From 65b1a7431680da730f24316c92e125bef6298462 Mon Sep 17 00:00:00 2001
From: "xiangren.yuan" <xiangren.yuan@ingenic.com>
Date: Mon, 5 Dec 2022 12:25:10 +0800
Subject: [PATCH] add mips halley5 board kernel(small) patches

Signed-off-by: xiangren.yuan <xiangren.yuan@ingenic.com>
Change-Id: I1270075f176f55e942ef3b93585b1f31419fe1ad
---
 linux-5.10/halley5_patch/halley5.patch | 1179626 +++++++++++++++++++++
 linux-5.10/halley5_patch/hdf.patch     |     341 +
 2 files changed, 1179967 insertions(+)
 create mode 100644 linux-5.10/halley5_patch/halley5.patch
 create mode 100644 linux-5.10/halley5_patch/hdf.patch

diff --git a/linux-5.10/halley5_patch/halley5.patch b/linux-5.10/halley5_patch/halley5.patch
new file mode 100644
index 0000000..d69caee
--- /dev/null
+++ b/linux-5.10/halley5_patch/halley5.patch
@@ -0,0 +1,1179626 @@
+From c861003ecee3406e2fd2aec131102b2fcbc70991 Mon Sep 17 00:00:00 2001
+From: "xiangren.yuan" <xiangren.yuan@ingenic.com>
+Date: Sat, 26 Nov 2022 12:37:47 +0800
+Subject: [PATCH] halley5
+
+---
+ Kconfig                                       |     2 +
+ Makefile                                      |     4 +-
+ arch/mips/Kbuild.platforms                    |     2 +
+ arch/mips/Kconfig                             |    63 +-
+ arch/mips/boot/dts/Makefile                   |     2 +
+ arch/mips/configs/halley5_small_defconfig     |  4478 +++
+ arch/mips/generic/board-ingenic.c             |     3 +
+ arch/mips/include/asm/bootinfo.h              |     1 +
+ arch/mips/include/asm/cpu-features.h          |    12 +
+ arch/mips/include/asm/cpu-type.h              |     1 +
+ arch/mips/include/asm/cpu.h                   |    17 +-
+ arch/mips/include/asm/mipsregs.h              |    11 +-
+ arch/mips/include/asm/msa.h                   |     4 +
+ arch/mips/include/asm/pgtable-bits.h          |    15 +
+ arch/mips/include/asm/processor.h             |    56 +-
+ arch/mips/include/asm/stackframe.h            |     2 +-
+ arch/mips/include/asm/switch_to.h             |    19 +
+ arch/mips/kernel/cpu-probe.c                  |    19 +-
+ arch/mips/kernel/genex.S                      |     1 +
+ arch/mips/kernel/idle.c                       |    18 +-
+ arch/mips/kernel/setup.c                      |     2 +-
+ arch/mips/kernel/smp.c                        |     1 +
+ arch/mips/kernel/traps.c                      |    56 +
+ arch/mips/mm/c-r4k.c                          |    33 +-
+ arch/mips/mm/dma-noncoherent.c                |     2 +
+ arch/mips/mm/sc-mips.c                        |     2 +-
+ arch/mips/mm/tlb-r4k.c                        |     7 +-
+ arch/mips/mm/tlbex.c                          |     1 +
+ arch/mips/xburst/Kconfig                      |    69 +
+ arch/mips/xburst/Makefile                     |     4 +
+ arch/mips/xburst/Platform                     |     7 +
+ arch/mips/xburst/common/Makefile              |     5 +
+ .../mips/xburst/common/include/ingenic_proc.h |    18 +
+ arch/mips/xburst/common/include/jz_notifier.h |    45 +
+ arch/mips/xburst/common/include/mxu.h         |    66 +
+ arch/mips/xburst/common/include/mxu_media.h   |  1832 ++
+ arch/mips/xburst/common/include/mxuv3.h       |    47 +
+ arch/mips/xburst/common/initrd-check.c        |    49 +
+ arch/mips/xburst/common/jz_notifier.c         |    83 +
+ arch/mips/xburst/common/mxu-xburst.c          |    85 +
+ arch/mips/xburst/common/proc.c                |    92 +
+ arch/mips/xburst/common/prom.c                |    63 +
+ arch/mips/xburst/common/sc-xburst.c           |   238 +
+ arch/mips/xburst/debug/Makefile               |     1 +
+ arch/mips/xburst/debug/trace-exit.c           |    31 +
+ arch/mips/xburst/soc-x1000/Kconfig.DT         |     9 +
+ arch/mips/xburst/soc-x1000/Makefile           |     5 +
+ arch/mips/xburst/soc-x1000/early_printk.c     |    76 +
+ .../soc-x1000/include/cpu-feature-overrides.h |    60 +
+ arch/mips/xburst/soc-x1000/include/irq.h      |    30 +
+ arch/mips/xburst/soc-x1000/include/soc/base.h |    90 +
+ .../mips/xburst/soc-x1000/include/soc/cache.h |   116 +
+ arch/mips/xburst/soc-x1000/include/soc/cpm.h  |   159 +
+ arch/mips/xburst/soc-x1000/include/soc/ost.h  |    41 +
+ arch/mips/xburst/soc-x1000/include/soc/sfc.h  |   152 +
+ .../soc-x1000/include/soc/tcsm_layout.h       |    53 +
+ arch/mips/xburst/soc-x1000/include/soc/tcu.h  |    37 +
+ arch/mips/xburst/soc-x1000/include/war.h      |    27 +
+ arch/mips/xburst/soc-x1000/pm.c               |   221 +
+ .../mips/xburst/soc-x1000/regs_save_restore.S |   174 +
+ arch/mips/xburst/soc-x1000/setup.c            |    80 +
+ arch/mips/xburst/soc-x1000/socid.c            |   110 +
+ arch/mips/xburst/soc-x1600/Kconfig.DT         |    19 +
+ arch/mips/xburst/soc-x1600/Makefile           |     6 +
+ arch/mips/xburst/soc-x1600/early_printk.c     |    99 +
+ arch/mips/xburst/soc-x1600/gpio.c             |   130 +
+ .../soc-x1600/include/cpu-feature-overrides.h |    61 +
+ arch/mips/xburst/soc-x1600/include/irq.h      |    35 +
+ arch/mips/xburst/soc-x1600/include/libdmmu.h  |    30 +
+ arch/mips/xburst/soc-x1600/include/soc/base.h |    66 +
+ .../mips/xburst/soc-x1600/include/soc/cache.h |    95 +
+ arch/mips/xburst/soc-x1600/include/soc/cpm.h  |   135 +
+ arch/mips/xburst/soc-x1600/include/soc/ddr.h  |   295 +
+ .../mips/xburst/soc-x1600/include/soc/efuse.h |   192 +
+ arch/mips/xburst/soc-x1600/include/soc/gpio.h |    44 +
+ arch/mips/xburst/soc-x1600/include/soc/ost.h  |    41 +
+ arch/mips/xburst/soc-x1600/include/soc/sfc.h  |   207 +
+ .../soc-x1600/include/soc/tcsm_layout.h       |    53 +
+ arch/mips/xburst/soc-x1600/include/soc/tcu.h  |    84 +
+ arch/mips/xburst/soc-x1600/include/war.h      |    27 +
+ arch/mips/xburst/soc-x1600/libdmmu.c          |  1087 +
+ arch/mips/xburst/soc-x1600/pm.c               |   762 +
+ arch/mips/xburst/soc-x1600/pm.h               |   136 +
+ .../mips/xburst/soc-x1600/regs_save_restore.S |   190 +
+ .../xburst/soc-x1600/regs_save_restore.py     |   123 +
+ arch/mips/xburst/soc-x1600/setup.c            |    93 +
+ arch/mips/xburst2/Kconfig                     |   105 +
+ arch/mips/xburst2/Makefile                    |     7 +
+ arch/mips/xburst2/Platform                    |     7 +
+ arch/mips/xburst2/common/Makefile             |    11 +
+ .../mips/xburst2/common/cpu_ddr_test/Makefile |    11 +
+ .../common/cpu_ddr_test/cpu_ccu_test.c        |    70 +
+ .../common/cpu_ddr_test/cpu_dma_test.c        |   269 +
+ .../common/cpu_ddr_test/cpu_spinlock_test.c   |    75 +
+ .../xburst2/common/cpu_ddr_test/cpu_tcsm.h    |    16 +
+ .../common/cpu_ddr_test/cpu_watch_test.c      |   200 +
+ .../cpu_ddr_test/ddr_bandwidth_monitor.c      |   461 +
+ .../common/cpu_ddr_test/ddr_change_freq.c     |   521 +
+ .../xburst2/common/cpu_ddr_test/l2c_test.c    |   527 +
+ .../common/cpu_ddr_test/multithread_test.c    |   258 +
+ .../common/cpu_ddr_test/multithread_test.h    |     9 +
+ .../common/cpu_ddr_test/raw_dma_test.c        |   273 +
+ arch/mips/xburst2/common/get-cpu-features.c   |    98 +
+ arch/mips/xburst2/common/initrd-check.c       |    58 +
+ arch/mips/xburst2/common/mxuv3.c              |   697 +
+ arch/mips/xburst2/common/proc.c               |    92 +
+ arch/mips/xburst2/core/Makefile               |     4 +
+ arch/mips/xburst2/core/include/ccu.h          |    42 +
+ arch/mips/xburst2/core/include/core_base.h    |     6 +
+ arch/mips/xburst2/core/include/ingenic_proc.h |    18 +
+ arch/mips/xburst2/core/include/irq_cpu.h      |     6 +
+ arch/mips/xburst2/core/include/mxu.h          |    59 +
+ arch/mips/xburst2/core/include/mxuv3.h        |    47 +
+ arch/mips/xburst2/core/prom.c                 |    79 +
+ arch/mips/xburst2/core/sc.c                   |   199 +
+ arch/mips/xburst2/core/smp.c                  |   505 +
+ arch/mips/xburst2/soc-m300/Kconfig.DT         |    11 +
+ arch/mips/xburst2/soc-m300/Makefile           |    12 +
+ .../soc-m300/include/cpu-feature-overrides.h  |    66 +
+ arch/mips/xburst2/soc-m300/include/irq.h      |    39 +
+ arch/mips/xburst2/soc-m300/include/libdmmu.h  |    30 +
+ arch/mips/xburst2/soc-m300/include/soc/base.h |    77 +
+ .../mips/xburst2/soc-m300/include/soc/cache.h |    28 +
+ arch/mips/xburst2/soc-m300/include/soc/cpm.h  |   136 +
+ arch/mips/xburst2/soc-m300/include/soc/ddr.h  |   293 +
+ .../mips/xburst2/soc-m300/include/soc/extal.h |    12 +
+ arch/mips/xburst2/soc-m300/include/soc/rtc.h  |    96 +
+ arch/mips/xburst2/soc-m300/include/soc/sfc.h  |   211 +
+ .../soc-m300/include/soc/tcsm_layout.h        |    53 +
+ arch/mips/xburst2/soc-m300/include/war.h      |    27 +
+ arch/mips/xburst2/soc-m300/libdmmu.c          |  1087 +
+ arch/mips/xburst2/soc-m300/pm.c               |   252 +
+ arch/mips/xburst2/soc-m300/pm.h               |   175 +
+ arch/mips/xburst2/soc-m300/pm_fastboot.c      |   503 +
+ arch/mips/xburst2/soc-m300/pm_fastboot.h      |   172 +
+ arch/mips/xburst2/soc-m300/pm_sleep.c         |   357 +
+ arch/mips/xburst2/soc-m300/pm_sleep.h         |    16 +
+ .../mips/xburst2/soc-m300/regs_save_restore.S |   190 +
+ .../xburst2/soc-m300/regs_save_restore.py     |   124 +
+ arch/mips/xburst2/soc-m300/reset.c            |   327 +
+ arch/mips/xburst2/soc-m300/serial.c           |    91 +
+ arch/mips/xburst2/soc-m300/setup.c            |    84 +
+ .../xburst2/soc-m300/sleep_firmware/Makefile  |    42 +
+ .../xburst2/soc-m300/sleep_firmware/Readme    |    14 +
+ .../soc-m300/sleep_firmware/include/base.h    |    91 +
+ .../soc-m300/sleep_firmware/include/cpm.h     |   230 +
+ .../soc-m300/sleep_firmware/include/ddr.h     |   289 +
+ .../soc-m300/sleep_firmware/include/gpio.h    |   267 +
+ .../sleep_firmware/include/pm_fastboot.h      |   187 +
+ .../soc-m300/sleep_firmware/include/uart.h    |   113 +
+ .../soc-m300/sleep_firmware/mkmodule.sh       |     7 +
+ .../sleep_firmware/src/fastboot_resume.c      |   314 +
+ .../soc-m300/sleep_firmware/src/uart.c        |    97 +
+ .../xburst2/soc-m300/sleep_firmware/target.ld |    37 +
+ arch/mips/xburst2/soc-x2000/Kconfig.DT        |    20 +
+ arch/mips/xburst2/soc-x2000/Makefile          |    12 +
+ arch/mips/xburst2/soc-x2000/gpio.c            |   123 +
+ .../soc-x2000/include/cpu-feature-overrides.h |    66 +
+ arch/mips/xburst2/soc-x2000/include/irq.h     |    39 +
+ arch/mips/xburst2/soc-x2000/include/libdmmu.h |    30 +
+ .../mips/xburst2/soc-x2000/include/soc/base.h |    77 +
+ .../xburst2/soc-x2000/include/soc/cache.h     |    73 +
+ arch/mips/xburst2/soc-x2000/include/soc/cpm.h |   136 +
+ arch/mips/xburst2/soc-x2000/include/soc/ddr.h |   293 +
+ .../xburst2/soc-x2000/include/soc/efuse.h     |   365 +
+ .../xburst2/soc-x2000/include/soc/extal.h     |    12 +
+ .../mips/xburst2/soc-x2000/include/soc/gpio.h |    42 +
+ arch/mips/xburst2/soc-x2000/include/soc/rtc.h |    96 +
+ arch/mips/xburst2/soc-x2000/include/soc/sfc.h |   211 +
+ .../soc-x2000/include/soc/tcsm_layout.h       |    53 +
+ arch/mips/xburst2/soc-x2000/include/war.h     |    27 +
+ arch/mips/xburst2/soc-x2000/libdmmu.c         |  1087 +
+ arch/mips/xburst2/soc-x2000/pm.c              |   539 +
+ arch/mips/xburst2/soc-x2000/pm.h              |   169 +
+ arch/mips/xburst2/soc-x2000/pm_fastboot.c     |   667 +
+ arch/mips/xburst2/soc-x2000/pm_fastboot.h     |   106 +
+ .../xburst2/soc-x2000/regs_save_restore.S     |   190 +
+ .../xburst2/soc-x2000/regs_save_restore.py    |   124 +
+ arch/mips/xburst2/soc-x2000/reset.c           |   327 +
+ arch/mips/xburst2/soc-x2000/serial.c          |    91 +
+ arch/mips/xburst2/soc-x2000/setup.c           |    84 +
+ .../xburst2/soc-x2000/sleep_firmware/Makefile |    42 +
+ .../xburst2/soc-x2000/sleep_firmware/Readme   |    14 +
+ .../soc-x2000/sleep_firmware/include/base.h   |    91 +
+ .../soc-x2000/sleep_firmware/include/cpm.h    |   230 +
+ .../soc-x2000/sleep_firmware/include/ddr.h    |   289 +
+ .../soc-x2000/sleep_firmware/include/gpio.h   |   267 +
+ .../sleep_firmware/include/pm_fastboot.h      |   106 +
+ .../soc-x2000/sleep_firmware/include/uart.h   |   113 +
+ .../soc-x2000/sleep_firmware/mkmodule.sh      |     7 +
+ .../sleep_firmware/src/fastboot_resume.c      |   328 +
+ .../soc-x2000/sleep_firmware/src/uart.c       |    97 +
+ .../soc-x2000/sleep_firmware/target.ld        |    37 +
+ .../xburst2/soc-x2000/sleep_firmware/tmp.map  |    75 +
+ arch/mips/xburst2/soc-x2500/Kconfig.DT        |    15 +
+ arch/mips/xburst2/soc-x2500/Makefile          |     8 +
+ arch/mips/xburst2/soc-x2500/gpio.c            |   123 +
+ .../soc-x2500/include/cpu-feature-overrides.h |    67 +
+ arch/mips/xburst2/soc-x2500/include/irq.h     |    40 +
+ arch/mips/xburst2/soc-x2500/include/libdmmu.h |    30 +
+ .../mips/xburst2/soc-x2500/include/soc/base.h |    97 +
+ .../xburst2/soc-x2500/include/soc/cache.h     |    73 +
+ arch/mips/xburst2/soc-x2500/include/soc/cpm.h |   143 +
+ arch/mips/xburst2/soc-x2500/include/soc/ddr.h |   293 +
+ .../xburst2/soc-x2500/include/soc/extal.h     |     8 +
+ .../mips/xburst2/soc-x2500/include/soc/gpio.h |    40 +
+ arch/mips/xburst2/soc-x2500/include/soc/mmc.h |     5 +
+ .../mips/xburst2/soc-x2500/include/soc/pdma.h |    49 +
+ arch/mips/xburst2/soc-x2500/include/soc/rtc.h |    96 +
+ arch/mips/xburst2/soc-x2500/include/soc/sfc.h |   211 +
+ .../soc-x2500/include/soc/tcsm_layout.h       |    53 +
+ arch/mips/xburst2/soc-x2500/include/war.h     |    27 +
+ arch/mips/xburst2/soc-x2500/libdmmu.c         |  1087 +
+ arch/mips/xburst2/soc-x2500/pm.c              |   608 +
+ arch/mips/xburst2/soc-x2500/pm.h              |   136 +
+ arch/mips/xburst2/soc-x2500/pm_fastboot.c     |   667 +
+ arch/mips/xburst2/soc-x2500/pm_fastboot.h     |   106 +
+ .../xburst2/soc-x2500/regs_save_restore.S     |   190 +
+ .../xburst2/soc-x2500/regs_save_restore.py    |   124 +
+ arch/mips/xburst2/soc-x2500/reset.c           |   331 +
+ arch/mips/xburst2/soc-x2500/serial.c          |    91 +
+ arch/mips/xburst2/soc-x2500/setup.c           |    84 +
+ block/partitions/efi.c                        |     2 +
+ drivers/char/Makefile                         |     2 +
+ drivers/char/jz_spinand_firmware.c            |   486 +
+ drivers/char/jz_spinand_firmware.h            |    63 +
+ drivers/media/platform/v4l2loopback/Makefile  |     1 +
+ .../platform/v4l2loopback/v4l2loopback.c      |  3016 +++
+ .../platform/v4l2loopback/v4l2loopback.h      |    92 +
+ .../v4l2loopback/v4l2loopback_formats.h       |   427 +
+ drivers/mmc/core/block.c                      |    29 +-
+ drivers/mmc/core/core.c                       |     5 +-
+ drivers/mmc/core/host.c                       |    56 +-
+ drivers/mmc/core/sdio.c                       |    36 +
+ drivers/mmc/host/sdhci.c                      |    15 +-
+ drivers/mmc/host/sdhci.h                      |     3 +-
+ drivers/mtd/Kconfig                           |    15 +
+ drivers/mtd/Makefile                          |     1 +
+ drivers/mtd/mtdblock_bbt_ro.c                 |   184 +
+ drivers/usb/common/common.c                   |   122 +-
+ drivers/usb/common/debug.c                    |    22 +-
+ drivers/usb/common/usb-conn-gpio.c            |     6 +-
+ drivers/usb/core/devices.c                    |    21 +-
+ drivers/usb/core/endpoint.c                   |    35 +-
+ drivers/usb/core/hcd.c                        |    45 +-
+ drivers/usb/core/hub.c                        |    37 +-
+ drivers/usb/core/sysfs.c                      |    29 +-
+ drivers/usb/core/urb.c                        |     9 +
+ drivers/usb/core/usb.c                        |     8 +-
+ drivers/usb/dwc2/Kconfig                      |    20 +
+ drivers/usb/dwc2/core.c                       |   214 +-
+ drivers/usb/dwc2/core.h                       |   102 +-
+ drivers/usb/dwc2/core_intr.c                  |   136 +-
+ drivers/usb/dwc2/debugfs.c                    |     5 +-
+ drivers/usb/dwc2/drd.c                        |   118 +-
+ drivers/usb/dwc2/gadget.c                     |   511 +-
+ drivers/usb/dwc2/hcd.c                        |   636 +-
+ drivers/usb/dwc2/hcd_queue.c                  |     2 +-
+ drivers/usb/dwc2/hw.h                         |    33 +-
+ drivers/usb/dwc2/params.c                     |   257 +-
+ drivers/usb/dwc2/pci.c                        |    18 -
+ drivers/usb/dwc2/platform.c                   |   195 +-
+ drivers/usb/gadget/Kconfig                    |    31 +
+ drivers/usb/gadget/composite.c                |   100 +-
+ drivers/usb/gadget/configfs.c                 |   157 +
+ drivers/usb/gadget/function/Makefile          |     4 +
+ drivers/usb/gadget/function/f_fs.c            |     9 +-
+ drivers/usb/gadget/function/f_hid.c           |   224 +-
+ drivers/usb/gadget/function/f_mass_storage.c  |    34 +-
+ drivers/usb/gadget/function/f_midi.c          |    12 +-
+ drivers/usb/gadget/function/f_mtp.c           |  1536 ++
+ drivers/usb/gadget/function/f_mtp.h           |    18 +
+ drivers/usb/gadget/function/f_ncm.c           |    50 +-
+ drivers/usb/gadget/function/f_printer.c       |     5 +-
+ drivers/usb/gadget/function/f_ptp.c           |    38 +
+ drivers/usb/gadget/function/f_uac1.c          |   893 +-
+ drivers/usb/gadget/function/f_uac2.c          |  1039 +-
+ drivers/usb/gadget/function/f_uvc.c           |     2 +-
+ drivers/usb/gadget/function/rndis.c           |    47 +-
+ drivers/usb/gadget/function/u_audio.c         |   717 +-
+ drivers/usb/gadget/function/u_audio.h         |    34 +
+ drivers/usb/gadget/function/u_ether.c         |    46 +-
+ drivers/usb/gadget/function/u_ether.h         |    12 +
+ .../usb/gadget/function/u_ether_configfs.h    |    15 +-
+ drivers/usb/gadget/function/u_hid.h           |     5 +-
+ drivers/usb/gadget/function/u_midi.h          |     4 +-
+ drivers/usb/gadget/function/u_serial.c        |    42 +-
+ drivers/usb/gadget/function/u_uac1.h          |    22 +-
+ drivers/usb/gadget/function/u_uac2.h          |    29 +-
+ drivers/usb/gadget/function/uvc.h             |    17 +-
+ drivers/usb/gadget/function/uvc_configfs.c    |     7 +-
+ drivers/usb/gadget/function/uvc_queue.c       |    24 +-
+ drivers/usb/gadget/function/uvc_queue.h       |     8 +-
+ drivers/usb/gadget/function/uvc_v4l2.c        |    51 +-
+ drivers/usb/gadget/function/uvc_video.c       |   156 +-
+ drivers/usb/gadget/function/uvc_video.h       |     2 +
+ drivers/usb/gadget/legacy/Kconfig             |    14 +-
+ drivers/usb/gadget/legacy/dbgp.c              |    15 +-
+ drivers/usb/gadget/legacy/hid.c               |     4 +-
+ drivers/usb/gadget/legacy/inode.c             |    29 +-
+ drivers/usb/gadget/legacy/mass_storage.c      |     4 +-
+ drivers/usb/gadget/legacy/multi.c             |    14 +-
+ drivers/usb/gadget/legacy/printer.c           |     1 +
+ drivers/usb/gadget/legacy/raw_gadget.c        |     3 +-
+ drivers/usb/gadget/legacy/webcam.c            |     2 +-
+ drivers/usb/gadget/udc/Kconfig                |     1 -
+ drivers/usb/gadget/udc/amd5536udc_pci.c       |    10 +-
+ drivers/usb/gadget/udc/aspeed-vhub/core.c     |     3 +-
+ drivers/usb/gadget/udc/aspeed-vhub/epn.c      |     2 +-
+ drivers/usb/gadget/udc/at91_udc.c             |     4 +-
+ drivers/usb/gadget/udc/bdc/bdc_core.c         |    30 +-
+ drivers/usb/gadget/udc/core.c                 |   107 +-
+ drivers/usb/gadget/udc/dummy_hcd.c            |    14 +-
+ drivers/usb/gadget/udc/fotg210-udc.c          |    26 +-
+ drivers/usb/gadget/udc/max3420_udc.c          |    14 +-
+ drivers/usb/gadget/udc/mv_u3d_core.c          |    19 +-
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+ drivers/usb/gadget/udc/tegra-xudc.c           |     7 +-
+ drivers/usb/gadget/udc/udc-xilinx.c           |     6 -
+ drivers/usb/phy/Kconfig                       |    20 +
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+ drivers/usb/phy/phy-fsl-usb.c                 |     2 -
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+ drivers/usb/phy/phy-ingenic-x1000.c           |    66 +
+ drivers/usb/phy/phy-ingenic-x1600.c           |   139 +
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+ drivers/usb/phy/phy-ingenic.c                 |   639 +
+ drivers/usb/phy/phy-ingenic.h                 |   111 +
+ drivers/usb/phy/phy-tahvo.c                   |     4 +-
+ drivers/usb/phy/phy-twl6030-usb.c             |     5 -
+ drivers/usb/phy/phy.c                         |    61 +-
+ drivers/usb/roles/class.c                     |     9 +
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+ include/dt-bindings/clock/ingenic-tcu.h       |    29 +
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+ include/dt-bindings/clock/ingenic-x2000.h     |   201 +
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+ include/dt-bindings/dma/ingenic-pdma.h        |    89 +
+ include/dt-bindings/gpio/ingenic-gpio.h       |     8 +
+ .../interrupt-controller/m300-irq.h           |    72 +
+ .../interrupt-controller/mips-irq.h           |    16 +
+ .../interrupt-controller/x1000-irq.h          |    72 +
+ .../interrupt-controller/x1600-irq.h          |    72 +
+ .../interrupt-controller/x2000-irq.h          |    72 +
+ .../interrupt-controller/x2500-irq.h          |    75 +
+ include/dt-bindings/net/ingenic_gmac.h        |     9 +
+ include/dt-bindings/pinctrl/ingenic-pinctrl.h |    79 +
+ include/dt-bindings/power/axp216-power.h      |    21 +
+ include/dt-bindings/sound/ingenic-baic.h      |    34 +
+ include/linux/dma-map-ops.h                   |     8 +-
+ include/linux/dmaengine.h                     |     8 +
+ include/linux/mfd/ingenic-tcu_v1.h            |   202 +
+ include/linux/mfd/ingenic-tcu_v2.h            |   383 +
+ include/linux/mfd/ingenic_adc.h               |   317 +
+ include/linux/usb.h                           |    13 +-
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+ include/linux/usb/ch9.h                       |    62 +-
+ include/linux/usb/composite.h                 |     4 +-
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+ include/linux/usb/gadget.h                    |    20 +-
+ include/linux/usb/hcd.h                       |    21 +-
+ include/linux/usb/otg-fsm.h                   |     1 -
+ include/linux/usb/otg.h                       |     3 +-
+ include/linux/usb/pd.h                        |     2 +-
+ include/linux/usb/phy.h                       |    11 +
+ include/linux/usb/quirks.h                    |     2 +-
+ include/linux/usb/role.h                      |     6 +
+ include/linux/usb/usbnet.h                    |     2 -
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+ include/media/v4l2-ioctl.h                    |     6 +
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+ include/uapi/linux/tty_flags.h                |     4 +-
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+ include/uapi/linux/usb/f_mtp.h                |    61 +
+ include/uapi/linux/videodev2.h                |     1 +
+ include/video/ingenic_logo.h                  |    15 +
+ kernel/dma/coherent.c                         |    64 +-
+ kernel/dma/mapping.c                          |    12 +-
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+ module_drivers/README.zh                      |    27 +
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+ module_drivers/drivers/char/ingenic_cdbus.c   |   733 +
+ module_drivers/drivers/clk/Makefile           |     1 +
+ module_drivers/drivers/clk/ingenic-v2/Kconfig |    49 +
+ .../drivers/clk/ingenic-v2/Makefile           |    35 +
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+ .../drivers/clk/ingenic-v2/clk-bus.h          |    24 +
+ .../drivers/clk/ingenic-v2/clk-div.c          |   258 +
+ .../drivers/clk/ingenic-v2/clk-div.h          |    18 +
+ .../drivers/clk/ingenic-v2/clk-m300.c         |   395 +
+ .../drivers/clk/ingenic-v2/clk-pll-v1.c       |   185 +
+ .../drivers/clk/ingenic-v2/clk-pll-v1.h       |    53 +
+ .../drivers/clk/ingenic-v2/clk-pll-v2.c       |   181 +
+ .../drivers/clk/ingenic-v2/clk-pll-v2.h       |    53 +
+ .../drivers/clk/ingenic-v2/clk-pll.c          |   185 +
+ .../drivers/clk/ingenic-v2/clk-pll.h          |    11 +
+ .../drivers/clk/ingenic-v2/clk-x1600.c        |   306 +
+ .../drivers/clk/ingenic-v2/clk-x2000.c        |   361 +
+ .../drivers/clk/ingenic-v2/clk-x2500.c        |   296 +
+ module_drivers/drivers/clk/ingenic-v2/clk.c   |   518 +
+ module_drivers/drivers/clk/ingenic-v2/clk.h   |   594 +
+ .../drivers/clk/ingenic-v2/power-gate.c       |   197 +
+ .../drivers/clk/ingenic-v2/power-gate.h       |    14 +
+ module_drivers/drivers/clocksource/Kconfig    |    16 +
+ module_drivers/drivers/clocksource/Makefile   |     2 +
+ .../drivers/clocksource/ingenic_core_ost.c    |   569 +
+ .../drivers/clocksource/ingenic_sysost.c      |   316 +
+ module_drivers/drivers/crypto/Kconfig         |    23 +
+ module_drivers/drivers/crypto/Makefile        |     2 +
+ module_drivers/drivers/crypto/ingenic-aes.c   |   923 +
+ module_drivers/drivers/crypto/ingenic-aes.h   |   113 +
+ module_drivers/drivers/crypto/ingenic-hash.c  |  1111 +
+ module_drivers/drivers/crypto/ingenic-hash.h  |   119 +
+ module_drivers/drivers/dma/Makefile           |     1 +
+ module_drivers/drivers/dma/ingenic/Kconfig    |    25 +
+ module_drivers/drivers/dma/ingenic/Makefile   |     3 +
+ .../drivers/dma/ingenic/ingenic_dma.c         |  1179 +
+ .../drivers/dma/ingenic/ingenic_dma.h         |   253 +
+ module_drivers/drivers/i2c/Makefile           |     1 +
+ module_drivers/drivers/i2c/busses/Kconfig     |    27 +
+ module_drivers/drivers/i2c/busses/Makefile    |     1 +
+ .../drivers/i2c/busses/i2c-ingenic.c          |  1146 +
+ module_drivers/drivers/input/Makefile         |     1 +
+ .../drivers/input/touchscreen/Kconfig         |    17 +
+ .../drivers/input/touchscreen/Makefile        |    11 +
+ .../input/touchscreen/focaltech_touch/Kconfig |    16 +
+ .../touchscreen/focaltech_touch/Makefile      |    13 +
+ .../focaltech_touch/focaltech_common.h        |   166 +
+ .../focaltech_touch/focaltech_config.h        |   165 +
+ .../focaltech_touch/focaltech_core.c          |  1723 ++
+ .../focaltech_touch/focaltech_core.h          |   260 +
+ .../focaltech_touch/focaltech_esdcheck.c      |   464 +
+ .../focaltech_touch/focaltech_ex_fun.c        |  1187 +
+ .../focaltech_touch/focaltech_ex_mode.c       |   307 +
+ .../focaltech_touch/focaltech_flash.c         |  2011 ++
+ .../focaltech_touch/focaltech_flash.h         |   205 +
+ .../focaltech_touch/focaltech_flash/Makefile  |     1 +
+ .../focaltech_upgrade_ft7511.c                |   154 +
+ .../focaltech_touch/focaltech_gesture.c       |   460 +
+ .../focaltech_touch/focaltech_i2c.c           |   193 +
+ .../focaltech_point_report_check.c            |   135 +
+ .../input/touchscreen/ft6236_touch/Kconfig    |    10 +
+ .../input/touchscreen/ft6236_touch/Makefile   |     6 +
+ .../touchscreen/ft6236_touch/ft6236_touch.c   |   592 +
+ .../touchscreen/ft6236_touch/ft6236_touch.h   |    52 +
+ .../input/touchscreen/gt9xx_touch/Kconfig     |    16 +
+ .../input/touchscreen/gt9xx_touch/Makefile    |     6 +
+ .../input/touchscreen/gt9xx_touch/goodix.h    |    69 +
+ .../touchscreen/gt9xx_touch/goodix_tool.c     |   529 +
+ .../input/touchscreen/gt9xx_touch/gt9xx.c     |  2576 ++
+ .../input/touchscreen/gt9xx_touch/gt9xx.h     |   384 +
+ .../touchscreen/gt9xx_touch/gt9xx_firmware.h  |  2338 ++
+ .../touchscreen/gt9xx_touch/gt9xx_update.c    |  2092 ++
+ .../hyn_cst3xx_0729_update1ok.c               |  1602 ++
+ .../hyn_cst3xx_RS659_fw.h                     |  1553 ++
+ .../hyn_cst3xx_0729_update3_firmware.c        |  1626 ++
+ .../hyn_cst3xx_RS659_fw_0729_update2.h        |  1552 ++
+ .../hyn_cst3xx_RS659_fw_0729_update3.h        |  1552 ++
+ .../input/touchscreen/hyn_touch/Kconfig       |    16 +
+ .../input/touchscreen/hyn_touch/Makefile      |     4 +
+ .../cst3xx_MCU_driver-ori/cst3xx.c            |  1422 +
+ .../cst3xx_MCU_driver-ori/cst3xx.h            |    29 +
+ .../hyn_cst3xx_RS659_fw.h                     |  1553 ++
+ .../cst3xx_MCU_driver_0729_update1/cst3xx.h   |    29 +
+ .../cst3xx_MCU_driver_0729_update1/cst3xx_1.c |  1422 +
+ .../cst3xx_MCU_driver_0729_update1/cst3xx_2.c |  1422 +
+ .../hyn_cst3xx_RS659_fw.h                     |  1553 ++
+ .../cst3xx_MCU_driver_0729_update2/cst3xx.c   |  1437 +
+ .../cst3xx_MCU_driver_0729_update2/cst3xx.h   |    29 +
+ .../hyn_cst3xx_RS659_fw.h                     |  1552 ++
+ .../hyn_cst3xx_RS659_fw_0730_268_800.h        |  1552 ++
+ .../input/touchscreen/hyn_touch/Readme        |     6 +
+ .../input/touchscreen/hyn_touch/hyn_cst3xx.c  |  1645 ++
+ .../input/touchscreen/hyn_touch/hyn_cst3xx.h  |   136 +
+ .../hyn_touch/hyn_cst3xx_RS659_fw.h           |  1550 ++
+ .../input/touchscreen/hyn_touch/hyn_i2c.c     |    99 +
+ module_drivers/drivers/irqchip/Kconfig        |    20 +
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+ .../drivers/irqchip/irq-ingenic-chip.c        |   560 +
+ .../drivers/irqchip/irq-ingenic-cpu.c         |   128 +
+ module_drivers/drivers/irqchip/irq-ingenic.c  |   266 +
+ module_drivers/drivers/md_export/Makefile     |     1 +
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+ module_drivers/drivers/media/Makefile         |     3 +
+ module_drivers/drivers/media/i2c/Kconfig      |     4 +
+ module_drivers/drivers/media/i2c/Makefile     |     3 +
+ .../drivers/media/i2c/ingenic-cim/Kconfig     |    56 +
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+ .../drivers/media/i2c/ingenic-cim/ar0144.c    |   935 +
+ .../drivers/media/i2c/ingenic-cim/ov2735b.c   |   999 +
+ .../drivers/media/i2c/ingenic-cim/ov4689.c    |  3115 +++
+ .../drivers/media/i2c/ingenic-cim/ov5640.c    |  1925 ++
+ .../drivers/media/i2c/ingenic-cim/ov5645.c    |  1629 ++
+ .../i2c/ingenic-cim/ov9281-dvp-snapshot.c     |  1223 +
+ .../drivers/media/i2c/ingenic-cim/ov9281.c    |  1068 +
+ .../media/i2c/ingenic-cim/sc031gs-mipi.c      |   919 +
+ .../drivers/media/i2c/ingenic-cim/sc031gs.c   |   985 +
+ .../drivers/media/i2c/ingenic-isp-v2/Kconfig  |    49 +
+ .../drivers/media/i2c/ingenic-isp-v2/Makefile |    10 +
+ .../drivers/media/i2c/ingenic-isp-v2/gc2053.c |  1001 +
+ .../drivers/media/i2c/ingenic-isp-v2/gc2093.c |  1255 +
+ .../drivers/media/i2c/ingenic-isp-v2/gc2155.c |  1516 ++
+ .../drivers/media/i2c/ingenic-isp-v2/imx327.c |  1109 +
+ .../media/i2c/ingenic-isp-v2/ov2735a.c        |  1132 +
+ .../drivers/media/i2c/ingenic-isp-v2/ov4689.c |  1629 ++
+ .../drivers/media/i2c/ingenic-isp-v2/ov7251.c |  1534 ++
+ .../media/i2c/ingenic-isp-v2/sc230ai.c        |  1972 ++
+ .../drivers/media/i2c/ingenic-isp-v2/sc2310.c |  2461 ++
+ .../drivers/media/i2c/ingenic-isp/Kconfig     |    92 +
+ .../drivers/media/i2c/ingenic-isp/Makefile    |    17 +
+ .../drivers/media/i2c/ingenic-isp/ar0144.c    |   998 +
+ .../drivers/media/i2c/ingenic-isp/ar0234.c    |  1183 +
+ .../drivers/media/i2c/ingenic-isp/cisadc.c    |   602 +
+ .../drivers/media/i2c/ingenic-isp/gc1054.c    |  1606 ++
+ .../drivers/media/i2c/ingenic-isp/gc2093.c    |  1043 +
+ .../i2c/ingenic-isp/gm8914_gm8913_gc2093.c    |  1508 ++
+ .../drivers/media/i2c/ingenic-isp/hm2140.c    |  1091 +
+ .../drivers/media/i2c/ingenic-isp/imx335.c    |  1429 +
+ .../drivers/media/i2c/ingenic-isp/ov2735a.c   |  1157 +
+ .../drivers/media/i2c/ingenic-isp/ov2735b.c   |  1202 +
+ .../drivers/media/i2c/ingenic-isp/ov4689.c    |  3224 +++
+ .../drivers/media/i2c/ingenic-isp/ov6710.c    |  1549 ++
+ .../drivers/media/i2c/ingenic-isp/ov7251.c    |  1396 +
+ .../drivers/media/i2c/ingenic-isp/sc0132gs.c  |  1630 ++
+ .../drivers/media/i2c/ingenic-isp/sc031gs.c   |  2226 ++
+ .../drivers/media/i2c/ingenic-isp/sc2232h.c   |  1173 +
+ .../drivers/media/i2c/ingenic-isp/sc230ai.c   |  1653 ++
+ module_drivers/drivers/media/platform/Kconfig |    41 +
+ .../drivers/media/platform/Makefile           |     6 +
+ .../media/platform/ingenic-cim/Kconfig        |    82 +
+ .../media/platform/ingenic-cim/Makefile       |     2 +
+ .../platform/ingenic-cim/ingenic_camera.c     |  2566 ++
+ .../platform/ingenic-cim/ingenic_camera.h     |   581 +
+ .../media/platform/ingenic-cim/mipi_csi.c     |   222 +
+ .../media/platform/ingenic-cim/mipi_csi.h     |    98 +
+ .../media/platform/ingenic-i2d/Kconfig        |    16 +
+ .../media/platform/ingenic-i2d/Makefile       |     1 +
+ .../media/platform/ingenic-i2d/i2d_video.c    |   751 +
+ .../media/platform/ingenic-i2d/i2d_video.h    |    75 +
+ .../media/platform/ingenic-i2d/ingenic_i2d.c  |   252 +
+ .../media/platform/ingenic-i2d/ingenic_i2d.h  |   157 +
+ .../media/platform/ingenic-isp-v2/Kconfig     |    56 +
+ .../media/platform/ingenic-isp-v2/Makefile    |    20 +
+ .../media/platform/ingenic-isp-v2/csi-regs.h  |    69 +
+ .../media/platform/ingenic-isp-v2/csi.c       |   554 +
+ .../platform/ingenic-isp-v2/isp-core-tuning.c |   704 +
+ .../platform/ingenic-isp-v2/isp-core/Makefile |     1 +
+ .../isp-core/inc/system_sensor_drv.h          |    96 +
+ .../isp-core/inc/tiziano-core-ctrl.h          |   868 +
+ .../ingenic-isp-v2/isp-core/inc/tiziano-isp.h |   257 +
+ .../ingenic-isp-v2/isp-core/inc/tiziano_sys.h |    11 +
+ .../ingenic-isp-v2/isp-core/inc/txx-funcs.h   |   222 +
+ .../media/platform/ingenic-isp-v2/isp-drv.c   |   451 +
+ .../media/platform/ingenic-isp-v2/isp-drv.h   |   398 +
+ .../platform/ingenic-isp-v2/isp-regs-x2000.h  |  1453 +
+ .../media/platform/ingenic-isp-v2/isp-regs.h  |  4289 +++
+ .../platform/ingenic-isp-v2/isp-sensor.h      |    97 +
+ .../ingenic-isp-v2/isp-video-mplane.c         |   729 +
+ .../media/platform/ingenic-isp-v2/isp-video.c |   992 +
+ .../media/platform/ingenic-isp-v2/isp.c       |  1173 +
+ .../platform/ingenic-isp-v2/mscaler-bdev.c    |   255 +
+ .../platform/ingenic-isp-v2/mscaler-regs.h    |    80 +
+ .../media/platform/ingenic-isp-v2/mscaler.c   |  1411 +
+ .../media/platform/ingenic-isp-v2/sensor.c    |   463 +
+ .../platform/ingenic-isp-v2/tx-vic-regs.h     |   182 +
+ .../media/platform/ingenic-isp-v2/vic-regs.h  |   174 +
+ .../media/platform/ingenic-isp-v2/vic.c       |  1486 +
+ .../media/platform/ingenic-isp/Kconfig        |   113 +
+ .../media/platform/ingenic-isp/Makefile       |    20 +
+ .../media/platform/ingenic-isp/csi-regs.h     |    51 +
+ .../drivers/media/platform/ingenic-isp/csi.c  |   482 +
+ .../platform/ingenic-isp/isp-core-tuning.c    |  1130 +
+ .../platform/ingenic-isp/isp-core/Makefile    |     3 +
+ .../isp-core/inc/system_sensor_drv.h          |    85 +
+ .../ingenic-isp/isp-core/inc/tiziano_core.h   |  1223 +
+ .../isp-core/inc/tiziano_core_tuning.h        |   170 +
+ .../ingenic-isp/isp-core/inc/tiziano_isp.h    |   104 +
+ .../isp-core/inc/tiziano_netlink.h            |    12 +
+ .../ingenic-isp/isp-core/inc/tiziano_priv.h   |    47 +
+ .../ingenic-isp/isp-core/inc/tiziano_sys.h    |    10 +
+ .../ingenic-isp/isp-core/src/Makefile         |     2 +
+ .../ingenic-isp/isp-core/tiziano_netlink.c    |   125 +
+ .../ingenic-isp/isp-core/tiziano_priv.c       |    56 +
+ .../media/platform/ingenic-isp/isp-drv.c      |   451 +
+ .../media/platform/ingenic-isp/isp-drv.h      |   415 +
+ .../media/platform/ingenic-isp/isp-regs.h     |  1450 +
+ .../media/platform/ingenic-isp/isp-sensor.h   |    80 +
+ .../platform/ingenic-isp/isp-video-mplane.c   |   729 +
+ .../media/platform/ingenic-isp/isp-video.c    |   890 +
+ .../drivers/media/platform/ingenic-isp/isp.c  |   785 +
+ .../media/platform/ingenic-isp/mscaler-bdev.c |   255 +
+ .../media/platform/ingenic-isp/mscaler-regs.h |    82 +
+ .../media/platform/ingenic-isp/mscaler.c      |  1531 ++
+ .../media/platform/ingenic-isp/sensor.c       |   302 +
+ .../media/platform/ingenic-isp/vic-regs.h     |   157 +
+ .../drivers/media/platform/ingenic-isp/vic.c  |  1224 +
+ .../media/platform/ingenic-rotate/Kconfig     |     8 +
+ .../media/platform/ingenic-rotate/Makefile    |     2 +
+ .../media/platform/ingenic-rotate/rotate-hw.c |   317 +
+ .../platform/ingenic-rotate/rotate-regs.h     |   204 +
+ .../media/platform/ingenic-rotate/rotate.c    |   876 +
+ .../media/platform/ingenic-rotate/rotate.h    |   150 +
+ .../media/platform/ingenic-vcodec/Kconfig     |    16 +
+ .../media/platform/ingenic-vcodec/Makefile    |     2 +
+ .../platform/ingenic-vcodec/felix/Makefile    |    29 +
+ .../platform/ingenic-vcodec/felix/felix_drv.c |   658 +
+ .../platform/ingenic-vcodec/felix/felix_drv.h |   159 +
+ .../platform/ingenic-vcodec/felix/felix_ops.c |  1235 +
+ .../platform/ingenic-vcodec/felix/felix_ops.h |    15 +
+ .../ingenic-vcodec/felix/libh264/Makefile     |    25 +
+ .../felix/libh264/api/jzm_h264_dec.c          |  1123 +
+ .../felix/libh264/api/jzm_h264_dec.h          |   125 +
+ .../felix/libh264/api/jzm_vpu.h               |  2674 ++
+ .../felix/libh264/include/avassert.h          |    53 +
+ .../felix/libh264/include/avcodec.h           |   404 +
+ .../felix/libh264/include/bswap.h             |    54 +
+ .../felix/libh264/include/buffer.h            |    70 +
+ .../felix/libh264/include/bytestream.h        |   358 +
+ .../felix/libh264/include/common.h            |   476 +
+ .../felix/libh264/include/devmem.h            |    26 +
+ .../felix/libh264/include/error.h             |   108 +
+ .../felix/libh264/include/frame.h             |   308 +
+ .../felix/libh264/include/get_bits.h          |   810 +
+ .../felix/libh264/include/golomb.h            |   715 +
+ .../felix/libh264/include/h264.h              |   113 +
+ .../felix/libh264/include/h2645_parse.h       |    93 +
+ .../felix/libh264/include/h264_parse.h        |    70 +
+ .../felix/libh264/include/h264_ps.h           |   184 +
+ .../felix/libh264/include/h264_sei.h          |   189 +
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+ .../felix/libh264/include/intreadwrite.h      |   509 +
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+ .../felix/libh264/include/mathops.h           |    63 +
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+ .../felix/libh264/include/put_bits.h          |   337 +
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+ .../felix/libh264/src/h2645_parse.c           |   401 +
+ .../felix/libh264/src/h264_direct.c           |   146 +
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+ .../felix/libh264/src/h264_sei.c              |   508 +
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+ .../felix/libh264/src/h264dec.c               |   613 +
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+ .../ingenic-vcodec/helix/api/helix_jpeg_enc.c |   241 +
+ .../ingenic-vcodec/helix/api/helix_jpeg_enc.h |    81 +
+ .../ingenic-vcodec/helix/api/helix_x264_enc.c |  1647 ++
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+ .../v4l2-core/videobuf2-dma-contig-ingenic.c  |   893 +
+ module_drivers/drivers/mfd/Kconfig            |    75 +
+ module_drivers/drivers/mfd/Makefile           |     5 +
+ module_drivers/drivers/mfd/ingenic-tcu.c      |   908 +
+ module_drivers/drivers/mfd/ingenic-tcu_v1.c   |   942 +
+ module_drivers/drivers/mfd/ingenic_adc_aux.c  |   362 +
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+ module_drivers/drivers/mfd/ricoh619-irq.c     |   565 +
+ module_drivers/drivers/mfd/ricoh619.c         |   727 +
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+ .../drivers/misc/bt_power_bluesleep.c         |   311 +
+ module_drivers/drivers/misc/hamming.c         |   374 +
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+ module_drivers/drivers/misc/ingenic_rsa.c     |   487 +
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+ module_drivers/drivers/mmc/host/Makefile      |     5 +
+ module_drivers/drivers/mmc/host/ingenic_mmc.c |  1815 ++
+ module_drivers/drivers/mmc/host/ingenic_mmc.h |   158 +
+ .../drivers/mmc/host/ingenic_mmc_reg.h        |   232 +
+ .../drivers/mmc/host/ingenic_sdio.c           |   275 +
+ .../drivers/mmc/host/sdhci-ingenic.c          |   741 +
+ .../drivers/mmc/host/sdhci-ingenic.h          |    97 +
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+ module_drivers/drivers/mtd/devices/Kconfig    |    90 +
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+ .../devices/ingenic_sfc_v2/ingenic_sfc_nor.c  |  1000 +
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+ .../ingenic_sfc_v2/nand_device/gd_nand.c      |   435 +
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+ .../ingenic_sfc_v2/nand_device/xcsp_nand.c    |   197 +
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+ .../nand_device/xtx_mid2c_nand.c              |   124 +
+ .../ingenic_sfc_v2/nand_device/xtx_nand.c     |   161 +
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+ .../drivers/mtd/devices/ingenic_sfc_v2/sfc.h  |   116 +
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+ .../mtd/devices/ingenic_sfc_v2/spinand.h      |   187 +
+ .../mtd/devices/ingenic_sfc_v2/spinand_cmd.h  |    30 +
+ .../mtd/devices/ingenic_sfc_v2/spinor.h       |   205 +
+ .../mtd/devices/ingenic_sfc_v2/spinor_cmd.h   |    84 +
+ module_drivers/drivers/net/Makefile           |     3 +
+ module_drivers/drivers/net/ethernet/Makefile  |     1 +
+ .../drivers/net/ethernet/ingenic/Kconfig      |    46 +
+ .../drivers/net/ethernet/ingenic/Makefile     |    31 +
+ .../drivers/net/ethernet/ingenic/ethtool.c    |   284 +
+ .../net/ethernet/ingenic/ingenic_mac.c        |  3424 +++
+ .../net/ethernet/ingenic/ingenic_mac.h        |   194 +
+ .../drivers/net/ethernet/ingenic/readme       |    26 +
+ .../net/ethernet/ingenic/synopGMAC_Dev.c      |  3839 +++
+ .../net/ethernet/ingenic/synopGMAC_Dev.h      |  2011 ++
+ .../net/ethernet/ingenic/synopGMAC_plat.c     |    94 +
+ .../net/ethernet/ingenic/synopGMAC_plat.h     |   211 +
+ module_drivers/drivers/net/wireless/Kconfig   |     2 +
+ module_drivers/drivers/net/wireless/Makefile  |     4 +
+ .../drivers/net/wireless/bcmdhd/Kconfig       |    60 +
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+ .../drivers/net/wireless/bcmdhd/README        |     2 +
+ .../drivers/net/wireless/bcmdhd/aiutils.c     |  1810 ++
+ .../net/wireless/bcmdhd/bcm_app_utils.c       |  1015 +
+ .../drivers/net/wireless/bcmdhd/bcmevent.c    |   385 +
+ .../drivers/net/wireless/bcmdhd/bcmsdh.c      |   847 +
+ .../net/wireless/bcmdhd/bcmsdh_linux.c        |   517 +
+ .../net/wireless/bcmdhd/bcmsdh_sdmmc.c        |  1774 ++
+ .../net/wireless/bcmdhd/bcmsdh_sdmmc_linux.c  |   405 +
+ .../net/wireless/bcmdhd/bcmsdspi_linux.c      |   252 +
+ .../drivers/net/wireless/bcmdhd/bcmspibrcm.c  |  1764 ++
+ .../drivers/net/wireless/bcmdhd/bcmutils.c    |  4106 +++
+ .../net/wireless/bcmdhd/bcmwifi_channels.c    |  1349 +
+ .../net/wireless/bcmdhd/bcmwifi_channels.h    |   645 +
+ .../net/wireless/bcmdhd/bcmwifi_rates.h       |   793 +
+ .../drivers/net/wireless/bcmdhd/bcmxtlv.c     |   457 +
+ .../drivers/net/wireless/bcmdhd/dbus.c        |  2904 ++
+ .../drivers/net/wireless/bcmdhd/dbus_usb.c    |  1172 +
+ .../net/wireless/bcmdhd/dbus_usb_linux.c      |  3403 +++
+ .../drivers/net/wireless/bcmdhd/dhd.h         |  2594 ++
+ .../drivers/net/wireless/bcmdhd/dhd_bus.h     |   298 +
+ .../drivers/net/wireless/bcmdhd/dhd_buzzz.h   |    37 +
+ .../drivers/net/wireless/bcmdhd/dhd_ccode.c   |   234 +
+ .../drivers/net/wireless/bcmdhd/dhd_cdc.c     |   962 +
+ .../net/wireless/bcmdhd/dhd_cfg80211.c        |   269 +
+ .../net/wireless/bcmdhd/dhd_cfg80211.h        |    54 +
+ .../drivers/net/wireless/bcmdhd/dhd_common.c  |  6076 +++++
+ .../drivers/net/wireless/bcmdhd/dhd_config.c  |  3851 +++
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+ .../net/wireless/bcmdhd/dhd_custom_gpio.c     |   299 +
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+ .../net/wireless/bcmdhd/dhd_custom_msm.c      |   253 +
+ .../drivers/net/wireless/bcmdhd/dhd_dbg.h     |   347 +
+ .../drivers/net/wireless/bcmdhd/dhd_debug.c   |  2335 ++
+ .../drivers/net/wireless/bcmdhd/dhd_debug.h   |   868 +
+ .../net/wireless/bcmdhd/dhd_debug_linux.c     |   520 +
+ .../net/wireless/bcmdhd/dhd_flowring.c        |  1063 +
+ .../net/wireless/bcmdhd/dhd_flowring.h        |   275 +
+ .../drivers/net/wireless/bcmdhd/dhd_gpio.c    |   360 +
+ .../drivers/net/wireless/bcmdhd/dhd_ip.c      |  1318 +
+ .../drivers/net/wireless/bcmdhd/dhd_ip.h      |    85 +
+ .../drivers/net/wireless/bcmdhd/dhd_linux.c   | 19882 ++++++++++++++
+ .../drivers/net/wireless/bcmdhd/dhd_linux.h   |   189 +
+ .../net/wireless/bcmdhd/dhd_linux_platdev.c   |  1013 +
+ .../net/wireless/bcmdhd/dhd_linux_sched.c     |    51 +
+ .../net/wireless/bcmdhd/dhd_linux_wq.c        |   379 +
+ .../net/wireless/bcmdhd/dhd_linux_wq.h        |    81 +
+ .../drivers/net/wireless/bcmdhd/dhd_mschdbg.c |   747 +
+ .../drivers/net/wireless/bcmdhd/dhd_mschdbg.h |    39 +
+ .../drivers/net/wireless/bcmdhd/dhd_msgbuf.c  |  8951 ++++++
+ .../drivers/net/wireless/bcmdhd/dhd_pcie.c    |  8489 ++++++
+ .../drivers/net/wireless/bcmdhd/dhd_pcie.h    |   607 +
+ .../net/wireless/bcmdhd/dhd_pcie_linux.c      |  2316 ++
+ .../drivers/net/wireless/bcmdhd/dhd_pno.c     |  4050 +++
+ .../drivers/net/wireless/bcmdhd/dhd_pno.h     |   572 +
+ .../drivers/net/wireless/bcmdhd/dhd_proto.h   |   201 +
+ .../drivers/net/wireless/bcmdhd/dhd_rtt.c     |  2421 ++
+ .../drivers/net/wireless/bcmdhd/dhd_rtt.h     |   387 +
+ .../drivers/net/wireless/bcmdhd/dhd_sdio.c    | 10180 +++++++
+ .../net/wireless/bcmdhd/dhd_static_buf.c      |   535 +
+ .../drivers/net/wireless/bcmdhd/dhd_wlfc.c    |  4567 ++++
+ .../drivers/net/wireless/bcmdhd/dhd_wlfc.h    |   562 +
+ .../drivers/net/wireless/bcmdhd/dngl_stats.h  |   383 +
+ .../drivers/net/wireless/bcmdhd/dngl_wlhdr.h  |    43 +
+ .../drivers/net/wireless/bcmdhd/hnd_pktpool.c |  1180 +
+ .../drivers/net/wireless/bcmdhd/hnd_pktq.c    |   973 +
+ .../drivers/net/wireless/bcmdhd/hndpmu.c      |   382 +
+ .../net/wireless/bcmdhd/include/802.11.h      |  5128 ++++
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+ .../net/wireless/bcmdhd/include/802.11s.h     |   336 +
+ .../net/wireless/bcmdhd/include/802.1d.h      |    53 +
+ .../net/wireless/bcmdhd/include/802.3.h       |    55 +
+ .../net/wireless/bcmdhd/include/aidmp.h       |   424 +
+ .../net/wireless/bcmdhd/include/bcm_cfg.h     |    32 +
+ .../wireless/bcmdhd/include/bcm_mpool_pub.h   |   364 +
+ .../net/wireless/bcmdhd/include/bcm_ring.h    |   634 +
+ .../net/wireless/bcmdhd/include/bcmcdc.h      |   135 +
+ .../net/wireless/bcmdhd/include/bcmdefs.h     |   462 +
+ .../net/wireless/bcmdhd/include/bcmdevs.h     |   933 +
+ .../net/wireless/bcmdhd/include/bcmdhcp.h     |    92 +
+ .../net/wireless/bcmdhd/include/bcmendian.h   |   332 +
+ .../net/wireless/bcmdhd/include/bcmeth.h      |   117 +
+ .../net/wireless/bcmdhd/include/bcmevent.h    |   948 +
+ .../net/wireless/bcmdhd/include/bcmip.h       |   264 +
+ .../net/wireless/bcmdhd/include/bcmipv6.h     |   163 +
+ .../net/wireless/bcmdhd/include/bcmmsgbuf.h   |  1202 +
+ .../net/wireless/bcmdhd/include/bcmnvram.h    |   329 +
+ .../net/wireless/bcmdhd/include/bcmpcie.h     |   440 +
+ .../net/wireless/bcmdhd/include/bcmpcispi.h   |   184 +
+ .../net/wireless/bcmdhd/include/bcmperf.h     |    39 +
+ .../net/wireless/bcmdhd/include/bcmsdbus.h    |   173 +
+ .../net/wireless/bcmdhd/include/bcmsdh.h      |   273 +
+ .../wireless/bcmdhd/include/bcmsdh_sdmmc.h    |   129 +
+ .../net/wireless/bcmdhd/include/bcmsdpcm.h    |   302 +
+ .../net/wireless/bcmdhd/include/bcmsdspi.h    |   138 +
+ .../net/wireless/bcmdhd/include/bcmsdstd.h    |   285 +
+ .../net/wireless/bcmdhd/include/bcmspi.h      |    43 +
+ .../net/wireless/bcmdhd/include/bcmspibrcm.h  |   165 +
+ .../net/wireless/bcmdhd/include/bcmsrom_fmt.h |   973 +
+ .../net/wireless/bcmdhd/include/bcmsrom_tbl.h |  1408 +
+ .../net/wireless/bcmdhd/include/bcmtcp.h      |    93 +
+ .../net/wireless/bcmdhd/include/bcmudp.h      |    61 +
+ .../net/wireless/bcmdhd/include/bcmutils.h    |  1355 +
+ .../wireless/bcmdhd/include/brcm_nl80211.h    |    73 +
+ .../net/wireless/bcmdhd/include/dbus.h        |   600 +
+ .../net/wireless/bcmdhd/include/dhd_daemon.h  |    62 +
+ .../net/wireless/bcmdhd/include/dhdioctl.h    |   159 +
+ .../net/wireless/bcmdhd/include/dnglevent.h   |   120 +
+ .../net/wireless/bcmdhd/include/eapol.h       |   218 +
+ .../net/wireless/bcmdhd/include/epivers.h     |    51 +
+ .../net/wireless/bcmdhd/include/ethernet.h    |   227 +
+ .../net/wireless/bcmdhd/include/event_log.h   |   388 +
+ .../bcmdhd/include/event_log_payload.h        |   673 +
+ .../wireless/bcmdhd/include/event_log_set.h   |    53 +
+ .../wireless/bcmdhd/include/event_log_tag.h   |   222 +
+ .../net/wireless/bcmdhd/include/event_trace.h |   123 +
+ .../net/wireless/bcmdhd/include/hnd_armtrap.h |    90 +
+ .../net/wireless/bcmdhd/include/hnd_cons.h    |    84 +
+ .../net/wireless/bcmdhd/include/hnd_debug.h   |   206 +
+ .../net/wireless/bcmdhd/include/hnd_pktpool.h |   225 +
+ .../net/wireless/bcmdhd/include/hnd_pktq.h    |   284 +
+ .../net/wireless/bcmdhd/include/hndpmu.h      |    56 +
+ .../net/wireless/bcmdhd/include/hndsoc.h      |   327 +
+ .../net/wireless/bcmdhd/include/linux_osl.h   |  1170 +
+ .../net/wireless/bcmdhd/include/linuxver.h    |   812 +
+ .../net/wireless/bcmdhd/include/miniopt.h     |    83 +
+ .../net/wireless/bcmdhd/include/msgtrace.h    |    62 +
+ .../drivers/net/wireless/bcmdhd/include/nan.h |  1468 +
+ .../drivers/net/wireless/bcmdhd/include/osl.h |   260 +
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+ .../net/wireless/bcmdhd/include/osl_ext.h     |   697 +
+ .../drivers/net/wireless/bcmdhd/include/p2p.h |   713 +
+ .../bcmdhd/include/packed_section_end.h       |    63 +
+ .../bcmdhd/include/packed_section_start.h     |    67 +
+ .../net/wireless/bcmdhd/include/pcicfg.h      |   330 +
+ .../net/wireless/bcmdhd/include/pcie_core.h   |   959 +
+ .../net/wireless/bcmdhd/include/rte_ioctl.h   |    87 +
+ .../net/wireless/bcmdhd/include/sbchipc.h     |  4417 +++
+ .../net/wireless/bcmdhd/include/sbconfig.h    |   285 +
+ .../net/wireless/bcmdhd/include/sbgci.h       |   248 +
+ .../net/wireless/bcmdhd/include/sbhnddma.h    |   429 +
+ .../net/wireless/bcmdhd/include/sbpcmcia.h    |   139 +
+ .../net/wireless/bcmdhd/include/sbsdio.h      |   189 +
+ .../net/wireless/bcmdhd/include/sbsdpcmdev.h  |   300 +
+ .../net/wireless/bcmdhd/include/sbsocram.h    |   205 +
+ .../net/wireless/bcmdhd/include/sbsysmem.h    |   180 +
+ .../net/wireless/bcmdhd/include/sdio.h        |   630 +
+ .../net/wireless/bcmdhd/include/sdioh.h       |   448 +
+ .../net/wireless/bcmdhd/include/sdiovar.h     |   107 +
+ .../net/wireless/bcmdhd/include/sdspi.h       |    78 +
+ .../net/wireless/bcmdhd/include/siutils.h     |   729 +
+ .../net/wireless/bcmdhd/include/spid.h        |   168 +
+ .../net/wireless/bcmdhd/include/trxhdr.h      |    95 +
+ .../net/wireless/bcmdhd/include/typedefs.h    |   386 +
+ .../net/wireless/bcmdhd/include/usbrdl.h      |   134 +
+ .../net/wireless/bcmdhd/include/vlan.h        |    98 +
+ .../net/wireless/bcmdhd/include/wlfc_proto.h  |   376 +
+ .../net/wireless/bcmdhd/include/wlioctl.h     | 13828 ++++++++++
+ .../wireless/bcmdhd/include/wlioctl_defs.h    |  2243 ++
+ .../wireless/bcmdhd/include/wlioctl_utils.h   |    61 +
+ .../drivers/net/wireless/bcmdhd/include/wpa.h |   217 +
+ .../drivers/net/wireless/bcmdhd/include/wps.h |   389 +
+ .../drivers/net/wireless/bcmdhd/linux_osl.c   |  2842 ++
+ .../drivers/net/wireless/bcmdhd/pcie_core.c   |   135 +
+ .../drivers/net/wireless/bcmdhd/sbutils.c     |  1101 +
+ .../drivers/net/wireless/bcmdhd/siutils.c     |  3727 +++
+ .../net/wireless/bcmdhd/siutils_priv.h        |   333 +
+ .../drivers/net/wireless/bcmdhd/wl_android.c  |  5511 ++++
+ .../drivers/net/wireless/bcmdhd/wl_android.h  |   311 +
+ .../net/wireless/bcmdhd/wl_android_ext.c      |  6631 +++++
+ .../drivers/net/wireless/bcmdhd/wl_cfg80211.c | 22544 ++++++++++++++++
+ .../drivers/net/wireless/bcmdhd/wl_cfg80211.h |  1742 ++
+ .../net/wireless/bcmdhd/wl_cfg_btcoex.c       |   570 +
+ .../drivers/net/wireless/bcmdhd/wl_cfgnan.c   |    27 +
+ .../drivers/net/wireless/bcmdhd/wl_cfgnan.h   |   364 +
+ .../drivers/net/wireless/bcmdhd/wl_cfgp2p.c   |  2600 ++
+ .../drivers/net/wireless/bcmdhd/wl_cfgp2p.h   |   451 +
+ .../net/wireless/bcmdhd/wl_cfgvendor.c        |  3746 +++
+ .../net/wireless/bcmdhd/wl_cfgvendor.h        |   583 +
+ .../drivers/net/wireless/bcmdhd/wl_dbg.h      |   246 +
+ .../drivers/net/wireless/bcmdhd/wl_escan.c    |  1595 ++
+ .../drivers/net/wireless/bcmdhd/wl_escan.h    |    78 +
+ .../drivers/net/wireless/bcmdhd/wl_event.c    |   557 +
+ .../drivers/net/wireless/bcmdhd/wl_iw.c       |  4450 +++
+ .../drivers/net/wireless/bcmdhd/wl_iw.h       |   173 +
+ .../net/wireless/bcmdhd/wl_linux_mon.c        |   406 +
+ .../drivers/net/wireless/bcmdhd/wl_roam.c     |    28 +
+ .../drivers/net/wireless/bcmdhd/wlc_types.h   |   337 +
+ .../net/wireless/bcmdhd/wldev_common.c        |   540 +
+ .../net/wireless/bcmdhd/wldev_common.h        |   130 +
+ .../net/wireless/bcmdhd_1_363_125_17/Kconfig  |    68 +
+ .../net/wireless/bcmdhd_1_363_125_17/Makefile |   323 +
+ .../wireless/bcmdhd_1_363_125_17/aiutils.c    |  1298 +
+ .../bcmdhd_1_363_125_17/bcm_app_utils.c       |  1016 +
+ .../wireless/bcmdhd_1_363_125_17/bcmevent.c   |   234 +
+ .../net/wireless/bcmdhd_1_363_125_17/bcmsdh.c |   723 +
+ .../bcmdhd_1_363_125_17/bcmsdh_linux.c        |   471 +
+ .../bcmdhd_1_363_125_17/bcmsdh_sdmmc.c        |  1536 ++
+ .../bcmdhd_1_363_125_17/bcmsdh_sdmmc_linux.c  |   413 +
+ .../bcmdhd_1_363_125_17/bcmsdspi_linux.c      |   252 +
+ .../wireless/bcmdhd_1_363_125_17/bcmspibrcm.c |  1813 ++
+ .../wireless/bcmdhd_1_363_125_17/bcmutils.c   |  3677 +++
+ .../bcmdhd_1_363_125_17/bcmwifi_channels.c    |  1291 +
+ .../bcmdhd_1_363_125_17/bcmwifi_channels.h    |   663 +
+ .../bcmdhd_1_363_125_17/bcmwifi_rates.h       |   930 +
+ .../wireless/bcmdhd_1_363_125_17/bcmxtlv.c    |   461 +
+ .../net/wireless/bcmdhd_1_363_125_17/dbus.c   |  2500 ++
+ .../wireless/bcmdhd_1_363_125_17/dbus_usb.c   |  1227 +
+ .../bcmdhd_1_363_125_17/dbus_usb_linux.c      |  4600 ++++
+ .../net/wireless/bcmdhd_1_363_125_17/dhd.h    |  1598 ++
+ .../wireless/bcmdhd_1_363_125_17/dhd_bta.c    |   354 +
+ .../wireless/bcmdhd_1_363_125_17/dhd_bta.h    |    42 +
+ .../wireless/bcmdhd_1_363_125_17/dhd_bus.h    |   222 +
+ .../wireless/bcmdhd_1_363_125_17/dhd_buzzz.h  |    37 +
+ .../wireless/bcmdhd_1_363_125_17/dhd_cdc.c    |   963 +
+ .../bcmdhd_1_363_125_17/dhd_cfg80211.c        |   268 +
+ .../bcmdhd_1_363_125_17/dhd_cfg80211.h        |    54 +
+ .../bcmdhd_1_363_125_17/dhd_cfg_vendor.c      |   174 +
+ .../bcmdhd_1_363_125_17/dhd_chip_info.c       |    38 +
+ .../bcmdhd_1_363_125_17/dhd_chip_info.h       |    43 +
+ .../wireless/bcmdhd_1_363_125_17/dhd_common.c |  3467 +++
+ .../bcmdhd_1_363_125_17/dhd_custom_gpio.c     |   436 +
+ .../wireless/bcmdhd_1_363_125_17/dhd_dbg.h    |   146 +
+ .../wireless/bcmdhd_1_363_125_17/dhd_debug.c  |  1297 +
+ .../wireless/bcmdhd_1_363_125_17/dhd_debug.h  |   348 +
+ .../bcmdhd_1_363_125_17/dhd_debug_linux.c     |   418 +
+ .../bcmdhd_1_363_125_17/dhd_flowring.c        |   996 +
+ .../bcmdhd_1_363_125_17/dhd_flowring.h        |   252 +
+ .../net/wireless/bcmdhd_1_363_125_17/dhd_ip.c |  1285 +
+ .../net/wireless/bcmdhd_1_363_125_17/dhd_ip.h |    85 +
+ .../wireless/bcmdhd_1_363_125_17/dhd_linux.c  | 14067 ++++++++++
+ .../wireless/bcmdhd_1_363_125_17/dhd_linux.h  |   136 +
+ .../bcmdhd_1_363_125_17/dhd_linux_platdev.c   |   913 +
+ .../bcmdhd_1_363_125_17/dhd_linux_sched.c     |    51 +
+ .../bcmdhd_1_363_125_17/dhd_linux_wq.c        |   320 +
+ .../bcmdhd_1_363_125_17/dhd_linux_wq.h        |    69 +
+ .../wireless/bcmdhd_1_363_125_17/dhd_msgbuf.c |  6332 +++++
+ .../wireless/bcmdhd_1_363_125_17/dhd_pcie.c   |  5662 ++++
+ .../wireless/bcmdhd_1_363_125_17/dhd_pcie.h   |   266 +
+ .../bcmdhd_1_363_125_17/dhd_pcie_linux.c      |  1287 +
+ .../wireless/bcmdhd_1_363_125_17/dhd_pno.c    |  4111 +++
+ .../wireless/bcmdhd_1_363_125_17/dhd_pno.h    |   562 +
+ .../wireless/bcmdhd_1_363_125_17/dhd_proto.h  |   168 +
+ .../wireless/bcmdhd_1_363_125_17/dhd_rtt.c    |  2063 ++
+ .../wireless/bcmdhd_1_363_125_17/dhd_rtt.h    |   338 +
+ .../wireless/bcmdhd_1_363_125_17/dhd_sdio.c   |  8736 ++++++
+ .../wireless/bcmdhd_1_363_125_17/dhd_wlfc.c   |  4566 ++++
+ .../wireless/bcmdhd_1_363_125_17/dhd_wlfc.h   |   562 +
+ .../wireless/bcmdhd_1_363_125_17/dngl_stats.h |   285 +
+ .../wireless/bcmdhd_1_363_125_17/dngl_wlhdr.h |    43 +
+ .../bcmdhd_1_363_125_17/hnd_pktpool.c         |  1131 +
+ .../wireless/bcmdhd_1_363_125_17/hnd_pktq.c   |   888 +
+ .../net/wireless/bcmdhd_1_363_125_17/hndpmu.c |   292 +
+ .../wireless/bcmdhd_1_363_125_17/linux_osl.c  |  2531 ++
+ .../wireless/bcmdhd_1_363_125_17/pcie_core.c  |   115 +
+ .../wireless/bcmdhd_1_363_125_17/sbutils.c    |  1108 +
+ .../wireless/bcmdhd_1_363_125_17/siutils.c    |  3310 +++
+ .../bcmdhd_1_363_125_17/siutils_priv.h        |   290 +
+ .../wireless/bcmdhd_1_363_125_17/uamp_api.h   |   181 +
+ .../wireless/bcmdhd_1_363_125_17/wl_android.c |  2717 ++
+ .../wireless/bcmdhd_1_363_125_17/wl_android.h |    94 +
+ .../bcmdhd_1_363_125_17/wl_cfg80211.c         | 16532 +++++++++++
+ .../bcmdhd_1_363_125_17/wl_cfg80211.h         |  1380 +
+ .../bcmdhd_1_363_125_17/wl_cfg_btcoex.c       |   562 +
+ .../wireless/bcmdhd_1_363_125_17/wl_cfgnan.c  |  2126 ++
+ .../wireless/bcmdhd_1_363_125_17/wl_cfgnan.h  |   226 +
+ .../wireless/bcmdhd_1_363_125_17/wl_cfgp2p.c  |  2536 ++
+ .../wireless/bcmdhd_1_363_125_17/wl_cfgp2p.h  |   441 +
+ .../bcmdhd_1_363_125_17/wl_cfgvendor.c        |  2892 ++
+ .../bcmdhd_1_363_125_17/wl_cfgvendor.h        |   418 +
+ .../net/wireless/bcmdhd_1_363_125_17/wl_dbg.h |   211 +
+ .../net/wireless/bcmdhd_1_363_125_17/wl_iw.c  |  3801 +++
+ .../net/wireless/bcmdhd_1_363_125_17/wl_iw.h  |   164 +
+ .../bcmdhd_1_363_125_17/wl_linux_mon.c        |   406 +
+ .../wireless/bcmdhd_1_363_125_17/wl_roam.c    |    28 +
+ .../bcmdhd_1_363_125_17/wldev_common.c        |   465 +
+ .../bcmdhd_1_363_125_17/wldev_common.h        |   123 +
+ .../drivers/net/wireless/realtek/Makefile     |     4 +
+ .../net/wireless/realtek/rtl8723ds/Kconfig    |     4 +
+ .../net/wireless/realtek/rtl8723ds/Makefile   |  2439 ++
+ .../net/wireless/realtek/rtl8723ds/clean      |     5 +
+ .../realtek/rtl8723ds/core/crypto/aes-ccm.c   |   211 +
+ .../realtek/rtl8723ds/core/crypto/aes-ctr.c   |    70 +
+ .../realtek/rtl8723ds/core/crypto/aes-gcm.c   |   326 +
+ .../rtl8723ds/core/crypto/aes-internal-enc.c  |   129 +
+ .../rtl8723ds/core/crypto/aes-internal.c      |   843 +
+ .../realtek/rtl8723ds/core/crypto/aes-omac1.c |   172 +
+ .../realtek/rtl8723ds/core/crypto/aes-siv.c   |   207 +
+ .../realtek/rtl8723ds/core/crypto/aes.h       |    21 +
+ .../realtek/rtl8723ds/core/crypto/aes_i.h     |   125 +
+ .../realtek/rtl8723ds/core/crypto/aes_siv.h   |    21 +
+ .../realtek/rtl8723ds/core/crypto/aes_wrap.h  |    73 +
+ .../realtek/rtl8723ds/core/crypto/ccmp.c      |   384 +
+ .../realtek/rtl8723ds/core/crypto/gcmp.c      |   193 +
+ .../rtl8723ds/core/crypto/rtw_crypto_wrap.c   |    90 +
+ .../rtl8723ds/core/crypto/rtw_crypto_wrap.h   |    65 +
+ .../rtl8723ds/core/crypto/sha256-internal.c   |   230 +
+ .../rtl8723ds/core/crypto/sha256-prf.c        |   109 +
+ .../realtek/rtl8723ds/core/crypto/sha256.c    |   104 +
+ .../realtek/rtl8723ds/core/crypto/sha256.h    |    30 +
+ .../realtek/rtl8723ds/core/crypto/sha256_i.h  |    25 +
+ .../rtl8723ds/core/crypto/wlancrypto_wrap.h   |    34 +
+ .../realtek/rtl8723ds/core/efuse/rtw_efuse.c  |  3538 +++
+ .../realtek/rtl8723ds/core/mesh/rtw_mesh.c    |  4392 +++
+ .../realtek/rtl8723ds/core/mesh/rtw_mesh.h    |   537 +
+ .../rtl8723ds/core/mesh/rtw_mesh_hwmp.c       |  1674 ++
+ .../rtl8723ds/core/mesh/rtw_mesh_hwmp.h       |    60 +
+ .../rtl8723ds/core/mesh/rtw_mesh_pathtbl.c    |  1242 +
+ .../rtl8723ds/core/mesh/rtw_mesh_pathtbl.h    |   211 +
+ .../rtl8723ds/core/monitor/rtw_radiotap.c     |   615 +
+ .../rtl8723ds/core/monitor/rtw_radiotap.h     |    63 +
+ .../wireless/realtek/rtl8723ds/core/rtw_ap.c  |  5941 ++++
+ .../realtek/rtl8723ds/core/rtw_beamforming.c  |  2121 ++
+ .../realtek/rtl8723ds/core/rtw_br_ext.c       |  1581 ++
+ .../realtek/rtl8723ds/core/rtw_bt_mp.c        |  1575 ++
+ .../realtek/rtl8723ds/core/rtw_btcoex.c       |  1801 ++
+ .../rtl8723ds/core/rtw_btcoex_wifionly.c      |    47 +
+ .../realtek/rtl8723ds/core/rtw_chplan.c       |  1241 +
+ .../realtek/rtl8723ds/core/rtw_chplan.h       |    77 +
+ .../wireless/realtek/rtl8723ds/core/rtw_cmd.c |  5511 ++++
+ .../realtek/rtl8723ds/core/rtw_debug.c        |  7601 ++++++
+ .../realtek/rtl8723ds/core/rtw_eeprom.c       |   329 +
+ .../wireless/realtek/rtl8723ds/core/rtw_ft.c  |   668 +
+ .../realtek/rtl8723ds/core/rtw_ieee80211.c    |  3090 +++
+ .../wireless/realtek/rtl8723ds/core/rtw_io.c  |   952 +
+ .../realtek/rtl8723ds/core/rtw_ioctl_query.c  |    19 +
+ .../realtek/rtl8723ds/core/rtw_ioctl_set.c    |   923 +
+ .../wireless/realtek/rtl8723ds/core/rtw_iol.c |   388 +
+ .../wireless/realtek/rtl8723ds/core/rtw_mbo.c |   803 +
+ .../wireless/realtek/rtl8723ds/core/rtw_mem.c |   128 +
+ .../wireless/realtek/rtl8723ds/core/rtw_mi.c  |  1550 ++
+ .../realtek/rtl8723ds/core/rtw_mlme.c         |  5440 ++++
+ .../realtek/rtl8723ds/core/rtw_mlme_ext.c     | 16111 +++++++++++
+ .../wireless/realtek/rtl8723ds/core/rtw_mp.c  |  3971 +++
+ .../wireless/realtek/rtl8723ds/core/rtw_odm.c |   586 +
+ .../wireless/realtek/rtl8723ds/core/rtw_p2p.c |  5437 ++++
+ .../realtek/rtl8723ds/core/rtw_pwrctrl.c      |  2943 ++
+ .../realtek/rtl8723ds/core/rtw_recv.c         |  4687 ++++
+ .../wireless/realtek/rtl8723ds/core/rtw_rf.c  |  2126 ++
+ .../wireless/realtek/rtl8723ds/core/rtw_rm.c  |  2471 ++
+ .../realtek/rtl8723ds/core/rtw_rm_fsm.c       |  1016 +
+ .../realtek/rtl8723ds/core/rtw_rm_util.c      |   434 +
+ .../realtek/rtl8723ds/core/rtw_rson.c         |   588 +
+ .../realtek/rtl8723ds/core/rtw_sdio.c         |   157 +
+ .../realtek/rtl8723ds/core/rtw_security.c     |  2872 ++
+ .../realtek/rtl8723ds/core/rtw_sreset.c       |   316 +
+ .../realtek/rtl8723ds/core/rtw_sta_mgt.c      |  1352 +
+ .../realtek/rtl8723ds/core/rtw_swcrypto.c     |   296 +
+ .../realtek/rtl8723ds/core/rtw_tdls.c         |  3507 +++
+ .../wireless/realtek/rtl8723ds/core/rtw_vht.c |  1134 +
+ .../realtek/rtl8723ds/core/rtw_wapi.c         |  1320 +
+ .../realtek/rtl8723ds/core/rtw_wapi_sms4.c    |   922 +
+ .../realtek/rtl8723ds/core/rtw_wlan_util.c    |  5029 ++++
+ .../wireless/realtek/rtl8723ds/core/rtw_wnm.c |   865 +
+ .../realtek/rtl8723ds/core/rtw_xmit.c         |  6338 +++++
+ .../realtek/rtl8723ds/core/wds/rtw_wds.c      |   463 +
+ .../realtek/rtl8723ds/core/wds/rtw_wds.h      |    54 +
+ .../realtek/rtl8723ds/hal/HalPwrSeqCmd.c      |   185 +
+ .../rtl8723ds/hal/btc/btc_basic_types.h       |    53 +
+ .../rtl8723ds/hal/btc/halbtc8723d1ant.c       |  5319 ++++
+ .../rtl8723ds/hal/btc/halbtc8723d1ant.h       |   475 +
+ .../rtl8723ds/hal/btc/halbtc8723d2ant.c       |  6236 +++++
+ .../rtl8723ds/hal/btc/halbtc8723d2ant.h       |   486 +
+ .../realtek/rtl8723ds/hal/btc/halbtcoutsrc.h  |  2061 ++
+ .../realtek/rtl8723ds/hal/btc/mp_precomp.h    |   159 +
+ .../realtek/rtl8723ds/hal/efuse/efuse_mask.h  |   181 +
+ .../efuse/rtl8723d/HalEfuseMask8723D_PCIE.c   |    91 +
+ .../efuse/rtl8723d/HalEfuseMask8723D_PCIE.h   |    32 +
+ .../efuse/rtl8723d/HalEfuseMask8723D_SDIO.c   |    89 +
+ .../efuse/rtl8723d/HalEfuseMask8723D_SDIO.h   |    31 +
+ .../efuse/rtl8723d/HalEfuseMask8723D_USB.c    |    92 +
+ .../efuse/rtl8723d/HalEfuseMask8723D_USB.h    |    34 +
+ .../realtek/rtl8723ds/hal/hal_btcoex.c        |  6388 +++++
+ .../rtl8723ds/hal/hal_btcoex_wifionly.c       |   264 +
+ .../wireless/realtek/rtl8723ds/hal/hal_com.c  | 15699 +++++++++++
+ .../realtek/rtl8723ds/hal/hal_com_c2h.h       |   140 +
+ .../realtek/rtl8723ds/hal/hal_com_phycfg.c    |  6197 +++++
+ .../wireless/realtek/rtl8723ds/hal/hal_dm.c   |  1855 ++
+ .../wireless/realtek/rtl8723ds/hal/hal_dm.h   |   118 +
+ .../realtek/rtl8723ds/hal/hal_dm_acs.c        |   554 +
+ .../realtek/rtl8723ds/hal/hal_dm_acs.h        |   167 +
+ .../realtek/rtl8723ds/hal/hal_halmac.c        |  5868 ++++
+ .../realtek/rtl8723ds/hal/hal_halmac.h        |   251 +
+ .../realtek/rtl8723ds/hal/hal_hci/hal_sdio.c  |   810 +
+ .../rtl8723ds/hal/hal_hci/hal_sdio_coex.c     |    35 +
+ .../wireless/realtek/rtl8723ds/hal/hal_intf.c |  2291 ++
+ .../wireless/realtek/rtl8723ds/hal/hal_mcc.c  |  4048 +++
+ .../wireless/realtek/rtl8723ds/hal/hal_mp.c   |  2634 ++
+ .../wireless/realtek/rtl8723ds/hal/hal_phy.c  |   257 +
+ .../realtek/rtl8723ds/hal/led/hal_led.c       |   254 +
+ .../realtek/rtl8723ds/hal/led/hal_sdio_led.c  |  2014 ++
+ .../rtl8723ds/hal/phydm/ap_makefile.mk        |   222 +
+ .../realtek/rtl8723ds/hal/phydm/halhwimg.h    |   137 +
+ .../rtl8723ds/hal/phydm/halrf/halphyrf_ap.c   |  1674 ++
+ .../rtl8723ds/hal/phydm/halrf/halphyrf_ap.h   |   170 +
+ .../rtl8723ds/hal/phydm/halrf/halphyrf_ce.c   |  1176 +
+ .../rtl8723ds/hal/phydm/halrf/halphyrf_ce.h   |   123 +
+ .../rtl8723ds/hal/phydm/halrf/halphyrf_iot.c  |   652 +
+ .../rtl8723ds/hal/phydm/halrf/halphyrf_iot.h  |   137 +
+ .../rtl8723ds/hal/phydm/halrf/halphyrf_win.c  |  1091 +
+ .../rtl8723ds/hal/phydm/halrf/halphyrf_win.h  |   132 +
+ .../realtek/rtl8723ds/hal/phydm/halrf/halrf.c |  4065 +++
+ .../realtek/rtl8723ds/hal/phydm/halrf/halrf.h |   787 +
+ .../rtl8723ds/hal/phydm/halrf/halrf_debug.c   |   390 +
+ .../rtl8723ds/hal/phydm/halrf/halrf_debug.h   |   123 +
+ .../rtl8723ds/hal/phydm/halrf/halrf_dpk.h     |   150 +
+ .../hal/phydm/halrf/halrf_features.h          |    43 +
+ .../rtl8723ds/hal/phydm/halrf/halrf_iqk.h     |   149 +
+ .../rtl8723ds/hal/phydm/halrf/halrf_kfree.c   |  2940 ++
+ .../rtl8723ds/hal/phydm/halrf/halrf_kfree.h   |   234 +
+ .../hal/phydm/halrf/halrf_powertracking.c     |   183 +
+ .../hal/phydm/halrf/halrf_powertracking.h     |    43 +
+ .../hal/phydm/halrf/halrf_powertracking_ap.c  |  1252 +
+ .../hal/phydm/halrf/halrf_powertracking_ap.h  |   406 +
+ .../hal/phydm/halrf/halrf_powertracking_ce.c  |   936 +
+ .../hal/phydm/halrf/halrf_powertracking_ce.h  |   330 +
+ .../hal/phydm/halrf/halrf_powertracking_iot.c |   980 +
+ .../hal/phydm/halrf/halrf_powertracking_iot.h |   371 +
+ .../hal/phydm/halrf/halrf_powertracking_win.c |   909 +
+ .../hal/phydm/halrf/halrf_powertracking_win.h |   305 +
+ .../rtl8723ds/hal/phydm/halrf/halrf_psd.c     |   531 +
+ .../rtl8723ds/hal/phydm/halrf/halrf_psd.h     |    50 +
+ .../hal/phydm/halrf/halrf_txgapcal.c          |   300 +
+ .../hal/phydm/halrf/halrf_txgapcal.h          |    31 +
+ .../hal/phydm/halrf/rtl8723d/halrf_8723d.c    |  2637 ++
+ .../hal/phydm/halrf/rtl8723d/halrf_8723d.h    |    83 +
+ .../realtek/rtl8723ds/hal/phydm/mp_precomp.h  |    24 +
+ .../realtek/rtl8723ds/hal/phydm/phydm.c       |  3684 +++
+ .../realtek/rtl8723ds/hal/phydm/phydm.h       |  1541 ++
+ .../realtek/rtl8723ds/hal/phydm/phydm.mk      |   233 +
+ .../rtl8723ds/hal/phydm/phydm_adaptivity.c    |   847 +
+ .../rtl8723ds/hal/phydm/phydm_adaptivity.h    |   126 +
+ .../rtl8723ds/hal/phydm/phydm_adc_sampling.c  |  1597 ++
+ .../rtl8723ds/hal/phydm/phydm_adc_sampling.h  |   172 +
+ .../rtl8723ds/hal/phydm/phydm_antdect.c       |   888 +
+ .../rtl8723ds/hal/phydm/phydm_antdect.h       |    78 +
+ .../rtl8723ds/hal/phydm/phydm_antdiv.c        |  6143 +++++
+ .../rtl8723ds/hal/phydm/phydm_antdiv.h        |   534 +
+ .../realtek/rtl8723ds/hal/phydm/phydm_api.c   |  3383 +++
+ .../realtek/rtl8723ds/hal/phydm/phydm_api.h   |   214 +
+ .../rtl8723ds/hal/phydm/phydm_auto_dbg.c      |   725 +
+ .../rtl8723ds/hal/phydm/phydm_auto_dbg.h      |   115 +
+ .../rtl8723ds/hal/phydm/phydm_beamforming.c   |  1986 ++
+ .../rtl8723ds/hal/phydm/phydm_beamforming.h   |   363 +
+ .../rtl8723ds/hal/phydm/phydm_cck_pd.c        |  1359 +
+ .../rtl8723ds/hal/phydm/phydm_cck_pd.h        |   192 +
+ .../hal/phydm/phydm_cck_rx_pathdiv.c          |   164 +
+ .../hal/phydm/phydm_cck_rx_pathdiv.h          |    67 +
+ .../realtek/rtl8723ds/hal/phydm/phydm_ccx.c   |  1951 ++
+ .../realtek/rtl8723ds/hal/phydm/phydm_ccx.h   |   261 +
+ .../rtl8723ds/hal/phydm/phydm_cfotracking.c   |   618 +
+ .../rtl8723ds/hal/phydm/phydm_cfotracking.h   |    74 +
+ .../realtek/rtl8723ds/hal/phydm/phydm_debug.c |  5864 ++++
+ .../realtek/rtl8723ds/hal/phydm/phydm_debug.h |   484 +
+ .../realtek/rtl8723ds/hal/phydm/phydm_dfs.c   |  2196 ++
+ .../realtek/rtl8723ds/hal/phydm/phydm_dfs.h   |   191 +
+ .../realtek/rtl8723ds/hal/phydm/phydm_dig.c   |  3447 +++
+ .../realtek/rtl8723ds/hal/phydm/phydm_dig.h   |   373 +
+ .../rtl8723ds/hal/phydm/phydm_direct_bf.c     |   366 +
+ .../rtl8723ds/hal/phydm/phydm_direct_bf.h     |    44 +
+ .../hal/phydm/phydm_dynamictxpower.c          |   764 +
+ .../hal/phydm/phydm_dynamictxpower.h          |   142 +
+ .../rtl8723ds/hal/phydm/phydm_features.h      |    80 +
+ .../rtl8723ds/hal/phydm/phydm_features_ap.h   |   218 +
+ .../rtl8723ds/hal/phydm/phydm_features_ce.h   |   232 +
+ .../hal/phydm/phydm_features_ce2_kernel.h     |    84 +
+ .../rtl8723ds/hal/phydm/phydm_features_iot.h  |   171 +
+ .../rtl8723ds/hal/phydm/phydm_features_win.h  |   210 +
+ .../rtl8723ds/hal/phydm/phydm_hwconfig.c      |  1641 ++
+ .../rtl8723ds/hal/phydm/phydm_hwconfig.h      |    79 +
+ .../rtl8723ds/hal/phydm/phydm_interface.c     |  1472 +
+ .../rtl8723ds/hal/phydm/phydm_interface.h     |   326 +
+ .../rtl8723ds/hal/phydm/phydm_lna_sat.c       |  1335 +
+ .../rtl8723ds/hal/phydm/phydm_lna_sat.h       |   173 +
+ .../rtl8723ds/hal/phydm/phydm_math_lib.c      |   285 +
+ .../rtl8723ds/hal/phydm/phydm_math_lib.h      |   120 +
+ .../realtek/rtl8723ds/hal/phydm/phydm_mp.c    |   302 +
+ .../realtek/rtl8723ds/hal/phydm/phydm_mp.h    |    78 +
+ .../rtl8723ds/hal/phydm/phydm_noisemonitor.c  |   467 +
+ .../rtl8723ds/hal/phydm/phydm_noisemonitor.h  |    48 +
+ .../rtl8723ds/hal/phydm/phydm_pathdiv.c       |  1115 +
+ .../rtl8723ds/hal/phydm/phydm_pathdiv.h       |   145 +
+ .../rtl8723ds/hal/phydm/phydm_phystatus.c     |  3134 +++
+ .../rtl8723ds/hal/phydm/phydm_phystatus.h     |  1178 +
+ .../hal/phydm/phydm_pmac_tx_setting.c         |   510 +
+ .../hal/phydm/phydm_pmac_tx_setting.h         |   109 +
+ .../rtl8723ds/hal/phydm/phydm_pow_train.c     |   171 +
+ .../rtl8723ds/hal/phydm/phydm_pow_train.h     |    84 +
+ .../rtl8723ds/hal/phydm/phydm_pre_define.h    |   980 +
+ .../rtl8723ds/hal/phydm/phydm_precomp.h       |   625 +
+ .../rtl8723ds/hal/phydm/phydm_primary_cca.c   |   173 +
+ .../rtl8723ds/hal/phydm/phydm_primary_cca.h   |    76 +
+ .../realtek/rtl8723ds/hal/phydm/phydm_psd.c   |   486 +
+ .../realtek/rtl8723ds/hal/phydm/phydm_psd.h   |    68 +
+ .../rtl8723ds/hal/phydm/phydm_rainfo.c        |  2365 ++
+ .../rtl8723ds/hal/phydm/phydm_rainfo.h        |   306 +
+ .../realtek/rtl8723ds/hal/phydm/phydm_reg.h   |   243 +
+ .../rtl8723ds/hal/phydm/phydm_regdefine11ac.h |   109 +
+ .../rtl8723ds/hal/phydm/phydm_regdefine11n.h  |   220 +
+ .../rtl8723ds/hal/phydm/phydm_regtable.h      |   969 +
+ .../rtl8723ds/hal/phydm/phydm_rssi_monitor.c  |   189 +
+ .../rtl8723ds/hal/phydm/phydm_rssi_monitor.h  |    58 +
+ .../rtl8723ds/hal/phydm/phydm_smt_ant.c       |  2277 ++
+ .../rtl8723ds/hal/phydm/phydm_smt_ant.h       |   210 +
+ .../realtek/rtl8723ds/hal/phydm/phydm_soml.c  |  1441 +
+ .../realtek/rtl8723ds/hal/phydm/phydm_soml.h  |   199 +
+ .../realtek/rtl8723ds/hal/phydm/phydm_types.h |   413 +
+ .../hal/phydm/rtl8723d/hal8723dreg.h          |   947 +
+ .../hal/phydm/rtl8723d/halhwimg8723d_bb.c     |   908 +
+ .../hal/phydm/rtl8723d/halhwimg8723d_bb.h     |    51 +
+ .../hal/phydm/rtl8723d/halhwimg8723d_mac.c    |   294 +
+ .../hal/phydm/rtl8723d/halhwimg8723d_mac.h    |    33 +
+ .../hal/phydm/rtl8723d/halhwimg8723d_rf.c     |  1182 +
+ .../hal/phydm/rtl8723d/halhwimg8723d_rf.h     |    78 +
+ .../hal/phydm/rtl8723d/phydm_regconfig8723d.c |   145 +
+ .../hal/phydm/rtl8723d/phydm_regconfig8723d.h |    44 +
+ .../hal/phydm/rtl8723d/phydm_rtl8723d.c       |    50 +
+ .../hal/phydm/rtl8723d/phydm_rtl8723d.h       |    24 +
+ .../hal/phydm/rtl8723d/version_rtl8723d.h     |     4 +
+ .../rtl8723ds/hal/phydm/sd4_phydm_2_kernel.mk |   188 +
+ .../rtl8723ds/hal/phydm/txbf/halcomtxbf.c     |   520 +
+ .../rtl8723ds/hal/phydm/txbf/halcomtxbf.h     |   183 +
+ .../rtl8723ds/hal/phydm/txbf/haltxbf8192e.c   |   384 +
+ .../rtl8723ds/hal/phydm/txbf/haltxbf8192e.h   |    71 +
+ .../rtl8723ds/hal/phydm/txbf/haltxbf8814a.c   |   675 +
+ .../rtl8723ds/hal/phydm/txbf/haltxbf8814a.h   |    77 +
+ .../rtl8723ds/hal/phydm/txbf/haltxbf8822b.c   |  1088 +
+ .../rtl8723ds/hal/phydm/txbf/haltxbf8822b.h   |    78 +
+ .../hal/phydm/txbf/haltxbfinterface.c         |  1484 +
+ .../hal/phydm/txbf/haltxbfinterface.h         |   167 +
+ .../rtl8723ds/hal/phydm/txbf/haltxbfjaguar.c  |   509 +
+ .../rtl8723ds/hal/phydm/txbf/haltxbfjaguar.h  |    78 +
+ .../hal/phydm/txbf/phydm_hal_txbf_api.c       |   748 +
+ .../hal/phydm/txbf/phydm_hal_txbf_api.h       |    89 +
+ .../rtl8723ds/hal/rtl8723d/Hal8723DPwrSeq.c   |    84 +
+ .../rtl8723ds/hal/rtl8723d/hal8723d_fw.c      | 10915 ++++++++
+ .../rtl8723ds/hal/rtl8723d/hal8723d_fw.h      |    40 +
+ .../rtl8723ds/hal/rtl8723d/rtl8723d_cmd.c     |   476 +
+ .../rtl8723ds/hal/rtl8723d/rtl8723d_dm.c      |   310 +
+ .../hal/rtl8723d/rtl8723d_hal_init.c          |  5476 ++++
+ .../hal/rtl8723d/rtl8723d_lps_poff.c          |   871 +
+ .../rtl8723ds/hal/rtl8723d/rtl8723d_phycfg.c  |  1193 +
+ .../rtl8723ds/hal/rtl8723d/rtl8723d_rf6052.c  |   235 +
+ .../rtl8723ds/hal/rtl8723d/rtl8723d_rxdesc.c  |    57 +
+ .../rtl8723ds/hal/rtl8723d/rtl8723d_sreset.c  |   101 +
+ .../hal/rtl8723d/sdio/rtl8723ds_led.c         |   123 +
+ .../hal/rtl8723d/sdio/rtl8723ds_recv.c        |   510 +
+ .../hal/rtl8723d/sdio/rtl8723ds_xmit.c        |   797 +
+ .../hal/rtl8723d/sdio/sdio_halinit.c          |  1761 ++
+ .../rtl8723ds/hal/rtl8723d/sdio/sdio_ops.c    |  1815 ++
+ .../wireless/realtek/rtl8723ds/ifcfg-wlan0    |     4 +
+ .../rtl8723ds/include/Hal8188EPhyCfg.h        |   249 +
+ .../rtl8723ds/include/Hal8188EPhyReg.h        |  1100 +
+ .../rtl8723ds/include/Hal8188EPwrSeq.h        |   170 +
+ .../rtl8723ds/include/Hal8188FPhyCfg.h        |   120 +
+ .../rtl8723ds/include/Hal8188FPhyReg.h        |  1165 +
+ .../rtl8723ds/include/Hal8188FPwrSeq.h        |   212 +
+ .../rtl8723ds/include/Hal8192EPhyCfg.h        |   136 +
+ .../rtl8723ds/include/Hal8192EPhyReg.h        |  1146 +
+ .../rtl8723ds/include/Hal8192EPwrSeq.h        |   169 +
+ .../rtl8723ds/include/Hal8192FPhyCfg.h        |   115 +
+ .../rtl8723ds/include/Hal8192FPhyReg.h        |  1134 +
+ .../rtl8723ds/include/Hal8192FPwrSeq.h        |   220 +
+ .../rtl8723ds/include/Hal8703BPhyCfg.h        |   116 +
+ .../rtl8723ds/include/Hal8703BPhyReg.h        |  1133 +
+ .../rtl8723ds/include/Hal8703BPwrSeq.h        |   198 +
+ .../rtl8723ds/include/Hal8710BPhyCfg.h        |   111 +
+ .../rtl8723ds/include/Hal8710BPhyReg.h        |  1134 +
+ .../rtl8723ds/include/Hal8710BPwrSeq.h        |   167 +
+ .../rtl8723ds/include/Hal8723BPhyCfg.h        |   116 +
+ .../rtl8723ds/include/Hal8723BPhyReg.h        |  1131 +
+ .../rtl8723ds/include/Hal8723BPwrSeq.h        |   246 +
+ .../rtl8723ds/include/Hal8723DPhyCfg.h        |   115 +
+ .../rtl8723ds/include/Hal8723DPhyReg.h        |  1134 +
+ .../rtl8723ds/include/Hal8723DPwrSeq.h        |   206 +
+ .../realtek/rtl8723ds/include/Hal8723PwrSeq.h |   183 +
+ .../realtek/rtl8723ds/include/Hal8812PhyCfg.h |   134 +
+ .../realtek/rtl8723ds/include/Hal8812PhyReg.h |   735 +
+ .../realtek/rtl8723ds/include/Hal8812PwrSeq.h |   208 +
+ .../realtek/rtl8723ds/include/Hal8814PhyCfg.h |   236 +
+ .../realtek/rtl8723ds/include/Hal8814PhyReg.h |   863 +
+ .../realtek/rtl8723ds/include/Hal8814PwrSeq.h |   231 +
+ .../rtl8723ds/include/Hal8821APwrSeq.h        |   200 +
+ .../realtek/rtl8723ds/include/HalPwrSeqCmd.h  |   130 +
+ .../realtek/rtl8723ds/include/HalVerDef.h     |   207 +
+ .../realtek/rtl8723ds/include/autoconf.h      |   303 +
+ .../realtek/rtl8723ds/include/basic_types.h   |   357 +
+ .../rtl8723ds/include/byteorder/big_endian.h  |    82 +
+ .../rtl8723ds/include/byteorder/generic.h     |   207 +
+ .../include/byteorder/little_endian.h         |    84 +
+ .../rtl8723ds/include/byteorder/swab.h        |   136 +
+ .../rtl8723ds/include/byteorder/swabb.h       |   151 +
+ .../realtek/rtl8723ds/include/circ_buf.h      |    23 +
+ .../realtek/rtl8723ds/include/cmd_osdep.h     |    26 +
+ .../rtl8723ds/include/cmn_info/rtw_sta_info.h |   277 +
+ .../realtek/rtl8723ds/include/custom_gpio.h   |    34 +
+ .../realtek/rtl8723ds/include/drv_conf.h      |   729 +
+ .../realtek/rtl8723ds/include/drv_types.h     |  1982 ++
+ .../realtek/rtl8723ds/include/drv_types_ce.h  |    86 +
+ .../rtl8723ds/include/drv_types_gspi.h        |    49 +
+ .../rtl8723ds/include/drv_types_linux.h       |    19 +
+ .../realtek/rtl8723ds/include/drv_types_pci.h |    60 +
+ .../rtl8723ds/include/drv_types_sdio.h        |    94 +
+ .../realtek/rtl8723ds/include/drv_types_xp.h  |    88 +
+ .../realtek/rtl8723ds/include/ethernet.h      |    36 +
+ .../realtek/rtl8723ds/include/gspi_hal.h      |    30 +
+ .../realtek/rtl8723ds/include/gspi_ops.h      |   180 +
+ .../rtl8723ds/include/gspi_ops_linux.h        |    18 +
+ .../realtek/rtl8723ds/include/gspi_osintf.h   |    19 +
+ .../realtek/rtl8723ds/include/h2clbk.h        |    26 +
+ .../realtek/rtl8723ds/include/hal_btcoex.h    |   106 +
+ .../rtl8723ds/include/hal_btcoex_wifionly.h   |    88 +
+ .../realtek/rtl8723ds/include/hal_com.h       |   803 +
+ .../realtek/rtl8723ds/include/hal_com_h2c.h   |   673 +
+ .../realtek/rtl8723ds/include/hal_com_led.h   |   437 +
+ .../rtl8723ds/include/hal_com_phycfg.h        |   350 +
+ .../realtek/rtl8723ds/include/hal_com_reg.h   |  1889 ++
+ .../realtek/rtl8723ds/include/hal_data.h      |   879 +
+ .../realtek/rtl8723ds/include/hal_gspi.h      |    26 +
+ .../realtek/rtl8723ds/include/hal_ic_cfg.h    |   602 +
+ .../realtek/rtl8723ds/include/hal_intf.h      |   895 +
+ .../realtek/rtl8723ds/include/hal_pg.h        |   954 +
+ .../realtek/rtl8723ds/include/hal_phy.h       |   234 +
+ .../realtek/rtl8723ds/include/hal_phy_reg.h   |   270 +
+ .../realtek/rtl8723ds/include/hal_sdio.h      |    84 +
+ .../realtek/rtl8723ds/include/hal_sdio_coex.h |    41 +
+ .../realtek/rtl8723ds/include/ieee80211.h     |  2045 ++
+ .../realtek/rtl8723ds/include/ieee80211_ext.h |   312 +
+ .../realtek/rtl8723ds/include/if_ether.h      |   106 +
+ .../wireless/realtek/rtl8723ds/include/ip.h   |   135 +
+ .../rtl8723ds/include/linux/wireless.h        |    87 +
+ .../realtek/rtl8723ds/include/mlme_osdep.h    |    25 +
+ .../realtek/rtl8723ds/include/nic_spec.h      |    41 +
+ .../realtek/rtl8723ds/include/osdep_intf.h    |   139 +
+ .../realtek/rtl8723ds/include/osdep_service.h |   825 +
+ .../rtl8723ds/include/osdep_service_bsd.h     |   757 +
+ .../rtl8723ds/include/osdep_service_ce.h      |   200 +
+ .../rtl8723ds/include/osdep_service_linux.h   |   550 +
+ .../rtl8723ds/include/osdep_service_xp.h      |   210 +
+ .../realtek/rtl8723ds/include/pci_hal.h       |    60 +
+ .../realtek/rtl8723ds/include/pci_ops.h       |   116 +
+ .../realtek/rtl8723ds/include/pci_osintf.h    |    69 +
+ .../realtek/rtl8723ds/include/recv_osdep.h    |    70 +
+ .../realtek/rtl8723ds/include/rtl8188e_cmd.h  |   165 +
+ .../realtek/rtl8723ds/include/rtl8188e_dm.h   |    27 +
+ .../realtek/rtl8723ds/include/rtl8188e_hal.h  |   316 +
+ .../realtek/rtl8723ds/include/rtl8188e_led.h  |    37 +
+ .../realtek/rtl8723ds/include/rtl8188e_recv.h |   156 +
+ .../realtek/rtl8723ds/include/rtl8188e_rf.h   |    27 +
+ .../realtek/rtl8723ds/include/rtl8188e_spec.h |   159 +
+ .../rtl8723ds/include/rtl8188e_sreset.h       |    24 +
+ .../realtek/rtl8723ds/include/rtl8188e_xmit.h |   293 +
+ .../realtek/rtl8723ds/include/rtl8188f_cmd.h  |   206 +
+ .../realtek/rtl8723ds/include/rtl8188f_dm.h   |    39 +
+ .../realtek/rtl8723ds/include/rtl8188f_hal.h  |   260 +
+ .../realtek/rtl8723ds/include/rtl8188f_led.h  |    45 +
+ .../realtek/rtl8723ds/include/rtl8188f_recv.h |    65 +
+ .../realtek/rtl8723ds/include/rtl8188f_rf.h   |    25 +
+ .../realtek/rtl8723ds/include/rtl8188f_spec.h |   275 +
+ .../rtl8723ds/include/rtl8188f_sreset.h       |    24 +
+ .../realtek/rtl8723ds/include/rtl8188f_xmit.h |   334 +
+ .../realtek/rtl8723ds/include/rtl8192e_cmd.h  |   147 +
+ .../realtek/rtl8723ds/include/rtl8192e_dm.h   |    28 +
+ .../realtek/rtl8723ds/include/rtl8192e_hal.h  |   330 +
+ .../realtek/rtl8723ds/include/rtl8192e_led.h  |    36 +
+ .../realtek/rtl8723ds/include/rtl8192e_recv.h |   175 +
+ .../realtek/rtl8723ds/include/rtl8192e_rf.h   |    28 +
+ .../realtek/rtl8723ds/include/rtl8192e_spec.h |   313 +
+ .../rtl8723ds/include/rtl8192e_sreset.h       |    24 +
+ .../realtek/rtl8723ds/include/rtl8192e_xmit.h |   448 +
+ .../realtek/rtl8723ds/include/rtl8192f_cmd.h  |   194 +
+ .../realtek/rtl8723ds/include/rtl8192f_dm.h   |    27 +
+ .../realtek/rtl8723ds/include/rtl8192f_hal.h  |   316 +
+ .../realtek/rtl8723ds/include/rtl8192f_led.h  |    59 +
+ .../realtek/rtl8723ds/include/rtl8192f_recv.h |   107 +
+ .../realtek/rtl8723ds/include/rtl8192f_rf.h   |    88 +
+ .../realtek/rtl8723ds/include/rtl8192f_spec.h |   541 +
+ .../rtl8723ds/include/rtl8192f_sreset.h       |    24 +
+ .../realtek/rtl8723ds/include/rtl8192f_xmit.h |   529 +
+ .../realtek/rtl8723ds/include/rtl8703b_cmd.h  |   205 +
+ .../realtek/rtl8723ds/include/rtl8703b_dm.h   |    39 +
+ .../realtek/rtl8723ds/include/rtl8703b_hal.h  |   266 +
+ .../realtek/rtl8723ds/include/rtl8703b_led.h  |    44 +
+ .../realtek/rtl8723ds/include/rtl8703b_recv.h |    82 +
+ .../realtek/rtl8723ds/include/rtl8703b_rf.h   |    25 +
+ .../realtek/rtl8723ds/include/rtl8703b_spec.h |   464 +
+ .../rtl8723ds/include/rtl8703b_sreset.h       |    24 +
+ .../realtek/rtl8723ds/include/rtl8703b_xmit.h |   333 +
+ .../realtek/rtl8723ds/include/rtl8710b_cmd.h  |   175 +
+ .../realtek/rtl8723ds/include/rtl8710b_dm.h   |    39 +
+ .../realtek/rtl8723ds/include/rtl8710b_hal.h  |   277 +
+ .../realtek/rtl8723ds/include/rtl8710b_led.h  |    44 +
+ .../rtl8723ds/include/rtl8710b_lps_poff.h     |    56 +
+ .../realtek/rtl8723ds/include/rtl8710b_recv.h |    81 +
+ .../realtek/rtl8723ds/include/rtl8710b_rf.h   |    20 +
+ .../realtek/rtl8723ds/include/rtl8710b_spec.h |   481 +
+ .../rtl8723ds/include/rtl8710b_sreset.h       |    24 +
+ .../realtek/rtl8723ds/include/rtl8710b_xmit.h |   520 +
+ .../realtek/rtl8723ds/include/rtl8723b_cmd.h  |   205 +
+ .../realtek/rtl8723ds/include/rtl8723b_dm.h   |    38 +
+ .../realtek/rtl8723ds/include/rtl8723b_hal.h  |   274 +
+ .../realtek/rtl8723ds/include/rtl8723b_led.h  |    44 +
+ .../realtek/rtl8723ds/include/rtl8723b_recv.h |    82 +
+ .../realtek/rtl8723ds/include/rtl8723b_rf.h   |    25 +
+ .../realtek/rtl8723ds/include/rtl8723b_spec.h |   280 +
+ .../rtl8723ds/include/rtl8723b_sreset.h       |    24 +
+ .../realtek/rtl8723ds/include/rtl8723b_xmit.h |   333 +
+ .../realtek/rtl8723ds/include/rtl8723d_cmd.h  |   189 +
+ .../realtek/rtl8723ds/include/rtl8723d_dm.h   |    39 +
+ .../realtek/rtl8723ds/include/rtl8723d_hal.h  |   303 +
+ .../realtek/rtl8723ds/include/rtl8723d_led.h  |    44 +
+ .../rtl8723ds/include/rtl8723d_lps_poff.h     |    56 +
+ .../realtek/rtl8723ds/include/rtl8723d_recv.h |   112 +
+ .../realtek/rtl8723ds/include/rtl8723d_rf.h   |    21 +
+ .../realtek/rtl8723ds/include/rtl8723d_spec.h |   447 +
+ .../rtl8723ds/include/rtl8723d_sreset.h       |    24 +
+ .../realtek/rtl8723ds/include/rtl8723d_xmit.h |   521 +
+ .../realtek/rtl8723ds/include/rtl8812a_cmd.h  |   158 +
+ .../realtek/rtl8723ds/include/rtl8812a_dm.h   |    27 +
+ .../realtek/rtl8723ds/include/rtl8812a_hal.h  |   369 +
+ .../realtek/rtl8723ds/include/rtl8812a_led.h  |    41 +
+ .../realtek/rtl8723ds/include/rtl8812a_recv.h |   149 +
+ .../realtek/rtl8723ds/include/rtl8812a_rf.h   |    28 +
+ .../realtek/rtl8723ds/include/rtl8812a_spec.h |   263 +
+ .../rtl8723ds/include/rtl8812a_sreset.h       |    24 +
+ .../realtek/rtl8723ds/include/rtl8812a_xmit.h |   365 +
+ .../realtek/rtl8723ds/include/rtl8814a_cmd.h  |   166 +
+ .../realtek/rtl8723ds/include/rtl8814a_dm.h   |    23 +
+ .../realtek/rtl8723ds/include/rtl8814a_hal.h  |   329 +
+ .../realtek/rtl8723ds/include/rtl8814a_led.h  |    36 +
+ .../realtek/rtl8723ds/include/rtl8814a_recv.h |   182 +
+ .../realtek/rtl8723ds/include/rtl8814a_rf.h   |    28 +
+ .../realtek/rtl8723ds/include/rtl8814a_spec.h |   654 +
+ .../rtl8723ds/include/rtl8814a_sreset.h       |    24 +
+ .../realtek/rtl8723ds/include/rtl8814a_xmit.h |   309 +
+ .../realtek/rtl8723ds/include/rtl8814b_hal.h  |   239 +
+ .../realtek/rtl8723ds/include/rtl8814be_hal.h |    30 +
+ .../realtek/rtl8723ds/include/rtl8814bu_hal.h |    61 +
+ .../realtek/rtl8723ds/include/rtl8821a_spec.h |    90 +
+ .../realtek/rtl8723ds/include/rtl8821a_xmit.h |   173 +
+ .../realtek/rtl8723ds/include/rtl8821c_dm.h   |    23 +
+ .../realtek/rtl8723ds/include/rtl8821c_hal.h  |    84 +
+ .../realtek/rtl8723ds/include/rtl8821c_spec.h |   202 +
+ .../realtek/rtl8723ds/include/rtl8821ce_hal.h |    23 +
+ .../realtek/rtl8723ds/include/rtl8821cs_hal.h |    23 +
+ .../realtek/rtl8723ds/include/rtl8821cu_hal.h |    24 +
+ .../realtek/rtl8723ds/include/rtl8822b_hal.h  |   234 +
+ .../realtek/rtl8723ds/include/rtl8822be_hal.h |    27 +
+ .../realtek/rtl8723ds/include/rtl8822bs_hal.h |    31 +
+ .../realtek/rtl8723ds/include/rtl8822bu_hal.h |    61 +
+ .../realtek/rtl8723ds/include/rtl8822c_hal.h  |   246 +
+ .../realtek/rtl8723ds/include/rtl8822ce_hal.h |    27 +
+ .../realtek/rtl8723ds/include/rtl8822cs_hal.h |    31 +
+ .../realtek/rtl8723ds/include/rtl8822cu_hal.h |    61 +
+ .../realtek/rtl8723ds/include/rtw_android.h   |   117 +
+ .../realtek/rtl8723ds/include/rtw_ap.h        |   143 +
+ .../rtl8723ds/include/rtw_beamforming.h       |   297 +
+ .../realtek/rtl8723ds/include/rtw_br_ext.h    |    69 +
+ .../realtek/rtl8723ds/include/rtw_bt_mp.h     |   288 +
+ .../realtek/rtl8723ds/include/rtw_btcoex.h    |   460 +
+ .../rtl8723ds/include/rtw_btcoex_wifionly.h   |    24 +
+ .../realtek/rtl8723ds/include/rtw_byteorder.h |    33 +
+ .../realtek/rtl8723ds/include/rtw_cmd.h       |   778 +
+ .../realtek/rtl8723ds/include/rtw_debug.h     |   700 +
+ .../realtek/rtl8723ds/include/rtw_eeprom.h    |   116 +
+ .../realtek/rtl8723ds/include/rtw_efuse.h     |   277 +
+ .../realtek/rtl8723ds/include/rtw_event.h     |    94 +
+ .../realtek/rtl8723ds/include/rtw_ft.h        |   183 +
+ .../realtek/rtl8723ds/include/rtw_ht.h        |   217 +
+ .../realtek/rtl8723ds/include/rtw_io.h        |   526 +
+ .../realtek/rtl8723ds/include/rtw_ioctl.h     |    47 +
+ .../rtl8723ds/include/rtw_ioctl_query.h       |    19 +
+ .../realtek/rtl8723ds/include/rtw_ioctl_set.h |    40 +
+ .../realtek/rtl8723ds/include/rtw_iol.h       |   131 +
+ .../realtek/rtl8723ds/include/rtw_mbo.h       |   114 +
+ .../realtek/rtl8723ds/include/rtw_mcc.h       |   315 +
+ .../realtek/rtl8723ds/include/rtw_mem.h       |    41 +
+ .../realtek/rtl8723ds/include/rtw_mi.h        |   310 +
+ .../realtek/rtl8723ds/include/rtw_mlme.h      |  1199 +
+ .../realtek/rtl8723ds/include/rtw_mlme_ext.h  |  1179 +
+ .../realtek/rtl8723ds/include/rtw_mp.h        |   937 +
+ .../rtl8723ds/include/rtw_mp_phy_regdef.h     |  1094 +
+ .../realtek/rtl8723ds/include/rtw_odm.h       |   102 +
+ .../realtek/rtl8723ds/include/rtw_p2p.h       |   169 +
+ .../realtek/rtl8723ds/include/rtw_pwrctrl.h   |   625 +
+ .../realtek/rtl8723ds/include/rtw_qos.h       |    66 +
+ .../realtek/rtl8723ds/include/rtw_recv.h      |   835 +
+ .../realtek/rtl8723ds/include/rtw_rf.h        |   306 +
+ .../realtek/rtl8723ds/include/rtw_rm.h        |    88 +
+ .../realtek/rtl8723ds/include/rtw_rm_fsm.h    |   396 +
+ .../realtek/rtl8723ds/include/rtw_rm_util.h   |    42 +
+ .../realtek/rtl8723ds/include/rtw_rson.h      |    61 +
+ .../realtek/rtl8723ds/include/rtw_sdio.h      |    26 +
+ .../realtek/rtl8723ds/include/rtw_security.h  |   421 +
+ .../realtek/rtl8723ds/include/rtw_sreset.h    |    66 +
+ .../realtek/rtl8723ds/include/rtw_swcrypto.h  |    49 +
+ .../realtek/rtl8723ds/include/rtw_tdls.h      |   185 +
+ .../realtek/rtl8723ds/include/rtw_version.h   |     2 +
+ .../realtek/rtl8723ds/include/rtw_vht.h       |   181 +
+ .../realtek/rtl8723ds/include/rtw_wapi.h      |   230 +
+ .../realtek/rtl8723ds/include/rtw_wnm.h       |   169 +
+ .../realtek/rtl8723ds/include/rtw_xmit.h      |  1085 +
+ .../realtek/rtl8723ds/include/sdio_hal.h      |    57 +
+ .../realtek/rtl8723ds/include/sdio_ops.h      |   206 +
+ .../realtek/rtl8723ds/include/sdio_ops_ce.h   |    49 +
+ .../rtl8723ds/include/sdio_ops_linux.h        |    58 +
+ .../realtek/rtl8723ds/include/sdio_ops_xp.h   |    49 +
+ .../realtek/rtl8723ds/include/sdio_osintf.h   |    19 +
+ .../realtek/rtl8723ds/include/sta_info.h      |   771 +
+ .../realtek/rtl8723ds/include/usb_hal.h       |    71 +
+ .../realtek/rtl8723ds/include/usb_ops.h       |   153 +
+ .../realtek/rtl8723ds/include/usb_ops_linux.h |    98 +
+ .../realtek/rtl8723ds/include/usb_osintf.h    |    26 +
+ .../rtl8723ds/include/usb_vendor_req.h        |    56 +
+ .../wireless/realtek/rtl8723ds/include/wifi.h |  1357 +
+ .../realtek/rtl8723ds/include/wlan_bssdef.h   |   327 +
+ .../realtek/rtl8723ds/include/xmit_osdep.h    |    96 +
+ .../os_dep/linux/custom_gpio_linux.c          |   377 +
+ .../rtl8723ds/os_dep/linux/ioctl_cfg80211.c   | 10775 ++++++++
+ .../rtl8723ds/os_dep/linux/ioctl_cfg80211.h   |   442 +
+ .../rtl8723ds/os_dep/linux/ioctl_linux.c      | 12920 +++++++++
+ .../realtek/rtl8723ds/os_dep/linux/ioctl_mp.c |  3393 +++
+ .../rtl8723ds/os_dep/linux/mlme_linux.c       |   444 +
+ .../realtek/rtl8723ds/os_dep/linux/os_intfs.c |  5646 ++++
+ .../rtl8723ds/os_dep/linux/recv_linux.c       |   678 +
+ .../rtl8723ds/os_dep/linux/rhashtable.c       |   844 +
+ .../rtl8723ds/os_dep/linux/rhashtable.h       |   827 +
+ .../rtl8723ds/os_dep/linux/rtw_android.c      |  1344 +
+ .../rtl8723ds/os_dep/linux/rtw_cfgvendor.c    |  2117 ++
+ .../rtl8723ds/os_dep/linux/rtw_cfgvendor.h    |   636 +
+ .../realtek/rtl8723ds/os_dep/linux/rtw_proc.c |  5614 ++++
+ .../realtek/rtl8723ds/os_dep/linux/rtw_proc.h |    66 +
+ .../rtl8723ds/os_dep/linux/rtw_rhashtable.c   |    77 +
+ .../rtl8723ds/os_dep/linux/rtw_rhashtable.h   |    67 +
+ .../rtl8723ds/os_dep/linux/sdio_intf.c        |  1374 +
+ .../rtl8723ds/os_dep/linux/sdio_ops_linux.c   |  1347 +
+ .../rtl8723ds/os_dep/linux/wifi_regd.c        |   128 +
+ .../rtl8723ds/os_dep/linux/wifi_regd.h        |    22 +
+ .../rtl8723ds/os_dep/linux/xmit_linux.c       |   538 +
+ .../realtek/rtl8723ds/os_dep/osdep_service.c  |  3220 +++
+ .../platform/custom_country_chplan.h          |    22 +
+ .../platform/platform_ARM_SUN50IW1P1_sdio.c   |    86 +
+ .../platform/platform_ARM_SUNnI_sdio.c        |   130 +
+ .../platform/platform_ARM_SUNxI_sdio.c        |    90 +
+ .../platform/platform_ARM_SUNxI_usb.c         |   136 +
+ .../platform/platform_ARM_WMT_sdio.c          |    46 +
+ .../rtl8723ds/platform/platform_RTK_DMP_usb.c |    30 +
+ .../platform/platform_aml_s905_sdio.c         |    54 +
+ .../platform/platform_aml_s905_sdio.h         |    28 +
+ .../platform/platform_arm_act_sdio.c          |    53 +
+ .../platform/platform_hisilicon_hi3798_sdio.c |   110 +
+ .../platform/platform_hisilicon_hi3798_sdio.h |    28 +
+ .../realtek/rtl8723ds/platform/platform_ops.c |    34 +
+ .../realtek/rtl8723ds/platform/platform_ops.h |    26 +
+ .../rtl8723ds/platform/platform_sprd_sdio.c   |    84 +
+ .../platform/platform_zte_zx296716_sdio.c     |    53 +
+ .../platform/platform_zte_zx296716_sdio.h     |    25 +
+ .../net/wireless/realtek/rtl8723ds/runwpa     |    20 +
+ .../net/wireless/realtek/rtl8723ds/wlan0dhcp  |    16 +
+ module_drivers/drivers/pinctrl/Kconfig        |    16 +
+ module_drivers/drivers/pinctrl/Makefile       |     3 +
+ module_drivers/drivers/pinctrl/multi-vgpio.c  |   168 +
+ .../drivers/pinctrl/pinctrl-ingenic.c         |  2056 ++
+ .../drivers/pinctrl/pinctrl-ingenic.h         |   370 +
+ module_drivers/drivers/power/Makefile         |     1 +
+ module_drivers/drivers/power/supply/Makefile  |     1 +
+ .../drivers/power/supply/axp_power/Kconfig    |    37 +
+ .../drivers/power/supply/axp_power/Makefile   |    12 +
+ .../power/supply/axp_power/axp-board.c        |   476 +
+ .../drivers/power/supply/axp_power/axp-cfg.h  |   344 +
+ .../power/supply/axp_power/axp-filenode.c     |   511 +
+ .../drivers/power/supply/axp_power/axp-gpio.c |   542 +
+ .../drivers/power/supply/axp_power/axp-gpio.h |    30 +
+ .../power/supply/axp_power/axp-mfd-216.h      |   191 +
+ .../drivers/power/supply/axp_power/axp-mfd.c  |   302 +
+ .../drivers/power/supply/axp_power/axp-mfd.h  |    95 +
+ .../drivers/power/supply/axp_power/axp-regu.c |   495 +
+ .../drivers/power/supply/axp_power/axp-regu.h |   186 +
+ .../drivers/power/supply/axp_power/axp-rw.c   |   142 +
+ .../drivers/power/supply/axp_power/axp-rw.h   |   209 +
+ .../drivers/power/supply/axp_power/axp-sply.c |  2297 ++
+ .../drivers/power/supply/axp_power/axp-sply.h |   180 +
+ .../power/supply/axp_power/axp-state.c        |   197 +
+ .../power/supply/axp_power/axp216-mfd.h       |   385 +
+ .../power/supply/axp_power/virtual216.c       |   472 +
+ .../power/supply/axp_power/virtual216_dev.c   |   157 +
+ module_drivers/drivers/pwm/Kconfig            |    36 +
+ module_drivers/drivers/pwm/Makefile           |     4 +
+ module_drivers/drivers/pwm/pwm-ingenic-v2.c   |   906 +
+ module_drivers/drivers/pwm/pwm-ingenic-v3.c   |  1273 +
+ module_drivers/drivers/pwm/pwm-ingenic.c      |   495 +
+ module_drivers/drivers/rtc/Kconfig            |    22 +
+ module_drivers/drivers/rtc/Makefile           |     1 +
+ module_drivers/drivers/rtc/rtc-ingenic.c      |   644 +
+ module_drivers/drivers/rtc/rtc-ingenic.h      |   141 +
+ module_drivers/drivers/spi/Kconfig            |    27 +
+ module_drivers/drivers/spi/Makefile           |     2 +
+ module_drivers/drivers/spi/ingenic_slv.c      |  1201 +
+ module_drivers/drivers/spi/ingenic_slv.h      |   564 +
+ module_drivers/drivers/spi/ingenic_spi.c      |  1505 ++
+ module_drivers/drivers/spi/ingenic_spi.h      |  1175 +
+ module_drivers/drivers/tty/Makefile           |     1 +
+ module_drivers/drivers/tty/serial/Kconfig     |    41 +
+ module_drivers/drivers/tty/serial/Makefile    |     1 +
+ .../drivers/tty/serial/ingenic_uart.c         |  1219 +
+ .../drivers/tty/serial/ingenic_uart.h         |   117 +
+ module_drivers/drivers/video/Makefile         |     6 +
+ module_drivers/drivers/video/fbdev/Makefile   |     1 +
+ .../drivers/video/fbdev/ingenic/Kconfig       |    60 +
+ .../drivers/video/fbdev/ingenic/Makefile      |     2 +
+ .../video/fbdev/ingenic/fb_stage/Kconfig      |    12 +
+ .../video/fbdev/ingenic/fb_stage/Makefile     |    12 +
+ .../video/fbdev/ingenic/fb_stage/README.md    |    59 +
+ .../fbdev/ingenic/fb_stage/displays/Kconfig   |   182 +
+ .../fbdev/ingenic/fb_stage/displays/Makefile  |    29 +
+ .../jd9365/JD9365_8001280init-4lane.txt       |   284 +
+ .../fb_stage/displays/jd9365/panel-jd9365.c   |   692 +
+ ...280_FP7721BX2_Column_G2.2_190613_Nolan.txt |   245 +
+ .../fb_stage/displays/jd9365d/panel-jd9365d.c |   725 +
+ .../fbdev/ingenic/fb_stage/displays/lt9211.c  |   585 +
+ .../fbdev/ingenic/fb_stage/displays/lt9211.h  |    62 +
+ .../fb_stage/displays/panel-G104X1L04.c       |  1124 +
+ .../fb_stage/displays/panel-MV238FHM-N30.c    |   416 +
+ .../ingenic/fb_stage/displays/panel-atk7016.c |   309 +
+ .../ingenic/fb_stage/displays/panel-bm8766.c  |   310 +
+ .../fb_stage/displays/panel-ek79007ad.c       |   462 +
+ .../ingenic/fb_stage/displays/panel-fw035.c   |   509 +
+ .../ingenic/fb_stage/displays/panel-fw040.c   |   644 +
+ .../ingenic/fb_stage/displays/panel-fw050.c   |   717 +
+ .../ingenic/fb_stage/displays/panel-gc9203.c  |   507 +
+ .../fb_stage/displays/panel-gwmtf16499b.c     |   304 +
+ .../ingenic/fb_stage/displays/panel-jd9161z.c |   528 +
+ .../ingenic/fb_stage/displays/panel-jd9366.c  |   749 +
+ .../fb_stage/displays/panel-kd035hvfbd037.c   |   563 +
+ .../fb_stage/displays/panel-kd035hvfmd057.c   |   472 +
+ .../fb_stage/displays/panel-kd050hdfia019.c   |   474 +
+ .../fb_stage/displays/panel-kd050hdfia020.c   |   724 +
+ .../fb_stage/displays/panel-kd050wvfpa029.c   |   307 +
+ .../ingenic/fb_stage/displays/panel-ma0060.c  |  1115 +
+ .../ingenic/fb_stage/displays/panel-st7282.c  |   271 +
+ .../fb_stage/displays/panel-st7701s-rgb666.c  |   976 +
+ .../ingenic/fb_stage/displays/panel-st7701s.c |   580 +
+ .../fb_stage/displays/panel-tl040hds01ct.c    |   373 +
+ .../fb_stage/displays/panel-tl040wvs03ct.c    |   736 +
+ .../ingenic/fb_stage/displays/panel-y88249.c  |   297 +
+ .../fb_stage/displays/panel-ylym286a.c        |   490 +
+ .../fb_stage/displays/panel-yts500xlai.c      |   494 +
+ ...T7701S_DX3.95IPS_mipi_480x480_V1.0-RGB.txt |   225 +
+ .../st7701s_dx3.95ips/panel-st7701sdx.c       |   497 +
+ .../video/fbdev/ingenic/fb_stage/dpu_ctrl.c   |  2005 ++
+ .../video/fbdev/ingenic/fb_stage/dpu_ctrl.h   |   196 +
+ .../fbdev/ingenic/fb_stage/dpu_dma_desc.h     |   183 +
+ .../video/fbdev/ingenic/fb_stage/dpu_reg.h    |   888 +
+ .../fbdev/ingenic/fb_stage/hw_composer.c      |   135 +
+ .../fbdev/ingenic/fb_stage/hw_composer.h      |    40 +
+ .../fbdev/ingenic/fb_stage/hw_composer_fb.c   |   871 +
+ .../fbdev/ingenic/fb_stage/hw_composer_fb.h   |    84 +
+ .../fbdev/ingenic/fb_stage/hw_composer_v4l2.c |   737 +
+ .../fbdev/ingenic/fb_stage/hw_composer_v4l2.h |    72 +
+ .../video/fbdev/ingenic/fb_stage/ingenicfb.c  |  1487 +
+ .../video/fbdev/ingenic/fb_stage/ingenicfb.h  |   144 +
+ .../video/fbdev/ingenic/fb_stage/jz_dsim.h    |   298 +
+ .../ingenic/fb_stage/jz_mipi_dsi/Makefile     |     1 +
+ .../fb_stage/jz_mipi_dsi/jz_mipi_dsi.c        |  1031 +
+ .../jz_mipi_dsi/jz_mipi_dsi_lowlevel.c        |   705 +
+ .../jz_mipi_dsi/jz_mipi_dsi_lowlevel.h        |    29 +
+ .../fb_stage/jz_mipi_dsi/jz_mipi_dsi_regs.h   |    79 +
+ .../fb_stage/jz_mipi_dsi/jz_mipi_dsih_hal.c   |  1302 +
+ .../fb_stage/jz_mipi_dsi/jz_mipi_dsih_hal.h   |   147 +
+ .../video/fbdev/ingenic/fb_stage/lcd_panel.h  |   156 +
+ .../video/fbdev/ingenic/fb_stage/sysfs.c      |   784 +
+ .../video/fbdev/ingenic/fb_stage/sysfs.h      |    45 +
+ .../fbdev/ingenic/fb_stage/todo/colorbar.c    |   247 +
+ .../video/fbdev/ingenic/fb_stage/todo/sysfs.c |  1259 +
+ .../fbdev/ingenic/fb_stage/uapi_ingenicfb.h   |   121 +
+ .../drivers/video/ingenic-nna/Kconfig         |     9 +
+ .../drivers/video/ingenic-nna/Makefile        |     5 +
+ .../video/ingenic-nna/mpsys-firmware/Makefile |     4 +
+ .../ingenic-nna/mpsys-firmware/mpsys-funcs.c  |   182 +
+ .../ingenic-nna/mpsys-firmware/mpsys-funcs.h  |    65 +
+ .../ingenic-nna/mpsys-firmware/mpsys_module.c |    52 +
+ .../drivers/video/ingenic-nna/soc_nna.c       |   883 +
+ .../drivers/video/ingenic-nna/soc_nna.h       |    65 +
+ .../video/ingenic-nna/soc_nna_common.h        |    24 +
+ .../drivers/video/ingenic-nna/soc_nna_hw.h    |    40 +
+ .../drivers/video/ingenic_avpu/Kconfig        |     9 +
+ .../drivers/video/ingenic_avpu/Makefile       |    19 +
+ .../drivers/video/ingenic_avpu/avpu_alloc.c   |    43 +
+ .../drivers/video/ingenic_avpu/avpu_alloc.h   |    15 +
+ .../video/ingenic_avpu/avpu_alloc_ioctl.c     |    92 +
+ .../video/ingenic_avpu/avpu_alloc_ioctl.h     |     8 +
+ .../drivers/video/ingenic_avpu/avpu_dmabuf.c  |   634 +
+ .../drivers/video/ingenic_avpu/avpu_dmabuf.h  |    13 +
+ .../drivers/video/ingenic_avpu/avpu_ioctl.h   |    22 +
+ .../drivers/video/ingenic_avpu/avpu_ip.c      |   144 +
+ .../drivers/video/ingenic_avpu/avpu_ip.h      |    84 +
+ .../drivers/video/ingenic_avpu/avpu_main.c    |   706 +
+ .../video/ingenic_avpu/avpu_no_dmabuf.c       |    21 +
+ .../drivers/video/ingenic_bscaler/Kconfig     |     4 +
+ .../drivers/video/ingenic_bscaler/Makefile    |     1 +
+ .../video/ingenic_bscaler/ingenic_bscaler.c   |   387 +
+ .../drivers/video/ingenic_ipu/Kconfig         |    18 +
+ .../drivers/video/ingenic_ipu/Makefile        |     2 +
+ .../video/ingenic_ipu/ingenic_drawbox.c       |   625 +
+ .../video/ingenic_ipu/ingenic_drawbox.h       |   161 +
+ .../video/ingenic_ipu/ingenic_ipu_v13.c       |  1206 +
+ .../video/ingenic_ipu/ingenic_ipu_v13.h       |   210 +
+ .../video/ingenic_ipu/ingenic_regs_v13.h      |   349 +
+ .../drivers/video/ingenic_ipu/ipu_dmabuf.c    |   702 +
+ .../drivers/video/ingenic_ipu/ipu_dmabuf.h    |    22 +
+ .../drivers/video/logo-ingenic/.gitignore     |     1 +
+ .../drivers/video/logo-ingenic/Kconfig        |    19 +
+ .../drivers/video/logo-ingenic/Makefile       |     4 +
+ .../drivers/video/logo-ingenic/logo.c         |   943 +
+ .../drivers/video/logo-ingenic/showlogo.c     |   133 +
+ module_drivers/drivers/watchdog/Kconfig       |    20 +
+ module_drivers/drivers/watchdog/Makefile      |     3 +
+ module_drivers/drivers/watchdog/ingenic_wdt.c |   328 +
+ module_drivers/drivers/watchdog/ingenic_wdt.h |    65 +
+ .../drivers/watchdog/ingenic_wdt_v1.c         |   601 +
+ module_drivers/drivers/watchdog/sgm820_wdt.c  |   107 +
+ module_drivers/dts/Makefile                   |    18 +
+ .../RD_X2000_HALLEY5_CAMERA_2V1.dtsi          |    83 +
+ .../RD_X2000_HALLEY5_CAMERA_3V2.dtsi          |    38 +
+ .../RD_X2000_HALLEY5_CAMERA_3V2_4LANE.dtsi    |    35 +
+ .../RD_X2000_HALLEY5_CAMERA_4V2.dtsi          |    83 +
+ .../RD_X2000_HALLEY5_CAMERA_4V3.dtsi          |    65 +
+ .../RD_X2000_HALLEY5_CAMERA_4V3_2KALE.dtsi    |    58 +
+ .../RD_X2000_HALLEY5_CAMERA_5V0.dtsi          |    38 +
+ .../RD_X2000_HALLEY5_CAMERA_cim.dtsi          |    70 +
+ module_drivers/dts/halley5_v20.dts            |   500 +
+ module_drivers/dts/halley5_v30.dts            |   556 +
+ .../RD_X1600_HALLEY6_DVP_CAMERA.dtsi          |    40 +
+ .../RD_X1600_HALLEY6_MIPI_CAMERA.dtsi         |    35 +
+ .../RD_X1600_HALLEY6_RGB_LCD_1V0.dtsi         |   117 +
+ .../RD_X1600_HALLEY6_RGB_SLCD_1V0.dtsi        |    64 +
+ .../RD_X1600_HALLEY6_RGB_SPI_LCD_1V0.dtsi     |   110 +
+ module_drivers/dts/halley6_v10.dts            |   396 +
+ module_drivers/dts/halley6_v20.dts            |   396 +
+ .../RD_X2000_HALLEY5_CAMERA_3V2.dtsi          |    34 +
+ .../RD_X2000_HALLEY5_CAMERA_4V3.dtsi          |    58 +
+ .../RD_X2500_HIPPO_CAMERA_1V0.dtsi            |   105 +
+ .../RD_X2500_HIPPO_CAMERA_1V1.dtsi            |    98 +
+ module_drivers/dts/hippo_cameras/ov2735a.dtsi |    35 +
+ module_drivers/dts/hippo_v10.dts              |   421 +
+ module_drivers/dts/hippo_v12.dts              |   431 +
+ module_drivers/dts/kale_v10.dts               |   574 +
+ module_drivers/dts/m300-pinctrl.dtsi          |   658 +
+ .../RD_X1600_PANDA_CAMERA_3V2.dtsi            |    38 +
+ .../RD_X1600_PANDA_DVP_CAMERA_1V0.dtsi        |    41 +
+ .../RD_X1600_PANDA_DVP_CAMERA_2V0.dtsi        |    40 +
+ ...RD_X1600_PANDA_DVP_CAMERA_AND_LCD_1V0.dtsi |    42 +
+ .../RD_X1600_PANDA_MIPI_CAMERA_1V0.dtsi       |    37 +
+ .../RD_X1600_PANDA_MIPI_CAMERA_2V0.dtsi       |    37 +
+ .../panda_lcd/RD_X1600_IRIS_RGB_LCD_1V0.dtsi  |    70 +
+ ...00_PANDA_LCD_AND_DVP_CAMERA_1V0_KD037.dtsi |    36 +
+ ...00_PANDA_LCD_AND_DVP_CAMERA_1V0_KD057.dtsi |    36 +
+ .../panda_lcd/RD_X1600_PANDA_RGB_LCD_1V0.dtsi |   124 +
+ .../panda_lcd/RD_X1600_PANDA_SPI_LCD_1V0.dtsi |    36 +
+ module_drivers/dts/panda_v10.dts              |   423 +
+ module_drivers/dts/viomi_v2000.dts            |   583 +
+ module_drivers/dts/x1600-pinctrl.dtsi         |   380 +
+ module_drivers/dts/x1600.dtsi                 |   523 +
+ module_drivers/dts/x1600_module_base.dts      |   154 +
+ module_drivers/dts/x2000-pinctrl.dtsi         |   651 +
+ module_drivers/dts/x2000.dtsi                 |   800 +
+ .../dts/x2000_lifesmart_480p_harmony.dts      |   423 +
+ module_drivers/dts/x2000_module_base.dts      |   194 +
+ module_drivers/dts/x2500-pinctrl.dtsi         |   297 +
+ module_drivers/dts/x2500.dtsi                 |   744 +
+ module_drivers/sound/Makefile                 |     1 +
+ module_drivers/sound/soc/Makefile             |     1 +
+ module_drivers/sound/soc/ingenic/Kconfig      |   329 +
+ module_drivers/sound/soc/ingenic/Makefile     |     8 +
+ module_drivers/sound/soc/ingenic/README       |    31 +
+ .../sound/soc/ingenic/as-v1/Makefile          |     9 +
+ .../sound/soc/ingenic/as-v1/asoc-aic.c        |   430 +
+ .../sound/soc/ingenic/as-v1/asoc-aic.h        |   793 +
+ .../sound/soc/ingenic/as-v1/asoc-dma.c        |   744 +
+ .../sound/soc/ingenic/as-v1/asoc-dma.h        |    31 +
+ .../sound/soc/ingenic/as-v1/asoc-dmic.c       |   540 +
+ .../sound/soc/ingenic/as-v1/asoc-dmic.h       |   301 +
+ .../sound/soc/ingenic/as-v1/asoc-i2s-tloop.c  |   331 +
+ .../sound/soc/ingenic/as-v1/asoc-i2s.c        |   637 +
+ .../sound/soc/ingenic/as-v1/asoc-pcm.c        |   417 +
+ .../sound/soc/ingenic/as-v1/asoc-pcm.h        |   253 +
+ .../sound/soc/ingenic/as-v1/asoc-spdif.c      |   490 +
+ .../sound/soc/ingenic/as-v1/assert.h          |    16 +
+ .../sound/soc/ingenic/as-v2/Makefile          |    17 +
+ .../sound/soc/ingenic/as-v2/as-baic.c         |   919 +
+ .../sound/soc/ingenic/as-v2/as-baic.h         |   175 +
+ .../sound/soc/ingenic/as-v2/as-dma.c          |   967 +
+ .../sound/soc/ingenic/as-v2/as-dma.h          |   205 +
+ .../sound/soc/ingenic/as-v2/as-dmic.c         |   309 +
+ .../sound/soc/ingenic/as-v2/as-dmic.h         |    64 +
+ .../sound/soc/ingenic/as-v2/as-dsp.c          |   585 +
+ .../sound/soc/ingenic/as-v2/as-dsp.h          |   150 +
+ .../sound/soc/ingenic/as-v2/as-fmtcov.c       |   187 +
+ .../sound/soc/ingenic/as-v2/as-fmtcov.h       |    57 +
+ .../sound/soc/ingenic/as-v2/as-mixer.c        |   186 +
+ .../sound/soc/ingenic/as-v2/as-mixer.h        |    50 +
+ .../sound/soc/ingenic/as-v2/as-spdif.c        |   445 +
+ .../sound/soc/ingenic/as-v2/as-spdif.h        |    99 +
+ .../sound/soc/ingenic/as-v2/as-vir-fe.c       |   148 +
+ .../sound/soc/ingenic/boards/Makefile         |    19 +
+ .../sound/soc/ingenic/boards/gewu.c           |   547 +
+ .../sound/soc/ingenic/boards/halley5_v20.c    |   624 +
+ .../sound/soc/ingenic/boards/halley6.c        |   225 +
+ .../sound/soc/ingenic/boards/hippo-board.c    |   258 +
+ .../sound/soc/ingenic/boards/kale_v10.c       |   624 +
+ .../sound/soc/ingenic/boards/panda.c          |   242 +
+ .../sound/soc/ingenic/ecodec/Kconfig          |    37 +
+ .../sound/soc/ingenic/ecodec/Makefile         |     5 +
+ .../sound/soc/ingenic/ecodec/ak4458.c         |   685 +
+ .../sound/soc/ingenic/ecodec/ak4458.h         |    88 +
+ .../sound/soc/ingenic/ecodec/ak5558.c         |   425 +
+ .../sound/soc/ingenic/ecodec/ak5558.h         |    52 +
+ .../sound/soc/ingenic/ecodec/nau8822.c        |  1179 +
+ .../sound/soc/ingenic/ecodec/nau8822.h        |   161 +
+ .../sound/soc/ingenic/ecodec/wm8594.c         |  1177 +
+ .../sound/soc/ingenic/ecodec/wm8594.h         |    64 +
+ .../sound/soc/ingenic/icodec/Makefile         |     6 +
+ .../sound/soc/ingenic/icodec/dump.c           |   119 +
+ .../sound/soc/ingenic/icodec/icdc_d3.c        |   762 +
+ .../sound/soc/ingenic/icodec/icdc_d3.h        |   407 +
+ .../sound/soc/ingenic/icodec/icdc_inno.c      |   906 +
+ .../sound/soc/ingenic/icodec/icdc_inno_v2.c   |  1239 +
+ net/wireless/core.c                           |     3 +-
+ scripts/Makefile                              |     3 +-
+ scripts/Makefile.lib                          |     4 +
+ .../pic2logo-include/stb_image/stb_image.h    |  7464 +++++
+ .../stb_image/stb_image_resize.h              |  2627 ++
+ .../stb_image/stb_image_write.h               |  1568 ++
+ scripts/pic2logo.c                            |   147 +
+ 1924 files changed, 1156993 insertions(+), 2123 deletions(-)
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+ create mode 100644 arch/mips/xburst/Kconfig
+ create mode 100644 arch/mips/xburst/Makefile
+ create mode 100644 arch/mips/xburst/Platform
+ create mode 100644 arch/mips/xburst/common/Makefile
+ create mode 100644 arch/mips/xburst/common/include/ingenic_proc.h
+ create mode 100644 arch/mips/xburst/common/include/jz_notifier.h
+ create mode 100755 arch/mips/xburst/common/include/mxu.h
+ create mode 100755 arch/mips/xburst/common/include/mxu_media.h
+ create mode 100644 arch/mips/xburst/common/include/mxuv3.h
+ create mode 100644 arch/mips/xburst/common/initrd-check.c
+ create mode 100644 arch/mips/xburst/common/jz_notifier.c
+ create mode 100644 arch/mips/xburst/common/mxu-xburst.c
+ create mode 100644 arch/mips/xburst/common/proc.c
+ create mode 100644 arch/mips/xburst/common/prom.c
+ create mode 100644 arch/mips/xburst/common/sc-xburst.c
+ create mode 100644 arch/mips/xburst/debug/Makefile
+ create mode 100644 arch/mips/xburst/debug/trace-exit.c
+ create mode 100644 arch/mips/xburst/soc-x1000/Kconfig.DT
+ create mode 100644 arch/mips/xburst/soc-x1000/Makefile
+ create mode 100644 arch/mips/xburst/soc-x1000/early_printk.c
+ create mode 100644 arch/mips/xburst/soc-x1000/include/cpu-feature-overrides.h
+ create mode 100644 arch/mips/xburst/soc-x1000/include/irq.h
+ create mode 100644 arch/mips/xburst/soc-x1000/include/soc/base.h
+ create mode 100644 arch/mips/xburst/soc-x1000/include/soc/cache.h
+ create mode 100644 arch/mips/xburst/soc-x1000/include/soc/cpm.h
+ create mode 100644 arch/mips/xburst/soc-x1000/include/soc/ost.h
+ create mode 100644 arch/mips/xburst/soc-x1000/include/soc/sfc.h
+ create mode 100644 arch/mips/xburst/soc-x1000/include/soc/tcsm_layout.h
+ create mode 100644 arch/mips/xburst/soc-x1000/include/soc/tcu.h
+ create mode 100644 arch/mips/xburst/soc-x1000/include/war.h
+ create mode 100644 arch/mips/xburst/soc-x1000/pm.c
+ create mode 100644 arch/mips/xburst/soc-x1000/regs_save_restore.S
+ create mode 100644 arch/mips/xburst/soc-x1000/setup.c
+ create mode 100644 arch/mips/xburst/soc-x1000/socid.c
+ create mode 100644 arch/mips/xburst/soc-x1600/Kconfig.DT
+ create mode 100644 arch/mips/xburst/soc-x1600/Makefile
+ create mode 100644 arch/mips/xburst/soc-x1600/early_printk.c
+ create mode 100644 arch/mips/xburst/soc-x1600/gpio.c
+ create mode 100644 arch/mips/xburst/soc-x1600/include/cpu-feature-overrides.h
+ create mode 100644 arch/mips/xburst/soc-x1600/include/irq.h
+ create mode 100644 arch/mips/xburst/soc-x1600/include/libdmmu.h
+ create mode 100644 arch/mips/xburst/soc-x1600/include/soc/base.h
+ create mode 100644 arch/mips/xburst/soc-x1600/include/soc/cache.h
+ create mode 100644 arch/mips/xburst/soc-x1600/include/soc/cpm.h
+ create mode 100644 arch/mips/xburst/soc-x1600/include/soc/ddr.h
+ create mode 100644 arch/mips/xburst/soc-x1600/include/soc/efuse.h
+ create mode 100644 arch/mips/xburst/soc-x1600/include/soc/gpio.h
+ create mode 100644 arch/mips/xburst/soc-x1600/include/soc/ost.h
+ create mode 100644 arch/mips/xburst/soc-x1600/include/soc/sfc.h
+ create mode 100644 arch/mips/xburst/soc-x1600/include/soc/tcsm_layout.h
+ create mode 100644 arch/mips/xburst/soc-x1600/include/soc/tcu.h
+ create mode 100644 arch/mips/xburst/soc-x1600/include/war.h
+ create mode 100644 arch/mips/xburst/soc-x1600/libdmmu.c
+ create mode 100644 arch/mips/xburst/soc-x1600/pm.c
+ create mode 100644 arch/mips/xburst/soc-x1600/pm.h
+ create mode 100644 arch/mips/xburst/soc-x1600/regs_save_restore.S
+ create mode 100755 arch/mips/xburst/soc-x1600/regs_save_restore.py
+ create mode 100644 arch/mips/xburst/soc-x1600/setup.c
+ create mode 100644 arch/mips/xburst2/Kconfig
+ create mode 100644 arch/mips/xburst2/Makefile
+ create mode 100644 arch/mips/xburst2/Platform
+ create mode 100644 arch/mips/xburst2/common/Makefile
+ create mode 100644 arch/mips/xburst2/common/cpu_ddr_test/Makefile
+ create mode 100644 arch/mips/xburst2/common/cpu_ddr_test/cpu_ccu_test.c
+ create mode 100644 arch/mips/xburst2/common/cpu_ddr_test/cpu_dma_test.c
+ create mode 100644 arch/mips/xburst2/common/cpu_ddr_test/cpu_spinlock_test.c
+ create mode 100644 arch/mips/xburst2/common/cpu_ddr_test/cpu_tcsm.h
+ create mode 100644 arch/mips/xburst2/common/cpu_ddr_test/cpu_watch_test.c
+ create mode 100644 arch/mips/xburst2/common/cpu_ddr_test/ddr_bandwidth_monitor.c
+ create mode 100644 arch/mips/xburst2/common/cpu_ddr_test/ddr_change_freq.c
+ create mode 100644 arch/mips/xburst2/common/cpu_ddr_test/l2c_test.c
+ create mode 100644 arch/mips/xburst2/common/cpu_ddr_test/multithread_test.c
+ create mode 100644 arch/mips/xburst2/common/cpu_ddr_test/multithread_test.h
+ create mode 100644 arch/mips/xburst2/common/cpu_ddr_test/raw_dma_test.c
+ create mode 100644 arch/mips/xburst2/common/get-cpu-features.c
+ create mode 100644 arch/mips/xburst2/common/initrd-check.c
+ create mode 100644 arch/mips/xburst2/common/mxuv3.c
+ create mode 100644 arch/mips/xburst2/common/proc.c
+ create mode 100644 arch/mips/xburst2/core/Makefile
+ create mode 100644 arch/mips/xburst2/core/include/ccu.h
+ create mode 100644 arch/mips/xburst2/core/include/core_base.h
+ create mode 100644 arch/mips/xburst2/core/include/ingenic_proc.h
+ create mode 100644 arch/mips/xburst2/core/include/irq_cpu.h
+ create mode 100755 arch/mips/xburst2/core/include/mxu.h
+ create mode 100644 arch/mips/xburst2/core/include/mxuv3.h
+ create mode 100644 arch/mips/xburst2/core/prom.c
+ create mode 100644 arch/mips/xburst2/core/sc.c
+ create mode 100644 arch/mips/xburst2/core/smp.c
+ create mode 100644 arch/mips/xburst2/soc-m300/Kconfig.DT
+ create mode 100644 arch/mips/xburst2/soc-m300/Makefile
+ create mode 100644 arch/mips/xburst2/soc-m300/include/cpu-feature-overrides.h
+ create mode 100644 arch/mips/xburst2/soc-m300/include/irq.h
+ create mode 100644 arch/mips/xburst2/soc-m300/include/libdmmu.h
+ create mode 100644 arch/mips/xburst2/soc-m300/include/soc/base.h
+ create mode 100644 arch/mips/xburst2/soc-m300/include/soc/cache.h
+ create mode 100644 arch/mips/xburst2/soc-m300/include/soc/cpm.h
+ create mode 100644 arch/mips/xburst2/soc-m300/include/soc/ddr.h
+ create mode 100644 arch/mips/xburst2/soc-m300/include/soc/extal.h
+ create mode 100644 arch/mips/xburst2/soc-m300/include/soc/rtc.h
+ create mode 100644 arch/mips/xburst2/soc-m300/include/soc/sfc.h
+ create mode 100644 arch/mips/xburst2/soc-m300/include/soc/tcsm_layout.h
+ create mode 100644 arch/mips/xburst2/soc-m300/include/war.h
+ create mode 100644 arch/mips/xburst2/soc-m300/libdmmu.c
+ create mode 100644 arch/mips/xburst2/soc-m300/pm.c
+ create mode 100644 arch/mips/xburst2/soc-m300/pm.h
+ create mode 100644 arch/mips/xburst2/soc-m300/pm_fastboot.c
+ create mode 100644 arch/mips/xburst2/soc-m300/pm_fastboot.h
+ create mode 100644 arch/mips/xburst2/soc-m300/pm_sleep.c
+ create mode 100644 arch/mips/xburst2/soc-m300/pm_sleep.h
+ create mode 100644 arch/mips/xburst2/soc-m300/regs_save_restore.S
+ create mode 100755 arch/mips/xburst2/soc-m300/regs_save_restore.py
+ create mode 100644 arch/mips/xburst2/soc-m300/reset.c
+ create mode 100644 arch/mips/xburst2/soc-m300/serial.c
+ create mode 100644 arch/mips/xburst2/soc-m300/setup.c
+ create mode 100644 arch/mips/xburst2/soc-m300/sleep_firmware/Makefile
+ create mode 100644 arch/mips/xburst2/soc-m300/sleep_firmware/Readme
+ create mode 100644 arch/mips/xburst2/soc-m300/sleep_firmware/include/base.h
+ create mode 100755 arch/mips/xburst2/soc-m300/sleep_firmware/include/cpm.h
+ create mode 100644 arch/mips/xburst2/soc-m300/sleep_firmware/include/ddr.h
+ create mode 100755 arch/mips/xburst2/soc-m300/sleep_firmware/include/gpio.h
+ create mode 100644 arch/mips/xburst2/soc-m300/sleep_firmware/include/pm_fastboot.h
+ create mode 100755 arch/mips/xburst2/soc-m300/sleep_firmware/include/uart.h
+ create mode 100755 arch/mips/xburst2/soc-m300/sleep_firmware/mkmodule.sh
+ create mode 100644 arch/mips/xburst2/soc-m300/sleep_firmware/src/fastboot_resume.c
+ create mode 100644 arch/mips/xburst2/soc-m300/sleep_firmware/src/uart.c
+ create mode 100644 arch/mips/xburst2/soc-m300/sleep_firmware/target.ld
+ create mode 100644 arch/mips/xburst2/soc-x2000/Kconfig.DT
+ create mode 100644 arch/mips/xburst2/soc-x2000/Makefile
+ create mode 100644 arch/mips/xburst2/soc-x2000/gpio.c
+ create mode 100644 arch/mips/xburst2/soc-x2000/include/cpu-feature-overrides.h
+ create mode 100644 arch/mips/xburst2/soc-x2000/include/irq.h
+ create mode 100644 arch/mips/xburst2/soc-x2000/include/libdmmu.h
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+ create mode 100644 arch/mips/xburst2/soc-x2000/include/soc/cache.h
+ create mode 100644 arch/mips/xburst2/soc-x2000/include/soc/cpm.h
+ create mode 100644 arch/mips/xburst2/soc-x2000/include/soc/ddr.h
+ create mode 100644 arch/mips/xburst2/soc-x2000/include/soc/efuse.h
+ create mode 100644 arch/mips/xburst2/soc-x2000/include/soc/extal.h
+ create mode 100644 arch/mips/xburst2/soc-x2000/include/soc/gpio.h
+ create mode 100644 arch/mips/xburst2/soc-x2000/include/soc/rtc.h
+ create mode 100644 arch/mips/xburst2/soc-x2000/include/soc/sfc.h
+ create mode 100644 arch/mips/xburst2/soc-x2000/include/soc/tcsm_layout.h
+ create mode 100644 arch/mips/xburst2/soc-x2000/include/war.h
+ create mode 100644 arch/mips/xburst2/soc-x2000/libdmmu.c
+ create mode 100644 arch/mips/xburst2/soc-x2000/pm.c
+ create mode 100644 arch/mips/xburst2/soc-x2000/pm.h
+ create mode 100644 arch/mips/xburst2/soc-x2000/pm_fastboot.c
+ create mode 100644 arch/mips/xburst2/soc-x2000/pm_fastboot.h
+ create mode 100644 arch/mips/xburst2/soc-x2000/regs_save_restore.S
+ create mode 100755 arch/mips/xburst2/soc-x2000/regs_save_restore.py
+ create mode 100644 arch/mips/xburst2/soc-x2000/reset.c
+ create mode 100644 arch/mips/xburst2/soc-x2000/serial.c
+ create mode 100644 arch/mips/xburst2/soc-x2000/setup.c
+ create mode 100644 arch/mips/xburst2/soc-x2000/sleep_firmware/Makefile
+ create mode 100644 arch/mips/xburst2/soc-x2000/sleep_firmware/Readme
+ create mode 100644 arch/mips/xburst2/soc-x2000/sleep_firmware/include/base.h
+ create mode 100755 arch/mips/xburst2/soc-x2000/sleep_firmware/include/cpm.h
+ create mode 100644 arch/mips/xburst2/soc-x2000/sleep_firmware/include/ddr.h
+ create mode 100755 arch/mips/xburst2/soc-x2000/sleep_firmware/include/gpio.h
+ create mode 100644 arch/mips/xburst2/soc-x2000/sleep_firmware/include/pm_fastboot.h
+ create mode 100755 arch/mips/xburst2/soc-x2000/sleep_firmware/include/uart.h
+ create mode 100755 arch/mips/xburst2/soc-x2000/sleep_firmware/mkmodule.sh
+ create mode 100644 arch/mips/xburst2/soc-x2000/sleep_firmware/src/fastboot_resume.c
+ create mode 100644 arch/mips/xburst2/soc-x2000/sleep_firmware/src/uart.c
+ create mode 100644 arch/mips/xburst2/soc-x2000/sleep_firmware/target.ld
+ create mode 100644 arch/mips/xburst2/soc-x2000/sleep_firmware/tmp.map
+ create mode 100644 arch/mips/xburst2/soc-x2500/Kconfig.DT
+ create mode 100644 arch/mips/xburst2/soc-x2500/Makefile
+ create mode 100644 arch/mips/xburst2/soc-x2500/gpio.c
+ create mode 100644 arch/mips/xburst2/soc-x2500/include/cpu-feature-overrides.h
+ create mode 100644 arch/mips/xburst2/soc-x2500/include/irq.h
+ create mode 100644 arch/mips/xburst2/soc-x2500/include/libdmmu.h
+ create mode 100644 arch/mips/xburst2/soc-x2500/include/soc/base.h
+ create mode 100644 arch/mips/xburst2/soc-x2500/include/soc/cache.h
+ create mode 100644 arch/mips/xburst2/soc-x2500/include/soc/cpm.h
+ create mode 100644 arch/mips/xburst2/soc-x2500/include/soc/ddr.h
+ create mode 100644 arch/mips/xburst2/soc-x2500/include/soc/extal.h
+ create mode 100644 arch/mips/xburst2/soc-x2500/include/soc/gpio.h
+ create mode 100644 arch/mips/xburst2/soc-x2500/include/soc/mmc.h
+ create mode 100644 arch/mips/xburst2/soc-x2500/include/soc/pdma.h
+ create mode 100644 arch/mips/xburst2/soc-x2500/include/soc/rtc.h
+ create mode 100644 arch/mips/xburst2/soc-x2500/include/soc/sfc.h
+ create mode 100644 arch/mips/xburst2/soc-x2500/include/soc/tcsm_layout.h
+ create mode 100644 arch/mips/xburst2/soc-x2500/include/war.h
+ create mode 100644 arch/mips/xburst2/soc-x2500/libdmmu.c
+ create mode 100644 arch/mips/xburst2/soc-x2500/pm.c
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+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-ek79007ad.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-fw035.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-fw040.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-fw050.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-gc9203.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-gwmtf16499b.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-jd9161z.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-jd9366.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd035hvfbd037.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd035hvfmd057.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd050hdfia019.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd050hdfia020.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd050wvfpa029.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-ma0060.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-st7282.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-st7701s-rgb666.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-st7701s.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-tl040hds01ct.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-tl040wvs03ct.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-y88249.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-ylym286a.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-yts500xlai.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/st7701s_dx3.95ips/ST7701S_DX3.95IPS_mipi_480x480_V1.0-RGB.txt
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/st7701s_dx3.95ips/panel-st7701sdx.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/dpu_ctrl.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/dpu_ctrl.h
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/dpu_dma_desc.h
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/dpu_reg.h
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer.h
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer_fb.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer_fb.h
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer_v4l2.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer_v4l2.h
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/ingenicfb.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/ingenicfb.h
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_dsim.h
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/Makefile
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsi.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsi_lowlevel.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsi_lowlevel.h
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsi_regs.h
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsih_hal.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsih_hal.h
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/lcd_panel.h
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/sysfs.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/sysfs.h
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/todo/colorbar.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/todo/sysfs.c
+ create mode 100644 module_drivers/drivers/video/fbdev/ingenic/fb_stage/uapi_ingenicfb.h
+ create mode 100644 module_drivers/drivers/video/ingenic-nna/Kconfig
+ create mode 100644 module_drivers/drivers/video/ingenic-nna/Makefile
+ create mode 100644 module_drivers/drivers/video/ingenic-nna/mpsys-firmware/Makefile
+ create mode 100755 module_drivers/drivers/video/ingenic-nna/mpsys-firmware/mpsys-funcs.c
+ create mode 100755 module_drivers/drivers/video/ingenic-nna/mpsys-firmware/mpsys-funcs.h
+ create mode 100755 module_drivers/drivers/video/ingenic-nna/mpsys-firmware/mpsys_module.c
+ create mode 100644 module_drivers/drivers/video/ingenic-nna/soc_nna.c
+ create mode 100644 module_drivers/drivers/video/ingenic-nna/soc_nna.h
+ create mode 100644 module_drivers/drivers/video/ingenic-nna/soc_nna_common.h
+ create mode 100644 module_drivers/drivers/video/ingenic-nna/soc_nna_hw.h
+ create mode 100644 module_drivers/drivers/video/ingenic_avpu/Kconfig
+ create mode 100644 module_drivers/drivers/video/ingenic_avpu/Makefile
+ create mode 100644 module_drivers/drivers/video/ingenic_avpu/avpu_alloc.c
+ create mode 100644 module_drivers/drivers/video/ingenic_avpu/avpu_alloc.h
+ create mode 100644 module_drivers/drivers/video/ingenic_avpu/avpu_alloc_ioctl.c
+ create mode 100644 module_drivers/drivers/video/ingenic_avpu/avpu_alloc_ioctl.h
+ create mode 100644 module_drivers/drivers/video/ingenic_avpu/avpu_dmabuf.c
+ create mode 100644 module_drivers/drivers/video/ingenic_avpu/avpu_dmabuf.h
+ create mode 100644 module_drivers/drivers/video/ingenic_avpu/avpu_ioctl.h
+ create mode 100644 module_drivers/drivers/video/ingenic_avpu/avpu_ip.c
+ create mode 100644 module_drivers/drivers/video/ingenic_avpu/avpu_ip.h
+ create mode 100644 module_drivers/drivers/video/ingenic_avpu/avpu_main.c
+ create mode 100644 module_drivers/drivers/video/ingenic_avpu/avpu_no_dmabuf.c
+ create mode 100644 module_drivers/drivers/video/ingenic_bscaler/Kconfig
+ create mode 100644 module_drivers/drivers/video/ingenic_bscaler/Makefile
+ create mode 100644 module_drivers/drivers/video/ingenic_bscaler/ingenic_bscaler.c
+ create mode 100644 module_drivers/drivers/video/ingenic_ipu/Kconfig
+ create mode 100644 module_drivers/drivers/video/ingenic_ipu/Makefile
+ create mode 100644 module_drivers/drivers/video/ingenic_ipu/ingenic_drawbox.c
+ create mode 100644 module_drivers/drivers/video/ingenic_ipu/ingenic_drawbox.h
+ create mode 100644 module_drivers/drivers/video/ingenic_ipu/ingenic_ipu_v13.c
+ create mode 100644 module_drivers/drivers/video/ingenic_ipu/ingenic_ipu_v13.h
+ create mode 100644 module_drivers/drivers/video/ingenic_ipu/ingenic_regs_v13.h
+ create mode 100644 module_drivers/drivers/video/ingenic_ipu/ipu_dmabuf.c
+ create mode 100644 module_drivers/drivers/video/ingenic_ipu/ipu_dmabuf.h
+ create mode 100644 module_drivers/drivers/video/logo-ingenic/.gitignore
+ create mode 100644 module_drivers/drivers/video/logo-ingenic/Kconfig
+ create mode 100644 module_drivers/drivers/video/logo-ingenic/Makefile
+ create mode 100644 module_drivers/drivers/video/logo-ingenic/logo.c
+ create mode 100644 module_drivers/drivers/video/logo-ingenic/showlogo.c
+ create mode 100644 module_drivers/drivers/watchdog/Kconfig
+ create mode 100644 module_drivers/drivers/watchdog/Makefile
+ create mode 100644 module_drivers/drivers/watchdog/ingenic_wdt.c
+ create mode 100644 module_drivers/drivers/watchdog/ingenic_wdt.h
+ create mode 100644 module_drivers/drivers/watchdog/ingenic_wdt_v1.c
+ create mode 100644 module_drivers/drivers/watchdog/sgm820_wdt.c
+ create mode 100644 module_drivers/dts/Makefile
+ create mode 100644 module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_2V1.dtsi
+ create mode 100644 module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_3V2.dtsi
+ create mode 100644 module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_3V2_4LANE.dtsi
+ create mode 100644 module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_4V2.dtsi
+ create mode 100644 module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_4V3.dtsi
+ create mode 100644 module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_4V3_2KALE.dtsi
+ create mode 100644 module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_5V0.dtsi
+ create mode 100644 module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_cim.dtsi
+ create mode 100644 module_drivers/dts/halley5_v20.dts
+ create mode 100644 module_drivers/dts/halley5_v30.dts
+ create mode 100644 module_drivers/dts/halley6_cameras/RD_X1600_HALLEY6_DVP_CAMERA.dtsi
+ create mode 100644 module_drivers/dts/halley6_cameras/RD_X1600_HALLEY6_MIPI_CAMERA.dtsi
+ create mode 100644 module_drivers/dts/halley6_lcd/RD_X1600_HALLEY6_RGB_LCD_1V0.dtsi
+ create mode 100644 module_drivers/dts/halley6_lcd/RD_X1600_HALLEY6_RGB_SLCD_1V0.dtsi
+ create mode 100644 module_drivers/dts/halley6_lcd/RD_X1600_HALLEY6_RGB_SPI_LCD_1V0.dtsi
+ create mode 100644 module_drivers/dts/halley6_v10.dts
+ create mode 100644 module_drivers/dts/halley6_v20.dts
+ create mode 100644 module_drivers/dts/hippo_cameras/RD_X2000_HALLEY5_CAMERA_3V2.dtsi
+ create mode 100644 module_drivers/dts/hippo_cameras/RD_X2000_HALLEY5_CAMERA_4V3.dtsi
+ create mode 100644 module_drivers/dts/hippo_cameras/RD_X2500_HIPPO_CAMERA_1V0.dtsi
+ create mode 100644 module_drivers/dts/hippo_cameras/RD_X2500_HIPPO_CAMERA_1V1.dtsi
+ create mode 100644 module_drivers/dts/hippo_cameras/ov2735a.dtsi
+ create mode 100644 module_drivers/dts/hippo_v10.dts
+ create mode 100644 module_drivers/dts/hippo_v12.dts
+ create mode 100644 module_drivers/dts/kale_v10.dts
+ create mode 100644 module_drivers/dts/m300-pinctrl.dtsi
+ create mode 100644 module_drivers/dts/panda_cameras/RD_X1600_PANDA_CAMERA_3V2.dtsi
+ create mode 100644 module_drivers/dts/panda_cameras/RD_X1600_PANDA_DVP_CAMERA_1V0.dtsi
+ create mode 100644 module_drivers/dts/panda_cameras/RD_X1600_PANDA_DVP_CAMERA_2V0.dtsi
+ create mode 100644 module_drivers/dts/panda_cameras/RD_X1600_PANDA_DVP_CAMERA_AND_LCD_1V0.dtsi
+ create mode 100644 module_drivers/dts/panda_cameras/RD_X1600_PANDA_MIPI_CAMERA_1V0.dtsi
+ create mode 100644 module_drivers/dts/panda_cameras/RD_X1600_PANDA_MIPI_CAMERA_2V0.dtsi
+ create mode 100644 module_drivers/dts/panda_lcd/RD_X1600_IRIS_RGB_LCD_1V0.dtsi
+ create mode 100644 module_drivers/dts/panda_lcd/RD_X1600_PANDA_LCD_AND_DVP_CAMERA_1V0_KD037.dtsi
+ create mode 100644 module_drivers/dts/panda_lcd/RD_X1600_PANDA_LCD_AND_DVP_CAMERA_1V0_KD057.dtsi
+ create mode 100644 module_drivers/dts/panda_lcd/RD_X1600_PANDA_RGB_LCD_1V0.dtsi
+ create mode 100644 module_drivers/dts/panda_lcd/RD_X1600_PANDA_SPI_LCD_1V0.dtsi
+ create mode 100644 module_drivers/dts/panda_v10.dts
+ create mode 100644 module_drivers/dts/viomi_v2000.dts
+ create mode 100644 module_drivers/dts/x1600-pinctrl.dtsi
+ create mode 100644 module_drivers/dts/x1600.dtsi
+ create mode 100644 module_drivers/dts/x1600_module_base.dts
+ create mode 100644 module_drivers/dts/x2000-pinctrl.dtsi
+ create mode 100644 module_drivers/dts/x2000.dtsi
+ create mode 100644 module_drivers/dts/x2000_lifesmart_480p_harmony.dts
+ create mode 100644 module_drivers/dts/x2000_module_base.dts
+ create mode 100644 module_drivers/dts/x2500-pinctrl.dtsi
+ create mode 100644 module_drivers/dts/x2500.dtsi
+ create mode 100644 module_drivers/sound/Makefile
+ create mode 100644 module_drivers/sound/soc/Makefile
+ create mode 100644 module_drivers/sound/soc/ingenic/Kconfig
+ create mode 100644 module_drivers/sound/soc/ingenic/Makefile
+ create mode 100644 module_drivers/sound/soc/ingenic/README
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v1/Makefile
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v1/asoc-aic.c
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v1/asoc-aic.h
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v1/asoc-dma.c
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v1/asoc-dma.h
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v1/asoc-dmic.c
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v1/asoc-dmic.h
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v1/asoc-i2s-tloop.c
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v1/asoc-i2s.c
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v1/asoc-pcm.c
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v1/asoc-pcm.h
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v1/asoc-spdif.c
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v1/assert.h
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v2/Makefile
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v2/as-baic.c
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v2/as-baic.h
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v2/as-dma.c
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v2/as-dma.h
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v2/as-dmic.c
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v2/as-dmic.h
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v2/as-dsp.c
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v2/as-dsp.h
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v2/as-fmtcov.c
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v2/as-fmtcov.h
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v2/as-mixer.c
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v2/as-mixer.h
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v2/as-spdif.c
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v2/as-spdif.h
+ create mode 100644 module_drivers/sound/soc/ingenic/as-v2/as-vir-fe.c
+ create mode 100644 module_drivers/sound/soc/ingenic/boards/Makefile
+ create mode 100644 module_drivers/sound/soc/ingenic/boards/gewu.c
+ create mode 100644 module_drivers/sound/soc/ingenic/boards/halley5_v20.c
+ create mode 100644 module_drivers/sound/soc/ingenic/boards/halley6.c
+ create mode 100644 module_drivers/sound/soc/ingenic/boards/hippo-board.c
+ create mode 100644 module_drivers/sound/soc/ingenic/boards/kale_v10.c
+ create mode 100644 module_drivers/sound/soc/ingenic/boards/panda.c
+ create mode 100644 module_drivers/sound/soc/ingenic/ecodec/Kconfig
+ create mode 100644 module_drivers/sound/soc/ingenic/ecodec/Makefile
+ create mode 100644 module_drivers/sound/soc/ingenic/ecodec/ak4458.c
+ create mode 100644 module_drivers/sound/soc/ingenic/ecodec/ak4458.h
+ create mode 100644 module_drivers/sound/soc/ingenic/ecodec/ak5558.c
+ create mode 100644 module_drivers/sound/soc/ingenic/ecodec/ak5558.h
+ create mode 100644 module_drivers/sound/soc/ingenic/ecodec/nau8822.c
+ create mode 100644 module_drivers/sound/soc/ingenic/ecodec/nau8822.h
+ create mode 100644 module_drivers/sound/soc/ingenic/ecodec/wm8594.c
+ create mode 100644 module_drivers/sound/soc/ingenic/ecodec/wm8594.h
+ create mode 100644 module_drivers/sound/soc/ingenic/icodec/Makefile
+ create mode 100644 module_drivers/sound/soc/ingenic/icodec/dump.c
+ create mode 100644 module_drivers/sound/soc/ingenic/icodec/icdc_d3.c
+ create mode 100644 module_drivers/sound/soc/ingenic/icodec/icdc_d3.h
+ create mode 100644 module_drivers/sound/soc/ingenic/icodec/icdc_inno.c
+ create mode 100644 module_drivers/sound/soc/ingenic/icodec/icdc_inno_v2.c
+ create mode 100644 scripts/pic2logo-include/stb_image/stb_image.h
+ create mode 100644 scripts/pic2logo-include/stb_image/stb_image_resize.h
+ create mode 100644 scripts/pic2logo-include/stb_image/stb_image_write.h
+ create mode 100644 scripts/pic2logo.c
+
+diff --git a/Kconfig b/Kconfig
+index ce7229470..ad919057a 100644
+--- a/Kconfig
++++ b/Kconfig
+@@ -31,4 +31,6 @@ source "lib/Kconfig.debug"
+ 
+ source "Documentation/Kconfig"
+ 
++source "module_drivers/Kconfig"
++
+ source "vendor/Kconfig"
+diff --git a/Makefile b/Makefile
+index b51f00f84..d164e2902 100644
+--- a/Makefile
++++ b/Makefile
+@@ -655,6 +655,8 @@ drivers-y	+= net/ virt/
+ libs-y		:= lib/
+ vendor-$(CONFIG_OHOS_VENDOR) := vendor/
+ endif # KBUILD_EXTMOD
++ 
++drivers-y += module_drivers/
+ 
+ # The all: target is the default when no target is given on the
+ # command line.
+@@ -1393,7 +1395,7 @@ kselftest-merge:
+ # Devicetree files
+ 
+ ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/boot/dts/),)
+-dtstree := arch/$(SRCARCH)/boot/dts
++dtstree := module_drivers/dts
+ endif
+ 
+ ifneq ($(dtstree),)
+diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
+index 5483e38b5..985c11af7 100644
+--- a/arch/mips/Kbuild.platforms
++++ b/arch/mips/Kbuild.platforms
+@@ -36,6 +36,8 @@ platform-$(CONFIG_SNI_RM)		+= sni/
+ platform-$(CONFIG_MACH_TX39XX)		+= txx9/
+ platform-$(CONFIG_MACH_TX49XX)		+= txx9/
+ platform-$(CONFIG_MACH_VR41XX)		+= vr41xx/
++platform-$(CONFIG_MACH_XBURST)		+= xburst/
++platform-$(CONFIG_MACH_XBURST2)		+= xburst2/
+ 
+ # include the platform specific files
+ include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platform-y))
+diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
+index 896a29df1..ef8bf2f8a 100644
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -421,8 +421,59 @@ config MACH_INGENIC_SOC
+ 	select MIPS_GENERIC
+ 	select MACH_INGENIC
+ 	select SYS_SUPPORTS_ZBOOT_UART16550
+-	select CPU_SUPPORTS_CPUFREQ
++
++config MACH_XBURST
++	bool "Ingenic Xburst based machines"
++	select SYS_SUPPORTS_32BIT_KERNEL
++	select SYS_SUPPORTS_LITTLE_ENDIAN
++	select SYS_HAS_CPU_MIPS32_R1
++	select SYS_HAS_CPU_MIPS32_R2
++	select SYS_HAS_EARLY_PRINTK
+ 	select MIPS_EXTERNAL_TIMER
++	select DMA_NONCOHERENT
++	select HAVE_CLK
++	select ARCH_REQUIRE_GPIOLIB
++	select SYS_SUPPORTS_HIGHMEM
++	select XBURST_CPU_SCACHE
++	select BOARD_SCACHE
++	select DMA_INGENIC_HIGHMEM_FLUSH
++	select HAVE_KERNEL_GZIP
++	select IRQ_MIPS_CPU
++	select USE_OF
++	select LIBFDT
++	select COMMON_CLK
++	select HARDIRQS_SW_RESEND
++
++config MACH_XBURST2
++	bool "Ingenic Xburst2 based machines"
++	select SYS_SUPPORTS_32BIT_KERNEL
++	select SYS_SUPPORTS_LITTLE_ENDIAN
++	select SYS_HAS_CPU_MIPS32_R1
++	select SYS_HAS_CPU_MIPS32_R2
++	select SYS_HAS_CPU_MIPS32_R5
++	select SYS_HAS_EARLY_PRINTK
++	select SYS_SUPPORTS_SMP
++	select SYS_SUPPORTS_HOTPLUG_CPU
++	select MIPS_EXTERNAL_TIMER
++	select DMA_NONCOHERENT
++	select HAVE_CLK
++	select ARCH_REQUIRE_GPIOLIB
++	select SYS_SUPPORTS_HIGHMEM
++	select XBURST2_CPU_SCACHE
++	select DMA_INGENIC_HIGHMEM_FLUSH
++	select HAVE_KERNEL_GZIP
++	select IRQ_MIPS_CPU
++	select USE_OF
++	select LIBFDT
++	select MIPS_O32_FP64_SUPPORT
++	select WEAK_ORDERING
++	select WEAK_REORDERING_BEYOND_LLSC
++	select COMMON_CLK
++	select BOARD_SCACHE
++	select CPU_SUPPORTS_CPUFREQ
++	select HARDIRQS_SW_RESEND
++
++
+ 
+ config LANTIQ
+ 	bool "Lantiq based platforms"
+@@ -1045,6 +1096,8 @@ source "arch/mips/bcm63xx/Kconfig"
+ source "arch/mips/bmips/Kconfig"
+ source "arch/mips/generic/Kconfig"
+ source "arch/mips/ingenic/Kconfig"
++source "arch/mips/xburst/Kconfig"
++source "arch/mips/xburst2/Kconfig"
+ source "arch/mips/jazz/Kconfig"
+ source "arch/mips/lantiq/Kconfig"
+ source "arch/mips/pic32/Kconfig"
+@@ -2305,6 +2358,14 @@ config MIPS_CPU_SCACHE
+ 	bool
+ 	select BOARD_SCACHE
+ 
++config XBURST_CPU_SCACHE
++	bool
++	select BOARD_SCACHE
++
++config XBURST2_CPU_SCACHE
++	bool
++	select BOARD_SCACHE
++
+ config R5000_CPU_SCACHE
+ 	bool
+ 	select BOARD_SCACHE
+diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
+index 19027129a..bcc5e9e8b 100644
+--- a/arch/mips/boot/dts/Makefile
++++ b/arch/mips/boot/dts/Makefile
+@@ -15,5 +15,7 @@ subdir-$(CONFIG_MACH_PIC32)		+= pic32
+ subdir-$(CONFIG_ATH79)			+= qca
+ subdir-$(CONFIG_RALINK)			+= ralink
+ subdir-$(CONFIG_FIT_IMAGE_FDT_XILFPGA)	+= xilfpga
++subdir-$(CONFIG_MACH_XBURST)		+= ingenic
++subdir-$(CONFIG_MACH_XBURST2)		+= ingenic
+ 
+ obj-$(CONFIG_BUILTIN_DTB)	:= $(addsuffix /, $(subdir-y))
+diff --git a/arch/mips/configs/halley5_small_defconfig b/arch/mips/configs/halley5_small_defconfig
+new file mode 100644
+index 000000000..44f9576cf
+--- /dev/null
++++ b/arch/mips/configs/halley5_small_defconfig
+@@ -0,0 +1,4478 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/mips 5.10.93 Kernel Configuration
++#
++CONFIG_CC_VERSION_TEXT="OHOS (dev) clang version 12.0.1 (llvm-project ca29bdb75cfb16ef1b9a01a42de3ebaa9281896f)"
++CONFIG_GCC_VERSION=0
++CONFIG_LD_VERSION=227000000
++CONFIG_CC_IS_CLANG=y
++CONFIG_CLANG_VERSION=120001
++CONFIG_LLD_VERSION=0
++CONFIG_CC_HAS_ASM_GOTO=y
++CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
++CONFIG_CC_HAS_ASM_INLINE=y
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_TABLE_SORT=y
++
++#
++# General setup
++#
++CONFIG_INIT_ENV_ARG_LIMIT=32
++# CONFIG_COMPILE_TEST is not set
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_BUILD_SALT=""
++CONFIG_HAVE_KERNEL_GZIP=y
++CONFIG_KERNEL_GZIP=y
++CONFIG_DEFAULT_INIT=""
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_WATCH_QUEUE is not set
++# CONFIG_CROSS_MEMORY_ATTACH is not set
++CONFIG_USELIB=y
++# CONFIG_AUDIT is not set
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_CHIP=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_HANDLE_DOMAIN_IRQ=y
++CONFIG_IRQ_FORCED_THREADING=y
++# CONFIG_GENERIC_IRQ_DEBUGFS is not set
++# end of IRQ subsystem
++
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_GENERIC_CMOS_UPDATE=y
++
++#
++# Timers subsystem
++#
++CONFIG_TICK_ONESHOT=y
++CONFIG_NO_HZ_COMMON=y
++# CONFIG_HZ_PERIODIC is not set
++CONFIG_NO_HZ_IDLE=y
++# CONFIG_NO_HZ is not set
++CONFIG_HIGH_RES_TIMERS=y
++# end of Timers subsystem
++
++# CONFIG_PREEMPT_NONE is not set
++# CONFIG_PREEMPT_VOLUNTARY is not set
++CONFIG_PREEMPT=y
++CONFIG_PREEMPT_COUNT=y
++CONFIG_PREEMPTION=y
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++# CONFIG_SCHED_WALT is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_PSI is not set
++# end of CPU/Task time and stats accounting
++
++CONFIG_CPU_ISOLATION=y
++# CONFIG_SCHED_RUNNING_AVG is not set
++# CONFIG_CPU_ISOLATION_OPT is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_RCU=y
++CONFIG_PREEMPT_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++CONFIG_TREE_SRCU=y
++CONFIG_TASKS_RCU_GENERIC=y
++CONFIG_TASKS_RCU=y
++CONFIG_RCU_STALL_COMMON=y
++CONFIG_RCU_NEED_SEGCBLIST=y
++# end of RCU Subsystem
++
++# CONFIG_IKCONFIG is not set
++# CONFIG_IKHEADERS is not set
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
++CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
++CONFIG_GENERIC_SCHED_CLOCK=y
++
++#
++# Scheduler features
++#
++# CONFIG_SCHED_LATENCY_NICE is not set
++
++#
++# Related Thread Group
++#
++# end of Related Thread Group
++
++# CONFIG_SCHED_EAS is not set
++# end of Scheduler features
++
++# CONFIG_CGROUPS is not set
++# CONFIG_NAMESPACES is not set
++# CONFIG_CHECKPOINT_RESTORE is not set
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++# CONFIG_BLK_DEV_INITRD is not set
++# CONFIG_BOOT_CONFIG is not set
++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
++# CONFIG_LD_DEAD_CODE_DATA_ELIMINATION is not set
++CONFIG_SYSCTL=y
++CONFIG_SYSCTL_EXCEPTION_TRACE=y
++CONFIG_BPF=y
++CONFIG_EXPERT=y
++CONFIG_MULTIUSER=y
++CONFIG_SGETMASK_SYSCALL=y
++CONFIG_SYSFS_SYSCALL=y
++CONFIG_FHANDLE=y
++CONFIG_POSIX_TIMERS=y
++CONFIG_PRINTK=y
++CONFIG_PRINTK_NMI=y
++CONFIG_BUG=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_FUTEX_PI=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_IO_URING=y
++# CONFIG_ADVISE_SYSCALLS is not set
++CONFIG_MEMBARRIER=y
++# CONFIG_KALLSYMS is not set
++# CONFIG_BPF_SYSCALL is not set
++# CONFIG_USERFAULTFD is not set
++# CONFIG_KCMP is not set
++CONFIG_RSEQ=y
++# CONFIG_DEBUG_RSEQ is not set
++# CONFIG_EMBEDDED is not set
++CONFIG_HAVE_PERF_EVENTS=y
++CONFIG_PERF_USE_VMALLOC=y
++# CONFIG_PC104 is not set
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++# end of Kernel Performance Events And Counters
++
++# CONFIG_VM_EVENT_COUNTERS is not set
++# CONFIG_COMPAT_BRK is not set
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLAB_MERGE_DEFAULT=y
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++# CONFIG_SLAB_FREELIST_HARDENED is not set
++# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
++CONFIG_SYSTEM_DATA_VERIFICATION=y
++# CONFIG_PROFILING is not set
++# end of General setup
++
++CONFIG_MIPS=y
++
++#
++# Machine selection
++#
++# CONFIG_MIPS_GENERIC_KERNEL is not set
++# CONFIG_MIPS_ALCHEMY is not set
++# CONFIG_AR7 is not set
++# CONFIG_ATH25 is not set
++# CONFIG_ATH79 is not set
++# CONFIG_BMIPS_GENERIC is not set
++# CONFIG_BCM47XX is not set
++# CONFIG_BCM63XX is not set
++# CONFIG_MIPS_COBALT is not set
++# CONFIG_MACH_DECSTATION is not set
++# CONFIG_MACH_JAZZ is not set
++# CONFIG_MACH_INGENIC_SOC is not set
++# CONFIG_MACH_XBURST is not set
++CONFIG_MACH_XBURST2=y
++# CONFIG_LANTIQ is not set
++# CONFIG_MACH_LOONGSON32 is not set
++# CONFIG_MACH_LOONGSON2EF is not set
++# CONFIG_MACH_LOONGSON64 is not set
++# CONFIG_MACH_PISTACHIO is not set
++# CONFIG_MIPS_MALTA is not set
++# CONFIG_MACH_PIC32 is not set
++# CONFIG_MACH_VR41XX is not set
++# CONFIG_RALINK is not set
++# CONFIG_SGI_IP22 is not set
++# CONFIG_SGI_IP27 is not set
++# CONFIG_SGI_IP28 is not set
++# CONFIG_SGI_IP30 is not set
++# CONFIG_SGI_IP32 is not set
++# CONFIG_SIBYTE_CRHINE is not set
++# CONFIG_SIBYTE_CARMEL is not set
++# CONFIG_SIBYTE_CRHONE is not set
++# CONFIG_SIBYTE_RHONE is not set
++# CONFIG_SIBYTE_SWARM is not set
++# CONFIG_SIBYTE_LITTLESUR is not set
++# CONFIG_SIBYTE_SENTOSA is not set
++# CONFIG_SIBYTE_BIGSUR is not set
++# CONFIG_SNI_RM is not set
++# CONFIG_MACH_TX39XX is not set
++# CONFIG_MACH_TX49XX is not set
++# CONFIG_MIKROTIK_RB532 is not set
++# CONFIG_CAVIUM_OCTEON_SOC is not set
++# CONFIG_NLM_XLR_BOARD is not set
++# CONFIG_NLM_XLP_BOARD is not set
++CONFIG_INGENIC_BUILTIN_DTB=y
++CONFIG_EXTAL_CLOCK=24
++CONFIG_INGENIC_GPT_CHECK=y
++# CONFIG_SUSPEND_TEST is not set
++
++#
++# SOC Type Selection
++#
++CONFIG_SOC_X2000=y
++# CONFIG_SOC_X2500 is not set
++# CONFIG_SOC_M300 is not set
++# CONFIG_SOC_X2100 is not set
++# CONFIG_DT_X2000_MODULE is not set
++# CONFIG_DT_HALLEY5_V20 is not set
++CONFIG_DT_HALLEY5_V30=y
++# CONFIG_DT_KALE_V10 is not set
++# CONFIG_DT_X2000_LIFESMART_480P is not set
++# CONFIG_RAW_BOOT is not set
++# CONFIG_FPGA_TEST is not set
++# CONFIG_XBURST2_CPU_TEST is not set
++# CONFIG_FASTBOOT is not set
++# end of SOC Type Selection
++# end of Machine selection
++
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_OMIT_FRAME_POINTER=y
++CONFIG_ARCH_SUPPORTS_UPROBES=y
++CONFIG_DMA_NONCOHERENT=y
++CONFIG_SYS_HAS_EARLY_PRINTK=y
++CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
++CONFIG_CPU_LITTLE_ENDIAN=y
++CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
++CONFIG_MIPS_SPRAM=y
++CONFIG_MIPS_L1_CACHE_SHIFT=5
++
++#
++# CPU selection
++#
++# CONFIG_CPU_MIPS32_R1 is not set
++# CONFIG_CPU_MIPS32_R2 is not set
++CONFIG_CPU_MIPS32_R5=y
++# CONFIG_CPU_MIPS32_R5_FEATURES is not set
++CONFIG_SYS_HAS_CPU_MIPS32_R1=y
++CONFIG_SYS_HAS_CPU_MIPS32_R2=y
++CONFIG_SYS_HAS_CPU_MIPS32_R5=y
++CONFIG_WEAK_ORDERING=y
++CONFIG_WEAK_REORDERING_BEYOND_LLSC=y
++# end of CPU selection
++
++CONFIG_CPU_MIPS32=y
++CONFIG_CPU_MIPSR5=y
++CONFIG_TARGET_ISA_REV=5
++CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
++CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
++CONFIG_CPU_SUPPORTS_CPUFREQ=y
++
++#
++# Kernel type
++#
++CONFIG_32BIT=y
++CONFIG_PAGE_SIZE_4KB=y
++# CONFIG_PAGE_SIZE_16KB is not set
++# CONFIG_PAGE_SIZE_64KB is not set
++CONFIG_FORCE_MAX_ZONEORDER=15
++CONFIG_BOARD_SCACHE=y
++CONFIG_XBURST2_CPU_SCACHE=y
++CONFIG_CPU_HAS_PREFETCH=y
++CONFIG_CPU_GENERIC_DUMP_TLB=y
++CONFIG_MIPS_FP_SUPPORT=y
++CONFIG_CPU_R4K_FPU=y
++CONFIG_CPU_R4K_CACHE_TLB=y
++CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
++CONFIG_CPU_HAS_MSA=y
++CONFIG_CPU_HAS_DIEI=y
++CONFIG_CPU_HAS_RIXI=y
++CONFIG_CPU_HAS_SYNC=y
++CONFIG_MIPS_ASID_SHIFT=0
++CONFIG_MIPS_ASID_BITS=8
++# CONFIG_HIGHMEM is not set
++CONFIG_CPU_SUPPORTS_HIGHMEM=y
++CONFIG_SYS_SUPPORTS_HIGHMEM=y
++CONFIG_CPU_SUPPORTS_MSA=y
++CONFIG_ARCH_FLATMEM_ENABLE=y
++CONFIG_SMP=y
++CONFIG_HOTPLUG_CPU=y
++CONFIG_SYS_SUPPORTS_SMP=y
++CONFIG_NR_CPUS=2
++CONFIG_MIPS_NR_CPU_NR_MAP=2
++# CONFIG_HZ_24 is not set
++# CONFIG_HZ_48 is not set
++CONFIG_HZ_100=y
++# CONFIG_HZ_128 is not set
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_256 is not set
++# CONFIG_HZ_1000 is not set
++# CONFIG_HZ_1024 is not set
++CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
++CONFIG_HZ=100
++CONFIG_SCHED_HRTICK=y
++# CONFIG_KEXEC is not set
++# CONFIG_CRASH_DUMP is not set
++CONFIG_MIPS_O32_FP64_SUPPORT=y
++CONFIG_USE_OF=y
++CONFIG_BUILTIN_DTB=y
++CONFIG_MIPS_NO_APPENDED_DTB=y
++# CONFIG_MIPS_ELF_APPENDED_DTB is not set
++# CONFIG_MIPS_RAW_APPENDED_DTB is not set
++CONFIG_MIPS_CMDLINE_FROM_DTB=y
++# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
++# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
++# end of Kernel type
++
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_PGTABLE_LEVELS=2
++
++#
++# Bus options (PCI, PCMCIA, EISA, ISA, TC)
++#
++CONFIG_PCI_DRIVERS_LEGACY=y
++CONFIG_MMU=y
++CONFIG_ARCH_MMAP_RND_BITS_MIN=8
++CONFIG_ARCH_MMAP_RND_BITS_MAX=15
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
++# end of Bus options (PCI, PCMCIA, EISA, ISA, TC)
++
++CONFIG_TRAD_SIGNALS=y
++
++#
++# Power management options
++#
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++# CONFIG_SUSPEND_SKIP_SYNC is not set
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_CLK=y
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++# end of Power management options
++
++CONFIG_MIPS_EXTERNAL_TIMER=y
++
++#
++# CPU Power Management
++#
++
++#
++# CPU Frequency scaling
++#
++# CONFIG_CPU_FREQ is not set
++# end of CPU Frequency scaling
++
++#
++# CPU Idle
++#
++# CONFIG_CPU_IDLE is not set
++# end of CPU Idle
++# end of CPU Power Management
++
++#
++# Firmware Drivers
++#
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_GOOGLE_FIRMWARE is not set
++
++#
++# Tegra firmware driver
++#
++# end of Tegra firmware driver
++# end of Firmware Drivers
++
++CONFIG_HAVE_KVM=y
++# CONFIG_VIRTUALIZATION is not set
++CONFIG_MIPS_LD_CAN_LINK_VDSO=y
++
++#
++# General architecture-dependent options
++#
++CONFIG_CRASH_CORE=y
++CONFIG_SET_FS=y
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++CONFIG_ARCH_USE_BUILTIN_BSWAP=y
++CONFIG_HAVE_IOREMAP_PROT=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_NMI=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
++CONFIG_ARCH_HAS_DMA_SET_UNCACHED=y
++CONFIG_ARCH_32BIT_OFF_T=y
++CONFIG_HAVE_ASM_MODVERSIONS=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_RSEQ=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
++CONFIG_HAVE_ARCH_SECCOMP=y
++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
++# CONFIG_SECCOMP is not set
++CONFIG_HAVE_STACKPROTECTOR=y
++CONFIG_STACKPROTECTOR=y
++CONFIG_STACKPROTECTOR_STRONG=y
++CONFIG_LTO_NONE=y
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_TIF_NOHZ=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
++CONFIG_MODULES_USE_ELF_REL=y
++CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_HAVE_EXIT_THREAD=y
++CONFIG_ARCH_MMAP_RND_BITS=8
++CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
++CONFIG_CLONE_BACKWARDS=y
++CONFIG_COMPAT_32BIT_TIME=y
++CONFIG_HAVE_ARCH_COMPILER_H=y
++# CONFIG_LOCK_EVENT_COUNTS is not set
++CONFIG_HAVE_SPARSE_SYSCALL_NR=y
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++# end of GCOV-based kernel profiling
++
++CONFIG_HAVE_GCC_PLUGINS=y
++# end of General architecture-dependent options
++
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_MODULE_COMPRESS is not set
++# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_BLOCK=y
++CONFIG_BLK_SCSI_REQUEST=y
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_BLK_DEV_BSGLIB is not set
++CONFIG_BLK_DEV_INTEGRITY=y
++CONFIG_BLK_DEV_INTEGRITY_T10=y
++# CONFIG_BLK_DEV_ZONED is not set
++# CONFIG_BLK_CMDLINE_PARSER is not set
++# CONFIG_BLK_WBT is not set
++CONFIG_BLK_DEBUG_FS=y
++# CONFIG_BLK_SED_OPAL is not set
++# CONFIG_BLK_INLINE_ENCRYPTION is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++# CONFIG_CMDLINE_PARTITION is not set
++# end of Partition Types
++
++CONFIG_BLK_PM=y
++
++#
++# IO Schedulers
++#
++CONFIG_MQ_IOSCHED_DEADLINE=y
++CONFIG_MQ_IOSCHED_KYBER=y
++# CONFIG_IOSCHED_BFQ is not set
++# end of IO Schedulers
++
++CONFIG_ASN1=y
++CONFIG_UNINLINE_SPIN_UNLOCK=y
++CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
++CONFIG_QUEUED_SPINLOCKS=y
++CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
++CONFIG_QUEUED_RWLOCKS=y
++CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
++CONFIG_FREEZER=y
++
++#
++# Executable file formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_ARCH_BINFMT_ELF_STATE=y
++CONFIG_ELFCORE=y
++CONFIG_BINFMT_SCRIPT=y
++# CONFIG_BINFMT_MISC is not set
++# CONFIG_COREDUMP is not set
++# end of Executable file formats
++
++#
++# Memory Management options
++#
++# CONFIG_PAGE_TRACING is not set
++# CONFIG_RECLAIM_ACCT is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_HAVE_FAST_GUP=y
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_COMPACTION=y
++# CONFIG_PAGE_REPORTING is not set
++CONFIG_MIGRATION=y
++CONFIG_VIRT_TO_BUS=y
++CONFIG_MMU_NOTIFIER=y
++# CONFIG_KSM is not set
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++# CONFIG_CLEANCACHE is not set
++# CONFIG_CMA is not set
++# CONFIG_ZPOOL is not set
++# CONFIG_ZBUD is not set
++# CONFIG_ZSMALLOC is not set
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_FRAME_VECTOR=y
++# CONFIG_PERCPU_STATS is not set
++# CONFIG_GUP_BENCHMARK is not set
++# CONFIG_LOWMEM is not set
++# CONFIG_LMKD_DBG is not set
++# end of Memory Management options
++
++CONFIG_NET=y
++CONFIG_NET_INGRESS=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++# CONFIG_PACKET_DIAG is not set
++CONFIG_UNIX=y
++CONFIG_UNIX_SCM=y
++# CONFIG_UNIX_DIAG is not set
++# CONFIG_TLS is not set
++# CONFIG_XFRM_USER is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++CONFIG_IP_PNP_RARP=y
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++# CONFIG_IP_MROUTE is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_NET_IPVTI is not set
++# CONFIG_NET_FOU is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_INET_UDP_DIAG is not set
++# CONFIG_INET_RAW_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_MPTCP is not set
++# CONFIG_NETWORK_SECMARK is not set
++CONFIG_NET_PTP_CLASSIFY=y
++CONFIG_NETWORK_PHY_TIMESTAMPING=y
++CONFIG_NETFILTER=y
++CONFIG_NETFILTER_ADVANCED=y
++# CONFIG_BRIDGE_NETFILTER is not set
++
++#
++# Core Netfilter Configuration
++#
++CONFIG_NETFILTER_INGRESS=y
++CONFIG_NETFILTER_NETLINK=y
++# CONFIG_NETFILTER_NETLINK_ACCT is not set
++CONFIG_NETFILTER_NETLINK_QUEUE=y
++CONFIG_NETFILTER_NETLINK_LOG=y
++# CONFIG_NETFILTER_NETLINK_OSF is not set
++# CONFIG_NF_CONNTRACK is not set
++# CONFIG_NF_LOG_NETDEV is not set
++# CONFIG_NF_TABLES is not set
++CONFIG_NETFILTER_XTABLES=y
++
++#
++# Xtables combined modules
++#
++# CONFIG_NETFILTER_XT_MARK is not set
++# CONFIG_NETFILTER_XT_SET is not set
++
++#
++# Xtables targets
++#
++# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
++# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
++# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
++# CONFIG_NETFILTER_XT_TARGET_HL is not set
++# CONFIG_NETFILTER_XT_TARGET_HMARK is not set
++# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
++# CONFIG_NETFILTER_XT_TARGET_LOG is not set
++# CONFIG_NETFILTER_XT_TARGET_MARK is not set
++CONFIG_NETFILTER_XT_TARGET_NFLOG=y
++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
++# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
++# CONFIG_NETFILTER_XT_TARGET_TEE is not set
++# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set
++# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
++# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
++# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
++
++#
++# Xtables matches
++#
++# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
++# CONFIG_NETFILTER_XT_MATCH_BPF is not set
++# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
++# CONFIG_NETFILTER_XT_MATCH_CPU is not set
++# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
++# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
++# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
++# CONFIG_NETFILTER_XT_MATCH_ECN is not set
++# CONFIG_NETFILTER_XT_MATCH_ESP is not set
++# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
++# CONFIG_NETFILTER_XT_MATCH_HL is not set
++# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set
++# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
++# CONFIG_NETFILTER_XT_MATCH_L2TP is not set
++# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
++# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
++# CONFIG_NETFILTER_XT_MATCH_MAC is not set
++# CONFIG_NETFILTER_XT_MATCH_MARK is not set
++# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
++# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set
++# CONFIG_NETFILTER_XT_MATCH_OSF is not set
++# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
++# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
++CONFIG_NETFILTER_XT_MATCH_QUOTA=y
++# CONFIG_NETFILTER_XT_MATCH_QUOTA2 is not set
++# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
++# CONFIG_NETFILTER_XT_MATCH_REALM is not set
++# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
++# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
++# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set
++# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
++# CONFIG_NETFILTER_XT_MATCH_STRING is not set
++# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
++# CONFIG_NETFILTER_XT_MATCH_TIME is not set
++# CONFIG_NETFILTER_XT_MATCH_U32 is not set
++# end of Core Netfilter Configuration
++
++CONFIG_IP_SET=y
++CONFIG_IP_SET_MAX=256
++# CONFIG_IP_SET_BITMAP_IP is not set
++CONFIG_IP_SET_BITMAP_IPMAC=m
++# CONFIG_IP_SET_BITMAP_PORT is not set
++# CONFIG_IP_SET_HASH_IP is not set
++# CONFIG_IP_SET_HASH_IPMARK is not set
++# CONFIG_IP_SET_HASH_IPPORT is not set
++# CONFIG_IP_SET_HASH_IPPORTIP is not set
++# CONFIG_IP_SET_HASH_IPPORTNET is not set
++# CONFIG_IP_SET_HASH_IPMAC is not set
++# CONFIG_IP_SET_HASH_MAC is not set
++# CONFIG_IP_SET_HASH_NETPORTNET is not set
++# CONFIG_IP_SET_HASH_NET is not set
++# CONFIG_IP_SET_HASH_NETNET is not set
++# CONFIG_IP_SET_HASH_NETPORT is not set
++# CONFIG_IP_SET_HASH_NETIFACE is not set
++# CONFIG_IP_SET_LIST_SET is not set
++# CONFIG_IP_VS is not set
++
++#
++# IP: Netfilter Configuration
++#
++# CONFIG_NF_SOCKET_IPV4 is not set
++# CONFIG_NF_TPROXY_IPV4 is not set
++# CONFIG_NF_DUP_IPV4 is not set
++# CONFIG_NF_LOG_ARP is not set
++# CONFIG_NF_LOG_IPV4 is not set
++# CONFIG_NF_REJECT_IPV4 is not set
++CONFIG_IP_NF_IPTABLES=y
++# CONFIG_IP_NF_MATCH_AH is not set
++# CONFIG_IP_NF_MATCH_ECN is not set
++# CONFIG_IP_NF_MATCH_RPFILTER is not set
++# CONFIG_IP_NF_MATCH_TTL is not set
++CONFIG_IP_NF_FILTER=y
++# CONFIG_IP_NF_TARGET_REJECT is not set
++CONFIG_IP_NF_MANGLE=y
++# CONFIG_IP_NF_TARGET_ECN is not set
++# CONFIG_IP_NF_TARGET_TTL is not set
++CONFIG_IP_NF_RAW=y
++# CONFIG_IP_NF_ARPTABLES is not set
++# end of IP: Netfilter Configuration
++
++# CONFIG_BRIDGE_NF_EBTABLES is not set
++# CONFIG_BPFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++CONFIG_STP=y
++CONFIG_BRIDGE=y
++CONFIG_BRIDGE_IGMP_SNOOPING=y
++# CONFIG_BRIDGE_MRP is not set
++CONFIG_HAVE_NET_DSA=y
++# CONFIG_NET_DSA is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++CONFIG_LLC=y
++# CONFIG_LLC2 is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++# CONFIG_DNS_RESOLVER is not set
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++# CONFIG_NETLINK_DIAG is not set
++# CONFIG_MPLS is not set
++# CONFIG_NET_NSH is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_QRTR is not set
++# CONFIG_NET_NCSI is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++CONFIG_NET_FLOW_LIMIT=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# end of Network testing
++# end of Networking options
++
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++CONFIG_WIRELESS=y
++CONFIG_WEXT_CORE=y
++CONFIG_WEXT_PROC=y
++CONFIG_CFG80211=y
++CONFIG_NL80211_TESTMODE=y
++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
++CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
++CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
++CONFIG_CFG80211_DEFAULT_PS=y
++# CONFIG_CFG80211_DEBUGFS is not set
++CONFIG_CFG80211_CRDA_SUPPORT=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_MAC80211=y
++CONFIG_MAC80211_HAS_RC=y
++CONFIG_MAC80211_RC_MINSTREL=y
++CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
++CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
++CONFIG_MAC80211_MESH=y
++# CONFIG_MAC80211_DEBUGFS is not set
++# CONFIG_MAC80211_MESSAGE_TRACING is not set
++# CONFIG_MAC80211_DEBUG_MENU is not set
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++# CONFIG_WIMAX is not set
++CONFIG_RFKILL=y
++CONFIG_RFKILL_INPUT=y
++# CONFIG_RFKILL_GPIO is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_PSAMPLE is not set
++# CONFIG_NET_IFE is not set
++# CONFIG_LWTUNNEL is not set
++# CONFIG_FAILOVER is not set
++CONFIG_ETHTOOL_NETLINK=y
++CONFIG_HAVE_CBPF_JIT=y
++
++#
++# Device Drivers
++#
++# CONFIG_PCCARD is not set
++# CONFIG_HYPERHOLD is not set
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER=y
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++# CONFIG_STANDALONE is not set
++# CONFIG_PREVENT_FIRMWARE_BUILD is not set
++
++#
++# Firmware loader
++#
++CONFIG_FW_LOADER=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_FW_LOADER_USER_HELPER is not set
++# CONFIG_FW_LOADER_COMPRESS is not set
++CONFIG_FW_CACHE=y
++# end of Firmware loader
++
++# CONFIG_ALLOW_DEV_COREDUMP is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
++CONFIG_GENERIC_CPU_AUTOPROBE=y
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_REGMAP_SPI=y
++CONFIG_REGMAP_MMIO=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_DMA_FENCE_TRACE is not set
++# end of Generic Driver Options
++
++#
++# Bus devices
++#
++# CONFIG_BRCMSTB_GISB_ARB is not set
++# CONFIG_MOXTET is not set
++# CONFIG_MIPS_CDMM is not set
++# CONFIG_SIMPLE_PM_BUS is not set
++# CONFIG_MHI_BUS is not set
++# end of Bus devices
++
++# CONFIG_CONNECTOR is not set
++# CONFIG_GNSS is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++
++#
++# Partition parsers
++#
++# CONFIG_MTD_AR7_PARTS is not set
++# CONFIG_MTD_CMDLINE_PARTS is not set
++CONFIG_MTD_OF_PARTS=y
++# CONFIG_MTD_REDBOOT_PARTS is not set
++# end of Partition parsers
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_MTD_BLOCK_BBT_RO is not set
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_PARTITIONED_MASTER is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++# end of RAM/ROM/Flash chip drivers
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PLATRAM is not set
++# end of Mapping drivers for chip access
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_MCHP23K256 is not set
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOCG3 is not set
++# end of Self-contained MTD device drivers
++
++#
++# NAND
++#
++CONFIG_MTD_NAND_CORE=y
++# CONFIG_MTD_ONENAND is not set
++CONFIG_MTD_NAND_ECC_SW_HAMMING=y
++# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
++CONFIG_MTD_RAW_NAND=y
++# CONFIG_MTD_NAND_ECC_SW_BCH is not set
++
++#
++# Raw/parallel NAND flash controllers
++#
++# CONFIG_MTD_NAND_DENALI_DT is not set
++# CONFIG_MTD_NAND_BRCMNAND is not set
++# CONFIG_MTD_NAND_MXIC is not set
++# CONFIG_MTD_NAND_GPIO is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_NAND_CADENCE is not set
++# CONFIG_MTD_NAND_ARASAN is not set
++
++#
++# Misc
++#
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_SPI_NAND is not set
++
++#
++# ECC engine support
++#
++CONFIG_MTD_NAND_ECC=y
++# end of ECC engine support
++# end of NAND
++
++#
++# LPDDR & LPDDR2 PCM memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++# end of LPDDR & LPDDR2 PCM memory drivers
++
++# CONFIG_MTD_SPI_NOR is not set
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++# CONFIG_MTD_UBI_GLUEBI is not set
++# CONFIG_MTD_UBI_BLOCK is not set
++# CONFIG_MTD_HYPERBUS is not set
++CONFIG_DTC=y
++CONFIG_OF=y
++# CONFIG_OF_UNITTEST is not set
++CONFIG_OF_FLATTREE=y
++CONFIG_OF_EARLY_FLATTREE=y
++CONFIG_OF_KOBJ=y
++CONFIG_OF_ADDRESS=y
++CONFIG_OF_IRQ=y
++CONFIG_OF_NET=y
++CONFIG_OF_RESERVED_MEM=y
++# CONFIG_OF_OVERLAY is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_LOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_RAM is not set
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_BLK_DEV_RBD is not set
++
++#
++# NVME Support
++#
++# CONFIG_NVME_FC is not set
++# CONFIG_NVME_TCP is not set
++# CONFIG_NVME_TARGET is not set
++# end of NVME Support
++
++#
++# Misc devices
++#
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_LATTICE_ECP3_CONFIG is not set
++# CONFIG_SRAM is not set
++# CONFIG_XILINX_SDFEC is not set
++# CONFIG_PVPANIC is not set
++# CONFIG_HISI_HIKEY_USB is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++# CONFIG_EEPROM_IDT_89HPESX is not set
++# CONFIG_EEPROM_EE1004 is not set
++# end of EEPROM support
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# end of Texas Instruments shared transport line discipline
++
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++# CONFIG_ALTERA_STAPL is not set
++# CONFIG_ECHO is not set
++# CONFIG_MISC_RTSX_USB is not set
++# end of Misc devices
++
++CONFIG_HAVE_IDE=y
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++# end of SCSI Transports
++
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_DH is not set
++# end of SCSI device support
++
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++CONFIG_NETDEVICES=y
++CONFIG_MII=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_WIREGUARD is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_IPVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_GENEVE is not set
++# CONFIG_BAREUDP is not set
++# CONFIG_GTP is not set
++# CONFIG_MACSEC is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++
++#
++# Distributed Switch Architecture drivers
++#
++# end of Distributed Switch Architecture drivers
++
++CONFIG_ETHERNET=y
++CONFIG_NET_VENDOR_ALACRITECH=y
++# CONFIG_ALTERA_TSE is not set
++CONFIG_NET_VENDOR_AMAZON=y
++CONFIG_NET_VENDOR_AQUANTIA=y
++# CONFIG_NET_VENDOR_ARC is not set
++# CONFIG_NET_VENDOR_AURORA is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++CONFIG_NET_VENDOR_CADENCE=y
++# CONFIG_MACB is not set
++CONFIG_NET_VENDOR_CAVIUM=y
++CONFIG_NET_VENDOR_CORTINA=y
++# CONFIG_GEMINI_ETHERNET is not set
++# CONFIG_DM9000 is not set
++# CONFIG_DNET is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++CONFIG_NET_VENDOR_GOOGLE=y
++CONFIG_NET_VENDOR_HUAWEI=y
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++CONFIG_NET_VENDOR_MELLANOX=y
++# CONFIG_MLXSW_CORE is not set
++# CONFIG_MLXFW is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++CONFIG_NET_VENDOR_MICROCHIP=y
++# CONFIG_ENC28J60 is not set
++# CONFIG_ENCX24J600 is not set
++CONFIG_NET_VENDOR_MICROSEMI=y
++# CONFIG_NET_VENDOR_NATSEMI is not set
++CONFIG_NET_VENDOR_NETRONOME=y
++CONFIG_NET_VENDOR_NI=y
++# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
++# CONFIG_ETHOC is not set
++CONFIG_NET_VENDOR_PENSANDO=y
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++CONFIG_NET_VENDOR_SOLARFLARE=y
++# CONFIG_NET_VENDOR_SMSC is not set
++CONFIG_NET_VENDOR_SOCIONEXT=y
++# CONFIG_NET_VENDOR_STMICRO is not set
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++CONFIG_NET_VENDOR_XILINX=y
++# CONFIG_XILINX_EMACLITE is not set
++# CONFIG_XILINX_AXI_EMAC is not set
++# CONFIG_XILINX_LL_TEMAC is not set
++CONFIG_PHYLIB=y
++CONFIG_SWPHY=y
++CONFIG_FIXED_PHY=y
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_ADIN_PHY is not set
++# CONFIG_AQUANTIA_PHY is not set
++# CONFIG_AX88796B_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_BCM54140_PHY is not set
++# CONFIG_BCM7XXX_PHY is not set
++# CONFIG_BCM84881_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_CORTINA_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_INTEL_XWAY_PHY is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_MARVELL_10G_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_MICROCHIP_PHY is not set
++# CONFIG_MICROCHIP_T1_PHY is not set
++# CONFIG_MICROSEMI_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_RENESAS_PHY is not set
++# CONFIG_ROCKCHIP_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_TERANETICS_PHY is not set
++# CONFIG_DP83822_PHY is not set
++# CONFIG_DP83TC811_PHY is not set
++# CONFIG_DP83848_PHY is not set
++# CONFIG_DP83867_PHY is not set
++# CONFIG_DP83869_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_XILINX_GMII2RGMII is not set
++# CONFIG_MICREL_KS8995MA is not set
++CONFIG_MDIO_DEVICE=y
++CONFIG_MDIO_BUS=y
++CONFIG_OF_MDIO=y
++CONFIG_MDIO_DEVRES=y
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MDIO_BCM_UNIMAC is not set
++# CONFIG_MDIO_HISI_FEMAC is not set
++# CONFIG_MDIO_MVUSB is not set
++# CONFIG_MDIO_MSCC_MIIM is not set
++# CONFIG_MDIO_IPQ4019 is not set
++# CONFIG_MDIO_IPQ8064 is not set
++
++#
++# MDIO Multiplexers
++#
++# CONFIG_MDIO_BUS_MUX_GPIO is not set
++# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
++
++#
++# PCS device drivers
++#
++# CONFIG_PCS_XPCS is not set
++# end of PCS device drivers
++
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++CONFIG_USB_NET_DRIVERS=y
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_RTL8152 is not set
++# CONFIG_USB_LAN78XX is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_HSO is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++# CONFIG_WIRELESS_WDS is not set
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++# CONFIG_WLAN_VENDOR_BROADCOM is not set
++# CONFIG_WLAN_VENDOR_CISCO is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_MICROCHIP is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++# CONFIG_MAC80211_HWSIM is not set
++# CONFIG_USB_NET_RNDIS_WLAN is not set
++# CONFIG_VIRT_WIFI is not set
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_NETDEVSIM is not set
++# CONFIG_NET_FAILOVER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1050 is not set
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_DLINK_DIR685 is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_OMAP4 is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_CAP11XX is not set
++# CONFIG_KEYBOARD_BCM is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_SERIO_APBPS2 is not set
++# CONFIG_SERIO_GPIO_PS2 is not set
++# CONFIG_USERIO is not set
++# CONFIG_GAMEPORT is not set
++# end of Hardware I/O ports
++# end of Input device support
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_VT_CONSOLE_SLEEP=y
++CONFIG_HW_CONSOLE=y
++CONFIG_VT_HW_CONSOLE_BINDING=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_LDISC_AUTOLOAD=y
++
++#
++# Serial drivers
++#
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX310X is not set
++# CONFIG_SERIAL_UARTLITE is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_SIFIVE is not set
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_FSL_LINFLEXUART is not set
++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
++# CONFIG_SERIAL_SPRD is not set
++# end of Serial drivers
++
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_N_GSM is not set
++CONFIG_NULL_TTY=y
++# CONFIG_TRACE_SINK is not set
++CONFIG_SERIAL_DEV_BUS=y
++CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
++CONFIG_TTY_PRINTK=y
++CONFIG_TTY_PRINTK_LEVEL=6
++# CONFIG_VIRTIO_CONSOLE is not set
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_HW_RANDOM_TIMERIOMEM is not set
++# CONFIG_HW_RANDOM_BA431 is not set
++# CONFIG_HW_RANDOM_CCTRNG is not set
++# CONFIG_HW_RANDOM_XIPHERA is not set
++CONFIG_DEVMEM=y
++# CONFIG_DEVKMEM is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++# CONFIG_XILLYBUS is not set
++# end of Character devices
++
++# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_COMPAT=y
++# CONFIG_I2C_CHARDEV is not set
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_GPMUX is not set
++# CONFIG_I2C_MUX_LTC4306 is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_DEMUX_PINCTRL is not set
++# CONFIG_I2C_MUX_MLXCPLD is not set
++# end of Multiplexer I2C Chip support
++
++CONFIG_I2C_HELPER_AUTO=y
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_CBUS_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_IMG is not set
++# CONFIG_I2C_JZ4780 is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_RK3X is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_XILINX is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++# end of I2C Hardware Bus support
++
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_SLAVE is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# end of I2C support
++
++# CONFIG_I3C is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++# CONFIG_SPI_MEM is not set
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_AXI_SPI_ENGINE is not set
++CONFIG_SPI_BITBANG=y
++# CONFIG_SPI_CADENCE is not set
++# CONFIG_SPI_DESIGNWARE is not set
++# CONFIG_SPI_NXP_FLEXSPI is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_IMG_SPFI is not set
++# CONFIG_SPI_FSL_SPI is not set
++# CONFIG_SPI_OC_TINY is not set
++# CONFIG_SPI_ROCKCHIP is not set
++# CONFIG_SPI_SC18IS602 is not set
++# CONFIG_SPI_SIFIVE is not set
++# CONFIG_SPI_MXIC is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_ZYNQMP_GQSPI is not set
++# CONFIG_SPI_AMD is not set
++
++#
++# SPI Multiplexer support
++#
++# CONFIG_SPI_MUX is not set
++
++#
++# SPI Protocol Masters
++#
++CONFIG_SPI_SPIDEV=y
++# CONFIG_SPI_LOOPBACK_TEST is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_SPI_SLAVE is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++# CONFIG_PPS is not set
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++# end of PTP clock support
++
++CONFIG_PINCTRL=y
++CONFIG_GENERIC_PINCTRL_GROUPS=y
++CONFIG_PINMUX=y
++CONFIG_GENERIC_PINMUX_FUNCTIONS=y
++CONFIG_PINCONF=y
++CONFIG_GENERIC_PINCONF=y
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINCTRL_MCP23S08 is not set
++# CONFIG_PINCTRL_SINGLE is not set
++# CONFIG_PINCTRL_SX150X is not set
++# CONFIG_PINCTRL_STMFX is not set
++# CONFIG_PINCTRL_INGENIC is not set
++# CONFIG_PINCTRL_OCELOT is not set
++
++#
++# Renesas pinctrl drivers
++#
++# end of Renesas pinctrl drivers
++
++CONFIG_GPIOLIB=y
++CONFIG_GPIOLIB_FASTPATH_LIMIT=512
++CONFIG_OF_GPIO=y
++CONFIG_GPIOLIB_IRQCHIP=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_CDEV=y
++CONFIG_GPIO_CDEV_V1=y
++
++#
++# Memory mapped GPIO drivers
++#
++# CONFIG_GPIO_74XX_MMIO is not set
++# CONFIG_GPIO_ALTERA is not set
++# CONFIG_GPIO_CADENCE is not set
++# CONFIG_GPIO_DWAPB is not set
++# CONFIG_GPIO_FTGPIO010 is not set
++# CONFIG_GPIO_GENERIC_PLATFORM is not set
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_HLWD is not set
++# CONFIG_GPIO_LOGICVC is not set
++# CONFIG_GPIO_MB86S7X is not set
++# CONFIG_GPIO_SAMA5D2_PIOBU is not set
++# CONFIG_GPIO_SIFIVE is not set
++# CONFIG_GPIO_SYSCON is not set
++# CONFIG_GPIO_XILINX is not set
++# CONFIG_GPIO_AMD_FCH is not set
++# end of Memory mapped GPIO drivers
++
++#
++# I2C GPIO expanders
++#
++# CONFIG_GPIO_ADP5588 is not set
++# CONFIG_GPIO_ADNP is not set
++# CONFIG_GPIO_GW_PLD is not set
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCA9570 is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_TPIC2810 is not set
++# end of I2C GPIO expanders
++
++#
++# MFD GPIO expanders
++#
++# end of MFD GPIO expanders
++
++#
++# SPI GPIO expanders
++#
++# CONFIG_GPIO_74X164 is not set
++# CONFIG_GPIO_MAX3191X is not set
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_PISOSR is not set
++# CONFIG_GPIO_XRA1403 is not set
++# end of SPI GPIO expanders
++
++#
++# USB GPIO expanders
++#
++# end of USB GPIO expanders
++
++# CONFIG_GPIO_AGGREGATOR is not set
++# CONFIG_GPIO_MOCKUP is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_RESET is not set
++# CONFIG_POWER_SUPPLY is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++CONFIG_WATCHDOG=y
++CONFIG_WATCHDOG_CORE=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
++CONFIG_WATCHDOG_OPEN_TIMEOUT=0
++# CONFIG_WATCHDOG_SYSFS is not set
++
++#
++# Watchdog Pretimeout Governors
++#
++# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++# CONFIG_GPIO_WATCHDOG is not set
++# CONFIG_XILINX_WATCHDOG is not set
++# CONFIG_ZIIRAVE_WATCHDOG is not set
++# CONFIG_CADENCE_WATCHDOG is not set
++# CONFIG_DW_WATCHDOG is not set
++# CONFIG_MAX63XX_WATCHDOG is not set
++# CONFIG_JZ4740_WDT is not set
++# CONFIG_IMGPDC_WDT is not set
++# CONFIG_MEN_A21_WDT is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=y
++# CONFIG_MFD_ACT8945A is not set
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_ATMEL_FLEXCOM is not set
++# CONFIG_MFD_ATMEL_HLCDC is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_BD9571MWV is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_MADERA is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_GATEWORKS_GSC is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_MP2629 is not set
++# CONFIG_MFD_HI6421_PMIC is not set
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_MFD_IQS62X is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77620 is not set
++# CONFIG_MFD_MAX77650 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6360 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_CPCAP is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_RK808 is not set
++# CONFIG_MFD_RN5T618 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_STMPE is not set
++CONFIG_MFD_SYSCON=y
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_TI_LMU is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TI_LP87565 is not set
++# CONFIG_MFD_TPS65218 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TQMX86 is not set
++# CONFIG_MFD_LOCHNAGAR is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_MFD_ROHM_BD718XX is not set
++# CONFIG_MFD_ROHM_BD70528 is not set
++# CONFIG_MFD_ROHM_BD71828 is not set
++# CONFIG_MFD_STPMIC1 is not set
++# CONFIG_MFD_STMFX is not set
++# CONFIG_RAVE_SP_CORE is not set
++# CONFIG_MFD_INTEL_M10_BMC is not set
++# end of Multifunction device drivers
++
++# CONFIG_REGULATOR is not set
++# CONFIG_RC_CORE is not set
++# CONFIG_MEDIA_CEC_SUPPORT is not set
++CONFIG_MEDIA_SUPPORT=y
++# CONFIG_MEDIA_SUPPORT_FILTER is not set
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++
++#
++# Media device types
++#
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
++CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
++CONFIG_MEDIA_RADIO_SUPPORT=y
++CONFIG_MEDIA_SDR_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++CONFIG_MEDIA_TEST_SUPPORT=y
++# end of Media device types
++
++#
++# Media core support
++#
++CONFIG_VIDEO_DEV=y
++CONFIG_MEDIA_CONTROLLER=y
++CONFIG_DVB_CORE=y
++# end of Media core support
++
++#
++# Video4Linux options
++#
++CONFIG_VIDEO_V4L2=y
++CONFIG_VIDEO_V4L2_I2C=y
++CONFIG_VIDEO_V4L2_SUBDEV_API=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++CONFIG_V4L2_MEM2MEM_DEV=y
++CONFIG_V4L2_FWNODE=y
++# end of Video4Linux options
++
++#
++# Media controller options
++#
++# CONFIG_MEDIA_CONTROLLER_DVB is not set
++# end of Media controller options
++
++#
++# Digital TV options
++#
++# CONFIG_DVB_MMAP is not set
++CONFIG_DVB_NET=y
++CONFIG_DVB_MAX_ADAPTERS=16
++CONFIG_DVB_DYNAMIC_MINORS=y
++# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
++# CONFIG_DVB_ULE_DEBUG is not set
++# end of Digital TV options
++
++#
++# Media drivers
++#
++CONFIG_MEDIA_USB_SUPPORT=y
++
++#
++# Webcam devices
++#
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++# CONFIG_USB_GSPCA is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_USB_ZR364XX is not set
++# CONFIG_USB_STKWEBCAM is not set
++# CONFIG_USB_S2255 is not set
++# CONFIG_VIDEO_USBTV is not set
++
++#
++# Analog TV USB devices
++#
++# CONFIG_VIDEO_PVRUSB2 is not set
++# CONFIG_VIDEO_HDPVR is not set
++# CONFIG_VIDEO_STK1160_COMMON is not set
++# CONFIG_VIDEO_GO7007 is not set
++
++#
++# Analog/digital TV USB devices
++#
++# CONFIG_VIDEO_AU0828 is not set
++# CONFIG_VIDEO_CX231XX is not set
++
++#
++# Digital TV USB devices
++#
++# CONFIG_DVB_USB_V2 is not set
++# CONFIG_SMS_USB_DRV is not set
++# CONFIG_DVB_B2C2_FLEXCOP_USB is not set
++# CONFIG_DVB_AS102 is not set
++
++#
++# Webcam, TV (analog/digital) USB devices
++#
++# CONFIG_VIDEO_EM28XX is not set
++
++#
++# Software defined radio USB devices
++#
++# CONFIG_USB_AIRSPY is not set
++# CONFIG_USB_HACKRF is not set
++# CONFIG_USB_MSI2500 is not set
++CONFIG_RADIO_ADAPTERS=y
++# CONFIG_RADIO_SI470X is not set
++# CONFIG_RADIO_SI4713 is not set
++# CONFIG_USB_MR800 is not set
++# CONFIG_USB_DSBR is not set
++# CONFIG_RADIO_SHARK is not set
++# CONFIG_RADIO_SHARK2 is not set
++# CONFIG_USB_KEENE is not set
++# CONFIG_USB_RAREMONO is not set
++# CONFIG_USB_MA901 is not set
++# CONFIG_RADIO_TEA5764 is not set
++# CONFIG_RADIO_SAA7706H is not set
++# CONFIG_RADIO_TEF6862 is not set
++# CONFIG_RADIO_WL1273 is not set
++CONFIG_VIDEOBUF2_CORE=y
++CONFIG_VIDEOBUF2_V4L2=y
++CONFIG_VIDEOBUF2_MEMOPS=y
++CONFIG_VIDEOBUF2_DMA_CONTIG=y
++CONFIG_VIDEOBUF2_VMALLOC=y
++CONFIG_VIDEOBUF2_DMA_SG=y
++CONFIG_V4L_PLATFORM_DRIVERS=y
++# CONFIG_VIDEO_CADENCE is not set
++# CONFIG_VIDEO_ASPEED is not set
++# CONFIG_VIDEO_MUX is not set
++# CONFIG_VIDEO_XILINX is not set
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
++# CONFIG_DVB_PLATFORM_DRIVERS is not set
++# CONFIG_SDR_PLATFORM_DRIVERS is not set
++
++#
++# MMC/SDIO DVB adapters
++#
++# CONFIG_SMS_SDIO_DRV is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++# CONFIG_DVB_TEST_DRIVERS is not set
++# end of Media drivers
++
++#
++# Media ancillary drivers
++#
++CONFIG_MEDIA_ATTACH=y
++
++#
++# Audio decoders, processors and mixers
++#
++# CONFIG_VIDEO_TVAUDIO is not set
++# CONFIG_VIDEO_TDA7432 is not set
++# CONFIG_VIDEO_TDA9840 is not set
++# CONFIG_VIDEO_TDA1997X is not set
++# CONFIG_VIDEO_TEA6415C is not set
++# CONFIG_VIDEO_TEA6420 is not set
++# CONFIG_VIDEO_MSP3400 is not set
++# CONFIG_VIDEO_CS3308 is not set
++# CONFIG_VIDEO_CS5345 is not set
++# CONFIG_VIDEO_CS53L32A is not set
++# CONFIG_VIDEO_TLV320AIC23B is not set
++# CONFIG_VIDEO_UDA1342 is not set
++# CONFIG_VIDEO_WM8775 is not set
++# CONFIG_VIDEO_WM8739 is not set
++# CONFIG_VIDEO_VP27SMPX is not set
++# CONFIG_VIDEO_SONY_BTF_MPX is not set
++# end of Audio decoders, processors and mixers
++
++#
++# RDS decoders
++#
++# CONFIG_VIDEO_SAA6588 is not set
++# end of RDS decoders
++
++#
++# Video decoders
++#
++# CONFIG_VIDEO_ADV7180 is not set
++# CONFIG_VIDEO_ADV7183 is not set
++# CONFIG_VIDEO_ADV748X is not set
++# CONFIG_VIDEO_ADV7604 is not set
++# CONFIG_VIDEO_ADV7842 is not set
++# CONFIG_VIDEO_BT819 is not set
++# CONFIG_VIDEO_BT856 is not set
++# CONFIG_VIDEO_BT866 is not set
++# CONFIG_VIDEO_KS0127 is not set
++# CONFIG_VIDEO_ML86V7667 is not set
++# CONFIG_VIDEO_SAA7110 is not set
++# CONFIG_VIDEO_SAA711X is not set
++# CONFIG_VIDEO_TC358743 is not set
++# CONFIG_VIDEO_TVP514X is not set
++# CONFIG_VIDEO_TVP5150 is not set
++# CONFIG_VIDEO_TVP7002 is not set
++# CONFIG_VIDEO_TW2804 is not set
++# CONFIG_VIDEO_TW9903 is not set
++# CONFIG_VIDEO_TW9906 is not set
++# CONFIG_VIDEO_TW9910 is not set
++# CONFIG_VIDEO_VPX3220 is not set
++# CONFIG_VIDEO_MAX9286 is not set
++
++#
++# Video and audio decoders
++#
++# CONFIG_VIDEO_SAA717X is not set
++# CONFIG_VIDEO_CX25840 is not set
++# end of Video decoders
++
++#
++# Video encoders
++#
++# CONFIG_VIDEO_SAA7127 is not set
++# CONFIG_VIDEO_SAA7185 is not set
++# CONFIG_VIDEO_ADV7170 is not set
++# CONFIG_VIDEO_ADV7175 is not set
++# CONFIG_VIDEO_ADV7343 is not set
++# CONFIG_VIDEO_ADV7393 is not set
++# CONFIG_VIDEO_ADV7511 is not set
++# CONFIG_VIDEO_AD9389B is not set
++# CONFIG_VIDEO_AK881X is not set
++# CONFIG_VIDEO_THS8200 is not set
++# end of Video encoders
++
++#
++# Video improvement chips
++#
++# CONFIG_VIDEO_UPD64031A is not set
++# CONFIG_VIDEO_UPD64083 is not set
++# end of Video improvement chips
++
++#
++# Audio/Video compression chips
++#
++# CONFIG_VIDEO_SAA6752HS is not set
++# end of Audio/Video compression chips
++
++#
++# SDR tuner chips
++#
++# CONFIG_SDR_MAX2175 is not set
++# end of SDR tuner chips
++
++#
++# Miscellaneous helper chips
++#
++# CONFIG_VIDEO_THS7303 is not set
++# CONFIG_VIDEO_M52790 is not set
++# CONFIG_VIDEO_I2C is not set
++# CONFIG_VIDEO_ST_MIPID02 is not set
++# end of Miscellaneous helper chips
++
++#
++# Camera sensor devices
++#
++# CONFIG_VIDEO_HI556 is not set
++# CONFIG_VIDEO_IMX214 is not set
++# CONFIG_VIDEO_IMX219 is not set
++# CONFIG_VIDEO_IMX258 is not set
++# CONFIG_VIDEO_IMX274 is not set
++# CONFIG_VIDEO_IMX290 is not set
++# CONFIG_VIDEO_IMX319 is not set
++# CONFIG_VIDEO_IMX355 is not set
++# CONFIG_VIDEO_OV2640 is not set
++# CONFIG_VIDEO_OV2659 is not set
++# CONFIG_VIDEO_OV2680 is not set
++# CONFIG_VIDEO_OV2685 is not set
++# CONFIG_VIDEO_OV5640 is not set
++# CONFIG_VIDEO_OV5645 is not set
++# CONFIG_VIDEO_OV5647 is not set
++# CONFIG_VIDEO_OV6650 is not set
++# CONFIG_VIDEO_OV5670 is not set
++# CONFIG_VIDEO_OV5675 is not set
++# CONFIG_VIDEO_OV5695 is not set
++# CONFIG_VIDEO_OV7251 is not set
++# CONFIG_VIDEO_OV772X is not set
++# CONFIG_VIDEO_OV7640 is not set
++# CONFIG_VIDEO_OV7670 is not set
++# CONFIG_VIDEO_OV7740 is not set
++CONFIG_VIDEO_OV8856=y
++# CONFIG_VIDEO_OV9640 is not set
++# CONFIG_VIDEO_OV9650 is not set
++# CONFIG_VIDEO_OV13858 is not set
++# CONFIG_VIDEO_VS6624 is not set
++# CONFIG_VIDEO_MT9M001 is not set
++# CONFIG_VIDEO_MT9M032 is not set
++# CONFIG_VIDEO_MT9M111 is not set
++# CONFIG_VIDEO_MT9P031 is not set
++# CONFIG_VIDEO_MT9T001 is not set
++# CONFIG_VIDEO_MT9T112 is not set
++# CONFIG_VIDEO_MT9V011 is not set
++# CONFIG_VIDEO_MT9V032 is not set
++# CONFIG_VIDEO_MT9V111 is not set
++# CONFIG_VIDEO_SR030PC30 is not set
++# CONFIG_VIDEO_NOON010PC30 is not set
++# CONFIG_VIDEO_M5MOLS is not set
++# CONFIG_VIDEO_RDACM20 is not set
++# CONFIG_VIDEO_RJ54N1 is not set
++# CONFIG_VIDEO_S5K6AA is not set
++# CONFIG_VIDEO_S5K6A3 is not set
++# CONFIG_VIDEO_S5K4ECGX is not set
++# CONFIG_VIDEO_S5K5BAF is not set
++# CONFIG_VIDEO_SMIAPP is not set
++# CONFIG_VIDEO_ET8EK8 is not set
++# CONFIG_VIDEO_S5C73M3 is not set
++# end of Camera sensor devices
++
++#
++# Lens drivers
++#
++# CONFIG_VIDEO_AD5820 is not set
++# CONFIG_VIDEO_AK7375 is not set
++# CONFIG_VIDEO_DW9714 is not set
++# CONFIG_VIDEO_DW9768 is not set
++# CONFIG_VIDEO_DW9807_VCM is not set
++# end of Lens drivers
++
++#
++# Flash devices
++#
++# CONFIG_VIDEO_ADP1653 is not set
++# CONFIG_VIDEO_LM3560 is not set
++# CONFIG_VIDEO_LM3646 is not set
++# end of Flash devices
++
++#
++# SPI helper chips
++#
++# CONFIG_VIDEO_GS1662 is not set
++# end of SPI helper chips
++
++#
++# Media SPI Adapters
++#
++CONFIG_CXD2880_SPI_DRV=m
++# end of Media SPI Adapters
++
++CONFIG_MEDIA_TUNER=y
++
++#
++# Customize TV tuners
++#
++# CONFIG_MEDIA_TUNER_SIMPLE is not set
++# CONFIG_MEDIA_TUNER_TDA18250 is not set
++# CONFIG_MEDIA_TUNER_TDA8290 is not set
++# CONFIG_MEDIA_TUNER_TDA827X is not set
++# CONFIG_MEDIA_TUNER_TDA18271 is not set
++# CONFIG_MEDIA_TUNER_TDA9887 is not set
++# CONFIG_MEDIA_TUNER_TEA5761 is not set
++# CONFIG_MEDIA_TUNER_TEA5767 is not set
++CONFIG_MEDIA_TUNER_MSI001=m
++# CONFIG_MEDIA_TUNER_MT20XX is not set
++# CONFIG_MEDIA_TUNER_MT2060 is not set
++# CONFIG_MEDIA_TUNER_MT2063 is not set
++# CONFIG_MEDIA_TUNER_MT2266 is not set
++# CONFIG_MEDIA_TUNER_MT2131 is not set
++# CONFIG_MEDIA_TUNER_QT1010 is not set
++# CONFIG_MEDIA_TUNER_XC2028 is not set
++# CONFIG_MEDIA_TUNER_XC5000 is not set
++# CONFIG_MEDIA_TUNER_XC4000 is not set
++# CONFIG_MEDIA_TUNER_MXL5005S is not set
++# CONFIG_MEDIA_TUNER_MXL5007T is not set
++# CONFIG_MEDIA_TUNER_MC44S803 is not set
++# CONFIG_MEDIA_TUNER_MAX2165 is not set
++# CONFIG_MEDIA_TUNER_TDA18218 is not set
++# CONFIG_MEDIA_TUNER_FC0011 is not set
++# CONFIG_MEDIA_TUNER_FC0012 is not set
++# CONFIG_MEDIA_TUNER_FC0013 is not set
++# CONFIG_MEDIA_TUNER_TDA18212 is not set
++# CONFIG_MEDIA_TUNER_E4000 is not set
++# CONFIG_MEDIA_TUNER_FC2580 is not set
++# CONFIG_MEDIA_TUNER_M88RS6000T is not set
++# CONFIG_MEDIA_TUNER_TUA9001 is not set
++# CONFIG_MEDIA_TUNER_SI2157 is not set
++# CONFIG_MEDIA_TUNER_IT913X is not set
++# CONFIG_MEDIA_TUNER_R820T is not set
++# CONFIG_MEDIA_TUNER_MXL301RF is not set
++# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
++# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
++# end of Customize TV tuners
++
++#
++# Customise DVB Frontends
++#
++
++#
++# Multistandard (satellite) frontends
++#
++# CONFIG_DVB_STB0899 is not set
++# CONFIG_DVB_STB6100 is not set
++# CONFIG_DVB_STV090x is not set
++# CONFIG_DVB_STV0910 is not set
++# CONFIG_DVB_STV6110x is not set
++# CONFIG_DVB_STV6111 is not set
++# CONFIG_DVB_MXL5XX is not set
++# CONFIG_DVB_M88DS3103 is not set
++
++#
++# Multistandard (cable + terrestrial) frontends
++#
++# CONFIG_DVB_DRXK is not set
++# CONFIG_DVB_TDA18271C2DD is not set
++# CONFIG_DVB_SI2165 is not set
++# CONFIG_DVB_MN88472 is not set
++# CONFIG_DVB_MN88473 is not set
++
++#
++# DVB-S (satellite) frontends
++#
++# CONFIG_DVB_CX24110 is not set
++# CONFIG_DVB_CX24123 is not set
++# CONFIG_DVB_MT312 is not set
++# CONFIG_DVB_ZL10036 is not set
++# CONFIG_DVB_ZL10039 is not set
++# CONFIG_DVB_S5H1420 is not set
++# CONFIG_DVB_STV0288 is not set
++# CONFIG_DVB_STB6000 is not set
++# CONFIG_DVB_STV0299 is not set
++# CONFIG_DVB_STV6110 is not set
++# CONFIG_DVB_STV0900 is not set
++# CONFIG_DVB_TDA8083 is not set
++# CONFIG_DVB_TDA10086 is not set
++# CONFIG_DVB_TDA8261 is not set
++# CONFIG_DVB_VES1X93 is not set
++# CONFIG_DVB_TUNER_ITD1000 is not set
++# CONFIG_DVB_TUNER_CX24113 is not set
++# CONFIG_DVB_TDA826X is not set
++# CONFIG_DVB_TUA6100 is not set
++# CONFIG_DVB_CX24116 is not set
++# CONFIG_DVB_CX24117 is not set
++# CONFIG_DVB_CX24120 is not set
++# CONFIG_DVB_SI21XX is not set
++# CONFIG_DVB_TS2020 is not set
++# CONFIG_DVB_DS3000 is not set
++# CONFIG_DVB_MB86A16 is not set
++# CONFIG_DVB_TDA10071 is not set
++
++#
++# DVB-T (terrestrial) frontends
++#
++# CONFIG_DVB_SP8870 is not set
++# CONFIG_DVB_SP887X is not set
++# CONFIG_DVB_CX22700 is not set
++# CONFIG_DVB_CX22702 is not set
++# CONFIG_DVB_S5H1432 is not set
++# CONFIG_DVB_DRXD is not set
++# CONFIG_DVB_L64781 is not set
++# CONFIG_DVB_TDA1004X is not set
++# CONFIG_DVB_NXT6000 is not set
++# CONFIG_DVB_MT352 is not set
++# CONFIG_DVB_ZL10353 is not set
++# CONFIG_DVB_DIB3000MB is not set
++# CONFIG_DVB_DIB3000MC is not set
++# CONFIG_DVB_DIB7000M is not set
++# CONFIG_DVB_DIB7000P is not set
++# CONFIG_DVB_DIB9000 is not set
++# CONFIG_DVB_TDA10048 is not set
++# CONFIG_DVB_AF9013 is not set
++# CONFIG_DVB_EC100 is not set
++# CONFIG_DVB_STV0367 is not set
++# CONFIG_DVB_CXD2820R is not set
++# CONFIG_DVB_CXD2841ER is not set
++# CONFIG_DVB_RTL2830 is not set
++# CONFIG_DVB_RTL2832 is not set
++# CONFIG_DVB_RTL2832_SDR is not set
++# CONFIG_DVB_SI2168 is not set
++# CONFIG_DVB_ZD1301_DEMOD is not set
++CONFIG_DVB_CXD2880=m
++
++#
++# DVB-C (cable) frontends
++#
++# CONFIG_DVB_VES1820 is not set
++# CONFIG_DVB_TDA10021 is not set
++# CONFIG_DVB_TDA10023 is not set
++# CONFIG_DVB_STV0297 is not set
++
++#
++# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
++#
++# CONFIG_DVB_NXT200X is not set
++# CONFIG_DVB_OR51211 is not set
++# CONFIG_DVB_OR51132 is not set
++# CONFIG_DVB_BCM3510 is not set
++# CONFIG_DVB_LGDT330X is not set
++# CONFIG_DVB_LGDT3305 is not set
++# CONFIG_DVB_LGDT3306A is not set
++# CONFIG_DVB_LG2160 is not set
++# CONFIG_DVB_S5H1409 is not set
++# CONFIG_DVB_AU8522_DTV is not set
++# CONFIG_DVB_AU8522_V4L is not set
++# CONFIG_DVB_S5H1411 is not set
++
++#
++# ISDB-T (terrestrial) frontends
++#
++# CONFIG_DVB_S921 is not set
++# CONFIG_DVB_DIB8000 is not set
++# CONFIG_DVB_MB86A20S is not set
++
++#
++# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
++#
++# CONFIG_DVB_TC90522 is not set
++# CONFIG_DVB_MN88443X is not set
++
++#
++# Digital terrestrial only tuners/PLL
++#
++# CONFIG_DVB_PLL is not set
++# CONFIG_DVB_TUNER_DIB0070 is not set
++# CONFIG_DVB_TUNER_DIB0090 is not set
++
++#
++# SEC control devices for DVB-S
++#
++# CONFIG_DVB_DRX39XYJ is not set
++# CONFIG_DVB_LNBH25 is not set
++# CONFIG_DVB_LNBH29 is not set
++# CONFIG_DVB_LNBP21 is not set
++# CONFIG_DVB_LNBP22 is not set
++# CONFIG_DVB_ISL6405 is not set
++# CONFIG_DVB_ISL6421 is not set
++# CONFIG_DVB_ISL6423 is not set
++# CONFIG_DVB_A8293 is not set
++# CONFIG_DVB_LGS8GL5 is not set
++# CONFIG_DVB_LGS8GXX is not set
++# CONFIG_DVB_ATBM8830 is not set
++# CONFIG_DVB_TDA665x is not set
++# CONFIG_DVB_IX2505V is not set
++# CONFIG_DVB_M88RS2000 is not set
++# CONFIG_DVB_AF9033 is not set
++# CONFIG_DVB_HORUS3A is not set
++# CONFIG_DVB_ASCOT2E is not set
++# CONFIG_DVB_HELENE is not set
++
++#
++# Common Interface (EN50221) controller drivers
++#
++# CONFIG_DVB_CXD2099 is not set
++# CONFIG_DVB_SP2 is not set
++# end of Customise DVB Frontends
++
++#
++# Tools to develop new frontends
++#
++# CONFIG_DVB_DUMMY_FE is not set
++# end of Media ancillary drivers
++
++#
++# Graphics support
++#
++# CONFIG_DRM is not set
++
++#
++# ARM devices
++#
++# end of ARM devices
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_SIMPLE is not set
++# CONFIG_FB_SSD1307 is not set
++# end of Frame buffer Devices
++
++#
++# Backlight & LCD device support
++#
++CONFIG_LCD_CLASS_DEVICE=y
++# CONFIG_LCD_L4F00242T03 is not set
++# CONFIG_LCD_LMS283GF05 is not set
++# CONFIG_LCD_LTV350QV is not set
++# CONFIG_LCD_ILI922X is not set
++# CONFIG_LCD_ILI9320 is not set
++# CONFIG_LCD_TDO24M is not set
++# CONFIG_LCD_VGG2432A4 is not set
++# CONFIG_LCD_PLATFORM is not set
++# CONFIG_LCD_AMS369FG06 is not set
++# CONFIG_LCD_LMS501KF03 is not set
++# CONFIG_LCD_HX8357 is not set
++# CONFIG_LCD_OTM3225A is not set
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++# CONFIG_BACKLIGHT_KTD253 is not set
++CONFIG_BACKLIGHT_PWM=y
++# CONFIG_BACKLIGHT_QCOM_WLED is not set
++# CONFIG_BACKLIGHT_ADP8860 is not set
++# CONFIG_BACKLIGHT_ADP8870 is not set
++# CONFIG_BACKLIGHT_LM3630A is not set
++# CONFIG_BACKLIGHT_LM3639 is not set
++# CONFIG_BACKLIGHT_LP855X is not set
++CONFIG_BACKLIGHT_GPIO=y
++# CONFIG_BACKLIGHT_LV5207LP is not set
++# CONFIG_BACKLIGHT_BD6107 is not set
++# CONFIG_BACKLIGHT_ARCXCNN is not set
++# end of Backlight & LCD device support
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_DUMMY_CONSOLE_COLUMNS=80
++CONFIG_DUMMY_CONSOLE_ROWS=25
++# CONFIG_FRAMEBUFFER_CONSOLE is not set
++# end of Console display driver support
++
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++# end of Graphics support
++
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++CONFIG_SND_JACK=y
++CONFIG_SND_JACK_INPUT_DEV=y
++# CONFIG_SND_OSSEMUL is not set
++CONFIG_SND_PCM_TIMER=y
++# CONFIG_SND_HRTIMER is not set
++CONFIG_SND_DYNAMIC_MINORS=y
++CONFIG_SND_MAX_CARDS=32
++CONFIG_SND_SUPPORT_OLD_API=y
++CONFIG_SND_PROC_FS=y
++CONFIG_SND_VERBOSE_PROCFS=y
++# CONFIG_SND_VERBOSE_PRINTK is not set
++# CONFIG_SND_DEBUG is not set
++# CONFIG_SND_SEQUENCER is not set
++CONFIG_SND_DRIVERS=y
++# CONFIG_SND_DUMMY is not set
++# CONFIG_SND_ALOOP is not set
++# CONFIG_SND_MTPAV is not set
++# CONFIG_SND_SERIAL_U16550 is not set
++# CONFIG_SND_MPU401 is not set
++
++#
++# HD-Audio
++#
++# end of HD-Audio
++
++CONFIG_SND_HDA_PREALLOC_SIZE=64
++CONFIG_SND_SPI=y
++# CONFIG_SND_MIPS is not set
++# CONFIG_SND_USB is not set
++CONFIG_SND_SOC=y
++# CONFIG_SND_SOC_AMD_ACP is not set
++# CONFIG_SND_ATMEL_SOC is not set
++# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
++# CONFIG_SND_DESIGNWARE_I2S is not set
++
++#
++# SoC Audio for Freescale CPUs
++#
++
++#
++# Common SoC Audio options for Freescale CPUs:
++#
++# CONFIG_SND_SOC_FSL_ASRC is not set
++# CONFIG_SND_SOC_FSL_SAI is not set
++# CONFIG_SND_SOC_FSL_AUDMIX is not set
++# CONFIG_SND_SOC_FSL_SSI is not set
++# CONFIG_SND_SOC_FSL_SPDIF is not set
++# CONFIG_SND_SOC_FSL_ESAI is not set
++# CONFIG_SND_SOC_FSL_MICFIL is not set
++# CONFIG_SND_SOC_IMX_AUDMUX is not set
++# end of SoC Audio for Freescale CPUs
++
++# CONFIG_SND_I2S_HI6210_I2S is not set
++# CONFIG_SND_JZ4740_SOC_I2S is not set
++# CONFIG_SND_SOC_IMG is not set
++# CONFIG_SND_SOC_MTK_BTCVSD is not set
++# CONFIG_SND_SOC_SOF_TOPLEVEL is not set
++
++#
++# STMicroelectronics STM32 SOC audio support
++#
++# end of STMicroelectronics STM32 SOC audio support
++
++# CONFIG_SND_SOC_XILINX_I2S is not set
++# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
++# CONFIG_SND_SOC_XILINX_SPDIF is not set
++# CONFIG_SND_SOC_XTFPGA_I2S is not set
++# CONFIG_ZX_TDM is not set
++CONFIG_SND_SOC_I2C_AND_SPI=y
++
++#
++# CODEC drivers
++#
++# CONFIG_SND_SOC_AC97_CODEC is not set
++# CONFIG_SND_SOC_ADAU1701 is not set
++# CONFIG_SND_SOC_ADAU1761_I2C is not set
++# CONFIG_SND_SOC_ADAU1761_SPI is not set
++# CONFIG_SND_SOC_ADAU7002 is not set
++# CONFIG_SND_SOC_ADAU7118_HW is not set
++# CONFIG_SND_SOC_ADAU7118_I2C is not set
++# CONFIG_SND_SOC_AK4104 is not set
++# CONFIG_SND_SOC_AK4118 is not set
++# CONFIG_SND_SOC_AK4458 is not set
++# CONFIG_SND_SOC_AK4554 is not set
++# CONFIG_SND_SOC_AK4613 is not set
++# CONFIG_SND_SOC_AK4642 is not set
++# CONFIG_SND_SOC_AK5386 is not set
++# CONFIG_SND_SOC_AK5558 is not set
++# CONFIG_SND_SOC_ALC5623 is not set
++# CONFIG_SND_SOC_BD28623 is not set
++# CONFIG_SND_SOC_BT_SCO is not set
++# CONFIG_SND_SOC_CS35L32 is not set
++# CONFIG_SND_SOC_CS35L33 is not set
++# CONFIG_SND_SOC_CS35L34 is not set
++# CONFIG_SND_SOC_CS35L35 is not set
++# CONFIG_SND_SOC_CS35L36 is not set
++# CONFIG_SND_SOC_CS42L42 is not set
++# CONFIG_SND_SOC_CS42L51_I2C is not set
++# CONFIG_SND_SOC_CS42L52 is not set
++# CONFIG_SND_SOC_CS42L56 is not set
++# CONFIG_SND_SOC_CS42L73 is not set
++# CONFIG_SND_SOC_CS4234 is not set
++# CONFIG_SND_SOC_CS4265 is not set
++# CONFIG_SND_SOC_CS4270 is not set
++# CONFIG_SND_SOC_CS4271_I2C is not set
++# CONFIG_SND_SOC_CS4271_SPI is not set
++# CONFIG_SND_SOC_CS42XX8_I2C is not set
++# CONFIG_SND_SOC_CS43130 is not set
++# CONFIG_SND_SOC_CS4341 is not set
++# CONFIG_SND_SOC_CS4349 is not set
++# CONFIG_SND_SOC_CS53L30 is not set
++# CONFIG_SND_SOC_CX2072X is not set
++# CONFIG_SND_SOC_JZ4740_CODEC is not set
++# CONFIG_SND_SOC_JZ4725B_CODEC is not set
++# CONFIG_SND_SOC_JZ4770_CODEC is not set
++# CONFIG_SND_SOC_DA7213 is not set
++# CONFIG_SND_SOC_DMIC is not set
++# CONFIG_SND_SOC_ES7134 is not set
++# CONFIG_SND_SOC_ES7241 is not set
++# CONFIG_SND_SOC_ES8316 is not set
++# CONFIG_SND_SOC_ES8328_I2C is not set
++# CONFIG_SND_SOC_ES8328_SPI is not set
++# CONFIG_SND_SOC_GTM601 is not set
++# CONFIG_SND_SOC_INNO_RK3036 is not set
++# CONFIG_SND_SOC_MAX98088 is not set
++# CONFIG_SND_SOC_MAX98357A is not set
++# CONFIG_SND_SOC_MAX98504 is not set
++# CONFIG_SND_SOC_MAX9867 is not set
++# CONFIG_SND_SOC_MAX98927 is not set
++# CONFIG_SND_SOC_MAX98373_I2C is not set
++# CONFIG_SND_SOC_MAX98390 is not set
++# CONFIG_SND_SOC_MAX9860 is not set
++# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set
++# CONFIG_SND_SOC_PCM1681 is not set
++# CONFIG_SND_SOC_PCM1789_I2C is not set
++# CONFIG_SND_SOC_PCM179X_I2C is not set
++# CONFIG_SND_SOC_PCM179X_SPI is not set
++# CONFIG_SND_SOC_PCM186X_I2C is not set
++# CONFIG_SND_SOC_PCM186X_SPI is not set
++# CONFIG_SND_SOC_PCM3060_I2C is not set
++# CONFIG_SND_SOC_PCM3060_SPI is not set
++# CONFIG_SND_SOC_PCM3168A_I2C is not set
++# CONFIG_SND_SOC_PCM3168A_SPI is not set
++# CONFIG_SND_SOC_PCM512x_I2C is not set
++# CONFIG_SND_SOC_PCM512x_SPI is not set
++# CONFIG_SND_SOC_RK3328 is not set
++# CONFIG_SND_SOC_RT5616 is not set
++# CONFIG_SND_SOC_RT5631 is not set
++# CONFIG_SND_SOC_SGTL5000 is not set
++# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set
++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set
++# CONFIG_SND_SOC_SPDIF is not set
++# CONFIG_SND_SOC_SSM2305 is not set
++# CONFIG_SND_SOC_SSM2602_SPI is not set
++# CONFIG_SND_SOC_SSM2602_I2C is not set
++# CONFIG_SND_SOC_SSM4567 is not set
++# CONFIG_SND_SOC_STA32X is not set
++# CONFIG_SND_SOC_STA350 is not set
++# CONFIG_SND_SOC_STI_SAS is not set
++# CONFIG_SND_SOC_TAS2552 is not set
++# CONFIG_SND_SOC_TAS2562 is not set
++# CONFIG_SND_SOC_TAS2764 is not set
++# CONFIG_SND_SOC_TAS2770 is not set
++# CONFIG_SND_SOC_TAS5086 is not set
++# CONFIG_SND_SOC_TAS571X is not set
++# CONFIG_SND_SOC_TAS5720 is not set
++# CONFIG_SND_SOC_TAS6424 is not set
++# CONFIG_SND_SOC_TDA7419 is not set
++# CONFIG_SND_SOC_TFA9879 is not set
++# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
++# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
++# CONFIG_SND_SOC_TLV320AIC31XX is not set
++# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
++# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
++# CONFIG_SND_SOC_TLV320AIC3X is not set
++# CONFIG_SND_SOC_TLV320ADCX140 is not set
++# CONFIG_SND_SOC_TS3A227E is not set
++# CONFIG_SND_SOC_TSCS42XX is not set
++# CONFIG_SND_SOC_TSCS454 is not set
++# CONFIG_SND_SOC_UDA1334 is not set
++# CONFIG_SND_SOC_WM8510 is not set
++# CONFIG_SND_SOC_WM8523 is not set
++# CONFIG_SND_SOC_WM8524 is not set
++# CONFIG_SND_SOC_WM8580 is not set
++# CONFIG_SND_SOC_WM8711 is not set
++# CONFIG_SND_SOC_WM8728 is not set
++# CONFIG_SND_SOC_WM8731 is not set
++# CONFIG_SND_SOC_WM8737 is not set
++# CONFIG_SND_SOC_WM8741 is not set
++# CONFIG_SND_SOC_WM8750 is not set
++# CONFIG_SND_SOC_WM8753 is not set
++# CONFIG_SND_SOC_WM8770 is not set
++# CONFIG_SND_SOC_WM8776 is not set
++# CONFIG_SND_SOC_WM8782 is not set
++# CONFIG_SND_SOC_WM8804_I2C is not set
++# CONFIG_SND_SOC_WM8804_SPI is not set
++# CONFIG_SND_SOC_WM8903 is not set
++# CONFIG_SND_SOC_WM8904 is not set
++# CONFIG_SND_SOC_WM8960 is not set
++# CONFIG_SND_SOC_WM8962 is not set
++# CONFIG_SND_SOC_WM8974 is not set
++# CONFIG_SND_SOC_WM8978 is not set
++# CONFIG_SND_SOC_WM8985 is not set
++# CONFIG_SND_SOC_ZL38060 is not set
++# CONFIG_SND_SOC_ZX_AUD96P22 is not set
++# CONFIG_SND_SOC_MAX9759 is not set
++# CONFIG_SND_SOC_MT6351 is not set
++# CONFIG_SND_SOC_MT6358 is not set
++# CONFIG_SND_SOC_MT6660 is not set
++# CONFIG_SND_SOC_NAU8540 is not set
++# CONFIG_SND_SOC_NAU8810 is not set
++# CONFIG_SND_SOC_NAU8822 is not set
++# CONFIG_SND_SOC_NAU8824 is not set
++# CONFIG_SND_SOC_TPA6130A2 is not set
++# end of CODEC drivers
++
++# CONFIG_SND_SIMPLE_CARD is not set
++# CONFIG_SND_AUDIO_GRAPH_CARD is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_UHID is not set
++# CONFIG_HID_GENERIC is not set
++
++#
++# Special HID drivers
++#
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_ACRUX is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_AUREAL is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_COUGAR is not set
++# CONFIG_HID_MACALLY is not set
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_GLORIOUS is not set
++# CONFIG_HID_VIVALDI is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_VIEWSONIC is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_ITE is not set
++# CONFIG_HID_JABRA is not set
++# CONFIG_HID_TWINHAN is not set
++# CONFIG_HID_KENSINGTON is not set
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO is not set
++# CONFIG_HID_MAGICMOUSE is not set
++# CONFIG_HID_MALTRON is not set
++# CONFIG_HID_MAYFLASH is not set
++# CONFIG_HID_REDRAGON is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTI is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEAM is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_UDRAW_PS3 is not set
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++# end of Special HID drivers
++
++#
++# USB HID support
++#
++# CONFIG_USB_HID is not set
++# CONFIG_HID_PID is not set
++
++#
++# USB HID Boot Protocol drivers
++#
++CONFIG_USB_KBD=y
++CONFIG_USB_MOUSE=y
++# end of USB HID Boot Protocol drivers
++# end of USB HID support
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID is not set
++# end of I2C HID support
++# end of HID support
++
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++# CONFIG_USB_ULPI_BUS is not set
++# CONFIG_USB_CONN_GPIO is not set
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_FEW_INIT_RETRIES is not set
++# CONFIG_USB_DYNAMIC_MINORS is not set
++CONFIG_USB_OTG=y
++# CONFIG_USB_OTG_PRODUCTLIST is not set
++# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
++# CONFIG_USB_OTG_FSM is not set
++CONFIG_USB_AUTOSUSPEND_DELAY=2
++# CONFIG_USB_MON is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++# CONFIG_USB_XHCI_HCD is not set
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_MAX3421_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++# CONFIG_USB_UAS is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_CDNS3 is not set
++# CONFIG_USB_MUSB_HDRC is not set
++# CONFIG_USB_DWC3 is not set
++CONFIG_USB_DWC2=y
++# CONFIG_USB_DWC2_HOST is not set
++
++#
++# Gadget/Dual-role mode requires USB Gadget support to be enabled
++#
++# CONFIG_USB_DWC2_PERIPHERAL is not set
++CONFIG_USB_DWC2_DUAL_ROLE=y
++# CONFIG_USB_DWC2_DEBUG is not set
++# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
++# CONFIG_USB_DWC2_FORCE_FULL_SPEED is not set
++# CONFIG_USB_DWC2_EXT_ID_PIN is not set
++CONFIG_USB_DWC2_EXT_VBUS_DETECT=y
++# CONFIG_USB_CHIPIDEA is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_APPLE_MFI_FASTCHARGE is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HUB_USB251XB is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++# CONFIG_USB_CHAOSKEY is not set
++
++#
++# USB Physical Layer drivers
++#
++CONFIG_USB_PHY=y
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_INGENIC_INNOPHY is not set
++CONFIG_INGENIC_USB_PHY=y
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ISP1301 is not set
++# CONFIG_JZ4770_PHY is not set
++# end of USB Physical Layer drivers
++
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++# CONFIG_U_SERIAL_CONSOLE is not set
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FUSB300 is not set
++# CONFIG_USB_FOTG210_UDC is not set
++# CONFIG_USB_GR_UDC is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_PXA27X is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_USB_MV_U3D is not set
++# CONFIG_USB_SNP_UDC_PLAT is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_BDC_UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_GADGET_XILINX is not set
++# CONFIG_USB_MAX3420_UDC is not set
++# CONFIG_USB_DUMMY_HCD is not set
++# end of USB Peripheral Controller
++
++CONFIG_USB_LIBCOMPOSITE=y
++CONFIG_USB_F_ACM=y
++CONFIG_USB_U_SERIAL=y
++CONFIG_USB_U_ETHER=y
++CONFIG_USB_U_AUDIO=y
++CONFIG_USB_F_SERIAL=y
++CONFIG_USB_F_OBEX=y
++CONFIG_USB_F_RNDIS=y
++CONFIG_USB_F_MASS_STORAGE=y
++CONFIG_USB_F_FS=y
++CONFIG_USB_F_UAC1=y
++CONFIG_USB_F_UVC=y
++CONFIG_USB_F_HID=y
++CONFIG_USB_F_PRINTER=y
++CONFIG_USB_CONFIGFS=y
++# CONFIG_CONFIGFS_UEVENT_REPORT is not set
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++# CONFIG_USB_CONFIGFS_NCM is not set
++# CONFIG_USB_CONFIGFS_ECM is not set
++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
++CONFIG_USB_CONFIGFS_RNDIS=y
++# CONFIG_USB_CONFIGFS_EEM is not set
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++# CONFIG_USB_CONFIGFS_F_LB_SS is not set
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_UAC1=y
++# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
++# CONFIG_USB_CONFIGFS_F_UAC2 is not set
++# CONFIG_USB_CONFIGFS_F_MIDI is not set
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_UVC=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++# CONFIG_USB_CONFIGFS_F_MTP is not set
++
++#
++# USB Gadget precomposed configurations
++#
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_AUDIO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++# CONFIG_USB_MASS_STORAGE is not set
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_MIDI_GADGET is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++# CONFIG_USB_G_MULTI is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++# CONFIG_USB_RAW_GADGET is not set
++# end of USB Gadget precomposed configurations
++
++# CONFIG_TYPEC is not set
++CONFIG_USB_ROLE_SWITCH=y
++CONFIG_MMC=y
++CONFIG_PWRSEQ_EMMC=y
++CONFIG_PWRSEQ_SIMPLE=y
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_MINORS=16
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_DEBUG is not set
++CONFIG_MMC_SDHCI=y
++# CONFIG_MMC_SDHCI_PLTFM is not set
++# CONFIG_MMC_SPI is not set
++# CONFIG_MMC_DW is not set
++# CONFIG_MMC_JZ4740 is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++# CONFIG_MMC_CQHCI is not set
++# CONFIG_MMC_HSQ is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_INFINIBAND is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_SYSTOHC=y
++CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++# CONFIG_RTC_NVMEM is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_ABB5ZES3 is not set
++# CONFIG_RTC_DRV_ABEOZ9 is not set
++# CONFIG_RTC_DRV_ABX80X is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_HYM8563 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_ISL12022 is not set
++# CONFIG_RTC_DRV_ISL12026 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8523 is not set
++# CONFIG_RTC_DRV_PCF85063 is not set
++# CONFIG_RTC_DRV_PCF85363 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_BQ32K is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8010 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++# CONFIG_RTC_DRV_RX8025 is not set
++# CONFIG_RTC_DRV_EM3027 is not set
++# CONFIG_RTC_DRV_RV3028 is not set
++# CONFIG_RTC_DRV_RV3032 is not set
++# CONFIG_RTC_DRV_RV8803 is not set
++# CONFIG_RTC_DRV_SD3078 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_M41T93 is not set
++# CONFIG_RTC_DRV_M41T94 is not set
++# CONFIG_RTC_DRV_DS1302 is not set
++# CONFIG_RTC_DRV_DS1305 is not set
++# CONFIG_RTC_DRV_DS1343 is not set
++# CONFIG_RTC_DRV_DS1347 is not set
++# CONFIG_RTC_DRV_DS1390 is not set
++# CONFIG_RTC_DRV_MAX6916 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RX4581 is not set
++# CONFIG_RTC_DRV_RX6110 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_PCF2123 is not set
++# CONFIG_RTC_DRV_MCP795 is not set
++CONFIG_RTC_I2C_AND_SPI=y
++
++#
++# SPI and I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS3232 is not set
++# CONFIG_RTC_DRV_PCF2127 is not set
++# CONFIG_RTC_DRV_RV3029C2 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1685_FAMILY is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_DS2404 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_MSM6242 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_RP5C01 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_ZYNQMP is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_CADENCE is not set
++# CONFIG_RTC_DRV_FTRTC010 is not set
++# CONFIG_RTC_DRV_JZ4740 is not set
++# CONFIG_RTC_DRV_R7301 is not set
++
++#
++# HID Sensor RTC drivers
++#
++CONFIG_DMADEVICES=y
++# CONFIG_DMADEVICES_DEBUG is not set
++
++#
++# DMA Devices
++#
++CONFIG_DMA_ENGINE=y
++CONFIG_DMA_VIRTUAL_CHANNELS=y
++CONFIG_DMA_OF=y
++# CONFIG_ALTERA_MSGDMA is not set
++# CONFIG_DMA_JZ4780 is not set
++# CONFIG_DW_AXI_DMAC is not set
++# CONFIG_FSL_EDMA is not set
++# CONFIG_IMG_MDC_DMA is not set
++# CONFIG_INTEL_IDMA64 is not set
++# CONFIG_XILINX_ZYNQMP_DPDMA is not set
++# CONFIG_QCOM_HIDMA_MGMT is not set
++# CONFIG_QCOM_HIDMA is not set
++# CONFIG_DW_DMAC is not set
++# CONFIG_SF_PDMA is not set
++
++#
++# DMA Clients
++#
++# CONFIG_ASYNC_TX_DMA is not set
++CONFIG_DMATEST=y
++CONFIG_DMA_ENGINE_RAID=y
++
++#
++# DMABUF options
++#
++# CONFIG_SYNC_FILE is not set
++# CONFIG_UDMABUF is not set
++# CONFIG_DMABUF_MOVE_NOTIFY is not set
++# CONFIG_DMABUF_SELFTESTS is not set
++# CONFIG_DMABUF_PROCESS_INFO is not set
++# CONFIG_DMABUF_HEAPS is not set
++# CONFIG_DMABUF_SYSFS_STATS is not set
++# end of DMABUF options
++
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++# CONFIG_VFIO is not set
++# CONFIG_VIRT_DRIVERS is not set
++# CONFIG_VIRTIO_MENU is not set
++# CONFIG_VDPA is not set
++# CONFIG_VHOST_MENU is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++# end of Microsoft Hyper-V guest support
++
++# CONFIG_GREYBUS is not set
++CONFIG_STAGING=y
++# CONFIG_PRISM2_USB is not set
++# CONFIG_COMEDI is not set
++# CONFIG_RTLLIB is not set
++# CONFIG_RTL8723BS is not set
++# CONFIG_R8712U is not set
++# CONFIG_R8188EU is not set
++# CONFIG_VT6656 is not set
++# CONFIG_STAGING_MEDIA is not set
++
++#
++# Android
++#
++# CONFIG_ASHMEM is not set
++# CONFIG_ION is not set
++# end of Android
++
++# CONFIG_STAGING_BOARD is not set
++# CONFIG_LTE_GDM724X is not set
++# CONFIG_GS_FPGABOOT is not set
++# CONFIG_UNISYSSPAR is not set
++# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
++# CONFIG_FB_TFT is not set
++# CONFIG_KS7010 is not set
++# CONFIG_PI433 is not set
++
++#
++# Gasket devices
++#
++# end of Gasket devices
++
++# CONFIG_XIL_AXIS_FIFO is not set
++# CONFIG_FIELDBUS_DEV is not set
++# CONFIG_WFX is not set
++CONFIG_HILOG=y
++CONFIG_HILOG_BUFFER_SIZE=4096
++CONFIG_HIEVENT=y
++CONFIG_BBOX_BUFFER_SIZE=2048
++# CONFIG_HISYSEVENT is not set
++# CONFIG_DFX_HUNGTASK is not set
++
++#
++# Blackbox Options
++#
++CONFIG_BLACKBOX=y
++CONFIG_BLACKBOX_LOG_ROOT_PATH=""
++CONFIG_BLACKBOX_LOG_PART_REPRESENTATIVE=""
++# CONFIG_BLACKBOX_STORAGE_BY_MEMORY is not set
++# CONFIG_BLACKBOX_USE_PSTORE_BLK_DEBUG is not set
++# CONFIG_BLACKBOX_STORAGE_BY_RAW_PARTITION is not set
++# end of Blackbox Options
++
++# CONFIG_MIPS_PLATFORM_DEVICES is not set
++# CONFIG_GOLDFISH is not set
++CONFIG_HAVE_CLK=y
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++# CONFIG_COMMON_CLK_MAX9485 is not set
++# CONFIG_COMMON_CLK_SI5341 is not set
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI514 is not set
++# CONFIG_COMMON_CLK_SI544 is not set
++# CONFIG_COMMON_CLK_SI570 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CDCE925 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_COMMON_CLK_PWM is not set
++# CONFIG_COMMON_CLK_VC5 is not set
++# CONFIG_COMMON_CLK_FIXED_MMIO is not set
++# CONFIG_COMMON_CLK_BOSTON is not set
++
++#
++# Ingenic SoCs drivers
++#
++# CONFIG_INGENIC_CGU_JZ4740 is not set
++# CONFIG_INGENIC_CGU_JZ4725B is not set
++# CONFIG_INGENIC_CGU_JZ4770 is not set
++# CONFIG_INGENIC_CGU_JZ4780 is not set
++# CONFIG_INGENIC_CGU_X1000 is not set
++# CONFIG_INGENIC_CGU_X1830 is not set
++# CONFIG_INGENIC_TCU_CLK is not set
++# end of Ingenic SoCs drivers
++
++# CONFIG_HWSPINLOCK is not set
++
++#
++# Clock Source drivers
++#
++CONFIG_TIMER_OF=y
++CONFIG_TIMER_PROBE=y
++CONFIG_INGENIC_TIMER=y
++# CONFIG_INGENIC_SYSOST is not set
++# CONFIG_INGENIC_OST is not set
++# CONFIG_MICROCHIP_PIT64B is not set
++# end of Clock Source drivers
++
++# CONFIG_MAILBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++
++#
++# Remoteproc drivers
++#
++# CONFIG_REMOTEPROC is not set
++# end of Remoteproc drivers
++
++#
++# Rpmsg drivers
++#
++# CONFIG_RPMSG_VIRTIO is not set
++# end of Rpmsg drivers
++
++# CONFIG_SOUNDWIRE is not set
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Amlogic SoC drivers
++#
++# end of Amlogic SoC drivers
++
++#
++# Aspeed SoC drivers
++#
++# end of Aspeed SoC drivers
++
++#
++# Broadcom SoC drivers
++#
++# end of Broadcom SoC drivers
++
++#
++# NXP/Freescale QorIQ SoC drivers
++#
++# end of NXP/Freescale QorIQ SoC drivers
++
++#
++# i.MX SoC drivers
++#
++# end of i.MX SoC drivers
++
++#
++# Qualcomm SoC drivers
++#
++# end of Qualcomm SoC drivers
++
++# CONFIG_SOC_TI is not set
++
++#
++# Xilinx SoC drivers
++#
++# CONFIG_XILINX_VCU is not set
++# end of Xilinx SoC drivers
++# end of SOC (System On Chip) specific Drivers
++
++# CONFIG_PM_DEVFREQ is not set
++CONFIG_EXTCON=y
++
++#
++# Extcon Device Drivers
++#
++# CONFIG_EXTCON_FSA9480 is not set
++# CONFIG_EXTCON_GPIO is not set
++# CONFIG_EXTCON_MAX3355 is not set
++# CONFIG_EXTCON_PTN5150 is not set
++# CONFIG_EXTCON_RT8973A is not set
++# CONFIG_EXTCON_SM5502 is not set
++# CONFIG_EXTCON_USB_GPIO is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++CONFIG_PWM=y
++CONFIG_PWM_SYSFS=y
++# CONFIG_PWM_DEBUG is not set
++# CONFIG_PWM_FSL_FTM is not set
++# CONFIG_PWM_IMG is not set
++# CONFIG_PWM_JZ4740 is not set
++# CONFIG_PWM_PCA9685 is not set
++
++#
++# IRQ chip support
++#
++CONFIG_IRQCHIP=y
++# CONFIG_AL_FIC is not set
++CONFIG_IRQ_MIPS_CPU=y
++# CONFIG_INGENIC_TCU_IRQ is not set
++# end of IRQ chip support
++
++# CONFIG_IPACK_BUS is not set
++# CONFIG_RESET_CONTROLLER is not set
++
++#
++# PHY Subsystem
++#
++# CONFIG_GENERIC_PHY is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++# CONFIG_PHY_CADENCE_TORRENT is not set
++# CONFIG_PHY_CADENCE_DPHY is not set
++# CONFIG_PHY_CADENCE_SALVO is not set
++# CONFIG_PHY_FSL_IMX8MQ_USB is not set
++# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_PHY_MAPPHONE_MDM6600 is not set
++# CONFIG_PHY_OCELOT_SERDES is not set
++# CONFIG_PHY_SAMSUNG_USB2 is not set
++# end of PHY Subsystem
++
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++# CONFIG_RAS is not set
++
++#
++# Android
++#
++CONFIG_ANDROID=y
++CONFIG_ANDROID_BINDER_IPC=y
++# CONFIG_ANDROID_BINDERFS is not set
++CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
++# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
++# CONFIG_BINDER_TRANSACTION_PROC_BRIEF is not set
++# end of Android
++
++# CONFIG_DAX is not set
++CONFIG_NVMEM=y
++CONFIG_NVMEM_SYSFS=y
++
++#
++# HW tracing support
++#
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++# end of HW tracing support
++
++# CONFIG_FPGA is not set
++# CONFIG_FSI is not set
++# CONFIG_SIOX is not set
++# CONFIG_SLIMBUS is not set
++# CONFIG_INTERCONNECT is not set
++# CONFIG_COUNTER is not set
++CONFIG_DRIVERS_HDF=y
++CONFIG_HDF_SUPPORT_LEVEL=1
++CONFIG_DRIVERS_HDF_PLATFORM=y
++# CONFIG_DRIVERS_HDF_PLATFORM_MIPI_DSI is not set
++# CONFIG_DRIVERS_HDF_PLATFORM_MIPI_CSI is not set
++CONFIG_DRIVERS_HDF_PLATFORM_GPIO=y
++CONFIG_DRIVERS_HDF_PLATFORM_I2C=y
++# CONFIG_DRIVERS_HDF_PLATFORM_WATCHDOG is not set
++# CONFIG_DRIVERS_HDF_PLATFORM_PWM is not set
++# CONFIG_DRIVERS_HDF_PLATFORM_UART is not set
++# CONFIG_DRIVERS_HDF_PLATFORM_EMMC is not set
++# CONFIG_DRIVERS_HDF_PLATFORM_MMC is not set
++# CONFIG_DRIVERS_HDF_PLATFORM_SPI is not set
++# CONFIG_DRIVERS_HDF_PLATFORM_RTC is not set
++# CONFIG_PWM_HI35XX is not set
++# CONFIG_DRIVERS_HDF_PLATFORM_REGULATOR is not set
++# CONFIG_DRIVERS_HDF_PLATFORM_ADC is not set
++# CONFIG_DRIVERS_HDF_PLATFORM_TRACE is not set
++# CONFIG_DRIVERS_HDF_PLATFORM_DUMPER is not set
++# CONFIG_IMX8MM_EMMC is not set
++# CONFIG_IMX8MM_SDIO is not set
++# CONFIG_DRIVERS_HDF_PLATFORM_IMX8MM_MIPI_DSI is not set
++# CONFIG_DRIVERS_HDF_TEST is not set
++# CONFIG_DRIVERS_HDF_DISP is not set
++CONFIG_DRIVERS_HDF_INPUT=y
++CONFIG_DRIVERS_HDF_TP_5P5_GT911=y
++# CONFIG_DRIVERS_HDF_TP_2P35_FT6236 is not set
++# CONFIG_DRIVERS_HDF_INPUT_INFRARED is not set
++# CONFIG_DRIVERS_HDF_TP_5P43_FT5406 is not set
++# CONFIG_ARCH_NXP_TOUCH is not set
++# CONFIG_DRIVERS_HDF_NETDEV_EXT is not set
++# CONFIG_DRIVERS_HDF_BT is not set
++# CONFIG_DRIVERS_HDF_SENSOR is not set
++# CONFIG_DRIVERS_HDF_STORAGE is not set
++# CONFIG_IMX8MM_SDIO_TEST is not set
++# CONFIG_DRIVERS_HDF_USB_PNP_NOTIFY is not set
++# CONFIG_DRIVERS_HDF_AUDIO is not set
++# CONFIG_DRIVERS_HDF_VIBRATOR is not set
++# CONFIG_DRIVERS_HDF_DSOFTBUS is not set
++# CONFIG_DRIVERS_HDF_LIGHT is not set
++# CONFIG_DRIVERS_HDF_NETWORK is not set
++# CONFIG_MOST is not set
++# CONFIG_ACCESS_TOKENID is not set
++
++#
++# Vendor Hooks
++#
++# end of Vendor Hooks
++# end of Device Drivers
++
++#
++# File systems
++#
++# CONFIG_VALIDATE_FS_PARSER is not set
++# CONFIG_EXT2_FS is not set
++# CONFIG_EXT3_FS is not set
++# CONFIG_EXT4_FS is not set
++# CONFIG_HMDFS_FS is not set
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++CONFIG_EXPORTFS=y
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++CONFIG_MANDATORY_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++# CONFIG_FS_VERITY is not set
++CONFIG_FSNOTIFY=y
++# CONFIG_DNOTIFY is not set
++CONFIG_INOTIFY_USER=y
++# CONFIG_FANOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_FUSE_FS is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++# end of Caches
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++# end of CD-ROM/DVD Filesystems
++
++#
++# DOS/FAT/EXFAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++# CONFIG_MSDOS_FS is not set
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++# CONFIG_EXFAT_FS is not set
++# CONFIG_NTFS_FS is not set
++# end of DOS/FAT/EXFAT/NT Filesystems
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_KCORE=y
++CONFIG_PROC_SYSCTL=y
++# CONFIG_PROC_PAGE_MONITOR is not set
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_TMPFS_XATTR is not set
++CONFIG_MEMFD_CREATE=y
++CONFIG_CONFIGFS_FS=y
++# end of Pseudo filesystems
++
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_ECRYPT_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++# CONFIG_JFFS2_FS is not set
++CONFIG_UBIFS_FS=y
++CONFIG_UBIFS_FS_ADVANCED_COMPR=y
++CONFIG_UBIFS_FS_LZO=y
++# CONFIG_UBIFS_FS_ZLIB is not set
++CONFIG_UBIFS_FS_ZSTD=y
++CONFIG_UBIFS_ATIME_SUPPORT=y
++CONFIG_UBIFS_FS_XATTR=y
++CONFIG_UBIFS_FS_SECURITY=y
++# CONFIG_UBIFS_FS_AUTHENTICATION is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++# CONFIG_EROFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++# CONFIG_NFS_FS is not set
++# CONFIG_NFSD is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++# CONFIG_UNICODE is not set
++CONFIG_IO_WQ=y
++# end of File systems
++
++#
++# Security options
++#
++CONFIG_KEYS=y
++# CONFIG_KEYS_REQUEST_CACHE is not set
++# CONFIG_PERSISTENT_KEYRINGS is not set
++# CONFIG_ENCRYPTED_KEYS is not set
++# CONFIG_KEY_DH_OPERATIONS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++# CONFIG_HARDENED_USERCOPY is not set
++# CONFIG_STATIC_USERMODEHELPER is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,bpf"
++
++#
++# Kernel hardening options
++#
++
++#
++# Memory initialization
++#
++CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
++CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
++CONFIG_INIT_STACK_NONE=y
++# CONFIG_INIT_STACK_ALL_PATTERN is not set
++# CONFIG_INIT_STACK_ALL_ZERO is not set
++# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
++# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
++# end of Memory initialization
++# end of Kernel hardening options
++# end of Security options
++
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_SKCIPHER=y
++CONFIG_CRYPTO_SKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=y
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_AKCIPHER=y
++CONFIG_CRYPTO_KPP2=y
++CONFIG_CRYPTO_ACOMP2=y
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
++# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set
++CONFIG_CRYPTO_GF128MUL=y
++CONFIG_CRYPTO_NULL=y
++CONFIG_CRYPTO_NULL2=y
++# CONFIG_CRYPTO_PCRYPT is not set
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Public-key cryptography
++#
++CONFIG_CRYPTO_RSA=y
++# CONFIG_CRYPTO_DH is not set
++# CONFIG_CRYPTO_ECDH is not set
++# CONFIG_CRYPTO_ECRDSA is not set
++# CONFIG_CRYPTO_SM2 is not set
++# CONFIG_CRYPTO_CURVE25519 is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=y
++CONFIG_CRYPTO_GCM=y
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++# CONFIG_CRYPTO_AEGIS128 is not set
++CONFIG_CRYPTO_SEQIV=y
++# CONFIG_CRYPTO_ECHAINIV is not set
++
++#
++# Block modes
++#
++# CONFIG_CRYPTO_CBC is not set
++# CONFIG_CRYPTO_CFB is not set
++CONFIG_CRYPTO_CTR=y
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=y
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_OFB is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_KEYWRAP is not set
++# CONFIG_CRYPTO_ADIANTUM is not set
++# CONFIG_CRYPTO_ESSIV is not set
++
++#
++# Hash modes
++#
++CONFIG_CRYPTO_CMAC=y
++CONFIG_CRYPTO_HMAC=y
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_CRC32 is not set
++# CONFIG_CRYPTO_XXHASH is not set
++# CONFIG_CRYPTO_BLAKE2B is not set
++# CONFIG_CRYPTO_BLAKE2S is not set
++CONFIG_CRYPTO_CRCT10DIF=y
++CONFIG_CRYPTO_GHASH=y
++# CONFIG_CRYPTO_POLY1305 is not set
++# CONFIG_CRYPTO_POLY1305_MIPS is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++CONFIG_CRYPTO_SHA256=y
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_SM3 is not set
++# CONFIG_CRYPTO_STREEBOG is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_AES_TI is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_SM4 is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++CONFIG_CRYPTO_ZSTD=y
++
++#
++# Random Number Generation
++#
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_DRBG_MENU=y
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++# CONFIG_CRYPTO_DRBG_CTR is not set
++CONFIG_CRYPTO_DRBG=y
++CONFIG_CRYPTO_JITTERENTROPY=y
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++# CONFIG_CRYPTO_USER_API_RNG is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_HASH_INFO=y
++
++#
++# Crypto library routines
++#
++CONFIG_CRYPTO_LIB_AES=y
++CONFIG_CRYPTO_LIB_ARC4=y
++# CONFIG_CRYPTO_LIB_BLAKE2S is not set
++# CONFIG_CRYPTO_LIB_CHACHA is not set
++# CONFIG_CRYPTO_LIB_CURVE25519 is not set
++CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
++# CONFIG_CRYPTO_LIB_POLY1305 is not set
++# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set
++CONFIG_CRYPTO_LIB_SHA256=y
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
++# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
++# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set
++# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
++# CONFIG_CRYPTO_DEV_CCREE is not set
++# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set
++CONFIG_ASYMMETRIC_KEY_TYPE=y
++CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
++CONFIG_X509_CERTIFICATE_PARSER=y
++# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
++CONFIG_PKCS7_MESSAGE_PARSER=y
++# CONFIG_PKCS7_TEST_KEY is not set
++# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
++
++#
++# Certificates for signature checking
++#
++CONFIG_SYSTEM_TRUSTED_KEYRING=y
++CONFIG_SYSTEM_TRUSTED_KEYS=""
++# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
++# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
++# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
++# end of Certificates for signature checking
++
++#
++# Library routines
++#
++# CONFIG_PACKING is not set
++CONFIG_BITREVERSE=y
++CONFIG_GENERIC_NET_UTILS=y
++# CONFIG_CORDIC is not set
++# CONFIG_PRIME_NUMBERS is not set
++CONFIG_RATIONAL=y
++CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IOMAP=y
++# CONFIG_CRC_CCITT is not set
++CONFIG_CRC16=y
++CONFIG_CRC_T10DIF=y
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC64 is not set
++# CONFIG_CRC4 is not set
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++# CONFIG_CRC8 is not set
++CONFIG_XXHASH=y
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_ZSTD_COMPRESS=y
++CONFIG_ZSTD_DECOMPRESS=y
++# CONFIG_XZ_DEC is not set
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_INTERVAL_TREE=y
++CONFIG_ASSOCIATIVE_ARRAY=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y
++CONFIG_DMA_DECLARE_COHERENT=y
++CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
++CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
++CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
++CONFIG_DMA_NONCOHERENT_MMAP=y
++# CONFIG_DMA_API_DEBUG is not set
++CONFIG_SGL_ALLOC=y
++CONFIG_CPU_RMAP=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++CONFIG_GENERIC_ATOMIC64=y
++CONFIG_CLZ_TAB=y
++# CONFIG_IRQ_POLL is not set
++CONFIG_MPILIB=y
++CONFIG_LIBFDT=y
++CONFIG_OID_REGISTRY=y
++CONFIG_HAVE_GENERIC_VDSO=y
++CONFIG_GENERIC_GETTIMEOFDAY=y
++CONFIG_SG_POOL=y
++CONFIG_SBITMAP=y
++# CONFIG_STRING_SELFTEST is not set
++# end of Library routines
++
++CONFIG_GENERIC_LIB_ASHLDI3=y
++CONFIG_GENERIC_LIB_ASHRDI3=y
++CONFIG_GENERIC_LIB_LSHRDI3=y
++CONFIG_GENERIC_LIB_CMPDI2=y
++CONFIG_GENERIC_LIB_UCMPDI2=y
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++CONFIG_PRINTK_TIME=y
++# CONFIG_PRINTK_CALLER is not set
++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=4
++CONFIG_CONSOLE_LOGLEVEL_QUIET=4
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
++# CONFIG_BOOT_PRINTK_DELAY is not set
++CONFIG_DYNAMIC_DEBUG=y
++CONFIG_DYNAMIC_DEBUG_CORE=y
++CONFIG_SYMBOLIC_ERRNAME=y
++# end of printk and dmesg options
++
++#
++# Compile-time checks and compiler options
++#
++# CONFIG_DEBUG_INFO is not set
++# CONFIG_ENABLE_MUST_CHECK is not set
++CONFIG_FRAME_WARN=1024
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_HEADERS_INSTALL is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_SECTION_MISMATCH_WARN_ONLY=y
++# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++# end of Compile-time checks and compiler options
++
++#
++# Generic Kernel Debugging Instruments
++#
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
++CONFIG_MAGIC_SYSRQ_SERIAL=y
++CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
++CONFIG_DEBUG_FS=y
++CONFIG_DEBUG_FS_ALLOW_ALL=y
++# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
++# CONFIG_DEBUG_FS_ALLOW_NONE is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
++# CONFIG_UBSAN is not set
++# end of Generic Kernel Debugging Instruments
++
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_MISC is not set
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_OWNER is not set
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_DEBUG_SLAB is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_SCHED_STACK_END_CHECK is not set
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_PER_CPU_MAPS is not set
++CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
++CONFIG_DEBUG_STACKOVERFLOW=y
++CONFIG_CC_HAS_KASAN_GENERIC=y
++CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
++# end of Memory Debugging
++
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Oops, Lockups and Hangs
++#
++# CONFIG_PANIC_ON_OOPS is not set
++CONFIG_PANIC_ON_OOPS_VALUE=0
++CONFIG_PANIC_TIMEOUT=10
++CONFIG_LOCKUP_DETECTOR=y
++CONFIG_SOFTLOCKUP_DETECTOR=y
++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
++CONFIG_WQ_WATCHDOG=y
++# CONFIG_TEST_LOCKUP is not set
++# end of Debug Oops, Lockups and Hangs
++
++#
++# Scheduler Debugging
++#
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# end of Scheduler Debugging
++
++# CONFIG_DEBUG_TIMEKEEPING is not set
++# CONFIG_DEBUG_PREEMPT is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++CONFIG_LOCK_DEBUGGING_SUPPORT=y
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++CONFIG_DEBUG_SPINLOCK=y
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_RWSEMS is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++# CONFIG_WW_MUTEX_SELFTEST is not set
++# CONFIG_SCF_TORTURE_TEST is not set
++# end of Lock Debugging (spinlocks, mutexes, etc...)
++
++CONFIG_STACKTRACE=y
++# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
++# CONFIG_DEBUG_KOBJECT is not set
++
++#
++# Debug kernel data structures
++#
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PLIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_DEBUG_NOTIFIERS=y
++# CONFIG_BUG_ON_DATA_CORRUPTION is not set
++# end of Debug kernel data structures
++
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_RCU_SCALE_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_RCU_REF_SCALE_TEST is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=21
++# CONFIG_RCU_TRACE is not set
++# CONFIG_RCU_EQS_DEBUG is not set
++# end of RCU Debugging
++
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++# CONFIG_SAMPLES is not set
++
++#
++# mips Debugging
++#
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_EARLY_PRINTK=y
++# CONFIG_CMDLINE_BOOL is not set
++CONFIG_SPINLOCK_TEST=y
++# CONFIG_SCACHE_DEBUGFS is not set
++# end of mips Debugging
++
++#
++# Kernel Testing and Coverage
++#
++# CONFIG_KUNIT is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++CONFIG_ARCH_HAS_KCOV=y
++CONFIG_CC_HAS_SANCOV_TRACE_PC=y
++# CONFIG_KCOV is not set
++CONFIG_RUNTIME_TESTING_MENU=y
++# CONFIG_LKDTM is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_TEST_MIN_HEAP is not set
++# CONFIG_TEST_SORT is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_REED_SOLOMON_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++# CONFIG_PERCPU_TEST is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_TEST_HEXDUMP is not set
++# CONFIG_TEST_STRING_HELPERS is not set
++# CONFIG_TEST_STRSCPY is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_TEST_PRINTF is not set
++# CONFIG_TEST_BITMAP is not set
++# CONFIG_TEST_UUID is not set
++# CONFIG_TEST_XARRAY is not set
++# CONFIG_TEST_OVERFLOW is not set
++# CONFIG_TEST_RHASHTABLE is not set
++# CONFIG_TEST_HASH is not set
++# CONFIG_TEST_IDA is not set
++# CONFIG_TEST_LKM is not set
++# CONFIG_TEST_BITOPS is not set
++# CONFIG_TEST_VMALLOC is not set
++# CONFIG_TEST_USER_COPY is not set
++# CONFIG_TEST_BPF is not set
++# CONFIG_TEST_BLACKHOLE_DEV is not set
++# CONFIG_FIND_BIT_BENCHMARK is not set
++# CONFIG_TEST_FIRMWARE is not set
++# CONFIG_TEST_SYSCTL is not set
++# CONFIG_TEST_UDELAY is not set
++# CONFIG_TEST_STATIC_KEYS is not set
++# CONFIG_TEST_KMOD is not set
++# CONFIG_TEST_MEMCAT_P is not set
++# CONFIG_TEST_STACKINIT is not set
++# CONFIG_TEST_MEMINIT is not set
++# CONFIG_TEST_FREE_PAGES is not set
++# CONFIG_MEMTEST is not set
++# end of Kernel Testing and Coverage
++# end of Kernel hacking
++
++#
++# Ingenic device-drivers Configurations
++#
++CONFIG_OUTSIDE_DRIVERS_PATH="module_drivers"
++
++#
++# ---- Minimal required Drivers ----
++#
++
++#
++# [Interrupt] Drivers
++#
++CONFIG_IRQ_INGENIC_CPU=y
++CONFIG_INGENIC_INTC_CHIP=y
++# end of [Interrupt] Drivers
++
++#
++# [OST] clocksoure Drivers
++#
++CONFIG_CLKSRC_INGENIC_CORE_OST=y
++# end of [OST] clocksoure Drivers
++
++#
++# [CPM] clk Drivers
++#
++CONFIG_COMMON_CLK_INGENIC=y
++CONFIG_INGENIC_CLK_DEBUG_FS=y
++CONFIG_CLK_X2000=y
++# end of [CPM] clk Drivers
++
++#
++# [GPIO] Pinctroller Drivers
++#
++CONFIG_PINCTRL_INGENIC_V2=y
++# CONFIG_MULTI_VGPIO_INGENIC is not set
++# end of [GPIO] Pinctroller Drivers
++
++#
++# [UART] Drivers
++#
++CONFIG_SERIAL_INGENIC_UART=y
++CONFIG_SERIAL_INGENIC_CONSOLE=y
++CONFIG_SERIAL_INGENIC_LARGE_BAUDRATE=y
++CONFIG_SERIAL_INGENIC_MAGIC_SYSRQ=y
++# end of [UART] Drivers
++
++#
++# [MSC] (eMMC/SD/SDIO) and Device Drivers
++#
++CONFIG_MMC_SDHCI_INGENIC=y
++CONFIG_MMC_INDEX_MATCH_CONTROLLER=y
++# end of [MSC] (eMMC/SD/SDIO) and Device Drivers
++
++#
++# [DMA] Drivers
++#
++CONFIG_INGENIC_PDMAC=y
++# CONFIG_INGENIC_AIC_USES_PDMA is not set
++# end of [DMA] Drivers
++
++#
++# [SFC] (SPI Nand/Nor Flash) Drivers
++#
++CONFIG_INGENIC_SFC=y
++# CONFIG_MTD_INGENIC_SFC_V1 is not set
++CONFIG_MTD_INGENIC_SFC_V2=y
++CONFIG_MTD_INGENIC_SFC_NORFLASH=y
++# CONFIG_MTD_INGENIC_SFC_NANDFLASH is not set
++# CONFIG_INGENIC_BUILTIN_PARAMS is not set
++# end of [SFC] (SPI Nand/Nor Flash) Drivers
++
++#
++# [SPI] Master/Slave Drivers
++#
++CONFIG_INGENIC_SPI=y
++CONFIG_INGENIC_SPI0=y
++# CONFIG_INGENIC_SPI_PIO_CE is not set
++# end of [SPI] Master/Slave Drivers
++
++#
++# [I2C] Master Drivers
++#
++CONFIG_I2C_INGENIC=y
++# CONFIG_I2C_NON_RESTART_MODE is not set
++CONFIG_I2C_FIFO_LEN=64
++# CONFIG_I2C_DEBUG_INFO is not set
++# end of [I2C] Master Drivers
++
++#
++# ---- minimal OS requirements. ----
++#
++
++#
++# [LCD] Panel/Touchscreen Drivers
++#
++CONFIG_FB_INGENIC=y
++# CONFIG_FB_VSYNC_SKIP_DISABLE is not set
++CONFIG_FB_VSYNC_SKIP=9
++CONFIG_FB_INGENIC_NR_FRAMES=3
++CONFIG_FB_INGENIC_NR_LAYERS=2
++# CONFIG_FB_INGENIC_DEBUG is not set
++# CONFIG_SLCDC_CONTINUA is not set
++# CONFIG_SLCDC_USE_TE is not set
++CONFIG_FB_INGENIC_STAGE=y
++CONFIG_FB_INGENIC_DISPLAYS_STAGE=y
++# CONFIG_STAGE_Y88249 is not set
++# CONFIG_STAGE_KD050HDFIA019 is not set
++# CONFIG_STAGE_MA0060 is not set
++CONFIG_STAGE_KD050HDFIA020=y
++# CONFIG_STAGE_FW050 is not set
++# CONFIG_STAGE_FW040 is not set
++# CONFIG_STAGE_FW035 is not set
++# CONFIG_STAGE_TL040WVS03CT is not set
++# CONFIG_STAGE_TL040HDS01CT is not set
++# CONFIG_STAGE_JD9161Z is not set
++# CONFIG_STAGE_JD9365D is not set
++# CONFIG_STAGE_ATK7016 is not set
++# CONFIG_STAGE_JD9365 is not set
++# CONFIG_STAGE_GC9203 is not set
++# CONFIG_STAGE_ST7701S is not set
++# CONFIG_STAGE_ST7701S_RGB666 is not set
++# CONFIG_STAGE_ST7701S_DX is not set
++# CONFIG_STAGE_YTS500XLAI is not set
++# CONFIG_STAGE_YLYM286A is not set
++# CONFIG_STAGE_KD035HVFBD037 is not set
++# CONFIG_PANEL_STAGE_MV238FHM_N30 is not set
++# CONFIG_STAGE_EK79007AD is not set
++# CONFIG_STAGE_JD9366 is not set
++# CONFIG_STAGE_BM8766 is not set
++# CONFIG_STAGE_KD050WVFPA029 is not set
++# CONFIG_STAGE_GWMTF16499B is not set
++# CONFIG_STAGE_ST7282 is not set
++# CONFIG_STAGE_G104X1L04 is not set
++# CONFIG_STAGE_KD035HVFMD057 is not set
++CONFIG_TRUE_COLOR_LOGO=y
++CONFIG_TRUE_COLOR_LOGO_FILE="module_drivers/drivers/video/logo-ingenic/logo.png"
++CONFIG_TRUE_COLOR_LOGO_BACKGROUND=0xffffffff
++
++#
++# Touchscreen Drivers
++#
++# CONFIG_TOUCHSCREEN_FTS is not set
++# CONFIG_TOUCHSCREEN_HYN is not set
++# CONFIG_TOUCHSCREEN_GT9XX is not set
++# CONFIG_TOUCHSCREEN_FT6236 is not set
++# CONFIG_TOUCHSCREEN_MXT336U is not set
++# end of Touchscreen Drivers
++# end of [LCD] Panel/Touchscreen Drivers
++
++#
++# [GMAC] (ethernet) Drivers
++#
++CONFIG_INGENIC_MAC=y
++CONFIG_INGENIC_MAC_DMA_INTERFACES=y
++CONFIG_INGENIC_MAC_AXI_BUS=y
++# CONFIG_INGENIC_MAC_AHB_BUS is not set
++# CONFIG_INGENIC_GMAC_USE_HWSTAMP is not set
++# CONFIG_INGENIC_GMAC_MUTUAL_TRANS is not set
++CONFIG_INGENIC_GMAC_RX_DESC_COUNT=512
++# end of [GMAC] (ethernet) Drivers
++
++#
++# [WIFI]  Drivers
++#
++# CONFIG_BCMDHD_1_363_125_17 is not set
++CONFIG_BCMDHD=y
++CONFIG_BCMDHD_FW_PATH="/firmware/fw_bcm43456c5_ag.bin"
++CONFIG_BCMDHD_NVRAM_PATH="/firmware/nvram_ap6256.txt"
++CONFIG_BCMDHD_SDIO=y
++# CONFIG_BCMDHD_USB is not set
++CONFIG_BCMDHD_OOB=y
++# CONFIG_BCMDHD_SDIO_IRQ is not set
++# CONFIG_RTL8723DS is not set
++# end of [WIFI]  Drivers
++
++#
++# [CAN] (ethernet) Drivers
++#
++
++#
++# ---- (V4L2) Media Device Drivers ----
++#
++CONFIG_VIDEOBUF2_DMA_CONTIG_INGENIC=y
++CONFIG_CAMERA_RESERVE_KB_SIZE=0
++
++#
++# [ISP] Drivers
++#
++# CONFIG_VIDEO_INGENIC_ISP is not set
++# end of [ISP] Drivers
++
++#
++# [CIM] Drivers
++#
++# CONFIG_VIDEO_INGENIC_CIM is not set
++# end of [CIM] Drivers
++
++#
++# [Rotator] Drivers
++#
++CONFIG_VIDEO_INGENIC_ROTATE=y
++# end of [Rotator] Drivers
++
++#
++# [VPU] Drivers
++#
++CONFIG_VIDEO_INGENIC_VCODEC=y
++CONFIG_INGENIC_HELIX=y
++CONFIG_INGENIC_FELIX=y
++# end of [VPU] Drivers
++
++#
++# [Sensors] Camera Sensors
++#
++
++#
++# ingenic-isp camera sensor drivers
++#
++
++#
++# ingenic-isp-v2 camera sensor drivers
++#
++
++#
++# ingenic-cim camera sensor drivers
++#
++# end of [Sensors] Camera Sensors
++
++#
++# ---- MISC Device Drivers ----
++#
++# CONFIG_INGENIC_RSA is not set
++# CONFIG_LINUX_PMEM is not set
++# CONFIG_INGENIC_EFUSE_X2000 is not set
++CONFIG_BCM_4345C5_RFKILL=y
++
++#
++# [RANDOM] drivers
++#
++# CONFIG_HW_RANDOM_INGENIC is not set
++# end of [RANDOM] drivers
++
++#
++# [MFD] Multi Function Device Drivers
++#
++CONFIG_MFD_INGENIC_SADC_V13=y
++CONFIG_MFD_INGENIC_SADC_AUX=y
++CONFIG_MFD_INGENIC_TCU=y
++# CONFIG_MFD_RICOH619 is not set
++
++#
++# [Power] power and regulator Drivers
++#
++# CONFIG_CRYPTO_DEV_INGENIC_SHA is not set
++# CONFIG_CRYPTO_DEV_INGENIC_AES is not set
++
++#
++# [WDT] watchdog Drivers
++#
++CONFIG_INGENIC_WDT=y
++# CONFIG_SGM820_WATCHDOG is not set
++# end of [WDT] watchdog Drivers
++
++#
++# [PWM] drivers
++#
++CONFIG_PWM_INGENIC_V2=y
++# end of [PWM] drivers
++
++#
++# [RTC] drivers
++#
++CONFIG_RTC_DRV_INGENIC=y
++# end of [RTC] drivers
++
++CONFIG_SND_ASOC_INGENIC=y
++# CONFIG_SND_ASOC_INGENIC_DEBUG is not set
++# CONFIG_SND_ASOC_INGENIC_VERBOSE is not set
++# CONFIG_DMIC_AND_AMIC_SYNC is not set
++CONFIG_SND_ASOC_INGENIC_AS_V2=y
++CONFIG_SND_ASOC_INGENIC_DMA_PREALLOC_PAGES=128
++CONFIG_SND_ASOC_INGENIC_AS_FE=y
++CONFIG_SND_ASOC_INGENIC_AS_BAIC=y
++CONFIG_SND_ASOC_INGENIC_AS_SPDIF=y
++CONFIG_SND_ASOC_INGENIC_AS_DMIC=y
++CONFIG_SND_ASOC_INGENIC_ICDC_INNO=y
++CONFIG_SND_ASOC_INGENIC_AS_VIR_FE=y
++
++#
++# Ingenic Board Type Select
++#
++# CONFIG_SND_ASOC_INGENIC_BOARD_EXTERNAL_SOURCE is not set
++# CONFIG_SND_ASOC_INGENIC_ZEBRA is not set
++# CONFIG_SND_ASOC_INGENIC_ZEBRA_DMIC_ICDC is not set
++CONFIG_SND_ASOC_INGENIC_HALLEY5_V20=y
++# end of Ingenic Board Type Select
++
++CONFIG_SND_ASOC_INGENIC_SPDIF_DUMMY_TIMES=800
++CONFIG_SND_ASOC_INGENIC_PLAYBACK_DUMMY_TIMES=20
++# CONFIG_SND_SOC_WM8594 is not set
++
++#
++# ingenic external codec Type select
++#
++# end of ingenic external codec Type select
++# end of Ingenic device-drivers Configurations
+diff --git a/arch/mips/generic/board-ingenic.c b/arch/mips/generic/board-ingenic.c
+index 0cec0bea1..51937997f 100644
+--- a/arch/mips/generic/board-ingenic.c
++++ b/arch/mips/generic/board-ingenic.c
+@@ -27,6 +27,8 @@ static __init char *ingenic_get_system_type(unsigned long machtype)
+ 		return "X2000";
+ 	case MACH_INGENIC_X1830:
+ 		return "X1830";
++	case MACH_INGENIC_X1600:
++		return "X1600";
+ 	case MACH_INGENIC_X1000E:
+ 		return "X1000E";
+ 	case MACH_INGENIC_X1000:
+@@ -68,6 +70,7 @@ static const struct of_device_id ingenic_of_match[] __initconst = {
+ 	{ .compatible = "ingenic,jz4780", .data = (void *)MACH_INGENIC_JZ4780 },
+ 	{ .compatible = "ingenic,x1000", .data = (void *)MACH_INGENIC_X1000 },
+ 	{ .compatible = "ingenic,x1000e", .data = (void *)MACH_INGENIC_X1000E },
++	{ .compatible = "ingenic,x1600", .data = (void *)MACH_INGENIC_X1600 },
+ 	{ .compatible = "ingenic,x1830", .data = (void *)MACH_INGENIC_X1830 },
+ 	{ .compatible = "ingenic,x2000", .data = (void *)MACH_INGENIC_X2000 },
+ 	{ .compatible = "ingenic,x2000e", .data = (void *)MACH_INGENIC_X2000E },
+diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
+index aa03b1237..a92b6b256 100644
+--- a/arch/mips/include/asm/bootinfo.h
++++ b/arch/mips/include/asm/bootinfo.h
+@@ -80,6 +80,7 @@ enum ingenic_machine_type {
+ 	MACH_INGENIC_JZ4780,
+ 	MACH_INGENIC_X1000,
+ 	MACH_INGENIC_X1000E,
++	MACH_INGENIC_X1600,
+ 	MACH_INGENIC_X1830,
+ 	MACH_INGENIC_X2000,
+ 	MACH_INGENIC_X2000E,
+diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
+index 8294eaa6f..947a5046a 100644
+--- a/arch/mips/include/asm/cpu-features.h
++++ b/arch/mips/include/asm/cpu-features.h
+@@ -424,6 +424,18 @@
+ #define cpu_has_loongson_ext2		__ase(MIPS_ASE_LOONGSON_EXT2)
+ #endif
+ 
++#ifndef cpu_has_mxu		//32bit simd for xburst Series soc.
++#define cpu_has_mxu	0
++#endif
++
++#ifndef cpu_has_mxuv2		//128bit simd for xburst series soc.
++#define cpu_has_mxuv2	0
++#endif
++
++#ifndef cpu_has_mxuv3		//512bit simd for xburst2 series soc.
++#define cpu_has_mxuv3	0
++#endif
++
+ #ifndef cpu_has_mipsmt
+ #define cpu_has_mipsmt		__isa_range_and_ase(2, 6, MIPS_ASE_MIPSMT)
+ #endif
+diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
+index 3288cef4b..1b33da2c2 100644
+--- a/arch/mips/include/asm/cpu-type.h
++++ b/arch/mips/include/asm/cpu-type.h
+@@ -57,6 +57,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
+ #ifdef CONFIG_SYS_HAS_CPU_MIPS32_R5
+ 	case CPU_M5150:
+ 	case CPU_P5600:
++	case CPU_XBURST2:
+ #endif
+ 
+ #if defined(CONFIG_SYS_HAS_CPU_MIPS32_R2) || \
+diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
+index c9222cc22..38c414132 100644
+--- a/arch/mips/include/asm/cpu.h
++++ b/arch/mips/include/asm/cpu.h
+@@ -47,7 +47,7 @@
+ #define PRID_COMP_CAVIUM	0x0d0000
+ #define PRID_COMP_LOONGSON	0x140000
+ #define PRID_COMP_INGENIC_13	0x130000	/* X2000 */
+-#define PRID_COMP_INGENIC_D0	0xd00000	/* JZ4740, JZ4750, X1830 */
++#define PRID_COMP_INGENIC_D0	0xd00000	/* JZ4740, JZ4750, X1830, X1600 */
+ #define PRID_COMP_INGENIC_D1	0xd10000	/* JZ4770, JZ4775, X1000 */
+ #define PRID_COMP_INGENIC_E1	0xe10000	/* JZ4780 */
+ 
+@@ -186,9 +186,20 @@
+  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
+  */
+ 
++#define PRID_IMP_XBURST		0x0000	/* XBurst®1 with ISA */
+ #define PRID_IMP_XBURST_REV1	0x0200	/* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA	*/
+ #define PRID_IMP_XBURST_REV2	0x0100	/* XBurst®1 with MXU2.0 SIMD ISA		*/
+-#define PRID_IMP_XBURST2		0x2000	/* XBurst®2 with MXU2.1 SIMD ISA		*/
++#define PRID_IMP_XBURST2	0x2000	/* XBurst®2 with MXU2.1 SIMD ISA		*/
++#define PRID_IMP_XBURST2_R2	0x2100	/* XBurst®2 with MXU3.0 SIMD ISA		*/
++
++#define PRID_COMPANY_ID_MASK   0x00FF0000
++#define PRID_CPU_ARCH_MASK     0x00001F00
++#define PRID_CPU_FEATURE_MASK       0xFFFF0000
++#define PRID_CPU_CHIPS_MASK         0x000FF000
++#define PRID_IMP_PROCESSOR_ID_MSK 0x0000E000
++#define PRID_CPU_ISA_MASK           0x00000FFF
++#define PRID_CPU_X2000              0x00130000
++
+ 
+ /*
+  * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
+@@ -319,7 +330,7 @@ enum cpu_type_enum {
+ 	 */
+ 	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
+ 	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
+-	CPU_BMIPS4380, CPU_BMIPS5000, CPU_XBURST, CPU_LOONGSON32, CPU_M14KC,
++	CPU_BMIPS4380, CPU_BMIPS5000, CPU_XBURST, CPU_XBURST2, CPU_LOONGSON32, CPU_M14KC,
+ 	CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,
+ 	CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250,
+ 
+diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
+index 7a7467d3f..dfabe15f7 100644
+--- a/arch/mips/include/asm/mipsregs.h
++++ b/arch/mips/include/asm/mipsregs.h
+@@ -484,6 +484,9 @@
+ /* Implementation specific trap codes used by Loongson cores */
+ #define LOONGSON_EXCCODE_GSEXC	16	/* Loongson-specific exception */
+ 
++/* Ingenic MXUV2 exceptions. */
++#define INGENIC_EXCCODE_MXUV2	16
++
+ /*
+  * Bits in the coprocessor 0 config register.
+  */
+@@ -2073,7 +2076,7 @@ _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
+ ({ int __res;								\
+ 	__asm__ __volatile__(						\
+ 		".set\tpush\n\t"					\
+-		".set\tmips32r5\n\t"					\
++		".set\tmips32r2\n\t"					\
+ 		_ASM_SET_VIRT						\
+ 		"mfgc0\t%0, " #source ", %1\n\t"			\
+ 		".set\tpop"						\
+@@ -2086,7 +2089,7 @@ _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
+ ({ unsigned long long __res;						\
+ 	__asm__ __volatile__(						\
+ 		".set\tpush\n\t"					\
+-		".set\tmips64r5\n\t"					\
++		".set\tmips64r2\n\t"					\
+ 		_ASM_SET_VIRT						\
+ 		"dmfgc0\t%0, " #source ", %1\n\t"			\
+ 		".set\tpop"						\
+@@ -2099,7 +2102,7 @@ _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
+ do {									\
+ 	__asm__ __volatile__(						\
+ 		".set\tpush\n\t"					\
+-		".set\tmips32r5\n\t"					\
++		".set\tmips32r2\n\t"					\
+ 		_ASM_SET_VIRT						\
+ 		"mtgc0\t%z0, " #register ", %1\n\t"			\
+ 		".set\tpop"						\
+@@ -2111,7 +2114,7 @@ do {									\
+ do {									\
+ 	__asm__ __volatile__(						\
+ 		".set\tpush\n\t"					\
+-		".set\tmips64r5\n\t"					\
++		".set\tmips64r2\n\t"					\
+ 		_ASM_SET_VIRT						\
+ 		"dmtgc0\t%z0, " #register ", %1\n\t"			\
+ 		".set\tpop"						\
+diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h
+index e0a3dd523..fa9197f46 100644
+--- a/arch/mips/include/asm/msa.h
++++ b/arch/mips/include/asm/msa.h
+@@ -98,6 +98,8 @@ static inline void enable_msa(void)
+ {
+ 	if (cpu_has_msa) {
+ 		set_c0_config5(MIPS_CONF5_MSAEN);
++		set_c0_status(ST0_CU2);
++		KSTK_STATUS(current) |= ST0_CU2;
+ 		enable_fpu_hazard();
+ 	}
+ }
+@@ -106,6 +108,8 @@ static inline void disable_msa(void)
+ {
+ 	if (cpu_has_msa) {
+ 		clear_c0_config5(MIPS_CONF5_MSAEN);
++		clear_c0_status(ST0_CU2);
++		KSTK_STATUS(current) &= ~ST0_CU2;
+ 		disable_fpu_hazard();
+ 	}
+ }
+diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
+index 2362842ee..2e168130a 100644
+--- a/arch/mips/include/asm/pgtable-bits.h
++++ b/arch/mips/include/asm/pgtable-bits.h
+@@ -249,6 +249,21 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
+ 
+ #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
+ 
++#elif defined(CONFIG_MACH_INGENIC)
++/* Ingenic uses the WA bit to achieve write-combine memory writes */
++#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
++#elif defined(CONFIG_MACH_XBURST) || defined(CONFIG_MACH_XBURST2)
++
++#define _CACHE_CACHABLE_WT_WA      (0<<_CACHE_SHIFT)  /* R4600 only      */
++#define _CACHE_UNCACHED_ACCELERATED    (1<<_CACHE_SHIFT)  /* R4600 only          */
++#define _CACHE_UNCACHED                        (2<<_CACHE_SHIFT)  /* R4[0246]00          */
++#define _CACHE_CACHABLE_WB_WA       (3<<_CACHE_SHIFT)  /* R4[0246]00     */
++#define _CACHE_CACHABLE_WT_WA_S            (4<<_CACHE_SHIFT)  /* R4[04]00MC only */
++#define _CACHE_CACHABLE_WB_WA_S            (5<<_CACHE_SHIFT)  /* R4[04]00MC only */
++#define _CACHE_CACHABLE_WA             _CACHE_UNCACHED_ACCELERATED
++#define _CACHE_CACHABLE_NONCOHERENT _CACHE_CACHABLE_WB_WA
++
++
+ #endif
+ 
+ #ifndef _CACHE_CACHABLE_NO_WA
+diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
+index 7834e7c0c..ac3887a40 100644
+--- a/arch/mips/include/asm/processor.h
++++ b/arch/mips/include/asm/processor.h
+@@ -87,6 +87,23 @@ extern unsigned long mips_stack_top(void);
+ 
+ #define NUM_FPU_REGS	32
+ 
++
++#if cpu_has_mxuv2
++#define NUM_MXU_VPR_REGS  16      //vpr0~15
++#define NUM_MXU_VSR_REGS  0
++#endif
++
++
++#if cpu_has_mxuv3
++#define NUM_MXU_VPR_REGS  32      //vpr0~31
++#define NUM_MXU_VSR_REGS  4       //vsr0~3
++#endif
++
++#if !cpu_has_mxuv2 && !cpu_has_mxuv3
++#define NUM_MXU_VPR_REGS 0
++#define NUM_MXU_VSR_REGS 0
++#endif
++
+ #ifdef CONFIG_CPU_HAS_MSA
+ # define FPU_REG_WIDTH	128
+ #else
+@@ -98,6 +115,22 @@ union fpureg {
+ 	__u64	val64[FPU_REG_WIDTH / 64];
+ };
+ 
++typedef union mxuvec {
++#if cpu_has_mxuv2
++    uint8_t    val128[16];     //simd128
++#endif
++#if cpu_has_mxuv3
++    uint8_t    val512[64];     //simd512
++#endif
++} mxuvec_t;
++
++struct xburst_mxu_struct {
++        mxuvec_t   vpr[NUM_MXU_VPR_REGS];
++        mxuvec_t   vsr[NUM_MXU_VSR_REGS];
++	uint32_t	csr;
++};
++
++
+ #ifdef CONFIG_CPU_LITTLE_ENDIAN
+ # define FPR_IDX(width, idx)	(idx)
+ #else
+@@ -156,8 +189,20 @@ struct mips3264_watch_reg_state {
+ union mips_watch_reg_state {
+ 	struct mips3264_watch_reg_state mips3264;
+ };
++#if defined(CONFIG_XBURST_MXUV2)
++typedef union {
++	u64 val64[2];
++} vpr_t;
++
++struct xburst_cop2_state {
++	u32 mxu_csr;
++	vpr_t vr[32];
++};
++
++#define COP2_INIT						\
++	.cp2			= {0,},
+ 
+-#if defined(CONFIG_CPU_CAVIUM_OCTEON)
++#elif defined(CONFIG_CPU_CAVIUM_OCTEON)
+ 
+ struct octeon_cop2_state {
+ 	/* DMFC2 rt, 0x0201 */
+@@ -272,6 +317,11 @@ struct thread_struct {
+ 	/* Saved state of the DSP ASE, if available. */
+ 	struct mips_dsp_state dsp;
+ 
++
++	/* Saved registers of the MXU, if available. */
++	struct xburst_mxu_struct mxu;
++
++
+ 	/* Saved watch register state, if available. */
+ 	union mips_watch_reg_state watch;
+ 
+@@ -280,6 +330,10 @@ struct thread_struct {
+ 	unsigned long cp0_baduaddr;	/* Last kernel fault accessing USEG */
+ 	unsigned long error_code;
+ 	unsigned long trap_nr;
++#ifdef CONFIG_XBURST_MXUV2
++	struct xburst_cop2_state cp2;
++#endif
++
+ #ifdef CONFIG_CPU_CAVIUM_OCTEON
+ 	struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
+ 	struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
+diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
+index aa430a6c6..deb613d70 100644
+--- a/arch/mips/include/asm/stackframe.h
++++ b/arch/mips/include/asm/stackframe.h
+@@ -424,7 +424,7 @@
+ 
+ 		.macro	RESTORE_SP_AND_RET docfi=0
+ 		RESTORE_SP \docfi
+-#if defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
++#ifdef CONFIG_CPU_MIPSR6
+ 		eretnc
+ #else
+ 		.set	push
+diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
+index a4374b4cb..94f2d0bdf 100644
+--- a/arch/mips/include/asm/switch_to.h
++++ b/arch/mips/include/asm/switch_to.h
+@@ -17,6 +17,8 @@
+ #include <asm/dsp.h>
+ #include <asm/cop2.h>
+ #include <asm/fpu.h>
++#include <mxu.h>
++#include <mxuv3.h>
+ 
+ struct task_struct;
+ 
+@@ -116,6 +118,23 @@ do {									\
+ 		__save_dsp(prev);					\
+ 		__restore_dsp(next);					\
+ 	}								\
++	if(cpu_has_mxu) {						\
++	        if (KSTK_STATUS(prev) & ST0_CU2) {                      \
++                       __save_mxu(prev);                               \
++               }                                                       \
++               if (KSTK_STATUS(next) & ST0_CU2) {                      \
++                       __restore_mxu(next);                            \
++               }                                                       \
++       }                                                               \
++       if (cpu_has_mxuv3) {                                            \
++		   if ((KSTK_STATUS(prev) & ST0_CU2))  { \
++			   __save_mxuv3(prev);                             \
++		   }                                                       \
++		   if ((KSTK_STATUS(next) & ST0_CU2))  { \
++			   set_c0_status(ST0_CU2);                         \
++			   __restore_mxuv3(next);                          \
++		   }                                                       \
++       }   								\
+ 	if (cop2_present) {						\
+ 		u32 status = read_c0_status();				\
+ 									\
+diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
+index d12020191..2b572f10d 100644
+--- a/arch/mips/kernel/cpu-probe.c
++++ b/arch/mips/kernel/cpu-probe.c
+@@ -1721,6 +1721,8 @@ static inline void decode_cpucfg(struct cpuinfo_mips *c)
+ 
+ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
+ {
++	decode_configs(c);
++
+ 	/* All Loongson processors covered here define ExcCode 16 as GSExc. */
+ 	c->options |= MIPS_CPU_GSEXCEX;
+ 
+@@ -1737,6 +1739,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
+ 			set_isa(c, MIPS_CPU_ISA_M64R2);
+ 			break;
+ 		}
++		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
+ 		c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT |
+ 				MIPS_ASE_LOONGSON_EXT2);
+ 		break;
+@@ -1766,6 +1769,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
+ 		 * register, we correct it here.
+ 		 */
+ 		c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
++		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
+ 		c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
+ 			MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
+ 		c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */
+@@ -1776,13 +1780,12 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
+ 		set_elf_platform(cpu, "loongson3a");
+ 		set_isa(c, MIPS_CPU_ISA_M64R2);
+ 		decode_cpucfg(c);
++		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
+ 		break;
+ 	default:
+ 		panic("Unknown Loongson Processor ID!");
+ 		break;
+ 	}
+-
+-	decode_configs(c);
+ }
+ #else
+ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { }
+@@ -1807,6 +1810,14 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
+ 
+ 	switch (c->processor_id & PRID_IMP_MASK) {
+ 
++	/* XBurst®1 with ISA */
++	case PRID_IMP_XBURST:
++		c->cputype = CPU_XBURST;
++		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
++		__cpu_name[cpu] = "Ingenic XBurst";
++		break;
++
++
+ 	/* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
+ 	case PRID_IMP_XBURST_REV1:
+ 
+@@ -1863,7 +1874,9 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
+ 
+ 	/* XBurst®2 with MXU2.1 SIMD ISA */
+ 	case PRID_IMP_XBURST2:
+-		c->cputype = CPU_XBURST;
++	case PRID_IMP_XBURST2_R2:
++		c->cputype = CPU_XBURST2;
++		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
+ 		__cpu_name[cpu] = "Ingenic XBurst II";
+ 		break;
+ 
+diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
+index bcce32a3d..70913c1e2 100644
+--- a/arch/mips/kernel/genex.S
++++ b/arch/mips/kernel/genex.S
+@@ -568,6 +568,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
+ #ifdef CONFIG_MIPS_FP_SUPPORT
+ 	BUILD_HANDLER fpe fpe fpe silent		/* #15 */
+ #endif
++	BUILD_HANDLER mfpe mfpe none silent		/* #16 */
+ 	BUILD_HANDLER ftlb ftlb none silent		/* #16 */
+ 	BUILD_HANDLER gsexc gsexc gsexc silent		/* #16 */
+ 	BUILD_HANDLER msa msa sti silent		/* #21 */
+diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
+index 18e69ebf5..c440bfb1a 100644
+--- a/arch/mips/kernel/idle.c
++++ b/arch/mips/kernel/idle.c
+@@ -67,6 +67,19 @@ void __cpuidle r4k_wait_irqoff(void)
+ 	raw_local_irq_enable();
+ }
+ 
++void ingenic_wait_irqoff(void)
++{
++	WARN_ON_ONCE(!raw_irqs_disabled());
++	if (!need_resched())
++		__asm__(
++		"       .set    push            \n"
++		"       .set    arch=r4000      \n"
++		"       sync                    \n"
++		"       wait                    \n"
++		"       .set    pop             \n");
++	raw_local_irq_enable();
++}
++
+ /*
+  * The RM7000 variant has to handle erratum 38.	 The workaround is to not
+  * have any pending stores when the WAIT instruction is executed.
+@@ -172,12 +185,15 @@ void __init check_wait(void)
+ 	case CPU_CAVIUM_OCTEON_PLUS:
+ 	case CPU_CAVIUM_OCTEON2:
+ 	case CPU_CAVIUM_OCTEON3:
+-	case CPU_XBURST:
+ 	case CPU_LOONGSON32:
+ 	case CPU_XLR:
+ 	case CPU_XLP:
+ 		cpu_wait = r4k_wait;
+ 		break;
++	case CPU_XBURST:
++	case CPU_XBURST2:
++		cpu_wait = ingenic_wait_irqoff;
++		break;
+ 	case CPU_LOONGSON64:
+ 		if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >=
+ 				(PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0) ||
+diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
+index 9d11f68a9..63de4bfde 100644
+--- a/arch/mips/kernel/setup.c
++++ b/arch/mips/kernel/setup.c
+@@ -686,7 +686,7 @@ static void __init arch_mem_init(char **cmdline_p)
+ 	memblock_reserve(__pa_symbol(&__nosave_begin),
+ 		__pa_symbol(&__nosave_end) - __pa_symbol(&__nosave_begin));
+ 
+-	fdt_init_reserved_mem();
++	//fdt_init_reserved_mem();
+ 
+ 	memblock_dump_all();
+ 
+diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
+index 14db66dbc..48629da39 100644
+--- a/arch/mips/kernel/smp.c
++++ b/arch/mips/kernel/smp.c
+@@ -348,6 +348,7 @@ asmlinkage void start_secondary(void)
+ 	 */
+ 
+ 	calibrate_delay();
++	preempt_disable();
+ 	cpu = smp_processor_id();
+ 	cpu_data[cpu].udelay_val = loops_per_jiffy;
+ 
+diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
+index b1fe4518b..13a388b18 100644
+--- a/arch/mips/kernel/traps.c
++++ b/arch/mips/kernel/traps.c
+@@ -89,6 +89,7 @@ extern asmlinkage void handle_ov(void);
+ extern asmlinkage void handle_tr(void);
+ extern asmlinkage void handle_msa_fpe(void);
+ extern asmlinkage void handle_fpe(void);
++extern asmlinkage void handle_mfpe(void);
+ extern asmlinkage void handle_ftlb(void);
+ extern asmlinkage void handle_gsexc(void);
+ extern asmlinkage void handle_msa(void);
+@@ -957,6 +958,14 @@ static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
+ 
+ #endif /* !CONFIG_MIPS_FP_SUPPORT */
+ 
++//MACH_XBURST
++asmlinkage void do_mfpe(struct pt_regs * regs)     
++{
++        die_if_kernel("Kernel bug detected", regs);
++        force_sig(SIGILL);
++}
++
++
+ void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
+ 	const char *str)
+ {
+@@ -1160,6 +1169,20 @@ asmlinkage void do_ri(struct pt_regs *regs)
+ 	unsigned int opcode = 0;
+ 	int status = -1;
+ 
++        /* If Config1.CU2 is not set, the exc_code = 10 of cause reg */
++        if (cpu_has_mxuv3 && (1 == smp_processor_id())) {
++                printk("%s(%d):reschedule to cpu0 to smp_processor_id()=%d, read_c0_status()=0x%x, task_cpu(current)=%d, KSTK_STATUS(current)=0x%lx, current->tgid=%d, current->pid=%d\n", __func__, __LINE__, smp_processor_id(), read_c0_status(), task_cpu(current), KSTK_STATUS(current), current->tgid, current->pid);
++                //resched_cpu(0);
++        	smp_send_reschedule(0);
++                if (0 == smp_processor_id()) {
++                        printk("%s(%d):open cu2 field to cpu0 to smp_processor_id()=%d, read_c0_status()=0x%x, task_cpu(current)=%d, KSTK_STATUS(current)=0x%lx, current->tgid=%d, current->pid=%d\n", __func__, __LINE__, smp_processor_id(), read_c0_status(), task_cpu(current), KSTK_STATUS(current), current->tgid, current->pid);
++                        set_c0_status(ST0_CU2);
++                        KSTK_STATUS(current) |= ST0_CU2;
++                }
++                printk("%s(%d):no cu2 coprocessor to smp_processor_id()=%d, read_c0_status()=0x%x, task_cpu(current)=%d, KSTK_STATUS(current)=0x%lx, current->tgid=%d, current->pid=%d\n", __func__, __LINE__, smp_processor_id(), read_c0_status(), task_cpu(current), KSTK_STATUS(current), current->tgid, current->pid);
++                return;
++        }
++
+ 	/*
+ 	 * Avoid any kernel code. Just emulate the R2 instruction
+ 	 * as quickly as possible.
+@@ -1500,6 +1523,32 @@ asmlinkage void do_cpu(struct pt_regs *regs)
+ #endif /* CONFIG_MIPS_FP_SUPPORT */
+ 
+ 	case 2:
++	        /* Processing of MXA instructions needs setting MSA enable. */
++
++		if(cpu_has_msa) {
++			int err = 0;
++			err = enable_restore_fp_context(1);
++			if (err)
++				force_sig(SIGILL);
++
++			break;
++		}
++                /* To Xburst2 T40, If Status.CU2 is not set and Config1.CU2 is set, the exc_code is 10 and CE field is 2 to Cause Reg
++                 * So here only need to open the Status.CU2 field */
++                if (cpu_has_mxuv3 && (0 == smp_processor_id())) {
++                        set_c0_status(ST0_CU2);
++                        KSTK_STATUS(current) |= ST0_CU2;
++			printk("%s(%d):open cu2 field to cpu0 to smp_processor_id()=%d, read_c0_status()=0x%x, task_cpu(current)=%d, KSTK_STATUS(current)=0x%lx, current->tgid=%d, current->pid=%d\n", __func__, __LINE__, smp_processor_id(), read_c0_status(), task_cpu(current), KSTK_STATUS(current), current->tgid, current->pid);
++
++			break;
++
++                } else if (cpu_has_mxuv3 && (1 == smp_processor_id())) {
++                        printk("%s(%d):no cu2 coprocessor to smp_processor_id()=%d, read_c0_status()=0x%x, task_cpu(current)=%d, KSTK_STATUS(current)=0x%lx, current->tgid=%d, current->pid=%d\n", __func__, __LINE__, smp_processor_id(), read_c0_status(), task_cpu(current), KSTK_STATUS(current), current->tgid, current->pid);
++                        force_sig(SIGILL);
++			break;
++                }
++
++		/*others case, call chain.*/
+ 		raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
+ 		break;
+ 	}
+@@ -2213,6 +2262,10 @@ static void configure_status(void)
+ 	if (cpu_has_dsp)
+ 		status_set |= ST0_MX;
+ 
++        if (cpu_has_mxuv3 && (KSTK_STATUS(current) & ST0_CU2)) {
++               status_set |= ST0_CU2;
++       }
++
+ 	change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
+ 			 status_set);
+ 	back_to_back_c0_hazard();
+@@ -2507,6 +2560,9 @@ void __init trap_init(void)
+ 	if (cpu_has_gsexcex)
+ 		set_except_vector(LOONGSON_EXCCODE_GSEXC, handle_gsexc);
+ 
++	if (cpu_has_mxuv2)
++		set_except_vector(INGENIC_EXCCODE_MXUV2, handle_mfpe);
++
+ 	if (cpu_has_rixiex) {
+ 		set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
+ 		set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
+diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
+index 96adc3d23..f6237185b 100644
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -96,9 +96,12 @@ static inline void r4k_on_each_cpu(unsigned int type,
+ 				   void (*func)(void *info), void *info)
+ {
+ 	preempt_disable();
++
++#ifndef CONFIG_MACH_XBURST2 
+ 	if (r4k_op_needs_ipi(type))
+ 		smp_call_function_many(&cpu_foreign_map[smp_processor_id()],
+ 				       func, info, 1);
++#endif
+ 	func(info);
+ 	preempt_enable();
+ }
+@@ -592,7 +595,7 @@ static inline void local_r4k_flush_cache_range(void * args)
+ 	 * If executable, we must ensure any dirty lines are written back far
+ 	 * enough to be visible to icache.
+ 	 */
+-	if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
++	if (1 /*TODO bypzqi*/ || cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
+ 		r4k_blast_dcache();
+ 	/* If executable, blast stale lines from icache */
+ 	if (exec)
+@@ -885,7 +888,11 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
+ 	 * we have to use the HIT-type alternative as IPI cannot be used
+ 	 * here due to interrupts possibly being disabled.
+ 	 */
++#ifndef CONFIG_MACH_XBURST2
+ 	if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
++#else
++	if(size >= dcache_size) {
++#endif
+ 		r4k_blast_dcache();
+ 	} else {
+ 		R4600_HIT_CACHEOP_WAR_IMPL;
+@@ -955,10 +962,29 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
+ 		return;
+ 	}
+ 
++#ifndef CONFIG_MACH_XBURST2
+ 	if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
++#else
++	if(size >= dcache_size) {
++#endif
++
+ 		r4k_blast_dcache();
+ 	} else {
++#if defined(CONFIG_MACH_XBURST) || defined(CONFIG_MACH_XBURST2)
++		unsigned long lsize = cpu_dcache_line_size();
++		unsigned long cmask = (lsize - 1);
++		unsigned long lmask = ~(cmask);
++#endif
+ 		R4600_HIT_CACHEOP_WAR_IMPL;
++#if defined(CONFIG_MACH_XBURST) || defined(CONFIG_MACH_XBURST2)
++		if (addr & cmask) {
++			cache_op(Hit_Writeback_Inv_D, addr & lmask);
++		}
++		if ((addr + size) & cmask) {
++			cache_op(Hit_Writeback_Inv_D, (addr + size - 1) & lmask);
++		}
++#endif
++
+ 		blast_inv_dcache_range(addr, addr + size);
+ 	}
+ 	preempt_enable();
+@@ -1645,6 +1671,7 @@ static void loongson3_sc_init(void)
+ extern int r5k_sc_init(void);
+ extern int rm7k_sc_init(void);
+ extern int mips_sc_init(void);
++extern int ingenic_sc_init(void);
+ 
+ static void setup_scache(void)
+ {
+@@ -1698,6 +1725,10 @@ static void setup_scache(void)
+ 	case CPU_LOONGSON64:
+ 		loongson3_sc_init();
+ 		return;
++	case CPU_XBURST:
++	case CPU_XBURST2:
++		ingenic_sc_init();
++		return;
+ 
+ 	case CPU_CAVIUM_OCTEON3:
+ 	case CPU_XLP:
+diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
+index 38d3d9143..918468645 100644
+--- a/arch/mips/mm/dma-noncoherent.c
++++ b/arch/mips/mm/dma-noncoherent.c
+@@ -33,6 +33,8 @@ static inline bool cpu_needs_post_dma_flush(void)
+ 	case CPU_R12000:
+ 	case CPU_BMIPS5000:
+ 	case CPU_LOONGSON2EF:
++	case CPU_XBURST:
++	case CPU_XBURST2:
+ 		return true;
+ 	default:
+ 		/*
+diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
+index 06ec304ad..831e98b8b 100644
+--- a/arch/mips/mm/sc-mips.c
++++ b/arch/mips/mm/sc-mips.c
+@@ -216,7 +216,7 @@ static inline int mips_sc_probe(void)
+ 		return 0;
+ 
+ 	tmp = (config2 >> 0) & 0x0f;
+-	if (tmp <= 7)
++	if ((tmp == 7) || (tmp == 15))
+ 		c->scache.ways = tmp + 1;
+ 	else
+ 		return 0;
+diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
+index 1b939abbe..14a0fd82b 100644
+--- a/arch/mips/mm/tlb-r4k.c
++++ b/arch/mips/mm/tlb-r4k.c
+@@ -55,7 +55,7 @@ void local_flush_tlb_all(void)
+ {
+ 	unsigned long flags;
+ 	unsigned long old_ctx;
+-	int entry, ftlbhighset;
++	int entry;
+ 
+ 	local_irq_save(flags);
+ 	/* Save old context and create impossible VPN2 value */
+@@ -71,6 +71,8 @@ void local_flush_tlb_all(void)
+ 	 * If there are any wired entries, fall back to iterating
+ 	 */
+ 	if (cpu_has_tlbinv && !entry) {
++#ifndef CONFIG_MACH_XBURST2
++		int ftlbhighset;
+ 		if (current_cpu_data.tlbsizevtlb) {
+ 			write_c0_index(0);
+ 			mtc0_tlbw_hazard();
+@@ -85,6 +87,9 @@ void local_flush_tlb_all(void)
+ 			mtc0_tlbw_hazard();
+ 			tlbinvf();  /* invalidate one FTLB set */
+ 		}
++#else
++		tlbinvf();  /* invalide FTLB/VTLB set */
++#endif
+ 	} else {
+ 		while (entry < current_cpu_data.tlbsize) {
+ 			/* Make sure all entries differ. */
+diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
+index a7521b8f7..f702c645c 100644
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
+@@ -613,6 +613,7 @@ void build_tlb_write_entry(u32 **p, struct uasm_label **l,
+ 		break;
+ 
+ 	case CPU_XBURST:
++	case CPU_XBURST2:
+ 		tlbw(p);
+ 		uasm_i_nop(p);
+ 		break;
+diff --git a/arch/mips/xburst/Kconfig b/arch/mips/xburst/Kconfig
+new file mode 100644
+index 000000000..f3e839e5d
+--- /dev/null
++++ b/arch/mips/xburst/Kconfig
+@@ -0,0 +1,69 @@
++menuconfig SOC_TYPE
++	tristate "SOC type"
++	depends on MACH_XBURST
++	default y
++
++if SOC_TYPE
++choice
++	prompt "SOC types"
++	depends on MACH_XBURST
++	default SOC_X1600
++
++config SOC_X1000
++	bool "x1000 socs"
++	select INGENIC_INTC
++	select CLK_X1000
++	select CLKSRC_OF
++	select PINCTRL
++	select TIMER_OF
++	select CLKDEV_LOOKUP
++	select PINCTRL_INGENIC
++	select CLKSRC_INGENIC_SYS_OST
++	select MMU_NOTIFIER
++
++config SOC_X1600
++	bool "x1600 socs"
++	select INGENIC_INTC
++	select CLK_X1600
++	select CLKSRC_OF
++	select PINCTRL
++	select TIMER_OF
++	select CLKDEV_LOOKUP
++	select PINCTRL_INGENIC
++	select CLKSRC_INGENIC_SYS_OST
++	select MMU_NOTIFIER
++endchoice
++
++config INGENIC_BUILTIN_DTB
++	select BUILTIN_DTB
++	depends on MACH_XBURST
++	bool "Ingenic Device Tree build into Kernel."
++	default y
++
++source "arch/mips/xburst/soc-x1000/Kconfig.DT"
++source "arch/mips/xburst/soc-x1600/Kconfig.DT"
++
++config EXTAL_CLOCK
++	depends on MACH_XBURST
++	int "extal clock in MHz"
++	default 24
++
++config INGENIC_GPT_CHECK
++	depends on MACH_XBURST
++	bool "The physical space is larger than the virtual space"
++	default y
++
++config SUSPEND_TEST
++	bool "auto suspend test"
++	default n
++
++config SUSPEND_ALARM_TIME
++	int "suspend alarm time(second)"
++	depends on SUSPEND_TEST
++	default 2
++
++config XBURST_MXUV2
++	bool
++	default n
++
++endif
+diff --git a/arch/mips/xburst/Makefile b/arch/mips/xburst/Makefile
+new file mode 100644
+index 000000000..f2979647c
+--- /dev/null
++++ b/arch/mips/xburst/Makefile
+@@ -0,0 +1,4 @@
++obj-y			+= common/
++obj-y			+= debug/
++obj-$(CONFIG_SOC_X1000) += soc-x1000/
++obj-$(CONFIG_SOC_X1600) += soc-x1600/
+diff --git a/arch/mips/xburst/Platform b/arch/mips/xburst/Platform
+new file mode 100644
+index 000000000..9930a99e8
+--- /dev/null
++++ b/arch/mips/xburst/Platform
+@@ -0,0 +1,7 @@
++platform-$(CONFIG_MACH_XBURST)	+= xburst/
++load-$(CONFIG_MACH_XBURST)	+= 0xffffffff80010000
++
++cflags-$(CONFIG_MACH_XBURST)	+= -I$(srctree)/arch/mips/xburst/common/include
++cflags-$(CONFIG_SOC_X1000)	+= -I$(srctree)/arch/mips/xburst/soc-x1000/include
++cflags-$(CONFIG_SOC_X1600)	+= -I$(srctree)/arch/mips/xburst/soc-x1600/include
++
+diff --git a/arch/mips/xburst/common/Makefile b/arch/mips/xburst/common/Makefile
+new file mode 100644
+index 000000000..ac731caeb
+--- /dev/null
++++ b/arch/mips/xburst/common/Makefile
+@@ -0,0 +1,5 @@
++obj-y	+= prom.o mxu-xburst.o jz_notifier.o
++obj-$(CONFIG_XBURST_CPU_SCACHE)	+= sc-xburst.o
++#obj-y += initrd-check.o
++obj-y += proc.o
++obj-$(CONFIG_XBURST_MXUV2)	+= mxu-v2-ex.obj
+diff --git a/arch/mips/xburst/common/include/ingenic_proc.h b/arch/mips/xburst/common/include/ingenic_proc.h
+new file mode 100644
+index 000000000..a1883087e
+--- /dev/null
++++ b/arch/mips/xburst/common/include/ingenic_proc.h
+@@ -0,0 +1,18 @@
++#ifndef _INGENIC_PROC_H_
++#define _INGENIC_PROC_H_
++
++struct jz_single_file_ops {
++	ssize_t (*read) (struct seq_file *, void *);
++	ssize_t (*write) (struct file *, const char __user *, size_t, loff_t *);
++	void *data;
++};
++
++struct proc_dir_entry * jz_proc_mkdir(char *s);
++struct proc_dir_entry *jz_proc_create_data(
++	const char *name, umode_t mode, struct proc_dir_entry *parent,
++	struct jz_single_file_ops *proc_fops, void *data);
++struct proc_dir_entry *jz_proc_create(
++	const char *name, umode_t mode, struct proc_dir_entry *parent,
++	struct jz_single_file_ops *proc_fops);
++struct proc_dir_entry * get_jz_proc_root(void);
++#endif /* _INGENIC_PROC_H_ */
+diff --git a/arch/mips/xburst/common/include/jz_notifier.h b/arch/mips/xburst/common/include/jz_notifier.h
+new file mode 100644
+index 000000000..ec582e9d3
+--- /dev/null
++++ b/arch/mips/xburst/common/include/jz_notifier.h
+@@ -0,0 +1,45 @@
++#ifndef _JZ_NOTIFIER_H_
++#define _JZ_NOTIFIER_H_
++
++#include <linux/notifier.h>
++
++/*
++ * Hibernation and suspend events
++ */
++enum jz_notif_cmd {
++	JZ_CMD_START = 0,
++	JZ_CLK_PRECHANGE,
++	JZ_CLK_CHANGING,
++	JZ_CLK_CHANGED,
++	JZ_CLKGATE_CHANGE,
++	JZ_POST_HIBERNATION, /* Hibernation finished */
++	JZ_PM_SUSPEND_STANDBY, /* Hibernation finished */
++	MMU_CONTEXT_EXIT_MMAP,
++	JZ_CMD_END
++};
++enum {
++	NOTEFY_PROI_START=1,
++	NOTEFY_PROI_HIGH,
++	NOTEFY_PROI_NORMAL,
++	NOTEFY_PROI_LOW,
++	NOTEFY_PROI_END
++};
++
++struct clk_notify_data
++{
++	unsigned long current_rate;
++	unsigned long target_rate;
++};
++
++struct jz_notifier {
++	struct notifier_block nb;
++	int (*jz_notify)(struct jz_notifier *notify,void *d);
++	int level;
++	enum jz_notif_cmd msg;
++};
++
++int jz_notifier_register(struct jz_notifier *notify, unsigned int priority);
++int jz_notifier_unregister(struct jz_notifier *notify, unsigned int priority);
++int jz_notifier_call(unsigned int priority, unsigned long val, void *v);
++
++#endif /* _JZ_NOTIFIER_H_ */
+diff --git a/arch/mips/xburst/common/include/mxu.h b/arch/mips/xburst/common/include/mxu.h
+new file mode 100755
+index 000000000..a82d4d8e0
+--- /dev/null
++++ b/arch/mips/xburst/common/include/mxu.h
+@@ -0,0 +1,66 @@
++/*
++ * Copyright (C) 2005 Mips Technologies
++ * Author: Chris Dearman, chris@mips.com derived from fpu.h
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#ifndef _ASM_MXU_H
++#define _ASM_MXU_H
++
++#include <asm/cpu.h>
++#include <asm/cpu-features.h>
++#include <asm/hazards.h>
++#include <asm/mipsregs.h>
++
++#include <mxu_media.h>
++
++static inline void __init_mxu(void)
++{
++	unsigned int register val asm("t0");
++	val = 3;
++	asm volatile(".word	0x7008042f \n\t"::"r"(val));
++}
++
++void __save_mxu(void *);
++void __restore_mxu(void * tsk_void);
++
++static inline void init_mxu(void)
++{
++	if(cpu_has_mxu)
++		__init_mxu();
++}
++
++
++#define save_mxu(tsk)							\
++	do {										\
++		if (cpu_has_mxu)						\
++			__save_mxu(tsk);					\
++	} while (0)
++
++#define restore_mxu(tsk)						\
++	do {										\
++		if (cpu_has_mxu)						\
++			__restore_mxu(tsk);					\
++	} while (0)
++
++#define __get_mxu_regs(tsk)						\
++	({											\
++		if (tsk == current)						\
++			__save_mxu(current);				\
++												\
++		tsk->thread.mxu.regs;					\
++	})
++
++#define __let_mxu_regs(tsk,regs)				\
++	do{											\
++		int i;									\
++		for(i = 0; i < NUM_MXU_REGS;i++)		\
++			tsk->thread.mxu.regs[i] = regs[i];	\
++		if (tsk == current)						\
++			__save_mxu(current);				\
++	}while(0)
++
++#endif /* _ASM_MXU_H */
+diff --git a/arch/mips/xburst/common/include/mxu_media.h b/arch/mips/xburst/common/include/mxu_media.h
+new file mode 100755
+index 000000000..655b47a84
+--- /dev/null
++++ b/arch/mips/xburst/common/include/mxu_media.h
+@@ -0,0 +1,1832 @@
++#ifndef _MXU_H_
++#define _MXU_H_
++
++#define xr00
++#define xr11
++#define xr22
++#define xr33
++#define xr44
++#define xr55
++#define xr66
++#define xr77
++#define xr88
++#define xr99
++#define xr1010
++#define xr1111
++#define xr1212
++#define xr1313
++#define xr1414
++#define xr1515
++#define xr1616
++
++#define ptn00
++#define ptn11
++#define ptn22
++#define ptn33
++#define ptn44
++#define ptn55
++#define ptn66
++#define ptn77
++
++/***********************************LD/SD***********************************/
++#define S32LDD(xra,rb,s12)								\
++	do{													\
++		__asm____volatile("S32LDDxr%0,%z1,%2"			\
++						  :								\
++						  :"K"(xra),"d"(rb),"I"(s12));	\
++	}while(0)
++
++#define S32STD(xra,rb,s12)										\
++	do{															\
++		__asm____volatile("S32STDxr%0,%z1,%2"					\
++						  :										\
++						  :"K"(xra),"d"(rb),"I"(s12):"memory");	\
++	}while(0)
++
++#define S32LDDV(xra,rb,rc,strd2)									\
++	do{																\
++		__asm____volatile("S32LDDVxr%0,%z1,%z2,%3"					\
++						  :											\
++						  :"K"(xra),"d"(rb),"d"(rc),"K"(strd2));	\
++	}while(0)
++
++#define S32STDV(xra,rb,rc,strd2)										\
++	do{																	\
++		__asm____volatile("S32STDVxr%0,%z1,%z2,%3"						\
++						  :												\
++						  :"K"(xra),"d"(rb),"d"(rc),"K"(strd2):"memory"); \
++	}while(0)
++
++#define S32LDI(xra,rb,s12)						\
++	do{											\
++		__asm____volatile("S32LDIxr%1,%z0,%2"	\
++						  :"+d"(rb)				\
++						  :"K"(xra),"I"(s12));	\
++	}while(0)
++
++#define S32SDI(xra,rb,s12)								\
++	do{													\
++		__asm____volatile("S32SDIxr%1,%z0,%2"			\
++						  :"+d"(rb)						\
++						  :"K"(xra),"I"(s12):"memory");	\
++	}while(0)
++
++#define S32LDIV(xra,rb,rc,strd2)							\
++	do{														\
++		__asm____volatile("S32LDIVxr%1,%z0,%z2,%3"			\
++						  :"+d"(rb)							\
++						  :"K"(xra),"d"(rc),"K"(strd2));	\
++	}while(0)
++
++#define S32SDIV(xra,rb,rc,strd2)									\
++	do{																\
++		__asm____volatile("S32SDIVxr%1,%z0,%z2,%3"					\
++						  :"+d"(rb)									\
++						  :"K"(xra),"d"(rc),"K"(strd2):"memory");	\
++	}while(0)
++//MXUenhancement
++#define S32LDDR(xra,rb,s12)								\
++	do{													\
++		__asm____volatile("S32LDDRxr%0,%z1,%2"			\
++						  :								\
++						  :"K"(xra),"d"(rb),"I"(s12));	\
++	}while(0)
++
++#define S32STDR(xra,rb,s12)										\
++	do{															\
++		__asm____volatile("S32STDRxr%0,%z1,%2"					\
++						  :										\
++						  :"K"(xra),"d"(rb),"I"(s12):"memory");	\
++	}while(0)
++
++#define S32LDDVR(xra,rb,rc,strd2)									\
++	do{																\
++		__asm____volatile("S32LDDVRxr%0,%z1,%z2,%3"					\
++						  :											\
++						  :"K"(xra),"d"(rb),"d"(rc),"K"(strd2));	\
++	}while(0)
++
++#define S32STDVR(xra,rb,rc,strd2)										\
++	do{																	\
++		__asm____volatile("S32STDVRxr%0,%z1,%z2,%3"						\
++						  :												\
++						  :"K"(xra),"d"(rb),"d"(rc),"K"(strd2):"memory"); \
++	}while(0)
++
++#define S32LDIR(xra,rb,s12)						\
++	do{											\
++		__asm____volatile("S32LDIRxr%1,%z0,%2"	\
++						  :"+d"(rb)				\
++						  :"K"(xra),"I"(s12));	\
++	}while(0)
++
++#define S32SDIR(xra,rb,s12)								\
++	do{													\
++		__asm____volatile("S32SDIRxr%1,%z0,%2"			\
++						  :"+d"(rb)						\
++						  :"K"(xra),"I"(s12):"memory");	\
++	}while(0)
++
++#define S32LDIVR(xra,rb,rc,strd2)							\
++	do{														\
++		__asm____volatile("S32LDIVRxr%1,%z0,%z2,%3"			\
++						  :"+d"(rb)							\
++						  :"K"(xra),"d"(rc),"K"(strd2));	\
++	}while(0)
++
++#define S32SDIVR(xra,rb,rc,strd2)									\
++	do{																\
++		__asm____volatile("S32SDIVRxr%1,%z0,%z2,%3"					\
++						  :"+d"(rb)									\
++						  :"K"(xra),"d"(rc),"K"(strd2):"memory");	\
++	}while(0)
++
++#define S8LDD(xra,rb,s8,optn3)										\
++	do{																\
++		__asm____volatile("S8LDDxr%0,%z1,%2,ptn%3"					\
++						  :											\
++						  :"K"(xra),"d"(rb),"I"(s8),"K"(optn3));	\
++	}while(0)
++
++#define S8STD(xra,rb,s8,optn3)											\
++	do{																	\
++		__asm____volatile("S8STDxr%0,%z1,%2,ptn%3"						\
++						  :												\
++						  :"K"(xra),"d"(rb),"I"(s8),"K"(optn3):"memory"); \
++	}while(0)
++
++#define S8LDI(xra,rb,s8,optn3)								\
++	do{														\
++		__asm____volatile("S8LDIxr%1,%z0,%2,ptn%3"			\
++						  :"+d"(rb)							\
++						  :"K"(xra),"I"(s8),"K"(optn3));	\
++	}while(0)
++
++#define S8SDI(xra,rb,s8,optn3)										\
++	do{																\
++		__asm____volatile("S8SDIxr%1,%z0,%2,ptn%3"					\
++						  :"+d"(rb)									\
++						  :"K"(xra),"I"(s8),"K"(optn3):"memory");	\
++	}while(0)
++
++#define S16LDD(xra,rb,s10,optn2)									\
++	do{																\
++		__asm____volatile("S16LDDxr%0,%z1,%2,ptn%3"					\
++						  :											\
++						  :"K"(xra),"d"(rb),"I"(s10),"K"(optn2));	\
++	}while(0)
++
++#define S16STD(xra,rb,s10,optn2)										\
++	do{																	\
++		__asm____volatile("S16STDxr%0,%z1,%2,ptn%3"						\
++						  :												\
++						  :"K"(xra),"d"(rb),"I"(s10),"K"(optn2):"memory"); \
++	}while(0)
++
++#define S16LDI(xra,rb,s10,optn2)							\
++	do{														\
++		__asm____volatile("S16LDIxr%1,%z0,%2,ptn%3"			\
++						  :"+d"(rb)							\
++						  :"K"(xra),"I"(s10),"K"(optn2));	\
++	}while(0)
++
++#define S16SDI(xra,rb,s10,optn2)									\
++	do{																\
++		__asm____volatile("S16SDIxr%1,%z0,%2,ptn%3"					\
++						  :"+d"(rb)									\
++						  :"K"(xra),"I"(s10),"K"(optn2):"memory");	\
++	}while(0)
++
++#define LXW(rb,rc,strd2)												\
++	({																	\
++		unsignedint_dst_;												\
++		__asm____volatile("LXW%0,%1,%2,%3":"=d"(_dst_):"d"(rb),"d"(rc),"K"(strd2));	\
++		_dst_;															\
++	})
++
++#define LXH(rb,rc,strd2)												\
++	({																	\
++		unsignedint_dst_;												\
++		__asm____volatile("LXH%0,%1,%2,%3":"=d"(_dst_):"d"(rb),"d"(rc),"K"(strd2));	\
++		_dst_;															\
++	})
++
++#define LXHU(rb,rc,strd2)												\
++	({																	\
++		unsignedint_dst_;												\
++		__asm____volatile("LXHU%0,%1,%2,%3":"=d"(_dst_):"d"(rb),"d"(rc),"K"(strd2)); \
++		_dst_;															\
++	})
++
++#define LXB(rb,rc,strd2)												\
++	({																	\
++		unsignedint_dst_;												\
++		__asm____volatile("LXB%0,%1,%2,%3":"=d"(_dst_):"d"(rb),"d"(rc),"K"(strd2));	\
++		_dst_;															\
++	})
++
++#define LXBU(rb,rc,strd2)												\
++	({																	\
++		unsignedint_dst_;												\
++		__asm____volatile("LXBU%0,%1,%2,%3":"=d"(_dst_):"d"(rb),"d"(rc),"K"(strd2)); \
++		_dst_;															\
++	})
++/***********************************D16MUL***********************************/
++#define D16MUL_WW(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D16MULxr%0,xr%1,xr%2,xr%3,WW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MUL_LW(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D16MULxr%0,xr%1,xr%2,xr%3,LW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MUL_HW(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D16MULxr%0,xr%1,xr%2,xr%3,HW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MUL_XW(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D16MULxr%0,xr%1,xr%2,xr%3,XW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++
++/**********************************D16MULF*******************************/
++#define D16MULF_WW(xra,xrb,xrc)							\
++	do{													\
++		__asm____volatile("D16MULFxr%0,xr%1,xr%2,WW"	\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define D16MULF_LW(xra,xrb,xrc)							\
++	do{													\
++		__asm____volatile("D16MULFxr%0,xr%1,xr%2,LW"	\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define D16MULF_HW(xra,xrb,xrc)							\
++	do{													\
++		__asm____volatile("D16MULFxr%0,xr%1,xr%2,HW"	\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define D16MULF_XW(xra,xrb,xrc)							\
++	do{													\
++		__asm____volatile("D16MULFxr%0,xr%1,xr%2,XW"	\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++//MXUenhancement
++#define D16MULE_WW(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D16MULExr%0,xr%1,xr%2,xr%3,WW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MULE_LW(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D16MULExr%0,xr%1,xr%2,xr%3,LW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MULE_HW(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D16MULExr%0,xr%1,xr%2,xr%3,HW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MULE_XW(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D16MULExr%0,xr%1,xr%2,xr%3,XW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++/***********************************D16MAC********************************/
++#define D16MAC_AA_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACxr%0,xr%1,xr%2,xr%3,AA,WW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MAC_AA_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACxr%0,xr%1,xr%2,xr%3,AA,LW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MAC_AA_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACxr%0,xr%1,xr%2,xr%3,AA,HW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MAC_AA_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACxr%0,xr%1,xr%2,xr%3,AA,XW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MAC_AS_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACxr%0,xr%1,xr%2,xr%3,AS,WW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MAC_AS_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACxr%0,xr%1,xr%2,xr%3,AS,LW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MAC_AS_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACxr%0,xr%1,xr%2,xr%3,AS,HW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MAC_AS_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACxr%0,xr%1,xr%2,xr%3,AS,XW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MAC_SA_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACxr%0,xr%1,xr%2,xr%3,SA,WW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MAC_SA_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACxr%0,xr%1,xr%2,xr%3,SA,LW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MAC_SA_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACxr%0,xr%1,xr%2,xr%3,SA,HW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MAC_SA_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACxr%0,xr%1,xr%2,xr%3,SA,XW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MAC_SS_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACxr%0,xr%1,xr%2,xr%3,SS,WW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MAC_SS_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACxr%0,xr%1,xr%2,xr%3,SS,LW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MAC_SS_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACxr%0,xr%1,xr%2,xr%3,SS,HW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MAC_SS_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACxr%0,xr%1,xr%2,xr%3,SS,XW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++
++/**********************************D16MACF*******************************/
++#define D16MACF_AA_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACFxr%0,xr%1,xr%2,xr%3,AA,WW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACF_AA_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACFxr%0,xr%1,xr%2,xr%3,AA,LW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACF_AA_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACFxr%0,xr%1,xr%2,xr%3,AA,HW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACF_AA_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACFxr%0,xr%1,xr%2,xr%3,AA,XW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACF_AS_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACFxr%0,xr%1,xr%2,xr%3,AS,WW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACF_AS_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACFxr%0,xr%1,xr%2,xr%3,AS,LW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACF_AS_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACFxr%0,xr%1,xr%2,xr%3,AS,HW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACF_AS_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACFxr%0,xr%1,xr%2,xr%3,AS,XW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACF_SA_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACFxr%0,xr%1,xr%2,xr%3,SA,WW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACF_SA_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACFxr%0,xr%1,xr%2,xr%3,SA,LW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACF_SA_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACFxr%0,xr%1,xr%2,xr%3,SA,HW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACF_SA_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACFxr%0,xr%1,xr%2,xr%3,SA,XW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACF_SS_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACFxr%0,xr%1,xr%2,xr%3,SS,WW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACF_SS_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACFxr%0,xr%1,xr%2,xr%3,SS,LW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACF_SS_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACFxr%0,xr%1,xr%2,xr%3,SS,HW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACF_SS_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACFxr%0,xr%1,xr%2,xr%3,SS,XW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++//MXUenhancement
++/**********************************D16MACE*******************************/
++#define D16MACE_AA_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACExr%0,xr%1,xr%2,xr%3,AA,WW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACE_AA_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACExr%0,xr%1,xr%2,xr%3,AA,LW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACE_AA_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACExr%0,xr%1,xr%2,xr%3,AA,HW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACE_AA_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACExr%0,xr%1,xr%2,xr%3,AA,XW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACE_AS_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACExr%0,xr%1,xr%2,xr%3,AS,WW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACE_AS_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACExr%0,xr%1,xr%2,xr%3,AS,LW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACE_AS_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACExr%0,xr%1,xr%2,xr%3,AS,HW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACE_AS_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACExr%0,xr%1,xr%2,xr%3,AS,XW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACE_SA_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACExr%0,xr%1,xr%2,xr%3,SA,WW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACE_SA_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACExr%0,xr%1,xr%2,xr%3,SA,LW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACE_SA_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACExr%0,xr%1,xr%2,xr%3,SA,HW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACE_SA_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACExr%0,xr%1,xr%2,xr%3,SA,XW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACE_SS_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACExr%0,xr%1,xr%2,xr%3,SS,WW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACE_SS_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACExr%0,xr%1,xr%2,xr%3,SS,LW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACE_SS_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACExr%0,xr%1,xr%2,xr%3,SS,HW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MACE_SS_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MACExr%0,xr%1,xr%2,xr%3,SS,XW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++
++/**********************************D16MADL*******************************/
++#define D16MADL_AA_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MADLxr%0,xr%1,xr%2,xr%3,AA,WW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MADL_AA_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MADLxr%0,xr%1,xr%2,xr%3,AA,LW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MADL_AA_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MADLxr%0,xr%1,xr%2,xr%3,AA,HW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MADL_AA_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MADLxr%0,xr%1,xr%2,xr%3,AA,XW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MADL_AS_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MADLxr%0,xr%1,xr%2,xr%3,AS,WW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MADL_AS_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MADLxr%0,xr%1,xr%2,xr%3,AS,LW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MADL_AS_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MADLxr%0,xr%1,xr%2,xr%3,AS,HW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MADL_AS_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MADLxr%0,xr%1,xr%2,xr%3,AS,XW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MADL_SA_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MADLxr%0,xr%1,xr%2,xr%3,SA,WW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MADL_SA_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MADLxr%0,xr%1,xr%2,xr%3,SA,LW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MADL_SA_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MADLxr%0,xr%1,xr%2,xr%3,SA,HW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MADL_SA_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MADLxr%0,xr%1,xr%2,xr%3,SA,XW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MADL_SS_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MADLxr%0,xr%1,xr%2,xr%3,SS,WW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MADL_SS_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MADLxr%0,xr%1,xr%2,xr%3,SS,LW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MADL_SS_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MADLxr%0,xr%1,xr%2,xr%3,SS,HW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D16MADL_SS_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("D16MADLxr%0,xr%1,xr%2,xr%3,SS,XW"		\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++
++/***********************************S16MAD*******************************/
++#define S16MAD_A_HH(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("S16MADxr%0,xr%1,xr%2,xr%3,A,0"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define S16MAD_A_LL(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("S16MADxr%0,xr%1,xr%2,xr%3,A,1"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define S16MAD_A_HL(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("S16MADxr%0,xr%1,xr%2,xr%3,A,2"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define S16MAD_A_LH(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("S16MADxr%0,xr%1,xr%2,xr%3,A,3"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define S16MAD_S_HH(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("S16MADxr%0,xr%1,xr%2,xr%3,S,0"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define S16MAD_S_LL(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("S16MADxr%0,xr%1,xr%2,xr%3,S,1"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define S16MAD_S_HL(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("S16MADxr%0,xr%1,xr%2,xr%3,S,2"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define S16MAD_S_LH(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("S16MADxr%0,xr%1,xr%2,xr%3,S,3"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++
++
++/***********************************Q8MUL********************************/
++#define Q8MUL(xra,xrb,xrc,xrd)										\
++	do{																\
++		__asm____volatile("Q8MULxr%0,xr%1,xr%2,xr%3"				\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++//MXUenhancement
++#define Q8MULSU(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8MULSUxr%0,xr%1,xr%2,xr%3"				\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++
++/***********************************Q8MAC********************************/
++#define Q8MAC_AA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8MACxr%0,xr%1,xr%2,xr%3,AA"				\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q8MAC_AS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8MACxr%0,xr%1,xr%2,xr%3,AS"				\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q8MAC_SA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8MACxr%0,xr%1,xr%2,xr%3,SA"				\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q8MAC_SS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8MACxr%0,xr%1,xr%2,xr%3,SS"				\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++//MXUenhancement
++#define Q8MACSU_AA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8MACSUxr%0,xr%1,xr%2,xr%3,AA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q8MACSU_AS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8MACSUxr%0,xr%1,xr%2,xr%3,AS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q8MACSU_SA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8MACSUxr%0,xr%1,xr%2,xr%3,SA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q8MACSU_SS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8MACSUxr%0,xr%1,xr%2,xr%3,SS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++/***********************************Q8MADL********************************/
++#define Q8MADL_AA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8MADLxr%0,xr%1,xr%2,xr%3,AA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q8MADL_AS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8MADLxr%0,xr%1,xr%2,xr%3,AS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q8MADL_SA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8MADLxr%0,xr%1,xr%2,xr%3,SA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q8MADL_SS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8MADLxr%0,xr%1,xr%2,xr%3,SS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++
++/***********************************D32ADD********************************/
++#define D32ADD_AA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D32ADDxr%0,xr%1,xr%2,xr%3,AA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D32ADD_AS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D32ADDxr%0,xr%1,xr%2,xr%3,AS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D32ADD_SA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D32ADDxr%0,xr%1,xr%2,xr%3,SA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D32ADD_SS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D32ADDxr%0,xr%1,xr%2,xr%3,SS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++
++/***********************************D32ACC********************************/
++#define D32ACC_AA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D32ACCxr%0,xr%1,xr%2,xr%3,AA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D32ACC_AS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D32ACCxr%0,xr%1,xr%2,xr%3,AS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D32ACC_SA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D32ACCxr%0,xr%1,xr%2,xr%3,SA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D32ACC_SS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D32ACCxr%0,xr%1,xr%2,xr%3,SS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++//MXUenhancement
++#define D32ACCM_AA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D32ACCMxr%0,xr%1,xr%2,xr%3,AA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D32ACCM_AS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D32ACCMxr%0,xr%1,xr%2,xr%3,AS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D32ACCM_SA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D32ACCMxr%0,xr%1,xr%2,xr%3,SA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D32ACCM_SS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D32ACCMxr%0,xr%1,xr%2,xr%3,SS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D32ASUM_AA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D32ASUMxr%0,xr%1,xr%2,xr%3,AA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D32ASUM_AS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D32ASUMxr%0,xr%1,xr%2,xr%3,AS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D32ASUM_SA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D32ASUMxr%0,xr%1,xr%2,xr%3,SA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define D32ASUM_SS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D32ASUMxr%0,xr%1,xr%2,xr%3,SS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++
++/***********************************S32CPS********************************/
++#define S32CPS(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("S32CPSxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++//MXUenhancement
++#define S32SLT(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("S32SLTxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define S32MOVZ(xra,xrb,xrc)							\
++	do{													\
++		__asm____volatile("S32MOVZxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define S32MOVN(xra,xrb,xrc)							\
++	do{													\
++		__asm____volatile("S32MOVNxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define S32AND(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("S32ANDxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define S32OR(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("S32ORxr%0,xr%1,xr%2"			\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define S32XOR(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("S32XORxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define S32NOR(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("S32NORxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define S32ABS(xra,xrb)									\
++	do{													\
++		__asm____volatile("S32CPSxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrb));	\
++	}while(0)
++
++/***********************************Q16ADD********************************/
++#define Q16ADD_AA_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("Q16ADDxr%0,xr%1,xr%2,xr%3,AA,WW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ADD_AA_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("Q16ADDxr%0,xr%1,xr%2,xr%3,AA,LW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ADD_AA_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("Q16ADDxr%0,xr%1,xr%2,xr%3,AA,HW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ADD_AA_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("Q16ADDxr%0,xr%1,xr%2,xr%3,AA,XW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++#define Q16ADD_AS_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("Q16ADDxr%0,xr%1,xr%2,xr%3,AS,WW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ADD_AS_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("Q16ADDxr%0,xr%1,xr%2,xr%3,AS,LW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ADD_AS_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("Q16ADDxr%0,xr%1,xr%2,xr%3,AS,HW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ADD_AS_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("Q16ADDxr%0,xr%1,xr%2,xr%3,AS,XW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ADD_SA_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("Q16ADDxr%0,xr%1,xr%2,xr%3,SA,WW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ADD_SA_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("Q16ADDxr%0,xr%1,xr%2,xr%3,SA,LW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ADD_SA_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("Q16ADDxr%0,xr%1,xr%2,xr%3,SA,HW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ADD_SA_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("Q16ADDxr%0,xr%1,xr%2,xr%3,SA,XW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ADD_SS_WW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("Q16ADDxr%0,xr%1,xr%2,xr%3,SS,WW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ADD_SS_LW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("Q16ADDxr%0,xr%1,xr%2,xr%3,SS,LW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ADD_SS_HW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("Q16ADDxr%0,xr%1,xr%2,xr%3,SS,HW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ADD_SS_XW(xra,xrb,xrc,xrd)								\
++	do{																\
++		__asm____volatile("Q16ADDxr%0,xr%1,xr%2,xr%3,SS,XW"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++
++/***********************************Q16ACC********************************/
++#define Q16ACC_AA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q16ACCxr%0,xr%1,xr%2,xr%3,AA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ACC_AS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q16ACCxr%0,xr%1,xr%2,xr%3,AS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ACC_SA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q16ACCxr%0,xr%1,xr%2,xr%3,SA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ACC_SS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q16ACCxr%0,xr%1,xr%2,xr%3,SS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++//MXUenhancement
++#define Q16ACCM_AA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q16ACCMxr%0,xr%1,xr%2,xr%3,AA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ACCM_AS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q16ACCMxr%0,xr%1,xr%2,xr%3,AS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ACCM_SA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q16ACCMxr%0,xr%1,xr%2,xr%3,SA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ACCM_SS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q16ACCMxr%0,xr%1,xr%2,xr%3,SS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ASUM_AA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q16ASUMxr%0,xr%1,xr%2,xr%3,AA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ASUM_AS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q16ASUMxr%0,xr%1,xr%2,xr%3,AS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ASUM_SA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q16ASUMxr%0,xr%1,xr%2,xr%3,SA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q16ASUM_SS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q16ASUMxr%0,xr%1,xr%2,xr%3,SS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++/***********************************D16CPS********************************/
++#define D16CPS(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("D16CPSxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++//MXUenhancement
++#define D16SLT(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("D16SLTxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define D16MOVZ(xra,xrb,xrc)							\
++	do{													\
++		__asm____volatile("D16MOVZxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define D16MOVN(xra,xrb,xrc)							\
++	do{													\
++		__asm____volatile("D16MOVNxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define D16ABS(xra,xrb)									\
++	do{													\
++		__asm____volatile("D16CPSxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrb));	\
++	}while(0)
++
++/*******************************D16ASUM************************************/
++#define D16ASUM_AA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D16ASUMxr%0,xr%1,xr%2,xr%3,AA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++#define D16ASUM_AS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D16ASUMxr%0,xr%1,xr%2,xr%3,AS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++#define D16ASUM_SA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D16ASUMxr%0,xr%1,xr%2,xr%3,SA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++#define D16ASUM_SS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("D16ASUMxr%0,xr%1,xr%2,xr%3,SS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++/*******************************D16AVG/D16AVGR*****************************/
++#define D16AVG(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("D16AVGxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++#define D16AVGR(xra,xrb,xrc)							\
++	do{													\
++		__asm____volatile("D16AVGRxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++/************************************Q8ADD********************************/
++#define Q8ADD_AA(xra,xrb,xrc)							\
++	do{													\
++		__asm____volatile("Q8ADDxr%0,xr%1,xr%2,AA"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define Q8ADD_AS(xra,xrb,xrc)							\
++	do{													\
++		__asm____volatile("Q8ADDxr%0,xr%1,xr%2,AS"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define Q8ADD_SA(xra,xrb,xrc)							\
++	do{													\
++		__asm____volatile("Q8ADDxr%0,xr%1,xr%2,SA"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define Q8ADD_SS(xra,xrb,xrc)							\
++	do{													\
++		__asm____volatile("Q8ADDxr%0,xr%1,xr%2,SS"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++
++/************************************Q8ADDE********************************/
++#define Q8ADDE_AA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8ADDExr%0,xr%1,xr%2,xr%3,AA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q8ADDE_AS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8ADDExr%0,xr%1,xr%2,xr%3,AS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q8ADDE_SA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8ADDExr%0,xr%1,xr%2,xr%3,SA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q8ADDE_SS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8ADDExr%0,xr%1,xr%2,xr%3,SS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++/************************************Q8ACCE********************************/
++#define Q8ACCE_AA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8ACCExr%0,xr%1,xr%2,xr%3,AA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q8ACCE_AS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8ACCExr%0,xr%1,xr%2,xr%3,AS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q8ACCE_SA(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8ACCExr%0,xr%1,xr%2,xr%3,SA"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++#define Q8ACCE_SS(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q8ACCExr%0,xr%1,xr%2,xr%3,SS"			\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++
++/************************************Q8ABD********************************/
++#define Q8ABD(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("Q8ABDxr%0,xr%1,xr%2"			\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++
++/************************************Q8SLT********************************/
++#define Q8SLT(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("Q8SLTxr%0,xr%1,xr%2"			\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++//MXUenhancement
++#define Q8SLTU(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("Q8SLTUxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define Q8MOVZ(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("Q8MOVZxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define Q8MOVN(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("Q8MOVNxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define D8SUM(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("D8SUMxr%0,xr%1,xr%2"			\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define D8SUMC(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("D8SUMCxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++/************************************Q8SAD********************************/
++#define Q8SAD(xra,xrb,xrc,xrd)										\
++	do{																\
++		__asm____volatile("Q8SADxr%0,xr%1,xr%2,xr%3"				\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++/************************************Q16SCOP******************************/
++#define Q16SCOP(xra,xrb,xrc,xrd)									\
++	do{																\
++		__asm____volatile("Q16SCOPxr%0,xr%1,xr%2,xr%3"				\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd));	\
++	}while(0)
++
++/********************************Q8AVG/Q8AVGR*****************************/
++#define Q8AVG(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("Q8AVGxr%0,xr%1,xr%2"			\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++#define Q8AVGR(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("Q8AVGRxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++
++/**********************************D32SHIFT******************************/
++#define D32SLL(xra,xrb,xrc,xrd,SFT4)									\
++	do{																	\
++		__asm____volatile("D32SLLxr%0,xr%1,xr%2,xr%3,%4"				\
++						  :												\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd),"K"(SFT4)); \
++	}while(0)
++
++#define D32SLR(xra,xrb,xrc,xrd,SFT4)									\
++	do{																	\
++		__asm____volatile("D32SLRxr%0,xr%1,xr%2,xr%3,%4"				\
++						  :												\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd),"K"(SFT4)); \
++	}while(0)
++
++#define D32SAR(xra,xrb,xrc,xrd,SFT4)									\
++	do{																	\
++		__asm____volatile("D32SARxr%0,xr%1,xr%2,xr%3,%4"				\
++						  :												\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd),"K"(SFT4)); \
++	}while(0)
++
++#define D32SARL(xra,xrb,xrc,SFT4)									\
++	do{																\
++		__asm____volatile("D32SARLxr%0,xr%1,xr%2,%3"				\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(SFT4));	\
++	}while(0)
++
++#define D32SLLV(xra,xrd,rb)								\
++	do{													\
++		__asm____volatile("D32SLLVxr%0,xr%1,%z2"		\
++						  :								\
++						  :"K"(xra),"K"(xrd),"d"(rb));	\
++	}while(0)
++
++#define D32SLRV(xra,xrd,rb)								\
++	do{													\
++		__asm____volatile("D32SLRVxr%0,xr%1,%z2"		\
++						  :								\
++						  :"K"(xra),"K"(xrd),"d"(rb));	\
++	}while(0)
++
++#define D32SARV(xra,xrd,rb)								\
++	do{													\
++		__asm____volatile("D32SARVxr%0,xr%1,%z2"		\
++						  :								\
++						  :"K"(xra),"K"(xrd),"d"(rb));	\
++	}while(0)
++
++#define D32SARW(xra,xrb,xrc,rb)									\
++	do{															\
++		__asm____volatile("D32SARWxr%0,xr%1,xr%2,%3"			\
++						  :										\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"d"(rb));	\
++	}while(0)
++
++
++/**********************************Q16SHIFT******************************/
++#define Q16SLL(xra,xrb,xrc,xrd,SFT4)									\
++	do{																	\
++		__asm____volatile("Q16SLLxr%0,xr%1,xr%2,xr%3,%4"				\
++						  :												\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd),"K"(SFT4)); \
++	}while(0)
++
++#define Q16SLR(xra,xrb,xrc,xrd,SFT4)									\
++	do{																	\
++		__asm____volatile("Q16SLRxr%0,xr%1,xr%2,xr%3,%4"				\
++						  :												\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd),"K"(SFT4)); \
++	}while(0)
++
++#define Q16SAR(xra,xrb,xrc,xrd,SFT4)									\
++	do{																	\
++		__asm____volatile("Q16SARxr%0,xr%1,xr%2,xr%3,%4"				\
++						  :												\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd),"K"(SFT4)); \
++	}while(0)
++
++#define Q16SLLV(xra,xrd,rb)								\
++	do{													\
++		__asm____volatile("Q16SLLVxr%0,xr%1,%z2"		\
++						  :								\
++						  :"K"(xra),"K"(xrd),"d"(rb));	\
++	}while(0)
++
++#define Q16SLRV(xra,xrd,rb)								\
++	do{													\
++		__asm____volatile("Q16SLRVxr%0,xr%1,%z2"		\
++						  :								\
++						  :"K"(xra),"K"(xrd),"d"(rb));	\
++	}while(0)
++
++#define Q16SARV(xra,xrd,rb)								\
++	do{													\
++		__asm____volatile("Q16SARVxr%0,xr%1,%z2"		\
++						  :								\
++						  :"K"(xra),"K"(xrd),"d"(rb));	\
++	}while(0)
++
++
++/*********************************MAX/MIN*********************************/
++#define S32MAX(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("S32MAXxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define S32MIN(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("S32MINxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define D16MAX(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("D16MAXxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define D16MIN(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("D16MINxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define Q8MAX(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("Q8MAXxr%0,xr%1,xr%2"			\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define Q8MIN(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("Q8MINxr%0,xr%1,xr%2"			\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++
++/*************************************MOVE********************************/
++#define S32I2M(xra,rb)							\
++	do{											\
++		__asm____volatile("S32I2Mxr%0,%z1"		\
++						  :						\
++						  :"K"(xra),"d"(rb));	\
++	}while(0)
++
++#define S32M2I(xra)								\
++	__extension__({								\
++			int__d;								\
++			__asm____volatile("S32M2Ixr%1,%0"	\
++							  :"=d"(__d)		\
++							  :"K"(xra));		\
++			__d;								\
++		})
++
++
++/*********************************S32SFL**********************************/
++#define S32SFL(xra,xrb,xrc,xrd,optn2)									\
++	do{																	\
++		__asm____volatile("S32SFLxr%0,xr%1,xr%2,xr%3,ptn%4"				\
++						  :												\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd),"K"(optn2));	\
++	}while(0)
++
++//MXUenhancement
++#define S32ALNI(xra,xrb,xrc,optn3)									\
++	do{																\
++		__asm____volatile("S32ALNIxr%0,xr%1,xr%2,ptn%3"				\
++						  :											\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"K"(optn3));	\
++	}while(0)
++
++#define S32LUI(xra,s8,optn3)								\
++	do{														\
++		__asm____volatile("S32LUIxr%0,%1,ptn%2"				\
++						  :									\
++						  :"K"(xra),"I"(s8),"K"(optn3));	\
++	}while(0)
++
++
++/*********************************S32ALN**********************************/
++#define S32ALN(xra,xrb,xrc,rs)									\
++	do{															\
++		__asm____volatile("S32ALNxr%0,xr%1,xr%2,%z3"			\
++						  :										\
++						  :"K"(xra),"K"(xrb),"K"(xrc),"d"(rs));	\
++	}while(0)
++
++
++/*********************************Q16SAT**********************************/
++#define Q16SAT(xra,xrb,xrc)								\
++	do{													\
++		__asm____volatile("Q16SATxr%0,xr%1,xr%2"		\
++						  :								\
++						  :"K"(xra),"K"(xrb),"K"(xrc));	\
++	}while(0)
++
++#define S32EXTR(xra,xrd,rs,bits5)									\
++	do{																\
++		__asm____volatile("S32EXTRxr%0,xr%1,%z2,%3"					\
++						  :											\
++						  :"K"(xra),"K"(xrd),"d"(rs),"I"(bits5));	\
++	}while(0)
++
++#define S32EXTRV(xra,xrd,rs,rt)									\
++	do{															\
++		__asm____volatile("S32EXTRVxr%0,xr%1,%z2,%z3"			\
++						  :										\
++						  :"K"(xra),"K"(xrd),"d"(rs),"d"(rt));	\
++	}while(0)
++
++/*********************************S32MUL**********************************/
++#define S32MUL(xra,xrd,rs,rt)									\
++	do{															\
++		__asm____volatile("S32MULxr%0,xr%1,%z2,%z3"				\
++						  :										\
++						  :"K"(xra),"K"(xrd),"d"(rs),"d"(rt));	\
++	}while(0)
++
++#define S32MULU(xra,xrd,rs,rt)									\
++	do{															\
++		__asm____volatile("S32MULUxr%0,xr%1,%z2,%z3"			\
++						  :										\
++						  :"K"(xra),"K"(xrd),"d"(rs),"d"(rt));	\
++	}while(0)
++
++#define S32MADD(xra,xrd,rs,rt)									\
++	do{															\
++		__asm____volatile("S32MADDxr%0,xr%1,%z2,%z3"			\
++						  :										\
++						  :"K"(xra),"K"(xrd),"d"(rs),"d"(rt));	\
++	}while(0)
++
++#define S32MADDU(xra,xrd,rs,rt)									\
++	do{															\
++		__asm____volatile("S32MADDUxr%0,xr%1,%z2,%z3"			\
++						  :										\
++						  :"K"(xra),"K"(xrd),"d"(rs),"d"(rt));	\
++	}while(0)
++
++#define S32MSUB(xra,xrd,rs,rt)									\
++	do{															\
++		__asm____volatile("S32MSUBxr%0,xr%1,%z2,%z3"			\
++						  :										\
++						  :"K"(xra),"K"(xrd),"d"(rs),"d"(rt));	\
++	}while(0)
++
++#define S32MSUBU(xra,xrd,rs,rt)									\
++	do{															\
++		__asm____volatile("S32MSUBUxr%0,xr%1,%z2,%z3"			\
++						  :										\
++						  :"K"(xra),"K"(xrd),"d"(rs),"d"(rt));	\
++	}while(0)
++
++#endif/*_MXU_H_*/
+diff --git a/arch/mips/xburst/common/include/mxuv3.h b/arch/mips/xburst/common/include/mxuv3.h
+new file mode 100644
+index 000000000..10c631b0e
+--- /dev/null
++++ b/arch/mips/xburst/common/include/mxuv3.h
+@@ -0,0 +1,47 @@
++/*
++ * Copyright (C) 2005 Mips Technologies
++ * Author: Chris Dearman, chris@mips.com derived from fpu.h
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#ifndef _ASM_MXU_V3_H
++#define _ASM_MXU_V3_H
++
++#include <asm/cpu.h>
++#include <asm/cpu-features.h>
++#include <asm/hazards.h>
++#include <asm/mipsregs.h>
++#include <linux/printk.h>
++
++void __init_mxuv3(void);
++void __save_mxuv3(void *tsk_void);
++void __restore_mxuv3(void *tsk_void);
++
++static inline void init_mxuv3(void)
++{
++	if(cpu_has_mxuv3)
++		__init_mxuv3();
++}
++
++
++#define save_mxuv3(tsk)							\
++	do {										\
++		if (cpu_has_mxuv3)						\
++			__save_mxuv3(tsk);					\
++	} while (0)
++
++static inline unsigned int is_mxuv3_enabled(void)
++{
++	return ((cpu_has_mxuv3) && (read_c0_status() & ST0_CU2));
++}
++
++#define restore_mxuv3(tsk)						\
++	do {										\
++		if (cpu_has_mxuv3)						\
++			__restore_mxuv3(tsk);					\
++	} while (0)
++
++#endif /* _ASM_MXU_V3_H */
+diff --git a/arch/mips/xburst/common/initrd-check.c b/arch/mips/xburst/common/initrd-check.c
+new file mode 100644
+index 000000000..9ed9b5513
+--- /dev/null
++++ b/arch/mips/xburst/common/initrd-check.c
+@@ -0,0 +1,49 @@
++
++#include <linux/init.h>
++#include <linux/stat.h>
++#include <linux/kdev_t.h>
++#include <linux/syscalls.h>
++
++static void check_file(char *fname)
++{
++	int err;
++	pr_info("check file %s ... ",fname);
++	err = sys_access((const char __user *) fname, O_RDONLY);
++	if (err < 0)
++		pr_info("failed %d.\n", err);
++	else
++		pr_info("successed.\n");
++}
++
++static int __init check_rootfs(void)
++{
++	int err;
++
++	if (sys_access((const char __user *) "/dev", O_RDWR) < 0) {
++		pr_info("Dir /dev is not exist.\n");
++		sys_mkdir((const char __user *) "/dev", O_RDWR);
++	}
++
++	if (sys_access((const char __user *) "/dev/console", O_RDWR) < 0) {
++		printk("create /dev/console\n");
++		err = sys_mknod((const char __user __force *) "/dev/console",
++				S_IFCHR | S_IRUSR | S_IWUSR,
++				new_encode_dev(MKDEV(5, 1)));
++		if (err < 0)
++			goto out;
++	}
++
++	check_file("/linuxrc");
++	check_file("/init");
++	check_file("/init.rc");
++	check_file("/sbin/adbd");
++	check_file("/bin/busybox");
++
++	return 0;
++
++out:
++	printk(KERN_WARNING "Failed to create dev\n");
++	return err;
++}
++
++late_initcall(check_rootfs);
+diff --git a/arch/mips/xburst/common/jz_notifier.c b/arch/mips/xburst/common/jz_notifier.c
+new file mode 100644
+index 000000000..48621a797
+--- /dev/null
++++ b/arch/mips/xburst/common/jz_notifier.c
+@@ -0,0 +1,83 @@
++#include <jz_notifier.h>
++
++static BLOCKING_NOTIFIER_HEAD(jz_notifier_chain_high);
++static BLOCKING_NOTIFIER_HEAD(jz_notifier_chain_normal);
++static BLOCKING_NOTIFIER_HEAD(jz_notifier_chain_low);
++static int jz_notifier(struct notifier_block *nb, unsigned long cmd, void *data)
++{
++	struct jz_notifier *jz_nb = container_of(nb,struct jz_notifier,nb);
++	int ret = 0;
++	if(jz_nb->msg == cmd) {
++		ret = jz_nb->jz_notify(jz_nb,data);
++	}
++	return ret;
++}
++
++int jz_notifier_register(struct jz_notifier *notify, unsigned int priority)
++{
++	unsigned int ret = 0;
++
++	if((notify->level < NOTEFY_PROI_START) && (notify->level >= NOTEFY_PROI_END))
++	{
++		printk("notify level can not support this %d\n",notify->level);
++		dump_stack();
++		return -1;
++	}
++	if((int)notify->msg >= JZ_CMD_END && (int)notify->msg <= JZ_CMD_START)
++	{
++		printk("notify msg can not support this %d\n",notify->msg);
++		dump_stack();
++		return -1;
++	}
++	if(notify->jz_notify == NULL)
++	{
++		printk("notify function(jz_notify) cand not support NULL\n");
++		dump_stack();
++		return -1;
++	}
++	notify->nb.priority = notify->level;
++	notify->nb.notifier_call = jz_notifier;
++
++	if(priority == NOTEFY_PROI_HIGH)
++		ret = blocking_notifier_chain_register(&jz_notifier_chain_high, &notify->nb);
++	else if(priority == NOTEFY_PROI_NORMAL)
++		ret = blocking_notifier_chain_register(&jz_notifier_chain_normal, &notify->nb);
++	else if(priority == NOTEFY_PROI_LOW)
++		ret = blocking_notifier_chain_register(&jz_notifier_chain_low, &notify->nb);
++	else
++		printk("not support\n");
++	return ret;
++}
++EXPORT_SYMBOL(jz_notifier_register);
++
++int jz_notifier_unregister(struct jz_notifier *notify, unsigned int priority)
++{
++	unsigned int ret = 0;
++
++	if(priority == NOTEFY_PROI_HIGH)
++		ret = blocking_notifier_chain_unregister(&jz_notifier_chain_high, &notify->nb);
++	else if(priority == NOTEFY_PROI_NORMAL)
++		ret = blocking_notifier_chain_unregister(&jz_notifier_chain_normal, &notify->nb);
++	else if(priority == NOTEFY_PROI_LOW)
++		ret = blocking_notifier_chain_unregister(&jz_notifier_chain_low, &notify->nb);
++	else
++		printk("not support\n");
++	return ret;
++}
++EXPORT_SYMBOL(jz_notifier_unregister);
++
++int jz_notifier_call(unsigned int priority, unsigned long val, void *v)
++{
++	unsigned int ret = 0;
++
++	if(priority == NOTEFY_PROI_HIGH)
++		ret = blocking_notifier_call_chain(&jz_notifier_chain_high, val, v);
++	else if(priority == NOTEFY_PROI_NORMAL)
++		ret = blocking_notifier_call_chain(&jz_notifier_chain_normal, val, v);
++	else if(priority == NOTEFY_PROI_LOW)
++		ret = blocking_notifier_call_chain(&jz_notifier_chain_low, val, v);
++	else
++		printk("not support\n");
++	return ret;
++}
++EXPORT_SYMBOL(jz_notifier_call);
+diff --git a/arch/mips/xburst/common/mxu-xburst.c b/arch/mips/xburst/common/mxu-xburst.c
+new file mode 100644
+index 000000000..dddaf6cc5
+--- /dev/null
++++ b/arch/mips/xburst/common/mxu-xburst.c
+@@ -0,0 +1,85 @@
++#include <asm/processor.h>
++#include <linux/sched.h>
++#include <mxu.h>
++
++void __save_mxu(void *tsk_void)
++{
++#if 0
++	struct task_struct *tsk = tsk_void;
++	register unsigned int reg_val asm("t0");
++	asm volatile(".word	0x7008042e \n\t");
++	tsk->thread.mxu.regs[0] = reg_val;
++	asm volatile(".word	0x7008006e \n\t");
++	tsk->thread.mxu.regs[1] = reg_val;
++	asm volatile(".word	0x700800ae \n\t");
++	tsk->thread.mxu.regs[2] = reg_val;
++	asm volatile(".word	0x700800ee \n\t");
++	tsk->thread.mxu.regs[3] = reg_val;
++	asm volatile(".word	0x7008012e \n\t");
++	tsk->thread.mxu.regs[4] = reg_val;
++	asm volatile(".word	0x7008016e \n\t");
++	tsk->thread.mxu.regs[5] = reg_val;
++	asm volatile(".word	0x700801ae \n\t");
++	tsk->thread.mxu.regs[6] = reg_val;
++	asm volatile(".word	0x700801ee \n\t");
++	tsk->thread.mxu.regs[7] = reg_val;
++	asm volatile(".word	0x7008022e \n\t");
++	tsk->thread.mxu.regs[8] = reg_val;
++	asm volatile(".word	0x7008026e \n\t");
++	tsk->thread.mxu.regs[9] = reg_val;
++	asm volatile(".word	0x700802ae \n\t");
++	tsk->thread.mxu.regs[10] = reg_val;
++	asm volatile(".word	0x700802ee \n\t");
++	tsk->thread.mxu.regs[11] = reg_val;
++	asm volatile(".word	0x7008032e \n\t");
++	tsk->thread.mxu.regs[12] = reg_val;
++	asm volatile(".word	0x7008036e \n\t");
++	tsk->thread.mxu.regs[13] = reg_val;
++	asm volatile(".word	0x700803ae \n\t");
++	tsk->thread.mxu.regs[14] = reg_val;
++	asm volatile(".word	0x700803ee \n\t");
++	tsk->thread.mxu.regs[15] = reg_val;
++#endif
++}
++
++void __restore_mxu(void * tsk_void)
++{
++#if 0
++	struct task_struct *tsk = tsk_void;
++	register unsigned int reg_val asm("t0");
++
++	reg_val = tsk->thread.mxu.regs[0];
++	asm volatile(".word	0x7008042f \n\t"::"r"(reg_val));
++	reg_val = tsk->thread.mxu.regs[1];
++	asm volatile(".word	0x7008006f \n\t"::"r"(reg_val));
++	reg_val = tsk->thread.mxu.regs[2];
++	asm volatile(".word	0x700800af \n\t"::"r"(reg_val));
++	reg_val = tsk->thread.mxu.regs[3];
++	asm volatile(".word	0x700800ef \n\t"::"r"(reg_val));
++	reg_val = tsk->thread.mxu.regs[4];
++	asm volatile(".word	0x7008012f \n\t"::"r"(reg_val));
++	reg_val = tsk->thread.mxu.regs[5];
++	asm volatile(".word	0x7008016f \n\t"::"r"(reg_val));
++	reg_val = tsk->thread.mxu.regs[6];
++	asm volatile(".word	0x700801af \n\t"::"r"(reg_val));
++	reg_val = tsk->thread.mxu.regs[7];
++	asm volatile(".word	0x700801ef \n\t"::"r"(reg_val));
++	reg_val = tsk->thread.mxu.regs[8];
++	asm volatile(".word	0x7008022f \n\t"::"r"(reg_val));
++	reg_val = tsk->thread.mxu.regs[9];
++	asm volatile(".word	0x7008026f \n\t"::"r"(reg_val));
++	reg_val = tsk->thread.mxu.regs[10];
++	asm volatile(".word	0x700802af \n\t"::"r"(reg_val));
++	reg_val = tsk->thread.mxu.regs[11];
++	asm volatile(".word	0x700802ef \n\t"::"r"(reg_val));
++	reg_val = tsk->thread.mxu.regs[12];
++	asm volatile(".word	0x7008032f \n\t"::"r"(reg_val));
++	reg_val = tsk->thread.mxu.regs[13];
++	asm volatile(".word	0x7008036f \n\t"::"r"(reg_val));
++	reg_val = tsk->thread.mxu.regs[14];
++	asm volatile(".word	0x700803af \n\t"::"r"(reg_val));
++	reg_val = tsk->thread.mxu.regs[15];
++	asm volatile(".word	0x700803ef \n\t"::"r"(reg_val));
++#endif
++}
++
+diff --git a/arch/mips/xburst/common/proc.c b/arch/mips/xburst/common/proc.c
+new file mode 100644
+index 000000000..a32e05820
+--- /dev/null
++++ b/arch/mips/xburst/common/proc.c
+@@ -0,0 +1,92 @@
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/sysctl.h>
++#include <linux/proc_fs.h>
++#include <linux/fs.h>
++#include <linux/slab.h>
++#include <linux/seq_file.h>
++#include <linux/page-flags.h>
++#include <asm/uaccess.h>
++#include <ingenic_proc.h>
++static struct proc_dir_entry *proc_jz_root;
++struct proc_dir_entry * jz_proc_mkdir(char *s)
++{
++	struct proc_dir_entry *p;
++	if(!proc_jz_root) {
++		proc_jz_root = proc_mkdir("jz", 0);
++		if(!proc_jz_root)
++			return NULL;
++	}
++	p = proc_mkdir(s,proc_jz_root);
++	return p;
++}
++
++EXPORT_SYMBOL(jz_proc_mkdir);
++
++static int jz_proc_show(struct seq_file *filq, void *v)
++{
++	int ret = 1;
++	struct jz_single_file_ops *proc_fops = filq->private;
++	filq->private = proc_fops->data;
++
++	if(proc_fops->read)
++		ret = proc_fops->read(filq, v);
++
++	filq->private = proc_fops;
++	return ret;
++}
++static int jz_proc_open(struct inode *inode, struct file *file)
++{
++	return single_open(file, jz_proc_show, PDE_DATA(inode));
++}
++static ssize_t jz_proc_write(struct file *file, const char __user *buffer, size_t usize, loff_t *off)
++{
++	size_t ret;
++	struct jz_single_file_ops *proc_fops = ((struct seq_file *)file->private_data)->private;
++	((struct seq_file *)file->private_data)->private = proc_fops->data;
++
++	ret = proc_fops->write(file, buffer, usize, off);
++	((struct seq_file *)file->private_data)->private = proc_fops;
++
++	return ret;
++}
++
++struct proc_dir_entry *jz_proc_create_data(
++	const char *name, umode_t mode, struct proc_dir_entry *parent,
++	struct jz_single_file_ops *proc_fops, void *data)
++{
++	struct proc_ops *jz_proc_fops;
++
++	jz_proc_fops = kmalloc(sizeof(struct proc_ops), GFP_KERNEL);
++	if(!jz_proc_fops) {
++		return NULL;
++	}
++
++	jz_proc_fops->proc_read = seq_read;
++	jz_proc_fops->proc_lseek = seq_lseek;
++	jz_proc_fops->proc_release = single_release;
++	jz_proc_fops->proc_open = jz_proc_open;
++	jz_proc_fops->proc_write = jz_proc_write;
++	proc_fops->data = data;
++
++	return proc_create_data(name, mode, parent, jz_proc_fops, proc_fops);
++}
++
++struct proc_dir_entry *jz_proc_create(
++	const char *name, umode_t mode, struct proc_dir_entry *parent,
++	struct jz_single_file_ops *proc_fops)
++{
++	return jz_proc_create_data(name, mode, parent, proc_fops, NULL);
++}
++
++struct proc_dir_entry * get_jz_proc_root(void)
++{
++	if(!proc_jz_root) {
++		proc_jz_root = proc_mkdir("jz", 0);
++		if(!proc_jz_root)
++			return NULL;
++	}
++	return proc_jz_root;
++}
+diff --git a/arch/mips/xburst/common/prom.c b/arch/mips/xburst/common/prom.c
+new file mode 100644
+index 000000000..d2dedbec0
+--- /dev/null
++++ b/arch/mips/xburst/common/prom.c
+@@ -0,0 +1,63 @@
++/*
++ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ *  INGENIC SoC prom code
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under  the terms of the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the License, or (at your
++ *  option) any later version.
++ *
++ *  You should have received a copy of the GNU General Public License along
++ *  with this program; if not, write to the Free Software Foundation, Inc.,
++ *  675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/of_fdt.h>
++#include <asm/fw/fw.h>
++#include <asm/io.h>
++#include <linux/kernel.h>
++#ifdef CONFIG_XBURST_MXUV2
++#include <asm/current.h>
++#include <linux/sched.h>
++#endif
++
++extern struct plat_smp_ops ingenic_soc_smp_ops;
++
++static void *_fw_fdt_addr;
++
++void __init prom_init(void)
++{
++	fw_init_cmdline();
++
++	if (fw_arg0 == 0 && fw_arg1 == 0xffffffffUL)
++		_fw_fdt_addr = phys_to_virt(fw_arg2);
++	else if ((int)fw_arg0 == -2)	/*UHI*/
++		_fw_fdt_addr = (void *)fw_arg1;
++	else if (__dtb_start != __dtb_end)
++		_fw_fdt_addr = __dtb_start;
++	else
++		panic("no dtb found!\n");
++
++	//mips_machtype = MACH_INGENIC_X1600;
++}
++
++void __init prom_free_prom_memory(void)
++{
++}
++
++const char *get_system_type(void)
++{
++	return "XBurst-Based";
++}
++
++void __init *get_fdt_addr(void)
++{
++	return _fw_fdt_addr;
++}
++#ifdef CONFIG_XBURST_MXUV2
++noinline struct xburst_cop2_state *get_current_cp2(void)
++{
++        return &(current->thread.cp2);
++}
++#endif
+diff --git a/arch/mips/xburst/common/sc-xburst.c b/arch/mips/xburst/common/sc-xburst.c
+new file mode 100644
+index 000000000..e50d9a160
+--- /dev/null
++++ b/arch/mips/xburst/common/sc-xburst.c
+@@ -0,0 +1,238 @@
++/*
++ * Copyright (C) 2006 Chris Dearman (chris@mips.com),
++ */
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/mm.h>
++
++#include <asm/mipsregs.h>
++#include <asm/bcache.h>
++#include <asm/cacheops.h>
++#include <asm/page.h>
++#include <asm/pgtable.h>
++#include <asm/mmu_context.h>
++#include <asm/r4kcache.h>
++
++/*
++ * MIPS32/MIPS64 L2 cache handling
++ */
++static unsigned long scache_size __read_mostly;
++static void (* r4k_blast_scache)(void);
++static void cache_noop(void) {}
++
++void __weak platform_early_l2_init(void)
++{
++}
++
++#if 0
++static void mips_bridge_sync_war(unsigned long addr, unsigned long size)
++{
++         __fast_iob();
++}
++#endif
++
++static void r4k_blast_scache_setup(void)
++{
++	unsigned long sc_lsize = cpu_scache_line_size();
++
++	/*default*/
++	r4k_blast_scache = blast_scache32;
++
++	if (scache_size == 0) {
++		//r4k_blast_scache = (void *)blast_inclusive_scache;
++		r4k_blast_scache = cache_noop;
++	} else if (sc_lsize == 16)
++		r4k_blast_scache = blast_scache16;
++	else if (sc_lsize == 32)
++		r4k_blast_scache = blast_scache32;
++	else if (sc_lsize == 64)
++		r4k_blast_scache = blast_scache64;
++	else if (sc_lsize == 128)
++		r4k_blast_scache = blast_scache128;
++}
++
++/*
++ * Writeback and invalidate the secondary cache before DMA.
++ */
++static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
++{
++	__sync();
++
++	if (size >= scache_size)
++		r4k_blast_scache();
++	else
++		blast_scache_range(addr, addr + size);
++
++#ifdef MIPS_BRIDGE_SYNC_WAR
++	if (MIPS_BRIDGE_SYNC_WAR)
++		__fast_iob();
++#endif
++}
++
++/*
++ * Invalidate the secondary cache before DMA.
++ */
++static void mips_sc_inv(unsigned long addr, unsigned long size)
++{
++	unsigned long lsize = cpu_scache_line_size();
++	unsigned long almask = ~(lsize - 1);
++
++	if (size >= scache_size) {
++		r4k_blast_scache();
++	}else {
++		cache_op(Hit_Writeback_Inv_SD, addr & almask);
++		cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
++		blast_inv_scache_range(addr, addr + size);
++	}
++
++#ifdef MIPS_BRIDGE_SYNC_WAR
++	if (MIPS_BRIDGE_SYNC_WAR)
++		__fast_iob();
++#endif
++}
++
++static struct bcache_ops mips_sc_ops = {
++	.bc_enable = (void *)cache_noop,
++	.bc_disable = (void *)cache_noop,
++	.bc_wback_inv = mips_sc_wback_inv,
++	.bc_inv = mips_sc_inv,
++};
++
++/*
++ * Check if the L2 cache controller is activated on a particular platform.
++ * MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
++ * cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
++ * cache being disabled.  However there is no guarantee for this to be
++ * true on all platforms.  In an act of stupidity the spec defined bits
++ * 12..15 as implementation defined so below function will eventually have
++ * to be replaced by a platform specific probe.
++ */
++static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
++{
++	unsigned int config2 = read_c0_config2();
++	unsigned int tmp;
++
++	/* Check the bypass bit (L2B) */
++	switch (current_cpu_type()) {
++	case CPU_34K:
++	case CPU_74K:
++	case CPU_1004K:
++	case CPU_1074K:
++	case CPU_INTERAPTIV:
++	case CPU_PROAPTIV:
++	case CPU_P5600:
++	case CPU_BMIPS5000:
++	case CPU_QEMU_GENERIC:
++		if (config2 & (1 << 12))
++			return 0;
++	}
++
++	tmp = (config2 >> 4) & 0x0f;
++	if (0 < tmp && tmp <= 7)
++		c->scache.linesz = 2 << tmp;
++	else
++		return 0;
++	return 1;
++}
++
++static inline int __init mips_sc_probe(void)
++{
++	struct cpuinfo_mips *c = &current_cpu_data;
++	unsigned int config1, config2;
++	unsigned int tmp;
++
++	/* Mark as not present until probe completed */
++	c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
++
++	/* Ignore anything but MIPSxx processors */
++	if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
++			MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
++			MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)))
++		return 0;
++
++	/*
++	 * Do we need some platform specific probing before
++	 * we configure L2?
++	 */
++	platform_early_l2_init();
++
++#if 0
++	switch(c->processor_id & PRID_CPU_FEATURE_MASK){
++	case PRID_CPU_JZ4775S:
++	case PRID_CPU_JZ4780:
++	case PRID_CPU_X1000:
++		if (MIPS_BRIDGE_SYNC_WAR) {
++			mips_sc_ops.bc_wback_inv = mips_bridge_sync_war;
++			return 1;
++		}
++		return 0;
++	case PRID_CPU_X1800:
++	case PRID_CPU_M200:
++		mips_sc_ops.bc_wback_inv = mips_sc_wback_inv;
++		mips_sc_ops.bc_inv = mips_sc_inv;
++		break;
++	default:
++		pr_warn("processor_id[0x%08x] s-cache is not support\n", c->processor_id);
++		break;
++	}
++#endif
++
++	/* Does this MIPS32/MIPS64 CPU have a config2 register? */
++	config1 = read_c0_config1();
++	if (!(config1 & MIPS_CONF_M))
++		return 0;
++
++	config2 = read_c0_config2();
++
++	if (!mips_sc_is_activated(c))
++		return 0;
++
++	tmp = (config2 >> 8) & 0x0f;
++	if (tmp <= 7)
++		c->scache.sets = 64 << tmp;
++	else
++		return 0;
++
++	tmp = (config2 >> 0) & 0x0f;
++	if (tmp <= 7)
++		c->scache.ways = tmp + 1;
++	else
++		return 0;
++
++	c->scache.waysize = c->scache.sets * c->scache.linesz;
++	c->scache.waybit = __ffs(c->scache.waysize);
++	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
++
++	scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
++	write_c0_ecc(0x0);
++
++	r4k_blast_scache_setup();
++	return 1;
++}
++
++static char *way_string[] = { NULL, "direct mapped", "2-way",
++	"3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
++	"9-way", "10-way", "11-way", "12-way",
++	"13-way", "14-way", "15-way", "16-way",
++};
++
++int ingenic_sc_init(void)
++{
++	struct cpuinfo_mips *c = &current_cpu_data;
++	int found = mips_sc_probe();
++
++	if (found) {
++		bcops = &mips_sc_ops;
++		bc_enable();
++		bc_prefetch_enable();
++	}
++
++	if (!scache_size)
++		return 0;
++
++	printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
++	       scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
++
++	return found;
++}
+diff --git a/arch/mips/xburst/debug/Makefile b/arch/mips/xburst/debug/Makefile
+new file mode 100644
+index 000000000..ebdd5af55
+--- /dev/null
++++ b/arch/mips/xburst/debug/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_TRACEPOINTS) += trace-exit.o
+diff --git a/arch/mips/xburst/debug/trace-exit.c b/arch/mips/xburst/debug/trace-exit.c
+new file mode 100644
+index 000000000..3fcfe2904
+--- /dev/null
++++ b/arch/mips/xburst/debug/trace-exit.c
+@@ -0,0 +1,31 @@
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <trace/events/sched.h>
++#include <linux/ftrace.h>
++
++static void
++probe_sched_process_exit(void *d,struct task_struct *p)
++{
++	struct thread_struct *thread = &p->thread;
++
++	printk("[EXIT] %s pid %d, ", p->comm, p->pid);
++	printk("exit_stat %d, exit_signal %d\n",p->exit_code,p->exit_signal);
++	printk("    badvaddr %lx, baduaddr %lx, error_code %ld\n",
++	       thread->cp0_badvaddr,thread->cp0_baduaddr,thread->error_code);
++
++	if (p->pid == 1)
++		ftrace_dump(DUMP_ALL);
++}
++
++static int init_trace(void)
++{
++	int ret = -1;
++
++	ret = register_trace_sched_process_exit(probe_sched_process_exit, NULL);
++	if (ret)
++		printk("register process exit failed.\n");
++
++	return ret;
++}
++arch_initcall(init_trace);
+diff --git a/arch/mips/xburst/soc-x1000/Kconfig.DT b/arch/mips/xburst/soc-x1000/Kconfig.DT
+new file mode 100644
+index 000000000..3938067c6
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1000/Kconfig.DT
+@@ -0,0 +1,9 @@
++choice
++	prompt "device tree select for X1000 boards"
++	default DT_X1000_MODULE
++	depends on SOC_X1000
++
++config DT_X1000_MODULE
++	bool "x1000 module base"
++
++endchoice
+diff --git a/arch/mips/xburst/soc-x1000/Makefile b/arch/mips/xburst/soc-x1000/Makefile
+new file mode 100644
+index 000000000..26cd0a5f7
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1000/Makefile
+@@ -0,0 +1,5 @@
++obj-y += setup.o
++obj-y += socid.o
++obj-y += regs_save_restore.o
++obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
++obj-$(CONFIG_PM) += pm.o
+diff --git a/arch/mips/xburst/soc-x1000/early_printk.c b/arch/mips/xburst/soc-x1000/early_printk.c
+new file mode 100644
+index 000000000..5d745d7c9
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1000/early_printk.c
+@@ -0,0 +1,76 @@
++/*
++ * INGENIC SOC serial routines for early_printk.
++ *
++ * Copyright (C) 2006 Ingenic Semiconductor Inc.
++ *
++ */
++#include <linux/moduleparam.h>
++#include <linux/serial_reg.h>
++#include <asm/setup.h>
++#include <asm/io.h>
++#include <soc/base.h>
++
++#define UART_OFF	(0x1000)
++
++static void check_uart(char c);
++
++static volatile u32 *uart_base;
++typedef void (*putchar_f_t)(char);
++
++static putchar_f_t putchar_f = check_uart;
++
++static void putchar(char ch)
++{
++	int timeout = 10000;
++	volatile u32 *base = uart_base;
++
++	/* Wait for fifo to shift out some bytes */
++	while ((base[UART_LSR] & (UART_LSR_THRE | UART_LSR_TEMT))
++	       != (UART_LSR_THRE | UART_LSR_TEMT) && timeout--)
++		;
++	base[UART_TX] = (u8)ch;
++}
++
++static void putchar_dummy(char ch)
++{
++	return;
++}
++
++#define UART_SPR (0x1C/4)
++
++static void check_uart(char c)
++{
++	/* We Couldn't use ioremap() here */
++	volatile u32 *base = (volatile u32*)CKSEG1ADDR(UART0_IOBASE);
++	int i;
++	for(i=0; i < 3; i++) {
++		if(base[UART_SPR] == 0xa9)
++			break;
++		base += (UART_OFF/sizeof(u32));
++	}
++
++	if(i < 3) {
++		uart_base = base;
++		putchar_f = putchar;
++		putchar_f(c);
++	} else {
++		putchar_f = putchar_dummy;
++	}
++}
++
++/* used by early printk */
++void prom_putchar(char c)
++{
++	putchar_f(c);
++}
++
++static int __init early_parse_console(char *p)
++{
++	unsigned char *param = "null";
++
++	if(strstr(p, param)){
++		putchar_f = putchar_dummy;
++	}
++	return 0;
++}
++early_param("console", early_parse_console);
+diff --git a/arch/mips/xburst/soc-x1000/include/cpu-feature-overrides.h b/arch/mips/xburst/soc-x1000/include/cpu-feature-overrides.h
+new file mode 100644
+index 000000000..88b84f5b5
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1000/include/cpu-feature-overrides.h
+@@ -0,0 +1,60 @@
++/*
++ *  Copyright (C) 2008 Ingenic Semiconductor Inc.
++ *
++ *  Author: <zpzhong@ingenic.cn>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_INGENIC_CPU_FEATURE_OVERRIDES_H__
++#define __ASM_MACH_INGENIC_CPU_FEATURE_OVERRIDES_H__
++
++#define cpu_dcache_size()       (16 * 1024)
++#define cpu_dcache_ways()       4
++#define cpu_dcache_line_size()  32
++#define cpu_icache_size()       (16 * 1024)
++#define cpu_icache_ways()       4
++#define cpu_icache_line_size()  32
++#define cpu_has_tlb                     1
++#define cpu_has_4kex                    1
++#define cpu_has_3k_cache                0
++#define cpu_has_4k_cache                1
++#define cpu_has_tx39_cache              0
++#define cpu_has_fpu                     1
++#define cpu_has_32fpr                   1
++#define cpu_has_counter                 0
++#define cpu_has_watch                   1
++#define cpu_has_divec                   1
++#define cpu_has_vce                     0
++#define cpu_has_cache_cdex_p            0
++#define cpu_has_cache_cdex_s            0
++#define cpu_has_prefetch                1
++#define cpu_has_mcheck                  1
++#define cpu_has_ejtag                   1
++#define cpu_has_llsc                    1
++#define cpu_has_mips16                  0
++#define cpu_has_mdmx                    0
++#define cpu_has_mips3d                  0
++#define cpu_has_smartmips               0
++#define cpu_has_vtag_icache             0
++#define cpu_has_dc_aliases              0
++#define cpu_has_ic_fills_f_dc           0
++#define cpu_has_pindexed_dcache         0
++#define cpu_icache_snoops_remote_store  0
++#define cpu_has_mips32r1                1
++#define cpu_has_mips32r2                1
++#define cpu_has_mips64r1                0
++#define cpu_has_mips64r2                0
++#define cpu_has_dsp                     0
++#define cpu_has_mipsmt                  0
++#define cpu_has_userlocal               0
++#define cpu_has_nofpuex                 0
++#define cpu_has_64bits                  0
++#define cpu_has_64bit_zero_reg          0
++#define cpu_has_vint                    0
++#define cpu_has_veic                    0
++#define cpu_has_inclusive_pcaches       0
++
++#endif
+diff --git a/arch/mips/xburst/soc-x1000/include/irq.h b/arch/mips/xburst/soc-x1000/include/irq.h
+new file mode 100644
+index 000000000..a3ce931ce
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1000/include/irq.h
+@@ -0,0 +1,30 @@
++/*
++ *  Copyright (C) 2010 Ingenic Semiconductor Inc.
++ *
++ *  Author: <zpzhong@ingenic.cn>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_INGENIC_IRQ_H__
++#define __ASM_MACH_INGENIC_IRQ_H__
++
++/* IRQ for MIPS CPU */
++#define MIPS_CPU_IRQ_BASE 		0
++#define MIPS_CPU_IRQ(x)			(MIPS_CPU_IRQ_BASE + (x))
++
++#define XBURST_INT			MIPS_CPU_IRQ(2)
++#define XBURST_SYS_OST			MIPS_CPU_IRQ(3)
++
++#define MIPS_CPU_IRQS			(MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
++#define XBURST_SOC_IRQ_BASE		MIPS_CPU_IRQS
++
++#define INTC_CHIP_NUM	2
++
++#ifndef NR_IRQS
++#define NR_IRQS		(200)
++#endif
++
++#endif
+diff --git a/arch/mips/xburst/soc-x1000/include/soc/base.h b/arch/mips/xburst/soc-x1000/include/soc/base.h
+new file mode 100644
+index 000000000..52a6ca30b
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1000/include/soc/base.h
+@@ -0,0 +1,90 @@
++
++#ifndef __INGENIC_SOC_SOC_H__
++#define __INGENIC_SOC_SOC_H__
++
++/*
++ * Define the module base addresses
++ */
++
++/* AHB0 BUS Devices Base */
++#define HARB0_IOBASE	0x13000000
++#define DDRC1_IOBASE	0x13010000
++#define DDRC_IOBASE	0x13020000
++#define X2D_IOBASE	0x13030000
++#define GPU_IOBASE	0x13040000
++#define LCDC_IOBASE	0x13050000
++#define CIM_IOBASE	0x13060000
++#define COMPRESS_IOBASE	0x13070000
++#define IPU0_IOBASE	0x13080000
++#define GPVLC_IOBASE	0x13090000
++#define IPU1_IOBASE	0x130b0000
++#define CIM1_IOBASE	0x130e0000
++#define MONITOR_IOBASE	0x130f0000
++#define EPDC_IOBASE	0x130c0000
++#define EPDCE_IOBASE	0x130d0000
++
++/* AHB1 BUS Devices Base */
++#define SCH_IOBASE	0x13200000
++#define	VDMA_IOBASE	0x13210000
++#define	EFE_IOBASE	0x13240000
++#define	MCE_IOBASE	0x13250000
++#define	DBLK_IOBASE	0x13270000
++#define	VMAU_IOBASE	0x13280000
++#define	SDE_IOBASE	0x13290000
++#define	AUX_IOBASE	0x132a0000
++#define	TCSM_IOBASE	0x132c0000
++#define	JPGC_IOBASE	0x132e0000
++#define	SRAM_IOBASE	0x132f0000
++
++/* AHB2 BUS Devices Base */
++#define HARB2_IOBASE	0x13400000
++#define NEMC_IOBASE	0x13410000
++#define PDMA_IOBASE	0x13420000
++#define SFC_IOBASE	0x13440000
++#define MSC0_IOBASE	0x13450000
++#define MSC1_IOBASE	0x13460000
++#define MSC2_IOBASE	0x13470000
++#define GPS_IOBASE	0x13480000
++#define EHCI_IOBASE	0x13490000
++#define OHCI_IOBASE	0x134a0000
++#define ETHC_IOBASE	0x134b0000
++#define BCH_IOBASE	0x134d0000
++#define TSSI0_IOBASE	0x134e0000
++#define TSSI1_IOBASE	0x134f0000
++#define OTG_IOBASE	0x13500000
++#define EFUSE_IOBASE	0x13540000
++#define SECURITY_IOBASE	0x13430000
++
++
++#define	OST_IOBASE	0x12000000
++#define	HDMI_IOBASE	0x10180000
++
++/* APB BUS Devices Base */
++#define	CPM_IOBASE	0x10000000
++#define	INTC_IOBASE	0x10001000
++#define	TCU_IOBASE	0x10002000
++#define	RTC_IOBASE	0x10003000
++#define	GPIO_IOBASE	0x10010000
++#define	AIC_IOBASE	0x10020000
++#define	DMIC_IOBASE	0x10021000
++#define	SPDIF0_IOBASE   0x10020080
++#define	UART0_IOBASE	0x10030000
++#define	UART1_IOBASE	0x10031000
++#define	UART2_IOBASE	0x10032000
++#define	UART3_IOBASE	0x10033000
++#define	SSC_IOBASE	0x10040000
++#define	SSI0_IOBASE	0x10043000
++#define	SSI1_IOBASE	0x10044000
++#define	I2C0_IOBASE	0x10050000
++#define	I2C1_IOBASE	0x10051000
++#define	I2C2_IOBASE	0x10052000
++#define	KMC_IOBASE	0x10060000
++#define	DES_IOBASE	0x10061000
++#define	SADC_IOBASE	0x10070000
++#define	PCM_IOBASE	0x10071000
++#define	OWI_IOBASE	0x10072000
++#define	WDT_IOBASE	0x10002000
++
++#define AUX_IOBASE	0x132a0000
++#define DDRC_BASE       0xb34f0000
++#endif
+diff --git a/arch/mips/xburst/soc-x1000/include/soc/cache.h b/arch/mips/xburst/soc-x1000/include/soc/cache.h
+new file mode 100644
+index 000000000..393ad6861
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1000/include/soc/cache.h
+@@ -0,0 +1,116 @@
++#ifndef __CHIP_CACHE_H__
++#define __CHIP_CACHE_H__
++
++#include <asm/cacheops.h>
++
++
++#define cache_prefetch(label,size)							\
++	do{														\
++		unsigned long addr,end;								\
++		/* Prefetch codes from label */						\
++		addr = (unsigned long)(&&label) & ~(32 - 1);		\
++		end = (unsigned long)(&&label + size) & ~(32 - 1);	\
++		end += 32;											\
++		for (; addr < end; addr += 32) {					\
++			__asm__ volatile (								\
++				".set mips32\n\t"							\
++				" cache %0, 0(%1)\n\t"						\
++				".set mips32\n\t"							\
++				:											\
++				: "I" (Index_Prefetch_I), "r"(addr));		\
++		}													\
++	}														\
++	while(0)
++
++#define cache_prefetch_lable(label,l2)					\
++	do{													\
++		unsigned long addr,end;							\
++		/* Prefetch codes from label */					\
++		addr = (unsigned long)(&&label) & ~(32 - 1);	\
++		end = (unsigned long)(&&l2) & ~(32 - 1);		\
++		end += 32;										\
++		for (; addr < end; addr += 32) {				\
++			__asm__ volatile (							\
++				".set mips32\n\t"						\
++				" cache %0, 0(%1)\n\t"					\
++				".set mips32\n\t"						\
++				:										\
++				: "I" (Index_Prefetch_I), "r"(addr));	\
++		}												\
++	}													\
++	while(0)
++
++#define K0BASE			KSEG0
++#define CFG_DCACHE_SIZE		16384
++#define CFG_ICACHE_SIZE		16384
++#define CFG_CACHELINE_SIZE	32
++
++static inline void __jz_flush_cache_all(void)
++{
++	register unsigned long addr;
++	/* Clear CP0 TagLo */
++	asm volatile ("mtc0 $0, $28\n\t");
++	for (addr = K0BASE; addr < (K0BASE + CFG_DCACHE_SIZE); addr += CFG_CACHELINE_SIZE) {
++		asm volatile (".set mips32\n\t"
++					  " cache %0, 0(%1)\n\t"
++					  ".set mips32\n\t"
++					  :
++					  : "I" (Index_Writeback_Inv_D), "r"(addr));
++	}
++
++	for (addr = K0BASE; addr < (K0BASE + CFG_ICACHE_SIZE); addr += CFG_CACHELINE_SIZE) {
++		asm volatile (".set mips32\n\t"
++					  " cache %0, 0(%1)\n\t"
++					  ".set mips32\n\t"
++					  :
++					  : "I" (Index_Store_Tag_I), "r"(addr));
++	}
++	/* invalidate BTB */
++	asm volatile (
++		".set mips32\n\t"
++		" mfc0 $26, $16, 7\n\t"
++		" nop\n\t"
++		" ori $26, 2\n\t"
++		" mtc0 $26, $16, 7\n\t"
++		" nop\n\t"
++		".set mips32\n\t"
++		);
++	asm volatile ("sync\n\t"
++				  "lw $0,0(%0)"
++				  ::"r" (0xa0000000));
++
++}
++
++static inline void __jz_cache_init(void)
++{
++	register unsigned long addr;
++	asm volatile ("mtc0 $0, $28\n\t"::);
++
++	for (addr = K0BASE; addr < (K0BASE + CFG_DCACHE_SIZE); addr += CFG_CACHELINE_SIZE) {
++		asm volatile (".set mips32\n\t"
++					  " cache %0, 0(%1)\n\t"
++					  ".set mips32\n\t"
++					  :
++					  : "I" (Index_Store_Tag_D), "r"(addr));
++	}
++	for (addr = K0BASE; addr < (K0BASE + CFG_ICACHE_SIZE); addr += CFG_CACHELINE_SIZE) {
++		asm volatile (".set mips32\n\t"
++					  " cache %0, 0(%1)\n\t"
++					  ".set mips32\n\t"
++					  :
++					  : "I" (Index_Store_Tag_I), "r"(addr));
++	}
++	/* invalidate BTB */
++	asm volatile (  ".set mips32\n\t"
++					" mfc0 $26, $16, 7\n\t"
++					" nop\n\t"
++					" ori $26, 2\n\t"
++					" mtc0 $26, $16, 7\n\t"
++					" nop\n\t"
++					"nop\n\t"
++					".set mips32\n\t"
++		);
++}
++
++
++#endif /* __CHIP_CACHE_H__ */
+diff --git a/arch/mips/xburst/soc-x1000/include/soc/cpm.h b/arch/mips/xburst/soc-x1000/include/soc/cpm.h
+new file mode 100644
+index 000000000..bc6d0695b
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1000/include/soc/cpm.h
+@@ -0,0 +1,159 @@
++/*
++ * SOC CPM register definition.
++ *
++ * CPM (Clock reset and Power control Management)
++ *
++ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.
++ */
++
++#ifndef __SOC_CPM_H__
++#define __SOC_CPM_H__
++
++#define CPM_CPCCR	(0x00)
++#define CPM_CPCSR	(0xd4)
++
++#define CPM_DDRCDR	(0x2c)
++#define CPM_I2SCDR	(0x60)
++#define CPM_I2SCDR1	(0x70)
++#define CPM_LPCDR	(0x64)
++#define CPM_MSC0CDR	(0x68)
++#define CPM_MSC1CDR	(0xa4)
++#define CPM_USBCDR	(0x50)
++#define CPM_MACCDR	(0x54)
++#define CPM_SFCCDR	(0x74)
++#define CPM_CIMCDR	(0x7c)
++#define CPM_PCMCDR	(0x84)
++#define CPM_PCMCDR1	(0xe0)
++#define CPM_MPHYC	(0xe8)
++
++#define CPM_INTR	(0xb0)
++#define CPM_INTRE	(0xb4)
++#define CPM_DRCG	(0xd0)
++#define CPM_CPSPPR	(0x38)
++#define CPM_CPPSR	(0x34)
++
++#define CPM_USBPCR	(0x3c)
++#define CPM_USBRDT	(0x40)
++#define CPM_USBVBFIL	(0x44)
++#define CPM_USBPCR1	(0x48)
++
++#define CPM_CPAPCR	(0x10)
++#define CPM_CPMPCR	(0x14)
++
++#define CPM_LCR		(0x04)
++#define CPM_PSWC0ST     (0x90)
++#define CPM_PSWC1ST     (0x94)
++#define CPM_PSWC2ST     (0x98)
++#define CPM_PSWC3ST     (0x9c)
++#define CPM_CLKGR	(0x20)
++#define CPM_MESTSEL	(0xec)
++#define CPM_SRBC	(0xc4)
++#define CPM_ERNG	(0xd8)
++#define CPM_RNG	        (0xdc)
++#define CPM_SLBC	(0xc8)
++#define CPM_SLPC	(0xcc)
++#define CPM_OPCR	(0x24)
++#define CPM_RSR		(0x08)
++
++#define LCR_LPM_MASK		(0x3)
++#define LCR_LPM_SLEEP		(0x1)
++
++#ifndef BIT
++#define BIT(nr)  (1UL << nr)
++#endif
++
++/*USB Parameter Control Register*/
++#define USBPCR_USB_MODE                 BIT(31)
++#define USBPCR_AVLD_REG                 BIT(30)
++#define USBPCR_IDPULLUP_MASK_BIT        28
++#define USBPCR_IDPULLUP_MASK_MSK                (0x3 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_IDPULLUP_OTG                             (0x0 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_IDPULLUP_ALWAYS_SUSPEND  (0x1 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_IDPULLUP_ALWAYS                  (0x2 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_INCR_MASK                BIT(27)
++#define USBPCR_TXRISETUNE               BIT(26)         /*0*/
++#define USBPCR_COMMONONN                BIT(25)
++#define USBPCR_VBUSVLDEXT               BIT(24)
++#define USBPCR_VBUSVLDEXTSEL    BIT(23)
++#define USBPCR_POR_BIT                  22
++#define USBPCR_POR                              BIT(USBPCR_POR_BIT)
++#define USBPCR_SIDDQ                    BIT(21)
++#define USBPCR_OTG_DISABLE              BIT(20)
++#define USBPCR_COMPDISTUNE_BIT  17
++#define USBPCR_COMPDISTUNE_MSK  (0x7 << USBPCR_COMPDISTUNE_BIT)
++#define USBPCR_COMPDISTUNE(x)   (((x) << USBPCR_COMPDISTUNE_BIT) & USBPCR_COMPDISTUNE_MSK)  /*4*/
++#define USBPCR_OTGTUNE_BIT              14
++#define USBPCR_OTGTUNE_MSK              (0x7 << USBPCR_OTGTUNE_BIT)
++#define USBPCR_OTGTUNE(x)               (((x) << USBPCR_OTGTUNE_BIT) & USBPCR_OTGTUNE_MSK)                      /*4*/
++#define USBPCR_SQRXTUNE_BIT             11
++#define USBPCR_SQRXTUNE_MSK             (0x7 << USBPCR_SQRXTUNE_BIT)
++#define USBPCR_SQRXTUNE(x)              (((x) << USBPCR_SQRXTUNE_BIT) & USBPCR_SQRXTUNE_MSK)            /*3*/
++#define USBPCR_TXFSLSTUNE_BIT   7
++#define USBPCR_TXFSLSTUNE_MSK   (0xf << USBPCR_TXFSLSTUNE_BIT)
++#define USBPCR_TXFSLSTUNE(x)    (((x) << USBPCR_TXFSLSTUNE_BIT) & USBPCR_TXFSLSTUNE_MSK)        /*2*/
++#define USBPCR_TXPREEMPHTUNE    BIT(6)                                          /*0*/
++#define USBPCR_TXHSXVTUNE_BIT   4
++#define USBPCR_TXHSXVTUNE_MSK   (0x3 << USBPCR_TXHSXVTUNE_BIT)
++#define USBPCR_TXHSXVTUNE(x)    (((x) << USBPCR_TXHSXVTUNE_BIT) & USBPCR_TXHSXVTUNE_MSK)        /*3*/
++#define USBPCR_TXVREFTUNE_BIT   0
++#define USBPCR_TXVREFTUNE_MSK   (0xf << USBPCR_TXVREFTUNE_BIT)
++#define USBPCR_TXVREFTUNE(x)    (((x) << USBPCR_TXVREFTUNE_BIT) & USBPCR_TXVREFTUNE_MSK)    /*4*/
++
++/*USB Reset Detect Timer Register*/
++#define USBRDT_HB_MASK                  BIT(26)
++#define USBRDT_VBFIL_LD_EN              BIT(25)
++#define USBRDT_IDDIG_EN                 24
++#define USBRDT_IDDIG_REG                23
++#define USBRDT_USBRDT_MSK               (0x7fffff)
++#define USBRDT_USBRDT(x)                ((x) & USBRDT_USBRDT_MSK)
++
++/*USB VBUS Jitter Filter Register*/
++#define USBVBFIL_USBVBFIL(x)    ((x) & 0xffff)
++#define USBVBFIL_IDDIGFIL(x)    ((x) & (0xffff << 16))
++
++/*USB Parameter Control Register1*/
++#define USBPCR1_BVLD_REG                BIT(31)
++#define USBPCR1_REFCLKSEL               (0x3 << 26)
++#define USBPCR1_REFCLKDIV_MSK   (0x3 << 24)
++#define USBPCR1_REFCLKDIV(x)    (((x) & 0x3) << 24)
++#define USBPCR1_REFCLKDIV_48M   (0x2)
++#define USBPCR1_REFCLKDIV_24M   (0x1)
++#define USBPCR1_REFCLKDIV_12M   (0x0)
++#define USBPCR1_PORT_RST		BIT(21)
++#define USBPCR1_PORT1_RST		BIT(20)
++#define USBPCR1_WORD_IF_16BIT		BIT(19)
++#define USBPCR1_WORD_IF1_16BIT		BIT(18)
++#define USBPCR1_COMPDISTUNE1_BIT	15
++#define USBPCR1_COMPDISTUNE1_MSK	(0x7 << USBPCR1_COMPDISTUNE1_BIT)
++#define USBPCR1_COMPDISTUNE1(x)		(((x) << USBPCR1_COMPDISTUNE1_BIT) & USBPCR1_COMPDISTUNE1_MSK)
++#define USBPCR1_SQRXTUNE1_BIT	12
++#define USBPCR1_SQRXTUNE1_MSK	(0x7 << USBPCR1_SQRXTUNE1_BIT)
++#define USBPCR1_SQRXTUNE1(x)	(((x) << USBPCR1_SQRXTUNE1_BIT) & USBPCR1_SQRXTUNE1_MSK)            /*3*/
++#define USBPCR1_TXFSLSTUNE1_BIT	8
++#define USBPCR1_TXFSLSTUNE1_MSK	(0xf << USBPCR1_TXFSLSTUNE1_BIT)
++#define USBPCR1_TXFSLSTUNE1(x)	(((x) << USBPCR1_TXFSLSTUNE1_BIT) & USBPCR1_TXFSLSTUNE1_MSK)        /*2*/
++#define USBPCR1_TXPREEMPHTUNE1	BIT(6)                                          /*0*/
++#define USBPCR1_TXHSXVTUNE1_BIT	5
++#define USBPCR1_TXHSXVTUNE1_MSK	(0x3 << USBPCR1_TXHSXVTUNE1_BIT)
++#define USBPCR1_TXHSXVTUNE1(x)	(((x) << USBPCR1_TXHSXVTUNE1_BIT) & USBPCR1_TXHSXVTUNE1_MSK)        /*3*/
++#define USBPCR1_TXVREFTUNE1_BIT 1
++#define USBPCR1_TXVREFTUNE1_MSK	(0xf << USBPCR1_TXVREFTUNE1_BIT)
++#define USBPCR1_TXVREFTUNE1(x)	(((x) << USBPCR1_TXVREFTUNE1_BIT) & USBPCR1_TXVREFTUNE1_MSK)    /*4*/
++#define USBPCR1_TXRISETUNE1	BIT(0)
++
++/*Oscillator and Power Control Register*/
++#define OPCR_IDLE		BIT(31)
++#define OPCR_USB_SPENDN		BIT(7)
++#define OPCR_USB_SPENDN1	BIT(6)
++#define OPCR_PD			BIT(3)
++#define OPCR_ERCS		BIT(2)
++
++/*Soft Reset and Bus Control Register*/
++#define SRBC_OTG_SR		BIT(12)
++
++#define cpm_inl(off)		inl(CPM_IOBASE + (off))
++#define cpm_outl(val,off)	outl(val,CPM_IOBASE + (off))
++#define cpm_clear_bit(val,off)	do{cpm_outl((cpm_inl(off) & ~(1<<(val))),off);}while(0)
++#define cpm_set_bit(val,off)	do{cpm_outl((cpm_inl(off) |  (1<<val)),off);}while(0)
++#define cpm_test_bit(val,off)	(cpm_inl(off) & (0x1<<val))
++#endif
+diff --git a/arch/mips/xburst/soc-x1000/include/soc/ost.h b/arch/mips/xburst/soc-x1000/include/soc/ost.h
+new file mode 100644
+index 000000000..220700a0e
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1000/include/soc/ost.h
+@@ -0,0 +1,41 @@
++/*
++ * INGENIC ost register definition.
++ *
++ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.
++ */
++
++#ifndef __OST_H__
++#define __OST_H__
++
++#define OST_TCCR    (0x00)   /* OS Timer Clock Control Register*/
++#define OST_TER     (0x04)   /* OS Timer Counter Enable Register */
++#define OST_TESR    (0x34)   /* OS Timer Counter Enable Set Register */
++#define OST_TECR    (0x38)   /* OS Timer Counter Enable Clear Register */
++#define OST_TCR     (0x08)   /* OS Timer clear Register */
++#define OST_TFR     (0x0C)   /* OS Timer Flag Register */
++#define OST_TMR     (0x10)   /* OS Timer Mask Register */
++#define OST_T1DFR   (0x14)   /* OS Timer1 Data FULL Register */
++#define OST_T1CNT   (0x18)   /* OS Timer1 Counter */
++#define OST_T2CNTL  (0x20)   /* OS Timer2 Counter Lower 32 Bits */
++#define OST_T2CNTH  (0x1c)   /* OS Timer2 Counter High 32 Bits */
++#define OST_TCNT2HBUF   (0x24)   /* OS Timer2 Counter Higher 32 Bits Buffer */
++
++#define TCCRDIV_MSK1	(0x3)
++#define TCCRDIV_SFT2	(2)
++#define TCCRDIV_MSK2	(TCCRDIV_MSK1 << TCCRDIV_SFT2)
++#define TCCRDIV1(x)	({int n = 0; int d = (x); while(d) { d >>= 2; n++; }; (n-1);})
++#define TCCRDIV2(x)	(TCCRDIV1((x)) << TCCRDIV_SFT2)
++
++#define TESR_OSTEN1   (1 << 0)   /* enable the counter1 in ost */
++#define TESR_OSTEN2   (1 << 1)   /* enable the counter2 in ost */
++
++#define TCR_OSTCLR1  (1 << 0)
++#define TCR_OSTCLR2  (1 << 1)
++
++#define TMR_OSTM    (1 << 0)   /* ost comparison match interrupt mask */
++
++#define TFR_OSTM    (1 << 0)   /* Comparison match */
++
++#define ost_readl(reg)		readl_relaxed(reg)
++#define ost_writel(reg, val)	writel_relaxed(val, reg)
++#endif
+diff --git a/arch/mips/xburst/soc-x1000/include/soc/sfc.h b/arch/mips/xburst/soc-x1000/include/soc/sfc.h
+new file mode 100644
+index 000000000..42477ab48
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1000/include/soc/sfc.h
+@@ -0,0 +1,152 @@
++#ifndef __SFC_REGISTER_H
++#define __SFC_REGISTER_H
++
++/* SFC register */
++
++#define	SFC_GLB				(0x0000)
++#define	SFC_DEV_CONF			(0x0004)
++#define	SFC_DEV_STA_EXP			(0x0008)
++#define	SFC_DEV_STA_RT			(0x000c)
++#define	SFC_DEV_STA_MSK			(0x0010)
++#define	SFC_TRAN_CONF(n)		(0x0014 + (n * 4))
++#define	SFC_TRAN_LEN			(0x002c)
++#define	SFC_DEV_ADDR(n)			(0x0030 + (n * 4))
++#define	SFC_DEV_ADDR_PLUS(n)		(0x0048 + (n * 4))
++#define	SFC_MEM_ADDR			(0x0060)
++#define	SFC_TRIG			(0x0064)
++#define	SFC_SR				(0x0068)
++#define	SFC_SCR				(0x006c)
++#define	SFC_INTC			(0x0070)
++#define	SFC_FSM				(0x0074)
++#define	SFC_CGE				(0x0078)
++#define	SFC_RM_DR			(0x1000)
++
++/* For SFC_GLB */
++#define	GLB_TRAN_DIR			(1 << 13)
++#define GLB_TRAN_DIR_WRITE		(1)
++#define GLB_TRAN_DIR_READ		(0)
++#define	GLB_THRESHOLD_OFFSET		(7)
++#define GLB_THRESHOLD_MSK		(0x3f << GLB_THRESHOLD_OFFSET)
++#define GLB_OP_MODE			(1 << 6)
++#define SLAVE_MODE			(0x0)
++#define DMA_MODE			(0x1)
++#define GLB_PHASE_NUM_OFFSET		(3)
++#define GLB_PHASE_NUM_MSK		(0x7  << GLB_PHASE_NUM_OFFSET)
++#define GLB_WP_EN			(1 << 2)
++#define GLB_BURST_MD_OFFSET		(0)
++#define GLB_BURST_MD_MSK		(0x3  << GLB_BURST_MD_OFFSET)
++
++/* For SFC_DEV_CONF */
++#define	DEV_CONF_ONE_AND_HALF_CYCLE_DELAY	(3)
++#define	DEV_CONF_ONE_CYCLE_DELAY	(2)
++#define	DEV_CONF_HALF_CYCLE_DELAY	(1)
++#define	DEV_CONF_NO_DELAY	        (0)
++#define	DEV_CONF_SMP_DELAY_OFFSET	(16)
++#define	DEV_CONF_SMP_DELAY_MSK		(0x3 << DEV_CONF_SMP_DELAY_OFFSET)
++#define DEV_CONF_CMD_TYPE		(0x1 << 15)
++#define DEV_CONF_STA_TYPE_OFFSET	(13)
++#define DEV_CONF_STA_TYPE_MSK		(0x1 << DEV_CONF_STA_TYPE_OFFSET)
++#define DEV_CONF_THOLD_OFFSET		(11)
++#define	DEV_CONF_THOLD_MSK		(0x3 << DEV_CONF_THOLD_OFFSET)
++#define DEV_CONF_TSETUP_OFFSET		(9)
++#define DEV_CONF_TSETUP_MSK		(0x3 << DEV_CONF_TSETUP_OFFSET)
++#define DEV_CONF_TSH_OFFSET		(5)
++#define DEV_CONF_TSH_MSK		(0xf << DEV_CONF_TSH_OFFSET)
++#define DEV_CONF_CPHA			(0x1 << 4)
++#define DEV_CONF_CPOL			(0x1 << 3)
++#define DEV_CONF_CEDL			(0x1 << 2)
++#define DEV_CONF_HOLDDL			(0x1 << 1)
++#define DEV_CONF_WPDL			(0x1 << 0)
++
++/* For SFC_TRAN_CONF */
++#define	TRAN_CONF_TRAN_MODE_OFFSET	(29)
++#define	TRAN_CONF_TRAN_MODE_MSK		(0x7)
++#define	TRAN_CONF_ADDR_WIDTH_OFFSET	(26)
++#define	TRAN_CONF_ADDR_WIDTH_MSK	(0x7 << ADDR_WIDTH_OFFSET)
++#define TRAN_CONF_POLLEN		(1 << 25)
++#define TRAN_CONF_POLL_OFFSET		(25)
++#define TRAN_CONF_CMDEN			(1 << 24)
++#define TRAN_CONF_FMAT			(1 << 23)
++#define TRAN_CONF_FMAT_OFFSET		(23)
++#define TRAN_CONF_DMYBITS_OFFSET	(17)
++#define TRAN_CONF_DMYBITS_MSK		(0x3f << DMYBITS_OFFSET)
++#define TRAN_CONF_DATEEN		(1 << 16)
++#define TRAN_CONF_DATEEN_OFFSET		(16)
++#define	TRAN_CONF_CMD_OFFSET		(0)
++#define	TRAN_CONF_CMD_MSK		(0xffff << CMD_OFFSET)
++#define	TRAN_CONF_CMD_LEN		(1 << 15)
++
++/* For SFC_TRIG */
++#define TRIG_FLUSH			(1 << 2)
++#define TRIG_STOP			(1 << 1)
++#define TRIG_START			(1 << 0)
++
++/* For SFC_SCR */
++#define	CLR_END			(1 << 4)
++#define CLR_TREQ		(1 << 3)
++#define CLR_RREQ		(1 << 2)
++#define CLR_OVER		(1 << 1)
++#define CLR_UNDER		(1 << 0)
++
++/* For SFC_TRAN_CONFx */
++#define	TRAN_MODE_OFFSET	(29)
++#define	TRAN_MODE_MSK		(0x7 << TRAN_MODE_OFFSET)
++#define TRAN_SPI_STANDARD   (0x0)
++#define TRAN_SPI_DUAL   (0x1 )
++#define TRAN_SPI_QUAD   (0x5 )
++#define TRAN_SPI_IO_QUAD   (0x6 )
++
++
++#define	ADDR_WIDTH_OFFSET	(26)
++#define	ADDR_WIDTH_MSK		(0x7 << ADDR_WIDTH_OFFSET)
++#define POLLEN			(1 << 25)
++#define CMDEN			(1 << 24)
++#define FMAT			(1 << 23)
++#define DMYBITS_OFFSET		(17)
++#define DMYBITS_MSK		(0x3f << DMYBITS_OFFSET)
++#define DATEEN			(1 << 16)
++#define	CMD_OFFSET		(0)
++#define	CMD_MSK			(0xffff << CMD_OFFSET)
++
++#define N_MAX				6
++#define MAX_SEGS        128
++
++#define CHANNEL_0		0
++#define CHANNEL_1		1
++#define CHANNEL_2		2
++#define CHANNEL_3		3
++#define CHANNEL_4		4
++#define CHANNEL_5		5
++
++#define ENABLE			1
++#define DISABLE			0
++
++#define COM_CMD			1	// common cmd
++#define POLL_CMD		2	// the cmd will poll the status of flash,ext: read status
++
++#define DMA_OPS			1
++#define CPU_OPS			0
++
++#define TM_STD_SPI		0
++#define TM_DI_DO_SPI	1
++#define TM_DIO_SPI		2
++#define TM_FULL_DIO_SPI	3
++#define TM_QI_QO_SPI	5
++#define TM_QIO_SPI		6
++#define	TM_FULL_QIO_SPI	7
++
++
++#define DEFAULT_ADDRSIZE	3
++
++
++#define THRESHOLD		32
++
++#define SFC_NOR_RATE    110
++#define DEF_ADDR_LEN    3
++#define DEF_TCHSH       5
++#define DEF_TSLCH       5
++#define DEF_TSHSL_R     20
++#define DEF_TSHSL_W     50
++
++
++#endif
+diff --git a/arch/mips/xburst/soc-x1000/include/soc/tcsm_layout.h b/arch/mips/xburst/soc-x1000/include/soc/tcsm_layout.h
+new file mode 100644
+index 000000000..19ba6667d
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1000/include/soc/tcsm_layout.h
+@@ -0,0 +1,53 @@
++#ifndef __TCSM_LAYOUT_H__
++#define __TCSM_LAYOUT_H__
++
++/**
++ *      |-------------|
++ *      |    BANK0    |
++ *      |-------------|     <--- SLEEP_TCSM_BOOTCODE_TEXT
++ *      |             |
++ *      |             |
++ *      |             |
++ *      |             |
++ *      |             |
++ *      |             |
++ *      |             |
++ *      |-------------|
++ *      | VO DMA DESC |
++ *      |_____________|     <--- VOICE_TCSM_DMA_DESC
++ *
++ *
++ *      |-------------|
++ *      |    BANK1    |
++ *      |-------------|     <--- VOICE_TCSM_DATA_BUF
++ *      |             |
++ *      |             |
++ *      |    ...      |
++ *      |  VOICE DATA |
++ *      |    ...      |
++ *      |             |
++ *      |             |
++ *      |_____________|
++ *
++ */
++
++/*
++ * If you use the VOICE TRIGGER,
++ * and you change the VOICE_* and TCSM_BANK_LEN,
++ * while compiling wakeup module
++ */
++#define SLEEP_TCSM_SPACE           0xb3422000
++#define VOICE_TCSM_DATA_BUF	       0xb3423000
++#define TCSM_BANK_LEN              4096
++
++#define SLEEP_TCSM_BOOT_TEXT       (SLEEP_TCSM_SPACE)
++
++#define VOICE_TCSM_DMA_DESC_LEN    512
++#define SLEEP_TCSM_SPACE_END       (SLEEP_TCSM_SPACE + TCSM_BANK_LEN - VOICE_TCSM_DMA_DESC_LEN)
++#define VOICE_TCSM_DMA_DESC_ADDR   SLEEP_TCSM_SPACE_END
++
++#define SLEEP_TCSM_CPU_RESMUE_SP   SLEEP_TCSM_SPACE_END - 4
++
++#define VOICE_TCSM_DATA_BUF_SIZE   TCSM_BANK_LEN
++
++#endif	/*  __TCSM_LAYOUT_H__ */
+diff --git a/arch/mips/xburst/soc-x1000/include/soc/tcu.h b/arch/mips/xburst/soc-x1000/include/soc/tcu.h
+new file mode 100644
+index 000000000..a8982aae7
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1000/include/soc/tcu.h
+@@ -0,0 +1,37 @@
++#ifndef __TCU_H__
++#define	__TCU_H__
++
++#define WDT_TDR			(0x00)  /* rw, 32, 0x???????? */
++#define WDT_TCER		(0x04)  /* rw, 32, 0x???????? */
++#define WDT_TCNT		(0x08)  /* rw, 32, 0x???????? */
++#define WDT_TCSR		(0x0c)  /* rw, 32, 0x???????? */
++
++#define TCU_TSTR		(0xF0)  /* Timer Status Register,Only Used In Tcu2 Mode */
++#define TCU_TSTSR		(0xF4)  /* Timer Status Set Register */
++#define TCU_TSTCR		(0xF8)  /* Timer Status Clear Register */
++#define TCU_TSR			(0x1C)  /* Timer Stop Register */
++#define TCU_TSSR		(0x2C)  /* Timer Stop Set Register */
++#define TCU_TSCR		(0x3C)  /* Timer Stop Clear Register */
++#define TCU_TER			(0x10)  /* Timer Counter Enable Register */
++#define TCU_TESR		(0x14)  /* Timer Counter Enable Set Register */
++#define TCU_TECR		(0x18)  /* Timer Counter Enable Clear Register */
++#define TCU_TFR			(0x20)  /* Timer Flag Register */
++#define TCU_TFSR		(0x24)  /* Timer Flag Set Register */
++#define TCU_TFCR		(0x28)  /* Timer Flag Clear Register */
++#define TCU_TMR			(0x30)  /* Timer Mask Register */
++#define TCU_TMSR		(0x34)  /* Timer Mask Set Register */
++#define TCU_TMCR		(0x38)  /* Timer Mask Clear Register */
++
++#define CH_TDFR(n)		(0x40 + (n)*0x10)		/* Timer Data Full Reg */
++#define CH_TDHR(n)		(0x44 + (n)*0x10)		/* Timer Data Half Reg */
++#define CH_TCNT(n)		(0x48 + (n)*0x10)		/* Timer Counter Reg */
++#define CH_TCSR(n)		(0x4C + (n)*0x10)		/* Timer Control Reg */
++
++#define TCSR_PWM_BYPASS	(1 << 11)		/* clear counter to 0, only used in TCU2 mode */
++#define TCSR_CNT_CLRZ	(1 << 10)		/* clear counter to 0, only used in TCU2 mode */
++#define TCSR_PWM_SD		(1 << 9)		/* shut down the pwm output only used in TCU1 mode */
++#define TCSR_PWM_HIGH	(1 << 8)		/* selects an initial output level for pwm output */
++#define TCSR_PWM_EN		(1 << 7)		/* pwm pin output enable */
++#define TCSR_PWM_IN		(1 << 6)		/* pwm pin output enable */
++
++#endif	/* __TCU_H__ */
+diff --git a/arch/mips/xburst/soc-x1000/include/war.h b/arch/mips/xburst/soc-x1000/include/war.h
+new file mode 100644
+index 000000000..fd1ef3147
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1000/include/war.h
+@@ -0,0 +1,27 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
++ */
++#ifndef __ASM_MACH_INGENIC_WAR_H__
++#define __ASM_MACH_INGENIC_WAR_H__
++
++#define R4600_V1_INDEX_ICACHEOP_WAR	0
++#define R4600_V1_HIT_CACHEOP_WAR	0
++#define R4600_V2_HIT_CACHEOP_WAR	0
++#define R5432_CP0_INTERRUPT_WAR		0
++#define BCM1250_M3_WAR			0
++#define SIBYTE_1956_WAR			0
++#define MIPS4K_ICACHE_REFILL_WAR	0
++#define MIPS_CACHE_SYNC_WAR		1
++#define MIPS_BRIDGE_SYNC_WAR            1
++#define TX49XX_ICACHE_INDEX_INV_WAR	0
++#define RM9000_CDEX_SMP_WAR		0
++#define ICACHE_REFILLS_WORKAROUND_WAR	0
++#define R10000_LLSC_WAR			0
++#define MIPS34K_MISSED_ITLB_WAR		0
++
++#endif
++
+diff --git a/arch/mips/xburst/soc-x1000/pm.c b/arch/mips/xburst/soc-x1000/pm.c
+new file mode 100644
+index 000000000..539b80ff7
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1000/pm.c
+@@ -0,0 +1,221 @@
++/*
++ * linux/arch/mips/xburst/soc-m200/common/pm_p0.c
++ *
++ *  M200 Power Management Routines
++ *  Copyright (C) 2006 - 2012 Ingenic Semiconductor Inc.
++ *
++ *  This program is free software; you can distribute it and/or modify it
++ *  under the terms of the GNU General Public License (Version 2) as
++ *  published by the Free Software Foundation.
++ *
++ *  This program is distributed in the hope it will be useful, but WITHOUT
++ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++ *  for more details.
++ *
++ *  You should have received a copy of the GNU General Public License along
++ *  with this program; if not, write to the Free Software Foundation, Inc.,
++ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/pm.h>
++#include <linux/sched.h>
++#include <linux/interrupt.h>
++#include <linux/suspend.h>
++#include <linux/proc_fs.h>
++#include <linux/syscalls.h>
++#include <linux/fs.h>
++#include <linux/sysctl.h>
++#include <linux/delay.h>
++#include <linux/syscore_ops.h>
++#include <linux/clk.h>
++#include <linux/notifier.h>
++#include <asm/cacheops.h>
++#include <asm/r4kcache.h>
++#include <asm/fpu.h>
++
++#include <soc/cache.h>
++#include <soc/base.h>
++#include <soc/cpm.h>
++#include <jz_notifier.h>
++#include <soc/tcsm_layout.h>
++
++extern long long save_goto(unsigned int);
++extern int restore_goto(void);
++
++unsigned int pm_firmware_new[] ={
++#include "core_sleep.hex"
++};
++
++void load_pm_firmware_new(unsigned int addr)
++{
++	void (*func)(unsigned int addr,unsigned int to);
++	unsigned int firmware_size = sizeof(pm_firmware_new);
++
++	if(firmware_size > TCSM_BANK_LEN * 1024)
++		printk("WARN: firmware_size %d bigger than"						\
++		       "TCSM_BANK_LEN %d\n", firmware_size, TCSM_BANK_LEN * 1024);
++
++	func = (void (*)(unsigned int,unsigned int))addr;
++	memcpy((void *)addr,pm_firmware_new,firmware_size);
++	func(addr,0);
++}
++struct sleep_param
++{
++	unsigned int  pm_core_enter;
++	unsigned char pmu_i2c_scl;           //default 0xff
++	unsigned char pmu_i2c_sda;           //default 0xff
++	unsigned char pmu_addr;               //default 0xff
++	unsigned char pmu_reg;                //default 0xff
++	unsigned char pmu_register_val;
++
++	unsigned char pmu_pin;               //default 0xff
++	unsigned char pmu_pin_func;          //default 0xff
++	unsigned char uart_id;          //default 0xff
++
++	unsigned int  prev_resume_pc;  //ddr is self-reflash default 0xffffffff
++	unsigned int  post_resume_pc;  //ddr is ok. default 0xffffffff
++	unsigned int  prev_sleep_pc;   //after flush cache. default 0xffffffff
++	unsigned int  post_sleep_pc;   //before wait. default 0xffffffff
++
++};
++struct sleep_save_register
++{
++	unsigned int lcr;
++	unsigned int opcr;
++	unsigned int clkgr;
++	unsigned int sleep_voice_enable;
++	unsigned int ddr_training_space[20];
++	suspend_state_t pm_state;
++};
++
++static struct sleep_save_register s_reg;
++struct sleep_param *sleep_param;
++
++static int soc_pm_enter(suspend_state_t state)
++{
++	unsigned int lcr,opcr, clkgr;
++
++	/**
++	   sleep code use PDMA_TCSM, so must enable pdma and nemc
++	 */
++	s_reg.clkgr = clkgr = cpm_inl(CPM_CLKGR);
++	clkgr &= ~(1 << 21);
++	cpm_outl(clkgr, CPM_CLKGR);
++
++	memcpy(&s_reg.ddr_training_space,(void*)0x80000000,sizeof(s_reg.ddr_training_space));
++	s_reg.opcr = cpm_inl(CPM_OPCR);
++	s_reg.lcr = cpm_inl(CPM_LCR);
++
++	load_pm_firmware_new(SLEEP_TCSM_SPACE);
++	sleep_param = (struct sleep_param *)SLEEP_TCSM_SPACE;
++
++	sleep_param->post_resume_pc = (unsigned int)restore_goto;
++	sleep_param->uart_id = -1;
++	/*
++	 *   set OPCR.
++	 */
++	opcr = s_reg.opcr;
++	lcr = s_reg.lcr;
++
++	opcr &= ~((1 << 25) | (1 << 22) | (0xfff << 8) | (1 << 4) | (1 << 3) | (1 << 2));
++	opcr |= (1 << 31) | (1 << 30) |  (1 << 25) | (0xfff << 8) | (1 << 4) | (1 << 3);
++	lcr &= ~3;
++
++#ifdef CONFIG_RTC_DRV_INGENIC
++	opcr &= ~((1 << 4) | (1 << 2));
++	opcr |= (1 << 2);
++#endif
++
++	if(s_reg.pm_state == PM_SUSPEND_STANDBY) {
++		opcr &= ~((1 << 31) | (1 << 30));
++	} else {
++		lcr |= LCR_LPM_SLEEP;
++	}
++	cpm_outl(opcr,CPM_OPCR);
++	cpm_outl(lcr,CPM_LCR);
++
++	lcr = cpm_inl(CPM_CLKGR);
++	lcr &= ~1; 		/* CPM_CLKGR bit0 NEMC: must not gate NEMC clock when sleeping */
++	cpm_outl(lcr,CPM_CLKGR);
++
++	printk("#####lcr:%08x\n", cpm_inl(CPM_LCR));
++	printk("#####gate:%08x\n", cpm_inl(CPM_CLKGR));
++	printk("#####opcr:%08x\n", cpm_inl(CPM_OPCR));
++	printk("#####INT_MASK0:%08x\n", *(volatile unsigned int*)(0xB0001004));
++	printk("#####INT_MASK1:%08x\n", *(volatile unsigned int*)(0xB0001024));
++	printk("#####INT_PEND0:%08x\n", *(volatile unsigned int*)(0xB0001010));
++	printk("#####INT_PEND1:%08x\n", *(volatile unsigned int*)(0xB0001030));
++
++	mb();
++	save_goto((unsigned int)sleep_param->pm_core_enter);
++	mb();
++
++	memcpy((void*)0x80000000,&s_reg.ddr_training_space,sizeof(s_reg.ddr_training_space));
++	dma_cache_wback_inv(0x80000000,sizeof(s_reg.ddr_training_space));
++	cpm_outl(s_reg.lcr,CPM_LCR);
++	cpm_outl(s_reg.opcr,CPM_OPCR);
++	cpm_outl(s_reg.clkgr, CPM_CLKGR);
++
++	return 0;
++}
++
++static int soc_valid(suspend_state_t state)
++{
++	switch (state) {
++	case PM_SUSPEND_ON:
++	case PM_SUSPEND_STANDBY:
++	case PM_SUSPEND_MEM:
++		return 1;
++
++	default:
++		return 0;
++	}
++}
++static void soc_finish(void)
++{
++	s_reg.pm_state = 0;
++}
++static int soc_begin(suspend_state_t state)
++{
++	s_reg.pm_state = state;
++	if(s_reg.pm_state == PM_SUSPEND_STANDBY) {
++		jz_notifier_call(NOTEFY_PROI_HIGH, JZ_PM_SUSPEND_STANDBY, &s_reg.pm_state);
++	}
++	return 0;
++}
++
++/*
++ * Initialize power interface
++ */
++struct platform_suspend_ops pm_ops = {
++	.valid = soc_valid,
++	.begin = soc_begin,
++	.enter = soc_pm_enter,
++	.end = soc_finish,
++};
++
++int __init soc_pm_init(void)
++{
++	volatile unsigned int lcr,opcr;
++
++	suspend_set_ops(&pm_ops);
++
++	/* init opcr and lcr for idle */
++	lcr = cpm_inl(CPM_LCR);
++	lcr &= ~(0x3);		/* LCR.SLEEP.DS=1'b0,LCR.LPM=2'b00*/
++	lcr |= 0xff << 8;	/* power stable time */
++	cpm_outl(lcr,CPM_LCR);
++
++	opcr = cpm_inl(CPM_OPCR);
++	opcr |= 0xff << 8;	/* EXCLK stable time */
++	opcr &= ~(1 << 4);	/* EXCLK oscillator is disabled in Sleep mode */
++	cpm_outl(opcr,CPM_OPCR);
++
++	/* sysfs */
++	return 0;
++}
++
++arch_initcall(soc_pm_init);
+diff --git a/arch/mips/xburst/soc-x1000/regs_save_restore.S b/arch/mips/xburst/soc-x1000/regs_save_restore.S
+new file mode 100644
+index 000000000..e4d013ccc
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1000/regs_save_restore.S
+@@ -0,0 +1,174 @@
++#include <asm/asm.h>
++#include <asm/regdef.h>
++
++#define CP0_CONTEXT	$4,0
++#define CP0_PAGEMASK	$5,0
++#define CP0_TLB_SPEC	$5,4
++#define CP0_STATUS	$12,0
++#define CP0_INTCTL	$12,1
++#define CP0_CAUSE	$13,0
++#define CP0_EBASE	$15,1
++#define CP0_CONFIG	$16,0
++#define CP0_CONFIG1	$16,1
++#define CP0_CONFIG2	$16,2
++#define CP0_CONFIG3	$16,3
++#define CP0_CONFIG7	$16,7
++#define CP0_LLADDR	$17,0
++#define PMON_CSR	$17,7
++#define PMON_HIGH	$17,4
++#define PMON_LC	$17,5
++#define PMON_RC	$17,6
++#define CP0_WATCHLo	$18,0
++#define CP0_WATCHHI	$19,0
++#define CP0_ERRCTL	$26,0
++
++	.data
++	.global _regs_stack
++_regs_stack:
++	.align 5
++	.space 128,0
++
++	.text
++	.global save_goto
++	.align 2
++	.ent save_goto,0
++	LEAF(save_goto)
++save_goto:
++	.set	push
++	.set	noreorder
++	.set	noat
++
++	la	k0, _regs_stack
++	sw	s0,0(k0)
++	sw	s1,4(k0)
++	sw	s2,8(k0)
++	sw	s3,12(k0)
++	sw	s4,16(k0)
++	sw	s5,20(k0)
++	sw	s6,24(k0)
++	sw	s7,28(k0)
++	sw	gp,32(k0)
++	sw	sp,36(k0)
++	sw	fp,40(k0)
++	sw	ra,44(k0)
++
++	mfc0	k1,CP0_PAGEMASK
++	sw	k1,48(k0)
++	mfc0	k1,CP0_TLB_SPEC
++	sw	k1,52(k0)
++	mfc0	k1,CP0_STATUS
++	sw	k1,56(k0)
++	mfc0	k1,CP0_INTCTL
++	sw	k1,60(k0)
++	mfc0	k1,CP0_CAUSE
++	sw	k1,64(k0)
++	mfc0	k1,CP0_EBASE
++	sw	k1,68(k0)
++	mfc0	k1,CP0_CONFIG
++	sw	k1,72(k0)
++	mfc0	k1,CP0_CONFIG1
++	sw	k1,76(k0)
++	mfc0	k1,CP0_CONFIG2
++	sw	k1,80(k0)
++	mfc0	k1,CP0_CONFIG3
++	sw	k1,84(k0)
++	mfc0	k1,CP0_CONFIG7
++	sw	k1,88(k0)
++	mfc0	k1,CP0_LLADDR
++	sw	k1,92(k0)
++	mfc0	k1,PMON_CSR
++	sw	k1,96(k0)
++	mfc0	k1,PMON_HIGH
++	sw	k1,100(k0)
++	mfc0	k1,PMON_LC
++	sw	k1,104(k0)
++	mfc0	k1,PMON_RC
++	sw	k1,108(k0)
++	mfc0	k1,CP0_WATCHLo
++	sw	k1,112(k0)
++	mfc0	k1,CP0_WATCHHI
++	sw	k1,116(k0)
++	mfc0	k1,CP0_ERRCTL
++	sw	k1,120(k0)
++	mfc0	k1,CP0_CONTEXT
++	sw	k1,124(k0)
++
++	jr	a0
++	nop
++
++	.set	at
++	.set	reorder
++	.set	pop
++	END(save_goto)
++	.text
++	.global restore_goto
++	.align 2
++	.ent restore_goto,0
++	LEAF(restore_goto)
++restore_goto:
++	.set	push
++	.set	noreorder
++	.set	noat
++
++	la	k0, _regs_stack
++	lw	s0,0(k0)
++	lw	s1,4(k0)
++	lw	s2,8(k0)
++	lw	s3,12(k0)
++	lw	s4,16(k0)
++	lw	s5,20(k0)
++	lw	s6,24(k0)
++	lw	s7,28(k0)
++	lw	gp,32(k0)
++	lw	sp,36(k0)
++	lw	fp,40(k0)
++	lw	ra,44(k0)
++
++	lw	k1,48(k0)
++	mtc0	k1,CP0_PAGEMASK
++	lw	k1,52(k0)
++	mtc0	k1,CP0_TLB_SPEC
++	lw	k1,56(k0)
++	mtc0	k1,CP0_STATUS
++	lw	k1,60(k0)
++	mtc0	k1,CP0_INTCTL
++	lw	k1,64(k0)
++	mtc0	k1,CP0_CAUSE
++	lw	k1,68(k0)
++	mtc0	k1,CP0_EBASE
++	lw	k1,72(k0)
++	mtc0	k1,CP0_CONFIG
++	lw	k1,76(k0)
++	mtc0	k1,CP0_CONFIG1
++	lw	k1,80(k0)
++	mtc0	k1,CP0_CONFIG2
++	lw	k1,84(k0)
++	mtc0	k1,CP0_CONFIG3
++	lw	k1,88(k0)
++	mtc0	k1,CP0_CONFIG7
++	lw	k1,92(k0)
++	mtc0	k1,CP0_LLADDR
++	lw	k1,96(k0)
++	mtc0	k1,PMON_CSR
++	lw	k1,100(k0)
++	mtc0	k1,PMON_HIGH
++	lw	k1,104(k0)
++	mtc0	k1,PMON_LC
++	lw	k1,108(k0)
++	mtc0	k1,PMON_RC
++	lw	k1,112(k0)
++	mtc0	k1,CP0_WATCHLo
++	lw	k1,116(k0)
++	mtc0	k1,CP0_WATCHHI
++	lw	k1,120(k0)
++	mtc0	k1,CP0_ERRCTL
++	lw	k1,124(k0)
++	mtc0	k1,CP0_CONTEXT
++
++	jr	ra
++	nop
++
++	.set	at
++	.set	reorder
++	.set	pop
++	END(restore_goto)
+diff --git a/arch/mips/xburst/soc-x1000/setup.c b/arch/mips/xburst/soc-x1000/setup.c
+new file mode 100644
+index 000000000..44a3b73b9
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1000/setup.c
+@@ -0,0 +1,80 @@
++/*
++ * INGENIC SOC Setup
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2006 Ingenic Semiconductor Inc.
++ */
++#include <linux/module.h>
++#include <linux/of_fdt.h>
++#include <linux/of_platform.h>
++#include <linux/irqchip.h>
++#include <linux/libfdt.h>
++#include <linux/clk-provider.h>
++#include <linux/clocksource.h>
++#include <asm/prom.h>
++#include <soc/cpm.h>
++#include <soc/base.h>
++
++
++extern void *get_fdt_addr(void);
++extern void __init soc_is_x1000e(void);
++
++void __init plat_mem_setup(void)
++{
++	void __iomem *cpm_iobase = (void __iomem *)CKSEG1ADDR(CPM_IOBASE);
++
++	/* ingenic mips cpu special */
++	__asm__ (
++		"li    $2, 0xa9000000 \n\t"
++		"mtc0  $2, $5, 4      \n\t"
++		"nop                  \n\t"
++		::"r"(2));
++
++	set_io_port_base(IO_BASE);
++	/*Not have ioport*/
++	ioport_resource.start	= 0x00000000;
++	ioport_resource.end	= 0x00000000;
++	iomem_resource.start	= 0x10000000;
++	iomem_resource.end	= 0x1fffffff;
++
++	/*x1000 cpu special*/
++	writel( 0, cpm_iobase + CPM_PSWC0ST);
++	writel(16, cpm_iobase + CPM_PSWC1ST);
++	writel(24, cpm_iobase + CPM_PSWC2ST);
++	writel( 8, cpm_iobase + CPM_PSWC3ST);
++
++	__dt_setup_arch(get_fdt_addr());
++
++	early_init_fdt_scan_reserved_mem();
++
++	soc_is_x1000e();
++
++	return;
++}
++
++void __init device_tree_init(void)
++{
++	unflatten_and_copy_device_tree();
++}
++
++static int __init plat_of_populate(void)
++{
++	of_platform_default_populate(NULL, NULL, NULL);
++	return 0;
++}
++arch_initcall(plat_of_populate);
++
++void __init plat_time_init(void)
++{
++	of_clk_init(NULL);
++
++	timer_probe();
++}
++
++void __init arch_init_irq(void) {
++
++	irqchip_init();
++}
+diff --git a/arch/mips/xburst/soc-x1000/socid.c b/arch/mips/xburst/soc-x1000/socid.c
+new file mode 100644
+index 000000000..72698e4ef
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1000/socid.c
+@@ -0,0 +1,110 @@
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/err.h>
++#include <asm/prom.h>
++#include <soc/base.h>
++
++#define CLKGATE		0x20
++#define CTRL_OFF	0x0
++#define STATUS_OFF	0x8
++#define DATA0_OFF	0xc
++
++enum socid {
++	X1000 = 0xff00,
++	X1000E = 0xff01,
++	X1500 = 0xff02,
++	X1000_NEW = 0xff08,
++	X1000E_NEW = 0xff09,
++	X1500_NEW = 0xff0a,
++};
++
++static int read_socid(void)
++{
++	void __iomem *efuse_iobase = (void __iomem *)CKSEG1ADDR(EFUSE_IOBASE);
++	void __iomem *cpm_iobase = (void __iomem *)CKSEG1ADDR(CPM_IOBASE);
++	uint32_t val = 0, timeout = 10;
++	uint32_t clkgat, clk_efuse_enable = 0;
++	int ret = 0;
++
++	clkgat = readl(cpm_iobase + CLKGATE);
++	if(clkgat & (0x1 << 1)) {
++		clk_efuse_enable = 1;
++		writel(clkgat & ~(0x1 << 1), cpm_iobase + CLKGATE);
++	}
++
++	writel(0, efuse_iobase + STATUS_OFF);
++
++	val = 0x3c << 21 | 1 << 16 | 1;
++	writel(val, efuse_iobase + CTRL_OFF);
++
++	while(!(readl(efuse_iobase + STATUS_OFF) & 1)) {
++		timeout --;
++		if(!timeout) {
++			ret = -EBUSY;
++			goto efuse_fail;
++		}
++	}
++	ret = readl(efuse_iobase + DATA0_OFF);
++efuse_fail:
++	if(clk_efuse_enable)
++		writel(clkgat, cpm_iobase + CLKGATE);
++	return ret;
++}
++
++static int __init check_socid(void) {
++
++	int socid = read_socid();
++	if (socid < 0) {
++		pr_err("socid: efuse busy !\n");
++		return -EBUSY;
++	}
++	switch(socid) {
++	case X1000:
++	case X1500:
++	case X1000E:
++	case X1000_NEW:
++	case X1000E_NEW:
++	case X1500_NEW:
++	case 0:
++		break;
++	default:
++		pr_err("socid: unknown x1000 socid !\n");
++		return -ENODEV;
++	}
++
++	return socid;
++}
++
++static void __init ddr_param_change(int ddr_size)
++{
++	int off;
++
++	off = strcspn(arcs_cmdline, "M@");
++	switch(ddr_size) {
++	case 64:
++		arcs_cmdline[off - 2] = '6';
++		arcs_cmdline[off - 1] = '4';
++		break;
++	case 256:
++		arcs_cmdline[off - 3] = '2';
++		arcs_cmdline[off - 2] = '5';
++		arcs_cmdline[off - 1] = '6';
++		break;
++	default:
++		return;
++	}
++}
++
++void __init soc_is_x1000e(void)
++{
++	int socid;
++
++	socid = check_socid();
++	if(socid == X1000E || socid == X1000E_NEW){
++		ddr_param_change(64);
++	}
++}
++
++MODULE_DESCRIPTION("x1000 socid driver special used by itself");
+diff --git a/arch/mips/xburst/soc-x1600/Kconfig.DT b/arch/mips/xburst/soc-x1600/Kconfig.DT
+new file mode 100644
+index 000000000..f05c35c30
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/Kconfig.DT
+@@ -0,0 +1,19 @@
++choice
++	prompt "device tree select for X1600 boards"
++	default DT_HALLEY6_V10
++	depends on SOC_X1600
++
++config DT_X1600_MODULE
++	bool "x1600 module base"
++
++config DT_PANDA_V10
++	bool "x1600 panda v10"
++
++config DT_HALLEY6_V10
++	bool "x1600 halley6 v10"
++
++config DT_HALLEY6_V20
++	bool "x1600 halley6 v20"
++
++endchoice
++
+diff --git a/arch/mips/xburst/soc-x1600/Makefile b/arch/mips/xburst/soc-x1600/Makefile
+new file mode 100644
+index 000000000..a25ee9e2e
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/Makefile
+@@ -0,0 +1,6 @@
++obj-y += setup.o
++obj-y += libdmmu.o
++obj-y += regs_save_restore.o
++obj-y += gpio.o
++obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
++obj-$(CONFIG_PM) += pm.o
+diff --git a/arch/mips/xburst/soc-x1600/early_printk.c b/arch/mips/xburst/soc-x1600/early_printk.c
+new file mode 100644
+index 000000000..e2d76bce2
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/early_printk.c
+@@ -0,0 +1,99 @@
++/*
++ * INGENIC SOC serial routines for early_printk.
++ *
++ * Copyright (C) 2006 Ingenic Semiconductor Inc.
++ *
++ */
++#include <linux/moduleparam.h>
++#include <linux/serial_reg.h>
++#include <asm/setup.h>
++#include <asm/io.h>
++#include <soc/base.h>
++
++#define UART_OFF	(0x1000)
++
++static void check_uart(char c);
++
++volatile u32 *uart_base;
++typedef void (*putchar_f_t)(char);
++
++static putchar_f_t putchar_f = check_uart;
++
++static void putchar(char ch)
++{
++	int timeout = 10000;
++	volatile u32 *base = uart_base;
++
++	/* Wait for fifo to shift out some bytes */
++	while ((base[UART_LSR] & (UART_LSR_THRE | UART_LSR_TEMT))
++	       != (UART_LSR_THRE | UART_LSR_TEMT) && timeout--)
++		;
++	base[UART_TX] = (u8)ch;
++}
++
++static void putchar_dummy(char ch)
++{
++	return;
++}
++
++static void check_uart(char c)
++{
++	/* We Couldn't use ioremap() here */
++	volatile u32 *base = (volatile u32*)CKSEG1ADDR(UART0_IOBASE);
++	int i;
++	for(i=0; i < 4; i++) {
++		if(base[UART_LCR])
++			break;
++		base += (UART_OFF/sizeof(u32));
++	}
++
++	if(i < 4) {
++		uart_base = base;
++		putchar_f = putchar;
++		putchar_f(c);
++	} else {
++		putchar_f = putchar_dummy;
++	}
++}
++
++/* used by early printk */
++void prom_putchar(char c)
++{
++	putchar_f(c);
++}
++
++static int __init early_parse_console(char *p)
++{
++	unsigned char *param = "null";
++
++	if(strstr(p, param)){
++		putchar_f = putchar_dummy;
++	}
++	return 0;
++}
++early_param("console", early_parse_console);
++
++#if 0
++/* for debug */
++void prom_putstr(char *s)
++{
++        while(*s) {
++                if(*s == '\n')
++                        putchar_f('\r');
++                putchar_f(*s);
++                s++;
++        }
++}
++
++static char pbuffer[4096];
++void prom_printk(const char *fmt, ...) {
++        va_list args;
++
++        va_start(args, fmt);
++        vsnprintf(pbuffer, 4096, fmt, args);
++        va_end(args);
++
++        prom_putstr(pbuffer);
++}
++#endif
++
+diff --git a/arch/mips/xburst/soc-x1600/gpio.c b/arch/mips/xburst/soc-x1600/gpio.c
+new file mode 100644
+index 000000000..b2437b9c0
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/gpio.c
+@@ -0,0 +1,130 @@
++#include <linux/kernel.h>
++#include <linux/printk.h>
++#include <linux/io.h>
++#include <soc/base.h>
++#include <soc/gpio.h>
++
++#define GPIO_PORT_OFF    0x100
++#define GPIO_SHADOW_OFF  0x700
++
++#define PXPIN       0x00   /* PIN Level Register */
++#define PXINT       0x10   /* Port Interrupt Register */
++#define PXINTS      0x14   /* Port Interrupt Set Register */
++#define PXINTC      0x18   /* Port Interrupt Clear Register */
++#define PXMSK       0x20   /* Port Interrupt Mask Reg */
++#define PXMSKS      0x24   /* Port Interrupt Mask Set Reg */
++#define PXMSKC      0x28   /* Port Interrupt Mask Clear Reg */
++#define PXPAT1      0x30   /* Port Pattern 1 Register. */
++#define PXPAT1S     0x34   /* Port Pattern 1 Set Register. */
++#define PXPAT1C     0x38   /* Port Pattern 1 Clear Register. */
++#define PXPAT0      0x40   /* Port Pattern 0 Register */
++#define PXPAT0S     0x44   /* Port Pattern 0 Set Register */
++#define PXPAT0C     0x48   /* Port Pattern 0 Clear Register */
++#define PXFLG       0x50   /* Port Flag Register */
++#define PXFLGC      0x58   /* Port Flag clear Register */
++#define PXDEG       0x70   /* Port Dual Edge Register */
++#define PXDEGS      0x74   /* Port Dual Edge Set Register */
++#define PXDEGC      0x78   /* Port Dual Edge Clear Register */
++#define PXPEN       0x80   /* Port Pull Enable Register */
++#define PXPENS      0x84   /* Port Pull Enable Set Register */
++#define PXPENC      0x88   /* Port Pull Enable Clear Register */
++
++#define PZGID2LD    0xF0   /* GPIOZ Group ID to load */
++
++#define SHADOW 4
++
++#define GPIO_FUNC_FLAG      0x0100
++#define GPIO_FUNC_OFFSET    0
++#define GPIO_FUNC_MASK      0x01ff
++
++#define GPIO_PULL_FLAG      0x8000
++#define GPIO_PULL_OFFSET    13
++#define GPIO_PULL_MASK      0xe000
++
++static const unsigned long gpiobase[] = {
++    [0] = (unsigned long)CKSEG1ADDR(GPIO_IOBASE + 0 * GPIO_PORT_OFF),
++    [1] = (unsigned long)CKSEG1ADDR(GPIO_IOBASE + 1 * GPIO_PORT_OFF),
++    [2] = (unsigned long)CKSEG1ADDR(GPIO_IOBASE + 2 * GPIO_PORT_OFF),
++    [3] = (unsigned long)CKSEG1ADDR(GPIO_IOBASE + 3 * GPIO_PORT_OFF),
++
++    [SHADOW] = (unsigned long)CKSEG1ADDR(GPIO_IOBASE + GPIO_SHADOW_OFF),
++};
++
++#define GPIO_ADDR(port, reg)            ((volatile unsigned long *)(gpiobase[port] + reg))
++
++static inline void gpio_write(int port, unsigned int reg, int val)
++{
++    *GPIO_ADDR(port, reg) = val;
++}
++
++static inline unsigned int gpio_read(int port, unsigned int reg)
++{
++    return *GPIO_ADDR(port, reg);
++}
++
++static void hal_gpio_port_set_func(enum gpio_port port, unsigned int pins, enum gpio_function func)
++{
++    /* func option */
++    if (func & GPIO_FUNC_FLAG) {
++        /* No Shadows registers for EDG, set registers directly */
++        if (func & 0x10)
++            gpio_write(port, PXDEGS, pins);
++        else
++            gpio_write(port, PXDEGC, pins);
++
++
++        if (func & 0x8)
++            gpio_write(SHADOW, PXINTS, pins);
++        else
++            gpio_write(SHADOW, PXINTC, pins);
++
++        if (func & 0x4)
++            gpio_write(SHADOW, PXMSKS, pins);
++        else
++            gpio_write(SHADOW, PXMSKC, pins);
++
++        if (func & 0x2)
++            gpio_write(SHADOW, PXPAT1S, pins);
++        else
++            gpio_write(SHADOW, PXPAT1C, pins);
++
++        if (func & 0x1)
++            gpio_write(SHADOW, PXPAT0S, pins);
++        else
++            gpio_write(SHADOW, PXPAT0C, pins);
++
++        /* configure PzGID2LD to specify which port group to load */
++        gpio_write(SHADOW, PZGID2LD, port);
++    }
++
++    /* pull option */
++    if (func & GPIO_PULL_FLAG) {
++        if (func & 0x2000)
++            gpio_write(port, PXPENS, pins);
++        else
++            gpio_write(port, PXPENC, pins);
++    }
++
++}
++
++unsigned long ingenic_pinctrl_lock(int port);
++void ingenic_pinctrl_unlock(int port, unsigned long flags);
++
++int jzgpio_set_func(int port, enum gpio_function func, unsigned long pins)
++{
++    unsigned long flags;
++
++    if (port < 0 || port > 3) {
++        printk(KERN_ERR "gpio: invalid gpio port for x1600: %d\n", port);
++        return -EINVAL;
++    }
++
++    flags = ingenic_pinctrl_lock(port);
++
++    hal_gpio_port_set_func(port, pins, func);
++
++    ingenic_pinctrl_unlock(port, flags);
++
++    return 0;
++}
++EXPORT_SYMBOL(jzgpio_set_func);
+diff --git a/arch/mips/xburst/soc-x1600/include/cpu-feature-overrides.h b/arch/mips/xburst/soc-x1600/include/cpu-feature-overrides.h
+new file mode 100644
+index 000000000..b33cfa6b7
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/include/cpu-feature-overrides.h
+@@ -0,0 +1,61 @@
++/*
++ *  Copyright (C) 2008 Ingenic Semiconductor Inc.
++ *
++ *  Author: <zpzhong@ingenic.cn>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_INGENIC_CPU_FEATURE_OVERRIDES_H__
++#define __ASM_MACH_INGENIC_CPU_FEATURE_OVERRIDES_H__
++
++#define cpu_dcache_size()       (16 * 1024)
++#define cpu_dcache_ways()       8
++#define cpu_dcache_line_size()  32
++#define cpu_icache_size()       (16 * 1024)
++#define cpu_icache_ways()       8
++#define cpu_icache_line_size()  32
++#define cpu_has_tlb                     1
++#define cpu_has_4kex                    1
++#define cpu_has_3k_cache                0
++#define cpu_has_4k_cache                1
++#define cpu_has_tx39_cache              0
++#define cpu_has_fpu                     1
++#define cpu_has_32fpr                   1
++#define cpu_has_counter                 0
++#define cpu_has_watch                   1
++#define cpu_has_divec                   1
++#define cpu_has_vce                     0
++#define cpu_has_cache_cdex_p            0
++#define cpu_has_cache_cdex_s            0
++#define cpu_has_prefetch                1
++#define cpu_has_mcheck                  1
++#define cpu_has_ejtag                   1
++#define cpu_has_llsc                    1
++#define cpu_has_mips16                  0
++#define cpu_has_mdmx                    0
++#define cpu_has_mips3d                  0
++#define cpu_has_smartmips               0
++#define cpu_has_vtag_icache             0
++#define cpu_has_dc_aliases              0
++#define cpu_has_ic_fills_f_dc           0
++#define cpu_has_pindexed_dcache         0
++#define cpu_icache_snoops_remote_store  0
++#define cpu_has_mips32r1                0
++#define cpu_has_mips32r2                1
++#define cpu_has_mips64r1                0
++#define cpu_has_mips64r2                0
++#define cpu_has_dsp                     0
++#define cpu_has_mipsmt                  0
++#define cpu_has_userlocal               0
++#define cpu_has_nofpuex                 0
++#define cpu_has_64bits                  0
++#define cpu_has_64bit_zero_reg          0
++#define cpu_has_vint                    0
++#define cpu_has_veic                    0
++#define cpu_has_inclusive_pcaches       0
++#define kernel_uses_smartmips_rixi      1
++#define cpu_has_mxu                     0
++#endif
+diff --git a/arch/mips/xburst/soc-x1600/include/irq.h b/arch/mips/xburst/soc-x1600/include/irq.h
+new file mode 100644
+index 000000000..c89c83538
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/include/irq.h
+@@ -0,0 +1,35 @@
++/*
++ *  Copyright (C) 2010 Ingenic Semiconductor Inc.
++ *
++ *  Author: <zpzhong@ingenic.cn>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_INGENIC_IRQ_H__
++#define __ASM_MACH_INGENIC_IRQ_H__
++
++#include <dt-bindings/interrupt-controller/mips-irq.h>
++
++/* IRQ for MIPS CPU */
++//#define MIPS_CPU_IRQ_BASE		0
++#define MIPS_CPU_IRQ(x)			(MIPS_CPU_IRQ_BASE + (x))
++
++#define XBURST_INT			MIPS_CPU_IRQ(2)
++#define XBURST_SYS_OST			MIPS_CPU_IRQ(3)
++
++#define MIPS_CPU_IRQS			(MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
++#define XBURST_SOC_IRQ_BASE		MIPS_CPU_IRQS
++
++#define INTC_CHIP_NUM			2
++
++#define TCU_NR_IRQS	(8)
++
++#ifndef NR_IRQS
++#define NR_IRQS				(200)
++#endif
++
++#endif
++
+diff --git a/arch/mips/xburst/soc-x1600/include/libdmmu.h b/arch/mips/xburst/soc-x1600/include/libdmmu.h
+new file mode 100644
+index 000000000..6e0fbdb42
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/include/libdmmu.h
+@@ -0,0 +1,30 @@
++#ifndef _LIBDMMU_
++#define _LIBDMMU_
++
++#include <linux/device.h>
++
++
++struct dmmu_mm_ops {
++	int (*mm_release)(void *data);
++};
++
++struct dmmu_mm_notifier {
++
++	struct device *dev;
++	void *data;
++	struct list_head list;
++
++	struct dmmu_mm_ops *ops;
++};
++
++int dmmu_register_mm_notifier(struct dmmu_mm_notifier *dmn);
++
++unsigned long dmmu_map(struct device *dev,unsigned long vaddr,unsigned long len);
++int dmmu_flush_cache(unsigned long vaddr, unsigned long len);
++int dmmu_unmap(struct device *dev,unsigned long vaddr, int len);
++int dmmu_unmap_all(struct device *dev);
++void dmmu_dump_vaddr(unsigned long vaddr);
++int dmmu_memory_smash(unsigned long vaddr, int smash_mode);
++int dmmu_dump_map(unsigned long vaddr);
++
++#endif
+diff --git a/arch/mips/xburst/soc-x1600/include/soc/base.h b/arch/mips/xburst/soc-x1600/include/soc/base.h
+new file mode 100644
+index 000000000..ae3b9c28c
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/include/soc/base.h
+@@ -0,0 +1,66 @@
++
++#ifndef __JZSOC_SOC_DEV_H__
++#define __JZSOC_SOC_DEV_H__
++
++/*
++ * Define the module base addresses
++ */
++
++/* AHB0 BUS Devices Base */
++#define HARB0_IOBASE	0x13000000 /* 64KB, AHB Bus Aribtier */
++#define DDR_PHY_IOBASE	0x13011000 /* 4KB, DDR PHY */
++#define DDRC_H0_IOBASE	0x13012000 /* 4KB, DDR Controller Registers@ASHB0 */
++#define DPU_IOBASE	0x13050000 /* 64KB, LCD Controller */
++#define CIM_IOBASE	0x13060000 /* 64KB, Camera Interface Module */
++
++
++/* AHB2 Bus Devices Base */
++#define HARB2_IOBASE	0x13400000 /* 64KB, AHB Bus Arbiter */
++#define NEMC_IOBASE	0x13410000 /* 64KB, External Normal Memory/Boot ROM/OTP Controller */
++#define PDMA_IOBASE	0x13420000 /* 64KB, Programmable DMA Controller */
++#define AES_IOBASE	0x13430000 /* 64KB, AES */
++#define SFC_IOBASE	0x13440000 /* 64KB, SPI Flash Controller */
++#define MSC0_IOBASE	0x13450000 /* 64KB, MMC SD Controller0 */
++#define MSC1_IOBASE	0x13460000 /* 64KB, MMC SD Controller1 */
++#define HASH_IOBASE	0x13470000 /* 64KB, HASH */
++#define MAC_IOBASE	0x134b0000 /* 64KB, GMAC/MAC */
++#define PWM_IOBASE	0x134c0000 /* 64KB, PWM */
++#define OTG_IOBASE	0x13500000 /* 256KB, OTG2.0 Controller */
++#define EFUSE_IOBASE	0x13540000 /* 64KB, EFUSE */
++#define CDBUS_IOBASE	0x13550000 /* 64KB, CDBUS */
++#define CAN0_IOBASE	0x13560000 /* 64KB, CAN0 */
++#define CAN1_IOBASE	0x13570000 /* 64KB, CAN0 */
++#define INTC_IOBASE	0x10001000 /* Interrupt Controller */
++
++
++/* APB BUS Devices Base */
++#define CPM_IOBASE	0x10000000 /* 4KB, Clocks and Power Manager */
++#define TCU_IOBASE	0x10002000 /* 4KB, Timer/Count Unit,OperatingSystemTimer,Watchdog Timer */
++#define WDT_IOBASE	TCU_IOBASE /* 4KB, Timer/Count Unit,OperatingSystemTimer,Watchdog Timer */
++#define RTC_IOBASE	0x10003000 /* 4KB, Real-Time Clock */
++#define GPIO_IOBASE	0x10010000 /* 4KB, General-Purpose I/O */
++#define	UART0_IOBASE	0x10030000 /* 4KB, UART0 Controller */
++#define	UART1_IOBASE	0x10031000 /* 4KB, UART1 Controller */
++#define	UART2_IOBASE	0x10032000 /* 4KB, UART2 Controller */
++#define	UART3_IOBASE	0x10033000 /* 4KB, UART3 Controller */
++#define AIC_IOBASE	0x10079000 /* 4KB, Audio interface Controller */
++#define SSI0_IOBASE	0x10043000 /* 4KB, Synchronous Serial Interface */
++#define SSI_SLV0_IOBASE	0x10045000 /* 4KB, Synchronous Serial Interface slave */
++#define I2C0_IOBASE	0x10050000 /* 4KB, I2C 0 Bus Interface */
++#define I2C1_IOBASE	0x10051000 /* 4KB, I2C 1 Bus Interface */
++#define	SADC_IOBASE	0x10070000 /* 4KB,  */
++#define	DTRNG_IOBASE	0x10072000 /* 4KB,  */
++#define	MIPI_CSI_IOBASE	0x10073000 /* 4KB,  */
++#define	MIPI_PHY_IOBASE	0x10076000 /* 4KB,  */
++#define	USB_PHY_IOBASE	0x10078000 /* 4KB,  */
++
++
++/* Static Memory Base Address */
++#define NEMC_CS1_IOBASE 0X1b000000
++#define NEMC_CS2_IOBASE 0X1a000000
++
++#define	OST_IOBASE	0x12000000
++
++#define DDRC_BASE       0xb34f0000
++#endif
++
+diff --git a/arch/mips/xburst/soc-x1600/include/soc/cache.h b/arch/mips/xburst/soc-x1600/include/soc/cache.h
+new file mode 100644
+index 000000000..350fe51fa
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/include/soc/cache.h
+@@ -0,0 +1,95 @@
++#ifndef __CHIP_CACHE_H__
++#define __CHIP_CACHE_H__
++#include <asm/cacheops.h>
++#define cache_prefetch(label,size)					\
++do{									\
++	unsigned long addr,end;						\
++	/* Prefetch codes from label */					\
++	addr = (unsigned long)(&&label) & ~(32 - 1);			\
++	end = (unsigned long)(&&label + size) & ~(32 - 1);		\
++	end += 32;							\
++	for (; addr < end; addr += 32) {				\
++		__asm__ volatile (					\
++				".set mips32\n\t"			\
++				" cache %0, 0(%1)\n\t"			\
++				".set mips32\n\t"			\
++				:					\
++				: "I" (Index_Prefetch_I), "r"(addr));	\
++	}								\
++}									\
++while(0)
++
++#define K0BASE			KSEG0
++#define CFG_DCACHE_SIZE		16384
++#define CFG_ICACHE_SIZE		16384
++#define CFG_CACHELINE_SIZE	32
++
++static inline void __jz_flush_cache_all(void)
++{
++	register unsigned long addr;
++	/* Clear CP0 TagLo */
++	asm volatile ("mtc0 $0, $28\n\t");
++	for (addr = K0BASE; addr < (K0BASE + CFG_DCACHE_SIZE); addr += CFG_CACHELINE_SIZE) {
++		asm volatile (".set mips32\n\t"
++				" cache %0, 0(%1)\n\t"
++				".set mips32\n\t"
++				:
++				: "I" (Index_Writeback_Inv_D), "r"(addr));
++	}
++
++	for (addr = K0BASE; addr < (K0BASE + CFG_ICACHE_SIZE); addr += CFG_CACHELINE_SIZE) {
++		asm volatile (".set mips32\n\t"
++				" cache %0, 0(%1)\n\t"
++				".set mips32\n\t"
++				:
++				: "I" (Index_Store_Tag_I), "r"(addr));
++	}
++	/* invalidate BTB */
++	asm volatile (
++			".set mips32\n\t"
++			" mfc0 $26, $16, 7\n\t"
++			" nop\n\t"
++			" ori $26, 2\n\t"
++			" mtc0 $26, $16, 7\n\t"
++			" nop\n\t"
++			".set mips32\n\t"
++		     );
++	asm volatile ("sync\n\t"
++		      "lw $0,0(%0)"
++		      ::"r" (0xa0000000));
++
++}
++
++static inline void __jz_cache_init(void)
++{
++	register unsigned long addr;
++	asm volatile ("mtc0 $0, $28\n\t"::);
++
++	for (addr = K0BASE; addr < (K0BASE + CFG_DCACHE_SIZE); addr += CFG_CACHELINE_SIZE) {
++		asm volatile (".set mips32\n\t"
++				" cache %0, 0(%1)\n\t"
++				".set mips32\n\t"
++				:
++				: "I" (Index_Store_Tag_D), "r"(addr));
++	}
++	for (addr = K0BASE; addr < (K0BASE + CFG_ICACHE_SIZE); addr += CFG_CACHELINE_SIZE) {
++		asm volatile (".set mips32\n\t"
++				" cache %0, 0(%1)\n\t"
++				".set mips32\n\t"
++				:
++				: "I" (Index_Store_Tag_I), "r"(addr));
++	}
++	/* invalidate BTB */
++	asm volatile (  ".set mips32\n\t"
++			" mfc0 $26, $16, 7\n\t"
++			" nop\n\t"
++			" ori $26, 2\n\t"
++			" mtc0 $26, $16, 7\n\t"
++			" nop\n\t"
++			"nop\n\t"
++			".set mips32\n\t"
++		    );
++}
++
++
++#endif /* __CHIP_CACHE_H__ */
+diff --git a/arch/mips/xburst/soc-x1600/include/soc/cpm.h b/arch/mips/xburst/soc-x1600/include/soc/cpm.h
+new file mode 100644
+index 000000000..c7fd73a09
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/include/soc/cpm.h
+@@ -0,0 +1,135 @@
++/*
++ * SOC CPM register definition.
++ *
++ * CPM (Clock reset and Power control Management)
++ *
++ * Copyright (C) 2021 Ingenic Semiconductor Co., Ltd.
++ */
++
++#ifndef __SOC_CPM_H__
++#define __SOC_CPM_H__
++#include <soc/base.h>
++
++/*
++ * CGU Register
++ * */
++#define CPM_CPCCR	(0x00)
++#define CPM_CPCSR	(0xd4)
++
++#define CPM_DDRCDR	(0x2c)
++#define CPM_MACPHYCDR	(0x54)
++#define CPM_I2SCDR	(0x60)
++#define CPM_I2SCDR1	(0x7c)
++#define CPM_LPCDR	(0x64)
++#define CPM_MSC0CDR	(0x68)
++#define CPM_MSC1CDR	(0xa4)
++#define CPM_SFCCDR	(0x74)
++#define CPM_SSICDR	(0x5c)
++#define CPM_CIMCDR	(0x78)
++#define CPM_PWMCDR	(0x6c)
++#define CPM_MACPHYC0	(0xe4)
++#define CPM_CAN0CDR	(0xa0)
++#define CPM_CAN1CDR	(0xa8)
++#define CPM_CDBUSCDR	(0xac)
++
++#define CPM_INTR	(0xb0)
++#define CPM_INTRE	(0xb4)
++#define CPM_SFTINT	(0xbc)
++#define CPM_DRCG	(0xd0)
++#define CPM_CPSPR	(0x34)
++#define CPM_CPSPPR	(0x38)
++
++#define CPM_USBPCR	(0x3c)
++#define CPM_USBRDT	(0x40)
++#define CPM_USBVBFIL	(0x44)
++#define CPM_USBPCR1	(0x48)
++
++#define CPM_CPPCR	(0x0c)
++#define CPM_CPAPCR	(0x10)
++#define CPM_CPAPACR	(0x84)
++#define CPM_CPMPCR	(0x14)
++#define CPM_CPMPACR	(0x88)
++#define CPM_CPEPCR	(0x18)
++#define CPM_CPEPACR	(0x8c)
++
++
++/*
++ * Power Management Register
++ * */
++#define CPM_LCR		(0x04)
++#define CPM_PSWC0ST     (0x90)
++#define CPM_PSWC1ST     (0x94)
++#define CPM_PSWC2ST     (0x98)
++#define CPM_PSWC3ST     (0x9c)
++
++#define CPM_SRBC	(0xc4)
++#define CPM_SLBC	(0xc8)
++#define CPM_SLPC	(0xcc)
++#define CPM_CLKGR	(0x20)
++#define CPM_CLKGR1	(0x28)
++#define CPM_MPDCR0	(0xF8)
++#define CPM_MPDCR1	(0xFC)
++#define CPM_OPCR	(0x24)
++#define CPM_MESTSEL	(0xEC)
++
++
++#ifndef BIT
++#define BIT(nr)  (1UL << nr)
++#endif
++
++/* USB Parameter Control Register */
++#define USBPCR_USB_MODE                 BIT(31)
++#define USBPCR_AVLD_REG                 BIT(30)
++#define USBPCR_IDPULLUP_MASK_BIT        28
++#define USBPCR_IDPULLUP_MASK		(0x3 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_IDPULLUP_OTG             (0x0 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_IDPULLUP_ALWAYS_SUSPEND  (0x1 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_IDPULLUP_ALWAYS          (0x2 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_POR_BIT                  22
++#define USBPCR_POR                      BIT(USBPCR_POR_BIT)
++
++/* USB Reset Detect Timer Register */
++#define USBRDT_RESUME_INTEEN		BIT(31)	/*RW*/
++#define USBRDT_RESUME_INTERCLR		BIT(30)	/*WO*/
++#define USBRDT_RESUME_SPEED_BIT		28	/*RW*/
++#define USBRDT_RESUME_SPEED_MSK		(0x3 << USBRDT_RESUME_SPEED_BIT)
++#define USBRDT_RESUME_SPEED_HIGH	(0x0 << USBRDT_RESUME_SPEED_BIT)
++#define USBRDT_RESUME_SPEED_FULL	(0x1 << USBRDT_RESUME_SPEED_BIT)
++#define USBRDT_RESUME_SPEED_LOW		(0x2 << USBRDT_RESUME_SPEED_BIT)
++#define USBRDT_RESUME_STATUS		BIT(27)	/*RO*/
++#define USBRDT_HB_MASK                  BIT(26)
++#define USBRDT_VBFIL_LD_EN              BIT(25)
++#define USBRDT_IDDIG_EN			BIT(24)
++#define USBRDT_IDDIG_REG                BIT(23)
++#define USBRDT_USBRDT_MSK               (0x7fffff)
++#define USBRDT_USBRDT(x)                ((x) & USBRDT_USBRDT_MSK)
++
++/* USB VBUS Jitter Filter Register */
++#define USBVBFIL_USBVBFIL(x)		((x) & 0xffff)
++#define USBVBFIL_IDDIGFIL(x)		((x) & (0xffff << 16))
++
++/* USB Parameter Control Register1 */
++#define USBPCR1_BVLD_REG        BIT(31)
++#define USBPCR1_DPPULLDOWN	BIT(29)
++#define USBPCR1_DMPULLDOWN	BIT(28)
++#define USBPCR1_PORT_RST	BIT(21)
++
++/* Oscillator and Power Control Register */
++#define OPCR_USB_SPENDN		BIT(7)
++#define OPCR_USB_PHY_GATE	BIT(23)
++#define OPCR_ERCS		(0x1<<2)
++#define OPCR_PD			(0x1<<3)
++#define OPCR_IDLE		(0x1<<31)
++
++/* Low Power Control Register */
++#define LCR_LPM_MASK		(0x3)
++#define LCR_LPM_SLEEP		(0x1)
++
++
++#define cpm_inl(off)		inl(CPM_IOBASE + (off))
++#define cpm_outl(val,off)	outl(val,CPM_IOBASE + (off))
++#define cpm_clear_bit(val,off)	do{cpm_outl((cpm_inl(off) & ~(1<<(val))),off);}while(0)
++#define cpm_set_bit(val,off)	do{cpm_outl((cpm_inl(off) |  (1<<val)),off);}while(0)
++#define cpm_test_bit(val,off)	(cpm_inl(off) & (0x1<<val))
++#endif
++
+diff --git a/arch/mips/xburst/soc-x1600/include/soc/ddr.h b/arch/mips/xburst/soc-x1600/include/soc/ddr.h
+new file mode 100644
+index 000000000..fbd8701c7
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/include/soc/ddr.h
+@@ -0,0 +1,295 @@
++/*
++ * JZ4780 ddr definitions
++ *
++ * Copyright (c) 2013 Ingenic Semiconductor Co.,Ltd
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __DDR_H__
++#define __DDR_H__
++
++#include <soc/base.h>
++
++/*
++ * DDR Controller Registers
++ **/
++#define DDR_MEM_PHY_BASE		0x20000000
++
++#define DDRC_AHB2_OFFSET        0xb34f0000
++#define DDRC_APB_OFFSET         0xb3012000
++#define DDR_PHY_OFFSET          (-0x4e0000 + 0x1000)
++
++
++
++#define DDRC_STATUS		0x0
++#define DDRC_CFG		0x4
++#define DDRC_CTRL		0x8
++#define DDRC_LMR		0xc
++#define DDRC_DLP		0xbc
++//#define DDRC_AUTOSR_EN	0x28
++//#define DDRC_AUTOSR_CNT	0x30
++#define DDRC_REFCNT		0x38
++#define DDRC_DBGINFO	0xE8
++#define DDRC_TIMING(n)	(0x40 + 8 * (n - 1))
++#define DDRC_MMAP0		0x78
++#define DDRC_MMAP1		0x80
++#define DDRC_HREGPRO	0xd8
++#define DDRC_DWCFG		(DDRC_APB_OFFSET + 0x00)
++#define DDRC_DWSTATUS	(DDRC_APB_OFFSET + 0x04)
++#define DDRC_REMAP(n)	(DDRC_APB_OFFSET + 0x08 + 4 * (n - 1))
++#define DDRC_CGUC0		(DDRC_APB_OFFSET + 0x64)
++#define DDRC_CGUC1		(DDRC_APB_OFFSET + 0x68)
++#define DDRC_PREGPRO	(DDRC_APB_OFFSET + 0x6c)
++
++/*
++ * DDR Innophy registers
++ * */
++#define DDRP_INNOPHY_PHY_RST			(DDR_PHY_OFFSET + 0x000)
++#define DDRP_INNOPHY_MEM_CFG			(DDR_PHY_OFFSET + 0x004)
++#define DDRP_INNOPHY_DQ_WIDTH			(DDR_PHY_OFFSET + 0x07c)
++#define DDRP_INNOPHY_CL					(DDR_PHY_OFFSET + 0x014)
++#define DDRP_INNOPHY_CWL				(DDR_PHY_OFFSET + 0x01c)
++#define DDRP_INNOPHY_AL					(DDR_PHY_OFFSET + 0x018)
++#define DDRP_INNOPHY_PLL_FBDIV			(DDR_PHY_OFFSET + 0x080)
++#define DDRP_INNOPHY_PLL_CTRL			(DDR_PHY_OFFSET + 0x084)
++#define DDRP_INNOPHY_PLL_PDIV			(DDR_PHY_OFFSET + 0x088)
++#define DDRP_INNOPHY_PLL_LOCK			(DDR_PHY_OFFSET + 0xc8)
++#define DDRP_INNOPHY_TRAINING_CTRL		(DDR_PHY_OFFSET + 0x008)
++#define DDRP_INNOPHY_CALIB_DONE			(DDR_PHY_OFFSET + 0x10c)
++#define DDRP_INNOPHY_CALIB_DELAY_AL		(DDR_PHY_OFFSET + 0x1d0)
++#define DDRP_INNOPHY_CALIB_DELAY_AH		(DDR_PHY_OFFSET + 0x1d4)
++#define DDRP_INNOPHY_CALIB_BYPASS_AL	(DDR_PHY_OFFSET + 0x158)
++#define DDRP_INNOPHY_CALIB_BYPASS_AH	(DDR_PHY_OFFSET + 0x198)
++#define DDRP_INNOPHY_WL_MODE1			(DDR_PHY_OFFSET + 0x00c)
++#define DDRP_INNOPHY_WL_MODE2			(DDR_PHY_OFFSET + 0x010)
++#define DDRP_INNOPHY_WL_DONE			(DDR_PHY_OFFSET + 0x0c0)
++#define DDRP_INNOPHY_INIT_COMP			(DDR_PHY_OFFSET + 0x0d0)
++
++
++/*
++ * DDRC REGISTER BITS DEFINE
++ * */
++
++/* DDRC Status Register */
++#define DDRC_DSTATUS_MISS	(1 << 6)
++#define DDRC_ST_DPDN		(1 << 5) /* 0 DDR memory is NOT in deep-power-down state
++										1 DDR memory is in deep-power-down state */
++#define DDRC_ST_PDN		(1 << 4) /* 0 DDR memory is NOT in power-down state
++									1 DDR memory is in power-down state */
++#define DDRC_ST_AREF		(1 << 3) /* 0 DDR memory is NOT in auto-refresh state
++										1 DDR memory is in auto-refresh state */
++#define DDRC_ST_SREF		(1 << 2) /* 0 DDR memory is NOT in self-refresh state
++										1 DDR memory is in self-refresh state */
++#define DDRC_ST_CKE1		(1 << 1) /* 0 CKE1 Pin is low
++										1 CKE1 Pin is high */
++#define DDRC_ST_CKE0		(1 << 0) /* 0 CKE0 Pin is low
++										1 CKE0 Pin is high */
++
++/* DDRC Configure Register */
++#define DDRC_CFG_ROW1_BIT	29 /* Row Address width. */
++#define DDRC_CFG_ROW1_MASK	(0x7 << DDRC_CFG_ROW1_BIT)
++#define DDRC_CFG_COL1_BIT	26 /* Row Address width. */
++#define DDRC_CFG_COL1_MASK	(0x7 << DDRC_CFG_COL1_BIT)
++#define DDRC_CFG_BA1		25 /* Bank Address width of DDR memory */
++#define DDRC_CFG_IMBA		(1 << 16)
++#define DDRC_CFG_ROW0_BIT	13 /* Row Address width. */
++#define DDRC_CFG_ROW0_MASK	(0x7 << DDRC_CFG_ROW0_BIT)
++#define DDRC_CFG_COL0_BIT	10 /* Row Address width. */
++#define DDRC_CFG_COL0_MASK	(0x7 << DDRC_CFG_COL1_BIT)
++#define DDRC_CFG_BA0		9 /* Bank Address width of DDR memory */
++
++#define DDRC_CFG_TYPE_BIT	3
++#define DDRC_CFG_TYPE_MASK	(0x7 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR1	(2 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_MDDR	(3 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR2	(4 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_LPDDR2	(5 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR3	(6 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_LPDDR3	(7 << DDRC_CFG_TYPE_BIT)
++
++#define DDRC_CFG_ODTEN		(1 << 2)  /* ODT EN */
++#define DDRC_CFG_CS1EN		(1 << 1)  /* DDR Chip-Select-1 Enable */
++#define DDRC_CFG_CS0EN		(1 << 0)  /* DDR Chip-Select-0 Enable */
++
++/* DDRC Control Register */
++#define DDRC_CTRL_DFI_RST	(1 << 23)
++#define DDRC_CTRL_DLL_RST	(1 << 22)
++#define DDRC_CTRL_CTL_RST	(1 << 21)
++#define DDRC_CTRL_CFG_RST	(1 << 20)
++#define DDRC_CTRL_ACTPD		(1 << 15) /* 0 Precharge all banks before entering power-down
++										 1 Do not precharge banks before entering power-down */
++#define DDRC_CTRL_PDT_BIT	12 /* Power-Down Timer */
++#define DDRC_CTRL_PDT_MASK	(0x7 << DDRC_CTRL_PDT_BIT)
++#define DDRC_CTRL_PDT_DIS	(0 << DDRC_CTRL_PDT_BIT) /* power-down disabled */
++#define DDRC_CTRL_PDT_8		(1 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 8 tCK idle */
++#define DDRC_CTRL_PDT_16	(2 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 16 tCK idle */
++#define DDRC_CTRL_PDT_32	(3 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 32 tCK idle */
++#define DDRC_CTRL_PDT_64	(4 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 64 tCK idle */
++#define DDRC_CTRL_PDT_128	(5 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 128 tCK idle */
++
++#define DDRC_CTRL_PD_CCE	(1 << 7) /* Power down clk freq change enable */
++#define DDRC_CTRL_DPD		(1 << 6) /* 1 Drive external MDDR device entering Deep-Power-Down mode */
++#define DDRC_CTRL_SR		(1 << 5) /* 1 Drive external DDR device entering self-refresh mode
++										0 Drive external DDR device exiting self-refresh mode */
++#define DDRC_CTRL_SR_CCE	(1 << 4) /* Self refresh clk stop request enable */
++#define DDRC_CTRL_CKE		(1 << 1) /* 0 Not set CKE Pin High, 1 Set CKE Pin HIGH */
++#define DDRC_CTRL_RESET		(1 << 0) /* 0 End resetting ddrc_controller, 1 Resetting ddrc_controller */
++
++/* DDRC DFI low power handshake control register */
++#define DDRC_DDLP_TCTLUDP_BIT	24
++#define DDRC_DDLP_TCTLUDP_FF	(0xff << DDRC_DDLP_TCTLUDP_BIT)
++
++/* DDRC Load-Mode-Register */
++#define DDRC_LMR_DDR_ADDR_BIT	12 /* When performing a DDR command, DDRC_ADDR[13:0]
++									  corresponding to external DDR address Pin A[13:0] */
++#define DDRC_LMR_DDR_ADDR_MASK	(0xfffff << DDRC_LMR_DDR_ADDR_BIT)
++
++#define DDRC_LMR_MA_BIT		16 /* FOR LPDDR2, MA[9:0] */
++#define DDRC_LMR_OP_BIT		24 /* FOR LPDDR2, OP[9:0] */
++
++#define DDRC_LMR_BA_BIT		9 /* When performing a DDR command, BA[2:0]
++								 corresponding to external DDR address Pin BA[2:0]. */
++#define DDRC_LMR_BA_MASK	(0x7 << DDRC_LMR_BA_BIT)
++#define DDRC_LMR_CMD_BIT	6
++#define DDRC_LMR_CMD_MASK	(0x7 << DDRC_LMR_CMD_BIT)
++#define DDRC_LMR_CMD_PREC	(0 << DDRC_LMR_CMD_BIT)/* Precharge one bank/All banks */
++#define DDRC_LMR_CMD_AUREF	(1 << DDRC_LMR_CMD_BIT)/* Auto-Refresh */
++#define DDRC_LMR_CMD_LMR	(2 << DDRC_LMR_CMD_BIT)/* Load Mode Register */
++#define DDRC_LMR_CMD_ZQCL_CS0	(3 << DDRC_LMR_CMD_BIT)/* ZQCL for DDR3 on CS0 */
++#define DDRC_LMR_CMD_ZQCL_CS1	(4 << DDRC_LMR_CMD_BIT)/* ZQCL for DDR3 on CS1 */
++#define DDRC_LMR_CMD_ZQCS_CS0	(5 << DDRC_LMR_CMD_BIT)/* ZQCS for DDR3 on CS0 */
++#define DDRC_LMR_CMD_ZQCS_CS1	(6 << DDRC_LMR_CMD_BIT)/* ZQCS for DDR3 on CS1 */
++
++#define DDRC_LMR_TMRD_BIT	1
++#define DDRC_LMR_TMRD_MASK	(0x1f << DDRC_LMR_TMRD_BIT)
++#define DDRC_LMR_START		(1 << 0) /* 0 No command is performed
++										1 On the posedge of START, perform a command
++										defined by CMD field */
++
++/* DDRC  Auto-Refresh Counter */
++#define DDRC_REFCNT_REF_EN		(1 << 0) /* Enable Refresh Counter */
++#define DDRC_REFCNT_CLK_DIV_BIT		1  /* Clock Divider for auto-refresh counter. */
++#define DDRC_REFCNT_CLK_DIV_MASK	(0x7 << DDRC_REFCNT_CLKDIV_BIT)
++
++#define DDRC_REFCNT_PREREF_CNT_BIT	4
++#define DDRC_REFCNT_PREREF_CNT_MASK	(0xf << DDRC_REFCNT_PREREF_CNT_BIT)
++#define DDRC_REFCNT_PREREF_CNT(val)	(val << DDRC_REFCNT_PREREF_CNT_BIT)
++#define DDRC_REFCNT_PREREF_CNT_DEFAULT	DDRC_REFCNT_PREREF_CNT(8)
++
++#define DDRC_REFCNT_CNT_BIT		8  /* 8-bit counter */
++#define DDRC_REFCNT_CNT_MASK		(0xff << DDRC_REFCNT_CNT_BIT)
++
++#define DDRC_REFCNT_CON_BIT		16 /* Constant value used to compare with CNT value. */
++#define DDRC_REFCNT_CON_MASK		(0xff << DDRC_REFCNT_CON_BIT)
++
++#define DDRC_REFCNT_TRFC_BIT		24
++#define DDRC_REFCNT_TRFC_MASK		(0x3f << DDRC_REFCNT_TRFC_BIT)
++
++#define DDRC_REFCNT_PREREF_EN_BIT	30
++#define DDRC_REFCNT_PREREF_EN		(1 << DDRC_REFCNT_PREREF_EN_BIT)
++
++#define DDRC_REFCNT_PBREF_EN_BIT	31
++#define DDRC_REFCNT_PBREF_EN		(1 << DDRC_REFCNT_PBREF_EN_BIT)
++
++/* DDRC Memory Map Config Register */
++#define DDRC_MMAP_BASE_BIT		8 /* base address */
++#define DDRC_MMAP_BASE_MASK		(0xff << DDRC_MMAP_BASE_BIT)
++#define DDRC_MMAP_MASK_BIT		0 /* address mask */
++#define DDRC_MMAP_MASK_MASK		(0xff << DDRC_MMAP_MASK_BIT)
++
++#define DDRC_MMAP0_BASE			(0x20 << DDRC_MMAP_BASE_BIT)
++#define DDRC_MMAP1_BASE_64M		(0x24 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++#define DDRC_MMAP1_BASE_128M		(0x28 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++#define DDRC_MMAP1_BASE_256M		(0x30 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++
++#define DDRC_MMAP_MASK_64_64		(0xfc << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++#define DDRC_MMAP_MASK_128_128		(0xf8 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++#define DDRC_MMAP_MASK_256_256		(0xf0 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++
++/* DDR device data width configure register */
++#define DDRC_DWCFG_DFI_INIT_START	(1 << 3)
++
++/* DDR device status register */
++#define DDRC_DWSTATUS_DFI_INIT_COMP	(1 << 0)
++
++/* DDRC AHB Bus Register Protection Register */
++#define DDRC_HREGPRO_HPRO_EN		(1 << 0)
++
++/* DDRC APB Bus Register Protection Register */
++#define DDRC_PREGPRO_PPRO_EN		(1 << 0)
++
++
++/* DDRC clock gate unit configure 0 */
++#define DDRC_CGU_PORT7		(1 << 28)
++#define DDRC_CGU_PORT6		(1 << 24)
++#define DDRC_CGU_PORT5		(1 << 20)
++#define DDRC_CGU_PORT4		(1 << 16)
++#define DDRC_CGU_PORT3		(1 << 12)
++#define DDRC_CGU_PORT2		(1 << 8)
++#define DDRC_CGU_PORT1		(1 << 4)
++#define DDRC_CGU_PORT0		(1 << 0)
++
++/* DDRC clock gate unit configure 1 */
++#define DDRC_CGU_BWM		(1 << 8)
++#define DDRC_CGU_PCTRL		(1 << 4)
++#define DDRC_CGU_SCH		(1 << 1)
++#define DDRC_CGU_PA		(1 << 0)
++
++
++
++/*
++ * DDR INNOPHY REGISTER BITS DEFINE
++ * */
++
++/* DDRP DQ Width Register */
++#define DDRP_DQ_WIDTH_DQ_H		(1 << 1)
++#define DDRP_DQ_WIDTH_DQ_L		(1 << 0)
++
++/* DDRP Pll Ctrl Register */
++#define DDRP_PLL_CTRL_PLLPDEN		(1 << 1)
++
++/* DDRP Training Ctrl Register */
++#define DDRP_TRAINING_CTRL_WL_BP	(1 << 3)
++#define DDRP_TRAINING_CTRL_WL_START	(1 << 2)
++#define DDRP_TRAINING_CTRL_DSCSE_BP	(1 << 1)
++#define DDRP_TRAINING_CTRL_DSACE_START	(1 << 0)
++
++/* DDRP Training Done Register */
++#define DDRP_CALIB_DONE_HDQCFB 		(1 << 3)
++#define DDRP_CALIB_DONE_LDQCFB 		(1 << 2)
++#define DDRP_CALIB_DONE_HDQCFA 		(1 << 1)
++#define DDRP_CALIB_DONE_LDQCFA 		(1 << 0)
++#define DDRP_CALIB_DONE_HWRLFB 		(1 << 3)
++#define DDRP_CALIB_DONE_LWRLFB 		(1 << 2)
++#define DDRP_CALIB_DONE_HWRLFA 		(1 << 1)
++#define DDRP_CALIB_DONE_LWRLFA 		(1 << 0)
++
++/* DDRP CALIB BP Register */
++#define DDRP_CALIB_BP_CYCLESELBH_BIT	4
++#define DDRP_CALIB_BP_OPHCSELBH_BIT	3
++#define DDRP_CALIB_BP_DLLSELBH_BIT	0
++
++/* DDRP Init Complete Register */
++#define DDRP_INIT_COMP			(1 << 0)
++
++#define DDRP_PLL_LOCK			(1 << 3)
++
++#define REG32(addr) *(volatile unsigned int *)(addr)
++
++#define ddr_writel(value, reg)	(REG32(DDRC_BASE + reg) = (value))
++#define ddr_readl(reg)		REG32(DDRC_BASE + reg)
++#endif /* __DDR_H__ */
+diff --git a/arch/mips/xburst/soc-x1600/include/soc/efuse.h b/arch/mips/xburst/soc-x1600/include/soc/efuse.h
+new file mode 100644
+index 000000000..4d1f660c7
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/include/soc/efuse.h
+@@ -0,0 +1,192 @@
++#ifndef __INGENIC_EFUSE_H__
++#define __INGENIC_EFUSE_H__
++
++#define EFUSE_CTRL		0x0
++#define EFUSE_CFG		0x4
++#define EFUSE_STATE		0x8
++#define EFUSE_DATA(n)		(0xC + (n) * 4)
++
++
++// efuse ctrl bits
++#define EFUSE_CTRL_ADDR              (21)
++#define EFUSE_CTRL_ADDR_MASK         (0x3f)
++#define EFUSE_CTRL_LEN               (16)
++#define EFUSE_CTRL_LEN_MASK          (0x1f)
++#define EFUSE_CTRL_PGEN              (1 << 15)
++#define EFUSE_CTRL_WREN              (1 << 1)
++#define EFUSE_CTRL_RDEN              (1 << 0)
++
++
++// efuse cfg bits
++#define EFUSE_CFG_INT_EN             (1 << 31)
++#define EFUSE_CFG_RD_ADJ             (20)
++#define EFUSE_CFG_RD_ADJ_MASK        (0xf)
++#define EFUSE_CFG_RD_STROBE          (16)
++#define EFUSE_CFG_RD_STROBE_MASK     (0xf)
++#define EFUSE_CFG_WR_ADJ             (12)
++#define EFUSE_CFG_WR_ADJ_MASK        (0xf)
++#define EFUSE_CFG_WR_STROBE          (0)
++#define EFUSE_CFG_WR_STROBE_MASK     (0x7ff)
++
++
++// efuse state bits
++#define EFUSE_STA_NKU_PRT            (1 << 21)
++#define EFUSE_STA_USERKEY_PRT	     (1 << 20)
++#define EFUSE_STA_CHIPKEY_PRT        (1 << 19)
++#define EFUSE_STA_HIDEBLK_PRT        (1 << 18)
++#define EFUSE_STA_SOCINFO_PRT        (1 << 17)
++#define EFUSE_STA_TRIM3_PRT          (1 << 16)
++#define EFUSE_STA_TRIM2_PRT          (1 << 15)
++#define EFUSE_STA_TRIM1_PRT          (1 << 14)
++#define EFUSE_STA_TRIM0_PRT          (1 << 13)
++#define EFUSE_STA_CUT_PRT	     (1 << 12)
++#define EFUSE_STA_CHIPID_PRT         (1 << 11)
++#define EFUSE_STA_SCBT_PRT	     (1 << 10)
++#define EFUSE_STA_DIS_JTAG           (1 << 9)
++#define EFUSE_STA_SCBT_EN            (1 << 8)
++#define EFUSE_STA_WR_DONE            (1 << 1)
++#define EFUSE_STA_RD_DONE            (1 << 0)
++
++
++#define CHIPID_OFFSET_ADDR            (0x0)
++#define CUT_OFFSET_ADDR		      (0x10)
++#define TRIM0_OFFSET_ADDR             (0x1b)
++#define TRIM1_OFFSET_ADDR             (0x1f)
++#define TRIM2_OFFSET_ADDR             (0x23)
++#define TRIM3_OFFSET_ADDR             (0x27)
++#define SOCINFO_OFFSET_ADDR           (0x2b)
++#define HIDEBLK_OFFSET_ADDR           (0x2d)
++#define PRT_OFFSET_ADDR               (0x2e)
++#define CHIPKEY_OFFSET_ADDR           (0x30)
++#define USERKEY_OFFSET_ADDR           (0x50)
++#define NKU_OFFSET_ADDR               (0x70)
++
++
++#define CHIPID_BIT_NUM		    (128)
++#define CUT_BIT_NUM		    (88)
++#define TRIM0_BIT_NUM               (32)
++#define TRIM1_BIT_NUM               (32)
++#define TRIM2_BIT_NUM               (32)
++#define TRIM3_BIT_NUM               (32)
++#define SOCINFO_BIT_NUM             (16)
++#define HIDEBLK_BIT_NUM             (8)
++#define PRT_BIT_NUM                 (16)
++#define CHIPKEY_BIT_NUM             (256)
++#define USERKEY_BIT_NUM		    (256)
++#define NKU_BIT_NUM                 (128)
++
++
++enum segment_id {
++	CHIPID = 0,
++	CUTID,
++	TRIM0,
++	TRIM1,
++	TRIM2,
++	TRIM3,
++	SOCINFO,
++	HIDEBLK,
++	PRT,
++	CHIPKEY,
++	USERKEY,
++	NKU
++};
++
++
++struct seg_info {
++	char seg_name[32];
++	uint32_t seg_id;
++	uint32_t offset_address;
++	uint32_t bit_num;
++	uint32_t prt_bit;
++};
++
++static struct seg_info seg_info_array[] = {
++	[0] = {
++		.seg_name = "CHIPID",
++		.seg_id = CHIPID,
++		.offset_address = CHIPID_OFFSET_ADDR,
++		.bit_num = CHIPID_BIT_NUM,
++		.prt_bit = EFUSE_STA_CHIPID_PRT,
++	},
++	[1] = {
++		.seg_name = "CUTID",
++		.seg_id = CUTID,
++		.offset_address = CUT_OFFSET_ADDR,
++		.bit_num = CUT_BIT_NUM,
++		.prt_bit = EFUSE_STA_CUT_PRT,
++	},
++	[2] = {
++		.seg_name = "TRIM0",
++		.seg_id = TRIM0,
++		.offset_address = TRIM0_OFFSET_ADDR,
++		.bit_num = TRIM0_BIT_NUM,
++		.prt_bit = EFUSE_STA_TRIM0_PRT,
++	},
++	[3] = {
++		.seg_name = "TRIM1",
++		.seg_id = TRIM1,
++		.offset_address = TRIM1_OFFSET_ADDR,
++		.bit_num = TRIM1_BIT_NUM,
++		.prt_bit = EFUSE_STA_TRIM1_PRT,
++	},
++	[4] = {
++		.seg_name = "TRIM2",
++		.seg_id = TRIM2,
++		.offset_address = TRIM2_OFFSET_ADDR,
++		.bit_num = TRIM2_BIT_NUM,
++		.prt_bit = EFUSE_STA_TRIM2_PRT,
++	},
++	[5] = {
++		.seg_name = "TRIM3",
++		.seg_id = TRIM3,
++		.offset_address = TRIM3_OFFSET_ADDR,
++		.bit_num = TRIM3_BIT_NUM,
++		.prt_bit = EFUSE_STA_TRIM3_PRT,
++	},
++	[6] = {
++		.seg_name = "SOCINFO",
++		.seg_id = SOCINFO,
++		.offset_address = SOCINFO_OFFSET_ADDR,
++		.bit_num = SOCINFO_BIT_NUM,
++		.prt_bit = EFUSE_STA_SOCINFO_PRT,
++	},
++	[7] = {
++		.seg_name = "HIDEBLK",
++		.seg_id = HIDEBLK,
++		.offset_address = HIDEBLK_OFFSET_ADDR,
++		.bit_num = HIDEBLK_BIT_NUM,
++		.prt_bit = EFUSE_STA_HIDEBLK_PRT,
++	},
++	[8] = {
++		.seg_name = "PRT",
++		.seg_id = PRT,
++		.offset_address = PRT_OFFSET_ADDR,
++		.bit_num = PRT_BIT_NUM,
++		.prt_bit = 0xffffffff,
++	},
++	[9] = {
++		.seg_name = "CHIPKEY",
++		.seg_id = CHIPKEY,
++		.offset_address = CHIPKEY_OFFSET_ADDR,
++		.bit_num = CHIPKEY_BIT_NUM,
++		.prt_bit = EFUSE_STA_CHIPKEY_PRT,
++	},
++	[10] = {
++		.seg_name = "USERKEY",
++		.seg_id = USERKEY,
++		.offset_address = USERKEY_OFFSET_ADDR,
++		.bit_num = USERKEY_BIT_NUM,
++		.prt_bit = EFUSE_STA_USERKEY_PRT,
++	},
++	[11] = {
++		.seg_name = "NKU",
++		.seg_id = NKU,
++		.offset_address = NKU_OFFSET_ADDR,
++		.bit_num = NKU_BIT_NUM,
++		.prt_bit = EFUSE_STA_NKU_PRT,
++	},
++};
++
++void jz_efuse_id_read(int is_chip_id, uint8_t *buf);
++
++#endif
+diff --git a/arch/mips/xburst/soc-x1600/include/soc/gpio.h b/arch/mips/xburst/soc-x1600/include/soc/gpio.h
+new file mode 100644
+index 000000000..aead63252
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/include/soc/gpio.h
+@@ -0,0 +1,44 @@
++#ifndef _SOC_GPIO_H_
++#define _SOC_GPIO_H_
++
++enum gpio_function {
++    GPIO_FUNC_0         = 0x0100,  //00000, GPIO as function 0 / device 0
++    GPIO_FUNC_1         = 0x0101,  //00001, GPIO as function 1 / device 1
++    GPIO_FUNC_2         = 0x0102,  //00010, GPIO as function 2 / device 2
++    GPIO_FUNC_3         = 0x0103,  //00011, GPIO as function 3 / device 3
++    GPIO_OUTPUT0        = 0x0104,  //00100, GPIO output low  level
++    GPIO_OUTPUT1        = 0x0105,  //00101, GPIO output high level
++    GPIO_INPUT          = 0x0106,  //00110, GPIO as input.7 also.
++    GPIO_INT_LO         = 0x0108,  //01000, Low  Level trigger interrupt
++    GPIO_INT_HI         = 0x0109,  //01001, High Level trigger interrupt
++    GPIO_INT_FE         = 0x010a,  //01010, Fall Edge trigger interrupt
++    GPIO_INT_RE         = 0x010b,  //01011, Rise Edge trigger interrupt
++    GPIO_INT_RE_FE      = 0x011b,  //11011, Dual Edge(both rise and fall) trigger interrupt
++    GPIO_INT_MASK_LO    = 0x010c,  //01100, Port is low level triggered interrupt input. Interrupt is masked.
++    GPIO_INT_MASK_HI    = 0x010d,  //01101, Port is high level triggered interrupt input. Interrupt is masked.
++    GPIO_INT_MASK_FE    = 0x010e,  //01110, Port is fall edge triggered interrupt input. Interrupt is masked.
++    GPIO_INT_MASK_RE    = 0x010f,  //01111, Port is rise edge triggered interrupt input. Interrupt is masked.
++    GPIO_INT_MASK_RE_FE = 0x011f,  //11111, Port is dual edge(both rise and fall edge) triggered interrupt input. Interrupt is masked.
++
++    GPIO_PULL_HIZ       = 0x8000,    //no pull
++    GPIO_PULL           = 0xa000,    //pull, x1600�支�pull,是什么类型的pull �看芯片手册
++};
++
++enum gpio_port {
++    GPIO_PORT_A = 0,
++    GPIO_PORT_B,
++    GPIO_PORT_C,
++    GPIO_PORT_D,
++
++    /* this must be last */
++    GPIO_NR_PORTS,
++};
++
++#define GPIO_PA(n)      (0 * 32 + (n))
++#define GPIO_PB(n)      (1 * 32 + (n))
++#define GPIO_PC(n)      (2 * 32 + (n))
++#define GPIO_PD(n)      (3 * 32 + (n))
++
++int jzgpio_set_func(int port, enum gpio_function func, unsigned long pins);
++
++#endif /* _SOC_GPIO_H_ */
+diff --git a/arch/mips/xburst/soc-x1600/include/soc/ost.h b/arch/mips/xburst/soc-x1600/include/soc/ost.h
+new file mode 100644
+index 000000000..86fbcc3cc
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/include/soc/ost.h
+@@ -0,0 +1,41 @@
++/*
++ * INGENIC ost register definition.
++ *
++ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.
++ */
++
++#ifndef __OST_H__
++#define __OST_H__
++
++#define OST_TCCR	(0x00)   /* OS Timer Clock Control Register*/
++#define OST_TER		(0x04)   /* OS Timer Counter Enable Register */
++#define OST_TCR     	(0x08)   /* OS Timer clear Register */
++#define OST_TFR     	(0x0C)   /* OS Timer Flag Register */
++#define OST_TMR     	(0x10)   /* OS Timer Mask Register */
++#define OST_T1DFR   	(0x14)   /* OS Timer1 Data FULL Register */
++#define OST_T1CNT   	(0x18)   /* OS Timer1 Counter */
++#define OST_T2CNTH  	(0x1c)   /* OS Timer2 Counter High 32 Bits */
++#define OST_T2CNTL  	(0x20)   /* OS Timer2 Counter Lower 32 Bits */
++#define OST_TCNT2HBUF   (0x24)   /* OS Timer2 Counter Higher 32 Bits Buffer */
++#define OST_TESR	(0x34)   /* OS Timer Counter Enable Set Register */
++#define OST_TECR	(0x38)   /* OS Timer Counter Enable Clear Register */
++
++#define TCCRDIV_MSK1	(0x3)
++#define TCCRDIV_SFT2	(2)
++#define TCCRDIV_MSK2	(TCCRDIV_MSK1 << TCCRDIV_SFT2)
++#define TCCRDIV1(x)	({int n = 0; int d = (x); while(d) { d >>= 2; n++; }; (n-1);})
++#define TCCRDIV2(x)	(TCCRDIV1((x)) << TCCRDIV_SFT2)
++
++#define TESR_OSTEN1	(1 << 0)   /* enable the counter1 in ost */
++#define TESR_OSTEN2	(1 << 1)   /* enable the counter2 in ost */
++
++#define TCR_OSTCLR1	(1 << 0)
++#define TCR_OSTCLR2	(1 << 1)
++
++#define TMR_OSTM	(1 << 0)   /* ost comparison match interrupt mask */
++
++#define TFR_OSTM	(1 << 0)   /* Comparison match */
++
++#define ost_readl(reg)		readl_relaxed(reg)
++#define ost_writel(reg, val)	writel_relaxed(val, reg)
++#endif
+diff --git a/arch/mips/xburst/soc-x1600/include/soc/sfc.h b/arch/mips/xburst/soc-x1600/include/soc/sfc.h
+new file mode 100644
+index 000000000..62d3978c9
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/include/soc/sfc.h
+@@ -0,0 +1,207 @@
++#ifndef __SFC_REGISTER_H
++#define __SFC_REGISTER_H
++
++/* SFC register */
++#define	SFC_GLB0			(0x0000)
++#define	SFC_DEV_CONF			(0x0004)
++#define	SFC_DEV_STA_EXP			(0x0008)
++#define	SFC_DEV0_STA_RT			(0x000c)
++#define	SFC_DEV_STA_MSK			(0x0010)
++#define	SFC_TRAN_CONF0(n)		(0x0014 + (n * 4))
++#define	SFC_TRAN_LEN			(0x002c)
++#define	SFC_DEV_ADDR(n)			(0x0030 + (n * 4))
++#define	SFC_DEV_ADDR_PLUS(n)		(0x0048 + (n * 4))
++#define	SFC_MEM_ADDR			(0x0060)
++#define	SFC_TRIG			(0x0064)
++#define	SFC_SR				(0x0068)
++#define	SFC_SCR				(0x006c)
++#define	SFC_INTC			(0x0070)
++#define	SFC_FSM				(0x0074)
++#define	SFC_CGE				(0x0078)
++#define SFC_CMD_IDX                     (0x007c)
++#define SFC_COL_ADDR                    (0x0080)
++#define SFC_ROW_ADDR                    (0x0084)
++#define SFC_STA_ADDR0                   (0x0088)
++#define SFC_STA_ADDR1                   (0x008c)
++#define SFC_DES_ADDR                    (0x0090)
++#define SFC_GLB1			(0x0094)
++#define SFC_DEV1_STA_RT			(0x0098)
++#define	SFC_TRAN_CONF1(n)		(0x009c + (n * 4))
++#define SFC_CDT                         (0x0800)  //0x800 ~ 0xbff
++#define	SFC_RM_DR			(0x1000)
++
++/* For SFC_GLB0 */
++#define GLB0_POLL_TIME_OFFSET		(16)
++#define GLB0_POLL_TIME_MSK		(0xffff << GLB0_POLL_TIME_OFFSET)
++#define GLB0_DES_EN			(1 << 15)
++#define GLB0_CDT_EN			(1 << 14)
++#define	GLB0_TRAN_DIR			(1 << 13)
++#define GLB0_TRAN_DIR_WRITE		(1)
++#define GLB0_TRAN_DIR_READ		(0)
++#define	GLB0_THRESHOLD_OFFSET		(7)
++#define GLB0_THRESHOLD_MSK		(0x3f << GLB0_THRESHOLD_OFFSET)
++#define GLB0_OP_MODE			(1 << 6)
++#define GLB0_OP_OFFSET                   (6)
++#define SLAVE_MODE			(0x0)
++#define DMA_MODE			(0x1)
++#define GLB0_PHASE_NUM_OFFSET		(3)
++#define GLB0_PHASE_NUM_MSK		(0x7  << GLB0_PHASE_NUM_OFFSET)
++#define GLB0_WP_EN			(1 << 2)
++#define GLB0_BURST_MD_OFFSET		(0)
++#define GLB0_BURST_MD_MSK		(0x3  << GLB0_BURST_MD_OFFSET)
++
++/* For SFC_DEV_CONF */
++#define DEV_CONF_STA_ENDIAN_OFFSET	(31)
++#define	STA_ENDIAN_LSB			(0)
++#define	STA_ENDIAN_MSB			(1)
++#define	DEV_CONF_SMP_DELAY_OFFSET	(16)
++#define	DEV_CONF_SMP_DELAY_MSK		(0x1f << DEV_CONF_SMP_DELAY_OFFSET)
++#define DEV_CONF_SMP_DELAY_0		(0)
++#define DEV_CONF_SMP_DELAY_45		(1)
++#define DEV_CONF_SMP_DELAY_90		(2)
++#define DEV_CONF_SMP_DELAY_135		(3)
++#define DEV_CONF_SMP_DELAY_180		(4)
++#define DEV_CONF_SMP_DELAY_225		(5)
++#define DEV_CONF_SMP_DELAY_270		(6)
++#define DEV_CONF_SMP_DELAY_315		(7)
++#define DEV_CONF_SMP_DELAY_1		(8)
++#define DEV_CONF_SMP_DELAY_2		(16)
++#define DEV_CONF_CMD_TYPE		(0x1 << 15)
++#define DEV_CONF_STA_TYPE_OFFSET	(13)
++#define DEV_CONF_STA_TYPE_MSK		(0x3 << DEV_CONF_STA_TYPE_OFFSET)
++#define DEV_CONF_THOLD_OFFSET		(11)
++#define	DEV_CONF_THOLD_MSK		(0x3 << DEV_CONF_THOLD_OFFSET)
++#define DEV_CONF_TSETUP_OFFSET		(9)
++#define DEV_CONF_TSETUP_MSK		(0x3 << DEV_CONF_TSETUP_OFFSET)
++#define DEV_CONF_TSH_OFFSET		(5)
++#define DEV_CONF_TSH_MSK		(0xf << DEV_CONF_TSH_OFFSET)
++#define DEV_CONF_CPHA			(0x1 << 4)
++#define DEV_CONF_CPOL			(0x1 << 3)
++#define DEV_CONF_CEDL			(0x1 << 2)
++#define DEV_CONF_HOLDDL			(0x1 << 1)
++#define DEV_CONF_WPDL			(0x1 << 0)
++
++/* For SFC_TRAN_CONF0 */
++#define TRAN_CONF0_CLK_MODE		(29)
++#define	TRAN_CONF0_CLK_MODE_MSK		(0x7 << TRAN_CONF0_CLK_MODE)
++#define TRAN_CONF0_CLK_MODE_SSS		(0)
++#define TRAN_CONF0_CLK_MODE_SSD		(1)
++#define TRAN_CONF0_CLK_MODE_SDS		(2)
++#define TRAN_CONF0_CLK_MODE_SDD		(3)
++#define TRAN_CONF0_CLK_MODE_DSS		(4)
++#define TRAN_CONF0_CLK_MODE_DSD		(5)
++#define TRAN_CONF0_CLK_MODE_DDS		(6)
++#define TRAN_CONF0_CLK_MODE_DDD		(7)
++#define	TRAN_CONF0_ADDR_WIDTH_OFFSET	(26)
++#define	TRAN_CONF0_ADDR_WIDTH_MSK	(0x7 << TRAN_CONF0_ADDR_WIDTH_OFFSET)
++#define TRAN_CONF0_POLLEN		(1 << 25)
++#define TRAN_CONF0_POLL_OFFSET		(25)
++#define TRAN_CONF0_CMDEN		(1 << 24)
++#define TRAN_CONF0_FMAT			(1 << 23)
++#define TRAN_CONF0_FMAT_OFFSET		(23)
++#define TRAN_CONF0_DMYBITS_OFFSET	(17)
++#define TRAN_CONF0_DMYBITS_MSK		(0x3f << TRAN_CONF0_DMYBITS_OFFSET)
++#define TRAN_CONF0_DATEEN		(1 << 16)
++#define TRAN_CONF0_DATEEN_OFFSET	(16)
++#define	TRAN_CONF0_CMD_OFFSET		(0)
++#define	TRAN_CONF0_CMD_MSK		(0xffff << TRAN_CONF0_CMD_OFFSET)
++
++/* For SFC_TRAN_CONF1 */
++#define TRAN_CONF1_DATA_ENDIAN		(1 << 18)
++#define TRAN_CONF1_DATA_ENDIAN_OFFSET	(18)
++#define TRAN_CONF1_DATA_ENDIAN_LSB	(0)
++#define TRAN_CONF1_DATA_ENDIAN_MSB	(1)
++#define TRAN_CONF1_WORD_UNIT_OFFSET	(16)
++#define TRAN_CONF1_WORD_UNIT_MSK	(3 << 16)
++#define TRAN_CONF1_TRAN_MODE_OFFSET	(4)
++#define TRAN_CONF1_TRAN_MODE_MSK	(0xf << TRAN_CONF1_TRAN_MODE_OFFSET)
++#define TRAN_CONF1_SPI_STANDARD		(0x0)
++#define TRAN_CONF1_SPI_DUAL		(0x1)
++#define TRAN_CONF1_SPI_QUAD		(0x5)
++#define TRAN_CONF1_SPI_IO_QUAD		(0x6)
++#define TRAN_CONF1_SPI_OCTAL		(0x9)
++#define TRAN_CONF1_SPI_IO_OCTAL		(0xa)
++#define TRAN_CONF1_SPI_FULL_OCTAL	(0xb)
++
++
++/* For SFC_TRIG */
++#define TRIG_FLUSH			(1 << 2)
++#define TRIG_STOP			(1 << 1)
++#define TRIG_START			(1 << 0)
++
++/* For SFC_SR */
++#define SFC_WORKING		(1 << 7)
++#define SFC_BUSY		(0x3 << 5)
++#define	SFC_END			(1 << 4)
++#define SFC_TREQ		(1 << 3)
++#define SFC_RREQ		(1 << 2)
++#define SFC_OVER		(1 << 1)
++#define SFC_UNDER		(1 << 0)
++
++/* For SFC_SCR */
++#define	CLR_END			(1 << 4)
++#define CLR_TREQ		(1 << 3)
++#define CLR_RREQ		(1 << 2)
++#define CLR_OVER		(1 << 1)
++#define CLR_UNDER		(1 << 0)
++
++/* SFC_CMD_IDX */
++#define CMD_IDX_MSK                     (0x3f << 0)
++#define CDT_DATAEN_MSK                  (0x1 << 31)
++#define CDT_DATAEN_OFF                  (31)
++#define CDT_DIR_MSK                     (0x1 << 30)
++#define CDT_DIR_OFF                     (30)
++
++/* For SFC_GLB1 */
++#define GLB1_CHIP1_SEL_OFFSET		(31)
++#define GLB1_CHIP1_SEL_MSK		(0x1 << GLB1_CHIP1_SEL_OFFSET)
++#define GLB1_CHIP_SEL_OFFSET		(0)
++#define GLB1_CHIP_SEL_MSK		(0x1 << GLB1_CHIP_SEL_OFFSET)
++#define GLB1_CHIP0_SEL			(0x0)
++#define GLB1_CHIP1_SEL			(0x1)
++
++#define N_MAX			6
++#define MAX_SEGS		128
++
++#define CHANNEL_0		0
++#define CHANNEL_1		1
++#define CHANNEL_2		2
++#define CHANNEL_3		3
++#define CHANNEL_4		4
++#define CHANNEL_5		5
++
++#define ENABLE			1
++#define DISABLE			0
++
++#define COM_CMD			1	// common cmd
++#define POLL_CMD		2	// the cmd will poll the status of flash,ext: read status
++
++#define DMA_OPS			1
++#define CPU_OPS			0
++
++#define TM_STD_SPI		0
++#define TM_DI_DO_SPI	1
++#define TM_DIO_SPI		2
++#define TM_FULL_DIO_SPI	3
++#define TM_QI_QO_SPI	5
++#define TM_QIO_SPI		6
++#define	TM_FULL_QIO_SPI	7
++
++
++#define DEFAULT_CDT		1
++#define UPDATE_CDT		2
++#define DEFAULT_ADDRSIZE	3
++#define DEFAULT_ADDRMODE	0
++
++
++#define THRESHOLD		32
++
++#define SFC_NOR_RATE    110
++#define DEF_ADDR_LEN    3
++#define DEF_TCHSH       6
++#define DEF_TSLCH       6
++#define DEF_TSHSL_R     20
++#define DEF_TSHSL_W     50
++
++
++#endif
+diff --git a/arch/mips/xburst/soc-x1600/include/soc/tcsm_layout.h b/arch/mips/xburst/soc-x1600/include/soc/tcsm_layout.h
+new file mode 100644
+index 000000000..19ba6667d
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/include/soc/tcsm_layout.h
+@@ -0,0 +1,53 @@
++#ifndef __TCSM_LAYOUT_H__
++#define __TCSM_LAYOUT_H__
++
++/**
++ *      |-------------|
++ *      |    BANK0    |
++ *      |-------------|     <--- SLEEP_TCSM_BOOTCODE_TEXT
++ *      |             |
++ *      |             |
++ *      |             |
++ *      |             |
++ *      |             |
++ *      |             |
++ *      |             |
++ *      |-------------|
++ *      | VO DMA DESC |
++ *      |_____________|     <--- VOICE_TCSM_DMA_DESC
++ *
++ *
++ *      |-------------|
++ *      |    BANK1    |
++ *      |-------------|     <--- VOICE_TCSM_DATA_BUF
++ *      |             |
++ *      |             |
++ *      |    ...      |
++ *      |  VOICE DATA |
++ *      |    ...      |
++ *      |             |
++ *      |             |
++ *      |_____________|
++ *
++ */
++
++/*
++ * If you use the VOICE TRIGGER,
++ * and you change the VOICE_* and TCSM_BANK_LEN,
++ * while compiling wakeup module
++ */
++#define SLEEP_TCSM_SPACE           0xb3422000
++#define VOICE_TCSM_DATA_BUF	       0xb3423000
++#define TCSM_BANK_LEN              4096
++
++#define SLEEP_TCSM_BOOT_TEXT       (SLEEP_TCSM_SPACE)
++
++#define VOICE_TCSM_DMA_DESC_LEN    512
++#define SLEEP_TCSM_SPACE_END       (SLEEP_TCSM_SPACE + TCSM_BANK_LEN - VOICE_TCSM_DMA_DESC_LEN)
++#define VOICE_TCSM_DMA_DESC_ADDR   SLEEP_TCSM_SPACE_END
++
++#define SLEEP_TCSM_CPU_RESMUE_SP   SLEEP_TCSM_SPACE_END - 4
++
++#define VOICE_TCSM_DATA_BUF_SIZE   TCSM_BANK_LEN
++
++#endif	/*  __TCSM_LAYOUT_H__ */
+diff --git a/arch/mips/xburst/soc-x1600/include/soc/tcu.h b/arch/mips/xburst/soc-x1600/include/soc/tcu.h
+new file mode 100644
+index 000000000..0532718c0
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/include/soc/tcu.h
+@@ -0,0 +1,84 @@
++/*
++ * JZ4770 tcu register definition.
++ *
++ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.
++ */
++
++#ifndef __TCU_H__
++#define __TCU_H__
++
++#define WDT_TDR			(0x00)  /* rw, 32, 0x???????? */
++#define WDT_TCER		(0x04)  /* rw, 32, 0x???????? */
++#define WDT_TCNT		(0x08)  /* rw, 32, 0x???????? */
++#define WDT_TCSR		(0x0c)  /* rw, 32, 0x???????? */
++
++#define TCU_TSTR	(0xF0)   /* Timer Status Register,Only Used In Tcu2 Mode */
++#define TCU_TSTSR	(0xF4)   /* Timer Status Set Register */
++#define TCU_TSTCR	(0xF8)   /* Timer Status Clear Register */
++#define TCU_TSR		(0x1C)   /* Timer Stop Register */
++#define TCU_TSSR	(0x2C)   /* Timer Stop Set Register */
++#define TCU_TSCR	(0x3C)   /* Timer Stop Clear Register */
++#define TCU_TER		(0x10)   /* Timer Counter Enable Register */
++#define TCU_TESR	(0x14)   /* Timer Counter Enable Set Register */
++#define TCU_TECR	(0x18)   /* Timer Counter Enable Clear Register */
++#define TCU_TFR		(0x20)   /* Timer Flag Register */
++#define TCU_TFSR	(0x24)   /* Timer Flag Set Register */
++#define TCU_TFCR	(0x28)   /* Timer Flag Clear Register */
++#define TCU_TMR		(0x30)   /* Timer Mask Register */
++#define TCU_TMSR	(0x34)   /* Timer Mask Set Register */
++#define TCU_TMCR	(0x38)   /* Timer Mask Clear Register */
++
++#define CH_TDFR(n)	(0x40 + (n)*0x10) /* Timer Data Full Reg */
++#define CH_TDHR(n)	(0x44 + (n)*0x10) /* Timer Data Half Reg */
++#define CH_TCNT(n)	(0x48 + (n)*0x10) /* Timer Counter Reg */
++#define CH_TCSR(n)	(0x4C + (n)*0x10) /* Timer Control Reg */
++
++#define TER_OSTEN	(1 << 15)   /* enable the counter in ost */
++#define TMR_OSTM	(1 << 15)   /* ost comparison match interrupt mask */
++#define TFR_OSTF	(1 << 15)   /* ost interrupt flag */
++#define TSR_OSTS	(1 << 15)   /*the clock supplies to osts is stopped */
++
++#define TSR_WDTS	(1 << 16)   /*the clock supplies to wdt is stopped */
++
++#define CSR_EXT_EN	(1 << 2)  /* select extal as the timer clock input */
++#define CSR_RTC_EN	(1 << 1)  /* select rtcclk as the timer clock input */
++#define CSR_PCK_EN	(1 << 0)  /* select pclk as the timer clock input */
++#define CSR_CLK_MSK	(0x7)
++
++#define CSR_DIV1	(0x0 << 3)
++#define CSR_DIV4	(0x1 << 3)
++#define CSR_DIV16	(0x2 << 3)
++#define CSR_DIV64	(0x3 << 3)
++#define CSR_DIV256	(0x4 << 3)
++#define CSR_DIV1024	(0x5 << 3)
++#define CSR_DIV_MSK	(0x7 << 3)
++
++// Register bits definitions
++#define TSTR_REAL2		(1 << 18) /* only used in TCU2 mode */
++#define TSTR_REAL1		(1 << 17) /* only used in TCU2 mode */
++#define TSTR_BUSY2		(1 << 2)  /* only used in TCU2 mode */
++#define TSTR_BUSY1		(1 << 1)  /* only used in TCU2 mode */
++
++#define TCSR_PWM_BYPASS (1 << 11) /* clear counter to 0, only used in TCU2 mode */
++#define TCSR_CNT_CLRZ		(1 << 10) /* clear counter to 0, only used in TCU2 mode */
++#define TCSR_PWM_SD		(1 << 9)  /* shut down the pwm output only used in TCU1 mode */
++#define TCSR_PWM_HIGH		(1 << 8)  /* selects an initial output level for pwm output */
++#define TCSR_PWM_EN		(1 << 7)  /* pwm pin output enable */
++#define TCSR_PWM_IN		(1 << 6)  /* pwm pin output enable */
++
++
++/*
++ * Operating system timer module(OST) address definition
++ */
++
++#define OST_DR		(0xe0)
++#define OST_CNTL	(0xe4)
++#define OST_CNTH	(0xe8)
++#define OST_CSR		(0xec)
++#define OST_CNTH_BUF	(0xfc)
++
++/* Operating system control register(OSTCSR) */
++#define OSTCSR_CNT_MD	(1 << 15)
++
++#endif
++
+diff --git a/arch/mips/xburst/soc-x1600/include/war.h b/arch/mips/xburst/soc-x1600/include/war.h
+new file mode 100644
+index 000000000..fd1ef3147
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/include/war.h
+@@ -0,0 +1,27 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
++ */
++#ifndef __ASM_MACH_INGENIC_WAR_H__
++#define __ASM_MACH_INGENIC_WAR_H__
++
++#define R4600_V1_INDEX_ICACHEOP_WAR	0
++#define R4600_V1_HIT_CACHEOP_WAR	0
++#define R4600_V2_HIT_CACHEOP_WAR	0
++#define R5432_CP0_INTERRUPT_WAR		0
++#define BCM1250_M3_WAR			0
++#define SIBYTE_1956_WAR			0
++#define MIPS4K_ICACHE_REFILL_WAR	0
++#define MIPS_CACHE_SYNC_WAR		1
++#define MIPS_BRIDGE_SYNC_WAR            1
++#define TX49XX_ICACHE_INDEX_INV_WAR	0
++#define RM9000_CDEX_SMP_WAR		0
++#define ICACHE_REFILLS_WORKAROUND_WAR	0
++#define R10000_LLSC_WAR			0
++#define MIPS34K_MISSED_ITLB_WAR		0
++
++#endif
++
+diff --git a/arch/mips/xburst/soc-x1600/libdmmu.c b/arch/mips/xburst/soc-x1600/libdmmu.c
+new file mode 100644
+index 000000000..457799b7c
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/libdmmu.c
+@@ -0,0 +1,1087 @@
++/*
++ * This driver is used by VPU driver.
++ *
++ * Copyright (C) 2015 Ingenic Semiconductor Co., Ltd.
++ *	http://www.ingenic.com
++ * Author:	Yan Zhengting <zhengting.yan@ingenic.com>
++ * Modify by:	Sun Jiwei <jiwei.sun@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/platform_device.h>
++#include <linux/fs.h>
++#include <linux/file.h>
++#include <linux/mm.h>
++#include <linux/list.h>
++#include <linux/mutex.h>
++#include <linux/proc_fs.h>
++#include <linux/debugfs.h>
++#include <linux/mempolicy.h>
++#include <linux/mm_types.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <asm/current.h>
++#include <asm/cacheflush.h>
++#include <asm/tlbflush.h>
++#include <asm/io.h>
++#include <linux/vmalloc.h>
++#include <linux/sched.h>
++#include <ingenic_proc.h>
++#include <linux/module.h>
++#include <linux/mmu_context.h>
++#include <linux/mmu_notifier.h>
++
++
++#include <libdmmu.h>
++#define print_dbg(f, arg...) printk(KERN_INFO "dpu: %s, %d: " f "\n", __func__, __LINE__, ## arg)
++
++#define MAP_COUNT		0x10
++#define MAP_CONUT_MASK		0xff0
++
++#define DMMU_PTE_VLD 		0x01
++#define DMMU_PMD_VLD 		0x01
++
++#define KSEG0_LOW_LIMIT		0x80000000
++#define KSEG1_HEIGH_LIMIT	0xC0000000
++
++enum mem_break{
++    MODE1,  /* 13 24 57 68 911 1012 ... */
++    MODE2,  /* 13 24 35 46 57 68 79 810 ... */
++    MODE3   /* 12 34 56 78 ... */
++};
++
++LIST_HEAD(handle_list);
++static unsigned long reserved_pte = 0;
++static unsigned long res_pte_paddr;
++
++struct pmd_node {
++	unsigned int count;
++	unsigned long index;
++	unsigned long page;
++	struct list_head list;
++};
++
++struct map_node {
++	struct device *dev;
++	unsigned long start;
++	unsigned long len;
++	struct list_head list;
++};
++
++struct dmmu_handle {
++	pid_t tgid;
++	unsigned long pdg;
++	struct mutex lock;
++	struct list_head list;
++	struct list_head pmd_list;
++	struct list_head map_list;
++	struct list_head dev_notifier_list;
++
++	struct mm_struct *handle_mm; /* mm struct used to match exit_mmap notify */
++
++	struct mmu_notifier mn;
++};
++
++
++/* for test */
++static struct dmmu_handle *find_handle(void);
++static struct dmmu_handle *create_handle(void);
++static void dmmu_cache_wback(struct dmmu_handle *h);
++static int dmmu_mm_dev_release(struct dmmu_handle *h);
++
++int dmmu_flush_cache(unsigned long vaddr, unsigned long len)
++{
++	struct list_head *pos, *next;
++	struct dmmu_handle *h = NULL;
++	struct map_node *n = NULL;
++	unsigned long *pgd, *pte_phys, *pte;
++	unsigned long virpage_phy;
++	unsigned long v_end = vaddr+len;
++	int found = 0;
++	int index;
++
++	h = find_handle();
++	if(!h){
++		printk("%s find handle err!\n",__func__);
++		return -1;
++	}
++	if (vaddr & 0xfff) {
++		printk("%s addr align page err!\n",__func__);
++		return -1;
++	}
++	list_for_each_safe(pos, next, &h->map_list) {
++		n = list_entry(pos, struct map_node, list);
++		if((vaddr >= n->start) &&
++			((vaddr+len) <= (n->start + n->len))) {
++			found = 1;
++			break;
++		}
++	}
++	if(!found) {
++		printk("%s addr err!\n",__func__);
++		return -1;
++	}
++	pgd = (unsigned long *)h->pdg;
++	while(vaddr < v_end) {
++		index = vaddr>>22;
++		pte_phys = (unsigned long *)(pgd[index] & ~DMMU_PMD_VLD);
++		pte = (unsigned long *)phys_to_virt((unsigned long)pte_phys);
++		index = ((vaddr & 0x3ff000) >> 12);
++		virpage_phy = pte[index] & ~DMMU_PTE_VLD;
++		dma_cache_wback((unsigned long)phys_to_virt(virpage_phy),PAGE_SIZE);
++		vaddr+=PAGE_SIZE;
++	}
++	return 0;
++}
++
++EXPORT_SYMBOL(dmmu_flush_cache);
++static int make_smash_list(struct dmmu_handle *h, unsigned long vaddr, unsigned long (**base)[2], unsigned int *len)
++{
++    unsigned long *pgd = (unsigned long *)h->pdg;
++    unsigned long (*list_smash)[2] = NULL;
++    unsigned int list_len = 0;
++    unsigned long *pte, *pte_phys;
++    unsigned int i, index;
++
++    struct list_head *pos, *next;
++	struct map_node *n;
++
++    list_for_each_safe(pos, next, &h->map_list) {
++        n = list_entry(pos, struct map_node, list);
++        if(vaddr == n->start) {
++            list_len = (n->len) >> 12;
++            break;
++        }
++    }
++
++    if (list_len) {
++        list_smash = kmalloc(list_len * 2 * 4, GFP_KERNEL);
++        if (list_smash) {
++            i = 0;
++            while(i < list_len) {
++                list_smash[i][0] = (unsigned long)(vaddr & 0xfffff000);
++
++		index = vaddr>>22;
++                pte_phys = (unsigned long *)(pgd[index] & ~DMMU_PMD_VLD);
++
++
++		pte = (unsigned long *)phys_to_virt((unsigned long)pte_phys);
++
++		index = ((vaddr & 0x3ff000) >> 12);
++//		printk(">>>>>>virt = 0x%lx, phys = 0x%lx\n", vaddr,
++//				*((unsigned long int *) (((unsigned long)pte_phys+index*4) | 0xa0000000)));
++		list_smash[i][1] = pte[index];
++
++                vaddr+=0x1000;
++		i++;
++            }
++        }
++    }
++
++    if (list_smash) {
++        *base = list_smash;
++        *len = list_len;
++        return 0;
++    } else {
++        return -1;
++    }
++}
++EXPORT_SYMBOL(dmmu_dump_map);
++
++int dmmu_dump_map(unsigned long vaddr)
++{
++	struct dmmu_handle *h = NULL;
++    unsigned long (*list_smash)[2] = NULL;
++    unsigned int list_len = 0;
++    unsigned long *tmp;
++
++	h = find_handle();
++	if(!h)
++		h = create_handle();
++	if(!h)
++		return -1;
++    /* 检查4k对� */
++    if (vaddr & 0xfff){
++        return -1;
++    }
++
++	mutex_lock(&h->lock);
++
++    if (make_smash_list(h, vaddr, &list_smash, &list_len)) {
++	    mutex_unlock(&h->lock);
++        return -1;
++    } else {
++        unsigned int i;
++        for (i = 0; i<list_len; i++) {
++	    tmp = (unsigned long*)((list_smash[i][1] & ~1) | 0xa0000000);
++            printk("[virt: 0x%08lx ---> phys: 0x%08lx] uncache: 0x%08lx\n",
++			    list_smash[i][0],list_smash[i][1],(unsigned long)tmp);
++
++	    printk("value[0] = 0x%08lx, value[1] = 0x%08lx value[2] = 0x%08lx value[1013] = 0x%08lx\n",
++			tmp[0], tmp[1], tmp[2], tmp[1013]);
++        }
++    }
++
++	mutex_unlock(&h->lock);
++    kfree((void*)list_smash);
++
++    return 0;
++}
++
++    /* 13 24 57 68 911 1012 ... */
++static int smash_mode1(unsigned long (*base)[2], unsigned int len)
++{
++    unsigned int i;
++    unsigned long tmp;
++    if (len >= 4) {
++        for (i=0; i<len; i += 2) {
++            tmp = base[i][1];
++            base[i][1] = base[i+1][1];
++            base[i+1][1] = tmp;
++        }
++    }
++    return 0;
++}
++
++    /* 13 24 35 46 57 68 79 810 ... */
++static int smash_mode2(unsigned long (*base)[2], unsigned int len)
++{
++    /* unsigned int i; */
++    /* unsigned long tmp; */
++    return 0;
++}
++
++    /* 12 34 56 78 ... */
++static int smash_mode3(unsigned long (*base)[2], unsigned int len)
++{
++    unsigned int i;
++    unsigned long tmp;
++if (len >= 4) {
++        for (i=0; i<len/2-1; i++) {
++            tmp = base[i][1];
++            base[i][1] = base[len-1-i][1];
++            base[len-1-i][1] = tmp;
++        }
++        for (i=0; i<len; i += 2) {
++            tmp = base[i][1];
++            base[i][1] = base[i+1][1];
++            base[i+1][1] = tmp;
++        }
++    }
++    return 0;
++}
++
++static int update_dmmu_pte(struct dmmu_handle *h, unsigned long vaddr,
++		           unsigned long (**base)[2], unsigned int len)
++{
++    unsigned long *pgd = (unsigned long *)h->pdg;
++    unsigned long *pte;
++    unsigned int i, index;
++
++    for (i=0; i<len; i++) {
++	index = vaddr>>22;
++        pte = (unsigned long *)(pgd[index] & ~DMMU_PMD_VLD);
++	pte = (unsigned long *)phys_to_virt((unsigned long)pte);
++
++	index = ((vaddr & 0x3ff000) >> 12);
++	pte[index] = (*base)[i][1];
++         vaddr+=0x1000;
++    }
++    return 0;
++}
++
++static int update_process_pte(unsigned long vaddr, unsigned long (**base)[2], unsigned int len)
++{
++    unsigned int i;
++    pgd_t *pgdir;
++    pmd_t *pmdir;
++    pte_t *pte;
++    spin_lock(&current->mm->page_table_lock);
++    for (i=0; i<len; i++) {
++        pgdir = pgd_offset(current->mm, vaddr);
++        if(pgd_none(*pgdir) || pgd_bad(*pgdir))
++            return 0;
++        pmdir = pmd_offset((pud_t *)pgdir, vaddr);
++        if(pmd_none(*pmdir) || pmd_bad(*pmdir))
++            return 0;
++        pte = pte_offset_kernel(pmdir,vaddr);
++        if (pte_present(*pte)){
++	  pte->pte = (*base)[i][1];
++	}
++        vaddr += 4096;
++    }
++    spin_unlock(&current->mm->page_table_lock);
++    return 0;
++}
++
++int dmmu_memory_smash(unsigned long vaddr, int smash_mode)
++{
++	struct dmmu_handle *h = NULL;
++    unsigned long (*list_smash)[2] = NULL;
++    unsigned int list_len = 0;
++	struct vm_area_struct * vma;
++
++	h = find_handle();
++	if(!h){
++		h = create_handle();
++	}
++	if(!h)
++		return -1;
++
++    /* 检查4k对� */
++    if (vaddr & 0xfff){
++        return -1;
++    }
++
++	mutex_lock(&h->lock);
++
++    if (make_smash_list(h, vaddr, &list_smash, &list_len)) {
++	    mutex_unlock(&h->lock);
++        return -1;
++    } else {
++        switch (smash_mode) {
++            case MODE1:
++		print_dbg("smash_mode = %u\n",smash_mode);
++                smash_mode1(list_smash, list_len);
++                break;
++            case MODE2:
++		print_dbg("smash_mode = %u\n",smash_mode);
++                smash_mode2(list_smash, list_len);
++                break;
++            case MODE3:
++		print_dbg("smash_mode = %u\n",smash_mode);
++                smash_mode3(list_smash, list_len);
++                break;
++            default:
++                break;
++        }
++    }
++    update_dmmu_pte(h, vaddr, &list_smash, list_len);
++    update_process_pte(vaddr, &list_smash, list_len);
++
++	dmmu_cache_wback(h);
++	vma = find_vma(current->mm, vaddr);
++	flush_tlb_range(vma, vaddr, vaddr+(list_len*PAGE_SIZE));
++
++	mutex_unlock(&h->lock);
++    kfree(list_smash);
++
++    return 0;
++}
++EXPORT_SYMBOL(dmmu_memory_smash);
++
++static struct map_node *check_map(struct dmmu_handle *h,unsigned long vaddr,unsigned long len)
++{
++	struct list_head *pos, *next;
++	struct map_node *n;
++	list_for_each_safe(pos, next, &h->map_list) {
++		n = list_entry(pos, struct map_node, list);
++		if(vaddr == n->start && len == n->len)
++			return n;
++	}
++	return NULL;
++}
++
++static void handle_add_map(struct device *dev,struct dmmu_handle *h,unsigned long vaddr,unsigned long len)
++{
++	struct map_node *n = kmalloc(sizeof(*n),GFP_KERNEL);
++	if(n == NULL) {
++		printk("malloc map_list node failed !!\n");
++		return;
++	}
++	n->dev = dev;
++	n->start = vaddr;
++	n->len = len;
++	INIT_LIST_HEAD(&n->list);
++	list_add(&n->list,&h->map_list);
++}
++
++static unsigned int get_pfn(unsigned int vaddr)
++{
++	pgd_t *pgdir;
++	pmd_t *pmdir;
++	pte_t *pte;
++	pgdir = pgd_offset(current->mm, vaddr);
++	if(pgd_none(*pgdir) || pgd_bad(*pgdir)) {
++		return 0;
++	}
++	pmdir = pmd_offset((pud_t *)pgdir, vaddr);
++	if(pmd_none(*pmdir) || pmd_bad(*pmdir)) {
++		return 0;
++	}
++	pte = pte_offset_kernel(pmdir,vaddr);
++	if (pte_present(*pte)) {
++
++		return pte_pfn(*pte) << PAGE_SHIFT;
++	}
++
++	return 0;
++}
++
++static unsigned long dmmu_v2pfn(unsigned long vaddr)
++{
++	if(vaddr < KSEG0_LOW_LIMIT)
++		return get_pfn(vaddr);
++
++	if(vaddr >= KSEG0_LOW_LIMIT && vaddr < KSEG1_HEIGH_LIMIT)
++		return virt_to_phys((void *)vaddr);
++
++	panic("dmmu_v2pfn error!");
++	return 0;
++}
++
++static unsigned long unmap_node(struct pmd_node *n,unsigned long vaddr,unsigned long end,int check)
++{
++	unsigned int *pte = (unsigned int *)n->page;
++	int index = ((vaddr & 0x3ff000) >> 12);
++	int free = !check || (--n->count == 0);
++	struct page *page = NULL;
++
++	if(vaddr && end) {
++		while(index < 1024 && vaddr < end) {
++			if(pte[index] & MAP_CONUT_MASK) {
++				pte[index] -= MAP_COUNT;
++			} else {
++				page = pfn_to_page(pte[index] >> PAGE_SHIFT);
++
++				ClearPageReserved(page);
++				pte[index] = reserved_pte;
++			}
++			index++;
++			vaddr += 4096;
++		}
++	}
++
++	if(free) {
++		ClearPageReserved(virt_to_page((void *)n->page));
++		free_page(n->page);
++		list_del(&n->list);
++		kfree(n);
++	}
++
++	return vaddr;
++}
++
++static unsigned long map_node(struct pmd_node *n,unsigned int vaddr,unsigned int end)
++{
++	unsigned int *pte = (unsigned int *)n->page;
++	int index = ((vaddr & 0x3ff000) >> 12);
++	struct page * page = NULL;
++	unsigned long pfn = 0;
++
++
++	while(index < 1024 && vaddr < end) {
++		if(pte[index] == reserved_pte) {
++
++			mmap_write_lock(current->mm);
++
++			pfn = dmmu_v2pfn(vaddr) >> PAGE_SHIFT;
++			page = pfn_to_page(pfn);
++
++			SetPageReserved(page);
++
++			pte[index] = (pfn << PAGE_SHIFT) | DMMU_PTE_VLD;
++
++			mmap_write_unlock(current->mm);
++		} else {
++			pte[index] += MAP_COUNT;
++		}
++		index++;
++		vaddr += 4096;
++	}
++	n->count++;
++	return vaddr;
++}
++
++static struct pmd_node *find_node(struct dmmu_handle *h,unsigned int vaddr)
++{
++	struct list_head *pos, *next;
++	struct pmd_node *n;
++
++	list_for_each_safe(pos, next, &h->pmd_list) {
++		n = list_entry(pos, struct pmd_node, list);
++		if(n->index == (vaddr & 0xffc00000))
++			return n;
++	}
++	return NULL;
++}
++
++static struct pmd_node *add_node(struct dmmu_handle *h,unsigned int vaddr)
++{
++	int i;
++	unsigned long *pte;
++	unsigned long *pgd = (unsigned long *)h->pdg;
++	struct pmd_node *n = kmalloc(sizeof(*n),GFP_KERNEL);
++	INIT_LIST_HEAD(&n->list);
++	n->count = 0;
++	n->index = vaddr & 0xffc00000;
++	n->page = __get_free_page(GFP_KERNEL);
++	SetPageReserved(virt_to_page((void *)n->page));
++
++	pte = (unsigned long *)n->page;
++	for(i=0;i<1024;i++)
++		pte[i] = reserved_pte;
++
++	list_add(&n->list, &h->pmd_list);
++
++	pgd[vaddr>>22] = dmmu_v2pfn(n->page) | DMMU_PMD_VLD;
++	return n;
++}
++
++static struct dmmu_handle *find_handle(void)
++{
++	struct list_head *pos, *next;
++	struct dmmu_handle *h;
++
++
++	list_for_each_safe(pos, next, &handle_list) {
++		h = list_entry(pos, struct dmmu_handle, list);
++		if(h->tgid == current->tgid)
++			return h;
++	}
++	return NULL;
++}
++
++/**
++* @brief unmap node from map list, clear each pmd_node in pmd_list,
++* 	Not free handle, let dmmu_unmap_all do it.
++*
++* @param h
++*
++* @return
++*/
++static int dmmu_unmap_node_unlock(struct dmmu_handle *h)
++{
++	struct map_node *cn;
++	struct list_head *pos, *next;
++
++	unsigned long vaddr;
++	int len;
++	unsigned long end;
++
++	struct pmd_node *node;
++
++	list_for_each_safe(pos, next, &h->map_list) {
++		/* find and delete a map node from map_list */
++		cn = list_entry(pos, struct map_node, list);
++		vaddr = cn->start;
++		len = cn->len;
++		end = vaddr + len;
++
++		while(vaddr < end) {
++			node = find_node(h,vaddr);
++			if(node)
++				vaddr = unmap_node(node,vaddr,end,1);
++		}
++
++		list_del(&cn->list);
++		kfree(cn);
++	}
++
++
++	return 0;
++
++}
++
++
++void dmmu_mm_release(struct mmu_notifier *mn,
++                struct mm_struct *mm)
++{
++	struct dmmu_handle *h = container_of(mn, struct dmmu_handle, mn);
++
++	printk("===== dmmu release mm (TODO: not checked) ====h: %p\n", h);
++
++	if(h->handle_mm != mm) {
++		return;
++	}
++
++	mutex_lock(&h->lock);
++
++	dmmu_mm_dev_release(h);
++
++	dmmu_unmap_node_unlock(h);
++
++	mutex_unlock(&h->lock);
++}
++
++static const struct mmu_notifier_ops dmmu_mm_notifier_ops = {
++        .release = dmmu_mm_release,
++};
++
++
++static struct dmmu_handle *create_handle(void)
++{
++	struct dmmu_handle *h;
++	unsigned int pgd_index;
++	unsigned long *pgd;
++
++	h = kmalloc(sizeof(struct dmmu_handle),GFP_KERNEL);
++	if(!h)
++		return NULL;
++
++	h->tgid = current->tgid;
++	h->pdg = __get_free_page(GFP_KERNEL);
++	if(!h->pdg) {
++		pr_err("%s %d, Get free page for PGD error\n",
++				__func__, __LINE__);
++		kfree(h);
++		return NULL;
++	}
++	SetPageReserved(virt_to_page((void *)h->pdg));
++
++	pgd = (unsigned long *)h->pdg;
++
++	for (pgd_index=0; pgd_index < PTRS_PER_PGD; pgd_index++)
++		pgd[pgd_index] = res_pte_paddr;
++
++	INIT_LIST_HEAD(&h->list);
++	INIT_LIST_HEAD(&h->pmd_list);
++	INIT_LIST_HEAD(&h->map_list);
++	INIT_LIST_HEAD(&h->dev_notifier_list);
++	mutex_init(&h->lock);
++
++	/* register exit_mmap notify */
++	h->handle_mm = current->mm;
++
++	h->mn.ops = &dmmu_mm_notifier_ops;
++
++	mmu_notifier_register(&h->mn, h->handle_mm);
++
++	list_add(&h->list, &handle_list);
++
++	return h;
++}
++
++static int dmmu_make_present(unsigned long addr,unsigned long end)
++{
++#if 0
++	unsigned long i;
++	for(i = addr; i < end; i += 4096) {
++		*(volatile unsigned char *)(i) = 0;
++	}
++	*(volatile unsigned char *)(end - 1) = 0;
++	return 0;
++#else
++	int ret, len, write;
++	struct vm_area_struct * vma;
++	unsigned long vm_page_prot;
++
++	mmap_write_lock(current->mm);
++	vma = find_vma(current->mm, addr);
++	if (!vma) {
++		printk("dmmu_make_present error. addr=%lx len=%lx\n",addr,end-addr);
++		mmap_write_unlock(current->mm);
++		return -1;
++	}
++
++	if(vma->vm_flags & VM_PFNMAP) {
++		mmap_write_unlock(current->mm);
++		return 0;
++	}
++	write = (vma->vm_flags & VM_WRITE) != 0;
++	BUG_ON(addr >= end);
++	BUG_ON(end > vma->vm_end);
++
++	vm_page_prot = pgprot_val(vma->vm_page_prot);
++	vma->vm_page_prot = __pgprot(vm_page_prot | _PAGE_VALID| _PAGE_ACCESSED | _PAGE_PRESENT);
++
++	len = DIV_ROUND_UP(end, PAGE_SIZE) - addr/PAGE_SIZE;
++	ret = get_user_pages(addr, len, write, NULL, NULL);
++	vma->vm_page_prot = __pgprot(vm_page_prot);
++	if (ret < 0) {
++		printk("dmmu_make_present get_user_pages error(%d). addr=%lx len=%lx\n",0-ret,addr,end-addr);
++		mmap_write_unlock(current->mm);
++		return ret;
++	}
++
++	mmap_write_unlock(current->mm);
++	return ret == len ? 0 : -1;
++#endif
++}
++
++static void dmmu_cache_wback(struct dmmu_handle *h)
++{
++	struct list_head *pos, *next;
++	struct pmd_node *n;
++
++	dma_cache_wback(h->pdg,PAGE_SIZE);
++
++	list_for_each_safe(pos, next, &h->pmd_list) {
++		n = list_entry(pos, struct pmd_node, list);
++		dma_cache_wback(n->page,PAGE_SIZE);
++	}
++}
++
++static void dmmu_dump_handle(struct seq_file *m, void *v, struct dmmu_handle *h);
++
++unsigned long dmmu_map(struct device *dev,unsigned long vaddr,unsigned long len)
++{
++	int end = vaddr + len;
++	struct dmmu_handle *h;
++	struct pmd_node *node;
++
++	h = find_handle();
++	if(!h)
++		h = create_handle();
++	if(!h)
++		return 0;
++
++	mutex_lock(&h->lock);
++#ifdef DEBUG
++	printk("(pid %d)dmmu_map %lx %lx================================================\n",h->tgid,vaddr,len);
++#endif
++	if(check_map(h,vaddr,len))
++	{
++		mutex_unlock(&h->lock);
++		return dmmu_v2pfn(h->pdg);
++	}
++
++	if(dmmu_make_present(vaddr,vaddr+len))
++	{
++		mutex_unlock(&h->lock);
++		return 0;
++	}
++
++	handle_add_map(dev,h,vaddr,len);
++
++	while(vaddr < end) {
++		node = find_node(h,vaddr);
++		if(!node) {
++			node = add_node(h,vaddr);
++		}
++		vaddr = map_node(node,vaddr,end);
++	}
++	dmmu_cache_wback(h);
++#ifdef DEBUG
++	dmmu_dump_handle(NULL,NULL,h);
++#endif
++	mutex_unlock(&h->lock);
++
++	return dmmu_v2pfn(h->pdg);
++}
++EXPORT_SYMBOL(dmmu_map);
++
++static int dmmu_mm_dev_release(struct dmmu_handle *h)
++{
++	struct dmmu_mm_notifier *n = NULL;
++	struct list_head *pos, *next;
++
++	list_for_each_safe(pos, next, &h->dev_notifier_list) {
++		n = list_entry(pos, struct dmmu_mm_notifier, list);
++		if(n && n->ops && n->ops->mm_release) {
++			n->ops->mm_release(n->data);
++		}
++
++		list_del(&n->list);
++	}
++
++
++	return 0;
++}
++
++
++int dmmu_register_mm_notifier(struct dmmu_mm_notifier *dmn)
++{
++	int dev_already_registered = 0;
++	struct dmmu_mm_notifier *n = NULL;
++	struct dmmu_handle *h;
++	struct list_head *pos, *next;
++
++	h = find_handle();
++	if(!h) {
++		return -EINVAL;
++	}
++
++	mutex_lock(&h->lock);
++
++	list_for_each_safe(pos, next, &h->dev_notifier_list) {
++		n = list_entry(pos, struct dmmu_mm_notifier, list);
++
++		if(n == dmn) {
++			/* already in dev_notifier_list*/
++			dev_already_registered = 1;
++		}
++
++	}
++
++	if(dev_already_registered) {
++		goto out;
++	}
++
++	list_add_tail(&dmn->list, &h->dev_notifier_list);
++out:
++	mutex_unlock(&h->lock);
++	return 0;
++}
++EXPORT_SYMBOL(dmmu_register_mm_notifier);
++
++int dmmu_unmap(struct device *dev,unsigned long vaddr, int len)
++{
++	unsigned long end = vaddr + len;
++	struct dmmu_handle *h;
++	struct pmd_node *node;
++	struct map_node *n;
++
++	h = find_handle();
++	if(!h) {
++		return 0;
++	}
++
++	mutex_lock(&h->lock);
++#ifdef DEBUG
++	printk("dmmu_unmap %lx %x**********************************************\n",vaddr,len);
++#endif
++	n = check_map(h,vaddr,len);
++	if(!n) {
++		mutex_unlock(&h->lock);
++		return -EAGAIN;
++	}
++	if(n->dev != dev) {
++		mutex_unlock(&h->lock);
++		return -EAGAIN;
++	}
++
++	list_del(&n->list);
++	kfree(n);
++
++	while(vaddr < end) {
++		node = find_node(h,vaddr);
++		if(node)
++			vaddr = unmap_node(node,vaddr,end,1);
++	}
++
++	if(list_empty(&h->pmd_list) && list_empty(&h->map_list)) {
++		list_del(&h->list);
++		ClearPageReserved(virt_to_page((void *)h->pdg));
++		free_page(h->pdg);
++		mutex_unlock(&h->lock);
++
++		mmu_notifier_unregister(&h->mn, h->handle_mm);
++
++		kfree(h);
++		return 0;
++	}
++
++	mutex_unlock(&h->lock);
++	return 0;
++}
++EXPORT_SYMBOL(dmmu_unmap);
++
++int dmmu_free_all(struct device *dev)
++{
++	struct dmmu_handle *h;
++	struct pmd_node *node;
++	struct map_node *cn;
++	struct list_head *pos, *next;
++
++	h = find_handle();
++	if(!h)
++		return 0;
++
++	mutex_lock(&h->lock);
++
++	list_for_each_safe(pos, next, &h->map_list) {
++		cn = list_entry(pos, struct map_node, list);
++		node = find_node(h,cn->start);
++		if(node)
++			unmap_node(node,cn->start,cn->len,1);
++		list_del(&cn->list);
++		kfree(cn);
++	}
++
++	list_for_each_safe(pos, next, &h->pmd_list) {
++		node = list_entry(pos, struct pmd_node, list);
++		if(node){
++			printk("WARN: pmd list should NULL\n");
++			unmap_node(node,0,0,0);
++		}
++	}
++
++	list_del(&h->list);
++	ClearPageReserved(virt_to_page((void *)h->pdg));
++	free_page(h->pdg);
++
++	mutex_unlock(&h->lock);
++	mmu_notifier_unregister(&h->mn, h->handle_mm);
++	kfree(h);
++	return 0;
++}
++
++/**
++* @brief release all resources, which should be called by driver close
++*
++* @param dev
++*
++* @return
++*/
++int dmmu_unmap_all(struct device *dev)
++{
++	struct dmmu_handle *h;
++	struct map_node *cn;
++	struct list_head *pos, *next;
++
++#ifdef DEBUG
++	printk("dmmu_unmap_all\n");
++#endif
++
++	h = find_handle();
++	if(!h) {
++		printk("dmmu unmap all not find hindle, maybe it has benn freed already, name: %s\n", dev->kobj.name);
++		return 0;
++	}
++
++	list_for_each_safe(pos, next, &h->map_list) {
++		cn = list_entry(pos, struct map_node, list);
++		if(dev == cn->dev) {
++			dmmu_unmap(dev,cn->start,cn->len);
++		}
++	}
++
++
++	if(list_empty(&h->map_list))
++		dmmu_free_all(dev);
++	return 0;
++}
++EXPORT_SYMBOL(dmmu_unmap_all);
++int __init dmmu_init(void)
++{
++	unsigned int pte_index;
++	unsigned long res_page_paddr;
++	unsigned long reserved_page;
++	unsigned int *res_pte_vaddr;
++
++	reserved_page = __get_free_page(GFP_KERNEL);
++	if (!reserved_page) {
++		pr_err("%s %d, Get reserved page error\n",
++				__func__, __LINE__);
++		return ENOMEM;
++	}
++	SetPageReserved(virt_to_page((void *)reserved_page));
++	reserved_pte = dmmu_v2pfn(reserved_page) | DMMU_PTE_VLD;
++
++	res_page_paddr = virt_to_phys((void *)reserved_page) | 0xFFF;
++
++	res_pte_vaddr = (unsigned int *)__get_free_page(GFP_KERNEL);
++	if (!res_pte_vaddr) {
++		pr_err("%s %d, Get free page for PTE error\n",
++				__func__, __LINE__);
++		free_page(reserved_page);
++		return ENOMEM;
++	}
++	SetPageReserved(virt_to_page(res_pte_vaddr));
++	res_pte_paddr = virt_to_phys((void *)res_pte_vaddr) | DMMU_PTE_VLD;
++
++	for (pte_index = 0; pte_index < PTRS_PER_PTE; pte_index++)
++		res_pte_vaddr[pte_index] = res_page_paddr;
++
++
++
++	return 0;
++}
++arch_initcall(dmmu_init);
++
++void dmmu_dump_vaddr(unsigned long vaddr)
++{
++	struct dmmu_handle *h;
++	struct pmd_node *node;
++
++	unsigned long *pmd,*pte;
++	h = find_handle();
++	if(!h) {
++		printk("dmmu_dump_vaddr %08lx error - h not found!\n",vaddr);
++		return;
++	}
++
++	node = find_node(h,vaddr);
++	if(!node) {
++		printk("dmmu_dump_vaddr %08lx error - node not found!\n",vaddr);
++		return;
++	}
++
++	pmd = (unsigned long *)h->pdg;
++	pte = (unsigned long *)node->page;
++
++	printk("pmd base = %p; pte base = %p\n",pmd,pte);
++	printk("pmd = %08lx; pte = %08lx\n",pmd[vaddr>>22],pte[(vaddr&0x3ff000)>>12]);
++}
++
++static void dmmu_dump_handle(struct seq_file *m, void *v, struct dmmu_handle *h)
++{
++	struct list_head *pos, *next;
++	struct map_node *n;
++
++	list_for_each_safe(pos, next, &h->map_list) {
++		n = list_entry(pos, struct map_node, list);
++		{
++			int i = 0;
++			int vaddr = n->start;
++			struct pmd_node *pn = find_node(h,vaddr);
++			unsigned int *pte = (unsigned int *)pn->page;
++
++			while(vaddr < (n->start + n->len)) {
++				if(i++%8 == 0)
++					printk("\nvaddr %08x : ",vaddr & 0xfffff000);
++				printk("%08x ",pte[(vaddr & 0x3ff000)>>12]);
++				vaddr += 4096;
++			}
++			printk("\n\n");
++		}
++	}
++}
++
++static int dmmu_proc_show(struct seq_file *m, void *v)
++{
++	struct list_head *pos, *next;
++	struct dmmu_handle *h;
++	volatile unsigned long flags;
++	local_irq_save(flags);
++		list_for_each_safe(pos, next, &handle_list) {
++			h = list_entry(pos, struct dmmu_handle, list);
++			dmmu_dump_handle(m, v, h);
++		}
++	local_irq_restore(flags);
++	return 0;
++}
++
++static int dmmu_open(struct inode *inode, struct file *file)
++{
++	return single_open(file, dmmu_proc_show, PDE_DATA(inode));
++}
++
++static const struct proc_ops dmmus_proc_fops ={
++	.proc_read = seq_read,
++	.proc_open = dmmu_open,
++	.proc_lseek = seq_lseek,
++	.proc_release = single_release,
++};
++
++static int __init init_dmmu_proc(void)
++{
++	struct proc_dir_entry *p;
++	p = jz_proc_mkdir("dmmu");
++	if (!p) {
++		printk("create_proc_entry for common dmmu failed.\n");
++		return -ENODEV;
++	}
++	proc_create("dmmus", 0600,p,&dmmus_proc_fops);
++
++	return 0;
++}
++
++module_init(init_dmmu_proc);
+diff --git a/arch/mips/xburst/soc-x1600/pm.c b/arch/mips/xburst/soc-x1600/pm.c
+new file mode 100644
+index 000000000..946c483c8
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/pm.c
+@@ -0,0 +1,762 @@
++#include <linux/init.h>
++#include <linux/pm.h>
++#include <linux/suspend.h>
++
++#include <soc/cache.h>
++#include <soc/base.h>
++#include <asm/io.h>
++#include <soc/ddr.h>
++#include <soc/base.h>
++#include <soc/cpm.h>
++#include <asm/r4kcache.h>
++#include "pm.h"
++
++#define CORE_PD
++#ifdef CORE_PD
++#define X1600_IDLE_PD
++#endif
++#define MEMORY_PD
++
++//#define PM_TEST
++
++
++/*************************************************************************************/
++#ifdef PM_TEST
++
++#define GPIO_PB_BASE (0xb0010100)
++#define GPIO_PC_BASE (0xb0010200)
++
++
++unsigned int intc0_msk;
++unsigned int intc1_msk;
++unsigned int gpio_pb_int;
++unsigned int gpio_pb_msk;
++unsigned int gpio_pb_pat1;
++unsigned int gpio_pb_pat0;
++unsigned int gpio_pc_int;
++unsigned int gpio_pc_msk;
++unsigned int gpio_pc_pat1;
++unsigned int gpio_pc_pat0;
++
++unsigned int clk_gate0;
++unsigned int clk_gate1;
++
++
++
++static void enable_pc31_int_low(void)
++{
++	unsigned int ahb2_intc = 0xb0001000;
++
++	printk("intc0 src, ahb2_intc + 0x00: %08x\n", *(volatile unsigned int *)(ahb2_intc + 0x00));
++	printk("intc0 msk, ahb2_intc + 0x04: %08x\n", *(volatile unsigned int *)(ahb2_intc + 0x04));
++	printk("intc0 pnd, ahb2_intc + 0x10: %08x\n", *(volatile unsigned int *)(ahb2_intc + 0x10));
++
++	printk("intc1 src, ahb2_intc + 0x20: %08x\n", *(volatile unsigned int *)(ahb2_intc + 0x20));
++	printk("intc1 msk, ahb2_intc + 0x24: %08x\n", *(volatile unsigned int *)(ahb2_intc + 0x24));
++	printk("intc1 pnd, ahb2_intc + 0x30: %08x\n", *(volatile unsigned int *)(ahb2_intc + 0x30));
++
++
++
++	intc0_msk = *(volatile unsigned int *)0xb0001004;
++	*(volatile unsigned int *)0xb0001004 = intc0_msk & ~(1<<15); // GPIO2 INT MSK
++	gpio_pc_int = *(volatile unsigned int *) (GPIO_PC_BASE + 0x10);
++	gpio_pc_msk = *(volatile unsigned int *) (GPIO_PC_BASE + 0x20);
++	gpio_pc_pat1 = *(volatile unsigned int *)(GPIO_PC_BASE + 0x30);
++	gpio_pc_pat0 = *(volatile unsigned int *)(GPIO_PC_BASE + 0x40);
++
++
++	*(volatile unsigned int *)(GPIO_PC_BASE + 0x10) = gpio_pc_int | (1<<31);
++	*(volatile unsigned int *)(GPIO_PC_BASE + 0x20) = gpio_pc_msk & ~(1<<31);
++	*(volatile unsigned int *)(GPIO_PC_BASE + 0x30) = gpio_pc_pat1 & ~(1<<31);
++	*(volatile unsigned int *)(GPIO_PC_BASE + 0x40) = gpio_pc_pat0 & ~(1<<31); // low level trigger int
++	//*(volatile unsigned int *)(GPIO_PB_BASE + 0x40) = gpio_pb_pat0 | ~(1<<23); // high level trigger int
++
++}
++
++
++
++
++static void enable_rtc_wakeup(void)
++{
++	unsigned int tmp;
++
++	intc1_msk = *(volatile unsigned int *)0xb0001024;
++	*(volatile unsigned int *)0xb0001024 = intc1_msk & ~(1<<0); // RTC INT MSK
++	tmp = rtc_read_reg(0xb0003048);
++	tmp |= (1 << 18);
++	rtc_write_reg(0xb0003048, tmp);
++
++	tmp = rtc_read_reg(0xb000302c);
++	tmp |= 1;
++	rtc_write_reg(0xb000302c, tmp);
++}
++
++
++static void pm_test_config(void)
++{
++
++	//clk gate
++	clk_gate0 = cpm_inl(CPM_CLKGR);
++	clk_gate1 = cpm_inl(CPM_CLKGR1);
++
++	clk_gate0 = 0xffffffff;
++	clk_gate0 &= ~(1 << 31);	//ddr
++	clk_gate0 &= ~(1 << 29);	//ahb0
++	clk_gate0 &= ~(1 << 28);	//apb0
++	clk_gate0 &= ~(1 << 27);	//rtc
++	clk_gate0 &= ~(1 << 21);	//pdma
++	clk_gate0 &= ~(1 << 20);	//ost
++	clk_gate0 &= ~(1 << 16);	//uart2
++
++	clk_gate1 = 0xffffffff;
++	clk_gate1 &= ~(1 << 30);	//arb
++	clk_gate1 &= ~(1 << 26);	//intc
++
++	cpm_outl(clk_gate0, CPM_CLKGR);
++	cpm_outl(clk_gate1, CPM_CLKGR1);
++
++	// wakeup source
++	enable_pc31_int_low();
++
++	enable_rtc_wakeup();
++
++
++}
++
++
++#endif	//PM_TEST
++/*************************************************************************************/
++
++static void memory_pd_enter(void)
++{
++#ifdef MEMORY_PD
++	unsigned int val;
++	val = 0xffffffff;
++	val &= ~(1 << 22);	//msc1
++	val &= ~(1 << 19);	//pdma_slp
++	val &= ~(1 << 18);	//pdma_sec
++	val &= ~(1 << 17);	//pdma
++	val &= ~(1 << 2);	//uart2
++	*(volatile unsigned int *)0xb00000f8 = val;
++	val = 0xfffffff0;
++	*(volatile unsigned int *)0xb00000fc = val;
++#endif
++}
++
++static void memory_pd_exit(void)
++{
++#ifdef MEMORY_PD
++	*(volatile unsigned int *)0xb00000f8 = 0;
++	*(volatile unsigned int *)0xb00000fc = 0;
++#endif
++}
++
++
++#ifdef DEBUG_PM
++static void x1600_pm_gate_check(void)
++{
++	unsigned int gate0 = cpm_inl(CPM_CLKGR);
++	unsigned int gate1 = cpm_inl(CPM_CLKGR1);
++	int i;
++	int x;
++
++	printk("gate0 = 0x%08x\n", gate0);
++	printk("gate1 = 0x%08x\n", gate1);
++	for (i = 0; i < 32; i++) {
++		x = (gate0 >> i) & 1;
++		if (x == 0)
++			 printk("warning : bit[%d] in clk gate0 is enabled\n", i);
++	}
++	for (i = 0; i < 32; i++) {
++		x = (gate1 >> i) & 1;
++		if (x == 0)
++			printk("warning : bit[%d] in clk gate1 is enabled\n", i);
++	}
++
++}
++#endif
++
++
++
++static void ddrp_auto_calibration(void)
++{
++	unsigned int reg;
++	unsigned int timeout = 0xffffff;
++	unsigned int al, ah;
++
++	reg = ddr_readl(DDRP_INNOPHY_TRAINING_CTRL);
++	reg &= ~(DDRP_TRAINING_CTRL_DSCSE_BP);
++	ddr_writel(reg, DDRP_INNOPHY_TRAINING_CTRL);
++
++	reg = ddr_readl(DDRP_INNOPHY_TRAINING_CTRL);
++	reg |= (DDRP_TRAINING_CTRL_DSACE_START);
++	ddr_writel(reg, DDRP_INNOPHY_TRAINING_CTRL);
++
++	while(!((ddr_readl(DDRP_INNOPHY_CALIB_DONE) & 0x13) == 3) && --timeout) {
++		TCSM_PCHAR('t');
++		serial_put_hex(ddr_readl(DDRP_INNOPHY_CALIB_DONE));
++	}
++
++	if(!timeout) {
++		TCSM_PCHAR('f');
++	}
++
++	reg = ddr_readl(DDRP_INNOPHY_TRAINING_CTRL);
++	reg &= ~(1);
++	ddr_writel(reg, DDRP_INNOPHY_TRAINING_CTRL);
++
++	al = ddr_readl(DDRP_INNOPHY_CALIB_DELAY_AL);
++	ah = ddr_readl(DDRP_INNOPHY_CALIB_DELAY_AH);
++
++	{
++		unsigned int cycsel, tmp;
++		unsigned int read_data0, read_data1;
++		unsigned int c0, c1;
++		unsigned int max;
++
++		read_data0 = *(volatile unsigned int *)(0xb3011000 + (0x74 << 2));
++		read_data1 = *(volatile unsigned int *)(0xb3011000 + (0x75 << 2));
++		c0 = (read_data0 >> 4) & 0x7;
++		c1 = (read_data1 >> 4) & 0x7;
++
++		max = max(c0, c1);
++
++		cycsel = max + 1;
++
++		tmp = *(volatile unsigned int *)(0xb3011000 + (0xa << 2));
++		tmp &= ~(7 << 1);
++		tmp |= cycsel << 1;
++		*(volatile unsigned int *)(0xb3011000 + (0xa << 2)) = tmp;
++
++
++		tmp = *(volatile unsigned int *)(0xb3011000 + 0x4);
++		tmp |= 1 << 6;
++		*(volatile unsigned int *)(0xb3011000 + (0x1 << 2)) = tmp;
++	}
++
++	TCSM_PCHAR('B');
++
++}
++
++
++
++
++static void load_func_to_tcsm(unsigned int *tcsm_addr,unsigned int *f_addr,unsigned int size)
++{
++	unsigned int instr;
++	int offset;
++	int i;
++#ifdef DEBUG_PM
++	printk("tcsm addr = %p %p size = %d\n",tcsm_addr,f_addr,size);
++#endif
++	for(i = 0;i < size / 4;i++) {
++		instr = f_addr[i];
++		if((instr >> 26) == 2){
++			offset = instr & 0x3ffffff;
++			offset = (offset << 2) - ((unsigned int)f_addr & 0xfffffff);
++			if(offset > 0) {
++				offset = ((unsigned int)tcsm_addr & 0xfffffff) + offset;
++				instr = (2 << 26) | (offset >> 2);
++			}
++		}
++		tcsm_addr[i] = instr;
++	}
++}
++
++
++#ifdef X1600_IDLE_PD
++static int soc_pm_idle_pd(void)
++{
++	unsigned int lcr = cpm_inl(CPM_LCR);
++	unsigned int opcr = cpm_inl(CPM_OPCR);
++
++	printk("lpm is idle pd\n");
++
++	lcr &=~ 0x3; // low power mode: IDLE
++	lcr |= 2;
++	cpm_outl(lcr, CPM_LCR);
++
++	opcr &= ~ (1<<31);
++	opcr |= (1 << 30);
++	opcr |= (1 << 26);	//l2c power down
++	opcr |= 1 << 2; // select RTC clk
++	cpm_outl(opcr, CPM_OPCR);
++
++	return 0;
++}
++#else
++static int soc_pm_idle(void)
++{
++	unsigned int lcr = cpm_inl(CPM_LCR);
++	unsigned int opcr = cpm_inl(CPM_OPCR);
++
++	printk("lpm is idle \n");
++
++	lcr &=~ 0x3; // low power mode: IDLE
++	cpm_outl(lcr, CPM_LCR);
++
++	opcr &= ~(1 << 30);
++	opcr &= ~(1 << 31);
++	cpm_outl(opcr, CPM_OPCR);
++
++	return 0;
++}
++#endif
++
++static int soc_pm_sleep(void)
++{
++	unsigned int lcr = cpm_inl(CPM_LCR);
++	unsigned int opcr = cpm_inl(CPM_OPCR);
++
++	lcr &=~ 0x3;
++	lcr |= 1 << 0; // low power mode: SLEEP
++	cpm_outl(lcr, CPM_LCR);
++
++	opcr &= ~(1 << 31);
++	opcr |= (1 << 30);
++	opcr |= (1 << 21); // pdma ram clear sd.
++	opcr &= ~(1 << 4); // exclk disable;
++	opcr |= (1 << 2); // select RTC clk
++	opcr |= (1 << 22);
++	opcr |= (1 << 20);
++
++#ifdef CORE_PD
++	opcr |= (1 << 3); // power down CPU
++	opcr |= (1 << 26); //L2C power down
++	printk("pd core and l2c\n");
++#else
++	opcr &= ~(1 << 3); // no power down CPU
++	opcr &= ~(1 << 26); //L2C not power down
++	printk("not pd core and l2c\n");
++#endif
++	cpm_outl(opcr, CPM_OPCR);
++
++	return 0;
++}
++
++static int soc_post_wakeup(void)
++{
++	unsigned int lcr = cpm_inl(CPM_LCR);
++	lcr &= ~0x3; // low power mode: IDLE
++	cpm_outl(lcr, CPM_LCR);
++
++	printk("post wakeup!\n");
++
++
++	{
++		/* after power down cpu by set PD in OPCR, resume cpu's frequency and L2C's freq */
++		unsigned int val;
++
++		/* change disable */
++		val = cpm_inl(CPM_CPCCR);
++		val &= ~(1 << 22);
++		cpm_outl(val, CPM_CPCCR);
++
++		/* resume cpu_div in CPCCR */
++		val &= ~0xf;
++		val |= sleep_param->cpu_div;
++		cpm_outl(val, CPM_CPCCR);
++
++		/* change enable */
++		val |= (1 << 22);
++		cpm_outl(val, CPM_CPCCR);
++
++		while (cpm_inl(CPM_CPCSR) & 1);
++	}
++
++#ifdef PM_TEST
++	{
++		cpm_outl(clk_gate0, CPM_CLKGR);
++		cpm_outl(clk_gate1, CPM_CLKGR1);
++
++		*(volatile unsigned int*)(GPIO_PB_BASE + 0x10) = gpio_pb_int;
++		*(volatile unsigned int*)(GPIO_PB_BASE + 0x20) = gpio_pb_msk;
++		*(volatile unsigned int *)(GPIO_PB_BASE + 0x30) = gpio_pb_pat1;
++		*(volatile unsigned int *)(GPIO_PB_BASE + 0x40) = gpio_pb_pat0;
++
++		*(volatile unsigned int*)(0xb0001004) = intc0_msk;
++
++	}
++#endif
++
++	memory_pd_exit();
++
++	return 0;
++}
++
++static noinline void cpu_resume_bootup(void)
++{
++	TCSM_PCHAR('X');
++
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"move $29, %0	\n\t"
++		"jr.hb   %1	\n\t"
++		"nop		\n\t"
++		".set pop	\n\t"
++		:
++		:"r" (SLEEP_CPU_RESUME_SP), "r"(SLEEP_CPU_RESUME_TEXT)
++		:
++		);
++
++}
++#define reg_ddr_phy(x)   (*(volatile unsigned int *)(0xb3011000 + ((x) << 2)))
++static noinline void cpu_resume(void)
++{
++	unsigned int ddrc_ctrl;
++	unsigned int r11s6;
++	unsigned int r16s6;
++
++	TCSM_PCHAR('R');
++
++	/* set reset entry */
++	r11s6 = __read_32bit_c0_register($11, 6);
++	__asm__ volatile("ehb\n\t");
++	r16s6 = __read_32bit_c0_register($16, 6);
++	__asm__ volatile("ehb\n\t");
++	r11s6 |= (1 << 8);
++	r16s6 &= ~0xfffff000;
++	r16s6 |= 0xbfc00000 & 0xfffff000;
++	__write_32bit_c0_register($11, 6, r11s6);
++	__write_32bit_c0_register($16, 6, r16s6);
++
++	TCSM_PCHAR('D');
++
++	if (sleep_param->state == PM_SUSPEND_STANDBY) {
++		/* ddr auto clock gating */
++		*(volatile unsigned int *)0xb3012068 &= ~(1 << 31);
++	}
++
++	if (sleep_param->state == PM_SUSPEND_MEM) {
++		int tmp;
++
++		/* enable pll */
++		tmp = reg_ddr_phy(0x21);
++		tmp &= ~(1 << 1);
++		reg_ddr_phy(0x21) = tmp;
++
++		while (!(reg_ddr_phy(0x42) & 0x8))
++			serial_put_hex(reg_ddr_phy(0x42));
++
++		/* dfi_init_start = 0, wait dfi_init_complete */
++		*(volatile unsigned int *)0xb301208c &= ~1;
++		while(!(*(volatile unsigned int *)0xb301208c & (0x1 << 1)));
++
++		/* bufferen_core = 1 */
++		tmp = *(volatile unsigned int *)0xb3012034;
++		tmp &= ~(1 << 2);	//high
++		*(volatile unsigned int *)0xb3012034 = tmp;
++
++		ddrc_ctrl = ddr_readl(DDRC_CTRL);
++		ddrc_ctrl &= ~(1<<5);
++		ddr_writel(ddrc_ctrl, DDRC_CTRL);
++
++		while(ddr_readl(DDRC_STATUS) & (1<<2));
++
++		TCSM_DELAY(1000);
++		TCSM_PCHAR('1');
++		ddrp_auto_calibration();
++		TCSM_PCHAR('2');
++
++		/* restore ddr auto-sr */
++		*(volatile unsigned int *)0xb3011304 = sleep_param->autorefresh;
++		TCSM_PCHAR('3');
++
++		/* restore ddr LPEN */
++		ddr_writel(sleep_param->dlp, DDRC_DLP);
++
++		/* restore ddr deep power down state */
++		ddrc_ctrl = ddr_readl(DDRC_CTRL);
++		ddrc_ctrl |= sleep_param->pdt;
++		ddrc_ctrl |= sleep_param->dpd;
++		ddr_writel(ddrc_ctrl, DDRC_CTRL);
++
++		TCSM_PCHAR('4');
++
++	}
++
++
++	TCSM_PCHAR('5');
++
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"jr.hb %0	\n\t"
++		"nop		\n\t"
++		".set pop 	\n\t"
++		:
++		: "r" (restore_goto)
++		:
++		);
++}
++
++
++static noinline void cpu_sleep(void)
++{
++
++	TCSM_PCHAR('C');
++
++	sleep_param->cpu_div = cpm_inl(CPM_CPCCR) & 0xf;
++
++	blast_dcache32();
++	blast_scache32();
++	__sync();
++	__fast_iob();
++
++	{
++		/* before power down cpu by set PD in OPCR, reduce cpu's frequency as the same as L2C's freq */
++		unsigned int val, div;
++
++		/* change disable */
++		val = cpm_inl(CPM_CPCCR);
++		val &= ~(1 << 22);
++		cpm_outl(val, CPM_CPCCR);
++
++		/* div cpu = div l2c */
++		div = val & (0xf << 4);
++		val &= ~0xf;
++		val |= (div >> 4);
++		cpm_outl(val, CPM_CPCCR);
++
++		/* change enable */
++		val |= (1 << 22);
++		cpm_outl(val, CPM_CPCCR);
++
++		while (cpm_inl(CPM_CPCSR) & 1);
++	}
++
++	TCSM_PCHAR('D');
++
++
++	if (sleep_param->state == PM_SUSPEND_STANDBY) {
++		/* ddr auto clock gating */
++		*(volatile unsigned int *)0xb000002c |= (1 << 26);
++		*(volatile unsigned int *)0xb3012068 |= (1 << 31) | (1 << 28);
++	}
++
++	if (sleep_param->state == PM_SUSPEND_MEM) {
++		unsigned int tmp;
++		unsigned int ddrc_ctrl;
++
++		ddrc_ctrl = ddr_readl(DDRC_CTRL);
++
++		/* save ddr low power state */
++		sleep_param->pdt = ddrc_ctrl & DDRC_CTRL_PDT_MASK;
++		sleep_param->dpd = ddrc_ctrl & DDRC_CTRL_DPD;
++		sleep_param->dlp = ddr_readl(DDRC_DLP);
++		sleep_param->autorefresh = *(volatile unsigned int *)0xb3011304;
++
++		/* ddr disable deep power down */
++		ddrc_ctrl &= ~(DDRC_CTRL_PDT_MASK);
++		ddrc_ctrl &= ~(DDRC_CTRL_DPD);
++		ddr_writel(ddrc_ctrl, DDRC_CTRL);
++
++		/* ddr diasble LPEN*/
++		ddr_writel(0, DDRC_DLP);
++
++		/* ddr disable auto-sr */
++		*(volatile unsigned int *)0xb3011304 = 0;
++		tmp = *(volatile unsigned int *)0xa0000000;
++
++
++		/* DDR self refresh, */
++		ddrc_ctrl = ddr_readl(DDRC_CTRL);
++		ddrc_ctrl |= 1 << 5;
++		ddr_writel(ddrc_ctrl, DDRC_CTRL);
++		while(!(ddr_readl(DDRC_STATUS) & (1<<2)));
++
++
++		/* bufferen_core = 0 */
++		tmp = *(volatile unsigned int *)0xb3012034;
++		tmp |= (1 << 2);	//low
++		*(volatile unsigned int *)0xb3012034 = tmp;
++
++
++
++		/* dfi_init_start = 1 */
++		*(volatile unsigned int *)0xb301208c |= 1;
++
++		{
++			int i;
++			for (i = 0; i < 4; i++) {
++
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++			}
++		}
++
++		/* disable pll */
++		reg_ddr_phy(0x21) |= (1 << 1);
++	}
++
++	TCSM_PCHAR('W');
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"wait		\n\t"
++		"nop		\n\t"
++		"nop		\n\t"
++		"nop		\n\t"
++		".set pop	\n\t"
++	);
++
++	TCSM_PCHAR('N');
++
++	TCSM_PCHAR('\r');
++	TCSM_PCHAR('\n');
++	TCSM_PCHAR('?');
++	TCSM_PCHAR('?');
++	TCSM_PCHAR('?');
++	TCSM_PCHAR('\r');
++	TCSM_PCHAR('\n');
++
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"jr.hb %0	\n\t"
++		"nop		\n\t"
++		".set pop 	\n\t"
++		:
++		: "r" (SLEEP_CPU_RESUME_BOOTUP_TEXT)
++		:
++		);
++	TCSM_PCHAR('F');
++}
++
++
++int x1600_pm_enter(suspend_state_t state)
++{
++	extern volatile u8 *uart_base;
++	unsigned int r11s6;
++	unsigned int r16s6;
++
++
++	printk("x1600 pm enter!!\n");
++
++	*(volatile unsigned int *)0xb0000020 &= ~(1 << 21);
++	set_c0_status(0x100 << 2);
++
++	sleep_param->uart_base = (unsigned int)uart_base;
++
++	sleep_param->state = state;
++
++#ifdef DEBUG_PM
++	printk("sleep_param->state addr =  %d\n", sleep_param->state);
++#endif
++
++	load_func_to_tcsm((unsigned int *)SLEEP_CPU_RESUME_BOOTUP_TEXT, (unsigned int *)cpu_resume_bootup, SLEEP_CPU_RESUME_BOOTUP_LEN);
++	load_func_to_tcsm((unsigned int *)SLEEP_CPU_RESUME_TEXT, (unsigned int *)cpu_resume, SLEEP_CPU_RESUME_LEN);
++	load_func_to_tcsm((unsigned int *)SLEEP_CPU_SLEEP_TEXT, (unsigned int *)cpu_sleep, SLEEP_CPU_SLEEP_LEN);
++
++	if (state == PM_SUSPEND_STANDBY) {
++#ifdef X1600_IDLE_PD
++		soc_pm_idle_pd();
++#else
++		soc_pm_idle();
++#endif
++	} else if (state == PM_SUSPEND_MEM) {
++		soc_pm_sleep();
++	} else {
++		printk("WARNING : unsupport pm suspend state\n");
++	}
++
++
++	/* set reset entry */
++	r11s6 = __read_32bit_c0_register($11, 6);
++	__asm__ volatile("ehb\n\t");
++	r16s6 = __read_32bit_c0_register($16, 6);
++	__asm__ volatile("ehb\n\t");
++	r11s6 |= (1 << 8);
++	r16s6 &= ~0xfffff000;
++	r16s6 |= SLEEP_CPU_RESUME_BOOTUP_TEXT & 0xfffff000;
++	__write_32bit_c0_register($11, 6, r11s6);
++	__write_32bit_c0_register($16, 6, r16s6);
++
++
++	memory_pd_enter();
++
++#ifdef PM_TEST
++	pm_test_config();
++#endif
++
++#ifdef DEBUG_PM
++	printk("LCR: %08x\n", cpm_inl(CPM_LCR));
++	printk("OPCR: %08x\n", cpm_inl(CPM_OPCR));
++	x1600_pm_gate_check();
++	printk("mem_pd0 = 0x%x\n", *(volatile unsigned int *)0xb00000f8);
++	printk("mem_pd1 = 0x%x\n", *(volatile unsigned int *)0xb00000fc);
++	printk("intc0 mask = 0x%x\n", *(volatile unsigned int *)0xb0001004);
++	printk("intc1 mask = 0x%x\n", *(volatile unsigned int *)0xb0001024);
++#endif
++
++	mb();
++	save_goto((unsigned int)SLEEP_CPU_SLEEP_TEXT);
++	mb();
++
++	soc_post_wakeup();
++
++	return 0;
++}
++
++static int x1600_pm_begin(suspend_state_t state)
++{
++	printk("x1600 suspend begin\n");
++	return 0;
++}
++
++static void x1600_pm_end(void)
++{
++	printk("x1600 pm end!\n");
++}
++static int x1600_suspend_prepare(void)
++{
++	printk("x1600 suspend prepare\n");
++
++	return 0;
++}
++static void x1600_suspend_finish(void)
++{
++	printk("x1600 suspend finish");
++}
++
++static int ingenic_pm_valid(suspend_state_t state)
++{
++	switch (state) {
++		case PM_SUSPEND_ON:
++		case PM_SUSPEND_STANDBY:
++		case PM_SUSPEND_MEM:
++			return 1;
++
++		default:
++			return 0;
++	}
++}
++static const struct platform_suspend_ops x1600_pm_ops = {
++	.valid		= ingenic_pm_valid,
++	.begin		= x1600_pm_begin,
++	.enter		= x1600_pm_enter,
++	.end		= x1600_pm_end,
++	.prepare	= x1600_suspend_prepare,
++	.finish		= x1600_suspend_finish,
++};
++
++/*
++ * Initialize suspend interface
++ */
++static int __init pm_init(void)
++{
++
++	suspend_set_ops(&x1600_pm_ops);
++
++
++	return 0;
++}
++
++late_initcall(pm_init);
+diff --git a/arch/mips/xburst/soc-x1600/pm.h b/arch/mips/xburst/soc-x1600/pm.h
+new file mode 100644
+index 000000000..7be158159
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/pm.h
+@@ -0,0 +1,136 @@
++
++
++
++struct sleep_param {
++	suspend_state_t state;
++	unsigned int pdt;
++	unsigned int dpd;
++	unsigned int dlp;
++	unsigned int autorefresh;
++	unsigned int cpu_div;
++	unsigned int uart_base;
++};
++
++
++/*
++ *
++ *	|-----------------------|
++ *	|			|
++ *	|			|
++ *	|	RESUME_SP	|
++ *	|			|
++ *	|-----------------------|
++ *	|			|
++ *	|  	  PARAM		|
++ *	|			|
++ *	|-----------------------|
++ *	|			|
++ *	|			|
++ *	|	SLEEP_TEXT      |
++ *	|			|
++ *	|			|
++ *	|-----------------------|
++ *	|			|
++ *	|			|
++ *	|	RESUME_TEXT	|
++ *	|			|
++ *	|			|
++ *	|-----------------------|
++ *	|			|
++*	|  RESUME_BOOTU_TEXTP	|
++ *	|			|
++ *	|-----------------------|     <------------ TCSM_START 0xb3422000
++ *
++ */
++
++
++#define SLEEP_MEMORY_START		0xb3422000
++#define SLEEP_MEMORY_END		0xb3429ff8
++#define SLEEP_RESUME_SP			SLEEP_MEMORY_END
++#define SLEEP_RESUME_BOOTUP_TEXT	SLEEP_MEMORY_START
++
++#define SLEEP_CPU_RESUME_BOOTUP_TEXT	SLEEP_RESUME_BOOTUP_TEXT
++#define SLEEP_CPU_RESUME_BOOTUP_LEN	64 // 16 instructions
++#define SLEEP_CPU_RESUME_TEXT		(SLEEP_CPU_RESUME_BOOTUP_TEXT + SLEEP_CPU_RESUME_BOOTUP_LEN)
++#define SLEEP_CPU_RESUME_LEN		(4096)
++#define SLEEP_CPU_SLEEP_TEXT		(SLEEP_CPU_RESUME_TEXT + SLEEP_CPU_RESUME_LEN)
++#define SLEEP_CPU_SLEEP_LEN		(3072)
++#define SLEEP_CPU_PARAM_ADDR		(SLEEP_CPU_SLEEP_TEXT + SLEEP_CPU_SLEEP_LEN)
++#define SLEEP_CPU_PARAM_SIZE		(sizeof(struct sleep_param))
++#define SLEEP_CPU_RESUME_SP		SLEEP_RESUME_SP
++
++#define sleep_param ((struct sleep_param *)SLEEP_CPU_PARAM_ADDR)
++
++
++
++extern long long save_goto(unsigned int func);
++extern int restore_goto(unsigned int func);
++
++
++#define reg_ddr_phy(x)   (*(volatile unsigned int *)(0xb3011000 + ((x) << 2)))
++
++#define rtc_read_reg(reg) ({ \
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) ); \
++	*(volatile unsigned int *)reg;\
++})
++
++#define rtc_write_reg(reg, val) do{ \
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) ); \
++	*(volatile unsigned int *)0xb000303c = 0xa55a; \
++	while (!((*(volatile unsigned int *)0xb000303c >> 31) & 0x1) ); \
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) ); \
++	*(volatile unsigned int *)reg = val; \
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) ); \
++}while(0)
++
++
++
++
++/************************************************
++ *		debug interface
++ ***********************************************/
++
++#define DEBUG_PM
++#define PRINT_DEBUG
++
++
++#define U_IOBASE (sleep_param->uart_base)
++
++#define OFF_TDR         (0x00)
++#define OFF_LCR         (0x0C)
++#define OFF_LSR         (0x14)
++#define LSR_TDRQ        (1 << 5)
++#define LSR_TEMT        (1 << 6)
++
++
++#ifdef PRINT_DEBUG
++#define TCSM_PCHAR(x)                                                   \
++	*((volatile unsigned int*)(U_IOBASE+OFF_TDR)) = x;              \
++while ((*((volatile unsigned int*)(U_IOBASE + OFF_LSR)) & (LSR_TDRQ | LSR_TEMT)) != (LSR_TDRQ | LSR_TEMT))
++#else
++#define TCSM_PCHAR(x)
++#endif
++
++#define TCSM_DELAY(x)						\
++	do{							\
++	register unsigned int i = x;				\
++	while(i--)						\
++		__asm__ volatile("nop\n\t");			\
++	}while(0)
++
++static inline void serial_put_hex(unsigned int x) {
++	int i;
++	unsigned int d;
++	for(i = 7;i >= 0;i--) {
++		d = (x  >> (i * 4)) & 0xf;
++		if(d < 10) d += '0';
++		else d += 'A' - 10;
++		TCSM_PCHAR(d);
++	}
++	TCSM_PCHAR('\r');
++	TCSM_PCHAR('\n');
++}
++
++
++
++
+diff --git a/arch/mips/xburst/soc-x1600/regs_save_restore.S b/arch/mips/xburst/soc-x1600/regs_save_restore.S
+new file mode 100644
+index 000000000..abe8b49df
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/regs_save_restore.S
+@@ -0,0 +1,190 @@
++#include <asm/asm.h>
++#include <asm/regdef.h>
++
++#define CP0_PAGEMASK	$5,0
++#define CP0_STATUS	$12,0
++#define CP0_INTCTL	$12,1
++#define CP0_CAUSE	$13,0
++#define CP0_EBASE	$15,1
++#define CP0_CONFIG	$16,0
++#define CP0_CONFIG1	$16,1
++#define CP0_CONFIG2	$16,2
++#define CP0_CONFIG3	$16,3
++#define CP0_CONFIG4	$16,4
++#define CP0_CONFIG5	$16,5
++#define CP0_CONFIG7	$16,7
++#define CP0_LLADDR	$17,0
++#define CP0_WATCHLo	$18,0
++#define CP0_WATCHHI	$19,0
++#define CP0_ERRCTL	$26,0
++#define CP0_CONTEXT	$4,0
++#define CP0_KSCRATCH1	$31,2
++#define CP0_KSCRATCH2	$31,3
++#define CP0_KSCRATCH3	$31,4
++#define CP0_KSCRATCH4	$31,5
++#define CP0_KSCRATCH5	$31,6
++#define CP0_KSCRATCH6	$31,7
++
++	.data
++	.global _regs_stack
++_regs_stack:
++	.align 5
++	.space 140,0
++
++	.text
++	.global save_goto
++	.align 2
++	.ent save_goto,0
++	LEAF(save_goto)
++save_goto:
++	.set	push
++	.set	noreorder
++	.set	noat
++
++	la	k0, _regs_stack
++	sw	s0,0(k0)
++	sw	s1,4(k0)
++	sw	s2,8(k0)
++	sw	s3,12(k0)
++	sw	s4,16(k0)
++	sw	s5,20(k0)
++	sw	s6,24(k0)
++	sw	s7,28(k0)
++	sw	gp,32(k0)
++	sw	sp,36(k0)
++	sw	fp,40(k0)
++	sw	ra,44(k0)
++
++	mfc0	k1,CP0_PAGEMASK
++	sw	k1,48(k0)
++	mfc0	k1,CP0_STATUS
++	sw	k1,52(k0)
++	mfc0	k1,CP0_INTCTL
++	sw	k1,56(k0)
++	mfc0	k1,CP0_CAUSE
++	sw	k1,60(k0)
++	mfc0	k1,CP0_EBASE
++	sw	k1,64(k0)
++	mfc0	k1,CP0_CONFIG
++	sw	k1,68(k0)
++	mfc0	k1,CP0_CONFIG1
++	sw	k1,72(k0)
++	mfc0	k1,CP0_CONFIG2
++	sw	k1,76(k0)
++	mfc0	k1,CP0_CONFIG3
++	sw	k1,80(k0)
++	mfc0	k1,CP0_CONFIG4
++	sw	k1,84(k0)
++	mfc0	k1,CP0_CONFIG5
++	sw	k1,88(k0)
++	mfc0	k1,CP0_CONFIG7
++	sw	k1,92(k0)
++	mfc0	k1,CP0_LLADDR
++	sw	k1,96(k0)
++	mfc0	k1,CP0_WATCHLo
++	sw	k1,100(k0)
++	mfc0	k1,CP0_WATCHHI
++	sw	k1,104(k0)
++	mfc0	k1,CP0_ERRCTL
++	sw	k1,108(k0)
++	mfc0	k1,CP0_CONTEXT
++	sw	k1,112(k0)
++	mfc0	k1,CP0_KSCRATCH1
++	sw	k1,116(k0)
++	mfc0	k1,CP0_KSCRATCH2
++	sw	k1,120(k0)
++	mfc0	k1,CP0_KSCRATCH3
++	sw	k1,124(k0)
++	mfc0	k1,CP0_KSCRATCH4
++	sw	k1,128(k0)
++	mfc0	k1,CP0_KSCRATCH5
++	sw	k1,132(k0)
++	mfc0	k1,CP0_KSCRATCH6
++	sw	k1,136(k0)
++
++	jr.hb	a0
++	nop
++
++	.set	at
++	.set	reorder
++	.set	pop
++	END(save_goto)
++
++	.text
++	.global restore_goto
++	.align 2
++	.ent restore_goto,0
++	LEAF(restore_goto)
++restore_goto:
++	.set	push
++	.set	noreorder
++	.set	noat
++
++	la	k0, _regs_stack
++	lw	s0,0(k0)
++	lw	s1,4(k0)
++	lw	s2,8(k0)
++	lw	s3,12(k0)
++	lw	s4,16(k0)
++	lw	s5,20(k0)
++	lw	s6,24(k0)
++	lw	s7,28(k0)
++	lw	gp,32(k0)
++	lw	sp,36(k0)
++	lw	fp,40(k0)
++	lw	ra,44(k0)
++
++	lw	k1,48(k0)
++	mtc0	k1,CP0_PAGEMASK
++	lw	k1,52(k0)
++	mtc0	k1,CP0_STATUS
++	lw	k1,56(k0)
++	mtc0	k1,CP0_INTCTL
++	lw	k1,60(k0)
++	mtc0	k1,CP0_CAUSE
++	lw	k1,64(k0)
++	mtc0	k1,CP0_EBASE
++	lw	k1,68(k0)
++	mtc0	k1,CP0_CONFIG
++	lw	k1,72(k0)
++	mtc0	k1,CP0_CONFIG1
++	lw	k1,76(k0)
++	mtc0	k1,CP0_CONFIG2
++	lw	k1,80(k0)
++	mtc0	k1,CP0_CONFIG3
++	lw	k1,84(k0)
++	mtc0	k1,CP0_CONFIG4
++	lw	k1,88(k0)
++	mtc0	k1,CP0_CONFIG5
++	lw	k1,92(k0)
++	mtc0	k1,CP0_CONFIG7
++	lw	k1,96(k0)
++	mtc0	k1,CP0_LLADDR
++	lw	k1,100(k0)
++	mtc0	k1,CP0_WATCHLo
++	lw	k1,104(k0)
++	mtc0	k1,CP0_WATCHHI
++	lw	k1,108(k0)
++	mtc0	k1,CP0_ERRCTL
++	lw	k1,112(k0)
++	mtc0	k1,CP0_CONTEXT
++	lw	k1,116(k0)
++	mtc0	k1,CP0_KSCRATCH1
++	lw	k1,120(k0)
++	mtc0	k1,CP0_KSCRATCH2
++	lw	k1,124(k0)
++	mtc0	k1,CP0_KSCRATCH3
++	lw	k1,128(k0)
++	mtc0	k1,CP0_KSCRATCH4
++	lw	k1,132(k0)
++	mtc0	k1,CP0_KSCRATCH5
++	lw	k1,136(k0)
++	mtc0	k1,CP0_KSCRATCH6
++
++	jr.hb	ra
++	nop
++
++	.set	at
++	.set	reorder
++	.set	pop
++	END(restore_goto)
+diff --git a/arch/mips/xburst/soc-x1600/regs_save_restore.py b/arch/mips/xburst/soc-x1600/regs_save_restore.py
+new file mode 100755
+index 000000000..df57fff6e
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/regs_save_restore.py
+@@ -0,0 +1,123 @@
++#!/usr/bin/env python
++import os
++import string
++
++common_regs=["s0","s1","s2","s3",
++        "s4","s5","s6","s7",
++        "gp","sp","fp","ra"]
++cp0_regs=[
++        ["CP0_PAGEMASK","$5","0"],
++        ["CP0_STATUS","$12","0"],
++        ["CP0_INTCTL","$12","1"],
++        ["CP0_CAUSE","$13","0"],
++        ["CP0_EBASE","$15","1"],
++        ["CP0_CONFIG","$16","0"],
++        ["CP0_CONFIG1","$16","1"],
++        ["CP0_CONFIG2","$16","2"],
++        ["CP0_CONFIG3","$16","3"],
++		["CP0_CONFIG4", "$16", "4"],
++		["CP0_CONFIG5", "$16", "5"],
++        ["CP0_CONFIG7","$16","7"],
++        ["CP0_LLADDR","$17","0"],
++        ["CP0_WATCHLo","$18","0"],
++        ["CP0_WATCHHI","$19","0"],
++        ["CP0_ERRCTL","$26","0"],
++        ["CP0_CONTEXT","$4","0"],
++        ["CP0_KSCRATCH1","$31","2"],
++        ["CP0_KSCRATCH2","$31","3"],
++        ["CP0_KSCRATCH3","$31","4"],
++        ["CP0_KSCRATCH4","$31","5"],
++        ["CP0_KSCRATCH5","$31","6"],
++        ["CP0_KSCRATCH6","$31","7"],
++        ]
++def gen_get_array_size():
++    size=0
++    size+=len(common_regs)
++    size+=len(cp0_regs)
++    return size
++
++def gen_print_head_and_macro():
++    print("#include <asm/asm.h>")
++    print("#include <asm/regdef.h>")
++    print("")
++    for s in cp0_regs:
++        print("#define %s\t%s,%s" %(s[0],s[1],s[2]))
++    print("")
++def gen_define_global_arg(str, num):
++    print("\t.data")
++    print("\t.global %s" %(str))
++    print("%s:" %(str))
++    print("\t.align 5")
++    print("\t.space %s,0" %(num))
++    print("")
++
++def gen_save_common_regs(index):
++    for s in common_regs:
++        print("\tsw\t%s,%d(k0)" % (s,index))
++        index=index+4
++    return index
++def gen_restore_common_regs(index):
++    for s in common_regs:
++        print("\tlw\t%s,%d(k0)" % (s,index))
++        index=index+4
++    return index
++def gen_save_cp0_regs(index):
++    for s in cp0_regs:
++        print("\tmfc0\tk1,%s" % (s[0]))
++        print("\tsw\tk1,%d(k0)" % (index))
++        index=index+4
++    return index
++def gen_restore_cp0_regs(index):
++    for s in cp0_regs:
++        print("\tlw\tk1,%d(k0)" % (index))
++        print("\tmtc0\tk1,%s" % (s[0]))
++        index=index+4
++    return index
++def gen_print_function(f_name, regs_stack):
++    index=0
++    print("\t.text")
++    print("\t.global %s" %(f_name))
++    print("\t.align 2")
++    print("\t.ent %s,0" %(f_name))
++    print("%s:" %(f_name))
++    print("\t.set\tpush")
++    print("\t.set\tnoreorder")
++    print("\t.set\tnoat")
++    print("")
++    print("\tla\tk0, %s" %(regs_stack))
++    if f_name == "save_goto":
++        index = gen_save_common_regs(index)
++        print("")
++        index = gen_save_cp0_regs(index)
++        print("")
++        print("\tjr.hb\ta0")
++        print("\tnop")
++    elif f_name == "restore_goto":
++        index = gen_restore_common_regs(index)
++        print("")
++        index = gen_restore_cp0_regs(index)
++        print("")
++        print("\tjr.hb\tra")
++        print("\tnop")
++    else:
++        print("not support")
++    print("")
++    print("\t.set\tat")
++    print("\t.set\treorder")
++    print("\t.set\tpop")
++    print("\tEND(%s)" %(f_name))
++
++
++def main():
++    regs_size=gen_get_array_size()
++    regs_size*=4
++
++    gen_print_head_and_macro()
++    gen_define_global_arg("_regs_stack", regs_size)
++    gen_print_function("save_goto", "_regs_stack")
++    print("")
++    gen_print_function("restore_goto", "_regs_stack")
++    pass
++
++if __name__ == '__main__':
++    main()
+diff --git a/arch/mips/xburst/soc-x1600/setup.c b/arch/mips/xburst/soc-x1600/setup.c
+new file mode 100644
+index 000000000..ef88c0816
+--- /dev/null
++++ b/arch/mips/xburst/soc-x1600/setup.c
+@@ -0,0 +1,93 @@
++/*
++ * INGENIC SOC Setup
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2006 Ingenic Semiconductor Inc.
++ */
++#include <linux/module.h>
++#include <linux/of_fdt.h>
++#include <linux/of_platform.h>
++#include <linux/irqchip.h>
++#include <linux/libfdt.h>
++#include <linux/clk-provider.h>
++#include <linux/clocksource.h>
++#include <asm/prom.h>
++#include <soc/cpm.h>
++#include <soc/base.h>
++
++
++extern void *get_fdt_addr(void);
++
++
++static void __init cpm_reset(void)
++{
++#ifndef CONFIG_FPGA_TEST
++        unsigned long clkgr = cpm_inl(CPM_CLKGR);
++
++        clkgr &= ~(1 << 28      /* DES */
++                | 1 << 26       /* TVE */
++                | 1 << 13       /* SADC */
++                );
++        cpm_outl(clkgr, CPM_CLKGR);
++
++        /* TODO set default clkgr here */
++#endif
++}
++
++static int __init setup_init(void)
++{
++        cpm_reset();
++        /* Set bus priority here */
++        *(volatile unsigned int *)0xb34f0240 = 0x00010003;
++        *(volatile unsigned int *)0xb34f0244 = 0x00010003;
++
++        return 0;
++}
++
++
++void __init plat_mem_setup(void)
++{
++
++	set_io_port_base(IO_BASE);
++
++	/*Not have ioport*/
++	ioport_resource.start   = 0x00000000;
++	ioport_resource.end     = 0xffffffff;
++	iomem_resource.start    = 0x00000000;
++	iomem_resource.end      = 0xffffffff;
++
++	setup_init();
++
++	__dt_setup_arch(get_fdt_addr());
++
++	early_init_fdt_scan_reserved_mem();
++
++	return;
++}
++
++void __init device_tree_init(void)
++{
++	unflatten_and_copy_device_tree();
++}
++
++static int __init plat_of_populate(void)
++{
++	of_platform_default_populate(NULL, NULL, NULL);
++	return 0;
++}
++arch_initcall(plat_of_populate);
++
++void __init plat_time_init(void)
++{
++	of_clk_init(NULL);
++
++	timer_probe();
++}
++
++void __init arch_init_irq(void) {
++
++	irqchip_init();
++}
+diff --git a/arch/mips/xburst2/Kconfig b/arch/mips/xburst2/Kconfig
+new file mode 100644
+index 000000000..4195dfd71
+--- /dev/null
++++ b/arch/mips/xburst2/Kconfig
+@@ -0,0 +1,105 @@
++if MACH_XBURST2
++
++menu "SOC Type Selection"
++	depends on MACH_XBURST2
++
++
++choice
++	prompt "SOC types"
++	depends on MACH_XBURST2
++	default SOC_X2000
++
++config SOC_X2000
++	bool "x2000"
++	select IRQ_INGENIC_CPU
++	select CLK_X2000
++	select INGENIC_INTC_CHIP
++	select PINCTRL
++	select PINCTRL_INGENIC_V2
++	select TIMER_OF
++	select CLKDEV_LOOKUP
++	select CLKSRC_INGENIC_CORE_OST
++	select MMU_NOTIFIER
++
++config SOC_X2500
++	bool "x2500"
++	select IRQ_INGENIC_CPU
++	select CLK_X2500
++	select INGENIC_INTC_CHIP
++	select PINCTRL
++	select PINCTRL_INGENIC_V2
++	select TIMER_OF
++	select CLKDEV_LOOKUP
++	select CLKSRC_INGENIC_CORE_OST
++	select MMU_NOTIFIER
++
++config SOC_M300
++	bool "m300"
++	select IRQ_INGENIC_CPU
++	select CLK_M300
++	select INGENIC_INTC_CHIP
++	select PINCTRL
++	select PINCTRL_INGENIC_V2
++	select TIMER_OF
++	select CLKDEV_LOOKUP
++	select CLKSRC_INGENIC_CORE_OST
++	select MMU_NOTIFIER
++
++config SOC_X2100
++	bool "x2100"
++	select IRQ_INGENIC_CPU
++	select CLK_X2100
++	select INGENIC_INTC_CHIP
++	select PINCTRL
++	select PINCTRL_INGENIC_V2
++	select TIMER_OF
++	select CLKDEV_LOOKUP
++	select CLKSRC_INGENIC_CORE_OST
++	select MMU_NOTIFIER
++
++endchoice
++
++config INGENIC_BUILTIN_DTB
++	select BUILTIN_DTB
++	depends on MACH_XBURST2
++	bool "Ingenic Device Tree build into Kernel."
++	default y
++
++source "arch/mips/xburst2/soc-x2000/Kconfig.DT"
++source "arch/mips/xburst2/soc-x2500/Kconfig.DT"
++source "arch/mips/xburst2/soc-m300/Kconfig.DT"
++
++
++config RAW_BOOT
++	bool "Raw Boot Kernel"
++	select BOOT_RAW
++	default n
++
++config EXTAL_CLOCK
++	depends on MACH_XBURST2
++	int "extal clock in MHz"
++	default 24
++
++config FPGA_TEST
++	depends on MACH_XBURST2
++	bool "FPGA_TEST"
++	default n
++
++config INGENIC_GPT_CHECK
++	depends on MACH_XBURST2
++	bool "The physical space is larger than the virtual space"
++	default y
++
++config XBURST2_CPU_TEST
++	depends on MACH_XBURST2
++	bool "xburst2 cpu ddr test"
++	default n
++
++
++config FASTBOOT
++	bool "FastBoot"
++	depends on SOC_X2000 || SOC_M300 || SOC_X2100
++
++endmenu
++
++endif
+diff --git a/arch/mips/xburst2/Makefile b/arch/mips/xburst2/Makefile
+new file mode 100644
+index 000000000..77dcad13f
+--- /dev/null
++++ b/arch/mips/xburst2/Makefile
+@@ -0,0 +1,7 @@
++obj-y			+= core/
++obj-y			+= common/
++
++obj-$(CONFIG_SOC_X2000) += soc-x2000/
++obj-$(CONFIG_SOC_X2500) += soc-x2500/
++obj-$(CONFIG_SOC_M300) += soc-m300/
++obj-$(CONFIG_SOC_X2100) += soc-x2000/
+diff --git a/arch/mips/xburst2/Platform b/arch/mips/xburst2/Platform
+new file mode 100644
+index 000000000..cba9ceb7e
+--- /dev/null
++++ b/arch/mips/xburst2/Platform
+@@ -0,0 +1,7 @@
++load-$(CONFIG_MACH_XBURST2)	+= 0xffffffff80010000
++cflags-$(CONFIG_MACH_XBURST2)	+= -I$(srctree)/arch/mips/xburst2/core/include
++
++cflags-$(CONFIG_SOC_X2000)	+= -I$(srctree)/arch/mips/xburst2/soc-x2000/include
++cflags-$(CONFIG_SOC_X2500)	+= -I$(srctree)/arch/mips/xburst2/soc-x2500/include
++cflags-$(CONFIG_SOC_M300)	+= -I$(srctree)/arch/mips/xburst2/soc-m300/include
++cflags-$(CONFIG_SOC_X2100)	+= -I$(srctree)/arch/mips/xburst2/soc-x2000/include
+diff --git a/arch/mips/xburst2/common/Makefile b/arch/mips/xburst2/common/Makefile
+new file mode 100644
+index 000000000..52af9c04a
+--- /dev/null
++++ b/arch/mips/xburst2/common/Makefile
+@@ -0,0 +1,11 @@
++
++# add object if need
++
++#obj-y += prom.o
++obj-y += get-cpu-features.o
++#obj-y += proc-exec.o
++obj-y += proc.o
++obj-y += mxuv3.o
++#obj-y += jz_notifier.o
++obj-$(CONFIG_XBURST2_CPU_TEST) += cpu_ddr_test/
++#obj-y += initrd-check.o
+diff --git a/arch/mips/xburst2/common/cpu_ddr_test/Makefile b/arch/mips/xburst2/common/cpu_ddr_test/Makefile
+new file mode 100644
+index 000000000..325683434
+--- /dev/null
++++ b/arch/mips/xburst2/common/cpu_ddr_test/Makefile
+@@ -0,0 +1,11 @@
++
++obj-y += multithread_test.o
++obj-y += ddr_bandwidth_monitor.o
++obj-y += ddr_change_freq.o
++obj-y += l2c_test.o
++obj-y += cpu_spinlock_test.o
++obj-y += cpu_ccu_test.o
++obj-y += raw_dma_test.o
++obj-y += cpu_dma_test.o
++obj-y += cpu_watch_test.o
++ccflags-y += -Wno-unused-function
+diff --git a/arch/mips/xburst2/common/cpu_ddr_test/cpu_ccu_test.c b/arch/mips/xburst2/common/cpu_ddr_test/cpu_ccu_test.c
+new file mode 100644
+index 000000000..62d34e66f
+--- /dev/null
++++ b/arch/mips/xburst2/common/cpu_ddr_test/cpu_ccu_test.c
+@@ -0,0 +1,70 @@
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/syscore_ops.h>
++#include <linux/slab.h>
++#include <linux/debugfs.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/dma-mapping.h>
++#include <linux/kthread.h>
++#include <linux/delay.h>
++#include <linux/random.h>
++#include <linux/vmalloc.h>
++#include <linux/list.h>
++
++#include "multithread_test.h"
++#include <ccu.h>
++
++#define PALLADIUM_TRIGER_2()	do {\
++	volatile unsigned int *a; \
++	a = (unsigned int *)0xAFFFFFFC; \
++	*a = *a; \
++	} while(0)
++
++struct cpu_ccu_test {
++	void* multithread;
++	unsigned int cnt;
++} cpu_ccu;
++
++
++static int cpu_ccu_test_func(void * param)
++{
++	struct cpu_ccu_test *p = (struct cpu_ccu_test *)param;
++	unsigned int cscr, cssr, csrr, rer;
++
++	cscr = get_ccu_cscr();
++
++	cssr = get_ccu_cssr();
++
++	csrr = get_ccu_csrr();
++
++	rer = get_ccu_rer();
++
++	p->cnt++;
++
++	if(p->cnt == 1000) {
++		p->cnt = 0;
++		printk("%s: cscr=0x%08x, cssr=0x%08x, csrr=0x%08x, rer=0x%08x\n", __func__, cscr, cssr, csrr, rer);
++	}
++#ifdef CONFIG_FPGA_TEST
++	mdelay(100);
++#endif
++	return 0;
++}
++
++static int __init cpu_ccu_test_init(void)
++{
++	cpu_ccu.multithread = multithread_test_init("cpu_ccu_test",1);
++
++	if(cpu_ccu.multithread){
++		multithread_test_add_func(cpu_ccu.multithread,"cpu_ccu_test",cpu_ccu_test_func,(void*)&cpu_ccu);
++	}
++	return 0;
++}
++static void __exit cpu_ccu_test_deinit(void)
++{
++}
++
++late_initcall(cpu_ccu_test_init);
++module_exit(cpu_ccu_test_deinit);
+diff --git a/arch/mips/xburst2/common/cpu_ddr_test/cpu_dma_test.c b/arch/mips/xburst2/common/cpu_ddr_test/cpu_dma_test.c
+new file mode 100644
+index 000000000..68b428034
+--- /dev/null
++++ b/arch/mips/xburst2/common/cpu_ddr_test/cpu_dma_test.c
+@@ -0,0 +1,269 @@
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/syscore_ops.h>
++#include <linux/slab.h>
++#include <linux/debugfs.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/dma-mapping.h>
++#include <linux/kthread.h>
++#include <linux/delay.h>
++#include <linux/random.h>
++//#include <mach/jzdma_v13.h>
++#include <linux/vmalloc.h>
++#include <linux/list.h>
++
++#include "multithread_test.h"
++#include "../../../../../drivers/dma/ingenic/ingenic_dma.h"
++
++struct cpu_dma_test{
++	void* multithread;
++	struct list_head dma_top;
++}cpu_dma;
++struct dma_channel {
++	struct list_head list;
++	struct dma_chan	*chan;
++	struct hdma_desc *desc;
++	void *from;
++	unsigned long pfrom;
++	void *to;
++	unsigned long pto;
++	unsigned long test_len;
++	struct mutex	lock;
++	unsigned long test_cnt;
++};
++static void init_buf(struct dma_channel *dc)
++{
++	int i;
++
++	unsigned long *p = dc->from;
++	struct device *dev;
++	dev = (struct device *)kzalloc(sizeof(struct device), GFP_KERNEL);
++	for(i = 0;i < dc->test_len/4;i++){
++		p[i] = (unsigned int)p + i * 4;
++	}
++
++	p = dc->to;
++	for(i = 0;i < dc->test_len/4;i++){
++		p[i] = 0x5a5a5a5a;
++	}
++	dma_cache_sync(dev,dc->from,dc->test_len,DMA_TO_DEVICE);
++	dma_cache_sync(dev,dc->to,dc->test_len,DMA_FROM_DEVICE);
++}
++
++static int cpu_dma_test_func_nowait(void * param)
++{
++	struct dma_channel *dc = (struct dma_channel *)param;
++	int i;
++	mutex_lock(&dc->lock);
++	init_buf(dc);
++	{
++		struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(dc->chan);
++		writel((unsigned int)virt_to_phys(dc->desc), dmac->iomem + CH_DDA);
++		/* initiate descriptor fetch */
++		writel(BIT(dmac->id), dmac->engine->iomem + DDRS);
++		writel(1 | (1 << 30),dmac->iomem + CH_DCS);
++	}
++
++	dc->test_cnt ++;
++	{
++		volatile unsigned long *p = (unsigned long *)CKSEG1ADDR(dc->to);
++		unsigned long e = (unsigned long)dc->from;
++		int timeout = 0x10000;
++		for(i = 0;i < dc->test_len/4;i++){
++			timeout = 0x10000;
++			while((p[i] != e) && --timeout);
++			if(timeout==0){
++				printk("xxxxxx error data is not ready! xxxxxx\n");
++				while(1);
++			}
++			e += 4;
++		}
++	}
++	mutex_unlock(&dc->lock);
++#ifdef CONFIG_FPGA_TEST
++	mdelay(100);
++#endif
++	return 0;
++}
++static int cpu_dma_test_func_wait(void * param)
++{
++	struct dma_channel *dc = (struct dma_channel *)param;
++	unsigned long *p = (unsigned long*)((unsigned long)dc->to + dc->test_len - 4);
++	unsigned long e = (unsigned long)dc->from + dc->test_len - 4;
++	unsigned long r;
++	int timeout = 0x10000;
++
++	struct device *dev;
++	dev = (struct device *)kzalloc(sizeof(struct device), GFP_KERNEL);
++
++	mutex_lock(&dc->lock);
++	init_buf(dc);
++	{
++		struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(dc->chan);
++
++		writel((unsigned int)virt_to_phys(dc->desc), dmac->iomem + CH_DDA);
++		/* initiate descriptor fetch */
++		writel(BIT(dmac->id), dmac->engine->iomem + DDRS);
++		writel(1 | (1 << 30),dmac->iomem + CH_DCS);
++		while(!(readl(dmac->iomem + CH_DCS) & (1 << 3)) && timeout--);
++	}
++
++	dc->test_cnt ++;
++
++	{
++		do
++		{
++			r = *p;
++			if(r != e){
++				unsigned long *uc = (unsigned long *)((unsigned long)p | 0xa0000000);
++
++				printk("error:from:%px to: %px data[%px] real: 0x%08lx, uc:0x%08lx expect: 0x%08lx, test_cnt: %ld\n",
++					dc->from, dc->to, p,r, *uc, e, dc->test_cnt);
++				break;
++			}
++			p--;
++			e -= 4;
++		}while((unsigned long)p != (unsigned long)dc->to - 4);
++	}
++	if(timeout==0){
++		printk("xxxxxx error dmac is not ready! xxxxxx\n");
++		while(1);
++	}
++
++	mutex_unlock(&dc->lock);
++#ifdef CONFIG_FPGA_TEST
++	mdelay(100);
++#endif
++	return 0;
++}
++static bool filter(struct dma_chan *chan, void *param)
++{
++#if 0
++	if (!((unsigned int)chan->private == 8))
++		return false;
++#endif
++	return true;
++}
++const static char dcm_tsz[8] = { 1, 2, 0, 0, 3, 4, 5, 6 };
++static inline unsigned int get_max_tsz(unsigned long val, unsigned long *dcmp)
++{
++
++	int ord;
++
++	ord = ffs(val) - 1;
++	if (ord < 0)
++		ord = 0;
++	else if (ord > 7)
++		ord = 7;
++
++	*dcmp &= ~DCM_TSZ_MSK;
++	*dcmp |= dcm_tsz[ord] << DCM_TSZ_SFT;
++
++	/* if tsz == 8, set it to 4 */
++	return ord == 3 ? 4 : 1 << ord;
++}
++static struct dma_channel *new_dma_channel(struct cpu_dma_test* cd)
++{
++	struct dma_channel *ch;
++	struct device *dev;
++	dev = (struct device *)kzalloc(sizeof(struct device), GFP_KERNEL);
++	ch = (struct dma_channel *)vmalloc(sizeof(struct dma_channel));
++	memset(ch,0,sizeof(struct dma_channel));
++	if(ch == NULL){
++		printk("mem alloc failed! %s %d\n",__FILE__,__LINE__);
++		return 0;
++	}
++
++	mutex_init(&ch->lock);
++
++	ch->test_len = 4096;
++	ch->from = (void *)kmalloc(ch->test_len,GFP_KERNEL);
++	ch->to = (void *)kmalloc(ch->test_len,GFP_KERNEL);
++	if(ch->to == 0 || ch->from == 0){
++		printk("mem alloc failed! %s %d\n",__FILE__,__LINE__);
++		goto error_exit;
++	}
++	ch->pfrom = virt_to_phys(ch->from);
++	ch->pto = virt_to_phys(ch->to);
++
++	{
++		dma_cap_mask_t mask;
++		struct hdma_desc *desc;
++		unsigned long burst_len = 128;
++		unsigned long burst_bits = 0;
++		dma_cap_zero(mask);
++		dma_cap_set(DMA_MEMCPY, mask);
++		ch->chan = dma_request_channel(mask, filter, 0);
++		if (!ch->chan) {
++			printk("dma channel request failed! %s %d\n",__FILE__,__LINE__);
++			goto error_exit;
++		}
++		ch->desc = (struct hdma_desc *)kmalloc(128,GFP_KERNEL);
++		if(!ch->desc){
++			printk("dma channel request desc failed! %s %d\n",__FILE__,__LINE__);
++			goto error_exit;
++		}
++		desc = ch->desc;
++		burst_len = get_max_tsz(burst_len,&burst_bits);
++		desc->dcm = DCM_SAI | DCM_DAI | burst_bits;
++		desc->dsa = ch->pfrom;
++		desc->dta = ch->pto;
++		desc->dtc = ch->test_len / burst_len;
++		desc->drt = 8;
++		dma_cache_sync(dev,desc,128,DMA_TO_DEVICE);
++	}
++
++	list_add_tail(&ch->list,&cd->dma_top);
++	return ch;
++error_exit:
++	if(ch->desc)
++		kfree(ch->desc);
++	if(ch->from)
++		kfree(ch->from);
++	if(ch->to)
++		kfree(ch->to);
++	vfree(ch);
++	return 0;
++}
++static void free_dma_channel(struct dma_channel *dc)
++{
++	if(dc->desc)
++		kfree(dc->desc);
++	if(dc->from)
++		kfree(dc->from);
++	if(dc->to)
++		kfree(dc->to);
++	vfree(dc);
++}
++static int __init cpu_dma_test_init(void)
++{
++	struct dma_channel *dc;
++	INIT_LIST_HEAD(&cpu_dma.dma_top);
++	cpu_dma.multithread = multithread_test_init("cpu_dma_test",2);
++	if(cpu_dma.multithread){
++		dc = new_dma_channel(&cpu_dma);
++		if(dc)
++			multithread_test_add_func(cpu_dma.multithread,"cpu-dma-nowait",cpu_dma_test_func_nowait,(void*)dc);
++
++		dc = new_dma_channel(&cpu_dma);
++		if(dc)
++			multithread_test_add_func(cpu_dma.multithread,"cpu-dma-wait",cpu_dma_test_func_wait,(void*)dc);
++
++		printk("cpu_dma_test register ok.\n");
++	}
++	return 0;
++}
++static void __exit cpu_dma_test_deinit(void)
++{
++	struct dma_channel *dc,*_dc;
++
++	list_for_each_entry_safe(dc, _dc, &cpu_dma.dma_top, list) {
++		list_del(&dc->list);
++		free_dma_channel(dc);
++	}
++	multithread_test_deinit(cpu_dma.multithread);
++}
++late_initcall(cpu_dma_test_init);
++module_exit(cpu_dma_test_deinit);
+diff --git a/arch/mips/xburst2/common/cpu_ddr_test/cpu_spinlock_test.c b/arch/mips/xburst2/common/cpu_ddr_test/cpu_spinlock_test.c
+new file mode 100644
+index 000000000..e6773ab5d
+--- /dev/null
++++ b/arch/mips/xburst2/common/cpu_ddr_test/cpu_spinlock_test.c
+@@ -0,0 +1,75 @@
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/syscore_ops.h>
++#include <linux/slab.h>
++#include <linux/debugfs.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/dma-mapping.h>
++#include <linux/kthread.h>
++#include <linux/delay.h>
++#include <linux/random.h>
++#include <linux/vmalloc.h>
++#include <linux/list.h>
++
++#include "multithread_test.h"
++
++#define PALLADIUM_TRIGER_2()	do {\
++	volatile unsigned int *a; \
++	a = (unsigned int *)0xAFFFFFFC; \
++	*a = *a; \
++	} while(0)
++
++struct cpu_spinlock_test {
++	void* multithread;
++	spinlock_t lock;
++	unsigned int cnt;
++	atomic_t acnt;
++} cpu_spinlock;
++
++
++static int cpu_spinlock_test_func(void * param)
++{
++	struct cpu_spinlock_test *p = (struct cpu_spinlock_test *)param;
++	unsigned int c;
++
++	spin_lock(&p->lock);
++
++#if 1
++	c = atomic_read(&p->acnt);
++	if(p->cnt != c) {
++	//	PALLADIUM_TRIGER_2();
++		printk("========= spinlock cnt %x != atomic cnt, %x\n",p->cnt, c);
++		return -1;
++	}
++#endif
++	p->cnt++;
++
++	udelay(10);
++
++	atomic_inc(&p->acnt);
++	spin_unlock(&p->lock);
++
++#ifdef CONFIG_FPGA_TEST
++	mdelay(100);
++#endif
++	return 0;
++}
++
++static int __init cpu_spinlock_test_init(void)
++{
++	cpu_spinlock.multithread = multithread_test_init("cpu_spinlock_test",1);
++	spin_lock_init(&cpu_spinlock.lock);
++
++	if(cpu_spinlock.multithread){
++		multithread_test_add_func(cpu_spinlock.multithread,"cpu_spinlock_test",cpu_spinlock_test_func,(void*)&cpu_spinlock);
++	}
++	return 0;
++}
++static void __exit cpu_spinlock_test_deinit(void)
++{
++}
++
++late_initcall(cpu_spinlock_test_init);
++module_exit(cpu_spinlock_test_deinit);
+diff --git a/arch/mips/xburst2/common/cpu_ddr_test/cpu_tcsm.h b/arch/mips/xburst2/common/cpu_ddr_test/cpu_tcsm.h
+new file mode 100644
+index 000000000..4d3466812
+--- /dev/null
++++ b/arch/mips/xburst2/common/cpu_ddr_test/cpu_tcsm.h
+@@ -0,0 +1,16 @@
++#ifndef __CPU_TCSM_H__
++#define __CPU_TCSM_H__
++
++#define CPU_TCSM_BASE (0xb2400000)
++
++#define CPU_TCSM_BANK0 CPU_TCSM_BASE
++#define CPU_TCSM_BANK0_SIZE (4096)
++#define CPU_TCSM_FUNC  CPU_TCSM_BANK0
++#define CPU_TCSM_FUNC_SIZE  2048
++#define CPU_TCSM_DATA  (CPU_TCSM_FUNC + CPU_TCSM_FUNC_SIZE)
++#define CPU_TCSM_SP  (CPU_TCSM_BANK0 + CPU_TCSM_BANK0_SIZE)
++
++#define CPU_TCSM_DDR_CALIB (CPU_TCSM_DATA)
++#define CPU_TCSM_CPU_WAIT_STATUS (CPU_TCSM_DDR_CALIB + 0x4)
++
++#endif	/* __CPU_TCSM_H__ */
+diff --git a/arch/mips/xburst2/common/cpu_ddr_test/cpu_watch_test.c b/arch/mips/xburst2/common/cpu_ddr_test/cpu_watch_test.c
+new file mode 100644
+index 000000000..4f78454f3
+--- /dev/null
++++ b/arch/mips/xburst2/common/cpu_ddr_test/cpu_watch_test.c
+@@ -0,0 +1,200 @@
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/err.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/random.h>
++#include <linux/syscore_ops.h>
++#include <linux/debugfs.h>
++#include <linux/kthread.h>
++
++#include <linux/mfd/core.h>
++//#include <mach/jz_tcu.h>
++
++#include <asm/r4kcache.h>
++#include <asm/mmu_context.h>
++
++
++#include"../../../../../include/linux/mfd/ingenic-tcu_v2.h"
++
++struct watch_struct
++{
++	struct task_struct *child;
++	unsigned int watchhi;
++	unsigned int watchlo;
++
++	/* debugfs */
++	struct dentry *root;
++};
++
++struct watch_struct _cwt; /* cpu watch test */
++struct watch_struct *cwt; /* cpu watch test */
++
++
++static struct task_struct *trace_get_task_struct(pid_t pid)
++{
++	struct task_struct *child;
++
++	rcu_read_lock();
++	child = find_task_by_vpid(pid);
++	if (child)
++		get_task_struct(child);
++	rcu_read_unlock();
++
++	if (!child)
++		return ERR_PTR(-ESRCH);
++	return child;
++}
++char g_buffer[256];
++
++static ssize_t cpu_watch_read_start(struct file *file, char __user *user_buf,
++							size_t count, loff_t *ppos)
++{
++	char *buf = g_buffer;
++
++	return simple_read_from_buffer(user_buf, count, ppos, buf, strlen(buf));
++
++}
++
++static void local_set_watch(void *args) {
++	struct watch_struct *watch = (struct watch_struct *)args;
++	unsigned int cpu = smp_processor_id();
++	unsigned int hi = 0;
++//	struct mips3264_watch_reg_state *watches =
++		//&watch->child->thread.watch.mips3264;
++
++	if(watch->watchhi & 0x40000000)
++		hi = watch->watchhi;
++	else
++		hi = (watch->watchhi & 0xffff) | (cpu_asid(cpu,watch->child->mm) << 16);
++	if(watch->watchlo == 0) hi = 0;
++//	watches->watchlo[0][cpu] = watch->watchlo;
++//	watches->watchhi[0][cpu] = hi;
++
++	printk("watchlo: %x, watchhi: %x, cpu; %d\n", watch->watchlo, hi, cpu);
++	write_c0_watchlo0(watch->watchlo);
++	write_c0_watchhi0(hi);
++
++}
++static inline void jz_on_each_cpu(void (*func) (void *info), void *info)
++{
++	preempt_disable();
++	smp_call_function(func, info, 1);
++	func(info);
++	preempt_enable();
++}
++
++static ssize_t cpu_watch_write_start(struct file *file, const char __user *user_buf,
++							 size_t count, loff_t *ppos)
++{
++	char s[20];
++	char *s1,*s2;
++	pid_t pid;
++	unsigned int hi;
++	unsigned int lo;
++	struct task_struct *child = NULL;
++	struct watch_struct watch;
++//	struct mips3264_watch_reg_state *watches;
++
++	copy_from_user(g_buffer,user_buf,count);
++
++	g_buffer[count] = 0;
++	printk("%s\n",g_buffer);
++	s1 = g_buffer;
++	s2 = strchr(s1,':');
++	printk("s1 = %px s2 = %px\n",s1,s2);
++	if(!s2 || count == 0) {
++		pid = simple_strtoul(s1,0,0);
++		child = trace_get_task_struct(pid);
++		watch.child = child;
++		watch.watchlo = 0;
++		watch.watchhi = 0;
++		jz_on_each_cpu(local_set_watch,&watch);
++		//watches = &child->thread.watch.mips3264;
++		//watches->trace_type = 0;
++		clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
++
++		return count;
++	}
++
++	memcpy(s,s1,s2 - s1);
++	s[s2 - s1]  = 0;
++	pid = simple_strtoul(s,0,0);
++
++	s1 = s2 + 1;
++	s2 = strchr(s1,':');
++	printk("s1 = %px s2 = %px\n",s1,s2);
++	memcpy(s,s1,s2 - s1);
++	s[s2 - s1]  = 0;
++	lo = simple_strtoul(s,0,0);
++
++	s1 = s2 + 1;
++	hi = simple_strtoul(s1,0,0);
++	printk("pid = %d lo = 0x%08x hi = %d\n",pid,lo,hi);
++	child = trace_get_task_struct(pid);
++	printk("child = %px\n",child);
++	//child->thread.watch.mips3264.watchlo[0] = lo;
++	//child->thread.watch.mips3264.watchhi[0] = hi;
++	watch.child = child;
++	watch.watchlo = lo;
++	watch.watchhi = hi;
++	jz_on_each_cpu(local_set_watch,&watch);
++	//watches = &child->thread.watch.mips3264;
++	//watches->trace_type = 1;
++
++	return count;
++}
++
++static const struct file_operations cpu_watch_start_ops = {
++	.read = cpu_watch_read_start,
++	.write = cpu_watch_write_start,
++	.open = simple_open,
++	.llseek = default_llseek,
++};
++
++static int create_debugfs(struct watch_struct *cwt)
++{
++	struct dentry *d;
++	d = debugfs_create_dir("cpu_watch", NULL);
++	if(IS_ERR(d)) {
++		pr_err("Create debugfs for tcu test failed!\n");
++		return PTR_ERR(d);
++	}
++
++	cwt->root = d;
++
++	d = debugfs_create_file("start", S_IWUSR| S_IRUGO, cwt->root, cwt, &cpu_watch_start_ops);
++	if(IS_ERR_OR_NULL(d)) {
++		pr_err("Debugfs create failed!\n");
++		goto err_node;
++	}
++
++	return 0;
++
++err_node:
++	debugfs_remove_recursive(cwt->root);
++	return -1;
++}
++
++static int __init cpu_watch_test_init(void)
++{
++	int ret;
++
++	cwt = &_cwt;
++
++	ret = create_debugfs(cwt);
++
++	printk("cpu watch test probe ok!\n");
++	return 0;
++}
++
++static void __exit cpu_watch_test_deinit(void)
++{
++
++}
++
++late_initcall(cpu_watch_test_init);
++module_exit(cpu_watch_test_deinit);
+diff --git a/arch/mips/xburst2/common/cpu_ddr_test/ddr_bandwidth_monitor.c b/arch/mips/xburst2/common/cpu_ddr_test/ddr_bandwidth_monitor.c
+new file mode 100644
+index 000000000..fb8816460
+--- /dev/null
++++ b/arch/mips/xburst2/common/cpu_ddr_test/ddr_bandwidth_monitor.c
+@@ -0,0 +1,461 @@
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/syscore_ops.h>
++#include <linux/slab.h>
++#include <linux/debugfs.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/spinlock.h>
++#define DDR_MONITOR_BASE   0x134F0000
++#define DDR_DYNAMIC_CLK    0x13012068
++#define DDR_DWCFG	   0x13012000
++#define DDR_CMONC0	   0x13012050
++
++#define DB_MONITOR_BASE_OFF  0x88// DDR bandwidth monitor base offset address.
++
++#define MAX_SUPPORTED_MONITORS	4
++
++struct dbw_channel_reg{
++	volatile unsigned int write;
++	unsigned int reserve1;
++	volatile unsigned int read;
++	unsigned int reserve2;
++};
++struct dbw_reg{
++	volatile unsigned int dbwcfg;
++	unsigned int reserve;
++	volatile unsigned int period;
++	unsigned int reserver;
++	struct dbw_channel_reg chan[4];
++};
++
++
++#define GMAC_MSC_CHANNEL 0	//DDR ch0
++#define VPU_CHANNEL	 1	//DDR ch1
++#define DPU_VPU_CHANNEL	 3	//DDR ch3
++#define AHB2_CHANNEL 	 5	//DDR ch5
++#define CPU_CHANNEL 	 6	//DDR ch6
++
++struct ddr_mon_chan {
++	int chn;
++	const char *desc;
++};
++
++static struct ddr_mon_chan mon_chans[] = {
++	{0, "gmac&msc"},
++	{1, "vpu&isp"},
++	{3, "dpu&cim"},
++	{5, "ahb2&audio&apb"},
++	{6, "cpu"}
++};
++
++static unsigned int default_monitor_chn[MAX_SUPPORTED_MONITORS] = {0, 3, 5, 6};
++
++struct ddr_dbw_monitor {
++	struct ddr_mon_chan *ch;
++	unsigned int read;
++	unsigned int write;
++};
++
++
++static inline struct ddr_mon_chan* get_mon_chn(int chn)
++{
++	int i;
++
++	for(i = 0; i < ARRAY_SIZE(mon_chans); i++) {
++		if(mon_chans[i].chn == chn)
++			return &mon_chans[i];
++	}
++
++	printk("Error find mon_chn, chn: %d\n", chn);
++	return NULL;
++}
++
++static int set_mon_chn(struct ddr_dbw_monitor *monitors, int chn)
++{
++	struct ddr_mon_chan *mon_chn = get_mon_chn(chn);
++
++	printk("set _mon_chn :%d\n", chn);
++
++	if(!mon_chn) {
++		return -EINVAL;
++	}
++
++	monitors->ch = mon_chn;
++
++	return 0;
++}
++
++
++struct ddr_statistics{
++	struct dentry		*root;
++	unsigned int periods;
++	unsigned int output;
++	int run;
++
++	unsigned int ahb2_read_rate;
++	unsigned int ahb2_write_rate;
++	unsigned int cpu_read_rate;
++	unsigned int cpu_write_rate;
++
++	/* 1 package  = 4 * 32 = 8 * 16 */
++	unsigned int pkg_cnt_to_cycle;
++
++	int poll_periods_ms;
++	struct dbw_reg *reg;
++
++	struct ddr_dbw_monitor dbw_monitors[4];
++
++	struct mutex		lock;
++	struct timer_list timer;
++};
++static struct ddr_statistics ddr_statistics = {
++	.periods = 25 * 1000 * 1000,
++	.run = 0,
++	.poll_periods_ms = 40,
++	.output = 1,
++};
++#define BW_DONE (1 << 3)
++#define BW_INT_EN (1 << 2)
++#define BW_CLR  (1 << 1)
++#define BW_EN   (1 << 0)
++
++#define DDR_PACKAGE_TO_CYCLE 4
++static void ddr_stat_output(struct ddr_statistics *ddr)
++{
++	uint64_t period = (uint64_t)ddr->reg->period;
++#define occupancy_show(title,chn,id) do{									\
++		uint64_t w_occupancy = (uint64_t)ddr->dbw_monitors[id].write * ddr->pkg_cnt_to_cycle; 	\
++		uint64_t r_occupancy = (uint64_t)ddr->dbw_monitors[id].read * ddr->pkg_cnt_to_cycle; 	\
++		uint64_t d = 100000 * w_occupancy;							\
++		uint64_t hi;										\
++		do_div(d,period);									\
++		hi = (uint32_t)d / 1000;								\
++		printk("%s chn:%d write occupancy rate:%lld.%03lld%%\n",title,chn,hi,d - hi * 1000); 		\
++		d = 100000 * r_occupancy;								\
++		do_div(d,period);									\
++		hi = (uint32_t)d / 1000;								\
++		printk("%s chn:%d read occupancy rate:%lld.%03lld%%\n",title,chn, hi,d - hi * 1000); 		\
++	}while(0)
++	occupancy_show(ddr->dbw_monitors[0].ch->desc, ddr->dbw_monitors[0].ch->chn, 0);
++	occupancy_show(ddr->dbw_monitors[1].ch->desc, ddr->dbw_monitors[1].ch->chn, 1);
++	occupancy_show(ddr->dbw_monitors[2].ch->desc, ddr->dbw_monitors[2].ch->chn, 2);
++	occupancy_show(ddr->dbw_monitors[3].ch->desc, ddr->dbw_monitors[3].ch->chn, 3);
++#undef occupancy_show
++}
++
++static struct ddr_dbw_monitor *get_dbw_monitor(struct ddr_statistics *ddr, int chn)
++{
++	struct ddr_dbw_monitor *m;
++	int i = 0;
++
++	for(i = 0; i < MAX_SUPPORTED_MONITORS; i++) {
++		m = &ddr->dbw_monitors[i];
++		if(m->ch->chn == chn)
++			return m;
++	}
++
++	return NULL;
++}
++
++static ssize_t ddr_read_run(struct file *file, char __user *user_buf,
++							size_t count, loff_t *ppos)
++{
++	struct ddr_statistics *ddr = file->private_data;
++	char *buf;
++
++	mutex_lock(&ddr->lock);
++	if(ddr->reg->dbwcfg & BW_EN)
++		buf = "Runing\n";
++	else
++		buf = "Stop\n";
++	mutex_unlock(&ddr->lock);
++	return simple_read_from_buffer(user_buf, count, ppos, buf, strlen(buf));
++}
++
++static ssize_t ddr_write_run(struct file *file, const char __user *user_buf,
++							 size_t count, loff_t *ppos)
++{
++	struct ddr_statistics *ddr = file->private_data;
++	struct ddr_dbw_monitor *m;
++	char buf[16];
++	bool bv;
++	int ret = 0;
++	unsigned int val;
++	int i = 0;
++	if (copy_from_user(buf, user_buf, min(count, (sizeof(buf) - 1))))
++		return -EFAULT;
++
++	if (strtobool(buf, &bv) == 0) {
++		mutex_lock(&ddr->lock);
++
++		if(bv){
++			val = readl((void*)CKSEG1ADDR(DDR_DYNAMIC_CLK));
++			val &= ~(1 << 8);
++			writel(val,(void*)CKSEG1ADDR(DDR_DYNAMIC_CLK));
++
++			del_timer_sync(&ddr->timer);
++			if(ddr->reg->period != ddr->periods)
++				ddr->poll_periods_ms = 0;
++			ddr->run = 1;
++			ddr->reg->period = ddr->periods;
++			val = ddr->reg->period;
++
++			ddr->reg->dbwcfg = BW_EN | BW_CLR;
++			while((ddr->reg->dbwcfg & (BW_CLR | BW_EN)) != BW_EN);
++			printk("run!\n");
++			mod_timer(&ddr->timer,jiffies + msecs_to_jiffies(ddr->poll_periods_ms));
++		}else{
++
++			del_timer_sync(&ddr->timer);
++			ddr->run = 0;
++			for(i = 0; i < MAX_SUPPORTED_MONITORS; i++) {
++				ddr->dbw_monitors[i].write = ddr->reg->chan[i].write;
++				ddr->dbw_monitors[i].read = ddr->reg->chan[i].read;
++			}
++
++			if(ddr->output){
++				ddr_stat_output(ddr);
++			}
++
++			ddr->ahb2_write_rate = (m = get_dbw_monitor(ddr, AHB2_CHANNEL)) == NULL ? 0:m->write;
++			ddr->ahb2_read_rate = (m = get_dbw_monitor(ddr, AHB2_CHANNEL)) == NULL ? 0:m->read;
++			ddr->cpu_write_rate = (m = get_dbw_monitor(ddr, CPU_CHANNEL)) == NULL ? 0:m->write;
++			ddr->cpu_read_rate = (m = get_dbw_monitor(ddr, CPU_CHANNEL)) == NULL ? 0:m->read;
++
++
++			ddr->reg->dbwcfg = 0;
++			printk("stopping!\n");
++		}
++		mutex_unlock(&ddr->lock);
++	}
++
++	return ret ? ret : count;
++}
++
++static const struct file_operations ddr_run_fops = {
++	.read	= ddr_read_run,
++	.write	= ddr_write_run,
++	.open	= simple_open,
++	.llseek	= default_llseek,
++};
++static void ddr_stat_timer_handler(struct timer_list *timer)
++{
++	struct ddr_statistics *ddr = container_of(timer, struct ddr_statistics, timer);
++	unsigned int dbwcfg = ddr->reg->dbwcfg;
++	struct ddr_dbw_monitor *m;
++	int i = 0;
++	if(dbwcfg & BW_DONE)
++	{
++		if(ddr->run){
++			for(i = 0; i < MAX_SUPPORTED_MONITORS; i++) {
++				ddr->dbw_monitors[i].write = ddr->reg->chan[i].write;
++				ddr->dbw_monitors[i].read = ddr->reg->chan[i].read;
++			}
++
++			if(ddr->output){
++				ddr_stat_output(ddr);
++			}
++			if(ddr->reg->dbwcfg != dbwcfg)
++				ddr->poll_periods_ms = 0;
++
++
++			ddr->ahb2_write_rate = (m = get_dbw_monitor(ddr, AHB2_CHANNEL)) == NULL ? 0:m->write;
++			ddr->ahb2_read_rate = (m = get_dbw_monitor(ddr, AHB2_CHANNEL)) == NULL ? 0:m->read;
++			ddr->cpu_write_rate = (m = get_dbw_monitor(ddr, CPU_CHANNEL)) == NULL ? 0:m->write;
++			ddr->cpu_read_rate = (m = get_dbw_monitor(ddr, CPU_CHANNEL)) == NULL ? 0:m->read;
++
++			dbwcfg |= BW_CLR;
++			ddr->reg->dbwcfg = dbwcfg;
++
++			while(ddr->reg->dbwcfg & BW_CLR);
++			mod_timer(&ddr->timer,jiffies + msecs_to_jiffies(ddr->poll_periods_ms));
++		}else{
++			ddr->reg->dbwcfg = 0;
++		}
++	} else {
++		mod_timer(&ddr->timer,jiffies + msecs_to_jiffies(10));
++		ddr->poll_periods_ms += 10;
++	}
++}
++
++static int dbw_monitors_init(struct ddr_statistics *ddr)
++{
++	unsigned int cmonc0;
++	int i;
++
++	for(i = 0; i < MAX_SUPPORTED_MONITORS; i++) {
++		ddr->dbw_monitors[i].ch = get_mon_chn(default_monitor_chn[i]);
++	}
++
++#if 0
++	ddr->dbw_monitors[0].ch = &mon_chans[0];
++	ddr->dbw_monitors[1].ch = &mon_chans[1];
++	ddr->dbw_monitors[2].ch = &mon_chans[2];
++	ddr->dbw_monitors[3].ch = &mon_chans[3];
++#endif
++	cmonc0 = readl((void *)CKSEG1ADDR(DDR_CMONC0));
++	/*cmonc0[15:4]*/
++	cmonc0 &= ~0xfff0;
++	cmonc0 |= (ddr->dbw_monitors[0].ch->chn << 13) \
++		| (ddr->dbw_monitors[1].ch->chn << 10) \
++		| (ddr->dbw_monitors[2].ch->chn << 7)  \
++		| (ddr->dbw_monitors[3].ch->chn << 4);
++	writel(cmonc0, (void *)CKSEG1ADDR(DDR_CMONC0));
++
++	return 0;
++}
++static ssize_t ddr_read_monitors(struct file *file, char __user *user_buf,
++							size_t count, loff_t *ppos)
++{
++	struct ddr_statistics *ddr = file->private_data;
++	struct ddr_dbw_monitor *m = NULL;
++	int i = 0;
++	int ret = 0;
++
++	unsigned char *buf = kzalloc(1024, GFP_KERNEL);
++	unsigned char *p = buf;
++
++	if(!buf) {
++		printk("Error alloc mem!\n");
++		return -ENOMEM;
++	}
++
++	for(i = 0; i < MAX_SUPPORTED_MONITORS; i++) {
++		m = &ddr->dbw_monitors[i];
++		ret = sprintf(p, "monitor:%d, chn:%d, desc:%s\n\t read:%d, write:%d\n",
++			i, m->ch->chn, m->ch->desc, m->read, m->write);
++		p += ret;
++	}
++
++	ret = simple_read_from_buffer(user_buf, count, ppos, buf, strlen(buf));
++	kfree(buf);
++	return ret;
++}
++
++static ssize_t ddr_write_monitors(struct file *file, const char __user *user_buf,
++							 size_t count, loff_t *ppos)
++{
++
++	struct ddr_statistics *ddr = file->private_data;
++	char buf[16];
++	int i = 0;
++	unsigned int val;
++	char *token, *cur = buf;
++	unsigned int cmonc0;
++
++	if (copy_from_user(buf, user_buf, min(count, (sizeof(buf) - 1))))
++		return -EFAULT;
++
++	for(i = 0; i < MAX_SUPPORTED_MONITORS; i++) {
++		token = strsep(&cur, ":");
++		if(!token) {
++			printk("Invalid monitor settings!\n");
++			return -EINVAL;
++		}
++		val = simple_strtoul(token, NULL, 10);
++
++		if(set_mon_chn(&ddr->dbw_monitors[i], val) < 0) {
++			return -EINVAL;
++		}
++	}
++
++	cmonc0 = readl((void *)CKSEG1ADDR(DDR_CMONC0));
++	/*cmonc0[15:4]*/
++	cmonc0 &= ~0xfff0;
++	cmonc0 |= (ddr->dbw_monitors[0].ch->chn << 13) \
++		| (ddr->dbw_monitors[1].ch->chn << 10) \
++		| (ddr->dbw_monitors[2].ch->chn << 7)  \
++		| (ddr->dbw_monitors[3].ch->chn << 4);
++	writel(cmonc0, (void *)CKSEG1ADDR(DDR_CMONC0));
++
++	return count;
++}
++
++static const struct file_operations ddr_monitors_fops = {
++	.read	= ddr_read_monitors,
++	.write	= ddr_write_monitors,
++	.open	= simple_open,
++	.llseek	= default_llseek,
++};
++
++
++static int __init ddr_stat_init(void)
++{
++	struct dentry * d;
++	struct ddr_statistics *ddr = &ddr_statistics;
++
++	d = debugfs_create_dir("ddr", NULL);
++	if (IS_ERR(d)){
++		pr_err("create debugfs for ddr failed.\n");
++		return PTR_ERR(d);
++	}
++
++
++	ddr->root = d;
++
++	d = debugfs_create_file("monitors", S_IWUSR | S_IRUGO, ddr->root,
++							ddr, &ddr_monitors_fops);
++	if (IS_ERR_OR_NULL(d))
++		goto err_node;
++
++	debugfs_create_u32("periods", S_IWUSR | S_IRUGO, ddr->root,
++						   (u32 *)&ddr->periods);
++
++	debugfs_create_u32("output", S_IWUSR | S_IRUGO, ddr->root,
++						   (u32 *)&ddr->output);
++
++	debugfs_create_u32("ahb2_read_rate", S_IWUSR | S_IRUGO, ddr->root,
++						   (u32 *)&ddr->ahb2_read_rate);
++
++	debugfs_create_u32("ahb2_write_rate", S_IWUSR | S_IRUGO, ddr->root,
++						   (u32 *)&ddr->ahb2_write_rate);
++
++	debugfs_create_u32("cpu_read_rate", S_IWUSR | S_IRUGO, ddr->root,
++						   (u32 *)&ddr->cpu_read_rate);
++
++	debugfs_create_u32("cpu_write_rate", S_IWUSR | S_IRUGO, ddr->root,
++						   (u32 *)&ddr->cpu_write_rate);
++
++
++
++	d = debugfs_create_file("run", S_IWUSR | S_IRUGO, ddr->root,
++							ddr, &ddr_run_fops);
++	if (IS_ERR_OR_NULL(d))
++		goto err_node;
++	mutex_init(&ddr->lock);
++
++	ddr->reg = ioremap(DDR_MONITOR_BASE + DB_MONITOR_BASE_OFF,sizeof(struct dbw_reg));
++
++	if(readl((void *)CKSEG1ADDR(DDR_DWCFG)) & 1) {
++		/* 32bit ddr*/
++		ddr->pkg_cnt_to_cycle = 4;
++
++	} else {
++		ddr->pkg_cnt_to_cycle = 8;
++
++	}
++
++	dbw_monitors_init(ddr);
++
++
++
++	init_timers();
++	ddr->timer.function = ddr_stat_timer_handler;
++
++	return 0;
++err_node:
++	debugfs_remove_recursive(ddr->root);
++
++	return -1;
++}
++
++static void __exit ddr_stat_deinit(void)
++{
++	struct ddr_statistics *ddr = &ddr_statistics;
++	debugfs_remove_recursive(ddr->root);
++}
++
++late_initcall(ddr_stat_init);
++module_exit(ddr_stat_deinit);
+diff --git a/arch/mips/xburst2/common/cpu_ddr_test/ddr_change_freq.c b/arch/mips/xburst2/common/cpu_ddr_test/ddr_change_freq.c
+new file mode 100644
+index 000000000..3841d6f8c
+--- /dev/null
++++ b/arch/mips/xburst2/common/cpu_ddr_test/ddr_change_freq.c
+@@ -0,0 +1,521 @@
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/syscore_ops.h>
++#include <linux/slab.h>
++#include <linux/debugfs.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/spinlock.h>
++#include <linux/clk.h>
++#include <asm/idle.h>
++#include <asm/mipsregs.h>
++#include <asm/cacheops.h>
++#include <linux/interrupt.h>
++
++#include <soc/ddr.h>
++
++#include <ccu.h>
++#include "cpu_tcsm.h"
++
++/* #define ALL_OTHER_CPU_WAITE */
++struct ddr_calib_value {
++	unsigned int rate;
++	unsigned int refcnt;
++	unsigned char bypass_al;
++	unsigned char bypass_ah;
++};
++
++typedef void  (*ddr_change_code)(unsigned int, unsigned int,
++								 unsigned int,unsigned int);
++
++struct ddr_cfreq {
++	struct dentry		*root;
++	spinlock_t lock;
++	struct timer_list timer;
++	struct clk *clk_ddr;
++
++	unsigned int ddr_cur_rate;
++	ddr_change_code tcsm_change_ddr_rate;
++};
++
++struct ddr_cfreq ddr_cfreq;
++
++#define CPM_DDRCDR (0xb000002c)
++
++static ssize_t ddr_read_rate(struct file *file, char __user *user_buf,
++							size_t count, loff_t *ppos)
++{
++	char buf[4];
++	int pos = 0;
++
++	pos = scnprintf(buf, 4, "%d\n", ddr_cfreq.ddr_cur_rate);
++	return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
++}
++
++static unsigned int get_ddr_parent_rate(void)
++{
++	unsigned int val;
++	struct clk *pll;
++	unsigned int pll_rate;
++
++	val = REG32(CPM_DDRCDR);
++	switch(val >> 30) {
++	case 1:
++		pll = clk_get(NULL, "apll");
++		break;
++	case 2:
++		pll = clk_get(NULL, "mpll");
++		break;
++	default :
++		printk("not support\n");
++		return 0;
++	}
++
++	pll_rate = clk_get_rate(pll);
++	return pll_rate;
++}
++static unsigned int get_ddr_rate(void)
++{
++	unsigned int pll_rate, ddr_rate;
++	unsigned int val;
++
++	val = REG32(CPM_DDRCDR);
++
++	pll_rate = get_ddr_parent_rate();
++	ddr_rate = pll_rate / ((val & 0xf) + 1);
++	return ddr_rate;
++}
++
++static unsigned int pp_mask, ost_mask, mailbox_mask;
++#ifdef ALL_OTHER_CPU_WAITE
++static unsigned int pp_pend,ost_pend, mailbox_pend;
++#endif
++
++static inline void unmask_others_cpu(void);
++static void change_ddr_rate(unsigned char bal, unsigned char bah, unsigned int refcnt, int div)
++{
++	unsigned int val, cur_div;//, div;
++	unsigned int hregpro, pregpro;
++	unsigned int autoself_en;
++#ifdef ALL_OTHER_CPU_WAITE
++	unsigned int wait_cpu;
++	unsigned int timeout = 10000;
++
++	REG32(0xb0032000) = '0';
++
++	div = change_div & 0xffff;
++	wait_cpu = (change_div >> 16);
++	while(!REG32(0xb2407ff8) && timeout --)
++		;
++	if(!timeout)
++		return;
++#endif
++	hregpro = ddr_readl(DDRC_HREGPRO);
++	pregpro = ddr_readl(DDRC_PREGPRO);
++	autoself_en = ddr_readl(DDRC_AUTOSR_EN);
++
++	ddr_writel(0, DDRC_HREGPRO);
++	ddr_writel(0, DDRC_PREGPRO);
++	ddr_writel(0, DDRC_AUTOSR_EN);
++
++	// Disable DFI lowpower handshake
++	/* val = ddr_readl(DDRC_DLP); */
++	/* val &= ~(1); */
++	/* ddr_writel(val, DDRC_DLP); */
++
++	val = REG32(CPM_DDRCDR);
++	cur_div = (val & 0xf);
++
++	if(cur_div > div) {
++		val = ddr_readl(DDRC_REFCNT);
++		val &= ~(0x3ffff << 8 | 0xe);
++		val |= refcnt;
++		ddr_writel(val, DDRC_REFCNT);
++	}
++	/**
++	 * don't use AHB0/2 APB BUS before freq exit.
++	 */
++	/**
++	 * Set !change_en and ce
++	 */
++	val = REG32(CPM_DDRCDR);
++	val |= ((1 << 29) | (1 << 25));
++	REG32(CPM_DDRCDR) = val;
++	/* while((REG32(CPM_DDRCDR) & (1 << 24))); */
++
++	/**
++	 * Set clock divider
++	 */
++	val = REG32(CPM_DDRCDR);
++	val &= ~(0xf);
++	val |= div;
++	REG32(CPM_DDRCDR) = val;
++//	while((REG32(CPM_DDRCDR) & (1 << 28)));
++	/**
++	 * Polling PHY_FREQ_DONE
++	 */
++	while((ddr_readl(DDRC_DWSTATUS) & (1 << 3 | 1 << 1)) != 0xa)
++		;
++
++	ddr_writel(DDRP_TRAINING_CTRL_DSCSE_BP, DDRP_INNOPHY_TRAINING_CTRL);
++	ddr_writel(bal, DDRP_INNOPHY_CALIB_BYPASS_AL);
++	ddr_writel(bah, DDRP_INNOPHY_CALIB_BYPASS_AH);
++
++	/**
++	 * Set Controller Freq Exit
++	 */
++	val = ddr_readl(DDRC_DWCFG);
++	val |= (1 << 2);
++	ddr_writel(val, DDRC_DWCFG);
++
++	/**
++	 * Clear Controller Freq Exit
++	 */
++	val = ddr_readl(DDRC_DWCFG);
++	val &= ~(1 << 2);
++	ddr_writel(val, DDRC_DWCFG);
++
++	/**
++	 * clear change_en and ce
++	 */
++	val = REG32(CPM_DDRCDR);
++	val &= ~((1 << 29) | (1 << 25));
++	REG32(CPM_DDRCDR) = val;
++
++	unmask_others_cpu();
++
++#ifdef ALL_OTHER_CPU_WAITE
++	if(ost_pend)
++		set_ccu_oipr(get_ccu_oipr() | (1 << wait_cpu));
++	if(pp_pend)
++		set_ccu_pipr(get_ccu_pipr() | (1 << wait_cpu));
++	if(mailbox_pend)
++		set_ccu_mipr(get_ccu_mipr() | (1 << wait_cpu));
++
++	if(ost_mask)
++		set_ccu_oimr(get_ccu_oimr() | (1 << wait_cpu));
++	if(pp_mask)
++		set_ccu_pimr(get_ccu_pimr() | (1 << wait_cpu));
++	if(mailbox_mask)
++		set_ccu_mimr(get_ccu_mimr() | (1 << wait_cpu));
++	/* REG32(0xb2407ff8) = 0; */
++#endif
++
++	if(cur_div < div) {
++		val = ddr_readl(DDRC_REFCNT);
++		val &= ~(0x3ffff << 8 | 0xe);
++		val |= refcnt;
++		ddr_writel(val, DDRC_REFCNT);
++	}
++
++	if(autoself_en)
++		ddr_writel(1, DDRC_AUTOSR_EN);
++	if(hregpro & (1 << 1))
++		ddr_writel(1, DDRC_HREGPRO);
++	if(pregpro & (1 << 1))
++		ddr_writel(1, DDRC_PREGPRO);
++}
++
++#define __read_32bit_register()					\
++	({ int __res;								\
++		__asm__ __volatile__(					\
++			"move \t %0, $29\n\t"				\
++			: "=r" (__res));					\
++		__res;									\
++	})
++
++#define __write_32bit_register(value)						\
++	do {													\
++		__asm__ __volatile__(								\
++			"move \t $29, %0\n\t"							\
++			: : "Jr" ((unsigned int)(value)));				\
++	} while (0)
++
++#define read_sp_register() __read_32bit_register()
++#define write_sp_register(val) __write_32bit_register(val)
++static unsigned int change_count;
++static int try_and_lock_ccu(unsigned int cpu)
++{
++	int timeout = 1000;
++	unsigned int cslr;
++
++	do {
++		set_ccu_csar(cpu);
++		cslr = get_ccu_cslr();
++		if((cslr & 1 << 31) && ((cslr & ((1 << CONFIG_NR_CPUS) -1)) == cpu))
++			break;
++	} while(timeout --);
++	if(timeout < 0)
++		return -1;
++	return 0;
++}
++static void unlock_ccu(void)
++{
++	set_ccu_cslr(0);
++}
++static int mask_and_wait_others_cpu(unsigned int cur_cpu)
++{
++	unsigned int pp_mval, mb_mval, ost_mval;
++	unsigned int max_cpu_num = CONFIG_NR_CPUS;
++	unsigned int mask_cpus = ((1 << max_cpu_num) - 1);
++	unsigned int mask_other_cpus = (mask_cpus & (~(1 << cur_cpu)));
++	int timeout, ret = 0;
++
++	pp_mval = get_ccu_pimr();
++	mb_mval = get_ccu_mimr();
++	ost_mval = get_ccu_oimr();
++
++	pp_mask = pp_mval & (mask_cpus);
++	mailbox_mask = mb_mval & (mask_cpus);
++	ost_mask = ost_mval & (mask_cpus);
++
++	try_and_lock_ccu(cur_cpu);
++	if(ret < 0) {
++		printk("try to lock ccu failed\n");
++		return ret;
++	}
++
++	set_ccu_pimr(0);
++	set_ccu_mimr(0);
++	set_ccu_oimr(0);
++
++	timeout = 100000;
++	while(((get_ccu_cssr() & mask_other_cpus) != mask_other_cpus)
++		  && timeout--);
++
++	if(!get_ccu_cssr() && timeout >= 0) {
++			printk("ERROR:get_ccu_cssr() %x timeout %d mask_other_cpus %x\n", get_ccu_cssr(), timeout, mask_other_cpus);
++			printk("ERROR:get_ccu_cssr() %x timeout %d mask_other_cpus %x\n", get_ccu_cssr(), timeout, mask_other_cpus);
++			printk("ERROR:get_ccu_cssr() %x timeout %d mask_other_cpus %x\n", get_ccu_cssr(), timeout, mask_other_cpus);
++			printk("ERROR:get_ccu_cssr() %x timeout %d mask_other_cpus %x\n", get_ccu_cssr(), timeout, mask_other_cpus);
++			printk("ERROR:get_ccu_cssr() %x timeout %d mask_other_cpus %x\n", get_ccu_cssr(), timeout, mask_other_cpus);
++			printk("get_ccu_cssr() %x timeout %d mask_other_cpus %x\n", get_ccu_cssr(), timeout, mask_other_cpus);
++			printk("SMP: ------------------wakeup--------CPU%d: cause %x\n", cur_cpu, read_c0_cause());
++			printk("SMP: ------------------wakeup--------CPU%d: pp pending %x\n", cur_cpu, REG32(0xb2200100));
++			printk("SMP: ------------------wakeup--------CPU%d: ost pending %x\n", cur_cpu, REG32(0xb2200180));
++			printk("SMP: ------------------wakeup--------CPU%d: mailbox pending %x\n", cur_cpu, REG32(0xb2200140));
++
++			printk("SMP: ------------------wakeup--------CPU%d: pp mask %x\n", cur_cpu, get_ccu_pimr());
++			printk("SMP: ------------------wakeup--------CPU%d: mailbox mask %x\n", cur_cpu, get_ccu_mimr());
++			printk("SMP: ------------------wakeup--------CPU%d: os mask %x\n", cur_cpu, get_ccu_oimr());
++			while(1);
++	}
++
++	if(timeout < 0) {
++		set_ccu_pimr(pp_mask);
++		set_ccu_mimr(mailbox_mask);
++		set_ccu_oimr(ost_mask);
++		ret = -1;
++	}
++	unlock_ccu();
++
++	return ret;
++}
++static inline void unmask_others_cpu(void)
++{
++	/* try_and_lock_ccu(cur_cpu); */
++	/* if(ret < 0) { */
++	/* 	printk("try to lock ccu failed\n"); */
++	/* 	return ret; */
++	/* } */
++	set_ccu_pimr(pp_mask);
++	set_ccu_mimr(mailbox_mask);
++	set_ccu_oimr(ost_mask);
++	/* unlock_ccu(); */
++}
++#ifdef ALL_OTHER_CPU_WAITE
++static void disable_interrupt(void *args)
++{
++	unsigned int cpu = smp_processor_id();
++	printk("SMP: --------------------------CPU%d is offline\n", cpu);
++
++	if(cpu != *(unsigned int *)args) {
++		unsigned int pp_mval, mb_mval, ost_mval;
++		unsigned int pp_pval, mb_pval, ost_pval;
++		pp_mval = get_ccu_pimr();
++		mb_mval = get_ccu_mimr();
++		ost_mval = get_ccu_oimr();
++
++		pp_mask = pp_mval & (1 << cpu);
++		mailbox_mask = mb_mval & (1 << cpu);
++		ost_mask = ost_mval & (1 << cpu);
++
++		set_ccu_pimr(pp_mval & (~(1 << cpu)));
++		set_ccu_mimr(mb_mval & (~(1 << cpu)));
++		set_ccu_oimr(ost_mval & (~(1 << cpu)));
++
++		pp_pval = get_ccu_pipr();
++		mb_pval = get_ccu_mipr();
++		ost_pval = get_ccu_oipr();
++
++		pp_pend = pp_pval & (1 << cpu);
++		mailbox_pend = mb_pval & (1 << cpu);
++		ost_pend = ost_pval & (1 << cpu);
++
++		set_ccu_pipr(pp_pval & (~(1 << cpu)));
++		set_ccu_mipr(mb_pval & (~(1 << cpu)));
++		set_ccu_oipr(ost_pval & (~(1 << cpu)));
++	}
++
++	REG32(0xb2407ff8) = 0xa5a5a5a5;
++	__asm__ __volatile__ ("wait \n\t");
++
++	printk("SMP: ------------------wakeup--------CPU%d: cause %x\n", cpu, read_c0_cause());
++	printk("SMP: ------------------wakeup--------CPU%d: pp pending %x\n", cpu, REG32(0xb2200100));
++	printk("SMP: ------------------wakeup--------CPU%d: ost pending %x\n", cpu, REG32(0xb2200180));
++	printk("SMP: ------------------wakeup--------CPU%d: mailbox pending %x\n", cpu, REG32(0xb2200140));
++}
++#endif
++
++static ssize_t ddr_write_rate(struct file *file, const char __user *user_buf,
++							  size_t count, loff_t *ppos)
++{
++	char buf[16];
++	unsigned int change_rate;
++	unsigned long flags;
++	unsigned int cpu = smp_processor_id();
++	unsigned int sp, change_div;
++	int ret;
++	struct ddr_calib_value *dcv, *curdcv;
++
++	dcv = (struct ddr_calib_value *)(CPU_TCSM_DDR_CALIB);
++
++	if (copy_from_user(buf, user_buf, min(count, (sizeof(buf) - 1))))
++		return -EFAULT;
++
++	change_rate = simple_strtoul(buf, NULL, 10) * 1000000;
++	printk("change_rate %d-----------------\n", change_rate);
++	if(change_rate == ddr_cfreq.ddr_cur_rate) {
++		printk("change rate equl current rate\n");
++		return count;
++	}
++
++	change_div = get_ddr_parent_rate() / change_rate - 1;
++	if(dcv[change_div].rate != change_rate) {
++		int i;
++		printk("rate %d not support %d\n", change_rate, dcv[change_div].rate);
++		for(i = 0; i< 6; i ++)
++			printk("div %d, rate %d\n", i, dcv[i].rate);
++		printk("change_div %d\n", change_div);
++		return count;
++	}
++	curdcv = &dcv[change_div];
++
++	change_count ++;
++	printk("------------cpu %d----------------%d------------------\n", cpu, change_count);
++
++#ifdef ALL_OTHER_CPU_WAITE
++	REG32(0xb2407ff8) = 0;
++	change_div |= ((cpu?0:1) << 16);
++//	preempt_disable();
++	/* on_each_cpu(disable_interrupt, &cpu, 0); */
++	smp_call_function(disable_interrupt, &cpu, 0);
++#endif
++
++	spin_lock_irqsave(&ddr_cfreq.lock,flags);
++	ret = mask_and_wait_others_cpu(cpu);
++	if(ret < 0) {
++		printk("lock failed\n");
++		change_count --;
++		spin_unlock_irqrestore(&ddr_cfreq.lock,flags);
++		return ret;
++	}
++	sp = read_sp_register();
++	write_sp_register(CPU_TCSM_SP);
++	ddr_cfreq.tcsm_change_ddr_rate(curdcv->bypass_al,
++								   curdcv->bypass_ah, curdcv->refcnt, change_div);
++	write_sp_register(sp);
++	spin_unlock_irqrestore(&ddr_cfreq.lock,flags);
++//	preempt_enable();
++	printk("change succeed\n");
++
++	ddr_cfreq.ddr_cur_rate = get_ddr_rate();
++	clk_set_rate(ddr_cfreq.clk_ddr, ddr_cfreq.ddr_cur_rate);
++	/* ddr_cfreq.ddr_cur_rate = clk_get_rate(ddr_cfreq.clk_ddr); */
++	printk("clk_get_rate(ddr_cfreq.clk_ddr) %d\n", (unsigned int)clk_get_rate(ddr_cfreq.clk_ddr));
++
++	return count;
++}
++
++static const struct file_operations ddr_run_fops = {
++	.read	= ddr_read_rate,
++	.write	= ddr_write_rate,
++	.open	= simple_open,
++	.llseek	= default_llseek,
++};
++
++static void load_func_to_tcsm(unsigned int *tcsm_addr,unsigned int *f_addr,unsigned int size)
++{
++	unsigned int instr;
++	int offset;
++	int i;
++	for(i = 0;i < size / 4;i++) {
++		instr = f_addr[i];
++		if((instr >> 26) == 2){
++			offset = instr & 0x3ffffff;
++			offset = (offset << 2) - ((unsigned int)f_addr & 0xfffffff);
++			if(offset > 0) {
++				printk("f_addr[i]%x: %x--------------------------------------------------\n", (unsigned int)&f_addr[i], f_addr[i]);
++				offset = ((unsigned int)tcsm_addr & 0xfffffff) + offset;
++				/* offset = ((unsigned int)0xf4000000 & 0xfffffff) + offset; */
++				instr = (2 << 26) | (offset >> 2);
++			}
++		}
++		tcsm_addr[i] = instr;
++	}
++}
++
++static int __init ddr_init(void)
++{
++	struct dentry * d;
++	struct ddr_cfreq *cfreq = &ddr_cfreq;
++
++	cfreq->clk_ddr = clk_get(NULL, "div_ddr");
++	if(!cfreq->clk_ddr) {
++		printk("get ddr clk failed\n");
++		return -1;
++	}
++
++	cfreq->ddr_cur_rate = clk_get_rate(cfreq->clk_ddr);
++	{
++		unsigned int *tcsm_bank0 = (unsigned int *)CPU_TCSM_FUNC;
++		/* unsigned int *tcsm_bank0 = (unsigned int *)0xb3423000; */
++		unsigned int *func0 = (unsigned int *)change_ddr_rate;
++
++		load_func_to_tcsm(tcsm_bank0, func0, CPU_TCSM_FUNC_SIZE);
++		cfreq->tcsm_change_ddr_rate = (ddr_change_code)tcsm_bank0;
++	}
++
++
++	d = debugfs_create_dir("ddrfreq", NULL);
++	if (IS_ERR(d)){
++		pr_err("create debugfs for ddr failed.\n");
++		return PTR_ERR(d);
++	}
++	spin_lock_init(&cfreq->lock);
++
++	cfreq->root = d;
++	debugfs_create_u32("ddr_cur_rate", S_IWUSR | S_IRUGO, cfreq->root,
++						   (u32 *)&cfreq->ddr_cur_rate);
++
++	d = debugfs_create_file("rate", S_IWUSR | S_IRUGO, cfreq->root,
++							cfreq, &ddr_run_fops);
++	if (IS_ERR_OR_NULL(d))
++		goto err_node;
++
++	return 0;
++err_node:
++	debugfs_remove_recursive(cfreq->root);
++
++	return -1;
++}
++
++static void __exit ddr_deinit(void)
++{
++	struct ddr_cfreq *cfreq = &ddr_cfreq;
++	debugfs_remove_recursive(cfreq->root);
++}
++
++late_initcall(ddr_init);
++module_exit(ddr_deinit);
+diff --git a/arch/mips/xburst2/common/cpu_ddr_test/l2c_test.c b/arch/mips/xburst2/common/cpu_ddr_test/l2c_test.c
+new file mode 100644
+index 000000000..397cd86a2
+--- /dev/null
++++ b/arch/mips/xburst2/common/cpu_ddr_test/l2c_test.c
+@@ -0,0 +1,527 @@
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/syscore_ops.h>
++#include <linux/slab.h>
++#include <linux/debugfs.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/dma-mapping.h>
++#include <linux/kthread.h>
++#include <linux/delay.h>
++#include <linux/random.h>
++/**
++  1.   start address align:  0-63
++  2.   size align:           0-63
++  3.   max size: 		     512k
++  4.   invalid:
++  5.   writeback:
++  6.   blast:
++  7.   8 thread.
++*/
++
++struct l2c_test_thread;
++typedef int (*TEST_FUNC)(struct l2c_test_thread *);
++struct l2c_test_thread{
++	struct list_head	list;
++	struct task_struct	*task;
++	TEST_FUNC test_func;
++	struct mutex		*lock;
++	int id;
++	volatile int done;
++};
++#define TO_UNC(x) ((unsigned int)x | 0x20000000)
++//#define TO_UNC(x) ((unsigned int)x)
++
++#define L2C_SIZE (512 * 1024)
++#define L2C_LINESIZE (64)
++
++#define PALLADIUM_TRIGER() do{					\
++		void (*func)(void);						\
++		func = (void(*)(void)) 0xbfc00000;		\
++		func();									\
++	}while(0)
++
++#define info(x,y...) do{							\
++		printk(x,##y);								\
++	}while(0)
++
++static __maybe_unused int writeback_align_address(struct l2c_test_thread *data)
++{
++	unsigned char *src;
++	unsigned char *src_org;
++	unsigned char *p;
++	unsigned char *unc_p;
++	int i,j;
++	struct device *dev;
++	dev = (struct device *)kzalloc(sizeof(struct device), GFP_KERNEL);
++	src_org = (unsigned char*)kmalloc(L2C_LINESIZE * 4,GFP_KERNEL);
++
++	if(IS_ERR_OR_NULL(src_org)){
++		src = 0;
++		info("kmalloc error!\n");
++	}else{
++		src = src_org + L2C_LINESIZE;
++		info("%s test addr: %px\n",__func__,src);
++		for(j = 0;j<L2C_LINESIZE;j++) {
++			for(i = 0;i<L2C_LINESIZE * 2;i++){
++				src[i] = i & 255;
++			}
++
++			dma_cache_sync(dev,&src[j],L2C_LINESIZE,DMA_TO_DEVICE);
++			p = src;
++			unc_p = (unsigned char*)TO_UNC(p);
++			//msleep(1);
++			for(i = 0;i<L2C_LINESIZE * 2;i++){
++				if(p >= &src[j] && p < (&src[j] + L2C_LINESIZE)){
++					if(*unc_p != (i & 255)){
++						PALLADIUM_TRIGER();
++						info("Err:addr:%px offset:%d e:0x%02x r:0x%02x\n",src,p-src,i & 255,*(unc_p));
++						return -1;
++					}
++				}else{
++					if(*p != (i & 255)){
++						PALLADIUM_TRIGER();
++						info("Err:addr:%px offset:%d e:0x%02x r:0x%02x\n",src,p-src,i & 255,*(p));
++						return -1;
++					}
++				}
++				p++;
++				unc_p++;
++			}
++			for(i = 0;i<L2C_LINESIZE * 2;i++){
++				src[i] = i & 255;
++			}
++		}
++	}
++	if(src_org)
++		kfree(src_org);
++	return 0;
++}
++
++static __maybe_unused int writeback_align_size(struct l2c_test_thread *data)
++{
++	unsigned char *src;
++	unsigned char *src_org;
++	unsigned char *p;
++	unsigned char *unc_p;
++	int i,j;
++	struct device *dev;
++	dev = (struct device *)kzalloc(sizeof(struct device), GFP_KERNEL);
++	src_org = (unsigned char*)kmalloc(L2C_LINESIZE * 4,GFP_KERNEL);
++	if(IS_ERR_OR_NULL(src_org)){
++		src = 0;
++		info("kmalloc error!\n");
++	}else{
++		src = src_org + L2C_LINESIZE;
++		info("%s test addr: %px\n",__func__,src);
++		for(j = 0;j<L2C_LINESIZE;j++) {
++			unc_p = (unsigned char *)TO_UNC(src);
++			for(i = 0;i<L2C_LINESIZE * 2;i++){
++				unc_p[i] = i & 0xff;
++				__sync();
++				src[i] = i & 0xff;
++			}
++			p = src;
++			for(i = 0;i < L2C_LINESIZE*2-j;i++){
++				*p = 0xff - i;
++				p++;
++			}
++			dma_cache_sync(dev,src,L2C_LINESIZE * 2 - j,DMA_TO_DEVICE);
++			p = src;
++			//msleep(1);
++			for(i = 0;i < L2C_LINESIZE * 2 - j;i++){
++				if(*p != 0xff - i){
++					PALLADIUM_TRIGER();
++					info("Err:addr:%px offset:%d e:0x%02x r:0x%02x\n",src,p-src,0xff - i,*p);
++					return -1;
++				}
++				p++;
++			}
++			for(;i < L2C_LINESIZE * 2;i++){
++				if(*p != (i & 255)){
++					PALLADIUM_TRIGER();
++					info("Err:addr:%px offset:%d e:0x%02x r:0x%02x\n",src,p-src,i & 255,*p);
++					return -1;
++				}
++				p++;
++			}
++		}
++	}
++	if(src_org)
++		kfree(src_org);
++	return 0;
++}
++static __maybe_unused int invalid_align_address(struct l2c_test_thread *data)
++{
++	unsigned char *src_org;
++	unsigned char *src;
++	unsigned char *p;
++	unsigned char *unc_p;
++	int i,j,n;
++	struct device *dev;
++	dev = (struct device *)kzalloc(sizeof(struct device), GFP_KERNEL);
++	src_org = (unsigned char*)kmalloc(L2C_LINESIZE * 5,GFP_KERNEL);
++	if(IS_ERR_OR_NULL(src_org)){
++		src = 0;
++		info("kmalloc error!\n");
++	}else{
++		src = src_org + L2C_LINESIZE;
++		info("%s test addr: %px\n",__func__,src);
++		for(j = 0;j<L2C_LINESIZE;j++) {
++			unc_p = (unsigned char *)TO_UNC(src);
++			for(i = 0;i<L2C_LINESIZE * 3;i++){
++				unc_p[i] = i & 0xff;
++				__sync();
++				src[i] = i & 0xff;
++			}
++
++			dma_cache_sync(dev,&src[j],L2C_LINESIZE * 2,DMA_FROM_DEVICE);
++			p = &src[j];
++			unc_p = (unsigned char*)TO_UNC(p);
++			for(i = 0;i < L2C_LINESIZE * 2;i++){
++				unc_p[i] = 0xff - i;
++				__sync();
++			}
++			//msleep(1);
++			p = src;
++			n = 0;
++			for(i = 0;i<L2C_LINESIZE * 3;i++){
++				if(p >= &src[j] && p < (&src[j] + L2C_LINESIZE * 2)){
++					if(*p != (0xff - n)){
++						PALLADIUM_TRIGER();
++						info("Err:addr:%px offset:%d e:0x%02x r:0x%02x\n",src,p-src,0xff - n,*p);
++						return -1;
++					}
++					n++;
++				}else{
++					if(*p != (i & 255)){
++						PALLADIUM_TRIGER();
++						info("Err:addr:%px offset:%d e:0x%02x r:0x%02x\n",src,p-src,i & 255,*p);
++						return -1;
++					}
++				}
++				p++;
++			}
++			for(i = 0;i<L2C_LINESIZE * 3;i++){
++				src[i] = i & 255;
++			}
++		}
++	}
++	if(src_org)
++		kfree(src_org);
++	return 0;
++}
++static __maybe_unused int invalid_align_size(struct l2c_test_thread *data)
++{
++	unsigned char *src;
++	unsigned char *src_org;
++	unsigned char *p;
++	unsigned char *unc_p;
++	int i,j;
++	struct device *dev;
++	dev = (struct device *)kzalloc(sizeof(struct device), GFP_KERNEL);
++
++	src_org = (unsigned char*)kmalloc(L2C_LINESIZE * 5,GFP_KERNEL);
++	if(IS_ERR_OR_NULL(src_org)){
++		src = 0;
++		info("kmalloc error!\n");
++	}else{
++		src = src_org + L2C_LINESIZE;
++		info("%s test addr: %px\n",__func__,src);
++		for(j = 0;j < L2C_LINESIZE;j++) {
++			for(i = 0;i<L2C_LINESIZE * 3;i++){
++				src[i] = i & 255;
++			}
++			dma_cache_sync(dev,src,L2C_LINESIZE * 3 - j,DMA_FROM_DEVICE);
++			p = src;
++			unc_p = (unsigned char*)TO_UNC(p);
++			for(i = 0;i < L2C_LINESIZE*3-j;i++){
++				*unc_p = 0xff - i;
++				__sync();
++				unc_p++;
++			}
++			//msleep(1);
++			for(i = 0;i < L2C_LINESIZE * 3 - j;i++){
++				if(*p != 0xff - i){
++					PALLADIUM_TRIGER();
++					info("Err:addr:%px offset:%d e:0x%02x r:0x%02x\n",src,p-src,0xff - i,*p);
++					return -1;
++				}
++				p++;
++			}
++			for(;i < L2C_LINESIZE * 3;i++){
++				if(*p != (i & 255)){
++					PALLADIUM_TRIGER();
++					info("Err:addr:%px offset:%d e:0x%02x r:0x%02x\n",src,p-src,i & 255,*p);
++					return -1;
++				}
++				p++;
++			}
++		}
++	}
++	if(src_org)
++		kfree(src_org);
++	return 0;
++}
++static __maybe_unused int blast_invalid_all(struct l2c_test_thread *data)
++{
++	unsigned char *src;
++	unsigned char *src_org;
++	unsigned char *p;
++	unsigned char *unc_p;
++	unsigned char eq;
++	int i,j;
++	struct device *dev;
++	dev = (struct device *)kzalloc(sizeof(struct device), GFP_KERNEL);
++	src_org = (unsigned char*)kmalloc(L2C_SIZE * 2 + L2C_LINESIZE * 2,GFP_KERNEL);
++	if(IS_ERR_OR_NULL(src_org)){
++		src = 0;
++		info("kmalloc error!\n");
++	}else{
++		src = src_org + L2C_LINESIZE;
++		info("%s test addr: %px\n",__func__,src);
++		for(i = 0;i < L2C_SIZE * 2;i++){
++			src[i] = i & 0xff;
++		}
++		dma_cache_sync(dev,src,L2C_SIZE * 2,DMA_FROM_DEVICE);
++		p = src;
++		unc_p = (unsigned char *)TO_UNC(p);
++		for(i = 0;i < L2C_SIZE;i++){
++			unc_p[L2C_SIZE / 2 + i] = 0xff - (i & 0xff);
++			__sync();
++		}
++		//msleep(1);
++		j = 0;
++		for(i = 0;i < L2C_SIZE * 2;i++){
++
++			if((i >= L2C_SIZE / 2) && (i < L2C_SIZE / 2 + L2C_SIZE))
++			{
++				eq = 0xff - (j & 0xff);
++				j++;
++			}else {
++				eq = i & 0xff;
++			}
++			if(p[i] != eq){
++				PALLADIUM_TRIGER();
++				info("Err:addr:%px e:0x%02x r:0x%02x\n",p,eq,p[i]);
++				return -1;
++			}
++		}
++	}
++	if(src_org)
++		kfree(src_org);
++	return 0;
++}
++static __maybe_unused int blast_writeback_all(struct l2c_test_thread *data)
++{
++	unsigned char *src;
++	unsigned char *src_org;
++	unsigned char *p;
++	unsigned char *unc_p;
++	int i;
++	unsigned char eq;
++	struct device *dev;
++	dev = (struct device *)kzalloc(sizeof(struct device), GFP_KERNEL);
++	src_org = (unsigned char*)kmalloc(L2C_SIZE * 2 + L2C_LINESIZE * 2,GFP_KERNEL);
++	if(IS_ERR_OR_NULL(src_org)){
++		src = 0;
++		info("kmalloc error!\n");
++	}else{
++		src = src_org + L2C_LINESIZE;
++		info("%s test addr: %px\n",__func__,src);
++		p = src;
++		unc_p = (unsigned char *)TO_UNC(p);
++		for(i = 0;i < L2C_SIZE;i++){
++			unc_p[L2C_SIZE / 2 + i] = 0xff - (i & 0xff);
++			__sync();
++		}
++		for(i = 0;i < L2C_SIZE * 2;i++){
++			src[i] = i & 0xff;
++		}
++		dma_cache_sync(dev,src,L2C_SIZE * 2,DMA_TO_DEVICE);
++
++		for(i = 0;i < L2C_SIZE * 2;i++){
++			eq = i & 0xff;
++			if(p[i] != eq){
++				PALLADIUM_TRIGER();
++				info("Err:addr:%px e:0x%02x r:0x%02x\n",p,eq,p[i]);
++				return -1;
++			}
++		}
++	}
++	if(src_org)
++		kfree(src_org);
++	return 0;
++}
++
++struct l2c_test{
++	struct dentry		*root;
++	int run;
++	struct mutex		lock;
++	struct mutex		resultlock;
++	struct list_head	top;
++	unsigned int thread_count;
++};
++static TEST_FUNC g_test_func[] ={
++	writeback_align_address,
++	writeback_align_size,
++	invalid_align_address,
++	invalid_align_size,
++	blast_invalid_all,
++	blast_writeback_all
++};
++static int g_thread_id = 0;
++
++
++static int l2c_test_func(void *data)
++{
++	struct l2c_test_thread *thread = data;
++	int index;
++	while (!kthread_should_stop())
++	{
++		printk("d:%px\n",thread->test_func);
++		thread->test_func(thread);
++		index = prandom_u32() % ARRAY_SIZE(g_test_func);
++		thread->test_func = g_test_func[index];
++	}
++	thread->done = 0;
++	return 0;
++}
++
++
++
++static int l2c_test_add_threads(struct l2c_test *l2ctest)
++{
++	struct l2c_test_thread *thread;
++	unsigned int index;
++	thread = (struct l2c_test_thread *)kmalloc(sizeof(struct l2c_test_thread), GFP_KERNEL);
++	if(IS_ERR_OR_NULL(thread)){
++		printk("thread kmalloc failed!\n");
++		return -1;
++	}
++	memset(thread,0,sizeof(struct l2c_test_thread));
++	thread->done = -1;
++	index = prandom_u32() % ARRAY_SIZE(g_test_func);
++	thread->test_func = g_test_func[index];
++	thread->id = g_thread_id;
++	thread->lock = &l2ctest->resultlock;
++	thread->task = kthread_run(l2c_test_func, thread, "l2c_test%d-func%u",g_thread_id++,index);
++	if (IS_ERR(thread->task)) {
++		info("l2c_test: Failed to run thread l2c_test%d-func%u\n",g_thread_id,index);
++		kfree(thread);
++		return -1;
++	}
++	list_add_tail(&thread->list, &l2ctest->top);
++	return 0;
++}
++static void stop_threaded_test(struct l2c_test *l2ctest)
++{
++	struct l2c_test_thread *thread,*_thread;
++
++	list_for_each_entry_safe(thread, _thread, &l2ctest->top, list) {
++		list_del(&thread->list);
++		kthread_stop(thread->task);
++		while(thread->done);
++		kfree(thread);
++	}
++}
++
++static int run_l2c_test(struct l2c_test *l2c)
++{
++	int i = 0;
++	if(l2c->thread_count > 0){
++		for(i = 0;i < l2c->thread_count;i++){
++			l2c_test_add_threads(l2c);
++		}
++	}
++	return 0;
++}
++
++static ssize_t l2c_test_read_run(struct file *file, char __user *user_buf,
++							size_t count, loff_t *ppos)
++{
++	struct l2c_test *l2c = file->private_data;
++	char *buf;
++	mutex_lock(&l2c->lock);
++	if(!list_empty(&l2c->top))
++		buf = "Runing\n";
++	else
++		buf = "Stop\n";
++	mutex_unlock(&l2c->lock);
++	return simple_read_from_buffer(user_buf, count, ppos, buf, strlen(buf));
++}
++static ssize_t l2c_test_write_run(struct file *file, const char __user *user_buf,
++							 size_t count, loff_t *ppos)
++{
++	struct l2c_test *l2c = file->private_data;
++	char buf[16];
++	bool bv;
++	int ret = 0;
++	if (copy_from_user(buf, user_buf, min(count, (sizeof(buf) - 1))))
++		return -EFAULT;
++
++	if (strtobool(buf, &bv) == 0) {
++		mutex_lock(&l2c->lock);
++		if(bv){
++			run_l2c_test(l2c);
++		}else{
++			stop_threaded_test(l2c);
++		}
++		mutex_unlock(&l2c->lock);
++	}
++
++	return ret ? ret : count;
++}
++
++static const struct file_operations l2c_test_run_fops = {
++	.read	= l2c_test_read_run,
++	.write	= l2c_test_write_run,
++	.open	= simple_open,
++	.llseek	= default_llseek,
++};
++struct l2c_test g_l2c_test;
++
++static int __init l2c_test_init(void)
++{
++	struct dentry * d;
++	struct l2c_test *l2c= &g_l2c_test;
++
++	memset(l2c,0,sizeof(struct l2c_test));
++	mutex_init(&l2c->lock);
++	mutex_init(&l2c->resultlock);
++	INIT_LIST_HEAD(&l2c->top);
++	l2c->thread_count = 1;
++
++	d = debugfs_create_dir("l2c_test", NULL);
++	if (IS_ERR(d)){
++		pr_err("create debugfs for l2c_test failed.\n");
++		return PTR_ERR(d);
++	}
++	l2c->root = d;
++
++	debugfs_create_u32("thread_count", S_IWUSR | S_IRUGO, l2c->root,
++						   (u32 *)&l2c->thread_count);
++
++	d = debugfs_create_file("run", S_IWUSR | S_IRUGO, l2c->root,
++							l2c, &l2c_test_run_fops);
++	if (IS_ERR_OR_NULL(d)){
++		pr_err("debugfs create run node failed\n");
++		goto err_node;
++	}
++	pr_info("l2c_test debugfs init ok.\n");
++	return 0;
++err_node:
++	debugfs_remove_recursive(l2c->root);
++	pr_err("l2c_test debugfs init failed.\n");
++	return -1;
++}
++late_initcall(l2c_test_init);
++
++static void __exit l2c_test_deinit(void)
++{
++	struct l2c_test *l2c= &g_l2c_test;
++	stop_threaded_test(l2c);
++	debugfs_remove_recursive(l2c->root);
++}
++module_exit(l2c_test_deinit);
+diff --git a/arch/mips/xburst2/common/cpu_ddr_test/multithread_test.c b/arch/mips/xburst2/common/cpu_ddr_test/multithread_test.c
+new file mode 100644
+index 000000000..1878ed248
+--- /dev/null
++++ b/arch/mips/xburst2/common/cpu_ddr_test/multithread_test.c
+@@ -0,0 +1,258 @@
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/syscore_ops.h>
++#include <linux/slab.h>
++#include <linux/debugfs.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/dma-mapping.h>
++#include <linux/kthread.h>
++#include <linux/delay.h>
++#include <linux/vmalloc.h>
++#include "multithread_test.h"
++struct multithread_test{
++	struct dentry		*root;
++	const char *name;
++	int run;
++	struct mutex		lock;
++	struct mutex		resultlock;
++	struct list_head	thread_top;
++	unsigned int thread_count;
++	struct list_head	func_top;
++};
++struct func_list {
++	struct list_head list;
++	const char *test_name;
++	TEST_FUNC    testfunc;
++	void           *param;
++	atomic_t testcount;
++};
++struct thread_test{
++	struct multithread_test *mt;
++	struct list_head	list;
++	struct task_struct	*task;
++	char thread_name[20];
++	TEST_FUNC test_func;
++	void* param;
++	struct mutex		*lock;
++	volatile int done;
++};
++static int mt_test_func(void *data);
++static int mt_test_add_threads(struct multithread_test *mt)
++{
++	struct thread_test *thread;
++	struct func_list *l_func;
++	struct func_list *min_func = NULL;
++	unsigned int testcount;
++	int retry = 100000;
++
++	if(list_empty(&mt->func_top))
++	{
++		printk("test func list is empty,please add func for multithread test.\n");
++		return -1;
++	}
++
++	thread = (struct thread_test *)vmalloc(sizeof(struct thread_test));
++	if(IS_ERR_OR_NULL(thread)){
++		printk("%s:thread kmalloc failed!\n",mt->name);
++		return -1;
++	}
++	memset(thread,0,sizeof(struct thread_test));
++	thread->done = -1;
++
++	testcount = 0xffffffff;
++	list_for_each_entry(l_func,&mt->func_top,list){
++		unsigned int tc;
++		tc = atomic_read(&l_func->testcount);
++		if(testcount >= tc){
++			min_func = l_func;
++			testcount = tc;
++		}
++	}
++	if(!min_func)
++	{
++		printk("Not find func %s %d\n",__FILE__,__LINE__);
++		goto err_exit;
++	}
++	atomic_inc(&min_func->testcount);
++
++	thread->mt = mt;
++	thread->test_func = min_func->testfunc;
++	thread->param = min_func->param;
++	thread->lock = &mt->resultlock;
++	snprintf(thread->thread_name,sizeof(thread->thread_name),"%s-%d\n",min_func->test_name,atomic_read(&min_func->testcount));
++
++	do {
++		if(retry <= 0) {
++			break;
++		}
++		thread->task = kthread_run(mt_test_func, thread, thread->thread_name);
++		msleep(1);
++
++		retry--;
++
++	} while ((int)thread->task == -EAGAIN);
++
++	if (IS_ERR(thread->task) || (retry == 0)) {
++		printk("%s: Failed to run thread func:%s, retry: %d\n",mt->name,thread->thread_name, retry);
++		goto err_exit;
++	}
++	list_add_tail(&thread->list, &mt->thread_top);
++	return 0;
++err_exit:
++	kfree(thread);
++	return -1;
++}
++
++static int mt_test_func(void *data)
++{
++	struct thread_test *thread = data;
++	while (!kthread_should_stop())
++	{
++		if(thread->test_func(thread->param) == 0)
++		{
++			mutex_lock(&thread->mt->lock);
++			mt_test_add_threads(thread->mt);
++			mutex_unlock(&thread->mt->lock);
++		}
++		break;
++	}
++
++	mutex_lock(&thread->mt->lock);
++	list_del(&thread->list);
++	thread->done = 0;
++	mutex_unlock(&thread->mt->lock);
++
++	vfree(thread);
++	return 0;
++}
++
++static int run_mt_test(struct multithread_test *mt)
++{
++	int i = 0;
++	if(mt->thread_count > 0){
++		for(i = 0;i < mt->thread_count;i++){
++			mt_test_add_threads(mt);
++		}
++	}
++	return 0;
++}
++static void stop_threaded_test(struct multithread_test *mt)
++{
++	struct thread_test *thread,*_thread;
++
++	list_for_each_entry_safe(thread, _thread, &mt->thread_top, list) {
++		list_del(&thread->list);
++		kthread_stop(thread->task);
++		while(thread->done);
++		vfree(thread);
++	}
++}
++
++static ssize_t mt_test_read_run(struct file *file, char __user *user_buf,
++								 size_t count, loff_t *ppos)
++{
++	struct multithread_test *mt = file->private_data;
++	char *buf;
++	mutex_lock(&mt->lock);
++	if(!list_empty(&mt->thread_top))
++		buf = "Runing\n";
++	else
++		buf = "Stop\n";
++	mutex_unlock(&mt->lock);
++	return simple_read_from_buffer(user_buf, count, ppos, buf, strlen(buf));
++}
++static ssize_t mt_test_write_run(struct file *file, const char __user *user_buf,
++								  size_t count, loff_t *ppos)
++{
++	struct multithread_test *mt = file->private_data;
++	char buf[16];
++	bool bv;
++	int ret = 0;
++	if (copy_from_user(buf, user_buf, min(count, (sizeof(buf) - 1))))
++		return -EFAULT;
++
++	if (strtobool(buf, &bv) == 0) {
++		mutex_lock(&mt->lock);
++		if(bv){
++			run_mt_test(mt);
++		}else{
++			stop_threaded_test(mt);
++		}
++		mutex_unlock(&mt->lock);
++	}
++	return ret ? ret : count;
++}
++static const struct file_operations mt_test_run_fops = {
++	.read	= mt_test_read_run,
++	.write	= mt_test_write_run,
++	.open	= simple_open,
++	.llseek	= default_llseek,
++};
++int multithread_test_add_func(void *handle,const char *name,TEST_FUNC testfunc,void *param)
++{
++	struct multithread_test *mt = (struct multithread_test *)handle;
++	struct func_list *funclist = vmalloc(sizeof(struct multithread_test));
++	if(funclist == NULL){
++		printk("add func failed,%s %d\n",__FILE__,__LINE__);
++		return -1;
++	}
++	funclist->test_name = name;
++	funclist->testfunc = testfunc;
++	funclist->param = param;
++	atomic_set(&funclist->testcount,0);
++	list_add_tail(&funclist->list,&mt->func_top);
++	return 0;
++}
++void* multithread_test_init(const char *name,int threadcount)
++{
++	struct dentry * d;
++	struct multithread_test *mt = vmalloc(sizeof(struct multithread_test));
++	if(!mt){
++		pr_err("%s:%s %d alloc struct multithread_test failed!\n",name,__FILE__,__LINE__);
++		return NULL;
++	}
++	memset(mt,0,sizeof(struct multithread_test));
++	mutex_init(&mt->lock);
++	mutex_init(&mt->resultlock);
++	INIT_LIST_HEAD(&mt->thread_top);
++	INIT_LIST_HEAD(&mt->func_top);
++	mt->thread_count = threadcount;
++	mt->name = name;
++	d = debugfs_create_dir(name, NULL);
++	if (IS_ERR(d)){
++		pr_err("create debugfs for %s failed.\n",name);
++		return NULL;
++	}
++	mt->root = d;
++
++	debugfs_create_u32("thread_count", S_IWUSR | S_IRUGO, mt->root,
++						   (u32 *)&mt->thread_count);
++
++	d = debugfs_create_file("run", S_IWUSR | S_IRUGO, mt->root,
++							mt, &mt_test_run_fops);
++	if (IS_ERR_OR_NULL(d)){
++		pr_err("%s:debugfs create run node failed\n",name);
++		goto err_node;
++	}
++	pr_info("%s:debugfs init ok.\n",name);
++	return (void*)mt;
++err_node:
++	debugfs_remove_recursive(mt->root);
++	pr_err("%s:debugfs init failed.\n",name);
++	return NULL;
++}
++
++void multithread_test_deinit(void *handle)
++{
++	struct multithread_test *mt = (struct multithread_test *)handle;
++	struct func_list *funclist,*_funclist;
++	stop_threaded_test(mt);
++	debugfs_remove_recursive(mt->root);
++	list_for_each_entry_safe(funclist, _funclist, &mt->thread_top, list) {
++		list_del(&funclist->list);
++		vfree(funclist);
++	}
++	vfree(mt);
++}
+diff --git a/arch/mips/xburst2/common/cpu_ddr_test/multithread_test.h b/arch/mips/xburst2/common/cpu_ddr_test/multithread_test.h
+new file mode 100644
+index 000000000..4c4223b85
+--- /dev/null
++++ b/arch/mips/xburst2/common/cpu_ddr_test/multithread_test.h
+@@ -0,0 +1,9 @@
++#ifndef _MULTITHREAD_TEST_H_
++#define _MULTITHREAD_TEST_H_
++
++typedef int (*TEST_FUNC)(void *);
++int multithread_test_add_func(void *handle,const char *name,TEST_FUNC testfunc,void *param);
++void* multithread_test_init(const char *name,int threadcount);
++void multithread_test_deinit(void* handle);
++
++#endif /* _MULTITHREAD_TEST_H_ */
+diff --git a/arch/mips/xburst2/common/cpu_ddr_test/raw_dma_test.c b/arch/mips/xburst2/common/cpu_ddr_test/raw_dma_test.c
+new file mode 100644
+index 000000000..ad4b892fe
+--- /dev/null
++++ b/arch/mips/xburst2/common/cpu_ddr_test/raw_dma_test.c
+@@ -0,0 +1,273 @@
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/syscore_ops.h>
++#include <linux/slab.h>
++#include <linux/debugfs.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/dma-mapping.h>
++#include <linux/kthread.h>
++#include <linux/delay.h>
++#include <linux/random.h>
++//#include <mach/jzdma_v13.h>
++
++#include "../../../../../drivers/dma/ingenic/ingenic_dma.h"
++
++const int dma_test_burst_len[] = {1,4,8,16,32,64,128};
++
++struct dma_channel{
++	struct list_head list;
++	struct dma_chan	*chan;
++	unsigned char *desc;
++	unsigned int blen_per_desc;
++};
++
++struct cycle_raw_dma_test{
++	struct dentry		*root;
++	int run;
++	struct mutex		lock;
++	struct list_head	top;
++};
++
++static struct cycle_raw_dma_test g_raw_cycle_dma;
++
++static bool filter(struct dma_chan *chan, void *param)
++{
++#if 0
++	if (!((unsigned int)chan->private == 8)) {
++		return false;
++	}
++#endif
++	return true;
++}
++const static char dcm_tsz[8] = { 1, 2, 0, 0, 3, 4, 5, 6 };
++static inline unsigned int get_max_tsz(unsigned long val, unsigned long *dcmp)
++{
++
++	int ord;
++
++	ord = ffs(val) - 1;
++	if (ord < 0)
++		ord = 0;
++	else if (ord > 7)
++		ord = 7;
++
++	*dcmp &= ~DCM_TSZ_MSK;
++	*dcmp |= dcm_tsz[ord] << DCM_TSZ_SFT;
++
++	/* if tsz == 8, set it to 4 */
++	return ord == 3 ? 4 : 1 << ord;
++}
++static void dump_desc(char *title,struct hdma_desc *desc)
++{
++	printk("=========== %s =========== \n",title);
++	printk("dcm:0x%08lx\n",desc->dcm);
++	printk("dsa:0x%08x\n",(unsigned int)desc->dsa);
++	printk("dta:0x%08x\n",(unsigned int)desc->dta);
++	printk("dtc:0x%08lx\n",desc->dtc);
++	printk("drt:0x%08lx\n",desc->drt);
++
++}
++static void build_desc(unsigned char *desc,int burst,int len)
++{
++	/**
++	 *    4 series A  B  A' B' desc.
++	 *    A desc is transmite (A B) to (A' B')
++	 *    A next desc is B'
++	 *    B desc is transmite (A' B') to (A B)
++	 *    B next desc is A
++	 */
++	unsigned long burst_bits = 0;
++	struct hdma_desc *A = (struct hdma_desc *)desc;
++	struct hdma_desc *B = (struct hdma_desc *)(desc + len * 1);
++	struct hdma_desc *A1 = (struct hdma_desc *)(desc + len * 2);
++	struct hdma_desc *B1 = (struct hdma_desc *)(desc + len * 3);
++	struct device *dev;
++
++	dev = (struct device *)kzalloc(sizeof(struct device), GFP_KERNEL);
++
++	burst = get_max_tsz(burst,&burst_bits);
++	A->dcm = DCM_SAI | DCM_DAI | DCM_LINK | burst_bits;
++	A->dsa = virt_to_phys(A);
++	A->dta = virt_to_phys(A1);
++	A->dtc = (len * 2 / burst) | ((((unsigned int)B1 & 0xff0) >> 4) << 24);
++	A->drt = 8;
++
++	B->dcm = DCM_SAI | DCM_DAI | DCM_LINK | burst_bits;
++	B->dsa = virt_to_phys(A1);
++	B->dta = virt_to_phys(A);
++	B->dtc = (len * 2 / burst) | ((((unsigned int)A & 0xff0) >> 4) << 24);
++	B->drt = 8;
++
++	dump_desc("A",A);
++	dump_desc("B",B);
++	dma_cache_sync(dev,A,len*4,DMA_TO_DEVICE);
++}
++static void start_dma_chans(struct cycle_raw_dma_test *dma)
++{
++	struct dma_channel *ch;
++	list_for_each_entry(ch,&dma->top,list){
++		struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(ch->chan);
++		writel((unsigned int)virt_to_phys(ch->desc), dmac->iomem + CH_DDA);
++		printk("dda:%px->0x%08lx\n",dmac->iomem + CH_DDA,virt_to_phys(ch->desc));
++		/* initiate descriptor fetch */
++		writel(BIT(dmac->id), dmac->engine->iomem + DDRS);
++		printk("ddrs:%px->0x%08lx\n",dmac->engine->iomem + DDRS,BIT(dmac->id));
++		writel(1 | (1 << 30),dmac->iomem + CH_DCS);
++	}
++}
++static void stop_dma_chans(struct cycle_raw_dma_test *dma)
++{
++	struct dma_channel *ch;
++	struct device *dev;
++
++	dev = (struct device *)kzalloc(sizeof(struct device), GFP_KERNEL);
++
++	list_for_each_entry(ch,&dma->top,list){
++		struct hdma_desc *A,*B;
++		struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(ch->chan);
++		int len = ch->blen_per_desc;
++		A = (struct hdma_desc *)(ch->desc);
++		B = (struct hdma_desc *)(ch->desc + len * 1);
++		A->dtc &= ~(0xff << 24);
++		B->dtc &= ~(0xff << 24);
++		dma_cache_sync(dev,A,len*4,DMA_TO_DEVICE);
++		while(readl(dmac->iomem + CH_DCS) & (1 << 3));
++		writel(0,dmac->iomem + CH_DCS);
++	}
++
++}
++static void start_cycle_raw_dma(struct cycle_raw_dma_test *dma)
++{
++	int i;
++	int max;
++	struct dma_channel *ch;
++	struct dma_chan	*chan;
++	dma_cap_mask_t mask;
++	dma_cap_zero(mask);
++	dma_cap_set(DMA_MEMCPY, mask);
++	for(i = 0;i < ARRAY_SIZE(dma_test_burst_len);i++){
++		chan = dma_request_channel(mask, filter, dma);
++		if (!chan) {
++			printk("dma channel request failed! curid = %d, burstlen: %d ignored\n",i,dma_test_burst_len[i]);
++//			break;
++			continue;
++		}
++		if(dma_test_burst_len[i] < 32)
++			max = 32;
++		else
++			max = dma_test_burst_len[i];
++
++		//extra add 16 byte for descriptor align.
++		ch = kmalloc(sizeof(struct dma_channel) + max * 4 + 16,GFP_KERNEL); // max * 4 is  (4's descs)
++		if(IS_ERR_OR_NULL(ch)){
++			pr_err("dma request channel failed!\n");
++			dma_release_channel(chan);
++			break;
++		}
++		ch->chan = chan;
++		ch->desc = (unsigned char*)(((unsigned int)(ch + 1) + 15) / 16 * 16);   // aligned 16 byte for dma descriptor
++		ch->blen_per_desc = max;
++		build_desc(ch->desc,dma_test_burst_len[i],max);
++		list_add_tail(&ch->list,&dma->top);
++	}
++	start_dma_chans(dma);
++}
++static void stop_cycle_raw_dma(struct cycle_raw_dma_test *dma)
++{
++
++	struct list_head *pos;
++	struct list_head *next;
++	struct dma_channel *ch;
++	stop_dma_chans(dma);
++	list_for_each_safe(pos,next,&dma->top){
++		ch = list_entry(pos,struct dma_channel,list);
++		dma_release_channel(ch->chan);
++		list_del(pos);
++		kfree(ch);
++	}
++}
++static int is_stop_cycle_raw_dma(struct cycle_raw_dma_test *dma)
++{
++	return list_empty(&dma->top);
++}
++static ssize_t cycle_raw_dma_test_read_run(struct file *file, char __user *user_buf,
++								 size_t count, loff_t *ppos)
++{
++	struct cycle_raw_dma_test *dma = file->private_data;
++	char *buf;
++	mutex_lock(&dma->lock);
++	if(!is_stop_cycle_raw_dma(dma))
++		buf = "Runing\n";
++	else
++		buf = "Stop\n";
++	mutex_unlock(&dma->lock);
++	return simple_read_from_buffer(user_buf, count, ppos, buf, strlen(buf));
++}
++static ssize_t cycle_raw_dma_test_write_run(struct file *file, const char __user *user_buf,
++								  size_t count, loff_t *ppos)
++{
++	struct cycle_raw_dma_test *dma = file->private_data;
++	char buf[16];
++	bool bv;
++	int ret = 0;
++	if (copy_from_user(buf, user_buf, min(count, (sizeof(buf) - 1))))
++		return -EFAULT;
++
++	if (strtobool(buf, &bv) == 0) {
++		mutex_lock(&dma->lock);
++		if(bv){
++			start_cycle_raw_dma(dma);
++		}else{
++			stop_cycle_raw_dma(dma);
++		}
++		mutex_unlock(&dma->lock);
++	}
++
++	return ret ? ret : count;
++}
++
++static const struct file_operations cycle_raw_dma_test_run_fops = {
++	.read	= cycle_raw_dma_test_read_run,
++	.write	= cycle_raw_dma_test_write_run,
++	.open	= simple_open,
++	.llseek	= default_llseek,
++};
++static int __init cycle_raw_dma_test_init(void)
++{
++	struct dentry * d;
++
++	struct cycle_raw_dma_test *dma= &g_raw_cycle_dma;
++
++	memset(dma,0,sizeof(struct cycle_raw_dma_test));
++	INIT_LIST_HEAD(&dma->top);
++	mutex_init(&dma->lock);
++	d = debugfs_create_dir("cycle_raw_dma_test", NULL);
++	if (IS_ERR(d)){
++		pr_err("create debugfs for cycle_raw_dma_test failed.\n");
++		return PTR_ERR(d);
++	}
++	dma->root = d;
++
++	d = debugfs_create_file("run", S_IWUSR | S_IRUGO, dma->root,
++							dma, &cycle_raw_dma_test_run_fops);
++	if (IS_ERR_OR_NULL(d)){
++		pr_err("debugfs create run node failed\n");
++		goto err_node;
++	}
++	pr_info("cycle raw dma_test debugfs init ok.\n");
++	return 0;
++err_node:
++	debugfs_remove_recursive(dma->root);
++	pr_err("cycle_raw_dma_test debugfs init failed.\n");
++	return -1;
++}
++late_initcall(cycle_raw_dma_test_init);
++
++static void __exit cycle_raw_dma_test_deinit(void)
++{
++	struct cycle_raw_dma_test *dma= &g_raw_cycle_dma;
++	debugfs_remove_recursive(dma->root);
++}
++module_exit(cycle_raw_dma_test_deinit);
+diff --git a/arch/mips/xburst2/common/get-cpu-features.c b/arch/mips/xburst2/common/get-cpu-features.c
+new file mode 100644
+index 000000000..731fbdbce
+--- /dev/null
++++ b/arch/mips/xburst2/common/get-cpu-features.c
+@@ -0,0 +1,98 @@
++/*
++ * Use this function to generate cpu-feature-override.h head file.
++ * Make sure of that, here is no cpu-feature-override.h in mach-xxx directory.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/proc_fs.h>
++#include <linux/seq_file.h>
++#define __ASM_MACH_INGENIC_CPU_FEATURE_OVERRIDES_H__
++#include <asm/cpu-features.h>
++#include <asm/mipsregs.h>
++
++static int cpu_proc_show(struct seq_file *m, void *v)
++{
++
++#define PRINT(ARGS...) seq_printf (m, ##ARGS)
++
++#define PRT0(X,Y) PRINT("#define " "%s()\t(%d * 1024)\n",#X,(Y)/1024)
++#define PRT1(X,Y) PRINT("#define " "%s()\t%d\n",#X,(Y))
++	PRT0(cpu_dcache_size,(1<<current_cpu_data.dcache.waybit)*current_cpu_data.dcache.ways);
++	PRT1(cpu_dcache_ways,current_cpu_data.dcache.ways);
++	PRT1(cpu_dcache_line_size,current_cpu_data.dcache.linesz);
++
++	PRT0(cpu_icache_size,(1<<current_cpu_data.icache.waybit)*current_cpu_data.icache.ways);
++	PRT1(cpu_icache_ways,current_cpu_data.icache.ways);
++	PRT1(cpu_icache_line_size,current_cpu_data.icache.linesz);
++
++#define PRT2(X) PRINT("#define " "%-30s\t%d\n",#X,X? 1: 0)
++	PRT2(cpu_has_tlb);
++	PRT2(cpu_has_4kex);
++	PRT2(cpu_has_3k_cache);
++	PRT2(cpu_has_4k_cache);
++	PRT2(cpu_has_tx39_cache);
++	PRT2(cpu_has_fpu);
++	PRT2(cpu_has_32fpr);
++	PRT2(cpu_has_counter);
++	PRT2(cpu_has_watch);
++	PRT2(cpu_has_divec);
++	PRT2(cpu_has_vce);
++	PRT2(cpu_has_cache_cdex_p);
++	PRT2(cpu_has_cache_cdex_s);
++	PRT2(cpu_has_prefetch);
++	PRT2(cpu_has_mcheck);
++	PRT2(cpu_has_ejtag);
++	PRT2(cpu_has_llsc);
++	PRT2(cpu_has_mips16);
++	PRT2(cpu_has_mdmx);
++	PRT2(cpu_has_mips3d);
++	PRT2(cpu_has_smartmips);
++	PRT2(cpu_has_vtag_icache);
++	PRT2(cpu_has_dc_aliases);
++	PRT2(cpu_has_ic_fills_f_dc);
++	PRT2(cpu_has_pindexed_dcache);
++	PRT2(cpu_icache_snoops_remote_store);
++	PRT2(cpu_has_mips32r1);
++	PRT2(cpu_has_mips32r2);
++	PRT2(cpu_has_mips64r1);
++	PRT2(cpu_has_mips64r2);
++	PRT2(cpu_has_dsp);
++	PRT2(cpu_has_mipsmt);
++	PRT2(cpu_has_userlocal);
++	PRT2(cpu_has_nofpuex);
++	PRT2(cpu_has_64bits);
++	PRT2(cpu_has_64bit_zero_reg);
++	PRT2(cpu_has_vint);
++	PRT2(cpu_has_veic);
++	PRT2(cpu_has_inclusive_pcaches);
++
++	PRINT("\n");
++	PRINT("cp0 prid:\t%08x\n",read_c0_prid());
++	PRINT("cp0 config0:\t%08x\n",read_c0_config());
++	PRINT("cp0 config1:\t%08x\n",read_c0_config1());
++	PRINT("cp0 config2:\t%08x\n",read_c0_config2());
++	PRINT("cp0 config3:\t%08x\n",read_c0_config3());
++	PRINT("cp0 config4:\t%08x\n",read_c0_config4());
++
++	return 0;
++}
++
++static int cpu_open(struct inode *inode, struct file *file)
++{
++	return single_open(file, cpu_proc_show, PDE_DATA(inode));
++}
++static const struct proc_ops cpu_proc_fops ={
++	.proc_read = seq_read,
++	.proc_open = cpu_open,
++	.proc_lseek = seq_lseek,
++	.proc_release = single_release,
++};
++static int __init init_cpu_features(void)
++{
++	proc_create("cpu-feature-override",0444,NULL,&cpu_proc_fops);
++
++	return 0;
++}
++
++module_init(init_cpu_features);
+diff --git a/arch/mips/xburst2/common/initrd-check.c b/arch/mips/xburst2/common/initrd-check.c
+new file mode 100644
+index 000000000..207555fef
+--- /dev/null
++++ b/arch/mips/xburst2/common/initrd-check.c
+@@ -0,0 +1,58 @@
++
++#include <linux/init.h>
++#include <linux/stat.h>
++#include <linux/kdev_t.h>
++#include <linux/syscalls.h>
++
++static void check_file(char *fname)
++{
++	int err;
++	pr_info("check file %s ... ",fname);
++	err = sys_access((const char __user *) fname, O_RDONLY);
++	if (err < 0)
++		pr_info("failed %d.\n", err);
++	else
++		pr_info("successed.\n");
++}
++
++static int __init check_rootfs(void)
++{
++	int err;
++
++	if (sys_access((const char __user *) "/dev", O_RDWR) < 0) {
++		pr_info("Dir /dev is not exist.\n");
++		sys_mkdir((const char __user *) "/dev", O_RDWR);
++	}
++
++	if (sys_access((const char __user *) "/dev/console", O_RDWR) < 0) {
++		printk("create /dev/console\n");
++		err = sys_mknod((const char __user __force *) "/dev/console",
++				S_IFCHR | S_IRUSR | S_IWUSR,
++				new_encode_dev(MKDEV(5, 1)));
++		if (err < 0)
++			goto out;
++	}
++
++	if (sys_access((const char __user *) "/dev/null", O_RDWR) < 0) {
++		printk("create /dev/null\n");
++		err = sys_mknod((const char __user __force *) "/dev/null",
++				S_IFCHR | S_IRUSR | S_IWUSR,
++				new_encode_dev(MKDEV(1, 3)));
++		if (err < 0)
++			goto out;
++	}
++
++	check_file("/linuxrc");
++	check_file("/init");
++	check_file("/init.rc");
++	check_file("/sbin/adbd");
++	check_file("/bin/busybox");
++
++	return 0;
++
++out:
++	printk(KERN_WARNING "Failed to create dev\n");
++	return err;
++}
++
++late_initcall(check_rootfs);
+diff --git a/arch/mips/xburst2/common/mxuv3.c b/arch/mips/xburst2/common/mxuv3.c
+new file mode 100644
+index 000000000..e19cf46db
+--- /dev/null
++++ b/arch/mips/xburst2/common/mxuv3.c
+@@ -0,0 +1,697 @@
++#include <linux/sched/task_stack.h>
++#include <linux/ptrace.h>
++#include <linux/sched.h>
++#include <asm/processor.h>
++#include <mxuv3.h>
++
++#define WORDCODE
++
++#pragma clang optimize off
++/*__attribute__((optimize("O0")))*/
++void __init_mxuv3(void)
++{
++	unsigned int register val asm("t0");
++	val = 0;
++	/* open mxuv3 and set thread status ST0_CU2 */
++	set_c0_status(ST0_CU2);
++	KSTK_STATUS(current) |= ST0_CU2;
++	//printk("%s(%d):smp_processor_id()=%d, read_c0_status()=0x%x, task_cpu(current)=%d, KSTK_STATUS(current)=0x%lx, current->tgid=%d, current->pid=%d\n", __func__, __LINE__, smp_processor_id(), read_c0_status(), task_cpu(current), KSTK_STATUS(current), current->tgid, current->pid);
++
++	/* dump mxuv3 control and status register */
++#ifdef WORDCODE
++	//asm volatile(".word	0x70100203 | (0x0 << 11)\n\t":"=r"(val));
++	//printk("%s(%d):smp_processor_id()=%d, read_c0_status()=0x%x, KSTK_STATUS(current)=0x%lx, current->tgid=%d, current->pid=%d, mir=0x%x\n", __func__, __LINE__, smp_processor_id(), read_c0_status(), KSTK_STATUS(current), current->tgid, current->pid, val);
++	//asm volatile(".word	0x70100203 | (0x1 << 11) \n\t":"=r"(val));
++	//printk("%s(%d):smp_processor_id()=%d, read_c0_status()=0x%x, KSTK_STATUS(current)=0x%lx, current->tgid=%d, current->pid=%d, mscr=0x%x\n", __func__, __LINE__, smp_processor_id(), read_c0_status(), KSTK_STATUS(current), current->tgid, current->pid, val);
++	//dump_stack();
++#else
++	CFCMXU(val, 0);
++	printk("mir=0x%x\n", val);
++	CFCMXU(val, 1);
++	printk("mcsr=0x%x\n", val);
++#endif
++}
++
++/*__attribute__((optimize("O0")))*/
++void __save_mxuv3(void *tsk_void)
++{
++	register void *base asm("t0");
++#ifndef WORDCODE
++	register void *base1 asm("t1");
++#endif
++	struct task_struct *tsk = tsk_void;
++	struct xburst_mxu_struct *mxu = &tsk->thread.mxu;
++	//printk("%s(%d):smp_processor_id()=%d, read_c0_status()=0x%x, KSTK_STATUS(current)=0x%lx, current->tgid=%d, current->pid=%d, , KSTK_STATUS(tsk)=0x%lx, task->tgid=%d, task->pid=%d\n", __func__, __LINE__, smp_processor_id(), read_c0_status(), KSTK_STATUS(current), current->tgid, current->pid, KSTK_STATUS(tsk), tsk->tgid, tsk->pid);
++	//dump_stack();
++	//printk("%s(%d):smp_processor_id()=%d, read_c0_status()=0x%x, task_cpu(current)=%d, KSTK_STATUS(current)=0x%lx, current->tgid=%d, current->pid=%d, task_cpu(p)=%d, KSTK_STATUS(p)=0x%lx, p->tgid=%d, p->pid=%d\n", __func__, __LINE__, smp_processor_id(), read_c0_status(), task_cpu(current), KSTK_STATUS(current), current->tgid, current->pid, task_cpu(tsk), KSTK_STATUS(tsk), tsk->tgid, tsk->pid);
++#ifdef WORDCODE
++	/**
++	 * sao ins: hex(0x700000d5 | 8 << 21 | 1 << 16 | 0 << 11 | 1 << 9)
++	 * 0x700000d5   ->sa0
++	 * 8            ->t0
++	 * 1            ->32>>5
++	 * 0            ->vpr0
++	 * 1            ->nn    // o means to be divided by 512/256=2, so n=[0,1]
++	 * because t0 is fixed, so 0x700000d5 | 8 << 21 = 0x710000d5
++	 * so the word format as follows:
++	 * asm volatile(".word	0x710000d5 | offset << 16 | vprn << 11 | n << 9 \n\t");
++	 * mfsum ins: hex(0x4a60000f | vss << 11 | vrd << 7)
++	 * for we fixed vrd to 0, so the word format as follows:
++	 * asm volatile(".word 0x4a60000f | vss << 11 \n\t");
++	 */
++	base = &mxu->vpr[0];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 0 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 0 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[1];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 1 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 1 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[2];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 2 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 2 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[3];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 3 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 3 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[4];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 4 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 4 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[5];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 5 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 5 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[6];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 6 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 6 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[7];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 7 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 7 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[8];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 8 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 8 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[9];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 9 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 9 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[10];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 10 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 10 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[11];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 11 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 11 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[12];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 12 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 12 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[13];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 13 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 13 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[14];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 14 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 14 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[15];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 15 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 15 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[16];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 16 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 16 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[17];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 17 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 17 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[18];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 18 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 18 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[19];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 19 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 19 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[20];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 20 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 20 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[21];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 21 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 21 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[22];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 22 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 22 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[23];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 23 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 23 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[24];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 24 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 24 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[25];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 25 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 25 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[26];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 26 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 26 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[27];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 27 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 27 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[28];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 28 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 28 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[29];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 29 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 29 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[30];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 30 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 30 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vpr[31];
++	asm volatile(".word	0x710000d5 | 0 << 16 | 31 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 31 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vsr[0];
++	asm volatile(".word 0x4a60000f | 0 << 11 \n\t");
++	asm volatile(".word	0x710000d5 | 0 << 16 | 0 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 0 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vsr[1];
++	asm volatile(".word 0x4a60000f | 1 << 11 \n\t");
++	asm volatile(".word	0x710000d5 | 0 << 16 | 0 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 0 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vsr[2];
++	asm volatile(".word 0x4a60000f | 2 << 11 \n\t");
++	asm volatile(".word	0x710000d5 | 0 << 16 | 0 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 0 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->vsr[3];
++	asm volatile(".word 0x4a60000f | 3 << 11 \n\t");
++	asm volatile(".word	0x710000d5 | 0 << 16 | 0 << 11 | 0 << 9 \n\t");
++	asm volatile(".word	0x710000d5 | 1 << 16 | 0 << 11 | 1 << 9 \n\t");
++
++	base = &mxu->csr;
++	asm volatile(".word	0x7010f803 | 9 << 6 \n\t"); // t1 <- mxu.csr
++	asm volatile(".word	0xac000000 | 8 << 21 | 9 << 16 \n\t"); // sw $t1 0($t0)
++#else
++	base = &mxu->vpr[0];
++	SA(o, VR0, 0, base, 0);
++	SA(o, VR0, 1, base, 32);
++
++	base = &mxu->vpr[1];
++	SA(o, VR1, 0, base, 0);
++	SA(o, VR1, 1, base, 32);
++
++	base = &mxu->vpr[2];
++	SA(o, VR2, 0, base, 0);
++	SA(o, VR2, 1, base, 32);
++
++	base = &mxu->vpr[3];
++	SA(o, VR3, 0, base, 0);
++	SA(o, VR3, 1, base, 32);
++
++	base = &mxu->vpr[4];
++	SA(o, VR4, 0, base, 0);
++	SA(o, VR4, 1, base, 32);
++
++	base = &mxu->vpr[5];
++	SA(o, VR5, 0, base, 0);
++	SA(o, VR5, 1, base, 32);
++
++	base = &mxu->vpr[6];
++	SA(o, VR6, 0, base, 0);
++	SA(o, VR6, 1, base, 32);
++
++	base = &mxu->vpr[7];
++	SA(o, VR7, 0, base, 0);
++	SA(o, VR7, 1, base, 32);
++
++	base = &mxu->vpr[8];
++	SA(o, VR8, 0, base, 0);
++	SA(o, VR8, 1, base, 32);
++
++	base = &mxu->vpr[9];
++	SA(o, VR9, 0, base, 0);
++	SA(o, VR9, 1, base, 32);
++
++	base = &mxu->vpr[10];
++	SA(o, VR10, 0, base, 0);
++	SA(o, VR10, 1, base, 32);
++
++	base = &mxu->vpr[11];
++	SA(o, VR11, 0, base, 0);
++	SA(o, VR11, 1, base, 32);
++
++	base = &mxu->vpr[12];
++	SA(o, VR12, 0, base, 0);
++	SA(o, VR12, 1, base, 32);
++
++	base = &mxu->vpr[13];
++	SA(o, VR13, 0, base, 0);
++	SA(o, VR13, 1, base, 32);
++
++	base = &mxu->vpr[14];
++	SA(o, VR14, 0, base, 0);
++	SA(o, VR14, 1, base, 32);
++
++	base = &mxu->vpr[15];
++	SA(o, VR15, 0, base, 0);
++	SA(o, VR15, 1, base, 32);
++
++	base = &mxu->vpr[16];
++	SA(o, VR16, 0, base, 0);
++	SA(o, VR16, 1, base, 32);
++
++	base = &mxu->vpr[17];
++	SA(o, VR17, 0, base, 0);
++	SA(o, VR17, 1, base, 32);
++
++	base = &mxu->vpr[18];
++	SA(o, VR18, 0, base, 0);
++	SA(o, VR18, 1, base, 32);
++
++	base = &mxu->vpr[19];
++	SA(o, VR19, 0, base, 0);
++	SA(o, VR19, 1, base, 32);
++
++	base = &mxu->vpr[20];
++	SA(o, VR20, 0, base, 0);
++	SA(o, VR20, 1, base, 32);
++
++	base = &mxu->vpr[21];
++	SA(o, VR21, 0, base, 0);
++	SA(o, VR21, 1, base, 32);
++
++	base = &mxu->vpr[22];
++	SA(o, VR22, 0, base, 0);
++	SA(o, VR22, 1, base, 32);
++
++	base = &mxu->vpr[23];
++	SA(o, VR23, 0, base, 0);
++	SA(o, VR23, 1, base, 32);
++
++	base = &mxu->vpr[24];
++	SA(o, VR24, 0, base, 0);
++	SA(o, VR24, 1, base, 32);
++
++	base = &mxu->vpr[25];
++	SA(o, VR25, 0, base, 0);
++	SA(o, VR25, 1, base, 32);
++
++	base = &mxu->vpr[26];
++	SA(o, VR26, 0, base, 0);
++	SA(o, VR26, 1, base, 32);
++
++	base = &mxu->vpr[27];
++	SA(o, VR27, 0, base, 0);
++	SA(o, VR27, 1, base, 32);
++
++	base = &mxu->vpr[28];
++	SA(o, VR28, 0, base, 0);
++	SA(o, VR28, 1, base, 32);
++
++	base = &mxu->vpr[29];
++	SA(o, VR29, 0, base, 0);
++	SA(o, VR29, 1, base, 32);
++
++	base = &mxu->vpr[30];
++	SA(o, VR30, 0, base, 0);
++	SA(o, VR30, 1, base, 32);
++
++	base = &mxu->vpr[31];
++	SA(o, VR31, 0, base, 0);
++	SA(o, VR31, 1, base, 32);
++
++	base = &mxu->vsr[0];
++	MFSUM(VR0, VS0);
++	SA(o, VR0, 0, base, 0);
++	SA(o, VR0, 1, base, 32);
++
++	base = &mxu->vsr[1];
++	MFSUM(VR0, VS1);
++	SA(o, VR0, 0, base, 0);
++	SA(o, VR0, 1, base, 32);
++
++	base = &mxu->vsr[2];
++	MFSUM(VR0, VS2);
++	SA(o, VR0, 0, base, 0);
++	SA(o, VR0, 1, base, 32);
++
++	base = &mxu->vsr[3];
++	MFSUM(VR0, VS3);
++	SA(o, VR0, 0, base, 0);
++	SA(o, VR0, 1, base, 32);
++
++	base = &mxu->csr;
++	CFCMXU(base1, 31);
++	asm volatile("sw $t1, 0($t0)\n\t");
++#endif
++}
++
++/*__attribute__((optimize("O0")))*/
++void __restore_mxuv3(void * tsk_void)
++{
++	register void *base asm("t0");
++	struct task_struct *tsk = tsk_void;
++	struct xburst_mxu_struct *mxu = &tsk->thread.mxu;
++	//printk("%s(%d):smp_processor_id()=%d, read_c0_status()=0x%x, KSTK_STATUS(current)=0x%lx, current->tgid=%d, current->pid=%d, , KSTK_STATUS(tsk)=0x%lx, task->tgid=%d, task->pid=%d\n", __func__, __LINE__, smp_processor_id(), read_c0_status(), KSTK_STATUS(current), current->tgid, current->pid, KSTK_STATUS(tsk), tsk->tgid, tsk->pid);
++	//dump_stack();
++	//printk("%s(%d):smp_processor_id()=%d, read_c0_status()=0x%x, task_cpu(current)=%d, KSTK_STATUS(current)=0x%lx, current->tgid=%d, current->pid=%d, task_cpu(p)=%d, KSTK_STATUS(p)=0x%lx, p->tgid=%d, p->pid=%d\n", __func__, __LINE__, smp_processor_id(), read_c0_status(), task_cpu(current), KSTK_STATUS(current), current->tgid, current->pid, task_cpu(tsk), KSTK_STATUS(tsk), tsk->tgid, tsk->pid);
++#ifdef WORDCODE
++	/**
++	 * lao ins: hex(0x70001811 | 8 << 21 | 1 << 16 | 1 << 14 | 0 << 6)
++	 * cmd:     0x70001811   ->la0
++	 * base:    8            ->t0
++	 * offset:  1            ->32>>5
++	 * nn:      1            ->nn    // o means to be divided by 512/256=2, so n=[0,1]
++	 * vpr:     0            ->vpr0
++	 * because t0 is fixed, so 0x70001811 | 8 << 21 = 0x71001811
++	 * so the word format as follows:
++	 * asm volatile(".word	0x71001811 | offset << 16 | n << 14 | vprn << 6 \n\t");
++	 *
++	 * mtsum ins: hex(0x4a60001d | vrs << 16 | vsd << 6)
++	 * for we fixed vrs to 0, so the word format as follows:
++	 * asm volatile(".word 0x4a60001d | vss << 6 \n\t");
++	 */
++	base = &mxu->csr;
++	asm volatile(".word 0x8c000000 | 8 << 21 | 9 << 16\n\t");// lw $t1, 0($t0)
++	asm volatile(".word 0x7011f803 | 9 << 21 \n\t");// mxu.csr <- t1
++
++	base = &mxu->vsr[0];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 0 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 0 << 6 \n\t");
++	asm volatile(".word 0x4a60001d | 0 << 6 \n\t");
++
++	base = &mxu->vsr[1];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 0 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 0 << 6 \n\t");
++	asm volatile(".word 0x4a60001d | 1 << 6 \n\t");
++
++	base = &mxu->vsr[2];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 0 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 0 << 6 \n\t");
++	asm volatile(".word 0x4a60001d | 2 << 6 \n\t");
++
++	base = &mxu->vsr[3];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 0 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 0 << 6 \n\t");
++	asm volatile(".word 0x4a60001d | 3 << 6 \n\t");
++
++	base = &mxu->vpr[0];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 0 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 0 << 6 \n\t");
++
++	base = &mxu->vpr[1];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 1 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 1 << 6 \n\t");
++
++	base = &mxu->vpr[2];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 2 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 2 << 6 \n\t");
++
++	base = &mxu->vpr[3];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 3 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 3 << 6 \n\t");
++
++	base = &mxu->vpr[4];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 4 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 4 << 6 \n\t");
++
++	base = &mxu->vpr[5];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 5 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 5 << 6 \n\t");
++
++	base = &mxu->vpr[6];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 6 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 6 << 6 \n\t");
++
++	base = &mxu->vpr[7];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 7 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 7 << 6 \n\t");
++
++	base = &mxu->vpr[8];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 8 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 8 << 6 \n\t");
++
++	base = &mxu->vpr[9];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 9 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 9 << 6 \n\t");
++
++	base = &mxu->vpr[10];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 10 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 10 << 6 \n\t");
++
++	base = &mxu->vpr[11];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 11 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 11 << 6 \n\t");
++
++	base = &mxu->vpr[12];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 12 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 12 << 6 \n\t");
++
++	base = &mxu->vpr[13];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 13 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 13 << 6 \n\t");
++
++	base = &mxu->vpr[14];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 14 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 14 << 6 \n\t");
++
++	base = &mxu->vpr[15];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 15 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 15 << 6 \n\t");
++
++	base = &mxu->vpr[16];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 16 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 16 << 6 \n\t");
++
++	base = &mxu->vpr[17];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 17 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 17 << 6 \n\t");
++
++	base = &mxu->vpr[18];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 18 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 18 << 6 \n\t");
++
++	base = &mxu->vpr[19];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 19 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 19 << 6 \n\t");
++
++	base = &mxu->vpr[20];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 20 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 20 << 6 \n\t");
++
++	base = &mxu->vpr[21];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 21 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 21 << 6 \n\t");
++
++	base = &mxu->vpr[22];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 22 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 22 << 6 \n\t");
++
++	base = &mxu->vpr[23];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 23 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 23 << 6 \n\t");
++
++	base = &mxu->vpr[24];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 24 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 24 << 6 \n\t");
++
++	base = &mxu->vpr[25];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 25 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 25 << 6 \n\t");
++
++	base = &mxu->vpr[26];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 26 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 26 << 6 \n\t");
++
++	base = &mxu->vpr[27];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 27 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 27 << 6 \n\t");
++
++	base = &mxu->vpr[28];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 28 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 28 << 6 \n\t");
++
++	base = &mxu->vpr[29];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 29 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 29 << 6 \n\t");
++
++	base = &mxu->vpr[30];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 30 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 30 << 6 \n\t");
++
++	base = &mxu->vpr[31];
++	asm volatile(".word	0x71001811 | 0 << 16 | 0 << 14 | 31 << 6 \n\t");
++	asm volatile(".word	0x71001811 | 1 << 16 | 1 << 14 | 31 << 6 \n\t");
++#else
++	base = &mxu->csr;
++	asm volatile("lw $t1, 0($t0)\n\t");
++	CTCMXU(31, base1);
++
++	base = &mxu->vsr[0];
++	LA(o, VR0, 0, base, 0);
++	LA(o, VR0, 1, base, 32);
++	MTSUM(VS0, VR0);
++
++	base = &mxu->vsr[1];
++	LA(o, VR0, 0, base, 0);
++	LA(o, VR0, 1, base, 32);
++	MTSUM(VS1, VR0);
++
++	base = &mxu->vsr[2];
++	LA(o, VR0, 0, base, 0);
++	LA(o, VR0, 1, base, 32);
++	MTSUM(VS2, VR0);
++
++	base = &mxu->vsr[3];
++	LA(o, VR0, 0, base, 0);
++	LA(o, VR0, 1, base, 32);
++	MTSUM(VS3, VR0);
++
++	base = &mxu->vpr[0];
++	LA(o, VR0, 0, base, 0);
++	LA(o, VR0, 1, base, 32);
++
++	base = &mxu->vpr[1];
++	LA(o, VR1, 0, base, 0);
++	LA(o, VR1, 1, base, 32);
++
++	base = &mxu->vpr[2];
++	LA(o, VR2, 0, base, 0);
++	LA(o, VR2, 1, base, 32);
++
++	base = &mxu->vpr[3];
++	LA(o, VR3, 0, base, 0);
++	LA(o, VR3, 1, base, 32);
++
++	base = &mxu->vpr[4];
++	LA(o, VR4, 0, base, 0);
++	LA(o, VR4, 1, base, 32);
++
++	base = &mxu->vpr[5];
++	LA(o, VR5, 0, base, 0);
++	LA(o, VR5, 1, base, 32);
++
++	base = &mxu->vpr[6];
++	LA(o, VR6, 0, base, 0);
++	LA(o, VR6, 1, base, 32);
++
++	base = &mxu->vpr[7];
++	LA(o, VR7, 0, base, 0);
++	LA(o, VR7, 1, base, 32);
++
++	base = &mxu->vpr[8];
++	LA(o, VR8, 0, base, 0);
++	LA(o, VR8, 1, base, 32);
++
++	base = &mxu->vpr[9];
++	LA(o, VR9, 0, base, 0);
++	LA(o, VR9, 1, base, 32);
++
++	base = &mxu->vpr[10];
++	LA(o, VR10, 0, base, 0);
++	LA(o, VR10, 1, base, 32);
++
++	base = &mxu->vpr[11];
++	LA(o, VR11, 0, base, 0);
++	LA(o, VR11, 1, base, 32);
++
++	base = &mxu->vpr[12];
++	LA(o, VR12, 0, base, 0);
++	LA(o, VR12, 1, base, 32);
++
++	base = &mxu->vpr[13];
++	LA(o, VR13, 0, base, 0);
++	LA(o, VR13, 1, base, 32);
++
++	base = &mxu->vpr[14];
++	LA(o, VR14, 0, base, 0);
++	LA(o, VR14, 1, base, 32);
++
++	base = &mxu->vpr[15];
++	LA(o, VR15, 0, base, 0);
++	LA(o, VR15, 1, base, 32);
++
++	base = &mxu->vpr[16];
++	LA(o, VR16, 0, base, 0);
++	LA(o, VR16, 1, base, 32);
++
++	base = &mxu->vpr[17];
++	LA(o, VR17, 0, base, 0);
++	LA(o, VR17, 1, base, 32);
++
++	base = &mxu->vpr[18];
++	LA(o, VR18, 0, base, 0);
++	LA(o, VR18, 1, base, 32);
++
++	base = &mxu->vpr[19];
++	LA(o, VR19, 0, base, 0);
++	LA(o, VR19, 1, base, 32);
++
++	base = &mxu->vpr[20];
++	LA(o, VR20, 0, base, 0);
++	LA(o, VR20, 1, base, 32);
++
++	base = &mxu->vpr[21];
++	LA(o, VR21, 0, base, 0);
++	LA(o, VR21, 1, base, 32);
++
++	base = &mxu->vpr[22];
++	LA(o, VR22, 0, base, 0);
++	LA(o, VR22, 1, base, 32);
++
++	base = &mxu->vpr[23];
++	LA(o, VR23, 0, base, 0);
++	LA(o, VR23, 1, base, 32);
++
++	base = &mxu->vpr[24];
++	LA(o, VR24, 0, base, 0);
++	LA(o, VR24, 1, base, 32);
++
++	base = &mxu->vpr[25];
++	LA(o, VR25, 0, base, 0);
++	LA(o, VR25, 1, base, 32);
++
++	base = &mxu->vpr[26];
++	LA(o, VR26, 0, base, 0);
++	LA(o, VR26, 1, base, 32);
++
++	base = &mxu->vpr[27];
++	LA(o, VR27, 0, base, 0);
++	LA(o, VR27, 1, base, 32);
++
++	base = &mxu->vpr[28];
++	LA(o, VR28, 0, base, 0);
++	LA(o, VR28, 1, base, 32);
++
++	base = &mxu->vpr[29];
++	LA(o, VR29, 0, base, 0);
++	LA(o, VR29, 1, base, 32);
++
++	base = &mxu->vpr[30];
++	LA(o, VR30, 0, base, 0);
++	LA(o, VR30, 1, base, 32);
++
++	base = &mxu->vpr[31];
++	LA(o, VR31, 0, base, 0);
++	LA(o, VR31, 1, base, 32);
++#endif
++}
+diff --git a/arch/mips/xburst2/common/proc.c b/arch/mips/xburst2/common/proc.c
+new file mode 100644
+index 000000000..a32e05820
+--- /dev/null
++++ b/arch/mips/xburst2/common/proc.c
+@@ -0,0 +1,92 @@
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/sysctl.h>
++#include <linux/proc_fs.h>
++#include <linux/fs.h>
++#include <linux/slab.h>
++#include <linux/seq_file.h>
++#include <linux/page-flags.h>
++#include <asm/uaccess.h>
++#include <ingenic_proc.h>
++static struct proc_dir_entry *proc_jz_root;
++struct proc_dir_entry * jz_proc_mkdir(char *s)
++{
++	struct proc_dir_entry *p;
++	if(!proc_jz_root) {
++		proc_jz_root = proc_mkdir("jz", 0);
++		if(!proc_jz_root)
++			return NULL;
++	}
++	p = proc_mkdir(s,proc_jz_root);
++	return p;
++}
++
++EXPORT_SYMBOL(jz_proc_mkdir);
++
++static int jz_proc_show(struct seq_file *filq, void *v)
++{
++	int ret = 1;
++	struct jz_single_file_ops *proc_fops = filq->private;
++	filq->private = proc_fops->data;
++
++	if(proc_fops->read)
++		ret = proc_fops->read(filq, v);
++
++	filq->private = proc_fops;
++	return ret;
++}
++static int jz_proc_open(struct inode *inode, struct file *file)
++{
++	return single_open(file, jz_proc_show, PDE_DATA(inode));
++}
++static ssize_t jz_proc_write(struct file *file, const char __user *buffer, size_t usize, loff_t *off)
++{
++	size_t ret;
++	struct jz_single_file_ops *proc_fops = ((struct seq_file *)file->private_data)->private;
++	((struct seq_file *)file->private_data)->private = proc_fops->data;
++
++	ret = proc_fops->write(file, buffer, usize, off);
++	((struct seq_file *)file->private_data)->private = proc_fops;
++
++	return ret;
++}
++
++struct proc_dir_entry *jz_proc_create_data(
++	const char *name, umode_t mode, struct proc_dir_entry *parent,
++	struct jz_single_file_ops *proc_fops, void *data)
++{
++	struct proc_ops *jz_proc_fops;
++
++	jz_proc_fops = kmalloc(sizeof(struct proc_ops), GFP_KERNEL);
++	if(!jz_proc_fops) {
++		return NULL;
++	}
++
++	jz_proc_fops->proc_read = seq_read;
++	jz_proc_fops->proc_lseek = seq_lseek;
++	jz_proc_fops->proc_release = single_release;
++	jz_proc_fops->proc_open = jz_proc_open;
++	jz_proc_fops->proc_write = jz_proc_write;
++	proc_fops->data = data;
++
++	return proc_create_data(name, mode, parent, jz_proc_fops, proc_fops);
++}
++
++struct proc_dir_entry *jz_proc_create(
++	const char *name, umode_t mode, struct proc_dir_entry *parent,
++	struct jz_single_file_ops *proc_fops)
++{
++	return jz_proc_create_data(name, mode, parent, proc_fops, NULL);
++}
++
++struct proc_dir_entry * get_jz_proc_root(void)
++{
++	if(!proc_jz_root) {
++		proc_jz_root = proc_mkdir("jz", 0);
++		if(!proc_jz_root)
++			return NULL;
++	}
++	return proc_jz_root;
++}
+diff --git a/arch/mips/xburst2/core/Makefile b/arch/mips/xburst2/core/Makefile
+new file mode 100644
+index 000000000..f24f8fa4d
+--- /dev/null
++++ b/arch/mips/xburst2/core/Makefile
+@@ -0,0 +1,4 @@
++obj-y += prom.o
++
++obj-$(CONFIG_XBURST2_CPU_SCACHE)	+= sc.o
++obj-$(CONFIG_SMP)	+= smp.o
+diff --git a/arch/mips/xburst2/core/include/ccu.h b/arch/mips/xburst2/core/include/ccu.h
+new file mode 100644
+index 000000000..af3b9c628
+--- /dev/null
++++ b/arch/mips/xburst2/core/include/ccu.h
+@@ -0,0 +1,42 @@
++
++#ifndef __CCU_H__
++#define __CCU_H__
++
++#include <core_base.h>
++#define CCU_RESET_ENTRY		0xbfc00000
++
++#define get_ccu_cscr()			inl(CCU_IO_BASE + 0)
++#define set_ccu_cscr(val)		outl(val, CCU_IO_BASE + 0)
++
++#define get_ccu_cssr()			inl(CCU_IO_BASE + 0x20)
++
++#define get_ccu_csrr()			inl(CCU_IO_BASE + 0x40)
++#define set_ccu_csrr(val)		outl(val, CCU_IO_BASE + 0x40)
++
++#define get_ccu_pipr()			inl(CCU_IO_BASE + 0x100)
++
++#define get_ccu_pimr()			inl(CCU_IO_BASE + 0x120)
++#define set_ccu_pimr(val)		outl(val, CCU_IO_BASE + 0x120)
++
++#define get_ccu_mipr()			inl(CCU_IO_BASE + 0x140)
++
++#define get_ccu_mimr()			inl(CCU_IO_BASE + 0x160)
++#define set_ccu_mimr(val)		outl(val, CCU_IO_BASE + 0x160)
++
++#define get_ccu_oipr()			inl(CCU_IO_BASE + 0x180)
++
++#define get_ccu_oimr()			inl(CCU_IO_BASE + 0x1a0)
++#define set_ccu_oimr(val)		outl(val, CCU_IO_BASE + 0x1a0)
++
++#define get_ccu_rer()			inl(CCU_IO_BASE + 0xf00)
++#define set_ccu_rer(val)		outl(val, CCU_IO_BASE + 0xf00)
++
++#define get_ccu_cslr()			inl(CCU_IO_BASE + 0xff8)
++#define set_ccu_cslr(val)		outl(val, CCU_IO_BASE + 0xff8)
++
++#define get_ccu_csar()			inl(CCU_IO_BASE + 0xffc)
++#define set_ccu_csar(val)		outl(val, CCU_IO_BASE + 0xffc)
++
++//#define get_ccu_mbr(cpu_id)			inl(CCU_IO_BASE + 0x1000 + cpu_id*4)
++//#define set_ccu_mbr(cpu_id, val)	outl(val, CCU_IO_BASE + 0x1000 + cpu_id*4)
++#endif
+diff --git a/arch/mips/xburst2/core/include/core_base.h b/arch/mips/xburst2/core/include/core_base.h
+new file mode 100644
+index 000000000..14d0071bd
+--- /dev/null
++++ b/arch/mips/xburst2/core/include/core_base.h
+@@ -0,0 +1,6 @@
++#ifndef __CORE_BASE_H__
++#define __CORE_BASE_H__
++
++#define CCU_IO_BASE			0x12200000
++
++#endif /* __CORE_BASE_H__ */
+diff --git a/arch/mips/xburst2/core/include/ingenic_proc.h b/arch/mips/xburst2/core/include/ingenic_proc.h
+new file mode 100644
+index 000000000..a1883087e
+--- /dev/null
++++ b/arch/mips/xburst2/core/include/ingenic_proc.h
+@@ -0,0 +1,18 @@
++#ifndef _INGENIC_PROC_H_
++#define _INGENIC_PROC_H_
++
++struct jz_single_file_ops {
++	ssize_t (*read) (struct seq_file *, void *);
++	ssize_t (*write) (struct file *, const char __user *, size_t, loff_t *);
++	void *data;
++};
++
++struct proc_dir_entry * jz_proc_mkdir(char *s);
++struct proc_dir_entry *jz_proc_create_data(
++	const char *name, umode_t mode, struct proc_dir_entry *parent,
++	struct jz_single_file_ops *proc_fops, void *data);
++struct proc_dir_entry *jz_proc_create(
++	const char *name, umode_t mode, struct proc_dir_entry *parent,
++	struct jz_single_file_ops *proc_fops);
++struct proc_dir_entry * get_jz_proc_root(void);
++#endif /* _INGENIC_PROC_H_ */
+diff --git a/arch/mips/xburst2/core/include/irq_cpu.h b/arch/mips/xburst2/core/include/irq_cpu.h
+new file mode 100644
+index 000000000..0584b7b84
+--- /dev/null
++++ b/arch/mips/xburst2/core/include/irq_cpu.h
+@@ -0,0 +1,6 @@
++#ifndef IRQ_CPU_H
++#define IRQ_CPU_H
++
++void ingenic_irq_migration(int lock);
++void ingenic_irq_cpumask_idle(int idle);
++#endif /* IRQ_CPU_H */
+diff --git a/arch/mips/xburst2/core/include/mxu.h b/arch/mips/xburst2/core/include/mxu.h
+new file mode 100755
+index 000000000..fae67540a
+--- /dev/null
++++ b/arch/mips/xburst2/core/include/mxu.h
+@@ -0,0 +1,59 @@
++/*
++ * Copyright (C) 2005 Mips Technologies
++ * Author: Chris Dearman, chris@mips.com derived from fpu.h
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#ifndef _ASM_MXU_H
++#define _ASM_MXU_H
++
++#include <asm/cpu.h>
++#include <asm/cpu-features.h>
++#include <asm/hazards.h>
++#include <asm/mipsregs.h>
++
++#define NUM_MXU_REGS	(0)
++
++/* There is no mxu implement in XBURST2, leave empty */
++static inline void __init_mxu(void)
++{
++}
++static inline void __save_mxu(void * tsk_void)
++{
++}
++static inline void __restore_mxu(void * tsk_void)
++{
++}
++
++static inline void init_mxu(void)
++{
++	if(cpu_has_mxu)
++		__init_mxu();
++}
++
++
++#define save_mxu(tsk)							\
++	do {										\
++		if (cpu_has_mxu)						\
++			__save_mxu(tsk);					\
++	} while (0)
++
++#define restore_mxu(tsk)						\
++	do {										\
++		if (cpu_has_mxu)						\
++			__restore_mxu(tsk);					\
++	} while (0)
++
++#define __get_mxu_regs(tsk)						\
++	({											\
++		NULL;	\
++	})
++
++#define __let_mxu_regs(tsk,regs)				\
++	do{											\
++	}while(0)
++
++#endif /* _ASM_MXU_H */
+diff --git a/arch/mips/xburst2/core/include/mxuv3.h b/arch/mips/xburst2/core/include/mxuv3.h
+new file mode 100644
+index 000000000..10c631b0e
+--- /dev/null
++++ b/arch/mips/xburst2/core/include/mxuv3.h
+@@ -0,0 +1,47 @@
++/*
++ * Copyright (C) 2005 Mips Technologies
++ * Author: Chris Dearman, chris@mips.com derived from fpu.h
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#ifndef _ASM_MXU_V3_H
++#define _ASM_MXU_V3_H
++
++#include <asm/cpu.h>
++#include <asm/cpu-features.h>
++#include <asm/hazards.h>
++#include <asm/mipsregs.h>
++#include <linux/printk.h>
++
++void __init_mxuv3(void);
++void __save_mxuv3(void *tsk_void);
++void __restore_mxuv3(void *tsk_void);
++
++static inline void init_mxuv3(void)
++{
++	if(cpu_has_mxuv3)
++		__init_mxuv3();
++}
++
++
++#define save_mxuv3(tsk)							\
++	do {										\
++		if (cpu_has_mxuv3)						\
++			__save_mxuv3(tsk);					\
++	} while (0)
++
++static inline unsigned int is_mxuv3_enabled(void)
++{
++	return ((cpu_has_mxuv3) && (read_c0_status() & ST0_CU2));
++}
++
++#define restore_mxuv3(tsk)						\
++	do {										\
++		if (cpu_has_mxuv3)						\
++			__restore_mxuv3(tsk);					\
++	} while (0)
++
++#endif /* _ASM_MXU_V3_H */
+diff --git a/arch/mips/xburst2/core/prom.c b/arch/mips/xburst2/core/prom.c
+new file mode 100644
+index 000000000..8dcb80d5c
+--- /dev/null
++++ b/arch/mips/xburst2/core/prom.c
+@@ -0,0 +1,79 @@
++/*
++ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ *  JZ4740 SoC prom code
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under  the terms of the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the License, or (at your
++ *  option) any later version.
++ *
++ *  You should have received a copy of the GNU General Public License along
++ *  with this program; if not, write to the Free Software Foundation, Inc.,
++ *  675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/string.h>
++#include <asm/bootinfo.h>
++#include <linux/of_fdt.h>
++
++#include <soc/base.h>
++
++static __init void prom_init_cmdline(int argc, char *argv[])
++{
++	unsigned int count = COMMAND_LINE_SIZE - 1;
++	int i;
++	char *dst = &(arcs_cmdline[0]);
++	char *src;
++
++	for (i = 1; i < argc && count; ++i) {
++		src = argv[i];
++		while (*src && count) {
++			*dst++ = *src++;
++			--count;
++		}
++		*dst++ = ' ';
++	}
++	if (i > 1)
++		--dst;
++
++	*dst = 0;
++}
++extern struct plat_smp_ops xburst2_smp_ops;
++static void *_fw_fdt_addr;
++
++void __init prom_init(void)
++{
++	prom_init_cmdline((int)fw_arg0, (char **)fw_arg1);
++
++	if (fw_arg0 == 0 && fw_arg1 == 0xffffffffUL)
++		_fw_fdt_addr = phys_to_virt(fw_arg2);
++	else if ((int)fw_arg0 == -2)	/*UHI*/
++		_fw_fdt_addr = (void *)fw_arg1;
++	else if ((void*)__dtb_start != (void*)__dtb_end)
++		_fw_fdt_addr = __dtb_start;
++	else
++		panic("no dtb found!\n");
++
++	mips_machtype = MACH_INGENIC_X2000;
++#ifdef CONFIG_SMP
++	register_smp_ops(&xburst2_smp_ops);
++#endif
++}
++
++void __init prom_free_prom_memory(void)
++{
++}
++
++const char *get_system_type(void)
++{
++//	return CONFIG_BOARD_NAME;
++	return "xburst2-based";
++}
++void __init *get_fdt_addr(void)
++{
++	return _fw_fdt_addr;
++}
+diff --git a/arch/mips/xburst2/core/sc.c b/arch/mips/xburst2/core/sc.c
+new file mode 100644
+index 000000000..229a9c539
+--- /dev/null
++++ b/arch/mips/xburst2/core/sc.c
+@@ -0,0 +1,199 @@
++/*
++ * Copyright (C) 2006 Chris Dearman (chris@mips.com),
++ */
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/mm.h>
++
++#include <asm/mipsregs.h>
++#include <asm/bcache.h>
++#include <asm/cacheops.h>
++#include <asm/page.h>
++#include <asm/pgtable.h>
++#include <asm/mmu_context.h>
++#include <asm/r4kcache.h>
++
++/*
++ * MIPS32/MIPS64 L2 cache handling
++ */
++static unsigned long scache_size __read_mostly;
++/*
++ * Writeback and invalidate the secondary cache before DMA.
++ */
++static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
++{
++	__sync();
++	if (size >= scache_size) {
++		unsigned long lsize = cpu_scache_line_size();
++		if (lsize == 64)
++			blast_scache64();
++		else if (lsize == 32)
++			blast_scache32();
++		else
++			printk("Error: Second CacheLine size.\n");
++	} else {
++		blast_scache_range(addr, addr + size);
++	}
++#ifdef MIPS_BRIDGE_SYNC_WAR
++	if (MIPS_BRIDGE_SYNC_WAR)
++		__fast_iob();
++#endif
++}
++
++/*
++ * Invalidate the secondary cache before DMA.
++ */
++static void mips_sc_inv(unsigned long addr, unsigned long size)
++{
++	unsigned long lsize = cpu_scache_line_size();
++	unsigned long almask = ~(lsize - 1);
++
++	if (size >= scache_size) {
++		if (lsize == 64)
++			blast_scache64();
++		else if (lsize == 32)
++			blast_scache32();
++		else
++			printk("Error: Second CacheLine size.\n");
++	}else {
++		cache_op(Hit_Writeback_Inv_SD, addr & almask);
++		cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
++		blast_inv_scache_range(addr, addr + size);
++	}
++#ifdef MIPS_BRIDGE_SYNC_WAR
++	if (MIPS_BRIDGE_SYNC_WAR)
++		__fast_iob();
++#endif
++}
++
++static void mips_sc_enable(void)
++{
++	/* L2 cache is permanently enabled */
++}
++
++static void mips_sc_disable(void)
++{
++	/* L2 cache is permanently enabled */
++}
++
++static struct bcache_ops mips_sc_ops = {
++	.bc_enable = mips_sc_enable,
++	.bc_disable = mips_sc_disable,
++	.bc_wback_inv = mips_sc_wback_inv,
++	.bc_inv = mips_sc_inv
++};
++
++/*
++ * Check if the L2 cache controller is activated on a particular platform.
++ * MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
++ * cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
++ * cache being disabled.  However there is no guarantee for this to be
++ * true on all platforms.  In an act of stupidity the spec defined bits
++ * 12..15 as implementation defined so below function will eventually have
++ * to be replaced by a platform specific probe.
++ */
++//static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
++//{
++//	unsigned int config2 = read_c0_config2();
++//	unsigned int tmp;
++//
++//	/* Check the bypass bit (L2B) */
++//	/*switch (c->cputype) {
++//	case CPU_34K:
++//	case CPU_74K:
++//	case CPU_1004K:
++//	case CPU_BMIPS5000:
++//		if (config2 & (1 << 12))
++//			return 0;
++//	}*/
++//
++//	tmp = (config2 >> 4) & 0x0f;
++//	if (0 < tmp && tmp <= 7)
++//		c->scache.linesz = 2 << tmp;
++//	else
++//		return 0;
++//	return 1;
++//}
++
++static inline int __init mips_sc_probe(void)
++{
++	struct cpuinfo_mips *c = &current_cpu_data;
++	unsigned int config1, config2;
++	unsigned int tmp;
++
++	/* Mark as not present until probe completed */
++	c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
++
++	/* Ignore anything but MIPSxx processors */
++	if((c->isa_level & (MIPS_CPU_ISA_M32R1
++			| MIPS_CPU_ISA_M32R1
++			| MIPS_CPU_ISA_M64R1
++			| MIPS_CPU_ISA_M64R2))  == 0) {
++		return 0;
++	}
++
++	switch (c->processor_id & PRID_CPU_FEATURE_MASK) {
++	case PRID_CPU_X2000:
++		break;
++	default:
++		printk("pls check processor_id[0x%08x],sc_jz not support!\n",c->processor_id);
++	}
++
++	/* Does this MIPS32/MIPS64 CPU have a config2 register? */
++	config1 = read_c0_config1();
++	if (!(config1 & MIPS_CONF_M))
++		return 0;
++
++	config2 = read_c0_config2();
++
++	//if (!mips_sc_is_activated(c))
++	tmp = (config2 >> 4) & 0x0f;
++	if (0 < tmp && tmp <= 7)
++		c->scache.linesz = 2 << tmp;
++	else
++		return 0;
++
++	tmp = (config2 >> 8) & 0x0f;
++	if (0 <= tmp && tmp <= 7)
++		c->scache.sets = 64 << tmp;
++	else
++		return 0;
++
++	tmp = (config2 >> 0) & 0x0f;
++	if ((tmp == 7) || (tmp == 15))
++		c->scache.ways = tmp + 1;
++	else
++		return 0;
++
++	c->scache.waysize = c->scache.sets * c->scache.linesz;
++	c->scache.waybit = __ffs(c->scache.waysize);
++
++	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
++	scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
++	//write_c0_ecc(0x0);//verify xburst2 whether CP0-$26-0 is implemented.
++	return 1;
++}
++
++static char *way_string[] = { NULL, "direct mapped", "2-way",
++	"3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
++	"9-way", "10-way", "11-way", "12-way",
++	"13-way", "14-way", "15-way", "16-way",
++};
++
++int ingenic_sc_init(void)
++{
++	struct cpuinfo_mips *c = &current_cpu_data;
++	int found = mips_sc_probe();
++	printk("=======found ...... ingenic sc cache ops ...!, found: %d\n\n", found);
++	if (found) {
++		mips_sc_enable();
++		bcops = &mips_sc_ops;
++	}
++
++	printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
++	       scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
++
++	c->options |= MIPS_CPU_INCLUSIVE_CACHES;
++	return found;
++}
+diff --git a/arch/mips/xburst2/core/smp.c b/arch/mips/xburst2/core/smp.c
+new file mode 100644
+index 000000000..17e91f513
+--- /dev/null
++++ b/arch/mips/xburst2/core/smp.c
+@@ -0,0 +1,505 @@
++/*
++ * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
++ */
++
++//#define DEBUG
++//#define SMP_DEBUG
++
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/cpu.h>
++#include <linux/cpumask.h>
++#include <linux/smp.h>
++#include <linux/kernel_stat.h>
++
++#include <asm/mmu_context.h>
++#include <asm/io.h>
++#include <asm/uasm.h>
++#include <asm/r4kcache.h>
++#include <asm/processor.h>
++
++#include <linux/regulator/consumer.h>
++#include <linux/err.h>
++#include <linux/sched/hotplug.h>
++#include <linux/sched/task_stack.h>
++
++
++#include <dt-bindings/interrupt-controller/mips-irq.h>
++
++#include <core_base.h>
++#include <ccu.h>
++
++#ifdef SMP_DEBUG
++static void xburst2_ccu_showregs(void)
++{
++	int cpu = smp_processor_id();
++	unsigned int val;
++	printk("CPU%d:\n",cpu);
++#define P(reg) do {								\
++		val = get_ccu_##reg();					\
++		printk(#reg ":\t%08x\n", val);			\
++	} while(0)
++
++	P(cscr); P(cssr); P(csrr); P(pipr); P(pimr);
++	P(mipr); P(mimr); P(oipr); P(oimr); P(rer);
++	P(cslr); P(csar);
++	//P(val);  P(lock);
++	printk("cp0 status:\t%08x\n", read_c0_status());
++	printk("cp0 cause:\t%08x\n", read_c0_cause());
++}
++static void dump_code(const unsigned int *handler, const int count)
++{
++	int i;
++	pr_info("\t.set push\n");
++	pr_info("\t.set noreorder\n");
++
++	for (i = 0; i < count; i++)
++		pr_info("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
++
++	pr_info("\t.set\tpop\n");
++}
++#else
++static inline void xburst2_ccu_showregs(void) {}
++static inline void dump_code(const unsigned int *handler, const int count) {}
++#endif
++struct xburst2_mailbox{
++	raw_spinlock_t lock;
++	void *__iomem *iobase;
++};
++struct xburst2_smp {
++	unsigned long context_sp, context_gp;
++	unsigned long entry_base;
++	struct xburst2_mailbox mailbox[NR_CPUS];
++	struct xburst2_mailbox * __percpu* percpu_mailbox;
++};
++static struct xburst2_smp smp_core;
++void ingenic_percpu_timerevent_init(unsigned int cpu_num);
++void ingenic_percpu_irq_init(unsigned int cpu_num);
++
++static irqreturn_t xburst2_mbox_interrupt(int irq, void *data)
++{
++	unsigned int action = 0;
++	struct xburst2_mailbox *mailbox = *(struct xburst2_mailbox **)data;
++	raw_spin_lock(&mailbox->lock);
++	action = readl(mailbox->iobase);
++	writel(0,mailbox->iobase);
++	raw_spin_unlock(&mailbox->lock);
++	if (!action) {
++		pr_err("SMP[%d]:invalid mailboxes action is NULL\n",smp_processor_id());
++		goto ipi_finish;
++	}
++	if (action & SMP_CALL_FUNCTION) {
++		generic_smp_call_function_interrupt();
++	}
++
++	if (action & SMP_RESCHEDULE_YOURSELF) {
++		scheduler_ipi();
++	}
++ipi_finish:
++	return IRQ_HANDLED;
++}
++
++void percpu_mailbox_init(int cpu)
++{
++	smp_core.mailbox[cpu].iobase = ioremap(CCU_IO_BASE + cpu * 4 + 0x1000,4);
++	raw_spin_lock_init(&smp_core.mailbox[cpu].lock);
++	*this_cpu_ptr(smp_core.percpu_mailbox) = &smp_core.mailbox[cpu];
++	writel(0, smp_core.mailbox[cpu].iobase);
++	enable_percpu_irq(CORE_MAILBOX_IRQ, IRQ_TYPE_NONE);
++}
++/*
++ * Code to run on secondary just after probing the CPU
++ */
++static void xburst2_init_secondary(void)
++{
++	int cpu = smp_processor_id();
++	unsigned int mb_msk = get_ccu_mimr();
++	unsigned int pmsk = get_ccu_pimr();
++	unsigned int cpu_num = read_c0_ebase() & 0x1ff;
++//	unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2;
++//	int ret;
++	if(cpu == 0){
++		pr_info("BUG: cpu0 is booted.\n");
++		dump_stack();
++		while(1);
++	}
++	pr_info("#### now starting init for cpu : %d\n", cpu);
++	clear_c0_cause(CAUSEF_IP);
++	clear_c0_status(ST0_IM);
++	mb_msk |= 1 << cpu;
++	set_ccu_mimr(mb_msk);
++	percpu_mailbox_init(cpu);
++	pr_debug("percpu %x\n",read_c0_status());
++	ingenic_percpu_irq_init(cpu_num);
++	pmsk |= (1 << cpu);
++	set_ccu_pimr(pmsk);
++
++	/* jzcpu_timer_setup(); */
++
++	xburst2_ccu_showregs();
++	ingenic_percpu_timerevent_init(cpu_num);
++	set_ccu_oimr((1<<cpu) | get_ccu_oimr());
++}
++static bool migrate_one_irq(int cpu,struct irq_desc *desc)
++{
++	struct irq_data *d = irq_desc_get_irq_data(desc);
++	const struct cpumask *affinity = d->common->affinity;
++	struct irq_chip *c;
++	bool ret = false;
++
++	if (irqd_is_per_cpu(d) || !cpumask_test_cpu(cpu, affinity))
++		return false;
++
++	c = irq_data_get_irq_chip(d);
++	if(!c->irq_set_affinity)
++		return false;
++	if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
++		affinity = cpu_online_mask;
++		ret = true;
++	}
++
++	if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret)
++		cpumask_copy(d->common->affinity, affinity);
++
++	return ret;
++}
++
++static void migrate_irqs(int cpu)
++{
++	unsigned int i;
++	struct irq_desc *desc;
++	for_each_irq_desc(i, desc) {
++		raw_spin_lock(&desc->lock);
++		migrate_one_irq(cpu,desc);
++		raw_spin_unlock(&desc->lock);
++	}
++}
++
++/*
++ * Do any tidying up before marking online and running the idle
++ * loop
++ */
++static void xburst2_smp_finish(void)
++{
++	int cpu = smp_processor_id();
++	migrate_irqs(cpu);
++	xburst2_ccu_showregs();
++	local_irq_enable();
++	pr_info("[SMP] slave cpu%d start up finished.\n",smp_processor_id());
++}
++static void build_bounce_code(struct xburst2_smp *smp)
++{
++	unsigned long *spp,*gpp;
++	unsigned int entry = (unsigned int)smp_bootstrap;
++	unsigned int *p;
++	p = (unsigned int*)__get_free_pages(GFP_KERNEL, 0);
++	spp = (unsigned long *)&smp->context_sp;
++	gpp = (unsigned long *)&smp->context_gp;
++	smp->entry_base = (unsigned int)p;
++
++#define STATUS_BITS  (ST0_CU0)
++#define CAUSE_BITS   (1 << 27)
++#define C0_CAUSE     13,0
++#define C0_STATUS    12,0
++#define C0_COUNT    9,0
++
++
++#define C0_CONFIG_0  16,0
++#define V0		2
++#define V1		3
++#define GP      28
++#define SP      29
++#define RA      31
++	/* the instructions'max size is 128 byte */
++
++	/* Disable IFU Small Buffer, system low power opt. */
++	UASM_i_MFC0(&p, V0, 16, 7);
++	uasm_i_ori(&p, V0, V0, 7 << 3);
++	UASM_i_MTC0(&p, V0, 16, 7);
++
++	/* kseg0 cache attribute */
++	UASM_i_MFC0(&p,V0,C0_CONFIG_0);
++	UASM_i_LA(&p,V1,~7);
++	uasm_i_and(&p,V0,V0,V1);
++	uasm_i_ori(&p,V0,V0,3);
++	UASM_i_MTC0(&p,V0,C0_CONFIG_0);
++
++	/* cause to DC disable. and status regitster reset */
++	UASM_i_LA(&p,V0,CAUSE_BITS);
++	UASM_i_MTC0(&p,V0,C0_CAUSE);
++
++	UASM_i_MTC0(&p,0,C0_COUNT);
++
++	UASM_i_LA(&p,V0,STATUS_BITS);
++	UASM_i_MTC0(&p,V0,C0_STATUS);
++
++	UASM_i_LA(&p, SP, (unsigned long)spp);
++	UASM_i_LW(&p, SP, 0,SP);
++	UASM_i_LA(&p, GP, (unsigned long)gpp);
++	UASM_i_LW(&p, GP, 0,GP);
++	UASM_i_LA(&p, RA, entry);
++	uasm_i_jr(&p, RA);
++	uasm_i_nop(&p);
++	dump_code((const unsigned int*)smp->entry_base,24);
++	//the code in ddr should be sure.
++	dma_cache_wback_inv(smp->entry_base,128);
++}
++
++/*
++ * Setup the PC, SP, and GP of a secondary processor and start it
++ * running!
++ */
++static int xburst2_boot_secondary(int cpu, struct task_struct *idle)
++{
++	unsigned int reset;//,mb_msk;
++//TODO: clk enable.
++	/* set soft reset. */
++	pr_info("[SMP] Booting CPU%d ...\n", cpu);
++	/* set reset entry! */
++	set_ccu_rer(smp_core.entry_base);
++
++	reset = get_ccu_csrr();
++	reset |= 1 << cpu;
++	set_ccu_csrr(reset);
++	smp_core.context_sp = __KSTK_TOS(idle);
++	smp_core.context_gp = (unsigned long)task_thread_info(idle);
++	wmb();
++/* clear soft reset. */
++	reset &= ~(1 << cpu);
++	set_ccu_csrr(reset);
++	pr_debug("percpu %x\n",read_c0_status());
++
++	return 0;
++}
++
++// prepare smp all core register but core0 should be hold.
++// the code is initialise core ccu register.
++
++static void __init xburst2_smp_setup(void)
++{
++	int i, num;
++	//set smp all core register disable.
++	set_ccu_mimr(0);
++	//note:core reset register and core0 shouldn't be set.
++	set_ccu_csrr(0xfffe);
++
++
++	cpumask_clear_cpu(NR_CPUS, (struct cpumask *)cpu_possible_mask);
++	cpumask_clear_cpu(NR_CPUS, (struct cpumask *)cpu_present_mask);
++
++	//initial core0 register.
++
++	cpumask_set_cpu(0, (struct cpumask *)cpu_possible_mask);
++	cpumask_set_cpu(0, (struct cpumask *)cpu_present_mask);
++
++	__cpu_number_map[0] = 0;
++	__cpu_logical_map[0] = 0;
++
++	for (i = 1, num = 0; i < NR_CPUS; i++) {
++		cpumask_set_cpu(i, (struct cpumask *)cpu_possible_mask);
++		cpumask_set_cpu(i, (struct cpumask *)cpu_present_mask);
++
++		__cpu_number_map[i] = ++num;
++		__cpu_logical_map[num] = i;
++	}
++
++	pr_info("[SMP] Slave CPU(s) %i available.\n", num);
++}
++
++//prepare initial code for every core.
++static void __init xburst2_prepare_cpus(unsigned int max_cpus)
++{
++	int ret;
++	pr_info("[SMP] Prepare %d cores., cpu: %d\n", max_cpus, smp_processor_id());//qiao
++
++	if (max_cpus <= 1)
++		return;
++
++	smp_core.percpu_mailbox = alloc_percpu(struct xburst2_mailbox*);
++	if(!smp_core.percpu_mailbox)
++		pr_err("ERROR:alloc mailbox percpu fail!\n");
++
++	ret = request_percpu_irq(CORE_MAILBOX_IRQ,xburst2_mbox_interrupt,"jz-mailbox",
++							 smp_core.percpu_mailbox);
++	if(ret) {
++		pr_err("ERROR: cpu%d request ost error\n",smp_processor_id());
++	}
++	percpu_mailbox_init(0);
++	set_ccu_mimr(1 << 0);
++	/* prepare slave cpus entry code */
++	build_bounce_code(&smp_core);
++	/* set reset entry point */
++	set_ccu_rer(smp_core.entry_base);//qiao
++	pr_debug("smp_bounce.base: %08lx\n", smp_core.entry_base);
++}
++
++static void xburst2_send_ipi_single(int cpu, unsigned int action)
++{
++	//unsigned int timeout=0x1000000;
++
++	struct xburst2_mailbox *mailbox = per_cpu(*smp_core.percpu_mailbox,cpu);
++	unsigned int val;
++	unsigned long flags;
++#if 0
++	while((readl(mailbox->iobase) & action) && (--timeout));
++	if(timeout == 0){
++		pr_err("SMP[%d] action:%d will reenter\n",cpu,action);
++	}
++#endif
++
++	raw_spin_lock_irqsave(&mailbox->lock,flags);
++	val = readl(mailbox->iobase);
++	writel(action | val,mailbox->iobase);
++	raw_spin_unlock_irqrestore(&mailbox->lock,flags);
++}
++
++static void xburst2_send_ipi_mask(const struct cpumask *mask, unsigned int action)
++{
++	int i;
++	for(i = 0; i < NR_CPUS;i++){
++		if(cpumask_test_cpu(i,(struct cpumask *)mask)){
++			xburst2_send_ipi_single(i,action);
++		}
++	}
++}
++/**
++ * all cpu finish
++ */
++void xburst2_cpus_done(void)
++{
++// FIXME: will remove this code.
++	pr_debug("[SMP]: xburst2_cpus_done\n");
++}
++
++#ifdef CONFIG_HOTPLUG_CPU
++
++void ingenic_percpu_timerevent_deinit(void);
++void ingenic_percpu_irq_deinit(void);
++static int xburst2_cpu_disable(void)
++{
++	unsigned int cpu = smp_processor_id();
++	unsigned int val;
++	if (cpu == 0)
++		return -EBUSY;
++	pr_info("SMP: CPU%d is offline\n", cpu);
++	set_cpu_online(cpu, false);
++//	cpumask_clear_cpu(cpu, &cpu_callin_map);
++	calculate_cpu_foreign_map();
++
++	val = get_ccu_pimr();
++	val &= ~(1 << cpu);
++	set_ccu_pimr(val);
++
++	val = get_ccu_oimr();
++	val &= ~(1 << cpu);
++	set_ccu_oimr(val);
++
++	//val = get_ccu_mimr();
++	//val &= ~(1 << cpu);
++	//set_ccu_mimr(val);
++
++	ingenic_percpu_irq_deinit();
++	ingenic_percpu_timerevent_deinit();
++	migrate_irqs(cpu);
++	clear_tasks_mm_cpumask(cpu);
++
++	pr_debug("disabled cpu %d\n",cpu);
++	return 0;
++}
++
++void xburst2_cpu_die(unsigned int cpu)
++{
++	unsigned int timeout = 0x100000;
++	unsigned int reset;
++	if (cpu == 0)
++		return;
++
++	while((get_ccu_cssr() & (1<<cpu)) == 0 && --timeout);
++	if(timeout == 0){
++		pr_err("SMP[%d] disabled failed!\n",cpu);
++		BUG_ON(1);
++	}
++
++	reset = get_ccu_csrr();
++	reset |= 1 << cpu;
++	set_ccu_csrr(reset); // keep reset state.
++
++	//TODO: clk disable.
++	pr_info("SMP[%d] is disabled\n",cpu);
++}
++#endif
++//cpu idle loop will enter it.
++void play_dead(void)
++{
++	unsigned int cpu = smp_processor_id();
++
++	unsigned int val;
++	pr_debug("---%s, cpu: %d\n", __func__, cpu);
++
++	val = get_ccu_mimr();
++	val &= ~(1 << cpu);
++	set_ccu_mimr(val);
++	idle_task_exit();
++	local_irq_disable();
++	local_flush_tlb_all();
++	// Isn't smt thread core.
++	if(!cpu_online(((cpu + 1) & 1) | (cpu & (~1))))
++	{
++		blast_dcache32();
++	}
++
++	__asm__ __volatile__ (  ".set	push            \n\t"
++							".set	mips32r2        \n\t"
++							"sync                   \n\t"
++							"wait                   \n\t"
++							"nop                    \n\t"
++							".set pop               \n\t"
++		);
++	pr_err("ERROR:SMP[%d]: shouldn't run here.",cpu);
++	while(1){
++		__asm__ __volatile__ (  ".set	push        \n\t"
++								".set	mips32r2    \n\t"
++								"wait               \n\t"
++								"nop                \n\t"
++								".set pop           \n\t"
++			);
++	}
++}
++
++struct plat_smp_ops xburst2_smp_ops = {
++	.send_ipi_single    = xburst2_send_ipi_single,
++	.send_ipi_mask      = xburst2_send_ipi_mask,
++
++	.init_secondary     = xburst2_init_secondary,
++	.smp_finish         = xburst2_smp_finish,
++	.boot_secondary     = xburst2_boot_secondary,
++
++//kernel init
++	.smp_setup          = xburst2_smp_setup,   //platfor init
++//	.cpus_done          = xburst2_cpus_done,
++	.prepare_cpus		= xburst2_prepare_cpus,  //main init
++
++
++#ifdef CONFIG_HOTPLUG_CPU
++	/* Ensure this CPU doesn't handle any more interrupts. */
++	.cpu_disable        = xburst2_cpu_disable,
++	/* This actually kills the CPU. */
++	.cpu_die            = xburst2_cpu_die,
++
++#endif
++};
+diff --git a/arch/mips/xburst2/soc-m300/Kconfig.DT b/arch/mips/xburst2/soc-m300/Kconfig.DT
+new file mode 100644
+index 000000000..42a36d553
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/Kconfig.DT
+@@ -0,0 +1,11 @@
++choice
++	prompt "device tree select for m300 boards"
++	depends on SOC_M300
++
++config DT_GEWU_V10
++	bool "m300 gewu v10"
++
++config DT_M300_ZEBRA
++	bool "m300 zebra"
++
++endchoice
+diff --git a/arch/mips/xburst2/soc-m300/Makefile b/arch/mips/xburst2/soc-m300/Makefile
+new file mode 100644
+index 000000000..357365c17
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/Makefile
+@@ -0,0 +1,12 @@
++obj-y += setup.o
++obj-y += serial.o
++
++
++obj-y += pm_fastboot.o
++obj-y += pm.o
++obj-y += regs_save_restore.o
++obj-y += pm_sleep.o
++
++
++obj-y += libdmmu.o
++obj-y += reset.o
+diff --git a/arch/mips/xburst2/soc-m300/include/cpu-feature-overrides.h b/arch/mips/xburst2/soc-m300/include/cpu-feature-overrides.h
+new file mode 100644
+index 000000000..46e526d6f
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/include/cpu-feature-overrides.h
+@@ -0,0 +1,66 @@
++/*
++ *  Copyright (C) 2008 Ingenic Semiconductor Inc.
++ *
++ *  Author: <zpzhong@ingenic.cn>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_INGENIC_CPU_FEATURE_OVERRIDES_H__
++#define __ASM_MACH_INGENIC_CPU_FEATURE_OVERRIDES_H__
++
++
++#define cpu_dcache_size()       	(32 * 1024)
++#define cpu_dcache_ways()       	8
++#define cpu_dcache_line_size()  	32
++#define cpu_icache_size()       	(32 * 1024)
++#define cpu_icache_ways()       	8
++#define cpu_icache_line_size()  	32
++#define cpu_has_xpa			0
++#define cpu_has_tlb                     1
++#define cpu_has_tlbinv                  1
++#define cpu_has_4kex                    1
++#define cpu_has_3k_cache                0
++#define cpu_has_4k_cache                1
++#define cpu_has_tx39_cache              0
++#define cpu_has_fpu                     1
++#define cpu_has_32fpr                   0
++#define cpu_has_counter                 0
++#define cpu_has_watch                   1
++#define cpu_has_divec                   1
++#define cpu_has_vce                     0
++#define cpu_has_cache_cdex_p            0
++#define cpu_has_cache_cdex_s            0
++#define cpu_has_prefetch                1
++#define cpu_has_mcheck                  1
++#define cpu_has_ejtag                   0
++#define cpu_has_llsc                    1
++#define kernel_uses_llsc		cpu_has_llsc
++#define cpu_has_mips16                  0
++#define cpu_has_mdmx                    0
++#define cpu_has_mips3d                  0
++#define cpu_has_smartmips               0
++#define cpu_has_vtag_icache             0
++#define cpu_has_dc_aliases              0
++#define cpu_has_ic_fills_f_dc           0
++#define cpu_has_pindexed_dcache         0
++#define cpu_icache_snoops_remote_store  0
++#define cpu_has_mips32r1                0
++#define cpu_has_mips32r2                1
++#define cpu_has_mips64r1                0
++#define cpu_has_mips64r2                0
++#define cpu_has_dsp                     0
++#define cpu_has_mipsmt                  0
++#define cpu_has_userlocal               1
++#define cpu_has_rixi                    1
++#define cpu_has_nofpuex                 0
++#define cpu_has_64bits                  0
++#define cpu_has_64bit_zero_reg          0
++#define cpu_has_vint                    0
++#define cpu_has_veic                    0
++#define cpu_has_inclusive_pcaches       0
++#define kernel_uses_smartmips_rixi      0
++#define cpu_has_mxu                     0
++#endif
+diff --git a/arch/mips/xburst2/soc-m300/include/irq.h b/arch/mips/xburst2/soc-m300/include/irq.h
+new file mode 100644
+index 000000000..0c1410546
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/include/irq.h
+@@ -0,0 +1,39 @@
++/*
++ *  Copyright (C) 2010 Ingenic Semiconductor Inc.
++ *
++ *  Author: <zpzhong@ingenic.cn>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_INGENIC_IRQ_H__
++#define __ASM_MACH_INGENIC_IRQ_H__
++#include <irq_cpu.h>
++#include <dt-bindings/interrupt-controller/mips-irq.h>
++
++enum {
++#define GPIO_NR_IRQS	(32 * 5 + 16)
++	IRQ_GPIO_BASE = (IRQ_INTC_END + 1),
++	IRQ_GPIO_END = IRQ_GPIO_BASE + GPIO_NR_IRQS - 1,
++
++#define TCU_NR_IRQS	(8)
++	IRQ_TCU_BASE,
++	IRQ_TCU_END = IRQ_TCU_BASE + TCU_NR_IRQS - 1,
++
++#define MCU_NR_IRQS    (5)
++	IRQ_MCU_BASE,
++	IRQ_MCU_END = IRQ_MCU_BASE + MCU_NR_IRQS - 1,
++
++#define RESERVED_NR_IRQS       (150)
++	IRQ_RESERVED_BASE,
++	IRQ_RESERVED_END = IRQ_RESERVED_BASE + RESERVED_NR_IRQS - 1,
++
++	NR_IRQS,
++
++
++
++};
++
++#endif
+diff --git a/arch/mips/xburst2/soc-m300/include/libdmmu.h b/arch/mips/xburst2/soc-m300/include/libdmmu.h
+new file mode 100644
+index 000000000..6e0fbdb42
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/include/libdmmu.h
+@@ -0,0 +1,30 @@
++#ifndef _LIBDMMU_
++#define _LIBDMMU_
++
++#include <linux/device.h>
++
++
++struct dmmu_mm_ops {
++	int (*mm_release)(void *data);
++};
++
++struct dmmu_mm_notifier {
++
++	struct device *dev;
++	void *data;
++	struct list_head list;
++
++	struct dmmu_mm_ops *ops;
++};
++
++int dmmu_register_mm_notifier(struct dmmu_mm_notifier *dmn);
++
++unsigned long dmmu_map(struct device *dev,unsigned long vaddr,unsigned long len);
++int dmmu_flush_cache(unsigned long vaddr, unsigned long len);
++int dmmu_unmap(struct device *dev,unsigned long vaddr, int len);
++int dmmu_unmap_all(struct device *dev);
++void dmmu_dump_vaddr(unsigned long vaddr);
++int dmmu_memory_smash(unsigned long vaddr, int smash_mode);
++int dmmu_dump_map(unsigned long vaddr);
++
++#endif
+diff --git a/arch/mips/xburst2/soc-m300/include/soc/base.h b/arch/mips/xburst2/soc-m300/include/soc/base.h
+new file mode 100644
+index 000000000..1b7d3d130
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/include/soc/base.h
+@@ -0,0 +1,77 @@
++
++#ifndef __JZSOC_SOC_DEV_H__
++#define __JZSOC_SOC_DEV_H__
++
++/*
++ * Define the module base addresses
++ */
++
++/* AHB0 BUS Devices Base */
++#define HARB0_IOBASE	0x13000000 /* 64KB, AHB Bus Aribtier */
++#define DDR_PHY_IOBASE	0x13011000 /* 4KB, DDR PHY */
++#define DDRC_H0_IOBASE	0x13012000 /* 4KB, DDR Controller Registers@ASHB0 */
++#define DPU_IOBASE	0x13050000 /* 64KB, LCD Controller */
++#define CIM_IOBASE	0x13060000 /* 64KB, Camera Interface Module */
++#define ROTATE_IOBASE	0x13070000 /* 64KB, Rotate DMA */
++#define JPEG_IOBASE	0x130d0000 /* 64KB, VPU-JPEG  */
++
++
++/* AHB2 Bus Devices Base */
++#define HARB2_IOBASE	0x13400000 /* 64KB, AHB Bus Arbiter */
++#define NEMC_IOBASE	0x13410000 /* 64KB, External Normal Memory/Boot ROM/OTP Controller */
++#define PDMA_IOBASE	0x13420000 /* 64KB, Programmable DMA Controller */
++#define AES_IOBASE	0x13430000 /* 64KB, AES */
++#define SFC_IOBASE	0x13440000 /* 64KB, SPI Flash Controller */
++#define MSC0_IOBASE	0x13450000 /* 64KB, MMC SD Controller0 */
++#define MSC1_IOBASE	0x13460000 /* 64KB, MMC SD Controller1 */
++#define HASH_IOBASE	0x13470000 /* 64KB, HASH */
++#define MAC_IOBASE	0x134b0000 /* 64KB, GMAC/MAC */
++#define PWM_IOBASE	0x134c0000 /* 64KB, PWM */
++#define DDRC_H2_IOBASE	0x134f0000 /* 4KB, DDR Controller Register @AHB2 */
++#define AUDIO_IOBASE	0x134e0000 /* 64KB, Aduio System */
++#define OTG_IOBASE	0x13500000 /* 256KB, OTG2.0 Controller */
++#define EFUSE_IOBASE	0x13540000 /* 64KB, EFUSE */
++//#define INTC_IOBASE	0x135f0000 /* Interrupt Controller */ /* TODO: to be fix */
++
++
++/* APB BUS Devices Base */
++#define CPM_IOBASE	0x10000000 /* 4KB, Clocks and Power Manager */
++#define TCU_IOBASE	0x10002000 /* 4KB, Timer/Count Unit,OperatingSystemTimer,Watchdog Timer */
++#define WDT_IOBASE	TCU_IOBASE /* 4KB, Timer/Count Unit,OperatingSystemTimer,Watchdog Timer */
++
++#define RTC_IOBASE	0x10003000 /* 4KB, Real-Time Clock */
++#define GPIO_IOBASE	0x10010000 /* 4KB, General-Purpose I/O */
++#define	UART0_IOBASE	0x10030000 /* 4KB, UART0 Controller */
++#define	UART1_IOBASE	0x10031000 /* 4KB, UART1 Controller */
++#define	UART2_IOBASE	0x10032000 /* 4KB, UART2 Controller */
++#define	UART3_IOBASE	0x10033000 /* 4KB, UART3 Controller */
++#define	UART4_IOBASE	0x10034000 /* 4KB, UART4 Controller */
++#define	UART5_IOBASE	0x10035000 /* 4KB, UART4 Controller */
++#define SCC_IOBASE	0x10040000 /* 4KB, Smart Card Controller */
++#define SSI0_IOBASE	0x10043000 /* 4KB, Synchronous Serial Interface */
++#define SSI1_IOBASE	0x10044000 /* 4KB, Synchronous Serial Interface */
++#define I2C0_IOBASE	0x10050000 /* 4KB, I2C 0 Bus Interface */
++#define I2C1_IOBASE	0x10051000 /* 4KB, I2C 1 Bus Interface */
++#define I2C2_IOBASE	0x10052000 /* 4KB, I2C 2 Bus Interface */
++#define I2C3_IOBASE	0x10053000 /* 4KB, I2C 3 Bus Interface */
++#define I2C4_IOBASE	0x10054000 /* 4KB, I2C 4 Bus Interface */
++#define I2C5_IOBASE	0x10055000 /* 4KB, I2C 5 Bus Interface */
++
++
++
++/* TODO: Others To Be add */
++/* NAND CHIP Base Address */
++#define NEMC_CS1_IOBASE 0X1b000000
++#define NEMC_CS2_IOBASE 0X1a000000
++#define NEMC_CS3_IOBASE 0X19000000
++#define NEMC_CS4_IOBASE 0X18000000
++#define NEMC_CS5_IOBASE 0X17000000
++#define NEMC_CS6_IOBASE 0X16000000
++
++
++#define	OST_IOBASE	0x12000000
++#define	TCU_IOBASE	0x10002000
++
++#define DDRC_BASE       0xb34f0000
++
++#endif
+diff --git a/arch/mips/xburst2/soc-m300/include/soc/cache.h b/arch/mips/xburst2/soc-m300/include/soc/cache.h
+new file mode 100644
+index 000000000..ea3b935a8
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/include/soc/cache.h
+@@ -0,0 +1,28 @@
++#ifndef __CHIP_CACHE_H__
++#define __CHIP_CACHE_H__
++#include <asm/cacheops.h>
++#include <asm/r4kcache.h>
++
++#define Index_Prefetch_I        0x1c
++
++
++#define cache_prefetch(label,size)					\
++do{									\
++	unsigned long addr,end;						\
++	/* Prefetch codes from label */					\
++	addr = (unsigned long)(&&label) & ~(32 - 1);			\
++	end = (unsigned long)(&&label + size) & ~(32 - 1);		\
++	end += 32;							\
++	for (; addr < end; addr += 32) {				\
++		__asm__ volatile (					\
++				".set push       \n\t"			\
++				".set mips32     \n\t"			\
++				" cache %0, 0(%1)\n\t"			\
++				".set pop        \n\t"			\
++				:					\
++				: "I" (Index_Prefetch_I), "r"(addr));	\
++	}								\
++}									\
++while(0)
++
++#endif /* __CHIP_CACHE_H__ */
+diff --git a/arch/mips/xburst2/soc-m300/include/soc/cpm.h b/arch/mips/xburst2/soc-m300/include/soc/cpm.h
+new file mode 100644
+index 000000000..d0fa6d8f0
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/include/soc/cpm.h
+@@ -0,0 +1,136 @@
++/*
++ * SOC CPM register definition.
++ *
++ * CPM (Clock reset and Power control Management)
++ *
++ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.
++ */
++
++#ifndef __SOC_CPM_H__
++#define __SOC_CPM_H__
++
++#include <soc/base.h>
++
++#define CPM_CPCCR		(0x00)
++#define CPM_CPCSR		(0xD4)
++
++#define CPM_DDRCDR		(0x2c)
++#define CPM_MACCDR		(0x54)
++#define CPM_MACTXCDR		(0x58)
++#define CPM_MACTXCDR1		(0xdc)
++#define CPM_MACPTP		(0x4c)
++#define CPM_I2S0CDR		(0x60)
++#define CPM_I2S1CDR		(0x7c)
++#define CPM_I2S2CDR		(0x84)
++#define CPM_I2S3CDR		(0x8c)
++#define CPM_I2S0CDR1		(0x70)
++#define CPM_I2S1CDR1		(0x80)
++#define CPM_I2S2CDR1		(0x88)
++#define CPM_I2S3CDR1		(0xa0)
++#define CPM_AUDIOCR		(0xac)
++#define CPM_LPCDR		(0x64)
++#define CPM_MSC0CDR		(0x68)
++#define CPM_MSC1CDR		(0xa4)
++#define CPM_MSC2CDR		(0xa8)
++#define CPM_SFCCDR		(0x74)
++#define CPM_SSICDR		(0x5c)
++#define CPM_CIMCDR		(0x78)
++#define CPM_PWMCDR		(0x6c)
++#define CPM_ISPCDR		(0x30)
++#define CPM_RSACDR		(0x50)
++
++#define CPM_INTR		(0xB0)
++#define CPM_INTRE		(0xB4)
++#define CPM_SFTINT		(0xBC)
++#define CPM_DRCG		(0xD0)
++#define CPM_CPPSR		(0x34)
++#define CPM_CPSPPR		(0x38)
++#define CPM_USBPCR		(0x3C)
++#define CPM_USBRDT		(0x40)
++#define CPM_USBVBFIL		(0x44)
++#define CPM_USBPCR1		(0x48)
++
++#define CPM_CPPCR		(0x0C)
++#define CPM_CPAPCR		(0x10)
++#define CPM_CPMPCR		(0x14)
++#define CPM_CPEPCR		(0x18)
++
++#define CPM_LCR			(0x04)
++#define CPM_PSWC0ST		(0x90)
++#define CPM_PSWC1ST		(0x94)
++#define CPM_PSWC2ST		(0x98)
++#define CPM_PSWC3ST		(0x9C)
++#define CPM_CLKGR		(0x20)
++#define CPM_CLKGR1		(0x28)
++#define CPM_MESTSEL		(0xEC)
++#define CPM_SRBC		(0xC4)
++#define CPM_EXCLK_DS		(0xE0)
++#define CPM_MPDCR		(0xF8)
++#define CPM_MPDCR1		(0xFC)
++#define CPM_SLBC		(0xC8)
++#define CPM_SLPC		(0xCC)
++#define CPM_OPCR		(0x24)
++
++#define CPM_RSR			(0x08)
++
++#ifndef BIT
++#define BIT(nr)  (1UL << nr)
++#endif
++
++/*USB Parameter Control Register*/
++#define USBPCR_USB_MODE                 BIT(31)
++#define USBPCR_AVLD_REG                 BIT(30)
++#define USBPCR_IDPULLUP_MASK_BIT        28
++#define USBPCR_IDPULLUP_MASK		(0x3 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_IDPULLUP_OTG             (0x0 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_IDPULLUP_ALWAYS_SUSPEND  (0x1 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_IDPULLUP_ALWAYS          (0x2 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_INCR_MASK                BIT(27)
++#define USBPCR_POR_BIT                  22
++#define USBPCR_POR                      BIT(USBPCR_POR_BIT)
++
++/*USB Reset Detect Timer Register*/
++#define USBRDT_RESUME_INTEEN		BIT(31)	/*RW*/
++#define USBRDT_RESUME_INTERCLR		BIT(30)	/*W0*/
++#define USBRDT_RESUME_SPEED_BIT		28	/*RW*/
++#define USBRDT_RESUME_SPEED_MSK		(0x3 << USBRDT_RESUME_SPEED_BIT)
++#define USBRDT_RESUME_SPEED_HIGH	(0x0 << USBRDT_RESUME_SPEED_BIT)
++#define USBRDT_RESUME_SPEED_FULL	(0x1 << USBRDT_RESUME_SPEED_BIT)
++#define USBRDT_RESUME_SPEED_LOW		(0x2 << USBRDT_RESUME_SPEED_BIT)
++#define USBRDT_RESUME_STATUS		27	/*RO*/
++#define USBRDT_HB_MASK                  BIT(26)
++#define USBRDT_VBFIL_LD_EN              BIT(25)
++#define USBRDT_IDDIG_EN                 24
++#define USBRDT_IDDIG_REG                23
++#define USBRDT_USBRDT_MSK               (0x7fffff)
++#define USBRDT_USBRDT(x)                ((x) & USBRDT_USBRDT_MSK)
++
++/*USB VBUS Jitter Filter Register*/
++#define USBVBFIL_USBVBFIL(x)		((x) & 0xffff)
++#define USBVBFIL_IDDIGFIL(x)		((x) & (0xffff << 16))
++
++/*USB Parameter Control Register1*/
++#define USBPCR1_BVLD_REG        BIT(31)
++#define USBPCR1_DPPULLDOWN	BIT(29)
++#define USBPCR1_DMPULLDOWN	BIT(28)
++#define USBPCR1_PORT_RST	BIT(21)
++
++/*Oscillator and Power Control Register*/
++#define OPCR_USB_SPENDN		BIT(7)
++
++
++#define LCR_LPM_MASK		(0x3)
++#define LCR_LPM_SLEEP		(0x1)
++
++#define OPCR_ERCS		(0x1<<2)
++#define OPCR_PD			(0x1<<3)
++#define OPCR_IDLE		(0x1<<31)
++
++
++#define cpm_inl(off)		inl(CPM_IOBASE + (off))
++#define cpm_outl(val,off)	outl(val,CPM_IOBASE + (off))
++#define cpm_clear_bit(val,off)	do{cpm_outl((cpm_inl(off) & ~(1<<(val))),off);}while(0)
++#define cpm_set_bit(val,off)	do{cpm_outl((cpm_inl(off) |  (1<<val)),off);}while(0)
++#define cpm_test_bit(val,off)	(cpm_inl(off) & (0x1<<val))
++
++#endif
+diff --git a/arch/mips/xburst2/soc-m300/include/soc/ddr.h b/arch/mips/xburst2/soc-m300/include/soc/ddr.h
+new file mode 100644
+index 000000000..4cbb89b1e
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/include/soc/ddr.h
+@@ -0,0 +1,293 @@
++/*
++ * JZ4780 ddr definitions
++ *
++ * Copyright (c) 2013 Ingenic Semiconductor Co.,Ltd
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __DDR_H__
++#define __DDR_H__
++
++#include <soc/base.h>
++
++/*
++ * DDR Controller Registers
++ **/
++#define DDR_MEM_PHY_BASE		0x20000000
++
++#define DDRC_AHB2_OFFSET	0xb34f0000
++#define DDRC_APB_OFFSET		0xb3012000
++#define DDR_PHY_OFFSET  (-0x4e0000 + 0x1000)
++
++#define DDRC_STATUS		0x0
++#define DDRC_CFG		0x8
++#define DDRC_CTRL		0x10
++#define DDRC_LMR		0x18
++#define DDRC_DLP		0x20
++#define DDRC_AUTOSR_EN	0x28
++#define DDRC_AUTOSR_CNT	0x30
++#define DDRC_REFCNT		0x38
++#define DDRC_DBGINFO	0xE8
++#define DDRC_TIMING(n)	(0x40 + 8 * (n - 1))
++#define DDRC_MMAP0		0x78
++#define DDRC_MMAP1		0x80
++#define DDRC_HREGPRO	0xd8
++#define DDRC_DWCFG		(DDRC_APB_OFFSET + 0x00)
++#define DDRC_DWSTATUS	(DDRC_APB_OFFSET + 0x04)
++#define DDRC_REMAP(n)	(DDRC_APB_OFFSET + 0x08 + 4 * (n - 1))
++#define DDRC_CGUC0		(DDRC_APB_OFFSET + 0x64)
++#define DDRC_CGUC1		(DDRC_APB_OFFSET + 0x68)
++#define DDRC_PREGPRO	(DDRC_APB_OFFSET + 0x6c)
++
++/*
++ * DDR Innophy registers
++ * */
++#define DDRP_INNOPHY_PHY_RST			(DDR_PHY_OFFSET + 0x000)
++#define DDRP_INNOPHY_MEM_CFG			(DDR_PHY_OFFSET + 0x004)
++#define DDRP_INNOPHY_DQ_WIDTH			(DDR_PHY_OFFSET + 0x07c)
++#define DDRP_INNOPHY_CL					(DDR_PHY_OFFSET + 0x014)
++#define DDRP_INNOPHY_CWL				(DDR_PHY_OFFSET + 0x01c)
++#define DDRP_INNOPHY_AL					(DDR_PHY_OFFSET + 0x018)
++#define DDRP_INNOPHY_PLL_FBDIV			(DDR_PHY_OFFSET + 0x080)
++#define DDRP_INNOPHY_PLL_CTRL			(DDR_PHY_OFFSET + 0x084)
++#define DDRP_INNOPHY_PLL_PDIV			(DDR_PHY_OFFSET + 0x088)
++#define DDRP_INNOPHY_PLL_LOCK			(DDR_PHY_OFFSET + 0xc8)
++#define DDRP_INNOPHY_TRAINING_CTRL		(DDR_PHY_OFFSET + 0x008)
++#define DDRP_INNOPHY_CALIB_DONE			(DDR_PHY_OFFSET + 0xcc)
++#define DDRP_INNOPHY_CALIB_DELAY_AL		(DDR_PHY_OFFSET + 0x190)
++#define DDRP_INNOPHY_CALIB_DELAY_AH		(DDR_PHY_OFFSET + 0x194)
++#define DDRP_INNOPHY_CALIB_BYPASS_AL	(DDR_PHY_OFFSET + 0x118)
++#define DDRP_INNOPHY_CALIB_BYPASS_AH	(DDR_PHY_OFFSET + 0x158)
++#define DDRP_INNOPHY_WL_MODE1			(DDR_PHY_OFFSET + 0x00c)
++#define DDRP_INNOPHY_WL_MODE2			(DDR_PHY_OFFSET + 0x010)
++#define DDRP_INNOPHY_WL_DONE			(DDR_PHY_OFFSET + 0x0c0)
++#define DDRP_INNOPHY_INIT_COMP			(DDR_PHY_OFFSET + 0x0d0)
++
++
++/*
++ * DDRC REGISTER BITS DEFINE
++ * */
++
++/* DDRC Status Register */
++#define DDRC_DSTATUS_MISS	(1 << 6)
++#define DDRC_ST_DPDN		(1 << 5) /* 0 DDR memory is NOT in deep-power-down state
++										1 DDR memory is in deep-power-down state */
++#define DDRC_ST_PDN		(1 << 4) /* 0 DDR memory is NOT in power-down state
++									1 DDR memory is in power-down state */
++#define DDRC_ST_AREF		(1 << 3) /* 0 DDR memory is NOT in auto-refresh state
++										1 DDR memory is in auto-refresh state */
++#define DDRC_ST_SREF		(1 << 2) /* 0 DDR memory is NOT in self-refresh state
++										1 DDR memory is in self-refresh state */
++#define DDRC_ST_CKE1		(1 << 1) /* 0 CKE1 Pin is low
++										1 CKE1 Pin is high */
++#define DDRC_ST_CKE0		(1 << 0) /* 0 CKE0 Pin is low
++										1 CKE0 Pin is high */
++
++/* DDRC Configure Register */
++#define DDRC_CFG_ROW1_BIT	29 /* Row Address width. */
++#define DDRC_CFG_ROW1_MASK	(0x7 << DDRC_CFG_ROW1_BIT)
++#define DDRC_CFG_COL1_BIT	26 /* Row Address width. */
++#define DDRC_CFG_COL1_MASK	(0x7 << DDRC_CFG_COL1_BIT)
++#define DDRC_CFG_BA1		25 /* Bank Address width of DDR memory */
++#define DDRC_CFG_IMBA		(1 << 16)
++#define DDRC_CFG_ROW0_BIT	13 /* Row Address width. */
++#define DDRC_CFG_ROW0_MASK	(0x7 << DDRC_CFG_ROW0_BIT)
++#define DDRC_CFG_COL0_BIT	10 /* Row Address width. */
++#define DDRC_CFG_COL0_MASK	(0x7 << DDRC_CFG_COL1_BIT)
++#define DDRC_CFG_BA0		9 /* Bank Address width of DDR memory */
++
++#define DDRC_CFG_TYPE_BIT	3
++#define DDRC_CFG_TYPE_MASK	(0x7 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR1	(2 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_MDDR	(3 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR2	(4 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_LPDDR2	(5 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR3	(6 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_LPDDR3	(7 << DDRC_CFG_TYPE_BIT)
++
++#define DDRC_CFG_ODTEN		(1 << 2)  /* ODT EN */
++#define DDRC_CFG_CS1EN		(1 << 1)  /* DDR Chip-Select-1 Enable */
++#define DDRC_CFG_CS0EN		(1 << 0)  /* DDR Chip-Select-0 Enable */
++
++/* DDRC Control Register */
++#define DDRC_CTRL_DFI_RST	(1 << 23)
++#define DDRC_CTRL_DLL_RST	(1 << 22)
++#define DDRC_CTRL_CTL_RST	(1 << 21)
++#define DDRC_CTRL_CFG_RST	(1 << 20)
++#define DDRC_CTRL_ACTPD		(1 << 15) /* 0 Precharge all banks before entering power-down
++										 1 Do not precharge banks before entering power-down */
++#define DDRC_CTRL_PDT_BIT	12 /* Power-Down Timer */
++#define DDRC_CTRL_PDT_MASK	(0x7 << DDRC_CTRL_PDT_BIT)
++#define DDRC_CTRL_PDT_DIS	(0 << DDRC_CTRL_PDT_BIT) /* power-down disabled */
++#define DDRC_CTRL_PDT_8		(1 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 8 tCK idle */
++#define DDRC_CTRL_PDT_16	(2 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 16 tCK idle */
++#define DDRC_CTRL_PDT_32	(3 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 32 tCK idle */
++#define DDRC_CTRL_PDT_64	(4 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 64 tCK idle */
++#define DDRC_CTRL_PDT_128	(5 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 128 tCK idle */
++
++#define DDRC_CTRL_PD_CCE	(1 << 7) /* Power down clk freq change enable */
++#define DDRC_CTRL_DPD		(1 << 6) /* 1 Drive external MDDR device entering Deep-Power-Down mode */
++#define DDRC_CTRL_SR		(1 << 5) /* 1 Drive external DDR device entering self-refresh mode
++										0 Drive external DDR device exiting self-refresh mode */
++#define DDRC_CTRL_SR_CCE	(1 << 4) /* Self refresh clk stop request enable */
++#define DDRC_CTRL_CKE		(1 << 1) /* 0 Not set CKE Pin High, 1 Set CKE Pin HIGH */
++#define DDRC_CTRL_RESET		(1 << 0) /* 0 End resetting ddrc_controller, 1 Resetting ddrc_controller */
++
++/* DDRC DFI low power handshake control register */
++#define DDRC_DDLP_TCTLUDP_BIT	24
++#define DDRC_DDLP_TCTLUDP_FF	(0xff << DDRC_DDLP_TCTLUDP_BIT)
++
++/* DDRC Load-Mode-Register */
++#define DDRC_LMR_DDR_ADDR_BIT	12 /* When performing a DDR command, DDRC_ADDR[13:0]
++									  corresponding to external DDR address Pin A[13:0] */
++#define DDRC_LMR_DDR_ADDR_MASK	(0xfffff << DDRC_LMR_DDR_ADDR_BIT)
++
++#define DDRC_LMR_MA_BIT		16 /* FOR LPDDR2, MA[9:0] */
++#define DDRC_LMR_OP_BIT		24 /* FOR LPDDR2, OP[9:0] */
++
++#define DDRC_LMR_BA_BIT		9 /* When performing a DDR command, BA[2:0]
++								 corresponding to external DDR address Pin BA[2:0]. */
++#define DDRC_LMR_BA_MASK	(0x7 << DDRC_LMR_BA_BIT)
++#define DDRC_LMR_CMD_BIT	6
++#define DDRC_LMR_CMD_MASK	(0x7 << DDRC_LMR_CMD_BIT)
++#define DDRC_LMR_CMD_PREC	(0 << DDRC_LMR_CMD_BIT)/* Precharge one bank/All banks */
++#define DDRC_LMR_CMD_AUREF	(1 << DDRC_LMR_CMD_BIT)/* Auto-Refresh */
++#define DDRC_LMR_CMD_LMR	(2 << DDRC_LMR_CMD_BIT)/* Load Mode Register */
++#define DDRC_LMR_CMD_ZQCL_CS0	(3 << DDRC_LMR_CMD_BIT)/* ZQCL for DDR3 on CS0 */
++#define DDRC_LMR_CMD_ZQCL_CS1	(4 << DDRC_LMR_CMD_BIT)/* ZQCL for DDR3 on CS1 */
++#define DDRC_LMR_CMD_ZQCS_CS0	(5 << DDRC_LMR_CMD_BIT)/* ZQCS for DDR3 on CS0 */
++#define DDRC_LMR_CMD_ZQCS_CS1	(6 << DDRC_LMR_CMD_BIT)/* ZQCS for DDR3 on CS1 */
++
++#define DDRC_LMR_TMRD_BIT	1
++#define DDRC_LMR_TMRD_MASK	(0x1f << DDRC_LMR_TMRD_BIT)
++#define DDRC_LMR_START		(1 << 0) /* 0 No command is performed
++										1 On the posedge of START, perform a command
++										defined by CMD field */
++
++/* DDRC  Auto-Refresh Counter */
++#define DDRC_REFCNT_REF_EN		(1 << 0) /* Enable Refresh Counter */
++#define DDRC_REFCNT_CLK_DIV_BIT		1  /* Clock Divider for auto-refresh counter. */
++#define DDRC_REFCNT_CLK_DIV_MASK	(0x7 << DDRC_REFCNT_CLKDIV_BIT)
++
++#define DDRC_REFCNT_PREREF_CNT_BIT	4
++#define DDRC_REFCNT_PREREF_CNT_MASK	(0xf << DDRC_REFCNT_PREREF_CNT_BIT)
++#define DDRC_REFCNT_PREREF_CNT(val)	(val << DDRC_REFCNT_PREREF_CNT_BIT)
++#define DDRC_REFCNT_PREREF_CNT_DEFAULT	DDRC_REFCNT_PREREF_CNT(8)
++
++#define DDRC_REFCNT_CNT_BIT		8  /* 8-bit counter */
++#define DDRC_REFCNT_CNT_MASK		(0xff << DDRC_REFCNT_CNT_BIT)
++
++#define DDRC_REFCNT_CON_BIT		16 /* Constant value used to compare with CNT value. */
++#define DDRC_REFCNT_CON_MASK		(0xff << DDRC_REFCNT_CON_BIT)
++
++#define DDRC_REFCNT_TRFC_BIT		24
++#define DDRC_REFCNT_TRFC_MASK		(0x3f << DDRC_REFCNT_TRFC_BIT)
++
++#define DDRC_REFCNT_PREREF_EN_BIT	30
++#define DDRC_REFCNT_PREREF_EN		(1 << DDRC_REFCNT_PREREF_EN_BIT)
++
++#define DDRC_REFCNT_PBREF_EN_BIT	31
++#define DDRC_REFCNT_PBREF_EN		(1 << DDRC_REFCNT_PBREF_EN_BIT)
++
++/* DDRC Memory Map Config Register */
++#define DDRC_MMAP_BASE_BIT		8 /* base address */
++#define DDRC_MMAP_BASE_MASK		(0xff << DDRC_MMAP_BASE_BIT)
++#define DDRC_MMAP_MASK_BIT		0 /* address mask */
++#define DDRC_MMAP_MASK_MASK		(0xff << DDRC_MMAP_MASK_BIT)
++
++#define DDRC_MMAP0_BASE			(0x20 << DDRC_MMAP_BASE_BIT)
++#define DDRC_MMAP1_BASE_64M		(0x24 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++#define DDRC_MMAP1_BASE_128M		(0x28 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++#define DDRC_MMAP1_BASE_256M		(0x30 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++
++#define DDRC_MMAP_MASK_64_64		(0xfc << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++#define DDRC_MMAP_MASK_128_128		(0xf8 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++#define DDRC_MMAP_MASK_256_256		(0xf0 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++
++/* DDR device data width configure register */
++#define DDRC_DWCFG_DFI_INIT_START	(1 << 3)
++
++/* DDR device status register */
++#define DDRC_DWSTATUS_DFI_INIT_COMP	(1 << 0)
++
++/* DDRC AHB Bus Register Protection Register */
++#define DDRC_HREGPRO_HPRO_EN		(1 << 0)
++
++/* DDRC APB Bus Register Protection Register */
++#define DDRC_PREGPRO_PPRO_EN		(1 << 0)
++
++
++/* DDRC clock gate unit configure 0 */
++#define DDRC_CGU_PORT7		(1 << 28)
++#define DDRC_CGU_PORT6		(1 << 24)
++#define DDRC_CGU_PORT5		(1 << 20)
++#define DDRC_CGU_PORT4		(1 << 16)
++#define DDRC_CGU_PORT3		(1 << 12)
++#define DDRC_CGU_PORT2		(1 << 8)
++#define DDRC_CGU_PORT1		(1 << 4)
++#define DDRC_CGU_PORT0		(1 << 0)
++
++/* DDRC clock gate unit configure 1 */
++#define DDRC_CGU_BWM		(1 << 8)
++#define DDRC_CGU_PCTRL		(1 << 4)
++#define DDRC_CGU_SCH		(1 << 1)
++#define DDRC_CGU_PA		(1 << 0)
++
++
++
++/*
++ * DDR INNOPHY REGISTER BITS DEFINE
++ * */
++
++/* DDRP DQ Width Register */
++#define DDRP_DQ_WIDTH_DQ_H		(1 << 1)
++#define DDRP_DQ_WIDTH_DQ_L		(1 << 0)
++
++/* DDRP Pll Ctrl Register */
++#define DDRP_PLL_CTRL_PLLPDEN		(1 << 1)
++
++/* DDRP Training Ctrl Register */
++#define DDRP_TRAINING_CTRL_WL_BP	(1 << 3)
++#define DDRP_TRAINING_CTRL_WL_START	(1 << 2)
++#define DDRP_TRAINING_CTRL_DSCSE_BP	(1 << 1)
++#define DDRP_TRAINING_CTRL_DSACE_START	(1 << 0)
++
++/* DDRP Training Done Register */
++#define DDRP_CALIB_DONE_HDQCFB 		(1 << 3)
++#define DDRP_CALIB_DONE_LDQCFB 		(1 << 2)
++#define DDRP_CALIB_DONE_HDQCFA 		(1 << 1)
++#define DDRP_CALIB_DONE_LDQCFA 		(1 << 0)
++#define DDRP_CALIB_DONE_HWRLFB 		(1 << 3)
++#define DDRP_CALIB_DONE_LWRLFB 		(1 << 2)
++#define DDRP_CALIB_DONE_HWRLFA 		(1 << 1)
++#define DDRP_CALIB_DONE_LWRLFA 		(1 << 0)
++
++/* DDRP CALIB BP Register */
++#define DDRP_CALIB_BP_CYCLESELBH_BIT	4
++#define DDRP_CALIB_BP_OPHCSELBH_BIT	3
++#define DDRP_CALIB_BP_DLLSELBH_BIT	0
++
++/* DDRP Init Complete Register */
++#define DDRP_INIT_COMP			(1 << 0)
++
++#define DDRP_PLL_LOCK			(1 << 3)
++
++#define REG32(addr) *(volatile unsigned int *)(addr)
++
++#define ddr_writel(value, reg)	(REG32(DDRC_BASE + reg) = (value))
++#define ddr_readl(reg)		REG32(DDRC_BASE + reg)
++#endif /* __DDR_H__ */
+diff --git a/arch/mips/xburst2/soc-m300/include/soc/extal.h b/arch/mips/xburst2/soc-m300/include/soc/extal.h
+new file mode 100644
+index 000000000..398b5912f
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/include/soc/extal.h
+@@ -0,0 +1,12 @@
++
++#ifndef __JZSOC_EXTAL_H__
++#define __JZSOC_EXTAL_H__
++
++#define JZ_EXTAL_RTC	32768     /* RTC extal freq: 32.768 KHz */
++#define JZ_EXTAL	(CONFIG_EXTAL_CLOCK * 1000000)
++
++#ifdef CONFIG_PALLADIUM_PLATFORM
++#define PALLADIUM_CLK_INPURT  (500*1000000)
++#endif
++
++#endif
+diff --git a/arch/mips/xburst2/soc-m300/include/soc/rtc.h b/arch/mips/xburst2/soc-m300/include/soc/rtc.h
+new file mode 100644
+index 000000000..871add1fc
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/include/soc/rtc.h
+@@ -0,0 +1,96 @@
++#ifndef __RTC_H__
++#define __RTC_H__
++
++/*
++ * RTC registers offset address definition
++ */
++#define RTC_RTCCR		(0x00)	/* rw, 32, 0x00000081 */
++#define RTC_RTCSR		(0x04)	/* rw, 32, 0x???????? */
++#define RTC_RTCSAR		(0x08)	/* rw, 32, 0x???????? */
++#define RTC_RTCGR		(0x0c)	/* rw, 32, 0x0??????? */
++
++#define RTC_HCR			(0x20)  /* rw, 32, 0x00000000 */
++#define RTC_HWFCR		(0x24)  /* rw, 32, 0x0000???0 */
++#define RTC_HRCR		(0x28)  /* rw, 32, 0x00000??0 */
++#define RTC_HWCR		(0x2c)  /* rw, 32, 0x00000008 */
++#define RTC_HWRSR		(0x30)  /* rw, 32, 0x00000000 */
++#define RTC_HSPR		(0x34)  /* rw, 32, 0x???????? */
++#define RTC_WENR		(0x3c)  /* rw, 32, 0x00000000 */
++#define RTC_WKUPPINCR		(0x48)	/* rw, 32, 0x00050064*/
++
++/*
++ * RTC registers common define
++ */
++
++/* RTC control register(RTCCR) */
++#define RTCCR_WRDY		BIT(7)
++#define RTCCR_1HZ		BIT(6)
++#define RTCCR_1HZIE		BIT(5)
++#define RTCCR_AF		BIT(4)
++#define RTCCR_AIE		BIT(3)
++#define RTCCR_AE		BIT(2)
++#define RTCCR_SELEXC		BIT(1)
++#define RTCCR_RTCE		BIT(0)
++
++
++/* Generate the bit field mask from msb to lsb */
++#define BITS_H2L(msb, lsb)  ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))
++
++/* RTC regulator register(RTCGR) */
++#define RTCGR_LOCK		BIT(31)
++#define RTCGR_ADJC_LSB		16
++#define RTCGR_ADJC_MASK		BITS_H2L(25, RTCGR_ADJC_LSB)
++#define RTCGR_NC1HZ_LSB		0
++#define RTCGR_NC1HZ_MASK	BITS_H2L(15, RTCGR_NC1HZ_LSB)
++
++/* Hibernate control register(HCR) */
++#define HCR_PD			BIT(0)
++
++/* Hibernate wakeup filter counter register(HWFCR) */
++#define HWFCR_LSB		5
++#define HWFCR_MASK		BITS_H2L(15, HWFCR_LSB)
++#define HWFCR_WAIT_TIME(ms, clk) (((ms)*(clk)/1000+0xf) > HWFCR_MASK ? HWFCR_MASK : ((ms)*(clk)/1000+0xf) & HWFCR_MASK)
++
++/* Hibernate reset counter register(HRCR) */
++#define HRCR_LSB		11
++#define HRCR_MASK		BITS_H2L(14, HRCR_LSB)
++#define HRCR_WAIT_TIME(ms, clk) (((ms)*(clk)/1000 + 0x3ff - 0x800) > HRCR_MASK ? HRCR_MASK : \
++								 ((ms)*(clk)/1000 + 0x3ff - 0x800) & HRCR_MASK)
++
++
++/* Hibernate wakeup control register(HWCR) */
++/* Power detect default value; this value means enable */
++#define EPDET_LSB		3
++#define EPDET_DEFAULT           (0x5aa5a5a << EPDET_LSB)
++#define EPDET_ENABLE		(0x5aa5a5a << EPDET_LSB)
++#define EPDET_DISABLE		(0x1a55a5a5 << EPDET_LSB)
++#define HWCR_EALM		BIT(0)
++
++
++/* Hibernate wakeup status register(HWRSR) */
++#define HWRSR_APD		BIT(8)
++#define HWRSR_HR		BIT(5)
++#define HWRSR_PPR		BIT(4)
++#define HWRSR_PIN		BIT(1)
++#define HWRSR_ALM		BIT(0)
++
++/* write enable pattern register(WENR) */
++#define WENR_WEN		BIT(31)
++#define WENR_WENPAT_LSB		0
++#define WENR_WENPAT_MASK	BITS_H2L(15, WENR_WENPAT_LSB)
++#define WENR_WENPAT_WRITABLE	(0xa55a)
++
++/* Hibernate scratch pattern register(HSPR) */
++#define HSPR_RTCV               0x52544356      /* The value is 'RTCV', means rtc is valid */
++
++/*WKUP_PIN_RST control register (WKUPPINCR)*/
++#define WKUPPINCR_BIAS_CTRL	(0x1 << 16)	/* fix value*/
++#define WKUPPINCR_OSC_EN        BIT(18)
++#define WKUPPINCR_P_JUD_LEN_LSB	4
++#define WKUPPINCR_P_JUD_LEN_MASK	BITS_H2L(7, WKUPPINCR_P_JUD_LEN_LSB)
++#define WKUPPINCR_P_JUD_LEN(s)  ((s) << WKUPPINCR_P_JUD_LEN_LSB) > WKUPPINCR_P_JUD_LEN_MASK ? \
++	WKUPPINCR_P_JUD_LEN_MASK : (s) << WKUPPINCR_P_JUD_LEN_LSB
++#define WKUPPINCR_P_JUD_EN	(0x4)
++/* The divider is decided by the RTC clock frequency. */
++#define RTC_FREQ_DIVIDER	(32768 - 1)
++#endif	/* __RTC_H__ */
+diff --git a/arch/mips/xburst2/soc-m300/include/soc/sfc.h b/arch/mips/xburst2/soc-m300/include/soc/sfc.h
+new file mode 100644
+index 000000000..b1684bec9
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/include/soc/sfc.h
+@@ -0,0 +1,211 @@
++#ifndef __SFC_REGISTER_H
++#define __SFC_REGISTER_H
++
++/* SFC register */
++
++#define	SFC_GLB0			(0x0000)
++#define	SFC_DEV_CONF			(0x0004)
++#define	SFC_DEV_STA_EXP			(0x0008)
++#define	SFC_DEV0_STA_RT			(0x000c)
++#define	SFC_DEV_STA_MSK			(0x0010)
++#define	SFC_TRAN_CONF0(n)		(0x0014 + (n * 4))
++#define	SFC_TRAN_LEN			(0x002c)
++#define	SFC_DEV_ADDR(n)			(0x0030 + (n * 4))
++#define	SFC_DEV_ADDR_PLUS(n)		(0x0048 + (n * 4))
++#define	SFC_MEM_ADDR			(0x0060)
++#define	SFC_TRIG			(0x0064)
++#define	SFC_SR				(0x0068)
++#define	SFC_SCR				(0x006c)
++#define	SFC_INTC			(0x0070)
++#define	SFC_FSM				(0x0074)
++#define	SFC_CGE				(0x0078)
++#define SFC_CMD_IDX                     (0x007c)
++#define SFC_COL_ADDR                    (0x0080)
++#define SFC_ROW_ADDR                    (0x0084)
++#define SFC_STA_ADDR0                   (0x0088)
++#define SFC_STA_ADDR1                   (0x008c)
++#define SFC_DES_ADDR                    (0x0090)
++#define SFC_GLB1			(0x0094)
++#define SFC_DEV1_STA_RT			(0x0098)
++#define	SFC_TRAN_CONF1(n)		(0x009c + (n * 4))
++#define SFC_CDT                         (0x0800)  //0x800 ~ 0xbff
++#define	SFC_RM_DR			(0x1000)
++
++/* For SFC_GLB0 */
++#define GLB0_POLL_TIME_OFFSET		(16)
++#define GLB0_POLL_TIME_MSK		(0xffff << GLB0_POLL_TIME_OFFSET)
++#define GLB0_DES_EN			(1 << 15)
++#define GLB0_CDT_EN			(1 << 14)
++#define	GLB0_TRAN_DIR			(1 << 13)
++#define GLB0_TRAN_DIR_WRITE		(1)
++#define GLB0_TRAN_DIR_READ		(0)
++#define	GLB0_THRESHOLD_OFFSET		(7)
++#define GLB0_THRESHOLD_MSK		(0x3f << GLB0_THRESHOLD_OFFSET)
++#define GLB0_OP_MODE			(1 << 6)
++#define GLB0_OP_OFFSET                   (6)
++#define SLAVE_MODE			(0x0)
++#define DMA_MODE			(0x1)
++#define GLB0_PHASE_NUM_OFFSET		(3)
++#define GLB0_PHASE_NUM_MSK		(0x7  << GLB0_PHASE_NUM_OFFSET)
++#define GLB0_WP_EN			(1 << 2)
++#define GLB0_BURST_MD_OFFSET		(0)
++#define GLB0_BURST_MD_MSK		(0x3  << GLB0_BURST_MD_OFFSET)
++
++/* For SFC_DEV_CONF */
++#define DEV_CONF_STA_ENDIAN_OFFSET	(31)
++#define	STA_ENDIAN_LSB			(0)
++#define	STA_ENDIAN_MSB			(1)
++#define	DEV_CONF_SMP_DELAY_OFFSET	(16)
++#define	DEV_CONF_SMP_DELAY_MSK		(0x1f << DEV_CONF_SMP_DELAY_OFFSET)
++#define DEV_CONF_SMP_DELAY_0		(0)
++#define DEV_CONF_SMP_DELAY_45		(1)
++#define DEV_CONF_SMP_DELAY_90		(2)
++#define DEV_CONF_SMP_DELAY_135		(3)
++#define DEV_CONF_SMP_DELAY_180		(4)
++#define DEV_CONF_SMP_DELAY_225		(5)
++#define DEV_CONF_SMP_DELAY_270		(6)
++#define DEV_CONF_SMP_DELAY_315		(7)
++#define DEV_CONF_SMP_DELAY_1		(8)
++#define DEV_CONF_SMP_DELAY_2		(16)
++#define DEV_CONF_CMD_TYPE		(0x1 << 15)
++#define DEV_CONF_STA_TYPE_OFFSET	(13)
++#define DEV_CONF_STA_TYPE_MSK		(0x3 << DEV_CONF_STA_TYPE_OFFSET)
++#define DEV_CONF_THOLD_OFFSET		(11)
++#define	DEV_CONF_THOLD_MSK		(0x3 << DEV_CONF_THOLD_OFFSET)
++#define DEV_CONF_TSETUP_OFFSET		(9)
++#define DEV_CONF_TSETUP_MSK		(0x3 << DEV_CONF_TSETUP_OFFSET)
++#define DEV_CONF_TSH_OFFSET		(5)
++#define DEV_CONF_TSH_MSK		(0xf << DEV_CONF_TSH_OFFSET)
++#define DEV_CONF_CPHA			(0x1 << 4)
++#define DEV_CONF_CPOL			(0x1 << 3)
++#define DEV_CONF_CEDL			(0x1 << 2)
++#define DEV_CONF_HOLDDL			(0x1 << 1)
++#define DEV_CONF_WPDL			(0x1 << 0)
++
++/* For SFC_TRAN_CONF0 */
++#define TRAN_CONF0_CLK_MODE		(29)
++#define	TRAN_CONF0_CLK_MODE_MSK		(0x7 << TRAN_CONF0_CLK_MODE)
++#define TRAN_CONF0_CLK_MODE_SSS		(0)
++#define TRAN_CONF0_CLK_MODE_SSD		(1)
++#define TRAN_CONF0_CLK_MODE_SDS		(2)
++#define TRAN_CONF0_CLK_MODE_SDD		(3)
++#define TRAN_CONF0_CLK_MODE_DSS		(4)
++#define TRAN_CONF0_CLK_MODE_DSD		(5)
++#define TRAN_CONF0_CLK_MODE_DDS		(6)
++#define TRAN_CONF0_CLK_MODE_DDD		(7)
++#define	TRAN_CONF0_ADDR_WIDTH_OFFSET	(26)
++#define	TRAN_CONF0_ADDR_WIDTH_MSK	(0x7 << TRAN_CONF0_ADDR_WIDTH_OFFSET)
++#define TRAN_CONF0_POLLEN		(1 << 25)
++#define TRAN_CONF0_POLL_OFFSET		(25)
++#define TRAN_CONF0_CMDEN		(1 << 24)
++#define TRAN_CONF0_FMAT			(1 << 23)
++#define TRAN_CONF0_FMAT_OFFSET		(23)
++#define TRAN_CONF0_DMYBITS_OFFSET	(17)
++#define TRAN_CONF0_DMYBITS_MSK		(0x3f << TRAN_CONF0_DMYBITS_OFFSET)
++#define TRAN_CONF0_DATEEN		(1 << 16)
++#define TRAN_CONF0_DATEEN_OFFSET	(16)
++#define	TRAN_CONF0_CMD_OFFSET		(0)
++#define	TRAN_CONF0_CMD_MSK		(0xffff << TRAN_CONF0_CMD_OFFSET)
++
++/* For SFC_TRAN_CONF1 */
++#define TRAN_CONF1_DATA_ENDIAN		(1 << 18)
++#define TRAN_CONF1_DATA_ENDIAN_OFFSET	(18)
++#define TRAN_CONF1_DATA_ENDIAN_LSB	(0)
++#define TRAN_CONF1_DATA_ENDIAN_MSB	(1)
++#define TRAN_CONF1_WORD_UNIT_OFFSET	(16)
++#define TRAN_CONF1_WORD_UNIT_MSK	(3 << 16)
++#define TRAN_CONF1_TRAN_MODE_OFFSET	(4)
++#define TRAN_CONF1_TRAN_MODE_MSK	(0xf << TRAN_CONF1_TRAN_MODE_OFFSET)
++#define TRAN_CONF1_SPI_STANDARD		(0x0)
++#define TRAN_CONF1_SPI_DUAL		(0x1)
++#define TRAN_CONF1_SPI_QUAD		(0x5)
++#define TRAN_CONF1_SPI_IO_QUAD		(0x6)
++#define TRAN_CONF1_SPI_OCTAL		(0x9)
++#define TRAN_CONF1_SPI_IO_OCTAL		(0xa)
++#define TRAN_CONF1_SPI_FULL_OCTAL	(0xb)
++
++
++/* For SFC_TRIG */
++#define TRIG_FLUSH			(1 << 2)
++#define TRIG_STOP			(1 << 1)
++#define TRIG_START			(1 << 0)
++
++/* For SFC_SR */
++#define SFC_WORKING		(1 << 7)
++#define SFC_BUSY		(0x3 << 5)
++#define	SFC_END			(1 << 4)
++#define SFC_TREQ		(1 << 3)
++#define SFC_RREQ		(1 << 2)
++#define SFC_OVER		(1 << 1)
++#define SFC_UNDER		(1 << 0)
++
++/* For SFC_SCR */
++#define	CLR_END			(1 << 4)
++#define CLR_TREQ		(1 << 3)
++#define CLR_RREQ		(1 << 2)
++#define CLR_OVER		(1 << 1)
++#define CLR_UNDER		(1 << 0)
++
++//SFC_CMD_IDX
++#define CMD_IDX_MSK                     (0x3f << 0)
++#define CDT_DATAEN_MSK                  (0x1 << 31)
++#define CDT_DATAEN_OFF                  (31)
++#define CDT_DIR_MSK                     (0x1 << 30)
++#define CDT_DIR_OFF                     (30)
++
++/* For SFC_GLB1 */
++#define GLB1_DQS_EN			(1 << 2)
++#define GLB1_CHIP_SEL_OFFSET		(0)
++#define GLB1_CHIP_SEL_MSK		(0x3 << 0)
++#define GLB1_CHIP_SEL_0			(0)
++#define GLB1_CHIP_SEL_1			(1)
++#define GLB1_CHIP_SEL_01		(2)
++
++#define N_MAX			6
++#define MAX_SEGS		128
++
++#define CHANNEL_0		0
++#define CHANNEL_1		1
++#define CHANNEL_2		2
++#define CHANNEL_3		3
++#define CHANNEL_4		4
++#define CHANNEL_5		5
++
++#define ENABLE			1
++#define DISABLE			0
++
++#define COM_CMD			1	// common cmd
++#define POLL_CMD		2	// the cmd will poll the status of flash,ext: read status
++
++#define DMA_OPS			1
++#define CPU_OPS			0
++
++#define TM_STD_SPI		0
++#define TM_DI_DO_SPI	1
++#define TM_DIO_SPI		2
++#define TM_FULL_DIO_SPI	3
++#define TM_QI_QO_SPI	5
++#define TM_QIO_SPI		6
++#define	TM_FULL_QIO_SPI	7
++#define TM_OCTAL_SPT		9
++#define TM_OCTAL_IO_SPI		10
++#define TM_OCTAL_FULL_SPI	11
++
++
++#define DEFAULT_CDT		1
++#define UPDATE_CDT		2
++#define DEFAULT_ADDRSIZE	3
++#define DEFAULT_ADDRMODE	0
++
++
++#define THRESHOLD		32
++
++#define SFC_NOR_RATE    110
++#define DEF_ADDR_LEN    3
++#define DEF_TCHSH       6
++#define DEF_TSLCH       6
++#define DEF_TSHSL_R     20
++#define DEF_TSHSL_W     50
++
++
++#endif
+diff --git a/arch/mips/xburst2/soc-m300/include/soc/tcsm_layout.h b/arch/mips/xburst2/soc-m300/include/soc/tcsm_layout.h
+new file mode 100644
+index 000000000..2de46b7bd
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/include/soc/tcsm_layout.h
+@@ -0,0 +1,53 @@
++#ifndef __TCSM_LAYOUT_H__
++#define __TCSM_LAYOUT_H__
++
++/**
++ *      |-------------|
++ *      |    BANK0    |
++ *      |-------------|     <--- SLEEP_TCSM_BOOTCODE_TEXT
++ *      | BOOT CODE   |
++ *      |-------------|     <--- SLEEP_TCSM_RESUMECODE_TEXT
++ *      |    ...      |
++ *      | RESUME CODE |
++ *      |    ...      |
++ *      |-------------|     <--- SLEEP_TCSM_RESUME_DATA
++ *      |    ...      |
++ *      | RESUME DATA |
++ *      |    ...      |
++ *      |_____________|     <--- SLEEP_TCSM_CPU_RESMUE_SP
++ *
++ *
++ *      |-------------|
++ *      |    BANK1    |
++ *      |-------------|     <--- TO BE DEFINED
++ *      |             |
++ *      |             |
++ *      |    ...      |
++ *      |  VOICE DATA |
++ *      |    ...      |
++ *      |             |
++ *      |             |
++ *      |_____________|
++ *
++ */
++
++#define SLEEP_TCSM_SPACE           0xb3422000
++#define VOICE_TCSM_DATA_BUF	   0xb3423000
++#define TCSM_BANK_LEN              4096
++
++#define SLEEP_TCSM_BOOT_TEXT       (SLEEP_TCSM_SPACE)
++#define SLEEP_TCSM_BOOT_LEN        64
++#define SLEEP_TCSM_BOOT_END        (SLEEP_TCSM_BOOT_TEXT + SLEEP_TCSM_BOOT_LEN)
++
++#define SLEEP_TCSM_RESUME_TEXT     (SLEEP_TCSM_BOOT_END)
++#define SLEEP_TCSM_RESUME_LEN      2048
++#define SLEEP_TCSM_RESUME_END      (SLEEP_TCSM_RESUME_TEXT + SLEEP_TCSM_RESUME_LEN)
++
++#define SLEEP_TCSM_RESUME_DATA     (SLEEP_TCSM_RESUME_END)
++
++#define SLEEP_TCSM_SPACE_END       (SLEEP_TCSM_SPACE + TCSM_BANK_LEN)
++
++#define SLEEP_TCSM_CPU_RESMUE_SP   SLEEP_TCSM_SPACE_END - 4
++
++
++#endif	/*  __TCSM_LAYOUT_H__ */
+diff --git a/arch/mips/xburst2/soc-m300/include/war.h b/arch/mips/xburst2/soc-m300/include/war.h
+new file mode 100644
+index 000000000..fd1ef3147
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/include/war.h
+@@ -0,0 +1,27 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
++ */
++#ifndef __ASM_MACH_INGENIC_WAR_H__
++#define __ASM_MACH_INGENIC_WAR_H__
++
++#define R4600_V1_INDEX_ICACHEOP_WAR	0
++#define R4600_V1_HIT_CACHEOP_WAR	0
++#define R4600_V2_HIT_CACHEOP_WAR	0
++#define R5432_CP0_INTERRUPT_WAR		0
++#define BCM1250_M3_WAR			0
++#define SIBYTE_1956_WAR			0
++#define MIPS4K_ICACHE_REFILL_WAR	0
++#define MIPS_CACHE_SYNC_WAR		1
++#define MIPS_BRIDGE_SYNC_WAR            1
++#define TX49XX_ICACHE_INDEX_INV_WAR	0
++#define RM9000_CDEX_SMP_WAR		0
++#define ICACHE_REFILLS_WORKAROUND_WAR	0
++#define R10000_LLSC_WAR			0
++#define MIPS34K_MISSED_ITLB_WAR		0
++
++#endif
++
+diff --git a/arch/mips/xburst2/soc-m300/libdmmu.c b/arch/mips/xburst2/soc-m300/libdmmu.c
+new file mode 100644
+index 000000000..457799b7c
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/libdmmu.c
+@@ -0,0 +1,1087 @@
++/*
++ * This driver is used by VPU driver.
++ *
++ * Copyright (C) 2015 Ingenic Semiconductor Co., Ltd.
++ *	http://www.ingenic.com
++ * Author:	Yan Zhengting <zhengting.yan@ingenic.com>
++ * Modify by:	Sun Jiwei <jiwei.sun@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/platform_device.h>
++#include <linux/fs.h>
++#include <linux/file.h>
++#include <linux/mm.h>
++#include <linux/list.h>
++#include <linux/mutex.h>
++#include <linux/proc_fs.h>
++#include <linux/debugfs.h>
++#include <linux/mempolicy.h>
++#include <linux/mm_types.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <asm/current.h>
++#include <asm/cacheflush.h>
++#include <asm/tlbflush.h>
++#include <asm/io.h>
++#include <linux/vmalloc.h>
++#include <linux/sched.h>
++#include <ingenic_proc.h>
++#include <linux/module.h>
++#include <linux/mmu_context.h>
++#include <linux/mmu_notifier.h>
++
++
++#include <libdmmu.h>
++#define print_dbg(f, arg...) printk(KERN_INFO "dpu: %s, %d: " f "\n", __func__, __LINE__, ## arg)
++
++#define MAP_COUNT		0x10
++#define MAP_CONUT_MASK		0xff0
++
++#define DMMU_PTE_VLD 		0x01
++#define DMMU_PMD_VLD 		0x01
++
++#define KSEG0_LOW_LIMIT		0x80000000
++#define KSEG1_HEIGH_LIMIT	0xC0000000
++
++enum mem_break{
++    MODE1,  /* 13 24 57 68 911 1012 ... */
++    MODE2,  /* 13 24 35 46 57 68 79 810 ... */
++    MODE3   /* 12 34 56 78 ... */
++};
++
++LIST_HEAD(handle_list);
++static unsigned long reserved_pte = 0;
++static unsigned long res_pte_paddr;
++
++struct pmd_node {
++	unsigned int count;
++	unsigned long index;
++	unsigned long page;
++	struct list_head list;
++};
++
++struct map_node {
++	struct device *dev;
++	unsigned long start;
++	unsigned long len;
++	struct list_head list;
++};
++
++struct dmmu_handle {
++	pid_t tgid;
++	unsigned long pdg;
++	struct mutex lock;
++	struct list_head list;
++	struct list_head pmd_list;
++	struct list_head map_list;
++	struct list_head dev_notifier_list;
++
++	struct mm_struct *handle_mm; /* mm struct used to match exit_mmap notify */
++
++	struct mmu_notifier mn;
++};
++
++
++/* for test */
++static struct dmmu_handle *find_handle(void);
++static struct dmmu_handle *create_handle(void);
++static void dmmu_cache_wback(struct dmmu_handle *h);
++static int dmmu_mm_dev_release(struct dmmu_handle *h);
++
++int dmmu_flush_cache(unsigned long vaddr, unsigned long len)
++{
++	struct list_head *pos, *next;
++	struct dmmu_handle *h = NULL;
++	struct map_node *n = NULL;
++	unsigned long *pgd, *pte_phys, *pte;
++	unsigned long virpage_phy;
++	unsigned long v_end = vaddr+len;
++	int found = 0;
++	int index;
++
++	h = find_handle();
++	if(!h){
++		printk("%s find handle err!\n",__func__);
++		return -1;
++	}
++	if (vaddr & 0xfff) {
++		printk("%s addr align page err!\n",__func__);
++		return -1;
++	}
++	list_for_each_safe(pos, next, &h->map_list) {
++		n = list_entry(pos, struct map_node, list);
++		if((vaddr >= n->start) &&
++			((vaddr+len) <= (n->start + n->len))) {
++			found = 1;
++			break;
++		}
++	}
++	if(!found) {
++		printk("%s addr err!\n",__func__);
++		return -1;
++	}
++	pgd = (unsigned long *)h->pdg;
++	while(vaddr < v_end) {
++		index = vaddr>>22;
++		pte_phys = (unsigned long *)(pgd[index] & ~DMMU_PMD_VLD);
++		pte = (unsigned long *)phys_to_virt((unsigned long)pte_phys);
++		index = ((vaddr & 0x3ff000) >> 12);
++		virpage_phy = pte[index] & ~DMMU_PTE_VLD;
++		dma_cache_wback((unsigned long)phys_to_virt(virpage_phy),PAGE_SIZE);
++		vaddr+=PAGE_SIZE;
++	}
++	return 0;
++}
++
++EXPORT_SYMBOL(dmmu_flush_cache);
++static int make_smash_list(struct dmmu_handle *h, unsigned long vaddr, unsigned long (**base)[2], unsigned int *len)
++{
++    unsigned long *pgd = (unsigned long *)h->pdg;
++    unsigned long (*list_smash)[2] = NULL;
++    unsigned int list_len = 0;
++    unsigned long *pte, *pte_phys;
++    unsigned int i, index;
++
++    struct list_head *pos, *next;
++	struct map_node *n;
++
++    list_for_each_safe(pos, next, &h->map_list) {
++        n = list_entry(pos, struct map_node, list);
++        if(vaddr == n->start) {
++            list_len = (n->len) >> 12;
++            break;
++        }
++    }
++
++    if (list_len) {
++        list_smash = kmalloc(list_len * 2 * 4, GFP_KERNEL);
++        if (list_smash) {
++            i = 0;
++            while(i < list_len) {
++                list_smash[i][0] = (unsigned long)(vaddr & 0xfffff000);
++
++		index = vaddr>>22;
++                pte_phys = (unsigned long *)(pgd[index] & ~DMMU_PMD_VLD);
++
++
++		pte = (unsigned long *)phys_to_virt((unsigned long)pte_phys);
++
++		index = ((vaddr & 0x3ff000) >> 12);
++//		printk(">>>>>>virt = 0x%lx, phys = 0x%lx\n", vaddr,
++//				*((unsigned long int *) (((unsigned long)pte_phys+index*4) | 0xa0000000)));
++		list_smash[i][1] = pte[index];
++
++                vaddr+=0x1000;
++		i++;
++            }
++        }
++    }
++
++    if (list_smash) {
++        *base = list_smash;
++        *len = list_len;
++        return 0;
++    } else {
++        return -1;
++    }
++}
++EXPORT_SYMBOL(dmmu_dump_map);
++
++int dmmu_dump_map(unsigned long vaddr)
++{
++	struct dmmu_handle *h = NULL;
++    unsigned long (*list_smash)[2] = NULL;
++    unsigned int list_len = 0;
++    unsigned long *tmp;
++
++	h = find_handle();
++	if(!h)
++		h = create_handle();
++	if(!h)
++		return -1;
++    /* 检查4k对� */
++    if (vaddr & 0xfff){
++        return -1;
++    }
++
++	mutex_lock(&h->lock);
++
++    if (make_smash_list(h, vaddr, &list_smash, &list_len)) {
++	    mutex_unlock(&h->lock);
++        return -1;
++    } else {
++        unsigned int i;
++        for (i = 0; i<list_len; i++) {
++	    tmp = (unsigned long*)((list_smash[i][1] & ~1) | 0xa0000000);
++            printk("[virt: 0x%08lx ---> phys: 0x%08lx] uncache: 0x%08lx\n",
++			    list_smash[i][0],list_smash[i][1],(unsigned long)tmp);
++
++	    printk("value[0] = 0x%08lx, value[1] = 0x%08lx value[2] = 0x%08lx value[1013] = 0x%08lx\n",
++			tmp[0], tmp[1], tmp[2], tmp[1013]);
++        }
++    }
++
++	mutex_unlock(&h->lock);
++    kfree((void*)list_smash);
++
++    return 0;
++}
++
++    /* 13 24 57 68 911 1012 ... */
++static int smash_mode1(unsigned long (*base)[2], unsigned int len)
++{
++    unsigned int i;
++    unsigned long tmp;
++    if (len >= 4) {
++        for (i=0; i<len; i += 2) {
++            tmp = base[i][1];
++            base[i][1] = base[i+1][1];
++            base[i+1][1] = tmp;
++        }
++    }
++    return 0;
++}
++
++    /* 13 24 35 46 57 68 79 810 ... */
++static int smash_mode2(unsigned long (*base)[2], unsigned int len)
++{
++    /* unsigned int i; */
++    /* unsigned long tmp; */
++    return 0;
++}
++
++    /* 12 34 56 78 ... */
++static int smash_mode3(unsigned long (*base)[2], unsigned int len)
++{
++    unsigned int i;
++    unsigned long tmp;
++if (len >= 4) {
++        for (i=0; i<len/2-1; i++) {
++            tmp = base[i][1];
++            base[i][1] = base[len-1-i][1];
++            base[len-1-i][1] = tmp;
++        }
++        for (i=0; i<len; i += 2) {
++            tmp = base[i][1];
++            base[i][1] = base[i+1][1];
++            base[i+1][1] = tmp;
++        }
++    }
++    return 0;
++}
++
++static int update_dmmu_pte(struct dmmu_handle *h, unsigned long vaddr,
++		           unsigned long (**base)[2], unsigned int len)
++{
++    unsigned long *pgd = (unsigned long *)h->pdg;
++    unsigned long *pte;
++    unsigned int i, index;
++
++    for (i=0; i<len; i++) {
++	index = vaddr>>22;
++        pte = (unsigned long *)(pgd[index] & ~DMMU_PMD_VLD);
++	pte = (unsigned long *)phys_to_virt((unsigned long)pte);
++
++	index = ((vaddr & 0x3ff000) >> 12);
++	pte[index] = (*base)[i][1];
++         vaddr+=0x1000;
++    }
++    return 0;
++}
++
++static int update_process_pte(unsigned long vaddr, unsigned long (**base)[2], unsigned int len)
++{
++    unsigned int i;
++    pgd_t *pgdir;
++    pmd_t *pmdir;
++    pte_t *pte;
++    spin_lock(&current->mm->page_table_lock);
++    for (i=0; i<len; i++) {
++        pgdir = pgd_offset(current->mm, vaddr);
++        if(pgd_none(*pgdir) || pgd_bad(*pgdir))
++            return 0;
++        pmdir = pmd_offset((pud_t *)pgdir, vaddr);
++        if(pmd_none(*pmdir) || pmd_bad(*pmdir))
++            return 0;
++        pte = pte_offset_kernel(pmdir,vaddr);
++        if (pte_present(*pte)){
++	  pte->pte = (*base)[i][1];
++	}
++        vaddr += 4096;
++    }
++    spin_unlock(&current->mm->page_table_lock);
++    return 0;
++}
++
++int dmmu_memory_smash(unsigned long vaddr, int smash_mode)
++{
++	struct dmmu_handle *h = NULL;
++    unsigned long (*list_smash)[2] = NULL;
++    unsigned int list_len = 0;
++	struct vm_area_struct * vma;
++
++	h = find_handle();
++	if(!h){
++		h = create_handle();
++	}
++	if(!h)
++		return -1;
++
++    /* 检查4k对� */
++    if (vaddr & 0xfff){
++        return -1;
++    }
++
++	mutex_lock(&h->lock);
++
++    if (make_smash_list(h, vaddr, &list_smash, &list_len)) {
++	    mutex_unlock(&h->lock);
++        return -1;
++    } else {
++        switch (smash_mode) {
++            case MODE1:
++		print_dbg("smash_mode = %u\n",smash_mode);
++                smash_mode1(list_smash, list_len);
++                break;
++            case MODE2:
++		print_dbg("smash_mode = %u\n",smash_mode);
++                smash_mode2(list_smash, list_len);
++                break;
++            case MODE3:
++		print_dbg("smash_mode = %u\n",smash_mode);
++                smash_mode3(list_smash, list_len);
++                break;
++            default:
++                break;
++        }
++    }
++    update_dmmu_pte(h, vaddr, &list_smash, list_len);
++    update_process_pte(vaddr, &list_smash, list_len);
++
++	dmmu_cache_wback(h);
++	vma = find_vma(current->mm, vaddr);
++	flush_tlb_range(vma, vaddr, vaddr+(list_len*PAGE_SIZE));
++
++	mutex_unlock(&h->lock);
++    kfree(list_smash);
++
++    return 0;
++}
++EXPORT_SYMBOL(dmmu_memory_smash);
++
++static struct map_node *check_map(struct dmmu_handle *h,unsigned long vaddr,unsigned long len)
++{
++	struct list_head *pos, *next;
++	struct map_node *n;
++	list_for_each_safe(pos, next, &h->map_list) {
++		n = list_entry(pos, struct map_node, list);
++		if(vaddr == n->start && len == n->len)
++			return n;
++	}
++	return NULL;
++}
++
++static void handle_add_map(struct device *dev,struct dmmu_handle *h,unsigned long vaddr,unsigned long len)
++{
++	struct map_node *n = kmalloc(sizeof(*n),GFP_KERNEL);
++	if(n == NULL) {
++		printk("malloc map_list node failed !!\n");
++		return;
++	}
++	n->dev = dev;
++	n->start = vaddr;
++	n->len = len;
++	INIT_LIST_HEAD(&n->list);
++	list_add(&n->list,&h->map_list);
++}
++
++static unsigned int get_pfn(unsigned int vaddr)
++{
++	pgd_t *pgdir;
++	pmd_t *pmdir;
++	pte_t *pte;
++	pgdir = pgd_offset(current->mm, vaddr);
++	if(pgd_none(*pgdir) || pgd_bad(*pgdir)) {
++		return 0;
++	}
++	pmdir = pmd_offset((pud_t *)pgdir, vaddr);
++	if(pmd_none(*pmdir) || pmd_bad(*pmdir)) {
++		return 0;
++	}
++	pte = pte_offset_kernel(pmdir,vaddr);
++	if (pte_present(*pte)) {
++
++		return pte_pfn(*pte) << PAGE_SHIFT;
++	}
++
++	return 0;
++}
++
++static unsigned long dmmu_v2pfn(unsigned long vaddr)
++{
++	if(vaddr < KSEG0_LOW_LIMIT)
++		return get_pfn(vaddr);
++
++	if(vaddr >= KSEG0_LOW_LIMIT && vaddr < KSEG1_HEIGH_LIMIT)
++		return virt_to_phys((void *)vaddr);
++
++	panic("dmmu_v2pfn error!");
++	return 0;
++}
++
++static unsigned long unmap_node(struct pmd_node *n,unsigned long vaddr,unsigned long end,int check)
++{
++	unsigned int *pte = (unsigned int *)n->page;
++	int index = ((vaddr & 0x3ff000) >> 12);
++	int free = !check || (--n->count == 0);
++	struct page *page = NULL;
++
++	if(vaddr && end) {
++		while(index < 1024 && vaddr < end) {
++			if(pte[index] & MAP_CONUT_MASK) {
++				pte[index] -= MAP_COUNT;
++			} else {
++				page = pfn_to_page(pte[index] >> PAGE_SHIFT);
++
++				ClearPageReserved(page);
++				pte[index] = reserved_pte;
++			}
++			index++;
++			vaddr += 4096;
++		}
++	}
++
++	if(free) {
++		ClearPageReserved(virt_to_page((void *)n->page));
++		free_page(n->page);
++		list_del(&n->list);
++		kfree(n);
++	}
++
++	return vaddr;
++}
++
++static unsigned long map_node(struct pmd_node *n,unsigned int vaddr,unsigned int end)
++{
++	unsigned int *pte = (unsigned int *)n->page;
++	int index = ((vaddr & 0x3ff000) >> 12);
++	struct page * page = NULL;
++	unsigned long pfn = 0;
++
++
++	while(index < 1024 && vaddr < end) {
++		if(pte[index] == reserved_pte) {
++
++			mmap_write_lock(current->mm);
++
++			pfn = dmmu_v2pfn(vaddr) >> PAGE_SHIFT;
++			page = pfn_to_page(pfn);
++
++			SetPageReserved(page);
++
++			pte[index] = (pfn << PAGE_SHIFT) | DMMU_PTE_VLD;
++
++			mmap_write_unlock(current->mm);
++		} else {
++			pte[index] += MAP_COUNT;
++		}
++		index++;
++		vaddr += 4096;
++	}
++	n->count++;
++	return vaddr;
++}
++
++static struct pmd_node *find_node(struct dmmu_handle *h,unsigned int vaddr)
++{
++	struct list_head *pos, *next;
++	struct pmd_node *n;
++
++	list_for_each_safe(pos, next, &h->pmd_list) {
++		n = list_entry(pos, struct pmd_node, list);
++		if(n->index == (vaddr & 0xffc00000))
++			return n;
++	}
++	return NULL;
++}
++
++static struct pmd_node *add_node(struct dmmu_handle *h,unsigned int vaddr)
++{
++	int i;
++	unsigned long *pte;
++	unsigned long *pgd = (unsigned long *)h->pdg;
++	struct pmd_node *n = kmalloc(sizeof(*n),GFP_KERNEL);
++	INIT_LIST_HEAD(&n->list);
++	n->count = 0;
++	n->index = vaddr & 0xffc00000;
++	n->page = __get_free_page(GFP_KERNEL);
++	SetPageReserved(virt_to_page((void *)n->page));
++
++	pte = (unsigned long *)n->page;
++	for(i=0;i<1024;i++)
++		pte[i] = reserved_pte;
++
++	list_add(&n->list, &h->pmd_list);
++
++	pgd[vaddr>>22] = dmmu_v2pfn(n->page) | DMMU_PMD_VLD;
++	return n;
++}
++
++static struct dmmu_handle *find_handle(void)
++{
++	struct list_head *pos, *next;
++	struct dmmu_handle *h;
++
++
++	list_for_each_safe(pos, next, &handle_list) {
++		h = list_entry(pos, struct dmmu_handle, list);
++		if(h->tgid == current->tgid)
++			return h;
++	}
++	return NULL;
++}
++
++/**
++* @brief unmap node from map list, clear each pmd_node in pmd_list,
++* 	Not free handle, let dmmu_unmap_all do it.
++*
++* @param h
++*
++* @return
++*/
++static int dmmu_unmap_node_unlock(struct dmmu_handle *h)
++{
++	struct map_node *cn;
++	struct list_head *pos, *next;
++
++	unsigned long vaddr;
++	int len;
++	unsigned long end;
++
++	struct pmd_node *node;
++
++	list_for_each_safe(pos, next, &h->map_list) {
++		/* find and delete a map node from map_list */
++		cn = list_entry(pos, struct map_node, list);
++		vaddr = cn->start;
++		len = cn->len;
++		end = vaddr + len;
++
++		while(vaddr < end) {
++			node = find_node(h,vaddr);
++			if(node)
++				vaddr = unmap_node(node,vaddr,end,1);
++		}
++
++		list_del(&cn->list);
++		kfree(cn);
++	}
++
++
++	return 0;
++
++}
++
++
++void dmmu_mm_release(struct mmu_notifier *mn,
++                struct mm_struct *mm)
++{
++	struct dmmu_handle *h = container_of(mn, struct dmmu_handle, mn);
++
++	printk("===== dmmu release mm (TODO: not checked) ====h: %p\n", h);
++
++	if(h->handle_mm != mm) {
++		return;
++	}
++
++	mutex_lock(&h->lock);
++
++	dmmu_mm_dev_release(h);
++
++	dmmu_unmap_node_unlock(h);
++
++	mutex_unlock(&h->lock);
++}
++
++static const struct mmu_notifier_ops dmmu_mm_notifier_ops = {
++        .release = dmmu_mm_release,
++};
++
++
++static struct dmmu_handle *create_handle(void)
++{
++	struct dmmu_handle *h;
++	unsigned int pgd_index;
++	unsigned long *pgd;
++
++	h = kmalloc(sizeof(struct dmmu_handle),GFP_KERNEL);
++	if(!h)
++		return NULL;
++
++	h->tgid = current->tgid;
++	h->pdg = __get_free_page(GFP_KERNEL);
++	if(!h->pdg) {
++		pr_err("%s %d, Get free page for PGD error\n",
++				__func__, __LINE__);
++		kfree(h);
++		return NULL;
++	}
++	SetPageReserved(virt_to_page((void *)h->pdg));
++
++	pgd = (unsigned long *)h->pdg;
++
++	for (pgd_index=0; pgd_index < PTRS_PER_PGD; pgd_index++)
++		pgd[pgd_index] = res_pte_paddr;
++
++	INIT_LIST_HEAD(&h->list);
++	INIT_LIST_HEAD(&h->pmd_list);
++	INIT_LIST_HEAD(&h->map_list);
++	INIT_LIST_HEAD(&h->dev_notifier_list);
++	mutex_init(&h->lock);
++
++	/* register exit_mmap notify */
++	h->handle_mm = current->mm;
++
++	h->mn.ops = &dmmu_mm_notifier_ops;
++
++	mmu_notifier_register(&h->mn, h->handle_mm);
++
++	list_add(&h->list, &handle_list);
++
++	return h;
++}
++
++static int dmmu_make_present(unsigned long addr,unsigned long end)
++{
++#if 0
++	unsigned long i;
++	for(i = addr; i < end; i += 4096) {
++		*(volatile unsigned char *)(i) = 0;
++	}
++	*(volatile unsigned char *)(end - 1) = 0;
++	return 0;
++#else
++	int ret, len, write;
++	struct vm_area_struct * vma;
++	unsigned long vm_page_prot;
++
++	mmap_write_lock(current->mm);
++	vma = find_vma(current->mm, addr);
++	if (!vma) {
++		printk("dmmu_make_present error. addr=%lx len=%lx\n",addr,end-addr);
++		mmap_write_unlock(current->mm);
++		return -1;
++	}
++
++	if(vma->vm_flags & VM_PFNMAP) {
++		mmap_write_unlock(current->mm);
++		return 0;
++	}
++	write = (vma->vm_flags & VM_WRITE) != 0;
++	BUG_ON(addr >= end);
++	BUG_ON(end > vma->vm_end);
++
++	vm_page_prot = pgprot_val(vma->vm_page_prot);
++	vma->vm_page_prot = __pgprot(vm_page_prot | _PAGE_VALID| _PAGE_ACCESSED | _PAGE_PRESENT);
++
++	len = DIV_ROUND_UP(end, PAGE_SIZE) - addr/PAGE_SIZE;
++	ret = get_user_pages(addr, len, write, NULL, NULL);
++	vma->vm_page_prot = __pgprot(vm_page_prot);
++	if (ret < 0) {
++		printk("dmmu_make_present get_user_pages error(%d). addr=%lx len=%lx\n",0-ret,addr,end-addr);
++		mmap_write_unlock(current->mm);
++		return ret;
++	}
++
++	mmap_write_unlock(current->mm);
++	return ret == len ? 0 : -1;
++#endif
++}
++
++static void dmmu_cache_wback(struct dmmu_handle *h)
++{
++	struct list_head *pos, *next;
++	struct pmd_node *n;
++
++	dma_cache_wback(h->pdg,PAGE_SIZE);
++
++	list_for_each_safe(pos, next, &h->pmd_list) {
++		n = list_entry(pos, struct pmd_node, list);
++		dma_cache_wback(n->page,PAGE_SIZE);
++	}
++}
++
++static void dmmu_dump_handle(struct seq_file *m, void *v, struct dmmu_handle *h);
++
++unsigned long dmmu_map(struct device *dev,unsigned long vaddr,unsigned long len)
++{
++	int end = vaddr + len;
++	struct dmmu_handle *h;
++	struct pmd_node *node;
++
++	h = find_handle();
++	if(!h)
++		h = create_handle();
++	if(!h)
++		return 0;
++
++	mutex_lock(&h->lock);
++#ifdef DEBUG
++	printk("(pid %d)dmmu_map %lx %lx================================================\n",h->tgid,vaddr,len);
++#endif
++	if(check_map(h,vaddr,len))
++	{
++		mutex_unlock(&h->lock);
++		return dmmu_v2pfn(h->pdg);
++	}
++
++	if(dmmu_make_present(vaddr,vaddr+len))
++	{
++		mutex_unlock(&h->lock);
++		return 0;
++	}
++
++	handle_add_map(dev,h,vaddr,len);
++
++	while(vaddr < end) {
++		node = find_node(h,vaddr);
++		if(!node) {
++			node = add_node(h,vaddr);
++		}
++		vaddr = map_node(node,vaddr,end);
++	}
++	dmmu_cache_wback(h);
++#ifdef DEBUG
++	dmmu_dump_handle(NULL,NULL,h);
++#endif
++	mutex_unlock(&h->lock);
++
++	return dmmu_v2pfn(h->pdg);
++}
++EXPORT_SYMBOL(dmmu_map);
++
++static int dmmu_mm_dev_release(struct dmmu_handle *h)
++{
++	struct dmmu_mm_notifier *n = NULL;
++	struct list_head *pos, *next;
++
++	list_for_each_safe(pos, next, &h->dev_notifier_list) {
++		n = list_entry(pos, struct dmmu_mm_notifier, list);
++		if(n && n->ops && n->ops->mm_release) {
++			n->ops->mm_release(n->data);
++		}
++
++		list_del(&n->list);
++	}
++
++
++	return 0;
++}
++
++
++int dmmu_register_mm_notifier(struct dmmu_mm_notifier *dmn)
++{
++	int dev_already_registered = 0;
++	struct dmmu_mm_notifier *n = NULL;
++	struct dmmu_handle *h;
++	struct list_head *pos, *next;
++
++	h = find_handle();
++	if(!h) {
++		return -EINVAL;
++	}
++
++	mutex_lock(&h->lock);
++
++	list_for_each_safe(pos, next, &h->dev_notifier_list) {
++		n = list_entry(pos, struct dmmu_mm_notifier, list);
++
++		if(n == dmn) {
++			/* already in dev_notifier_list*/
++			dev_already_registered = 1;
++		}
++
++	}
++
++	if(dev_already_registered) {
++		goto out;
++	}
++
++	list_add_tail(&dmn->list, &h->dev_notifier_list);
++out:
++	mutex_unlock(&h->lock);
++	return 0;
++}
++EXPORT_SYMBOL(dmmu_register_mm_notifier);
++
++int dmmu_unmap(struct device *dev,unsigned long vaddr, int len)
++{
++	unsigned long end = vaddr + len;
++	struct dmmu_handle *h;
++	struct pmd_node *node;
++	struct map_node *n;
++
++	h = find_handle();
++	if(!h) {
++		return 0;
++	}
++
++	mutex_lock(&h->lock);
++#ifdef DEBUG
++	printk("dmmu_unmap %lx %x**********************************************\n",vaddr,len);
++#endif
++	n = check_map(h,vaddr,len);
++	if(!n) {
++		mutex_unlock(&h->lock);
++		return -EAGAIN;
++	}
++	if(n->dev != dev) {
++		mutex_unlock(&h->lock);
++		return -EAGAIN;
++	}
++
++	list_del(&n->list);
++	kfree(n);
++
++	while(vaddr < end) {
++		node = find_node(h,vaddr);
++		if(node)
++			vaddr = unmap_node(node,vaddr,end,1);
++	}
++
++	if(list_empty(&h->pmd_list) && list_empty(&h->map_list)) {
++		list_del(&h->list);
++		ClearPageReserved(virt_to_page((void *)h->pdg));
++		free_page(h->pdg);
++		mutex_unlock(&h->lock);
++
++		mmu_notifier_unregister(&h->mn, h->handle_mm);
++
++		kfree(h);
++		return 0;
++	}
++
++	mutex_unlock(&h->lock);
++	return 0;
++}
++EXPORT_SYMBOL(dmmu_unmap);
++
++int dmmu_free_all(struct device *dev)
++{
++	struct dmmu_handle *h;
++	struct pmd_node *node;
++	struct map_node *cn;
++	struct list_head *pos, *next;
++
++	h = find_handle();
++	if(!h)
++		return 0;
++
++	mutex_lock(&h->lock);
++
++	list_for_each_safe(pos, next, &h->map_list) {
++		cn = list_entry(pos, struct map_node, list);
++		node = find_node(h,cn->start);
++		if(node)
++			unmap_node(node,cn->start,cn->len,1);
++		list_del(&cn->list);
++		kfree(cn);
++	}
++
++	list_for_each_safe(pos, next, &h->pmd_list) {
++		node = list_entry(pos, struct pmd_node, list);
++		if(node){
++			printk("WARN: pmd list should NULL\n");
++			unmap_node(node,0,0,0);
++		}
++	}
++
++	list_del(&h->list);
++	ClearPageReserved(virt_to_page((void *)h->pdg));
++	free_page(h->pdg);
++
++	mutex_unlock(&h->lock);
++	mmu_notifier_unregister(&h->mn, h->handle_mm);
++	kfree(h);
++	return 0;
++}
++
++/**
++* @brief release all resources, which should be called by driver close
++*
++* @param dev
++*
++* @return
++*/
++int dmmu_unmap_all(struct device *dev)
++{
++	struct dmmu_handle *h;
++	struct map_node *cn;
++	struct list_head *pos, *next;
++
++#ifdef DEBUG
++	printk("dmmu_unmap_all\n");
++#endif
++
++	h = find_handle();
++	if(!h) {
++		printk("dmmu unmap all not find hindle, maybe it has benn freed already, name: %s\n", dev->kobj.name);
++		return 0;
++	}
++
++	list_for_each_safe(pos, next, &h->map_list) {
++		cn = list_entry(pos, struct map_node, list);
++		if(dev == cn->dev) {
++			dmmu_unmap(dev,cn->start,cn->len);
++		}
++	}
++
++
++	if(list_empty(&h->map_list))
++		dmmu_free_all(dev);
++	return 0;
++}
++EXPORT_SYMBOL(dmmu_unmap_all);
++int __init dmmu_init(void)
++{
++	unsigned int pte_index;
++	unsigned long res_page_paddr;
++	unsigned long reserved_page;
++	unsigned int *res_pte_vaddr;
++
++	reserved_page = __get_free_page(GFP_KERNEL);
++	if (!reserved_page) {
++		pr_err("%s %d, Get reserved page error\n",
++				__func__, __LINE__);
++		return ENOMEM;
++	}
++	SetPageReserved(virt_to_page((void *)reserved_page));
++	reserved_pte = dmmu_v2pfn(reserved_page) | DMMU_PTE_VLD;
++
++	res_page_paddr = virt_to_phys((void *)reserved_page) | 0xFFF;
++
++	res_pte_vaddr = (unsigned int *)__get_free_page(GFP_KERNEL);
++	if (!res_pte_vaddr) {
++		pr_err("%s %d, Get free page for PTE error\n",
++				__func__, __LINE__);
++		free_page(reserved_page);
++		return ENOMEM;
++	}
++	SetPageReserved(virt_to_page(res_pte_vaddr));
++	res_pte_paddr = virt_to_phys((void *)res_pte_vaddr) | DMMU_PTE_VLD;
++
++	for (pte_index = 0; pte_index < PTRS_PER_PTE; pte_index++)
++		res_pte_vaddr[pte_index] = res_page_paddr;
++
++
++
++	return 0;
++}
++arch_initcall(dmmu_init);
++
++void dmmu_dump_vaddr(unsigned long vaddr)
++{
++	struct dmmu_handle *h;
++	struct pmd_node *node;
++
++	unsigned long *pmd,*pte;
++	h = find_handle();
++	if(!h) {
++		printk("dmmu_dump_vaddr %08lx error - h not found!\n",vaddr);
++		return;
++	}
++
++	node = find_node(h,vaddr);
++	if(!node) {
++		printk("dmmu_dump_vaddr %08lx error - node not found!\n",vaddr);
++		return;
++	}
++
++	pmd = (unsigned long *)h->pdg;
++	pte = (unsigned long *)node->page;
++
++	printk("pmd base = %p; pte base = %p\n",pmd,pte);
++	printk("pmd = %08lx; pte = %08lx\n",pmd[vaddr>>22],pte[(vaddr&0x3ff000)>>12]);
++}
++
++static void dmmu_dump_handle(struct seq_file *m, void *v, struct dmmu_handle *h)
++{
++	struct list_head *pos, *next;
++	struct map_node *n;
++
++	list_for_each_safe(pos, next, &h->map_list) {
++		n = list_entry(pos, struct map_node, list);
++		{
++			int i = 0;
++			int vaddr = n->start;
++			struct pmd_node *pn = find_node(h,vaddr);
++			unsigned int *pte = (unsigned int *)pn->page;
++
++			while(vaddr < (n->start + n->len)) {
++				if(i++%8 == 0)
++					printk("\nvaddr %08x : ",vaddr & 0xfffff000);
++				printk("%08x ",pte[(vaddr & 0x3ff000)>>12]);
++				vaddr += 4096;
++			}
++			printk("\n\n");
++		}
++	}
++}
++
++static int dmmu_proc_show(struct seq_file *m, void *v)
++{
++	struct list_head *pos, *next;
++	struct dmmu_handle *h;
++	volatile unsigned long flags;
++	local_irq_save(flags);
++		list_for_each_safe(pos, next, &handle_list) {
++			h = list_entry(pos, struct dmmu_handle, list);
++			dmmu_dump_handle(m, v, h);
++		}
++	local_irq_restore(flags);
++	return 0;
++}
++
++static int dmmu_open(struct inode *inode, struct file *file)
++{
++	return single_open(file, dmmu_proc_show, PDE_DATA(inode));
++}
++
++static const struct proc_ops dmmus_proc_fops ={
++	.proc_read = seq_read,
++	.proc_open = dmmu_open,
++	.proc_lseek = seq_lseek,
++	.proc_release = single_release,
++};
++
++static int __init init_dmmu_proc(void)
++{
++	struct proc_dir_entry *p;
++	p = jz_proc_mkdir("dmmu");
++	if (!p) {
++		printk("create_proc_entry for common dmmu failed.\n");
++		return -ENODEV;
++	}
++	proc_create("dmmus", 0600,p,&dmmus_proc_fops);
++
++	return 0;
++}
++
++module_init(init_dmmu_proc);
+diff --git a/arch/mips/xburst2/soc-m300/pm.c b/arch/mips/xburst2/soc-m300/pm.c
+new file mode 100644
+index 000000000..74e8d94c1
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/pm.c
+@@ -0,0 +1,252 @@
++#include <linux/init.h>
++#include <linux/pm.h>
++#include <linux/suspend.h>
++#include <linux/ctype.h>
++
++#include <soc/cache.h>
++#include <soc/base.h>
++#include <asm/io.h>
++#include <soc/ddr.h>
++#include <soc/base.h>
++#include <soc/cpm.h>
++#include "pm.h"
++#include "pm_sleep.h"
++#include "pm_fastboot.h"
++
++
++#define SLEEP_LEVEL		(*(volatile unsigned int *)0xb0000034 & 0xf)
++#define SLEEP_LEVEL_MAGIC	((*(volatile unsigned int *)0xb0000034 >> 16) & 0xffff)
++#define SLEEP_MAGIC		(0x0915)
++
++
++#ifdef DEBUG_PM
++static void m300_pm_gate_check(void)
++{
++	unsigned int gate0 = cpm_inl(CPM_CLKGR);
++	unsigned int gate1 = cpm_inl(CPM_CLKGR1);
++	int i;
++	int x;
++
++	printk("gate0 = 0x%08x\n", gate0);
++	printk("gate1 = 0x%08x\n", gate1);
++	for (i = 0; i < 32; i++) {
++		x = (gate0 >> i) & 1;
++		if (x == 0)
++			printk("warning : bit[%d] in clk gate0 is enabled\n", i);
++	}
++	for (i = 0; i < 32; i++) {
++		x = (gate1 >> i) & 1;
++		if (x == 0)
++			printk("warning : bit[%d] in clk gate1 is enabled\n", i);
++	}
++
++}
++#endif
++
++
++
++void load_func_to_tcsm(unsigned int *tcsm_addr,unsigned int *f_addr,unsigned int size)
++{
++	unsigned int instr;
++	int offset;
++	int i;
++#ifdef DEBUG_PM
++	printk("tcsm addr = %p %p size = %d\n",tcsm_addr,f_addr,size);
++#endif
++	for(i = 0;i < size / 4;i++) {
++		instr = f_addr[i];
++		if((instr >> 26) == 2){
++			offset = instr & 0x3ffffff;
++			offset = (offset << 2) - ((unsigned int)f_addr & 0xfffffff);
++			if(offset > 0) {
++				offset = ((unsigned int)tcsm_addr & 0xfffffff) + offset;
++				instr = (2 << 26) | (offset >> 2);
++			}
++		}
++		tcsm_addr[i] = instr;
++	}
++}
++
++static int soc_pm_idle(void)
++{
++	printk("soc pm idle \n");
++
++	load_func_to_sram();
++
++	soc_pm_idle_config();
++
++	return 0;
++}
++
++static int soc_pm_idle_pd(void)
++{
++	printk("soc pm idle pd \n");
++
++	load_func_to_sram();
++
++	soc_pm_idle_pd_config();
++
++	soc_set_reset_entry();
++
++	return 0;
++}
++
++static void soc_pm_sleep(void)
++{
++	printk("soc pm sleep \n");
++
++	load_func_to_sram();
++
++	soc_pm_sleep_config();
++
++	soc_set_reset_entry();
++}
++
++
++static void soc_pm_fastboot(void)
++{
++	printk("soc pm fastboot \n");
++
++	soc_pm_fastboot_config();
++
++	load_func_to_rtc_ram();
++
++	sys_save();
++}
++
++
++static void goto_sleep(unsigned int sleep_addr)
++{
++	mb();
++	save_goto(sleep_addr);
++	mb();
++}
++
++int m300_pm_enter(suspend_state_t state)
++{
++	unsigned int sleep_addr = 0;
++	unsigned int sleep_level = 0;
++
++	printk("m300 pm enter!!\n");
++
++	sleep_param->uart_base = (UART0_IOBASE | 0xa0000000) + UART_OFF * bc_idx;
++	sleep_param->state = state;
++
++	if (SLEEP_LEVEL_MAGIC == SLEEP_MAGIC) {
++		if ((state == PM_SUSPEND_STANDBY) && (SLEEP_LEVEL == IDLE)) {
++			soc_pm_idle();
++			sleep_addr = NORMAL_SLEEP_CODE_ADDR;
++		} else if ((state == PM_SUSPEND_STANDBY) && (SLEEP_LEVEL == IDLE_PD)) {
++			soc_pm_idle_pd();
++			sleep_addr = NORMAL_SLEEP_CODE_ADDR;
++		} else if ((state == PM_SUSPEND_MEM) && (SLEEP_LEVEL == SLEEP)) {
++			soc_pm_sleep();
++			sleep_addr = NORMAL_SLEEP_CODE_ADDR;
++		} else if ((state == PM_SUSPEND_MEM) && (SLEEP_LEVEL == FASTBOOT)) {
++			soc_pm_fastboot();
++			sleep_addr = FASTBOOT_SLEEP_CODE_ADDR;
++			sleep_level = FASTBOOT;
++		} else {
++			printk("error suspend state or suspend level ! \n");
++			return -1;
++		}
++	} else {
++		if (state == PM_SUSPEND_STANDBY) {
++			soc_pm_idle();
++			sleep_addr = NORMAL_SLEEP_CODE_ADDR;
++		} else if (state == PM_SUSPEND_MEM) {
++			soc_pm_sleep();
++			sleep_addr = NORMAL_SLEEP_CODE_ADDR;
++		} else {
++			printk("error suspend state ! \n");
++			return -1;
++		}
++	}
++
++
++#ifdef DEBUG_PM
++	printk("LCR: %08x\n", cpm_inl(CPM_LCR));
++	printk("OPCR: %08x\n", cpm_inl(CPM_OPCR));
++	m300_pm_gate_check();
++#endif
++
++
++	goto_sleep(sleep_addr);
++
++
++	if (sleep_level == FASTBOOT) {
++		soc_pm_wakeup_fastboot();
++	} else {
++		soc_pm_wakeup_idle_sleep();
++	}
++
++	return 0;
++}
++
++static int m300_pm_begin(suspend_state_t state)
++{
++	printk("m300 suspend begin\n");
++	return 0;
++}
++
++static void m300_pm_end(void)
++{
++	printk("m300 pm end!\n");
++}
++
++static int ingenic_pm_valid(suspend_state_t state)
++{
++	switch (state) {
++		case PM_SUSPEND_ON:
++		case PM_SUSPEND_STANDBY:
++		case PM_SUSPEND_MEM:
++			return 1;
++
++		default:
++			return 0;
++	}
++}
++static const struct platform_suspend_ops m300_pm_ops = {
++	.valid		= ingenic_pm_valid,
++	.begin		= m300_pm_begin,
++	.enter		= m300_pm_enter,
++	.end		= m300_pm_end,
++};
++
++
++int bc_idx = 0;
++static int __init suspend_console_setup(char *str)
++{
++
++	char buf[32];
++	char *s;
++
++	strncpy(buf, str, sizeof(buf) - 1);
++
++	for (s = buf; *s; s++)
++		if (isdigit(*s) || *s == ',')
++			break;
++
++	bc_idx = simple_strtoul(s, NULL, 10);
++
++	return 0;
++}
++
++__setup("console=", suspend_console_setup);
++
++
++
++
++/*
++ * Initialize suspend interface
++ */
++static int __init pm_init(void)
++{
++
++	suspend_set_ops(&m300_pm_ops);
++
++
++	return 0;
++}
++
++late_initcall(pm_init);
+diff --git a/arch/mips/xburst2/soc-m300/pm.h b/arch/mips/xburst2/soc-m300/pm.h
+new file mode 100644
+index 000000000..183b00c45
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/pm.h
+@@ -0,0 +1,175 @@
++#ifndef __PM_H__
++#define __PM_H__
++
++#include <soc/base.h>
++
++
++/*
++ *
++ *	|-----------------------|
++ *	|			|
++ *	|			|
++ *	|	RESUME_SP	|
++ *	|			|
++ *	|-----------------------|
++ *	|			|
++ *	|  	  PARAM		|
++ *	|			|
++ *	|-----------------------|
++ *	|			|
++ *	|			|
++ *	|	SLEEP_TEXT      |
++ *	|			|
++ *	|			|
++ *	|-----------------------|
++ *	|			|
++ *	|			|
++ *	|	RESUME_TEXT	|
++ *	|			|
++ *	|			|
++ *	|-----------------------|
++ *	|			|
++ *	|  RESUME_BOOTU_TEXTP	|
++ *	|			|
++ *	|-----------------------|     <------------ TCSM_START 0xb2400000
++ *
++ */
++#define SRAM_MEMORY_START	0xb2400000
++#define SRAM_MEMORY_END		0xb2407ff8
++#define RTC_MEMORY_START	0xb0004000
++#define RTC_MEMORY_END          0xb0005000
++
++
++#define NORMAL_RESUME_SP		(SRAM_MEMORY_END - 4)
++#define	NORMAL_RESUME_CODE1_ADDR	SRAM_MEMORY_START
++#define NORMAL_RESUME_CODE1_LEN		64
++#define	NORMAL_RESUME_CODE2_ADDR	(NORMAL_RESUME_CODE1_ADDR + NORMAL_RESUME_CODE1_LEN)
++#define NORMAL_RESUME_CODE2_LEN		(4096)
++#define NORMAL_SLEEP_CODE_ADDR		(NORMAL_RESUME_CODE2_ADDR + NORMAL_RESUME_CODE2_LEN)
++#define NORMAL_SLEEP_CODE_LEN		(3072)
++#define NORMAL_PARAM_ADDR		(NORMAL_SLEEP_CODE_ADDR + NORMAL_SLEEP_CODE_LEN)
++#define NORMAL_PARAM_LEN		(sizeof(struct sleep_param))
++
++
++#define FASTBOOT_RESUME_SP		(FASTBOOT_DATA_ADDR - 4)
++#define FASTBOOT_RESUME_CODE1_ADDR	RTC_MEMORY_START
++#define FASTBOOT_RESUME_CODE1_LEN	64
++#define FASTBOOT_RESUME_CODE2_ADDR	(FASTBOOT_RESUME_CODE1_ADDR + FASTBOOT_RESUME_CODE1_LEN)
++#define FASTBOOT_RESUME_CODE_LEN	0xb00
++#define FASTBOOT_SLEEP_CODE_ADDR	SRAM_MEMORY_START
++#define FASTBOOT_SLEEP_CODE_LEN		4096
++#define FASTBOOT_DATA_ADDR		0xb0004c00
++#define FASTBOOT_DATA_LEN		1024
++
++
++
++
++
++struct sleep_param {
++	suspend_state_t state;
++	unsigned int pdt;
++	unsigned int dpd;
++	unsigned int dlp;
++	unsigned int autorefresh;
++	unsigned int cpu_div;
++	unsigned int uart_base;
++	unsigned int sleep_level;
++};
++
++#define sleep_param ((struct sleep_param *)NORMAL_PARAM_ADDR)
++
++enum {
++	IDLE,
++	IDLE_PD,
++	SLEEP,
++	FASTBOOT,
++};
++
++
++void load_func_to_tcsm(unsigned int *tcsm_addr,unsigned int *f_addr,unsigned int size);
++
++
++
++long long save_goto(unsigned int func);
++int restore_goto(unsigned int func);
++
++
++static inline void rtc_write_reg(unsigned int reg, unsigned int val)
++{
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++	*(volatile unsigned int *)0xb000303c = 0xa55a;
++	while (!((*(volatile unsigned int *)0xb000303c >> 31) & 0x1) );
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++
++	*(volatile unsigned int *)reg = val;
++
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++}
++
++static inline unsigned int  rtc_read_reg(unsigned int reg)
++{
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++
++	return *(volatile unsigned int *)reg;
++}
++
++
++
++
++#define reg_ddr_phy(x)   (*(volatile unsigned int *)(0xb3011000 + ((x) << 2)))
++
++
++
++extern int bc_idx;
++
++
++
++/************************************************
++ *		debug interface
++ ***********************************************/
++
++#define DEBUG_PM
++#define PRINT_DEBUG
++
++
++#define U_IOBASE	(sleep_param->uart_base)
++#define UART_OFF        (0x1000)
++
++
++#define OFF_TDR         (0x00)
++#define OFF_LCR         (0x0C)
++#define OFF_LSR         (0x14)
++#define LSR_TDRQ        (1 << 5)
++#define LSR_TEMT        (1 << 6)
++
++
++#ifdef PRINT_DEBUG
++#define TCSM_PCHAR(x)                                                   \
++	*((volatile unsigned int*)(U_IOBASE+OFF_TDR)) = x;              \
++while ((*((volatile unsigned int*)(U_IOBASE + OFF_LSR)) & (LSR_TDRQ | LSR_TEMT)) != (LSR_TDRQ | LSR_TEMT))
++#else
++#define TCSM_PCHAR(x)
++#endif
++
++#define TCSM_DELAY(x)						\
++	do{							\
++	register unsigned int i = x;				\
++	while(i--)						\
++		__asm__ volatile("nop\n\t");			\
++	}while(0)
++
++static inline void serial_put_hex(unsigned int x) {
++	int i;
++	unsigned int d;
++	for(i = 7;i >= 0;i--) {
++		d = (x  >> (i * 4)) & 0xf;
++		if(d < 10) d += '0';
++		else d += 'A' - 10;
++		TCSM_PCHAR(d);
++	}
++	TCSM_PCHAR('\r');
++	TCSM_PCHAR('\n');
++}
++
++
++#endif
+diff --git a/arch/mips/xburst2/soc-m300/pm_fastboot.c b/arch/mips/xburst2/soc-m300/pm_fastboot.c
+new file mode 100644
+index 000000000..69980521a
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/pm_fastboot.c
+@@ -0,0 +1,503 @@
++#include <linux/init.h>
++#include <linux/pm.h>
++#include <linux/suspend.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++
++#include <soc/cache.h>
++#include <soc/base.h>
++#include <asm/io.h>
++#include <soc/ddr.h>
++#include <soc/base.h>
++#include <soc/cpm.h>
++#include <ccu.h>
++
++#include "pm.h"
++#include "pm_fastboot.h"
++
++
++static int fastboot_resume_code[] = {
++#include "fastboot_resume_code.hex"
++};
++
++static noinline void fastboot_cpu_resume(void);
++static noinline void fastboot_cpu_sleep(void);
++
++
++
++static void rtc_ram_write_enable(void)
++{
++	unsigned int tmp;
++
++	/* write RTC RAM enable */
++	tmp = rtc_read_reg(0xb0003048);
++	tmp &= ~(1 << 23);
++	tmp &= ~(1 << 22);
++	tmp |= (1 << 21);
++	tmp |= (1 << 20);
++	rtc_write_reg(0xb0003048, tmp);
++
++}
++
++static void rtc_ram_write_disable(void)
++{
++	unsigned int tmp;
++
++	/*exit write RTC RAM enable */
++	tmp = rtc_read_reg(0xb0003048);
++	tmp |= (1 << 22);
++	rtc_write_reg(0xb0003048, tmp);
++
++}
++
++
++
++
++
++static void ost_save(struct ost_regs *ost_regs)
++{
++	ost_regs->ostccr = *(volatile unsigned int *)0xb2100000;
++	ost_regs->oster = *(volatile unsigned int *)0xb2100004;
++	ost_regs->ostcr = *(volatile unsigned int *)0xb2100008;
++	ost_regs->ostfr = *(volatile unsigned int *)0xb210000c;
++	ost_regs->ostmr = *(volatile unsigned int *)0xb2100010;
++	ost_regs->ostdfr = *(volatile unsigned int *)0xb2100014;
++	ost_regs->ostcnt = *(volatile unsigned int *)0xb2100018;
++
++	ost_regs->g_ostccr = *(volatile unsigned int *)0xb2000000;
++	ost_regs->g_oster = *(volatile unsigned int *)0xb2000004;
++	ost_regs->g_ostcr = *(volatile unsigned int *)0xb2000008;
++	ost_regs->g_ostcnth = *(volatile unsigned int *)0xb200000c;
++	ost_regs->g_ostcntl = *(volatile unsigned int *)0xb2000010;
++	ost_regs->g_ostcntb = *(volatile unsigned int *)0xb2000014;
++
++}
++
++static void ost_restore(struct ost_regs *ost_regs)
++{
++	*(volatile unsigned int *)0xb2100000 = ost_regs->ostccr;
++	*(volatile unsigned int *)0xb2100008 = ost_regs->ostcr;
++	*(volatile unsigned int *)0xb210000c = ost_regs->ostfr;
++	*(volatile unsigned int *)0xb2100010 = ost_regs->ostmr;
++	*(volatile unsigned int *)0xb2100014 = ost_regs->ostdfr;
++	*(volatile unsigned int *)0xb2100018 = ost_regs->ostcnt;
++	*(volatile unsigned int *)0xb2100004 = ost_regs->oster;
++
++	*(volatile unsigned int *)0xb2000000 = ost_regs->g_ostccr;
++	*(volatile unsigned int *)0xb2000008 = ost_regs->g_ostcr;
++	*(volatile unsigned int *)0xb2000004 = ost_regs->g_oster;
++
++}
++
++static void cpm_save(struct cpm_regs *cpm_regs)
++{
++	cpm_regs->cpm_sftint = *(volatile unsigned int *)0xb00000bc;
++	cpm_regs->cpsppr = *(volatile unsigned int *)0xb0000038;
++	cpm_regs->cpspr = *(volatile unsigned int *)0xb0000034;
++	cpm_regs->lcr = *(volatile unsigned int *)0xb0000004;
++	cpm_regs->pswc0st = *(volatile unsigned int *)0xb0000090;
++	cpm_regs->pswc1st = *(volatile unsigned int *)0xb0000094;
++	cpm_regs->pswc2st = *(volatile unsigned int *)0xb0000098;
++	cpm_regs->pswc3st = *(volatile unsigned int *)0xb000009c;
++	cpm_regs->clkgr0 = *(volatile unsigned int*)0xb0000020;
++	cpm_regs->clkgr1 = *(volatile unsigned int*)0xb0000028;
++	cpm_regs->mestsel = *(volatile unsigned int*)0xb00000ec;
++	cpm_regs->srbc = *(volatile unsigned int*)0xb00000c4;
++	cpm_regs->exclk_ds = *(volatile unsigned int*)0xb00000e0;
++	cpm_regs->memory_pd0 = *(volatile unsigned int*)0xb00000f8;
++	cpm_regs->memory_pd1 = *(volatile unsigned int*)0xb00000fc;
++	cpm_regs->slbc = *(volatile unsigned int*)0xb00000c8;
++	cpm_regs->slpc = *(volatile unsigned int*)0xb00000cc;
++	cpm_regs->opcr = *(volatile unsigned int*)0xb0000024;
++	cpm_regs->rsr = *(volatile unsigned int*)0xb0000008;
++
++}
++
++static void cpm_restore(struct cpm_regs *cpm_regs)
++{
++	*(volatile unsigned int *)0xb0000020 = 0;
++	*(volatile unsigned int *)0xb0000028 = 0;
++	*(volatile unsigned int *)0xb00000bc = cpm_regs->cpm_sftint;
++	*(volatile unsigned int *)0xb0000038 = cpm_regs->cpsppr;
++	*(volatile unsigned int *)0xb0000034 = cpm_regs->cpspr;
++	*(volatile unsigned int *)0xb0000004 = cpm_regs->lcr;
++	*(volatile unsigned int *)0xb0000090 = cpm_regs->pswc0st;
++	*(volatile unsigned int *)0xb0000094 = cpm_regs->pswc1st;
++	*(volatile unsigned int *)0xb0000098 = cpm_regs->pswc2st;
++	*(volatile unsigned int *)0xb000009c = cpm_regs->pswc3st;
++	*(volatile unsigned int *)0xb00000ec = cpm_regs->mestsel;
++	*(volatile unsigned int *)0xb00000c4 = cpm_regs->srbc;
++	*(volatile unsigned int *)0xb00000e0 = cpm_regs->exclk_ds;
++	*(volatile unsigned int *)0xb00000f8 = cpm_regs->memory_pd0;
++	*(volatile unsigned int *)0xb00000fc = cpm_regs->memory_pd1;
++	*(volatile unsigned int *)0xb00000c8 = cpm_regs->slbc;
++	*(volatile unsigned int *)0xb00000cc = cpm_regs->slpc;
++	*(volatile unsigned int *)0xb0000024 = cpm_regs->opcr;
++	*(volatile unsigned int *)0xb0000008 = cpm_regs->rsr;
++	*(volatile unsigned int *)0xb0000020 = cpm_regs->clkgr0;
++	*(volatile unsigned int *)0xb0000028 = cpm_regs->clkgr1;
++
++}
++
++static void ccu_save(struct ccu_regs *ccu_regs)
++{
++	ccu_regs->mscr = *(volatile unsigned int *)0xb2200060;
++	ccu_regs->pimr = *(volatile unsigned int *)0xb2200120;
++	ccu_regs->mimr = *(volatile unsigned int *)0xb2200160;
++	ccu_regs->oimr = *(volatile unsigned int *)0xb22001a0;
++	ccu_regs->dipr = *(volatile unsigned int *)0xb22001c0;
++	ccu_regs->gdimr = *(volatile unsigned int *)0xb22001e0;
++	ccu_regs->ldimr0 = *(volatile unsigned int *)0xb2200300;
++	ccu_regs->ldimr1 = *(volatile unsigned int *)0xb2200332;
++	ccu_regs->rer = *(volatile unsigned int *)0xb2200f00;
++	ccu_regs->mbr0 = *(volatile unsigned int *)0xb2201000;
++	ccu_regs->mbr1 = *(volatile unsigned int *)0xb2201004;
++	ccu_regs->cslr0 = *(volatile unsigned int *)0xb2200f10;
++	ccu_regs->cslr1 = *(volatile unsigned int *)0xb2200f18;
++	ccu_regs->csar0 = *(volatile unsigned int *)0xb2200f14;
++	ccu_regs->csar1 = *(volatile unsigned int *)0xb2200f1c;
++
++}
++
++static void ccu_restore(struct ccu_regs *ccu_regs)
++{
++	*(volatile unsigned int *)0xb2200060 = ccu_regs->mscr;
++	*(volatile unsigned int *)0xb2200120 = ccu_regs->pimr;
++	*(volatile unsigned int *)0xb2200160 = ccu_regs->mimr;
++	*(volatile unsigned int *)0xb22001a0 = ccu_regs->oimr;
++	*(volatile unsigned int *)0xb22001c0 = ccu_regs->dipr;
++	*(volatile unsigned int *)0xb22001e0 = ccu_regs->gdimr;
++	*(volatile unsigned int *)0xb2200300 = ccu_regs->ldimr0;
++	*(volatile unsigned int *)0xb2200332 = ccu_regs->ldimr1;
++	*(volatile unsigned int *)0xb2200f00 = ccu_regs->rer;
++	*(volatile unsigned int *)0xb2201000 = ccu_regs->mbr0;
++	*(volatile unsigned int *)0xb2201004 = ccu_regs->mbr1;
++	*(volatile unsigned int *)0xb2200f10 = ccu_regs->cslr0;
++	*(volatile unsigned int *)0xb2200f18 = ccu_regs->cslr1;
++	*(volatile unsigned int *)0xb2200f14 = ccu_regs->csar0;
++	*(volatile unsigned int *)0xb2200f1c = ccu_regs->csar1;
++
++}
++
++
++
++
++
++struct uart_regs *uart_regs;
++struct ost_regs *ost_regs;
++struct cpm_regs *cpm_regs;
++struct ccu_regs *ccu_regs;
++
++void sys_save(void)
++{
++	uart_regs = kmalloc(sizeof(struct uart_regs), GFP_KERNEL);
++	ost_regs = kmalloc(sizeof(struct ost_regs), GFP_KERNEL);
++	cpm_regs = kmalloc(sizeof(struct cpm_regs), GFP_KERNEL);
++	ccu_regs = kmalloc(sizeof(struct ccu_regs), GFP_KERNEL);
++
++	ost_save(ost_regs);
++	cpm_save(cpm_regs);
++	ccu_save(ccu_regs);
++}
++
++void sys_restore(void)
++{
++	ost_restore(ost_regs);
++	cpm_restore(cpm_regs);
++	ccu_restore(ccu_regs);
++
++
++	kfree(uart_regs);
++	kfree(ost_regs);
++}
++
++
++
++
++
++
++static struct store_regs *store_regs;
++
++static void save_resume_pc(void)
++{
++
++	store_regs = (struct store_regs *)FASTBOOT_DATA_ADDR;
++	store_regs->resume_pc = (unsigned int)fastboot_cpu_resume;
++	printk("xxxxxxxxxxxxxxxxxxx save resume_pc = 0x%08x\n", store_regs->resume_pc);
++}
++
++static void save_uart_index(void)
++{
++	store_regs = (struct store_regs *)FASTBOOT_DATA_ADDR;
++	store_regs->uart_index = bc_idx;
++	printk("xxxxxxxxxxxxxxxxxxx save uart_index = %d\n", store_regs->uart_index);
++}
++
++static void pll_store(void)
++{
++	struct pll_resume_reg *pll_resume_reg;
++
++	store_regs = (struct store_regs *)FASTBOOT_DATA_ADDR;
++	pll_resume_reg = &store_regs->pll_resume_reg;
++
++	pll_resume_reg->cpccr = *(volatile unsigned int *)0xb0000000;
++	pll_resume_reg->cppcr = *(volatile unsigned int *)0xb000000c;
++	pll_resume_reg->cpapcr = *(volatile unsigned int *)0xb0000010;
++	pll_resume_reg->cpmpcr = *(volatile unsigned int *)0xb0000014;
++	pll_resume_reg->cpepcr = *(volatile unsigned int *)0xb0000018;
++	pll_resume_reg->ddrcdr = *(volatile unsigned int *)0xb000002c;
++
++}
++
++static void ddrc_store(void)
++{
++	struct ddrc_resume_reg *ddrc_resume_reg;
++
++	store_regs = (struct store_regs *)FASTBOOT_DATA_ADDR;
++	ddrc_resume_reg = &store_regs->ddrc_resume_reg;
++
++	ddrc_resume_reg->dcfg = *(volatile unsigned int *)0xb34f0008;
++	ddrc_resume_reg->dctrl = *(volatile unsigned int *)0xb34f0010;
++	ddrc_resume_reg->dlmr = *(volatile unsigned int *)0xb34f0018;
++	ddrc_resume_reg->ddlp = *(volatile unsigned int *)0xb34f0020;
++	ddrc_resume_reg->dasr_en = *(volatile unsigned int *)0xb34f0030;
++	ddrc_resume_reg->dasr_cnt = *(volatile unsigned int *)0xb34f0028;
++	ddrc_resume_reg->drefcnt = *(volatile unsigned int *)0xb34f0038;
++	ddrc_resume_reg->dtimming1 = *(volatile unsigned int *)0xb34f0040;
++	ddrc_resume_reg->dtimming2 = *(volatile unsigned int *)0xb34f0048;
++	ddrc_resume_reg->dtimming3 = *(volatile unsigned int *)0xb34f0050;
++	ddrc_resume_reg->dtimming4 = *(volatile unsigned int *)0xb34f0058;
++	ddrc_resume_reg->dtimming5 = *(volatile unsigned int *)0xb34f0060;
++	ddrc_resume_reg->dmmap0 = *(volatile unsigned int *)0xb34f0078;
++	ddrc_resume_reg->dmmap1 = *(volatile unsigned int *)0xb34f0080;
++
++	ddrc_resume_reg->dbwcfg = *(volatile unsigned int *)0xb34f0088;
++	ddrc_resume_reg->dbwstp = *(volatile unsigned int *)0xb34f0090;
++	ddrc_resume_reg->hregpro = *(volatile unsigned int *)0xb34f00d8;
++	ddrc_resume_reg->dbgen = *(volatile unsigned int *)0xb34f00e0;
++
++	ddrc_resume_reg->dwcfg = *(volatile unsigned int *)0xb3012000;
++	ddrc_resume_reg->dremap1 = *(volatile unsigned int *)0xb3012008;
++	ddrc_resume_reg->dremap2 = *(volatile unsigned int *)0xb301200c;
++	ddrc_resume_reg->dremap3 = *(volatile unsigned int *)0xb3012010;
++	ddrc_resume_reg->dremap4 = *(volatile unsigned int *)0xb3012014;
++	ddrc_resume_reg->dremap5 = *(volatile unsigned int *)0xb3012018;
++
++	ddrc_resume_reg->cpac = *(volatile unsigned int *)0xb301201c;
++	ddrc_resume_reg->cchc0 = *(volatile unsigned int *)0xb3012020;
++	ddrc_resume_reg->cchc1 = *(volatile unsigned int *)0xb3012024;
++	ddrc_resume_reg->cchc2 = *(volatile unsigned int *)0xb3012028;
++	ddrc_resume_reg->cchc3 = *(volatile unsigned int *)0xb301202c;
++	ddrc_resume_reg->cchc4 = *(volatile unsigned int *)0xb3012030;
++	ddrc_resume_reg->cchc5 = *(volatile unsigned int *)0xb3012034;
++	ddrc_resume_reg->cchc6 = *(volatile unsigned int *)0xb3012038;
++	ddrc_resume_reg->cchc7 = *(volatile unsigned int *)0xb301203c;
++	ddrc_resume_reg->cschc0 = *(volatile unsigned int *)0xb3012040;
++	ddrc_resume_reg->cschc1 = *(volatile unsigned int *)0xb3012044;
++	ddrc_resume_reg->cschc2 = *(volatile unsigned int *)0xb3012048;
++	ddrc_resume_reg->cschc3 = *(volatile unsigned int *)0xb301204c;
++	ddrc_resume_reg->cmonc0 = *(volatile unsigned int *)0xb3012050;
++	ddrc_resume_reg->cmonc1 = *(volatile unsigned int *)0xb3012054;
++	ddrc_resume_reg->cmonc2 = *(volatile unsigned int *)0xb3012058;
++	ddrc_resume_reg->cmonc3 = *(volatile unsigned int *)0xb301205c;
++	ddrc_resume_reg->cmonc4 = *(volatile unsigned int *)0xb3012060;
++
++	ddrc_resume_reg->ccguc0 = *(volatile unsigned int *)0xb3012064;
++	ddrc_resume_reg->ccguc1 = *(volatile unsigned int *)0xb3012068;
++
++	ddrc_resume_reg->pregpro = *(volatile unsigned int *)0xb301206c;
++	ddrc_resume_reg->bufcfg = *(volatile unsigned int *)0xb3012070;
++}
++
++static void ddr_phy_store(void)
++{
++	struct ddr_phy_resume_reg *ddr_phy_resume_reg;
++
++	store_regs = (struct store_regs *)FASTBOOT_DATA_ADDR;
++	ddr_phy_resume_reg = &store_regs->ddr_phy_resume_reg;
++
++	ddr_phy_resume_reg->mem_cfg = *(volatile unsigned int *)0xb3011004;
++	ddr_phy_resume_reg->dq_width = *(volatile unsigned int *)0xb301107c;
++	ddr_phy_resume_reg->cl = *(volatile unsigned int *)0xb3011014;
++	ddr_phy_resume_reg->al = *(volatile unsigned int *)0xb3011018;
++	ddr_phy_resume_reg->cwl = *(volatile unsigned int *)0xb301101c;
++	ddr_phy_resume_reg->pll_fbdiv = *(volatile unsigned int *)0xb3011080;
++	ddr_phy_resume_reg->pll_ctrl = *(volatile unsigned int *)0xb3011084;
++	ddr_phy_resume_reg->pll_pdiv = *(volatile unsigned int *)0xb3011088;
++	ddr_phy_resume_reg->training_ctrl = *(volatile unsigned int *)0xb3011008;
++	ddr_phy_resume_reg->calib_bypass_al = *(volatile unsigned int *)0xb3011118;
++	ddr_phy_resume_reg->calib_bypass_ah = *(volatile unsigned int *)0xb3011158;
++	ddr_phy_resume_reg->wl_mode1 = *(volatile unsigned int *)0xb301100c;
++	ddr_phy_resume_reg->wl_mode2 = *(volatile unsigned int *)0xb3011010;
++}
++
++static void rtc_ram_store(void)
++{
++	pll_store();
++	ddrc_store();
++	ddr_phy_store();
++	save_resume_pc();
++	save_uart_index();
++}
++
++
++void load_func_to_rtc_ram(void)
++{
++
++	load_func_to_tcsm((unsigned int *)FASTBOOT_SLEEP_CODE_ADDR, (unsigned int *)fastboot_cpu_sleep, FASTBOOT_SLEEP_CODE_LEN);
++
++	rtc_ram_write_enable();
++	memset((unsigned int *)RTC_MEMORY_START, 0, 4096);
++	rtc_ram_store();
++	memcpy((unsigned int *)FASTBOOT_RESUME_CODE1_ADDR, (unsigned int *)fastboot_resume_code, FASTBOOT_RESUME_CODE_LEN);
++	rtc_ram_write_disable();
++}
++
++
++
++
++
++static noinline void fastboot_cpu_resume(void)
++{
++
++
++	*(volatile unsigned int *)0xb2200f00 = 0xbfc00000; /* RESET entry = 0xbfc00000 ,reset value */
++
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"jr.hb %0	\n\t"
++		"nop		\n\t"
++		".set pop 	\n\t"
++		:
++		: "r" (restore_goto)
++		:
++		);
++}
++
++
++static noinline void fastboot_cpu_sleep(void)
++{
++
++
++	unsigned int tmp;
++	unsigned int ddrc_ctrl;
++
++	blast_dcache32();
++	blast_scache64();
++	__sync();
++	__fast_iob();
++
++	ddr_writel(0, DDRC_AUTOSR_EN);
++	tmp = *(volatile unsigned int *)0xa0000000;
++
++
++	/* DDR self refresh */
++	ddrc_ctrl = ddr_readl(DDRC_CTRL);
++	ddrc_ctrl |= 1 << 5;
++	ddr_writel(ddrc_ctrl, DDRC_CTRL);
++	while(!(ddr_readl(DDRC_STATUS) & (1<<2)));
++
++	/* bufferen_core = 0 */
++	tmp = rtc_read_reg(0xb0003048);
++	tmp &= ~(1 << 21);
++	rtc_write_reg(0xb0003048, tmp);
++
++	/* dfi_init_start = 1 */
++	*(volatile unsigned int *)0xb3012000 |= (1 << 3);
++
++
++	{
++		int i;
++		for (i = 0; i < 4; i++) {
++
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++		}
++	}
++	/* ddr phy pll power down */
++	*(volatile unsigned int *)0xb3011084 |= (1 << 1);
++
++
++	TCSM_PCHAR('W');
++
++
++	/* rtc disable power detect */
++	rtc_write_reg(0xb000302c, (0x1a55a5a5 << 3) | 1);
++	/* RTC PD */
++	rtc_write_reg(0xb0003020, 1);
++
++
++	while (1);
++}
++
++
++void soc_pm_fastboot_config(void)
++{
++
++	unsigned int tmp;
++	unsigned int intc1_msk;
++	unsigned int clk_gate0;
++
++	clk_gate0 = cpm_inl(CPM_CLKGR);
++
++	clk_gate0 &= ~(1 << 27); //enable rtc
++
++	cpm_outl(clk_gate0, CPM_CLKGR);
++
++
++	intc1_msk = *(volatile unsigned int *)0xb0001024;
++	*(volatile unsigned int *)0xb0001024 = intc1_msk & ~(1<<0); // RTC INT MSK
++
++	/* RTC EALM */
++	tmp = rtc_read_reg(0xb000302c);
++	tmp |= 1;
++	rtc_write_reg(0xb000302c, tmp);
++
++	/* RTC enable AE */
++	tmp = rtc_read_reg(0xb0003000);
++	tmp |= (1 << 2) | (1 << 0);
++	rtc_write_reg(0xb0003000, tmp);
++
++	/* 32k rtc clk */
++	tmp = rtc_read_reg(0xb0003000);
++	tmp &= ~(1 << 1);
++	rtc_write_reg(0xb0003000, tmp);
++
++	rtc_write_reg(0xb0003028, 0);
++	rtc_write_reg(0xb0003024, 0);
++}
++
++
++
++static int soc_pm_wakeup_fastboot_config(void)
++{
++
++	return 0;
++}
++
++void soc_pm_wakeup_fastboot(void)
++{
++
++	soc_pm_wakeup_fastboot_config();
++
++	sys_restore();
++
++}
++
++
++
++
++
++
++
++
++
+diff --git a/arch/mips/xburst2/soc-m300/pm_fastboot.h b/arch/mips/xburst2/soc-m300/pm_fastboot.h
+new file mode 100644
+index 000000000..7c9a4682d
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/pm_fastboot.h
+@@ -0,0 +1,172 @@
++#ifndef __PM_FASTBOOT_H__
++#define __PM_FASTBOOT_H__
++
++struct pll_resume_reg {
++	unsigned int cpccr;
++	unsigned int cppcr;
++	unsigned int cpapcr;
++	unsigned int cpmpcr;
++	unsigned int cpepcr;
++	unsigned int ddrcdr;
++};
++
++struct ddrc_resume_reg {
++	unsigned int dcfg;
++	unsigned int dctrl;
++	unsigned int dlmr;
++	unsigned int ddlp;
++	unsigned int dasr_en;
++	unsigned int dasr_cnt;
++	unsigned int drefcnt;
++	unsigned int dtimming1;
++	unsigned int dtimming2;
++	unsigned int dtimming3;
++	unsigned int dtimming4;
++	unsigned int dtimming5;
++	unsigned int dmmap0;
++	unsigned int dmmap1;
++	unsigned int dbwcfg;
++	unsigned int dbwstp;
++	unsigned int hregpro;
++	unsigned int dbgen;
++	unsigned int dwcfg;
++	unsigned int dremap1;
++	unsigned int dremap2;
++	unsigned int dremap3;
++	unsigned int dremap4;
++	unsigned int dremap5;
++	unsigned int cpac;
++	unsigned int cchc0;
++	unsigned int cchc1;
++	unsigned int cchc2;
++	unsigned int cchc3;
++	unsigned int cchc4;
++	unsigned int cchc5;
++	unsigned int cchc6;
++	unsigned int cchc7;
++	unsigned int cschc0;
++	unsigned int cschc1;
++	unsigned int cschc2;
++	unsigned int cschc3;
++	unsigned int cmonc0;
++	unsigned int cmonc1;
++	unsigned int cmonc2;
++	unsigned int cmonc3;
++	unsigned int cmonc4;
++	unsigned int ccguc0;
++	unsigned int ccguc1;
++	unsigned int pregpro;
++	unsigned int bufcfg;
++};
++
++struct ddr_phy_resume_reg {
++	unsigned int phy_rst;
++	unsigned int mem_cfg;
++	unsigned int dq_width;
++	unsigned int cl;
++	unsigned int al;
++	unsigned int cwl;
++	unsigned int pll_fbdiv;
++	unsigned int pll_ctrl;
++	unsigned int pll_pdiv;
++	unsigned int training_ctrl;
++	unsigned int calib_bypass_al;
++	unsigned int calib_bypass_ah;
++	unsigned int wl_mode1;
++	unsigned int wl_mode2;
++
++};
++
++struct store_regs {
++	unsigned int resume_pc;
++	unsigned int uart_index;
++	struct pll_resume_reg pll_resume_reg;
++	struct ddrc_resume_reg ddrc_resume_reg;
++	struct ddr_phy_resume_reg ddr_phy_resume_reg;
++};
++
++
++
++struct uart_regs {
++	unsigned int udllr;
++	unsigned int udlhr;
++	unsigned int uthr;
++	unsigned int uier;
++	unsigned int ufcr;
++	unsigned int ulcr;
++	unsigned int umcr;
++	unsigned int uspr;
++	unsigned int isr;
++	unsigned int umr;
++	unsigned int uacr;
++	unsigned int urcr;
++	unsigned int utcr;
++
++};
++
++
++struct ost_regs {
++	unsigned int ostccr;
++	unsigned int oster;
++	unsigned int ostcr;
++	unsigned int ostfr;
++	unsigned int ostmr;
++	unsigned int ostdfr;
++	unsigned int ostcnt;
++
++	unsigned int g_ostccr;
++	unsigned int g_oster;
++	unsigned int g_ostcr;
++	unsigned int g_ostcnth;
++	unsigned int g_ostcntl;
++	unsigned int g_ostcntb;
++};
++
++struct cpm_regs {
++	unsigned int cpm_sftint;
++	unsigned int cpsppr;
++	unsigned int cpspr;
++	unsigned int lcr;
++	unsigned int pswc0st;
++	unsigned int pswc1st;
++	unsigned int pswc2st;
++	unsigned int pswc3st;
++	unsigned int clkgr0;
++	unsigned int clkgr1;
++	unsigned int mestsel;
++	unsigned int srbc;
++	unsigned int exclk_ds;
++	unsigned int memory_pd0;
++	unsigned int memory_pd1;
++	unsigned int slbc;
++	unsigned int slpc;
++	unsigned int opcr;
++	unsigned int rsr;
++};
++
++struct ccu_regs {
++	unsigned int mscr;
++	unsigned int pimr;
++	unsigned int mimr;
++	unsigned int oimr;
++	unsigned int dipr;
++	unsigned int gdimr;
++	unsigned int ldimr0;
++	unsigned int ldimr1;
++	unsigned int rer;
++	unsigned int mbr0;
++	unsigned int mbr1;
++	unsigned int cslr0;
++	unsigned int cslr1;
++	unsigned int csar0;
++	unsigned int csar1;
++};
++
++
++void load_func_to_rtc_ram(void);
++void soc_pm_fastboot_config(void);
++void soc_pm_wakeup_fastboot(void);
++void sys_save(void);
++void sys_restore(void);
++
++#endif
+diff --git a/arch/mips/xburst2/soc-m300/pm_sleep.c b/arch/mips/xburst2/soc-m300/pm_sleep.c
+new file mode 100644
+index 000000000..ca7cbbfa3
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/pm_sleep.c
+@@ -0,0 +1,357 @@
++#include <linux/init.h>
++#include <linux/pm.h>
++#include <linux/suspend.h>
++
++#include <soc/cache.h>
++#include <soc/base.h>
++#include <asm/io.h>
++#include <soc/ddr.h>
++#include <soc/base.h>
++#include <soc/cpm.h>
++#include "pm.h"
++#include "pm_sleep.h"
++
++
++
++static inline void ddrp_auto_calibration(void)
++{
++	unsigned int reg_val = ddr_readl(DDRP_INNOPHY_TRAINING_CTRL);
++	unsigned int timeout = 0xffffff;
++	unsigned int wait_cal_done = DDRP_CALIB_DONE_HDQCFA | DDRP_CALIB_DONE_LDQCFA;
++
++	reg_val &= ~(DDRP_TRAINING_CTRL_DSCSE_BP);
++	reg_val |= DDRP_TRAINING_CTRL_DSACE_START;
++	ddr_writel(reg_val, DDRP_INNOPHY_TRAINING_CTRL);
++
++	while(!((ddr_readl(DDRP_INNOPHY_CALIB_DONE) & wait_cal_done) == wait_cal_done) && --timeout) {
++		TCSM_PCHAR('t');
++	}
++
++	if(!timeout) {
++		TCSM_PCHAR('f');
++	}
++	ddr_writel(0, DDRP_INNOPHY_TRAINING_CTRL);
++}
++
++int soc_pm_idle_config(void)
++{
++	unsigned int lcr = cpm_inl(CPM_LCR);
++	unsigned int opcr = cpm_inl(CPM_OPCR);
++
++	lcr &=~ 0x3; // low power mode: IDLE
++	cpm_outl(lcr, CPM_LCR);
++
++	opcr &= ~(1 << 30);
++	opcr &= ~(1 << 31);
++	cpm_outl(opcr, CPM_OPCR);
++
++	return 0;
++}
++
++int soc_pm_idle_pd_config(void)
++{
++	unsigned int lcr = cpm_inl(CPM_LCR);
++	unsigned int opcr = cpm_inl(CPM_OPCR);
++
++	lcr &=~ 0x3; // low power mode: IDLE
++	lcr |= 2;
++	cpm_outl(lcr, CPM_LCR);
++
++	opcr &= ~ (1<<31);
++	opcr |= (1 << 30);
++	opcr &= ~(1 << 26);	//l2c power down
++	opcr |= 1 << 2; // select RTC clk
++	cpm_outl(opcr, CPM_OPCR);
++
++	return 0;
++}
++
++int soc_pm_sleep_config(void)
++{
++	unsigned int lcr = cpm_inl(CPM_LCR);
++	unsigned int opcr = cpm_inl(CPM_OPCR);
++
++	lcr &=~ 0x3;
++	lcr |= 1 << 0; // low power mode: SLEEP
++	cpm_outl(lcr, CPM_LCR);
++
++	opcr &= ~(1 << 31);
++	opcr |= (1 << 30);
++	opcr &= ~(1 << 26); //L2C power down
++	opcr |= (1 << 21); // cpu 32k ram retention.
++	opcr |= (1 << 3); // power down CPU
++	opcr &= ~(1 << 4); // exclk disable;
++	opcr |= (1 << 2); // select RTC clk
++	opcr |= (1 << 22);
++	opcr |= (1 << 20);
++	cpm_outl(opcr, CPM_OPCR);
++
++	return 0;
++}
++
++int soc_pm_wakeup_idle_sleep(void)
++{
++	unsigned int lcr = cpm_inl(CPM_LCR);
++	lcr &= ~0x3; // low power mode: IDLE
++	cpm_outl(lcr, CPM_LCR);
++
++	printk("post wakeup!\n");
++
++
++	{
++		/* after power down cpu by set PD in OPCR, resume cpu's frequency and L2C's freq */
++		unsigned int val;
++
++		/* change disable */
++		val = cpm_inl(CPM_CPCCR);
++		val &= ~(1 << 22);
++		cpm_outl(val, CPM_CPCCR);
++
++		/* resume cpu_div in CPCCR */
++		val &= ~0xf;
++		val |= sleep_param->cpu_div;
++		cpm_outl(val, CPM_CPCCR);
++
++		/* change enable */
++		val |= (1 << 22);
++		cpm_outl(val, CPM_CPCCR);
++
++		while (cpm_inl(CPM_CPCSR) & 1);
++	}
++	return 0;
++}
++
++void soc_set_reset_entry(void)
++{
++	*(volatile unsigned int *)0xb2200f00 = NORMAL_RESUME_CODE1_ADDR;
++
++}
++
++
++static noinline void cpu_resume_bootup(void)
++{
++	TCSM_PCHAR('X');
++	/* set reset entry */
++	*(volatile unsigned int *)0xb2200f00 = 0xbfc00000;
++
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"move $29, %0	\n\t"
++		"jr.hb   %1	\n\t"
++		"nop		\n\t"
++		".set pop	\n\t"
++		:
++		:"r" (NORMAL_RESUME_SP), "r"(NORMAL_RESUME_CODE2_ADDR)
++		:
++		);
++
++}
++static noinline void cpu_resume(void)
++{
++	unsigned int ddrc_ctrl;
++
++	TCSM_PCHAR('R');
++
++	if (sleep_param->state == PM_SUSPEND_MEM) {
++		int tmp;
++
++		/* enable pll */
++		tmp = reg_ddr_phy(0x21);
++		tmp &= ~(1 << 1);
++		reg_ddr_phy(0x21) = tmp;
++
++		while (!(reg_ddr_phy(0x32) & 0x8))
++			serial_put_hex(reg_ddr_phy(0x32));
++
++		/* dfi_init_start = 0, wait dfi_init_complete */
++		*(volatile unsigned int *)0xb3012000 &= ~(1 << 3);
++		while(!(*(volatile unsigned int *)0xb3012004 & 0x1));
++
++		/* bufferen_core = 1 */
++		tmp = rtc_read_reg(0xb0003048);
++		tmp |= (1 << 21);
++		rtc_write_reg(0xb0003048, tmp);
++
++		/* exit sr */
++		ddrc_ctrl = ddr_readl(DDRC_CTRL);
++		ddrc_ctrl &= ~(1<<5);
++		ddr_writel(ddrc_ctrl, DDRC_CTRL);
++
++		while(ddr_readl(DDRC_STATUS) & (1<<2));
++
++		TCSM_DELAY(1000);
++		TCSM_PCHAR('1');
++		ddrp_auto_calibration();
++		TCSM_PCHAR('2');
++
++		/* restore ddr auto-sr */
++		ddr_writel(sleep_param->autorefresh, DDRC_AUTOSR_EN);
++		TCSM_PCHAR('3');
++
++		/* restore ddr LPEN */
++		ddr_writel(sleep_param->dlp, DDRC_DLP);
++
++		/* restore ddr deep power down state */
++		ddrc_ctrl = ddr_readl(DDRC_CTRL);
++		ddrc_ctrl |= sleep_param->pdt;
++		ddrc_ctrl |= sleep_param->dpd;
++		ddr_writel(ddrc_ctrl, DDRC_CTRL);
++
++		TCSM_PCHAR('4');
++	}
++
++
++	TCSM_PCHAR('5');
++
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"jr.hb %0	\n\t"
++		"nop		\n\t"
++		".set pop 	\n\t"
++		:
++		: "r" (restore_goto)
++		:
++		);
++}
++
++
++static noinline void cpu_sleep(void)
++{
++
++
++	sleep_param->cpu_div = cpm_inl(CPM_CPCCR) & 0xf;
++
++	blast_dcache32();
++	blast_scache64();
++	__sync();
++	__fast_iob();
++
++	{
++		/* before power down cpu by set PD in OPCR, reduce cpu's frequency as the same as L2C's freq */
++		unsigned int val, div;
++
++		/* change disable */
++		val = cpm_inl(CPM_CPCCR);
++		val &= ~(1 << 22);
++		cpm_outl(val, CPM_CPCCR);
++
++		/* div cpu = div l2c */
++		div = val & (0xf << 4);
++		val &= ~0xf;
++		val |= (div >> 4);
++		cpm_outl(val, CPM_CPCCR);
++
++		/* change enable */
++		val |= (1 << 22);
++		cpm_outl(val, CPM_CPCCR);
++
++		while (cpm_inl(CPM_CPCSR) & 1);
++	}
++
++	TCSM_PCHAR('D');
++
++	if (sleep_param->state == PM_SUSPEND_MEM) {
++		unsigned int tmp;
++		unsigned int ddrc_ctrl;
++
++		ddrc_ctrl = ddr_readl(DDRC_CTRL);
++
++		/* save ddr low power state */
++		sleep_param->pdt = ddrc_ctrl & DDRC_CTRL_PDT_MASK;
++		sleep_param->dpd = ddrc_ctrl & DDRC_CTRL_DPD;
++		sleep_param->dlp = ddr_readl(DDRC_DLP);
++		sleep_param->autorefresh = ddr_readl(DDRC_AUTOSR_EN);
++
++		/* ddr disable deep power down */
++		ddrc_ctrl &= ~(DDRC_CTRL_PDT_MASK);
++		ddrc_ctrl &= ~(DDRC_CTRL_DPD);
++		ddr_writel(ddrc_ctrl, DDRC_CTRL);
++
++		/* ddr diasble LPEN*/
++		ddr_writel(0, DDRC_DLP);
++
++		/* ddr disable auto-sr */
++		ddr_writel(0, DDRC_AUTOSR_EN);
++		tmp = *(volatile unsigned int *)0xa0000000;
++
++		/* DDR self refresh */
++		ddrc_ctrl = ddr_readl(DDRC_CTRL);
++		ddrc_ctrl |= 1 << 5;
++		ddr_writel(ddrc_ctrl, DDRC_CTRL);
++		while(!(ddr_readl(DDRC_STATUS) & (1<<2)));
++
++
++		/* bufferen_core = 0 */
++		tmp = rtc_read_reg(0xb0003048);
++		tmp &= ~(1 << 21);
++		rtc_write_reg(0xb0003048, tmp);
++
++
++		/* dfi_init_start = 1 */
++		*(volatile unsigned int *)0xb3012000 |= (1 << 3);
++
++		{
++			int i;
++			for (i = 0; i < 4; i++) {
++
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++			}
++		}
++
++		/* disable pll */
++		reg_ddr_phy(0x21) |= (1 << 1);
++	}
++
++	TCSM_PCHAR('W');
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"wait		\n\t"
++		"nop		\n\t"
++		"nop		\n\t"
++		"nop		\n\t"
++		".set pop	\n\t"
++	);
++
++	TCSM_PCHAR('N');
++
++	TCSM_PCHAR('\r');
++	TCSM_PCHAR('\n');
++	TCSM_PCHAR('?');
++	TCSM_PCHAR('?');
++	TCSM_PCHAR('?');
++	TCSM_PCHAR('\r');
++	TCSM_PCHAR('\n');
++
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"jr.hb %0	\n\t"
++		"nop		\n\t"
++		".set pop 	\n\t"
++		:
++		: "r" (NORMAL_RESUME_CODE1_ADDR)
++		:
++		);
++	TCSM_PCHAR('F');
++}
++
++
++void load_func_to_sram(void)
++{
++	load_func_to_tcsm((unsigned int *)NORMAL_RESUME_CODE1_ADDR, (unsigned int *)cpu_resume_bootup, NORMAL_RESUME_CODE1_LEN);
++	load_func_to_tcsm((unsigned int *)NORMAL_RESUME_CODE2_ADDR, (unsigned int *)cpu_resume, NORMAL_RESUME_CODE2_LEN);
++	load_func_to_tcsm((unsigned int *)NORMAL_SLEEP_CODE_ADDR, (unsigned int *)cpu_sleep, NORMAL_SLEEP_CODE_LEN);
++}
++
++
++
+diff --git a/arch/mips/xburst2/soc-m300/pm_sleep.h b/arch/mips/xburst2/soc-m300/pm_sleep.h
+new file mode 100644
+index 000000000..01eb77aed
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/pm_sleep.h
+@@ -0,0 +1,16 @@
++#ifndef __PM_SLEEP_H__
++#define __PM_SLEEP_H__
++
++
++
++void load_func_to_sram(void);
++int soc_pm_idle_pd_config(void);
++int soc_pm_idle_config(void);
++int soc_pm_sleep_config(void);
++int soc_pm_wakeup_idle_sleep(void);
++void soc_set_reset_entry(void);
++
++
++
++#endif
++
+diff --git a/arch/mips/xburst2/soc-m300/regs_save_restore.S b/arch/mips/xburst2/soc-m300/regs_save_restore.S
+new file mode 100644
+index 000000000..abe8b49df
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/regs_save_restore.S
+@@ -0,0 +1,190 @@
++#include <asm/asm.h>
++#include <asm/regdef.h>
++
++#define CP0_PAGEMASK	$5,0
++#define CP0_STATUS	$12,0
++#define CP0_INTCTL	$12,1
++#define CP0_CAUSE	$13,0
++#define CP0_EBASE	$15,1
++#define CP0_CONFIG	$16,0
++#define CP0_CONFIG1	$16,1
++#define CP0_CONFIG2	$16,2
++#define CP0_CONFIG3	$16,3
++#define CP0_CONFIG4	$16,4
++#define CP0_CONFIG5	$16,5
++#define CP0_CONFIG7	$16,7
++#define CP0_LLADDR	$17,0
++#define CP0_WATCHLo	$18,0
++#define CP0_WATCHHI	$19,0
++#define CP0_ERRCTL	$26,0
++#define CP0_CONTEXT	$4,0
++#define CP0_KSCRATCH1	$31,2
++#define CP0_KSCRATCH2	$31,3
++#define CP0_KSCRATCH3	$31,4
++#define CP0_KSCRATCH4	$31,5
++#define CP0_KSCRATCH5	$31,6
++#define CP0_KSCRATCH6	$31,7
++
++	.data
++	.global _regs_stack
++_regs_stack:
++	.align 5
++	.space 140,0
++
++	.text
++	.global save_goto
++	.align 2
++	.ent save_goto,0
++	LEAF(save_goto)
++save_goto:
++	.set	push
++	.set	noreorder
++	.set	noat
++
++	la	k0, _regs_stack
++	sw	s0,0(k0)
++	sw	s1,4(k0)
++	sw	s2,8(k0)
++	sw	s3,12(k0)
++	sw	s4,16(k0)
++	sw	s5,20(k0)
++	sw	s6,24(k0)
++	sw	s7,28(k0)
++	sw	gp,32(k0)
++	sw	sp,36(k0)
++	sw	fp,40(k0)
++	sw	ra,44(k0)
++
++	mfc0	k1,CP0_PAGEMASK
++	sw	k1,48(k0)
++	mfc0	k1,CP0_STATUS
++	sw	k1,52(k0)
++	mfc0	k1,CP0_INTCTL
++	sw	k1,56(k0)
++	mfc0	k1,CP0_CAUSE
++	sw	k1,60(k0)
++	mfc0	k1,CP0_EBASE
++	sw	k1,64(k0)
++	mfc0	k1,CP0_CONFIG
++	sw	k1,68(k0)
++	mfc0	k1,CP0_CONFIG1
++	sw	k1,72(k0)
++	mfc0	k1,CP0_CONFIG2
++	sw	k1,76(k0)
++	mfc0	k1,CP0_CONFIG3
++	sw	k1,80(k0)
++	mfc0	k1,CP0_CONFIG4
++	sw	k1,84(k0)
++	mfc0	k1,CP0_CONFIG5
++	sw	k1,88(k0)
++	mfc0	k1,CP0_CONFIG7
++	sw	k1,92(k0)
++	mfc0	k1,CP0_LLADDR
++	sw	k1,96(k0)
++	mfc0	k1,CP0_WATCHLo
++	sw	k1,100(k0)
++	mfc0	k1,CP0_WATCHHI
++	sw	k1,104(k0)
++	mfc0	k1,CP0_ERRCTL
++	sw	k1,108(k0)
++	mfc0	k1,CP0_CONTEXT
++	sw	k1,112(k0)
++	mfc0	k1,CP0_KSCRATCH1
++	sw	k1,116(k0)
++	mfc0	k1,CP0_KSCRATCH2
++	sw	k1,120(k0)
++	mfc0	k1,CP0_KSCRATCH3
++	sw	k1,124(k0)
++	mfc0	k1,CP0_KSCRATCH4
++	sw	k1,128(k0)
++	mfc0	k1,CP0_KSCRATCH5
++	sw	k1,132(k0)
++	mfc0	k1,CP0_KSCRATCH6
++	sw	k1,136(k0)
++
++	jr.hb	a0
++	nop
++
++	.set	at
++	.set	reorder
++	.set	pop
++	END(save_goto)
++
++	.text
++	.global restore_goto
++	.align 2
++	.ent restore_goto,0
++	LEAF(restore_goto)
++restore_goto:
++	.set	push
++	.set	noreorder
++	.set	noat
++
++	la	k0, _regs_stack
++	lw	s0,0(k0)
++	lw	s1,4(k0)
++	lw	s2,8(k0)
++	lw	s3,12(k0)
++	lw	s4,16(k0)
++	lw	s5,20(k0)
++	lw	s6,24(k0)
++	lw	s7,28(k0)
++	lw	gp,32(k0)
++	lw	sp,36(k0)
++	lw	fp,40(k0)
++	lw	ra,44(k0)
++
++	lw	k1,48(k0)
++	mtc0	k1,CP0_PAGEMASK
++	lw	k1,52(k0)
++	mtc0	k1,CP0_STATUS
++	lw	k1,56(k0)
++	mtc0	k1,CP0_INTCTL
++	lw	k1,60(k0)
++	mtc0	k1,CP0_CAUSE
++	lw	k1,64(k0)
++	mtc0	k1,CP0_EBASE
++	lw	k1,68(k0)
++	mtc0	k1,CP0_CONFIG
++	lw	k1,72(k0)
++	mtc0	k1,CP0_CONFIG1
++	lw	k1,76(k0)
++	mtc0	k1,CP0_CONFIG2
++	lw	k1,80(k0)
++	mtc0	k1,CP0_CONFIG3
++	lw	k1,84(k0)
++	mtc0	k1,CP0_CONFIG4
++	lw	k1,88(k0)
++	mtc0	k1,CP0_CONFIG5
++	lw	k1,92(k0)
++	mtc0	k1,CP0_CONFIG7
++	lw	k1,96(k0)
++	mtc0	k1,CP0_LLADDR
++	lw	k1,100(k0)
++	mtc0	k1,CP0_WATCHLo
++	lw	k1,104(k0)
++	mtc0	k1,CP0_WATCHHI
++	lw	k1,108(k0)
++	mtc0	k1,CP0_ERRCTL
++	lw	k1,112(k0)
++	mtc0	k1,CP0_CONTEXT
++	lw	k1,116(k0)
++	mtc0	k1,CP0_KSCRATCH1
++	lw	k1,120(k0)
++	mtc0	k1,CP0_KSCRATCH2
++	lw	k1,124(k0)
++	mtc0	k1,CP0_KSCRATCH3
++	lw	k1,128(k0)
++	mtc0	k1,CP0_KSCRATCH4
++	lw	k1,132(k0)
++	mtc0	k1,CP0_KSCRATCH5
++	lw	k1,136(k0)
++	mtc0	k1,CP0_KSCRATCH6
++
++	jr.hb	ra
++	nop
++
++	.set	at
++	.set	reorder
++	.set	pop
++	END(restore_goto)
+diff --git a/arch/mips/xburst2/soc-m300/regs_save_restore.py b/arch/mips/xburst2/soc-m300/regs_save_restore.py
+new file mode 100755
+index 000000000..8a23de0d0
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/regs_save_restore.py
+@@ -0,0 +1,124 @@
++#!/usr/bin/env python
++import os
++import string
++
++common_regs=["s0","s1","s2","s3",
++        "s4","s5","s6","s7",
++        "gp","sp","fp","ra"]
++cp0_regs=[
++        ["CP0_PAGEMASK","$5","0"],
++        ["CP0_STATUS","$12","0"],
++        ["CP0_INTCTL","$12","1"],
++        ["CP0_CAUSE","$13","0"],
++        ["CP0_EBASE","$15","1"],
++        ["CP0_CONFIG","$16","0"],
++        ["CP0_CONFIG1","$16","1"],
++        ["CP0_CONFIG2","$16","2"],
++        ["CP0_CONFIG3","$16","3"],
++	["CP0_CONFIG4", "$16", "4"],
++	["CP0_CONFIG5", "$16", "5"],
++	["CP0_CONFIG7", "$16", "7"],
++        ["CP0_LLADDR","$17","0"],
++        ["CP0_WATCHLo","$18","0"],
++        ["CP0_WATCHHI","$19","0"],
++        ["CP0_ERRCTL","$26","0"],
++        ["CP0_CONTEXT","$4","0"],
++        ["CP0_KSCRATCH1","$31","2"],
++        ["CP0_KSCRATCH2","$31","3"],
++        ["CP0_KSCRATCH3","$31","4"],
++        ["CP0_KSCRATCH4","$31","5"],
++        ["CP0_KSCRATCH5","$31","6"],
++        ["CP0_KSCRATCH6","$31","7"],
++        ]
++def gen_get_array_size():
++    size=0
++    size+=len(common_regs)
++    size+=len(cp0_regs)
++    return size
++
++def gen_print_head_and_macro():
++    print("#include <asm/asm.h>")
++    print("#include <asm/regdef.h>")
++    print("")
++    for s in cp0_regs:
++        print("#define %s\t%s,%s" %(s[0],s[1],s[2]))
++    print("")
++def gen_define_global_arg(str, num):
++    print("\t.data")
++    print("\t.global %s" %(str))
++    print("%s:" %(str))
++    print("\t.align 5")
++    print("\t.space %s,0" %(num))
++    print("")
++
++def gen_save_common_regs(index):
++    for s in common_regs:
++        print("\tsw\t%s,%d(k0)" % (s,index))
++        index=index+4
++    return index
++def gen_restore_common_regs(index):
++    for s in common_regs:
++        print("\tlw\t%s,%d(k0)" % (s,index))
++        index=index+4
++    return index
++def gen_save_cp0_regs(index):
++    for s in cp0_regs:
++        print("\tmfc0\tk1,%s" % (s[0]))
++        print("\tsw\tk1,%d(k0)" % (index))
++        index=index+4
++    return index
++def gen_restore_cp0_regs(index):
++    for s in cp0_regs:
++        print("\tlw\tk1,%d(k0)" % (index))
++        print("\tmtc0\tk1,%s" % (s[0]))
++        index=index+4
++    return index
++def gen_print_function(f_name, regs_stack):
++    index=0
++    print("\t.text")
++    print("\t.global %s" %(f_name))
++    print("\t.align 2")
++    print("\t.ent %s,0" %(f_name))
++    print("\tLEAF(%s)" %(f_name))
++    print("%s:" %(f_name))
++    print("\t.set\tpush")
++    print("\t.set\tnoreorder")
++    print("\t.set\tnoat")
++    print("")
++    print("\tla\tk0, %s" %(regs_stack))
++    if f_name == "save_goto":
++        index = gen_save_common_regs(index)
++        print("")
++        index = gen_save_cp0_regs(index)
++        print("")
++        print("\tjr.hb\ta0")
++        print("\tnop")
++    elif f_name == "restore_goto":
++        index = gen_restore_common_regs(index)
++        print("")
++        index = gen_restore_cp0_regs(index)
++        print("")
++        print("\tjr.hb\tra")
++        print("\tnop")
++    else:
++        print("not support")
++    print("")
++    print("\t.set\tat")
++    print("\t.set\treorder")
++    print("\t.set\tpop")
++    print("\tEND(%s)" %(f_name))
++
++
++def main():
++    regs_size=gen_get_array_size()
++    regs_size*=4
++
++    gen_print_head_and_macro()
++    gen_define_global_arg("_regs_stack", regs_size)
++    gen_print_function("save_goto", "_regs_stack")
++    print("")
++    gen_print_function("restore_goto", "_regs_stack")
++    pass
++
++if __name__ == '__main__':
++    main()
+diff --git a/arch/mips/xburst2/soc-m300/reset.c b/arch/mips/xburst2/soc-m300/reset.c
+new file mode 100644
+index 000000000..e792ef140
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/reset.c
+@@ -0,0 +1,327 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/irq.h>
++#include <linux/tty.h>
++#include <linux/delay.h>
++#include <linux/proc_fs.h>
++#include <linux/kthread.h>
++#include <linux/syscore_ops.h>
++#include <linux/platform_device.h>
++#include <linux/sched/rt.h>
++#include <linux/slab.h>
++#include <linux/proc_fs.h>
++#include <linux/seq_file.h>
++#include <linux/module.h>
++
++
++#include <soc/base.h>
++#include <soc/cpm.h>
++#include <soc/extal.h>
++
++#include <asm/reboot.h>
++
++#include <ingenic_proc.h>
++
++#define RTC_RTCCR		(0x00)	/* rw, 32, 0x00000081 */
++#define RTC_RTCSR		(0x04)	/* rw, 32, 0x???????? */
++#define RTC_RTCSAR		(0x08)	/* rw, 32, 0x???????? */
++#define RTC_RTCGR		(0x0c)	/* rw, 32, 0x0??????? */
++#define RTC_HCR			(0x20)  /* rw, 32, 0x00000000 */
++#define RTC_HWFCR		(0x24)  /* rw, 32, 0x0000???0 */
++#define RTC_HRCR		(0x28)  /* rw, 32, 0x00000??0 */
++#define RTC_HWCR		(0x2c)  /* rw, 32, 0x00000008 */
++#define RTC_HWRSR		(0x30)  /* rw, 32, 0x00000000 */
++#define RTC_HSPR		(0x34)  /* rw, 32, 0x???????? */
++#define RTC_WENR		(0x3c)  /* rw, 32, 0x00000000 */
++#define RTC_CKPCR		(0x40)  /* rw, 32, 0x00000010 */
++#define RTC_OWIPCR		(0x44)  /* rw, 32, 0x00000010 */
++#define RTC_PWRONCR		(0x48)  /* rw, 32, 0x???????? */
++
++#define WDT_TCSR		(0x0c)  /* rw, 32, 0x???????? */
++#define WDT_TCER		(0x04)  /* rw, 32, 0x???????? */
++#define WDT_TDR			(0x00)  /* rw, 32, 0x???????? */
++#define WDT_TCNT		(0x08)  /* rw, 32, 0x???????? */
++
++#define TCU_TSSR	(0x2C)   /* Timer Stop Set Register */
++#define TCU_TSCR	(0x3C)   /* Timer Stop Clear Register */
++
++#define RTCCR_WRDY		BIT(7)
++#define WENR_WEN                BIT(31)
++
++#define RECOVERY_SIGNATURE	(0x001a1a)
++#define REBOOT_SIGNATURE	(0x003535)
++#define UNMSAK_SIGNATURE	(0x7c0000)//do not use these bits
++
++static void wdt_start_count(int msecs)
++{
++	int time = JZ_EXTAL_RTC / 64 * msecs / 1000;
++	if(time > 65535)
++		time = 65535;
++
++//	outl(1 << 16,TCU_IOBASE + TCU_TSCR);
++
++	outl(0,WDT_IOBASE + WDT_TCNT);		//counter
++	outl(time,WDT_IOBASE + WDT_TDR);	//data
++	outl((3<<3 | 2<<0 | 1 << 10),WDT_IOBASE + WDT_TCSR);
++	outl(0,WDT_IOBASE + WDT_TCER);
++	outl(1,WDT_IOBASE + WDT_TCER);
++}
++
++static void __attribute__((unused)) wdt_stop_count(void)
++{
++	outl(1 << 16,TCU_IOBASE + TCU_TSCR);
++	outl(0,WDT_IOBASE + WDT_TCNT);		//counter
++	outl(65535,WDT_IOBASE + WDT_TDR);	//data
++	outl(1 << 16,TCU_IOBASE + TCU_TSSR);
++}
++
++static int inline rtc_write_reg(int reg,int value)
++{
++	int timeout = 0x2000;
++	while(!(inl(RTC_IOBASE + RTC_RTCCR) & RTCCR_WRDY) && timeout--);
++	if(!timeout)
++	{
++		printk("WARN:NO USE RTC!!!!!\n");
++		return -1;
++	}
++	outl(0xa55a,(RTC_IOBASE + RTC_WENR));
++	while(!(inl(RTC_IOBASE + RTC_RTCCR) & RTCCR_WRDY));
++	while(!(inl(RTC_IOBASE + RTC_WENR) & WENR_WEN));
++	while(!(inl(RTC_IOBASE + RTC_RTCCR) & RTCCR_WRDY));
++	outl(value,(RTC_IOBASE + reg));
++	while(!(inl(RTC_IOBASE + RTC_RTCCR) & RTCCR_WRDY));
++
++	return 0;
++}
++
++/*
++ * Function: Keep power for CPU core when reset.
++ * So that EPC, tcsm and so on can maintain it's status after reset-key pressed.
++ */
++static int inline reset_keep_power(void)
++{
++	return rtc_write_reg(RTC_PWRONCR,
++			     inl(RTC_IOBASE + RTC_PWRONCR) & ~(1 << 0));
++}
++
++#define HWFCR_WAIT_TIME(x) ((x > 0x7fff ? 0x7fff: (0x7ff*(x)) / 2000) << 5)
++#define HRCR_WAIT_TIME(x) ((((x) > 1875 ? 1875: (x)) / 125) << 11)
++
++void jz_hibernate(void)
++{
++	uint32_t rtc_rtccr;
++
++	local_irq_disable();
++	/* Set minimum wakeup_n pin low-level assertion time for wakeup: 1000ms */
++	rtc_write_reg(RTC_HWFCR, HWFCR_WAIT_TIME(1000));
++
++	/* Set reset pin low-level assertion time after wakeup: must  > 60ms */
++	rtc_write_reg(RTC_HRCR, HRCR_WAIT_TIME(125));
++
++	/* clear wakeup status register */
++	rtc_write_reg(RTC_HWRSR, 0x0);
++
++	rtc_write_reg(RTC_HWCR, 0x0);
++
++	rtc_rtccr = inl(RTC_IOBASE + RTC_RTCCR);
++	rtc_rtccr |= 0x1 << 0;
++	rtc_write_reg(RTC_RTCCR,rtc_rtccr);
++
++	/* Put CPU to hibernate mode */
++	rtc_write_reg(RTC_HCR, 0x1);
++
++	/*poweroff the pmu*/
++//	jz_notifier_call(NOTEFY_PROI_HIGH, JZ_POST_HIBERNATION, NULL);
++
++	mdelay(200);
++
++	while(1)
++		printk("%s:We should NOT come here.%08x\n",__func__, inl(RTC_IOBASE + RTC_HCR));
++}
++
++void jz_wdt_restart(char *command)
++{
++	printk("Restarting after 4 ms\n");
++	if ((command != NULL) && !strcmp(command, "recovery")) {
++		while(cpm_inl(CPM_CPPSR) != RECOVERY_SIGNATURE) {
++			printk("set RECOVERY_SIGNATURE\n");
++			cpm_outl(0x5a5a,CPM_CPSPPR);
++			cpm_outl(RECOVERY_SIGNATURE,CPM_CPPSR);
++			cpm_outl(0x0,CPM_CPSPPR);
++			udelay(100);
++		}
++	} else {
++		cpm_outl(0x5a5a,CPM_CPSPPR);
++		cpm_outl(REBOOT_SIGNATURE,CPM_CPPSR);
++		cpm_outl(0x0,CPM_CPSPPR);
++	}
++
++	wdt_start_count(4);
++	mdelay(200);
++	while(1)
++		printk("check wdt.\n");
++}
++
++static void hibernate_restart(void)
++{
++	uint32_t rtc_rtcsr,rtc_rtccr;
++
++	while(!(inl(RTC_IOBASE + RTC_RTCCR) & RTCCR_WRDY));
++
++	rtc_rtcsr = inl(RTC_IOBASE + RTC_RTCSR);
++	rtc_rtccr = inl(RTC_IOBASE + RTC_RTCCR);
++
++	rtc_write_reg(RTC_RTCSAR,rtc_rtcsr + 5);
++	rtc_rtccr &= ~(1 << 4 | 1 << 1);
++	rtc_rtccr |= 0x3 << 2;
++	rtc_write_reg(RTC_RTCCR,rtc_rtccr);
++
++	/* Clear reset status */
++	cpm_outl(0,CPM_RSR);
++
++	/* Set minimum wakeup_n pin low-level assertion time for wakeup: 1000ms */
++	rtc_write_reg(RTC_HWFCR, HWFCR_WAIT_TIME(1000));
++
++	/* Set reset pin low-level assertion time after wakeup: must  > 60ms */
++	rtc_write_reg(RTC_HRCR, HRCR_WAIT_TIME(125));
++
++	/* clear wakeup status register */
++	rtc_write_reg(RTC_HWRSR, 0x0);
++
++	rtc_write_reg(RTC_HWCR, 0x1);
++
++
++	rtc_rtccr = inl(RTC_IOBASE + RTC_RTCCR);
++	rtc_rtccr |= 0x1 << 0;
++	rtc_write_reg(RTC_RTCCR,rtc_rtccr);
++
++
++	/* Put CPU to hibernate mode */
++	rtc_write_reg(RTC_HCR, 0x1);
++
++	mdelay(200);
++	while(1)
++		printk("%s:We should NOT come here.%08x\n",__func__, inl(RTC_IOBASE + RTC_HCR));
++}
++
++#ifdef CONFIG_HIBERNATE_RESET
++void jz_hibernate_restart(char *command)
++{
++	local_irq_disable();
++
++	if ((command != NULL) && !strcmp(command, "recovery")) {
++		jz_wdt_restart(command);
++	}
++
++	hibernate_restart();
++}
++#endif
++
++int __init reset_init(void)
++{
++	pm_power_off = jz_hibernate;
++#ifdef CONFIG_HIBERNATE_RESET
++	_machine_restart = jz_hibernate_restart;
++#else
++	_machine_restart = jz_wdt_restart;
++#endif
++	return 0;
++}
++arch_initcall(reset_init);
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++struct wdt_reset {
++	unsigned stop;
++	unsigned msecs;
++	unsigned count;
++};
++
++/* ============================reset proc=================================== */
++static char *reset_command[] = {"wdt","hibernate","recovery", "poweroff"};
++
++static int reset_show(struct seq_file *filq, void *v)
++{
++	int len = 0, i;
++
++	for(i = 0; i < ARRAY_SIZE(reset_command); i++)
++		seq_printf(filq, "%s\t", reset_command[i]);
++	seq_printf(filq,"\n");
++
++	return len;
++}
++
++static int reset_write(struct file *file, const char __user *buffer,
++		       size_t usize, loff_t *off)
++{
++	int command_size = 0;
++	int i;
++
++	if(usize == 0)
++		return -EINVAL;
++
++	command_size = ARRAY_SIZE(reset_command);
++	for(i = 0;i < command_size; i++) {
++		if(!strncmp(buffer, reset_command[i], strlen(reset_command[i])))
++			break;
++	}
++	if(i == command_size)
++		return -EINVAL;
++
++	local_irq_disable();
++	switch(i) {
++	case 0:
++		jz_wdt_restart(NULL);
++		break;
++	case 1:
++		hibernate_restart();
++		break;
++	case 2:
++		jz_wdt_restart("recovery");
++		break;
++	case 3:
++		jz_hibernate();
++		break;
++	default:
++		printk("not support command %d\n", i);
++	}
++
++	return usize;
++}
++static struct jz_single_file_ops reset_proc_fops = {
++	.read = reset_show,
++	.write = reset_write,
++};
++/* ============================reset proc end=============================== */
++
++static int __init init_reset(void)
++{
++	struct wdt_reset *wdt;
++	struct proc_dir_entry *p, *res;
++
++	wdt = kmalloc(sizeof(struct wdt_reset),GFP_KERNEL);
++	if(!wdt) {
++		return -ENOMEM;
++	}
++
++	wdt->count = 0;
++	wdt->msecs = 3000;
++
++	wdt->stop = 1;
++
++	p = jz_proc_mkdir("reset");
++	if (!p) {
++		printk("create_proc_entry for common reset failed.\n");
++		return -ENODEV;
++	}
++
++	res = jz_proc_create_data("reset", 0444, p, &reset_proc_fops, wdt);
++
++	return 0;
++}
++module_init(init_reset);
+diff --git a/arch/mips/xburst2/soc-m300/serial.c b/arch/mips/xburst2/soc-m300/serial.c
+new file mode 100644
+index 000000000..563208c52
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/serial.c
+@@ -0,0 +1,91 @@
++/*
++ * JZ SOC serial routines for early_printk.
++ *
++ * Copyright (C) 2006 Ingenic Semiconductor Inc.
++ *
++ */
++
++#include <asm/io.h>
++
++#include <soc/base.h>
++
++#define UART_BASE	UART0_IOBASE
++#define UART_OFF	0x1000
++
++#define OFF_TDR		(0x00)
++#define OFF_LCR		(0x0C)
++#define OFF_LSR		(0x14)
++
++#define LSR_TDRQ	(1 << 5)
++#define LSR_TEMT	(1 << 6)
++
++static void check_uart(char c);
++
++volatile u8 *uart_base;
++typedef void (*putchar_f_t)(char);
++static putchar_f_t putchar_f = check_uart;
++
++static void putchar(char ch)
++{
++	int timeout = 10000;
++	volatile u8 *base = uart_base;
++	/* Wait for fifo to shift out some bytes */
++	while ((base[OFF_LSR] & (LSR_TDRQ | LSR_TEMT))
++	       != (LSR_TDRQ | LSR_TEMT) && timeout--)
++		;
++	base[OFF_TDR] = (u8)ch;
++}
++
++static void putchar_dummy(char ch)
++{
++	return;
++}
++
++static void check_uart(char c)
++{
++	/* We Couldn't use ioremap() here */
++	volatile u8 *base = (volatile u8*)CKSEG1ADDR(UART0_IOBASE);
++	int i = 0;
++	for(i=0; i<10; i++) {
++		if(base[OFF_LCR])
++			break;
++		base += UART_OFF;
++	}
++
++	if(i<10) {
++		uart_base = base;
++		putchar_f = putchar;
++		putchar_f(c);
++	} else {
++		putchar_f = putchar_dummy;
++	}
++}
++
++/* used by early printk */
++void prom_putchar(char c)
++{
++	putchar_f(c);
++}
++
++void prom_putstr(char *s)
++{
++	while(*s) {
++		if(*s == '\n')
++			putchar_f('\r');
++		putchar_f(*s);
++		s++;
++	}
++}
++
++#if 1
++static char pbuffer[4096];
++void prom_printk(const char *fmt, ...) {
++	va_list args;
++
++	va_start(args, fmt);
++	vsnprintf(pbuffer, 4096, fmt, args);
++	va_end(args);
++
++	prom_putstr(pbuffer);
++}
++#endif
+diff --git a/arch/mips/xburst2/soc-m300/setup.c b/arch/mips/xburst2/soc-m300/setup.c
+new file mode 100644
+index 000000000..c4d68f03b
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/setup.c
+@@ -0,0 +1,84 @@
++/*
++ * Ingenic Soc Setup
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2006 Ingenic Semiconductor Inc.
++ */
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/delay.h>
++#include <linux/module.h>
++#include <linux/err.h>
++#include <linux/proc_fs.h>
++#include <linux/ioport.h>
++#include <linux/of_fdt.h>
++#include <linux/of_platform.h>
++#include <linux/clk-provider.h>
++#include <linux/clocksource.h>
++#include <linux/irqchip.h>
++#include <linux/clocksource.h>
++
++#include <asm/prom.h>
++#include <soc/base.h>
++
++void __init cpm_reset(void)
++{
++}
++
++int __init setup_init(void)
++{
++#if 0
++	cpm_reset();
++	/* Set bus priority here */
++	*(volatile unsigned int *)0xb34f0240 = 0x00010003;
++	*(volatile unsigned int *)0xb34f0244 = 0x00010003;
++#endif
++
++	return 0;
++}
++extern void __init init_all_clk(void);
++/* used by linux-mti code */
++extern void *get_fdt_addr(void);
++void __init plat_mem_setup(void)
++{
++	/* use IO_BASE, so that we can use phy addr on hard manual
++	 * directly with in(bwlq)/out(bwlq) in io.h.
++	 */
++	set_io_port_base(IO_BASE);
++	ioport_resource.start	= 0x00000000;
++	ioport_resource.end	= 0xffffffff;
++	iomem_resource.start	= 0x00000000;
++	iomem_resource.end	= 0xffffffff;
++	setup_init();
++
++	__dt_setup_arch(get_fdt_addr());
++
++	return;
++}
++void __init device_tree_init(void)
++{
++	unflatten_and_copy_device_tree();
++}
++
++static int __init plat_of_populate(void)
++{
++	of_platform_default_populate(NULL, NULL, NULL);
++	return 0;
++}
++arch_initcall(plat_of_populate);
++
++void __init plat_time_init(void)
++{
++	of_clk_init(NULL);
++
++	timer_probe();
++}
++
++void __init arch_init_irq(void)
++{
++	irqchip_init();
++}
+diff --git a/arch/mips/xburst2/soc-m300/sleep_firmware/Makefile b/arch/mips/xburst2/soc-m300/sleep_firmware/Makefile
+new file mode 100644
+index 000000000..45222b254
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/sleep_firmware/Makefile
+@@ -0,0 +1,42 @@
++TOPDIR = .
++
++CC = mips-linux-gnu-gcc
++LD = mips-linux-gnu-ld
++OBJCOPY = mips-linux-gnu-objcopy
++OBJDUMP	= mips-linux-gnu-objdump
++drop-sections := .reginfo .mdebug .oomment .note .pdr .options .MIPS.options
++strip-flags   := $(addprefix --remove-section=,$(drop-sections))
++
++CFLAGS += -I$(TOPDIR)/include
++CFLAGS += -nostdinc -Wall -Wundef -Werror-implicit-function-declaration \
++	 -fno-common -EL -Os -march=mips32 -mabi=32 -G 0 -mno-abicalls -fno-pic\
++	 -msoft-float
++
++LDFLAGS	:= -nostdlib -EL -T target.ld
++OBJCOPY_ARGS  := -O elf32-tradlittlemips
++
++OBJS := $(TOPDIR)/src/fastboot_resume.o	\
++	$(TOPDIR)/src/uart.o
++
++
++all: $(TOPDIR)/firmware.bin
++	@hexdump -v -e '"0x" 1/4 "%08x" "," "\n"' $< > $(TOPDIR)/fastboot_resume_code.hex
++
++$(TOPDIR)/firmware.bin:$(TOPDIR)/firmware.o
++	@$(LD) -nostdlib -EL -T $(TOPDIR)/target.ld $(OBJS) -Map $(TOPDIR)/fastboot.map -o $(TOPDIR)/fastboot.elf
++	@$(OBJCOPY) $(strip-flags) $(OBJCOPY_ARGS) -O binary $(TOPDIR)/fastboot.elf $@
++	@$(OBJDUMP) $(TOPDIR)/fastboot.elf -D > fastboot.dump
++$(TOPDIR)/firmware.o:$(OBJS)
++
++
++%.o:%.c
++	$(CC) $(CFLAGS) -o $@ -c $^
++
++%.o:%.S
++	$(CC) $(CFLAGS) -o $@ -c $^
++
++clean:
++	find . -name "*.o" | xargs rm -vf
++	find . -name "*.o.cmd" | xargs rm -vf
++	rm *.dump *.map *.elf *.bin *.hex
++
+diff --git a/arch/mips/xburst2/soc-m300/sleep_firmware/Readme b/arch/mips/xburst2/soc-m300/sleep_firmware/Readme
+new file mode 100644
+index 000000000..215604c5a
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/sleep_firmware/Readme
+@@ -0,0 +1,14 @@
++
++! this wakeup module is none of bussiness with the kernel.
++if you want to modify the code in the module. you should use
++the script mkmodule.sh right here.
++
++
++
++
++
++
++
++
++
++
+diff --git a/arch/mips/xburst2/soc-m300/sleep_firmware/include/base.h b/arch/mips/xburst2/soc-m300/sleep_firmware/include/base.h
+new file mode 100644
+index 000000000..b2eb14f02
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/sleep_firmware/include/base.h
+@@ -0,0 +1,91 @@
++
++#ifndef __JZSOC_SOC_DEV_H__
++#define __JZSOC_SOC_DEV_H__
++
++/*
++ * Define the module base addresses
++ */
++#define DDRC_BASE	0xb34f0000
++#define DDRC_APB_OFFSET (-0x4e0000 + 0x2000)
++#define DDR_PHY_OFFSET	(-0x4e0000 + 0x1000)
++
++/* AHB0 BUS Devices Base */
++#define HARB0_IOBASE	0x13000000 /* 64KB, AHB Bus Aribtier */
++#define DDR_PHY_IOBASE	0x13011000 /* 4KB, DDR PHY */
++#define DDRC_H0_IOBASE	0x13012000 /* 4KB, DDR Controller Registers@ASHB0 */
++#define DPU_IOBASE	0x13050000 /* 64KB, LCD Controller */
++#define CIM_IOBASE	0x13060000 /* 64KB, Camera Interface Module */
++#define ROTATE_IOBASE	0x13070000 /* 64KB, Rotate DMA */
++#define HELIX_IOBASE	0x13200000 /* 64KB VPU encoder */
++#define FELIX_IOBASE	0x13300000 /* 64KB VPU decoder */
++#define ISP0_IOBASE	0x13700000 /* 64KB Tiziano ISP0 */
++#define ISP1_IOBASE	0x13800000 /* 64KB Tiziano ISP1 */
++
++/* AHB2 Bus Devices Base */
++#define HARB2_IOBASE	0x13400000 /* 64KB, AHB Bus Arbiter */
++#define NEMC_IOBASE	0x13410000 /* 64KB, External Normal Memory/Boot ROM/OTP Controller */
++#define PDMA_IOBASE	0x13420000 /* 64KB, Programmable DMA Controller */
++#define AES_IOBASE	0x13430000 /* 64KB, AES */
++#define SFC_IOBASE	0x13440000 /* 64KB, SPI Flash Controller */
++#define MSC0_IOBASE	0x13450000 /* 64KB, MMC SD Controller0 */
++#define MSC1_IOBASE	0x13460000 /* 64KB, MMC SD Controller1 */
++#define MSC2_IOBASE	0x13490000 /* 64KB, MMC SD Controller2 */
++#define HASH_IOBASE	0x13470000 /* 64KB, HASH */
++#define RSA_IOBASE	0x13480000 /* 64KB, RSA */
++#define MAC0_IOBASE	0x134b0000 /* 64KB, GMAC/MAC */
++#define MAC1_IOBASE	0x134a0000 /* 64KB, GMAC/MAC */
++#define PWM_IOBASE	0x134c0000 /* 64KB, PWM */
++#define DDRC_H2_IOBASE	0x134f0000 /* 4KB, DDR Controller Register @AHB2 */
++#define AUDIO_IOBASE	0x134d0000 /* 64KB, Aduio System */
++#define OTG_IOBASE	0x13500000 /* 256KB, OTG2.0 Controller */
++#define EFUSE_IOBASE	0x13540000 /* 64KB, EFUSE */
++//#define INTC_IOBASE	0x13600000 /* Interrupt Controller */
++
++
++/* APB BUS Devices Base */
++#define CPM_IOBASE	0x10000000 /* 4KB, Clocks and Power Manager */
++#define TCU_IOBASE	0x10002000 /* 4KB, Timer/Count Unit,OperatingSystemTimer,Watchdog Timer */
++#define WDT_IOBASE	TCU_IOBASE /* 4KB, Timer/Count Unit,OperatingSystemTimer,Watchdog Timer */
++#define RTC_IOBASE	0x10003000 /* 4KB, Real-Time Clock */
++#define GPIO_IOBASE	0x10010000 /* 4KB, General-Purpose I/O */
++#define CODEC_IOBASE	0x10020000 /* 4KB, icodec I/O */
++#define	UART0_IOBASE	0x10030000 /* 4KB, UART0 Controller */
++#define	UART1_IOBASE	0x10031000 /* 4KB, UART1 Controller */
++#define	UART2_IOBASE	0x10032000 /* 4KB, UART2 Controller */
++#define	UART3_IOBASE	0x10033000 /* 4KB, UART3 Controller */
++#define	UART4_IOBASE	0x10034000 /* 4KB, UART4 Controller */
++#define	UART5_IOBASE	0x10035000 /* 4KB, UART5 Controller */
++#define	UART6_IOBASE	0x10036000 /* 4KB, UART6 Controller */
++#define	UART7_IOBASE	0x10037000 /* 4KB, UART7 Controller */
++#define	UART8_IOBASE	0x10038000 /* 4KB, UART8 Controller */
++#define	UART9_IOBASE	0x10039000 /* 4KB, UART9 Controller */
++#define SCC_IOBASE	0x10040000 /* 4KB, Smart Card Controller */
++#define SSI0_IOBASE	0x10043000 /* 4KB, Synchronous Serial Interface */
++#define SSI1_IOBASE	0x10044000 /* 4KB, Synchronous Serial Interface */
++#define I2C0_IOBASE	0x10050000 /* 4KB, I2C 0 Bus Interface */
++#define I2C1_IOBASE	0x10051000 /* 4KB, I2C 1 Bus Interface */
++#define I2C2_IOBASE	0x10052000 /* 4KB, I2C 2 Bus Interface */
++#define I2C3_IOBASE	0x10053000 /* 4KB, I2C 3 Bus Interface */
++#define I2C4_IOBASE	0x10054000 /* 4KB, I2C 4 Bus Interface */
++#define I2C5_IOBASE	0x10055000 /* 4KB, I2C 5 Bus Interface */
++#define SADC_IOBASE	0x10070000 /* 4KB, SADC */
++#define DTRNG_IOBASE	0x10072000 /* 4KB, DTRNG */
++#define MIPI_RX_2_IOBASE	0x10073000 /* 4KB, MIPI RX 2 Lane ctrl */
++#define MIPI_RX_4_IOBASE	0x10074000 /* 4KB, MIPI RX 4 lane ctrl */
++#define MIPI_TX_2_IOBASE	0x10075000 /* 4KB, MIPI TX 2 lane ctrl */
++#define MIPI_RX_PHY_IOBASE	0x10076000 /* 4KB, MIPI RX PHY  */
++#define MIPI_TX_PHY_IOBASE	0x10077000 /* 4KB, MIPI TX PHY  */
++#define USB_PHY_IOBASE		0x10078000 /* 4KB, USB PHY */
++
++/* TODO: Others To Be add */
++/* NAND CHIP Base Address */
++#define NEMC_CS1_IOBASE 0X1b000000
++#define NEMC_CS2_IOBASE 0X1a000000
++#define NEMC_CS3_IOBASE 0X19000000
++#define NEMC_CS4_IOBASE 0X18000000
++#define NEMC_CS5_IOBASE 0X17000000
++#define NEMC_CS6_IOBASE 0X16000000
++
++#define	OST_IOBASE	0x12000000
++
++#endif
+diff --git a/arch/mips/xburst2/soc-m300/sleep_firmware/include/cpm.h b/arch/mips/xburst2/soc-m300/sleep_firmware/include/cpm.h
+new file mode 100755
+index 000000000..495e3a4b1
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/sleep_firmware/include/cpm.h
+@@ -0,0 +1,230 @@
++/*
++ * X2000 CPM register definition
++ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.
++ */
++
++#ifndef __CPM_H__
++#define __CPM_H__
++
++#define BIT0            (1 << 0)
++#define BIT1            (1 << 1)
++#define BIT2            (1 << 2)
++#define BIT3            (1 << 3)
++#define BIT4            (1 << 4)
++#define BIT5            (1 << 5)
++#define BIT6            (1 << 6)
++#define BIT7            (1 << 7)
++#define BIT8            (1 << 8)
++#define BIT9            (1 << 9)
++#define BIT10           (1 << 10)
++#define BIT11           (1 << 11)
++#define BIT12           (1 << 12)
++#define BIT13           (1 << 13)
++#define BIT14           (1 << 14)
++#define BIT15           (1 << 15)
++#define BIT16           (1 << 16)
++#define BIT17           (1 << 17)
++#define BIT18           (1 << 18)
++#define BIT19           (1 << 19)
++#define BIT20           (1 << 20)
++#define BIT21           (1 << 21)
++#define BIT22           (1 << 22)
++#define BIT23           (1 << 23)
++#define BIT24           (1 << 24)
++#define BIT25           (1 << 25)
++#define BIT26           (1 << 26)
++#define BIT27           (1 << 27)
++#define BIT28           (1 << 28)
++#define BIT29           (1 << 29)
++#define BIT30           (1 << 30)
++#define BIT31           (1 << 31)
++
++/*
++ * Clock reset and power controller module(CPM) address definition
++ */
++#define	CPM_BASE		0xB0000000
++
++/*
++ * CPM registers offset address definition
++ */
++#define CPM_CPCCR		(0x00)
++#define CPM_RSR			(0x08)
++#define CPM_RSACDR		(0x50)
++#define CPM_CLKGR0		(0x20)
++#define CPM_OPCR		(0x24)
++#define CPM_CLKGR1		(0x28)
++#define CPM_DDRCDR		(0x2c)
++#define CPM_USBPCR		(0x3c)
++#define CPM_USBRDT		(0x40)
++#define CPM_USBVBFIL		(0x44)
++#define CPM_USBPCR1		(0x48)
++#define CPM_MSC0CDR		(0x68)
++#define CPM_MSC1CDR		(0xA4)
++#define CPM_MSC4CDR		(0xA8)
++#define CPM_SFCCDR		(0x74)
++#define CPM_CPCSR		(0xd4)
++#define CPM_SLBC		(0xc8)
++#define CPM_SLPC		(0xcc)
++#define CPM_CPPCR		(0x0c)
++#define CPM_CPAPCR		(0x10)
++#define CPM_CPMPCR		(0x14)
++#define CPM_EXCLK_DS		(0xE0)
++
++/*
++ * CPM registers common define
++ */
++/* Reset status register(RSR) */
++#define RSR_P0R			BIT2
++#define RSR_WR			BIT1
++#define RSR_PR			BIT0
++
++/* Clk Gate Register (CLKGR0) */
++#define CLKGR0_DDR		BIT31
++#define CLKGR0_RSA		BIT25
++#define CLKGR0_AES		BIT24
++#define CLKGR0_PDMA		BIT21
++#define CLKGR0_OST		BIT20
++#define CLKGR0_TCU		BIT18
++#define CLKGR0_UART2		BIT16
++#define CLKGR0_UART1		BIT15
++#define CLKGR0_UART0		BIT14
++#define CLKGR0_MSC1		BIT5
++#define CLKGR0_MSC0		BIT4
++#define CLKGR0_OTG		BIT3
++#define CLKGR0_SFC		BIT2
++#define CLKGR0_EFUSE		BIT1
++
++/* Clk Gate Register (CLKGR1) */
++#define CLKGR1_MSC4		BIT25
++#define CLKGR1_HASH		BIT6
++
++/* Msc Device Clock Divider Register (MSCnCDR) */
++#define MSCCDR_DIV_LSB		0
++#define MSCCDR_DIV_MASK		BITS_H2L(7, MSCCDR_DIV_LSB)
++
++#define MSCCDR_MPCS_LSB		30
++#define MSCCDR_MPCS_MASK	BITS_H2L(31, MSCCDR_MPCS_LSB)
++#define MSCCDR_MPCS_EXCLK	(0x2 << MSCCDR_MPCS_LSB)
++
++#define MSCCDR_BUSY		BIT28
++#define MSCCDR_CE		BIT29
++#define MSCCDR_EXCK_E		BIT21
++
++/* Sleep Pc Register (SLPC) */
++#define SLPC_SW_MAGIC		0x425753 // SWB (software boot)
++#define SLPC_SW_USB_BOOT	(0x2 << 0)
++
++/* APLL Control Register (CPAPCR) */
++#define CPAPCR_PLLFD_LSB	20
++#define CPAPCR_PLLFD_MASK	BITS_H2L(28, CPAPCR_PLLFD_LSB)
++
++#define CPAPCR_PLLRD_LSB	14
++#define CPAPCR_PLLRD_MASK	BITS_H2L(19, CPAPCR_PLLRD_LSB)
++
++#define CPAPCR_PLLOD_LSB	11
++#define CPAPCR_PLLOD_MASK	BITS_H2L(13, CPAPCR_PLLOD_LSB)
++
++#define CPAPCR_PLLRG_LSB	5
++#define CPAPCR_PLLRG_MASK	BITS_H2L(7, CPAPCR_PLLRG_LSB)
++
++#define CPAPCR_PLL_ON		BIT3
++#define CPAPCR_PLL_LOCK		BIT2
++#define CPAPCR_PLL_EN		BIT0
++
++/* EXCLK_DS MSC VOL SELECT */
++#define EXCLKDS_POC_MSC		BIT31
++
++
++#define cpm_readl(o)		readl(CPM_BASE + (o))
++#define cpm_writel(b, o)	writel(b, CPM_BASE + (o))
++
++
++#define __cpm_start_sfc()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_CLKGR0);		\
++		tmp &= ~CLKGR0_SFC;			\
++		cpm_writel(tmp, CPM_CLKGR0);		\
++	} while (0)
++#define __cpm_start_msc()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_CLKGR0);		\
++		tmp &= ~(CLKGR0_MSC0 | CLKGR0_MSC1);	\
++		cpm_writel(tmp, CPM_CLKGR0);		\
++		tmp = cpm_readl(CPM_CLKGR1);		\
++		tmp &= ~CLKGR1_MSC4;			\
++		cpm_writel(tmp, CPM_CLKGR1);		\
++	} while (0)
++#define __cpm_start_otg()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_CLKGR0);		\
++		tmp &= ~CLKGR0_OTG;			\
++		cpm_writel(tmp, CPM_CLKGR0);		\
++	} while (0)
++
++#define __cpm_start_uart0()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_CLKGR0);		\
++		tmp &= ~CLKGR0_UART0;			\
++		cpm_writel(tmp, CPM_CLKGR0);		\
++	} while (0)
++#define __cpm_start_uart1()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_CLKGR0);		\
++		tmp &= ~CLKGR0_UART1;			\
++		cpm_writel(tmp, CPM_CLKGR0);		\
++	} while (0)
++#define __cpm_start_uart2()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_CLKGR0);		\
++		tmp &= ~CLKGR0_UART2;			\
++		cpm_writel(tmp, CPM_CLKGR0);		\
++	} while (0)
++#define __cpm_start_ost()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_CLKGR0);		\
++		tmp &= ~CLKGR0_OST;			\
++		cpm_writel(tmp, CPM_CLKGR0);		\
++	} while (0)
++
++#define __cpm_msc4_vol_1_8V()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_EXCLK_DS);		\
++		tmp |= EXCLKDS_POC_MSC;			\
++		cpm_writel(tmp, CPM_EXCLK_DS);		\
++	} while (0)
++
++#define __cpm_msc4_vol_3_3V()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_EXCLK_DS);		\
++		tmp &= ~EXCLKDS_POC_MSC;			\
++		cpm_writel(tmp, CPM_EXCLK_DS);		\
++	} while (0)
++
++#ifdef FPGA_TEST
++#define __cpm_msc_tuning_set(v, n)				\
++	do {							\
++		unsigned int tmp;				\
++		unsigned int off;				\
++		if(n==0)					\
++			off = CPM_MSC0CDR;			\
++		else if(n==4)					\
++			off = CPM_MSC4CDR;			\
++		else						\
++			off = CPM_MSC1CDR;			\
++		tmp = cpm_readl(off);				\
++		tmp &= ~(1 << 20);				\
++		tmp |= ((v) & 0x1) << 20;			\
++		cpm_writel(tmp, off);				\
++	} while (0)
++#endif
++
++#endif /* __CPM_H__ */
+diff --git a/arch/mips/xburst2/soc-m300/sleep_firmware/include/ddr.h b/arch/mips/xburst2/soc-m300/sleep_firmware/include/ddr.h
+new file mode 100644
+index 000000000..241da4607
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/sleep_firmware/include/ddr.h
+@@ -0,0 +1,289 @@
++/*
++ * JZ4780 ddr definitions
++ *
++ * Copyright (c) 2013 Ingenic Semiconductor Co.,Ltd
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __DDR_H__
++#define __DDR_H__
++
++#include <base.h>
++
++/*
++ * DDR Controller Registers
++ **/
++#define DDR_MEM_PHY_BASE		0x20000000
++
++#define DDRC_STATUS		0x0
++#define DDRC_CFG		0x8
++#define DDRC_CTRL		0x10
++#define DDRC_LMR		0x18
++#define DDRC_DLP		0x20
++#define DDRC_AUTOSR_EN	0x28
++#define DDRC_AUTOSR_CNT	0x30
++#define DDRC_REFCNT		0x38
++#define DDRC_DBGINFO	0xE8
++#define DDRC_TIMING(n)	(0x40 + 8 * (n - 1))
++#define DDRC_MMAP0		0x78
++#define DDRC_MMAP1		0x80
++#define DDRC_HREGPRO	0xd8
++#define DDRC_DWCFG		(DDRC_APB_OFFSET + 0x00)
++#define DDRC_DWSTATUS	(DDRC_APB_OFFSET + 0x04)
++#define DDRC_REMAP(n)	(DDRC_APB_OFFSET + 0x08 + 4 * (n - 1))
++#define DDRC_CGUC0		(DDRC_APB_OFFSET + 0x64)
++#define DDRC_CGUC1		(DDRC_APB_OFFSET + 0x68)
++#define DDRC_PREGPRO	(DDRC_APB_OFFSET + 0x6c)
++
++/*
++ * DDR Innophy registers
++ * */
++#define DDRP_INNOPHY_PHY_RST			(DDR_PHY_OFFSET + 0x000)
++#define DDRP_INNOPHY_MEM_CFG			(DDR_PHY_OFFSET + 0x004)
++#define DDRP_INNOPHY_DQ_WIDTH			(DDR_PHY_OFFSET + 0x07c)
++#define DDRP_INNOPHY_CL					(DDR_PHY_OFFSET + 0x014)
++#define DDRP_INNOPHY_CWL				(DDR_PHY_OFFSET + 0x01c)
++#define DDRP_INNOPHY_AL					(DDR_PHY_OFFSET + 0x018)
++#define DDRP_INNOPHY_PLL_FBDIV			(DDR_PHY_OFFSET + 0x080)
++#define DDRP_INNOPHY_PLL_CTRL			(DDR_PHY_OFFSET + 0x084)
++#define DDRP_INNOPHY_PLL_PDIV			(DDR_PHY_OFFSET + 0x088)
++#define DDRP_INNOPHY_PLL_LOCK			(DDR_PHY_OFFSET + 0xc8)
++#define DDRP_INNOPHY_TRAINING_CTRL		(DDR_PHY_OFFSET + 0x008)
++#define DDRP_INNOPHY_CALIB_DONE			(DDR_PHY_OFFSET + 0xcc)
++#define DDRP_INNOPHY_CALIB_DELAY_AL		(DDR_PHY_OFFSET + 0x190)
++#define DDRP_INNOPHY_CALIB_DELAY_AH		(DDR_PHY_OFFSET + 0x194)
++#define DDRP_INNOPHY_CALIB_BYPASS_AL	(DDR_PHY_OFFSET + 0x118)
++#define DDRP_INNOPHY_CALIB_BYPASS_AH	(DDR_PHY_OFFSET + 0x158)
++#define DDRP_INNOPHY_WL_MODE1			(DDR_PHY_OFFSET + 0x00c)
++#define DDRP_INNOPHY_WL_MODE2			(DDR_PHY_OFFSET + 0x010)
++#define DDRP_INNOPHY_WL_DONE			(DDR_PHY_OFFSET + 0x0c0)
++#define DDRP_INNOPHY_INIT_COMP			(DDR_PHY_OFFSET + 0x0d0)
++
++
++/*
++ * DDRC REGISTER BITS DEFINE
++ * */
++
++/* DDRC Status Register */
++#define DDRC_DSTATUS_MISS	(1 << 6)
++#define DDRC_ST_DPDN		(1 << 5) /* 0 DDR memory is NOT in deep-power-down state
++										1 DDR memory is in deep-power-down state */
++#define DDRC_ST_PDN		(1 << 4) /* 0 DDR memory is NOT in power-down state
++									1 DDR memory is in power-down state */
++#define DDRC_ST_AREF		(1 << 3) /* 0 DDR memory is NOT in auto-refresh state
++										1 DDR memory is in auto-refresh state */
++#define DDRC_ST_SREF		(1 << 2) /* 0 DDR memory is NOT in self-refresh state
++										1 DDR memory is in self-refresh state */
++#define DDRC_ST_CKE1		(1 << 1) /* 0 CKE1 Pin is low
++										1 CKE1 Pin is high */
++#define DDRC_ST_CKE0		(1 << 0) /* 0 CKE0 Pin is low
++										1 CKE0 Pin is high */
++
++/* DDRC Configure Register */
++#define DDRC_CFG_ROW1_BIT	29 /* Row Address width. */
++#define DDRC_CFG_ROW1_MASK	(0x7 << DDRC_CFG_ROW1_BIT)
++#define DDRC_CFG_COL1_BIT	26 /* Row Address width. */
++#define DDRC_CFG_COL1_MASK	(0x7 << DDRC_CFG_COL1_BIT)
++#define DDRC_CFG_BA1		25 /* Bank Address width of DDR memory */
++#define DDRC_CFG_IMBA		(1 << 16)
++#define DDRC_CFG_ROW0_BIT	13 /* Row Address width. */
++#define DDRC_CFG_ROW0_MASK	(0x7 << DDRC_CFG_ROW0_BIT)
++#define DDRC_CFG_COL0_BIT	10 /* Row Address width. */
++#define DDRC_CFG_COL0_MASK	(0x7 << DDRC_CFG_COL1_BIT)
++#define DDRC_CFG_BA0		9 /* Bank Address width of DDR memory */
++
++#define DDRC_CFG_TYPE_BIT	3
++#define DDRC_CFG_TYPE_MASK	(0x7 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR1	(2 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_MDDR	(3 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR2	(4 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_LPDDR2	(5 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR3	(6 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_LPDDR3	(7 << DDRC_CFG_TYPE_BIT)
++
++#define DDRC_CFG_ODTEN		(1 << 2)  /* ODT EN */
++#define DDRC_CFG_CS1EN		(1 << 1)  /* DDR Chip-Select-1 Enable */
++#define DDRC_CFG_CS0EN		(1 << 0)  /* DDR Chip-Select-0 Enable */
++
++/* DDRC Control Register */
++#define DDRC_CTRL_DFI_RST	(1 << 23)
++#define DDRC_CTRL_DLL_RST	(1 << 22)
++#define DDRC_CTRL_CTL_RST	(1 << 21)
++#define DDRC_CTRL_CFG_RST	(1 << 20)
++#define DDRC_CTRL_ACTPD		(1 << 15) /* 0 Precharge all banks before entering power-down
++										 1 Do not precharge banks before entering power-down */
++#define DDRC_CTRL_PDT_BIT	12 /* Power-Down Timer */
++#define DDRC_CTRL_PDT_MASK	(0x7 << DDRC_CTRL_PDT_BIT)
++#define DDRC_CTRL_PDT_DIS	(0 << DDRC_CTRL_PDT_BIT) /* power-down disabled */
++#define DDRC_CTRL_PDT_8		(1 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 8 tCK idle */
++#define DDRC_CTRL_PDT_16	(2 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 16 tCK idle */
++#define DDRC_CTRL_PDT_32	(3 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 32 tCK idle */
++#define DDRC_CTRL_PDT_64	(4 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 64 tCK idle */
++#define DDRC_CTRL_PDT_128	(5 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 128 tCK idle */
++
++#define DDRC_CTRL_PD_CCE	(1 << 7) /* Power down clk freq change enable */
++#define DDRC_CTRL_DPD		(1 << 6) /* 1 Drive external MDDR device entering Deep-Power-Down mode */
++#define DDRC_CTRL_SR		(1 << 5) /* 1 Drive external DDR device entering self-refresh mode
++										0 Drive external DDR device exiting self-refresh mode */
++#define DDRC_CTRL_SR_CCE	(1 << 4) /* Self refresh clk stop request enable */
++#define DDRC_CTRL_CKE		(1 << 1) /* 0 Not set CKE Pin High, 1 Set CKE Pin HIGH */
++#define DDRC_CTRL_RESET		(1 << 0) /* 0 End resetting ddrc_controller, 1 Resetting ddrc_controller */
++
++/* DDRC DFI low power handshake control register */
++#define DDRC_DDLP_TCTLUDP_BIT	24
++#define DDRC_DDLP_TCTLUDP_FF	(0xff << DDRC_DDLP_TCTLUDP_BIT)
++
++/* DDRC Load-Mode-Register */
++#define DDRC_LMR_DDR_ADDR_BIT	12 /* When performing a DDR command, DDRC_ADDR[13:0]
++									  corresponding to external DDR address Pin A[13:0] */
++#define DDRC_LMR_DDR_ADDR_MASK	(0xfffff << DDRC_LMR_DDR_ADDR_BIT)
++
++#define DDRC_LMR_MA_BIT		16 /* FOR LPDDR2, MA[9:0] */
++#define DDRC_LMR_OP_BIT		24 /* FOR LPDDR2, OP[9:0] */
++
++#define DDRC_LMR_BA_BIT		9 /* When performing a DDR command, BA[2:0]
++								 corresponding to external DDR address Pin BA[2:0]. */
++#define DDRC_LMR_BA_MASK	(0x7 << DDRC_LMR_BA_BIT)
++#define DDRC_LMR_CMD_BIT	6
++#define DDRC_LMR_CMD_MASK	(0x7 << DDRC_LMR_CMD_BIT)
++#define DDRC_LMR_CMD_PREC	(0 << DDRC_LMR_CMD_BIT)/* Precharge one bank/All banks */
++#define DDRC_LMR_CMD_AUREF	(1 << DDRC_LMR_CMD_BIT)/* Auto-Refresh */
++#define DDRC_LMR_CMD_LMR	(2 << DDRC_LMR_CMD_BIT)/* Load Mode Register */
++#define DDRC_LMR_CMD_ZQCL_CS0	(3 << DDRC_LMR_CMD_BIT)/* ZQCL for DDR3 on CS0 */
++#define DDRC_LMR_CMD_ZQCL_CS1	(4 << DDRC_LMR_CMD_BIT)/* ZQCL for DDR3 on CS1 */
++#define DDRC_LMR_CMD_ZQCS_CS0	(5 << DDRC_LMR_CMD_BIT)/* ZQCS for DDR3 on CS0 */
++#define DDRC_LMR_CMD_ZQCS_CS1	(6 << DDRC_LMR_CMD_BIT)/* ZQCS for DDR3 on CS1 */
++
++#define DDRC_LMR_TMRD_BIT	1
++#define DDRC_LMR_TMRD_MASK	(0x1f << DDRC_LMR_TMRD_BIT)
++#define DDRC_LMR_START		(1 << 0) /* 0 No command is performed
++										1 On the posedge of START, perform a command
++										defined by CMD field */
++
++/* DDRC  Auto-Refresh Counter */
++#define DDRC_REFCNT_REF_EN		(1 << 0) /* Enable Refresh Counter */
++#define DDRC_REFCNT_CLK_DIV_BIT		1  /* Clock Divider for auto-refresh counter. */
++#define DDRC_REFCNT_CLK_DIV_MASK	(0x7 << DDRC_REFCNT_CLKDIV_BIT)
++
++#define DDRC_REFCNT_PREREF_CNT_BIT	4
++#define DDRC_REFCNT_PREREF_CNT_MASK	(0xf << DDRC_REFCNT_PREREF_CNT_BIT)
++#define DDRC_REFCNT_PREREF_CNT(val)	(val << DDRC_REFCNT_PREREF_CNT_BIT)
++#define DDRC_REFCNT_PREREF_CNT_DEFAULT	DDRC_REFCNT_PREREF_CNT(8)
++
++#define DDRC_REFCNT_CNT_BIT		8  /* 8-bit counter */
++#define DDRC_REFCNT_CNT_MASK		(0xff << DDRC_REFCNT_CNT_BIT)
++
++#define DDRC_REFCNT_CON_BIT		16 /* Constant value used to compare with CNT value. */
++#define DDRC_REFCNT_CON_MASK		(0xff << DDRC_REFCNT_CON_BIT)
++
++#define DDRC_REFCNT_TRFC_BIT		24
++#define DDRC_REFCNT_TRFC_MASK		(0x3f << DDRC_REFCNT_TRFC_BIT)
++
++#define DDRC_REFCNT_PREREF_EN_BIT	30
++#define DDRC_REFCNT_PREREF_EN		(1 << DDRC_REFCNT_PREREF_EN_BIT)
++
++#define DDRC_REFCNT_PBREF_EN_BIT	31
++#define DDRC_REFCNT_PBREF_EN		(1 << DDRC_REFCNT_PBREF_EN_BIT)
++
++/* DDRC Memory Map Config Register */
++#define DDRC_MMAP_BASE_BIT		8 /* base address */
++#define DDRC_MMAP_BASE_MASK		(0xff << DDRC_MMAP_BASE_BIT)
++#define DDRC_MMAP_MASK_BIT		0 /* address mask */
++#define DDRC_MMAP_MASK_MASK		(0xff << DDRC_MMAP_MASK_BIT)
++
++#define DDRC_MMAP0_BASE			(0x20 << DDRC_MMAP_BASE_BIT)
++#define DDRC_MMAP1_BASE_64M		(0x24 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++#define DDRC_MMAP1_BASE_128M		(0x28 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++#define DDRC_MMAP1_BASE_256M		(0x30 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++
++#define DDRC_MMAP_MASK_64_64		(0xfc << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++#define DDRC_MMAP_MASK_128_128		(0xf8 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++#define DDRC_MMAP_MASK_256_256		(0xf0 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++
++/* DDR device data width configure register */
++#define DDRC_DWCFG_DFI_INIT_START	(1 << 3)
++
++/* DDR device status register */
++#define DDRC_DWSTATUS_DFI_INIT_COMP	(1 << 0)
++
++/* DDRC AHB Bus Register Protection Register */
++#define DDRC_HREGPRO_HPRO_EN		(1 << 0)
++
++/* DDRC APB Bus Register Protection Register */
++#define DDRC_PREGPRO_PPRO_EN		(1 << 0)
++
++
++/* DDRC clock gate unit configure 0 */
++#define DDRC_CGU_PORT7		(1 << 28)
++#define DDRC_CGU_PORT6		(1 << 24)
++#define DDRC_CGU_PORT5		(1 << 20)
++#define DDRC_CGU_PORT4		(1 << 16)
++#define DDRC_CGU_PORT3		(1 << 12)
++#define DDRC_CGU_PORT2		(1 << 8)
++#define DDRC_CGU_PORT1		(1 << 4)
++#define DDRC_CGU_PORT0		(1 << 0)
++
++/* DDRC clock gate unit configure 1 */
++#define DDRC_CGU_BWM		(1 << 8)
++#define DDRC_CGU_PCTRL		(1 << 4)
++#define DDRC_CGU_SCH		(1 << 1)
++#define DDRC_CGU_PA		(1 << 0)
++
++
++
++/*
++ * DDR INNOPHY REGISTER BITS DEFINE
++ * */
++
++/* DDRP DQ Width Register */
++#define DDRP_DQ_WIDTH_DQ_H		(1 << 1)
++#define DDRP_DQ_WIDTH_DQ_L		(1 << 0)
++
++/* DDRP Pll Ctrl Register */
++#define DDRP_PLL_CTRL_PLLPDEN		(1 << 1)
++
++/* DDRP Training Ctrl Register */
++#define DDRP_TRAINING_CTRL_WL_BP	(1 << 3)
++#define DDRP_TRAINING_CTRL_WL_START	(1 << 2)
++#define DDRP_TRAINING_CTRL_DSCSE_BP	(1 << 1)
++#define DDRP_TRAINING_CTRL_DSACE_START	(1 << 0)
++
++/* DDRP Training Done Register */
++#define DDRP_CALIB_DONE_HDQCFB 		(1 << 3)
++#define DDRP_CALIB_DONE_LDQCFB 		(1 << 2)
++#define DDRP_CALIB_DONE_HDQCFA 		(1 << 1)
++#define DDRP_CALIB_DONE_LDQCFA 		(1 << 0)
++#define DDRP_CALIB_DONE_HWRLFB 		(1 << 3)
++#define DDRP_CALIB_DONE_LWRLFB 		(1 << 2)
++#define DDRP_CALIB_DONE_HWRLFA 		(1 << 1)
++#define DDRP_CALIB_DONE_LWRLFA 		(1 << 0)
++
++/* DDRP CALIB BP Register */
++#define DDRP_CALIB_BP_CYCLESELBH_BIT	4
++#define DDRP_CALIB_BP_OPHCSELBH_BIT	3
++#define DDRP_CALIB_BP_DLLSELBH_BIT	0
++
++/* DDRP Init Complete Register */
++#define DDRP_INIT_COMP			(1 << 0)
++
++#define DDRP_PLL_LOCK			(1 << 3)
++
++#define REG32(addr) *(volatile unsigned int *)(addr)
++
++#define ddr_writel(value, reg)	(REG32(DDRC_BASE + reg) = (value))
++#define ddr_readl(reg)		REG32(DDRC_BASE + reg)
++#endif /* __DDR_H__ */
+diff --git a/arch/mips/xburst2/soc-m300/sleep_firmware/include/gpio.h b/arch/mips/xburst2/soc-m300/sleep_firmware/include/gpio.h
+new file mode 100755
+index 000000000..8440f2a91
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/sleep_firmware/include/gpio.h
+@@ -0,0 +1,267 @@
++/*
++ *
++ * X2000 GPIO register definition.
++ *
++ * Copyright (C) 2012 Ingenic Semiconductor Co., Ltd.
++ */
++
++/* check */
++
++#ifndef __GPIO_H__
++#define __GPIO_H__
++
++
++/*************************************************************************
++ * GPIO (General-Purpose I/O Ports)
++ *************************************************************************/
++#define GPIO_BASE	0xB0010000
++
++#define GPA(x) 		(32 * 0 + (x))
++#define GPB(x) 		(32 * 1 + (x))
++#define GPC(x) 		(32 * 2 + (x))
++#define GPD(x) 		(32 * 3 + (x))
++#define GPE(x) 		(32 * 4 + (x))
++#define GPF(x) 		(32 * 5 + (x))
++
++#define GPIO_PORT_NUM   6
++#define MAX_GPIO_NUM	192
++#define GPIO_WAKEUP     GPF(31)  //WAKE_UP key PF31
++
++//n = 0,1,2,3,4 (PORTA, PORTB, PORTC, PORTD, PORTE)
++#define GPIO_PXPIN(n)	(0x00 + (n) * 0x100) /* PIN Level Register */
++
++#define GPIO_PXINT(n)	(0x10 + (n) * 0x100) /* Port Interrupt Register */
++#define GPIO_PXINTS(n)	(0x14 + (n) * 0x100) /* Port Interrupt Set Register */
++#define GPIO_PXINTC(n)	(0x18 + (n) * 0x100) /* Port Interrupt Clear Register */
++
++#define GPIO_PXMASK(n)	(0x20 + (n) * 0x100) /* Port Interrupt Mask Register */
++#define GPIO_PXMASKS(n)	(0x24 + (n) * 0x100) /* Port Interrupt Mask Set Reg */
++#define GPIO_PXMASKC(n)	(0x28 + (n) * 0x100) /* Port Interrupt Mask Clear Reg */
++
++#define GPIO_PXPAT1(n)	(0x30 + (n) * 0x100) /* Port Pattern 1 Register */
++#define GPIO_PXPAT1S(n)	(0x34 + (n) * 0x100) /* Port Pattern 1 Set Reg. */
++#define GPIO_PXPAT1C(n)	(0x38 + (n) * 0x100) /* Port Pattern 1 Clear Reg. */
++
++#define GPIO_PXPAT0(n)	(0x40 + (n) * 0x100) /* Port Pattern 0 Register */
++#define GPIO_PXPAT0S(n)	(0x44 + (n) * 0x100) /* Port Pattern 0 Set Register */
++#define GPIO_PXPAT0C(n)	(0x48 + (n) * 0x100) /* Port Pattern 0 Clear Register */
++
++#define GPIO_PXFLG(n)	(0x50 + (n) * 0x100) /* Port Flag Register */
++#define GPIO_PXFLGC(n)	(0x58 + (n) * 0x100) /* Port Flag clear Register */
++
++#define GPIO_PXPU(n)	(0x80 + (n) * 0x100) /* PORT PULL-UP State Register */
++#define GPIO_PXPUS(n)	(0x84 + (n) * 0x100) /* PORT PULL-UP State Set Register*/
++#define GPIO_PXPUC(n)	(0x88 + (n) * 0x100) /* PORT PULL-UP State Clear Register */
++
++#define GPIO_PXPD(n)	(0x90 + (n) * 0x100) /* PORT PULL-DOWN State Register */
++#define GPIO_PXPDS(n)	(0x94 + (n) * 0x100) /* PORT PULL-DOWN State Set Register */
++#define GPIO_PXPDC(n)	(0x98 + (n) * 0x100) /* PORT PULL-DOWN State Set Register */
++
++#define gpio_readl(o)		readl(GPIO_BASE + (o))
++#define gpio_writel(b, o)	writel(b, GPIO_BASE + (o))
++
++#ifndef __MIPS_ASSEMBLER
++
++/*----------------------------------------------------------------
++ * p is the port number (0,1,2,3,4,5)
++ * o is the pin offset (0-31) inside the port
++ * n is the absolute number of a pin (0-127), regardless of the port
++ */
++
++//----------------------------------------------------------------
++/*
++ * Gpio Pull set
++ */
++#define __gpio_set_hiz(v, p)			\
++do {						\
++	unsigned long val = v;			\
++	gpio_writel(val, GPIO_PXPUC(p));	\
++	gpio_writel(val, GPIO_PXPDC(p));	\
++} while (0)
++
++/*
++ * UART0_TxD, UART0_RxD, PD27
++ */
++#define __gpio_as_uart0()			\
++do {						\
++	gpio_writel((3 << 23), GPIO_PXINTC(3));	\
++	gpio_writel((3 << 23), GPIO_PXMASKC(3));\
++	gpio_writel((3 << 23), GPIO_PXPAT1S(3));\
++	gpio_writel((3 << 23), GPIO_PXPAT0C(3));\
++} while (0)
++
++/*
++ * UART1_TxD, UART1_RxD, PA23
++ */
++#define __gpio_as_uart1()			\
++do {						\
++	gpio_writel((3 << 23), GPIO_PXINTC(2));	\
++	gpio_writel((3 << 23), GPIO_PXMASKC(2));	\
++	gpio_writel((3 << 23), GPIO_PXPAT1C(2));	\
++	gpio_writel((3 << 23), GPIO_PXPAT0S(2));	\
++} while (0)
++
++/*
++ * UART2_TxD, UART2_RxD
++ */
++#define __gpio_as_uart2()			\
++do {						\
++	gpio_writel((3 << 30), GPIO_PXINTC(3));	\
++	gpio_writel((3 << 30), GPIO_PXMASKC(3));\
++	gpio_writel((3 << 30), GPIO_PXPAT1C(3));\
++	gpio_writel((3 << 30), GPIO_PXPAT0C(3));\
++} while (0)
++
++/*
++ * CS2#, RD#, WR#, WAIT#, A0 ~ A5
++ * @n: chip select number(1 ~ 4)
++ */
++#define __gpio_as_nor(n)				\
++do {							\
++	gpio_writel((0x7 << 13), GPIO_PXINTC(1));	\
++	gpio_writel((0x7 << 13), GPIO_PXMASKC(1));	\
++	gpio_writel((0x7 << 13), GPIO_PXPAT1C(1));	\
++	gpio_writel((0x7 << 13), GPIO_PXPAT0C(1));	\
++	gpio_writel((0x3 << 23), GPIO_PXINTC(2));	\
++	gpio_writel((0x3 << 23), GPIO_PXMASKC(2));	\
++	gpio_writel((0x3 << 23), GPIO_PXPAT1S(2));	\
++	gpio_writel((0x3 << 23), GPIO_PXPAT0S(2));	\
++} while (0)
++/*
++ * D0 ~ D7
++ */
++#define __gpio_as_nor_8bit()						\
++do {									\
++	gpio_writel((0xffffffff), GPIO_PXINTC(1));		\
++	gpio_writel((0xffffffff), GPIO_PXMASKC(1));		\
++	gpio_writel((0xffffffff), GPIO_PXPAT1C(1));		\
++	gpio_writel((0xffffffff), GPIO_PXPAT0C(1));		\
++} while (0)
++
++/*
++ * D0 ~ D15
++ */
++#define __gpio_as_nor_16bit()						\
++do {	               							\
++	gpio_writel((0xffffffff), GPIO_PXINTC(1));		\
++	gpio_writel((0xffffffff), GPIO_PXMASKC(1));		\
++	gpio_writel((0xffffffff), GPIO_PXPAT1C(1));		\
++	gpio_writel((0xffffffff), GPIO_PXPAT0C(1));		\
++} while (0)
++
++
++/* gpio as sfc disable pull */
++/* PE16 - PE21 */
++#define __gpio_as_3_3V_sfc()				\
++do {						\
++	gpio_writel((0x3f << 16), GPIO_PXINTC(4));	\
++	gpio_writel((0x3f << 16), GPIO_PXMASKC(4));	\
++	gpio_writel((0x3f << 16), GPIO_PXPAT1C(4));	\
++	gpio_writel((0x3f << 16), GPIO_PXPAT0C(4));	\
++	if(!EFUSE_SWC_SFC)				\
++		__gpio_set_hiz((0x3f) << 16, 4);	\
++} while (0)
++
++/* gpio as sfc disable pull */
++/* PD17 - PD22 */
++#define __gpio_as_1_8V_sfc()				\
++do {						\
++	gpio_writel((0x3f << 17), GPIO_PXINTC(3));	\
++	gpio_writel((0x3f << 17), GPIO_PXMASKC(3));	\
++	gpio_writel((0x3f << 17), GPIO_PXPAT1C(3));	\
++	gpio_writel((0x3f << 17), GPIO_PXPAT0S(3));	\
++	if(!EFUSE_SWC_SFC)				\
++		__gpio_set_hiz((0x3f) << 17, 3);	\
++} while (0)
++
++/*
++ * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D7
++ */
++
++/* pull disable */
++
++/* PD17 - PD26, func0, 1bit*/
++#define __gpio_as_msc0_1bit()			\
++do {						\
++	gpio_writel(0x7 << 17, GPIO_PXINTC(3));	\
++	gpio_writel(0x7 << 17, GPIO_PXMASKC(3));	\
++	gpio_writel(0x7 << 17, GPIO_PXPAT1C(3));	\
++	gpio_writel(0x7 << 17, GPIO_PXPAT0C(3));	\
++	if(!EFUSE_SWC_MSC)			\
++		__gpio_set_hiz((0x7 << 17), 3);	\
++} while (0)
++
++/* PD17 - PD26, func0, 4bit*/
++#define __gpio_as_msc0_4bit()			\
++do {						\
++	gpio_writel(0x3f << 17, GPIO_PXINTC(3));	\
++	gpio_writel(0x3f << 17, GPIO_PXMASKC(3));	\
++	gpio_writel(0x3f << 17, GPIO_PXPAT1C(3));	\
++	gpio_writel(0x3f << 17, GPIO_PXPAT0C(3));	\
++	if(!EFUSE_SWC_MSC)			\
++		__gpio_set_hiz((0x3f << 17), 3);	\
++} while (0)
++
++
++/* PD08 - PD13, func0, 1bit*/
++#define __gpio_as_msc1_1bit()			\
++do {						\
++	gpio_writel(0x7 << 8, GPIO_PXINTC(3));	\
++	gpio_writel(0x7 << 8, GPIO_PXMASKC(3));	\
++	gpio_writel(0x7 << 8, GPIO_PXPAT1C(3));	\
++	gpio_writel(0x7 << 8, GPIO_PXPAT0C(3));	\
++	if(!EFUSE_SWC_MSC)			\
++		__gpio_set_hiz((0x7 << 8), 3);	\
++} while (0)
++
++/* PD08 - PD13, func0, 4bit*/
++#define __gpio_as_msc1_4bit()			\
++do {						\
++	gpio_writel(0x3f << 8, GPIO_PXINTC(3));	\
++	gpio_writel(0x3f << 8, GPIO_PXMASKC(3));	\
++	gpio_writel(0x3f << 8, GPIO_PXPAT1C(3));	\
++	gpio_writel(0x3f << 8, GPIO_PXPAT0C(3));	\
++	if(!EFUSE_SWC_MSC)			\
++		__gpio_set_hiz((0x3f << 8), 3);	\
++} while (0)
++
++
++/* PE0 - PE5, func0 */
++#define __gpio_as_msc4_1bit()			\
++do {						\
++	gpio_writel((0x7 << 0), GPIO_PXINTC(4));	\
++	gpio_writel((0x7 << 0), GPIO_PXMASKC(4));	\
++	gpio_writel((0x7 << 0), GPIO_PXPAT1C(4));	\
++	gpio_writel((0x7 << 0), GPIO_PXPAT0C(4));	\
++	if(!EFUSE_SWC_MSC)				\
++		__gpio_set_hiz((0x7) << 0, 4);	\
++} while (0)
++
++/* PE0 - PE5, func0 */
++#define __gpio_as_msc4_4bit()			\
++do {						\
++	gpio_writel((0x3f << 0), GPIO_PXINTC(4));	\
++	gpio_writel((0x3f << 0), GPIO_PXMASKC(4));	\
++	gpio_writel((0x3f << 0), GPIO_PXPAT1C(4));	\
++	gpio_writel((0x3f << 0), GPIO_PXPAT0C(4));	\
++	if(!EFUSE_SWC_MSC)				\
++		__gpio_set_hiz((0x3f) << 0, 4);	\
++} while (0)
++
++#define bootsel_gpio_init() 			\
++do{						\
++	gpio_writel((0x7 << 25), GPIO_PXINTC(4));	\
++	gpio_writel((0x7 << 25), GPIO_PXMASKS(4));\
++	gpio_writel((0x7 << 25), GPIO_PXPAT1S(4));\
++	gpio_writel((0x7 << 25), GPIO_PXPAT0C(4));\
++	__gpio_set_hiz((0x7) << 25, 4);	\
++}while(0)
++
++#define boot_select()	((gpio_readl(GPIO_PXPIN(4)) >> 25) & 0x7)
++
++#define BOOT_SELECT_3_3V	(0)
++#define BOOT_SELECT_1_8V	(1)
++#endif /* __MIPS_ASSEMBLER */
++
++#endif /* __GPIO_H__ */
++
+diff --git a/arch/mips/xburst2/soc-m300/sleep_firmware/include/pm_fastboot.h b/arch/mips/xburst2/soc-m300/sleep_firmware/include/pm_fastboot.h
+new file mode 100644
+index 000000000..1151e77a2
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/sleep_firmware/include/pm_fastboot.h
+@@ -0,0 +1,187 @@
++
++
++#define RTC_SLEEP_MEMORY_START          0xb0004000
++#define RTC_SLEEP_MEMORY_END            0xb0005000
++#define RTC_RAM_SP_ADDR                 (RTC_RAM_DATA_ADDR - 4)
++//#define RTC_RAM_SP_SIZE                 (256 - 4)
++#define RTC_RAM_DATA_ADDR               0xb0004c00
++#define RTC_RAM_DATA_SIZE               1024
++#define RTC_RAM_CODE_ADDR1              0xb0004000
++#define RTC_RAM_CODE_ADDR2              (RTC_RAM_CODE_ADDR1 + 64)
++#define RTC_RAM_CODE_SIZE               0xb00
++
++#define SLEEP_CPU_SLEEP_TEXT		0xb2400000
++#define SLEEP_CPU_SLEEP_LEN		4096
++
++
++
++struct pll_resume_reg {
++	unsigned int cpccr;
++	unsigned int cppcr;
++	unsigned int cpapcr;
++	unsigned int cpmpcr;
++	unsigned int cpepcr;
++	unsigned int ddrcdr;
++};
++
++struct ddrc_resume_reg {
++	unsigned int dcfg;
++	unsigned int dctrl;
++	unsigned int dlmr;
++	unsigned int ddlp;
++	unsigned int dasr_en;
++	unsigned int dasr_cnt;
++	unsigned int drefcnt;
++	unsigned int dtimming1;
++	unsigned int dtimming2;
++	unsigned int dtimming3;
++	unsigned int dtimming4;
++	unsigned int dtimming5;
++	unsigned int dmmap0;
++	unsigned int dmmap1;
++	unsigned int dbwcfg;
++	unsigned int dbwstp;
++	unsigned int hregpro;
++	unsigned int dbgen;
++	unsigned int dwcfg;
++	unsigned int dremap1;
++	unsigned int dremap2;
++	unsigned int dremap3;
++	unsigned int dremap4;
++	unsigned int dremap5;
++	unsigned int cpac;
++	unsigned int cchc0;
++	unsigned int cchc1;
++	unsigned int cchc2;
++	unsigned int cchc3;
++	unsigned int cchc4;
++	unsigned int cchc5;
++	unsigned int cchc6;
++	unsigned int cchc7;
++	unsigned int cschc0;
++	unsigned int cschc1;
++	unsigned int cschc2;
++	unsigned int cschc3;
++	unsigned int cmonc0;
++	unsigned int cmonc1;
++	unsigned int cmonc2;
++	unsigned int cmonc3;
++	unsigned int cmonc4;
++	unsigned int ccguc0;
++	unsigned int ccguc1;
++	unsigned int pregpro;
++	unsigned int bufcfg;
++};
++
++struct ddr_phy_resume_reg {
++	unsigned int phy_rst;
++	unsigned int mem_cfg;
++	unsigned int dq_width;
++	unsigned int cl;
++	unsigned int al;
++	unsigned int cwl;
++	unsigned int pll_fbdiv;
++	unsigned int pll_ctrl;
++	unsigned int pll_pdiv;
++	unsigned int training_ctrl;
++	unsigned int calib_bypass_al;
++	unsigned int calib_bypass_ah;
++	unsigned int wl_mode1;
++	unsigned int wl_mode2;
++
++};
++
++struct store_regs {
++	unsigned int resume_pc;
++	unsigned int uart_index;
++	struct pll_resume_reg pll_resume_reg;
++	struct ddrc_resume_reg ddrc_resume_reg;
++	struct ddr_phy_resume_reg ddr_phy_resume_reg;
++};
++
++
++
++
++#define DDR_PHY_OFFSET  (-0x4e0000 + 0x1000)
++#define DDRP_INNOPHY_RXDLL_DELAY_AL             (DDR_PHY_OFFSET + (0x48 << 2))
++#define DDRP_INNOPHY_RXDLL_DELAY_AH             (DDR_PHY_OFFSET + (0x58 << 2))
++
++#define REG32(addr) *(volatile unsigned int *)(addr)
++#define ddr_writel(value, reg)  (REG32(DDRC_BASE + reg) = (value))
++#define ddr_readl(reg)          REG32(DDRC_BASE + reg)
++
++
++
++static void rtc_write_reg(unsigned int reg, unsigned int val)
++{
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++	*(volatile unsigned int *)0xb000303c = 0xa55a;
++	while (!((*(volatile unsigned int *)0xb000303c >> 31) & 0x1) );
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++
++	*(volatile unsigned int *)reg = val;
++
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++}
++
++static unsigned int  rtc_read_reg(unsigned int reg)
++{
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++
++	return *(volatile unsigned int *)reg;
++}
++
++
++#define FASTBOOT_DEBUG
++
++#ifdef FASTBOOT_DEBUG
++
++#include <uart.h>
++
++extern unsigned int get_uart_index(void);
++
++void DEBUG(const char *s)
++{
++	serial_puts(get_uart_index(), s);
++}
++
++void DEBUG_HEX(unsigned int  d)
++{
++	serial_put_hex(get_uart_index(), d);
++}
++
++
++#define	GPIO_PULSE()		\
++	while (1) {		\
++		*(volatile unsigned int *)0xb0010218 = (1 << 20);	\
++		*(volatile unsigned int *)0xb0010224 = (1 << 20);	\
++		*(volatile unsigned int *)0xb0010238 = (1 << 20);	\
++		*(volatile unsigned int *)0xb0010248 = (1 << 20);	\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		*(volatile unsigned int *)0xb0010218 = (1 << 20);	\
++		*(volatile unsigned int *)0xb0010224 = (1 << 20);	\
++		*(volatile unsigned int *)0xb0010238 = (1 << 20);	\
++		*(volatile unsigned int *)0xb0010244 = (1 << 20);	\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++	}
++
++
++#else
++#define DEBUG(s)
++#define DEBUG_HEX(a)
++#endif
++
+diff --git a/arch/mips/xburst2/soc-m300/sleep_firmware/include/uart.h b/arch/mips/xburst2/soc-m300/sleep_firmware/include/uart.h
+new file mode 100755
+index 000000000..b87b2d236
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/sleep_firmware/include/uart.h
+@@ -0,0 +1,113 @@
++/*
++ *
++ * X2000 UART register definition.
++ *
++ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.
++ */
++
++#ifndef __UART_H__
++#define __UART_H__
++
++#define readb(addr)     (*(volatile unsigned char *)(addr))
++#define readw(addr)     (*(volatile unsigned short *)(addr))
++#define readl(addr)     (*(volatile unsigned int *)(addr))
++#define writeb(b, addr) (*(volatile unsigned char *)(addr)) = (b)
++#define writew(b, addr) (*(volatile unsigned short *)(addr)) = (b)
++#define writel(b, addr) (*(volatile unsigned int *)(addr)) = (b)
++
++void serial_init(int);
++void serial_puts(int, const char *);
++void serial_put_hex(int, unsigned int);
++
++
++#define	UART0_BASE	0xB0030000
++
++/*************************************************************************
++ * UART
++ *************************************************************************/
++
++#define UART_BASE	UART0_BASE
++#define UART_OFF	0x1000
++
++/* Register Offset */
++#define OFF_RDR(n)		((n) * UART_OFF + 0x00)	/* R  8b H'xx */
++#define OFF_TDR(n)		((n) * UART_OFF + 0x00)	/* W  8b H'xx */
++#define OFF_DLLR(n)		((n) * UART_OFF + 0x00)	/* RW 8b H'00 */
++#define OFF_DLHR(n)		((n) * UART_OFF + 0x04)	/* RW 8b H'00 */
++#define OFF_IER(n)		((n) * UART_OFF + 0x04)	/* RW 8b H'00 */
++#define OFF_ISR(n)		((n) * UART_OFF + 0x08)	/* R  8b H'01 */
++#define OFF_FCR(n)		((n) * UART_OFF + 0x08)	/* W  8b H'00 */
++#define OFF_LCR(n)		((n) * UART_OFF + 0x0C)	/* RW 8b H'00 */
++#define OFF_MCR(n)		((n) * UART_OFF + 0x10)	/* RW 8b H'00 */
++#define OFF_LSR(n)		((n) * UART_OFF + 0x14)	/* R  8b H'00 */
++#define OFF_MSR(n)		((n) * UART_OFF + 0x18)	/* R  8b H'00 */
++#define OFF_SPR(n)		((n) * UART_OFF + 0x1C)	/* RW 8b H'00 */
++#define OFF_SIRCR(n)	((n) * UART_OFF + 0x20)	/* RW 8b H'00, UART0 */
++#define OFF_UMR(n)		((n) * UART_OFF + 0x24)	/* RW 8b H'00, UART M Register */
++#define OFF_UACR(n)		((n) * UART_OFF + 0x28)	/* RW 8b H'00, UART Add Cycle Register */
++#define OFF_URCR(n)		((n) * UART_OFF + 0x40)	/* R  8b   00, UART RXFIFO Counter Register */
++#define OFF_UTCR(n)		((n) * UART_OFF + 0x44)	/* R  8b   00, UART TXFIFO Counter Register */
++
++/*
++ * Define macros for UARTFCR
++ * UART FIFO Control Register
++ */
++#define UARTFCR_FE	(1 << 0)	/* 0: non-FIFO mode  1: FIFO mode */
++#define UARTFCR_RFLS	(1 << 1)	/* write 1 to flush receive FIFO */
++#define UARTFCR_TFLS	(1 << 2)	/* write 1 to flush transmit FIFO */
++#define UARTFCR_DMS	(1 << 3)	/* 0: disable DMA mode */
++#define UARTFCR_UUE	(1 << 4)	/* 0: disable UART */
++#define UARTFCR_RTRG	(3 << 6)	/* Receive FIFO Data Trigger */
++#define UARTFCR_RTRG_1	(0 << 6)
++#define UARTFCR_RTRG_16	(1 << 6)
++#define UARTFCR_RTRG_32	(2 << 6)
++#define UARTFCR_RTRG_60	(3 << 6)
++
++/*
++ * Define macros for UARTLCR
++ * UART Line Control Register
++ */
++#define UARTLCR_WLEN	(3 << 0)	/* word length */
++#define UARTLCR_WLEN_5	(0 << 0)
++#define UARTLCR_WLEN_6	(1 << 0)
++#define UARTLCR_WLEN_7	(2 << 0)
++#define UARTLCR_WLEN_8	(3 << 0)
++#define UARTLCR_STOP	(1 << 2)	/* 0: 1 stop bit when word length is 5,6,7,8
++					   1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
++#define UARTLCR_STOP1	(0 << 2)
++#define UARTLCR_STOP2	(1 << 2)
++#define UARTLCR_PE	(1 << 3)	/* 0: parity disable */
++#define UARTLCR_PROE	(1 << 4)	/* 0: even parity  1: odd parity */
++#define UARTLCR_SPAR	(1 << 5)	/* 0: sticky parity disable */
++#define UARTLCR_SBRK	(1 << 6)	/* write 0 normal, write 1 send break */
++#define UARTLCR_DLAB	(1 << 7)	/* 0: access UARTRDR/TDR/IER  1: access UARTDLLR/DLHR */
++
++/*
++ * Define macros for SIRCR
++ * Slow IrDA Control Register
++ */
++#define SIRCR_TSIRE	(1 << 0)  /* 0: transmitter is in UART mode  1: SIR mode */
++#define SIRCR_RSIRE	(1 << 1)  /* 0: receiver is in UART mode  1: SIR mode */
++#define SIRCR_TPWS	(1 << 2)  /* 0: transmit 0 pulse width is 3/16 of bit length
++					   1: 0 pulse width is 1.6us for 115.2Kbps */
++#define SIRCR_TDPL	(1 << 3)  /* 0: encoder generates a positive pulse for 0 */
++#define SIRCR_RDPL	(1 << 4)  /* 0: decoder interprets positive pulse as 0 */
++
++/*
++ * Define macros for UART_LSR
++ * UART Line Status Register
++ */
++#define UART_LSR_DR	(1 << 0)	/* 0: receive FIFO is empty  1: receive data is ready */
++#define UART_LSR_ORER	(1 << 1)	/* 0: no overrun error */
++#define UART_LSR_PER	(1 << 2)	/* 0: no parity error */
++#define UART_LSR_FER	(1 << 3)	/* 0; no framing error */
++#define UART_LSR_BRK	(1 << 4)	/* 0: no break detected  1: receive a break signal */
++#define UART_LSR_TDRQ	(1 << 5)	/* 1: transmit FIFO half "empty" */
++#define UART_LSR_TEMT	(1 << 6)	/* 1: transmit FIFO and shift registers empty */
++#define UART_LSR_RFER	(1 << 7)	/* 0: no receive error  1: receive error in FIFO mode */
++
++#define uart_readl(o)		readl(UART_BASE + (o))
++#define uart_writel(b, o)	writel(b, UART_BASE + (o))
++
++#endif /* __UART_H__ */
++
+diff --git a/arch/mips/xburst2/soc-m300/sleep_firmware/mkmodule.sh b/arch/mips/xburst2/soc-m300/sleep_firmware/mkmodule.sh
+new file mode 100755
+index 000000000..698e07160
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/sleep_firmware/mkmodule.sh
+@@ -0,0 +1,7 @@
++#!/bin/sh
++
++make clean
++
++make
++
++cp fastboot_resume_code.hex ../
+diff --git a/arch/mips/xburst2/soc-m300/sleep_firmware/src/fastboot_resume.c b/arch/mips/xburst2/soc-m300/sleep_firmware/src/fastboot_resume.c
+new file mode 100644
+index 000000000..a5debf77e
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/sleep_firmware/src/fastboot_resume.c
+@@ -0,0 +1,314 @@
++#include <ddr.h>
++#include <pm_fastboot.h>
++
++
++
++static struct store_regs *store_regs;
++
++
++void sys_clk_restore(void)
++{
++	unsigned int tmp;
++	struct pll_resume_reg *pll_resume_reg;
++	store_regs = (struct store_regs *)RTC_RAM_DATA_ADDR;
++
++	pll_resume_reg = &store_regs->pll_resume_reg;
++
++	tmp = *(volatile unsigned int *)0xb0000000;
++
++	tmp &= ~(7 << 20);
++	tmp |= (pll_resume_reg->cpccr & 0x000fffff);
++	*(volatile unsigned int *)0xb0000000 = tmp;
++	*(volatile unsigned int *)0xb0000000 |= (7 << 20);
++	while ((*(volatile unsigned int *)0xb00000d4) & 0x7);
++
++	tmp = *(volatile unsigned int *)0xb0000000;
++	tmp &= ~(0xff << 24);
++	tmp |= (pll_resume_reg->cpccr & 0xff000000);
++	*(volatile unsigned int *)0xb0000000 = tmp;
++
++
++	while (!((*(volatile unsigned int *)0xb00000d4 & 0xf0000000) == 0xf0000000));
++
++}
++
++
++static void pll_restore(void)
++{
++	struct pll_resume_reg *pll_resume_reg;
++	store_regs = (struct store_regs *)RTC_RAM_DATA_ADDR;
++
++	pll_resume_reg = &store_regs->pll_resume_reg;
++
++	*(volatile unsigned int *)0xb000000c = pll_resume_reg->cppcr;
++
++	*(volatile unsigned int *)0xb0000010 = (pll_resume_reg->cpapcr & 0xfffffff0) | 1;
++	while (!((*(volatile unsigned int *)0xb0000010 >> 3) & 1));
++
++	*(volatile unsigned int *)0xb0000014 = (pll_resume_reg->cpmpcr & 0xfffffff0) | 1;
++	while (!((*(volatile unsigned int *)0xb0000014 >> 3) & 1));
++
++	*(volatile unsigned int *)0xb0000018 = (pll_resume_reg->cpepcr & 0xfffffff0) | 1;
++	while (!((*(volatile unsigned int *)0xb0000018 >> 3) & 1));
++
++
++	*(volatile unsigned int *)0xb000002c = (pll_resume_reg->ddrcdr & 0xc000000f);
++	*(volatile unsigned int *)0xb000002c |= (1 << 29);
++	while (((*(volatile unsigned int *)0xb000002c) >> 28) & 1);
++
++	sys_clk_restore();
++}
++
++
++
++static void phy_pll_init(struct ddr_phy_resume_reg *ddr_phy_resume_reg)
++{
++	*(volatile unsigned int *)0xb3011084 |= (1 << 1);
++
++	*(volatile unsigned int *)0xb3010080 &= ~0xff;
++	*(volatile unsigned int *)0xb3011080 |= ddr_phy_resume_reg->pll_fbdiv;
++
++	*(volatile unsigned int *)0xb3010088 &= ~0xff;
++	*(volatile unsigned int *)0xb3011088 |= ddr_phy_resume_reg->pll_pdiv;
++
++	*(volatile unsigned int *)0xb3010084 &= ~3;
++	*(volatile unsigned int *)0xb3011084 |= (ddr_phy_resume_reg->pll_ctrl & 0x1);
++
++	*(volatile unsigned int *)0xb3011084 &= ~(1 << 1);	//enable pll
++
++	while(!(*(volatile unsigned int *)0xb30110c8 & (1 << 3)));	//wait pll lock
++}
++
++static void phy_cfg(struct ddr_phy_resume_reg *ddr_phy_resume_reg)
++{
++	*(volatile unsigned int *)0xb3011004 = ddr_phy_resume_reg->mem_cfg;
++	*(volatile unsigned int *)0xb301107c = ddr_phy_resume_reg->dq_width;
++	*(volatile unsigned int *)0xb3011014 = ddr_phy_resume_reg->cl;
++	*(volatile unsigned int *)0xb3011018 = ddr_phy_resume_reg->al;
++	*(volatile unsigned int *)0xb301101c = ddr_phy_resume_reg->cwl;
++}
++
++
++
++static void dfi_init(struct ddrc_resume_reg *ddrc_resume_reg)
++{
++	*(volatile unsigned int *)0xb3012000 &= ~(1 << 3);	//dfi_init_start = 0
++	while(!(*(volatile unsigned int *)0xb3012004 & 0x1));	//wait dfi_init_compllete
++	*(volatile unsigned int *)0xb34f0008 = ddrc_resume_reg->dcfg;
++
++}
++
++
++static void ddrc_init(struct ddrc_resume_reg *ddrc_resume_reg)
++{
++	*(volatile unsigned int *)0xb34f0040 = ddrc_resume_reg->dtimming1;
++	*(volatile unsigned int *)0xb34f0048 = ddrc_resume_reg->dtimming2;
++	*(volatile unsigned int *)0xb34f0050 = ddrc_resume_reg->dtimming3;
++	*(volatile unsigned int *)0xb34f0058 = ddrc_resume_reg->dtimming4;
++	*(volatile unsigned int *)0xb34f0060 = ddrc_resume_reg->dtimming5;
++	*(volatile unsigned int *)0xb34f0078 = ddrc_resume_reg->dmmap0;
++	*(volatile unsigned int *)0xb34f0080 = ddrc_resume_reg->dmmap1;
++	*(volatile unsigned int *)0xb34f0038 = ddrc_resume_reg->drefcnt;
++	*(volatile unsigned int *)0xb34f0010 = ddrc_resume_reg->dctrl;
++
++	*(volatile unsigned int *)0xb3012008 = ddrc_resume_reg->dremap1;
++	*(volatile unsigned int *)0xb301200c = ddrc_resume_reg->dremap2;
++	*(volatile unsigned int *)0xb3012010 = ddrc_resume_reg->dremap3;
++	*(volatile unsigned int *)0xb3012014 = ddrc_resume_reg->dremap4;
++	*(volatile unsigned int *)0xb3012018 = ddrc_resume_reg->dremap5;
++
++	*(volatile unsigned int *)0xb3012000 &= ~0x3;
++	*(volatile unsigned int *)0xb3012000 |= ddrc_resume_reg->dwcfg & 0x3;
++
++
++	*(volatile unsigned int *)0xb34f0088 = ddrc_resume_reg->dbwcfg;
++	*(volatile unsigned int *)0xb34f0090 = ddrc_resume_reg->dbwstp;
++	*(volatile unsigned int *)0xb34f00d8 = ddrc_resume_reg->hregpro;
++	*(volatile unsigned int *)0xb34f00e0 = ddrc_resume_reg->dbgen;
++	*(volatile unsigned int *)0xb301201c = ddrc_resume_reg->cpac;
++	*(volatile unsigned int *)0xb3012020 = ddrc_resume_reg->cchc0;
++	*(volatile unsigned int *)0xb3012024 = ddrc_resume_reg->cchc1;
++	*(volatile unsigned int *)0xb3012028 = ddrc_resume_reg->cchc2;
++	*(volatile unsigned int *)0xb301202c = ddrc_resume_reg->cchc3;
++	*(volatile unsigned int *)0xb3012030 = ddrc_resume_reg->cchc4;
++	*(volatile unsigned int *)0xb3012034 = ddrc_resume_reg->cchc5;
++	*(volatile unsigned int *)0xb3012038 = ddrc_resume_reg->cchc6;
++	*(volatile unsigned int *)0xb301203c = ddrc_resume_reg->cchc7;
++	*(volatile unsigned int *)0xb3012040 = ddrc_resume_reg->cschc0;
++	*(volatile unsigned int *)0xb3012044 = ddrc_resume_reg->cschc1;
++	*(volatile unsigned int *)0xb3012048 = ddrc_resume_reg->cschc2;
++	*(volatile unsigned int *)0xb301204c = ddrc_resume_reg->cschc3;
++	*(volatile unsigned int *)0xb3012050 = ddrc_resume_reg->cmonc0;
++	*(volatile unsigned int *)0xb3012054 = ddrc_resume_reg->cmonc1;
++	*(volatile unsigned int *)0xb3012058 = ddrc_resume_reg->cmonc2;
++	*(volatile unsigned int *)0xb301205c = ddrc_resume_reg->cmonc3;
++	*(volatile unsigned int *)0xb3012060 = ddrc_resume_reg->cmonc4;
++	*(volatile unsigned int *)0xb301206c = ddrc_resume_reg->pregpro;
++	*(volatile unsigned int *)0xb3012070 = ddrc_resume_reg->bufcfg ;
++
++
++}
++
++static void ddr_lp_restore(struct ddrc_resume_reg *ddrc_resume_reg)
++{
++	*(volatile unsigned int *)0xb34f0020 = ddrc_resume_reg->ddlp;
++	*(volatile unsigned int *)0xb34f0030 = ddrc_resume_reg->dasr_en;
++	*(volatile unsigned int *)0xb34f0028 = ddrc_resume_reg->dasr_cnt;
++
++}
++
++static void ddrp_auto_calibration(void)
++{
++	unsigned int reg_val = ddr_readl(DDRP_INNOPHY_TRAINING_CTRL);
++	unsigned int timeout = 0xffffff;
++	unsigned int wait_cal_done = DDRP_CALIB_DONE_HDQCFA | DDRP_CALIB_DONE_LDQCFA;
++
++	reg_val &= ~(DDRP_TRAINING_CTRL_DSCSE_BP);
++	reg_val |= DDRP_TRAINING_CTRL_DSACE_START;
++	ddr_writel(reg_val, DDRP_INNOPHY_TRAINING_CTRL);
++
++	while(!((ddr_readl(DDRP_INNOPHY_CALIB_DONE) & wait_cal_done) == wait_cal_done) && --timeout) {
++		DEBUG("t");
++	}
++
++	if(!timeout) {
++		DEBUG("f");
++	}
++	ddr_writel(0, DDRP_INNOPHY_TRAINING_CTRL);
++
++}
++
++static void ddr_init(void)
++{
++	struct ddrc_resume_reg *ddrc_resume_reg;
++	struct ddr_phy_resume_reg *ddr_phy_resume_reg;
++
++	unsigned int ddrc_ctrl;
++	volatile unsigned int tmp;
++
++	store_regs = (struct store_regs *)RTC_RAM_DATA_ADDR;
++	ddrc_resume_reg = &store_regs->ddrc_resume_reg;
++	ddr_phy_resume_reg = &store_regs->ddr_phy_resume_reg;
++
++
++//	*(volatile unsigned int *)0xb34f0010 = (0x1 << 20);	//phy reset
++	phy_cfg(ddr_phy_resume_reg);
++//	*(volatile unsigned int *)0xb34f0010 &= ~(0x1 << 20);
++
++	phy_pll_init(ddr_phy_resume_reg);
++	dfi_init(ddrc_resume_reg);
++	ddrc_init(ddrc_resume_reg);
++
++	*(volatile unsigned int *)0xb34f0030 = 0;
++	*(volatile unsigned int *)0xb34f0028 = 0;
++
++
++	{
++		ddrc_ctrl = *(volatile unsigned int *)0xb34f0010;
++
++		/* bufferen_core = 1 */
++		tmp = rtc_read_reg(0xb0003048);
++		tmp |= (1 << 21);
++		rtc_write_reg(0xb0003048, tmp);
++
++		/* exit ddr self refresh */
++		ddrc_ctrl &= ~(1<<5);
++		ddrc_ctrl |= 1 << 1;
++		*(volatile unsigned int*)0xb34f0010 = ddrc_ctrl;
++
++		while((*(volatile unsigned int *)0xb34f0000) & (1<<2));
++	}
++
++
++	DEBUG("ddr restore finish\n");
++
++	ddrp_auto_calibration();
++
++
++	ddr_lp_restore(ddrc_resume_reg);
++
++
++}
++
++
++
++static unsigned int get_resume_pc(void)
++{
++	unsigned int resume_pc;
++
++	store_regs = (struct store_regs *)RTC_RAM_DATA_ADDR;
++	resume_pc = store_regs->resume_pc;
++
++	return resume_pc;
++}
++
++unsigned int get_uart_index(void)
++{
++	unsigned int uart_index;
++
++	store_regs = (struct store_regs *)RTC_RAM_DATA_ADDR;
++	uart_index = store_regs->uart_index;
++
++	return uart_index;
++}
++
++
++
++
++void fastboot_restore_code_2(void)
++{
++	unsigned int resume_pc;
++	unsigned int uart_index;
++
++	uart_index = get_uart_index();
++#ifdef FASTBOOT_DEBUG
++	serial_init(uart_index);
++	DEBUG_HEX(uart_index);
++#endif
++
++	resume_pc = get_resume_pc();
++	DEBUG_HEX(resume_pc);
++
++	DEBUG("fastboot begin restore\n");
++
++	pll_restore();
++	DEBUG("pll restore ok\n");
++
++	ddr_init();
++
++
++	__asm__ volatile(
++			".set push      \n\t"
++			".set mips32r2  \n\t"
++			"sync       \n\t"
++			"jr.hb %0       \n\t"
++			"nop            \n\t"
++			".set pop       \n\t"
++			:
++			: "r" (resume_pc)
++			:
++			);
++
++}
++
++
++__attribute__((section(".resume"))) void fastboot_restore_code_1(void)
++{
++
++	__asm__ volatile(
++			".set push      \n\t"
++			".set noreorder      \n\t"
++			".set mips32r2  \n\t"
++			"move $29, %0   \n\t"
++			"jr.hb   %1     \n\t"
++			"nop            \n\t"
++			".set reorder      \n\t"
++			".set pop       \n\t"
++			:
++			:"r" (RTC_RAM_SP_ADDR), "r"(fastboot_restore_code_2)
++			:
++			);
++
++}
++
++
+diff --git a/arch/mips/xburst2/soc-m300/sleep_firmware/src/uart.c b/arch/mips/xburst2/soc-m300/sleep_firmware/src/uart.c
+new file mode 100644
+index 000000000..abb6a82ac
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/sleep_firmware/src/uart.c
+@@ -0,0 +1,97 @@
++#include <uart.h>
++#include <cpm.h>
++#include <gpio.h>
++
++static void serial_putc (int num, const char c)
++{
++	if (c == '\n')
++		serial_putc (num, '\r');
++
++	/* Wait for fifo to shift out some bytes */
++	while ( !((uart_readl(OFF_LSR(num)) & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60) );
++
++	uart_writel((unsigned char)c, OFF_TDR(num));
++}
++
++static void serial_setbrg(int num)
++{
++	unsigned int baud_div, tmp;
++
++	uart_writel(16, OFF_UMR(num));
++	uart_writel(0, OFF_UACR(num));
++	baud_div = 13;
++
++	tmp = uart_readl(OFF_LCR(num));
++	tmp |= UARTLCR_DLAB;
++	uart_writel(tmp, OFF_LCR(num));
++
++	uart_writel((baud_div >> 8) & 0xff, OFF_DLHR(num));
++	uart_writel(baud_div & 0xff, OFF_DLLR(num));
++
++	tmp &= ~UARTLCR_DLAB;
++	uart_writel(tmp, OFF_LCR(num));
++}
++
++void serial_init(int num)
++{
++	switch(num){
++		case 0:
++			__gpio_as_uart0();
++			__cpm_start_uart0();
++			break;
++		case 2:
++			__gpio_as_uart2();
++			__cpm_start_uart2();
++			break;
++		case 1:
++		default:
++			__gpio_as_uart1();
++			__cpm_start_uart1();
++			break;
++	}
++
++	uart_writel(0, OFF_SPR(num));
++	uart_writel(0, OFF_MCR(num));
++
++	/* Disable port interrupts while changing hardware */
++	uart_writel(0, OFF_IER(num));
++
++	/* Disable UART unit function */
++	uart_writel(~UARTFCR_UUE, OFF_FCR(num));
++
++	/* Set both receiver and transmitter in UART mode (not SIR) */
++	uart_writel(~(SIRCR_RSIRE | SIRCR_TSIRE), OFF_SIRCR(num));
++
++	/* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
++	uart_writel(UARTLCR_WLEN_8 & ~(UARTLCR_STOP2), OFF_LCR(num));
++
++	serial_setbrg(num);
++
++	/* Enable UART unit, enable and clear FIFO */
++	uart_writel(UARTFCR_UUE | UARTFCR_TFLS | UARTFCR_RFLS | UARTFCR_FE, OFF_FCR(num));
++
++}
++
++void serial_puts (int num,  const char *s)
++{
++	while (*s) {
++		serial_putc (num, *s++);
++	}
++}
++
++void serial_put_hex(int num, unsigned int  d)
++{
++	char c[12];
++	unsigned char i;
++	for(i = 0; i < 8; i++)
++	{
++		c[i] = (d >> ((7 - i) * 4)) & 0xf;
++		if(c[i] < 10)
++			c[i] += 0x30;
++		else
++			c[i] += (0x41 - 10);
++	}
++	c[8] = '\n';
++	c[9] = 0;
++	serial_puts(num, c);
++}
+diff --git a/arch/mips/xburst2/soc-m300/sleep_firmware/target.ld b/arch/mips/xburst2/soc-m300/sleep_firmware/target.ld
+new file mode 100644
+index 000000000..44f03a97a
+--- /dev/null
++++ b/arch/mips/xburst2/soc-m300/sleep_firmware/target.ld
+@@ -0,0 +1,37 @@
++OUTPUT_ARCH(mips)
++MEMORY{
++	/* TOTAL MEM :4KBytes */
++	ram   : ORIGIN = 0xb0004000 , LENGTH = 2784
++}
++
++ENTRY(fastboot_restore_code_1)
++SECTIONS
++{
++	.text : {
++		*(.resume)
++		*(.text)
++	} > ram
++
++	.data : {
++		*(.data)
++	        *(.rodata)
++	} > ram /**(.data)*/
++	.bss : {
++		. = ALIGN(4);
++			__bss_start = .;
++			*(.sbss.*)
++			*(.bss.*)
++			*(COMMON)
++		. = ALIGN(4);
++			__bss_end = .;
++	} > ram
++
++
++	/DISCARD/ : {
++		*(COMMON)
++		*(.pdri)
++		*(.comment)
++		*(.gnu.attributes)
++		*(.reginfo)
++	}
++}
+diff --git a/arch/mips/xburst2/soc-x2000/Kconfig.DT b/arch/mips/xburst2/soc-x2000/Kconfig.DT
+new file mode 100644
+index 000000000..a44823544
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/Kconfig.DT
+@@ -0,0 +1,20 @@
++choice
++	prompt "device tree select for X2000 X2100 boards"
++	depends on SOC_X2000 || SOC_X2100
++
++config DT_X2000_MODULE
++       bool "x2000 module base"
++
++config DT_HALLEY5_V20
++       bool "x2000 halley5_v20"
++
++config DT_HALLEY5_V30
++       bool "x2000 halley5_v30"
++
++config DT_KALE_V10
++       bool "x2100 kale_v10"
++
++config DT_X2000_LIFESMART_480P
++       bool "x2000 lifesmart 480p"
++
++endchoice
+diff --git a/arch/mips/xburst2/soc-x2000/Makefile b/arch/mips/xburst2/soc-x2000/Makefile
+new file mode 100644
+index 000000000..c0b63551f
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/Makefile
+@@ -0,0 +1,12 @@
++obj-y += setup.o
++obj-y += serial.o
++
++ifdef CONFIG_FASTBOOT
++obj-y += pm_fastboot.o
++else
++obj-y += pm.o
++endif
++obj-y += regs_save_restore.o
++obj-y += libdmmu.o
++obj-y += gpio.o
++obj-y += reset.o
+diff --git a/arch/mips/xburst2/soc-x2000/gpio.c b/arch/mips/xburst2/soc-x2000/gpio.c
+new file mode 100644
+index 000000000..89984c014
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/gpio.c
+@@ -0,0 +1,123 @@
++#include <linux/kernel.h>
++#include <linux/printk.h>
++#include <linux/io.h>
++#include <soc/base.h>
++#include <soc/gpio.h>
++
++#define GPIO_PORT_OFF    0x100
++#define GPIO_SHADOW_OFF  0x700
++
++#define PXPIN      0x00   /* PIN Level Register */
++#define PXINT      0x10   /* Port Interrupt Register */
++#define PXINTS     0x14   /* Port Interrupt Set Register */
++#define PXINTC     0x18   /* Port Interrupt Clear Register */
++#define PXMSK      0x20   /* Port Interrupt Mask Reg */
++#define PXMSKS     0x24   /* Port Interrupt Mask Set Reg */
++#define PXMSKC     0x28   /* Port Interrupt Mask Clear Reg */
++#define PXPAT1     0x30   /* Port Pattern 1 Set Reg. */
++#define PXPAT1S    0x34   /* Port Pattern 1 Set Reg. */
++#define PXPAT1C    0x38   /* Port Pattern 1 Clear Reg. */
++#define PXPAT0     0x40   /* Port Pattern 0 Register */
++#define PXPAT0S    0x44   /* Port Pattern 0 Set Register */
++#define PXPAT0C    0x48   /* Port Pattern 0 Clear Register */
++#define PXFLG      0x50   /* Port Flag Register */
++#define PXFLGC     0x58   /* Port Flag clear Register */
++#define PXPU       0x80   /* Port PULL-UP State Register */
++#define PXPUS      0x84   /* Port PULL-UP State Set Register */
++#define PXPUC      0x88   /* Port PULL-UP State Clear Register */
++#define PXPD       0x90   /* Port PULL-DOWN State Register */
++#define PXPDS      0x94   /* Port PULL-DOWN State Set Register */
++#define PXPDC      0x98   /* Port PULL-DOWN State Clear Register */
++
++#define PZGID2LD   0xF0   /* GPIOZ Group ID to load */
++
++#define SHADOW 5
++
++static const unsigned long gpiobase[] = {
++    [0] = (unsigned long)CKSEG1ADDR(GPIO_IOBASE + 0 * GPIO_PORT_OFF),
++    [1] = (unsigned long)CKSEG1ADDR(GPIO_IOBASE + 1 * GPIO_PORT_OFF),
++    [2] = (unsigned long)CKSEG1ADDR(GPIO_IOBASE + 2 * GPIO_PORT_OFF),
++    [3] = (unsigned long)CKSEG1ADDR(GPIO_IOBASE + 3 * GPIO_PORT_OFF),
++    [4] = (unsigned long)CKSEG1ADDR(GPIO_IOBASE + 4 * GPIO_PORT_OFF),
++
++    [SHADOW] = (unsigned long)CKSEG1ADDR(GPIO_IOBASE + GPIO_SHADOW_OFF),
++};
++
++#define GPIO_ADDR(port, reg) ((volatile unsigned long *)(gpiobase[port] + reg))
++
++static inline void gpio_write(int port, unsigned int reg, int val)
++{
++    *GPIO_ADDR(port, reg) = val;
++}
++
++static inline unsigned int gpio_read(int port, unsigned int reg)
++{
++    return *GPIO_ADDR(port, reg);
++}
++
++static void hal_gpio_port_set_func(int port, unsigned int pins, enum gpio_function func)
++{
++    /* func option */
++    if (func & 0x10) {
++        if (func & 0x8)
++            gpio_write(SHADOW, PXINTS, pins);
++        else
++            gpio_write(SHADOW, PXINTC, pins);
++
++        if (func & 0x4)
++            gpio_write(SHADOW, PXMSKS, pins);
++        else
++            gpio_write(SHADOW, PXMSKC, pins);
++
++        if (func & 0x2)
++            gpio_write(SHADOW, PXPAT1S, pins);
++        else
++            gpio_write(SHADOW, PXPAT1C, pins);
++
++        if (func & 0x1)
++            gpio_write(SHADOW, PXPAT0S, pins);
++        else
++            gpio_write(SHADOW, PXPAT0C, pins);
++
++        /* configure PzGID2LD to specify which port group to load */
++        gpio_write(SHADOW, PZGID2LD, port);
++    }
++
++    if (func & 0x80) {
++        int pull = (func >> 5) & 0x3;
++        if (pull == 0) { // no pull
++            gpio_write(port, PXPUC, pins);
++            gpio_write(port, PXPDC, pins);
++        }
++        if (pull == 1) { // pull up
++            gpio_write(port, PXPDC, pins);
++            gpio_write(port, PXPUS, pins);
++        }
++        if (pull == 2) { // pull down
++            gpio_write(port, PXPUC, pins);
++            gpio_write(port, PXPDS, pins);
++        }
++    }
++}
++
++unsigned long ingenic_pinctrl_lock(int port);
++void ingenic_pinctrl_unlock(int port, unsigned long flags);
++
++int jzgpio_set_func(int port, enum gpio_function func, unsigned long pins)
++{
++    unsigned long flags;
++
++    if (port < 0 || port > 4) {
++        printk(KERN_ERR "gpio: invalid gpio port for x2000: %d\n", port);
++        return -EINVAL;
++    }
++
++    flags = ingenic_pinctrl_lock(port);
++
++    hal_gpio_port_set_func(port, pins, func);
++
++    ingenic_pinctrl_unlock(port, flags);
++
++    return 0;
++}
++EXPORT_SYMBOL(jzgpio_set_func);
+diff --git a/arch/mips/xburst2/soc-x2000/include/cpu-feature-overrides.h b/arch/mips/xburst2/soc-x2000/include/cpu-feature-overrides.h
+new file mode 100644
+index 000000000..46e526d6f
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/include/cpu-feature-overrides.h
+@@ -0,0 +1,66 @@
++/*
++ *  Copyright (C) 2008 Ingenic Semiconductor Inc.
++ *
++ *  Author: <zpzhong@ingenic.cn>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_INGENIC_CPU_FEATURE_OVERRIDES_H__
++#define __ASM_MACH_INGENIC_CPU_FEATURE_OVERRIDES_H__
++
++
++#define cpu_dcache_size()       	(32 * 1024)
++#define cpu_dcache_ways()       	8
++#define cpu_dcache_line_size()  	32
++#define cpu_icache_size()       	(32 * 1024)
++#define cpu_icache_ways()       	8
++#define cpu_icache_line_size()  	32
++#define cpu_has_xpa			0
++#define cpu_has_tlb                     1
++#define cpu_has_tlbinv                  1
++#define cpu_has_4kex                    1
++#define cpu_has_3k_cache                0
++#define cpu_has_4k_cache                1
++#define cpu_has_tx39_cache              0
++#define cpu_has_fpu                     1
++#define cpu_has_32fpr                   0
++#define cpu_has_counter                 0
++#define cpu_has_watch                   1
++#define cpu_has_divec                   1
++#define cpu_has_vce                     0
++#define cpu_has_cache_cdex_p            0
++#define cpu_has_cache_cdex_s            0
++#define cpu_has_prefetch                1
++#define cpu_has_mcheck                  1
++#define cpu_has_ejtag                   0
++#define cpu_has_llsc                    1
++#define kernel_uses_llsc		cpu_has_llsc
++#define cpu_has_mips16                  0
++#define cpu_has_mdmx                    0
++#define cpu_has_mips3d                  0
++#define cpu_has_smartmips               0
++#define cpu_has_vtag_icache             0
++#define cpu_has_dc_aliases              0
++#define cpu_has_ic_fills_f_dc           0
++#define cpu_has_pindexed_dcache         0
++#define cpu_icache_snoops_remote_store  0
++#define cpu_has_mips32r1                0
++#define cpu_has_mips32r2                1
++#define cpu_has_mips64r1                0
++#define cpu_has_mips64r2                0
++#define cpu_has_dsp                     0
++#define cpu_has_mipsmt                  0
++#define cpu_has_userlocal               1
++#define cpu_has_rixi                    1
++#define cpu_has_nofpuex                 0
++#define cpu_has_64bits                  0
++#define cpu_has_64bit_zero_reg          0
++#define cpu_has_vint                    0
++#define cpu_has_veic                    0
++#define cpu_has_inclusive_pcaches       0
++#define kernel_uses_smartmips_rixi      0
++#define cpu_has_mxu                     0
++#endif
+diff --git a/arch/mips/xburst2/soc-x2000/include/irq.h b/arch/mips/xburst2/soc-x2000/include/irq.h
+new file mode 100644
+index 000000000..0c1410546
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/include/irq.h
+@@ -0,0 +1,39 @@
++/*
++ *  Copyright (C) 2010 Ingenic Semiconductor Inc.
++ *
++ *  Author: <zpzhong@ingenic.cn>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_INGENIC_IRQ_H__
++#define __ASM_MACH_INGENIC_IRQ_H__
++#include <irq_cpu.h>
++#include <dt-bindings/interrupt-controller/mips-irq.h>
++
++enum {
++#define GPIO_NR_IRQS	(32 * 5 + 16)
++	IRQ_GPIO_BASE = (IRQ_INTC_END + 1),
++	IRQ_GPIO_END = IRQ_GPIO_BASE + GPIO_NR_IRQS - 1,
++
++#define TCU_NR_IRQS	(8)
++	IRQ_TCU_BASE,
++	IRQ_TCU_END = IRQ_TCU_BASE + TCU_NR_IRQS - 1,
++
++#define MCU_NR_IRQS    (5)
++	IRQ_MCU_BASE,
++	IRQ_MCU_END = IRQ_MCU_BASE + MCU_NR_IRQS - 1,
++
++#define RESERVED_NR_IRQS       (150)
++	IRQ_RESERVED_BASE,
++	IRQ_RESERVED_END = IRQ_RESERVED_BASE + RESERVED_NR_IRQS - 1,
++
++	NR_IRQS,
++
++
++
++};
++
++#endif
+diff --git a/arch/mips/xburst2/soc-x2000/include/libdmmu.h b/arch/mips/xburst2/soc-x2000/include/libdmmu.h
+new file mode 100644
+index 000000000..6e0fbdb42
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/include/libdmmu.h
+@@ -0,0 +1,30 @@
++#ifndef _LIBDMMU_
++#define _LIBDMMU_
++
++#include <linux/device.h>
++
++
++struct dmmu_mm_ops {
++	int (*mm_release)(void *data);
++};
++
++struct dmmu_mm_notifier {
++
++	struct device *dev;
++	void *data;
++	struct list_head list;
++
++	struct dmmu_mm_ops *ops;
++};
++
++int dmmu_register_mm_notifier(struct dmmu_mm_notifier *dmn);
++
++unsigned long dmmu_map(struct device *dev,unsigned long vaddr,unsigned long len);
++int dmmu_flush_cache(unsigned long vaddr, unsigned long len);
++int dmmu_unmap(struct device *dev,unsigned long vaddr, int len);
++int dmmu_unmap_all(struct device *dev);
++void dmmu_dump_vaddr(unsigned long vaddr);
++int dmmu_memory_smash(unsigned long vaddr, int smash_mode);
++int dmmu_dump_map(unsigned long vaddr);
++
++#endif
+diff --git a/arch/mips/xburst2/soc-x2000/include/soc/base.h b/arch/mips/xburst2/soc-x2000/include/soc/base.h
+new file mode 100644
+index 000000000..1b7d3d130
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/include/soc/base.h
+@@ -0,0 +1,77 @@
++
++#ifndef __JZSOC_SOC_DEV_H__
++#define __JZSOC_SOC_DEV_H__
++
++/*
++ * Define the module base addresses
++ */
++
++/* AHB0 BUS Devices Base */
++#define HARB0_IOBASE	0x13000000 /* 64KB, AHB Bus Aribtier */
++#define DDR_PHY_IOBASE	0x13011000 /* 4KB, DDR PHY */
++#define DDRC_H0_IOBASE	0x13012000 /* 4KB, DDR Controller Registers@ASHB0 */
++#define DPU_IOBASE	0x13050000 /* 64KB, LCD Controller */
++#define CIM_IOBASE	0x13060000 /* 64KB, Camera Interface Module */
++#define ROTATE_IOBASE	0x13070000 /* 64KB, Rotate DMA */
++#define JPEG_IOBASE	0x130d0000 /* 64KB, VPU-JPEG  */
++
++
++/* AHB2 Bus Devices Base */
++#define HARB2_IOBASE	0x13400000 /* 64KB, AHB Bus Arbiter */
++#define NEMC_IOBASE	0x13410000 /* 64KB, External Normal Memory/Boot ROM/OTP Controller */
++#define PDMA_IOBASE	0x13420000 /* 64KB, Programmable DMA Controller */
++#define AES_IOBASE	0x13430000 /* 64KB, AES */
++#define SFC_IOBASE	0x13440000 /* 64KB, SPI Flash Controller */
++#define MSC0_IOBASE	0x13450000 /* 64KB, MMC SD Controller0 */
++#define MSC1_IOBASE	0x13460000 /* 64KB, MMC SD Controller1 */
++#define HASH_IOBASE	0x13470000 /* 64KB, HASH */
++#define MAC_IOBASE	0x134b0000 /* 64KB, GMAC/MAC */
++#define PWM_IOBASE	0x134c0000 /* 64KB, PWM */
++#define DDRC_H2_IOBASE	0x134f0000 /* 4KB, DDR Controller Register @AHB2 */
++#define AUDIO_IOBASE	0x134e0000 /* 64KB, Aduio System */
++#define OTG_IOBASE	0x13500000 /* 256KB, OTG2.0 Controller */
++#define EFUSE_IOBASE	0x13540000 /* 64KB, EFUSE */
++//#define INTC_IOBASE	0x135f0000 /* Interrupt Controller */ /* TODO: to be fix */
++
++
++/* APB BUS Devices Base */
++#define CPM_IOBASE	0x10000000 /* 4KB, Clocks and Power Manager */
++#define TCU_IOBASE	0x10002000 /* 4KB, Timer/Count Unit,OperatingSystemTimer,Watchdog Timer */
++#define WDT_IOBASE	TCU_IOBASE /* 4KB, Timer/Count Unit,OperatingSystemTimer,Watchdog Timer */
++
++#define RTC_IOBASE	0x10003000 /* 4KB, Real-Time Clock */
++#define GPIO_IOBASE	0x10010000 /* 4KB, General-Purpose I/O */
++#define	UART0_IOBASE	0x10030000 /* 4KB, UART0 Controller */
++#define	UART1_IOBASE	0x10031000 /* 4KB, UART1 Controller */
++#define	UART2_IOBASE	0x10032000 /* 4KB, UART2 Controller */
++#define	UART3_IOBASE	0x10033000 /* 4KB, UART3 Controller */
++#define	UART4_IOBASE	0x10034000 /* 4KB, UART4 Controller */
++#define	UART5_IOBASE	0x10035000 /* 4KB, UART4 Controller */
++#define SCC_IOBASE	0x10040000 /* 4KB, Smart Card Controller */
++#define SSI0_IOBASE	0x10043000 /* 4KB, Synchronous Serial Interface */
++#define SSI1_IOBASE	0x10044000 /* 4KB, Synchronous Serial Interface */
++#define I2C0_IOBASE	0x10050000 /* 4KB, I2C 0 Bus Interface */
++#define I2C1_IOBASE	0x10051000 /* 4KB, I2C 1 Bus Interface */
++#define I2C2_IOBASE	0x10052000 /* 4KB, I2C 2 Bus Interface */
++#define I2C3_IOBASE	0x10053000 /* 4KB, I2C 3 Bus Interface */
++#define I2C4_IOBASE	0x10054000 /* 4KB, I2C 4 Bus Interface */
++#define I2C5_IOBASE	0x10055000 /* 4KB, I2C 5 Bus Interface */
++
++
++
++/* TODO: Others To Be add */
++/* NAND CHIP Base Address */
++#define NEMC_CS1_IOBASE 0X1b000000
++#define NEMC_CS2_IOBASE 0X1a000000
++#define NEMC_CS3_IOBASE 0X19000000
++#define NEMC_CS4_IOBASE 0X18000000
++#define NEMC_CS5_IOBASE 0X17000000
++#define NEMC_CS6_IOBASE 0X16000000
++
++
++#define	OST_IOBASE	0x12000000
++#define	TCU_IOBASE	0x10002000
++
++#define DDRC_BASE       0xb34f0000
++
++#endif
+diff --git a/arch/mips/xburst2/soc-x2000/include/soc/cache.h b/arch/mips/xburst2/soc-x2000/include/soc/cache.h
+new file mode 100644
+index 000000000..249e4230a
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/include/soc/cache.h
+@@ -0,0 +1,73 @@
++#ifndef __CHIP_CACHE_H__
++#define __CHIP_CACHE_H__
++#include <asm/cacheops.h>
++#include <asm/r4kcache.h>
++
++#define Index_Prefetch_I        0x1c
++
++
++#define cache_prefetch(label,size)					\
++do{									\
++	unsigned long addr,end;						\
++	/* Prefetch codes from label */					\
++	addr = (unsigned long)(&&label) & ~(32 - 1);			\
++	end = (unsigned long)(&&label + size) & ~(32 - 1);		\
++	end += 32;							\
++	for (; addr < end; addr += 32) {				\
++		__asm__ volatile (					\
++				".set push       \n\t"			\
++				".set mips32     \n\t"			\
++				" cache %0, 0(%1)\n\t"			\
++				".set pop        \n\t"			\
++				:					\
++				: "I" (Index_Prefetch_I), "r"(addr));	\
++	}								\
++}									\
++while(0)
++
++#define K0BASE			KSEG0
++#define CFG_DCACHE_SIZE		32768
++#define CFG_ICACHE_SIZE		32768
++#define CFG_CACHELINE_SIZE	32
++
++#define CFG_SDCACHE_SIZE	(512*1024)
++#define CFG_SDCACHELINE_SIZE	64
++
++static inline void __jz_flush_cache_all(void)
++{
++	register unsigned long addr;
++	/* Clear CP0 TagLo */
++	for (addr = K0BASE; addr < (K0BASE + CFG_DCACHE_SIZE); addr += CFG_CACHELINE_SIZE) {
++		asm volatile (".set mips32\n\t"
++					  " cache %0, 0(%1)\n\t"
++					  ".set mips32\n\t"
++					  :
++					  : "I" (Index_Writeback_Inv_D), "r"(addr));
++	}
++
++	for (addr = K0BASE; addr < (K0BASE + CFG_ICACHE_SIZE); addr += CFG_CACHELINE_SIZE) {
++		asm volatile (".set mips32\n\t"
++					  " cache %0, 0(%1)\n\t"
++					  ".set mips32\n\t"
++					  :
++					  : "I" (Index_Invalidate_I), "r"(addr));
++	}
++
++	asm volatile ("sync\n\t"
++				  "lw $0,0(%0)"
++				  ::"r" (0xa0000000));
++	/* 2nd cache */
++	for (addr = K0BASE; addr < (K0BASE + CFG_SDCACHE_SIZE); addr += CFG_SDCACHELINE_SIZE) {
++		asm volatile (".set mips32\n\t"
++					  " cache %0, 0(%1)\n\t"
++					  ".set mips32\n\t"
++					  :
++					  : "I" (Index_Writeback_Inv_SD), "r"(addr));
++	}
++
++	asm volatile ("sync\n\t"
++				  "lw $0,0(%0)"
++				  ::"r" (0xa0000000));
++}
++
++#endif /* __CHIP_CACHE_H__ */
+diff --git a/arch/mips/xburst2/soc-x2000/include/soc/cpm.h b/arch/mips/xburst2/soc-x2000/include/soc/cpm.h
+new file mode 100644
+index 000000000..3efdc80e1
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/include/soc/cpm.h
+@@ -0,0 +1,136 @@
++/*
++ * SOC CPM register definition.
++ *
++ * CPM (Clock reset and Power control Management)
++ *
++ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.
++ */
++
++#ifndef __SOC_CPM_H__
++#define __SOC_CPM_H__
++
++#include <soc/base.h>
++
++#define CPM_CPCCR		(0x00)
++#define CPM_CPCSR		(0xD4)
++
++#define CPM_DDRCDR		(0x2c)
++#define CPM_MACCDR		(0x54)
++#define CPM_MACTXCDR		(0x58)
++#define CPM_MACTXCDR1		(0xdc)
++#define CPM_MACPTP		(0x4c)
++#define CPM_I2S0CDR		(0x60)
++#define CPM_I2S1CDR		(0x7c)
++#define CPM_I2S2CDR		(0x84)
++#define CPM_I2S3CDR		(0x8c)
++#define CPM_I2S0CDR1		(0x70)
++#define CPM_I2S1CDR1		(0x80)
++#define CPM_I2S2CDR1		(0x88)
++#define CPM_I2S3CDR1		(0xa0)
++#define CPM_AUDIOCR		(0xac)
++#define CPM_LPCDR		(0x64)
++#define CPM_MSC0CDR		(0x68)
++#define CPM_MSC1CDR		(0xa4)
++#define CPM_MSC2CDR		(0xa8)
++#define CPM_SFCCDR		(0x74)
++#define CPM_SSICDR		(0x5c)
++#define CPM_CIMCDR		(0x78)
++#define CPM_PWMCDR		(0x6c)
++#define CPM_ISPCDR		(0x30)
++#define CPM_RSACDR		(0x50)
++
++#define CPM_INTR		(0xB0)
++#define CPM_INTRE		(0xB4)
++#define CPM_SFTINT		(0xBC)
++#define CPM_DRCG		(0xD0)
++#define CPM_CPPSR		(0x34)
++#define CPM_CPSPPR		(0x38)
++#define CPM_USBPCR		(0x3C)
++#define CPM_USBRDT		(0x40)
++#define CPM_USBVBFIL		(0x44)
++#define CPM_USBPCR1		(0x48)
++
++#define CPM_CPPCR		(0x0C)
++#define CPM_CPAPCR		(0x10)
++#define CPM_CPMPCR		(0x14)
++#define CPM_CPEPCR		(0x18)
++
++#define CPM_LCR			(0x04)
++#define CPM_PSWC0ST		(0x90)
++#define CPM_PSWC1ST		(0x94)
++#define CPM_PSWC2ST		(0x98)
++#define CPM_PSWC3ST		(0x9C)
++#define CPM_CLKGR		(0x20)
++#define CPM_CLKGR1		(0x28)
++#define CPM_MESTSEL		(0xEC)
++#define CPM_SRBC		(0xC4)
++#define CPM_EXCLK_DS		(0xE0)
++#define CPM_MPDCR		(0xF8)
++#define CPM_MPDCR1		(0xFC)
++#define CPM_SLBC		(0xC8)
++#define CPM_SLPC		(0xCC)
++#define CPM_OPCR		(0x24)
++#define CPM_RSR			(0x08)
++
++#ifndef BIT
++#define BIT(nr)  (1UL << nr)
++#endif
++
++/*USB Parameter Control Register*/
++#define USBPCR_USB_MODE                 BIT(31)
++#define USBPCR_AVLD_REG                 BIT(30)
++#define USBPCR_IDPULLUP_MASK_BIT        28
++#define USBPCR_IDPULLUP_MASK		(0x3 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_IDPULLUP_OTG             (0x0 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_IDPULLUP_ALWAYS_SUSPEND  (0x1 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_IDPULLUP_ALWAYS          (0x2 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_INCR_MASK                BIT(27)
++#define USBPCR_POR_BIT                  22
++#define USBPCR_POR                      BIT(USBPCR_POR_BIT)
++
++/*USB Reset Detect Timer Register*/
++#define USBRDT_RESUME_INTEEN		BIT(31)	/*RW*/
++#define USBRDT_RESUME_INTERCLR		BIT(30)	/*W0*/
++#define USBRDT_RESUME_SPEED_BIT		28	/*RW*/
++#define USBRDT_RESUME_SPEED_MSK		(0x3 << USBRDT_RESUME_SPEED_BIT)
++#define USBRDT_RESUME_SPEED_HIGH	(0x0 << USBRDT_RESUME_SPEED_BIT)
++#define USBRDT_RESUME_SPEED_FULL	(0x1 << USBRDT_RESUME_SPEED_BIT)
++#define USBRDT_RESUME_SPEED_LOW		(0x2 << USBRDT_RESUME_SPEED_BIT)
++#define USBRDT_RESUME_STATUS		BIT(27)	/*RO*/
++#define USBRDT_HB_MASK                  BIT(26)
++#define USBRDT_VBFIL_LD_EN              BIT(25)
++#define USBRDT_IDDIG_EN                 BIT(24)
++#define USBRDT_IDDIG_REG                BIT(23)
++#define USBRDT_USBRDT_MSK               (0x7fffff)
++#define USBRDT_USBRDT(x)                ((x) & USBRDT_USBRDT_MSK)
++
++/*USB VBUS Jitter Filter Register*/
++#define USBVBFIL_USBVBFIL(x)		((x) & 0xffff)
++#define USBVBFIL_IDDIGFIL(x)		((x) & (0xffff << 16))
++
++/*USB Parameter Control Register1*/
++#define USBPCR1_BVLD_REG        BIT(31)
++#define USBPCR1_DPPULLDOWN	BIT(29)
++#define USBPCR1_DMPULLDOWN	BIT(28)
++#define USBPCR1_PORT_RST	BIT(21)
++
++/*Oscillator and Power Control Register*/
++#define OPCR_USB_SPENDN		BIT(7)
++#define OPCR_USB_PHY_GATE	BIT(23)
++
++
++#define LCR_LPM_MASK		(0x3)
++#define LCR_LPM_SLEEP		(0x1)
++
++#define OPCR_ERCS		(0x1<<2)
++#define OPCR_PD			(0x1<<3)
++#define OPCR_IDLE		(0x1<<31)
++
++
++#define cpm_inl(off)		inl(CPM_IOBASE + (off))
++#define cpm_outl(val,off)	outl(val,CPM_IOBASE + (off))
++#define cpm_clear_bit(val,off)	do{cpm_outl((cpm_inl(off) & ~(1<<(val))),off);}while(0)
++#define cpm_set_bit(val,off)	do{cpm_outl((cpm_inl(off) |  (1<<val)),off);}while(0)
++#define cpm_test_bit(val,off)	(cpm_inl(off) & (0x1<<val))
++
++#endif
+diff --git a/arch/mips/xburst2/soc-x2000/include/soc/ddr.h b/arch/mips/xburst2/soc-x2000/include/soc/ddr.h
+new file mode 100644
+index 000000000..4cbb89b1e
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/include/soc/ddr.h
+@@ -0,0 +1,293 @@
++/*
++ * JZ4780 ddr definitions
++ *
++ * Copyright (c) 2013 Ingenic Semiconductor Co.,Ltd
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __DDR_H__
++#define __DDR_H__
++
++#include <soc/base.h>
++
++/*
++ * DDR Controller Registers
++ **/
++#define DDR_MEM_PHY_BASE		0x20000000
++
++#define DDRC_AHB2_OFFSET	0xb34f0000
++#define DDRC_APB_OFFSET		0xb3012000
++#define DDR_PHY_OFFSET  (-0x4e0000 + 0x1000)
++
++#define DDRC_STATUS		0x0
++#define DDRC_CFG		0x8
++#define DDRC_CTRL		0x10
++#define DDRC_LMR		0x18
++#define DDRC_DLP		0x20
++#define DDRC_AUTOSR_EN	0x28
++#define DDRC_AUTOSR_CNT	0x30
++#define DDRC_REFCNT		0x38
++#define DDRC_DBGINFO	0xE8
++#define DDRC_TIMING(n)	(0x40 + 8 * (n - 1))
++#define DDRC_MMAP0		0x78
++#define DDRC_MMAP1		0x80
++#define DDRC_HREGPRO	0xd8
++#define DDRC_DWCFG		(DDRC_APB_OFFSET + 0x00)
++#define DDRC_DWSTATUS	(DDRC_APB_OFFSET + 0x04)
++#define DDRC_REMAP(n)	(DDRC_APB_OFFSET + 0x08 + 4 * (n - 1))
++#define DDRC_CGUC0		(DDRC_APB_OFFSET + 0x64)
++#define DDRC_CGUC1		(DDRC_APB_OFFSET + 0x68)
++#define DDRC_PREGPRO	(DDRC_APB_OFFSET + 0x6c)
++
++/*
++ * DDR Innophy registers
++ * */
++#define DDRP_INNOPHY_PHY_RST			(DDR_PHY_OFFSET + 0x000)
++#define DDRP_INNOPHY_MEM_CFG			(DDR_PHY_OFFSET + 0x004)
++#define DDRP_INNOPHY_DQ_WIDTH			(DDR_PHY_OFFSET + 0x07c)
++#define DDRP_INNOPHY_CL					(DDR_PHY_OFFSET + 0x014)
++#define DDRP_INNOPHY_CWL				(DDR_PHY_OFFSET + 0x01c)
++#define DDRP_INNOPHY_AL					(DDR_PHY_OFFSET + 0x018)
++#define DDRP_INNOPHY_PLL_FBDIV			(DDR_PHY_OFFSET + 0x080)
++#define DDRP_INNOPHY_PLL_CTRL			(DDR_PHY_OFFSET + 0x084)
++#define DDRP_INNOPHY_PLL_PDIV			(DDR_PHY_OFFSET + 0x088)
++#define DDRP_INNOPHY_PLL_LOCK			(DDR_PHY_OFFSET + 0xc8)
++#define DDRP_INNOPHY_TRAINING_CTRL		(DDR_PHY_OFFSET + 0x008)
++#define DDRP_INNOPHY_CALIB_DONE			(DDR_PHY_OFFSET + 0xcc)
++#define DDRP_INNOPHY_CALIB_DELAY_AL		(DDR_PHY_OFFSET + 0x190)
++#define DDRP_INNOPHY_CALIB_DELAY_AH		(DDR_PHY_OFFSET + 0x194)
++#define DDRP_INNOPHY_CALIB_BYPASS_AL	(DDR_PHY_OFFSET + 0x118)
++#define DDRP_INNOPHY_CALIB_BYPASS_AH	(DDR_PHY_OFFSET + 0x158)
++#define DDRP_INNOPHY_WL_MODE1			(DDR_PHY_OFFSET + 0x00c)
++#define DDRP_INNOPHY_WL_MODE2			(DDR_PHY_OFFSET + 0x010)
++#define DDRP_INNOPHY_WL_DONE			(DDR_PHY_OFFSET + 0x0c0)
++#define DDRP_INNOPHY_INIT_COMP			(DDR_PHY_OFFSET + 0x0d0)
++
++
++/*
++ * DDRC REGISTER BITS DEFINE
++ * */
++
++/* DDRC Status Register */
++#define DDRC_DSTATUS_MISS	(1 << 6)
++#define DDRC_ST_DPDN		(1 << 5) /* 0 DDR memory is NOT in deep-power-down state
++										1 DDR memory is in deep-power-down state */
++#define DDRC_ST_PDN		(1 << 4) /* 0 DDR memory is NOT in power-down state
++									1 DDR memory is in power-down state */
++#define DDRC_ST_AREF		(1 << 3) /* 0 DDR memory is NOT in auto-refresh state
++										1 DDR memory is in auto-refresh state */
++#define DDRC_ST_SREF		(1 << 2) /* 0 DDR memory is NOT in self-refresh state
++										1 DDR memory is in self-refresh state */
++#define DDRC_ST_CKE1		(1 << 1) /* 0 CKE1 Pin is low
++										1 CKE1 Pin is high */
++#define DDRC_ST_CKE0		(1 << 0) /* 0 CKE0 Pin is low
++										1 CKE0 Pin is high */
++
++/* DDRC Configure Register */
++#define DDRC_CFG_ROW1_BIT	29 /* Row Address width. */
++#define DDRC_CFG_ROW1_MASK	(0x7 << DDRC_CFG_ROW1_BIT)
++#define DDRC_CFG_COL1_BIT	26 /* Row Address width. */
++#define DDRC_CFG_COL1_MASK	(0x7 << DDRC_CFG_COL1_BIT)
++#define DDRC_CFG_BA1		25 /* Bank Address width of DDR memory */
++#define DDRC_CFG_IMBA		(1 << 16)
++#define DDRC_CFG_ROW0_BIT	13 /* Row Address width. */
++#define DDRC_CFG_ROW0_MASK	(0x7 << DDRC_CFG_ROW0_BIT)
++#define DDRC_CFG_COL0_BIT	10 /* Row Address width. */
++#define DDRC_CFG_COL0_MASK	(0x7 << DDRC_CFG_COL1_BIT)
++#define DDRC_CFG_BA0		9 /* Bank Address width of DDR memory */
++
++#define DDRC_CFG_TYPE_BIT	3
++#define DDRC_CFG_TYPE_MASK	(0x7 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR1	(2 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_MDDR	(3 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR2	(4 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_LPDDR2	(5 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR3	(6 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_LPDDR3	(7 << DDRC_CFG_TYPE_BIT)
++
++#define DDRC_CFG_ODTEN		(1 << 2)  /* ODT EN */
++#define DDRC_CFG_CS1EN		(1 << 1)  /* DDR Chip-Select-1 Enable */
++#define DDRC_CFG_CS0EN		(1 << 0)  /* DDR Chip-Select-0 Enable */
++
++/* DDRC Control Register */
++#define DDRC_CTRL_DFI_RST	(1 << 23)
++#define DDRC_CTRL_DLL_RST	(1 << 22)
++#define DDRC_CTRL_CTL_RST	(1 << 21)
++#define DDRC_CTRL_CFG_RST	(1 << 20)
++#define DDRC_CTRL_ACTPD		(1 << 15) /* 0 Precharge all banks before entering power-down
++										 1 Do not precharge banks before entering power-down */
++#define DDRC_CTRL_PDT_BIT	12 /* Power-Down Timer */
++#define DDRC_CTRL_PDT_MASK	(0x7 << DDRC_CTRL_PDT_BIT)
++#define DDRC_CTRL_PDT_DIS	(0 << DDRC_CTRL_PDT_BIT) /* power-down disabled */
++#define DDRC_CTRL_PDT_8		(1 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 8 tCK idle */
++#define DDRC_CTRL_PDT_16	(2 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 16 tCK idle */
++#define DDRC_CTRL_PDT_32	(3 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 32 tCK idle */
++#define DDRC_CTRL_PDT_64	(4 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 64 tCK idle */
++#define DDRC_CTRL_PDT_128	(5 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 128 tCK idle */
++
++#define DDRC_CTRL_PD_CCE	(1 << 7) /* Power down clk freq change enable */
++#define DDRC_CTRL_DPD		(1 << 6) /* 1 Drive external MDDR device entering Deep-Power-Down mode */
++#define DDRC_CTRL_SR		(1 << 5) /* 1 Drive external DDR device entering self-refresh mode
++										0 Drive external DDR device exiting self-refresh mode */
++#define DDRC_CTRL_SR_CCE	(1 << 4) /* Self refresh clk stop request enable */
++#define DDRC_CTRL_CKE		(1 << 1) /* 0 Not set CKE Pin High, 1 Set CKE Pin HIGH */
++#define DDRC_CTRL_RESET		(1 << 0) /* 0 End resetting ddrc_controller, 1 Resetting ddrc_controller */
++
++/* DDRC DFI low power handshake control register */
++#define DDRC_DDLP_TCTLUDP_BIT	24
++#define DDRC_DDLP_TCTLUDP_FF	(0xff << DDRC_DDLP_TCTLUDP_BIT)
++
++/* DDRC Load-Mode-Register */
++#define DDRC_LMR_DDR_ADDR_BIT	12 /* When performing a DDR command, DDRC_ADDR[13:0]
++									  corresponding to external DDR address Pin A[13:0] */
++#define DDRC_LMR_DDR_ADDR_MASK	(0xfffff << DDRC_LMR_DDR_ADDR_BIT)
++
++#define DDRC_LMR_MA_BIT		16 /* FOR LPDDR2, MA[9:0] */
++#define DDRC_LMR_OP_BIT		24 /* FOR LPDDR2, OP[9:0] */
++
++#define DDRC_LMR_BA_BIT		9 /* When performing a DDR command, BA[2:0]
++								 corresponding to external DDR address Pin BA[2:0]. */
++#define DDRC_LMR_BA_MASK	(0x7 << DDRC_LMR_BA_BIT)
++#define DDRC_LMR_CMD_BIT	6
++#define DDRC_LMR_CMD_MASK	(0x7 << DDRC_LMR_CMD_BIT)
++#define DDRC_LMR_CMD_PREC	(0 << DDRC_LMR_CMD_BIT)/* Precharge one bank/All banks */
++#define DDRC_LMR_CMD_AUREF	(1 << DDRC_LMR_CMD_BIT)/* Auto-Refresh */
++#define DDRC_LMR_CMD_LMR	(2 << DDRC_LMR_CMD_BIT)/* Load Mode Register */
++#define DDRC_LMR_CMD_ZQCL_CS0	(3 << DDRC_LMR_CMD_BIT)/* ZQCL for DDR3 on CS0 */
++#define DDRC_LMR_CMD_ZQCL_CS1	(4 << DDRC_LMR_CMD_BIT)/* ZQCL for DDR3 on CS1 */
++#define DDRC_LMR_CMD_ZQCS_CS0	(5 << DDRC_LMR_CMD_BIT)/* ZQCS for DDR3 on CS0 */
++#define DDRC_LMR_CMD_ZQCS_CS1	(6 << DDRC_LMR_CMD_BIT)/* ZQCS for DDR3 on CS1 */
++
++#define DDRC_LMR_TMRD_BIT	1
++#define DDRC_LMR_TMRD_MASK	(0x1f << DDRC_LMR_TMRD_BIT)
++#define DDRC_LMR_START		(1 << 0) /* 0 No command is performed
++										1 On the posedge of START, perform a command
++										defined by CMD field */
++
++/* DDRC  Auto-Refresh Counter */
++#define DDRC_REFCNT_REF_EN		(1 << 0) /* Enable Refresh Counter */
++#define DDRC_REFCNT_CLK_DIV_BIT		1  /* Clock Divider for auto-refresh counter. */
++#define DDRC_REFCNT_CLK_DIV_MASK	(0x7 << DDRC_REFCNT_CLKDIV_BIT)
++
++#define DDRC_REFCNT_PREREF_CNT_BIT	4
++#define DDRC_REFCNT_PREREF_CNT_MASK	(0xf << DDRC_REFCNT_PREREF_CNT_BIT)
++#define DDRC_REFCNT_PREREF_CNT(val)	(val << DDRC_REFCNT_PREREF_CNT_BIT)
++#define DDRC_REFCNT_PREREF_CNT_DEFAULT	DDRC_REFCNT_PREREF_CNT(8)
++
++#define DDRC_REFCNT_CNT_BIT		8  /* 8-bit counter */
++#define DDRC_REFCNT_CNT_MASK		(0xff << DDRC_REFCNT_CNT_BIT)
++
++#define DDRC_REFCNT_CON_BIT		16 /* Constant value used to compare with CNT value. */
++#define DDRC_REFCNT_CON_MASK		(0xff << DDRC_REFCNT_CON_BIT)
++
++#define DDRC_REFCNT_TRFC_BIT		24
++#define DDRC_REFCNT_TRFC_MASK		(0x3f << DDRC_REFCNT_TRFC_BIT)
++
++#define DDRC_REFCNT_PREREF_EN_BIT	30
++#define DDRC_REFCNT_PREREF_EN		(1 << DDRC_REFCNT_PREREF_EN_BIT)
++
++#define DDRC_REFCNT_PBREF_EN_BIT	31
++#define DDRC_REFCNT_PBREF_EN		(1 << DDRC_REFCNT_PBREF_EN_BIT)
++
++/* DDRC Memory Map Config Register */
++#define DDRC_MMAP_BASE_BIT		8 /* base address */
++#define DDRC_MMAP_BASE_MASK		(0xff << DDRC_MMAP_BASE_BIT)
++#define DDRC_MMAP_MASK_BIT		0 /* address mask */
++#define DDRC_MMAP_MASK_MASK		(0xff << DDRC_MMAP_MASK_BIT)
++
++#define DDRC_MMAP0_BASE			(0x20 << DDRC_MMAP_BASE_BIT)
++#define DDRC_MMAP1_BASE_64M		(0x24 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++#define DDRC_MMAP1_BASE_128M		(0x28 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++#define DDRC_MMAP1_BASE_256M		(0x30 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++
++#define DDRC_MMAP_MASK_64_64		(0xfc << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++#define DDRC_MMAP_MASK_128_128		(0xf8 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++#define DDRC_MMAP_MASK_256_256		(0xf0 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++
++/* DDR device data width configure register */
++#define DDRC_DWCFG_DFI_INIT_START	(1 << 3)
++
++/* DDR device status register */
++#define DDRC_DWSTATUS_DFI_INIT_COMP	(1 << 0)
++
++/* DDRC AHB Bus Register Protection Register */
++#define DDRC_HREGPRO_HPRO_EN		(1 << 0)
++
++/* DDRC APB Bus Register Protection Register */
++#define DDRC_PREGPRO_PPRO_EN		(1 << 0)
++
++
++/* DDRC clock gate unit configure 0 */
++#define DDRC_CGU_PORT7		(1 << 28)
++#define DDRC_CGU_PORT6		(1 << 24)
++#define DDRC_CGU_PORT5		(1 << 20)
++#define DDRC_CGU_PORT4		(1 << 16)
++#define DDRC_CGU_PORT3		(1 << 12)
++#define DDRC_CGU_PORT2		(1 << 8)
++#define DDRC_CGU_PORT1		(1 << 4)
++#define DDRC_CGU_PORT0		(1 << 0)
++
++/* DDRC clock gate unit configure 1 */
++#define DDRC_CGU_BWM		(1 << 8)
++#define DDRC_CGU_PCTRL		(1 << 4)
++#define DDRC_CGU_SCH		(1 << 1)
++#define DDRC_CGU_PA		(1 << 0)
++
++
++
++/*
++ * DDR INNOPHY REGISTER BITS DEFINE
++ * */
++
++/* DDRP DQ Width Register */
++#define DDRP_DQ_WIDTH_DQ_H		(1 << 1)
++#define DDRP_DQ_WIDTH_DQ_L		(1 << 0)
++
++/* DDRP Pll Ctrl Register */
++#define DDRP_PLL_CTRL_PLLPDEN		(1 << 1)
++
++/* DDRP Training Ctrl Register */
++#define DDRP_TRAINING_CTRL_WL_BP	(1 << 3)
++#define DDRP_TRAINING_CTRL_WL_START	(1 << 2)
++#define DDRP_TRAINING_CTRL_DSCSE_BP	(1 << 1)
++#define DDRP_TRAINING_CTRL_DSACE_START	(1 << 0)
++
++/* DDRP Training Done Register */
++#define DDRP_CALIB_DONE_HDQCFB 		(1 << 3)
++#define DDRP_CALIB_DONE_LDQCFB 		(1 << 2)
++#define DDRP_CALIB_DONE_HDQCFA 		(1 << 1)
++#define DDRP_CALIB_DONE_LDQCFA 		(1 << 0)
++#define DDRP_CALIB_DONE_HWRLFB 		(1 << 3)
++#define DDRP_CALIB_DONE_LWRLFB 		(1 << 2)
++#define DDRP_CALIB_DONE_HWRLFA 		(1 << 1)
++#define DDRP_CALIB_DONE_LWRLFA 		(1 << 0)
++
++/* DDRP CALIB BP Register */
++#define DDRP_CALIB_BP_CYCLESELBH_BIT	4
++#define DDRP_CALIB_BP_OPHCSELBH_BIT	3
++#define DDRP_CALIB_BP_DLLSELBH_BIT	0
++
++/* DDRP Init Complete Register */
++#define DDRP_INIT_COMP			(1 << 0)
++
++#define DDRP_PLL_LOCK			(1 << 3)
++
++#define REG32(addr) *(volatile unsigned int *)(addr)
++
++#define ddr_writel(value, reg)	(REG32(DDRC_BASE + reg) = (value))
++#define ddr_readl(reg)		REG32(DDRC_BASE + reg)
++#endif /* __DDR_H__ */
+diff --git a/arch/mips/xburst2/soc-x2000/include/soc/efuse.h b/arch/mips/xburst2/soc-x2000/include/soc/efuse.h
+new file mode 100644
+index 000000000..1298986ea
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/include/soc/efuse.h
+@@ -0,0 +1,365 @@
++#ifndef __INGENIC_EFUSE_H__
++#define __INGENIC_EFUSE_H__
++
++#define EFUSE_CTRL		0x0
++#define EFUSE_CFG		0x4
++#define EFUSE_STATE		0x8
++#define EFUSE_DATA(n)		(0xC + (n) * 4)
++
++#define EFUSE_RIR_RF                 (0)
++#define EFUSE_RIR_DATA               (1)
++#define EFUSE_RIR_ADDR               (2)
++#define EFUSE_RIR_DISABLE            (15)
++
++
++// efuse ctrl bits
++#define EFUSE_CTRL_ADDR              (21)
++#define EFUSE_CTRL_ADDR_MASK         (0x3f)
++#define EFUSE_CTRL_LEN               (16)
++#define EFUSE_CTRL_LEN_MASK          (7)
++#define EFUSE_CTRL_PGEN              (1 << 15)
++#define EFUSE_CTRL_RWL               (1 << 11)
++#define EFUSE_CTRL_MR                (1 << 10)
++#define EFUSE_CTRL_PS                (1 << 9)
++#define EFUSE_CTRL_PD                (1 << 8)
++#define EFUSE_CTRL_WREN              (1 << 1)
++#define EFUSE_CTRL_RDEN              (1 << 0)
++
++
++// efuse cfg bits
++#define EFUSE_CFG_INT_EN             (1 << 31)
++#define EFUSE_CFG_RD_ADJ             (24)
++#define EFUSE_CFG_RD_ADJ_MASK        (0xf)
++#define EFUSE_CFG_RD_STROBE          (16)
++#define EFUSE_CFG_RD_STROBE_MASK     (0x1f)
++#define EFUSE_CFG_WR_ADJ             (12)
++#define EFUSE_CFG_WR_ADJ_MASK        (0xf)
++#define EFUSE_CFG_WR_STROBE          (16)
++#define EFUSE_CFG_WR_STROBE_MASK     (0x3ff)
++
++
++// efuse state bits
++#define EFUSE_STA_NKU_PRT            (1 << 23)
++#define EFUSE_STA_USERKEY1_PRT       (1 << 22)
++#define EFUSE_STA_USERKEY0_PRT       (1 << 21)
++#define EFUSE_STA_CHIPKEY_PRT        (1 << 20)
++#define EFUSE_STA_HIDEBLK_PRT        (1 << 19)
++#define EFUSE_STA_SOCINFO_PRT        (1 << 18)
++#define EFUSE_STA_TRIM2_PRT          (1 << 17)
++#define EFUSE_STA_TRIM1_PRT          (1 << 16)
++#define EFUSE_STA_TRIM0_PRT          (1 << 15)
++#define EFUSE_STA_CUSTID2_PRT        (1 << 14)
++#define EFUSE_STA_CUSTID1_PRT        (1 << 13)
++#define EFUSE_STA_CUSTID0_PRT        (1 << 12)
++#define EFUSE_STA_CHIPID_PRT         (1 << 11)
++#define EFUSE_STA_SECBOOT_PRT        (1 << 10)
++#define EFUSE_STA_DIS_JTAG           (1 << 9)
++#define EFUSE_STA_SECBOOT_EN         (1 << 8)
++#define EFUSE_STA_WR_DONE            (1 << 1)
++#define EFUSE_STA_RD_DONE            (1 << 0)
++
++
++
++#define CHIPID_OFFSET_ADDR            (0x0)
++#define CUSTID0_OFFSET_ADDR           (0x11)
++#define CUSTID1_OFFSET_ADDR           (0x22)
++#define CUSTID2_OFFSET_ADDR           (0x3f)
++#define TRIM0_OFFSET_ADDR             (0x5c)
++#define TRIM1_OFFSET_ADDR             (0x61)
++#define TRIM2_OFFSET_ADDR             (0x66)
++#define SOCINFO_OFFSET_ADDR           (0x6b)
++#define PRT_OFFSET_ADDR               (0x70)
++#define HIDEBLK_OFFSET_ADDR           (0x74)
++#define CHIPKEY_OFFSET_ADDR           (0x78)
++#define USERKEY0_OFFSET_ADDR          (0x9a)
++#define USERKEY1_OFFSET_ADDR          (0xbc)
++#define NKU_OFFSET_ADDR               (0xde)
++
++#define CHIPID_WORD_ADDR            (0x0)
++#define CUSTID0_WORD_ADDR           (0x4)
++#define CUSTID1_WORD_ADDR           (0x8)
++#define CUSTID2_WORD_ADDR           (0xf)
++#define TRIM0_WORD_ADDR             (0x17)
++#define TRIM1_WORD_ADDR             (0x18)
++#define TRIM2_WORD_ADDR             (0x19)
++#define SOCINFO_WORD_ADDR           (0x1a)
++#define PRT_WORD_ADDR               (0x1c)
++#define HIDEBLK_WORD_ADDR           (0x1d)
++#define CHIPKEY_WORD_ADDR           (0x1e)
++#define USERKEY0_WORD_ADDR          (0x26)
++#define USERKEY1_WORD_ADDR          (0x2f)
++#define NKU_WORD_ADDR               (0x37)
++
++#define CHIPID_BIT_NUM		    (128)
++#define CUSTID0_BIT_NUM		    (128)
++#define CUSTID1_BIT_NUM             (216)
++#define CUSTID2_BIT_NUM             (216)
++#define TRIM0_BIT_NUM               (32)
++#define TRIM1_BIT_NUM               (32)
++#define TRIM2_BIT_NUM               (32)
++#define SOCINFO_BIT_NUM             (32)
++#define PRT_BIT_NUM                 (16)
++#define HIDEBLK_BIT_NUM             (16)
++#define CHIPKEY_BIT_NUM             (256)
++#define USERKEY0_BIT_NUM            (256)
++#define USERKEY1_BIT_NUM            (256)
++#define NKU_BIT_NUM                 (256)
++
++#define CHIPID_EXT_BIT_NUM           (8)
++#define CUSTID0_EXT_BIT_NUM          (8)
++#define CUSTID1_EXT_BIT_NUM          (16)
++#define CUSTID2_EXT_BIT_NUM          (16)
++#define TRIM0_EXT_BIT_NUM            (8)
++#define TRIM1_EXT_BIT_NUM            (8)
++#define TRIM2_EXT_BIT_NUM            (8)
++#define SOCINFO_EXT_BIT_NUM          (8)
++#define PRT_EXT_BIT_NUM              (16)
++#define HIDEBLK_EXT_BIT_NUM          (16)
++#define CHIPKEY_EXT_BIT_NUM          (16)
++#define USERKEY0_EXT_BIT_NUM         (16)
++#define USERKEY1_EXT_BIT_NUM         (16)
++#define NKU_EXT_BIT_NUM              (16)
++
++#define CHIPID_WORD_NUM           (((CHIPID_BIT_NUM	+ CHIPID_EXT_BIT_NUM 	) / 32) + (((CHIPID_BIT_NUM	+ CHIPID_EXT_BIT_NUM 	) % 32) ? 1 : 0))
++#define CUSTID0_WORD_NUM          (((CUSTID0_BIT_NUM	+ CUSTID0_EXT_BIT_NUM	) / 32) + (((CUSTID0_BIT_NUM	+ CUSTID0_EXT_BIT_NUM	) % 32) ? 1 : 0))
++#define CUSTID1_WORD_NUM          (((CUSTID1_BIT_NUM	+ CUSTID1_EXT_BIT_NUM	) / 32) + (((CUSTID1_BIT_NUM	+ CUSTID1_EXT_BIT_NUM	) % 32) ? 1 : 0))
++#define CUSTID2_WORD_NUM          (((CUSTID2_BIT_NUM	+ CUSTID2_EXT_BIT_NUM	) / 32) + (((CUSTID2_BIT_NUM	+ CUSTID2_EXT_BIT_NUM	) % 32) ? 1 : 0))
++#define TRIM0_WORD_NUM            (((TRIM0_BIT_NUM	+ TRIM0_EXT_BIT_NUM	) / 32) + (((TRIM0_BIT_NUM	+ TRIM0_EXT_BIT_NUM	) % 32) ? 1 : 0))
++#define TRIM1_WORD_NUM            (((TRIM1_BIT_NUM	+ TRIM1_EXT_BIT_NUM	) / 32) + (((TRIM1_BIT_NUM	+ TRIM1_EXT_BIT_NUM	) % 32) ? 1 : 0))
++#define TRIM2_WORD_NUM            (((TRIM2_BIT_NUM	+ TRIM2_EXT_BIT_NUM	) / 32) + (((TRIM2_BIT_NUM	+ TRIM2_EXT_BIT_NUM	) % 32) ? 1 : 0))
++#define SOCINFO_WORD_NUM          (((SOCINFO_BIT_NUM	+ SOCINFO_EXT_BIT_NUM	) / 32) + (((SOCINFO_BIT_NUM	+ SOCINFO_EXT_BIT_NUM	) % 32) ? 1 : 0))
++#define PRT_WORD_NUM              (((PRT_BIT_NUM	+ PRT_EXT_BIT_NUM	) / 32) + (((PRT_BIT_NUM	+ PRT_EXT_BIT_NUM	) % 32) ? 1 : 0))
++#define HIDEBLK_WORD_NUM          (((HIDEBLK_BIT_NUM	+ HIDEBLK_EXT_BIT_NUM	) / 32) + (((HIDEBLK_BIT_NUM	+ HIDEBLK_EXT_BIT_NUM	) % 32) ? 1 : 0))
++#define CHIPKEY_WORD_NUM          (((CHIPKEY_BIT_NUM	+ CHIPKEY_EXT_BIT_NUM	) / 32) + (((CHIPKEY_BIT_NUM	+ CHIPKEY_EXT_BIT_NUM	) % 32) ? 1 : 0))
++#define USERKEY0_WORD_NUM         (((USERKEY0_BIT_NUM	+ USERKEY0_EXT_BIT_NUM	) / 32) + (((USERKEY0_BIT_NUM	+ USERKEY0_EXT_BIT_NUM	) % 32) ? 1 : 0))
++#define USERKEY1_WORD_NUM         (((USERKEY1_BIT_NUM	+ USERKEY1_EXT_BIT_NUM	) / 32) + (((USERKEY1_BIT_NUM	+ USERKEY1_EXT_BIT_NUM	) % 32) ? 1 : 0))
++#define NKU_WORD_NUM              (((NKU_BIT_NUM	+ NKU_EXT_BIT_NUM	) / 32) + (((NKU_BIT_NUM	+ NKU_EXT_BIT_NUM	) % 32) ? 1 : 0))
++
++
++#define CHIPID_BEGIN_ALIGN          (CHIPID_OFFSET_ADDR   - (CHIPID_WORD_ADDR   << 2))
++#define CUSTID0_BEGIN_ALIGN         (CUSTID0_OFFSET_ADDR  - (CUSTID0_WORD_ADDR  << 2))
++#define CUSTID1_BEGIN_ALIGN         (CUSTID1_OFFSET_ADDR  - (CUSTID1_WORD_ADDR  << 2))
++#define CUSTID2_BEGIN_ALIGN         (CUSTID2_OFFSET_ADDR  - (CUSTID2_WORD_ADDR  << 2))
++#define TRIM0_BEGIN_ALIGN           (TRIM0_OFFSET_ADDR    - (TRIM0_WORD_ADDR    << 2))
++#define TRIM1_BEGIN_ALIGN           (TRIM1_OFFSET_ADDR    - (TRIM1_WORD_ADDR    << 2))
++#define TRIM2_BEGIN_ALIGN           (TRIM2_OFFSET_ADDR	  - (TRIM2_WORD_ADDR    << 2))
++#define SOCINFO_BEGIN_ALIGN         (SOCINFO_OFFSET_ADDR  - (SOCINFO_WORD_ADDR  << 2))
++#define PRT_BEGIN_ALIGN             (PRT_OFFSET_ADDR      - (PRT_WORD_ADDR      << 2))
++#define HIDEBLK_BEGIN_ALIGN         (HIDEBLK_OFFSET_ADDR  - (HIDEBLK_WORD_ADDR  << 2))
++#define CHIPKEY_BEGIN_ALIGN         (CHIPKEY_OFFSET_ADDR  - (CHIPKEY_WORD_ADDR  << 2))
++#define USERKEY0_BEGIN_ALIGN        (USERKEY0_OFFSET_ADDR - (USERKEY0_WORD_ADDR << 2))
++#define USERKEY1_BEGIN_ALIGN        (USERKEY1_OFFSET_ADDR - (USERKEY1_WORD_ADDR << 2))
++#define NKU_BEGIN_ALIGN             (NKU_OFFSET_ADDR      - (NKU_WORD_ADDR      << 2))
++
++
++#define CHIPID_END_ALIGN	    (4 - CHIPID_BEGIN_ALIGN   - (((CHIPID_BIT_NUM   + CHIPID_EXT_BIT_NUM   ) % 32) >> 3))
++#define CUSTID0_END_ALIGN           (4 - CUSTID0_BEGIN_ALIGN  - (((CUSTID0_BIT_NUM  + CUSTID0_EXT_BIT_NUM  ) % 32) >> 3))
++#define CUSTID1_END_ALIGN           (4 - CUSTID1_BEGIN_ALIGN  - (((CUSTID1_BIT_NUM  + CUSTID1_EXT_BIT_NUM  ) % 32) >> 3))
++#define CUSTID2_END_ALIGN           (4 - CUSTID2_BEGIN_ALIGN  - (((CUSTID2_BIT_NUM  + CUSTID2_EXT_BIT_NUM  ) % 32) >> 3))
++#define TRIM0_END_ALIGN             (4 - TRIM0_BEGIN_ALIGN    - (((TRIM0_BIT_NUM    + TRIM0_EXT_BIT_NUM	   ) % 32) >> 3))
++#define TRIM1_END_ALIGN             (4 - TRIM1_BEGIN_ALIGN    - (((TRIM1_BIT_NUM    + TRIM1_EXT_BIT_NUM	   ) % 32) >> 3))
++#define TRIM2_END_ALIGN             (4 - TRIM2_BEGIN_ALIGN    - (((TRIM2_BIT_NUM    + TRIM2_EXT_BIT_NUM	   ) % 32) >> 3))
++#define SOCINFO_END_ALIGN           (4 - SOCINFO_BEGIN_ALIGN  - (((SOCINFO_BIT_NUM  + SOCINFO_EXT_BIT_NUM  ) % 32) >> 3))
++#define PRT_END_ALIGN               (4 - PRT_BEGIN_ALIGN      - (((PRT_BIT_NUM      + PRT_EXT_BIT_NUM	   ) % 32) >> 3))
++#define HIDEBLK_END_ALIGN           (4 - HIDEBLK_BEGIN_ALIGN  - (((HIDEBLK_BIT_NUM  + HIDEBLK_EXT_BIT_NUM  ) % 32) >> 3))
++#define CHIPKEY_END_ALIGN           (4 - CHIPKEY_BEGIN_ALIGN  - (((CHIPKEY_BIT_NUM  + CHIPKEY_EXT_BIT_NUM  ) % 32) >> 3))
++#define USERKEY0_END_ALIGN          (4 - USERKEY0_BEGIN_ALIGN - (((USERKEY0_BIT_NUM + USERKEY0_EXT_BIT_NUM ) % 32) >> 3))
++#define USERKEY1_END_ALIGN          (4 - USERKEY1_BEGIN_ALIGN - (((USERKEY1_BIT_NUM + USERKEY1_EXT_BIT_NUM ) % 32) >> 3))
++#define NKU_END_ALIGN               (4 - NKU_BEGIN_ALIGN      - (((NKU_BIT_NUM      + NKU_EXT_BIT_NUM	   ) % 32) >> 3))
++
++
++enum segment_id {
++	CHIPID = 0,
++	CUSTID0,
++	CUSTID1,
++	CUSTID2,
++	TRIM0,
++	TRIM1,
++	TRIM2,
++	SOCINFO,
++	PRT,
++	HIDEBLK,
++	CHIPKEY,
++	USERKEY0,
++	USERKEY1,
++	NKU
++};
++
++enum verify_mode {
++	NONE = 0,
++	DOUBLE,
++	HAMMING
++};
++
++struct seg_info {
++	char seg_name[32];
++	uint32_t seg_id;
++	uint32_t word_address;
++	uint32_t word_num;
++	uint32_t bit_num;
++	uint32_t begin_align;
++	uint32_t end_align;
++	uint32_t prt_bit;
++	uint32_t verify_mode;
++};
++
++static struct seg_info seg_info_array[] = {
++	[0] = {
++		.seg_name = "CHIPID",
++		.seg_id = CHIPID,
++		.word_address = CHIPID_WORD_ADDR,
++		.begin_align = CHIPID_BEGIN_ALIGN,
++		.end_align = CHIPID_END_ALIGN,
++		.bit_num = CHIPID_BIT_NUM,
++		.word_num = CHIPID_WORD_NUM,
++		.prt_bit = EFUSE_STA_CHIPID_PRT,
++		.verify_mode = HAMMING,
++	},
++	[1] = {
++		.seg_name = "CUSTID0",
++		.seg_id = CUSTID0,
++		.word_address = CUSTID0_WORD_ADDR,
++		.begin_align = CUSTID0_BEGIN_ALIGN,
++		.end_align = CUSTID0_END_ALIGN,
++		.bit_num = CUSTID0_BIT_NUM,
++		.word_num = CUSTID0_WORD_NUM,
++		.prt_bit = EFUSE_STA_CUSTID0_PRT,
++		.verify_mode = HAMMING,
++	},
++	[2] = {
++		.seg_name = "CUSTID1",
++		.seg_id = CUSTID1,
++		.word_address = CUSTID1_WORD_ADDR,
++		.begin_align = CUSTID1_BEGIN_ALIGN,
++		.end_align = CUSTID1_END_ALIGN,
++		.bit_num = CUSTID1_BIT_NUM,
++		.word_num = CUSTID1_WORD_NUM,
++		.prt_bit = EFUSE_STA_CUSTID1_PRT,
++		.verify_mode = HAMMING,
++	},
++	[3] = {
++		.seg_name = "CUSTID2",
++		.seg_id = CUSTID2,
++		.word_address = CUSTID2_WORD_ADDR,
++		.begin_align = CUSTID2_BEGIN_ALIGN,
++		.end_align = CUSTID2_END_ALIGN,
++		.bit_num = CUSTID2_BIT_NUM,
++		.word_num = CUSTID2_WORD_NUM,
++		.prt_bit = EFUSE_STA_CUSTID2_PRT,
++		.verify_mode = HAMMING,
++	},
++	[4] = {
++		.seg_name = "TRIM0",
++		.seg_id = TRIM0,
++		.word_address = TRIM0_WORD_ADDR,
++		.begin_align = TRIM0_BEGIN_ALIGN,
++		.end_align = TRIM0_END_ALIGN,
++		.bit_num = TRIM0_BIT_NUM,
++		.word_num = TRIM0_WORD_NUM,
++		.prt_bit = EFUSE_STA_TRIM0_PRT,
++		.verify_mode = HAMMING,
++	},
++	[5] = {
++		.seg_name = "TRIM1",
++		.seg_id = TRIM1,
++		.word_address = TRIM1_WORD_ADDR,
++		.begin_align = TRIM1_BEGIN_ALIGN,
++		.end_align = TRIM1_END_ALIGN,
++		.bit_num = TRIM1_BIT_NUM,
++		.word_num = TRIM1_WORD_NUM,
++		.prt_bit = EFUSE_STA_TRIM1_PRT,
++		.verify_mode = HAMMING,
++	},
++	[6] = {
++		.seg_name = "TRIM2",
++		.seg_id = TRIM2,
++		.word_address = TRIM2_WORD_ADDR,
++		.begin_align = TRIM2_BEGIN_ALIGN,
++		.end_align = TRIM2_END_ALIGN,
++		.bit_num = TRIM2_BIT_NUM,
++		.word_num = TRIM2_WORD_NUM,
++		.prt_bit = EFUSE_STA_TRIM2_PRT,
++		.verify_mode = NONE,
++	},
++	[7] = {
++		.seg_name = "SOCINFO",
++		.seg_id = SOCINFO,
++		.word_address = SOCINFO_WORD_ADDR,
++		.begin_align = SOCINFO_BEGIN_ALIGN,
++		.end_align = SOCINFO_END_ALIGN,
++		.bit_num = SOCINFO_BIT_NUM + SOCINFO_EXT_BIT_NUM,
++		.word_num = SOCINFO_WORD_NUM,
++		.prt_bit = EFUSE_STA_SOCINFO_PRT,
++		.verify_mode = DOUBLE,
++	},
++	[8] = {
++		.seg_name = "PRT",
++		.seg_id = PRT,
++		.word_address = PRT_WORD_ADDR,
++		.begin_align = PRT_BEGIN_ALIGN,
++		.end_align = PRT_END_ALIGN,
++		.bit_num = PRT_BIT_NUM + PRT_EXT_BIT_NUM,
++		.word_num = PRT_WORD_NUM,
++		.prt_bit = 0xffffffff,
++		.verify_mode = DOUBLE,
++	},
++	[9] = {
++		.seg_name = "HIDEBLK",
++		.seg_id = HIDEBLK,
++		.word_address = HIDEBLK_WORD_ADDR,
++		.begin_align = HIDEBLK_BEGIN_ALIGN,
++		.end_align = HIDEBLK_END_ALIGN,
++		.bit_num = HIDEBLK_BIT_NUM,
++		.word_num = HIDEBLK_WORD_NUM,
++		.prt_bit = EFUSE_STA_HIDEBLK_PRT,
++		.verify_mode = HAMMING,
++	},
++	[10] = {
++		.seg_name = "CHIPKEY",
++		.seg_id = CHIPKEY,
++		.word_address = CHIPKEY_WORD_ADDR,
++		.begin_align = CHIPKEY_BEGIN_ALIGN,
++		.end_align = CHIPKEY_END_ALIGN,
++		.bit_num = CHIPKEY_BIT_NUM,
++		.word_num = CHIPKEY_WORD_NUM,
++		.prt_bit = EFUSE_STA_CHIPKEY_PRT,
++		.verify_mode = HAMMING,
++	},
++	[11] = {
++		.seg_name = "USERKEY0",
++		.seg_id = USERKEY0,
++		.word_address = USERKEY0_WORD_ADDR,
++		.begin_align = USERKEY0_BEGIN_ALIGN,
++		.end_align = USERKEY0_END_ALIGN,
++		.bit_num = USERKEY0_BIT_NUM,
++		.word_num = USERKEY0_WORD_NUM,
++		.prt_bit = EFUSE_STA_USERKEY0_PRT,
++		.verify_mode = HAMMING,
++	},
++	[12] = {
++		.seg_name = "USERKEY1",
++		.seg_id = USERKEY1,
++		.word_address = USERKEY1_WORD_ADDR,
++		.begin_align = USERKEY1_BEGIN_ALIGN,
++		.end_align = USERKEY1_END_ALIGN,
++		.bit_num = USERKEY1_BIT_NUM,
++		.word_num = USERKEY1_WORD_NUM,
++		.prt_bit = EFUSE_STA_USERKEY1_PRT,
++		.verify_mode = HAMMING,
++	},
++	[13] = {
++		.seg_name = "NKU",
++		.seg_id = NKU,
++		.word_address = NKU_WORD_ADDR,
++		.begin_align = NKU_BEGIN_ALIGN,
++		.end_align = NKU_END_ALIGN,
++		.bit_num = NKU_BIT_NUM,
++		.word_num = NKU_WORD_NUM,
++		.prt_bit = EFUSE_STA_NKU_PRT,
++		.verify_mode = HAMMING,
++	},
++};
++
++void jz_efuse_id_read(int is_chip_id, uint32_t *buf);
++
++#endif
+diff --git a/arch/mips/xburst2/soc-x2000/include/soc/extal.h b/arch/mips/xburst2/soc-x2000/include/soc/extal.h
+new file mode 100644
+index 000000000..398b5912f
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/include/soc/extal.h
+@@ -0,0 +1,12 @@
++
++#ifndef __JZSOC_EXTAL_H__
++#define __JZSOC_EXTAL_H__
++
++#define JZ_EXTAL_RTC	32768     /* RTC extal freq: 32.768 KHz */
++#define JZ_EXTAL	(CONFIG_EXTAL_CLOCK * 1000000)
++
++#ifdef CONFIG_PALLADIUM_PLATFORM
++#define PALLADIUM_CLK_INPURT  (500*1000000)
++#endif
++
++#endif
+diff --git a/arch/mips/xburst2/soc-x2000/include/soc/gpio.h b/arch/mips/xburst2/soc-x2000/include/soc/gpio.h
+new file mode 100644
+index 000000000..25656adc5
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/include/soc/gpio.h
+@@ -0,0 +1,42 @@
++#ifndef _SOC_GPIO_H_
++#define _SOC_GPIO_H_
++
++enum gpio_function {
++    GPIO_FUNC_0    = 0x10,  //0000, GPIO as function 0 / device 0
++    GPIO_FUNC_1    = 0x11,  //0001, GPIO as function 1 / device 1
++    GPIO_FUNC_2    = 0x12,  //0010, GPIO as function 2 / device 2
++    GPIO_FUNC_3    = 0x13,  //0011, GPIO as function 3 / device 3
++    GPIO_OUTPUT0   = 0x14,  //0100, GPIO output low  level
++    GPIO_OUTPUT1   = 0x15,  //0101, GPIO output high level
++    GPIO_INPUT     = 0x16,  //0110, GPIO as input.7 also.
++    GPIO_INT_LO    = 0x18,  //1000, Low  Level trigger interrupt
++    GPIO_INT_HI    = 0x19,  //1001, High Level trigger interrupt
++    GPIO_INT_FE    = 0x1a,  //1010, Fall Edge trigger interrupt
++    GPIO_INT_RE    = 0x1b,  //1011, Rise Edge trigger interrupt
++    GPIO_INT_MASK_LO   = 0x1c,  //1100, Port is low level triggered interrupt input. Interrupt is masked.
++    GPIO_INT_MASK_HI   = 0x1d,  //1101, Port is high level triggered interrupt input. Interrupt is masked.
++    GPIO_INT_MASK_FE   = 0x1e,  //1110, Port is fall edge triggered interrupt input. Interrupt is masked.
++    GPIO_INT_MASK_RE   = 0x1f,  //1111, Port is rise edge triggered interrupt input. Interrupt is masked.
++
++    GPIO_PULL_HIZ  = 0x80,    //no pull
++    GPIO_PULL_UP   = 0xa0,    //pull high
++    GPIO_PULL_DOWN = 0xc0,    //pull low
++};
++
++#define GPIO_PA(n) (0 * 32 + (n))
++#define GPIO_PB(n) (1 * 32 + (n))
++#define GPIO_PC(n) (2 * 32 + (n))
++#define GPIO_PD(n) (3 * 32 + (n))
++#define GPIO_PE(n) (4 * 32 + (n))
++#define GPIO_PF(n) (5 * 32 + (n))
++
++enum gpio_port {
++	GPIO_PORT_A, GPIO_PORT_B,
++	GPIO_PORT_C, GPIO_PORT_D, GPIO_PORT_E,
++	/* this must be last */
++	GPIO_NR_PORTS,
++};
++
++int jzgpio_set_func(int port, enum gpio_function func, unsigned long pins);
++
++#endif /* _SOC_GPIO_H_ */
+diff --git a/arch/mips/xburst2/soc-x2000/include/soc/rtc.h b/arch/mips/xburst2/soc-x2000/include/soc/rtc.h
+new file mode 100644
+index 000000000..871add1fc
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/include/soc/rtc.h
+@@ -0,0 +1,96 @@
++#ifndef __RTC_H__
++#define __RTC_H__
++
++/*
++ * RTC registers offset address definition
++ */
++#define RTC_RTCCR		(0x00)	/* rw, 32, 0x00000081 */
++#define RTC_RTCSR		(0x04)	/* rw, 32, 0x???????? */
++#define RTC_RTCSAR		(0x08)	/* rw, 32, 0x???????? */
++#define RTC_RTCGR		(0x0c)	/* rw, 32, 0x0??????? */
++
++#define RTC_HCR			(0x20)  /* rw, 32, 0x00000000 */
++#define RTC_HWFCR		(0x24)  /* rw, 32, 0x0000???0 */
++#define RTC_HRCR		(0x28)  /* rw, 32, 0x00000??0 */
++#define RTC_HWCR		(0x2c)  /* rw, 32, 0x00000008 */
++#define RTC_HWRSR		(0x30)  /* rw, 32, 0x00000000 */
++#define RTC_HSPR		(0x34)  /* rw, 32, 0x???????? */
++#define RTC_WENR		(0x3c)  /* rw, 32, 0x00000000 */
++#define RTC_WKUPPINCR		(0x48)	/* rw, 32, 0x00050064*/
++
++/*
++ * RTC registers common define
++ */
++
++/* RTC control register(RTCCR) */
++#define RTCCR_WRDY		BIT(7)
++#define RTCCR_1HZ		BIT(6)
++#define RTCCR_1HZIE		BIT(5)
++#define RTCCR_AF		BIT(4)
++#define RTCCR_AIE		BIT(3)
++#define RTCCR_AE		BIT(2)
++#define RTCCR_SELEXC		BIT(1)
++#define RTCCR_RTCE		BIT(0)
++
++
++/* Generate the bit field mask from msb to lsb */
++#define BITS_H2L(msb, lsb)  ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))
++
++/* RTC regulator register(RTCGR) */
++#define RTCGR_LOCK		BIT(31)
++#define RTCGR_ADJC_LSB		16
++#define RTCGR_ADJC_MASK		BITS_H2L(25, RTCGR_ADJC_LSB)
++#define RTCGR_NC1HZ_LSB		0
++#define RTCGR_NC1HZ_MASK	BITS_H2L(15, RTCGR_NC1HZ_LSB)
++
++/* Hibernate control register(HCR) */
++#define HCR_PD			BIT(0)
++
++/* Hibernate wakeup filter counter register(HWFCR) */
++#define HWFCR_LSB		5
++#define HWFCR_MASK		BITS_H2L(15, HWFCR_LSB)
++#define HWFCR_WAIT_TIME(ms, clk) (((ms)*(clk)/1000+0xf) > HWFCR_MASK ? HWFCR_MASK : ((ms)*(clk)/1000+0xf) & HWFCR_MASK)
++
++/* Hibernate reset counter register(HRCR) */
++#define HRCR_LSB		11
++#define HRCR_MASK		BITS_H2L(14, HRCR_LSB)
++#define HRCR_WAIT_TIME(ms, clk) (((ms)*(clk)/1000 + 0x3ff - 0x800) > HRCR_MASK ? HRCR_MASK : \
++								 ((ms)*(clk)/1000 + 0x3ff - 0x800) & HRCR_MASK)
++
++
++/* Hibernate wakeup control register(HWCR) */
++/* Power detect default value; this value means enable */
++#define EPDET_LSB		3
++#define EPDET_DEFAULT           (0x5aa5a5a << EPDET_LSB)
++#define EPDET_ENABLE		(0x5aa5a5a << EPDET_LSB)
++#define EPDET_DISABLE		(0x1a55a5a5 << EPDET_LSB)
++#define HWCR_EALM		BIT(0)
++
++
++/* Hibernate wakeup status register(HWRSR) */
++#define HWRSR_APD		BIT(8)
++#define HWRSR_HR		BIT(5)
++#define HWRSR_PPR		BIT(4)
++#define HWRSR_PIN		BIT(1)
++#define HWRSR_ALM		BIT(0)
++
++/* write enable pattern register(WENR) */
++#define WENR_WEN		BIT(31)
++#define WENR_WENPAT_LSB		0
++#define WENR_WENPAT_MASK	BITS_H2L(15, WENR_WENPAT_LSB)
++#define WENR_WENPAT_WRITABLE	(0xa55a)
++
++/* Hibernate scratch pattern register(HSPR) */
++#define HSPR_RTCV               0x52544356      /* The value is 'RTCV', means rtc is valid */
++
++/*WKUP_PIN_RST control register (WKUPPINCR)*/
++#define WKUPPINCR_BIAS_CTRL	(0x1 << 16)	/* fix value*/
++#define WKUPPINCR_OSC_EN        BIT(18)
++#define WKUPPINCR_P_JUD_LEN_LSB	4
++#define WKUPPINCR_P_JUD_LEN_MASK	BITS_H2L(7, WKUPPINCR_P_JUD_LEN_LSB)
++#define WKUPPINCR_P_JUD_LEN(s)  ((s) << WKUPPINCR_P_JUD_LEN_LSB) > WKUPPINCR_P_JUD_LEN_MASK ? \
++	WKUPPINCR_P_JUD_LEN_MASK : (s) << WKUPPINCR_P_JUD_LEN_LSB
++#define WKUPPINCR_P_JUD_EN	(0x4)
++/* The divider is decided by the RTC clock frequency. */
++#define RTC_FREQ_DIVIDER	(32768 - 1)
++#endif	/* __RTC_H__ */
+diff --git a/arch/mips/xburst2/soc-x2000/include/soc/sfc.h b/arch/mips/xburst2/soc-x2000/include/soc/sfc.h
+new file mode 100644
+index 000000000..b1684bec9
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/include/soc/sfc.h
+@@ -0,0 +1,211 @@
++#ifndef __SFC_REGISTER_H
++#define __SFC_REGISTER_H
++
++/* SFC register */
++
++#define	SFC_GLB0			(0x0000)
++#define	SFC_DEV_CONF			(0x0004)
++#define	SFC_DEV_STA_EXP			(0x0008)
++#define	SFC_DEV0_STA_RT			(0x000c)
++#define	SFC_DEV_STA_MSK			(0x0010)
++#define	SFC_TRAN_CONF0(n)		(0x0014 + (n * 4))
++#define	SFC_TRAN_LEN			(0x002c)
++#define	SFC_DEV_ADDR(n)			(0x0030 + (n * 4))
++#define	SFC_DEV_ADDR_PLUS(n)		(0x0048 + (n * 4))
++#define	SFC_MEM_ADDR			(0x0060)
++#define	SFC_TRIG			(0x0064)
++#define	SFC_SR				(0x0068)
++#define	SFC_SCR				(0x006c)
++#define	SFC_INTC			(0x0070)
++#define	SFC_FSM				(0x0074)
++#define	SFC_CGE				(0x0078)
++#define SFC_CMD_IDX                     (0x007c)
++#define SFC_COL_ADDR                    (0x0080)
++#define SFC_ROW_ADDR                    (0x0084)
++#define SFC_STA_ADDR0                   (0x0088)
++#define SFC_STA_ADDR1                   (0x008c)
++#define SFC_DES_ADDR                    (0x0090)
++#define SFC_GLB1			(0x0094)
++#define SFC_DEV1_STA_RT			(0x0098)
++#define	SFC_TRAN_CONF1(n)		(0x009c + (n * 4))
++#define SFC_CDT                         (0x0800)  //0x800 ~ 0xbff
++#define	SFC_RM_DR			(0x1000)
++
++/* For SFC_GLB0 */
++#define GLB0_POLL_TIME_OFFSET		(16)
++#define GLB0_POLL_TIME_MSK		(0xffff << GLB0_POLL_TIME_OFFSET)
++#define GLB0_DES_EN			(1 << 15)
++#define GLB0_CDT_EN			(1 << 14)
++#define	GLB0_TRAN_DIR			(1 << 13)
++#define GLB0_TRAN_DIR_WRITE		(1)
++#define GLB0_TRAN_DIR_READ		(0)
++#define	GLB0_THRESHOLD_OFFSET		(7)
++#define GLB0_THRESHOLD_MSK		(0x3f << GLB0_THRESHOLD_OFFSET)
++#define GLB0_OP_MODE			(1 << 6)
++#define GLB0_OP_OFFSET                   (6)
++#define SLAVE_MODE			(0x0)
++#define DMA_MODE			(0x1)
++#define GLB0_PHASE_NUM_OFFSET		(3)
++#define GLB0_PHASE_NUM_MSK		(0x7  << GLB0_PHASE_NUM_OFFSET)
++#define GLB0_WP_EN			(1 << 2)
++#define GLB0_BURST_MD_OFFSET		(0)
++#define GLB0_BURST_MD_MSK		(0x3  << GLB0_BURST_MD_OFFSET)
++
++/* For SFC_DEV_CONF */
++#define DEV_CONF_STA_ENDIAN_OFFSET	(31)
++#define	STA_ENDIAN_LSB			(0)
++#define	STA_ENDIAN_MSB			(1)
++#define	DEV_CONF_SMP_DELAY_OFFSET	(16)
++#define	DEV_CONF_SMP_DELAY_MSK		(0x1f << DEV_CONF_SMP_DELAY_OFFSET)
++#define DEV_CONF_SMP_DELAY_0		(0)
++#define DEV_CONF_SMP_DELAY_45		(1)
++#define DEV_CONF_SMP_DELAY_90		(2)
++#define DEV_CONF_SMP_DELAY_135		(3)
++#define DEV_CONF_SMP_DELAY_180		(4)
++#define DEV_CONF_SMP_DELAY_225		(5)
++#define DEV_CONF_SMP_DELAY_270		(6)
++#define DEV_CONF_SMP_DELAY_315		(7)
++#define DEV_CONF_SMP_DELAY_1		(8)
++#define DEV_CONF_SMP_DELAY_2		(16)
++#define DEV_CONF_CMD_TYPE		(0x1 << 15)
++#define DEV_CONF_STA_TYPE_OFFSET	(13)
++#define DEV_CONF_STA_TYPE_MSK		(0x3 << DEV_CONF_STA_TYPE_OFFSET)
++#define DEV_CONF_THOLD_OFFSET		(11)
++#define	DEV_CONF_THOLD_MSK		(0x3 << DEV_CONF_THOLD_OFFSET)
++#define DEV_CONF_TSETUP_OFFSET		(9)
++#define DEV_CONF_TSETUP_MSK		(0x3 << DEV_CONF_TSETUP_OFFSET)
++#define DEV_CONF_TSH_OFFSET		(5)
++#define DEV_CONF_TSH_MSK		(0xf << DEV_CONF_TSH_OFFSET)
++#define DEV_CONF_CPHA			(0x1 << 4)
++#define DEV_CONF_CPOL			(0x1 << 3)
++#define DEV_CONF_CEDL			(0x1 << 2)
++#define DEV_CONF_HOLDDL			(0x1 << 1)
++#define DEV_CONF_WPDL			(0x1 << 0)
++
++/* For SFC_TRAN_CONF0 */
++#define TRAN_CONF0_CLK_MODE		(29)
++#define	TRAN_CONF0_CLK_MODE_MSK		(0x7 << TRAN_CONF0_CLK_MODE)
++#define TRAN_CONF0_CLK_MODE_SSS		(0)
++#define TRAN_CONF0_CLK_MODE_SSD		(1)
++#define TRAN_CONF0_CLK_MODE_SDS		(2)
++#define TRAN_CONF0_CLK_MODE_SDD		(3)
++#define TRAN_CONF0_CLK_MODE_DSS		(4)
++#define TRAN_CONF0_CLK_MODE_DSD		(5)
++#define TRAN_CONF0_CLK_MODE_DDS		(6)
++#define TRAN_CONF0_CLK_MODE_DDD		(7)
++#define	TRAN_CONF0_ADDR_WIDTH_OFFSET	(26)
++#define	TRAN_CONF0_ADDR_WIDTH_MSK	(0x7 << TRAN_CONF0_ADDR_WIDTH_OFFSET)
++#define TRAN_CONF0_POLLEN		(1 << 25)
++#define TRAN_CONF0_POLL_OFFSET		(25)
++#define TRAN_CONF0_CMDEN		(1 << 24)
++#define TRAN_CONF0_FMAT			(1 << 23)
++#define TRAN_CONF0_FMAT_OFFSET		(23)
++#define TRAN_CONF0_DMYBITS_OFFSET	(17)
++#define TRAN_CONF0_DMYBITS_MSK		(0x3f << TRAN_CONF0_DMYBITS_OFFSET)
++#define TRAN_CONF0_DATEEN		(1 << 16)
++#define TRAN_CONF0_DATEEN_OFFSET	(16)
++#define	TRAN_CONF0_CMD_OFFSET		(0)
++#define	TRAN_CONF0_CMD_MSK		(0xffff << TRAN_CONF0_CMD_OFFSET)
++
++/* For SFC_TRAN_CONF1 */
++#define TRAN_CONF1_DATA_ENDIAN		(1 << 18)
++#define TRAN_CONF1_DATA_ENDIAN_OFFSET	(18)
++#define TRAN_CONF1_DATA_ENDIAN_LSB	(0)
++#define TRAN_CONF1_DATA_ENDIAN_MSB	(1)
++#define TRAN_CONF1_WORD_UNIT_OFFSET	(16)
++#define TRAN_CONF1_WORD_UNIT_MSK	(3 << 16)
++#define TRAN_CONF1_TRAN_MODE_OFFSET	(4)
++#define TRAN_CONF1_TRAN_MODE_MSK	(0xf << TRAN_CONF1_TRAN_MODE_OFFSET)
++#define TRAN_CONF1_SPI_STANDARD		(0x0)
++#define TRAN_CONF1_SPI_DUAL		(0x1)
++#define TRAN_CONF1_SPI_QUAD		(0x5)
++#define TRAN_CONF1_SPI_IO_QUAD		(0x6)
++#define TRAN_CONF1_SPI_OCTAL		(0x9)
++#define TRAN_CONF1_SPI_IO_OCTAL		(0xa)
++#define TRAN_CONF1_SPI_FULL_OCTAL	(0xb)
++
++
++/* For SFC_TRIG */
++#define TRIG_FLUSH			(1 << 2)
++#define TRIG_STOP			(1 << 1)
++#define TRIG_START			(1 << 0)
++
++/* For SFC_SR */
++#define SFC_WORKING		(1 << 7)
++#define SFC_BUSY		(0x3 << 5)
++#define	SFC_END			(1 << 4)
++#define SFC_TREQ		(1 << 3)
++#define SFC_RREQ		(1 << 2)
++#define SFC_OVER		(1 << 1)
++#define SFC_UNDER		(1 << 0)
++
++/* For SFC_SCR */
++#define	CLR_END			(1 << 4)
++#define CLR_TREQ		(1 << 3)
++#define CLR_RREQ		(1 << 2)
++#define CLR_OVER		(1 << 1)
++#define CLR_UNDER		(1 << 0)
++
++//SFC_CMD_IDX
++#define CMD_IDX_MSK                     (0x3f << 0)
++#define CDT_DATAEN_MSK                  (0x1 << 31)
++#define CDT_DATAEN_OFF                  (31)
++#define CDT_DIR_MSK                     (0x1 << 30)
++#define CDT_DIR_OFF                     (30)
++
++/* For SFC_GLB1 */
++#define GLB1_DQS_EN			(1 << 2)
++#define GLB1_CHIP_SEL_OFFSET		(0)
++#define GLB1_CHIP_SEL_MSK		(0x3 << 0)
++#define GLB1_CHIP_SEL_0			(0)
++#define GLB1_CHIP_SEL_1			(1)
++#define GLB1_CHIP_SEL_01		(2)
++
++#define N_MAX			6
++#define MAX_SEGS		128
++
++#define CHANNEL_0		0
++#define CHANNEL_1		1
++#define CHANNEL_2		2
++#define CHANNEL_3		3
++#define CHANNEL_4		4
++#define CHANNEL_5		5
++
++#define ENABLE			1
++#define DISABLE			0
++
++#define COM_CMD			1	// common cmd
++#define POLL_CMD		2	// the cmd will poll the status of flash,ext: read status
++
++#define DMA_OPS			1
++#define CPU_OPS			0
++
++#define TM_STD_SPI		0
++#define TM_DI_DO_SPI	1
++#define TM_DIO_SPI		2
++#define TM_FULL_DIO_SPI	3
++#define TM_QI_QO_SPI	5
++#define TM_QIO_SPI		6
++#define	TM_FULL_QIO_SPI	7
++#define TM_OCTAL_SPT		9
++#define TM_OCTAL_IO_SPI		10
++#define TM_OCTAL_FULL_SPI	11
++
++
++#define DEFAULT_CDT		1
++#define UPDATE_CDT		2
++#define DEFAULT_ADDRSIZE	3
++#define DEFAULT_ADDRMODE	0
++
++
++#define THRESHOLD		32
++
++#define SFC_NOR_RATE    110
++#define DEF_ADDR_LEN    3
++#define DEF_TCHSH       6
++#define DEF_TSLCH       6
++#define DEF_TSHSL_R     20
++#define DEF_TSHSL_W     50
++
++
++#endif
+diff --git a/arch/mips/xburst2/soc-x2000/include/soc/tcsm_layout.h b/arch/mips/xburst2/soc-x2000/include/soc/tcsm_layout.h
+new file mode 100644
+index 000000000..2de46b7bd
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/include/soc/tcsm_layout.h
+@@ -0,0 +1,53 @@
++#ifndef __TCSM_LAYOUT_H__
++#define __TCSM_LAYOUT_H__
++
++/**
++ *      |-------------|
++ *      |    BANK0    |
++ *      |-------------|     <--- SLEEP_TCSM_BOOTCODE_TEXT
++ *      | BOOT CODE   |
++ *      |-------------|     <--- SLEEP_TCSM_RESUMECODE_TEXT
++ *      |    ...      |
++ *      | RESUME CODE |
++ *      |    ...      |
++ *      |-------------|     <--- SLEEP_TCSM_RESUME_DATA
++ *      |    ...      |
++ *      | RESUME DATA |
++ *      |    ...      |
++ *      |_____________|     <--- SLEEP_TCSM_CPU_RESMUE_SP
++ *
++ *
++ *      |-------------|
++ *      |    BANK1    |
++ *      |-------------|     <--- TO BE DEFINED
++ *      |             |
++ *      |             |
++ *      |    ...      |
++ *      |  VOICE DATA |
++ *      |    ...      |
++ *      |             |
++ *      |             |
++ *      |_____________|
++ *
++ */
++
++#define SLEEP_TCSM_SPACE           0xb3422000
++#define VOICE_TCSM_DATA_BUF	   0xb3423000
++#define TCSM_BANK_LEN              4096
++
++#define SLEEP_TCSM_BOOT_TEXT       (SLEEP_TCSM_SPACE)
++#define SLEEP_TCSM_BOOT_LEN        64
++#define SLEEP_TCSM_BOOT_END        (SLEEP_TCSM_BOOT_TEXT + SLEEP_TCSM_BOOT_LEN)
++
++#define SLEEP_TCSM_RESUME_TEXT     (SLEEP_TCSM_BOOT_END)
++#define SLEEP_TCSM_RESUME_LEN      2048
++#define SLEEP_TCSM_RESUME_END      (SLEEP_TCSM_RESUME_TEXT + SLEEP_TCSM_RESUME_LEN)
++
++#define SLEEP_TCSM_RESUME_DATA     (SLEEP_TCSM_RESUME_END)
++
++#define SLEEP_TCSM_SPACE_END       (SLEEP_TCSM_SPACE + TCSM_BANK_LEN)
++
++#define SLEEP_TCSM_CPU_RESMUE_SP   SLEEP_TCSM_SPACE_END - 4
++
++
++#endif	/*  __TCSM_LAYOUT_H__ */
+diff --git a/arch/mips/xburst2/soc-x2000/include/war.h b/arch/mips/xburst2/soc-x2000/include/war.h
+new file mode 100644
+index 000000000..fd1ef3147
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/include/war.h
+@@ -0,0 +1,27 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
++ */
++#ifndef __ASM_MACH_INGENIC_WAR_H__
++#define __ASM_MACH_INGENIC_WAR_H__
++
++#define R4600_V1_INDEX_ICACHEOP_WAR	0
++#define R4600_V1_HIT_CACHEOP_WAR	0
++#define R4600_V2_HIT_CACHEOP_WAR	0
++#define R5432_CP0_INTERRUPT_WAR		0
++#define BCM1250_M3_WAR			0
++#define SIBYTE_1956_WAR			0
++#define MIPS4K_ICACHE_REFILL_WAR	0
++#define MIPS_CACHE_SYNC_WAR		1
++#define MIPS_BRIDGE_SYNC_WAR            1
++#define TX49XX_ICACHE_INDEX_INV_WAR	0
++#define RM9000_CDEX_SMP_WAR		0
++#define ICACHE_REFILLS_WORKAROUND_WAR	0
++#define R10000_LLSC_WAR			0
++#define MIPS34K_MISSED_ITLB_WAR		0
++
++#endif
++
+diff --git a/arch/mips/xburst2/soc-x2000/libdmmu.c b/arch/mips/xburst2/soc-x2000/libdmmu.c
+new file mode 100644
+index 000000000..e3288d299
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/libdmmu.c
+@@ -0,0 +1,1087 @@
++/*
++ * This driver is used by VPU driver.
++ *
++ * Copyright (C) 2015 Ingenic Semiconductor Co., Ltd.
++ *	http://www.ingenic.com
++ * Author:	Yan Zhengting <zhengting.yan@ingenic.com>
++ * Modify by:	Sun Jiwei <jiwei.sun@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/platform_device.h>
++#include <linux/fs.h>
++#include <linux/file.h>
++#include <linux/mm.h>
++#include <linux/list.h>
++#include <linux/mutex.h>
++#include <linux/proc_fs.h>
++#include <linux/debugfs.h>
++#include <linux/mempolicy.h>
++#include <linux/mm_types.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <asm/current.h>
++#include <asm/cacheflush.h>
++#include <asm/tlbflush.h>
++#include <asm/io.h>
++#include <linux/vmalloc.h>
++#include <linux/sched.h>
++#include <ingenic_proc.h>
++#include <linux/module.h>
++#include <linux/mmu_context.h>
++#include <linux/mmu_notifier.h>
++#include <linux/pgtable.h>
++
++#include <libdmmu.h>
++#define print_dbg(f, arg...) printk(KERN_INFO "dpu: %s, %d: " f "\n", __func__, __LINE__, ## arg)
++
++#define MAP_COUNT		0x10
++#define MAP_CONUT_MASK		0xff0
++
++#define DMMU_PTE_VLD 		0x01
++#define DMMU_PMD_VLD 		0x01
++
++#define KSEG0_LOW_LIMIT		0x80000000
++#define KSEG1_HEIGH_LIMIT	0xC0000000
++
++enum mem_break{
++    MODE1,  /* 13 24 57 68 911 1012 ... */
++    MODE2,  /* 13 24 35 46 57 68 79 810 ... */
++    MODE3   /* 12 34 56 78 ... */
++};
++
++LIST_HEAD(handle_list);
++static unsigned long reserved_pte = 0;
++static unsigned long res_pte_paddr;
++
++struct pmd_node {
++	unsigned int count;
++	unsigned long index;
++	unsigned long page;
++	struct list_head list;
++};
++
++struct map_node {
++	struct device *dev;
++	unsigned long start;
++	unsigned long len;
++	struct list_head list;
++};
++
++struct dmmu_handle {
++	pid_t tgid;
++	unsigned long pdg;
++	struct mutex lock;
++	struct list_head list;
++	struct list_head pmd_list;
++	struct list_head map_list;
++	struct list_head dev_notifier_list;
++
++	struct mm_struct *handle_mm; /* mm struct used to match exit_mmap notify */
++
++	struct mmu_notifier mn;
++};
++
++/* for test */
++static struct dmmu_handle *find_handle(void);
++static struct dmmu_handle *create_handle(void);
++static void dmmu_cache_wback(struct dmmu_handle *h);
++static int dmmu_mm_dev_release(struct dmmu_handle *h);
++
++int dmmu_flush_cache(unsigned long vaddr, unsigned long len)
++{
++	struct list_head *pos, *next;
++	struct dmmu_handle *h = NULL;
++	struct map_node *n = NULL;
++	unsigned long *pgd, *pte_phys, *pte;
++	unsigned long virpage_phy;
++	unsigned long v_end = vaddr+len;
++	int found = 0;
++	int index;
++
++	h = find_handle();
++	if(!h){
++		printk("%s find handle err!\n",__func__);
++		return -1;
++	}
++	if (vaddr & 0xfff) {
++		printk("%s addr align page err!\n",__func__);
++		return -1;
++	}
++	list_for_each_safe(pos, next, &h->map_list) {
++		n = list_entry(pos, struct map_node, list);
++		if((vaddr >= n->start) &&
++			((vaddr+len) <= (n->start + n->len))) {
++			found = 1;
++			break;
++		}
++	}
++	if(!found) {
++		printk("%s addr err!\n",__func__);
++		return -1;
++	}
++	pgd = (unsigned long *)h->pdg;
++	while(vaddr < v_end) {
++		index = vaddr>>22;
++		pte_phys = (unsigned long *)(pgd[index] & ~DMMU_PMD_VLD);
++		pte = (unsigned long *)phys_to_virt((unsigned long)pte_phys);
++		index = ((vaddr & 0x3ff000) >> 12);
++		virpage_phy = pte[index] & ~DMMU_PTE_VLD;
++		dma_cache_wback((unsigned long)phys_to_virt(virpage_phy),PAGE_SIZE);
++		vaddr+=PAGE_SIZE;
++	}
++	return 0;
++}
++
++EXPORT_SYMBOL(dmmu_flush_cache);
++static int make_smash_list(struct dmmu_handle *h, unsigned long vaddr, unsigned long (**base)[2], unsigned int *len)
++{
++    unsigned long *pgd = (unsigned long *)h->pdg;
++    unsigned long (*list_smash)[2] = NULL;
++    unsigned int list_len = 0;
++    unsigned long *pte, *pte_phys;
++    unsigned int i, index;
++
++    struct list_head *pos, *next;
++	struct map_node *n;
++
++    list_for_each_safe(pos, next, &h->map_list) {
++        n = list_entry(pos, struct map_node, list);
++        if(vaddr == n->start) {
++            list_len = (n->len) >> 12;
++            break;
++        }
++    }
++
++    if (list_len) {
++        list_smash = kmalloc(list_len * 2 * 4, GFP_KERNEL);
++        if (list_smash) {
++            i = 0;
++            while(i < list_len) {
++                list_smash[i][0] = (unsigned long)(vaddr & 0xfffff000);
++
++		index = vaddr>>22;
++                pte_phys = (unsigned long *)(pgd[index] & ~DMMU_PMD_VLD);
++
++
++		pte = (unsigned long *)phys_to_virt((unsigned long)pte_phys);
++
++		index = ((vaddr & 0x3ff000) >> 12);
++//		printk(">>>>>>virt = 0x%lx, phys = 0x%lx\n", vaddr,
++//				*((unsigned long int *) (((unsigned long)pte_phys+index*4) | 0xa0000000)));
++		list_smash[i][1] = pte[index];
++
++                vaddr+=0x1000;
++		i++;
++            }
++        }
++    }
++
++    if (list_smash) {
++        *base = list_smash;
++        *len = list_len;
++        return 0;
++    } else {
++        return -1;
++    }
++}
++EXPORT_SYMBOL(dmmu_dump_map);
++
++int dmmu_dump_map(unsigned long vaddr)
++{
++	struct dmmu_handle *h = NULL;
++    unsigned long (*list_smash)[2] = NULL;
++    unsigned int list_len = 0;
++    unsigned long *tmp;
++
++	h = find_handle();
++	if(!h)
++		h = create_handle();
++	if(!h)
++		return -1;
++    /* 检查4k对� */
++    if (vaddr & 0xfff){
++        return -1;
++    }
++
++	mutex_lock(&h->lock);
++
++    if (make_smash_list(h, vaddr, &list_smash, &list_len)) {
++	    mutex_unlock(&h->lock);
++        return -1;
++    } else {
++        unsigned int i;
++        for (i = 0; i<list_len; i++) {
++	    tmp = (unsigned long*)((list_smash[i][1] & ~1) | 0xa0000000);
++            printk("[virt: 0x%08lx ---> phys: 0x%08lx] uncache: 0x%08lx\n",
++			    list_smash[i][0],list_smash[i][1],(unsigned long)tmp);
++
++	    printk("value[0] = 0x%08lx, value[1] = 0x%08lx value[2] = 0x%08lx value[1013] = 0x%08lx\n",
++			tmp[0], tmp[1], tmp[2], tmp[1013]);
++        }
++    }
++
++	mutex_unlock(&h->lock);
++    kfree((void*)list_smash);
++
++    return 0;
++}
++
++    /* 13 24 57 68 911 1012 ... */
++static int smash_mode1(unsigned long (*base)[2], unsigned int len)
++{
++    unsigned int i;
++    unsigned long tmp;
++    if (len >= 4) {
++        for (i=0; i<len; i += 2) {
++            tmp = base[i][1];
++            base[i][1] = base[i+1][1];
++            base[i+1][1] = tmp;
++        }
++    }
++    return 0;
++}
++
++    /* 13 24 35 46 57 68 79 810 ... */
++static int smash_mode2(unsigned long (*base)[2], unsigned int len)
++{
++    /* unsigned int i; */
++    /* unsigned long tmp; */
++    return 0;
++}
++
++    /* 12 34 56 78 ... */
++static int smash_mode3(unsigned long (*base)[2], unsigned int len)
++{
++    unsigned int i;
++    unsigned long tmp;
++if (len >= 4) {
++        for (i=0; i<len/2-1; i++) {
++            tmp = base[i][1];
++            base[i][1] = base[len-1-i][1];
++            base[len-1-i][1] = tmp;
++        }
++        for (i=0; i<len; i += 2) {
++            tmp = base[i][1];
++            base[i][1] = base[i+1][1];
++            base[i+1][1] = tmp;
++        }
++    }
++    return 0;
++}
++
++static int update_dmmu_pte(struct dmmu_handle *h, unsigned long vaddr,
++		           unsigned long (**base)[2], unsigned int len)
++{
++    unsigned long *pgd = (unsigned long *)h->pdg;
++    unsigned long *pte;
++    unsigned int i, index;
++
++    for (i=0; i<len; i++) {
++	index = vaddr>>22;
++        pte = (unsigned long *)(pgd[index] & ~DMMU_PMD_VLD);
++	pte = (unsigned long *)phys_to_virt((unsigned long)pte);
++
++	index = ((vaddr & 0x3ff000) >> 12);
++	pte[index] = (*base)[i][1];
++         vaddr+=0x1000;
++    }
++    return 0;
++}
++
++static int update_process_pte(unsigned long vaddr, unsigned long (**base)[2], unsigned int len)
++{
++    unsigned int i;
++    pgd_t *pgdir;
++    pmd_t *pmdir;
++    pte_t *pte;
++    spin_lock(&current->mm->page_table_lock);
++    for (i=0; i<len; i++) {
++        pgdir = pgd_offset(current->mm, vaddr);
++        if(pgd_none(*pgdir) || pgd_bad(*pgdir))
++            return 0;
++        pmdir = pmd_offset((pud_t *)pgdir, vaddr);
++        if(pmd_none(*pmdir) || pmd_bad(*pmdir))
++            return 0;
++        pte = pte_offset_kernel(pmdir,vaddr);
++        if (pte_present(*pte)){
++	  pte->pte = (*base)[i][1];
++	}
++        vaddr += 4096;
++    }
++    spin_unlock(&current->mm->page_table_lock);
++    return 0;
++}
++
++int dmmu_memory_smash(unsigned long vaddr, int smash_mode)
++{
++	struct dmmu_handle *h = NULL;
++    unsigned long (*list_smash)[2] = NULL;
++    unsigned int list_len = 0;
++	struct vm_area_struct * vma;
++
++	h = find_handle();
++	if(!h){
++		h = create_handle();
++	}
++	if(!h)
++		return -1;
++
++    /* 检查4k对� */
++    if (vaddr & 0xfff){
++        return -1;
++    }
++
++	mutex_lock(&h->lock);
++
++    if (make_smash_list(h, vaddr, &list_smash, &list_len)) {
++	    mutex_unlock(&h->lock);
++        return -1;
++    } else {
++        switch (smash_mode) {
++            case MODE1:
++		print_dbg("smash_mode = %u\n",smash_mode);
++                smash_mode1(list_smash, list_len);
++                break;
++            case MODE2:
++		print_dbg("smash_mode = %u\n",smash_mode);
++                smash_mode2(list_smash, list_len);
++                break;
++            case MODE3:
++		print_dbg("smash_mode = %u\n",smash_mode);
++                smash_mode3(list_smash, list_len);
++                break;
++            default:
++                break;
++        }
++    }
++    update_dmmu_pte(h, vaddr, &list_smash, list_len);
++    update_process_pte(vaddr, &list_smash, list_len);
++
++	dmmu_cache_wback(h);
++	vma = find_vma(current->mm, vaddr);
++	flush_tlb_range(vma, vaddr, vaddr+(list_len*PAGE_SIZE));
++
++	mutex_unlock(&h->lock);
++    kfree(list_smash);
++
++    return 0;
++}
++EXPORT_SYMBOL(dmmu_memory_smash);
++
++static struct map_node *check_map(struct dmmu_handle *h,unsigned long vaddr,unsigned long len)
++{
++	struct list_head *pos, *next;
++	struct map_node *n;
++	list_for_each_safe(pos, next, &h->map_list) {
++		n = list_entry(pos, struct map_node, list);
++		if(vaddr == n->start && len == n->len)
++			return n;
++	}
++	return NULL;
++}
++
++static void handle_add_map(struct device *dev,struct dmmu_handle *h,unsigned long vaddr,unsigned long len)
++{
++	struct map_node *n = kmalloc(sizeof(*n),GFP_KERNEL);
++	if(n == NULL) {
++		printk("malloc map_list node failed !!\n");
++		return;
++	}
++	n->dev = dev;
++	n->start = vaddr;
++	n->len = len;
++	INIT_LIST_HEAD(&n->list);
++	list_add(&n->list,&h->map_list);
++}
++
++static unsigned int get_pfn(unsigned int vaddr)
++{
++	pgd_t *pgdir;
++	pmd_t *pmdir;
++	pte_t *pte;
++	pgdir = pgd_offset(current->mm, vaddr);
++	if(pgd_none(*pgdir) || pgd_bad(*pgdir)) {
++		return 0;
++	}
++	pmdir = pmd_offset((pud_t *)pgdir, vaddr);
++	if(pmd_none(*pmdir) || pmd_bad(*pmdir)) {
++		return 0;
++	}
++	// TODO: 如果是kmap的地�，比如C空间的地�这里需�处�一下使用pte_offset_kmap.
++	pte = pte_offset_kernel(pmdir,vaddr);
++	if (pte_present(*pte)) {
++
++		return pte_pfn(*pte) << PAGE_SHIFT;
++	}
++
++	return 0;
++}
++
++static unsigned long dmmu_v2pfn(unsigned long vaddr)
++{
++	if(vaddr < KSEG0_LOW_LIMIT)
++		return get_pfn(vaddr);
++
++	if(vaddr >= KSEG0_LOW_LIMIT && vaddr < KSEG1_HEIGH_LIMIT)
++		return virt_to_phys((void *)vaddr);
++
++	panic("dmmu_v2pfn error!");
++	return 0;
++}
++
++static unsigned long unmap_node(struct pmd_node *n,unsigned long vaddr,unsigned long end,int check)
++{
++	unsigned int *pte = (unsigned int *)n->page;
++	int index = ((vaddr & 0x3ff000) >> 12);
++	int free = !check || (--n->count == 0);
++	struct page *page = NULL;
++
++	if(vaddr && end) {
++		while(index < 1024 && vaddr < end) {
++			if(pte[index] & MAP_CONUT_MASK) {
++				pte[index] -= MAP_COUNT;
++			} else {
++				page = pfn_to_page(pte[index] >> PAGE_SHIFT);
++
++				ClearPageReserved(page);
++				pte[index] = reserved_pte;
++			}
++			index++;
++			vaddr += 4096;
++		}
++	}
++
++	if(free) {
++		ClearPageReserved(virt_to_page((void *)n->page));
++		free_page(n->page);
++		list_del(&n->list);
++		kfree(n);
++	}
++
++	return vaddr;
++}
++
++static unsigned long map_node(struct pmd_node *n,unsigned int vaddr,unsigned int end)
++{
++	unsigned int *pte = (unsigned int *)n->page;
++	int index = ((vaddr & 0x3ff000) >> 12);
++	struct page * page = NULL;
++	unsigned long pfn = 0;
++
++
++	while(index < 1024 && vaddr < end) {
++		if(pte[index] == reserved_pte) {
++
++			mmap_write_lock(current->mm);
++
++			pfn = dmmu_v2pfn(vaddr) >> PAGE_SHIFT;
++			page = pfn_to_page(pfn);
++
++			SetPageReserved(page);
++
++			pte[index] = (pfn << PAGE_SHIFT) | DMMU_PTE_VLD;
++
++			mmap_write_unlock(current->mm);
++		} else {
++			pte[index] += MAP_COUNT;
++		}
++		index++;
++		vaddr += 4096;
++	}
++	n->count++;
++	return vaddr;
++}
++
++static struct pmd_node *find_node(struct dmmu_handle *h,unsigned int vaddr)
++{
++	struct list_head *pos, *next;
++	struct pmd_node *n;
++
++	list_for_each_safe(pos, next, &h->pmd_list) {
++		n = list_entry(pos, struct pmd_node, list);
++		if(n->index == (vaddr & 0xffc00000))
++			return n;
++	}
++	return NULL;
++}
++
++static struct pmd_node *add_node(struct dmmu_handle *h,unsigned int vaddr)
++{
++	int i;
++	unsigned long *pte;
++	unsigned long *pgd = (unsigned long *)h->pdg;
++	struct pmd_node *n = kmalloc(sizeof(*n),GFP_KERNEL);
++	INIT_LIST_HEAD(&n->list);
++	n->count = 0;
++	n->index = vaddr & 0xffc00000;
++	n->page = __get_free_page(GFP_KERNEL);
++	SetPageReserved(virt_to_page((void *)n->page));
++
++	pte = (unsigned long *)n->page;
++	for(i=0;i<1024;i++)
++		pte[i] = reserved_pte;
++
++	list_add(&n->list, &h->pmd_list);
++
++	pgd[vaddr>>22] = dmmu_v2pfn(n->page) | DMMU_PMD_VLD;
++//	printk(">>>>>>> n->page = %lx, pgd[vaddr>>22] = %lx <<<<<<<\n\n", n->page, pgd[vaddr>>22]);
++	return n;
++}
++
++static struct dmmu_handle *find_handle(void)
++{
++	struct list_head *pos, *next;
++	struct dmmu_handle *h;
++
++	list_for_each_safe(pos, next, &handle_list) {
++		h = list_entry(pos, struct dmmu_handle, list);
++		if(h->tgid == current->tgid)
++			return h;
++	}
++	return NULL;
++}
++
++/**
++* @brief unmap node from map list, clear each pmd_node in pmd_list,
++* 	Not free handle, let dmmu_unmap_all do it.
++*
++* @param h
++*
++* @return
++*/
++static int dmmu_unmap_node_unlock(struct dmmu_handle *h)
++{
++	struct map_node *cn;
++	struct list_head *pos, *next;
++
++	unsigned long vaddr;
++	int len;
++	unsigned long end;
++
++	struct pmd_node *node;
++
++	list_for_each_safe(pos, next, &h->map_list) {
++		/* find and delete a map node from map_list */
++		cn = list_entry(pos, struct map_node, list);
++		vaddr = cn->start;
++		len = cn->len;
++		end = vaddr + len;
++
++		while(vaddr < end) {
++			node = find_node(h,vaddr);
++			if(node)
++				vaddr = unmap_node(node,vaddr,end,1);
++		}
++
++		list_del(&cn->list);
++		kfree(cn);
++	}
++
++
++	return 0;
++
++}
++
++
++void dmmu_mm_release(struct mmu_notifier *mn,
++                struct mm_struct *mm)
++{
++	struct dmmu_handle *h = container_of(mn, struct dmmu_handle, mn);
++
++	printk("===== dmmu release mm (TODO: not checked) ====h: %p\n", h);
++
++	if(h->handle_mm != mm) {
++		return;
++	}
++
++	mutex_lock(&h->lock);
++
++	dmmu_mm_dev_release(h);
++
++	dmmu_unmap_node_unlock(h);
++
++	mutex_unlock(&h->lock);
++}
++
++static const struct mmu_notifier_ops dmmu_mm_notifier_ops = {
++        .release = dmmu_mm_release,
++};
++
++
++static struct dmmu_handle *create_handle(void)
++{
++	struct dmmu_handle *h;
++	unsigned int pgd_index;
++	unsigned long *pgd;
++
++	h = kmalloc(sizeof(struct dmmu_handle),GFP_KERNEL);
++	if(!h)
++		return NULL;
++
++	h->tgid = current->tgid;
++	h->pdg = __get_free_page(GFP_KERNEL);
++	if(!h->pdg) {
++		pr_err("%s %d, Get free page for PGD error\n",
++				__func__, __LINE__);
++		kfree(h);
++		return NULL;
++	}
++	SetPageReserved(virt_to_page((void *)h->pdg));
++
++	pgd = (unsigned long *)h->pdg;
++
++	for (pgd_index=0; pgd_index < PTRS_PER_PGD; pgd_index++)
++		pgd[pgd_index] = res_pte_paddr;
++
++	INIT_LIST_HEAD(&h->list);
++	INIT_LIST_HEAD(&h->pmd_list);
++	INIT_LIST_HEAD(&h->map_list);
++	INIT_LIST_HEAD(&h->dev_notifier_list);
++	mutex_init(&h->lock);
++
++	/* register exit_mmap notify */
++	h->handle_mm = current->mm;
++
++	h->mn.ops = &dmmu_mm_notifier_ops;
++
++	mmu_notifier_register(&h->mn, h->handle_mm);
++
++	list_add(&h->list, &handle_list);
++
++	return h;
++}
++
++static int dmmu_make_present(unsigned long addr,unsigned long end)
++{
++#if 0
++	unsigned long i;
++	for(i = addr; i < end; i += 4096) {
++		*(volatile unsigned char *)(i) = 0;
++	}
++	*(volatile unsigned char *)(end - 1) = 0;
++	return 0;
++#else
++	int ret, len, write;
++	struct vm_area_struct * vma;
++	unsigned long vm_page_prot;
++
++	mmap_write_lock(current->mm);
++	vma = find_vma(current->mm, addr);
++	if (!vma) {
++		printk("dmmu_make_present error. addr=%lx len=%lx\n",addr,end-addr);
++		mmap_write_unlock(current->mm);
++		return -1;
++	}
++
++	if(vma->vm_flags & VM_PFNMAP) {
++		mmap_write_unlock(current->mm);
++		return 0;
++	}
++	write = (vma->vm_flags & VM_WRITE) != 0;
++	BUG_ON(addr >= end);
++	BUG_ON(end > vma->vm_end);
++
++	vm_page_prot = pgprot_val(vma->vm_page_prot);
++	vma->vm_page_prot = __pgprot(vm_page_prot | _PAGE_VALID| _PAGE_ACCESSED | _PAGE_PRESENT);
++
++	len = DIV_ROUND_UP(end, PAGE_SIZE) - addr/PAGE_SIZE;
++	ret = get_user_pages(addr, len, write, NULL, NULL);
++	vma->vm_page_prot = __pgprot(vm_page_prot);
++	if (ret < 0) {
++		printk("dmmu_make_present get_user_pages error(%d). addr=%lx len=%lx\n",0-ret,addr,end-addr);
++		mmap_write_unlock(current->mm);
++		return ret;
++	}
++
++	mmap_write_unlock(current->mm);
++	return ret == len ? 0 : -1;
++#endif
++}
++
++static void dmmu_cache_wback(struct dmmu_handle *h)
++{
++	struct list_head *pos, *next;
++	struct pmd_node *n;
++
++	dma_cache_wback(h->pdg,PAGE_SIZE);
++
++	list_for_each_safe(pos, next, &h->pmd_list) {
++		n = list_entry(pos, struct pmd_node, list);
++		dma_cache_wback(n->page,PAGE_SIZE);
++	}
++}
++
++static void dmmu_dump_handle(struct seq_file *m, void *v, struct dmmu_handle *h);
++
++unsigned long dmmu_map(struct device *dev,unsigned long vaddr,unsigned long len)
++{
++	int end = vaddr + len;
++	struct dmmu_handle *h;
++	struct pmd_node *node;
++
++	h = find_handle();
++	if(!h)
++		h = create_handle();
++	if(!h)
++		return 0;
++
++	mutex_lock(&h->lock);
++#ifdef DEBUG
++	printk("(pid %d)dmmu_map %lx %lx================================================\n",h->tgid,vaddr,len);
++#endif
++	if(check_map(h,vaddr,len))
++	{
++		mutex_unlock(&h->lock);
++		return dmmu_v2pfn(h->pdg);
++	}
++
++	if(dmmu_make_present(vaddr,vaddr+len))
++	{
++		mutex_unlock(&h->lock);
++		return 0;
++	}
++
++	handle_add_map(dev,h,vaddr,len);
++
++	while(vaddr < end) {
++		node = find_node(h,vaddr);
++		if(!node) {
++			node = add_node(h,vaddr);
++		}
++		vaddr = map_node(node,vaddr,end);
++	}
++	dmmu_cache_wback(h);
++#ifdef DEBUG
++	dmmu_dump_handle(NULL,NULL,h);
++#endif
++	mutex_unlock(&h->lock);
++
++	return dmmu_v2pfn(h->pdg);
++}
++EXPORT_SYMBOL(dmmu_map);
++
++static int dmmu_mm_dev_release(struct dmmu_handle *h)
++{
++	struct dmmu_mm_notifier *n = NULL;
++	struct list_head *pos, *next;
++
++	list_for_each_safe(pos, next, &h->dev_notifier_list) {
++		n = list_entry(pos, struct dmmu_mm_notifier, list);
++		if(n && n->ops && n->ops->mm_release) {
++			n->ops->mm_release(n->data);
++		}
++
++		list_del(&n->list);
++	}
++
++
++	return 0;
++}
++
++
++int dmmu_register_mm_notifier(struct dmmu_mm_notifier *dmn)
++{
++	int dev_already_registered = 0;
++	struct dmmu_mm_notifier *n = NULL;
++	struct dmmu_handle *h;
++	struct list_head *pos, *next;
++
++	h = find_handle();
++	if(!h) {
++		return -EINVAL;
++	}
++
++	mutex_lock(&h->lock);
++
++	list_for_each_safe(pos, next, &h->dev_notifier_list) {
++		n = list_entry(pos, struct dmmu_mm_notifier, list);
++
++		if(n == dmn) {
++			/* already in dev_notifier_list*/
++			dev_already_registered = 1;
++		}
++
++	}
++
++	if(dev_already_registered) {
++		goto out;
++	}
++
++	list_add_tail(&dmn->list, &h->dev_notifier_list);
++out:
++	mutex_unlock(&h->lock);
++	return 0;
++}
++EXPORT_SYMBOL(dmmu_register_mm_notifier);
++
++int dmmu_unmap(struct device *dev,unsigned long vaddr, int len)
++{
++	unsigned long end = vaddr + len;
++	struct dmmu_handle *h;
++	struct pmd_node *node;
++	struct map_node *n;
++
++	h = find_handle();
++	if(!h) {
++		return 0;
++	}
++
++	mutex_lock(&h->lock);
++#ifdef DEBUG
++	/*This printk can cause a memory leak. */
++	printk("dmmu_unmap %lx %x**********************************************\n",vaddr,len);
++#endif
++	n = check_map(h,vaddr,len);
++	if(!n) {
++		mutex_unlock(&h->lock);
++		return -EAGAIN;
++	}
++	if(n->dev != dev) {
++		mutex_unlock(&h->lock);
++		return -EAGAIN;
++	}
++
++	list_del(&n->list);
++	kfree(n);
++
++	while(vaddr < end) {
++		node = find_node(h,vaddr);
++		if(node)
++			vaddr = unmap_node(node,vaddr,end,1);
++	}
++
++	if(list_empty(&h->pmd_list) && list_empty(&h->map_list)) {
++		list_del(&h->list);
++		ClearPageReserved(virt_to_page((void *)h->pdg));
++		free_page(h->pdg);
++		mutex_unlock(&h->lock);
++
++		mmu_notifier_unregister(&h->mn, h->handle_mm);
++
++		kfree(h);
++		return 0;
++	}
++
++	mutex_unlock(&h->lock);
++	return 0;
++}
++EXPORT_SYMBOL(dmmu_unmap);
++
++int dmmu_free_all(struct device *dev)
++{
++	struct dmmu_handle *h;
++	struct pmd_node *node;
++	struct map_node *cn;
++	struct list_head *pos, *next;
++
++	h = find_handle();
++	if(!h)
++		return 0;
++
++	mutex_lock(&h->lock);
++
++	list_for_each_safe(pos, next, &h->map_list) {
++		cn = list_entry(pos, struct map_node, list);
++		node = find_node(h,cn->start);
++		if(node)
++			unmap_node(node,cn->start,cn->len,1);
++		list_del(&cn->list);
++		kfree(cn);
++	}
++
++	list_for_each_safe(pos, next, &h->pmd_list) {
++		node = list_entry(pos, struct pmd_node, list);
++		if(node){
++			printk("WARN: pmd list should NULL\n");
++			unmap_node(node,0,0,0);
++		}
++	}
++
++	list_del(&h->list);
++	ClearPageReserved(virt_to_page((void *)h->pdg));
++	free_page(h->pdg);
++
++	mutex_unlock(&h->lock);
++	mmu_notifier_unregister(&h->mn, h->handle_mm);
++	kfree(h);
++	return 0;
++}
++
++/**
++* @brief release all resources, which should be called by driver close
++*
++* @param dev
++*
++* @return
++*/
++int dmmu_unmap_all(struct device *dev)
++{
++	struct dmmu_handle *h;
++	struct map_node *cn;
++	struct list_head *pos, *next;
++
++#ifdef DEBUG
++	printk("dmmu_unmap_all\n");
++#endif
++
++	h = find_handle();
++	if(!h) {
++		printk("dmmu unmap all not find hindle, maybe it has benn freed already, name: %s\n", dev->kobj.name);
++		return 0;
++	}
++
++	list_for_each_safe(pos, next, &h->map_list) {
++		cn = list_entry(pos, struct map_node, list);
++		if(dev == cn->dev) {
++			dmmu_unmap(dev,cn->start,cn->len);
++		}
++	}
++
++
++	if(list_empty(&h->map_list))
++		dmmu_free_all(dev);
++	return 0;
++}
++EXPORT_SYMBOL(dmmu_unmap_all);
++int __init dmmu_init(void)
++{
++	unsigned int pte_index;
++	unsigned long res_page_paddr;
++	unsigned long reserved_page;
++	unsigned int *res_pte_vaddr;
++
++	reserved_page = __get_free_page(GFP_KERNEL);
++	if (!reserved_page) {
++		pr_err("%s %d, Get reserved page error\n",
++				__func__, __LINE__);
++		return ENOMEM;
++	}
++	SetPageReserved(virt_to_page((void *)reserved_page));
++	reserved_pte = dmmu_v2pfn(reserved_page) | DMMU_PTE_VLD;
++
++	res_page_paddr = virt_to_phys((void *)reserved_page) | 0xFFF;
++
++	res_pte_vaddr = (unsigned int *)__get_free_page(GFP_KERNEL);
++	if (!res_pte_vaddr) {
++		pr_err("%s %d, Get free page for PTE error\n",
++				__func__, __LINE__);
++		free_page(reserved_page);
++		return ENOMEM;
++	}
++	SetPageReserved(virt_to_page(res_pte_vaddr));
++	res_pte_paddr = virt_to_phys((void *)res_pte_vaddr) | DMMU_PTE_VLD;
++
++	for (pte_index = 0; pte_index < PTRS_PER_PTE; pte_index++)
++		res_pte_vaddr[pte_index] = res_page_paddr;
++	printk("%s %d PTRS_PER_PTE = %lu\n",__func__,__LINE__,PTRS_PER_PTE);
++
++	return 0;
++}
++arch_initcall(dmmu_init);
++
++void dmmu_dump_vaddr(unsigned long vaddr)
++{
++	struct dmmu_handle *h;
++	struct pmd_node *node;
++
++	unsigned long *pmd,*pte;
++	h = find_handle();
++	if(!h) {
++		printk("dmmu_dump_vaddr %08lx error - h not found!\n",vaddr);
++		return;
++	}
++
++	node = find_node(h,vaddr);
++	if(!node) {
++		printk("dmmu_dump_vaddr %08lx error - node not found!\n",vaddr);
++		return;
++	}
++
++	pmd = (unsigned long *)h->pdg;
++	pte = (unsigned long *)node->page;
++
++	printk("pmd base = %p; pte base = %p\n",pmd,pte);
++	printk("pmd = %08lx; pte = %08lx\n",pmd[vaddr>>22],pte[(vaddr&0x3ff000)>>12]);
++}
++
++static void dmmu_dump_handle(struct seq_file *m, void *v, struct dmmu_handle *h)
++{
++	struct list_head *pos, *next;
++	struct map_node *n;
++
++	list_for_each_safe(pos, next, &h->map_list) {
++		n = list_entry(pos, struct map_node, list);
++		{
++			int i = 0;
++			int vaddr = n->start;
++			struct pmd_node *pn = find_node(h,vaddr);
++			unsigned int *pte = (unsigned int *)pn->page;
++
++			while(vaddr < (n->start + n->len)) {
++				if(i++%8 == 0)
++					printk("\nvaddr %08x : ",vaddr & 0xfffff000);
++				printk("%08x ",pte[(vaddr & 0x3ff000)>>12]);
++				vaddr += 4096;
++			}
++			printk("\n\n");
++		}
++	}
++}
++
++static int dmmu_proc_show(struct seq_file *m, void *v)
++{
++	struct list_head *pos, *next;
++	struct dmmu_handle *h;
++	volatile unsigned long flags;
++	local_irq_save(flags);
++		list_for_each_safe(pos, next, &handle_list) {
++			h = list_entry(pos, struct dmmu_handle, list);
++			dmmu_dump_handle(m, v, h);
++		}
++	local_irq_restore(flags);
++	return 0;
++}
++
++static int dmmu_open(struct inode *inode, struct file *file)
++{
++	return single_open(file, dmmu_proc_show, PDE_DATA(inode));
++}
++
++static const struct proc_ops dmmus_proc_fops ={
++	.proc_read = seq_read,
++	.proc_open = dmmu_open,
++	.proc_lseek = seq_lseek,
++	.proc_release = single_release,
++};
++
++static int __init init_dmmu_proc(void)
++{
++	struct proc_dir_entry *p;
++	p = jz_proc_mkdir("dmmu");
++	if (!p) {
++		printk("create_proc_entry for common dmmu failed.\n");
++		return -ENODEV;
++	}
++	proc_create("dmmus", 0600,p,&dmmus_proc_fops);
++
++	return 0;
++}
++
++module_init(init_dmmu_proc);
+diff --git a/arch/mips/xburst2/soc-x2000/pm.c b/arch/mips/xburst2/soc-x2000/pm.c
+new file mode 100644
+index 000000000..c55425d5c
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/pm.c
+@@ -0,0 +1,539 @@
++#include <linux/init.h>
++#include <linux/pm.h>
++#include <linux/suspend.h>
++
++#include <soc/gpio.h>
++#include <linux/gpio.h>
++
++#include <soc/cache.h>
++#include <soc/base.h>
++#include <asm/io.h>
++#include <soc/ddr.h>
++#include <soc/base.h>
++#include <soc/cpm.h>
++#include "pm.h"
++#if defined CONFIG_KP_AXP
++#include <linux/regulator/machine.h>
++#endif
++
++
++
++//#define X2000_IDLE_PD
++// #define X2000_SLEEP_GPIO	GPIO_PB(30)
++
++#ifdef DEBUG_PM
++static void x2000_pm_gate_check(void)
++{
++	unsigned int gate0 = cpm_inl(CPM_CLKGR);
++	unsigned int gate1 = cpm_inl(CPM_CLKGR1);
++	int i;
++	int x;
++
++	printk("gate0 = 0x%08x\n", gate0);
++	printk("gate1 = 0x%08x\n", gate1);
++	for (i = 0; i < 32; i++) {
++		x = (gate0 >> i) & 1;
++		if (x == 0)
++			printk("warning : bit[%d] in clk gate0 is enabled\n", i);
++	}
++	for (i = 0; i < 32; i++) {
++		x = (gate1 >> i) & 1;
++		if (x == 0)
++			printk("warning : bit[%d] in clk gate1 is enabled\n", i);
++	}
++
++}
++#endif
++
++
++
++
++static inline void ddrp_auto_calibration(void)
++{
++	unsigned int reg_val = ddr_readl(DDRP_INNOPHY_TRAINING_CTRL);
++	unsigned int timeout = 0xffffff;
++	unsigned int wait_cal_done = DDRP_CALIB_DONE_HDQCFA | DDRP_CALIB_DONE_LDQCFA;
++
++	reg_val &= ~(DDRP_TRAINING_CTRL_DSCSE_BP);
++	reg_val |= DDRP_TRAINING_CTRL_DSACE_START;
++	ddr_writel(reg_val, DDRP_INNOPHY_TRAINING_CTRL);
++
++	while(!((ddr_readl(DDRP_INNOPHY_CALIB_DONE) & wait_cal_done) == wait_cal_done) && --timeout) {
++		TCSM_PCHAR('t');
++	}
++
++	if(!timeout) {
++		TCSM_PCHAR('f');
++	}
++	ddr_writel(0, DDRP_INNOPHY_TRAINING_CTRL);
++}
++
++
++
++
++static void load_func_to_tcsm(unsigned int *tcsm_addr,unsigned int *f_addr,unsigned int size)
++{
++	unsigned int instr;
++	int offset;
++	int i;
++#ifdef DEBUG_PM
++	printk("tcsm addr = %p %p size = %d\n",tcsm_addr,f_addr,size);
++#endif
++	for(i = 0;i < size / 4;i++) {
++		instr = f_addr[i];
++		if((instr >> 26) == 2){
++			offset = instr & 0x3ffffff;
++			offset = (offset << 2) - ((unsigned int)f_addr & 0xfffffff);
++			if(offset > 0) {
++				offset = ((unsigned int)tcsm_addr & 0xfffffff) + offset;
++				instr = (2 << 26) | (offset >> 2);
++			}
++		}
++		tcsm_addr[i] = instr;
++	}
++}
++
++
++#ifdef X2000_IDLE_PD
++static int soc_pm_idle_pd(void)
++{
++	unsigned int lcr = cpm_inl(CPM_LCR);
++	unsigned int opcr = cpm_inl(CPM_OPCR);
++
++	lcr &=~ 0x3; // low power mode: IDLE
++	lcr |= 2;
++	cpm_outl(lcr, CPM_LCR);
++
++	opcr &= ~ (1<<31);
++	opcr |= (1 << 30);
++	opcr &= ~(1 << 26);	//l2c power down
++	opcr |= 1 << 2; // select RTC clk
++	cpm_outl(opcr, CPM_OPCR);
++
++	return 0;
++}
++#else
++static int soc_pm_idle(void)
++{
++	unsigned int lcr = cpm_inl(CPM_LCR);
++	unsigned int opcr = cpm_inl(CPM_OPCR);
++
++	lcr &=~ 0x3; // low power mode: IDLE
++	cpm_outl(lcr, CPM_LCR);
++
++	opcr &= ~(1 << 30);
++	opcr &= ~(1 << 31);
++	cpm_outl(opcr, CPM_OPCR);
++
++	return 0;
++}
++#endif
++
++static int soc_pm_sleep(void)
++{
++	unsigned int lcr = cpm_inl(CPM_LCR);
++	unsigned int opcr = cpm_inl(CPM_OPCR);
++
++	lcr &=~ 0x3;
++	lcr |= 1 << 0; // low power mode: SLEEP
++	cpm_outl(lcr, CPM_LCR);
++
++	opcr &= ~(1 << 31);
++	opcr |= (1 << 30);
++	opcr &= ~(1 << 26); //L2C power down
++	opcr |= (1 << 21); // cpu 32k ram retention.
++	opcr |= (1 << 3); // power down CPU
++	opcr &= ~(1 << 4); // exclk disable;
++	opcr |= (1 << 2); // select RTC clk
++	opcr |= (1 << 22);
++	opcr |= (1 << 20);
++	cpm_outl(opcr, CPM_OPCR);
++
++	return 0;
++}
++
++static int soc_post_wakeup(void)
++{
++	unsigned int lcr = cpm_inl(CPM_LCR);
++	lcr &= ~0x3; // low power mode: IDLE
++	cpm_outl(lcr, CPM_LCR);
++
++	printk("post wakeup!\n");
++
++
++	{
++		/* after power down cpu by set PD in OPCR, resume cpu's frequency and L2C's freq */
++		unsigned int val;
++
++		/* change disable */
++		val = cpm_inl(CPM_CPCCR);
++		val &= ~(1 << 22);
++		cpm_outl(val, CPM_CPCCR);
++
++		/* resume cpu_div in CPCCR */
++		val &= ~0xf;
++		val |= sleep_param->cpu_div;
++		cpm_outl(val, CPM_CPCCR);
++
++		/* change enable */
++		val |= (1 << 22);
++		cpm_outl(val, CPM_CPCCR);
++
++		while (cpm_inl(CPM_CPCSR) & 1);
++	}
++	return 0;
++}
++
++static noinline void cpu_resume_bootup(void)
++{
++	TCSM_PCHAR('X');
++	/* set reset entry */
++	*(volatile unsigned int *)0xb2200f00 = 0xbfc00000;
++
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"move $29, %0	\n\t"
++		"jr.hb   %1	\n\t"
++		"nop		\n\t"
++		".set pop	\n\t"
++		:
++		:"r" (SLEEP_CPU_RESUME_SP), "r"(SLEEP_CPU_RESUME_TEXT)
++		:
++		);
++
++}
++static noinline void cpu_resume(void)
++{
++	unsigned int ddrc_ctrl;
++
++	TCSM_PCHAR('R');
++
++#ifdef X2000_SLEEP_GPIO
++	/* resume normal voltage */
++	gpio_writel(1 << (X2000_SLEEP_GPIO % 32), GPIO_PXPAT0S(X2000_SLEEP_GPIO / 32));
++	/* wait voltage to stabilize unit: 3.33ns*/
++	TCSM_DELAY(300000);
++	/* resume clk div */
++	cpm_writel(0x55700000 | (sleep_param->cpccr & 0xFFFFF), CPM_CPCCR);
++	while(cpm_readl(CPM_CPCSR) & 7);
++	/* resume clk source */
++	cpm_writel(sleep_param->cpccr, CPM_CPCCR);
++	while((cpm_readl(CPM_CPCSR) & 0xf0000000) != 0xf0000000);
++#endif
++
++	if (sleep_param->state == PM_SUSPEND_MEM) {
++		int tmp;
++
++		/* enable pll */
++		tmp = reg_ddr_phy(0x21);
++		tmp &= ~(1 << 1);
++		reg_ddr_phy(0x21) = tmp;
++
++		while (!(reg_ddr_phy(0x32) & 0x8))
++			serial_put_hex(reg_ddr_phy(0x32));
++
++		/* dfi_init_start = 0, wait dfi_init_complete */
++		*(volatile unsigned int *)0xb3012000 &= ~(1 << 3);
++		while(!(*(volatile unsigned int *)0xb3012004 & 0x1));
++
++		/* bufferen_core = 1 */
++		tmp = rtc_read_reg(0xb0003048);
++		tmp |= (1 << 21);
++		rtc_write_reg(0xb0003048, tmp);
++
++		/* exit sr */
++		ddrc_ctrl = ddr_readl(DDRC_CTRL);
++		ddrc_ctrl &= ~(1<<5);
++		ddr_writel(ddrc_ctrl, DDRC_CTRL);
++
++		while(ddr_readl(DDRC_STATUS) & (1<<2));
++
++		TCSM_DELAY(1000);
++		TCSM_PCHAR('1');
++		ddrp_auto_calibration();
++		TCSM_PCHAR('2');
++
++		/* restore ddr auto-sr */
++		ddr_writel(sleep_param->autorefresh, DDRC_AUTOSR_EN);
++		TCSM_PCHAR('3');
++
++		/* restore ddr LPEN */
++		ddr_writel(sleep_param->dlp, DDRC_DLP);
++
++		/* restore ddr deep power down state */
++		ddrc_ctrl = ddr_readl(DDRC_CTRL);
++		ddrc_ctrl |= sleep_param->pdt;
++		ddrc_ctrl |= sleep_param->dpd;
++		ddr_writel(ddrc_ctrl, DDRC_CTRL);
++
++		TCSM_PCHAR('4');
++	}
++
++
++	TCSM_PCHAR('5');
++
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"jr.hb %0	\n\t"
++		"nop		\n\t"
++		".set pop 	\n\t"
++		:
++		: "r" (restore_goto)
++		:
++		);
++}
++
++
++static noinline void cpu_sleep(void)
++{
++
++
++	sleep_param->cpu_div = cpm_inl(CPM_CPCCR) & 0xf;
++
++	blast_dcache32();
++	blast_scache64();
++	__sync();
++	__fast_iob();
++
++	{
++		/* before power down cpu by set PD in OPCR, reduce cpu's frequency as the same as L2C's freq */
++		unsigned int val, div;
++
++		/* change disable */
++		val = cpm_inl(CPM_CPCCR);
++		val &= ~(1 << 22);
++		cpm_outl(val, CPM_CPCCR);
++
++		/* div cpu = div l2c */
++		div = val & (0xf << 4);
++		val &= ~0xf;
++		val |= (div >> 4);
++		cpm_outl(val, CPM_CPCCR);
++
++		/* change enable */
++		val |= (1 << 22);
++		cpm_outl(val, CPM_CPCCR);
++
++		while (cpm_inl(CPM_CPCSR) & 1);
++	}
++
++	TCSM_PCHAR('D');
++
++	if (sleep_param->state == PM_SUSPEND_MEM) {
++		unsigned int tmp;
++		unsigned int ddrc_ctrl;
++
++		ddrc_ctrl = ddr_readl(DDRC_CTRL);
++
++		/* save ddr low power state */
++		sleep_param->pdt = ddrc_ctrl & DDRC_CTRL_PDT_MASK;
++		sleep_param->dpd = ddrc_ctrl & DDRC_CTRL_DPD;
++		sleep_param->dlp = ddr_readl(DDRC_DLP);
++		sleep_param->autorefresh = ddr_readl(DDRC_AUTOSR_EN);
++
++		/* ddr disable deep power down */
++		ddrc_ctrl &= ~(DDRC_CTRL_PDT_MASK);
++		ddrc_ctrl &= ~(DDRC_CTRL_DPD);
++		ddr_writel(ddrc_ctrl, DDRC_CTRL);
++
++		/* ddr diasble LPEN*/
++		ddr_writel(0, DDRC_DLP);
++
++		/* ddr disable auto-sr */
++		ddr_writel(0, DDRC_AUTOSR_EN);
++		tmp = *(volatile unsigned int *)0xa0000000;
++
++		/* DDR self refresh */
++		ddrc_ctrl = ddr_readl(DDRC_CTRL);
++		ddrc_ctrl |= 1 << 5;
++		ddr_writel(ddrc_ctrl, DDRC_CTRL);
++		while(!(ddr_readl(DDRC_STATUS) & (1<<2)));
++
++
++		/* bufferen_core = 0 */
++		tmp = rtc_read_reg(0xb0003048);
++		tmp &= ~(1 << 21);
++		rtc_write_reg(0xb0003048, tmp);
++
++
++		/* dfi_init_start = 1 */
++		*(volatile unsigned int *)0xb3012000 |= (1 << 3);
++
++		{
++			int i;
++			for (i = 0; i < 4; i++) {
++
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++			}
++		}
++
++		/* disable pll */
++		reg_ddr_phy(0x21) |= (1 << 1);
++	}
++
++	TCSM_PCHAR('W');
++
++#ifdef X2000_SLEEP_GPIO
++	sleep_param->cpccr = cpm_readl(CPM_CPCCR);
++	/* set cpu clk to 24M */
++	cpm_writel(0x55700000,CPM_CPCCR);
++	while((cpm_readl(CPM_CPCSR) & 0xf0000007) != 0xf0000000);
++	gpio_writel(1 << (X2000_SLEEP_GPIO % 32), GPIO_PXPAT0C(X2000_SLEEP_GPIO / 32));
++#endif
++
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"wait		\n\t"
++		"nop		\n\t"
++		"nop		\n\t"
++		"nop		\n\t"
++		".set pop	\n\t"
++	);
++
++	TCSM_PCHAR('N');
++
++	TCSM_PCHAR('\r');
++	TCSM_PCHAR('\n');
++	TCSM_PCHAR('?');
++	TCSM_PCHAR('?');
++	TCSM_PCHAR('?');
++	TCSM_PCHAR('\r');
++	TCSM_PCHAR('\n');
++
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"jr.hb %0	\n\t"
++		"nop		\n\t"
++		".set pop 	\n\t"
++		:
++		: "r" (SLEEP_CPU_RESUME_BOOTUP_TEXT)
++		:
++		);
++	TCSM_PCHAR('F');
++}
++
++
++int x2000_pm_enter(suspend_state_t state)
++{
++	extern volatile u8 *uart_base;
++
++	printk("x2000 pm enter!!\n");
++
++	sleep_param->uart_base = (unsigned int)uart_base;
++
++	sleep_param->state = state;
++
++#ifdef DEBUG_PM
++	printk("sleep_param->state addr =  %d\n", sleep_param->state);
++#endif
++
++	load_func_to_tcsm((unsigned int *)SLEEP_CPU_RESUME_BOOTUP_TEXT, (unsigned int *)cpu_resume_bootup, SLEEP_CPU_RESUME_BOOTUP_LEN);
++	load_func_to_tcsm((unsigned int *)SLEEP_CPU_RESUME_TEXT, (unsigned int *)cpu_resume, SLEEP_CPU_RESUME_LEN);
++	load_func_to_tcsm((unsigned int *)SLEEP_CPU_SLEEP_TEXT, (unsigned int *)cpu_sleep, SLEEP_CPU_SLEEP_LEN);
++
++	if (state == PM_SUSPEND_STANDBY) {
++#ifdef X2000_IDLE_PD
++		soc_pm_idle_pd();
++#else
++		soc_pm_idle();
++#endif
++	} else if (state == PM_SUSPEND_MEM) {
++		soc_pm_sleep();
++	} else {
++		printk("WARNING : unsupport pm suspend state\n");
++	}
++
++
++	/* set reset entry */
++	*(volatile unsigned int *)0xb2200f00 = SLEEP_CPU_RESUME_BOOTUP_TEXT;
++
++
++#ifdef DEBUG_PM
++	printk("LCR: %08x\n", cpm_inl(CPM_LCR));
++	printk("OPCR: %08x\n", cpm_inl(CPM_OPCR));
++	x2000_pm_gate_check();
++#endif
++
++	mb();
++	save_goto((unsigned int)SLEEP_CPU_SLEEP_TEXT);
++	mb();
++
++	soc_post_wakeup();
++
++	return 0;
++}
++
++static int x2000_pm_begin(suspend_state_t state)
++{
++	printk("x2000 suspend begin\n");
++	return 0;
++}
++
++static void x2000_pm_end(void)
++{
++	printk("x2000 pm end!\n");
++}
++#if defined CONFIG_KP_AXP
++static int x2000_suspend_prepare(void)
++{
++	return regulator_suspend_prepare(PM_SUSPEND_MEM);
++}
++static void x2000_suspend_finish(void)
++{
++	if (regulator_suspend_finish())
++		pr_err("%s: Suspend finish failed\n", __func__);
++}
++#endif
++
++static int ingenic_pm_valid(suspend_state_t state)
++{
++	switch (state) {
++		case PM_SUSPEND_ON:
++		case PM_SUSPEND_STANDBY:
++		case PM_SUSPEND_MEM:
++			return 1;
++
++		default:
++			return 0;
++	}
++}
++static const struct platform_suspend_ops x2000_pm_ops = {
++	.valid		= ingenic_pm_valid,
++	.begin		= x2000_pm_begin,
++	.enter		= x2000_pm_enter,
++	.end		= x2000_pm_end,
++#if defined CONFIG_KP_AXP
++	.prepare = x2000_suspend_prepare,
++	.finish = x2000_suspend_finish,
++#endif
++};
++
++/*
++ * Initialize suspend interface
++ */
++static int __init pm_init(void)
++{
++
++#ifdef X2000_SLEEP_GPIO
++	gpio_request(X2000_SLEEP_GPIO, "sleep_gpio");
++	gpio_direction_output(X2000_SLEEP_GPIO, 1);
++#endif
++
++	suspend_set_ops(&x2000_pm_ops);
++
++
++	return 0;
++}
++
++late_initcall(pm_init);
+diff --git a/arch/mips/xburst2/soc-x2000/pm.h b/arch/mips/xburst2/soc-x2000/pm.h
+new file mode 100644
+index 000000000..5799b6399
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/pm.h
+@@ -0,0 +1,169 @@
++
++
++
++struct sleep_param {
++	suspend_state_t state;
++	unsigned int pdt;
++	unsigned int dpd;
++	unsigned int dlp;
++	unsigned int autorefresh;
++	unsigned int cpu_div;
++	unsigned int uart_base;
++	unsigned int cpccr;
++};
++
++
++/*
++ *
++ *	|-----------------------|
++ *	|			|
++ *	|			|
++ *	|	RESUME_SP	|
++ *	|			|
++ *	|-----------------------|
++ *	|			|
++ *	|  	  PARAM		|
++ *	|			|
++ *	|-----------------------|
++ *	|			|
++ *	|			|
++ *	|	SLEEP_TEXT      |
++ *	|			|
++ *	|			|
++ *	|-----------------------|
++ *	|			|
++ *	|			|
++ *	|	RESUME_TEXT	|
++ *	|			|
++ *	|			|
++ *	|-----------------------|
++ *	|			|
++*	|  RESUME_BOOTU_TEXTP	|
++ *	|			|
++ *	|-----------------------|     <------------ TCSM_START 0xb2400000
++ *
++ */
++
++
++#define SLEEP_MEMORY_START		0xb2400000
++#define SLEEP_MEMORY_END		0xb2407ff8
++#define SLEEP_RESUME_SP			SLEEP_MEMORY_END
++#define SLEEP_RESUME_BOOTUP_TEXT	SLEEP_MEMORY_START
++
++#define SLEEP_CPU_RESUME_BOOTUP_TEXT	SLEEP_RESUME_BOOTUP_TEXT
++#define SLEEP_CPU_RESUME_BOOTUP_LEN	64 // 16 instructions
++#define SLEEP_CPU_RESUME_TEXT		(SLEEP_CPU_RESUME_BOOTUP_TEXT + SLEEP_CPU_RESUME_BOOTUP_LEN)
++#define SLEEP_CPU_RESUME_LEN		(4096)
++#define SLEEP_CPU_SLEEP_TEXT		(SLEEP_CPU_RESUME_TEXT + SLEEP_CPU_RESUME_LEN)
++#define SLEEP_CPU_SLEEP_LEN		(3072)
++#define SLEEP_CPU_PARAM_ADDR		(SLEEP_CPU_SLEEP_TEXT + SLEEP_CPU_SLEEP_LEN)
++#define SLEEP_CPU_PARAM_SIZE		(sizeof(struct sleep_param))
++#define SLEEP_CPU_RESUME_SP		SLEEP_RESUME_SP
++
++#define sleep_param ((struct sleep_param *)SLEEP_CPU_PARAM_ADDR)
++
++
++
++extern long long save_goto(unsigned int func);
++extern int restore_goto(unsigned int func);
++
++
++#define reg_ddr_phy(x)   (*(volatile unsigned int *)(0xb3011000 + ((x) << 2)))
++
++#define rtc_read_reg(reg) ({ \
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) ); \
++	*(volatile unsigned int *)reg;\
++})
++
++#define rtc_write_reg(reg, val) do{ \
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) ); \
++	*(volatile unsigned int *)0xb000303c = 0xa55a; \
++	while (!((*(volatile unsigned int *)0xb000303c >> 31) & 0x1) ); \
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) ); \
++	*(volatile unsigned int *)reg = val; \
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) ); \
++}while(0)
++
++#define readb(addr)     (*(volatile unsigned char *)(addr))
++#define readw(addr)     (*(volatile unsigned short *)(addr))
++#define readl(addr)     (*(volatile unsigned int *)(addr))
++#define writeb(b, addr) (*(volatile unsigned char *)(addr)) = (b)
++#define writew(b, addr) (*(volatile unsigned short *)(addr)) = (b)
++#define writel(b, addr) (*(volatile unsigned int *)(addr)) = (b)
++
++#define GPIO_PXPIN(n)	(0x00 + (n) * 0x100) /* PIN Level Register */
++#define GPIO_PXINT(n)	(0x10 + (n) * 0x100) /* Port Interrupt Register */
++#define GPIO_PXINTS(n)	(0x14 + (n) * 0x100) /* Port Interrupt Set Register */
++#define GPIO_PXINTC(n)	(0x18 + (n) * 0x100) /* Port Interrupt Clear Register */
++#define GPIO_PXMASK(n)	(0x20 + (n) * 0x100) /* Port Interrupt Mask Register */
++#define GPIO_PXMASKS(n)	(0x24 + (n) * 0x100) /* Port Interrupt Mask Set Reg */
++#define GPIO_PXMASKC(n)	(0x28 + (n) * 0x100) /* Port Interrupt Mask Clear Reg */
++#define GPIO_PXPAT1(n)	(0x30 + (n) * 0x100) /* Port Pattern 1 Register */
++#define GPIO_PXPAT1S(n)	(0x34 + (n) * 0x100) /* Port Pattern 1 Set Reg. */
++#define GPIO_PXPAT1C(n)	(0x38 + (n) * 0x100) /* Port Pattern 1 Clear Reg. */
++#define GPIO_PXPAT0(n)	(0x40 + (n) * 0x100) /* Port Pattern 0 Register */
++#define GPIO_PXPAT0S(n)	(0x44 + (n) * 0x100) /* Port Pattern 0 Set Register */
++#define GPIO_PXPAT0C(n)	(0x48 + (n) * 0x100) /* Port Pattern 0 Clear Register */
++#define GPIO_PXFLG(n)	(0x50 + (n) * 0x100) /* Port Flag Register */
++#define GPIO_PXFLGC(n)	(0x58 + (n) * 0x100) /* Port Flag clear Register */
++#define GPIO_PXPU(n)	(0x80 + (n) * 0x100) /* PORT PULL-UP State Register */
++#define GPIO_PXPUS(n)	(0x84 + (n) * 0x100) /* PORT PULL-UP State Set Register*/
++#define GPIO_PXPUC(n)	(0x88 + (n) * 0x100) /* PORT PULL-UP State Clear Register */
++#define GPIO_PXPD(n)	(0x90 + (n) * 0x100) /* PORT PULL-DOWN State Register */
++#define GPIO_PXPDS(n)	(0x94 + (n) * 0x100) /* PORT PULL-DOWN State Set Register */
++#define GPIO_PXPDC(n)	(0x98 + (n) * 0x100) /* PORT PULL-DOWN State Set Register */
++
++#define gpio_readl(o)		readl(0xb0010000 + (o))
++#define gpio_writel(b, o)	writel(b, 0xb0010000 + (o))
++
++#define cpm_readl(o)		readl(0xb0000000 + (o))
++#define cpm_writel(b, o)	writel(b, 0xb0000000 + (o))
++
++/************************************************
++ *		debug interface
++ ***********************************************/
++
++#define DEBUG_PM
++#define PRINT_DEBUG
++
++
++#define U_IOBASE (sleep_param->uart_base)
++
++#define OFF_TDR         (0x00)
++#define OFF_LCR         (0x0C)
++#define OFF_LSR         (0x14)
++#define LSR_TDRQ        (1 << 5)
++#define LSR_TEMT        (1 << 6)
++
++
++#ifdef PRINT_DEBUG
++#define TCSM_PCHAR(x)                                                   \
++	*((volatile unsigned int*)(U_IOBASE+OFF_TDR)) = x;              \
++while ((*((volatile unsigned int*)(U_IOBASE + OFF_LSR)) & (LSR_TDRQ | LSR_TEMT)) != (LSR_TDRQ | LSR_TEMT))
++#else
++#define TCSM_PCHAR(x)
++#endif
++
++#define TCSM_DELAY(x)						\
++	do{							\
++	register unsigned int i = x;				\
++	while(i--)						\
++		__asm__ volatile("nop\n\t");			\
++	}while(0)
++
++static inline void serial_put_hex(unsigned int x) {
++	int i;
++	unsigned int d;
++	for(i = 7;i >= 0;i--) {
++		d = (x  >> (i * 4)) & 0xf;
++		if(d < 10) d += '0';
++		else d += 'A' - 10;
++		TCSM_PCHAR(d);
++	}
++	TCSM_PCHAR('\r');
++	TCSM_PCHAR('\n');
++}
++
++
++
++
+diff --git a/arch/mips/xburst2/soc-x2000/pm_fastboot.c b/arch/mips/xburst2/soc-x2000/pm_fastboot.c
+new file mode 100644
+index 000000000..53d44a4be
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/pm_fastboot.c
+@@ -0,0 +1,667 @@
++#include <linux/init.h>
++#include <linux/pm.h>
++#include <linux/suspend.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++
++#include <soc/cache.h>
++#include <soc/base.h>
++#include <asm/io.h>
++#include <soc/ddr.h>
++#include <soc/base.h>
++#include <soc/cpm.h>
++#include <ccu.h>
++
++#include "pm_fastboot.h"
++
++
++volatile unsigned int intc0_msk;
++volatile unsigned int intc1_msk;
++volatile unsigned int gpio_pb_int;
++volatile unsigned int gpio_pb_msk;
++volatile unsigned int gpio_pb_pat1;
++volatile unsigned int gpio_pb_pat0;
++volatile unsigned int gpio_pe_int;
++volatile unsigned int gpio_pe_msk;
++volatile unsigned int gpio_pe_pat1;
++volatile unsigned int gpio_pe_pat0;
++
++volatile unsigned int clk_gate0;
++volatile unsigned int clk_gate1;
++
++volatile unsigned int mem_pd0;
++volatile unsigned int mem_pd1;
++
++#define  g_state  ((volatile suspend_state_t *)0xb0000bfc)
++volatile unsigned int _regs_stack_0[136 / 4];
++volatile unsigned int _regs_stack_1[136 / 4];
++volatile unsigned int *_regs_stack;
++
++static inline void rtc_write_reg(unsigned int reg, unsigned int val)
++{
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++	*(volatile unsigned int *)0xb000303c = 0xa55a;
++	while (!((*(volatile unsigned int *)0xb000303c >> 31) & 0x1) );
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++
++	*(volatile unsigned int *)reg = val;
++
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++}
++
++static inline unsigned int  rtc_read_reg(unsigned int reg)
++{
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++
++	return *(volatile unsigned int *)reg;
++}
++
++#define PRINT_DEBUG
++
++
++#ifdef PRINT_DEBUG
++
++#define OFF_TDR         (0x00)
++#define OFF_LCR         (0x0C)
++#define OFF_LSR         (0x14)
++#define LSR_TDRQ        (1 << 5)
++#define LSR_TEMT        (1 << 6)
++
++#define U_IOBASE (UART2_IOBASE + 0xa0000000)
++#define TCSM_PCHAR(x)                                                   \
++	*((volatile unsigned int*)(U_IOBASE+OFF_TDR)) = x;              \
++while ((*((volatile unsigned int*)(U_IOBASE + OFF_LSR)) & (LSR_TDRQ | LSR_TEMT)) != (LSR_TDRQ | LSR_TEMT))
++#else
++#define TCSM_PCHAR(x)
++#endif
++
++#define TCSM_DELAY(x)                                           \
++	do{                                                     \
++		register unsigned int i = x;                    \
++		while(i--)                                      \
++		__asm__ volatile(".set mips32\n\t"      \
++				"nop\n\t"              \
++				".set mips32");        \
++	}while(0)                                               \
++
++static inline void serial_put_hex(unsigned int x) {
++	int i;
++	unsigned int d;
++	for(i = 7;i >= 0;i--) {
++		d = (x  >> (i * 4)) & 0xf;
++		if(d < 10) d += '0';
++		else d += 'A' - 10;
++		TCSM_PCHAR(d);
++	}
++	TCSM_PCHAR('\r');
++	TCSM_PCHAR('\n');
++}
++
++#if 1
++struct uart_regs {
++	unsigned int udllr;
++	unsigned int udlhr;
++	unsigned int uthr;
++	unsigned int uier;
++	unsigned int ufcr;
++	unsigned int ulcr;
++	unsigned int umcr;
++	unsigned int uspr;
++	unsigned int isr;
++	unsigned int umr;
++	unsigned int uacr;
++	unsigned int urcr;
++	unsigned int utcr;
++
++};
++
++
++static void uart_save(struct uart_regs *uart_regs)
++{
++	printk("uart save\n");
++	*(volatile unsigned int *)0xb003200c |= (1 << 7);
++	uart_regs->udllr = *(volatile unsigned int *)0xb0032000;
++	uart_regs->udlhr = *(volatile unsigned int *)0xb0032004;
++
++	*(volatile unsigned int *)0xb003200c &= ~(1 << 7);
++	uart_regs->uthr = *(volatile unsigned int  *)0xb0032000;
++	uart_regs->uier = *(volatile unsigned int  *)0xb0032004;
++
++	uart_regs->ufcr = *(volatile unsigned int  *)0xb0032008;
++	uart_regs->ulcr = *(volatile unsigned int  *)0xb003200c;
++	uart_regs->umcr = *(volatile unsigned int  *)0xb0032010;
++	uart_regs->uspr = *(volatile unsigned int  *)0xb003201c;
++	uart_regs->isr = *(volatile unsigned int  *)0xb0032020;
++	uart_regs->umr = *(volatile unsigned int  *)0xb0032024;
++	uart_regs->uacr = *(volatile unsigned int *)0xb0032028;
++	uart_regs->urcr = *(volatile unsigned int *)0xb0032040;
++	uart_regs->utcr = *(volatile unsigned int *)0xb0032044;
++
++	printk("uthr   = 0x%08x\n", uart_regs->uthr);
++	printk("uier   = 0x%08x\n", uart_regs->uier);
++	printk("udllr   = 0x%08x\n", uart_regs->udllr);
++	printk("udlhr   = 0x%08x\n", uart_regs->udlhr);
++	printk("ULCR = 0x%08x\n", *(volatile unsigned int *)0xb003200c);
++	printk("UMCR = 0x%08x\n", *(volatile unsigned int *)0xb0032010);
++	printk("ULSR = 0x%08x\n", *(volatile unsigned int *)0xb0032014);
++	printk("UMSR = 0x%08x\n", *(volatile unsigned int *)0xb0032018);
++	printk("USPR = 0x%08x\n", *(volatile unsigned int *)0xb003201c);
++	printk("ISR  = 0x%08x\n", *(volatile unsigned int *)0xb0032020);
++	printk("UMR  = 0x%08x\n", *(volatile unsigned int *)0xb0032024);
++	printk("UACR = 0x%08x\n", *(volatile unsigned int *)0xb0032028);
++	printk("URCR = 0x%08x\n", *(volatile unsigned int *)0xb0032040);
++	printk("UTCR = 0x%08x\n", *(volatile unsigned int *)0xb0032044);
++
++
++}
++
++static void uart_set_baud(struct uart_regs *uart_regs)
++{
++	*(volatile unsigned int *)0xb0032024 = uart_regs->umr;
++	*(volatile unsigned int *)0xb0032028 = uart_regs->uacr;
++
++	*(volatile unsigned int *)0xb003200c |= (1 << 7);
++	*(volatile unsigned int *)0xb0032000 = uart_regs->udllr;
++	*(volatile unsigned int *)0xb0032004 = uart_regs->udlhr;
++	*(volatile unsigned int *)0xb003200c &= ~(1 << 7);
++
++}
++
++
++static void uart_restore(struct uart_regs *uart_regs)
++{
++
++	*(volatile unsigned int *)0xb0000020 &= ~(1 << 16);
++
++	/*uart2 PD30 PD31 func0 */
++	*(volatile unsigned int *)0xb0010318 |= (3 << 30);
++	*(volatile unsigned int *)0xb0010328 |= (3 << 30);
++	*(volatile unsigned int *)0xb0010338 |= (3 << 30);
++	*(volatile unsigned int *)0xb0010348 |= (3 << 30);
++
++
++	*(volatile unsigned int *)0xb0032008 = uart_regs->ufcr;
++	*(volatile unsigned int *)0xb003200c = uart_regs->ulcr;
++	*(volatile unsigned int *)0xb0032010 = uart_regs->umcr;
++	*(volatile unsigned int *)0xb003201c = uart_regs->uspr;
++	*(volatile unsigned int *)0xb0032020 = uart_regs->isr;
++	*(volatile unsigned int *)0xb0032024 = uart_regs->umr;
++	*(volatile unsigned int *)0xb0032028 = uart_regs->uacr;
++	*(volatile unsigned int *)0xb0032040 = uart_regs->urcr;
++	*(volatile unsigned int *)0xb0032044 = uart_regs->utcr;
++
++	uart_set_baud(uart_regs);
++
++	*(volatile unsigned int *)0xb0032008 = (1 << 4) | (1 << 0) | (1 << 1) | (1 << 2);
++
++}
++#endif
++
++struct ost_regs {
++	unsigned int ostccr;
++	unsigned int oster;
++	unsigned int ostcr;
++	unsigned int ostfr;
++	unsigned int ostmr;
++	unsigned int ostdfr;
++	unsigned int ostcnt;
++
++	unsigned int g_ostccr;
++	unsigned int g_oster;
++	unsigned int g_ostcr;
++	unsigned int g_ostcnth;
++	unsigned int g_ostcntl;
++	unsigned int g_ostcntb;
++};
++
++static void ost_save(struct ost_regs *ost_regs)
++{
++	ost_regs->ostccr = *(volatile unsigned int *)0xb2100000;
++	ost_regs->oster = *(volatile unsigned int *)0xb2100004;
++	ost_regs->ostcr = *(volatile unsigned int *)0xb2100008;
++	ost_regs->ostfr = *(volatile unsigned int *)0xb210000c;
++	ost_regs->ostmr = *(volatile unsigned int *)0xb2100010;
++	ost_regs->ostdfr = *(volatile unsigned int *)0xb2100014;
++	ost_regs->ostcnt = *(volatile unsigned int *)0xb2100018;
++
++	ost_regs->g_ostccr = *(volatile unsigned int *)0xb2000000;
++	ost_regs->g_oster = *(volatile unsigned int *)0xb2000004;
++	ost_regs->g_ostcr = *(volatile unsigned int *)0xb2000008;
++	ost_regs->g_ostcnth = *(volatile unsigned int *)0xb200000c;
++	ost_regs->g_ostcntl = *(volatile unsigned int *)0xb2000010;
++	ost_regs->g_ostcntb = *(volatile unsigned int *)0xb2000014;
++
++}
++
++static void ost_restore(struct ost_regs *ost_regs)
++{
++	*(volatile unsigned int *)0xb2100000 = ost_regs->ostccr;
++	*(volatile unsigned int *)0xb2100008 = ost_regs->ostcr;
++	*(volatile unsigned int *)0xb210000c = ost_regs->ostfr;
++	*(volatile unsigned int *)0xb2100010 = ost_regs->ostmr;
++	*(volatile unsigned int *)0xb2100014 = ost_regs->ostdfr;
++	*(volatile unsigned int *)0xb2100018 = ost_regs->ostcnt;
++	*(volatile unsigned int *)0xb2100004 = ost_regs->oster;
++
++	*(volatile unsigned int *)0xb2000000 = ost_regs->g_ostccr;
++	*(volatile unsigned int *)0xb2000008 = ost_regs->g_ostcr;
++	*(volatile unsigned int *)0xb2000004 = ost_regs->g_oster;
++
++}
++
++static noinline void cpu_resume(void);
++
++
++static void rtc_ram_write_enable(void)
++{
++	unsigned int tmp;
++
++	/* write RTC RAM enable */
++	tmp = rtc_read_reg(0xb0003048);
++	tmp &= ~(1 << 23);
++	tmp &= ~(1 << 22);
++	tmp |= (1 << 21);
++	tmp |= (1 << 20);
++	rtc_write_reg(0xb0003048, tmp);
++
++}
++
++static void rtc_ram_write_disable(void)
++{
++	unsigned int tmp;
++
++	/*exit write RTC RAM enable */
++	tmp = rtc_read_reg(0xb0003048);
++	tmp |= (1 << 22);
++	rtc_write_reg(0xb0003048, tmp);
++
++}
++
++
++static void soc_pm_fastboot(void)
++{
++
++	unsigned int tmp;
++
++	clk_gate0 = cpm_inl(CPM_CLKGR);
++	clk_gate1 = cpm_inl(CPM_CLKGR1);
++
++	clk_gate0 |= 1 << 20; // disable ost
++	clk_gate0 &= ~(1 << 28); // enable apb0
++	clk_gate0 &= ~(1 << 27); //enable rtc
++
++	cpm_outl(clk_gate0, CPM_CLKGR);
++
++	printk("clk_gate0: 0x%08x, clk_gate1: 0x%08x\n", clk_gate0, clk_gate1);
++
++
++
++	intc1_msk = *(volatile unsigned int *)0xb0001024;
++	*(volatile unsigned int *)0xb0001024 = intc1_msk & ~(1<<0); // RTC INT MSK
++
++	/* RTC EALM */
++	tmp = rtc_read_reg(0xb000302c);
++	tmp |= 1;
++	rtc_write_reg(0xb000302c, tmp);
++
++	/* RTC enable AE */
++	tmp = rtc_read_reg(0xb0003000);
++	tmp |= (1 << 2) | (1 << 0);
++	rtc_write_reg(0xb0003000, tmp);
++
++	/* 32k rtc clk */
++	tmp = rtc_read_reg(0xb0003000);
++	tmp &= ~(1 << 1);
++	rtc_write_reg(0xb0003000, tmp);
++}
++
++static int soc_post_wakeup(void)
++{
++
++	clk_gate0 &= ~(1 << 20);	//enable ost
++	cpm_outl(clk_gate0, CPM_CLKGR);
++	cpm_outl(clk_gate1, CPM_CLKGR1);
++
++
++	return 0;
++}
++
++
++
++
++
++static struct store_regs *store_regs;
++
++static void save_resume_pc(void)
++{
++
++	store_regs = (struct store_regs *)RTC_RAM_DATA_ADDR;
++	store_regs->resume_pc = (unsigned int)cpu_resume;
++	printk("xxxxxxxxxxxxxxxxxxx save resume_pc = 0x%08x\n", store_regs->resume_pc);
++}
++static void pll_store(void)
++{
++	struct pll_resume_reg *pll_resume_reg;
++
++	store_regs = (struct store_regs *)RTC_RAM_DATA_ADDR;
++	pll_resume_reg = &store_regs->pll_resume_reg;
++
++	pll_resume_reg->cpccr = *(volatile unsigned int *)0xb0000000;
++	pll_resume_reg->cppcr = *(volatile unsigned int *)0xb000000c;
++	pll_resume_reg->cpapcr = *(volatile unsigned int *)0xb0000010;
++	pll_resume_reg->cpmpcr = *(volatile unsigned int *)0xb0000014;
++	pll_resume_reg->cpepcr = *(volatile unsigned int *)0xb0000018;
++	pll_resume_reg->ddrcdr = *(volatile unsigned int *)0xb000002c;
++
++}
++
++static void ddrc_store(void)
++{
++	struct ddrc_resume_reg *ddrc_resume_reg;
++
++	store_regs = (struct store_regs *)RTC_RAM_DATA_ADDR;
++	ddrc_resume_reg = &store_regs->ddrc_resume_reg;
++
++	ddrc_resume_reg->dcfg = *(volatile unsigned int *)0xb34f0008;
++	ddrc_resume_reg->dctrl = *(volatile unsigned int *)0xb34f0010;
++	ddrc_resume_reg->dlmr = *(volatile unsigned int *)0xb34f0018;
++	ddrc_resume_reg->ddlp = *(volatile unsigned int *)0xb34f0020;
++	ddrc_resume_reg->dasr_en = *(volatile unsigned int *)0xb34f0030;
++	ddrc_resume_reg->dasr_cnt = *(volatile unsigned int *)0xb34f0028;
++	ddrc_resume_reg->drefcnt = *(volatile unsigned int *)0xb34f0038;
++	ddrc_resume_reg->dtimming1 = *(volatile unsigned int *)0xb34f0040;
++	ddrc_resume_reg->dtimming2 = *(volatile unsigned int *)0xb34f0048;
++	ddrc_resume_reg->dtimming3 = *(volatile unsigned int *)0xb34f0050;
++	ddrc_resume_reg->dtimming4 = *(volatile unsigned int *)0xb34f0058;
++	ddrc_resume_reg->dtimming5 = *(volatile unsigned int *)0xb34f0060;
++	ddrc_resume_reg->dmmap0 = *(volatile unsigned int *)0xb34f0078;
++	ddrc_resume_reg->dmmap1 = *(volatile unsigned int *)0xb34f0080;
++	ddrc_resume_reg->dwcfg = *(volatile unsigned int *)0xb3012000;
++	ddrc_resume_reg->dremap1 = *(volatile unsigned int *)0xb3012008;
++	ddrc_resume_reg->dremap2 = *(volatile unsigned int *)0xb301200c;
++	ddrc_resume_reg->dremap3 = *(volatile unsigned int *)0xb3012010;
++	ddrc_resume_reg->dremap4 = *(volatile unsigned int *)0xb3012014;
++	ddrc_resume_reg->dremap5 = *(volatile unsigned int *)0xb3012018;
++	ddrc_resume_reg->ccguc0 = *(volatile unsigned int *)0xb3012064;
++	ddrc_resume_reg->ccguc1 = *(volatile unsigned int *)0xb3012068;
++
++}
++
++static void ddr_phy_store(void)
++{
++	struct ddr_phy_resume_reg *ddr_phy_resume_reg;
++
++	store_regs = (struct store_regs *)RTC_RAM_DATA_ADDR;
++	ddr_phy_resume_reg = &store_regs->ddr_phy_resume_reg;
++
++	ddr_phy_resume_reg->mem_cfg = *(volatile unsigned int *)0xb3011004;
++	ddr_phy_resume_reg->dq_width = *(volatile unsigned int *)0xb301107c;
++	ddr_phy_resume_reg->cl = *(volatile unsigned int *)0xb3011014;
++	ddr_phy_resume_reg->al = *(volatile unsigned int *)0xb3011018;
++	ddr_phy_resume_reg->cwl = *(volatile unsigned int *)0xb301101c;
++	ddr_phy_resume_reg->pll_fbdiv = *(volatile unsigned int *)0xb3011080;
++	ddr_phy_resume_reg->pll_ctrl = *(volatile unsigned int *)0xb3011084;
++	ddr_phy_resume_reg->pll_pdiv = *(volatile unsigned int *)0xb3011088;
++	ddr_phy_resume_reg->training_ctrl = *(volatile unsigned int *)0xb3011008;
++	ddr_phy_resume_reg->calib_bypass_al = *(volatile unsigned int *)0xb3011118;
++	ddr_phy_resume_reg->calib_bypass_ah = *(volatile unsigned int *)0xb3011158;
++	ddr_phy_resume_reg->wl_mode1 = *(volatile unsigned int *)0xb301100c;
++	ddr_phy_resume_reg->wl_mode2 = *(volatile unsigned int *)0xb3011010;
++}
++
++static void rtc_ram_store(void)
++{
++	pll_store();
++	ddrc_store();
++	ddr_phy_store();
++	save_resume_pc();
++}
++
++
++static int fastboot_resume_code[] = {
++
++#include "fastboot_resume_code.hex"
++
++};
++
++
++
++
++
++
++extern long long save_goto(unsigned int);
++extern int restore_goto(void);
++
++
++
++static noinline void cpu_resume(void)
++{
++
++	unsigned int cpu_id;
++
++
++	cpu_id = read_c0_ebase() & 0x3ff;
++
++	if (cpu_id == 0) {
++		_regs_stack = _regs_stack_0;
++	} else if (cpu_id == 1) {
++		_regs_stack = _regs_stack_1;
++	}
++
++	*(volatile unsigned int *)0xb2200f00 = 0xbfc00000; /* RESET entry = 0xbfc00000 ,reset value */
++
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"jr.hb %0	\n\t"
++		"nop		\n\t"
++		".set pop 	\n\t"
++		:
++		: "r" (restore_goto)
++		:
++		);
++}
++
++
++
++
++#define jump() do{                                  \
++	                void (*func)(void);                                             \
++	                func = (void(*)(void)) 0xb0004000;              \
++	                func();                                                                 \
++	        }while(0)
++
++#if 0
++static void ddrp_auto_calibration(void)
++{
++	unsigned int reg_val = ddr_readl(DDRP_INNOPHY_TRAINING_CTRL);
++	unsigned int timeout = 0xffffff;
++	unsigned int wait_cal_done = DDRP_CALIB_DONE_HDQCFA | DDRP_CALIB_DONE_LDQCFA;
++
++	reg_val &= ~(DDRP_TRAINING_CTRL_DSCSE_BP);
++	reg_val |= DDRP_TRAINING_CTRL_DSACE_START;
++	ddr_writel(reg_val, DDRP_INNOPHY_TRAINING_CTRL);
++
++	while(!((ddr_readl(DDRP_INNOPHY_CALIB_DONE) & wait_cal_done) == wait_cal_done) && --timeout) {
++		TCSM_PCHAR('t');
++		serial_put_hex(*(volatile unsigned int *)(0x80015060 + 0 * 4));
++		serial_put_hex(*(volatile unsigned int *)(0x80015060 + 1 * 4));
++		serial_put_hex(*(volatile unsigned int *)(0x80015060 + 2 * 4));
++		serial_put_hex(*(volatile unsigned int *)(0x80015060 + 3 * 4));
++	}
++
++	if(!timeout) {
++		TCSM_PCHAR('f');
++	}
++	ddr_writel(0, DDRP_INNOPHY_TRAINING_CTRL);
++}
++#endif
++
++
++static noinline void cpu_sleep(void)
++{
++
++
++	unsigned int tmp;
++	unsigned int ddrc_ctrl;
++
++	blast_dcache32();
++	blast_scache64();
++	__sync();
++	__fast_iob();
++
++	ddr_writel(0, DDRC_AUTOSR_EN);
++	tmp = *(volatile unsigned int *)0xa0000000;
++
++
++	/* DDR self refresh, */
++	ddrc_ctrl = ddr_readl(DDRC_CTRL);
++	ddrc_ctrl |= 1 << 5;
++	ddr_writel(ddrc_ctrl, DDRC_CTRL);
++	while(!(ddr_readl(DDRC_STATUS) & (1<<2)));
++
++	/* bufferen_core = 0 */
++	tmp = rtc_read_reg(0xb0003048);
++	tmp &= ~(1 << 21);
++	rtc_write_reg(0xb0003048, tmp);
++
++	/* dfi_init_start = 1 */
++	*(volatile unsigned int *)0xb3012000 |= (1 << 3);
++
++
++	{
++		int i;
++		for (i = 0; i < 4; i++) {
++
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++		}
++	}
++	/* ddr phy pll power down */
++	*(volatile unsigned int *)0xb3011084 |= (1 << 1);
++
++
++
++	TCSM_PCHAR('o');
++
++
++	/* rtc disable power detect */
++	rtc_write_reg(0xb000302c, (0x1a55a5a5 << 3) | 1);
++	/* RTC PD */
++	rtc_write_reg(0xb0003020, 1);
++
++
++	while (1);
++}
++
++
++
++static void load_func_to_tcsm(unsigned int *tcsm_addr,unsigned int *f_addr,unsigned int size)
++{
++	unsigned int instr;
++	int offset;
++	int i;
++#ifdef DEBUG_PM
++	printk("tcsm addr = %p %p size = %d\n",tcsm_addr,f_addr,size);
++#endif
++	for(i = 0;i < size / 4;i++) {
++		instr = f_addr[i];
++		if((instr >> 26) == 2){
++			offset = instr & 0x3ffffff;
++			offset = (offset << 2) - ((unsigned int)f_addr & 0xfffffff);
++			if(offset > 0) {
++				offset = ((unsigned int)tcsm_addr & 0xfffffff) + offset;
++				instr = (2 << 26) | (offset >> 2);
++			}
++		}
++		tcsm_addr[i] = instr;
++	}
++}
++
++
++static int x2000_pm_enter(suspend_state_t state)
++{
++	unsigned int cpu_id;
++	struct uart_regs *uart_regs;
++	struct ost_regs *ost_regs;
++
++	uart_regs = kmalloc(sizeof(struct uart_regs), GFP_KERNEL);
++	ost_regs = kmalloc(sizeof(struct ost_regs), GFP_KERNEL);
++	soc_pm_fastboot();
++
++	load_func_to_tcsm((unsigned int *)SLEEP_CPU_SLEEP_TEXT, (unsigned int *)cpu_sleep, SLEEP_CPU_SLEEP_LEN);
++
++	rtc_ram_write_enable();
++	rtc_ram_store();
++	memcpy((unsigned int *)RTC_RAM_CODE_ADDR1, (unsigned int *)fastboot_resume_code, RTC_RAM_CODE_SIZE);
++	rtc_ram_write_disable();
++
++	uart_save(uart_regs);
++	ost_save(ost_regs);
++
++	cpu_id = read_c0_ebase() & 0x3ff;
++
++	printk("cpu_id = %d\n", cpu_id);
++
++	if (cpu_id == 0) {
++		_regs_stack = _regs_stack_0;
++	} else if (cpu_id == 1) {
++		_regs_stack = _regs_stack_1;
++	}
++
++
++	mb();
++	save_goto((unsigned int)SLEEP_CPU_SLEEP_TEXT);
++	mb();
++
++
++	soc_post_wakeup();
++
++	ost_restore(ost_regs);
++	uart_restore(uart_regs);
++	set_ccu_mimr(1 << 0);
++
++
++	return 0;
++}
++
++static int x2000_pm_begin(suspend_state_t state)
++{
++	printk("x2000 suspend begin\n");
++
++	return 0;
++}
++
++static void x2000_pm_end(void)
++{
++	printk("x2000 pm end!\n");
++
++}
++
++static const struct platform_suspend_ops x2000_pm_ops = {
++	.valid		= suspend_valid_only_mem,
++	.begin		= x2000_pm_begin,
++	.enter		= x2000_pm_enter,
++	.end		= x2000_pm_end,
++};
++
++/*
++ * Initialize suspend interface
++ */
++static int __init pm_init(void)
++{
++
++	suspend_set_ops(&x2000_pm_ops);
++
++	return 0;
++}
++
++arch_initcall(pm_init);
+diff --git a/arch/mips/xburst2/soc-x2000/pm_fastboot.h b/arch/mips/xburst2/soc-x2000/pm_fastboot.h
+new file mode 100644
+index 000000000..3bad4d885
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/pm_fastboot.h
+@@ -0,0 +1,106 @@
++
++
++#define RTC_SLEEP_MEMORY_START          0xb0004000
++#define RTC_SLEEP_MEMORY_END            0xb0005000
++#define RTC_RAM_SP_ADDR                 (RTC_RAM_DATA_ADDR - 4)
++//#define RTC_RAM_SP_SIZE                 (256 - 4)
++#define RTC_RAM_DATA_ADDR               0xb0004c00
++#define RTC_RAM_DATA_SIZE               1024
++#define RTC_RAM_CODE_ADDR1              0xb0004000
++#define RTC_RAM_CODE_ADDR2              (RTC_RAM_CODE_ADDR1 + 64)
++#define RTC_RAM_CODE_SIZE               0xb00
++
++#define SLEEP_CPU_SLEEP_TEXT		0xb2400000
++#define SLEEP_CPU_SLEEP_LEN		4096
++
++
++
++struct pll_resume_reg {
++	unsigned int cpccr;
++	unsigned int cppcr;
++	unsigned int cpapcr;
++	unsigned int cpmpcr;
++	unsigned int cpepcr;
++	unsigned int ddrcdr;
++};
++
++struct ddrc_resume_reg {
++	unsigned int dcfg;
++	unsigned int dctrl;
++	unsigned int dlmr;
++	unsigned int ddlp;
++	unsigned int dasr_en;
++	unsigned int dasr_cnt;
++	unsigned int drefcnt;
++	unsigned int dtimming1;
++	unsigned int dtimming2;
++	unsigned int dtimming3;
++	unsigned int dtimming4;
++	unsigned int dtimming5;
++	unsigned int dmmap0;
++	unsigned int dmmap1;
++#if 0
++	unsigned int dbwcfg;
++	unsigned int dbwstp;
++	unsigned int hregpro;
++	unsigned int dbgen;
++#endif
++	unsigned int dwcfg;
++	unsigned int dremap1;
++	unsigned int dremap2;
++	unsigned int dremap3;
++	unsigned int dremap4;
++	unsigned int dremap5;
++#if 0
++	unsigned int cpac;
++	unsigned int cchc0;
++	unsigned int cchc1;
++	unsigned int cchc2;
++	unsigned int cchc3;
++	unsigned int cchc4;
++	unsigned int cchc5;
++	unsigned int cchc6;
++	unsigned int cchc7;
++	unsigned int cschc0;
++	unsigned int cschc1;
++	unsigned int cschc2;
++	unsigned int cschc3;
++	unsigned int cmonc0;
++	unsigned int cmonc1;
++	unsigned int cmonc2;
++	unsigned int cmonc3;
++	unsigned int cmonc4;
++#endif
++	unsigned int ccguc0;
++	unsigned int ccguc1;
++#if 0
++	unsigned int pregpro;
++	unsigned int bufcfg;
++#endif
++};
++
++struct ddr_phy_resume_reg {
++	unsigned int phy_rst;
++	unsigned int mem_cfg;
++	unsigned int dq_width;
++	unsigned int cl;
++	unsigned int al;
++	unsigned int cwl;
++	unsigned int pll_fbdiv;
++	unsigned int pll_ctrl;
++	unsigned int pll_pdiv;
++	unsigned int training_ctrl;
++	unsigned int calib_bypass_al;
++	unsigned int calib_bypass_ah;
++	unsigned int wl_mode1;
++	unsigned int wl_mode2;
++
++};
++
++struct store_regs {
++	unsigned int resume_pc;
++	struct pll_resume_reg pll_resume_reg;
++	struct ddrc_resume_reg ddrc_resume_reg;
++	struct ddr_phy_resume_reg ddr_phy_resume_reg;
++};
++
+diff --git a/arch/mips/xburst2/soc-x2000/regs_save_restore.S b/arch/mips/xburst2/soc-x2000/regs_save_restore.S
+new file mode 100644
+index 000000000..abe8b49df
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/regs_save_restore.S
+@@ -0,0 +1,190 @@
++#include <asm/asm.h>
++#include <asm/regdef.h>
++
++#define CP0_PAGEMASK	$5,0
++#define CP0_STATUS	$12,0
++#define CP0_INTCTL	$12,1
++#define CP0_CAUSE	$13,0
++#define CP0_EBASE	$15,1
++#define CP0_CONFIG	$16,0
++#define CP0_CONFIG1	$16,1
++#define CP0_CONFIG2	$16,2
++#define CP0_CONFIG3	$16,3
++#define CP0_CONFIG4	$16,4
++#define CP0_CONFIG5	$16,5
++#define CP0_CONFIG7	$16,7
++#define CP0_LLADDR	$17,0
++#define CP0_WATCHLo	$18,0
++#define CP0_WATCHHI	$19,0
++#define CP0_ERRCTL	$26,0
++#define CP0_CONTEXT	$4,0
++#define CP0_KSCRATCH1	$31,2
++#define CP0_KSCRATCH2	$31,3
++#define CP0_KSCRATCH3	$31,4
++#define CP0_KSCRATCH4	$31,5
++#define CP0_KSCRATCH5	$31,6
++#define CP0_KSCRATCH6	$31,7
++
++	.data
++	.global _regs_stack
++_regs_stack:
++	.align 5
++	.space 140,0
++
++	.text
++	.global save_goto
++	.align 2
++	.ent save_goto,0
++	LEAF(save_goto)
++save_goto:
++	.set	push
++	.set	noreorder
++	.set	noat
++
++	la	k0, _regs_stack
++	sw	s0,0(k0)
++	sw	s1,4(k0)
++	sw	s2,8(k0)
++	sw	s3,12(k0)
++	sw	s4,16(k0)
++	sw	s5,20(k0)
++	sw	s6,24(k0)
++	sw	s7,28(k0)
++	sw	gp,32(k0)
++	sw	sp,36(k0)
++	sw	fp,40(k0)
++	sw	ra,44(k0)
++
++	mfc0	k1,CP0_PAGEMASK
++	sw	k1,48(k0)
++	mfc0	k1,CP0_STATUS
++	sw	k1,52(k0)
++	mfc0	k1,CP0_INTCTL
++	sw	k1,56(k0)
++	mfc0	k1,CP0_CAUSE
++	sw	k1,60(k0)
++	mfc0	k1,CP0_EBASE
++	sw	k1,64(k0)
++	mfc0	k1,CP0_CONFIG
++	sw	k1,68(k0)
++	mfc0	k1,CP0_CONFIG1
++	sw	k1,72(k0)
++	mfc0	k1,CP0_CONFIG2
++	sw	k1,76(k0)
++	mfc0	k1,CP0_CONFIG3
++	sw	k1,80(k0)
++	mfc0	k1,CP0_CONFIG4
++	sw	k1,84(k0)
++	mfc0	k1,CP0_CONFIG5
++	sw	k1,88(k0)
++	mfc0	k1,CP0_CONFIG7
++	sw	k1,92(k0)
++	mfc0	k1,CP0_LLADDR
++	sw	k1,96(k0)
++	mfc0	k1,CP0_WATCHLo
++	sw	k1,100(k0)
++	mfc0	k1,CP0_WATCHHI
++	sw	k1,104(k0)
++	mfc0	k1,CP0_ERRCTL
++	sw	k1,108(k0)
++	mfc0	k1,CP0_CONTEXT
++	sw	k1,112(k0)
++	mfc0	k1,CP0_KSCRATCH1
++	sw	k1,116(k0)
++	mfc0	k1,CP0_KSCRATCH2
++	sw	k1,120(k0)
++	mfc0	k1,CP0_KSCRATCH3
++	sw	k1,124(k0)
++	mfc0	k1,CP0_KSCRATCH4
++	sw	k1,128(k0)
++	mfc0	k1,CP0_KSCRATCH5
++	sw	k1,132(k0)
++	mfc0	k1,CP0_KSCRATCH6
++	sw	k1,136(k0)
++
++	jr.hb	a0
++	nop
++
++	.set	at
++	.set	reorder
++	.set	pop
++	END(save_goto)
++
++	.text
++	.global restore_goto
++	.align 2
++	.ent restore_goto,0
++	LEAF(restore_goto)
++restore_goto:
++	.set	push
++	.set	noreorder
++	.set	noat
++
++	la	k0, _regs_stack
++	lw	s0,0(k0)
++	lw	s1,4(k0)
++	lw	s2,8(k0)
++	lw	s3,12(k0)
++	lw	s4,16(k0)
++	lw	s5,20(k0)
++	lw	s6,24(k0)
++	lw	s7,28(k0)
++	lw	gp,32(k0)
++	lw	sp,36(k0)
++	lw	fp,40(k0)
++	lw	ra,44(k0)
++
++	lw	k1,48(k0)
++	mtc0	k1,CP0_PAGEMASK
++	lw	k1,52(k0)
++	mtc0	k1,CP0_STATUS
++	lw	k1,56(k0)
++	mtc0	k1,CP0_INTCTL
++	lw	k1,60(k0)
++	mtc0	k1,CP0_CAUSE
++	lw	k1,64(k0)
++	mtc0	k1,CP0_EBASE
++	lw	k1,68(k0)
++	mtc0	k1,CP0_CONFIG
++	lw	k1,72(k0)
++	mtc0	k1,CP0_CONFIG1
++	lw	k1,76(k0)
++	mtc0	k1,CP0_CONFIG2
++	lw	k1,80(k0)
++	mtc0	k1,CP0_CONFIG3
++	lw	k1,84(k0)
++	mtc0	k1,CP0_CONFIG4
++	lw	k1,88(k0)
++	mtc0	k1,CP0_CONFIG5
++	lw	k1,92(k0)
++	mtc0	k1,CP0_CONFIG7
++	lw	k1,96(k0)
++	mtc0	k1,CP0_LLADDR
++	lw	k1,100(k0)
++	mtc0	k1,CP0_WATCHLo
++	lw	k1,104(k0)
++	mtc0	k1,CP0_WATCHHI
++	lw	k1,108(k0)
++	mtc0	k1,CP0_ERRCTL
++	lw	k1,112(k0)
++	mtc0	k1,CP0_CONTEXT
++	lw	k1,116(k0)
++	mtc0	k1,CP0_KSCRATCH1
++	lw	k1,120(k0)
++	mtc0	k1,CP0_KSCRATCH2
++	lw	k1,124(k0)
++	mtc0	k1,CP0_KSCRATCH3
++	lw	k1,128(k0)
++	mtc0	k1,CP0_KSCRATCH4
++	lw	k1,132(k0)
++	mtc0	k1,CP0_KSCRATCH5
++	lw	k1,136(k0)
++	mtc0	k1,CP0_KSCRATCH6
++
++	jr.hb	ra
++	nop
++
++	.set	at
++	.set	reorder
++	.set	pop
++	END(restore_goto)
+diff --git a/arch/mips/xburst2/soc-x2000/regs_save_restore.py b/arch/mips/xburst2/soc-x2000/regs_save_restore.py
+new file mode 100755
+index 000000000..8a23de0d0
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/regs_save_restore.py
+@@ -0,0 +1,124 @@
++#!/usr/bin/env python
++import os
++import string
++
++common_regs=["s0","s1","s2","s3",
++        "s4","s5","s6","s7",
++        "gp","sp","fp","ra"]
++cp0_regs=[
++        ["CP0_PAGEMASK","$5","0"],
++        ["CP0_STATUS","$12","0"],
++        ["CP0_INTCTL","$12","1"],
++        ["CP0_CAUSE","$13","0"],
++        ["CP0_EBASE","$15","1"],
++        ["CP0_CONFIG","$16","0"],
++        ["CP0_CONFIG1","$16","1"],
++        ["CP0_CONFIG2","$16","2"],
++        ["CP0_CONFIG3","$16","3"],
++	["CP0_CONFIG4", "$16", "4"],
++	["CP0_CONFIG5", "$16", "5"],
++	["CP0_CONFIG7", "$16", "7"],
++        ["CP0_LLADDR","$17","0"],
++        ["CP0_WATCHLo","$18","0"],
++        ["CP0_WATCHHI","$19","0"],
++        ["CP0_ERRCTL","$26","0"],
++        ["CP0_CONTEXT","$4","0"],
++        ["CP0_KSCRATCH1","$31","2"],
++        ["CP0_KSCRATCH2","$31","3"],
++        ["CP0_KSCRATCH3","$31","4"],
++        ["CP0_KSCRATCH4","$31","5"],
++        ["CP0_KSCRATCH5","$31","6"],
++        ["CP0_KSCRATCH6","$31","7"],
++        ]
++def gen_get_array_size():
++    size=0
++    size+=len(common_regs)
++    size+=len(cp0_regs)
++    return size
++
++def gen_print_head_and_macro():
++    print("#include <asm/asm.h>")
++    print("#include <asm/regdef.h>")
++    print("")
++    for s in cp0_regs:
++        print("#define %s\t%s,%s" %(s[0],s[1],s[2]))
++    print("")
++def gen_define_global_arg(str, num):
++    print("\t.data")
++    print("\t.global %s" %(str))
++    print("%s:" %(str))
++    print("\t.align 5")
++    print("\t.space %s,0" %(num))
++    print("")
++
++def gen_save_common_regs(index):
++    for s in common_regs:
++        print("\tsw\t%s,%d(k0)" % (s,index))
++        index=index+4
++    return index
++def gen_restore_common_regs(index):
++    for s in common_regs:
++        print("\tlw\t%s,%d(k0)" % (s,index))
++        index=index+4
++    return index
++def gen_save_cp0_regs(index):
++    for s in cp0_regs:
++        print("\tmfc0\tk1,%s" % (s[0]))
++        print("\tsw\tk1,%d(k0)" % (index))
++        index=index+4
++    return index
++def gen_restore_cp0_regs(index):
++    for s in cp0_regs:
++        print("\tlw\tk1,%d(k0)" % (index))
++        print("\tmtc0\tk1,%s" % (s[0]))
++        index=index+4
++    return index
++def gen_print_function(f_name, regs_stack):
++    index=0
++    print("\t.text")
++    print("\t.global %s" %(f_name))
++    print("\t.align 2")
++    print("\t.ent %s,0" %(f_name))
++    print("\tLEAF(%s)" %(f_name))
++    print("%s:" %(f_name))
++    print("\t.set\tpush")
++    print("\t.set\tnoreorder")
++    print("\t.set\tnoat")
++    print("")
++    print("\tla\tk0, %s" %(regs_stack))
++    if f_name == "save_goto":
++        index = gen_save_common_regs(index)
++        print("")
++        index = gen_save_cp0_regs(index)
++        print("")
++        print("\tjr.hb\ta0")
++        print("\tnop")
++    elif f_name == "restore_goto":
++        index = gen_restore_common_regs(index)
++        print("")
++        index = gen_restore_cp0_regs(index)
++        print("")
++        print("\tjr.hb\tra")
++        print("\tnop")
++    else:
++        print("not support")
++    print("")
++    print("\t.set\tat")
++    print("\t.set\treorder")
++    print("\t.set\tpop")
++    print("\tEND(%s)" %(f_name))
++
++
++def main():
++    regs_size=gen_get_array_size()
++    regs_size*=4
++
++    gen_print_head_and_macro()
++    gen_define_global_arg("_regs_stack", regs_size)
++    gen_print_function("save_goto", "_regs_stack")
++    print("")
++    gen_print_function("restore_goto", "_regs_stack")
++    pass
++
++if __name__ == '__main__':
++    main()
+diff --git a/arch/mips/xburst2/soc-x2000/reset.c b/arch/mips/xburst2/soc-x2000/reset.c
+new file mode 100644
+index 000000000..d7a87f1d8
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/reset.c
+@@ -0,0 +1,327 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/irq.h>
++#include <linux/tty.h>
++#include <linux/delay.h>
++#include <linux/proc_fs.h>
++#include <linux/kthread.h>
++#include <linux/syscore_ops.h>
++#include <linux/platform_device.h>
++#include <linux/sched/rt.h>
++#include <linux/slab.h>
++#include <linux/proc_fs.h>
++#include <linux/seq_file.h>
++#include <linux/module.h>
++
++
++#include <soc/base.h>
++#include <soc/cpm.h>
++#include <soc/extal.h>
++
++#include <asm/reboot.h>
++
++#include <ingenic_proc.h>
++
++#define RTC_RTCCR		(0x00)	/* rw, 32, 0x00000081 */
++#define RTC_RTCSR		(0x04)	/* rw, 32, 0x???????? */
++#define RTC_RTCSAR		(0x08)	/* rw, 32, 0x???????? */
++#define RTC_RTCGR		(0x0c)	/* rw, 32, 0x0??????? */
++#define RTC_HCR			(0x20)  /* rw, 32, 0x00000000 */
++#define RTC_HWFCR		(0x24)  /* rw, 32, 0x0000???0 */
++#define RTC_HRCR		(0x28)  /* rw, 32, 0x00000??0 */
++#define RTC_HWCR		(0x2c)  /* rw, 32, 0x00000008 */
++#define RTC_HWRSR		(0x30)  /* rw, 32, 0x00000000 */
++#define RTC_HSPR		(0x34)  /* rw, 32, 0x???????? */
++#define RTC_WENR		(0x3c)  /* rw, 32, 0x00000000 */
++#define RTC_CKPCR		(0x40)  /* rw, 32, 0x00000010 */
++#define RTC_OWIPCR		(0x44)  /* rw, 32, 0x00000010 */
++#define RTC_PWRONCR		(0x48)  /* rw, 32, 0x???????? */
++
++#define WDT_TCSR		(0x0c)  /* rw, 32, 0x???????? */
++#define WDT_TCER		(0x04)  /* rw, 32, 0x???????? */
++#define WDT_TDR			(0x00)  /* rw, 32, 0x???????? */
++#define WDT_TCNT		(0x08)  /* rw, 32, 0x???????? */
++
++#define TCU_TSSR	(0x2C)   /* Timer Stop Set Register */
++#define TCU_TSCR	(0x3C)   /* Timer Stop Clear Register */
++
++#define RTCCR_WRDY		BIT(7)
++#define WENR_WEN                BIT(31)
++
++#define RECOVERY_SIGNATURE	(0x001a1a)
++#define REBOOT_SIGNATURE	(0x003535)
++#define UNMSAK_SIGNATURE	(0x7c0000)//do not use these bits
++
++static void wdt_start_count(int msecs)
++{
++	int time = JZ_EXTAL_RTC / 64 * msecs / 1000;
++	if(time > 65535)
++		time = 65535;
++
++//	outl(1 << 16,TCU_IOBASE + TCU_TSCR);
++
++	outl(0,WDT_IOBASE + WDT_TCNT);		//counter
++	outl(time,WDT_IOBASE + WDT_TDR);	//data
++	outl((3<<3 | 2<<0 | 1 << 10),WDT_IOBASE + WDT_TCSR);
++	outl(0,WDT_IOBASE + WDT_TCER);
++	outl(1,WDT_IOBASE + WDT_TCER);
++}
++
++static void __attribute__((unused)) wdt_stop_count(void)
++{
++	outl(1 << 16,TCU_IOBASE + TCU_TSCR);
++	outl(0,WDT_IOBASE + WDT_TCNT);		//counter
++	outl(65535,WDT_IOBASE + WDT_TDR);	//data
++	outl(1 << 16,TCU_IOBASE + TCU_TSSR);
++}
++
++static int inline rtc_write_reg(int reg,int value)
++{
++	int timeout = 0x2000;
++	while(!(inl(RTC_IOBASE + RTC_RTCCR) & RTCCR_WRDY) && timeout--);
++	if(!timeout)
++	{
++		printk("WARN:NO USE RTC!!!!!\n");
++		return -1;
++	}
++	outl(0xa55a,(RTC_IOBASE + RTC_WENR));
++	while(!(inl(RTC_IOBASE + RTC_RTCCR) & RTCCR_WRDY));
++	while(!(inl(RTC_IOBASE + RTC_WENR) & WENR_WEN));
++	while(!(inl(RTC_IOBASE + RTC_RTCCR) & RTCCR_WRDY));
++	outl(value,(RTC_IOBASE + reg));
++	while(!(inl(RTC_IOBASE + RTC_RTCCR) & RTCCR_WRDY));
++
++	return 0;
++}
++
++/*
++ * Function: Keep power for CPU core when reset.
++ * So that EPC, tcsm and so on can maintain it's status after reset-key pressed.
++ */
++static int inline reset_keep_power(void)
++{
++	return rtc_write_reg(RTC_PWRONCR,
++			     inl(RTC_IOBASE + RTC_PWRONCR) & ~(1 << 0));
++}
++
++#define HWFCR_WAIT_TIME(x) ((x > 0x7fff ? 0x7fff: (0x7ff*(x)) / 2000) << 5)
++#define HRCR_WAIT_TIME(x) ((((x) > 1875 ? 1875: (x)) / 125) << 11)
++
++void jz_hibernate(void)
++{
++	uint32_t rtc_rtccr;
++
++	local_irq_disable();
++	/* Set minimum wakeup_n pin low-level assertion time for wakeup: 1000ms */
++	rtc_write_reg(RTC_HWFCR, HWFCR_WAIT_TIME(1000));
++
++	/* Set reset pin low-level assertion time after wakeup: must  > 60ms */
++	rtc_write_reg(RTC_HRCR, HRCR_WAIT_TIME(125));
++
++	/* clear wakeup status register */
++	rtc_write_reg(RTC_HWRSR, 0x0);
++
++	rtc_write_reg(RTC_HWCR, 0x0);
++
++	rtc_rtccr = inl(RTC_IOBASE + RTC_RTCCR);
++	rtc_rtccr |= 0x1 << 0;
++	rtc_write_reg(RTC_RTCCR,rtc_rtccr);
++
++	/* Put CPU to hibernate mode */
++	rtc_write_reg(RTC_HCR, 0x1);
++
++	/*poweroff the pmu*/
++//	jz_notifier_call(NOTEFY_PROI_HIGH, JZ_POST_HIBERNATION, NULL);
++
++	mdelay(200);
++
++	while(1)
++		printk("%s:We should NOT come here.%08x\n",__func__, inl(RTC_IOBASE + RTC_HCR));
++}
++
++void jz_wdt_restart(char *command)
++{
++	printk("Restarting after 4 ms\n");
++	if ((command != NULL) && !strcmp(command, "recovery")) {
++		while(cpm_inl(CPM_CPPSR) != RECOVERY_SIGNATURE) {
++			printk("set RECOVERY_SIGNATURE\n");
++			cpm_outl(0x5a5a,CPM_CPSPPR);
++			cpm_outl(RECOVERY_SIGNATURE,CPM_CPPSR);
++			cpm_outl(0x0,CPM_CPSPPR);
++			udelay(100);
++		}
++	} else {
++		cpm_outl(0x5a5a,CPM_CPSPPR);
++		cpm_outl(REBOOT_SIGNATURE,CPM_CPPSR);
++		cpm_outl(0x0,CPM_CPSPPR);
++	}
++
++	wdt_start_count(4);
++	mdelay(200);
++	while(1)
++		printk("check wdt.\n");
++}
++
++static void hibernate_restart(void)
++{
++	uint32_t rtc_rtcsr,rtc_rtccr;
++
++	while(!(inl(RTC_IOBASE + RTC_RTCCR) & RTCCR_WRDY));
++
++	rtc_rtcsr = inl(RTC_IOBASE + RTC_RTCSR);
++	rtc_rtccr = inl(RTC_IOBASE + RTC_RTCCR);
++
++	rtc_write_reg(RTC_RTCSAR,rtc_rtcsr + 5);
++	rtc_rtccr &= ~(1 << 4 | 1 << 1);
++	rtc_rtccr |= 0x3 << 2;
++	rtc_write_reg(RTC_RTCCR,rtc_rtccr);
++
++	/* Clear reset status */
++	cpm_outl(0,CPM_RSR);
++
++	/* Set minimum wakeup_n pin low-level assertion time for wakeup: 1000ms */
++	rtc_write_reg(RTC_HWFCR, HWFCR_WAIT_TIME(1000));
++
++	/* Set reset pin low-level assertion time after wakeup: must  > 60ms */
++	rtc_write_reg(RTC_HRCR, HRCR_WAIT_TIME(125));
++
++	/* clear wakeup status register */
++	rtc_write_reg(RTC_HWRSR, 0x0);
++
++	rtc_write_reg(RTC_HWCR, 0x1);
++
++
++	rtc_rtccr = inl(RTC_IOBASE + RTC_RTCCR);
++	rtc_rtccr |= 0x1 << 0;
++	rtc_write_reg(RTC_RTCCR,rtc_rtccr);
++
++
++	/* Put CPU to hibernate mode */
++	rtc_write_reg(RTC_HCR, 0x1);
++
++	mdelay(200);
++	while(1)
++		printk("%s:We should NOT come here.%08x\n",__func__, inl(RTC_IOBASE + RTC_HCR));
++}
++
++#ifdef CONFIG_HIBERNATE_RESET
++void jz_hibernate_restart(char *command)
++{
++	local_irq_disable();
++
++	if ((command != NULL) && !strcmp(command, "recovery")) {
++		jz_wdt_restart(command);
++	}
++
++	hibernate_restart();
++}
++#endif
++
++int __init reset_init(void)
++{
++	pm_power_off = jz_hibernate;
++#ifdef CONFIG_HIBERNATE_RESET
++	_machine_restart = jz_hibernate_restart;
++#else
++	_machine_restart = jz_wdt_restart;
++#endif
++	return 0;
++}
++arch_initcall(reset_init);
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++struct wdt_reset {
++	unsigned stop;
++	unsigned msecs;
++	unsigned count;
++};
++
++/* ============================reset proc=================================== */
++static char *reset_command[] = {"wdt","hibernate","recovery", "poweroff"};
++
++static int reset_show(struct seq_file *filq, void *v)
++{
++	int len = 0, i;
++
++	for(i = 0; i < ARRAY_SIZE(reset_command); i++)
++		seq_printf(filq, "%s\t", reset_command[i]);
++	seq_printf(filq,"\n");
++
++	return len;
++}
++
++static int reset_write(struct file *file, const char __user *buffer,
++		       size_t usize, loff_t *off)
++{
++	int command_size = 0;
++	int i;
++
++	if(usize == 0)
++		return -EINVAL;
++
++	command_size = ARRAY_SIZE(reset_command);
++	for(i = 0;i < command_size; i++) {
++		if(!strncmp(buffer, reset_command[i], strlen(reset_command[i])))
++			break;
++	}
++	if(i == command_size)
++		return -EINVAL;
++
++	local_irq_disable();
++	switch(i) {
++	case 0:
++		jz_wdt_restart(NULL);
++		break;
++	case 1:
++		hibernate_restart();
++		break;
++	case 2:
++		jz_wdt_restart("recovery");
++		break;
++	case 3:
++		jz_hibernate();
++		break;
++	default:
++		printk("not support command %d\n", i);
++	}
++
++	return usize;
++}
++static struct jz_single_file_ops reset_proc_fops = {
++	.read = reset_show,
++	.write = reset_write,
++};
++/* ============================reset proc end=============================== */
++
++static int __init init_reset(void)
++{
++	struct wdt_reset *wdt;
++	struct proc_dir_entry *p, *res;
++
++	wdt = kmalloc(sizeof(struct wdt_reset),GFP_KERNEL);
++	if(!wdt) {
++		return -ENOMEM;
++	}
++
++	wdt->count = 0;
++	wdt->msecs = 3000;
++
++	wdt->stop = 1;
++
++	p = jz_proc_mkdir("reset");
++	if (!p) {
++		pr_warn("create_proc_entry for common reset failed.\n");
++		return -ENODEV;
++	}
++
++	res = jz_proc_create_data("reset", 0444, p, &reset_proc_fops, wdt);
++
++	return 0;
++}
++module_init(init_reset);
+diff --git a/arch/mips/xburst2/soc-x2000/serial.c b/arch/mips/xburst2/soc-x2000/serial.c
+new file mode 100644
+index 000000000..563208c52
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/serial.c
+@@ -0,0 +1,91 @@
++/*
++ * JZ SOC serial routines for early_printk.
++ *
++ * Copyright (C) 2006 Ingenic Semiconductor Inc.
++ *
++ */
++
++#include <asm/io.h>
++
++#include <soc/base.h>
++
++#define UART_BASE	UART0_IOBASE
++#define UART_OFF	0x1000
++
++#define OFF_TDR		(0x00)
++#define OFF_LCR		(0x0C)
++#define OFF_LSR		(0x14)
++
++#define LSR_TDRQ	(1 << 5)
++#define LSR_TEMT	(1 << 6)
++
++static void check_uart(char c);
++
++volatile u8 *uart_base;
++typedef void (*putchar_f_t)(char);
++static putchar_f_t putchar_f = check_uart;
++
++static void putchar(char ch)
++{
++	int timeout = 10000;
++	volatile u8 *base = uart_base;
++	/* Wait for fifo to shift out some bytes */
++	while ((base[OFF_LSR] & (LSR_TDRQ | LSR_TEMT))
++	       != (LSR_TDRQ | LSR_TEMT) && timeout--)
++		;
++	base[OFF_TDR] = (u8)ch;
++}
++
++static void putchar_dummy(char ch)
++{
++	return;
++}
++
++static void check_uart(char c)
++{
++	/* We Couldn't use ioremap() here */
++	volatile u8 *base = (volatile u8*)CKSEG1ADDR(UART0_IOBASE);
++	int i = 0;
++	for(i=0; i<10; i++) {
++		if(base[OFF_LCR])
++			break;
++		base += UART_OFF;
++	}
++
++	if(i<10) {
++		uart_base = base;
++		putchar_f = putchar;
++		putchar_f(c);
++	} else {
++		putchar_f = putchar_dummy;
++	}
++}
++
++/* used by early printk */
++void prom_putchar(char c)
++{
++	putchar_f(c);
++}
++
++void prom_putstr(char *s)
++{
++	while(*s) {
++		if(*s == '\n')
++			putchar_f('\r');
++		putchar_f(*s);
++		s++;
++	}
++}
++
++#if 1
++static char pbuffer[4096];
++void prom_printk(const char *fmt, ...) {
++	va_list args;
++
++	va_start(args, fmt);
++	vsnprintf(pbuffer, 4096, fmt, args);
++	va_end(args);
++
++	prom_putstr(pbuffer);
++}
++#endif
+diff --git a/arch/mips/xburst2/soc-x2000/setup.c b/arch/mips/xburst2/soc-x2000/setup.c
+new file mode 100644
+index 000000000..c4d68f03b
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/setup.c
+@@ -0,0 +1,84 @@
++/*
++ * Ingenic Soc Setup
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2006 Ingenic Semiconductor Inc.
++ */
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/delay.h>
++#include <linux/module.h>
++#include <linux/err.h>
++#include <linux/proc_fs.h>
++#include <linux/ioport.h>
++#include <linux/of_fdt.h>
++#include <linux/of_platform.h>
++#include <linux/clk-provider.h>
++#include <linux/clocksource.h>
++#include <linux/irqchip.h>
++#include <linux/clocksource.h>
++
++#include <asm/prom.h>
++#include <soc/base.h>
++
++void __init cpm_reset(void)
++{
++}
++
++int __init setup_init(void)
++{
++#if 0
++	cpm_reset();
++	/* Set bus priority here */
++	*(volatile unsigned int *)0xb34f0240 = 0x00010003;
++	*(volatile unsigned int *)0xb34f0244 = 0x00010003;
++#endif
++
++	return 0;
++}
++extern void __init init_all_clk(void);
++/* used by linux-mti code */
++extern void *get_fdt_addr(void);
++void __init plat_mem_setup(void)
++{
++	/* use IO_BASE, so that we can use phy addr on hard manual
++	 * directly with in(bwlq)/out(bwlq) in io.h.
++	 */
++	set_io_port_base(IO_BASE);
++	ioport_resource.start	= 0x00000000;
++	ioport_resource.end	= 0xffffffff;
++	iomem_resource.start	= 0x00000000;
++	iomem_resource.end	= 0xffffffff;
++	setup_init();
++
++	__dt_setup_arch(get_fdt_addr());
++
++	return;
++}
++void __init device_tree_init(void)
++{
++	unflatten_and_copy_device_tree();
++}
++
++static int __init plat_of_populate(void)
++{
++	of_platform_default_populate(NULL, NULL, NULL);
++	return 0;
++}
++arch_initcall(plat_of_populate);
++
++void __init plat_time_init(void)
++{
++	of_clk_init(NULL);
++
++	timer_probe();
++}
++
++void __init arch_init_irq(void)
++{
++	irqchip_init();
++}
+diff --git a/arch/mips/xburst2/soc-x2000/sleep_firmware/Makefile b/arch/mips/xburst2/soc-x2000/sleep_firmware/Makefile
+new file mode 100644
+index 000000000..4014918a8
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/sleep_firmware/Makefile
+@@ -0,0 +1,42 @@
++TOPDIR = .
++
++CC = mips-linux-gnu-gcc
++LD = mips-linux-gnu-ld
++OBJCOPY = mips-linux-gnu-objcopy
++OBJDUMP	= mips-linux-gnu-objdump
++drop-sections := .reginfo .mdebug .oomment .note .pdr .options .MIPS.options
++strip-flags   := $(addprefix --remove-section=,$(drop-sections))
++
++CFLAGS += -I$(TOPDIR)/include
++CFLAGS += -nostdinc -Wall -Wundef -Werror-implicit-function-declaration \
++	 -fno-common -EL -Os -march=mips32 -mabi=32 -G 0 -mno-abicalls -fno-pic\
++	 -msoft-float
++
++LDFLAGS	:= -nostdlib -EL -T target.ld
++OBJCOPY_ARGS  := -O elf32-tradlittlemips
++
++OBJS := $(TOPDIR)/src/fastboot_resume.o	\
++	$(TOPDIR)/src/uart.o
++
++
++all: $(TOPDIR)/firmware.bin
++	@hexdump -v -e '"0x" 1/4 "%08x" "," "\n"' $< > $(TOPDIR)/fastboot_resume_code.hex
++
++$(TOPDIR)/firmware.bin:$(TOPDIR)/firmware.o
++	@$(LD) -nostdlib -EL -T $(TOPDIR)/target.ld $(OBJS) -Map $(TOPDIR)/tmp.map -o $(TOPDIR)/tmp.elf
++	@$(OBJCOPY) $(strip-flags) $(OBJCOPY_ARGS) -O binary $(TOPDIR)/tmp.elf $@
++	@$(OBJDUMP) $(TOPDIR)/tmp.elf -D > tmp.dump
++$(TOPDIR)/firmware.o:$(OBJS)
++
++
++%.o:%.c
++	$(CC) $(CFLAGS) -o $@ -c $^
++
++%.o:%.S
++	$(CC) $(CFLAGS) -o $@ -c $^
++
++clean:
++	find . -name "*.o" | xargs rm -vf
++	find . -name "*.o.cmd" | xargs rm -vf
++	rm *.dump *.map *.elf *.bin *.hex
++
+diff --git a/arch/mips/xburst2/soc-x2000/sleep_firmware/Readme b/arch/mips/xburst2/soc-x2000/sleep_firmware/Readme
+new file mode 100644
+index 000000000..215604c5a
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/sleep_firmware/Readme
+@@ -0,0 +1,14 @@
++
++! this wakeup module is none of bussiness with the kernel.
++if you want to modify the code in the module. you should use
++the script mkmodule.sh right here.
++
++
++
++
++
++
++
++
++
++
+diff --git a/arch/mips/xburst2/soc-x2000/sleep_firmware/include/base.h b/arch/mips/xburst2/soc-x2000/sleep_firmware/include/base.h
+new file mode 100644
+index 000000000..b2eb14f02
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/sleep_firmware/include/base.h
+@@ -0,0 +1,91 @@
++
++#ifndef __JZSOC_SOC_DEV_H__
++#define __JZSOC_SOC_DEV_H__
++
++/*
++ * Define the module base addresses
++ */
++#define DDRC_BASE	0xb34f0000
++#define DDRC_APB_OFFSET (-0x4e0000 + 0x2000)
++#define DDR_PHY_OFFSET	(-0x4e0000 + 0x1000)
++
++/* AHB0 BUS Devices Base */
++#define HARB0_IOBASE	0x13000000 /* 64KB, AHB Bus Aribtier */
++#define DDR_PHY_IOBASE	0x13011000 /* 4KB, DDR PHY */
++#define DDRC_H0_IOBASE	0x13012000 /* 4KB, DDR Controller Registers@ASHB0 */
++#define DPU_IOBASE	0x13050000 /* 64KB, LCD Controller */
++#define CIM_IOBASE	0x13060000 /* 64KB, Camera Interface Module */
++#define ROTATE_IOBASE	0x13070000 /* 64KB, Rotate DMA */
++#define HELIX_IOBASE	0x13200000 /* 64KB VPU encoder */
++#define FELIX_IOBASE	0x13300000 /* 64KB VPU decoder */
++#define ISP0_IOBASE	0x13700000 /* 64KB Tiziano ISP0 */
++#define ISP1_IOBASE	0x13800000 /* 64KB Tiziano ISP1 */
++
++/* AHB2 Bus Devices Base */
++#define HARB2_IOBASE	0x13400000 /* 64KB, AHB Bus Arbiter */
++#define NEMC_IOBASE	0x13410000 /* 64KB, External Normal Memory/Boot ROM/OTP Controller */
++#define PDMA_IOBASE	0x13420000 /* 64KB, Programmable DMA Controller */
++#define AES_IOBASE	0x13430000 /* 64KB, AES */
++#define SFC_IOBASE	0x13440000 /* 64KB, SPI Flash Controller */
++#define MSC0_IOBASE	0x13450000 /* 64KB, MMC SD Controller0 */
++#define MSC1_IOBASE	0x13460000 /* 64KB, MMC SD Controller1 */
++#define MSC2_IOBASE	0x13490000 /* 64KB, MMC SD Controller2 */
++#define HASH_IOBASE	0x13470000 /* 64KB, HASH */
++#define RSA_IOBASE	0x13480000 /* 64KB, RSA */
++#define MAC0_IOBASE	0x134b0000 /* 64KB, GMAC/MAC */
++#define MAC1_IOBASE	0x134a0000 /* 64KB, GMAC/MAC */
++#define PWM_IOBASE	0x134c0000 /* 64KB, PWM */
++#define DDRC_H2_IOBASE	0x134f0000 /* 4KB, DDR Controller Register @AHB2 */
++#define AUDIO_IOBASE	0x134d0000 /* 64KB, Aduio System */
++#define OTG_IOBASE	0x13500000 /* 256KB, OTG2.0 Controller */
++#define EFUSE_IOBASE	0x13540000 /* 64KB, EFUSE */
++//#define INTC_IOBASE	0x13600000 /* Interrupt Controller */
++
++
++/* APB BUS Devices Base */
++#define CPM_IOBASE	0x10000000 /* 4KB, Clocks and Power Manager */
++#define TCU_IOBASE	0x10002000 /* 4KB, Timer/Count Unit,OperatingSystemTimer,Watchdog Timer */
++#define WDT_IOBASE	TCU_IOBASE /* 4KB, Timer/Count Unit,OperatingSystemTimer,Watchdog Timer */
++#define RTC_IOBASE	0x10003000 /* 4KB, Real-Time Clock */
++#define GPIO_IOBASE	0x10010000 /* 4KB, General-Purpose I/O */
++#define CODEC_IOBASE	0x10020000 /* 4KB, icodec I/O */
++#define	UART0_IOBASE	0x10030000 /* 4KB, UART0 Controller */
++#define	UART1_IOBASE	0x10031000 /* 4KB, UART1 Controller */
++#define	UART2_IOBASE	0x10032000 /* 4KB, UART2 Controller */
++#define	UART3_IOBASE	0x10033000 /* 4KB, UART3 Controller */
++#define	UART4_IOBASE	0x10034000 /* 4KB, UART4 Controller */
++#define	UART5_IOBASE	0x10035000 /* 4KB, UART5 Controller */
++#define	UART6_IOBASE	0x10036000 /* 4KB, UART6 Controller */
++#define	UART7_IOBASE	0x10037000 /* 4KB, UART7 Controller */
++#define	UART8_IOBASE	0x10038000 /* 4KB, UART8 Controller */
++#define	UART9_IOBASE	0x10039000 /* 4KB, UART9 Controller */
++#define SCC_IOBASE	0x10040000 /* 4KB, Smart Card Controller */
++#define SSI0_IOBASE	0x10043000 /* 4KB, Synchronous Serial Interface */
++#define SSI1_IOBASE	0x10044000 /* 4KB, Synchronous Serial Interface */
++#define I2C0_IOBASE	0x10050000 /* 4KB, I2C 0 Bus Interface */
++#define I2C1_IOBASE	0x10051000 /* 4KB, I2C 1 Bus Interface */
++#define I2C2_IOBASE	0x10052000 /* 4KB, I2C 2 Bus Interface */
++#define I2C3_IOBASE	0x10053000 /* 4KB, I2C 3 Bus Interface */
++#define I2C4_IOBASE	0x10054000 /* 4KB, I2C 4 Bus Interface */
++#define I2C5_IOBASE	0x10055000 /* 4KB, I2C 5 Bus Interface */
++#define SADC_IOBASE	0x10070000 /* 4KB, SADC */
++#define DTRNG_IOBASE	0x10072000 /* 4KB, DTRNG */
++#define MIPI_RX_2_IOBASE	0x10073000 /* 4KB, MIPI RX 2 Lane ctrl */
++#define MIPI_RX_4_IOBASE	0x10074000 /* 4KB, MIPI RX 4 lane ctrl */
++#define MIPI_TX_2_IOBASE	0x10075000 /* 4KB, MIPI TX 2 lane ctrl */
++#define MIPI_RX_PHY_IOBASE	0x10076000 /* 4KB, MIPI RX PHY  */
++#define MIPI_TX_PHY_IOBASE	0x10077000 /* 4KB, MIPI TX PHY  */
++#define USB_PHY_IOBASE		0x10078000 /* 4KB, USB PHY */
++
++/* TODO: Others To Be add */
++/* NAND CHIP Base Address */
++#define NEMC_CS1_IOBASE 0X1b000000
++#define NEMC_CS2_IOBASE 0X1a000000
++#define NEMC_CS3_IOBASE 0X19000000
++#define NEMC_CS4_IOBASE 0X18000000
++#define NEMC_CS5_IOBASE 0X17000000
++#define NEMC_CS6_IOBASE 0X16000000
++
++#define	OST_IOBASE	0x12000000
++
++#endif
+diff --git a/arch/mips/xburst2/soc-x2000/sleep_firmware/include/cpm.h b/arch/mips/xburst2/soc-x2000/sleep_firmware/include/cpm.h
+new file mode 100755
+index 000000000..495e3a4b1
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/sleep_firmware/include/cpm.h
+@@ -0,0 +1,230 @@
++/*
++ * X2000 CPM register definition
++ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.
++ */
++
++#ifndef __CPM_H__
++#define __CPM_H__
++
++#define BIT0            (1 << 0)
++#define BIT1            (1 << 1)
++#define BIT2            (1 << 2)
++#define BIT3            (1 << 3)
++#define BIT4            (1 << 4)
++#define BIT5            (1 << 5)
++#define BIT6            (1 << 6)
++#define BIT7            (1 << 7)
++#define BIT8            (1 << 8)
++#define BIT9            (1 << 9)
++#define BIT10           (1 << 10)
++#define BIT11           (1 << 11)
++#define BIT12           (1 << 12)
++#define BIT13           (1 << 13)
++#define BIT14           (1 << 14)
++#define BIT15           (1 << 15)
++#define BIT16           (1 << 16)
++#define BIT17           (1 << 17)
++#define BIT18           (1 << 18)
++#define BIT19           (1 << 19)
++#define BIT20           (1 << 20)
++#define BIT21           (1 << 21)
++#define BIT22           (1 << 22)
++#define BIT23           (1 << 23)
++#define BIT24           (1 << 24)
++#define BIT25           (1 << 25)
++#define BIT26           (1 << 26)
++#define BIT27           (1 << 27)
++#define BIT28           (1 << 28)
++#define BIT29           (1 << 29)
++#define BIT30           (1 << 30)
++#define BIT31           (1 << 31)
++
++/*
++ * Clock reset and power controller module(CPM) address definition
++ */
++#define	CPM_BASE		0xB0000000
++
++/*
++ * CPM registers offset address definition
++ */
++#define CPM_CPCCR		(0x00)
++#define CPM_RSR			(0x08)
++#define CPM_RSACDR		(0x50)
++#define CPM_CLKGR0		(0x20)
++#define CPM_OPCR		(0x24)
++#define CPM_CLKGR1		(0x28)
++#define CPM_DDRCDR		(0x2c)
++#define CPM_USBPCR		(0x3c)
++#define CPM_USBRDT		(0x40)
++#define CPM_USBVBFIL		(0x44)
++#define CPM_USBPCR1		(0x48)
++#define CPM_MSC0CDR		(0x68)
++#define CPM_MSC1CDR		(0xA4)
++#define CPM_MSC4CDR		(0xA8)
++#define CPM_SFCCDR		(0x74)
++#define CPM_CPCSR		(0xd4)
++#define CPM_SLBC		(0xc8)
++#define CPM_SLPC		(0xcc)
++#define CPM_CPPCR		(0x0c)
++#define CPM_CPAPCR		(0x10)
++#define CPM_CPMPCR		(0x14)
++#define CPM_EXCLK_DS		(0xE0)
++
++/*
++ * CPM registers common define
++ */
++/* Reset status register(RSR) */
++#define RSR_P0R			BIT2
++#define RSR_WR			BIT1
++#define RSR_PR			BIT0
++
++/* Clk Gate Register (CLKGR0) */
++#define CLKGR0_DDR		BIT31
++#define CLKGR0_RSA		BIT25
++#define CLKGR0_AES		BIT24
++#define CLKGR0_PDMA		BIT21
++#define CLKGR0_OST		BIT20
++#define CLKGR0_TCU		BIT18
++#define CLKGR0_UART2		BIT16
++#define CLKGR0_UART1		BIT15
++#define CLKGR0_UART0		BIT14
++#define CLKGR0_MSC1		BIT5
++#define CLKGR0_MSC0		BIT4
++#define CLKGR0_OTG		BIT3
++#define CLKGR0_SFC		BIT2
++#define CLKGR0_EFUSE		BIT1
++
++/* Clk Gate Register (CLKGR1) */
++#define CLKGR1_MSC4		BIT25
++#define CLKGR1_HASH		BIT6
++
++/* Msc Device Clock Divider Register (MSCnCDR) */
++#define MSCCDR_DIV_LSB		0
++#define MSCCDR_DIV_MASK		BITS_H2L(7, MSCCDR_DIV_LSB)
++
++#define MSCCDR_MPCS_LSB		30
++#define MSCCDR_MPCS_MASK	BITS_H2L(31, MSCCDR_MPCS_LSB)
++#define MSCCDR_MPCS_EXCLK	(0x2 << MSCCDR_MPCS_LSB)
++
++#define MSCCDR_BUSY		BIT28
++#define MSCCDR_CE		BIT29
++#define MSCCDR_EXCK_E		BIT21
++
++/* Sleep Pc Register (SLPC) */
++#define SLPC_SW_MAGIC		0x425753 // SWB (software boot)
++#define SLPC_SW_USB_BOOT	(0x2 << 0)
++
++/* APLL Control Register (CPAPCR) */
++#define CPAPCR_PLLFD_LSB	20
++#define CPAPCR_PLLFD_MASK	BITS_H2L(28, CPAPCR_PLLFD_LSB)
++
++#define CPAPCR_PLLRD_LSB	14
++#define CPAPCR_PLLRD_MASK	BITS_H2L(19, CPAPCR_PLLRD_LSB)
++
++#define CPAPCR_PLLOD_LSB	11
++#define CPAPCR_PLLOD_MASK	BITS_H2L(13, CPAPCR_PLLOD_LSB)
++
++#define CPAPCR_PLLRG_LSB	5
++#define CPAPCR_PLLRG_MASK	BITS_H2L(7, CPAPCR_PLLRG_LSB)
++
++#define CPAPCR_PLL_ON		BIT3
++#define CPAPCR_PLL_LOCK		BIT2
++#define CPAPCR_PLL_EN		BIT0
++
++/* EXCLK_DS MSC VOL SELECT */
++#define EXCLKDS_POC_MSC		BIT31
++
++
++#define cpm_readl(o)		readl(CPM_BASE + (o))
++#define cpm_writel(b, o)	writel(b, CPM_BASE + (o))
++
++
++#define __cpm_start_sfc()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_CLKGR0);		\
++		tmp &= ~CLKGR0_SFC;			\
++		cpm_writel(tmp, CPM_CLKGR0);		\
++	} while (0)
++#define __cpm_start_msc()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_CLKGR0);		\
++		tmp &= ~(CLKGR0_MSC0 | CLKGR0_MSC1);	\
++		cpm_writel(tmp, CPM_CLKGR0);		\
++		tmp = cpm_readl(CPM_CLKGR1);		\
++		tmp &= ~CLKGR1_MSC4;			\
++		cpm_writel(tmp, CPM_CLKGR1);		\
++	} while (0)
++#define __cpm_start_otg()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_CLKGR0);		\
++		tmp &= ~CLKGR0_OTG;			\
++		cpm_writel(tmp, CPM_CLKGR0);		\
++	} while (0)
++
++#define __cpm_start_uart0()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_CLKGR0);		\
++		tmp &= ~CLKGR0_UART0;			\
++		cpm_writel(tmp, CPM_CLKGR0);		\
++	} while (0)
++#define __cpm_start_uart1()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_CLKGR0);		\
++		tmp &= ~CLKGR0_UART1;			\
++		cpm_writel(tmp, CPM_CLKGR0);		\
++	} while (0)
++#define __cpm_start_uart2()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_CLKGR0);		\
++		tmp &= ~CLKGR0_UART2;			\
++		cpm_writel(tmp, CPM_CLKGR0);		\
++	} while (0)
++#define __cpm_start_ost()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_CLKGR0);		\
++		tmp &= ~CLKGR0_OST;			\
++		cpm_writel(tmp, CPM_CLKGR0);		\
++	} while (0)
++
++#define __cpm_msc4_vol_1_8V()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_EXCLK_DS);		\
++		tmp |= EXCLKDS_POC_MSC;			\
++		cpm_writel(tmp, CPM_EXCLK_DS);		\
++	} while (0)
++
++#define __cpm_msc4_vol_3_3V()				\
++	do {						\
++		unsigned int tmp;			\
++		tmp = cpm_readl(CPM_EXCLK_DS);		\
++		tmp &= ~EXCLKDS_POC_MSC;			\
++		cpm_writel(tmp, CPM_EXCLK_DS);		\
++	} while (0)
++
++#ifdef FPGA_TEST
++#define __cpm_msc_tuning_set(v, n)				\
++	do {							\
++		unsigned int tmp;				\
++		unsigned int off;				\
++		if(n==0)					\
++			off = CPM_MSC0CDR;			\
++		else if(n==4)					\
++			off = CPM_MSC4CDR;			\
++		else						\
++			off = CPM_MSC1CDR;			\
++		tmp = cpm_readl(off);				\
++		tmp &= ~(1 << 20);				\
++		tmp |= ((v) & 0x1) << 20;			\
++		cpm_writel(tmp, off);				\
++	} while (0)
++#endif
++
++#endif /* __CPM_H__ */
+diff --git a/arch/mips/xburst2/soc-x2000/sleep_firmware/include/ddr.h b/arch/mips/xburst2/soc-x2000/sleep_firmware/include/ddr.h
+new file mode 100644
+index 000000000..241da4607
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/sleep_firmware/include/ddr.h
+@@ -0,0 +1,289 @@
++/*
++ * JZ4780 ddr definitions
++ *
++ * Copyright (c) 2013 Ingenic Semiconductor Co.,Ltd
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __DDR_H__
++#define __DDR_H__
++
++#include <base.h>
++
++/*
++ * DDR Controller Registers
++ **/
++#define DDR_MEM_PHY_BASE		0x20000000
++
++#define DDRC_STATUS		0x0
++#define DDRC_CFG		0x8
++#define DDRC_CTRL		0x10
++#define DDRC_LMR		0x18
++#define DDRC_DLP		0x20
++#define DDRC_AUTOSR_EN	0x28
++#define DDRC_AUTOSR_CNT	0x30
++#define DDRC_REFCNT		0x38
++#define DDRC_DBGINFO	0xE8
++#define DDRC_TIMING(n)	(0x40 + 8 * (n - 1))
++#define DDRC_MMAP0		0x78
++#define DDRC_MMAP1		0x80
++#define DDRC_HREGPRO	0xd8
++#define DDRC_DWCFG		(DDRC_APB_OFFSET + 0x00)
++#define DDRC_DWSTATUS	(DDRC_APB_OFFSET + 0x04)
++#define DDRC_REMAP(n)	(DDRC_APB_OFFSET + 0x08 + 4 * (n - 1))
++#define DDRC_CGUC0		(DDRC_APB_OFFSET + 0x64)
++#define DDRC_CGUC1		(DDRC_APB_OFFSET + 0x68)
++#define DDRC_PREGPRO	(DDRC_APB_OFFSET + 0x6c)
++
++/*
++ * DDR Innophy registers
++ * */
++#define DDRP_INNOPHY_PHY_RST			(DDR_PHY_OFFSET + 0x000)
++#define DDRP_INNOPHY_MEM_CFG			(DDR_PHY_OFFSET + 0x004)
++#define DDRP_INNOPHY_DQ_WIDTH			(DDR_PHY_OFFSET + 0x07c)
++#define DDRP_INNOPHY_CL					(DDR_PHY_OFFSET + 0x014)
++#define DDRP_INNOPHY_CWL				(DDR_PHY_OFFSET + 0x01c)
++#define DDRP_INNOPHY_AL					(DDR_PHY_OFFSET + 0x018)
++#define DDRP_INNOPHY_PLL_FBDIV			(DDR_PHY_OFFSET + 0x080)
++#define DDRP_INNOPHY_PLL_CTRL			(DDR_PHY_OFFSET + 0x084)
++#define DDRP_INNOPHY_PLL_PDIV			(DDR_PHY_OFFSET + 0x088)
++#define DDRP_INNOPHY_PLL_LOCK			(DDR_PHY_OFFSET + 0xc8)
++#define DDRP_INNOPHY_TRAINING_CTRL		(DDR_PHY_OFFSET + 0x008)
++#define DDRP_INNOPHY_CALIB_DONE			(DDR_PHY_OFFSET + 0xcc)
++#define DDRP_INNOPHY_CALIB_DELAY_AL		(DDR_PHY_OFFSET + 0x190)
++#define DDRP_INNOPHY_CALIB_DELAY_AH		(DDR_PHY_OFFSET + 0x194)
++#define DDRP_INNOPHY_CALIB_BYPASS_AL	(DDR_PHY_OFFSET + 0x118)
++#define DDRP_INNOPHY_CALIB_BYPASS_AH	(DDR_PHY_OFFSET + 0x158)
++#define DDRP_INNOPHY_WL_MODE1			(DDR_PHY_OFFSET + 0x00c)
++#define DDRP_INNOPHY_WL_MODE2			(DDR_PHY_OFFSET + 0x010)
++#define DDRP_INNOPHY_WL_DONE			(DDR_PHY_OFFSET + 0x0c0)
++#define DDRP_INNOPHY_INIT_COMP			(DDR_PHY_OFFSET + 0x0d0)
++
++
++/*
++ * DDRC REGISTER BITS DEFINE
++ * */
++
++/* DDRC Status Register */
++#define DDRC_DSTATUS_MISS	(1 << 6)
++#define DDRC_ST_DPDN		(1 << 5) /* 0 DDR memory is NOT in deep-power-down state
++										1 DDR memory is in deep-power-down state */
++#define DDRC_ST_PDN		(1 << 4) /* 0 DDR memory is NOT in power-down state
++									1 DDR memory is in power-down state */
++#define DDRC_ST_AREF		(1 << 3) /* 0 DDR memory is NOT in auto-refresh state
++										1 DDR memory is in auto-refresh state */
++#define DDRC_ST_SREF		(1 << 2) /* 0 DDR memory is NOT in self-refresh state
++										1 DDR memory is in self-refresh state */
++#define DDRC_ST_CKE1		(1 << 1) /* 0 CKE1 Pin is low
++										1 CKE1 Pin is high */
++#define DDRC_ST_CKE0		(1 << 0) /* 0 CKE0 Pin is low
++										1 CKE0 Pin is high */
++
++/* DDRC Configure Register */
++#define DDRC_CFG_ROW1_BIT	29 /* Row Address width. */
++#define DDRC_CFG_ROW1_MASK	(0x7 << DDRC_CFG_ROW1_BIT)
++#define DDRC_CFG_COL1_BIT	26 /* Row Address width. */
++#define DDRC_CFG_COL1_MASK	(0x7 << DDRC_CFG_COL1_BIT)
++#define DDRC_CFG_BA1		25 /* Bank Address width of DDR memory */
++#define DDRC_CFG_IMBA		(1 << 16)
++#define DDRC_CFG_ROW0_BIT	13 /* Row Address width. */
++#define DDRC_CFG_ROW0_MASK	(0x7 << DDRC_CFG_ROW0_BIT)
++#define DDRC_CFG_COL0_BIT	10 /* Row Address width. */
++#define DDRC_CFG_COL0_MASK	(0x7 << DDRC_CFG_COL1_BIT)
++#define DDRC_CFG_BA0		9 /* Bank Address width of DDR memory */
++
++#define DDRC_CFG_TYPE_BIT	3
++#define DDRC_CFG_TYPE_MASK	(0x7 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR1	(2 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_MDDR	(3 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR2	(4 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_LPDDR2	(5 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR3	(6 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_LPDDR3	(7 << DDRC_CFG_TYPE_BIT)
++
++#define DDRC_CFG_ODTEN		(1 << 2)  /* ODT EN */
++#define DDRC_CFG_CS1EN		(1 << 1)  /* DDR Chip-Select-1 Enable */
++#define DDRC_CFG_CS0EN		(1 << 0)  /* DDR Chip-Select-0 Enable */
++
++/* DDRC Control Register */
++#define DDRC_CTRL_DFI_RST	(1 << 23)
++#define DDRC_CTRL_DLL_RST	(1 << 22)
++#define DDRC_CTRL_CTL_RST	(1 << 21)
++#define DDRC_CTRL_CFG_RST	(1 << 20)
++#define DDRC_CTRL_ACTPD		(1 << 15) /* 0 Precharge all banks before entering power-down
++										 1 Do not precharge banks before entering power-down */
++#define DDRC_CTRL_PDT_BIT	12 /* Power-Down Timer */
++#define DDRC_CTRL_PDT_MASK	(0x7 << DDRC_CTRL_PDT_BIT)
++#define DDRC_CTRL_PDT_DIS	(0 << DDRC_CTRL_PDT_BIT) /* power-down disabled */
++#define DDRC_CTRL_PDT_8		(1 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 8 tCK idle */
++#define DDRC_CTRL_PDT_16	(2 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 16 tCK idle */
++#define DDRC_CTRL_PDT_32	(3 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 32 tCK idle */
++#define DDRC_CTRL_PDT_64	(4 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 64 tCK idle */
++#define DDRC_CTRL_PDT_128	(5 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 128 tCK idle */
++
++#define DDRC_CTRL_PD_CCE	(1 << 7) /* Power down clk freq change enable */
++#define DDRC_CTRL_DPD		(1 << 6) /* 1 Drive external MDDR device entering Deep-Power-Down mode */
++#define DDRC_CTRL_SR		(1 << 5) /* 1 Drive external DDR device entering self-refresh mode
++										0 Drive external DDR device exiting self-refresh mode */
++#define DDRC_CTRL_SR_CCE	(1 << 4) /* Self refresh clk stop request enable */
++#define DDRC_CTRL_CKE		(1 << 1) /* 0 Not set CKE Pin High, 1 Set CKE Pin HIGH */
++#define DDRC_CTRL_RESET		(1 << 0) /* 0 End resetting ddrc_controller, 1 Resetting ddrc_controller */
++
++/* DDRC DFI low power handshake control register */
++#define DDRC_DDLP_TCTLUDP_BIT	24
++#define DDRC_DDLP_TCTLUDP_FF	(0xff << DDRC_DDLP_TCTLUDP_BIT)
++
++/* DDRC Load-Mode-Register */
++#define DDRC_LMR_DDR_ADDR_BIT	12 /* When performing a DDR command, DDRC_ADDR[13:0]
++									  corresponding to external DDR address Pin A[13:0] */
++#define DDRC_LMR_DDR_ADDR_MASK	(0xfffff << DDRC_LMR_DDR_ADDR_BIT)
++
++#define DDRC_LMR_MA_BIT		16 /* FOR LPDDR2, MA[9:0] */
++#define DDRC_LMR_OP_BIT		24 /* FOR LPDDR2, OP[9:0] */
++
++#define DDRC_LMR_BA_BIT		9 /* When performing a DDR command, BA[2:0]
++								 corresponding to external DDR address Pin BA[2:0]. */
++#define DDRC_LMR_BA_MASK	(0x7 << DDRC_LMR_BA_BIT)
++#define DDRC_LMR_CMD_BIT	6
++#define DDRC_LMR_CMD_MASK	(0x7 << DDRC_LMR_CMD_BIT)
++#define DDRC_LMR_CMD_PREC	(0 << DDRC_LMR_CMD_BIT)/* Precharge one bank/All banks */
++#define DDRC_LMR_CMD_AUREF	(1 << DDRC_LMR_CMD_BIT)/* Auto-Refresh */
++#define DDRC_LMR_CMD_LMR	(2 << DDRC_LMR_CMD_BIT)/* Load Mode Register */
++#define DDRC_LMR_CMD_ZQCL_CS0	(3 << DDRC_LMR_CMD_BIT)/* ZQCL for DDR3 on CS0 */
++#define DDRC_LMR_CMD_ZQCL_CS1	(4 << DDRC_LMR_CMD_BIT)/* ZQCL for DDR3 on CS1 */
++#define DDRC_LMR_CMD_ZQCS_CS0	(5 << DDRC_LMR_CMD_BIT)/* ZQCS for DDR3 on CS0 */
++#define DDRC_LMR_CMD_ZQCS_CS1	(6 << DDRC_LMR_CMD_BIT)/* ZQCS for DDR3 on CS1 */
++
++#define DDRC_LMR_TMRD_BIT	1
++#define DDRC_LMR_TMRD_MASK	(0x1f << DDRC_LMR_TMRD_BIT)
++#define DDRC_LMR_START		(1 << 0) /* 0 No command is performed
++										1 On the posedge of START, perform a command
++										defined by CMD field */
++
++/* DDRC  Auto-Refresh Counter */
++#define DDRC_REFCNT_REF_EN		(1 << 0) /* Enable Refresh Counter */
++#define DDRC_REFCNT_CLK_DIV_BIT		1  /* Clock Divider for auto-refresh counter. */
++#define DDRC_REFCNT_CLK_DIV_MASK	(0x7 << DDRC_REFCNT_CLKDIV_BIT)
++
++#define DDRC_REFCNT_PREREF_CNT_BIT	4
++#define DDRC_REFCNT_PREREF_CNT_MASK	(0xf << DDRC_REFCNT_PREREF_CNT_BIT)
++#define DDRC_REFCNT_PREREF_CNT(val)	(val << DDRC_REFCNT_PREREF_CNT_BIT)
++#define DDRC_REFCNT_PREREF_CNT_DEFAULT	DDRC_REFCNT_PREREF_CNT(8)
++
++#define DDRC_REFCNT_CNT_BIT		8  /* 8-bit counter */
++#define DDRC_REFCNT_CNT_MASK		(0xff << DDRC_REFCNT_CNT_BIT)
++
++#define DDRC_REFCNT_CON_BIT		16 /* Constant value used to compare with CNT value. */
++#define DDRC_REFCNT_CON_MASK		(0xff << DDRC_REFCNT_CON_BIT)
++
++#define DDRC_REFCNT_TRFC_BIT		24
++#define DDRC_REFCNT_TRFC_MASK		(0x3f << DDRC_REFCNT_TRFC_BIT)
++
++#define DDRC_REFCNT_PREREF_EN_BIT	30
++#define DDRC_REFCNT_PREREF_EN		(1 << DDRC_REFCNT_PREREF_EN_BIT)
++
++#define DDRC_REFCNT_PBREF_EN_BIT	31
++#define DDRC_REFCNT_PBREF_EN		(1 << DDRC_REFCNT_PBREF_EN_BIT)
++
++/* DDRC Memory Map Config Register */
++#define DDRC_MMAP_BASE_BIT		8 /* base address */
++#define DDRC_MMAP_BASE_MASK		(0xff << DDRC_MMAP_BASE_BIT)
++#define DDRC_MMAP_MASK_BIT		0 /* address mask */
++#define DDRC_MMAP_MASK_MASK		(0xff << DDRC_MMAP_MASK_BIT)
++
++#define DDRC_MMAP0_BASE			(0x20 << DDRC_MMAP_BASE_BIT)
++#define DDRC_MMAP1_BASE_64M		(0x24 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++#define DDRC_MMAP1_BASE_128M		(0x28 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++#define DDRC_MMAP1_BASE_256M		(0x30 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++
++#define DDRC_MMAP_MASK_64_64		(0xfc << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++#define DDRC_MMAP_MASK_128_128		(0xf8 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++#define DDRC_MMAP_MASK_256_256		(0xf0 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++
++/* DDR device data width configure register */
++#define DDRC_DWCFG_DFI_INIT_START	(1 << 3)
++
++/* DDR device status register */
++#define DDRC_DWSTATUS_DFI_INIT_COMP	(1 << 0)
++
++/* DDRC AHB Bus Register Protection Register */
++#define DDRC_HREGPRO_HPRO_EN		(1 << 0)
++
++/* DDRC APB Bus Register Protection Register */
++#define DDRC_PREGPRO_PPRO_EN		(1 << 0)
++
++
++/* DDRC clock gate unit configure 0 */
++#define DDRC_CGU_PORT7		(1 << 28)
++#define DDRC_CGU_PORT6		(1 << 24)
++#define DDRC_CGU_PORT5		(1 << 20)
++#define DDRC_CGU_PORT4		(1 << 16)
++#define DDRC_CGU_PORT3		(1 << 12)
++#define DDRC_CGU_PORT2		(1 << 8)
++#define DDRC_CGU_PORT1		(1 << 4)
++#define DDRC_CGU_PORT0		(1 << 0)
++
++/* DDRC clock gate unit configure 1 */
++#define DDRC_CGU_BWM		(1 << 8)
++#define DDRC_CGU_PCTRL		(1 << 4)
++#define DDRC_CGU_SCH		(1 << 1)
++#define DDRC_CGU_PA		(1 << 0)
++
++
++
++/*
++ * DDR INNOPHY REGISTER BITS DEFINE
++ * */
++
++/* DDRP DQ Width Register */
++#define DDRP_DQ_WIDTH_DQ_H		(1 << 1)
++#define DDRP_DQ_WIDTH_DQ_L		(1 << 0)
++
++/* DDRP Pll Ctrl Register */
++#define DDRP_PLL_CTRL_PLLPDEN		(1 << 1)
++
++/* DDRP Training Ctrl Register */
++#define DDRP_TRAINING_CTRL_WL_BP	(1 << 3)
++#define DDRP_TRAINING_CTRL_WL_START	(1 << 2)
++#define DDRP_TRAINING_CTRL_DSCSE_BP	(1 << 1)
++#define DDRP_TRAINING_CTRL_DSACE_START	(1 << 0)
++
++/* DDRP Training Done Register */
++#define DDRP_CALIB_DONE_HDQCFB 		(1 << 3)
++#define DDRP_CALIB_DONE_LDQCFB 		(1 << 2)
++#define DDRP_CALIB_DONE_HDQCFA 		(1 << 1)
++#define DDRP_CALIB_DONE_LDQCFA 		(1 << 0)
++#define DDRP_CALIB_DONE_HWRLFB 		(1 << 3)
++#define DDRP_CALIB_DONE_LWRLFB 		(1 << 2)
++#define DDRP_CALIB_DONE_HWRLFA 		(1 << 1)
++#define DDRP_CALIB_DONE_LWRLFA 		(1 << 0)
++
++/* DDRP CALIB BP Register */
++#define DDRP_CALIB_BP_CYCLESELBH_BIT	4
++#define DDRP_CALIB_BP_OPHCSELBH_BIT	3
++#define DDRP_CALIB_BP_DLLSELBH_BIT	0
++
++/* DDRP Init Complete Register */
++#define DDRP_INIT_COMP			(1 << 0)
++
++#define DDRP_PLL_LOCK			(1 << 3)
++
++#define REG32(addr) *(volatile unsigned int *)(addr)
++
++#define ddr_writel(value, reg)	(REG32(DDRC_BASE + reg) = (value))
++#define ddr_readl(reg)		REG32(DDRC_BASE + reg)
++#endif /* __DDR_H__ */
+diff --git a/arch/mips/xburst2/soc-x2000/sleep_firmware/include/gpio.h b/arch/mips/xburst2/soc-x2000/sleep_firmware/include/gpio.h
+new file mode 100755
+index 000000000..8440f2a91
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/sleep_firmware/include/gpio.h
+@@ -0,0 +1,267 @@
++/*
++ *
++ * X2000 GPIO register definition.
++ *
++ * Copyright (C) 2012 Ingenic Semiconductor Co., Ltd.
++ */
++
++/* check */
++
++#ifndef __GPIO_H__
++#define __GPIO_H__
++
++
++/*************************************************************************
++ * GPIO (General-Purpose I/O Ports)
++ *************************************************************************/
++#define GPIO_BASE	0xB0010000
++
++#define GPA(x) 		(32 * 0 + (x))
++#define GPB(x) 		(32 * 1 + (x))
++#define GPC(x) 		(32 * 2 + (x))
++#define GPD(x) 		(32 * 3 + (x))
++#define GPE(x) 		(32 * 4 + (x))
++#define GPF(x) 		(32 * 5 + (x))
++
++#define GPIO_PORT_NUM   6
++#define MAX_GPIO_NUM	192
++#define GPIO_WAKEUP     GPF(31)  //WAKE_UP key PF31
++
++//n = 0,1,2,3,4 (PORTA, PORTB, PORTC, PORTD, PORTE)
++#define GPIO_PXPIN(n)	(0x00 + (n) * 0x100) /* PIN Level Register */
++
++#define GPIO_PXINT(n)	(0x10 + (n) * 0x100) /* Port Interrupt Register */
++#define GPIO_PXINTS(n)	(0x14 + (n) * 0x100) /* Port Interrupt Set Register */
++#define GPIO_PXINTC(n)	(0x18 + (n) * 0x100) /* Port Interrupt Clear Register */
++
++#define GPIO_PXMASK(n)	(0x20 + (n) * 0x100) /* Port Interrupt Mask Register */
++#define GPIO_PXMASKS(n)	(0x24 + (n) * 0x100) /* Port Interrupt Mask Set Reg */
++#define GPIO_PXMASKC(n)	(0x28 + (n) * 0x100) /* Port Interrupt Mask Clear Reg */
++
++#define GPIO_PXPAT1(n)	(0x30 + (n) * 0x100) /* Port Pattern 1 Register */
++#define GPIO_PXPAT1S(n)	(0x34 + (n) * 0x100) /* Port Pattern 1 Set Reg. */
++#define GPIO_PXPAT1C(n)	(0x38 + (n) * 0x100) /* Port Pattern 1 Clear Reg. */
++
++#define GPIO_PXPAT0(n)	(0x40 + (n) * 0x100) /* Port Pattern 0 Register */
++#define GPIO_PXPAT0S(n)	(0x44 + (n) * 0x100) /* Port Pattern 0 Set Register */
++#define GPIO_PXPAT0C(n)	(0x48 + (n) * 0x100) /* Port Pattern 0 Clear Register */
++
++#define GPIO_PXFLG(n)	(0x50 + (n) * 0x100) /* Port Flag Register */
++#define GPIO_PXFLGC(n)	(0x58 + (n) * 0x100) /* Port Flag clear Register */
++
++#define GPIO_PXPU(n)	(0x80 + (n) * 0x100) /* PORT PULL-UP State Register */
++#define GPIO_PXPUS(n)	(0x84 + (n) * 0x100) /* PORT PULL-UP State Set Register*/
++#define GPIO_PXPUC(n)	(0x88 + (n) * 0x100) /* PORT PULL-UP State Clear Register */
++
++#define GPIO_PXPD(n)	(0x90 + (n) * 0x100) /* PORT PULL-DOWN State Register */
++#define GPIO_PXPDS(n)	(0x94 + (n) * 0x100) /* PORT PULL-DOWN State Set Register */
++#define GPIO_PXPDC(n)	(0x98 + (n) * 0x100) /* PORT PULL-DOWN State Set Register */
++
++#define gpio_readl(o)		readl(GPIO_BASE + (o))
++#define gpio_writel(b, o)	writel(b, GPIO_BASE + (o))
++
++#ifndef __MIPS_ASSEMBLER
++
++/*----------------------------------------------------------------
++ * p is the port number (0,1,2,3,4,5)
++ * o is the pin offset (0-31) inside the port
++ * n is the absolute number of a pin (0-127), regardless of the port
++ */
++
++//----------------------------------------------------------------
++/*
++ * Gpio Pull set
++ */
++#define __gpio_set_hiz(v, p)			\
++do {						\
++	unsigned long val = v;			\
++	gpio_writel(val, GPIO_PXPUC(p));	\
++	gpio_writel(val, GPIO_PXPDC(p));	\
++} while (0)
++
++/*
++ * UART0_TxD, UART0_RxD, PD27
++ */
++#define __gpio_as_uart0()			\
++do {						\
++	gpio_writel((3 << 23), GPIO_PXINTC(3));	\
++	gpio_writel((3 << 23), GPIO_PXMASKC(3));\
++	gpio_writel((3 << 23), GPIO_PXPAT1S(3));\
++	gpio_writel((3 << 23), GPIO_PXPAT0C(3));\
++} while (0)
++
++/*
++ * UART1_TxD, UART1_RxD, PA23
++ */
++#define __gpio_as_uart1()			\
++do {						\
++	gpio_writel((3 << 23), GPIO_PXINTC(2));	\
++	gpio_writel((3 << 23), GPIO_PXMASKC(2));	\
++	gpio_writel((3 << 23), GPIO_PXPAT1C(2));	\
++	gpio_writel((3 << 23), GPIO_PXPAT0S(2));	\
++} while (0)
++
++/*
++ * UART2_TxD, UART2_RxD
++ */
++#define __gpio_as_uart2()			\
++do {						\
++	gpio_writel((3 << 30), GPIO_PXINTC(3));	\
++	gpio_writel((3 << 30), GPIO_PXMASKC(3));\
++	gpio_writel((3 << 30), GPIO_PXPAT1C(3));\
++	gpio_writel((3 << 30), GPIO_PXPAT0C(3));\
++} while (0)
++
++/*
++ * CS2#, RD#, WR#, WAIT#, A0 ~ A5
++ * @n: chip select number(1 ~ 4)
++ */
++#define __gpio_as_nor(n)				\
++do {							\
++	gpio_writel((0x7 << 13), GPIO_PXINTC(1));	\
++	gpio_writel((0x7 << 13), GPIO_PXMASKC(1));	\
++	gpio_writel((0x7 << 13), GPIO_PXPAT1C(1));	\
++	gpio_writel((0x7 << 13), GPIO_PXPAT0C(1));	\
++	gpio_writel((0x3 << 23), GPIO_PXINTC(2));	\
++	gpio_writel((0x3 << 23), GPIO_PXMASKC(2));	\
++	gpio_writel((0x3 << 23), GPIO_PXPAT1S(2));	\
++	gpio_writel((0x3 << 23), GPIO_PXPAT0S(2));	\
++} while (0)
++/*
++ * D0 ~ D7
++ */
++#define __gpio_as_nor_8bit()						\
++do {									\
++	gpio_writel((0xffffffff), GPIO_PXINTC(1));		\
++	gpio_writel((0xffffffff), GPIO_PXMASKC(1));		\
++	gpio_writel((0xffffffff), GPIO_PXPAT1C(1));		\
++	gpio_writel((0xffffffff), GPIO_PXPAT0C(1));		\
++} while (0)
++
++/*
++ * D0 ~ D15
++ */
++#define __gpio_as_nor_16bit()						\
++do {	               							\
++	gpio_writel((0xffffffff), GPIO_PXINTC(1));		\
++	gpio_writel((0xffffffff), GPIO_PXMASKC(1));		\
++	gpio_writel((0xffffffff), GPIO_PXPAT1C(1));		\
++	gpio_writel((0xffffffff), GPIO_PXPAT0C(1));		\
++} while (0)
++
++
++/* gpio as sfc disable pull */
++/* PE16 - PE21 */
++#define __gpio_as_3_3V_sfc()				\
++do {						\
++	gpio_writel((0x3f << 16), GPIO_PXINTC(4));	\
++	gpio_writel((0x3f << 16), GPIO_PXMASKC(4));	\
++	gpio_writel((0x3f << 16), GPIO_PXPAT1C(4));	\
++	gpio_writel((0x3f << 16), GPIO_PXPAT0C(4));	\
++	if(!EFUSE_SWC_SFC)				\
++		__gpio_set_hiz((0x3f) << 16, 4);	\
++} while (0)
++
++/* gpio as sfc disable pull */
++/* PD17 - PD22 */
++#define __gpio_as_1_8V_sfc()				\
++do {						\
++	gpio_writel((0x3f << 17), GPIO_PXINTC(3));	\
++	gpio_writel((0x3f << 17), GPIO_PXMASKC(3));	\
++	gpio_writel((0x3f << 17), GPIO_PXPAT1C(3));	\
++	gpio_writel((0x3f << 17), GPIO_PXPAT0S(3));	\
++	if(!EFUSE_SWC_SFC)				\
++		__gpio_set_hiz((0x3f) << 17, 3);	\
++} while (0)
++
++/*
++ * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D7
++ */
++
++/* pull disable */
++
++/* PD17 - PD26, func0, 1bit*/
++#define __gpio_as_msc0_1bit()			\
++do {						\
++	gpio_writel(0x7 << 17, GPIO_PXINTC(3));	\
++	gpio_writel(0x7 << 17, GPIO_PXMASKC(3));	\
++	gpio_writel(0x7 << 17, GPIO_PXPAT1C(3));	\
++	gpio_writel(0x7 << 17, GPIO_PXPAT0C(3));	\
++	if(!EFUSE_SWC_MSC)			\
++		__gpio_set_hiz((0x7 << 17), 3);	\
++} while (0)
++
++/* PD17 - PD26, func0, 4bit*/
++#define __gpio_as_msc0_4bit()			\
++do {						\
++	gpio_writel(0x3f << 17, GPIO_PXINTC(3));	\
++	gpio_writel(0x3f << 17, GPIO_PXMASKC(3));	\
++	gpio_writel(0x3f << 17, GPIO_PXPAT1C(3));	\
++	gpio_writel(0x3f << 17, GPIO_PXPAT0C(3));	\
++	if(!EFUSE_SWC_MSC)			\
++		__gpio_set_hiz((0x3f << 17), 3);	\
++} while (0)
++
++
++/* PD08 - PD13, func0, 1bit*/
++#define __gpio_as_msc1_1bit()			\
++do {						\
++	gpio_writel(0x7 << 8, GPIO_PXINTC(3));	\
++	gpio_writel(0x7 << 8, GPIO_PXMASKC(3));	\
++	gpio_writel(0x7 << 8, GPIO_PXPAT1C(3));	\
++	gpio_writel(0x7 << 8, GPIO_PXPAT0C(3));	\
++	if(!EFUSE_SWC_MSC)			\
++		__gpio_set_hiz((0x7 << 8), 3);	\
++} while (0)
++
++/* PD08 - PD13, func0, 4bit*/
++#define __gpio_as_msc1_4bit()			\
++do {						\
++	gpio_writel(0x3f << 8, GPIO_PXINTC(3));	\
++	gpio_writel(0x3f << 8, GPIO_PXMASKC(3));	\
++	gpio_writel(0x3f << 8, GPIO_PXPAT1C(3));	\
++	gpio_writel(0x3f << 8, GPIO_PXPAT0C(3));	\
++	if(!EFUSE_SWC_MSC)			\
++		__gpio_set_hiz((0x3f << 8), 3);	\
++} while (0)
++
++
++/* PE0 - PE5, func0 */
++#define __gpio_as_msc4_1bit()			\
++do {						\
++	gpio_writel((0x7 << 0), GPIO_PXINTC(4));	\
++	gpio_writel((0x7 << 0), GPIO_PXMASKC(4));	\
++	gpio_writel((0x7 << 0), GPIO_PXPAT1C(4));	\
++	gpio_writel((0x7 << 0), GPIO_PXPAT0C(4));	\
++	if(!EFUSE_SWC_MSC)				\
++		__gpio_set_hiz((0x7) << 0, 4);	\
++} while (0)
++
++/* PE0 - PE5, func0 */
++#define __gpio_as_msc4_4bit()			\
++do {						\
++	gpio_writel((0x3f << 0), GPIO_PXINTC(4));	\
++	gpio_writel((0x3f << 0), GPIO_PXMASKC(4));	\
++	gpio_writel((0x3f << 0), GPIO_PXPAT1C(4));	\
++	gpio_writel((0x3f << 0), GPIO_PXPAT0C(4));	\
++	if(!EFUSE_SWC_MSC)				\
++		__gpio_set_hiz((0x3f) << 0, 4);	\
++} while (0)
++
++#define bootsel_gpio_init() 			\
++do{						\
++	gpio_writel((0x7 << 25), GPIO_PXINTC(4));	\
++	gpio_writel((0x7 << 25), GPIO_PXMASKS(4));\
++	gpio_writel((0x7 << 25), GPIO_PXPAT1S(4));\
++	gpio_writel((0x7 << 25), GPIO_PXPAT0C(4));\
++	__gpio_set_hiz((0x7) << 25, 4);	\
++}while(0)
++
++#define boot_select()	((gpio_readl(GPIO_PXPIN(4)) >> 25) & 0x7)
++
++#define BOOT_SELECT_3_3V	(0)
++#define BOOT_SELECT_1_8V	(1)
++#endif /* __MIPS_ASSEMBLER */
++
++#endif /* __GPIO_H__ */
++
+diff --git a/arch/mips/xburst2/soc-x2000/sleep_firmware/include/pm_fastboot.h b/arch/mips/xburst2/soc-x2000/sleep_firmware/include/pm_fastboot.h
+new file mode 100644
+index 000000000..3bad4d885
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/sleep_firmware/include/pm_fastboot.h
+@@ -0,0 +1,106 @@
++
++
++#define RTC_SLEEP_MEMORY_START          0xb0004000
++#define RTC_SLEEP_MEMORY_END            0xb0005000
++#define RTC_RAM_SP_ADDR                 (RTC_RAM_DATA_ADDR - 4)
++//#define RTC_RAM_SP_SIZE                 (256 - 4)
++#define RTC_RAM_DATA_ADDR               0xb0004c00
++#define RTC_RAM_DATA_SIZE               1024
++#define RTC_RAM_CODE_ADDR1              0xb0004000
++#define RTC_RAM_CODE_ADDR2              (RTC_RAM_CODE_ADDR1 + 64)
++#define RTC_RAM_CODE_SIZE               0xb00
++
++#define SLEEP_CPU_SLEEP_TEXT		0xb2400000
++#define SLEEP_CPU_SLEEP_LEN		4096
++
++
++
++struct pll_resume_reg {
++	unsigned int cpccr;
++	unsigned int cppcr;
++	unsigned int cpapcr;
++	unsigned int cpmpcr;
++	unsigned int cpepcr;
++	unsigned int ddrcdr;
++};
++
++struct ddrc_resume_reg {
++	unsigned int dcfg;
++	unsigned int dctrl;
++	unsigned int dlmr;
++	unsigned int ddlp;
++	unsigned int dasr_en;
++	unsigned int dasr_cnt;
++	unsigned int drefcnt;
++	unsigned int dtimming1;
++	unsigned int dtimming2;
++	unsigned int dtimming3;
++	unsigned int dtimming4;
++	unsigned int dtimming5;
++	unsigned int dmmap0;
++	unsigned int dmmap1;
++#if 0
++	unsigned int dbwcfg;
++	unsigned int dbwstp;
++	unsigned int hregpro;
++	unsigned int dbgen;
++#endif
++	unsigned int dwcfg;
++	unsigned int dremap1;
++	unsigned int dremap2;
++	unsigned int dremap3;
++	unsigned int dremap4;
++	unsigned int dremap5;
++#if 0
++	unsigned int cpac;
++	unsigned int cchc0;
++	unsigned int cchc1;
++	unsigned int cchc2;
++	unsigned int cchc3;
++	unsigned int cchc4;
++	unsigned int cchc5;
++	unsigned int cchc6;
++	unsigned int cchc7;
++	unsigned int cschc0;
++	unsigned int cschc1;
++	unsigned int cschc2;
++	unsigned int cschc3;
++	unsigned int cmonc0;
++	unsigned int cmonc1;
++	unsigned int cmonc2;
++	unsigned int cmonc3;
++	unsigned int cmonc4;
++#endif
++	unsigned int ccguc0;
++	unsigned int ccguc1;
++#if 0
++	unsigned int pregpro;
++	unsigned int bufcfg;
++#endif
++};
++
++struct ddr_phy_resume_reg {
++	unsigned int phy_rst;
++	unsigned int mem_cfg;
++	unsigned int dq_width;
++	unsigned int cl;
++	unsigned int al;
++	unsigned int cwl;
++	unsigned int pll_fbdiv;
++	unsigned int pll_ctrl;
++	unsigned int pll_pdiv;
++	unsigned int training_ctrl;
++	unsigned int calib_bypass_al;
++	unsigned int calib_bypass_ah;
++	unsigned int wl_mode1;
++	unsigned int wl_mode2;
++
++};
++
++struct store_regs {
++	unsigned int resume_pc;
++	struct pll_resume_reg pll_resume_reg;
++	struct ddrc_resume_reg ddrc_resume_reg;
++	struct ddr_phy_resume_reg ddr_phy_resume_reg;
++};
++
+diff --git a/arch/mips/xburst2/soc-x2000/sleep_firmware/include/uart.h b/arch/mips/xburst2/soc-x2000/sleep_firmware/include/uart.h
+new file mode 100755
+index 000000000..b87b2d236
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/sleep_firmware/include/uart.h
+@@ -0,0 +1,113 @@
++/*
++ *
++ * X2000 UART register definition.
++ *
++ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.
++ */
++
++#ifndef __UART_H__
++#define __UART_H__
++
++#define readb(addr)     (*(volatile unsigned char *)(addr))
++#define readw(addr)     (*(volatile unsigned short *)(addr))
++#define readl(addr)     (*(volatile unsigned int *)(addr))
++#define writeb(b, addr) (*(volatile unsigned char *)(addr)) = (b)
++#define writew(b, addr) (*(volatile unsigned short *)(addr)) = (b)
++#define writel(b, addr) (*(volatile unsigned int *)(addr)) = (b)
++
++void serial_init(int);
++void serial_puts(int, const char *);
++void serial_put_hex(int, unsigned int);
++
++
++#define	UART0_BASE	0xB0030000
++
++/*************************************************************************
++ * UART
++ *************************************************************************/
++
++#define UART_BASE	UART0_BASE
++#define UART_OFF	0x1000
++
++/* Register Offset */
++#define OFF_RDR(n)		((n) * UART_OFF + 0x00)	/* R  8b H'xx */
++#define OFF_TDR(n)		((n) * UART_OFF + 0x00)	/* W  8b H'xx */
++#define OFF_DLLR(n)		((n) * UART_OFF + 0x00)	/* RW 8b H'00 */
++#define OFF_DLHR(n)		((n) * UART_OFF + 0x04)	/* RW 8b H'00 */
++#define OFF_IER(n)		((n) * UART_OFF + 0x04)	/* RW 8b H'00 */
++#define OFF_ISR(n)		((n) * UART_OFF + 0x08)	/* R  8b H'01 */
++#define OFF_FCR(n)		((n) * UART_OFF + 0x08)	/* W  8b H'00 */
++#define OFF_LCR(n)		((n) * UART_OFF + 0x0C)	/* RW 8b H'00 */
++#define OFF_MCR(n)		((n) * UART_OFF + 0x10)	/* RW 8b H'00 */
++#define OFF_LSR(n)		((n) * UART_OFF + 0x14)	/* R  8b H'00 */
++#define OFF_MSR(n)		((n) * UART_OFF + 0x18)	/* R  8b H'00 */
++#define OFF_SPR(n)		((n) * UART_OFF + 0x1C)	/* RW 8b H'00 */
++#define OFF_SIRCR(n)	((n) * UART_OFF + 0x20)	/* RW 8b H'00, UART0 */
++#define OFF_UMR(n)		((n) * UART_OFF + 0x24)	/* RW 8b H'00, UART M Register */
++#define OFF_UACR(n)		((n) * UART_OFF + 0x28)	/* RW 8b H'00, UART Add Cycle Register */
++#define OFF_URCR(n)		((n) * UART_OFF + 0x40)	/* R  8b   00, UART RXFIFO Counter Register */
++#define OFF_UTCR(n)		((n) * UART_OFF + 0x44)	/* R  8b   00, UART TXFIFO Counter Register */
++
++/*
++ * Define macros for UARTFCR
++ * UART FIFO Control Register
++ */
++#define UARTFCR_FE	(1 << 0)	/* 0: non-FIFO mode  1: FIFO mode */
++#define UARTFCR_RFLS	(1 << 1)	/* write 1 to flush receive FIFO */
++#define UARTFCR_TFLS	(1 << 2)	/* write 1 to flush transmit FIFO */
++#define UARTFCR_DMS	(1 << 3)	/* 0: disable DMA mode */
++#define UARTFCR_UUE	(1 << 4)	/* 0: disable UART */
++#define UARTFCR_RTRG	(3 << 6)	/* Receive FIFO Data Trigger */
++#define UARTFCR_RTRG_1	(0 << 6)
++#define UARTFCR_RTRG_16	(1 << 6)
++#define UARTFCR_RTRG_32	(2 << 6)
++#define UARTFCR_RTRG_60	(3 << 6)
++
++/*
++ * Define macros for UARTLCR
++ * UART Line Control Register
++ */
++#define UARTLCR_WLEN	(3 << 0)	/* word length */
++#define UARTLCR_WLEN_5	(0 << 0)
++#define UARTLCR_WLEN_6	(1 << 0)
++#define UARTLCR_WLEN_7	(2 << 0)
++#define UARTLCR_WLEN_8	(3 << 0)
++#define UARTLCR_STOP	(1 << 2)	/* 0: 1 stop bit when word length is 5,6,7,8
++					   1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
++#define UARTLCR_STOP1	(0 << 2)
++#define UARTLCR_STOP2	(1 << 2)
++#define UARTLCR_PE	(1 << 3)	/* 0: parity disable */
++#define UARTLCR_PROE	(1 << 4)	/* 0: even parity  1: odd parity */
++#define UARTLCR_SPAR	(1 << 5)	/* 0: sticky parity disable */
++#define UARTLCR_SBRK	(1 << 6)	/* write 0 normal, write 1 send break */
++#define UARTLCR_DLAB	(1 << 7)	/* 0: access UARTRDR/TDR/IER  1: access UARTDLLR/DLHR */
++
++/*
++ * Define macros for SIRCR
++ * Slow IrDA Control Register
++ */
++#define SIRCR_TSIRE	(1 << 0)  /* 0: transmitter is in UART mode  1: SIR mode */
++#define SIRCR_RSIRE	(1 << 1)  /* 0: receiver is in UART mode  1: SIR mode */
++#define SIRCR_TPWS	(1 << 2)  /* 0: transmit 0 pulse width is 3/16 of bit length
++					   1: 0 pulse width is 1.6us for 115.2Kbps */
++#define SIRCR_TDPL	(1 << 3)  /* 0: encoder generates a positive pulse for 0 */
++#define SIRCR_RDPL	(1 << 4)  /* 0: decoder interprets positive pulse as 0 */
++
++/*
++ * Define macros for UART_LSR
++ * UART Line Status Register
++ */
++#define UART_LSR_DR	(1 << 0)	/* 0: receive FIFO is empty  1: receive data is ready */
++#define UART_LSR_ORER	(1 << 1)	/* 0: no overrun error */
++#define UART_LSR_PER	(1 << 2)	/* 0: no parity error */
++#define UART_LSR_FER	(1 << 3)	/* 0; no framing error */
++#define UART_LSR_BRK	(1 << 4)	/* 0: no break detected  1: receive a break signal */
++#define UART_LSR_TDRQ	(1 << 5)	/* 1: transmit FIFO half "empty" */
++#define UART_LSR_TEMT	(1 << 6)	/* 1: transmit FIFO and shift registers empty */
++#define UART_LSR_RFER	(1 << 7)	/* 0: no receive error  1: receive error in FIFO mode */
++
++#define uart_readl(o)		readl(UART_BASE + (o))
++#define uart_writel(b, o)	writel(b, UART_BASE + (o))
++
++#endif /* __UART_H__ */
++
+diff --git a/arch/mips/xburst2/soc-x2000/sleep_firmware/mkmodule.sh b/arch/mips/xburst2/soc-x2000/sleep_firmware/mkmodule.sh
+new file mode 100755
+index 000000000..698e07160
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/sleep_firmware/mkmodule.sh
+@@ -0,0 +1,7 @@
++#!/bin/sh
++
++make clean
++
++make
++
++cp fastboot_resume_code.hex ../
+diff --git a/arch/mips/xburst2/soc-x2000/sleep_firmware/src/fastboot_resume.c b/arch/mips/xburst2/soc-x2000/sleep_firmware/src/fastboot_resume.c
+new file mode 100644
+index 000000000..dae83e238
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/sleep_firmware/src/fastboot_resume.c
+@@ -0,0 +1,328 @@
++#include <ddr.h>
++#include <pm_fastboot.h>
++
++
++
++//#define FASTBOOT_DEBUG
++#ifdef FASTBOOT_DEBUG
++
++#include <uart.h>
++
++#define DEBUG(s)        serial_puts(2, s)
++#define DEBUG_HEX(a)    serial_put_hex(2, a)
++
++
++#define	GPIO_PULSE()		\
++	while (1) {		\
++		*(volatile unsigned int *)0xb0010218 = (1 << 20);	\
++		*(volatile unsigned int *)0xb0010224 = (1 << 20);	\
++		*(volatile unsigned int *)0xb0010238 = (1 << 20);	\
++		*(volatile unsigned int *)0xb0010248 = (1 << 20);	\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		*(volatile unsigned int *)0xb0010218 = (1 << 20);	\
++		*(volatile unsigned int *)0xb0010224 = (1 << 20);	\
++		*(volatile unsigned int *)0xb0010238 = (1 << 20);	\
++		*(volatile unsigned int *)0xb0010244 = (1 << 20);	\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++		__asm__ __volatile__("nop\n\t");			\
++	}
++
++
++#else
++#define DEBUG(s)
++#define DEBUG_HEX(a)
++#endif
++
++
++static struct store_regs *store_regs;
++
++
++
++void sys_clk_restore(void)
++{
++	unsigned int tmp;
++	struct pll_resume_reg *pll_resume_reg;
++	store_regs = (struct store_regs *)RTC_RAM_DATA_ADDR;
++
++	pll_resume_reg = &store_regs->pll_resume_reg;
++
++	tmp = *(volatile unsigned int *)0xb0000000;
++
++	tmp &= ~(7 << 20);
++	tmp |= (pll_resume_reg->cpccr & 0x000fffff);
++	*(volatile unsigned int *)0xb0000000 = tmp;
++	*(volatile unsigned int *)0xb0000000 |= (7 << 20);
++	while ((*(volatile unsigned int *)0xb00000d4) & 0x7);
++
++	tmp = *(volatile unsigned int *)0xb0000000;
++	tmp &= ~(0xff << 24);
++	tmp |= (pll_resume_reg->cpccr & 0xff000000);
++	*(volatile unsigned int *)0xb0000000 = tmp;
++
++
++	while (!((*(volatile unsigned int *)0xb00000d4 & 0xf0000000) == 0xf0000000));
++
++}
++
++
++static void pll_restore(void)
++{
++	struct pll_resume_reg *pll_resume_reg;
++	store_regs = (struct store_regs *)RTC_RAM_DATA_ADDR;
++
++	pll_resume_reg = &store_regs->pll_resume_reg;
++
++	*(volatile unsigned int *)0xb000000c = pll_resume_reg->cppcr;
++
++	*(volatile unsigned int *)0xb0000010 = (pll_resume_reg->cpapcr & 0xfffffff0) | 1;
++	while (!((*(volatile unsigned int *)0xb0000010 >> 3) & 1));
++
++	*(volatile unsigned int *)0xb0000014 = (pll_resume_reg->cpmpcr & 0xfffffff0) | 1;
++	while (!((*(volatile unsigned int *)0xb0000014 >> 3) & 1));
++
++	*(volatile unsigned int *)0xb0000018 = (pll_resume_reg->cpepcr & 0xfffffff0) | 1;
++	while (!((*(volatile unsigned int *)0xb0000018 >> 3) & 1));
++
++
++	*(volatile unsigned int *)0xb000002c = (pll_resume_reg->ddrcdr & 0xc000000f);
++	*(volatile unsigned int *)0xb000002c |= (1 << 29);
++	while (((*(volatile unsigned int *)0xb000002c) >> 28) & 1);
++
++	sys_clk_restore();
++}
++
++
++
++static void phy_pll_init(struct ddr_phy_resume_reg *ddr_phy_resume_reg)
++{
++	*(volatile unsigned int *)0xb3011084 |= (1 << 1);
++
++	*(volatile unsigned int *)0xb3010080 &= ~0xff;
++	*(volatile unsigned int *)0xb3011080 |= ddr_phy_resume_reg->pll_fbdiv;
++
++	*(volatile unsigned int *)0xb3010088 &= ~0xff;
++	*(volatile unsigned int *)0xb3011088 |= ddr_phy_resume_reg->pll_pdiv;
++
++	*(volatile unsigned int *)0xb3010084 &= ~3;
++	*(volatile unsigned int *)0xb3011084 |= (ddr_phy_resume_reg->pll_ctrl & 0x1);
++
++	*(volatile unsigned int *)0xb3011084 &= ~(1 << 1);	//enable pll
++
++	while(!(*(volatile unsigned int *)0xb30110c8 & (1 << 3)));	//wait pll lock
++}
++
++static void phy_cfg(struct ddr_phy_resume_reg *ddr_phy_resume_reg)
++{
++	*(volatile unsigned int *)0xb3011004 = ddr_phy_resume_reg->mem_cfg;
++	*(volatile unsigned int *)0xb301107c = ddr_phy_resume_reg->dq_width;
++	*(volatile unsigned int *)0xb3011014 = ddr_phy_resume_reg->cl;
++	*(volatile unsigned int *)0xb3011018 = ddr_phy_resume_reg->al;
++	*(volatile unsigned int *)0xb301101c = ddr_phy_resume_reg->cwl;
++}
++
++
++
++static void dfi_init(struct ddrc_resume_reg *ddrc_resume_reg)
++{
++	*(volatile unsigned int *)0xb3012000 &= ~(1 << 3);	//dfi_init_start = 0
++	while(!(*(volatile unsigned int *)0xb3012004 & 0x1));	//wait dfi_init_compllete
++	*(volatile unsigned int *)0xb34f0008 = ddrc_resume_reg->dcfg;
++
++}
++
++
++static void ddrc_init(struct ddrc_resume_reg *ddrc_resume_reg)
++{
++	*(volatile unsigned int *)0xb34f0040 = ddrc_resume_reg->dtimming1;
++	*(volatile unsigned int *)0xb34f0048 = ddrc_resume_reg->dtimming2;
++	*(volatile unsigned int *)0xb34f0050 = ddrc_resume_reg->dtimming3;
++	*(volatile unsigned int *)0xb34f0058 = ddrc_resume_reg->dtimming4;
++	*(volatile unsigned int *)0xb34f0060 = ddrc_resume_reg->dtimming5;
++	*(volatile unsigned int *)0xb34f0078 = ddrc_resume_reg->dmmap0;
++	*(volatile unsigned int *)0xb34f0080 = ddrc_resume_reg->dmmap1;
++	*(volatile unsigned int *)0xb34f0038 = ddrc_resume_reg->drefcnt;
++	*(volatile unsigned int *)0xb34f0010 = ddrc_resume_reg->dctrl;
++
++	*(volatile unsigned int *)0xb3012008 = ddrc_resume_reg->dremap1;
++	*(volatile unsigned int *)0xb301200c = ddrc_resume_reg->dremap2;
++	*(volatile unsigned int *)0xb3012010 = ddrc_resume_reg->dremap3;
++	*(volatile unsigned int *)0xb3012014 = ddrc_resume_reg->dremap4;
++	*(volatile unsigned int *)0xb3012018 = ddrc_resume_reg->dremap5;
++
++	*(volatile unsigned int *)0xb3012000 &= ~0x3;
++	*(volatile unsigned int *)0xb3012000 |= ddrc_resume_reg->dwcfg & 0x3;
++}
++
++static void ddr_init(void)
++{
++	struct ddrc_resume_reg *ddrc_resume_reg;
++	struct ddr_phy_resume_reg *ddr_phy_resume_reg;
++
++	store_regs = (struct store_regs *)RTC_RAM_DATA_ADDR;
++	ddrc_resume_reg = &store_regs->ddrc_resume_reg;
++	ddr_phy_resume_reg = &store_regs->ddr_phy_resume_reg;
++
++
++//	*(volatile unsigned int *)0xb34f0010 = (0x1 << 20);	//phy reset
++	phy_cfg(ddr_phy_resume_reg);
++//	*(volatile unsigned int *)0xb34f0010 &= ~(0x1 << 20);
++
++	phy_pll_init(ddr_phy_resume_reg);
++	dfi_init(ddrc_resume_reg);
++	ddrc_init(ddrc_resume_reg);
++}
++
++#define DDR_PHY_OFFSET  (-0x4e0000 + 0x1000)
++#define DDRP_INNOPHY_RXDLL_DELAY_AL             (DDR_PHY_OFFSET + (0x48 << 2))
++#define DDRP_INNOPHY_RXDLL_DELAY_AH             (DDR_PHY_OFFSET + (0x58 << 2))
++
++#define REG32(addr) *(volatile unsigned int *)(addr)
++#define ddr_writel(value, reg)  (REG32(DDRC_BASE + reg) = (value))
++#define ddr_readl(reg)          REG32(DDRC_BASE + reg)
++
++static void ddrp_auto_calibration(void)
++{
++	unsigned int reg_val = ddr_readl(DDRP_INNOPHY_TRAINING_CTRL);
++	unsigned int timeout = 0xffffff;
++	unsigned int wait_cal_done = DDRP_CALIB_DONE_HDQCFA | DDRP_CALIB_DONE_LDQCFA;
++
++	reg_val &= ~(DDRP_TRAINING_CTRL_DSCSE_BP);
++	reg_val |= DDRP_TRAINING_CTRL_DSACE_START;
++	ddr_writel(reg_val, DDRP_INNOPHY_TRAINING_CTRL);
++
++	while(!((ddr_readl(DDRP_INNOPHY_CALIB_DONE) & wait_cal_done) == wait_cal_done) && --timeout) {
++		DEBUG("t");
++	}
++
++	if(!timeout) {
++		DEBUG("f");
++	}
++	ddr_writel(0, DDRP_INNOPHY_TRAINING_CTRL);
++
++}
++
++
++
++
++
++static unsigned int get_resume_pc(void)
++{
++	unsigned int resume_pc;
++
++	store_regs = (struct store_regs *)RTC_RAM_DATA_ADDR;
++	resume_pc = store_regs->resume_pc;
++
++	return resume_pc;
++}
++
++
++static void rtc_write_reg(unsigned int reg, unsigned int val)
++{
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++	*(volatile unsigned int *)0xb000303c = 0xa55a;
++	while (!((*(volatile unsigned int *)0xb000303c >> 31) & 0x1) );
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++
++	*(volatile unsigned int *)reg = val;
++
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++}
++
++static unsigned int  rtc_read_reg(unsigned int reg)
++{
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++
++	return *(volatile unsigned int *)reg;
++}
++
++void fastboot_restore_code_2(void)
++{
++	unsigned int resume_pc;
++
++#ifdef FASTBOOT_DEBUG
++	serial_init(2);
++#endif
++
++	resume_pc = get_resume_pc();
++	DEBUG_HEX(resume_pc);
++
++	DEBUG("fastboot begin restore\n");
++
++	pll_restore();
++	DEBUG("pll restore ok\n");
++
++	ddr_init();
++
++	{
++		unsigned int ddrc_ctrl = *(volatile unsigned int *)0xb34f0010;
++		volatile unsigned int tmp;
++
++		/* bufferen_core = 1 */
++		tmp = rtc_read_reg(0xb0003048);
++		tmp |= (1 << 21);
++		rtc_write_reg(0xb0003048, tmp);
++
++		/* exit ddr self refresh */
++		ddrc_ctrl &= ~(1<<5);
++		ddrc_ctrl |= 1 << 1;
++		*(volatile unsigned int*)0xb34f0010 = ddrc_ctrl;
++
++		while((*(volatile unsigned int *)0xb34f0000) & (1<<2));
++	}
++
++
++	ddr_writel(1, DDRC_AUTOSR_EN);
++	while(ddr_readl(DDRC_STATUS) & (1<<2));
++
++	DEBUG("ddr restore finish\n");
++
++	ddrp_auto_calibration();
++
++	__asm__ volatile(
++			".set push      \n\t"
++			".set mips32r2  \n\t"
++			"sync       \n\t"
++			"jr.hb %0       \n\t"
++			"nop            \n\t"
++			".set pop       \n\t"
++			:
++			: "r" (resume_pc)
++			:
++			);
++
++}
++
++
++__attribute__((section(".resume"))) void fastboot_restore_code_1(void)
++{
++
++	__asm__ volatile(
++			".set push      \n\t"
++			".set noreorder      \n\t"
++			".set mips32r2  \n\t"
++			"move $29, %0   \n\t"
++			"jr.hb   %1     \n\t"
++			"nop            \n\t"
++			".set reorder      \n\t"
++			".set pop       \n\t"
++			:
++			:"r" (RTC_RAM_SP_ADDR), "r"(fastboot_restore_code_2)
++			:
++			);
++
++}
++
++
+diff --git a/arch/mips/xburst2/soc-x2000/sleep_firmware/src/uart.c b/arch/mips/xburst2/soc-x2000/sleep_firmware/src/uart.c
+new file mode 100644
+index 000000000..abb6a82ac
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/sleep_firmware/src/uart.c
+@@ -0,0 +1,97 @@
++#include <uart.h>
++#include <cpm.h>
++#include <gpio.h>
++
++static void serial_putc (int num, const char c)
++{
++	if (c == '\n')
++		serial_putc (num, '\r');
++
++	/* Wait for fifo to shift out some bytes */
++	while ( !((uart_readl(OFF_LSR(num)) & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60) );
++
++	uart_writel((unsigned char)c, OFF_TDR(num));
++}
++
++static void serial_setbrg(int num)
++{
++	unsigned int baud_div, tmp;
++
++	uart_writel(16, OFF_UMR(num));
++	uart_writel(0, OFF_UACR(num));
++	baud_div = 13;
++
++	tmp = uart_readl(OFF_LCR(num));
++	tmp |= UARTLCR_DLAB;
++	uart_writel(tmp, OFF_LCR(num));
++
++	uart_writel((baud_div >> 8) & 0xff, OFF_DLHR(num));
++	uart_writel(baud_div & 0xff, OFF_DLLR(num));
++
++	tmp &= ~UARTLCR_DLAB;
++	uart_writel(tmp, OFF_LCR(num));
++}
++
++void serial_init(int num)
++{
++	switch(num){
++		case 0:
++			__gpio_as_uart0();
++			__cpm_start_uart0();
++			break;
++		case 2:
++			__gpio_as_uart2();
++			__cpm_start_uart2();
++			break;
++		case 1:
++		default:
++			__gpio_as_uart1();
++			__cpm_start_uart1();
++			break;
++	}
++
++	uart_writel(0, OFF_SPR(num));
++	uart_writel(0, OFF_MCR(num));
++
++	/* Disable port interrupts while changing hardware */
++	uart_writel(0, OFF_IER(num));
++
++	/* Disable UART unit function */
++	uart_writel(~UARTFCR_UUE, OFF_FCR(num));
++
++	/* Set both receiver and transmitter in UART mode (not SIR) */
++	uart_writel(~(SIRCR_RSIRE | SIRCR_TSIRE), OFF_SIRCR(num));
++
++	/* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
++	uart_writel(UARTLCR_WLEN_8 & ~(UARTLCR_STOP2), OFF_LCR(num));
++
++	serial_setbrg(num);
++
++	/* Enable UART unit, enable and clear FIFO */
++	uart_writel(UARTFCR_UUE | UARTFCR_TFLS | UARTFCR_RFLS | UARTFCR_FE, OFF_FCR(num));
++
++}
++
++void serial_puts (int num,  const char *s)
++{
++	while (*s) {
++		serial_putc (num, *s++);
++	}
++}
++
++void serial_put_hex(int num, unsigned int  d)
++{
++	char c[12];
++	unsigned char i;
++	for(i = 0; i < 8; i++)
++	{
++		c[i] = (d >> ((7 - i) * 4)) & 0xf;
++		if(c[i] < 10)
++			c[i] += 0x30;
++		else
++			c[i] += (0x41 - 10);
++	}
++	c[8] = '\n';
++	c[9] = 0;
++	serial_puts(num, c);
++}
+diff --git a/arch/mips/xburst2/soc-x2000/sleep_firmware/target.ld b/arch/mips/xburst2/soc-x2000/sleep_firmware/target.ld
+new file mode 100644
+index 000000000..44f03a97a
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/sleep_firmware/target.ld
+@@ -0,0 +1,37 @@
++OUTPUT_ARCH(mips)
++MEMORY{
++	/* TOTAL MEM :4KBytes */
++	ram   : ORIGIN = 0xb0004000 , LENGTH = 2784
++}
++
++ENTRY(fastboot_restore_code_1)
++SECTIONS
++{
++	.text : {
++		*(.resume)
++		*(.text)
++	} > ram
++
++	.data : {
++		*(.data)
++	        *(.rodata)
++	} > ram /**(.data)*/
++	.bss : {
++		. = ALIGN(4);
++			__bss_start = .;
++			*(.sbss.*)
++			*(.bss.*)
++			*(COMMON)
++		. = ALIGN(4);
++			__bss_end = .;
++	} > ram
++
++
++	/DISCARD/ : {
++		*(COMMON)
++		*(.pdri)
++		*(.comment)
++		*(.gnu.attributes)
++		*(.reginfo)
++	}
++}
+diff --git a/arch/mips/xburst2/soc-x2000/sleep_firmware/tmp.map b/arch/mips/xburst2/soc-x2000/sleep_firmware/tmp.map
+new file mode 100644
+index 000000000..9b5f0312d
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2000/sleep_firmware/tmp.map
+@@ -0,0 +1,75 @@
++
++Discarded input sections
++
++ .reginfo       0x0000000000000000       0x18 ./src/fastboot_resume.o
++ .comment       0x0000000000000000       0x2f ./src/fastboot_resume.o
++ .gnu.attributes
++                0x0000000000000000       0x10 ./src/fastboot_resume.o
++ .reginfo       0x0000000000000000       0x18 ./src/uart.o
++ .MIPS.abiflags
++                0x0000000000000000       0x18 ./src/uart.o
++ .comment       0x0000000000000000       0x2f ./src/uart.o
++ .gnu.attributes
++                0x0000000000000000       0x10 ./src/uart.o
++
++Memory Configuration
++
++Name             Origin             Length             Attributes
++ram              0x00000000b0004000 0x0000000000000ae0
++*default*        0x0000000000000000 0xffffffffffffffff
++
++Linker script and memory map
++
++
++.text           0x00000000b0004000      0x690
++ *(.resume)
++ .resume        0x00000000b0004000       0x24 ./src/fastboot_resume.o
++                0x00000000b0004000                fastboot_restore_code_1
++ *(.text)
++ *fill*         0x00000000b0004024        0xc 
++ .text          0x00000000b0004030      0x400 ./src/fastboot_resume.o
++                0x00000000b0004030                sys_clk_restore
++                0x00000000b00040c0                fastboot_restore_code_2
++ .text          0x00000000b0004430      0x260 ./src/uart.o
++                0x00000000b000449c                serial_init
++                0x00000000b00045e4                serial_puts
++                0x00000000b000461c                serial_put_hex
++
++.MIPS.abiflags  0x00000000b0004690       0x18
++ .MIPS.abiflags
++                0x00000000b0004690       0x18 ./src/fastboot_resume.o
++
++.data           0x00000000b00046b0        0x0
++ *(.data)
++ .data          0x00000000b00046b0        0x0 ./src/fastboot_resume.o
++ .data          0x00000000b00046b0        0x0 ./src/uart.o
++ *(.rodata)
++
++.bss            0x00000000b00046b0        0x0
++                0x00000000b00046b0                . = ALIGN (0x4)
++                0x00000000b00046b0                __bss_start = .
++ *(.sbss.*)
++ *(.bss.*)
++ *(COMMON)
++                0x00000000b00046b0                . = ALIGN (0x4)
++                0x00000000b00046b0                __bss_end = .
++ .bss           0x00000000b00046b0        0x0 ./src/fastboot_resume.o
++ .bss           0x00000000b00046b0        0x0 ./src/uart.o
++
++/DISCARD/
++ *(COMMON)
++ *(.pdri)
++ *(.comment)
++ *(.gnu.attributes)
++ *(.reginfo)
++LOAD ./src/fastboot_resume.o
++LOAD ./src/uart.o
++OUTPUT(./tmp.elf elf32-tradlittlemips)
++
++.pdr            0x0000000000000000       0xe0
++ .pdr           0x0000000000000000       0x60 ./src/fastboot_resume.o
++ .pdr           0x0000000000000060       0x80 ./src/uart.o
++
++.mdebug.abi32   0x0000000000000000        0x0
++ .mdebug.abi32  0x0000000000000000        0x0 ./src/fastboot_resume.o
++ .mdebug.abi32  0x0000000000000000        0x0 ./src/uart.o
+diff --git a/arch/mips/xburst2/soc-x2500/Kconfig.DT b/arch/mips/xburst2/soc-x2500/Kconfig.DT
+new file mode 100644
+index 000000000..8324a4809
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/Kconfig.DT
+@@ -0,0 +1,15 @@
++choice
++	prompt "device tree select for X2500 boards"
++	default DT_HIPPO_V10
++	depends on SOC_X2500
++
++config DT_GANDER_V10
++	bool "x2500 gander_v10"
++config DT_DARWIN_V14
++	bool "x2500 darwin_v14"
++config DT_HIPPO_V10
++	bool "x2500 hippo_v10"
++config DT_HIPPO_V12
++	bool "x2500 hippo_v12"
++
++endchoice
+diff --git a/arch/mips/xburst2/soc-x2500/Makefile b/arch/mips/xburst2/soc-x2500/Makefile
+new file mode 100644
+index 000000000..ce532920c
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/Makefile
+@@ -0,0 +1,8 @@
++obj-y += setup.o
++obj-y += serial.o
++
++obj-y += pm.o
++obj-y += regs_save_restore.o
++obj-y += libdmmu.o
++obj-y += gpio.o
++obj-y += reset.o
+diff --git a/arch/mips/xburst2/soc-x2500/gpio.c b/arch/mips/xburst2/soc-x2500/gpio.c
+new file mode 100644
+index 000000000..606920fda
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/gpio.c
+@@ -0,0 +1,123 @@
++#include <linux/kernel.h>
++#include <linux/printk.h>
++#include <linux/io.h>
++#include <soc/base.h>
++#include <soc/gpio.h>
++
++#define GPIO_PORT_OFF    0x1000
++#define GPIO_SHADOW_OFF  0x7000
++
++#define PXPIN      0x00   /* PIN Level Register */
++#define PXINT      0x10   /* Port Interrupt Register */
++#define PXINTS     0x14   /* Port Interrupt Set Register */
++#define PXINTC     0x18   /* Port Interrupt Clear Register */
++#define PXMSK      0x20   /* Port Interrupt Mask Reg */
++#define PXMSKS     0x24   /* Port Interrupt Mask Set Reg */
++#define PXMSKC     0x28   /* Port Interrupt Mask Clear Reg */
++#define PXPAT1     0x30   /* Port Pattern 1 Set Reg. */
++#define PXPAT1S    0x34   /* Port Pattern 1 Set Reg. */
++#define PXPAT1C    0x38   /* Port Pattern 1 Clear Reg. */
++#define PXPAT0     0x40   /* Port Pattern 0 Register */
++#define PXPAT0S    0x44   /* Port Pattern 0 Set Register */
++#define PXPAT0C    0x48   /* Port Pattern 0 Clear Register */
++#define PXFLG      0x50   /* Port Flag Register */
++#define PXFLGC     0x58   /* Port Flag clear Register */
++#define PXPU       0x110   /* Port PULL-UP State Register */
++#define PXPUS      0x114   /* Port PULL-UP State Set Register */
++#define PXPUC      0x118   /* Port PULL-UP State Clear Register */
++#define PXPD       0x120   /* Port PULL-DOWN State Register */
++#define PXPDS      0x124   /* Port PULL-DOWN State Set Register */
++#define PXPDC      0x128   /* Port PULL-DOWN State Clear Register */
++
++#define PZGID2LD   0xF0   /* GPIOZ Group ID to load */
++
++#define SHADOW 5
++
++static const unsigned long gpiobase[] = {
++    [0] = (unsigned long)CKSEG1ADDR(GPIO_IOBASE + 0 * GPIO_PORT_OFF),
++    [1] = (unsigned long)CKSEG1ADDR(GPIO_IOBASE + 1 * GPIO_PORT_OFF),
++    [2] = (unsigned long)CKSEG1ADDR(GPIO_IOBASE + 2 * GPIO_PORT_OFF),
++    [3] = (unsigned long)CKSEG1ADDR(GPIO_IOBASE + 3 * GPIO_PORT_OFF),
++    [4] = (unsigned long)CKSEG1ADDR(GPIO_IOBASE + 4 * GPIO_PORT_OFF),
++
++    [SHADOW] = (unsigned long)CKSEG1ADDR(GPIO_IOBASE + GPIO_SHADOW_OFF),
++};
++
++#define GPIO_ADDR(port, reg) ((volatile unsigned long *)(gpiobase[port] + reg))
++
++static inline void gpio_write(int port, unsigned int reg, int val)
++{
++    *GPIO_ADDR(port, reg) = val;
++}
++
++static inline unsigned int gpio_read(int port, unsigned int reg)
++{
++    return *GPIO_ADDR(port, reg);
++}
++
++static void hal_gpio_port_set_func(int port, unsigned int pins, enum gpio_function func)
++{
++    /* func option */
++    if (func & 0x10) {
++        if (func & 0x8)
++            gpio_write(SHADOW, PXINTS, pins);
++        else
++            gpio_write(SHADOW, PXINTC, pins);
++
++        if (func & 0x4)
++            gpio_write(SHADOW, PXMSKS, pins);
++        else
++            gpio_write(SHADOW, PXMSKC, pins);
++
++        if (func & 0x2)
++            gpio_write(SHADOW, PXPAT1S, pins);
++        else
++            gpio_write(SHADOW, PXPAT1C, pins);
++
++        if (func & 0x1)
++            gpio_write(SHADOW, PXPAT0S, pins);
++        else
++            gpio_write(SHADOW, PXPAT0C, pins);
++
++        /* configure PzGID2LD to specify which port group to load */
++        gpio_write(SHADOW, PZGID2LD, port);
++    }
++
++    if (func & 0x80) {
++        int pull = (func >> 5) & 0x3;
++        if (pull == 0) { // no pull
++            gpio_write(port, PXPUC, pins);
++            gpio_write(port, PXPDC, pins);
++        }
++        if (pull == 1) { // pull up
++            gpio_write(port, PXPDC, pins);
++            gpio_write(port, PXPUS, pins);
++        }
++        if (pull == 2) { // pull down
++            gpio_write(port, PXPUC, pins);
++            gpio_write(port, PXPDS, pins);
++        }
++    }
++}
++
++unsigned long ingenic_pinctrl_lock(int port);
++void ingenic_pinctrl_unlock(int port, unsigned long flags);
++
++int jzgpio_set_func(int port, enum gpio_function func, unsigned long pins)
++{
++    unsigned long flags;
++
++    if (port < 0 || port > 4) {
++        printk(KERN_ERR "gpio: invalid gpio port for x2000: %d\n", port);
++        return -EINVAL;
++    }
++
++    flags = ingenic_pinctrl_lock(port);
++
++    hal_gpio_port_set_func(port, pins, func);
++
++    ingenic_pinctrl_unlock(port, flags);
++
++    return 0;
++}
++EXPORT_SYMBOL(jzgpio_set_func);
+diff --git a/arch/mips/xburst2/soc-x2500/include/cpu-feature-overrides.h b/arch/mips/xburst2/soc-x2500/include/cpu-feature-overrides.h
+new file mode 100644
+index 000000000..a0d0c1ff3
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/include/cpu-feature-overrides.h
+@@ -0,0 +1,67 @@
++/*
++ *  Copyright (C) 2008 Ingenic Semiconductor Inc.
++ *
++ *  Author: <zpzhong@ingenic.cn>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_INGENIC_CPU_FEATURE_OVERRIDES_H__
++#define __ASM_MACH_INGENIC_CPU_FEATURE_OVERRIDES_H__
++
++
++#define cpu_dcache_size()       	(32 * 1024)
++#define cpu_dcache_ways()       	8
++#define cpu_dcache_line_size()  	32
++#define cpu_icache_size()       	(32 * 1024)
++#define cpu_icache_ways()       	8
++#define cpu_icache_line_size()  	32
++#define cpu_has_xpa			0
++#define cpu_has_tlb                     1
++#define cpu_has_tlbinv                  1
++#define cpu_has_4kex                    1
++#define cpu_has_3k_cache                0
++#define cpu_has_4k_cache                1
++#define cpu_has_tx39_cache              0
++#define cpu_has_fpu                     1
++#define cpu_has_32fpr                   0
++#define cpu_has_counter                 0
++#define cpu_has_watch                   1
++#define cpu_has_divec                   1
++#define cpu_has_vce                     0
++#define cpu_has_cache_cdex_p            0
++#define cpu_has_cache_cdex_s            0
++#define cpu_has_prefetch                1
++#define cpu_has_mcheck                  1
++#define cpu_has_ejtag                   0
++#define cpu_has_llsc                    1
++#define kernel_uses_llsc		cpu_has_llsc
++#define cpu_has_mips16                  0
++#define cpu_has_mdmx                    0
++#define cpu_has_mips3d                  0
++#define cpu_has_smartmips               0
++#define cpu_has_vtag_icache             0
++#define cpu_has_dc_aliases              0
++#define cpu_has_ic_fills_f_dc           0
++#define cpu_has_pindexed_dcache         0
++#define cpu_icache_snoops_remote_store  0
++#define cpu_has_mips32r1                0
++#define cpu_has_mips32r2                1
++#define cpu_has_mips64r1                0
++#define cpu_has_mips64r2                0
++#define cpu_has_dsp                     0
++#define cpu_has_mipsmt                  0
++#define cpu_has_userlocal               1
++#define cpu_has_rixi                    1
++#define cpu_has_nofpuex                 0
++#define cpu_has_64bits                  0
++#define cpu_has_64bit_zero_reg          0
++#define cpu_has_vint                    0
++#define cpu_has_veic                    0
++#define cpu_has_inclusive_pcaches       0
++#define kernel_uses_smartmips_rixi      0
++#define cpu_has_mxu                     0
++#define cpu_has_mxuv3                   1
++#endif
+diff --git a/arch/mips/xburst2/soc-x2500/include/irq.h b/arch/mips/xburst2/soc-x2500/include/irq.h
+new file mode 100644
+index 000000000..11cef19d6
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/include/irq.h
+@@ -0,0 +1,40 @@
++/*
++ *  Copyright (C) 2010 Ingenic Semiconductor Inc.
++ *
++ *  Author: <zpzhong@ingenic.cn>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_INGENIC_IRQ_H__
++#define __ASM_MACH_INGENIC_IRQ_H__
++#include <irq_cpu.h>
++#include <dt-bindings/interrupt-controller/mips-irq.h>
++
++enum {
++#define GPIO_NR_IRQS	(32 * 5 + 16)
++	IRQ_GPIO_BASE = (IRQ_INTC_END + 1),
++	IRQ_GPIO_END = IRQ_GPIO_BASE + GPIO_NR_IRQS - 1,
++
++#define TCU_NR_IRQS	(8)
++	IRQ_TCU_BASE,
++	IRQ_TCU_END = IRQ_TCU_BASE + TCU_NR_IRQS - 1,
++
++#define MCU_NR_IRQS    (5)
++	IRQ_MCU_BASE,
++	IRQ_MCU_END = IRQ_MCU_BASE + MCU_NR_IRQS - 1,
++
++#define SADC_NR_IRQS	(8)
++	IRQ_SADC_BASE,
++	IRQ_SADC_END = IRQ_SADC_BASE + SADC_NR_IRQS - 1,
++
++#define RESERVED_NR_IRQS       (150)
++	IRQ_RESERVED_BASE,
++	IRQ_RESERVED_END = IRQ_RESERVED_BASE + RESERVED_NR_IRQS - 1,
++
++	NR_IRQS,
++};
++
++#endif
+diff --git a/arch/mips/xburst2/soc-x2500/include/libdmmu.h b/arch/mips/xburst2/soc-x2500/include/libdmmu.h
+new file mode 100644
+index 000000000..6e0fbdb42
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/include/libdmmu.h
+@@ -0,0 +1,30 @@
++#ifndef _LIBDMMU_
++#define _LIBDMMU_
++
++#include <linux/device.h>
++
++
++struct dmmu_mm_ops {
++	int (*mm_release)(void *data);
++};
++
++struct dmmu_mm_notifier {
++
++	struct device *dev;
++	void *data;
++	struct list_head list;
++
++	struct dmmu_mm_ops *ops;
++};
++
++int dmmu_register_mm_notifier(struct dmmu_mm_notifier *dmn);
++
++unsigned long dmmu_map(struct device *dev,unsigned long vaddr,unsigned long len);
++int dmmu_flush_cache(unsigned long vaddr, unsigned long len);
++int dmmu_unmap(struct device *dev,unsigned long vaddr, int len);
++int dmmu_unmap_all(struct device *dev);
++void dmmu_dump_vaddr(unsigned long vaddr);
++int dmmu_memory_smash(unsigned long vaddr, int smash_mode);
++int dmmu_dump_map(unsigned long vaddr);
++
++#endif
+diff --git a/arch/mips/xburst2/soc-x2500/include/soc/base.h b/arch/mips/xburst2/soc-x2500/include/soc/base.h
+new file mode 100644
+index 000000000..7e60f3f09
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/include/soc/base.h
+@@ -0,0 +1,97 @@
++
++#ifndef __JZSOC_SOC_DEV_H__
++#define __JZSOC_SOC_DEV_H__
++
++/*
++ * Define the module base addresses
++ */
++
++/* AHB0 BUS Devices Base */
++#define HARB0_IOBASE	        0x13000000
++#define DDRC_BASE	            0xb34f0000
++#define DDRC1_IOBASE	        0x13010000 /*DDR_APB_BASE*/
++#define DDRC_IOBASE	            0x134f0000 /*TODO:*/
++#define DDRPHY_IOBASE	        0x13011000 /*TODO:*/
++#define AXI_ARB1_IOBASE	        0x13013000 /*TODO:*/
++#define AXI_ARB2_IOBASE	        0x13014000 /*TODO:*/
++#define LCDC_IOBASE	            0x13050000
++#define MSC0_IOBASE	            0x13060000
++#define MSC1_IOBASE	            0x13070000
++#define IPU_IOBASE	            0x13080000
++#define BSCALER_IOBASE	        0x13090000
++#define MONITOR_IOBASE	        0x130a0000
++#define I2D_IOBASE	            0x130b0000
++#define VO_IOBASE	            0x130c0000
++#define DRAW_BOX_IOBASE	        0x130d0000
++#define ISP_IOBASE	            0x13300000
++#define LZMA_IOBASE				0x13090000
++
++/* AHB1 BUS Devices Base */
++#define RTC_IOBASE	            0x132a0000
++#define EL150_IOBASE            0x13200000
++#define RADIX_IOBASE            0x13100000
++#define RADIX_IOBASE_UNIT(ID)	(RADIX_IOBASE + 0x400000 * ID)
++#define AVPU_IOBASE             0x13200000
++#define AVPU_IOBASE_UNIT(ID)	(AVPU_IOBASE + 0x400000 * ID)
++
++/* AHB2 BUS Devices Base */
++#define HARB2_IOBASE	        0x13400000
++#define NEMC_IOBASE	            0x13410000
++#define PDMA_IOBASE	            0x13420000
++#define AES_IOBASE  	        0x13430000
++#define SFC_IOBASE	            0x13440000
++#define HASH_IOBASE	            0x13480000
++#define GMAC_IOBASE	            0x134b0000
++#define RSA_IOBASE	            0x134c0000
++#define OTG_IOBASE	            0x13500000
++#define EFUSE_IOBASE	        0x13540000
++#define INTC_IOBASE	            0x10001000
++
++/* CPU and OST */
++#define G_OST_IOBASE	        0x12000000 /* G_OST_BASE */
++#define N_OST_IOBASE            0x12100000 /* N_OST_BASE */
++#define CCU_IOBASE	            0x12200000
++#define INTCN_IOBASE	        0x12300000
++#define SRAM_IOBASE	            0x12400000
++#define NNDMA_IOBASE	        0x12500000
++#define LEPOST_IOBASE	        0x12600000  /* RISC-V OST */
++#define LEPCCU_IOBASE	        0x12700000  /* RISC-V CCU */
++
++/* APB BUS Devices Base */
++#define CPM_IOBASE	            0x10000000
++#define TCU_IOBASE	            0x10002000
++#define MIPI_DSI_TX_IOBASE	    0x10003000
++#define MIPI_DSI_PHY_IOBASE	    0x10004000
++#define GPIO_IOBASE	            0x10010000
++#define AIC0_IOBASE	            0x10020000
++#define CODEC_IOBASE	        0x10021000
++#define MIPI_PHY_IOBASE         0x10022000
++#define MIPI_CSI_IOBASE	        0x10023000
++#define UART0_IOBASE	        0x10030000
++#define UART1_IOBASE	        0x10031000
++#define UART2_IOBASE	        0x10032000
++#define UART3_IOBASE	        0x10033000
++#define DMIC_IOBASE 	        0x10034000
++#define SSISLV_IOBASE	        0x10040000
++#define SSI0_IOBASE	            0x10043000
++#define SSI1_IOBASE 	        0x10044000
++#define I2C0_IOBASE	            0x10050000
++#define I2C1_IOBASE	            0x10051000
++#define I2C2_IOBASE 	        0x10052000
++#define I2C3_IOBASE 	        0x10053000
++#define MIPI_RX_4L_IOBASE 	    0x10054000
++#define USB_IOBASE 	            0x10060000
++#define DES_IOBASE  	        0x10061000
++#define SADC_IOBASE	            0x10070000
++#define DTRNG_IOBASE            0x10072000
++#define WDT_IOBASE	            0x10002000
++
++/* NAND CHIP Base Address*/
++#define NEMC_CS1_IOBASE         0X1b000000
++#define NEMC_CS2_IOBASE         0X1a000000
++#define NEMC_CS3_IOBASE         0X19000000
++#define NEMC_CS4_IOBASE         0X18000000
++#define NEMC_CS5_IOBASE         0X17000000
++#define NEMC_CS6_IOBASE         0X16000000
++
++#endif
+diff --git a/arch/mips/xburst2/soc-x2500/include/soc/cache.h b/arch/mips/xburst2/soc-x2500/include/soc/cache.h
+new file mode 100644
+index 000000000..249e4230a
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/include/soc/cache.h
+@@ -0,0 +1,73 @@
++#ifndef __CHIP_CACHE_H__
++#define __CHIP_CACHE_H__
++#include <asm/cacheops.h>
++#include <asm/r4kcache.h>
++
++#define Index_Prefetch_I        0x1c
++
++
++#define cache_prefetch(label,size)					\
++do{									\
++	unsigned long addr,end;						\
++	/* Prefetch codes from label */					\
++	addr = (unsigned long)(&&label) & ~(32 - 1);			\
++	end = (unsigned long)(&&label + size) & ~(32 - 1);		\
++	end += 32;							\
++	for (; addr < end; addr += 32) {				\
++		__asm__ volatile (					\
++				".set push       \n\t"			\
++				".set mips32     \n\t"			\
++				" cache %0, 0(%1)\n\t"			\
++				".set pop        \n\t"			\
++				:					\
++				: "I" (Index_Prefetch_I), "r"(addr));	\
++	}								\
++}									\
++while(0)
++
++#define K0BASE			KSEG0
++#define CFG_DCACHE_SIZE		32768
++#define CFG_ICACHE_SIZE		32768
++#define CFG_CACHELINE_SIZE	32
++
++#define CFG_SDCACHE_SIZE	(512*1024)
++#define CFG_SDCACHELINE_SIZE	64
++
++static inline void __jz_flush_cache_all(void)
++{
++	register unsigned long addr;
++	/* Clear CP0 TagLo */
++	for (addr = K0BASE; addr < (K0BASE + CFG_DCACHE_SIZE); addr += CFG_CACHELINE_SIZE) {
++		asm volatile (".set mips32\n\t"
++					  " cache %0, 0(%1)\n\t"
++					  ".set mips32\n\t"
++					  :
++					  : "I" (Index_Writeback_Inv_D), "r"(addr));
++	}
++
++	for (addr = K0BASE; addr < (K0BASE + CFG_ICACHE_SIZE); addr += CFG_CACHELINE_SIZE) {
++		asm volatile (".set mips32\n\t"
++					  " cache %0, 0(%1)\n\t"
++					  ".set mips32\n\t"
++					  :
++					  : "I" (Index_Invalidate_I), "r"(addr));
++	}
++
++	asm volatile ("sync\n\t"
++				  "lw $0,0(%0)"
++				  ::"r" (0xa0000000));
++	/* 2nd cache */
++	for (addr = K0BASE; addr < (K0BASE + CFG_SDCACHE_SIZE); addr += CFG_SDCACHELINE_SIZE) {
++		asm volatile (".set mips32\n\t"
++					  " cache %0, 0(%1)\n\t"
++					  ".set mips32\n\t"
++					  :
++					  : "I" (Index_Writeback_Inv_SD), "r"(addr));
++	}
++
++	asm volatile ("sync\n\t"
++				  "lw $0,0(%0)"
++				  ::"r" (0xa0000000));
++}
++
++#endif /* __CHIP_CACHE_H__ */
+diff --git a/arch/mips/xburst2/soc-x2500/include/soc/cpm.h b/arch/mips/xburst2/soc-x2500/include/soc/cpm.h
+new file mode 100644
+index 000000000..21e2a56fd
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/include/soc/cpm.h
+@@ -0,0 +1,143 @@
++/*
++ * JZSOC CPM register definition.
++ *
++ * CPM (Clock reset and Power control Management)
++ *
++ * Copyright (C) 2019 Ingenic Semiconductor Co., Ltd.
++ */
++
++#ifndef __CPM_H__
++#define __CPM_H__
++#include <soc/base.h>
++
++#define CPM_CPCCR		(0x00)
++#define CPM_CPPCR		(0x0c)
++#define CPM_CPAPCR		(0x10)
++#define CPM_CPMPCR		(0x14)
++#define CPM_CPAPACR		(0x18)
++#define CPM_CPMPACR		(0x1c)
++#define CPM_DDRCDR		(0x2c)
++#define CPM_EL150CDR	(0x30)
++#define CPM_CPPSR		(0x34)
++#define CPM_CPSPPR		(0x38)
++#define CPM_USBPCR		(0x3c)
++#define CPM_USBRDT		(0x40)
++#define CPM_USBVBFIL	(0x44)
++#define CPM_USBPCR1		(0x48)
++#define CPM_RSACDR		(0x4c)
++#define CPM_MACCDR		(0x54)
++#define CPM_CPEPCR		(0x58)
++#define CPM_CPEPACR		(0x5c)
++#define CPM_SFCCDR		(0x60)
++#define CPM_LPCDR		(0x64)
++#define CPM_MSC0CDR		(0x68)
++#define CPM_MSC1CDR		(0x6c)
++#define CPM_I2STCDR 	(0x70)
++#define CPM_I2STCDR1	(0x78)
++#define CPM_SSICDR		(0x74)
++#define CPM_ISPCDR		(0x80)
++#define CPM_I2SRCDR 	(0x84)
++#define CPM_I2SRCDR1	(0x88)
++#define CPM_BSCALERCDR  (0xa0)
++#define CPM_EXCLKDS		(0x8c)
++#define CPM_CIM0CDR		(0x90)
++#define CPM_CIM1CDR		(0x94)
++#define CPM_CIM2CDR		(0x98)
++#define CPM_SOFTAPP		(0x9c)
++#define CPM_BSCALERCDR	(0xa0)
++#define CPM_RADIXCDR	(0xa4)
++#define CPM_INTR		(0xb0)
++#define CPM_INTRE		(0xb4)
++#define CPM_BT0CDR		(0xb8)
++#define CPM_DRCG		(0xd0)
++#define CPM_CPCSR		(0xd4)
++#define CPM_CPVPCR		(0xe0)
++#define CPM_CPVPACR		(0xe4)
++#define CPM_MACPHY		(0xe8)
++
++
++#define CPM_LCR			(0x04)
++#define CPM_CLKGR		(0x20)/* def changed*/
++#define CPM_OPCR		(0x24)
++#define CPM_CLKGR1		(0x28)/* def changed*/
++#define CPM_SRBC		(0xc4)
++#define SRBC_USB_SR BIT (12)
++#define CPM_MESTSEL		(0xec)
++
++#define CPM_MEMCTRL_MA0		(0xf0)
++#define CPM_MEMCTRL_MA1	    (0xf4)
++#define CPM_MEMCTRL_MA2		(0xf8)
++
++#define CPM_RSR		(0x08)
++
++#ifndef BIT
++#define BIT(nr)  (1UL << nr)
++#endif
++
++/*USB Parameter Control Register*/
++#define USBPCR_USB_MODE                 BIT(31)
++#define USBPCR_AVLD_REG                 BIT(30)
++#define USBPCR_IDPULLUP_MASK_BIT        28
++#define USBPCR_IDPULLUP_MASK            (0x3 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_IDPULLUP_OTG             (0x0 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_IDPULLUP_ALWAYS_SUSPEND  (0x1 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_IDPULLUP_ALWAYS          (0x2 << USBPCR_IDPULLUP_MASK_BIT)
++#define USBPCR_INCR_MASK                BIT(27)
++#define USBPCR_POR_BIT                  22
++#define USBPCR_POR                      BIT(USBPCR_POR_BIT)
++
++/*USB Reset Detect Timer Register*/
++#define USBRDT_RESUME_INTEEN            BIT(31) /*RW*/
++#define USBRDT_RESUME_INTERCLR          BIT(30) /*W0*/
++#define USBRDT_RESUME_SPEED_BIT         28  /*RW*/
++#define USBRDT_RESUME_SPEED_MSK         (0x3 << USBRDT_RESUME_SPEED_BIT)
++#define USBRDT_RESUME_SPEED_HIGH        (0x0 << USBRDT_RESUME_SPEED_BIT)
++#define USBRDT_RESUME_SPEED_FULL        (0x1 << USBRDT_RESUME_SPEED_BIT)
++#define USBRDT_RESUME_SPEED_LOW         (0x2 << USBRDT_RESUME_SPEED_BIT)
++#define USBRDT_RESUME_STATUS            BIT(27) /*RO*/
++#define USBRDT_HB_MASK                  BIT(26)
++#define USBRDT_VBFIL_LD_EN              BIT(25)
++#define USBRDT_IDDIG_EN                 BIT(1)
++#define USBRDT_IDDIG_REG                BIT(0)
++#define USBRDT_USBRDT_MSK               (0x7fffff)
++#define USBRDT_USBRDT(x)                ((x) & USBRDT_USBRDT_MSK)
++#define USBRDT_UTMI_RST                 BIT(27)
++
++/*USB VBUS Jitter Filter Register*/
++#define USBVBFIL_USBVBFIL(x)        ((x) & 0xffff)
++#define USBVBFIL_IDDIGFIL(x)        ((x) & (0xffff << 16))
++
++/*USB Parameter Control Register1*/
++#define USBPCR1_BVLD_REG    BIT(31)
++#define USBPCR1_DPPULLDOWN  BIT(29)
++#define USBPCR1_DMPULLDOWN  BIT(28)
++#define USBPCR1_PORT_RST    BIT(21)
++
++/*Oscillator and Power Control Register*/
++#define OPCR_USB_SPENDN     BIT(7)
++#define OPCR_USB_PHY_GATE   BIT(23)
++
++#define LCR_LPM_MASK		(0x3)
++#define LCR_LPM_SLEEP		(0x1)
++
++#define CPM_LCR_PD_X2D		(0x1<<31)
++#define CPM_LCR_PD_VPU		(0x1<<30)
++#define CPM_LCR_PD_MASK		(0x3<<30)
++#define CPM_LCR_X2DS 		(0x1<<27)
++#define CPM_LCR_VPUS		(0x1<<26)
++#define CPM_LCR_STATUS_MASK	(0x3<<26)
++
++#define OPCR_ERCS		(0x1<<2)
++#define OPCR_PD			(0x1<<3) //T31 delete
++#define OPCR_IDLE		(0x1<<31)
++
++#define CLKGR1_VPU              (0x1<<0)
++
++#define cpm_inl(off)		inl(CPM_IOBASE + (off))
++#define cpm_outl(val,off)	outl(val,CPM_IOBASE + (off))
++#define cpm_clear_bit(val,off)	do{cpm_outl((cpm_inl(off) & ~(1 << (val))),off);}while(0)
++#define cpm_set_bit(val,off)	do{cpm_outl((cpm_inl(off) | (1 << (val))),off);}while(0)
++#define cpm_test_bit(val,off)	(cpm_inl(off) & (0x1 << (val)))
++
++#endif
++/* __CPM_H__ */
+diff --git a/arch/mips/xburst2/soc-x2500/include/soc/ddr.h b/arch/mips/xburst2/soc-x2500/include/soc/ddr.h
+new file mode 100644
+index 000000000..4f80e31b6
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/include/soc/ddr.h
+@@ -0,0 +1,293 @@
++/*
++ * JZ4780 ddr definitions
++ *
++ * Copyright (c) 2013 Ingenic Semiconductor Co.,Ltd
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __DDR_H__
++#define __DDR_H__
++
++#include <soc/base.h>
++
++/*
++ * DDR Controller Registers
++ **/
++#define DDR_MEM_PHY_BASE		0x20000000
++
++#define DDRC_AHB2_OFFSET	0xb34f0000
++#define DDRC_APB_OFFSET		0xb3012000
++#define DDR_PHY_OFFSET  (-0x4e0000 + 0x1000)
++
++#define DDRC_STATUS		0x0
++#define DDRC_CFG		0x8
++#define DDRC_CTRL		0x10
++#define DDRC_LMR		0x18
++#define DDRC_DLP		0x20
++#define DDRC_AUTOSR_EN		0x28
++#define DDRC_AUTOSR_CNT		0x30
++#define DDRC_REFCNT		0x38
++#define DDRC_DBGINFO		0xE8
++#define DDRC_TIMING(n)		(0x40 + 8 * (n - 1))
++#define DDRC_MMAP0		0x78
++#define DDRC_MMAP1		0x80
++#define DDRC_HREGPRO		0xd8
++#define DDRC_DWCFG		(DDRC_APB_OFFSET + 0x00)
++#define DDRC_DWSTATUS		(DDRC_APB_OFFSET + 0x04)
++#define DDRC_REMAP(n)		(DDRC_APB_OFFSET + 0x08 + 4 * (n - 1))
++#define DDRC_CGUC0		(DDRC_APB_OFFSET + 0x64)
++#define DDRC_CGUC1		(DDRC_APB_OFFSET + 0x68)
++#define DDRC_PREGPRO		(DDRC_APB_OFFSET + 0x6c)
++
++/*
++ * DDR Innophy registers
++ * */
++#define DDRP_INNOPHY_PHY_RST			(DDR_PHY_OFFSET + 0x000)
++#define DDRP_INNOPHY_MEM_CFG			(DDR_PHY_OFFSET + 0x004)
++#define DDRP_INNOPHY_DQ_WIDTH			(DDR_PHY_OFFSET + 0x07c)
++#define DDRP_INNOPHY_CL				(DDR_PHY_OFFSET + 0x014)
++#define DDRP_INNOPHY_CWL			(DDR_PHY_OFFSET + 0x01c)
++#define DDRP_INNOPHY_AL				(DDR_PHY_OFFSET + 0x018)
++#define DDRP_INNOPHY_PLL_FBDIV			(DDR_PHY_OFFSET + 0x080)
++#define DDRP_INNOPHY_PLL_CTRL			(DDR_PHY_OFFSET + 0x084)
++#define DDRP_INNOPHY_PLL_PDIV			(DDR_PHY_OFFSET + 0x088)
++#define DDRP_INNOPHY_PLL_LOCK			(DDR_PHY_OFFSET + 0xc8)
++#define DDRP_INNOPHY_TRAINING_CTRL		(DDR_PHY_OFFSET + 0x008)
++#define DDRP_INNOPHY_CALIB_DONE			(DDR_PHY_OFFSET + 0x10c)
++#define DDRP_INNOPHY_CALIB_DELAY_AL		(DDR_PHY_OFFSET + 0x190)
++#define DDRP_INNOPHY_CALIB_DELAY_AH		(DDR_PHY_OFFSET + 0x194)
++#define DDRP_INNOPHY_CALIB_BYPASS_AL		(DDR_PHY_OFFSET + 0x118)
++#define DDRP_INNOPHY_CALIB_BYPASS_AH		(DDR_PHY_OFFSET + 0x158)
++#define DDRP_INNOPHY_WL_MODE1			(DDR_PHY_OFFSET + 0x00c)
++#define DDRP_INNOPHY_WL_MODE2			(DDR_PHY_OFFSET + 0x010)
++#define DDRP_INNOPHY_WL_DONE			(DDR_PHY_OFFSET + 0x100)
++#define DDRP_INNOPHY_INIT_COMP			(DDR_PHY_OFFSET + 0x0d0)
++
++
++/*
++ * DDRC REGISTER BITS DEFINE
++ * */
++
++/* DDRC Status Register */
++#define DDRC_DSTATUS_MISS	(1 << 6)
++#define DDRC_ST_DPDN		(1 << 5) /* 0 DDR memory is NOT in deep-power-down state
++										1 DDR memory is in deep-power-down state */
++#define DDRC_ST_PDN		(1 << 4) /* 0 DDR memory is NOT in power-down state
++									1 DDR memory is in power-down state */
++#define DDRC_ST_AREF		(1 << 3) /* 0 DDR memory is NOT in auto-refresh state
++										1 DDR memory is in auto-refresh state */
++#define DDRC_ST_SREF		(1 << 2) /* 0 DDR memory is NOT in self-refresh state
++										1 DDR memory is in self-refresh state */
++#define DDRC_ST_CKE1		(1 << 1) /* 0 CKE1 Pin is low
++										1 CKE1 Pin is high */
++#define DDRC_ST_CKE0		(1 << 0) /* 0 CKE0 Pin is low
++										1 CKE0 Pin is high */
++
++/* DDRC Configure Register */
++#define DDRC_CFG_ROW1_BIT	29 /* Row Address width. */
++#define DDRC_CFG_ROW1_MASK	(0x7 << DDRC_CFG_ROW1_BIT)
++#define DDRC_CFG_COL1_BIT	26 /* Row Address width. */
++#define DDRC_CFG_COL1_MASK	(0x7 << DDRC_CFG_COL1_BIT)
++#define DDRC_CFG_BA1		25 /* Bank Address width of DDR memory */
++#define DDRC_CFG_IMBA		(1 << 16)
++#define DDRC_CFG_ROW0_BIT	13 /* Row Address width. */
++#define DDRC_CFG_ROW0_MASK	(0x7 << DDRC_CFG_ROW0_BIT)
++#define DDRC_CFG_COL0_BIT	10 /* Row Address width. */
++#define DDRC_CFG_COL0_MASK	(0x7 << DDRC_CFG_COL1_BIT)
++#define DDRC_CFG_BA0		9 /* Bank Address width of DDR memory */
++
++#define DDRC_CFG_TYPE_BIT	3
++#define DDRC_CFG_TYPE_MASK	(0x7 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR1	(2 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_MDDR	(3 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR2	(4 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_LPDDR2	(5 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_DDR3	(6 << DDRC_CFG_TYPE_BIT)
++#define DDRC_CFG_TYPE_LPDDR3	(7 << DDRC_CFG_TYPE_BIT)
++
++#define DDRC_CFG_ODTEN		(1 << 2)  /* ODT EN */
++#define DDRC_CFG_CS1EN		(1 << 1)  /* DDR Chip-Select-1 Enable */
++#define DDRC_CFG_CS0EN		(1 << 0)  /* DDR Chip-Select-0 Enable */
++
++/* DDRC Control Register */
++#define DDRC_CTRL_DFI_RST	(1 << 23)
++#define DDRC_CTRL_DLL_RST	(1 << 22)
++#define DDRC_CTRL_CTL_RST	(1 << 21)
++#define DDRC_CTRL_CFG_RST	(1 << 20)
++#define DDRC_CTRL_ACTPD		(1 << 15) /* 0 Precharge all banks before entering power-down
++										 1 Do not precharge banks before entering power-down */
++#define DDRC_CTRL_PDT_BIT	12 /* Power-Down Timer */
++#define DDRC_CTRL_PDT_MASK	(0x7 << DDRC_CTRL_PDT_BIT)
++#define DDRC_CTRL_PDT_DIS	(0 << DDRC_CTRL_PDT_BIT) /* power-down disabled */
++#define DDRC_CTRL_PDT_8		(1 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 8 tCK idle */
++#define DDRC_CTRL_PDT_16	(2 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 16 tCK idle */
++#define DDRC_CTRL_PDT_32	(3 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 32 tCK idle */
++#define DDRC_CTRL_PDT_64	(4 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 64 tCK idle */
++#define DDRC_CTRL_PDT_128	(5 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 128 tCK idle */
++
++#define DDRC_CTRL_PD_CCE	(1 << 7) /* Power down clk freq change enable */
++#define DDRC_CTRL_DPD		(1 << 6) /* 1 Drive external MDDR device entering Deep-Power-Down mode */
++#define DDRC_CTRL_SR		(1 << 5) /* 1 Drive external DDR device entering self-refresh mode
++										0 Drive external DDR device exiting self-refresh mode */
++#define DDRC_CTRL_SR_CCE	(1 << 4) /* Self refresh clk stop request enable */
++#define DDRC_CTRL_CKE		(1 << 1) /* 0 Not set CKE Pin High, 1 Set CKE Pin HIGH */
++#define DDRC_CTRL_RESET		(1 << 0) /* 0 End resetting ddrc_controller, 1 Resetting ddrc_controller */
++
++/* DDRC DFI low power handshake control register */
++#define DDRC_DDLP_TCTLUDP_BIT	24
++#define DDRC_DDLP_TCTLUDP_FF	(0xff << DDRC_DDLP_TCTLUDP_BIT)
++
++/* DDRC Load-Mode-Register */
++#define DDRC_LMR_DDR_ADDR_BIT	12 /* When performing a DDR command, DDRC_ADDR[13:0]
++									  corresponding to external DDR address Pin A[13:0] */
++#define DDRC_LMR_DDR_ADDR_MASK	(0xfffff << DDRC_LMR_DDR_ADDR_BIT)
++
++#define DDRC_LMR_MA_BIT		16 /* FOR LPDDR2, MA[9:0] */
++#define DDRC_LMR_OP_BIT		24 /* FOR LPDDR2, OP[9:0] */
++
++#define DDRC_LMR_BA_BIT		9 /* When performing a DDR command, BA[2:0]
++								 corresponding to external DDR address Pin BA[2:0]. */
++#define DDRC_LMR_BA_MASK	(0x7 << DDRC_LMR_BA_BIT)
++#define DDRC_LMR_CMD_BIT	6
++#define DDRC_LMR_CMD_MASK	(0x7 << DDRC_LMR_CMD_BIT)
++#define DDRC_LMR_CMD_PREC	(0 << DDRC_LMR_CMD_BIT)/* Precharge one bank/All banks */
++#define DDRC_LMR_CMD_AUREF	(1 << DDRC_LMR_CMD_BIT)/* Auto-Refresh */
++#define DDRC_LMR_CMD_LMR	(2 << DDRC_LMR_CMD_BIT)/* Load Mode Register */
++#define DDRC_LMR_CMD_ZQCL_CS0	(3 << DDRC_LMR_CMD_BIT)/* ZQCL for DDR3 on CS0 */
++#define DDRC_LMR_CMD_ZQCL_CS1	(4 << DDRC_LMR_CMD_BIT)/* ZQCL for DDR3 on CS1 */
++#define DDRC_LMR_CMD_ZQCS_CS0	(5 << DDRC_LMR_CMD_BIT)/* ZQCS for DDR3 on CS0 */
++#define DDRC_LMR_CMD_ZQCS_CS1	(6 << DDRC_LMR_CMD_BIT)/* ZQCS for DDR3 on CS1 */
++
++#define DDRC_LMR_TMRD_BIT	1
++#define DDRC_LMR_TMRD_MASK	(0x1f << DDRC_LMR_TMRD_BIT)
++#define DDRC_LMR_START		(1 << 0) /* 0 No command is performed
++										1 On the posedge of START, perform a command
++										defined by CMD field */
++
++/* DDRC  Auto-Refresh Counter */
++#define DDRC_REFCNT_REF_EN		(1 << 0) /* Enable Refresh Counter */
++#define DDRC_REFCNT_CLK_DIV_BIT		1  /* Clock Divider for auto-refresh counter. */
++#define DDRC_REFCNT_CLK_DIV_MASK	(0x7 << DDRC_REFCNT_CLKDIV_BIT)
++
++#define DDRC_REFCNT_PREREF_CNT_BIT	4
++#define DDRC_REFCNT_PREREF_CNT_MASK	(0xf << DDRC_REFCNT_PREREF_CNT_BIT)
++#define DDRC_REFCNT_PREREF_CNT(val)	(val << DDRC_REFCNT_PREREF_CNT_BIT)
++#define DDRC_REFCNT_PREREF_CNT_DEFAULT	DDRC_REFCNT_PREREF_CNT(8)
++
++#define DDRC_REFCNT_CNT_BIT		8  /* 8-bit counter */
++#define DDRC_REFCNT_CNT_MASK		(0xff << DDRC_REFCNT_CNT_BIT)
++
++#define DDRC_REFCNT_CON_BIT		16 /* Constant value used to compare with CNT value. */
++#define DDRC_REFCNT_CON_MASK		(0xff << DDRC_REFCNT_CON_BIT)
++
++#define DDRC_REFCNT_TRFC_BIT		24
++#define DDRC_REFCNT_TRFC_MASK		(0x3f << DDRC_REFCNT_TRFC_BIT)
++
++#define DDRC_REFCNT_PREREF_EN_BIT	30
++#define DDRC_REFCNT_PREREF_EN		(1 << DDRC_REFCNT_PREREF_EN_BIT)
++
++#define DDRC_REFCNT_PBREF_EN_BIT	31
++#define DDRC_REFCNT_PBREF_EN		(1 << DDRC_REFCNT_PBREF_EN_BIT)
++
++/* DDRC Memory Map Config Register */
++#define DDRC_MMAP_BASE_BIT		8 /* base address */
++#define DDRC_MMAP_BASE_MASK		(0xff << DDRC_MMAP_BASE_BIT)
++#define DDRC_MMAP_MASK_BIT		0 /* address mask */
++#define DDRC_MMAP_MASK_MASK		(0xff << DDRC_MMAP_MASK_BIT)
++
++#define DDRC_MMAP0_BASE			(0x20 << DDRC_MMAP_BASE_BIT)
++#define DDRC_MMAP1_BASE_64M		(0x24 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++#define DDRC_MMAP1_BASE_128M		(0x28 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++#define DDRC_MMAP1_BASE_256M		(0x30 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
++
++#define DDRC_MMAP_MASK_64_64		(0xfc << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++#define DDRC_MMAP_MASK_128_128		(0xf8 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++#define DDRC_MMAP_MASK_256_256		(0xf0 << DDRC_MMAP_MASK_BIT)  /*mask for two 128M SDRAM*/
++
++/* DDR device data width configure register */
++#define DDRC_DWCFG_DFI_INIT_START	(1 << 3)
++
++/* DDR device status register */
++#define DDRC_DWSTATUS_DFI_INIT_COMP	(1 << 0)
++
++/* DDRC AHB Bus Register Protection Register */
++#define DDRC_HREGPRO_HPRO_EN		(1 << 0)
++
++/* DDRC APB Bus Register Protection Register */
++#define DDRC_PREGPRO_PPRO_EN		(1 << 0)
++
++
++/* DDRC clock gate unit configure 0 */
++#define DDRC_CGU_PORT7		(1 << 28)
++#define DDRC_CGU_PORT6		(1 << 24)
++#define DDRC_CGU_PORT5		(1 << 20)
++#define DDRC_CGU_PORT4		(1 << 16)
++#define DDRC_CGU_PORT3		(1 << 12)
++#define DDRC_CGU_PORT2		(1 << 8)
++#define DDRC_CGU_PORT1		(1 << 4)
++#define DDRC_CGU_PORT0		(1 << 0)
++
++/* DDRC clock gate unit configure 1 */
++#define DDRC_CGU_BWM		(1 << 8)
++#define DDRC_CGU_PCTRL		(1 << 4)
++#define DDRC_CGU_SCH		(1 << 1)
++#define DDRC_CGU_PA		(1 << 0)
++
++
++
++/*
++ * DDR INNOPHY REGISTER BITS DEFINE
++ * */
++
++/* DDRP DQ Width Register */
++#define DDRP_DQ_WIDTH_DQ_H		(1 << 1)
++#define DDRP_DQ_WIDTH_DQ_L		(1 << 0)
++
++/* DDRP Pll Ctrl Register */
++#define DDRP_PLL_CTRL_PLLPDEN		(1 << 1)
++
++/* DDRP Training Ctrl Register */
++#define DDRP_TRAINING_CTRL_WL_BP	(1 << 3)
++#define DDRP_TRAINING_CTRL_WL_START	(1 << 2)
++#define DDRP_TRAINING_CTRL_DSCSE_BP	(1 << 1)
++#define DDRP_TRAINING_CTRL_DSACE_START	(1 << 0)
++
++/* DDRP Training Done Register */
++#define DDRP_CALIB_DONE_HDQCFB 		(1 << 3)
++#define DDRP_CALIB_DONE_LDQCFB 		(1 << 2)
++#define DDRP_CALIB_DONE_HDQCFA 		(1 << 1)
++#define DDRP_CALIB_DONE_LDQCFA 		(1 << 0)
++#define DDRP_CALIB_DONE_HWRLFB 		(1 << 3)
++#define DDRP_CALIB_DONE_LWRLFB 		(1 << 2)
++#define DDRP_CALIB_DONE_HWRLFA 		(1 << 1)
++#define DDRP_CALIB_DONE_LWRLFA 		(1 << 0)
++
++/* DDRP CALIB BP Register */
++#define DDRP_CALIB_BP_CYCLESELBH_BIT	4
++#define DDRP_CALIB_BP_OPHCSELBH_BIT	3
++#define DDRP_CALIB_BP_DLLSELBH_BIT	0
++
++/* DDRP Init Complete Register */
++#define DDRP_INIT_COMP			(1 << 0)
++
++#define DDRP_PLL_LOCK			(1 << 3)
++
++#define REG32(addr) *(volatile unsigned int *)(addr)
++
++#define ddr_writel(value, reg)	(REG32(DDRC_BASE + reg) = (value))
++#define ddr_readl(reg)		REG32(DDRC_BASE + reg)
++#endif /* __DDR_H__ */
+diff --git a/arch/mips/xburst2/soc-x2500/include/soc/extal.h b/arch/mips/xburst2/soc-x2500/include/soc/extal.h
+new file mode 100644
+index 000000000..78541e723
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/include/soc/extal.h
+@@ -0,0 +1,8 @@
++
++#ifndef __JZSOC_EXTAL_H__
++#define __JZSOC_EXTAL_H__
++
++#define JZ_EXTAL_RTC	32768     /* RTC extal freq: 32.768 KHz */
++#define JZ_EXTAL	(CONFIG_EXTAL_CLOCK * 1000000)
++
++#endif
+diff --git a/arch/mips/xburst2/soc-x2500/include/soc/gpio.h b/arch/mips/xburst2/soc-x2500/include/soc/gpio.h
+new file mode 100644
+index 000000000..66c53e6e8
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/include/soc/gpio.h
+@@ -0,0 +1,40 @@
++#ifndef _SOC_GPIO_H_
++#define _SOC_GPIO_H_
++
++enum gpio_function {
++    GPIO_FUNC_0    = 0x10,  //0000, GPIO as function 0 / device 0
++    GPIO_FUNC_1    = 0x11,  //0001, GPIO as function 1 / device 1
++    GPIO_FUNC_2    = 0x12,  //0010, GPIO as function 2 / device 2
++    GPIO_FUNC_3    = 0x13,  //0011, GPIO as function 3 / device 3
++    GPIO_OUTPUT0   = 0x14,  //0100, GPIO output low  level
++    GPIO_OUTPUT1   = 0x15,  //0101, GPIO output high level
++    GPIO_INPUT     = 0x16,  //0110, GPIO as input.7 also.
++    GPIO_INT_LO    = 0x18,  //1000, Low  Level trigger interrupt
++    GPIO_INT_HI    = 0x19,  //1001, High Level trigger interrupt
++    GPIO_INT_FE    = 0x1a,  //1010, Fall Edge trigger interrupt
++    GPIO_INT_RE    = 0x1b,  //1011, Rise Edge trigger interrupt
++    GPIO_INT_MASK_LO   = 0x1c,  //1100, Port is low level triggered interrupt input. Interrupt is masked.
++    GPIO_INT_MASK_HI   = 0x1d,  //1101, Port is high level triggered interrupt input. Interrupt is masked.
++    GPIO_INT_MASK_FE   = 0x1e,  //1110, Port is fall edge triggered interrupt input. Interrupt is masked.
++    GPIO_INT_MASK_RE   = 0x1f,  //1111, Port is rise edge triggered interrupt input. Interrupt is masked.
++
++    GPIO_PULL_HIZ  = 0x80,    //no pull
++    GPIO_PULL_UP   = 0xa0,    //pull high
++    GPIO_PULL_DOWN = 0xc0,    //pull low
++};
++
++#define GPIO_PA(n) (0 * 32 + (n))
++#define GPIO_PB(n) (1 * 32 + (n))
++#define GPIO_PC(n) (2 * 32 + (n))
++#define GPIO_PD(n) (3 * 32 + (n))
++
++enum gpio_port {
++	GPIO_PORT_A, GPIO_PORT_B,
++	GPIO_PORT_C, GPIO_PORT_D,
++	/* this must be last */
++	GPIO_NR_PORTS,
++};
++
++int jzgpio_set_func(int port, enum gpio_function func, unsigned long pins);
++
++#endif /* _SOC_GPIO_H_ */
+diff --git a/arch/mips/xburst2/soc-x2500/include/soc/mmc.h b/arch/mips/xburst2/soc-x2500/include/soc/mmc.h
+new file mode 100644
+index 000000000..6db74c179
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/include/soc/mmc.h
+@@ -0,0 +1,5 @@
++#ifndef __MMC_H
++#define __MMC_H
++
++extern int jzmmc_manual_detect(int index, int on);
++#endif
+diff --git a/arch/mips/xburst2/soc-x2500/include/soc/pdma.h b/arch/mips/xburst2/soc-x2500/include/soc/pdma.h
+new file mode 100644
+index 000000000..2308505d1
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/include/soc/pdma.h
+@@ -0,0 +1,49 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2021 by nick shen <xianghui.shen@ingneic.com>
++ */
++#ifndef __ASM_MACH_INGENIC_PDMA_H__
++#define __ASM_MACH_INGENIC_PDMA_H__
++
++#include <dt-bindings/dma/ingenic-pdma.h>
++#define INGENIC_DMA_REQ_AUTO 0xff
++#define INGENIC_DMA_CHAN_CNT 32
++unsigned int pdma_maps[INGENIC_DMA_CHAN_CNT] = {
++	INGENIC_DMA_REQ_AUTO,
++	INGENIC_DMA_REQ_AUTO,
++	INGENIC_DMA_REQ_AIC_LOOP_RX,
++	INGENIC_DMA_REQ_AIC_TX,
++	INGENIC_DMA_REQ_AIC_F_RX,
++	INGENIC_DMA_REQ_AUTO_TX,
++	INGENIC_DMA_REQ_SADC_RX,
++	INGENIC_DMA_REQ_DMIC_RX,
++	INGENIC_DMA_REQ_UART3_TX,
++	INGENIC_DMA_REQ_UART3_RX,
++	INGENIC_DMA_REQ_UART2_TX,
++	INGENIC_DMA_REQ_UART2_RX,
++	INGENIC_DMA_REQ_UART1_TX,
++	INGENIC_DMA_REQ_UART1_RX,
++	INGENIC_DMA_REQ_UART0_TX,
++	INGENIC_DMA_REQ_UART0_RX,
++	INGENIC_DMA_REQ_SSI0_TX,
++	INGENIC_DMA_REQ_SSI0_RX,
++	INGENIC_DMA_REQ_SSI1_TX,
++	INGENIC_DMA_REQ_SSI1_RX,
++	INGENIC_DMA_REQ_SLV_TX,
++	INGENIC_DMA_REQ_SLV_RX,
++	INGENIC_DMA_REQ_I2C0_TX,
++	INGENIC_DMA_REQ_I2C0_RX,
++	INGENIC_DMA_REQ_I2C1_TX,
++	INGENIC_DMA_REQ_I2C1_RX,
++	INGENIC_DMA_REQ_I2C2_TX,
++	INGENIC_DMA_REQ_I2C2_RX,
++	INGENIC_DMA_REQ_I2C3_TX,
++	INGENIC_DMA_REQ_I2C3_RX,
++	INGENIC_DMA_REQ_DES_TX,
++	INGENIC_DMA_REQ_DES_RX,
++};
++#endif
++
+diff --git a/arch/mips/xburst2/soc-x2500/include/soc/rtc.h b/arch/mips/xburst2/soc-x2500/include/soc/rtc.h
+new file mode 100644
+index 000000000..871add1fc
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/include/soc/rtc.h
+@@ -0,0 +1,96 @@
++#ifndef __RTC_H__
++#define __RTC_H__
++
++/*
++ * RTC registers offset address definition
++ */
++#define RTC_RTCCR		(0x00)	/* rw, 32, 0x00000081 */
++#define RTC_RTCSR		(0x04)	/* rw, 32, 0x???????? */
++#define RTC_RTCSAR		(0x08)	/* rw, 32, 0x???????? */
++#define RTC_RTCGR		(0x0c)	/* rw, 32, 0x0??????? */
++
++#define RTC_HCR			(0x20)  /* rw, 32, 0x00000000 */
++#define RTC_HWFCR		(0x24)  /* rw, 32, 0x0000???0 */
++#define RTC_HRCR		(0x28)  /* rw, 32, 0x00000??0 */
++#define RTC_HWCR		(0x2c)  /* rw, 32, 0x00000008 */
++#define RTC_HWRSR		(0x30)  /* rw, 32, 0x00000000 */
++#define RTC_HSPR		(0x34)  /* rw, 32, 0x???????? */
++#define RTC_WENR		(0x3c)  /* rw, 32, 0x00000000 */
++#define RTC_WKUPPINCR		(0x48)	/* rw, 32, 0x00050064*/
++
++/*
++ * RTC registers common define
++ */
++
++/* RTC control register(RTCCR) */
++#define RTCCR_WRDY		BIT(7)
++#define RTCCR_1HZ		BIT(6)
++#define RTCCR_1HZIE		BIT(5)
++#define RTCCR_AF		BIT(4)
++#define RTCCR_AIE		BIT(3)
++#define RTCCR_AE		BIT(2)
++#define RTCCR_SELEXC		BIT(1)
++#define RTCCR_RTCE		BIT(0)
++
++
++/* Generate the bit field mask from msb to lsb */
++#define BITS_H2L(msb, lsb)  ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))
++
++/* RTC regulator register(RTCGR) */
++#define RTCGR_LOCK		BIT(31)
++#define RTCGR_ADJC_LSB		16
++#define RTCGR_ADJC_MASK		BITS_H2L(25, RTCGR_ADJC_LSB)
++#define RTCGR_NC1HZ_LSB		0
++#define RTCGR_NC1HZ_MASK	BITS_H2L(15, RTCGR_NC1HZ_LSB)
++
++/* Hibernate control register(HCR) */
++#define HCR_PD			BIT(0)
++
++/* Hibernate wakeup filter counter register(HWFCR) */
++#define HWFCR_LSB		5
++#define HWFCR_MASK		BITS_H2L(15, HWFCR_LSB)
++#define HWFCR_WAIT_TIME(ms, clk) (((ms)*(clk)/1000+0xf) > HWFCR_MASK ? HWFCR_MASK : ((ms)*(clk)/1000+0xf) & HWFCR_MASK)
++
++/* Hibernate reset counter register(HRCR) */
++#define HRCR_LSB		11
++#define HRCR_MASK		BITS_H2L(14, HRCR_LSB)
++#define HRCR_WAIT_TIME(ms, clk) (((ms)*(clk)/1000 + 0x3ff - 0x800) > HRCR_MASK ? HRCR_MASK : \
++								 ((ms)*(clk)/1000 + 0x3ff - 0x800) & HRCR_MASK)
++
++
++/* Hibernate wakeup control register(HWCR) */
++/* Power detect default value; this value means enable */
++#define EPDET_LSB		3
++#define EPDET_DEFAULT           (0x5aa5a5a << EPDET_LSB)
++#define EPDET_ENABLE		(0x5aa5a5a << EPDET_LSB)
++#define EPDET_DISABLE		(0x1a55a5a5 << EPDET_LSB)
++#define HWCR_EALM		BIT(0)
++
++
++/* Hibernate wakeup status register(HWRSR) */
++#define HWRSR_APD		BIT(8)
++#define HWRSR_HR		BIT(5)
++#define HWRSR_PPR		BIT(4)
++#define HWRSR_PIN		BIT(1)
++#define HWRSR_ALM		BIT(0)
++
++/* write enable pattern register(WENR) */
++#define WENR_WEN		BIT(31)
++#define WENR_WENPAT_LSB		0
++#define WENR_WENPAT_MASK	BITS_H2L(15, WENR_WENPAT_LSB)
++#define WENR_WENPAT_WRITABLE	(0xa55a)
++
++/* Hibernate scratch pattern register(HSPR) */
++#define HSPR_RTCV               0x52544356      /* The value is 'RTCV', means rtc is valid */
++
++/*WKUP_PIN_RST control register (WKUPPINCR)*/
++#define WKUPPINCR_BIAS_CTRL	(0x1 << 16)	/* fix value*/
++#define WKUPPINCR_OSC_EN        BIT(18)
++#define WKUPPINCR_P_JUD_LEN_LSB	4
++#define WKUPPINCR_P_JUD_LEN_MASK	BITS_H2L(7, WKUPPINCR_P_JUD_LEN_LSB)
++#define WKUPPINCR_P_JUD_LEN(s)  ((s) << WKUPPINCR_P_JUD_LEN_LSB) > WKUPPINCR_P_JUD_LEN_MASK ? \
++	WKUPPINCR_P_JUD_LEN_MASK : (s) << WKUPPINCR_P_JUD_LEN_LSB
++#define WKUPPINCR_P_JUD_EN	(0x4)
++/* The divider is decided by the RTC clock frequency. */
++#define RTC_FREQ_DIVIDER	(32768 - 1)
++#endif	/* __RTC_H__ */
+diff --git a/arch/mips/xburst2/soc-x2500/include/soc/sfc.h b/arch/mips/xburst2/soc-x2500/include/soc/sfc.h
+new file mode 100644
+index 000000000..b1684bec9
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/include/soc/sfc.h
+@@ -0,0 +1,211 @@
++#ifndef __SFC_REGISTER_H
++#define __SFC_REGISTER_H
++
++/* SFC register */
++
++#define	SFC_GLB0			(0x0000)
++#define	SFC_DEV_CONF			(0x0004)
++#define	SFC_DEV_STA_EXP			(0x0008)
++#define	SFC_DEV0_STA_RT			(0x000c)
++#define	SFC_DEV_STA_MSK			(0x0010)
++#define	SFC_TRAN_CONF0(n)		(0x0014 + (n * 4))
++#define	SFC_TRAN_LEN			(0x002c)
++#define	SFC_DEV_ADDR(n)			(0x0030 + (n * 4))
++#define	SFC_DEV_ADDR_PLUS(n)		(0x0048 + (n * 4))
++#define	SFC_MEM_ADDR			(0x0060)
++#define	SFC_TRIG			(0x0064)
++#define	SFC_SR				(0x0068)
++#define	SFC_SCR				(0x006c)
++#define	SFC_INTC			(0x0070)
++#define	SFC_FSM				(0x0074)
++#define	SFC_CGE				(0x0078)
++#define SFC_CMD_IDX                     (0x007c)
++#define SFC_COL_ADDR                    (0x0080)
++#define SFC_ROW_ADDR                    (0x0084)
++#define SFC_STA_ADDR0                   (0x0088)
++#define SFC_STA_ADDR1                   (0x008c)
++#define SFC_DES_ADDR                    (0x0090)
++#define SFC_GLB1			(0x0094)
++#define SFC_DEV1_STA_RT			(0x0098)
++#define	SFC_TRAN_CONF1(n)		(0x009c + (n * 4))
++#define SFC_CDT                         (0x0800)  //0x800 ~ 0xbff
++#define	SFC_RM_DR			(0x1000)
++
++/* For SFC_GLB0 */
++#define GLB0_POLL_TIME_OFFSET		(16)
++#define GLB0_POLL_TIME_MSK		(0xffff << GLB0_POLL_TIME_OFFSET)
++#define GLB0_DES_EN			(1 << 15)
++#define GLB0_CDT_EN			(1 << 14)
++#define	GLB0_TRAN_DIR			(1 << 13)
++#define GLB0_TRAN_DIR_WRITE		(1)
++#define GLB0_TRAN_DIR_READ		(0)
++#define	GLB0_THRESHOLD_OFFSET		(7)
++#define GLB0_THRESHOLD_MSK		(0x3f << GLB0_THRESHOLD_OFFSET)
++#define GLB0_OP_MODE			(1 << 6)
++#define GLB0_OP_OFFSET                   (6)
++#define SLAVE_MODE			(0x0)
++#define DMA_MODE			(0x1)
++#define GLB0_PHASE_NUM_OFFSET		(3)
++#define GLB0_PHASE_NUM_MSK		(0x7  << GLB0_PHASE_NUM_OFFSET)
++#define GLB0_WP_EN			(1 << 2)
++#define GLB0_BURST_MD_OFFSET		(0)
++#define GLB0_BURST_MD_MSK		(0x3  << GLB0_BURST_MD_OFFSET)
++
++/* For SFC_DEV_CONF */
++#define DEV_CONF_STA_ENDIAN_OFFSET	(31)
++#define	STA_ENDIAN_LSB			(0)
++#define	STA_ENDIAN_MSB			(1)
++#define	DEV_CONF_SMP_DELAY_OFFSET	(16)
++#define	DEV_CONF_SMP_DELAY_MSK		(0x1f << DEV_CONF_SMP_DELAY_OFFSET)
++#define DEV_CONF_SMP_DELAY_0		(0)
++#define DEV_CONF_SMP_DELAY_45		(1)
++#define DEV_CONF_SMP_DELAY_90		(2)
++#define DEV_CONF_SMP_DELAY_135		(3)
++#define DEV_CONF_SMP_DELAY_180		(4)
++#define DEV_CONF_SMP_DELAY_225		(5)
++#define DEV_CONF_SMP_DELAY_270		(6)
++#define DEV_CONF_SMP_DELAY_315		(7)
++#define DEV_CONF_SMP_DELAY_1		(8)
++#define DEV_CONF_SMP_DELAY_2		(16)
++#define DEV_CONF_CMD_TYPE		(0x1 << 15)
++#define DEV_CONF_STA_TYPE_OFFSET	(13)
++#define DEV_CONF_STA_TYPE_MSK		(0x3 << DEV_CONF_STA_TYPE_OFFSET)
++#define DEV_CONF_THOLD_OFFSET		(11)
++#define	DEV_CONF_THOLD_MSK		(0x3 << DEV_CONF_THOLD_OFFSET)
++#define DEV_CONF_TSETUP_OFFSET		(9)
++#define DEV_CONF_TSETUP_MSK		(0x3 << DEV_CONF_TSETUP_OFFSET)
++#define DEV_CONF_TSH_OFFSET		(5)
++#define DEV_CONF_TSH_MSK		(0xf << DEV_CONF_TSH_OFFSET)
++#define DEV_CONF_CPHA			(0x1 << 4)
++#define DEV_CONF_CPOL			(0x1 << 3)
++#define DEV_CONF_CEDL			(0x1 << 2)
++#define DEV_CONF_HOLDDL			(0x1 << 1)
++#define DEV_CONF_WPDL			(0x1 << 0)
++
++/* For SFC_TRAN_CONF0 */
++#define TRAN_CONF0_CLK_MODE		(29)
++#define	TRAN_CONF0_CLK_MODE_MSK		(0x7 << TRAN_CONF0_CLK_MODE)
++#define TRAN_CONF0_CLK_MODE_SSS		(0)
++#define TRAN_CONF0_CLK_MODE_SSD		(1)
++#define TRAN_CONF0_CLK_MODE_SDS		(2)
++#define TRAN_CONF0_CLK_MODE_SDD		(3)
++#define TRAN_CONF0_CLK_MODE_DSS		(4)
++#define TRAN_CONF0_CLK_MODE_DSD		(5)
++#define TRAN_CONF0_CLK_MODE_DDS		(6)
++#define TRAN_CONF0_CLK_MODE_DDD		(7)
++#define	TRAN_CONF0_ADDR_WIDTH_OFFSET	(26)
++#define	TRAN_CONF0_ADDR_WIDTH_MSK	(0x7 << TRAN_CONF0_ADDR_WIDTH_OFFSET)
++#define TRAN_CONF0_POLLEN		(1 << 25)
++#define TRAN_CONF0_POLL_OFFSET		(25)
++#define TRAN_CONF0_CMDEN		(1 << 24)
++#define TRAN_CONF0_FMAT			(1 << 23)
++#define TRAN_CONF0_FMAT_OFFSET		(23)
++#define TRAN_CONF0_DMYBITS_OFFSET	(17)
++#define TRAN_CONF0_DMYBITS_MSK		(0x3f << TRAN_CONF0_DMYBITS_OFFSET)
++#define TRAN_CONF0_DATEEN		(1 << 16)
++#define TRAN_CONF0_DATEEN_OFFSET	(16)
++#define	TRAN_CONF0_CMD_OFFSET		(0)
++#define	TRAN_CONF0_CMD_MSK		(0xffff << TRAN_CONF0_CMD_OFFSET)
++
++/* For SFC_TRAN_CONF1 */
++#define TRAN_CONF1_DATA_ENDIAN		(1 << 18)
++#define TRAN_CONF1_DATA_ENDIAN_OFFSET	(18)
++#define TRAN_CONF1_DATA_ENDIAN_LSB	(0)
++#define TRAN_CONF1_DATA_ENDIAN_MSB	(1)
++#define TRAN_CONF1_WORD_UNIT_OFFSET	(16)
++#define TRAN_CONF1_WORD_UNIT_MSK	(3 << 16)
++#define TRAN_CONF1_TRAN_MODE_OFFSET	(4)
++#define TRAN_CONF1_TRAN_MODE_MSK	(0xf << TRAN_CONF1_TRAN_MODE_OFFSET)
++#define TRAN_CONF1_SPI_STANDARD		(0x0)
++#define TRAN_CONF1_SPI_DUAL		(0x1)
++#define TRAN_CONF1_SPI_QUAD		(0x5)
++#define TRAN_CONF1_SPI_IO_QUAD		(0x6)
++#define TRAN_CONF1_SPI_OCTAL		(0x9)
++#define TRAN_CONF1_SPI_IO_OCTAL		(0xa)
++#define TRAN_CONF1_SPI_FULL_OCTAL	(0xb)
++
++
++/* For SFC_TRIG */
++#define TRIG_FLUSH			(1 << 2)
++#define TRIG_STOP			(1 << 1)
++#define TRIG_START			(1 << 0)
++
++/* For SFC_SR */
++#define SFC_WORKING		(1 << 7)
++#define SFC_BUSY		(0x3 << 5)
++#define	SFC_END			(1 << 4)
++#define SFC_TREQ		(1 << 3)
++#define SFC_RREQ		(1 << 2)
++#define SFC_OVER		(1 << 1)
++#define SFC_UNDER		(1 << 0)
++
++/* For SFC_SCR */
++#define	CLR_END			(1 << 4)
++#define CLR_TREQ		(1 << 3)
++#define CLR_RREQ		(1 << 2)
++#define CLR_OVER		(1 << 1)
++#define CLR_UNDER		(1 << 0)
++
++//SFC_CMD_IDX
++#define CMD_IDX_MSK                     (0x3f << 0)
++#define CDT_DATAEN_MSK                  (0x1 << 31)
++#define CDT_DATAEN_OFF                  (31)
++#define CDT_DIR_MSK                     (0x1 << 30)
++#define CDT_DIR_OFF                     (30)
++
++/* For SFC_GLB1 */
++#define GLB1_DQS_EN			(1 << 2)
++#define GLB1_CHIP_SEL_OFFSET		(0)
++#define GLB1_CHIP_SEL_MSK		(0x3 << 0)
++#define GLB1_CHIP_SEL_0			(0)
++#define GLB1_CHIP_SEL_1			(1)
++#define GLB1_CHIP_SEL_01		(2)
++
++#define N_MAX			6
++#define MAX_SEGS		128
++
++#define CHANNEL_0		0
++#define CHANNEL_1		1
++#define CHANNEL_2		2
++#define CHANNEL_3		3
++#define CHANNEL_4		4
++#define CHANNEL_5		5
++
++#define ENABLE			1
++#define DISABLE			0
++
++#define COM_CMD			1	// common cmd
++#define POLL_CMD		2	// the cmd will poll the status of flash,ext: read status
++
++#define DMA_OPS			1
++#define CPU_OPS			0
++
++#define TM_STD_SPI		0
++#define TM_DI_DO_SPI	1
++#define TM_DIO_SPI		2
++#define TM_FULL_DIO_SPI	3
++#define TM_QI_QO_SPI	5
++#define TM_QIO_SPI		6
++#define	TM_FULL_QIO_SPI	7
++#define TM_OCTAL_SPT		9
++#define TM_OCTAL_IO_SPI		10
++#define TM_OCTAL_FULL_SPI	11
++
++
++#define DEFAULT_CDT		1
++#define UPDATE_CDT		2
++#define DEFAULT_ADDRSIZE	3
++#define DEFAULT_ADDRMODE	0
++
++
++#define THRESHOLD		32
++
++#define SFC_NOR_RATE    110
++#define DEF_ADDR_LEN    3
++#define DEF_TCHSH       6
++#define DEF_TSLCH       6
++#define DEF_TSHSL_R     20
++#define DEF_TSHSL_W     50
++
++
++#endif
+diff --git a/arch/mips/xburst2/soc-x2500/include/soc/tcsm_layout.h b/arch/mips/xburst2/soc-x2500/include/soc/tcsm_layout.h
+new file mode 100644
+index 000000000..2de46b7bd
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/include/soc/tcsm_layout.h
+@@ -0,0 +1,53 @@
++#ifndef __TCSM_LAYOUT_H__
++#define __TCSM_LAYOUT_H__
++
++/**
++ *      |-------------|
++ *      |    BANK0    |
++ *      |-------------|     <--- SLEEP_TCSM_BOOTCODE_TEXT
++ *      | BOOT CODE   |
++ *      |-------------|     <--- SLEEP_TCSM_RESUMECODE_TEXT
++ *      |    ...      |
++ *      | RESUME CODE |
++ *      |    ...      |
++ *      |-------------|     <--- SLEEP_TCSM_RESUME_DATA
++ *      |    ...      |
++ *      | RESUME DATA |
++ *      |    ...      |
++ *      |_____________|     <--- SLEEP_TCSM_CPU_RESMUE_SP
++ *
++ *
++ *      |-------------|
++ *      |    BANK1    |
++ *      |-------------|     <--- TO BE DEFINED
++ *      |             |
++ *      |             |
++ *      |    ...      |
++ *      |  VOICE DATA |
++ *      |    ...      |
++ *      |             |
++ *      |             |
++ *      |_____________|
++ *
++ */
++
++#define SLEEP_TCSM_SPACE           0xb3422000
++#define VOICE_TCSM_DATA_BUF	   0xb3423000
++#define TCSM_BANK_LEN              4096
++
++#define SLEEP_TCSM_BOOT_TEXT       (SLEEP_TCSM_SPACE)
++#define SLEEP_TCSM_BOOT_LEN        64
++#define SLEEP_TCSM_BOOT_END        (SLEEP_TCSM_BOOT_TEXT + SLEEP_TCSM_BOOT_LEN)
++
++#define SLEEP_TCSM_RESUME_TEXT     (SLEEP_TCSM_BOOT_END)
++#define SLEEP_TCSM_RESUME_LEN      2048
++#define SLEEP_TCSM_RESUME_END      (SLEEP_TCSM_RESUME_TEXT + SLEEP_TCSM_RESUME_LEN)
++
++#define SLEEP_TCSM_RESUME_DATA     (SLEEP_TCSM_RESUME_END)
++
++#define SLEEP_TCSM_SPACE_END       (SLEEP_TCSM_SPACE + TCSM_BANK_LEN)
++
++#define SLEEP_TCSM_CPU_RESMUE_SP   SLEEP_TCSM_SPACE_END - 4
++
++
++#endif	/*  __TCSM_LAYOUT_H__ */
+diff --git a/arch/mips/xburst2/soc-x2500/include/war.h b/arch/mips/xburst2/soc-x2500/include/war.h
+new file mode 100644
+index 000000000..fd1ef3147
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/include/war.h
+@@ -0,0 +1,27 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
++ */
++#ifndef __ASM_MACH_INGENIC_WAR_H__
++#define __ASM_MACH_INGENIC_WAR_H__
++
++#define R4600_V1_INDEX_ICACHEOP_WAR	0
++#define R4600_V1_HIT_CACHEOP_WAR	0
++#define R4600_V2_HIT_CACHEOP_WAR	0
++#define R5432_CP0_INTERRUPT_WAR		0
++#define BCM1250_M3_WAR			0
++#define SIBYTE_1956_WAR			0
++#define MIPS4K_ICACHE_REFILL_WAR	0
++#define MIPS_CACHE_SYNC_WAR		1
++#define MIPS_BRIDGE_SYNC_WAR            1
++#define TX49XX_ICACHE_INDEX_INV_WAR	0
++#define RM9000_CDEX_SMP_WAR		0
++#define ICACHE_REFILLS_WORKAROUND_WAR	0
++#define R10000_LLSC_WAR			0
++#define MIPS34K_MISSED_ITLB_WAR		0
++
++#endif
++
+diff --git a/arch/mips/xburst2/soc-x2500/libdmmu.c b/arch/mips/xburst2/soc-x2500/libdmmu.c
+new file mode 100644
+index 000000000..e3288d299
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/libdmmu.c
+@@ -0,0 +1,1087 @@
++/*
++ * This driver is used by VPU driver.
++ *
++ * Copyright (C) 2015 Ingenic Semiconductor Co., Ltd.
++ *	http://www.ingenic.com
++ * Author:	Yan Zhengting <zhengting.yan@ingenic.com>
++ * Modify by:	Sun Jiwei <jiwei.sun@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/platform_device.h>
++#include <linux/fs.h>
++#include <linux/file.h>
++#include <linux/mm.h>
++#include <linux/list.h>
++#include <linux/mutex.h>
++#include <linux/proc_fs.h>
++#include <linux/debugfs.h>
++#include <linux/mempolicy.h>
++#include <linux/mm_types.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <asm/current.h>
++#include <asm/cacheflush.h>
++#include <asm/tlbflush.h>
++#include <asm/io.h>
++#include <linux/vmalloc.h>
++#include <linux/sched.h>
++#include <ingenic_proc.h>
++#include <linux/module.h>
++#include <linux/mmu_context.h>
++#include <linux/mmu_notifier.h>
++#include <linux/pgtable.h>
++
++#include <libdmmu.h>
++#define print_dbg(f, arg...) printk(KERN_INFO "dpu: %s, %d: " f "\n", __func__, __LINE__, ## arg)
++
++#define MAP_COUNT		0x10
++#define MAP_CONUT_MASK		0xff0
++
++#define DMMU_PTE_VLD 		0x01
++#define DMMU_PMD_VLD 		0x01
++
++#define KSEG0_LOW_LIMIT		0x80000000
++#define KSEG1_HEIGH_LIMIT	0xC0000000
++
++enum mem_break{
++    MODE1,  /* 13 24 57 68 911 1012 ... */
++    MODE2,  /* 13 24 35 46 57 68 79 810 ... */
++    MODE3   /* 12 34 56 78 ... */
++};
++
++LIST_HEAD(handle_list);
++static unsigned long reserved_pte = 0;
++static unsigned long res_pte_paddr;
++
++struct pmd_node {
++	unsigned int count;
++	unsigned long index;
++	unsigned long page;
++	struct list_head list;
++};
++
++struct map_node {
++	struct device *dev;
++	unsigned long start;
++	unsigned long len;
++	struct list_head list;
++};
++
++struct dmmu_handle {
++	pid_t tgid;
++	unsigned long pdg;
++	struct mutex lock;
++	struct list_head list;
++	struct list_head pmd_list;
++	struct list_head map_list;
++	struct list_head dev_notifier_list;
++
++	struct mm_struct *handle_mm; /* mm struct used to match exit_mmap notify */
++
++	struct mmu_notifier mn;
++};
++
++/* for test */
++static struct dmmu_handle *find_handle(void);
++static struct dmmu_handle *create_handle(void);
++static void dmmu_cache_wback(struct dmmu_handle *h);
++static int dmmu_mm_dev_release(struct dmmu_handle *h);
++
++int dmmu_flush_cache(unsigned long vaddr, unsigned long len)
++{
++	struct list_head *pos, *next;
++	struct dmmu_handle *h = NULL;
++	struct map_node *n = NULL;
++	unsigned long *pgd, *pte_phys, *pte;
++	unsigned long virpage_phy;
++	unsigned long v_end = vaddr+len;
++	int found = 0;
++	int index;
++
++	h = find_handle();
++	if(!h){
++		printk("%s find handle err!\n",__func__);
++		return -1;
++	}
++	if (vaddr & 0xfff) {
++		printk("%s addr align page err!\n",__func__);
++		return -1;
++	}
++	list_for_each_safe(pos, next, &h->map_list) {
++		n = list_entry(pos, struct map_node, list);
++		if((vaddr >= n->start) &&
++			((vaddr+len) <= (n->start + n->len))) {
++			found = 1;
++			break;
++		}
++	}
++	if(!found) {
++		printk("%s addr err!\n",__func__);
++		return -1;
++	}
++	pgd = (unsigned long *)h->pdg;
++	while(vaddr < v_end) {
++		index = vaddr>>22;
++		pte_phys = (unsigned long *)(pgd[index] & ~DMMU_PMD_VLD);
++		pte = (unsigned long *)phys_to_virt((unsigned long)pte_phys);
++		index = ((vaddr & 0x3ff000) >> 12);
++		virpage_phy = pte[index] & ~DMMU_PTE_VLD;
++		dma_cache_wback((unsigned long)phys_to_virt(virpage_phy),PAGE_SIZE);
++		vaddr+=PAGE_SIZE;
++	}
++	return 0;
++}
++
++EXPORT_SYMBOL(dmmu_flush_cache);
++static int make_smash_list(struct dmmu_handle *h, unsigned long vaddr, unsigned long (**base)[2], unsigned int *len)
++{
++    unsigned long *pgd = (unsigned long *)h->pdg;
++    unsigned long (*list_smash)[2] = NULL;
++    unsigned int list_len = 0;
++    unsigned long *pte, *pte_phys;
++    unsigned int i, index;
++
++    struct list_head *pos, *next;
++	struct map_node *n;
++
++    list_for_each_safe(pos, next, &h->map_list) {
++        n = list_entry(pos, struct map_node, list);
++        if(vaddr == n->start) {
++            list_len = (n->len) >> 12;
++            break;
++        }
++    }
++
++    if (list_len) {
++        list_smash = kmalloc(list_len * 2 * 4, GFP_KERNEL);
++        if (list_smash) {
++            i = 0;
++            while(i < list_len) {
++                list_smash[i][0] = (unsigned long)(vaddr & 0xfffff000);
++
++		index = vaddr>>22;
++                pte_phys = (unsigned long *)(pgd[index] & ~DMMU_PMD_VLD);
++
++
++		pte = (unsigned long *)phys_to_virt((unsigned long)pte_phys);
++
++		index = ((vaddr & 0x3ff000) >> 12);
++//		printk(">>>>>>virt = 0x%lx, phys = 0x%lx\n", vaddr,
++//				*((unsigned long int *) (((unsigned long)pte_phys+index*4) | 0xa0000000)));
++		list_smash[i][1] = pte[index];
++
++                vaddr+=0x1000;
++		i++;
++            }
++        }
++    }
++
++    if (list_smash) {
++        *base = list_smash;
++        *len = list_len;
++        return 0;
++    } else {
++        return -1;
++    }
++}
++EXPORT_SYMBOL(dmmu_dump_map);
++
++int dmmu_dump_map(unsigned long vaddr)
++{
++	struct dmmu_handle *h = NULL;
++    unsigned long (*list_smash)[2] = NULL;
++    unsigned int list_len = 0;
++    unsigned long *tmp;
++
++	h = find_handle();
++	if(!h)
++		h = create_handle();
++	if(!h)
++		return -1;
++    /* 检查4k对� */
++    if (vaddr & 0xfff){
++        return -1;
++    }
++
++	mutex_lock(&h->lock);
++
++    if (make_smash_list(h, vaddr, &list_smash, &list_len)) {
++	    mutex_unlock(&h->lock);
++        return -1;
++    } else {
++        unsigned int i;
++        for (i = 0; i<list_len; i++) {
++	    tmp = (unsigned long*)((list_smash[i][1] & ~1) | 0xa0000000);
++            printk("[virt: 0x%08lx ---> phys: 0x%08lx] uncache: 0x%08lx\n",
++			    list_smash[i][0],list_smash[i][1],(unsigned long)tmp);
++
++	    printk("value[0] = 0x%08lx, value[1] = 0x%08lx value[2] = 0x%08lx value[1013] = 0x%08lx\n",
++			tmp[0], tmp[1], tmp[2], tmp[1013]);
++        }
++    }
++
++	mutex_unlock(&h->lock);
++    kfree((void*)list_smash);
++
++    return 0;
++}
++
++    /* 13 24 57 68 911 1012 ... */
++static int smash_mode1(unsigned long (*base)[2], unsigned int len)
++{
++    unsigned int i;
++    unsigned long tmp;
++    if (len >= 4) {
++        for (i=0; i<len; i += 2) {
++            tmp = base[i][1];
++            base[i][1] = base[i+1][1];
++            base[i+1][1] = tmp;
++        }
++    }
++    return 0;
++}
++
++    /* 13 24 35 46 57 68 79 810 ... */
++static int smash_mode2(unsigned long (*base)[2], unsigned int len)
++{
++    /* unsigned int i; */
++    /* unsigned long tmp; */
++    return 0;
++}
++
++    /* 12 34 56 78 ... */
++static int smash_mode3(unsigned long (*base)[2], unsigned int len)
++{
++    unsigned int i;
++    unsigned long tmp;
++if (len >= 4) {
++        for (i=0; i<len/2-1; i++) {
++            tmp = base[i][1];
++            base[i][1] = base[len-1-i][1];
++            base[len-1-i][1] = tmp;
++        }
++        for (i=0; i<len; i += 2) {
++            tmp = base[i][1];
++            base[i][1] = base[i+1][1];
++            base[i+1][1] = tmp;
++        }
++    }
++    return 0;
++}
++
++static int update_dmmu_pte(struct dmmu_handle *h, unsigned long vaddr,
++		           unsigned long (**base)[2], unsigned int len)
++{
++    unsigned long *pgd = (unsigned long *)h->pdg;
++    unsigned long *pte;
++    unsigned int i, index;
++
++    for (i=0; i<len; i++) {
++	index = vaddr>>22;
++        pte = (unsigned long *)(pgd[index] & ~DMMU_PMD_VLD);
++	pte = (unsigned long *)phys_to_virt((unsigned long)pte);
++
++	index = ((vaddr & 0x3ff000) >> 12);
++	pte[index] = (*base)[i][1];
++         vaddr+=0x1000;
++    }
++    return 0;
++}
++
++static int update_process_pte(unsigned long vaddr, unsigned long (**base)[2], unsigned int len)
++{
++    unsigned int i;
++    pgd_t *pgdir;
++    pmd_t *pmdir;
++    pte_t *pte;
++    spin_lock(&current->mm->page_table_lock);
++    for (i=0; i<len; i++) {
++        pgdir = pgd_offset(current->mm, vaddr);
++        if(pgd_none(*pgdir) || pgd_bad(*pgdir))
++            return 0;
++        pmdir = pmd_offset((pud_t *)pgdir, vaddr);
++        if(pmd_none(*pmdir) || pmd_bad(*pmdir))
++            return 0;
++        pte = pte_offset_kernel(pmdir,vaddr);
++        if (pte_present(*pte)){
++	  pte->pte = (*base)[i][1];
++	}
++        vaddr += 4096;
++    }
++    spin_unlock(&current->mm->page_table_lock);
++    return 0;
++}
++
++int dmmu_memory_smash(unsigned long vaddr, int smash_mode)
++{
++	struct dmmu_handle *h = NULL;
++    unsigned long (*list_smash)[2] = NULL;
++    unsigned int list_len = 0;
++	struct vm_area_struct * vma;
++
++	h = find_handle();
++	if(!h){
++		h = create_handle();
++	}
++	if(!h)
++		return -1;
++
++    /* 检查4k对� */
++    if (vaddr & 0xfff){
++        return -1;
++    }
++
++	mutex_lock(&h->lock);
++
++    if (make_smash_list(h, vaddr, &list_smash, &list_len)) {
++	    mutex_unlock(&h->lock);
++        return -1;
++    } else {
++        switch (smash_mode) {
++            case MODE1:
++		print_dbg("smash_mode = %u\n",smash_mode);
++                smash_mode1(list_smash, list_len);
++                break;
++            case MODE2:
++		print_dbg("smash_mode = %u\n",smash_mode);
++                smash_mode2(list_smash, list_len);
++                break;
++            case MODE3:
++		print_dbg("smash_mode = %u\n",smash_mode);
++                smash_mode3(list_smash, list_len);
++                break;
++            default:
++                break;
++        }
++    }
++    update_dmmu_pte(h, vaddr, &list_smash, list_len);
++    update_process_pte(vaddr, &list_smash, list_len);
++
++	dmmu_cache_wback(h);
++	vma = find_vma(current->mm, vaddr);
++	flush_tlb_range(vma, vaddr, vaddr+(list_len*PAGE_SIZE));
++
++	mutex_unlock(&h->lock);
++    kfree(list_smash);
++
++    return 0;
++}
++EXPORT_SYMBOL(dmmu_memory_smash);
++
++static struct map_node *check_map(struct dmmu_handle *h,unsigned long vaddr,unsigned long len)
++{
++	struct list_head *pos, *next;
++	struct map_node *n;
++	list_for_each_safe(pos, next, &h->map_list) {
++		n = list_entry(pos, struct map_node, list);
++		if(vaddr == n->start && len == n->len)
++			return n;
++	}
++	return NULL;
++}
++
++static void handle_add_map(struct device *dev,struct dmmu_handle *h,unsigned long vaddr,unsigned long len)
++{
++	struct map_node *n = kmalloc(sizeof(*n),GFP_KERNEL);
++	if(n == NULL) {
++		printk("malloc map_list node failed !!\n");
++		return;
++	}
++	n->dev = dev;
++	n->start = vaddr;
++	n->len = len;
++	INIT_LIST_HEAD(&n->list);
++	list_add(&n->list,&h->map_list);
++}
++
++static unsigned int get_pfn(unsigned int vaddr)
++{
++	pgd_t *pgdir;
++	pmd_t *pmdir;
++	pte_t *pte;
++	pgdir = pgd_offset(current->mm, vaddr);
++	if(pgd_none(*pgdir) || pgd_bad(*pgdir)) {
++		return 0;
++	}
++	pmdir = pmd_offset((pud_t *)pgdir, vaddr);
++	if(pmd_none(*pmdir) || pmd_bad(*pmdir)) {
++		return 0;
++	}
++	// TODO: 如果是kmap的地�，比如C空间的地�这里需�处�一下使用pte_offset_kmap.
++	pte = pte_offset_kernel(pmdir,vaddr);
++	if (pte_present(*pte)) {
++
++		return pte_pfn(*pte) << PAGE_SHIFT;
++	}
++
++	return 0;
++}
++
++static unsigned long dmmu_v2pfn(unsigned long vaddr)
++{
++	if(vaddr < KSEG0_LOW_LIMIT)
++		return get_pfn(vaddr);
++
++	if(vaddr >= KSEG0_LOW_LIMIT && vaddr < KSEG1_HEIGH_LIMIT)
++		return virt_to_phys((void *)vaddr);
++
++	panic("dmmu_v2pfn error!");
++	return 0;
++}
++
++static unsigned long unmap_node(struct pmd_node *n,unsigned long vaddr,unsigned long end,int check)
++{
++	unsigned int *pte = (unsigned int *)n->page;
++	int index = ((vaddr & 0x3ff000) >> 12);
++	int free = !check || (--n->count == 0);
++	struct page *page = NULL;
++
++	if(vaddr && end) {
++		while(index < 1024 && vaddr < end) {
++			if(pte[index] & MAP_CONUT_MASK) {
++				pte[index] -= MAP_COUNT;
++			} else {
++				page = pfn_to_page(pte[index] >> PAGE_SHIFT);
++
++				ClearPageReserved(page);
++				pte[index] = reserved_pte;
++			}
++			index++;
++			vaddr += 4096;
++		}
++	}
++
++	if(free) {
++		ClearPageReserved(virt_to_page((void *)n->page));
++		free_page(n->page);
++		list_del(&n->list);
++		kfree(n);
++	}
++
++	return vaddr;
++}
++
++static unsigned long map_node(struct pmd_node *n,unsigned int vaddr,unsigned int end)
++{
++	unsigned int *pte = (unsigned int *)n->page;
++	int index = ((vaddr & 0x3ff000) >> 12);
++	struct page * page = NULL;
++	unsigned long pfn = 0;
++
++
++	while(index < 1024 && vaddr < end) {
++		if(pte[index] == reserved_pte) {
++
++			mmap_write_lock(current->mm);
++
++			pfn = dmmu_v2pfn(vaddr) >> PAGE_SHIFT;
++			page = pfn_to_page(pfn);
++
++			SetPageReserved(page);
++
++			pte[index] = (pfn << PAGE_SHIFT) | DMMU_PTE_VLD;
++
++			mmap_write_unlock(current->mm);
++		} else {
++			pte[index] += MAP_COUNT;
++		}
++		index++;
++		vaddr += 4096;
++	}
++	n->count++;
++	return vaddr;
++}
++
++static struct pmd_node *find_node(struct dmmu_handle *h,unsigned int vaddr)
++{
++	struct list_head *pos, *next;
++	struct pmd_node *n;
++
++	list_for_each_safe(pos, next, &h->pmd_list) {
++		n = list_entry(pos, struct pmd_node, list);
++		if(n->index == (vaddr & 0xffc00000))
++			return n;
++	}
++	return NULL;
++}
++
++static struct pmd_node *add_node(struct dmmu_handle *h,unsigned int vaddr)
++{
++	int i;
++	unsigned long *pte;
++	unsigned long *pgd = (unsigned long *)h->pdg;
++	struct pmd_node *n = kmalloc(sizeof(*n),GFP_KERNEL);
++	INIT_LIST_HEAD(&n->list);
++	n->count = 0;
++	n->index = vaddr & 0xffc00000;
++	n->page = __get_free_page(GFP_KERNEL);
++	SetPageReserved(virt_to_page((void *)n->page));
++
++	pte = (unsigned long *)n->page;
++	for(i=0;i<1024;i++)
++		pte[i] = reserved_pte;
++
++	list_add(&n->list, &h->pmd_list);
++
++	pgd[vaddr>>22] = dmmu_v2pfn(n->page) | DMMU_PMD_VLD;
++//	printk(">>>>>>> n->page = %lx, pgd[vaddr>>22] = %lx <<<<<<<\n\n", n->page, pgd[vaddr>>22]);
++	return n;
++}
++
++static struct dmmu_handle *find_handle(void)
++{
++	struct list_head *pos, *next;
++	struct dmmu_handle *h;
++
++	list_for_each_safe(pos, next, &handle_list) {
++		h = list_entry(pos, struct dmmu_handle, list);
++		if(h->tgid == current->tgid)
++			return h;
++	}
++	return NULL;
++}
++
++/**
++* @brief unmap node from map list, clear each pmd_node in pmd_list,
++* 	Not free handle, let dmmu_unmap_all do it.
++*
++* @param h
++*
++* @return
++*/
++static int dmmu_unmap_node_unlock(struct dmmu_handle *h)
++{
++	struct map_node *cn;
++	struct list_head *pos, *next;
++
++	unsigned long vaddr;
++	int len;
++	unsigned long end;
++
++	struct pmd_node *node;
++
++	list_for_each_safe(pos, next, &h->map_list) {
++		/* find and delete a map node from map_list */
++		cn = list_entry(pos, struct map_node, list);
++		vaddr = cn->start;
++		len = cn->len;
++		end = vaddr + len;
++
++		while(vaddr < end) {
++			node = find_node(h,vaddr);
++			if(node)
++				vaddr = unmap_node(node,vaddr,end,1);
++		}
++
++		list_del(&cn->list);
++		kfree(cn);
++	}
++
++
++	return 0;
++
++}
++
++
++void dmmu_mm_release(struct mmu_notifier *mn,
++                struct mm_struct *mm)
++{
++	struct dmmu_handle *h = container_of(mn, struct dmmu_handle, mn);
++
++	printk("===== dmmu release mm (TODO: not checked) ====h: %p\n", h);
++
++	if(h->handle_mm != mm) {
++		return;
++	}
++
++	mutex_lock(&h->lock);
++
++	dmmu_mm_dev_release(h);
++
++	dmmu_unmap_node_unlock(h);
++
++	mutex_unlock(&h->lock);
++}
++
++static const struct mmu_notifier_ops dmmu_mm_notifier_ops = {
++        .release = dmmu_mm_release,
++};
++
++
++static struct dmmu_handle *create_handle(void)
++{
++	struct dmmu_handle *h;
++	unsigned int pgd_index;
++	unsigned long *pgd;
++
++	h = kmalloc(sizeof(struct dmmu_handle),GFP_KERNEL);
++	if(!h)
++		return NULL;
++
++	h->tgid = current->tgid;
++	h->pdg = __get_free_page(GFP_KERNEL);
++	if(!h->pdg) {
++		pr_err("%s %d, Get free page for PGD error\n",
++				__func__, __LINE__);
++		kfree(h);
++		return NULL;
++	}
++	SetPageReserved(virt_to_page((void *)h->pdg));
++
++	pgd = (unsigned long *)h->pdg;
++
++	for (pgd_index=0; pgd_index < PTRS_PER_PGD; pgd_index++)
++		pgd[pgd_index] = res_pte_paddr;
++
++	INIT_LIST_HEAD(&h->list);
++	INIT_LIST_HEAD(&h->pmd_list);
++	INIT_LIST_HEAD(&h->map_list);
++	INIT_LIST_HEAD(&h->dev_notifier_list);
++	mutex_init(&h->lock);
++
++	/* register exit_mmap notify */
++	h->handle_mm = current->mm;
++
++	h->mn.ops = &dmmu_mm_notifier_ops;
++
++	mmu_notifier_register(&h->mn, h->handle_mm);
++
++	list_add(&h->list, &handle_list);
++
++	return h;
++}
++
++static int dmmu_make_present(unsigned long addr,unsigned long end)
++{
++#if 0
++	unsigned long i;
++	for(i = addr; i < end; i += 4096) {
++		*(volatile unsigned char *)(i) = 0;
++	}
++	*(volatile unsigned char *)(end - 1) = 0;
++	return 0;
++#else
++	int ret, len, write;
++	struct vm_area_struct * vma;
++	unsigned long vm_page_prot;
++
++	mmap_write_lock(current->mm);
++	vma = find_vma(current->mm, addr);
++	if (!vma) {
++		printk("dmmu_make_present error. addr=%lx len=%lx\n",addr,end-addr);
++		mmap_write_unlock(current->mm);
++		return -1;
++	}
++
++	if(vma->vm_flags & VM_PFNMAP) {
++		mmap_write_unlock(current->mm);
++		return 0;
++	}
++	write = (vma->vm_flags & VM_WRITE) != 0;
++	BUG_ON(addr >= end);
++	BUG_ON(end > vma->vm_end);
++
++	vm_page_prot = pgprot_val(vma->vm_page_prot);
++	vma->vm_page_prot = __pgprot(vm_page_prot | _PAGE_VALID| _PAGE_ACCESSED | _PAGE_PRESENT);
++
++	len = DIV_ROUND_UP(end, PAGE_SIZE) - addr/PAGE_SIZE;
++	ret = get_user_pages(addr, len, write, NULL, NULL);
++	vma->vm_page_prot = __pgprot(vm_page_prot);
++	if (ret < 0) {
++		printk("dmmu_make_present get_user_pages error(%d). addr=%lx len=%lx\n",0-ret,addr,end-addr);
++		mmap_write_unlock(current->mm);
++		return ret;
++	}
++
++	mmap_write_unlock(current->mm);
++	return ret == len ? 0 : -1;
++#endif
++}
++
++static void dmmu_cache_wback(struct dmmu_handle *h)
++{
++	struct list_head *pos, *next;
++	struct pmd_node *n;
++
++	dma_cache_wback(h->pdg,PAGE_SIZE);
++
++	list_for_each_safe(pos, next, &h->pmd_list) {
++		n = list_entry(pos, struct pmd_node, list);
++		dma_cache_wback(n->page,PAGE_SIZE);
++	}
++}
++
++static void dmmu_dump_handle(struct seq_file *m, void *v, struct dmmu_handle *h);
++
++unsigned long dmmu_map(struct device *dev,unsigned long vaddr,unsigned long len)
++{
++	int end = vaddr + len;
++	struct dmmu_handle *h;
++	struct pmd_node *node;
++
++	h = find_handle();
++	if(!h)
++		h = create_handle();
++	if(!h)
++		return 0;
++
++	mutex_lock(&h->lock);
++#ifdef DEBUG
++	printk("(pid %d)dmmu_map %lx %lx================================================\n",h->tgid,vaddr,len);
++#endif
++	if(check_map(h,vaddr,len))
++	{
++		mutex_unlock(&h->lock);
++		return dmmu_v2pfn(h->pdg);
++	}
++
++	if(dmmu_make_present(vaddr,vaddr+len))
++	{
++		mutex_unlock(&h->lock);
++		return 0;
++	}
++
++	handle_add_map(dev,h,vaddr,len);
++
++	while(vaddr < end) {
++		node = find_node(h,vaddr);
++		if(!node) {
++			node = add_node(h,vaddr);
++		}
++		vaddr = map_node(node,vaddr,end);
++	}
++	dmmu_cache_wback(h);
++#ifdef DEBUG
++	dmmu_dump_handle(NULL,NULL,h);
++#endif
++	mutex_unlock(&h->lock);
++
++	return dmmu_v2pfn(h->pdg);
++}
++EXPORT_SYMBOL(dmmu_map);
++
++static int dmmu_mm_dev_release(struct dmmu_handle *h)
++{
++	struct dmmu_mm_notifier *n = NULL;
++	struct list_head *pos, *next;
++
++	list_for_each_safe(pos, next, &h->dev_notifier_list) {
++		n = list_entry(pos, struct dmmu_mm_notifier, list);
++		if(n && n->ops && n->ops->mm_release) {
++			n->ops->mm_release(n->data);
++		}
++
++		list_del(&n->list);
++	}
++
++
++	return 0;
++}
++
++
++int dmmu_register_mm_notifier(struct dmmu_mm_notifier *dmn)
++{
++	int dev_already_registered = 0;
++	struct dmmu_mm_notifier *n = NULL;
++	struct dmmu_handle *h;
++	struct list_head *pos, *next;
++
++	h = find_handle();
++	if(!h) {
++		return -EINVAL;
++	}
++
++	mutex_lock(&h->lock);
++
++	list_for_each_safe(pos, next, &h->dev_notifier_list) {
++		n = list_entry(pos, struct dmmu_mm_notifier, list);
++
++		if(n == dmn) {
++			/* already in dev_notifier_list*/
++			dev_already_registered = 1;
++		}
++
++	}
++
++	if(dev_already_registered) {
++		goto out;
++	}
++
++	list_add_tail(&dmn->list, &h->dev_notifier_list);
++out:
++	mutex_unlock(&h->lock);
++	return 0;
++}
++EXPORT_SYMBOL(dmmu_register_mm_notifier);
++
++int dmmu_unmap(struct device *dev,unsigned long vaddr, int len)
++{
++	unsigned long end = vaddr + len;
++	struct dmmu_handle *h;
++	struct pmd_node *node;
++	struct map_node *n;
++
++	h = find_handle();
++	if(!h) {
++		return 0;
++	}
++
++	mutex_lock(&h->lock);
++#ifdef DEBUG
++	/*This printk can cause a memory leak. */
++	printk("dmmu_unmap %lx %x**********************************************\n",vaddr,len);
++#endif
++	n = check_map(h,vaddr,len);
++	if(!n) {
++		mutex_unlock(&h->lock);
++		return -EAGAIN;
++	}
++	if(n->dev != dev) {
++		mutex_unlock(&h->lock);
++		return -EAGAIN;
++	}
++
++	list_del(&n->list);
++	kfree(n);
++
++	while(vaddr < end) {
++		node = find_node(h,vaddr);
++		if(node)
++			vaddr = unmap_node(node,vaddr,end,1);
++	}
++
++	if(list_empty(&h->pmd_list) && list_empty(&h->map_list)) {
++		list_del(&h->list);
++		ClearPageReserved(virt_to_page((void *)h->pdg));
++		free_page(h->pdg);
++		mutex_unlock(&h->lock);
++
++		mmu_notifier_unregister(&h->mn, h->handle_mm);
++
++		kfree(h);
++		return 0;
++	}
++
++	mutex_unlock(&h->lock);
++	return 0;
++}
++EXPORT_SYMBOL(dmmu_unmap);
++
++int dmmu_free_all(struct device *dev)
++{
++	struct dmmu_handle *h;
++	struct pmd_node *node;
++	struct map_node *cn;
++	struct list_head *pos, *next;
++
++	h = find_handle();
++	if(!h)
++		return 0;
++
++	mutex_lock(&h->lock);
++
++	list_for_each_safe(pos, next, &h->map_list) {
++		cn = list_entry(pos, struct map_node, list);
++		node = find_node(h,cn->start);
++		if(node)
++			unmap_node(node,cn->start,cn->len,1);
++		list_del(&cn->list);
++		kfree(cn);
++	}
++
++	list_for_each_safe(pos, next, &h->pmd_list) {
++		node = list_entry(pos, struct pmd_node, list);
++		if(node){
++			printk("WARN: pmd list should NULL\n");
++			unmap_node(node,0,0,0);
++		}
++	}
++
++	list_del(&h->list);
++	ClearPageReserved(virt_to_page((void *)h->pdg));
++	free_page(h->pdg);
++
++	mutex_unlock(&h->lock);
++	mmu_notifier_unregister(&h->mn, h->handle_mm);
++	kfree(h);
++	return 0;
++}
++
++/**
++* @brief release all resources, which should be called by driver close
++*
++* @param dev
++*
++* @return
++*/
++int dmmu_unmap_all(struct device *dev)
++{
++	struct dmmu_handle *h;
++	struct map_node *cn;
++	struct list_head *pos, *next;
++
++#ifdef DEBUG
++	printk("dmmu_unmap_all\n");
++#endif
++
++	h = find_handle();
++	if(!h) {
++		printk("dmmu unmap all not find hindle, maybe it has benn freed already, name: %s\n", dev->kobj.name);
++		return 0;
++	}
++
++	list_for_each_safe(pos, next, &h->map_list) {
++		cn = list_entry(pos, struct map_node, list);
++		if(dev == cn->dev) {
++			dmmu_unmap(dev,cn->start,cn->len);
++		}
++	}
++
++
++	if(list_empty(&h->map_list))
++		dmmu_free_all(dev);
++	return 0;
++}
++EXPORT_SYMBOL(dmmu_unmap_all);
++int __init dmmu_init(void)
++{
++	unsigned int pte_index;
++	unsigned long res_page_paddr;
++	unsigned long reserved_page;
++	unsigned int *res_pte_vaddr;
++
++	reserved_page = __get_free_page(GFP_KERNEL);
++	if (!reserved_page) {
++		pr_err("%s %d, Get reserved page error\n",
++				__func__, __LINE__);
++		return ENOMEM;
++	}
++	SetPageReserved(virt_to_page((void *)reserved_page));
++	reserved_pte = dmmu_v2pfn(reserved_page) | DMMU_PTE_VLD;
++
++	res_page_paddr = virt_to_phys((void *)reserved_page) | 0xFFF;
++
++	res_pte_vaddr = (unsigned int *)__get_free_page(GFP_KERNEL);
++	if (!res_pte_vaddr) {
++		pr_err("%s %d, Get free page for PTE error\n",
++				__func__, __LINE__);
++		free_page(reserved_page);
++		return ENOMEM;
++	}
++	SetPageReserved(virt_to_page(res_pte_vaddr));
++	res_pte_paddr = virt_to_phys((void *)res_pte_vaddr) | DMMU_PTE_VLD;
++
++	for (pte_index = 0; pte_index < PTRS_PER_PTE; pte_index++)
++		res_pte_vaddr[pte_index] = res_page_paddr;
++	printk("%s %d PTRS_PER_PTE = %lu\n",__func__,__LINE__,PTRS_PER_PTE);
++
++	return 0;
++}
++arch_initcall(dmmu_init);
++
++void dmmu_dump_vaddr(unsigned long vaddr)
++{
++	struct dmmu_handle *h;
++	struct pmd_node *node;
++
++	unsigned long *pmd,*pte;
++	h = find_handle();
++	if(!h) {
++		printk("dmmu_dump_vaddr %08lx error - h not found!\n",vaddr);
++		return;
++	}
++
++	node = find_node(h,vaddr);
++	if(!node) {
++		printk("dmmu_dump_vaddr %08lx error - node not found!\n",vaddr);
++		return;
++	}
++
++	pmd = (unsigned long *)h->pdg;
++	pte = (unsigned long *)node->page;
++
++	printk("pmd base = %p; pte base = %p\n",pmd,pte);
++	printk("pmd = %08lx; pte = %08lx\n",pmd[vaddr>>22],pte[(vaddr&0x3ff000)>>12]);
++}
++
++static void dmmu_dump_handle(struct seq_file *m, void *v, struct dmmu_handle *h)
++{
++	struct list_head *pos, *next;
++	struct map_node *n;
++
++	list_for_each_safe(pos, next, &h->map_list) {
++		n = list_entry(pos, struct map_node, list);
++		{
++			int i = 0;
++			int vaddr = n->start;
++			struct pmd_node *pn = find_node(h,vaddr);
++			unsigned int *pte = (unsigned int *)pn->page;
++
++			while(vaddr < (n->start + n->len)) {
++				if(i++%8 == 0)
++					printk("\nvaddr %08x : ",vaddr & 0xfffff000);
++				printk("%08x ",pte[(vaddr & 0x3ff000)>>12]);
++				vaddr += 4096;
++			}
++			printk("\n\n");
++		}
++	}
++}
++
++static int dmmu_proc_show(struct seq_file *m, void *v)
++{
++	struct list_head *pos, *next;
++	struct dmmu_handle *h;
++	volatile unsigned long flags;
++	local_irq_save(flags);
++		list_for_each_safe(pos, next, &handle_list) {
++			h = list_entry(pos, struct dmmu_handle, list);
++			dmmu_dump_handle(m, v, h);
++		}
++	local_irq_restore(flags);
++	return 0;
++}
++
++static int dmmu_open(struct inode *inode, struct file *file)
++{
++	return single_open(file, dmmu_proc_show, PDE_DATA(inode));
++}
++
++static const struct proc_ops dmmus_proc_fops ={
++	.proc_read = seq_read,
++	.proc_open = dmmu_open,
++	.proc_lseek = seq_lseek,
++	.proc_release = single_release,
++};
++
++static int __init init_dmmu_proc(void)
++{
++	struct proc_dir_entry *p;
++	p = jz_proc_mkdir("dmmu");
++	if (!p) {
++		printk("create_proc_entry for common dmmu failed.\n");
++		return -ENODEV;
++	}
++	proc_create("dmmus", 0600,p,&dmmus_proc_fops);
++
++	return 0;
++}
++
++module_init(init_dmmu_proc);
+diff --git a/arch/mips/xburst2/soc-x2500/pm.c b/arch/mips/xburst2/soc-x2500/pm.c
+new file mode 100644
+index 000000000..835f43e16
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/pm.c
+@@ -0,0 +1,608 @@
++#include <linux/init.h>
++#include <linux/pm.h>
++#include <linux/suspend.h>
++
++#include <soc/cache.h>
++#include <soc/base.h>
++#include <asm/io.h>
++#include <soc/ddr.h>
++#include <soc/base.h>
++#include <soc/cpm.h>
++#include "pm.h"
++
++
++#define DDR_DEEP_SLEEP
++
++#ifdef DEBUG_PM
++static void x2500_pm_gate_check(void)
++{
++	unsigned int gate0 = cpm_inl(CPM_CLKGR);
++	unsigned int gate1 = cpm_inl(CPM_CLKGR1);
++	int i;
++	int x;
++
++	printk("gate0 = 0x%08x\n", gate0);
++	printk("gate1 = 0x%08x\n", gate1);
++	for (i = 0; i < 32; i++) {
++		x = (gate0 >> i) & 1;
++		if (x == 0)
++			printk("warning : bit[%d] in clk gate0 is enabled\n", i);
++	}
++	for (i = 0; i < 16; i++) {
++		x = (gate1 >> i) & 1;
++		if (x == 0)
++			printk("warning : bit[%d] in clk gate1 is enabled\n", i);
++	}
++
++}
++#endif
++
++
++
++#ifdef DDR_DEEP_SLEEP
++static void ddrp_auto_calibration(void)
++{
++	unsigned int timeout = 0xffffff;
++
++	serial_put_hex(*(volatile unsigned int *)(0xb3011000 + (0x74 << 2)));
++	serial_put_hex(*(volatile unsigned int *)(0xb3011000 + (0x75 << 2)));
++	serial_put_hex(*(volatile unsigned int *)(0xb3011000 + (0xa4 << 2)));
++	serial_put_hex(*(volatile unsigned int *)(0xb3011000 + (0xa5 << 2)));
++
++	timeout = 0xffffff;
++	ddr_writel(0xa1, DDRP_INNOPHY_TRAINING_CTRL);
++
++	while(!((ddr_readl(DDRP_INNOPHY_CALIB_DONE) & 0xf) == 0xf) && --timeout) {
++		TCSM_PCHAR('t');
++	}
++
++	if(!timeout) {
++		TCSM_PCHAR('f');
++	}
++
++	ddr_writel(0xa0, DDRP_INNOPHY_TRAINING_CTRL);
++
++	serial_put_hex(*(volatile unsigned int *)(0xb3011000 + (0x74 << 2)));
++	serial_put_hex(*(volatile unsigned int *)(0xb3011000 + (0x75 << 2)));
++	serial_put_hex(*(volatile unsigned int *)(0xb3011000 + (0xa4 << 2)));
++	serial_put_hex(*(volatile unsigned int *)(0xb3011000 + (0xa5 << 2)));
++#if 1
++	{
++		unsigned int cycsel, tmp;
++		unsigned int read_data0, read_data1;
++		unsigned int read_data2, read_data3;
++		unsigned int c0, c1, c2, c3;
++		unsigned int max;
++
++		read_data0 = *(volatile unsigned int *)(0xb3011000 + (0x74 << 2));
++		read_data1 = *(volatile unsigned int *)(0xb3011000 + (0x75 << 2));
++		read_data2 = *(volatile unsigned int *)(0xb3011000 + (0xa4 << 2));
++		read_data3 = *(volatile unsigned int *)(0xb3011000 + (0xa5 << 2));
++		c0 = (read_data0 >> 4) & 0x7;
++		c1 = (read_data1 >> 4) & 0x7;
++		c2 = (read_data0 >> 4) & 0x7;
++		c3 = (read_data1 >> 4) & 0x7;
++
++		max = max(max(c0, c1), max(c2, c3));
++
++		cycsel = max + 3;
++
++		tmp = *(volatile unsigned int *)(0xb3011000 + (0xa << 2));
++		tmp &= ~(7 << 1);
++		tmp |= cycsel << 1;
++		*(volatile unsigned int *)(0xb3011000 + (0xa << 2)) = tmp;
++
++
++		tmp = *(volatile unsigned int *)(0xb3011000 + 0x4);
++		tmp |= 1 << 6;
++		*(volatile unsigned int *)(0xb3011000 + (0x1 << 2)) = tmp;
++		TCSM_PCHAR('C');
++	}
++#endif
++}
++
++static void ddrp_hs_config(void)
++{
++
++	/* odt */
++	reg_ddr_phy(0xb0) = 0xf;
++	reg_ddr_phy(0xb1) = 0xf;
++	reg_ddr_phy(0xb2) = 0x11;
++	reg_ddr_phy(0xb3) = 0x11;
++
++	reg_ddr_phy(0xc0) = 0x3;
++	reg_ddr_phy(0xc1) = 0x3;
++	reg_ddr_phy(0xd0) = 0x3;
++	reg_ddr_phy(0xd1) = 0x3;
++	reg_ddr_phy(0xe0) = 0x3;
++	reg_ddr_phy(0xe1) = 0x3;
++	reg_ddr_phy(0xf0) = 0x3;
++	reg_ddr_phy(0xf1) = 0x3;
++
++	reg_ddr_phy(0xc2) = 0x11;
++	reg_ddr_phy(0xc3) = 0x11;
++	reg_ddr_phy(0xd2) = 0x11;
++	reg_ddr_phy(0xd3) = 0x11;
++	reg_ddr_phy(0xe2) = 0x11;
++	reg_ddr_phy(0xe3) = 0x11;
++	reg_ddr_phy(0xf2) = 0x11;
++	reg_ddr_phy(0xf3) = 0x11;
++
++	/* dll */
++	reg_ddr_phy(0x15) = 0xc;
++	reg_ddr_phy(0x16) = 0x1;
++
++	reg_ddr_phy(0x54) = 0xc;
++	reg_ddr_phy(0x64) = 0xc;
++	reg_ddr_phy(0x84) = 0xc;
++	reg_ddr_phy(0x94) = 0xc;
++
++	reg_ddr_phy(0x55) = 0x1;
++	reg_ddr_phy(0x65) = 0x1;
++	reg_ddr_phy(0x85) = 0x1;
++	reg_ddr_phy(0x95) = 0x1;
++
++	/* skew */
++	reg_ddr_phy(0x100 + 0x0) = 0x8;
++	reg_ddr_phy(0x100 + 0x1) = 0x8;
++	reg_ddr_phy(0x100 + 0x2) = 0x8;
++	reg_ddr_phy(0x100 + 0x3) = 0x8;
++	reg_ddr_phy(0x100 + 0x4) = 0x8;
++	reg_ddr_phy(0x100 + 0x5) = 0x8;
++	reg_ddr_phy(0x100 + 0x6) = 0x8;
++	reg_ddr_phy(0x100 + 0x7) = 0x8;
++	reg_ddr_phy(0x100 + 0x8) = 0x8;
++	reg_ddr_phy(0x100 + 0x9) = 0x8;
++	reg_ddr_phy(0x100 + 0xa) = 0x8;
++	reg_ddr_phy(0x100 + 0xb) = 0x8;
++	reg_ddr_phy(0x100 + 0xc) = 0x8;
++	reg_ddr_phy(0x100 + 0xd) = 0x8;
++	reg_ddr_phy(0x100 + 0xe) = 0x8;
++	reg_ddr_phy(0x100 + 0xf) = 0x8;
++	reg_ddr_phy(0x100 + 0x10) = 0x8;
++	reg_ddr_phy(0x100 + 0x11) = 0x8;
++	reg_ddr_phy(0x100 + 0x12) = 0x8;
++	reg_ddr_phy(0x100 + 0x13) = 0x8;
++	reg_ddr_phy(0x100 + 0x14) = 0x8;
++	reg_ddr_phy(0x100 + 0x15) = 0x8;
++	reg_ddr_phy(0x100 + 0x16) = 0x8;
++	reg_ddr_phy(0x100 + 0x17) = 0x8;
++	reg_ddr_phy(0x100 + 0x18) = 0x8;
++	reg_ddr_phy(0x100 + 0x19) = 0x8;
++	reg_ddr_phy(0x100 + 0x1a) = 0x8;
++	reg_ddr_phy(0x100 + 0x1b) = 0x8;
++	reg_ddr_phy(0x100 + 0x1c) = 0x8;
++	reg_ddr_phy(0x100 + 0x1d) = 0x8;
++	reg_ddr_phy(0x100 + 0x1e) = 0x8;
++
++	reg_ddr_phy(0x100 + 0x16) = 0x8;
++	reg_ddr_phy(0x100 + 0x17) = 0x8;
++
++	reg_ddr_phy(0x120 + 0x0) = 0x8;
++	reg_ddr_phy(0x120 + 0x1) = 0x8;
++	reg_ddr_phy(0x120 + 0x2) = 0x8;
++	reg_ddr_phy(0x120 + 0x3) = 0x8;
++	reg_ddr_phy(0x120 + 0x4) = 0x8;
++	reg_ddr_phy(0x120 + 0x5) = 0x8;
++	reg_ddr_phy(0x120 + 0x6) = 0x8;
++	reg_ddr_phy(0x120 + 0x7) = 0x8;
++	reg_ddr_phy(0x120 + 0x8) = 0x8;
++	reg_ddr_phy(0x120 + 0xb) = 0x8;
++	reg_ddr_phy(0x120 + 0xc) = 0x8;
++	reg_ddr_phy(0x120 + 0xd) = 0x8;
++	reg_ddr_phy(0x120 + 0xe) = 0x8;
++	reg_ddr_phy(0x120 + 0xf) = 0x8;
++	reg_ddr_phy(0x120 + 0x10) = 0x8;
++	reg_ddr_phy(0x120 + 0x11) = 0x8;
++	reg_ddr_phy(0x120 + 0x12) = 0x8;
++	reg_ddr_phy(0x120 + 0x13) = 0x8;
++
++	reg_ddr_phy(0x1a0 + 0x0) = 0x8;
++	reg_ddr_phy(0x1a0 + 0x1) = 0x8;
++	reg_ddr_phy(0x1a0 + 0x2) = 0x8;
++	reg_ddr_phy(0x1a0 + 0x3) = 0x8;
++	reg_ddr_phy(0x1a0 + 0x4) = 0x8;
++	reg_ddr_phy(0x1a0 + 0x5) = 0x8;
++	reg_ddr_phy(0x1a0 + 0x6) = 0x8;
++	reg_ddr_phy(0x1a0 + 0x7) = 0x8;
++	reg_ddr_phy(0x1a0 + 0x8) = 0x8;
++	reg_ddr_phy(0x1a0 + 0xb) = 0x8;
++	reg_ddr_phy(0x1a0 + 0xc) = 0x8;
++	reg_ddr_phy(0x1a0 + 0xd) = 0x8;
++	reg_ddr_phy(0x1a0 + 0xe) = 0x8;
++	reg_ddr_phy(0x1a0 + 0xf) = 0x8;
++	reg_ddr_phy(0x1a0 + 0x10) = 0x8;
++	reg_ddr_phy(0x1a0 + 0x11) = 0x8;
++	reg_ddr_phy(0x1a0 + 0x12) = 0x8;
++	reg_ddr_phy(0x1a0 + 0x13) = 0x8;
++
++
++	reg_ddr_phy(2) |= 0x8;
++}
++
++#endif
++
++
++
++static void load_func_to_tcsm(unsigned int *tcsm_addr,unsigned int *f_addr,unsigned int size)
++{
++	unsigned int instr;
++	int offset;
++	int i;
++#ifdef DEBUG_PM
++	printk("tcsm addr = %p %p size = %d\n",tcsm_addr,f_addr,size);
++#endif
++	for(i = 0;i < size / 4;i++) {
++		instr = f_addr[i];
++		if((instr >> 26) == 2){
++			offset = instr & 0x3ffffff;
++			offset = (offset << 2) - ((unsigned int)f_addr & 0xfffffff);
++			if(offset > 0) {
++				offset = ((unsigned int)tcsm_addr & 0xfffffff) + offset;
++				instr = (2 << 26) | (offset >> 2);
++			}
++		}
++		tcsm_addr[i] = instr;
++	}
++}
++
++
++static int soc_pm_idle(void)
++{
++	unsigned int lcr = cpm_inl(CPM_LCR);
++	unsigned int opcr = cpm_inl(CPM_OPCR);
++
++	lcr &=~ 0x3; // low power mode: IDLE
++	cpm_outl(lcr, CPM_LCR);
++
++	opcr &= ~(1 << 30);
++	opcr &= ~(1 << 31);
++	cpm_outl(opcr, CPM_OPCR);
++
++	return 0;
++}
++
++static int soc_pm_sleep(void)
++{
++	unsigned int lcr = cpm_inl(CPM_LCR);
++	unsigned int opcr = cpm_inl(CPM_OPCR);
++
++	lcr &=~ 0x3;
++	lcr |= 1 << 0; // low power mode: SLEEP
++	cpm_outl(lcr, CPM_LCR);
++
++	opcr &= ~(1 << 31);
++	opcr |= (1 << 30);
++	opcr |= (1 << 4); // exclk enable;
++	opcr &= ~(1 << 24);
++	cpm_outl(opcr, CPM_OPCR);
++
++	return 0;
++}
++
++static int soc_post_wakeup(void)
++{
++	unsigned int lcr = cpm_inl(CPM_LCR);
++	lcr &= ~0x3; // low power mode: IDLE
++	cpm_outl(lcr, CPM_LCR);
++
++	printk("post wakeup!\n");
++
++
++	return 0;
++}
++
++static noinline void cpu_resume_bootup(void)
++{
++
++	TCSM_PCHAR('X');
++	/* set reset entry */
++	*(volatile unsigned int *)0xb2200f00 = 0xbfc00000;
++
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"move $29, %0	\n\t"
++		"jr.hb   %1	\n\t"
++		"nop		\n\t"
++		".set pop	\n\t"
++		:
++		:"r" (SLEEP_CPU_RESUME_SP), "r"(SLEEP_CPU_RESUME_TEXT)
++		:
++		);
++
++}
++#define reg_ddr_phy(x)   (*(volatile unsigned int *)(0xb3011000 + ((x) << 2)))
++static noinline void cpu_resume(void)
++{
++	unsigned int ddrc_ctrl;
++
++	TCSM_PCHAR('R');
++
++	if (sleep_param->state == PM_SUSPEND_MEM) {
++#ifdef DDR_DEEP_SLEEP
++		int tmp;
++
++		/* enable pll */
++		tmp = reg_ddr_phy(0x21);
++		tmp &= ~(1 << 1);
++		reg_ddr_phy(0x21) = tmp;
++
++		while (!(reg_ddr_phy(0x42) & 0x8))
++			serial_put_hex(reg_ddr_phy(0x42));
++#endif
++
++		/* dfi_init_start = 0, wait dfi_init_complete */
++		*(volatile unsigned int *)0xb3012000 &= ~(1 << 3);
++		while(!(*(volatile unsigned int *)0xb3012004 & 0x1));
++
++#ifdef DDR_DEEP_SLEEP
++		/* bufferen_core = 1 */
++		*(volatile unsigned int *)0xb3012000 &= ~(1 << 4);
++
++#endif
++
++		ddrc_ctrl = ddr_readl(DDRC_CTRL);
++		ddrc_ctrl &= ~(1<<5);
++		ddrc_ctrl |= (1<<1);
++		ddr_writel(ddrc_ctrl, DDRC_CTRL);
++
++		while(ddr_readl(DDRC_STATUS) & (1<<2));
++		while(REG32(DDRC_DWSTATUS) & (1<<4));
++
++		TCSM_DELAY(1000);
++		TCSM_PCHAR('1');
++#ifdef DDR_DEEP_SLEEP
++		ddrp_hs_config();
++		ddrp_auto_calibration();
++#endif
++		TCSM_PCHAR('2');
++
++		/* restore ddr auto-sr */
++		ddr_writel(sleep_param->autorefresh, DDRC_AUTOSR_EN);
++		TCSM_PCHAR('3');
++
++		/* restore ddr LPEN */
++		ddr_writel(sleep_param->dlp, DDRC_DLP);
++
++		/* restore ddr deep power down state */
++		ddrc_ctrl = ddr_readl(DDRC_CTRL);
++		ddrc_ctrl |= sleep_param->pdt;
++		ddrc_ctrl |= sleep_param->dpd;
++		ddr_writel(ddrc_ctrl, DDRC_CTRL);
++
++		TCSM_PCHAR('4');
++	}
++
++
++	TCSM_PCHAR('5');
++
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"jr.hb %0	\n\t"
++		"nop		\n\t"
++		".set pop 	\n\t"
++		:
++		: "r" (restore_goto)
++		:
++		);
++}
++
++
++static noinline void cpu_sleep(void)
++{
++
++
++	sleep_param->cpu_div = cpm_inl(CPM_CPCCR) & 0xf;
++
++	blast_dcache32();
++	blast_scache64();
++	__sync();
++	__fast_iob();
++
++
++	TCSM_PCHAR('D');
++
++	if (sleep_param->state == PM_SUSPEND_MEM) {
++		unsigned int tmp;
++		unsigned int ddrc_ctrl;
++
++		ddrc_ctrl = ddr_readl(DDRC_CTRL);
++
++		/* save ddr low power state */
++		sleep_param->pdt = ddrc_ctrl & DDRC_CTRL_PDT_MASK;
++		sleep_param->dpd = ddrc_ctrl & DDRC_CTRL_DPD;
++		sleep_param->dlp = ddr_readl(DDRC_DLP);
++		sleep_param->autorefresh = ddr_readl(DDRC_AUTOSR_EN);
++
++		/* ddr disable deep power down */
++		ddrc_ctrl &= ~(DDRC_CTRL_PDT_MASK);
++		ddrc_ctrl &= ~(DDRC_CTRL_DPD);
++		ddr_writel(ddrc_ctrl, DDRC_CTRL);
++
++		/* ddr diasble LPEN*/
++		ddr_writel(0, DDRC_DLP);
++
++		/* ddr disable auto-sr */
++		ddr_writel(0, DDRC_AUTOSR_EN);
++		tmp = *(volatile unsigned int *)0xa0000000;
++
++
++
++		/* DDR self refresh, */
++		ddrc_ctrl = ddr_readl(DDRC_CTRL);
++		ddrc_ctrl |= 1 << 5;
++		ddrc_ctrl &= ~(1 << 1);
++		ddr_writel(ddrc_ctrl, DDRC_CTRL);
++		while(!(ddr_readl(DDRC_STATUS) & (1<<2)));
++		while(!(REG32(DDRC_DWSTATUS) & (1<<4)));
++
++#ifdef DDR_DEEP_SLEEP
++		/* bufferen_core = 0 */
++		*(volatile unsigned int *)0xb3012000 |= (1 << 4);
++#endif
++
++		/* dfi_init_start = 1 */
++		*(volatile unsigned int *)0xb3012000 |= (1 << 3);
++
++		{
++			int i;
++			for (i = 0; i < 4; i++) {
++
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++				__asm__ volatile("ssnop\t\n");
++			}
++		}
++
++#ifdef DDR_DEEP_SLEEP
++		/* disable pll */
++		reg_ddr_phy(0x21) |= (1 << 1);
++#endif
++	}
++
++
++	TCSM_PCHAR('W');
++
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"wait		\n\t"
++		"nop		\n\t"
++		"nop		\n\t"
++		"nop		\n\t"
++		".set pop	\n\t"
++	);
++
++	TCSM_PCHAR('N');
++
++	TCSM_PCHAR('\r');
++	TCSM_PCHAR('\n');
++	TCSM_PCHAR('?');
++	TCSM_PCHAR('?');
++	TCSM_PCHAR('?');
++	TCSM_PCHAR('\r');
++	TCSM_PCHAR('\n');
++
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"jr.hb %0	\n\t"
++		"nop		\n\t"
++		".set pop 	\n\t"
++		:
++		: "r" (SLEEP_CPU_RESUME_BOOTUP_TEXT)
++		:
++		);
++	TCSM_PCHAR('F');
++}
++
++
++int x2500_pm_enter(suspend_state_t state)
++{
++	extern volatile u8 *uart_base;
++
++	printk("x2500 pm enter!!\n");
++
++	sleep_param->uart_base = (unsigned int)uart_base;
++
++	sleep_param->state = state;
++
++#ifdef DEBUG_PM
++	printk("sleep_param->state addr =  %d\n", sleep_param->state);
++#endif
++
++	load_func_to_tcsm((unsigned int *)SLEEP_CPU_RESUME_BOOTUP_TEXT, (unsigned int *)cpu_resume_bootup, SLEEP_CPU_RESUME_BOOTUP_LEN);
++	load_func_to_tcsm((unsigned int *)SLEEP_CPU_RESUME_TEXT, (unsigned int *)cpu_resume, SLEEP_CPU_RESUME_LEN);
++	load_func_to_tcsm((unsigned int *)SLEEP_CPU_SLEEP_TEXT, (unsigned int *)cpu_sleep, SLEEP_CPU_SLEEP_LEN);
++
++	if (state == PM_SUSPEND_STANDBY) {
++		soc_pm_idle();
++	} else if (state == PM_SUSPEND_MEM) {
++		soc_pm_sleep();
++	} else {
++		printk("WARNING : unsupport pm suspend state\n");
++	}
++
++
++	/* set reset entry */
++	*(volatile unsigned int *)0xb2200f00 = SLEEP_CPU_RESUME_BOOTUP_TEXT;
++
++
++#ifdef DEBUG_PM
++	printk("LCR: %08x\n", cpm_inl(CPM_LCR));
++	printk("OPCR: %08x\n", cpm_inl(CPM_OPCR));
++	x2500_pm_gate_check();
++#endif
++
++	mb();
++	save_goto((unsigned int)SLEEP_CPU_SLEEP_TEXT);
++	mb();
++
++	soc_post_wakeup();
++
++	return 0;
++}
++
++static int x2500_pm_begin(suspend_state_t state)
++{
++	printk("x2500 suspend begin\n");
++	return 0;
++}
++
++static void x2500_pm_end(void)
++{
++	printk("x2500 pm end!\n");
++}
++
++static int x2500_suspend_prepare(void)
++{
++	printk("x2500 suspend prepare\n");
++	return 0;
++}
++
++static void x2500_suspend_finish(void)
++{
++	printk("x2500 suspend finish\n");
++}
++
++static int ingenic_pm_valid(suspend_state_t state)
++{
++	switch (state) {
++		case PM_SUSPEND_ON:
++		case PM_SUSPEND_STANDBY:
++		case PM_SUSPEND_MEM:
++			return 1;
++
++		default:
++			return 0;
++	}
++}
++static const struct platform_suspend_ops x2500_pm_ops = {
++	.valid		= ingenic_pm_valid,
++	.begin		= x2500_pm_begin,
++	.enter		= x2500_pm_enter,
++	.end		= x2500_pm_end,
++	.prepare	= x2500_suspend_prepare,
++	.finish		= x2500_suspend_finish,
++};
++
++/*
++ * Initialize suspend interface
++ */
++static int __init pm_init(void)
++{
++
++	suspend_set_ops(&x2500_pm_ops);
++
++
++	return 0;
++}
++
++late_initcall(pm_init);
+diff --git a/arch/mips/xburst2/soc-x2500/pm.h b/arch/mips/xburst2/soc-x2500/pm.h
+new file mode 100644
+index 000000000..b53f7dcd8
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/pm.h
+@@ -0,0 +1,136 @@
++
++
++
++struct sleep_param {
++	suspend_state_t state;
++	unsigned int pdt;
++	unsigned int dpd;
++	unsigned int dlp;
++	unsigned int autorefresh;
++	unsigned int cpu_div;
++	unsigned int uart_base;
++};
++
++
++/*
++ *
++ *	|-----------------------|
++ *	|			|
++ *	|			|
++ *	|	RESUME_SP	|
++ *	|			|
++ *	|-----------------------|
++ *	|			|
++ *	|  	  PARAM		|
++ *	|			|
++ *	|-----------------------|
++ *	|			|
++ *	|			|
++ *	|	SLEEP_TEXT      |
++ *	|			|
++ *	|			|
++ *	|-----------------------|
++ *	|			|
++ *	|			|
++ *	|	RESUME_TEXT	|
++ *	|			|
++ *	|			|
++ *	|-----------------------|
++ *	|			|
++*	|  RESUME_BOOTU_TEXTP	|
++ *	|			|
++ *	|-----------------------|     <------------ TCSM_START 0xb2400000
++ *
++ */
++
++
++#define SLEEP_MEMORY_START		0xb2400000
++#define SLEEP_MEMORY_END		0xb2407ff8
++#define SLEEP_RESUME_SP			SLEEP_MEMORY_END
++#define SLEEP_RESUME_BOOTUP_TEXT	SLEEP_MEMORY_START
++
++#define SLEEP_CPU_RESUME_BOOTUP_TEXT	SLEEP_RESUME_BOOTUP_TEXT
++#define SLEEP_CPU_RESUME_BOOTUP_LEN	64 // 16 instructions
++#define SLEEP_CPU_RESUME_TEXT		(SLEEP_CPU_RESUME_BOOTUP_TEXT + SLEEP_CPU_RESUME_BOOTUP_LEN)
++#define SLEEP_CPU_RESUME_LEN		(4096)
++#define SLEEP_CPU_SLEEP_TEXT		(SLEEP_CPU_RESUME_TEXT + SLEEP_CPU_RESUME_LEN)
++#define SLEEP_CPU_SLEEP_LEN		(3072)
++#define SLEEP_CPU_PARAM_ADDR		(SLEEP_CPU_SLEEP_TEXT + SLEEP_CPU_SLEEP_LEN)
++#define SLEEP_CPU_PARAM_SIZE		(sizeof(struct sleep_param))
++#define SLEEP_CPU_RESUME_SP		SLEEP_RESUME_SP
++
++#define sleep_param ((struct sleep_param *)SLEEP_CPU_PARAM_ADDR)
++
++
++
++extern long long save_goto(unsigned int func);
++extern int restore_goto(unsigned int func);
++
++
++#define reg_ddr_phy(x)   (*(volatile unsigned int *)(0xb3011000 + ((x) << 2)))
++
++#define rtc_read_reg(reg) ({ \
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) ); \
++	*(volatile unsigned int *)reg;\
++})
++
++#define rtc_write_reg(reg, val) do{ \
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) ); \
++	*(volatile unsigned int *)0xb000303c = 0xa55a; \
++	while (!((*(volatile unsigned int *)0xb000303c >> 31) & 0x1) ); \
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) ); \
++	*(volatile unsigned int *)reg = val; \
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) ); \
++}while(0)
++
++
++
++
++/************************************************
++ *		debug interface
++ ***********************************************/
++
++#define DEBUG_PM
++#define PRINT_DEBUG
++
++
++#define U_IOBASE (sleep_param->uart_base)
++
++#define OFF_TDR         (0x00)
++#define OFF_LCR         (0x0C)
++#define OFF_LSR         (0x14)
++#define LSR_TDRQ        (1 << 5)
++#define LSR_TEMT        (1 << 6)
++
++
++#ifdef PRINT_DEBUG
++#define TCSM_PCHAR(x)                                                   \
++	*((volatile unsigned int*)(U_IOBASE+OFF_TDR)) = x;              \
++while ((*((volatile unsigned int*)(U_IOBASE + OFF_LSR)) & (LSR_TDRQ | LSR_TEMT)) != (LSR_TDRQ | LSR_TEMT))
++#else
++#define TCSM_PCHAR(x)
++#endif
++
++#define TCSM_DELAY(x)						\
++	do{							\
++	register unsigned int i = x;				\
++	while(i--)						\
++		__asm__ volatile("nop\n\t");			\
++	}while(0)
++
++static inline void serial_put_hex(unsigned int x) {
++	int i;
++	unsigned int d;
++	for(i = 7;i >= 0;i--) {
++		d = (x  >> (i * 4)) & 0xf;
++		if(d < 10) d += '0';
++		else d += 'A' - 10;
++		TCSM_PCHAR(d);
++	}
++	TCSM_PCHAR('\r');
++	TCSM_PCHAR('\n');
++}
++
++
++
++
+diff --git a/arch/mips/xburst2/soc-x2500/pm_fastboot.c b/arch/mips/xburst2/soc-x2500/pm_fastboot.c
+new file mode 100644
+index 000000000..53d44a4be
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/pm_fastboot.c
+@@ -0,0 +1,667 @@
++#include <linux/init.h>
++#include <linux/pm.h>
++#include <linux/suspend.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++
++#include <soc/cache.h>
++#include <soc/base.h>
++#include <asm/io.h>
++#include <soc/ddr.h>
++#include <soc/base.h>
++#include <soc/cpm.h>
++#include <ccu.h>
++
++#include "pm_fastboot.h"
++
++
++volatile unsigned int intc0_msk;
++volatile unsigned int intc1_msk;
++volatile unsigned int gpio_pb_int;
++volatile unsigned int gpio_pb_msk;
++volatile unsigned int gpio_pb_pat1;
++volatile unsigned int gpio_pb_pat0;
++volatile unsigned int gpio_pe_int;
++volatile unsigned int gpio_pe_msk;
++volatile unsigned int gpio_pe_pat1;
++volatile unsigned int gpio_pe_pat0;
++
++volatile unsigned int clk_gate0;
++volatile unsigned int clk_gate1;
++
++volatile unsigned int mem_pd0;
++volatile unsigned int mem_pd1;
++
++#define  g_state  ((volatile suspend_state_t *)0xb0000bfc)
++volatile unsigned int _regs_stack_0[136 / 4];
++volatile unsigned int _regs_stack_1[136 / 4];
++volatile unsigned int *_regs_stack;
++
++static inline void rtc_write_reg(unsigned int reg, unsigned int val)
++{
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++	*(volatile unsigned int *)0xb000303c = 0xa55a;
++	while (!((*(volatile unsigned int *)0xb000303c >> 31) & 0x1) );
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++
++	*(volatile unsigned int *)reg = val;
++
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++}
++
++static inline unsigned int  rtc_read_reg(unsigned int reg)
++{
++	while (!((*(volatile unsigned int *)0xb0003000 >> 7) & 0x1) );
++
++	return *(volatile unsigned int *)reg;
++}
++
++#define PRINT_DEBUG
++
++
++#ifdef PRINT_DEBUG
++
++#define OFF_TDR         (0x00)
++#define OFF_LCR         (0x0C)
++#define OFF_LSR         (0x14)
++#define LSR_TDRQ        (1 << 5)
++#define LSR_TEMT        (1 << 6)
++
++#define U_IOBASE (UART2_IOBASE + 0xa0000000)
++#define TCSM_PCHAR(x)                                                   \
++	*((volatile unsigned int*)(U_IOBASE+OFF_TDR)) = x;              \
++while ((*((volatile unsigned int*)(U_IOBASE + OFF_LSR)) & (LSR_TDRQ | LSR_TEMT)) != (LSR_TDRQ | LSR_TEMT))
++#else
++#define TCSM_PCHAR(x)
++#endif
++
++#define TCSM_DELAY(x)                                           \
++	do{                                                     \
++		register unsigned int i = x;                    \
++		while(i--)                                      \
++		__asm__ volatile(".set mips32\n\t"      \
++				"nop\n\t"              \
++				".set mips32");        \
++	}while(0)                                               \
++
++static inline void serial_put_hex(unsigned int x) {
++	int i;
++	unsigned int d;
++	for(i = 7;i >= 0;i--) {
++		d = (x  >> (i * 4)) & 0xf;
++		if(d < 10) d += '0';
++		else d += 'A' - 10;
++		TCSM_PCHAR(d);
++	}
++	TCSM_PCHAR('\r');
++	TCSM_PCHAR('\n');
++}
++
++#if 1
++struct uart_regs {
++	unsigned int udllr;
++	unsigned int udlhr;
++	unsigned int uthr;
++	unsigned int uier;
++	unsigned int ufcr;
++	unsigned int ulcr;
++	unsigned int umcr;
++	unsigned int uspr;
++	unsigned int isr;
++	unsigned int umr;
++	unsigned int uacr;
++	unsigned int urcr;
++	unsigned int utcr;
++
++};
++
++
++static void uart_save(struct uart_regs *uart_regs)
++{
++	printk("uart save\n");
++	*(volatile unsigned int *)0xb003200c |= (1 << 7);
++	uart_regs->udllr = *(volatile unsigned int *)0xb0032000;
++	uart_regs->udlhr = *(volatile unsigned int *)0xb0032004;
++
++	*(volatile unsigned int *)0xb003200c &= ~(1 << 7);
++	uart_regs->uthr = *(volatile unsigned int  *)0xb0032000;
++	uart_regs->uier = *(volatile unsigned int  *)0xb0032004;
++
++	uart_regs->ufcr = *(volatile unsigned int  *)0xb0032008;
++	uart_regs->ulcr = *(volatile unsigned int  *)0xb003200c;
++	uart_regs->umcr = *(volatile unsigned int  *)0xb0032010;
++	uart_regs->uspr = *(volatile unsigned int  *)0xb003201c;
++	uart_regs->isr = *(volatile unsigned int  *)0xb0032020;
++	uart_regs->umr = *(volatile unsigned int  *)0xb0032024;
++	uart_regs->uacr = *(volatile unsigned int *)0xb0032028;
++	uart_regs->urcr = *(volatile unsigned int *)0xb0032040;
++	uart_regs->utcr = *(volatile unsigned int *)0xb0032044;
++
++	printk("uthr   = 0x%08x\n", uart_regs->uthr);
++	printk("uier   = 0x%08x\n", uart_regs->uier);
++	printk("udllr   = 0x%08x\n", uart_regs->udllr);
++	printk("udlhr   = 0x%08x\n", uart_regs->udlhr);
++	printk("ULCR = 0x%08x\n", *(volatile unsigned int *)0xb003200c);
++	printk("UMCR = 0x%08x\n", *(volatile unsigned int *)0xb0032010);
++	printk("ULSR = 0x%08x\n", *(volatile unsigned int *)0xb0032014);
++	printk("UMSR = 0x%08x\n", *(volatile unsigned int *)0xb0032018);
++	printk("USPR = 0x%08x\n", *(volatile unsigned int *)0xb003201c);
++	printk("ISR  = 0x%08x\n", *(volatile unsigned int *)0xb0032020);
++	printk("UMR  = 0x%08x\n", *(volatile unsigned int *)0xb0032024);
++	printk("UACR = 0x%08x\n", *(volatile unsigned int *)0xb0032028);
++	printk("URCR = 0x%08x\n", *(volatile unsigned int *)0xb0032040);
++	printk("UTCR = 0x%08x\n", *(volatile unsigned int *)0xb0032044);
++
++
++}
++
++static void uart_set_baud(struct uart_regs *uart_regs)
++{
++	*(volatile unsigned int *)0xb0032024 = uart_regs->umr;
++	*(volatile unsigned int *)0xb0032028 = uart_regs->uacr;
++
++	*(volatile unsigned int *)0xb003200c |= (1 << 7);
++	*(volatile unsigned int *)0xb0032000 = uart_regs->udllr;
++	*(volatile unsigned int *)0xb0032004 = uart_regs->udlhr;
++	*(volatile unsigned int *)0xb003200c &= ~(1 << 7);
++
++}
++
++
++static void uart_restore(struct uart_regs *uart_regs)
++{
++
++	*(volatile unsigned int *)0xb0000020 &= ~(1 << 16);
++
++	/*uart2 PD30 PD31 func0 */
++	*(volatile unsigned int *)0xb0010318 |= (3 << 30);
++	*(volatile unsigned int *)0xb0010328 |= (3 << 30);
++	*(volatile unsigned int *)0xb0010338 |= (3 << 30);
++	*(volatile unsigned int *)0xb0010348 |= (3 << 30);
++
++
++	*(volatile unsigned int *)0xb0032008 = uart_regs->ufcr;
++	*(volatile unsigned int *)0xb003200c = uart_regs->ulcr;
++	*(volatile unsigned int *)0xb0032010 = uart_regs->umcr;
++	*(volatile unsigned int *)0xb003201c = uart_regs->uspr;
++	*(volatile unsigned int *)0xb0032020 = uart_regs->isr;
++	*(volatile unsigned int *)0xb0032024 = uart_regs->umr;
++	*(volatile unsigned int *)0xb0032028 = uart_regs->uacr;
++	*(volatile unsigned int *)0xb0032040 = uart_regs->urcr;
++	*(volatile unsigned int *)0xb0032044 = uart_regs->utcr;
++
++	uart_set_baud(uart_regs);
++
++	*(volatile unsigned int *)0xb0032008 = (1 << 4) | (1 << 0) | (1 << 1) | (1 << 2);
++
++}
++#endif
++
++struct ost_regs {
++	unsigned int ostccr;
++	unsigned int oster;
++	unsigned int ostcr;
++	unsigned int ostfr;
++	unsigned int ostmr;
++	unsigned int ostdfr;
++	unsigned int ostcnt;
++
++	unsigned int g_ostccr;
++	unsigned int g_oster;
++	unsigned int g_ostcr;
++	unsigned int g_ostcnth;
++	unsigned int g_ostcntl;
++	unsigned int g_ostcntb;
++};
++
++static void ost_save(struct ost_regs *ost_regs)
++{
++	ost_regs->ostccr = *(volatile unsigned int *)0xb2100000;
++	ost_regs->oster = *(volatile unsigned int *)0xb2100004;
++	ost_regs->ostcr = *(volatile unsigned int *)0xb2100008;
++	ost_regs->ostfr = *(volatile unsigned int *)0xb210000c;
++	ost_regs->ostmr = *(volatile unsigned int *)0xb2100010;
++	ost_regs->ostdfr = *(volatile unsigned int *)0xb2100014;
++	ost_regs->ostcnt = *(volatile unsigned int *)0xb2100018;
++
++	ost_regs->g_ostccr = *(volatile unsigned int *)0xb2000000;
++	ost_regs->g_oster = *(volatile unsigned int *)0xb2000004;
++	ost_regs->g_ostcr = *(volatile unsigned int *)0xb2000008;
++	ost_regs->g_ostcnth = *(volatile unsigned int *)0xb200000c;
++	ost_regs->g_ostcntl = *(volatile unsigned int *)0xb2000010;
++	ost_regs->g_ostcntb = *(volatile unsigned int *)0xb2000014;
++
++}
++
++static void ost_restore(struct ost_regs *ost_regs)
++{
++	*(volatile unsigned int *)0xb2100000 = ost_regs->ostccr;
++	*(volatile unsigned int *)0xb2100008 = ost_regs->ostcr;
++	*(volatile unsigned int *)0xb210000c = ost_regs->ostfr;
++	*(volatile unsigned int *)0xb2100010 = ost_regs->ostmr;
++	*(volatile unsigned int *)0xb2100014 = ost_regs->ostdfr;
++	*(volatile unsigned int *)0xb2100018 = ost_regs->ostcnt;
++	*(volatile unsigned int *)0xb2100004 = ost_regs->oster;
++
++	*(volatile unsigned int *)0xb2000000 = ost_regs->g_ostccr;
++	*(volatile unsigned int *)0xb2000008 = ost_regs->g_ostcr;
++	*(volatile unsigned int *)0xb2000004 = ost_regs->g_oster;
++
++}
++
++static noinline void cpu_resume(void);
++
++
++static void rtc_ram_write_enable(void)
++{
++	unsigned int tmp;
++
++	/* write RTC RAM enable */
++	tmp = rtc_read_reg(0xb0003048);
++	tmp &= ~(1 << 23);
++	tmp &= ~(1 << 22);
++	tmp |= (1 << 21);
++	tmp |= (1 << 20);
++	rtc_write_reg(0xb0003048, tmp);
++
++}
++
++static void rtc_ram_write_disable(void)
++{
++	unsigned int tmp;
++
++	/*exit write RTC RAM enable */
++	tmp = rtc_read_reg(0xb0003048);
++	tmp |= (1 << 22);
++	rtc_write_reg(0xb0003048, tmp);
++
++}
++
++
++static void soc_pm_fastboot(void)
++{
++
++	unsigned int tmp;
++
++	clk_gate0 = cpm_inl(CPM_CLKGR);
++	clk_gate1 = cpm_inl(CPM_CLKGR1);
++
++	clk_gate0 |= 1 << 20; // disable ost
++	clk_gate0 &= ~(1 << 28); // enable apb0
++	clk_gate0 &= ~(1 << 27); //enable rtc
++
++	cpm_outl(clk_gate0, CPM_CLKGR);
++
++	printk("clk_gate0: 0x%08x, clk_gate1: 0x%08x\n", clk_gate0, clk_gate1);
++
++
++
++	intc1_msk = *(volatile unsigned int *)0xb0001024;
++	*(volatile unsigned int *)0xb0001024 = intc1_msk & ~(1<<0); // RTC INT MSK
++
++	/* RTC EALM */
++	tmp = rtc_read_reg(0xb000302c);
++	tmp |= 1;
++	rtc_write_reg(0xb000302c, tmp);
++
++	/* RTC enable AE */
++	tmp = rtc_read_reg(0xb0003000);
++	tmp |= (1 << 2) | (1 << 0);
++	rtc_write_reg(0xb0003000, tmp);
++
++	/* 32k rtc clk */
++	tmp = rtc_read_reg(0xb0003000);
++	tmp &= ~(1 << 1);
++	rtc_write_reg(0xb0003000, tmp);
++}
++
++static int soc_post_wakeup(void)
++{
++
++	clk_gate0 &= ~(1 << 20);	//enable ost
++	cpm_outl(clk_gate0, CPM_CLKGR);
++	cpm_outl(clk_gate1, CPM_CLKGR1);
++
++
++	return 0;
++}
++
++
++
++
++
++static struct store_regs *store_regs;
++
++static void save_resume_pc(void)
++{
++
++	store_regs = (struct store_regs *)RTC_RAM_DATA_ADDR;
++	store_regs->resume_pc = (unsigned int)cpu_resume;
++	printk("xxxxxxxxxxxxxxxxxxx save resume_pc = 0x%08x\n", store_regs->resume_pc);
++}
++static void pll_store(void)
++{
++	struct pll_resume_reg *pll_resume_reg;
++
++	store_regs = (struct store_regs *)RTC_RAM_DATA_ADDR;
++	pll_resume_reg = &store_regs->pll_resume_reg;
++
++	pll_resume_reg->cpccr = *(volatile unsigned int *)0xb0000000;
++	pll_resume_reg->cppcr = *(volatile unsigned int *)0xb000000c;
++	pll_resume_reg->cpapcr = *(volatile unsigned int *)0xb0000010;
++	pll_resume_reg->cpmpcr = *(volatile unsigned int *)0xb0000014;
++	pll_resume_reg->cpepcr = *(volatile unsigned int *)0xb0000018;
++	pll_resume_reg->ddrcdr = *(volatile unsigned int *)0xb000002c;
++
++}
++
++static void ddrc_store(void)
++{
++	struct ddrc_resume_reg *ddrc_resume_reg;
++
++	store_regs = (struct store_regs *)RTC_RAM_DATA_ADDR;
++	ddrc_resume_reg = &store_regs->ddrc_resume_reg;
++
++	ddrc_resume_reg->dcfg = *(volatile unsigned int *)0xb34f0008;
++	ddrc_resume_reg->dctrl = *(volatile unsigned int *)0xb34f0010;
++	ddrc_resume_reg->dlmr = *(volatile unsigned int *)0xb34f0018;
++	ddrc_resume_reg->ddlp = *(volatile unsigned int *)0xb34f0020;
++	ddrc_resume_reg->dasr_en = *(volatile unsigned int *)0xb34f0030;
++	ddrc_resume_reg->dasr_cnt = *(volatile unsigned int *)0xb34f0028;
++	ddrc_resume_reg->drefcnt = *(volatile unsigned int *)0xb34f0038;
++	ddrc_resume_reg->dtimming1 = *(volatile unsigned int *)0xb34f0040;
++	ddrc_resume_reg->dtimming2 = *(volatile unsigned int *)0xb34f0048;
++	ddrc_resume_reg->dtimming3 = *(volatile unsigned int *)0xb34f0050;
++	ddrc_resume_reg->dtimming4 = *(volatile unsigned int *)0xb34f0058;
++	ddrc_resume_reg->dtimming5 = *(volatile unsigned int *)0xb34f0060;
++	ddrc_resume_reg->dmmap0 = *(volatile unsigned int *)0xb34f0078;
++	ddrc_resume_reg->dmmap1 = *(volatile unsigned int *)0xb34f0080;
++	ddrc_resume_reg->dwcfg = *(volatile unsigned int *)0xb3012000;
++	ddrc_resume_reg->dremap1 = *(volatile unsigned int *)0xb3012008;
++	ddrc_resume_reg->dremap2 = *(volatile unsigned int *)0xb301200c;
++	ddrc_resume_reg->dremap3 = *(volatile unsigned int *)0xb3012010;
++	ddrc_resume_reg->dremap4 = *(volatile unsigned int *)0xb3012014;
++	ddrc_resume_reg->dremap5 = *(volatile unsigned int *)0xb3012018;
++	ddrc_resume_reg->ccguc0 = *(volatile unsigned int *)0xb3012064;
++	ddrc_resume_reg->ccguc1 = *(volatile unsigned int *)0xb3012068;
++
++}
++
++static void ddr_phy_store(void)
++{
++	struct ddr_phy_resume_reg *ddr_phy_resume_reg;
++
++	store_regs = (struct store_regs *)RTC_RAM_DATA_ADDR;
++	ddr_phy_resume_reg = &store_regs->ddr_phy_resume_reg;
++
++	ddr_phy_resume_reg->mem_cfg = *(volatile unsigned int *)0xb3011004;
++	ddr_phy_resume_reg->dq_width = *(volatile unsigned int *)0xb301107c;
++	ddr_phy_resume_reg->cl = *(volatile unsigned int *)0xb3011014;
++	ddr_phy_resume_reg->al = *(volatile unsigned int *)0xb3011018;
++	ddr_phy_resume_reg->cwl = *(volatile unsigned int *)0xb301101c;
++	ddr_phy_resume_reg->pll_fbdiv = *(volatile unsigned int *)0xb3011080;
++	ddr_phy_resume_reg->pll_ctrl = *(volatile unsigned int *)0xb3011084;
++	ddr_phy_resume_reg->pll_pdiv = *(volatile unsigned int *)0xb3011088;
++	ddr_phy_resume_reg->training_ctrl = *(volatile unsigned int *)0xb3011008;
++	ddr_phy_resume_reg->calib_bypass_al = *(volatile unsigned int *)0xb3011118;
++	ddr_phy_resume_reg->calib_bypass_ah = *(volatile unsigned int *)0xb3011158;
++	ddr_phy_resume_reg->wl_mode1 = *(volatile unsigned int *)0xb301100c;
++	ddr_phy_resume_reg->wl_mode2 = *(volatile unsigned int *)0xb3011010;
++}
++
++static void rtc_ram_store(void)
++{
++	pll_store();
++	ddrc_store();
++	ddr_phy_store();
++	save_resume_pc();
++}
++
++
++static int fastboot_resume_code[] = {
++
++#include "fastboot_resume_code.hex"
++
++};
++
++
++
++
++
++
++extern long long save_goto(unsigned int);
++extern int restore_goto(void);
++
++
++
++static noinline void cpu_resume(void)
++{
++
++	unsigned int cpu_id;
++
++
++	cpu_id = read_c0_ebase() & 0x3ff;
++
++	if (cpu_id == 0) {
++		_regs_stack = _regs_stack_0;
++	} else if (cpu_id == 1) {
++		_regs_stack = _regs_stack_1;
++	}
++
++	*(volatile unsigned int *)0xb2200f00 = 0xbfc00000; /* RESET entry = 0xbfc00000 ,reset value */
++
++	__asm__ volatile(
++		".set push	\n\t"
++		".set mips32r2	\n\t"
++		"jr.hb %0	\n\t"
++		"nop		\n\t"
++		".set pop 	\n\t"
++		:
++		: "r" (restore_goto)
++		:
++		);
++}
++
++
++
++
++#define jump() do{                                  \
++	                void (*func)(void);                                             \
++	                func = (void(*)(void)) 0xb0004000;              \
++	                func();                                                                 \
++	        }while(0)
++
++#if 0
++static void ddrp_auto_calibration(void)
++{
++	unsigned int reg_val = ddr_readl(DDRP_INNOPHY_TRAINING_CTRL);
++	unsigned int timeout = 0xffffff;
++	unsigned int wait_cal_done = DDRP_CALIB_DONE_HDQCFA | DDRP_CALIB_DONE_LDQCFA;
++
++	reg_val &= ~(DDRP_TRAINING_CTRL_DSCSE_BP);
++	reg_val |= DDRP_TRAINING_CTRL_DSACE_START;
++	ddr_writel(reg_val, DDRP_INNOPHY_TRAINING_CTRL);
++
++	while(!((ddr_readl(DDRP_INNOPHY_CALIB_DONE) & wait_cal_done) == wait_cal_done) && --timeout) {
++		TCSM_PCHAR('t');
++		serial_put_hex(*(volatile unsigned int *)(0x80015060 + 0 * 4));
++		serial_put_hex(*(volatile unsigned int *)(0x80015060 + 1 * 4));
++		serial_put_hex(*(volatile unsigned int *)(0x80015060 + 2 * 4));
++		serial_put_hex(*(volatile unsigned int *)(0x80015060 + 3 * 4));
++	}
++
++	if(!timeout) {
++		TCSM_PCHAR('f');
++	}
++	ddr_writel(0, DDRP_INNOPHY_TRAINING_CTRL);
++}
++#endif
++
++
++static noinline void cpu_sleep(void)
++{
++
++
++	unsigned int tmp;
++	unsigned int ddrc_ctrl;
++
++	blast_dcache32();
++	blast_scache64();
++	__sync();
++	__fast_iob();
++
++	ddr_writel(0, DDRC_AUTOSR_EN);
++	tmp = *(volatile unsigned int *)0xa0000000;
++
++
++	/* DDR self refresh, */
++	ddrc_ctrl = ddr_readl(DDRC_CTRL);
++	ddrc_ctrl |= 1 << 5;
++	ddr_writel(ddrc_ctrl, DDRC_CTRL);
++	while(!(ddr_readl(DDRC_STATUS) & (1<<2)));
++
++	/* bufferen_core = 0 */
++	tmp = rtc_read_reg(0xb0003048);
++	tmp &= ~(1 << 21);
++	rtc_write_reg(0xb0003048, tmp);
++
++	/* dfi_init_start = 1 */
++	*(volatile unsigned int *)0xb3012000 |= (1 << 3);
++
++
++	{
++		int i;
++		for (i = 0; i < 4; i++) {
++
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++			__asm__ volatile("ssnop\t\n");
++		}
++	}
++	/* ddr phy pll power down */
++	*(volatile unsigned int *)0xb3011084 |= (1 << 1);
++
++
++
++	TCSM_PCHAR('o');
++
++
++	/* rtc disable power detect */
++	rtc_write_reg(0xb000302c, (0x1a55a5a5 << 3) | 1);
++	/* RTC PD */
++	rtc_write_reg(0xb0003020, 1);
++
++
++	while (1);
++}
++
++
++
++static void load_func_to_tcsm(unsigned int *tcsm_addr,unsigned int *f_addr,unsigned int size)
++{
++	unsigned int instr;
++	int offset;
++	int i;
++#ifdef DEBUG_PM
++	printk("tcsm addr = %p %p size = %d\n",tcsm_addr,f_addr,size);
++#endif
++	for(i = 0;i < size / 4;i++) {
++		instr = f_addr[i];
++		if((instr >> 26) == 2){
++			offset = instr & 0x3ffffff;
++			offset = (offset << 2) - ((unsigned int)f_addr & 0xfffffff);
++			if(offset > 0) {
++				offset = ((unsigned int)tcsm_addr & 0xfffffff) + offset;
++				instr = (2 << 26) | (offset >> 2);
++			}
++		}
++		tcsm_addr[i] = instr;
++	}
++}
++
++
++static int x2000_pm_enter(suspend_state_t state)
++{
++	unsigned int cpu_id;
++	struct uart_regs *uart_regs;
++	struct ost_regs *ost_regs;
++
++	uart_regs = kmalloc(sizeof(struct uart_regs), GFP_KERNEL);
++	ost_regs = kmalloc(sizeof(struct ost_regs), GFP_KERNEL);
++	soc_pm_fastboot();
++
++	load_func_to_tcsm((unsigned int *)SLEEP_CPU_SLEEP_TEXT, (unsigned int *)cpu_sleep, SLEEP_CPU_SLEEP_LEN);
++
++	rtc_ram_write_enable();
++	rtc_ram_store();
++	memcpy((unsigned int *)RTC_RAM_CODE_ADDR1, (unsigned int *)fastboot_resume_code, RTC_RAM_CODE_SIZE);
++	rtc_ram_write_disable();
++
++	uart_save(uart_regs);
++	ost_save(ost_regs);
++
++	cpu_id = read_c0_ebase() & 0x3ff;
++
++	printk("cpu_id = %d\n", cpu_id);
++
++	if (cpu_id == 0) {
++		_regs_stack = _regs_stack_0;
++	} else if (cpu_id == 1) {
++		_regs_stack = _regs_stack_1;
++	}
++
++
++	mb();
++	save_goto((unsigned int)SLEEP_CPU_SLEEP_TEXT);
++	mb();
++
++
++	soc_post_wakeup();
++
++	ost_restore(ost_regs);
++	uart_restore(uart_regs);
++	set_ccu_mimr(1 << 0);
++
++
++	return 0;
++}
++
++static int x2000_pm_begin(suspend_state_t state)
++{
++	printk("x2000 suspend begin\n");
++
++	return 0;
++}
++
++static void x2000_pm_end(void)
++{
++	printk("x2000 pm end!\n");
++
++}
++
++static const struct platform_suspend_ops x2000_pm_ops = {
++	.valid		= suspend_valid_only_mem,
++	.begin		= x2000_pm_begin,
++	.enter		= x2000_pm_enter,
++	.end		= x2000_pm_end,
++};
++
++/*
++ * Initialize suspend interface
++ */
++static int __init pm_init(void)
++{
++
++	suspend_set_ops(&x2000_pm_ops);
++
++	return 0;
++}
++
++arch_initcall(pm_init);
+diff --git a/arch/mips/xburst2/soc-x2500/pm_fastboot.h b/arch/mips/xburst2/soc-x2500/pm_fastboot.h
+new file mode 100644
+index 000000000..3bad4d885
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/pm_fastboot.h
+@@ -0,0 +1,106 @@
++
++
++#define RTC_SLEEP_MEMORY_START          0xb0004000
++#define RTC_SLEEP_MEMORY_END            0xb0005000
++#define RTC_RAM_SP_ADDR                 (RTC_RAM_DATA_ADDR - 4)
++//#define RTC_RAM_SP_SIZE                 (256 - 4)
++#define RTC_RAM_DATA_ADDR               0xb0004c00
++#define RTC_RAM_DATA_SIZE               1024
++#define RTC_RAM_CODE_ADDR1              0xb0004000
++#define RTC_RAM_CODE_ADDR2              (RTC_RAM_CODE_ADDR1 + 64)
++#define RTC_RAM_CODE_SIZE               0xb00
++
++#define SLEEP_CPU_SLEEP_TEXT		0xb2400000
++#define SLEEP_CPU_SLEEP_LEN		4096
++
++
++
++struct pll_resume_reg {
++	unsigned int cpccr;
++	unsigned int cppcr;
++	unsigned int cpapcr;
++	unsigned int cpmpcr;
++	unsigned int cpepcr;
++	unsigned int ddrcdr;
++};
++
++struct ddrc_resume_reg {
++	unsigned int dcfg;
++	unsigned int dctrl;
++	unsigned int dlmr;
++	unsigned int ddlp;
++	unsigned int dasr_en;
++	unsigned int dasr_cnt;
++	unsigned int drefcnt;
++	unsigned int dtimming1;
++	unsigned int dtimming2;
++	unsigned int dtimming3;
++	unsigned int dtimming4;
++	unsigned int dtimming5;
++	unsigned int dmmap0;
++	unsigned int dmmap1;
++#if 0
++	unsigned int dbwcfg;
++	unsigned int dbwstp;
++	unsigned int hregpro;
++	unsigned int dbgen;
++#endif
++	unsigned int dwcfg;
++	unsigned int dremap1;
++	unsigned int dremap2;
++	unsigned int dremap3;
++	unsigned int dremap4;
++	unsigned int dremap5;
++#if 0
++	unsigned int cpac;
++	unsigned int cchc0;
++	unsigned int cchc1;
++	unsigned int cchc2;
++	unsigned int cchc3;
++	unsigned int cchc4;
++	unsigned int cchc5;
++	unsigned int cchc6;
++	unsigned int cchc7;
++	unsigned int cschc0;
++	unsigned int cschc1;
++	unsigned int cschc2;
++	unsigned int cschc3;
++	unsigned int cmonc0;
++	unsigned int cmonc1;
++	unsigned int cmonc2;
++	unsigned int cmonc3;
++	unsigned int cmonc4;
++#endif
++	unsigned int ccguc0;
++	unsigned int ccguc1;
++#if 0
++	unsigned int pregpro;
++	unsigned int bufcfg;
++#endif
++};
++
++struct ddr_phy_resume_reg {
++	unsigned int phy_rst;
++	unsigned int mem_cfg;
++	unsigned int dq_width;
++	unsigned int cl;
++	unsigned int al;
++	unsigned int cwl;
++	unsigned int pll_fbdiv;
++	unsigned int pll_ctrl;
++	unsigned int pll_pdiv;
++	unsigned int training_ctrl;
++	unsigned int calib_bypass_al;
++	unsigned int calib_bypass_ah;
++	unsigned int wl_mode1;
++	unsigned int wl_mode2;
++
++};
++
++struct store_regs {
++	unsigned int resume_pc;
++	struct pll_resume_reg pll_resume_reg;
++	struct ddrc_resume_reg ddrc_resume_reg;
++	struct ddr_phy_resume_reg ddr_phy_resume_reg;
++};
++
+diff --git a/arch/mips/xburst2/soc-x2500/regs_save_restore.S b/arch/mips/xburst2/soc-x2500/regs_save_restore.S
+new file mode 100644
+index 000000000..abe8b49df
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/regs_save_restore.S
+@@ -0,0 +1,190 @@
++#include <asm/asm.h>
++#include <asm/regdef.h>
++
++#define CP0_PAGEMASK	$5,0
++#define CP0_STATUS	$12,0
++#define CP0_INTCTL	$12,1
++#define CP0_CAUSE	$13,0
++#define CP0_EBASE	$15,1
++#define CP0_CONFIG	$16,0
++#define CP0_CONFIG1	$16,1
++#define CP0_CONFIG2	$16,2
++#define CP0_CONFIG3	$16,3
++#define CP0_CONFIG4	$16,4
++#define CP0_CONFIG5	$16,5
++#define CP0_CONFIG7	$16,7
++#define CP0_LLADDR	$17,0
++#define CP0_WATCHLo	$18,0
++#define CP0_WATCHHI	$19,0
++#define CP0_ERRCTL	$26,0
++#define CP0_CONTEXT	$4,0
++#define CP0_KSCRATCH1	$31,2
++#define CP0_KSCRATCH2	$31,3
++#define CP0_KSCRATCH3	$31,4
++#define CP0_KSCRATCH4	$31,5
++#define CP0_KSCRATCH5	$31,6
++#define CP0_KSCRATCH6	$31,7
++
++	.data
++	.global _regs_stack
++_regs_stack:
++	.align 5
++	.space 140,0
++
++	.text
++	.global save_goto
++	.align 2
++	.ent save_goto,0
++	LEAF(save_goto)
++save_goto:
++	.set	push
++	.set	noreorder
++	.set	noat
++
++	la	k0, _regs_stack
++	sw	s0,0(k0)
++	sw	s1,4(k0)
++	sw	s2,8(k0)
++	sw	s3,12(k0)
++	sw	s4,16(k0)
++	sw	s5,20(k0)
++	sw	s6,24(k0)
++	sw	s7,28(k0)
++	sw	gp,32(k0)
++	sw	sp,36(k0)
++	sw	fp,40(k0)
++	sw	ra,44(k0)
++
++	mfc0	k1,CP0_PAGEMASK
++	sw	k1,48(k0)
++	mfc0	k1,CP0_STATUS
++	sw	k1,52(k0)
++	mfc0	k1,CP0_INTCTL
++	sw	k1,56(k0)
++	mfc0	k1,CP0_CAUSE
++	sw	k1,60(k0)
++	mfc0	k1,CP0_EBASE
++	sw	k1,64(k0)
++	mfc0	k1,CP0_CONFIG
++	sw	k1,68(k0)
++	mfc0	k1,CP0_CONFIG1
++	sw	k1,72(k0)
++	mfc0	k1,CP0_CONFIG2
++	sw	k1,76(k0)
++	mfc0	k1,CP0_CONFIG3
++	sw	k1,80(k0)
++	mfc0	k1,CP0_CONFIG4
++	sw	k1,84(k0)
++	mfc0	k1,CP0_CONFIG5
++	sw	k1,88(k0)
++	mfc0	k1,CP0_CONFIG7
++	sw	k1,92(k0)
++	mfc0	k1,CP0_LLADDR
++	sw	k1,96(k0)
++	mfc0	k1,CP0_WATCHLo
++	sw	k1,100(k0)
++	mfc0	k1,CP0_WATCHHI
++	sw	k1,104(k0)
++	mfc0	k1,CP0_ERRCTL
++	sw	k1,108(k0)
++	mfc0	k1,CP0_CONTEXT
++	sw	k1,112(k0)
++	mfc0	k1,CP0_KSCRATCH1
++	sw	k1,116(k0)
++	mfc0	k1,CP0_KSCRATCH2
++	sw	k1,120(k0)
++	mfc0	k1,CP0_KSCRATCH3
++	sw	k1,124(k0)
++	mfc0	k1,CP0_KSCRATCH4
++	sw	k1,128(k0)
++	mfc0	k1,CP0_KSCRATCH5
++	sw	k1,132(k0)
++	mfc0	k1,CP0_KSCRATCH6
++	sw	k1,136(k0)
++
++	jr.hb	a0
++	nop
++
++	.set	at
++	.set	reorder
++	.set	pop
++	END(save_goto)
++
++	.text
++	.global restore_goto
++	.align 2
++	.ent restore_goto,0
++	LEAF(restore_goto)
++restore_goto:
++	.set	push
++	.set	noreorder
++	.set	noat
++
++	la	k0, _regs_stack
++	lw	s0,0(k0)
++	lw	s1,4(k0)
++	lw	s2,8(k0)
++	lw	s3,12(k0)
++	lw	s4,16(k0)
++	lw	s5,20(k0)
++	lw	s6,24(k0)
++	lw	s7,28(k0)
++	lw	gp,32(k0)
++	lw	sp,36(k0)
++	lw	fp,40(k0)
++	lw	ra,44(k0)
++
++	lw	k1,48(k0)
++	mtc0	k1,CP0_PAGEMASK
++	lw	k1,52(k0)
++	mtc0	k1,CP0_STATUS
++	lw	k1,56(k0)
++	mtc0	k1,CP0_INTCTL
++	lw	k1,60(k0)
++	mtc0	k1,CP0_CAUSE
++	lw	k1,64(k0)
++	mtc0	k1,CP0_EBASE
++	lw	k1,68(k0)
++	mtc0	k1,CP0_CONFIG
++	lw	k1,72(k0)
++	mtc0	k1,CP0_CONFIG1
++	lw	k1,76(k0)
++	mtc0	k1,CP0_CONFIG2
++	lw	k1,80(k0)
++	mtc0	k1,CP0_CONFIG3
++	lw	k1,84(k0)
++	mtc0	k1,CP0_CONFIG4
++	lw	k1,88(k0)
++	mtc0	k1,CP0_CONFIG5
++	lw	k1,92(k0)
++	mtc0	k1,CP0_CONFIG7
++	lw	k1,96(k0)
++	mtc0	k1,CP0_LLADDR
++	lw	k1,100(k0)
++	mtc0	k1,CP0_WATCHLo
++	lw	k1,104(k0)
++	mtc0	k1,CP0_WATCHHI
++	lw	k1,108(k0)
++	mtc0	k1,CP0_ERRCTL
++	lw	k1,112(k0)
++	mtc0	k1,CP0_CONTEXT
++	lw	k1,116(k0)
++	mtc0	k1,CP0_KSCRATCH1
++	lw	k1,120(k0)
++	mtc0	k1,CP0_KSCRATCH2
++	lw	k1,124(k0)
++	mtc0	k1,CP0_KSCRATCH3
++	lw	k1,128(k0)
++	mtc0	k1,CP0_KSCRATCH4
++	lw	k1,132(k0)
++	mtc0	k1,CP0_KSCRATCH5
++	lw	k1,136(k0)
++	mtc0	k1,CP0_KSCRATCH6
++
++	jr.hb	ra
++	nop
++
++	.set	at
++	.set	reorder
++	.set	pop
++	END(restore_goto)
+diff --git a/arch/mips/xburst2/soc-x2500/regs_save_restore.py b/arch/mips/xburst2/soc-x2500/regs_save_restore.py
+new file mode 100755
+index 000000000..8a23de0d0
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/regs_save_restore.py
+@@ -0,0 +1,124 @@
++#!/usr/bin/env python
++import os
++import string
++
++common_regs=["s0","s1","s2","s3",
++        "s4","s5","s6","s7",
++        "gp","sp","fp","ra"]
++cp0_regs=[
++        ["CP0_PAGEMASK","$5","0"],
++        ["CP0_STATUS","$12","0"],
++        ["CP0_INTCTL","$12","1"],
++        ["CP0_CAUSE","$13","0"],
++        ["CP0_EBASE","$15","1"],
++        ["CP0_CONFIG","$16","0"],
++        ["CP0_CONFIG1","$16","1"],
++        ["CP0_CONFIG2","$16","2"],
++        ["CP0_CONFIG3","$16","3"],
++	["CP0_CONFIG4", "$16", "4"],
++	["CP0_CONFIG5", "$16", "5"],
++	["CP0_CONFIG7", "$16", "7"],
++        ["CP0_LLADDR","$17","0"],
++        ["CP0_WATCHLo","$18","0"],
++        ["CP0_WATCHHI","$19","0"],
++        ["CP0_ERRCTL","$26","0"],
++        ["CP0_CONTEXT","$4","0"],
++        ["CP0_KSCRATCH1","$31","2"],
++        ["CP0_KSCRATCH2","$31","3"],
++        ["CP0_KSCRATCH3","$31","4"],
++        ["CP0_KSCRATCH4","$31","5"],
++        ["CP0_KSCRATCH5","$31","6"],
++        ["CP0_KSCRATCH6","$31","7"],
++        ]
++def gen_get_array_size():
++    size=0
++    size+=len(common_regs)
++    size+=len(cp0_regs)
++    return size
++
++def gen_print_head_and_macro():
++    print("#include <asm/asm.h>")
++    print("#include <asm/regdef.h>")
++    print("")
++    for s in cp0_regs:
++        print("#define %s\t%s,%s" %(s[0],s[1],s[2]))
++    print("")
++def gen_define_global_arg(str, num):
++    print("\t.data")
++    print("\t.global %s" %(str))
++    print("%s:" %(str))
++    print("\t.align 5")
++    print("\t.space %s,0" %(num))
++    print("")
++
++def gen_save_common_regs(index):
++    for s in common_regs:
++        print("\tsw\t%s,%d(k0)" % (s,index))
++        index=index+4
++    return index
++def gen_restore_common_regs(index):
++    for s in common_regs:
++        print("\tlw\t%s,%d(k0)" % (s,index))
++        index=index+4
++    return index
++def gen_save_cp0_regs(index):
++    for s in cp0_regs:
++        print("\tmfc0\tk1,%s" % (s[0]))
++        print("\tsw\tk1,%d(k0)" % (index))
++        index=index+4
++    return index
++def gen_restore_cp0_regs(index):
++    for s in cp0_regs:
++        print("\tlw\tk1,%d(k0)" % (index))
++        print("\tmtc0\tk1,%s" % (s[0]))
++        index=index+4
++    return index
++def gen_print_function(f_name, regs_stack):
++    index=0
++    print("\t.text")
++    print("\t.global %s" %(f_name))
++    print("\t.align 2")
++    print("\t.ent %s,0" %(f_name))
++    print("\tLEAF(%s)" %(f_name))
++    print("%s:" %(f_name))
++    print("\t.set\tpush")
++    print("\t.set\tnoreorder")
++    print("\t.set\tnoat")
++    print("")
++    print("\tla\tk0, %s" %(regs_stack))
++    if f_name == "save_goto":
++        index = gen_save_common_regs(index)
++        print("")
++        index = gen_save_cp0_regs(index)
++        print("")
++        print("\tjr.hb\ta0")
++        print("\tnop")
++    elif f_name == "restore_goto":
++        index = gen_restore_common_regs(index)
++        print("")
++        index = gen_restore_cp0_regs(index)
++        print("")
++        print("\tjr.hb\tra")
++        print("\tnop")
++    else:
++        print("not support")
++    print("")
++    print("\t.set\tat")
++    print("\t.set\treorder")
++    print("\t.set\tpop")
++    print("\tEND(%s)" %(f_name))
++
++
++def main():
++    regs_size=gen_get_array_size()
++    regs_size*=4
++
++    gen_print_head_and_macro()
++    gen_define_global_arg("_regs_stack", regs_size)
++    gen_print_function("save_goto", "_regs_stack")
++    print("")
++    gen_print_function("restore_goto", "_regs_stack")
++    pass
++
++if __name__ == '__main__':
++    main()
+diff --git a/arch/mips/xburst2/soc-x2500/reset.c b/arch/mips/xburst2/soc-x2500/reset.c
+new file mode 100644
+index 000000000..52a2a16a9
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/reset.c
+@@ -0,0 +1,331 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/irq.h>
++#include <linux/tty.h>
++#include <linux/delay.h>
++#include <linux/proc_fs.h>
++#include <linux/kthread.h>
++#include <linux/syscore_ops.h>
++#include <linux/platform_device.h>
++#include <linux/sched/rt.h>
++#include <linux/slab.h>
++#include <linux/proc_fs.h>
++#include <linux/seq_file.h>
++#include <linux/module.h>
++
++
++#include <soc/base.h>
++#include <soc/cpm.h>
++#include <soc/extal.h>
++
++#include <asm/reboot.h>
++
++#include <ingenic_proc.h>
++
++#define RTC_RTCCR		(0x00)	/* rw, 32, 0x00000081 */
++#define RTC_RTCSR		(0x04)	/* rw, 32, 0x???????? */
++#define RTC_RTCSAR		(0x08)	/* rw, 32, 0x???????? */
++#define RTC_RTCGR		(0x0c)	/* rw, 32, 0x0??????? */
++#define RTC_HCR			(0x20)  /* rw, 32, 0x00000000 */
++#define RTC_HWFCR		(0x24)  /* rw, 32, 0x0000???0 */
++#define RTC_HRCR		(0x28)  /* rw, 32, 0x00000??0 */
++#define RTC_HWCR		(0x2c)  /* rw, 32, 0x00000008 */
++#define RTC_HWRSR		(0x30)  /* rw, 32, 0x00000000 */
++#define RTC_HSPR		(0x34)  /* rw, 32, 0x???????? */
++#define RTC_WENR		(0x3c)  /* rw, 32, 0x00000000 */
++#define RTC_CKPCR		(0x40)  /* rw, 32, 0x00000010 */
++#define RTC_OWIPCR		(0x44)  /* rw, 32, 0x00000010 */
++#define RTC_PWRONCR		(0x48)  /* rw, 32, 0x???????? */
++
++#define WDT_TCSR		(0x0c)  /* rw, 32, 0x???????? */
++#define WDT_TCER		(0x04)  /* rw, 32, 0x???????? */
++#define WDT_TDR			(0x00)  /* rw, 32, 0x???????? */
++#define WDT_TCNT		(0x08)  /* rw, 32, 0x???????? */
++
++#define TCU_TSSR	(0x2C)   /* Timer Stop Set Register */
++#define TCU_TSCR	(0x3C)   /* Timer Stop Clear Register */
++
++#define RTCCR_WRDY		BIT(7)
++#define WENR_WEN                BIT(31)
++
++#define RECOVERY_SIGNATURE	(0x001a1a)
++#define REBOOT_SIGNATURE	(0x003535)
++#define UNMSAK_SIGNATURE	(0x7c0000)//do not use these bits
++
++#if 0
++static void wdt_start_count(int msecs)
++{
++	int time = JZ_EXTAL_RTC / 64 * msecs / 1000;
++	if(time > 65535)
++		time = 65535;
++
++//	outl(1 << 16,TCU_IOBASE + TCU_TSCR);
++
++	outl(0,WDT_IOBASE + WDT_TCNT);		//counter
++	outl(time,WDT_IOBASE + WDT_TDR);	//data
++	outl((3<<3 | 2<<0 | 1 << 10),WDT_IOBASE + WDT_TCSR);
++	outl(0,WDT_IOBASE + WDT_TCER);
++	outl(1,WDT_IOBASE + WDT_TCER);
++}
++#endif
++static void __attribute__((unused)) wdt_stop_count(void)
++{
++	outl(1 << 16,TCU_IOBASE + TCU_TSCR);
++	outl(0,WDT_IOBASE + WDT_TCNT);		//counter
++	outl(65535,WDT_IOBASE + WDT_TDR);	//data
++	outl(1 << 16,TCU_IOBASE + TCU_TSSR);
++}
++
++static int inline rtc_write_reg(int reg,int value)
++{
++	int timeout = 0x2000;
++	while(!(inl(RTC_IOBASE + RTC_RTCCR) & RTCCR_WRDY) && timeout--);
++	if(!timeout)
++	{
++		printk("WARN:NO USE RTC!!!!!\n");
++		return -1;
++	}
++	outl(0xa55a,(RTC_IOBASE + RTC_WENR));
++	while(!(inl(RTC_IOBASE + RTC_RTCCR) & RTCCR_WRDY));
++	while(!(inl(RTC_IOBASE + RTC_WENR) & WENR_WEN));
++	while(!(inl(RTC_IOBASE + RTC_RTCCR) & RTCCR_WRDY));
++	outl(value,(RTC_IOBASE + reg));
++	while(!(inl(RTC_IOBASE + RTC_RTCCR) & RTCCR_WRDY));
++
++	return 0;
++}
++
++/*
++ * Function: Keep power for CPU core when reset.
++ * So that EPC, tcsm and so on can maintain it's status after reset-key pressed.
++ */
++static int inline reset_keep_power(void)
++{
++	return rtc_write_reg(RTC_PWRONCR,
++			     inl(RTC_IOBASE + RTC_PWRONCR) & ~(1 << 0));
++}
++
++#define HWFCR_WAIT_TIME(x) ((x > 0x7fff ? 0x7fff: (0x7ff*(x)) / 2000) << 5)
++#define HRCR_WAIT_TIME(x) ((((x) > 1875 ? 1875: (x)) / 125) << 11)
++
++void jz_hibernate(void)
++{
++	uint32_t rtc_rtccr;
++
++	local_irq_disable();
++	/* Set minimum wakeup_n pin low-level assertion time for wakeup: 1000ms */
++	rtc_write_reg(RTC_HWFCR, HWFCR_WAIT_TIME(1000));
++
++	/* Set reset pin low-level assertion time after wakeup: must  > 60ms */
++	rtc_write_reg(RTC_HRCR, HRCR_WAIT_TIME(125));
++
++	/* clear wakeup status register */
++	rtc_write_reg(RTC_HWRSR, 0x0);
++
++	rtc_write_reg(RTC_HWCR, 0x0);
++
++	rtc_rtccr = inl(RTC_IOBASE + RTC_RTCCR);
++	rtc_rtccr |= 0x1 << 0;
++	rtc_write_reg(RTC_RTCCR,rtc_rtccr);
++
++	/* Put CPU to hibernate mode */
++	rtc_write_reg(RTC_HCR, 0x1);
++
++	/*poweroff the pmu*/
++//	jz_notifier_call(NOTEFY_PROI_HIGH, JZ_POST_HIBERNATION, NULL);
++
++	mdelay(200);
++
++	while(1)
++		printk("%s:We should NOT come here.%08x\n",__func__, inl(RTC_IOBASE + RTC_HCR));
++}
++
++void jz_wdt_restart(char *command)
++{
++	return;
++#if 0
++	printk("Restarting after 4 ms\n");
++	if ((command != NULL) && !strcmp(command, "recovery")) {
++		while(cpm_inl(CPM_CPPSR) != RECOVERY_SIGNATURE) {
++			printk("set RECOVERY_SIGNATURE\n");
++			cpm_outl(0x5a5a,CPM_CPSPPR);
++			cpm_outl(RECOVERY_SIGNATURE,CPM_CPPSR);
++			cpm_outl(0x0,CPM_CPSPPR);
++			udelay(100);
++		}
++	} else {
++		cpm_outl(0x5a5a,CPM_CPSPPR);
++		cpm_outl(REBOOT_SIGNATURE,CPM_CPPSR);
++		cpm_outl(0x0,CPM_CPSPPR);
++	}
++
++	wdt_start_count(4);
++	mdelay(200);
++	while(1)
++		printk("check wdt.\n");
++#endif
++}
++
++static void hibernate_restart(void)
++{
++	uint32_t rtc_rtcsr,rtc_rtccr;
++
++	while(!(inl(RTC_IOBASE + RTC_RTCCR) & RTCCR_WRDY));
++
++	rtc_rtcsr = inl(RTC_IOBASE + RTC_RTCSR);
++	rtc_rtccr = inl(RTC_IOBASE + RTC_RTCCR);
++
++	rtc_write_reg(RTC_RTCSAR,rtc_rtcsr + 5);
++	rtc_rtccr &= ~(1 << 4 | 1 << 1);
++	rtc_rtccr |= 0x3 << 2;
++	rtc_write_reg(RTC_RTCCR,rtc_rtccr);
++
++	/* Clear reset status */
++	cpm_outl(0,CPM_RSR);
++
++	/* Set minimum wakeup_n pin low-level assertion time for wakeup: 1000ms */
++	rtc_write_reg(RTC_HWFCR, HWFCR_WAIT_TIME(1000));
++
++	/* Set reset pin low-level assertion time after wakeup: must  > 60ms */
++	rtc_write_reg(RTC_HRCR, HRCR_WAIT_TIME(125));
++
++	/* clear wakeup status register */
++	rtc_write_reg(RTC_HWRSR, 0x0);
++
++	rtc_write_reg(RTC_HWCR, 0x1);
++
++
++	rtc_rtccr = inl(RTC_IOBASE + RTC_RTCCR);
++	rtc_rtccr |= 0x1 << 0;
++	rtc_write_reg(RTC_RTCCR,rtc_rtccr);
++
++
++	/* Put CPU to hibernate mode */
++	rtc_write_reg(RTC_HCR, 0x1);
++
++	mdelay(200);
++	while(1)
++		printk("%s:We should NOT come here.%08x\n",__func__, inl(RTC_IOBASE + RTC_HCR));
++}
++
++#ifdef CONFIG_HIBERNATE_RESET
++void jz_hibernate_restart(char *command)
++{
++	local_irq_disable();
++
++	if ((command != NULL) && !strcmp(command, "recovery")) {
++		jz_wdt_restart(command);
++	}
++
++	hibernate_restart();
++}
++#endif
++
++int __init reset_init(void)
++{
++	pm_power_off = jz_hibernate;
++#ifdef CONFIG_HIBERNATE_RESET
++	_machine_restart = jz_hibernate_restart;
++#else
++	_machine_restart = jz_wdt_restart;
++#endif
++	return 0;
++}
++arch_initcall(reset_init);
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++struct wdt_reset {
++	unsigned stop;
++	unsigned msecs;
++	unsigned count;
++};
++
++/* ============================reset proc=================================== */
++static char *reset_command[] = {"wdt","hibernate","recovery", "poweroff"};
++
++static int reset_show(struct seq_file *filq, void *v)
++{
++	int len = 0, i;
++
++	for(i = 0; i < ARRAY_SIZE(reset_command); i++)
++		seq_printf(filq, "%s\t", reset_command[i]);
++	seq_printf(filq,"\n");
++
++	return len;
++}
++
++static int reset_write(struct file *file, const char __user *buffer,
++		       size_t usize, loff_t *off)
++{
++	int command_size = 0;
++	int i;
++
++	if(usize == 0)
++		return -EINVAL;
++
++	command_size = ARRAY_SIZE(reset_command);
++	for(i = 0;i < command_size; i++) {
++		if(!strncmp(buffer, reset_command[i], strlen(reset_command[i])))
++			break;
++	}
++	if(i == command_size)
++		return -EINVAL;
++
++	local_irq_disable();
++	switch(i) {
++	case 0:
++		jz_wdt_restart(NULL);
++		break;
++	case 1:
++		hibernate_restart();
++		break;
++	case 2:
++		jz_wdt_restart("recovery");
++		break;
++	case 3:
++		jz_hibernate();
++		break;
++	default:
++		printk("not support command %d\n", i);
++	}
++
++	return usize;
++}
++static struct jz_single_file_ops reset_proc_fops = {
++	.read = reset_show,
++	.write = reset_write,
++};
++/* ============================reset proc end=============================== */
++
++static int __init init_reset(void)
++{
++	struct wdt_reset *wdt;
++	struct proc_dir_entry *p, *res;
++
++	wdt = kmalloc(sizeof(struct wdt_reset),GFP_KERNEL);
++	if(!wdt) {
++		return -ENOMEM;
++	}
++
++	wdt->count = 0;
++	wdt->msecs = 3000;
++
++	wdt->stop = 1;
++
++	p = jz_proc_mkdir("reset");
++	if (!p) {
++		pr_warn("create_proc_entry for common reset failed.\n");
++		return -ENODEV;
++	}
++
++	res = jz_proc_create_data("reset", 0444, p, &reset_proc_fops, wdt);
++
++	return 0;
++}
++module_init(init_reset);
+diff --git a/arch/mips/xburst2/soc-x2500/serial.c b/arch/mips/xburst2/soc-x2500/serial.c
+new file mode 100644
+index 000000000..563208c52
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/serial.c
+@@ -0,0 +1,91 @@
++/*
++ * JZ SOC serial routines for early_printk.
++ *
++ * Copyright (C) 2006 Ingenic Semiconductor Inc.
++ *
++ */
++
++#include <asm/io.h>
++
++#include <soc/base.h>
++
++#define UART_BASE	UART0_IOBASE
++#define UART_OFF	0x1000
++
++#define OFF_TDR		(0x00)
++#define OFF_LCR		(0x0C)
++#define OFF_LSR		(0x14)
++
++#define LSR_TDRQ	(1 << 5)
++#define LSR_TEMT	(1 << 6)
++
++static void check_uart(char c);
++
++volatile u8 *uart_base;
++typedef void (*putchar_f_t)(char);
++static putchar_f_t putchar_f = check_uart;
++
++static void putchar(char ch)
++{
++	int timeout = 10000;
++	volatile u8 *base = uart_base;
++	/* Wait for fifo to shift out some bytes */
++	while ((base[OFF_LSR] & (LSR_TDRQ | LSR_TEMT))
++	       != (LSR_TDRQ | LSR_TEMT) && timeout--)
++		;
++	base[OFF_TDR] = (u8)ch;
++}
++
++static void putchar_dummy(char ch)
++{
++	return;
++}
++
++static void check_uart(char c)
++{
++	/* We Couldn't use ioremap() here */
++	volatile u8 *base = (volatile u8*)CKSEG1ADDR(UART0_IOBASE);
++	int i = 0;
++	for(i=0; i<10; i++) {
++		if(base[OFF_LCR])
++			break;
++		base += UART_OFF;
++	}
++
++	if(i<10) {
++		uart_base = base;
++		putchar_f = putchar;
++		putchar_f(c);
++	} else {
++		putchar_f = putchar_dummy;
++	}
++}
++
++/* used by early printk */
++void prom_putchar(char c)
++{
++	putchar_f(c);
++}
++
++void prom_putstr(char *s)
++{
++	while(*s) {
++		if(*s == '\n')
++			putchar_f('\r');
++		putchar_f(*s);
++		s++;
++	}
++}
++
++#if 1
++static char pbuffer[4096];
++void prom_printk(const char *fmt, ...) {
++	va_list args;
++
++	va_start(args, fmt);
++	vsnprintf(pbuffer, 4096, fmt, args);
++	va_end(args);
++
++	prom_putstr(pbuffer);
++}
++#endif
+diff --git a/arch/mips/xburst2/soc-x2500/setup.c b/arch/mips/xburst2/soc-x2500/setup.c
+new file mode 100644
+index 000000000..c4d68f03b
+--- /dev/null
++++ b/arch/mips/xburst2/soc-x2500/setup.c
+@@ -0,0 +1,84 @@
++/*
++ * Ingenic Soc Setup
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2006 Ingenic Semiconductor Inc.
++ */
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/delay.h>
++#include <linux/module.h>
++#include <linux/err.h>
++#include <linux/proc_fs.h>
++#include <linux/ioport.h>
++#include <linux/of_fdt.h>
++#include <linux/of_platform.h>
++#include <linux/clk-provider.h>
++#include <linux/clocksource.h>
++#include <linux/irqchip.h>
++#include <linux/clocksource.h>
++
++#include <asm/prom.h>
++#include <soc/base.h>
++
++void __init cpm_reset(void)
++{
++}
++
++int __init setup_init(void)
++{
++#if 0
++	cpm_reset();
++	/* Set bus priority here */
++	*(volatile unsigned int *)0xb34f0240 = 0x00010003;
++	*(volatile unsigned int *)0xb34f0244 = 0x00010003;
++#endif
++
++	return 0;
++}
++extern void __init init_all_clk(void);
++/* used by linux-mti code */
++extern void *get_fdt_addr(void);
++void __init plat_mem_setup(void)
++{
++	/* use IO_BASE, so that we can use phy addr on hard manual
++	 * directly with in(bwlq)/out(bwlq) in io.h.
++	 */
++	set_io_port_base(IO_BASE);
++	ioport_resource.start	= 0x00000000;
++	ioport_resource.end	= 0xffffffff;
++	iomem_resource.start	= 0x00000000;
++	iomem_resource.end	= 0xffffffff;
++	setup_init();
++
++	__dt_setup_arch(get_fdt_addr());
++
++	return;
++}
++void __init device_tree_init(void)
++{
++	unflatten_and_copy_device_tree();
++}
++
++static int __init plat_of_populate(void)
++{
++	of_platform_default_populate(NULL, NULL, NULL);
++	return 0;
++}
++arch_initcall(plat_of_populate);
++
++void __init plat_time_init(void)
++{
++	of_clk_init(NULL);
++
++	timer_probe();
++}
++
++void __init arch_init_irq(void)
++{
++	irqchip_init();
++}
+diff --git a/block/partitions/efi.c b/block/partitions/efi.c
+index b64bfdd43..d16b8d018 100644
+--- a/block/partitions/efi.c
++++ b/block/partitions/efi.c
+@@ -406,7 +406,9 @@ static int is_gpt_valid(struct parsed_partitions *state, u64 lba,
+ 		pr_debug("GPT: last_usable_lba incorrect: %lld > %lld\n",
+ 			 (unsigned long long)le64_to_cpu((*gpt)->last_usable_lba),
+ 			 (unsigned long long)lastlba);
++#ifndef CONFIG_INGENIC_GPT_CHECK
+ 		goto fail;
++#endif
+ 	}
+ 	if (le64_to_cpu((*gpt)->last_usable_lba) < le64_to_cpu((*gpt)->first_usable_lba)) {
+ 		pr_debug("GPT: last_usable_lba incorrect: %lld > %lld\n",
+diff --git a/drivers/char/Makefile b/drivers/char/Makefile
+index ffce287ef..ffe6dd788 100644
+--- a/drivers/char/Makefile
++++ b/drivers/char/Makefile
+@@ -47,3 +47,5 @@ obj-$(CONFIG_PS3_FLASH)		+= ps3flash.o
+ obj-$(CONFIG_XILLYBUS)		+= xillybus/
+ obj-$(CONFIG_POWERNV_OP_PANEL)	+= powernv-op-panel.o
+ obj-$(CONFIG_ADI)		+= adi.o
++obj-$(CONFIG_INGENIC_SFCNAND_FMW) += jz_spinand_firmware.o
++ccflags-$(CONFIG_INGENIC_SFCNAND_FMW) += -I$(srctree)/module_drivers/drivers/mtd/devices/ingenic_sfc_v2
+diff --git a/drivers/char/jz_spinand_firmware.c b/drivers/char/jz_spinand_firmware.c
+new file mode 100644
+index 000000000..bb488bc0b
+--- /dev/null
++++ b/drivers/char/jz_spinand_firmware.c
+@@ -0,0 +1,486 @@
++/**
++ * 兼容x1830平�，便于应用集�
++ */
++
++#include <linux/init.h>
++#include <linux/err.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/nand.h>
++#include <asm/io.h>
++#include <linux/cdev.h>
++
++#include "jz_spinand_firmware.h"
++#include "sfc_flash.h"
++
++
++static int fmw_open(struct inode *inode, struct file *filp)
++{
++    struct cdev *cdev = inode->i_cdev;
++    struct fmw_dev *fmw = container_of(cdev, struct fmw_dev, cdev);
++
++    filp->private_data = fmw;
++
++    if(!driver_find(JZ_SFC_NAND, &platform_bus_type)) {
++        printk(KERN_ERR "%s %s %d: %s driver module init failed!\n",
++            __FILE__, __func__, __LINE__, JZ_SFC_NAND);
++        return -ENODEV;
++    }
++
++    return 0;
++}
++
++static int32_t fmw_read(uint32_t flash_off, void *buf, uint32_t len)
++{
++    struct mtd_info *mtd = &fmw_flash->mtd;
++    uint32_t retlen = 0;
++    int ret;
++
++    ret = mtd->_read(mtd, flash_off, len, &retlen, buf);
++    return ret;
++}
++
++static int32_t fmw_write(uint32_t flash_off, void *buf, uint32_t len)
++{
++    struct mtd_info *mtd = &fmw_flash->mtd;
++    uint32_t retlen = 0;
++    int ret;
++
++    ret = mtd->_write(mtd, flash_off, len, &retlen, buf);
++    return ret;
++}
++
++static int32_t fwm_erase(uint32_t flash_off, uint32_t flash_size)
++{
++    int i;
++    struct mtd_info *mtd = &fmw_flash->mtd;
++    struct erase_info info = {
++        .addr = flash_off,
++        .len  = mtd->erasesize,
++    };
++
++    for (i = 0; i < flash_size / mtd->erasesize; i++) {
++        mtd->_erase(mtd, &info);
++        info.addr += info.len;
++    }
++    return 0;
++}
++
++static int32_t fwm_buf_compare(uint8_t *wbuf, uint8_t *rbuf, uint32_t len)
++{
++    int ret = memcmp(wbuf, rbuf, len);
++    if (ret) {
++        printk(KERN_ERR "compare err wbuf do not equal to rbuf.\n");
++        return -EIO;
++    }
++    return 0;
++}
++
++static int32_t sn_read_config(struct fmw_dev *fmw)
++{
++
++    struct mtd_info *mtd = &fmw_flash->mtd;
++    int i,ret;
++    int32_t flash_off = CONFIG_MAC_FLASH_SIZE;
++
++    for (i = 0; i < CONFIG_SN_FLASH_SIZE / mtd->erasesize; i++) {
++        ret  = fmw_read(mtd->size + flash_off, &fmw->sn_config, sizeof(fmw->sn_config));
++        if(ret >= 0 && fmw->sn_config.sn_len != 0 && fmw->sn_config.crc_val != 0)
++            break;
++        flash_off += mtd->erasesize;
++    }
++
++    if(fmw->sn_config.sn_len == -1 ||
++        fmw->sn_config.crc_val == -1 ||
++        fmw->sn_config.sn_len >= SN_BUF_LEN) {
++        printk(KERN_ERR "%s %s %d: flash don`t save sn value!\n",
++            __FILE__, __func__, __LINE__);
++        return -ENODATA;
++    }
++
++    if(i == CONFIG_SN_FLASH_SIZE / mtd->erasesize) {
++        printk(KERN_ERR "%s %s %d:flash all blocks ecc error!\n",
++            __FILE__, __func__, __LINE__);
++            return -EIO;
++    }
++
++    return 0;
++}
++
++static int32_t sn_read(struct fmw_dev *fmw)
++{
++    struct mtd_info *mtd = &fmw_flash->mtd;
++    uint32_t flash_off = mtd->size + CONFIG_MAC_FLASH_SIZE;
++    uint32_t blocksize = mtd->erasesize;
++    int32_t ret = 0;
++    uint8_t i;
++
++    if(sn_read_config(fmw)) {
++        printk(KERN_ERR "%s %s %d:read sn config failed!\n",
++            __FILE__, __func__, __LINE__);
++        return -EIO;
++    }
++
++    for (i = 0; i < CONFIG_SN_FLASH_SIZE / blocksize; i++) {
++        ret = fmw_read(flash_off + sizeof(fmw->sn_config), fmw->buf, fmw->sn_config.sn_len);
++        if(ret < 0) {
++            flash_off += blocksize;
++            continue;
++        }
++
++        if(local_crc32(0xffffffff, fmw->buf, fmw->sn_config.sn_len) == fmw->sn_config.crc_val)
++            break;
++        flash_off += blocksize;
++    }
++    if(i == CONFIG_SN_FLASH_SIZE / blocksize) {
++        printk(KERN_ERR "%s %s %d: sn flash all blocks ecc error!\n",
++            __FILE__, __func__, __LINE__);
++            return -EIO;
++    }
++
++    return 0;
++}
++
++static int32_t mac_read_config(struct fmw_dev *fmw)
++{
++    struct mtd_info *mtd = &fmw_flash->mtd;
++    int i,ret;
++    int32_t flash_off = 0;
++
++    for (i = 0; i < CONFIG_MAC_FLASH_SIZE / mtd->erasesize; i++) {
++        ret = fmw_read(mtd->size + flash_off, &fmw->mac_config, sizeof(fmw->mac_config));
++        if(ret >= 0 && fmw->mac_config.mac_len != 0 && fmw->mac_config.crc_val != 0)
++                break;
++        flash_off += mtd->erasesize;
++
++    }
++
++    if(fmw->mac_config.mac_len == -1 ||
++        fmw->mac_config.crc_val == -1 ||
++        fmw->mac_config.mac_len >= MAC_BUF_LEN) {
++        printk(KERN_ERR "%s %s %d: flash don`t save mac value!\n",
++            __FILE__, __func__, __LINE__);
++        return -ENODATA;
++    }
++
++    if(i == CONFIG_MAC_FLASH_SIZE / mtd->erasesize) {
++        printk(KERN_ERR "%s %s %d:flash all blocks ecc error!\n",
++            __FILE__, __func__, __LINE__);
++            return -EIO;
++    }
++
++    return 0;
++}
++
++static int32_t mac_read(struct fmw_dev *fmw)
++{
++    struct mtd_info *mtd = &fmw_flash->mtd;
++    uint32_t flash_off = mtd->size;
++    uint32_t blocksize = mtd->erasesize;
++    int32_t ret = 0;
++    uint8_t i;
++
++    if(mac_read_config(fmw)) {
++        printk(KERN_ERR "%s %s %d:read mac config failed!\n",
++            __FILE__, __func__, __LINE__);
++        return -EIO;
++    }
++
++    for (i = 0; i < CONFIG_MAC_FLASH_SIZE / blocksize; i++) {
++        ret = fmw_read(flash_off + sizeof(fmw->mac_config), fmw->buf, fmw->mac_config.mac_len);
++        if(ret < 0) {
++            flash_off += blocksize;
++            continue;
++        }
++
++        if(local_crc32(0xffffffff, fmw->buf, fmw->mac_config.mac_len) == fmw->mac_config.crc_val)
++            break;
++        flash_off += blocksize;
++    }
++
++    if(i == CONFIG_MAC_FLASH_SIZE / blocksize) {
++        printk(KERN_ERR "%s %s %d: mac flash all blocks ecc error!\n",
++            __FILE__, __func__, __LINE__);
++            return -EIO;
++    }
++
++    return 0;
++}
++
++static int32_t license_read_config(struct fmw_dev *fmw)
++{
++    struct mtd_info *mtd = &fmw_flash->mtd;
++    int i, ret;
++    int32_t flash_off = CONFIG_MAC_FLASH_SIZE + CONFIG_SN_FLASH_SIZE;
++
++    for (i = 0; i < CONFIG_LICENSE_FLASH_SIZE / mtd->erasesize; i++) {
++        ret = fmw_read(mtd->size + flash_off, &fmw->license_config, sizeof(fmw->license_config));
++        if (ret >= 0 && fmw->license_config.license_len != 0 && fmw->license_config.crc_val != 0) {
++            break;
++        }
++        flash_off += mtd->erasesize;
++    }
++    if (fmw->license_config.license_len == -1 ||
++        fmw->license_config.crc_val == -1 ||
++        fmw->license_config.license_len >= LICENSE_BUF_LEN) {
++            pr_err("%s %s %d: flash don't save license value!\n",
++                    __FILE__, __func__, __LINE__);
++            return -ENODATA;
++    }
++
++    if (i == CONFIG_LICENSE_FLASH_SIZE / mtd->erasesize) {
++        pr_err("%s %s %d:flash all blocks ecc error!\n",
++                __FILE__, __func__, __LINE__);
++        return -EIO;
++    }
++    return 0;
++}
++
++static int32_t license_read(struct fmw_dev *fmw)
++{
++    struct mtd_info *mtd = &fmw_flash->mtd;
++    uint32_t flash_off = mtd->size + CONFIG_MAC_FLASH_SIZE + CONFIG_SN_FLASH_SIZE;
++    uint32_t blocksize = mtd->erasesize;
++    int32_t ret = 0;
++    uint32_t i;
++
++    if (license_read_config(fmw)) {
++        pr_err("%s %s %d:license config failed\n",
++                __FILE__, __func__, __LINE__);
++        return -EIO;
++    }
++
++    for (i = 0; i < CONFIG_LICENSE_FLASH_SIZE / blocksize; i++) {
++        ret = fmw_read(flash_off + sizeof(fmw->license_config), fmw->buf, fmw->license_config.license_len);
++        if (ret < 0) {
++            flash_off += blocksize;
++            continue;
++        }
++        if(local_crc32(0xffffffff, fmw->buf, fmw->license_config.license_len) == fmw->license_config.crc_val)
++            break;
++        flash_off += blocksize;
++    }
++
++    if(i == CONFIG_LICENSE_FLASH_SIZE / blocksize) {
++        printk(KERN_ERR "%s %s %d: license flash all blocks ecc error!\n",
++            __FILE__, __func__, __LINE__);
++        return -EIO;
++    }
++
++    return 0;
++}
++
++static int32_t license_write(struct fmw_dev *fmw)
++{
++    int i;
++    uint8_t errcount = 0;
++    struct mtd_info *mtd = &fmw_flash->mtd;
++    uint32_t flash_offs = mtd->size + CONFIG_MAC_FLASH_SIZE + CONFIG_SN_FLASH_SIZE;
++    uint32_t flash_size = CONFIG_LICENSE_FLASH_SIZE;
++    int32_t ret = 0;
++    uint8_t *rbuf;
++
++    void *buf = kzalloc(sizeof(fmw->license_config) + fmw->license_config.license_len, GFP_KERNEL);
++    if(!buf) {
++        printk(KERN_ERR "alloc mem failed!\n");
++        return -ENOMEM;
++    }
++
++    memcpy(buf, &fmw->license_config, sizeof(fmw->license_config));
++    memcpy(buf + sizeof(fmw->license_config), fmw->buf, fmw->license_config.license_len);
++
++    fwm_erase(flash_offs, flash_size);
++    for (i = 0; i < flash_size / mtd->erasesize; i++) {
++        ret = fmw_write(flash_offs, buf, sizeof(fmw->license_config) + fmw->license_config.license_len);
++        if(ret) {
++            printk(KERN_ERR "%s %s %d:write data failed! errcount = %d\n",
++                    __FILE__, __func__, __LINE__, errcount++);
++            flash_offs += mtd->erasesize;
++            continue;
++        }
++
++        rbuf = kzalloc(sizeof(fmw->license_config) + fmw->license_config.license_len, GFP_KERNEL);
++        if (rbuf) {
++            ret = fmw_read(flash_offs, rbuf, sizeof(fmw->license_config) + fmw->license_config.license_len);
++            if (!ret) {
++                if ((ret = fwm_buf_compare(buf, rbuf, sizeof(fmw->license_config) + fmw->license_config.license_len))) {
++                    printk(KERN_ERR "%s %s %d: buf compare err!\n", __FILE__, __func__, __LINE__);
++                }
++            }
++            kfree(rbuf);
++        }
++    }
++    if(errcount == flash_size / mtd->erasesize) {
++        printk(KERN_ERR "all blk write failed!\n");
++        kfree(buf);
++        return -EIO;
++    }
++
++    kfree(buf);
++    return ret;
++}
++
++
++static long fmw_ioctl(struct file *filp, unsigned int cmd, unsigned long args)
++{
++    struct fmw_dev *fmw = filp->private_data;
++    uint32_t max_len;
++    int32_t ret = 0;
++
++    switch(cmd) {
++        case SN_GET_CONFIG:
++            if((ret = sn_read_config(fmw))) {
++                printk(KERN_ERR "%s %s %d: sn get config failed, ret = %d\n",
++                    __FILE__, __func__, __LINE__, ret);
++                break;
++            }
++            copy_to_user((void *)args, &fmw->sn_config, sizeof(fmw->sn_config));
++            break;
++        case SN_READ:
++            if((ret = sn_read(fmw))) {
++                printk(KERN_ERR "%s %s %d: sn_read failed, ret = %d\n",
++                    __FILE__, __func__, __LINE__, ret);
++                break;
++            }
++            copy_to_user((void *)args, fmw->buf, fmw->sn_config.sn_len);
++            break;
++
++        case MAC_GET_CONFIG:
++            if((ret = mac_read_config(fmw))) {
++                printk(KERN_ERR "%s %s %d: mac get config failed, ret = %d\n",
++                    __FILE__, __func__, __LINE__, ret);
++                break;
++            }
++            copy_to_user((void *)args, &fmw->mac_config, sizeof(fmw->mac_config));
++            break;
++        case MAC_READ:
++            if((ret = mac_read(fmw))) {
++                printk(KERN_ERR "%s %s %d: mac_read failed, ret = %d\n",
++                    __FILE__, __func__, __LINE__, ret);
++                break;
++            }
++            copy_to_user((void *)args, fmw->buf, fmw->mac_config.mac_len);
++            break;
++
++        case LICENSE_GET_CONFIG:
++            if (license_read_config(fmw)) {
++                pr_err("%s %s %d:license get config failed, ret = %d\n",
++                       __FILE__, __func__, __LINE__, ret);
++                break;
++            }
++            copy_to_user((void *)args, &fmw->license_config, sizeof(fmw->license_config));
++            break;
++        case LICENSE_MAX_LEN:
++            max_len = LICENSE_BUF_LEN;
++            copy_to_user((void *)args, &max_len, sizeof(uint32_t));
++            break;
++        case LICENSE_READ:
++            if (license_read(fmw)) {
++                pr_err("%s %s %d:license read failed, ret = %d\n",
++                     __FILE__, __func__, __LINE__, ret);
++                break;
++            }
++            copy_to_user((void *)args, fmw->buf, fmw->license_config.license_len);
++            break;
++        case LICENSE_WRITE:
++            if((copy_from_user(&fmw->license_config, (void *)args, sizeof(fmw->license_config)))) {
++                printk(KERN_ERR "%s %s %d: get license_config error, ret = %d\n",
++                    __FILE__, __func__, __LINE__, ret);
++                break;
++            }
++            fmw->buf = kzalloc(fmw->license_config.license_len, GFP_KERNEL);
++            if (!fmw->buf) {
++                printk(KERN_ERR "%s %s %d: alloc fmw buf error.\n", __FILE__, __func__, __LINE__);
++                return -ENOMEM;
++            }
++            if((ret = copy_from_user(fmw->buf, (char*)args+sizeof(struct license_config), fmw->license_config.license_len))) {
++                printk(KERN_ERR "%s %s %d: get license data error, ret = %d\n",
++                    __FILE__, __func__, __LINE__, ret);
++                break;
++            }
++            if((ret = license_write(fmw))) {
++                printk(KERN_ERR "%s %s %d: license write failed, ret = %d\n",
++                    __FILE__, __func__, __LINE__, ret);
++                break;
++            }
++            break;
++
++        default:
++            printk(KERN_ERR "%s %s %d: don`t support this cmd!\n", __FILE__, __func__, __LINE__);
++            ret = -EINVAL;
++    }
++    return ret;
++}
++
++static int fmw_close (struct inode * inode, struct file *filp)
++{
++    return 0;
++
++}
++
++static struct file_operations fmw_ops = {
++
++    .owner = THIS_MODULE,
++    .open = fmw_open,
++    .release = fmw_close,
++    .unlocked_ioctl = fmw_ioctl,
++};
++
++static int __init fmw_init(void)
++{
++    dev_t dev;
++    int32_t ret = 0;
++
++    struct fmw_dev *fmw = kzalloc(sizeof(*fmw), GFP_KERNEL);
++    if(!fmw) {
++        printk(KERN_ERR "%s %s %d :alloc sn failed!\n",
++            __FILE__, __func__, __LINE__);
++        return -ENOMEM;
++    }
++
++    fmw->buf = kzalloc(SN_BUF_LEN, GFP_KERNEL);
++    if(!fmw->buf) {
++        printk(KERN_ERR "%s %s %d: alloc sn buf failed!\n", __FILE__, __func__, __LINE__);
++        kfree(fmw);
++        return -ENOMEM;
++    }
++
++    fmw->class = class_create(THIS_MODULE, "jz-spinand-sn");
++    fmw->minor = 0;
++    fmw->nr_devs = 1;
++
++    if(alloc_chrdev_region(&dev, fmw->minor, fmw->nr_devs, "jz-spinand-fmw")) {
++
++        printk(KERN_ERR "%s %s %d: alloc chrdev failed!\n",
++            __FILE__, __func__, __LINE__);
++        ret = -ENODEV;
++        goto failed;
++    }
++
++    cdev_init(&fmw->cdev, &fmw_ops);
++    fmw->cdev.owner = THIS_MODULE;
++    cdev_add(&fmw->cdev, dev, fmw->nr_devs);
++
++    fmw->dev = device_create(fmw->class, NULL, dev, NULL, "jz-spinand-fmw");
++    if(IS_ERR_OR_NULL(fmw->dev)) {
++        printk(KERN_ERR "%s %s %d :creates a device and register sysfs failed !\n",
++            __FILE__, __func__, __LINE__);
++        ret = -ENODEV;
++        goto free_all;
++    }
++
++    return 0;
++
++free_all:
++    unregister_chrdev_region(dev, fmw->nr_devs);
++failed:
++    kfree(fmw->buf);
++    kfree(fmw);
++    return ret;
++}
++
++module_init(fmw_init);
++MODULE_AUTHOR("zhangronghua<rhzhang@ingenic.com>");
++MODULE_DESCRIPTION("sn speace read driver");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/char/jz_spinand_firmware.h b/drivers/char/jz_spinand_firmware.h
+new file mode 100644
+index 000000000..b18aceb2e
+--- /dev/null
++++ b/drivers/char/jz_spinand_firmware.h
+@@ -0,0 +1,63 @@
++#ifndef __JZ_SPINAND_FIRMWARE_H
++#define __JZ_SPINAND_FIRMWARE_H
++#include <linux/types.h>
++#include <linux/ioctl.h>
++#include "fmw.h"
++
++#define JZ_SFC_NAND      "ingenic-sfc"
++#define SN_BUF_LEN       512
++#define MAC_BUF_LEN      512
++#define LICENSE_BUF_LEN  CONFIG_LICENSE_FLASH_SIZE
++
++
++#define SN_GET_CONFIG       _IOR('S', 0x0, uint32_t)
++#define SN_READ             _IOR('S', 0x1, uint32_t)
++#define MAC_GET_CONFIG      _IOR('S', 0x2, uint32_t)
++#define MAC_READ            _IOR('S', 0x3, uint32_t)
++#define LICENSE_GET_CONFIG  _IOR('S', 0x4, uint32_t)
++#define LICENSE_READ        _IOR('S', 0x5, uint32_t)
++#define LICENSE_WRITE       _IOR('S', 0x6, uint32_t)
++#define LICENSE_MAX_LEN     _IOR('S', 0x7, uint32_t)
++
++struct sn_config {
++    uint32_t sn_len;
++    uint32_t crc_val;
++};
++
++struct mac_config {
++    uint32_t mac_len;
++    uint32_t crc_val;
++};
++
++struct license_config {
++    uint32_t license_len;
++    uint32_t crc_val;
++};
++
++struct fmw_dev {
++
++    uint8_t minor;
++    uint8_t nr_devs;
++
++    struct class *class;
++    struct cdev cdev;
++    struct device *dev;
++
++    uint8_t *buf;
++
++    /*mac*/
++    struct mac_config mac_config;
++
++    /*sn*/
++    struct sn_config sn_config;
++
++    /*license*/
++    struct license_config license_config;
++};
++
++extern struct bus_type platform_bus_type;
++extern struct sfc_flash *fmw_flash;
++
++#endif
++
++
+diff --git a/drivers/media/platform/v4l2loopback/Makefile b/drivers/media/platform/v4l2loopback/Makefile
+new file mode 100644
+index 000000000..8c58cedf9
+--- /dev/null
++++ b/drivers/media/platform/v4l2loopback/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_V4L2_LOOPBACK_DEVICE) += v4l2loopback.o
+diff --git a/drivers/media/platform/v4l2loopback/v4l2loopback.c b/drivers/media/platform/v4l2loopback/v4l2loopback.c
+new file mode 100644
+index 000000000..29af286d0
+--- /dev/null
++++ b/drivers/media/platform/v4l2loopback/v4l2loopback.c
+@@ -0,0 +1,3016 @@
++/* -*- c-file-style: "linux" -*- */
++/*
++ * v4l2loopback.c  --  video4linux2 loopback driver
++ *
++ * Copyright (C) 2005-2009 Vasily Levin (vasaka@gmail.com)
++ * Copyright (C) 2010-2019 IOhannes m zmoelnig (zmoelnig@iem.at)
++ * Copyright (C) 2011 Stefan Diewald (stefan.diewald@mytum.de)
++ * Copyright (C) 2012 Anton Novikov (random.plant@gmail.com)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++#include <linux/version.h>
++#include <linux/vmalloc.h>
++#include <linux/mm.h>
++#include <linux/time.h>
++#include <linux/module.h>
++#include <linux/videodev2.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/fs.h>
++#include <linux/dma-mapping.h>
++#include <linux/capability.h>
++#include <linux/eventpoll.h>
++#include <media/v4l2-ioctl.h>
++#include <media/v4l2-common.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)
++#define HAVE__V4L2_DEVICE
++#include <media/v4l2-device.h>
++#endif
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
++#define HAVE__V4L2_CTRLS
++#include <media/v4l2-ctrls.h>
++#endif
++#include <media/v4l2-event.h>
++
++#include <linux/miscdevice.h>
++#include "v4l2loopback.h"
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 1)
++#define kstrtoul strict_strtoul
++#endif
++
++#if defined(timer_setup) && defined(from_timer)
++#define HAVE_TIMER_SETUP
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 7, 0)
++#define VFL_TYPE_VIDEO VFL_TYPE_GRABBER
++#endif
++
++//#define USING_DMA_ALLOC_BUFFER
++
++#define V4L2LOOPBACK_VERSION_CODE                                              \
++	KERNEL_VERSION(V4L2LOOPBACK_VERSION_MAJOR, V4L2LOOPBACK_VERSION_MINOR, \
++		       V4L2LOOPBACK_VERSION_BUGFIX)
++
++MODULE_DESCRIPTION("V4L2 loopback video device");
++MODULE_AUTHOR("Vasily Levin, "
++	      "IOhannes m zmoelnig <zmoelnig@iem.at>,"
++	      "Stefan Diewald,"
++	      "Anton Novikov"
++	      "et al.");
++MODULE_LICENSE("GPL");
++
++/*
++ * helpers
++ */
++#define STRINGIFY(s) #s
++#define STRINGIFY2(s) STRINGIFY(s)
++
++#define dprintk(fmt, args...)                                                  \
++	do {                                                                   \
++		if (debug > 0) {                                               \
++			printk(KERN_INFO "v4l2-loopback[" STRINGIFY2(          \
++				       __LINE__) "]: " fmt,                    \
++			       ##args);                                        \
++		}                                                              \
++	} while (0)
++
++#define MARK()                                                                 \
++	do {                                                                   \
++		if (debug > 1) {                                               \
++			printk(KERN_INFO "%s:%d[%s]\n", __FILE__, __LINE__,    \
++			       __func__);                                      \
++		}                                                              \
++	} while (0)
++
++#define dprintkrw(fmt, args...)                                                \
++	do {                                                                   \
++		if (debug > 2) {                                               \
++			printk(KERN_INFO "v4l2-loopback[" STRINGIFY2(          \
++				       __LINE__) "]: " fmt,                    \
++			       ##args);                                        \
++		}                                                              \
++	} while (0)
++
++/*
++ * compatibility hacks
++ */
++
++#ifndef HAVE__V4L2_CTRLS
++struct v4l2_ctrl_handler {
++	int error;
++};
++struct v4l2_ctrl_config {
++	void *ops;
++	u32 id;
++	const char *name;
++	int type;
++	s32 min;
++	s32 max;
++	u32 step;
++	s32 def;
++};
++int v4l2_ctrl_handler_init(struct v4l2_ctrl_handler *hdl,
++			   unsigned nr_of_controls_hint)
++{
++	hdl->error = 0;
++	return 0;
++}
++void v4l2_ctrl_handler_free(struct v4l2_ctrl_handler *hdl)
++{
++}
++void *v4l2_ctrl_new_custom(struct v4l2_ctrl_handler *hdl,
++			   const struct v4l2_ctrl_config *conf, void *priv)
++{
++	return NULL;
++}
++#endif /* HAVE__V4L2_CTRLS */
++
++#ifndef HAVE__V4L2_DEVICE
++/* dummy v4l2_device struct/functions */
++#define V4L2_DEVICE_NAME_SIZE (20 + 16)
++struct v4l2_device {
++	char name[V4L2_DEVICE_NAME_SIZE];
++	struct v4l2_ctrl_handler *ctrl_handler;
++};
++static inline int v4l2_device_register(void *dev, void *v4l2_dev)
++{
++	return 0;
++}
++static inline void v4l2_device_unregister(struct v4l2_device *v4l2_dev)
++{
++	return;
++}
++#endif /*  HAVE__V4L2_DEVICE */
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29)
++#define v4l2_file_operations file_operations
++#endif
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)
++void *v4l2l_vzalloc(unsigned long size)
++{
++	void *data = vmalloc(size);
++
++	memset(data, 0, size);
++	return data;
++}
++#else
++#define v4l2l_vzalloc vzalloc
++#endif
++
++static inline void v4l2l_get_timestamp(struct v4l2_buffer *b)
++{
++	/* ktime_get_ts is considered deprecated, so use ktime_get_ts64 if possible */
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 17, 0)
++	struct timespec ts;
++	ktime_get_ts(&ts);
++#else
++	struct timespec64 ts;
++	ktime_get_ts64(&ts);
++#endif
++
++	b->timestamp.tv_sec = ts.tv_sec;
++	b->timestamp.tv_usec = (ts.tv_nsec / NSEC_PER_USEC);
++}
++
++#if !defined(__poll_t)
++typedef unsigned __poll_t;
++#endif
++
++/* module constants
++ *  can be overridden during he build process using something like
++ *	make KCPPFLAGS="-DMAX_DEVICES=100"
++ */
++
++/* maximum number of v4l2loopback devices that can be created */
++#ifndef MAX_DEVICES
++#define MAX_DEVICES 8
++#endif
++
++/* whether the default is to announce capabilities exclusively or not */
++#ifndef V4L2LOOPBACK_DEFAULT_EXCLUSIVECAPS
++#define V4L2LOOPBACK_DEFAULT_EXCLUSIVECAPS 0
++#endif
++
++/* when a producer is considered to have gone stale */
++#ifndef MAX_TIMEOUT
++#define MAX_TIMEOUT (100 * 1000) /* in msecs */
++#endif
++
++/* max buffers that can be mapped, actually they
++ * are all mapped to max_buffers buffers */
++#ifndef MAX_BUFFERS
++#define MAX_BUFFERS 32
++#endif
++
++/* module parameters */
++static int debug = 0;
++module_param(debug, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(debug, "debugging level (higher values == more verbose)");
++
++#define V4L2LOOPBACK_DEFAULT_MAX_BUFFERS 2
++static int max_buffers = V4L2LOOPBACK_DEFAULT_MAX_BUFFERS;
++module_param(max_buffers, int, S_IRUGO);
++MODULE_PARM_DESC(max_buffers,
++		 "how many buffers should be allocated [DEFAULT: " STRINGIFY2(
++			 V4L2LOOPBACK_DEFAULT_MAX_BUFFERS) "]");
++
++/* how many times a device can be opened
++ * the per-module default value can be overridden on a per-device basis using
++ * the /sys/devices interface
++ *
++ * note that max_openers should be at least 2 in order to get a working system:
++ *   one opener for the producer and one opener for the consumer
++ *   however, we leave that to the user
++ */
++#define V4L2LOOPBACK_DEFAULT_MAX_OPENERS 10
++static int max_openers = V4L2LOOPBACK_DEFAULT_MAX_OPENERS;
++module_param(max_openers, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(
++	max_openers,
++	"how many users can open the loopback device [DEFAULT: " STRINGIFY2(
++		V4L2LOOPBACK_DEFAULT_MAX_OPENERS) "]");
++
++static int devices = -1;
++module_param(devices, int, 0);
++MODULE_PARM_DESC(devices, "how many devices should be created");
++
++static int video_nr[MAX_DEVICES] = { [0 ...(MAX_DEVICES - 1)] = -1 };
++module_param_array(video_nr, int, NULL, 0444);
++MODULE_PARM_DESC(video_nr,
++		 "video device numbers (-1=auto, 0=/dev/video0, etc.)");
++
++static char *card_label[MAX_DEVICES];
++module_param_array(card_label, charp, NULL, 0000);
++MODULE_PARM_DESC(card_label, "card labels for each device");
++
++static bool exclusive_caps[MAX_DEVICES] = {
++	[0 ...(MAX_DEVICES - 1)] = V4L2LOOPBACK_DEFAULT_EXCLUSIVECAPS
++};
++module_param_array(exclusive_caps, bool, NULL, 0444);
++/* FIXXME: wording */
++MODULE_PARM_DESC(
++	exclusive_caps,
++	"whether to announce OUTPUT/CAPTURE capabilities exclusively or not  [DEFAULT: " STRINGIFY2(
++		V4L2LOOPBACK_DEFAULT_EXCLUSIVECAPS) "]");
++
++/* format specifications */
++#define V4L2LOOPBACK_SIZE_MIN_WIDTH 48
++#define V4L2LOOPBACK_SIZE_MIN_HEIGHT 32
++#define V4L2LOOPBACK_SIZE_DEFAULT_MAX_WIDTH 8192
++#define V4L2LOOPBACK_SIZE_DEFAULT_MAX_HEIGHT 8192
++
++#define V4L2LOOPBACK_SIZE_DEFAULT_WIDTH 640
++#define V4L2LOOPBACK_SIZE_DEFAULT_HEIGHT 480
++
++static int max_width = V4L2LOOPBACK_SIZE_DEFAULT_MAX_WIDTH;
++module_param(max_width, int, S_IRUGO);
++MODULE_PARM_DESC(max_width, "maximum allowed frame width [DEFAULT: " STRINGIFY2(
++				    V4L2LOOPBACK_SIZE_DEFAULT_MAX_WIDTH) "]");
++static int max_height = V4L2LOOPBACK_SIZE_DEFAULT_MAX_HEIGHT;
++module_param(max_height, int, S_IRUGO);
++MODULE_PARM_DESC(max_height,
++		 "maximum allowed frame height [DEFAULT: " STRINGIFY2(
++			 V4L2LOOPBACK_SIZE_DEFAULT_MAX_HEIGHT) "]");
++
++static DEFINE_IDR(v4l2loopback_index_idr);
++static DEFINE_MUTEX(v4l2loopback_ctl_mutex);
++
++/* control IDs */
++#ifndef HAVE__V4L2_CTRLS
++#define V4L2LOOPBACK_CID_BASE (V4L2_CID_PRIVATE_BASE)
++#else
++#define V4L2LOOPBACK_CID_BASE (V4L2_CID_USER_BASE | 0xf000)
++#endif
++#define CID_KEEP_FORMAT (V4L2LOOPBACK_CID_BASE + 0)
++#define CID_SUSTAIN_FRAMERATE (V4L2LOOPBACK_CID_BASE + 1)
++#define CID_TIMEOUT (V4L2LOOPBACK_CID_BASE + 2)
++#define CID_TIMEOUT_IMAGE_IO (V4L2LOOPBACK_CID_BASE + 3)
++
++static int v4l2loopback_s_ctrl(struct v4l2_ctrl *ctrl);
++static const struct v4l2_ctrl_ops v4l2loopback_ctrl_ops = {
++	.s_ctrl = v4l2loopback_s_ctrl,
++};
++static const struct v4l2_ctrl_config v4l2loopback_ctrl_keepformat = {
++	// clang-format off
++	.ops	= &v4l2loopback_ctrl_ops,
++	.id	= CID_KEEP_FORMAT,
++	.name	= "keep_format",
++	.type	= V4L2_CTRL_TYPE_BOOLEAN,
++	.min	= 0,
++	.max	= 1,
++	.step	= 1,
++	.def	= 0,
++	// clang-format on
++};
++static const struct v4l2_ctrl_config v4l2loopback_ctrl_sustainframerate = {
++	// clang-format off
++	.ops	= &v4l2loopback_ctrl_ops,
++	.id	= CID_SUSTAIN_FRAMERATE,
++	.name	= "sustain_framerate",
++	.type	= V4L2_CTRL_TYPE_BOOLEAN,
++	.min	= 0,
++	.max	= 1,
++	.step	= 1,
++	.def	= 0,
++	// clang-format on
++};
++static const struct v4l2_ctrl_config v4l2loopback_ctrl_timeout = {
++	// clang-format off
++	.ops	= &v4l2loopback_ctrl_ops,
++	.id	= CID_TIMEOUT,
++	.name	= "timeout",
++	.type	= V4L2_CTRL_TYPE_INTEGER,
++	.min	= 0,
++	.max	= MAX_TIMEOUT,
++	.step	= 1,
++	.def	= 0,
++	// clang-format on
++};
++static const struct v4l2_ctrl_config v4l2loopback_ctrl_timeoutimageio = {
++	// clang-format off
++	.ops	= &v4l2loopback_ctrl_ops,
++	.id	= CID_TIMEOUT_IMAGE_IO,
++	.name	= "timeout_image_io",
++	.type	= V4L2_CTRL_TYPE_BOOLEAN,
++	.min	= 0,
++	.max	= 1,
++	.step	= 1,
++	.def	= 0,
++	// clang-format on
++};
++
++/* module structures */
++struct v4l2loopback_private {
++	int device_nr;
++};
++
++/* TODO(vasaka) use typenames which are common to kernel, but first find out if
++ * it is needed */
++/* struct keeping state and settings of loopback device */
++
++struct v4l2l_buffer {
++	struct v4l2_buffer buffer;
++	struct list_head list_head;
++	int use_count;
++};
++
++struct v4l2_loopback_device {
++	struct v4l2_device v4l2_dev;
++	struct v4l2_ctrl_handler ctrl_handler;
++	struct video_device *vdev;
++	/* pixel and stream format */
++	struct v4l2_pix_format pix_format;
++	struct v4l2_captureparm capture_param;
++	unsigned long frame_jiffies;
++
++	/* ctrls */
++	int keep_format; /* CID_KEEP_FORMAT; stay ready_for_capture even when all
++			    openers close() the device */
++	int sustain_framerate; /* CID_SUSTAIN_FRAMERATE; duplicate frames to maintain
++				  (close to) nominal framerate */
++
++	/* buffers stuff */
++	u8 *image; /* pointer to actual buffers data */
++	dma_addr_t image_paddr; /* pointer to actual buffers data */
++	unsigned long int imagesize; /* size of buffers data */
++	int buffers_number; /* should not be big, 4 is a good choice */
++	struct v4l2l_buffer buffers[MAX_BUFFERS]; /* inner driver buffers */
++	int used_buffers; /* number of the actually used buffers */
++	int max_openers; /* how many times can this device be opened */
++
++	int write_position; /* number of last written frame + 1 */
++	struct list_head outbufs_list; /* buffers in output DQBUF order */
++	int bufpos2index
++		[MAX_BUFFERS]; /* mapping of (read/write_position % used_buffers)
++                        * to inner buffer index */
++	long buffer_size;
++
++	/* sustain_framerate stuff */
++	struct timer_list sustain_timer;
++	unsigned int reread_count;
++
++	/* timeout stuff */
++	unsigned long timeout_jiffies; /* CID_TIMEOUT; 0 means disabled */
++	int timeout_image_io; /* CID_TIMEOUT_IMAGE_IO; next opener will
++			       * read/write to timeout_image */
++	u8 *timeout_image; /* copy of it will be captured when timeout passes */
++	struct v4l2l_buffer timeout_image_buffer;
++	struct timer_list timeout_timer;
++	int timeout_happened;
++
++	/* sync stuff */
++	atomic_t open_count;
++
++	int ready_for_capture; /* set to the number of writers that opened the
++                                * device and negotiated format. */
++	int ready_for_output; /* set to true when no writer is currently attached
++			       * this differs slightly from !ready_for_capture,
++			       * e.g. when using fallback images */
++	int announce_all_caps; /* set to false, if device caps (OUTPUT/CAPTURE)
++                                * should only be announced if the resp. "ready"
++                                * flag is set; default=TRUE */
++	int gen_timestamp;	/*whether generate timestamp by kernel or not.*/
++
++
++	struct list_head queued_list;	/*list for capture queued buffer.*/
++	struct list_head done_list;	/*list for output queued buffer.*/
++
++	spinlock_t done_lock;
++	unsigned int output_sequence;
++
++
++	int max_width;
++	int max_height;
++
++	char card_label[32];
++
++	wait_queue_head_t read_event;
++	spinlock_t lock;
++};
++
++/* types of opener shows what opener wants to do with loopback */
++enum opener_type {
++	// clang-format off
++	UNNEGOTIATED	= 0,
++	READER		= 1,
++	WRITER		= 2,
++	// clang-format on
++};
++
++/* struct keeping state and type of opener */
++struct v4l2_loopback_opener {
++	enum opener_type type;
++	int vidioc_enum_frameintervals_calls;
++	int read_position; /* number of last processed frame + 1 or
++			    * write_position - 1 if reader went out of sync */
++	unsigned int reread_count;
++	struct v4l2_buffer *buffers;
++	int buffers_number; /* should not be big, 4 is a good choice */
++	int timeout_image_io;
++
++	struct v4l2_fh fh;
++};
++
++#define fh_to_opener(ptr) container_of((ptr), struct v4l2_loopback_opener, fh)
++
++/* this is heavily inspired by the bttv driver found in the linux kernel */
++struct v4l2l_format {
++	char *name;
++	int fourcc; /* video4linux 2 */
++	int depth; /* bit/pixel */
++	int flags;
++};
++/* set the v4l2l_format.flags to PLANAR for non-packed formats */
++#define FORMAT_FLAGS_PLANAR 0x01
++#define FORMAT_FLAGS_COMPRESSED 0x02
++
++static const struct v4l2l_format formats[] = {
++#include "v4l2loopback_formats.h"
++};
++
++static const unsigned int FORMATS = ARRAY_SIZE(formats);
++
++static char *fourcc2str(unsigned int fourcc, char buf[4])
++{
++	buf[0] = (fourcc >> 0) & 0xFF;
++	buf[1] = (fourcc >> 8) & 0xFF;
++	buf[2] = (fourcc >> 16) & 0xFF;
++	buf[3] = (fourcc >> 24) & 0xFF;
++
++	return buf;
++}
++
++static const struct v4l2l_format *format_by_fourcc(int fourcc)
++{
++	unsigned int i;
++
++	for (i = 0; i < FORMATS; i++) {
++		if (formats[i].fourcc == fourcc)
++			return formats + i;
++	}
++
++	dprintk("unsupported format '%c%c%c%c'\n", (fourcc >> 0) & 0xFF,
++		(fourcc >> 8) & 0xFF, (fourcc >> 16) & 0xFF,
++		(fourcc >> 24) & 0xFF);
++	return NULL;
++}
++
++static void pix_format_set_size(struct v4l2_pix_format *f,
++				const struct v4l2l_format *fmt,
++				unsigned int width, unsigned int height)
++{
++	f->width = width;
++	f->height = height;
++
++	if (fmt->flags & FORMAT_FLAGS_PLANAR) {
++		f->bytesperline = width; /* Y plane */
++		f->sizeimage = (width * height * fmt->depth) >> 3;
++	} else if (fmt->flags & FORMAT_FLAGS_COMPRESSED) {
++		/* doesn't make sense for compressed formats */
++		f->bytesperline = 0;
++		f->sizeimage = (width * height * fmt->depth) >> 3;
++	} else {
++		f->bytesperline = (width * fmt->depth) >> 3;
++		f->sizeimage = height * f->bytesperline;
++	}
++}
++
++static int set_timeperframe(struct v4l2_loopback_device *dev,
++			    struct v4l2_fract *tpf)
++{
++	if ((tpf->denominator < 1) || (tpf->numerator < 1)) {
++		return -EINVAL;
++	}
++	dev->capture_param.timeperframe = *tpf;
++	dev->frame_jiffies = max(1UL, msecs_to_jiffies(1000) * tpf->numerator /
++					      tpf->denominator);
++	return 0;
++}
++
++static struct v4l2_loopback_device *v4l2loopback_cd2dev(struct device *cd);
++
++/* device attributes */
++/* available via sysfs: /sys/devices/virtual/video4linux/video* */
++
++static ssize_t attr_show_format(struct device *cd,
++				struct device_attribute *attr, char *buf)
++{
++	/* gets the current format as "FOURCC:WxH@f/s", e.g. "YUYV:320x240@1000/30" */
++	struct v4l2_loopback_device *dev = v4l2loopback_cd2dev(cd);
++	const struct v4l2_fract *tpf;
++	char buf4cc[5], buf_fps[32];
++
++	if (!dev || !dev->ready_for_capture)
++		return 0;
++	tpf = &dev->capture_param.timeperframe;
++
++	fourcc2str(dev->pix_format.pixelformat, buf4cc);
++	buf4cc[4] = 0;
++	if (tpf->numerator == 1)
++		snprintf(buf_fps, sizeof(buf_fps), "%d", tpf->denominator);
++	else
++		snprintf(buf_fps, sizeof(buf_fps), "%d/%d", tpf->denominator,
++			 tpf->numerator);
++	return sprintf(buf, "%4s:%dx%d@%s\n", buf4cc, dev->pix_format.width,
++		       dev->pix_format.height, buf_fps);
++}
++
++static ssize_t attr_store_format(struct device *cd,
++				 struct device_attribute *attr, const char *buf,
++				 size_t len)
++{
++	struct v4l2_loopback_device *dev = v4l2loopback_cd2dev(cd);
++	int fps_num = 0, fps_den = 1;
++
++	/* only fps changing is supported */
++	if (sscanf(buf, "@%d/%d", &fps_num, &fps_den) > 0) {
++		struct v4l2_fract f = { .numerator = fps_den,
++					.denominator = fps_num };
++		int err = 0;
++		if ((err = set_timeperframe(dev, &f)) < 0)
++			return err;
++		return len;
++	}
++	return -EINVAL;
++}
++
++static DEVICE_ATTR(format, S_IRUGO | S_IWUSR, attr_show_format,
++		   attr_store_format);
++
++static ssize_t attr_show_buffers(struct device *cd,
++				 struct device_attribute *attr, char *buf)
++{
++	struct v4l2_loopback_device *dev = v4l2loopback_cd2dev(cd);
++
++	return sprintf(buf, "%d\n", dev->used_buffers);
++}
++
++static DEVICE_ATTR(buffers, S_IRUGO, attr_show_buffers, NULL);
++
++static ssize_t attr_show_maxopeners(struct device *cd,
++				    struct device_attribute *attr, char *buf)
++{
++	struct v4l2_loopback_device *dev = v4l2loopback_cd2dev(cd);
++
++	return sprintf(buf, "%d\n", dev->max_openers);
++}
++
++static ssize_t attr_store_maxopeners(struct device *cd,
++				     struct device_attribute *attr,
++				     const char *buf, size_t len)
++{
++	struct v4l2_loopback_device *dev = NULL;
++	unsigned long curr = 0;
++
++	if (kstrtoul(buf, 0, &curr))
++		return -EINVAL;
++
++	dev = v4l2loopback_cd2dev(cd);
++
++	if (dev->max_openers == curr)
++		return len;
++
++	if (dev->open_count.counter > curr) {
++		/* request to limit to less openers as are currently attached to us */
++		return -EINVAL;
++	}
++
++	dev->max_openers = (int)curr;
++
++	return len;
++}
++
++static DEVICE_ATTR(max_openers, S_IRUGO | S_IWUSR, attr_show_maxopeners,
++		   attr_store_maxopeners);
++
++static void v4l2loopback_remove_sysfs(struct video_device *vdev)
++{
++#define V4L2_SYSFS_DESTROY(x) device_remove_file(&vdev->dev, &dev_attr_##x)
++
++	if (vdev) {
++		V4L2_SYSFS_DESTROY(format);
++		V4L2_SYSFS_DESTROY(buffers);
++		V4L2_SYSFS_DESTROY(max_openers);
++		/* ... */
++	}
++}
++
++static void v4l2loopback_create_sysfs(struct video_device *vdev)
++{
++	int res = 0;
++
++#define V4L2_SYSFS_CREATE(x)                                                   \
++	res = device_create_file(&vdev->dev, &dev_attr_##x);                   \
++	if (res < 0)                                                           \
++	break
++	if (!vdev)
++		return;
++	do {
++		V4L2_SYSFS_CREATE(format);
++		V4L2_SYSFS_CREATE(buffers);
++		V4L2_SYSFS_CREATE(max_openers);
++		/* ... */
++	} while (0);
++
++	if (res >= 0)
++		return;
++	dev_err(&vdev->dev, "%s error: %d\n", __func__, res);
++}
++
++/* global module data */
++/* find a device based on it's device-number (e.g. '3' for /dev/video3) */
++struct v4l2loopback_lookup_cb_data {
++	int device_nr;
++	struct v4l2_loopback_device *device;
++};
++static int v4l2loopback_lookup_cb(int id, void *ptr, void *data)
++{
++	struct v4l2_loopback_device *device = ptr;
++	struct v4l2loopback_lookup_cb_data *cbdata = data;
++	if (cbdata && device && device->vdev) {
++		if (device->vdev->num == cbdata->device_nr) {
++			cbdata->device = device;
++			cbdata->device_nr = id;
++			return 1;
++		}
++	}
++	return 0;
++}
++static int v4l2loopback_lookup(int device_nr,
++			       struct v4l2_loopback_device **device)
++{
++	struct v4l2loopback_lookup_cb_data data = {
++		.device_nr = device_nr,
++		.device = NULL,
++	};
++	int err = idr_for_each(&v4l2loopback_index_idr, &v4l2loopback_lookup_cb,
++			       &data);
++	if (1 == err) {
++		if (device)
++			*device = data.device;
++		return data.device_nr;
++	}
++	return -ENODEV;
++}
++static struct v4l2_loopback_device *v4l2loopback_cd2dev(struct device *cd)
++{
++	struct video_device *loopdev = to_video_device(cd);
++	struct v4l2loopback_private *ptr =
++		(struct v4l2loopback_private *)video_get_drvdata(loopdev);
++	int nr = ptr->device_nr;
++
++	return idr_find(&v4l2loopback_index_idr, nr);
++}
++
++static struct v4l2_loopback_device *v4l2loopback_getdevice(struct file *f)
++{
++	struct video_device *loopdev = video_devdata(f);
++	struct v4l2loopback_private *ptr =
++		(struct v4l2loopback_private *)video_get_drvdata(loopdev);
++	int nr = ptr->device_nr;
++
++	return idr_find(&v4l2loopback_index_idr, nr);
++}
++
++/* forward declarations */
++static void init_buffers(struct v4l2_loopback_device *dev);
++static int allocate_buffers(struct v4l2_loopback_device *dev);
++static int free_buffers(struct v4l2_loopback_device *dev);
++static void try_free_buffers(struct v4l2_loopback_device *dev);
++static int allocate_timeout_image(struct v4l2_loopback_device *dev);
++static void check_timers(struct v4l2_loopback_device *dev);
++static const struct v4l2_file_operations v4l2_loopback_fops;
++static const struct v4l2_ioctl_ops v4l2_loopback_ioctl_ops;
++
++/* Queue helpers */
++/* next functions sets buffer flags and adjusts counters accordingly */
++static inline void set_done(struct v4l2l_buffer *buffer)
++{
++	buffer->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED;
++	buffer->buffer.flags |= V4L2_BUF_FLAG_DONE;
++}
++
++static inline void set_queued(struct v4l2l_buffer *buffer)
++{
++	buffer->buffer.flags &= ~V4L2_BUF_FLAG_DONE;
++	buffer->buffer.flags |= V4L2_BUF_FLAG_QUEUED;
++}
++
++static inline void unset_flags(struct v4l2l_buffer *buffer)
++{
++	buffer->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED;
++	buffer->buffer.flags &= ~V4L2_BUF_FLAG_DONE;
++}
++
++/* V4L2 ioctl caps and params calls */
++/* returns device capabilities
++ * called on VIDIOC_QUERYCAP
++ */
++static int vidioc_querycap(struct file *file, void *priv,
++			   struct v4l2_capability *cap)
++{
++	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
++	int labellen = (sizeof(cap->card) < sizeof(dev->card_label)) ?
++			       sizeof(cap->card) :
++			       sizeof(dev->card_label);
++	int device_nr =
++		((struct v4l2loopback_private *)video_get_drvdata(dev->vdev))
++			->device_nr;
++	__u32 capabilities = V4L2_CAP_STREAMING | V4L2_CAP_READWRITE;
++
++	strlcpy(cap->driver, "v4l2 loopback", sizeof(cap->driver));
++	snprintf(cap->card, labellen, dev->card_label);
++	snprintf(cap->bus_info, sizeof(cap->bus_info),
++		 "platform:v4l2loopback-%03d", device_nr);
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0)
++	/* since 3.1.0, the v4l2-core system is supposed to set the version */
++	cap->version = V4L2LOOPBACK_VERSION_CODE;
++#endif
++
++#ifdef V4L2_CAP_VIDEO_M2M
++	capabilities |= V4L2_CAP_VIDEO_M2M;
++#endif /* V4L2_CAP_VIDEO_M2M */
++
++	if (dev->announce_all_caps) {
++		capabilities |= V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT;
++	} else {
++		if (dev->ready_for_capture) {
++			capabilities |= V4L2_CAP_VIDEO_CAPTURE;
++		}
++		if (dev->ready_for_output) {
++			capabilities |= V4L2_CAP_VIDEO_OUTPUT;
++		}
++	}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)
++	dev->vdev->device_caps =
++#endif /* >=linux-4.7.0 */
++		cap->device_caps = cap->capabilities = capabilities;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)
++	cap->capabilities |= V4L2_CAP_DEVICE_CAPS;
++#endif
++
++	memset(cap->reserved, 0, sizeof(cap->reserved));
++	return 0;
++}
++
++static int vidioc_enum_framesizes(struct file *file, void *fh,
++				  struct v4l2_frmsizeenum *argp)
++{
++	struct v4l2_loopback_device *dev;
++
++	/* LATER: what does the index really  mean?
++	 * if it's about enumerating formats, we can safely ignore it
++	 * (CHECK)
++	 */
++
++	/* there can be only one... */
++	if (argp->index)
++		return -EINVAL;
++
++	dev = v4l2loopback_getdevice(file);
++	if (dev->ready_for_capture) {
++		/* format has already been negotiated
++		 * cannot change during runtime
++		 */
++		argp->type = V4L2_FRMSIZE_TYPE_DISCRETE;
++
++		argp->discrete.width = dev->pix_format.width;
++		argp->discrete.height = dev->pix_format.height;
++	} else {
++		/* if the format has not been negotiated yet, we accept anything
++		 */
++		argp->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
++
++		argp->stepwise.min_width = V4L2LOOPBACK_SIZE_MIN_WIDTH;
++		argp->stepwise.min_height = V4L2LOOPBACK_SIZE_MIN_HEIGHT;
++
++		argp->stepwise.max_width = dev->max_width;
++		argp->stepwise.max_height = dev->max_height;
++
++		argp->stepwise.step_width = 1;
++		argp->stepwise.step_height = 1;
++	}
++	return 0;
++}
++
++/* returns frameinterval (fps) for the set resolution
++ * called on VIDIOC_ENUM_FRAMEINTERVALS
++ */
++static int vidioc_enum_frameintervals(struct file *file, void *fh,
++				      struct v4l2_frmivalenum *argp)
++{
++	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
++	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
++
++	if (dev->ready_for_capture) {
++		if (opener->vidioc_enum_frameintervals_calls > 0)
++			return -EINVAL;
++		if (argp->width == dev->pix_format.width &&
++		    argp->height == dev->pix_format.height) {
++			argp->type = V4L2_FRMIVAL_TYPE_DISCRETE;
++			argp->discrete = dev->capture_param.timeperframe;
++			opener->vidioc_enum_frameintervals_calls++;
++			return 0;
++		}
++		return -EINVAL;
++	}
++	return 0;
++}
++
++/* ------------------ CAPTURE ----------------------- */
++
++/* returns device formats
++ * called on VIDIOC_ENUM_FMT, with v4l2_buf_type set to V4L2_BUF_TYPE_VIDEO_CAPTURE
++ */
++static int vidioc_enum_fmt_cap(struct file *file, void *fh,
++			       struct v4l2_fmtdesc *f)
++{
++	struct v4l2_loopback_device *dev;
++	MARK();
++
++	dev = v4l2loopback_getdevice(file);
++
++	if (f->index)
++		return -EINVAL;
++	if (dev->ready_for_capture) {
++		const __u32 format = dev->pix_format.pixelformat;
++
++		snprintf(f->description, sizeof(f->description), "[%c%c%c%c]",
++			 (format >> 0) & 0xFF, (format >> 8) & 0xFF,
++			 (format >> 16) & 0xFF, (format >> 24) & 0xFF);
++
++		f->pixelformat = dev->pix_format.pixelformat;
++	} else {
++		return -EINVAL;
++	}
++	f->flags = 0;
++	MARK();
++	return 0;
++}
++
++/* returns current video format format fmt
++ * called on VIDIOC_G_FMT, with v4l2_buf_type set to V4L2_BUF_TYPE_VIDEO_CAPTURE
++ */
++static int vidioc_g_fmt_cap(struct file *file, void *priv,
++			    struct v4l2_format *fmt)
++{
++	struct v4l2_loopback_device *dev;
++	MARK();
++
++	dev = v4l2loopback_getdevice(file);
++
++	if (!dev->ready_for_capture)
++		return -EINVAL;
++
++	fmt->fmt.pix = dev->pix_format;
++	MARK();
++	return 0;
++}
++
++/* checks if it is OK to change to format fmt;
++ * actual check is done by inner_try_fmt_cap
++ * just checking that pixelformat is OK and set other parameters, app should
++ * obey this decision
++ * called on VIDIOC_TRY_FMT, with v4l2_buf_type set to V4L2_BUF_TYPE_VIDEO_CAPTURE
++ */
++static int vidioc_try_fmt_cap(struct file *file, void *priv,
++			      struct v4l2_format *fmt)
++{
++	struct v4l2_loopback_device *dev;
++	char buf[5];
++
++	dev = v4l2loopback_getdevice(file);
++
++	if (0 == dev->ready_for_capture) {
++		dprintk("setting fmt_cap not possible yet\n");
++		return -EBUSY;
++	}
++
++	if (fmt->fmt.pix.pixelformat != dev->pix_format.pixelformat)
++		return -EINVAL;
++
++	fmt->fmt.pix = dev->pix_format;
++
++	buf[4] = 0;
++	dprintk("capFOURCC=%s\n", fourcc2str(dev->pix_format.pixelformat, buf));
++	return 0;
++}
++
++/* sets new output format, if possible
++ * actually format is set  by input and we even do not check it, just return
++ * current one, but it is possible to set subregions of input TODO(vasaka)
++ * called on VIDIOC_S_FMT, with v4l2_buf_type set to V4L2_BUF_TYPE_VIDEO_CAPTURE
++ */
++static int vidioc_s_fmt_cap(struct file *file, void *priv,
++			    struct v4l2_format *fmt)
++{
++	return vidioc_try_fmt_cap(file, priv, fmt);
++}
++
++/* ------------------ OUTPUT ----------------------- */
++
++/* returns device formats;
++ * LATER: allow all formats
++ * called on VIDIOC_ENUM_FMT, with v4l2_buf_type set to V4L2_BUF_TYPE_VIDEO_OUTPUT
++ */
++static int vidioc_enum_fmt_out(struct file *file, void *fh,
++			       struct v4l2_fmtdesc *f)
++{
++	struct v4l2_loopback_device *dev;
++	const struct v4l2l_format *fmt;
++
++	dev = v4l2loopback_getdevice(file);
++
++	if (dev->ready_for_capture) {
++		const __u32 format = dev->pix_format.pixelformat;
++
++		/* format has been fixed by the writer, so only one single format is supported */
++		if (f->index)
++			return -EINVAL;
++
++		fmt = format_by_fourcc(format);
++		if (NULL == fmt)
++			return -EINVAL;
++
++		f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++		/* f->flags = ??; */
++		snprintf(f->description, sizeof(f->description), "%s",
++			 fmt->name);
++
++		f->pixelformat = dev->pix_format.pixelformat;
++	} else {
++		/* fill in a dummy format */
++		/* coverity[unsigned_compare] */
++		if (f->index < 0 || f->index >= FORMATS)
++			return -EINVAL;
++
++		fmt = &formats[f->index];
++
++		f->pixelformat = fmt->fourcc;
++		snprintf(f->description, sizeof(f->description), "%s",
++			 fmt->name);
++	}
++	f->flags = 0;
++
++	return 0;
++}
++
++/* returns current video format format fmt */
++/* NOTE: this is called from the producer
++ * so if format has not been negotiated yet,
++ * it should return ALL of available formats,
++ * called on VIDIOC_G_FMT, with v4l2_buf_type set to V4L2_BUF_TYPE_VIDEO_OUTPUT
++ */
++static int vidioc_g_fmt_out(struct file *file, void *priv,
++			    struct v4l2_format *fmt)
++{
++	struct v4l2_loopback_device *dev;
++	MARK();
++
++	dev = v4l2loopback_getdevice(file);
++
++	/*
++	 * LATER: this should return the currently valid format
++	 * gstreamer doesn't like it, if this returns -EINVAL, as it
++	 * then concludes that there is _no_ valid format
++	 * CHECK whether this assumption is wrong,
++	 * or whether we have to always provide a valid format
++	 */
++
++	fmt->fmt.pix = dev->pix_format;
++	return 0;
++}
++
++/* checks if it is OK to change to format fmt;
++ * if format is negotiated do not change it
++ * called on VIDIOC_TRY_FMT with v4l2_buf_type set to V4L2_BUF_TYPE_VIDEO_OUTPUT
++ */
++static int vidioc_try_fmt_out(struct file *file, void *priv,
++			      struct v4l2_format *fmt)
++{
++	struct v4l2_loopback_device *dev;
++	MARK();
++
++	dev = v4l2loopback_getdevice(file);
++
++	/* TODO(vasaka) loopback does not care about formats writer want to set,
++	 * maybe it is a good idea to restrict format somehow */
++	if (dev->ready_for_capture) {
++		fmt->fmt.pix = dev->pix_format;
++	} else {
++		__u32 w = fmt->fmt.pix.width;
++		__u32 h = fmt->fmt.pix.height;
++		__u32 pixfmt = fmt->fmt.pix.pixelformat;
++		const struct v4l2l_format *format = format_by_fourcc(pixfmt);
++
++		if (w > dev->max_width)
++			w = dev->max_width;
++		if (h > dev->max_height)
++			h = dev->max_height;
++
++		dprintk("trying image %dx%d\n", w, h);
++
++		if (w < 1)
++			w = V4L2LOOPBACK_SIZE_DEFAULT_WIDTH;
++
++		if (h < 1)
++			h = V4L2LOOPBACK_SIZE_DEFAULT_HEIGHT;
++
++		if (NULL == format)
++			format = &formats[0];
++
++		pix_format_set_size(&fmt->fmt.pix, format, w, h);
++
++		fmt->fmt.pix.pixelformat = format->fourcc;
++		fmt->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB;
++
++		if (V4L2_FIELD_ANY == fmt->fmt.pix.field)
++			fmt->fmt.pix.field = V4L2_FIELD_NONE;
++
++		/* FIXXME: try_fmt should never modify the device-state */
++		dev->pix_format = fmt->fmt.pix;
++	}
++	return 0;
++}
++
++/* sets new output format, if possible;
++ * allocate data here because we do not know if it will be streaming or
++ * read/write IO
++ * called on VIDIOC_S_FMT with v4l2_buf_type set to V4L2_BUF_TYPE_VIDEO_OUTPUT
++ */
++static int vidioc_s_fmt_out(struct file *file, void *priv,
++			    struct v4l2_format *fmt)
++{
++	struct v4l2_loopback_device *dev;
++	char buf[5];
++	int ret;
++	MARK();
++
++	dev = v4l2loopback_getdevice(file);
++	ret = vidioc_try_fmt_out(file, priv, fmt);
++
++	dprintk("s_fmt_out(%d) %d...%d\n", ret, dev->ready_for_capture,
++		dev->pix_format.sizeimage);
++
++	buf[4] = 0;
++	dprintk("outFOURCC=%s\n", fourcc2str(dev->pix_format.pixelformat, buf));
++
++	if (ret < 0)
++		return ret;
++
++	if (!dev->ready_for_capture) {
++		dev->buffer_size = PAGE_ALIGN(dev->pix_format.sizeimage);
++		fmt->fmt.pix.sizeimage = dev->buffer_size;
++		allocate_buffers(dev);
++	}
++	return ret;
++}
++
++// #define V4L2L_OVERLAY
++#ifdef V4L2L_OVERLAY
++/* ------------------ OVERLAY ----------------------- */
++/* currently unsupported */
++/* GSTreamer's v4l2sink is buggy, as it requires the overlay to work
++ * while it should only require it, if overlay is requested
++ * once the gstreamer element is fixed, remove the overlay dummies
++ */
++#warning OVERLAY dummies
++static int vidioc_g_fmt_overlay(struct file *file, void *priv,
++				struct v4l2_format *fmt)
++{
++	return 0;
++}
++
++static int vidioc_s_fmt_overlay(struct file *file, void *priv,
++				struct v4l2_format *fmt)
++{
++	return 0;
++}
++#endif /* V4L2L_OVERLAY */
++
++/* ------------------ PARAMs ----------------------- */
++
++/* get some data flow parameters, only capability, fps and readbuffers has
++ * effect on this driver
++ * called on VIDIOC_G_PARM
++ */
++static int vidioc_g_parm(struct file *file, void *priv,
++			 struct v4l2_streamparm *parm)
++{
++	/* do not care about type of opener, hope these enums would always be
++	 * compatible */
++	struct v4l2_loopback_device *dev;
++	MARK();
++
++	dev = v4l2loopback_getdevice(file);
++	parm->parm.capture = dev->capture_param;
++	return 0;
++}
++
++/* get some data flow parameters, only capability, fps and readbuffers has
++ * effect on this driver
++ * called on VIDIOC_S_PARM
++ */
++static int vidioc_s_parm(struct file *file, void *priv,
++			 struct v4l2_streamparm *parm)
++{
++	struct v4l2_loopback_device *dev;
++	int err = 0;
++	MARK();
++
++	dev = v4l2loopback_getdevice(file);
++	dprintk("vidioc_s_parm called frate=%d/%d\n",
++		parm->parm.capture.timeperframe.numerator,
++		parm->parm.capture.timeperframe.denominator);
++
++	switch (parm->type) {
++	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++		if ((err = set_timeperframe(
++			     dev, &parm->parm.capture.timeperframe)) < 0)
++			return err;
++		break;
++	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++		if ((err = set_timeperframe(
++			     dev, &parm->parm.capture.timeperframe)) < 0)
++			return err;
++		break;
++	default:
++		return -1;
++	}
++
++	parm->parm.capture = dev->capture_param;
++	return 0;
++}
++
++#ifdef V4L2LOOPBACK_WITH_STD
++/* sets a tv standard, actually we do not need to handle this any special way
++ * added to support effecttv
++ * called on VIDIOC_S_STD
++ */
++static int vidioc_s_std(struct file *file, void *fh, v4l2_std_id *_std)
++{
++	v4l2_std_id req_std = 0, supported_std = 0;
++	const v4l2_std_id all_std = V4L2_STD_ALL, no_std = 0;
++
++	if (_std) {
++		req_std = *_std;
++		*_std = all_std;
++	}
++
++	/* we support everything in V4L2_STD_ALL, but not more... */
++	supported_std = (all_std & req_std);
++	if (no_std == supported_std)
++		return -EINVAL;
++
++	return 0;
++}
++
++/* gets a fake video standard
++ * called on VIDIOC_G_STD
++ */
++static int vidioc_g_std(struct file *file, void *fh, v4l2_std_id *norm)
++{
++	if (norm)
++		*norm = V4L2_STD_ALL;
++	return 0;
++}
++/* gets a fake video standard
++ * called on VIDIOC_QUERYSTD
++ */
++static int vidioc_querystd(struct file *file, void *fh, v4l2_std_id *norm)
++{
++	if (norm)
++		*norm = V4L2_STD_ALL;
++	return 0;
++}
++#endif /* V4L2LOOPBACK_WITH_STD */
++
++/* get ctrls info
++ * called on VIDIOC_QUERYCTRL
++ */
++static int vidioc_queryctrl(struct file *file, void *fh,
++			    struct v4l2_queryctrl *q)
++{
++	const struct v4l2_ctrl_config *cnf = 0;
++	switch (q->id) {
++	case CID_KEEP_FORMAT:
++		cnf = &v4l2loopback_ctrl_keepformat;
++		break;
++	case CID_SUSTAIN_FRAMERATE:
++		cnf = &v4l2loopback_ctrl_sustainframerate;
++		break;
++	case CID_TIMEOUT:
++		cnf = &v4l2loopback_ctrl_timeout;
++		break;
++	case CID_TIMEOUT_IMAGE_IO:
++		cnf = &v4l2loopback_ctrl_timeoutimageio;
++		break;
++	default:
++		return -EINVAL;
++	}
++	if (!cnf)
++		BUG();
++
++	strcpy(q->name, cnf->name);
++	q->default_value = cnf->def;
++	q->type = cnf->type;
++	q->minimum = cnf->min;
++	q->maximum = cnf->max;
++	q->step = cnf->step;
++
++	memset(q->reserved, 0, sizeof(q->reserved));
++	return 0;
++}
++
++static int vidioc_g_ctrl(struct file *file, void *fh, struct v4l2_control *c)
++{
++	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
++
++	switch (c->id) {
++	case CID_KEEP_FORMAT:
++		c->value = dev->keep_format;
++		break;
++	case CID_SUSTAIN_FRAMERATE:
++		c->value = dev->sustain_framerate;
++		break;
++	case CID_TIMEOUT:
++		c->value = jiffies_to_msecs(dev->timeout_jiffies);
++		break;
++	case CID_TIMEOUT_IMAGE_IO:
++		c->value = dev->timeout_image_io;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int v4l2loopback_set_ctrl(struct v4l2_loopback_device *dev, u32 id,
++				 s64 val)
++{
++	switch (id) {
++	case CID_KEEP_FORMAT:
++		if (val < 0 || val > 1)
++			return -EINVAL;
++		dev->keep_format = val;
++		try_free_buffers(dev); /* will only free buffers if !keep_format */
++		break;
++	case CID_SUSTAIN_FRAMERATE:
++		if (val < 0 || val > 1)
++			return -EINVAL;
++		spin_lock_bh(&dev->lock);
++		dev->sustain_framerate = val;
++		check_timers(dev);
++		spin_unlock_bh(&dev->lock);
++		break;
++	case CID_TIMEOUT:
++		if (val < 0 || val > MAX_TIMEOUT)
++			return -EINVAL;
++		spin_lock_bh(&dev->lock);
++		dev->timeout_jiffies = msecs_to_jiffies(val);
++		check_timers(dev);
++		spin_unlock_bh(&dev->lock);
++		allocate_timeout_image(dev);
++		break;
++	case CID_TIMEOUT_IMAGE_IO:
++		if (val < 0 || val > 1)
++			return -EINVAL;
++		dev->timeout_image_io = val;
++		break;
++	default:
++		return -EINVAL;
++	}
++	return 0;
++}
++
++static int v4l2loopback_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_loopback_device *dev = container_of(
++		ctrl->handler, struct v4l2_loopback_device, ctrl_handler);
++	return v4l2loopback_set_ctrl(dev, ctrl->id, ctrl->val);
++}
++static int vidioc_s_ctrl(struct file *file, void *fh, struct v4l2_control *c)
++{
++	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
++	return v4l2loopback_set_ctrl(dev, c->id, c->value);
++}
++
++/* returns set of device outputs, in our case there is only one
++ * called on VIDIOC_ENUMOUTPUT
++ */
++static int vidioc_enum_output(struct file *file, void *fh,
++			      struct v4l2_output *outp)
++{
++	__u32 index = outp->index;
++	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
++	MARK();
++
++	if (!dev->announce_all_caps && !dev->ready_for_output)
++		return -ENOTTY;
++
++	if (0 != index)
++		return -EINVAL;
++
++	/* clear all data (including the reserved fields) */
++	memset(outp, 0, sizeof(*outp));
++
++	outp->index = index;
++	strlcpy(outp->name, "loopback in", sizeof(outp->name));
++	outp->type = V4L2_OUTPUT_TYPE_ANALOG;
++	outp->audioset = 0;
++	outp->modulator = 0;
++#ifdef V4L2LOOPBACK_WITH_STD
++	outp->std = V4L2_STD_ALL;
++#ifdef V4L2_OUT_CAP_STD
++	outp->capabilities |= V4L2_OUT_CAP_STD;
++#endif /*  V4L2_OUT_CAP_STD */
++#endif /* V4L2LOOPBACK_WITH_STD */
++
++	return 0;
++}
++
++/* which output is currently active,
++ * called on VIDIOC_G_OUTPUT
++ */
++static int vidioc_g_output(struct file *file, void *fh, unsigned int *i)
++{
++	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
++	if (!dev->announce_all_caps && !dev->ready_for_output)
++		return -ENOTTY;
++	if (i)
++		*i = 0;
++	return 0;
++}
++
++/* set output, can make sense if we have more than one video src,
++ * called on VIDIOC_S_OUTPUT
++ */
++static int vidioc_s_output(struct file *file, void *fh, unsigned int i)
++{
++	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
++	if (!dev->announce_all_caps && !dev->ready_for_output)
++		return -ENOTTY;
++
++	if (i)
++		return -EINVAL;
++
++	return 0;
++}
++
++/* returns set of device inputs, in our case there is only one,
++ * but later I may add more
++ * called on VIDIOC_ENUMINPUT
++ */
++static int vidioc_enum_input(struct file *file, void *fh,
++			     struct v4l2_input *inp)
++{
++	__u32 index = inp->index;
++	MARK();
++
++	if (0 != index)
++		return -EINVAL;
++
++	/* clear all data (including the reserved fields) */
++	memset(inp, 0, sizeof(*inp));
++
++	inp->index = index;
++	strlcpy(inp->name, "loopback", sizeof(inp->name));
++	inp->type = V4L2_INPUT_TYPE_CAMERA;
++	inp->audioset = 0;
++	inp->tuner = 0;
++	inp->status = 0;
++
++#ifdef V4L2LOOPBACK_WITH_STD
++	inp->std = V4L2_STD_ALL;
++#ifdef V4L2_IN_CAP_STD
++	inp->capabilities |= V4L2_IN_CAP_STD;
++#endif
++#endif /* V4L2LOOPBACK_WITH_STD */
++
++	return 0;
++}
++
++/* which input is currently active,
++ * called on VIDIOC_G_INPUT
++ */
++static int vidioc_g_input(struct file *file, void *fh, unsigned int *i)
++{
++	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
++	if (!dev->announce_all_caps && !dev->ready_for_capture)
++		return -ENOTTY;
++	if (i)
++		*i = 0;
++	return 0;
++}
++
++/* set input, can make sense if we have more than one video src,
++ * called on VIDIOC_S_INPUT
++ */
++static int vidioc_s_input(struct file *file, void *fh, unsigned int i)
++{
++	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
++	if (!dev->announce_all_caps && !dev->ready_for_capture)
++		return -ENOTTY;
++	if (i == 0)
++		return 0;
++	return -EINVAL;
++}
++
++/* --------------- V4L2 ioctl buffer related calls ----------------- */
++
++/* negotiate buffer type
++ * only mmap streaming supported
++ * called on VIDIOC_REQBUFS
++ */
++static int vidioc_reqbufs(struct file *file, void *fh,
++			  struct v4l2_requestbuffers *b)
++{
++	struct v4l2_loopback_device *dev;
++	struct v4l2_loopback_opener *opener;
++	int i;
++	MARK();
++
++	dev = v4l2loopback_getdevice(file);
++	opener = fh_to_opener(fh);
++	dev->gen_timestamp = 0;
++
++	dprintk("reqbufs: %d\t%d=%d\n", b->memory, b->count,
++		dev->buffers_number);
++	if (opener->timeout_image_io) {
++		if (b->memory != V4L2_MEMORY_MMAP)
++			return -EINVAL;
++		b->count = 1;
++		return 0;
++	}
++
++	INIT_LIST_HEAD(&dev->queued_list);
++	INIT_LIST_HEAD(&dev->done_list);
++
++	switch (b->memory) {
++	case V4L2_MEMORY_MMAP:
++		/* do nothing here, buffers are always allocated */
++		if (b->count < 1 || dev->buffers_number < 1)
++			return 0;
++
++
++		if(b->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
++			if(b->count > dev->used_buffers) {
++				b->count = dev->used_buffers;
++			}
++		} else {
++			/*OUTPUT*/
++			if (b->count > dev->buffers_number)
++				b->count = dev->buffers_number;
++
++		}
++
++#if 0
++		/* make sure that outbufs_list contains buffers from 0 to used_buffers-1
++		 * actually, it will have been already populated via v4l2_loopback_init()
++		 * at this point */
++		if (list_empty(&dev->outbufs_list)) {
++			for (i = 0; i < dev->used_buffers; ++i)
++				list_add_tail(&dev->buffers[i].list_head,
++					      &dev->outbufs_list);
++		}
++#endif
++
++#if 0
++
++		/* also, if dev->used_buffers is going to be decreased, we should remove
++		 * out-of-range buffers from outbufs_list, and fix bufpos2index mapping */
++		if (b->count < dev->used_buffers) {
++			struct v4l2l_buffer *pos, *n;
++
++			list_for_each_entry_safe (pos, n, &dev->outbufs_list,
++						  list_head) {
++				if (pos->buffer.index >= b->count)
++					list_del(&pos->list_head);
++			}
++
++			/* after we update dev->used_buffers, buffers in outbufs_list will
++			 * correspond to dev->write_position + [0;b->count-1] range */
++			i = dev->write_position;
++			list_for_each_entry (pos, &dev->outbufs_list,
++					     list_head) {
++				dev->bufpos2index[i % b->count] =
++					pos->buffer.index;
++				++i;
++			}
++		}
++#endif
++		opener->buffers_number = b->count;
++		if (opener->buffers_number < dev->used_buffers)
++			dev->used_buffers = opener->buffers_number;
++
++		init_buffers(dev);
++		return 0;
++	default:
++		return -EINVAL;
++	}
++}
++
++/* returns buffer asked for;
++ * give app as many buffers as it wants, if it less than MAX,
++ * but map them in our inner buffers
++ * called on VIDIOC_QUERYBUF
++ */
++static int vidioc_querybuf(struct file *file, void *fh, struct v4l2_buffer *b)
++{
++	enum v4l2_buf_type type;
++	int index;
++	struct v4l2_loopback_device *dev;
++	struct v4l2_loopback_opener *opener;
++
++	MARK();
++
++	type = b->type;
++	index = b->index;
++	dev = v4l2loopback_getdevice(file);
++	opener = fh_to_opener(fh);
++
++	if ((b->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
++	    (b->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)) {
++		return -EINVAL;
++	}
++	if (b->index > max_buffers)
++		return -EINVAL;
++
++	if (opener->timeout_image_io)
++		*b = dev->timeout_image_buffer.buffer;
++	else
++		*b = dev->buffers[b->index % dev->used_buffers].buffer;
++
++	b->type = type;
++	b->index = index;
++	dprintkrw("buffer type: %d (of %d with size=%ld)\n", b->memory,
++		  dev->buffers_number, dev->buffer_size);
++
++	/*  Hopefully fix 'DQBUF return bad index if queue bigger then 2 for capture'
++            https://github.com/umlaeute/v4l2loopback/issues/60 */
++	b->flags &= ~V4L2_BUF_FLAG_DONE;
++	b->flags |= V4L2_BUF_FLAG_QUEUED;
++
++	return 0;
++}
++
++static void buffer_written(struct v4l2_loopback_device *dev,
++			   struct v4l2l_buffer *buf)
++{
++	del_timer_sync(&dev->sustain_timer);
++	del_timer_sync(&dev->timeout_timer);
++	spin_lock_bh(&dev->lock);
++
++	dev->bufpos2index[dev->write_position % dev->used_buffers] =
++		buf->buffer.index;
++	list_move_tail(&buf->list_head, &dev->outbufs_list);
++	++dev->write_position;
++	dev->reread_count = 0;
++
++	check_timers(dev);
++	spin_unlock_bh(&dev->lock);
++}
++
++/* put buffer to queue
++ * called on VIDIOC_QBUF
++ */
++static int vidioc_qbuf(struct file *file, void *fh, struct v4l2_buffer *buf)
++{
++	struct v4l2_loopback_device *dev;
++	struct v4l2_loopback_opener *opener;
++	struct v4l2l_buffer *b;
++	int index;
++	unsigned long flags;
++
++	dev = v4l2loopback_getdevice(file);
++	opener = fh_to_opener(fh);
++
++	if (buf->index > max_buffers)
++		return -EINVAL;
++	if (opener->timeout_image_io)
++		return 0;
++
++	index = buf->index % dev->used_buffers;
++	b = &dev->buffers[index];
++
++	switch (buf->type) {
++	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++
++		spin_lock_irqsave(&dev->done_lock, flags);
++		set_queued(b);
++		list_add_tail(&b->list_head, &dev->queued_list);
++		spin_unlock_irqrestore(&dev->done_lock, flags);
++
++		dprintkrw("[capture] qbuf: %d, b: %x, add_to queued_list.\n", buf->index, b);
++		return 0;
++	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++
++		if(!(b->buffer.flags & V4L2_BUF_FLAG_QUEUED)) {
++			printk("[output] qbuf [%d] without V4L2_BUF_FLAG_QUEUED.\n", b->buffer.index);
++			return -EINVAL;
++		}
++
++		v4l2l_get_timestamp(&b->buffer);
++		b->buffer.bytesused = buf->bytesused;
++		b->buffer.sequence = dev->output_sequence ++;
++
++		spin_lock_irqsave(&dev->done_lock, flags);
++		set_done(b);
++		list_add_tail(&b->list_head, &dev->done_list);
++
++		dprintkrw("[output] qbuf: %d, b: %x, add_to done_list\n", b->buffer.index, b);
++		spin_unlock_irqrestore(&dev->done_lock, flags);
++
++		wake_up_all(&dev->read_event);
++		return 0;
++	default:
++		return -EINVAL;
++	}
++}
++
++static int can_read(struct v4l2_loopback_device *dev,
++		    struct v4l2_loopback_opener *opener)
++{
++	int ret = 0;
++
++	ret =  (!list_empty(&dev->done_list) || dev->ready_for_output);
++
++	return ret;
++}
++
++/* put buffer to dequeue
++ * called on VIDIOC_DQBUF
++ */
++static int vidioc_dqbuf(struct file *file, void *fh, struct v4l2_buffer *buf)
++{
++	struct v4l2_loopback_device *dev;
++	struct v4l2_loopback_opener *opener;
++	int index;
++	struct v4l2l_buffer *b;
++	unsigned long flags;
++
++	dev = v4l2loopback_getdevice(file);
++	opener = fh_to_opener(fh);
++	if (opener->timeout_image_io) {
++		*buf = dev->timeout_image_buffer.buffer;
++		return 0;
++	}
++
++	switch (buf->type) {
++	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++
++		wait_event_interruptible(dev->read_event, (!list_empty(&dev->done_list) || dev->ready_for_output));
++		if(dev->ready_for_output) {
++			printk("output is not streaming!\n");
++			return -EINVAL;
++		}
++
++		spin_lock_irqsave(&dev->done_lock, flags);
++
++		b = list_first_entry_or_null(&dev->done_list, struct v4l2l_buffer, list_head);
++
++		if(!b) {
++			printk("no available buffer on done_list.!\n");
++			spin_unlock_irqrestore(&dev->done_lock, flags);
++			return -EINVAL;
++		}
++
++		/*remove from done list*/
++		list_del(&b->list_head);
++
++		unset_flags(b);
++		*buf = b->buffer; //dev->buffers[index].buffer;
++		spin_unlock_irqrestore(&dev->done_lock, flags);
++
++		dprintkrw("[capture] [dbuf: %x index: %d - %d userptr: %x]: tv_sec: %d, tv_usec: %d, sequence: %d\n", b, index, buf->index, buf->m.userptr, buf->timestamp.tv_sec, buf->timestamp.tv_usec, buf->sequence);
++		return 0;
++	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++
++		spin_lock_irqsave(&dev->done_lock, flags);
++		b = list_first_entry_or_null(&dev->queued_list, struct v4l2l_buffer, list_head);
++		if(!b) {
++			spin_unlock_irqrestore(&dev->done_lock, flags);
++			return -EINVAL;
++		}
++
++		dprintkrw("[output] dqbuf get b: %x, b->buffer.index: %d, b->buffer.flags: %x\n", b, b->buffer.index, b->buffer.flags);
++
++		list_del(&b->list_head);
++		spin_unlock_irqrestore(&dev->done_lock, flags);
++
++		*buf = b->buffer;
++		buf->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
++		return 0;
++	default:
++		return -EINVAL;
++	}
++}
++
++/* ------------- STREAMING ------------------- */
++
++/* start streaming
++ * called on VIDIOC_STREAMON
++ */
++static int vidioc_streamon(struct file *file, void *fh, enum v4l2_buf_type type)
++{
++	struct v4l2_loopback_device *dev;
++	struct v4l2_loopback_opener *opener;
++	MARK();
++
++	dev = v4l2loopback_getdevice(file);
++	opener = fh_to_opener(fh);
++
++	switch (type) {
++	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++		opener->type = WRITER;
++		dev->ready_for_output = 0;
++		if (!dev->ready_for_capture) {
++			int ret = allocate_buffers(dev);
++			if (ret < 0)
++				return ret;
++		}
++		dev->ready_for_capture++;
++		return 0;
++	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++		opener->type = READER;
++		if (!dev->ready_for_capture)
++			return -EIO;
++		return 0;
++	default:
++		return -EINVAL;
++	}
++	return -EINVAL;
++}
++
++/* stop streaming
++ * called on VIDIOC_STREAMOFF
++ */
++static int vidioc_streamoff(struct file *file, void *fh,
++			    enum v4l2_buf_type type)
++{
++	struct v4l2_loopback_device *dev;
++	MARK();
++	dprintk("%d\n", type);
++
++	dev = v4l2loopback_getdevice(file);
++
++	switch (type) {
++	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++		if (dev->ready_for_capture > 0)
++			dev->ready_for_capture--;
++		return 0;
++	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++		return 0;
++	default:
++		return -EINVAL;
++	}
++	return -EINVAL;
++}
++
++#ifdef CONFIG_VIDEO_V4L1_COMPAT
++static int vidiocgmbuf(struct file *file, void *fh, struct video_mbuf *p)
++{
++	struct v4l2_loopback_device *dev;
++	MARK();
++
++	dev = v4l2loopback_getdevice(file);
++	p->frames = dev->buffers_number;
++	p->offsets[0] = 0;
++	p->offsets[1] = 0;
++	p->size = dev->buffer_size;
++	return 0;
++}
++#endif
++
++static int vidioc_subscribe_event(struct v4l2_fh *fh,
++				  const struct v4l2_event_subscription *sub)
++{
++	switch (sub->type) {
++	case V4L2_EVENT_CTRL:
++		return v4l2_ctrl_subscribe_event(fh, sub);
++	}
++
++	return -EINVAL;
++}
++
++/* file operations */
++static void vm_open(struct vm_area_struct *vma)
++{
++	struct v4l2l_buffer *buf;
++	MARK();
++
++	buf = vma->vm_private_data;
++	buf->use_count++;
++}
++
++static void vm_close(struct vm_area_struct *vma)
++{
++	struct v4l2l_buffer *buf;
++	MARK();
++
++	buf = vma->vm_private_data;
++	buf->use_count--;
++}
++
++static struct vm_operations_struct vm_ops = {
++	.open = vm_open,
++	.close = vm_close,
++};
++
++#ifdef USING_DMA_ALLOC_BUFFER
++static int dma_mmap_noncoherent(struct device *dev, struct vm_area_struct *vma,
++		void *cpu_addr, dma_addr_t dma_addr, size_t size)
++{
++	int ret = -ENXIO;
++	unsigned long user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
++	unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
++	unsigned long pfn = page_to_pfn(virt_to_page(cpu_addr));
++	unsigned long off = vma->vm_pgoff;
++
++	pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
++	pgprot_val(vma->vm_page_prot) |= _CACHE_CACHABLE_NONCOHERENT;
++
++	if (off < count && user_count <= (count - off)) {
++
++		ret = remap_pfn_range(vma, vma->vm_start,
++				pfn + off,
++				user_count << PAGE_SHIFT,
++				vma->vm_page_prot);
++	}
++
++	return ret;
++}
++#endif
++
++static int v4l2_loopback_mmap(struct file *file, struct vm_area_struct *vma)
++{
++	unsigned long addr;
++	unsigned long addr_p;
++	unsigned long start;
++	unsigned long size;
++	struct v4l2_loopback_device *dev;
++	struct v4l2_loopback_opener *opener;
++	struct v4l2l_buffer *buffer = NULL;
++	int ret = 0;
++	MARK();
++
++	start = (unsigned long)vma->vm_start;
++	size = (unsigned long)(vma->vm_end - vma->vm_start);
++
++	dev = v4l2loopback_getdevice(file);
++	opener = fh_to_opener(file->private_data);
++
++	if (size > dev->buffer_size) {
++		dprintk("userspace tries to mmap too much, fail\n");
++		return -EINVAL;
++	}
++	if (opener->timeout_image_io) {
++		/* we are going to map the timeout_image_buffer */
++		if ((vma->vm_pgoff << PAGE_SHIFT) !=
++		    dev->buffer_size * MAX_BUFFERS) {
++			dprintk("invalid mmap offset for timeout_image_io mode\n");
++			return -EINVAL;
++		}
++	} else if ((vma->vm_pgoff << PAGE_SHIFT) >
++		   dev->buffer_size * (dev->buffers_number - 1)) {
++		dprintk("userspace tries to mmap too far, fail\n");
++		return -EINVAL;
++	}
++
++	/* FIXXXXXME: allocation should not happen here! */
++	if (NULL == dev->image)
++		if (allocate_buffers(dev) < 0)
++			return -EINVAL;
++
++	if (opener->timeout_image_io) {
++		buffer = &dev->timeout_image_buffer;
++		addr = (unsigned long)dev->timeout_image;
++	} else {
++		int i;
++		for (i = 0; i < dev->buffers_number; ++i) {
++			buffer = &dev->buffers[i];
++			if ((buffer->buffer.m.offset >> PAGE_SHIFT) ==
++			    vma->vm_pgoff)
++				break;
++		}
++
++		if (NULL == buffer)
++			return -EINVAL;
++
++		addr = (unsigned long)dev->image +
++		       (vma->vm_pgoff << PAGE_SHIFT);
++#ifdef USING_DMA_ALLOC_BUFFER
++		// TODO:
++		addr_p = (unsigned long)dev->image_paddr + (vma->vm_pgoff << PAGE_SHIFT);
++#endif
++	}
++
++#ifdef USING_DMA_ALLOC_BUFFER
++	vma->vm_pgoff = 0;
++	ret = dma_mmap_noncoherent(&dev->vdev->dev, vma, addr, addr_p, size);
++	vma->vm_flags           |= VM_DONTEXPAND | VM_DONTDUMP;
++	//printk("-----%s, %d addr:%x, dma_addr: %x size: %d, start:%x vma->vm_pgoff: %d, ret: %d\n", __func__, __LINE__, addr, addr_p, size, start, vma->vm_pgoff, ret);
++#else
++	while (size > 0) {
++		struct page *page;
++
++		page = (void *)vmalloc_to_page((void *)addr);
++
++		if (vm_insert_page(vma, start, page) < 0)
++			return -EAGAIN;
++
++		start += PAGE_SIZE;
++		addr += PAGE_SIZE;
++		size -= PAGE_SIZE;
++	}
++#endif
++	vma->vm_ops = &vm_ops;
++	vma->vm_private_data = buffer;
++	buffer->buffer.flags |= V4L2_BUF_FLAG_MAPPED;
++
++	vm_open(vma);
++
++	MARK();
++	return 0;
++}
++
++static unsigned int v4l2_loopback_poll(struct file *file,
++				       struct poll_table_struct *pts)
++{
++	struct v4l2_loopback_opener *opener;
++	struct v4l2_loopback_device *dev;
++	__poll_t req_events = poll_requested_events(pts);
++	int ret_mask = 0;
++	MARK();
++
++	opener = fh_to_opener(file->private_data);
++	dev = v4l2loopback_getdevice(file);
++
++	if (req_events & POLLPRI) {
++		if (!v4l2_event_pending(&opener->fh))
++			poll_wait(file, &opener->fh.wait, pts);
++		if (v4l2_event_pending(&opener->fh)) {
++			ret_mask |= POLLPRI;
++			if (!(req_events & DEFAULT_POLLMASK))
++				return ret_mask;
++		}
++	}
++
++	switch (opener->type) {
++	case WRITER:
++		ret_mask |= POLLOUT | POLLWRNORM;
++		break;
++	case READER:
++		if (!can_read(dev, opener)) {
++			if (ret_mask)
++				return ret_mask;
++			poll_wait(file, &dev->read_event, pts);
++		}
++		if (can_read(dev, opener))
++			ret_mask |= POLLIN | POLLRDNORM;
++		if (v4l2_event_pending(&opener->fh))
++			ret_mask |= POLLPRI;
++		break;
++	default:
++		break;
++	}
++
++	MARK();
++	return ret_mask;
++}
++
++/* do not want to limit device opens, it can be as many readers as user want,
++ * writers are limited by means of setting writer field */
++static int v4l2_loopback_open(struct file *file)
++{
++	struct v4l2_loopback_device *dev;
++	struct v4l2_loopback_opener *opener;
++	MARK();
++	dev = v4l2loopback_getdevice(file);
++	if (dev->open_count.counter >= dev->max_openers)
++		return -EBUSY;
++	/* kfree on close */
++	opener = kzalloc(sizeof(*opener), GFP_KERNEL);
++	if (opener == NULL)
++		return -ENOMEM;
++
++	v4l2_fh_init(&opener->fh, video_devdata(file));
++	file->private_data = &opener->fh;
++	atomic_inc(&dev->open_count);
++
++	opener->timeout_image_io = dev->timeout_image_io;
++	dev->timeout_image_io = 0;
++
++	if (opener->timeout_image_io) {
++		int r = allocate_timeout_image(dev);
++
++		if (r < 0) {
++			dprintk("timeout image allocation failed\n");
++			return r;
++		}
++	}
++
++	v4l2_fh_add(&opener->fh);
++	dprintk("opened dev:%p with image:%p\n", dev, dev ? dev->image : NULL);
++	MARK();
++	return 0;
++}
++
++static int v4l2_loopback_close(struct file *file)
++{
++	struct v4l2_loopback_opener *opener;
++	struct v4l2_loopback_device *dev;
++	int iswriter = 0;
++	MARK();
++
++	opener = fh_to_opener(file->private_data);
++	dev = v4l2loopback_getdevice(file);
++
++	if (WRITER == opener->type)
++		iswriter = 1;
++
++	atomic_dec(&dev->open_count);
++	if (dev->open_count.counter == 0) {
++		del_timer_sync(&dev->sustain_timer);
++		del_timer_sync(&dev->timeout_timer);
++	}
++	try_free_buffers(dev);
++
++	v4l2_fh_del(&opener->fh);
++	v4l2_fh_exit(&opener->fh);
++
++	kfree(opener);
++	if (iswriter) {
++		dev->ready_for_output = 1;
++		/*try to wakeup all readers. */
++		wake_up_all(&dev->read_event);
++	}
++	MARK();
++	return 0;
++}
++
++static ssize_t v4l2_loopback_read(struct file *file, char __user *buf,
++				  size_t count, loff_t *ppos)
++{
++	int read_index;
++	struct v4l2_loopback_device *dev;
++	struct v4l2l_buffer *b;
++	unsigned long flags;
++	MARK();
++
++	dev = v4l2loopback_getdevice(file);
++	//TODO. not support
++#if 0
++
++	/*
++	 * for capture stream:
++	 *
++	 * 1. get done buffer from done list?
++	 *
++	 * 2. memcpy from done buffer.
++	 *
++	 * 3. put it back to queued list?
++	 *
++	 *
++	 * */
++	wait_event_interruptible(dev->read_event, !list_empty(&dev->read_list));
++
++	spin_lock_irqsave(&dev->read_write_lock, flags);
++
++	b = list_first_entry_or_null(&dev->read_list, struct v4l2l_buffer, list_head);
++
++	if(!b) {
++		printk("error no buffer on read list.!\n");
++		//TODO:
++	}
++	list_del(&b->list_head);
++
++	spin_unlock_irqrestore(&dev->read_write_lock, flags);
++
++	if (count > b->bytesused)
++		count = b->bytesused;
++	if (copy_to_user((void *)buf, (void *)(dev->image + b->m.offset),
++			 count)) {
++		printk(KERN_ERR
++		       "v4l2-loopback: failed copy_to_user() in read buf\n");
++		return -EFAULT;
++	}
++
++	// give back buffer to write list.
++	list_add_tail(&b->list_head, &dev->write_list);
++#endif
++	dprintkrw("leave v4l2_loopback_read()\n");
++	return count;
++}
++
++static ssize_t v4l2_loopback_write(struct file *file, const char __user *buf,
++				   size_t count, loff_t *ppos)
++{
++	struct v4l2_loopback_device *dev;
++	int write_index;
++	struct v4l2l_buffer *b;
++	unsigned flags;
++	MARK();
++
++	dev = v4l2loopback_getdevice(file);
++
++	/* there's at least one writer, so don't stop announcing output capabilities */
++	dev->ready_for_output = 0;
++
++	if (!dev->ready_for_capture) {
++		int ret = allocate_buffers(dev);
++		if (ret < 0)
++			return ret;
++		dev->ready_for_capture = 1;
++	}
++	dprintkrw("v4l2_loopback_write() trying to write %zu bytes\n", count);
++	if (count > dev->buffer_size)
++		count = dev->buffer_size;
++
++	spin_lock_irqsave(&dev->done_lock, flags);
++
++	b = list_first_entry_or_null(&dev->queued_list, struct v4l2l_buffer, list_head);
++
++	if(!b) {
++		//
++		spin_unlock_irqrestore(&dev->done_lock, flags);
++		return count; //direct return.
++	}
++
++	list_del(&b->list_head);
++
++	spin_unlock_irqrestore(&dev->done_lock, flags);
++
++	if (copy_from_user((void *)(dev->image + b->buffer.m.offset), (void *)buf,
++			   count)) {
++		printk(KERN_ERR
++		       "v4l2-loopback: failed copy_from_user() in write buf, could not write %zu\n",
++		       count);
++		return -EFAULT;
++	}
++
++	// update timestamp.
++	v4l2l_get_timestamp(&b->buffer);
++	b->buffer.bytesused = count;
++	b->buffer.sequence = dev->output_sequence ++;	//TODO:
++	set_done(b);
++
++	list_add_tail(&b->list_head, &dev->done_list);
++
++	wake_up_all(&dev->read_event);
++	dprintkrw("leave v4l2_loopback_write()\n");
++	return count;
++}
++
++/* init functions */
++/* frees buffers, if already allocated */
++static int free_buffers(struct v4l2_loopback_device *dev)
++{
++	MARK();
++	dprintk("freeing image@%p for dev:%p\n", dev ? dev->image : NULL, dev);
++	if (dev->image) {
++#ifdef USING_DMA_ALLOC_BUFFER
++		dma_free_noncoherent(&dev->vdev->dev, dev->imagesize, dev->image, dev->image_paddr);
++#else
++		vfree(dev->image);
++#endif
++		dev->image = NULL;
++	}
++	if (dev->timeout_image) {
++		vfree(dev->timeout_image);
++		dev->timeout_image = NULL;
++	}
++	dev->imagesize = 0;
++
++	return 0;
++}
++/* frees buffers, if they are no longer needed */
++static void try_free_buffers(struct v4l2_loopback_device *dev)
++{
++	MARK();
++	if (0 == dev->open_count.counter && !dev->keep_format) {
++		free_buffers(dev);
++		dev->ready_for_capture = 0;
++		dev->buffer_size = 0;
++		dev->write_position = 0;
++	}
++}
++/* allocates buffers, if buffer_size is set */
++static int allocate_buffers(struct v4l2_loopback_device *dev)
++{
++	MARK();
++	/* vfree on close file operation in case no open handles left */
++	if (0 == dev->buffer_size)
++		return -EINVAL;
++
++	if (dev->image) {
++		dprintk("allocating buffers again: %ld %ld\n",
++			dev->buffer_size * dev->buffers_number, dev->imagesize);
++		/* FIXME: prevent double allocation more intelligently! */
++		if (dev->buffer_size * dev->buffers_number == dev->imagesize)
++			return 0;
++
++		/* if there is only one writer, no problem should occur */
++		if (dev->open_count.counter == 1)
++			free_buffers(dev);
++		else
++			return -EINVAL;
++	}
++
++	dev->imagesize = dev->buffer_size * dev->buffers_number;
++
++	dprintk("allocating %ld = %ldx%d\n", dev->imagesize, dev->buffer_size,
++		dev->buffers_number);
++
++#ifdef USING_DMA_ALLOC_BUFFER
++	dev->image = dma_alloc_noncoherent(&dev->vdev->dev, dev->imagesize, &dev->image_paddr, GFP_KERNEL);
++#else
++	dev->image = vmalloc(dev->imagesize);
++#endif
++	if (dev->timeout_jiffies > 0)
++		allocate_timeout_image(dev);
++
++	if (dev->image == NULL)
++		return -ENOMEM;
++	dprintk("vmallocated %ld bytes\n", dev->imagesize);
++	MARK();
++
++	dev->output_sequence = 0;
++	//init_buffers(dev);
++	return 0;
++}
++
++/* init inner buffers, they are capture mode and flags are set as
++ * for capture mod buffers */
++static void init_buffers(struct v4l2_loopback_device *dev)
++{
++	int i;
++	int buffer_size;
++	int bytesused;
++	MARK();
++
++	buffer_size = dev->buffer_size;
++	bytesused = dev->pix_format.sizeimage;
++
++	for (i = 0; i < dev->buffers_number; ++i) {
++		struct v4l2_buffer *b = &dev->buffers[i].buffer;
++		b->index = i;
++		b->bytesused = bytesused;
++		b->length = buffer_size;
++		b->field = V4L2_FIELD_NONE;
++	//	b->flags = 0;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 1)
++		b->input = 0;
++#endif
++		b->m.offset = i * buffer_size;
++		b->memory = V4L2_MEMORY_MMAP;
++		b->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++#if 0
++		/*dev->buffers 作为output 和 capture 共��作的数�, 是�是应该加�处�????*/
++		b->sequence = 0;
++		b->timestamp.tv_sec = 0;
++		b->timestamp.tv_usec = 0;
++
++		v4l2l_get_timestamp(b);
++#endif
++	}
++	dev->timeout_image_buffer = dev->buffers[0];
++	dev->timeout_image_buffer.buffer.m.offset = MAX_BUFFERS * buffer_size;
++	MARK();
++}
++
++static int allocate_timeout_image(struct v4l2_loopback_device *dev)
++{
++	MARK();
++	if (dev->buffer_size <= 0)
++		return -EINVAL;
++
++	if (dev->timeout_image == NULL) {
++		dev->timeout_image = v4l2l_vzalloc(dev->buffer_size);
++		if (dev->timeout_image == NULL)
++			return -ENOMEM;
++	}
++	return 0;
++}
++
++/* fills and register video device */
++static void init_vdev(struct video_device *vdev, int nr)
++{
++	MARK();
++
++#ifdef V4L2LOOPBACK_WITH_STD
++	vdev->tvnorms = V4L2_STD_ALL;
++#endif /* V4L2LOOPBACK_WITH_STD */
++
++	vdev->vfl_type = VFL_TYPE_VIDEO;
++	vdev->fops = &v4l2_loopback_fops;
++	vdev->ioctl_ops = &v4l2_loopback_ioctl_ops;
++	vdev->release = &video_device_release;
++	vdev->minor = -1;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)
++	vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
++			    V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
++#ifdef V4L2_CAP_VIDEO_M2M
++	vdev->device_caps |= V4L2_CAP_VIDEO_M2M;
++#endif
++#endif /* >=linux-4.7.0 */
++
++	if (debug > 1)
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 20, 0)
++		vdev->debug = V4L2_DEBUG_IOCTL | V4L2_DEBUG_IOCTL_ARG;
++#else
++		vdev->dev_debug =
++			V4L2_DEV_DEBUG_IOCTL | V4L2_DEV_DEBUG_IOCTL_ARG;
++#endif
++
++		/* since kernel-3.7, there is a new field 'vfl_dir' that has to be
++	 * set to VFL_DIR_M2M for bidirectional devices */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0)
++	vdev->vfl_dir = VFL_DIR_M2M;
++#endif
++
++	MARK();
++}
++
++/* init default capture parameters, only fps may be changed in future */
++static void init_capture_param(struct v4l2_captureparm *capture_param)
++{
++	MARK();
++	capture_param->capability = 0;
++	capture_param->capturemode = 0;
++	capture_param->extendedmode = 0;
++	capture_param->readbuffers = max_buffers;
++	capture_param->timeperframe.numerator = 1;
++	capture_param->timeperframe.denominator = 30;
++}
++
++static void check_timers(struct v4l2_loopback_device *dev)
++{
++	if (!dev->ready_for_capture)
++		return;
++
++	if (dev->timeout_jiffies > 0 && !timer_pending(&dev->timeout_timer))
++		mod_timer(&dev->timeout_timer, jiffies + dev->timeout_jiffies);
++	if (dev->sustain_framerate && !timer_pending(&dev->sustain_timer))
++		mod_timer(&dev->sustain_timer,
++			  jiffies + dev->frame_jiffies * 3 / 2);
++}
++#ifdef HAVE_TIMER_SETUP
++static void sustain_timer_clb(struct timer_list *t)
++{
++	struct v4l2_loopback_device *dev = from_timer(dev, t, sustain_timer);
++#else
++static void sustain_timer_clb(unsigned long nr)
++{
++	struct v4l2_loopback_device *dev =
++		idr_find(&v4l2loopback_index_idr, nr);
++#endif
++	spin_lock(&dev->lock);
++	if (dev->sustain_framerate) {
++		dev->reread_count++;
++		dprintkrw("reread: %d %d\n", dev->write_position,
++			  dev->reread_count);
++		if (dev->reread_count == 1)
++			mod_timer(&dev->sustain_timer,
++				  jiffies + max(1UL, dev->frame_jiffies / 2));
++		else
++			mod_timer(&dev->sustain_timer,
++				  jiffies + dev->frame_jiffies);
++		wake_up_all(&dev->read_event);
++	}
++	spin_unlock(&dev->lock);
++}
++#ifdef HAVE_TIMER_SETUP
++static void timeout_timer_clb(struct timer_list *t)
++{
++	struct v4l2_loopback_device *dev = from_timer(dev, t, timeout_timer);
++#else
++static void timeout_timer_clb(unsigned long nr)
++{
++	struct v4l2_loopback_device *dev =
++		idr_find(&v4l2loopback_index_idr, nr);
++#endif
++	spin_lock(&dev->lock);
++	if (dev->timeout_jiffies > 0) {
++		dev->timeout_happened = 1;
++		mod_timer(&dev->timeout_timer, jiffies + dev->timeout_jiffies);
++		wake_up_all(&dev->read_event);
++	}
++	spin_unlock(&dev->lock);
++}
++
++/* init loopback main structure */
++#define DEFAULT_FROM_CONF(confmember, default_condition, default_value)        \
++	((conf) ?                                                              \
++		 ((conf->confmember default_condition) ? (default_value) :     \
++							 (conf->confmember)) : \
++		 default_value)
++
++static int v4l2_loopback_add(struct v4l2_loopback_config *conf, int *ret_nr)
++{
++	struct v4l2_loopback_device *dev;
++	struct v4l2_ctrl_handler *hdl;
++
++	int err = -ENOMEM;
++
++	int _max_width = DEFAULT_FROM_CONF(
++		max_width, <= V4L2LOOPBACK_SIZE_MIN_WIDTH, max_width);
++	int _max_height = DEFAULT_FROM_CONF(
++		max_height, <= V4L2LOOPBACK_SIZE_MIN_HEIGHT, max_height);
++	bool _announce_all_caps = (conf && conf->announce_all_caps >= 0) ?
++					  (conf->announce_all_caps) :
++					  V4L2LOOPBACK_DEFAULT_EXCLUSIVECAPS;
++
++	int _max_buffers = DEFAULT_FROM_CONF(max_buffers, <= 0, max_buffers);
++	int _max_openers = DEFAULT_FROM_CONF(max_openers, <= 0, max_openers);
++
++	int nr = -1;
++	if (conf) {
++		if (conf->capture_nr >= 0 &&
++		    conf->output_nr == conf->capture_nr) {
++			nr = conf->capture_nr;
++		} else if (conf->capture_nr < 0 && conf->output_nr < 0) {
++			nr = -1;
++		} else if (conf->capture_nr < 0) {
++			nr = conf->output_nr;
++		} else if (conf->output_nr < 0) {
++			nr = conf->capture_nr;
++		} else {
++			printk(KERN_ERR
++			       "split OUTPUT and CAPTURE devices not yet supported.");
++			printk(KERN_INFO
++			       "both devices must have the same number (%d != %d).",
++			       conf->output_nr, conf->capture_nr);
++			return -EINVAL;
++		}
++	}
++
++	if (idr_find(&v4l2loopback_index_idr, nr))
++		return -EEXIST;
++
++	dprintk("creating v4l2loopback-device #%d\n", nr);
++	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
++	if (!dev)
++		return -ENOMEM;
++
++	/* allocate id, if @id >= 0, we're requesting that specific id */
++	if (nr >= 0) {
++		err = idr_alloc(&v4l2loopback_index_idr, dev, nr, nr + 1,
++				GFP_KERNEL);
++		if (err == -ENOSPC)
++			err = -EEXIST;
++	} else {
++		err = idr_alloc(&v4l2loopback_index_idr, dev, 0, 0, GFP_KERNEL);
++	}
++	if (err < 0)
++		goto out_free_dev;
++	nr = err;
++	err = -ENOMEM;
++
++	if (conf && conf->card_label && *(conf->card_label)) {
++		snprintf(dev->card_label, sizeof(dev->card_label), "%s",
++			 conf->card_label);
++	} else {
++		snprintf(dev->card_label, sizeof(dev->card_label),
++			 "Dummy video device (0x%04X)", nr);
++	}
++	snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name),
++		 "v4l2loopback-%03d", nr);
++
++	err = v4l2_device_register(NULL, &dev->v4l2_dev);
++	if (err)
++		goto out_free_idr;
++	MARK();
++
++	dev->vdev = video_device_alloc();
++	if (dev->vdev == NULL) {
++		err = -ENOMEM;
++		goto out_unregister;
++	}
++	video_set_drvdata(dev->vdev,
++			  kzalloc(sizeof(struct v4l2loopback_private),
++				  GFP_KERNEL));
++	if (video_get_drvdata(dev->vdev) == NULL) {
++		err = -ENOMEM;
++		goto out_unregister;
++	}
++
++	MARK();
++	snprintf(dev->vdev->name, sizeof(dev->vdev->name), dev->card_label);
++
++	((struct v4l2loopback_private *)video_get_drvdata(dev->vdev))
++		->device_nr = nr;
++
++	init_vdev(dev->vdev, nr);
++	dev->vdev->v4l2_dev = &dev->v4l2_dev;
++	init_capture_param(&dev->capture_param);
++	set_timeperframe(dev, &dev->capture_param.timeperframe);
++	dev->keep_format = 0;
++	dev->sustain_framerate = 0;
++
++	dev->announce_all_caps = _announce_all_caps;
++	dev->max_width = _max_width;
++	dev->max_height = _max_height;
++	dev->max_openers = _max_openers;
++	dev->buffers_number = dev->used_buffers = _max_buffers;
++
++	dev->write_position = 0;
++
++	MARK();
++	spin_lock_init(&dev->lock);
++	INIT_LIST_HEAD(&dev->outbufs_list);
++	if (list_empty(&dev->outbufs_list)) {
++		int i;
++
++		for (i = 0; i < dev->used_buffers; ++i)
++			list_add_tail(&dev->buffers[i].list_head,
++				      &dev->outbufs_list);
++	}
++
++	INIT_LIST_HEAD(&dev->queued_list);
++	INIT_LIST_HEAD(&dev->done_list);
++	spin_lock_init(&dev->done_lock);
++
++	memset(dev->bufpos2index, 0, sizeof(dev->bufpos2index));
++	atomic_set(&dev->open_count, 0);
++	dev->ready_for_capture = 0;
++	dev->ready_for_output = 1;
++
++	dev->buffer_size = 0;
++	dev->image = NULL;
++	dev->imagesize = 0;
++#ifdef HAVE_TIMER_SETUP
++	timer_setup(&dev->sustain_timer, sustain_timer_clb, 0);
++	timer_setup(&dev->timeout_timer, timeout_timer_clb, 0);
++#else
++	setup_timer(&dev->sustain_timer, sustain_timer_clb, nr);
++	setup_timer(&dev->timeout_timer, timeout_timer_clb, nr);
++#endif
++	dev->reread_count = 0;
++	dev->timeout_jiffies = 0;
++	dev->timeout_image = NULL;
++	dev->timeout_happened = 0;
++
++	hdl = &dev->ctrl_handler;
++	err = v4l2_ctrl_handler_init(hdl, 4);
++	if (err)
++		goto out_unregister;
++	v4l2_ctrl_new_custom(hdl, &v4l2loopback_ctrl_keepformat, NULL);
++	v4l2_ctrl_new_custom(hdl, &v4l2loopback_ctrl_sustainframerate, NULL);
++	v4l2_ctrl_new_custom(hdl, &v4l2loopback_ctrl_timeout, NULL);
++	v4l2_ctrl_new_custom(hdl, &v4l2loopback_ctrl_timeoutimageio, NULL);
++	if (hdl->error) {
++		err = hdl->error;
++		goto out_free_handler;
++	}
++	dev->v4l2_dev.ctrl_handler = hdl;
++
++	err = v4l2_ctrl_handler_setup(hdl);
++
++	/* FIXME set buffers to 0 */
++
++	/* Set initial format */
++	dev->pix_format.width = 0; /* V4L2LOOPBACK_SIZE_DEFAULT_WIDTH; */
++	dev->pix_format.height = 0; /* V4L2LOOPBACK_SIZE_DEFAULT_HEIGHT; */
++	dev->pix_format.pixelformat = formats[0].fourcc;
++	dev->pix_format.colorspace =
++		V4L2_COLORSPACE_SRGB; /* do we need to set this ? */
++	dev->pix_format.field = V4L2_FIELD_NONE;
++
++	dev->buffer_size = PAGE_ALIGN(dev->pix_format.sizeimage);
++	dprintk("buffer_size = %ld (=%d)\n", dev->buffer_size,
++		dev->pix_format.sizeimage);
++	allocate_buffers(dev);
++
++	init_waitqueue_head(&dev->read_event);
++
++	/* register the device -> it creates /dev/video* */
++	if (video_register_device(dev->vdev, VFL_TYPE_VIDEO, nr) < 0) {
++		printk(KERN_ERR
++		       "v4l2loopback: failed video_register_device()\n");
++		err = -EFAULT;
++		goto out_free_device;
++	}
++	v4l2loopback_create_sysfs(dev->vdev);
++
++	MARK();
++	if (ret_nr)
++		*ret_nr = dev->vdev->num;
++	return 0;
++
++out_free_device:
++	video_device_release(dev->vdev);
++out_free_handler:
++	v4l2_ctrl_handler_free(&dev->ctrl_handler);
++out_unregister:
++	v4l2_device_unregister(&dev->v4l2_dev);
++out_free_idr:
++	idr_remove(&v4l2loopback_index_idr, nr);
++out_free_dev:
++	kfree(dev);
++	return err;
++}
++
++static void v4l2_loopback_remove(struct v4l2_loopback_device *dev)
++{
++	free_buffers(dev);
++	v4l2loopback_remove_sysfs(dev->vdev);
++	kfree(video_get_drvdata(dev->vdev));
++	video_unregister_device(dev->vdev);
++	v4l2_device_unregister(&dev->v4l2_dev);
++	v4l2_ctrl_handler_free(&dev->ctrl_handler);
++	kfree(dev);
++}
++
++static long v4l2loopback_control_ioctl(struct file *file, unsigned int cmd,
++				       unsigned long parm)
++{
++	struct v4l2_loopback_device *dev;
++	struct v4l2_loopback_config conf;
++	struct v4l2_loopback_config *confptr = &conf;
++	int device_nr;
++	int ret;
++
++	ret = mutex_lock_killable(&v4l2loopback_ctl_mutex);
++	if (ret)
++		return ret;
++
++	ret = -EINVAL;
++	switch (cmd) {
++	default:
++		ret = -ENOSYS;
++		break;
++		/* add a v4l2loopback device (pair), based on the user-provided specs */
++	case V4L2LOOPBACK_CTL_ADD:
++		if (parm) {
++			if ((ret = copy_from_user(&conf, (void *)parm,
++						  sizeof(conf))) < 0)
++				break;
++		} else
++			confptr = NULL;
++		ret = v4l2_loopback_add(confptr, &device_nr);
++		if (ret >= 0)
++			ret = device_nr;
++		break;
++		/* remove a v4l2loopback device (both capture and output) */
++	case V4L2LOOPBACK_CTL_REMOVE:
++		ret = v4l2loopback_lookup((int)parm, &dev);
++		if (ret >= 0 && dev) {
++			int nr = ret;
++			ret = -EBUSY;
++			if (dev->open_count.counter > 0)
++				break;
++			idr_remove(&v4l2loopback_index_idr, nr);
++			v4l2_loopback_remove(dev);
++			ret = 0;
++		};
++		break;
++		/* get information for a loopback device.
++                 * this is mostly about limits (which cannot be queried directly with  VIDIOC_G_FMT and friends
++                 */
++	case V4L2LOOPBACK_CTL_QUERY:
++		if (!parm)
++			break;
++		if ((ret = copy_from_user(&conf, (void *)parm, sizeof(conf))) <
++		    0)
++			break;
++		device_nr =
++			(conf.output_nr < 0) ? conf.capture_nr : conf.output_nr;
++		MARK();
++		/* get the device from either capture_nr or output_nr (whatever is valid) */
++		if ((ret = v4l2loopback_lookup(device_nr, &dev)) < 0)
++			break;
++		MARK();
++		/* if we got the device from output_nr and there is a valid capture_nr,
++                 * make sure that both refer to the same device (or bail out)
++                 */
++		if ((device_nr != conf.capture_nr) && (conf.capture_nr >= 0) &&
++		    (ret != v4l2loopback_lookup(conf.capture_nr, 0)))
++			break;
++		MARK();
++		/* if otoh, we got the device from capture_nr and there is a valid output_nr,
++                 * make sure that both refer to the same device (or bail out)
++                 */
++		if ((device_nr != conf.output_nr) && (conf.output_nr >= 0) &&
++		    (ret != v4l2loopback_lookup(conf.output_nr, 0)))
++			break;
++		MARK();
++
++		/* v4l2_loopback_config identified a single device, so fetch the data */
++		snprintf(conf.card_label, sizeof(conf.card_label), "%s",
++			 dev->card_label);
++		MARK();
++		conf.output_nr = conf.capture_nr = dev->vdev->num;
++		conf.max_width = dev->max_width;
++		conf.max_height = dev->max_height;
++		conf.announce_all_caps = dev->announce_all_caps;
++		conf.max_buffers = dev->buffers_number;
++		conf.max_openers = dev->max_openers;
++		conf.debug = debug;
++		MARK();
++		if (copy_to_user((void *)parm, &conf, sizeof(conf))) {
++			ret = -EFAULT;
++			break;
++		}
++		MARK();
++		ret = 0;
++		;
++		break;
++	}
++
++	MARK();
++	mutex_unlock(&v4l2loopback_ctl_mutex);
++	MARK();
++	return ret;
++}
++
++/* LINUX KERNEL */
++
++static const struct file_operations v4l2loopback_ctl_fops = {
++	// clang-format off
++	.open		= nonseekable_open,
++	.unlocked_ioctl	= v4l2loopback_control_ioctl,
++	.compat_ioctl	= v4l2loopback_control_ioctl,
++	.owner		= THIS_MODULE,
++	.llseek		= noop_llseek,
++	// clang-format on
++};
++
++static struct miscdevice v4l2loopback_misc = {
++	// clang-format off
++	.minor		= MISC_DYNAMIC_MINOR,
++	.name		= "v4l2loopback",
++	.fops		= &v4l2loopback_ctl_fops,
++	// clang-format on
++};
++
++static const struct v4l2_file_operations v4l2_loopback_fops = {
++	// clang-format off
++	.owner		= THIS_MODULE,
++	.open		= v4l2_loopback_open,
++	.release	= v4l2_loopback_close,
++	.read		= v4l2_loopback_read,
++	.write		= v4l2_loopback_write,
++	.poll		= v4l2_loopback_poll,
++	.mmap		= v4l2_loopback_mmap,
++	.unlocked_ioctl	= video_ioctl2,
++	// clang-format on
++};
++
++static const struct v4l2_ioctl_ops v4l2_loopback_ioctl_ops = {
++	// clang-format off
++	.vidioc_querycap		= &vidioc_querycap,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)
++	.vidioc_enum_framesizes		= &vidioc_enum_framesizes,
++	.vidioc_enum_frameintervals	= &vidioc_enum_frameintervals,
++#endif
++
++#ifndef HAVE__V4L2_CTRLS
++	.vidioc_queryctrl		= &vidioc_queryctrl,
++	.vidioc_g_ctrl			= &vidioc_g_ctrl,
++	.vidioc_s_ctrl			= &vidioc_s_ctrl,
++#endif /* HAVE__V4L2_CTRLS */
++
++	.vidioc_enum_output		= &vidioc_enum_output,
++	.vidioc_g_output		= &vidioc_g_output,
++	.vidioc_s_output		= &vidioc_s_output,
++
++	.vidioc_enum_input		= &vidioc_enum_input,
++	.vidioc_g_input			= &vidioc_g_input,
++	.vidioc_s_input			= &vidioc_s_input,
++
++	.vidioc_enum_fmt_vid_cap	= &vidioc_enum_fmt_cap,
++	.vidioc_g_fmt_vid_cap		= &vidioc_g_fmt_cap,
++	.vidioc_s_fmt_vid_cap		= &vidioc_s_fmt_cap,
++	.vidioc_try_fmt_vid_cap		= &vidioc_try_fmt_cap,
++
++	.vidioc_enum_fmt_vid_out	= &vidioc_enum_fmt_out,
++	.vidioc_s_fmt_vid_out		= &vidioc_s_fmt_out,
++	.vidioc_g_fmt_vid_out		= &vidioc_g_fmt_out,
++	.vidioc_try_fmt_vid_out		= &vidioc_try_fmt_out,
++
++#ifdef V4L2L_OVERLAY
++	.vidioc_s_fmt_vid_overlay	= &vidioc_s_fmt_overlay,
++	.vidioc_g_fmt_vid_overlay	= &vidioc_g_fmt_overlay,
++#endif
++
++#ifdef V4L2LOOPBACK_WITH_STD
++	.vidioc_s_std			= &vidioc_s_std,
++	.vidioc_g_std			= &vidioc_g_std,
++	.vidioc_querystd		= &vidioc_querystd,
++#endif /* V4L2LOOPBACK_WITH_STD */
++
++	.vidioc_g_parm			= &vidioc_g_parm,
++	.vidioc_s_parm			= &vidioc_s_parm,
++
++	.vidioc_reqbufs			= &vidioc_reqbufs,
++	.vidioc_querybuf		= &vidioc_querybuf,
++	.vidioc_qbuf			= &vidioc_qbuf,
++	.vidioc_dqbuf			= &vidioc_dqbuf,
++
++	.vidioc_streamon		= &vidioc_streamon,
++	.vidioc_streamoff		= &vidioc_streamoff,
++
++#ifdef CONFIG_VIDEO_V4L1_COMPAT
++	.vidiocgmbuf			= &vidiocgmbuf,
++#endif
++
++	.vidioc_subscribe_event		= &vidioc_subscribe_event,
++	.vidioc_unsubscribe_event	= &v4l2_event_unsubscribe,
++	// clang-format on
++};
++
++static int free_device_cb(int id, void *ptr, void *data)
++{
++	struct v4l2_loopback_device *dev = ptr;
++	v4l2_loopback_remove(dev);
++	return 0;
++}
++static void free_devices(void)
++{
++	idr_for_each(&v4l2loopback_index_idr, &free_device_cb, NULL);
++	idr_destroy(&v4l2loopback_index_idr);
++}
++
++static int __init v4l2loopback_init_module(void)
++{
++	int err;
++	int i;
++	MARK();
++
++	err = misc_register(&v4l2loopback_misc);
++	if (err < 0)
++		return err;
++
++	if (devices < 0) {
++		devices = 1;
++
++		/* try guessing the devices from the "video_nr" parameter */
++		for (i = MAX_DEVICES - 1; i >= 0; i--) {
++			if (video_nr[i] >= 0) {
++				devices = i + 1;
++				break;
++			}
++		}
++	}
++
++	if (devices > MAX_DEVICES) {
++		devices = MAX_DEVICES;
++		printk(KERN_INFO
++		       "v4l2loopback: number of initial devices is limited to: %d\n",
++		       MAX_DEVICES);
++	}
++
++	if (max_buffers > MAX_BUFFERS) {
++		max_buffers = MAX_BUFFERS;
++		printk(KERN_INFO
++		       "v4l2loopback: number of buffers is limited to: %d\n",
++		       MAX_BUFFERS);
++	}
++
++	if (max_openers < 0) {
++		printk(KERN_INFO
++		       "v4l2loopback: allowing %d openers rather than %d\n",
++		       2, max_openers);
++		max_openers = 2;
++	}
++
++	if (max_width < 1) {
++		max_width = V4L2LOOPBACK_SIZE_DEFAULT_MAX_WIDTH;
++		printk(KERN_INFO "v4l2loopback: using max_width %d\n",
++		       max_width);
++	}
++	if (max_height < 1) {
++		max_height = V4L2LOOPBACK_SIZE_DEFAULT_MAX_HEIGHT;
++		printk(KERN_INFO "v4l2loopback: using max_height %d\n",
++		       max_height);
++	}
++
++	/* kfree on module release */
++	for (i = 0; i < devices; i++) {
++		struct v4l2_loopback_config cfg = {
++			// clang-format off
++			.output_nr		= video_nr[i],
++			.capture_nr		= video_nr[i],
++			.max_width		= max_width,
++			.max_height		= max_height,
++			.announce_all_caps	= (!exclusive_caps[i]),
++			.max_buffers		= max_buffers,
++			.max_openers		= max_openers,
++			.debug			= debug,
++			// clang-format on
++		};
++		cfg.card_label[0] = 0;
++		if (card_label[i])
++			snprintf(cfg.card_label, sizeof(cfg.card_label), "%s",
++				 card_label[i]);
++		err = v4l2_loopback_add(&cfg, 0);
++		if (err) {
++			free_devices();
++			goto error;
++		}
++	}
++
++	dprintk("module installed\n");
++
++	printk(KERN_INFO "v4l2loopback driver version %d.%d.%d loaded\n",
++	       // clang-format off
++	       (V4L2LOOPBACK_VERSION_CODE >> 16) & 0xff,
++	       (V4L2LOOPBACK_VERSION_CODE >>  8) & 0xff,
++	       (V4L2LOOPBACK_VERSION_CODE      ) & 0xff);
++	// clang-format on
++
++	return 0;
++error:
++	misc_deregister(&v4l2loopback_misc);
++	return err;
++}
++
++static void v4l2loopback_cleanup_module(void)
++{
++	MARK();
++	/* unregister the device -> it deletes /dev/video* */
++	free_devices();
++	/* and get rid of /dev/v4l2loopback */
++	misc_deregister(&v4l2loopback_misc);
++	dprintk("module removed\n");
++}
++
++MODULE_ALIAS_MISCDEV(MISC_DYNAMIC_MINOR);
++MODULE_ALIAS("devname:v4l2loopback");
++
++#ifdef MODULE
++int __init init_module(void)
++{
++	return v4l2loopback_init_module();
++}
++void __exit cleanup_module(void)
++{
++	return v4l2loopback_cleanup_module();
++}
++#else
++late_initcall(v4l2loopback_init_module);
++#endif
++
++/*
++ * fake usage of unused functions
++ */
++#ifdef HAVE__V4L2_CTRLS
++static int vidioc_queryctrl(struct file *file, void *fh,
++			    struct v4l2_queryctrl *q) __attribute__((unused));
++static int vidioc_g_ctrl(struct file *file, void *fh, struct v4l2_control *c)
++	__attribute__((unused));
++static int vidioc_s_ctrl(struct file *file, void *fh, struct v4l2_control *c)
++	__attribute__((unused));
++#endif /* HAVE__V4L2_CTRLS */
+diff --git a/drivers/media/platform/v4l2loopback/v4l2loopback.h b/drivers/media/platform/v4l2loopback/v4l2loopback.h
+new file mode 100644
+index 000000000..77c671971
+--- /dev/null
++++ b/drivers/media/platform/v4l2loopback/v4l2loopback.h
+@@ -0,0 +1,92 @@
++/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
++/*
++ * v4l2loopback.h
++ *
++ * Written by IOhannes m zmölnig, 7/1/20.
++ *
++ * Copyright 2020 by IOhannes m zmölnig.  Redistribution of this file is
++ * permitted under the GNU General Public License.
++ */
++#ifndef _V4L2LOOPBACK_H
++#define _V4L2LOOPBACK_H
++
++#define V4L2LOOPBACK_VERSION_MAJOR 0
++#define V4L2LOOPBACK_VERSION_MINOR 12
++#define V4L2LOOPBACK_VERSION_BUGFIX 5
++
++/* /dev/v4l2loopback interface */
++
++struct v4l2_loopback_config {
++	/** 
++         * the device-number (/dev/video<nr>)
++         * V4L2LOOPBACK_CTL_ADD:
++         * setting this to a value<0, will allocate an available one
++         * if nr>=0 and the device already exists, the ioctl will EEXIST
++         * if output_nr and capture_nr are the same, only a single device will be created
++         *
++         * V4L2LOOPBACK_CTL_QUERY:
++         * either both output_nr and capture_nr must refer to the same loopback,
++         * or one (and only one) of them must be -1
++         *
++         */
++	int output_nr;
++	int capture_nr;
++
++	/**
++         * a nice name for your device
++         * if (*card_label)==0, an automatic name is assigned
++         */
++	char card_label[32];
++
++	/**
++         * maximum allowed frame size
++         * if too low, default values are used
++         */
++	int max_width;
++	int max_height;
++
++	/**
++         * whether to announce OUTPUT/CAPTURE capabilities exclusively
++         * for this device or not
++         * (!exclusive_caps)
++         * FIXXME: this ought to be removed (if superseded by output_nr vs capture_nr)
++         */
++	int announce_all_caps;
++
++	/**
++         * number of buffers to allocate for the queue
++         * if set to <=0, default values are used
++         */
++	int max_buffers;
++
++	/**
++         * how many consumers are allowed to open this device concurrently
++         * if set to <=0, default values are used
++         */
++	int max_openers;
++
++	/**
++         * set the debugging level for this device
++         */
++	int debug;
++};
++
++/* a pointer to a (struct v4l2_loopback_config) that has all values you wish to impose on the
++ * to-be-created device set.
++ * if the ptr is NULL, a new device is created with default values at the driver's discretion.
++ *
++ * returns the device_nr of the OUTPUT device (which can be used with V4L2LOOPBACK_CTL_QUERY,
++ * to get more information on the device)
++ */
++#define V4L2LOOPBACK_CTL_ADD 0x4C80
++
++/* a pointer to a (struct v4l2_loopback_config) that has output_nr and/or capture_nr set
++ * (the two values must either refer to video-devices associated with the same loopback device
++ *  or exactly one of them must be <0
++ */
++#define V4L2LOOPBACK_CTL_QUERY 0x4C82
++
++/* the device-number (either CAPTURE or OUTPUT) associated with the loopback-device */
++#define V4L2LOOPBACK_CTL_REMOVE 0x4C81
++
++#endif /* _V4L2LOOPBACK_H */
+diff --git a/drivers/media/platform/v4l2loopback/v4l2loopback_formats.h b/drivers/media/platform/v4l2loopback/v4l2loopback_formats.h
+new file mode 100644
+index 000000000..6cb6f842c
+--- /dev/null
++++ b/drivers/media/platform/v4l2loopback/v4l2loopback_formats.h
+@@ -0,0 +1,427 @@
++#ifndef V4L2_PIX_FMT_VP9
++#define V4L2_PIX_FMT_VP9 v4l2_fourcc('V', 'P', '9', '0')
++#endif
++#ifndef V4L2_PIX_FMT_HEVC
++#define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C')
++#endif
++
++/* here come the packed formats */
++{
++	.name = "32 bpp RGB, le",
++	.fourcc = V4L2_PIX_FMT_BGR32,
++	.depth = 32,
++	.flags = 0,
++},
++	{
++		.name = "32 bpp RGB, be",
++		.fourcc = V4L2_PIX_FMT_RGB32,
++		.depth = 32,
++		.flags = 0,
++	},
++	{
++		.name = "24 bpp RGB, le",
++		.fourcc = V4L2_PIX_FMT_BGR24,
++		.depth = 24,
++		.flags = 0,
++	},
++	{
++		.name = "24 bpp RGB, be",
++		.fourcc = V4L2_PIX_FMT_RGB24,
++		.depth = 24,
++		.flags = 0,
++	},
++#ifdef V4L2_PIX_FMT_RGB332
++	{
++		.name = "8 bpp RGB-3-3-2",
++		.fourcc = V4L2_PIX_FMT_RGB332,
++		.depth = 8,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_RGB332 */
++#ifdef V4L2_PIX_FMT_RGB444
++	{
++		.name = "16 bpp RGB (xxxxrrrr ggggbbbb)",
++		.fourcc = V4L2_PIX_FMT_RGB444,
++		.depth = 16,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_RGB444 */
++#ifdef V4L2_PIX_FMT_RGB555
++	{
++		.name = "16 bpp RGB-5-5-5",
++		.fourcc = V4L2_PIX_FMT_RGB555,
++		.depth = 16,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_RGB555 */
++#ifdef V4L2_PIX_FMT_RGB565
++	{
++		.name = "16 bpp RGB-5-6-5",
++		.fourcc = V4L2_PIX_FMT_RGB565,
++		.depth = 16,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_RGB565 */
++#ifdef V4L2_PIX_FMT_RGB555X
++	{
++		.name = "16 bpp RGB-5-5-5 BE",
++		.fourcc = V4L2_PIX_FMT_RGB555X,
++		.depth = 16,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_RGB555X */
++#ifdef V4L2_PIX_FMT_RGB565X
++	{
++		.name = "16 bpp RGB-5-6-5 BE",
++		.fourcc = V4L2_PIX_FMT_RGB565X,
++		.depth = 16,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_RGB565X */
++#ifdef V4L2_PIX_FMT_BGR666
++	{
++		.name = "18 bpp BGR-6-6-6",
++		.fourcc = V4L2_PIX_FMT_BGR666,
++		.depth = 18,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_BGR666 */
++	{
++		.name = "4:2:2, packed, YUYV",
++		.fourcc = V4L2_PIX_FMT_YUYV,
++		.depth = 16,
++		.flags = 0,
++	},
++	{
++		.name = "4:2:2, packed, UYVY",
++		.fourcc = V4L2_PIX_FMT_UYVY,
++		.depth = 16,
++		.flags = 0,
++	},
++#ifdef V4L2_PIX_FMT_YVYU
++	{
++		.name = "4:2:2, packed YVYU",
++		.fourcc = V4L2_PIX_FMT_YVYU,
++		.depth = 16,
++		.flags = 0,
++	},
++#endif
++#ifdef V4L2_PIX_FMT_VYUY
++	{
++		.name = "4:2:2, packed VYUY",
++		.fourcc = V4L2_PIX_FMT_VYUY,
++		.depth = 16,
++		.flags = 0,
++	},
++#endif
++	{
++		.name = "4:2:2, packed YYUV",
++		.fourcc = V4L2_PIX_FMT_YYUV,
++		.depth = 16,
++		.flags = 0,
++	},
++	{
++		.name = "YUV-8-8-8-8",
++		.fourcc = V4L2_PIX_FMT_YUV32,
++		.depth = 32,
++		.flags = 0,
++	},
++	{
++		.name = "8 bpp, Greyscale",
++		.fourcc = V4L2_PIX_FMT_GREY,
++		.depth = 8,
++		.flags = 0,
++	},
++#ifdef V4L2_PIX_FMT_Y4
++	{
++		.name = "4 bpp Greyscale",
++		.fourcc = V4L2_PIX_FMT_Y4,
++		.depth = 4,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_Y4 */
++#ifdef V4L2_PIX_FMT_Y6
++	{
++		.name = "6 bpp Greyscale",
++		.fourcc = V4L2_PIX_FMT_Y6,
++		.depth = 6,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_Y6 */
++#ifdef V4L2_PIX_FMT_Y10
++	{
++		.name = "10 bpp Greyscale",
++		.fourcc = V4L2_PIX_FMT_Y10,
++		.depth = 10,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_Y10 */
++#ifdef V4L2_PIX_FMT_Y12
++	{
++		.name = "12 bpp Greyscale",
++		.fourcc = V4L2_PIX_FMT_Y12,
++		.depth = 12,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_Y12 */
++	{
++		.name = "16 bpp, Greyscale",
++		.fourcc = V4L2_PIX_FMT_Y16,
++		.depth = 16,
++		.flags = 0,
++	},
++#ifdef V4L2_PIX_FMT_YUV444
++	{
++		.name = "16 bpp xxxxyyyy uuuuvvvv",
++		.fourcc = V4L2_PIX_FMT_YUV444,
++		.depth = 16,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_YUV444 */
++#ifdef V4L2_PIX_FMT_YUV555
++	{
++		.name = "16 bpp YUV-5-5-5",
++		.fourcc = V4L2_PIX_FMT_YUV555,
++		.depth = 16,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_YUV555 */
++#ifdef V4L2_PIX_FMT_YUV565
++	{
++		.name = "16 bpp YUV-5-6-5",
++		.fourcc = V4L2_PIX_FMT_YUV565,
++		.depth = 16,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_YUV565 */
++
++/* bayer formats */
++#ifdef V4L2_PIX_FMT_SRGGB8
++	{
++		.name = "Bayer RGGB 8bit",
++		.fourcc = V4L2_PIX_FMT_SRGGB8,
++		.depth = 8,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_SRGGB8 */
++#ifdef V4L2_PIX_FMT_SGRBG8
++	{
++		.name = "Bayer GRBG 8bit",
++		.fourcc = V4L2_PIX_FMT_SGRBG8,
++		.depth = 8,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_SGRBG8 */
++#ifdef V4L2_PIX_FMT_SGBRG8
++	{
++		.name = "Bayer GBRG 8bit",
++		.fourcc = V4L2_PIX_FMT_SGBRG8,
++		.depth = 8,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_SGBRG8 */
++#ifdef V4L2_PIX_FMT_SBGGR8
++	{
++		.name = "Bayer BA81 8bit",
++		.fourcc = V4L2_PIX_FMT_SBGGR8,
++		.depth = 8,
++		.flags = 0,
++	},
++#endif /* V4L2_PIX_FMT_SBGGR8 */
++
++	/* here come the planar formats */
++	{
++		.name = "4:1:0, planar, Y-Cr-Cb",
++		.fourcc = V4L2_PIX_FMT_YVU410,
++		.depth = 9,
++		.flags = FORMAT_FLAGS_PLANAR,
++	},
++	{
++		.name = "4:2:0, planar, Y-Cr-Cb",
++		.fourcc = V4L2_PIX_FMT_YVU420,
++		.depth = 12,
++		.flags = FORMAT_FLAGS_PLANAR,
++	},
++	{
++		.name = "4:1:0, planar, Y-Cb-Cr",
++		.fourcc = V4L2_PIX_FMT_YUV410,
++		.depth = 9,
++		.flags = FORMAT_FLAGS_PLANAR,
++	},
++	{
++		.name = "4:2:0, planar, Y-Cb-Cr",
++		.fourcc = V4L2_PIX_FMT_YUV420,
++		.depth = 12,
++		.flags = FORMAT_FLAGS_PLANAR,
++	},
++#ifdef V4L2_PIX_FMT_YUV422P
++	{
++		.name = "16 bpp YVU422 planar",
++		.fourcc = V4L2_PIX_FMT_YUV422P,
++		.depth = 16,
++		.flags = FORMAT_FLAGS_PLANAR,
++	},
++#endif /* V4L2_PIX_FMT_YUV422P */
++#ifdef V4L2_PIX_FMT_YUV411P
++	{
++		.name = "16 bpp YVU411 planar",
++		.fourcc = V4L2_PIX_FMT_YUV411P,
++		.depth = 16,
++		.flags = FORMAT_FLAGS_PLANAR,
++	},
++#endif /* V4L2_PIX_FMT_YUV411P */
++#ifdef V4L2_PIX_FMT_Y41P
++	{
++		.name = "12 bpp YUV 4:1:1",
++		.fourcc = V4L2_PIX_FMT_Y41P,
++		.depth = 12,
++		.flags = FORMAT_FLAGS_PLANAR,
++	},
++#endif /* V4L2_PIX_FMT_Y41P */
++#ifdef V4L2_PIX_FMT_NV12
++	{
++		.name = "12 bpp Y/CbCr 4:2:0 ",
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.depth = 12,
++		.flags = FORMAT_FLAGS_PLANAR,
++	},
++#endif /* V4L2_PIX_FMT_NV12 */
++
++/* here come the compressed formats */
++
++#ifdef V4L2_PIX_FMT_MJPEG
++	{
++		.name = "Motion-JPEG",
++		.fourcc = V4L2_PIX_FMT_MJPEG,
++		.depth = 32,
++		.flags = FORMAT_FLAGS_COMPRESSED,
++	},
++#endif /* V4L2_PIX_FMT_MJPEG */
++#ifdef V4L2_PIX_FMT_JPEG
++	{
++		.name = "JFIF JPEG",
++		.fourcc = V4L2_PIX_FMT_JPEG,
++		.depth = 32,
++		.flags = FORMAT_FLAGS_COMPRESSED,
++	},
++#endif /* V4L2_PIX_FMT_JPEG */
++#ifdef V4L2_PIX_FMT_DV
++	{
++		.name = "DV1394",
++		.fourcc = V4L2_PIX_FMT_DV,
++		.depth = 32,
++		.flags = FORMAT_FLAGS_COMPRESSED,
++	},
++#endif /* V4L2_PIX_FMT_DV */
++#ifdef V4L2_PIX_FMT_MPEG
++	{
++		.name = "MPEG-1/2/4 Multiplexed",
++		.fourcc = V4L2_PIX_FMT_MPEG,
++		.depth = 32,
++		.flags = FORMAT_FLAGS_COMPRESSED,
++	},
++#endif /* V4L2_PIX_FMT_MPEG */
++#ifdef V4L2_PIX_FMT_H264
++	{
++		.name = "H264 with start codes",
++		.fourcc = V4L2_PIX_FMT_H264,
++		.depth = 32,
++		.flags = FORMAT_FLAGS_COMPRESSED,
++	},
++#endif /* V4L2_PIX_FMT_H264 */
++#ifdef V4L2_PIX_FMT_H264_NO_SC
++	{
++		.name = "H264 without start codes",
++		.fourcc = V4L2_PIX_FMT_H264_NO_SC,
++		.depth = 32,
++		.flags = FORMAT_FLAGS_COMPRESSED,
++	},
++#endif /* V4L2_PIX_FMT_H264_NO_SC */
++#ifdef V4L2_PIX_FMT_H264_MVC
++	{
++		.name = "H264 MVC",
++		.fourcc = V4L2_PIX_FMT_H264_MVC,
++		.depth = 32,
++		.flags = FORMAT_FLAGS_COMPRESSED,
++	},
++#endif /* V4L2_PIX_FMT_H264_MVC */
++#ifdef V4L2_PIX_FMT_H263
++	{
++		.name = "H263",
++		.fourcc = V4L2_PIX_FMT_H263,
++		.depth = 32,
++		.flags = FORMAT_FLAGS_COMPRESSED,
++	},
++#endif /* V4L2_PIX_FMT_H263 */
++#ifdef V4L2_PIX_FMT_MPEG1
++	{
++		.name = "MPEG-1 ES",
++		.fourcc = V4L2_PIX_FMT_MPEG1,
++		.depth = 32,
++		.flags = FORMAT_FLAGS_COMPRESSED,
++	},
++#endif /* V4L2_PIX_FMT_MPEG1 */
++#ifdef V4L2_PIX_FMT_MPEG2
++	{
++		.name = "MPEG-2 ES",
++		.fourcc = V4L2_PIX_FMT_MPEG2,
++		.depth = 32,
++		.flags = FORMAT_FLAGS_COMPRESSED,
++	},
++#endif /* V4L2_PIX_FMT_MPEG2 */
++#ifdef V4L2_PIX_FMT_MPEG4
++	{
++		.name = "MPEG-4 part 2 ES",
++		.fourcc = V4L2_PIX_FMT_MPEG4,
++		.depth = 32,
++		.flags = FORMAT_FLAGS_COMPRESSED,
++	},
++#endif /* V4L2_PIX_FMT_MPEG4 */
++#ifdef V4L2_PIX_FMT_XVID
++	{
++		.name = "Xvid",
++		.fourcc = V4L2_PIX_FMT_XVID,
++		.depth = 32,
++		.flags = FORMAT_FLAGS_COMPRESSED,
++	},
++#endif /* V4L2_PIX_FMT_XVID */
++#ifdef V4L2_PIX_FMT_VC1_ANNEX_G
++	{
++		.name = "SMPTE 421M Annex G compliant stream",
++		.fourcc = V4L2_PIX_FMT_VC1_ANNEX_G,
++		.depth = 32,
++		.flags = FORMAT_FLAGS_COMPRESSED,
++	},
++#endif /* V4L2_PIX_FMT_VC1_ANNEX_G */
++#ifdef V4L2_PIX_FMT_VC1_ANNEX_L
++	{
++		.name = "SMPTE 421M Annex L compliant stream",
++		.fourcc = V4L2_PIX_FMT_VC1_ANNEX_L,
++		.depth = 32,
++		.flags = FORMAT_FLAGS_COMPRESSED,
++	},
++#endif /* V4L2_PIX_FMT_VC1_ANNEX_L */
++#ifdef V4L2_PIX_FMT_VP8
++	{
++		.name = "VP8",
++		.fourcc = V4L2_PIX_FMT_VP8,
++		.depth = 32,
++		.flags = FORMAT_FLAGS_COMPRESSED,
++	},
++#endif /* V4L2_PIX_FMT_VP8 */
++#ifdef V4L2_PIX_FMT_VP9
++	{
++		.name = "VP9",
++		.fourcc = V4L2_PIX_FMT_VP9,
++		.depth = 32,
++		.flags = FORMAT_FLAGS_COMPRESSED,
++	},
++#endif /* V4L2_PIX_FMT_VP9 */
++#ifdef V4L2_PIX_FMT_HEVC
++	{
++		.name = "HEVC",
++		.fourcc = V4L2_PIX_FMT_HEVC,
++		.depth = 32,
++		.flags = FORMAT_FLAGS_COMPRESSED,
++	},
++#endif /* V4L2_PIX_FMT_HEVC */
+diff --git a/drivers/mmc/core/block.c b/drivers/mmc/core/block.c
+index 66a00b7c7..0af727295 100644
+--- a/drivers/mmc/core/block.c
++++ b/drivers/mmc/core/block.c
+@@ -94,6 +94,9 @@ static int max_devices;
+ 
+ static DEFINE_IDA(mmc_blk_ida);
+ static DEFINE_IDA(mmc_rpmb_ida);
++#ifndef CONFIG_MMC_INDEX_MATCH_CONTROLLER
++static DECLARE_BITMAP(name_use, MAX_DEVICES);
++#endif
+ 
+ /*
+  * There is one mmc_blk_data per slot.
+@@ -112,6 +115,7 @@ struct mmc_blk_data {
+ 	unsigned int	usage;
+ 	unsigned int	read_only;
+ 	unsigned int	part_type;
++	unsigned int	name_idx;
+ 	unsigned int	reset_done;
+ #define MMC_BLK_READ		BIT(0)
+ #define MMC_BLK_WRITE		BIT(1)
+@@ -2303,6 +2307,24 @@ static struct mmc_blk_data *mmc_blk_alloc_req(struct mmc_card *card,
+ 		goto out;
+ 	}
+ 
++#ifdef CONFIG_MMC_INDEX_MATCH_CONTROLLER
++	/* Corresponding to the controller node */
++	md->name_idx = card->host->index;
++#else
++	/*
++	 * !subname implies we are creating main mmc_blk_data that will be
++	 * associated with mmc_card with dev_set_drvdata. Due to device
++	 * partitions, devidx will not coincide with a per-physical card
++	 * index anymore so we keep track of a name index.
++	 */
++	if (!subname) {
++		md->name_idx = find_first_zero_bit(name_use, max_devices);
++		__set_bit(md->name_idx, name_use);
++	} else
++		md->name_idx = ((struct mmc_blk_data *)
++				dev_to_disk(parent)->private_data)->name_idx;
++#endif
++
+ 	md->area_type = area_type;
+ 
+ 	/*
+@@ -2364,7 +2386,7 @@ static struct mmc_blk_data *mmc_blk_alloc_req(struct mmc_card *card,
+ 	 */
+ 
+ 	snprintf(md->disk->disk_name, sizeof(md->disk->disk_name),
+-		 "mmcblk%u%s", card->host->index, subname ? subname : "");
++		 "mmcblk%u%s", md->name_idx, subname ? subname : "");
+ 
+ 	set_capacity(md->disk, size);
+ 
+@@ -2551,7 +2573,7 @@ static int mmc_blk_alloc_rpmb_part(struct mmc_card *card,
+ 	}
+ 
+ 	snprintf(rpmb_name, sizeof(rpmb_name),
+-		 "mmcblk%u%s", card->host->index, subname ? subname : "");
++		 "mmcblk%u%s", md->name_idx, subname ? subname : "");
+ 
+ 	rpmb->id = devidx;
+ 	rpmb->part_index = part_index;
+@@ -2670,6 +2692,9 @@ static void mmc_blk_remove_parts(struct mmc_card *card,
+ 	struct mmc_blk_data *part_md;
+ 	struct mmc_rpmb_data *rpmb;
+ 
++#ifndef CONFIG_MMC_INDEX_MATCH_CONTROLLER
++	__clear_bit(md->name_idx, name_use);
++#endif
+ 	/* Remove RPMB partitions */
+ 	list_for_each_safe(pos, q, &md->rpmbs) {
+ 		rpmb = list_entry(pos, struct mmc_rpmb_data, node);
+diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
+index eb82f6aac..d79dda762 100644
+--- a/drivers/mmc/core/core.c
++++ b/drivers/mmc/core/core.c
+@@ -2249,7 +2249,7 @@ void mmc_rescan(struct work_struct *work)
+ 	/* If there is a non-removable card registered, only scan once */
+ 	if (!mmc_card_is_removable(host) && host->rescan_entered)
+ 		return;
+-	host->rescan_entered = 1;
++	//host->rescan_entered = 1; /* To support wifi rescan. */
+ 
+ 	if (host->trigger_card_event && host->ops->card_event) {
+ 		mmc_claim_host(host);
+@@ -2261,7 +2261,8 @@ void mmc_rescan(struct work_struct *work)
+ 	mmc_bus_get(host);
+ 
+ 	/* Verify a registered card to be functional, else remove it. */
+-	if (host->bus_ops && !host->bus_dead)
++	if (host->bus_ops && !host->bus_dead
++	    && !(host->caps & MMC_CAP_NONREMOVABLE))
+ 		host->bus_ops->detect(host);
+ 
+ 	host->detect_change = 0;
+diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
+index 03e2f965a..0d31a7d58 100644
+--- a/drivers/mmc/core/host.c
++++ b/drivers/mmc/core/host.c
+@@ -32,7 +32,12 @@
+ 
+ #define cls_dev_to_mmc_host(d)	container_of(d, struct mmc_host, class_dev)
+ 
++#ifdef CONFIG_MMC_INDEX_MATCH_CONTROLLER
+ static DEFINE_IDA(mmc_host_ida);
++#else
++static DEFINE_IDR(mmc_host_idr);
++static DEFINE_SPINLOCK(mmc_host_lock);
++#endif
+ 
+ #ifdef CONFIG_PM_SLEEP
+ static int mmc_host_class_prepare(struct device *dev)
+@@ -66,16 +71,19 @@ static const struct dev_pm_ops mmc_host_class_dev_pm_ops = {
+ };
+ 
+ #define MMC_HOST_CLASS_DEV_PM_OPS (&mmc_host_class_dev_pm_ops)
+-#else
+-#define MMC_HOST_CLASS_DEV_PM_OPS NULL
+ #endif
+ 
+ static void mmc_host_classdev_release(struct device *dev)
+ {
+ 	struct mmc_host *host = cls_dev_to_mmc_host(dev);
+ 	wakeup_source_unregister(host->ws);
+-	if (of_alias_get_id(host->parent->of_node, "mmc") < 0)
+-		ida_simple_remove(&mmc_host_ida, host->index);
++#ifdef CONFIG_MMC_INDEX_MATCH_CONTROLLER
++	ida_simple_remove(&mmc_host_ida, host->index);
++#else
++	spin_lock(&mmc_host_lock);
++	idr_remove(&mmc_host_idr, host->index);
++	spin_unlock(&mmc_host_lock);
++#endif
+ 	kfree(host);
+ }
+ 
+@@ -423,6 +431,7 @@ int mmc_of_parse_voltage(struct device_node *np, u32 *mask)
+ }
+ EXPORT_SYMBOL(mmc_of_parse_voltage);
+ 
++#ifdef CONFIG_MMC_INDEX_MATCH_CONTROLLER
+ /**
+  * mmc_first_nonreserved_index() - get the first index that is not reserved
+  */
+@@ -436,6 +445,7 @@ static int mmc_first_nonreserved_index(void)
+ 
+ 	return max + 1;
+ }
++#endif
+ 
+ /**
+  *	mmc_alloc_host - initialise the per-host structure.
+@@ -448,7 +458,6 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *dev)
+ {
+ 	int index;
+ 	struct mmc_host *host;
+-	int alias_id, min_idx, max_idx;
+ 
+ 	host = kzalloc(sizeof(struct mmc_host) + extra, GFP_KERNEL);
+ 	if (!host)
+@@ -457,21 +466,40 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *dev)
+ 	/* scanning will be enabled when we're ready */
+ 	host->rescan_disable = 1;
+ 
+-	alias_id = of_alias_get_id(dev->of_node, "mmc");
+-	if (alias_id >= 0) {
+-		index = alias_id;
+-	} else {
+-		min_idx = mmc_first_nonreserved_index();
+-		max_idx = 0;
++#ifdef CONFIG_MMC_INDEX_MATCH_CONTROLLER
++	int err = 0;
++	{
++		int alias_id, min_idx, max_idx;
++		alias_id = of_alias_get_id(dev->of_node, "mmc");
++		if (alias_id >= 0) {
++			min_idx = alias_id;
++			max_idx = alias_id + 1;
++		} else {
++			min_idx = mmc_first_nonreserved_index();
++			max_idx = 0;
++		}
+ 
+-		index = ida_simple_get(&mmc_host_ida, min_idx, max_idx, GFP_KERNEL);
+-		if (index < 0) {
++		err = ida_simple_get(&mmc_host_ida, min_idx, max_idx, GFP_KERNEL);
++		if (err < 0) {
+ 			kfree(host);
+ 			return NULL;
+ 		}
+ 	}
+ 
+-	host->index = index;
++	host->index = err;
++#else
++	idr_preload(GFP_KERNEL);
++	spin_lock(&mmc_host_lock);
++	err = idr_alloc(&mmc_host_idr, host, 0, 0, GFP_NOWAIT);
++	if (err >= 0)
++		host->index = err;
++	spin_unlock(&mmc_host_lock);
++	idr_preload_end();
++	if (err < 0) {
++		kfree(host);
++		return NULL;
++	}
++#endif
+ 
+ 	dev_set_name(&host->class_dev, "mmc%d", host->index);
+ 	host->ws = wakeup_source_register(NULL, dev_name(&host->class_dev));
+diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c
+index 99a4ce68d..63bc6b3d9 100644
+--- a/drivers/mmc/core/sdio.c
++++ b/drivers/mmc/core/sdio.c
+@@ -1308,3 +1308,39 @@ int mmc_attach_sdio(struct mmc_host *host)
+ 	return err;
+ }
+ 
++int sdio_reset_comm(struct mmc_card *card)
++{
++	struct mmc_host *host = card->host;
++	u32 ocr;
++	int err;
++
++	printk("%s():\n", __func__);
++	mmc_claim_host(host);
++
++	mmc_go_idle(host);
++
++	mmc_set_clock(host, host->f_min);
++
++	err = mmc_send_io_op_cond(host, 0, &ocr);
++	if (err)
++		goto err;
++
++	host->ocr_avail_sdio = mmc_select_voltage(host, ocr);
++	if (!host->ocr_avail_sdio) {
++		err = -EINVAL;
++		goto err;
++	}
++
++	err = mmc_sdio_init_card(host, host->ocr_avail_sdio, card);
++	if (err)
++		goto err;
++
++	mmc_release_host(host);
++	return 0;
++err:
++	printk("%s: Error resetting SDIO communications (%d)\n",
++	       mmc_hostname(host), err);
++	mmc_release_host(host);
++	return err;
++}
++EXPORT_SYMBOL(sdio_reset_comm);
+diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
+index d42e86cdf..0a37f59ff 100644
+--- a/drivers/mmc/host/sdhci.c
++++ b/drivers/mmc/host/sdhci.c
+@@ -1541,8 +1541,7 @@ static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
+ 	 */
+ 	if (data->error) {
+ 		if (!host->cmd || host->cmd == data_cmd)
+-			sdhci_do_reset(host, SDHCI_RESET_CMD);
+-		sdhci_do_reset(host, SDHCI_RESET_DATA);
++			sdhci_do_reset(host, SDHCI_RESET_DATA);
+ 	}
+ 
+ 	if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
+@@ -2096,6 +2095,8 @@ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
+ 			sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
+ 
+ 		pwr |= SDHCI_POWER_ON;
++		if(host->ops->power_set)
++			host->ops->power_set(host,MMC_POWER_UP);
+ 
+ 		sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
+ 
+@@ -2280,6 +2281,8 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+ 	if (ios->power_mode == MMC_POWER_OFF) {
+ 		sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
+ 		sdhci_reinit(host);
++		if(host->ops->power_set)
++			host->ops->power_set(host,MMC_POWER_OFF);
+ 	}
+ 
+ 	if (host->version >= SDHCI_SPEC_300 &&
+@@ -2558,6 +2561,8 @@ int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ 		ctrl &= ~SDHCI_CTRL_VDD_180;
+ 		sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ 
++		if (host->ops->voltage_switch)
++			host->ops->voltage_switch(host,MMC_SIGNAL_VOLTAGE_330);
+ 		if (!IS_ERR(mmc->supply.vqmmc)) {
+ 			ret = mmc_regulator_set_vqmmc(mmc, ios);
+ 			if (ret < 0) {
+@@ -2599,7 +2604,7 @@ int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ 
+ 		/* Some controller need to do more when switching */
+ 		if (host->ops->voltage_switch)
+-			host->ops->voltage_switch(host);
++			host->ops->voltage_switch(host,MMC_SIGNAL_VOLTAGE_180);
+ 
+ 		/* 1.8V regulator output should be stable within 5 ms */
+ 		ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+@@ -2969,8 +2974,8 @@ static void sdhci_card_event(struct mmc_host *mmc)
+ 		pr_err("%s: Resetting controller.\n",
+ 			mmc_hostname(host->mmc));
+ 
+-		sdhci_do_reset(host, SDHCI_RESET_CMD);
+ 		sdhci_do_reset(host, SDHCI_RESET_DATA);
++		sdhci_do_reset(host, SDHCI_RESET_CMD);
+ 
+ 		sdhci_error_out_mrqs(host, -ENOMEDIUM);
+ 	}
+@@ -3865,8 +3870,8 @@ void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
+ 	host->cqe_on = false;
+ 
+ 	if (recovery) {
+-		sdhci_do_reset(host, SDHCI_RESET_CMD);
+ 		sdhci_do_reset(host, SDHCI_RESET_DATA);
++		sdhci_do_reset(host, SDHCI_RESET_CMD);
+ 	}
+ 
+ 	pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
+diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
+index 8b1650f37..6e8faec4b 100644
+--- a/drivers/mmc/host/sdhci.h
++++ b/drivers/mmc/host/sdhci.h
+@@ -646,7 +646,8 @@ struct sdhci_ops {
+ 	void	(*hw_reset)(struct sdhci_host *host);
+ 	void    (*adma_workaround)(struct sdhci_host *host, u32 intmask);
+ 	void    (*card_event)(struct sdhci_host *host);
+-	void	(*voltage_switch)(struct sdhci_host *host);
++	void	(*voltage_switch)(struct sdhci_host *host,int vlotage);
++	void	(*power_set)(struct sdhci_host *host,int vlotage);
+ 	void	(*adma_write_desc)(struct sdhci_host *host, void **desc,
+ 				   dma_addr_t addr, int len, unsigned int cmd);
+ 	void	(*copy_to_bounce_buffer)(struct sdhci_host *host,
+diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
+index 6ddab7962..bbddeccf5 100644
+--- a/drivers/mtd/Kconfig
++++ b/drivers/mtd/Kconfig
+@@ -70,6 +70,21 @@ config MTD_BLOCK_RO
+ 	  You do not need this option for use with the DiskOnChip devices. For
+ 	  those, enable NFTL support (CONFIG_NFTL) instead.
+ 
++config MTD_BLOCK_BBT_RO
++	tristate "Bad block tab based readonly block device access to MTD devices, "
++	depends on BLOCK
++	select MTD_BLKDEVS
++	help
++	  This allows you to mount read-only file systems (such as squashfs)
++	  There is a bad block tab to skip the bad block on nand for readonly use.
++	  It's a sample bad block tab, create at init, so you'd better don't write
++	  the nand at runtime.
++
++config MTD_BLOCK_BBT_RO_BLOCK_SIZE
++	int "block size of /dev/mtdblock_bbt_ro"
++	depends on MTD_BLOCK_BBT_RO
++	default 4096
++
+ config FTL
+ 	tristate "FTL (Flash Translation Layer) support"
+ 	depends on BLOCK
+diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
+index 593d0593a..bfecfa486 100644
+--- a/drivers/mtd/Makefile
++++ b/drivers/mtd/Makefile
+@@ -13,6 +13,7 @@ obj-y				+= parsers/
+ obj-$(CONFIG_MTD_BLKDEVS)	+= mtd_blkdevs.o
+ obj-$(CONFIG_MTD_BLOCK)		+= mtdblock.o
+ obj-$(CONFIG_MTD_BLOCK_RO)	+= mtdblock_ro.o
++obj-$(CONFIG_MTD_BLOCK_BBT_RO) += mtdblock_bbt_ro.o
+ obj-$(CONFIG_FTL)		+= ftl.o
+ obj-$(CONFIG_NFTL)		+= nftl.o
+ obj-$(CONFIG_INFTL)		+= inftl.o
+diff --git a/drivers/mtd/mtdblock_bbt_ro.c b/drivers/mtd/mtdblock_bbt_ro.c
+new file mode 100644
+index 000000000..5f6d5a135
+--- /dev/null
++++ b/drivers/mtd/mtdblock_bbt_ro.c
+@@ -0,0 +1,184 @@
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/blktrans.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/major.h>
++
++struct m_mtd_data {
++	struct mtd_blktrans_dev dev;
++	void *bbt;
++	int block_count;
++	int usable_count;
++};
++
++#define MY_BLOCK_SIZE CONFIG_MTD_BLOCK_BBT_RO_BLOCK_SIZE
++
++static void create_bbt(struct m_mtd_data *data, struct mtd_info *mtd)
++{
++	int i, bad_count;
++	loff_t offs = 0;
++	int block_count = mtd_div_by_eb(mtd->size, mtd);
++	int item_size;
++	void *bbt;
++
++
++	if (block_count < 256)
++		item_size = 1;
++	else if (block_count < 65536)
++		item_size = 2;
++	else
++		item_size = 4;
++
++	bbt = kzalloc(block_count * item_size, GFP_KERNEL);
++	BUG_ON(!bbt);
++
++	for (i = 0, bad_count = 0; i < block_count; i++) {
++		int is_bad = mtd_block_isbad(mtd, offs) > 0;
++		offs += mtd->erasesize;
++		if (is_bad) {
++			bad_count++;
++			continue;
++		}
++
++		switch (item_size) {
++		case 1:
++			((unsigned char *)bbt)[i-bad_count] = i; break;
++		case 2:
++			((unsigned short *)bbt)[i-bad_count] = i; break;
++		case 4:
++			((unsigned int *)bbt)[i-bad_count] = i; break;
++		}
++	}
++
++	printk("mtd: %s %lld %d %d\n",
++		mtd->name, mtd->size, mtd->erasesize, bad_count);
++
++	data->usable_count = block_count - bad_count;
++	data->block_count = block_count;
++	data->bbt = bbt;
++}
++
++static unsigned int get_from_bbt(struct m_mtd_data *data, int index)
++{
++	int block_count = data->block_count;
++	void *bbt = data->bbt;
++	int ret;
++
++	if (block_count < 256)
++		ret = ((unsigned char *)bbt)[index];
++	else if (block_count < 65536)
++		ret = ((unsigned short *)bbt)[index];
++	else
++		ret = ((unsigned int *)bbt)[index];
++
++	if (ret == 0)
++		return index ? -1 : 0;
++	else
++		return ret;
++}
++
++static int mtdblock_readsect(struct mtd_blktrans_dev *dev,
++				  unsigned long block, char *buf)
++{
++	struct m_mtd_data *data = (struct m_mtd_data *)dev;
++	struct mtd_info *mtd = dev->mtd;
++	int index = mtd_div_by_eb(((uint64_t)block * MY_BLOCK_SIZE), mtd);
++	int delta = mtd_mod_by_eb(((uint64_t)block * MY_BLOCK_SIZE), mtd);
++	int err;
++	loff_t off;
++	size_t retlen;
++
++	if (!data->bbt)
++		create_bbt(data, mtd);
++
++	if (!data->usable_count)
++		return -EOVERFLOW;
++
++	index = get_from_bbt(data, index);
++	if (index < 0)
++		return -EOVERFLOW;
++
++	off = index * mtd->erasesize + delta;
++
++	err = mtd_read(dev->mtd, off, MY_BLOCK_SIZE, &retlen, buf);
++	if (err) {
++			/*
++			 * -EUCLEAN is reported if there was a bit-flip which
++			 * was corrected, so this is harmless.
++			 *
++			 * We do not report about it here unless debugging is
++			 * enabled. A corresponding message will be printed
++			 * later, when it is has been scrubbed.
++			 */
++		if (mtd_is_bitflip(err) && (MY_BLOCK_SIZE == retlen))
++			return 0;
++		else
++			return 1;
++	}
++
++	return 0;
++}
++
++static int mtdblock_writesect(struct mtd_blktrans_dev *dev,
++				  unsigned long block, char *buf)
++{
++	return 1;
++}
++
++static void mtdblock_add_mtd(struct mtd_blktrans_ops *tr, struct mtd_info *mtd)
++{
++	struct m_mtd_data *data = kzalloc(sizeof(*data), GFP_KERNEL);
++	struct mtd_blktrans_dev *dev = (struct mtd_blktrans_dev *)data;
++	BUG_ON(!data);
++
++	dev->mtd = mtd;
++	dev->devnum = mtd->index;
++	dev->size = mtd->size / MY_BLOCK_SIZE;
++	dev->tr = tr;
++	dev->readonly = 1;
++
++	if (add_mtd_blktrans_dev(dev))
++		kfree(dev);
++}
++
++static void mtdblock_remove_dev(struct mtd_blktrans_dev *dev)
++{
++	struct m_mtd_data *data = (struct m_mtd_data *)dev;
++
++	if (data->bbt)
++		kfree(data->bbt);
++
++	del_mtd_blktrans_dev(dev);
++
++}
++
++static struct mtd_blktrans_ops mtdblock_tr = {
++	.name		= "mtdblock_bbt_ro",
++	.major		= MTD_BLOCK_MAJOR,
++	.part_bits	= 0,
++	.blksize 	= MY_BLOCK_SIZE,
++	.readsect	= mtdblock_readsect,
++	.writesect	= mtdblock_writesect,
++	.add_mtd	= mtdblock_add_mtd,
++	.remove_dev	= mtdblock_remove_dev,
++	.owner		= THIS_MODULE,
++};
++
++static int __init mtdblock_init(void)
++{
++	return register_mtd_blktrans(&mtdblock_tr);
++}
++
++static void __exit mtdblock_exit(void)
++{
++	deregister_mtd_blktrans(&mtdblock_tr);
++}
++
++module_init(mtdblock_init);
++module_exit(mtdblock_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("wujiao");
++MODULE_DESCRIPTION("Simple bad block tab based read-only block device emulation access to MTD devices");
+diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c
+index 1433260d9..c9bdeb4dd 100644
+--- a/drivers/usb/common/common.c
++++ b/drivers/usb/common/common.c
+@@ -25,6 +25,12 @@ static const char *const ep_type_names[] = {
+ 	[USB_ENDPOINT_XFER_INT] = "intr",
+ };
+ 
++/**
++ * usb_ep_type_string() - Returns human readable-name of the endpoint type.
++ * @ep_type: The endpoint type to return human-readable name for.  If it's not
++ *   any of the types: USB_ENDPOINT_XFER_{CONTROL, ISOC, BULK, INT},
++ *   usually got by usb_endpoint_type(), the string 'unknown' will be returned.
++ */
+ const char *usb_ep_type_string(int ep_type)
+ {
+ 	if (ep_type < 0 || ep_type >= ARRAY_SIZE(ep_type_names))
+@@ -69,6 +75,19 @@ static const char *const speed_names[] = {
+ 	[USB_SPEED_SUPER_PLUS] = "super-speed-plus",
+ };
+ 
++static const char *const ssp_rate[] = {
++	[USB_SSP_GEN_UNKNOWN] = "UNKNOWN",
++	[USB_SSP_GEN_2x1] = "super-speed-plus-gen2x1",
++	[USB_SSP_GEN_1x2] = "super-speed-plus-gen1x2",
++	[USB_SSP_GEN_2x2] = "super-speed-plus-gen2x2",
++};
++
++/**
++ * usb_speed_string() - Returns human readable-name of the speed.
++ * @speed: The speed to return human-readable name for.  If it's not
++ *   any of the speeds defined in usb_device_speed enum, string for
++ *   USB_SPEED_UNKNOWN will be returned.
++ */
+ const char *usb_speed_string(enum usb_device_speed speed)
+ {
+ 	if (speed < 0 || speed >= ARRAY_SIZE(speed_names))
+@@ -77,6 +96,14 @@ const char *usb_speed_string(enum usb_device_speed speed)
+ }
+ EXPORT_SYMBOL_GPL(usb_speed_string);
+ 
++/**
++ * usb_get_maximum_speed - Get maximum requested speed for a given USB
++ * controller.
++ * @dev: Pointer to the given USB controller device
++ *
++ * The function gets the maximum speed string from property "maximum-speed",
++ * and returns the corresponding enum usb_device_speed.
++ */
+ enum usb_device_speed usb_get_maximum_speed(struct device *dev)
+ {
+ 	const char *maximum_speed;
+@@ -86,12 +113,44 @@ enum usb_device_speed usb_get_maximum_speed(struct device *dev)
+ 	if (ret < 0)
+ 		return USB_SPEED_UNKNOWN;
+ 
+-	ret = match_string(speed_names, ARRAY_SIZE(speed_names), maximum_speed);
++	ret = match_string(ssp_rate, ARRAY_SIZE(ssp_rate), maximum_speed);
++	if (ret > 0)
++		return USB_SPEED_SUPER_PLUS;
+ 
++	ret = match_string(speed_names, ARRAY_SIZE(speed_names), maximum_speed);
+ 	return (ret < 0) ? USB_SPEED_UNKNOWN : ret;
+ }
+ EXPORT_SYMBOL_GPL(usb_get_maximum_speed);
+ 
++/**
++ * usb_get_maximum_ssp_rate - Get the signaling rate generation and lane count
++ *	of a SuperSpeed Plus capable device.
++ * @dev: Pointer to the given USB controller device
++ *
++ * If the string from "maximum-speed" property is super-speed-plus-genXxY where
++ * 'X' is the generation number and 'Y' is the number of lanes, then this
++ * function returns the corresponding enum usb_ssp_rate.
++ */
++enum usb_ssp_rate usb_get_maximum_ssp_rate(struct device *dev)
++{
++	const char *maximum_speed;
++	int ret;
++
++	ret = device_property_read_string(dev, "maximum-speed", &maximum_speed);
++	if (ret < 0)
++		return USB_SSP_GEN_UNKNOWN;
++
++	ret = match_string(ssp_rate, ARRAY_SIZE(ssp_rate), maximum_speed);
++	return (ret < 0) ? USB_SSP_GEN_UNKNOWN : ret;
++}
++EXPORT_SYMBOL_GPL(usb_get_maximum_ssp_rate);
++
++/**
++ * usb_state_string - Returns human readable name for the state.
++ * @state: The state to return a human-readable name for. If it's not
++ *	any of the states devices in usb_device_state_string enum,
++ *	the string UNKNOWN will be returned.
++ */
+ const char *usb_state_string(enum usb_device_state state)
+ {
+ 	static const char *const names[] = {
+@@ -141,6 +200,67 @@ enum usb_dr_mode usb_get_dr_mode(struct device *dev)
+ }
+ EXPORT_SYMBOL_GPL(usb_get_dr_mode);
+ 
++/**
++ * usb_get_role_switch_default_mode - Get default mode for given device
++ * @dev: Pointer to the given device
++ *
++ * The function gets string from property 'role-switch-default-mode',
++ * and returns the corresponding enum usb_dr_mode.
++ */
++enum usb_dr_mode usb_get_role_switch_default_mode(struct device *dev)
++{
++	const char *str;
++	int ret;
++
++	ret = device_property_read_string(dev, "role-switch-default-mode", &str);
++	if (ret < 0)
++		return USB_DR_MODE_UNKNOWN;
++
++	return usb_get_dr_mode_from_string(str);
++}
++EXPORT_SYMBOL_GPL(usb_get_role_switch_default_mode);
++
++/**
++ * usb_decode_interval - Decode bInterval into the time expressed in 1us unit
++ * @epd: The descriptor of the endpoint
++ * @speed: The speed that the endpoint works as
++ *
++ * Function returns the interval expressed in 1us unit for servicing
++ * endpoint for data transfers.
++ */
++unsigned int usb_decode_interval(const struct usb_endpoint_descriptor *epd,
++				 enum usb_device_speed speed)
++{
++	unsigned int interval = 0;
++
++	switch (usb_endpoint_type(epd)) {
++	case USB_ENDPOINT_XFER_CONTROL:
++		/* uframes per NAK */
++		if (speed == USB_SPEED_HIGH)
++			interval = epd->bInterval;
++		break;
++	case USB_ENDPOINT_XFER_ISOC:
++		interval = 1 << (epd->bInterval - 1);
++		break;
++	case USB_ENDPOINT_XFER_BULK:
++		/* uframes per NAK */
++		if (speed == USB_SPEED_HIGH && usb_endpoint_dir_out(epd))
++			interval = epd->bInterval;
++		break;
++	case USB_ENDPOINT_XFER_INT:
++		if (speed >= USB_SPEED_HIGH)
++			interval = 1 << (epd->bInterval - 1);
++		else
++			interval = epd->bInterval;
++		break;
++	}
++
++	interval *= (speed >= USB_SPEED_HIGH) ? 125 : 1000;
++
++	return interval;
++}
++EXPORT_SYMBOL_GPL(usb_decode_interval);
++
+ #ifdef CONFIG_OF
+ /**
+  * of_usb_get_dr_mode_by_phy - Get dual role mode for the controller device
+diff --git a/drivers/usb/common/debug.c b/drivers/usb/common/debug.c
+index ba849c7bc..a76a086b9 100644
+--- a/drivers/usb/common/debug.c
++++ b/drivers/usb/common/debug.c
+@@ -207,8 +207,26 @@ static void usb_decode_set_isoch_delay(__u8 wValue, char *str, size_t size)
+ 	snprintf(str, size, "Set Isochronous Delay(Delay = %d ns)", wValue);
+ }
+ 
+-/*
+- * usb_decode_ctrl - returns a string representation of ctrl request
++/**
++ * usb_decode_ctrl - Returns human readable representation of control request.
++ * @str: buffer to return a human-readable representation of control request.
++ *       This buffer should have about 200 bytes.
++ * @size: size of str buffer.
++ * @bRequestType: matches the USB bmRequestType field
++ * @bRequest: matches the USB bRequest field
++ * @wValue: matches the USB wValue field (CPU byte order)
++ * @wIndex: matches the USB wIndex field (CPU byte order)
++ * @wLength: matches the USB wLength field (CPU byte order)
++ *
++ * Function returns decoded, formatted and human-readable description of
++ * control request packet.
++ *
++ * The usage scenario for this is for tracepoints, so function as a return
++ * use the same value as in parameters. This approach allows to use this
++ * function in TP_printk
++ *
++ * Important: wValue, wIndex, wLength parameters before invoking this function
++ * should be processed by le16_to_cpu macro.
+  */
+ const char *usb_decode_ctrl(char *str, size_t size, __u8 bRequestType,
+ 			    __u8 bRequest, __u16 wValue, __u16 wIndex,
+diff --git a/drivers/usb/common/usb-conn-gpio.c b/drivers/usb/common/usb-conn-gpio.c
+index c9545a4ef..581d6db36 100644
+--- a/drivers/usb/common/usb-conn-gpio.c
++++ b/drivers/usb/common/usb-conn-gpio.c
+@@ -83,11 +83,11 @@ static void usb_conn_detect_cable(struct work_struct *work)
+ 	else
+ 		role = USB_ROLE_NONE;
+ 
+-	dev_dbg(info->dev, "role %d/%d, gpios: id %d, vbus %d\n",
+-		info->last_role, role, id, vbus);
++	dev_dbg(info->dev, "role %s -> %s, gpios: id %d, vbus %d\n",
++		usb_role_string(info->last_role), usb_role_string(role), id, vbus);
+ 
+ 	if (info->last_role == role) {
+-		dev_warn(info->dev, "repeated role: %d\n", role);
++		dev_warn(info->dev, "repeated role: %s\n", usb_role_string(role));
+ 		return;
+ 	}
+ 
+diff --git a/drivers/usb/core/devices.c b/drivers/usb/core/devices.c
+index 1ef2de6e3..d8b0041de 100644
+--- a/drivers/usb/core/devices.c
++++ b/drivers/usb/core/devices.c
+@@ -157,38 +157,25 @@ static char *usb_dump_endpoint_descriptor(int speed, char *start, char *end,
+ 	switch (usb_endpoint_type(desc)) {
+ 	case USB_ENDPOINT_XFER_CONTROL:
+ 		type = "Ctrl";
+-		if (speed == USB_SPEED_HIGH)	/* uframes per NAK */
+-			interval = desc->bInterval;
+-		else
+-			interval = 0;
+ 		dir = 'B';			/* ctrl is bidirectional */
+ 		break;
+ 	case USB_ENDPOINT_XFER_ISOC:
+ 		type = "Isoc";
+-		interval = 1 << (desc->bInterval - 1);
+ 		break;
+ 	case USB_ENDPOINT_XFER_BULK:
+ 		type = "Bulk";
+-		if (speed == USB_SPEED_HIGH && dir == 'O') /* uframes per NAK */
+-			interval = desc->bInterval;
+-		else
+-			interval = 0;
+ 		break;
+ 	case USB_ENDPOINT_XFER_INT:
+ 		type = "Int.";
+-		if (speed == USB_SPEED_HIGH || speed >= USB_SPEED_SUPER)
+-			interval = 1 << (desc->bInterval - 1);
+-		else
+-			interval = desc->bInterval;
+ 		break;
+ 	default:	/* "can't happen" */
+ 		return start;
+ 	}
+-	interval *= (speed == USB_SPEED_HIGH ||
+-		     speed >= USB_SPEED_SUPER) ? 125 : 1000;
+-	if (interval % 1000)
++
++	interval = usb_decode_interval(desc, speed);
++	if (interval % 1000) {
+ 		unit = 'u';
+-	else {
++	} else {
+ 		unit = 'm';
+ 		interval /= 1000;
+ 	}
+diff --git a/drivers/usb/core/endpoint.c b/drivers/usb/core/endpoint.c
+index 1c2c04079..fc3341f2b 100644
+--- a/drivers/usb/core/endpoint.c
++++ b/drivers/usb/core/endpoint.c
+@@ -84,40 +84,13 @@ static ssize_t interval_show(struct device *dev, struct device_attribute *attr,
+ 			     char *buf)
+ {
+ 	struct ep_device *ep = to_ep_device(dev);
++	unsigned int interval;
+ 	char unit;
+-	unsigned interval = 0;
+-	unsigned in;
+ 
+-	in = (ep->desc->bEndpointAddress & USB_DIR_IN);
+-
+-	switch (usb_endpoint_type(ep->desc)) {
+-	case USB_ENDPOINT_XFER_CONTROL:
+-		if (ep->udev->speed == USB_SPEED_HIGH)
+-			/* uframes per NAK */
+-			interval = ep->desc->bInterval;
+-		break;
+-
+-	case USB_ENDPOINT_XFER_ISOC:
+-		interval = 1 << (ep->desc->bInterval - 1);
+-		break;
+-
+-	case USB_ENDPOINT_XFER_BULK:
+-		if (ep->udev->speed == USB_SPEED_HIGH && !in)
+-			/* uframes per NAK */
+-			interval = ep->desc->bInterval;
+-		break;
+-
+-	case USB_ENDPOINT_XFER_INT:
+-		if (ep->udev->speed == USB_SPEED_HIGH)
+-			interval = 1 << (ep->desc->bInterval - 1);
+-		else
+-			interval = ep->desc->bInterval;
+-		break;
+-	}
+-	interval *= (ep->udev->speed == USB_SPEED_HIGH) ? 125 : 1000;
+-	if (interval % 1000)
++	interval = usb_decode_interval(ep->desc, ep->udev->speed);
++	if (interval % 1000) {
+ 		unit = 'u';
+-	else {
++	} else {
+ 		unit = 'm';
+ 		interval /= 1000;
+ 	}
+diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
+index ac347f9d5..1103bc58a 100644
+--- a/drivers/usb/core/hcd.c
++++ b/drivers/usb/core/hcd.c
+@@ -2649,6 +2649,26 @@ static void usb_put_invalidate_rhdev(struct usb_hcd *hcd)
+ 	usb_put_dev(rhdev);
+ }
+ 
++/**
++ * usb_stop_hcd - Halt the HCD
++ * @hcd: the usb_hcd that has to be halted
++ *
++ * Stop the root-hub polling timer and invoke the HCD's ->stop callback.
++ */
++static void usb_stop_hcd(struct usb_hcd *hcd)
++{
++	hcd->rh_pollable = 0;
++	clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
++	del_timer_sync(&hcd->rh_timer);
++
++	hcd->driver->stop(hcd);
++	hcd->state = HC_STATE_HALT;
++
++	/* In case the HCD restarted the timer, stop it again. */
++	clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
++	del_timer_sync(&hcd->rh_timer);
++}
++
+ /**
+  * usb_add_hcd - finish generic HCD structure initialization and register
+  * @hcd: the usb_hcd structure to initialize
+@@ -2741,6 +2761,7 @@ int usb_add_hcd(struct usb_hcd *hcd,
+ 
+ 	rhdev->rx_lanes = 1;
+ 	rhdev->tx_lanes = 1;
++	rhdev->ssp_rate = USB_SSP_GEN_UNKNOWN;
+ 
+ 	switch (hcd->speed) {
+ 	case HCD_USB11:
+@@ -2758,8 +2779,11 @@ int usb_add_hcd(struct usb_hcd *hcd,
+ 	case HCD_USB32:
+ 		rhdev->rx_lanes = 2;
+ 		rhdev->tx_lanes = 2;
+-		fallthrough;
++		rhdev->ssp_rate = USB_SSP_GEN_2x2;
++		rhdev->speed = USB_SPEED_SUPER_PLUS;
++		break;
+ 	case HCD_USB31:
++		rhdev->ssp_rate = USB_SSP_GEN_2x1;
+ 		rhdev->speed = USB_SPEED_SUPER_PLUS;
+ 		break;
+ 	default:
+@@ -2846,13 +2870,7 @@ int usb_add_hcd(struct usb_hcd *hcd,
+ 	return retval;
+ 
+ err_register_root_hub:
+-	hcd->rh_pollable = 0;
+-	clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
+-	del_timer_sync(&hcd->rh_timer);
+-	hcd->driver->stop(hcd);
+-	hcd->state = HC_STATE_HALT;
+-	clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
+-	del_timer_sync(&hcd->rh_timer);
++    usb_stop_hcd(hcd);
+ err_hcd_driver_start:
+ 	if (usb_hcd_is_primary_hcd(hcd) && hcd->irq > 0)
+ 		free_irq(irqnum, hcd);
+@@ -2924,16 +2942,7 @@ void usb_remove_hcd(struct usb_hcd *hcd)
+ 	 * interrupt occurs), but usb_hcd_poll_rh_status() won't invoke
+ 	 * the hub_status_data() callback.
+ 	 */
+-	hcd->rh_pollable = 0;
+-	clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
+-	del_timer_sync(&hcd->rh_timer);
+-
+-	hcd->driver->stop(hcd);
+-	hcd->state = HC_STATE_HALT;
+-
+-	/* In case the HCD restarted the timer, stop it again. */
+-	clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
+-	del_timer_sync(&hcd->rh_timer);
++	usb_stop_hcd(hcd);
+ 
+ 	if (usb_hcd_is_primary_hcd(hcd)) {
+ 		if (hcd->irq > 0)
+diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
+index 18ee3914b..e230027cb 100644
+--- a/drivers/usb/core/hub.c
++++ b/drivers/usb/core/hub.c
+@@ -31,6 +31,7 @@
+ #include <linux/pm_qos.h>
+ #include <linux/kobject.h>
+ 
++#include <linux/bitfield.h>
+ #include <linux/uaccess.h>
+ #include <asm/byteorder.h>
+ 
+@@ -2861,12 +2862,11 @@ static int hub_port_wait_reset(struct usb_hub *hub, int port1,
+ 	} else {
+ 		udev->rx_lanes = 1;
+ 		udev->tx_lanes = 1;
++		udev->ssp_rate = USB_SSP_GEN_UNKNOWN;
+ 	}
+ 	if (hub_is_wusb(hub))
+ 		udev->speed = USB_SPEED_WIRELESS;
+-	else if (hub_is_superspeedplus(hub->hdev) &&
+-		 port_speed_is_ssp(hub->hdev, ext_portstatus &
+-				   USB_EXT_PORT_STAT_RX_SPEED_ID))
++	else if (udev->ssp_rate != USB_SSP_GEN_UNKNOWN)
+ 		udev->speed = USB_SPEED_SUPER_PLUS;
+ 	else if (hub_is_superspeed(hub->hdev))
+ 		udev->speed = USB_SPEED_SUPER;
+@@ -3344,6 +3344,26 @@ int usb_port_suspend(struct usb_device *udev, pm_message_t msg)
+ 		status = 0;
+ 	}
+ 	if (status) {
++		/* Check if the port has been suspended for the timeout case
++		 * to prevent the suspended port from incorrect handling.
++		 */
++		if (status == -ETIMEDOUT) {
++			int ret;
++			u16 portstatus, portchange;
++
++			portstatus = portchange = 0;
++			ret = hub_port_status(hub, port1, &portstatus,
++					&portchange);
++
++			dev_dbg(&port_dev->dev,
++				"suspend timeout, status %04x\n", portstatus);
++
++			if (ret == 0 && port_is_suspended(hub, portstatus)) {
++				status = 0;
++				goto suspend_done;
++			}
++		}
++
+ 		dev_dbg(&port_dev->dev, "can't suspend, status %d\n", status);
+ 
+ 		/* Try to enable USB3 LTM again */
+@@ -3360,6 +3380,7 @@ int usb_port_suspend(struct usb_device *udev, pm_message_t msg)
+ 		if (!PMSG_IS_AUTO(msg))
+ 			status = 0;
+ 	} else {
++ suspend_done:
+ 		dev_dbg(&udev->dev, "usb %ssuspend, wakeup %d\n",
+ 				(PMSG_IS_AUTO(msg) ? "auto-" : ""),
+ 				udev->do_remote_wakeup);
+@@ -4831,9 +4852,13 @@ hub_port_init(struct usb_hub *hub, struct usb_device *udev, int port1,
+ 						"%s SuperSpeed%s%s USB device number %d using %s\n",
+ 						(udev->config) ? "reset" : "new",
+ 					 (udev->speed == USB_SPEED_SUPER_PLUS) ?
+-							"Plus Gen 2" : " Gen 1",
+-					 (udev->rx_lanes == 2 && udev->tx_lanes == 2) ?
+-							"x2" : "",
++							" Plus" : "",
++					 (udev->ssp_rate == USB_SSP_GEN_2x2) ?
++							" Gen 2x2" :
++					 (udev->ssp_rate == USB_SSP_GEN_2x1) ?
++							" Gen 2x1" :
++					 (udev->ssp_rate == USB_SSP_GEN_1x2) ?
++							" Gen 1x2" : "",
+ 					 devnum, driver_name);
+ 			}
+ 
+diff --git a/drivers/usb/core/sysfs.c b/drivers/usb/core/sysfs.c
+index 8d134193f..3014c9356 100644
+--- a/drivers/usb/core/sysfs.c
++++ b/drivers/usb/core/sysfs.c
+@@ -167,7 +167,10 @@ static ssize_t speed_show(struct device *dev, struct device_attribute *attr,
+ 		speed = "5000";
+ 		break;
+ 	case USB_SPEED_SUPER_PLUS:
+-		speed = "10000";
++		if (udev->ssp_rate == USB_SSP_GEN_2x2)
++			speed = "20000";
++		else
++			speed = "10000";
+ 		break;
+ 	default:
+ 		speed = "unknown";
+@@ -298,29 +301,6 @@ static ssize_t urbnum_show(struct device *dev, struct device_attribute *attr,
+ }
+ static DEVICE_ATTR_RO(urbnum);
+ 
+-static ssize_t removable_show(struct device *dev, struct device_attribute *attr,
+-			      char *buf)
+-{
+-	struct usb_device *udev;
+-	char *state;
+-
+-	udev = to_usb_device(dev);
+-
+-	switch (udev->removable) {
+-	case USB_DEVICE_REMOVABLE:
+-		state = "removable";
+-		break;
+-	case USB_DEVICE_FIXED:
+-		state = "fixed";
+-		break;
+-	default:
+-		state = "unknown";
+-	}
+-
+-	return sprintf(buf, "%s\n", state);
+-}
+-static DEVICE_ATTR_RO(removable);
+-
+ static ssize_t ltm_capable_show(struct device *dev,
+ 				struct device_attribute *attr, char *buf)
+ {
+@@ -825,7 +805,6 @@ static struct attribute *dev_attrs[] = {
+ 	&dev_attr_avoid_reset_quirk.attr,
+ 	&dev_attr_authorized.attr,
+ 	&dev_attr_remove.attr,
+-	&dev_attr_removable.attr,
+ 	&dev_attr_ltm_capable.attr,
+ #ifdef CONFIG_OF
+ 	&dev_attr_devspec.attr,
+diff --git a/drivers/usb/core/urb.c b/drivers/usb/core/urb.c
+index 9c285026f..33d62d7e3 100644
+--- a/drivers/usb/core/urb.c
++++ b/drivers/usb/core/urb.c
+@@ -407,6 +407,15 @@ int usb_submit_urb(struct urb *urb, gfp_t mem_flags)
+ 			return -ENOEXEC;
+ 		is_out = !(setup->bRequestType & USB_DIR_IN) ||
+ 				!setup->wLength;
++		dev_WARN_ONCE(&dev->dev, (usb_pipeout(urb->pipe) != is_out),
++				"BOGUS control dir, pipe %x doesn't match bRequestType %x\n",
++				urb->pipe, setup->bRequestType);
++		if (le16_to_cpu(setup->wLength) != urb->transfer_buffer_length) {
++			dev_dbg(&dev->dev, "BOGUS control len %d doesn't match transfer length %d\n",
++					le16_to_cpu(setup->wLength),
++					urb->transfer_buffer_length);
++			return -EBADR;
++		}
+ 	} else {
+ 		is_out = usb_endpoint_dir_out(&ep->desc);
+ 	}
+diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c
+index db4de5367..b241d1bbf 100644
+--- a/drivers/usb/core/usb.c
++++ b/drivers/usb/core/usb.c
+@@ -982,17 +982,15 @@ static struct notifier_block usb_bus_nb = {
+ 	.notifier_call = usb_bus_notify,
+ };
+ 
+-static struct dentry *usb_devices_root;
+-
+ static void usb_debugfs_init(void)
+ {
+-	usb_devices_root = debugfs_create_file("devices", 0444, usb_debug_root,
+-					       NULL, &usbfs_devices_fops);
++	debugfs_create_file("devices", 0444, usb_debug_root, NULL,
++			    &usbfs_devices_fops);
+ }
+ 
+ static void usb_debugfs_cleanup(void)
+ {
+-	debugfs_remove(usb_devices_root);
++	debugfs_remove(debugfs_lookup("devices", usb_debug_root));
+ }
+ 
+ /*
+diff --git a/drivers/usb/dwc2/Kconfig b/drivers/usb/dwc2/Kconfig
+index c13171936..0376d8f4f 100644
+--- a/drivers/usb/dwc2/Kconfig
++++ b/drivers/usb/dwc2/Kconfig
+@@ -94,4 +94,24 @@ config USB_DWC2_DEBUG_PERIODIC
+ 	  non-periodic transfers, but of course the debug logs will be
+ 	  incomplete. Note that this also disables some debug messages
+ 	  for which the transfer type cannot be deduced.
++
++config USB_DWC2_FORCE_FULL_SPEED
++	bool "Force full speed mode"
++	help
++	  Say Y here to force full speed mode in the DWC2 Driver.
++
++config USB_DWC2_EXT_ID_PIN
++	bool "External Id Pin"
++	help
++	  Say Y here to enable external id pin in the DWC2 Driver.
++	  Example：
++	    echo "device" > /sys/class/usb_role/dwc2_new-role-switch/role
++	    echo "host" > /sys/class/usb_role/dwc2_new-role-switch/role
++	    echo "none" > /sys/class/usb_role/dwc2_new-role-switch/role
++
++config USB_DWC2_EXT_VBUS_DETECT
++	bool "External Vbus Detect"
++	help
++	  Say Y here to enable external vbus detect in the DWC2 Driver.
++
+ endif
+diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
+index 15911ac75..3d9259f8f 100644
+--- a/drivers/usb/dwc2/core.c
++++ b/drivers/usb/dwc2/core.c
+@@ -80,10 +80,8 @@ int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
+ 	gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
+ 	gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
+ 	gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
+-	gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
+ 	gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG);
+ 	gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL);
+-	gr->pcgcctl = dwc2_readl(hsotg, PCGCTL);
+ 
+ 	gr->valid = true;
+ 	return 0;
+@@ -119,9 +117,7 @@ int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
+ 	dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ);
+ 	dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ);
+ 	dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG);
+-	dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1);
+ 	dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG);
+-	dwc2_writel(hsotg, gr->pcgcctl, PCGCTL);
+ 	dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL);
+ 
+ 	return 0;
+@@ -131,54 +127,26 @@ int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
+  * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down.
+  *
+  * @hsotg: Programming view of the DWC_otg controller
++ * @rem_wakeup: indicates whether resume is initiated by Reset.
+  * @restore: Controller registers need to be restored
+  */
+-int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore)
++int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup,
++				 bool restore)
+ {
+-	u32 pcgcctl;
+-	int ret = 0;
+-
+-	if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL)
+-		return -ENOTSUPP;
+-
+-	pcgcctl = dwc2_readl(hsotg, PCGCTL);
+-	pcgcctl &= ~PCGCTL_STOPPCLK;
+-	dwc2_writel(hsotg, pcgcctl, PCGCTL);
+-
+-	pcgcctl = dwc2_readl(hsotg, PCGCTL);
+-	pcgcctl &= ~PCGCTL_PWRCLMP;
+-	dwc2_writel(hsotg, pcgcctl, PCGCTL);
+-
+-	pcgcctl = dwc2_readl(hsotg, PCGCTL);
+-	pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
+-	dwc2_writel(hsotg, pcgcctl, PCGCTL);
+-
+-	udelay(100);
+-	if (restore) {
+-		ret = dwc2_restore_global_registers(hsotg);
+-		if (ret) {
+-			dev_err(hsotg->dev, "%s: failed to restore registers\n",
+-				__func__);
+-			return ret;
+-		}
+-		if (dwc2_is_host_mode(hsotg)) {
+-			ret = dwc2_restore_host_registers(hsotg);
+-			if (ret) {
+-				dev_err(hsotg->dev, "%s: failed to restore host registers\n",
+-					__func__);
+-				return ret;
+-			}
+-		} else {
+-			ret = dwc2_restore_device_registers(hsotg, 0);
+-			if (ret) {
+-				dev_err(hsotg->dev, "%s: failed to restore device registers\n",
+-					__func__);
+-				return ret;
+-			}
+-		}
+-	}
++	struct dwc2_gregs_backup *gr;
++
++	gr = &hsotg->gr_backup;
+ 
+-	return ret;
++	/*
++	 * Restore host or device regisers with the same mode core enterted
++	 * to partial power down by checking "GOTGCTL_CURMODE_HOST" backup
++	 * value of the "gotgctl" register.
++	 */
++	if (gr->gotgctl & GOTGCTL_CURMODE_HOST)
++		return dwc2_host_exit_partial_power_down(hsotg, rem_wakeup,
++							 restore);
++	else
++		return dwc2_gadget_exit_partial_power_down(hsotg, restore);
+ }
+ 
+ /**
+@@ -188,57 +156,10 @@ int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore)
+  */
+ int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg)
+ {
+-	u32 pcgcctl;
+-	int ret = 0;
+-
+-	if (!hsotg->params.power_down)
+-		return -ENOTSUPP;
+-
+-	/* Backup all registers */
+-	ret = dwc2_backup_global_registers(hsotg);
+-	if (ret) {
+-		dev_err(hsotg->dev, "%s: failed to backup global registers\n",
+-			__func__);
+-		return ret;
+-	}
+-
+-	if (dwc2_is_host_mode(hsotg)) {
+-		ret = dwc2_backup_host_registers(hsotg);
+-		if (ret) {
+-			dev_err(hsotg->dev, "%s: failed to backup host registers\n",
+-				__func__);
+-			return ret;
+-		}
+-	} else {
+-		ret = dwc2_backup_device_registers(hsotg);
+-		if (ret) {
+-			dev_err(hsotg->dev, "%s: failed to backup device registers\n",
+-				__func__);
+-			return ret;
+-		}
+-	}
+-
+-	/*
+-	 * Clear any pending interrupts since dwc2 will not be able to
+-	 * clear them after entering partial_power_down.
+-	 */
+-	dwc2_writel(hsotg, 0xffffffff, GINTSTS);
+-
+-	/* Put the controller in low power state */
+-	pcgcctl = dwc2_readl(hsotg, PCGCTL);
+-
+-	pcgcctl |= PCGCTL_PWRCLMP;
+-	dwc2_writel(hsotg, pcgcctl, PCGCTL);
+-	ndelay(20);
+-
+-	pcgcctl |= PCGCTL_RSTPDWNMODULE;
+-	dwc2_writel(hsotg, pcgcctl, PCGCTL);
+-	ndelay(20);
+-
+-	pcgcctl |= PCGCTL_STOPPCLK;
+-	dwc2_writel(hsotg, pcgcctl, PCGCTL);
+-
+-	return ret;
++	if (dwc2_is_host_mode(hsotg))
++		return dwc2_host_enter_partial_power_down(hsotg);
++	else
++		return dwc2_gadget_enter_partial_power_down(hsotg);
+ }
+ 
+ /**
+@@ -251,7 +172,6 @@ int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg)
+ static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode,
+ 					int is_host)
+ {
+-	u32 pcgcctl;
+ 	struct dwc2_gregs_backup *gr;
+ 	struct dwc2_dregs_backup *dr;
+ 	struct dwc2_hregs_backup *hr;
+@@ -262,18 +182,6 @@ static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode,
+ 
+ 	dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__);
+ 
+-	/* Load restore values for [31:14] bits */
+-	pcgcctl = (gr->pcgcctl & 0xffffc000);
+-	/* If High Speed */
+-	if (is_host) {
+-		if (!(pcgcctl & PCGCTL_P2HD_PRT_SPD_MASK))
+-			pcgcctl |= BIT(17);
+-	} else {
+-		if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK))
+-			pcgcctl |= BIT(17);
+-	}
+-	dwc2_writel(hsotg, pcgcctl, PCGCTL);
+-
+ 	/* Umnask global Interrupt in GAHBCFG and restore it */
+ 	dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG);
+ 
+@@ -288,23 +196,9 @@ static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode,
+ 
+ 	if (is_host) {
+ 		dwc2_writel(hsotg, hr->hcfg, HCFG);
+-		if (rmode)
+-			pcgcctl |= PCGCTL_RESTOREMODE;
+-		dwc2_writel(hsotg, pcgcctl, PCGCTL);
+-		udelay(10);
+-
+-		pcgcctl |= PCGCTL_ESS_REG_RESTORED;
+-		dwc2_writel(hsotg, pcgcctl, PCGCTL);
+ 		udelay(10);
+ 	} else {
+ 		dwc2_writel(hsotg, dr->dcfg, DCFG);
+-		if (!rmode)
+-			pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE;
+-		dwc2_writel(hsotg, pcgcctl, PCGCTL);
+-		udelay(10);
+-
+-		pcgcctl |= PCGCTL_ESS_REG_RESTORED;
+-		dwc2_writel(hsotg, pcgcctl, PCGCTL);
+ 		udelay(10);
+ 	}
+ }
+@@ -370,11 +264,16 @@ void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
+ 	if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_RESTOREDONE,
+ 				    20000)) {
+ 		dev_dbg(hsotg->dev,
+-			"%s: Restore Done wan't generated here\n",
++			"%s: Restore Done wasn't generated here\n",
+ 			__func__);
+ 	} else {
+ 		dev_dbg(hsotg->dev, "restore done  generated here\n");
+-	}
++
++		/*
++		 * To avoid restore done interrupt storm after restore is
++		 * generated clear GINTSTS_RESTOREDONE bit.
++		 */
++		dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTSTS);	}
+ }
+ 
+ /**
+@@ -387,7 +286,7 @@ static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
+ {
+ 	ktime_t start;
+ 	ktime_t end;
+-	unsigned int timeout = 110;
++	unsigned int timeout = 5000;
+ 
+ 	dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
+ 		 host_mode ? "host" : "device");
+@@ -460,9 +359,6 @@ static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
+  */
+ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host)
+ {
+-	if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_HIBERNATION)
+-		return -ENOTSUPP;
+-
+ 	if (is_host)
+ 		return dwc2_host_enter_hibernation(hsotg);
+ 	else
+@@ -527,14 +423,14 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
+ 	if ((hsotg->hw_params.snpsid & DWC2_CORE_REV_MASK) <
+ 		(DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
+ 		if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL,
+-					      GRSTCTL_CSFTRST, 10000)) {
++					      GRSTCTL_CSFTRST, 100000)) {
+ 			dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST\n",
+ 				 __func__);
+ 			return -EBUSY;
+ 		}
+ 	} else {
+ 		if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
+-					    GRSTCTL_CSFTRST_DONE, 10000)) {
++					    GRSTCTL_CSFTRST_DONE, 100000)) {
+ 			dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST_DONE\n",
+ 				 __func__);
+ 			return -EBUSY;
+@@ -545,6 +441,22 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
+ 		dwc2_writel(hsotg, greset, GRSTCTL);
+ 	}
+ 
++	/*
++	 * Switching from device mode to host mode by disconnecting
++	 * device cable core enters and exits form hibernation.
++	 * However, the fifo map remains not cleared. It results
++	 * to a WARNING (WARNING: CPU: 5 PID: 0 at drivers/usb/dwc2/
++	 * gadget.c:307 dwc2_hsotg_init_fifo+0x12/0x152 [dwc2])
++	 * if in host mode we disconnect the micro a to b host
++	 * cable. Because core reset occurs.
++	 * To avoid the WARNING, fifo_map should be cleared
++	 * in dwc2_core_reset() function by taking into account configs.
++	 * fifo_map must be cleared only if driver is configured in
++	 * "CONFIG_USB_DWC2_PERIPHERAL" or "CONFIG_USB_DWC2_DUAL_ROLE"
++	 * mode.
++	 */
++	dwc2_clear_fifo_map(hsotg);
++
+ 	/* Wait for AHB master IDLE state */
+ 	if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) {
+ 		dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n",
+@@ -682,16 +594,7 @@ void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
+ /*
+  * dwc2_enable_acg - enable active clock gating feature
+  */
+-void dwc2_enable_acg(struct dwc2_hsotg *hsotg)
+-{
+-	if (hsotg->params.acg_enable) {
+-		u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
+-
+-		dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");
+-		pcgcctl1 |= PCGCCTL1_GATEEN;
+-		dwc2_writel(hsotg, pcgcctl1, PCGCCTL1);
+-	}
+-}
++void dwc2_enable_acg(struct dwc2_hsotg *hsotg) { }
+ 
+ /**
+  * dwc2_dump_host_registers() - Prints the host registers
+@@ -819,9 +722,6 @@ void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
+ 	addr = hsotg->regs + GPVNDCTL;
+ 	dev_dbg(hsotg->dev, "GPVNDCTL	 @0x%08lX : 0x%08X\n",
+ 		(unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL));
+-	addr = hsotg->regs + GGPIO;
+-	dev_dbg(hsotg->dev, "GGPIO	 @0x%08lX : 0x%08X\n",
+-		(unsigned long)addr, dwc2_readl(hsotg, GGPIO));
+ 	addr = hsotg->regs + GUID;
+ 	dev_dbg(hsotg->dev, "GUID	 @0x%08lX : 0x%08X\n",
+ 		(unsigned long)addr, dwc2_readl(hsotg, GUID));
+@@ -852,10 +752,6 @@ void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
+ 	addr = hsotg->regs + HPTXFSIZ;
+ 	dev_dbg(hsotg->dev, "HPTXFSIZ	 @0x%08lX : 0x%08X\n",
+ 		(unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ));
+-
+-	addr = hsotg->regs + PCGCTL;
+-	dev_dbg(hsotg->dev, "PCGCTL	 @0x%08lX : 0x%08X\n",
+-		(unsigned long)addr, dwc2_readl(hsotg, PCGCTL));
+ #endif
+ }
+ 
+@@ -1063,7 +959,7 @@ void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
+ 
+ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
+ {
+-	u32 usbcfg, ggpio, i2cctl;
++	u32 usbcfg, i2cctl;
+ 	int retval = 0;
+ 
+ 	/*
+@@ -1087,19 +983,6 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
+ 				return retval;
+ 			}
+ 		}
+-
+-		if (hsotg->params.activate_stm_fs_transceiver) {
+-			ggpio = dwc2_readl(hsotg, GGPIO);
+-			if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
+-				dev_dbg(hsotg->dev, "Activating transceiver\n");
+-				/*
+-				 * STM32F4x9 uses the GGPIO register as general
+-				 * core configuration register.
+-				 */
+-				ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
+-				dwc2_writel(hsotg, ggpio, GGPIO);
+-			}
+-		}
+ 	}
+ 
+ 	/*
+@@ -1206,6 +1089,7 @@ static void dwc2_set_turnaround_time(struct dwc2_hsotg *hsotg)
+ 	dwc2_writel(hsotg, usbcfg, GUSBCFG);
+ }
+ 
++
+ int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
+ {
+ 	u32 usbcfg;
+diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
+index 03d16a082..598817d99 100644
+--- a/drivers/usb/dwc2/core.h
++++ b/drivers/usb/dwc2/core.h
+@@ -121,6 +121,7 @@ struct dwc2_hsotg_req;
+  * @periodic: Set if this is a periodic ep, such as Interrupt
+  * @isochronous: Set if this is a isochronous ep
+  * @send_zlp: Set if we need to send a zero-length packet.
++ * @wedged: Set if ep is wedged.
+  * @desc_list_dma: The DMA address of descriptor chain currently in use.
+  * @desc_list: Pointer to descriptor DMA chain head currently in use.
+  * @desc_count: Count of entries within the DMA descriptor chain of EP.
+@@ -171,6 +172,7 @@ struct dwc2_hsotg_ep {
+ 	unsigned int            periodic:1;
+ 	unsigned int            isochronous:1;
+ 	unsigned int            send_zlp:1;
++	unsigned int            wedged:1;
+ 	unsigned int            target_frame;
+ #define TARGET_FRAME_INITIAL   0xFFFFFFFF
+ 	bool			frame_overrun;
+@@ -208,8 +210,21 @@ do { \
+ 		spin_lock(&_hs->lock); \
+ 	} \
+ } while (0)
++
++#define call_gadget_set_state(_hs, _state) \
++	usb_gadget_set_state(&_hs->gadget, _state)
++
++#define set_gadget_resume_state(_hs)	_hs->resume_state = _hs->gadget.state
++#define get_gadget_resume_state(_hs)	_hs->resume_state
++#define get_gadget_enabled(_hs)		_hs->enabled
+ #else
++
+ #define call_gadget(_hs, _entry)	do {} while (0)
++#define call_gadget_set_state(_hs, _state)	do {} while (0)
++
++#define set_gadget_resume_state(_hs)	do {} while (0)
++#define get_gadget_resume_state(_hs)	0
++#define get_gadget_enabled(_hs)		0
+ #endif
+ 
+ struct dwc2_hsotg;
+@@ -235,11 +250,14 @@ enum dwc2_ep0_state {
+ /**
+  * struct dwc2_core_params - Parameters for configuring the core
+  *
+- * @otg_cap:            Specifies the OTG capabilities.
+- *                       0 - HNP and SRP capable
+- *                       1 - SRP Only capable
+- *                       2 - No HNP/SRP capable (always available)
+- *                      Defaults to best available option (0, 1, then 2)
++ * @otg_caps:           Specifies the OTG capabilities. OTG caps from the platform parameters,
++ *                      used to setup the:
++ *                       - HNP and SRP capable
++ *                       - SRP Only capable
++ *                       - No HNP/SRP capable (always available)
++ *                       Defaults to best available option
++ *                       - OTG revision number the device is compliant with, in binary-coded
++ *                         decimal (i.e. 2.0 is 0200H). (see struct usb_otg_caps)
+  * @host_dma:           Specifies whether to use slave or DMA mode for accessing
+  *                      the data FIFOs. The driver will automatically detect the
+  *                      value for this parameter if none is specified.
+@@ -375,6 +393,9 @@ enum dwc2_ep0_state {
+  *                      case.
+  *                      0 - No (default)
+  *                      1 - Yes
++ * @external_vbus_detect: Specifies whether VBUS detect is handled externally.
++ *                      0 - No (default)
++ *                      1 - Yes
+  * @power_down:         Specifies whether the controller support power_down.
+  *			If power_down is enabled, the controller will enter
+  *			power_down in both peripheral and host mode when
+@@ -409,14 +430,6 @@ enum dwc2_ep0_state {
+  *                      device had been in L1 state until that period.
+  *                      This is used by SW to initiate Remote WakeUp in the
+  *                      controller so as to sync to the uF number from the host.
+- * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
+- *			register.
+- *			0 - Deactivate the transceiver (default)
+- *			1 - Activate the transceiver
+- * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level
+- *			detection using GGPIO register.
+- *			0 - Deactivate the external level detection (default)
+- *			1 - Activate the external level detection
+  * @g_dma:              Enables gadget dma usage (default: autodetect).
+  * @g_dma_desc:         Enables gadget descriptor DMA (default: autodetect).
+  * @g_rx_fifo_size:	The periodic rx fifo size for the device, in
+@@ -428,7 +441,7 @@ enum dwc2_ep0_state {
+  * @g_tx_fifo_size:	An array of TX fifo sizes in dedicated fifo
+  *			mode. Each value corresponds to one EP
+  *			starting from EP1 (max 15 values). Sizes are
+- *			in DWORDS with possible values from from
++ *			in DWORDS with possible values from
+  *			16-32768 (default: 256, 256, 256, 256, 768,
+  *			768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
+  * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL
+@@ -447,10 +460,7 @@ enum dwc2_ep0_state {
+  * default described above.
+  */
+ struct dwc2_core_params {
+-	u8 otg_cap;
+-#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE		0
+-#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE		1
+-#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE	2
++	struct usb_otg_caps otg_caps;
+ 
+ 	u8 phy_type;
+ #define DWC2_PHY_TYPE_PARAM_FS		0
+@@ -474,6 +484,7 @@ struct dwc2_core_params {
+ 	bool reload_ctl;
+ 	bool uframe_sched;
+ 	bool external_id_pin_ctl;
++	bool external_vbus_detect;
+ 
+ 	int power_down;
+ #define DWC2_POWER_DOWN_PARAM_NONE		0
+@@ -486,8 +497,6 @@ struct dwc2_core_params {
+ 	bool hird_threshold_en;
+ 	bool service_interval;
+ 	u8 hird_threshold;
+-	bool activate_stm_fs_transceiver;
+-	bool activate_stm_id_vb_detection;
+ 	bool ipg_isoc_en;
+ 	u16 max_packet_count;
+ 	u32 max_transfer_size;
+@@ -690,7 +699,6 @@ struct dwc2_hw_params {
+  * @glpmcfg:		Backup of GLPMCFG register
+  * @gdfifocfg:		Backup of GDFIFOCFG register
+  * @pcgcctl:		Backup of PCGCCTL register
+- * @pcgcctl1:		Backup of PCGCCTL1 register
+  * @dtxfsiz:		Backup of DTXFSIZ registers for each endpoint
+  * @gpwrdn:		Backup of GPWRDN register
+  * @valid:		True if registers values backuped.
+@@ -704,8 +712,6 @@ struct dwc2_gregs_backup {
+ 	u32 gnptxfsiz;
+ 	u32 gi2cctl;
+ 	u32 glpmcfg;
+-	u32 pcgcctl;
+-	u32 pcgcctl1;
+ 	u32 gdfifocfg;
+ 	u32 gpwrdn;
+ 	bool valid;
+@@ -867,6 +873,8 @@ struct dwc2_hregs_backup {
+  * @gadget_enabled:	Peripheral mode sub-driver initialization indicator.
+  * @ll_hw_enabled:	Status of low-level hardware resources.
+  * @hibernated:		True if core is hibernated
++ * @in_ppd:		True if core is partial power down mode.
++ * @bus_suspended:	True if bus is suspended
+  * @reset_phy_on_wake:	Quirk saying that we should assert PHY reset on a
+  *			remote wakeup.
+  * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend.
+@@ -1024,7 +1032,6 @@ struct dwc2_hregs_backup {
+  *			a pointer to an array of register definitions, the
+  *			array size and the base address where the register bank
+  *			is to be found.
+- * @bus_suspended:	True if bus is suspended
+  * @last_frame_num:	Number of last frame. Range from 0 to  32768
+  * @frame_num_array:    Used only  if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
+  *			defined, for missed SOFs tracking. Array holds that
+@@ -1062,9 +1069,12 @@ struct dwc2_hsotg {
+ 	unsigned int gadget_enabled:1;
+ 	unsigned int ll_hw_enabled:1;
+ 	unsigned int hibernated:1;
++	unsigned int in_ppd:1;
++	bool bus_suspended;
+ 	unsigned int reset_phy_on_wake:1;
+ 	unsigned int need_phy_for_wake:1;
+ 	unsigned int phy_off_for_suspend:1;
++	unsigned int vbus_supply_enabled:1;
+ 	u16 frame_number;
+ 
+ 	struct phy *phy;
+@@ -1072,7 +1082,6 @@ struct dwc2_hsotg {
+ 	struct dwc2_hsotg_plat *plat;
+ 	struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];
+ 	struct regulator *vbus_supply;
+-	struct regulator *usb33d;
+ 
+ 	spinlock_t lock;
+ 	void *priv;
+@@ -1145,7 +1154,6 @@ struct dwc2_hsotg {
+ 	unsigned long hs_periodic_bitmap[
+ 		DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
+ 	u16 periodic_qh_count;
+-	bool bus_suspended;
+ 	bool new_connection;
+ 
+ 	u16 last_frame_num;
+@@ -1206,6 +1214,7 @@ struct dwc2_hsotg {
+ 	struct dwc2_dma_desc *ctrl_out_desc;
+ 
+ 	struct usb_gadget gadget;
++	enum usb_device_state resume_state;
+ 	unsigned int enabled:1;
+ 	unsigned int connected:1;
+ 	unsigned int remote_wakeup_allowed:1;
+@@ -1303,7 +1312,8 @@ static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
+  */
+ int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait);
+ int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg);
+-int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore);
++int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup,
++				 bool restore);
+ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host);
+ int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
+ 		int reset, int is_host);
+@@ -1381,8 +1391,6 @@ static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
+ }
+ 
+ int dwc2_drd_init(struct dwc2_hsotg *hsotg);
+-void dwc2_drd_suspend(struct dwc2_hsotg *hsotg);
+-void dwc2_drd_resume(struct dwc2_hsotg *hsotg);
+ void dwc2_drd_exit(struct dwc2_hsotg *hsotg);
+ 
+ /*
+@@ -1412,11 +1420,19 @@ int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup);
+ int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg);
+ int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
+ 				 int rem_wakeup, int reset);
++int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg);
++int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
++					bool restore);
++void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg);
++void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg,
++				   int rem_wakeup);
+ int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg);
+ int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg);
+ int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg);
+ void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg);
+ void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg);
++static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg)
++{ hsotg->fifo_map = 0; }
+ #else
+ static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
+ { return 0; }
+@@ -1446,6 +1462,14 @@ static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
+ static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
+ 					       int rem_wakeup, int reset)
+ { return 0; }
++static inline int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
++{ return 0; }
++static inline int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
++						      bool restore)
++{ return 0; }
++static inline void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) {}
++static inline void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg,
++						 int rem_wakeup) {}
+ static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
+ { return 0; }
+ static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
+@@ -1454,6 +1478,7 @@ static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
+ { return 0; }
+ static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {}
+ static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {}
++static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) {}
+ #endif
+ 
+ #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
+@@ -1463,11 +1488,18 @@ void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
+ void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
+ void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
+ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup);
++int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex);
++int dwc2_port_resume(struct dwc2_hsotg *hsotg);
+ int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
+ int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
+ int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg);
+ int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
+ 			       int rem_wakeup, int reset);
++int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg);
++int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg,
++				      int rem_wakeup, bool restore);
++void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg);
++void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup);
+ bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2);
+ static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg)
+ { schedule_work(&hsotg->phy_reset_work); }
+@@ -1483,6 +1515,10 @@ static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
+ static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
+ static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
+ { return 0; }
++static inline int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
++{ return 0; }
++static inline int dwc2_port_resume(struct dwc2_hsotg *hsotg)
++{ return 0; }
+ static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
+ { return 0; }
+ static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
+@@ -1494,6 +1530,14 @@ static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
+ static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
+ 					     int rem_wakeup, int reset)
+ { return 0; }
++static inline int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg)
++{ return 0; }
++static inline int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg,
++						    int rem_wakeup, bool restore)
++{ return 0; }
++static inline void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg) {}
++static inline void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg,
++					       int rem_wakeup) {}
+ static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
+ { return false; }
+ static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {}
+diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
+index e3f429f15..b1a4a1a0a 100644
+--- a/drivers/usb/dwc2/core_intr.c
++++ b/drivers/usb/dwc2/core_intr.c
+@@ -317,10 +317,17 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
+ 
+ 	if (dwc2_is_device_mode(hsotg)) {
+ 		if (hsotg->lx_state == DWC2_L2) {
+-			ret = dwc2_exit_partial_power_down(hsotg, true);
+-			if (ret && (ret != -ENOTSUPP))
+-				dev_err(hsotg->dev,
+-					"exit power_down failed\n");
++			if (hsotg->in_ppd) {
++				ret = dwc2_exit_partial_power_down(hsotg, 0, true);
++				if (ret)
++					dev_err(hsotg->dev,
++						"exit power_down failed\n");
++			}
++
++			/* Exit gadget mode clock gating. */
++			if (hsotg->params.power_down ==
++			    DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended)
++				dwc2_gadget_exit_clock_gating(hsotg, 0);
+ 		}
+ 
+ 		/*
+@@ -387,6 +394,7 @@ static void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg)
+ 
+ 	/* Inform gadget to exit from L1 */
+ 	call_gadget(hsotg, resume);
++	call_gadget_set_state(hsotg, get_gadget_resume_state(hsotg));
+ }
+ 
+ /*
+@@ -415,32 +423,39 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
+ 		dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
+ 			dwc2_readl(hsotg, DSTS));
+ 		if (hsotg->lx_state == DWC2_L2) {
+-			u32 dctl = dwc2_readl(hsotg, DCTL);
+-
+-			/* Clear Remote Wakeup Signaling */
+-			dctl &= ~DCTL_RMTWKUPSIG;
+-			dwc2_writel(hsotg, dctl, DCTL);
+-			ret = dwc2_exit_partial_power_down(hsotg, true);
+-			if (ret && (ret != -ENOTSUPP))
+-				dev_err(hsotg->dev, "exit power_down failed\n");
++			if (hsotg->in_ppd) {
++				u32 dctl = dwc2_readl(hsotg, DCTL);
++				/* Clear Remote Wakeup Signaling */
++				dctl &= ~DCTL_RMTWKUPSIG;
++				dwc2_writel(hsotg, dctl, DCTL);
++				ret = dwc2_exit_partial_power_down(hsotg, 1, true);
++				if (ret)
++					dev_err(hsotg->dev,
++						"exit partial_power_down failed\n");
++				call_gadget(hsotg, resume);
++				call_gadget_set_state(hsotg, get_gadget_resume_state(hsotg));
++			}
+ 
+-			/* Change to L0 state */
+-			hsotg->lx_state = DWC2_L0;
+-			call_gadget(hsotg, resume);
++			/* Exit gadget mode clock gating. */
++			if (hsotg->params.power_down ==
++			    DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended)
++				dwc2_gadget_exit_clock_gating(hsotg, 0);
+ 		} else {
+ 			/* Change to L0 state */
+ 			hsotg->lx_state = DWC2_L0;
+ 		}
+ 	} else {
+-		if (hsotg->params.power_down)
+-			return;
+-
+-		if (hsotg->lx_state != DWC2_L1) {
+-			u32 pcgcctl = dwc2_readl(hsotg, PCGCTL);
++		if (hsotg->lx_state == DWC2_L2) {
++			if (hsotg->in_ppd) {
++				ret = dwc2_exit_partial_power_down(hsotg, 1, true);
++				if (ret)
++					dev_err(hsotg->dev,
++						"exit partial_power_down failed\n");
++			}
+ 
+-			/* Restart the Phy Clock */
+-			pcgcctl &= ~PCGCTL_STOPPCLK;
+-			dwc2_writel(hsotg, pcgcctl, PCGCTL);
++			if (hsotg->params.power_down ==
++			    DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended)
++				dwc2_host_exit_clock_gating(hsotg, 1);
+ 
+ 			/*
+ 			 * If we've got this quirk then the PHY is stuck upon
+@@ -516,31 +531,32 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
+ 			return;
+ 		}
+ 		if (dsts & DSTS_SUSPSTS) {
+-			if (hsotg->hw_params.power_optimized) {
++			switch (hsotg->params.power_down) {
++			case DWC2_POWER_DOWN_PARAM_PARTIAL:
+ 				ret = dwc2_enter_partial_power_down(hsotg);
+-				if (ret) {
+-					if (ret != -ENOTSUPP)
+-						dev_err(hsotg->dev,
+-							"%s: enter partial_power_down failed\n",
+-							__func__);
+-					goto skip_power_saving;
+-				}
++				if (ret)
++					dev_err(hsotg->dev,
++						"enter partial_power_down failed\n");
+ 
+ 				udelay(100);
+ 
+ 				/* Ask phy to be suspended */
+-				if (!IS_ERR_OR_NULL(hsotg->uphy))
+-					usb_phy_set_suspend(hsotg->uphy, true);
+-			}
+-
+-			if (hsotg->hw_params.hibernation) {
++				usb_phy_set_suspend(hsotg->uphy, true);
++				break;
++			case DWC2_POWER_DOWN_PARAM_HIBERNATION:
+ 				ret = dwc2_enter_hibernation(hsotg, 0);
+-				if (ret && ret != -ENOTSUPP)
++				if (ret)
+ 					dev_err(hsotg->dev,
+-						"%s: enter hibernation failed\n",
+-						__func__);
++						"enter hibernation failed\n");
++				break;
++			case DWC2_POWER_DOWN_PARAM_NONE:
++				/*
++				 * If neither hibernation nor partial power down are supported,
++				 * clock gating is used to save power.
++				 */
++				dwc2_gadget_enter_clock_gating(hsotg);
+ 			}
+-skip_power_saving:
++
+ 			/*
+ 			 * Change to L2 (suspend) state before releasing
+ 			 * spinlock
+@@ -549,6 +565,8 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
+ 
+ 			/* Call gadget suspend callback */
+ 			call_gadget(hsotg, suspend);
++			set_gadget_resume_state(hsotg);
++			call_gadget_set_state(hsotg, USB_STATE_SUSPENDED);
+ 		}
+ 	} else {
+ 		if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
+@@ -565,6 +583,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
+ 	}
+ }
+ 
++
+ /**
+  * dwc2_handle_lpm_intr - GINTSTS_LPMTRANRCVD Interrupt handler
+  *
+@@ -574,7 +593,6 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
+ static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg)
+ {
+ 	u32 glpmcfg;
+-	u32 pcgcctl;
+ 	u32 hird;
+ 	u32 hird_thres;
+ 	u32 hird_thres_en;
+@@ -605,10 +623,6 @@ static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg)
+ 			dev_dbg(hsotg->dev, "L1 with utmi_sleep_n\n");
+ 		} else {
+ 			dev_dbg(hsotg->dev, "Entering Sleep with L1 Gating\n");
+-
+-			pcgcctl = dwc2_readl(hsotg, PCGCTL);
+-			pcgcctl |= PCGCTL_ENBL_SLEEP_GATING;
+-			dwc2_writel(hsotg, pcgcctl, PCGCTL);
+ 		}
+ 		/**
+ 		 * Examine prt_sleep_sts after TL1TokenTetry period max (10 us)
+@@ -625,6 +639,8 @@ static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg)
+ 
+ 			/* Inform gadget that we are in L1 state */
+ 			call_gadget(hsotg, suspend);
++			set_gadget_resume_state(hsotg);
++			call_gadget_set_state(hsotg, USB_STATE_SUSPENDED);
+ 		}
+ 	}
+ }
+@@ -707,11 +723,7 @@ static inline void dwc_handle_gpwrdn_disc_det(struct dwc2_hsotg *hsotg,
+ 	dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
+ 
+ 	hsotg->hibernated = 0;
+-
+-#if IS_ENABLED(CONFIG_USB_DWC2_HOST) ||	\
+-	IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
+ 	hsotg->bus_suspended = 0;
+-#endif
+ 
+ 	if (gpwrdn & GPWRDN_IDSTS) {
+ 		hsotg->op_state = OTG_STATE_B_PERIPHERAL;
+@@ -735,10 +747,11 @@ static inline void dwc_handle_gpwrdn_disc_det(struct dwc2_hsotg *hsotg,
+  * The GPWRDN interrupts are those that occur in both Host and
+  * Device mode while core is in hibernated state.
+  */
+-static void dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
++static int dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
+ {
+ 	u32 gpwrdn;
+ 	int linestate;
++	int ret = 0;
+ 
+ 	gpwrdn = dwc2_readl(hsotg, GPWRDN);
+ 	/* clear all interrupt */
+@@ -762,17 +775,28 @@ static void dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
+ 		if (hsotg->hw_params.hibernation &&
+ 		    hsotg->hibernated) {
+ 			if (gpwrdn & GPWRDN_IDSTS) {
+-				dwc2_exit_hibernation(hsotg, 0, 0, 0);
++				ret = dwc2_exit_hibernation(hsotg, 0, 0, 0);
++				if (ret)
++					dev_err(hsotg->dev,
++						"exit hibernation failed.\n");
+ 				call_gadget(hsotg, resume);
++				call_gadget_set_state(hsotg, get_gadget_resume_state(hsotg));
+ 			} else {
+-				dwc2_exit_hibernation(hsotg, 1, 0, 1);
++				ret = dwc2_exit_hibernation(hsotg, 1, 0, 1);
++				if (ret)
++					dev_err(hsotg->dev,
++						"exit hibernation failed.\n");
+ 			}
+ 		}
+ 	} else if ((gpwrdn & GPWRDN_RST_DET) &&
+ 		   (gpwrdn & GPWRDN_RST_DET_MSK)) {
+ 		dev_dbg(hsotg->dev, "%s: GPWRDN_RST_DET\n", __func__);
+-		if (!linestate && (gpwrdn & GPWRDN_BSESSVLD))
+-			dwc2_exit_hibernation(hsotg, 0, 1, 0);
++		if (!linestate) {
++			ret = dwc2_exit_hibernation(hsotg, 0, 1, 0);
++			if (ret)
++				dev_err(hsotg->dev,
++					"exit hibernation failed.\n");
++		}
+ 	} else if ((gpwrdn & GPWRDN_STS_CHGINT) &&
+ 		   (gpwrdn & GPWRDN_STS_CHGINT_MSK)) {
+ 		dev_dbg(hsotg->dev, "%s: GPWRDN_STS_CHGINT\n", __func__);
+@@ -784,6 +808,8 @@ static void dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
+ 		 */
+ 		dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn);
+ 	}
++
++	return ret;
+ }
+ 
+ /*
+@@ -841,7 +867,7 @@ irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
+ 		dwc2_handle_disconnect_intr(hsotg);
+ 	if (gintsts & GINTSTS_SESSREQINT)
+ 		dwc2_handle_session_req_intr(hsotg);
+-	if (gintsts & GINTSTS_WKUPINT)
++	if (usb_phy_get_wakeup(hsotg->uphy) || (gintsts & GINTSTS_WKUPINT))
+ 		dwc2_handle_wakeup_detected_intr(hsotg);
+ 	if (gintsts & GINTSTS_USBSUSP)
+ 		dwc2_handle_usb_suspend_intr(hsotg);
+diff --git a/drivers/usb/dwc2/debugfs.c b/drivers/usb/dwc2/debugfs.c
+index aaafd463d..0455491b8 100644
+--- a/drivers/usb/dwc2/debugfs.c
++++ b/drivers/usb/dwc2/debugfs.c
+@@ -535,7 +535,6 @@ static const struct debugfs_reg32 dwc2_regs[] = {
+ 	dump_register(DTXFSTS(13)),
+ 	dump_register(DTXFSTS(14)),
+ 	dump_register(DTXFSTS(15)),
+-	dump_register(PCGCTL),
+ 	dump_register(HCFG),
+ 	dump_register(HFIR),
+ 	dump_register(HFNUM),
+@@ -670,7 +669,9 @@ static int params_show(struct seq_file *seq, void *v)
+ 	struct dwc2_core_params *p = &hsotg->params;
+ 	int i;
+ 
+-	print_param(seq, p, otg_cap);
++	print_param(seq, p, otg_caps.hnp_support);
++	print_param(seq, p, otg_caps.srp_support);
++	print_param(seq, p, otg_caps.otg_rev);
+ 	print_param(seq, p, dma_desc_enable);
+ 	print_param(seq, p, dma_desc_fs_enable);
+ 	print_param(seq, p, speed);
+diff --git a/drivers/usb/dwc2/drd.c b/drivers/usb/dwc2/drd.c
+index 36f2c3841..a5d23f1d1 100644
+--- a/drivers/usb/dwc2/drd.c
++++ b/drivers/usb/dwc2/drd.c
+@@ -13,6 +13,22 @@
+ #include <linux/usb/role.h>
+ #include "core.h"
+ 
++static void dwc2_vbus_valid(struct dwc2_hsotg *hsotg)
++{
++	unsigned long flags;
++	u32 gotgctl;
++
++	spin_lock_irqsave(&hsotg->lock, flags);
++
++	gotgctl = dwc2_readl(hsotg, GOTGCTL);
++	gotgctl |= GOTGCTL_VBVALOEN | GOTGCTL_VBVALOVAL;
++	gotgctl |= GOTGCTL_AVALOEN | GOTGCTL_AVALOVAL;
++	gotgctl |= GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL;
++	dwc2_writel(hsotg, gotgctl, GOTGCTL);
++
++	spin_unlock_irqrestore(&hsotg->lock, flags);
++}
++
+ static void dwc2_ovr_init(struct dwc2_hsotg *hsotg)
+ {
+ 	unsigned long flags;
+@@ -35,11 +51,6 @@ static int dwc2_ovr_avalid(struct dwc2_hsotg *hsotg, bool valid)
+ {
+ 	u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
+ 
+-	/* Check if A-Session is already in the right state */
+-	if ((valid && (gotgctl & GOTGCTL_ASESVLD)) ||
+-	    (!valid && !(gotgctl & GOTGCTL_ASESVLD)))
+-		return -EALREADY;
+-
+ 	gotgctl &= ~GOTGCTL_BVALOVAL;
+ 	if (valid)
+ 		gotgctl |= GOTGCTL_AVALOVAL | GOTGCTL_VBVALOVAL;
+@@ -54,11 +65,6 @@ static int dwc2_ovr_bvalid(struct dwc2_hsotg *hsotg, bool valid)
+ {
+ 	u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
+ 
+-	/* Check if B-Session is already in the right state */
+-	if ((valid && (gotgctl & GOTGCTL_BSESVLD)) ||
+-	    (!valid && !(gotgctl & GOTGCTL_BSESVLD)))
+-		return -EALREADY;
+-
+ 	gotgctl &= ~GOTGCTL_AVALOVAL;
+ 	if (valid)
+ 		gotgctl |= GOTGCTL_BVALOVAL | GOTGCTL_VBVALOVAL;
+@@ -73,22 +79,12 @@ static int dwc2_drd_role_sw_set(struct usb_role_switch *sw, enum usb_role role)
+ {
+ 	struct dwc2_hsotg *hsotg = usb_role_switch_get_drvdata(sw);
+ 	unsigned long flags;
+-	int already = 0;
+ 
+ 	/* Skip session not in line with dr_mode */
+ 	if ((role == USB_ROLE_DEVICE && hsotg->dr_mode == USB_DR_MODE_HOST) ||
+ 	    (role == USB_ROLE_HOST && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
+ 		return -EINVAL;
+ 
+-#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
+-	IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
+-	/* Skip session if core is in test mode */
+-	if (role == USB_ROLE_NONE && hsotg->test_mode) {
+-		dev_dbg(hsotg->dev, "Core is in test mode\n");
+-		return -EBUSY;
+-	}
+-#endif
+-
+ 	/*
+ 	 * In case of USB_DR_MODE_PERIPHERAL, clock is disabled at the end of
+ 	 * the probe and enabled on udc_start.
+@@ -106,18 +102,18 @@ static int dwc2_drd_role_sw_set(struct usb_role_switch *sw, enum usb_role role)
+ 	spin_lock_irqsave(&hsotg->lock, flags);
+ 
+ 	if (role == USB_ROLE_HOST) {
+-		already = dwc2_ovr_avalid(hsotg, true);
++		dwc2_ovr_avalid(hsotg, true);
+ 	} else if (role == USB_ROLE_DEVICE) {
+-		already = dwc2_ovr_bvalid(hsotg, true);
++		dwc2_ovr_bvalid(hsotg, true);
+ 		if (dwc2_is_device_enabled(hsotg)) {
+ 			/* This clear DCTL.SFTDISCON bit */
+ 			dwc2_hsotg_core_connect(hsotg);
+ 		}
+ 	} else {
+ 		if (dwc2_is_device_mode(hsotg)) {
+-			if (!dwc2_ovr_bvalid(hsotg, false))
+-				/* This set DCTL.SFTDISCON bit */
+-				dwc2_hsotg_core_disconnect(hsotg);
++			dwc2_ovr_bvalid(hsotg, false);
++			/* This set DCTL.SFTDISCON bit */
++			dwc2_hsotg_core_disconnect(hsotg);
+ 		} else {
+ 			dwc2_ovr_avalid(hsotg, false);
+ 		}
+@@ -125,9 +121,29 @@ static int dwc2_drd_role_sw_set(struct usb_role_switch *sw, enum usb_role role)
+ 
+ 	spin_unlock_irqrestore(&hsotg->lock, flags);
+ 
+-	if (!already && hsotg->dr_mode == USB_DR_MODE_OTG)
+-		/* This will raise a Connector ID Status Change Interrupt */
+-		dwc2_force_mode(hsotg, role == USB_ROLE_HOST);
++	/* Wait for the session parameters to take effect */
++	msleep(100);
++
++	if (role == USB_ROLE_HOST) {
++		if (dwc2_is_device_mode(hsotg)) {
++			dwc2_force_mode(hsotg, true);
++
++			if (hsotg->wq_otg)
++					queue_work(hsotg->wq_otg, &hsotg->wf_otg);
++		}
++	} else if (role == USB_ROLE_DEVICE) {
++		if (dwc2_is_host_mode(hsotg)) {
++			dwc2_force_mode(hsotg, false);
++
++			if (hsotg->wq_otg)
++					queue_work(hsotg->wq_otg, &hsotg->wf_otg);
++		} else {
++			spin_lock_irqsave(&hsotg->lock, flags);
++			if (get_gadget_enabled(hsotg))
++				dwc2_hsotg_core_connect(hsotg);
++			spin_unlock_irqrestore(&hsotg->lock, flags);
++		}
++	}
+ 
+ 	if (!hsotg->ll_hw_enabled && hsotg->clk)
+ 		clk_disable_unprepare(hsotg->clk);
+@@ -139,23 +155,35 @@ static int dwc2_drd_role_sw_set(struct usb_role_switch *sw, enum usb_role role)
+ 	return 0;
+ }
+ 
++static const struct software_node ingenic_usb_node = {
++	"ingenic-usb-sw",
++};
++
+ int dwc2_drd_init(struct dwc2_hsotg *hsotg)
+ {
+ 	struct usb_role_switch_desc role_sw_desc = {0};
+ 	struct usb_role_switch *role_sw;
+ 	int ret;
+ 
+-	if (!device_property_read_bool(hsotg->dev, "usb-role-switch"))
++	if (hsotg->params.external_vbus_detect)
++		dwc2_vbus_valid(hsotg);
++
++	if (!hsotg->params.external_id_pin_ctl)
+ 		return 0;
+ 
++	ret = software_node_register(&ingenic_usb_node);
++	if (ret)
++		return ret;
++
+ 	role_sw_desc.driver_data = hsotg;
+-	role_sw_desc.fwnode = dev_fwnode(hsotg->dev);
++	role_sw_desc.fwnode = software_node_fwnode(&ingenic_usb_node);
+ 	role_sw_desc.set = dwc2_drd_role_sw_set;
+ 	role_sw_desc.allow_userspace_control = true;
+ 
+ 	role_sw = usb_role_switch_register(hsotg->dev, &role_sw_desc);
+ 	if (IS_ERR(role_sw)) {
+ 		ret = PTR_ERR(role_sw);
++		fwnode_handle_put(role_sw_desc.fwnode);
+ 		dev_err(hsotg->dev,
+ 			"failed to register role switch: %d\n", ret);
+ 		return ret;
+@@ -169,34 +197,10 @@ int dwc2_drd_init(struct dwc2_hsotg *hsotg)
+ 	return 0;
+ }
+ 
+-void dwc2_drd_suspend(struct dwc2_hsotg *hsotg)
+-{
+-	u32 gintsts, gintmsk;
+-
+-	if (hsotg->role_sw && !hsotg->params.external_id_pin_ctl) {
+-		gintmsk = dwc2_readl(hsotg, GINTMSK);
+-		gintmsk &= ~GINTSTS_CONIDSTSCHNG;
+-		dwc2_writel(hsotg, gintmsk, GINTMSK);
+-		gintsts = dwc2_readl(hsotg, GINTSTS);
+-		dwc2_writel(hsotg, gintsts | GINTSTS_CONIDSTSCHNG, GINTSTS);
+-	}
+-}
+-
+-void dwc2_drd_resume(struct dwc2_hsotg *hsotg)
+-{
+-	u32 gintsts, gintmsk;
+-
+-	if (hsotg->role_sw && !hsotg->params.external_id_pin_ctl) {
+-		gintsts = dwc2_readl(hsotg, GINTSTS);
+-		dwc2_writel(hsotg, gintsts | GINTSTS_CONIDSTSCHNG, GINTSTS);
+-		gintmsk = dwc2_readl(hsotg, GINTMSK);
+-		gintmsk |= GINTSTS_CONIDSTSCHNG;
+-		dwc2_writel(hsotg, gintmsk, GINTMSK);
+-	}
+-}
+-
+ void dwc2_drd_exit(struct dwc2_hsotg *hsotg)
+ {
+-	if (hsotg->role_sw)
++	if (hsotg->role_sw) {
+ 		usb_role_switch_unregister(hsotg->role_sw);
++		fwnode_handle_put(software_node_fwnode(&ingenic_usb_node));
++	}
+ }
+diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
+index 64485f82d..650a674cd 100644
+--- a/drivers/usb/dwc2/gadget.c
++++ b/drivers/usb/dwc2/gadget.c
+@@ -1030,12 +1030,6 @@ static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
+ 	dwc2_writel(hsotg, ctrl, depctl);
+ }
+ 
+-static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep);
+-static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
+-					struct dwc2_hsotg_ep *hs_ep,
+-				       struct dwc2_hsotg_req *hs_req,
+-				       int result);
+-
+ /**
+  * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
+  * @hsotg: The controller state.
+@@ -1188,21 +1182,14 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
+ 		}
+ 	}
+ 
+-	if (hs_ep->isochronous) {
+-		if (!dwc2_gadget_target_frame_elapsed(hs_ep)) {
+-			if (hs_ep->interval == 1) {
+-				if (hs_ep->target_frame & 0x1)
+-					ctrl |= DXEPCTL_SETODDFR;
+-				else
+-					ctrl |= DXEPCTL_SETEVENFR;
+-			}
+-			ctrl |= DXEPCTL_CNAK;
+-		} else {
+-			hs_req->req.frame_number = hs_ep->target_frame;
+-			hs_req->req.actual = 0;
+-			dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
+-			return;
+-		}
++	if (hs_ep->isochronous && hs_ep->interval == 1) {
++		hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
++		dwc2_gadget_incr_frame_num(hs_ep);
++
++		if (hs_ep->target_frame & 0x1)
++			ctrl |= DXEPCTL_SETODDFR;
++		else
++			ctrl |= DXEPCTL_SETEVENFR;
+ 	}
+ 
+ 	ctrl |= DXEPCTL_EPENA;	/* ensure ep enabled */
+@@ -1525,8 +1512,8 @@ static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
+ {
+ 	struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
+ 	struct dwc2_hsotg *hs = hs_ep->parent;
+-	unsigned long flags = 0;
+-	int ret = 0;
++	unsigned long flags;
++	int ret;
+ 
+ 	spin_lock_irqsave(&hs->lock, flags);
+ 	ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
+@@ -1742,9 +1729,11 @@ static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
+  */
+ static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
+ {
++	u32 mask;
+ 	struct dwc2_hsotg *hsotg = hs_ep->parent;
+ 	int dir_in = hs_ep->dir_in;
+ 	struct dwc2_hsotg_req *hs_req;
++	u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
+ 
+ 	if (!list_empty(&hs_ep->queue)) {
+ 		hs_req = get_ep_head(hs_ep);
+@@ -1760,6 +1749,9 @@ static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
+ 	} else {
+ 		dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
+ 			__func__);
++		mask = dwc2_readl(hsotg, epmsk_reg);
++		mask |= DOEPMSK_OUTTKNEPDISMSK;
++		dwc2_writel(hsotg, mask, epmsk_reg);
+ 	}
+ }
+ 
+@@ -1791,6 +1783,8 @@ static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
+ 	switch (recip) {
+ 	case USB_RECIP_DEVICE:
+ 		switch (wValue) {
++		case USB_DEVICE_B_HNP_ENABLE:
++			break;
+ 		case USB_DEVICE_REMOTE_WAKEUP:
+ 			if (set)
+ 				hsotg->remote_wakeup_allowed = 1;
+@@ -1830,7 +1824,8 @@ static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
+ 		case USB_ENDPOINT_HALT:
+ 			halted = ep->halted;
+ 
+-			dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
++			if (!ep->wedged)
++				dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
+ 
+ 			ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
+ 			if (ret) {
+@@ -1961,6 +1956,10 @@ static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
+ 			dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
+ 
+ 			ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
++			if (ctrl->wValue)
++				call_gadget_set_state(hsotg, USB_STATE_ADDRESS);
++			else
++				call_gadget_set_state(hsotg, USB_STATE_DEFAULT);
+ 			return;
+ 
+ 		case USB_REQ_GET_STATUS:
+@@ -2329,6 +2328,19 @@ static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
+ 	dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
+ }
+ 
++static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
++					    u32 epctl_reg)
++{
++	u32 ctrl;
++
++	ctrl = dwc2_readl(hsotg, epctl_reg);
++	if (ctrl & DXEPCTL_EOFRNUM)
++		ctrl |= DXEPCTL_SETEVENFR;
++	else
++		ctrl |= DXEPCTL_SETODDFR;
++	dwc2_writel(hsotg, ctrl, epctl_reg);
++}
++
+ /*
+  * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
+  * @hs_ep - The endpoint on which transfer went
+@@ -2449,12 +2461,21 @@ static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
+ 			dwc2_hsotg_ep0_zlp(hsotg, true);
+ 	}
+ 
+-	/* Set actual frame number for completed transfers */
+-	if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
+-		req->frame_number = hs_ep->target_frame;
+-		dwc2_gadget_incr_frame_num(hs_ep);
++	/*
++	 * Slave mode OUT transfers do not go through XferComplete so
++	 * adjust the ISOC parity here.
++	 */
++	if (!using_dma(hsotg)) {
++		if (hs_ep->isochronous && hs_ep->interval == 1)
++			dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
++		else if (hs_ep->isochronous && hs_ep->interval > 1)
++			dwc2_gadget_incr_frame_num(hs_ep);
+ 	}
+ 
++	/* Set actual frame number for completed transfers */
++	if (!using_desc_dma(hsotg) && hs_ep->isochronous)
++		req->frame_number = hsotg->frame_number;
++
+ 	dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
+ }
+ 
+@@ -2767,12 +2788,6 @@ static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
+ 		return;
+ 	}
+ 
+-	/* Set actual frame number for completed transfers */
+-	if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
+-		hs_req->req.frame_number = hs_ep->target_frame;
+-		dwc2_gadget_incr_frame_num(hs_ep);
+-	}
+-
+ 	dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
+ }
+ 
+@@ -2833,18 +2848,23 @@ static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
+ 
+ 		dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
+ 
++		if (hs_ep->isochronous) {
++			dwc2_hsotg_complete_in(hsotg, hs_ep);
++			return;
++		}
++
+ 		if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
+ 			int dctl = dwc2_readl(hsotg, DCTL);
+ 
+ 			dctl |= DCTL_CGNPINNAK;
+ 			dwc2_writel(hsotg, dctl, DCTL);
+ 		}
+-	} else {
++		return;
++	}
+ 
+-		if (dctl & DCTL_GOUTNAKSTS) {
+-			dctl |= DCTL_CGOUTNAK;
+-			dwc2_writel(hsotg, dctl, DCTL);
+-		}
++	if (dctl & DCTL_GOUTNAKSTS) {
++		dctl |= DCTL_CGOUTNAK;
++		dwc2_writel(hsotg, dctl, DCTL);
+ 	}
+ 
+ 	if (!hs_ep->isochronous)
+@@ -2861,13 +2881,14 @@ static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
+ 		if (hs_req) {
+ 			hs_req->req.frame_number = hs_ep->target_frame;
+ 			hs_req->req.actual = 0;
+-			dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
+-						    -ENODATA);
++			dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
+ 		}
+ 		dwc2_gadget_incr_frame_num(hs_ep);
+ 		/* Update current frame number value. */
+ 		hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
+ 	} while (dwc2_gadget_target_frame_elapsed(hs_ep));
++
++	dwc2_gadget_start_next_request(hs_ep);
+ }
+ 
+ /**
+@@ -2884,8 +2905,8 @@ static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
+ static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
+ {
+ 	struct dwc2_hsotg *hsotg = ep->parent;
+-	struct dwc2_hsotg_req *hs_req;
+ 	int dir_in = ep->dir_in;
++	u32 doepmsk;
+ 
+ 	if (dir_in || !ep->isochronous)
+ 		return;
+@@ -2899,42 +2920,28 @@ static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
+ 		return;
+ 	}
+ 
+-	if (ep->target_frame == TARGET_FRAME_INITIAL) {
++	if (ep->interval > 1 &&
++	    ep->target_frame == TARGET_FRAME_INITIAL) {
+ 		u32 ctrl;
+ 
+ 		ep->target_frame = hsotg->frame_number;
+-		if (ep->interval > 1) {
+-			ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
+-			if (ep->target_frame & 0x1)
+-				ctrl |= DXEPCTL_SETODDFR;
+-			else
+-				ctrl |= DXEPCTL_SETEVENFR;
+-
+-			dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
+-		}
+-	}
++		dwc2_gadget_incr_frame_num(ep);
+ 
+-	while (dwc2_gadget_target_frame_elapsed(ep)) {
+-		hs_req = get_ep_head(ep);
+-		if (hs_req) {
+-			hs_req->req.frame_number = ep->target_frame;
+-			hs_req->req.actual = 0;
+-			dwc2_hsotg_complete_request(hsotg, ep, hs_req, -ENODATA);
+-		}
++		ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
++		if (ep->target_frame & 0x1)
++			ctrl |= DXEPCTL_SETODDFR;
++		else
++			ctrl |= DXEPCTL_SETEVENFR;
+ 
+-		dwc2_gadget_incr_frame_num(ep);
+-		/* Update current frame number value. */
+-		hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
++		dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
+ 	}
+ 
+-	if (!ep->req)
+-		dwc2_gadget_start_next_request(ep);
+-
++	dwc2_gadget_start_next_request(ep);
++	doepmsk = dwc2_readl(hsotg, DOEPMSK);
++	doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
++	dwc2_writel(hsotg, doepmsk, DOEPMSK);
+ }
+ 
+-static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
+-				   struct dwc2_hsotg_ep *hs_ep);
+-
+ /**
+  * dwc2_gadget_handle_nak - handle NAK interrupt
+  * @hs_ep: The endpoint on which interrupt is asserted.
+@@ -2952,9 +2959,7 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
+ static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
+ {
+ 	struct dwc2_hsotg *hsotg = hs_ep->parent;
+-	struct dwc2_hsotg_req *hs_req;
+ 	int dir_in = hs_ep->dir_in;
+-	u32 ctrl;
+ 
+ 	if (!dir_in || !hs_ep->isochronous)
+ 		return;
+@@ -2996,32 +3001,13 @@ static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
+ 
+ 			dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
+ 		}
+-	}
+ 
+-	if (using_desc_dma(hsotg))
+-		return;
+-
+-	ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index));
+-	if (ctrl & DXEPCTL_EPENA)
+-		dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
+-	else
+-		dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
+-
+-	while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
+-		hs_req = get_ep_head(hs_ep);
+-		if (hs_req) {
+-			hs_req->req.frame_number = hs_ep->target_frame;
+-			hs_req->req.actual = 0;
+-			dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
+-		}
+-
+-		dwc2_gadget_incr_frame_num(hs_ep);
+-		/* Update current frame number value. */
+-		hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
++		dwc2_hsotg_complete_request(hsotg, hs_ep,
++					    get_ep_head(hs_ep), 0);
+ 	}
+ 
+-	if (!hs_ep->req)
+-		dwc2_gadget_start_next_request(hs_ep);
++	if (!using_desc_dma(hsotg))
++		dwc2_gadget_incr_frame_num(hs_ep);
+ }
+ 
+ /**
+@@ -3084,8 +3070,12 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
+ 			 * need to look at completing IN requests here
+ 			 * if operating slave mode
+ 			 */
+-			if (!hs_ep->isochronous || !(ints & DXEPINT_NAKINTRPT))
+-				dwc2_hsotg_complete_in(hsotg, hs_ep);
++			if (hs_ep->isochronous && hs_ep->interval > 1)
++				dwc2_gadget_incr_frame_num(hs_ep);
++
++			dwc2_hsotg_complete_in(hsotg, hs_ep);
++			if (ints & DXEPINT_NAKINTRPT)
++				ints &= ~DXEPINT_NAKINTRPT;
+ 
+ 			if (idx == 0 && !hs_ep->req)
+ 				dwc2_hsotg_enqueue_setup(hsotg);
+@@ -3094,8 +3084,10 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
+ 			 * We're using DMA, we need to fire an OutDone here
+ 			 * as we ignore the RXFIFO.
+ 			 */
+-			if (!hs_ep->isochronous || !(ints & DXEPINT_OUTTKNEPDIS))
+-				dwc2_hsotg_handle_outdone(hsotg, idx);
++			if (hs_ep->isochronous && hs_ep->interval > 1)
++				dwc2_gadget_incr_frame_num(hs_ep);
++
++			dwc2_hsotg_handle_outdone(hsotg, idx);
+ 		}
+ 	}
+ 
+@@ -3312,6 +3304,7 @@ void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
+ {
+ 	unsigned int ep;
+ 
++
+ 	if (!hsotg->connected)
+ 		return;
+ 
+@@ -3329,9 +3322,8 @@ void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
+ 	}
+ 
+ 	call_gadget(hsotg, disconnect);
++	call_gadget_set_state(hsotg, USB_STATE_NOTATTACHED);
+ 	hsotg->lx_state = DWC2_L3;
+-
+-	usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
+ }
+ 
+ /**
+@@ -3371,7 +3363,7 @@ static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
+ 
+ static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
+ /**
+- * dwc2_hsotg_core_init - issue softreset to the core
++ * dwc2_hsotg_core_init_disconnected - issue softreset to the core
+  * @hsotg: The device state
+  * @is_usb_reset: Usb resetting flag
+  *
+@@ -3456,8 +3448,14 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
+ 		GINTSTS_USBSUSP | GINTSTS_WKUPINT |
+ 		GINTSTS_LPMTRANRCVD;
+ 
+-	if (!using_desc_dma(hsotg))
+-		intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
++	/*
++	 * Ignoring the abnormal transmission of the synchronization endpoint,
++	 * the controller classifies the missing frame as abnormal transmission.
++	 * Some embedded hosts are unstable in the synchronization cycle,
++	 * missing frame causes the abnormal transmission of data to be discarded.
++	 */
++	// if (!using_desc_dma(hsotg))
++	// 	intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
+ 
+ 	if (!hsotg->params.external_id_pin_ctl)
+ 		intmsk |= GINTSTS_CONIDSTSCHNG;
+@@ -3723,14 +3721,13 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
+ 		dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
+ 
+ 		/* This event must be used only if controller is suspended */
+-		if (hsotg->lx_state == DWC2_L2) {
+-			dwc2_exit_partial_power_down(hsotg, true);
+-			hsotg->lx_state = DWC2_L0;
+-		}
++		if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2)
++			dwc2_exit_partial_power_down(hsotg, 0, true);
++
++		hsotg->lx_state = DWC2_L0;
+ 	}
+ 
+ 	if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
+-		u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
+ 		u32 connected = hsotg->connected;
+ 
+ 		dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
+@@ -3745,8 +3742,10 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
+ 		/* Reset device address to zero */
+ 		dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
+ 
+-		if (usb_status & GOTGCTL_BSESVLD && connected)
++		if (connected)
+ 			dwc2_hsotg_core_init_disconnected(hsotg, true);
++		
++		call_gadget_set_state(hsotg, USB_STATE_DEFAULT);
+ 	}
+ 
+ 	if (gintsts & GINTSTS_ENUMDONE) {
+@@ -4097,6 +4096,7 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
+ 	hs_ep->isochronous = 0;
+ 	hs_ep->periodic = 0;
+ 	hs_ep->halted = 0;
++	hs_ep->wedged = 0;
+ 	hs_ep->interval = desc->bInterval;
+ 
+ 	switch (ep_type) {
+@@ -4114,7 +4114,6 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
+ 			mask |= DIEPMSK_NAKMSK;
+ 			dwc2_writel(hsotg, mask, DIEPMSK);
+ 		} else {
+-			epctrl |= DXEPCTL_SNAK;
+ 			mask = dwc2_readl(hsotg, DOEPMSK);
+ 			mask |= DOEPMSK_OUTTKNEPDISMSK;
+ 			dwc2_writel(hsotg, mask, DOEPMSK);
+@@ -4338,6 +4337,27 @@ static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
+ 	return 0;
+ }
+ 
++/**
++ * dwc2_gadget_ep_set_wedge - set wedge on a given endpoint
++ * @ep: The endpoint to be wedged.
++ *
++ */
++static int dwc2_gadget_ep_set_wedge(struct usb_ep *ep)
++{
++	struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
++	struct dwc2_hsotg *hs = hs_ep->parent;
++
++	unsigned long	flags;
++	int		ret;
++
++	spin_lock_irqsave(&hs->lock, flags);
++	hs_ep->wedged = 1;
++	ret = dwc2_hsotg_ep_sethalt(ep, 1, false);
++	spin_unlock_irqrestore(&hs->lock, flags);
++
++	return ret;
++}
++
+ /**
+  * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
+  * @ep: The endpoint to set halt.
+@@ -4389,6 +4409,7 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
+ 				epctl |= DXEPCTL_EPDIS;
+ 		} else {
+ 			epctl &= ~DXEPCTL_STALL;
++			hs_ep->wedged = 0;
+ 			xfertype = epctl & DXEPCTL_EPTYPE_MASK;
+ 			if (xfertype == DXEPCTL_EPTYPE_BULK ||
+ 			    xfertype == DXEPCTL_EPTYPE_INTERRUPT)
+@@ -4408,6 +4429,7 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
+ 			// STALL bit will be set in GOUTNAKEFF interrupt handler
+ 		} else {
+ 			epctl &= ~DXEPCTL_STALL;
++			hs_ep->wedged = 0;
+ 			xfertype = epctl & DXEPCTL_EPTYPE_MASK;
+ 			if (xfertype == DXEPCTL_EPTYPE_BULK ||
+ 			    xfertype == DXEPCTL_EPTYPE_INTERRUPT)
+@@ -4429,8 +4451,8 @@ static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
+ {
+ 	struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
+ 	struct dwc2_hsotg *hs = hs_ep->parent;
+-	unsigned long flags = 0;
+-	int ret = 0;
++	unsigned long flags;
++	int ret;
+ 
+ 	spin_lock_irqsave(&hs->lock, flags);
+ 	ret = dwc2_hsotg_ep_sethalt(ep, value, false);
+@@ -4447,6 +4469,7 @@ static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
+ 	.queue		= dwc2_hsotg_ep_queue_lock,
+ 	.dequeue	= dwc2_hsotg_ep_dequeue,
+ 	.set_halt	= dwc2_hsotg_ep_sethalt_lock,
++	.set_wedge	= dwc2_gadget_ep_set_wedge,
+ 	/* note, don't believe we have any call for the fifo routines */
+ };
+ 
+@@ -4559,7 +4582,7 @@ static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
+ static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
+ {
+ 	struct dwc2_hsotg *hsotg = to_hsotg(gadget);
+-	unsigned long flags = 0;
++	unsigned long flags;
+ 	int ep;
+ 
+ 	if (!hsotg)
+@@ -4631,7 +4654,7 @@ static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
+ static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
+ {
+ 	struct dwc2_hsotg *hsotg = to_hsotg(gadget);
+-	unsigned long flags = 0;
++	unsigned long flags;
+ 
+ 	dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
+ 		hsotg->op_state);
+@@ -4667,20 +4690,28 @@ static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
+ 	unsigned long flags;
+ 
+ 	dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
++
++	/* called in host mode? */
++	if (hsotg->op_state != OTG_STATE_B_PERIPHERAL)
++		return -EINVAL;
++
+ 	spin_lock_irqsave(&hsotg->lock, flags);
+ 
+ 	/*
+-	 * If controller is hibernated, it must exit from power_down
+-	 * before being initialized / de-initialized
++	 * If controller is in partial power down state, it must exit from
++	 * that state before being initialized / de-initialized
+ 	 */
+-	if (hsotg->lx_state == DWC2_L2)
+-		dwc2_exit_partial_power_down(hsotg, false);
++	if (hsotg->lx_state == DWC2_L2 && hsotg->in_ppd)
++		/*
++		 * No need to check the return value as
++		 * registers are not being restored.
++		 */
++		dwc2_exit_partial_power_down(hsotg, 0, false);
+ 
+ 	if (is_active) {
+-		hsotg->op_state = OTG_STATE_B_PERIPHERAL;
+-
++		call_gadget_set_state(hsotg, USB_STATE_POWERED);
+ 		dwc2_hsotg_core_init_disconnected(hsotg, false);
+-		if (hsotg->enabled) {
++		if (get_gadget_enabled(hsotg)) {
+ 			/* Enable ACG feature in device mode,if supported */
+ 			dwc2_enable_acg(hsotg);
+ 			dwc2_hsotg_core_connect(hsotg);
+@@ -4710,14 +4741,90 @@ static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
+ 	return usb_phy_set_power(hsotg->uphy, mA);
+ }
+ 
++static void dwc2_gadget_set_speed(struct usb_gadget *g, enum usb_device_speed speed)
++{
++	struct dwc2_hsotg *hsotg = to_hsotg(g);
++	unsigned long		flags;
++
++	spin_lock_irqsave(&hsotg->lock, flags);
++	switch (speed) {
++	case USB_SPEED_HIGH:
++		hsotg->params.speed = DWC2_SPEED_PARAM_HIGH;
++		break;
++	case USB_SPEED_FULL:
++		hsotg->params.speed = DWC2_SPEED_PARAM_FULL;
++		break;
++	case USB_SPEED_LOW:
++		hsotg->params.speed = DWC2_SPEED_PARAM_LOW;
++		break;
++	default:
++		dev_err(hsotg->dev, "invalid speed (%d)\n", speed);
++	}
++	spin_unlock_irqrestore(&hsotg->lock, flags);
++}
++
++static int dwc2_hsotg_wakeup(struct usb_gadget *gadget)
++{
++	int ret;
++	u32 dsts, dctl;
++	unsigned long flags;
++	struct dwc2_hsotg *hsotg = to_hsotg(gadget);
++
++	if (!dwc2_is_device_mode(hsotg))
++		return -EINVAL;
++
++	spin_lock_irqsave(&hsotg->lock, flags);
++
++	if (hsotg->connected) {
++		if (hsotg->remote_wakeup_allowed) {
++			dsts = dwc2_readl(hsotg, DSTS);
++			if (dsts & DSTS_SUSPSTS) {
++				dctl = dwc2_readl(hsotg, DCTL);
++				dctl |= DCTL_RMTWKUPSIG;
++				dwc2_writel(hsotg, dctl, DCTL);
++				mdelay(10);
++				dctl &= ~DCTL_RMTWKUPSIG;
++				dwc2_writel(hsotg, dctl, DCTL);
++
++				if (hsotg->lx_state == DWC2_L2) {
++					if (hsotg->in_ppd) {
++						ret = dwc2_exit_partial_power_down(hsotg, 1, true);
++						if (ret)
++							dev_err(hsotg->dev,
++								"exit partial_power_down failed\n");
++						call_gadget(hsotg, resume);
++						call_gadget_set_state(hsotg, hsotg->resume_state);
++					}
++
++					/* Exit gadget mode clock gating. */
++					if (hsotg->params.power_down ==
++						DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended)
++						dwc2_gadget_exit_clock_gating(hsotg, 0);
++				} else {
++					/* Change to L0 state */
++					hsotg->lx_state = DWC2_L0;
++				}
++			}
++		} else {
++			dev_info(hsotg->dev, "Remote Wakeup is disabled\n");
++		}
++	}
++
++	spin_unlock_irqrestore(&hsotg->lock, flags);
++
++	return 0;
++}
++
+ static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
+ 	.get_frame	= dwc2_hsotg_gadget_getframe,
+ 	.set_selfpowered	= dwc2_hsotg_set_selfpowered,
+ 	.udc_start		= dwc2_hsotg_udc_start,
+ 	.udc_stop		= dwc2_hsotg_udc_stop,
+ 	.pullup                 = dwc2_hsotg_pullup,
++	.udc_set_speed		= dwc2_gadget_set_speed,
+ 	.vbus_session		= dwc2_hsotg_vbus_session,
+ 	.vbus_draw		= dwc2_hsotg_vbus_draw,
++	.wakeup		= dwc2_hsotg_wakeup,
+ };
+ 
+ /**
+@@ -4923,6 +5030,7 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
+ 	hsotg->gadget.max_speed = USB_SPEED_HIGH;
+ 	hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
+ 	hsotg->gadget.name = dev_name(dev);
++	hsotg->gadget.otg_caps = &hsotg->params.otg_caps;
+ 	hsotg->remote_wakeup_allowed = 0;
+ 
+ 	if (hsotg->params.lpm)
+@@ -5025,7 +5133,7 @@ int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
+ 			 hsotg->driver->driver.name);
+ 
+ 		spin_lock_irqsave(&hsotg->lock, flags);
+-		if (hsotg->enabled)
++		if (get_gadget_enabled(hsotg))
+ 			dwc2_hsotg_core_disconnect(hsotg);
+ 		dwc2_hsotg_disconnect(hsotg);
+ 		hsotg->gadget.speed = USB_SPEED_UNKNOWN;
+@@ -5055,7 +5163,7 @@ int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
+ 
+ 		spin_lock_irqsave(&hsotg->lock, flags);
+ 		dwc2_hsotg_core_init_disconnected(hsotg, false);
+-		if (hsotg->enabled) {
++		if (get_gadget_enabled(hsotg)) {
+ 			/* Enable ACG feature in device mode,if supported */
+ 			dwc2_enable_acg(hsotg);
+ 			dwc2_hsotg_core_connect(hsotg);
+@@ -5314,7 +5422,6 @@ int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
+ int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
+ 				 int rem_wakeup, int reset)
+ {
+-	u32 pcgcctl;
+ 	u32 gpwrdn;
+ 	u32 dctl;
+ 	int ret = 0;
+@@ -5345,17 +5452,15 @@ int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
+ 	dwc2_writel(hsotg, gpwrdn, GPWRDN);
+ 	udelay(10);
+ 
+-	if (!rem_wakeup) {
+-		pcgcctl = dwc2_readl(hsotg, PCGCTL);
+-		pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
+-		dwc2_writel(hsotg, pcgcctl, PCGCTL);
+-	}
+-
+ 	/* Restore GUSBCFG, DCFG and DCTL */
+ 	dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
+ 	dwc2_writel(hsotg, dr->dcfg, DCFG);
+ 	dwc2_writel(hsotg, dr->dctl, DCTL);
+ 
++	/* On USB Reset, reset device address to zero */
++	if (reset)
++		dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
++
+ 	/* De-assert Wakeup Logic */
+ 	gpwrdn = dwc2_readl(hsotg, GPWRDN);
+ 	gpwrdn &= ~GPWRDN_PMUACTV;
+@@ -5406,3 +5511,149 @@ int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
+ 
+ 	return ret;
+ }
++
++
++/**
++ * dwc2_gadget_enter_partial_power_down() - Put controller in partial
++ * power down.
++ *
++ * @hsotg: Programming view of the DWC_otg controller
++ *
++ * Return: non-zero if failed to enter device partial power down.
++ *
++ * This function is for entering device mode partial power down.
++ */
++int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
++{
++	int ret = 0;
++
++	dev_dbg(hsotg->dev, "Entering device partial power down started.\n");
++
++	/* Backup all registers */
++	ret = dwc2_backup_global_registers(hsotg);
++	if (ret) {
++		dev_err(hsotg->dev, "%s: failed to backup global registers\n",
++			__func__);
++		return ret;
++	}
++
++	ret = dwc2_backup_device_registers(hsotg);
++	if (ret) {
++		dev_err(hsotg->dev, "%s: failed to backup device registers\n",
++			__func__);
++		return ret;
++	}
++
++	/*
++	 * Clear any pending interrupts since dwc2 will not be able to
++	 * clear them after entering partial_power_down.
++	 */
++	dwc2_writel(hsotg, 0xffffffff, GINTSTS);
++
++	/* Set in_ppd flag to 1 as here core enters suspend. */
++	hsotg->in_ppd = 1;
++	hsotg->lx_state = DWC2_L2;
++
++	dev_dbg(hsotg->dev, "Entering device partial power down completed.\n");
++
++	return ret;
++}
++
++/*
++ * dwc2_gadget_exit_partial_power_down() - Exit controller from device partial
++ * power down.
++ *
++ * @hsotg: Programming view of the DWC_otg controller
++ * @restore: indicates whether need to restore the registers or not.
++ *
++ * Return: non-zero if failed to exit device partial power down.
++ *
++ * This function is for exiting from device mode partial power down.
++ */
++int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
++					bool restore)
++{
++	u32 dctl;
++	struct dwc2_dregs_backup *dr;
++	int ret = 0;
++
++	dr = &hsotg->dr_backup;
++
++	dev_dbg(hsotg->dev, "Exiting device partial Power Down started.\n");
++
++	udelay(100);
++	if (restore) {
++		ret = dwc2_restore_global_registers(hsotg);
++		if (ret) {
++			dev_err(hsotg->dev, "%s: failed to restore registers\n",
++				__func__);
++			return ret;
++		}
++		/* Restore DCFG */
++		dwc2_writel(hsotg, dr->dcfg, DCFG);
++
++		ret = dwc2_restore_device_registers(hsotg, 0);
++		if (ret) {
++			dev_err(hsotg->dev, "%s: failed to restore device registers\n",
++				__func__);
++			return ret;
++		}
++	}
++
++	/* Set the Power-On Programming done bit */
++	dctl = dwc2_readl(hsotg, DCTL);
++	dctl |= DCTL_PWRONPRGDONE;
++	dwc2_writel(hsotg, dctl, DCTL);
++
++	/* Set in_ppd flag to 0 as here core exits from suspend. */
++	hsotg->in_ppd = 0;
++	hsotg->lx_state = DWC2_L0;
++
++	dev_dbg(hsotg->dev, "Exiting device partial Power Down completed.\n");
++	return ret;
++}
++
++/**
++ * dwc2_gadget_enter_clock_gating() - Put controller in clock gating.
++ *
++ * @hsotg: Programming view of the DWC_otg controller
++ *
++ * Return: non-zero if failed to enter device partial power down.
++ *
++ * This function is for entering device mode clock gating.
++ */
++void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg)
++{
++	dev_dbg(hsotg->dev, "Entering device clock gating.\n");
++
++	hsotg->lx_state = DWC2_L2;
++	hsotg->bus_suspended = true;
++}
++
++/*
++ * dwc2_gadget_exit_clock_gating() - Exit controller from device clock gating.
++ *
++ * @hsotg: Programming view of the DWC_otg controller
++ * @rem_wakeup: indicates whether remote wake up is enabled.
++ *
++ * This function is for exiting from device mode clock gating.
++ */
++void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup)
++{
++	u32 dctl;
++
++	dev_dbg(hsotg->dev, "Exiting device clock gating.\n");
++
++	if (rem_wakeup) {
++		/* Set Remote Wakeup Signaling */
++		dctl = dwc2_readl(hsotg, DCTL);
++		dctl |= DCTL_RMTWKUPSIG;
++		dwc2_writel(hsotg, dctl, DCTL);
++	}
++
++	/* Change to L0 state */
++	call_gadget(hsotg, resume);
++	hsotg->lx_state = DWC2_L0;
++	hsotg->bus_suspended = false;
++	call_gadget_set_state(hsotg, hsotg->resume_state);
++}
+diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
+index 9279d3d36..e228bfbe0 100644
+--- a/drivers/usb/dwc2/hcd.c
++++ b/drivers/usb/dwc2/hcd.c
+@@ -56,8 +56,6 @@
+ #include "core.h"
+ #include "hcd.h"
+ 
+-static void dwc2_port_resume(struct dwc2_hsotg *hsotg);
+-
+ /*
+  * =========================================================================
+  *  Host Core Layer Functions
+@@ -140,19 +138,17 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
+ 
+ 	switch (hsotg->hw_params.op_mode) {
+ 	case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
+-		if (hsotg->params.otg_cap ==
+-				DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
++		if (hsotg->params.otg_caps.hnp_support &&
++		    hsotg->params.otg_caps.srp_support)
+ 			usbcfg |= GUSBCFG_HNPCAP;
+-		if (hsotg->params.otg_cap !=
+-				DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
++		if (hsotg->params.otg_caps.srp_support)
+ 			usbcfg |= GUSBCFG_SRPCAP;
+ 		break;
+ 
+ 	case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
+ 	case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
+ 	case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
+-		if (hsotg->params.otg_cap !=
+-				DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
++		if (hsotg->params.otg_caps.srp_support)
+ 			usbcfg |= GUSBCFG_SRPCAP;
+ 		break;
+ 
+@@ -168,16 +164,28 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
+ 
+ static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg)
+ {
+-	if (hsotg->vbus_supply)
+-		return regulator_enable(hsotg->vbus_supply);
++	if (!hsotg->vbus_supply_enabled) {
++		hsotg->vbus_supply_enabled = 1;
++
++		usb_phy_vbus_on(hsotg->uphy);
++
++		if (hsotg->vbus_supply)
++			regulator_enable(hsotg->vbus_supply);
++	}
+ 
+ 	return 0;
+ }
+ 
+ static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg)
+ {
+-	if (hsotg->vbus_supply)
+-		return regulator_disable(hsotg->vbus_supply);
++	if (hsotg->vbus_supply_enabled) {
++		hsotg->vbus_supply_enabled = 0;
++
++		if (hsotg->vbus_supply)
++			regulator_disable(hsotg->vbus_supply);
++
++		usb_phy_vbus_off(hsotg->uphy);
++	}
+ 
+ 	return 0;
+ }
+@@ -1748,6 +1756,8 @@ static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
+ 	}
+ }
+ 
++extern void usb_kick_hub_wq(struct usb_device *hdev);
++
+ /**
+  * dwc2_hcd_connect() - Handles connect of the HCD
+  *
+@@ -1776,6 +1786,8 @@ void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
+ {
+ 	u32 intr;
+ 	u32 hprt0;
++	struct usb_hcd *hcd = (struct usb_hcd *)hsotg->priv;
++	struct usb_device *rhdev = hcd->self.root_hub;
+ 
+ 	/* Set status flags for the hub driver */
+ 	hsotg->flags.b.port_connect_status_change = 1;
+@@ -1815,6 +1827,10 @@ void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
+ 
+ 	dwc2_host_disconnect(hsotg);
+ 
++	/* Handling hub disconnect events */
++	if (rhdev->state == USB_STATE_SUSPENDED) {
++		usb_kick_hub_wq(rhdev);
++	}
+ 	/*
+ 	 * Add an extra check here to see if we're actually connected but
+ 	 * we don't have a detection interrupt pending.  This can happen if:
+@@ -2179,9 +2195,6 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
+ 	usbcfg |= GUSBCFG_TOUTCAL(7);
+ 	dwc2_writel(hsotg, usbcfg, GUSBCFG);
+ 
+-	/* Restart the Phy Clock */
+-	dwc2_writel(hsotg, 0, PCGCTL);
+-
+ 	/* Initialize Host Configuration Register */
+ 	dwc2_init_fs_ls_pclk_sel(hsotg);
+ 	if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
+@@ -3208,15 +3221,26 @@ static void dwc2_conn_id_status_change(struct work_struct *work)
+ 		if (count > 250)
+ 			dev_err(hsotg->dev,
+ 				"Connection id status change timed out\n");
++
++		/*
++		 * Exit Partial Power Down without restoring registers.
++		 * No need to check the return value as registers
++		 * are not being restored.
++		 */
++		if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2)
++			dwc2_exit_partial_power_down(hsotg, 0, false);
++
+ 		hsotg->op_state = OTG_STATE_B_PERIPHERAL;
+ 		dwc2_core_init(hsotg, false);
+ 		dwc2_enable_global_interrupts(hsotg);
+ 		spin_lock_irqsave(&hsotg->lock, flags);
+ 		dwc2_hsotg_core_init_disconnected(hsotg, false);
++		if (get_gadget_enabled(hsotg)) {
++			/* Enable ACG feature in device mode,if supported */
++			dwc2_enable_acg(hsotg);
++			dwc2_hsotg_core_connect(hsotg);
++		}
+ 		spin_unlock_irqrestore(&hsotg->lock, flags);
+-		/* Enable ACG feature in device mode,if supported */
+-		dwc2_enable_acg(hsotg);
+-		dwc2_hsotg_core_connect(hsotg);
+ 	} else {
+ host:
+ 		/* A-Device connector (Host Mode) */
+@@ -3277,13 +3301,22 @@ static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
+ 	return hcd->self.b_hnp_enable;
+ }
+ 
+-/* Must NOT be called with interrupt disabled or spinlock held */
+-static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
++/**
++ * dwc2_port_suspend() - Put controller in suspend mode for host.
++ *
++ * @hsotg: Programming view of the DWC_otg controller
++ * @windex: The control request wIndex field
++ *
++ * Return: non-zero if failed to enter suspend mode for host.
++ *
++ * This function is for entering Host mode suspend.
++ * Must NOT be called with interrupt disabled or spinlock held.
++ */
++int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
+ {
+ 	unsigned long flags;
+-	u32 hprt0;
+-	u32 pcgctl;
+ 	u32 gotgctl;
++	int ret = 0;
+ 
+ 	dev_dbg(hsotg->dev, "%s()\n", __func__);
+ 
+@@ -3296,74 +3329,88 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
+ 		hsotg->op_state = OTG_STATE_A_SUSPEND;
+ 	}
+ 
+-	hprt0 = dwc2_read_hprt0(hsotg);
+-	hprt0 |= HPRT0_SUSP;
+-	dwc2_writel(hsotg, hprt0, HPRT0);
+-
+-	hsotg->bus_suspended = true;
+-
+-	/*
+-	 * If power_down is supported, Phy clock will be suspended
+-	 * after registers are backuped.
+-	 */
+-	if (!hsotg->params.power_down) {
+-		/* Suspend the Phy Clock */
+-		pcgctl = dwc2_readl(hsotg, PCGCTL);
+-		pcgctl |= PCGCTL_STOPPCLK;
+-		dwc2_writel(hsotg, pcgctl, PCGCTL);
+-		udelay(10);
++	switch (hsotg->params.power_down) {
++	case DWC2_POWER_DOWN_PARAM_PARTIAL:
++		ret = dwc2_enter_partial_power_down(hsotg);
++		if (ret)
++			dev_err(hsotg->dev,
++				"enter partial_power_down failed.\n");
++		break;
++	case DWC2_POWER_DOWN_PARAM_HIBERNATION:
++		/*
++		 * Perform spin unlock and lock because in
++		 * "dwc2_host_enter_hibernation()" function there is a spinlock
++		 * logic which prevents servicing of any IRQ during entering
++		 * hibernation.
++		 */
++		spin_unlock_irqrestore(&hsotg->lock, flags);
++		ret = dwc2_enter_hibernation(hsotg, 1);
++		if (ret)
++			dev_err(hsotg->dev, "enter hibernation failed.\n");
++		spin_lock_irqsave(&hsotg->lock, flags);
++		break;
++	case DWC2_POWER_DOWN_PARAM_NONE:
++		/*
++		 * If not hibernation nor partial power down are supported,
++		 * clock gating is used to save power.
++		 */
++		dwc2_host_enter_clock_gating(hsotg);
++		break;
+ 	}
+ 
+-	/* For HNP the bus must be suspended for at least 200ms */
+-	if (dwc2_host_is_b_hnp_enabled(hsotg)) {
+-		pcgctl = dwc2_readl(hsotg, PCGCTL);
+-		pcgctl &= ~PCGCTL_STOPPCLK;
+-		dwc2_writel(hsotg, pcgctl, PCGCTL);
+-
+-		spin_unlock_irqrestore(&hsotg->lock, flags);
++	spin_unlock_irqrestore(&hsotg->lock, flags);
+ 
++	/* For HNP the bus must be suspended for at least 200ms */
++	if (dwc2_host_is_b_hnp_enabled(hsotg))
+ 		msleep(200);
+-	} else {
+-		spin_unlock_irqrestore(&hsotg->lock, flags);
+-	}
++
++	return ret;
+ }
+ 
+-/* Must NOT be called with interrupt disabled or spinlock held */
+-static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
++/**
++ * dwc2_port_resume() - Exit controller from suspend mode for host.
++ *
++ * @hsotg: Programming view of the DWC_otg controller
++ *
++ * Return: non-zero if failed to exit suspend mode for host.
++ *
++ * This function is for exiting Host mode suspend.
++ * Must NOT be called with interrupt disabled or spinlock held.
++ */
++int dwc2_port_resume(struct dwc2_hsotg *hsotg)
+ {
+ 	unsigned long flags;
+-	u32 hprt0;
+-	u32 pcgctl;
++	int ret = 0;
+ 
+ 	spin_lock_irqsave(&hsotg->lock, flags);
+ 
+-	/*
+-	 * If power_down is supported, Phy clock is already resumed
+-	 * after registers restore.
+-	 */
+-	if (!hsotg->params.power_down) {
+-		pcgctl = dwc2_readl(hsotg, PCGCTL);
+-		pcgctl &= ~PCGCTL_STOPPCLK;
+-		dwc2_writel(hsotg, pcgctl, PCGCTL);
++	switch (hsotg->params.power_down) {
++	case DWC2_POWER_DOWN_PARAM_PARTIAL:
++		ret = dwc2_exit_partial_power_down(hsotg, 0, true);
++		if (ret)
++			dev_err(hsotg->dev,
++				"exit partial_power_down failed.\n");
++		break;
++	case DWC2_POWER_DOWN_PARAM_HIBERNATION:
++		/* Exit host hibernation. */
++		ret = dwc2_exit_hibernation(hsotg, 0, 0, 1);
++		if (ret)
++			dev_err(hsotg->dev, "exit hibernation failed.\n");
++		break;
++	case DWC2_POWER_DOWN_PARAM_NONE:
++		/*
++		 * If not hibernation nor partial power down are supported,
++		 * port resume is done using the clock gating programming flow.
++		 */
+ 		spin_unlock_irqrestore(&hsotg->lock, flags);
+-		msleep(20);
++		dwc2_host_exit_clock_gating(hsotg, 0);
+ 		spin_lock_irqsave(&hsotg->lock, flags);
++		break;
+ 	}
+ 
+-	hprt0 = dwc2_read_hprt0(hsotg);
+-	hprt0 |= HPRT0_RES;
+-	hprt0 &= ~HPRT0_SUSP;
+-	dwc2_writel(hsotg, hprt0, HPRT0);
+ 	spin_unlock_irqrestore(&hsotg->lock, flags);
+ 
+-	msleep(USB_RESUME_TIMEOUT);
+-
+-	spin_lock_irqsave(&hsotg->lock, flags);
+-	hprt0 = dwc2_read_hprt0(hsotg);
+-	hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
+-	dwc2_writel(hsotg, hprt0, HPRT0);
+-	hsotg->bus_suspended = false;
+-	spin_unlock_irqrestore(&hsotg->lock, flags);
++	return ret;
+ }
+ 
+ /* Handles hub class-specific requests */
+@@ -3375,7 +3422,6 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
+ 	u32 hprt0;
+ 	u32 port_status;
+ 	u32 speed;
+-	u32 pcgctl;
+ 	u32 pwr;
+ 
+ 	switch (typereq) {
+@@ -3413,12 +3459,8 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
+ 			dev_dbg(hsotg->dev,
+ 				"ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
+ 
+-			if (hsotg->bus_suspended) {
+-				if (hsotg->hibernated)
+-					dwc2_exit_hibernation(hsotg, 0, 0, 1);
+-				else
+-					dwc2_port_resume(hsotg);
+-			}
++			if (hsotg->bus_suspended)
++				retval = dwc2_port_resume(hsotg);
+ 			break;
+ 
+ 		case USB_PORT_FEAT_POWER:
+@@ -3629,10 +3671,8 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
+ 				"SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
+ 			if (windex != hsotg->otg_port)
+ 				goto error;
+-			if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_HIBERNATION)
+-				dwc2_enter_hibernation(hsotg, 1);
+-			else
+-				dwc2_port_suspend(hsotg, windex);
++			if (!hsotg->bus_suspended)
++				retval = dwc2_port_suspend(hsotg, windex);
+ 			break;
+ 
+ 		case USB_PORT_FEAT_POWER:
+@@ -3647,17 +3687,29 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
+ 			break;
+ 
+ 		case USB_PORT_FEAT_RESET:
+-			if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_HIBERNATION &&
+-			    hsotg->hibernated)
+-				dwc2_exit_hibernation(hsotg, 0, 1, 1);
+-			hprt0 = dwc2_read_hprt0(hsotg);
+ 			dev_dbg(hsotg->dev,
+ 				"SetPortFeature - USB_PORT_FEAT_RESET\n");
+-			pcgctl = dwc2_readl(hsotg, PCGCTL);
+-			pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
+-			dwc2_writel(hsotg, pcgctl, PCGCTL);
+-			/* ??? Original driver does this */
+-			dwc2_writel(hsotg, 0, PCGCTL);
++
++			hprt0 = dwc2_read_hprt0(hsotg);
++
++			if (hsotg->hibernated) {
++				retval = dwc2_exit_hibernation(hsotg, 0, 1, 1);
++				if (retval)
++					dev_err(hsotg->dev,
++						"exit hibernation failed\n");
++			}
++
++			if (hsotg->in_ppd) {
++				retval = dwc2_exit_partial_power_down(hsotg, 1,
++								      true);
++				if (retval)
++					dev_err(hsotg->dev,
++						"exit partial_power_down failed\n");
++			}
++
++			if (hsotg->params.power_down ==
++			    DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended)
++				dwc2_host_exit_clock_gating(hsotg, 0);
+ 
+ 			hprt0 = dwc2_read_hprt0(hsotg);
+ 			pwr = hprt0 & HPRT0_PWR;
+@@ -4305,8 +4357,6 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
+ 	struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
+ 	unsigned long flags;
+ 	int ret = 0;
+-	u32 hprt0;
+-	u32 pcgctl;
+ 
+ 	spin_lock_irqsave(&hsotg->lock, flags);
+ 
+@@ -4322,47 +4372,43 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
+ 	if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
+ 		goto unlock;
+ 
+-	if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL ||
+-	    hsotg->flags.b.port_connect_status == 0)
++	if (hsotg->bus_suspended)
+ 		goto skip_power_saving;
+ 
+-	/*
+-	 * Drive USB suspend and disable port Power
+-	 * if usb bus is not suspended.
+-	 */
+-	if (!hsotg->bus_suspended) {
+-		hprt0 = dwc2_read_hprt0(hsotg);
+-		if (hprt0 & HPRT0_CONNSTS) {
+-			hprt0 |= HPRT0_SUSP;
+-			if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL)
+-				hprt0 &= ~HPRT0_PWR;
+-			dwc2_writel(hsotg, hprt0, HPRT0);
+-		}
+-		if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
+-			spin_unlock_irqrestore(&hsotg->lock, flags);
+-			dwc2_vbus_supply_exit(hsotg);
+-			spin_lock_irqsave(&hsotg->lock, flags);
+-		} else {
+-			pcgctl = readl(hsotg->regs + PCGCTL);
+-			pcgctl |= PCGCTL_STOPPCLK;
+-			writel(pcgctl, hsotg->regs + PCGCTL);
+-		}
+-	}
++	if (hsotg->flags.b.port_connect_status == 0)
++		goto skip_power_saving;
+ 
+-	if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
++	switch (hsotg->params.power_down) {
++	case DWC2_POWER_DOWN_PARAM_PARTIAL:
+ 		/* Enter partial_power_down */
+ 		ret = dwc2_enter_partial_power_down(hsotg);
+-		if (ret) {
+-			if (ret != -ENOTSUPP)
+-				dev_err(hsotg->dev,
+-					"enter partial_power_down failed\n");
+-			goto skip_power_saving;
+-		}
+-
+-		/* After entering partial_power_down, hardware is no more accessible */
+-		clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
++		if (ret)
++			dev_err(hsotg->dev,
++				"enter partial_power_down failed\n");
++		break;
++	case DWC2_POWER_DOWN_PARAM_HIBERNATION:
++		/* Enter hibernation */
++		spin_unlock_irqrestore(&hsotg->lock, flags);
++		ret = dwc2_enter_hibernation(hsotg, 1);
++		if (ret)
++			dev_err(hsotg->dev, "enter hibernation failed\n");
++		spin_lock_irqsave(&hsotg->lock, flags);
++		break;
++	case DWC2_POWER_DOWN_PARAM_NONE:
++		/*
++		 * If not hibernation nor partial power down are supported,
++		 * clock gating is used to save power.
++		 */
++		dwc2_host_enter_clock_gating(hsotg);
++		break;
++	default:
++		goto skip_power_saving;
+ 	}
+ 
++	spin_unlock_irqrestore(&hsotg->lock, flags);
++	dwc2_vbus_supply_exit(hsotg);
++	spin_lock_irqsave(&hsotg->lock, flags);
++
+ 	/* Ask phy to be suspended */
+ 	if (!IS_ERR_OR_NULL(hsotg->uphy)) {
+ 		spin_unlock_irqrestore(&hsotg->lock, flags);
+@@ -4382,7 +4428,6 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd)
+ {
+ 	struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
+ 	unsigned long flags;
+-	u32 pcgctl;
+ 	int ret = 0;
+ 
+ 	spin_lock_irqsave(&hsotg->lock, flags);
+@@ -4393,11 +4438,53 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd)
+ 	if (hsotg->lx_state != DWC2_L2)
+ 		goto unlock;
+ 
+-	if (hsotg->params.power_down > DWC2_POWER_DOWN_PARAM_PARTIAL) {
++	/*
++		if (dwc2_read_hprt0(hsotg) & HPRT0_CONNSTS) dont use.
++		GOTGCTL_VBVALOEN is setting when external_vbus_detect mode, so dont use HPRT0_CONNSTS to judge Port Connect Status.
++		use vbus_supply_enabled flag to judge Port Connect Status.
++	*/
++	if (hsotg->vbus_supply_enabled) {
+ 		hsotg->lx_state = DWC2_L0;
+ 		goto unlock;
+ 	}
+ 
++	switch (hsotg->params.power_down) {
++	case DWC2_POWER_DOWN_PARAM_PARTIAL:
++		ret = dwc2_exit_partial_power_down(hsotg, 0, true);
++		if (ret)
++			dev_err(hsotg->dev,
++				"exit partial_power_down failed\n");
++		break;
++	case DWC2_POWER_DOWN_PARAM_HIBERNATION:
++		ret = dwc2_exit_hibernation(hsotg, 0, 0, 1);
++		if (ret)
++			dev_err(hsotg->dev, "exit hibernation failed.\n");
++		break;
++	case DWC2_POWER_DOWN_PARAM_NONE:
++		/*
++		 * If not hibernation nor partial power down are supported,
++		 * port resume is done using the clock gating programming flow.
++		 */
++		spin_unlock_irqrestore(&hsotg->lock, flags);
++		dwc2_host_exit_clock_gating(hsotg, 0);
++
++		/*
++		 * Initialize the Core for Host mode, as after system resume
++		 * the global interrupts are disabled.
++		 */
++		dwc2_core_init(hsotg, false);
++		dwc2_enable_global_interrupts(hsotg);
++		dwc2_hcd_reinit(hsotg);
++		spin_lock_irqsave(&hsotg->lock, flags);
++		break;
++	default:
++		hsotg->lx_state = DWC2_L0;
++		goto unlock;
++	}
++
++	/* Change Root port status, as port status change occurred after resume.*/
++	hsotg->flags.b.port_suspend_change = 1;
++
+ 	/*
+ 	 * Enable power if not already done.
+ 	 * This must not be spinlocked since duration
+@@ -4409,52 +4496,25 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd)
+ 		spin_lock_irqsave(&hsotg->lock, flags);
+ 	}
+ 
+-	if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
+-		/*
+-		 * Set HW accessible bit before powering on the controller
+-		 * since an interrupt may rise.
+-		 */
+-		set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+-
+-
+-		/* Exit partial_power_down */
+-		ret = dwc2_exit_partial_power_down(hsotg, true);
+-		if (ret && (ret != -ENOTSUPP))
+-			dev_err(hsotg->dev, "exit partial_power_down failed\n");
+-	} else {
+-		pcgctl = readl(hsotg->regs + PCGCTL);
+-		pcgctl &= ~PCGCTL_STOPPCLK;
+-		writel(pcgctl, hsotg->regs + PCGCTL);
+-	}
+-
+-	hsotg->lx_state = DWC2_L0;
+-
++	/* Enable external vbus supply after resuming the port. */
+ 	spin_unlock_irqrestore(&hsotg->lock, flags);
++	dwc2_vbus_supply_init(hsotg);
+ 
+-	if (hsotg->bus_suspended) {
+-		spin_lock_irqsave(&hsotg->lock, flags);
+-		hsotg->flags.b.port_suspend_change = 1;
+-		spin_unlock_irqrestore(&hsotg->lock, flags);
+-		dwc2_port_resume(hsotg);
+-	} else {
+-		if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
+-			dwc2_vbus_supply_init(hsotg);
+-
+-			/* Wait for controller to correctly update D+/D- level */
+-			usleep_range(3000, 5000);
+-		}
++	/* Wait for controller to correctly update D+/D- level */
++	usleep_range(3000, 5000);
++	spin_lock_irqsave(&hsotg->lock, flags);
+ 
+-		/*
+-		 * Clear Port Enable and Port Status changes.
+-		 * Enable Port Power.
+-		 */
+-		dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET |
+-				HPRT0_ENACHG, HPRT0);
+-		/* Wait for controller to detect Port Connect */
+-		usleep_range(5000, 7000);
+-	}
++	/*
++	 * Clear Port Enable and Port Status changes.
++	 * Enable Port Power.
++	 */
++	dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET |
++			HPRT0_ENACHG, HPRT0);
+ 
+-	return ret;
++	/* Wait for controller to detect Port Connect */
++	spin_unlock_irqrestore(&hsotg->lock, flags);
++	usleep_range(5000, 7000);
++	spin_lock_irqsave(&hsotg->lock, flags);
+ unlock:
+ 	spin_unlock_irqrestore(&hsotg->lock, flags);
+ 
+@@ -4565,12 +4625,41 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
+ 	struct dwc2_qh *qh;
+ 	bool qh_allocated = false;
+ 	struct dwc2_qtd *qtd;
++	struct dwc2_gregs_backup *gr;
++
++	gr = &hsotg->gr_backup;
+ 
+ 	if (dbg_urb(urb)) {
+ 		dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
+ 		dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
+ 	}
+ 
++	if (hsotg->hibernated) {
++		if (gr->gotgctl & GOTGCTL_CURMODE_HOST)
++			retval = dwc2_exit_hibernation(hsotg, 0, 0, 1);
++		else
++			retval = dwc2_exit_hibernation(hsotg, 0, 0, 0);
++
++		if (retval)
++			dev_err(hsotg->dev,
++				"exit hibernation failed.\n");
++	}
++
++	if (hsotg->in_ppd) {
++		retval = dwc2_exit_partial_power_down(hsotg, 0, true);
++		if (retval)
++			dev_err(hsotg->dev,
++				"exit partial_power_down failed\n");
++	}
++
++	if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_NONE &&
++	    hsotg->bus_suspended) {
++		if (dwc2_is_device_mode(hsotg))
++			dwc2_gadget_exit_clock_gating(hsotg, 0);
++		else
++			dwc2_host_exit_clock_gating(hsotg, 0);
++	}
++
+ 	if (!ep)
+ 		return -EINVAL;
+ 
+@@ -5378,7 +5467,6 @@ int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
+ 	unsigned long flags;
+ 	int ret = 0;
+ 	u32 hprt0;
+-	u32 pcgcctl;
+ 	u32 gusbcfg;
+ 	u32 gpwrdn;
+ 
+@@ -5416,12 +5504,6 @@ int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
+ 	gusbcfg = dwc2_readl(hsotg, GUSBCFG);
+ 	if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) {
+ 		/* ULPI interface */
+-		/* Suspend the Phy Clock */
+-		pcgcctl = dwc2_readl(hsotg, PCGCTL);
+-		pcgcctl |= PCGCTL_STOPPCLK;
+-		dwc2_writel(hsotg, pcgcctl, PCGCTL);
+-		udelay(10);
+-
+ 		gpwrdn = dwc2_readl(hsotg, GPWRDN);
+ 		gpwrdn |= GPWRDN_PMUACTV;
+ 		dwc2_writel(hsotg, gpwrdn, GPWRDN);
+@@ -5432,11 +5514,6 @@ int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
+ 		gpwrdn |= GPWRDN_PMUACTV;
+ 		dwc2_writel(hsotg, gpwrdn, GPWRDN);
+ 		udelay(10);
+-
+-		pcgcctl = dwc2_readl(hsotg, PCGCTL);
+-		pcgcctl |= PCGCTL_STOPPCLK;
+-		dwc2_writel(hsotg, pcgcctl, PCGCTL);
+-		udelay(10);
+ 	}
+ 
+ 	/* Enable interrupts from wake up logic */
+@@ -5619,3 +5696,192 @@ bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
+ 	/* No reason to keep the PHY powered, so allow poweroff */
+ 	return true;
+ }
++
++/**
++ * dwc2_host_enter_partial_power_down() - Put controller in partial
++ * power down.
++ *
++ * @hsotg: Programming view of the DWC_otg controller
++ *
++ * Return: non-zero if failed to enter host partial power down.
++ *
++ * This function is for entering Host mode partial power down.
++ */
++int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg)
++{
++	u32 hprt0;
++	int ret = 0;
++
++	dev_dbg(hsotg->dev, "Entering host partial power down started.\n");
++
++	/* Put this port in suspend mode. */
++	hprt0 = dwc2_read_hprt0(hsotg);
++	hprt0 |= HPRT0_SUSP;
++	dwc2_writel(hsotg, hprt0, HPRT0);
++	udelay(5);
++
++	/* Wait for the HPRT0.PrtSusp register field to be set */
++	if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 3000))
++		dev_warn(hsotg->dev, "Suspend wasn't generated\n");
++
++	/* Backup all registers */
++	ret = dwc2_backup_global_registers(hsotg);
++	if (ret) {
++		dev_err(hsotg->dev, "%s: failed to backup global registers\n",
++			__func__);
++		return ret;
++	}
++
++	ret = dwc2_backup_host_registers(hsotg);
++	if (ret) {
++		dev_err(hsotg->dev, "%s: failed to backup host registers\n",
++			__func__);
++		return ret;
++	}
++
++	/*
++	 * Clear any pending interrupts since dwc2 will not be able to
++	 * clear them after entering partial_power_down.
++	 */
++	dwc2_writel(hsotg, 0xffffffff, GINTSTS);
++
++	/* Set in_ppd flag to 1 as here core enters suspend. */
++	hsotg->in_ppd = 1;
++	hsotg->lx_state = DWC2_L2;
++	hsotg->bus_suspended = true;
++
++	dev_dbg(hsotg->dev, "Entering host partial power down completed.\n");
++
++	return ret;
++}
++
++/*
++ * dwc2_host_exit_partial_power_down() - Exit controller from host partial
++ * power down.
++ *
++ * @hsotg: Programming view of the DWC_otg controller
++ * @rem_wakeup: indicates whether resume is initiated by Reset.
++ * @restore: indicates whether need to restore the registers or not.
++ *
++ * Return: non-zero if failed to exit host partial power down.
++ *
++ * This function is for exiting from Host mode partial power down.
++ */
++int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg,
++				      int rem_wakeup, bool restore)
++{
++	int ret = 0;
++	u32 hprt0;
++
++	dev_dbg(hsotg->dev, "Exiting host partial power down started.\n");
++
++	if (restore) {
++		ret = dwc2_restore_global_registers(hsotg);
++		if (ret) {
++			dev_err(hsotg->dev, "%s: failed to restore registers\n",
++				__func__);
++			return ret;
++		}
++
++		ret = dwc2_restore_host_registers(hsotg);
++		if (ret) {
++			dev_err(hsotg->dev, "%s: failed to restore host registers\n",
++				__func__);
++			return ret;
++		}
++	}
++
++	/* Drive resume signaling and exit suspend mode on the port. */
++	hprt0 = dwc2_read_hprt0(hsotg);
++	hprt0 |= HPRT0_RES;
++	hprt0 &= ~HPRT0_SUSP;
++	dwc2_writel(hsotg, hprt0, HPRT0);
++	udelay(5);
++
++	if (!rem_wakeup) {
++		/* Stop driveing resume signaling on the port. */
++		hprt0 = dwc2_read_hprt0(hsotg);
++		hprt0 &= ~HPRT0_RES;
++		dwc2_writel(hsotg, hprt0, HPRT0);
++
++		hsotg->bus_suspended = false;
++	} else {
++		/* Turn on the port power bit. */
++		hprt0 = dwc2_read_hprt0(hsotg);
++		hprt0 |= HPRT0_PWR;
++		dwc2_writel(hsotg, hprt0, HPRT0);
++
++		/* Connect hcd. */
++		dwc2_hcd_connect(hsotg);
++
++		mod_timer(&hsotg->wkp_timer,
++			  jiffies + msecs_to_jiffies(71));
++	}
++
++	/* Set lx_state to and in_ppd to 0 as here core exits from suspend. */
++	hsotg->in_ppd = 0;
++	hsotg->lx_state = DWC2_L0;
++
++	dev_dbg(hsotg->dev, "Exiting host partial power down completed.\n");
++	return ret;
++}
++
++/**
++ * dwc2_host_enter_clock_gating() - Put controller in clock gating.
++ *
++ * @hsotg: Programming view of the DWC_otg controller
++ *
++ * This function is for entering Host mode clock gating.
++ */
++void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg)
++{
++	u32 hprt0;
++
++	dev_dbg(hsotg->dev, "Entering host clock gating.\n");
++
++	/* Put this port in suspend mode. */
++	hprt0 = dwc2_read_hprt0(hsotg);
++	hprt0 |= HPRT0_SUSP;
++	dwc2_writel(hsotg, hprt0, HPRT0);
++
++	hsotg->bus_suspended = true;
++	hsotg->lx_state = DWC2_L2;
++}
++
++/**
++ * dwc2_host_exit_clock_gating() - Exit controller from clock gating.
++ *
++ * @hsotg: Programming view of the DWC_otg controller
++ * @rem_wakeup: indicates whether resume is initiated by remote wakeup
++ *
++ * This function is for exiting Host mode clock gating.
++ */
++void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup)
++{
++	u32 hprt0;
++
++	dev_dbg(hsotg->dev, "Exiting host clock gating.\n");
++
++	/* Drive resume signaling and exit suspend mode on the port. */
++	hprt0 = dwc2_read_hprt0(hsotg);
++	hprt0 |= HPRT0_RES;
++	hprt0 &= ~HPRT0_SUSP;
++	dwc2_writel(hsotg, hprt0, HPRT0);
++	udelay(5);
++
++	if (!rem_wakeup) {
++		/* In case of port resume need to wait for 40 ms */
++		msleep(USB_RESUME_TIMEOUT);
++
++		/* Stop driveing resume signaling on the port. */
++		hprt0 = dwc2_read_hprt0(hsotg);
++		hprt0 &= ~HPRT0_RES;
++		dwc2_writel(hsotg, hprt0, HPRT0);
++
++		hsotg->bus_suspended = false;
++		hsotg->lx_state = DWC2_L0;
++	} else {
++		mod_timer(&hsotg->wkp_timer,
++			  jiffies + msecs_to_jiffies(71));
++	}
++}
+diff --git a/drivers/usb/dwc2/hcd_queue.c b/drivers/usb/dwc2/hcd_queue.c
+index 94af71e98..24beff610 100644
+--- a/drivers/usb/dwc2/hcd_queue.c
++++ b/drivers/usb/dwc2/hcd_queue.c
+@@ -675,7 +675,7 @@ static int dwc2_hs_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
+ }
+ 
+ /**
+- * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_hs_pmap_schedule()
++ * dwc2_hs_pmap_unschedule() - Undo work done by dwc2_hs_pmap_schedule()
+  *
+  * @hsotg:       The HCD state structure for the DWC OTG controller.
+  * @qh:          QH for the periodic transfer.
+diff --git a/drivers/usb/dwc2/hw.h b/drivers/usb/dwc2/hw.h
+index c3d6dde2a..1cc216ebd 100644
+--- a/drivers/usb/dwc2/hw.h
++++ b/drivers/usb/dwc2/hw.h
+@@ -44,6 +44,7 @@
+ #define GOTGCTL_CHIRPEN			BIT(27)
+ #define GOTGCTL_MULT_VALID_BC_MASK	(0x1f << 22)
+ #define GOTGCTL_MULT_VALID_BC_SHIFT	22
++#define GOTGCTL_CURMODE_HOST		BIT(21)
+ #define GOTGCTL_OTGVER			BIT(20)
+ #define GOTGCTL_BSESVLD			BIT(19)
+ #define GOTGCTL_ASESVLD			BIT(18)
+@@ -648,38 +649,6 @@
+ 
+ #define DTXFSTS(_a)			HSOTG_REG(0x918 + ((_a) * 0x20))
+ 
+-#define PCGCTL				HSOTG_REG(0x0e00)
+-#define PCGCTL_IF_DEV_MODE		BIT(31)
+-#define PCGCTL_P2HD_PRT_SPD_MASK	(0x3 << 29)
+-#define PCGCTL_P2HD_PRT_SPD_SHIFT	29
+-#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK	(0x3 << 27)
+-#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT	27
+-#define PCGCTL_MAC_DEV_ADDR_MASK	(0x7f << 20)
+-#define PCGCTL_MAC_DEV_ADDR_SHIFT	20
+-#define PCGCTL_MAX_TERMSEL		BIT(19)
+-#define PCGCTL_MAX_XCVRSELECT_MASK	(0x3 << 17)
+-#define PCGCTL_MAX_XCVRSELECT_SHIFT	17
+-#define PCGCTL_PORT_POWER		BIT(16)
+-#define PCGCTL_PRT_CLK_SEL_MASK		(0x3 << 14)
+-#define PCGCTL_PRT_CLK_SEL_SHIFT	14
+-#define PCGCTL_ESS_REG_RESTORED		BIT(13)
+-#define PCGCTL_EXTND_HIBER_SWITCH	BIT(12)
+-#define PCGCTL_EXTND_HIBER_PWRCLMP	BIT(11)
+-#define PCGCTL_ENBL_EXTND_HIBER		BIT(10)
+-#define PCGCTL_RESTOREMODE		BIT(9)
+-#define PCGCTL_RESETAFTSUSP		BIT(8)
+-#define PCGCTL_DEEP_SLEEP		BIT(7)
+-#define PCGCTL_PHY_IN_SLEEP		BIT(6)
+-#define PCGCTL_ENBL_SLEEP_GATING	BIT(5)
+-#define PCGCTL_RSTPDWNMODULE		BIT(3)
+-#define PCGCTL_PWRCLMP			BIT(2)
+-#define PCGCTL_GATEHCLK			BIT(1)
+-#define PCGCTL_STOPPCLK			BIT(0)
+-
+-#define PCGCCTL1                        HSOTG_REG(0xe04)
+-#define PCGCCTL1_TIMER                  (0x3 << 1)
+-#define PCGCCTL1_GATEEN                 BIT(0)
+-
+ #define EPFIFO(_a)			HSOTG_REG(0x1000 + ((_a) * 0x1000))
+ 
+ /* Host Mode Registers */
+diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
+index 267543c3d..0850a6669 100644
+--- a/drivers/usb/dwc2/params.c
++++ b/drivers/usb/dwc2/params.c
+@@ -39,210 +39,65 @@
+ 
+ #include "core.h"
+ 
+-static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
+-{
+-	struct dwc2_core_params *p = &hsotg->params;
+-
+-	p->host_rx_fifo_size = 774;
+-	p->max_transfer_size = 65535;
+-	p->max_packet_count = 511;
+-	p->ahbcfg = 0x10;
+-}
+-
+-static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
+-{
+-	struct dwc2_core_params *p = &hsotg->params;
+-
+-	p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
+-	p->speed = DWC2_SPEED_PARAM_HIGH;
+-	p->host_rx_fifo_size = 512;
+-	p->host_nperio_tx_fifo_size = 512;
+-	p->host_perio_tx_fifo_size = 512;
+-	p->max_transfer_size = 65535;
+-	p->max_packet_count = 511;
+-	p->host_channels = 16;
+-	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
+-	p->phy_utmi_width = 8;
+-	p->i2c_enable = false;
+-	p->reload_ctl = false;
+-	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
+-		GAHBCFG_HBSTLEN_SHIFT;
+-	p->change_speed_quirk = true;
+-	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+-}
+-
+-static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
+-{
+-	struct dwc2_core_params *p = &hsotg->params;
+-
+-	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+-	p->phy_utmi_width = 8;
+-}
+-
+-static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
+-{
+-	struct dwc2_core_params *p = &hsotg->params;
+-
+-	p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
+-	p->host_rx_fifo_size = 525;
+-	p->host_nperio_tx_fifo_size = 128;
+-	p->host_perio_tx_fifo_size = 256;
+-	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
+-		GAHBCFG_HBSTLEN_SHIFT;
+-	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+-}
+-
+-static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
+-{
+-	struct dwc2_core_params *p = &hsotg->params;
+-
+-	p->otg_cap = 2;
+-	p->host_rx_fifo_size = 288;
+-	p->host_nperio_tx_fifo_size = 128;
+-	p->host_perio_tx_fifo_size = 96;
+-	p->max_transfer_size = 65535;
+-	p->max_packet_count = 511;
+-	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
+-		GAHBCFG_HBSTLEN_SHIFT;
+-}
+-
+-static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
+-{
+-	struct dwc2_core_params *p = &hsotg->params;
+-
+-	p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
+-	p->speed = DWC2_SPEED_PARAM_HIGH;
+-	p->host_rx_fifo_size = 512;
+-	p->host_nperio_tx_fifo_size = 500;
+-	p->host_perio_tx_fifo_size = 500;
+-	p->host_channels = 16;
+-	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
+-	p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
+-		GAHBCFG_HBSTLEN_SHIFT;
+-	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+-}
+-
+-static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg)
+-{
+-	struct dwc2_core_params *p = &hsotg->params;
+-
+-	p->lpm = false;
+-	p->lpm_clock_gating = false;
+-	p->besl = false;
+-	p->hird_threshold_en = false;
+-}
+-
+-static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
++static void dwc2_set_hsotg_params(struct dwc2_hsotg *hsotg)
+ {
+ 	struct dwc2_core_params *p = &hsotg->params;
+ 
+ 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
+-}
+ 
+-static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
+-{
+-	struct dwc2_core_params *p = &hsotg->params;
++	p->otg_caps.otg_rev = 0x200;
+ 
+-	p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
+-	p->speed = DWC2_SPEED_PARAM_FULL;
+-	p->host_rx_fifo_size = 128;
+-	p->host_nperio_tx_fifo_size = 96;
+-	p->host_perio_tx_fifo_size = 96;
+-	p->max_packet_count = 256;
+-	p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
+-	p->i2c_enable = false;
+-	p->activate_stm_fs_transceiver = true;
+-}
++	p->host_rx_fifo_size = 1528;
++	p->host_nperio_tx_fifo_size = 1024;
++	p->host_perio_tx_fifo_size = 1024;
+ 
+-static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
+-{
+-	struct dwc2_core_params *p = &hsotg->params;
++#ifdef CONFIG_USB_DWC2_EXT_ID_PIN
++	p->external_id_pin_ctl = true;
++#endif
+ 
+-	p->host_rx_fifo_size = 622;
+-	p->host_nperio_tx_fifo_size = 128;
+-	p->host_perio_tx_fifo_size = 256;
+-}
++#ifdef CONFIG_USB_DWC2_EXT_VBUS_DETECT
++	p->external_vbus_detect = true;
++#endif
+ 
+-static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
+-{
+-	struct dwc2_core_params *p = &hsotg->params;
+-
+-	p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
++#ifdef CONFIG_USB_DWC2_FORCE_FULL_SPEED
+ 	p->speed = DWC2_SPEED_PARAM_FULL;
+-	p->host_rx_fifo_size = 128;
+-	p->host_nperio_tx_fifo_size = 96;
+-	p->host_perio_tx_fifo_size = 96;
+-	p->max_packet_count = 256;
+-	p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
+-	p->i2c_enable = false;
+-	p->activate_stm_fs_transceiver = true;
+-	p->activate_stm_id_vb_detection = true;
+-	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+-}
+-
+-static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
+-{
+-	struct dwc2_core_params *p = &hsotg->params;
+-
+-	p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
+-	p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch");
+-	p->host_rx_fifo_size = 440;
+-	p->host_nperio_tx_fifo_size = 256;
+-	p->host_perio_tx_fifo_size = 256;
+-	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
++#endif
+ }
+ 
+ const struct of_device_id dwc2_of_match_table[] = {
+-	{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
+-	{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params  },
+-	{ .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
+-	{ .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
+-	{ .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
+ 	{ .compatible = "snps,dwc2" },
+-	{ .compatible = "samsung,s3c6400-hsotg",
+-	  .data = dwc2_set_s3c6400_params },
+-	{ .compatible = "amlogic,meson8-usb",
+-	  .data = dwc2_set_amlogic_params },
+-	{ .compatible = "amlogic,meson8b-usb",
+-	  .data = dwc2_set_amlogic_params },
+-	{ .compatible = "amlogic,meson-gxbb-usb",
+-	  .data = dwc2_set_amlogic_params },
+-	{ .compatible = "amlogic,meson-g12a-usb",
+-	  .data = dwc2_set_amlogic_g12a_params },
+-	{ .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
+-	{ .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
+-	{ .compatible = "st,stm32f4x9-fsotg",
+-	  .data = dwc2_set_stm32f4x9_fsotg_params },
+-	{ .compatible = "st,stm32f4x9-hsotg" },
+-	{ .compatible = "st,stm32f7-hsotg",
+-	  .data = dwc2_set_stm32f7_hsotg_params },
+-	{ .compatible = "st,stm32mp15-fsotg",
+-	  .data = dwc2_set_stm32mp15_fsotg_params },
+-	{ .compatible = "st,stm32mp15-hsotg",
+-	  .data = dwc2_set_stm32mp15_hsotg_params },
++	{ .compatible = "ingenic,x1000-dwc2-hsotg",
++	  .data = dwc2_set_hsotg_params },
++	{ .compatible = "ingenic,x1600-dwc2-hsotg",
++	  .data = dwc2_set_hsotg_params },
++	{ .compatible = "ingenic,x2000-dwc2-hsotg",
++	  .data = dwc2_set_hsotg_params },
++	{ .compatible = "ingenic,x2500-dwc2-hsotg",
++	  .data = dwc2_set_hsotg_params },
++	{ .compatible = "ingenic,m300-dwc2-hsotg",
++	  .data = dwc2_set_hsotg_params },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
+ 
+ static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
+ {
+-	u8 val;
+-
+ 	switch (hsotg->hw_params.op_mode) {
+ 	case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
+-		val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
++		hsotg->params.otg_caps.hnp_support = true;
++		hsotg->params.otg_caps.srp_support = true;
+ 		break;
+ 	case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
+ 	case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
+ 	case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
+-		val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
++		hsotg->params.otg_caps.hnp_support = false;
++		hsotg->params.otg_caps.srp_support = true;
+ 		break;
+ 	default:
+-		val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
++		hsotg->params.otg_caps.hnp_support = false;
++		hsotg->params.otg_caps.srp_support = false;
+ 		break;
+ 	}
+-
+-	hsotg->params.otg_cap = val;
+ }
+ 
+ static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
+@@ -412,8 +267,8 @@ static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
+ 		 * auto-detect if the hardware does not support the
+ 		 * default.
+ 		 */
+-		p->g_rx_fifo_size = 2048;
+-		p->g_np_tx_fifo_size = 1024;
++		p->g_rx_fifo_size = 768;
++		p->g_np_tx_fifo_size = 256;
+ 		dwc2_set_param_tx_fifo_sizes(hsotg);
+ 	}
+ }
+@@ -452,35 +307,47 @@ static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
+ 
+ 	if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL))
+ 		p->oc_disable = true;
++
++	if (of_find_property(hsotg->dev->of_node, "force-full-speed", NULL))
++		p->speed = DWC2_SPEED_PARAM_FULL;
++
++	if (of_find_property(hsotg->dev->of_node, "external-id-pin", NULL))
++		p->external_id_pin_ctl = true;
++
++	if (of_find_property(hsotg->dev->of_node, "external-vbus-detect", NULL))
++		p->external_vbus_detect = true;
++
++	if (of_find_property(hsotg->dev->of_node, "device-using-dma", NULL)) {
++		p->g_dma_desc = false;
++		p->g_dma =  true;
++	}
+ }
+ 
+ static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
+ {
+ 	int valid = 1;
+ 
+-	switch (hsotg->params.otg_cap) {
+-	case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
++	if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) {
++		/* check HNP && SRP capable */
+ 		if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
+ 			valid = 0;
+-		break;
+-	case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
+-		switch (hsotg->hw_params.op_mode) {
+-		case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
+-		case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
+-		case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
+-		case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
+-			break;
+-		default:
+-			valid = 0;
+-			break;
++	} else if (!hsotg->params.otg_caps.hnp_support) {
++		/* check SRP only capable */
++		if (hsotg->params.otg_caps.srp_support) {
++			switch (hsotg->hw_params.op_mode) {
++			case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
++			case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
++			case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
++			case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
++				break;
++			default:
++				valid = 0;
++				break;
++			}
+ 		}
+-		break;
+-	case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
+-		/* always valid */
+-		break;
+-	default:
++		/* else: NO HNP && NO SRP capable: always valid */
++	} else {
+ 		valid = 0;
+-		break;
+ 	}
+ 
+ 	if (!valid)
+diff --git a/drivers/usb/dwc2/pci.c b/drivers/usb/dwc2/pci.c
+index 7afc10872..0000151e3 100644
+--- a/drivers/usb/dwc2/pci.c
++++ b/drivers/usb/dwc2/pci.c
+@@ -63,20 +63,6 @@ struct dwc2_pci_glue {
+ 	struct platform_device *phy;
+ };
+ 
+-static int dwc2_pci_quirks(struct pci_dev *pdev, struct platform_device *dwc2)
+-{
+-	if (pdev->vendor == PCI_VENDOR_ID_SYNOPSYS &&
+-	    pdev->device == PCI_PRODUCT_ID_HAPS_HSOTG) {
+-		struct property_entry properties[] = {
+-			{ },
+-		};
+-
+-		return platform_device_add_properties(dwc2, properties);
+-	}
+-
+-	return 0;
+-}
+-
+ /**
+  * dwc2_pci_probe() - Provides the cleanup entry points for the DWC_otg PCI
+  * driver
+@@ -143,10 +129,6 @@ static int dwc2_pci_probe(struct pci_dev *pci,
+ 
+ 	dwc2->dev.parent = dev;
+ 
+-	ret = dwc2_pci_quirks(pci, dwc2);
+-	if (ret)
+-		goto err;
+-
+ 	glue = devm_kzalloc(dev, sizeof(*glue), GFP_KERNEL);
+ 	if (!glue) {
+ 		ret = -ENOMEM;
+diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
+index 49d333f02..6b88e5dd5 100644
+--- a/drivers/usb/dwc2/platform.c
++++ b/drivers/usb/dwc2/platform.c
+@@ -49,7 +49,6 @@
+ #include <linux/reset.h>
+ 
+ #include <linux/usb/of.h>
+-
+ #include "core.h"
+ #include "hcd.h"
+ #include "debug.h"
+@@ -281,7 +280,7 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
+ 	hsotg->plat = dev_get_platdata(hsotg->dev);
+ 
+ 	/* Clock */
+-	hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
++	hsotg->clk = devm_clk_get_optional(hsotg->dev, "gate_otg");
+ 	if (IS_ERR(hsotg->clk)) {
+ 		dev_err(hsotg->dev, "cannot get otg clock\n");
+ 		return PTR_ERR(hsotg->clk);
+@@ -299,6 +298,7 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
+ 				ret);
+ 		return ret;
+ 	}
++
+ 	return 0;
+ }
+ 
+@@ -316,6 +316,31 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
+ static int dwc2_driver_remove(struct platform_device *dev)
+ {
+ 	struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
++	struct dwc2_gregs_backup *gr;
++	int ret = 0;
++
++	gr = &hsotg->gr_backup;
++
++	/* Exit Hibernation when driver is removed. */
++	if (hsotg->hibernated) {
++		if (gr->gotgctl & GOTGCTL_CURMODE_HOST)
++			ret = dwc2_exit_hibernation(hsotg, 0, 0, 1);
++		else
++			ret = dwc2_exit_hibernation(hsotg, 0, 0, 0);
++
++		if (ret)
++			dev_err(hsotg->dev,
++				"exit hibernation failed.\n");
++	}
++
++	/* Exit clock gating when driver is removed. */
++	if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_NONE &&
++	    hsotg->bus_suspended) {
++		if (dwc2_is_device_mode(hsotg))
++			dwc2_gadget_exit_clock_gating(hsotg, 0);
++		else
++			dwc2_host_exit_clock_gating(hsotg, 0);
++	}
+ 
+ 	dwc2_debugfs_exit(hsotg);
+ 	if (hsotg->hcd_enabled)
+@@ -325,16 +350,13 @@ static int dwc2_driver_remove(struct platform_device *dev)
+ 
+ 	dwc2_drd_exit(hsotg);
+ 
+-	if (hsotg->params.activate_stm_id_vb_detection)
+-		regulator_disable(hsotg->usb33d);
+-
+ 	if (hsotg->ll_hw_enabled)
+ 		dwc2_lowlevel_hw_disable(hsotg);
+ 
+ 	reset_control_assert(hsotg->reset);
+ 	reset_control_assert(hsotg->reset_ecc);
+ 
+-	return 0;
++	return ret;
+ }
+ 
+ /**
+@@ -375,7 +397,7 @@ static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg)
+ }
+ 
+ /**
+- * Check core version
++ * dwc2_check_core_version() - Check core version
+  *
+  * @hsotg: Programming view of the DWC_otg controller
+  *
+@@ -405,6 +427,44 @@ int dwc2_check_core_version(struct dwc2_hsotg *hsotg)
+ 	return 0;
+ }
+ 
++static ssize_t show_id_status(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct dwc2_hsotg *hsotg = dev_get_drvdata(dev);
++	unsigned long gotgctl = dwc2_readl(hsotg, GOTGCTL);
++	return sprintf(buf, "%s\n", (gotgctl & GOTGCTL_CONID_B) ? "device" : "host");
++}
++
++static ssize_t dwc2_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	char *mode;
++	struct dwc2_hsotg *hsotg = dev_get_drvdata(dev);
++
++	if (hsotg->dr_mode == USB_DR_MODE_HOST) {
++		mode = "host";
++	} else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
++		mode = "peripheral";
++	} else {
++		mode = "otg";
++	}
++
++	return sprintf(buf, "%s\n", mode);
++}
++
++static DEVICE_ATTR(id_status, S_IRUGO, show_id_status, NULL);
++static DEVICE_ATTR(dwc2_mode, S_IRUGO, dwc2_mode_show, NULL);
++
++#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
++	IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
++static ssize_t show_connected(struct device *dev, struct device_attribute *attr, char *buf)
++{
++
++	struct dwc2_hsotg *hsotg = dev_get_drvdata(dev);
++	return sprintf(buf, "%s\n", hsotg->connected ? "connect" : "disconnect");
++}
++
++static DEVICE_ATTR(connected, S_IRUGO, show_connected, NULL);
++#endif /* CONFIG_USB_DWC2_NEW_PERIPHERAL || CONFIG_USB_DWC2_NEW_DUAL_ROLE */
++
+ /**
+  * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
+  * driver
+@@ -519,39 +579,11 @@ static int dwc2_driver_probe(struct platform_device *dev)
+ 	if (retval)
+ 		goto error;
+ 
+-	if (hsotg->params.activate_stm_id_vb_detection) {
+-		u32 ggpio;
+-
+-		hsotg->usb33d = devm_regulator_get(hsotg->dev, "usb33d");
+-		if (IS_ERR(hsotg->usb33d)) {
+-			retval = PTR_ERR(hsotg->usb33d);
+-			if (retval != -EPROBE_DEFER)
+-				dev_err(hsotg->dev,
+-					"failed to request usb33d supply: %d\n",
+-					retval);
+-			goto error;
+-		}
+-		retval = regulator_enable(hsotg->usb33d);
+-		if (retval) {
+-			dev_err(hsotg->dev,
+-				"failed to enable usb33d supply: %d\n", retval);
+-			goto error;
+-		}
+-
+-		ggpio = dwc2_readl(hsotg, GGPIO);
+-		ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
+-		ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
+-		dwc2_writel(hsotg, ggpio, GGPIO);
+-
+-		/* ID/VBUS detection startup time */
+-		usleep_range(5000, 7000);
+-	}
+-
+ 	retval = dwc2_drd_init(hsotg);
+ 	if (retval) {
+ 		if (retval != -EPROBE_DEFER)
+ 			dev_err(hsotg->dev, "failed to initialize dual-role\n");
+-		goto error_init;
++		goto error;
+ 	}
+ 
+ 	if (hsotg->dr_mode != USB_DR_MODE_HOST) {
+@@ -597,8 +629,12 @@ static int dwc2_driver_probe(struct platform_device *dev)
+ 	if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
+ 		dwc2_lowlevel_hw_disable(hsotg);
+ 
++	device_create_file(hsotg->dev, &dev_attr_id_status);
++	device_create_file(hsotg->dev, &dev_attr_dwc2_mode);
++
+ #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
+ 	IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
++	device_create_file(hsotg->dev, &dev_attr_connected);
+ 	/* Postponed adding a new gadget to the udc class driver list */
+ 	if (hsotg->gadget_enabled) {
+ 		retval = usb_add_gadget_udc(hsotg->dev, &hsotg->gadget);
+@@ -620,10 +656,6 @@ static int dwc2_driver_probe(struct platform_device *dev)
+ #endif
+ error_drd:
+ 	dwc2_drd_exit(hsotg);
+-
+-error_init:
+-	if (hsotg->params.activate_stm_id_vb_detection)
+-		regulator_disable(hsotg->usb33d);
+ error:
+ 	if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL)
+ 		dwc2_lowlevel_hw_disable(hsotg);
+@@ -633,51 +665,23 @@ static int dwc2_driver_probe(struct platform_device *dev)
+ static int __maybe_unused dwc2_suspend(struct device *dev)
+ {
+ 	struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
+-	bool is_device_mode = dwc2_is_device_mode(dwc2);
+ 	int ret = 0;
+ 
+-	if (is_device_mode)
++#if 0 /* not close endpoint and disconnet */
++	if (dwc2_is_device_mode(dwc2))
+ 		dwc2_hsotg_suspend(dwc2);
++#endif
+ 
+-	dwc2_drd_suspend(dwc2);
+-
+-	if (dwc2->params.activate_stm_id_vb_detection) {
+-		unsigned long flags;
+-		u32 ggpio, gotgctl;
+-
+-		/*
+-		 * Need to force the mode to the current mode to avoid Mode
+-		 * Mismatch Interrupt when ID detection will be disabled.
+-		 */
+-		dwc2_force_mode(dwc2, !is_device_mode);
+-
+-		spin_lock_irqsave(&dwc2->lock, flags);
+-		gotgctl = dwc2_readl(dwc2, GOTGCTL);
+-		/* bypass debounce filter, enable overrides */
+-		gotgctl |= GOTGCTL_DBNCE_FLTR_BYPASS;
+-		gotgctl |= GOTGCTL_BVALOEN | GOTGCTL_AVALOEN;
+-		/* Force A / B session if needed */
+-		if (gotgctl & GOTGCTL_ASESVLD)
+-			gotgctl |= GOTGCTL_AVALOVAL;
+-		if (gotgctl & GOTGCTL_BSESVLD)
+-			gotgctl |= GOTGCTL_BVALOVAL;
+-		dwc2_writel(dwc2, gotgctl, GOTGCTL);
+-		spin_unlock_irqrestore(&dwc2->lock, flags);
+-
+-		ggpio = dwc2_readl(dwc2, GGPIO);
+-		ggpio &= ~GGPIO_STM32_OTG_GCCFG_IDEN;
+-		ggpio &= ~GGPIO_STM32_OTG_GCCFG_VBDEN;
+-		dwc2_writel(dwc2, ggpio, GGPIO);
+-
+-		regulator_disable(dwc2->usb33d);
+-	}
++	usb_phy_set_wakeup(dwc2->uphy, true);
+ 
+-	if (dwc2->ll_hw_enabled &&
+-	    (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) {
++	if (dwc2->ll_hw_enabled && !dwc2->need_phy_for_wake) {
+ 		ret = __dwc2_lowlevel_hw_disable(dwc2);
+ 		dwc2->phy_off_for_suspend = true;
+ 	}
+ 
++	if (dwc2->need_phy_for_wake)
++		enable_irq_wake(dwc2->irq);
++
+ 	return ret;
+ }
+ 
+@@ -686,6 +690,9 @@ static int __maybe_unused dwc2_resume(struct device *dev)
+ 	struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
+ 	int ret = 0;
+ 
++	if (dwc2->need_phy_for_wake)
++		disable_irq_wake(dwc2->irq);
++
+ 	if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) {
+ 		ret = __dwc2_lowlevel_hw_enable(dwc2);
+ 		if (ret)
+@@ -693,38 +700,12 @@ static int __maybe_unused dwc2_resume(struct device *dev)
+ 	}
+ 	dwc2->phy_off_for_suspend = false;
+ 
+-	if (dwc2->params.activate_stm_id_vb_detection) {
+-		unsigned long flags;
+-		u32 ggpio, gotgctl;
+-
+-		ret = regulator_enable(dwc2->usb33d);
+-		if (ret)
+-			return ret;
+-
+-		ggpio = dwc2_readl(dwc2, GGPIO);
+-		ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
+-		ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
+-		dwc2_writel(dwc2, ggpio, GGPIO);
+-
+-		/* ID/VBUS detection startup time */
+-		usleep_range(5000, 7000);
+-
+-		spin_lock_irqsave(&dwc2->lock, flags);
+-		gotgctl = dwc2_readl(dwc2, GOTGCTL);
+-		gotgctl &= ~GOTGCTL_DBNCE_FLTR_BYPASS;
+-		gotgctl &= ~(GOTGCTL_BVALOEN | GOTGCTL_AVALOEN |
+-			     GOTGCTL_BVALOVAL | GOTGCTL_AVALOVAL);
+-		dwc2_writel(dwc2, gotgctl, GOTGCTL);
+-		spin_unlock_irqrestore(&dwc2->lock, flags);
+-	}
+-
+-	/* Need to restore FORCEDEVMODE/FORCEHOSTMODE */
+-	dwc2_force_dr_mode(dwc2);
+-
+-	dwc2_drd_resume(dwc2);
++	usb_phy_set_wakeup(dwc2->uphy, false);
+ 
++#if 0 /* not close endpoint and disconnet */
+ 	if (dwc2_is_device_mode(dwc2))
+ 		ret = dwc2_hsotg_resume(dwc2);
++#endif
+ 
+ 	return ret;
+ }
+@@ -745,7 +726,3 @@ static struct platform_driver dwc2_platform_driver = {
+ };
+ 
+ module_platform_driver(dwc2_platform_driver);
+-
+-MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
+-MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
+-MODULE_LICENSE("Dual BSD/GPL");
+diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
+index 2d152571a..5b19024ae 100644
+--- a/drivers/usb/gadget/Kconfig
++++ b/drivers/usb/gadget/Kconfig
+@@ -216,6 +216,13 @@ config USB_F_PRINTER
+ config USB_F_TCM
+ 	tristate
+ 
++config USB_F_MTP
++        tristate
++
++config USB_F_PTP
++        tristate
++
++
+ # this first set of drivers all depend on bulk-capable hardware.
+ 
+ config USB_CONFIGFS
+@@ -230,6 +237,14 @@ config USB_CONFIGFS
+ 	  appropriate symbolic links.
+ 	  For more information see Documentation/usb/gadget_configfs.rst.
+ 
++config CONFIGFS_UEVENT_REPORT
++	tristate "Support configfs uevent report, Legacy Usage"
++	depends on USB_CONFIGFS
++	default no
++	help
++	  Support uevent report, which is compatible for old android usage.
++	  some platform still need these reports.
++
+ config USB_CONFIGFS_SERIAL
+ 	bool "Generic serial bulk in/out"
+ 	depends on USB_CONFIGFS
+@@ -450,6 +465,7 @@ config USB_CONFIGFS_F_UVC
+ 	depends on USB_CONFIGFS
+ 	depends on VIDEO_V4L2
+ 	depends on VIDEO_DEV
++	select VIDEOBUF2_DMA_SG
+ 	select VIDEOBUF2_VMALLOC
+ 	select USB_F_UVC
+ 	help
+@@ -485,6 +501,21 @@ config USB_CONFIGFS_F_TCM
+ 	  Both protocols can work on USB2.0 and USB3.0.
+ 	  UAS utilizes the USB 3.0 feature called streams support.
+ 
++config USB_CONFIGFS_F_MTP
++        bool "MTP gadget"
++        depends on USB_CONFIGFS
++        select USB_F_MTP
++        help
++          USB gadget MTP support
++
++config USB_CONFIGFS_F_PTP
++        bool "PTP gadget"
++        depends on USB_CONFIGFS && USB_CONFIGFS_F_MTP
++        select USB_F_PTP
++        help
++          USB gadget PTP support
++
++
+ source "drivers/usb/gadget/legacy/Kconfig"
+ 
+ endif # USB_GADGET
+diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
+index a98079990..a03522dfb 100644
+--- a/drivers/usb/gadget/composite.c
++++ b/drivers/usb/gadget/composite.c
+@@ -13,6 +13,7 @@
+ #include <linux/module.h>
+ #include <linux/device.h>
+ #include <linux/utsname.h>
++#include <linux/bitfield.h>
+ 
+ #include <linux/usb/composite.h>
+ #include <linux/usb/otg.h>
+@@ -734,47 +735,77 @@ static int bos_desc(struct usb_composite_dev *cdev)
+ 	/* The SuperSpeedPlus USB Device Capability descriptor */
+ 	if (gadget_is_superspeed_plus(cdev->gadget)) {
+ 		struct usb_ssp_cap_descriptor *ssp_cap;
++		u8 ssac = 1;
++		u8 ssic;
++		int i;
+ 
+-		ssp_cap = cdev->req->buf + le16_to_cpu(bos->wTotalLength);
+-		bos->bNumDeviceCaps++;
++		if (cdev->gadget->max_ssp_rate == USB_SSP_GEN_2x2)
++			ssac = 3;
+ 
+ 		/*
+-		 * Report typical values.
++		 * Paired RX and TX sublink speed attributes share
++		 * the same SSID.
+ 		 */
++		ssic = (ssac + 1) / 2 - 1;
++
++		ssp_cap = cdev->req->buf + le16_to_cpu(bos->wTotalLength);
++		bos->bNumDeviceCaps++;
+ 
+-		le16_add_cpu(&bos->wTotalLength, USB_DT_USB_SSP_CAP_SIZE(1));
+-		ssp_cap->bLength = USB_DT_USB_SSP_CAP_SIZE(1);
++		le16_add_cpu(&bos->wTotalLength, USB_DT_USB_SSP_CAP_SIZE(ssac));
++		ssp_cap->bLength = USB_DT_USB_SSP_CAP_SIZE(ssac);
+ 		ssp_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
+ 		ssp_cap->bDevCapabilityType = USB_SSP_CAP_TYPE;
+ 		ssp_cap->bReserved = 0;
+ 		ssp_cap->wReserved = 0;
+ 
+-		/* SSAC = 1 (2 attributes) */
+-		ssp_cap->bmAttributes = cpu_to_le32(1);
++		ssp_cap->bmAttributes =
++			cpu_to_le32(FIELD_PREP(USB_SSP_SUBLINK_SPEED_ATTRIBS, ssac) |
++				    FIELD_PREP(USB_SSP_SUBLINK_SPEED_IDS, ssic));
+ 
+-		/* Min RX/TX Lane Count = 1 */
+ 		ssp_cap->wFunctionalitySupport =
+-			cpu_to_le16((1 << 8) | (1 << 12));
++			cpu_to_le16(FIELD_PREP(USB_SSP_MIN_SUBLINK_SPEED_ATTRIBUTE_ID, 0) |
++				    FIELD_PREP(USB_SSP_MIN_RX_LANE_COUNT, 1) |
++				    FIELD_PREP(USB_SSP_MIN_TX_LANE_COUNT, 1));
+ 
+ 		/*
+-		 * bmSublinkSpeedAttr[0]:
+-		 *   ST  = Symmetric, RX
+-		 *   LSE =  3 (Gbps)
+-		 *   LP  =  1 (SuperSpeedPlus)
+-		 *   LSM = 10 (10 Gbps)
++		 * Use 1 SSID if the gadget supports up to gen2x1 or not
++		 * specified:
++		 * - SSID 0 for symmetric RX/TX sublink speed of 10 Gbps.
++		 *
++		 * Use 1 SSID if the gadget supports up to gen1x2:
++		 * - SSID 0 for symmetric RX/TX sublink speed of 5 Gbps.
++		 *
++		 * Use 2 SSIDs if the gadget supports up to gen2x2:
++		 * - SSID 0 for symmetric RX/TX sublink speed of 5 Gbps.
++		 * - SSID 1 for symmetric RX/TX sublink speed of 10 Gbps.
+ 		 */
+-		ssp_cap->bmSublinkSpeedAttr[0] =
+-			cpu_to_le32((3 << 4) | (1 << 14) | (0xa << 16));
+-		/*
+-		 * bmSublinkSpeedAttr[1] =
+-		 *   ST  = Symmetric, TX
+-		 *   LSE =  3 (Gbps)
+-		 *   LP  =  1 (SuperSpeedPlus)
+-		 *   LSM = 10 (10 Gbps)
+-		 */
+-		ssp_cap->bmSublinkSpeedAttr[1] =
+-			cpu_to_le32((3 << 4) | (1 << 14) |
+-				    (0xa << 16) | (1 << 7));
++		for (i = 0; i < ssac + 1; i++) {
++			u8 ssid;
++			u8 mantissa;
++			u8 type;
++
++			ssid = i >> 1;
++
++			if (cdev->gadget->max_ssp_rate == USB_SSP_GEN_2x1 ||
++			    cdev->gadget->max_ssp_rate == USB_SSP_GEN_UNKNOWN)
++				mantissa = 10;
++			else
++				mantissa = 5 << ssid;
++
++			if (i % 2)
++				type = USB_SSP_SUBLINK_SPEED_ST_SYM_TX;
++			else
++				type = USB_SSP_SUBLINK_SPEED_ST_SYM_RX;
++
++			ssp_cap->bmSublinkSpeedAttr[i] =
++				cpu_to_le32(FIELD_PREP(USB_SSP_SUBLINK_SPEED_SSID, ssid) |
++					    FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSE,
++						       USB_SSP_SUBLINK_SPEED_LSE_GBPS) |
++					    FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST, type) |
++					    FIELD_PREP(USB_SSP_SUBLINK_SPEED_LP,
++						       USB_SSP_SUBLINK_SPEED_LP_SSP) |
++					    FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSM, mantissa));
++		}
+ 	}
+ 
+ 	return le16_to_cpu(bos->wTotalLength);
+@@ -1648,18 +1679,6 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
+ 	struct usb_function		*f = NULL;
+ 	u8				endp;
+ 
+-	if (w_length > USB_COMP_EP0_BUFSIZ) {
+-		if (ctrl->bRequestType & USB_DIR_IN) {
+-			/* Cast away the const, we are going to overwrite on purpose. */
+-			__le16 *temp = (__le16 *)&ctrl->wLength;
+-
+-			*temp = cpu_to_le16(USB_COMP_EP0_BUFSIZ);
+-			w_length = USB_COMP_EP0_BUFSIZ;
+-		} else {
+-			goto done;
+-		}
+-	}
+-
+ 	/* partial re-init of the response message; the function or the
+ 	 * gadget might need to intercept e.g. a control-OUT completion
+ 	 * when we delegate to it.
+@@ -1944,9 +1963,6 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
+ 				if (w_index != 0x5 || (w_value >> 8))
+ 					break;
+ 				interface = w_value & 0xFF;
+-				if (interface >= MAX_CONFIG_INTERFACES ||
+-				    !os_desc_cfg->interface[interface])
+-					break;
+ 				buf[6] = w_index;
+ 				count = count_ext_prop(os_desc_cfg,
+ 					interface);
+@@ -2176,7 +2192,7 @@ int composite_dev_prepare(struct usb_composite_driver *composite,
+ 	if (!cdev->req)
+ 		return -ENOMEM;
+ 
+-	cdev->req->buf = kzalloc(USB_COMP_EP0_BUFSIZ, GFP_KERNEL);
++	cdev->req->buf = kmalloc(USB_COMP_EP0_BUFSIZ, GFP_KERNEL);
+ 	if (!cdev->req->buf)
+ 		goto fail;
+ 
+diff --git a/drivers/usb/gadget/configfs.c b/drivers/usb/gadget/configfs.c
+index d51ea1c05..576490f78 100644
+--- a/drivers/usb/gadget/configfs.c
++++ b/drivers/usb/gadget/configfs.c
+@@ -10,6 +10,13 @@
+ #include "u_f.h"
+ #include "u_os_desc.h"
+ 
++#include <linux/kdev_t.h>
++#include <linux/usb/ch9.h>
++
++static struct class *android_class;
++static struct device *android_device;
++
++
+ int check_user_usb_string(const char *name,
+ 		struct usb_gadget_strings *stringtab_dev)
+ {
+@@ -51,6 +58,7 @@ struct gadget_info {
+ 	char qw_sign[OS_STRING_QW_SIGN_LEN];
+ 	spinlock_t spinlock;
+ 	bool unbind;
++	bool connected;
+ };
+ 
+ static inline struct gadget_info *to_gadget_info(struct config_item *item)
+@@ -1404,6 +1412,10 @@ static int configfs_composite_bind(struct usb_gadget *gadget,
+ 				goto err_purge_funcs;
+ 			}
+ 		}
++		ret = usb_gadget_check_config(cdev->gadget);
++		if (ret)
++			goto err_purge_funcs;
++
+ 		usb_ep_autoconfig_reset(cdev->gadget);
+ 	}
+ 	if (cdev->use_os_string) {
+@@ -1449,6 +1461,52 @@ static void configfs_composite_unbind(struct usb_gadget *gadget)
+ 	spin_unlock_irqrestore(&gi->spinlock, flags);
+ }
+ 
++static void configfs_uevent_report(struct usb_gadget *gadget, enum usb_device_state s)
++{
++#ifdef CONFIG_CONFIGFS_UEVENT_REPORT
++	struct usb_composite_dev *cdev;
++	char *disconnected[2] = { "USB_STATE=DISCONNECTED", NULL };
++	char *connected[2]    = { "USB_STATE=CONNECTED", NULL };
++	char *configured[2]   = { "USB_STATE=CONFIGURED", NULL };
++	/* 0-connected 1-configured 2-disconnected*/
++	bool status[3] = { false, false, false };
++	bool uevent_sent = false;
++
++	cdev = get_gadget_data(gadget);
++
++	if(s == USB_STATE_ATTACHED) {
++		status[0] = true;
++	} else if(s == USB_STATE_CONFIGURED) {
++		status[1] = true;
++	} else if(s == USB_STATE_NOTATTACHED) {
++		status[2] = true;
++	} else {
++		/*Invalid Status.*/
++	}
++
++	if (status[0]) {
++		kobject_uevent_env(&android_device->kobj,
++				KOBJ_CHANGE, connected);
++		pr_info("%s: sent uevent %s\n", __func__, connected[0]);
++		uevent_sent = true;
++	}
++
++	if (status[1]) {
++		kobject_uevent_env(&android_device->kobj,
++				KOBJ_CHANGE, configured);
++		pr_info("%s: sent uevent %s\n", __func__, configured[0]);
++		uevent_sent = true;
++	}
++
++	if (status[2]) {
++		kobject_uevent_env(&android_device->kobj,
++				KOBJ_CHANGE, disconnected);
++		pr_info("%s: sent uevent %s\n", __func__, disconnected[0]);
++		uevent_sent = true;
++	}
++#endif
++}
++
+ static int configfs_composite_setup(struct usb_gadget *gadget,
+ 		const struct usb_ctrlrequest *ctrl)
+ {
+@@ -1469,7 +1527,15 @@ static int configfs_composite_setup(struct usb_gadget *gadget,
+ 		return 0;
+ 	}
+ 
++	if(!gi->connected) {
++		configfs_uevent_report(gadget, USB_STATE_ATTACHED);
++		gi->connected = 1;
++	}
++
+ 	ret = composite_setup(gadget, ctrl);
++	if((ctrl->bRequest == USB_REQ_SET_CONFIGURATION) && cdev->config) {
++		configfs_uevent_report(gadget, USB_STATE_CONFIGURED);
++	}
+ 	spin_unlock_irqrestore(&gi->spinlock, flags);
+ 	return ret;
+ }
+@@ -1493,6 +1559,11 @@ static void configfs_composite_disconnect(struct usb_gadget *gadget)
+ 	}
+ 
+ 	composite_disconnect(gadget);
++
++	configfs_uevent_report(gadget, USB_STATE_NOTATTACHED);
++
++	gi->connected = 0;
++
+ 	spin_unlock_irqrestore(&gi->spinlock, flags);
+ }
+ 
+@@ -1559,6 +1630,79 @@ static const struct usb_gadget_driver configfs_driver_template = {
+ 	.match_existing_only = 1,
+ };
+ 
++static ssize_t state_show(struct device *pdev, struct device_attribute *attr,
++		char *buf)
++{
++	struct gadget_info *gi = dev_get_drvdata(pdev);
++	struct usb_composite_dev *cdev;
++	char *state = "DISCONNECTED";
++	unsigned long flags;
++
++	if (!gi)
++		goto out;
++
++	cdev = &gi->cdev;
++
++	if (!cdev)
++		goto out;
++
++	spin_lock_irqsave(&gi->spinlock, flags);
++	if (cdev->config)
++		state = "CONFIGURED";
++	else if (gi->connected)
++		state = "CONNECTED";
++	spin_unlock_irqrestore(&gi->spinlock, flags);
++out:
++	return sprintf(buf, "%s\n", state);
++}
++
++static DEVICE_ATTR(state, S_IRUGO, state_show, NULL);
++
++static struct device_attribute *android_usb_attributes[] = {
++	&dev_attr_state,
++	NULL
++};
++
++static int android_device_create(struct gadget_info *gi)
++{
++	struct device_attribute **attrs;
++	struct device_attribute *attr;
++
++	android_device = device_create(android_class, NULL,
++			MKDEV(0, 0), NULL, "android0");
++	if (IS_ERR(android_device))
++		return PTR_ERR(android_device);
++
++	dev_set_drvdata(android_device, gi);
++
++	attrs = android_usb_attributes;
++	while ((attr = *attrs++)) {
++		int err;
++
++		err = device_create_file(android_device, attr);
++		if (err) {
++			device_destroy(android_device->class,
++					android_device->devt);
++			return err;
++		}
++	}
++
++	return 0;
++}
++
++static void android_device_destroy(void)
++{
++	struct device_attribute **attrs;
++	struct device_attribute *attr;
++
++	attrs = android_usb_attributes;
++	while ((attr = *attrs++))
++		device_remove_file(android_device, attr);
++	device_destroy(android_device->class, android_device->devt);
++}
++
++
++
+ static struct config_group *gadgets_make(
+ 		struct config_group *group,
+ 		const char *name)
+@@ -1611,6 +1755,9 @@ static struct config_group *gadgets_make(
+ 	if (!gi->composite.gadget_driver.function)
+ 		goto err;
+ 
++	if (android_device_create(gi) < 0)
++		goto err;
++
+ 	return &gi->group;
+ err:
+ 	kfree(gi);
+@@ -1620,6 +1767,7 @@ static struct config_group *gadgets_make(
+ static void gadgets_drop(struct config_group *group, struct config_item *item)
+ {
+ 	config_item_put(item);
++	android_device_destroy();
+ }
+ 
+ static struct configfs_group_operations gadgets_ops = {
+@@ -1659,6 +1807,11 @@ static int __init gadget_cfs_init(void)
+ 	config_group_init(&gadget_subsys.su_group);
+ 
+ 	ret = configfs_register_subsystem(&gadget_subsys);
++
++	android_class = class_create(THIS_MODULE, "android_usb");
++	if (IS_ERR(android_class))
++		return PTR_ERR(android_class);
++
+ 	return ret;
+ }
+ module_init(gadget_cfs_init);
+@@ -1666,5 +1819,9 @@ module_init(gadget_cfs_init);
+ static void __exit gadget_cfs_exit(void)
+ {
+ 	configfs_unregister_subsystem(&gadget_subsys);
++
++	if (!IS_ERR(android_class))
++		class_destroy(android_class);
++
+ }
+ module_exit(gadget_cfs_exit);
+diff --git a/drivers/usb/gadget/function/Makefile b/drivers/usb/gadget/function/Makefile
+index 5d3a6cf02..346f460a1 100644
+--- a/drivers/usb/gadget/function/Makefile
++++ b/drivers/usb/gadget/function/Makefile
+@@ -50,3 +50,7 @@ usb_f_printer-y			:= f_printer.o
+ obj-$(CONFIG_USB_F_PRINTER)	+= usb_f_printer.o
+ usb_f_tcm-y			:= f_tcm.o
+ obj-$(CONFIG_USB_F_TCM)		+= usb_f_tcm.o
++usb_f_mtp-y                     := f_mtp.o
++obj-$(CONFIG_USB_F_MTP) 	+= usb_f_mtp.o
++usb_f_ptp-y                     := f_ptp.o
++obj-$(CONFIG_USB_F_PTP) 	+= usb_f_ptp.o
+diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c
+index bb0d92837..8042d812b 100644
+--- a/drivers/usb/gadget/function/f_fs.c
++++ b/drivers/usb/gadget/function/f_fs.c
+@@ -614,7 +614,7 @@ static int ffs_ep0_open(struct inode *inode, struct file *file)
+ 	file->private_data = ffs;
+ 	ffs_data_opened(ffs);
+ 
+-	return stream_open(inode, file);
++	return 0;
+ }
+ 
+ static int ffs_ep0_release(struct inode *inode, struct file *file)
+@@ -1152,7 +1152,7 @@ ffs_epfile_open(struct inode *inode, struct file *file)
+ 	file->private_data = epfile;
+ 	ffs_data_opened(epfile->ffs);
+ 
+-	return stream_open(inode, file);
++	return 0;
+ }
+ 
+ static int ffs_aio_cancel(struct kiocb *kiocb)
+@@ -1562,13 +1562,13 @@ static int ffs_fs_get_tree(struct fs_context *fc)
+ 		return invalf(fc, "No source specified");
+ 
+ 	ffs = ffs_data_new(fc->source);
+-	if (unlikely(!ffs))
++	if (!ffs)
+ 		return -ENOMEM;
+ 	ffs->file_perms = ctx->perms;
+ 	ffs->no_disconnect = ctx->no_disconnect;
+ 
+ 	ffs->dev_name = kstrdup(fc->source, GFP_KERNEL);
+-	if (unlikely(!ffs->dev_name)) {
++	if (!ffs->dev_name) {
+ 		ffs_data_put(ffs);
+ 		return -ENOMEM;
+ 	}
+@@ -1814,6 +1814,7 @@ static void ffs_data_reset(struct ffs_data *ffs)
+ 
+ 	ffs_data_clear(ffs);
+ 
++	ffs->epfiles = NULL;
+ 	ffs->raw_descs_data = NULL;
+ 	ffs->raw_descs = NULL;
+ 	ffs->raw_strings = NULL;
+diff --git a/drivers/usb/gadget/function/f_hid.c b/drivers/usb/gadget/function/f_hid.c
+index 6742271cd..ddccfa8fc 100644
+--- a/drivers/usb/gadget/function/f_hid.c
++++ b/drivers/usb/gadget/function/f_hid.c
+@@ -45,12 +45,25 @@ struct f_hidg {
+ 	unsigned short			report_desc_length;
+ 	char				*report_desc;
+ 	unsigned short			report_length;
++	/*
++	 * use_out_ep - if true, the OUT Endpoint (interrupt out method)
++	 *              will be used to receive reports from the host
++	 *              using functions with the "intout" suffix.
++	 *              Otherwise, the OUT Endpoint will not be configured
++	 *              and the SETUP/SET_REPORT method ("ssreport" suffix)
++	 *              will be used to receive reports.
++	 */
++	bool				use_out_ep;
+ 
+ 	/* recv report */
+-	struct list_head		completed_out_req;
+ 	spinlock_t			read_spinlock;
+ 	wait_queue_head_t		read_queue;
++	/* recv report - interrupt out only (use_out_ep == 1) */
++	struct list_head		completed_out_req;
+ 	unsigned int			qlen;
++	/* recv report - setup set_report only (use_out_ep == 0) */
++	char				*set_report_buf;
++	unsigned int			set_report_length;
+ 
+ 	/* send report */
+ 	spinlock_t			write_spinlock;
+@@ -79,7 +92,7 @@ static struct usb_interface_descriptor hidg_interface_desc = {
+ 	.bDescriptorType	= USB_DT_INTERFACE,
+ 	/* .bInterfaceNumber	= DYNAMIC */
+ 	.bAlternateSetting	= 0,
+-	.bNumEndpoints		= 2,
++	/* .bNumEndpoints	= DYNAMIC (depends on use_out_ep) */
+ 	.bInterfaceClass	= USB_CLASS_HID,
+ 	/* .bInterfaceSubClass	= DYNAMIC */
+ 	/* .bInterfaceProtocol	= DYNAMIC */
+@@ -140,7 +153,7 @@ static struct usb_ss_ep_comp_descriptor hidg_ss_out_comp_desc = {
+ 	/* .wBytesPerInterval   = DYNAMIC */
+ };
+ 
+-static struct usb_descriptor_header *hidg_ss_descriptors[] = {
++static struct usb_descriptor_header *hidg_ss_descriptors_intout[] = {
+ 	(struct usb_descriptor_header *)&hidg_interface_desc,
+ 	(struct usb_descriptor_header *)&hidg_desc,
+ 	(struct usb_descriptor_header *)&hidg_ss_in_ep_desc,
+@@ -150,6 +163,14 @@ static struct usb_descriptor_header *hidg_ss_descriptors[] = {
+ 	NULL,
+ };
+ 
++static struct usb_descriptor_header *hidg_ss_descriptors_ssreport[] = {
++	(struct usb_descriptor_header *)&hidg_interface_desc,
++	(struct usb_descriptor_header *)&hidg_desc,
++	(struct usb_descriptor_header *)&hidg_ss_in_ep_desc,
++	(struct usb_descriptor_header *)&hidg_ss_in_comp_desc,
++	NULL,
++};
++
+ /* High-Speed Support */
+ 
+ static struct usb_endpoint_descriptor hidg_hs_in_ep_desc = {
+@@ -176,7 +197,7 @@ static struct usb_endpoint_descriptor hidg_hs_out_ep_desc = {
+ 				      */
+ };
+ 
+-static struct usb_descriptor_header *hidg_hs_descriptors[] = {
++static struct usb_descriptor_header *hidg_hs_descriptors_intout[] = {
+ 	(struct usb_descriptor_header *)&hidg_interface_desc,
+ 	(struct usb_descriptor_header *)&hidg_desc,
+ 	(struct usb_descriptor_header *)&hidg_hs_in_ep_desc,
+@@ -184,6 +205,13 @@ static struct usb_descriptor_header *hidg_hs_descriptors[] = {
+ 	NULL,
+ };
+ 
++static struct usb_descriptor_header *hidg_hs_descriptors_ssreport[] = {
++	(struct usb_descriptor_header *)&hidg_interface_desc,
++	(struct usb_descriptor_header *)&hidg_desc,
++	(struct usb_descriptor_header *)&hidg_hs_in_ep_desc,
++	NULL,
++};
++
+ /* Full-Speed Support */
+ 
+ static struct usb_endpoint_descriptor hidg_fs_in_ep_desc = {
+@@ -210,7 +238,7 @@ static struct usb_endpoint_descriptor hidg_fs_out_ep_desc = {
+ 				       */
+ };
+ 
+-static struct usb_descriptor_header *hidg_fs_descriptors[] = {
++static struct usb_descriptor_header *hidg_fs_descriptors_intout[] = {
+ 	(struct usb_descriptor_header *)&hidg_interface_desc,
+ 	(struct usb_descriptor_header *)&hidg_desc,
+ 	(struct usb_descriptor_header *)&hidg_fs_in_ep_desc,
+@@ -218,6 +246,13 @@ static struct usb_descriptor_header *hidg_fs_descriptors[] = {
+ 	NULL,
+ };
+ 
++static struct usb_descriptor_header *hidg_fs_descriptors_ssreport[] = {
++	(struct usb_descriptor_header *)&hidg_interface_desc,
++	(struct usb_descriptor_header *)&hidg_desc,
++	(struct usb_descriptor_header *)&hidg_fs_in_ep_desc,
++	NULL,
++};
++
+ /*-------------------------------------------------------------------------*/
+ /*                                 Strings                                 */
+ 
+@@ -241,8 +276,8 @@ static struct usb_gadget_strings *ct_func_strings[] = {
+ /*-------------------------------------------------------------------------*/
+ /*                              Char Device                                */
+ 
+-static ssize_t f_hidg_read(struct file *file, char __user *buffer,
+-			size_t count, loff_t *ptr)
++static ssize_t f_hidg_intout_read(struct file *file, char __user *buffer,
++				  size_t count, loff_t *ptr)
+ {
+ 	struct f_hidg *hidg = file->private_data;
+ 	struct f_hidg_req_list *list;
+@@ -255,15 +290,15 @@ static ssize_t f_hidg_read(struct file *file, char __user *buffer,
+ 
+ 	spin_lock_irqsave(&hidg->read_spinlock, flags);
+ 
+-#define READ_COND (!list_empty(&hidg->completed_out_req))
++#define READ_COND_INTOUT (!list_empty(&hidg->completed_out_req))
+ 
+ 	/* wait for at least one buffer to complete */
+-	while (!READ_COND) {
++	while (!READ_COND_INTOUT) {
+ 		spin_unlock_irqrestore(&hidg->read_spinlock, flags);
+ 		if (file->f_flags & O_NONBLOCK)
+ 			return -EAGAIN;
+ 
+-		if (wait_event_interruptible(hidg->read_queue, READ_COND))
++		if (wait_event_interruptible(hidg->read_queue, READ_COND_INTOUT))
+ 			return -ERESTARTSYS;
+ 
+ 		spin_lock_irqsave(&hidg->read_spinlock, flags);
+@@ -313,6 +348,60 @@ static ssize_t f_hidg_read(struct file *file, char __user *buffer,
+ 	return count;
+ }
+ 
++#define READ_COND_SSREPORT (hidg->set_report_buf != NULL)
++
++static ssize_t f_hidg_ssreport_read(struct file *file, char __user *buffer,
++				    size_t count, loff_t *ptr)
++{
++	struct f_hidg *hidg = file->private_data;
++	char *tmp_buf = NULL;
++	unsigned long flags;
++
++	if (!count)
++		return 0;
++
++	spin_lock_irqsave(&hidg->read_spinlock, flags);
++
++	while (!READ_COND_SSREPORT) {
++		spin_unlock_irqrestore(&hidg->read_spinlock, flags);
++		if (file->f_flags & O_NONBLOCK)
++			return -EAGAIN;
++
++		if (wait_event_interruptible(hidg->read_queue, READ_COND_SSREPORT))
++			return -ERESTARTSYS;
++
++		spin_lock_irqsave(&hidg->read_spinlock, flags);
++	}
++
++	count = min_t(unsigned int, count, hidg->set_report_length);
++	tmp_buf = hidg->set_report_buf;
++	hidg->set_report_buf = NULL;
++
++	spin_unlock_irqrestore(&hidg->read_spinlock, flags);
++
++	if (tmp_buf != NULL) {
++		count -= copy_to_user(buffer, tmp_buf, count);
++		kfree(tmp_buf);
++	} else {
++		count = -ENOMEM;
++	}
++
++	wake_up(&hidg->read_queue);
++
++	return count;
++}
++
++static ssize_t f_hidg_read(struct file *file, char __user *buffer,
++			   size_t count, loff_t *ptr)
++{
++	struct f_hidg *hidg = file->private_data;
++
++	if (hidg->use_out_ep)
++		return f_hidg_intout_read(file, buffer, count, ptr);
++	else
++		return f_hidg_ssreport_read(file, buffer, count, ptr);
++}
++
+ static void f_hidg_req_complete(struct usb_ep *ep, struct usb_request *req)
+ {
+ 	struct f_hidg *hidg = (struct f_hidg *)ep->driver_data;
+@@ -433,14 +522,20 @@ static __poll_t f_hidg_poll(struct file *file, poll_table *wait)
+ 	if (WRITE_COND)
+ 		ret |= EPOLLOUT | EPOLLWRNORM;
+ 
+-	if (READ_COND)
+-		ret |= EPOLLIN | EPOLLRDNORM;
++	if (hidg->use_out_ep) {
++		if (READ_COND_INTOUT)
++			ret |= EPOLLIN | EPOLLRDNORM;
++	} else {
++		if (READ_COND_SSREPORT)
++			ret |= EPOLLIN | EPOLLRDNORM;
++	}
+ 
+ 	return ret;
+ }
+ 
+ #undef WRITE_COND
+-#undef READ_COND
++#undef READ_COND_SSREPORT
++#undef READ_COND_INTOUT
+ 
+ static int f_hidg_release(struct inode *inode, struct file *fd)
+ {
+@@ -467,7 +562,7 @@ static inline struct usb_request *hidg_alloc_ep_req(struct usb_ep *ep,
+ 	return alloc_ep_req(ep, length);
+ }
+ 
+-static void hidg_set_report_complete(struct usb_ep *ep, struct usb_request *req)
++static void hidg_intout_complete(struct usb_ep *ep, struct usb_request *req)
+ {
+ 	struct f_hidg *hidg = (struct f_hidg *) req->context;
+ 	struct usb_composite_dev *cdev = hidg->func.config->cdev;
+@@ -502,6 +597,37 @@ static void hidg_set_report_complete(struct usb_ep *ep, struct usb_request *req)
+ 	}
+ }
+ 
++static void hidg_ssreport_complete(struct usb_ep *ep, struct usb_request *req)
++{
++	struct f_hidg *hidg = (struct f_hidg *)req->context;
++	struct usb_composite_dev *cdev = hidg->func.config->cdev;
++	char *new_buf = NULL;
++	unsigned long flags;
++
++	if (req->status != 0 || req->buf == NULL || req->actual == 0) {
++		ERROR(cdev,
++		      "%s FAILED: status=%d, buf=%p, actual=%d\n",
++		      __func__, req->status, req->buf, req->actual);
++		return;
++	}
++
++	spin_lock_irqsave(&hidg->read_spinlock, flags);
++
++	new_buf = krealloc(hidg->set_report_buf, req->actual, GFP_ATOMIC);
++	if (new_buf == NULL) {
++		spin_unlock_irqrestore(&hidg->read_spinlock, flags);
++		return;
++	}
++	hidg->set_report_buf = new_buf;
++
++	hidg->set_report_length = req->actual;
++	memcpy(hidg->set_report_buf, req->buf, req->actual);
++
++	spin_unlock_irqrestore(&hidg->read_spinlock, flags);
++
++	wake_up(&hidg->read_queue);
++}
++
+ static int hidg_setup(struct usb_function *f,
+ 		const struct usb_ctrlrequest *ctrl)
+ {
+@@ -549,7 +675,11 @@ static int hidg_setup(struct usb_function *f,
+ 	case ((USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE) << 8
+ 		  | HID_REQ_SET_REPORT):
+ 		VDBG(cdev, "set_report | wLength=%d\n", ctrl->wLength);
+-		goto stall;
++		if (hidg->use_out_ep)
++			goto stall;
++		req->complete = hidg_ssreport_complete;
++		req->context  = hidg;
++		goto respond;
+ 		break;
+ 
+ 	case ((USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE) << 8
+@@ -637,15 +767,18 @@ static void hidg_disable(struct usb_function *f)
+ 	unsigned long flags;
+ 
+ 	usb_ep_disable(hidg->in_ep);
+-	usb_ep_disable(hidg->out_ep);
+ 
+-	spin_lock_irqsave(&hidg->read_spinlock, flags);
+-	list_for_each_entry_safe(list, next, &hidg->completed_out_req, list) {
+-		free_ep_req(hidg->out_ep, list->req);
+-		list_del(&list->list);
+-		kfree(list);
++	if (hidg->out_ep) {
++		usb_ep_disable(hidg->out_ep);
++
++		spin_lock_irqsave(&hidg->read_spinlock, flags);
++		list_for_each_entry_safe(list, next, &hidg->completed_out_req, list) {
++			free_ep_req(hidg->out_ep, list->req);
++			list_del(&list->list);
++			kfree(list);
++		}
++		spin_unlock_irqrestore(&hidg->read_spinlock, flags);
+ 	}
+-	spin_unlock_irqrestore(&hidg->read_spinlock, flags);
+ 
+ 	spin_lock_irqsave(&hidg->write_spinlock, flags);
+ 	if (!hidg->write_pending) {
+@@ -691,8 +824,7 @@ static int hidg_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
+ 		}
+ 	}
+ 
+-
+-	if (hidg->out_ep != NULL) {
++	if (hidg->use_out_ep && hidg->out_ep != NULL) {
+ 		/* restart endpoint */
+ 		usb_ep_disable(hidg->out_ep);
+ 
+@@ -717,7 +849,7 @@ static int hidg_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
+ 					hidg_alloc_ep_req(hidg->out_ep,
+ 							  hidg->report_length);
+ 			if (req) {
+-				req->complete = hidg_set_report_complete;
++				req->complete = hidg_intout_complete;
+ 				req->context  = hidg;
+ 				status = usb_ep_queue(hidg->out_ep, req,
+ 						      GFP_ATOMIC);
+@@ -743,7 +875,8 @@ static int hidg_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
+ 	}
+ 	return 0;
+ disable_out_ep:
+-	usb_ep_disable(hidg->out_ep);
++	if (hidg->out_ep)
++		usb_ep_disable(hidg->out_ep);
+ free_req_in:
+ 	if (req_in)
+ 		free_ep_req(hidg->in_ep, req_in);
+@@ -795,14 +928,21 @@ static int hidg_bind(struct usb_configuration *c, struct usb_function *f)
+ 		goto fail;
+ 	hidg->in_ep = ep;
+ 
+-	ep = usb_ep_autoconfig(c->cdev->gadget, &hidg_fs_out_ep_desc);
+-	if (!ep)
+-		goto fail;
+-	hidg->out_ep = ep;
++	hidg->out_ep = NULL;
++	if (hidg->use_out_ep) {
++		ep = usb_ep_autoconfig(c->cdev->gadget, &hidg_fs_out_ep_desc);
++		if (!ep)
++			goto fail;
++		hidg->out_ep = ep;
++	}
++
++	/* used only if use_out_ep == 1 */
++	hidg->set_report_buf = NULL;
+ 
+ 	/* set descriptor dynamic values */
+ 	hidg_interface_desc.bInterfaceSubClass = hidg->bInterfaceSubClass;
+ 	hidg_interface_desc.bInterfaceProtocol = hidg->bInterfaceProtocol;
++	hidg_interface_desc.bNumEndpoints = hidg->use_out_ep ? 2 : 1;
+ 	hidg->protocol = HID_REPORT_PROTOCOL;
+ 	hidg->idle = 1;
+ 	hidg_ss_in_ep_desc.wMaxPacketSize = cpu_to_le16(hidg->report_length);
+@@ -833,9 +973,19 @@ static int hidg_bind(struct usb_configuration *c, struct usb_function *f)
+ 	hidg_ss_out_ep_desc.bEndpointAddress =
+ 		hidg_fs_out_ep_desc.bEndpointAddress;
+ 
+-	status = usb_assign_descriptors(f, hidg_fs_descriptors,
+-			hidg_hs_descriptors, hidg_ss_descriptors,
+-			hidg_ss_descriptors);
++	if (hidg->use_out_ep)
++		status = usb_assign_descriptors(f,
++			hidg_fs_descriptors_intout,
++			hidg_hs_descriptors_intout,
++			hidg_ss_descriptors_intout,
++			hidg_ss_descriptors_intout);
++	else
++		status = usb_assign_descriptors(f,
++			hidg_fs_descriptors_ssreport,
++			hidg_hs_descriptors_ssreport,
++			hidg_ss_descriptors_ssreport,
++			hidg_ss_descriptors_ssreport);
++
+ 	if (status)
+ 		goto fail;
+ 
+@@ -950,6 +1100,7 @@ CONFIGFS_ATTR(f_hid_opts_, name)
+ 
+ F_HID_OPT(subclass, 8, 255);
+ F_HID_OPT(protocol, 8, 255);
++F_HID_OPT(no_out_endpoint, 8, 1);
+ F_HID_OPT(report_length, 16, 65535);
+ 
+ static ssize_t f_hid_opts_report_desc_show(struct config_item *item, char *page)
+@@ -1009,6 +1160,7 @@ CONFIGFS_ATTR_RO(f_hid_opts_, dev);
+ static struct configfs_attribute *hid_attrs[] = {
+ 	&f_hid_opts_attr_subclass,
+ 	&f_hid_opts_attr_protocol,
++	&f_hid_opts_attr_no_out_endpoint,
+ 	&f_hid_opts_attr_report_length,
+ 	&f_hid_opts_attr_report_desc,
+ 	&f_hid_opts_attr_dev,
+@@ -1093,6 +1245,7 @@ static void hidg_free(struct usb_function *f)
+ 	hidg = func_to_hidg(f);
+ 	opts = container_of(f->fi, struct f_hid_opts, func_inst);
+ 	kfree(hidg->report_desc);
++	kfree(hidg->set_report_buf);
+ 	kfree(hidg);
+ 	mutex_lock(&opts->lock);
+ 	--opts->refcnt;
+@@ -1139,6 +1292,7 @@ static struct usb_function *hidg_alloc(struct usb_function_instance *fi)
+ 			return ERR_PTR(-ENOMEM);
+ 		}
+ 	}
++	hidg->use_out_ep = !opts->no_out_endpoint;
+ 
+ 	mutex_unlock(&opts->lock);
+ 
+@@ -1150,7 +1304,7 @@ static struct usb_function *hidg_alloc(struct usb_function_instance *fi)
+ 	hidg->func.setup   = hidg_setup;
+ 	hidg->func.free_func = hidg_free;
+ 
+-	/* this could me made configurable at some point */
++	/* this could be made configurable at some point */
+ 	hidg->qlen	   = 4;
+ 
+ 	return &hidg->func;
+@@ -1194,4 +1348,4 @@ void ghid_cleanup(void)
+ 
+ 	class_destroy(hidg_class);
+ 	hidg_class = NULL;
+-}
++}
+\ No newline at end of file
+diff --git a/drivers/usb/gadget/function/f_mass_storage.c b/drivers/usb/gadget/function/f_mass_storage.c
+index 950c9435b..665a97496 100644
+--- a/drivers/usb/gadget/function/f_mass_storage.c
++++ b/drivers/usb/gadget/function/f_mass_storage.c
+@@ -6,36 +6,6 @@
+  * Copyright (C) 2009 Samsung Electronics
+  *                    Author: Michal Nazarewicz <mina86@mina86.com>
+  * All rights reserved.
+- *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions
+- * are met:
+- * 1. Redistributions of source code must retain the above copyright
+- *    notice, this list of conditions, and the following disclaimer,
+- *    without modification.
+- * 2. Redistributions in binary form must reproduce the above copyright
+- *    notice, this list of conditions and the following disclaimer in the
+- *    documentation and/or other materials provided with the distribution.
+- * 3. The names of the above-listed copyright holders may not be used
+- *    to endorse or promote products derived from this software without
+- *    specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+- * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  */
+ 
+ /*
+@@ -351,8 +321,6 @@ static inline struct fsg_dev *fsg_from_func(struct usb_function *f)
+ 	return container_of(f, struct fsg_dev, function);
+ }
+ 
+-typedef void (*fsg_routine_t)(struct fsg_dev *);
+-
+ static int exception_in_progress(struct fsg_common *common)
+ {
+ 	return common->state > FSG_STATE_NORMAL;
+@@ -3473,4 +3441,4 @@ void fsg_config_from_params(struct fsg_config *cfg,
+ 	cfg->can_stall = params->stall;
+ 	cfg->fsg_num_buffers = fsg_num_buffers;
+ }
+-EXPORT_SYMBOL_GPL(fsg_config_from_params);
++EXPORT_SYMBOL_GPL(fsg_config_from_params);
+\ No newline at end of file
+diff --git a/drivers/usb/gadget/function/f_midi.c b/drivers/usb/gadget/function/f_midi.c
+index 8fff995b8..71a1a26e8 100644
+--- a/drivers/usb/gadget/function/f_midi.c
++++ b/drivers/usb/gadget/function/f_midi.c
+@@ -87,7 +87,7 @@ struct f_midi {
+ 	struct snd_rawmidi_substream *out_substream[MAX_PORTS];
+ 
+ 	unsigned long		out_triggered;
+-	struct tasklet_struct	tasklet;
++	struct work_struct	work;
+ 	unsigned int in_ports;
+ 	unsigned int out_ports;
+ 	int index;
+@@ -698,9 +698,11 @@ static void f_midi_transmit(struct f_midi *midi)
+ 	f_midi_drop_out_substreams(midi);
+ }
+ 
+-static void f_midi_in_tasklet(struct tasklet_struct *t)
++static void f_midi_in_work(struct work_struct *work)
+ {
+-	struct f_midi *midi = from_tasklet(midi, t, tasklet);
++	struct f_midi *midi;
++
++	midi = container_of(work, struct f_midi, work);
+ 	f_midi_transmit(midi);
+ }
+ 
+@@ -737,7 +739,7 @@ static void f_midi_in_trigger(struct snd_rawmidi_substream *substream, int up)
+ 	VDBG(midi, "%s() %d\n", __func__, up);
+ 	midi->in_ports_array[substream->number].active = up;
+ 	if (up)
+-		tasklet_hi_schedule(&midi->tasklet);
++		queue_work(system_highpri_wq, &midi->work);
+ }
+ 
+ static int f_midi_out_open(struct snd_rawmidi_substream *substream)
+@@ -875,7 +877,7 @@ static int f_midi_bind(struct usb_configuration *c, struct usb_function *f)
+ 	int status, n, jack = 1, i = 0, endpoint_descriptor_index = 0;
+ 
+ 	midi->gadget = cdev->gadget;
+-	tasklet_setup(&midi->tasklet, f_midi_in_tasklet);
++	INIT_WORK(&midi->work, f_midi_in_work);
+ 	status = f_midi_register_card(midi);
+ 	if (status < 0)
+ 		goto fail_register;
+diff --git a/drivers/usb/gadget/function/f_mtp.c b/drivers/usb/gadget/function/f_mtp.c
+new file mode 100755
+index 000000000..133dcfaca
+--- /dev/null
++++ b/drivers/usb/gadget/function/f_mtp.c
+@@ -0,0 +1,1536 @@
++/*
++ * Gadget Function Driver for MTP
++ *
++ * Copyright (C) 2010 Google, Inc.
++ * Author: Mike Lockwood <lockwood@android.com>
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++/* #define DEBUG */
++/* #define VERBOSE_DEBUG */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/poll.h>
++#include <linux/delay.h>
++#include <linux/wait.h>
++#include <linux/err.h>
++#include <linux/interrupt.h>
++
++#include <linux/types.h>
++#include <linux/file.h>
++#include <linux/device.h>
++#include <linux/miscdevice.h>
++
++#include <linux/usb.h>
++#include <linux/usb_usual.h>
++#include <linux/usb/ch9.h>
++#include <linux/usb/f_mtp.h>
++#include <linux/configfs.h>
++#include <linux/usb/composite.h>
++
++#include "configfs.h"
++
++#define MTP_BULK_BUFFER_SIZE       16384
++#define INTR_BUFFER_SIZE           28
++#define MAX_INST_NAME_LEN          40
++
++/* String IDs */
++#define INTERFACE_STRING_INDEX	0
++
++/* values for mtp_dev.state */
++#define STATE_OFFLINE               0   /* initial state, disconnected */
++#define STATE_READY                 1   /* ready for userspace calls */
++#define STATE_BUSY                  2   /* processing userspace calls */
++#define STATE_CANCELED              3   /* transaction canceled by host */
++#define STATE_ERROR                 4   /* error from completion routine */
++
++/* number of tx and rx requests to allocate */
++#define TX_REQ_MAX 4
++#define RX_REQ_MAX 2
++#define INTR_REQ_MAX 5
++
++/* ID for Microsoft MTP OS String */
++#define MTP_OS_STRING_ID   0xEE
++
++/* MTP class reqeusts */
++#define MTP_REQ_CANCEL              0x64
++#define MTP_REQ_GET_EXT_EVENT_DATA  0x65
++#define MTP_REQ_RESET               0x66
++#define MTP_REQ_GET_DEVICE_STATUS   0x67
++
++/* constants for device status */
++#define MTP_RESPONSE_OK             0x2001
++#define MTP_RESPONSE_DEVICE_BUSY    0x2019
++#define DRIVER_NAME "mtp"
++
++static const char mtp_shortname[] = DRIVER_NAME "_usb";
++
++struct mtp_dev {
++	struct usb_function function;
++	struct usb_composite_dev *cdev;
++	spinlock_t lock;
++
++	struct usb_ep *ep_in;
++	struct usb_ep *ep_out;
++	struct usb_ep *ep_intr;
++
++	int state;
++
++	/* synchronize access to our device file */
++	atomic_t open_excl;
++	/* to enforce only one ioctl at a time */
++	atomic_t ioctl_excl;
++
++	struct list_head tx_idle;
++	struct list_head intr_idle;
++
++	wait_queue_head_t read_wq;
++	wait_queue_head_t write_wq;
++	wait_queue_head_t intr_wq;
++	struct usb_request *rx_req[RX_REQ_MAX];
++	int rx_done;
++
++	/* for processing MTP_SEND_FILE, MTP_RECEIVE_FILE and
++	 * MTP_SEND_FILE_WITH_HEADER ioctls on a work queue
++	 */
++	struct workqueue_struct *wq;
++	struct work_struct send_file_work;
++	struct work_struct receive_file_work;
++	struct file *xfer_file;
++	loff_t xfer_file_offset;
++	int64_t xfer_file_length;
++	unsigned xfer_send_header;
++	uint16_t xfer_command;
++	uint32_t xfer_transaction_id;
++	int xfer_result;
++};
++
++static struct usb_interface_descriptor mtp_interface_desc = {
++	.bLength                = USB_DT_INTERFACE_SIZE,
++	.bDescriptorType        = USB_DT_INTERFACE,
++	.bInterfaceNumber       = 0,
++	.bNumEndpoints          = 3,
++	.bInterfaceClass        = USB_CLASS_STILL_IMAGE,
++	.bInterfaceSubClass     = 1,
++	.bInterfaceProtocol     = 1,
++};
++
++static struct usb_interface_descriptor ptp_interface_desc = {
++	.bLength                = USB_DT_INTERFACE_SIZE,
++	.bDescriptorType        = USB_DT_INTERFACE,
++	.bInterfaceNumber       = 0,
++	.bNumEndpoints          = 3,
++	.bInterfaceClass        = USB_CLASS_STILL_IMAGE,
++	.bInterfaceSubClass     = 1,
++	.bInterfaceProtocol     = 1,
++};
++
++static struct usb_endpoint_descriptor mtp_ss_in_desc = {
++	.bLength                = USB_DT_ENDPOINT_SIZE,
++	.bDescriptorType        = USB_DT_ENDPOINT,
++	.bEndpointAddress       = USB_DIR_IN,
++	.bmAttributes           = USB_ENDPOINT_XFER_BULK,
++	.wMaxPacketSize         = __constant_cpu_to_le16(1024),
++};
++
++static struct usb_ss_ep_comp_descriptor mtp_ss_in_comp_desc = {
++	.bLength                = sizeof(mtp_ss_in_comp_desc),
++	.bDescriptorType        = USB_DT_SS_ENDPOINT_COMP,
++	/* .bMaxBurst           = DYNAMIC, */
++};
++
++static struct usb_endpoint_descriptor mtp_ss_out_desc = {
++	.bLength                = USB_DT_ENDPOINT_SIZE,
++	.bDescriptorType        = USB_DT_ENDPOINT,
++	.bEndpointAddress       = USB_DIR_OUT,
++	.bmAttributes           = USB_ENDPOINT_XFER_BULK,
++	.wMaxPacketSize         = __constant_cpu_to_le16(1024),
++};
++
++static struct usb_ss_ep_comp_descriptor mtp_ss_out_comp_desc = {
++	.bLength                = sizeof(mtp_ss_out_comp_desc),
++	.bDescriptorType        = USB_DT_SS_ENDPOINT_COMP,
++	/* .bMaxBurst           = DYNAMIC, */
++};
++
++static struct usb_endpoint_descriptor mtp_highspeed_in_desc = {
++	.bLength                = USB_DT_ENDPOINT_SIZE,
++	.bDescriptorType        = USB_DT_ENDPOINT,
++	.bEndpointAddress       = USB_DIR_IN,
++	.bmAttributes           = USB_ENDPOINT_XFER_BULK,
++	.wMaxPacketSize         = __constant_cpu_to_le16(512),
++};
++
++static struct usb_endpoint_descriptor mtp_highspeed_out_desc = {
++	.bLength                = USB_DT_ENDPOINT_SIZE,
++	.bDescriptorType        = USB_DT_ENDPOINT,
++	.bEndpointAddress       = USB_DIR_OUT,
++	.bmAttributes           = USB_ENDPOINT_XFER_BULK,
++	.wMaxPacketSize         = __constant_cpu_to_le16(512),
++};
++
++static struct usb_endpoint_descriptor mtp_fullspeed_in_desc = {
++	.bLength                = USB_DT_ENDPOINT_SIZE,
++	.bDescriptorType        = USB_DT_ENDPOINT,
++	.bEndpointAddress       = USB_DIR_IN,
++	.bmAttributes           = USB_ENDPOINT_XFER_BULK,
++};
++
++static struct usb_endpoint_descriptor mtp_fullspeed_out_desc = {
++	.bLength                = USB_DT_ENDPOINT_SIZE,
++	.bDescriptorType        = USB_DT_ENDPOINT,
++	.bEndpointAddress       = USB_DIR_OUT,
++	.bmAttributes           = USB_ENDPOINT_XFER_BULK,
++};
++
++static struct usb_endpoint_descriptor mtp_intr_desc = {
++	.bLength                = USB_DT_ENDPOINT_SIZE,
++	.bDescriptorType        = USB_DT_ENDPOINT,
++	.bEndpointAddress       = USB_DIR_IN,
++	.bmAttributes           = USB_ENDPOINT_XFER_INT,
++	.wMaxPacketSize         = __constant_cpu_to_le16(INTR_BUFFER_SIZE),
++	.bInterval              = 6,
++};
++
++static struct usb_ss_ep_comp_descriptor mtp_intr_ss_comp_desc = {
++	.bLength                = sizeof(mtp_intr_ss_comp_desc),
++	.bDescriptorType        = USB_DT_SS_ENDPOINT_COMP,
++	.wBytesPerInterval      = cpu_to_le16(INTR_BUFFER_SIZE),
++};
++
++static struct usb_descriptor_header *fs_mtp_descs[] = {
++	(struct usb_descriptor_header *) &mtp_interface_desc,
++	(struct usb_descriptor_header *) &mtp_fullspeed_in_desc,
++	(struct usb_descriptor_header *) &mtp_fullspeed_out_desc,
++	(struct usb_descriptor_header *) &mtp_intr_desc,
++	NULL,
++};
++
++static struct usb_descriptor_header *hs_mtp_descs[] = {
++	(struct usb_descriptor_header *) &mtp_interface_desc,
++	(struct usb_descriptor_header *) &mtp_highspeed_in_desc,
++	(struct usb_descriptor_header *) &mtp_highspeed_out_desc,
++	(struct usb_descriptor_header *) &mtp_intr_desc,
++	NULL,
++};
++
++static struct usb_descriptor_header *ss_mtp_descs[] = {
++	(struct usb_descriptor_header *) &mtp_interface_desc,
++	(struct usb_descriptor_header *) &mtp_ss_in_desc,
++	(struct usb_descriptor_header *) &mtp_ss_in_comp_desc,
++	(struct usb_descriptor_header *) &mtp_ss_out_desc,
++	(struct usb_descriptor_header *) &mtp_ss_out_comp_desc,
++	(struct usb_descriptor_header *) &mtp_intr_desc,
++	(struct usb_descriptor_header *) &mtp_intr_ss_comp_desc,
++	NULL,
++};
++
++static struct usb_descriptor_header *fs_ptp_descs[] = {
++	(struct usb_descriptor_header *) &ptp_interface_desc,
++	(struct usb_descriptor_header *) &mtp_fullspeed_in_desc,
++	(struct usb_descriptor_header *) &mtp_fullspeed_out_desc,
++	(struct usb_descriptor_header *) &mtp_intr_desc,
++	NULL,
++};
++
++static struct usb_descriptor_header *hs_ptp_descs[] = {
++	(struct usb_descriptor_header *) &ptp_interface_desc,
++	(struct usb_descriptor_header *) &mtp_highspeed_in_desc,
++	(struct usb_descriptor_header *) &mtp_highspeed_out_desc,
++	(struct usb_descriptor_header *) &mtp_intr_desc,
++	NULL,
++};
++
++static struct usb_descriptor_header *ss_ptp_descs[] = {
++	(struct usb_descriptor_header *) &ptp_interface_desc,
++	(struct usb_descriptor_header *) &mtp_ss_in_desc,
++	(struct usb_descriptor_header *) &mtp_ss_in_comp_desc,
++	(struct usb_descriptor_header *) &mtp_ss_out_desc,
++	(struct usb_descriptor_header *) &mtp_ss_out_comp_desc,
++	(struct usb_descriptor_header *) &mtp_intr_desc,
++	(struct usb_descriptor_header *) &mtp_intr_ss_comp_desc,
++	NULL,
++};
++
++static struct usb_string mtp_string_defs[] = {
++	/* Naming interface "MTP" so libmtp will recognize us */
++	[INTERFACE_STRING_INDEX].s	= "MTP",
++	{  },	/* end of list */
++};
++
++static struct usb_gadget_strings mtp_string_table = {
++	.language		= 0x0409,	/* en-US */
++	.strings		= mtp_string_defs,
++};
++
++static struct usb_gadget_strings *mtp_strings[] = {
++	&mtp_string_table,
++	NULL,
++};
++
++/* Microsoft MTP OS String */
++static u8 mtp_os_string[] = {
++	18, /* sizeof(mtp_os_string) */
++	USB_DT_STRING,
++	/* Signature field: "MSFT100" */
++	'M', 0, 'S', 0, 'F', 0, 'T', 0, '1', 0, '0', 0, '0', 0,
++	/* vendor code */
++	1,
++	/* padding */
++	0
++};
++
++/* Microsoft Extended Configuration Descriptor Header Section */
++struct mtp_ext_config_desc_header {
++	__le32	dwLength;
++	__u16	bcdVersion;
++	__le16	wIndex;
++	__u8	bCount;
++	__u8	reserved[7];
++};
++
++/* Microsoft Extended Configuration Descriptor Function Section */
++struct mtp_ext_config_desc_function {
++	__u8	bFirstInterfaceNumber;
++	__u8	bInterfaceCount;
++	__u8	compatibleID[8];
++	__u8	subCompatibleID[8];
++	__u8	reserved[6];
++};
++
++/* MTP Extended Configuration Descriptor */
++struct {
++	struct mtp_ext_config_desc_header	header;
++	struct mtp_ext_config_desc_function    function;
++} mtp_ext_config_desc = {
++	.header = {
++		.dwLength = __constant_cpu_to_le32(sizeof(mtp_ext_config_desc)),
++		.bcdVersion = __constant_cpu_to_le16(0x0100),
++		.wIndex = __constant_cpu_to_le16(4),
++		.bCount = 1,
++	},
++	.function = {
++		.bFirstInterfaceNumber = 0,
++		.bInterfaceCount = 1,
++		.compatibleID = { 'M', 'T', 'P' },
++	},
++};
++
++struct mtp_device_status {
++	__le16	wLength;
++	__le16	wCode;
++};
++
++struct mtp_data_header {
++	/* length of packet, including this header */
++	__le32	length;
++	/* container type (2 for data packet) */
++	__le16	type;
++	/* MTP command code */
++	__le16	command;
++	/* MTP transaction ID */
++	__le32	transaction_id;
++};
++
++struct mtp_instance {
++	struct usb_function_instance func_inst;
++	const char *name;
++	struct mtp_dev *dev;
++	char mtp_ext_compat_id[16];
++	struct usb_os_desc mtp_os_desc;
++};
++
++/* temporary variable used between mtp_open() and mtp_gadget_bind() */
++static struct mtp_dev *_mtp_dev;
++
++static inline struct mtp_dev *func_to_mtp(struct usb_function *f)
++{
++	return container_of(f, struct mtp_dev, function);
++}
++
++static struct usb_request *mtp_request_new(struct usb_ep *ep, int buffer_size)
++{
++	struct usb_request *req = usb_ep_alloc_request(ep, GFP_KERNEL);
++
++	if (!req)
++		return NULL;
++
++	/* now allocate buffers for the requests */
++	req->buf = kmalloc(buffer_size, GFP_KERNEL);
++	if (!req->buf) {
++		usb_ep_free_request(ep, req);
++		return NULL;
++	}
++
++	return req;
++}
++
++static void mtp_request_free(struct usb_request *req, struct usb_ep *ep)
++{
++	if (req) {
++		kfree(req->buf);
++		usb_ep_free_request(ep, req);
++	}
++}
++
++static inline int mtp_lock(atomic_t *excl)
++{
++	if (atomic_inc_return(excl) == 1) {
++		return 0;
++	} else {
++		atomic_dec(excl);
++		return -1;
++	}
++}
++
++static inline void mtp_unlock(atomic_t *excl)
++{
++	atomic_dec(excl);
++}
++
++/* add a request to the tail of a list */
++static void mtp_req_put(struct mtp_dev *dev, struct list_head *head,
++		struct usb_request *req)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&dev->lock, flags);
++	list_add_tail(&req->list, head);
++	spin_unlock_irqrestore(&dev->lock, flags);
++}
++
++/* remove a request from the head of a list */
++static struct usb_request
++*mtp_req_get(struct mtp_dev *dev, struct list_head *head)
++{
++	unsigned long flags;
++	struct usb_request *req;
++
++	spin_lock_irqsave(&dev->lock, flags);
++	if (list_empty(head)) {
++		req = 0;
++	} else {
++		req = list_first_entry(head, struct usb_request, list);
++		list_del(&req->list);
++	}
++	spin_unlock_irqrestore(&dev->lock, flags);
++	return req;
++}
++
++static void mtp_complete_in(struct usb_ep *ep, struct usb_request *req)
++{
++	struct mtp_dev *dev = _mtp_dev;
++
++	if (req->status != 0)
++		dev->state = STATE_ERROR;
++
++	mtp_req_put(dev, &dev->tx_idle, req);
++
++	wake_up(&dev->write_wq);
++}
++
++static void mtp_complete_out(struct usb_ep *ep, struct usb_request *req)
++{
++	struct mtp_dev *dev = _mtp_dev;
++
++	dev->rx_done = 1;
++	if (req->status != 0)
++		dev->state = STATE_ERROR;
++
++	wake_up(&dev->read_wq);
++}
++
++static void mtp_complete_intr(struct usb_ep *ep, struct usb_request *req)
++{
++	struct mtp_dev *dev = _mtp_dev;
++
++	if (req->status != 0)
++		dev->state = STATE_ERROR;
++
++	mtp_req_put(dev, &dev->intr_idle, req);
++
++	wake_up(&dev->intr_wq);
++}
++
++static int mtp_create_bulk_endpoints(struct mtp_dev *dev,
++				struct usb_endpoint_descriptor *in_desc,
++				struct usb_endpoint_descriptor *out_desc,
++				struct usb_endpoint_descriptor *intr_desc)
++{
++	struct usb_composite_dev *cdev = dev->cdev;
++	struct usb_request *req;
++	struct usb_ep *ep;
++	int i;
++
++	DBG(cdev, "create_bulk_endpoints dev: %p\n", dev);
++
++	ep = usb_ep_autoconfig(cdev->gadget, in_desc);
++	if (!ep) {
++		DBG(cdev, "usb_ep_autoconfig for ep_in failed\n");
++		return -ENODEV;
++	}
++	DBG(cdev, "usb_ep_autoconfig for ep_in got %s\n", ep->name);
++	ep->driver_data = dev;		/* claim the endpoint */
++	dev->ep_in = ep;
++
++	ep = usb_ep_autoconfig(cdev->gadget, out_desc);
++	if (!ep) {
++		DBG(cdev, "usb_ep_autoconfig for ep_out failed\n");
++		return -ENODEV;
++	}
++	DBG(cdev, "usb_ep_autoconfig for mtp ep_out got %s\n", ep->name);
++	ep->driver_data = dev;		/* claim the endpoint */
++	dev->ep_out = ep;
++
++	ep = usb_ep_autoconfig(cdev->gadget, intr_desc);
++	if (!ep) {
++		DBG(cdev, "usb_ep_autoconfig for ep_intr failed\n");
++		return -ENODEV;
++	}
++	DBG(cdev, "usb_ep_autoconfig for mtp ep_intr got %s\n", ep->name);
++	ep->driver_data = dev;		/* claim the endpoint */
++	dev->ep_intr = ep;
++
++	/* now allocate requests for our endpoints */
++	for (i = 0; i < TX_REQ_MAX; i++) {
++		req = mtp_request_new(dev->ep_in, MTP_BULK_BUFFER_SIZE);
++		if (!req)
++			goto fail;
++		req->complete = mtp_complete_in;
++		mtp_req_put(dev, &dev->tx_idle, req);
++	}
++	for (i = 0; i < RX_REQ_MAX; i++) {
++		req = mtp_request_new(dev->ep_out, MTP_BULK_BUFFER_SIZE);
++		if (!req)
++			goto fail;
++		req->complete = mtp_complete_out;
++		dev->rx_req[i] = req;
++	}
++	for (i = 0; i < INTR_REQ_MAX; i++) {
++		req = mtp_request_new(dev->ep_intr, INTR_BUFFER_SIZE);
++		if (!req)
++			goto fail;
++		req->complete = mtp_complete_intr;
++		mtp_req_put(dev, &dev->intr_idle, req);
++	}
++
++	return 0;
++
++fail:
++	pr_err("mtp_bind() could not allocate requests\n");
++	return -1;
++}
++
++static ssize_t mtp_read(struct file *fp, char __user *buf,
++	size_t count, loff_t *pos)
++{
++	struct mtp_dev *dev = fp->private_data;
++	struct usb_composite_dev *cdev = dev->cdev;
++	struct usb_request *req;
++	ssize_t r = count;
++	unsigned xfer;
++	int ret = 0;
++
++	DBG(cdev, "mtp_read(%zu)\n", count);
++
++	if (count > MTP_BULK_BUFFER_SIZE)
++		return -EINVAL;
++
++	/* we will block until we're online */
++	DBG(cdev, "mtp_read: waiting for online state\n");
++	ret = wait_event_interruptible(dev->read_wq,
++		dev->state != STATE_OFFLINE);
++	if (ret < 0) {
++		r = ret;
++		goto done;
++	}
++	spin_lock_irq(&dev->lock);
++	if (dev->state == STATE_CANCELED) {
++		/* report cancelation to userspace */
++		dev->state = STATE_READY;
++		spin_unlock_irq(&dev->lock);
++		return -ECANCELED;
++	}
++	dev->state = STATE_BUSY;
++	spin_unlock_irq(&dev->lock);
++
++requeue_req:
++	/* queue a request */
++	req = dev->rx_req[0];
++	req->length = count;
++	dev->rx_done = 0;
++	ret = usb_ep_queue(dev->ep_out, req, GFP_KERNEL);
++	if (ret < 0) {
++		r = -EIO;
++		goto done;
++	} else {
++		DBG(cdev, "rx %p queue\n", req);
++	}
++
++	/* wait for a request to complete */
++	ret = wait_event_interruptible(dev->read_wq, dev->rx_done);
++	if (ret < 0) {
++		r = ret;
++		usb_ep_dequeue(dev->ep_out, req);
++		goto done;
++	}
++	if (dev->state == STATE_BUSY) {
++		/* If we got a 0-len packet, throw it back and try again. */
++		if (req->actual == 0)
++			goto requeue_req;
++
++		DBG(cdev, "rx %p %d\n", req, req->actual);
++		xfer = (req->actual < count) ? req->actual : count;
++		r = xfer;
++		if (copy_to_user(buf, req->buf, xfer))
++			r = -EFAULT;
++	} else
++		r = -EIO;
++
++done:
++	spin_lock_irq(&dev->lock);
++	if (dev->state == STATE_CANCELED)
++		r = -ECANCELED;
++	else if (dev->state != STATE_OFFLINE)
++		dev->state = STATE_READY;
++	spin_unlock_irq(&dev->lock);
++
++	DBG(cdev, "mtp_read returning %zd\n", r);
++	return r;
++}
++
++static ssize_t mtp_write(struct file *fp, const char __user *buf,
++	size_t count, loff_t *pos)
++{
++	struct mtp_dev *dev = fp->private_data;
++	struct usb_composite_dev *cdev = dev->cdev;
++	struct usb_request *req = 0;
++	ssize_t r = count;
++	unsigned xfer;
++	int sendZLP = 0;
++	int ret;
++
++	DBG(cdev, "mtp_write(%zu)\n", count);
++
++	spin_lock_irq(&dev->lock);
++	if (dev->state == STATE_CANCELED) {
++		/* report cancelation to userspace */
++		dev->state = STATE_READY;
++		spin_unlock_irq(&dev->lock);
++		return -ECANCELED;
++	}
++	if (dev->state == STATE_OFFLINE) {
++		spin_unlock_irq(&dev->lock);
++		return -ENODEV;
++	}
++	dev->state = STATE_BUSY;
++	spin_unlock_irq(&dev->lock);
++
++	/* we need to send a zero length packet to signal the end of transfer
++	 * if the transfer size is aligned to a packet boundary.
++	 */
++	if ((count & (dev->ep_in->maxpacket - 1)) == 0)
++		sendZLP = 1;
++
++	while (count > 0 || sendZLP) {
++		/* so we exit after sending ZLP */
++		if (count == 0)
++			sendZLP = 0;
++
++		if (dev->state != STATE_BUSY) {
++			DBG(cdev, "mtp_write dev->error\n");
++			r = -EIO;
++			break;
++		}
++
++		/* get an idle tx request to use */
++		req = 0;
++		ret = wait_event_interruptible(dev->write_wq,
++			((req = mtp_req_get(dev, &dev->tx_idle))
++				|| dev->state != STATE_BUSY));
++		if (!req) {
++			r = ret;
++			break;
++		}
++
++		if (count > MTP_BULK_BUFFER_SIZE)
++			xfer = MTP_BULK_BUFFER_SIZE;
++		else
++			xfer = count;
++		if (xfer && copy_from_user(req->buf, buf, xfer)) {
++			r = -EFAULT;
++			break;
++		}
++
++		req->length = xfer;
++		ret = usb_ep_queue(dev->ep_in, req, GFP_KERNEL);
++		if (ret < 0) {
++			DBG(cdev, "mtp_write: xfer error %d\n", ret);
++			r = -EIO;
++			break;
++		}
++
++		buf += xfer;
++		count -= xfer;
++
++		/* zero this so we don't try to free it on error exit */
++		req = 0;
++	}
++
++	if (req)
++		mtp_req_put(dev, &dev->tx_idle, req);
++
++	spin_lock_irq(&dev->lock);
++	if (dev->state == STATE_CANCELED)
++		r = -ECANCELED;
++	else if (dev->state != STATE_OFFLINE)
++		dev->state = STATE_READY;
++	spin_unlock_irq(&dev->lock);
++
++	DBG(cdev, "mtp_write returning %zd\n", r);
++	return r;
++}
++
++/* read from a local file and write to USB */
++static void send_file_work(struct work_struct *data)
++{
++	struct mtp_dev *dev = container_of(data, struct mtp_dev,
++						send_file_work);
++	struct usb_composite_dev *cdev = dev->cdev;
++	struct usb_request *req = 0;
++	struct mtp_data_header *header;
++	struct file *filp;
++	loff_t offset;
++	int64_t count;
++	int xfer, ret, hdr_size;
++	int r = 0;
++	int sendZLP = 0;
++
++	/* read our parameters */
++	smp_rmb();
++	filp = dev->xfer_file;
++	offset = dev->xfer_file_offset;
++	count = dev->xfer_file_length;
++
++	DBG(cdev, "send_file_work(%lld %lld)\n", offset, count);
++
++	if (dev->xfer_send_header) {
++		hdr_size = sizeof(struct mtp_data_header);
++		count += hdr_size;
++	} else {
++		hdr_size = 0;
++	}
++
++	/* we need to send a zero length packet to signal the end of transfer
++	 * if the transfer size is aligned to a packet boundary.
++	 */
++	if ((count & (dev->ep_in->maxpacket - 1)) == 0)
++		sendZLP = 1;
++
++	while (count > 0 || sendZLP) {
++		/* so we exit after sending ZLP */
++		if (count == 0)
++			sendZLP = 0;
++
++		/* get an idle tx request to use */
++		req = 0;
++		ret = wait_event_interruptible(dev->write_wq,
++			(req = mtp_req_get(dev, &dev->tx_idle))
++			|| dev->state != STATE_BUSY);
++		if (dev->state == STATE_CANCELED) {
++			r = -ECANCELED;
++			break;
++		}
++		if (!req) {
++			r = ret;
++			break;
++		}
++
++		if (count > MTP_BULK_BUFFER_SIZE)
++			xfer = MTP_BULK_BUFFER_SIZE;
++		else
++			xfer = count;
++
++		if (hdr_size) {
++			/* prepend MTP data header */
++			header = (struct mtp_data_header *)req->buf;
++			header->length = __cpu_to_le32(count);
++			header->type = __cpu_to_le16(2); /* data packet */
++			header->command = __cpu_to_le16(dev->xfer_command);
++			header->transaction_id =
++					__cpu_to_le32(dev->xfer_transaction_id);
++		}
++
++		ret = vfs_read(filp, req->buf + hdr_size, xfer - hdr_size,
++								&offset);
++		if (ret < 0) {
++			r = ret;
++			break;
++		}
++		xfer = ret + hdr_size;
++		hdr_size = 0;
++
++		req->length = xfer;
++		ret = usb_ep_queue(dev->ep_in, req, GFP_KERNEL);
++		if (ret < 0) {
++			DBG(cdev, "send_file_work: xfer error %d\n", ret);
++			dev->state = STATE_ERROR;
++			r = -EIO;
++			break;
++		}
++
++		count -= xfer;
++
++		/* zero this so we don't try to free it on error exit */
++		req = 0;
++	}
++
++	if (req)
++		mtp_req_put(dev, &dev->tx_idle, req);
++
++	DBG(cdev, "send_file_work returning %d\n", r);
++	/* write the result */
++	dev->xfer_result = r;
++	smp_wmb();
++}
++
++/* read from USB and write to a local file */
++static void receive_file_work(struct work_struct *data)
++{
++	struct mtp_dev *dev = container_of(data, struct mtp_dev,
++						receive_file_work);
++	struct usb_composite_dev *cdev = dev->cdev;
++	struct usb_request *read_req = NULL, *write_req = NULL;
++	struct file *filp;
++	loff_t offset;
++	int64_t count;
++	int ret, cur_buf = 0;
++	int r = 0;
++
++	/* read our parameters */
++	smp_rmb();
++	filp = dev->xfer_file;
++	offset = dev->xfer_file_offset;
++	count = dev->xfer_file_length;
++
++	DBG(cdev, "receive_file_work(%lld)\n", count);
++
++	while (count > 0 || write_req) {
++		if (count > 0) {
++			/* queue a request */
++			read_req = dev->rx_req[cur_buf];
++			cur_buf = (cur_buf + 1) % RX_REQ_MAX;
++
++			read_req->length = (count > MTP_BULK_BUFFER_SIZE
++					? MTP_BULK_BUFFER_SIZE : count);
++			dev->rx_done = 0;
++			ret = usb_ep_queue(dev->ep_out, read_req, GFP_KERNEL);
++			if (ret < 0) {
++				r = -EIO;
++				dev->state = STATE_ERROR;
++				break;
++			}
++		}
++
++		if (write_req) {
++			DBG(cdev, "rx %p %d\n", write_req, write_req->actual);
++			ret = vfs_write(filp, write_req->buf, write_req->actual,
++				&offset);
++			DBG(cdev, "vfs_write %d\n", ret);
++			if (ret != write_req->actual) {
++				r = -EIO;
++				dev->state = STATE_ERROR;
++				break;
++			}
++			write_req = NULL;
++		}
++
++		if (read_req) {
++			/* wait for our last read to complete */
++			ret = wait_event_interruptible(dev->read_wq,
++				dev->rx_done || dev->state != STATE_BUSY);
++			if (dev->state == STATE_CANCELED) {
++				r = -ECANCELED;
++				if (!dev->rx_done)
++					usb_ep_dequeue(dev->ep_out, read_req);
++				break;
++			}
++			/* if xfer_file_length is 0xFFFFFFFF, then we read until
++			 * we get a zero length packet
++			 */
++			if (count != 0xFFFFFFFF)
++				count -= read_req->actual;
++			if (read_req->actual < read_req->length) {
++				/*
++				 * short packet is used to signal EOF for
++				 * sizes > 4 gig
++				 */
++				DBG(cdev, "got short packet\n");
++				count = 0;
++			}
++
++			write_req = read_req;
++			read_req = NULL;
++		}
++	}
++
++	DBG(cdev, "receive_file_work returning %d\n", r);
++	/* write the result */
++	dev->xfer_result = r;
++	smp_wmb();
++}
++
++static int mtp_send_event(struct mtp_dev *dev, struct mtp_event *event)
++{
++	struct usb_request *req = NULL;
++	int ret;
++	int length = event->length;
++
++	DBG(dev->cdev, "mtp_send_event(%zu)\n", event->length);
++
++	if (length < 0 || length > INTR_BUFFER_SIZE)
++		return -EINVAL;
++	if (dev->state == STATE_OFFLINE)
++		return -ENODEV;
++
++	ret = wait_event_interruptible_timeout(dev->intr_wq,
++			(req = mtp_req_get(dev, &dev->intr_idle)),
++			msecs_to_jiffies(1000));
++	if (!req)
++		return -ETIME;
++
++	if (copy_from_user(req->buf, (void __user *)event->data, length)) {
++		mtp_req_put(dev, &dev->intr_idle, req);
++		return -EFAULT;
++	}
++	req->length = length;
++	ret = usb_ep_queue(dev->ep_intr, req, GFP_KERNEL);
++	if (ret)
++		mtp_req_put(dev, &dev->intr_idle, req);
++
++	return ret;
++}
++
++static long mtp_ioctl(struct file *fp, unsigned code, unsigned long value)
++{
++	struct mtp_dev *dev = fp->private_data;
++	struct file *filp = NULL;
++	int ret = -EINVAL;
++
++	if (mtp_lock(&dev->ioctl_excl))
++		return -EBUSY;
++
++	switch (code) {
++	case MTP_SEND_FILE:
++	case MTP_RECEIVE_FILE:
++	case MTP_SEND_FILE_WITH_HEADER:
++	{
++		struct mtp_file_range	mfr;
++		struct work_struct *work;
++
++		spin_lock_irq(&dev->lock);
++		if (dev->state == STATE_CANCELED) {
++			/* report cancelation to userspace */
++			dev->state = STATE_READY;
++			spin_unlock_irq(&dev->lock);
++			ret = -ECANCELED;
++			goto out;
++		}
++		if (dev->state == STATE_OFFLINE) {
++			spin_unlock_irq(&dev->lock);
++			ret = -ENODEV;
++			goto out;
++		}
++		dev->state = STATE_BUSY;
++		spin_unlock_irq(&dev->lock);
++
++		if (copy_from_user(&mfr, (void __user *)value, sizeof(mfr))) {
++			ret = -EFAULT;
++			goto fail;
++		}
++		/* hold a reference to the file while we are working with it */
++		filp = fget(mfr.fd);
++		if (!filp) {
++			ret = -EBADF;
++			goto fail;
++		}
++
++		/* write the parameters */
++		dev->xfer_file = filp;
++		dev->xfer_file_offset = mfr.offset;
++		dev->xfer_file_length = mfr.length;
++		smp_wmb();
++
++		if (code == MTP_SEND_FILE_WITH_HEADER) {
++			work = &dev->send_file_work;
++			dev->xfer_send_header = 1;
++			dev->xfer_command = mfr.command;
++			dev->xfer_transaction_id = mfr.transaction_id;
++		} else if (code == MTP_SEND_FILE) {
++			work = &dev->send_file_work;
++			dev->xfer_send_header = 0;
++		} else {
++			work = &dev->receive_file_work;
++		}
++
++		/* We do the file transfer on a work queue so it will run
++		 * in kernel context, which is necessary for vfs_read and
++		 * vfs_write to use our buffers in the kernel address space.
++		 */
++		queue_work(dev->wq, work);
++		/* wait for operation to complete */
++		flush_workqueue(dev->wq);
++		fput(filp);
++
++		/* read the result */
++		smp_rmb();
++		ret = dev->xfer_result;
++		break;
++	}
++	case MTP_SEND_EVENT:
++	{
++		struct mtp_event	event;
++		/* return here so we don't change dev->state below,
++		 * which would interfere with bulk transfer state.
++		 */
++		if (copy_from_user(&event, (void __user *)value, sizeof(event)))
++			ret = -EFAULT;
++		else
++			ret = mtp_send_event(dev, &event);
++		goto out;
++	}
++	}
++
++fail:
++	spin_lock_irq(&dev->lock);
++	if (dev->state == STATE_CANCELED)
++		ret = -ECANCELED;
++	else if (dev->state != STATE_OFFLINE)
++		dev->state = STATE_READY;
++	spin_unlock_irq(&dev->lock);
++out:
++	mtp_unlock(&dev->ioctl_excl);
++	DBG(dev->cdev, "ioctl returning %d\n", ret);
++	return ret;
++}
++
++static int mtp_open(struct inode *ip, struct file *fp)
++{
++	printk(KERN_INFO "mtp_open\n");
++	if (mtp_lock(&_mtp_dev->open_excl))
++		return -EBUSY;
++
++	/* clear any error condition */
++	if (_mtp_dev->state != STATE_OFFLINE)
++		_mtp_dev->state = STATE_READY;
++
++	fp->private_data = _mtp_dev;
++	return 0;
++}
++
++static int mtp_release(struct inode *ip, struct file *fp)
++{
++	printk(KERN_INFO "mtp_release\n");
++
++	mtp_unlock(&_mtp_dev->open_excl);
++	return 0;
++}
++
++/* file operations for /dev/mtp_usb */
++static const struct file_operations mtp_fops = {
++	.owner = THIS_MODULE,
++	.read = mtp_read,
++	.write = mtp_write,
++	.unlocked_ioctl = mtp_ioctl,
++	.open = mtp_open,
++	.release = mtp_release,
++};
++
++static struct miscdevice mtp_device = {
++	.minor = MISC_DYNAMIC_MINOR,
++	.name = mtp_shortname,
++	.fops = &mtp_fops,
++};
++
++static int mtp_ctrlrequest(struct usb_composite_dev *cdev,
++				const struct usb_ctrlrequest *ctrl)
++{
++	struct mtp_dev *dev = _mtp_dev;
++	int	value = -EOPNOTSUPP;
++	u16	w_index = le16_to_cpu(ctrl->wIndex);
++	u16	w_value = le16_to_cpu(ctrl->wValue);
++	u16	w_length = le16_to_cpu(ctrl->wLength);
++	unsigned long	flags;
++
++	VDBG(cdev, "mtp_ctrlrequest "
++			"%02x.%02x v%04x i%04x l%u\n",
++			ctrl->bRequestType, ctrl->bRequest,
++			w_value, w_index, w_length);
++
++	/* Handle MTP OS string */
++	if (ctrl->bRequestType ==
++			(USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE)
++			&& ctrl->bRequest == USB_REQ_GET_DESCRIPTOR
++			&& (w_value >> 8) == USB_DT_STRING
++			&& (w_value & 0xFF) == MTP_OS_STRING_ID) {
++		value = (w_length < sizeof(mtp_os_string)
++				? w_length : sizeof(mtp_os_string));
++		memcpy(cdev->req->buf, mtp_os_string, value);
++	} else if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_VENDOR) {
++		/* Handle MTP OS descriptor */
++		DBG(cdev, "vendor request: %d index: %d value: %d length: %d\n",
++			ctrl->bRequest, w_index, w_value, w_length);
++
++		if (ctrl->bRequest == 1
++				&& (ctrl->bRequestType & USB_DIR_IN)
++				&& (w_index == 4 || w_index == 5)) {
++			value = (w_length < sizeof(mtp_ext_config_desc) ?
++					w_length : sizeof(mtp_ext_config_desc));
++			memcpy(cdev->req->buf, &mtp_ext_config_desc, value);
++		}
++	} else if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS) {
++		DBG(cdev, "class request: %d index: %d value: %d length: %d\n",
++			ctrl->bRequest, w_index, w_value, w_length);
++
++		if (ctrl->bRequest == MTP_REQ_CANCEL && w_index == 0
++				&& w_value == 0) {
++			DBG(cdev, "MTP_REQ_CANCEL\n");
++
++			spin_lock_irqsave(&dev->lock, flags);
++			if (dev->state == STATE_BUSY) {
++				dev->state = STATE_CANCELED;
++				wake_up(&dev->read_wq);
++				wake_up(&dev->write_wq);
++			}
++			spin_unlock_irqrestore(&dev->lock, flags);
++
++			/* We need to queue a request to read the remaining
++			 *  bytes, but we don't actually need to look at
++			 * the contents.
++			 */
++			value = w_length;
++		} else if (ctrl->bRequest == MTP_REQ_GET_DEVICE_STATUS
++				&& w_index == 0 && w_value == 0) {
++			struct mtp_device_status *status = cdev->req->buf;
++
++			status->wLength =
++				__constant_cpu_to_le16(sizeof(*status));
++
++			DBG(cdev, "MTP_REQ_GET_DEVICE_STATUS\n");
++			spin_lock_irqsave(&dev->lock, flags);
++			/* device status is "busy" until we report
++			 * the cancelation to userspace
++			 */
++			if (dev->state == STATE_CANCELED)
++				status->wCode =
++					__cpu_to_le16(MTP_RESPONSE_DEVICE_BUSY);
++			else
++				status->wCode =
++					__cpu_to_le16(MTP_RESPONSE_OK);
++			spin_unlock_irqrestore(&dev->lock, flags);
++			value = sizeof(*status);
++		}
++	}
++
++	/* respond with data transfer or status phase? */
++	if (value >= 0) {
++		int rc;
++
++		cdev->req->zero = value < w_length;
++		cdev->req->length = value;
++		rc = usb_ep_queue(cdev->gadget->ep0, cdev->req, GFP_ATOMIC);
++		if (rc < 0)
++			ERROR(cdev, "%s: response queue error\n", __func__);
++	}
++	return value;
++}
++
++static int
++mtp_function_bind(struct usb_configuration *c, struct usb_function *f)
++{
++	struct usb_composite_dev *cdev = c->cdev;
++	struct mtp_dev	*dev = func_to_mtp(f);
++	int			id;
++	int			ret;
++	struct mtp_instance *fi_mtp;
++
++	dev->cdev = cdev;
++	DBG(cdev, "mtp_function_bind dev: %p\n", dev);
++
++	/* allocate interface ID(s) */
++	id = usb_interface_id(c, f);
++	if (id < 0)
++		return id;
++	mtp_interface_desc.bInterfaceNumber = id;
++
++	if (mtp_string_defs[INTERFACE_STRING_INDEX].id == 0) {
++		ret = usb_string_id(c->cdev);
++		if (ret < 0)
++			return ret;
++		mtp_string_defs[INTERFACE_STRING_INDEX].id = ret;
++		mtp_interface_desc.iInterface = ret;
++	}
++
++	fi_mtp = container_of(f->fi, struct mtp_instance, func_inst);
++
++	if (cdev->use_os_string) {
++		f->os_desc_table = kzalloc(sizeof(*f->os_desc_table),
++					GFP_KERNEL);
++		if (!f->os_desc_table)
++			return -ENOMEM;
++		f->os_desc_n = 1;
++		f->os_desc_table[0].os_desc = &fi_mtp->mtp_os_desc;
++	}
++
++	/* allocate endpoints */
++	ret = mtp_create_bulk_endpoints(dev, &mtp_fullspeed_in_desc,
++			&mtp_fullspeed_out_desc, &mtp_intr_desc);
++	if (ret)
++		return ret;
++
++	/* support high speed hardware */
++	if (gadget_is_dualspeed(c->cdev->gadget)) {
++		mtp_highspeed_in_desc.bEndpointAddress =
++			mtp_fullspeed_in_desc.bEndpointAddress;
++		mtp_highspeed_out_desc.bEndpointAddress =
++			mtp_fullspeed_out_desc.bEndpointAddress;
++	}
++	/* support super speed hardware */
++	if (gadget_is_superspeed(c->cdev->gadget)) {
++		unsigned max_burst;
++
++		/* Calculate bMaxBurst, we know packet size is 1024 */
++		max_burst = min_t(unsigned, MTP_BULK_BUFFER_SIZE / 1024, 15);
++		mtp_ss_in_desc.bEndpointAddress =
++			mtp_fullspeed_in_desc.bEndpointAddress;
++		mtp_ss_in_comp_desc.bMaxBurst = max_burst;
++		mtp_ss_out_desc.bEndpointAddress =
++			mtp_fullspeed_out_desc.bEndpointAddress;
++		mtp_ss_out_comp_desc.bMaxBurst = max_burst;
++	}
++
++	DBG(cdev, "%s speed %s: IN/%s, OUT/%s\n",
++		gadget_is_superspeed(c->cdev->gadget) ? "super" :
++		(gadget_is_dualspeed(c->cdev->gadget) ? "dual" : "full"),
++		f->name, dev->ep_in->name, dev->ep_out->name);
++	return 0;
++}
++
++static void
++mtp_function_unbind(struct usb_configuration *c, struct usb_function *f)
++{
++	struct mtp_dev	*dev = func_to_mtp(f);
++	struct usb_request *req;
++	int i;
++
++	mtp_string_defs[INTERFACE_STRING_INDEX].id = 0;
++	while ((req = mtp_req_get(dev, &dev->tx_idle)))
++		mtp_request_free(req, dev->ep_in);
++	for (i = 0; i < RX_REQ_MAX; i++)
++		mtp_request_free(dev->rx_req[i], dev->ep_out);
++	while ((req = mtp_req_get(dev, &dev->intr_idle)))
++		mtp_request_free(req, dev->ep_intr);
++	dev->state = STATE_OFFLINE;
++	kfree(f->os_desc_table);
++	f->os_desc_n = 0;
++}
++
++static int mtp_function_set_alt(struct usb_function *f,
++		unsigned intf, unsigned alt)
++{
++	struct mtp_dev	*dev = func_to_mtp(f);
++	struct usb_composite_dev *cdev = f->config->cdev;
++	int ret;
++
++	DBG(cdev, "mtp_function_set_alt intf: %d alt: %d\n", intf, alt);
++
++	ret = config_ep_by_speed(cdev->gadget, f, dev->ep_in);
++	if (ret)
++		return ret;
++
++	ret = usb_ep_enable(dev->ep_in);
++	if (ret)
++		return ret;
++
++	ret = config_ep_by_speed(cdev->gadget, f, dev->ep_out);
++	if (ret)
++		return ret;
++
++	ret = usb_ep_enable(dev->ep_out);
++	if (ret) {
++		usb_ep_disable(dev->ep_in);
++		return ret;
++	}
++
++	ret = config_ep_by_speed(cdev->gadget, f, dev->ep_intr);
++	if (ret)
++		return ret;
++
++	ret = usb_ep_enable(dev->ep_intr);
++	if (ret) {
++		usb_ep_disable(dev->ep_out);
++		usb_ep_disable(dev->ep_in);
++		return ret;
++	}
++	dev->state = STATE_READY;
++
++	/* readers may be blocked waiting for us to go online */
++	wake_up(&dev->read_wq);
++	return 0;
++}
++
++static void mtp_function_disable(struct usb_function *f)
++{
++	struct mtp_dev	*dev = func_to_mtp(f);
++	struct usb_composite_dev	*cdev = dev->cdev;
++
++	DBG(cdev, "mtp_function_disable\n");
++	dev->state = STATE_OFFLINE;
++	usb_ep_disable(dev->ep_in);
++	usb_ep_disable(dev->ep_out);
++	usb_ep_disable(dev->ep_intr);
++
++	/* readers may be blocked waiting for us to go online */
++	wake_up(&dev->read_wq);
++
++	VDBG(cdev, "%s disabled\n", dev->function.name);
++}
++
++static int __mtp_setup(struct mtp_instance *fi_mtp)
++{
++	struct mtp_dev *dev;
++	int ret;
++
++	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
++
++	if (fi_mtp != NULL)
++		fi_mtp->dev = dev;
++
++	if (!dev)
++		return -ENOMEM;
++
++	spin_lock_init(&dev->lock);
++	init_waitqueue_head(&dev->read_wq);
++	init_waitqueue_head(&dev->write_wq);
++	init_waitqueue_head(&dev->intr_wq);
++	atomic_set(&dev->open_excl, 0);
++	atomic_set(&dev->ioctl_excl, 0);
++	INIT_LIST_HEAD(&dev->tx_idle);
++	INIT_LIST_HEAD(&dev->intr_idle);
++
++	dev->wq = create_singlethread_workqueue("f_mtp");
++	if (!dev->wq) {
++		ret = -ENOMEM;
++		goto err1;
++	}
++	INIT_WORK(&dev->send_file_work, send_file_work);
++	INIT_WORK(&dev->receive_file_work, receive_file_work);
++
++	_mtp_dev = dev;
++
++	ret = misc_register(&mtp_device);
++	if (ret)
++		goto err2;
++
++	return 0;
++
++err2:
++	destroy_workqueue(dev->wq);
++err1:
++	_mtp_dev = NULL;
++	kfree(dev);
++	printk(KERN_ERR "mtp gadget driver failed to initialize\n");
++	return ret;
++}
++
++static int mtp_setup_configfs(struct mtp_instance *fi_mtp)
++{
++	return __mtp_setup(fi_mtp);
++}
++
++
++static void mtp_cleanup(void)
++{
++	struct mtp_dev *dev = _mtp_dev;
++
++	if (!dev)
++		return;
++
++	misc_deregister(&mtp_device);
++	destroy_workqueue(dev->wq);
++	_mtp_dev = NULL;
++	kfree(dev);
++}
++
++static struct mtp_instance *to_mtp_instance(struct config_item *item)
++{
++	return container_of(to_config_group(item), struct mtp_instance,
++		func_inst.group);
++}
++
++static void mtp_attr_release(struct config_item *item)
++{
++	struct mtp_instance *fi_mtp = to_mtp_instance(item);
++
++	usb_put_function_instance(&fi_mtp->func_inst);
++}
++
++static struct configfs_item_operations mtp_item_ops = {
++	.release        = mtp_attr_release,
++};
++
++static struct config_item_type mtp_func_type = {
++	.ct_item_ops    = &mtp_item_ops,
++	.ct_owner       = THIS_MODULE,
++};
++
++
++static struct mtp_instance *to_fi_mtp(struct usb_function_instance *fi)
++{
++	return container_of(fi, struct mtp_instance, func_inst);
++}
++
++static int mtp_set_inst_name(struct usb_function_instance *fi, const char *name)
++{
++	struct mtp_instance *fi_mtp;
++	char *ptr;
++	int name_len;
++
++	name_len = strlen(name) + 1;
++	if (name_len > MAX_INST_NAME_LEN)
++		return -ENAMETOOLONG;
++
++	ptr = kstrndup(name, name_len, GFP_KERNEL);
++	if (!ptr)
++		return -ENOMEM;
++
++	fi_mtp = to_fi_mtp(fi);
++	fi_mtp->name = ptr;
++
++	return 0;
++}
++
++static void mtp_free_inst(struct usb_function_instance *fi)
++{
++	struct mtp_instance *fi_mtp;
++
++	fi_mtp = to_fi_mtp(fi);
++	kfree(fi_mtp->name);
++	mtp_cleanup();
++	//kfree(fi_mtp->mtp_os_desc.group.default_groups);
++	kfree(fi_mtp);
++}
++
++struct usb_function_instance *alloc_inst_mtp_ptp(bool mtp_config)
++{
++	struct mtp_instance *fi_mtp;
++	int ret = 0;
++	struct usb_os_desc *descs[1];
++	char *names[1];
++
++	fi_mtp = kzalloc(sizeof(*fi_mtp), GFP_KERNEL);
++	if (!fi_mtp)
++		return ERR_PTR(-ENOMEM);
++	fi_mtp->func_inst.set_inst_name = mtp_set_inst_name;
++	fi_mtp->func_inst.free_func_inst = mtp_free_inst;
++
++	fi_mtp->mtp_os_desc.ext_compat_id = fi_mtp->mtp_ext_compat_id;
++	INIT_LIST_HEAD(&fi_mtp->mtp_os_desc.ext_prop);
++	descs[0] = &fi_mtp->mtp_os_desc;
++	names[0] = "MTP";
++	config_group_init_type_name(&fi_mtp->func_inst.group,
++					"", &mtp_func_type);
++	usb_os_desc_prepare_interf_dir(&fi_mtp->func_inst.group, 1,
++					descs, names, THIS_MODULE);
++
++	if (mtp_config) {
++		ret = mtp_setup_configfs(fi_mtp);
++		if (ret) {
++			kfree(fi_mtp);
++			pr_err("Error setting MTP\n");
++			return ERR_PTR(ret);
++		}
++	} else
++		fi_mtp->dev = _mtp_dev;
++
++	return  &fi_mtp->func_inst;
++}
++EXPORT_SYMBOL_GPL(alloc_inst_mtp_ptp);
++
++static struct usb_function_instance *mtp_alloc_inst(void)
++{
++		return alloc_inst_mtp_ptp(true);
++}
++
++static int mtp_ctrlreq_configfs(struct usb_function *f,
++				const struct usb_ctrlrequest *ctrl)
++{
++	return mtp_ctrlrequest(f->config->cdev, ctrl);
++}
++
++static void mtp_free(struct usb_function *f)
++{
++	/*NO-OP: no function specific resource allocation in mtp_alloc*/
++}
++
++struct usb_function *function_alloc_mtp_ptp(struct usb_function_instance *fi,
++					bool mtp_config)
++{
++	struct mtp_instance *fi_mtp = to_fi_mtp(fi);
++	struct mtp_dev *dev;
++
++	/*
++	 * PTP piggybacks on MTP function so make sure we have
++	 * created MTP function before we associate this PTP
++	 * function with a gadget configuration.
++	 */
++	if (fi_mtp->dev == NULL) {
++		pr_err("Error: Create MTP function before linking"
++				" PTP function with a gadget configuration\n");
++		pr_err("\t1: Delete existing PTP function if any\n");
++		pr_err("\t2: Create MTP function\n");
++		pr_err("\t3: Create and symlink PTP function"
++				" with a gadget configuration\n");
++		return ERR_PTR(-EINVAL); /* Invalid Configuration */
++	}
++
++	dev = fi_mtp->dev;
++	dev->function.name = DRIVER_NAME;
++	dev->function.strings = mtp_strings;
++	if (mtp_config) {
++		dev->function.fs_descriptors = fs_mtp_descs;
++		dev->function.hs_descriptors = hs_mtp_descs;
++		dev->function.ss_descriptors = ss_mtp_descs;
++	} else {
++		dev->function.fs_descriptors = fs_ptp_descs;
++		dev->function.hs_descriptors = hs_ptp_descs;
++		dev->function.ss_descriptors = ss_ptp_descs;
++	}
++	dev->function.bind = mtp_function_bind;
++	dev->function.unbind = mtp_function_unbind;
++	dev->function.set_alt = mtp_function_set_alt;
++	dev->function.disable = mtp_function_disable;
++	dev->function.setup = mtp_ctrlreq_configfs;
++	dev->function.free_func = mtp_free;
++
++	return &dev->function;
++}
++EXPORT_SYMBOL_GPL(function_alloc_mtp_ptp);
++
++static struct usb_function *mtp_alloc(struct usb_function_instance *fi)
++{
++	return function_alloc_mtp_ptp(fi, true);
++}
++
++DECLARE_USB_FUNCTION_INIT(mtp, mtp_alloc_inst, mtp_alloc);
++MODULE_LICENSE("GPL");
+diff --git a/drivers/usb/gadget/function/f_mtp.h b/drivers/usb/gadget/function/f_mtp.h
+new file mode 100644
+index 000000000..7adb1ff08
+--- /dev/null
++++ b/drivers/usb/gadget/function/f_mtp.h
+@@ -0,0 +1,18 @@
++/*
++ * Copyright (C) 2014 Google, Inc.
++ * Author: Badhri Jagan Sridharan <badhri@android.com>
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++extern struct usb_function_instance *alloc_inst_mtp_ptp(bool mtp_config);
++extern struct usb_function *function_alloc_mtp_ptp(
++			struct usb_function_instance *fi, bool mtp_config);
+diff --git a/drivers/usb/gadget/function/f_ncm.c b/drivers/usb/gadget/function/f_ncm.c
+index 855127249..dc8f078f9 100644
+--- a/drivers/usb/gadget/function/f_ncm.c
++++ b/drivers/usb/gadget/function/f_ncm.c
+@@ -72,9 +72,7 @@ struct f_ncm {
+ 	struct sk_buff			*skb_tx_data;
+ 	struct sk_buff			*skb_tx_ndp;
+ 	u16				ndp_dgram_count;
+-	bool				timer_force_tx;
+ 	struct hrtimer			task_timer;
+-	bool				timer_stopping;
+ };
+ 
+ static inline struct f_ncm *func_to_ncm(struct usb_function *f)
+@@ -890,7 +888,6 @@ static int ncm_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
+ 
+ 		if (ncm->port.in_ep->enabled) {
+ 			DBG(cdev, "reset ncm\n");
+-			ncm->timer_stopping = true;
+ 			ncm->netdev = NULL;
+ 			gether_disconnect(&ncm->port);
+ 			ncm_reset_values(ncm);
+@@ -928,7 +925,6 @@ static int ncm_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
+ 			if (IS_ERR(net))
+ 				return PTR_ERR(net);
+ 			ncm->netdev = net;
+-			ncm->timer_stopping = false;
+ 		}
+ 
+ 		spin_lock(&ncm->lock);
+@@ -1017,22 +1013,20 @@ static struct sk_buff *ncm_wrap_ntb(struct gether *port,
+ {
+ 	struct f_ncm	*ncm = func_to_ncm(&port->func);
+ 	struct sk_buff	*skb2 = NULL;
+-	int		ncb_len = 0;
+-	__le16		*ntb_data;
+-	__le16		*ntb_ndp;
+-	int		dgram_pad;
+-
+-	unsigned	max_size = ncm->port.fixed_in_len;
+-	const struct ndp_parser_opts *opts = ncm->parser_opts;
+-	const int ndp_align = le16_to_cpu(ntb_parameters.wNdpInAlignment);
+-	const int div = le16_to_cpu(ntb_parameters.wNdpInDivisor);
+-	const int rem = le16_to_cpu(ntb_parameters.wNdpInPayloadRemainder);
+-	const int dgram_idx_len = 2 * 2 * opts->dgram_item_len;
+-
+-	if (!skb && !ncm->skb_tx_data)
+-		return NULL;
+ 
+ 	if (skb) {
++		int		ncb_len = 0;
++		__le16		*ntb_data;
++		__le16		*ntb_ndp;
++		int		dgram_pad;
++
++		unsigned	max_size = ncm->port.fixed_in_len;
++		const struct ndp_parser_opts *opts = ncm->parser_opts;
++		const int ndp_align = le16_to_cpu(ntb_parameters.wNdpInAlignment);
++		const int div = le16_to_cpu(ntb_parameters.wNdpInDivisor);
++		const int rem = le16_to_cpu(ntb_parameters.wNdpInPayloadRemainder);
++		const int dgram_idx_len = 2 * 2 * opts->dgram_item_len;
++
+ 		/* Add the CRC if required up front */
+ 		if (ncm->is_crc) {
+ 			uint32_t	crc;
+@@ -1126,8 +1120,11 @@ static struct sk_buff *ncm_wrap_ntb(struct gether *port,
+ 		dev_consume_skb_any(skb);
+ 		skb = NULL;
+ 
+-	} else if (ncm->skb_tx_data && ncm->timer_force_tx) {
+-		/* If the tx was requested because of a timeout then send */
++	} else if (ncm->skb_tx_data) {
++		/* If we get here ncm_wrap_ntb() was called with NULL skb,
++		 * because eth_start_xmit() was called with NULL skb by
++		 * ncm_tx_timeout() - hence, this is our signal to flush/send.
++		 */
+ 		skb2 = package_for_tx(ncm);
+ 		if (!skb2)
+ 			goto err;
+@@ -1155,20 +1152,18 @@ static struct sk_buff *ncm_wrap_ntb(struct gether *port,
+ static enum hrtimer_restart ncm_tx_timeout(struct hrtimer *data)
+ {
+ 	struct f_ncm *ncm = container_of(data, struct f_ncm, task_timer);
++	struct net_device *netdev = READ_ONCE(ncm->netdev);
+ 
+-	/* Only send if data is available. */
+-	if (!ncm->timer_stopping && ncm->skb_tx_data) {
+-		ncm->timer_force_tx = true;
+-
++	if (netdev) {
+ 		/* XXX This allowance of a NULL skb argument to ndo_start_xmit
+ 		 * XXX is not sane.  The gadget layer should be redesigned so
+ 		 * XXX that the dev->wrap() invocations to build SKBs is transparent
+ 		 * XXX and performed in some way outside of the ndo_start_xmit
+ 		 * XXX interface.
++		 *
++		 * This will call directly into u_ether's eth_start_xmit()
+ 		 */
+-		ncm->netdev->netdev_ops->ndo_start_xmit(NULL, ncm->netdev);
+-
+-		ncm->timer_force_tx = false;
++		netdev->netdev_ops->ndo_start_xmit(NULL, netdev);
+ 	}
+ 	return HRTIMER_NORESTART;
+ }
+@@ -1357,7 +1352,6 @@ static void ncm_disable(struct usb_function *f)
+ 	DBG(cdev, "ncm deactivated\n");
+ 
+ 	if (ncm->port.in_ep->enabled) {
+-		ncm->timer_stopping = true;
+ 		ncm->netdev = NULL;
+ 		gether_disconnect(&ncm->port);
+ 	}
+diff --git a/drivers/usb/gadget/function/f_printer.c b/drivers/usb/gadget/function/f_printer.c
+index 236ecc968..53158477f 100644
+--- a/drivers/usb/gadget/function/f_printer.c
++++ b/drivers/usb/gadget/function/f_printer.c
+@@ -665,8 +665,7 @@ printer_write(struct file *fd, const char __user *buf, size_t len, loff_t *ptr)
+ 		value = usb_ep_queue(dev->in_ep, req, GFP_ATOMIC);
+ 		spin_lock(&dev->lock);
+ 		if (value) {
+-			list_del(&req->list);
+-			list_add(&req->list, &dev->tx_reqs);
++			list_move(&req->list, &dev->tx_reqs);
+ 			spin_unlock_irqrestore(&dev->lock, flags);
+ 			mutex_unlock(&dev->lock_printer_io);
+ 			return -EAGAIN;
+@@ -823,7 +822,7 @@ set_printer_interface(struct printer_dev *dev)
+ 
+ 	result = usb_ep_enable(dev->out_ep);
+ 	if (result != 0) {
+-		DBG(dev, "enable %s --> %d\n", dev->in_ep->name, result);
++		DBG(dev, "enable %s --> %d\n", dev->out_ep->name, result);
+ 		goto done;
+ 	}
+ 
+diff --git a/drivers/usb/gadget/function/f_ptp.c b/drivers/usb/gadget/function/f_ptp.c
+new file mode 100644
+index 000000000..da3e4d53e
+--- /dev/null
++++ b/drivers/usb/gadget/function/f_ptp.c
+@@ -0,0 +1,38 @@
++/*
++ * Gadget Function Driver for PTP
++ *
++ * Copyright (C) 2014 Google, Inc.
++ * Author: Badhri Jagan Sridharan <badhri@android.com>
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/types.h>
++
++#include <linux/configfs.h>
++#include <linux/usb/composite.h>
++
++#include "f_mtp.h"
++
++static struct usb_function_instance *ptp_alloc_inst(void)
++{
++	return alloc_inst_mtp_ptp(false);
++}
++
++static struct usb_function *ptp_alloc(struct usb_function_instance *fi)
++{
++	return function_alloc_mtp_ptp(fi, false);
++}
++
++DECLARE_USB_FUNCTION_INIT(ptp, ptp_alloc_inst, ptp_alloc);
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Badhri Jagan Sridharan");
+diff --git a/drivers/usb/gadget/function/f_uac1.c b/drivers/usb/gadget/function/f_uac1.c
+index e65f474ad..51772f430 100644
+--- a/drivers/usb/gadget/function/f_uac1.c
++++ b/drivers/usb/gadget/function/f_uac1.c
+@@ -22,10 +22,26 @@
+ /* UAC1 spec: 3.7.2.3 Audio Channel Cluster Format */
+ #define UAC1_CHANNEL_MASK 0x0FFF
+ 
++#define USB_OUT_FU_ID	(out_feature_unit_desc->bUnitID)
++#define USB_IN_FU_ID	(in_feature_unit_desc->bUnitID)
++
++#define EPIN_EN(_opts) ((_opts)->p_chmask != 0)
++#define EPOUT_EN(_opts) ((_opts)->c_chmask != 0)
++#define FUIN_EN(_opts) ((_opts)->p_mute_present \
++			|| (_opts)->p_volume_present)
++#define FUOUT_EN(_opts) ((_opts)->c_mute_present \
++			|| (_opts)->c_volume_present)
++
+ struct f_uac1 {
+ 	struct g_audio g_audio;
+ 	u8 ac_intf, as_in_intf, as_out_intf;
+ 	u8 ac_alt, as_in_alt, as_out_alt;	/* needed for get_alt() */
++
++	struct usb_ctrlrequest setup_cr;	/* will be used in data stage */
++
++	/* Interrupt IN endpoint of AC interface */
++	struct usb_ep	*int_ep;
++	atomic_t	int_count;
+ };
+ 
+ static inline struct f_uac1 *func_to_uac1(struct usb_function *f)
+@@ -50,88 +66,70 @@ static inline struct f_uac1_opts *g_audio_to_uac1_opts(struct g_audio *audio)
+  * USB-OUT -> IT_1 -> OT_2 -> ALSA_Capture
+  * ALSA_Playback -> IT_3 -> OT_4 -> USB-IN
+  */
+-#define F_AUDIO_AC_INTERFACE		0
+-#define F_AUDIO_AS_OUT_INTERFACE	1
+-#define F_AUDIO_AS_IN_INTERFACE		2
+-/* Number of streaming interfaces */
+-#define F_AUDIO_NUM_INTERFACES		2
+ 
+ /* B.3.1  Standard AC Interface Descriptor */
+ static struct usb_interface_descriptor ac_interface_desc = {
+ 	.bLength =		USB_DT_INTERFACE_SIZE,
+ 	.bDescriptorType =	USB_DT_INTERFACE,
+-	.bNumEndpoints =	0,
++	/* .bNumEndpoints =	DYNAMIC */
+ 	.bInterfaceClass =	USB_CLASS_AUDIO,
+ 	.bInterfaceSubClass =	USB_SUBCLASS_AUDIOCONTROL,
+ };
+ 
+-/*
+- * The number of AudioStreaming and MIDIStreaming interfaces
+- * in the Audio Interface Collection
+- */
+-DECLARE_UAC_AC_HEADER_DESCRIPTOR(2);
+-
+-#define UAC_DT_AC_HEADER_LENGTH	UAC_DT_AC_HEADER_SIZE(F_AUDIO_NUM_INTERFACES)
+-/* 2 input terminals and 2 output terminals */
+-#define UAC_DT_TOTAL_LENGTH (UAC_DT_AC_HEADER_LENGTH \
+-	+ 2*UAC_DT_INPUT_TERMINAL_SIZE + 2*UAC_DT_OUTPUT_TERMINAL_SIZE)
+ /* B.3.2  Class-Specific AC Interface Descriptor */
+-static struct uac1_ac_header_descriptor_2 ac_header_desc = {
+-	.bLength =		UAC_DT_AC_HEADER_LENGTH,
+-	.bDescriptorType =	USB_DT_CS_INTERFACE,
+-	.bDescriptorSubtype =	UAC_HEADER,
+-	.bcdADC =		cpu_to_le16(0x0100),
+-	.wTotalLength =		cpu_to_le16(UAC_DT_TOTAL_LENGTH),
+-	.bInCollection =	F_AUDIO_NUM_INTERFACES,
+-	.baInterfaceNr = {
+-	/* Interface number of the AudioStream interfaces */
+-		[0] =		1,
+-		[1] =		2,
+-	}
+-};
++static struct uac1_ac_header_descriptor *ac_header_desc;
+ 
+-#define USB_OUT_IT_ID	1
+ static struct uac_input_terminal_descriptor usb_out_it_desc = {
+ 	.bLength =		UAC_DT_INPUT_TERMINAL_SIZE,
+ 	.bDescriptorType =	USB_DT_CS_INTERFACE,
+ 	.bDescriptorSubtype =	UAC_INPUT_TERMINAL,
+-	.bTerminalID =		USB_OUT_IT_ID,
++	/* .bTerminalID =	DYNAMIC */
+ 	.wTerminalType =	cpu_to_le16(UAC_TERMINAL_STREAMING),
+ 	.bAssocTerminal =	0,
+ 	.wChannelConfig =	cpu_to_le16(0x3),
+ };
+ 
+-#define IO_OUT_OT_ID	2
+ static struct uac1_output_terminal_descriptor io_out_ot_desc = {
+ 	.bLength		= UAC_DT_OUTPUT_TERMINAL_SIZE,
+ 	.bDescriptorType	= USB_DT_CS_INTERFACE,
+ 	.bDescriptorSubtype	= UAC_OUTPUT_TERMINAL,
+-	.bTerminalID		= IO_OUT_OT_ID,
++	/* .bTerminalID =	DYNAMIC */
+ 	.wTerminalType		= cpu_to_le16(UAC_OUTPUT_TERMINAL_SPEAKER),
+ 	.bAssocTerminal		= 0,
+-	.bSourceID		= USB_OUT_IT_ID,
++	/* .bSourceID =		DYNAMIC */
+ };
+ 
+-#define IO_IN_IT_ID	3
+ static struct uac_input_terminal_descriptor io_in_it_desc = {
+ 	.bLength		= UAC_DT_INPUT_TERMINAL_SIZE,
+ 	.bDescriptorType	= USB_DT_CS_INTERFACE,
+ 	.bDescriptorSubtype	= UAC_INPUT_TERMINAL,
+-	.bTerminalID		= IO_IN_IT_ID,
++	/* .bTerminalID		= DYNAMIC */
+ 	.wTerminalType		= cpu_to_le16(UAC_INPUT_TERMINAL_MICROPHONE),
+ 	.bAssocTerminal		= 0,
+ 	.wChannelConfig		= cpu_to_le16(0x3),
+ };
+ 
+-#define USB_IN_OT_ID	4
+ static struct uac1_output_terminal_descriptor usb_in_ot_desc = {
+ 	.bLength =		UAC_DT_OUTPUT_TERMINAL_SIZE,
+ 	.bDescriptorType =	USB_DT_CS_INTERFACE,
+ 	.bDescriptorSubtype =	UAC_OUTPUT_TERMINAL,
+-	.bTerminalID =		USB_IN_OT_ID,
++	/* .bTerminalID =	DYNAMIC */
+ 	.wTerminalType =	cpu_to_le16(UAC_TERMINAL_STREAMING),
+ 	.bAssocTerminal =	0,
+-	.bSourceID =		IO_IN_IT_ID,
++	/* .bSourceID =		DYNAMIC */
++};
++
++static struct uac_feature_unit_descriptor *in_feature_unit_desc;
++static struct uac_feature_unit_descriptor *out_feature_unit_desc;
++
++/* AC IN Interrupt Endpoint */
++static struct usb_endpoint_descriptor ac_int_ep_desc = {
++	.bLength = USB_DT_ENDPOINT_SIZE,
++	.bDescriptorType = USB_DT_ENDPOINT,
++	.bEndpointAddress = USB_DIR_IN,
++	.bmAttributes = USB_ENDPOINT_XFER_INT,
++	.wMaxPacketSize = cpu_to_le16(2),
++	.bInterval = 4,
+ };
+ 
+ /* B.4.1  Standard AS Interface Descriptor */
+@@ -176,7 +174,7 @@ static struct uac1_as_header_descriptor as_out_header_desc = {
+ 	.bLength =		UAC_DT_AS_HEADER_SIZE,
+ 	.bDescriptorType =	USB_DT_CS_INTERFACE,
+ 	.bDescriptorSubtype =	UAC_AS_GENERAL,
+-	.bTerminalLink =	USB_OUT_IT_ID,
++	/* .bTerminalLink =	DYNAMIC */
+ 	.bDelay =		1,
+ 	.wFormatTag =		cpu_to_le16(UAC_FORMAT_TYPE_I_PCM),
+ };
+@@ -185,7 +183,7 @@ static struct uac1_as_header_descriptor as_in_header_desc = {
+ 	.bLength =		UAC_DT_AS_HEADER_SIZE,
+ 	.bDescriptorType =	USB_DT_CS_INTERFACE,
+ 	.bDescriptorSubtype =	UAC_AS_GENERAL,
+-	.bTerminalLink =	USB_IN_OT_ID,
++	/* .bTerminalLink =	DYNAMIC */
+ 	.bDelay =		1,
+ 	.wFormatTag =		cpu_to_le16(UAC_FORMAT_TYPE_I_PCM),
+ };
+@@ -260,8 +258,13 @@ static struct usb_descriptor_header *f_audio_desc[] = {
+ 
+ 	(struct usb_descriptor_header *)&usb_out_it_desc,
+ 	(struct usb_descriptor_header *)&io_out_ot_desc,
++	(struct usb_descriptor_header *)&out_feature_unit_desc,
++
+ 	(struct usb_descriptor_header *)&io_in_it_desc,
+ 	(struct usb_descriptor_header *)&usb_in_ot_desc,
++	(struct usb_descriptor_header *)&in_feature_unit_desc,
++
++	(struct usb_descriptor_header *)&ac_int_ep_desc,
+ 
+ 	(struct usb_descriptor_header *)&as_out_interface_alt_0_desc,
+ 	(struct usb_descriptor_header *)&as_out_interface_alt_1_desc,
+@@ -291,6 +294,8 @@ enum {
+ 	STR_IO_IN_IT,
+ 	STR_IO_IN_IT_CH_NAMES,
+ 	STR_USB_IN_OT,
++	STR_FU_IN,
++	STR_FU_OUT,
+ 	STR_AS_OUT_IF_ALT0,
+ 	STR_AS_OUT_IF_ALT1,
+ 	STR_AS_IN_IF_ALT0,
+@@ -305,6 +310,8 @@ static struct usb_string strings_uac1[] = {
+ 	[STR_IO_IN_IT].s = "Capture Input terminal",
+ 	[STR_IO_IN_IT_CH_NAMES].s = "Capture Channels",
+ 	[STR_USB_IN_OT].s = "Capture Output terminal",
++	[STR_FU_IN].s = "Capture Volume",
++	[STR_FU_OUT].s = "Playback Volume",
+ 	[STR_AS_OUT_IF_ALT0].s = "Playback Inactive",
+ 	[STR_AS_OUT_IF_ALT1].s = "Playback Active",
+ 	[STR_AS_IN_IF_ALT0].s = "Capture Inactive",
+@@ -326,6 +333,376 @@ static struct usb_gadget_strings *uac1_strings[] = {
+  * This function is an ALSA sound card following USB Audio Class Spec 1.0.
+  */
+ 
++static void audio_notify_complete(struct usb_ep *_ep, struct usb_request *req)
++{
++	struct g_audio *audio = req->context;
++	struct f_uac1 *uac1 = func_to_uac1(&audio->func);
++
++	atomic_dec(&uac1->int_count);
++	kfree(req->buf);
++	usb_ep_free_request(_ep, req);
++}
++
++static int audio_notify(struct g_audio *audio, int unit_id, int cs)
++{
++	struct f_uac1 *uac1 = func_to_uac1(&audio->func);
++	struct usb_request *req;
++	struct uac1_status_word *msg;
++	int ret;
++
++	if (!uac1->int_ep->enabled)
++		return 0;
++
++	if (atomic_inc_return(&uac1->int_count) > UAC1_DEF_INT_REQ_NUM) {
++		atomic_dec(&uac1->int_count);
++		return 0;
++	}
++
++	req = usb_ep_alloc_request(uac1->int_ep, GFP_ATOMIC);
++	if (req == NULL) {
++		ret = -ENOMEM;
++		goto err_dec_int_count;
++	}
++
++	msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
++	if (msg == NULL) {
++		ret = -ENOMEM;
++		goto err_free_request;
++	}
++
++	msg->bStatusType = UAC1_STATUS_TYPE_IRQ_PENDING
++				| UAC1_STATUS_TYPE_ORIG_AUDIO_CONTROL_IF;
++	msg->bOriginator = unit_id;
++
++	req->length = sizeof(*msg);
++	req->buf = msg;
++	req->context = audio;
++	req->complete = audio_notify_complete;
++
++	ret = usb_ep_queue(uac1->int_ep, req, GFP_ATOMIC);
++
++	if (ret)
++		goto err_free_msg;
++
++	return 0;
++
++err_free_msg:
++	kfree(msg);
++err_free_request:
++	usb_ep_free_request(uac1->int_ep, req);
++err_dec_int_count:
++	atomic_dec(&uac1->int_count);
++
++	return ret;
++}
++
++static int
++in_rq_cur(struct usb_function *fn, const struct usb_ctrlrequest *cr)
++{
++	struct usb_request *req = fn->config->cdev->req;
++	struct g_audio *audio = func_to_g_audio(fn);
++	struct f_uac1_opts *opts = g_audio_to_uac1_opts(audio);
++	u16 w_length = le16_to_cpu(cr->wLength);
++	u16 w_index = le16_to_cpu(cr->wIndex);
++	u16 w_value = le16_to_cpu(cr->wValue);
++	u8 entity_id = (w_index >> 8) & 0xff;
++	u8 control_selector = w_value >> 8;
++	int value = -EOPNOTSUPP;
++
++	if ((FUIN_EN(opts) && (entity_id == USB_IN_FU_ID)) ||
++			(FUOUT_EN(opts) && (entity_id == USB_OUT_FU_ID))) {
++		unsigned int is_playback = 0;
++
++		if (FUIN_EN(opts) && (entity_id == USB_IN_FU_ID))
++			is_playback = 1;
++
++		if (control_selector == UAC_FU_MUTE) {
++			unsigned int mute;
++
++			u_audio_get_mute(audio, is_playback, &mute);
++
++			*(u8 *)req->buf = mute;
++			value = min_t(unsigned int, w_length, 1);
++		} else if (control_selector == UAC_FU_VOLUME) {
++			__le16 c;
++			s16 volume;
++
++			u_audio_get_volume(audio, is_playback, &volume);
++
++			c = cpu_to_le16(volume);
++
++			value = min_t(unsigned int, w_length, sizeof(c));
++			memcpy(req->buf, &c, value);
++		} else {
++			dev_err(&audio->gadget->dev,
++				"%s:%d control_selector=%d TODO!\n",
++				__func__, __LINE__, control_selector);
++		}
++	} else {
++		dev_err(&audio->gadget->dev,
++			"%s:%d entity_id=%d control_selector=%d TODO!\n",
++			__func__, __LINE__, entity_id, control_selector);
++	}
++
++	return value;
++}
++
++static int
++in_rq_min(struct usb_function *fn, const struct usb_ctrlrequest *cr)
++{
++	struct usb_request *req = fn->config->cdev->req;
++	struct g_audio *audio = func_to_g_audio(fn);
++	struct f_uac1_opts *opts = g_audio_to_uac1_opts(audio);
++	u16 w_length = le16_to_cpu(cr->wLength);
++	u16 w_index = le16_to_cpu(cr->wIndex);
++	u16 w_value = le16_to_cpu(cr->wValue);
++	u8 entity_id = (w_index >> 8) & 0xff;
++	u8 control_selector = w_value >> 8;
++	int value = -EOPNOTSUPP;
++
++	if ((FUIN_EN(opts) && (entity_id == USB_IN_FU_ID)) ||
++			(FUOUT_EN(opts) && (entity_id == USB_OUT_FU_ID))) {
++		unsigned int is_playback = 0;
++
++		if (FUIN_EN(opts) && (entity_id == USB_IN_FU_ID))
++			is_playback = 1;
++
++		if (control_selector == UAC_FU_VOLUME) {
++			__le16 r;
++			s16 min_db;
++
++			if (is_playback)
++				min_db = opts->p_volume_min;
++			else
++				min_db = opts->c_volume_min;
++
++			r = cpu_to_le16(min_db);
++
++			value = min_t(unsigned int, w_length, sizeof(r));
++			memcpy(req->buf, &r, value);
++		} else {
++			dev_err(&audio->gadget->dev,
++				"%s:%d control_selector=%d TODO!\n",
++				__func__, __LINE__, control_selector);
++		}
++	} else {
++		dev_err(&audio->gadget->dev,
++			"%s:%d entity_id=%d control_selector=%d TODO!\n",
++			__func__, __LINE__, entity_id, control_selector);
++	}
++
++	return value;
++}
++
++static int
++in_rq_max(struct usb_function *fn, const struct usb_ctrlrequest *cr)
++{
++	struct usb_request *req = fn->config->cdev->req;
++	struct g_audio *audio = func_to_g_audio(fn);
++	struct f_uac1_opts *opts = g_audio_to_uac1_opts(audio);
++	u16 w_length = le16_to_cpu(cr->wLength);
++	u16 w_index = le16_to_cpu(cr->wIndex);
++	u16 w_value = le16_to_cpu(cr->wValue);
++	u8 entity_id = (w_index >> 8) & 0xff;
++	u8 control_selector = w_value >> 8;
++	int value = -EOPNOTSUPP;
++
++	if ((FUIN_EN(opts) && (entity_id == USB_IN_FU_ID)) ||
++			(FUOUT_EN(opts) && (entity_id == USB_OUT_FU_ID))) {
++		unsigned int is_playback = 0;
++
++		if (FUIN_EN(opts) && (entity_id == USB_IN_FU_ID))
++			is_playback = 1;
++
++		if (control_selector == UAC_FU_VOLUME) {
++			__le16 r;
++			s16 max_db;
++
++			if (is_playback)
++				max_db = opts->p_volume_max;
++			else
++				max_db = opts->c_volume_max;
++
++			r = cpu_to_le16(max_db);
++
++			value = min_t(unsigned int, w_length, sizeof(r));
++			memcpy(req->buf, &r, value);
++		} else {
++			dev_err(&audio->gadget->dev,
++				"%s:%d control_selector=%d TODO!\n",
++				__func__, __LINE__, control_selector);
++		}
++	} else {
++		dev_err(&audio->gadget->dev,
++			"%s:%d entity_id=%d control_selector=%d TODO!\n",
++			__func__, __LINE__, entity_id, control_selector);
++	}
++
++	return value;
++}
++
++static int
++in_rq_res(struct usb_function *fn, const struct usb_ctrlrequest *cr)
++{
++	struct usb_request *req = fn->config->cdev->req;
++	struct g_audio *audio = func_to_g_audio(fn);
++	struct f_uac1_opts *opts = g_audio_to_uac1_opts(audio);
++	u16 w_length = le16_to_cpu(cr->wLength);
++	u16 w_index = le16_to_cpu(cr->wIndex);
++	u16 w_value = le16_to_cpu(cr->wValue);
++	u8 entity_id = (w_index >> 8) & 0xff;
++	u8 control_selector = w_value >> 8;
++	int value = -EOPNOTSUPP;
++
++	if ((FUIN_EN(opts) && (entity_id == USB_IN_FU_ID)) ||
++			(FUOUT_EN(opts) && (entity_id == USB_OUT_FU_ID))) {
++		unsigned int is_playback = 0;
++
++		if (FUIN_EN(opts) && (entity_id == USB_IN_FU_ID))
++			is_playback = 1;
++
++		if (control_selector == UAC_FU_VOLUME) {
++			__le16 r;
++			s16 res_db;
++
++			if (is_playback)
++				res_db = opts->p_volume_res;
++			else
++				res_db = opts->c_volume_res;
++
++			r = cpu_to_le16(res_db);
++
++			value = min_t(unsigned int, w_length, sizeof(r));
++			memcpy(req->buf, &r, value);
++		} else {
++			dev_err(&audio->gadget->dev,
++				"%s:%d control_selector=%d TODO!\n",
++				__func__, __LINE__, control_selector);
++		}
++	} else {
++		dev_err(&audio->gadget->dev,
++			"%s:%d entity_id=%d control_selector=%d TODO!\n",
++			__func__, __LINE__, entity_id, control_selector);
++	}
++
++	return value;
++}
++
++static void
++out_rq_cur_complete(struct usb_ep *ep, struct usb_request *req)
++{
++	struct g_audio *audio = req->context;
++	struct usb_composite_dev *cdev = audio->func.config->cdev;
++	struct f_uac1_opts *opts = g_audio_to_uac1_opts(audio);
++	struct f_uac1 *uac1 = func_to_uac1(&audio->func);
++	struct usb_ctrlrequest *cr = &uac1->setup_cr;
++	u16 w_index = le16_to_cpu(cr->wIndex);
++	u16 w_value = le16_to_cpu(cr->wValue);
++	u8 entity_id = (w_index >> 8) & 0xff;
++	u8 control_selector = w_value >> 8;
++
++	if (req->status != 0) {
++		dev_dbg(&cdev->gadget->dev, "completion err %d\n", req->status);
++		return;
++	}
++
++	if ((FUIN_EN(opts) && (entity_id == USB_IN_FU_ID)) ||
++			(FUOUT_EN(opts) && (entity_id == USB_OUT_FU_ID))) {
++		unsigned int is_playback = 0;
++
++		if (FUIN_EN(opts) && (entity_id == USB_IN_FU_ID))
++			is_playback = 1;
++
++		if (control_selector == UAC_FU_MUTE) {
++			u8 mute = *(u8 *)req->buf;
++
++			u_audio_set_mute(audio, is_playback, mute);
++
++			return;
++		} else if (control_selector == UAC_FU_VOLUME) {
++			__le16 *c = req->buf;
++			s16 volume;
++
++			volume = le16_to_cpu(*c);
++			u_audio_set_volume(audio, is_playback, volume);
++
++			return;
++		} else {
++			dev_err(&audio->gadget->dev,
++				"%s:%d control_selector=%d TODO!\n",
++				__func__, __LINE__, control_selector);
++			usb_ep_set_halt(ep);
++		}
++	} else {
++		dev_err(&audio->gadget->dev,
++			"%s:%d entity_id=%d control_selector=%d TODO!\n",
++			__func__, __LINE__, entity_id, control_selector);
++		usb_ep_set_halt(ep);
++
++	}
++}
++
++static int
++out_rq_cur(struct usb_function *fn, const struct usb_ctrlrequest *cr)
++{
++	struct usb_request *req = fn->config->cdev->req;
++	struct g_audio *audio = func_to_g_audio(fn);
++	struct f_uac1_opts *opts = g_audio_to_uac1_opts(audio);
++	struct f_uac1 *uac1 = func_to_uac1(&audio->func);
++	u16 w_length = le16_to_cpu(cr->wLength);
++	u16 w_index = le16_to_cpu(cr->wIndex);
++	u16 w_value = le16_to_cpu(cr->wValue);
++	u8 entity_id = (w_index >> 8) & 0xff;
++	u8 control_selector = w_value >> 8;
++
++	if ((FUIN_EN(opts) && (entity_id == USB_IN_FU_ID)) ||
++			(FUOUT_EN(opts) && (entity_id == USB_OUT_FU_ID))) {
++		memcpy(&uac1->setup_cr, cr, sizeof(*cr));
++		req->context = audio;
++		req->complete = out_rq_cur_complete;
++
++		return w_length;
++	} else {
++		dev_err(&audio->gadget->dev,
++			"%s:%d entity_id=%d control_selector=%d TODO!\n",
++			__func__, __LINE__, entity_id, control_selector);
++	}
++	return -EOPNOTSUPP;
++}
++
++static int ac_rq_in(struct usb_function *f,
++		const struct usb_ctrlrequest *ctrl)
++{
++	struct usb_composite_dev *cdev = f->config->cdev;
++	int value = -EOPNOTSUPP;
++	u8 ep = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF);
++	u16 len = le16_to_cpu(ctrl->wLength);
++	u16 w_value = le16_to_cpu(ctrl->wValue);
++
++	DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, endpoint %d\n",
++			ctrl->bRequest, w_value, len, ep);
++
++	switch (ctrl->bRequest) {
++	case UAC_GET_CUR:
++		return in_rq_cur(f, ctrl);
++	case UAC_GET_MIN:
++		return in_rq_min(f, ctrl);
++	case UAC_GET_MAX:
++		return in_rq_max(f, ctrl);
++	case UAC_GET_RES:
++		return in_rq_res(f, ctrl);
++	case UAC_GET_MEM:
++		break;
++	case UAC_GET_STAT:
++		value = len;
++		break;
++	default:
++		break;
++	}
++
++	return value;
++}
++
+ static int audio_set_endpoint_req(struct usb_function *f,
+ 		const struct usb_ctrlrequest *ctrl)
+ {
+@@ -411,7 +788,13 @@ f_audio_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl)
+ 	case USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_ENDPOINT:
+ 		value = audio_get_endpoint_req(f, ctrl);
+ 		break;
+-
++	case USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE:
++		if (ctrl->bRequest == UAC_SET_CUR)
++			value = out_rq_cur(f, ctrl);
++		break;
++	case USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE:
++		value = ac_rq_in(f, ctrl);
++		break;
+ 	default:
+ 		ERROR(cdev, "invalid control req%02x.%02x v%04x i%04x l%d\n",
+ 			ctrl->bRequestType, ctrl->bRequest,
+@@ -439,6 +822,7 @@ static int f_audio_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
+ 	struct usb_composite_dev *cdev = f->config->cdev;
+ 	struct usb_gadget *gadget = cdev->gadget;
+ 	struct device *dev = &gadget->dev;
++	struct g_audio *audio = func_to_g_audio(f);
+ 	struct f_uac1 *uac1 = func_to_uac1(f);
+ 	int ret = 0;
+ 
+@@ -454,6 +838,14 @@ static int f_audio_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
+ 			dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
+ 			return -EINVAL;
+ 		}
++
++		/* restart interrupt endpoint */
++		if (uac1->int_ep) {
++			usb_ep_disable(uac1->int_ep);
++			config_ep_by_speed(gadget, &audio->func, uac1->int_ep);
++			usb_ep_enable(uac1->int_ep);
++		}
++
+ 		return 0;
+ 	}
+ 
+@@ -509,9 +901,159 @@ static void f_audio_disable(struct usb_function *f)
+ 
+ 	u_audio_stop_playback(&uac1->g_audio);
+ 	u_audio_stop_capture(&uac1->g_audio);
++	if (uac1->int_ep)
++		usb_ep_disable(uac1->int_ep);
+ }
+ 
+ /*-------------------------------------------------------------------------*/
++static struct uac_feature_unit_descriptor *build_fu_desc(int chmask)
++{
++	struct uac_feature_unit_descriptor *fu_desc;
++	int channels = num_channels(chmask);
++	int fu_desc_size = UAC_DT_FEATURE_UNIT_SIZE(channels);
++
++	fu_desc = kzalloc(fu_desc_size, GFP_KERNEL);
++	if (!fu_desc)
++		return NULL;
++
++	fu_desc->bLength = fu_desc_size;
++	fu_desc->bDescriptorType = USB_DT_CS_INTERFACE;
++
++	fu_desc->bDescriptorSubtype = UAC_FEATURE_UNIT;
++	fu_desc->bControlSize  = 2;
++
++	/* bUnitID, bSourceID and bmaControls will be defined later */
++
++	return fu_desc;
++}
++
++/* B.3.2  Class-Specific AC Interface Descriptor */
++static struct
++uac1_ac_header_descriptor *build_ac_header_desc(struct f_uac1_opts *opts)
++{
++	struct uac1_ac_header_descriptor *ac_desc;
++	int ac_header_desc_size;
++	int num_ifaces = 0;
++
++	if (EPOUT_EN(opts))
++		num_ifaces++;
++	if (EPIN_EN(opts))
++		num_ifaces++;
++
++	ac_header_desc_size = UAC_DT_AC_HEADER_SIZE(num_ifaces);
++
++	ac_desc = kzalloc(ac_header_desc_size, GFP_KERNEL);
++	if (!ac_desc)
++		return NULL;
++
++	ac_desc->bLength = ac_header_desc_size;
++	ac_desc->bDescriptorType = USB_DT_CS_INTERFACE;
++	ac_desc->bDescriptorSubtype = UAC_HEADER;
++	ac_desc->bcdADC = cpu_to_le16(0x0100);
++	ac_desc->bInCollection = num_ifaces;
++
++	/* wTotalLength and baInterfaceNr will be defined later */
++
++	return ac_desc;
++}
++
++/* Use macro to overcome line length limitation */
++#define USBDHDR(p) (struct usb_descriptor_header *)(p)
++
++static void setup_descriptor(struct f_uac1_opts *opts)
++{
++	/* patch descriptors */
++	int i = 1; /* ID's start with 1 */
++
++	if (EPOUT_EN(opts))
++		usb_out_it_desc.bTerminalID = i++;
++	if (EPIN_EN(opts))
++		io_in_it_desc.bTerminalID = i++;
++	if (EPOUT_EN(opts))
++		io_out_ot_desc.bTerminalID = i++;
++	if (EPIN_EN(opts))
++		usb_in_ot_desc.bTerminalID = i++;
++	if (FUOUT_EN(opts))
++		out_feature_unit_desc->bUnitID = i++;
++	if (FUIN_EN(opts))
++		in_feature_unit_desc->bUnitID = i++;
++
++	if (FUIN_EN(opts)) {
++		usb_in_ot_desc.bSourceID = in_feature_unit_desc->bUnitID;
++		in_feature_unit_desc->bSourceID = io_in_it_desc.bTerminalID;
++	} else {
++		usb_in_ot_desc.bSourceID = io_in_it_desc.bTerminalID;
++	}
++	if (FUOUT_EN(opts)) {
++		io_out_ot_desc.bSourceID = out_feature_unit_desc->bUnitID;
++		out_feature_unit_desc->bSourceID = usb_out_it_desc.bTerminalID;
++	} else {
++		io_out_ot_desc.bSourceID = usb_out_it_desc.bTerminalID;
++	}
++
++	as_out_header_desc.bTerminalLink = usb_out_it_desc.bTerminalID;
++	as_in_header_desc.bTerminalLink = usb_in_ot_desc.bTerminalID;
++
++	ac_header_desc->wTotalLength = cpu_to_le16(ac_header_desc->bLength);
++
++	if (EPIN_EN(opts)) {
++		u16 len = le16_to_cpu(ac_header_desc->wTotalLength);
++
++		len += sizeof(usb_in_ot_desc);
++		len += sizeof(io_in_it_desc);
++		if (FUIN_EN(opts))
++			len += in_feature_unit_desc->bLength;
++		ac_header_desc->wTotalLength = cpu_to_le16(len);
++	}
++	if (EPOUT_EN(opts)) {
++		u16 len = le16_to_cpu(ac_header_desc->wTotalLength);
++
++		len += sizeof(usb_out_it_desc);
++		len += sizeof(io_out_ot_desc);
++		if (FUOUT_EN(opts))
++			len += out_feature_unit_desc->bLength;
++		ac_header_desc->wTotalLength = cpu_to_le16(len);
++	}
++
++	i = 0;
++	f_audio_desc[i++] = USBDHDR(&ac_interface_desc);
++	f_audio_desc[i++] = USBDHDR(ac_header_desc);
++
++	if (EPOUT_EN(opts)) {
++		f_audio_desc[i++] = USBDHDR(&usb_out_it_desc);
++		f_audio_desc[i++] = USBDHDR(&io_out_ot_desc);
++		if (FUOUT_EN(opts))
++			f_audio_desc[i++] = USBDHDR(out_feature_unit_desc);
++	}
++
++	if (EPIN_EN(opts)) {
++		f_audio_desc[i++] = USBDHDR(&io_in_it_desc);
++		f_audio_desc[i++] = USBDHDR(&usb_in_ot_desc);
++		if (FUIN_EN(opts))
++			f_audio_desc[i++] = USBDHDR(in_feature_unit_desc);
++	}
++
++	if (FUOUT_EN(opts) || FUIN_EN(opts))
++		f_audio_desc[i++] = USBDHDR(&ac_int_ep_desc);
++
++	if (EPOUT_EN(opts)) {
++		f_audio_desc[i++] = USBDHDR(&as_out_interface_alt_0_desc);
++		f_audio_desc[i++] = USBDHDR(&as_out_interface_alt_1_desc);
++		f_audio_desc[i++] = USBDHDR(&as_out_header_desc);
++		f_audio_desc[i++] = USBDHDR(&as_out_type_i_desc);
++		f_audio_desc[i++] = USBDHDR(&as_out_ep_desc);
++		f_audio_desc[i++] = USBDHDR(&as_iso_out_desc);
++	}
++	if (EPIN_EN(opts)) {
++		f_audio_desc[i++] = USBDHDR(&as_in_interface_alt_0_desc);
++		f_audio_desc[i++] = USBDHDR(&as_in_interface_alt_1_desc);
++		f_audio_desc[i++] = USBDHDR(&as_in_header_desc);
++		f_audio_desc[i++] = USBDHDR(&as_in_type_i_desc);
++		f_audio_desc[i++] = USBDHDR(&as_in_ep_desc);
++		f_audio_desc[i++] = USBDHDR(&as_iso_in_desc);
++	}
++	f_audio_desc[i] = NULL;
++}
+ 
+ static int f_audio_validate_opts(struct g_audio *audio, struct device *dev)
+ {
+@@ -540,6 +1082,28 @@ static int f_audio_validate_opts(struct g_audio *audio, struct device *dev)
+ 		return -EINVAL;
+ 	}
+ 
++	if (opts->p_volume_max <= opts->p_volume_min) {
++		dev_err(dev, "Error: incorrect playback volume max/min\n");
++		return -EINVAL;
++	} else if (opts->c_volume_max <= opts->c_volume_min) {
++		dev_err(dev, "Error: incorrect capture volume max/min\n");
++		return -EINVAL;
++	} else if (opts->p_volume_res <= 0) {
++		dev_err(dev, "Error: negative/zero playback volume resolution\n");
++		return -EINVAL;
++	} else if (opts->c_volume_res <= 0) {
++		dev_err(dev, "Error: negative/zero capture volume resolution\n");
++		return -EINVAL;
++	}
++
++	if ((opts->p_volume_max - opts->p_volume_min) % opts->p_volume_res) {
++		dev_err(dev, "Error: incorrect playback volume resolution\n");
++		return -EINVAL;
++	} else if ((opts->c_volume_max - opts->c_volume_min) % opts->c_volume_res) {
++		dev_err(dev, "Error: incorrect capture volume resolution\n");
++		return -EINVAL;
++	}
++
+ 	return 0;
+ }
+ 
+@@ -556,6 +1120,7 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f)
+ 	struct usb_string		*us;
+ 	u8				*sam_freq;
+ 	int				rate;
++	int				ba_iface_id;
+ 	int				status;
+ 
+ 	status = f_audio_validate_opts(audio, dev);
+@@ -567,6 +1132,26 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f)
+ 	us = usb_gstrings_attach(cdev, uac1_strings, ARRAY_SIZE(strings_uac1));
+ 	if (IS_ERR(us))
+ 		return PTR_ERR(us);
++
++	ac_header_desc = build_ac_header_desc(audio_opts);
++	if (!ac_header_desc)
++		return -ENOMEM;
++
++	if (FUOUT_EN(audio_opts)) {
++		out_feature_unit_desc = build_fu_desc(audio_opts->c_chmask);
++		if (!out_feature_unit_desc) {
++			status = -ENOMEM;
++			goto fail;
++		}
++	}
++	if (FUIN_EN(audio_opts)) {
++		in_feature_unit_desc = build_fu_desc(audio_opts->p_chmask);
++		if (!in_feature_unit_desc) {
++			status = -ENOMEM;
++			goto err_free_fu;
++		}
++	}
++
+ 	ac_interface_desc.iInterface = us[STR_AC_IF].id;
+ 	usb_out_it_desc.iTerminal = us[STR_USB_OUT_IT].id;
+ 	usb_out_it_desc.iChannelNames = us[STR_USB_OUT_IT_CH_NAMES].id;
+@@ -579,6 +1164,21 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f)
+ 	as_in_interface_alt_0_desc.iInterface = us[STR_AS_IN_IF_ALT0].id;
+ 	as_in_interface_alt_1_desc.iInterface = us[STR_AS_IN_IF_ALT1].id;
+ 
++	if (FUOUT_EN(audio_opts)) {
++		u8 *i_feature;
++
++		i_feature = (u8 *)out_feature_unit_desc +
++					out_feature_unit_desc->bLength - 1;
++		*i_feature = us[STR_FU_OUT].id;
++	}
++	if (FUIN_EN(audio_opts)) {
++		u8 *i_feature;
++
++		i_feature = (u8 *)in_feature_unit_desc +
++					in_feature_unit_desc->bLength - 1;
++		*i_feature = us[STR_FU_IN].id;
++	}
++
+ 	/* Set channel numbers */
+ 	usb_out_it_desc.bNrChannels = num_channels(audio_opts->c_chmask);
+ 	usb_out_it_desc.wChannelConfig = cpu_to_le16(audio_opts->c_chmask);
+@@ -591,6 +1191,27 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f)
+ 	as_in_type_i_desc.bSubframeSize = audio_opts->p_ssize;
+ 	as_in_type_i_desc.bBitResolution = audio_opts->p_ssize * 8;
+ 
++	if (FUOUT_EN(audio_opts)) {
++		__le16 *bma = (__le16 *)&out_feature_unit_desc->bmaControls[0];
++		u32 control = 0;
++
++		if (audio_opts->c_mute_present)
++			control |= UAC_FU_MUTE;
++		if (audio_opts->c_volume_present)
++			control |= UAC_FU_VOLUME;
++		*bma = cpu_to_le16(control);
++	}
++	if (FUIN_EN(audio_opts)) {
++		__le16 *bma = (__le16 *)&in_feature_unit_desc->bmaControls[0];
++		u32 control = 0;
++
++		if (audio_opts->p_mute_present)
++			control |= UAC_FU_MUTE;
++		if (audio_opts->p_volume_present)
++			control |= UAC_FU_VOLUME;
++		*bma = cpu_to_le16(control);
++	}
++
+ 	/* Set sample rates */
+ 	rate = audio_opts->c_srate;
+ 	sam_freq = as_out_type_i_desc.tSamFreq[0];
+@@ -602,61 +1223,106 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f)
+ 	/* allocate instance-specific interface IDs, and patch descriptors */
+ 	status = usb_interface_id(c, f);
+ 	if (status < 0)
+-		goto fail;
++		goto err_free_fu;
+ 	ac_interface_desc.bInterfaceNumber = status;
+ 	uac1->ac_intf = status;
+ 	uac1->ac_alt = 0;
+ 
+-	status = usb_interface_id(c, f);
+-	if (status < 0)
+-		goto fail;
+-	as_out_interface_alt_0_desc.bInterfaceNumber = status;
+-	as_out_interface_alt_1_desc.bInterfaceNumber = status;
+-	ac_header_desc.baInterfaceNr[0] = status;
+-	uac1->as_out_intf = status;
+-	uac1->as_out_alt = 0;
++	ba_iface_id = 0;
++
++	if (EPOUT_EN(audio_opts)) {
++		status = usb_interface_id(c, f);
++		if (status < 0)
++			goto err_free_fu;
++		as_out_interface_alt_0_desc.bInterfaceNumber = status;
++		as_out_interface_alt_1_desc.bInterfaceNumber = status;
++		ac_header_desc->baInterfaceNr[ba_iface_id++] = status;
++		uac1->as_out_intf = status;
++		uac1->as_out_alt = 0;
++	}
+ 
+-	status = usb_interface_id(c, f);
+-	if (status < 0)
+-		goto fail;
+-	as_in_interface_alt_0_desc.bInterfaceNumber = status;
+-	as_in_interface_alt_1_desc.bInterfaceNumber = status;
+-	ac_header_desc.baInterfaceNr[1] = status;
+-	uac1->as_in_intf = status;
+-	uac1->as_in_alt = 0;
++	if (EPIN_EN(audio_opts)) {
++		status = usb_interface_id(c, f);
++		if (status < 0)
++			goto err_free_fu;
++		as_in_interface_alt_0_desc.bInterfaceNumber = status;
++		as_in_interface_alt_1_desc.bInterfaceNumber = status;
++		ac_header_desc->baInterfaceNr[ba_iface_id++] = status;
++		uac1->as_in_intf = status;
++		uac1->as_in_alt = 0;
++	}
+ 
+ 	audio->gadget = gadget;
+ 
+ 	status = -ENODEV;
+ 
++	ac_interface_desc.bNumEndpoints = 0;
++
++	/* allocate AC interrupt endpoint */
++	if (FUOUT_EN(audio_opts) || FUIN_EN(audio_opts)) {
++		ep = usb_ep_autoconfig(cdev->gadget, &ac_int_ep_desc);
++		if (!ep)
++			goto err_free_fu;
++		uac1->int_ep = ep;
++		uac1->int_ep->desc = &ac_int_ep_desc;
++
++		ac_interface_desc.bNumEndpoints = 1;
++	}
++
+ 	/* allocate instance-specific endpoints */
+-	ep = usb_ep_autoconfig(cdev->gadget, &as_out_ep_desc);
+-	if (!ep)
+-		goto fail;
+-	audio->out_ep = ep;
+-	audio->out_ep->desc = &as_out_ep_desc;
+-
+-	ep = usb_ep_autoconfig(cdev->gadget, &as_in_ep_desc);
+-	if (!ep)
+-		goto fail;
+-	audio->in_ep = ep;
+-	audio->in_ep->desc = &as_in_ep_desc;
++	if (EPOUT_EN(audio_opts)) {
++		ep = usb_ep_autoconfig(cdev->gadget, &as_out_ep_desc);
++		if (!ep)
++			goto err_free_fu;
++		audio->out_ep = ep;
++		audio->out_ep->desc = &as_out_ep_desc;
++	}
++
++	if (EPIN_EN(audio_opts)) {
++		ep = usb_ep_autoconfig(cdev->gadget, &as_in_ep_desc);
++		if (!ep)
++			goto err_free_fu;
++		audio->in_ep = ep;
++		audio->in_ep->desc = &as_in_ep_desc;
++	}
++
++	setup_descriptor(audio_opts);
+ 
+ 	/* copy descriptors, and track endpoint copies */
+ 	status = usb_assign_descriptors(f, f_audio_desc, f_audio_desc, NULL,
+ 					NULL);
+ 	if (status)
+-		goto fail;
++		goto err_free_fu;
+ 
+ 	audio->out_ep_maxpsize = le16_to_cpu(as_out_ep_desc.wMaxPacketSize);
+ 	audio->in_ep_maxpsize = le16_to_cpu(as_in_ep_desc.wMaxPacketSize);
+ 	audio->params.c_chmask = audio_opts->c_chmask;
+ 	audio->params.c_srate = audio_opts->c_srate;
+ 	audio->params.c_ssize = audio_opts->c_ssize;
++	if (FUIN_EN(audio_opts)) {
++		audio->params.p_fu.id = USB_IN_FU_ID;
++		audio->params.p_fu.mute_present = audio_opts->p_mute_present;
++		audio->params.p_fu.volume_present =
++				audio_opts->p_volume_present;
++		audio->params.p_fu.volume_min = audio_opts->p_volume_min;
++		audio->params.p_fu.volume_max = audio_opts->p_volume_max;
++		audio->params.p_fu.volume_res = audio_opts->p_volume_res;
++	}
+ 	audio->params.p_chmask = audio_opts->p_chmask;
+ 	audio->params.p_srate = audio_opts->p_srate;
+ 	audio->params.p_ssize = audio_opts->p_ssize;
++	if (FUOUT_EN(audio_opts)) {
++		audio->params.c_fu.id = USB_OUT_FU_ID;
++		audio->params.c_fu.mute_present = audio_opts->c_mute_present;
++		audio->params.c_fu.volume_present =
++				audio_opts->c_volume_present;
++		audio->params.c_fu.volume_min = audio_opts->c_volume_min;
++		audio->params.c_fu.volume_max = audio_opts->c_volume_max;
++		audio->params.c_fu.volume_res = audio_opts->c_volume_res;
++	}
+ 	audio->params.req_number = audio_opts->req_number;
++	if (FUOUT_EN(audio_opts) || FUIN_EN(audio_opts))
++		audio->notify = audio_notify;
+ 
+ 	status = g_audio_setup(audio, "UAC1_PCM", "UAC1_Gadget");
+ 	if (status)
+@@ -666,7 +1332,14 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f)
+ 
+ err_card_register:
+ 	usb_free_all_descriptors(f);
++err_free_fu:
++	kfree(out_feature_unit_desc);
++	out_feature_unit_desc = NULL;
++	kfree(in_feature_unit_desc);
++	in_feature_unit_desc = NULL;
+ fail:
++	kfree(ac_header_desc);
++	ac_header_desc = NULL;
+ 	return status;
+ }
+ 
+@@ -689,7 +1362,15 @@ static struct configfs_item_operations f_uac1_item_ops = {
+ 	.release	= f_uac1_attr_release,
+ };
+ 
+-#define UAC1_ATTRIBUTE(name)						\
++#define uac1_kstrtou32			kstrtou32
++#define uac1_kstrtos16			kstrtos16
++#define uac1_kstrtobool(s, base, res)	kstrtobool((s), (res))
++
++static const char *u32_fmt = "%u\n";
++static const char *s16_fmt = "%hd\n";
++static const char *bool_fmt = "%u\n";
++
++#define UAC1_ATTRIBUTE(type, name)					\
+ static ssize_t f_uac1_opts_##name##_show(				\
+ 					  struct config_item *item,	\
+ 					  char *page)			\
+@@ -698,7 +1379,7 @@ static ssize_t f_uac1_opts_##name##_show(				\
+ 	int result;							\
+ 									\
+ 	mutex_lock(&opts->lock);					\
+-	result = sprintf(page, "%u\n", opts->name);			\
++	result = sprintf(page, type##_fmt, opts->name);			\
+ 	mutex_unlock(&opts->lock);					\
+ 									\
+ 	return result;							\
+@@ -710,7 +1391,7 @@ static ssize_t f_uac1_opts_##name##_store(				\
+ {									\
+ 	struct f_uac1_opts *opts = to_f_uac1_opts(item);		\
+ 	int ret;							\
+-	u32 num;							\
++	type num;							\
+ 									\
+ 	mutex_lock(&opts->lock);					\
+ 	if (opts->refcnt) {						\
+@@ -718,7 +1399,7 @@ static ssize_t f_uac1_opts_##name##_store(				\
+ 		goto end;						\
+ 	}								\
+ 									\
+-	ret = kstrtou32(page, 0, &num);					\
++	ret = uac1_kstrto##type(page, 0, &num);				\
+ 	if (ret)							\
+ 		goto end;						\
+ 									\
+@@ -732,13 +1413,25 @@ end:									\
+ 									\
+ CONFIGFS_ATTR(f_uac1_opts_, name)
+ 
+-UAC1_ATTRIBUTE(c_chmask);
+-UAC1_ATTRIBUTE(c_srate);
+-UAC1_ATTRIBUTE(c_ssize);
+-UAC1_ATTRIBUTE(p_chmask);
+-UAC1_ATTRIBUTE(p_srate);
+-UAC1_ATTRIBUTE(p_ssize);
+-UAC1_ATTRIBUTE(req_number);
++UAC1_ATTRIBUTE(u32, c_chmask);
++UAC1_ATTRIBUTE(u32, c_srate);
++UAC1_ATTRIBUTE(u32, c_ssize);
++UAC1_ATTRIBUTE(u32, p_chmask);
++UAC1_ATTRIBUTE(u32, p_srate);
++UAC1_ATTRIBUTE(u32, p_ssize);
++UAC1_ATTRIBUTE(u32, req_number);
++
++UAC1_ATTRIBUTE(bool, p_mute_present);
++UAC1_ATTRIBUTE(bool, p_volume_present);
++UAC1_ATTRIBUTE(s16, p_volume_min);
++UAC1_ATTRIBUTE(s16, p_volume_max);
++UAC1_ATTRIBUTE(s16, p_volume_res);
++
++UAC1_ATTRIBUTE(bool, c_mute_present);
++UAC1_ATTRIBUTE(bool, c_volume_present);
++UAC1_ATTRIBUTE(s16, c_volume_min);
++UAC1_ATTRIBUTE(s16, c_volume_max);
++UAC1_ATTRIBUTE(s16, c_volume_res);
+ 
+ static struct configfs_attribute *f_uac1_attrs[] = {
+ 	&f_uac1_opts_attr_c_chmask,
+@@ -748,6 +1441,19 @@ static struct configfs_attribute *f_uac1_attrs[] = {
+ 	&f_uac1_opts_attr_p_srate,
+ 	&f_uac1_opts_attr_p_ssize,
+ 	&f_uac1_opts_attr_req_number,
++
++	&f_uac1_opts_attr_p_mute_present,
++	&f_uac1_opts_attr_p_volume_present,
++	&f_uac1_opts_attr_p_volume_min,
++	&f_uac1_opts_attr_p_volume_max,
++	&f_uac1_opts_attr_p_volume_res,
++
++	&f_uac1_opts_attr_c_mute_present,
++	&f_uac1_opts_attr_c_volume_present,
++	&f_uac1_opts_attr_c_volume_min,
++	&f_uac1_opts_attr_c_volume_max,
++	&f_uac1_opts_attr_c_volume_res,
++
+ 	NULL,
+ };
+ 
+@@ -785,6 +1491,19 @@ static struct usb_function_instance *f_audio_alloc_inst(void)
+ 	opts->p_chmask = UAC1_DEF_PCHMASK;
+ 	opts->p_srate = UAC1_DEF_PSRATE;
+ 	opts->p_ssize = UAC1_DEF_PSSIZE;
++
++	opts->p_mute_present = UAC1_DEF_MUTE_PRESENT;
++	opts->p_volume_present = UAC1_DEF_VOLUME_PRESENT;
++	opts->p_volume_min = UAC1_DEF_MIN_DB;
++	opts->p_volume_max = UAC1_DEF_MAX_DB;
++	opts->p_volume_res = UAC1_DEF_RES_DB;
++
++	opts->c_mute_present = UAC1_DEF_MUTE_PRESENT;
++	opts->c_volume_present = UAC1_DEF_VOLUME_PRESENT;
++	opts->c_volume_min = UAC1_DEF_MIN_DB;
++	opts->c_volume_max = UAC1_DEF_MAX_DB;
++	opts->c_volume_res = UAC1_DEF_RES_DB;
++
+ 	opts->req_number = UAC1_DEF_REQ_NUM;
+ 	return &opts->func_inst;
+ }
+@@ -809,6 +1528,14 @@ static void f_audio_unbind(struct usb_configuration *c, struct usb_function *f)
+ 	g_audio_cleanup(audio);
+ 	usb_free_all_descriptors(f);
+ 
++	kfree(out_feature_unit_desc);
++	out_feature_unit_desc = NULL;
++	kfree(in_feature_unit_desc);
++	in_feature_unit_desc = NULL;
++
++	kfree(ac_header_desc);
++	ac_header_desc = NULL;
++
+ 	audio->gadget = NULL;
+ }
+ 
+@@ -841,4 +1568,4 @@ static struct usb_function *f_audio_alloc(struct usb_function_instance *fi)
+ 
+ DECLARE_USB_FUNCTION_INIT(uac1, f_audio_alloc_inst, f_audio_alloc);
+ MODULE_LICENSE("GPL");
+-MODULE_AUTHOR("Ruslan Bilovol");
++MODULE_AUTHOR("Ruslan Bilovol");
+\ No newline at end of file
+diff --git a/drivers/usb/gadget/function/f_uac2.c b/drivers/usb/gadget/function/f_uac2.c
+index 11cc6056b..5226a47b6 100644
+--- a/drivers/usb/gadget/function/f_uac2.c
++++ b/drivers/usb/gadget/function/f_uac2.c
+@@ -5,6 +5,9 @@
+  * Copyright (C) 2011
+  *    Yadwinder Singh (yadi.brar01@gmail.com)
+  *    Jaswinder Singh (jaswinder.singh@linaro.org)
++ *
++ * Copyright (C) 2020
++ *    Ruslan Bilovol (ruslan.bilovol@gmail.com)
+  */
+ 
+ #include <linux/usb/audio.h>
+@@ -19,14 +22,16 @@
+ 
+ /*
+  * The driver implements a simple UAC_2 topology.
+- * USB-OUT -> IT_1 -> OT_3 -> ALSA_Capture
+- * ALSA_Playback -> IT_2 -> OT_4 -> USB-IN
++ * USB-OUT -> IT_1 -> FU -> OT_3 -> ALSA_Capture
++ * ALSA_Playback -> IT_2 -> FU -> OT_4 -> USB-IN
+  * Capture and Playback sampling rates are independently
+  *  controlled by two clock sources :
+  *    CLK_5 := c_srate, and CLK_6 := p_srate
+  */
+ #define USB_OUT_CLK_ID	(out_clk_src_desc.bClockID)
+ #define USB_IN_CLK_ID	(in_clk_src_desc.bClockID)
++#define USB_OUT_FU_ID	(out_feature_unit_desc->bUnitID)
++#define USB_IN_FU_ID	(in_feature_unit_desc->bUnitID)
+ 
+ #define CONTROL_ABSENT	0
+ #define CONTROL_RDONLY	1
+@@ -34,6 +39,8 @@
+ 
+ #define CLK_FREQ_CTRL	0
+ #define CLK_VLD_CTRL	2
++#define FU_MUTE_CTRL	0
++#define FU_VOL_CTRL	2
+ 
+ #define COPY_CTRL	0
+ #define CONN_CTRL	2
+@@ -44,11 +51,24 @@
+ 
+ #define EPIN_EN(_opts) ((_opts)->p_chmask != 0)
+ #define EPOUT_EN(_opts) ((_opts)->c_chmask != 0)
++#define FUIN_EN(_opts) (EPIN_EN(_opts) \
++				&& ((_opts)->p_mute_present \
++				|| (_opts)->p_volume_present))
++#define FUOUT_EN(_opts) (EPOUT_EN(_opts) \
++				&& ((_opts)->c_mute_present \
++				|| (_opts)->c_volume_present))
++#define EPOUT_FBACK_IN_EN(_opts) ((_opts)->c_sync == USB_ENDPOINT_SYNC_ASYNC)
+ 
+ struct f_uac2 {
+ 	struct g_audio g_audio;
+ 	u8 ac_intf, as_in_intf, as_out_intf;
+ 	u8 ac_alt, as_in_alt, as_out_alt;	/* needed for get_alt() */
++
++	struct usb_ctrlrequest setup_cr;	/* will be used in data stage */
++
++	/* Interrupt IN endpoint of AC interface */
++	struct usb_ep	*int_ep;
++	atomic_t	int_count;
+ };
+ 
+ static inline struct f_uac2 *func_to_uac2(struct usb_function *f)
+@@ -62,6 +82,8 @@ struct f_uac2_opts *g_audio_to_uac2_opts(struct g_audio *agdev)
+ 	return container_of(agdev->func.fi, struct f_uac2_opts, func_inst);
+ }
+ 
++static int afunc_notify(struct g_audio *agdev, int unit_id, int cs);
++
+ /* --------- USB Function Interface ------------- */
+ 
+ enum {
+@@ -73,6 +95,8 @@ enum {
+ 	STR_IO_IT,
+ 	STR_USB_OT,
+ 	STR_IO_OT,
++	STR_FU_IN,
++	STR_FU_OUT,
+ 	STR_AS_OUT_ALT0,
+ 	STR_AS_OUT_ALT1,
+ 	STR_AS_IN_ALT0,
+@@ -91,6 +115,8 @@ static struct usb_string strings_fn[] = {
+ 	[STR_IO_IT].s = "USBD Out",
+ 	[STR_USB_OT].s = "USBH In",
+ 	[STR_IO_OT].s = "USBD In",
++	[STR_FU_IN].s = "Capture Volume",
++	[STR_FU_OUT].s = "Playback Volume",
+ 	[STR_AS_OUT_ALT0].s = "Playback Inactive",
+ 	[STR_AS_OUT_ALT1].s = "Playback Active",
+ 	[STR_AS_IN_ALT0].s = "Capture Inactive",
+@@ -125,7 +151,7 @@ static struct usb_interface_descriptor std_ac_if_desc = {
+ 	.bDescriptorType = USB_DT_INTERFACE,
+ 
+ 	.bAlternateSetting = 0,
+-	.bNumEndpoints = 0,
++	/* .bNumEndpoints = DYNAMIC */
+ 	.bInterfaceClass = USB_CLASS_AUDIO,
+ 	.bInterfaceSubClass = USB_SUBCLASS_AUDIOCONTROL,
+ 	.bInterfaceProtocol = UAC_VERSION_2,
+@@ -211,6 +237,9 @@ static struct uac2_output_terminal_descriptor io_out_ot_desc = {
+ 	.bmControls = cpu_to_le16(CONTROL_RDWR << COPY_CTRL),
+ };
+ 
++static struct uac2_feature_unit_descriptor *in_feature_unit_desc;
++static struct uac2_feature_unit_descriptor *out_feature_unit_desc;
++
+ static struct uac2_ac_header_descriptor ac_hdr_desc = {
+ 	.bLength = sizeof ac_hdr_desc,
+ 	.bDescriptorType = USB_DT_CS_INTERFACE,
+@@ -222,6 +251,36 @@ static struct uac2_ac_header_descriptor ac_hdr_desc = {
+ 	.bmControls = 0,
+ };
+ 
++/* AC IN Interrupt Endpoint */
++static struct usb_endpoint_descriptor fs_ep_int_desc = {
++	.bLength = USB_DT_ENDPOINT_SIZE,
++	.bDescriptorType = USB_DT_ENDPOINT,
++
++	.bEndpointAddress = USB_DIR_IN,
++	.bmAttributes = USB_ENDPOINT_XFER_INT,
++	.wMaxPacketSize = cpu_to_le16(6),
++	.bInterval = 1,
++};
++
++static struct usb_endpoint_descriptor hs_ep_int_desc = {
++	.bLength = USB_DT_ENDPOINT_SIZE,
++	.bDescriptorType = USB_DT_ENDPOINT,
++
++	.bmAttributes = USB_ENDPOINT_XFER_INT,
++	.wMaxPacketSize = cpu_to_le16(6),
++	.bInterval = 4,
++};
++
++static struct usb_endpoint_descriptor ss_ep_int_desc = {
++	.bLength = USB_DT_ENDPOINT_SIZE,
++	.bDescriptorType = USB_DT_ENDPOINT,
++
++	.bEndpointAddress = USB_DIR_IN,
++	.bmAttributes = USB_ENDPOINT_XFER_INT,
++	.wMaxPacketSize = cpu_to_le16(6),
++	.bInterval = 4,
++};
++
+ /* Audio Streaming OUT Interface - Alt0 */
+ static struct usb_interface_descriptor std_as_out_if0_desc = {
+ 	.bLength = sizeof std_as_out_if0_desc,
+@@ -273,7 +332,7 @@ static struct usb_endpoint_descriptor fs_epout_desc = {
+ 	.bDescriptorType = USB_DT_ENDPOINT,
+ 
+ 	.bEndpointAddress = USB_DIR_OUT,
+-	.bmAttributes = USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_SYNC_ASYNC,
++	/* .bmAttributes = DYNAMIC */
+ 	/* .wMaxPacketSize = DYNAMIC */
+ 	.bInterval = 1,
+ };
+@@ -282,11 +341,29 @@ static struct usb_endpoint_descriptor hs_epout_desc = {
+ 	.bLength = USB_DT_ENDPOINT_SIZE,
+ 	.bDescriptorType = USB_DT_ENDPOINT,
+ 
+-	.bmAttributes = USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_SYNC_ASYNC,
++	/* .bmAttributes = DYNAMIC */
++	/* .wMaxPacketSize = DYNAMIC */
++	.bInterval = 4,
++};
++
++static struct usb_endpoint_descriptor ss_epout_desc = {
++	.bLength = USB_DT_ENDPOINT_SIZE,
++	.bDescriptorType = USB_DT_ENDPOINT,
++
++	.bEndpointAddress = USB_DIR_OUT,
++	/* .bmAttributes = DYNAMIC */
+ 	/* .wMaxPacketSize = DYNAMIC */
+ 	.bInterval = 4,
+ };
+ 
++static struct usb_ss_ep_comp_descriptor ss_epout_desc_comp = {
++	.bLength		= sizeof(ss_epout_desc_comp),
++	.bDescriptorType	= USB_DT_SS_ENDPOINT_COMP,
++	.bMaxBurst		= 0,
++	.bmAttributes		= 0,
++	/* wBytesPerInterval = DYNAMIC */
++};
++
+ /* CS AS ISO OUT Endpoint */
+ static struct uac2_iso_endpoint_descriptor as_iso_out_desc = {
+ 	.bLength = sizeof as_iso_out_desc,
+@@ -299,6 +376,45 @@ static struct uac2_iso_endpoint_descriptor as_iso_out_desc = {
+ 	.wLockDelay = 0,
+ };
+ 
++/* STD AS ISO IN Feedback Endpoint */
++static struct usb_endpoint_descriptor fs_epin_fback_desc = {
++	.bLength = USB_DT_ENDPOINT_SIZE,
++	.bDescriptorType = USB_DT_ENDPOINT,
++
++	.bEndpointAddress = USB_DIR_IN,
++	.bmAttributes = USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_USAGE_FEEDBACK,
++	.wMaxPacketSize = cpu_to_le16(3),
++	.bInterval = 1,
++};
++
++static struct usb_endpoint_descriptor hs_epin_fback_desc = {
++	.bLength = USB_DT_ENDPOINT_SIZE,
++	.bDescriptorType = USB_DT_ENDPOINT,
++
++	.bmAttributes = USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_USAGE_FEEDBACK,
++	.wMaxPacketSize = cpu_to_le16(4),
++	.bInterval = 4,
++};
++
++static struct usb_endpoint_descriptor ss_epin_fback_desc = {
++	.bLength = USB_DT_ENDPOINT_SIZE,
++	.bDescriptorType = USB_DT_ENDPOINT,
++
++	.bEndpointAddress = USB_DIR_IN,
++	.bmAttributes = USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_USAGE_FEEDBACK,
++	.wMaxPacketSize = cpu_to_le16(4),
++	.bInterval = 4,
++};
++
++static struct usb_ss_ep_comp_descriptor ss_epin_fback_desc_comp = {
++	.bLength		= sizeof(ss_epin_fback_desc_comp),
++	.bDescriptorType	= USB_DT_SS_ENDPOINT_COMP,
++	.bMaxBurst		= 0,
++	.bmAttributes		= 0,
++	.wBytesPerInterval	= cpu_to_le16(4),
++};
++
++
+ /* Audio Streaming IN Interface - Alt0 */
+ static struct usb_interface_descriptor std_as_in_if0_desc = {
+ 	.bLength = sizeof std_as_in_if0_desc,
+@@ -364,6 +480,24 @@ static struct usb_endpoint_descriptor hs_epin_desc = {
+ 	.bInterval = 4,
+ };
+ 
++static struct usb_endpoint_descriptor ss_epin_desc = {
++	.bLength = USB_DT_ENDPOINT_SIZE,
++	.bDescriptorType = USB_DT_ENDPOINT,
++
++	.bEndpointAddress = USB_DIR_IN,
++	.bmAttributes = USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_SYNC_ASYNC,
++	/* .wMaxPacketSize = DYNAMIC */
++	.bInterval = 4,
++};
++
++static struct usb_ss_ep_comp_descriptor ss_epin_desc_comp = {
++	.bLength		= sizeof(ss_epin_desc_comp),
++	.bDescriptorType	= USB_DT_SS_ENDPOINT_COMP,
++	.bMaxBurst		= 0,
++	.bmAttributes		= 0,
++	/* wBytesPerInterval = DYNAMIC */
++};
++
+ /* CS AS ISO IN Endpoint */
+ static struct uac2_iso_endpoint_descriptor as_iso_in_desc = {
+ 	.bLength = sizeof as_iso_in_desc,
+@@ -384,10 +518,14 @@ static struct usb_descriptor_header *fs_audio_desc[] = {
+ 	(struct usb_descriptor_header *)&in_clk_src_desc,
+ 	(struct usb_descriptor_header *)&out_clk_src_desc,
+ 	(struct usb_descriptor_header *)&usb_out_it_desc,
++	(struct usb_descriptor_header *)&out_feature_unit_desc,
+ 	(struct usb_descriptor_header *)&io_in_it_desc,
+ 	(struct usb_descriptor_header *)&usb_in_ot_desc,
++	(struct usb_descriptor_header *)&in_feature_unit_desc,
+ 	(struct usb_descriptor_header *)&io_out_ot_desc,
+ 
++	(struct usb_descriptor_header *)&fs_ep_int_desc,
++
+ 	(struct usb_descriptor_header *)&std_as_out_if0_desc,
+ 	(struct usb_descriptor_header *)&std_as_out_if1_desc,
+ 
+@@ -395,6 +533,7 @@ static struct usb_descriptor_header *fs_audio_desc[] = {
+ 	(struct usb_descriptor_header *)&as_out_fmt1_desc,
+ 	(struct usb_descriptor_header *)&fs_epout_desc,
+ 	(struct usb_descriptor_header *)&as_iso_out_desc,
++	(struct usb_descriptor_header *)&fs_epin_fback_desc,
+ 
+ 	(struct usb_descriptor_header *)&std_as_in_if0_desc,
+ 	(struct usb_descriptor_header *)&std_as_in_if1_desc,
+@@ -414,10 +553,14 @@ static struct usb_descriptor_header *hs_audio_desc[] = {
+ 	(struct usb_descriptor_header *)&in_clk_src_desc,
+ 	(struct usb_descriptor_header *)&out_clk_src_desc,
+ 	(struct usb_descriptor_header *)&usb_out_it_desc,
++	(struct usb_descriptor_header *)&out_feature_unit_desc,
+ 	(struct usb_descriptor_header *)&io_in_it_desc,
+ 	(struct usb_descriptor_header *)&usb_in_ot_desc,
++	(struct usb_descriptor_header *)&in_feature_unit_desc,
+ 	(struct usb_descriptor_header *)&io_out_ot_desc,
+ 
++	(struct usb_descriptor_header *)&hs_ep_int_desc,
++
+ 	(struct usb_descriptor_header *)&std_as_out_if0_desc,
+ 	(struct usb_descriptor_header *)&std_as_out_if1_desc,
+ 
+@@ -425,6 +568,7 @@ static struct usb_descriptor_header *hs_audio_desc[] = {
+ 	(struct usb_descriptor_header *)&as_out_fmt1_desc,
+ 	(struct usb_descriptor_header *)&hs_epout_desc,
+ 	(struct usb_descriptor_header *)&as_iso_out_desc,
++	(struct usb_descriptor_header *)&hs_epin_fback_desc,
+ 
+ 	(struct usb_descriptor_header *)&std_as_in_if0_desc,
+ 	(struct usb_descriptor_header *)&std_as_in_if1_desc,
+@@ -436,6 +580,55 @@ static struct usb_descriptor_header *hs_audio_desc[] = {
+ 	NULL,
+ };
+ 
++static struct usb_descriptor_header *ss_audio_desc[] = {
++	(struct usb_descriptor_header *)&iad_desc,
++	(struct usb_descriptor_header *)&std_ac_if_desc,
++
++	(struct usb_descriptor_header *)&ac_hdr_desc,
++	(struct usb_descriptor_header *)&in_clk_src_desc,
++	(struct usb_descriptor_header *)&out_clk_src_desc,
++	(struct usb_descriptor_header *)&usb_out_it_desc,
++  (struct usb_descriptor_header *)&out_feature_unit_desc,
++	(struct usb_descriptor_header *)&io_in_it_desc,
++	(struct usb_descriptor_header *)&usb_in_ot_desc,
++	(struct usb_descriptor_header *)&in_feature_unit_desc,
++	(struct usb_descriptor_header *)&io_out_ot_desc,
++
++  (struct usb_descriptor_header *)&ss_ep_int_desc,
++
++	(struct usb_descriptor_header *)&std_as_out_if0_desc,
++	(struct usb_descriptor_header *)&std_as_out_if1_desc,
++
++	(struct usb_descriptor_header *)&as_out_hdr_desc,
++	(struct usb_descriptor_header *)&as_out_fmt1_desc,
++	(struct usb_descriptor_header *)&ss_epout_desc,
++	(struct usb_descriptor_header *)&ss_epout_desc_comp,
++	(struct usb_descriptor_header *)&as_iso_out_desc,
++	(struct usb_descriptor_header *)&ss_epin_fback_desc,
++	(struct usb_descriptor_header *)&ss_epin_fback_desc_comp,
++
++	(struct usb_descriptor_header *)&std_as_in_if0_desc,
++	(struct usb_descriptor_header *)&std_as_in_if1_desc,
++
++	(struct usb_descriptor_header *)&as_in_hdr_desc,
++	(struct usb_descriptor_header *)&as_in_fmt1_desc,
++	(struct usb_descriptor_header *)&ss_epin_desc,
++	(struct usb_descriptor_header *)&ss_epin_desc_comp,
++	(struct usb_descriptor_header *)&as_iso_in_desc,
++	NULL,
++};
++
++struct cntrl_cur_lay2 {
++	__le16	wCUR;
++};
++
++struct cntrl_range_lay2 {
++	__le16	wNumSubRanges;
++	__le16	wMIN;
++	__le16	wMAX;
++	__le16	wRES;
++} __packed;
++
+ struct cntrl_cur_lay3 {
+ 	__le32	dCUR;
+ };
+@@ -462,6 +655,7 @@ static int set_ep_max_packet_size(const struct f_uac2_opts *uac2_opts,
+ 		break;
+ 
+ 	case USB_SPEED_HIGH:
++	case USB_SPEED_SUPER:
+ 		max_size_ep = 1024;
+ 		factor = 8000;
+ 		break;
+@@ -480,17 +674,143 @@ static int set_ep_max_packet_size(const struct f_uac2_opts *uac2_opts,
+ 		ssize = uac2_opts->c_ssize;
+ 	}
+ 
+-	max_size_bw = num_channels(chmask) * ssize *
+-		((srate / (factor / (1 << (ep_desc->bInterval - 1)))) + 1);
++	if (!is_playback && (uac2_opts->c_sync == USB_ENDPOINT_SYNC_ASYNC)) {
++	  // Win10 requires max packet size + 1 frame
++		srate = srate * (1000 + uac2_opts->fb_max) / 1000;
++		// updated srate is always bigger, therefore DIV_ROUND_UP always yields +1
++		max_size_bw = num_channels(chmask) * ssize *
++			(DIV_ROUND_UP(srate, factor / (1 << (ep_desc->bInterval - 1))));
++	} else {
++		// adding 1 frame provision for Win10
++		max_size_bw = num_channels(chmask) * ssize *
++			(DIV_ROUND_UP(srate, factor / (1 << (ep_desc->bInterval - 1))) + 1);
++	}
+ 	ep_desc->wMaxPacketSize = cpu_to_le16(min_t(u16, max_size_bw,
+ 						    max_size_ep));
+ 
+ 	return 0;
+ }
+ 
++static struct uac2_feature_unit_descriptor *build_fu_desc(int chmask)
++{
++	struct uac2_feature_unit_descriptor *fu_desc;
++	int channels = num_channels(chmask);
++	int fu_desc_size = UAC2_DT_FEATURE_UNIT_SIZE(channels);
++
++	fu_desc = kzalloc(fu_desc_size, GFP_KERNEL);
++	if (!fu_desc)
++		return NULL;
++
++	fu_desc->bLength = fu_desc_size;
++	fu_desc->bDescriptorType = USB_DT_CS_INTERFACE;
++
++	fu_desc->bDescriptorSubtype = UAC_FEATURE_UNIT;
++
++	/* bUnitID, bSourceID and bmaControls will be defined later */
++
++	return fu_desc;
++}
++
+ /* Use macro to overcome line length limitation */
+ #define USBDHDR(p) (struct usb_descriptor_header *)(p)
+ 
++static void setup_headers(struct f_uac2_opts *opts,
++			  struct usb_descriptor_header **headers,
++			  enum usb_device_speed speed)
++{
++	struct usb_ss_ep_comp_descriptor *epout_desc_comp = NULL;
++	struct usb_ss_ep_comp_descriptor *epin_desc_comp = NULL;
++	struct usb_ss_ep_comp_descriptor *epin_fback_desc_comp = NULL;
++	struct usb_endpoint_descriptor *epout_desc;
++	struct usb_endpoint_descriptor *epin_desc;
++	struct usb_endpoint_descriptor *epin_fback_desc;
++	struct usb_endpoint_descriptor *ep_int_desc;
++	int i;
++
++	switch (speed) {
++	case USB_SPEED_FULL:
++		epout_desc = &fs_epout_desc;
++		epin_desc = &fs_epin_desc;
++		epin_fback_desc = &fs_epin_fback_desc;
++		ep_int_desc = &fs_ep_int_desc;
++		break;
++	case USB_SPEED_HIGH:
++		epout_desc = &hs_epout_desc;
++		epin_desc = &hs_epin_desc;
++		epin_fback_desc = &hs_epin_fback_desc;
++		ep_int_desc = &hs_ep_int_desc;
++		break;
++	default:
++		epout_desc = &ss_epout_desc;
++		epin_desc = &ss_epin_desc;
++		epout_desc_comp = &ss_epout_desc_comp;
++		epin_desc_comp = &ss_epin_desc_comp;
++		epin_fback_desc = &ss_epin_fback_desc;
++		epin_fback_desc_comp = &ss_epin_fback_desc_comp;
++		ep_int_desc = &ss_ep_int_desc;
++	}
++
++	i = 0;
++	headers[i++] = USBDHDR(&iad_desc);
++	headers[i++] = USBDHDR(&std_ac_if_desc);
++	headers[i++] = USBDHDR(&ac_hdr_desc);
++	if (EPIN_EN(opts))
++		headers[i++] = USBDHDR(&in_clk_src_desc);
++	if (EPOUT_EN(opts)) {
++		headers[i++] = USBDHDR(&out_clk_src_desc);
++		headers[i++] = USBDHDR(&usb_out_it_desc);
++
++    if (FUOUT_EN(opts))
++      headers[i++] = USBDHDR(out_feature_unit_desc);
++  }
++
++	if (EPIN_EN(opts)) {
++		headers[i++] = USBDHDR(&io_in_it_desc);
++
++    if (FUIN_EN(opts))
++      headers[i++] = USBDHDR(in_feature_unit_desc);
++
++		headers[i++] = USBDHDR(&usb_in_ot_desc);
++	}
++
++	if (EPOUT_EN(opts))
++		headers[i++] = USBDHDR(&io_out_ot_desc);
++
++  if (FUOUT_EN(opts) || FUIN_EN(opts))
++      headers[i++] = USBDHDR(ep_int_desc);
++
++  if (EPOUT_EN(opts)) {
++		headers[i++] = USBDHDR(&std_as_out_if0_desc);
++		headers[i++] = USBDHDR(&std_as_out_if1_desc);
++		headers[i++] = USBDHDR(&as_out_hdr_desc);
++		headers[i++] = USBDHDR(&as_out_fmt1_desc);
++		headers[i++] = USBDHDR(epout_desc);
++		if (epout_desc_comp)
++			headers[i++] = USBDHDR(epout_desc_comp);
++
++		headers[i++] = USBDHDR(&as_iso_out_desc);
++
++		if (EPOUT_FBACK_IN_EN(opts)) {
++			headers[i++] = USBDHDR(epin_fback_desc);
++			if (epin_fback_desc_comp)
++				headers[i++] = USBDHDR(epin_fback_desc_comp);
++		}
++	}
++
++	if (EPIN_EN(opts)) {
++		headers[i++] = USBDHDR(&std_as_in_if0_desc);
++		headers[i++] = USBDHDR(&std_as_in_if1_desc);
++		headers[i++] = USBDHDR(&as_in_hdr_desc);
++		headers[i++] = USBDHDR(&as_in_fmt1_desc);
++		headers[i++] = USBDHDR(epin_desc);
++		if (epin_desc_comp)
++			headers[i++] = USBDHDR(epin_desc_comp);
++
++		headers[i++] = USBDHDR(&as_iso_in_desc);
++	}
++	headers[i] = NULL;
++}
++
+ static void setup_descriptor(struct f_uac2_opts *opts)
+ {
+ 	/* patch descriptors */
+@@ -504,17 +824,35 @@ static void setup_descriptor(struct f_uac2_opts *opts)
+ 		io_out_ot_desc.bTerminalID = i++;
+ 	if (EPIN_EN(opts))
+ 		usb_in_ot_desc.bTerminalID = i++;
++	if (FUOUT_EN(opts))
++		out_feature_unit_desc->bUnitID = i++;
++	if (FUIN_EN(opts))
++		in_feature_unit_desc->bUnitID = i++;
+ 	if (EPOUT_EN(opts))
+ 		out_clk_src_desc.bClockID = i++;
+ 	if (EPIN_EN(opts))
+ 		in_clk_src_desc.bClockID = i++;
+ 
+ 	usb_out_it_desc.bCSourceID = out_clk_src_desc.bClockID;
+-	usb_in_ot_desc.bSourceID = io_in_it_desc.bTerminalID;
++
++	if (FUIN_EN(opts)) {
++		usb_in_ot_desc.bSourceID = in_feature_unit_desc->bUnitID;
++		in_feature_unit_desc->bSourceID = io_in_it_desc.bTerminalID;
++	} else {
++		usb_in_ot_desc.bSourceID = io_in_it_desc.bTerminalID;
++	}
++
+ 	usb_in_ot_desc.bCSourceID = in_clk_src_desc.bClockID;
+ 	io_in_it_desc.bCSourceID = in_clk_src_desc.bClockID;
+ 	io_out_ot_desc.bCSourceID = out_clk_src_desc.bClockID;
+-	io_out_ot_desc.bSourceID = usb_out_it_desc.bTerminalID;
++
++	if (FUOUT_EN(opts)) {
++		io_out_ot_desc.bSourceID = out_feature_unit_desc->bUnitID;
++		out_feature_unit_desc->bSourceID = usb_out_it_desc.bTerminalID;
++	} else {
++		io_out_ot_desc.bSourceID = usb_out_it_desc.bTerminalID;
++	}
++
+ 	as_out_hdr_desc.bTerminalLink = usb_out_it_desc.bTerminalID;
+ 	as_in_hdr_desc.bTerminalLink = usb_in_ot_desc.bTerminalID;
+ 
+@@ -526,6 +864,10 @@ static void setup_descriptor(struct f_uac2_opts *opts)
+ 
+ 		len += sizeof(in_clk_src_desc);
+ 		len += sizeof(usb_in_ot_desc);
++
++		if (FUIN_EN(opts))
++			len += in_feature_unit_desc->bLength;
++
+ 		len += sizeof(io_in_it_desc);
+ 		ac_hdr_desc.wTotalLength = cpu_to_le16(len);
+ 		iad_desc.bInterfaceCount++;
+@@ -535,76 +877,18 @@ static void setup_descriptor(struct f_uac2_opts *opts)
+ 
+ 		len += sizeof(out_clk_src_desc);
+ 		len += sizeof(usb_out_it_desc);
++
++		if (FUOUT_EN(opts))
++			len += out_feature_unit_desc->bLength;
++
+ 		len += sizeof(io_out_ot_desc);
+ 		ac_hdr_desc.wTotalLength = cpu_to_le16(len);
+ 		iad_desc.bInterfaceCount++;
+ 	}
+ 
+-	i = 0;
+-	fs_audio_desc[i++] = USBDHDR(&iad_desc);
+-	fs_audio_desc[i++] = USBDHDR(&std_ac_if_desc);
+-	fs_audio_desc[i++] = USBDHDR(&ac_hdr_desc);
+-	if (EPIN_EN(opts))
+-		fs_audio_desc[i++] = USBDHDR(&in_clk_src_desc);
+-	if (EPOUT_EN(opts)) {
+-		fs_audio_desc[i++] = USBDHDR(&out_clk_src_desc);
+-		fs_audio_desc[i++] = USBDHDR(&usb_out_it_desc);
+-	}
+-	if (EPIN_EN(opts)) {
+-		fs_audio_desc[i++] = USBDHDR(&io_in_it_desc);
+-		fs_audio_desc[i++] = USBDHDR(&usb_in_ot_desc);
+-	}
+-	if (EPOUT_EN(opts)) {
+-		fs_audio_desc[i++] = USBDHDR(&io_out_ot_desc);
+-		fs_audio_desc[i++] = USBDHDR(&std_as_out_if0_desc);
+-		fs_audio_desc[i++] = USBDHDR(&std_as_out_if1_desc);
+-		fs_audio_desc[i++] = USBDHDR(&as_out_hdr_desc);
+-		fs_audio_desc[i++] = USBDHDR(&as_out_fmt1_desc);
+-		fs_audio_desc[i++] = USBDHDR(&fs_epout_desc);
+-		fs_audio_desc[i++] = USBDHDR(&as_iso_out_desc);
+-	}
+-	if (EPIN_EN(opts)) {
+-		fs_audio_desc[i++] = USBDHDR(&std_as_in_if0_desc);
+-		fs_audio_desc[i++] = USBDHDR(&std_as_in_if1_desc);
+-		fs_audio_desc[i++] = USBDHDR(&as_in_hdr_desc);
+-		fs_audio_desc[i++] = USBDHDR(&as_in_fmt1_desc);
+-		fs_audio_desc[i++] = USBDHDR(&fs_epin_desc);
+-		fs_audio_desc[i++] = USBDHDR(&as_iso_in_desc);
+-	}
+-	fs_audio_desc[i] = NULL;
+-
+-	i = 0;
+-	hs_audio_desc[i++] = USBDHDR(&iad_desc);
+-	hs_audio_desc[i++] = USBDHDR(&std_ac_if_desc);
+-	hs_audio_desc[i++] = USBDHDR(&ac_hdr_desc);
+-	if (EPIN_EN(opts))
+-		hs_audio_desc[i++] = USBDHDR(&in_clk_src_desc);
+-	if (EPOUT_EN(opts)) {
+-		hs_audio_desc[i++] = USBDHDR(&out_clk_src_desc);
+-		hs_audio_desc[i++] = USBDHDR(&usb_out_it_desc);
+-	}
+-	if (EPIN_EN(opts)) {
+-		hs_audio_desc[i++] = USBDHDR(&io_in_it_desc);
+-		hs_audio_desc[i++] = USBDHDR(&usb_in_ot_desc);
+-	}
+-	if (EPOUT_EN(opts)) {
+-		hs_audio_desc[i++] = USBDHDR(&io_out_ot_desc);
+-		hs_audio_desc[i++] = USBDHDR(&std_as_out_if0_desc);
+-		hs_audio_desc[i++] = USBDHDR(&std_as_out_if1_desc);
+-		hs_audio_desc[i++] = USBDHDR(&as_out_hdr_desc);
+-		hs_audio_desc[i++] = USBDHDR(&as_out_fmt1_desc);
+-		hs_audio_desc[i++] = USBDHDR(&hs_epout_desc);
+-		hs_audio_desc[i++] = USBDHDR(&as_iso_out_desc);
+-	}
+-	if (EPIN_EN(opts)) {
+-		hs_audio_desc[i++] = USBDHDR(&std_as_in_if0_desc);
+-		hs_audio_desc[i++] = USBDHDR(&std_as_in_if1_desc);
+-		hs_audio_desc[i++] = USBDHDR(&as_in_hdr_desc);
+-		hs_audio_desc[i++] = USBDHDR(&as_in_fmt1_desc);
+-		hs_audio_desc[i++] = USBDHDR(&hs_epin_desc);
+-		hs_audio_desc[i++] = USBDHDR(&as_iso_in_desc);
+-	}
+-	hs_audio_desc[i] = NULL;
++	setup_headers(opts, fs_audio_desc, USB_SPEED_FULL);
++	setup_headers(opts, hs_audio_desc, USB_SPEED_HIGH);
++	setup_headers(opts, ss_audio_desc, USB_SPEED_SUPER);
+ }
+ 
+ static int afunc_validate_opts(struct g_audio *agdev, struct device *dev)
+@@ -634,6 +918,28 @@ static int afunc_validate_opts(struct g_audio *agdev, struct device *dev)
+ 		return -EINVAL;
+ 	}
+ 
++	if (opts->p_volume_max <= opts->p_volume_min) {
++		dev_err(dev, "Error: incorrect playback volume max/min\n");
++			return -EINVAL;
++	} else if (opts->c_volume_max <= opts->c_volume_min) {
++		dev_err(dev, "Error: incorrect capture volume max/min\n");
++			return -EINVAL;
++	} else if (opts->p_volume_res <= 0) {
++		dev_err(dev, "Error: negative/zero playback volume resolution\n");
++			return -EINVAL;
++	} else if (opts->c_volume_res <= 0) {
++		dev_err(dev, "Error: negative/zero capture volume resolution\n");
++			return -EINVAL;
++	}
++
++	if ((opts->p_volume_max - opts->p_volume_min) % opts->p_volume_res) {
++		dev_err(dev, "Error: incorrect playback volume resolution\n");
++			return -EINVAL;
++	} else if ((opts->c_volume_max - opts->c_volume_min) % opts->c_volume_res) {
++		dev_err(dev, "Error: incorrect capture volume resolution\n");
++			return -EINVAL;
++	}
++
+ 	return 0;
+ }
+ 
+@@ -656,6 +962,20 @@ afunc_bind(struct usb_configuration *cfg, struct usb_function *fn)
+ 	us = usb_gstrings_attach(cdev, fn_strings, ARRAY_SIZE(strings_fn));
+ 	if (IS_ERR(us))
+ 		return PTR_ERR(us);
++
++	if (FUOUT_EN(uac2_opts)) {
++		out_feature_unit_desc = build_fu_desc(uac2_opts->c_chmask);
++		if (!out_feature_unit_desc)
++			return -ENOMEM;
++	}
++	if (FUIN_EN(uac2_opts)) {
++		in_feature_unit_desc = build_fu_desc(uac2_opts->p_chmask);
++		if (!in_feature_unit_desc) {
++			ret = -ENOMEM;
++			goto err_free_fu;
++		}
++	}
++
+ 	iad_desc.iFunction = us[STR_ASSOC].id;
+ 	std_ac_if_desc.iInterface = us[STR_IF_CTRL].id;
+ 	in_clk_src_desc.iClockSource = us[STR_CLKSRC_IN].id;
+@@ -669,6 +989,17 @@ afunc_bind(struct usb_configuration *cfg, struct usb_function *fn)
+ 	std_as_in_if0_desc.iInterface = us[STR_AS_IN_ALT0].id;
+ 	std_as_in_if1_desc.iInterface = us[STR_AS_IN_ALT1].id;
+ 
++	if (FUOUT_EN(uac2_opts)) {
++		u8 *i_feature = (u8 *)out_feature_unit_desc +
++				out_feature_unit_desc->bLength - 1;
++		*i_feature = us[STR_FU_OUT].id;
++	}
++	if (FUIN_EN(uac2_opts)) {
++		u8 *i_feature = (u8 *)in_feature_unit_desc +
++				in_feature_unit_desc->bLength - 1;
++		*i_feature = us[STR_FU_IN].id;
++	}
++
+ 
+ 	/* Initialize the configurable parameters */
+ 	usb_out_it_desc.bNrChannels = num_channels(uac2_opts->c_chmask);
+@@ -683,6 +1014,26 @@ afunc_bind(struct usb_configuration *cfg, struct usb_function *fn)
+ 	as_out_fmt1_desc.bBitResolution = uac2_opts->c_ssize * 8;
+ 	as_in_fmt1_desc.bSubslotSize = uac2_opts->p_ssize;
+ 	as_in_fmt1_desc.bBitResolution = uac2_opts->p_ssize * 8;
++	if (FUOUT_EN(uac2_opts)) {
++		__le32 *bma = (__le32 *)&out_feature_unit_desc->bmaControls[0];
++		u32 control = 0;
++
++		if (uac2_opts->c_mute_present)
++			control |= CONTROL_RDWR << FU_MUTE_CTRL;
++		if (uac2_opts->c_volume_present)
++			control |= CONTROL_RDWR << FU_VOL_CTRL;
++		*bma = cpu_to_le32(control);
++	}
++	if (FUIN_EN(uac2_opts)) {
++		__le32 *bma = (__le32 *)&in_feature_unit_desc->bmaControls[0];
++		u32 control = 0;
++
++		if (uac2_opts->p_mute_present)
++			control |= CONTROL_RDWR << FU_MUTE_CTRL;
++		if (uac2_opts->p_volume_present)
++			control |= CONTROL_RDWR << FU_VOL_CTRL;
++		*bma = cpu_to_le32(control);
++	}
+ 
+ 	snprintf(clksrc_in, sizeof(clksrc_in), "%uHz", uac2_opts->p_srate);
+ 	snprintf(clksrc_out, sizeof(clksrc_out), "%uHz", uac2_opts->c_srate);
+@@ -690,7 +1041,7 @@ afunc_bind(struct usb_configuration *cfg, struct usb_function *fn)
+ 	ret = usb_interface_id(cfg, fn);
+ 	if (ret < 0) {
+ 		dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
+-		return ret;
++		goto err_free_fu;
+ 	}
+ 	iad_desc.bFirstInterface = ret;
+ 
+@@ -702,19 +1053,36 @@ afunc_bind(struct usb_configuration *cfg, struct usb_function *fn)
+ 		ret = usb_interface_id(cfg, fn);
+ 		if (ret < 0) {
+ 			dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
+-			return ret;
++			goto err_free_fu;
+ 		}
+ 		std_as_out_if0_desc.bInterfaceNumber = ret;
+ 		std_as_out_if1_desc.bInterfaceNumber = ret;
+ 		uac2->as_out_intf = ret;
+ 		uac2->as_out_alt = 0;
++
++		if (EPOUT_FBACK_IN_EN(uac2_opts)) {
++			fs_epout_desc.bmAttributes =
++			  USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_SYNC_ASYNC;
++			hs_epout_desc.bmAttributes =
++			  USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_SYNC_ASYNC;
++			ss_epout_desc.bmAttributes =
++			  USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_SYNC_ASYNC;
++			std_as_out_if1_desc.bNumEndpoints++;
++		} else {
++			fs_epout_desc.bmAttributes =
++			  USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_SYNC_ADAPTIVE;
++			hs_epout_desc.bmAttributes =
++			  USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_SYNC_ADAPTIVE;
++			ss_epout_desc.bmAttributes =
++			  USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_SYNC_ADAPTIVE;
++		}
+ 	}
+ 
+ 	if (EPIN_EN(uac2_opts)) {
+ 		ret = usb_interface_id(cfg, fn);
+ 		if (ret < 0) {
+ 			dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
+-			return ret;
++			goto err_free_fu;
+ 		}
+ 		std_as_in_if0_desc.bInterfaceNumber = ret;
+ 		std_as_in_if1_desc.bInterfaceNumber = ret;
+@@ -722,6 +1090,17 @@ afunc_bind(struct usb_configuration *cfg, struct usb_function *fn)
+ 		uac2->as_in_alt = 0;
+ 	}
+ 
++	if (FUOUT_EN(uac2_opts) || FUIN_EN(uac2_opts)) {
++		uac2->int_ep = usb_ep_autoconfig(gadget, &fs_ep_int_desc);
++		if (!uac2->int_ep) {
++			dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
++			ret = -ENODEV;
++			goto err_free_fu;
++		}
++
++		std_ac_if_desc.bNumEndpoints = 1;
++	}
++
+ 	/* Calculate wMaxPacketSize according to audio bandwidth */
+ 	ret = set_ep_max_packet_size(uac2_opts, &fs_epin_desc, USB_SPEED_FULL,
+ 				     true);
+@@ -751,11 +1130,36 @@ afunc_bind(struct usb_configuration *cfg, struct usb_function *fn)
+ 		return ret;
+ 	}
+ 
++	ret = set_ep_max_packet_size(uac2_opts, &ss_epin_desc, USB_SPEED_SUPER,
++				     true);
++	if (ret < 0) {
++		dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
++		return ret;
++	}
++
++	ret = set_ep_max_packet_size(uac2_opts, &ss_epout_desc, USB_SPEED_SUPER,
++				     false);
++	if (ret < 0) {
++		dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
++		return ret;
++	}
++
+ 	if (EPOUT_EN(uac2_opts)) {
+ 		agdev->out_ep = usb_ep_autoconfig(gadget, &fs_epout_desc);
+ 		if (!agdev->out_ep) {
+ 			dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
+-			return -ENODEV;
++			ret = -ENODEV;
++			goto err_free_fu;
++		}
++		if (EPOUT_FBACK_IN_EN(uac2_opts)) {
++			agdev->in_ep_fback = usb_ep_autoconfig(gadget,
++						       &fs_epin_fback_desc);
++			if (!agdev->in_ep_fback) {
++				dev_err(dev, "%s:%d Error!\n",
++					__func__, __LINE__);
++				ret = -ENODEV;
++				goto err_free_fu;
++			}
+ 		}
+ 	}
+ 
+@@ -763,7 +1167,8 @@ afunc_bind(struct usb_configuration *cfg, struct usb_function *fn)
+ 		agdev->in_ep = usb_ep_autoconfig(gadget, &fs_epin_desc);
+ 		if (!agdev->in_ep) {
+ 			dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
+-			return -ENODEV;
++			ret = -ENODEV;
++			goto err_free_fu;
+ 		}
+ 	}
+ 
+@@ -774,33 +1179,145 @@ afunc_bind(struct usb_configuration *cfg, struct usb_function *fn)
+ 				le16_to_cpu(fs_epout_desc.wMaxPacketSize),
+ 				le16_to_cpu(hs_epout_desc.wMaxPacketSize));
+ 
++	agdev->in_ep_maxpsize = max_t(u16, agdev->in_ep_maxpsize,
++				le16_to_cpu(ss_epin_desc.wMaxPacketSize));
++	agdev->out_ep_maxpsize = max_t(u16, agdev->out_ep_maxpsize,
++				le16_to_cpu(ss_epout_desc.wMaxPacketSize));
++
++	ss_epin_desc_comp.wBytesPerInterval = ss_epin_desc.wMaxPacketSize;
++	ss_epout_desc_comp.wBytesPerInterval = ss_epout_desc.wMaxPacketSize;
++
++	// HS and SS endpoint addresses are copied from autoconfigured FS descriptors
++	hs_ep_int_desc.bEndpointAddress = fs_ep_int_desc.bEndpointAddress;
+ 	hs_epout_desc.bEndpointAddress = fs_epout_desc.bEndpointAddress;
++	hs_epin_fback_desc.bEndpointAddress = fs_epin_fback_desc.bEndpointAddress;
+ 	hs_epin_desc.bEndpointAddress = fs_epin_desc.bEndpointAddress;
++	ss_epout_desc.bEndpointAddress = fs_epout_desc.bEndpointAddress;
++	ss_epin_fback_desc.bEndpointAddress = fs_epin_fback_desc.bEndpointAddress;
++	ss_epin_desc.bEndpointAddress = fs_epin_desc.bEndpointAddress;
++	ss_ep_int_desc.bEndpointAddress = fs_ep_int_desc.bEndpointAddress;
+ 
+ 	setup_descriptor(uac2_opts);
+ 
+-	ret = usb_assign_descriptors(fn, fs_audio_desc, hs_audio_desc, NULL,
+-				     NULL);
++	ret = usb_assign_descriptors(fn, fs_audio_desc, hs_audio_desc, ss_audio_desc,
++				     ss_audio_desc);
+ 	if (ret)
+-		return ret;
++		goto err_free_fu;
+ 
+ 	agdev->gadget = gadget;
+ 
+ 	agdev->params.p_chmask = uac2_opts->p_chmask;
+ 	agdev->params.p_srate = uac2_opts->p_srate;
+ 	agdev->params.p_ssize = uac2_opts->p_ssize;
++	if (FUIN_EN(uac2_opts)) {
++		agdev->params.p_fu.id = USB_IN_FU_ID;
++		agdev->params.p_fu.mute_present = uac2_opts->p_mute_present;
++		agdev->params.p_fu.volume_present = uac2_opts->p_volume_present;
++		agdev->params.p_fu.volume_min = uac2_opts->p_volume_min;
++		agdev->params.p_fu.volume_max = uac2_opts->p_volume_max;
++		agdev->params.p_fu.volume_res = uac2_opts->p_volume_res;
++	}
+ 	agdev->params.c_chmask = uac2_opts->c_chmask;
+ 	agdev->params.c_srate = uac2_opts->c_srate;
+ 	agdev->params.c_ssize = uac2_opts->c_ssize;
++	if (FUOUT_EN(uac2_opts)) {
++		agdev->params.c_fu.id = USB_OUT_FU_ID;
++		agdev->params.c_fu.mute_present = uac2_opts->c_mute_present;
++		agdev->params.c_fu.volume_present = uac2_opts->c_volume_present;
++		agdev->params.c_fu.volume_min = uac2_opts->c_volume_min;
++		agdev->params.c_fu.volume_max = uac2_opts->c_volume_max;
++		agdev->params.c_fu.volume_res = uac2_opts->c_volume_res;
++	}
+ 	agdev->params.req_number = uac2_opts->req_number;
++	agdev->params.fb_max = uac2_opts->fb_max;
++
++	if (FUOUT_EN(uac2_opts) || FUIN_EN(uac2_opts))
++    agdev->notify = afunc_notify;
++
+ 	ret = g_audio_setup(agdev, "UAC2 PCM", "UAC2_Gadget");
+ 	if (ret)
+ 		goto err_free_descs;
++
+ 	return 0;
+ 
+ err_free_descs:
+ 	usb_free_all_descriptors(fn);
+ 	agdev->gadget = NULL;
++err_free_fu:
++	kfree(out_feature_unit_desc);
++	out_feature_unit_desc = NULL;
++	kfree(in_feature_unit_desc);
++	in_feature_unit_desc = NULL;
++	return ret;
++}
++
++static void
++afunc_notify_complete(struct usb_ep *_ep, struct usb_request *req)
++{
++	struct g_audio *agdev = req->context;
++	struct f_uac2 *uac2 = func_to_uac2(&agdev->func);
++
++	atomic_dec(&uac2->int_count);
++	kfree(req->buf);
++	usb_ep_free_request(_ep, req);
++}
++
++static int
++afunc_notify(struct g_audio *agdev, int unit_id, int cs)
++{
++	struct f_uac2 *uac2 = func_to_uac2(&agdev->func);
++	struct usb_request *req;
++	struct uac2_interrupt_data_msg *msg;
++	u16 w_index, w_value;
++	int ret;
++
++	if (!uac2->int_ep->enabled)
++		return 0;
++
++	if (atomic_inc_return(&uac2->int_count) > UAC2_DEF_INT_REQ_NUM) {
++		atomic_dec(&uac2->int_count);
++		return 0;
++	}
++
++	req = usb_ep_alloc_request(uac2->int_ep, GFP_ATOMIC);
++	if (req == NULL) {
++		ret = -ENOMEM;
++		goto err_dec_int_count;
++	}
++
++	msg = kzalloc(sizeof(*msg), GFP_ATOMIC);
++	if (msg == NULL) {
++		ret = -ENOMEM;
++		goto err_free_request;
++	}
++
++	w_index = unit_id << 8 | uac2->ac_intf;
++	w_value = cs << 8;
++
++	msg->bInfo = 0; /* Non-vendor, interface interrupt */
++	msg->bAttribute = UAC2_CS_CUR;
++	msg->wIndex = cpu_to_le16(w_index);
++	msg->wValue = cpu_to_le16(w_value);
++
++	req->length = sizeof(*msg);
++	req->buf = msg;
++	req->context = agdev;
++	req->complete = afunc_notify_complete;
++
++	ret = usb_ep_queue(uac2->int_ep, req, GFP_ATOMIC);
++
++	if (ret)
++		goto err_free_msg;
++
++	return 0;
++
++err_free_msg:
++	kfree(msg);
++err_free_request:
++	usb_ep_free_request(uac2->int_ep, req);
++err_dec_int_count:
++	atomic_dec(&uac2->int_count);
++
+ 	return ret;
+ }
+ 
+@@ -809,6 +1326,7 @@ afunc_set_alt(struct usb_function *fn, unsigned intf, unsigned alt)
+ {
+ 	struct usb_composite_dev *cdev = fn->config->cdev;
+ 	struct f_uac2 *uac2 = func_to_uac2(fn);
++	struct g_audio *agdev = func_to_g_audio(fn);
+ 	struct usb_gadget *gadget = cdev->gadget;
+ 	struct device *dev = &gadget->dev;
+ 	int ret = 0;
+@@ -825,6 +1343,14 @@ afunc_set_alt(struct usb_function *fn, unsigned intf, unsigned alt)
+ 			dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
+ 			return -EINVAL;
+ 		}
++
++		/* restart interrupt endpoint */
++		if (uac2->int_ep) {
++			usb_ep_disable(uac2->int_ep);
++			config_ep_by_speed(gadget, &agdev->func, uac2->int_ep);
++			usb_ep_enable(uac2->int_ep);
++		}
++
+ 		return 0;
+ 	}
+ 
+@@ -879,6 +1405,8 @@ afunc_disable(struct usb_function *fn)
+ 	uac2->as_out_alt = 0;
+ 	u_audio_stop_capture(&uac2->g_audio);
+ 	u_audio_stop_playback(&uac2->g_audio);
++	if (uac2->int_ep)
++		usb_ep_disable(uac2->int_ep);
+ }
+ 
+ static int
+@@ -886,7 +1414,7 @@ in_rq_cur(struct usb_function *fn, const struct usb_ctrlrequest *cr)
+ {
+ 	struct usb_request *req = fn->config->cdev->req;
+ 	struct g_audio *agdev = func_to_g_audio(fn);
+-	struct f_uac2_opts *opts;
++	struct f_uac2_opts *opts = g_audio_to_uac2_opts(agdev);
+ 	u16 w_length = le16_to_cpu(cr->wLength);
+ 	u16 w_index = le16_to_cpu(cr->wIndex);
+ 	u16 w_value = le16_to_cpu(cr->wValue);
+@@ -895,28 +1423,64 @@ in_rq_cur(struct usb_function *fn, const struct usb_ctrlrequest *cr)
+ 	int value = -EOPNOTSUPP;
+ 	int p_srate, c_srate;
+ 
+-	opts = g_audio_to_uac2_opts(agdev);
+ 	p_srate = opts->p_srate;
+ 	c_srate = opts->c_srate;
+ 
+-	if (control_selector == UAC2_CS_CONTROL_SAM_FREQ) {
+-		struct cntrl_cur_lay3 c;
+-		memset(&c, 0, sizeof(struct cntrl_cur_lay3));
++	if ((entity_id == USB_IN_CLK_ID) || (entity_id == USB_OUT_CLK_ID)) {
++		if (control_selector == UAC2_CS_CONTROL_SAM_FREQ) {
++			struct cntrl_cur_lay3 c;
++
++			memset(&c, 0, sizeof(struct cntrl_cur_lay3));
++
++			if (entity_id == USB_IN_CLK_ID)
++				c.dCUR = cpu_to_le32(p_srate);
++			else if (entity_id == USB_OUT_CLK_ID)
++				c.dCUR = cpu_to_le32(c_srate);
++
++			value = min_t(unsigned int, w_length, sizeof(c));
++			memcpy(req->buf, &c, value);
++		} else if (control_selector == UAC2_CS_CONTROL_CLOCK_VALID) {
++			*(u8 *)req->buf = 1;
++			value = min_t(unsigned int, w_length, 1);
++		} else {
++			dev_err(&agdev->gadget->dev,
++				"%s:%d control_selector=%d TODO!\n",
++				__func__, __LINE__, control_selector);
++		}
++	} else if ((FUIN_EN(opts) && (entity_id == USB_IN_FU_ID)) ||
++			(FUOUT_EN(opts) && (entity_id == USB_OUT_FU_ID))) {
++		unsigned int is_playback = 0;
++
++		if (FUIN_EN(opts) && (entity_id == USB_IN_FU_ID))
++			is_playback = 1;
++
++		if (control_selector == UAC_FU_MUTE) {
++			unsigned int mute;
+ 
+-		if (entity_id == USB_IN_CLK_ID)
+-			c.dCUR = cpu_to_le32(p_srate);
+-		else if (entity_id == USB_OUT_CLK_ID)
+-			c.dCUR = cpu_to_le32(c_srate);
++			u_audio_get_mute(agdev, is_playback, &mute);
+ 
+-		value = min_t(unsigned, w_length, sizeof c);
+-		memcpy(req->buf, &c, value);
+-	} else if (control_selector == UAC2_CS_CONTROL_CLOCK_VALID) {
+-		*(u8 *)req->buf = 1;
+-		value = min_t(unsigned, w_length, 1);
++			*(u8 *)req->buf = mute;
++			value = min_t(unsigned int, w_length, 1);
++		} else if (control_selector == UAC_FU_VOLUME) {
++			struct cntrl_cur_lay2 c;
++			s16 volume;
++
++			memset(&c, 0, sizeof(struct cntrl_cur_lay2));
++
++			u_audio_get_volume(agdev, is_playback, &volume);
++			c.wCUR = cpu_to_le16(volume);
++
++			value = min_t(unsigned int, w_length, sizeof(c));
++			memcpy(req->buf, &c, value);
++		} else {
++			dev_err(&agdev->gadget->dev,
++				"%s:%d control_selector=%d TODO!\n",
++				__func__, __LINE__, control_selector);
++		}
+ 	} else {
+ 		dev_err(&agdev->gadget->dev,
+-			"%s:%d control_selector=%d TODO!\n",
+-			__func__, __LINE__, control_selector);
++			"%s:%d entity_id=%d control_selector=%d TODO!\n",
++			__func__, __LINE__, entity_id, control_selector);
+ 	}
+ 
+ 	return value;
+@@ -927,38 +1491,77 @@ in_rq_range(struct usb_function *fn, const struct usb_ctrlrequest *cr)
+ {
+ 	struct usb_request *req = fn->config->cdev->req;
+ 	struct g_audio *agdev = func_to_g_audio(fn);
+-	struct f_uac2_opts *opts;
++	struct f_uac2_opts *opts = g_audio_to_uac2_opts(agdev);
+ 	u16 w_length = le16_to_cpu(cr->wLength);
+ 	u16 w_index = le16_to_cpu(cr->wIndex);
+ 	u16 w_value = le16_to_cpu(cr->wValue);
+ 	u8 entity_id = (w_index >> 8) & 0xff;
+ 	u8 control_selector = w_value >> 8;
+-	struct cntrl_range_lay3 r;
+ 	int value = -EOPNOTSUPP;
+ 	int p_srate, c_srate;
+ 
+-	opts = g_audio_to_uac2_opts(agdev);
+ 	p_srate = opts->p_srate;
+ 	c_srate = opts->c_srate;
+ 
+-	if (control_selector == UAC2_CS_CONTROL_SAM_FREQ) {
+-		if (entity_id == USB_IN_CLK_ID)
+-			r.dMIN = cpu_to_le32(p_srate);
+-		else if (entity_id == USB_OUT_CLK_ID)
+-			r.dMIN = cpu_to_le32(c_srate);
+-		else
+-			return -EOPNOTSUPP;
++	if ((entity_id == USB_IN_CLK_ID) || (entity_id == USB_OUT_CLK_ID)) {
++		if (control_selector == UAC2_CS_CONTROL_SAM_FREQ) {
++			struct cntrl_range_lay3 r;
++
++			if (entity_id == USB_IN_CLK_ID)
++				r.dMIN = cpu_to_le32(p_srate);
++			else if (entity_id == USB_OUT_CLK_ID)
++				r.dMIN = cpu_to_le32(c_srate);
++			else
++				return -EOPNOTSUPP;
+ 
+-		r.dMAX = r.dMIN;
+-		r.dRES = 0;
+-		r.wNumSubRanges = cpu_to_le16(1);
++			r.dMAX = r.dMIN;
++			r.dRES = 0;
++			r.wNumSubRanges = cpu_to_le16(1);
+ 
+-		value = min_t(unsigned, w_length, sizeof r);
+-		memcpy(req->buf, &r, value);
++			value = min_t(unsigned int, w_length, sizeof(r));
++			memcpy(req->buf, &r, value);
++		} else {
++			dev_err(&agdev->gadget->dev,
++				"%s:%d control_selector=%d TODO!\n",
++				__func__, __LINE__, control_selector);
++		}
++	} else if ((FUIN_EN(opts) && (entity_id == USB_IN_FU_ID)) ||
++			(FUOUT_EN(opts) && (entity_id == USB_OUT_FU_ID))) {
++		unsigned int is_playback = 0;
++
++		if (FUIN_EN(opts) && (entity_id == USB_IN_FU_ID))
++			is_playback = 1;
++
++		if (control_selector == UAC_FU_VOLUME) {
++			struct cntrl_range_lay2 r;
++			s16 max_db, min_db, res_db;
++
++			if (is_playback) {
++				max_db = opts->p_volume_max;
++				min_db = opts->p_volume_min;
++				res_db = opts->p_volume_res;
++			} else {
++				max_db = opts->c_volume_max;
++				min_db = opts->c_volume_min;
++				res_db = opts->c_volume_res;
++			}
++
++			r.wMAX = cpu_to_le16(max_db);
++			r.wMIN = cpu_to_le16(min_db);
++			r.wRES = cpu_to_le16(res_db);
++			r.wNumSubRanges = cpu_to_le16(1);
++
++			value = min_t(unsigned int, w_length, sizeof(r));
++			memcpy(req->buf, &r, value);
++		} else {
++			dev_err(&agdev->gadget->dev,
++				"%s:%d control_selector=%d TODO!\n",
++				__func__, __LINE__, control_selector);
++		}
+ 	} else {
+ 		dev_err(&agdev->gadget->dev,
+-			"%s:%d control_selector=%d TODO!\n",
+-			__func__, __LINE__, control_selector);
++			"%s:%d entity_id=%d control_selector=%d TODO!\n",
++			__func__, __LINE__, entity_id, control_selector);
+ 	}
+ 
+ 	return value;
+@@ -975,16 +1578,82 @@ ac_rq_in(struct usb_function *fn, const struct usb_ctrlrequest *cr)
+ 		return -EOPNOTSUPP;
+ }
+ 
++static void
++out_rq_cur_complete(struct usb_ep *ep, struct usb_request *req)
++{
++	struct g_audio *agdev = req->context;
++	struct usb_composite_dev *cdev = agdev->func.config->cdev;
++	struct f_uac2_opts *opts = g_audio_to_uac2_opts(agdev);
++	struct f_uac2 *uac2 = func_to_uac2(&agdev->func);
++	struct usb_ctrlrequest *cr = &uac2->setup_cr;
++	u16 w_index = le16_to_cpu(cr->wIndex);
++	u16 w_value = le16_to_cpu(cr->wValue);
++	u8 entity_id = (w_index >> 8) & 0xff;
++	u8 control_selector = w_value >> 8;
++
++	if (req->status != 0) {
++		dev_dbg(&cdev->gadget->dev, "completion err %d\n", req->status);
++		return;
++	}
++
++	if ((FUIN_EN(opts) && (entity_id == USB_IN_FU_ID)) ||
++		(FUOUT_EN(opts) && (entity_id == USB_OUT_FU_ID))) {
++		unsigned int is_playback = 0;
++
++		if (FUIN_EN(opts) && (entity_id == USB_IN_FU_ID))
++			is_playback = 1;
++
++		if (control_selector == UAC_FU_MUTE) {
++			u8 mute = *(u8 *)req->buf;
++
++			u_audio_set_mute(agdev, is_playback, mute);
++
++			return;
++		} else if (control_selector == UAC_FU_VOLUME) {
++			struct cntrl_cur_lay2 *c = req->buf;
++			s16 volume;
++
++			volume = le16_to_cpu(c->wCUR);
++			u_audio_set_volume(agdev, is_playback, volume);
++
++			return;
++		} else {
++			dev_err(&agdev->gadget->dev,
++				"%s:%d control_selector=%d TODO!\n",
++				__func__, __LINE__, control_selector);
++			usb_ep_set_halt(ep);
++		}
++	}
++}
++
+ static int
+ out_rq_cur(struct usb_function *fn, const struct usb_ctrlrequest *cr)
+ {
++	struct usb_request *req = fn->config->cdev->req;
++	struct g_audio *agdev = func_to_g_audio(fn);
++	struct f_uac2_opts *opts = g_audio_to_uac2_opts(agdev);
++	struct f_uac2 *uac2 = func_to_uac2(fn);
+ 	u16 w_length = le16_to_cpu(cr->wLength);
++	u16 w_index = le16_to_cpu(cr->wIndex);
+ 	u16 w_value = le16_to_cpu(cr->wValue);
++	u8 entity_id = (w_index >> 8) & 0xff;
+ 	u8 control_selector = w_value >> 8;
+ 
+-	if (control_selector == UAC2_CS_CONTROL_SAM_FREQ)
+-		return w_length;
++	if ((entity_id == USB_IN_CLK_ID) || (entity_id == USB_OUT_CLK_ID)) {
++		if (control_selector == UAC2_CS_CONTROL_SAM_FREQ)
++			return w_length;
++	} else if ((FUIN_EN(opts) && (entity_id == USB_IN_FU_ID)) ||
++			(FUOUT_EN(opts) && (entity_id == USB_OUT_FU_ID))) {
++		memcpy(&uac2->setup_cr, cr, sizeof(*cr));
++		req->context = agdev;
++		req->complete = out_rq_cur_complete;
+ 
++		return w_length;
++	} else {
++		dev_err(&agdev->gadget->dev,
++			"%s:%d entity_id=%d control_selector=%d TODO!\n",
++			__func__, __LINE__, entity_id, control_selector);
++	}
+ 	return -EOPNOTSUPP;
+ }
+ 
+@@ -1060,7 +1729,15 @@ static struct configfs_item_operations f_uac2_item_ops = {
+ 	.release	= f_uac2_attr_release,
+ };
+ 
+-#define UAC2_ATTRIBUTE(name)						\
++#define uac2_kstrtou32 kstrtou32
++#define uac2_kstrtos16 kstrtos16
++#define uac2_kstrtobool(s, base, res) kstrtobool((s), (res))
++
++static const char *u32_fmt = "%u\n";
++static const char *s16_fmt = "%hd\n";
++static const char *bool_fmt = "%u\n";
++
++#define UAC2_ATTRIBUTE(type, name)					\
+ static ssize_t f_uac2_opts_##name##_show(struct config_item *item,	\
+ 					 char *page)			\
+ {									\
+@@ -1068,7 +1745,7 @@ static ssize_t f_uac2_opts_##name##_show(struct config_item *item,	\
+ 	int result;							\
+ 									\
+ 	mutex_lock(&opts->lock);					\
+-	result = sprintf(page, "%u\n", opts->name);			\
++	result = sprintf(page, type##_fmt, opts->name);			\
+ 	mutex_unlock(&opts->lock);					\
+ 									\
+ 	return result;							\
+@@ -1079,7 +1756,7 @@ static ssize_t f_uac2_opts_##name##_store(struct config_item *item,	\
+ {									\
+ 	struct f_uac2_opts *opts = to_f_uac2_opts(item);		\
+ 	int ret;							\
+-	u32 num;							\
++	type num;							\
+ 									\
+ 	mutex_lock(&opts->lock);					\
+ 	if (opts->refcnt) {						\
+@@ -1087,7 +1764,7 @@ static ssize_t f_uac2_opts_##name##_store(struct config_item *item,	\
+ 		goto end;						\
+ 	}								\
+ 									\
+-	ret = kstrtou32(page, 0, &num);					\
++	ret = uac2_kstrto##type(page, 0, &num);				\
+ 	if (ret)							\
+ 		goto end;						\
+ 									\
+@@ -1101,13 +1778,83 @@ end:									\
+ 									\
+ CONFIGFS_ATTR(f_uac2_opts_, name)
+ 
+-UAC2_ATTRIBUTE(p_chmask);
+-UAC2_ATTRIBUTE(p_srate);
+-UAC2_ATTRIBUTE(p_ssize);
+-UAC2_ATTRIBUTE(c_chmask);
+-UAC2_ATTRIBUTE(c_srate);
+-UAC2_ATTRIBUTE(c_ssize);
+-UAC2_ATTRIBUTE(req_number);
++#define UAC2_ATTRIBUTE_SYNC(name)					\
++static ssize_t f_uac2_opts_##name##_show(struct config_item *item,	\
++					 char *page)			\
++{									\
++	struct f_uac2_opts *opts = to_f_uac2_opts(item);		\
++	int result;							\
++	char *str;							\
++									\
++	mutex_lock(&opts->lock);					\
++	switch (opts->name) {						\
++	case USB_ENDPOINT_SYNC_ASYNC:					\
++		str = "async";						\
++		break;							\
++	case USB_ENDPOINT_SYNC_ADAPTIVE:				\
++		str = "adaptive";					\
++		break;							\
++	default:							\
++		str = "unknown";					\
++		break;							\
++	}								\
++	result = sprintf(page, "%s\n", str);				\
++	mutex_unlock(&opts->lock);					\
++									\
++	return result;							\
++}									\
++									\
++static ssize_t f_uac2_opts_##name##_store(struct config_item *item,	\
++					  const char *page, size_t len)	\
++{									\
++	struct f_uac2_opts *opts = to_f_uac2_opts(item);		\
++	int ret = 0;							\
++									\
++	mutex_lock(&opts->lock);					\
++	if (opts->refcnt) {						\
++		ret = -EBUSY;						\
++		goto end;						\
++	}								\
++									\
++	if (!strncmp(page, "async", 5))					\
++		opts->name = USB_ENDPOINT_SYNC_ASYNC;			\
++	else if (!strncmp(page, "adaptive", 8))				\
++		opts->name = USB_ENDPOINT_SYNC_ADAPTIVE;		\
++	else {								\
++		ret = -EINVAL;						\
++		goto end;						\
++	}								\
++									\
++	ret = len;							\
++									\
++end:									\
++	mutex_unlock(&opts->lock);					\
++	return ret;							\
++}									\
++									\
++CONFIGFS_ATTR(f_uac2_opts_, name)
++
++UAC2_ATTRIBUTE(u32, p_chmask);
++UAC2_ATTRIBUTE(u32, p_srate);
++UAC2_ATTRIBUTE(u32, p_ssize);
++UAC2_ATTRIBUTE(u32, c_chmask);
++UAC2_ATTRIBUTE(u32, c_srate);
++UAC2_ATTRIBUTE_SYNC(c_sync);
++UAC2_ATTRIBUTE(u32, c_ssize);
++UAC2_ATTRIBUTE(u32, req_number);
++
++UAC2_ATTRIBUTE(bool, p_mute_present);
++UAC2_ATTRIBUTE(bool, p_volume_present);
++UAC2_ATTRIBUTE(s16, p_volume_min);
++UAC2_ATTRIBUTE(s16, p_volume_max);
++UAC2_ATTRIBUTE(s16, p_volume_res);
++
++UAC2_ATTRIBUTE(bool, c_mute_present);
++UAC2_ATTRIBUTE(bool, c_volume_present);
++UAC2_ATTRIBUTE(s16, c_volume_min);
++UAC2_ATTRIBUTE(s16, c_volume_max);
++UAC2_ATTRIBUTE(s16, c_volume_res);
++UAC2_ATTRIBUTE(u32, fb_max);
+ 
+ static struct configfs_attribute *f_uac2_attrs[] = {
+ 	&f_uac2_opts_attr_p_chmask,
+@@ -1116,7 +1863,22 @@ static struct configfs_attribute *f_uac2_attrs[] = {
+ 	&f_uac2_opts_attr_c_chmask,
+ 	&f_uac2_opts_attr_c_srate,
+ 	&f_uac2_opts_attr_c_ssize,
++	&f_uac2_opts_attr_c_sync,
+ 	&f_uac2_opts_attr_req_number,
++	&f_uac2_opts_attr_fb_max,
++
++	&f_uac2_opts_attr_p_mute_present,
++	&f_uac2_opts_attr_p_volume_present,
++	&f_uac2_opts_attr_p_volume_min,
++	&f_uac2_opts_attr_p_volume_max,
++	&f_uac2_opts_attr_p_volume_res,
++
++	&f_uac2_opts_attr_c_mute_present,
++	&f_uac2_opts_attr_c_volume_present,
++	&f_uac2_opts_attr_c_volume_min,
++	&f_uac2_opts_attr_c_volume_max,
++	&f_uac2_opts_attr_c_volume_res,
++
+ 	NULL,
+ };
+ 
+@@ -1154,7 +1916,22 @@ static struct usb_function_instance *afunc_alloc_inst(void)
+ 	opts->c_chmask = UAC2_DEF_CCHMASK;
+ 	opts->c_srate = UAC2_DEF_CSRATE;
+ 	opts->c_ssize = UAC2_DEF_CSSIZE;
++	opts->c_sync = UAC2_DEF_CSYNC;
++
++	opts->p_mute_present = UAC2_DEF_MUTE_PRESENT;
++	opts->p_volume_present = UAC2_DEF_VOLUME_PRESENT;
++	opts->p_volume_min = UAC2_DEF_MIN_DB;
++	opts->p_volume_max = UAC2_DEF_MAX_DB;
++	opts->p_volume_res = UAC2_DEF_RES_DB;
++
++	opts->c_mute_present = UAC2_DEF_MUTE_PRESENT;
++	opts->c_volume_present = UAC2_DEF_VOLUME_PRESENT;
++	opts->c_volume_min = UAC2_DEF_MIN_DB;
++	opts->c_volume_max = UAC2_DEF_MAX_DB;
++	opts->c_volume_res = UAC2_DEF_RES_DB;
++
+ 	opts->req_number = UAC2_DEF_REQ_NUM;
++	opts->fb_max = UAC2_DEF_FB_MAX;
+ 	return &opts->func_inst;
+ }
+ 
+@@ -1179,6 +1956,11 @@ static void afunc_unbind(struct usb_configuration *c, struct usb_function *f)
+ 	usb_free_all_descriptors(f);
+ 
+ 	agdev->gadget = NULL;
++
++	kfree(out_feature_unit_desc);
++	out_feature_unit_desc = NULL;
++	kfree(in_feature_unit_desc);
++	in_feature_unit_desc = NULL;
+ }
+ 
+ static struct usb_function *afunc_alloc(struct usb_function_instance *fi)
+@@ -1211,3 +1993,4 @@ DECLARE_USB_FUNCTION_INIT(uac2, afunc_alloc_inst, afunc_alloc);
+ MODULE_LICENSE("GPL");
+ MODULE_AUTHOR("Yadwinder Singh");
+ MODULE_AUTHOR("Jaswinder Singh");
++MODULE_AUTHOR("Ruslan Bilovol");
+diff --git a/drivers/usb/gadget/function/f_uvc.c b/drivers/usb/gadget/function/f_uvc.c
+index fecdba85a..762c646bf 100644
+--- a/drivers/usb/gadget/function/f_uvc.c
++++ b/drivers/usb/gadget/function/f_uvc.c
+@@ -418,6 +418,7 @@ uvc_register_video(struct uvc_device *uvc)
+ 
+ 	/* TODO reference counting. */
+ 	uvc->vdev.v4l2_dev = &uvc->v4l2_dev;
++	uvc->vdev.v4l2_dev->dev = &cdev->gadget->dev;
+ 	uvc->vdev.fops = &uvc_v4l2_fops;
+ 	uvc->vdev.ioctl_ops = &uvc_v4l2_ioctl_ops;
+ 	uvc->vdev.release = video_device_release_empty;
+@@ -633,7 +634,6 @@ uvc_function_bind(struct usb_configuration *c, struct usb_function *f)
+ 
+ 	uvc_hs_streaming_ep.wMaxPacketSize =
+ 		cpu_to_le16(max_packet_size | ((max_packet_mult - 1) << 11));
+-
+ 	/* A high-bandwidth endpoint must specify a bInterval value of 1 */
+ 	if (max_packet_mult > 1)
+ 		uvc_hs_streaming_ep.bInterval = 1;
+diff --git a/drivers/usb/gadget/function/rndis.c b/drivers/usb/gadget/function/rndis.c
+index eef71a12f..65e3626e2 100644
+--- a/drivers/usb/gadget/function/rndis.c
++++ b/drivers/usb/gadget/function/rndis.c
+@@ -506,10 +506,6 @@ static int gen_ndis_set_resp(struct rndis_params *params, u32 OID,
+ 
+ 	switch (OID) {
+ 	case RNDIS_OID_GEN_CURRENT_PACKET_FILTER:
+-		if (buf_len < 2) {
+-			pr_err("%s:Not support for buf_len < 2\n", __func__);
+-			break;
+-		}
+ 
+ 		/* these NDIS_PACKET_TYPE_* bitflags are shared with
+ 		 * cdc_filter; it's not RNDIS-specific
+@@ -596,7 +592,6 @@ static int rndis_query_response(struct rndis_params *params,
+ 				rndis_query_msg_type *buf)
+ {
+ 	rndis_query_cmplt_type *resp;
+-	u32 BufOffset, BufLength;
+ 	rndis_resp_t *r;
+ 
+ 	/* pr_debug("%s: OID = %08X\n", __func__, cpu_to_le32(buf->OID)); */
+@@ -617,25 +612,12 @@ static int rndis_query_response(struct rndis_params *params,
+ 
+ 	resp->MessageType = cpu_to_le32(RNDIS_MSG_QUERY_C);
+ 	resp->RequestID = buf->RequestID; /* Still LE in msg buffer */
+-	BufOffset = le32_to_cpu(buf->InformationBufferOffset);
+-	BufLength = le32_to_cpu(buf->InformationBufferLength);
+-
+-	/*
+-	 * If the address of the buf to be accessed exceeds the valid
+-	 * range of the buf, then return RNDIS_STATUS_NOT_SUPPORTED.
+-	 */
+-	if (8 + BufOffset + BufLength >= USB_COMP_EP0_BUFSIZ) {
+-		resp->Status = cpu_to_le32(RNDIS_STATUS_NOT_SUPPORTED);
+-		resp->MessageLength = cpu_to_le32(sizeof(*resp));
+-		resp->InformationBufferLength = cpu_to_le32(0);
+-		resp->InformationBufferOffset = cpu_to_le32(0);
+-		params->resp_avail(params->v);
+-		return 0;
+-	}
+ 
+ 	if (gen_ndis_query_resp(params, le32_to_cpu(buf->OID),
+-				BufOffset + 8 + (u8 *)buf, BufLength,
+-				r)) {
++			le32_to_cpu(buf->InformationBufferOffset)
++					+ 8 + (u8 *)buf,
++			le32_to_cpu(buf->InformationBufferLength),
++			r)) {
+ 		/* OID not supported */
+ 		resp->Status = cpu_to_le32(RNDIS_STATUS_NOT_SUPPORTED);
+ 		resp->MessageLength = cpu_to_le32(sizeof *resp);
+@@ -655,18 +637,14 @@ static int rndis_set_response(struct rndis_params *params,
+ 	rndis_set_cmplt_type *resp;
+ 	rndis_resp_t *r;
+ 
+-	BufLength = le32_to_cpu(buf->InformationBufferLength);
+-	BufOffset = le32_to_cpu(buf->InformationBufferOffset);
+-	if ((BufLength > RNDIS_MAX_TOTAL_SIZE) ||
+-	    (BufOffset > RNDIS_MAX_TOTAL_SIZE) ||
+-	    (BufOffset + 8 >= RNDIS_MAX_TOTAL_SIZE))
+-		    return -EINVAL;
+-
+ 	r = rndis_add_response(params, sizeof(rndis_set_cmplt_type));
+ 	if (!r)
+ 		return -ENOMEM;
+ 	resp = (rndis_set_cmplt_type *)r->buf;
+ 
++	BufLength = le32_to_cpu(buf->InformationBufferLength);
++	BufOffset = le32_to_cpu(buf->InformationBufferOffset);
++
+ #ifdef	VERBOSE_DEBUG
+ 	pr_debug("%s: Length: %d\n", __func__, BufLength);
+ 	pr_debug("%s: Offset: %d\n", __func__, BufOffset);
+@@ -682,17 +660,6 @@ static int rndis_set_response(struct rndis_params *params,
+ 	resp->MessageType = cpu_to_le32(RNDIS_MSG_SET_C);
+ 	resp->MessageLength = cpu_to_le32(16);
+ 	resp->RequestID = buf->RequestID; /* Still LE in msg buffer */
+-
+-	/*
+-	 * If the address of the buf to be accessed exceeds the valid
+-	 * range of the buf, then return RNDIS_STATUS_NOT_SUPPORTED.
+-	 */
+-	if (8 + BufOffset + BufLength >= USB_COMP_EP0_BUFSIZ) {
+-		resp->Status = cpu_to_le32(RNDIS_STATUS_NOT_SUPPORTED);
+-		params->resp_avail(params->v);
+-		return 0;
+-	}
+-
+ 	if (gen_ndis_set_resp(params, le32_to_cpu(buf->OID),
+ 			((u8 *)buf) + 8 + BufOffset, BufLength, r))
+ 		resp->Status = cpu_to_le32(RNDIS_STATUS_NOT_SUPPORTED);
+diff --git a/drivers/usb/gadget/function/u_audio.c b/drivers/usb/gadget/function/u_audio.c
+index 95605b1ef..7037a555c 100644
+--- a/drivers/usb/gadget/function/u_audio.c
++++ b/drivers/usb/gadget/function/u_audio.c
+@@ -12,10 +12,14 @@
+  *    Jaswinder Singh (jaswinder.singh@linaro.org)
+  */
+ 
++#include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <sound/core.h>
+ #include <sound/pcm.h>
+ #include <sound/pcm_params.h>
++#include <sound/control.h>
++#include <sound/tlv.h>
++#include <linux/usb/audio.h>
+ 
+ #include "u_audio.h"
+ 
+@@ -23,9 +27,10 @@
+ #define PRD_SIZE_MAX	PAGE_SIZE
+ #define MIN_PERIODS	4
+ 
+-struct uac_req {
+-	struct uac_rtd_params *pp; /* parent param */
+-	struct usb_request *req;
++enum {
++	UAC_FBACK_CTRL,
++	UAC_MUTE_CTRL,
++	UAC_VOLUME_CTRL,
+ };
+ 
+ /* Runtime data params for one stream */
+@@ -40,10 +45,24 @@ struct uac_rtd_params {
+ 
+ 	void *rbuf;
+ 
++	unsigned int pitch;	/* Stream pitch ratio to 1000000 */
+ 	unsigned int max_psize;	/* MaxPacketSize of endpoint */
+-	struct uac_req *ureq;
+ 
+-	spinlock_t lock;
++	struct usb_request **reqs;
++
++	struct usb_request *req_fback; /* Feedback endpoint request */
++	bool fb_ep_enabled; /* if the ep is enabled */
++
++  /* Volume/Mute controls and their state */
++  int fu_id; /* Feature Unit ID */
++  struct snd_kcontrol *snd_kctl_volume;
++  struct snd_kcontrol *snd_kctl_mute;
++  s16 volume_min, volume_max, volume_res;
++  s16 volume;
++  int mute;
++
++  spinlock_t lock; /* lock for control transfers */
++
+ };
+ 
+ struct snd_uac_chip {
+@@ -76,16 +95,63 @@ static const struct snd_pcm_hardware uac_pcm_hardware = {
+ 	.periods_min = MIN_PERIODS,
+ };
+ 
++static void u_audio_set_fback_frequency(enum usb_device_speed speed,
++					struct usb_ep *out_ep,
++					unsigned long long freq,
++					unsigned int pitch,
++					void *buf)
++{
++	u32 ff = 0;
++	const struct usb_endpoint_descriptor *ep_desc;
++
++	/*
++	 * Because the pitch base is 1000000, the final divider here
++	 * will be 1000 * 1000000 = 1953125 << 9
++	 *
++	 * Instead of dealing with big numbers lets fold this 9 left shift
++	 */
++
++	if (speed == USB_SPEED_FULL) {
++		/*
++		 * Full-speed feedback endpoints report frequency
++		 * in samples/frame
++		 * Format is encoded in Q10.10 left-justified in the 24 bits,
++		 * so that it has a Q10.14 format.
++		 *
++		 * ff = (freq << 14) / 1000
++		 */
++		freq <<= 5;
++	} else {
++		/*
++		 * High-speed feedback endpoints report frequency
++		 * in samples/microframe.
++		 * Format is encoded in Q12.13 fitted into four bytes so that
++		 * the binary point is located between the second and the third
++		 * byte fromat (that is Q16.16)
++		 *
++		 * ff = (freq << 16) / 8000
++		 *
++		 * Win10 and OSX UAC2 drivers require number of samples per packet
++		 * in order to honor the feedback value.
++		 * Linux snd-usb-audio detects the applied bit-shift automatically.
++		 */
++		ep_desc = out_ep->desc;
++		freq <<= 4 + (ep_desc->bInterval - 1);
++	}
++
++	ff = DIV_ROUND_CLOSEST_ULL((freq * pitch), 1953125);
++
++	*(__le32 *)buf = cpu_to_le32(ff);
++}
++
+ static void u_audio_iso_complete(struct usb_ep *ep, struct usb_request *req)
+ {
+ 	unsigned int pending;
+-	unsigned long flags, flags2;
+ 	unsigned int hw_ptr;
+ 	int status = req->status;
+-	struct uac_req *ur = req->context;
+ 	struct snd_pcm_substream *substream;
+ 	struct snd_pcm_runtime *runtime;
+-	struct uac_rtd_params *prm = ur->pp;
++	struct uac_rtd_params *prm = req->context;
+ 	struct snd_uac_chip *uac = prm->uac;
+ 
+ 	/* i/f shutting down */
+@@ -111,16 +177,14 @@ static void u_audio_iso_complete(struct usb_ep *ep, struct usb_request *req)
+ 	if (!substream)
+ 		goto exit;
+ 
+-	snd_pcm_stream_lock_irqsave(substream, flags2);
++	snd_pcm_stream_lock(substream);
+ 
+ 	runtime = substream->runtime;
+ 	if (!runtime || !snd_pcm_running(substream)) {
+-		snd_pcm_stream_unlock_irqrestore(substream, flags2);
++		snd_pcm_stream_unlock(substream);
+ 		goto exit;
+ 	}
+ 
+-	spin_lock_irqsave(&prm->lock, flags);
+-
+ 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ 		/*
+ 		 * For each IN packet, take the quotient of the current data
+@@ -147,8 +211,6 @@ static void u_audio_iso_complete(struct usb_ep *ep, struct usb_request *req)
+ 
+ 	hw_ptr = prm->hw_ptr;
+ 
+-	spin_unlock_irqrestore(&prm->lock, flags);
+-
+ 	/* Pack USB load in ALSA ring buffer */
+ 	pending = runtime->dma_bytes - hw_ptr;
+ 
+@@ -172,12 +234,10 @@ static void u_audio_iso_complete(struct usb_ep *ep, struct usb_request *req)
+ 		}
+ 	}
+ 
+-	spin_lock_irqsave(&prm->lock, flags);
+ 	/* update hw_ptr after data is copied to memory */
+ 	prm->hw_ptr = (hw_ptr + req->actual) % runtime->dma_bytes;
+ 	hw_ptr = prm->hw_ptr;
+-	spin_unlock_irqrestore(&prm->lock, flags);
+-	snd_pcm_stream_unlock_irqrestore(substream, flags2);
++	snd_pcm_stream_unlock(substream);
+ 
+ 	if ((hw_ptr % snd_pcm_lib_period_bytes(substream)) < req->actual)
+ 		snd_pcm_period_elapsed(substream);
+@@ -187,13 +247,47 @@ static void u_audio_iso_complete(struct usb_ep *ep, struct usb_request *req)
+ 		dev_err(uac->card->dev, "%d Error!\n", __LINE__);
+ }
+ 
++static void u_audio_iso_fback_complete(struct usb_ep *ep,
++				       struct usb_request *req)
++{
++	struct uac_rtd_params *prm = req->context;
++	struct snd_uac_chip *uac = prm->uac;
++	struct g_audio *audio_dev = uac->audio_dev;
++	struct uac_params *params = &audio_dev->params;
++	int status = req->status;
++
++	/* i/f shutting down */
++	if (!prm->fb_ep_enabled) {
++		kfree(req->buf);
++		usb_ep_free_request(ep, req);
++		return;
++	}
++
++	if (req->status == -ESHUTDOWN)
++		return;
++
++	/*
++	 * We can't really do much about bad xfers.
++	 * Afterall, the ISOCH xfers could fail legitimately.
++	 */
++	if (status)
++		pr_debug("%s: iso_complete status(%d) %d/%d\n",
++			__func__, status, req->actual, req->length);
++
++	u_audio_set_fback_frequency(audio_dev->gadget->speed, audio_dev->out_ep,
++				    params->c_srate, prm->pitch,
++				    req->buf);
++
++	if (usb_ep_queue(ep, req, GFP_ATOMIC))
++		dev_err(uac->card->dev, "%d Error!\n", __LINE__);
++}
++
+ static int uac_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
+ {
+ 	struct snd_uac_chip *uac = snd_pcm_substream_chip(substream);
+ 	struct uac_rtd_params *prm;
+ 	struct g_audio *audio_dev;
+ 	struct uac_params *params;
+-	unsigned long flags;
+ 	int err = 0;
+ 
+ 	audio_dev = uac->audio_dev;
+@@ -204,8 +298,6 @@ static int uac_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
+ 	else
+ 		prm = &uac->c_prm;
+ 
+-	spin_lock_irqsave(&prm->lock, flags);
+-
+ 	/* Reset */
+ 	prm->hw_ptr = 0;
+ 
+@@ -222,8 +314,6 @@ static int uac_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
+ 		err = -EINVAL;
+ 	}
+ 
+-	spin_unlock_irqrestore(&prm->lock, flags);
+-
+ 	/* Clear buffer after Play stops */
+ 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && !prm->ss)
+ 		memset(prm->rbuf, 0, prm->max_psize * params->req_number);
+@@ -244,6 +334,25 @@ static snd_pcm_uframes_t uac_pcm_pointer(struct snd_pcm_substream *substream)
+ 	return bytes_to_frames(substream->runtime, prm->hw_ptr);
+ }
+ 
++static u64 uac_ssize_to_fmt(int ssize)
++{
++	u64 ret;
++
++	switch (ssize) {
++	case 3:
++		ret = SNDRV_PCM_FMTBIT_S24_3LE;
++		break;
++	case 4:
++		ret = SNDRV_PCM_FMTBIT_S32_LE;
++		break;
++	default:
++		ret = SNDRV_PCM_FMTBIT_S16_LE;
++		break;
++	}
++
++	return ret;
++}
++
+ static int uac_pcm_open(struct snd_pcm_substream *substream)
+ {
+ 	struct snd_uac_chip *uac = snd_pcm_substream_chip(substream);
+@@ -267,36 +376,14 @@ static int uac_pcm_open(struct snd_pcm_substream *substream)
+ 	runtime->hw = uac_pcm_hardware;
+ 
+ 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+-		spin_lock_init(&uac->p_prm.lock);
+ 		runtime->hw.rate_min = p_srate;
+-		switch (p_ssize) {
+-		case 3:
+-			runtime->hw.formats = SNDRV_PCM_FMTBIT_S24_3LE;
+-			break;
+-		case 4:
+-			runtime->hw.formats = SNDRV_PCM_FMTBIT_S32_LE;
+-			break;
+-		default:
+-			runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
+-			break;
+-		}
++		runtime->hw.formats = uac_ssize_to_fmt(p_ssize);
+ 		runtime->hw.channels_min = num_channels(p_chmask);
+ 		runtime->hw.period_bytes_min = 2 * uac->p_prm.max_psize
+ 						/ runtime->hw.periods_min;
+ 	} else {
+-		spin_lock_init(&uac->c_prm.lock);
+ 		runtime->hw.rate_min = c_srate;
+-		switch (c_ssize) {
+-		case 3:
+-			runtime->hw.formats = SNDRV_PCM_FMTBIT_S24_3LE;
+-			break;
+-		case 4:
+-			runtime->hw.formats = SNDRV_PCM_FMTBIT_S32_LE;
+-			break;
+-		default:
+-			runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
+-			break;
+-		}
++		runtime->hw.formats = uac_ssize_to_fmt(c_ssize);
+ 		runtime->hw.channels_min = num_channels(c_chmask);
+ 		runtime->hw.period_bytes_min = 2 * uac->c_prm.max_psize
+ 						/ runtime->hw.periods_min;
+@@ -338,16 +425,16 @@ static inline void free_ep(struct uac_rtd_params *prm, struct usb_ep *ep)
+ 	params = &audio_dev->params;
+ 
+ 	for (i = 0; i < params->req_number; i++) {
+-		if (prm->ureq[i].req) {
+-			if (usb_ep_dequeue(ep, prm->ureq[i].req))
+-				usb_ep_free_request(ep, prm->ureq[i].req);
++		if (prm->reqs[i]) {
++			if (usb_ep_dequeue(ep, prm->reqs[i]))
++				usb_ep_free_request(ep, prm->reqs[i]);
+ 			/*
+ 			 * If usb_ep_dequeue() cannot successfully dequeue the
+ 			 * request, the request will be freed by the completion
+ 			 * callback.
+ 			 */
+ 
+-			prm->ureq[i].req = NULL;
++			prm->reqs[i] = NULL;
+ 		}
+ 	}
+ 
+@@ -357,13 +444,34 @@ static inline void free_ep(struct uac_rtd_params *prm, struct usb_ep *ep)
+ 		dev_err(uac->card->dev, "%s:%d Error!\n", __func__, __LINE__);
+ }
+ 
++static inline void free_ep_fback(struct uac_rtd_params *prm, struct usb_ep *ep)
++{
++	struct snd_uac_chip *uac = prm->uac;
++
++	if (!prm->fb_ep_enabled)
++		return;
++
++	if (prm->req_fback) {
++		if (usb_ep_dequeue(ep, prm->req_fback)) {
++			kfree(prm->req_fback->buf);
++			usb_ep_free_request(ep, prm->req_fback);
++		}
++		prm->req_fback = NULL;
++	}
++
++	prm->fb_ep_enabled = false;
++
++	if (usb_ep_disable(ep))
++		dev_err(uac->card->dev, "%s:%d Error!\n", __func__, __LINE__);
++}
++
+ int u_audio_start_capture(struct g_audio *audio_dev)
+ {
+ 	struct snd_uac_chip *uac = audio_dev->uac;
+ 	struct usb_gadget *gadget = audio_dev->gadget;
+ 	struct device *dev = &gadget->dev;
+-	struct usb_request *req;
+-	struct usb_ep *ep;
++	struct usb_request *req, *req_fback;
++	struct usb_ep *ep, *ep_fback;
+ 	struct uac_rtd_params *prm;
+ 	struct uac_params *params = &audio_dev->params;
+ 	int req_len, i;
+@@ -377,25 +485,61 @@ int u_audio_start_capture(struct g_audio *audio_dev)
+ 	usb_ep_enable(ep);
+ 
+ 	for (i = 0; i < params->req_number; i++) {
+-		if (!prm->ureq[i].req) {
++		if (!prm->reqs[i]) {
+ 			req = usb_ep_alloc_request(ep, GFP_ATOMIC);
+ 			if (req == NULL)
+ 				return -ENOMEM;
+ 
+-			prm->ureq[i].req = req;
+-			prm->ureq[i].pp = prm;
++			prm->reqs[i] = req;
+ 
+ 			req->zero = 0;
+-			req->context = &prm->ureq[i];
++			req->context = prm;
+ 			req->length = req_len;
+ 			req->complete = u_audio_iso_complete;
+ 			req->buf = prm->rbuf + i * ep->maxpacket;
+ 		}
+ 
+-		if (usb_ep_queue(ep, prm->ureq[i].req, GFP_ATOMIC))
++		if (usb_ep_queue(ep, prm->reqs[i], GFP_ATOMIC))
+ 			dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
+ 	}
+ 
++	ep_fback = audio_dev->in_ep_fback;
++	if (!ep_fback)
++		return 0;
++
++	/* Setup feedback endpoint */
++	config_ep_by_speed(gadget, &audio_dev->func, ep_fback);
++	prm->fb_ep_enabled = true;
++	usb_ep_enable(ep_fback);
++	req_len = ep_fback->maxpacket;
++
++	req_fback = usb_ep_alloc_request(ep_fback, GFP_ATOMIC);
++	if (req_fback == NULL)
++		return -ENOMEM;
++
++	prm->req_fback = req_fback;
++	req_fback->zero = 0;
++	req_fback->context = prm;
++	req_fback->length = req_len;
++	req_fback->complete = u_audio_iso_fback_complete;
++
++	req_fback->buf = kzalloc(req_len, GFP_ATOMIC);
++	if (!req_fback->buf)
++		return -ENOMEM;
++
++	/*
++	 * Configure the feedback endpoint's reported frequency.
++	 * Always start with original frequency since its deviation can't
++	 * be meauserd at start of playback
++	 */
++	prm->pitch = 1000000;
++	u_audio_set_fback_frequency(audio_dev->gadget->speed, ep,
++				    params->c_srate, prm->pitch,
++				    req_fback->buf);
++
++	if (usb_ep_queue(ep_fback, req_fback, GFP_ATOMIC))
++		dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
++
+ 	return 0;
+ }
+ EXPORT_SYMBOL_GPL(u_audio_start_capture);
+@@ -404,6 +548,8 @@ void u_audio_stop_capture(struct g_audio *audio_dev)
+ {
+ 	struct snd_uac_chip *uac = audio_dev->uac;
+ 
++	if (audio_dev->in_ep_fback)
++		free_ep_fback(&uac->c_prm, audio_dev->in_ep_fback);
+ 	free_ep(&uac->c_prm, audio_dev->out_ep);
+ }
+ EXPORT_SYMBOL_GPL(u_audio_stop_capture);
+@@ -455,22 +601,21 @@ int u_audio_start_playback(struct g_audio *audio_dev)
+ 	usb_ep_enable(ep);
+ 
+ 	for (i = 0; i < params->req_number; i++) {
+-		if (!prm->ureq[i].req) {
++		if (!prm->reqs[i]) {
+ 			req = usb_ep_alloc_request(ep, GFP_ATOMIC);
+ 			if (req == NULL)
+ 				return -ENOMEM;
+ 
+-			prm->ureq[i].req = req;
+-			prm->ureq[i].pp = prm;
++			prm->reqs[i] = req;
+ 
+ 			req->zero = 0;
+-			req->context = &prm->ureq[i];
++			req->context = prm;
+ 			req->length = req_len;
+ 			req->complete = u_audio_iso_complete;
+ 			req->buf = prm->rbuf + i * ep->maxpacket;
+ 		}
+ 
+-		if (usb_ep_queue(ep, prm->ureq[i].req, GFP_ATOMIC))
++		if (usb_ep_queue(ep, prm->reqs[i], GFP_ATOMIC))
+ 			dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
+ 	}
+ 
+@@ -486,15 +631,326 @@ void u_audio_stop_playback(struct g_audio *audio_dev)
+ }
+ EXPORT_SYMBOL_GPL(u_audio_stop_playback);
+ 
++int u_audio_get_volume(struct g_audio *audio_dev, int playback, s16 *val)
++{
++	struct snd_uac_chip *uac = audio_dev->uac;
++	struct uac_rtd_params *prm;
++	unsigned long flags;
++
++	if (playback)
++		prm = &uac->p_prm;
++	else
++		prm = &uac->c_prm;
++
++	spin_lock_irqsave(&prm->lock, flags);
++	*val = prm->volume;
++	spin_unlock_irqrestore(&prm->lock, flags);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(u_audio_get_volume);
++
++int u_audio_set_volume(struct g_audio *audio_dev, int playback, s16 val)
++{
++	struct snd_uac_chip *uac = audio_dev->uac;
++	struct uac_rtd_params *prm;
++	unsigned long flags;
++	int change = 0;
++
++	if (playback)
++		prm = &uac->p_prm;
++	else
++		prm = &uac->c_prm;
++
++	spin_lock_irqsave(&prm->lock, flags);
++	val = clamp(val, prm->volume_min, prm->volume_max);
++	if (prm->volume != val) {
++		prm->volume = val;
++		change = 1;
++	}
++	spin_unlock_irqrestore(&prm->lock, flags);
++
++	if (change)
++		snd_ctl_notify(uac->card, SNDRV_CTL_EVENT_MASK_VALUE,
++				&prm->snd_kctl_volume->id);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(u_audio_set_volume);
++
++int u_audio_get_mute(struct g_audio *audio_dev, int playback, int *val)
++{
++	struct snd_uac_chip *uac = audio_dev->uac;
++	struct uac_rtd_params *prm;
++	unsigned long flags;
++
++	if (playback)
++		prm = &uac->p_prm;
++	else
++		prm = &uac->c_prm;
++
++	spin_lock_irqsave(&prm->lock, flags);
++	*val = prm->mute;
++	spin_unlock_irqrestore(&prm->lock, flags);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(u_audio_get_mute);
++
++int u_audio_set_mute(struct g_audio *audio_dev, int playback, int val)
++{
++	struct snd_uac_chip *uac = audio_dev->uac;
++	struct uac_rtd_params *prm;
++	unsigned long flags;
++	int change = 0;
++	int mute;
++
++	if (playback)
++		prm = &uac->p_prm;
++	else
++		prm = &uac->c_prm;
++
++	mute = val ? 1 : 0;
++
++	spin_lock_irqsave(&prm->lock, flags);
++	if (prm->mute != mute) {
++		prm->mute = mute;
++		change = 1;
++	}
++	spin_unlock_irqrestore(&prm->lock, flags);
++
++	if (change)
++		snd_ctl_notify(uac->card, SNDRV_CTL_EVENT_MASK_VALUE,
++			       &prm->snd_kctl_mute->id);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(u_audio_set_mute);
++
++
++static int u_audio_pitch_info(struct snd_kcontrol *kcontrol,
++				   struct snd_ctl_elem_info *uinfo)
++{
++	struct uac_rtd_params *prm = snd_kcontrol_chip(kcontrol);
++	struct snd_uac_chip *uac = prm->uac;
++	struct g_audio *audio_dev = uac->audio_dev;
++	struct uac_params *params = &audio_dev->params;
++	unsigned int pitch_min, pitch_max;
++
++	pitch_min = (1000 - FBACK_SLOW_MAX) * 1000;
++	pitch_max = (1000 + params->fb_max) * 1000;
++
++	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
++	uinfo->count = 1;
++	uinfo->value.integer.min = pitch_min;
++	uinfo->value.integer.max = pitch_max;
++	uinfo->value.integer.step = 1;
++	return 0;
++}
++
++static int u_audio_pitch_get(struct snd_kcontrol *kcontrol,
++				   struct snd_ctl_elem_value *ucontrol)
++{
++	struct uac_rtd_params *prm = snd_kcontrol_chip(kcontrol);
++
++	ucontrol->value.integer.value[0] = prm->pitch;
++
++	return 0;
++}
++
++static int u_audio_pitch_put(struct snd_kcontrol *kcontrol,
++				  struct snd_ctl_elem_value *ucontrol)
++{
++	struct uac_rtd_params *prm = snd_kcontrol_chip(kcontrol);
++	struct snd_uac_chip *uac = prm->uac;
++	struct g_audio *audio_dev = uac->audio_dev;
++	struct uac_params *params = &audio_dev->params;
++	unsigned int val;
++	unsigned int pitch_min, pitch_max;
++	int change = 0;
++
++	pitch_min = (1000 - FBACK_SLOW_MAX) * 1000;
++	pitch_max = (1000 + params->fb_max) * 1000;
++
++	val = ucontrol->value.integer.value[0];
++
++	if (val < pitch_min)
++		val = pitch_min;
++	if (val > pitch_max)
++		val = pitch_max;
++
++	if (prm->pitch != val) {
++		prm->pitch = val;
++		change = 1;
++	}
++
++	return change;
++}
++
++static int u_audio_mute_info(struct snd_kcontrol *kcontrol,
++				   struct snd_ctl_elem_info *uinfo)
++{
++	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
++	uinfo->count = 1;
++	uinfo->value.integer.min = 0;
++	uinfo->value.integer.max = 1;
++	uinfo->value.integer.step = 1;
++
++	return 0;
++}
++
++static int u_audio_mute_get(struct snd_kcontrol *kcontrol,
++				   struct snd_ctl_elem_value *ucontrol)
++{
++	struct uac_rtd_params *prm = snd_kcontrol_chip(kcontrol);
++	unsigned long flags;
++
++	spin_lock_irqsave(&prm->lock, flags);
++	ucontrol->value.integer.value[0] = !prm->mute;
++	spin_unlock_irqrestore(&prm->lock, flags);
++
++	return 0;
++}
++
++static int u_audio_mute_put(struct snd_kcontrol *kcontrol,
++				  struct snd_ctl_elem_value *ucontrol)
++{
++	struct uac_rtd_params *prm = snd_kcontrol_chip(kcontrol);
++	struct snd_uac_chip *uac = prm->uac;
++	struct g_audio *audio_dev = uac->audio_dev;
++	unsigned int val;
++	unsigned long flags;
++	int change = 0;
++
++	val = !ucontrol->value.integer.value[0];
++
++	spin_lock_irqsave(&prm->lock, flags);
++	if (val != prm->mute) {
++		prm->mute = val;
++		change = 1;
++	}
++	spin_unlock_irqrestore(&prm->lock, flags);
++
++	if (change && audio_dev->notify)
++		audio_dev->notify(audio_dev, prm->fu_id, UAC_FU_MUTE);
++
++	return change;
++}
++
++/*
++ * TLV callback for mixer volume controls
++ */
++static int u_audio_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
++			 unsigned int size, unsigned int __user *_tlv)
++{
++	struct uac_rtd_params *prm = snd_kcontrol_chip(kcontrol);
++	DECLARE_TLV_DB_MINMAX(scale, 0, 0);
++
++	if (size < sizeof(scale))
++		return -ENOMEM;
++
++	/* UAC volume resolution is 1/256 dB, TLV is 1/100 dB */
++	scale[2] = (prm->volume_min * 100) / 256;
++	scale[3] = (prm->volume_max * 100) / 256;
++	if (copy_to_user(_tlv, scale, sizeof(scale)))
++		return -EFAULT;
++
++	return 0;
++}
++
++static int u_audio_volume_info(struct snd_kcontrol *kcontrol,
++				   struct snd_ctl_elem_info *uinfo)
++{
++	struct uac_rtd_params *prm = snd_kcontrol_chip(kcontrol);
++
++	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
++	uinfo->count = 1;
++	uinfo->value.integer.min = 0;
++	uinfo->value.integer.max =
++		(prm->volume_max - prm->volume_min + prm->volume_res - 1)
++		/ prm->volume_res;
++	uinfo->value.integer.step = 1;
++
++	return 0;
++}
++
++static int u_audio_volume_get(struct snd_kcontrol *kcontrol,
++				   struct snd_ctl_elem_value *ucontrol)
++{
++	struct uac_rtd_params *prm = snd_kcontrol_chip(kcontrol);
++	unsigned long flags;
++
++	spin_lock_irqsave(&prm->lock, flags);
++	ucontrol->value.integer.value[0] =
++			(prm->volume - prm->volume_min) / prm->volume_res;
++	spin_unlock_irqrestore(&prm->lock, flags);
++
++	return 0;
++}
++
++static int u_audio_volume_put(struct snd_kcontrol *kcontrol,
++				  struct snd_ctl_elem_value *ucontrol)
++{
++	struct uac_rtd_params *prm = snd_kcontrol_chip(kcontrol);
++	struct snd_uac_chip *uac = prm->uac;
++	struct g_audio *audio_dev = uac->audio_dev;
++	unsigned int val;
++	s16 volume;
++	unsigned long flags;
++	int change = 0;
++
++	val = ucontrol->value.integer.value[0];
++
++	spin_lock_irqsave(&prm->lock, flags);
++	volume = (val * prm->volume_res) + prm->volume_min;
++	volume = clamp(volume, prm->volume_min, prm->volume_max);
++	if (volume != prm->volume) {
++		prm->volume = volume;
++		change = 1;
++	}
++	spin_unlock_irqrestore(&prm->lock, flags);
++
++	if (change && audio_dev->notify)
++		audio_dev->notify(audio_dev, prm->fu_id, UAC_FU_VOLUME);
++
++	return change;
++}
++
++
++static struct snd_kcontrol_new u_audio_controls[]  = {
++  [UAC_FBACK_CTRL] {
++    .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
++    .name =         "Capture Pitch 1000000",
++    .info =         u_audio_pitch_info,
++    .get =          u_audio_pitch_get,
++    .put =          u_audio_pitch_put,
++  },
++  [UAC_MUTE_CTRL] {
++		.iface =	SNDRV_CTL_ELEM_IFACE_MIXER,
++		.name =		"", /* will be filled later */
++		.info =		u_audio_mute_info,
++		.get =		u_audio_mute_get,
++		.put =		u_audio_mute_put,
++	},
++	[UAC_VOLUME_CTRL] {
++		.iface =	SNDRV_CTL_ELEM_IFACE_MIXER,
++		.name =		"", /* will be filled later */
++		.info =		u_audio_volume_info,
++		.get =		u_audio_volume_get,
++		.put =		u_audio_volume_put,
++	},
++};
++
+ int g_audio_setup(struct g_audio *g_audio, const char *pcm_name,
+ 					const char *card_name)
+ {
+ 	struct snd_uac_chip *uac;
+ 	struct snd_card *card;
+ 	struct snd_pcm *pcm;
++	struct snd_kcontrol *kctl;
+ 	struct uac_params *params;
+ 	int p_chmask, c_chmask;
+-	int err;
++	int i, err;
+ 
+ 	if (!g_audio)
+ 		return -EINVAL;
+@@ -512,12 +968,14 @@ int g_audio_setup(struct g_audio *g_audio, const char *pcm_name,
+ 	if (c_chmask) {
+ 		struct uac_rtd_params *prm = &uac->c_prm;
+ 
+-		uac->c_prm.uac = uac;
++    spin_lock_init(&prm->lock);
++    uac->c_prm.uac = uac;
+ 		prm->max_psize = g_audio->out_ep_maxpsize;
+ 
+-		prm->ureq = kcalloc(params->req_number, sizeof(struct uac_req),
+-				GFP_KERNEL);
+-		if (!prm->ureq) {
++		prm->reqs = kcalloc(params->req_number,
++				    sizeof(struct usb_request *),
++				    GFP_KERNEL);
++		if (!prm->reqs) {
+ 			err = -ENOMEM;
+ 			goto fail;
+ 		}
+@@ -534,12 +992,14 @@ int g_audio_setup(struct g_audio *g_audio, const char *pcm_name,
+ 	if (p_chmask) {
+ 		struct uac_rtd_params *prm = &uac->p_prm;
+ 
++		spin_lock_init(&prm->lock);
+ 		uac->p_prm.uac = uac;
+ 		prm->max_psize = g_audio->in_ep_maxpsize;
+ 
+-		prm->ureq = kcalloc(params->req_number, sizeof(struct uac_req),
+-				GFP_KERNEL);
+-		if (!prm->ureq) {
++		prm->reqs = kcalloc(params->req_number,
++				    sizeof(struct usb_request *),
++				    GFP_KERNEL);
++		if (!prm->reqs) {
+ 			err = -ENOMEM;
+ 			goto fail;
+ 		}
+@@ -570,15 +1030,116 @@ int g_audio_setup(struct g_audio *g_audio, const char *pcm_name,
+ 	if (err < 0)
+ 		goto snd_fail;
+ 
+-	strlcpy(pcm->name, pcm_name, sizeof(pcm->name));
++	strscpy(pcm->name, pcm_name, sizeof(pcm->name));
+ 	pcm->private_data = uac;
+ 	uac->pcm = pcm;
+ 
+ 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &uac_pcm_ops);
+ 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &uac_pcm_ops);
+ 
+-	strlcpy(card->driver, card_name, sizeof(card->driver));
+-	strlcpy(card->shortname, card_name, sizeof(card->shortname));
++	/*
++	 * Create mixer and controls
++	 * Create only if it's required on USB side
++	 */
++	if ((c_chmask && g_audio->in_ep_fback)
++			|| (p_chmask && params->p_fu.id)
++			|| (c_chmask && params->c_fu.id))
++		strscpy(card->mixername, card_name, sizeof(card->driver));
++
++	if (c_chmask && g_audio->in_ep_fback) {
++		kctl = snd_ctl_new1(&u_audio_controls[UAC_FBACK_CTRL],
++				    &uac->c_prm);
++		if (!kctl) {
++			err = -ENOMEM;
++			goto snd_fail;
++		}
++
++		kctl->id.device = pcm->device;
++		kctl->id.subdevice = 0;
++
++		err = snd_ctl_add(card, kctl);
++		if (err < 0)
++			goto snd_fail;
++	}
++
++	for (i = 0; i <= SNDRV_PCM_STREAM_LAST; i++) {
++		struct uac_rtd_params *prm;
++		struct uac_fu_params *fu;
++		char ctrl_name[24];
++		char *direction;
++
++		if (!pcm->streams[i].substream_count)
++			continue;
++
++		if (i == SNDRV_PCM_STREAM_PLAYBACK) {
++			prm = &uac->p_prm;
++			fu = &params->p_fu;
++			direction = "Playback";
++		} else {
++			prm = &uac->c_prm;
++			fu = &params->c_fu;
++			direction = "Capture";
++		}
++
++		prm->fu_id = fu->id;
++
++		if (fu->mute_present) {
++			snprintf(ctrl_name, sizeof(ctrl_name),
++					"PCM %s Switch", direction);
++
++			u_audio_controls[UAC_MUTE_CTRL].name = ctrl_name;
++
++			kctl = snd_ctl_new1(&u_audio_controls[UAC_MUTE_CTRL],
++					    prm);
++			if (!kctl) {
++				err = -ENOMEM;
++				goto snd_fail;
++			}
++
++			kctl->id.device = pcm->device;
++			kctl->id.subdevice = i;
++
++			err = snd_ctl_add(card, kctl);
++			if (err < 0)
++				goto snd_fail;
++			prm->snd_kctl_mute = kctl;
++			prm->mute = 0;
++		}
++
++		if (fu->volume_present) {
++			snprintf(ctrl_name, sizeof(ctrl_name),
++					"PCM %s Volume", direction);
++
++			u_audio_controls[UAC_VOLUME_CTRL].name = ctrl_name;
++
++			kctl = snd_ctl_new1(&u_audio_controls[UAC_VOLUME_CTRL],
++					    prm);
++			if (!kctl) {
++				err = -ENOMEM;
++				goto snd_fail;
++			}
++
++			kctl->id.device = pcm->device;
++			kctl->id.subdevice = i;
++
++
++			kctl->tlv.c = u_audio_volume_tlv;
++			kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_TLV_READ |
++					SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
++
++			err = snd_ctl_add(card, kctl);
++			if (err < 0)
++				goto snd_fail;
++			prm->snd_kctl_volume = kctl;
++			prm->volume = fu->volume_max;
++			prm->volume_max = fu->volume_max;
++			prm->volume_min = fu->volume_min;
++			prm->volume_res = fu->volume_res;
++		}
++	}
++
++	strscpy(card->driver, card_name, sizeof(card->driver));
++	strscpy(card->shortname, card_name, sizeof(card->shortname));
+ 	sprintf(card->longname, "%s %i", card_name, card->dev->id);
+ 
+ 	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
+@@ -592,8 +1153,8 @@ int g_audio_setup(struct g_audio *g_audio, const char *pcm_name,
+ snd_fail:
+ 	snd_card_free(card);
+ fail:
+-	kfree(uac->p_prm.ureq);
+-	kfree(uac->c_prm.ureq);
++	kfree(uac->p_prm.reqs);
++	kfree(uac->c_prm.reqs);
+ 	kfree(uac->p_prm.rbuf);
+ 	kfree(uac->c_prm.rbuf);
+ 	kfree(uac);
+@@ -615,8 +1176,8 @@ void g_audio_cleanup(struct g_audio *g_audio)
+ 	if (card)
+ 		snd_card_free(card);
+ 
+-	kfree(uac->p_prm.ureq);
+-	kfree(uac->c_prm.ureq);
++	kfree(uac->p_prm.reqs);
++	kfree(uac->c_prm.reqs);
+ 	kfree(uac->p_prm.rbuf);
+ 	kfree(uac->c_prm.rbuf);
+ 	kfree(uac);
+@@ -625,4 +1186,4 @@ EXPORT_SYMBOL_GPL(g_audio_cleanup);
+ 
+ MODULE_LICENSE("GPL");
+ MODULE_DESCRIPTION("USB gadget \"ALSA sound card\" utilities");
+-MODULE_AUTHOR("Ruslan Bilovol");
++MODULE_AUTHOR("Ruslan Bilovol");
+\ No newline at end of file
+diff --git a/drivers/usb/gadget/function/u_audio.h b/drivers/usb/gadget/function/u_audio.h
+index 5ea6b86f1..001a79a46 100644
+--- a/drivers/usb/gadget/function/u_audio.h
++++ b/drivers/usb/gadget/function/u_audio.h
+@@ -11,18 +11,41 @@
+ 
+ #include <linux/usb/composite.h>
+ 
++/*
++ * Same maximum frequency deviation on the slower side as in
++ * sound/usb/endpoint.c. Value is expressed in per-mil deviation.
++ * The maximum deviation on the faster side will be provided as
++ * parameter, as it impacts the endpoint required bandwidth.
++ */
++#define FBACK_SLOW_MAX	250
++
++/* Feature Unit parameters */
++struct uac_fu_params {
++	int id;			/* Feature Unit ID */
++
++	bool mute_present;	/* mute control enable */
++
++	bool volume_present;	/* volume control enable */
++	s16 volume_min;		/* min volume in 1/256 dB */
++	s16 volume_max;		/* max volume in 1/256 dB */
++	s16 volume_res;		/* volume resolution in 1/256 dB */
++};
++
+ struct uac_params {
+ 	/* playback */
+ 	int p_chmask;	/* channel mask */
+ 	int p_srate;	/* rate in Hz */
+ 	int p_ssize;	/* sample size */
++	struct uac_fu_params p_fu;	/* Feature Unit parameters */
+ 
+ 	/* capture */
+ 	int c_chmask;	/* channel mask */
+ 	int c_srate;	/* rate in Hz */
+ 	int c_ssize;	/* sample size */
++	struct uac_fu_params c_fu;	/* Feature Unit parameters */
+ 
+ 	int req_number; /* number of preallocated requests */
++	int fb_max;	/* upper frequency drift feedback limit per-mil */
+ };
+ 
+ struct g_audio {
+@@ -30,13 +53,19 @@ struct g_audio {
+ 	struct usb_gadget *gadget;
+ 
+ 	struct usb_ep *in_ep;
++
+ 	struct usb_ep *out_ep;
++	/* feedback IN endpoint corresponding to out_ep */
++	struct usb_ep *in_ep_fback;
+ 
+ 	/* Max packet size for all in_ep possible speeds */
+ 	unsigned int in_ep_maxpsize;
+ 	/* Max packet size for all out_ep possible speeds */
+ 	unsigned int out_ep_maxpsize;
+ 
++	/* Notify UAC driver about control change */
++	int (*notify)(struct g_audio *g_audio, int unit_id, int cs);
++
+ 	/* The ALSA Sound Card it represents on the USB-Client side */
+ 	struct snd_uac_chip *uac;
+ 
+@@ -82,4 +111,9 @@ void u_audio_stop_capture(struct g_audio *g_audio);
+ int u_audio_start_playback(struct g_audio *g_audio);
+ void u_audio_stop_playback(struct g_audio *g_audio);
+ 
++int u_audio_get_volume(struct g_audio *g_audio, int playback, s16 *val);
++int u_audio_set_volume(struct g_audio *g_audio, int playback, s16 val);
++int u_audio_get_mute(struct g_audio *g_audio, int playback, int *val);
++int u_audio_set_mute(struct g_audio *g_audio, int playback, int val);
++
+ #endif /* __U_AUDIO_H */
+diff --git a/drivers/usb/gadget/function/u_ether.c b/drivers/usb/gadget/function/u_ether.c
+index 64ef97ab9..904c394df 100644
+--- a/drivers/usb/gadget/function/u_ether.c
++++ b/drivers/usb/gadget/function/u_ether.c
+@@ -80,6 +80,7 @@ struct eth_dev {
+ 
+ 	bool			zlp;
+ 	bool			no_skb_reserve;
++	bool			ifname_set;
+ 	u8			host_mac[ETH_ALEN];
+ 	u8			dev_mac[ETH_ALEN];
+ };
+@@ -867,6 +868,7 @@ int gether_register_netdev(struct net_device *net)
+ {
+ 	struct eth_dev *dev;
+ 	struct usb_gadget *g;
++	struct sockaddr sa;
+ 	int status;
+ 
+ 	if (!net->dev.parent)
+@@ -874,15 +876,12 @@ int gether_register_netdev(struct net_device *net)
+ 	dev = netdev_priv(net);
+ 	g = dev->gadget;
+ 
+-	memcpy(net->dev_addr, dev->dev_mac, ETH_ALEN);
+-
+ 	status = register_netdev(net);
+ 	if (status < 0) {
+ 		dev_dbg(&g->dev, "register_netdev failed, %d\n", status);
+ 		return status;
+ 	} else {
+ 		INFO(dev, "HOST MAC %pM\n", dev->host_mac);
+-		INFO(dev, "MAC %pM\n", dev->dev_mac);
+ 
+ 		/* two kinds of host-initiated state changes:
+ 		 *  - iff DATA transfer is active, carrier is "on"
+@@ -890,6 +889,15 @@ int gether_register_netdev(struct net_device *net)
+ 		 */
+ 		netif_carrier_off(net);
+ 	}
++	sa.sa_family = net->type;
++	memcpy(sa.sa_data, dev->dev_mac, ETH_ALEN);
++	rtnl_lock();
++	status = dev_set_mac_address(net, &sa, NULL);
++	rtnl_unlock();
++	if (status)
++		pr_warn("cannot set self ethernet address: %d\n", status);
++	else
++		INFO(dev, "MAC %pM\n", dev->dev_mac);
+ 
+ 	return status;
+ }
+@@ -1007,15 +1015,45 @@ EXPORT_SYMBOL_GPL(gether_get_qmult);
+ 
+ int gether_get_ifname(struct net_device *net, char *name, int len)
+ {
++	struct eth_dev *dev = netdev_priv(net);
+ 	int ret;
+ 
+ 	rtnl_lock();
+-	ret = scnprintf(name, len, "%s\n", netdev_name(net));
++	ret = scnprintf(name, len, "%s\n",
++			dev->ifname_set ? net->name : netdev_name(net));
+ 	rtnl_unlock();
+ 	return ret;
+ }
+ EXPORT_SYMBOL_GPL(gether_get_ifname);
+ 
++int gether_set_ifname(struct net_device *net, const char *name, int len)
++{
++	struct eth_dev *dev = netdev_priv(net);
++	char tmp[IFNAMSIZ];
++	const char *p;
++
++	if (name[len - 1] == '\n')
++		len--;
++
++	if (len >= sizeof(tmp))
++		return -E2BIG;
++
++	strscpy(tmp, name, len + 1);
++	if (!dev_valid_name(tmp))
++		return -EINVAL;
++
++	/* Require exactly one %d, so binding will not fail with EEXIST. */
++	p = strchr(name, '%');
++	if (!p || p[1] != 'd' || strchr(p + 2, '%'))
++		return -EINVAL;
++
++	strncpy(net->name, tmp, sizeof(net->name));
++	dev->ifname_set = true;
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(gether_set_ifname);
++
+ /*
+  * gether_cleanup - remove Ethernet-over-USB device
+  * Context: may sleep
+diff --git a/drivers/usb/gadget/function/u_ether.h b/drivers/usb/gadget/function/u_ether.h
+index 10dd64068..40144546d 100644
+--- a/drivers/usb/gadget/function/u_ether.h
++++ b/drivers/usb/gadget/function/u_ether.h
+@@ -244,6 +244,18 @@ unsigned gether_get_qmult(struct net_device *net);
+  */
+ int gether_get_ifname(struct net_device *net, char *name, int len);
+ 
++/**
++ * gether_set_ifname - set an ethernet-over-usb link interface name
++ * @net: device representing this link
++ * @name: new interface name
++ * @len: length of @name
++ *
++ * This sets the interface name of this ethernet-over-usb link.
++ * A single terminating newline, if any, is ignored.
++ * Returns zero on success, else negative errno.
++ */
++int gether_set_ifname(struct net_device *net, const char *name, int len);
++
+ void gether_cleanup(struct eth_dev *dev);
+ 
+ /* connect/disconnect is handled by individual functions */
+diff --git a/drivers/usb/gadget/function/u_ether_configfs.h b/drivers/usb/gadget/function/u_ether_configfs.h
+index f982e18a5..f558c3139 100644
+--- a/drivers/usb/gadget/function/u_ether_configfs.h
++++ b/drivers/usb/gadget/function/u_ether_configfs.h
+@@ -148,7 +148,20 @@ out:									\
+ 		return ret;						\
+ 	}								\
+ 									\
+-	CONFIGFS_ATTR_RO(_f_##_opts_, ifname)
++	static ssize_t _f_##_opts_ifname_store(struct config_item *item, \
++					       const char *page, size_t len)\
++	{								\
++		struct f_##_f_##_opts *opts = to_f_##_f_##_opts(item);	\
++		int ret = -EBUSY;					\
++									\
++		mutex_lock(&opts->lock);				\
++		if (!opts->refcnt)					\
++			ret = gether_set_ifname(opts->net, page, len);	\
++		mutex_unlock(&opts->lock);				\
++		return ret ?: len;					\
++	}								\
++									\
++	CONFIGFS_ATTR(_f_##_opts_, ifname)
+ 
+ #define USB_ETHER_CONFIGFS_ITEM_ATTR_U8_RW(_f_, _n_)			\
+ 	static ssize_t _f_##_opts_##_n_##_show(struct config_item *item,\
+diff --git a/drivers/usb/gadget/function/u_hid.h b/drivers/usb/gadget/function/u_hid.h
+index 84e6da302..84bb70292 100644
+--- a/drivers/usb/gadget/function/u_hid.h
++++ b/drivers/usb/gadget/function/u_hid.h
+@@ -20,6 +20,7 @@ struct f_hid_opts {
+ 	int				minor;
+ 	unsigned char			subclass;
+ 	unsigned char			protocol;
++	unsigned char			no_out_endpoint;
+ 	unsigned short			report_length;
+ 	unsigned short			report_desc_length;
+ 	unsigned char			*report_desc;
+@@ -29,8 +30,8 @@ struct f_hid_opts {
+ 	 * Protect the data form concurrent access by read/write
+ 	 * and create symlink/remove symlink.
+ 	 */
+-	 struct mutex			lock;
+-	 int				refcnt;
++	struct mutex			lock;
++	int				refcnt;
+ };
+ 
+ int ghid_setup(struct usb_gadget *g, int count);
+diff --git a/drivers/usb/gadget/function/u_midi.h b/drivers/usb/gadget/function/u_midi.h
+index f6e14af7f..2e400b495 100644
+--- a/drivers/usb/gadget/function/u_midi.h
++++ b/drivers/usb/gadget/function/u_midi.h
+@@ -29,8 +29,8 @@ struct f_midi_opts {
+ 	 * Protect the data form concurrent access by read/write
+ 	 * and create symlink/remove symlink.
+ 	 */
+-	 struct mutex			lock;
+-	 int				refcnt;
++	struct mutex			lock;
++	int				refcnt;
+ };
+ 
+ #endif /* U_MIDI_H */
+diff --git a/drivers/usb/gadget/function/u_serial.c b/drivers/usb/gadget/function/u_serial.c
+index 2caccbb6e..d70f6dc9f 100644
+--- a/drivers/usb/gadget/function/u_serial.c
++++ b/drivers/usb/gadget/function/u_serial.c
+@@ -346,7 +346,7 @@ __acquires(&port->port_lock)
+ }
+ 
+ /*
+- * RX tasklet takes data out of the RX queue and hands it up to the TTY
++ * RX work takes data out of the RX queue and hands it up to the TTY
+  * layer until it refuses to take any more data (or is throttled back).
+  * Then it issues reads for any further data.
+  *
+@@ -709,7 +709,7 @@ static void gs_close(struct tty_struct *tty, struct file *file)
+ 
+ 	/* Iff we're disconnected, there can be no I/O in flight so it's
+ 	 * ok to free the circular buffer; else just scrub it.  And don't
+-	 * let the push tasklet fire again until we're re-opened.
++	 * let the push async work fire again until we're re-opened.
+ 	 */
+ 	if (gser == NULL)
+ 		kfifo_free(&port->port_write_buf);
+@@ -1200,7 +1200,7 @@ void gserial_free_line(unsigned char port_num)
+ 	struct gs_port	*port;
+ 
+ 	mutex_lock(&ports[port_num].lock);
+-	if (WARN_ON(!ports[port_num].port)) {
++	if (!ports[port_num].port) {
+ 		mutex_unlock(&ports[port_num].lock);
+ 		return;
+ 	}
+@@ -1447,51 +1447,53 @@ EXPORT_SYMBOL_GPL(gserial_resume);
+ 
+ static int userial_init(void)
+ {
++	struct tty_driver *driver;
+ 	unsigned			i;
+ 	int				status;
+ 
+-	gs_tty_driver = alloc_tty_driver(MAX_U_SERIAL_PORTS);
+-	if (!gs_tty_driver)
+-		return -ENOMEM;
++	driver = tty_alloc_driver(MAX_U_SERIAL_PORTS, TTY_DRIVER_REAL_RAW |
++			TTY_DRIVER_DYNAMIC_DEV);
++	if (IS_ERR(driver))
++		return PTR_ERR(driver);
+ 
+-	gs_tty_driver->driver_name = "g_serial";
+-	gs_tty_driver->name = "ttyGS";
++	driver->driver_name = "g_serial";
++	driver->name = "ttyGS";
+ 	/* uses dynamically assigned dev_t values */
+ 
+-	gs_tty_driver->type = TTY_DRIVER_TYPE_SERIAL;
+-	gs_tty_driver->subtype = SERIAL_TYPE_NORMAL;
+-	gs_tty_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
+-	gs_tty_driver->init_termios = tty_std_termios;
++	driver->type = TTY_DRIVER_TYPE_SERIAL;
++	driver->subtype = SERIAL_TYPE_NORMAL;
++	driver->init_termios = tty_std_termios;
+ 
+ 	/* 9600-8-N-1 ... matches defaults expected by "usbser.sys" on
+ 	 * MS-Windows.  Otherwise, most of these flags shouldn't affect
+ 	 * anything unless we were to actually hook up to a serial line.
+ 	 */
+-	gs_tty_driver->init_termios.c_cflag =
++	driver->init_termios.c_cflag =
+ 			B9600 | CS8 | CREAD | HUPCL | CLOCAL;
+-	gs_tty_driver->init_termios.c_ispeed = 9600;
+-	gs_tty_driver->init_termios.c_ospeed = 9600;
++	driver->init_termios.c_ispeed = 9600;
++	driver->init_termios.c_ospeed = 9600;
+ 
+-	tty_set_operations(gs_tty_driver, &gs_tty_ops);
++	tty_set_operations(driver, &gs_tty_ops);
+ 	for (i = 0; i < MAX_U_SERIAL_PORTS; i++)
+ 		mutex_init(&ports[i].lock);
+ 
+ 	/* export the driver ... */
+-	status = tty_register_driver(gs_tty_driver);
++	status = tty_register_driver(driver);
+ 	if (status) {
+ 		pr_err("%s: cannot register, err %d\n",
+ 				__func__, status);
+ 		goto fail;
+ 	}
+ 
++	gs_tty_driver = driver;
++
+ 	pr_debug("%s: registered %d ttyGS* device%s\n", __func__,
+ 			MAX_U_SERIAL_PORTS,
+ 			(MAX_U_SERIAL_PORTS == 1) ? "" : "s");
+ 
+ 	return status;
+ fail:
+-	put_tty_driver(gs_tty_driver);
+-	gs_tty_driver = NULL;
++	tty_driver_kref_put(driver);
+ 	return status;
+ }
+ module_init(userial_init);
+@@ -1499,7 +1501,7 @@ module_init(userial_init);
+ static void userial_cleanup(void)
+ {
+ 	tty_unregister_driver(gs_tty_driver);
+-	put_tty_driver(gs_tty_driver);
++	tty_driver_kref_put(gs_tty_driver);
+ 	gs_tty_driver = NULL;
+ }
+ module_exit(userial_cleanup);
+diff --git a/drivers/usb/gadget/function/u_uac1.h b/drivers/usb/gadget/function/u_uac1.h
+index 39c0e29e1..9979514ba 100644
+--- a/drivers/usb/gadget/function/u_uac1.h
++++ b/drivers/usb/gadget/function/u_uac1.h
+@@ -18,6 +18,13 @@
+ #define UAC1_DEF_PSRATE		48000
+ #define UAC1_DEF_PSSIZE		2
+ #define UAC1_DEF_REQ_NUM	2
++#define UAC1_DEF_INT_REQ_NUM	10
++
++#define UAC1_DEF_MUTE_PRESENT	1
++#define UAC1_DEF_VOLUME_PRESENT 1
++#define UAC1_DEF_MIN_DB		(-100*256)	/* -100 dB */
++#define UAC1_DEF_MAX_DB		0		/* 0 dB */
++#define UAC1_DEF_RES_DB		(1*256)	/* 1 dB */
+ 
+ 
+ struct f_uac1_opts {
+@@ -28,6 +35,19 @@ struct f_uac1_opts {
+ 	int				p_chmask;
+ 	int				p_srate;
+ 	int				p_ssize;
++
++	bool			p_mute_present;
++	bool			p_volume_present;
++	s16				p_volume_min;
++	s16				p_volume_max;
++	s16				p_volume_res;
++
++	bool			c_mute_present;
++	bool			c_volume_present;
++	s16				c_volume_min;
++	s16				c_volume_max;
++	s16				c_volume_res;
++
+ 	int				req_number;
+ 	unsigned			bound:1;
+ 
+@@ -35,4 +55,4 @@ struct f_uac1_opts {
+ 	int				refcnt;
+ };
+ 
+-#endif /* __U_UAC1_H */
++#endif /* __U_UAC1_H */
+\ No newline at end of file
+diff --git a/drivers/usb/gadget/function/u_uac2.h b/drivers/usb/gadget/function/u_uac2.h
+index b50357111..569897f87 100644
+--- a/drivers/usb/gadget/function/u_uac2.h
++++ b/drivers/usb/gadget/function/u_uac2.h
+@@ -21,7 +21,17 @@
+ #define UAC2_DEF_CCHMASK 0x3
+ #define UAC2_DEF_CSRATE 64000
+ #define UAC2_DEF_CSSIZE 2
++#define UAC2_DEF_CSYNC		USB_ENDPOINT_SYNC_ASYNC
++
++#define UAC2_DEF_MUTE_PRESENT	1
++#define UAC2_DEF_VOLUME_PRESENT 1
++#define UAC2_DEF_MIN_DB		(-100*256)	/* -100 dB */
++#define UAC2_DEF_MAX_DB		0		/* 0 dB */
++#define UAC2_DEF_RES_DB		(1*256)		/* 1 dB */
++
+ #define UAC2_DEF_REQ_NUM 2
++#define UAC2_DEF_FB_MAX 5
++#define UAC2_DEF_INT_REQ_NUM	10
+ 
+ struct f_uac2_opts {
+ 	struct usb_function_instance	func_inst;
+@@ -31,11 +41,26 @@ struct f_uac2_opts {
+ 	int				c_chmask;
+ 	int				c_srate;
+ 	int				c_ssize;
++	int				c_sync;
++
++	bool			p_mute_present;
++	bool			p_volume_present;
++	s16				p_volume_min;
++	s16				p_volume_max;
++	s16				p_volume_res;
++
++	bool			c_mute_present;
++	bool			c_volume_present;
++	s16				c_volume_min;
++	s16				c_volume_max;
++	s16				c_volume_res;
++
+ 	int				req_number;
+-	bool				bound;
++	int				fb_max;
++	bool			bound;
+ 
+ 	struct mutex			lock;
+ 	int				refcnt;
+ };
+ 
+-#endif
++#endif
+\ No newline at end of file
+diff --git a/drivers/usb/gadget/function/uvc.h b/drivers/usb/gadget/function/uvc.h
+index 6c4fc4913..f3e9c764f 100644
+--- a/drivers/usb/gadget/function/uvc.h
++++ b/drivers/usb/gadget/function/uvc.h
+@@ -66,13 +66,19 @@ extern unsigned int uvc_gadget_trace_param;
+  * Driver specific constants
+  */
+ 
+-#define UVC_NUM_REQUESTS			4
+ #define UVC_MAX_REQUEST_SIZE			64
+ #define UVC_MAX_EVENTS				4
+ 
+ /* ------------------------------------------------------------------------
+  * Structures
+  */
++struct uvc_request {
++   struct usb_request *req;
++   u8 *req_buffer;
++   struct uvc_video *video;
++   struct sg_table sgt;
++   u8 header[2];
++};
+ 
+ struct uvc_video {
+ 	struct uvc_device *uvc;
+@@ -88,13 +94,16 @@ struct uvc_video {
+ 	unsigned int imagesize;
+ 	struct mutex mutex;	/* protects frame parameters */
+ 
++    unsigned int uvc_num_requests;
++
+ 	/* Requests */
+ 	unsigned int req_size;
+-	struct usb_request *req[UVC_NUM_REQUESTS];
+-	__u8 *req_buffer[UVC_NUM_REQUESTS];
++    struct uvc_request *ureq;
+ 	struct list_head req_free;
+ 	spinlock_t req_lock;
+ 
++    unsigned int req_int_count;
++
+ 	void (*encode) (struct usb_request *req, struct uvc_video *video,
+ 			struct uvc_buffer *buf);
+ 
+@@ -118,7 +127,7 @@ struct uvc_device {
+ 	enum uvc_state state;
+ 	struct usb_function func;
+ 	struct uvc_video video;
+-	bool func_connected;
++    bool func_connected;
+ 	wait_queue_head_t func_connected_queue;
+ 
+ 	/* Descriptors */
+diff --git a/drivers/usb/gadget/function/uvc_configfs.c b/drivers/usb/gadget/function/uvc_configfs.c
+index 00fb58e50..77d64031a 100644
+--- a/drivers/usb/gadget/function/uvc_configfs.c
++++ b/drivers/usb/gadget/function/uvc_configfs.c
+@@ -231,7 +231,7 @@ static struct config_item *uvcg_control_header_make(struct config_group *group,
+ 	h->desc.bLength			= UVC_DT_HEADER_SIZE(1);
+ 	h->desc.bDescriptorType		= USB_DT_CS_INTERFACE;
+ 	h->desc.bDescriptorSubType	= UVC_VC_HEADER;
+-	h->desc.bcdUVC			= cpu_to_le16(0x0100);
++	h->desc.bcdUVC			= cpu_to_le16(0x0110);
+ 	h->desc.dwClockFrequency	= cpu_to_le32(48000000);
+ 
+ 	config_item_init_type_name(&h->item, name, &uvcg_control_header_type);
+@@ -914,8 +914,6 @@ static int uvcg_streaming_header_allow_link(struct config_item *src,
+ 
+ 	target_fmt = container_of(to_config_group(target), struct uvcg_format,
+ 				  group);
+-	if (!target_fmt)
+-		goto out;
+ 
+ 	uvcg_format_set_indices(to_config_group(target));
+ 
+@@ -955,8 +953,6 @@ static void uvcg_streaming_header_drop_link(struct config_item *src,
+ 	mutex_lock(&opts->lock);
+ 	target_fmt = container_of(to_config_group(target), struct uvcg_format,
+ 				  group);
+-	if (!target_fmt)
+-		goto out;
+ 
+ 	list_for_each_entry_safe(format_ptr, tmp, &src_hdr->formats, entry)
+ 		if (format_ptr->fmt == target_fmt) {
+@@ -968,7 +964,6 @@ static void uvcg_streaming_header_drop_link(struct config_item *src,
+ 
+ 	--target_fmt->linked;
+ 
+-out:
+ 	mutex_unlock(&opts->lock);
+ 	mutex_unlock(su_mutex);
+ }
+diff --git a/drivers/usb/gadget/function/uvc_queue.c b/drivers/usb/gadget/function/uvc_queue.c
+index cab1e3046..cd99d6c4a 100644
+--- a/drivers/usb/gadget/function/uvc_queue.c
++++ b/drivers/usb/gadget/function/uvc_queue.c
+@@ -17,6 +17,7 @@
+ #include <linux/wait.h>
+ 
+ #include <media/v4l2-common.h>
++#include <media/videobuf2-dma-sg.h>
+ #include <media/videobuf2-vmalloc.h>
+ 
+ #include "uvc.h"
+@@ -43,6 +44,7 @@ static int uvc_queue_setup(struct vb2_queue *vq,
+ {
+ 	struct uvc_video_queue *queue = vb2_get_drv_priv(vq);
+ 	struct uvc_video *video = container_of(queue, struct uvc_video, queue);
++	struct usb_composite_dev *cdev = video->uvc->func.config->cdev;
+ 
+ 	if (*nbuffers > UVC_MAX_VIDEO_BUFFERS)
+ 		*nbuffers = UVC_MAX_VIDEO_BUFFERS;
+@@ -70,7 +72,12 @@ static int uvc_buffer_prepare(struct vb2_buffer *vb)
+ 		return -ENODEV;
+ 
+ 	buf->state = UVC_BUF_STATE_QUEUED;
+-	buf->mem = vb2_plane_vaddr(vb, 0);
++	if (queue->use_sg) {
++		buf->sgt = vb2_dma_sg_plane_desc(vb, 0);
++		buf->sg = buf->sgt->sgl;
++	} else {
++		buf->mem = vb2_plane_vaddr(vb, 0);
++	}
+ 	buf->length = vb2_plane_size(vb, 0);
+ 	if (vb->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ 		buf->bytesused = 0;
+@@ -110,9 +117,11 @@ static const struct vb2_ops uvc_queue_qops = {
+ 	.wait_finish = vb2_ops_wait_finish,
+ };
+ 
+-int uvcg_queue_init(struct uvc_video_queue *queue, enum v4l2_buf_type type,
++int uvcg_queue_init(struct uvc_video_queue *queue, struct device *dev, enum v4l2_buf_type type,
+ 		    struct mutex *lock)
+ {
++	struct uvc_video *video = container_of(queue, struct uvc_video, queue);
++	struct usb_composite_dev *cdev = video->uvc->func.config->cdev;
+ 	int ret;
+ 
+ 	queue->queue.type = type;
+@@ -121,9 +130,17 @@ int uvcg_queue_init(struct uvc_video_queue *queue, enum v4l2_buf_type type,
+ 	queue->queue.buf_struct_size = sizeof(struct uvc_buffer);
+ 	queue->queue.ops = &uvc_queue_qops;
+ 	queue->queue.lock = lock;
+-	queue->queue.mem_ops = &vb2_vmalloc_memops;
++	if (cdev->gadget->sg_supported) {
++		queue->queue.mem_ops = &vb2_dma_sg_memops;
++		queue->use_sg = 1;
++	} else {
++		queue->queue.mem_ops = &vb2_vmalloc_memops;
++	}
++
+ 	queue->queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC
+ 				     | V4L2_BUF_FLAG_TSTAMP_SRC_EOF;
++	queue->queue.dev = dev;
++
+ 	ret = vb2_queue_init(&queue->queue);
+ 	if (ret)
+ 		return ret;
+@@ -347,4 +364,3 @@ struct uvc_buffer *uvcg_queue_head(struct uvc_video_queue *queue)
+ 
+ 	return buf;
+ }
+-
+diff --git a/drivers/usb/gadget/function/uvc_queue.h b/drivers/usb/gadget/function/uvc_queue.h
+index 2f0fff769..13275e932 100644
+--- a/drivers/usb/gadget/function/uvc_queue.h
++++ b/drivers/usb/gadget/function/uvc_queue.h
+@@ -34,6 +34,9 @@ struct uvc_buffer {
+ 
+ 	enum uvc_buffer_state state;
+ 	void *mem;
++	struct sg_table *sgt;
++	struct scatterlist *sg;
++	unsigned int offset;
+ 	unsigned int length;
+ 	unsigned int bytesused;
+ };
+@@ -50,6 +53,8 @@ struct uvc_video_queue {
+ 
+ 	unsigned int buf_used;
+ 
++	bool use_sg;
++
+ 	spinlock_t irqlock;	/* Protects flags and irqqueue */
+ 	struct list_head irqqueue;
+ };
+@@ -59,7 +64,7 @@ static inline int uvc_queue_streaming(struct uvc_video_queue *queue)
+ 	return vb2_is_streaming(&queue->queue);
+ }
+ 
+-int uvcg_queue_init(struct uvc_video_queue *queue, enum v4l2_buf_type type,
++int uvcg_queue_init(struct uvc_video_queue *queue, struct device *dev, enum v4l2_buf_type type,
+ 		    struct mutex *lock);
+ 
+ void uvcg_free_buffers(struct uvc_video_queue *queue);
+@@ -94,4 +99,3 @@ struct uvc_buffer *uvcg_queue_next_buffer(struct uvc_video_queue *queue,
+ struct uvc_buffer *uvcg_queue_head(struct uvc_video_queue *queue);
+ 
+ #endif /* _UVC_QUEUE_H_ */
+-
+diff --git a/drivers/usb/gadget/function/uvc_v4l2.c b/drivers/usb/gadget/function/uvc_v4l2.c
+index 65abd55ce..d036d11dd 100644
+--- a/drivers/usb/gadget/function/uvc_v4l2.c
++++ b/drivers/usb/gadget/function/uvc_v4l2.c
+@@ -227,56 +227,16 @@ static int
+ uvc_v4l2_subscribe_event(struct v4l2_fh *fh,
+ 			 const struct v4l2_event_subscription *sub)
+ {
+-	struct uvc_device *uvc = video_get_drvdata(fh->vdev);
+-	struct uvc_file_handle *handle = to_uvc_file_handle(fh);
+-	int ret;
+-
+ 	if (sub->type < UVC_EVENT_FIRST || sub->type > UVC_EVENT_LAST)
+ 		return -EINVAL;
+-
+-	if (sub->type == UVC_EVENT_SETUP && uvc->func_connected)
+-		return -EBUSY;
+-
+-	ret = v4l2_event_subscribe(fh, sub, 2, NULL);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (sub->type == UVC_EVENT_SETUP) {
+-		uvc->func_connected = true;
+-		handle->is_uvc_app_handle = true;
+-		uvc_function_connect(uvc);
+-	}
+-
+-	return 0;
+-}
+-
+-static void uvc_v4l2_disable(struct uvc_device *uvc)
+-{
+-	uvc_function_disconnect(uvc);
+-	uvcg_video_enable(&uvc->video, 0);
+-	uvcg_free_buffers(&uvc->video.queue);
+-	uvc->func_connected = false;
+-	wake_up_interruptible(&uvc->func_connected_queue);
++	return v4l2_event_subscribe(fh, sub, 2, NULL);
+ }
+ 
+ static int
+ uvc_v4l2_unsubscribe_event(struct v4l2_fh *fh,
+ 			   const struct v4l2_event_subscription *sub)
+ {
+-	struct uvc_device *uvc = video_get_drvdata(fh->vdev);
+-	struct uvc_file_handle *handle = to_uvc_file_handle(fh);
+-	int ret;
+-
+-	ret = v4l2_event_unsubscribe(fh, sub);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (sub->type == UVC_EVENT_SETUP && handle->is_uvc_app_handle) {
+-		uvc_v4l2_disable(uvc);
+-		handle->is_uvc_app_handle = false;
+-	}
+-
+-	return 0;
++	return v4l2_event_unsubscribe(fh, sub);
+ }
+ 
+ static long
+@@ -331,6 +291,7 @@ uvc_v4l2_open(struct file *file)
+ 	handle->device = &uvc->video;
+ 	file->private_data = &handle->vfh;
+ 
++	uvc_function_connect(uvc);
+ 	return 0;
+ }
+ 
+@@ -342,9 +303,11 @@ uvc_v4l2_release(struct file *file)
+ 	struct uvc_file_handle *handle = to_uvc_file_handle(file->private_data);
+ 	struct uvc_video *video = handle->device;
+ 
++	uvc_function_disconnect(uvc);
++
+ 	mutex_lock(&video->mutex);
+-	if (handle->is_uvc_app_handle)
+-		uvc_v4l2_disable(uvc);
++	uvcg_video_enable(video, 0);
++	uvcg_free_buffers(&video->queue);
+ 	mutex_unlock(&video->mutex);
+ 
+ 	file->private_data = NULL;
+diff --git a/drivers/usb/gadget/function/uvc_video.c b/drivers/usb/gadget/function/uvc_video.c
+index 633e23d58..db273e9a0 100644
+--- a/drivers/usb/gadget/function/uvc_video.c
++++ b/drivers/usb/gadget/function/uvc_video.c
+@@ -27,10 +27,10 @@ static int
+ uvc_video_encode_header(struct uvc_video *video, struct uvc_buffer *buf,
+ 		u8 *data, int len)
+ {
+-	data[0] = 2;
++	data[0] = UVCG_REQUEST_HEADER_LEN;
+ 	data[1] = UVC_STREAM_EOH | video->fid;
+ 
+-	if (buf->bytesused - video->queue.buf_used <= len - 2)
++	if (buf->bytesused - video->queue.buf_used <= len - UVCG_REQUEST_HEADER_LEN)
+ 		data[1] |= UVC_STREAM_EOF;
+ 
+ 	return 2;
+@@ -94,6 +94,71 @@ uvc_video_encode_bulk(struct usb_request *req, struct uvc_video *video,
+ 		video->payload_size = 0;
+ }
+ 
++static void
++uvc_video_encode_isoc_sg(struct usb_request *req, struct uvc_video *video,
++		struct uvc_buffer *buf)
++{
++	unsigned int pending = buf->bytesused - video->queue.buf_used;
++	struct uvc_request *ureq = req->context;
++	struct scatterlist *sg, *iter;
++	unsigned int len = video->req_size;
++	unsigned int sg_left, part = 0;
++	unsigned int i;
++	int ret;
++
++	sg = ureq->sgt.sgl;
++	sg_init_table(sg, ureq->sgt.nents);
++
++	/* Init the header. */
++	ret = uvc_video_encode_header(video, buf, ureq->header,
++				      video->req_size);
++	sg_set_buf(sg, ureq->header, UVCG_REQUEST_HEADER_LEN);
++	len -= ret;
++
++	if (pending <= len)
++		len = pending;
++
++	req->length = (len == pending) ?
++		len + UVCG_REQUEST_HEADER_LEN : video->req_size;
++
++	/* Init the pending sgs with payload */
++	sg = sg_next(sg);
++
++	for_each_sg(sg, iter, ureq->sgt.nents - 1, i) {
++		if (!len || !buf->sg)
++			break;
++
++		sg_left = sg_dma_len(buf->sg) - buf->offset;
++		part = min_t(unsigned int, len, sg_left);
++
++		sg_set_page(iter, sg_page(buf->sg), part, buf->offset);
++
++		if (part == sg_left) {
++			buf->offset = 0;
++			buf->sg = sg_next(buf->sg);
++		} else {
++			buf->offset += part;
++		}
++		len -= part;
++	}
++
++	/* Assign the video data with header. */
++	req->buf = NULL;
++	req->sg	= ureq->sgt.sgl;
++	req->num_sgs = i + 1;
++
++	req->length -= len;
++	video->queue.buf_used += req->length - UVCG_REQUEST_HEADER_LEN;
++
++	if (buf->bytesused == video->queue.buf_used || !buf->sg) {
++		video->queue.buf_used = 0;
++		buf->state = UVC_BUF_STATE_DONE;
++		buf->offset = 0;
++		uvcg_queue_next_buffer(&video->queue, buf);
++		video->fid ^= UVC_STREAM_FID;
++	}
++}
++
+ static void
+ uvc_video_encode_isoc(struct usb_request *req, struct uvc_video *video,
+ 		struct uvc_buffer *buf)
+@@ -145,7 +210,8 @@ static int uvcg_video_ep_queue(struct uvc_video *video, struct usb_request *req)
+ static void
+ uvc_video_complete(struct usb_ep *ep, struct usb_request *req)
+ {
+-	struct uvc_video *video = req->context;
++	struct uvc_request *ureq = req->context;
++	struct uvc_video *video = ureq->video;
+ 	struct uvc_video_queue *queue = &video->queue;
+ 	unsigned long flags;
+ 
+@@ -177,16 +243,23 @@ uvc_video_free_requests(struct uvc_video *video)
+ {
+ 	unsigned int i;
+ 
+-	for (i = 0; i < UVC_NUM_REQUESTS; ++i) {
+-		if (video->req[i]) {
+-			usb_ep_free_request(video->ep, video->req[i]);
+-			video->req[i] = NULL;
+-		}
++	if (video->ureq) {
++		for (i = 0; i < video->uvc_num_requests; ++i) {
++			sg_free_table(&video->ureq[i].sgt);
++
++			if (video->ureq[i].req) {
++				usb_ep_free_request(video->ep, video->ureq[i].req);
++				video->ureq[i].req = NULL;
++			}
+ 
+-		if (video->req_buffer[i]) {
+-			kfree(video->req_buffer[i]);
+-			video->req_buffer[i] = NULL;
++			if (video->ureq[i].req_buffer) {
++				kfree(video->ureq[i].req_buffer);
++				video->ureq[i].req_buffer = NULL;
++			}
+ 		}
++
++		kfree(video->ureq);
++		video->ureq = NULL;
+ 	}
+ 
+ 	INIT_LIST_HEAD(&video->req_free);
+@@ -207,21 +280,30 @@ uvc_video_alloc_requests(struct uvc_video *video)
+ 		 * max_t(unsigned int, video->ep->maxburst, 1)
+ 		 * (video->ep->mult);
+ 
+-	for (i = 0; i < UVC_NUM_REQUESTS; ++i) {
+-		video->req_buffer[i] = kmalloc(req_size, GFP_KERNEL);
+-		if (video->req_buffer[i] == NULL)
+-			goto error;
++	video->ureq = kcalloc(video->uvc_num_requests, sizeof(struct uvc_request), GFP_KERNEL);
++	if (video->ureq == NULL)
++		return -ENOMEM;
+ 
+-		video->req[i] = usb_ep_alloc_request(video->ep, GFP_KERNEL);
+-		if (video->req[i] == NULL)
++	for (i = 0; i < video->uvc_num_requests; ++i) {
++		video->ureq[i].req_buffer = kmalloc(req_size, GFP_KERNEL);
++		if (video->ureq[i].req_buffer == NULL)
+ 			goto error;
+ 
+-		video->req[i]->buf = video->req_buffer[i];
+-		video->req[i]->length = 0;
+-		video->req[i]->complete = uvc_video_complete;
+-		video->req[i]->context = video;
++		video->ureq[i].req = usb_ep_alloc_request(video->ep, GFP_KERNEL);
++		if (video->ureq[i].req == NULL)
++			goto error;
+ 
+-		list_add_tail(&video->req[i]->list, &video->req_free);
++		video->ureq[i].req->buf = video->ureq[i].req_buffer;
++		video->ureq[i].req->length = 0;
++		video->ureq[i].req->complete = uvc_video_complete;
++		video->ureq[i].req->context = &video->ureq[i];
++		video->ureq[i].video = video;
++
++		list_add_tail(&video->ureq[i].req->list, &video->req_free);
++		/* req_size/PAGE_SIZE + 1 for overruns and + 1 for header */
++		sg_alloc_table(&video->ureq[i].sgt,
++			       DIV_ROUND_UP(req_size - 2, PAGE_SIZE) + 2,
++			       GFP_KERNEL);
+ 	}
+ 
+ 	video->req_size = req_size;
+@@ -278,6 +360,19 @@ static void uvcg_video_pump(struct work_struct *work)
+ 
+ 		video->encode(req, video, buf);
+ 
++		/* With usb3 we have more requests. This will decrease the
++		 * interrupt load to a quarter but also catches the corner
++		 * cases, which needs to be handled */
++		if (list_empty(&video->req_free) ||
++		    buf->state == UVC_BUF_STATE_DONE ||
++		    !(video->req_int_count %
++		       DIV_ROUND_UP(video->uvc_num_requests, 4))) {
++			video->req_int_count = 0;
++			req->no_interrupt = 0;
++		} else {
++			req->no_interrupt = 1;
++		}
++
+ 		/* Queue the USB request */
+ 		ret = uvcg_video_ep_queue(video, req);
+ 		spin_unlock_irqrestore(&queue->irqlock, flags);
+@@ -286,6 +381,7 @@ static void uvcg_video_pump(struct work_struct *work)
+ 			uvcg_queue_cancel(queue, 0);
+ 			break;
+ 		}
++		video->req_int_count++;
+ 	}
+ 
+ 	spin_lock_irqsave(&video->req_lock, flags);
+@@ -312,9 +408,9 @@ int uvcg_video_enable(struct uvc_video *video, int enable)
+ 		cancel_work_sync(&video->pump);
+ 		uvcg_queue_cancel(&video->queue, 0);
+ 
+-		for (i = 0; i < UVC_NUM_REQUESTS; ++i)
+-			if (video->req[i])
+-				usb_ep_dequeue(video->ep, video->req[i]);
++		for (i = 0; i < video->uvc_num_requests; ++i)
++			if (video->ureq && video->ureq[i].req)
++				usb_ep_dequeue(video->ep, video->ureq[i].req);
+ 
+ 		uvc_video_free_requests(video);
+ 		uvcg_queue_enable(&video->queue, 0);
+@@ -331,7 +427,10 @@ int uvcg_video_enable(struct uvc_video *video, int enable)
+ 		video->encode = uvc_video_encode_bulk;
+ 		video->payload_size = 0;
+ 	} else
+-		video->encode = uvc_video_encode_isoc;
++		video->encode = video->queue.use_sg ?
++			uvc_video_encode_isoc_sg : uvc_video_encode_isoc;
++
++	video->req_int_count = 0;
+ 
+ 	schedule_work(&video->pump);
+ 
+@@ -355,8 +454,7 @@ int uvcg_video_init(struct uvc_video *video, struct uvc_device *uvc)
+ 	video->imagesize = 320 * 240 * 2;
+ 
+ 	/* Initialize the video buffers queue. */
+-	uvcg_queue_init(&video->queue, V4L2_BUF_TYPE_VIDEO_OUTPUT,
+-			&video->mutex);
++	uvcg_queue_init(&video->queue, uvc->v4l2_dev.dev->parent,
++			V4L2_BUF_TYPE_VIDEO_OUTPUT, &video->mutex);
+ 	return 0;
+ }
+-
+diff --git a/drivers/usb/gadget/function/uvc_video.h b/drivers/usb/gadget/function/uvc_video.h
+index 03adeefa3..9bf19475f 100644
+--- a/drivers/usb/gadget/function/uvc_video.h
++++ b/drivers/usb/gadget/function/uvc_video.h
+@@ -12,6 +12,8 @@
+ #ifndef __UVC_VIDEO_H__
+ #define __UVC_VIDEO_H__
+ 
++#define UVCG_REQUEST_HEADER_LEN			2
++
+ struct uvc_video;
+ 
+ int uvcg_video_enable(struct uvc_video *video, int enable);
+diff --git a/drivers/usb/gadget/legacy/Kconfig b/drivers/usb/gadget/legacy/Kconfig
+index f02c38b32..de6668e58 100644
+--- a/drivers/usb/gadget/legacy/Kconfig
++++ b/drivers/usb/gadget/legacy/Kconfig
+@@ -502,6 +502,7 @@ config USB_G_WEBCAM
+ 	tristate "USB Webcam Gadget"
+ 	depends on VIDEO_V4L2
+ 	select USB_LIBCOMPOSITE
++	select VIDEOBUF2_DMA_SG
+ 	select VIDEOBUF2_VMALLOC
+ 	select USB_F_UVC
+ 	help
+@@ -515,10 +516,15 @@ config USB_G_WEBCAM
+ config USB_RAW_GADGET
+ 	tristate "USB Raw Gadget"
+ 	help
+-	  USB Raw Gadget is a kernel module that provides a userspace interface
+-	  for the USB Gadget subsystem. Essentially it allows to emulate USB
+-	  devices from userspace. See Documentation/usb/raw-gadget.rst for
+-	  details.
++	  USB Raw Gadget is a gadget driver that gives userspace low-level
++	  control over the gadget's communication process.
++
++	  Like any other gadget driver, Raw Gadget implements USB devices via
++	  the USB gadget API. Unlike most gadget drivers, Raw Gadget does not
++	  implement any concrete USB functions itself but requires userspace
++	  to do that.
++
++	  See Documentation/usb/raw-gadget.rst for details.
+ 
+ 	  Say "y" to link the driver statically, or "m" to build a
+ 	  dynamically linked module called "raw_gadget".
+diff --git a/drivers/usb/gadget/legacy/dbgp.c b/drivers/usb/gadget/legacy/dbgp.c
+index 6bcbad382..e1d566c99 100644
+--- a/drivers/usb/gadget/legacy/dbgp.c
++++ b/drivers/usb/gadget/legacy/dbgp.c
+@@ -137,7 +137,7 @@ static int dbgp_enable_ep_req(struct usb_ep *ep)
+ 		goto fail_1;
+ 	}
+ 
+-	req->buf = kzalloc(DBGP_REQ_LEN, GFP_KERNEL);
++	req->buf = kmalloc(DBGP_REQ_LEN, GFP_KERNEL);
+ 	if (!req->buf) {
+ 		err = -ENOMEM;
+ 		stp = 2;
+@@ -345,19 +345,6 @@ static int dbgp_setup(struct usb_gadget *gadget,
+ 	void *data = NULL;
+ 	u16 len = 0;
+ 
+-	if (length > DBGP_REQ_LEN) {
+-		if (ctrl->bRequestType & USB_DIR_IN) {
+-			/* Cast away the const, we are going to overwrite on purpose. */
+-			__le16 *temp = (__le16 *)&ctrl->wLength;
+-
+-			*temp = cpu_to_le16(DBGP_REQ_LEN);
+-			length = DBGP_REQ_LEN;
+-		} else {
+-			return err;
+-		}
+-	}
+-
+-
+ 	if (request == USB_REQ_GET_DESCRIPTOR) {
+ 		switch (value>>8) {
+ 		case USB_DT_DEVICE:
+diff --git a/drivers/usb/gadget/legacy/hid.c b/drivers/usb/gadget/legacy/hid.c
+index 3912cc805..5b27d2894 100644
+--- a/drivers/usb/gadget/legacy/hid.c
++++ b/drivers/usb/gadget/legacy/hid.c
+@@ -99,10 +99,8 @@ static int do_config(struct usb_configuration *c)
+ 
+ 	list_for_each_entry(e, &hidg_func_list, node) {
+ 		e->f = usb_get_function(e->fi);
+-		if (IS_ERR(e->f)) {
+-			status = PTR_ERR(e->f);
++		if (IS_ERR(e->f))
+ 			goto put;
+-		}
+ 		status = usb_add_function(c, e->f);
+ 		if (status < 0) {
+ 			usb_put_function(e->f);
+diff --git a/drivers/usb/gadget/legacy/inode.c b/drivers/usb/gadget/legacy/inode.c
+index 454860d52..cd8e27379 100644
+--- a/drivers/usb/gadget/legacy/inode.c
++++ b/drivers/usb/gadget/legacy/inode.c
+@@ -110,8 +110,6 @@ enum ep0_state {
+ /* enough for the whole queue: most events invalidate others */
+ #define	N_EVENT			5
+ 
+-#define RBUF_SIZE		256
+-
+ struct dev_data {
+ 	spinlock_t			lock;
+ 	refcount_t			count;
+@@ -146,7 +144,7 @@ struct dev_data {
+ 	struct dentry			*dentry;
+ 
+ 	/* except this scratch i/o buffer for ep0 */
+-	u8				rbuf[RBUF_SIZE];
++	u8				rbuf [256];
+ };
+ 
+ static inline void get_dev (struct dev_data *data)
+@@ -500,7 +498,8 @@ static void ep_aio_complete(struct usb_ep *ep, struct usb_request *req)
+ 		iocb->private = NULL;
+ 		/* aio_complete() reports bytes-transferred _and_ faults */
+ 
+-		iocb->ki_complete(iocb, req->actual ? req->actual : req->status,
++		iocb->ki_complete(iocb,
++				req->actual ? req->actual : (long)req->status,
+ 				req->status);
+ 	} else {
+ 		/* ep_copy_to_user() won't report both; we hide some faults */
+@@ -1335,18 +1334,6 @@ gadgetfs_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
+ 	u16				w_value = le16_to_cpu(ctrl->wValue);
+ 	u16				w_length = le16_to_cpu(ctrl->wLength);
+ 
+-	if (w_length > RBUF_SIZE) {
+-		if (ctrl->bRequestType & USB_DIR_IN) {
+-			/* Cast away the const, we are going to overwrite on purpose. */
+-			__le16 *temp = (__le16 *)&ctrl->wLength;
+-
+-			*temp = cpu_to_le16(RBUF_SIZE);
+-			w_length = RBUF_SIZE;
+-		} else {
+-			return value;
+-		}
+-	}
+-
+ 	spin_lock (&dev->lock);
+ 	dev->setup_abort = 0;
+ 	if (dev->state == STATE_DEV_UNCONNECTED) {
+@@ -1828,9 +1815,8 @@ dev_config (struct file *fd, const char __user *buf, size_t len, loff_t *ptr)
+ 	spin_lock_irq (&dev->lock);
+ 	value = -EINVAL;
+ 	if (dev->buf) {
+-		spin_unlock_irq(&dev->lock);
+ 		kfree(kbuf);
+-		return value;
++		goto fail;
+ 	}
+ 	dev->buf = kbuf;
+ 
+@@ -1877,8 +1863,8 @@ dev_config (struct file *fd, const char __user *buf, size_t len, loff_t *ptr)
+ 
+ 	value = usb_gadget_probe_driver(&gadgetfs_driver);
+ 	if (value != 0) {
+-		spin_lock_irq(&dev->lock);
+-		goto fail;
++		kfree (dev->buf);
++		dev->buf = NULL;
+ 	} else {
+ 		/* at this point "good" hardware has for the first time
+ 		 * let the USB the host see us.  alternatively, if users
+@@ -1895,9 +1881,6 @@ dev_config (struct file *fd, const char __user *buf, size_t len, loff_t *ptr)
+ 	return value;
+ 
+ fail:
+-	dev->config = NULL;
+-	dev->hs_config = NULL;
+-	dev->dev = NULL;
+ 	spin_unlock_irq (&dev->lock);
+ 	pr_debug ("%s: %s fail %zd, %p\n", shortname, __func__, value, dev);
+ 	kfree (dev->buf);
+diff --git a/drivers/usb/gadget/legacy/mass_storage.c b/drivers/usb/gadget/legacy/mass_storage.c
+index 9ed22c5fb..ac1741126 100644
+--- a/drivers/usb/gadget/legacy/mass_storage.c
++++ b/drivers/usb/gadget/legacy/mass_storage.c
+@@ -175,8 +175,10 @@ static int msg_bind(struct usb_composite_dev *cdev)
+ 		struct usb_descriptor_header *usb_desc;
+ 
+ 		usb_desc = usb_otg_descriptor_alloc(cdev->gadget);
+-		if (!usb_desc)
++		if (!usb_desc) {
++			status = -ENOMEM;
+ 			goto fail_string_ids;
++		}
+ 		usb_otg_descriptor_init(cdev->gadget, usb_desc);
+ 		otg_desc[0] = usb_desc;
+ 		otg_desc[1] = NULL;
+diff --git a/drivers/usb/gadget/legacy/multi.c b/drivers/usb/gadget/legacy/multi.c
+index ec9749845..8db5c91ae 100644
+--- a/drivers/usb/gadget/legacy/multi.c
++++ b/drivers/usb/gadget/legacy/multi.c
+@@ -182,7 +182,7 @@ static int rndis_do_config(struct usb_configuration *c)
+ 	return ret;
+ }
+ 
+-static __ref int rndis_config_register(struct usb_composite_dev *cdev)
++static int rndis_config_register(struct usb_composite_dev *cdev)
+ {
+ 	static struct usb_configuration config = {
+ 		.bConfigurationValue	= MULTI_RNDIS_CONFIG_NUM,
+@@ -197,7 +197,7 @@ static __ref int rndis_config_register(struct usb_composite_dev *cdev)
+ 
+ #else
+ 
+-static __ref int rndis_config_register(struct usb_composite_dev *cdev)
++static int rndis_config_register(struct usb_composite_dev *cdev)
+ {
+ 	return 0;
+ }
+@@ -265,7 +265,7 @@ static int cdc_do_config(struct usb_configuration *c)
+ 	return ret;
+ }
+ 
+-static __ref int cdc_config_register(struct usb_composite_dev *cdev)
++static int cdc_config_register(struct usb_composite_dev *cdev)
+ {
+ 	static struct usb_configuration config = {
+ 		.bConfigurationValue	= MULTI_CDC_CONFIG_NUM,
+@@ -280,7 +280,7 @@ static __ref int cdc_config_register(struct usb_composite_dev *cdev)
+ 
+ #else
+ 
+-static __ref int cdc_config_register(struct usb_composite_dev *cdev)
++static int cdc_config_register(struct usb_composite_dev *cdev)
+ {
+ 	return 0;
+ }
+@@ -291,7 +291,7 @@ static __ref int cdc_config_register(struct usb_composite_dev *cdev)
+ 
+ /****************************** Gadget Bind ******************************/
+ 
+-static int __ref multi_bind(struct usb_composite_dev *cdev)
++static int multi_bind(struct usb_composite_dev *cdev)
+ {
+ 	struct usb_gadget *gadget = cdev->gadget;
+ #ifdef CONFIG_USB_G_MULTI_CDC
+@@ -399,8 +399,10 @@ static int __ref multi_bind(struct usb_composite_dev *cdev)
+ 		struct usb_descriptor_header *usb_desc;
+ 
+ 		usb_desc = usb_otg_descriptor_alloc(gadget);
+-		if (!usb_desc)
++		if (!usb_desc) {
++			status = -ENOMEM;
+ 			goto fail_string_ids;
++		}
+ 		usb_otg_descriptor_init(gadget, usb_desc);
+ 		otg_desc[0] = usb_desc;
+ 		otg_desc[1] = NULL;
+diff --git a/drivers/usb/gadget/legacy/printer.c b/drivers/usb/gadget/legacy/printer.c
+index 2cd389575..ed762ba9b 100644
+--- a/drivers/usb/gadget/legacy/printer.c
++++ b/drivers/usb/gadget/legacy/printer.c
+@@ -50,6 +50,7 @@ MODULE_PARM_DESC(iPNPstring, "MFG:linux;MDL:g_printer;CLS:PRINTER;SN:1;");
+ /* Number of requests to allocate per endpoint, not used for ep0. */
+ static unsigned qlen = 10;
+ module_param(qlen, uint, S_IRUGO|S_IWUSR);
++MODULE_PARM_DESC(qlen, "The number of 8k buffers to use per endpoint");
+ 
+ #define QLEN	qlen
+ 
+diff --git a/drivers/usb/gadget/legacy/raw_gadget.c b/drivers/usb/gadget/legacy/raw_gadget.c
+index b496ca937..2869bda64 100644
+--- a/drivers/usb/gadget/legacy/raw_gadget.c
++++ b/drivers/usb/gadget/legacy/raw_gadget.c
+@@ -3,7 +3,8 @@
+  * USB Raw Gadget driver.
+  * See Documentation/usb/raw-gadget.rst for more details.
+  *
+- * Andrey Konovalov <andreyknvl@gmail.com>
++ * Copyright (c) 2020 Google, Inc.
++ * Author: Andrey Konovalov <andreyknvl@gmail.com>
+  */
+ 
+ #include <linux/compiler.h>
+diff --git a/drivers/usb/gadget/legacy/webcam.c b/drivers/usb/gadget/legacy/webcam.c
+index 2c9eab2b8..94e22867d 100644
+--- a/drivers/usb/gadget/legacy/webcam.c
++++ b/drivers/usb/gadget/legacy/webcam.c
+@@ -90,7 +90,7 @@ static const struct UVC_HEADER_DESCRIPTOR(1) uvc_control_header = {
+ 	.bLength		= UVC_DT_HEADER_SIZE(1),
+ 	.bDescriptorType	= USB_DT_CS_INTERFACE,
+ 	.bDescriptorSubType	= UVC_VC_HEADER,
+-	.bcdUVC			= cpu_to_le16(0x0100),
++	.bcdUVC			= cpu_to_le16(0x0110),
+ 	.wTotalLength		= 0, /* dynamic */
+ 	.dwClockFrequency	= cpu_to_le32(48000000),
+ 	.bInCollection		= 0, /* dynamic */
+diff --git a/drivers/usb/gadget/udc/Kconfig b/drivers/usb/gadget/udc/Kconfig
+index f28e1bbd5..6c8842e54 100644
+--- a/drivers/usb/gadget/udc/Kconfig
++++ b/drivers/usb/gadget/udc/Kconfig
+@@ -330,7 +330,6 @@ config USB_AMD5536UDC
+ config USB_FSL_QE
+ 	tristate "Freescale QE/CPM USB Device Controller"
+ 	depends on FSL_SOC && (QUICC_ENGINE || CPM)
+-	depends on !64BIT || BROKEN
+ 	help
+ 	   Some of Freescale PowerPC processors have a Full Speed
+ 	   QE/CPM2 USB controller, which support device mode with 4
+diff --git a/drivers/usb/gadget/udc/amd5536udc_pci.c b/drivers/usb/gadget/udc/amd5536udc_pci.c
+index c80f9bd51..8d387e0e4 100644
+--- a/drivers/usb/gadget/udc/amd5536udc_pci.c
++++ b/drivers/usb/gadget/udc/amd5536udc_pci.c
+@@ -153,11 +153,6 @@ static int udc_pci_probe(
+ 	pci_set_master(pdev);
+ 	pci_try_set_mwi(pdev);
+ 
+-	dev->phys_addr = resource;
+-	dev->irq = pdev->irq;
+-	dev->pdev = pdev;
+-	dev->dev = &pdev->dev;
+-
+ 	/* init dma pools */
+ 	if (use_dma) {
+ 		retval = init_dma_pools(dev);
+@@ -165,6 +160,11 @@ static int udc_pci_probe(
+ 			goto err_dma;
+ 	}
+ 
++	dev->phys_addr = resource;
++	dev->irq = pdev->irq;
++	dev->pdev = pdev;
++	dev->dev = &pdev->dev;
++
+ 	/* general probing */
+ 	if (udc_probe(dev)) {
+ 		retval = -ENODEV;
+diff --git a/drivers/usb/gadget/udc/aspeed-vhub/core.c b/drivers/usb/gadget/udc/aspeed-vhub/core.c
+index d11d3d143..be7bb64e3 100644
+--- a/drivers/usb/gadget/udc/aspeed-vhub/core.c
++++ b/drivers/usb/gadget/udc/aspeed-vhub/core.c
+@@ -36,7 +36,6 @@ void ast_vhub_done(struct ast_vhub_ep *ep, struct ast_vhub_req *req,
+ 		   int status)
+ {
+ 	bool internal = req->internal;
+-	struct ast_vhub *vhub = ep->vhub;
+ 
+ 	EPVDBG(ep, "completing request @%p, status %d\n", req, status);
+ 
+@@ -47,7 +46,7 @@ void ast_vhub_done(struct ast_vhub_ep *ep, struct ast_vhub_req *req,
+ 
+ 	if (req->req.dma) {
+ 		if (!WARN_ON(!ep->dev))
+-			usb_gadget_unmap_request_by_dev(&vhub->pdev->dev,
++			usb_gadget_unmap_request(&ep->dev->gadget,
+ 						 &req->req, ep->epn.is_in);
+ 		req->req.dma = 0;
+ 	}
+diff --git a/drivers/usb/gadget/udc/aspeed-vhub/epn.c b/drivers/usb/gadget/udc/aspeed-vhub/epn.c
+index cb164c615..02d8bfae5 100644
+--- a/drivers/usb/gadget/udc/aspeed-vhub/epn.c
++++ b/drivers/usb/gadget/udc/aspeed-vhub/epn.c
+@@ -376,7 +376,7 @@ static int ast_vhub_epn_queue(struct usb_ep* u_ep, struct usb_request *u_req,
+ 	if (ep->epn.desc_mode ||
+ 	    ((((unsigned long)u_req->buf & 7) == 0) &&
+ 	     (ep->epn.is_in || !(u_req->length & (u_ep->maxpacket - 1))))) {
+-		rc = usb_gadget_map_request_by_dev(&vhub->pdev->dev, u_req,
++		rc = usb_gadget_map_request(&ep->dev->gadget, u_req,
+ 					    ep->epn.is_in);
+ 		if (rc) {
+ 			dev_warn(&vhub->pdev->dev,
+diff --git a/drivers/usb/gadget/udc/at91_udc.c b/drivers/usb/gadget/udc/at91_udc.c
+index d9ad9adf7..eede5ceda 100644
+--- a/drivers/usb/gadget/udc/at91_udc.c
++++ b/drivers/usb/gadget/udc/at91_udc.c
+@@ -1876,9 +1876,7 @@ static int at91udc_probe(struct platform_device *pdev)
+ 	clk_disable(udc->iclk);
+ 
+ 	/* request UDC and maybe VBUS irqs */
+-	udc->udp_irq = retval = platform_get_irq(pdev, 0);
+-	if (retval < 0)
+-		goto err_unprepare_iclk;
++	udc->udp_irq = platform_get_irq(pdev, 0);
+ 	retval = devm_request_irq(dev, udc->udp_irq, at91_udc_irq, 0,
+ 				  driver_name, udc);
+ 	if (retval) {
+diff --git a/drivers/usb/gadget/udc/bdc/bdc_core.c b/drivers/usb/gadget/udc/bdc/bdc_core.c
+index fa1a3908e..0bef6b3f0 100644
+--- a/drivers/usb/gadget/udc/bdc/bdc_core.c
++++ b/drivers/usb/gadget/udc/bdc/bdc_core.c
+@@ -488,14 +488,27 @@ static int bdc_probe(struct platform_device *pdev)
+ 	int irq;
+ 	u32 temp;
+ 	struct device *dev = &pdev->dev;
++	struct clk *clk;
+ 	int phy_num;
+ 
+ 	dev_dbg(dev, "%s()\n", __func__);
+ 
++	clk = devm_clk_get_optional(dev, "sw_usbd");
++	if (IS_ERR(clk))
++		return PTR_ERR(clk);
++
++	ret = clk_prepare_enable(clk);
++	if (ret) {
++		dev_err(dev, "could not enable clock\n");
++		return ret;
++	}
++
+ 	bdc = devm_kzalloc(dev, sizeof(*bdc), GFP_KERNEL);
+ 	if (!bdc)
+ 		return -ENOMEM;
+ 
++	bdc->clk = clk;
++
+ 	bdc->regs = devm_platform_ioremap_resource(pdev, 0);
+ 	if (IS_ERR(bdc->regs))
+ 		return PTR_ERR(bdc->regs);
+@@ -532,20 +545,10 @@ static int bdc_probe(struct platform_device *pdev)
+ 		}
+ 	}
+ 
+-	bdc->clk = devm_clk_get_optional(dev, "sw_usbd");
+-	if (IS_ERR(bdc->clk))
+-		return PTR_ERR(bdc->clk);
+-
+-	ret = clk_prepare_enable(bdc->clk);
+-	if (ret) {
+-		dev_err(dev, "could not enable clock\n");
+-		return ret;
+-	}
+-
+ 	ret = bdc_phy_init(bdc);
+ 	if (ret) {
+ 		dev_err(bdc->dev, "BDC phy init failure:%d\n", ret);
+-		goto disable_clk;
++		return ret;
+ 	}
+ 
+ 	temp = bdc_readl(bdc->regs, BDC_BDCCAP1);
+@@ -557,8 +560,7 @@ static int bdc_probe(struct platform_device *pdev)
+ 		if (ret) {
+ 			dev_err(dev,
+ 				"No suitable DMA config available, abort\n");
+-			ret = -ENOTSUPP;
+-			goto phycleanup;
++			return -ENOTSUPP;
+ 		}
+ 		dev_dbg(dev, "Using 32-bit address\n");
+ 	}
+@@ -578,8 +580,6 @@ static int bdc_probe(struct platform_device *pdev)
+ 	bdc_hw_exit(bdc);
+ phycleanup:
+ 	bdc_phy_exit(bdc);
+-disable_clk:
+-	clk_disable_unprepare(bdc->clk);
+ 	return ret;
+ }
+ 
+diff --git a/drivers/usb/gadget/udc/core.c b/drivers/usb/gadget/udc/core.c
+index 3a3b5a03d..5e8fb3598 100644
+--- a/drivers/usb/gadget/udc/core.c
++++ b/drivers/usb/gadget/udc/core.c
+@@ -29,6 +29,7 @@
+  * @list: for use by the udc class driver
+  * @vbus: for udcs who care about vbus status, this value is real vbus status;
+  * for udcs who do not care about vbus status, this value is always true
++ * @started: the UDC's started state. True if the UDC had started.
+  *
+  * This represents the internal data structure which is used by the UDC-class
+  * to hold information about udc driver and gadget together.
+@@ -39,6 +40,7 @@ struct usb_udc {
+ 	struct device			dev;
+ 	struct list_head		list;
+ 	bool				vbus;
++	bool				started;
+ };
+ 
+ static struct class *udc_class;
+@@ -1004,6 +1006,25 @@ int usb_gadget_ep_match_desc(struct usb_gadget *gadget,
+ }
+ EXPORT_SYMBOL_GPL(usb_gadget_ep_match_desc);
+ 
++/**
++ * usb_gadget_check_config - checks if the UDC can support the binded
++ *	configuration
++ * @gadget: controller to check the USB configuration
++ *
++ * Ensure that a UDC is able to support the requested resources by a
++ * configuration, and that there are no resource limitations, such as
++ * internal memory allocated to all requested endpoints.
++ *
++ * Returns zero on success, else a negative errno.
++ */
++int usb_gadget_check_config(struct usb_gadget *gadget)
++{
++	if (gadget->ops->check_config)
++		return gadget->ops->check_config(gadget);
++	return 0;
++}
++EXPORT_SYMBOL_GPL(usb_gadget_check_config);
++
+ /* ------------------------------------------------------------------------- */
+ 
+ static void usb_gadget_state_work(struct work_struct *work)
+@@ -1085,7 +1106,18 @@ EXPORT_SYMBOL_GPL(usb_gadget_udc_reset);
+  */
+ static inline int usb_gadget_udc_start(struct usb_udc *udc)
+ {
+-	return udc->gadget->ops->udc_start(udc->gadget, udc->driver);
++	int ret;
++
++	if (udc->started) {
++		dev_err(&udc->dev, "UDC had already started\n");
++		return -EBUSY;
++	}
++
++	ret = udc->gadget->ops->udc_start(udc->gadget, udc->driver);
++	if (!ret)
++		udc->started = true;
++
++	return ret;
+ }
+ 
+ /**
+@@ -1101,7 +1133,13 @@ static inline int usb_gadget_udc_start(struct usb_udc *udc)
+  */
+ static inline void usb_gadget_udc_stop(struct usb_udc *udc)
+ {
++	if (!udc->started) {
++		dev_err(&udc->dev, "UDC had already stopped\n");
++		return;
++	}
++
+ 	udc->gadget->ops->udc_stop(udc->gadget);
++	udc->started = false;
+ }
+ 
+ /**
+@@ -1117,12 +1155,65 @@ static inline void usb_gadget_udc_stop(struct usb_udc *udc)
+ static inline void usb_gadget_udc_set_speed(struct usb_udc *udc,
+ 					    enum usb_device_speed speed)
+ {
+-	if (udc->gadget->ops->udc_set_speed) {
+-		enum usb_device_speed s;
++	struct usb_gadget *gadget = udc->gadget;
++	enum usb_device_speed s;
+ 
+-		s = min(speed, udc->gadget->max_speed);
+-		udc->gadget->ops->udc_set_speed(udc->gadget, s);
+-	}
++	if (speed == USB_SPEED_UNKNOWN)
++		s = gadget->max_speed;
++	else
++		s = min(speed, gadget->max_speed);
++
++	if (s == USB_SPEED_SUPER_PLUS && gadget->ops->udc_set_ssp_rate)
++		gadget->ops->udc_set_ssp_rate(gadget, gadget->max_ssp_rate);
++	else if (gadget->ops->udc_set_speed)
++		gadget->ops->udc_set_speed(gadget, s);
++}
++
++/**
++ * usb_gadget_enable_async_callbacks - tell usb device controller to enable asynchronous callbacks
++ * @udc: The UDC which should enable async callbacks
++ *
++ * This routine is used when binding gadget drivers.  It undoes the effect
++ * of usb_gadget_disable_async_callbacks(); the UDC driver should enable IRQs
++ * (if necessary) and resume issuing callbacks.
++ *
++ * This routine will always be called in process context.
++ */
++static inline void usb_gadget_enable_async_callbacks(struct usb_udc *udc)
++{
++	struct usb_gadget *gadget = udc->gadget;
++
++	if (gadget->ops->udc_async_callbacks)
++		gadget->ops->udc_async_callbacks(gadget, true);
++}
++
++/**
++ * usb_gadget_disable_async_callbacks - tell usb device controller to disable asynchronous callbacks
++ * @udc: The UDC which should disable async callbacks
++ *
++ * This routine is used when unbinding gadget drivers.  It prevents a race:
++ * The UDC driver doesn't know when the gadget driver's ->unbind callback
++ * runs, so unless it is told to disable asynchronous callbacks, it might
++ * issue a callback (such as ->disconnect) after the unbind has completed.
++ *
++ * After this function runs, the UDC driver must suppress all ->suspend,
++ * ->resume, ->disconnect, ->reset, and ->setup callbacks to the gadget driver
++ * until async callbacks are again enabled.  A simple-minded but effective
++ * way to accomplish this is to tell the UDC hardware not to generate any
++ * more IRQs.
++ *
++ * Request completion callbacks must still be issued.  However, it's okay
++ * to defer them until the request is cancelled, since the pull-up will be
++ * turned off during the time period when async callbacks are disabled.
++ *
++ * This routine will always be called in process context.
++ */
++static inline void usb_gadget_disable_async_callbacks(struct usb_udc *udc)
++{
++	struct usb_gadget *gadget = udc->gadget;
++
++	if (gadget->ops->udc_async_callbacks)
++		gadget->ops->udc_async_callbacks(gadget, false);
+ }
+ 
+ /**
+@@ -1225,6 +1316,8 @@ int usb_add_gadget(struct usb_gadget *gadget)
+ 	udc->gadget = gadget;
+ 	gadget->udc = udc;
+ 
++	udc->started = false;
++
+ 	mutex_lock(&udc_lock);
+ 	list_add_tail(&udc->list, &udc_list);
+ 
+@@ -1337,6 +1430,7 @@ static void usb_gadget_remove_driver(struct usb_udc *udc)
+ 	kobject_uevent(&udc->dev.kobj, KOBJ_CHANGE);
+ 
+ 	usb_gadget_disconnect(udc->gadget);
++	usb_gadget_disable_async_callbacks(udc);
+ 	if (udc->gadget->irq)
+ 		synchronize_irq(udc->gadget->irq);
+ 	udc->driver->unbind(udc->gadget);
+@@ -1416,6 +1510,7 @@ static int udc_bind_to_driver(struct usb_udc *udc, struct usb_gadget_driver *dri
+ 		driver->unbind(udc->gadget);
+ 		goto err1;
+ 	}
++	usb_gadget_enable_async_callbacks(udc);
+ 	usb_udc_connect_control(udc);
+ 
+ 	kobject_uevent(&udc->dev.kobj, KOBJ_CHANGE);
+diff --git a/drivers/usb/gadget/udc/dummy_hcd.c b/drivers/usb/gadget/udc/dummy_hcd.c
+index 92d01ddae..9ae5fc8da 100644
+--- a/drivers/usb/gadget/udc/dummy_hcd.c
++++ b/drivers/usb/gadget/udc/dummy_hcd.c
+@@ -932,6 +932,15 @@ static void dummy_udc_set_speed(struct usb_gadget *_gadget,
+ 	dummy_udc_update_ep0(dum);
+ }
+ 
++static void dummy_udc_async_callbacks(struct usb_gadget *_gadget, bool enable)
++{
++	struct dummy	*dum = gadget_dev_to_dummy(&_gadget->dev);
++
++	spin_lock_irq(&dum->lock);
++	dum->ints_enabled = enable;
++	spin_unlock_irq(&dum->lock);
++}
++
+ static int dummy_udc_start(struct usb_gadget *g,
+ 		struct usb_gadget_driver *driver);
+ static int dummy_udc_stop(struct usb_gadget *g);
+@@ -944,6 +953,7 @@ static const struct usb_gadget_ops dummy_ops = {
+ 	.udc_start	= dummy_udc_start,
+ 	.udc_stop	= dummy_udc_stop,
+ 	.udc_set_speed	= dummy_udc_set_speed,
++	.udc_async_callbacks = dummy_udc_async_callbacks,
+ };
+ 
+ /*-------------------------------------------------------------------------*/
+@@ -1003,7 +1013,6 @@ static int dummy_udc_start(struct usb_gadget *g,
+ 	spin_lock_irq(&dum->lock);
+ 	dum->devstatus = 0;
+ 	dum->driver = driver;
+-	dum->ints_enabled = 1;
+ 	spin_unlock_irq(&dum->lock);
+ 
+ 	return 0;
+@@ -1017,6 +1026,7 @@ static int dummy_udc_stop(struct usb_gadget *g)
+ 	spin_lock_irq(&dum->lock);
+ 	dum->ints_enabled = 0;
+ 	stop_activity(dum);
++
+ 	dum->driver = NULL;
+ 	spin_unlock_irq(&dum->lock);
+ 
+@@ -1869,7 +1879,7 @@ static void dummy_timer(struct timer_list *t)
+ 		/* handle control requests */
+ 		if (ep == &dum->ep[0] && ep->setup_stage) {
+ 			struct usb_ctrlrequest		setup;
+-			int				value = 1;
++			int				value;
+ 
+ 			setup = *(struct usb_ctrlrequest *) urb->setup_packet;
+ 			/* paranoia, in case of stale queued data */
+diff --git a/drivers/usb/gadget/udc/fotg210-udc.c b/drivers/usb/gadget/udc/fotg210-udc.c
+index 75bf446f4..d6ca50f01 100644
+--- a/drivers/usb/gadget/udc/fotg210-udc.c
++++ b/drivers/usb/gadget/udc/fotg210-udc.c
+@@ -338,16 +338,15 @@ static void fotg210_start_dma(struct fotg210_ep *ep,
+ 		} else {
+ 			buffer = req->req.buf + req->req.actual;
+ 			length = ioread32(ep->fotg210->reg +
+-					FOTG210_FIBCR(ep->epnum - 1)) & FIBCR_BCFX;
+-			if (length > req->req.length - req->req.actual)
+-				length = req->req.length - req->req.actual;
++					FOTG210_FIBCR(ep->epnum - 1));
++			length &= FIBCR_BCFX;
+ 		}
+ 	} else {
+ 		buffer = req->req.buf + req->req.actual;
+ 		if (req->req.length - req->req.actual > ep->ep.maxpacket)
+ 			length = ep->ep.maxpacket;
+ 		else
+-			length = req->req.length - req->req.actual;
++			length = req->req.length;
+ 	}
+ 
+ 	d = dma_map_single(dev, buffer, length,
+@@ -380,7 +379,8 @@ static void fotg210_ep0_queue(struct fotg210_ep *ep,
+ 	}
+ 	if (ep->dir_in) { /* if IN */
+ 		fotg210_start_dma(ep, req);
+-		if (req->req.length == req->req.actual)
++		if ((req->req.length == req->req.actual) ||
++		    (req->req.actual < ep->ep.maxpacket))
+ 			fotg210_done(ep, req, 0);
+ 	} else { /* OUT */
+ 		u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR0);
+@@ -820,7 +820,7 @@ static void fotg210_ep0in(struct fotg210_udc *fotg210)
+ 		if (req->req.length)
+ 			fotg210_start_dma(ep, req);
+ 
+-		if (req->req.actual == req->req.length)
++		if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
+ 			fotg210_done(ep, req, 0);
+ 	} else {
+ 		fotg210_set_cxdone(fotg210);
+@@ -849,16 +849,12 @@ static void fotg210_out_fifo_handler(struct fotg210_ep *ep)
+ {
+ 	struct fotg210_request *req = list_entry(ep->queue.next,
+ 						 struct fotg210_request, queue);
+-	int disgr1 = ioread32(ep->fotg210->reg + FOTG210_DISGR1);
+ 
+ 	fotg210_start_dma(ep, req);
+ 
+-	/* Complete the request when it's full or a short packet arrived.
+-	 * Like other drivers, short_not_ok isn't handled.
+-	 */
+-
++	/* finish out transfer */
+ 	if (req->req.length == req->req.actual ||
+-	    (disgr1 & DISGR1_SPK_INT(ep->epnum - 1)))
++	    req->req.actual < ep->ep.maxpacket)
+ 		fotg210_done(ep, req, 0);
+ }
+ 
+@@ -1031,12 +1027,6 @@ static void fotg210_init(struct fotg210_udc *fotg210)
+ 	value &= ~DMCR_GLINT_EN;
+ 	iowrite32(value, fotg210->reg + FOTG210_DMCR);
+ 
+-	/* enable only grp2 irqs we handle */
+-	iowrite32(~(DISGR2_DMA_ERROR | DISGR2_RX0BYTE_INT | DISGR2_TX0BYTE_INT
+-		    | DISGR2_ISO_SEQ_ABORT_INT | DISGR2_ISO_SEQ_ERR_INT
+-		    | DISGR2_RESM_INT | DISGR2_SUSP_INT | DISGR2_USBRST_INT),
+-		  fotg210->reg + FOTG210_DMISGR2);
+-
+ 	/* disable all fifo interrupt */
+ 	iowrite32(~(u32)0, fotg210->reg + FOTG210_DMISGR1);
+ 
+diff --git a/drivers/usb/gadget/udc/max3420_udc.c b/drivers/usb/gadget/udc/max3420_udc.c
+index 91c9e9057..35179543c 100644
+--- a/drivers/usb/gadget/udc/max3420_udc.c
++++ b/drivers/usb/gadget/udc/max3420_udc.c
+@@ -1260,14 +1260,12 @@ static int max3420_probe(struct spi_device *spi)
+ 	err = devm_request_irq(&spi->dev, irq, max3420_irq_handler, 0,
+ 			       "max3420", udc);
+ 	if (err < 0)
+-		goto del_gadget;
++		return err;
+ 
+ 	udc->thread_task = kthread_create(max3420_thread, udc,
+ 					  "max3420-thread");
+-	if (IS_ERR(udc->thread_task)) {
+-		err = PTR_ERR(udc->thread_task);
+-		goto del_gadget;
+-	}
++	if (IS_ERR(udc->thread_task))
++		return PTR_ERR(udc->thread_task);
+ 
+ 	irq = of_irq_get_byname(spi->dev.of_node, "vbus");
+ 	if (irq <= 0) { /* no vbus irq implies self-powered design */
+@@ -1287,14 +1285,10 @@ static int max3420_probe(struct spi_device *spi)
+ 		err = devm_request_irq(&spi->dev, irq,
+ 				       max3420_vbus_handler, 0, "vbus", udc);
+ 		if (err < 0)
+-			goto del_gadget;
++			return err;
+ 	}
+ 
+ 	return 0;
+-
+-del_gadget:
+-	usb_del_gadget_udc(&udc->gadget);
+-	return err;
+ }
+ 
+ static int max3420_remove(struct spi_device *spi)
+diff --git a/drivers/usb/gadget/udc/mv_u3d_core.c b/drivers/usb/gadget/udc/mv_u3d_core.c
+index 0db97fecf..5486f5a70 100644
+--- a/drivers/usb/gadget/udc/mv_u3d_core.c
++++ b/drivers/usb/gadget/udc/mv_u3d_core.c
+@@ -1921,6 +1921,14 @@ static int mv_u3d_probe(struct platform_device *dev)
+ 		goto err_get_irq;
+ 	}
+ 	u3d->irq = r->start;
++	if (request_irq(u3d->irq, mv_u3d_irq,
++		IRQF_SHARED, driver_name, u3d)) {
++		u3d->irq = 0;
++		dev_err(&dev->dev, "Request irq %d for u3d failed\n",
++			u3d->irq);
++		retval = -ENODEV;
++		goto err_request_irq;
++	}
+ 
+ 	/* initialize gadget structure */
+ 	u3d->gadget.ops = &mv_u3d_ops;	/* usb_gadget_ops */
+@@ -1933,15 +1941,6 @@ static int mv_u3d_probe(struct platform_device *dev)
+ 
+ 	mv_u3d_eps_init(u3d);
+ 
+-	if (request_irq(u3d->irq, mv_u3d_irq,
+-		IRQF_SHARED, driver_name, u3d)) {
+-		u3d->irq = 0;
+-		dev_err(&dev->dev, "Request irq %d for u3d failed\n",
+-			u3d->irq);
+-		retval = -ENODEV;
+-		goto err_request_irq;
+-	}
+-
+ 	/* external vbus detection */
+ 	if (u3d->vbus) {
+ 		u3d->clock_gating = 1;
+@@ -1965,8 +1964,8 @@ static int mv_u3d_probe(struct platform_device *dev)
+ 
+ err_unregister:
+ 	free_irq(u3d->irq, u3d);
+-err_get_irq:
+ err_request_irq:
++err_get_irq:
+ 	kfree(u3d->status_req);
+ err_alloc_status_req:
+ 	kfree(u3d->eps);
+diff --git a/drivers/usb/gadget/udc/pch_udc.c b/drivers/usb/gadget/udc/pch_udc.c
+index fd3656d0f..a3c1fc924 100644
+--- a/drivers/usb/gadget/udc/pch_udc.c
++++ b/drivers/usb/gadget/udc/pch_udc.c
+@@ -7,14 +7,12 @@
+ #include <linux/module.h>
+ #include <linux/pci.h>
+ #include <linux/delay.h>
+-#include <linux/dmi.h>
+ #include <linux/errno.h>
+-#include <linux/gpio/consumer.h>
+-#include <linux/gpio/machine.h>
+ #include <linux/list.h>
+ #include <linux/interrupt.h>
+ #include <linux/usb/ch9.h>
+ #include <linux/usb/gadget.h>
++#include <linux/gpio/consumer.h>
+ #include <linux/irq.h>
+ 
+ #define PCH_VBUS_PERIOD		3000	/* VBUS polling period (msec) */
+@@ -598,22 +596,18 @@ static void pch_udc_reconnect(struct pch_udc_dev *dev)
+ static inline void pch_udc_vbus_session(struct pch_udc_dev *dev,
+ 					  int is_active)
+ {
+-	unsigned long		iflags;
+-
+-	spin_lock_irqsave(&dev->lock, iflags);
+ 	if (is_active) {
+ 		pch_udc_reconnect(dev);
+ 		dev->vbus_session = 1;
+ 	} else {
+ 		if (dev->driver && dev->driver->disconnect) {
+-			spin_unlock_irqrestore(&dev->lock, iflags);
++			spin_lock(&dev->lock);
+ 			dev->driver->disconnect(&dev->gadget);
+-			spin_lock_irqsave(&dev->lock, iflags);
++			spin_unlock(&dev->lock);
+ 		}
+ 		pch_udc_set_disconnect(dev);
+ 		dev->vbus_session = 0;
+ 	}
+-	spin_unlock_irqrestore(&dev->lock, iflags);
+ }
+ 
+ /**
+@@ -1172,25 +1166,20 @@ static int pch_udc_pcd_selfpowered(struct usb_gadget *gadget, int value)
+ static int pch_udc_pcd_pullup(struct usb_gadget *gadget, int is_on)
+ {
+ 	struct pch_udc_dev	*dev;
+-	unsigned long		iflags;
+ 
+ 	if (!gadget)
+ 		return -EINVAL;
+-
+ 	dev = container_of(gadget, struct pch_udc_dev, gadget);
+-
+-	spin_lock_irqsave(&dev->lock, iflags);
+ 	if (is_on) {
+ 		pch_udc_reconnect(dev);
+ 	} else {
+ 		if (dev->driver && dev->driver->disconnect) {
+-			spin_unlock_irqrestore(&dev->lock, iflags);
++			spin_lock(&dev->lock);
+ 			dev->driver->disconnect(&dev->gadget);
+-			spin_lock_irqsave(&dev->lock, iflags);
++			spin_unlock(&dev->lock);
+ 		}
+ 		pch_udc_set_disconnect(dev);
+ 	}
+-	spin_unlock_irqrestore(&dev->lock, iflags);
+ 
+ 	return 0;
+ }
+@@ -1361,43 +1350,6 @@ static irqreturn_t pch_vbus_gpio_irq(int irq, void *data)
+ 	return IRQ_HANDLED;
+ }
+ 
+-static struct gpiod_lookup_table minnowboard_udc_gpios = {
+-	.dev_id		= "0000:02:02.4",
+-	.table		= {
+-		GPIO_LOOKUP("sch_gpio.33158", 12, NULL, GPIO_ACTIVE_HIGH),
+-		{}
+-	},
+-};
+-
+-static const struct dmi_system_id pch_udc_gpio_dmi_table[] = {
+-	{
+-		.ident = "MinnowBoard",
+-		.matches = {
+-			DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
+-		},
+-		.driver_data = &minnowboard_udc_gpios,
+-	},
+-	{ }
+-};
+-
+-static void pch_vbus_gpio_remove_table(void *table)
+-{
+-	gpiod_remove_lookup_table(table);
+-}
+-
+-static int pch_vbus_gpio_add_table(struct pch_udc_dev *dev)
+-{
+-	struct device *d = &dev->pdev->dev;
+-	const struct dmi_system_id *dmi;
+-
+-	dmi = dmi_first_match(pch_udc_gpio_dmi_table);
+-	if (!dmi)
+-		return 0;
+-
+-	gpiod_add_lookup_table(dmi->driver_data);
+-	return devm_add_action_or_reset(d, pch_vbus_gpio_remove_table, dmi->driver_data);
+-}
+-
+ /**
+  * pch_vbus_gpio_init() - This API initializes GPIO port detecting VBUS.
+  * @dev:		Reference to the driver structure
+@@ -1408,7 +1360,6 @@ static int pch_vbus_gpio_add_table(struct pch_udc_dev *dev)
+  */
+ static int pch_vbus_gpio_init(struct pch_udc_dev *dev)
+ {
+-	struct device *d = &dev->pdev->dev;
+ 	int err;
+ 	int irq_num = 0;
+ 	struct gpio_desc *gpiod;
+@@ -1416,12 +1367,8 @@ static int pch_vbus_gpio_init(struct pch_udc_dev *dev)
+ 	dev->vbus_gpio.port = NULL;
+ 	dev->vbus_gpio.intr = 0;
+ 
+-	err = pch_vbus_gpio_add_table(dev);
+-	if (err)
+-		return err;
+-
+ 	/* Retrieve the GPIO line from the USB gadget device */
+-	gpiod = devm_gpiod_get_optional(d, NULL, GPIOD_IN);
++	gpiod = devm_gpiod_get(dev->gadget.dev.parent, NULL, GPIOD_IN);
+ 	if (IS_ERR(gpiod))
+ 		return PTR_ERR(gpiod);
+ 	gpiod_set_consumer_name(gpiod, "pch_vbus");
+@@ -1809,7 +1756,7 @@ static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep,
+ 	}
+ 	/* prevent from using desc. - set HOST BUSY */
+ 	dma_desc->status |= PCH_UDC_BS_HST_BSY;
+-	dma_desc->dataptr = lower_32_bits(DMA_ADDR_INVALID);
++	dma_desc->dataptr = cpu_to_le32(DMA_ADDR_INVALID);
+ 	req->td_data = dma_desc;
+ 	req->td_data_last = dma_desc;
+ 	req->chain_len = 1;
+@@ -2351,21 +2298,6 @@ static void pch_udc_svc_data_out(struct pch_udc_dev *dev, int ep_num)
+ 		pch_udc_set_dma(dev, DMA_DIR_RX);
+ }
+ 
+-static int pch_udc_gadget_setup(struct pch_udc_dev *dev)
+-	__must_hold(&dev->lock)
+-{
+-	int rc;
+-
+-	/* In some cases we can get an interrupt before driver gets setup */
+-	if (!dev->driver)
+-		return -ESHUTDOWN;
+-
+-	spin_unlock(&dev->lock);
+-	rc = dev->driver->setup(&dev->gadget, &dev->setup_data);
+-	spin_lock(&dev->lock);
+-	return rc;
+-}
+-
+ /**
+  * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts
+  * @dev:	Reference to the device structure
+@@ -2437,12 +2369,15 @@ static void pch_udc_svc_control_out(struct pch_udc_dev *dev)
+ 			dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
+ 		else /* OUT */
+ 			dev->gadget.ep0 = &ep->ep;
++		spin_lock(&dev->lock);
+ 		/* If Mass storage Reset */
+ 		if ((dev->setup_data.bRequestType == 0x21) &&
+ 		    (dev->setup_data.bRequest == 0xFF))
+ 			dev->prot_stall = 0;
+ 		/* call gadget with setup data received */
+-		setup_supported = pch_udc_gadget_setup(dev);
++		setup_supported = dev->driver->setup(&dev->gadget,
++						     &dev->setup_data);
++		spin_unlock(&dev->lock);
+ 
+ 		if (dev->setup_data.bRequestType & USB_DIR_IN) {
+ 			ep->td_data->status = (ep->td_data->status &
+@@ -2690,7 +2625,9 @@ static void pch_udc_svc_intf_interrupt(struct pch_udc_dev *dev)
+ 		dev->ep[i].halted = 0;
+ 	}
+ 	dev->stall = 0;
+-	pch_udc_gadget_setup(dev);
++	spin_unlock(&dev->lock);
++	dev->driver->setup(&dev->gadget, &dev->setup_data);
++	spin_lock(&dev->lock);
+ }
+ 
+ /**
+@@ -2725,7 +2662,9 @@ static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev *dev)
+ 	dev->stall = 0;
+ 
+ 	/* call gadget zero with setup data received */
+-	pch_udc_gadget_setup(dev);
++	spin_unlock(&dev->lock);
++	dev->driver->setup(&dev->gadget, &dev->setup_data);
++	spin_lock(&dev->lock);
+ }
+ 
+ /**
+@@ -2931,20 +2870,14 @@ static void pch_udc_pcd_reinit(struct pch_udc_dev *dev)
+  * @dev:	Reference to the driver structure
+  *
+  * Return codes:
+- *	0:		Success
+- *	-%ERRNO:	All kind of errors when retrieving VBUS GPIO
++ *	0: Success
+  */
+ static int pch_udc_pcd_init(struct pch_udc_dev *dev)
+ {
+-	int ret;
+-
+ 	pch_udc_init(dev);
+ 	pch_udc_pcd_reinit(dev);
+-
+-	ret = pch_vbus_gpio_init(dev);
+-	if (ret)
+-		pch_udc_exit(dev);
+-	return ret;
++	pch_vbus_gpio_init(dev);
++	return 0;
+ }
+ 
+ /**
+@@ -3005,7 +2938,7 @@ static int init_dma_pools(struct pch_udc_dev *dev)
+ 	dev->dma_addr = dma_map_single(&dev->pdev->dev, ep0out_buf,
+ 				       UDC_EP0OUT_BUFF_SIZE * 4,
+ 				       DMA_FROM_DEVICE);
+-	return dma_mapping_error(&dev->pdev->dev, dev->dma_addr);
++	return 0;
+ }
+ 
+ static int pch_udc_start(struct usb_gadget *g,
+@@ -3130,7 +3063,6 @@ static int pch_udc_probe(struct pci_dev *pdev,
+ 	if (retval)
+ 		return retval;
+ 
+-	dev->pdev = pdev;
+ 	pci_set_drvdata(pdev, dev);
+ 
+ 	/* Determine BAR based on PCI ID */
+@@ -3146,10 +3078,16 @@ static int pch_udc_probe(struct pci_dev *pdev,
+ 
+ 	dev->base_addr = pcim_iomap_table(pdev)[bar];
+ 
++	/*
++	 * FIXME: add a GPIO descriptor table to pdev.dev using
++	 * gpiod_add_descriptor_table() from <linux/gpio/machine.h> based on
++	 * the PCI subsystem ID. The system-dependent GPIO is necessary for
++	 * VBUS operation.
++	 */
++
+ 	/* initialize the hardware */
+-	retval = pch_udc_pcd_init(dev);
+-	if (retval)
+-		return retval;
++	if (pch_udc_pcd_init(dev))
++		return -ENODEV;
+ 
+ 	pci_enable_msi(pdev);
+ 
+@@ -3166,6 +3104,7 @@ static int pch_udc_probe(struct pci_dev *pdev,
+ 
+ 	/* device struct setup */
+ 	spin_lock_init(&dev->lock);
++	dev->pdev = pdev;
+ 	dev->gadget.ops = &pch_udc_ops;
+ 
+ 	retval = init_dma_pools(dev);
+diff --git a/drivers/usb/gadget/udc/r8a66597-udc.c b/drivers/usb/gadget/udc/r8a66597-udc.c
+index 38e4d6b50..896c1a016 100644
+--- a/drivers/usb/gadget/udc/r8a66597-udc.c
++++ b/drivers/usb/gadget/udc/r8a66597-udc.c
+@@ -1250,7 +1250,7 @@ static void set_feature(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
+ 			do {
+ 				tmp = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
+ 				udelay(1);
+-			} while (tmp != CS_IDST && timeout-- > 0);
++			} while (tmp != CS_IDST || timeout-- > 0);
+ 
+ 			if (tmp == CS_IDST)
+ 				r8a66597_bset(r8a66597,
+@@ -1849,8 +1849,6 @@ static int r8a66597_probe(struct platform_device *pdev)
+ 		return PTR_ERR(reg);
+ 
+ 	ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+-	if (!ires)
+-		return -EINVAL;
+ 	irq = ires->start;
+ 	irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
+ 
+diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
+index 601829a6b..e91cbe43d 100644
+--- a/drivers/usb/gadget/udc/renesas_usb3.c
++++ b/drivers/usb/gadget/udc/renesas_usb3.c
+@@ -1488,7 +1488,7 @@ static void usb3_start_pipen(struct renesas_usb3_ep *usb3_ep,
+ 			     struct renesas_usb3_request *usb3_req)
+ {
+ 	struct renesas_usb3 *usb3 = usb3_ep_to_usb3(usb3_ep);
+-	struct renesas_usb3_request *usb3_req_first;
++	struct renesas_usb3_request *usb3_req_first = usb3_get_request(usb3_ep);
+ 	unsigned long flags;
+ 	int ret = -EAGAIN;
+ 	u32 enable_bits = 0;
+@@ -1496,8 +1496,7 @@ static void usb3_start_pipen(struct renesas_usb3_ep *usb3_ep,
+ 	spin_lock_irqsave(&usb3->lock, flags);
+ 	if (usb3_ep->halt || usb3_ep->started)
+ 		goto out;
+-	usb3_req_first = __usb3_get_request(usb3_ep);
+-	if (!usb3_req_first || usb3_req != usb3_req_first)
++	if (usb3_req != usb3_req_first)
+ 		goto out;
+ 
+ 	if (usb3_pn_change(usb3, usb3_ep->num) < 0)
+@@ -2709,15 +2708,10 @@ static const struct renesas_usb3_priv renesas_usb3_priv_r8a77990 = {
+ 
+ static const struct of_device_id usb3_of_match[] = {
+ 	{
+-		.compatible = "renesas,r8a774c0-usb3-peri",
+-		.data = &renesas_usb3_priv_r8a77990,
+-	}, {
+ 		.compatible = "renesas,r8a7795-usb3-peri",
+ 		.data = &renesas_usb3_priv_gen3,
+-	}, {
+-		.compatible = "renesas,r8a77990-usb3-peri",
+-		.data = &renesas_usb3_priv_r8a77990,
+-	}, {
++	},
++	{
+ 		.compatible = "renesas,rcar-gen3-usb3-peri",
+ 		.data = &renesas_usb3_priv_gen3,
+ 	},
+@@ -2726,10 +2720,18 @@ static const struct of_device_id usb3_of_match[] = {
+ MODULE_DEVICE_TABLE(of, usb3_of_match);
+ 
+ static const struct soc_device_attribute renesas_usb3_quirks_match[] = {
++	{
++		.soc_id = "r8a774c0",
++		.data = &renesas_usb3_priv_r8a77990,
++	},
+ 	{
+ 		.soc_id = "r8a7795", .revision = "ES1.*",
+ 		.data = &renesas_usb3_priv_r8a7795_es1,
+ 	},
++	{
++		.soc_id = "r8a77990",
++		.data = &renesas_usb3_priv_r8a77990,
++	},
+ 	{ /* sentinel */ },
+ };
+ 
+diff --git a/drivers/usb/gadget/udc/s3c2410_udc.c b/drivers/usb/gadget/udc/s3c2410_udc.c
+index 82c4f3fb2..f1ea51476 100644
+--- a/drivers/usb/gadget/udc/s3c2410_udc.c
++++ b/drivers/usb/gadget/udc/s3c2410_udc.c
+@@ -54,6 +54,8 @@ static struct clk		*udc_clock;
+ static struct clk		*usb_bus_clock;
+ static void __iomem		*base_addr;
+ static int			irq_usbd;
++static u64			rsrc_start;
++static u64			rsrc_len;
+ static struct dentry		*s3c2410_udc_debugfs_root;
+ 
+ static inline u32 udc_read(u32 reg)
+@@ -1750,8 +1752,7 @@ static int s3c2410_udc_probe(struct platform_device *pdev)
+ 	udc_clock = clk_get(NULL, "usb-device");
+ 	if (IS_ERR(udc_clock)) {
+ 		dev_err(dev, "failed to get udc clock source\n");
+-		retval = PTR_ERR(udc_clock);
+-		goto err_usb_bus_clk;
++		return PTR_ERR(udc_clock);
+ 	}
+ 
+ 	clk_prepare_enable(udc_clock);
+@@ -1772,9 +1773,9 @@ static int s3c2410_udc_probe(struct platform_device *pdev)
+ 	udc_info = dev_get_platdata(&pdev->dev);
+ 
+ 	base_addr = devm_platform_ioremap_resource(pdev, 0);
+-	if (IS_ERR(base_addr)) {
+-		retval = PTR_ERR(base_addr);
+-		goto err_udc_clk;
++	if (!base_addr) {
++		retval = -ENOMEM;
++		goto err_mem;
+ 	}
+ 
+ 	the_controller = udc;
+@@ -1784,10 +1785,6 @@ static int s3c2410_udc_probe(struct platform_device *pdev)
+ 	s3c2410_udc_reinit(udc);
+ 
+ 	irq_usbd = platform_get_irq(pdev, 0);
+-	if (irq_usbd < 0) {
+-		retval = irq_usbd;
+-		goto err_udc_clk;
+-	}
+ 
+ 	/* irq setup after old hardware state is cleaned up */
+ 	retval = request_irq(irq_usbd, s3c2410_udc_irq,
+@@ -1796,7 +1793,7 @@ static int s3c2410_udc_probe(struct platform_device *pdev)
+ 	if (retval != 0) {
+ 		dev_err(dev, "cannot get irq %i, err %d\n", irq_usbd, retval);
+ 		retval = -EBUSY;
+-		goto err_udc_clk;
++		goto err_map;
+ 	}
+ 
+ 	dev_dbg(dev, "got irq %i\n", irq_usbd);
+@@ -1867,14 +1864,10 @@ static int s3c2410_udc_probe(struct platform_device *pdev)
+ 		gpio_free(udc_info->vbus_pin);
+ err_int:
+ 	free_irq(irq_usbd, udc);
+-err_udc_clk:
+-	clk_disable_unprepare(udc_clock);
+-	clk_put(udc_clock);
+-	udc_clock = NULL;
+-err_usb_bus_clk:
+-	clk_disable_unprepare(usb_bus_clock);
+-	clk_put(usb_bus_clock);
+-	usb_bus_clock = NULL;
++err_map:
++	iounmap(base_addr);
++err_mem:
++	release_mem_region(rsrc_start, rsrc_len);
+ 
+ 	return retval;
+ }
+@@ -1906,6 +1899,9 @@ static int s3c2410_udc_remove(struct platform_device *pdev)
+ 
+ 	free_irq(irq_usbd, udc);
+ 
++	iounmap(base_addr);
++	release_mem_region(rsrc_start, rsrc_len);
++
+ 	if (!IS_ERR(udc_clock) && udc_clock != NULL) {
+ 		clk_disable_unprepare(udc_clock);
+ 		clk_put(udc_clock);
+diff --git a/drivers/usb/gadget/udc/snps_udc_core.c b/drivers/usb/gadget/udc/snps_udc_core.c
+index 6c726d2e1..d046c09fa 100644
+--- a/drivers/usb/gadget/udc/snps_udc_core.c
++++ b/drivers/usb/gadget/udc/snps_udc_core.c
+@@ -36,7 +36,6 @@
+ #include <asm/unaligned.h>
+ #include "amd5536udc.h"
+ 
+-static void udc_tasklet_disconnect(unsigned long);
+ static void udc_setup_endpoints(struct udc *dev);
+ static void udc_soft_reset(struct udc *dev);
+ static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep);
+@@ -95,9 +94,6 @@ static struct timer_list udc_pollstall_timer;
+ static int stop_pollstall_timer;
+ static DECLARE_COMPLETION(on_pollstall_exit);
+ 
+-/* tasklet for usb disconnect */
+-static DECLARE_TASKLET_OLD(disconnect_tasklet, udc_tasklet_disconnect);
+-
+ /* endpoint names used for print */
+ static const char ep0_string[] = "ep0in";
+ static const struct {
+@@ -1637,6 +1633,8 @@ static void usb_connect(struct udc *dev)
+  */
+ static void usb_disconnect(struct udc *dev)
+ {
++	u32 tmp;
++
+ 	/* Return if already disconnected */
+ 	if (!dev->connected)
+ 		return;
+@@ -1648,23 +1646,6 @@ static void usb_disconnect(struct udc *dev)
+ 	/* mask interrupts */
+ 	udc_mask_unused_interrupts(dev);
+ 
+-	/* REVISIT there doesn't seem to be a point to having this
+-	 * talk to a tasklet ... do it directly, we already hold
+-	 * the spinlock needed to process the disconnect.
+-	 */
+-
+-	tasklet_schedule(&disconnect_tasklet);
+-}
+-
+-/* Tasklet for disconnect to be outside of interrupt context */
+-static void udc_tasklet_disconnect(unsigned long par)
+-{
+-	struct udc *dev = udc;
+-	u32 tmp;
+-
+-	DBG(dev, "Tasklet disconnect\n");
+-	spin_lock_irq(&dev->lock);
+-
+ 	if (dev->driver) {
+ 		spin_unlock(&dev->lock);
+ 		dev->driver->disconnect(&dev->gadget);
+@@ -1673,13 +1654,10 @@ static void udc_tasklet_disconnect(unsigned long par)
+ 		/* empty queues */
+ 		for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
+ 			empty_req_queue(&dev->ep[tmp]);
+-
+ 	}
+ 
+ 	/* disable ep0 */
+-	ep_init(dev->regs,
+-			&dev->ep[UDC_EP0IN_IX]);
+-
++	ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
+ 
+ 	if (!soft_reset_occured) {
+ 		/* init controller by soft reset */
+@@ -1695,8 +1673,6 @@ static void udc_tasklet_disconnect(unsigned long par)
+ 		tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
+ 		writel(tmp, &dev->regs->cfg);
+ 	}
+-
+-	spin_unlock_irq(&dev->lock);
+ }
+ 
+ /* Reset the UDC core */
+diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c
+index 3ebc8c541..95826f953 100644
+--- a/drivers/usb/gadget/udc/tegra-xudc.c
++++ b/drivers/usb/gadget/udc/tegra-xudc.c
+@@ -1612,7 +1612,7 @@ static void tegra_xudc_ep_context_setup(struct tegra_xudc_ep *ep)
+ 	u16 maxpacket, maxburst = 0, esit = 0;
+ 	u32 val;
+ 
+-	maxpacket = usb_endpoint_maxp(desc);
++	maxpacket = usb_endpoint_maxp(desc) & 0x7ff;
+ 	if (xudc->gadget.speed == USB_SPEED_SUPER) {
+ 		if (!usb_endpoint_xfer_control(desc))
+ 			maxburst = comp_desc->bMaxBurst;
+@@ -1623,7 +1623,7 @@ static void tegra_xudc_ep_context_setup(struct tegra_xudc_ep *ep)
+ 		   (usb_endpoint_xfer_int(desc) ||
+ 		    usb_endpoint_xfer_isoc(desc))) {
+ 		if (xudc->gadget.speed == USB_SPEED_HIGH) {
+-			maxburst = usb_endpoint_maxp_mult(desc) - 1;
++			maxburst = (usb_endpoint_maxp(desc) >> 11) & 0x3;
+ 			if (maxburst == 0x3) {
+ 				dev_warn(xudc->dev,
+ 					 "invalid endpoint maxburst\n");
+@@ -3861,7 +3861,6 @@ static int tegra_xudc_probe(struct platform_device *pdev)
+ 	return 0;
+ 
+ free_eps:
+-	pm_runtime_disable(&pdev->dev);
+ 	tegra_xudc_free_eps(xudc);
+ free_event_ring:
+ 	tegra_xudc_free_event_ring(xudc);
+@@ -3884,7 +3883,7 @@ static int tegra_xudc_remove(struct platform_device *pdev)
+ 
+ 	pm_runtime_get_sync(xudc->dev);
+ 
+-	cancel_delayed_work_sync(&xudc->plc_reset_work);
++	cancel_delayed_work(&xudc->plc_reset_work);
+ 	cancel_work_sync(&xudc->usb_role_sw_work);
+ 
+ 	usb_del_gadget_udc(&xudc->gadget);
+diff --git a/drivers/usb/gadget/udc/udc-xilinx.c b/drivers/usb/gadget/udc/udc-xilinx.c
+index 096f56a09..d5e9d20c0 100644
+--- a/drivers/usb/gadget/udc/udc-xilinx.c
++++ b/drivers/usb/gadget/udc/udc-xilinx.c
+@@ -1612,8 +1612,6 @@ static void xudc_getstatus(struct xusb_udc *udc)
+ 		break;
+ 	case USB_RECIP_ENDPOINT:
+ 		epnum = udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK;
+-		if (epnum >= XUSB_MAX_ENDPOINTS)
+-			goto stall;
+ 		target_ep = &udc->ep[epnum];
+ 		epcfgreg = udc->read_fn(udc->addr + target_ep->offset);
+ 		halt = epcfgreg & XUSB_EP_CFG_STALL_MASK;
+@@ -1681,10 +1679,6 @@ static void xudc_set_clear_feature(struct xusb_udc *udc)
+ 	case USB_RECIP_ENDPOINT:
+ 		if (!udc->setup.wValue) {
+ 			endpoint = udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK;
+-			if (endpoint >= XUSB_MAX_ENDPOINTS) {
+-				xudc_ep0_stall(udc);
+-				return;
+-			}
+ 			target_ep = &udc->ep[endpoint];
+ 			outinbit = udc->setup.wIndex & USB_ENDPOINT_DIR_MASK;
+ 			outinbit = outinbit >> 7;
+diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
+index ef4787cd3..cb6a714bc 100644
+--- a/drivers/usb/phy/Kconfig
++++ b/drivers/usb/phy/Kconfig
+@@ -76,6 +76,26 @@ config AM335X_PHY_USB
+ 	  This driver provides PHY support for that phy which part for the
+ 	  AM335x SoC.
+ 
++choice
++	prompt "Ingenic usb Phy selects"
++
++config INGENIC_INNOPHY
++	tristate "Ingenic usb phy(INNO) implemented."
++	select USB_PHY
++	help
++	  Enable this to support Ingenic USB phy helper driver for ingenic SoCs.
++	  This driver provides common interface to interact, for ingenic Inno PHY,
++	  typically used for X2000 SOCs.
++
++config INGENIC_USB_PHY
++	tristate "Ingenic usb phy."
++	select USB_PHY
++	help
++	  Enable this to support Ingenic USB phy helper driver for ingenic SoCs.
++	  This driver provides common interface to interact, typically used for INGENIC SOCs.
++
++endchoice
++
+ config TWL6030_USB
+ 	tristate "TWL6030 USB Transceiver Driver"
+ 	depends on TWL4030_CORE && OMAP_USB2 && USB_MUSB_OMAP2PLUS
+diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
+index b352bdbe8..08b70220f 100644
+--- a/drivers/usb/phy/Makefile
++++ b/drivers/usb/phy/Makefile
+@@ -25,3 +25,6 @@ obj-$(CONFIG_USB_ULPI)			+= phy-ulpi.o
+ obj-$(CONFIG_USB_ULPI_VIEWPORT)		+= phy-ulpi-viewport.o
+ obj-$(CONFIG_KEYSTONE_USB_PHY)		+= phy-keystone.o
+ obj-$(CONFIG_JZ4770_PHY)		+= phy-jz4770.o
++obj-$(CONFIG_INGENIC_INNOPHY)		+= phy-ingenic-inno.o
++obj-$(CONFIG_INGENIC_USB_PHY)		+= phy-ingenic.o phy-ingenic-x1000.o phy-ingenic-x1600.o phy-ingenic-x2000.o phy-ingenic-x2500.o
++
+diff --git a/drivers/usb/phy/phy-fsl-usb.c b/drivers/usb/phy/phy-fsl-usb.c
+index 972704262..f34c9437a 100644
+--- a/drivers/usb/phy/phy-fsl-usb.c
++++ b/drivers/usb/phy/phy-fsl-usb.c
+@@ -873,8 +873,6 @@ int usb_otg_start(struct platform_device *pdev)
+ 
+ 	/* request irq */
+ 	p_otg->irq = platform_get_irq(pdev, 0);
+-	if (p_otg->irq < 0)
+-		return p_otg->irq;
+ 	status = request_irq(p_otg->irq, fsl_otg_isr,
+ 				IRQF_SHARED, driver_name, p_otg);
+ 	if (status) {
+diff --git a/drivers/usb/phy/phy-ingenic-inno.c b/drivers/usb/phy/phy-ingenic-inno.c
+new file mode 100644
+index 000000000..8cbb313dc
+--- /dev/null
++++ b/drivers/usb/phy/phy-ingenic-inno.c
+@@ -0,0 +1,748 @@
++#include <linux/module.h>
++#include <linux/gpio/consumer.h>
++#include <linux/spinlock.h>
++#include <linux/workqueue.h>
++#include <linux/usb/phy.h>
++#include <linux/platform_device.h>
++#include <linux/usb/gadget.h>
++#include <linux/usb/otg.h>
++#include <linux/of.h>
++#include <linux/clk.h>
++#include <linux/of_gpio.h>
++#include <linux/of_device.h>
++#include <linux/gpio.h>
++#include <linux/delay.h>
++#include <linux/regmap.h>
++#include <linux/mfd/syscon.h>
++#include <soc/cpm.h>
++#include "../dwc2/core.h"
++#include "../dwc2/hcd.h"
++#include <linux/usb/hcd.h>
++
++#define usb_phy_readb(addr)	readb((addr))
++#define usb_phy_writeb(val, addr) writeb(val,(addr))
++
++#define PHY_TX_HS_STRENGTH_CONF	(0x40)
++#define PHY_EYES_MAP_ADJ_CONF	(0x60)
++#define PHY_REG_100		(0x100)
++#define PHY_SUSPEND_LPM		(0x108)
++
++#define PHY_RX_SQU_TRI		(0x64)
++#define PHY_RX_SQU_TRI_112MV    (0x0)
++#define PHY_RX_SQU_TRI_125MV    (0x8)
++
++/* just define for x2500  */
++#define SRBC_USB_SR			BIT (12)
++#define USBRDT_UTMI_RST                 BIT(27)
++
++
++static const struct of_device_id of_matchs[];
++
++struct inno_phy_tuning {
++	u8 val;
++	u8 msk;
++	u8 bit_off;
++	u32 reg_addr;
++};
++
++struct ingenic_usb_phy_priv {
++	bool phy_remote_wakeup;
++	bool phy_vbus_detect_ctl;
++	bool phy_ls_fs_driver_ctl;
++	int (*phyinit)(struct usb_phy*);
++	u32 phy_tuning_num;
++	struct inno_phy_tuning phy_tuning[];
++};
++
++struct ingenic_usb_phy {
++	struct usb_phy phy;
++	struct device *dev;
++	struct clk *gate_clk;
++	struct regmap *regmap;
++	void __iomem *base;
++	char hsotg_sw_switch[8];
++	struct ingenic_usb_phy_priv *iphy_priv;
++
++	/*otg phy*/
++	spinlock_t phy_lock;
++	struct gpio_desc	*gpiod_drvvbus;
++	struct gpio_desc	*gpiod_id;
++	struct gpio_desc	*gpiod_vbus;
++
++#define USB_DETE_VBUS	0x1
++#define USB_DETE_ID	0x2
++	unsigned int usb_dete_state;
++	unsigned int forced_dev_flags;
++	struct delayed_work	work;
++
++	enum usb_device_speed	roothub_port_speed;
++};
++
++static inline int inno_usbphy_read(struct usb_phy *x, u32 reg)
++{
++	struct ingenic_usb_phy *iphy = container_of(x, struct ingenic_usb_phy, phy);
++	u32 val = 0;
++	regmap_read(iphy->regmap, reg, &val);
++	return val;
++}
++
++static inline int inno_usbphy_write(struct usb_phy *x, u32 val, u32 reg)
++{
++	struct ingenic_usb_phy *iphy = container_of(x, struct ingenic_usb_phy, phy);
++
++	return regmap_write(iphy->regmap, reg, val);
++}
++
++static inline int inno_usbphy_update_bits(struct usb_phy *x, u32 reg, u32 mask, u32 bits)
++{
++	struct ingenic_usb_phy *iphy = container_of(x, struct ingenic_usb_phy, phy);
++
++	return regmap_update_bits_check(iphy->regmap, reg, mask, bits, NULL);
++}
++
++#ifdef CONFIG_USB_DWC2_DETECT_CONNECT
++static irqreturn_t usb_dete_irq_handler(int irq, void *data)
++{
++	struct ingenic_usb_phy *iphy = (struct ingenic_usb_phy *)data;
++
++	schedule_delayed_work(&iphy->work, msecs_to_jiffies(100));
++	return IRQ_HANDLED;
++}
++
++static void usb_dete_work(struct work_struct *work)
++{
++	struct ingenic_usb_phy *iphy =
++		container_of(work, struct ingenic_usb_phy, work.work);
++	struct usb_otg		*otg = iphy->phy.otg;
++	int vbus = 0, id_level = 1, usb_state = 0;
++	char *disconnected[2] = { "USB_STATE=DISCONNECTED", NULL };
++	char *connected[2]    = { "USB_STATE=CONNECTED", NULL };
++	char *configured[2]   = { "USB_STATE=CONFIGURED", NULL };
++
++	if (iphy->gpiod_vbus)
++		vbus = gpiod_get_value_cansleep(iphy->gpiod_vbus);
++
++	if (iphy->gpiod_id)
++		id_level = gpiod_get_value_cansleep(iphy->gpiod_id);
++
++	if (!strcmp(iphy->hsotg_sw_switch, "device")) {
++		id_level = 1;
++	}
++
++	if (vbus && id_level)
++		usb_state |= USB_DETE_VBUS;
++	else
++		usb_state &= ~USB_DETE_VBUS;
++
++	if (id_level)
++		usb_state |= USB_DETE_ID;
++	else
++		usb_state &= ~USB_DETE_ID;
++
++
++	if (usb_state != iphy->usb_dete_state) {
++		enum usb_phy_events	status;
++
++		iphy->usb_dete_state = usb_state;
++		printk(KERN_DEBUG "%s() usb_state=0x%x, iphy->phy.devname=%s\n", __func__, usb_state, dev_name(iphy->phy.dev));
++		if (!(usb_state & USB_DETE_VBUS)) {
++			status = USB_EVENT_NONE;
++			otg->state = OTG_STATE_B_IDLE;
++			iphy->phy.last_event = status;
++#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
++			if (otg->gadget){
++				usb_gadget_vbus_disconnect(otg->gadget);
++				atomic_notifier_call_chain(&iphy->phy.notifier, status,
++					otg->gadget);
++			}
++#endif
++			kobject_uevent_env(&iphy->phy.dev->kobj,
++					   KOBJ_CHANGE, disconnected);
++		}
++
++		if (!(usb_state & USB_DETE_ID)) {
++			status = USB_EVENT_ID;
++			otg->state = OTG_STATE_A_IDLE;
++			iphy->phy.last_event = status;
++#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
++			if (otg->gadget) {
++				usb_gadget_vbus_connect(otg->gadget);
++			}
++#endif
++			if (otg->host) {
++				atomic_notifier_call_chain(&iphy->phy.notifier, status,
++						otg->host);
++			}
++			kobject_uevent_env(&iphy->phy.dev->kobj,
++					   KOBJ_CHANGE, connected);
++		}
++
++		if (usb_state & USB_DETE_VBUS) {
++			status = USB_EVENT_VBUS;
++			otg->state = OTG_STATE_B_PERIPHERAL;
++			iphy->phy.last_event = status;
++
++#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
++			if (otg->gadget){
++				usb_gadget_vbus_connect(otg->gadget);
++				atomic_notifier_call_chain(&iphy->phy.notifier, status,
++                                         otg->gadget);
++			}
++#endif
++			kobject_uevent_env(&iphy->phy.dev->kobj,
++					   KOBJ_CHANGE, connected);
++		}
++		iphy->usb_dete_state = usb_state;
++	}
++
++	return;
++}
++#endif
++
++static int iphy_init(struct usb_phy *x)
++{
++	struct ingenic_usb_phy *iphy = container_of(x, struct ingenic_usb_phy, phy);
++	struct inno_phy_tuning *phy_tuning = iphy->iphy_priv->phy_tuning;
++	u32 phy_tuning_num = iphy->iphy_priv->phy_tuning_num;
++	u32 usbpcr, usbpcr1;
++	unsigned long flags;
++	u32 i;
++	u8 reg;
++
++	/* USB phy clk opened. */
++	if (!IS_ERR_OR_NULL(iphy->gate_clk))
++		clk_prepare_enable(iphy->gate_clk);
++
++	spin_lock_irqsave(&iphy->phy_lock, flags);
++	usbpcr1 = inno_usbphy_read(x, CPM_USBPCR1);
++	usbpcr1 &= ~(USBPCR1_DPPULLDOWN | USBPCR1_DMPULLDOWN);
++	inno_usbphy_write(x, usbpcr1, CPM_USBPCR1);
++
++	usbpcr = inno_usbphy_read(x, CPM_USBPCR);
++	usbpcr &= ~USBPCR_IDPULLUP_MASK;
++#if (IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE))
++	usbpcr |= USBPCR_USB_MODE | USBPCR_IDPULLUP_OTG;
++#elif IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)
++	usbpcr &= ~USBPCR_USB_MODE | USBPCR_IDPULLUP_OTG;
++#endif
++	inno_usbphy_write(x, usbpcr, CPM_USBPCR);
++
++	inno_usbphy_update_bits(x, CPM_USBPCR1, USBPCR1_PORT_RST, USBPCR1_PORT_RST);
++	inno_usbphy_update_bits(x, CPM_USBPCR, USBPCR_POR, USBPCR_POR);
++	udelay(11);
++	inno_usbphy_update_bits(x, CPM_USBPCR, USBPCR_POR, 0);
++	udelay(11);
++	inno_usbphy_update_bits(x, CPM_OPCR, OPCR_USB_SPENDN, OPCR_USB_SPENDN);
++	udelay(501);
++	inno_usbphy_update_bits(x, CPM_USBPCR1, USBPCR1_PORT_RST, 0);
++	udelay(1);
++
++	usbpcr1 = inno_usbphy_read(x, CPM_USBPCR1);
++	usbpcr1 |= USBPCR1_DPPULLDOWN | USBPCR1_DMPULLDOWN;
++	inno_usbphy_write(x, usbpcr1, CPM_USBPCR1);
++
++	/* set squelch trigger point */
++	reg = usb_phy_readb(iphy->base + PHY_RX_SQU_TRI);
++	reg &= ~(0xf << 3);
++	reg |= PHY_RX_SQU_TRI_125MV << 3;
++	usb_phy_writeb(reg,iphy->base + PHY_RX_SQU_TRI);
++
++	/* set inno usb phy tuning */
++	for (i = 0; i < phy_tuning_num; i++) {
++		reg = usb_phy_readb(iphy->base + phy_tuning[i].reg_addr);
++		reg &= ~(phy_tuning[i].msk << phy_tuning[i].bit_off);
++		reg |= (phy_tuning[i].val << phy_tuning[i].bit_off);
++		usb_phy_writeb(reg, iphy->base + phy_tuning[i].reg_addr);
++	}
++
++	spin_unlock_irqrestore(&iphy->phy_lock, flags);
++	return 0;
++}
++
++static int iphy_init_x2500(struct usb_phy *x)
++{
++	struct ingenic_usb_phy *iphy = container_of(x, struct ingenic_usb_phy, phy);
++	u32 usbpcr, usbpcr1;
++	unsigned long flags;
++	u8 reg;
++
++	if (!IS_ERR_OR_NULL(iphy->gate_clk))
++		clk_prepare_enable(iphy->gate_clk);
++
++	spin_lock_irqsave(&iphy->phy_lock, flags);
++	usbpcr1 = inno_usbphy_read(x, CPM_USBPCR1);
++	usbpcr1 |= USBPCR1_DPPULLDOWN | USBPCR1_DMPULLDOWN;
++	inno_usbphy_write(x, usbpcr1, CPM_USBPCR1);
++
++	usbpcr = inno_usbphy_read(x, CPM_USBPCR);
++	usbpcr &= ~USBPCR_IDPULLUP_MASK;
++#if IS_ENABLED(CONFIG_USB_DWC2_HOST)
++	usbpcr |= USBPCR_USB_MODE | USBPCR_IDPULLUP_OTG;
++#elif IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)
++	usbpcr &= ~USBPCR_USB_MODE;
++#endif
++	inno_usbphy_write(x, usbpcr, CPM_USBPCR);
++	inno_usbphy_update_bits(x, CPM_USBPCR1, USBPCR1_PORT_RST, USBPCR1_PORT_RST);
++	inno_usbphy_update_bits(x, CPM_USBRDT, USBRDT_UTMI_RST, 0);
++	inno_usbphy_update_bits(x, CPM_USBPCR, USBPCR_POR, USBPCR_POR);
++	inno_usbphy_update_bits(x, CPM_SRBC, SRBC_USB_SR, SRBC_USB_SR);
++	udelay(5);
++	inno_usbphy_update_bits(x, CPM_USBPCR, USBPCR_POR, 0);
++	udelay(10);
++	inno_usbphy_update_bits(x, CPM_OPCR, OPCR_USB_SPENDN, OPCR_USB_SPENDN);
++	udelay(550);
++	inno_usbphy_update_bits(x, CPM_USBRDT, USBRDT_UTMI_RST, USBRDT_UTMI_RST);
++	udelay(10);
++	inno_usbphy_update_bits(x, CPM_SRBC, SRBC_USB_SR, 0);
++
++	/* set squelch trigger point */
++	reg = usb_phy_readb(iphy->base + PHY_RX_SQU_TRI);
++	reg &= ~(0xf << 3);
++	reg |= PHY_RX_SQU_TRI_125MV << 3;
++	usb_phy_writeb(reg,iphy->base + PHY_RX_SQU_TRI);
++
++
++	spin_unlock_irqrestore(&iphy->phy_lock, flags);
++	return 0;
++}
++
++static int iphy_set_suspend(struct usb_phy *x, int suspend);
++static void iphy_shutdown(struct usb_phy *x)
++{
++	struct ingenic_usb_phy *iphy = container_of(x, struct ingenic_usb_phy, phy);
++	bool vbus_detect_ctl = iphy->iphy_priv->phy_vbus_detect_ctl;
++	bool ls_fs_driver_ctl = iphy->iphy_priv->phy_ls_fs_driver_ctl;
++
++	iphy_set_suspend(x, 1);
++
++	/* VBUS voltage level detection power down. */
++	if (vbus_detect_ctl)
++		usb_phy_writeb(0x8, iphy->base + PHY_SUSPEND_LPM);
++
++	/* disable full/low speed driver at the receiver */
++	/* NOTE: it is used to reducepower consumption. */
++	if (ls_fs_driver_ctl) {
++		unsigned int reg = usb_phy_readb(iphy->base + PHY_REG_100);
++		reg &= ~(1<<6);
++		usb_phy_writeb(reg, iphy->base + PHY_REG_100);
++	}
++
++	/* USB phy clk gate. */
++	if (!IS_ERR_OR_NULL(iphy->gate_clk))
++		clk_disable_unprepare(iphy->gate_clk);
++}
++
++static int iphy_set_vbus(struct usb_phy *x, int on)
++{
++	struct ingenic_usb_phy *iphy = container_of(x, struct ingenic_usb_phy, phy);
++
++	if (!(IS_ERR_OR_NULL(iphy->gpiod_drvvbus))) {
++		printk("OTG VBUS %s\n", on ? "ON" : "OFF");
++
++#ifdef CONFIG_HALLEY5_V10_HOST_TO_4GMODULE
++		if(!(IS_ENABLED(CONFIG_DT_HALLEY5_V10) && IS_ENABLED(CONFIG_USB_DWC2_HOST)))
++#endif
++			gpiod_set_value(iphy->gpiod_drvvbus, on);
++	}
++	return 0;
++}
++
++static int iphy_set_wakeup(struct usb_phy *x, bool enabled);
++static int iphy_set_suspend(struct usb_phy *x, int suspend)
++{
++	struct ingenic_usb_phy *iphy = container_of(x, struct ingenic_usb_phy, phy);
++	unsigned long flags;
++
++	spin_lock_irqsave(&iphy->phy_lock, flags);
++
++	if(suspend){
++		/* USB phy port reset is low. */
++		inno_usbphy_update_bits(x, CPM_OPCR, USBPCR1_PORT_RST, 0);
++
++		/* USB phy enter suspend. */
++		inno_usbphy_update_bits(x, CPM_OPCR, OPCR_USB_SPENDN, 0);
++
++		udelay(10);
++	} else {
++		/* USB PHY resume. */
++		inno_usbphy_update_bits(x, CPM_OPCR, OPCR_USB_SPENDN, OPCR_USB_SPENDN);
++		udelay(501);
++
++		inno_usbphy_update_bits(x, CPM_USBPCR1, USBPCR1_PORT_RST, USBPCR1_PORT_RST);
++		udelay(2);
++
++		inno_usbphy_update_bits(x, CPM_USBPCR1, USBPCR1_PORT_RST, 0);
++		udelay(1);
++
++	}
++
++	spin_unlock_irqrestore(&iphy->phy_lock, flags);
++
++	return 0;
++}
++
++static int iphy_set_wakeup(struct usb_phy *x, bool enabled)
++{
++	struct ingenic_usb_phy *iphy = container_of(x, struct ingenic_usb_phy, phy);
++	struct usb_otg *otg = iphy->phy.otg;
++	enum usb_device_speed speed;
++	unsigned long flags;
++	int timeout;
++	unsigned int usbrdt;
++#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
++	struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)container_of(otg->gadget, struct dwc2_hsotg, gadget);
++#endif
++
++	spin_lock_irqsave(&iphy->phy_lock, flags);
++
++	if (enabled) {
++		/* Enable resume interrupt */
++		usbrdt = inno_usbphy_read(x, CPM_USBRDT);
++		usbrdt &= ~USBRDT_RESUME_SPEED_MSK;
++#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
++		if (dwc2_is_device_mode(hsotg)) {
++			speed = (otg && otg->gadget) ? otg->gadget->speed : USB_SPEED_FULL;
++			if(speed == USB_SPEED_HIGH)
++				usbrdt |= USBRDT_RESUME_SPEED_HIGH;
++			if(speed == USB_SPEED_FULL)
++				usbrdt |= USBRDT_RESUME_SPEED_FULL;
++			if(speed == USB_SPEED_LOW)
++				usbrdt |= USBRDT_RESUME_SPEED_LOW;
++		} else {
++			/* Remote wakeup device speed. */
++			usbrdt |= USBRDT_RESUME_SPEED_LOW;
++		}
++#else
++		usbrdt |= USBRDT_RESUME_SPEED_LOW;
++#endif
++		inno_usbphy_write(x, usbrdt, CPM_USBRDT);
++
++		//TODO: the function be in suspend.
++		inno_usbphy_update_bits(x, CPM_USBRDT, USBRDT_RESUME_INTEEN, USBRDT_RESUME_INTEEN);
++
++	} else {
++		/* Disable usb resume interrupt. */
++		inno_usbphy_update_bits(x, CPM_USBRDT, USBRDT_RESUME_INTEEN, 0);
++
++		/* Clear usb resume interrupt. */
++		usbrdt = inno_usbphy_read(x, CPM_USBRDT);
++		if(usbrdt & (USBRDT_RESUME_STATUS)){
++			usbrdt |= USBRDT_RESUME_INTERCLR;
++			inno_usbphy_write(x, usbrdt, CPM_USBRDT);
++			timeout = 100;
++			while(1){
++				if(timeout-- < 0){
++					printk("%s:%d resume interrupt clear failed\n", __func__, __LINE__);
++					return -EAGAIN;
++				}
++				usbrdt = inno_usbphy_read(x, CPM_USBRDT);
++				if(!(usbrdt & (USBRDT_RESUME_STATUS)))
++					break;
++			}
++		}
++
++	}
++	/* Clear usb resume interrupt bit. */
++	inno_usbphy_update_bits(x, CPM_USBRDT, USBRDT_RESUME_INTERCLR, 0);
++
++	spin_unlock_irqrestore(&iphy->phy_lock, flags);
++
++	return 0;
++}
++
++static int iphy_set_host(struct usb_otg *otg, struct usb_bus *host)
++{
++	if (!otg)
++		return -ENODEV;
++	otg->host = host;
++	return 0;
++}
++
++#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
++static int iphy_set_peripheral(struct usb_otg *otg, struct usb_gadget *gadget)
++{
++	if (!otg)
++		return -ENODEV;
++
++	otg->gadget = gadget;
++#ifdef CONFIG_USB_DWC2_DETECT_CONNECT
++	struct ingenic_usb_phy *iphy = container_of(otg->usb_phy, struct ingenic_usb_phy, phy);
++	if(gadget){
++		iphy->usb_dete_state = ~iphy->usb_dete_state;
++		schedule_delayed_work(&iphy->work, msecs_to_jiffies(100));
++	}
++#endif
++	return 0;
++}
++#else
++#define iphy_set_peripheral NULL
++#endif
++
++static int iphy_notify_connect(struct usb_phy *x,
++		enum usb_device_speed speed)
++{
++	struct ingenic_usb_phy *iphy = container_of(x, struct ingenic_usb_phy, phy);
++
++	iphy->roothub_port_speed = speed;
++
++	return 0;
++}
++
++static int usb_phy_ingenic_probe(struct platform_device *pdev)
++{
++	struct ingenic_usb_phy *iphy;
++	struct resource *res;
++	const struct of_device_id *match;
++	int ret;
++#ifdef CONFIG_USB_DWC2_DETECT_CONNECT
++	int vbus;
++#endif
++
++	iphy = (struct ingenic_usb_phy *)
++		devm_kzalloc(&pdev->dev, sizeof(*iphy), GFP_KERNEL);
++	if (!iphy)
++		return -ENOMEM;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++	iphy->base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(iphy->base))
++		return PTR_ERR(iphy->base);
++	match = of_match_node(of_matchs, pdev->dev.of_node);
++	if (!match)
++	        return -ENODEV;
++	iphy->iphy_priv = (struct ingenic_usb_phy_priv*)match->data;
++	iphy->phy.init = iphy->iphy_priv->phyinit;
++	iphy->phy.shutdown = iphy_shutdown;
++	iphy->phy.dev = &pdev->dev;
++	iphy->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, NULL);
++	if (IS_ERR(iphy->regmap)) {
++		dev_err(&pdev->dev, "failed to find regmap for usb phy %ld\n", PTR_ERR(iphy->regmap));
++		return PTR_ERR(iphy->regmap);
++	}
++
++	spin_lock_init(&iphy->phy_lock);
++
++#ifdef CONFIG_USB_DWC2_DETECT_CONNECT
++	iphy->gpiod_id = devm_gpiod_get_optional(&pdev->dev,"ingenic,id-dete", GPIOD_IN);
++	iphy->gpiod_vbus = devm_gpiod_get_optional(&pdev->dev,"ingenic,vbus-dete", GPIOD_ASIS);
++	if (iphy->gpiod_id || iphy->gpiod_vbus) {
++		INIT_DELAYED_WORK(&iphy->work, usb_dete_work);
++	}
++
++
++	if (!IS_ERR_OR_NULL(iphy->gpiod_id)) {
++		ret = devm_request_irq(&pdev->dev,
++				gpiod_to_irq(iphy->gpiod_id),
++				usb_dete_irq_handler,
++				IRQF_TRIGGER_RISING|IRQF_TRIGGER_FALLING|IRQF_ONESHOT,
++				"id_dete",
++				(void *)iphy);
++		if (ret)
++			return ret;
++	} else {
++		iphy->usb_dete_state |= USB_DETE_ID;
++		iphy->gpiod_id = NULL;
++	}
++
++	if (!IS_ERR_OR_NULL(iphy->gpiod_vbus)) {
++		ret = devm_request_irq(&pdev->dev,
++				gpiod_to_irq(iphy->gpiod_vbus),
++				usb_dete_irq_handler,
++				IRQF_TRIGGER_RISING|IRQF_TRIGGER_FALLING|IRQF_ONESHOT,
++				"vbus_dete",
++				(void *)iphy);
++		if (ret)
++			return ret;
++		vbus = gpiod_get_value_cansleep(iphy->gpiod_vbus);
++		if(vbus)
++			iphy->usb_dete_state |= USB_DETE_VBUS;
++		else
++			iphy->usb_dete_state &= ~USB_DETE_VBUS;
++	} else {
++		iphy->usb_dete_state &= ~USB_DETE_VBUS;
++		iphy->gpiod_vbus = NULL;
++	}
++#else
++	iphy->usb_dete_state |= USB_DETE_ID;
++	iphy->gpiod_id = NULL;
++
++	iphy->usb_dete_state &= ~USB_DETE_VBUS;
++	iphy->gpiod_vbus = NULL;
++#endif
++	iphy->gpiod_drvvbus = devm_gpiod_get_optional(&pdev->dev,"ingenic,drvvbus", GPIOD_OUT_LOW);
++	if (IS_ERR_OR_NULL(iphy->gpiod_drvvbus))
++		iphy->gpiod_drvvbus = NULL;
++	iphy->phy.set_vbus = iphy_set_vbus;
++	iphy->phy.set_suspend = iphy_set_suspend;
++	if (iphy->iphy_priv->phy_remote_wakeup) {
++		iphy->phy.set_wakeup = iphy_set_wakeup;
++	}
++
++	iphy->phy.notify_connect = iphy_notify_connect;
++	iphy->phy.otg = devm_kzalloc(&pdev->dev, sizeof(*iphy->phy.otg),
++			GFP_KERNEL);
++	iphy->phy.io_ops = devm_kzalloc(&pdev->dev, sizeof(*iphy->phy.io_ops),
++			GFP_KERNEL);
++
++	if (!iphy->phy.otg)
++		return -ENOMEM;
++
++	iphy->phy.type			= USB_PHY_TYPE_USB2;
++	iphy->phy.otg->state		= OTG_STATE_UNDEFINED;
++	iphy->phy.otg->usb_phy		= &iphy->phy;
++	iphy->phy.otg->set_host		= iphy_set_host;
++	iphy->phy.otg->set_peripheral	= iphy_set_peripheral;
++	iphy->phy.io_ops->read		= inno_usbphy_read;
++	iphy->phy.io_ops->write		= inno_usbphy_write;
++
++	iphy->gate_clk = devm_clk_get(&pdev->dev, "gate_usbphy");
++	if (IS_ERR_OR_NULL(iphy->gate_clk)){
++		iphy->gate_clk = NULL;
++		dev_err(&pdev->dev, "cannot get usbphy clock !\n");
++		return -ENODEV;
++	}
++
++	ret = usb_add_phy_dev(&iphy->phy);
++	if (ret) {
++		dev_err(&pdev->dev, "can't register transceiver, err: %d\n",
++				ret);
++		return ret;
++	}
++	platform_set_drvdata(pdev, iphy);
++	pr_info("inno phy probe success\n");
++	return 0;
++}
++
++static int usb_phy_ingenic_remove(struct platform_device *pdev)
++{
++	struct ingenic_usb_phy *iphy = platform_get_drvdata(pdev);
++
++	usb_remove_phy(&iphy->phy);
++	return 0;
++}
++
++static int usb_gpio_suspend(struct platform_device *dev, pm_message_t state)
++{
++
++	return 0;
++}
++
++static int usb_gpio_resume(struct platform_device *dev)
++{
++#ifdef CONFIG_USB_DWC2_DETECT_CONNECT
++	struct ingenic_usb_phy *iphy = platform_get_drvdata(dev);
++
++
++	schedule_delayed_work(&iphy->work, msecs_to_jiffies(100));
++#endif
++
++	return 0;
++}
++
++/* for x1600 */
++struct ingenic_usb_phy_priv usb_phy_x1600_priv = {
++	.phyinit = iphy_init,
++	.phy_tuning_num = 8,
++	.phy_tuning = {
++		/* set 45ohm HS ODT value */
++		[0].reg_addr = 0x11c,
++		[0].msk = 0x1f,
++		[0].bit_off = 0,
++		[0].val = 0x1c,
++
++		/* always enable pre-emphasis */
++		[1].reg_addr = 0x30,
++		[1].msk = 0x7,
++		[1].bit_off = 0,
++		[1].val = 0x7,
++
++		/* Tx HS pre_emphasize strength */
++		[2].reg_addr = 0x40,
++		[2].msk = 0x7,
++		[2].bit_off = 3,
++		[2].val = 0x7,
++
++		/* set A session valid reference tuning */
++		[3].reg_addr = 0x10c,
++		[3].msk = 0x7,
++		[3].bit_off = 0,
++		[3].val = 0x5,
++
++		/* set B session valid reference tuning */
++		[4].reg_addr = 0x10c,
++		[4].msk = 0x7,
++		[4].bit_off = 3,
++		[4].val = 0x5,
++
++		/* set vbus valid reference tuning */
++		[5].reg_addr = 0x110,
++		[5].msk = 0x7,
++		[5].bit_off = 0,
++		[5].val = 0x5,
++
++		/* set session end reference tuning */
++		[6].reg_addr = 0x110,
++		[6].msk = 0x7,
++		[6].bit_off = 3,
++		[6].val = 0x5,
++
++		/* enable control of full/low speed driver at the receiver */
++		/* NOTE: Set to 0 during suspend, it is used to reducepower consumption. Restore here. */
++		[7].reg_addr = 0x100,
++		[7].msk = 0x1,
++		[7].bit_off = 6,
++		[7].val = 0x1,
++	},
++	.phy_remote_wakeup = 1,
++	.phy_vbus_detect_ctl = 1,
++	.phy_ls_fs_driver_ctl = 1,
++};
++
++/* for x2500 */
++struct ingenic_usb_phy_priv usb_phy_x2500_priv = {
++	.phyinit = iphy_init_x2500,
++	.phy_tuning_num = 0,
++	.phy_remote_wakeup = 0,
++	.phy_vbus_detect_ctl = 0,
++	.phy_ls_fs_driver_ctl = 0,
++};
++
++/* usb_phy_common for x2000/x2000E x2100 m300 */
++struct ingenic_usb_phy_priv usb_phy_common_priv = {
++	.phyinit = iphy_init,
++	.phy_tuning_num = 0,
++	.phy_remote_wakeup = 0,
++	.phy_vbus_detect_ctl = 1,
++	.phy_ls_fs_driver_ctl = 0,
++};
++
++static const struct of_device_id of_matchs[] = {
++	{ .compatible = "ingenic,innophy",.data = (void*)&usb_phy_common_priv},
++	{ .compatible = "ingenic,innophy-x1600",.data = (void*)&usb_phy_x1600_priv},
++	{ .compatible = "ingenic,innophy-x2500",.data = (void*)&usb_phy_x2500_priv},
++	{ },
++};
++MODULE_DEVICE_TABLE(of, ingenic_xceiv_dt_ids);
++
++static struct platform_driver usb_phy_ingenic_driver = {
++	.probe		= usb_phy_ingenic_probe,
++	.remove		= usb_phy_ingenic_remove,
++	.suspend	= usb_gpio_suspend,
++	.resume		= usb_gpio_resume,
++	.driver		= {
++		.name	= "usb_phy",
++		.of_match_table = of_matchs,
++	},
++};
++
++static int __init usb_phy_ingenic_init(void)
++{
++	return platform_driver_register(&usb_phy_ingenic_driver);
++}
++subsys_initcall(usb_phy_ingenic_init);
++
++static void __exit usb_phy_ingenic_exit(void)
++{
++	platform_driver_unregister(&usb_phy_ingenic_driver);
++}
++module_exit(usb_phy_ingenic_exit);
+diff --git a/drivers/usb/phy/phy-ingenic-x1000.c b/drivers/usb/phy/phy-ingenic-x1000.c
+new file mode 100644
+index 000000000..81b90e6f4
+--- /dev/null
++++ b/drivers/usb/phy/phy-ingenic-x1000.c
+@@ -0,0 +1,66 @@
++#include <linux/delay.h>
++#include "phy-ingenic.h"
++
++#define CPM_USBPCR    (0x3c)
++#define CPM_USBRDT    (0x40)
++#define CPM_USBVBFIL  (0x44)
++#define CPM_USBPCR1   (0x48)
++
++#define CPM_SRBC      (0xc4)
++#define CPM_OPCR      (0x24)
++
++#define OPCR_SPENDN0_BIT			7
++#define OPCR_GATE_USBPHY_CLK_BIT	23
++#define SRBC_USB_SR					12
++
++static int x1000_priv_data_init(struct usb_phy_data *usb_phy)
++{
++	/* reset usb */
++	usb_cpm_set_bit(usb_phy, SRBC_USB_SR, CPM_SRBC);
++	udelay(10);
++	usb_cpm_clear_bit(usb_phy, SRBC_USB_SR, CPM_SRBC);
++
++	usb_cpm_set_bit(usb_phy, OPCR_SPENDN0_BIT, CPM_OPCR);
++
++	return 0;
++}
++
++static int x1000_phy_init(struct usb_phy_data *usb_phy)
++{
++	/* vbus signal always valid, id pin always pullup */
++	usb_cpm_writel(usb_phy, 0xA3C919FF, CPM_USBPCR);
++	usb_cpm_writel(usb_phy, 0x0D280000, CPM_USBPCR1);
++	udelay(500);
++#ifdef CONFIG_USB_DWC2_EXT_VBUS_DETECT
++	usb_cpm_writel(usb_phy, 0xA38919FF, CPM_USBPCR);
++#else
++	usb_cpm_writel(usb_phy, 0xA20919FF, CPM_USBPCR);
++#endif
++	usb_cpm_writel(usb_phy, 0x0D080000, CPM_USBPCR1);
++	udelay(500);
++
++	/* jitter filter */
++	usb_cpm_writel(usb_phy, 0x00FF0080, CPM_USBVBFIL);
++
++	/* reset detect time */
++	usb_cpm_writel(usb_phy, 0x02000096, CPM_USBRDT);
++
++	return 0;
++}
++
++static int x1000_phy_set_wakeup(struct usb_phy_data *usb_phy, bool enabled)
++{
++	if (enabled)
++		usb_cpm_clear_bit(usb_phy, OPCR_SPENDN0_BIT, CPM_OPCR);
++	else
++		usb_cpm_set_bit(usb_phy, OPCR_SPENDN0_BIT, CPM_OPCR);
++
++	return 0;
++}
++
++struct usb_phy_priv usb_phy_x1000_priv = {
++	.priv_data_init = x1000_priv_data_init,
++
++	.phy_init = x1000_phy_init,
++	.phy_set_wakeup = x1000_phy_set_wakeup,
++};
+\ No newline at end of file
+diff --git a/drivers/usb/phy/phy-ingenic-x1600.c b/drivers/usb/phy/phy-ingenic-x1600.c
+new file mode 100644
+index 000000000..5b3017702
+--- /dev/null
++++ b/drivers/usb/phy/phy-ingenic-x1600.c
+@@ -0,0 +1,139 @@
++#include <linux/delay.h>
++#include "phy-ingenic.h"
++
++#define CPM_USBPCR                      (0x3C)
++#define CPM_USBRDT                      (0x40)
++#define CPM_USBVBFIL                    (0x44)
++#define CPM_USBPCR1                     (0x48)
++
++#define CPM_SRBC                        (0xC4)
++#define CPM_OPCR                        (0x24)
++
++#define OPCR_SPENDN0_BIT			7
++#define OPCR_GATE_USBPHY_CLK_BIT	23
++#define SRBC_USB_SR					12
++
++#define USBRDT_RESUME_IRQ_ENABLE			31
++#define USBRDT_RESUME_CLEAR_IRQ				30
++#define USBRDT_RESUME_STATUS				27
++
++static int x1600_priv_data_init(struct usb_phy_data *usb_phy)
++{
++	/* reset usb */
++	usb_cpm_set_bit(usb_phy, SRBC_USB_SR, CPM_SRBC);
++	udelay(10);
++	usb_cpm_clear_bit(usb_phy, SRBC_USB_SR, CPM_SRBC);
++
++	usb_cpm_set_bit(usb_phy, OPCR_SPENDN0_BIT, CPM_OPCR);
++
++	return 0;
++}
++
++static int x1600_phy_init(struct usb_phy_data *usb_phy)
++{
++	unsigned int value;
++
++	/* vbus signal always valid, id pin always pullup */
++	usb_cpm_writel(usb_phy, 0x00200000, CPM_USBPCR1);
++	usb_cpm_writel(usb_phy, 0x80400000, CPM_USBPCR);
++	udelay(500);
++	usb_cpm_writel(usb_phy, 0x80000000, CPM_USBPCR);
++	usb_cpm_writel(usb_phy, 0x70000000, CPM_USBPCR1);
++	udelay(500);
++
++	/* always enable pre-emphasis */
++	value = usb_phy_readl(usb_phy, 0x30);
++	// value &= ~(0x7 << 0);
++	value |= 0x7 << 0;
++	usb_phy_writel(usb_phy, value, 0x30);
++
++	/* Tx HS pre_emphasize strength configure */
++	value = usb_phy_readl(usb_phy, 0x40);
++	// value &= ~(0x7 << 3);
++	value |= 0x7 << 3;
++	usb_phy_writel(usb_phy, value, 0x40);
++
++	/* Vbus 5V mode */
++	value = usb_phy_readl(usb_phy, 0x10C);
++	value &= ~((0x7 << 0) | (0x7 << 3));
++	value |= ((0x5 << 0) | (0x5 << 3));
++	usb_phy_writel(usb_phy, value, 0x10C);
++
++	/* Vbus 5V mode */
++	value = usb_phy_readl(usb_phy, 0x110);
++	value &= ~((0x7 << 0) | (0x7 << 3));
++	value |= ((0x5 << 0) | (0x5 << 3));
++	usb_phy_writel(usb_phy, value, 0x110);
++
++#ifdef CONFIG_USB_DWC2_EXT_VBUS_DETECT
++	/* VBUS voltage level detection power down. */
++	value = usb_phy_readl(usb_phy, 0x108);
++	value |= 0x1 << 3;
++	usb_phy_writel(usb_phy, value, 0x108);
++#endif
++
++	return 0;
++}
++
++static int x1600_phy_set_wakeup(struct usb_phy_data *usb_phy, bool enabled)
++{
++	unsigned long value;
++
++	if (enabled) {
++#ifndef CONFIG_USB_DWC2_EXT_VBUS_DETECT
++		/* VBUS voltage level detection power down. */
++		value = usb_phy_readl(usb_phy, 0x108);
++		value |= 1 << 3;
++		usb_phy_writel(usb_phy, value, 0x108);
++#endif
++
++		/* disable full/low speed driver at the receiver */
++		value = usb_phy_readl(usb_phy, 0x100);
++		value &= ~(1 << 6);
++		usb_phy_writel(usb_phy, value, 0x100);
++
++		usb_cpm_clear_bit(usb_phy, OPCR_SPENDN0_BIT, CPM_OPCR);
++		if (usb_phy->usb_wakeup) {
++			usb_cpm_clear_bit(usb_phy, USBRDT_RESUME_CLEAR_IRQ, CPM_USBRDT);
++			usb_cpm_set_bit(usb_phy, USBRDT_RESUME_IRQ_ENABLE, CPM_USBRDT);
++		}
++	} else {
++		if (usb_phy->usb_wakeup)
++			usb_cpm_clear_bit(usb_phy, USBRDT_RESUME_IRQ_ENABLE, CPM_USBRDT);
++		usb_cpm_set_bit(usb_phy, OPCR_SPENDN0_BIT, CPM_OPCR);
++
++		/* enable full/low speed driver at the receiver */
++		value = usb_phy_readl(usb_phy, 0x100);
++		value |= 1 << 6;
++		usb_phy_writel(usb_phy, value, 0x100);
++
++#ifndef CONFIG_USB_DWC2_EXT_VBUS_DETECT
++		/* VBUS voltage level detection power on. */
++		value = usb_phy_readl(usb_phy, 0x108);
++		value &= ~(1 << 3);
++		usb_phy_writel(usb_phy, value, 0x108);
++#endif
++	}
++
++	return 0;
++}
++
++static int x1600_phy_get_wakeup(struct usb_phy_data *usb_phy)
++{
++	if (usb_phy->usb_wakeup) {
++		if (usb_cpm_test_bit(usb_phy, USBRDT_RESUME_STATUS,CPM_USBRDT)) {
++			usb_cpm_set_bit(usb_phy, USBRDT_RESUME_CLEAR_IRQ, CPM_USBRDT);
++			return 1;
++		}
++	}
++
++	return 0;
++}
++
++struct usb_phy_priv usb_phy_x1600_priv = {
++	.priv_data_init = x1600_priv_data_init,
++
++	.phy_init = x1600_phy_init,
++	.phy_set_wakeup = x1600_phy_set_wakeup,
++	.phy_get_wakeup = x1600_phy_get_wakeup,
++};
+diff --git a/drivers/usb/phy/phy-ingenic-x2000.c b/drivers/usb/phy/phy-ingenic-x2000.c
+new file mode 100644
+index 000000000..08446648e
+--- /dev/null
++++ b/drivers/usb/phy/phy-ingenic-x2000.c
+@@ -0,0 +1,85 @@
++#include <linux/delay.h>
++#include "phy-ingenic.h"
++
++#define CPM_USBPCR     0x3C
++#define CPM_USBRDT     0x40
++#define CPM_USBVBFIL   0x44
++#define CPM_USBPCR1    0x48
++
++#define CPM_SRBC    0xC4
++#define CPM_OPCR    0x24
++
++#define OPCR_SPENDN0_BIT			7
++#define OPCR_GATE_USBPHY_CLK_BIT	23
++#define SRBC_USB_SR					12
++
++#define USBRDT_RESUME_IRQ_ENABLE			31
++#define USBRDT_RESUME_CLEAR_IRQ				30
++#define USBRDT_RESUME_STATUS				27
++
++static int x2000_priv_data_init(struct usb_phy_data *usb_phy)
++{
++	usb_cpm_set_bit(usb_phy, SRBC_USB_SR, CPM_SRBC);
++	udelay(10);
++	usb_cpm_clear_bit(usb_phy, SRBC_USB_SR, CPM_SRBC);
++
++	usb_cpm_set_bit(usb_phy, OPCR_SPENDN0_BIT, CPM_OPCR);
++	return 0;
++}
++
++static int x2000_phy_init(struct usb_phy_data *usb_phy)
++{
++	unsigned int value;
++
++	/* vbus signal always valid, id pin always pullup */
++	usb_cpm_writel(usb_phy, 0x00200000, CPM_USBPCR1);
++	usb_cpm_writel(usb_phy, 0x80400000, CPM_USBPCR);
++	udelay(800);
++	usb_cpm_writel(usb_phy, 0x80000000, CPM_USBPCR);
++	usb_cpm_writel(usb_phy, 0x70000000, CPM_USBPCR1);
++	udelay(800);
++
++	/* TX HS driver strength configure */
++	value = usb_phy_readl(usb_phy, 0x40);
++	value |= 0x7 << 3;
++	usb_phy_writel(usb_phy, value, 0x40);
++
++	return 0;
++}
++
++static int x2000_phy_set_wakeup(struct usb_phy_data *usb_phy, bool enabled)
++{
++	if (enabled) {
++		usb_cpm_clear_bit(usb_phy, OPCR_SPENDN0_BIT, CPM_OPCR);
++		if (usb_phy->usb_wakeup) {
++			usb_cpm_clear_bit(usb_phy, USBRDT_RESUME_CLEAR_IRQ, CPM_USBRDT);
++			usb_cpm_set_bit(usb_phy, USBRDT_RESUME_IRQ_ENABLE, CPM_USBRDT);
++		}
++	} else {
++		if (usb_phy->usb_wakeup)
++			usb_cpm_clear_bit(usb_phy, USBRDT_RESUME_IRQ_ENABLE, CPM_USBRDT);
++		usb_cpm_set_bit(usb_phy, OPCR_SPENDN0_BIT, CPM_OPCR);
++	}
++
++	return 0;
++}
++
++static int x2000_phy_get_wakeup(struct usb_phy_data *usb_phy)
++{
++	if (usb_phy->usb_wakeup) {
++		if (usb_cpm_test_bit(usb_phy, USBRDT_RESUME_STATUS,CPM_USBRDT)) {
++			usb_cpm_set_bit(usb_phy, USBRDT_RESUME_CLEAR_IRQ, CPM_USBRDT);
++			return 1;
++		}
++	}
++
++	return 0;
++}
++
++struct usb_phy_priv usb_phy_x2000_priv = {
++	.priv_data_init = x2000_priv_data_init,
++
++	.phy_init = x2000_phy_init,
++	.phy_set_wakeup = x2000_phy_set_wakeup,
++	.phy_get_wakeup = x2000_phy_get_wakeup,
++};
+\ No newline at end of file
+diff --git a/drivers/usb/phy/phy-ingenic-x2500.c b/drivers/usb/phy/phy-ingenic-x2500.c
+new file mode 100644
+index 000000000..636ce2060
+--- /dev/null
++++ b/drivers/usb/phy/phy-ingenic-x2500.c
+@@ -0,0 +1,117 @@
++#include <linux/delay.h>
++#include "phy-ingenic.h"
++
++#define CPM_USBPCR                      0x3C
++#define CPM_USBRDT                      0x40
++#define CPM_USBVBFIL                    0x44
++#define CPM_USBPCR1                     0x48
++
++#define CPM_SRBC                        (0xC4)
++#define CPM_OPCR                        (0x24)
++
++#define OPCR_SPENDN0_BIT			7
++#define OPCR_GATE_USBPHY_CLK_BIT	23
++#define SRBC_USB_SR					12
++
++#define USBRDT_RESUME_IRQ_ENABLE			31
++#define USBRDT_RESUME_CLEAR_IRQ				30
++#define USBRDT_RESUME_STATUS				27
++
++static int x2500_priv_data_init(struct usb_phy_data *usb_phy)
++{
++	/* reset usb */
++	usb_cpm_clear_bit(usb_phy, 27, CPM_USBRDT);
++	usb_cpm_set_bit(usb_phy, SRBC_USB_SR, CPM_SRBC);
++	udelay(10);
++	usb_cpm_set_bit(usb_phy, OPCR_SPENDN0_BIT, CPM_OPCR);
++	udelay(550);
++	usb_cpm_set_bit(usb_phy, 27, CPM_USBRDT);
++	udelay(10);
++	usb_cpm_clear_bit(usb_phy, SRBC_USB_SR, CPM_SRBC);
++
++
++	return 0;
++}
++
++static int x2500_phy_init(struct usb_phy_data *usb_phy)
++{
++	unsigned int value;
++
++	/* vbus signal always valid, id pin always pullup */
++	usb_cpm_writel(usb_phy, 0x00200000, CPM_USBPCR1);
++	usb_cpm_writel(usb_phy, 0x80400000, CPM_USBPCR);
++	udelay(800);
++	usb_cpm_writel(usb_phy, 0x80000000, CPM_USBPCR);
++	usb_cpm_writel(usb_phy, 0x70000000, CPM_USBPCR1);
++	udelay(800);
++
++	/* TX HS driver strength configure */
++	value = usb_phy_readl(usb_phy, 0x40);
++	value |= 0x7 << 3;
++	usb_phy_writel(usb_phy, value, 0x40);
++
++	return 0;
++}
++
++static int x2500_phy_set_wakeup(struct usb_phy_data *usb_phy, bool enabled)
++{
++	unsigned long value;
++
++	if (enabled) {
++#ifndef CONFIG_USB_DWC2_EXT_VBUS_DETECT
++		/* VBUS voltage level detection power down. */
++		value = usb_phy_readl(usb_phy, 0x108);
++		value |= 1 << 3;
++		usb_phy_writel(usb_phy, value, 0x108);
++#endif
++
++		/* disable full/low speed driver at the receiver */
++		value = usb_phy_readl(usb_phy, 0x100);
++		value &= ~(1 << 6);
++		usb_phy_writel(usb_phy, value, 0x100);
++
++		usb_cpm_clear_bit(usb_phy, OPCR_SPENDN0_BIT, CPM_OPCR);
++		if (usb_phy->usb_wakeup) {
++			usb_cpm_clear_bit(usb_phy, USBRDT_RESUME_CLEAR_IRQ, CPM_USBRDT);
++			usb_cpm_set_bit(usb_phy, USBRDT_RESUME_IRQ_ENABLE, CPM_USBRDT);
++		}
++	} else {
++		if (usb_phy->usb_wakeup)
++			usb_cpm_clear_bit(usb_phy, USBRDT_RESUME_IRQ_ENABLE, CPM_USBRDT);
++		usb_cpm_set_bit(usb_phy, OPCR_SPENDN0_BIT, CPM_OPCR);
++
++		/* enable full/low speed driver at the receiver */
++		value = usb_phy_readl(usb_phy, 0x100);
++		value |= 1 << 6;
++		usb_phy_writel(usb_phy, value, 0x100);
++
++#ifndef CONFIG_USB_DWC2_EXT_VBUS_DETECT
++		/* VBUS voltage level detection power on. */
++		value = usb_phy_readl(usb_phy, 0x108);
++		value &= ~(1 << 3);
++		usb_phy_writel(usb_phy, value, 0x108);
++#endif
++	}
++
++	return 0;
++}
++
++static int x2500_phy_get_wakeup(struct usb_phy_data *usb_phy)
++{
++	if (usb_phy->usb_wakeup) {
++		if (usb_cpm_test_bit(usb_phy, USBRDT_RESUME_STATUS,CPM_USBRDT)) {
++			usb_cpm_set_bit(usb_phy, USBRDT_RESUME_CLEAR_IRQ, CPM_USBRDT);
++			return 1;
++		}
++	}
++
++	return 0;
++}
++
++struct usb_phy_priv usb_phy_x2500_priv = {
++	.priv_data_init = x2500_priv_data_init,
++
++	.phy_init = x2500_phy_init,
++	.phy_set_wakeup = x2500_phy_set_wakeup,
++	.phy_get_wakeup = x2500_phy_get_wakeup,
++};
+diff --git a/drivers/usb/phy/phy-ingenic.c b/drivers/usb/phy/phy-ingenic.c
+new file mode 100644
+index 000000000..370fa853c
+--- /dev/null
++++ b/drivers/usb/phy/phy-ingenic.c
+@@ -0,0 +1,639 @@
++
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/gpio/consumer.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/clk.h>
++#include <linux/usb/role.h>
++#include <soc/cpm.h>
++
++#include "phy-ingenic.h"
++
++/*
++ * This driver relies on "both edges" triggering.  VBUS has 100 msec to
++ * stabilize, so the peripheral controller driver may need to cope with
++ * some bouncing due to current surges (e.g. charging local capacitance)
++ * and contact chatter.
++ *
++ * REVISIT in desperate straits, toggling between rising and falling
++ * edges might be workable.
++ */
++#define VBUS_IRQ_FLAGS \
++	(IRQF_SHARED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)
++
++#define ID_IRQ_FLAGS \
++	(IRQF_SHARED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)
++
++#define WAKEUP_IRQ_FLAGS \
++	(IRQF_SHARED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)
++
++#define FORCE_NONE 0
++#define FORCE_DEVICE 1
++#define FORCE_HOST 2
++
++static const struct of_device_id of_matchs[] = {
++	{ .compatible = "ingenic,usbphy-x1000", .data = (void*)&usb_phy_x1000_priv},
++	{ .compatible = "ingenic,usbphy-x1600", .data = (void*)&usb_phy_x1600_priv},
++	{ .compatible = "ingenic,usbphy-x2000", .data = (void*)&usb_phy_x2000_priv},
++	{ .compatible = "ingenic,usbphy-m300", .data = (void*)&usb_phy_x2000_priv},
++	{ .compatible = "ingenic,usbphy-x2500", .data = (void*)&usb_phy_x2500_priv},
++	{ },
++};
++
++static int common_phy_init(struct usb_phy *phy)
++{
++	int ret = 0;
++	struct usb_phy_data *usb_phy = container_of(phy, struct usb_phy_data, phy);
++
++	if (usb_phy->gate_clk)
++		clk_prepare_enable(usb_phy->gate_clk);
++
++	usleep_range(5000, 5000);
++
++	if (usb_phy->phy_priv->phy_init)
++		ret = usb_phy->phy_priv->phy_init(usb_phy);
++
++	return ret;
++}
++
++static void common_phy_shutdown(struct usb_phy *phy)
++{
++	struct usb_phy_data *usb_phy = container_of(phy, struct usb_phy_data, phy);
++
++	if (usb_phy->phy_priv->phy_shutdown)
++		usb_phy->phy_priv->phy_shutdown(usb_phy);
++
++	if (usb_phy->gate_clk)
++		clk_disable_unprepare(usb_phy->gate_clk);
++}
++
++static int common_phy_set_suspend(struct usb_phy *phy, int suspend)
++{
++	int ret = 0;
++	struct usb_phy_data *usb_phy = container_of(phy, struct usb_phy_data, phy);
++
++	if (usb_phy->phy_priv->phy_set_suspend)
++		ret = usb_phy->phy_priv->phy_set_suspend(usb_phy, suspend);
++
++	return ret;
++}
++
++static int common_phy_set_wakeup(struct usb_phy *phy, bool enabled)
++{
++	struct usb_phy_data *usb_phy = container_of(phy, struct usb_phy_data, phy);
++
++	if (enabled){
++		if (usb_phy->phy_priv->phy_set_wakeup)
++			usb_phy->phy_priv->phy_set_wakeup(usb_phy, 1);
++
++		/* change usb switch to gpio */
++		if (usb_phy->switch_gpiod)
++			gpiod_set_value(usb_phy->switch_gpiod, 1);
++
++		/* enable usb wakeup irq */
++		if (usb_phy->wakeup_gpiod) {
++#ifdef TEST_USB_WAKEUP_FLAG
++			usb_phy->wakeup_flag = 0;
++#endif
++			enable_irq(usb_phy->wakeup_irq);
++			enable_irq_wake(usb_phy->wakeup_irq);
++		}
++	} else {
++		/* disable usb wakeup irq */
++		if (usb_phy->wakeup_gpiod) {
++			disable_irq_wake(usb_phy->wakeup_irq);
++			disable_irq(usb_phy->wakeup_irq);
++		}
++
++		/* change usb switch to phy */
++		if (usb_phy->switch_gpiod)
++			gpiod_set_value(usb_phy->switch_gpiod, 0);
++
++		if (usb_phy->phy_priv->phy_set_wakeup)
++			usb_phy->phy_priv->phy_set_wakeup(usb_phy, 0);
++	}
++
++	return 0;
++}
++
++static int common_phy_get_wakeup(struct usb_phy *phy)
++{
++	struct usb_phy_data *usb_phy = container_of(phy, struct usb_phy_data, phy);
++	int ret = 0;
++
++	if (usb_phy->phy_priv->phy_get_wakeup)
++		ret = usb_phy->phy_priv->phy_get_wakeup(usb_phy);
++
++#ifdef TEST_USB_WAKEUP_FLAG
++	if (usb_phy->wakeup_flag) {
++		usb_phy->wakeup_flag = 0;
++		ret = 1;
++	}
++#endif
++
++	return ret;
++}
++
++static irqreturn_t usb_wakeup_irq_handler(int irq, void *data)
++{
++#ifdef TEST_USB_WAKEUP_FLAG
++	struct usb_phy_data *usb_phy = (struct usb_phy_data *)data;
++	usb_phy->wakeup_flag = 1;
++#endif
++
++	return IRQ_HANDLED;
++}
++
++static int is_vbus_powered(struct usb_phy_data *usb_phy)
++{
++	return gpiod_get_value(usb_phy->vbus_gpiod);
++}
++
++static int is_id_host(struct usb_phy_data *usb_phy)
++{
++	return gpiod_get_value(usb_phy->id_gpiod);
++}
++
++static void gpio_vbus_work(struct work_struct *work)
++{
++	struct usb_phy_data *usb_phy =
++		container_of(work, struct usb_phy_data, vbus_work.work);
++	int status, vbus;
++
++	if (!usb_phy->phy.otg->gadget)
++		return;
++
++	vbus = is_vbus_powered(usb_phy);
++	if ((vbus ^ usb_phy->vbus) == 0)
++		return;
++	usb_phy->vbus = vbus;
++
++	/* Peripheral controllers which manage the pullup themselves won't have
++	 * a pullup GPIO configured here.  If it's configured here, we'll do
++	 * what isp1301_omap::b_peripheral() does and enable the pullup here...
++	 * although that may complicate usb_gadget_{,dis}connect() support.
++	 */
++
++	if (vbus) {
++		status = USB_EVENT_VBUS;
++		usb_phy->phy.otg->state = OTG_STATE_B_PERIPHERAL;
++		usb_phy->phy.last_event = status;
++		usb_gadget_vbus_connect(usb_phy->phy.otg->gadget);
++
++		atomic_notifier_call_chain(&usb_phy->phy.notifier,
++					   status, usb_phy->phy.otg->gadget);
++		usb_phy_set_event(&usb_phy->phy, USB_EVENT_ENUMERATED);
++	} else {
++		usb_gadget_vbus_disconnect(usb_phy->phy.otg->gadget);
++		status = USB_EVENT_NONE;
++		usb_phy->phy.otg->state = OTG_STATE_B_IDLE;
++		usb_phy->phy.last_event = status;
++
++		atomic_notifier_call_chain(&usb_phy->phy.notifier,
++					   status, usb_phy->phy.otg->gadget);
++		usb_phy_set_event(&usb_phy->phy, USB_EVENT_NONE);
++	}
++}
++
++/* VBUS change IRQ handler */
++static irqreturn_t gpio_vbus_irq(int irq, void *data)
++{
++	struct platform_device *pdev = data;
++	struct usb_phy_data *usb_phy = platform_get_drvdata(pdev);
++	struct usb_otg *otg = usb_phy->phy.otg;
++
++	dev_dbg(&pdev->dev, "VBUS %s (gadget: %s)\n",
++		is_vbus_powered(usb_phy) ? "supplied" : "inactive",
++		otg->gadget ? otg->gadget->name : "none");
++
++	if (otg->gadget)
++		schedule_delayed_work(&usb_phy->vbus_work, msecs_to_jiffies(100));
++
++	return IRQ_HANDLED;
++}
++
++static void gpio_id_work(struct work_struct *work)
++{
++	struct usb_phy_data *usb_phy =
++		container_of(work, struct usb_phy_data, id_work.work);
++	const struct software_node *swnode;
++	struct fwnode_handle *fwnode;
++	struct usb_role_switch *role_sw;
++	int id;
++
++	id = is_id_host(usb_phy);
++	if ((id ^ usb_phy->id) == 0)
++		return;
++	usb_phy->id = id;
++
++	swnode = software_node_find_by_name(NULL, "ingenic-usb-sw");
++	if (!swnode)
++		return;
++
++	fwnode = software_node_fwnode(swnode);
++	role_sw = usb_role_switch_find_by_fwnode(fwnode);
++	fwnode_handle_put(fwnode);
++
++	if (role_sw) {
++		usb_role_switch_set_role(role_sw, id ? USB_ROLE_HOST : USB_ROLE_DEVICE);
++		usb_role_switch_put(role_sw);
++	}
++
++}
++
++/* ID change IRQ handler */
++static irqreturn_t gpio_id_irq(int irq, void *data)
++{
++	struct platform_device *pdev = data;
++	struct usb_phy_data *usb_phy = platform_get_drvdata(pdev);
++
++	dev_dbg(&pdev->dev, "ID %s\n", is_id_host(usb_phy) ? "host" : "device");
++
++	schedule_delayed_work(&usb_phy->id_work, msecs_to_jiffies(100));
++
++	return IRQ_HANDLED;
++}
++
++static int usb_phy_set_vbus(struct usb_phy *phy, int on)
++{
++	struct usb_phy_data *usb_phy = container_of(phy, struct usb_phy_data, phy);
++
++	dev_dbg(usb_phy->dev, "OTG VBUS %s\n", on ? "ON" : "OFF");
++
++	if (usb_phy->drvvbus_gpiod)
++		gpiod_set_value(usb_phy->drvvbus_gpiod, on);
++	return 0;
++}
++
++/* bind/unbind the peripheral controller */
++static int usb_phy_set_peripheral(struct usb_otg *otg,
++					struct usb_gadget *gadget)
++{
++	struct usb_phy_data *usb_phy;
++	struct platform_device *pdev;
++
++	usb_phy = container_of(otg->usb_phy, struct usb_phy_data, phy);
++	pdev = to_platform_device(usb_phy->dev);
++
++	if (!gadget) {
++		dev_dbg(&pdev->dev, "unregistering gadget '%s'\n",
++			otg->gadget->name);
++
++		usb_gadget_vbus_disconnect(otg->gadget);
++		otg->state = OTG_STATE_UNDEFINED;
++
++		otg->gadget = NULL;
++		return 0;
++	}
++
++	otg->gadget = gadget;
++	dev_dbg(&pdev->dev, "registered gadget '%s'\n", gadget->name);
++
++	/* initialize connection state */
++	usb_phy->vbus = 0; /* start with disconnected */
++	if (usb_phy->vbus_gpiod)
++		gpio_vbus_irq(usb_phy->vbus_irq, pdev);
++	return 0;
++}
++
++static ssize_t sw_switch_hsotg_store(struct device *dev, struct device_attribute *attr,
++		const char *buf, size_t count)
++{
++	struct usb_phy_data *usb_phy = (struct usb_phy_data *)dev->driver_data;
++	struct usb_otg		*otg = usb_phy->phy.otg;
++	unsigned int usbrdt;
++
++	if (!sscanf(buf, "%s", usb_phy->hsotg_sw_switch)){
++		printk("input %s not invailed\n", usb_phy->hsotg_sw_switch);
++		return count;
++	}
++
++	if (!strcmp(usb_phy->hsotg_sw_switch, "device")) {
++		if(usb_phy->sw_switch_mode == FORCE_DEVICE){
++			printk("OTG aleady in Device Mode\n");
++			return count;
++		}
++		printk("---Forced switching Device mode!\n");
++
++		usb_phy->sw_switch_mode = FORCE_DEVICE;
++
++		if (usb_phy->drvvbus_gpiod){
++			gpiod_set_value(usb_phy->drvvbus_gpiod,0);
++		}
++
++		usbrdt = cpm_inl(CPM_USBRDT);
++		usbrdt |= USBRDT_IDDIG_EN;
++		usbrdt |= USBRDT_IDDIG_REG;
++		/*ID level is high*/
++		cpm_outl(usbrdt, CPM_USBRDT);
++
++	} else if (!strcmp(usb_phy->hsotg_sw_switch, "host")){
++		if(usb_phy->sw_switch_mode == FORCE_HOST){
++			printk("OTG aleady in Host Mode\n");
++			return count;
++		}
++		printk("---Forced switching Host mode!\n");
++
++		usb_phy->sw_switch_mode = FORCE_HOST;
++
++		usbrdt = cpm_inl(CPM_USBRDT);
++		usbrdt |= USBRDT_IDDIG_EN;
++		usbrdt &= ~USBRDT_IDDIG_REG;
++		/*ID level is low*/
++		cpm_outl(usbrdt, CPM_USBRDT);
++
++		if(usb_phy->drvvbus_gpiod){
++			gpiod_set_value(usb_phy->drvvbus_gpiod,1);
++		}
++
++	} else if (!strcmp(usb_phy->hsotg_sw_switch, "none")){
++		printk("---switching mode from pin!\n");
++
++		usb_phy->sw_switch_mode = FORCE_NONE;
++
++		usbrdt = cpm_inl(CPM_USBRDT);
++		usbrdt &= ~(USBRDT_IDDIG_EN | USBRDT_IDDIG_REG);
++		cpm_outl(usbrdt, CPM_USBRDT);
++
++		if (otg->gadget)
++			schedule_delayed_work(&usb_phy->vbus_work, msecs_to_jiffies(100));
++
++	}
++
++	memset(usb_phy->hsotg_sw_switch, 0 , sizeof(usb_phy->hsotg_sw_switch));
++
++	return count;
++}
++
++static DEVICE_ATTR(sw_switch_hsotg, S_IWUSR, NULL, sw_switch_hsotg_store);
++
++static struct device_attribute *usb_phy_attributes[] = {
++	&dev_attr_sw_switch_hsotg,
++	NULL
++};
++
++static int device_create_node(struct device * dev, struct device_attribute **attrs)
++{
++	struct device_attribute *attr;
++	while ((attr = *attrs++)) {
++		int err;
++		err = device_create_file(dev, attr);
++		if (err) {
++			printk("%s() device_create_file() failed.\n", __func__);
++			return err;
++		}
++	}
++	return 0;
++}
++static int device_remove_node(struct device * dev, struct device_attribute **attrs)
++{
++	struct device_attribute *attr;
++	while ((attr = *attrs++)) {
++		device_remove_file(dev, attr);
++	}
++	return 0;
++}
++
++/* platform driver interface */
++static int ingenic_usb_phy_probe(struct platform_device *pdev)
++{
++	struct usb_phy_data *usb_phy;
++	const struct of_device_id *match;
++	struct device *dev = &pdev->dev;
++	int err;
++
++	usb_phy = devm_kzalloc(dev, sizeof(struct usb_phy_data),
++				 GFP_KERNEL);
++	if (!usb_phy)
++		return -ENOMEM;
++
++	usb_phy->phy.otg = devm_kzalloc(dev, sizeof(struct usb_otg),
++					  GFP_KERNEL);
++	if (!usb_phy->phy.otg)
++		return -ENOMEM;
++
++	usb_phy->cpm_base = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(usb_phy->cpm_base))
++		return PTR_ERR(usb_phy->cpm_base);
++
++	usb_phy->phy_base = devm_platform_ioremap_resource(pdev, 1);
++	if (IS_ERR(usb_phy->phy_base))
++		dev_warn(dev, "dont have usb phy base addr !\n");
++
++	match = of_match_node(of_matchs, dev->of_node);
++	if (!match)
++	        return -ENODEV;
++	usb_phy->phy_priv = (struct usb_phy_priv*)match->data;
++
++	platform_set_drvdata(pdev, usb_phy);
++	usb_phy->dev = dev;
++	usb_phy->phy.label = "ingenic_usb_phy";
++	usb_phy->phy.dev = dev;
++	usb_phy->phy.set_vbus = usb_phy_set_vbus;
++
++	usb_phy->phy.init = common_phy_init;
++	usb_phy->phy.shutdown = common_phy_shutdown;
++	usb_phy->phy.set_suspend = common_phy_set_suspend;
++	usb_phy->phy.set_wakeup = common_phy_set_wakeup;
++	usb_phy->phy.get_wakeup = common_phy_get_wakeup;
++
++	usb_phy->phy.otg->state = OTG_STATE_UNDEFINED;
++	usb_phy->phy.otg->usb_phy = &usb_phy->phy;
++	usb_phy->phy.otg->set_peripheral = usb_phy_set_peripheral;
++
++	usb_phy->gate_clk = devm_clk_get(&pdev->dev, "gate_usbphy");
++	if (IS_ERR(usb_phy->gate_clk)){
++		usb_phy->gate_clk = NULL;
++		dev_err(dev, "cannot get usbphy clock !\n");
++		return -ENODEV;
++	}
++
++	usb_phy->drvvbus_gpiod = devm_gpiod_get_optional(dev, "ingenic,drvvbus", GPIOD_OUT_LOW);
++	if (IS_ERR(usb_phy->drvvbus_gpiod)) {
++		err = PTR_ERR(usb_phy->drvvbus_gpiod);
++		dev_err(dev, "can't request vbus draw gpio, err: %d\n", err);
++		return err;
++	}
++	if (usb_phy->drvvbus_gpiod)
++		gpiod_set_consumer_name(usb_phy->drvvbus_gpiod, "drvvbus");
++
++	usb_phy->vbus_gpiod = devm_gpiod_get_optional(dev, "ingenic,vbus-dete", GPIOD_IN);
++	if (IS_ERR(usb_phy->vbus_gpiod)) {
++		err = PTR_ERR(usb_phy->vbus_gpiod);
++		dev_err(dev, "can't request vbus gpio, err: %d\n", err);
++		return err;
++	}
++
++	if (usb_phy->vbus_gpiod) {
++		gpiod_set_consumer_name(usb_phy->vbus_gpiod, "vbus_detect");
++		INIT_DELAYED_WORK(&usb_phy->vbus_work, gpio_vbus_work);
++		usb_phy->vbus_irq = gpiod_to_irq(usb_phy->vbus_gpiod);
++
++		err = devm_request_irq(dev, usb_phy->vbus_irq, gpio_vbus_irq, VBUS_IRQ_FLAGS,
++					"vbus_detect", pdev);
++		if (err) {
++			dev_err(dev, "can't request vbus irq %i, err: %d\n",
++				usb_phy->vbus_irq, err);
++			return err;
++		}
++	}
++
++	usb_phy->id_gpiod = devm_gpiod_get_optional(dev, "ingenic,id-dete", GPIOD_IN);
++	if (IS_ERR(usb_phy->id_gpiod)) {
++		err = PTR_ERR(usb_phy->id_gpiod);
++		dev_err(dev, "can't request id gpio, err: %d\n", err);
++		return err;
++	}
++
++	if (usb_phy->id_gpiod) {
++		gpiod_set_consumer_name(usb_phy->id_gpiod, "id_detect");
++		INIT_DELAYED_WORK(&usb_phy->id_work, gpio_id_work);
++		usb_phy->id_irq = gpiod_to_irq(usb_phy->id_gpiod);
++
++		err = devm_request_irq(dev, usb_phy->id_irq, gpio_id_irq, ID_IRQ_FLAGS,
++					"id_detect", pdev);
++		if (err) {
++			dev_err(dev, "can't request id irq %i, err: %d\n",
++				usb_phy->id_irq, err);
++			return err;
++		}
++	}
++
++	device_init_wakeup(dev, true);
++
++	if (of_find_property(dev->of_node, "enable-vbus-wakeup", NULL))
++		usb_phy->vbus_wakeup = true;
++
++	if (of_find_property(dev->of_node, "enable-id-wakeup", NULL))
++		usb_phy->id_wakeup = true;
++
++	if (of_find_property(dev->of_node, "enable-usb-wakeup", NULL))
++		usb_phy->usb_wakeup = true;
++
++	if (usb_phy->usb_wakeup) {
++		usb_phy->switch_gpiod = devm_gpiod_get_optional(dev, "ingenic,usb-switch", GPIOD_OUT_LOW);
++		if (IS_ERR(usb_phy->switch_gpiod)) {
++			err = PTR_ERR(usb_phy->switch_gpiod);
++			dev_err(dev, "can't request usb switch gpio, err: %d\n", err);
++			return err;
++		}
++		if (usb_phy->switch_gpiod)
++			gpiod_set_consumer_name(usb_phy->switch_gpiod, "usb_switch");
++
++		usb_phy->wakeup_gpiod = devm_gpiod_get_optional(dev, "ingenic,usb-wakeup", GPIOD_IN);
++		if (IS_ERR(usb_phy->wakeup_gpiod)) {
++			err = PTR_ERR(usb_phy->wakeup_gpiod);
++			dev_err(dev, "can't request usb wakeup gpio, err: %d\n", err);
++			return err;
++		}
++
++		if (usb_phy->wakeup_gpiod) {
++			gpiod_set_consumer_name(usb_phy->wakeup_gpiod, "usb_wakeup");
++			usb_phy->wakeup_irq = gpiod_to_irq(usb_phy->wakeup_gpiod);
++			err = devm_request_irq(dev, usb_phy->wakeup_irq, usb_wakeup_irq_handler,
++					WAKEUP_IRQ_FLAGS, "usb_wakeup", usb_phy);
++			if (err) {
++				dev_err(dev, "can't request usb wakeup irq, err: %d\n", err);
++				return err;
++			}
++
++			disable_irq(usb_phy->wakeup_irq);
++		}
++	}
++
++	err = usb_phy->phy_priv->priv_data_init(usb_phy);
++	if (err) {
++		dev_err(dev, "priv_data_init fail, err: %d\n", err);
++		return err;
++	}
++
++	/* only active when a gadget is registered */
++	err = usb_add_phy(&usb_phy->phy, USB_PHY_TYPE_USB2);
++	if (err) {
++		dev_err(dev, "can't register transceiver, err: %d\n", err);
++		return err;
++	}
++
++	device_create_node(&pdev->dev, usb_phy_attributes);
++
++	return 0;
++}
++
++static int ingenic_usb_phy_remove(struct platform_device *pdev)
++{
++	struct usb_phy_data *usb_phy = platform_get_drvdata(pdev);
++
++	device_init_wakeup(&pdev->dev, 0);
++
++	if (usb_phy->vbus_gpiod)
++		cancel_delayed_work_sync(&usb_phy->vbus_work);
++
++	if (usb_phy->id_gpiod)
++		cancel_delayed_work_sync(&usb_phy->id_work);
++
++	usb_phy->phy_priv->priv_data_exit(usb_phy);
++
++	usb_remove_phy(&usb_phy->phy);
++
++	device_remove_node(usb_phy->dev, usb_phy_attributes);
++
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int ingenic_usb_phy_pm_suspend(struct device *dev)
++{
++	struct usb_phy_data *usb_phy = dev_get_drvdata(dev);
++
++	if (usb_phy->vbus_wakeup && usb_phy->vbus_gpiod)
++		enable_irq_wake(usb_phy->vbus_irq);
++
++	if (usb_phy->id_wakeup && usb_phy->id_gpiod)
++		enable_irq_wake(usb_phy->id_irq);
++
++	return 0;
++}
++
++static int ingenic_usb_phy_pm_resume(struct device *dev)
++{
++	struct usb_phy_data *usb_phy = dev_get_drvdata(dev);
++
++	if (usb_phy->vbus_gpiod) {
++		if (usb_phy->vbus_wakeup)
++			disable_irq_wake(usb_phy->vbus_irq);
++		if (usb_phy->phy.otg->gadget)
++			schedule_delayed_work(&usb_phy->vbus_work, msecs_to_jiffies(100));
++	}
++
++	if (usb_phy->id_gpiod) {
++		if (usb_phy->id_wakeup)
++			disable_irq_wake(usb_phy->id_irq);
++
++		schedule_delayed_work(&usb_phy->id_work, msecs_to_jiffies(100));
++	}
++
++	return 0;
++}
++
++static const struct dev_pm_ops ingenic_usb_phy_pm_ops = {
++	.suspend	= ingenic_usb_phy_pm_suspend,
++	.resume		= ingenic_usb_phy_pm_resume,
++};
++#endif
++
++static struct platform_driver ingenic_usb_phy_driver = {
++	.driver = {
++		.name  = "ingenic_usb_phy",
++		.of_match_table = of_matchs,
++#ifdef CONFIG_PM
++
++		.pm = &ingenic_usb_phy_pm_ops,
++#endif
++	},
++	.probe		= ingenic_usb_phy_probe,
++	.remove		= ingenic_usb_phy_remove,
++};
++
++module_platform_driver(ingenic_usb_phy_driver);
+diff --git a/drivers/usb/phy/phy-ingenic.h b/drivers/usb/phy/phy-ingenic.h
+new file mode 100644
+index 000000000..c49337fc2
+--- /dev/null
++++ b/drivers/usb/phy/phy-ingenic.h
+@@ -0,0 +1,111 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++#ifndef _PHY_INGENIC_H_
++#define _PHY_INGENIC_H_
++
++#include <asm/io.h>
++#include <linux/err.h>
++#include <linux/workqueue.h>
++#include <linux/usb.h>
++#include <linux/usb/gadget.h>
++#include <linux/usb/otg.h>
++
++/* If gpio wake-up mode, OTG cannot detect wake-up interrupt, enable this macro definition */
++//#define TEST_USB_WAKEUP_FLAG
++
++
++struct usb_phy_priv;
++
++struct usb_phy_data {
++	void __iomem *cpm_base;
++	void __iomem *phy_base;
++	char hsotg_sw_switch[8];
++	unsigned char sw_switch_mode;
++	struct clk *gate_clk;
++	struct gpio_desc	*vbus_gpiod;
++	struct gpio_desc	*id_gpiod;
++	struct gpio_desc	*drvvbus_gpiod;
++	struct usb_phy		phy;
++	struct device          *dev;
++	struct delayed_work	vbus_work;
++	struct delayed_work	id_work;
++	int			vbus;
++	int			vbus_irq;
++	int			id;
++	int			id_irq;
++	bool	usb_wakeup;
++	bool	vbus_wakeup;
++	bool	id_wakeup;
++
++#ifdef TEST_USB_WAKEUP_FLAG
++	unsigned int wakeup_flag;
++#endif
++	struct gpio_desc	*switch_gpiod;
++	struct gpio_desc	*wakeup_gpiod;
++	int			wakeup_irq;
++
++	struct usb_phy_priv *phy_priv;
++	void *priv_data;
++};
++
++struct usb_phy_priv {
++	int (*priv_data_init)(struct usb_phy_data *usb_phy);
++	void (*priv_data_exit)(struct usb_phy_data *usb_phy);
++
++	int	(*phy_init)(struct usb_phy_data *usb_phy);
++	void (*phy_shutdown)(struct usb_phy_data *usb_phy);
++
++	int (*phy_set_suspend)(struct usb_phy_data *usb_phy, int suspend);
++
++	int (*phy_set_wakeup)(struct usb_phy_data *usb_phy, bool enabled);
++	int (*phy_get_wakeup)(struct usb_phy_data *usb_phy);
++};
++
++
++static inline unsigned int usb_cpm_readl(struct usb_phy_data *usb_phy, unsigned int reg_offset)
++{
++	return readl(usb_phy->cpm_base + reg_offset);
++}
++
++static inline void usb_cpm_writel(struct usb_phy_data *usb_phy, unsigned int reg_data, unsigned int reg_offset)
++{
++	writel(reg_data, (usb_phy->cpm_base + reg_offset));
++}
++
++#define usb_cpm_clear_bit(_data,_val,_off) \
++		do{usb_cpm_writel(_data, (usb_cpm_readl(_data, _off) & ~(1 << (_val))),(_off));}while(0)
++#define usb_cpm_set_bit(_data,_val,_off) \
++		do{usb_cpm_writel(_data, (usb_cpm_readl(_data, _off) | (1 << (_val))),(_off));}while(0)
++#define usb_cpm_test_bit(_data,_val,_off) \
++		(usb_cpm_readl(_data, _off) & (0x1 << (_val)))
++
++
++static inline unsigned int usb_phy_readl(struct usb_phy_data *usb_phy, unsigned int reg_offset)
++{
++	unsigned int data = 0;
++
++	if (!IS_ERR_OR_NULL(usb_phy->phy_base))
++		data = readl(usb_phy->phy_base + reg_offset);
++
++	return data;
++}
++
++static inline void usb_phy_writel(struct usb_phy_data *usb_phy, unsigned int reg_data, unsigned int reg_offset)
++{
++	if (!IS_ERR_OR_NULL(usb_phy->phy_base))
++		writel(reg_data, (usb_phy->phy_base + reg_offset));
++}
++
++#define usb_phy_clear_bit(_data,_val,_off) \
++		do{usb_phy_writel(_data, (usb_phy_readl(_data, _off) & ~(1 << (_val))),(_off));}while(0)
++#define usb_phy_set_bit(_data,_val,_off) \
++		do{usb_phy_writel(_data, (usb_phy_readl(_data, _off) | (1 << (_val))),(_off));}while(0)
++#define usb_phy_test_bit(_data,_val,_off) \
++		(usb_phy_readl(_data, _off) & (0x1 << (_val)))
++
++
++extern struct usb_phy_priv usb_phy_x1000_priv;
++extern struct usb_phy_priv usb_phy_x1600_priv;
++extern struct usb_phy_priv usb_phy_x2000_priv;
++extern struct usb_phy_priv usb_phy_x2500_priv;
++
++#endif /* _PHY_INGENIC_H_ */
+diff --git a/drivers/usb/phy/phy-tahvo.c b/drivers/usb/phy/phy-tahvo.c
+index a3e043e3e..baebb1f5a 100644
+--- a/drivers/usb/phy/phy-tahvo.c
++++ b/drivers/usb/phy/phy-tahvo.c
+@@ -393,9 +393,7 @@ static int tahvo_usb_probe(struct platform_device *pdev)
+ 
+ 	dev_set_drvdata(&pdev->dev, tu);
+ 
+-	tu->irq = ret = platform_get_irq(pdev, 0);
+-	if (ret < 0)
+-		return ret;
++	tu->irq = platform_get_irq(pdev, 0);
+ 	ret = request_threaded_irq(tu->irq, NULL, tahvo_usb_vbus_interrupt,
+ 				   IRQF_ONESHOT,
+ 				   "tahvo-vbus", tu);
+diff --git a/drivers/usb/phy/phy-twl6030-usb.c b/drivers/usb/phy/phy-twl6030-usb.c
+index ab3c38a7d..8ba6c5a91 100644
+--- a/drivers/usb/phy/phy-twl6030-usb.c
++++ b/drivers/usb/phy/phy-twl6030-usb.c
+@@ -348,11 +348,6 @@ static int twl6030_usb_probe(struct platform_device *pdev)
+ 	twl->irq2		= platform_get_irq(pdev, 1);
+ 	twl->linkstat		= MUSB_UNKNOWN;
+ 
+-	if (twl->irq1 < 0)
+-		return twl->irq1;
+-	if (twl->irq2 < 0)
+-		return twl->irq2;
+-
+ 	twl->comparator.set_vbus	= twl6030_set_vbus;
+ 	twl->comparator.start_srp	= twl6030_start_srp;
+ 
+diff --git a/drivers/usb/phy/phy.c b/drivers/usb/phy/phy.c
+index b47285f02..1b24492bb 100644
+--- a/drivers/usb/phy/phy.c
++++ b/drivers/usb/phy/phy.c
+@@ -42,6 +42,12 @@ static const char *const usb_chger_type[] = {
+ 	[ACA_TYPE]			= "USB_CHARGER_ACA_TYPE",
+ };
+ 
++static const char *const usb_chger_state[] = {
++	[USB_CHARGER_DEFAULT]	= "USB_CHARGER_DEFAULT",
++	[USB_CHARGER_PRESENT]	= "USB_CHARGER_PRESENT",
++	[USB_CHARGER_ABSENT]	= "USB_CHARGER_ABSENT",
++};
++
+ static struct usb_phy *__usb_find_phy(struct list_head *list,
+ 	enum usb_phy_type type)
+ {
+@@ -74,6 +80,18 @@ static struct usb_phy *__of_usb_find_phy(struct device_node *node)
+ 	return ERR_PTR(-EPROBE_DEFER);
+ }
+ 
++static struct usb_phy *__device_to_usb_phy(struct device *dev)
++{
++	struct usb_phy *usb_phy;
++
++	list_for_each_entry(usb_phy, &phy_list, head) {
++		if (usb_phy->dev == dev)
++			return usb_phy;
++	}
++
++	return NULL;
++}
++
+ static void usb_phy_set_default_current(struct usb_phy *usb_phy)
+ {
+ 	usb_phy->chg_cur.sdp_min = DEFAULT_SDP_CUR_MIN;
+@@ -105,9 +123,6 @@ static void usb_phy_set_default_current(struct usb_phy *usb_phy)
+ static void usb_phy_notify_charger_work(struct work_struct *work)
+ {
+ 	struct usb_phy *usb_phy = container_of(work, struct usb_phy, chg_work);
+-	char uchger_state[50] = { 0 };
+-	char uchger_type[50] = { 0 };
+-	char *envp[] = { uchger_state, uchger_type, NULL };
+ 	unsigned int min, max;
+ 
+ 	switch (usb_phy->chg_state) {
+@@ -115,15 +130,11 @@ static void usb_phy_notify_charger_work(struct work_struct *work)
+ 		usb_phy_get_charger_current(usb_phy, &min, &max);
+ 
+ 		atomic_notifier_call_chain(&usb_phy->notifier, max, usb_phy);
+-		snprintf(uchger_state, ARRAY_SIZE(uchger_state),
+-			 "USB_CHARGER_STATE=%s", "USB_CHARGER_PRESENT");
+ 		break;
+ 	case USB_CHARGER_ABSENT:
+ 		usb_phy_set_default_current(usb_phy);
+ 
+ 		atomic_notifier_call_chain(&usb_phy->notifier, 0, usb_phy);
+-		snprintf(uchger_state, ARRAY_SIZE(uchger_state),
+-			 "USB_CHARGER_STATE=%s", "USB_CHARGER_ABSENT");
+ 		break;
+ 	default:
+ 		dev_warn(usb_phy->dev, "Unknown USB charger state: %d\n",
+@@ -131,9 +142,36 @@ static void usb_phy_notify_charger_work(struct work_struct *work)
+ 		return;
+ 	}
+ 
++	kobject_uevent(&usb_phy->dev->kobj, KOBJ_CHANGE);
++}
++
++static int usb_phy_uevent(struct device *dev, struct kobj_uevent_env *env)
++{
++	struct usb_phy *usb_phy;
++	char uchger_state[50] = { 0 };
++	char uchger_type[50] = { 0 };
++	unsigned long flags;
++
++	spin_lock_irqsave(&phy_lock, flags);
++	usb_phy = __device_to_usb_phy(dev);
++	spin_unlock_irqrestore(&phy_lock, flags);
++
++	if (!usb_phy)
++		return -ENODEV;
++
++	snprintf(uchger_state, ARRAY_SIZE(uchger_state),
++		 "USB_CHARGER_STATE=%s", usb_chger_state[usb_phy->chg_state]);
++
+ 	snprintf(uchger_type, ARRAY_SIZE(uchger_type),
+ 		 "USB_CHARGER_TYPE=%s", usb_chger_type[usb_phy->chg_type]);
+-	kobject_uevent_env(&usb_phy->dev->kobj, KOBJ_CHANGE, envp);
++
++	if (add_uevent_var(env, uchger_state))
++		return -ENOMEM;
++
++	if (add_uevent_var(env, uchger_type))
++		return -ENOMEM;
++
++	return 0;
+ }
+ 
+ static void __usb_phy_get_charger_type(struct usb_phy *usb_phy)
+@@ -661,6 +699,11 @@ int usb_add_phy(struct usb_phy *x, enum usb_phy_type type)
+ }
+ EXPORT_SYMBOL_GPL(usb_add_phy);
+ 
++static struct device_type usb_phy_dev_type = {
++	.name = "usb_phy",
++	.uevent = usb_phy_uevent,
++};
++
+ /**
+  * usb_add_phy_dev - declare the USB PHY
+  * @x: the USB phy to be used; or NULL
+@@ -684,6 +727,8 @@ int usb_add_phy_dev(struct usb_phy *x)
+ 	if (ret)
+ 		return ret;
+ 
++	x->dev->type = &usb_phy_dev_type;
++
+ 	ATOMIC_INIT_NOTIFIER_HEAD(&x->notifier);
+ 
+ 	spin_lock_irqsave(&phy_lock, flags);
+diff --git a/drivers/usb/roles/class.c b/drivers/usb/roles/class.c
+index 33b637d0d..dfaed7eee 100644
+--- a/drivers/usb/roles/class.c
++++ b/drivers/usb/roles/class.c
+@@ -214,6 +214,15 @@ static const char * const usb_roles[] = {
+ 	[USB_ROLE_DEVICE]	= "device",
+ };
+ 
++const char *usb_role_string(enum usb_role role)
++{
++	if (role < 0 || role >= ARRAY_SIZE(usb_roles))
++		return "unknown";
++
++	return usb_roles[role];
++}
++EXPORT_SYMBOL_GPL(usb_role_string);
++
+ static ssize_t
+ role_show(struct device *dev, struct device_attribute *attr, char *buf)
+ {
+diff --git a/include/dt-bindings/clock/ingenic-m300.h b/include/dt-bindings/clock/ingenic-m300.h
+new file mode 100644
+index 000000000..edee16efb
+--- /dev/null
++++ b/include/dt-bindings/clock/ingenic-m300.h
+@@ -0,0 +1,201 @@
++#ifndef _DT_BINDINGS_CLOCK_M300_H
++#define _DT_BINDINGS_CLOCK_M300_H
++
++/* Fixed Clk */
++#define CLK_ID_FIEXED	0
++#define	CLK_EXT		(CLK_ID_FIEXED + 0)
++#define	CLK_RTC_EXT	(CLK_ID_FIEXED + 1)
++#define	CLK_EXT_DIV_512	(CLK_ID_FIEXED + 2)
++#define CLK_NR_FIXED	(3)
++
++/* PLL clk */
++#define CLK_ID_PLL	(CLK_ID_FIEXED + CLK_NR_FIXED)
++#define CLK_PLL_APLL	(CLK_ID_PLL + 0)
++#define CLK_PLL_MPLL	(CLK_ID_PLL + 1)
++#define CLK_PLL_EPLL	(CLK_ID_PLL + 2)
++#define CLK_NR_PLL	(3)
++
++/* MUX clk */
++#define CLK_ID_MUX		(CLK_ID_PLL + CLK_NR_PLL)
++#define CLK_MUX_SCLKA		(CLK_ID_MUX + 0)
++#define CLK_MUX_CPU_L2C		(CLK_ID_MUX + 1)
++#define CLK_MUX_AHB0		(CLK_ID_MUX + 2)
++#define CLK_MUX_AHB2		(CLK_ID_MUX + 3)
++#define CLK_MUX_DDR		(CLK_ID_MUX + 4)
++#define CLK_MUX_MACPHY		(CLK_ID_MUX + 5)
++#define CLK_MUX_MACTXPHY	(CLK_ID_MUX + 6)
++#define CLK_MUX_MACTXPHY1	(CLK_ID_MUX + 7)
++#define CLK_MUX_I2S0		(CLK_ID_MUX + 8)
++#define CLK_MUX_I2S1		(CLK_ID_MUX + 9)
++#define CLK_MUX_I2S2            (CLK_ID_MUX + 10)
++#define CLK_MUX_I2S3            (CLK_ID_MUX + 11)
++#define CLK_MUX_AUDIO_RAM       (CLK_ID_MUX + 12)
++#define CLK_MUX_SPDIF           (CLK_ID_MUX + 13)
++#define CLK_MUX_PCM             (CLK_ID_MUX + 14)
++#define CLK_MUX_DMIC            (CLK_ID_MUX + 15)
++#define CLK_MUX_LCD             (CLK_ID_MUX + 16)
++#define CLK_MUX_MSC0            (CLK_ID_MUX + 17)
++#define CLK_MUX_MSC1		(CLK_ID_MUX + 18)
++#define CLK_MUX_MSC2            (CLK_ID_MUX + 19)
++#define CLK_MUX_SFC             (CLK_ID_MUX + 20)
++#define CLK_MUX_SSI             (CLK_ID_MUX + 21)
++#define CLK_MUX_CIM             (CLK_ID_MUX + 22)
++#define CLK_MUX_PWM             (CLK_ID_MUX + 23)
++#define CLK_MUX_ISP             (CLK_ID_MUX + 24)
++#define CLK_MUX_RSA             (CLK_ID_MUX + 25)
++#define CLK_MUX_MACPTP		(CLK_ID_MUX + 26)
++#define CLK_MUX_WDT		(CLK_ID_MUX + 27)
++
++
++#define CLK_NR_MUX		(28)
++
++
++#define CLK_ID_DIV		(CLK_ID_MUX + CLK_NR_MUX)
++#define CLK_DIV_DDR		(CLK_ID_DIV + 0)
++#define CLK_DIV_MACPHY		(CLK_ID_DIV + 1)
++#define CLK_DIV_MACTXPHY	(CLK_ID_DIV + 2)
++#define CLK_DIV_MACTXPHY1       (CLK_ID_DIV + 3)
++#define CLK_DIV_I2S0		(CLK_ID_DIV + 4)
++#define CLK_DIV_I2S1            (CLK_ID_DIV + 5)
++#define CLK_DIV_I2S2            (CLK_ID_DIV + 6)
++#define CLK_DIV_I2S3            (CLK_ID_DIV + 7)
++#define CLK_DIV_LCD		(CLK_ID_DIV + 8)
++#define CLK_DIV_MSC0            (CLK_ID_DIV + 9)
++#define CLK_DIV_MSC1            (CLK_ID_DIV + 10)
++#define CLK_DIV_MSC2            (CLK_ID_DIV + 11)
++#define CLK_DIV_SFC             (CLK_ID_DIV + 12)
++#define CLK_DIV_SSI             (CLK_ID_DIV + 13)
++#define CLK_DIV_CIM             (CLK_ID_DIV + 14)
++#define CLK_DIV_PWM             (CLK_ID_DIV + 15)
++#define CLK_DIV_ISP		(CLK_ID_DIV + 16)
++#define CLK_DIV_RSA             (CLK_ID_DIV + 17)
++#define CLK_DIV_MACPTP		(CLK_ID_DIV + 18)
++
++#define CLK_DIV_CPU		(CLK_ID_DIV + 19)
++#define CLK_DIV_L2C             (CLK_ID_DIV + 20)
++#define CLK_DIV_AHB0            (CLK_ID_DIV + 21)
++#define CLK_DIV_AHB2            (CLK_ID_DIV + 22)
++#define CLK_DIV_APB             (CLK_ID_DIV + 23)
++#define CLK_DIV_CPU_L2C_X1      (CLK_ID_DIV + 24)
++#define CLK_DIV_CPU_L2C_X2      (CLK_ID_DIV + 25)
++
++#define CLK_NR_DIV		(26)
++
++
++/* Gate Clocks */
++#define CLK_ID_GATE		(CLK_ID_DIV + CLK_NR_DIV)
++#define CLK_GATE_DDR		(CLK_ID_GATE + 0)
++#define CLK_GATE_IPU		(CLK_ID_GATE + 1)
++#define CLK_GATE_AHB0		(CLK_ID_GATE + 2)
++#define CLK_GATE_APB0		(CLK_ID_GATE + 3)
++#define CLK_GATE_RTC		(CLK_ID_GATE + 4)
++#define CLK_GATE_SSI1		(CLK_ID_GATE + 5)
++#define CLK_GATE_RSA		(CLK_ID_GATE + 6)
++#define CLK_GATE_AES		(CLK_ID_GATE + 7)
++#define CLK_GATE_LCD		(CLK_ID_GATE + 8)
++#define CLK_GATE_CIM		(CLK_ID_GATE + 9)
++#define CLK_GATE_PDMA		(CLK_ID_GATE + 10)
++#define CLK_GATE_OST		(CLK_ID_GATE + 11)
++#define CLK_GATE_SSI0		(CLK_ID_GATE + 12)
++#define CLK_GATE_TCU		(CLK_ID_GATE + 13)
++#define CLK_GATE_DTRNG		(CLK_ID_GATE + 14)
++#define CLK_GATE_UART2		(CLK_ID_GATE + 15)
++#define CLK_GATE_UART1		(CLK_ID_GATE + 16)
++#define CLK_GATE_UART0		(CLK_ID_GATE + 17)
++#define CLK_GATE_SADC		(CLK_ID_GATE + 18)
++#define CLK_GATE_HELIX		(CLK_ID_GATE + 19)
++#define CLK_GATE_AUDIO		(CLK_ID_GATE + 20)
++#define CLK_GATE_SMB3		(CLK_ID_GATE + 21)
++#define CLK_GATE_SMB2		(CLK_ID_GATE + 22)
++#define CLK_GATE_SMB1		(CLK_ID_GATE + 23)
++#define CLK_GATE_SMB0		(CLK_ID_GATE + 24)
++#define CLK_GATE_SCC		(CLK_ID_GATE + 25)
++#define CLK_GATE_MSC1		(CLK_ID_GATE + 26)
++#define CLK_GATE_MSC0		(CLK_ID_GATE + 27)
++#define CLK_GATE_OTG		(CLK_ID_GATE + 28)
++#define CLK_GATE_SFC		(CLK_ID_GATE + 29)
++#define CLK_GATE_EFUSE		(CLK_ID_GATE + 30)
++#define CLK_GATE_NEMC		(CLK_ID_GATE + 31)
++#define CLK_GATE_ARB		(CLK_ID_GATE + 32)
++#define CLK_GATE_MIPI_DSI	(CLK_ID_GATE + 33)
++#define CLK_GATE_MIPI_CSI	(CLK_ID_GATE + 34)
++#define CLK_GATE_INTC		(CLK_ID_GATE + 35)
++#define CLK_GATE_MSC2		(CLK_ID_GATE + 36)
++#define CLK_GATE_GMAC1		(CLK_ID_GATE + 37)
++#define CLK_GATE_GMAC0		(CLK_ID_GATE + 38)
++#define CLK_GATE_UART9		(CLK_ID_GATE + 39)
++#define CLK_GATE_UART8		(CLK_ID_GATE + 40)
++#define CLK_GATE_UART7		(CLK_ID_GATE + 41)
++#define CLK_GATE_UATR6		(CLK_ID_GATE + 42)
++#define CLK_GATE_UART5		(CLK_ID_GATE + 43)
++#define CLK_GATE_UART4		(CLK_ID_GATE + 44)
++#define CLK_GATE_UART3		(CLK_ID_GATE + 45)
++#define CLK_GATE_SPDIF		(CLK_ID_GATE + 46)
++#define CLK_GATE_DMIC		(CLK_ID_GATE + 47)
++#define CLK_GATE_PCM		(CLK_ID_GATE + 48)
++#define CLK_GATE_I2S3		(CLK_ID_GATE + 49)
++#define CLK_GATE_I2S2		(CLK_ID_GATE + 50)
++#define CLK_GATE_I2S1		(CLK_ID_GATE + 51)
++#define CLK_GATE_I2S0		(CLK_ID_GATE + 52)
++#define CLK_GATE_ROT		(CLK_ID_GATE + 53)
++#define CLK_GATE_HASH		(CLK_ID_GATE + 54)
++#define CLK_GATE_PWM		(CLK_ID_GATE + 55)
++#define CLK_GATE_FELIX		(CLK_ID_GATE + 56)
++#define CLK_GATE_ISP1		(CLK_ID_GATE + 57)
++#define CLK_GATE_ISP0		(CLK_ID_GATE + 58)
++#define CLK_GATE_SMB5		(CLK_ID_GATE + 59)
++#define CLK_GATE_SMB4		(CLK_ID_GATE + 60)
++#define CLK_GATE_USBPHY		(CLK_ID_GATE + 61)
++#define CLK_CE_I2S0		(CLK_ID_GATE + 62)
++#define CLK_CE_I2S1		(CLK_ID_GATE + 63)
++#define CLK_CE_I2S2		(CLK_ID_GATE + 64)
++#define CLK_CE_I2S3		(CLK_ID_GATE + 65)
++#define CLK_NR_GATE		(66)
++
++#define POWER_ID		(CLK_ID_GATE + CLK_NR_GATE)
++#define POWER_ISP0		(POWER_ID + 0)
++#define POWER_ISP1		(POWER_ID + 1)
++#define POWER_FELIX		(POWER_ID + 2)
++#define POWER_HELIX		(POWER_ID + 3)
++
++#define PD_MEM_NEMC    		(POWER_ID + 4)
++#define PD_MEM_USB     		(POWER_ID + 5)
++#define PD_MEM_SFC     		(POWER_ID + 6)
++#define PD_MEM_PDMA_SEC		(POWER_ID + 7)
++#define PD_MEM_PDMA    		(POWER_ID + 8)
++#define PD_MEM_MSC2    		(POWER_ID + 9)
++#define PD_MEM_MSC1    		(POWER_ID + 10)
++#define PD_MEM_MSC0    		(POWER_ID + 11)
++#define PD_MEM_GMAC1   		(POWER_ID + 12)
++#define PD_MEM_GMAC0   		(POWER_ID + 13)
++#define PD_MEM_DMIC    		(POWER_ID + 14)
++#define PD_MEM_AUDIO   		(POWER_ID + 15)
++#define PD_MEM_AES     		(POWER_ID + 16)
++#define PD_MEM_DSI     		(POWER_ID + 17)
++#define PD_MEM_SSI1    		(POWER_ID + 18)
++#define PD_MEM_SSI0    		(POWER_ID + 19)
++#define PD_MEM_UART9   		(POWER_ID + 20)
++#define PD_MEM_UART8   		(POWER_ID + 21)
++#define PD_MEM_UART7   		(POWER_ID + 22)
++#define PD_MEM_UART6   		(POWER_ID + 23)
++#define PD_MEM_UART5   		(POWER_ID + 24)
++#define PD_MEM_UART4   		(POWER_ID + 25)
++#define PD_MEM_UART3   		(POWER_ID + 26)
++#define PD_MEM_UART2   		(POWER_ID + 27)
++#define PD_MEM_UART1   		(POWER_ID + 28)
++#define PD_MEM_UART0   		(POWER_ID + 29)
++#define PD_MEM_ROT     		(POWER_ID + 30)
++#define PD_MEM_CIM     		(POWER_ID + 31)
++#define PD_MEM_DPU     		(POWER_ID + 32)
++#define PD_MEM_DDR_CH6 		(POWER_ID + 33)
++#define PD_MEM_DDR_CH5 		(POWER_ID + 34)
++#define PD_MEM_DDR_CH3 		(POWER_ID + 35)
++#define PD_MEM_DDR_CH1 		(POWER_ID + 36)
++#define PD_MEM_DDR_CH0 		(POWER_ID + 37)
++#define PD_MEM_DDR_TOP 		(POWER_ID + 38)
++#define CLK_NR_POWER		(39)
++
++#define CLK_ID_OTHER		(POWER_ID + CLK_NR_POWER)
++
++#define NR_CLKS		(CLK_NR_FIXED + CLK_NR_PLL + CLK_NR_MUX + CLK_NR_DIV + CLK_NR_GATE + CLK_NR_POWER)
++#endif
+diff --git a/include/dt-bindings/clock/ingenic-tcu.h b/include/dt-bindings/clock/ingenic-tcu.h
+new file mode 100644
+index 000000000..d92493c33
+--- /dev/null
++++ b/include/dt-bindings/clock/ingenic-tcu.h
+@@ -0,0 +1,29 @@
++#ifndef __DT_BINDINGS_CLOCK_INGENIC_TCU_H__
++#define __DT_BINDINGS_CLOCK_INGENIC_TCU_H__
++
++#define TCU_MODE1				1
++#define TCU_MODE2				2
++
++#define PWM_FUNC					1
++#define TRACKBALL_FUNC				2
++#define PWM_AND_TRACKBALL_FUNC		(PWM_FUNC | TRACKBALL_FUNC)
++
++#define NO_PWM_IN			0
++#define PWM_IN				1
++
++#define NOWORK_SLEEP			0
++#define WORK_SLEEP				1
++
++#define CHANNEL_BASE_OFF 4
++#define CHANNEL_ID_OFF 0
++#define CHANNEL_MODE_OFF (CHANNEL_ID_OFF + CHANNEL_BASE_OFF*2)
++#define CHANNEL_FUNC_OFF (CHANNEL_MODE_OFF + CHANNEL_BASE_OFF)
++#define CHANNEL_IN_OFF (CHANNEL_FUNC_OFF + CHANNEL_BASE_OFF)
++#define CHANNEL_SLEEP_OFF (CHANNEL_IN_OFF + CHANNEL_BASE_OFF)
++
++#define CHANNEL_INFO(ID, MODE, FUNC, IN, SLEEP)			\
++	((ID << CHANNEL_ID_OFF)|(MODE << CHANNEL_MODE_OFF)	\
++	 |(FUNC << CHANNEL_FUNC_OFF)|(IN << CHANNEL_IN_OFF)	\
++	 |(SLEEP << CHANNEL_SLEEP_OFF))
++
++#endif /* __DT_BINDINGS_CLOCK_INGENIC_TCU_H__ */
+diff --git a/include/dt-bindings/clock/ingenic-x1600.h b/include/dt-bindings/clock/ingenic-x1600.h
+new file mode 100644
+index 000000000..c5ea4975e
+--- /dev/null
++++ b/include/dt-bindings/clock/ingenic-x1600.h
+@@ -0,0 +1,146 @@
++#ifndef _DT_BINDINGS_CLOCK_X2000_V12_H
++#define _DT_BINDINGS_CLOCK_X2000_V12_H
++
++/* Fixed Clk */
++#define CLK_ID_FIEXED	0
++#define	CLK_EXT		(CLK_ID_FIEXED + 0)
++#define	CLK_RTC_EXT	(CLK_ID_FIEXED + 1)
++#define	CLK_EXT_DIV_512	(CLK_ID_FIEXED + 2)
++#define CLK_NR_FIXED	(3)
++
++/* PLL clk */
++#define CLK_ID_PLL	(CLK_ID_FIEXED + CLK_NR_FIXED)
++#define CLK_PLL_APLL	(CLK_ID_PLL + 0)
++#define CLK_PLL_MPLL	(CLK_ID_PLL + 1)
++#define CLK_PLL_EPLL	(CLK_ID_PLL + 2)
++#define CLK_NR_PLL	(3)
++
++/* MUX clk */
++#define CLK_ID_MUX		(CLK_ID_PLL + CLK_NR_PLL)
++#define CLK_MUX_SCLKA		(CLK_ID_MUX + 0)
++#define CLK_MUX_CPU_L2C		(CLK_ID_MUX + 1)
++#define CLK_MUX_AHB0		(CLK_ID_MUX + 2)
++#define CLK_MUX_AHB2		(CLK_ID_MUX + 3)
++#define CLK_MUX_DDR		(CLK_ID_MUX + 4)
++#define CLK_MUX_MACPHY		(CLK_ID_MUX + 5)
++#define CLK_MUX_I2S0T		(CLK_ID_MUX + 6)
++#define CLK_MUX_LCD             (CLK_ID_MUX + 7)
++#define CLK_MUX_MSC0            (CLK_ID_MUX + 8)
++#define CLK_MUX_MSC1		(CLK_ID_MUX + 9)
++#define CLK_MUX_SFC             (CLK_ID_MUX + 10)
++#define CLK_MUX_SSI             (CLK_ID_MUX + 11)
++#define CLK_MUX_CIM             (CLK_ID_MUX + 12)
++#define CLK_MUX_PWM             (CLK_ID_MUX + 13)
++#define CLK_MUX_CAN0	        (CLK_ID_MUX + 14)
++#define CLK_MUX_CAN1		(CLK_ID_MUX + 15)
++#define CLK_MUX_CDBUS		(CLK_ID_MUX + 16)
++#define CLK_MUX_I2S0R		(CLK_ID_MUX + 17)
++#define CLK_MUX_WDT		(CLK_ID_MUX + 18)
++
++#define CLK_NR_MUX		(19)
++
++
++#define CLK_ID_DIV		(CLK_ID_MUX + CLK_NR_MUX)
++#define CLK_DIV_DDR		(CLK_ID_DIV + 0)
++#define CLK_DIV_MACPHY		(CLK_ID_DIV + 1)
++#define CLK_DIV_I2S0T		(CLK_ID_DIV + 2)
++#define CLK_DIV_LCD		(CLK_ID_DIV + 3)
++#define CLK_DIV_MSC0            (CLK_ID_DIV + 4)
++#define CLK_DIV_MSC1            (CLK_ID_DIV + 5)
++#define CLK_DIV_SFC             (CLK_ID_DIV + 6)
++#define CLK_DIV_SSI             (CLK_ID_DIV + 7)
++#define CLK_DIV_CIM             (CLK_ID_DIV + 8)
++#define CLK_DIV_PWM             (CLK_ID_DIV + 9)
++#define CLK_DIV_CAN0	 	(CLK_ID_DIV + 10)
++#define CLK_DIV_CAN1		(CLK_ID_DIV + 11)
++#define CLK_DIV_CDBUS		(CLK_ID_DIV + 12)
++
++#define CLK_DIV_CPU		(CLK_ID_DIV + 13)
++#define CLK_DIV_L2C             (CLK_ID_DIV + 14)
++#define CLK_DIV_AHB0            (CLK_ID_DIV + 15)
++#define CLK_DIV_AHB2            (CLK_ID_DIV + 16)
++#define CLK_DIV_APB             (CLK_ID_DIV + 17)
++#define CLK_DIV_CPU_L2C_X1      (CLK_ID_DIV + 18)
++#define CLK_DIV_CPU_L2C_X2      (CLK_ID_DIV + 19)
++#define CLK_DIV_I2S0R		(CLK_ID_DIV + 20)
++
++#define CLK_NR_DIV		(21)
++
++
++/* Gate Clocks */
++#define CLK_ID_GATE		(CLK_ID_DIV + CLK_NR_DIV)
++#define CLK_GATE_DDR		(CLK_ID_GATE + 0)
++#define CLK_GATE_AHB0		(CLK_ID_GATE + 1)
++#define CLK_GATE_APB0		(CLK_ID_GATE + 2)
++#define CLK_GATE_RTC		(CLK_ID_GATE + 3)
++#define CLK_GATE_AES		(CLK_ID_GATE + 4)
++#define CLK_GATE_LCD		(CLK_ID_GATE + 5)
++#define CLK_GATE_CIM		(CLK_ID_GATE + 6)
++#define CLK_GATE_PDMA		(CLK_ID_GATE + 7)
++#define CLK_GATE_OST		(CLK_ID_GATE + 8)
++#define CLK_GATE_SSI0		(CLK_ID_GATE + 9)
++#define CLK_GATE_TCU		(CLK_ID_GATE + 10)
++#define CLK_GATE_DTRNG		(CLK_ID_GATE + 11)
++#define CLK_GATE_UART2		(CLK_ID_GATE + 12)
++#define CLK_GATE_UART1		(CLK_ID_GATE + 13)
++#define CLK_GATE_UART0		(CLK_ID_GATE + 14)
++#define CLK_GATE_SADC		(CLK_ID_GATE + 15)
++#define CLK_GATE_AUDIO		(CLK_ID_GATE + 16)
++#define CLK_GATE_SSISLV		(CLK_ID_GATE + 17)
++#define CLK_GATE_SMB1		(CLK_ID_GATE + 18)
++#define CLK_GATE_SMB0		(CLK_ID_GATE + 19)
++#define CLK_GATE_MSC1		(CLK_ID_GATE + 20)
++#define CLK_GATE_MSC0		(CLK_ID_GATE + 21)
++#define CLK_GATE_OTG		(CLK_ID_GATE + 22)
++#define CLK_GATE_SFC		(CLK_ID_GATE + 23)
++#define CLK_GATE_EFUSE		(CLK_ID_GATE + 24)
++#define CLK_GATE_NEMC		(CLK_ID_GATE + 25)
++#define CLK_GATE_ARB		(CLK_ID_GATE + 26)
++#define CLK_GATE_MIPI_CSI	(CLK_ID_GATE + 27)
++#define CLK_GATE_INTC		(CLK_ID_GATE + 28)
++#define CLK_GATE_GMAC0		(CLK_ID_GATE + 29)
++#define CLK_GATE_UART3		(CLK_ID_GATE + 30)
++#define CLK_GATE_I2S0T		(CLK_ID_GATE + 31)
++#define CLK_GATE_I2S0R		(CLK_ID_GATE + 32)
++#define CLK_GATE_HASH		(CLK_ID_GATE + 33)
++#define CLK_GATE_PWM		(CLK_ID_GATE + 34)
++#define CLK_GATE_CDBUS		(CLK_ID_GATE + 35)
++#define CLK_GATE_CAN1		(CLK_ID_GATE + 36)
++#define CLK_GATE_CAN0		(CLK_ID_GATE + 37)
++#define CLK_GATE_USBPHY		(CLK_ID_GATE + 38)
++#define CLK_CE_I2S0T		(CLK_ID_GATE + 39)
++#define CLK_CE_I2S0R		(CLK_ID_GATE + 40)
++#define CLK_NR_GATE		(41)
++
++#define POWER_ID		(CLK_ID_GATE + CLK_NR_GATE)
++#define PD_MEM_CDBUS		(POWER_ID + 4)
++#define PD_MEM_PWM		(POWER_ID + 5)
++#define PD_MEM_GMAC		(POWER_ID + 6)
++#define PD_MEM_USB		(POWER_ID + 7)
++#define PD_MEM_SFC		(POWER_ID + 8)
++#define PD_MEM_MSC1		(POWER_ID + 9)
++#define PD_MEM_MSC0		(POWER_ID + 10)
++#define PD_MEM_AES		(POWER_ID + 11)
++#define PD_MEM_PDMA_SLP		(POWER_ID + 12)
++#define PD_MEM_PDMA_SEC		(POWER_ID + 13)
++#define PD_MEM_PDMA		(POWER_ID + 14)
++#define PD_MEM_NEMC		(POWER_ID + 15)
++#define PD_MEM_AIC		(POWER_ID + 16)
++#define PD_MEM_SSISLV		(POWER_ID + 17)
++#define PD_MEM_SSI0		(POWER_ID + 18)
++#define PD_MEM_UART3		(POWER_ID + 19)
++#define PD_MEM_UART2		(POWER_ID + 20)
++#define PD_MEM_UART1		(POWER_ID + 21)
++#define PD_MEM_UART0		(POWER_ID + 22)
++#define PD_MEM_CIM		(POWER_ID + 23)
++#define PD_MEM_DPU		(POWER_ID + 24)
++#define PD_MEM_DDR_CH6		(POWER_ID + 25)
++#define PD_MEM_DDR_CH5		(POWER_ID + 26)
++#define PD_MEM_DDR_CH3		(POWER_ID + 27)
++#define PD_MEM_DDR_TOP		(POWER_ID + 28)
++#define CLK_NR_POWER		(29)
++
++#define CLK_ID_OTHER		(POWER_ID + CLK_NR_POWER)
++
++#define NR_CLKS		(CLK_NR_FIXED + CLK_NR_PLL + CLK_NR_MUX + CLK_NR_DIV + CLK_NR_GATE + CLK_NR_POWER)
++#endif
+diff --git a/include/dt-bindings/clock/ingenic-x2000.h b/include/dt-bindings/clock/ingenic-x2000.h
+new file mode 100644
+index 000000000..25ce88570
+--- /dev/null
++++ b/include/dt-bindings/clock/ingenic-x2000.h
+@@ -0,0 +1,201 @@
++#ifndef _DT_BINDINGS_CLOCK_X2000_H
++#define _DT_BINDINGS_CLOCK_X2000_H
++
++/* Fixed Clk */
++#define CLK_ID_FIEXED	0
++#define	CLK_EXT		(CLK_ID_FIEXED + 0)
++#define	CLK_RTC_EXT	(CLK_ID_FIEXED + 1)
++#define	CLK_EXT_DIV_512	(CLK_ID_FIEXED + 2)
++#define CLK_NR_FIXED	(3)
++
++/* PLL clk */
++#define CLK_ID_PLL	(CLK_ID_FIEXED + CLK_NR_FIXED)
++#define CLK_PLL_APLL	(CLK_ID_PLL + 0)
++#define CLK_PLL_MPLL	(CLK_ID_PLL + 1)
++#define CLK_PLL_EPLL	(CLK_ID_PLL + 2)
++#define CLK_NR_PLL	(3)
++
++/* MUX clk */
++#define CLK_ID_MUX		(CLK_ID_PLL + CLK_NR_PLL)
++#define CLK_MUX_SCLKA		(CLK_ID_MUX + 0)
++#define CLK_MUX_CPU_L2C		(CLK_ID_MUX + 1)
++#define CLK_MUX_AHB0		(CLK_ID_MUX + 2)
++#define CLK_MUX_AHB2		(CLK_ID_MUX + 3)
++#define CLK_MUX_DDR		(CLK_ID_MUX + 4)
++#define CLK_MUX_MACPHY		(CLK_ID_MUX + 5)
++#define CLK_MUX_MACTXPHY	(CLK_ID_MUX + 6)
++#define CLK_MUX_MACTXPHY1	(CLK_ID_MUX + 7)
++#define CLK_MUX_I2S0		(CLK_ID_MUX + 8)
++#define CLK_MUX_I2S1		(CLK_ID_MUX + 9)
++#define CLK_MUX_I2S2            (CLK_ID_MUX + 10)
++#define CLK_MUX_I2S3            (CLK_ID_MUX + 11)
++#define CLK_MUX_AUDIO_RAM       (CLK_ID_MUX + 12)
++#define CLK_MUX_SPDIF           (CLK_ID_MUX + 13)
++#define CLK_MUX_PCM             (CLK_ID_MUX + 14)
++#define CLK_MUX_DMIC            (CLK_ID_MUX + 15)
++#define CLK_MUX_LCD             (CLK_ID_MUX + 16)
++#define CLK_MUX_MSC0            (CLK_ID_MUX + 17)
++#define CLK_MUX_MSC1		(CLK_ID_MUX + 18)
++#define CLK_MUX_MSC2            (CLK_ID_MUX + 19)
++#define CLK_MUX_SFC             (CLK_ID_MUX + 20)
++#define CLK_MUX_SSI             (CLK_ID_MUX + 21)
++#define CLK_MUX_CIM             (CLK_ID_MUX + 22)
++#define CLK_MUX_PWM             (CLK_ID_MUX + 23)
++#define CLK_MUX_ISP             (CLK_ID_MUX + 24)
++#define CLK_MUX_RSA             (CLK_ID_MUX + 25)
++#define CLK_MUX_MACPTP		(CLK_ID_MUX + 26)
++#define CLK_MUX_WDT		(CLK_ID_MUX + 27)
++
++
++#define CLK_NR_MUX		(28)
++
++
++#define CLK_ID_DIV		(CLK_ID_MUX + CLK_NR_MUX)
++#define CLK_DIV_DDR		(CLK_ID_DIV + 0)
++#define CLK_DIV_MACPHY		(CLK_ID_DIV + 1)
++#define CLK_DIV_MACTXPHY	(CLK_ID_DIV + 2)
++#define CLK_DIV_MACTXPHY1       (CLK_ID_DIV + 3)
++#define CLK_DIV_I2S0		(CLK_ID_DIV + 4)
++#define CLK_DIV_I2S1            (CLK_ID_DIV + 5)
++#define CLK_DIV_I2S2            (CLK_ID_DIV + 6)
++#define CLK_DIV_I2S3            (CLK_ID_DIV + 7)
++#define CLK_DIV_LCD		(CLK_ID_DIV + 8)
++#define CLK_DIV_MSC0            (CLK_ID_DIV + 9)
++#define CLK_DIV_MSC1            (CLK_ID_DIV + 10)
++#define CLK_DIV_MSC2            (CLK_ID_DIV + 11)
++#define CLK_DIV_SFC             (CLK_ID_DIV + 12)
++#define CLK_DIV_SSI             (CLK_ID_DIV + 13)
++#define CLK_DIV_CIM             (CLK_ID_DIV + 14)
++#define CLK_DIV_PWM             (CLK_ID_DIV + 15)
++#define CLK_DIV_ISP		(CLK_ID_DIV + 16)
++#define CLK_DIV_RSA             (CLK_ID_DIV + 17)
++#define CLK_DIV_MACPTP		(CLK_ID_DIV + 18)
++
++#define CLK_DIV_CPU		(CLK_ID_DIV + 19)
++#define CLK_DIV_L2C             (CLK_ID_DIV + 20)
++#define CLK_DIV_AHB0            (CLK_ID_DIV + 21)
++#define CLK_DIV_AHB2            (CLK_ID_DIV + 22)
++#define CLK_DIV_APB             (CLK_ID_DIV + 23)
++#define CLK_DIV_CPU_L2C_X1      (CLK_ID_DIV + 24)
++#define CLK_DIV_CPU_L2C_X2      (CLK_ID_DIV + 25)
++
++#define CLK_NR_DIV		(26)
++
++
++/* Gate Clocks */
++#define CLK_ID_GATE		(CLK_ID_DIV + CLK_NR_DIV)
++#define CLK_GATE_DDR		(CLK_ID_GATE + 0)
++#define CLK_GATE_IPU		(CLK_ID_GATE + 1)
++#define CLK_GATE_AHB0		(CLK_ID_GATE + 2)
++#define CLK_GATE_APB0		(CLK_ID_GATE + 3)
++#define CLK_GATE_RTC		(CLK_ID_GATE + 4)
++#define CLK_GATE_SSI1		(CLK_ID_GATE + 5)
++#define CLK_GATE_RSA		(CLK_ID_GATE + 6)
++#define CLK_GATE_AES		(CLK_ID_GATE + 7)
++#define CLK_GATE_LCD		(CLK_ID_GATE + 8)
++#define CLK_GATE_CIM		(CLK_ID_GATE + 9)
++#define CLK_GATE_PDMA		(CLK_ID_GATE + 10)
++#define CLK_GATE_OST		(CLK_ID_GATE + 11)
++#define CLK_GATE_SSI0		(CLK_ID_GATE + 12)
++#define CLK_GATE_TCU		(CLK_ID_GATE + 13)
++#define CLK_GATE_DTRNG		(CLK_ID_GATE + 14)
++#define CLK_GATE_UART2		(CLK_ID_GATE + 15)
++#define CLK_GATE_UART1		(CLK_ID_GATE + 16)
++#define CLK_GATE_UART0		(CLK_ID_GATE + 17)
++#define CLK_GATE_SADC		(CLK_ID_GATE + 18)
++#define CLK_GATE_HELIX		(CLK_ID_GATE + 19)
++#define CLK_GATE_AUDIO		(CLK_ID_GATE + 20)
++#define CLK_GATE_SMB3		(CLK_ID_GATE + 21)
++#define CLK_GATE_SMB2		(CLK_ID_GATE + 22)
++#define CLK_GATE_SMB1		(CLK_ID_GATE + 23)
++#define CLK_GATE_SMB0		(CLK_ID_GATE + 24)
++#define CLK_GATE_SCC		(CLK_ID_GATE + 25)
++#define CLK_GATE_MSC1		(CLK_ID_GATE + 26)
++#define CLK_GATE_MSC0		(CLK_ID_GATE + 27)
++#define CLK_GATE_OTG		(CLK_ID_GATE + 28)
++#define CLK_GATE_SFC		(CLK_ID_GATE + 29)
++#define CLK_GATE_EFUSE		(CLK_ID_GATE + 30)
++#define CLK_GATE_NEMC		(CLK_ID_GATE + 31)
++#define CLK_GATE_ARB		(CLK_ID_GATE + 32)
++#define CLK_GATE_MIPI_DSI	(CLK_ID_GATE + 33)
++#define CLK_GATE_MIPI_CSI	(CLK_ID_GATE + 34)
++#define CLK_GATE_INTC		(CLK_ID_GATE + 35)
++#define CLK_GATE_MSC2		(CLK_ID_GATE + 36)
++#define CLK_GATE_GMAC1		(CLK_ID_GATE + 37)
++#define CLK_GATE_GMAC0		(CLK_ID_GATE + 38)
++#define CLK_GATE_UART9		(CLK_ID_GATE + 39)
++#define CLK_GATE_UART8		(CLK_ID_GATE + 40)
++#define CLK_GATE_UART7		(CLK_ID_GATE + 41)
++#define CLK_GATE_UATR6		(CLK_ID_GATE + 42)
++#define CLK_GATE_UART5		(CLK_ID_GATE + 43)
++#define CLK_GATE_UART4		(CLK_ID_GATE + 44)
++#define CLK_GATE_UART3		(CLK_ID_GATE + 45)
++#define CLK_GATE_SPDIF		(CLK_ID_GATE + 46)
++#define CLK_GATE_DMIC		(CLK_ID_GATE + 47)
++#define CLK_GATE_PCM		(CLK_ID_GATE + 48)
++#define CLK_GATE_I2S3		(CLK_ID_GATE + 49)
++#define CLK_GATE_I2S2		(CLK_ID_GATE + 50)
++#define CLK_GATE_I2S1		(CLK_ID_GATE + 51)
++#define CLK_GATE_I2S0		(CLK_ID_GATE + 52)
++#define CLK_GATE_ROT		(CLK_ID_GATE + 53)
++#define CLK_GATE_HASH		(CLK_ID_GATE + 54)
++#define CLK_GATE_PWM		(CLK_ID_GATE + 55)
++#define CLK_GATE_FELIX		(CLK_ID_GATE + 56)
++#define CLK_GATE_ISP1		(CLK_ID_GATE + 57)
++#define CLK_GATE_ISP0		(CLK_ID_GATE + 58)
++#define CLK_GATE_SMB5		(CLK_ID_GATE + 59)
++#define CLK_GATE_SMB4		(CLK_ID_GATE + 60)
++#define CLK_GATE_USBPHY		(CLK_ID_GATE + 61)
++#define CLK_CE_I2S0		(CLK_ID_GATE + 62)
++#define CLK_CE_I2S1		(CLK_ID_GATE + 63)
++#define CLK_CE_I2S2		(CLK_ID_GATE + 64)
++#define CLK_CE_I2S3		(CLK_ID_GATE + 65)
++#define CLK_NR_GATE		(66)
++
++#define POWER_ID		(CLK_ID_GATE + CLK_NR_GATE)
++#define POWER_ISP0		(POWER_ID + 0)
++#define POWER_ISP1		(POWER_ID + 1)
++#define POWER_FELIX		(POWER_ID + 2)
++#define POWER_HELIX		(POWER_ID + 3)
++
++#define PD_MEM_NEMC    		(POWER_ID + 4)
++#define PD_MEM_USB     		(POWER_ID + 5)
++#define PD_MEM_SFC     		(POWER_ID + 6)
++#define PD_MEM_PDMA_SEC		(POWER_ID + 7)
++#define PD_MEM_PDMA    		(POWER_ID + 8)
++#define PD_MEM_MSC2    		(POWER_ID + 9)
++#define PD_MEM_MSC1    		(POWER_ID + 10)
++#define PD_MEM_MSC0    		(POWER_ID + 11)
++#define PD_MEM_GMAC1   		(POWER_ID + 12)
++#define PD_MEM_GMAC0   		(POWER_ID + 13)
++#define PD_MEM_DMIC    		(POWER_ID + 14)
++#define PD_MEM_AUDIO   		(POWER_ID + 15)
++#define PD_MEM_AES     		(POWER_ID + 16)
++#define PD_MEM_DSI     		(POWER_ID + 17)
++#define PD_MEM_SSI1    		(POWER_ID + 18)
++#define PD_MEM_SSI0    		(POWER_ID + 19)
++#define PD_MEM_UART9   		(POWER_ID + 20)
++#define PD_MEM_UART8   		(POWER_ID + 21)
++#define PD_MEM_UART7   		(POWER_ID + 22)
++#define PD_MEM_UART6   		(POWER_ID + 23)
++#define PD_MEM_UART5   		(POWER_ID + 24)
++#define PD_MEM_UART4   		(POWER_ID + 25)
++#define PD_MEM_UART3   		(POWER_ID + 26)
++#define PD_MEM_UART2   		(POWER_ID + 27)
++#define PD_MEM_UART1   		(POWER_ID + 28)
++#define PD_MEM_UART0   		(POWER_ID + 29)
++#define PD_MEM_ROT     		(POWER_ID + 30)
++#define PD_MEM_CIM     		(POWER_ID + 31)
++#define PD_MEM_DPU     		(POWER_ID + 32)
++#define PD_MEM_DDR_CH6 		(POWER_ID + 33)
++#define PD_MEM_DDR_CH5 		(POWER_ID + 34)
++#define PD_MEM_DDR_CH3 		(POWER_ID + 35)
++#define PD_MEM_DDR_CH1 		(POWER_ID + 36)
++#define PD_MEM_DDR_CH0 		(POWER_ID + 37)
++#define PD_MEM_DDR_TOP 		(POWER_ID + 38)
++#define CLK_NR_POWER		(39)
++
++#define CLK_ID_OTHER		(POWER_ID + CLK_NR_POWER)
++
++#define NR_CLKS		(CLK_NR_FIXED + CLK_NR_PLL + CLK_NR_MUX + CLK_NR_DIV + CLK_NR_GATE + CLK_NR_POWER)
++#endif
+diff --git a/include/dt-bindings/clock/ingenic-x2500.h b/include/dt-bindings/clock/ingenic-x2500.h
+new file mode 100644
+index 000000000..02630d04d
+--- /dev/null
++++ b/include/dt-bindings/clock/ingenic-x2500.h
+@@ -0,0 +1,136 @@
++#ifndef _DT_BINDINGS_CLOCK_X2500_H
++#define _DT_BINDINGS_CLOCK_X2500_H
++
++/* Fixed Clk */
++#define CLK_ID_FIEXED	0
++#define	CLK_EXT		    (CLK_ID_FIEXED + 0)
++#define	CLK_RTC_EXT	    (CLK_ID_FIEXED + 1)
++#define CLK_NR_FIXED	(2)
++
++/* PLL clk */
++#define CLK_ID_PLL	    (CLK_ID_FIEXED + CLK_NR_FIXED)
++#define CLK_PLL_APLL	(CLK_ID_PLL + 0)
++#define CLK_PLL_MPLL	(CLK_ID_PLL + 1)
++#define CLK_PLL_VPLL	(CLK_ID_PLL + 2)
++#define CLK_PLL_EPLL	(CLK_ID_PLL + 3)
++#define CLK_NR_PLL	    (4)
++
++/* MUX clk */
++#define CLK_ID_MUX		        (CLK_ID_PLL + CLK_NR_PLL)
++#define CLK_MUX_SCLKA		    (CLK_ID_MUX + 0)
++#define CLK_MUX_CPU_L2C		    (CLK_ID_MUX + 1)
++#define CLK_MUX_AHB0		    (CLK_ID_MUX + 2)
++#define CLK_MUX_AHB2		    (CLK_ID_MUX + 3)
++#define CLK_MUX_PCLK		    (CLK_ID_MUX + 4)
++#define CLK_MUX_DDR		        (CLK_ID_MUX + 5)
++#define CLK_MUX_MACPHY		    (CLK_ID_MUX + 6)
++#define CLK_MUX_LCD             (CLK_ID_MUX + 7)
++#define CLK_MUX_MSC0            (CLK_ID_MUX + 8)
++#define CLK_MUX_MSC1		    (CLK_ID_MUX + 9)
++#define CLK_MUX_SFC             (CLK_ID_MUX + 10)
++#define CLK_MUX_SSI             (CLK_ID_MUX + 11)
++#define CLK_MUX_CIM0            (CLK_ID_MUX + 12)
++#define CLK_MUX_CIM1            (CLK_ID_MUX + 13)
++#define CLK_MUX_CIM2            (CLK_ID_MUX + 14)
++#define CLK_MUX_ISP             (CLK_ID_MUX + 15)
++#define CLK_MUX_RSA             (CLK_ID_MUX + 16)
++#define CLK_MUX_EL150           (CLK_ID_MUX + 17)
++#define CLK_MUX_I2ST            (CLK_ID_MUX + 18)
++#define CLK_MUX_I2SR            (CLK_ID_MUX + 19)
++#define CLK_MUX_BSCALER         (CLK_ID_MUX + 20)
++#define CLK_MUX_BT0             (CLK_ID_MUX + 21)
++#define CLK_MUX_BT1             (CLK_ID_MUX + 22)
++
++#define CLK_NR_MUX		(23)
++
++
++#define CLK_ID_DIV		        (CLK_ID_MUX + CLK_NR_MUX)
++#define CLK_DIV_DDR		        (CLK_ID_DIV + 0)
++#define CLK_DIV_MACPHY		    (CLK_ID_DIV + 1)
++#define CLK_DIV_LCD		        (CLK_ID_DIV + 2)
++#define CLK_DIV_MSC0            (CLK_ID_DIV + 3)
++#define CLK_DIV_MSC1            (CLK_ID_DIV + 4)
++#define CLK_DIV_SFC             (CLK_ID_DIV + 5)
++#define CLK_DIV_SSI             (CLK_ID_DIV + 6)
++#define CLK_DIV_CIM0            (CLK_ID_DIV + 7)
++#define CLK_DIV_CIM1            (CLK_ID_DIV + 8)
++#define CLK_DIV_CIM2            (CLK_ID_DIV + 9)
++#define CLK_DIV_ISP		        (CLK_ID_DIV + 10)
++#define CLK_DIV_RSA             (CLK_ID_DIV + 11)
++#define CLK_DIV_EL150           (CLK_ID_DIV + 12)
++#define CLK_DIV_I2ST          (CLK_ID_DIV + 13)
++#define CLK_DIV_I2SR          (CLK_ID_DIV + 14)
++#define CLK_DIV_BSCALER         (CLK_ID_DIV + 15)
++#define CLK_DIV_BT0             (CLK_ID_DIV + 16)
++#define CLK_DIV_BT1             (CLK_ID_DIV + 17)
++
++#define CLK_DIV_CPU		        (CLK_ID_DIV + 18)
++#define CLK_DIV_L2C             (CLK_ID_DIV + 19)
++#define CLK_DIV_AHB0            (CLK_ID_DIV + 20)
++#define CLK_DIV_AHB2            (CLK_ID_DIV + 21)
++#define CLK_DIV_APB             (CLK_ID_DIV + 22)
++#define CLK_DIV_CPU_L2C         (CLK_ID_DIV + 23)
++#define CLK_DIV_CPU_L2C_X1      (CLK_ID_DIV + 24)
++#define CLK_DIV_CPU_L2C_X2      (CLK_ID_DIV + 25)
++
++#define CLK_NR_DIV		        (26)
++
++
++/* Gate Clocks */
++#define CLK_ID_GATE		        (CLK_ID_DIV + CLK_NR_DIV)
++#define CLK_GATE_DDR		    (CLK_ID_GATE + 0)
++#define CLK_GATE_TCU		    (CLK_ID_GATE + 1)
++#define CLK_GATE_RESERVER29		(CLK_ID_GATE + 2)
++#define CLK_GATE_DES		    (CLK_ID_GATE + 3)
++#define CLK_GATE_RSA		    (CLK_ID_GATE + 4)
++#define CLK_GATE_VO	        	(CLK_ID_GATE + 5)
++#define CLK_GATE_MIPI_CSI		(CLK_ID_GATE + 6)
++#define CLK_GATE_LCD		    (CLK_ID_GATE + 7)
++#define CLK_GATE_ISP		    (CLK_ID_GATE + 8)
++#define CLK_GATE_PDMA		    (CLK_ID_GATE + 9)
++#define CLK_GATE_SFC		    (CLK_ID_GATE + 10)
++#define CLK_GATE_SSI1		    (CLK_ID_GATE + 11)
++#define CLK_GATE_HASH		    (CLK_ID_GATE + 12)
++#define CLK_GATE_SLV		    (CLK_ID_GATE + 13)
++#define CLK_GATE_UART3		    (CLK_ID_GATE + 14)
++#define CLK_GATE_UART2		    (CLK_ID_GATE + 15)
++#define CLK_GATE_UART1		    (CLK_ID_GATE + 16)
++#define CLK_GATE_UART0		    (CLK_ID_GATE + 17)
++#define CLK_GATE_SADC		    (CLK_ID_GATE + 18)
++#define CLK_GATE_DMIC		    (CLK_ID_GATE + 19)
++#define CLK_GATE_AIC		    (CLK_ID_GATE + 20)
++#define CLK_GATE_SMB3		    (CLK_ID_GATE + 21)
++#define CLK_GATE_SMB2		    (CLK_ID_GATE + 22)
++#define CLK_GATE_SMB1		    (CLK_ID_GATE + 23)
++#define CLK_GATE_SMB0		    (CLK_ID_GATE + 24)
++#define CLK_GATE_SSI0		    (CLK_ID_GATE + 25)
++#define CLK_GATE_MSC1		    (CLK_ID_GATE + 26)
++#define CLK_GATE_MSC0		    (CLK_ID_GATE + 27)
++#define CLK_GATE_OTG		    (CLK_ID_GATE + 28)
++#define CLK_GATE_BSCALER		(CLK_ID_GATE + 29)
++#define CLK_GATE_EFUSE		    (CLK_ID_GATE + 30)
++#define CLK_GATE_NEMC		    (CLK_ID_GATE + 31)
++#define CLK_GATE_CPU		    (CLK_ID_GATE + 32)
++#define CLK_GATE_APB0	        (CLK_ID_GATE + 33)
++#define CLK_GATE_RESERVER13	    (CLK_ID_GATE + 34)
++#define CLK_GATE_RESERVER12		(CLK_ID_GATE + 35)
++#define CLK_GATE_OST		    (CLK_ID_GATE + 36)
++#define CLK_GATE_AHB0		    (CLK_ID_GATE + 37)
++#define CLK_GATE_BUS_MONITOR	(CLK_ID_GATE + 38)
++#define CLK_GATE_I2D		    (CLK_ID_GATE + 39)
++#define CLK_GATE_MIPI_DSI		(CLK_ID_GATE + 40)
++#define CLK_GATE_DRAWBOX		(CLK_ID_GATE + 41)
++#define CLK_GATE_AES		    (CLK_ID_GATE + 42)
++#define CLK_GATE_GMAC		    (CLK_ID_GATE + 43)
++#define CLK_GATE_AHB1		    (CLK_ID_GATE + 44)
++#define CLK_GATE_IPU		    (CLK_ID_GATE + 45)
++#define CLK_GATE_DTRNG		    (CLK_ID_GATE + 46)
++#define CLK_GATE_EL150		    (CLK_ID_GATE + 47)
++#define CLK_CE_I2ST		        (CLK_ID_GATE + 48)
++#define CLK_CE_I2SR		        (CLK_ID_GATE + 49)
++#define CLK_GATE_USBPHY         (CLK_ID_GATE + 50)
++#define CLK_NR_GATE		        (61)
++#define CLK_ID_OTHER		    (CLK_ID_GATE + CLK_NR_GATE)
++
++#define NR_CLKS		(CLK_NR_FIXED + CLK_NR_PLL + CLK_NR_MUX + CLK_NR_DIV + CLK_NR_GATE)
++#endif
+diff --git a/include/dt-bindings/dma/ingenic-pdma.h b/include/dt-bindings/dma/ingenic-pdma.h
+new file mode 100644
+index 000000000..d06583ed3
+--- /dev/null
++++ b/include/dt-bindings/dma/ingenic-pdma.h
+@@ -0,0 +1,89 @@
++#ifndef __INGENIC_PDMA_H__
++#define __INGENIC_PDMA_H__
++#include<generated/autoconf.h>
++
++#ifndef CONFIG_SOC_X2500
++#define INGENIC_DMA_REQ_DMIC_RX		0x5
++#else
++#define INGENIC_DMA_REQ_DMIC_RX		0xd
++#endif
++#define INGENIC_DMA_REQ_I2S_TX		0x6
++#define INGENIC_DMA_REQ_I2S_RX		0x7
++#define INGENIC_DMA_REQ_AUTO_TX		0x8
++#define INGENIC_DMA_REQ_SADC_RX		0x9
++#define INGENIC_DMA_REQ_UART4_TX	0xc
++#define INGENIC_DMA_REQ_UART4_RX	0xd
++#define INGENIC_DMA_REQ_UART3_TX	0xe
++#define INGENIC_DMA_REQ_UART3_RX	0xf
++#define INGENIC_DMA_REQ_UART2_TX	0x10
++#define INGENIC_DMA_REQ_UART2_RX	0x11
++#define INGENIC_DMA_REQ_UART1_TX	0x12
++#define INGENIC_DMA_REQ_UART1_RX	0x13
++#define INGENIC_DMA_REQ_UART0_TX	0x14
++#define INGENIC_DMA_REQ_UART0_RX	0x15
++#define INGENIC_DMA_REQ_SSI0_TX		0x16
++#define INGENIC_DMA_REQ_SSI0_RX		0x17
++#define INGENIC_DMA_REQ_SSI1_TX		0x18
++#define INGENIC_DMA_REQ_SSI1_RX		0x19
++#define INGENIC_DMA_REQ_MSC0_TX		0x1a
++#define INGENIC_DMA_REQ_MSC0_RX		0x1b
++#define INGENIC_DMA_REQ_MSC1_TX		0x1c
++#define INGENIC_DMA_REQ_MSC1_RX		0x1d
++#define INGENIC_DMA_REQ_MSC2_TX		0x1e
++#define INGENIC_DMA_REQ_MSC2_RX		0x1f
++#define INGENIC_DMA_REQ_PCM_TX		0X20
++#define INGENIC_DMA_REQ_PCM_RX		0X21
++#define INGENIC_DMA_REQ_I2C0_TX		0x24
++#define INGENIC_DMA_REQ_I2C0_RX		0x25
++#define INGENIC_DMA_REQ_I2C1_TX		0x26
++#define INGENIC_DMA_REQ_I2C1_RX		0x27
++#define INGENIC_DMA_REQ_I2C2_TX		0x28
++#define INGENIC_DMA_REQ_I2C2_RX		0x29
++#define INGENIC_DMA_REQ_I2C3_TX		0x2a
++#define INGENIC_DMA_REQ_I2C3_RX		0x2b
++#define INGENIC_DMA_REQ_I2C4_TX		0x2c
++#define INGENIC_DMA_REQ_I2C4_RX		0x2d
++#define INGENIC_DMA_REQ_DES_TX		0x2e
++#define INGENIC_DMA_REQ_DES_RX		0x2f
++
++
++/* define for x1600 */
++
++#define INGENIC_DMA_REQ_CAN0_TX		0xa
++#define INGENIC_DMA_REQ_CAN0_RX		0xb
++#define INGENIC_DMA_REQ_CAN1_TX		0xc
++#define INGENIC_DMA_REQ_CAN1_RX		0xd
++#define INGENIC_DMA_REQ_SLV0_TX		0x2a
++#define INGENIC_DMA_REQ_SLV0_RX		0x2b
++#define INGENIC_DMA_REQ_PWM0_TX		0x2c
++#define INGENIC_DMA_REQ_PWM1_TX		0x2d
++#define INGENIC_DMA_REQ_PWM2_TX		0x2e
++#define INGENIC_DMA_REQ_PWM3_TX		0x2f
++#define INGENIC_DMA_REQ_PWM4_TX		0x30
++#define INGENIC_DMA_REQ_PWM5_TX		0x31
++#define INGENIC_DMA_REQ_PWM6_TX		0x32
++#define INGENIC_DMA_REQ_PWM7_TX		0x33
++#define INGENIC_DMA_REQ_ASOC_AIC_LOOP	0x3d
++#define INGENIC_DMA_REQ_ASOC_AIC_TX	0x3e
++#define INGENIC_DMA_REQ_ASOC_AIC_RX	0x3f
++
++/* define for x2500 */
++#define INGENIC_DMA_REQ_AIC_LOOP_RX	0x5
++#define INGENIC_DMA_REQ_AIC_TX	    	0x6
++#define INGENIC_DMA_REQ_AIC_F_RX	0x7
++#define INGENIC_DMA_REQ_SLV_TX		0x1a
++#define INGENIC_DMA_REQ_SLV_RX		0x1b
++
++#define INGENIC_DMA_TYPE_REQ_MSK	0xff
++#define INGENIC_DMA_TYPE_CH_SFT		8
++#define INGENIC_DMA_TYPE_CH_MSK		(0xff << INGENIC_DMA_TYPE_CH_SFT)
++#define INGENIC_DMA_TYPE_CH_EN		(1 << 16)
++#define INGENIC_DMA_TYPE_PROG		(1 << 17)
++#define INGENIC_DMA_TYPE_SPEC		(1 << 18)
++
++#define INGENIC_DMA_CH(ch)		((((ch) << INGENIC_DMA_TYPE_CH_SFT) & INGENIC_DMA_TYPE_CH_MSK) | INGENIC_DMA_TYPE_CH_EN)
++#define INGENIC_DMA_TYPE(type)	((type) & INGENIC_DMA_TYPE_REQ_MSK)
++#define INGENIC_DMA_TYPE_CH(type, ch)	(INGENIC_DMA_TYPE((type)) | INGENIC_DMA_CH((ch)))
++#define INGENIC_DMA_PG_CH(type, ch)	(INGENIC_DMA_TYPE_CH((type), (ch)) | INGENIC_DMA_TYPE_PROG_MSK)
++#define INGENIC_DMA_SP_CH(type, ch)	(INGENIC_DMA_PG_CH(type, id) | INGENIC_DMA_TYPE_SPEC_MSK)
++#endif	/* __INGENIC_PDMA_H__ */
+diff --git a/include/dt-bindings/gpio/ingenic-gpio.h b/include/dt-bindings/gpio/ingenic-gpio.h
+new file mode 100644
+index 000000000..6df94b339
+--- /dev/null
++++ b/include/dt-bindings/gpio/ingenic-gpio.h
+@@ -0,0 +1,8 @@
++#ifndef __INGENIC_GPIO_H_
++#define __INGENIC_GPIO_H_
++
++#define GPIO_VOLTAGE_1V8	1
++#define GPIO_VOLTAGE_3V3	2
++
++#endif
++
+diff --git a/include/dt-bindings/interrupt-controller/m300-irq.h b/include/dt-bindings/interrupt-controller/m300-irq.h
+new file mode 100644
+index 000000000..afd5069c6
+--- /dev/null
++++ b/include/dt-bindings/interrupt-controller/m300-irq.h
+@@ -0,0 +1,72 @@
++#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_M300_IRQ_H
++#define _DT_BINDINGS_INTERRUPT_CONTROLLER_M300_IRQ_H
++
++#include <dt-bindings/interrupt-controller/mips-irq.h>
++
++#define IRQ_AUDIO			(0)
++#define IRQ_OTG				(1)
++#define IRQ_RESERVED0_2			(2)
++#define IRQ_PDMA			(3)
++#define IRQ_PDMAD			(4)
++#define IRQ_PDMAM			(5)
++#define IRQ_PWM				(6)
++#define IRQ_SFC				(7)
++#define IRQ_SSI1			(8)
++#define IRQ_SSI0			(9)
++#define IRQ_MIPI_DSI			(10)
++#define IRQ_SADC			(11)
++#define IRQ_MIPI_CSI_4			(12)
++#define IRQ_GPIO4			(13)
++#define IRQ_GPIO3			(14)
++#define IRQ_GPIO2			(15)
++#define IRQ_GPIO1			(16)
++#define IRQ_GPIO0			(17)
++#define IRQ_VIC1			(18)
++#define IRQ_VIC0			(19)
++#define IRQ_ISP1			(20)
++#define IRQ_ISP0			(21)
++#define IRQ_HASH			(22)
++#define IRQ_AES				(23)
++#define IRQ_RSA				(24)
++#define IRQ_TCU2			(25)
++#define IRQ_TCU1			(26)
++#define IRQ_TCU0			(27)
++#define IRQ_MIPI_CSI2			(28)
++#define IRQ_ROTATE			(29)
++#define IRQ_CIM				(30)
++#define IRQ_LCD				(31)
++
++#define IRQ_RTC				(32 + 0)
++#define IRQ_SOFT			(32 + 1)
++#define IRQ_DTRNG			(32 + 2)
++#define IRQ_SCC				(32 + 3)
++#define IRQ_MSC1			(32 + 4)
++#define IRQ_MSC0			(32 + 5)
++#define IRQ_UART9			(32 + 6)
++#define IRQ_UART8			(32 + 7)
++#define IRQ_UART7			(32 + 8)
++#define IRQ_UART6			(32 + 9)
++#define IRQ_UART5			(32 + 10)
++#define IRQ_UART4			(32 + 11)
++#define IRQ_UART3			(32 + 12)
++#define IRQ_UART2			(32 + 13)
++#define IRQ_UART1			(32 + 14)
++#define IRQ_UART0			(32 + 15)
++#define IRQ_MSC2			(32 + 16)
++#define IRQ_HARB2			(32 + 17)
++#define IRQ_HARB0			(32 + 18)
++#define IRQ_CPM				(32 + 19)
++#define IRQ_DDR				(32 + 20)
++#define IRQ_GMAC1			(32 + 21)
++#define IRQ_EFUSE			(32 + 22)
++#define IRQ_GMAC0			(32 + 23)
++#define IRQ_I2C5			(32 + 24)
++#define IRQ_I2C4			(32 + 25)
++#define IRQ_I2C3			(32 + 26)
++#define IRQ_I2C2			(32 + 27)
++#define IRQ_I2C1			(32 + 28)
++#define IRQ_I2C0			(32 + 29)
++#define IRQ_HELIX			(32 + 30)
++#define IRQ_FELIX			(32 + 31)
++
++#endif
+diff --git a/include/dt-bindings/interrupt-controller/mips-irq.h b/include/dt-bindings/interrupt-controller/mips-irq.h
+new file mode 100644
+index 000000000..963d38f58
+--- /dev/null
++++ b/include/dt-bindings/interrupt-controller/mips-irq.h
+@@ -0,0 +1,16 @@
++#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_IRQ_H
++#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_IRQ_H
++
++#define MIPS_CPU_IRQ_BASE	(0)
++
++#define CORE_INTC_IRQ       (MIPS_CPU_IRQ_BASE + 2)
++#define CORE_MAILBOX_IRQ    (MIPS_CPU_IRQ_BASE + 3)
++#define CORE_SYS_OST_IRQ    (MIPS_CPU_IRQ_BASE + 4)
++
++#define CORE_IRQS_END	(7)
++
++#define INTC_NR_IRQS    (64)
++#define IRQ_INTC_BASE   (CORE_IRQS_END + 1)
++#define IRQ_INTC_END    (IRQ_INTC_BASE + INTC_NR_IRQS - 1)
++
++#endif
+diff --git a/include/dt-bindings/interrupt-controller/x1000-irq.h b/include/dt-bindings/interrupt-controller/x1000-irq.h
+new file mode 100644
+index 000000000..4cc671674
+--- /dev/null
++++ b/include/dt-bindings/interrupt-controller/x1000-irq.h
+@@ -0,0 +1,72 @@
++#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_X1000_IRQ_H
++#define _DT_BINDINGS_INTERRUPT_CONTROLLER_X1000_IRQ_H
++
++#include <dt-bindings/interrupt-controller/mips-irq.h>
++
++#define IRQ_DMIC			(0)
++#define IRQ_AIC0				(1)
++#define IRQ_RESERVED0_2			(2)
++#define IRQ_RESERVED0_3			(3)
++#define IRQ_RESERVED0_4			(4)
++#define IRQ_RESERVED0_5			(5)
++#define IRQ_RESERVED0_6				(6)
++#define IRQ_SFC				(7)
++#define IRQ_SSI0			(8)
++#define IRQ_RESERVED0_9			(9)
++#define IRQ_PDMA			(10)
++#define IRQ_PDMAD			(11)
++#define IRQ_RESERVED0_12			(12)
++#define IRQ_RESERVED0_13			(13)
++#define IRQ_GPIO3			(14)
++#define IRQ_GPIO2			(15)
++#define IRQ_GPIO1			(16)
++#define IRQ_GPIO0			(17)
++#define IRQ_RESERVED0_18			(18)
++#define IRQ_RESERVED0_19			(19)
++#define IRQ_RESERVED0_20			(20)
++#define IRQ_OTG			(21)
++#define IRQ_RESERVED0_22			(22)
++#define IRQ_AES				(23)
++#define IRQ_RESERVED0_24				(24)
++#define IRQ_TCU2			(25)
++#define IRQ_TCU1			(26)
++#define IRQ_TCU0			(27)
++#define IRQ_RESERVED0_28			(28)
++#define IRQ_RESERVED0_29			(29)
++#define IRQ_CIM				(30)
++#define IRQ_LCD				(31)
++
++#define IRQ_RTC				(32 + 0)
++#define IRQ_RESERVED1_1			(32 + 1)
++#define IRQ_RESERVED1_2			(32 + 2)
++#define IRQ_RESERVED1_3				(32 + 3)
++#define IRQ_MSC1			(32 + 4)
++#define IRQ_MSC0			(32 + 5)
++#define IRQ_SCC			(32 + 6)
++#define IRQ_RESERVED1_7			(32 + 7)
++#define IRQ_PCM0			(32 + 8)
++#define IRQ_RESERVED1_9			(32 + 9)
++#define IRQ_RESERVED1_10			(32 + 10)
++#define IRQ_RESERVED1_11			(32 + 11)
++#define IRQ_HARB2			(32 + 12)
++#define IRQ_RESERVED1_13			(32 + 13)
++#define IRQ_HARB0			(32 + 14)
++#define IRQ_CPM			(32 + 15)
++#define IRQ_RESERVED1_16			(32 + 16)
++#define IRQ_UART2			(32 + 17)
++#define IRQ_UART1			(32 + 18)
++#define IRQ_UART0				(32 + 19)
++#define IRQ_DDR				(32 + 20)
++#define IRQ_RESERVED1_21			(32 + 21)
++#define IRQ_EFUSE			(32 + 22)
++#define IRQ_MAC			(32 + 23)
++#define IRQ_RESERVED1_24			(32 + 24)
++#define IRQ_RESERVED1_25			(32 + 25)
++#define IRQ_I2C2			(32 + 26)
++#define IRQ_I2C1			(32 + 27)
++#define IRQ_I2C0			(32 + 28)
++#define IRQ_PDMAM			(32 + 29)
++#define IRQ_JPEG			(32 + 30)
++#define IRQ_RESERVED1_31			(32 + 31)
++
++#endif
+diff --git a/include/dt-bindings/interrupt-controller/x1600-irq.h b/include/dt-bindings/interrupt-controller/x1600-irq.h
+new file mode 100644
+index 000000000..2d313dc28
+--- /dev/null
++++ b/include/dt-bindings/interrupt-controller/x1600-irq.h
+@@ -0,0 +1,72 @@
++#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_X1600_IRQ_H
++#define _DT_BINDINGS_INTERRUPT_CONTROLLER_X1600_IRQ_H
++
++#include <dt-bindings/interrupt-controller/mips-irq.h>
++
++#define IRQ_AUDIO			(0)
++#define IRQ_OTG				(1)
++#define IRQ_RESERVED0_2			(2)
++#define IRQ_PDMA			(3)
++#define IRQ_PDMAD			(4)
++#define IRQ_PDMAM			(5)
++#define IRQ_PWM				(6)
++#define IRQ_SFC				(7)
++#define IRQ_RESERVED0_8			(8)
++#define IRQ_SSI0			(9)
++#define IRQ_RESERVED0_10		(10)
++#define IRQ_SADC			(11)
++#define IRQ_RESERVED0_12		(12)
++#define IRQ_RESERVED0_13		(13)
++#define IRQ_GPIO3			(14)
++#define IRQ_GPIO2			(15)
++#define IRQ_GPIO1			(16)
++#define IRQ_GPIO0			(17)
++#define IRQ_RESERVED0_18		(18)
++#define IRQ_RESERVED0_19		(19)
++#define IRQ_RESERVED0_20		(20)
++#define IRQ_RESERVED0_21		(21)
++#define IRQ_HASH			(22)
++#define IRQ_AES				(23)
++#define IRQ_RESERVED0_14		(24)
++#define IRQ_TCU2			(25)
++#define IRQ_TCU1			(26)
++#define IRQ_TCU0			(27)
++#define IRQ_MIPI_CSI_2			(28)
++#define IRQ_RESERVED0_29		(29)
++#define IRQ_CIM				(30)
++#define IRQ_LCD				(31)
++
++#define IRQ_RTC				(32 + 0)
++#define IRQ_SOFT			(32 + 1)
++#define IRQ_DTRNG			(32 + 2)
++#define IRQ_RESERVED1_3			(32 + 3)
++#define IRQ_MSC1			(32 + 4)
++#define IRQ_MSC0			(32 + 5)
++#define IRQ_RESERVED1_6			(32 + 6)
++#define IRQ_RESERVED1_7			(32 + 7)
++#define IRQ_CAN0			(32 + 8)
++#define IRQ_CAN1			(32 + 9)
++#define IRQ_CDBUS			(32 + 10)
++#define IRQ_RESERVED1_11		(32 + 11)
++#define IRQ_UART3			(32 + 12)
++#define IRQ_UART2			(32 + 13)
++#define IRQ_UART1			(32 + 14)
++#define IRQ_UART0			(32 + 15)
++#define IRQ_RESERVED1_16		(32 + 16)
++#define IRQ_HARB2			(32 + 17)
++#define IRQ_HARB0			(32 + 18)
++#define IRQ_CPM				(32 + 19)
++#define IRQ_DDR				(32 + 20)
++#define IRQ_RESERVED1_21		(32 + 21)
++#define IRQ_EFUSE			(32 + 22)
++#define IRQ_GMAC0			(32 + 23)
++#define IRQ_RESERVED1_24		(32 + 24)
++#define IRQ_RESERVED1_25		(32 + 25)
++#define IRQ_RESERVED1_26		(32 + 26)
++#define IRQ_RESERVED1_27		(32 + 27)
++#define IRQ_I2C1			(32 + 28)
++#define IRQ_I2C0			(32 + 29)
++#define IRQ_SSI_SLV			(32 + 30)
++#define IRQ_RESERVED1_31		(32 + 31)
++
++#endif
+diff --git a/include/dt-bindings/interrupt-controller/x2000-irq.h b/include/dt-bindings/interrupt-controller/x2000-irq.h
+new file mode 100644
+index 000000000..ad684f85c
+--- /dev/null
++++ b/include/dt-bindings/interrupt-controller/x2000-irq.h
+@@ -0,0 +1,72 @@
++#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_X2000_IRQ_H
++#define _DT_BINDINGS_INTERRUPT_CONTROLLER_X2000_IRQ_H
++
++#include <dt-bindings/interrupt-controller/mips-irq.h>
++
++#define IRQ_AUDIO			(0)
++#define IRQ_OTG				(1)
++#define IRQ_RESERVED0_2			(2)
++#define IRQ_PDMA			(3)
++#define IRQ_PDMAD			(4)
++#define IRQ_PDMAM			(5)
++#define IRQ_PWM				(6)
++#define IRQ_SFC				(7)
++#define IRQ_SSI1			(8)
++#define IRQ_SSI0			(9)
++#define IRQ_MIPI_DSI			(10)
++#define IRQ_SADC			(11)
++#define IRQ_MIPI_CSI_4			(12)
++#define IRQ_GPIO4			(13)
++#define IRQ_GPIO3			(14)
++#define IRQ_GPIO2			(15)
++#define IRQ_GPIO1			(16)
++#define IRQ_GPIO0			(17)
++#define IRQ_VIC1			(18)
++#define IRQ_VIC0			(19)
++#define IRQ_ISP1			(20)
++#define IRQ_ISP0			(21)
++#define IRQ_HASH			(22)
++#define IRQ_AES				(23)
++#define IRQ_RSA				(24)
++#define IRQ_TCU2			(25)
++#define IRQ_TCU1			(26)
++#define IRQ_TCU0			(27)
++#define IRQ_MIPI_CSI2			(28)
++#define IRQ_ROTATE			(29)
++#define IRQ_CIM				(30)
++#define IRQ_LCD				(31)
++
++#define IRQ_RTC				(32 + 0)
++#define IRQ_SOFT			(32 + 1)
++#define IRQ_DTRNG			(32 + 2)
++#define IRQ_SCC				(32 + 3)
++#define IRQ_MSC1			(32 + 4)
++#define IRQ_MSC0			(32 + 5)
++#define IRQ_UART9			(32 + 6)
++#define IRQ_UART8			(32 + 7)
++#define IRQ_UART7			(32 + 8)
++#define IRQ_UART6			(32 + 9)
++#define IRQ_UART5			(32 + 10)
++#define IRQ_UART4			(32 + 11)
++#define IRQ_UART3			(32 + 12)
++#define IRQ_UART2			(32 + 13)
++#define IRQ_UART1			(32 + 14)
++#define IRQ_UART0			(32 + 15)
++#define IRQ_MSC2			(32 + 16)
++#define IRQ_HARB2			(32 + 17)
++#define IRQ_HARB0			(32 + 18)
++#define IRQ_CPM				(32 + 19)
++#define IRQ_DDR				(32 + 20)
++#define IRQ_GMAC1			(32 + 21)
++#define IRQ_EFUSE			(32 + 22)
++#define IRQ_GMAC0			(32 + 23)
++#define IRQ_I2C5			(32 + 24)
++#define IRQ_I2C4			(32 + 25)
++#define IRQ_I2C3			(32 + 26)
++#define IRQ_I2C2			(32 + 27)
++#define IRQ_I2C1			(32 + 28)
++#define IRQ_I2C0			(32 + 29)
++#define IRQ_HELIX			(32 + 30)
++#define IRQ_FELIX			(32 + 31)
++
++#endif
+diff --git a/include/dt-bindings/interrupt-controller/x2500-irq.h b/include/dt-bindings/interrupt-controller/x2500-irq.h
+new file mode 100644
+index 000000000..fed7771d6
+--- /dev/null
++++ b/include/dt-bindings/interrupt-controller/x2500-irq.h
+@@ -0,0 +1,75 @@
++#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_X2500_IRQ_H
++#define _DT_BINDINGS_INTERRUPT_CONTROLLER_X2500_IRQ_H
++
++#include <dt-bindings/interrupt-controller/mips-irq.h>
++
++#define IRQ_RESERVED0			(0)
++#define IRQ_AIC0				(1)
++#define IRQ_SYS_LEP	    		(2)   /* RISC-V */
++#define IRQ_MIPI_DSI			(3)
++#define IRQ_MIPI_RX_4L			(4)
++#define IRQ_MIPI_RX_2L			(5)
++#define IRQ_IPU			    	(6)
++#define IRQ_SFC			    	(7)
++#define IRQ_SSI1		    	(8)
++#define IRQ_SSI0	    		(9)
++#define IRQ_PDMA	    		(10)
++#define IRQ_SSISLV	    		(11)
++#define IRQ_DMIC	    		(12)
++#define IRQ_RESERVED13			(13)
++#define IRQ_GPIO3	    		(14)
++#define IRQ_GPIO2		    	(15)
++#define IRQ_GPIO1		    	(16)
++#define IRQ_GPIO0		    	(17)
++#define IRQ_GPIO_PORT(N) (IRQ_GPIO0 - (N))
++#define IRQ_SADC	    		(18)
++#define IRQ_RESERVED19			(19)
++#define IRQ_LCD     			(20)
++#define IRQ_OTG	        		(21)
++#define IRQ_HASH	    		(22)
++#define IRQ_AES	    			(23)
++#define IRQ_RSA		    		(24)
++#define IRQ_TCU2		    	(25)
++#define IRQ_TCU1		    	(26)
++#define IRQ_TCU0		    	(27)
++#define IRQ_S2_VIC	    		(28)
++#define IRQ_S1_VIC     			(29)
++#define IRQ_S0_VIC	   			(30)
++#define IRQ_ISP		    		(31)
++
++#define IRQ_RESERVED32    		(32 + 0)
++#define IRQ_RESERVED33			(32 + 1)
++#define IRQ_DTRNG	    		(32 + 2)
++#define IRQ_RESERVED35			(32 + 3)
++#define IRQ_MSC1	    		(32 + 4)
++#define IRQ_MSC0		    	(32 + 5)
++#define IRQ_RESERVED38			(32 + 6)
++#define IRQ_BSCALER1			(32 + 7)
++#define IRQ_BSCALER0			(32 + 8)
++#define IRQ_DDR_DWU	    		(32 + 9)
++#define IRQ_DRAW_BOX			(32 + 10)
++#define IRQ_VO	        		(32 + 11)
++#define IRQ_HARB2	    		(32 + 12)
++#define IRQ_I2D     			(32 + 13)
++#define IRQ_RESERVED46			(32 + 14)
++#define IRQ_CPM	        		(32 + 15)
++#define IRQ_UART3	    		(32 + 16)
++#define IRQ_UART2	    		(32 + 17)
++#define IRQ_UART1		    	(32 + 18)
++#define IRQ_UART0		    	(32 + 19)
++#define IRQ_DDR	    			(32 + 20)
++#define IRQ_MON		        	(32 + 21)
++#define IRQ_EFUSE	    		(32 + 22)
++#define IRQ_GMAC0	    		(32 + 23)
++#define IRQ_RESERVED56	    	(32 + 24)
++#define IRQ_I2C3    			(32 + 25)
++#define IRQ_I2C2	    		(32 + 26)
++#define IRQ_I2C1	    		(32 + 27)
++#define IRQ_I2C0	    		(32 + 28)
++#define IRQ_PDMAM	    		(32 + 29)
++#define IRQ_EL150	    		(32 + 30)
++#define IRQ_RADIX    	    	(32 + 31)
++#define IRQ_PCM0			(32 + 32)
++
++
++#endif
+diff --git a/include/dt-bindings/net/ingenic_gmac.h b/include/dt-bindings/net/ingenic_gmac.h
+new file mode 100644
+index 000000000..32207f24e
+--- /dev/null
++++ b/include/dt-bindings/net/ingenic_gmac.h
+@@ -0,0 +1,9 @@
++#ifndef __INGENIC_GMAC_H__
++#define __INGENIC_GMAC_H__
++
++#define GMII	0
++#define RGMII	1
++#define MII	2
++#define RMII	4
++
++#endif
+diff --git a/include/dt-bindings/pinctrl/ingenic-pinctrl.h b/include/dt-bindings/pinctrl/ingenic-pinctrl.h
+new file mode 100644
+index 000000000..d574e2326
+--- /dev/null
++++ b/include/dt-bindings/pinctrl/ingenic-pinctrl.h
+@@ -0,0 +1,79 @@
++#ifndef _DT_INGENIC_PINCTL_H__
++#define _DT_INGENIC_PINCTL_H__
++#include <dt-bindings/gpio/gpio.h>
++
++#define PINCTL_FUNCTION0	0
++#define PINCTL_FUNCTION1	1
++#define PINCTL_FUNCTION2	2
++#define PINCTL_FUNCTION3	3
++#define PINCTL_FUNCHILVL	4
++#define PINCTL_FUNCLOLVL	5
++#define PINCTL_FUNCINPUT	6
++#define PINCTL_FUNCINPUT_LO	7
++#define PINCTL_FUNCINPUT_HI	8
++#define PINCTL_FUNCINPUT_FE	9
++#define PINCTL_FUNCINPUT_RE	10
++#define PINCTL_FUNCINPUT_RE_FE	11
++#define PINCTL_FUNCTIONS	12
++
++
++#define PINCTL_CFG_TYPES	1
++
++/* Used in device tree for gpio function settings. ingenic,pincfg*/
++#define PINCTL_CFG_BIAS_DISABLE			1
++#define PINCTL_CFG_BIAS_HIGH_IMPEDANCE		2
++#define PINCTL_CFG_BIAS_PULL_DOWN		3
++#define PINCTL_CFG_BIAS_PULL_PIN_DEFAULT	4
++#define PINCTL_CFG_BIAS_PULL_UP			5
++#define PINCTL_CFG_DRIVE_STRENGTH		9
++#define PINCTL_CFG_FILTER			10
++#define PINCTL_CFG_INPUT_SCHMITT_ENABLE		11
++#define PINCTL_CFG_SLEW_RATE			17
++
++#define PINCTL_CFG_TYPE_MSK	0xFFFF
++#define PINCTL_CFGVAL_SFT	16
++#define PINCTL_CFGVAL_MSK	(0xFFFF << PINCTL_CFGVAL_SFT)
++
++#define PINCFG_PACK(type, value)	(((value) << PINCTL_CFGVAL_SFT) | type)
++#define PINCFG_UNPACK_TYPE(cfg)		((cfg) & PINCTL_CFG_TYPE_MSK)
++#define PINCFG_UNPACK_VALUE(cfg)	(((cfg) & PINCTL_CFGVAL_MSK) >> \
++						PINCTL_CFGVAL_SFT)
++
++#define PINCTL_NOBIAS		((0 << PINCTL_CFGVAL_SFT) | PINCTL_CFG_PULL)
++#define PINCTL_PULLEN		((1 << PINCTL_CFGVAL_SFT) | PINCTL_CFG_PULL)
++
++
++/* Used in device tree for gpio settings. eg, <&gpb 0, GPIO_ACTIVE_LOW INGENIC_GPIO_PULL_UP | INGENIC_GPIO_DS_0> */
++#define INGENIC_GPIO_BIAS_MASK		0x7
++#define INGENIC_GPIO_BIAS_SFT		0
++#define INGENIC_GPIO_NOBIAS		(0 << INGENIC_GPIO_BIAS_SFT)
++#define INGENIC_GPIO_PULLEN		(1 << INGENIC_GPIO_BIAS_SFT)
++#define INGENIC_GPIO_PULLUP		(2 << INGENIC_GPIO_BIAS_SFT)
++#define INGENIC_GPIO_PULLDOWN		(3 << INGENIC_GPIO_BIAS_SFT)
++#define INGENIC_GPIO_HIZ		(4 << INGENIC_GPIO_BIAS_SFT)
++
++#define INGENIC_GPIO_DS_SFT		3
++#define INGENIC_GPIO_DS_MSK		0x7
++#define INGENIC_GPIO_DS_0		(0 << INGENIC_GPIO_DS_SFT)
++#define INGENIC_GPIO_DS_1		(1 << INGENIC_GPIO_DS_SFT)
++#define INGENIC_GPIO_DS_2		(2 << INGENIC_GPIO_DS_SFT)
++#define INGENIC_GPIO_DS_3		(3 << INGENIC_GPIO_DS_SFT)
++#define INGENIC_GPIO_DS_4		(4 << INGENIC_GPIO_DS_SFT)
++#define INGENIC_GPIO_DS_5		(5 << INGENIC_GPIO_DS_SFT)
++#define INGENIC_GPIO_DS_6		(6 << INGENIC_GPIO_DS_SFT)
++#define INGENIC_GPIO_DS_7		(7 << INGENIC_GPIO_DS_SFT)
++
++#define INGENIC_GPIO_SLEW_RATE_SFT	6
++#define INGENIC_GPIO_SLEW_RATE		(1 << INGENIC_GPIO_SLEW_RATE_SFT)
++
++#define INGENIC_GPIO_SCHMITT_SFT	7
++#define INGENIC_GPIO_SCHMITT		(1 << INGENIC_GPIO_SCHMITT_SFT)
++
++/* Use in pinctrl drivers.*/
++#define INGENIC_GPIO_PULL(x)		(((x) >> INGENIC_GPIO_BIAS_SFT) & INGENIC_GPIO_BIAS_MASK)
++#define INGENIC_GPIO_DRIVE_STRENGTH(x)  (((x) >> INGENIC_GPIO_DS_SFT) & INGENIC_GPIO_DS_MSK)
++#define INGENIC_GPIO_SCHMITT_ENABLE(x)	((x) >> INGENIC_GPIO_SCHMITT_SFT)
++#define INGENIC_GPIO_SLEW_RATE_ENABLE(x) ((x) >> INGENIC_GPIO_SLEW_RATE_SFT)
++
++
++#endif /*_DT_INGENIC_PINCTL_H__*/
+diff --git a/include/dt-bindings/power/axp216-power.h b/include/dt-bindings/power/axp216-power.h
+new file mode 100644
+index 000000000..fd28e910b
+--- /dev/null
++++ b/include/dt-bindings/power/axp216-power.h
+@@ -0,0 +1,21 @@
++#ifndef _DT_BINDINGS_POWER_AXP216_POWER_H
++#define _DT_BINDINGS_POWER_AXP216_POWER_H
++
++#define AXP216_POWER_DOMAIN_ID_RTC 0
++#define AXP216_POWER_DOMAIN_ID_ALDO1 1
++#define AXP216_POWER_DOMAIN_ID_ALDO2 2
++#define AXP216_POWER_DOMAIN_ID_ALDO3 3
++#define AXP216_POWER_DOMAIN_ID_ELDO1 4
++#define AXP216_POWER_DOMAIN_ID_ELDO2 5
++#define AXP216_POWER_DOMAIN_ID_DCDC1 6
++#define AXP216_POWER_DOMAIN_ID_DCDC2 7
++#define AXP216_POWER_DOMAIN_ID_DCDC3 8
++#define AXP216_POWER_DOMAIN_ID_DCDC4 9
++#define AXP216_POWER_DOMAIN_ID_DCDC5 10
++#define AXP216_POWER_DOMAIN_ID_LDOIO1 11
++#define AXP216_POWER_DOMAIN_ID_SUPPLY 12
++#define AXP216_POWER_DOMAIN_ID_GPIO 13
++
++#define POWER_SUPPLY_TECHNOLOGY_LION 2
++
++#endif /* _DT_BINDINGS_POWER_AXP216_POWER_H */
+diff --git a/include/dt-bindings/sound/ingenic-baic.h b/include/dt-bindings/sound/ingenic-baic.h
+new file mode 100644
+index 000000000..b33d9bffd
+--- /dev/null
++++ b/include/dt-bindings/sound/ingenic-baic.h
+@@ -0,0 +1,34 @@
++#ifndef __INGENIC_BAIC_H__
++#define __INGENIC_BAIC_H__
++
++#undef BIT
++#define BIT(n)			(1 << (n))
++#define BAIC_DAIFMT_NO_GRP	(0x0 << 0)
++#define BAIC_DAIFMT_I2S_GRP	(0x1 << 0)
++#define BAIC_DAIFMT_DSP_GRP	(0x2 << 0)
++#define BAIC_DAIFMT_GRP_MSK	(0x3 << 0)
++#define BAIC_DAIFMT_MODEA	(BIT(0) << 2)	/*dsp grp*/
++#define BAIC_DAIFMT_MODEB	(BIT(1) << 2)
++#define BAIC_DAIFMT_PCM		(BIT(0) << 4)
++#define BAIC_DAIFMT_DSP		(BIT(1) << 4)
++#define BAIC_DAIFMT_TDM2	(BIT(2) << 4)
++#define BAIC_DAIFMT_TDM1	(BIT(3) << 4)
++#define BAIC_DAIFMT_I2S		(BIT(4) << 4)	/*i2s grp*/
++#define BAIC_DAIFMT_RIGHTJ	(BIT(5) << 4)
++#define BAIC_DAIFMT_LEFTJ	(BIT(6) << 4)
++
++#define BAIC_NO_REPLAY		(BIT(7) << 4)	/*just support replay or record*/
++#define BAIC_NO_RECORD		(BIT(8) << 4)
++
++#define BAIC_PCM_MODE	(BAIC_DAIFMT_PCM|BAIC_DAIFMT_DSP_GRP|BAIC_DAIFMT_MODEA|BAIC_DAIFMT_MODEB)
++#define BAIC_DSP_MODE	(BAIC_DAIFMT_DSP|BAIC_DAIFMT_DSP_GRP|BAIC_DAIFMT_MODEA|BAIC_DAIFMT_MODEB)
++#define BAIC_TDM1_MODE	(BAIC_DAIFMT_TDM1|BAIC_DAIFMT_DSP_GRP|BAIC_DAIFMT_MODEA|BAIC_DAIFMT_MODEB)
++#define BAIC_TDM2_MODE	(BAIC_DAIFMT_TDM2|BAIC_DAIFMT_DSP_GRP|BAIC_DAIFMT_MODEA|BAIC_DAIFMT_MODEB)
++#define BAIC_I2S_MODE	(BAIC_DAIFMT_I2S|BAIC_DAIFMT_RIGHTJ|BAIC_DAIFMT_LEFTJ|BAIC_DAIFMT_I2S_GRP)
++
++#define BAIC_2AND(x,y)		((x) | (y))
++#define BAIC_3AND(x,y,z)	((x) | (y) | (z))
++#define BAIC_4AND(x,y,z,m)	((x) | (y) | (z) | (m))
++#define BAIC_5AND(x,y,z,m,n)	((x) | (y) | (z) | (m) | (n))
++
++#endif /*__INGENIC_BAIC_H__*/
+diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h
+index a5f89fc4d..9d48ccfb9 100644
+--- a/include/linux/dma-map-ops.h
++++ b/include/linux/dma-map-ops.h
+@@ -167,13 +167,13 @@ int dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
+ 		dma_addr_t device_addr, size_t size);
+ int dma_alloc_from_dev_coherent(struct device *dev, ssize_t size,
+ 		dma_addr_t *dma_handle, void **ret);
+-int dma_release_from_dev_coherent(struct device *dev, int order, void *vaddr);
++int dma_release_from_dev_coherent(struct device *dev, ssize_t size, void *vaddr);
+ int dma_mmap_from_dev_coherent(struct device *dev, struct vm_area_struct *vma,
+ 		void *cpu_addr, size_t size, int *ret);
+ 
+ void *dma_alloc_from_global_coherent(struct device *dev, ssize_t size,
+ 		dma_addr_t *dma_handle);
+-int dma_release_from_global_coherent(int order, void *vaddr);
++int dma_release_from_global_coherent(ssize_t size, void *vaddr);
+ int dma_mmap_from_global_coherent(struct vm_area_struct *vma, void *cpu_addr,
+ 		size_t size, int *ret);
+ 
+@@ -184,7 +184,7 @@ static inline int dma_declare_coherent_memory(struct device *dev,
+ 	return -ENOSYS;
+ }
+ #define dma_alloc_from_dev_coherent(dev, size, handle, ret) (0)
+-#define dma_release_from_dev_coherent(dev, order, vaddr) (0)
++#define dma_release_from_dev_coherent(dev, size, vaddr) (0)
+ #define dma_mmap_from_dev_coherent(dev, vma, vaddr, order, ret) (0)
+ 
+ static inline void *dma_alloc_from_global_coherent(struct device *dev,
+@@ -192,7 +192,7 @@ static inline void *dma_alloc_from_global_coherent(struct device *dev,
+ {
+ 	return NULL;
+ }
+-static inline int dma_release_from_global_coherent(int order, void *vaddr)
++static inline int dma_release_from_global_coherent(ssize_t size, void *vaddr)
+ {
+ 	return 0;
+ }
+diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
+index dd357a747..8d0993f7d 100644
+--- a/include/linux/dmaengine.h
++++ b/include/linux/dmaengine.h
+@@ -876,6 +876,14 @@ struct dma_device {
+ 	int (*device_alloc_chan_resources)(struct dma_chan *chan);
+ 	void (*device_free_chan_resources)(struct dma_chan *chan);
+ 
++	/* Legacy Interface For ingenic chips. New DMA Driver should never use.*/
++	struct dma_async_tx_descriptor *(*device_add_desc)(
++			struct dma_chan *chan, dma_addr_t src,dma_addr_t dst,
++			unsigned cnt,enum dma_transfer_direction direction,int flag);
++	dma_addr_t (*get_current_trans_addr)(
++			struct dma_chan *chan,dma_addr_t *dst_addr,
++			dma_addr_t *src_addr,enum dma_transfer_direction direction);
++
+ 	struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
+ 		struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
+ 		size_t len, unsigned long flags);
+diff --git a/include/linux/mfd/ingenic-tcu_v1.h b/include/linux/mfd/ingenic-tcu_v1.h
+new file mode 100644
+index 000000000..bd8ff03e2
+--- /dev/null
++++ b/include/linux/mfd/ingenic-tcu_v1.h
+@@ -0,0 +1,202 @@
++#ifndef __INGENIC_TCU_H__
++#define __INGENIC_TCU_H__
++
++#include <dt-bindings/clock/ingenic-tcu.h>
++
++#define NR_TCU_CHNS TCU_NR_IRQS
++
++enum irq_bit {
++	FULL_BIT,
++	HALF_BIT,
++};
++enum tcu_prescale {
++	TCU_PRESCALE_1,
++	TCU_PRESCALE_4,
++	TCU_PRESCALE_16,
++	TCU_PRESCALE_64,
++	TCU_PRESCALE_256,
++	TCU_PRESCALE_1024
++};
++
++enum tcu_clksrc {
++	TCU_CLKSRC_PCK = 1,
++	TCU_CLKSRC_RTC = 2,
++	TCU_CLKSRC_EXT = 4
++};
++
++enum tcu_irq_type {
++	NULL_IRQ_MODE,
++	FULL_IRQ_MODE,
++	HALF_IRQ_MODE,
++	FULL_HALF_IRQ_MODE,
++};
++
++struct info_bits {
++	unsigned int id:CHANNEL_BASE_OFF*2;
++	unsigned int mode:CHANNEL_BASE_OFF;
++	unsigned int func:CHANNEL_BASE_OFF;
++	unsigned int pwmin:CHANNEL_BASE_OFF;
++};
++
++struct ingenic_tcu_chn {
++	union {
++		unsigned int chn_info;
++		struct info_bits cib;
++	};
++    unsigned int index;
++	char virq[2];
++	char irq_type;
++	char clk_src;
++
++	char clk_div;
++	char init_level;
++	char shutdown_mode;
++	char pwm_bapass_mode;
++
++	char is_pwm;
++	char is_count_clear;
++	char pwm_in_en;
++	char work_sleep;
++
++	int half_num;
++	int full_num;
++	struct device_node *np;
++	void (*enable)(int id);
++	void (*disable)(int id);
++};
++
++void tcu_start_counter(int id);
++void tcu_stop_counter(int id);
++void tcu_set_counter(int id, unsigned int val);
++int tcu_get_counter(int id);
++void tcu_enable_counter(int id);
++void tcu_disable_counter(int id);
++
++/**
++ * ingenic_tcu_set_full_num - set the number of tcu Timer Data FULL Register (TDFR)
++ *
++ * @id:		tcu channel id.
++ * @full_num:	the number of set TDFR.
++ *
++ */
++void ingenic_tcu_set_period(int id, uint16_t period);
++/**
++ * ingenic_tcu_set_half_num - set the number of tcu Timer Data FULL Register (TDHR)
++ *
++ * @id:		tcu channel id.
++ * @half_num:	the number of set TDFR.
++ *
++ */
++void ingenic_tcu_set_duty(int id, uint16_t duty);
++/**
++ * ingenic_tcu_set_prescale - set clk div of TCU prescale.
++ * Don‘t call the function  when the channel is running.
++ *
++ * @id:		tcu channel id.
++ * @prescale:	the div of clk value.
++ *
++ */
++void ingenic_tcu_set_prescale(int id, enum tcu_prescale prescale);
++/**
++ * ingenic_tcu_set_pwm_output_init_level - set an initial output level for PWM output.
++ *
++ * @id:		tcu channel id.
++ * @level:	0 LOW, 1 HIGH.
++ *
++ */
++void ingenic_tcu_set_pwm_output_init_level(int id, int level);
++/**
++ * ingenic_tcu_set_clksrc - set clk soruce of the timer clock input.
++ * Don‘t call the function  when the channel is running.
++ *
++ * @id:		tcu channel id.
++ * @src:	the clk source;0 PCLK, 1 RTC, 2 EXT.
++ *
++ */
++void ingenic_tcu_set_clksrc(int id, enum tcu_clksrc src);
++/**
++ * ingenic_tcu_channel_to_virq - get virtual irq though to tcu channel id
++ * (channel 0 ~ 4, 6 ~ 7 use common hardware irq(TCU2))
++ *
++ * @tcu_chn: the struct of request cell(TCU channel).
++ *
++ * Search for a virq in a irq domain and save irq to struct ingenic_tcu_chn
++ * ->virq[2].
++ */
++void ingenic_tcu_channel_to_virq(struct ingenic_tcu_chn *tcu_chn);
++/**
++ * ingenic_tcu_get_count - get the value of the timer counter (TCNT).
++ *
++ * @id:		tcu channel id.
++ *
++ * Returns number of timer counter on sucess,
++ * -EINVAL if The value read from counter 1 or 2 is a false value.
++ *
++ */
++int ingenic_tcu_get_count(int id);
++/**
++ * ingenic_tcu_config - init the current channel struct.
++ *
++ * @tcu_chn:		tcu channel struct.
++ *
++ * Returns 0 on sucess,
++ * Returns < 0 if init failed.
++ *
++ */
++int ingenic_tcu_config(struct ingenic_tcu_chn *tcu_chn);
++/**
++ * ingenic_tcu_counter_begin - begin counting up, if channel function is pwm, enable pwm.
++ *
++ * @tcu_chn:		tcu channel struct.
++ *
++ */
++int ingenic_tcu_counter_begin(struct ingenic_tcu_chn *tcu_chn);
++/**
++ * ingenic_tcu_counter_stop - stop counting up, if channel function is pwm, disable pwm.
++ *
++ * @tcu_chn:		tcu channel struct.
++ *
++ * Explain：
++ * TCU count stop, is the next stop after match, not immediately stop.
++ * If you want to stop immediately, you can use cell->disable.
++ *
++ */
++void ingenic_tcu_counter_stop(struct ingenic_tcu_chn *tcu_chn);
++
++/**
++ * ingenic_watchdog_set_count - setwatchdog timer counter.
++ * This function is only used for watchdog.
++ *
++ * @value:		the number of set watchdog counter.
++ *
++ */
++void ingenic_watchdog_set_count(unsigned int value);
++/**
++ * ingenic_watchdog_config - init watchdog.
++ * This function is only used for watchdog.
++ *
++ * @tcsr_val:		the number of set watchdog TCSR.
++ * @timeout_value:		the number of set watchdog TCNT.
++ *
++ */
++void ingenic_watchdog_config(unsigned int tcsr_val, unsigned int timeout_value);
++
++/**
++ * request_cell - request tcu channel cell.
++ *
++ * @id:		tcu channel id.
++ *
++ * Returns struct cell on sucess,
++ * NULL if The channel busy.
++ *
++ */
++struct mfd_cell *request_cell(int id);
++/**
++ * free_cell - free tcu channel cell.
++ *
++ * @id:		tcu channel id.
++ *
++ */
++void free_cell(int id);
++
++#endif /* __INGENIC_TCU_H__ */
+diff --git a/include/linux/mfd/ingenic-tcu_v2.h b/include/linux/mfd/ingenic-tcu_v2.h
+new file mode 100644
+index 000000000..a342b0d99
+--- /dev/null
++++ b/include/linux/mfd/ingenic-tcu_v2.h
+@@ -0,0 +1,383 @@
++#ifndef __INGENIC_TCU_H__
++#define __INGENIC_TCU_H__
++
++#define CHN_TDFR	(0x0)    /*channel N data full register*/
++#define CHN_TDHR	(0x4)    /*channel N data half register*/
++#define CHN_TCNT	(0x8)    /*channel N counter register*/
++#define CHN_TCSR	(0xc)    /*channel N control register*/
++
++#define TCU_TSR		(0x1C)   /* Timer Stop Register */
++#define TCU_TSSR	(0x2C)   /* Timer Stop Set Register */
++#define TCU_TSCR	(0x3C)   /* Timer Stop Clear Register */
++#define TCU_TER		(0x10)   /* Timer Counter Enable Register */
++#define TCU_TESR	(0x14)   /* Timer Counter Enable Set Register */
++#define TCU_TECR	(0x18)   /* Timer Counter Enable Clear Register */
++#define TCU_TFR		(0x20)   /* Timer Flag Register */
++#define TCU_TFSR	(0x24)   /* Timer Flag Set Register */
++#define TCU_TFCR	(0x28)   /* Timer Flag Clear Register */
++#define TCU_TMR		(0x30)   /* Timer Mask Register */
++#define TCU_TMSR	(0x34)   /* Timer Mask Set Register */
++#define TCU_TMCR	(0x38)   /* Timer Mask Clear Register */
++#define TCU_STORE_FLAG          (0x200)
++#define TCU_STORE_FLAG_SET      (0x204)
++#define TCU_STORE_FLAG_CLR      (0x208)
++#define TCU_STORE_MASK_RD       (0x210)
++#define TCU_STORE_MASK_SET      (0x214)
++#define TCU_STORE_MASK_CLR      (0x218)
++
++#define CH_TDFR(n)	(0x40 + (n)*0x10) /* Timer Data Full Reg */
++#define CH_TDHR(n)	(0x44 + (n)*0x10) /* Timer Data Half Reg */
++#define CH_TCNT(n)	(0x48 + (n)*0x10) /* Timer Counter Reg */
++#define CH_TCSR(n)	(0x4C + (n)*0x10) /* Timer Control Reg */
++
++#define CHN_CAP(n)	(0xc0 + (n)*0x04) /*Capture register*/
++#define CHN_CAP_VAL(n)	(0xe0 + (n)*0x04) /*Capture Value register*/
++#define CHN_FIL_VAL(n)	(0x1a0 + (n)*0x04) /*filter value*/
++
++#define TCU_STORE_VAL(n)	(0x220 + (n)*0x04)
++#define TCU_STORE_FIL_VAL(n)	(0x240 + (n)*0x04)
++
++//OST control
++#define TER_OSTEN	(1 << 15)   /* enable the counter in ost */
++#define TMR_OSTM	(1 << 15)   /* ost comparison match interrupt mask */
++#define TFR_OSTF	(1 << 15)   /* ost interrupt flag */
++#define	TSR_OSTS	(1 << 15)   /*the clock supplies to osts is stopped */
++
++//watchdog bit
++#define TSR_WDTS	(1 << 16)   /*the clock supplies to wdt is stopped */
++#define TCU_FLAG_RD	(1 << 24)   /*HALF comparison match flag of WDT. (TCNT = TDHR) */
++
++//timer control Register bit operation
++#define CSR_EXT_EN	(1 << 2)  /* select extal as the timer clock input */
++#define CSR_DIV1	(0x0 << 3) /*select the TCNT count clock frequency*/
++#define CSR_DIV4	(0x1 << 3)
++#define CSR_DIV16	(0x2 << 3)
++#define CSR_DIV64	(0x3 << 3)
++#define CSR_DIV256	(0x4 << 3)
++#define CSR_DIV1024	(0x5 << 3)
++#define CSR_DIV_MSK	(0x7 << 3)
++
++#define CSR_DIR_HIGH	(0x0 << 8)  /*0:direction signal hold on 1*/
++#define CSR_DIR_CLK	(0x1 << 8)  /*1:use clock with direction signal*/
++#define CSR_DIR_GPIO0	(0x2 << 8)  /*2:use gpio0 with direction signal*/
++#define CSR_DIR_GPIO1	(0x3 << 8)  /*3:use gpio1 with direction signal*/
++#define CSR_DIR_QUADRATURE	(0x4 << 8)  /*4:use gpio0 and gpio1 quadrature result with direction signal*/
++#define CSR_DIR_MSK	(0x7 << 8)
++
++#define CSR_GATE_LOW	(0x0 << 11)  /*0:gate signal hold on 0*/
++#define CSR_GATE_CLK	(0x1 << 11)  /*1:use clock with gate signal*/
++#define CSR_GATE_GPIO0	(0x2 << 11)  /*2:use gpio0 with gate signal*/
++#define CSR_GATE_GPIO1	(0x3 << 11)  /*3:use gpio1 with gate signal*/
++#define CSR_GATE_MSK	(0x3 << 11)
++
++#define CLK_POS		(16)
++#define CLK_NEG		(17)
++#define GPIO0_POS	(18)
++#define GPIO0_NEG	(19)
++#define GPIO1_POS	(20)
++#define GPIO1_NEG	(21)
++#define STORE_EN	(24)
++#define STORE_POS_EN	(25)
++#define STORE_NEG_EN	(26)
++
++
++#define CSR_CM_FCZ	(0x0 << 22)  /*count range 0 <-> full with clear to 0*/
++#define CSR_CM_MCZ	(0x1 << 22)  /*count range 0 <-> 0xffff with clear to 0*/
++#define CSR_CM_MH	(0x2 << 22)  /*count range 0 <-> 0xffff with hold on*/
++#define CSR_CM_MSK	(0x3 << 22)
++
++#define TCU_CONTROL_BIT(n)	(1 << n)
++
++//Capture register bit operation
++#define CAP_SEL_CLK	(0x0 << 16)  /*TCU will capture clock*/
++#define CAP_SEL_GPIO0	(0x1 << 16)  /*TCU will capture gpio0*/
++#define CAP_SEL_GPIO1	(0x2 << 16)  /*TCU will capture gpio1*/
++/*if capture mode is disable then these bits will:*/
++#define CAP_SEL_CCG0P	(0x1 << 16)  /*counter will clear when gpio0 posedge*/
++#define CAP_SEL_CCG1P	(0x2 << 16)  /*counter will clear when gpio1 posedge*/
++#define CAP_SEL_MSK	(0x7 << 16)
++#define CAP_NUM_MSK	(0xff)
++
++//filter value register bit operation
++#define  FIL_VAL_GPIO1_MSK	(0x3ff << 16)  /*Gpio1 filter counter value*/
++#define  FIL_VAL_GPIO0_MSK	(0x3ff)	       /*Gpio0 filter counter value*/
++
++//Common 1 bit offset
++#define ONE_BIT_OFFSET(n)	TCU_CONTROL_BIT(n)
++
++
++#define timeout	 (500)
++#define CAPTURE_LOOP_FLAGS (0x1 << 7)
++
++#define TCU_CHN_TDFR	(0x0)
++#define TCU_CHN_TDHR	(0x4)
++#define TCU_CHN_TCNT	(0x8)
++#define TCU_CHN_TCSR	(0xc)
++#define TCU_FULL0	(0x40)
++#define TCU_CHN_OFFSET	(0x10)
++
++
++#define tcu_readl(tcu,reg)			\
++	__raw_readl((tcu)->iomem + reg)
++#define tcu_writel(tcu,reg,value)			\
++	__raw_writel((value), (tcu)->iomem + reg)
++
++#define tcu_chn_readl(tcu_chn,reg)					\
++	__raw_readl((tcu_chn)->tcu->iomem + (tcu_chn)->reg_base + reg)
++#define tcu_chn_writel(tcu_chn,reg,value)				\
++	__raw_writel((value), (tcu_chn)->tcu->iomem + (tcu_chn)->reg_base + reg)
++
++enum tcu_prescale {
++	TCU_PRESCALE_1,
++	TCU_PRESCALE_4,
++	TCU_PRESCALE_16,
++	TCU_PRESCALE_64,
++	TCU_PRESCALE_256,
++	TCU_PRESCALE_1024
++};
++
++enum tcu_irq_type {
++	NULL_IRQ_MODE,
++	FULL_IRQ_MODE,
++	HALF_IRQ_MODE,
++	FULL_HALF_IRQ_MODE,
++};
++
++enum tcu_clksrc {
++	TCU_CLKSRC_NULL,
++	TCU_CLKSRC_EXT = ONE_BIT_OFFSET(2),
++	TCU_CLKSRC_GPIO0 = ONE_BIT_OFFSET(6),
++	TCU_CLKSRC_GPIO1 = ONE_BIT_OFFSET(7)
++};
++
++enum tcu_count_mode{
++	COUNT_MODE_FCZ,
++	COUNT_MODE_MCZ,
++	COUNT_MODE_MH
++};
++
++enum tcu_gate_sel{
++	GATE_SEL_HZ,
++	GATE_SEL_CLK,
++	GATE_SEL_GPIO0,
++	GATE_SEL_GPIO1
++};
++
++enum tcu_gate_pola{
++	GATE_POLA_LOW,
++	GATE_POLA_HIGH
++};
++
++enum tcu_dir_sel{
++	DIR_SEL_HH,
++	DIR_SEL_CLK,
++	DIR_SEL_GPIO0,
++	DIR_SEL_GPIO1,
++	DIR_SEL_GPIO_QUA
++};
++
++enum tcu_dir_pola{
++	DIR_POLA_LOW,
++	DIR_POLA_HIGH
++};
++
++enum tcu_mode_sel{
++	GENERAL_MODE,
++	GATE_MODE,
++	DIRECTION_MODE,
++	QUADRATURE_MODE,
++	POS_MODE,
++	CAPTURE_MODE,
++	FILTER_MODE
++};
++
++enum tcu_pos_sel{
++	GPIO0_POS_CLR = 1,
++	GPIO1_POS_CLR,
++	GPIO0_NEG_CLR
++};
++
++enum tcu_capture_sel{
++	CAPTURE_CLK,
++	CAPTURE_GPIO0,
++	CAPTURE_GPIO1
++};
++
++enum signal_pos_neg{
++	SIG_INIT,
++	SIG_NEG_EN,
++	SIG_POS_EN,
++	SIG_POS_NEG_EN
++};
++
++struct ingenic_tcu {
++	void __iomem *iomem;
++	struct resource *res;
++	struct clk *clk;
++	int irq;
++	int irq_trigger;
++	int irq_base;
++	spinlock_t lock;
++};
++
++
++struct ingenic_tcu_chn {
++	int index;			/* Channel number */
++	int id;				/* Channel number */
++	int en_flag;
++	u32 reg_base;
++	void __iomem *iomem;
++	int using;
++
++	enum tcu_irq_type irq_type;
++	enum tcu_clksrc clk_ext,clk_gpio0,clk_gpio1;
++	enum tcu_prescale prescale;
++	enum tcu_count_mode count_mode;
++	enum tcu_gate_sel gate_sel;
++	enum tcu_gate_pola gate_pola;
++	enum tcu_dir_sel dir_sel;
++	enum tcu_dir_pola dir_pola;
++	enum tcu_mode_sel mode_sel;
++	enum signal_pos_neg sig_ext,sig_gpio0,sig_gpio1;
++	enum tcu_pos_sel pos_sel;
++	enum tcu_capture_sel capture_sel;
++
++	int capture_num;
++	int half_num;
++	int full_num;
++	int fil_a_num;
++	int fil_b_num;
++	int count_value;
++	unsigned int divi_ratio;  /*  0/1/2/3/4/5/something else------>1/4/16/64/256/1024/mask  */
++	int shutdown_mode;
++	struct ingenic_tcu *tcu;
++	bool gpio_trigger;
++};
++static inline void ingenic_tcu_enable_counter(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_writel(tcu_chn->tcu, TCU_TESR, 1 << tcu_chn->index);
++}
++
++static inline int ingenic_tcu_disable_counter(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_writel(tcu_chn->tcu, TCU_TECR, 1 << tcu_chn->index);
++	return 1;
++}
++
++static inline void ingenic_tcu_start_counter(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_writel(tcu_chn->tcu, TCU_TSCR, 1 << tcu_chn->index);
++}
++
++static inline void ingenic_tcu_stop_counter(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_writel(tcu_chn->tcu, TCU_TSSR, 1 << tcu_chn->index);
++}
++
++static inline void ingenic_tcu_set_count(struct ingenic_tcu_chn *tcu_chn, u16 cnt)
++{
++	tcu_chn_writel(tcu_chn, CHN_TCNT, cnt);
++}
++
++static inline unsigned long ingenic_tcu_flag_st(struct ingenic_tcu_chn *tcu_chn)
++{
++	return tcu_readl(tcu_chn->tcu, TCU_TFR);
++}
++
++static inline int ingenic_tcu_get_count(struct ingenic_tcu_chn *tcu_chn)
++{
++	return tcu_chn_readl(tcu_chn, CHN_TCNT);
++}
++
++static inline int ingenic_tcu_get_cap_val(struct ingenic_tcu_chn *tcu_chn)
++{
++	return tcu_readl(tcu_chn->tcu,CHN_CAP_VAL(tcu_chn->index));
++}
++
++static inline unsigned int ingenic_tcu_store_flag_st(struct ingenic_tcu *tcu)
++{
++	return tcu_readl(tcu, TCU_STORE_FLAG);
++}
++
++static inline void ingenic_tcu_store_flag_clr(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_writel(tcu_chn->tcu, TCU_STORE_FLAG_CLR, 1 << tcu_chn->index);
++}
++
++static inline void ingenic_tcu_store_flag_set(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_writel(tcu_chn->tcu, TCU_STORE_FLAG_SET, 1 << tcu_chn->index);
++}
++
++static inline unsigned int ingenic_tcu_store_mask_val(struct ingenic_tcu *tcu)
++{
++	return tcu_readl(tcu, TCU_STORE_MASK_RD);
++}
++
++static inline void ingenic_tcu_store_mask_clr(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_writel(tcu_chn->tcu, TCU_STORE_MASK_CLR, 1 << tcu_chn->index);
++}
++
++static inline void ingenic_tcu_store_mask_set(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_writel(tcu_chn->tcu, TCU_STORE_MASK_SET, 1 << tcu_chn->index);
++}
++
++static inline unsigned int ingenic_tcu_store_val(struct ingenic_tcu_chn *tcu_chn)
++{
++	return tcu_readl(tcu_chn->tcu, TCU_STORE_VAL(tcu_chn->index));
++}
++
++static inline void ingenic_tcu_store_set_filter(struct ingenic_tcu_chn *tcu_chn,
++		unsigned int val)
++{
++	tcu_writel(tcu_chn->tcu, TCU_STORE_FIL_VAL(tcu_chn->index), val & 0x3ff);
++}
++
++static inline void ingenic_tcu_store_enable(struct ingenic_tcu_chn *tcu_chn)
++{
++	unsigned int tmp;
++	tmp = tcu_chn_readl(tcu_chn, CHN_TCSR);
++	tcu_chn_writel(tcu_chn, CHN_TCSR, (1 << STORE_EN) | tmp);
++}
++
++static inline void ingenic_tcu_store_disable(struct ingenic_tcu_chn *tcu_chn)
++{
++	unsigned int tmp;
++	tmp = tcu_chn_readl(tcu_chn, CHN_TCSR);
++	tcu_chn_writel(tcu_chn, CHN_TCSR, ~(1 << STORE_EN) & tmp);
++}
++
++static inline void ingenic_tcu_store_neg_enable(struct ingenic_tcu_chn *tcu_chn)
++{
++	unsigned int tmp;
++	tmp = tcu_readl(tcu_chn->tcu, CH_TCSR(tcu_chn->index));
++	tcu_writel(tcu_chn->tcu, CH_TCSR(tcu_chn->index), (1 << STORE_NEG_EN) | tmp);
++}
++
++static inline void ingenic_tcu_store_neg_disable(struct ingenic_tcu_chn *tcu_chn)
++{
++	unsigned int tmp;
++	tmp = tcu_readl(tcu_chn->tcu, CH_TCSR(tcu_chn->index));
++	tcu_writel(tcu_chn->tcu, CH_TCSR(tcu_chn->index), ~(1 << STORE_NEG_EN) | tmp);
++}
++
++static inline void ingenic_tcu_store_pos_enable(struct ingenic_tcu_chn *tcu_chn)
++{
++	unsigned int tmp;
++	tmp = tcu_readl(tcu_chn->tcu, CH_TCSR(tcu_chn->index));
++	tcu_writel(tcu_chn->tcu, CH_TCSR(tcu_chn->index), (1 << STORE_POS_EN) | tmp);
++}
++
++static inline void ingenic_tcu_store_pos_disable(struct ingenic_tcu_chn *tcu_chn)
++{
++	unsigned int tmp;
++	tmp = tcu_readl(tcu_chn->tcu, CH_TCSR(tcu_chn->index));
++	tcu_writel(tcu_chn->tcu, CH_TCSR(tcu_chn->index), ~(1 << STORE_POS_EN) | tmp);
++}
++
++void sws_pr_debug(struct ingenic_tcu_chn *tcu_chn);
++void ingenic_tcu_config_chn(struct ingenic_tcu_chn *tcu_chn);
++void ingenic_tcu_clear_irq_flag(struct ingenic_tcu_chn *tcu_chn);
++#endif /* __ingenic_TCU_H__ */
+diff --git a/include/linux/mfd/ingenic_adc.h b/include/linux/mfd/ingenic_adc.h
+new file mode 100644
+index 000000000..ec652f1fe
+--- /dev/null
++++ b/include/linux/mfd/ingenic_adc.h
+@@ -0,0 +1,317 @@
++#ifndef __LINUX_INGENIC_ADC_H__
++#define __LINUX_INGENIC_ADC_H__
++
++#include <linux/device.h>
++
++/*
++ * SAR A/D Controller(SADC) address definition
++ */
++#define	SADC_BASE		0xb0070000
++
++/*************************************************************************
++ * SADC (Smart A/D Controller)
++ *************************************************************************/
++#define BIT0            (1 << 0)
++#define BIT1            (1 << 1)
++#define BIT2            (1 << 2)
++#define BIT3            (1 << 3)
++#define BIT4            (1 << 4)
++#define BIT5            (1 << 5)
++#define BIT6            (1 << 6)
++#define BIT7            (1 << 7)
++#define BIT8            (1 << 8)
++#define BIT9            (1 << 9)
++#define BIT10           (1 << 10)
++#define BIT11           (1 << 11)
++#define BIT12 	        (1 << 12)
++#define BIT13 	        (1 << 13)
++#define BIT14 	        (1 << 14)
++#define BIT15 	        (1 << 15)
++#define BIT16 	        (1 << 16)
++#define BIT17 	        (1 << 17)
++#define BIT18 	        (1 << 18)
++#define BIT19 	        (1 << 19)
++#define BIT20 	        (1 << 20)
++#define BIT21 	        (1 << 21)
++#define BIT22 	        (1 << 22)
++#define BIT23 	        (1 << 23)
++#define BIT24 	        (1 << 24)
++#define BIT25 	        (1 << 25)
++#define BIT26 	        (1 << 26)
++#define BIT27 	        (1 << 27)
++#define BIT28 	        (1 << 28)
++#define BIT29 	        (1 << 29)
++#define BIT30 	        (1 << 30)
++#define BIT31 	        (1 << 31)
++
++
++
++
++
++#define SADC_ENA	(SADC_BASE + 0x00)  /* ADC Enable Register */
++#define SADC_CFG	(SADC_BASE + 0x04)  /* ADC Configure Register */
++#define SADC_CTRL	(SADC_BASE + 0x08)  /* ADC Control Register */
++#define SADC_STATE	(SADC_BASE + 0x0C)  /* ADC Status Register*/
++#define SADC_SAMETIME	(SADC_BASE + 0x10)  /* ADC Same Point Time Register */
++#define SADC_WAITTIME	(SADC_BASE + 0x14)  /* ADC Wait Time Register */
++#define SADC_TSDAT	(SADC_BASE + 0x18)  /* ADC Touch Screen Data Register */
++#define SADC_BATDAT	(SADC_BASE + 0x1C)  /* ADC VBAT Data Register */
++#define SADC_SADDAT	(SADC_BASE + 0x20)  /* ADC AUX Data Register */
++#define SADC_FLT	(SADC_BASE + 0x24)  /* ADC Filter Register */
++
++#define REG_SADC_ENA		REG8(SADC_ENA)
++#define REG_SADC_CFG		REG32(SADC_CFG)
++#define REG_SADC_CTRL		REG8(SADC_CTRL)
++#define REG_SADC_STATE		REG8(SADC_STATE)
++#define REG_SADC_SAMETIME	REG16(SADC_SAMETIME)
++#define REG_SADC_WAITTIME	REG16(SADC_WAITTIME)
++#define REG_SADC_TSDAT		REG32(SADC_TSDAT)
++#define REG_SADC_BATDAT		REG16(SADC_BATDAT)
++#define REG_SADC_SADDAT		REG16(SADC_SADDAT)
++#define REG_SADC_ADCLK		REG32(SADC_ADCLK)
++#define REG_SADC_FLT		REG16(SADC_FLT)
++   #define SADC_FLT_ENA		(1 << 15)
++
++/* ADENA: ADC Enable Register */
++#define SADC_ENA_POWER		(1 << 7)  /* SADC Power control bit */
++#define SADC_ENA_SLP_MD		(1 << 6)  /* SLEEP mode control */
++#define SADC_ENA_TSEN		(1 << 2)  /* Touch Screen Enable */
++#define SADC_ENA_PBATEN		(1 << 1)  /* PBAT Enable */
++#define SADC_ENA_SADCINEN	(1 << 0)  /* AUX n Enable */
++
++/* ADC Configure Register */
++#define SADC_CFG_SPZZ           (1 << 31)
++#define SADC_CFG_TS_DMA		(1 << 15)  /* Touch Screen DMA Enable */
++#define SADC_CFG_XYZ_BIT	13  /* XYZ selection */
++#define SADC_CFG_XYZ_MASK	(0x3 << SADC_CFG_XYZ_BIT)
++  #define SADC_CFG_XY		(0 << SADC_CFG_XYZ_BIT)
++  #define SADC_CFG_XYZ		(1 << SADC_CFG_XYZ_BIT)
++  #define SADC_CFG_XYZ1Z2	(2 << SADC_CFG_XYZ_BIT)
++#define SADC_CFG_SNUM_BIT	10  /* Sample Number */
++#define SADC_CFG_SNUM(x)	(((x) - 1) << SADC_CFG_SNUM_BIT)
++#define SADC_CFG_SNUM_MASK	(0x7 << SADC_CFG_SNUM_BIT)
++  #define SADC_CFG_SNUM_1	(0x0 << SADC_CFG_SNUM_BIT)
++  #define SADC_CFG_SNUM_2	(0x1 << SADC_CFG_SNUM_BIT)
++  #define SADC_CFG_SNUM_3	(0x2 << SADC_CFG_SNUM_BIT)
++  #define SADC_CFG_SNUM_4	(0x3 << SADC_CFG_SNUM_BIT)
++  #define SADC_CFG_SNUM_5	(0x4 << SADC_CFG_SNUM_BIT)
++  #define SADC_CFG_SNUM_6	(0x5 << SADC_CFG_SNUM_BIT)
++  #define SADC_CFG_SNUM_8	(0x6 << SADC_CFG_SNUM_BIT)
++  #define SADC_CFG_SNUM_9	(0x7 << SADC_CFG_SNUM_BIT)
++#define SADC_CFG_CMD_BIT	0  /* ADC Command */
++#define SADC_CFG_CMD_MASK	(0x3 << SADC_CFG_CMD_BIT)
++  #define SADC_CFG_CMD_AUX0	(0x0 << SADC_CFG_CMD_BIT) /* AUX voltage */
++  #define SADC_CFG_CMD_AUX1	(0x1 << SADC_CFG_CMD_BIT) /* AUX1 voltage */
++  #define SADC_CFG_CMD_AUX2	(0x2 << SADC_CFG_CMD_BIT) /* AUX2 voltage */
++  #define SADC_CFG_CMD_RESERVED	(0x3 << SADC_CFG_CMD_BIT) /* Reserved */
++
++/* ADCCTRL: ADC Control Register */
++#define SADC_CTRL_SLPENDM	(1 << 5)  /* Sleep Interrupt Mask */
++#define SADC_CTRL_PENDM		(1 << 4)  /* Pen Down Interrupt Mask */
++#define SADC_CTRL_PENUM		(1 << 3)  /* Pen Up Interrupt Mask */
++#define SADC_CTRL_TSRDYM	(1 << 2)  /* Touch Screen Data Ready Interrupt Mask */
++#define SADC_CTRL_PBATRDYM	(1 << 1)  /* VBAT Data Ready Interrupt Mask */
++#define SADC_CTRL_SRDYM		(1 << 0)  /* AUX Data Ready Interrupt Mask */
++
++/* ADSTATE: ADC Status Register */
++#define SADC_STATE_SLP_RDY	(1 << 7)  /* Sleep state bit */
++#define SADC_STATE_SLEEPND	(1 << 5)  /* Pen Down Interrupt Flag */
++#define SADC_STATE_PEND		(1 << 4)  /* Pen Down Interrupt Flag */
++#define SADC_STATE_PENU		(1 << 3)  /* Pen Up Interrupt Flag */
++#define SADC_STATE_TSRDY	(1 << 2)  /* Touch Screen Data Ready Interrupt Flag */
++#define SADC_STATE_PBATRDY		(1 << 1)  /* VBAT Data Ready Interrupt Flag */
++#define SADC_STATE_SRDY		(1 << 0)  /* AUX Data Ready Interrupt Flag */
++
++/* ADTCH: ADC Touch Screen Data Register */
++#define SADC_TSDAT_TYPE1	(1 << 31)
++#define SADC_TSDAT_DATA1_BIT	16
++#define SADC_TSDAT_DATA1_MASK	(0xfff << SADC_TSDAT_DATA1_BIT)
++#define SADC_TSDAT_TYPE0	(1 << 15)
++#define SADC_TSDAT_DATA0_BIT	0
++#define SADC_TSDAT_DATA0_MASK	(0xfff << SADC_TSDAT_DATA0_BIT)
++
++/* ADCLK: ADC Clock Divide Register */
++#define SADC_ADCLK_CLKDIV_MS	16
++#define SADC_ADCLK_CLKDIV_MS_MASK	(0xffff << SADC_ADCLK_CLKDIV_MS)
++#define SADC_ADCLK_CLKDIV_US	8
++#define SADC_ADCLK_CLKDIV_US_MASK	(0xff << SADC_ADCLK_CLKDIV_US)
++#define SADC_ADCLK_CLKDIV_BIT		0
++#define SADC_ADCLK_CLKDIV_MASK		(0xff << SADC_ADCLK_CLKDIV_BIT)
++
++/*
++ * SADC registers offset definition
++ */
++#define SADC_ADENA_OFFSET	(0x00)	/* rw,  8, 0x00 */
++#define SADC_ADCFG_OFFSET       (0x04)  /* rw, 32, 0x0002000c */
++#define SADC_ADCTRL_OFFSET      (0x08)  /* rw,  8, 0x3f */
++#define SADC_ADSTATE_OFFSET     (0x0c)  /* rw,  8, 0x00 */
++#define SADC_ADSAME_OFFSET    	(0x10)  /* rw, 16, 0x0000 */
++#define SADC_ADWAIT_OFFSET    	(0x14)  /* rw, 16, 0x0000 */
++#define SADC_ADTCH_OFFSET       (0x18)  /* rw, 32, 0x00000000 */
++#define SADC_ADVDAT_OFFSET      (0x1c)  /* rw, 16, 0x0000 */
++#define SADC_ADADAT_OFFSET      (0x20)  /* rw, 16, 0x0000 */
++#define SADC_ADCMD_OFFSET       (0x24)  /* rw, 32, 0x00000000 */
++#define SADC_ADCLK_OFFSET       (0x28)  /* rw, 32, 0x00000000 */
++
++/*
++ * SADC registers address definition
++ */
++#define SADC_ADENA		(SADC_BASE + SADC_ADENA_OFFSET)	 /* ADC Enable Register */
++#define SADC_ADCFG		(SADC_BASE + SADC_ADCFG_OFFSET)	 /* ADC Configure Register */
++#define SADC_ADCTRL		(SADC_BASE + SADC_ADCTRL_OFFSET) /* ADC Control Register */
++#define SADC_ADSTATE		(SADC_BASE + SADC_ADSTATE_OFFSET)/* ADC Status Register*/
++#define SADC_ADSAME		(SADC_BASE + SADC_ADSAME_OFFSET) /* ADC Same Point Time Register */
++#define SADC_ADWAIT		(SADC_BASE + SADC_ADWAIT_OFFSET) /* ADC Wait Time Register */
++#define SADC_ADTCH		(SADC_BASE + SADC_ADTCH_OFFSET)  /* ADC Touch Screen Data Register */
++#define SADC_ADVDAT		(SADC_BASE + SADC_ADVDAT_OFFSET) /* ADC VBAT Data Register */
++#define SADC_ADADAT		(SADC_BASE + SADC_ADADAT_OFFSET) /* ADC AUX Data Register */
++#define SADC_ADCMD		(SADC_BASE + SADC_ADCMD_OFFSET)  /* ADC COMMAND Register */
++#define SADC_ADCLK		(SADC_BASE + SADC_ADCLK_OFFSET)  /* ADC Clock Divide Register */
++
++
++/*
++ * SADC registers common define
++ */
++
++/* ADC Enable Register (ADENA) */
++#define ADENA_POWER		BIT7
++#define ADENA_SLP_MD		BIT6
++#define ADENA_TCHEN		BIT2
++#define ADENA_PENDEN		BIT3
++#define ADENA_VBATEN		BIT1
++#define ADENA_AUXEN		BIT0
++
++/* ADC Configure Register (ADCFG) */
++#define ADCFG_SPZZ           	BIT31
++
++#define ADCFG_CMD_SEL		BIT22
++
++#define ADCFG_DMA_EN		BIT15
++
++#define ADCFG_XYZ_LSB		13
++#define ADCFG_XYZ_MASK		BITS_H2L(14, ADCFG_XYZ_LSB)
++#define ADCFG_XYZ_XYS		(0x0 << ADCFG_XYZ_LSB)
++#define ADCFG_XYZ_XYD		(0x1 << ADCFG_XYZ_LSB)
++#define ADCFG_XYZ_XYZ1Z2	(0x2 << ADCFG_XYZ_LSB)
++#define ADCFG_XYZ_XYZ1Z2X2Y2	(0x3 << ADCFG_XYZ_LSB)
++
++#define ADCFG_SNUM_LSB		10
++#define ADCFG_SNUM_MASK		BITS_H2L(12, ADCFG_SNUM_LSB)
++#define ADCFG_SNUM(n)          (((n) <= 6 ? ((n)-1) : ((n)-2)) << ADCFG_SNUM_LSB)
++
++#define ADCFG_CMD_LSB		0
++#define ADCFG_CMD_MASK		BITS_H2L(1, ADCFG_CMD_LSB)
++#define ADCFG_CMD_AUX(n)	((n) << ADCFG_CMD_LSB)
++
++/* ADC Control Register (ADCCTRL) */
++#define ADCTRL_SLPENDM		BIT5
++#define ADCTRL_PENDM		BIT4
++#define ADCTRL_PENUM		BIT3
++#define ADCTRL_DTCHM		BIT2
++#define ADCTRL_VRDYM		BIT1
++#define ADCTRL_ARDYM		BIT0
++#define ADCTRL_MASK_ALL         (ADCTRL_SLPENDM | ADCTRL_PENDM | ADCTRL_PENUM \
++                                | ADCTRL_DTCHM | ADCTRL_VRDYM | ADCTRL_ARDYM)
++
++/*  ADC Status Register  (ADSTATE) */
++#define ADSTATE_SLP_RDY		BIT7
++#define ADSTATE_SLPEND		BIT5
++#define ADSTATE_PEND		BIT4
++#define ADSTATE_PENU		BIT3
++#define ADSTATE_DTCH		BIT2
++#define ADSTATE_VRDY		BIT1
++#define ADSTATE_ARDY		BIT0
++
++/* ADC Same Point Time Register (ADSAME) */
++#define ADSAME_SCNT_LSB		0
++#define ADSAME_SCNT_MASK	BITS_H2L(15, ADSAME_SCNT_LSB)
++
++/* ADC Wait Pen Down Time Register (ADWAIT) */
++#define ADWAIT_WCNT_LSB		0
++#define ADWAIT_WCNT_MASK	BITS_H2L(15, ADWAIT_WCNT_LSB)
++
++/* ADC Touch Screen Data Register (ADTCH) */
++#define ADTCH_TYPE1		BIT31
++#define ADTCH_TYPE0		BIT15
++
++#define ADTCH_DATA1_LSB		16
++#define ADTCH_DATA1_MASK	BITS_H2L(27, ADTCH_DATA1_LSB)
++
++#define ADTCH_DATA0_LSB		0
++#define ADTCH_DATA0_MASK	BITS_H2L(11, ADTCH_DATA0_LSB)
++
++/* ADC VBAT Date Register (ADVDAT) */
++#define ADVDAT_VDATA_LSB	0
++#define ADVDAT_VDATA_MASK	BITS_H2L(11, ADVDAT_VDATA_LSB)
++
++/* ADC AUX Data Register (ADADAT) */
++#define ADADAT_ADATA_LSB	0
++#define ADADAT_ADATA_MASK	BITS_H2L(11, ADADAT_ADATA_LSB)
++
++/*  ADC Clock Divide Register (ADCLK) */
++#define ADCLK_CLKDIV_MS_LSB	16
++#define ADCLK_CLKDIV_MS_MASK	BITS_H2L(31, ADCLK_CLKDIV_MS_LSB)
++
++#define ADCLK_CLKDIV_US_LSB	8
++#define ADCLK_CLKDIV_US_MASK	BITS_H2L(15, ADCLK_CLKDIV_US_LSB)
++
++#define ADCLK_CLKDIV_LSB	0
++#define ADCLK_CLKDIV_MASK	BITS_H2L(7, ADCLK_CLKDIV_LSB)
++
++/* ADC Filter Register (ADFLT) */
++#define ADFLT_FLT_EN		BIT15
++
++#define ADFLT_FLT_D_LSB		0
++#define ADFLT_FLT_D_MASK	BITS_H2L(11, ADFLT_FLT_D_LSB)
++
++/* ADC Command Register (ADCMD) */
++#define ADCMD_PIL		BIT31
++#define ADCMD_RPU(n)		((n) << 26)
++#define ADCMD_XPSUP		BIT25
++#define ADCMD_YPSUP		BIT23
++#define	ADCMD_XNGRU		BIT21
++#define	ADCMD_YNGRU		BIT20
++#define	ADCMD_VREFNXN		BIT18
++#define	ADCMD_VREFNYN		BIT16
++#define ADCMD_VREFPXP		BIT12
++#define ADCMD_VREFPYP		BIT11
++#define ADCMD_XPADC		BIT10
++#define ADCMD_YPADC		BIT8
++struct ingenic_ts_info{
++	unsigned int x_max;
++	unsigned int x_min;
++	unsigned int y_max;
++	unsigned int y_min;
++	unsigned int z_max;
++	unsigned int z_min;
++	unsigned short x_resolution;
++	unsigned short y_resolution;
++	unsigned short	y_r_plate;
++	unsigned short	x_r_plate;
++	unsigned short  pressure_max;
++	unsigned int	use_5_wire;
++	unsigned int	support_keypad;
++	unsigned int	support_mt_touch;
++	unsigned int	support_sleepmode;
++	void		*private_data;
++};
++
++
++
++/*
++ * ingenic_adc_set_config - Configure a ingenic adc device
++ * @dev: Pointer to a ingenic-adc device
++ * @mask: Mask for the config value to be set
++ * @val: Value to be set
++ *
++ * This function can be used by the ingenic
++ * ADC mfd cells to confgure their options in the shared config register.
++ */
++
++#if 0
++	int ingenic_adc_set_config(struct device *dev, uint32_t mask, uint32_t val);
++#endif
++
++int adc_write_reg(struct device *dev,uint8_t addr_offset,uint32_t mask,uint32_t val);
++uint32_t adc_read_reg(struct device *dev,uint8_t addr_offset);
++#endif /*ingenic_adc.h*/
+diff --git a/include/linux/usb.h b/include/linux/usb.h
+index d6a41841b..b7d079728 100644
+--- a/include/linux/usb.h
++++ b/include/linux/usb.h
+@@ -560,6 +560,7 @@ struct usb3_lpm_parameters {
+  * @speed: device speed: high/full/low (or error)
+  * @rx_lanes: number of rx lanes in use, USB 3.2 adds dual-lane support
+  * @tx_lanes: number of tx lanes in use, USB 3.2 adds dual-lane support
++ * @ssp_rate: SuperSpeed Plus phy signaling rate and lane count
+  * @tt: Transaction Translator info; used with low/full speed dev, highspeed hub
+  * @ttport: device port on that tt hub
+  * @toggle: one bit for each endpoint, with ([0] = IN, [1] = OUT) endpoints
+@@ -636,6 +637,7 @@ struct usb_device {
+ 	enum usb_device_speed	speed;
+ 	unsigned int		rx_lanes;
+ 	unsigned int		tx_lanes;
++	enum usb_ssp_rate	ssp_rate;
+ 
+ 	struct usb_tt	*tt;
+ 	int		ttport;
+@@ -880,6 +882,15 @@ extern struct usb_host_interface *usb_find_alt_setting(
+ 		unsigned int iface_num,
+ 		unsigned int alt_num);
+ 
++#if IS_REACHABLE(CONFIG_USB)
++int usb_for_each_port(void *data, int (*fn)(struct device *, void *));
++#else
++static inline int usb_for_each_port(void *data, int (*fn)(struct device *, void *))
++{
++	return 0;
++}
++#endif
++
+ /* port claiming functions */
+ int usb_hub_claim_port(struct usb_device *hdev, unsigned port1,
+ 		struct usb_dev_state *owner);
+@@ -1476,7 +1487,7 @@ typedef void (*usb_complete_t)(struct urb *);
+  *
+  * Note that transfer_buffer must still be set if the controller
+  * does not support DMA (as indicated by hcd_uses_dma()) and when talking
+- * to root hub. If you have to trasfer between highmem zone and the device
++ * to root hub. If you have to transfer between highmem zone and the device
+  * on such controller, create a bounce buffer or bail out with an error.
+  * If transfer_buffer cannot be set (is in highmem) and the controller is DMA
+  * capable, assign NULL to it, so that usbmon knows not to use the value.
+diff --git a/include/linux/usb/audio-v2.h b/include/linux/usb/audio-v2.h
+index ead8c9a47..8fc2abd7a 100644
+--- a/include/linux/usb/audio-v2.h
++++ b/include/linux/usb/audio-v2.h
+@@ -156,6 +156,20 @@ struct uac2_feature_unit_descriptor {
+ 	__u8 bmaControls[]; /* variable length */
+ } __attribute__((packed));
+ 
++#define UAC2_DT_FEATURE_UNIT_SIZE(ch)		(6 + ((ch) + 1) * 4)
++
++/* As above, but more useful for defining your own descriptors: */
++#define DECLARE_UAC2_FEATURE_UNIT_DESCRIPTOR(ch)		\
++struct uac2_feature_unit_descriptor_##ch {			\
++	__u8  bLength;						\
++	__u8  bDescriptorType;					\
++	__u8  bDescriptorSubtype;				\
++	__u8  bUnitID;						\
++	__u8  bSourceID;					\
++	__le32 bmaControls[ch + 1];				\
++	__u8  iFeature;						\
++} __packed
++
+ /* 4.7.2.10 Effect Unit Descriptor */
+ 
+ struct uac2_effect_unit_descriptor {
+diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h
+index 604c6c514..1cffa3474 100644
+--- a/include/linux/usb/ch9.h
++++ b/include/linux/usb/ch9.h
+@@ -36,62 +36,24 @@
+ #include <linux/device.h>
+ #include <uapi/linux/usb/ch9.h>
+ 
+-/**
+- * usb_ep_type_string() - Returns human readable-name of the endpoint type.
+- * @ep_type: The endpoint type to return human-readable name for.  If it's not
+- *   any of the types: USB_ENDPOINT_XFER_{CONTROL, ISOC, BULK, INT},
+- *   usually got by usb_endpoint_type(), the string 'unknown' will be returned.
+- */
+-extern const char *usb_ep_type_string(int ep_type);
++/* USB 3.2 SuperSpeed Plus phy signaling rate generation and lane count */
+ 
+-/**
+- * usb_speed_string() - Returns human readable-name of the speed.
+- * @speed: The speed to return human-readable name for.  If it's not
+- *   any of the speeds defined in usb_device_speed enum, string for
+- *   USB_SPEED_UNKNOWN will be returned.
+- */
+-extern const char *usb_speed_string(enum usb_device_speed speed);
++enum usb_ssp_rate {
++	USB_SSP_GEN_UNKNOWN = 0,
++	USB_SSP_GEN_2x1,
++	USB_SSP_GEN_1x2,
++	USB_SSP_GEN_2x2,
++};
+ 
+-/**
+- * usb_get_maximum_speed - Get maximum requested speed for a given USB
+- * controller.
+- * @dev: Pointer to the given USB controller device
+- *
+- * The function gets the maximum speed string from property "maximum-speed",
+- * and returns the corresponding enum usb_device_speed.
+- */
++extern const char *usb_ep_type_string(int ep_type);
++extern const char *usb_speed_string(enum usb_device_speed speed);
+ extern enum usb_device_speed usb_get_maximum_speed(struct device *dev);
+-
+-/**
+- * usb_state_string - Returns human readable name for the state.
+- * @state: The state to return a human-readable name for. If it's not
+- *	any of the states devices in usb_device_state_string enum,
+- *	the string UNKNOWN will be returned.
+- */
++extern enum usb_ssp_rate usb_get_maximum_ssp_rate(struct device *dev);
+ extern const char *usb_state_string(enum usb_device_state state);
++unsigned int usb_decode_interval(const struct usb_endpoint_descriptor *epd,
++				 enum usb_device_speed speed);
+ 
+ #ifdef CONFIG_TRACING
+-/**
+- * usb_decode_ctrl - Returns human readable representation of control request.
+- * @str: buffer to return a human-readable representation of control request.
+- *       This buffer should have about 200 bytes.
+- * @size: size of str buffer.
+- * @bRequestType: matches the USB bmRequestType field
+- * @bRequest: matches the USB bRequest field
+- * @wValue: matches the USB wValue field (CPU byte order)
+- * @wIndex: matches the USB wIndex field (CPU byte order)
+- * @wLength: matches the USB wLength field (CPU byte order)
+- *
+- * Function returns decoded, formatted and human-readable description of
+- * control request packet.
+- *
+- * The usage scenario for this is for tracepoints, so function as a return
+- * use the same value as in parameters. This approach allows to use this
+- * function in TP_printk
+- *
+- * Important: wValue, wIndex, wLength parameters before invoking this function
+- * should be processed by le16_to_cpu macro.
+- */
+ extern const char *usb_decode_ctrl(char *str, size_t size, __u8 bRequestType,
+ 				   __u8 bRequest, __u16 wValue, __u16 wIndex,
+ 				   __u16 wLength);
+diff --git a/include/linux/usb/composite.h b/include/linux/usb/composite.h
+index a2d229ab6..5e002c39c 100644
+--- a/include/linux/usb/composite.h
++++ b/include/linux/usb/composite.h
+@@ -271,7 +271,7 @@ int config_ep_by_speed(struct usb_gadget *g, struct usb_function *f,
+  * @bConfigurationValue: Copied into configuration descriptor.
+  * @iConfiguration: Copied into configuration descriptor.
+  * @bmAttributes: Copied into configuration descriptor.
+- * @MaxPower: Power consumtion in mA. Used to compute bMaxPower in the
++ * @MaxPower: Power consumption in mA. Used to compute bMaxPower in the
+  *	configuration descriptor after considering the bus speed.
+  * @cdev: assigned by @usb_add_config() before calling @bind(); this is
+  *	the device associated with this configuration.
+@@ -525,6 +525,8 @@ extern struct usb_string *usb_gstrings_attach(struct usb_composite_dev *cdev,
+ extern int usb_string_ids_n(struct usb_composite_dev *c, unsigned n);
+ 
+ extern void composite_disconnect(struct usb_gadget *gadget);
++extern void composite_reset(struct usb_gadget *gadget);
++
+ extern int composite_setup(struct usb_gadget *gadget,
+ 		const struct usb_ctrlrequest *ctrl);
+ extern void composite_suspend(struct usb_gadget *gadget);
+diff --git a/include/linux/usb/f_mtp.h b/include/linux/usb/f_mtp.h
+new file mode 100644
+index 000000000..4e8417791
+--- /dev/null
++++ b/include/linux/usb/f_mtp.h
+@@ -0,0 +1,23 @@
++/*
++ * Gadget Function Driver for MTP
++ *
++ * Copyright (C) 2010 Google, Inc.
++ * Author: Mike Lockwood <lockwood@android.com>
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#ifndef __LINUX_USB_F_MTP_H
++#define __LINUX_USB_F_MTP_H
++
++#include <uapi/linux/usb/f_mtp.h>
++
++#endif /* __LINUX_USB_F_MTP_H */
+diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
+index e7351d64f..10fe57cf4 100644
+--- a/include/linux/usb/gadget.h
++++ b/include/linux/usb/gadget.h
+@@ -197,7 +197,7 @@ struct usb_ep_caps {
+  * @name:identifier for the endpoint, such as "ep-a" or "ep9in-bulk"
+  * @ops: Function pointers used to access hardware-specific operations.
+  * @ep_list:the gadget's ep_list holds all of its endpoints
+- * @caps:The structure describing types and directions supported by endoint.
++ * @caps:The structure describing types and directions supported by endpoint.
+  * @enabled: The current endpoint enabled/disabled state.
+  * @claimed: True if this endpoint is claimed by a function.
+  * @maxpacket:The maximum packet size used on this endpoint.  The initial
+@@ -323,9 +323,13 @@ struct usb_gadget_ops {
+ 			struct usb_gadget_driver *);
+ 	int	(*udc_stop)(struct usb_gadget *);
+ 	void	(*udc_set_speed)(struct usb_gadget *, enum usb_device_speed);
++	void	(*udc_set_ssp_rate)(struct usb_gadget *gadget,
++			enum usb_ssp_rate rate);
++	void	(*udc_async_callbacks)(struct usb_gadget *gadget, bool enable);
+ 	struct usb_ep *(*match_ep)(struct usb_gadget *,
+ 			struct usb_endpoint_descriptor *,
+ 			struct usb_ss_ep_comp_descriptor *);
++	int	(*check_config)(struct usb_gadget *gadget);
+ };
+ 
+ /**
+@@ -339,6 +343,10 @@ struct usb_gadget_ops {
+  * @speed: Speed of current connection to USB host.
+  * @max_speed: Maximal speed the UDC can handle.  UDC must support this
+  *      and all slower speeds.
++ * @ssp_rate: Current connected SuperSpeed Plus signaling rate and lane count.
++ * @max_ssp_rate: Maximum SuperSpeed Plus signaling rate and lane count the UDC
++ *	can handle. The UDC must support this and all slower speeds and lower
++ *	number of lanes.
+  * @state: the state we are now (attached, suspended, configured, etc)
+  * @name: Identifies the controller hardware type.  Used in diagnostics
+  *	and sometimes configuration.
+@@ -406,6 +414,11 @@ struct usb_gadget {
+ 	struct list_head		ep_list;	/* of usb_ep */
+ 	enum usb_device_speed		speed;
+ 	enum usb_device_speed		max_speed;
++
++	/* USB SuperSpeed Plus only */
++	enum usb_ssp_rate		ssp_rate;
++	enum usb_ssp_rate		max_ssp_rate;
++
+ 	enum usb_device_state		state;
+ 	const char			*name;
+ 	struct device			dev;
+@@ -479,7 +492,7 @@ extern char *usb_get_gadget_udc_name(void);
+  */
+ static inline size_t usb_ep_align(struct usb_ep *ep, size_t len)
+ {
+-	int max_packet_size = (size_t)usb_endpoint_maxp(ep->desc) & 0x7ff;
++	int max_packet_size = (size_t)usb_endpoint_maxp(ep->desc);
+ 
+ 	return round_up(len, max_packet_size);
+ }
+@@ -596,6 +609,7 @@ int usb_gadget_connect(struct usb_gadget *gadget);
+ int usb_gadget_disconnect(struct usb_gadget *gadget);
+ int usb_gadget_deactivate(struct usb_gadget *gadget);
+ int usb_gadget_activate(struct usb_gadget *gadget);
++int usb_gadget_check_config(struct usb_gadget *gadget);
+ #else
+ static inline int usb_gadget_frame_number(struct usb_gadget *gadget)
+ { return 0; }
+@@ -619,6 +633,8 @@ static inline int usb_gadget_deactivate(struct usb_gadget *gadget)
+ { return 0; }
+ static inline int usb_gadget_activate(struct usb_gadget *gadget)
+ { return 0; }
++static inline int usb_gadget_check_config(struct usb_gadget *gadget)
++{ return 0; }
+ #endif /* CONFIG_USB_GADGET */
+ 
+ /*-------------------------------------------------------------------------*/
+diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h
+index c0cf20b19..98d1921f0 100644
+--- a/include/linux/usb/hcd.h
++++ b/include/linux/usb/hcd.h
+@@ -59,7 +59,7 @@
+  * USB Host Controller Driver (usb_hcd) framework
+  *
+  * Since "struct usb_bus" is so thin, you can't share much code in it.
+- * This framework is a layer over that, and should be more sharable.
++ * This framework is a layer over that, and should be more shareable.
+  */
+ 
+ /*-------------------------------------------------------------------------*/
+@@ -302,7 +302,7 @@ struct hc_driver {
+ 	 * (optional) these hooks allow an HCD to override the default DMA
+ 	 * mapping and unmapping routines.  In general, they shouldn't be
+ 	 * necessary unless the host controller has special DMA requirements,
+-	 * such as alignment contraints.  If these are not specified, the
++	 * such as alignment constraints.  If these are not specified, the
+ 	 * general usb_hcd_(un)?map_urb_for_dma functions will be used instead
+ 	 * (and it may be a good idea to call these functions in your HCD
+ 	 * implementation)
+@@ -412,7 +412,10 @@ struct hc_driver {
+ 	int	(*find_raw_port_number)(struct usb_hcd *, int);
+ 	/* Call for power on/off the port if necessary */
+ 	int	(*port_power)(struct usb_hcd *hcd, int portnum, bool enable);
+-
++	/* Call for SINGLE_STEP_SET_FEATURE Test for USB2 EH certification */
++#define EHSET_TEST_SINGLE_STEP_SET_FEATURE 0x06
++	int	(*submit_single_step_set_feature)(struct usb_hcd *,
++			struct urb *, int);
+ };
+ 
+ static inline int hcd_giveback_urb_in_bh(struct usb_hcd *hcd)
+@@ -477,6 +480,14 @@ int usb_hcd_setup_local_mem(struct usb_hcd *hcd, phys_addr_t phys_addr,
+ 
+ struct platform_device;
+ extern void usb_hcd_platform_shutdown(struct platform_device *dev);
++#ifdef CONFIG_USB_HCD_TEST_MODE
++extern int ehset_single_step_set_feature(struct usb_hcd *hcd, int port);
++#else
++static inline int ehset_single_step_set_feature(struct usb_hcd *hcd, int port)
++{
++	return 0;
++}
++#endif /* CONFIG_USB_HCD_TEST_MODE */
+ 
+ #ifdef CONFIG_USB_PCI
+ struct pci_dev;
+@@ -737,10 +748,6 @@ static inline void usbmon_urb_complete(struct usb_bus *bus, struct urb *urb,
+ 
+ /* random stuff */
+ 
+-#define	RUN_CONTEXT (in_irq() ? "in_irq" \
+-		: (in_interrupt() ? "in_interrupt" : "can sleep"))
+-
+-
+ /* This rwsem is for use only by the hub driver and ehci-hcd.
+  * Nobody else should touch it.
+  */
+diff --git a/include/linux/usb/otg-fsm.h b/include/linux/usb/otg-fsm.h
+index 8ef7d148c..e78eb577d 100644
+--- a/include/linux/usb/otg-fsm.h
++++ b/include/linux/usb/otg-fsm.h
+@@ -196,7 +196,6 @@ struct otg_fsm {
+ 	struct mutex lock;
+ 	u8 *host_req_flag;
+ 	struct delayed_work hnp_polling_work;
+-	bool hnp_work_inited;
+ 	bool state_changed;
+ };
+ 
+diff --git a/include/linux/usb/otg.h b/include/linux/usb/otg.h
+index 69f1b6328..6475f880b 100644
+--- a/include/linux/usb/otg.h
++++ b/include/linux/usb/otg.h
+@@ -125,8 +125,9 @@ enum usb_dr_mode {
+  * @dev: Pointer to the given device
+  *
+  * The function gets phy interface string from property 'dr_mode',
+- * and returns the correspondig enum usb_dr_mode
++ * and returns the corresponding enum usb_dr_mode
+  */
+ extern enum usb_dr_mode usb_get_dr_mode(struct device *dev);
++extern enum usb_dr_mode usb_get_role_switch_default_mode(struct device *dev);
+ 
+ #endif /* __LINUX_USB_OTG_H */
+diff --git a/include/linux/usb/pd.h b/include/linux/usb/pd.h
+index 433040ff8..3a805e2ec 100644
+--- a/include/linux/usb/pd.h
++++ b/include/linux/usb/pd.h
+@@ -459,7 +459,7 @@ static inline unsigned int rdo_max_power(u32 rdo)
+ #define PD_T_RECEIVER_RESPONSE	15	/* 15ms max */
+ #define PD_T_SOURCE_ACTIVITY	45
+ #define PD_T_SINK_ACTIVITY	135
+-#define PD_T_SINK_WAIT_CAP	310	/* 310 - 620 ms */
++#define PD_T_SINK_WAIT_CAP	240
+ #define PD_T_PS_TRANSITION	500
+ #define PD_T_SRC_TRANSITION	35
+ #define PD_T_DRP_SNK		40
+diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h
+index e4de6bc1f..a9971c273 100644
+--- a/include/linux/usb/phy.h
++++ b/include/linux/usb/phy.h
+@@ -144,6 +144,8 @@ struct usb_phy {
+ 	 */
+ 	int	(*set_wakeup)(struct usb_phy *x, bool enabled);
+ 
++	int	(*get_wakeup)(struct usb_phy *x);
++
+ 	/* notify phy connect status change */
+ 	int	(*notify_connect)(struct usb_phy *x,
+ 			enum usb_device_speed speed);
+@@ -316,6 +318,15 @@ usb_phy_set_wakeup(struct usb_phy *x, bool enabled)
+ 		return 0;
+ }
+ 
++static inline int
++usb_phy_get_wakeup(struct usb_phy *x)
++{
++	if (x && x->get_wakeup)
++		return x->get_wakeup(x);
++	else
++		return 0;
++}
++
+ static inline int
+ usb_phy_notify_connect(struct usb_phy *x, enum usb_device_speed speed)
+ {
+diff --git a/include/linux/usb/quirks.h b/include/linux/usb/quirks.h
+index 5e4c497f5..eeb7c2157 100644
+--- a/include/linux/usb/quirks.h
++++ b/include/linux/usb/quirks.h
+@@ -32,7 +32,7 @@
+ #define USB_QUIRK_DELAY_INIT			BIT(6)
+ 
+ /*
+- * For high speed and super speed interupt endpoints, the USB 2.0 and
++ * For high speed and super speed interrupt endpoints, the USB 2.0 and
+  * USB 3.0 spec require the interval in microframes
+  * (1 microframe = 125 microseconds) to be calculated as
+  * interval = 2 ^ (bInterval-1).
+diff --git a/include/linux/usb/role.h b/include/linux/usb/role.h
+index b9ccaeb8a..b5deafd91 100644
+--- a/include/linux/usb/role.h
++++ b/include/linux/usb/role.h
+@@ -65,6 +65,7 @@ void usb_role_switch_unregister(struct usb_role_switch *sw);
+ 
+ void usb_role_switch_set_drvdata(struct usb_role_switch *sw, void *data);
+ void *usb_role_switch_get_drvdata(struct usb_role_switch *sw);
++const char *usb_role_string(enum usb_role role);
+ #else
+ static inline int usb_role_switch_set_role(struct usb_role_switch *sw,
+ 		enum usb_role role)
+@@ -115,6 +116,11 @@ static inline void *usb_role_switch_get_drvdata(struct usb_role_switch *sw)
+ 	return NULL;
+ }
+ 
++static inline const char *usb_role_string(enum usb_role role)
++{
++	return "unknown";
++}
++
+ #endif
+ 
+ #endif /* __LINUX_USB_ROLE_H */
+diff --git a/include/linux/usb/usbnet.h b/include/linux/usb/usbnet.h
+index 8110c29fa..2e4f7721f 100644
+--- a/include/linux/usb/usbnet.h
++++ b/include/linux/usb/usbnet.h
+@@ -83,8 +83,6 @@ struct usbnet {
+ #		define EVENT_LINK_CHANGE	11
+ #		define EVENT_SET_RX_MODE	12
+ #		define EVENT_NO_IP_ALIGN	13
+-	u32			rx_speed;	/* in bps - NOT Mbps */
+-	u32			tx_speed;	/* in bps - NOT Mbps */
+ };
+ 
+ static inline struct usb_driver *driver_of(struct usb_interface *intf)
+diff --git a/include/media/ingenic_video_nr.h b/include/media/ingenic_video_nr.h
+new file mode 100644
+index 000000000..70ec7bcbd
+--- /dev/null
++++ b/include/media/ingenic_video_nr.h
+@@ -0,0 +1,23 @@
++#ifndef __INGENIC_VIDEO_NR_H__
++#define __INGENIC_VIDEO_NR_H__
++
++enum ingenic_video_nr {
++	INGENIC_ROTATE_VIDEO_NR = 0,
++	INGENIC_HELIX_VIDEO_NR,		/*1*/
++	INGENIC_FELIX_VIDEO_NR,		/*2*/
++	INGENIC_VIC0_VIDEO_NR,		/*3*/
++	INGENIC_MSCA0_CH0_VIDEO_NR,	/*4*/
++	INGENIC_MSCA0_CH1_VIDEO_NR,	/*5*/
++	INGENIC_MSCA0_CH2_VIDEO_NR,	/*6*/
++	INGENIC_VIC1_VIDEO_NR,		/*7*/
++	INGENIC_MSCA1_CH0_VIDEO_NR,	/*8*/
++	INGENIC_MSCA1_CH1_VIDEO_NR,	/*9*/
++	INGENIC_MSCA1_CH2_VIDEO_NR,	/*10*/
++	INGENIC_CIM_VIDEO_NR_0,		/*11*/
++	INGENIC_UVC_VIDEO_NR,		/*12*/
++	INGENIC_VIC2_VIDEO_NR,		/*13*/
++	INGENIC_CIM_VIDEO_NR_1,		/*14*/
++	INGENIC_DPU_COMP_VIDEO_NR,		/*15*/
++};
++
++#endif
+diff --git a/include/media/v4l2-ioctl.h b/include/media/v4l2-ioctl.h
+index 86878fba3..3aaaf9eb3 100644
+--- a/include/media/v4l2-ioctl.h
++++ b/include/media/v4l2-ioctl.h
+@@ -496,6 +496,12 @@ struct v4l2_ioctl_ops {
+ 	/* Crop ioctls */
+ 	int (*vidioc_g_pixelaspect)(struct file *file, void *fh,
+ 				    int buf_type, struct v4l2_fract *aspect);
++	int (*vidioc_cropcap)(struct file *file, void *fh,
++					struct v4l2_cropcap *a);
++	int (*vidioc_g_crop)(struct file *file, void *fh,
++					struct v4l2_crop *a);
++	int (*vidioc_s_crop)(struct file *file, void *fh,
++					const struct v4l2_crop *a);
+ 	int (*vidioc_g_selection)(struct file *file, void *fh,
+ 				  struct v4l2_selection *s);
+ 	int (*vidioc_s_selection)(struct file *file, void *fh,
+diff --git a/include/media/v4l2-subdev.h b/include/media/v4l2-subdev.h
+index 73150520c..fadfe6418 100644
+--- a/include/media/v4l2-subdev.h
++++ b/include/media/v4l2-subdev.h
+@@ -422,6 +422,9 @@ struct v4l2_subdev_video_ops {
+ 	int (*g_tvnorms_output)(struct v4l2_subdev *sd, v4l2_std_id *std);
+ 	int (*g_input_status)(struct v4l2_subdev *sd, u32 *status);
+ 	int (*s_stream)(struct v4l2_subdev *sd, int enable);
++	int (*cropcap)(struct v4l2_subdev *sd, struct v4l2_cropcap *cc);
++	int (*g_crop)(struct v4l2_subdev *sd, struct v4l2_crop *crop);
++	int (*s_crop)(struct v4l2_subdev *sd, const struct v4l2_crop *crop);
+ 	int (*g_pixelaspect)(struct v4l2_subdev *sd, struct v4l2_fract *aspect);
+ 	int (*g_frame_interval)(struct v4l2_subdev *sd,
+ 				struct v4l2_subdev_frame_interval *interval);
+diff --git a/include/media/videobuf2-dma-contig-ingenic.h b/include/media/videobuf2-dma-contig-ingenic.h
+new file mode 100644
+index 000000000..5f9378c74
+--- /dev/null
++++ b/include/media/videobuf2-dma-contig-ingenic.h
+@@ -0,0 +1,32 @@
++/*
++ * videobuf2-dma-contig.h - DMA contig memory allocator for videobuf2
++ *
++ * Copyright (C) 2010 Samsung Electronics
++ *
++ * Author: Pawel Osciak <pawel@osciak.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation.
++ */
++
++#ifndef _MEDIA_VIDEOBUF2_DMA_CONTIG_H
++#define _MEDIA_VIDEOBUF2_DMA_CONTIG_H
++
++#include <media/videobuf2-core.h>
++#include <linux/dma-mapping.h>
++
++static inline dma_addr_t
++ingenic_vb2_dma_contig_plane_dma_addr(struct vb2_buffer *vb, unsigned int plane_no)
++{
++	dma_addr_t *addr = vb2_plane_cookie(vb, plane_no);
++
++	return *addr;
++}
++
++void *ingenic_vb2_dma_contig_init_ctx(struct device *dev);
++void ingenic_vb2_dma_contig_cleanup_ctx(void *alloc_ctx);
++
++extern const struct vb2_mem_ops ingenic_vb2_dma_contig_memops;
++
++#endif
+diff --git a/include/uapi/linux/android/binder.h b/include/uapi/linux/android/binder.h
+index 3abb5b15a..5756df2f5 100644
+--- a/include/uapi/linux/android/binder.h
++++ b/include/uapi/linux/android/binder.h
+@@ -24,6 +24,10 @@
+ #include <linux/types.h>
+ #include <linux/ioctl.h>
+ 
++#ifndef CONFIG_ANDROID_BINDER_IPC_64BIT
++#define BINDER_IPC_32BIT 1
++#endif
++
+ #define B_PACK_CHARS(c1, c2, c3, c4) \
+ 	((((c1)<<24)) | (((c2)<<16)) | (((c3)<<8)) | (c4))
+ #define B_TYPE_LARGE 0x85
+diff --git a/include/uapi/linux/tty_flags.h b/include/uapi/linux/tty_flags.h
+index 6a3ac496a..900a32e63 100644
+--- a/include/uapi/linux/tty_flags.h
++++ b/include/uapi/linux/tty_flags.h
+@@ -39,7 +39,7 @@
+  * WARNING: These flags are no longer used and have been superceded by the
+  *	    TTY_PORT_ flags in the iflags field (and not userspace-visible)
+  */
+-#ifndef __KERNEL__
++#ifndef _KERNEL_
+ #define ASYNCB_INITIALIZED	31 /* Serial port was initialized */
+ #define ASYNCB_SUSPENDED	30 /* Serial port is suspended */
+ #define ASYNCB_NORMAL_ACTIVE	29 /* Normal device is active */
+@@ -81,7 +81,7 @@
+ #define ASYNC_SPD_WARP		(ASYNC_SPD_HI|ASYNC_SPD_SHI)
+ #define ASYNC_SPD_MASK		(ASYNC_SPD_HI|ASYNC_SPD_VHI|ASYNC_SPD_SHI)
+ 
+-#ifndef __KERNEL__
++#ifndef _KERNEL_
+ /* These flags are no longer used (and were always masked from userspace) */
+ #define ASYNC_INITIALIZED	(1U << ASYNCB_INITIALIZED)
+ #define ASYNC_NORMAL_ACTIVE	(1U << ASYNCB_NORMAL_ACTIVE)
+diff --git a/include/uapi/linux/usb/ch9.h b/include/uapi/linux/usb/ch9.h
+index 0f865ae4b..17ce56198 100644
+--- a/include/uapi/linux/usb/ch9.h
++++ b/include/uapi/linux/usb/ch9.h
+@@ -968,9 +968,22 @@ struct usb_ssp_cap_descriptor {
+ 	__le32 bmSublinkSpeedAttr[1]; /* list of sublink speed attrib entries */
+ #define USB_SSP_SUBLINK_SPEED_SSID	(0xf)		/* sublink speed ID */
+ #define USB_SSP_SUBLINK_SPEED_LSE	(0x3 << 4)	/* Lanespeed exponent */
++#define USB_SSP_SUBLINK_SPEED_LSE_BPS		0
++#define USB_SSP_SUBLINK_SPEED_LSE_KBPS		1
++#define USB_SSP_SUBLINK_SPEED_LSE_MBPS		2
++#define USB_SSP_SUBLINK_SPEED_LSE_GBPS		3
++
+ #define USB_SSP_SUBLINK_SPEED_ST	(0x3 << 6)	/* Sublink type */
++#define USB_SSP_SUBLINK_SPEED_ST_SYM_RX		0
++#define USB_SSP_SUBLINK_SPEED_ST_ASYM_RX	1
++#define USB_SSP_SUBLINK_SPEED_ST_SYM_TX		2
++#define USB_SSP_SUBLINK_SPEED_ST_ASYM_TX	3
++
+ #define USB_SSP_SUBLINK_SPEED_RSVD	(0x3f << 8)	/* Reserved */
+ #define USB_SSP_SUBLINK_SPEED_LP	(0x3 << 14)	/* Link protocol */
++#define USB_SSP_SUBLINK_SPEED_LP_SS		0
++#define USB_SSP_SUBLINK_SPEED_LP_SSP		1
++
+ #define USB_SSP_SUBLINK_SPEED_LSM	(0xff << 16)	/* Lanespeed mantissa */
+ } __attribute__((packed));
+ 
+diff --git a/include/uapi/linux/usb/f_mtp.h b/include/uapi/linux/usb/f_mtp.h
+new file mode 100644
+index 000000000..503291855
+--- /dev/null
++++ b/include/uapi/linux/usb/f_mtp.h
+@@ -0,0 +1,61 @@
++/*
++ * Gadget Function Driver for MTP
++ *
++ * Copyright (C) 2010 Google, Inc.
++ * Author: Mike Lockwood <lockwood@android.com>
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#ifndef _UAPI_LINUX_USB_F_MTP_H
++#define _UAPI_LINUX_USB_F_MTP_H
++
++#include <linux/ioctl.h>
++#include <linux/types.h>
++
++struct mtp_file_range {
++	/* file descriptor for file to transfer */
++	int			fd;
++	/* offset in file for start of transfer */
++	loff_t		offset;
++	/* number of bytes to transfer */
++	int64_t		length;
++	/* MTP command ID for data header,
++	 * used only for MTP_SEND_FILE_WITH_HEADER
++	 */
++	uint16_t	command;
++	/* MTP transaction ID for data header,
++	 * used only for MTP_SEND_FILE_WITH_HEADER
++	 */
++	uint32_t	transaction_id;
++};
++
++struct mtp_event {
++	/* size of the event */
++	size_t		length;
++	/* event data to send */
++	void		*data;
++};
++
++/* Sends the specified file range to the host */
++#define MTP_SEND_FILE              _IOW('M', 0, struct mtp_file_range)
++/* Receives data from the host and writes it to a file.
++ * The file is created if it does not exist.
++ */
++#define MTP_RECEIVE_FILE           _IOW('M', 1, struct mtp_file_range)
++/* Sends an event to the host via the interrupt endpoint */
++#define MTP_SEND_EVENT             _IOW('M', 3, struct mtp_event)
++/* Sends the specified file range to the host,
++ * with a 12 byte MTP data packet header at the beginning.
++ */
++#define MTP_SEND_FILE_WITH_HEADER  _IOW('M', 4, struct mtp_file_range)
++
++#endif /* _UAPI_LINUX_USB_F_MTP_H */
+diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
+index 534eaa4d3..52ca5ba4c 100644
+--- a/include/uapi/linux/videodev2.h
++++ b/include/uapi/linux/videodev2.h
+@@ -583,6 +583,7 @@ struct v4l2_pix_format {
+ #define V4L2_PIX_FMT_UV8     v4l2_fourcc('U', 'V', '8', ' ') /*  8  UV 4:4 */
+ 
+ /* Luminance+Chrominance formats */
++#define V4L2_PIX_FMT_JZ420B  v4l2_fourcc('J', 'Z', '1', '2') /* 12  YUV 4:2:0 B   */
+ #define V4L2_PIX_FMT_YUYV    v4l2_fourcc('Y', 'U', 'Y', 'V') /* 16  YUV 4:2:2     */
+ #define V4L2_PIX_FMT_YYUV    v4l2_fourcc('Y', 'Y', 'U', 'V') /* 16  YUV 4:2:2     */
+ #define V4L2_PIX_FMT_YVYU    v4l2_fourcc('Y', 'V', 'Y', 'U') /* 16 YVU 4:2:2 */
+diff --git a/include/video/ingenic_logo.h b/include/video/ingenic_logo.h
+new file mode 100644
+index 000000000..8d6602df1
+--- /dev/null
++++ b/include/video/ingenic_logo.h
+@@ -0,0 +1,15 @@
++#ifndef __LOGO_H__
++#define __LOGO_H__
++
++struct _logo_info {
++	int width;
++	int height;
++	int bpp;
++	unsigned char *p8;
++	unsigned int background_color;
++} __attribute__ ((packed));
++
++extern struct _logo_info logo_info;
++extern unsigned char logo_buf_initdata[];
++
++#endif /* __LOGO_H__ */
+diff --git a/kernel/dma/coherent.c b/kernel/dma/coherent.c
+index 5b5b6c7ec..470b6111e 100644
+--- a/kernel/dma/coherent.c
++++ b/kernel/dma/coherent.c
+@@ -52,11 +52,13 @@ static int dma_init_coherent_memory(phys_addr_t phys_addr,
+ 		goto out;
+ 	}
+ 
+-	mem_base = memremap(phys_addr, size, MEMREMAP_WC);
++	//mem_base = memremap(phys_addr, size, MEMREMAP_WB);
++	mem_base = ioremap(phys_addr, size);
+ 	if (!mem_base) {
+ 		ret = -EINVAL;
+ 		goto out;
+ 	}
++
+ 	dma_mem = kzalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL);
+ 	if (!dma_mem) {
+ 		ret = -ENOMEM;
+@@ -80,7 +82,7 @@ static int dma_init_coherent_memory(phys_addr_t phys_addr,
+ out:
+ 	kfree(dma_mem);
+ 	if (mem_base)
+-		memunmap(mem_base);
++		iounmap(mem_base);
+ 	return ret;
+ }
+ 
+@@ -89,7 +91,7 @@ static void dma_release_coherent_memory(struct dma_coherent_mem *mem)
+ 	if (!mem)
+ 		return;
+ 
+-	memunmap(mem->virt_base);
++	iounmap(mem->virt_base);
+ 	kfree(mem->bitmap);
+ 	kfree(mem);
+ }
+@@ -111,7 +113,7 @@ static int dma_assign_coherent_memory(struct device *dev,
+  * Declare a region of memory to be handed out by dma_alloc_coherent() when it
+  * is asked for coherent memory for this device.  This shall only be used
+  * from platform code, usually based on the device tree description.
+- * 
++ *
+  * phys_addr is the CPU physical address to which the memory is currently
+  * assigned (this will be ioremapped so the CPU can access the region).
+  *
+@@ -140,11 +142,40 @@ int dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
+ 	return ret;
+ }
+ 
++static int dma_bitmap_find_free_region(unsigned long *bitmap, unsigned int bits, unsigned int pages)
++{
++	unsigned int pos, end;		/* scans bitmap by regions of size order */
++	unsigned long start = 0;
++
++	/*step = 1 << 5 pages. */
++	for (pos = 0; (end = pos + (1U << 5)) <= bits; pos = end) {
++		start = bitmap_find_next_zero_area(bitmap, bits, pos, pages, 0);
++		if( start > bits) {
++			return -ENOMEM;
++		}
++
++		break;
++	}
++
++	//ALLOC buffer.
++	bitmap_set(bitmap, start, pages);
++
++	return start;
++}
++
++static int dma_bitmap_release_region(unsigned long *bitmap, unsigned int bits, int pages)
++{
++	bitmap_clear(bitmap, bits, pages);
++
++	return 0;
++}
++
++
+ static void *__dma_alloc_from_coherent(struct device *dev,
+ 				       struct dma_coherent_mem *mem,
+ 				       ssize_t size, dma_addr_t *dma_handle)
+ {
+-	int order = get_order(size);
++	unsigned int pages = ALIGN(size, PAGE_SIZE) >> PAGE_SHIFT;
+ 	unsigned long flags;
+ 	int pageno;
+ 	void *ret;
+@@ -154,7 +185,8 @@ static void *__dma_alloc_from_coherent(struct device *dev,
+ 	if (unlikely(size > ((dma_addr_t)mem->size << PAGE_SHIFT)))
+ 		goto err;
+ 
+-	pageno = bitmap_find_free_region(mem->bitmap, mem->size, order);
++	//pageno = bitmap_find_free_region(mem->bitmap, mem->size, order);
++	pageno = dma_bitmap_find_free_region(mem->bitmap, mem->size, pages);
+ 	if (unlikely(pageno < 0))
+ 		goto err;
+ 
+@@ -164,8 +196,11 @@ static void *__dma_alloc_from_coherent(struct device *dev,
+ 	*dma_handle = dma_get_device_base(dev, mem) +
+ 			((dma_addr_t)pageno << PAGE_SHIFT);
+ 	ret = mem->virt_base + ((dma_addr_t)pageno << PAGE_SHIFT);
++	
++	dev_dbg(dev, "%s, allocated@ 0x%p, start: %d, pages: %d\n", __func__, ret, pageno, pages);
++
+ 	spin_unlock_irqrestore(&mem->spinlock, flags);
+-	memset(ret, 0, size);
++	//memset(ret, 0, size);
+ 	return ret;
+ err:
+ 	spin_unlock_irqrestore(&mem->spinlock, flags);
+@@ -209,15 +244,16 @@ void *dma_alloc_from_global_coherent(struct device *dev, ssize_t size,
+ }
+ 
+ static int __dma_release_from_coherent(struct dma_coherent_mem *mem,
+-				       int order, void *vaddr)
++				       ssize_t size, void *vaddr)
+ {
++	unsigned int pages = ALIGN(size, PAGE_SIZE) >> PAGE_SHIFT;
+ 	if (mem && vaddr >= mem->virt_base && vaddr <
+ 		   (mem->virt_base + ((dma_addr_t)mem->size << PAGE_SHIFT))) {
+ 		int page = (vaddr - mem->virt_base) >> PAGE_SHIFT;
+ 		unsigned long flags;
+ 
+ 		spin_lock_irqsave(&mem->spinlock, flags);
+-		bitmap_release_region(mem->bitmap, page, order);
++		dma_bitmap_release_region(mem->bitmap, page, pages);
+ 		spin_unlock_irqrestore(&mem->spinlock, flags);
+ 		return 1;
+ 	}
+@@ -236,19 +272,21 @@ static int __dma_release_from_coherent(struct dma_coherent_mem *mem,
+  * Returns 1 if we correctly released the memory, or 0 if the caller should
+  * proceed with releasing memory from generic pools.
+  */
+-int dma_release_from_dev_coherent(struct device *dev, int order, void *vaddr)
++int dma_release_from_dev_coherent(struct device *dev, ssize_t size, void *vaddr)
+ {
+ 	struct dma_coherent_mem *mem = dev_get_coherent_memory(dev);
++	
++	dev_dbg(dev, "%s, vaddr: %p, size: %d\n", __func__, vaddr, size);
+ 
+-	return __dma_release_from_coherent(mem, order, vaddr);
++	return __dma_release_from_coherent(mem, size, vaddr);
+ }
+ 
+-int dma_release_from_global_coherent(int order, void *vaddr)
++int dma_release_from_global_coherent(ssize_t size, void *vaddr)
+ {
+ 	if (!dma_coherent_default_memory)
+ 		return 0;
+ 
+-	return __dma_release_from_coherent(dma_coherent_default_memory, order,
++	return __dma_release_from_coherent(dma_coherent_default_memory, size,
+ 			vaddr);
+ }
+ 
+diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
+index 51bb8fa8e..1af3e1dd1 100644
+--- a/kernel/dma/mapping.c
++++ b/kernel/dma/mapping.c
+@@ -449,7 +449,7 @@ void dma_free_attrs(struct device *dev, size_t size, void *cpu_addr,
+ {
+ 	const struct dma_map_ops *ops = get_dma_ops(dev);
+ 
+-	if (dma_release_from_dev_coherent(dev, get_order(size), cpu_addr))
++	if (dma_release_from_dev_coherent(dev, size, cpu_addr))
+ 		return;
+ 	/*
+ 	 * On non-coherent platforms which implement DMA-coherent buffers via
+@@ -517,6 +517,12 @@ void *dma_alloc_noncoherent(struct device *dev, size_t size,
+ 	const struct dma_map_ops *ops = get_dma_ops(dev);
+ 	void *vaddr;
+ 
++
++	/*1. try to alloc from dev coheren area.*/
++	if(dma_alloc_from_dev_coherent(dev, size, dma_handle, &vaddr)) {
++		return (void *)CKSEG0ADDR(vaddr);
++	}
++
+ 	if (!ops || !ops->alloc_noncoherent) {
+ 		struct page *page;
+ 
+@@ -540,6 +546,10 @@ void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
+ {
+ 	const struct dma_map_ops *ops = get_dma_ops(dev);
+ 
++	if(dma_release_from_dev_coherent(dev, size, (void *)CKSEG1ADDR(vaddr))) {
++		return;
++	}
++
+ 	if (!ops || !ops->free_noncoherent) {
+ 		dma_free_pages(dev, size, virt_to_page(vaddr), dma_handle, dir);
+ 		return;
+diff --git a/module_drivers/Kconfig b/module_drivers/Kconfig
+new file mode 100644
+index 000000000..e617b4c83
+--- /dev/null
++++ b/module_drivers/Kconfig
+@@ -0,0 +1,11 @@
++menu "Ingenic device-drivers Configurations"
++
++
++config OUTSIDE_DRIVERS_PATH
++	string
++	default "module_drivers"
++
++source "module_drivers/drivers/Kconfig"
++source "module_drivers/sound/soc/ingenic/Kconfig"
++
++endmenu
+diff --git a/module_drivers/Makefile b/module_drivers/Makefile
+new file mode 100644
+index 000000000..f68d62266
+--- /dev/null
++++ b/module_drivers/Makefile
+@@ -0,0 +1,6 @@
++# Device Tree
++obj-$(CONFIG_BUILTIN_DTB)       := dts/
++
++# Device Drivers
++obj-y += sound/
++obj-y += drivers/
+diff --git a/module_drivers/README.zh b/module_drivers/README.zh
+new file mode 100644
+index 000000000..f8c7256c3
+--- /dev/null
++++ b/module_drivers/README.zh
+@@ -0,0 +1,27 @@
++�正�有的内核驱动，按照�个驱动基于的框架，以内核的目录结构展开，
++独立存放在该module_drivers目录.
++
++Kconfig 定义原则，尽�清晰，贴近SOC本身. �显示SOC支�的控制器驱动.
++
++
++
++1. 如何嵌入到内核��编译
++
++内核��顶层Kconfig添加
++
++```
++config OUTSIDE_DRIVERS
++	string
++	option env="OUTSIDE_DRIVERS"
++	default "module_drivers"
++
++
++source "$OUTSIDE_DRIVERS/Kconfig"
++```
++
++内核Makefile添加
++
++```
++drivers-y	+= module_drivers/
++```
++
+diff --git a/module_drivers/drivers/Kconfig b/module_drivers/drivers/Kconfig
+new file mode 100644
+index 000000000..4cd5b3c17
+--- /dev/null
++++ b/module_drivers/drivers/Kconfig
+@@ -0,0 +1,111 @@
++comment "---- Minimal required Drivers ----"
++menu "[Interrupt] Drivers"
++source "module_drivers/drivers/irqchip/Kconfig"
++endmenu
++
++menu "[OST] clocksoure Drivers"
++source "module_drivers/drivers/clocksource/Kconfig"
++endmenu
++
++menu "[CPM] clk Drivers"
++source "module_drivers/drivers/clk/ingenic-v2/Kconfig"
++endmenu
++
++menu "[GPIO] Pinctroller Drivers"
++source "module_drivers/drivers/pinctrl/Kconfig"
++endmenu
++
++menu "[UART] Drivers"
++source "module_drivers/drivers/tty/serial/Kconfig"
++endmenu
++
++menu "[MSC] (eMMC/SD/SDIO) and Device Drivers"
++source "module_drivers/drivers/mmc/host/Kconfig"
++endmenu
++
++menu "[DMA] Drivers"
++source "module_drivers/drivers/dma/ingenic/Kconfig"
++endmenu
++
++menu "[SFC] (SPI Nand/Nor Flash) Drivers"
++source "module_drivers/drivers/mtd/devices/Kconfig"
++endmenu
++
++menu "[SPI] Master/Slave Drivers"
++source "module_drivers/drivers/spi/Kconfig"
++endmenu
++
++menu "[I2C] Master Drivers"
++source "module_drivers/drivers/i2c/busses/Kconfig"
++endmenu
++
++comment "---- minimal OS requirements. ----"
++
++menu "[LCD] Panel/Touchscreen Drivers"
++
++source "module_drivers/drivers/video/fbdev/ingenic/Kconfig"
++source "module_drivers/drivers/video/logo-ingenic/Kconfig"
++
++menu "Touchscreen Drivers"
++source "module_drivers/drivers/input/touchscreen/Kconfig"
++endmenu
++endmenu
++
++
++
++menu "[GMAC] (ethernet) Drivers"
++source "module_drivers/drivers/net/ethernet/ingenic/Kconfig"
++endmenu
++menu "[WIFI]  Drivers"
++source "module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/Kconfig"
++source "module_drivers/drivers/net/wireless/bcmdhd/Kconfig"
++source "module_drivers/drivers/net/wireless/realtek/rtl8723ds/Kconfig"
++endmenu
++
++menu "[CAN] (ethernet) Drivers"
++#source "module_drivers/drivers/net/can/ingenic/Kconfig"
++endmenu
++
++comment "---- (V4L2) Media Device Drivers ----"
++source "module_drivers/drivers/media/v4l2-core/Kconfig"
++source "module_drivers/drivers/media/platform/Kconfig"
++menu "[Sensors] Camera Sensors"
++source "module_drivers/drivers/media/i2c/Kconfig"
++endmenu
++
++source "module_drivers/drivers/video/ingenic_bscaler/Kconfig"
++source "module_drivers/drivers/video/ingenic-nna/Kconfig"
++source "module_drivers/drivers/video/ingenic_ipu/Kconfig"
++source "module_drivers/drivers/video/ingenic_avpu/Kconfig"
++
++
++
++comment "---- MISC Device Drivers ----"
++source "module_drivers/drivers/misc/Kconfig"
++
++menu "[RANDOM] drivers"
++source "module_drivers/drivers/char/hw_random/Kconfig"
++endmenu
++
++comment "[MFD] Multi Function Device Drivers"
++source "module_drivers/drivers/mfd/Kconfig"
++
++comment "[Power] power and regulator Drivers"
++#source "module_drivers/drivers/power/Kconfig"
++#source "module_drivers/drivers/regulator/Kconfig"
++
++source "module_drivers/drivers/crypto/Kconfig"
++
++
++menu "[WDT] watchdog Drivers"
++source "module_drivers/drivers/watchdog/Kconfig"
++endmenu
++
++
++menu "[PWM] drivers"
++source "module_drivers/drivers/pwm/Kconfig"
++endmenu
++
++menu "[RTC] drivers"
++source "module_drivers/drivers/rtc/Kconfig"
++endmenu
+diff --git a/module_drivers/drivers/Makefile b/module_drivers/drivers/Makefile
+new file mode 100644
+index 000000000..a38e6da10
+--- /dev/null
++++ b/module_drivers/drivers/Makefile
+@@ -0,0 +1,25 @@
++obj-y += char/
++obj-y += clk/
++obj-y += clocksource/
++obj-y += crypto/
++obj-y += dma/
++obj-y += i2c/
++obj-y += video/
++obj-y += media/
++obj-y += mfd/
++obj-y += misc/
++obj-y += mmc/
++obj-y += mtd/
++obj-y += net/
++obj-y += pinctrl/
++obj-y += power/
++obj-y += pwm/
++#obj-y += regulator/
++#obj-y += remoteproc/
++obj-y += spi/
++obj-y += tty/
++obj-y += rtc/
++obj-y += watchdog/
++obj-y += irqchip/
++obj-y += input/
++obj-y += md_export/
+diff --git a/module_drivers/drivers/char/Makefile b/module_drivers/drivers/char/Makefile
+new file mode 100644
+index 000000000..ae402d410
+--- /dev/null
++++ b/module_drivers/drivers/char/Makefile
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_INGENIC_CDBUS)     += ingenic_cdbus.o
++obj-$(CONFIG_HW_RANDOM)         += hw_random/
+diff --git a/module_drivers/drivers/char/hw_random/Kconfig b/module_drivers/drivers/char/hw_random/Kconfig
+new file mode 100644
+index 000000000..c96be1d94
+--- /dev/null
++++ b/module_drivers/drivers/char/hw_random/Kconfig
+@@ -0,0 +1,12 @@
++config HW_RANDOM_INGENIC
++        tristate "[RANDOM] Ingenic HW Random Number Generator support"
++        depends on MIPS
++        help
++         This driver provides kernel-side support for the Random Number
++         Generator hardware found on Ingenic processors.
++
++         To compile this driver as a module, choose M here: the
++         module will be called ingenic-rng.
++
++         If unsure, say N.
++
+diff --git a/module_drivers/drivers/char/hw_random/Makefile b/module_drivers/drivers/char/hw_random/Makefile
+new file mode 100644
+index 000000000..e89c182cc
+--- /dev/null
++++ b/module_drivers/drivers/char/hw_random/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_HW_RANDOM_INGENIC) += ingenic-rng.o
+diff --git a/module_drivers/drivers/char/hw_random/ingenic-rng.c b/module_drivers/drivers/char/hw_random/ingenic-rng.c
+new file mode 100644
+index 000000000..8334de3af
+--- /dev/null
++++ b/module_drivers/drivers/char/hw_random/ingenic-rng.c
+@@ -0,0 +1,284 @@
++
++/*
++ * dtrng driver of Ingenic's SoC X2000
++ *
++ * Copyright (C) 2020 Ingenic Semiconductor Co., Ltd.
++ *      http://www.ingenic.com
++ * Author:      wenshuo.song <wenshuo.song@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/hw_random.h>
++#include <linux/platform_device.h>
++#include <irq.h>
++#include <linux/random.h>
++#include <linux/interrupt.h>
++
++#define TRNG_INT_SWITCH
++#undef  TRNG_INT_SWITCH
++
++#define TRNG_CFG	0x00
++#define TRNG_RANDOMNUM	0x04
++#define TRNG_STATUS	0x08
++
++#define TRNG_CFG_RDY_CLR	(1 << 12)
++#define TRNG_CFG_GEN_EN		(1 << 0)
++#define TRNG_CFG_INT_MASK	(1 << 11)
++
++/*f(clk)=f(pclk)/(div_num+1)*/
++#define	TRNG_CFG_DIV_NUM 0x00
++
++struct ingenic_trng {
++	int irq;
++	struct clk *clk_gate;
++	void __iomem *base;
++	struct hwrng rng;
++};
++
++
++
++static irqreturn_t ingenic_trng_interrupt(int irq, void *dev_id)
++{
++
++	unsigned int trng_cfg;
++	unsigned int trng_randomnum;
++	struct ingenic_trng *trng = (struct ingenic_trng *)(dev_id);
++
++	//TODO?
++
++	trng_randomnum = readl(trng->base + TRNG_RANDOMNUM);
++
++	/* Clear the interupt */
++	trng_cfg = readl(trng->base + TRNG_CFG);
++	trng_cfg |= TRNG_CFG_RDY_CLR;
++	writel(trng_cfg,trng->base + TRNG_CFG);
++	trng_cfg &= ~TRNG_CFG_RDY_CLR;
++	writel(trng_cfg,trng->base + TRNG_CFG);
++
++	return IRQ_HANDLED;
++}
++
++static void ingenic_trng_enable(struct hwrng *rng)
++{
++	unsigned int trng_cfg;
++	struct ingenic_trng *trng = container_of(rng, struct ingenic_trng, rng);
++
++	trng_cfg = readl(trng->base + TRNG_CFG);
++	trng_cfg |= (1 << 0);
++	writel(trng_cfg, trng->base + TRNG_CFG);
++
++}
++
++static void ingenic_trng_disable(struct hwrng *rng)
++{
++	unsigned int trng_cfg;
++	struct ingenic_trng *trng = container_of(rng, struct ingenic_trng, rng);
++
++	trng_cfg = readl(trng->base + TRNG_CFG);
++	trng_cfg &= ~(1 << 0);
++	writel(trng_cfg, trng->base + TRNG_CFG);
++
++}
++
++static int ingenic_trng_init(struct hwrng *rng)
++{
++
++	unsigned int trng_cfg;
++	struct ingenic_trng *trng = container_of(rng, struct ingenic_trng, rng);
++
++	trng_cfg = readl(trng->base + TRNG_CFG);
++	trng_cfg |= (1 << 0);
++	writel(trng_cfg, trng->base + TRNG_CFG);
++
++	return 0;
++}
++
++static void ingenic_trng_cleanup(struct hwrng *rng)
++{
++	unsigned int trng_cfg;
++	struct ingenic_trng *trng = container_of(rng, struct ingenic_trng, rng);
++
++	trng_cfg = readl(trng->base + TRNG_CFG);
++	trng_cfg &= ~TRNG_CFG_GEN_EN;
++	writel(trng_cfg, trng->base + TRNG_CFG);
++}
++
++static int ingenic_trng_read(struct hwrng *rng, void *buf, size_t max,
++		bool wait)
++{
++
++
++	struct ingenic_trng *trng = container_of(rng, struct ingenic_trng, rng);
++	unsigned int trng_cfg;
++	u32 val,tmp_data;
++	u32 *data = buf;
++	int ret;
++
++	ingenic_trng_enable(rng);
++
++	/* data ready? */
++	if (readl(trng->base + TRNG_STATUS) & 1) {
++		get_random_bytes(&val, sizeof(u32));
++		tmp_data = readl(trng->base + TRNG_RANDOMNUM);
++		tmp_data ^= val;
++		*data = tmp_data;
++
++		/* Clear the ramdom_rdy */
++		trng_cfg = readl(trng->base + TRNG_CFG);
++		trng_cfg |= TRNG_CFG_RDY_CLR;
++		writel(trng_cfg,trng->base + TRNG_CFG);
++		trng_cfg &= ~TRNG_CFG_RDY_CLR;
++		writel(trng_cfg,trng->base + TRNG_CFG);
++
++		ret = 4;
++	} else
++		ret = 0;
++
++	ingenic_trng_disable(rng);
++
++	return ret;
++}
++
++static int ingenic_trng_probe(struct platform_device *pdev)
++{
++	struct ingenic_trng *trng;
++	struct resource *res;
++	int ret;
++
++	trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL);
++	if (!trng)
++		return -ENOMEM;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	trng->base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(trng->base))
++		return PTR_ERR(trng->base);
++
++	trng->irq = platform_get_irq(pdev, 0);
++	if(trng->irq < 0){
++		dev_err(&pdev->dev, "Cannot get %d  IORESOURCE_IRQ\n",trng->irq);
++		return  -ENOENT;
++	}
++
++	trng->clk_gate = devm_clk_get(&pdev->dev, "gate_dtrng");
++	if (IS_ERR(trng->clk_gate))
++		return PTR_ERR(trng->clk_gate);
++
++	ret = clk_prepare_enable(trng->clk_gate);
++	if (ret)
++		return ret;
++
++
++	trng->rng.name = pdev->name;
++	trng->rng.init = ingenic_trng_init;
++	trng->rng.cleanup = ingenic_trng_cleanup;
++	trng->rng.read = ingenic_trng_read;
++
++#ifdef TRNG_INT_SWITCH
++	writel(readl(TRNG_CFG) & ~TRNG_CFG_INT_MASK, TRNG_CFG);
++	ret = request_irq(trng->irq,ingenic_trng_interrupt,
++			IRQF_SHARED | IRQF_TRIGGER_LOW,"trng-interrupt",trng);
++	if (ret) {
++		dev_err(&pdev->dev, "request_irq failed !! %d-\n",trng->irq);
++		goto err_register;
++	}
++#endif
++	ret = hwrng_register(&trng->rng);
++	if (ret)
++		goto err_register;
++
++	platform_set_drvdata(pdev, trng);
++
++	ingenic_trng_disable(&trng->rng);
++
++	dev_info(&pdev->dev, "ingenic HW dtrng Probe success!\n");
++	return 0;
++
++err_register:
++	clk_disable(trng->clk_gate);
++	return ret;
++}
++
++static int ingenic_trng_remove(struct platform_device *pdev)
++{
++	struct ingenic_trng *trng = platform_get_drvdata(pdev);
++	unsigned int trng_cfg;
++
++	hwrng_unregister(&trng->rng);
++
++	trng_cfg = readl(trng->base + TRNG_CFG);
++	trng_cfg &= ~(1 << 0);
++	writel(trng_cfg, trng->base + TRNG_CFG);
++
++	clk_disable_unprepare(trng->clk_gate);
++
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int ingenic_trng_suspend(struct device *dev)
++{
++	struct ingenic_trng *trng = dev_get_drvdata(dev);
++
++	clk_disable_unprepare(trng->clk_gate);
++
++	return 0;
++}
++
++static int ingenic_trng_resume(struct device *dev)
++{
++	struct ingenic_trng *trng = dev_get_drvdata(dev);
++
++	return clk_prepare_enable(trng->clk_gate);
++}
++
++static const struct dev_pm_ops ingenic_trng_pm_ops = {
++	.suspend	= ingenic_trng_suspend,
++	.resume		= ingenic_trng_resume,
++};
++#endif /* CONFIG_PM */
++
++static const struct of_device_id ingenic_trng_dt_ids[] = {
++	{ .compatible = "ingenic,dtrng" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, ingenic_trng_dt_ids);
++
++static struct platform_driver ingenic_trng_driver = {
++	.probe		= ingenic_trng_probe,
++	.remove		= ingenic_trng_remove,
++	.driver		= {
++		.name	= "ingenic-trng",
++#ifdef CONFIG_PM
++		.pm	= &ingenic_trng_pm_ops,
++#endif /* CONFIG_PM */
++		.of_match_table = ingenic_trng_dt_ids,
++	},
++};
++
++module_platform_driver(ingenic_trng_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("wenshuo.song <wenshuo.song@ingenic.com>");
++MODULE_DESCRIPTION("ingenic true random number generator driver");
+diff --git a/module_drivers/drivers/char/ingenic_cdbus.c b/module_drivers/drivers/char/ingenic_cdbus.c
+new file mode 100644
+index 000000000..ba51c09df
+--- /dev/null
++++ b/module_drivers/drivers/char/ingenic_cdbus.c
+@@ -0,0 +1,733 @@
++/* linux/drivers/char/jz_cdbus.c
++ *
++ * Ingenic cdbus driver, use kernel char device framework
++ *
++ * Copyright (c) 2021 Ingenic
++ * Author:zhangxu <xu.zhang@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/kernel.h>
++#include <linux/fs.h>
++#include <linux/errno.h>
++#include <linux/types.h>
++#include <linux/fcntl.h>
++#include <linux/cdev.h>
++#include <linux/device.h>
++#include <linux/sched.h>
++#include <asm/uaccess.h>
++#include <linux/gpio.h>
++#include <linux/spinlock.h>
++
++#define VERSION         0x00
++#define SETTING         0x04
++#define IDLE_WAIT_LEN   0x08
++#define TX_PERMIT_LEN   0x0c
++#define MAX_IDLE_LEN    0x10
++#define TX_PRE_LEN      0x14
++#define FILTER          0x18
++#define DIV_LS          0x1c
++#define DIV_HS          0x20
++#define INT_FLAG        0x24
++#define INT_MASK        0x28
++#define RX_CTRL         0x2c
++#define TX_CTRL         0x30
++#define RX_PAGE_FLAG    0x34
++#define FILTER_M        0x38
++#define TX_FIFO         0x200
++#define RX_FIFO         0x500
++#define SELFTEST        0x900
++
++/* SETTING */
++#define BIT_SETTING_TX_PUSH_PULL    (1 << 0)
++#define BIT_SETTING_TX_INVERT       (1 << 1)
++#define BIT_SETTING_USER_CRC        (1 << 2)
++#define BIT_SETTING_NO_DROP         (1 << 3)
++#define BIT_SETTING_ARBITRATION     (1 << 4)
++#define BIT_SETTING_BREAK_SYNC      (1 << 5)
++#define BIT_SETTING_FULL_DUPLEX     (1 << 6)
++
++/* INT_MASK */
++#define BIT_MASK_BUS_IDLE           (1 << 0)
++#define BIT_MASK_RX_PENDING         (1 << 1)
++#define BIT_MASK_RX_BREAK           (1 << 2)
++//#define BIT_MASK_RX_LOST            (1 << 3)
++#define BIT_MASK_RX_ERROR           (1 << 4)
++#define BIT_MASK_TX_PENDING         (1 << 5)
++#define BIT_MASK_TX_CD              (1 << 6)
++#define BIT_MASK_TX_ERROR           (1 << 7)
++
++/* INT_FLAG */
++#define BIT_FLAG_BUS_IDLE           (1 << 0)
++#define BIT_FLAG_RX_PENDING         (1 << 1)
++#define BIT_FLAG_RX_BREAK           (1 << 2)
++//#define BIT_FLAG_RX_LOST            (1 << 3)
++#define BIT_FLAG_RX_ERROR           (1 << 4)
++#define BIT_FLAG_TX_BUF_CLEAN       (1 << 5)
++#define BIT_FLAG_TX_CD              (1 << 6)
++#define BIT_FLAG_TX_ERROR           (1 << 7)
++
++/* TX_CTRL */
++#define BIT_TX_RST_POINTER          (1 << 0)
++#define BIT_TX_START                (1 << 1)
++#define BIT_TX_CLR_CD               (1 << 2)
++#define BIT_TX_CLR_ERROR            (1 << 3)
++#define BIT_TX_ABORT                (1 << 4)
++#define BIT_TX_SEND_BREAK           (1 << 5)
++
++/* RX_CTRL */
++#define BIT_RX_RST_POINTER          (1 << 0)
++#define BIT_RX_SWITCH_PAGE          (1 << 1)
++#define BIT_RX_CLR_LOST             (1 << 2)
++#define BIT_RX_CLR_ERROR            (1 << 3)
++#define BIT_RX_RST                  (1 << 4)
++#define BIT_RX_CLR_BREAK            (1 << 5)
++
++
++#define CDBUS_BUF_SIZE (4 * 6)
++#define CDBUS_KERNEL_BUF_SIZE 500
++
++struct cdbus_kernel_buf_info {
++	unsigned char data[CDBUS_KERNEL_BUF_SIZE][256];
++	unsigned int wr_ptr;
++	unsigned int rd_ptr;
++};
++
++struct cdbus_buf_info {
++	unsigned char data[CDBUS_BUF_SIZE][256];
++	unsigned int wr_ptr;
++	unsigned int rd_ptr;
++};
++
++struct cdbus_info {
++	unsigned int tx_flag;
++	unsigned int rx_flag;
++	unsigned int rx_buf_full;
++	unsigned int rx_underrun;
++	unsigned int tx_cd_flag;
++	unsigned int tx_err_flag;
++	unsigned int rx_err_flag;
++	unsigned int rx_break_flag;
++	unsigned int rx_page;
++	struct cdbus_buf_info tx_buf;
++	struct cdbus_buf_info rx_buf;
++};
++
++struct jz_cdbus {
++	int major;
++	int minor;
++	dev_t dev_num;
++	int nr_devs;
++
++	struct class *class;
++	struct cdev cdev;
++	struct device *dev;
++
++	void __iomem *iomem;
++	struct completion done_tx;
++	struct completion done_rx;
++	struct timer_list timer;
++
++	struct cdbus_info *dev_info;
++	struct cdbus_buf_info *tx_buf_info;
++	struct cdbus_buf_info *rx_buf_info;
++
++	struct cdbus_kernel_buf_info *rx_buf;
++};
++
++enum cdbus_ioctl_cmd {
++	CDBUS_A_MODE,
++	CDBUS_BS_MODE,
++	CDBUS_HAIF_FULL_DUPLEX_MODE,
++	CDBUS_FULL_DUPLEX_MODE,
++	CDBUS_SET_LOW_RATE,
++	CDBUS_SET_HIGH_RATE,
++	CDBUS_WRITE_FILTER,
++	CDBUS_WRITE_FILTERM,
++	CDBUS_ENABLE_LOOPBACK,
++};
++
++static struct jz_cdbus *global_cdbus;
++
++static unsigned char *cdbus_kernel_buf_get_wr_ptr(struct cdbus_kernel_buf_info *buf)
++{
++	return buf->data[buf->wr_ptr % CDBUS_KERNEL_BUF_SIZE];
++}
++
++static unsigned char *cdbus_kernel_buf_get_rd_ptr(struct cdbus_kernel_buf_info *buf)
++{
++	return buf->data[buf->rd_ptr % CDBUS_KERNEL_BUF_SIZE];
++}
++
++static int cdbus_kernel_buf_is_full(struct cdbus_kernel_buf_info *buf)
++{
++	return buf->wr_ptr - buf->rd_ptr == CDBUS_KERNEL_BUF_SIZE;
++}
++
++static int cdbus_kernel_buf_is_empty(struct cdbus_kernel_buf_info *buf)
++{
++	return buf->wr_ptr == buf->rd_ptr;
++}
++
++static unsigned char *cdbus_buf_get_wr_ptr(struct cdbus_buf_info *buf)
++{
++	return buf->data[buf->wr_ptr % CDBUS_BUF_SIZE];
++}
++
++static unsigned char *cdbus_buf_get_rd_ptr(struct cdbus_buf_info *buf)
++{
++	return buf->data[buf->rd_ptr % CDBUS_BUF_SIZE];
++}
++
++static int cdbus_buf_is_full(struct cdbus_buf_info *buf)
++{
++	return buf->wr_ptr - buf->rd_ptr == CDBUS_BUF_SIZE;
++}
++
++static int cdbus_buf_is_empty(struct cdbus_buf_info *buf)
++{
++	return buf->wr_ptr == buf->rd_ptr;
++}
++
++static int cdbus_buf_get_valid_len(struct cdbus_buf_info *buf)
++{
++	return (buf->wr_ptr - buf->rd_ptr);
++}
++
++static void ingenic_cdbus_reset_rx_block(struct jz_cdbus *cdbus)
++{
++	writel(1 << 4, cdbus->iomem + RX_CTRL);
++	cdbus->dev_info->rx_page = 0;
++}
++
++
++static unsigned int ingenic_cdbus_recv_frame(struct jz_cdbus *cdbus, unsigned char *buf)
++{
++	unsigned int frm_len, data_len;
++	unsigned char *rx_buf = cdbus_buf_get_rd_ptr(cdbus->rx_buf_info);
++
++	data_len = rx_buf[2] & 0xff;
++	frm_len = data_len + 3;
++	memcpy(buf, rx_buf, frm_len);
++
++	cdbus->rx_buf_info->rd_ptr++;
++
++	return frm_len;
++}
++
++static int ingenic_cdbus_send_frame(struct jz_cdbus *cdbus, unsigned char *buf, int frm_len)
++{
++	unsigned char *tx_buf = cdbus_buf_get_wr_ptr(cdbus->tx_buf_info);
++
++	memcpy(tx_buf, buf, frm_len);
++	cdbus->tx_buf_info->wr_ptr++;
++
++	if (cdbus_buf_get_valid_len(cdbus->tx_buf_info) == 1) {
++		writel(readl(cdbus->iomem + INT_MASK) | (1 << 5), cdbus->iomem + INT_MASK);
++	}
++
++	return 0;
++}
++
++static int ingenic_cdbus_send_frame_to_user(struct jz_cdbus *cdbus, unsigned char **buf)
++{
++	unsigned int frm_len, data_len;
++	unsigned char *rx_buf = cdbus_kernel_buf_get_rd_ptr(cdbus->rx_buf);
++
++	data_len = rx_buf[2] & 0xff;
++	frm_len = data_len + 3;
++
++	*buf = rx_buf;
++	cdbus->rx_buf->rd_ptr++;
++
++	//printk("%s():%d >>> ##### read buffer >>> wr_ptr = %d, rd_ptr = %d\n", __func__, __LINE__, cdbus->rx_buf->wr_ptr, cdbus->rx_buf->rd_ptr);
++	return frm_len;
++}
++
++static unsigned int ingenic_cdbus_recv_frame_from_mcu(struct jz_cdbus *cdbus)
++{
++	unsigned char *rx_buf;
++	unsigned int frm_len;
++
++	while (!cdbus_buf_is_empty(cdbus->rx_buf_info)) {
++		rx_buf = cdbus_kernel_buf_get_wr_ptr(cdbus->rx_buf);
++		frm_len = ingenic_cdbus_recv_frame(cdbus, rx_buf);
++		cdbus->rx_buf->wr_ptr++;
++		//printk("%s():%d >>> ##### write buffer >>> wr_ptr = %d, rd_ptr = %d\n", __func__, __LINE__, cdbus->rx_buf->wr_ptr, cdbus->rx_buf->rd_ptr);
++	}
++
++	return 0;
++}
++
++extern void mygpio_cdbus_output(unsigned gpio, int value);
++int ingenic_cdbus_irq_handler(void)
++{
++	struct jz_cdbus *cdbus = global_cdbus;
++
++	/* Receive */
++	if (cdbus->dev_info->rx_flag == 1) {
++#if 1
++		if (!cdbus_kernel_buf_is_full(cdbus->rx_buf)) {
++	//		printk("%s:%d >>> kernel buffer is not full!\n", __func__, __LINE__);
++			ingenic_cdbus_recv_frame_from_mcu(cdbus);
++			//complete(&cdbus->done_rx);
++		} else {
++			cdbus->rx_buf->rd_ptr = 0;
++			cdbus->rx_buf->wr_ptr = 0;
++			printk("%s:%d >>> kernel buffer is full!\n", __func__, __LINE__);
++		}
++#endif
++		cdbus->dev_info->rx_flag = 0;
++	}
++
++	/* Rxfifo underrun */
++	if (cdbus->dev_info->rx_underrun != 0) {
++		//printk("Rxfifo Underrun:%d: wr_ptr = %d, rd_ptr = %d, rx_underrun = %d\n", __LINE__, cdbus->rx_buf_info->wr_ptr, cdbus->rx_buf_info->rd_ptr, cdbus->dev_info->rx_underrun);
++		printk("ru%d %d\n", cdbus->rx_buf_info->wr_ptr, cdbus->rx_buf_info->rd_ptr);
++		cdbus->dev_info->rx_underrun = 0;
++	}
++
++	/* Rxfifo full */
++	if (cdbus->dev_info->rx_buf_full != 0) {
++		//printk("Rxfifo Full:%d: wr_ptr = %d, rd_ptr = %d, rx_buf_full = %d\n", __LINE__, cdbus->rx_buf_info->wr_ptr, cdbus->rx_buf_info->rd_ptr, cdbus->dev_info->rx_buf_full);
++		printk("rf%d %d\n", cdbus->rx_buf_info->wr_ptr, cdbus->rx_buf_info->rd_ptr);
++		cdbus->dev_info->rx_buf_full = 0;
++		cdbus->rx_buf_info->rd_ptr = 0;
++		cdbus->rx_buf_info->wr_ptr = 0;
++	}
++
++#if 1
++	/* Send */
++	if (cdbus->dev_info->tx_flag == 1) {
++		if (!cdbus_buf_is_full(cdbus->tx_buf_info)) {
++	//		printk("########%s:%d >>> tx_buf is not full\n", __func__, __LINE__);
++			complete(&cdbus->done_tx);
++		}
++
++		cdbus->dev_info->tx_flag = 0;
++	}
++#endif
++
++	/* Rx break */
++	if (cdbus->dev_info->rx_break_flag == 1) {
++		dev_err(cdbus->dev, "%s():%d >>> Receive break character\n", __func__, __LINE__);
++		cdbus->dev_info->rx_break_flag = 0;
++	}
++
++	/* Rx error */
++	if (cdbus->dev_info->rx_err_flag == 1) {
++		dev_err(cdbus->dev, "%s():%d >>> RX error: frame broken\n", __func__, __LINE__);
++		cdbus->dev_info->rx_err_flag = 0;
++	}
++
++	/* Tx collision detected */
++	if (cdbus->dev_info->tx_cd_flag == 1) {
++		dev_err(cdbus->dev, "%s():%d >>> TX collision detected\n", __func__, __LINE__);
++		cdbus->dev_info->tx_cd_flag = 0;
++	}
++
++	/* Tx error */
++	if (cdbus->dev_info->tx_err_flag == 1) {
++		dev_err(cdbus->dev, "%s():%d >>> TX error: tx is 0, but rx is 1\n", __func__, __LINE__);
++		cdbus->dev_info->tx_err_flag = 0;
++	}
++
++	return 0;
++}
++
++static void ingenic_cdbus_timer_handler(unsigned long data)
++{
++	struct jz_cdbus *cdbus = (struct jz_cdbus *)data;
++
++	if (!cdbus_kernel_buf_is_empty(cdbus->rx_buf)) {
++		complete(&cdbus->done_rx);
++	} else {
++		printk("%s:%d >>> kernel buffer is empty\n", __func__, __LINE__);
++	}
++
++	//cdbus->timer.expires = jiffies + msecs_to_jiffies(50);
++	cdbus->timer.expires = jiffies + usecs_to_jiffies(100);
++	add_timer(&cdbus->timer);
++}
++
++//#define CDBUS_CPU_BREAK_SYNC_MODE
++/*
++ * Init cdbus controler
++ */
++static void jz_cdbus_hw_init(struct jz_cdbus *cdbus)
++{
++	/* Enable tx push-pull output */
++#ifndef CDBUS_CPU_BREAK_SYNC_MODE
++	printk("%s:%d >>> mode CDBUS-A mode\n", __func__, __LINE__);
++	writel(BIT_SETTING_ARBITRATION | BIT_SETTING_TX_PUSH_PULL, cdbus->iomem + SETTING);
++#else
++	printk("%s:%d >>> mode CDBUS-BS mode\n", __func__, __LINE__);
++	writel(BIT_SETTING_BREAK_SYNC | BIT_SETTING_TX_PUSH_PULL, cdbus->iomem + SETTING);
++#endif
++
++	/* Set baudrates */
++	// CDBUS dve_clk = 150Mhz
++#ifndef CDBUS_CPU_BREAK_SYNC_MODE
++	/* a mode */
++	printk("%s:%d >>> clock CDBUS-A mode\n", __func__, __LINE__);
++	writel(149, cdbus->iomem + DIV_LS);	// low_speed rate = 1Mhz
++	writel(14, cdbus->iomem + DIV_HS);	// high_speed rate = 10Mhz
++#else
++	/* bs mode */
++	printk("%s:%d >>> clock CDBUS-BS mode\n", __func__, __LINE__);
++	writel(14, cdbus->iomem + DIV_LS);	// low_speed rate = 50Mhz
++	writel(14, cdbus->iomem + DIV_HS);	// high_speed rate = 50Mhz
++#endif
++
++	/* Clean RX buffer */
++	//writel(BIT_RX_RST_POINTER, cdbus->iomem + RX_CTRL);
++
++	/* Enable interrupts */
++#ifndef CDBUS_CPU_BREAK_SYNC_MODE
++	printk("%s:%d >>> interrupt CDBUS-A mode\n", __func__, __LINE__);
++	writel(BIT_MASK_TX_ERROR | BIT_MASK_TX_CD | BIT_MASK_RX_ERROR |
++		BIT_MASK_RX_BREAK | BIT_MASK_RX_PENDING, cdbus->iomem + INT_MASK);
++#else
++	printk("%s:%d >>> interrupt CDBUS-BS mode\n", __func__, __LINE__);
++	writel(BIT_MASK_TX_ERROR | BIT_MASK_TX_CD | BIT_MASK_RX_ERROR |
++		BIT_MASK_RX_PENDING, cdbus->iomem + INT_MASK);
++#endif
++
++	/* Set time length */
++	writel(1, cdbus->iomem + TX_PERMIT_LEN);
++	writel(1, cdbus->iomem + MAX_IDLE_LEN);
++	writel(1, cdbus->iomem + IDLE_WAIT_LEN);
++
++	/* Set local address and Multicast filter */
++	writel(0x0, cdbus->iomem + FILTER);
++	writel(0x0, cdbus->iomem + FILTER_M);
++}
++
++static int jz_cdbus_open(struct inode *inode, struct file *filp)
++{
++	struct jz_cdbus *cdbus;
++	unsigned int mcu_ddr = *(volatile unsigned int *)(0xb342201c);
++
++	cdbus = container_of(inode->i_cdev, struct jz_cdbus, cdev);
++	if (!cdbus)
++		return -EINVAL;
++	filp->private_data = cdbus;
++
++#if 1
++	mcu_ddr = ((mcu_ddr & 0xffff) + 0x2000) | 0xb3420000;
++	cdbus->dev_info = (struct cdbus_info *)mcu_ddr;
++
++	cdbus->tx_buf_info = &cdbus->dev_info->tx_buf;
++	cdbus->rx_buf_info = &cdbus->dev_info->rx_buf;
++	cdbus->rx_buf_info->rd_ptr = 0;
++	cdbus->rx_buf_info->wr_ptr = 0;
++	cdbus->tx_buf_info->rd_ptr = 0;
++	cdbus->tx_buf_info->wr_ptr = 0;
++	cdbus->dev_info->rx_underrun = 0;
++	cdbus->dev_info->rx_buf_full = 0;
++	cdbus->dev_info->tx_cd_flag = 0;
++	cdbus->dev_info->tx_err_flag = 0;
++	cdbus->dev_info->rx_err_flag = 0;
++	cdbus->dev_info->rx_break_flag = 0;
++	cdbus->dev_info->rx_page = 0;
++
++	//cdbus->rx_buf = devm_kzalloc(cdbus->dev, sizeof(struct cdbus_kernel_buf_info), GFP_KERNEL);
++	cdbus->rx_buf = kzalloc(sizeof(struct cdbus_kernel_buf_info), GFP_KERNEL);
++	if (!cdbus->rx_buf) {
++		printk("%s:%d >>> rx_buf kzalloc failed!\n", __func__, __LINE__);
++		return -ENOMEM;
++	}
++
++
++	cdbus->rx_buf->rd_ptr = 0;
++	cdbus->rx_buf->wr_ptr = 0;
++#endif
++
++	jz_cdbus_hw_init(cdbus);
++
++	return 0;
++}
++
++int cdbus_debug = 0;
++static int jz_cdbus_read(struct file *filp, char *user_buf, size_t count, loff_t *f_pos)
++{
++	struct jz_cdbus *cdbus = filp->private_data;
++	//unsigned char rx_buf[256];
++	unsigned char *rx_buf;
++	int frm_len;
++
++	if (!cdbus_debug) {
++		printk("cdbus debug\n");
++		cdbus_debug = 1;
++	}
++
++#if 1
++	if (cdbus_kernel_buf_is_empty(cdbus->rx_buf)) {
++		//printk("%s:%d >>> kernel buffer is empty\n", __func__, __LINE__);
++		return -1;
++	}
++#endif
++#if 0
++	wait_for_completion_interruptible(&cdbus->done_rx);
++#endif
++	frm_len = ingenic_cdbus_send_frame_to_user(cdbus, &rx_buf);
++	copy_to_user(user_buf, rx_buf, frm_len);
++
++	return frm_len;
++}
++
++static int jz_cdbus_write(struct file *filp, const char *user_buf, size_t count, loff_t *f_pos)
++{
++	struct jz_cdbus *cdbus = filp->private_data;
++	unsigned char tx_buf[256];
++
++	copy_from_user(tx_buf, user_buf, count);
++	ingenic_cdbus_send_frame(cdbus, tx_buf, count);
++#if 1
++	wait_for_completion_interruptible(&cdbus->done_tx);
++#endif
++
++	return count;
++}
++
++static long jz_cdbus_ioctl(struct file *filp, unsigned int cmd, unsigned long args)
++{
++	int ret = 0;
++	struct jz_cdbus *cdbus = filp->private_data;
++
++	switch (cmd) {
++	case CDBUS_A_MODE:
++		writel(readl(cdbus->iomem + SETTING) & ~(0x7 << 4), cdbus->iomem + SETTING);
++		writel(readl(cdbus->iomem + SETTING) | BIT_SETTING_ARBITRATION, cdbus->iomem + SETTING);
++		break;
++	case CDBUS_BS_MODE:
++		writel(readl(cdbus->iomem + SETTING) & ~(0x7 << 4), cdbus->iomem + SETTING);
++		writel(readl(cdbus->iomem + SETTING) | BIT_SETTING_BREAK_SYNC, cdbus->iomem + SETTING);
++		break;
++	case CDBUS_HAIF_FULL_DUPLEX_MODE:
++		writel(readl(cdbus->iomem + SETTING) & ~(0x7 << 4), cdbus->iomem + SETTING);
++		break;
++	case CDBUS_FULL_DUPLEX_MODE:
++		writel(readl(cdbus->iomem + SETTING) & ~(0x7 << 4), cdbus->iomem + SETTING);
++		writel(readl(cdbus->iomem + SETTING) | BIT_SETTING_FULL_DUPLEX, cdbus->iomem + SETTING);
++		break;
++	case CDBUS_SET_LOW_RATE:
++		writel(150 / args - 1, cdbus->iomem + DIV_LS);
++		break;
++	case CDBUS_SET_HIGH_RATE:
++		writel(150 / args - 1, cdbus->iomem + DIV_HS);
++		break;
++	case CDBUS_WRITE_FILTER:
++		writel(args, cdbus->iomem + FILTER);
++		break;
++	case CDBUS_WRITE_FILTERM:
++		writel(args, cdbus->iomem + FILTER_M);
++		break;
++	case CDBUS_ENABLE_LOOPBACK:
++		dev_info(cdbus->dev, "Loopback Mode\n");
++		writel(0x1, cdbus->iomem + SELFTEST);
++		break;
++	default:
++		break;
++	}
++
++	return ret;
++}
++
++static int jz_cdbus_close(struct inode *inode, struct file *filp)
++{
++	struct jz_cdbus *cdbus = filp->private_data;
++
++	/* Disable interrupts */
++	writel(0x0, cdbus->iomem + INT_MASK);
++	kfree(cdbus->rx_buf);
++
++	return 0;
++}
++
++static struct file_operations jz_cdbus_ops = {
++	.owner = THIS_MODULE,
++	.write = jz_cdbus_write,
++	.read = jz_cdbus_read,
++	.open = jz_cdbus_open,
++	.release = jz_cdbus_close,
++	.unlocked_ioctl = jz_cdbus_ioctl,
++};
++
++static int jz_cdbus_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	struct jz_cdbus *cdbus;
++	struct resource *res;
++	dev_t devno;
++	struct clk *clk_cgu;
++	struct clk *clk_gate;
++	unsigned int cdbus_clk_freq = 150000000;
++
++	cdbus = devm_kzalloc(&pdev->dev, sizeof(struct jz_cdbus), GFP_KERNEL);
++	if (!cdbus)
++		return -ENOMEM;
++
++	global_cdbus = cdbus;
++
++	cdbus->dev = &pdev->dev;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res) {
++		dev_err(&pdev->dev, "cannot get IORESOURCE_MEM\n");
++		return -ENODEV;
++	}
++
++	cdbus->iomem = devm_ioremap(cdbus->dev, res->start, res->end - res->start + 1);
++	if (!cdbus->iomem) {
++		dev_err(&pdev->dev, "ioremap failed!\n");
++		return -ENOMEM;
++	}
++
++	platform_set_drvdata(pdev, cdbus);
++
++	init_completion(&cdbus->done_tx);
++	init_completion(&cdbus->done_rx);
++
++	clk_gate = devm_clk_get(&pdev->dev, "gate_cdbus");
++	if (IS_ERR(clk_gate)) {
++		dev_err(&pdev->dev, "%s Cannot get clock: %s\n", __func__, "gate_cdbus");
++		goto __err0;
++	}
++
++	clk_cgu = devm_clk_get(&pdev->dev, "div_cdbus");
++	if (IS_ERR(clk_cgu)) {
++		dev_err(&pdev->dev, "%s Cannot get clock: %s\n", __func__, "div_cdbus");
++		goto __err0;
++	}
++
++	clk_set_parent(clk_get(NULL, "mux_cdbus"), clk_get(NULL, "epll"));
++
++	if (clk_set_rate(clk_cgu, cdbus_clk_freq)) {
++		dev_err(&pdev->dev, "Set cgu_cdbus clk rate faild\n");
++		goto __err0;
++	}
++
++	if ((ret = clk_prepare_enable(clk_gate)) < 0) {
++		dev_err(&pdev->dev, "Enable gate_cdbus clk failed\n");
++		goto __err0;
++	}
++
++	//printk("############# cdbus clock: clk_get_clk = %ld, set clk = %d\n", clk_get_rate(clk_cgu), cdbus_clk_freq);
++
++	cdbus->minor = 0;
++	cdbus->nr_devs = 1;
++	ret = alloc_chrdev_region(&devno, cdbus->minor, cdbus->nr_devs, "jz-cdbus");
++	if (ret) {
++		dev_err(cdbus->dev, "alloc chrdev failed\n");
++		return ret;
++	}
++	cdbus->major = MAJOR(devno);
++	cdbus->dev_num = MKDEV(cdbus->major, cdbus->minor);
++	dev_dbg(&pdev->dev, "%s():%d >>> cdbus->major = %d, cdbus->minor = %d, cdbus->dev_num = %x\n",
++			__func__, __LINE__, cdbus->major, cdbus->minor, cdbus->dev_num);
++
++	cdev_init(&cdbus->cdev, &jz_cdbus_ops);
++	cdbus->cdev.owner = THIS_MODULE;
++	cdev_add(&cdbus->cdev, cdbus->dev_num, 1);
++	if (ret) {
++		dev_err(cdbus->dev, "cdev_add failed\n");
++		goto __err1;
++	}
++
++	cdbus->class = class_create(THIS_MODULE, "jz-cdbus");
++	if (IS_ERR(cdbus->class)) {
++		dev_err(cdbus->dev, "class_create failed\n");
++		ret = PTR_ERR(cdbus->class);
++		goto __err2;
++	}
++
++	cdbus->dev = device_create(cdbus->class, NULL, cdbus->dev_num, NULL, "cdbus");
++	if (IS_ERR(cdbus->dev)) {
++		dev_err(cdbus->dev, "device_create failed\n");
++		ret = PTR_ERR(cdbus->dev);
++		goto __err3;
++	}
++
++	init_timer(&cdbus->timer);
++	cdbus->timer.expires = jiffies + msecs_to_jiffies(100);
++	cdbus->timer.function = ingenic_cdbus_timer_handler;
++	cdbus->timer.data = (unsigned long)cdbus;
++
++	dev_info(cdbus->dev, "Ingenic cdbus driver init successfully!\n");
++
++	return 0;
++
++__err3:
++	class_destroy(cdbus->class);
++__err2:
++	cdev_del(&cdbus->cdev);
++__err1:
++	unregister_chrdev_region(cdbus->dev_num, cdbus->nr_devs);
++__err0:
++	return ret;
++}
++
++static int jz_cdbus_remove(struct platform_device *pdev)
++{
++	struct jz_cdbus *cdbus = platform_get_drvdata(pdev);
++
++	device_destroy(cdbus->class, cdbus->dev_num);
++	class_destroy(cdbus->class);
++	cdev_del(&cdbus->cdev);
++	unregister_chrdev_region(cdbus->dev_num, cdbus->nr_devs);
++
++	return 0;
++}
++
++static const struct of_device_id ingenic_cdbus_match[] = {
++	{ .compatible = "ingenic,x1600-cdbus", },
++	{}
++};
++MODULE_DEVICE_TABLE(of, ingenic_cdbus_match);
++
++static struct platform_driver jz_cdbus_driver = {
++	.probe          = jz_cdbus_probe,
++	.remove         = jz_cdbus_remove,
++	.driver		= {
++		.name	= "jz-cdbus",
++		.owner	= THIS_MODULE,
++		.of_match_table	= ingenic_cdbus_match,
++	},
++};
++
++static int __init jz_cdbus_init(void)
++{
++	int ret;
++
++	ret = platform_driver_register(&jz_cdbus_driver);
++	if (ret)
++		platform_driver_unregister(&jz_cdbus_driver);
++
++	return ret;
++}
++
++static void __exit jz_cdbus_exit(void)
++{
++	platform_driver_unregister(&jz_cdbus_driver);
++}
++
++module_init(jz_cdbus_init);
++module_exit(jz_cdbus_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Ingenic cdbus driver");
++MODULE_AUTHOR("xu.zhang@ingenic.com");
++
+diff --git a/module_drivers/drivers/clk/Makefile b/module_drivers/drivers/clk/Makefile
+new file mode 100644
+index 000000000..e55de3616
+--- /dev/null
++++ b/module_drivers/drivers/clk/Makefile
+@@ -0,0 +1 @@
++obj-y += ingenic-v2/
+diff --git a/module_drivers/drivers/clk/ingenic-v2/Kconfig b/module_drivers/drivers/clk/ingenic-v2/Kconfig
+new file mode 100644
+index 000000000..659f97293
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/Kconfig
+@@ -0,0 +1,49 @@
++config COMMON_CLK_INGENIC
++	bool
++	depends on MACH_XBURST || MACH_XBURST2
++	select MFD_SYSCON
++	select INGENIC_CLK_DEBUG_FS
++
++config INGENIC_CLK_DEBUG_FS
++	bool
++	depends on DEBUG_FS
++	help
++	  enable ingenic common clock debugfs
++
++
++config CLK_X2000
++	bool "clk x2000"
++	depends on SOC_X2000
++	select COMMON_CLK_INGENIC
++	help
++	  build the ingenic x2000 soc clock driver.
++
++config CLK_X2100
++	bool "clk x2100"
++	depends on SOC_X2100
++	select COMMON_CLK_INGENIC
++	help
++	  build the ingenic x2000-v12 soc clock driver.
++
++config CLK_M300
++	bool "clk m300"
++	depends on SOC_M300
++	select COMMON_CLK_INGENIC
++	help
++	  build the ingenic m300 soc clock driver.
++
++
++config CLK_X2500
++	bool "clk x2500"
++	depends on SOC_X2500
++	select COMMON_CLK_INGENIC
++	help
++	  build the ingenic x2500 soc clock driver.
++
++config CLK_X1600
++	bool "clk x1600"
++	depends on SOC_X1600
++	select COMMON_CLK_INGENIC
++	help
++	  build the ingenic x1600 soc clock driver.
++
+diff --git a/module_drivers/drivers/clk/ingenic-v2/Makefile b/module_drivers/drivers/clk/ingenic-v2/Makefile
+new file mode 100644
+index 000000000..43fcf84c8
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/Makefile
+@@ -0,0 +1,35 @@
++
++ifdef CONFIG_CLK_X2000
++	EXTRA_CFLAGS += -DCLK_PLL_V1
++	CLK_PLL_V1 := y
++endif
++ifdef CONFIG_CLK_X2100
++	EXTRA_CFLAGS += -DCLK_PLL_V1
++	CLK_PLL_V1 := y
++endif
++ifdef CONFIG_CLK_M300
++	EXTRA_CFLAGS += -DCLK_PLL_V1
++	CLK_PLL_V1 := y
++endif
++ifdef CONFIG_CLK_X1600
++	EXTRA_CFLAGS += -DCLK_PLL_V2
++	CLK_PLL_V2 := y
++endif
++ifdef CONFIG_CLK_X2500
++	EXTRA_CFLAGS += -DCLK_PLL_V2
++	CLK_PLL_V2 := y
++endif
++
++obj-$(CONFIG_COMMON_CLK_INGENIC) += clk.o clk-div.o clk-bus.o power-gate.o
++obj-$(CLK_PLL_V1) += clk-pll-v1.o
++obj-$(CLK_PLL_V2) += clk-pll-v2.o
++
++
++obj-$(CONFIG_CLK_X2000)		+= clk-x2000.o
++obj-$(CONFIG_CLK_X2100)		+= clk-x2000.o
++obj-$(CONFIG_CLK_M300)		+= clk-m300.o
++obj-$(CONFIG_CLK_X1600)		+= clk-x1600.o
++obj-$(CONFIG_CLK_X2500)		+= clk-x2500.o
++
++
++
+diff --git a/module_drivers/drivers/clk/ingenic-v2/clk-bus.c b/module_drivers/drivers/clk/ingenic-v2/clk-bus.c
+new file mode 100644
+index 000000000..7fa55378b
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/clk-bus.c
+@@ -0,0 +1,238 @@
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/jiffies.h>
++#include <linux/err.h>
++#include "clk.h"
++
++static int clk_bus_wait(void __iomem *reg, u8 shift)
++{
++	unsigned int timeout = 0xfffff;
++
++	while (((readl(reg) >> shift) & 1) && --timeout);
++	if (!timeout) {
++		printk("WARNING : why cannot wait bus stable ???\n");
++		return -EIO;
++	} else {
++		return 0;
++	}
++}
++
++struct clk_bus_divider {
++	struct clk_divider div;
++	const struct clk_ops *div_ops;
++
++	void __iomem *busy_reg;
++
++	int busy_shift;
++	int ce_shift;
++
++	int shift1;
++	int width1;
++	int shift2;
++	int width2;
++
++	int div_flags;
++
++	spinlock_t * lock;
++};
++
++//static inline struct clk_bus *to_clk_bus_divider(struct clk_hw *hw)
++static inline struct clk_bus_divider *to_clk_bus_divider(struct clk_hw *hw)
++{
++	struct clk_divider *div = container_of(hw, struct clk_divider, hw);
++
++	return container_of(div, struct clk_bus_divider, div);
++}
++
++static unsigned long clk_bus_divider_recalc_rate(struct clk_hw *hw,
++						  unsigned long parent_rate)
++{
++	struct clk_bus_divider *bus_div = to_clk_bus_divider(hw);
++	struct clk_divider *divider = &bus_div->div;
++
++	divider->shift = bus_div->shift1;
++	divider->width = bus_div->width1;
++
++	return bus_div->div_ops->recalc_rate(&bus_div->div.hw, parent_rate);
++}
++
++static long clk_bus_divider_round_rate(struct clk_hw *hw, unsigned long rate,
++					unsigned long *prate)
++{
++	struct clk_bus_divider *bus_div = to_clk_bus_divider(hw);
++
++	return bus_div->div_ops->round_rate(&bus_div->div.hw, rate, prate);
++}
++
++static int clk_bus_divider_set_rate(struct clk_hw *hw, unsigned long rate,
++		unsigned long parent_rate)
++{
++	struct clk_bus_divider *bus_div = to_clk_bus_divider(hw);
++	struct clk_divider *divider = &bus_div->div;
++	int ret;
++	unsigned long flags = 0;
++	unsigned int val;
++	int ce = bus_div->ce_shift;
++
++
++	if(bus_div->lock) {
++		spin_lock_irqsave(bus_div->lock, flags);
++	}
++
++	/* set bus rate . */
++	if (bus_div->div_flags == BUS_DIV_SELF) {
++		ret = bus_div->div_ops->set_rate(&bus_div->div.hw, rate, parent_rate);
++	} else if (bus_div->div_flags == BUS_DIV_ONE) {
++
++		divider->shift = bus_div->shift1;
++		divider->width = bus_div->width1;
++		ret = bus_div->div_ops->set_rate(&bus_div->div.hw, rate, parent_rate);
++
++		divider->shift = bus_div->shift2;
++		divider->width = bus_div->width2;
++		ret = bus_div->div_ops->set_rate(&bus_div->div.hw, rate, parent_rate);
++	} else if (bus_div->div_flags == BUS_DIV_TWO) {
++
++		divider->shift = bus_div->shift1;
++		divider->width = bus_div->width1;
++		ret = bus_div->div_ops->set_rate(&bus_div->div.hw, rate, parent_rate);
++
++		divider->shift = bus_div->shift2;
++		divider->width = bus_div->width2;
++		ret = bus_div->div_ops->set_rate(&bus_div->div.hw, rate / 2, parent_rate);
++	}
++
++	/* ce  */
++	if(ce > 0) {
++		val = readl(bus_div->div.reg);
++		val |= (1 << ce);
++		writel(val, bus_div->div.reg);
++
++		ret = clk_bus_wait(bus_div->busy_reg, bus_div->busy_shift);
++		if(ret < 0) {
++			pr_err("wait bus clk: (%s)  stable timeout!\n", __clk_get_name(hw->clk));
++		}
++
++		val &= ~(1 << ce);
++		writel(val, bus_div->div.reg);
++	}
++	if(bus_div->lock) {
++		spin_unlock_irqrestore(bus_div->lock, flags);
++	}
++
++	return ret;
++}
++
++
++static struct clk_ops clk_bus_divider_ops = {
++	.recalc_rate = clk_bus_divider_recalc_rate,
++	.round_rate = clk_bus_divider_round_rate,
++	.set_rate = clk_bus_divider_set_rate,
++};
++
++struct clk *_register_bus_divider(struct device *dev, const char *name,
++		const char *parent_name, unsigned long flags,
++		void __iomem *reg, u8 shift1, u8 width1, u8 shift2, u8 width2,
++		void __iomem *busy_reg, u8 busy_shift,
++		int ce_shift,
++		u8 clk_divider_flags, u8 div_flags,
++		const struct clk_div_table *table,
++		spinlock_t *lock)
++{
++	struct clk_bus_divider *bus_div;
++	struct clk *clk;
++	struct clk_init_data init;
++
++	bus_div = kzalloc(sizeof(*bus_div), GFP_KERNEL);
++	if (!bus_div)
++		return ERR_PTR(-ENOMEM);
++
++	init.name = name;
++	init.ops = &clk_bus_divider_ops;
++	init.flags = flags;
++	init.parent_names = (parent_name ? &parent_name: NULL);
++	init.num_parents = (parent_name ? 1 : 0);
++
++	bus_div->busy_reg = busy_reg;
++	bus_div->busy_shift = busy_shift;
++	bus_div->ce_shift = ce_shift;
++	bus_div->lock = lock;
++
++	bus_div->div.reg = reg;
++	bus_div->div.shift = shift1;
++	bus_div->div.width = width1;
++	bus_div->shift1 = shift1;
++	bus_div->width1 = width1;
++	bus_div->shift2 = shift2;
++	bus_div->width2 = width2;
++	//bus_div->div.lock = lock;
++	bus_div->div.lock = NULL;	/* keep common block unlocked. add lock in this file */
++	bus_div->div.table = table;
++	bus_div->div.flags = clk_divider_flags ;
++	bus_div->div_ops = &clk_divider_ops;
++	bus_div->div_flags = div_flags ;
++
++
++	bus_div->div.hw.init = &init;
++
++	clk = clk_register(dev, &bus_div->div.hw);
++	if (IS_ERR(clk))
++		kfree(bus_div);
++
++	return clk;
++}
++
++/**
++ * clk_register_bus_divider_table - register a table based divider clock with
++ * the clock framework
++ * @dev: device registering this clock
++ * @name: name of this clock
++ * @parent_name: name of clock's parent
++ * @flags: framework-specific flags
++ * @reg: register address to adjust divider
++ * @shift: number of bits to shift the bitfield
++ * @busy_reg: register address of busy bit waiting.
++ * @busy_shift: bit index of busy in busy register.
++ * @width: width of the bitfield
++ * @clk_divider_flags: divider-specific flags for this clock
++ * @table: array of divider/value pairs ending with a div set to 0
++ * @lock: shared register lock for this clock
++ */
++struct clk *clk_register_bus_divider_table(struct device *dev, const char *name,
++		const char *parent_name, unsigned long flags,
++		void __iomem *reg, u8 shift1, u8 width1, u8 shift2, u8 width2,
++		void __iomem *busy_reg, u8 busy_shift, int ce_shift,
++		u8 clk_divider_flags, u8 div_flags,
++		const struct clk_div_table *table,
++		spinlock_t *lock)
++{
++	return _register_bus_divider(dev, name, parent_name, flags, reg, shift1,
++			width1, shift2, width2, busy_reg, busy_shift, ce_shift, clk_divider_flags, div_flags, table, lock);
++}
++
++
++/**
++ * clk_register_bus_divider - register a divider clock with the clock framework
++ * @dev: device registering this clock
++ * @name: name of this clock
++ * @parent_name: name of clock's parent
++ * @flags: framework-specific flags
++ * @reg: register address to adjust divider
++ * @shift: number of bits to shift the bitfield
++ * @width: width of the bitfield
++ * @busy_reg: register address of busy bit waiting.
++ * @busy_shift: bit index of busy in busy register.
++ * @clk_divider_flags: divider-specific flags for this clock
++ * @lock: shared register lock for this clock
++ */
++struct clk *clk_register_bus_divider(struct device *dev, const char *name,
++		const char *parent_name, unsigned long flags,
++		void __iomem *reg, u8 shift1 , u8 width1, u8 shift2, u8 width2,
++		void __iomem *busy_reg, u8 busy_shift, int ce_shift,
++		u8 clk_divider_flags, u8 div_flags, spinlock_t *lock)
++{
++	return _register_bus_divider(dev, name, parent_name, flags, reg, shift1, width1, shift2, width2, busy_reg, busy_shift, ce_shift, clk_divider_flags, div_flags, NULL, lock);
++}
++
+diff --git a/module_drivers/drivers/clk/ingenic-v2/clk-bus.h b/module_drivers/drivers/clk/ingenic-v2/clk-bus.h
+new file mode 100644
+index 000000000..56e0b710b
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/clk-bus.h
+@@ -0,0 +1,24 @@
++#ifndef __INGENIC_CLK_BUS_DIVIDER_H
++#define __INGENIC_CLK_BUS_DIVIDER_H
++
++#define BUS_DIV_SELF	BIT(6) + 1
++#define BUS_DIV_ONE	BIT(6) + 2
++#define BUS_DIV_TWO	BIT(6) + 3
++#define BUS_DIV_THREE	BIT(6) + 4
++#define BUS_DIV_FORE	BIT(6) + 5
++
++
++struct clk *clk_register_bus_divider_table(struct device *dev, const char *name,
++		const char *parent_name, unsigned long flags,
++		void __iomem *reg, u8 shift1, u8 width1, u8 shift2, u8 width2,
++		void __iomem *busy_reg, u8 busy_shift, int ce_shift,
++		u8 clk_divider_flags, u8 divider_flags,
++		const struct clk_div_table *table,
++		spinlock_t *lock);
++
++struct clk *clk_register_bus_divider(struct device *dev, const char *name,
++		const char *parent_name, unsigned long flags,
++		void __iomem *reg, u8 shift1, u8 width1, u8 shift2, u8 width2,
++		void __iomem *busy_reg, u8 busy_shift, int ce_shift,
++		u8 clk_divider_flags, u8 divider_flags, spinlock_t *lock);
++#endif
+diff --git a/module_drivers/drivers/clk/ingenic-v2/clk-div.c b/module_drivers/drivers/clk/ingenic-v2/clk-div.c
+new file mode 100644
+index 000000000..49aebd46a
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/clk-div.c
+@@ -0,0 +1,258 @@
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/jiffies.h>
++#include <linux/err.h>
++#include "clk.h"
++
++
++struct clk_cgu_divider {
++	struct clk_divider div;
++	const struct clk_ops *div_ops;
++	int busy_shift;
++	int en_shift;
++	int stop_shift;
++	spinlock_t *lock;
++};
++
++
++static int clk_cgu_wait(void __iomem *reg, u8 shift)
++{
++	unsigned int timeout = 0xfffff;
++
++	while (((readl(reg) >> shift) & 1) && --timeout);
++	if (!timeout) {
++		printk("WARNING : why cannot wait cgu stable ???\n");
++		return -ETIMEDOUT;
++	} else {
++		return 0;
++	}
++
++}
++
++static int cgu_divider_enable(struct clk_cgu_divider *cgu_div)
++{
++	int ret;
++	unsigned int val;
++	int ce, stop;
++
++	val = readl(cgu_div->div.reg);
++
++	ce = cgu_div->en_shift;
++	stop = cgu_div->stop_shift;
++
++	val |= (1 << ce);
++	val &= ~(1 << stop);
++	writel(val, cgu_div->div.reg);
++
++	ret = clk_cgu_wait(cgu_div->div.reg, cgu_div->busy_shift);
++	if(ret < 0) {
++		printk("wait cgu stable timeout!\n");
++	}
++
++	val &= ~(1 << ce);
++	writel(val, cgu_div->div.reg);
++
++	return ret;
++}
++
++static void cgu_divider_disable(struct clk_cgu_divider *cgu_div)
++{
++	unsigned int val;
++	int ce, stop;
++
++	val = readl(cgu_div->div.reg);
++
++	ce = cgu_div->en_shift;
++	stop = cgu_div->stop_shift;
++
++	val |= (1 << ce);
++	val |= (1 << stop);
++	writel(val, cgu_div->div.reg);
++
++	val &= ~(1 << ce);
++	writel(val, cgu_div->div.reg);
++
++}
++
++static inline struct clk_cgu_divider *to_clk_cgu_divider(struct clk_hw *hw)
++{
++	struct clk_divider *div = container_of(hw, struct clk_divider, hw);
++
++	return container_of(div, struct clk_cgu_divider, div);
++}
++
++static unsigned long clk_cgu_divider_recalc_rate(struct clk_hw *hw,
++						  unsigned long parent_rate)
++{
++	struct clk_cgu_divider *cgu_div = to_clk_cgu_divider(hw);
++	struct clk_divider *divider = &cgu_div->div;
++
++	return cgu_div->div_ops->recalc_rate(&cgu_div->div.hw, parent_rate);
++}
++
++static long clk_cgu_divider_round_rate(struct clk_hw *hw, unsigned long rate,
++					unsigned long *prate)
++{
++	struct clk_cgu_divider *cgu_div = to_clk_cgu_divider(hw);
++	unsigned long bestrate;
++
++	return  cgu_div->div_ops->round_rate(&cgu_div->div.hw, rate, prate);
++}
++
++static int clk_cgu_divider_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)
++{
++	struct clk_cgu_divider *cgu_div = to_clk_cgu_divider(hw);
++	struct clk_divider *divider = &cgu_div->div;
++	int ret;
++	unsigned long flags = 0;
++
++	if(cgu_div->lock)
++		spin_lock_irqsave(cgu_div->lock, flags);
++
++	ret = cgu_div->div_ops->set_rate(&cgu_div->div.hw, rate, parent_rate);
++
++	cgu_divider_enable(cgu_div);
++
++
++	if(cgu_div->lock)
++		spin_unlock_irqrestore(cgu_div->lock, flags);
++
++	return ret;
++}
++
++static void clk_cgu_divider_disable(struct clk_hw *hw)
++{
++	struct clk_cgu_divider *cgu_div = to_clk_cgu_divider(hw);
++	unsigned long flags = 0;
++
++	if(cgu_div->lock)
++		spin_lock_irqsave(cgu_div->lock, flags);
++
++	cgu_divider_disable(cgu_div);
++
++	if(cgu_div->lock)
++		spin_unlock_irqrestore(cgu_div->lock, flags);
++
++}
++
++
++static int clk_cgu_divider_enable(struct clk_hw *hw)
++{
++	struct clk_cgu_divider *cgu_div = to_clk_cgu_divider(hw);
++	unsigned long flags = 0;
++
++	if(cgu_div->lock)
++		spin_lock_irqsave(cgu_div->lock, flags);
++
++	cgu_divider_enable(cgu_div);
++
++	if(cgu_div->lock)
++		spin_unlock_irqrestore(cgu_div->lock, flags);
++
++	return 0;
++}
++
++static struct clk_ops clk_cgu_divider_ops = {
++	.recalc_rate = clk_cgu_divider_recalc_rate,
++	.round_rate = clk_cgu_divider_round_rate,
++	.set_rate = clk_cgu_divider_set_rate,
++	.enable = clk_cgu_divider_enable,
++	.disable = clk_cgu_divider_disable,
++};
++
++struct clk *_register_cgu_divider(struct device *dev, const char *name,
++		const char *parent_name, unsigned long flags,
++		void __iomem *reg, u8 shift, u8 width, u8 busy_shift,
++		int en_shift, u8 stop_shift, u8 clk_divider_flags,
++		const struct clk_div_table *table,
++		spinlock_t *lock)
++{
++	struct clk_cgu_divider *cgu_div;
++	struct clk *clk;
++	struct clk_init_data init;
++
++	cgu_div = kzalloc(sizeof(*cgu_div), GFP_KERNEL);
++	if (!cgu_div)
++		return ERR_PTR(-ENOMEM);
++
++	init.name = name;
++	init.ops = &clk_cgu_divider_ops;
++	init.flags = flags;
++	init.parent_names = (parent_name ? &parent_name: NULL);
++	init.num_parents = (parent_name ? 1 : 0);
++
++	cgu_div->busy_shift = busy_shift;
++	cgu_div->en_shift = en_shift;
++	cgu_div->stop_shift = stop_shift;
++	cgu_div->lock = lock;
++
++	cgu_div->div.reg = reg;
++	cgu_div->div.shift = shift;
++	cgu_div->div.width = width;
++	//cgu_div->div.lock = lock;
++	cgu_div->div.lock = NULL;	/* keep common block unlocked. add lock in this file */
++	cgu_div->div.table = table;
++	cgu_div->div.flags = clk_divider_flags;
++	cgu_div->div_ops = &clk_divider_ops;
++
++
++	cgu_div->div.hw.init = &init;
++
++	clk = clk_register(dev, &cgu_div->div.hw);
++	if (IS_ERR(clk))
++		kfree(cgu_div);
++
++	return clk;
++}
++
++/**
++ * clk_register_divider_table - register a table based divider clock with
++ * the clock framework
++ * @dev: device registering this clock
++ * @name: name of this clock
++ * @parent_name: name of clock's parent
++ * @flags: framework-specific flags
++ * @reg: register address to adjust divider
++ * @shift: number of bits to shift the bitfield
++ * @busy_shift: bit index of busy in busy register.
++ * @width: width of the bitfield
++ * @clk_divider_flags: divider-specific flags for this clock
++ * @table: array of divider/value pairs ending with a div set to 0
++ * @lock: shared register lock for this clock
++ */
++struct clk *clk_register_cgu_divider_table(struct device *dev, const char *name,
++		const char *parent_name, unsigned long flags,
++		void __iomem *reg, u8 shift, u8 width, u8 busy_shift,
++		int en_shift, u8 stop_shift, u8 clk_divider_flags,
++		const struct clk_div_table *table,
++		spinlock_t *lock)
++{
++	return _register_cgu_divider(dev, name, parent_name, flags, reg, shift,
++			width, busy_shift, en_shift, stop_shift, clk_divider_flags, table, lock);
++}
++
++
++/**
++ * clk_register_divider - register a divider clock with the clock framework
++ * @dev: device registering this clock
++ * @name: name of this clock
++ * @parent_name: name of clock's parent
++ * @flags: framework-specific flags
++ * @reg: register address to adjust divider
++ * @shift: number of bits to shift the bitfield
++ * @width: width of the bitfield
++ * @busy_shift: bit index of busy in busy register.
++ * @clk_divider_flags: divider-specific flags for this clock
++ * @lock: shared register lock for this clock
++ */
++struct clk *clk_register_cgu_divider(struct device *dev, const char *name,
++		const char *parent_name, unsigned long flags,
++		void __iomem *reg, u8 shift, u8 width, u8 busy_shift,
++		int en_shift, u8 stop_shift,
++		u8 clk_divider_flags, spinlock_t *lock)
++{
++	return _register_cgu_divider(dev, name, parent_name, flags, reg, shift, width, busy_shift, en_shift, stop_shift, clk_divider_flags, NULL, lock);
++}
++
+diff --git a/module_drivers/drivers/clk/ingenic-v2/clk-div.h b/module_drivers/drivers/clk/ingenic-v2/clk-div.h
+new file mode 100644
+index 000000000..e9e9d9949
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/clk-div.h
+@@ -0,0 +1,18 @@
++#ifndef __INGENIC_CLK_CGU_DIVIDER_H
++#define __INGENIC_CLK_CGU_DIVIDER_H
++
++
++struct clk *clk_register_cgu_divider_table(struct device *dev, const char *name,
++		const char *parent_name, unsigned long flags,
++		void __iomem *reg, u8 shift, u8 width, u8 busy_shift, 
++		int en_shift, u8 stop_shift, u8 clk_divider_flags,
++		const struct clk_div_table *table,
++		spinlock_t *lock);
++
++struct clk *clk_register_cgu_divider(struct device *dev, const char *name,
++		const char *parent_name, unsigned long flags, 
++		void __iomem *reg, u8 shift, u8 width, u8 busy_shift, 
++		int en_shift, u8 stop_shift,
++		u8 clk_divider_flags, spinlock_t *lock);
++
++#endif /* __SAMSUNG_CLK_PLL_H */
+diff --git a/module_drivers/drivers/clk/ingenic-v2/clk-m300.c b/module_drivers/drivers/clk/ingenic-v2/clk-m300.c
+new file mode 100644
+index 000000000..40375492c
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/clk-m300.c
+@@ -0,0 +1,395 @@
++#include <linux/slab.h>
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/syscore_ops.h>
++#include <linux/clk.h>
++
++#include <dt-bindings/clock/ingenic-m300.h>
++
++#include "clk.h"
++
++
++
++/*******************************************************************************
++ *      FIXED CLK
++ ********************************************************************************/
++static struct ingenic_fixed_rate_clock m300_fixed_rate_ext_clks[] __initdata = {
++	FRATE(CLK_EXT, "ext", NULL, 0, 24000000),
++	FRATE(CLK_RTC_EXT, "rtc_ext", NULL, 0, 32768),
++	FRATE(CLK_EXT_DIV_512, "ext_div_512", NULL,0, 46875),
++};
++
++
++
++/*******************************************************************************
++ *      PLL
++ ********************************************************************************/
++
++static struct ingenic_pll_rate_table m300_pll_rate_table[] = {
++	PLL_RATE(1500000000, 124, 1, 1),
++	PLL_RATE(1200000000, 49, 0, 1),
++	PLL_RATE(800000000, 199, 2, 2),
++	PLL_RATE(600000000, 49, 0, 2),
++	PLL_RATE(300000000, 49, 0, 3),
++};
++
++
++
++/*PLL HWDESC*/
++static struct ingenic_pll_hwdesc apll_hwdesc = \
++	PLL_DESC(CPM_CPAPCR, 20, 9, 14, 6, 11, 3, 3, 0, pll_od_encode);
++
++static struct ingenic_pll_hwdesc mpll_hwdesc = \
++	PLL_DESC(CPM_CPMPCR, 20, 9, 14, 6, 11, 3, 3, 0, pll_od_encode);
++
++static struct ingenic_pll_hwdesc epll_hwdesc = \
++	PLL_DESC(CPM_CPEPCR, 20, 9, 14, 6, 11, 3, 3, 0, pll_od_encode);
++
++
++
++static struct ingenic_pll_clock m300_pll_clks[] __initdata = {
++	PLL(CLK_PLL_APLL, "apll", "ext", &apll_hwdesc, m300_pll_rate_table),
++	PLL(CLK_PLL_MPLL, "mpll", "ext", &mpll_hwdesc, m300_pll_rate_table),
++	PLL(CLK_PLL_EPLL, "epll", "ext", &epll_hwdesc, m300_pll_rate_table),
++};
++
++
++/*******************************************************************************
++ *      MUX
++ ********************************************************************************/
++PNAME(mux_table_0)	= {"stop",	"ext",		"apll"};
++PNAME(mux_table_1)	= {"stop",	"sclka",	"mpll"};
++PNAME(mux_table_2)	= {"sclka",	"mpll",		"epll"};
++PNAME(mux_table_3)	= {"sclka", 	"mpll",		"ext"};
++PNAME(mux_table_4)	= {"sclka", 	"epll"};
++PNAME(mux_table_5)	= {"mux_ahb2",	"ext"};
++PNAME(mux_table_6)	= {"ext",	"div_i2s3"};
++PNAME(mux_table_7)	= {"div_i2s0",	"div_i2s1",	"div_i2s2",	"div_i2s3"};
++PNAME(mux_table_8)	= {"ext_div_512",	"rtc_ext"};
++
++static unsigned int ingenic_mux_table[] = {0, 1, 2, 3};
++
++
++static struct ingenic_mux_clock m300_mux_clks[] __initdata = {
++	MUX(CLK_MUX_SCLKA,	"sclka",		ingenic_mux_table, mux_table_0, CPM_CPCCR,	30, 2, 0),
++	MUX(CLK_MUX_CPU_L2C,	"mux_cpu_l2c",		ingenic_mux_table, mux_table_1, CPM_CPCCR,	28, 2, 0),
++	MUX(CLK_MUX_AHB0,	"mux_ahb0",		ingenic_mux_table, mux_table_1, CPM_CPCCR,	26, 2, 0),
++	MUX(CLK_MUX_AHB2,	"mux_ahb2",		ingenic_mux_table, mux_table_1, CPM_CPCCR,	24, 2, 0),
++
++	MUX(CLK_MUX_DDR,	"mux_ddr",		ingenic_mux_table, mux_table_1, CPM_DDRCDR,	30, 2, 0),
++	MUX(CLK_MUX_MACPHY,	"mux_macphy",		ingenic_mux_table, mux_table_2, CPM_MACCDR,	30, 2, 0),
++	MUX(CLK_MUX_MACTXPHY,	"mux_mactxphy",		ingenic_mux_table, mux_table_2, CPM_MACTXCDR,	30, 2, 0),
++	MUX(CLK_MUX_MACTXPHY1,	"mux_mactxphy1",	ingenic_mux_table, mux_table_2, CPM_MACTXCDR1,	30, 2, 0),
++	MUX(CLK_MUX_MACPTP,	"mux_macptp",		ingenic_mux_table, mux_table_2, CPM_MACPTP,	30, 2, 0),
++	MUX(CLK_MUX_I2S0,	"mux_i2s0",		ingenic_mux_table, mux_table_4, CPM_I2S0CDR,	30, 1, 0),
++	MUX(CLK_MUX_I2S1,	"mux_i2s1",		ingenic_mux_table, mux_table_4, CPM_I2S1CDR,	30, 1, 0),
++	MUX(CLK_MUX_I2S2,	"mux_i2s2",		ingenic_mux_table, mux_table_4, CPM_I2S2CDR,	30, 1, 0),
++	MUX(CLK_MUX_I2S3,	"mux_i2s3",		ingenic_mux_table, mux_table_4, CPM_I2S3CDR,	30, 1, 0),
++	MUX(CLK_MUX_AUDIO_RAM,	"mux_audio_ram",	ingenic_mux_table, mux_table_5, CPM_AUDIOCR,	30, 1, 0),
++	MUX(CLK_MUX_SPDIF,	"mux_spdif",		ingenic_mux_table, mux_table_7, CPM_AUDIOCR,	3,  2, CLK_SET_RATE_PARENT|CLK_SET_RATE_NO_REPARENT),
++	MUX(CLK_MUX_PCM,	"mux_pcm",		ingenic_mux_table, mux_table_7, CPM_AUDIOCR,	1,  2, CLK_SET_RATE_PARENT|CLK_SET_RATE_NO_REPARENT),
++	MUX(CLK_MUX_DMIC,	"mux_dmic",		ingenic_mux_table, mux_table_6, CPM_AUDIOCR,	0,  1, CLK_SET_RATE_PARENT|CLK_SET_RATE_NO_REPARENT),
++	MUX(CLK_MUX_LCD,	"mux_lcd",		ingenic_mux_table, mux_table_2, CPM_LPCDR,	30, 2, 0),
++	MUX(CLK_MUX_MSC0,	"mux_msc0",		ingenic_mux_table, mux_table_3, CPM_MSC0CDR,	30, 2, 0),
++	MUX(CLK_MUX_MSC1,	"mux_msc1",		ingenic_mux_table, mux_table_3, CPM_MSC1CDR,	30, 2, 0),
++	MUX(CLK_MUX_MSC2,	"mux_msc2",		ingenic_mux_table, mux_table_3, CPM_MSC2CDR,	30, 2, 0),
++	MUX(CLK_MUX_SFC,	"mux_sfc",		ingenic_mux_table, mux_table_2, CPM_SFCCDR,	30, 2, 0),
++	MUX(CLK_MUX_SSI,	"mux_ssi",		ingenic_mux_table, mux_table_2, CPM_SSICDR,	30, 2, 0),
++	MUX(CLK_MUX_CIM,	"mux_cim",		ingenic_mux_table, mux_table_2, CPM_CIMCDR,	30, 2, 0),
++	MUX(CLK_MUX_PWM,	"mux_pwm",		ingenic_mux_table, mux_table_2, CPM_PWMCDR,	30, 2, 0),
++	MUX(CLK_MUX_ISP,	"mux_isp",		ingenic_mux_table, mux_table_2, CPM_ISPCDR,	30, 2, 0),
++	MUX(CLK_MUX_RSA,	"mux_rsa",		ingenic_mux_table, mux_table_2, CPM_RSACDR,	30, 2, 0),
++	MUX(CLK_MUX_WDT,	"mux_wdt",		ingenic_mux_table, mux_table_8, CPM_OPCR,	2, 1, 0),
++
++};
++
++/*******************************************************************************
++ *      DIV BUS
++ ********************************************************************************/
++
++static struct ingenic_bus_clock m300_bus_div_clks[] __initdata = {
++	BUS_DIV(CLK_DIV_CPU,		"div_cpu",		"mux_cpu_l2c",		CPM_CPCCR,	0,  4, 0, 0, CPM_CPCSR, 0, 22, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_L2C,		"div_l2c",		"mux_cpu_l2c",		CPM_CPCCR,	4,  4, 0, 0, CPM_CPCSR, 0, 22, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_AHB0,		"div_ahb0",		"mux_ahb0",		CPM_CPCCR,	8,  4, 0, 0, CPM_CPCSR, 1, 21, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_AHB2,		"div_ahb2",		"mux_ahb2",		CPM_CPCCR,	12, 4, 0, 0, CPM_CPCSR, 2, 20, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_APB,		"div_apb",		"mux_ahb2",		CPM_CPCCR,	16, 4, 0, 0, CPM_CPCSR, 2, 20, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_CPU_L2C_X1,	"div_cpu_l2c_x1",	"mux_cpu_l2c",		CPM_CPCCR,	0,  4, 4, 4, CPM_CPCSR, 0, 22, BUS_DIV_ONE),
++	BUS_DIV(CLK_DIV_CPU_L2C_X2,	"div_cpu_l2c_x2",	"mux_cpu_l2c",		CPM_CPCCR,	0,  4, 4, 4, CPM_CPCSR, 0, 22, BUS_DIV_TWO),
++};
++
++
++/*******************************************************************************
++ *      DIV
++ ********************************************************************************/
++
++static struct clk_div_table m300_clk_div_table[256] = {};
++
++static struct ingenic_div_clock m300_div_clks[] __initdata = {
++	DIV(CLK_DIV_DDR,		"div_ddr",		"mux_ddr",		CPM_DDRCDR,	4,  0, NULL),
++	DIV(CLK_DIV_MACPHY,		"div_macphy",		"mux_macphy",		CPM_MACCDR,	8,  0, NULL),
++	DIV(CLK_DIV_MACTXPHY,		"div_mactxphy0",	"mux_mactxphy",		CPM_MACTXCDR,	8,  0, NULL),
++	DIV(CLK_DIV_MACTXPHY1,		"div_mactxphy1",	"mux_mactxphy1",	CPM_MACTXCDR1,	8,  0, NULL),
++	DIV(CLK_DIV_MACPTP,		"div_macptp",		"mux_macptp",		CPM_MACPTP,	8,  0, NULL),
++	DIV(CLK_DIV_LCD,		"div_lcd",		"mux_lcd",		CPM_LPCDR,	8,  0, NULL),
++	DIV(CLK_DIV_MSC0,		"div_msc0",		"mux_msc0",		CPM_MSC0CDR,	8,  0, m300_clk_div_table),
++	DIV(CLK_DIV_MSC1,		"div_msc1",		"mux_msc1",		CPM_MSC1CDR,	8,  0, m300_clk_div_table),
++	DIV(CLK_DIV_MSC2,		"div_msc2",		"mux_msc2",		CPM_MSC2CDR,	8,  0, m300_clk_div_table),
++	DIV(CLK_DIV_SFC,		"div_sfc",		"mux_sfc",		CPM_SFCCDR,	8,  0, NULL),
++	DIV(CLK_DIV_SSI,		"div_ssi",		"mux_ssi",		CPM_SSICDR,	8,  0, NULL),
++	DIV(CLK_DIV_CIM,		"div_cim",		"mux_cim",		CPM_CIMCDR,	8,  0, NULL),
++	DIV(CLK_DIV_PWM,		"div_pwm",		"mux_pwm",		CPM_PWMCDR,	4,  0, NULL),
++	DIV(CLK_DIV_ISP,		"div_isp",		"mux_isp",		CPM_ISPCDR,	4,  0, NULL),
++	DIV(CLK_DIV_RSA,		"div_rsa",		"mux_rsa",		CPM_RSACDR,	4,  0, NULL),
++
++};
++
++/*******************************************************************************
++ *      FRACTIONAL-DIVIDER
++ ********************************************************************************/
++
++static struct ingenic_fra_div_clock m300_fdiv_clks[] __initdata = {
++	FRA_DIV(CLK_DIV_I2S0,	"div_i2s0",	"mux_i2s0",	CPM_I2S0CDR,	20, 9, 0, 20),
++	FRA_DIV(CLK_DIV_I2S1,	"div_i2s1",	"mux_i2s1",	CPM_I2S1CDR,	20, 9, 0, 20),
++	FRA_DIV(CLK_DIV_I2S2,	"div_i2s2",	"mux_i2s2",	CPM_I2S2CDR,	20, 9, 0, 20),
++	FRA_DIV(CLK_DIV_I2S3,	"div_i2s3",	"mux_i2s3",	CPM_I2S3CDR,	20, 9, 0, 20),
++};
++
++/*******************************************************************************
++ *      GATE
++ ********************************************************************************/
++static struct ingenic_gate_clock m300_gate_clks[] __initdata = {
++
++	GATE(CLK_GATE_DDR,	"gate_ddr",		"div_ddr",	CPM_CLKGR,  31, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE),
++//	GATE(CLK_GATE_IPU,	"gate_ipu",		"div_ipu",	CPM_CLKGR,  30, 0,			 CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_AHB0,	"gate_ahb0",		"div_ahb0",	CPM_CLKGR,  29, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_APB0,	"gate_apb0",		"div_ahb0",	CPM_CLKGR,  28, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_RTC,	"gate_rtc",		"rtc_ext",	CPM_CLKGR,  27, 0,			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SSI1,	"gate_ssi1",		"div_ssi",	CPM_CLKGR,  26, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_RSA,	"gate_rsa",		"div_rsa",	CPM_CLKGR,  25, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_AES,	"gate_aes",		"div_ahb2",	CPM_CLKGR,  24, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_LCD,	"gate_lcd",		"div_lcd",	CPM_CLKGR,  23, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_CIM,	"gate_cim",		"div_cim",	CPM_CLKGR,  22, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_PDMA,	"gate_pdma",		"div_ahb2",	CPM_CLKGR,  21, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_OST,	"gate_ost",		"ext",		CPM_CLKGR,  20, CLK_IGNORE_UNUSED, 	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SSI0,	"gate_ssi0",		"div_ssi",	CPM_CLKGR,  19, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_TCU,	"gate_tcu",		"div_apb",	CPM_CLKGR,  18, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_DTRNG,	"gate_dtrng",		"div_apb",	CPM_CLKGR,  17, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART2,	"gate_uart2",		"div_apb",	CPM_CLKGR,  16, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART1,	"gate_uart1",		"div_apb",	CPM_CLKGR,  15, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART0,	"gate_uart0",		"div_apb",	CPM_CLKGR,  14, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SADC,	"gate_sadc",		"div_apb",	CPM_CLKGR,  13, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_HELIX,	"gate_helix",		"div_ahb0",	CPM_CLKGR,  12, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_AUDIO,	"gate_audio",		"div_ahb2",	CPM_CLKGR,  11, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB3,	"gate_i2c3",		"div_apb",	CPM_CLKGR,  10, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB2,	"gate_i2c2",		"div_apb",	CPM_CLKGR,  9,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB1,	"gate_i2c1",		"div_apb",	CPM_CLKGR,  8,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB0,	"gate_i2c0",		"div_apb",	CPM_CLKGR,  7,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SCC,	"gate_scc",		"div_apb",	CPM_CLKGR,  6,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_MSC1,	"gate_msc1",		"div_msc1",	CPM_CLKGR,  5,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_MSC0,	"gate_msc0",		"div_msc0",	CPM_CLKGR,  4,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_OTG,	"gate_otg",		"div_ahb2",	CPM_CLKGR,  3,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SFC,	"gate_sfc",		"div_sfc",	CPM_CLKGR,  2,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_EFUSE,	"gate_efuse",		"div_ahb2",	CPM_CLKGR,  1,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_NEMC,	"gate_nemc",		"div_ahb2",	CPM_CLKGR,  0,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_ARB,	"gate_arb",		"div_ahb0",	CPM_CLKGR1, 30, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_MIPI_DSI, "gate_dsi",		"div_ahb0",	CPM_CLKGR1, 29, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_MIPI_CSI, "gate_csi",		"div_ahb0",	CPM_CLKGR1, 28, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_INTC,	"gate_intc",		"div_ahb2",	CPM_CLKGR1, 26, CLK_IGNORE_UNUSED, 	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_MSC2,	"gate_msc2",		"div_msc2",	CPM_CLKGR1, 25, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_GMAC1,	"gate_gmac1",		"div_ahb2",	CPM_CLKGR1, 24, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_GMAC0,	"gate_gmac0",		"div_ahb2",	CPM_CLKGR1, 23, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART9,	"gate_uart9",		"div_apb",	CPM_CLKGR1, 22, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART8,	"gate_uart8",		"div_apb",	CPM_CLKGR1, 21, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART7,	"gate_uart7",		"div_apb",	CPM_CLKGR1, 20, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UATR6,	"gate_uart6",		"div_apb",	CPM_CLKGR1, 19, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART5,	"gate_uart5",		"div_apb",	CPM_CLKGR1, 18, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART4,	"gate_uart4",		"div_apb",	CPM_CLKGR1, 17, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART3,	"gate_uart3",		"div_apb",	CPM_CLKGR1, 16, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SPDIF,	"gate_spdif",		"mux_spdif",	CPM_CLKGR1, 14, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_DMIC,	"gate_dmic",		"mux_dmic",	CPM_CLKGR1, 13, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_PCM,	"gate_pcm",		"mux_pcm",	CPM_CLKGR1, 12, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_I2S3,	"gate_i2s3",		"div_i2s3",	CPM_CLKGR1, 11, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_I2S2,	"gate_i2s2",		"div_i2s2",	CPM_CLKGR1, 10, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_I2S1,	"gate_i2s1",		"div_i2s1",	CPM_CLKGR1, 9,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_I2S0,	"gate_i2s0",		"div_i2s0",	CPM_CLKGR1, 8,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_ROT,	"gate_rot",		"div_ahb0",	CPM_CLKGR1, 7,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_HASH,	"gate_hash",		"div_ahb2",	CPM_CLKGR1, 6,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_PWM,	"gate_pwm",		"div_pwm",	CPM_CLKGR1, 5,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_FELIX,	"gate_felix",		"div_ahb0",	CPM_CLKGR1, 4,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_ISP1,	"gate_isp1",		"div_apb",	CPM_CLKGR1, 3,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_ISP0,	"gate_isp0",		"div_apb",	CPM_CLKGR1, 2,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB5,	"gate_i2c5",		"div_apb",	CPM_CLKGR1, 1,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB4,	"gate_i2c4",		"div_apb",	CPM_CLKGR1, 0,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_USBPHY,	"gate_usbphy",		"div_apb",	CPM_OPCR,   23, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_CE_I2S0,	"ce_i2s0",		"div_i2s0",	CPM_I2S0CDR, 29, 0, 0),
++	GATE(CLK_CE_I2S1,	"ce_i2s1",		"div_i2s1",	CPM_I2S1CDR, 29, 0, 0),
++	GATE(CLK_CE_I2S2,	"ce_i2s2",		"div_i2s2",	CPM_I2S2CDR, 29, 0, 0),
++	GATE(CLK_CE_I2S3,	"ce_i2s3",		"div_i2s3",	CPM_I2S3CDR, 29, 0, 0),
++};
++
++static struct ingenic_gate_power m300_gate_power[] __initdata = {
++
++	POWER(POWER_ISP0,	"power_isp0",		"gate_isp0",	CPM_LCR,  31, 27, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, POWER_GATE_WAIT),
++	POWER(POWER_ISP1,	"power_isp1",		"gate_isp1",	CPM_LCR,  30, 26, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, POWER_GATE_WAIT),
++	POWER(POWER_FELIX,	"power_felix",		"gate_felix",	CPM_LCR,  29, 25, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, POWER_GATE_WAIT),
++	POWER(POWER_HELIX,	"power_helix",		"gate_helix",	CPM_LCR,  28, 24, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, POWER_GATE_WAIT),
++
++	POWER(PD_MEM_NEMC,	"pd_mem_nemc",		"gate_nemc",	CPM_MPDCR,  28, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_USB,	"pd_mem_usb",		"gate_usb",	CPM_MPDCR,  27, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_SFC,	"pd_mem_sfc",		"gate_sfc",	CPM_MPDCR,  26, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_PDMA_SEC,	"pd_mem_pdma_sec",	"gate_pdma",	CPM_MPDCR,  25, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_PDMA,	"pd_mem_pdma",		"gate_pdma",	CPM_MPDCR,  24, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_MSC2,	"pd_mem_msc2",		"gate_msc2",	CPM_MPDCR,  23, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_MSC1,	"pd_mem_msc1",		"gate_msc1",	CPM_MPDCR,  22, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_MSC0,	"pd_mem_msc0",		"gate_msc0",	CPM_MPDCR,  21, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_GMAC1,	"pd_mem_gmac1",		"gate_gmac1",	CPM_MPDCR,  20, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_GMAC0,	"pd_mem_gmac0",		"gate_gmac0",	CPM_MPDCR,  19, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DMIC,	"pd_mem_dmic",		"gate_dmic",	CPM_MPDCR,  18, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_AUDIO,	"pd_mem_audio",		"gate_audio",	CPM_MPDCR,  17, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_AES,	"pd_mem_aes",		"gate_aes",	CPM_MPDCR,  16, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DSI,	"pd_mem_dsi",		"gate_dsi",	CPM_MPDCR,  12, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_SSI1,	"pd_mem_ssi1",		"gate_ssi1",	CPM_MPDCR,  11, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_SSI0,	"pd_mem_ssi0",		"gate_ssi0",	CPM_MPDCR,  10, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART9,	"pd_mem_uart9",		"gate_uart9",	CPM_MPDCR,  9,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART8,	"pd_mem_uart8",		"gate_uart8",	CPM_MPDCR,  8,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART7,	"pd_mem_uart7",		"gate_uart7",	CPM_MPDCR,  7,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART6,	"pd_mem_uart6",		"gate_uart6",	CPM_MPDCR,  6,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART5,	"pd_mem_uart5",		"gate_uart5",	CPM_MPDCR,  5,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART4,	"pd_mem_uart4",		"gate_uart4",	CPM_MPDCR,  4,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART3,	"pd_mem_uart3",		"gate_uart3",	CPM_MPDCR,  3,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART2,	"pd_mem_uart2",		"gate_uart2",	CPM_MPDCR,  2,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART1,	"pd_mem_uart1",		"gate_uart1",	CPM_MPDCR,  1,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART0,	"pd_mem_uart0",		"gate_uart0",	CPM_MPDCR,  0,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_ROT,	"pd_mem_rot",		"gate_rot",	CPM_MPDCR1, 8,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_CIM,	"pd_mem_cim",		"gate_cim",	CPM_MPDCR1, 7,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DPU,	"pd_mem_dpu",		"gate_dpu",	CPM_MPDCR1, 6,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DDR_CH6,	"pd_mem_ddr_ch6",	"gate_ddr",	CPM_MPDCR1, 5,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DDR_CH5,	"pd_mem_ddr_ch5",	"gate_ddr",	CPM_MPDCR1, 4,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DDR_CH3,	"pd_mem_ddr_ch3",	"gate_ddr",	CPM_MPDCR1, 3,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DDR_CH1,	"pd_mem_ddr_ch1",	"gate_ddr",	CPM_MPDCR1, 2,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DDR_CH0,	"pd_mem_ddr_ch0",	"gate_ddr",	CPM_MPDCR1, 1,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DDR_TOP,	"pd_mem_ddr_top",	"gate_ddr",	CPM_MPDCR1, 0,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++
++};
++
++static void clk_div_table_generate(void)
++{
++	int i;
++	for (i = 0; i < ARRAY_SIZE(m300_clk_div_table); i++) {
++		m300_clk_div_table[i].val = i;
++		m300_clk_div_table[i].div = (i + 1) * 4;
++	}
++
++}
++
++static const struct of_device_id ext_clk_match[] __initconst = {
++	        { .compatible = "ingenic,fixed-clock", .data = (void *)0, },
++		{},
++};
++
++
++struct ingenic_clk_reg_sleep m300_clk_reg_sleep[] = {
++
++	REG_SLEEP(CPM_MACCDR,	29, 28, 0),
++	REG_SLEEP(CPM_MACTXCDR,	29, 28, 0),
++	REG_SLEEP(CPM_MACTXCDR1,29, 28, 0),
++	REG_SLEEP(CPM_MACPTP,	29, 28, 0),
++	REG_SLEEP(CPM_I2S0CDR,	0,0,0),
++	REG_SLEEP(CPM_I2S1CDR,	0,0,0),
++	REG_SLEEP(CPM_I2S2CDR,	0,0,0),
++	REG_SLEEP(CPM_I2S3CDR,	0,0,0),
++	REG_SLEEP(CPM_I2S0CDR1,	0,0,0),
++	REG_SLEEP(CPM_I2S1CDR1,	0,0,0),
++	REG_SLEEP(CPM_I2S2CDR1,	0,0,0),
++	REG_SLEEP(CPM_I2S3CDR1,	0,0,0),
++	REG_SLEEP(CPM_AUDIOCR,	0,0,0),
++	REG_SLEEP(CPM_LPCDR,    29,28,0),
++	REG_SLEEP(CPM_MSC0CDR,    29,28,0),
++	REG_SLEEP(CPM_MSC1CDR,    29,28,0),
++	REG_SLEEP(CPM_MSC2CDR,    29,28,0),
++	REG_SLEEP(CPM_SFCCDR,    29,28,0),
++	REG_SLEEP(CPM_SSICDR,    29,28,0),
++	REG_SLEEP(CPM_CIMCDR,    29,28,0),
++	REG_SLEEP(CPM_PWMCDR,    29,28,0),
++	REG_SLEEP(CPM_ISPCDR,    29,28,0),
++	REG_SLEEP(CPM_RSACDR,    29,28,0),
++};
++
++unsigned int m300_nr_clk_reg_sleep = ARRAY_SIZE(m300_clk_reg_sleep);
++
++
++/* Register m300 clocks. */
++static void __init m300_clk_init(struct device_node *np, void __iomem *base)
++{
++	struct ingenic_clk_provider *ctx;
++	void __iomem *reg_base;
++
++
++	printk("m300 Clock Power Management Unit init!\n");
++
++	reg_base = base;
++
++	if (np) {
++		reg_base = of_iomap(np, 0);
++		if (!reg_base)
++			panic("%s: failed to map registers\n", __func__);
++	}
++
++
++	ctx = ingenic_clk_init(np, reg_base, NR_CLKS);
++	if (!ctx)
++		panic("%s: unable to allocate context.\n", __func__);
++
++	/* Register Ext Clocks From DT */
++	ingenic_clk_of_register_fixed_ext(ctx, m300_fixed_rate_ext_clks,
++			                        ARRAY_SIZE(m300_fixed_rate_ext_clks), ext_clk_match);
++
++	/* Register PLLs. */
++	ingenic_clk_register_pll(ctx, m300_pll_clks,
++				ARRAY_SIZE(m300_pll_clks), reg_base);
++
++
++	/* Register Muxs */
++	ingenic_clk_register_mux(ctx, m300_mux_clks, ARRAY_SIZE(m300_mux_clks));
++
++	/* Register Bus Divs */
++	ingenic_clk_register_bus_div(ctx, m300_bus_div_clks, ARRAY_SIZE(m300_bus_div_clks));
++
++	/* Register Divs */
++	clk_div_table_generate();
++	ingenic_clk_register_cgu_div(ctx, m300_div_clks, ARRAY_SIZE(m300_div_clks));
++
++	/* Register Fractional Divs */
++	ingenic_clk_register_fra_div(ctx, m300_fdiv_clks, ARRAY_SIZE(m300_fdiv_clks));
++
++	/* Register Gates */
++	ingenic_clk_register_gate(ctx, m300_gate_clks, ARRAY_SIZE(m300_gate_clks));
++
++	/* Register Powers */
++	ingenic_power_register_gate(ctx, m300_gate_power, ARRAY_SIZE(m300_gate_power));
++
++
++	ingenic_clk_of_add_provider(np, ctx);
++
++
++	ingenic_clk_sleep_init(reg_base, m300_clk_reg_sleep, m300_nr_clk_reg_sleep);
++
++
++//	ingenic_clk_of_dump(ctx);
++
++
++	pr_info("=========== m300 clocks: =============\n"
++		"\tapll     = %lu , mpll     = %lu\n"
++		"\tcpu_clk  = %lu , l2c_clk  = %lu\n"
++		"\tahb0_clk = %lu , ahb2_clk = %lu\n"
++		"\tapb_clk  = %lu , ext_clk  = %lu\n\n",
++		_get_rate("apll"),	_get_rate("mpll"),
++		_get_rate("div_cpu"), _get_rate("div_l2c"),
++		_get_rate("div_ahb0"), _get_rate("div_ahb2"),
++		_get_rate("div_apb"), _get_rate("ext"));
++
++}
++
++CLK_OF_DECLARE(m300_clk, "ingenic,m300-clocks", m300_clk_init);
++
+diff --git a/module_drivers/drivers/clk/ingenic-v2/clk-pll-v1.c b/module_drivers/drivers/clk/ingenic-v2/clk-pll-v1.c
+new file mode 100644
+index 000000000..3834cf9cb
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/clk-pll-v1.c
+@@ -0,0 +1,185 @@
++#include <linux/err.h>
++#include <linux/hrtimer.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/clkdev.h>
++#include "clk.h"
++#include "clk-pll-v1.h"
++
++#define PLL_TIMEOUT_MS		10
++
++struct ingenic_clk_pll {
++	struct clk_hw		hw;
++	void __iomem		*lock_reg;
++	void __iomem		*con_reg;
++	unsigned int		rate_count;
++
++	struct ingenic_pll_hwdesc *hwdesc;
++	struct ingenic_pll_rate_table *rate_table;
++
++};
++
++#define to_clk_pll(_hw) container_of(_hw, struct ingenic_clk_pll, hw)
++
++
++
++static long ingenic_pll_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate)
++{
++	struct ingenic_clk_pll *pll = to_clk_pll(hw);
++	const struct ingenic_pll_rate_table *rate_table = pll->rate_table;
++	int i;
++	unsigned int rate;
++
++	for (i = 0; i < pll->rate_count; i++) {
++		if (drate >= rate_table[i].rate)
++			return  rate_table[i].rate;
++	}
++
++	return rate_table[i - 1].rate;
++
++
++}
++
++
++static unsigned long ingenic_v1_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++	struct ingenic_clk_pll *pll = to_clk_pll(hw);
++	unsigned int val;
++	unsigned int fd, rd, od;
++	unsigned int nf, nr, no;
++	unsigned long fout;
++
++
++	val = readl(pll->con_reg);
++
++	fd = (val >> pll->hwdesc->fd_sft) & ((1 << pll->hwdesc->fd_width) - 1);
++	rd = (val >> pll->hwdesc->rd_sft) & ((1 << pll->hwdesc->rd_width) - 1);
++	od = (val >> pll->hwdesc->od_sft) & ((1 << pll->hwdesc->od_width) - 1);
++
++	nf = 1 + fd;
++	nr = 1 + rd;
++	no = pll_od_encode[od];
++
++	fout = parent_rate / (nr * no) * 2 * nf;
++
++	return fout;
++}
++
++static int wait_pll_stable(void __iomem *reg, u32 shift)
++{
++	unsigned int timeout = 0xffff;
++
++	while ((!((readl(reg) >> shift) & 1)) && --timeout);
++	if (!timeout) {
++		printk("WARNING : why cannot wait pll stable ???\n");
++		return -ETIMEDOUT;
++	} else {
++		return 0;
++	}
++}
++
++static int ingenic_v1_pll_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate)
++{
++	struct ingenic_clk_pll *pll = to_clk_pll(hw);
++
++	unsigned int fd;
++	unsigned int rd;
++	unsigned int od;
++	unsigned int val, i;
++
++	for (i = 0; i < pll->rate_count; i++) {
++		if (drate == pll->rate_table[i].rate) {
++			fd = pll->rate_table[i].fd;
++			rd = pll->rate_table[i].rd;
++			od = pll->rate_table[i].od;
++		}
++	}
++
++
++
++	writel(0, pll->con_reg);
++	val = (fd << pll->hwdesc->fd_sft) | (rd << pll->hwdesc->rd_sft) | (od << pll->hwdesc->od_sft) | 1;
++	writel(val, pll->con_reg);
++
++	wait_pll_stable(pll->con_reg, pll->hwdesc->on_bit);
++
++	return 0;
++}
++
++
++static const struct clk_ops ingenic_v1_pll_clk_ops = {
++	.recalc_rate = ingenic_v1_pll_recalc_rate,
++	.round_rate = ingenic_pll_round_rate,
++	.set_rate = ingenic_v1_pll_set_rate,
++};
++
++static void __init _ingenic_clk_register_pll(struct ingenic_clk_provider *ctx,
++				const struct ingenic_pll_clock *pll_clk,
++				void __iomem *base)
++{
++	struct ingenic_clk_pll *pll;
++	struct clk *clk;
++	struct clk_init_data init;
++	int ret, len;
++
++	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
++	if (!pll) {
++		pr_err("%s: could not allocate pll clk %s\n",
++			__func__, pll_clk->dev_name);
++		return;
++	}
++
++	init.name = pll_clk->dev_name;
++//	init.flags = pll_clk->flags;
++	init.parent_names = &pll_clk->parent_name;
++	init.num_parents = 1;
++	init.ops = &ingenic_v1_pll_clk_ops;
++
++
++	pll->hw.init = &init;
++	pll->hwdesc = pll_clk->hwdesc;
++	pll->con_reg = base + pll_clk->hwdesc->regoff;
++
++	if (pll_clk->rate_table) {
++		/* find count of rates in rate_table */
++		for (len = 0; pll_clk->rate_table[len].rate != 0; )
++			len++;
++
++		pll->rate_count = len - 1;
++		pll->rate_table = kmemdup(pll_clk->rate_table,
++				pll->rate_count *
++				sizeof(struct ingenic_pll_rate_table),
++				GFP_KERNEL);
++		WARN(!pll->rate_table,
++				"%s: could not allocate rate table for %s\n",
++				__func__, pll_clk->name);
++	}
++
++
++
++	clk = clk_register(NULL, &pll->hw);
++	if (IS_ERR(clk)) {
++		pr_err("%s: failed to register pll clock %s : %ld\n",
++			__func__, pll_clk->dev_name, PTR_ERR(clk));
++		kfree(pll);
++		return;
++	}
++
++	ingenic_clk_add_lookup(ctx, clk, pll_clk->id);
++
++
++	ret = clk_register_clkdev(clk, pll_clk->dev_name, NULL);
++	if (ret)
++		pr_err("%s: failed to register lookup for %s : %d",
++			__func__, pll_clk->dev_name, ret);
++}
++
++void __init ingenic_clk_register_pll(struct ingenic_clk_provider *ctx,
++			const struct ingenic_pll_clock *pll_list,
++			unsigned int nr_pll, void __iomem *base)
++{
++	int cnt;
++
++	for (cnt = 0; cnt < nr_pll; cnt++)
++		_ingenic_clk_register_pll(ctx, &pll_list[cnt], base);
++}
+diff --git a/module_drivers/drivers/clk/ingenic-v2/clk-pll-v1.h b/module_drivers/drivers/clk/ingenic-v2/clk-pll-v1.h
+new file mode 100644
+index 000000000..32c77cab6
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/clk-pll-v1.h
+@@ -0,0 +1,53 @@
++#ifndef __INGENIC_CLK_PLLV_H__
++#define __INGENIC_CLK_PLLV_H__
++
++
++extern const struct clk_ops ingenic_pll_ro_ops;
++
++static const s8 pll_od_encode[7] = {-1, 2, 4, 8, 16, 32, 64};
++
++#define PLL_RATE(_rate, _fd, _rd, _od)	\
++{					\
++	.rate = _rate,			\
++	.fd = _fd,			\
++	.rd = _rd,			\
++	.od = _od,			\
++}
++
++struct ingenic_pll_rate_table {
++	unsigned int rate;
++	unsigned int fd;
++	unsigned int rd;
++	unsigned int od;
++};
++
++
++
++#define PLL_DESC(_regoff, _fd, _fd_w, _rd, _rd_w, _od, _od_w, _on, _en, _od_code)	\
++{				\
++	.regoff = _regoff,	\
++	.fd_sft = _fd,		\
++	.fd_width = _fd_w,	\
++	.rd_sft = _rd,		\
++	.rd_width = _rd_w,	\
++	.od_sft = _od,		\
++	.od_width = _od_w,	\
++	.od_encode = _od_code,	\
++	.on_bit = _on,		\
++	.en_bit =  _en,		\
++}
++
++struct ingenic_pll_hwdesc {
++	u32 regoff;
++	u8 fd_sft;
++	u8 fd_width;
++	u8 rd_sft;
++	u8 rd_width;
++	u8 od_sft;
++	u8 od_width;
++	u8 on_bit;
++	u8 en_bit;
++	const s8 *od_encode;		/*od rules, -1 not support*/
++};
++
++#endif /*__INGENIC_CLK_PLLV1_H__*/
+diff --git a/module_drivers/drivers/clk/ingenic-v2/clk-pll-v2.c b/module_drivers/drivers/clk/ingenic-v2/clk-pll-v2.c
+new file mode 100644
+index 000000000..1503a3443
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/clk-pll-v2.c
+@@ -0,0 +1,181 @@
++#include <linux/err.h>
++#include <linux/hrtimer.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/clkdev.h>
++#include "clk.h"
++#include "clk-pll-v2.h"
++
++#define PLL_TIMEOUT_MS		10
++
++struct ingenic_clk_pll {
++	struct clk_hw		hw;
++	void __iomem		*lock_reg;
++	void __iomem		*con_reg;
++	unsigned int		rate_count;
++
++	struct ingenic_pll_hwdesc *hwdesc;
++	struct ingenic_pll_rate_table *rate_table;
++
++};
++
++#define to_clk_pll(_hw) container_of(_hw, struct ingenic_clk_pll, hw)
++
++
++
++static long ingenic_pll_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate)
++{
++	struct ingenic_clk_pll *pll = to_clk_pll(hw);
++	const struct ingenic_pll_rate_table *rate_table = pll->rate_table;
++	int i;
++	unsigned int rate;
++
++	for (i = 0; i < pll->rate_count; i++) {
++		if (drate >= rate_table[i].rate)
++			return  rate_table[i].rate;
++	}
++
++	return rate_table[i - 1].rate;
++
++
++}
++
++
++static unsigned long ingenic_v2_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++	struct ingenic_clk_pll *pll = to_clk_pll(hw);
++	unsigned int val;
++	unsigned int m, n, od0, od1;
++	unsigned long fout;
++
++
++	val = readl(pll->con_reg);
++
++	m = (val >> pll->hwdesc->m_sft) & ((1 << pll->hwdesc->m_width) - 1);
++	n = (val >> pll->hwdesc->n_sft) & ((1 << pll->hwdesc->n_width) - 1);
++	od0 = (val >> pll->hwdesc->od0_sft) & ((1 << pll->hwdesc->od0_width) - 1);
++	od1 = (val >> pll->hwdesc->od1_sft) & ((1 << pll->hwdesc->od1_width) - 1);
++
++
++	fout = parent_rate / (od1 * od0) / n * m;
++
++	return fout;
++}
++
++static int wait_pll_stable(void __iomem *reg, u32 shift)
++{
++	unsigned int timeout = 0xffff;
++
++	while ((!((readl(reg) >> shift) & 1)) && --timeout);
++	if (!timeout) {
++		printk("WARNING : why cannot wait pll stable ???\n");
++		return -ETIMEDOUT;
++	} else {
++		return 0;
++	}
++}
++
++static int ingenic_v2_pll_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate)
++{
++	struct ingenic_clk_pll *pll = to_clk_pll(hw);
++
++	unsigned int m, n, od0, od1;
++	unsigned int val, i;
++
++	for (i = 0; i < pll->rate_count; i++) {
++		if (drate == pll->rate_table[i].rate) {
++			m = pll->rate_table[i].m;
++			n = pll->rate_table[i].n;
++			od0 = pll->rate_table[i].od0;
++			od1 = pll->rate_table[i].od1;
++		}
++	}
++
++
++
++	writel(0, pll->con_reg);
++	val = (m << pll->hwdesc->m_sft) | (n << pll->hwdesc->n_sft) | (od0 << pll->hwdesc->od0_sft) | (od1 << pll->hwdesc->od1_sft) | 1;
++	writel(val, pll->con_reg);
++
++	wait_pll_stable(pll->con_reg, pll->hwdesc->on_bit);
++
++	return 0;
++}
++
++
++static const struct clk_ops ingenic_v2_pll_clk_ops = {
++	.recalc_rate = ingenic_v2_pll_recalc_rate,
++	.round_rate = ingenic_pll_round_rate,
++	.set_rate = ingenic_v2_pll_set_rate,
++};
++
++static void __init _ingenic_clk_register_pll(struct ingenic_clk_provider *ctx,
++				const struct ingenic_pll_clock *pll_clk,
++				void __iomem *base)
++{
++	struct ingenic_clk_pll *pll;
++	struct clk *clk;
++	struct clk_init_data init;
++	int ret, len;
++
++	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
++	if (!pll) {
++		pr_err("%s: could not allocate pll clk %s\n",
++			__func__, pll_clk->dev_name);
++		return;
++	}
++
++	init.name = pll_clk->dev_name;
++//	init.flags = pll_clk->flags;
++	init.parent_names = &pll_clk->parent_name;
++	init.num_parents = 1;
++	init.ops = &ingenic_v2_pll_clk_ops;
++
++
++	pll->hw.init = &init;
++	pll->hwdesc = pll_clk->hwdesc;
++	pll->con_reg = base + pll_clk->hwdesc->regoff;
++
++	if (pll_clk->rate_table) {
++		/* find count of rates in rate_table */
++		for (len = 0; pll_clk->rate_table[len].rate != 0; )
++			len++;
++
++		pll->rate_count = len - 1;
++		pll->rate_table = kmemdup(pll_clk->rate_table,
++				pll->rate_count *
++				sizeof(struct ingenic_pll_rate_table),
++				GFP_KERNEL);
++		WARN(!pll->rate_table,
++				"%s: could not allocate rate table for %s\n",
++				__func__, pll_clk->name);
++	}
++
++
++
++	clk = clk_register(NULL, &pll->hw);
++	if (IS_ERR(clk)) {
++		pr_err("%s: failed to register pll clock %s : %ld\n",
++			__func__, pll_clk->dev_name, PTR_ERR(clk));
++		kfree(pll);
++		return;
++	}
++
++	ingenic_clk_add_lookup(ctx, clk, pll_clk->id);
++
++
++	ret = clk_register_clkdev(clk, pll_clk->dev_name, NULL);
++	if (ret)
++		pr_err("%s: failed to register lookup for %s : %d",
++			__func__, pll_clk->dev_name, ret);
++}
++
++void __init ingenic_clk_register_pll(struct ingenic_clk_provider *ctx,
++			const struct ingenic_pll_clock *pll_list,
++			unsigned int nr_pll, void __iomem *base)
++{
++	int cnt;
++
++	for (cnt = 0; cnt < nr_pll; cnt++)
++		_ingenic_clk_register_pll(ctx, &pll_list[cnt], base);
++}
+diff --git a/module_drivers/drivers/clk/ingenic-v2/clk-pll-v2.h b/module_drivers/drivers/clk/ingenic-v2/clk-pll-v2.h
+new file mode 100644
+index 000000000..80c037c6e
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/clk-pll-v2.h
+@@ -0,0 +1,53 @@
++#ifndef __INGENIC_CLK_PLLV_H__
++#define __INGENIC_CLK_PLLV_H__
++
++
++extern const struct clk_ops ingenic_pll_ro_ops;
++
++#define PLL_RATE(_rate, _m, _n, _od1, _od0)	\
++{					\
++	.rate = _rate,			\
++	.m = _m,			\
++	.n = _n,			\
++	.od1 = _od1,			\
++	.od0 = _od0,			\
++}
++
++struct ingenic_pll_rate_table {
++	unsigned int rate;
++	unsigned int m;
++	unsigned int n;
++	unsigned int od1;
++	unsigned int od0;
++};
++
++#define PLL_DESC(_regoff, _m, _m_w, _n, _n_w, _od1, _od1_w, _od0, _od0_w, _on, _en)	\
++{				\
++	.regoff = _regoff,	\
++	.m_sft = _m,		\
++	.m_width = _m_w,	\
++	.n_sft = _n,		\
++	.n_width = _n_w,	\
++	.od1_sft = _od1,		\
++	.od1_width = _od1_w,	\
++	.od0_sft = _od0,		\
++	.od0_width = _od0_w,	\
++	.on_bit = _on,		\
++	.en_bit =  _en,		\
++}
++
++struct ingenic_pll_hwdesc {
++	u32 regoff;
++	u8 m_sft;
++	u8 m_width;
++	u8 n_sft;
++	u8 n_width;
++	u8 od1_sft;
++	u8 od1_width;
++	u8 od0_sft;
++	u8 od0_width;
++	u8 on_bit;
++	u8 en_bit;
++};
++
++#endif /*__INGENIC_CLK_PLLV1_H__*/
+diff --git a/module_drivers/drivers/clk/ingenic-v2/clk-pll.c b/module_drivers/drivers/clk/ingenic-v2/clk-pll.c
+new file mode 100644
+index 000000000..7e440eb59
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/clk-pll.c
+@@ -0,0 +1,185 @@
++#include <linux/errno.h>
++#include <linux/hrtimer.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/clkdev.h>
++#include "clk.h"
++#include "clk-pll.h"
++
++#define PLL_TIMEOUT_MS		10
++
++struct ingenic_clk_pll {
++	struct clk_hw		hw;
++	void __iomem		*lock_reg;
++	void __iomem		*con_reg;
++	unsigned int		rate_count;
++
++	struct ingenic_pll_hwdesc *hwdesc;
++	struct ingenic_pll_rate_table *rate_table;
++
++};
++
++#define to_clk_pll(_hw) container_of(_hw, struct ingenic_clk_pll, hw)
++
++
++
++static long ingenic_pll_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate)
++{
++	struct ingenic_clk_pll *pll = to_clk_pll(hw);
++	const struct ingenic_pll_rate_table *rate_table = pll->rate_table;
++	int i;
++	unsigned int rate;
++
++	for (i = 0; i < pll->rate_count; i++) {
++		if (drate >= rate_table[i].rate)
++			return  rate_table[i].rate;
++	}
++
++	return rate_table[i - 1].rate;
++
++
++}
++
++
++static unsigned long ingenic_x2000_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++{
++	struct ingenic_clk_pll *pll = to_clk_pll(hw);
++	unsigned int val;
++	unsigned int fd, rd, od;
++	unsigned int nf, nr, no;
++	unsigned long fout;
++
++
++	val = readl(pll->con_reg);
++
++	fd = (val >> pll->hwdesc->fd_sft) & ((1 << pll->hwdesc->fd_width) - 1);
++	rd = (val >> pll->hwdesc->rd_sft) & ((1 << pll->hwdesc->rd_width) - 1);
++	od = (val >> pll->hwdesc->od_sft) & ((1 << pll->hwdesc->od_width) - 1);
++
++	nf = 1 + fd;
++	nr = 1 + rd;
++	no = pll_od_encode[od];
++
++	fout = parent_rate / (nr * no) * 2 * nf;
++
++	return fout;
++}
++
++static int wait_pll_stable(void __iomem *reg, u32 shift)
++{
++	unsigned int timeout = 0xffff;
++
++	while ((!((readl(reg) >> shift) & 1)) && timeout--);
++	if (!timeout) {
++		printk("WARNING : why cannot wait pll stable ???\n");
++		return -EIO;
++	} else {
++		return 0;
++	}
++}
++
++static int ingenic_x2000_pll_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate)
++{
++	struct ingenic_clk_pll *pll = to_clk_pll(hw);
++
++	unsigned int fd;
++	unsigned int rd;
++	unsigned int od;
++	unsigned int val, i;
++
++	for (i = 0; i < pll->rate_count; i++) {
++		if (drate == pll->rate_table[i].rate) {
++			fd = pll->rate_table[i].fd;
++			rd = pll->rate_table[i].rd;
++			od = pll->rate_table[i].od;
++		}
++	}
++
++
++
++	writel(0, pll->con_reg);
++	val = (fd << pll->hwdesc->fd_sft) | (rd << pll->hwdesc->rd_sft) | (od << pll->hwdesc->od_sft) | 1;
++	writel(val, pll->con_reg);
++
++	wait_pll_stable(pll->con_reg, pll->hwdesc->on_bit);
++
++	return 0;
++}
++
++
++static const struct clk_ops ingenic_x2000_pll_clk_ops = {
++	.recalc_rate = ingenic_x2000_pll_recalc_rate,
++	.round_rate = ingenic_pll_round_rate,
++	.set_rate = ingenic_x2000_pll_set_rate,
++};
++
++static void __init _ingenic_clk_register_pll(struct ingenic_clk_provider *ctx,
++				const struct ingenic_pll_clock *pll_clk,
++				void __iomem *base)
++{
++	struct ingenic_clk_pll *pll;
++	struct clk *clk;
++	struct clk_init_data init;
++	int ret, len;
++
++	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
++	if (!pll) {
++		pr_err("%s: could not allocate pll clk %s\n",
++			__func__, pll_clk->dev_name);
++		return;
++	}
++
++	init.name = pll_clk->dev_name;
++//	init.flags = pll_clk->flags;
++	init.parent_names = &pll_clk->parent_name;
++	init.num_parents = 1;
++	init.ops = &ingenic_x2000_pll_clk_ops;
++
++
++	pll->hw.init = &init;
++	pll->hwdesc = pll_clk->hwdesc;
++	pll->con_reg = base + pll_clk->hwdesc->regoff;
++
++	if (pll_clk->rate_table) {
++		/* find count of rates in rate_table */
++		for (len = 0; pll_clk->rate_table[len].rate != 0; )
++			len++;
++
++		pll->rate_count = len - 1;
++		pll->rate_table = kmemdup(pll_clk->rate_table,
++				pll->rate_count *
++				sizeof(struct ingenic_pll_rate_table),
++				GFP_KERNEL);
++		WARN(!pll->rate_table,
++				"%s: could not allocate rate table for %s\n",
++				__func__, pll_clk->name);
++	}
++
++
++
++	clk = clk_register(NULL, &pll->hw);
++	if (IS_ERR(clk)) {
++		pr_err("%s: failed to register pll clock %s : %ld\n",
++			__func__, pll_clk->dev_name, PTR_ERR(clk));
++		kfree(pll);
++		return;
++	}
++
++	ingenic_clk_add_lookup(ctx, clk, pll_clk->id);
++
++
++	ret = clk_register_clkdev(clk, pll_clk->dev_name, NULL);
++	if (ret)
++		pr_err("%s: failed to register lookup for %s : %d",
++			__func__, pll_clk->dev_name, ret);
++}
++
++void __init ingenic_clk_register_pll(struct ingenic_clk_provider *ctx,
++			const struct ingenic_pll_clock *pll_list,
++			unsigned int nr_pll, void __iomem *base)
++{
++	int cnt;
++
++	for (cnt = 0; cnt < nr_pll; cnt++)
++		_ingenic_clk_register_pll(ctx, &pll_list[cnt], base);
++}
+diff --git a/module_drivers/drivers/clk/ingenic-v2/clk-pll.h b/module_drivers/drivers/clk/ingenic-v2/clk-pll.h
+new file mode 100644
+index 000000000..c55824756
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/clk-pll.h
+@@ -0,0 +1,11 @@
++
++#ifdef CLK_PLL_V1
++#include "clk-pll-v1.h"
++#endif
++
++#ifdef CLK_PLL_V2
++#include "clk-pll-v2.h"
++#endif
++
++
++
+diff --git a/module_drivers/drivers/clk/ingenic-v2/clk-x1600.c b/module_drivers/drivers/clk/ingenic-v2/clk-x1600.c
+new file mode 100644
+index 000000000..7923422ee
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/clk-x1600.c
+@@ -0,0 +1,306 @@
++#include <linux/slab.h>
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/syscore_ops.h>
++#include <linux/clk.h>
++
++#include <dt-bindings/clock/ingenic-x1600.h>
++
++#include "clk.h"
++
++
++
++/*******************************************************************************
++ *      FIXED CLK
++ ********************************************************************************/
++static struct ingenic_fixed_rate_clock x1600_fixed_rate_ext_clks[] __initdata = {
++	FRATE(CLK_EXT, "ext", NULL, 0, 24000000),
++	FRATE(CLK_RTC_EXT, "rtc_ext", NULL, 0, 32768),
++	FRATE(CLK_EXT_DIV_512, "ext_div_512", NULL, 0, 46875),
++};
++
++
++
++/*******************************************************************************
++ *      PLL
++ ********************************************************************************/
++
++static struct ingenic_pll_rate_table x1600_pll_rate_table[] = {
++	PLL_RATE(1000000000, 125, 3, 1, 1),
++	PLL_RATE(900000000, 75, 1, 2, 1),
++	PLL_RATE(800000000, 100, 1, 3, 1),
++	PLL_RATE(700000000, 175, 2, 3, 1),
++	PLL_RATE(600000000, 25, 1, 1, 1),
++	PLL_RATE(500000000, 125, 2, 3, 1),
++	PLL_RATE(400000000, 50, 1, 3, 1),
++};
++
++
++
++/*PLL HWDESC*/
++static struct ingenic_pll_hwdesc apll_hwdesc = \
++	PLL_DESC(CPM_CPAPCR, 20,12, 14, 6, 11, 3, 8, 3, 3, 0);
++
++static struct ingenic_pll_hwdesc mpll_hwdesc = \
++	PLL_DESC(CPM_CPMPCR, 20,12, 14, 6, 11, 3, 8, 3, 3, 0);
++
++static struct ingenic_pll_hwdesc epll_hwdesc = \
++	PLL_DESC(CPM_CPEPCR, 20,12, 14, 6, 11, 3, 8, 3, 3, 0);
++
++
++
++static struct ingenic_pll_clock x1600_pll_clks[] __initdata = {
++	PLL(CLK_PLL_APLL, "apll", "ext", &apll_hwdesc, x1600_pll_rate_table),
++	PLL(CLK_PLL_MPLL, "mpll", "ext", &mpll_hwdesc, x1600_pll_rate_table),
++	PLL(CLK_PLL_EPLL, "epll", "ext", &epll_hwdesc, x1600_pll_rate_table),
++};
++
++
++/*******************************************************************************
++ *      MUX
++ ********************************************************************************/
++PNAME(mux_table_0)	= {"stop",	"ext",		"apll"};
++PNAME(mux_table_1)	= {"stop",	"sclka",	"mpll"};
++PNAME(mux_table_2)	= {"sclka",	"mpll",		"epll"};
++PNAME(mux_table_3)	= {"sclka", 	"mpll",		"epll",		"ext"};
++PNAME(mux_table_4)	= {"sclka", 	"epll"};
++PNAME(mux_table_5)	= {"ext_div_512", 	"rtc_ext"};
++
++static unsigned int ingenic_mux_table[] = {0, 1, 2, 3, 4};
++
++
++static struct ingenic_mux_clock x1600_mux_clks[] __initdata = {
++	MUX(CLK_MUX_SCLKA,	"sclka",		ingenic_mux_table, mux_table_0, CPM_CPCCR,	30, 2, 0),
++	MUX(CLK_MUX_CPU_L2C,	"mux_cpu_l2c",		ingenic_mux_table, mux_table_1, CPM_CPCCR,	28, 2, 0),
++	MUX(CLK_MUX_AHB0,	"mux_ahb0",		ingenic_mux_table, mux_table_1, CPM_CPCCR,	26, 2, 0),
++	MUX(CLK_MUX_AHB2,	"mux_ahb2",		ingenic_mux_table, mux_table_1, CPM_CPCCR,	24, 2, 0),
++
++	MUX(CLK_MUX_DDR,	"mux_ddr",		ingenic_mux_table, mux_table_1, CPM_DDRCDR,	30, 2, 0),
++	MUX(CLK_MUX_MACPHY,	"mux_macphy",		ingenic_mux_table, mux_table_2, CPM_MACPHYCDR,	30, 2, 0),
++	MUX(CLK_MUX_I2S0T,	"mux_i2s0t",		ingenic_mux_table, mux_table_4, CPM_I2SCDR1,	30, 1, 0),
++	MUX(CLK_MUX_I2S0R,	"mux_i2s0r",		ingenic_mux_table, mux_table_4, CPM_I2SCDR,	30, 1, 0),
++	MUX(CLK_MUX_LCD,	"mux_lcd",		ingenic_mux_table, mux_table_2, CPM_LPCDR,	30, 2, 0),
++	MUX(CLK_MUX_MSC0,	"mux_msc0",		ingenic_mux_table, mux_table_2, CPM_MSC0CDR,	30, 2, 0),
++	MUX(CLK_MUX_MSC1,	"mux_msc1",		ingenic_mux_table, mux_table_2, CPM_MSC1CDR,	30, 2, 0),
++	MUX(CLK_MUX_SFC,	"mux_sfc",		ingenic_mux_table, mux_table_2, CPM_SFCCDR,	30, 2, 0),
++	MUX(CLK_MUX_SSI,	"mux_ssi",		ingenic_mux_table, mux_table_2, CPM_SSICDR,	30, 2, 0),
++	MUX(CLK_MUX_CIM,	"mux_cim",		ingenic_mux_table, mux_table_2, CPM_CIMCDR,	30, 2, 0),
++	MUX(CLK_MUX_PWM,	"mux_pwm",		ingenic_mux_table, mux_table_2, CPM_PWMCDR,	30, 2, 0),
++	MUX(CLK_MUX_CAN0,	"mux_can0",		ingenic_mux_table, mux_table_3, CPM_CAN0CDR,	30, 2, 0),
++	MUX(CLK_MUX_CAN1,	"mux_can1",		ingenic_mux_table, mux_table_3, CPM_CAN1CDR,	30, 2, 0),
++	MUX(CLK_MUX_CDBUS,	"mux_cdbus",		ingenic_mux_table, mux_table_2, CPM_CDBUSCDR,	30, 2, 0),
++	MUX(CLK_MUX_WDT,	"mux_wdt",		ingenic_mux_table, mux_table_5, CPM_OPCR,	2, 1, 0),
++
++};
++
++/*******************************************************************************
++ *      DIV BUS
++ ********************************************************************************/
++
++static struct ingenic_bus_clock x1600_bus_div_clks[] __initdata = {
++	BUS_DIV(CLK_DIV_CPU,		"div_cpu",		"mux_cpu_l2c",		CPM_CPCCR,	0,  4, 0, 0, CPM_CPCSR, 0, 22, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_L2C,		"div_l2c",		"mux_cpu_l2c",		CPM_CPCCR,	4,  4, 0, 0, CPM_CPCSR, 0, 22, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_AHB0,		"div_ahb0",		"mux_ahb0",		CPM_CPCCR,	8,  4, 0, 0, CPM_CPCSR, 1, 21, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_AHB2,		"div_ahb2",		"mux_ahb2",		CPM_CPCCR,	12, 4, 0, 0, CPM_CPCSR, 2, 20, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_APB,		"div_apb",		"mux_ahb2",		CPM_CPCCR,	16, 4, 0, 0, CPM_CPCSR, 2, 20, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_CPU_L2C_X1,	"div_cpu_l2c_x1",	"mux_cpu_l2c",		CPM_CPCCR,	0,  4, 4, 4, CPM_CPCSR, 0, 22, BUS_DIV_ONE),
++	BUS_DIV(CLK_DIV_CPU_L2C_X2,	"div_cpu_l2c_x2",	"mux_cpu_l2c",		CPM_CPCCR,	0,  4, 4, 4, CPM_CPCSR, 0, 22, BUS_DIV_TWO),
++};
++
++
++/*******************************************************************************
++ *      DIV
++ ********************************************************************************/
++
++static struct clk_div_table x1600_clk_div_table[256] = {};
++
++static struct ingenic_div_clock x1600_div_clks[] __initdata = {
++	DIV(CLK_DIV_DDR,		"div_ddr",		"mux_ddr",		CPM_DDRCDR,	4,  0, NULL),
++	DIV(CLK_DIV_MACPHY,		"div_macphy",		"mux_macphy",		CPM_MACPHYCDR,	8,  0, NULL),
++	DIV(CLK_DIV_LCD,		"div_lcd",		"mux_lcd",		CPM_LPCDR,	8,  0, NULL),
++	DIV(CLK_DIV_MSC0,		"div_msc0",		"mux_msc0",		CPM_MSC0CDR,	8,  0, x1600_clk_div_table),
++	DIV(CLK_DIV_MSC1,		"div_msc1",		"mux_msc1",		CPM_MSC1CDR,	8,  0, x1600_clk_div_table),
++	DIV(CLK_DIV_SFC,		"div_sfc",		"mux_sfc",		CPM_SFCCDR,	8,  0, NULL),
++	DIV(CLK_DIV_SSI,		"div_ssi",		"mux_ssi",		CPM_SSICDR,	8,  0, NULL),
++	DIV(CLK_DIV_CIM,		"div_cim",		"mux_cim",		CPM_CIMCDR,	8,  0, NULL),
++	DIV(CLK_DIV_PWM,		"div_pwm",		"mux_pwm",		CPM_PWMCDR,	4,  0, NULL),
++	DIV(CLK_DIV_CAN0,		"div_can0",		"mux_can0",		CPM_CAN0CDR,	8,  0, NULL),
++	DIV(CLK_DIV_CAN1,		"div_can1",		"mux_can1",		CPM_CAN1CDR,	8,  0, NULL),
++	DIV(CLK_DIV_CDBUS,		"div_cdbus",		"mux_cdbus",		CPM_CDBUSCDR,	8,  0, NULL),
++
++};
++
++/*******************************************************************************
++ *      FRACTIONAL-DIVIDER
++ ********************************************************************************/
++
++static struct ingenic_fra_div_clock x1600_fdiv_clks[] __initdata = {
++	FRA_DIV(CLK_DIV_I2S0R,	"div_i2s0r",	"mux_i2s0r",	CPM_I2SCDR,	20, 9, 0, 20),
++	FRA_DIV(CLK_DIV_I2S0T,	"div_i2s0t",	"mux_i2s0t",	CPM_I2SCDR1,	20, 9, 0, 20),
++};
++
++/*******************************************************************************
++ *      GATE
++ ********************************************************************************/
++static struct ingenic_gate_clock x1600_gate_clks[] __initdata = {
++
++	GATE(CLK_GATE_DDR,	"gate_ddr",		"div_ddr",	CPM_CLKGR,  31, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_AHB0,	"gate_ahb0",		"div_ahb0",	CPM_CLKGR,  29, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_APB0,	"gate_apb0",		"div_ahb0",	CPM_CLKGR,  28, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_RTC,	"gate_rtc",		"rtc_ext",	CPM_CLKGR,  27, 0,			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_AES,	"gate_aes",		"div_ahb2",	CPM_CLKGR,  24, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_LCD,	"gate_lcd",		"div_lcd",	CPM_CLKGR,  23, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_CIM,	"gate_cim",		"div_cim",	CPM_CLKGR,  22, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_PDMA,	"gate_pdma",		"div_ahb2",	CPM_CLKGR,  21, CLK_IGNORE_UNUSED, 	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_OST,	"gate_ost",		"ext",		CPM_CLKGR,  20, CLK_IGNORE_UNUSED, 	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SSI0,	"gate_ssi0",		"div_ssi",	CPM_CLKGR,  19, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_TCU,	"gate_tcu",		"div_apb",	CPM_CLKGR,  18, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_DTRNG,	"gate_dtrng",		"div_apb",	CPM_CLKGR,  17, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART2,	"gate_uart2",		"div_apb",	CPM_CLKGR,  16, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART1,	"gate_uart1",		"div_apb",	CPM_CLKGR,  15, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART0,	"gate_uart0",		"div_apb",	CPM_CLKGR,  14, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SADC,	"gate_sadc",		"div_apb",	CPM_CLKGR,  13, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_AUDIO,	"gate_audio",		"div_ahb2",	CPM_CLKGR,  11, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SSISLV,	"gate_ssislv",		"div_apb",	CPM_CLKGR,  10, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB1,	"gate_i2c1",		"div_apb",	CPM_CLKGR,  8,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB0,	"gate_i2c0",		"div_apb",	CPM_CLKGR,  7,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_MSC1,	"gate_msc1",		"div_msc1",	CPM_CLKGR,  5,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_MSC0,	"gate_msc0",		"div_msc0",	CPM_CLKGR,  4,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_OTG,	"gate_otg",		"div_ahb2",	CPM_CLKGR,  3,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SFC,	"gate_sfc",		"div_sfc",	CPM_CLKGR,  2,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_EFUSE,	"gate_efuse",		"div_ahb2",	CPM_CLKGR,  1,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_NEMC,	"gate_nemc",		"div_ahb2",	CPM_CLKGR,  0,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_ARB,	"gate_arb",		"div_ahb0",	CPM_CLKGR1, 30, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_MIPI_CSI, "gate_csi",		"div_ahb0",	CPM_CLKGR1, 28, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_INTC,	"gate_intc",		"div_ahb2",	CPM_CLKGR1, 26, CLK_IGNORE_UNUSED, 	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_GMAC0,	"gate_gmac0",		"div_ahb2",	CPM_CLKGR1, 23, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART3,	"gate_uart3",		"div_apb",	CPM_CLKGR1, 16, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_I2S0T,	"gate_i2s0t",		"div_i2s0t",	CPM_CLKGR1, 9,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_I2S0R,	"gate_i2s0r",		"div_i2s0r",	CPM_CLKGR1, 8,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_HASH,	"gate_hash",		"div_ahb2",	CPM_CLKGR1, 6,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_PWM,	"gate_pwm",		"div_pwm",	CPM_CLKGR1, 5,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_CDBUS,	"gate_cdbus",		"div_apb",	CPM_CLKGR1, 2,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_CAN1,	"gate_can1",		"div_apb",	CPM_CLKGR1, 1,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_CAN0,	"gate_can0",		"div_apb",	CPM_CLKGR1, 0,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_USBPHY,	"gate_usbphy",		"div_apb",	CPM_OPCR,   23, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_CE_I2S0T,	"ce_i2s0t",		"div_i2s0t",	CPM_I2SCDR1, 29, 0, 0),
++	GATE(CLK_CE_I2S0R,	"ce_i2s0r",		"div_i2s0r",	CPM_I2SCDR, 29, 0, 0),
++};
++
++static struct ingenic_gate_power x1600_gate_power[] __initdata = {
++
++	POWER(PD_MEM_CDBUS,	"pd_mem_cdbus",		"gate_cdbus",	CPM_MPDCR0,  29, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_PWM,	"pd_mem_pwm",		"gate_cdbus",	CPM_MPDCR0,  26, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_GMAC,	"pd_mem_gmac",		"gate_cdbus",	CPM_MPDCR0,  25, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_USB,	"pd_mem_usb",		"gate_usb",	CPM_MPDCR0,  24, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_SFC,	"pd_mem_sfc",		"gate_sfc",	CPM_MPDCR0,  23, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_MSC1,	"pd_mem_msc1",		"gate_msc1",	CPM_MPDCR0,  22, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_MSC0,	"pd_mem_msc0",		"gate_msc0",	CPM_MPDCR0,  21, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_AES,	"pd_mem_aes",		"gate_aes",	CPM_MPDCR0,  20, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_PDMA_SLP,	"pd_mem_pdma_slp",	"gate_pdma",	CPM_MPDCR0,  19, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_PDMA_SEC,	"pd_mem_pdma_sec",	"gate_pdma",	CPM_MPDCR0,  18, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_PDMA,	"pd_mem_pdma",		"gate_pdma",	CPM_MPDCR0,  17, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_NEMC,	"pd_mem_nemc",		"gate_nemc",	CPM_MPDCR0,  16, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_AIC,	"pd_mem_aic",		"gate_audio",	CPM_MPDCR0,  6,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_SSISLV,	"pd_mem_ssislv",	"gate_ssislv",	CPM_MPDCR0,  5,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_SSI0,	"pd_mem_ssi0",		"gate_ssi0",	CPM_MPDCR0,  4,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART3,	"pd_mem_uart3",		"gate_uart3",	CPM_MPDCR0,  3,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART2,	"pd_mem_uart2",		"gate_uart2",	CPM_MPDCR0,  2,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART1,	"pd_mem_uart1",		"gate_uart1",	CPM_MPDCR0,  1,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART0,	"pd_mem_uart0",		"gate_uart0",	CPM_MPDCR0,  0,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_CIM,	"pd_mem_cim",		"gate_cim",	CPM_MPDCR1, 5,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DPU,	"pd_mem_dpu",		"gate_dpu",	CPM_MPDCR1, 4,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DDR_CH6,	"pd_mem_ddr_ch6",	"gate_ddr",	CPM_MPDCR1, 3,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DDR_CH5,	"pd_mem_ddr_ch5",	"gate_ddr",	CPM_MPDCR1, 2,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DDR_CH3,	"pd_mem_ddr_ch3",	"gate_ddr",	CPM_MPDCR1, 1,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DDR_TOP,	"pd_mem_ddr_top",	"gate_ddr",	CPM_MPDCR1, 0,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++
++};
++
++static void clk_div_table_generate(void)
++{
++	int i;
++	for (i = 0; i < ARRAY_SIZE(x1600_clk_div_table); i++) {
++		x1600_clk_div_table[i].val = i;
++		x1600_clk_div_table[i].div = (i + 1) * 2;
++	}
++
++}
++
++static const struct of_device_id ext_clk_match[] __initconst = {
++	        { .compatible = "ingenic,fixed-clock", .data = (void *)0, },
++		{},
++};
++
++
++/* Register x1600 clocks. */
++static void __init x1600_clk_init(struct device_node *np, void __iomem *base)
++{
++	struct ingenic_clk_provider *ctx;
++	void __iomem *reg_base;
++
++
++	printk("x1600 Clock Power Management Unit init!\n");
++
++	reg_base = base;
++
++	if (np) {
++		reg_base = of_iomap(np, 0);
++		if (!reg_base)
++			panic("%s: failed to map registers\n", __func__);
++	}
++
++
++	ctx = ingenic_clk_init(np, reg_base, NR_CLKS);
++	if (!ctx)
++		panic("%s: unable to allocate context.\n", __func__);
++
++	/* Register Ext Clocks From DT */
++	ingenic_clk_of_register_fixed_ext(ctx, x1600_fixed_rate_ext_clks,
++			                        ARRAY_SIZE(x1600_fixed_rate_ext_clks), ext_clk_match);
++
++	/* Register PLLs. */
++	ingenic_clk_register_pll(ctx, x1600_pll_clks,
++				ARRAY_SIZE(x1600_pll_clks), reg_base);
++
++
++	/* Register Muxs */
++	ingenic_clk_register_mux(ctx, x1600_mux_clks, ARRAY_SIZE(x1600_mux_clks));
++
++	/* Register Bus Divs */
++	ingenic_clk_register_bus_div(ctx, x1600_bus_div_clks, ARRAY_SIZE(x1600_bus_div_clks));
++
++	/* Register Divs */
++	clk_div_table_generate();
++	ingenic_clk_register_cgu_div(ctx, x1600_div_clks, ARRAY_SIZE(x1600_div_clks));
++
++	/* Register Fractional Divs */
++	ingenic_clk_register_fra_div(ctx, x1600_fdiv_clks, ARRAY_SIZE(x1600_fdiv_clks));
++
++	/* Register Gates */
++	ingenic_clk_register_gate(ctx, x1600_gate_clks, ARRAY_SIZE(x1600_gate_clks));
++
++	/* Register Powers */
++	ingenic_power_register_gate(ctx, x1600_gate_power, ARRAY_SIZE(x1600_gate_power));
++
++	ingenic_clk_of_add_provider(np, ctx);
++
++
++	//ingenic_clk_of_dump(ctx);
++
++
++	pr_info("=========== x1600 clocks: =============\n"
++		"\tapll     = %lu , mpll     = %lu, ddr = %lu\n"
++		"\tcpu_clk  = %lu , l2c_clk  = %lu\n"
++		"\tahb0_clk = %lu , ahb2_clk = %lu\n"
++		"\tapb_clk  = %lu , ext_clk  = %lu\n\n",
++		_get_rate("apll"),	_get_rate("mpll"), _get_rate("div_ddr"),
++		_get_rate("div_cpu"), _get_rate("div_l2c"),
++		_get_rate("div_ahb0"), _get_rate("div_ahb2"),
++		_get_rate("div_apb"), _get_rate("ext"));
++
++}
++
++CLK_OF_DECLARE(x1600_clk, "ingenic,x1600-clocks", x1600_clk_init);
++
+diff --git a/module_drivers/drivers/clk/ingenic-v2/clk-x2000.c b/module_drivers/drivers/clk/ingenic-v2/clk-x2000.c
+new file mode 100644
+index 000000000..d5be8c7e3
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/clk-x2000.c
+@@ -0,0 +1,361 @@
++#include <linux/slab.h>
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/syscore_ops.h>
++#include <linux/clk.h>
++
++#include <dt-bindings/clock/ingenic-x2000.h>
++
++#include "clk.h"
++#include "clk-pll-v1.h"
++
++
++/*******************************************************************************
++ *      FIXED CLK
++ ********************************************************************************/
++static struct ingenic_fixed_rate_clock x2000_fixed_rate_ext_clks[] __initdata = {
++	FRATE(CLK_EXT, "ext", NULL, 0, 24000000),
++	FRATE(CLK_RTC_EXT, "rtc_ext", NULL, 0, 32768),
++	FRATE(CLK_EXT_DIV_512, "ext_div_512", NULL,0, 46875),
++};
++
++
++
++/*******************************************************************************
++ *      PLL
++ ********************************************************************************/
++
++static struct ingenic_pll_rate_table x2000_pll_rate_table[] = {
++	PLL_RATE(1500000000, 124, 1, 1),
++	PLL_RATE(1200000000, 49, 0, 1),
++	PLL_RATE(800000000, 199, 2, 2),
++	PLL_RATE(600000000, 49, 0, 2),
++	PLL_RATE(300000000, 49, 0, 3),
++};
++
++
++
++/*PLL HWDESC*/
++static struct ingenic_pll_hwdesc apll_hwdesc = \
++	PLL_DESC(CPM_CPAPCR, 20, 9, 14, 6, 11, 3, 3, 0, pll_od_encode);
++
++static struct ingenic_pll_hwdesc mpll_hwdesc = \
++	PLL_DESC(CPM_CPMPCR, 20, 9, 14, 6, 11, 3, 3, 0, pll_od_encode);
++
++static struct ingenic_pll_hwdesc epll_hwdesc = \
++	PLL_DESC(CPM_CPEPCR, 20, 9, 14, 6, 11, 3, 3, 0, pll_od_encode);
++
++
++
++static struct ingenic_pll_clock x2000_pll_clks[] __initdata = {
++	PLL(CLK_PLL_APLL, "apll", "ext", &apll_hwdesc, x2000_pll_rate_table),
++	PLL(CLK_PLL_MPLL, "mpll", "ext", &mpll_hwdesc, x2000_pll_rate_table),
++	PLL(CLK_PLL_EPLL, "epll", "ext", &epll_hwdesc, x2000_pll_rate_table),
++};
++
++
++/*******************************************************************************
++ *      MUX
++ ********************************************************************************/
++PNAME(mux_table_0)	= {"stop",	"ext",		"apll"};
++PNAME(mux_table_1)	= {"stop",	"sclka",	"mpll"};
++PNAME(mux_table_2)	= {"sclka",	"mpll",		"epll"};
++PNAME(mux_table_3)	= {"sclka", 	"mpll",		"ext"};
++PNAME(mux_table_4)	= {"sclka", 	"epll"};
++PNAME(mux_table_5)	= {"mux_ahb2",	"ext"};
++PNAME(mux_table_6)	= {"ext",	"div_i2s3"};
++PNAME(mux_table_7)	= {"div_i2s0",	"div_i2s1",	"div_i2s2",	"div_i2s3"};
++PNAME(mux_table_8)	= {"ext_div_512",	"rtc_ext"};
++
++static unsigned int ingenic_mux_table[] = {0, 1, 2, 3};
++
++
++static struct ingenic_mux_clock x2000_mux_clks[] __initdata = {
++	MUX(CLK_MUX_SCLKA,	"sclka",		ingenic_mux_table, mux_table_0, CPM_CPCCR,	30, 2, 0),
++	MUX(CLK_MUX_CPU_L2C,	"mux_cpu_l2c",		ingenic_mux_table, mux_table_1, CPM_CPCCR,	28, 2, 0),
++	MUX(CLK_MUX_AHB0,	"mux_ahb0",		ingenic_mux_table, mux_table_1, CPM_CPCCR,	26, 2, 0),
++	MUX(CLK_MUX_AHB2,	"mux_ahb2",		ingenic_mux_table, mux_table_1, CPM_CPCCR,	24, 2, 0),
++
++	MUX(CLK_MUX_DDR,	"mux_ddr",		ingenic_mux_table, mux_table_1, CPM_DDRCDR,	30, 2, 0),
++	MUX(CLK_MUX_MACPHY,	"mux_macphy",		ingenic_mux_table, mux_table_2, CPM_MACCDR,	30, 2, 0),
++	MUX(CLK_MUX_MACTXPHY,	"mux_mactxphy",		ingenic_mux_table, mux_table_2, CPM_MACTXCDR,	30, 2, 0),
++	MUX(CLK_MUX_MACTXPHY1,	"mux_mactxphy1",	ingenic_mux_table, mux_table_2, CPM_MACTXCDR1,	30, 2, 0),
++	MUX(CLK_MUX_MACPTP,	"mux_macptp",		ingenic_mux_table, mux_table_2, CPM_MACPTP,	30, 2, 0),
++	MUX(CLK_MUX_I2S0,	"mux_i2s0",		ingenic_mux_table, mux_table_4, CPM_I2S0CDR,	30, 1, 0),
++	MUX(CLK_MUX_I2S1,	"mux_i2s1",		ingenic_mux_table, mux_table_4, CPM_I2S1CDR,	30, 1, 0),
++	MUX(CLK_MUX_I2S2,	"mux_i2s2",		ingenic_mux_table, mux_table_4, CPM_I2S2CDR,	30, 1, 0),
++	MUX(CLK_MUX_I2S3,	"mux_i2s3",		ingenic_mux_table, mux_table_4, CPM_I2S3CDR,	30, 1, 0),
++	MUX(CLK_MUX_AUDIO_RAM,	"mux_audio_ram",	ingenic_mux_table, mux_table_5, CPM_AUDIOCR,	30, 1, 0),
++	MUX(CLK_MUX_SPDIF,	"mux_spdif",		ingenic_mux_table, mux_table_7, CPM_AUDIOCR,	3,  2, CLK_SET_RATE_PARENT|CLK_SET_RATE_NO_REPARENT),
++	MUX(CLK_MUX_PCM,	"mux_pcm",		ingenic_mux_table, mux_table_7, CPM_AUDIOCR,	1,  2, CLK_SET_RATE_PARENT|CLK_SET_RATE_NO_REPARENT),
++	MUX(CLK_MUX_DMIC,	"mux_dmic",		ingenic_mux_table, mux_table_6, CPM_AUDIOCR,	0,  1, CLK_SET_RATE_PARENT|CLK_SET_RATE_NO_REPARENT),
++	MUX(CLK_MUX_LCD,	"mux_lcd",		ingenic_mux_table, mux_table_2, CPM_LPCDR,	30, 2, 0),
++	MUX(CLK_MUX_MSC0,	"mux_msc0",		ingenic_mux_table, mux_table_3, CPM_MSC0CDR,	30, 2, 0),
++	MUX(CLK_MUX_MSC1,	"mux_msc1",		ingenic_mux_table, mux_table_3, CPM_MSC1CDR,	30, 2, 0),
++	MUX(CLK_MUX_MSC2,	"mux_msc2",		ingenic_mux_table, mux_table_3, CPM_MSC2CDR,	30, 2, 0),
++	MUX(CLK_MUX_SFC,	"mux_sfc",		ingenic_mux_table, mux_table_2, CPM_SFCCDR,	30, 2, 0),
++	MUX(CLK_MUX_SSI,	"mux_ssi",		ingenic_mux_table, mux_table_2, CPM_SSICDR,	30, 2, 0),
++	MUX(CLK_MUX_CIM,	"mux_cim",		ingenic_mux_table, mux_table_2, CPM_CIMCDR,	30, 2, 0),
++	MUX(CLK_MUX_PWM,	"mux_pwm",		ingenic_mux_table, mux_table_2, CPM_PWMCDR,	30, 2, 0),
++	MUX(CLK_MUX_ISP,	"mux_isp",		ingenic_mux_table, mux_table_2, CPM_ISPCDR,	30, 2, 0),
++	MUX(CLK_MUX_RSA,	"mux_rsa",		ingenic_mux_table, mux_table_2, CPM_RSACDR,	30, 2, 0),
++	MUX(CLK_MUX_WDT,	"mux_wdt",		ingenic_mux_table, mux_table_8, CPM_OPCR,	2, 1, 0),
++
++};
++
++/*******************************************************************************
++ *      DIV BUS
++ ********************************************************************************/
++
++static struct ingenic_bus_clock x2000_bus_div_clks[] __initdata = {
++	BUS_DIV(CLK_DIV_CPU,		"div_cpu",		"mux_cpu_l2c",		CPM_CPCCR,	0,  4, 0, 0, CPM_CPCSR, 0, 22, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_L2C,		"div_l2c",		"mux_cpu_l2c",		CPM_CPCCR,	4,  4, 0, 0, CPM_CPCSR, 0, 22, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_AHB0,		"div_ahb0",		"mux_ahb0",		CPM_CPCCR,	8,  4, 0, 0, CPM_CPCSR, 1, 21, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_AHB2,		"div_ahb2",		"mux_ahb2",		CPM_CPCCR,	12, 4, 0, 0, CPM_CPCSR, 2, 20, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_APB,		"div_apb",		"mux_ahb2",		CPM_CPCCR,	16, 4, 0, 0, CPM_CPCSR, 2, 20, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_CPU_L2C_X1,	"div_cpu_l2c_x1",	"mux_cpu_l2c",		CPM_CPCCR,	0,  4, 4, 4, CPM_CPCSR, 0, 22, BUS_DIV_ONE),
++	BUS_DIV(CLK_DIV_CPU_L2C_X2,	"div_cpu_l2c_x2",	"mux_cpu_l2c",		CPM_CPCCR,	0,  4, 4, 4, CPM_CPCSR, 0, 22, BUS_DIV_TWO),
++};
++
++
++/*******************************************************************************
++ *      DIV
++ ********************************************************************************/
++
++static struct clk_div_table x2000_clk_div_table[256] = {};
++
++static struct ingenic_div_clock x2000_div_clks[] __initdata = {
++	DIV(CLK_DIV_DDR,		"div_ddr",		"mux_ddr",		CPM_DDRCDR,	4,  0, NULL),
++	DIV(CLK_DIV_MACPHY,		"div_macphy",		"mux_macphy",		CPM_MACCDR,	8,  0, NULL),
++	DIV(CLK_DIV_MACTXPHY,		"div_mactxphy0",	"mux_mactxphy",		CPM_MACTXCDR,	8,  0, NULL),
++	DIV(CLK_DIV_MACTXPHY1,		"div_mactxphy1",	"mux_mactxphy1",	CPM_MACTXCDR1,	8,  0, NULL),
++	DIV(CLK_DIV_MACPTP,		"div_macptp",		"mux_macptp",		CPM_MACPTP,	8,  0, NULL),
++	DIV(CLK_DIV_LCD,		"div_lcd",		"mux_lcd",		CPM_LPCDR,	8,  0, NULL),
++	DIV(CLK_DIV_MSC0,		"div_msc0",		"mux_msc0",		CPM_MSC0CDR,	8,  0, x2000_clk_div_table),
++	DIV(CLK_DIV_MSC1,		"div_msc1",		"mux_msc1",		CPM_MSC1CDR,	8,  0, x2000_clk_div_table),
++	DIV(CLK_DIV_MSC2,		"div_msc2",		"mux_msc2",		CPM_MSC2CDR,	8,  0, x2000_clk_div_table),
++	DIV(CLK_DIV_SFC,		"div_sfc",		"mux_sfc",		CPM_SFCCDR,	8,  0, NULL),
++	DIV(CLK_DIV_SSI,		"div_ssi",		"mux_ssi",		CPM_SSICDR,	8,  0, NULL),
++	DIV(CLK_DIV_CIM,		"div_cim",		"mux_cim",		CPM_CIMCDR,	8,  0, NULL),
++	DIV(CLK_DIV_PWM,		"div_pwm",		"mux_pwm",		CPM_PWMCDR,	4,  0, NULL),
++	DIV(CLK_DIV_ISP,		"div_isp",		"mux_isp",		CPM_ISPCDR,	4,  0, NULL),
++	DIV(CLK_DIV_RSA,		"div_rsa",		"mux_rsa",		CPM_RSACDR,	4,  0, NULL),
++
++};
++
++/*******************************************************************************
++ *      FRACTIONAL-DIVIDER
++ ********************************************************************************/
++
++static struct ingenic_fra_div_clock x2000_fdiv_clks[] __initdata = {
++	FRA_DIV(CLK_DIV_I2S0,	"div_i2s0",	"mux_i2s0",	CPM_I2S0CDR,	20, 9, 0, 20),
++	FRA_DIV(CLK_DIV_I2S1,	"div_i2s1",	"mux_i2s1",	CPM_I2S1CDR,	20, 9, 0, 20),
++	FRA_DIV(CLK_DIV_I2S2,	"div_i2s2",	"mux_i2s2",	CPM_I2S2CDR,	20, 9, 0, 20),
++	FRA_DIV(CLK_DIV_I2S3,	"div_i2s3",	"mux_i2s3",	CPM_I2S3CDR,	20, 9, 0, 20),
++};
++
++/*******************************************************************************
++ *      GATE
++ ********************************************************************************/
++static struct ingenic_gate_clock x2000_gate_clks[] __initdata = {
++
++	GATE(CLK_GATE_DDR,	"gate_ddr",		"div_ddr",	CPM_CLKGR,  31, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE),
++//	GATE(CLK_GATE_IPU,	"gate_ipu",		"div_ipu",	CPM_CLKGR,  30, 0,			 CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_AHB0,	"gate_ahb0",		"div_ahb0",	CPM_CLKGR,  29, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_APB0,	"gate_apb0",		"div_ahb0",	CPM_CLKGR,  28, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_RTC,	"gate_rtc",		"rtc_ext",	CPM_CLKGR,  27, 0,			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SSI1,	"gate_ssi1",		"div_ssi",	CPM_CLKGR,  26, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_RSA,	"gate_rsa",		"div_rsa",	CPM_CLKGR,  25, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_AES,	"gate_aes",		"div_ahb2",	CPM_CLKGR,  24, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_LCD,	"gate_lcd",		"div_lcd",	CPM_CLKGR,  23, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_CIM,	"gate_cim",		"div_cim",	CPM_CLKGR,  22, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_PDMA,	"gate_pdma",		"div_ahb2",	CPM_CLKGR,  21, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_OST,	"gate_ost",		"ext",		CPM_CLKGR,  20, CLK_IGNORE_UNUSED, 	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SSI0,	"gate_ssi0",		"div_ssi",	CPM_CLKGR,  19, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_TCU,	"gate_tcu",		"div_apb",	CPM_CLKGR,  18, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_DTRNG,	"gate_dtrng",		"div_apb",	CPM_CLKGR,  17, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART2,	"gate_uart2",		"div_apb",	CPM_CLKGR,  16, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART1,	"gate_uart1",		"div_apb",	CPM_CLKGR,  15, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART0,	"gate_uart0",		"div_apb",	CPM_CLKGR,  14, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SADC,	"gate_sadc",		"div_apb",	CPM_CLKGR,  13, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_HELIX,	"gate_helix",		"div_ahb0",	CPM_CLKGR,  12, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_AUDIO,	"gate_audio",		"div_ahb2",	CPM_CLKGR,  11, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB3,	"gate_i2c3",		"div_apb",	CPM_CLKGR,  10, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB2,	"gate_i2c2",		"div_apb",	CPM_CLKGR,  9,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB1,	"gate_i2c1",		"div_apb",	CPM_CLKGR,  8,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB0,	"gate_i2c0",		"div_apb",	CPM_CLKGR,  7,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SCC,	"gate_scc",		"div_apb",	CPM_CLKGR,  6,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_MSC1,	"gate_msc1",		"div_msc1",	CPM_CLKGR,  5,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_MSC0,	"gate_msc0",		"div_msc0",	CPM_CLKGR,  4,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_OTG,	"gate_otg",		"div_ahb2",	CPM_CLKGR,  3,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SFC,	"gate_sfc",		"div_sfc",	CPM_CLKGR,  2,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_EFUSE,	"gate_efuse",		"div_ahb2",	CPM_CLKGR,  1,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_NEMC,	"gate_nemc",		"div_ahb2",	CPM_CLKGR,  0,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_ARB,	"gate_arb",		"div_ahb0",	CPM_CLKGR1, 30, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_MIPI_DSI, "gate_dsi",		"div_ahb0",	CPM_CLKGR1, 29, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_MIPI_CSI, "gate_csi",		"div_ahb0",	CPM_CLKGR1, 28, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_INTC,	"gate_intc",		"div_ahb2",	CPM_CLKGR1, 26, CLK_IGNORE_UNUSED, 	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_MSC2,	"gate_msc2",		"div_msc2",	CPM_CLKGR1, 25, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_GMAC1,	"gate_gmac1",		"div_ahb2",	CPM_CLKGR1, 24, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_GMAC0,	"gate_gmac0",		"div_ahb2",	CPM_CLKGR1, 23, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART9,	"gate_uart9",		"div_apb",	CPM_CLKGR1, 22, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART8,	"gate_uart8",		"div_apb",	CPM_CLKGR1, 21, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART7,	"gate_uart7",		"div_apb",	CPM_CLKGR1, 20, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UATR6,	"gate_uart6",		"div_apb",	CPM_CLKGR1, 19, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART5,	"gate_uart5",		"div_apb",	CPM_CLKGR1, 18, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART4,	"gate_uart4",		"div_apb",	CPM_CLKGR1, 17, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART3,	"gate_uart3",		"div_apb",	CPM_CLKGR1, 16, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SPDIF,	"gate_spdif",		"mux_spdif",	CPM_CLKGR1, 14, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_DMIC,	"gate_dmic",		"mux_dmic",	CPM_CLKGR1, 13, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_PCM,	"gate_pcm",		"mux_pcm",	CPM_CLKGR1, 12, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_I2S3,	"gate_i2s3",		"div_i2s3",	CPM_CLKGR1, 11, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_I2S2,	"gate_i2s2",		"div_i2s2",	CPM_CLKGR1, 10, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_I2S1,	"gate_i2s1",		"div_i2s1",	CPM_CLKGR1, 9,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_I2S0,	"gate_i2s0",		"div_i2s0",	CPM_CLKGR1, 8,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_ROT,	"gate_rot",		"div_ahb0",	CPM_CLKGR1, 7,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_HASH,	"gate_hash",		"div_ahb2",	CPM_CLKGR1, 6,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_PWM,	"gate_pwm",		"div_pwm",	CPM_CLKGR1, 5,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_FELIX,	"gate_felix",		"div_ahb0",	CPM_CLKGR1, 4,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_ISP1,	"gate_isp1",		"div_apb",	CPM_CLKGR1, 3,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_ISP0,	"gate_isp0",		"div_apb",	CPM_CLKGR1, 2,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB5,	"gate_i2c5",		"div_apb",	CPM_CLKGR1, 1,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB4,	"gate_i2c4",		"div_apb",	CPM_CLKGR1, 0,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_USBPHY,	"gate_usbphy",		"div_apb",	CPM_OPCR,   23, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_CE_I2S0,	"ce_i2s0",		"div_i2s0",	CPM_I2S0CDR, 29, 0, 0),
++	GATE(CLK_CE_I2S1,	"ce_i2s1",		"div_i2s1",	CPM_I2S1CDR, 29, 0, 0),
++	GATE(CLK_CE_I2S2,	"ce_i2s2",		"div_i2s2",	CPM_I2S2CDR, 29, 0, 0),
++	GATE(CLK_CE_I2S3,	"ce_i2s3",		"div_i2s3",	CPM_I2S3CDR, 29, 0, 0),
++};
++
++static struct ingenic_gate_power x2000_gate_power[] __initdata = {
++
++	POWER(POWER_ISP0,	"power_isp0",		"gate_isp0",	CPM_LCR,  31, 27, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, POWER_GATE_WAIT),
++	POWER(POWER_ISP1,	"power_isp1",		"gate_isp1",	CPM_LCR,  30, 26, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, POWER_GATE_WAIT),
++	POWER(POWER_FELIX,	"power_felix",		"gate_felix",	CPM_LCR,  29, 25, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, POWER_GATE_WAIT),
++	POWER(POWER_HELIX,	"power_helix",		"gate_helix",	CPM_LCR,  28, 24, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, POWER_GATE_WAIT),
++
++	POWER(PD_MEM_NEMC,	"pd_mem_nemc",		"gate_nemc",	CPM_MPDCR,  28, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_USB,	"pd_mem_usb",		"gate_usb",	CPM_MPDCR,  27, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_SFC,	"pd_mem_sfc",		"gate_sfc",	CPM_MPDCR,  26, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_PDMA_SEC,	"pd_mem_pdma_sec",	"gate_pdma",	CPM_MPDCR,  25, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_PDMA,	"pd_mem_pdma",		"gate_pdma",	CPM_MPDCR,  24, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_MSC2,	"pd_mem_msc2",		"gate_msc2",	CPM_MPDCR,  23, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_MSC1,	"pd_mem_msc1",		"gate_msc1",	CPM_MPDCR,  22, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_MSC0,	"pd_mem_msc0",		"gate_msc0",	CPM_MPDCR,  21, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_GMAC1,	"pd_mem_gmac1",		"gate_gmac1",	CPM_MPDCR,  20, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_GMAC0,	"pd_mem_gmac0",		"gate_gmac0",	CPM_MPDCR,  19, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DMIC,	"pd_mem_dmic",		"gate_dmic",	CPM_MPDCR,  18, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_AUDIO,	"pd_mem_audio",		"gate_audio",	CPM_MPDCR,  17, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_AES,	"pd_mem_aes",		"gate_aes",	CPM_MPDCR,  16, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DSI,	"pd_mem_dsi",		"gate_dsi",	CPM_MPDCR,  12, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_SSI1,	"pd_mem_ssi1",		"gate_ssi1",	CPM_MPDCR,  11, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_SSI0,	"pd_mem_ssi0",		"gate_ssi0",	CPM_MPDCR,  10, 0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART9,	"pd_mem_uart9",		"gate_uart9",	CPM_MPDCR,  9,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART8,	"pd_mem_uart8",		"gate_uart8",	CPM_MPDCR,  8,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART7,	"pd_mem_uart7",		"gate_uart7",	CPM_MPDCR,  7,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART6,	"pd_mem_uart6",		"gate_uart6",	CPM_MPDCR,  6,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART5,	"pd_mem_uart5",		"gate_uart5",	CPM_MPDCR,  5,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART4,	"pd_mem_uart4",		"gate_uart4",	CPM_MPDCR,  4,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART3,	"pd_mem_uart3",		"gate_uart3",	CPM_MPDCR,  3,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART2,	"pd_mem_uart2",		"gate_uart2",	CPM_MPDCR,  2,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART1,	"pd_mem_uart1",		"gate_uart1",	CPM_MPDCR,  1,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_UART0,	"pd_mem_uart0",		"gate_uart0",	CPM_MPDCR,  0,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_ROT,	"pd_mem_rot",		"gate_rot",	CPM_MPDCR1, 8,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_CIM,	"pd_mem_cim",		"gate_cim",	CPM_MPDCR1, 7,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DPU,	"pd_mem_dpu",		"gate_dpu",	CPM_MPDCR1, 6,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DDR_CH6,	"pd_mem_ddr_ch6",	"gate_ddr",	CPM_MPDCR1, 5,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DDR_CH5,	"pd_mem_ddr_ch5",	"gate_ddr",	CPM_MPDCR1, 4,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DDR_CH3,	"pd_mem_ddr_ch3",	"gate_ddr",	CPM_MPDCR1, 3,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DDR_CH1,	"pd_mem_ddr_ch1",	"gate_ddr",	CPM_MPDCR1, 2,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DDR_CH0,	"pd_mem_ddr_ch0",	"gate_ddr",	CPM_MPDCR1, 1,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++	POWER(PD_MEM_DDR_TOP,	"pd_mem_ddr_top",	"gate_ddr",	CPM_MPDCR1, 0,  0, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE, 0),
++
++};
++
++static void clk_div_table_generate(void)
++{
++	int i;
++	for (i = 0; i < ARRAY_SIZE(x2000_clk_div_table); i++) {
++		x2000_clk_div_table[i].val = i;
++		x2000_clk_div_table[i].div = (i + 1) * 4;
++	}
++
++}
++
++static const struct of_device_id ext_clk_match[] __initconst = {
++	        { .compatible = "ingenic,fixed-clock", .data = (void *)0, },
++		{},
++};
++
++
++/* Register x2000 clocks. */
++static void __init x2000_clk_init(struct device_node *np, void __iomem *base)
++{
++	struct ingenic_clk_provider *ctx;
++	void __iomem *reg_base;
++
++
++	printk("x2000 Clock Power Management Unit init!\n");
++
++	reg_base = base;
++
++	if (np) {
++		reg_base = of_iomap(np, 0);
++		if (!reg_base)
++			panic("%s: failed to map registers\n", __func__);
++	}
++
++
++	ctx = ingenic_clk_init(np, reg_base, NR_CLKS);
++	if (!ctx)
++		panic("%s: unable to allocate context.\n", __func__);
++
++	/* Register Ext Clocks From DT */
++	ingenic_clk_of_register_fixed_ext(ctx, x2000_fixed_rate_ext_clks,
++			                        ARRAY_SIZE(x2000_fixed_rate_ext_clks), ext_clk_match);
++
++	/* Register PLLs. */
++	ingenic_clk_register_pll(ctx, x2000_pll_clks,
++				ARRAY_SIZE(x2000_pll_clks), reg_base);
++
++
++	/* Register Muxs */
++	ingenic_clk_register_mux(ctx, x2000_mux_clks, ARRAY_SIZE(x2000_mux_clks));
++
++	/* Register Bus Divs */
++	ingenic_clk_register_bus_div(ctx, x2000_bus_div_clks, ARRAY_SIZE(x2000_bus_div_clks));
++
++	/* Register Divs */
++	clk_div_table_generate();
++	ingenic_clk_register_cgu_div(ctx, x2000_div_clks, ARRAY_SIZE(x2000_div_clks));
++
++	/* Register Fractional Divs */
++	ingenic_clk_register_fra_div(ctx, x2000_fdiv_clks, ARRAY_SIZE(x2000_fdiv_clks));
++
++	/* Register Gates */
++	ingenic_clk_register_gate(ctx, x2000_gate_clks, ARRAY_SIZE(x2000_gate_clks));
++
++	/* Register Powers */
++	ingenic_power_register_gate(ctx, x2000_gate_power, ARRAY_SIZE(x2000_gate_power));
++
++	ingenic_clk_of_add_provider(np, ctx);
++
++
++	//ingenic_clk_of_dump(ctx);
++
++
++	pr_info("=========== x2000 clocks: =============\n"
++		"\tapll     = %lu , mpll     = %lu\n"
++		"\tcpu_clk  = %lu , l2c_clk  = %lu\n"
++		"\tahb0_clk = %lu , ahb2_clk = %lu\n"
++		"\tapb_clk  = %lu , ext_clk  = %lu\n\n",
++		_get_rate("apll"),	_get_rate("mpll"),
++		_get_rate("div_cpu"), _get_rate("div_l2c"),
++		_get_rate("div_ahb0"), _get_rate("div_ahb2"),
++		_get_rate("div_apb"), _get_rate("ext"));
++
++}
++
++CLK_OF_DECLARE(x2000_clk, "ingenic,x2000-clocks", x2000_clk_init);
++
+diff --git a/module_drivers/drivers/clk/ingenic-v2/clk-x2500.c b/module_drivers/drivers/clk/ingenic-v2/clk-x2500.c
+new file mode 100644
+index 000000000..be585d0d3
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/clk-x2500.c
+@@ -0,0 +1,296 @@
++#include <linux/slab.h>
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/syscore_ops.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/seq_file.h>
++#include <linux/proc_fs.h>
++#include <soc/cpm.h>
++#include <soc/base.h>
++#include <dt-bindings/clock/ingenic-x2500.h>
++
++#include <ingenic_proc.h>
++#include "clk.h"
++
++#define CLK_FLG_ENABLE BIT(1)
++static struct ingenic_clk_provider *ctx;
++
++extern void __clk_set_flags(struct clk *clk, unsigned long enable);
++/*******************************************************************************
++ *      FIXED CLK
++ ********************************************************************************/
++static struct ingenic_fixed_rate_clock x2500_fixed_rate_ext_clks[] __initdata = {
++	FRATE(CLK_EXT, "ext", NULL, 0, 24000000),
++	FRATE(CLK_RTC_EXT, "rtc_ext", NULL, 0, 32768),
++};
++
++
++
++/*******************************************************************************
++ *      PLL
++ ********************************************************************************/
++
++static struct ingenic_pll_rate_table x2500_pll_rate_table[] = {
++	PLL_RATE(1500000000, 125, 1, 2, 1),
++	PLL_RATE(1404000000, 117, 1, 2, 1),
++	PLL_RATE(1392000000, 116, 1, 2, 1),
++	PLL_RATE(1296000000, 108, 1, 2, 1),
++	PLL_RATE(1200000000, 100, 1, 2, 1),
++	PLL_RATE(1000000000, 125, 1, 3, 1),
++	PLL_RATE(900000000, 75, 1, 2, 1),
++	PLL_RATE(891000000, 297, 4, 2, 1),
++	PLL_RATE(864000000, 72, 1, 2, 1),
++	PLL_RATE(600000000, 75, 1, 3, 1),
++};
++
++
++
++/*PLL HWDESC*/
++static struct ingenic_pll_hwdesc apll_hwdesc = \
++	PLL_DESC(CPM_CPAPCR, 20, 12, 14, 6, 11, 3, 8, 3, 3, 0);
++
++static struct ingenic_pll_hwdesc mpll_hwdesc = \
++	PLL_DESC(CPM_CPMPCR, 20, 12, 14, 6, 11, 3, 8, 3, 3, 0);
++
++static struct ingenic_pll_hwdesc vpll_hwdesc = \
++	PLL_DESC(CPM_CPVPCR, 20, 12, 14, 6, 11, 3, 8, 3, 3, 0);
++
++static struct ingenic_pll_hwdesc epll_hwdesc = \
++	PLL_DESC(CPM_CPEPCR, 20, 12, 14, 6, 11, 3, 8, 3, 3, 0);
++
++
++
++static struct ingenic_pll_clock x2500_pll_clks[] __initdata = {
++	PLL(CLK_PLL_APLL, "apll", "ext", &apll_hwdesc, x2500_pll_rate_table),
++	PLL(CLK_PLL_MPLL, "mpll", "ext", &mpll_hwdesc, x2500_pll_rate_table),
++	PLL(CLK_PLL_VPLL, "vpll", "ext", &vpll_hwdesc, x2500_pll_rate_table),
++	PLL(CLK_PLL_EPLL, "epll", "ext", &epll_hwdesc, x2500_pll_rate_table),
++};
++
++
++/*******************************************************************************
++ *      MUX
++ ********************************************************************************/
++PNAME(mux_table_0)	= {"stop",	    "ext",		"apll"};
++PNAME(mux_table_1)	= {"stop",	    "sclka",	"mpll"};
++PNAME(mux_table_2)	= {"sclka",	    "mpll",		"vpll",    "epll"};
++PNAME(mux_table_3)	= {"sclka", 	"mpll",		"epll",    "ext"};
++PNAME(mux_table_4)	= {"sclka", 	"vpll",		"ext"};
++PNAME(mux_table_5)	= {"mux_ahb2",	"ext"};
++
++static unsigned int ingenic_mux_table[] = {0, 1, 2, 3};
++
++
++static struct ingenic_mux_clock x2500_mux_clks[] __initdata = {
++	MUX(CLK_MUX_SCLKA,	    "sclka",		ingenic_mux_table, mux_table_0, CPM_CPCCR,	    30, 2, 0),
++	MUX(CLK_MUX_CPU_L2C,	"mux_cpu_l2c",	ingenic_mux_table, mux_table_1, CPM_CPCCR,	    28, 2, 0),
++	MUX(CLK_MUX_AHB0,	    "mux_ahb0",		ingenic_mux_table, mux_table_1, CPM_CPCCR,	    26, 2, 0),
++	MUX(CLK_MUX_AHB2,	    "mux_ahb2",		ingenic_mux_table, mux_table_1, CPM_CPCCR,	    24, 2, 0),
++
++	MUX(CLK_MUX_DDR,	    "mux_ddr",		ingenic_mux_table, mux_table_1, CPM_DDRCDR,	    30, 2, 0),
++	MUX(CLK_MUX_EL150,	    "mux_el150",	ingenic_mux_table, mux_table_2, CPM_EL150CDR,   30, 2, 0),
++	MUX(CLK_MUX_RSA,	    "mux_rsa",		ingenic_mux_table, mux_table_2, CPM_RSACDR,	    30, 2, 0),
++	MUX(CLK_MUX_MACPHY,	    "mux_macphy",	ingenic_mux_table, mux_table_2, CPM_MACCDR,	    30, 2, 0),
++	MUX(CLK_MUX_SFC,	    "mux_sfc",		ingenic_mux_table, mux_table_2, CPM_SFCCDR,	    30, 2, 0),
++	MUX(CLK_MUX_LCD,	    "mux_lcd",		ingenic_mux_table, mux_table_2, CPM_LPCDR,	    30, 2, 0),
++	MUX(CLK_MUX_MSC0,	    "mux_msc0",		ingenic_mux_table, mux_table_2, CPM_MSC0CDR,	30, 2, 0),
++	MUX(CLK_MUX_MSC1,	    "mux_msc1",		ingenic_mux_table, mux_table_2, CPM_MSC1CDR,	30, 2, 0),
++	MUX(CLK_MUX_SSI,	    "mux_ssi",		ingenic_mux_table, mux_table_2, CPM_SSICDR,	    30, 2, 0),
++	MUX(CLK_MUX_I2ST,	    "mux_i2st",		ingenic_mux_table, mux_table_2, CPM_I2STCDR,    30, 2, 0),
++	MUX(CLK_MUX_ISP,	    "mux_isp",		ingenic_mux_table, mux_table_2, CPM_ISPCDR,	    30, 2, 0),
++	MUX(CLK_MUX_I2SR,	    "mux_i2sr",		ingenic_mux_table, mux_table_2, CPM_I2SRCDR,    30, 2, 0),
++	MUX(CLK_MUX_CIM0,	    "mux_cim0",		ingenic_mux_table, mux_table_2, CPM_CIM0CDR,	30, 2, 0),
++	MUX(CLK_MUX_CIM1,	    "mux_cim1",		ingenic_mux_table, mux_table_2, CPM_CIM1CDR,	30, 2, 0),
++	MUX(CLK_MUX_CIM2,	    "mux_cim2",		ingenic_mux_table, mux_table_2, CPM_CIM2CDR,	30, 2, 0),
++	MUX(CLK_MUX_BSCALER,	"mux_bscaler",	ingenic_mux_table, mux_table_2, CPM_BSCALERCDR,	30, 2, 0),
++	MUX(CLK_MUX_BT0,	    "mux_bt0",	    ingenic_mux_table, mux_table_2, CPM_BT0CDR,	    30, 2, 0),
++
++};
++
++/*******************************************************************************
++ *      DIV BUS
++ ********************************************************************************/
++
++static struct ingenic_bus_clock x2500_bus_div_clks[] __initdata = {
++	BUS_DIV(CLK_DIV_CPU,		"div_cpu",		    "mux_cpu_l2c",		CPM_CPCCR,	0,  4, 0, 0, CPM_CPCSR, 0, 22, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_L2C,		"div_l2c",		    "mux_cpu_l2c",		CPM_CPCCR,	4,  4, 0, 0, CPM_CPCSR, 0, 22, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_AHB0,		"div_ahb0",		    "mux_ahb0",		    CPM_CPCCR,	8,  4, 0, 0, CPM_CPCSR, 1, 21, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_AHB2,		"div_ahb2",		    "mux_ahb2",		    CPM_CPCCR,	12, 4, 0, 0, CPM_CPCSR, 2, 20, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_APB,		"div_apb",		    "mux_ahb2",		    CPM_CPCCR,	16, 4, 0, 0, CPM_CPCSR, 2, 20, BUS_DIV_SELF),
++	BUS_DIV(CLK_DIV_CPU_L2C_X1,	"div_cpu_l2c_x1",	"mux_cpu_l2c",		CPM_CPCCR,	0,  4, 4, 4, CPM_CPCSR, 0, 22, BUS_DIV_ONE),
++	BUS_DIV(CLK_DIV_CPU_L2C_X2,	"div_cpu_l2c_x2",	"mux_cpu_l2c",		CPM_CPCCR,	0,  4, 4, 4, CPM_CPCSR, 0, 22, BUS_DIV_TWO),
++};
++
++
++/*******************************************************************************
++ *      DIV
++ ********************************************************************************/
++
++static struct clk_div_table x2500_clk_div_table[256] = {};
++
++static struct ingenic_div_clock x2500_div_clks[] __initdata = {
++	DIV(CLK_DIV_DDR,		"div_ddr",		"mux_ddr",		CPM_DDRCDR,	    4,  0, NULL),
++	DIV(CLK_DIV_MACPHY,		"div_macphy",	"mux_macphy",	CPM_MACCDR,	    8,  0, NULL),
++	DIV(CLK_DIV_LCD,		"div_lcd",		"mux_lcd",		CPM_LPCDR,	    8,  0, NULL),
++	DIV(CLK_DIV_MSC0,		"div_msc0",		"mux_msc0",		CPM_MSC0CDR,	8,  0, x2500_clk_div_table),
++	DIV(CLK_DIV_MSC1,		"div_msc1",		"mux_msc1",		CPM_MSC1CDR,	8,  0, x2500_clk_div_table),
++	DIV(CLK_DIV_SFC,		"div_sfc",		"mux_sfc",		CPM_SFCCDR,	    8,  0, NULL),
++	DIV(CLK_DIV_SSI,		"div_ssi",		"mux_ssi",		CPM_SSICDR,	    8,  0, NULL),
++	DIV(CLK_DIV_CIM0,		"div_cim0",		"mux_cim0",		CPM_CIM0CDR,	8,  0, NULL),
++	DIV(CLK_DIV_CIM1,		"div_cim1",		"mux_cim1",		CPM_CIM1CDR,	8,  0, NULL),
++	DIV(CLK_DIV_CIM2,		"div_cim2",		"mux_cim2",		CPM_CIM2CDR,	8,  0, NULL),
++	DIV(CLK_DIV_ISP,		"div_isp",		"mux_isp",		CPM_ISPCDR,	    4,  0, NULL),
++	DIV(CLK_DIV_RSA,		"div_rsa",		"mux_rsa",		CPM_RSACDR,	    4,  0, NULL),
++	DIV(CLK_DIV_EL150,		"div_el150",	"mux_el150",	CPM_EL150CDR,   4,  0, NULL),
++	DIV(CLK_DIV_BSCALER,	"div_bscaler",	"mux_bscaler",	CPM_BSCALERCDR,	4,  0, NULL),
++	DIV(CLK_DIV_BT0,		"div_bt0",		"mux_bt0",		CPM_BT0CDR,	    8,  0, NULL),
++
++};
++
++/*******************************************************************************
++ *      FRACTIONAL-DIVIDER
++ ********************************************************************************/
++
++static struct ingenic_fra_div_clock x2500_fdiv_clks[] __initdata = {
++	FRA_DIV(CLK_DIV_I2ST,	"div_i2st",	"mux_i2st",	CPM_I2STCDR,	20, 9, 0, 20),
++	FRA_DIV(CLK_DIV_I2SR,	"div_i2sr",	"mux_i2sr",	CPM_I2SRCDR,	20, 9, 0, 20),
++};
++
++/*******************************************************************************
++ *      GATE
++ ********************************************************************************/
++static struct ingenic_gate_clock x2500_gate_clks[] __initdata = {
++
++	GATE(CLK_GATE_DDR,	    "gate_ddr",		    "div_ddr",	    CPM_CLKGR,  31, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_TCU,	    "gate_tcu",		    "div_apb",	    CPM_CLKGR,  30, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_DES,	    "gate_des",		    "div_apb",	    CPM_CLKGR,  28, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_RSA,	    "gate_rsa",		    "div_rsa",	    CPM_CLKGR,  27, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_MIPI_CSI, "gate_csi",		    "div_ahb0",	    CPM_CLKGR,  25, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_LCD,	    "gate_lcd",		    "div_lcd",	    CPM_CLKGR,  24, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_ISP,	    "gate_isp",		    "div_isp",	    CPM_CLKGR,  23, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_PDMA,	    "gate_pdma",		"div_ahb2",	    CPM_CLKGR,  22, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SFC,	    "gate_sfc",		    "div_sfc",	    CPM_CLKGR,  21, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SSI1,	    "gate_ssi1",		"div_ssi",	    CPM_CLKGR,  20, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_HASH,	    "gate_hash",		"div_ahb2",	    CPM_CLKGR,  19, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SLV,	    "gate_slv",		    "div_apb",	    CPM_CLKGR,  18, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART3,	"gate_uart3",		"div_apb",	    CPM_CLKGR,  17, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART2,	"gate_uart2",		"div_apb",	    CPM_CLKGR,  16, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART1,	"gate_uart1",		"div_apb",	    CPM_CLKGR,  15, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_UART0,	"gate_uart0",		"div_apb",	    CPM_CLKGR,  14, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SADC,	    "gate_sadc",		"div_apb",	    CPM_CLKGR,  13, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_DMIC,	    "gate_dmic",		"mux_apb",	    CPM_CLKGR,  12, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_AIC,	    "gate_aic",		    "div_i2st",	    CPM_CLKGR,  11, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB3,	    "gate_i2c3",		"div_apb",	    CPM_CLKGR,  10, 0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB2,	    "gate_i2c2",		"div_apb",	    CPM_CLKGR,  9,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB1,	    "gate_i2c1",		"div_apb",	    CPM_CLKGR,  8,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SMB0,	    "gate_i2c0",		"div_apb",	    CPM_CLKGR,  7,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_SSI0,	    "gate_ssi0",		"div_ssi",	    CPM_CLKGR,  6,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_MSC1,	    "gate_msc1",		"div_msc1",	    CPM_CLKGR,  5,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_MSC0,	    "gate_msc0",		"div_msc0",	    CPM_CLKGR,  4,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_OTG,	    "gate_otg",		    "div_ahb2",	    CPM_CLKGR,  3,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_BSCALER,	"gate_bscaler",		"div_bscaler",	CPM_CLKGR,  2,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_EFUSE,	"gate_efuse",		"div_ahb2",	    CPM_CLKGR,  1,  0,			CLK_GATE_HIWORD_MASK),
++	GATE(CLK_GATE_NEMC,	    "gate_nemc",		"div_ahb2",	    CPM_CLKGR,  0,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_CPU,	    "gate_cpu",		    "div_cpu",	    CPM_CLKGR1, 15, 0,  		CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_APB0,	    "gate_apb0",		"div_ahb0",	    CPM_CLKGR1, 14, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_OST,	    "gate_ost",		    "ext",		    CPM_CLKGR1, 11, CLK_IGNORE_UNUSED, 	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_AHB0,	    "gate_ahb0",		"div_ahb0",	    CPM_CLKGR1, 10, CLK_IGNORE_UNUSED,	CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_BUS_MONITOR,	"gate_bus_monitor",	"div_ahb0",	    CPM_CLKGR1, 9,  0,	        CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_I2D,	    "gate_i2d",		    "div_ahb0",	    CPM_CLKGR1, 8,  0,	        CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_MIPI_DSI, "gate_dsi",		    "div_ahb0",	    CPM_CLKGR1, 7,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_DRAWBOX,  "gate_drawbox",     "div_ahb0",     CPM_CLKGR1, 6,  0,          CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_AES,	    "gate_aes",		    "div_ahb2",	    CPM_CLKGR1, 5,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_GMAC,	    "gate_gmac",		"div_ahb2",	CPM_CLKGR1, 4,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_AHB1,	    "gate_ahb1",		"div_ahb2",	    CPM_CLKGR1, 3,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_IPU,      "gate_ipu",         "div_ahb0",     CPM_CLKGR1, 2,  0,          CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_DTRNG,	"gate_dtrng",		"div_apb",	    CPM_CLKGR1, 1,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_GATE_EL150,	"gate_el150",		"div_el150",    CPM_CLKGR1, 0,  0, 			CLK_GATE_SET_TO_DISABLE),
++	GATE(CLK_CE_I2ST,	    "ce_i2st",		    "div_i2st",	    CPM_I2STCDR, 29, 0, 0),
++	GATE(CLK_CE_I2SR,	    "ce_i2sr",		    "div_i2sr",	    CPM_I2SRCDR, 29, 0, 0),
++	GATE(CLK_GATE_USBPHY,   "gate_usbphy",      "div_apb",      CPM_OPCR,   23, 0,          CLK_GATE_SET_TO_DISABLE)
++};
++
++static void clk_div_table_generate(void)
++{
++	int i;
++	for (i = 0; i < ARRAY_SIZE(x2500_clk_div_table); i++) {
++		x2500_clk_div_table[i].val = i;
++		x2500_clk_div_table[i].div = (i + 1) * 4;
++	}
++
++}
++
++static const struct of_device_id ext_clk_match[] __initconst = {
++	        { .compatible = "ingenic,fixed-clock", .data = (void *)0, },
++			{},
++};
++
++/* Register x2500 clocks. */
++static void __init x2500_clk_init(struct device_node *np, void __iomem *base)
++{
++	void __iomem *reg_base;
++
++	printk("x2500 Clock Power Management Unit init!\n");
++
++	reg_base = base;
++
++	if (np) {
++		reg_base = of_iomap(np, 0);
++		if (!reg_base)
++			panic("%s: failed to map registers\n", __func__);
++	}
++
++
++	ctx = ingenic_clk_init(np, reg_base, NR_CLKS);
++	if (!ctx)
++		panic("%s: unable to allocate context.\n", __func__);
++
++	/* Register Ext Clocks From DT */
++	ingenic_clk_of_register_fixed_ext(ctx, x2500_fixed_rate_ext_clks,
++			                        ARRAY_SIZE(x2500_fixed_rate_ext_clks), ext_clk_match);
++
++	/* Register PLLs. */
++	ingenic_clk_register_pll(ctx, x2500_pll_clks,
++				ARRAY_SIZE(x2500_pll_clks), reg_base);
++
++
++	/* Register Muxs */
++	ingenic_clk_register_mux(ctx, x2500_mux_clks, ARRAY_SIZE(x2500_mux_clks));
++
++	/* Register Bus Divs */
++	ingenic_clk_register_bus_div(ctx, x2500_bus_div_clks, ARRAY_SIZE(x2500_bus_div_clks));
++
++	/* Register Divs */
++	clk_div_table_generate();
++	ingenic_clk_register_cgu_div(ctx, x2500_div_clks, ARRAY_SIZE(x2500_div_clks));
++
++	/* Register Fractional Divs */
++	ingenic_clk_register_fra_div(ctx, x2500_fdiv_clks, ARRAY_SIZE(x2500_fdiv_clks));
++
++	/* Register Gates */
++	ingenic_clk_register_gate(ctx, x2500_gate_clks, ARRAY_SIZE(x2500_gate_clks));
++
++	/* Register Powers */
++//	ingenic_power_register_gate(ctx, x2500_gate_power, ARRAY_SIZE(x2500_gate_power));
++
++	ingenic_clk_of_add_provider(np, ctx);
++
++
++	//ingenic_clk_of_dump(ctx);
++
++
++	pr_info("=========== x2500 clocks: =============\n"
++		"\tapll     = %lu , mpll     = %lu\n"
++		"\tcpu_clk  = %lu , l2c_clk  = %lu\n"
++		"\tahb0_clk = %lu , ahb2_clk = %lu\n"
++		"\tapb_clk  = %lu , ext_clk  = %lu\n\n",
++		_get_rate("apll"),	_get_rate("mpll"),
++		_get_rate("div_cpu"), _get_rate("div_l2c"),
++		_get_rate("div_ahb0"), _get_rate("div_ahb2"),
++		_get_rate("div_apb"), _get_rate("ext"));
++
++}
++
++CLK_OF_DECLARE(x2500_clk, "ingenic,x2500-clocks", x2500_clk_init);
+diff --git a/module_drivers/drivers/clk/ingenic-v2/clk.c b/module_drivers/drivers/clk/ingenic-v2/clk.c
+new file mode 100644
+index 000000000..aa34d7f0a
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/clk.c
+@@ -0,0 +1,518 @@
++#include <linux/slab.h>
++#include <linux/clkdev.h>
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/of_address.h>
++#include <linux/syscore_ops.h>
++
++#include "clk.h"
++
++static LIST_HEAD(clock_reg_cache_list);
++
++void ingenic_clk_save(void __iomem *base,
++				    struct ingenic_clk_reg_sleep *rd,
++				    unsigned int num_regs)
++{
++	for (; num_regs > 0; --num_regs, ++rd)
++		rd->value = readl(base + rd->offset);
++}
++
++void ingenic_clk_restore(void __iomem *base,
++				      struct ingenic_clk_reg_sleep *rd,
++				      unsigned int num_regs)
++{
++	unsigned int timeout = 0xffff;
++	for (; num_regs > 0; --num_regs, ++rd) {
++
++		if(!rd->ce && !rd->busy) {
++			writel(rd->value, base + rd->offset);
++		} else {
++			writel(rd->value | 1 << rd->ce, base + rd->offset);
++
++			timeout = 0xffff;
++
++#if 0
++			while(--timeout && readl(base + rd->offset) & (1 << rd->busy));
++
++			if(!timeout) {
++				printk("Error restore clk regs: %x\n", rd->offset);
++			}
++#endif
++		}
++	}
++}
++
++/* setup the essentials required to support clock lookup using ccf */
++struct ingenic_clk_provider *__init ingenic_clk_init(struct device_node *np,
++			void __iomem *base, unsigned long nr_clks)
++{
++	struct ingenic_clk_provider *ctx;
++	struct clk **clk_table;
++	int i;
++
++	ctx = kzalloc(sizeof(struct ingenic_clk_provider), GFP_KERNEL);
++	if (!ctx)
++		panic("could not allocate clock provider context.\n");
++
++	clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
++	if (!clk_table)
++		panic("could not allocate clock lookup table\n");
++
++	for (i = 0; i < nr_clks; ++i)
++		clk_table[i] = ERR_PTR(-ENOENT);
++
++	ctx->reg_base = base;
++	ctx->clk_data.clks = clk_table;
++	ctx->clk_data.clk_num = nr_clks;
++	spin_lock_init(&ctx->lock);
++
++	return ctx;
++}
++
++void __init ingenic_clk_of_add_provider(struct device_node *np,
++				struct ingenic_clk_provider *ctx)
++{
++	if (np) {
++		if (of_clk_add_provider(np, of_clk_src_onecell_get,
++					&ctx->clk_data))
++			panic("could not register clk provider\n");
++	}
++}
++
++void ingenic_clk_of_dump(struct ingenic_clk_provider *ctx)
++{
++	struct clk_onecell_data * clk_data;
++	struct clk *clk;
++	int i;
++
++	clk_data = &ctx->clk_data;
++
++	for(i = 0; i < clk_data->clk_num; i++) {
++
++		clk = clk_data->clks[i];
++		if(clk != ERR_PTR(-ENOENT)) {
++			printk("clk->id: %d clk->name: %s \n", i,  __clk_get_name(clk));
++		} else {
++			printk("clk->id: %d , clk: %p\n", i, clk);
++		}
++	}
++
++
++
++}
++
++
++/* add a clock instance to the clock lookup table used for dt based lookup */
++void ingenic_clk_add_lookup(struct ingenic_clk_provider *ctx, struct clk *clk,
++				unsigned int id)
++{
++	if (ctx->clk_data.clks && id) {
++		ctx->clk_data.clks[id] = clk;
++	}
++}
++
++/* register a list of aliases */
++void __init ingenic_clk_register_alias(struct ingenic_clk_provider *ctx,
++				const struct ingenic_clock_alias *list,
++				unsigned int nr_clk)
++{
++	struct clk *clk;
++	unsigned int idx, ret;
++
++	if (!ctx->clk_data.clks) {
++		pr_err("%s: clock table missing\n", __func__);
++		return;
++	}
++
++	for (idx = 0; idx < nr_clk; idx++, list++) {
++		if (!list->id) {
++			pr_err("%s: clock id missing for index %d\n", __func__,
++				idx);
++			continue;
++		}
++
++		clk = ctx->clk_data.clks[list->id];
++		if (!clk) {
++			pr_err("%s: failed to find clock %d\n", __func__,
++				list->id);
++			continue;
++		}
++
++		ret = clk_register_clkdev(clk, list->alias, list->dev_name);
++		if (ret)
++			pr_err("%s: failed to register lookup %s\n",
++					__func__, list->alias);
++	}
++}
++
++/* register a list of fixed clocks */
++void __init ingenic_clk_register_fixed_rate(struct ingenic_clk_provider *ctx,
++		const struct ingenic_fixed_rate_clock *list,
++		unsigned int nr_clk)
++{
++	struct clk *clk;
++	unsigned int idx, ret;
++
++	for (idx = 0; idx < nr_clk; idx++, list++) {
++		clk = clk_register_fixed_rate(NULL, list->name,
++			list->parent_name, list->flags, list->fixed_rate);
++		if (IS_ERR(clk)) {
++			pr_err("%s: failed to register clock %s\n", __func__,
++				list->name);
++			continue;
++		}
++
++		ingenic_clk_add_lookup(ctx, clk, list->id);
++
++		ret = clk_register_clkdev(clk, list->name, NULL);
++		if (ret)
++			pr_err("%s: failed to register clock lookup for %s",
++				__func__, list->name);
++	}
++}
++
++/* register a list of fixed factor clocks */
++void __init ingenic_clk_register_fixed_factor(struct ingenic_clk_provider *ctx,
++		const struct ingenic_fixed_factor_clock *list, unsigned int nr_clk)
++{
++	struct clk *clk;
++	unsigned int idx;
++
++	for (idx = 0; idx < nr_clk; idx++, list++) {
++		clk = clk_register_fixed_factor(NULL, list->name,
++			list->parent_name, list->flags, list->mult, list->div);
++		if (IS_ERR(clk)) {
++			pr_err("%s: failed to register clock %s\n", __func__,
++				list->name);
++			continue;
++		}
++
++		ingenic_clk_add_lookup(ctx, clk, list->id);
++	}
++}
++
++/* register a list of mux clocks */
++void __init ingenic_clk_register_mux(struct ingenic_clk_provider *ctx,
++				const struct ingenic_mux_clock *list,
++				unsigned int nr_clk)
++{
++	struct clk *clk;
++	unsigned int idx, ret;
++
++	for (idx = 0; idx < nr_clk; idx++, list++) {
++		if(list->table) {
++			clk = clk_register_mux_table(NULL, list->name, list->parent_names,
++					list->num_parents, list->flags,
++					ctx->reg_base + list->offset,
++					list->shift, BIT(list->width) - 1, list->mux_flags, list->table, &ctx->lock);
++		} else {
++			clk = clk_register_mux(NULL, list->name, list->parent_names,
++					list->num_parents, list->flags,
++					ctx->reg_base + list->offset,
++					list->shift, list->width, list->mux_flags, &ctx->lock);
++
++		}
++		if (IS_ERR(clk)) {
++			pr_err("%s: failed to register clock %s\n", __func__,
++				list->name);
++			continue;
++		}
++
++		ingenic_clk_add_lookup(ctx, clk, list->id);
++
++		/* register a clock lookup only if a clock alias is specified */
++		if (list->alias) {
++			ret = clk_register_clkdev(clk, list->alias,
++						list->dev_name);
++			if (ret)
++				pr_err("%s: failed to register lookup %s\n",
++						__func__, list->alias);
++		}
++	}
++}
++
++/* register a list of div clocks */
++void __init ingenic_clk_register_cgu_div(struct ingenic_clk_provider *ctx,
++				const struct ingenic_div_clock *list,
++				unsigned int nr_clk)
++{
++	struct clk *clk;
++	unsigned int idx, ret;
++
++	for (idx = 0; idx < nr_clk; idx++, list++) {
++		if (list->table)
++			clk = clk_register_cgu_divider_table(NULL, list->name,
++				list->parent_name, list->flags,
++				ctx->reg_base + list->offset,
++				list->shift, list->width,
++				list->busy_shift, list->en_shift, list->stop_shift,
++				list->div_flags, list->table, &ctx->lock);
++		else
++			clk = clk_register_cgu_divider(NULL, list->name,
++				list->parent_name, list->flags,
++				ctx->reg_base + list->offset,
++				list->shift, list->width,
++				list->busy_shift, list->en_shift, list->stop_shift,
++				list->div_flags, &ctx->lock);
++		if (IS_ERR(clk)) {
++			pr_err("%s: failed to register clock %s\n", __func__,
++				list->name);
++			continue;
++		}
++
++		ingenic_clk_add_lookup(ctx, clk, list->id);
++
++		/* register a clock lookup only if a clock alias is specified */
++		if (list->alias) {
++			ret = clk_register_clkdev(clk, list->alias,
++						list->dev_name);
++			if (ret)
++				pr_err("%s: failed to register lookup %s\n",
++						__func__, list->alias);
++		}
++	}
++}
++
++/* register a list of div clocks */
++void __init ingenic_clk_register_bus_div(struct ingenic_clk_provider *ctx,
++				const struct ingenic_bus_clock *list,
++				unsigned int nr_clk)
++{
++	struct clk *clk;
++	unsigned int idx, ret;
++
++	for (idx = 0; idx < nr_clk; idx++, list++) {
++		if (list->table)
++			clk = clk_register_bus_divider_table(NULL, list->name,
++				list->parent_name, list->flags,
++				ctx->reg_base + list->cfg_offset,
++				list->div_shift1, list->div_width1,
++				list->div_shift2, list->div_width2,
++				ctx->reg_base + list->busy_offset,
++				list->busy_shift, list->ce_shift,
++				list->div_flags, list->div_flags_2,
++				list->table, &ctx->lock);
++		else
++			clk = clk_register_bus_divider(NULL, list->name,
++				list->parent_name, list->flags,
++				ctx->reg_base + list->cfg_offset,
++				list->div_shift1, list->div_width1,
++				list->div_shift2, list->div_width2,
++				ctx->reg_base + list->busy_offset,
++				list->busy_shift, list->ce_shift,
++				list->div_flags, list->div_flags_2,
++				&ctx->lock);
++		if (IS_ERR(clk)) {
++			pr_err("%s: failed to register clock %s\n", __func__,
++				list->name);
++			continue;
++		}
++
++		ingenic_clk_add_lookup(ctx, clk, list->id);
++
++		/* register a clock lookup only if a clock alias is specified */
++		if (list->alias) {
++			ret = clk_register_clkdev(clk, list->alias,
++						list->dev_name);
++			if (ret)
++				pr_err("%s: failed to register lookup %s\n",
++						__func__, list->alias);
++		}
++	}
++}
++
++void __init ingenic_clk_register_fra_div(struct ingenic_clk_provider *ctx,
++					const struct ingenic_fra_div_clock *list,
++					unsigned int nr_clk)
++{
++	struct clk *clk;
++	unsigned int idx, ret;
++
++	for (idx = 0; idx < nr_clk; idx++, list++) {
++		clk = clk_register_fractional_divider(NULL,
++				list->name, list->parent_name, list->flags,
++				ctx->reg_base + list->offset,
++				list->mshift, list->mwidth, list->nshift, list->nwidth,
++				list->div_flags, &ctx->lock);
++
++		if (IS_ERR(clk)) {
++			pr_err("%s: failed to register clock %s\n", __func__,
++					list->name);
++			continue;
++		}
++
++		ingenic_clk_add_lookup(ctx, clk, list->id);
++
++		/* register a clock lookup only if a clock alias is specified */
++		if (list->alias) {
++			ret = clk_register_clkdev(clk, list->alias,
++					list->dev_name);
++			if (ret)
++				pr_err("%s: failed to register lookup %s\n", __func__, list->alias);
++		}
++	}
++}
++
++
++/* register a list of gate clocks */
++void __init ingenic_clk_register_gate(struct ingenic_clk_provider *ctx,
++				const struct ingenic_gate_clock *list,
++				unsigned int nr_clk)
++{
++	struct clk *clk;
++	unsigned int idx, ret, i;
++
++
++	for (idx = 0; idx < nr_clk; idx++, list++) {
++
++		clk = clk_register_gate(NULL, list->name, list->parent_name, list->flags,
++				        ctx->reg_base + list->offset, list->bit_idx,
++					list->gate_flags, &ctx->lock);
++
++		if (IS_ERR(clk)) {
++			pr_err("%s: failed to register clock %s\n", __func__,
++				list->name);
++			continue;
++		}
++
++		/* register a clock lookup only if a clock alias is specified */
++		if (list->alias) {
++			ret = clk_register_clkdev(clk, list->alias,
++							list->dev_name);
++			if (ret)
++				pr_err("%s: failed to register lookup %s\n",
++					__func__, list->alias);
++		}
++
++		ingenic_clk_add_lookup(ctx, clk, list->id);
++
++
++	}
++
++
++
++}
++
++void __init ingenic_power_register_gate(struct ingenic_clk_provider *ctx,
++				const struct ingenic_gate_power *list,
++				unsigned int nr_clk)
++{
++	struct clk *clk;
++	unsigned int idx, ret, i;
++
++	for (idx = 0; idx < nr_clk; idx++, list++) {
++
++		clk = power_register_gate(NULL, list->name, list->parent_name, list->flags,
++				        ctx->reg_base + list->offset, list->ctrl_bit, list->wait_bit,
++					list->gate_flags, list->power_flags, &ctx->lock);
++
++		if (IS_ERR(clk)) {
++			pr_err("%s: failed to register clock %s\n", __func__,
++				list->name);
++			continue;
++		}
++
++		/* register a clock lookup only if a clock alias is specified */
++		if (list->alias) {
++			ret = clk_register_clkdev(clk, list->alias,
++							list->dev_name);
++			if (ret)
++				pr_err("%s: failed to register lookup %s\n",
++					__func__, list->alias);
++		}
++
++		ingenic_clk_add_lookup(ctx, clk, list->id);
++
++	}
++
++}
++/*
++ * obtain the clock speed of all external fixed clock sources from device
++ * tree and register it
++ */
++void __init ingenic_clk_of_register_fixed_ext(struct ingenic_clk_provider *ctx,
++			struct ingenic_fixed_rate_clock *fixed_rate_clk,
++			unsigned int nr_fixed_rate_clk,
++			const struct of_device_id *clk_matches)
++{
++	const struct of_device_id *match;
++	struct device_node *clk_np;
++	u32 freq;
++	u32 index = 0;
++
++	for_each_matching_node_and_match(clk_np, clk_matches, &match) {
++		if (of_property_read_u32(clk_np, "clock-frequency", &freq))
++			continue;
++		fixed_rate_clk[index].fixed_rate = freq;
++		index++;
++	}
++	ingenic_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
++}
++
++/* utility function to get the rate of a specified clock */
++unsigned long _get_rate(const char *clk_name)
++{
++	struct clk *clk;
++
++	clk = __clk_lookup(clk_name);
++	if (!clk) {
++		pr_err("%s: could not find clock %s\n", __func__, clk_name);
++		return 0;
++	}
++
++	return clk_get_rate(clk);
++}
++
++#ifdef CONFIG_PM
++static int ingenic_clk_suspend(void)
++{
++	struct ingenic_clock_reg_cache *reg_cache;
++
++	list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
++		ingenic_clk_save(reg_cache->reg_base, reg_cache->reg_sleep,
++				reg_cache->nr_reg_sleep);
++	return 0;
++}
++
++static void ingenic_clk_resume(void)
++{
++	struct ingenic_clock_reg_cache *reg_cache;
++
++	list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
++		ingenic_clk_restore(reg_cache->reg_base, reg_cache->reg_sleep,
++				reg_cache->nr_reg_sleep);
++}
++
++static struct syscore_ops ingenic_clk_syscore_ops = {
++	.suspend = ingenic_clk_suspend,
++	.resume = ingenic_clk_resume,
++};
++
++void __init ingenic_clk_sleep_init(void __iomem *reg_base,
++		struct ingenic_clk_reg_sleep  *reg_sleep,
++		unsigned long nr_reg_sleep)
++{
++	struct ingenic_clock_reg_cache *reg_cache;
++
++	reg_cache = kzalloc(sizeof(struct ingenic_clock_reg_cache),
++			GFP_KERNEL);
++	if (!reg_cache)
++		panic("could not allocate register reg_cache.\n");
++
++	reg_cache->reg_sleep = reg_sleep;
++	reg_cache->nr_reg_sleep = nr_reg_sleep;
++
++
++	if (list_empty(&clock_reg_cache_list))
++		register_syscore_ops(&ingenic_clk_syscore_ops);
++
++	reg_cache->reg_base = reg_base;
++	list_add_tail(&reg_cache->node, &clock_reg_cache_list);
++}
++
++#else
++static void ingenic_clk_sleep_init(void __iomem *reg_base,
++		unsigned long *rdump,
++		unsigned long nr_rdump) {}
++#endif
++
+diff --git a/module_drivers/drivers/clk/ingenic-v2/clk.h b/module_drivers/drivers/clk/ingenic-v2/clk.h
+new file mode 100644
+index 000000000..c636430a8
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/clk.h
+@@ -0,0 +1,594 @@
++#ifndef __INGENIC_CLK_H
++#define __INGENIC_CLK_H
++
++#include <linux/clk-provider.h>
++#include "clk-pll.h"
++#include "clk-div.h"
++#include "clk-bus.h"
++#include "power-gate.h"
++#include <soc/cpm.h>
++
++struct clk;
++
++/**
++ * struct ingenic_clk_provider: information about clock provider
++ * @reg_base: virtual address for the register base.
++ * @clk_data: holds clock related data like clk* and number of clocks.
++ * @lock: maintains exclusion between callbacks for a given clock-provider.
++ */
++struct ingenic_clk_provider {
++	void __iomem *reg_base;
++	struct clk_onecell_data clk_data;
++	spinlock_t lock;
++};
++
++/**
++ * struct ingenic_clock_alias: information about mux clock
++ * @id: platform specific id of the clock.
++ * @dev_name: name of the device to which this clock belongs.
++ * @alias: optional clock alias name to be assigned to this clock.
++ */
++struct ingenic_clock_alias {
++	unsigned int		id;
++	const char		*dev_name;
++	const char		*alias;
++};
++
++#define ALIAS(_id, dname, a)	\
++	{							\
++		.id		= _id,				\
++		.dev_name	= dname,			\
++		.alias		= a,				\
++	}
++
++#define MHZ (1000 * 1000)
++
++/**
++ * struct ingenic_fixed_rate_clock: information about fixed-rate clock
++ * @id: platform specific id of the clock.
++ * @name: name of this fixed-rate clock.
++ * @parent_name: optional parent clock name.
++ * @flags: optional fixed-rate clock flags.
++ * @fixed-rate: fixed clock rate of this clock.
++ */
++struct ingenic_fixed_rate_clock {
++	unsigned int		id;
++	char			*name;
++	const char		*parent_name;
++	unsigned long		flags;
++	unsigned long		fixed_rate;
++};
++
++#define FRATE(_id, cname, pname, f, frate)		\
++	{						\
++		.id		= _id,			\
++		.name		= cname,		\
++		.parent_name	= pname,		\
++		.flags		= (f | CLK_IGNORE_UNUSED),			\
++		.fixed_rate	= frate,		\
++	}
++
++/*
++ * struct ingenic_fixed_factor_clock: information about fixed-factor clock
++ * @id: platform specific id of the clock.
++ * @name: name of this fixed-factor clock.
++ * @parent_name: parent clock name.
++ * @mult: fixed multiplication factor.
++ * @div: fixed division factor.
++ * @flags: optional fixed-factor clock flags.
++ */
++struct ingenic_fixed_factor_clock {
++	unsigned int		id;
++	char			*name;
++	const char		*parent_name;
++	unsigned long		mult;
++	unsigned long		div;
++	unsigned long		flags;
++};
++
++#define FFACTOR(_id, cname, pname, m, d, f)		\
++	{						\
++		.id		= _id,			\
++		.name		= cname,		\
++		.parent_name	= pname,		\
++		.mult		= m,			\
++		.div		= d,			\
++		.flags		= f,			\
++	}
++
++/**
++ * struct ingenic_mux_clock: information about mux clock
++ * @id: platform specific id of the clock.
++ * @dev_name: name of the device to which this clock belongs.
++ * @name: name of this mux clock.
++ * @table: mux table in regs.
++ * @parent_names: array of pointer to parent clock names.
++ * @num_parents: number of parents listed in @parent_names.
++ * @flags: optional flags for basic clock.
++ * @offset: offset of the register for configuring the mux.
++ * @shift: starting bit location of the mux control bit-field in @reg.
++ * @width: width of the mux control bit-field in @reg.
++ * @mux_flags: flags for mux-type clock.
++ * @alias: optional clock alias name to be assigned to this clock.
++ */
++struct ingenic_mux_clock {
++	unsigned int		id;
++	const char		*dev_name;
++	const char		*name;
++	unsigned int 		*table;
++	const char		**parent_names;
++	u8			num_parents;
++	unsigned long		flags;
++	unsigned long		offset;
++	u8			shift;
++	u8			width;
++	u8			mux_flags;
++	const char		*alias;
++};
++
++#define __MUX(_id, dname, cname, tb, pnames, o, s, w, f, mf, a)	\
++	{							\
++		.id		= _id,				\
++		.dev_name	= dname,			\
++		.name		= cname,			\
++		.table 		= tb,				\
++		.parent_names	= pnames,			\
++		.num_parents	= ARRAY_SIZE(pnames),		\
++		.flags		= f, 				\
++		.offset		= o,				\
++		.shift		= s,				\
++		.width		= w,				\
++		.mux_flags	= mf,				\
++		.alias		= a,				\
++	}
++
++#define MUX(_id, cname, tb, pnames, o, s, w, f)			\
++	__MUX(_id, NULL, cname, tb, pnames, o, s, w, f, 0, cname)
++
++#define MUX_A(_id, cname, tb, pnames, o, s, w, a)			\
++	__MUX(_id, NULL, cname, tb, pnames, o, s, w, 0, 0, a)
++
++#define MUX_F(_id, cname, tb, pnames, o, s, w, f, mf)		\
++	__MUX(_id, NULL, cname, tb, pnames, o, s, w, f, mf, NULL)
++
++#define MUX_FA(_id, cname, tb, pnames, o, s, w, f, mf, a)		\
++	__MUX(_id, NULL, cname, tb, pnames, o, s, w, f, mf, a)
++
++/**
++ * @id: platform specific id of the clock.
++ * struct ingenic_div_clock: information about div clock
++ * @dev_name: name of the device to which this clock belongs.
++ * @name: name of this div clock.
++ * @parent_name: name of the parent clock.
++ * @flags: optional flags for basic clock.
++ * @offset: offset of the register for configuring the div.
++ * @shift: starting bit location of the div control bit-field in @reg.
++ * @busy_offset: offset of the register waiting for div stable.
++ * @busy_shift: bit-field of the busy bit in busy_reg, by finding the busy shift, we can also find the ce, and stop bit.
++ * @en_shift: points to some gateble clk in div cfg, ugly we gate clock in div clocks.
++ * @div_flags: divider flags.
++ * @alias: optional clock alias name to be assigned to this clock.
++ * @table: clk div table if possible.
++ */
++struct ingenic_div_clock {
++	unsigned int		id;
++	const char		*dev_name;
++	const char		*name;
++	const char		*parent_name;
++	unsigned long		flags;
++	unsigned long		offset;
++	u8			shift;
++	u8			width;
++
++	unsigned long		busy_offset;
++	int			busy_shift;
++	int			en_shift;
++	int			stop_shift;
++
++	int 			div_flags;
++	const char		*alias;
++	struct clk_div_table	*table;
++};
++
++#define __DIV(_id, dname, cname, pname, o, s, w, bs, e, st, f, df, a, t)	\
++	{							\
++		.id		= _id,				\
++		.dev_name	= dname,			\
++		.name		= cname,			\
++		.parent_name	= pname,			\
++		.flags		= (f | CLK_IGNORE_UNUSED),				\
++		.offset		= o,				\
++		.shift		= s,				\
++		.width		= w,				\
++		.div_flags	= df,				\
++		.busy_shift	= bs,				\
++		.en_shift	= e,				\
++		.stop_shift	= st,				\
++		.alias		= a,				\
++		.table		= t,				\
++	}
++
++#define DIV(_id, cname, pname, o, w, df, t)				\
++	__DIV(_id, NULL, cname, pname, o, 0, w, 28, 29, 27, 0, df, cname, t)
++
++#define DIV_EN(_id, cname, pname, o, s, w, bs, e)				\
++	__DIV(_id, NULL, cname, pname, o, s, w, bs, e, 0, 0, NULL, NULL)
++
++/**
++ * @id: platform specific id of the clock.
++ * struct ingenic_bus_clock: information about div clock
++ * @dev_name: name of the device to which this clock belongs.
++ * @name: name of this div clock.
++ * @parent_name: name of the parent clock.
++ * @flags: optional flags for basic clock.
++ * @cfg_offset: offset of the register for configuring the div.
++ * @div_shift: starting bit location of the div control bit-field in @reg.
++ * @div_width: bit width of the div field.
++ * @busy_offset: offset of the register waiting for div stable.
++ * @busy_shift: bit-field of the busy bit in busy_reg, by finding the busy shift, we can also find the ce, and stop bit.
++ * @en_shift: points to some gateble clk in div cfg, ugly we gate clock in div clocks.
++ * @div_flags: flags for div-type clock, For example, DIV_NO_BUSY.
++ * @alias: optional clock alias name to be assigned to this clock.
++ * @table: clk div table if possible.
++ */
++
++
++struct ingenic_bus_clock {
++	unsigned int		id;
++	const char		*dev_name;
++	const char		*name;
++	const char		*parent_name;
++	unsigned long		flags;
++	unsigned long		cfg_offset;
++	u8			div_shift1;
++	u8			div_width1;
++	u8			div_shift2;
++	u8			div_width2;
++	int 	  		ce_shift;
++
++	int 			busy_offset;
++	int			busy_shift;
++
++	int 			div_flags;
++	int 			div_flags_2;
++	const char		*alias;
++	struct clk_div_table	*table;
++};
++
++#define __BUS_DIV(_id, dname, cname, pname, o, s1, w1, s2, w2, bo, bs, ce, f, df, df2, a, t)	\
++	{							\
++		.id		= _id,				\
++		.dev_name	= dname,			\
++		.name		= cname,			\
++		.parent_name	= pname,			\
++		.flags		= (f | CLK_IGNORE_UNUSED),	\
++		.cfg_offset	= o,				\
++		.div_shift1	= s1,				\
++		.div_width1	= w1,				\
++		.div_shift2	= s2,				\
++		.div_width2	= w2,				\
++		.ce_shift	= ce,				\
++		.busy_offset	= bo,				\
++		.busy_shift	= bs,				\
++		.div_flags	= df,				\
++		.alias		= a,				\
++		.table		= t,				\
++		.div_flags_2	= df2,				\
++	}
++
++#define BUS_DIV(_id, cname, pname, o, s1, w1, s2, w2, bo, bs, ce, df2)				\
++	__BUS_DIV(_id, NULL, cname, pname, o, s1, w1, s2, w2, bo, bs, ce, CLK_GET_RATE_NOCACHE, 0, df2, cname, NULL)
++
++
++
++struct ingenic_fra_div_clock {
++	unsigned int		id;
++	const char		*dev_name;
++	const char		*name;
++	const char		*parent_name;
++	unsigned long		flags;
++
++	unsigned long		offset;
++	u8			mshift;
++	u8			mwidth;
++	u8			nshift;
++	u8			nwidth;
++
++	int 			div_flags;
++	const char		*alias;
++};
++
++#define __FRA_DIV(_id, dname, cname, pname, f, o, ms, mw, ns, nw, df, a)	\
++	{									\
++		.id		= _id,		\
++		.dev_name	= dname,	\
++		.name		= cname,	\
++		.parent_name	= pname,	\
++		.flags		= f,		\
++		.offset		= o,		\
++		.mshift		= ms,		\
++		.mwidth		= mw,		\
++		.nshift		= ns,		\
++		.nwidth		= nw,		\
++		.div_flags	= df,		\
++		.alias		= a,		\
++	}
++
++#define FRA_DIV(_id, cname, pname, o, ms, mw, ns, nw)	\
++	__FRA_DIV(_id, NULL, cname, pname, 0, o, ms, mw, ns, nw, 0, cname)
++
++/**
++ * struct ingenic_gate_clock: information about gate clock
++ * @id: platform specific id of the clock.
++ * @dev_name: name of the device to which this clock belongs.
++ * @name: name of this gate clock.
++ * @parent_name: name of the parent clock.
++ * @pwc_name: name of the power control clk under this clock gate.
++ * @flags: optional flags for basic clock.
++ * @offset: offset of the register for configuring the gate.
++ * @bit_idx: bit index of the gate control bit-field in @reg.
++ * @sram_offset: offset of the corresponding sram contrl reg.
++ * @sram_shift: shift for the sram control bit idx in sram_reg.
++ * @gate_flags: flags for gate-type clock.
++ * @alias: optional clock alias name to be assigned to this clock.
++ * @gate_flags: flags for gate clock.
++ * @alias: alias name for this clock.
++ */
++struct ingenic_gate_clock {
++	unsigned int		id;
++	const char		*dev_name;
++	const char		*name;
++	const char		*parent_name;
++
++	unsigned long		flags;
++	unsigned long		offset;
++	u8			bit_idx;
++	int			sram_offset;
++	int			sram_shift;
++	u8			gate_flags;
++	const char		*alias;
++
++};
++
++#define __GATE(_id, dname, cname, pname, o, b, f, so, sps, gf, a)	\
++	{							\
++		.id		= _id,				\
++		.dev_name	= dname,			\
++		.name		= cname,			\
++		.parent_name	= pname,			\
++		.flags		= f,				\
++		.offset		= o,				\
++		.bit_idx	= b,				\
++		.sram_offset	= so,				\
++		.sram_shift 	= sps,				\
++		.gate_flags	= gf,				\
++		.alias		= a,				\
++	}
++
++#define GATE(_id, cname, pname, o, b, f, gf)			\
++	__GATE(_id, NULL, cname, pname, o, b, f, -1, -1, gf, cname)
++
++
++#define GATE_SRAM(_id, cname, pname, o, b, f, gf, so, sps)			\
++	__GATE(_id, NULL, cname, pname, NULL, o, b, f, so, sps, gf, cname)
++
++
++/**
++ * struct ingenic_power_clock: information about power clock
++ * @id: platform specific id of the clock.
++ * @dev_name: name of the device to which this clock belongs.
++ * @name: name of this gate clock.
++ * @parent_name: name of the parent clock.
++ * @flags: optional flags for basic clock.
++ * @offset: offset of the register for configuring the gate.
++ * @ctrl_bit: bit index of the power control bit-field in @reg.
++ * @wait_bit: bit index of the power status bit-field in @reg.
++ * @delay_ms: wait for ms time stable @reg.
++ * @gate_flags: flags for gate-type clock.
++ * @alias: optional clock alias name to be assigned to this clock.
++ * @clk_flags: ingneic special flags.
++ */
++struct ingenic_gate_power {
++	unsigned int		id;
++	const char		*dev_name;
++	const char		*name;
++	const char		*parent_name;
++
++	unsigned long		flags;
++	unsigned long		offset;
++	u8			ctrl_bit;
++	u8			wait_bit;
++	u8			gate_flags;
++	const char		*alias;
++	unsigned long 		power_flags;
++};
++
++#define __POWER(_id, dname, cname, pname, f, o, cb, wb, gf, a, pf)	\
++	{							\
++		.id		= _id,				\
++		.dev_name	= dname,			\
++		.name		= cname,			\
++		.parent_name	= pname,			\
++		.flags		= f,				\
++		.offset		= o,				\
++		.ctrl_bit	= cb,				\
++		.wait_bit	= wb,				\
++		.gate_flags	= gf,				\
++		.alias		= a,				\
++		.power_flags	= pf,				\
++	}
++
++#define POWER(_id, cname, pname, o, cb, wb, f, gf, pf)			\
++	__POWER(_id, NULL, cname, pname, f, o, cb, wb, gf, cname, pf)
++
++#define PNAME(x) static const char *x[] __initdata
++
++#define REG_SLEEP(o, c, b, f)	\
++{	\
++	.offset = o,	\
++	.ce = c,	\
++	.busy = b,	\
++	.flags = f,	\
++}
++
++/**
++ * struct ingenic_clk_reg_sleep: register dump of clock controller registers.
++ * @offset: clock register offset from the controller base address.
++ * @value: the value to be register at offset.
++ */
++struct ingenic_clk_reg_sleep {
++	u32	offset;
++	u32	value;
++	u32	ce;
++	u32	busy;
++	u32	flags;
++};
++
++
++/**
++ * struct ingenic_pll_clock: information about pll clock
++ * @id: platform specific id of the clock.
++ * @dev_name: name of the device to which this clock belongs.
++ * @name: name of this pll clock.
++ * @parent_name: name of the parent clock.
++ * @flags: optional flags for basic clock.
++ * @con_offset: offset of the register for configuring the PLL.
++ * @lock_offset: offset of the register for locking the PLL.
++ * @type: Type of PLL to be registered.
++ * @alias: optional clock alias name to be assigned to this clock.
++ */
++struct ingenic_pll_clock {
++	unsigned int		id;
++	const char		*dev_name;
++	const char		*name;
++	const char		*parent_name;
++
++	unsigned long		flags;
++	int			con_offset;
++	int			lock_offset;
++	const char              *alias;
++	struct ingenic_pll_hwdesc *hwdesc;
++	struct ingenic_pll_rate_table *rate_table;
++};
++
++#define PLL(_id, _name, _parent_name, _hwdesc, _rtable)	\
++{	\
++	.id = _id,	\
++	.dev_name = _name,	\
++	.name = _name,	\
++	.parent_name = _parent_name,	\
++	.hwdesc = _hwdesc,	\
++	.rate_table = _rtable,	\
++}
++
++struct ingenic_clock_reg_cache {
++	struct list_head node;
++	void __iomem *reg_base;
++	struct ingenic_clk_reg_sleep *reg_sleep;
++	unsigned int nr_reg_sleep;
++};
++
++struct ingenic_cmu_info {
++	/* list of pll clocks and respective count */
++	struct ingenic_pll_clock *pll_clks;
++	unsigned int nr_pll_clks;
++	/* list of mux clocks and respective count */
++	struct ingenic_mux_clock *mux_clks;
++	unsigned int nr_mux_clks;
++	/* list of div clocks and respective count */
++	struct ingenic_div_clock *div_clks;
++	unsigned int nr_div_clks;
++	/* list of gate clocks and respective count */
++	struct ingenic_gate_clock *gate_clks;
++	unsigned int nr_gate_clks;
++	/* list of fixed clocks and respective count */
++	struct ingenic_fixed_rate_clock *fixed_clks;
++	unsigned int nr_fixed_clks;
++	/* list of fixed factor clocks and respective count */
++	struct ingenic_fixed_factor_clock *fixed_factor_clks;
++	unsigned int nr_fixed_factor_clks;
++	/* total number of clocks with IDs assigned*/
++	unsigned int nr_clk_ids;
++
++	/* list and number of clocks registers */
++	unsigned long *clk_regs;
++	unsigned int nr_clk_regs;
++};
++
++struct ingenic_cpm_info {
++	struct ingenic_power_clock *pwc_clks;
++	unsigned int nr_pwc_clks;
++
++};
++
++extern struct ingenic_clk_provider *__init ingenic_clk_init(
++			struct device_node *np, void __iomem *base,
++			unsigned long nr_clks);
++extern void __init ingenic_clk_of_add_provider(struct device_node *np,
++			struct ingenic_clk_provider *ctx);
++extern void __init ingenic_clk_of_register_fixed_ext(
++			struct ingenic_clk_provider *ctx,
++			struct ingenic_fixed_rate_clock *fixed_rate_clk,
++			unsigned int nr_fixed_rate_clk,
++			const struct of_device_id *clk_matches);
++
++extern void ingenic_clk_add_lookup(struct ingenic_clk_provider *ctx,
++			struct clk *clk, unsigned int id);
++
++extern void __init ingenic_clk_register_alias(struct ingenic_clk_provider *ctx,
++			const struct ingenic_clock_alias *list,
++			unsigned int nr_clk);
++extern void __init ingenic_clk_register_fixed_rate(
++			struct ingenic_clk_provider *ctx,
++			const struct ingenic_fixed_rate_clock *clk_list,
++			unsigned int nr_clk);
++extern void __init ingenic_clk_register_fixed_factor(
++			struct ingenic_clk_provider *ctx,
++			const struct ingenic_fixed_factor_clock *list,
++			unsigned int nr_clk);
++extern void __init ingenic_clk_register_mux(struct ingenic_clk_provider *ctx,
++			const struct ingenic_mux_clock *clk_list,
++			unsigned int nr_clk);
++extern void __init ingenic_clk_register_cgu_div(struct ingenic_clk_provider *ctx,
++			const struct ingenic_div_clock *clk_list,
++			unsigned int nr_clk);
++
++extern void __init ingenic_clk_register_gate(struct ingenic_clk_provider *ctx,
++				const struct ingenic_gate_clock *list,
++				unsigned int nr_clk);
++
++extern void __init ingenic_power_register_gate(struct ingenic_clk_provider *ctx,
++				const struct ingenic_gate_power *list,
++				unsigned int nr_clk);
++
++extern void __init ingenic_clk_register_pll(struct ingenic_clk_provider *ctx,
++			const struct ingenic_pll_clock *pll_list,
++			unsigned int nr_clk, void __iomem *base);
++
++extern struct ingenic_clk_provider __init *ingenic_cmu_register_one(
++			struct device_node *,
++			struct ingenic_cmu_info *);
++
++extern unsigned long _get_rate(const char *clk_name);
++
++extern void ingenic_clk_save(void __iomem *base,
++			struct ingenic_clk_reg_sleep *rd,
++			unsigned int num_regs);
++extern void ingenic_clk_restore(void __iomem *base,
++			struct ingenic_clk_reg_sleep *rd,
++			unsigned int num_regs);
++
++extern void __init ingenic_clk_register_bus_div(struct ingenic_clk_provider *ctx,
++				const struct ingenic_bus_clock *list,
++				unsigned int nr_clk);
++
++extern void __init ingenic_clk_register_fra_div(struct ingenic_clk_provider *ctx,
++					const struct ingenic_fra_div_clock *list,
++					unsigned int nr_clk);
++
++extern void __init ingenic_clk_sleep_init(void __iomem *reg_base,
++		struct ingenic_clk_reg_sleep *rdump,
++		unsigned long nr_rdump);
++
++void ingenic_clk_of_dump(struct ingenic_clk_provider *ctx);
++#endif /* __INGENIC_CLK_H */
+diff --git a/module_drivers/drivers/clk/ingenic-v2/power-gate.c b/module_drivers/drivers/clk/ingenic-v2/power-gate.c
+new file mode 100644
+index 000000000..91bd19a2c
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/power-gate.c
+@@ -0,0 +1,197 @@
++/*
++ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
++ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Gated clock implementation
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/io.h>
++#include <linux/err.h>
++#include <linux/string.h>
++
++#include "power-gate.h"
++
++
++struct power_gate {
++	struct clk_hw hw;
++	void __iomem    *reg;
++	u8              ctrl_bit;
++	u8              wait_bit;
++	u8              flags;
++	unsigned long   power_flags;
++	spinlock_t      *lock;
++
++};
++
++
++/**
++ * DOC: basic gatable clock which can gate and ungate it's ouput
++ *
++ * Traits of this clock:
++ * prepare - clk_(un)prepare only ensures parent is (un)prepared
++ * enable - clk_enable and clk_disable are functional & control gating
++ * rate - inherits rate from parent.  No clk_set_rate support
++ * parent - fixed parent.  No clk_set_parent support
++ */
++
++#define to_power_gate(_hw) container_of(_hw, struct power_gate, hw)
++
++/*
++ * It works on following logic:
++ *
++ * For enabling clock, enable = 1
++ *	set2dis = 1	-> clear bit	-> set = 0
++ *	set2dis = 0	-> set bit	-> set = 1
++ *
++ * For disabling clock, enable = 0
++ *	set2dis = 1	-> set bit	-> set = 1
++ *	set2dis = 0	-> clear bit	-> set = 0
++ *
++ * So, result is always: enable xor set2dis.
++ */
++static int power_gate_is_enabled(struct clk_hw *hw)
++{
++	u32 reg;
++	struct power_gate *gate = to_power_gate(hw);
++
++	reg = readl(gate->reg);
++
++	/* if a set bit disables this clk, flip it before masking */
++	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
++		reg ^= BIT(gate->wait_bit);
++
++	reg &= BIT(gate->wait_bit);
++
++	return reg ? 1 : 0;
++}
++
++static void power_gate_endisable(struct clk_hw *hw, int enable)
++{
++	struct power_gate *gate = to_power_gate(hw);
++	int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
++	unsigned long flags;
++	u32 reg;
++
++	set ^= enable;
++
++	if (gate->lock)
++		spin_lock_irqsave(gate->lock, flags);
++	else
++		__acquire(gate->lock);
++
++	reg = readl(gate->reg);
++
++	if (set)
++		reg |= BIT(gate->ctrl_bit);
++	else
++		reg &= ~BIT(gate->ctrl_bit);
++	writel(reg, gate->reg);
++
++	if (gate->lock)
++		spin_unlock_irqrestore(gate->lock, flags);
++	else
++		__release(gate->lock);
++}
++
++static int power_gate_enable(struct clk_hw *hw)
++{
++	struct power_gate *gate = to_power_gate(hw);
++
++	power_gate_endisable(hw, 1);
++
++	if (gate->power_flags & POWER_GATE_WAIT) {
++		while (!power_gate_is_enabled(hw));
++	}
++
++	return 0;
++}
++
++static void power_gate_disable(struct clk_hw *hw)
++{
++	struct power_gate *gate = to_power_gate(hw);
++
++	power_gate_endisable(hw, 0);
++
++	if (gate->power_flags & POWER_GATE_WAIT) {
++		while (power_gate_is_enabled(hw));
++	}
++}
++
++const struct clk_ops power_gate_ops = {
++	.enable = power_gate_enable,
++	.disable = power_gate_disable,
++	.is_enabled = power_gate_is_enabled,
++};
++EXPORT_SYMBOL_GPL(power_gate_ops);
++
++/**
++ * clk_register_gate - register a gate clock with the clock framework
++ * @dev: device that is registering this clock
++ * @name: name of this clock
++ * @parent_name: name of this clock's parent
++ * @flags: framework-specific flags for this clock
++ * @reg: register address to control gating of this clock
++ * @bit_idx: which bit in the register controls gating of this clock
++ * @clk_gate_flags: gate-specific flags for this clock
++ * @lock: shared register lock for this clock
++ */
++struct clk *power_register_gate(struct device *dev, const char *name,
++		const char *parent_name, unsigned long flags,
++		void __iomem *reg, u8 ctrl_bit, u8 wait_bit,
++		u8 clk_gate_flags, unsigned long power_flags, spinlock_t *lock)
++{
++	struct power_gate *gate;
++	struct clk *clk;
++	struct clk_init_data init;
++
++	/* allocate the gate */
++	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
++	if (!gate)
++		return ERR_PTR(-ENOMEM);
++
++	init.name = name;
++	init.ops = &power_gate_ops;
++	init.flags = flags;
++	init.parent_names = (parent_name ? &parent_name: NULL);
++	init.num_parents = (parent_name ? 1 : 0);
++
++	/* struct power_gate assignments */
++	gate->reg = reg;
++	gate->ctrl_bit = ctrl_bit;
++	gate->wait_bit = wait_bit;
++	gate->flags = clk_gate_flags;
++	gate->power_flags = power_flags;
++	gate->lock = lock;
++	gate->hw.init = &init;
++
++	clk = clk_register(dev, &gate->hw);
++
++	if (IS_ERR(clk))
++		kfree(gate);
++
++	return clk;
++}
++EXPORT_SYMBOL_GPL(power_register_gate);
++
++void power_unregister_gate(struct clk *clk)
++{
++	struct power_gate *gate;
++	struct clk_hw *hw;
++
++	hw = __clk_get_hw(clk);
++	if (!hw)
++		return;
++
++	gate = to_power_gate(hw);
++
++	clk_unregister(clk);
++	kfree(gate);
++}
++EXPORT_SYMBOL_GPL(power_unregister_gate);
+diff --git a/module_drivers/drivers/clk/ingenic-v2/power-gate.h b/module_drivers/drivers/clk/ingenic-v2/power-gate.h
+new file mode 100644
+index 000000000..bcf34c8b8
+--- /dev/null
++++ b/module_drivers/drivers/clk/ingenic-v2/power-gate.h
+@@ -0,0 +1,14 @@
++#ifndef __INGENIC_POWER_GATE_H
++#define __INGENIC_CLK_CGU_DIVIDER_H
++
++
++#define POWER_GATE_WAIT	BIT(1)
++
++struct clk *power_register_gate(struct device *dev, const char *name,
++		const char *parent_name, unsigned long flags,
++		void __iomem *reg, u8 ctrl_bit, u8 wait_bit,
++		u8 clk_gate_flags, unsigned long power_flags, spinlock_t *lock);
++
++void power_unregister_gate(struct clk *clk);
++
++#endif /* __SAMSUNG_CLK_PLL_H */
+diff --git a/module_drivers/drivers/clocksource/Kconfig b/module_drivers/drivers/clocksource/Kconfig
+new file mode 100644
+index 000000000..18c97e867
+--- /dev/null
++++ b/module_drivers/drivers/clocksource/Kconfig
+@@ -0,0 +1,16 @@
++config CLKSRC_INGENIC_SYS_OST
++        bool "OST clocksource."
++        select CLKSRC_OF
++	depends on SOC_X1600
++	help
++	    sys ost for ingenic xburst base socs.
++
++config CLKSRC_INGENIC_CORE_OST
++        bool "Core OST clocksource."
++        select CLKSRC_OF
++	depends on SOC_X2000 || SOC_X2000_V12 || SOC_M300 || SOC_X2100 || SOC_X2500
++        help
++          core sys ost for ingenic xburst2 based SOCs. each cpu has
++          an ost and all cpu shares a global clocksource.
++
++
+diff --git a/module_drivers/drivers/clocksource/Makefile b/module_drivers/drivers/clocksource/Makefile
+new file mode 100644
+index 000000000..13c2dad38
+--- /dev/null
++++ b/module_drivers/drivers/clocksource/Makefile
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_CLKSRC_INGENIC_SYS_OST)            += ingenic_sysost.o
++obj-$(CONFIG_CLKSRC_INGENIC_CORE_OST)           += ingenic_core_ost.o
+diff --git a/module_drivers/drivers/clocksource/ingenic_core_ost.c b/module_drivers/drivers/clocksource/ingenic_core_ost.c
+new file mode 100644
+index 000000000..f30f5d482
+--- /dev/null
++++ b/module_drivers/drivers/clocksource/ingenic_core_ost.c
+@@ -0,0 +1,569 @@
++/*
++ * Setting up the xburst2 system ost, including:
++ *		---->	core system ost;
++ *		---->	global system ost.
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ *  Author: dongsheng.qiu, dongsheng.qiu@ingenic.com
++ *  	Modified by qipengzhen, aric.pzqi@ingenic.com
++ *
++ *  This program is free software; you can distribute it and/or modify it
++ *  under the terms of the GNU General Public License (Version 2) as
++ *  published by the Free Software Foundation.
++ *
++ *  This program is distributed in the hope it will be useful, but WITHOUT
++ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++ *  for more details.
++ *
++ *  You should have received a copy of the GNU General Public License along
++ *  with this program; if not, write to the Free Software Foundation, Inc.,
++ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ */
++
++/* #define DEBUG */
++/* #define VERBOSE_DEBUG */
++
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/err.h>
++#include <linux/time.h>
++#include <linux/clockchips.h>
++#include <linux/sched_clock.h>
++#include <linux/clk.h>
++#include <linux/notifier.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <linux/delay.h>
++#include <linux/cpu.h>
++#include <linux/delay.h>
++
++#include <dt-bindings/interrupt-controller/mips-irq.h>
++
++#define OSTCCR 0x00
++#define OSTER  0x04
++#define OSTCR  0x08
++#define OSTFR  0x0C
++#define OSTMR  0x10
++#define OSTDFR 0x14
++#define OSTCNT 0x18
++
++#define G_OSTCCR   0x00
++#define G_OSTER    0x04
++#define G_OSTCR    0x08
++#define G_OSTCNTH  0x0C
++#define G_OSTCNTL  0x10
++#define G_OSTCNTB  0x14
++/*-----------------------------------------------------------------------------
++ *  -- global ost, clocksource, the whole system shares only one.
++ *  -- core ost, each cpu owns one.
++ *
++ *	   -----------------------------------------------
++ *        |		  |	        |		  |
++ *	  |	      --------	    --------           --------
++ *	  |	     |  cpu0  |	   |  cpu1  |	      |  cpuN  |
++ *	  |	      --------	    --------           --------
++ *	  |		  ^		^		  ^
++ *	  V		  |		|		  |
++ *   ------------    ------------   -----------       -----------
++ *  | global OST |   | core ost0 | | core ost1 | ... | core ostN |
++ *   ------------     -----------   -----------       -----------
++ *
++ *-----------------------------------------------------------------------------*/
++
++struct cpu_ost_map {
++	unsigned int cpu_num;
++	unsigned int dev_base;
++};
++static struct cpu_ost_map cpu_ost_map[NR_CPUS];
++
++struct core_timerevent {
++	struct clock_event_device clkevt;
++	struct irqaction evt_action;
++	void __iomem *iobase;
++	unsigned int rate;
++	raw_spinlock_t	lock;
++	unsigned int prev_set;
++};
++
++static struct core_timerevent timerevent_buf[NR_CPUS];
++#define CLK_DIV  1
++#define CSRDIV(x)      ({int n = 0;int d = x; while(d){ d >>= 2;n++;};(n-1);})
++
++#define ost_readl(reg)			readl(reg)
++#define ost_writel(value,reg)	writel(value, reg)
++
++struct tmr_src {
++	struct clocksource cs;
++	struct core_global_ost_resource *resource;
++	struct clk *clk_gate;
++	void __iomem *iobase;
++	raw_spinlock_t	lock;
++};
++#ifdef CONFIG_SMP
++#define ost_lock(lock,flags) raw_spin_lock_irqsave(&(lock),flags)
++#define ost_unlock(lock,flags) raw_spin_unlock_irqrestore(&(lock),flags)
++#else
++#define ost_lock(lock,flags) (flags = 0)
++#define ost_unlock(lock,flags) (flags = 0)
++#endif
++
++struct core_ost_chip{
++	struct tmr_src *tmrsrc;
++
++	struct core_timerevent* __percpu *percpu_timerevent;
++	struct clk *core_gate;
++	void __iomem *iobase;
++	unsigned int rate;
++	int irq;
++} g_core_ost;
++
++static raw_spinlock_t clocksource_lock;
++
++static u64 core_clocksource_get_cycles(struct clocksource *cs)
++{
++	union clycle_type {
++		u64 cycle64;
++		unsigned int cycle32[2];
++	} cycle;
++	struct tmr_src *tmr = container_of(cs,struct tmr_src,cs);
++	unsigned long flags;
++	raw_spin_lock_irqsave(&clocksource_lock,flags);
++	void __iomem *iobase = tmr->iobase;
++
++	do {
++		cycle.cycle32[1] = ost_readl(iobase + G_OSTCNTH);
++		cycle.cycle32[0] = ost_readl(iobase + G_OSTCNTL);
++	} while(cycle.cycle32[1] != ost_readl(iobase + G_OSTCNTH));
++	raw_spin_unlock_irqrestore(&clocksource_lock,flags);
++
++	return cycle.cycle64;
++}
++
++static int tmr_src_enable(struct clocksource *cs)
++{
++	struct tmr_src *tmr = container_of(cs,struct tmr_src,cs);
++	void __iomem *iobase = tmr->iobase;
++	unsigned long flags;
++	ost_lock(tmr->lock,flags);
++	ost_writel(1,iobase + G_OSTER);
++	ost_unlock(tmr->lock,flags);
++	return 0;
++}
++
++static 	void tmr_src_disable(struct clocksource *cs)
++{
++	struct tmr_src *tmr = container_of(cs,struct tmr_src,cs);
++	void __iomem *iobase = tmr->iobase;
++	unsigned long flags;
++	ost_lock(tmr->lock,flags);
++	ost_writel(0,iobase + G_OSTER);
++	ost_unlock(tmr->lock,flags);
++}
++static	void tmr_src_suspend(struct clocksource *cs)
++{
++	struct tmr_src *tmr = container_of(cs,struct tmr_src,cs);
++	struct core_ost_chip *core_ost = &g_core_ost;
++
++	if(core_ost->core_gate)
++		clk_disable_unprepare(core_ost->core_gate);
++	if(tmr->clk_gate)
++		clk_disable_unprepare(tmr->clk_gate);
++}
++static void tmr_src_resume(struct clocksource *cs)
++{
++	struct tmr_src *tmr = container_of(cs,struct tmr_src,cs);
++	struct core_ost_chip *core_ost = &g_core_ost;
++
++	if(tmr->clk_gate)
++		clk_prepare_enable(tmr->clk_gate);
++	if(core_ost->core_gate)
++		clk_prepare_enable(core_ost->core_gate);
++
++}
++static struct tmr_src g_tmr_src = {
++	.cs = {
++		.name 		= "jz_clocksource",
++		.rating		= 400,
++		.read		= core_clocksource_get_cycles,
++		.mask		= 0x7FFFFFFFFFFFFFFFULL,
++		.shift 		= 10,
++		.flags		= CLOCK_SOURCE_WATCHDOG | CLOCK_SOURCE_IS_CONTINUOUS,
++		.enable         = tmr_src_enable,
++		.disable        = tmr_src_disable,
++		.suspend        = tmr_src_suspend,
++		.resume         = tmr_src_resume,
++	}
++};
++
++static unsigned long long sched_clock(void)
++{
++	struct tmr_src *tmr = &g_tmr_src;
++	if(!tmr->iobase)
++		return 0LL;
++	if(!ost_readl(tmr->iobase + G_OSTER))
++		return 0LL;
++	return ((u64)core_clocksource_get_cycles(&tmr->cs)); // * tmr_src.cs.mult) >> tmr_src.cs.shift;
++}
++
++void __init core_clocksource_init(struct core_ost_chip *core_ost, struct tmr_src *tmr)
++{
++	unsigned long hz;
++	void __iomem *iobase;
++
++	core_ost->tmrsrc = tmr;
++	tmr->cs.mult = clocksource_hz2mult(core_ost->rate, tmr->cs.shift);
++	iobase = tmr->iobase;
++
++	if(tmr->clk_gate)
++		clk_prepare_enable(tmr->clk_gate);
++
++	hz = core_ost->rate;
++
++	raw_spin_lock_init(&clocksource_lock);
++
++	raw_spin_lock_init(&tmr->lock);
++	ost_writel(0,iobase + G_OSTER);
++	ost_writel(CSRDIV(CLK_DIV),iobase + OSTCCR);
++	ost_writel(1,iobase + G_OSTCR);
++
++	clocksource_register_hz(&tmr->cs, hz);
++	sched_clock_register(sched_clock, 64, hz);
++}
++
++static int core_timerevent_set_next_event(unsigned long evt,
++			     struct clock_event_device *clk_evt_dev)
++{
++	struct core_timerevent *evt_dev = container_of(clk_evt_dev, struct core_timerevent, clkevt);
++	void __iomem *iobase = evt_dev->iobase;
++	unsigned long flags;
++	ost_lock(evt_dev->lock,flags);
++	if(evt <= 1) {
++		WARN_ON(1);
++		evt = 2;
++	}
++	ost_writel(0,iobase + OSTER);
++	if(!ost_readl(iobase + OSTFR))
++	{
++		ost_writel(evt,iobase + OSTDFR);
++		ost_writel(1,iobase + OSTCR);
++		ost_writel(1,iobase + OSTER);
++	}else{
++		//pr_err("OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO evt = %ld\n",evt);
++		evt_dev->prev_set = evt;
++	}
++
++	ost_unlock(evt_dev->lock,flags);
++	return 0;
++}
++extern void sysrq_handle_showallcpus(int key);
++extern void sysrq_handle_showlocks(int key);
++static int time_count[4] = {100,100,100,100};
++static irqreturn_t core_timerevent_interrupt(int irq, void *dev_id)
++{
++	struct core_timerevent *evt_dev =  *(struct core_timerevent **)dev_id;
++	void __iomem *iobase = evt_dev->iobase;
++	int cpu = smp_processor_id();
++	unsigned long flags;
++	if (ost_readl(iobase + OSTFR)){
++#if 0
++		if(time_count[cpu] >= 1000) {
++#if 0
++			printk("\n\n---timer interrupt , 100 count, on cpu: %d %x %x\n", cpu,read_c0_status(),read_c0_cause());
++			 printk("intc src0:%x: %x\n", 0xb2300000 + cpu * 0x1000, *(volatile unsigned int *)(0xb2300000 + cpu * 0x1000 ));
++			 printk("intc msk0:%x: %x\n", 0xb2300004 + cpu * 0x1000, *(volatile unsigned int *)(0xb2300004 + cpu * 0x1000 ));
++			 printk("intc pnd0:%x: %x\n", 0xb2300010 + cpu * 0x1000, *(volatile unsigned int *)(0xb2300010 + cpu * 0x1000 ));
++			 printk("intc src1:%x: %x\n", 0xb2300020 + cpu * 0x1000, *(volatile unsigned int *)(0xb2300020 + cpu * 0x1000 ));
++			 printk("intc msk1:%x: %x\n", 0xb2300024 + cpu * 0x1000, *(volatile unsigned int *)(0xb2300024 + cpu * 0x1000 ));
++			 printk("intc pnd1:%x: %x\n", 0xb2300030 + cpu * 0x1000, *(volatile unsigned int *)(0xb2300030 + cpu * 0x1000 ));
++			 printk("ccu  msk: %x: %x\n", 0xb2200120, *(volatile unsigned int *)(0xb2200120));
++			 printk("ccu  pnd: %x: %x\n", 0xb2200100, *(volatile unsigned int *)(0xb2200100));
++
++			printk("uart0 ier: %x\n", *(volatile unsigned int *)0xb0030004);
++			printk("uart0 isr: %x\n", *(volatile unsigned int *)0xb0030014);
++
++			 printk("\n\n");
++#endif
++			time_count[cpu] = 0;
++		}
++		time_count[cpu]++;
++#endif
++		ost_lock(evt_dev->lock,flags);
++		ost_writel(0,iobase + OSTFR);
++
++		if( clockevent_state_oneshot(&evt_dev->clkevt) ||
++				clockevent_state_oneshot_stopped(&evt_dev->clkevt)) {
++			if(evt_dev->prev_set == 0){
++				ost_writel(0,iobase + OSTER);
++			}else{
++				ost_writel(evt_dev->prev_set,iobase + OSTDFR);
++				ost_writel(1,iobase + OSTCR);
++				ost_writel(1,iobase + OSTER);
++				evt_dev->prev_set = 0;
++			}
++
++		}
++
++		ost_unlock(evt_dev->lock,flags);
++		evt_dev->clkevt.event_handler(&evt_dev->clkevt);
++	}else{
++		pr_err("\nERROR: cpu: %d c0_status:%x c0_cause:%x\n", cpu,read_c0_status(),read_c0_cause());
++		pr_err("CPU[%d]: ost couldn't find ostfr.\n",cpu);
++	}
++	return IRQ_HANDLED;
++}
++
++static int set_state_periodic(struct clock_event_device *clkevt)
++{
++	struct core_timerevent *evt_dev = container_of(clkevt,struct core_timerevent,clkevt);
++	void __iomem *iobase = evt_dev->iobase;
++	unsigned int latch = (evt_dev->rate + (HZ >> 1)) / HZ;
++	unsigned long flags;
++
++	ost_lock(evt_dev->lock,flags);
++
++	ost_writel(latch,iobase + OSTDFR);
++	ost_writel(1,iobase + OSTER);
++	ost_unlock(evt_dev->lock,flags);
++	return 0;
++}
++#if 0
++static int set_state_oneshot(struct clock_event_device *clkevt)
++{
++	struct core_timerevent *evt_dev = container_of(clkevt,struct core_timerevent,clkevt);
++	void __iomem *iobase = evt_dev->iobase;
++	unsigned int latch = (evt_dev->rate + (HZ >> 1)) / HZ;
++	unsigned long flags;
++
++	ost_lock(evt_dev->lock,flags);
++	ost_writel(latch,iobase + OSTDFR);
++	ost_writel(1,iobase + OSTER);
++	ost_unlock(evt_dev->lock,flags);
++	return 0;
++
++}
++static int set_state_oneshot_stopped(struct clock_event_device *clkevt)
++{
++	struct core_timerevent *evt_dev = container_of(clkevt,struct core_timerevent,clkevt);
++	void __iomem *iobase = evt_dev->iobase;
++	unsigned long flags;
++
++	ost_lock(evt_dev->lock,flags);
++	ost_writel(1,iobase + OSTER);
++	ost_unlock(evt_dev->lock,flags);
++	return 0;
++}
++#endif
++
++static int set_state_shutdown(struct clock_event_device *clkevt)
++{
++	struct core_timerevent *evt_dev = container_of(clkevt,struct core_timerevent,clkevt);
++	void __iomem *iobase = evt_dev->iobase;
++	unsigned long flags;
++
++	ost_lock(evt_dev->lock,flags);
++	ost_writel(0,iobase + OSTER);
++	ost_unlock(evt_dev->lock,flags);
++	return 0;
++}
++#if 0
++static int tick_resume(struct clock_event_device *clkevt)
++{
++	struct core_timerevent *evt_dev = container_of(clkevt,struct core_timerevent,clkevt);
++	void __iomem *iobase = evt_dev->iobase;
++	unsigned int latch = (evt_dev->rate + (HZ >> 1)) / HZ;
++	unsigned long flags;
++	unsigned int val;
++
++	ost_lock(evt_dev->lock,flags);
++	val = ost_readl(iobase + OSTCNT);
++	if(val >= latch)
++		ost_writel(latch,iobase + OSTDFR);
++	ost_writel(1,iobase + OSTER);
++
++	ost_unlock(evt_dev->lock,flags);
++
++	return 0;
++}
++#endif
++
++static void percpu_timerevent_init(struct core_ost_chip *core_ost, int cpu_num)
++{
++	int i;
++	void __iomem *iobase;
++	unsigned int base = 0;
++	struct core_timerevent *timerevent = NULL;
++	struct clock_event_device *cd = NULL;
++	pr_info("percpu cpu_num:%d timerevent init\n",cpu_num);
++	for(i = 0;i < NR_CPUS;i++)
++	{
++		if(cpu_ost_map[i].cpu_num == cpu_num) {
++			base = cpu_ost_map[i].dev_base;
++			timerevent = &timerevent_buf[i];
++			break;
++		}
++	}
++
++	if(base == 0){
++		pr_err("Error: CPU[%d] don't finded ost base address\n",cpu_num);
++		return;
++	}
++
++	iobase = (void *)base;
++	if(timerevent->iobase == NULL)
++	{
++		timerevent->iobase = iobase;
++		timerevent->rate = core_ost->rate;
++
++		raw_spin_lock_init(&timerevent->lock);
++		cd = &timerevent->clkevt;
++		memset(cd,0,sizeof(struct clock_event_device));
++		cd->name = "clockenvent";
++		cd->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;
++		cd->shift = 10;
++		cd->rating = 400;
++		cd->set_state_periodic = set_state_periodic;
++		cd->set_state_oneshot = set_state_shutdown;
++		cd->set_state_oneshot_stopped = set_state_shutdown;
++		cd->set_state_shutdown = set_state_shutdown;
++		cd->tick_resume = set_state_shutdown;
++		cd->set_next_event = core_timerevent_set_next_event;
++		cd->irq = core_ost->irq;
++		cd->cpumask = cpumask_of(smp_processor_id());
++	}else {
++		iobase = timerevent->iobase;
++		cd = &timerevent->clkevt;
++	}
++	ost_writel(0,iobase + OSTER);  //disable ost
++	ost_writel(CSRDIV(CLK_DIV),iobase + OSTCCR);
++	ost_writel(1,iobase + OSTCR);
++	ost_writel(0,iobase + OSTMR);
++
++	clockevents_config_and_register(cd, timerevent->rate, 0xf, 0xffffffff);
++
++	*this_cpu_ptr(core_ost->percpu_timerevent) = timerevent;
++
++	enable_percpu_irq(core_ost->irq, IRQ_TYPE_NONE);
++	printk("clockevents_config_and_register success.\n");
++}
++void ingenic_percpu_timerevent_init(unsigned int cpu_num)
++{
++	percpu_timerevent_init(&g_core_ost, cpu_num);
++}
++EXPORT_SYMBOL_GPL(ingenic_percpu_timerevent_init);
++
++
++static void percpu_timerevent_deinit(struct core_ost_chip * core_ost)
++{
++	struct core_timerevent *timerevent = *this_cpu_ptr(core_ost->percpu_timerevent);
++	disable_percpu_irq(core_ost->irq);
++	ost_writel(0,timerevent->iobase + OSTER);  //disable ost
++	ost_writel(1,timerevent->iobase + OSTMR);
++}
++void ingenic_percpu_timerevent_deinit(void)
++{
++	percpu_timerevent_deinit(&g_core_ost);
++}
++EXPORT_SYMBOL_GPL(ingenic_percpu_timerevent_deinit);
++
++
++static void __init core_ost_setup(struct core_ost_chip *core_ost, unsigned long ext_rate)
++{
++	int ret;
++
++	if(core_ost->core_gate) {
++		clk_prepare_enable(core_ost->core_gate);
++	}
++
++	core_ost->rate = (ext_rate / CLK_DIV);   /* TODO: should be clk_get_rate(extclk) / CLK_DIV in real chip */
++
++	core_ost->percpu_timerevent = alloc_percpu(struct core_timerevent *);
++	if(!core_ost->percpu_timerevent) {
++		pr_err("ost percpu alloc fail!\n");
++		return;
++	}
++	ret = request_percpu_irq(core_ost->irq, core_timerevent_interrupt,"core_timerevent",core_ost->percpu_timerevent);
++	if(ret < 0) {
++		pr_err("dddd timer request ost error %d \n",ret);
++	}
++	memset(timerevent_buf,0,sizeof(timerevent_buf));
++
++}
++
++static void __init ingenic_ost_init(struct device_node *np)
++{
++	struct core_ost_chip *core_ost = &g_core_ost;
++	struct tmr_src *tmr = &g_tmr_src ;
++	struct clk *ext_clk = NULL;
++	unsigned long ext_rate;
++	void __iomem *g_iobase = NULL;
++	void __iomem *core_iobase = NULL;
++	int irq = -1;
++	struct property *prop;
++	const unsigned int *vp;
++	unsigned int pv;
++	int index = 0;
++
++	g_iobase = of_io_request_and_map(np, 0, "ost");
++	if(g_iobase == NULL) {
++		pr_err("Failed to map global clocksource iobase!\n");
++		return;
++	}
++	core_iobase = of_io_request_and_map(np, 1, "core-ost");
++	if(core_iobase == NULL) {
++		pr_err("Failed to map core clockevent iobase!\n");
++		return;
++	}
++
++	irq = of_irq_get_byname(np, "sys_ost");
++	if (irq < 0) {
++		pr_err("ftm: unable to get IRQ from DT, %d\n", irq);
++		return;
++	}
++
++	of_property_for_each_u32(np, "cpu-ost-map", prop, vp, pv) {
++		if(index % 2) {
++			cpu_ost_map[index/2].dev_base = (unsigned int)core_iobase + pv;
++		} else {
++			cpu_ost_map[index/2].cpu_num = pv;
++		}
++		index ++;
++		if(index > NR_CPUS * 2 - 1) {
++			printk("parse cpu-ost-iomap, ost number define in dt is too large!\n");
++			break;
++		}
++        }
++
++	ext_clk = clk_get(NULL, "ext");
++	if (IS_ERR_OR_NULL(ext_clk)) {
++		pr_err("Warnning ... Ingenic Ost: Failed to get ext clk, Using default clk rate(24MHz),\n");
++		ext_rate = 24000000;
++	} else {
++		ext_rate = clk_get_rate(ext_clk);
++		clk_put(ext_clk);
++	}
++
++	tmr->iobase = g_iobase;
++	core_ost->iobase = core_iobase;
++	core_ost->irq = irq;
++
++	tmr->clk_gate = clk_get(NULL, "gate_ost");
++	if(IS_ERR_OR_NULL(tmr->clk_gate)) {
++		pr_err("Failed to get global ost clk gate!\n");
++		tmr->clk_gate = NULL;
++	}
++
++	core_ost->core_gate = clk_get(NULL, "gate_ost");
++	if(IS_ERR_OR_NULL(core_ost->core_gate)) {
++		pr_err("Failed to get core ost clk gate!\n");
++		core_ost->core_gate = NULL;
++	}
++
++	core_ost_setup(core_ost, ext_rate);
++	percpu_timerevent_init(core_ost, 0);
++	core_clocksource_init(core_ost, tmr);
++}
++
++TIMER_OF_DECLARE(ingenic_ost_init, "ingenic,core-ost", ingenic_ost_init);
+diff --git a/module_drivers/drivers/clocksource/ingenic_sysost.c b/module_drivers/drivers/clocksource/ingenic_sysost.c
+new file mode 100644
+index 000000000..1994135f3
+--- /dev/null
++++ b/module_drivers/drivers/clocksource/ingenic_sysost.c
+@@ -0,0 +1,316 @@
++/*
++ * Copyright (C) 2015 Ingenic Semiconductor Co., Ltd.
++ * Author:	xyfu <xiaoyang.fu@ingenic.com> (kernel.3.10.14)
++ * Modified:	cli <chen.li@ingenic.com>
++ *
++ * Operating System Timer interface for Ingenic's SOC, such as X1000,
++ * and so on. (kernel.4.4)
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++
++/* #define DEBUG */
++/* #define VERBOSE_DEBUG */
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/err.h>
++#include <linux/time.h>
++#include <linux/clockchips.h>
++#include <linux/clk.h>
++#include <linux/sched_clock.h>
++#include <linux/clk-provider.h>
++#include <linux/notifier.h>
++#include <linux/cpu.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <linux/delay.h>
++#include <soc/ost.h>
++
++#define CLKSOURCE_DIV   (16)
++#define CLKEVENT_DIV    (16)
++
++/*-----------------------------------------------------------------------------
++ *  C L O C K S O U R C E
++ *-----------------------------------------------------------------------------*/
++struct tmr_src {
++	struct clocksource cs;
++	struct clk *clk_gate;
++	void __iomem *iobase;
++};
++
++/* clocksource cycle base type */
++typedef u64 cycle_t;
++
++static cycle_t ingenic_read_cycles(struct clocksource *cs)
++{
++	struct tmr_src *tmr = container_of(cs, struct tmr_src, cs);
++	union clycle_type
++	{
++		cycle_t cycle64;
++		unsigned int cycle32[2];
++	} cycle;
++
++	cycle.cycle32[0] = ost_readl(tmr->iobase + OST_T2CNTL);
++	cycle.cycle32[1] = ost_readl(tmr->iobase + OST_TCNT2HBUF);
++
++	return cycle.cycle64;
++}
++
++static int tmr_src_enable(struct clocksource *cs)
++{
++	struct tmr_src *tmr = container_of(cs,struct tmr_src,cs);
++
++	ost_writel(tmr->iobase + OST_TESR, TESR_OSTEN2);
++	return 0;
++}
++static 	void tmr_src_disable(struct clocksource *cs)
++{
++	struct tmr_src *tmr = container_of(cs,struct tmr_src,cs);
++
++	ost_writel(tmr->iobase + OST_TCR, TCR_OSTCLR2);
++	ost_writel(tmr->iobase + OST_TECR, TESR_OSTEN2);
++}
++static void tmr_src_suspend(struct clocksource *cs)
++{
++	struct tmr_src *tmr = container_of(cs, struct tmr_src, cs);
++
++	ost_writel(tmr->iobase + OST_TFR , ~TFR_OSTM);
++	if (tmr->clk_gate) {
++		clk_disable_unprepare(tmr->clk_gate);
++
++	}
++}
++static void tmr_src_resume(struct clocksource *cs)
++{
++	struct tmr_src *tmr = container_of(cs, struct tmr_src, cs);
++	if (tmr->clk_gate)
++		clk_prepare_enable(tmr->clk_gate);
++}
++
++static struct tmr_src tmr_src = {
++	.cs = {
++		.name 		= "ingenic_clocksource",
++		.rating		= 400,
++		.read		= ingenic_read_cycles,
++		.mask		= CLOCKSOURCE_MASK(64),
++		.flags		= CLOCK_SOURCE_WATCHDOG | CLOCK_SOURCE_IS_CONTINUOUS,
++		.enable         = tmr_src_enable,
++		.disable        = tmr_src_disable,
++		.suspend        = tmr_src_suspend,
++		.resume         = tmr_src_resume,
++	}
++};
++
++static u64 notrace ingenic_read_sched_clock(void)
++{
++	union clycle_type {
++		uint64_t cycle64;
++		uint32_t cycle32[2];
++	} cycle;
++	cycle.cycle32[0] = ost_readl(tmr_src.iobase + OST_T2CNTL);
++	cycle.cycle32[1] = ost_readl(tmr_src.iobase + OST_TCNT2HBUF);
++
++	return cycle.cycle64;
++}
++
++static void __init ingenic_clocksource_init(struct tmr_src *tmr, unsigned long ext_rate)
++{
++	unsigned long hz = ext_rate / CLKSOURCE_DIV;
++	unsigned int val;
++
++	tmr->clk_gate = clk_get(NULL, "gate_ost");
++	if (IS_ERR_OR_NULL(tmr->clk_gate)) {
++		pr_err("ERROR: Failed to get clk, Please check clk driver.\n");
++		pr_err("%s, incase of Debug at the very beginning, we ignore the clk_gate. \n \
++			You must implemented clk driver immediately\n\n\t\n", __func__);
++	} else {
++		clk_prepare_enable(tmr->clk_gate);
++	}
++
++	val =  ost_readl(tmr->iobase + OST_TCCR);
++	if (ost_readl(tmr->iobase + OST_TER) & TESR_OSTEN2) {
++		u32 div = 0;
++		/*
++		 * get previous boot time
++		 */
++		switch ((val & TCCRDIV_MSK2) >> TCCRDIV_SFT2) {
++		case 0: div = 1; break;
++		case 1: div = 4; break;
++		case 2: div = 16; break;
++		}
++		if (likely(div)) {
++			u64 cycles = ingenic_read_sched_clock();
++			u32 pre_hz = ext_rate / div;
++			cycles = cycles * USEC_PER_SEC;
++			do_div(cycles, pre_hz);
++			pr_info("Previous Boot Time is %u us\n", (u32)cycles);
++		}
++		ost_writel(tmr->iobase + OST_TECR, TESR_OSTEN2);
++	}
++	val &= ~TCCRDIV_MSK2;
++	val |= TCCRDIV2(CLKSOURCE_DIV);
++	ost_writel(tmr->iobase + OST_TCCR, val);
++	ost_writel(tmr->iobase + OST_TCR, TCR_OSTCLR2);
++	ost_writel(tmr->iobase + OST_TESR, TESR_OSTEN2);
++
++	clocksource_register_hz(&tmr->cs, hz);
++	sched_clock_register(ingenic_read_sched_clock, 64, hz);
++}
++
++/*-----------------------------------------------------------------------------
++ *  C L O C K E V E N T
++ *-----------------------------------------------------------------------------*/
++struct ingenic_timerevent {
++	struct clock_event_device clkevt;
++	void __iomem *iobase;
++	unsigned int periodic_ticks;
++	struct clk *clk_gate;
++	unsigned int rate;
++	int irq;
++	struct irqaction evt_action;
++} ingenic_clockevent;
++
++
++static int ingenic_set_state_periodic(struct clock_event_device *cd)
++{
++	struct ingenic_timerevent *evt_dev = container_of(cd,
++			struct ingenic_timerevent, clkevt);
++
++	ost_writel(evt_dev->iobase + OST_TMR , TMR_OSTM);
++	ost_writel(evt_dev->iobase + OST_TECR , TESR_OSTEN1);
++	ost_writel(evt_dev->iobase + OST_TFR , ~TFR_OSTM);
++	ost_writel(evt_dev->iobase + OST_T1DFR,  evt_dev->periodic_ticks);
++	ost_writel(evt_dev->iobase + OST_TCR , TCR_OSTCLR1);
++	ost_writel(evt_dev->iobase + OST_TESR , TESR_OSTEN1);
++	ost_writel(evt_dev->iobase + OST_TMR , ~TMR_OSTM);
++	return 0;
++}
++
++static int ingenic_set_state_shutdown(struct clock_event_device *cd)
++{
++	struct ingenic_timerevent *evt_dev = container_of(cd,
++			struct ingenic_timerevent, clkevt);
++	ost_writel(evt_dev->iobase + OST_TECR , TESR_OSTEN1);
++	return 0;
++
++}
++static int ingenic_set_next_event(unsigned long evt, struct clock_event_device *cd)
++{
++	struct ingenic_timerevent *evt_dev = container_of(cd,
++			struct ingenic_timerevent, clkevt);
++
++	ost_writel(evt_dev->iobase + OST_TMR , TMR_OSTM);
++	ost_writel(evt_dev->iobase + OST_TECR , TESR_OSTEN1);
++	ost_writel(evt_dev->iobase + OST_TFR , ~TFR_OSTM);
++	ost_writel(evt_dev->iobase + OST_T1DFR, evt);
++	ost_writel(evt_dev->iobase + OST_TCR , TCR_OSTCLR1);
++	ost_writel(evt_dev->iobase + OST_TESR , TESR_OSTEN1);
++	ost_writel(evt_dev->iobase + OST_TMR , ~TMR_OSTM);
++	return 0;
++}
++
++static irqreturn_t ingenic_timer_interrupt(int irq, void *dev_id)
++{
++	struct ingenic_timerevent *evt_dev = dev_id;
++	struct clock_event_device *cd = &evt_dev->clkevt;
++
++	ost_writel(evt_dev->iobase + OST_TFR, ~TFR_OSTM);
++
++	if (clockevent_state_oneshot(cd))
++		ost_writel(evt_dev->iobase + OST_TECR , TESR_OSTEN1);
++
++	evt_dev->clkevt.event_handler(&evt_dev->clkevt);
++	return IRQ_HANDLED;
++}
++
++static void __init ingenic_clockevent_init(struct ingenic_timerevent *evt_dev, unsigned long ext_rate)
++{
++	struct clock_event_device *cd = &evt_dev->clkevt;
++	unsigned int val;
++	int ret;
++
++	ost_writel(evt_dev->iobase + OST_TMR, TMR_OSTM);
++	ost_writel(evt_dev->iobase + OST_TECR, TESR_OSTEN1);
++	ost_writel(evt_dev->iobase + OST_TFR, ~TFR_OSTM);
++	val = ost_readl(evt_dev->iobase + OST_TCCR);
++	val &= ~TCCRDIV_MSK1;
++	val |= TCCRDIV1(CLKEVENT_DIV);
++	ost_writel(evt_dev->iobase + OST_TCCR, val);
++	ost_writel(evt_dev->iobase + OST_TCR, TCR_OSTCLR1);
++
++	evt_dev->evt_action.handler = ingenic_timer_interrupt;
++	evt_dev->evt_action.flags = IRQF_TIMER;
++	evt_dev->evt_action.name = "ingenic-timerost";
++	evt_dev->evt_action.dev_id = (void*)evt_dev;
++	evt_dev->rate = ext_rate / CLKEVENT_DIV;
++	evt_dev->periodic_ticks = ((evt_dev->rate + (HZ >> 1)) / HZ) - 1;	/* - 1 for scroll back */
++
++	memset(cd, 0, sizeof(struct clock_event_device));
++	ret = request_irq(evt_dev->irq, evt_dev->evt_action.handler, evt_dev->evt_action.flags, evt_dev->evt_action.name, (void *)cd);
++	if(ret < 0) {
++		pr_err("request system ost error %d \n",ret);
++	}
++
++	cd->name = "ingenic-clockenvent";
++	cd->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;
++	cd->rating = 400;
++	cd->set_state_periodic = ingenic_set_state_periodic;
++	cd->set_state_oneshot = ingenic_set_state_shutdown;
++	cd->set_state_shutdown = ingenic_set_state_shutdown;
++	cd->set_next_event = ingenic_set_next_event;
++	cd->irq = evt_dev->irq;
++	cd->cpumask = cpumask_of(0);
++
++	clockevents_config_and_register(cd, evt_dev->rate, 4, 0xffffffff);
++}
++
++static int __init ingenic_ost_init(struct device_node *np)
++{
++	struct ingenic_timerevent *evt = &ingenic_clockevent;
++	struct tmr_src *tmr = &tmr_src ;
++	struct clk *ext_clk = NULL;
++	unsigned long ext_rate;
++	void __iomem *iobase = NULL;
++	int irq_ost = -1;
++
++	iobase = of_io_request_and_map(np, 0, "ost");
++	if(iobase == NULL) {
++		pr_err("Failed to map clocksource iobase!\n");
++		return -EINVAL;
++	}
++
++	irq_ost = of_irq_get_byname(np, "sys_ost");
++	if (irq_ost < 0) {
++		pr_err("ftm: unable to get IRQ from DT, %d\n", irq_ost);
++		return -EINVAL;
++	}
++
++	ext_clk = clk_get(NULL, "ext");
++	if (IS_ERR_OR_NULL(ext_clk)) {
++		pr_warn("Warning Ingenic Ost: Can not get extern clock, Please check clk driver !!\n\n\t\n");
++		ext_rate = 24000000;
++	} else {
++
++		ext_rate = clk_get_rate(ext_clk);
++		clk_put(ext_clk);
++	}
++
++	tmr->iobase = iobase;
++	evt->iobase = iobase;
++	evt->irq = irq_ost;
++
++	ingenic_clocksource_init(tmr, ext_rate);
++	ingenic_clockevent_init(evt, ext_rate);
++
++	return 0;
++}
++
++TIMER_OF_DECLARE(x1000_ost_init, "ingenic,x1000-ost", ingenic_ost_init);
++TIMER_OF_DECLARE(x1800_ost_init, "ingenic,x1800-ost", ingenic_ost_init);
++TIMER_OF_DECLARE(x1021_ost_init, "ingenic,x1021-ost", ingenic_ost_init);
++TIMER_OF_DECLARE(x1520_ost_init, "ingenic,x1520-ost", ingenic_ost_init);
++TIMER_OF_DECLARE(x1600_ost_init, "ingenic,x1600-ost", ingenic_ost_init);
++TIMER_OF_DECLARE(x1630_ost_init, "ingenic,x1630-ost", ingenic_ost_init);
+diff --git a/module_drivers/drivers/crypto/Kconfig b/module_drivers/drivers/crypto/Kconfig
+new file mode 100644
+index 000000000..6081b8635
+--- /dev/null
++++ b/module_drivers/drivers/crypto/Kconfig
+@@ -0,0 +1,23 @@
++config CRYPTO_DEV_INGENIC_SHA
++        tristate "[SHA] Support for Ingenic SHA hw accelerator"
++        depends on MACH_XBURST || MACH_XBURST2
++        select CRYPTO_ALGAPI
++        help
++          Some Ingenic processors have MD5/SHA1/SHA224/SHA256/SHA384/SHA512
++          hw accelerator.
++          Select this if you want to use the Ingenic module for
++          MD5/SHA1/SHA224/SHA256/SHA384/SHA512 algorithms.
++
++          To compile this driver as a module, choose M here: the module
++          will be called ingenic-sha.
++
++
++config CRYPTO_DEV_INGENIC_AES
++        tristate "[AES] Support for INGENIC AES hw engine"
++        depends on MACH_XBURST || MACH_XBURST2
++        select CRYPTO_AES
++        select CRYPTO_BLKCIPHER2
++        help
++          INGENIC processors have AES module accelerator. Select this if you
++          want to use the INGENIC module for AES algorithms.
++
+diff --git a/module_drivers/drivers/crypto/Makefile b/module_drivers/drivers/crypto/Makefile
+new file mode 100644
+index 000000000..b31d46a02
+--- /dev/null
++++ b/module_drivers/drivers/crypto/Makefile
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_CRYPTO_DEV_INGENIC_AES) += ingenic-aes.o
++obj-$(CONFIG_CRYPTO_DEV_INGENIC_SHA) += ingenic-hash.o
+diff --git a/module_drivers/drivers/crypto/ingenic-aes.c b/module_drivers/drivers/crypto/ingenic-aes.c
+new file mode 100644
+index 000000000..6d1981356
+--- /dev/null
++++ b/module_drivers/drivers/crypto/ingenic-aes.c
+@@ -0,0 +1,923 @@
++/*
++ * Cryptographic API.
++ *
++ * Support for Ingenic AES HW acceleration.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ */
++
++#include <linux/err.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/errno.h>
++#include <linux/clk.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/scatterlist.h>
++#include <linux/dma-mapping.h>
++#include <linux/pm_runtime.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/io.h>
++#include <linux/crypto.h>
++#include <linux/interrupt.h>
++#include <crypto/scatterwalk.h>
++#include <crypto/aes.h>
++#include <linux/delay.h>
++#include "ingenic-aes.h"
++#include <crypto/internal/skcipher.h>
++
++/* keep registered devices data here */
++static LIST_HEAD(dev_list);
++static DEFINE_SPINLOCK(list_lock);
++
++
++static inline unsigned long aes_read(struct ingenic_aes_dev *aes, unsigned long offset)
++{
++	return readl(aes->io_base + offset);
++}
++
++static inline void aes_write(struct ingenic_aes_dev *aes, unsigned long offset,
++	unsigned long value)
++{
++	writel(value, aes->io_base + offset);
++}
++
++void dump_aes_reg(struct ingenic_aes_dev *aes){
++	dev_info(aes->dev,"AES_ASCR: 0x%08lx\n",aes_read(aes,AES_ASCR));
++	dev_info(aes->dev,"AES_ASSR: 0x%08lx\n",aes_read(aes,AES_ASSR));
++	dev_info(aes->dev,"AES_ASINTM: 0x%08lx\n",aes_read(aes,AES_ASINTM));
++	dev_info(aes->dev,"AES_ASSA: 0x%08lx\n",aes_read(aes,AES_ASSA));
++	dev_info(aes->dev,"AES_ASDA: 0x%08lx\n",aes_read(aes,AES_ASDA));
++	dev_info(aes->dev,"AES_ASTC: 0x%08lx\n",aes_read(aes,AES_ASTC));
++}
++
++static inline int ingenic_aes_hw_init(struct ingenic_aes_dev *aes)
++{
++	/*
++	 * clocks are enabled when request starts and disabled when finished.
++	 * It may be long delays between requests.
++	 * Device might go to off mode to save power.
++	 */
++	pm_runtime_get_sync(aes->dev);
++
++	if (!(aes->flags & FLAGS_INIT)) {
++		aes->flags |= FLAGS_INIT;
++		aes->err = 0;
++	}
++
++	return 0;
++}
++
++static inline int check_keydone(struct ingenic_aes_dev *aes)
++{
++	unsigned long timeout = 1000;
++	while(!(aes_read(aes,AES_ASSR) & (1 << 0)) && --timeout);
++	if(timeout == 0){
++		dev_err(aes->dev,"Write keys is timeout.\n");
++		return -1;
++	}
++	return 0;
++}
++
++static inline void ingenic_aes_stop(struct ingenic_aes_dev *aes)
++{
++	unsigned long d;
++	d = aes_read(aes, AES_ASCR);
++	d &= ~1;
++	aes_write(aes, AES_ASCR,d);
++	aes->flags = 0;
++	pm_runtime_put_sync(aes->dev);
++	pr_debug("ingenic aes stop. finished!\n");
++}
++static inline int ingenic_aes_write_ctrl(struct ingenic_aes_dev *aes)
++{
++	unsigned int key32;
++	int i;
++	unsigned long val,init_data,mode,alg;
++	int err;
++	err = ingenic_aes_hw_init(aes);
++	if (err){
++		dev_err(aes->dev,"aes hw init failed.\n");
++		return err;
++	}
++	// 1. Mask interrupt and clear interrupt.
++	aes_write(aes,AES_ASINTM,0);
++	aes_read(aes,AES_ASSR);
++
++    // 2. AES enable and clear data for new process.
++	init_data = ASCR_PS_DEF | ASCR_CLR | ASCR_EN;
++	aes_write(aes,AES_ASCR,init_data);
++
++	// 3. configure AES
++
++	key32 = aes->ctx->keylen / sizeof(unsigned long);
++	switch(aes->ctx->keylen){
++	case AES_KEYSIZE_128:
++		val = 0;
++		break;
++	case AES_KEYSIZE_192:
++		val = 1;
++		break;
++	case AES_KEYSIZE_256:
++		val = 2;
++		break;
++	default:
++		dev_err(aes->dev,"len error\n");
++		return -EINVAL;
++	}
++	alg = (aes->flags & FLAGS_CBC) == FLAGS_CBC ? CBC_ALG:ECB_ALG;
++	mode = (aes->flags & FLAGS_DECRYPT) == FLAGS_DECRYPT ? DECRYPTO_MODE : ENCRYPTO_MODE;
++	init_data = ASCR_PS_DEF | ASCR_KEYL(val) | ASCR_ALGS(alg) | ASCR_DECE(mode) | ASCR_EN;
++	aes_write(aes,AES_ASCR,init_data);
++
++	if (alg == CBC_ALG){
++		// Initialize IV of cbc alg
++		unsigned int *dat = (unsigned int *)aes->req->iv;
++		if(dat == NULL){
++			dev_err(aes->dev,"no set iv data in cbc(aes)\n");
++		}
++		for (i = 0; i < 4; i++) {
++			aes_write(aes, AES_ASIV,__be32_to_cpu(dat[i]));
++			/* printk("======== iv:0x%08lx 0x%08x\n",dat[i],__be32_to_cpu(dat[i])); */
++		}
++		init_data = aes_read(aes,AES_ASCR);
++		aes_write(aes,AES_ASCR,init_data | ASCR_INIT_IV);
++	}
++	// Initialize Key.
++	for (i = 0; i < key32; i++) {
++		aes_write(aes, AES_ASKY,
++			__be32_to_cpu(aes->ctx->key[i]));
++		/* printk("======== 0x%08lx 0x%08x\n",aes->ctx->key[i],__be32_to_cpu(aes->ctx->key[i])); */
++	}
++
++	init_data = aes_read(aes,AES_ASCR);
++	aes_write(aes,AES_ASCR,init_data | ASCR_KEYS); // check key done in dma process.
++	return 0;
++}
++
++static struct ingenic_aes_dev *ingenic_aes_find_dev(struct ingenic_aes_ctx *ctx)
++{
++	struct ingenic_aes_dev *aes = NULL, *tmp;
++
++	spin_lock(&list_lock);
++	if (!ctx->aes) {
++		list_for_each_entry(tmp, &dev_list, list) {
++			/* FIXME: take fist available aes core */
++			aes = tmp;
++			break;
++		}
++		ctx->aes = aes;
++	} else {
++		/* already found before */
++		aes = ctx->aes;
++	}
++	spin_unlock(&list_lock);
++
++	return aes;
++}
++
++static int ingenic_aes_dma_init(struct ingenic_aes_dev *aes)
++{
++	int err = -ENOMEM;
++	aes->buf_in = (void *)__get_free_pages(GFP_KERNEL, INGENIC_AES_CACHE_PAGE_SHIFT);
++	aes->buf_out = (void *)__get_free_pages(GFP_KERNEL, INGENIC_AES_CACHE_PAGE_SHIFT);
++	aes->buflen = PAGE_SIZE << INGENIC_AES_CACHE_PAGE_SHIFT;
++	aes->buflen &= ~(AES_BLOCK_SIZE - 1);
++
++	if (!aes->buf_in || !aes->buf_out) {
++		dev_err(aes->dev, "unable to alloc pages.\n");
++		goto err_alloc;
++	}
++	aes->dma_addr_in = dma_map_single(aes->dev, aes->buf_in, aes->buflen,
++		DMA_TO_DEVICE);
++	if (dma_mapping_error(aes->dev, aes->dma_addr_in)) {
++		dev_err(aes->dev, "dma %d bytes error\n", aes->buflen);
++		err = -EINVAL;
++		goto err_map_in;
++	}
++
++	aes->dma_addr_out = dma_map_single(aes->dev, aes->buf_out, aes->buflen,
++		DMA_FROM_DEVICE);
++	if (dma_mapping_error(aes->dev, aes->dma_addr_out)) {
++		dev_err(aes->dev, "dma %d bytes error\n", aes->buflen);
++		err = -EINVAL;
++		goto err_map_out;
++	}
++	return 0;
++err_map_out:
++	dma_unmap_single(aes->dev, aes->dma_addr_in, aes->buflen, DMA_TO_DEVICE);
++err_map_in:
++	free_pages((unsigned long)aes->buf_out, INGENIC_AES_CACHE_PAGE_SHIFT);
++	free_pages((unsigned long)aes->buf_in, INGENIC_AES_CACHE_PAGE_SHIFT);
++err_alloc:
++	if (err)
++		pr_err("error: %d\n", err);
++	return err;
++}
++
++static void ingenic_aes_dma_cleanup(struct ingenic_aes_dev *aes)
++{
++	free_pages((unsigned long)aes->buf_out, INGENIC_AES_CACHE_PAGE_SHIFT);
++	free_pages((unsigned long)aes->buf_in, INGENIC_AES_CACHE_PAGE_SHIFT);
++}
++
++static void sg_copy_buf(void *buf, struct scatterlist *sg,
++	unsigned int start, unsigned int nbytes, int out)
++{
++	struct scatter_walk walk;
++
++	if (!nbytes)
++		return;
++
++	scatterwalk_start(&walk, sg);
++	scatterwalk_advance(&walk, start);
++	scatterwalk_copychunks(buf, &walk, nbytes, out);
++	scatterwalk_done(&walk, out, 0);
++}
++
++static int sg_copy(struct scatterlist **sg, size_t *offset, void *buf,
++	size_t buflen, size_t total, int out)
++{
++	unsigned int count, off = 0;
++
++	while (buflen && total) {
++		count = min((*sg)->length - *offset, total);
++		count = min(count, buflen);
++
++		if (!count)
++			return off;
++
++		/*
++		 * buflen and total are AES_BLOCK_SIZE size aligned,
++		 * so count should be also aligned
++		 */
++
++		sg_copy_buf(buf + off, *sg, *offset, count, out);
++
++		off += count;
++		buflen -= count;
++		*offset += count;
++		total -= count;
++
++		if (*offset == (*sg)->length) {
++			*sg = sg_next(*sg);
++			if (*sg)
++				*offset = 0;
++			else
++				total = 0;
++		}
++	}
++
++	return off;
++}
++
++void dump_sgdata(struct scatterlist *sg)
++{
++	int i;
++	unsigned int *d =  sg_virt(sg);
++	for(i = 0;i < sg->length;i += 4)
++	{
++		printk("%5d:0x%08x\n",i,d[i/4]);
++	}
++}
++
++void prep_sgdata(struct scatterlist *sg)
++{
++	int i;
++	unsigned int *d =  sg_virt(sg);
++	unsigned int dat;
++	for(i = 0;i < sg->length + 16;i += 4)
++	{
++		dat = d[i/4];
++		d[i/4] = __be32_to_cpu(dat);
++	}
++}
++
++
++static int ingenic_aes_crypt_dma(struct crypto_tfm *tfm,
++	struct scatterlist *in_sg, struct scatterlist *out_sg)
++{
++	struct ingenic_aes_ctx *ctx = crypto_tfm_ctx(tfm);
++	struct ingenic_aes_dev *aes = ctx->aes;
++
++	dma_addr_t dma_addr_in = sg_dma_address(in_sg);
++	dma_addr_t dma_addr_out = sg_dma_address(out_sg);
++	int length = sg_dma_len(in_sg);
++	int blen = 0;
++
++	unsigned int config;
++//	dev_info(aes->dev,"len: %d\n", length);
++	if(check_keydone(aes) != 0){
++		dev_err(aes->dev,"check key done failed!\n");
++		return -EINPROGRESS;
++	}
++
++	config = aes_read(aes,AES_ASCR);
++
++	aes->dma_size = length;
++	aes_write(aes,AES_ASSA,dma_addr_in);
++	aes_write(aes,AES_ASDA,dma_addr_out);
++
++	blen = length / 16; // perblock is 128bit.
++
++	if(length % 16)
++		return -EINVAL;
++
++	aes_write(aes,AES_ASTC,blen);
++	aes_write(aes,AES_ASINTM,4);
++	config |= (ASCR_DMAE | ASCR_DMAS);
++	aes_write(aes,AES_ASCR,config);
++	return 0;
++}
++static int ingenic_aes_crypt_dma_start(struct ingenic_aes_dev *aes)
++{
++	struct crypto_tfm *tfm = crypto_skcipher_tfm(crypto_skcipher_reqtfm(aes->req));
++	int err, fast = 0, in, out;
++	size_t count;
++	dma_addr_t addr_in, addr_out;
++	struct scatterlist *in_sg, *out_sg;
++	int len32;
++
++	unsigned int ivoffset = aes->req->cryptlen - AES_BLOCK_SIZE;
++	dev_dbg(aes->dev,"total: %d\n", aes->total);
++
++	if (sg_is_last(aes->in_sg) && sg_is_last(aes->out_sg)) {
++		/* check for alignment */
++		in = IS_ALIGNED((unsigned long)aes->in_sg->offset, sizeof(unsigned long));
++		out = IS_ALIGNED((unsigned long)aes->out_sg->offset, sizeof(unsigned long));
++
++		fast = in && out;
++	}
++	if (fast)  {
++		count = min(aes->total, sg_dma_len(aes->in_sg));
++		count = min(count, sg_dma_len(aes->out_sg));
++		if (count != aes->total) {
++			pr_err("request length != buffer length\n");
++			return -EINVAL;
++		}
++
++		if(aes->flags & FLAGS_CBC){
++			if(aes->flags & FLAGS_DECRYPT){
++				memcpy(aes->req->iv, sg_virt(aes->in_sg) + ivoffset, AES_BLOCK_SIZE);
++			}
++		}
++
++		prep_sgdata(aes->in_sg);
++		//dump_sgdata(aes->in_sg);
++
++		pr_debug("fast\n");
++		err = dma_map_sg(aes->dev, aes->in_sg, 1, DMA_TO_DEVICE);
++
++		if (!err) {
++			dev_err(aes->dev, "dma_map_sg() error\n");
++			return -EINVAL;
++		}
++
++		err = dma_map_sg(aes->dev, aes->out_sg, 1, DMA_FROM_DEVICE);
++		if (!err) {
++			dev_err(aes->dev, "dma_map_sg() error\n");
++			dma_unmap_sg(aes->dev, aes->in_sg, 1, DMA_TO_DEVICE);
++			return -EINVAL;
++		}
++
++		addr_in = sg_dma_address(aes->in_sg);
++		addr_out = sg_dma_address(aes->out_sg);
++		in_sg = aes->in_sg;
++		out_sg = aes->out_sg;
++
++		aes->flags |= FLAGS_FAST;
++
++	} else {
++		/* use cache buffers */
++		count = sg_copy(&aes->in_sg, &aes->in_offset, aes->buf_in,
++			aes->buflen, aes->total, 0);
++
++		len32 = DIV_ROUND_UP(count, DMA_MIN) * DMA_MIN;
++		/*
++		 * The data going into the AES module has been copied
++		 * to a local buffer and the data coming out will go
++		 * into a local buffer so set up local SG entries for
++		 * both.
++		 */
++
++		sg_init_one(&aes->in_sgl,aes->buf_in,len32);
++		sg_dma_len(&aes->in_sgl) = len32;
++		sg_dma_address(&aes->in_sgl) = aes->dma_addr_in;
++		sg_init_one(&aes->out_sgl,aes->buf_out,len32);
++		sg_dma_len(&aes->out_sgl) = len32;
++		sg_dma_address(&aes->out_sgl) = aes->dma_addr_out;
++
++		in_sg = &aes->in_sgl;
++		out_sg = &aes->out_sgl;
++
++		addr_in = aes->dma_addr_in;
++		addr_out = aes->dma_addr_out;
++
++		if(aes->flags & FLAGS_CBC){
++			if(aes->flags & FLAGS_DECRYPT){
++				memcpy(aes->req->iv, aes->buf_in + ivoffset, AES_BLOCK_SIZE);
++			}
++		}
++
++		prep_sgdata(in_sg);
++		//dump_sgdata(in_sg);
++
++		aes->flags &= ~FLAGS_FAST;
++		dma_sync_sg_for_device(aes->dev, in_sg, 1, DMA_TO_DEVICE);
++		dma_sync_sg_for_device(aes->dev, out_sg, 1, DMA_FROM_DEVICE);
++	}
++
++	aes->total -= count;
++	err = ingenic_aes_crypt_dma(tfm, in_sg, out_sg);
++	if (err) {
++		dma_unmap_sg(aes->dev, aes->in_sg, 1, DMA_TO_DEVICE);
++		dma_unmap_sg(aes->dev, aes->out_sg, 1, DMA_FROM_DEVICE);
++	}
++
++	return err;
++}
++
++static void ingenic_aes_finish_req(struct ingenic_aes_dev *aes, int err)
++{
++	struct skcipher_request *req = aes->req;
++
++	pr_debug("err: %d\n", err);
++
++	aes->flags &= ~FLAGS_BUSY;
++	req->base.complete(&req->base, err);
++
++#ifdef CONFIG_HIGHMEM
++	if (PageHighMem(sg_page(req->src)))
++		kunmap_high(sg_page(req->src));
++	if (PageHighMem(sg_page(req->dst)))
++		kunmap_high(sg_page(req->dst));
++#endif
++}
++
++static int ingenic_aes_crypt_dma_stop(struct ingenic_aes_dev *aes)
++{
++	int err = 0;
++	size_t count;
++	/* unsigned int val; */
++	pr_debug("total: %d\n", aes->total);
++
++	/* val = aes_read(aes,AES_ASCR); */
++	/* val &= ~(3 << 8); */
++	/* aes_write(aes,AES_ASCR,val); */
++
++
++	unsigned int ivoffset = aes->req->cryptlen - AES_BLOCK_SIZE;
++
++	if (aes->flags & FLAGS_FAST)
++	{
++		dma_unmap_sg(aes->dev, aes->out_sg, 1, DMA_FROM_DEVICE);
++		prep_sgdata(aes->out_sg);
++		//dump_sgdata(aes->out_sg);
++		dma_unmap_sg(aes->dev, aes->in_sg, 1, DMA_TO_DEVICE);
++		if(aes->flags & FLAGS_CBC){
++			if(!(aes->flags & FLAGS_DECRYPT)){
++				memcpy(aes->req->iv, sg_virt(aes->out_sg) + ivoffset, AES_BLOCK_SIZE);
++			}
++		}
++
++	} else {
++		dma_sync_single_for_device(aes->dev, aes->dma_addr_out,
++			aes->dma_size, DMA_FROM_DEVICE);
++
++		prep_sgdata(&aes->out_sgl);
++		//dump_sgdata(&aes->out_sgl);
++
++		/* copy data */
++		count = sg_copy(&aes->out_sg, &aes->out_offset, aes->buf_out,
++			aes->buflen, aes->dma_size, 1);
++		if(aes->flags & FLAGS_CBC){
++			if(!(aes->flags & FLAGS_DECRYPT)){
++				unsigned int ivoffset = aes->req->cryptlen - AES_BLOCK_SIZE;
++				memcpy(aes->req->iv, aes->buf_out + ivoffset, AES_BLOCK_SIZE);
++			}
++		}
++		if (count != aes->dma_size) {
++			err = -EINVAL;
++			pr_err("not all data converted: %u\n", count);
++		}
++	}
++	return err;
++}
++
++static int ingenic_aes_start(struct ingenic_aes_dev *aes,
++	struct skcipher_request *req)
++{
++	struct crypto_async_request *async_req, *backlog;
++	struct ingenic_aes_ctx *ctx;
++	struct ingenic_aes_reqctx *rctx;
++	unsigned long flags;
++	int err, ret = 0;
++	spin_lock_irqsave(&aes->lock, flags);
++	if (req) {
++
++#ifdef CONFIG_HIGHMEM
++		if (PageHighMem(sg_page(req->src)))
++			kmap_high(sg_page(req->src));
++		if (PageHighMem(sg_page(req->dst)))
++			kmap_high(sg_page(req->dst));
++#endif
++
++		ret = crypto_enqueue_request(&aes->queue, &req->base);
++	}
++	if (aes->flags & FLAGS_BUSY) {
++		spin_unlock_irqrestore(&aes->lock, flags);
++		return ret;
++	}
++	backlog = crypto_get_backlog(&aes->queue);
++	async_req = crypto_dequeue_request(&aes->queue);
++	if (async_req)
++		aes->flags |= FLAGS_BUSY;
++	spin_unlock_irqrestore(&aes->lock, flags);
++
++	if (!async_req){
++		ingenic_aes_stop(aes);
++		return ret;
++	}
++	if (backlog)
++		backlog->complete(backlog, -EINPROGRESS);
++	req = skcipher_request_cast(async_req);
++
++	/* assign new request to device */
++	aes->req = req;
++	aes->total = req->cryptlen;
++	aes->in_offset = 0;
++	aes->in_sg = req->src;
++	aes->out_offset = 0;
++	aes->out_sg = req->dst;
++
++	rctx = skcipher_request_ctx(req);
++	ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
++	rctx->mode &= FLAGS_MODE_MASK;
++	aes->flags = (aes->flags & ~FLAGS_MODE_MASK) | rctx->mode;
++
++	aes->ctx = ctx;
++	ctx->aes = aes;
++
++	err = ingenic_aes_write_ctrl(aes);
++	if (!err)
++		err = ingenic_aes_crypt_dma_start(aes);
++
++	if (err) {
++
++		dev_err(aes->dev,"dma start failed.!\n");
++		ingenic_aes_stop(aes);
++		/* aes_task will not finish it, so do it here */
++		ingenic_aes_finish_req(aes, err);
++	}
++	return ret; /* return ret, which is enqueue return value */
++}
++
++static int ingenic_aes_crypt(struct skcipher_request *req, unsigned long mode)
++{
++	struct ingenic_aes_ctx *ctx = crypto_skcipher_ctx(
++		crypto_skcipher_reqtfm(req));
++	struct ingenic_aes_reqctx *rctx = skcipher_request_ctx(req);
++	struct ingenic_aes_dev *aes;
++	pr_info("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen,
++		!(mode & FLAGS_DECRYPT),
++		!!(mode & FLAGS_CBC));
++
++	if (!IS_ALIGNED(req->cryptlen, AES_BLOCK_SIZE)) {
++		pr_err("request size is not exact amount of AES blocks\n");
++		return -EINVAL;
++	}
++	aes = ingenic_aes_find_dev(ctx);
++	if (!aes)
++		return -ENODEV;
++	rctx->mode = mode;
++	return ingenic_aes_start(aes, req);
++}
++static irqreturn_t ingenic_aec_irqthread(int irq, void *data)
++{
++	struct ingenic_aes_dev *aes = (struct ingenic_aes_dev *)data;
++	unsigned long val;
++	unsigned long mask;
++
++	val = aes_read(aes,AES_ASSR);
++	mask = aes_read(aes,AES_ASINTM);
++	val = val & mask;
++
++	if(val & 4){
++		int err;
++		err = ingenic_aes_crypt_dma_stop(aes);
++		aes_write(aes,AES_ASSR,4);
++		err = aes->err ? : err;
++		if (aes->total && !err) {
++			err = ingenic_aes_crypt_dma_start(aes);
++			if (!err)
++				return IRQ_HANDLED; /* DMA started. Not fininishing. */
++		}
++		ingenic_aes_finish_req(aes, err);
++		ingenic_aes_start(aes,NULL);
++	}else if(val & 2){
++		aes_write(aes,AES_ASSR,2);
++	}else if(val & 1){
++		aes_write(aes,AES_ASSR,1);
++	}else{
++		dev_err(aes->dev,"unknown irq!!!\n");
++		dump_aes_reg(aes);
++	}
++
++	return IRQ_HANDLED;
++}
++
++/* ********************** ALG API ************************************ */
++
++static int ingenic_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
++	unsigned int keylen)
++{
++	struct ingenic_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
++
++	if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
++		keylen != AES_KEYSIZE_256)
++		return -EINVAL;
++
++	pr_debug("enter, keylen: %d\n", keylen);
++
++	memcpy(ctx->key, key, keylen);
++	ctx->keylen = keylen;
++
++	return 0;
++}
++
++static int ingenic_aes_ecb_encrypt(struct skcipher_request *req)
++{
++	return ingenic_aes_crypt(req, 0);
++}
++
++static int ingenic_aes_ecb_decrypt(struct skcipher_request *req)
++{
++	return ingenic_aes_crypt(req, FLAGS_DECRYPT);
++}
++
++static int ingenic_aes_cbc_encrypt(struct skcipher_request *req)
++{
++	return ingenic_aes_crypt(req, FLAGS_CBC);
++}
++
++static int ingenic_aes_cbc_decrypt(struct skcipher_request *req)
++{
++	return ingenic_aes_crypt(req, FLAGS_DECRYPT | FLAGS_CBC);
++}
++
++static int ingenic_aes_cra_init(struct crypto_skcipher *tfm)
++{
++	pr_debug("enter\n");
++	tfm->reqsize = sizeof(struct ingenic_aes_reqctx);
++	return 0;
++}
++
++static void ingenic_aes_cra_exit(struct crypto_skcipher *tfm)
++{
++	pr_debug("exit\n");
++}
++
++/* ********************** ALGS ************************************ */
++static struct skcipher_alg algs_ecb_cbc[] = {
++	{
++		.base.cra_name		= "ecb(aes)",
++		.base.cra_driver_name	= "ecb-aes-ingenic",
++		.base.cra_priority	= 100,
++		.base.cra_flags		= CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_ASYNC,
++		.base.cra_blocksize	= AES_BLOCK_SIZE,
++		.base.cra_ctxsize	= sizeof(struct ingenic_aes_ctx),
++		.base.cra_alignmask	= 0,
++		.base.cra_module	= THIS_MODULE,
++
++		.min_keysize		= AES_MIN_KEY_SIZE,
++		.max_keysize		= AES_MAX_KEY_SIZE,
++		.setkey			= ingenic_aes_setkey,
++		.encrypt		= ingenic_aes_ecb_encrypt,
++		.decrypt		= ingenic_aes_ecb_decrypt,
++
++		.init			= ingenic_aes_cra_init,
++		.exit			= ingenic_aes_cra_exit,
++	},
++	{
++		.base.cra_name		= "cbc(aes)",
++		.base.cra_driver_name	= "cbc-aes-ingenic",
++		.base.cra_priority	= 100,
++		.base.cra_flags		= CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_ASYNC,
++		.base.cra_blocksize	= AES_BLOCK_SIZE,
++		.base.cra_ctxsize	= sizeof(struct ingenic_aes_ctx),
++		.base.cra_alignmask	= 0,
++		.base.cra_module	= THIS_MODULE,
++
++		.min_keysize		= AES_MIN_KEY_SIZE,
++		.max_keysize		= AES_MAX_KEY_SIZE,
++		.ivsize			= AES_BLOCK_SIZE,
++		.setkey			= ingenic_aes_setkey,
++		.encrypt		= ingenic_aes_cbc_encrypt,
++		.decrypt		= ingenic_aes_cbc_decrypt,
++
++		.init			= ingenic_aes_cra_init,
++		.exit			= ingenic_aes_cra_exit,
++	},
++};
++
++static struct ingenic_aes_pdata ingenic_aes_pdata = {
++	.algs_list	= algs_ecb_cbc,
++	.size		= ARRAY_SIZE(algs_ecb_cbc),
++};
++static int ingenic_aes_get_res_pdev(struct ingenic_aes_dev *aes,
++	struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct resource *r;
++	int err;
++	int ret = 0;
++	/* Get the base address */
++	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!r) {
++		dev_err(dev, "no MEM resource info\n");
++		err = -ENODEV;
++		goto err;
++	}
++
++	aes->io_base = devm_ioremap(aes->dev, r->start, resource_size(r));
++	if(IS_ERR_OR_NULL(aes->io_base)) {
++		dev_err(&pdev->dev, "Failed to remap io resources!\n");
++		ret = -ENOMEM;
++		goto err;
++	}
++
++	aes->irq = platform_get_irq(pdev,0);
++	if(aes->irq < 0){
++		dev_err(dev,"Failed to request irq resource info\n");
++		ret = -EBUSY;
++		goto err;
++	}
++
++	err = request_threaded_irq(aes->irq,NULL,ingenic_aec_irqthread,
++		IRQF_ONESHOT,dev_name(dev),aes);
++
++	aes->pdata = &ingenic_aes_pdata;
++
++err:
++	return ret;
++}
++static noinline void pdma_wait(void)
++{
++	__asm__ volatile (
++		"	.set	push		\n\t"
++		"	.set	noreorder	\n\t"
++		"	.set	mips32		\n\t"
++		"	li	$26, 0		\n\t"
++		"	mtc0	$26, $12	\n\t"
++		"	nop			\n\t"
++		"1:				\n\t"
++		"	wait			\n\t"
++		"	b	1b		\n\t"
++		"	nop			\n\t"
++		"	.set	reorder		\n\t"
++		"	.set	pop		\n\t"
++		);
++}
++
++static int ingenic_aes_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct ingenic_aes_dev *aes;
++	struct skcipher_alg *algp;
++	int err = -ENOMEM, i;
++
++	aes = devm_kzalloc(dev,sizeof(struct ingenic_aes_dev), GFP_KERNEL);
++	if (aes == NULL) {
++		dev_err(dev, "unable to alloc data struct.\n");
++		goto err_data;
++	}
++	aes->dev = dev;
++	aes->clk_gate = devm_clk_get(&pdev->dev, "gate_aes");
++	if (IS_ERR(aes->clk_gate)) {
++		dev_err(&pdev->dev, "cannot find RTC clock\n");
++		err = PTR_ERR(aes->clk_gate);
++		goto err_data;
++	}
++
++	clk_prepare_enable(aes->clk_gate);
++	aes->clk_gate = devm_clk_get(&pdev->dev, "gate_pdma");
++	if (IS_ERR(aes->clk_gate)) {
++		dev_err(&pdev->dev, "cannot find aes clock\n");
++		err = PTR_ERR(aes->clk_gate);
++		goto err_data;
++	}
++
++	clk_prepare_enable(aes->clk_gate);
++	printk("gate = %lx\n", *(unsigned long*)0xb0000020);
++
++	platform_set_drvdata(pdev, aes);
++
++	reset_mcu();
++	memcpy((void*)MCU_BOOT,pdma_wait,64);
++	boot_up_mcu();
++
++	mdelay(100);
++	/* *(unsigned long*)0xb3421030 = 1; */
++
++	spin_lock_init(&aes->lock);
++	crypto_init_queue(&aes->queue, INGENIC_AES_QUEUE_LENGTH);
++
++	err = ingenic_aes_get_res_pdev(aes, pdev);
++	if (err)
++		goto err_data;
++
++	err = ingenic_aes_dma_init(aes);
++	if (err)
++		goto err_data;
++
++	INIT_LIST_HEAD(&aes->list);
++	spin_lock(&list_lock);
++	list_add_tail(&aes->list, &dev_list);
++	spin_unlock(&list_lock);
++	for (i = 0; i < aes->pdata->size; i++) {
++			algp = &aes->pdata->algs_list[i];
++			pr_info("reg alg: %s\n", algp->base.cra_name);
++			err = crypto_register_skcipher(algp);
++			if (err)
++				goto err_algs;
++			aes->pdata->registered++;
++	}
++	printk("ingenic aes[%d] register ok.",aes->pdata->registered);
++	return 0;
++err_algs:
++	for (i = aes->pdata->registered - 1; i >= 0; i--)
++		crypto_unregister_skcipher(&aes->pdata->algs_list[i]);
++	ingenic_aes_dma_cleanup(aes);
++err_data:
++	dev_err(dev, "initialization failed.\n");
++	return err;
++}
++
++static int ingenic_aes_remove(struct platform_device *pdev)
++{
++	struct ingenic_aes_dev *aes = platform_get_drvdata(pdev);
++	int i;
++
++	if (!aes)
++		return -ENODEV;
++
++	spin_lock(&list_lock);
++	list_del(&aes->list);
++	spin_unlock(&list_lock);
++	for (i = aes->pdata->registered - 1; i >= 0; i--)
++		crypto_unregister_skcipher(&aes->pdata->algs_list[i]);
++	aes->pdata->registered = 0;
++	ingenic_aes_dma_cleanup(aes);
++	pm_runtime_disable(aes->dev);
++	kfree(aes);
++	aes = NULL;
++
++	return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int ingenic_aes_suspend(struct device *dev)
++{
++	pm_runtime_put_sync(dev);
++	return 0;
++}
++
++static int ingenic_aes_resume(struct device *dev)
++{
++	pm_runtime_get_sync(dev);
++	return 0;
++}
++#endif
++
++static const struct dev_pm_ops ingenic_aes_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(ingenic_aes_suspend, ingenic_aes_resume)
++};
++
++static const struct of_device_id ingenic_aes_dt_match[] = {
++	{ .compatible = "ingenic,aes", .data = NULL },
++	{},
++};
++MODULE_DEVICE_TABLE(of, aic_dt_match);
++
++
++static struct platform_driver ingenic_aes_driver = {
++	.probe	= ingenic_aes_probe,
++	.remove	= ingenic_aes_remove,
++	.driver	= {
++		.name	= "aes",
++		.owner	= THIS_MODULE,
++		.pm	= &ingenic_aes_pm_ops,
++		.of_match_table = of_match_ptr(ingenic_aes_dt_match),
++	},
++};
++
++module_platform_driver(ingenic_aes_driver);
++
++MODULE_DESCRIPTION("Ingenic AES hw acceleration support.");
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Stephon.Qiu");
+diff --git a/module_drivers/drivers/crypto/ingenic-aes.h b/module_drivers/drivers/crypto/ingenic-aes.h
+new file mode 100644
+index 000000000..f0f4a2b85
+--- /dev/null
++++ b/module_drivers/drivers/crypto/ingenic-aes.h
+@@ -0,0 +1,113 @@
++#ifndef __INGENIC_AES_H__
++#define __INGENIC_AES_H__
++
++#define INGENIC_AES_QUEUE_LENGTH       (50)
++#define INGENIC_AES_CACHE_PAGE_SHIFT   (0)
++#define DMA_MIN     4
++
++#define AES_ASCR      (0x00)
++#define AES_ASSR      (0x04)
++#define AES_ASINTM    (0x08)
++#define AES_ASSA      (0x0c)
++#define AES_ASDA      (0x10)
++#define AES_ASTC      (0x14)
++#define AES_ASDI      (0x18)
++#define AES_ASDO      (0x1c)
++#define AES_ASKY      (0x20)
++#define AES_ASIV      (0x24)
++
++#define ASCR_PS_DEF   (3 << 28)
++#define ASCR_CLR      (1 << 10)
++
++#define ASCR_DMAS     (1 << 9)
++#define ASCR_DMAE     (1 << 8)
++
++#define ASCR_KEYL(len)   ((len) << 6)
++
++#define ECB_ALG       (0)
++#define CBC_ALG       (1)
++#define ASCR_ALGS(alg) ((alg) << 5)
++
++#define ENCRYPTO_MODE  (0)
++#define DECRYPTO_MODE  (1)
++#define ASCR_DECE(m)  ((m) << 4)
++
++
++#define ASCR_AESS     (1 << 3)
++#define ASCR_KEYS     (1 << 2)
++#define ASCR_INIT_IV  (1 << 1)
++#define ASCR_EN       (1 << 0)
++
++struct ingenic_aes_reqctx {
++	unsigned long mode;
++};
++
++struct ingenic_aes_ctx {
++	struct ingenic_aes_dev *aes;
++
++	int		keylen;
++	unsigned long		key[AES_KEYSIZE_256 / sizeof(unsigned long)];
++	unsigned long	flags;
++	struct crypto_skcipher	*fallback;
++};
++
++/* struct ingenic_aes_algs_info { */
++/* 	struct crypto_alg	*algs_list; */
++/* 	unsigned int		size; */
++/* 	unsigned int		registered; */
++/* }; */
++struct ingenic_aes_pdata {
++	struct skcipher_alg	*algs_list;
++	unsigned int		size;
++	unsigned int		registered;
++};
++
++struct ingenic_aes_dev {
++	struct list_head	list;
++	void __iomem	*io_base;
++	int 			irq;
++	struct clk		*clk_gate;
++	struct ingenic_aes_ctx	*ctx;
++	struct device		*dev;
++	unsigned long		flags;
++	int			err;
++
++	spinlock_t		lock;
++	struct crypto_queue	queue;
++	struct skcipher_request		*req;
++	size_t				total;
++
++	struct scatterlist		*in_sg;
++
++	struct scatterlist		in_sgl;
++	size_t				in_offset;
++	struct scatterlist		*out_sg;
++	struct scatterlist		out_sgl;
++	size_t				out_offset;
++
++	size_t			buflen;
++	void			*buf_in;
++	void			*buf_out;
++	dma_addr_t		dma_addr_in;
++	dma_addr_t		dma_addr_out;
++
++	size_t			dma_size;
++	struct ingenic_aes_pdata *pdata;
++};
++
++
++#define FLAGS_MODE_MASK		0x000f
++#define FLAGS_DECRYPT		BIT(0)
++#define FLAGS_CBC		BIT(1)
++
++#define FLAGS_INIT		BIT(4)
++#define FLAGS_FAST		BIT(5)
++#define FLAGS_BUSY		BIT(6)
++
++#define MCU_BOOT		0xb3422000
++
++#define DMCS                    0xb3421030
++#define boot_up_mcu()           *(volatile unsigned int *)(DMCS) = 0;
++#define reset_mcu()           *(volatile unsigned int *)(DMCS) = 1;
++
++#endif /*__INGENIC_AES_H__*/
+diff --git a/module_drivers/drivers/crypto/ingenic-hash.c b/module_drivers/drivers/crypto/ingenic-hash.c
+new file mode 100644
+index 000000000..fee8942a3
+--- /dev/null
++++ b/module_drivers/drivers/crypto/ingenic-hash.c
+@@ -0,0 +1,1111 @@
++/*
++ * Cryptographic API.
++ *
++ * Support for Ingenic HASH HW acceleration.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ */
++
++#include <linux/err.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/errno.h>
++#include <linux/clk.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/scatterlist.h>
++#include <linux/dma-mapping.h>
++#include <linux/pm_runtime.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_address.h>
++#include <linux/io.h>
++#include <linux/crypto.h>
++#include <linux/interrupt.h>
++#include <crypto/scatterwalk.h>
++#include <crypto/hash.h>
++#include <linux/delay.h>
++#include <crypto/internal/hash.h>
++#include "ingenic-hash.h"
++#include <crypto/sha.h>
++
++/* keep registered devices data here */
++static LIST_HEAD(dev_list);
++static DEFINE_SPINLOCK(list_lock);
++
++
++static inline unsigned long hash_read(struct ingenic_hash_dev *hash, unsigned long offset)
++{
++	return readl(hash->io_base + offset);
++}
++
++static inline void hash_write(struct ingenic_hash_dev *hash, unsigned long offset,
++	unsigned long value)
++{
++	writel(value, hash->io_base + offset);
++}
++
++static inline void dump_reg(struct ingenic_hash_dev *hash)
++{
++	dev_info(hash->dev,"HASH_HSCR: 0x%08lx\n",hash_read(hash,HASH_HSCR));
++	dev_info(hash->dev,"HASH_HSSR: 0x%08lx\n",hash_read(hash,HASH_HSSR));
++	dev_info(hash->dev,"hash_ASINTM: 0x%08lx\n",hash_read(hash,HASH_HSINTM));
++	dev_info(hash->dev,"HASH_HSSA: 0x%08lx\n",hash_read(hash,HASH_HSSA));
++	dev_info(hash->dev,"HASH_HSTC: 0x%08lx\n",hash_read(hash,HASH_HSTC));
++}
++static inline int ingenic_hash_hw_init(struct ingenic_hash_dev *hash,struct ingenic_hash_reqctx *ctx)
++{
++	/*
++	 * clocks are enabled when request starts and disabled when finished.
++	 * It may be long delays between requests.
++	 * Device might go to off mode to save power.
++	 */
++	unsigned int alg = -1;
++	unsigned int init_data = 0;
++	pm_runtime_get_sync(hash->dev);
++
++	if(ctx->flags & HASH_FLAGS_MD5){
++		alg = 0;
++		init_data = 0;
++	}else if(ctx->flags & HASH_FLAGS_SHA1)
++	{
++		init_data = 3 << 7;
++		alg = 1;
++	}else if(ctx->flags & HASH_FLAGS_SHA224)
++	{
++		init_data = 3 << 7;
++		alg = 2;
++	}else if(ctx->flags & HASH_FLAGS_SHA256)
++	{
++		init_data = 3 << 7;
++		alg = 3;
++	}else if(ctx->flags & HASH_FLAGS_SHA384)
++	{
++		init_data = 3 << 7;
++		alg = 4;
++	}else if(ctx->flags & HASH_FLAGS_SHA512)
++	{
++		init_data = 3 << 7;
++		alg = 5;
++	}
++	init_data |= 3 << 28 | 1 << 4 | alg << 1 | 1;
++	hash_write(hash, HASH_HSCR,init_data);
++	hash_write(hash,HASH_HSINTM,0);
++	hash->flags |= HASH_FLAGS_INIT;
++	return 0;
++}
++static int ingenic_hash_update_dma_stop(struct ingenic_hash_dev *hash)
++{
++	struct ingenic_hash_reqctx *ctx = ahash_request_ctx(hash->req);
++
++	if (ctx->flags & HASH_FLAGS_SG) {
++		dma_unmap_sg(hash->dev, ctx->sg, 1, DMA_TO_DEVICE);
++		if (ctx->sg->length == ctx->offset) {
++			ctx->sg = sg_next(ctx->sg);
++			if (ctx->sg)
++				ctx->offset = 0;
++		}
++		if (ctx->flags & HASH_FLAGS_PAD) {
++			dma_unmap_single(hash->dev, ctx->dma_addr,
++				ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
++		}
++	} else {
++		dma_unmap_single(hash->dev, ctx->dma_addr, ctx->buflen +
++			ctx->block_size, DMA_TO_DEVICE);
++	}
++
++	return 0;
++}
++static void ingenic_hash_copy_hash(struct ahash_request *req)
++{
++	struct ingenic_hash_reqctx *ctx = ahash_request_ctx(req);
++	u32 *hash = (u32 *)ctx->digest;
++	int i;
++	if(ctx->flags & HASH_FLAGS_MD5){
++		for (i = 0; i < MD5_DIGEST_SIZE / sizeof(u32); i++)
++			hash[i] = hash_read(ctx->hash, HASH_HSDO);
++	}else if (ctx->flags & HASH_FLAGS_SHA1)
++		for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++)
++			hash[i] = hash_read(ctx->hash, HASH_HSDO);
++	else if (ctx->flags & HASH_FLAGS_SHA224)
++		for (i = 0; i < SHA224_DIGEST_SIZE / sizeof(u32); i++)
++			hash[i] = hash_read(ctx->hash, HASH_HSDO);
++	else if (ctx->flags & HASH_FLAGS_SHA256)
++		for (i = 0; i < SHA256_DIGEST_SIZE / sizeof(u32); i++)
++			hash[i] = hash_read(ctx->hash, HASH_HSDO);
++	else if (ctx->flags & HASH_FLAGS_SHA384)
++		for (i = 0; i < SHA384_DIGEST_SIZE / sizeof(u32); i++)
++			hash[i] = hash_read(ctx->hash, HASH_HSDO);
++	else
++		for (i = 0; i < SHA512_DIGEST_SIZE / sizeof(u32); i++)
++			hash[i] = hash_read(ctx->hash, HASH_HSDO);
++}
++
++static void ingenic_hash_copy_ready_hash(struct ahash_request *req)
++{
++	struct ingenic_hash_reqctx *ctx = ahash_request_ctx(req);
++	if (!req->result)
++		return;
++	if (ctx->flags & HASH_FLAGS_MD5)
++		memcpy(req->result, ctx->digest, MD5_DIGEST_SIZE);
++	if (ctx->flags & HASH_FLAGS_SHA1)
++		memcpy(req->result, ctx->digest, SHA1_DIGEST_SIZE);
++	else if (ctx->flags & HASH_FLAGS_SHA224)
++		memcpy(req->result, ctx->digest, SHA224_DIGEST_SIZE);
++	else if (ctx->flags & HASH_FLAGS_SHA256)
++		memcpy(req->result, ctx->digest, SHA256_DIGEST_SIZE);
++	else if (ctx->flags & HASH_FLAGS_SHA384)
++		memcpy(req->result, ctx->digest, SHA384_DIGEST_SIZE);
++	else
++		memcpy(req->result, ctx->digest, SHA512_DIGEST_SIZE);
++}
++
++static int ingenic_hash_finish(struct ahash_request *req)
++{
++	struct ingenic_hash_reqctx *ctx = ahash_request_ctx(req);
++	struct ingenic_hash_dev *hash = ctx->hash;
++	int err = 0;
++
++	if (ctx->digcnt[0] || ctx->digcnt[1])
++		ingenic_hash_copy_ready_hash(req);
++
++	dev_dbg(hash->dev, "digcnt: 0x%llx 0x%llx, bufcnt: %d\n", ctx->digcnt[1],
++		ctx->digcnt[0], ctx->bufcnt);
++
++	return err;
++}
++static void ingenic_hash_finish_req(struct ahash_request *req, int err)
++{
++	struct ingenic_hash_reqctx *ctx = ahash_request_ctx(req);
++	struct ingenic_hash_dev *hash = ctx->hash;
++	if(ctx->bufcnt == 0){
++		if (!err) {
++			ingenic_hash_copy_hash(req);
++			if (HASH_FLAGS_FINAL & hash->flags)
++				err = ingenic_hash_finish(req);
++		} else {
++			ctx->flags |= HASH_FLAGS_ERROR;
++		}
++
++		/* atomic operation is not needed here */
++		hash->flags &= ~(HASH_FLAGS_BUSY | HASH_FLAGS_FINAL | HASH_FLAGS_INIT);
++		pm_runtime_put_sync(hash->dev);
++	}
++	/* clk_disable_unprepare(hash->iclk); */
++	if (req->base.complete)
++		req->base.complete(&req->base, err);
++}
++
++static struct ingenic_hash_dev *ingenic_hash_find_dev(struct ingenic_hash_ctx *ctx)
++{
++	struct ingenic_hash_dev *hash = NULL, *tmp;
++
++	spin_lock(&list_lock);
++	hash = ctx->hash;
++	if (!hash) {
++		list_for_each_entry(tmp, &dev_list, list) {
++			/* FIXME: take fist available hash core */
++			hash = tmp;
++			ctx->hash = tmp;
++			break;
++		}
++	}
++	spin_unlock(&list_lock);
++	return hash;
++}
++/*
++ * The purpose of this padding is to ensure that the padded message is a
++ * multiple of 512 bits (SHA1/SHA224/SHA256) or 1024 bits (SHA384/SHA512).
++ * The bit "1" is appended at the end of the message followed by
++ * "padlen-1" zero bits. Then a 64 bits block (SHA1/SHA224/SHA256) or
++ * 128 bits block (SHA384/SHA512) equals to the message length in bits
++ * is appended.
++ *
++ * For SHA1/SHA224/SHA256, padlen is calculated as followed:
++ *  - if message length < 56 bytes then padlen = 56 - message length
++ *  - else padlen = 64 + 56 - message length
++ *
++ * For SHA384/SHA512, padlen is calculated as followed:
++ *  - if message length < 112 bytes then padlen = 112 - message length
++ *  - else padlen = 128 + 112 - message length
++ */
++static void ingenic_hash_fill_padding(struct ingenic_hash_reqctx *ctx, int length)
++{
++
++	unsigned int index, padlen;
++	u64 bits[2];
++	u64 size[2];
++
++	size[0] = ctx->digcnt[0];
++	size[1] = ctx->digcnt[1];
++
++	size[0] += ctx->bufcnt;
++	if (size[0] < ctx->bufcnt)
++		size[1]++;
++
++	size[0] += length;
++	if (size[0]  < length)
++		size[1]++;
++
++	bits[1] = cpu_to_be64(size[0] << 3);
++	bits[0] = cpu_to_be64(size[1] << 3 | size[0] >> 61);
++	if (ctx->flags & (HASH_FLAGS_SHA384 | HASH_FLAGS_SHA512)) {
++		index = ctx->bufcnt & 0x7f;
++		padlen = (index < 112) ? (112 - index) : ((128+112) - index);
++		*(ctx->buffer + ctx->bufcnt) = 0x80;
++		memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1);
++		memcpy(ctx->buffer + ctx->bufcnt + padlen, bits, 16);
++		ctx->bufcnt += padlen + 16;
++		ctx->flags |= HASH_FLAGS_PAD;
++	} else if(ctx->flags & HASH_FLAGS_MD5){
++		unsigned int *d;
++		index = ctx->bufcnt & 0x3f;
++		padlen = (index < 56) ? (56 - index) : ((64+56) - index);
++		*(ctx->buffer + ctx->bufcnt) = 0x80;
++		memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1);
++		d = (unsigned int *)((unsigned char*)ctx->buffer + ctx->bufcnt + padlen);
++		d[0] = cpu_to_le32(size[0] << 3);
++		d[1] = cpu_to_le32(size[0] >> 29);
++		//memcpy(ctx->buffer + ctx->bufcnt + padlen + 1, &bits1[1], 4);
++		ctx->bufcnt += padlen + 8;
++		ctx->flags |= HASH_FLAGS_PAD;
++	}else {
++		index = ctx->bufcnt & 0x3f;
++		padlen = (index < 56) ? (56 - index) : ((64+56) - index);
++		*(ctx->buffer + ctx->bufcnt) = 0x80;
++		memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1);
++		memcpy(ctx->buffer + ctx->bufcnt + padlen, &bits[1], 8);
++		ctx->bufcnt += padlen + 8;
++		ctx->flags |= HASH_FLAGS_PAD;
++	}
++	/* for(int i = 0;i < 64/4;i++){ */
++	/* 	unsigned int *d = ctx->buffer; */
++	/* 	d +=(ctx->bufcnt - 64) / sizeof(unsigned int); */
++	/* 	printk("buffer[%p]%03d: 0x%08x\n",d+i,i,d[i]); */
++	/* } */
++}
++
++static size_t ingenic_hash_append_sg(struct ingenic_hash_reqctx *ctx)
++{
++	size_t count;
++
++	while ((ctx->bufcnt < ctx->buflen) && ctx->total) {
++		count = min(ctx->sg->length - ctx->offset, ctx->total);
++		count = min(count, ctx->buflen - ctx->bufcnt);
++
++		if (count <= 0)
++			break;
++
++		scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, ctx->sg,
++			ctx->offset, count, 0);
++
++		ctx->bufcnt += count;
++		ctx->offset += count;
++		ctx->total -= count;
++
++		if (ctx->offset == ctx->sg->length) {
++			ctx->sg = sg_next(ctx->sg);
++			if (ctx->sg)
++				ctx->offset = 0;
++			else
++				ctx->total = 0;
++		}
++	}
++	return 0;
++}
++static int ingenic_hash_xmit_start(struct ingenic_hash_dev *hash, dma_addr_t dma_addr,
++	size_t length, int final)
++{
++	struct ingenic_hash_reqctx *ctx = ahash_request_ctx(hash->req);
++	ctx->digcnt[0] += length;
++	if (ctx->digcnt[0] < length)
++		ctx->digcnt[1]++;
++
++	if (final)
++		hash->flags |= HASH_FLAGS_FINAL;
++	hash->flags |= HASH_FLAGS_DMA_ACTIVE;
++	hash_write(hash,HASH_HSSA,dma_addr);
++	hash_write(hash, HASH_HSTC, length / (512 / 8));
++
++	hash_write(hash, HASH_HSINTM,2);
++//	dump_reg(hash);
++	{
++		unsigned int val;
++		val = hash_read(hash, HASH_HSCR);
++		hash_write(hash, HASH_HSCR, val | (3 << 5));
++	}
++	return -EINPROGRESS;
++}
++
++static int ingenic_hash_xmit_dma_map(struct ingenic_hash_dev *hash,
++	struct ingenic_hash_reqctx *ctx,
++	size_t length, int final)
++{
++	ctx->dma_addr = dma_map_single(hash->dev, ctx->buffer,
++		ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
++
++	if (dma_mapping_error(hash->dev, ctx->dma_addr)) {
++		dev_err(hash->dev, "dma %u bytes error\n", ctx->buflen +
++			ctx->block_size);
++		return -EINVAL;
++	}
++
++	ctx->flags &= ~HASH_FLAGS_SG;
++
++	/* next call does not fail... so no unmap in the case of error */
++	return ingenic_hash_xmit_start(hash, ctx->dma_addr, length, final);
++}
++static int ingenic_hash_final_req(struct ingenic_hash_dev *hash)
++{
++	struct ahash_request *req = hash->req;
++	struct ingenic_hash_reqctx *ctx = ahash_request_ctx(req);
++	int err = 0;
++	int count;
++
++	ingenic_hash_fill_padding(ctx, 0);
++	count = ctx->bufcnt;
++	ctx->bufcnt = 0;
++	err = ingenic_hash_xmit_dma_map(hash, ctx, count, 1);
++	dev_dbg(hash->dev, "final_req: err: %d\n", err);
++
++	return err;
++}
++
++static int ingenic_hash_update_dma_slow(struct ingenic_hash_dev *hash)
++{
++	struct ingenic_hash_reqctx *ctx = ahash_request_ctx(hash->req);
++	unsigned int final;
++	size_t count;
++
++	ingenic_hash_append_sg(ctx);
++
++	final = (ctx->flags & HASH_FLAGS_FINUP) && !ctx->total;
++
++	dev_dbg(hash->dev, "slow: bufcnt: %u, digcnt: 0x%llx 0x%llx, final: %d\n",
++		ctx->bufcnt, ctx->digcnt[1], ctx->digcnt[0], final);
++
++	if (final)
++		ingenic_hash_fill_padding(ctx, 0);
++
++	if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
++		count = ctx->bufcnt;
++		ctx->bufcnt = 0;
++		return ingenic_hash_xmit_dma_map(hash, ctx, count, final);
++	}
++
++	return 0;
++}
++
++
++static int ingenic_hash_update_dma_start(struct ingenic_hash_dev *hash)
++{
++	struct ingenic_hash_reqctx *ctx = ahash_request_ctx(hash->req);
++	unsigned int length, final, tail;
++	struct scatterlist *sg;
++	unsigned int count;
++	sg = ctx->sg;
++	if (!ctx->total && !ctx->bufcnt){
++		return 0;
++	}
++	if(ctx->flags & HASH_FLAGS_FINUP)
++	{
++		if (ctx->bufcnt || ctx->offset)
++			return ingenic_hash_update_dma_slow(hash);
++		dev_dbg(hash->dev, "fast: digcnt: 0x%llx 0x%llx, bufcnt: %u, total: %u\n",
++			ctx->digcnt[1], ctx->digcnt[0], ctx->bufcnt, ctx->total);
++
++		if (!IS_ALIGNED(sg->offset, sizeof(u32)))
++			return ingenic_hash_update_dma_slow(hash);
++
++		if (!sg_is_last(sg) && !IS_ALIGNED(sg->length, ctx->block_size)){
++			/* size is not ctx->block_size aligned */
++			return ingenic_hash_update_dma_slow(hash);
++		}
++	}
++	length = min(ctx->total, sg->length);
++	if (sg_is_last(sg)) {
++		if (!(ctx->flags & HASH_FLAGS_FINUP))
++		{
++		/* not last sg must be ctx->block_size aligned */
++			tail = length & (ctx->block_size - 1);
++			length -= tail;
++			if(length == 0){
++				ingenic_hash_append_sg(ctx);
++				hash->flags &= ~HASH_FLAGS_BUSY;
++				return 0;
++			}
++		}else if(length + ctx->bufcnt > ctx->buflen)
++		{
++			length = ctx->buflen - ctx->bufcnt;
++		}
++	}
++	final = (ctx->flags & HASH_FLAGS_FINUP) && !(ctx->total - length);
++	/* Add padding */
++	if (final) {
++
++		sg = ctx->sg;
++		ingenic_hash_append_sg(ctx);
++
++		ingenic_hash_fill_padding(ctx, 0);
++
++		ctx->dma_addr = dma_map_single(hash->dev, ctx->buffer,
++			ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
++
++		if (dma_mapping_error(hash->dev, ctx->dma_addr)) {
++			dev_err(hash->dev, "dma %u bytes error\n",
++				ctx->buflen + ctx->block_size);
++			return -EINVAL;
++		}
++
++		if (ctx->bufcnt != 0) {
++			ctx->flags &= ~HASH_FLAGS_SG;
++			count = ctx->bufcnt;
++			ctx->bufcnt = 0;
++			return ingenic_hash_xmit_start(hash, ctx->dma_addr, count, final);
++		}
++	}else if(ctx->bufcnt && (ctx->flags & HASH_FLAGS_FINUP)){
++		return ingenic_hash_update_dma_slow(hash);
++	}else{
++		ctx->total -= length;
++		ctx->offset = length; /* offset where to start slow */
++	}
++
++	if (!dma_map_sg(hash->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
++		dev_err(hash->dev, "dma_map_sg  error\n");
++		return -EINVAL;
++	}
++	ctx->flags |= HASH_FLAGS_SG;
++
++	/* next call does not fail... so no unmap in the case of error */
++	return ingenic_hash_xmit_start(hash, sg_dma_address(ctx->sg), length, final);
++}
++
++static int ingenic_hash_update_req(struct ingenic_hash_dev *hash)
++{
++	struct ahash_request *req = hash->req;
++	struct ingenic_hash_reqctx *ctx = ahash_request_ctx(req);
++	int err;
++
++	dev_dbg(hash->dev, "update_req: total: %u, digcnt: 0x%llx 0x%llx\n",
++		ctx->total, ctx->digcnt[1], ctx->digcnt[0]);
++
++	err = ingenic_hash_update_dma_start(hash);
++
++	/* wait for dma completion before can take more data */
++	dev_dbg(hash->dev, "update: err: %d, digcnt: 0x%llx 0%llx\n",
++		err, ctx->digcnt[1], ctx->digcnt[0]);
++
++	return err;
++}
++static int ingenic_hash_handle_queue(struct ingenic_hash_dev *hash,
++	struct ahash_request *req)
++{
++	struct crypto_async_request *async_req, *backlog;
++	struct ingenic_hash_reqctx *ctx;
++	unsigned long flags;
++	int err = 0, ret = 0;
++	spin_lock_irqsave(&hash->lock, flags);
++	if (req)
++		ret = ahash_enqueue_request(&hash->queue, req);
++
++	if (HASH_FLAGS_BUSY & hash->flags) {
++		spin_unlock_irqrestore(&hash->lock, flags);
++		return ret;
++	}
++
++	backlog = crypto_get_backlog(&hash->queue);
++	async_req = crypto_dequeue_request(&hash->queue);
++	if (async_req)
++		hash->flags |= HASH_FLAGS_BUSY;
++
++	spin_unlock_irqrestore(&hash->lock, flags);
++
++	if (!async_req)
++		return ret;
++
++	if (backlog)
++		backlog->complete(backlog, -EINPROGRESS);
++
++	req = ahash_request_cast(async_req);
++	hash->req = req;
++	ctx = ahash_request_ctx(req);
++
++	dev_dbg(hash->dev, "handling new req, op: %lu, nbytes: %d\n",
++		ctx->op, req->nbytes);
++
++	if(!(hash->flags & HASH_FLAGS_INIT)){
++		err = ingenic_hash_hw_init(hash,ctx);
++		if (err)
++			goto err1;
++	}
++	/* if (ctx->op == HASH_OP_UPDATE) { */
++		err = ingenic_hash_update_req(hash);
++	/* 	if (err != -EINPROGRESS && (ctx->flags & HASH_FLAGS_FINUP)) */
++	/* 		/\* no final() after finup() *\/ */
++	/* 		err = ingenic_hash_final_req(hash); */
++	/* } else if (ctx->op == HASH_OP_FINAL) { */
++	/* 	err = ingenic_hash_final_req(hash); */
++	/* } */
++err1:
++	return err;
++#if 0
++err1:
++	if (err != -EINPROGRESS)
++		/* done_task will not finish it, so do it here */
++		ingenic_hash_finish_req(req, err);
++
++	dev_dbg(hash->dev, "exit, err: %d\n", err);
++
++	return err;
++#endif
++}
++
++static int ingenic_hash_enqueue(struct ahash_request *req, unsigned int op)
++{
++	struct ingenic_hash_reqctx *ctx = ahash_request_ctx(req);
++	struct ingenic_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
++	struct ingenic_hash_dev *hash = tctx->hash;
++
++	ctx->op = op;
++
++	return ingenic_hash_handle_queue(hash, req);
++}
++static void hash_dma_done(struct ingenic_hash_dev *hash)
++{
++	int err = 0;
++	if (HASH_FLAGS_DMA_ACTIVE & hash->flags) {
++		hash->flags &= ~HASH_FLAGS_DMA_ACTIVE;
++		ingenic_hash_update_dma_stop(hash);
++	}
++	err = ingenic_hash_update_dma_start(hash);
++	if (err != -EINPROGRESS){
++		ingenic_hash_finish_req(hash->req, err);
++	}else if (!(HASH_FLAGS_BUSY & hash->flags)) {
++		ingenic_hash_handle_queue(hash, NULL);
++	}
++}
++static irqreturn_t ingenic_hash_irqthread(int irq, void *data)
++{
++	struct ingenic_hash_dev *hash = (struct ingenic_hash_dev *)data;
++	unsigned int val;
++	val = hash_read(hash,HASH_HSSR);
++	hash_write(hash,HASH_HSSR,val);
++	if(val & 2){
++		hash_dma_done(hash);
++	}else{
++		printk("Don't support the irq");
++	}
++	return IRQ_HANDLED;
++}
++
++/* ********************** ALG API ************************************ */
++
++static int ingenic_hash_init(struct ahash_request *req)
++{
++	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
++	struct ingenic_hash_ctx *ctx = crypto_ahash_ctx(tfm);
++	struct ingenic_hash_reqctx *rctx = ahash_request_ctx(req);
++	struct ingenic_hash_dev *hash = NULL;
++	/* struct ingenic_hash_dev *tmp; */
++	ENTER();
++	hash = ingenic_hash_find_dev(ctx);
++
++	rctx->hash = hash;
++	rctx->flags = 0;
++	dev_dbg(hash->dev, "init: digest size: %d\n",
++		crypto_ahash_digestsize(tfm));
++
++	switch (crypto_ahash_digestsize(tfm)) {
++	case MD5_DIGEST_SIZE:
++		rctx->flags |= HASH_FLAGS_MD5;
++		rctx->block_size = MD5_BLOCK_SIZE;
++	case SHA1_DIGEST_SIZE:
++		rctx->flags |= HASH_FLAGS_SHA1;
++		rctx->block_size = SHA1_BLOCK_SIZE;
++		break;
++	case SHA224_DIGEST_SIZE:
++		rctx->flags |= HASH_FLAGS_SHA224;
++		rctx->block_size = SHA224_BLOCK_SIZE;
++		break;
++	case SHA256_DIGEST_SIZE:
++		rctx->flags |= HASH_FLAGS_SHA256;
++		rctx->block_size = SHA256_BLOCK_SIZE;
++		break;
++	case SHA384_DIGEST_SIZE:
++		rctx->flags |= HASH_FLAGS_SHA384;
++		rctx->block_size = SHA384_BLOCK_SIZE;
++		break;
++	case SHA512_DIGEST_SIZE:
++		rctx->flags |= HASH_FLAGS_SHA512;
++		rctx->block_size = SHA512_BLOCK_SIZE;
++		break;
++	default:
++		return -EINVAL;
++		break;
++	}
++	rctx->bufcnt = 0;
++	rctx->total = 0;
++	rctx->digcnt[0] = 0;
++	rctx->digcnt[1] = 0;
++	rctx->buffer = ctx->buf;
++	rctx->buflen = HASH_BUFFER_LEN;
++	EXIT();
++
++	return 0;
++}
++static int ingenic_hash_final(struct ahash_request *req)
++{
++	struct ingenic_hash_reqctx *ctx = ahash_request_ctx(req);
++	struct ingenic_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
++	struct ingenic_hash_dev *hash = tctx->hash;
++
++	int err = 0;
++	ENTER();
++	ctx->flags |= HASH_FLAGS_FINUP;
++	if (ctx->flags & HASH_FLAGS_ERROR){
++		EXIT();
++		return 0; /* uncompleted hash is not needed */
++	}
++	if (ctx->bufcnt) {
++		err = ingenic_hash_enqueue(req, HASH_OP_FINAL);
++		EXIT();
++		return err;
++	} else if (!(ctx->flags & HASH_FLAGS_PAD)) { /* add padding */
++		err = ingenic_hash_hw_init(hash,ctx);
++		if (err)
++			goto err1;
++		hash->req = req;
++		hash->flags |= HASH_FLAGS_BUSY;
++		err = ingenic_hash_final_req(hash);
++	} else {
++		/* copy ready hash (+ finalize hmac) */
++		return ingenic_hash_finish(req);
++	}
++err1:
++	if (err != -EINPROGRESS)
++		/* done_task will not finish it, so do it here */
++		ingenic_hash_finish_req(req, err);
++	EXIT();
++	return err;
++}
++
++static int ingenic_hash_update(struct ahash_request *req)
++{
++	struct ingenic_hash_reqctx *ctx = ahash_request_ctx(req);
++	int ret;
++	ENTER();
++	if (!req->nbytes){
++		EXIT();
++		return 0;
++	}
++
++	ctx->total = req->nbytes;
++	ctx->sg = req->src;
++
++	ctx->offset = 0;
++      if (ctx->bufcnt + ctx->total < ctx->buflen) {
++		ingenic_hash_append_sg(ctx);
++		return 0;
++	}
++	ret = ingenic_hash_enqueue(req, HASH_OP_UPDATE);
++	EXIT();
++	return ret;
++}
++
++static int ingenic_hash_finup(struct ahash_request *req)
++{
++	struct ingenic_hash_reqctx *ctx = ahash_request_ctx(req);
++	int err1, err2;
++	ENTER();
++	ctx->flags |= HASH_FLAGS_FINUP;
++
++	err1 = ingenic_hash_update(req);
++	if (err1 == -EINPROGRESS || err1 == -EBUSY)
++		return err1;
++
++	/*
++	 * final() has to be always called to cleanup resources
++	 * even if udpate() failed, except EINPROGRESS
++	 */
++	err2 = ingenic_hash_final(req);
++	EXIT();
++	return err1 ?: err2;
++}
++
++static int ingenic_hash_digest(struct ahash_request *req)
++{
++	return ingenic_hash_init(req) ?: ingenic_hash_finup(req);
++}
++
++static int ingenic_hash_export(struct ahash_request *req, void *out)
++{
++	struct ingenic_hash_reqctx *rctx = ahash_request_ctx(req);
++
++	memcpy(out, rctx, sizeof(*rctx));
++
++	return 0;
++}
++
++static int ingenic_hash_import(struct ahash_request *req, const void *in)
++{
++	struct ingenic_hash_reqctx *rctx = ahash_request_ctx(req);
++
++	memcpy(rctx, in, sizeof(*rctx));
++
++	return 0;
++}
++
++static int ingenic_hash_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
++{
++//	struct ingenic_hash_ctx *tctx = crypto_tfm_ctx(tfm);
++//	const char *alg_name = crypto_tfm_alg_name(tfm);
++//	ENTER();
++//	/* Allocate a fallback and abort if it failed. */
++//	tctx->fallback = crypto_alloc_shash(alg_name, 0,
++//		CRYPTO_ALG_NEED_FALLBACK);
++//	if (IS_ERR(tctx->fallback)) {
++//		pr_err("ingenic-hash: fallback driver '%s' could not be loaded.\n",
++//			alg_name);
++//		EXIT();
++//		return PTR_ERR(tctx->fallback);
++//	}
++	crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
++		sizeof(struct ingenic_hash_reqctx));
++//	EXIT();
++	return 0;
++}
++
++static int ingenic_hash_cra_init(struct crypto_tfm *tfm)
++{
++	return ingenic_hash_cra_init_alg(tfm, NULL);
++}
++
++static void ingenic_hash_cra_exit(struct crypto_tfm *tfm)
++{
++	struct ingenic_hash_ctx *tctx = crypto_tfm_ctx(tfm);
++	ENTER();
++	tctx->fallback = NULL;
++	EXIT();
++}
++
++
++/* ********************** ALGS ************************************ */
++static struct ahash_alg hash_md5_algs[] = {
++#if 0
++	{
++		.init		= ingenic_hash_init,
++		.update		= ingenic_hash_update,
++		.final		= ingenic_hash_final,
++		.finup		= ingenic_hash_finup,
++		.digest		= ingenic_hash_digest,
++		.halg = {
++			.digestsize	= MD5_DIGEST_SIZE,
++	        .statesize	= 1,
++			.base	= {
++				.cra_name		= "md5",
++				.cra_driver_name= "ingenic-sha1",
++				.cra_priority	= 100,
++				.cra_flags		= CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
++				.cra_blocksize	= MD5_BLOCK_SIZE,
++				.cra_ctxsize	= sizeof(struct ingenic_hash_ctx),
++				.cra_alignmask	= 0,
++				.cra_module		= THIS_MODULE,
++				.cra_init		= ingenic_hash_cra_init,
++				.cra_exit		= ingenic_hash_cra_exit,
++			}
++		}
++	},
++#endif
++	{
++		.init		= ingenic_hash_init,
++		.update		= ingenic_hash_update,
++		.final		= ingenic_hash_final,
++		.finup		= ingenic_hash_finup,
++		.export		= ingenic_hash_export,
++		.import		= ingenic_hash_import,
++		.digest		= ingenic_hash_digest,
++		.halg = {
++			.digestsize	= SHA1_DIGEST_SIZE,
++			.statesize = sizeof(struct ingenic_hash_reqctx),
++			.base	= {
++				.cra_name		= "sha1",
++				.cra_driver_name	= "ingenic-sha1",
++				.cra_priority		= 100,
++				.cra_flags		= CRYPTO_ALG_ASYNC,
++				.cra_blocksize		= SHA1_BLOCK_SIZE,
++				.cra_ctxsize		= sizeof(struct ingenic_hash_ctx),
++				.cra_alignmask		= 0,
++				.cra_module		= THIS_MODULE,
++				.cra_init		= ingenic_hash_cra_init,
++				.cra_exit		= ingenic_hash_cra_exit,
++			}
++		}
++	},
++	{
++		.init		= ingenic_hash_init,
++		.update		= ingenic_hash_update,
++		.final		= ingenic_hash_final,
++		.finup		= ingenic_hash_finup,
++		.export		= ingenic_hash_export,
++		.import		= ingenic_hash_import,
++		.digest		= ingenic_hash_digest,
++		.halg = {
++			.digestsize	= SHA224_DIGEST_SIZE,
++			.statesize = sizeof(struct ingenic_hash_reqctx),
++			.base	= {
++				.cra_name		= "sha224",
++				.cra_driver_name	= "ingenic-sha224",
++				.cra_priority		= 100,
++				.cra_flags		= CRYPTO_ALG_ASYNC,
++				.cra_blocksize		= SHA224_BLOCK_SIZE,
++				.cra_ctxsize		= sizeof(struct ingenic_hash_ctx),
++				.cra_alignmask		= 0,
++				.cra_module		= THIS_MODULE,
++				.cra_init		= ingenic_hash_cra_init,
++				.cra_exit		= ingenic_hash_cra_exit,
++			}
++		}
++	},
++	{
++		.init		= ingenic_hash_init,
++		.update		= ingenic_hash_update,
++		.final		= ingenic_hash_final,
++		.finup		= ingenic_hash_finup,
++		.export		= ingenic_hash_export,
++		.import		= ingenic_hash_import,
++		.digest		= ingenic_hash_digest,
++		.halg = {
++			.digestsize	= SHA256_DIGEST_SIZE,
++			.statesize = sizeof(struct ingenic_hash_reqctx),
++			.base	= {
++				.cra_name		= "sha256",
++				.cra_driver_name	= "ingenic-sha256",
++				.cra_priority		= 100,
++				.cra_flags		= CRYPTO_ALG_ASYNC,
++				.cra_blocksize		= SHA256_BLOCK_SIZE,
++				.cra_ctxsize		= sizeof(struct ingenic_hash_ctx),
++				.cra_alignmask		= 0,
++				.cra_module		= THIS_MODULE,
++				.cra_init		= ingenic_hash_cra_init,
++				.cra_exit		= ingenic_hash_cra_exit,
++			}
++		}
++	},
++	{
++		.init		= ingenic_hash_init,
++		.update		= ingenic_hash_update,
++		.final		= ingenic_hash_final,
++		.finup		= ingenic_hash_finup,
++		.digest		= ingenic_hash_digest,
++		.export		= ingenic_hash_export,
++		.import		= ingenic_hash_import,
++		.halg = {
++			.digestsize	= SHA384_DIGEST_SIZE,
++			.statesize = sizeof(struct ingenic_hash_reqctx),
++			.base	= {
++				.cra_name		= "sha384",
++				.cra_driver_name	= "ingenic-sha384",
++				.cra_priority		= 100,
++				.cra_flags		= CRYPTO_ALG_ASYNC,
++				.cra_blocksize		= SHA384_BLOCK_SIZE,
++				.cra_ctxsize		= sizeof(struct ingenic_hash_ctx),
++				.cra_alignmask		= 0x3,
++				.cra_module		= THIS_MODULE,
++				.cra_init		= ingenic_hash_cra_init,
++				.cra_exit		= ingenic_hash_cra_exit,
++			}
++		}
++	},
++	{
++		.init		= ingenic_hash_init,
++		.update		= ingenic_hash_update,
++		.final		= ingenic_hash_final,
++		.finup		= ingenic_hash_finup,
++		.digest		= ingenic_hash_digest,
++		.export		= ingenic_hash_export,
++		.import		= ingenic_hash_import,
++		.halg = {
++			.digestsize	= SHA512_DIGEST_SIZE,
++			.statesize = sizeof(struct ingenic_hash_reqctx),
++			.base	= {
++				.cra_name		= "sha512",
++				.cra_driver_name	= "ingenic-sha512",
++				.cra_priority		= 100,
++				.cra_flags		= CRYPTO_ALG_ASYNC,
++				.cra_blocksize		= SHA512_BLOCK_SIZE,
++				.cra_ctxsize		= sizeof(struct ingenic_hash_ctx),
++				.cra_alignmask		= 0x3,
++				.cra_module		= THIS_MODULE,
++				.cra_init		= ingenic_hash_cra_init,
++				.cra_exit		= ingenic_hash_cra_exit,
++			}
++		}
++	},
++};
++
++static struct ingenic_hash_pdata ingenic_hash_pdata = {
++	.algs_list	= hash_md5_algs,
++	.size		= ARRAY_SIZE(hash_md5_algs),
++};
++static int ingenic_hash_get_res_pdev(struct ingenic_hash_dev *hash,
++	struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct resource *r;
++	int err;
++	int ret = 0;
++	/* Get the base address */
++	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!r) {
++		dev_err(dev, "no MEM resource info\n");
++		err = -ENODEV;
++		goto err;
++	}
++
++	hash->io_base = devm_ioremap(hash->dev, r->start, resource_size(r));
++	if(IS_ERR_OR_NULL(hash->io_base)) {
++		dev_err(&pdev->dev, "Failed to remap io resources!\n");
++		ret = -ENOMEM;
++		goto err;
++	}
++
++	hash->irq = platform_get_irq(pdev,0);
++	if(hash->irq < 0){
++		dev_err(dev,"Failed to request irq resource info\n");
++		ret = -EBUSY;
++		goto err;
++	}
++
++	err = request_threaded_irq(hash->irq,NULL,ingenic_hash_irqthread,
++		IRQF_ONESHOT,dev_name(dev),hash);
++
++	hash->pdata = &ingenic_hash_pdata;
++
++err:
++	return ret;
++}
++
++static int ingenic_hash_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct ingenic_hash_dev *hash;
++	struct ahash_alg *algp;
++	int err = -ENOMEM, i;
++
++	hash = devm_kzalloc(dev,sizeof(struct ingenic_hash_dev), GFP_KERNEL);
++	if (hash == NULL) {
++		dev_err(dev, "unable to alloc data struct.\n");
++		goto err_data;
++	}
++	hash->dev = dev;
++
++	hash->clk_gate = devm_clk_get(&pdev->dev, "gate_hash");
++	if (IS_ERR(hash->clk_gate)) {
++		dev_err(&pdev->dev, "cannot find hash clock\n");
++		err = PTR_ERR(hash->clk_gate);
++		goto err_data;
++	}
++
++	clk_prepare_enable(hash->clk_gate);
++
++	platform_set_drvdata(pdev, hash);
++
++	crypto_init_queue(&hash->queue, INGENIC_HASH_QUEUE_LENGTH);
++	spin_lock_init(&hash->lock);
++	err = ingenic_hash_get_res_pdev(hash, pdev);
++	if (err)
++		goto err_data;
++
++	pm_runtime_enable(dev);
++
++	INIT_LIST_HEAD(&hash->list);
++	spin_lock(&list_lock);
++	list_add_tail(&hash->list, &dev_list);
++
++	spin_unlock(&list_lock);
++	for (i = 0; i < hash->pdata->size; i++) {
++			algp = &hash->pdata->algs_list[i];
++			 pr_info("reg alg:  %s\n", algp->halg.base.cra_name);
++//			INIT_LIST_HEAD(&algp->cra_list);
++			err = crypto_register_ahash(algp);
++			if (err)
++				goto err_algs;
++			hash->pdata->registered++;
++	}
++	printk("ingenic hash[%d] register ok.",hash->pdata->registered);
++	return 0;
++err_algs:
++	for (i = hash->pdata->registered - 1; i >= 0; i--)
++		crypto_unregister_ahash(
++				&hash->pdata->algs_list[i]);
++	pm_runtime_disable(dev);
++err_data:
++	dev_err(dev, "initialization failed.\n");
++	return err;
++}
++
++static int ingenic_hash_remove(struct platform_device *pdev)
++{
++	struct ingenic_hash_dev *hash = platform_get_drvdata(pdev);
++	int i;
++
++	if (!hash)
++		return -ENODEV;
++
++	spin_lock(&list_lock);
++	list_del(&hash->list);
++	spin_unlock(&list_lock);
++	for (i = hash->pdata->registered - 1; i >= 0; i--)
++		crypto_unregister_ahash(
++			&hash->pdata->algs_list[i]);
++	hash->pdata->registered = 0;
++	pm_runtime_disable(hash->dev);
++	kfree(hash);
++	hash = NULL;
++
++	return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int ingenic_hash_suspend(struct device *dev)
++{
++	pm_runtime_put_sync(dev);
++	return 0;
++}
++
++static int ingenic_hash_resume(struct device *dev)
++{
++	pm_runtime_get_sync(dev);
++	return 0;
++}
++#endif
++
++static const struct dev_pm_ops ingenic_hash_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(ingenic_hash_suspend, ingenic_hash_resume)
++};
++
++static const struct of_device_id ingenic_hash_dt_match[] = {
++	{ .compatible = "ingenic,hash", .data = NULL },
++	{},
++};
++
++MODULE_DEVICE_TABLE(of, ingenic_hash_dt_match);
++static struct platform_driver ingenic_hash_driver = {
++	.probe	= ingenic_hash_probe,
++	.remove	= ingenic_hash_remove,
++	.driver	= {
++		.name	= "hash",
++		.owner	= THIS_MODULE,
++		.pm	= &ingenic_hash_pm_ops,
++		.of_match_table = of_match_ptr(ingenic_hash_dt_match),
++	},
++};
++
++module_platform_driver(ingenic_hash_driver);
++
++MODULE_DESCRIPTION("Ingenic MD5,SHA(160,224,256,384,512) hw acceleration support.");
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Stephon.Qiu");
+diff --git a/module_drivers/drivers/crypto/ingenic-hash.h b/module_drivers/drivers/crypto/ingenic-hash.h
+new file mode 100644
+index 000000000..be045a571
+--- /dev/null
++++ b/module_drivers/drivers/crypto/ingenic-hash.h
+@@ -0,0 +1,119 @@
++#ifndef __INGENIC_HASH_H__
++#define __INGENIC_HASH_H__
++
++#define ENTER()
++#define EXIT()
++
++#define INGENIC_HASH_QUEUE_LENGTH       (50)
++#define INGENIC_HASH_CACHE_PAGE_SHIFT   (0)
++#define DMA_MIN     4
++#define HASH_BUFFER_LEN		PAGE_SIZE
++
++/* HASH flags */
++#define HASH_FLAGS_BUSY			BIT(0)
++#define	HASH_FLAGS_FINAL			BIT(1)
++#define HASH_FLAGS_DMA_ACTIVE	BIT(2)
++#define HASH_FLAGS_OUTPUT_READY	BIT(3)
++#define HASH_FLAGS_INIT			BIT(4)
++#define HASH_FLAGS_CPU			BIT(5)
++#define HASH_FLAGS_DMA_READY		BIT(6)
++
++#define HASH_FLAGS_FINUP		BIT(16)
++#define HASH_FLAGS_SG		BIT(17)
++#define HASH_FLAGS_MD5      BIT(18)
++#define HASH_FLAGS_SHA1		BIT(19)
++#define HASH_FLAGS_SHA224	BIT(20)
++#define HASH_FLAGS_SHA256	BIT(21)
++#define HASH_FLAGS_SHA384	BIT(22)
++#define HASH_FLAGS_SHA512	BIT(23)
++#define HASH_FLAGS_ERROR		BIT(24)
++#define HASH_FLAGS_PAD		BIT(25)
++
++#define HASH_OP_UPDATE	1
++#define HASH_OP_FINAL	2
++
++
++#define INGENIC_HASH_DMA_THRESHOLD	56
++
++#define MD5_DIGEST_SIZE         16
++#define MD5_BLOCK_SIZE          64
++
++#define SHA1_DIGEST_SIZE        20
++#define SHA1_BLOCK_SIZE         64
++
++#define SHA224_DIGEST_SIZE	28
++#define SHA224_BLOCK_SIZE	64
++
++#define SHA256_DIGEST_SIZE      32
++#define SHA256_BLOCK_SIZE       64
++
++#define SHA384_DIGEST_SIZE      48
++#define SHA384_BLOCK_SIZE       128
++
++#define SHA512_DIGEST_SIZE      64
++#define SHA512_BLOCK_SIZE       128
++
++#define HASH_HSCR                0
++#define HASH_HSSR                4
++#define HASH_HSINTM              8
++#define HASH_HSSA                0xc
++#define HASH_HSTC                0x10
++#define HASH_HSDI                0x14
++#define HASH_HSDO                0x18
++
++
++struct ingenic_hash_reqctx {
++	struct ingenic_hash_dev	*hash;
++	unsigned long	flags;
++	unsigned long	op;
++
++	u8	digest[SHA512_DIGEST_SIZE] __aligned(sizeof(u32));
++	u64	digcnt[2];
++	size_t	bufcnt;
++	size_t	buflen;
++	dma_addr_t	dma_addr;
++
++	/* walk state */
++	struct scatterlist	*sg;
++	unsigned int	offset;	/* offset in current sg */
++	unsigned int	total;	/* total request */
++
++	size_t block_size;
++	u8 *buffer;
++
++};
++
++struct ingenic_hash_ctx {
++	struct ingenic_hash_dev *hash;
++	unsigned long		flags;
++	/* fallback stuff */
++	struct crypto_ahash	*fallback;
++	u8 buf[HASH_BUFFER_LEN] __aligned(sizeof(u32));
++};
++
++struct ingenic_hash_pdata {
++	struct ahash_alg    *algs_list;
++	unsigned int		size;
++	unsigned int		registered;
++};
++
++struct ingenic_hash_dev {
++	struct list_head	list;
++	void __iomem	*io_base;
++	int 			irq;
++	struct clk		*clk_gate;
++	struct ingenic_hash_ctx	*ctx;
++	struct device		*dev;
++	unsigned long		flags;
++	spinlock_t		lock;
++	struct crypto_queue	queue;
++	struct ahash_request	*req;
++	struct ingenic_hash_pdata *pdata;
++};
++
++#define MCU_BOOT		0xb3422000
++
++#define DMCS                    0xb3421030
++#define boot_up_mcu()           *(volatile unsigned int *)(DMCS) = 0;
++
++#endif	/*__INGENIC_HASH_H__*/
+diff --git a/module_drivers/drivers/dma/Makefile b/module_drivers/drivers/dma/Makefile
+new file mode 100644
+index 000000000..10e2febc6
+--- /dev/null
++++ b/module_drivers/drivers/dma/Makefile
+@@ -0,0 +1 @@
++obj-y += ingenic/
+diff --git a/module_drivers/drivers/dma/ingenic/Kconfig b/module_drivers/drivers/dma/ingenic/Kconfig
+new file mode 100644
+index 000000000..fff749d74
+--- /dev/null
++++ b/module_drivers/drivers/dma/ingenic/Kconfig
+@@ -0,0 +1,25 @@
++config INGENIC_PDMAC
++        bool "Ingenic programmable dma controller (Of Driver)"
++        depends on MACH_XBURST || MACH_XBURST2
++        select DMA_VIRTUAL_CHANNELS
++        select DMA_ENGINE
++        help
++          This selects support for the DMA controller in Ingenic X1000 M200 SoCs.
++          If you have a board based on such a SoC and wish to use DMA for
++          devices which can use the DMA controller, say Y or M here.
++
++
++
++# DMA engine configuration for ingenic
++config INGENIC_DMA_RECEIVE_DXTERNAL_DECIDE
++	tristate "ingenic dma receiving data is externally determined"
++	depends on INGENIC_PDMAC && SOC_X1600
++	default n
++	help
++	How much data is received is externally determined
++
++config INGENIC_AIC_USES_PDMA
++	bool "Ingenic AIC use pdma as dma."
++	depends on INGENIC_PDMAC
++	default n
++
+diff --git a/module_drivers/drivers/dma/ingenic/Makefile b/module_drivers/drivers/dma/ingenic/Makefile
+new file mode 100644
+index 000000000..0fe3db703
+--- /dev/null
++++ b/module_drivers/drivers/dma/ingenic/Makefile
+@@ -0,0 +1,3 @@
++ccflags-y := -I$(srctree)/drivers/dma/
++
++obj-$(CONFIG_INGENIC_PDMAC) += ingenic_dma.o
+diff --git a/module_drivers/drivers/dma/ingenic/ingenic_dma.c b/module_drivers/drivers/dma/ingenic/ingenic_dma.c
+new file mode 100644
+index 000000000..0a98a6df0
+--- /dev/null
++++ b/module_drivers/drivers/dma/ingenic/ingenic_dma.c
+@@ -0,0 +1,1179 @@
++/*
++ * Copyright (C) 2016 Ingenic Semiconductor Co., Ltd.
++ * Author: cli <chen.li@ingenic.com>
++ *
++ * Programmable DMA Controller Driver For Ingenic's SOC,
++ * such as X1000, and so on. (kernel.4.4)
++ *
++ *  Author:	cli <chen.li@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++
++#undef DEBUG
++/* #define VERBOSE_DEBUG */
++
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++#include <linux/irq.h>
++#include <linux/device.h>
++#include <linux/of.h>
++#include <linux/of_dma.h>
++#include <linux/dmapool.h>
++#include "ingenic_dma.h"
++
++#if defined(CONFIG_SOC_X2500) || defined(CONFIG_INGENIC_AIC_USES_PDMA)
++#define AIC_USES_PDMA
++#endif
++
++#ifdef CONFIG_SOC_X2500
++#include <soc/pdma.h>
++#endif
++
++#define JZCAN_RX_DATA_OFFSET	0x90
++
++/* tsz for 1,2,4,8,16,32,64 128bytes */
++const static char dcm_tsz[8] = { 1, 2, 0, 0, 3, 4, 5, 6};
++static inline unsigned int get_current_tsz(unsigned long dcmp)
++{
++	int i;
++	int val = (dcmp & DCM_TSZ_MSK) >> DCM_TSZ_SFT;
++
++	if (DCM_TSZ_AUTO == val)
++		return 0;
++
++	for (i = 0; i < ARRAY_SIZE(dcm_tsz); i++) {
++		if (val == dcm_tsz[i])
++			break;
++	}
++
++	return i;
++}
++
++static inline unsigned get_max_tsz(unsigned long val, unsigned int *shift)
++{
++	int ord = ffs(val) - 1;
++
++	/*
++	 * 8 byte transfer sizes unsupported so fall back on 4. If it's larger
++	 * than the maximum, just limit it. It is perfectly safe to fall back
++	 * in this way since we won't exceed the maximum burst size supported
++	 * by the device, the only effect is reduced efficiency. This is better
++	 * than refusing to perform the request at all.
++	 */
++	if (ord == 3)
++		ord = 2;
++	else if (ord > 7)
++		ord = 7;
++
++	if (shift)
++		*shift = ord;
++
++	return dcm_tsz[ord];
++}
++
++static const struct of_device_id ingenic_dma_dt_match[];
++static struct ingenic_dma_engine *ingenic_dma_parse_dt(struct platform_device *pdev)
++{
++	const struct of_device_id *match;
++	struct ingenic_dma_engine *ingenic_dma;
++	u32 nr_chs;
++
++	if (!pdev->dev.of_node)
++		return ERR_PTR(-ENODEV);
++
++	match = of_match_node(ingenic_dma_dt_match, pdev->dev.of_node);
++	if (!match)
++		return ERR_PTR(-ENODEV);
++
++	if (of_property_read_u32(pdev->dev.of_node, "#dma-channels", &nr_chs))
++		nr_chs = 32;
++
++	ingenic_dma = devm_kzalloc(&pdev->dev, sizeof(*ingenic_dma) +
++			sizeof(struct ingenic_dma_chan *) * nr_chs, GFP_KERNEL);
++	if (!ingenic_dma)
++		return ERR_PTR(-ENOMEM);
++
++	ingenic_dma->dev = &pdev->dev;
++	ingenic_dma->nr_chs = nr_chs;
++	ingenic_dma->hwattr = (unsigned int)match->data;
++
++	/* Property is optional, if it doesn't exist the value will remain 0. */
++	of_property_read_u32(pdev->dev.of_node, "ingenic,reserved-chs",
++			&ingenic_dma->chan_reserved);
++
++	if (!of_property_read_u32(pdev->dev.of_node, "ingenic,programed-chs",
++				&ingenic_dma->chan_programed))
++		ingenic_dma->chan_reserved |= ingenic_dma->chan_programed;
++
++	if (HWATTR_SPECIAL_CH01_SUP(ingenic_dma->hwattr) &&
++			of_property_read_bool(pdev->dev.of_node, "ingenic,special-chs")) {
++		ingenic_dma->chan_reserved |= DMA_SPECAIL_CHS;
++		ingenic_dma->chan_programed |= DMA_SPECAIL_CHS;
++		ingenic_dma->special_ch = true;
++	}
++
++	ingenic_dma->intc_ch = -1;
++	if (HWATTR_INTC_IRQ_SUP(ingenic_dma->hwattr) &&
++			!of_property_read_u32(pdev->dev.of_node, "ingenic,intc-ch",
++				(u32 *)&ingenic_dma->intc_ch)) {
++
++		if (ingenic_dma->intc_ch >= ingenic_dma->nr_chs)
++			ingenic_dma->intc_ch = (ingenic_dma->nr_chs - 1);
++
++		if (BIT(ingenic_dma->intc_ch) & ingenic_dma->chan_reserved)
++			dev_warn(ingenic_dma->dev, "WARN: intc irq channel %d is already reserved\n",
++					ingenic_dma->intc_ch);
++
++		ingenic_dma->chan_reserved |= BIT(ingenic_dma->intc_ch);
++	}
++	return ingenic_dma;
++}
++
++#define ALIGN_DOWN(addr, size)  ((addr)&(~((size)-1)))
++
++static int dump_dma_hdesc(struct hdma_desc * desc, const char * d)
++{
++	int i;
++	unsigned long *p;
++	printk(KERN_DEBUG "%s(): %s\n", __func__, d);
++	p = (unsigned long *)desc;
++	for (i=0;i<8;i++) {
++		printk(KERN_DEBUG "\t%08lx\n", (unsigned long)*p);
++		p++;
++	}
++
++	return 0;
++}
++
++static unsigned int build_one_desc(dma_addr_t saddr, dma_addr_t daddr,
++		unsigned int length, struct hdma_desc *desc)
++{
++	unsigned len = length;
++
++	if (length < DTC_TC_MSK) {
++		desc->dcm = DCM_DAI | DCM_SAI | \
++			    (DCM_TSZ_AUTO << DCM_TSZ_SFT) | (DCM_RDIL_MAX << DCM_RDIL_SFT);
++		desc->dtc = len; /* DCM_TSZ_AUTO in bytes */
++	} else {
++		unsigned int tsz, transfer_shift;
++		len = ALIGN_DOWN(len, sizeof(uint32_t));
++		tsz = get_max_tsz(len , &transfer_shift);
++		desc->dcm = DCM_DAI | DCM_SAI | tsz << DCM_TSZ_SFT;
++		desc->dtc = len >> transfer_shift; /* in burst unit */
++		barrier();
++		len = desc->dtc << transfer_shift;
++	}
++
++	desc->dsa = saddr;
++	desc->dta = daddr;
++	desc->sd = 0;
++	desc->drt = INGENIC_DMA_REQ_AUTO_TX;
++
++	return len;
++}
++
++static unsigned int build_one_slave_desc(struct ingenic_dma_chan *dmac, dma_addr_t addr,
++		unsigned int length,
++		enum dma_transfer_direction direction,
++		struct hdma_desc *desc)
++{
++	enum dma_transfer_direction dir;
++	unsigned int rdil;
++
++	desc->dcm = dmac->dcm;
++	desc->drt = dmac->slave_id;
++	desc->sd = 0;
++
++	if ((direction != DMA_DEV_TO_MEM) && (direction != DMA_MEM_TO_DEV))
++		dir = dmac->direction;
++	else
++		dir = direction;
++
++	if (dir == DMA_DEV_TO_MEM) {
++		desc->dta = addr;
++		desc->dsa = dmac->slave_addr;
++		desc->dcm |= DCM_DAI;
++	} else {
++		desc->dsa = addr;
++		desc->dta = dmac->slave_addr;
++		desc->dcm |= DCM_SAI;
++	}
++
++	rdil = dmac->maxburst * dmac->transfer_width;
++	if (rdil > 4)
++		rdil = min((int)fls(rdil) + 1, (int)DCM_RDIL_MAX);
++
++	WARN_ON(length & (~DTC_TC_MSK));
++	if (WARN_ON(!IS_ALIGNED(length, dmac->transfer_width))) {
++		desc->dtc = ALIGN_DOWN((length & DTC_TC_MSK), dmac->transfer_width);
++	} else {
++		desc->dtc = (length & DTC_TC_MSK);
++	}
++	desc->dcm |= DCM_TSZ_MSK | (rdil << DCM_RDIL_SFT);
++
++	return desc->dtc;
++}
++
++static void ingenic_dma_free_swdesc(struct virt_dma_desc *vd)
++{
++	struct ingenic_dma_sdesc *sdesc = to_ingenic_dma_sdesc(vd);
++	struct ingenic_dma_chan *dmac = sdesc->dmac;
++	unsigned long flags;
++	int i;
++
++	WARN_ON(!sdesc->dmac);
++
++	spin_lock_irqsave(&dmac->hdesc_lock, flags);
++	if (dmac->hdesc_pool) {
++		for (i = 0; i < sdesc->nb_desc; i++)
++			dma_pool_free(dmac->hdesc_pool, sdesc->hw_desc[i], sdesc->hw_desc_dma[i]);
++		dmac->hdesc_num -= sdesc->nb_desc;
++	}
++	spin_unlock_irqrestore(&dmac->hdesc_lock, flags);
++
++	kfree(sdesc);
++	return;
++}
++
++static struct ingenic_dma_sdesc *ingenic_dma_alloc_swdesc(struct ingenic_dma_chan *dmac, int num_hdesc)
++{
++	struct ingenic_dma_sdesc *sdesc;
++	int i;
++	unsigned long flags;
++
++	spin_lock_irqsave(&dmac->hdesc_lock, flags);
++	if (num_hdesc > (dmac->hdesc_max - dmac->hdesc_num) || !dmac->hdesc_pool) {
++		spin_unlock_irqrestore(&dmac->hdesc_lock, flags);
++		return NULL;
++	}
++
++	sdesc = (struct ingenic_dma_sdesc *)kzalloc(sizeof(struct ingenic_dma_sdesc) +
++			num_hdesc * (sizeof(void **) + sizeof(dma_addr_t)),
++			GFP_NOWAIT);
++	if (!sdesc) {
++		spin_unlock_irqrestore(&dmac->hdesc_lock, flags);
++		return NULL;
++	}
++
++	sdesc->hw_desc = (struct hdma_desc**)(sdesc + 1);
++	sdesc->hw_desc_dma = (dma_addr_t *)(sdesc->hw_desc + num_hdesc);
++	sdesc->dmac = dmac;
++
++	for (i = 0; i < num_hdesc; i++) {
++		sdesc->hw_desc[i] = dma_pool_alloc(dmac->hdesc_pool, GFP_NOWAIT, &sdesc->hw_desc_dma[i]);
++		pr_debug("sdesc->hw_desc[%d] = %p, sdesc->hw_desc_dma[%d] = 0x%08x\n",
++				i, sdesc->hw_desc[i],
++				i, sdesc->hw_desc_dma[i]);
++		if (!sdesc->hw_desc[i]) {
++			dev_err(&dmac->vc.chan.dev->device,
++					"%s(): Couldn't allocate the hw_desc from dma_pool %p\n",
++					__func__, dmac->hdesc_pool);
++			spin_unlock_irqrestore(&dmac->hdesc_lock, flags);
++			goto err;
++		}
++		sdesc->nb_desc++;
++	}
++	dmac->hdesc_num += sdesc->nb_desc;
++	spin_unlock_irqrestore(&dmac->hdesc_lock, flags);
++	return sdesc;
++err:
++	ingenic_dma_free_swdesc(&sdesc->vd);
++	return NULL;
++}
++
++#ifdef CONFIG_INGENIC_DMA_RECEIVE_DXTERNAL_DECIDE
++static void ingenic_dma_use_external_trigger(struct dma_chan *chan,
++		struct ingenic_dma_sdesc *sdesc, unsigned int desc_len)
++{
++	struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(chan);
++	int i;
++	unsigned long des_offset = 0;
++
++	for(i = 0; i < desc_len; i++) {
++		if(sdesc->hw_desc[i]->drt == INGENIC_DMA_REQ_CAN0_TX ||
++			sdesc->hw_desc[i]->drt == INGENIC_DMA_REQ_CAN1_TX) {
++			sdesc->hw_desc[i]->dcm = DCM_SAI | DCM_DAI;
++			des_offset = sdesc->hw_desc[i]->dtc & (~DTC_TC_MSK);
++			sdesc->hw_desc[i]->dtc = sdesc->hw_desc[i]->dtc - des_offset;
++			sdesc->hw_desc[i]->dtc /= 4;
++			sdesc->hw_desc[i]->dtc += des_offset;
++		} else if(sdesc->hw_desc[i]->drt == INGENIC_DMA_REQ_CAN0_RX ||
++			sdesc->hw_desc[i]->drt == INGENIC_DMA_REQ_CAN1_RX) {
++			des_offset = sdesc->hw_desc[i]->dtc & (~DTC_TC_MSK);
++			sdesc->hw_desc[i]->dtc = sdesc->hw_desc[i]->dtc - des_offset;
++			sdesc->hw_desc[i]->dtc /= 16;
++			sdesc->hw_desc[i]->dtc += des_offset;
++			sdesc->hw_desc[i]->dcm = DCM_DAI | DCM_SAIW | DCM_TSZ_EXTR;
++			writel(JZCAN_RX_DATA_OFFSET, dmac->engine->iomem + DSN0);
++		} else if ((sdesc->hw_desc[i]->drt == INGENIC_DMA_REQ_UART0_RX) ||
++					(sdesc->hw_desc[i]->drt == INGENIC_DMA_REQ_UART1_RX) ||
++					(sdesc->hw_desc[i]->drt == INGENIC_DMA_REQ_UART2_RX) ||
++					(sdesc->hw_desc[i]->drt == INGENIC_DMA_REQ_UART3_RX)) {
++			sdesc->hw_desc[i]->dcm &= ~DCM_RDIL_MSK;
++			sdesc->hw_desc[i]->dcm &= ~DCM_TSZ_MSK;
++			sdesc->hw_desc[i]->dcm |= DCM_DAI | DCM_TSZ_EXTR;
++		} else {
++			/* add other need external trigger controller*/
++		}
++
++		if (i) {
++			sdesc->hw_desc[i - 1]->dcm |= DCM_LINK;
++		}
++	}
++	sdesc->hw_desc[i - 1]->dcm |= DCM_TIE;
++}
++#endif
++
++static struct dma_async_tx_descriptor *ingenic_dma_prep_slave_sg(
++		struct dma_chan *chan, struct scatterlist *sgl,
++		unsigned int sg_len, enum dma_transfer_direction direction,
++		unsigned long flags, void *context)
++{
++	struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(chan);
++	struct ingenic_dma_sdesc *sdesc;
++	int i;
++
++	sdesc = ingenic_dma_alloc_swdesc(dmac, sg_len);
++	if (!sdesc)
++		return NULL;
++
++	for (i = 0; i < sg_len; i++) {
++		sdesc->len += build_one_slave_desc(dmac, sg_dma_address(&sgl[i]),
++				sg_dma_len(&sgl[i]), direction, sdesc->hw_desc[i]);
++		if (i) {
++			sdesc->hw_desc[i - 1]->dcm |= DCM_LINK;
++			sdesc->hw_desc[i - 1]->dtc |= PHY_TO_DESC_DOA(sdesc->hw_desc_dma[i]);
++		}
++	}
++	sdesc->hw_desc[i - 1]->dcm |= DCM_TIE;
++
++#ifdef CONFIG_INGENIC_DMA_RECEIVE_DXTERNAL_DECIDE
++	ingenic_dma_use_external_trigger(chan, sdesc, sg_len);
++#endif
++	/* use 8-word descriptors */
++	sdesc->dcs = DCS_DES8;
++
++	return vchan_tx_prep(&dmac->vc, &sdesc->vd, flags);
++}
++
++static struct dma_async_tx_descriptor *ingenic_dma_prep_dma_cyclic(
++		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
++		size_t period_len, enum dma_transfer_direction direction,
++		unsigned long flags)
++{
++	struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(chan);
++	unsigned int periods = buf_len / period_len;
++	struct ingenic_dma_sdesc *sdesc;
++	int i;
++
++	sdesc = ingenic_dma_alloc_swdesc(dmac, periods);
++	if (!sdesc)
++		return NULL;
++
++	for (i = 0; i < periods; i++) {
++		sdesc->len += build_one_slave_desc(dmac, buf_addr + (i * period_len),
++				period_len, direction, sdesc->hw_desc[i]);
++		if (i) {
++			sdesc->hw_desc[i - 1]->dcm |= DCM_LINK | DCM_TIE;
++			sdesc->hw_desc[i - 1]->dtc |= PHY_TO_DESC_DOA(sdesc->hw_desc_dma[i]);
++		}
++	}
++
++#ifdef CONFIG_INGENIC_DMA_RECEIVE_DXTERNAL_DECIDE
++	ingenic_dma_use_external_trigger(chan, sdesc, periods);
++#endif
++	/*make it cyclic*/
++	sdesc->hw_desc[i - 1]->dcm |= DCM_LINK | DCM_TIE;
++	sdesc->hw_desc[i - 1]->dtc |= PHY_TO_DESC_DOA(sdesc->hw_desc_dma[0]);
++	sdesc->cyclic = true;
++
++	/* use 8-word descriptors */
++	sdesc->dcs = DCS_DES8;
++
++	return vchan_tx_prep(&dmac->vc, &sdesc->vd, flags);
++}
++
++static struct dma_async_tx_descriptor *ingenic_dma_prep_dma_memcpy(struct dma_chan *chan,
++		dma_addr_t dma_dest,
++		dma_addr_t dma_src,
++		size_t len,
++		unsigned long flags)
++{
++	struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(chan);
++	struct ingenic_dma_sdesc *sdesc;
++
++	sdesc = ingenic_dma_alloc_swdesc(dmac, 1);
++	if (!sdesc)
++		return NULL;
++
++	sdesc->len = build_one_desc(dma_src, dma_dest, len, sdesc->hw_desc[0]);
++	sdesc->hw_desc[0]->dcm |= DCM_TIE;
++
++	/* use 8-word descriptors */
++	sdesc->dcs = DCS_DES8;
++
++	return vchan_tx_prep(&dmac->vc, &sdesc->vd, flags);
++}
++
++static int build_dma_sg_desc(struct ingenic_dma_sdesc *sdesc,
++		struct scatterlist *dst_sg, unsigned int dst_nents,
++		struct scatterlist *src_sg, unsigned int src_nents)
++{
++	int src_sg_avail = 0;
++	int dst_sg_avail = 0;
++	int size;
++	dma_addr_t src_addr;
++	dma_addr_t dst_addr;
++	int i = 0;
++
++	src_nents--;
++	dst_nents--;
++	dst_sg_avail = sg_dma_len(src_sg);
++	src_sg_avail = sg_dma_len(dst_sg);
++	while (true) {
++		src_addr = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_sg_avail;
++		dst_addr = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_sg_avail;
++
++		size = min(src_sg_avail, dst_sg_avail);
++		size = min(size, (DTC_TC_MSK & (~0x3)));
++
++		if (NULL != sdesc) {
++			sdesc->len += build_one_desc(src_addr, dst_addr, size, sdesc->hw_desc[i]);
++			if (i) {
++				sdesc->hw_desc[i - 1]->dcm |= DCM_LINK;
++				sdesc->hw_desc[i - 1]->dtc |= PHY_TO_DESC_DOA(sdesc->hw_desc_dma[i]);
++			}
++		}
++
++		dst_sg_avail -= size;
++		src_sg_avail -= size;
++
++		if (0 == src_sg_avail) {
++			if (0 == src_nents)
++				break;
++			src_sg = sg_next(src_sg);
++			src_sg_avail = sg_dma_len(src_sg);
++			src_nents--;
++		}
++
++		if (0 == dst_sg_avail) {
++			if (0 == dst_nents)
++				break;
++			dst_sg = sg_next(dst_sg);
++			dst_sg_avail = sg_dma_len(dst_sg);
++			dst_nents--;
++		}
++		i++;
++	}
++	if (sdesc)
++		sdesc->hw_desc[i]->dcm |= DCM_TIE;
++	return ++i;
++}
++
++static struct dma_async_tx_descriptor* ingenic_dma_prep_dma_sg(
++		struct dma_chan *chan,
++		struct scatterlist *dst_sg, unsigned int dst_nents,
++		struct scatterlist *src_sg, unsigned int src_nents,
++		unsigned long flags)
++{
++	struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(chan);
++	struct ingenic_dma_sdesc *sdesc;
++	int hw_nums;
++
++	if (0 == dst_nents || 0 == src_nents)
++		return NULL;
++
++	if (NULL == dst_sg || NULL == src_sg)
++		return NULL;
++
++	hw_nums = build_dma_sg_desc(NULL, dst_sg, dst_nents, src_sg, src_nents);
++
++	sdesc = ingenic_dma_alloc_swdesc(dmac, hw_nums);
++	if (!sdesc)
++		return NULL;
++
++	build_dma_sg_desc(sdesc, dst_sg, dst_nents, src_sg, src_nents);
++
++	/* use 8-word descriptors */
++	sdesc->dcs = DCS_DES8;
++
++	return vchan_tx_prep(&dmac->vc, &sdesc->vd, flags);
++}
++
++static size_t ingenic_dma_desc_residue(struct ingenic_dma_chan *dmac, struct ingenic_dma_sdesc *sdesc)
++{
++	unsigned int residue = 0, shift, pass = 0;
++	unsigned int i;
++	bool dsa = false;
++	dma_addr_t start, end, compare;
++
++	if (sdesc->hw_desc[0]->dcm & DCM_SAI) {
++		compare = readl(dmac->iomem + CH_DSA);
++		dsa = true;
++	} else {
++		compare = readl(dmac->iomem + CH_DTA);
++	}
++
++	for (i = 0; i < sdesc->nb_desc; i++) {
++		start = dsa ? sdesc->hw_desc[i]->dsa : sdesc->hw_desc[i]->dta;
++		shift = get_current_tsz(sdesc->hw_desc[i]->dcm);
++		end = start + (sdesc->hw_desc[i]->dtc << shift);
++		if (start <= compare && end > compare) {
++			pass += (compare - start);
++			break;
++		} else {
++			pass += sdesc->hw_desc[i]->dtc << shift;
++		}
++	}
++
++	residue = sdesc->len - pass;
++	return residue;
++}
++
++static enum dma_status ingenic_dma_tx_status(struct dma_chan *chan,
++		dma_cookie_t cookie,
++		struct dma_tx_state *txstate)
++{
++	struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(chan);
++	struct virt_dma_desc *vd;
++	enum dma_status status;
++	unsigned long flags;
++
++	status = dma_cookie_status(chan, cookie, txstate);
++	if ((status == DMA_COMPLETE) || (txstate == NULL))
++		return status;
++
++	spin_lock_irqsave(&dmac->vc.lock, flags);
++
++	vd = vchan_find_desc(&dmac->vc, cookie);
++	if (vd) {
++		dma_set_residue(txstate, to_ingenic_dma_sdesc(vd)->len);
++	} else if (dmac->sdesc && cookie == dmac->sdesc->vd.tx.cookie) {
++		dma_set_residue(txstate, ingenic_dma_desc_residue(dmac, dmac->sdesc));
++	} else
++		dma_set_residue(txstate, 0);
++
++	spin_unlock_irqrestore(&dmac->vc.lock, flags);
++	return status;
++}
++
++static void ingenic_dma_start_trans(struct ingenic_dma_chan *dmac)
++{
++	static struct virt_dma_desc *vd = NULL;
++	struct ingenic_dma_sdesc *sdesc;
++	int i;
++
++	if (!dmac->sdesc) {
++		vd = vchan_next_desc(&dmac->vc);
++		if (!vd)
++			return;
++
++		list_del(&vd->node);
++
++		sdesc = dmac->sdesc = to_ingenic_dma_sdesc(vd);
++
++		if (dmac->fake_cyclic && sdesc->cyclic && vd->tx.callback) {
++			/*
++			 * The DMA controller doesn't support triggering an interrupt
++			 * after processing each descriptor, only after processing an
++			 * entire terminated list of descriptors.For a cyclic DMA
++			 * setup the list of descriptors is not terminated so we can
++			 * never get an interrupt.
++			 *
++			 * If the user requested a callback for a cyclic DMA setup then
++			 * we workaround this hardware limitation here by degrading to
++			 * a set of unlinked descriptors which we will submit in
++			 * sequence in response to the completion of processing the
++			 * previous descriptor
++			 */
++			for (i = 0; i < sdesc->nb_desc; i++) {
++				sdesc->hw_desc[i]->dcm &= ~DCM_LINK;
++			}
++		}
++
++		for (i = 0; i < sdesc->nb_desc; i++) {
++			int j;
++			uint32_t *vaddr = (void *)sdesc->hw_desc[i];
++			for (j = 0; j < 8; j++) {
++				pr_debug("<%d>: &vaddr[0] %p vaddr[0] %x\n",i, &vaddr[j], vaddr[j]);
++			}
++			pr_debug("sdesc->hw_desc_dma[0] 0x%08x dmac->iomem %p\n", sdesc->hw_desc_dma[i], dmac->iomem);
++		}
++
++		sdesc->curr_desc = 0;
++		sdesc->status = STAT_RUNNING;
++	} else {
++		sdesc = dmac->sdesc;
++		WARN_ON_ONCE((!sdesc->cyclic));
++		WARN_ON_ONCE((!vd->tx.callback));
++		WARN_ON_ONCE((!dmac->fake_cyclic));
++		sdesc->status = STAT_RUNNING;
++		sdesc->curr_desc++;
++		sdesc->curr_desc = sdesc->curr_desc % sdesc->nb_desc;
++	}
++
++	/* dump_dma_hdesc(sdesc->hw_desc[sdesc->curr_desc], __func__); */
++	/* dma descriptor address */
++	writel(sdesc->hw_desc_dma[sdesc->curr_desc], dmac->iomem + CH_DDA);
++	/* initiate descriptor fetch */
++	writel(BIT(dmac->id), dmac->engine->iomem + DDRS);
++	/* transfer start */
++	dev_dbg(chan2dev(&dmac->vc.chan), "dcs:%x start transfer\n",
++			readl(dmac->iomem + CH_DCS));
++
++	writel(sdesc->dcs | DCS_CTE, dmac->iomem + CH_DCS);
++	return;
++}
++
++static void ingenic_dma_issue_pending(struct dma_chan *chan)
++{
++	struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(chan);
++	unsigned long flags;
++
++	spin_lock_irqsave(&dmac->vc.lock, flags);
++
++	if (vchan_issue_pending(&dmac->vc) && !dmac->sdesc)
++		ingenic_dma_start_trans(dmac);
++
++	spin_unlock_irqrestore(&dmac->vc.lock, flags);
++}
++
++#ifdef AIC_USES_PDMA
++/*
++ *	get dma current transfer address
++ */
++static dma_addr_t jzdma_get_current_trans_addr(struct dma_chan *chan,
++					       dma_addr_t * dst_addr,
++					       dma_addr_t * src_addr,
++					       enum dma_transfer_direction
++					       direction)
++{
++	struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(chan);
++	dma_addr_t ret_val = 0;
++
++	if(!dmac->sdesc)
++		return 0;
++	if (dmac->sdesc->status == STAT_STOPPED)
++		return 0;
++
++	if (direction ==  DMA_MEM_TO_DEV) {
++		ret_val	= readl(dmac->iomem + CH_DSA);
++		if (src_addr)
++			*src_addr = ret_val;
++		if (dst_addr)
++			*dst_addr = readl(dmac->iomem + CH_DTA);
++	} else if (direction == DMA_DEV_TO_MEM) {
++		ret_val = readl(dmac->iomem + CH_DTA);
++		if (dst_addr)
++			*dst_addr = ret_val;
++		if (src_addr)
++			*src_addr = readl(dmac->iomem + CH_DSA);
++	} else if (direction == DMA_MEM_TO_MEM) {
++		if (dst_addr)
++			*dst_addr = readl(dmac->iomem + CH_DTA);
++		if (src_addr)
++			*src_addr = readl(dmac->iomem + CH_DSA);
++	}
++
++	return ret_val;
++}
++#endif
++
++static int ingenic_dma_terminate_all(struct dma_chan *chan)
++{
++	struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(chan);
++	unsigned long flags;
++	int ret = 0;
++	LIST_HEAD(head);
++
++	spin_lock_irqsave(&dmac->vc.lock, flags);
++#ifdef AIC_USES_PDMA
++	/* the part handler audio driver */
++	if(dmac->slave_id == INGENIC_DMA_REQ_AIC_LOOP_RX || dmac->slave_id == INGENIC_DMA_REQ_AIC_TX || dmac->slave_id == INGENIC_DMA_REQ_ASOC_AIC_RX
++	|| dmac->slave_id == INGENIC_DMA_REQ_ASOC_AIC_TX || dmac->slave_id == INGENIC_DMA_REQ_AIC_F_RX || dmac->slave_id == INGENIC_DMA_REQ_DMIC_RX)
++	{
++		if (dmac->sdesc) {	/*DMA transfer is running*/
++			if (dmac->sdesc->status != STAT_STOPPED) {
++				dmac->sdesc->status = STAT_STOPPED;
++				writel(0, dmac->iomem + CH_DCS);
++			}
++			ingenic_dma_free_swdesc(&dmac->sdesc->vd);
++			dmac->sdesc = NULL;
++		}
++
++//    	printk("%s[%d]: pdma%d\n",__func__,__LINE__,dmac->slave_id);
++		goto done;
++	}
++#endif
++	if (dmac->sdesc) {	/*DMA transfer is running*/
++		int i;
++		ret = -EBUSY;
++		if (dmac->sdesc->status != STAT_STOPPED) {
++			dmac->sdesc->status = STAT_STOPPED;
++			reinit_completion(&dmac->completion);
++
++			for (i = 0; i < dmac->sdesc->nb_desc; i++) {
++				dmac->sdesc->hw_desc[i]->dcm |= DCM_TIE;
++				dmac->sdesc->hw_desc[i]->dcm &= ~DCM_LINK;
++			}
++
++			if (HWATTR_DESC_INTER_SUP(dmac->engine->hwattr)) {
++				/*
++				 * The version of controller support descriptor interrupt
++				 * can clear LINK on runtime
++				 */
++				unsigned int dcm = readl(dmac->iomem + CH_DCM);
++				if (dcm & DCM_LINK) {
++					dcm &= ~DCM_LINK;
++					writel(dcm, dmac->iomem + CH_DCM);
++				}
++			}
++		} else if (readl(dmac->iomem + CH_DRT) != INGENIC_DMA_REQ_AUTO_TX) {
++			writel(0, dmac->iomem + CH_DCS);
++			ingenic_dma_free_swdesc(&dmac->sdesc->vd);
++			dmac->sdesc = NULL;
++			complete(&dmac->completion);
++			ret = 0; /*DMA transfer force stop !!!!!*/
++		}
++	} else {	/*DMA transfer already stoped*/
++		writel(0, dmac->iomem + CH_DCS);
++	}
++done:
++	vchan_get_all_descriptors(&dmac->vc, &head);
++
++	spin_unlock_irqrestore(&dmac->vc.lock, flags);
++
++	vchan_dma_desc_free_list(&dmac->vc, &head);
++
++	return ret;
++}
++
++static int ingenic_dma_wait_terminate_complete(struct dma_chan *chan)
++{
++	struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(chan);
++
++	if (dmac->sdesc)
++		wait_for_completion(&dmac->completion);
++	return 0;
++}
++
++static int ingenic_dma_config(struct dma_chan *chan, struct dma_slave_config *config)
++{
++	struct ingenic_dma_chan* dmac = to_ingenic_dma_chan(chan);
++	enum dma_slave_buswidth transfer_width;
++
++	if (!config)
++		return -EINVAL;
++
++	switch (config->direction) {
++	case DMA_MEM_TO_DEV:
++		if (!config->dst_addr_width || !config->dst_addr)
++			return -EINVAL;
++		if (!config->dst_maxburst)
++			config->dst_maxburst = 1;
++		transfer_width = config->dst_addr_width;
++		dmac->slave_addr = config->dst_addr;
++		dmac->maxburst = config->dst_maxburst;
++		break;
++	case DMA_DEV_TO_MEM:
++		if (!config->src_addr_width || !config->src_addr)
++			return -EINVAL;
++		if (!config->src_maxburst)
++			config->src_maxburst = 1;
++		transfer_width = config->src_addr_width;
++		dmac->slave_addr = config->src_addr;
++		dmac->maxburst = config->src_maxburst;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	switch (transfer_width) {
++	case DMA_SLAVE_BUSWIDTH_1_BYTE:
++		dmac->dcm = DCM_PORT_8;
++		dmac->transfer_width = 1;
++		break;
++	case DMA_SLAVE_BUSWIDTH_2_BYTES:
++		dmac->dcm = DCM_PORT_16;
++		dmac->transfer_width = 2;
++		break;
++	case DMA_SLAVE_BUSWIDTH_4_BYTES:
++		dmac->dcm = DCM_PORT_32;
++		dmac->transfer_width = 4;
++		break;
++	default:
++		return -EINVAL;
++	}
++#ifndef CONFIG_SOC_X2500
++	if (config->slave_id & INGENIC_DMA_TYPE_REQ_MSK)
++		dmac->slave_id = config->slave_id & INGENIC_DMA_TYPE_REQ_MSK;
++#endif
++	return 0;
++}
++
++static void pdma_handle_chan_irq(struct ingenic_dma_engine *ingenic_dma, int ch_id)
++{
++	struct ingenic_dma_chan *dmac = ingenic_dma->chan[ch_id];
++	struct ingenic_dma_sdesc *sdesc;
++	unsigned int dcs;
++
++	spin_lock(&dmac->vc.lock);
++
++	dcs = readl(dmac->iomem + CH_DCS);
++	writel(0, dmac->iomem + CH_DCS);
++
++	if (dcs & DCS_AR)
++		dev_warn(&dmac->vc.chan.dev->device,
++				"address error (DCS=0x%x)\n", dcs);
++
++	if (dcs & DCS_HLT)
++		dev_warn(&dmac->vc.chan.dev->device,
++				"channel halt (DCS=0x%x)\n", dcs);
++	sdesc = dmac->sdesc;
++	if (sdesc) {
++		if (sdesc->status == STAT_STOPPED) {
++			dma_cookie_complete(&sdesc->vd.tx);
++			dmac->sdesc = NULL;
++			ingenic_dma_free_swdesc(&sdesc->vd);
++			complete(&dmac->completion);
++		} else if (dmac->fake_cyclic && sdesc->cyclic) {
++			vchan_cyclic_callback(&sdesc->vd);
++		} else {
++			vchan_cookie_complete(&sdesc->vd);
++			dmac->sdesc = NULL;
++		}
++		ingenic_dma_start_trans(dmac);
++	} else {
++		dev_warn(&dmac->vc.chan.dev->device,
++			"channel irq with no active transfer, channel stop\n");
++	}
++
++	spin_unlock(&dmac->vc.lock);
++}
++
++static irqreturn_t pdma_int_handler(int irq, void *dev)
++{
++	struct ingenic_dma_engine *ingenic_dma = (struct ingenic_dma_engine *)dev;
++	unsigned long pending, dmac;
++	int i;
++
++	pending = readl(ingenic_dma->iomem + DIRQP);
++	writel(~pending, ingenic_dma->iomem + DIRQP);
++
++	for (i = 0; i < ingenic_dma->nr_chs ; i++) {
++		if (!(pending & (1 << i)))
++			continue;
++		pdma_handle_chan_irq(ingenic_dma, i);
++	}
++
++	dmac = readl(ingenic_dma->iomem + DMAC);
++	dmac &= ~(DMAC_HLT | DMAC_AR);
++	writel(dmac, ingenic_dma->iomem + DMAC);
++	return IRQ_HANDLED;
++}
++
++static irqreturn_t pdmam_int_handler(int irq, void *dev)
++{
++	/*TODO*/
++	return IRQ_HANDLED;
++}
++
++static irqreturn_t pdmad_int_handler(int irq, void *dev)
++{
++	struct ingenic_dma_engine *ingenic_dma = (struct ingenic_dma_engine *)dev;
++	unsigned long pending;
++	int i;
++
++	pending = readl(ingenic_dma->iomem + DIP);
++	writel(readl(ingenic_dma->iomem + DIP) & (~pending), ingenic_dma->iomem + DIC);
++
++	for (i = 0; i < ingenic_dma->nr_chs; i++) {
++		struct ingenic_dma_chan *dmac = ingenic_dma->chan[i];
++		struct ingenic_dma_sdesc *sdesc;
++
++		if (!(pending & (1 << i)))
++			continue;
++		sdesc = dmac->sdesc;
++		if (sdesc && sdesc->cyclic) {
++			spin_lock(&dmac->vc.lock);
++			vchan_cyclic_callback(&sdesc->vd);
++			spin_unlock(&dmac->vc.lock);
++		}
++	}
++	return IRQ_HANDLED;
++
++}
++
++static int ingenic_dma_alloc_chan_resources(struct dma_chan *chan)
++{
++	struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(chan);
++
++	dmac->hdesc_pool = dma_pool_create(dev_name(&chan->dev->device),
++			chan->device->dev,
++			sizeof(struct hdma_desc),
++			0, PAGE_SIZE);
++	if (!dmac->hdesc_pool) {
++		dev_err(&chan->dev->device,
++				"failed to allocate descriptor pool\n");
++		return -ENOMEM;
++	}
++	dmac->hdesc_max = PAGE_SIZE / sizeof(struct hdma_desc);
++	dmac->hdesc_num = 0;
++	return 0;
++}
++
++static void ingenic_dma_free_chan_resources(struct dma_chan *chan)
++{
++	struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(chan);
++	unsigned long flags;
++
++	ingenic_dma_terminate_all(chan);
++
++	ingenic_dma_wait_terminate_complete(chan);
++
++	spin_lock_irqsave(&dmac->hdesc_lock, flags);
++	dma_pool_destroy(dmac->hdesc_pool);
++	dmac->hdesc_pool = NULL;
++	dmac->hdesc_max = 0;
++	dmac->hdesc_num = 0;
++	spin_unlock_irqrestore(&dmac->hdesc_lock, flags);
++}
++
++static bool ingenic_dma_filter_fn(struct dma_chan *chan, void *param)
++{
++	struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(chan);
++	unsigned int private  = *(unsigned int *)param;
++	int channel = -1;
++
++	if (private & INGENIC_DMA_TYPE_CH_EN) {
++		channel = (private & INGENIC_DMA_TYPE_CH_MSK) >> INGENIC_DMA_TYPE_CH_SFT;
++		if (dmac->id == channel)
++			return true;
++		return false;
++	}
++
++	if (dmac->engine->chan_reserved & BIT(dmac->id))
++		return false;
++
++	dmac->slave_id = private & INGENIC_DMA_TYPE_REQ_MSK;
++	return true;
++}
++
++static struct of_dma_filter_info of_ingenic_dma_info = {
++	.filter_fn = ingenic_dma_filter_fn,
++};
++
++static int ingenic_dma_chan_init(struct ingenic_dma_engine *dma, int id)
++{
++	struct ingenic_dma_chan *dmac = NULL;
++
++	dmac = devm_kzalloc(dma->dev, sizeof(*dmac), GFP_KERNEL);
++	if (!dmac)
++		return -ENOMEM;
++	dmac->id = id;
++	dmac->iomem = dma->iomem + dmac->id * DMACH_OFF;
++	dmac->engine = dma;
++	dmac->fake_cyclic = HWATTR_DESC_INTER_SUP(dma->hwattr) ? false : true;
++	spin_lock_init(&dmac->hdesc_lock);
++	init_completion(&dmac->completion);
++
++	vchan_init(&dmac->vc, &dma->dma_device);
++
++	dmac->vc.desc_free = ingenic_dma_free_swdesc;
++#ifdef CONFIG_SOC_X2500
++	dmac->vc.chan.private = (void*)pdma_maps[id];
++	dmac->slave_id = pdma_maps[id] & INGENIC_DMA_TYPE_REQ_MSK;
++#endif
++	dma->chan[id] = dmac;
++	return 0;
++}
++
++static int __init ingenic_dma_probe(struct platform_device *pdev)
++{
++	struct ingenic_dma_engine *dma = NULL;
++	struct resource *iores;
++	u32 reg_dmac = DMAC_DMAE;
++	int i, ret = 0;
++
++	/* check of first. if of failed, use platform */
++	dma = ingenic_dma_parse_dt(pdev);
++	if (IS_ERR(dma))
++		return PTR_ERR(dma);
++
++	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	dma->iomem = devm_ioremap_resource(&pdev->dev, iores);
++	if (IS_ERR(dma->iomem))
++		return PTR_ERR(dma->iomem);
++
++	/* PDMA interrupt*/
++	dma->irq_pdma = platform_get_irq_byname(pdev, "pdma");
++	if (dma->irq_pdma < 0)
++		return dma->irq_pdma;
++	ret = devm_request_irq(&pdev->dev, dma->irq_pdma, pdma_int_handler,
++			0, "pdma", dma);
++	if (ret)
++		return ret;
++
++	/* PDMA mcu interrupt*/
++	dma->irq_pdmam = platform_get_irq_byname(pdev, "pdmam");
++	if (dma->irq_pdmam >= 0) {
++		ret = devm_request_irq(&pdev->dev, dma->irq_pdmam, pdmam_int_handler,
++				0, "pdmam", dma);
++		if (ret)
++			return ret;
++	}
++
++	/* PDMA descriptor interrupt */
++	if (HWATTR_DESC_INTER_SUP(dma->hwattr)) {
++		dma->irq_pdmad = platform_get_irq_byname(pdev, "pdmad");
++		if (dma->irq_pdmad < 0)
++			return dma->irq_pdmad;
++		ret = devm_request_irq(&pdev->dev, dma->irq_pdmad, pdmad_int_handler,
++				0, "pdmad", dma);
++		if (ret)
++			return ret;
++		irq_set_irq_wake(dma->irq_pdmad, 1);
++	}
++
++	/* Initialize dma engine */
++	INIT_LIST_HEAD(&dma->dma_device.channels);
++	for (i = 0; i < dma->nr_chs; i++ ) {
++		/*reserved one channel for intc interrupt*/
++		if (dma->intc_ch == i)
++			continue;
++		ingenic_dma_chan_init(dma, i);
++	}
++	dma_cap_set(DMA_MEMCPY, dma->dma_device.cap_mask);
++	dma_cap_set(DMA_SLAVE, dma->dma_device.cap_mask);
++	dma_cap_set(DMA_CYCLIC, dma->dma_device.cap_mask);
++
++	dma->dma_device.dev = &pdev->dev;
++	dma->dma_device.device_alloc_chan_resources = ingenic_dma_alloc_chan_resources;
++	dma->dma_device.device_free_chan_resources = ingenic_dma_free_chan_resources;
++	dma->dma_device.device_tx_status = ingenic_dma_tx_status;
++	dma->dma_device.device_prep_slave_sg = ingenic_dma_prep_slave_sg;
++	dma->dma_device.device_prep_dma_cyclic = ingenic_dma_prep_dma_cyclic;
++	dma->dma_device.device_prep_dma_memcpy = ingenic_dma_prep_dma_memcpy;
++	dma->dma_device.device_config = ingenic_dma_config;
++	dma->dma_device.device_terminate_all = ingenic_dma_terminate_all;
++	dma->dma_device.device_issue_pending = ingenic_dma_issue_pending;
++	dma->dma_device.copy_align = DMAENGINE_ALIGN_4_BYTES;
++	dma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES)
++		| BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
++	dma->dma_device.dst_addr_widths = dma->dma_device.src_addr_widths;
++	dma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | BIT(DMA_MEM_TO_MEM);
++	dma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
++	dma->dma_device.dev->dma_parms = &dma->dma_parms;
++	dma_set_max_seg_size(dma->dma_device.dev, DTC_TC_MSK);	/*At least*/
++
++#ifdef AIC_USES_PDMA
++	dma->dma_device.get_current_trans_addr = jzdma_get_current_trans_addr;
++#endif
++
++	dma->gate_clk = devm_clk_get(&pdev->dev, "gate_pdma");
++	if (IS_ERR(dma->gate_clk))
++		return PTR_ERR(dma->gate_clk);
++
++	ret = dma_async_device_register(&dma->dma_device);
++	if (ret) {
++		dev_err(&pdev->dev, "unable to register\n");
++		clk_disable(dma->gate_clk);
++		return ret;
++	}
++
++	of_ingenic_dma_info.dma_cap = dma->dma_device.cap_mask;
++	ret = of_dma_controller_register(pdev->dev.of_node,
++			of_dma_simple_xlate, &of_ingenic_dma_info);
++	if (ret) {
++		dev_err(&pdev->dev, "unable to register dma to device tree\n");
++		dma_async_device_unregister(&dma->dma_device);
++		clk_disable(dma->gate_clk);
++		return ret;
++	}
++	platform_set_drvdata(pdev, dma);
++
++	/*enable pdma controller*/
++	clk_prepare_enable(dma->gate_clk);
++
++	if (dma->chan_programed)
++		writel(dma->chan_programed, dma->iomem + DMACP);
++	if (dma->intc_ch >= 0)
++		reg_dmac |= DMAC_INTCE | ((dma->intc_ch << DMAC_INTCC_SFT) & DMAC_INTCC_MSK);
++	if (dma->special_ch)
++		reg_dmac |= DMAC_CH01;
++	writel(reg_dmac, dma->iomem + DMAC);
++	dev_info(dma->dev, "INGENIC SoC DMA initialized\n");
++	return 0;
++}
++
++static int ingenic_dma_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	struct ingenic_dma_engine *ingenic_dma = platform_get_drvdata(pdev);
++	struct dma_chan *chan;
++
++	list_for_each_entry(chan, &ingenic_dma->dma_device.channels, device_node) {
++		struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(chan);
++		struct ingenic_dma_sdesc *sdesc = dmac->sdesc;
++
++		if (sdesc && (sdesc->hw_desc[0]->drt != INGENIC_DMA_REQ_UART0_RX) &&
++				(sdesc->hw_desc[0]->drt != INGENIC_DMA_REQ_UART1_RX) &&
++				(sdesc->hw_desc[0]->drt != INGENIC_DMA_REQ_UART2_RX) &&
++				(sdesc->hw_desc[0]->drt != INGENIC_DMA_REQ_UART3_RX) &&
++				(sdesc->hw_desc[0]->drt != INGENIC_DMA_REQ_CAN0_RX) &&
++				(sdesc->hw_desc[0]->drt != INGENIC_DMA_REQ_CAN1_RX)) {
++			return -EBUSY;
++		}
++	}
++	clk_disable_unprepare(ingenic_dma->gate_clk);
++	return 0;
++}
++
++static int ingenic_dma_resume(struct platform_device * pdev)
++{
++	struct ingenic_dma_engine *ingenic_dma = platform_get_drvdata(pdev);
++	clk_prepare_enable(ingenic_dma->gate_clk);
++	return 0;
++}
++
++static const struct of_device_id ingenic_dma_dt_match[] = {
++	{ .compatible = "ingenic,m200-pdma", .data = (void *)(HWATTR_SPECIAL_CH01|HWATTR_INTC_IRQ)},
++	{ .compatible = "ingenic,x1000-pdma", .data = (void *)HWATTR_DESC_INTER},
++	{ .compatible = "ingenic,x1021-pdma", .data = (void *)HWATTR_DESC_INTER},
++	{ .compatible = "ingenic,x1520-pdma", .data = (void *)HWATTR_DESC_INTER},
++	{ .compatible = "ingenic,x1630-pdma", .data = (void *)HWATTR_DESC_INTER},
++	{ .compatible = "ingenic,x2000-pdma", .data = (void *)HWATTR_DESC_INTER},
++	{ .compatible = "ingenic,x2500-pdma", .data = (void *)HWATTR_INTC_IRQ},
++	{ .compatible = "ingenic,m300-pdma", .data = (void *)HWATTR_DESC_INTER},
++	{ .compatible = "ingenic,x1600-pdma", .data = (void *)HWATTR_DESC_INTER},
++	{},
++};
++MODULE_DEVICE_TABLE(of, ingenic_dma_dt_match);
++
++static struct platform_driver ingenic_dma_driver = {
++	.driver = {
++		.name = "ingenic-dma",
++		.owner  = THIS_MODULE,
++		.of_match_table = of_match_ptr(ingenic_dma_dt_match),
++	},
++	.suspend = ingenic_dma_suspend,
++	.resume = ingenic_dma_resume,
++};
++
++static int __init ingenic_dma_module_init(void)
++{
++	return platform_driver_probe(&ingenic_dma_driver, ingenic_dma_probe);
++}
++subsys_initcall(ingenic_dma_module_init);
++MODULE_AUTHOR("Chen.li <chen.li@ingenic.cn>");
++MODULE_DESCRIPTION("Ingenic dma driver");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/dma/ingenic/ingenic_dma.h b/module_drivers/drivers/dma/ingenic/ingenic_dma.h
+new file mode 100644
+index 000000000..56c66f74f
+--- /dev/null
++++ b/module_drivers/drivers/dma/ingenic/ingenic_dma.h
+@@ -0,0 +1,253 @@
++/*
++ * Copyright (C) 2016 Ingenic Semiconductor Co., Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++
++
++#ifndef __INGENIC_DMA_H__
++#define __INGENIC_DMA_H__
++#include <dt-bindings/dma/ingenic-pdma.h>
++#include "virt-dma.h"
++#include "dmaengine.h"
++#define CH_DSA	0x00
++#define CH_DTA	0x04
++#define CH_DTC	0x08
++#define CH_DRT	0x0C
++#define CH_DCS	0x10
++#define CH_DCM	0x14
++#define CH_DDA	0x18
++#define CH_DSD	0x1C
++
++#define TCSM	0x2000
++
++#define DMAC	0x1000
++#define DIRQP	0x1004
++#define DDR	0x1008
++#define DDRS	0x100C
++#define DIP	0x1010
++#define DIC	0x1014
++#define DMACP	0x101C
++#define DSIRQP	0x1020
++#define DSIRQM	0x1024
++#define DCIRQP	0x1028
++#define DCIRQM	0x102C
++#define DSN0    0x1060
++#define DSN1    0x1064
++#define DSCIDX0 0x1068
++#define DSCIDX1 0x106C
++
++#define DMACH_OFF	0x20
++/* DCS */
++#define DCS_NDES	BIT(31)
++#define DCS_DES8	BIT(30)
++#define DCS_CDOA_SFT	8
++#define DCS_CDOA_MSK	(0xff << DCS_CDOA_SFT)
++#define DCS_AR		BIT(4)
++#define DCS_TT		BIT(3)
++#define DCS_HLT		BIT(2)
++#define DCS_CTE		BIT(0)
++
++/* DTC */
++#define DTC_TC_SFT	0
++#define DTC_TC_MSK	0xffffff
++
++/* DCM */
++#define DCM_SAI		BIT(23)
++#define DCM_DAI		BIT(22)
++#define DCM_SAIW        BIT(21)
++#define DCM_DAIW        BIT(20)
++#define DCM_PORT_MSK	(0xf << 12)
++#define DCM_PORT_8	(0x1 << 14 | 0x1 <<12)
++#define DCM_PORT_16	(0x2 << 14 | 0x2 <<12)
++#define DCM_PORT_32	(0x0 << 14 | 0x0 <<12)
++#define DCM_RDIL_SFT	16
++#define DCM_RDIL_MAX	0x9
++#define DCM_RDIL_MSK	(0xf << DCM_RDIL_SFT)
++#define DCM_TSZ_SFT	8
++#define DCM_TSZ_AUTO	0x7
++#define DCM_TSZ_MSK	(0x7 << DCM_TSZ_SFT)
++#define DCM_TSZ_EXTR    (0x8 << DCM_TSZ_SFT)
++#define DCM_STDE	BIT(2)
++#define DCM_TIE		BIT(1)
++#define DCM_LINK	BIT(0)
++
++/* DDA */
++#define DDA_DBA_SFT	12
++#define DDA_DBA_MSK	(0xfffff << DDA_DBA_SFT)
++#define DDA_DOA_SFT	4
++#define DDA_DOA_MSK	(0xff << DDA_DOA_SFT)
++#define PHY_TO_DESC_DOA(dma)	 ((((dma) & DDA_DOA_MSK) >> DDA_DOA_SFT) << 24)
++
++/* DSD */
++#define DSD_TSD_SFT	16
++#define DSD_TSD_MSK	(0xffff << DSD_TSD_SFT)
++#define DSD_SSD_SFT	0
++#define DSD_SSD_MSK	(0xffff << DSD_SSD_SFT)
++
++/* DMAC */
++#define DMAC_FMSC	BIT(31)
++#define DMAC_FSSI	BIT(30)
++#define DMAC_FTSSI	BIT(29)
++#define DMAC_FUART	BIT(28)
++#define DMAC_FAIC	BIT(27)
++#define DMAC_INTCC_SFT	17
++#define DMAC_INTCC_MSK	(0x1f << 17)
++#define DMAC_INTCE	BIT(16)
++#define DMAC_HLT	BIT(3)
++#define DMAC_AR		BIT(2)
++#define DMAC_CH01	BIT(1)
++#define DMAC_DMAE	BIT(0)
++
++/* MCU of PDMA */
++#define DMCS	0x1030
++#define DMNMB	0x1034
++#define DMSMB	0x1038
++#define DMINT	0x103C
++
++/* MCU of PDMA */
++#define DMINT_S_IP      BIT(17)
++#define DMINT_N_IP      BIT(16)
++
++#define DMA_SPECAIL_CHS	0x3		/*Channel 0 & 1*/
++
++
++/*8-word hardware dma descriptor*/
++struct hdma_desc {
++	unsigned long dcm;
++	dma_addr_t dsa;
++	dma_addr_t dta;
++	unsigned long dtc;
++	unsigned long sd;
++	unsigned long drt;
++	unsigned long reserved[2];
++};
++
++enum sdesc_status {
++	STAT_STOPPED = 0, STAT_RUNNING, STAT_ERROR
++};
++
++struct ingenic_dma_chan;
++struct ingenic_dma_sdesc {
++	struct virt_dma_desc	vd;		/* Virtual descriptor */
++	int			nb_desc;	/* Number of hw. descriptors */
++	size_t			len;		/* Number of bytes xfered */
++	bool			cyclic;
++	struct hdma_desc	**hw_desc;	/* DMA coherent descriptors */
++	dma_addr_t		*hw_desc_dma;	/* DMA address of the Descriptors*/
++	struct ingenic_dma_chan	*dmac;		/* for free*/
++	int			dcs;		/* The DCS initial value */
++	int			curr_desc;
++	enum sdesc_status	status;
++};
++
++struct ingenic_dma_chan {
++	struct virt_dma_chan	vc;		/* Virtual channel */
++	int 			id;		/* Channel id*/
++	void __iomem   		*iomem;
++	struct ingenic_dma_engine	*engine;
++	bool			fake_cyclic;
++
++	/*dma slave channel config*/
++	unsigned int		slave_id;	/* Request type of the channel */
++	enum dma_transfer_direction direction;
++	dma_addr_t		slave_addr;
++	unsigned int		maxburst;
++	unsigned int		transfer_width;
++	unsigned int		fast_mode;	/* The fast mode bit of dmac*/
++	unsigned int 		dcm;		/* The DCM of HW Descriptor initial value*/
++
++
++	/*Descriptors*/
++	struct dma_pool		*hdesc_pool;	/*HW Descriptors pool */
++	spinlock_t		hdesc_lock;	/*HW Descriptor assign lock*/
++	int			hdesc_num;	/*HW Descriptors assigned num*/
++	int			hdesc_max;	/*HW Descriptors maxnum capacity*/
++
++	struct ingenic_dma_sdesc	*sdesc;		/*Current Running Async Tx Desc*/
++
++	/*channel terminated completion*/
++	struct completion completion;
++};
++
++struct ingenic_dma_engine {
++	struct device		*dev;
++	void __iomem   		*iomem;
++	struct clk		*gate_clk;
++	struct dma_device		dma_device;
++	struct device_dma_parameters	dma_parms;
++
++	uint32_t		chan_reserved;
++	uint32_t		chan_programed;
++	int			intc_ch;
++	bool			special_ch;
++
++	/*hardware interrupt*/
++	int 			irq_pdma;	/* pdma interrupt*/
++	int                     irq_pdmam;	/* pdma mcu interrupt */
++	int			irq_pdmad;	/* pdma per-descriptor interrupt*/
++
++	/*hardware params*/
++#define HWATTR_INTC_IRQ		(1 << 0)
++#define HWATTR_SPECIAL_CH01	(1 << 1)
++#define HWATTR_DESC_INTER	(1 << 2)
++#define HWATTR_INTC_IRQ_SUP(x)		(HWATTR_INTC_IRQ & (x))
++#define	HWATTR_SPECIAL_CH01_SUP(x)	(HWATTR_SPECIAL_CH01 & (x))
++#define HWATTR_DESC_INTER_SUP(x)	(HWATTR_DESC_INTER & (x))
++	unsigned int		hwattr;
++	/*channels*/
++	int			nr_chs;
++	struct ingenic_dma_chan*	chan[];
++};
++
++static inline struct device *chan2dev(struct dma_chan *chan)
++{
++	return &chan->dev->device;
++}
++
++static inline struct ingenic_dma_chan *to_ingenic_dma_chan(struct dma_chan *chan)
++{
++	return container_of(chan, struct ingenic_dma_chan, vc.chan);
++}
++
++static inline struct ingenic_dma_sdesc *to_ingenic_dma_sdesc(struct virt_dma_desc *vd)
++{
++	return container_of(vd, struct ingenic_dma_sdesc, vd);
++}
++
++u32 ingenic_dma_read_dtc(struct dma_chan *chan)
++{
++	struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(chan);
++	return readl(dmac->iomem + CH_DTC);
++}
++EXPORT_SYMBOL_GPL(ingenic_dma_read_dtc);
++
++u32 ingenic_dma_read_dda(struct dma_chan *chan)
++{
++	struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(chan);
++	return readl(dmac->iomem + CH_DDA);
++}
++EXPORT_SYMBOL_GPL(ingenic_dma_read_dda);
++
++int ingenic_dma_get_desc_index(struct dma_chan *chan, unsigned int doa, int desc_num)
++{
++	struct ingenic_dma_chan *dmac = to_ingenic_dma_chan(chan);
++	struct ingenic_dma_sdesc *sdesc = dmac->sdesc;
++	int i;
++	for(i = 0; i < desc_num; i++) {
++		if ((doa << 24) == PHY_TO_DESC_DOA(sdesc->hw_desc_dma[i])){
++			if (i == 0)
++				return desc_num - 1;
++			else
++				return i - 1;
++		}
++	}
++
++	return -1;
++}
++EXPORT_SYMBOL_GPL(ingenic_dma_get_desc_index);
++
++#endif /*__INGENIC_DMA_H__*/
+diff --git a/module_drivers/drivers/i2c/Makefile b/module_drivers/drivers/i2c/Makefile
+new file mode 100644
+index 000000000..0717b752f
+--- /dev/null
++++ b/module_drivers/drivers/i2c/Makefile
+@@ -0,0 +1 @@
++obj-y += busses/
+diff --git a/module_drivers/drivers/i2c/busses/Kconfig b/module_drivers/drivers/i2c/busses/Kconfig
+new file mode 100644
+index 000000000..b67e622de
+--- /dev/null
++++ b/module_drivers/drivers/i2c/busses/Kconfig
+@@ -0,0 +1,27 @@
++config I2C_INGENIC
++        bool "Ingenic SoC based on Xburst arch's I2C controler Driver support"
++        help
++          Say Y here in order to support Ingenic SoC's I2C Controller Drvier
++
++config I2C_NON_RESTART_MODE
++        bool "controler i2c no restart mode"
++        depends on I2C_INGENIC
++        default n
++
++config I2C_FIFO_LEN
++        int "INGENIC I2C Controller FIFO length"
++        default 64
++        depends on I2C_INGENIC
++        help
++          M200 and JZ4775 have 64 entries FIFO.
++
++config I2C_DEBUG_INFO
++        bool "enable or disable Ingenic Soc's I2C driver debug info"
++        default n
++        depends on I2C_INGENIC
++        help
++          I2C debug print info, you can get the debug information from
++          /sys/devices/platform/i2c-ingenic.x/debug_info,
++          for example, echo 3 > /sys/devices/platform/i2c-ingenic.x/debug
++
++
+diff --git a/module_drivers/drivers/i2c/busses/Makefile b/module_drivers/drivers/i2c/busses/Makefile
+new file mode 100644
+index 000000000..6d81983b5
+--- /dev/null
++++ b/module_drivers/drivers/i2c/busses/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_I2C_INGENIC)       += i2c-ingenic.o
+diff --git a/module_drivers/drivers/i2c/busses/i2c-ingenic.c b/module_drivers/drivers/i2c/busses/i2c-ingenic.c
+new file mode 100644
+index 000000000..a62e93ed7
+--- /dev/null
++++ b/module_drivers/drivers/i2c/busses/i2c-ingenic.c
+@@ -0,0 +1,1146 @@
++/* drivers/i2c/busses/i2c-v12-ingenic.c
++ *
++ * Copyright (C) 2014 Ingenic Semiconductor Co., Ltd.
++ *      http://www.ingenic.com
++ *      Sun Jiwei<jwsun@ingenic.cn>
++ *
++ * I2C adapter driver for the Ingenic I2C controller
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/i2c.h>
++#include <linux/init.h>
++#include <linux/time.h>
++#include <linux/sched.h>
++#include <linux/errno.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <linux/completion.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/gpio.h>
++#include <linux/of.h>
++#include <linux/clk-provider.h>
++
++#define	I2C_CTRL		(0x00)
++#define	I2C_TAR     		(0x04)
++#define	I2C_SAR     		(0x08)
++#define	I2C_DC      		(0x10)
++#define	I2C_SHCNT		(0x14)
++#define	I2C_SLCNT		(0x18)
++#define	I2C_FHCNT		(0x1C)
++#define	I2C_FLCNT		(0x20)
++#define	I2C_INTST		(0x2C)
++#define	I2C_INTM		(0x30)
++#define I2C_RAW_INTR_STAT	(0x34)
++#define I2C_RXTL		(0x38)
++#define I2C_TXTL		(0x3c)
++#define	I2C_CINTR		(0x40)
++#define	I2C_CRXUF		(0x44)
++#define	I2C_CRXOF		(0x48)
++#define	I2C_CTXOF		(0x4C)
++#define	I2C_CRXREQ		(0x50)
++#define	I2C_CTXABRT		(0x54)
++#define	I2C_CRXDONE		(0x58)
++#define	I2C_CACT		(0x5C)
++#define	I2C_CSTP		(0x60)
++#define	I2C_CSTT		(0x64)
++#define	I2C_CGC    		(0x68)
++#define	I2C_ENB     		(0x6C)
++#define	I2C_STA     		(0x70)
++#define I2C_TXFLR		(0x74)
++#define I2C_RXFLR		(0x78)
++#define I2C_SDAHD		(0x7C)
++#define	I2C_TXABRT		(0x80)
++#define I2C_DMACR            	(0x88)
++#define I2C_DMATDLR          	(0x8c)
++#define I2C_DMARDLR     	(0x90)
++#define	I2C_SDASU		(0x94)
++#define	I2C_ACKGC		(0x98)
++#define	I2C_ENSTA		(0x9C)
++#define I2C_FLT			(0xA0)
++
++/* I2C Control Register (I2C_CTRL) */
++#define I2C_CTRL_SLVDIS		(1 << 6)	/* after reset slave is disabled */
++#define I2C_CTRL_REST		(1 << 5)
++#define I2C_CTRL_MATP		(1 << 4)	/* 1: 10bit address 0: 7bit addressing */
++#define I2C_CTRL_SATP		(1 << 3)	/* 1: 10bit address 0: 7bit address */
++#define I2C_CTRL_SPDF		(2 << 1)	/* fast mode 400kbps */
++#define I2C_CTRL_SPDS		(1 << 1)	/* standard mode 100kbps */
++#define I2C_CTRL_MD		(1 << 0)	/* master enabled */
++
++/* I2C Status Register (I2C_STA) */
++#define I2C_STA_SLVACT		(1 << 6)	/* Slave FSM is not in IDLE state */
++#define I2C_STA_MSTACT		(1 << 5)	/* Master FSM is not in IDLE state */
++#define I2C_STA_RFF		(1 << 4)	/* RFIFO if full */
++#define I2C_STA_RFNE		(1 << 3)	/* RFIFO is not empty */
++#define I2C_STA_TFE		(1 << 2)	/* TFIFO is empty */
++#define I2C_STA_TFNF		(1 << 1)	/* TFIFO is not full  */
++#define I2C_STA_ACT		(1 << 0)	/* I2C Activity Status */
++
++/* i2c interrupt status (I2C_INTST) */
++#define I2C_INTST_IGC           (1 << 11)
++#define I2C_INTST_ISTT          (1 << 10)
++#define I2C_INTST_ISTP          (1 << 9)
++#define I2C_INTST_IACT          (1 << 8)
++#define I2C_INTST_RXDN          (1 << 7)
++#define I2C_INTST_TXABT         (1 << 6)
++#define I2C_INTST_RDREQ         (1 << 5)
++#define I2C_INTST_TXEMP         (1 << 4)
++#define I2C_INTST_TXOF          (1 << 3)
++#define I2C_INTST_RXFL          (1 << 2)
++#define I2C_INTST_RXOF          (1 << 1)
++#define I2C_INTST_RXUF          (1 << 0)
++
++/* i2c interrupt mask status (I2C_INTM) */
++#define I2C_INTM_MIGC		(1 << 11)
++#define I2C_INTM_MISTT		(1 << 10)
++#define I2C_INTM_MISTP		(1 << 9)
++#define I2C_INTM_MIACT		(1 << 8)
++#define I2C_INTM_MRXDN		(1 << 7)
++#define I2C_INTM_MTXABT		(1 << 6)
++#define I2C_INTM_MRDREQ		(1 << 5)
++#define I2C_INTM_MTXEMP		(1 << 4)
++#define I2C_INTM_MTXOF		(1 << 3)
++#define I2C_INTM_MRXFL		(1 << 2)
++#define I2C_INTM_MRXOF		(1 << 1)
++#define I2C_INTM_MRXUF		(1 << 0)
++
++#define I2C_DC_REST		(1 << 10)
++#define I2C_DC_STP		(1 << 9)
++#define I2C_DC_READ    		(1 << 8)
++
++#define I2C_ENB_I2CENB		(1 << 0)	/* Enable the i2c */
++
++#ifdef CONFIG_I2C_FIFO_LEN
++#define I2C_FIFO_LEN		(CONFIG_I2C_FIFO_LEN)
++#else
++#define I2C_FIFO_LEN		(64)
++#endif
++
++#define TX_LEVEL		(I2C_FIFO_LEN / 2)
++#define RX_LEVEL		(I2C_FIFO_LEN / 2 - 1)
++#define TIMEOUT			0xff
++#define DEBUG_INFO		2
++#define DEBUG_WARN		1
++
++//#define I2C_DEBUG
++/*
++ *  msg_end_type: The bus control which need to be send at end of transfer.
++ *  @MSG_END_STOP: Send stop pulse at end of transfer.
++ *  @MSG_END_REPEAT_START: Send repeat start at end of transfer.
++ */
++enum msg_end_type {
++	MSG_END_STOP,
++	MSG_END_CONTINUE,
++	MSG_END_REPEAT_START,
++};
++
++/* I2C Transmit Abort Status Register (I2C_TXABRT) */
++static const char *abrt_src[] = {
++	"I2C_TXABRT_ABRT_7B_ADDR_NOACK",
++	"I2C_TXABRT_ABRT_10ADDR1_NOACK",
++	"I2C_TXABRT_ABRT_10ADDR2_NOACK",
++	"I2C_TXABRT_ABRT_XDATA_NOACK",
++	"I2C_TXABRT_ABRT_GCALL_NOACK",
++	"I2C_TXABRT_ABRT_GCALL_READ",
++	"I2C_TXABRT_ABRT_HS_ACKD",
++	"I2C_TXABRT_SBYTE_ACKDET",
++	"I2C_TXABRT_ABRT_HS_NORSTRT",
++	"I2C_TXABRT_SBYTE_NORSTRT",
++	"I2C_TXABRT_ABRT_10B_RD_NORSTRT",
++	"I2C_TXABRT_ABRT_MASTER_DIS",
++	"I2C_TXABRT_ARB_LOST",
++	"I2C_TXABRT_SLVFLUSH_TXFIFO",
++	"I2C_TXABRT_SLV_ARBLOST",
++	"I2C_TXABRT_SLVRD_INTX",
++};
++
++/* I2C standard mode high count register(I2CSHCNT) */
++#define I2CSHCNT_ADJUST(n)      (((n) - 8) < 6 ? 6 : ((n) - 8))
++/* I2C standard mode low count register(I2CSLCNT) */
++#define I2CSLCNT_ADJUST(n)      (((n) - 1) < 8 ? 8 : ((n) - 1))
++/* I2C fast mode high count register(I2CFHCNT) */
++#define I2CFHCNT_ADJUST(n)      (((n) - 8) < 6 ? 6 : ((n) - 8))
++/* I2C fast mode low count register(I2CFLCNT) */
++#define I2CFLCNT_ADJUST(n)      (((n) - 1) < 8 ? 8 : ((n) - 1))
++
++struct i2c_ingenic {
++	void __iomem *iomem;
++	struct device *dev;
++	int irq;
++	struct clk *clk;
++	struct i2c_adapter adap;
++
++	enum msg_end_type w_end_type;
++	enum msg_end_type r_end_type;
++	unsigned char *rbuf;
++	unsigned char *wbuf;
++	unsigned int rd_len;
++	int len;
++
++	struct completion complete;
++
++	int debug;
++	unsigned int rate;
++
++	unsigned int timeout_ms;	/*ms*/
++	unsigned int speed_hz;		/*hz*/
++	unsigned int id;		/*chip id*/
++	bool clk_always_enable;
++};
++
++static inline unsigned short i2c_readl(struct i2c_ingenic *i2c,
++		unsigned short offset);
++#ifdef I2C_DEBUG
++static void i2c_ingenic_dump_regs(struct i2c_ingenic *i2c)
++{
++	struct i2c_ingenic *i2c_id = i2c;
++
++#define PRINT_REG_WITH_ID(reg_name, id)					\
++	dev_info(&(i2c->adap.dev),"--"#reg_name "    	0x%08x\n",i2c_readl(id, reg_name))
++
++	PRINT_REG_WITH_ID(I2C_CTRL, i2c_id);
++	PRINT_REG_WITH_ID(I2C_INTST, i2c_id);
++	PRINT_REG_WITH_ID(I2C_INTM, i2c_id);
++	PRINT_REG_WITH_ID(I2C_RAW_INTR_STAT, i2c_id);
++	PRINT_REG_WITH_ID(I2C_RXTL, i2c_id);
++	PRINT_REG_WITH_ID(I2C_TXTL, i2c_id);
++	PRINT_REG_WITH_ID(I2C_STA, i2c_id);
++	PRINT_REG_WITH_ID(0x78, i2c_id);
++	return;
++
++	PRINT_REG_WITH_ID(I2C_CTRL, i2c_id);
++	PRINT_REG_WITH_ID(I2C_TAR, i2c_id);
++	PRINT_REG_WITH_ID(I2C_SAR, i2c_id);
++	//      PRINT_REG_WITH_ID(I2C_DC, i2c_id);
++	PRINT_REG_WITH_ID(I2C_SHCNT, i2c_id);
++	PRINT_REG_WITH_ID(I2C_SLCNT, i2c_id);
++	PRINT_REG_WITH_ID(I2C_FHCNT, i2c_id);
++	PRINT_REG_WITH_ID(I2C_FLCNT, i2c_id);
++	PRINT_REG_WITH_ID(I2C_INTST, i2c_id);
++	PRINT_REG_WITH_ID(I2C_INTM, i2c_id);
++	PRINT_REG_WITH_ID(I2C_RXTL, i2c_id);
++	PRINT_REG_WITH_ID(I2C_TXTL, i2c_id);
++	PRINT_REG_WITH_ID(I2C_CINTR, i2c_id);
++	PRINT_REG_WITH_ID(I2C_CRXUF, i2c_id);
++	PRINT_REG_WITH_ID(I2C_CRXOF, i2c_id);
++	PRINT_REG_WITH_ID(I2C_CTXOF, i2c_id);
++	PRINT_REG_WITH_ID(I2C_CRXREQ, i2c_id);
++	PRINT_REG_WITH_ID(I2C_CTXABRT, i2c_id);
++	PRINT_REG_WITH_ID(I2C_CRXDONE, i2c_id);
++	PRINT_REG_WITH_ID(I2C_CACT, i2c_id);
++	PRINT_REG_WITH_ID(I2C_CSTP, i2c_id);
++	PRINT_REG_WITH_ID(I2C_CSTT, i2c_id);
++	PRINT_REG_WITH_ID(I2C_CGC, i2c_id);
++	PRINT_REG_WITH_ID(I2C_ENB, i2c_id);
++	PRINT_REG_WITH_ID(I2C_STA, i2c_id);
++	/*debug trans & recive fifo count */
++	PRINT_REG_WITH_ID(0x74, i2c_id);
++	PRINT_REG_WITH_ID(0x78, i2c_id);
++
++	PRINT_REG_WITH_ID(I2C_TXABRT, i2c_id);
++	PRINT_REG_WITH_ID(I2C_DMACR, i2c_id);
++	PRINT_REG_WITH_ID(I2C_DMATDLR, i2c_id);
++	PRINT_REG_WITH_ID(I2C_DMARDLR, i2c_id);
++	PRINT_REG_WITH_ID(I2C_SDASU, i2c_id);
++	PRINT_REG_WITH_ID(I2C_ACKGC, i2c_id);
++	PRINT_REG_WITH_ID(I2C_ENSTA, i2c_id);
++	PRINT_REG_WITH_ID(I2C_SDAHD, i2c_id);
++#undef PRINT_REG_WITH_ID
++}
++#else	/* I2C_DEBUG */
++static void i2c_ingenic_dump_regs(struct i2c_ingenic *i2c) {}
++#endif /* !I2C_DEBUG */
++
++static inline unsigned short i2c_readl(struct i2c_ingenic *i2c,
++		unsigned short offset)
++{
++	return readl(i2c->iomem + offset);
++}
++
++static inline void i2c_writel(struct i2c_ingenic *i2c, unsigned short offset,
++		unsigned short value)
++{
++	writel(value, i2c->iomem + offset);
++}
++
++static int i2c_ingenic_enable(struct i2c_ingenic *i2c, int enable)
++{
++	int timeout = TIMEOUT;
++
++	i2c_writel(i2c, I2C_ENB, enable);
++	while (((i2c_readl(i2c, I2C_ENSTA) & I2C_ENB_I2CENB) == !enable) && (--timeout > 0))
++		msleep(1);
++
++	if (timeout)
++		return 0;
++
++	dev_err(&(i2c->adap.dev), "%s i2c%d failed\n", enable?"enable":"disable", i2c->adap.nr);
++	return -ETIMEDOUT;
++}
++
++static void i2c_ingenic_reset(struct i2c_ingenic *i2c)
++{
++	i2c_readl(i2c, I2C_CTXABRT);
++	i2c_readl(i2c, I2C_INTST);
++
++	i2c_ingenic_enable(i2c, 0);
++	udelay(10);					/* Don't know why to wait for 10us */
++	i2c_ingenic_enable(i2c, 1);
++}
++
++/* function: send read command
++ * return:	0, successful
++ *		1, txfifo valid entry is more than receive fifo, before send read command,
++ *			must be read.
++ *		2, txfifo count is 0 or rxfifo count is 0.
++ * */
++static inline unsigned int i2c_send_rcmd(struct i2c_ingenic *i2c)
++{
++	unsigned int tx_count, rx_count, count, tx_valid, rx_valid;
++
++	tx_valid = i2c_readl(i2c, I2C_TXFLR);
++	rx_valid = i2c_readl(i2c, I2C_RXFLR);
++	tx_count = I2C_FIFO_LEN - tx_valid;
++	rx_count = I2C_FIFO_LEN - rx_valid;
++
++#ifdef CONFIG_I2C_DEBUG_INFO
++	if(i2c->debug > DEBUG_INFO)
++		dev_info(&(i2c->adap.dev),
++				"%s, tx_valid = %d, rx_valid = %d,"
++				" tx_count = %d, rx_count = %d\n",
++				__func__, tx_valid, rx_valid, tx_count, rx_count);
++#endif
++
++	if (tx_valid > rx_count) {
++		dev_warn(&(i2c->adap.dev),
++				"\n\n###Warrning: I2C transfer fifo valid entry is more receive fifo, "
++				"before send read cmd, please read data from "
++				"the read fifo.\n\n");
++		return 1;
++	}
++
++	if (!tx_count || !rx_count) {
++		dev_warn(&(i2c->adap.dev),
++				"\n\n###Warrning: I2C receive fifo or transfer fifo is full, "
++				"before send read cmd, please read data from "
++				"the read fifo or wait some time.\n\n");
++		return 2;
++	}
++
++	count = min3(i2c->rd_len, tx_count, rx_count);
++
++#ifdef CONFIG_I2C_DEBUG_INFO
++	if (i2c->debug > DEBUG_INFO)
++		dev_info(&(i2c->adap.dev),
++				"%s, Before send read cmd, "
++				"need_send = %d, left_send = %d\n",
++				__func__, count ,i2c->rd_len);
++#endif
++
++	i2c->rd_len -= count;
++
++	if (!i2c->rd_len) {
++		while (count > 1) {
++			i2c_writel(i2c, I2C_DC, I2C_DC_READ);
++			count--;
++		}
++		if (i2c->r_end_type == MSG_END_STOP) {
++			i2c_writel(i2c, I2C_DC, I2C_DC_READ | I2C_DC_STP);
++		} else {
++			i2c_writel(i2c, I2C_DC, I2C_DC_READ);
++		}
++	} else {
++		while (count > 0) {
++			i2c_writel(i2c, I2C_DC, I2C_DC_READ);
++			count--;
++		}
++	}
++
++#ifdef CONFIG_I2C_DEBUG_INFO
++	if(i2c->debug > DEBUG_INFO)
++		dev_info(&(i2c->adap.dev),
++				"%s, After send read cmd, "
++				"left_send = %d\n",
++				__func__, i2c->rd_len);
++#endif
++	return 0;
++}
++
++#ifdef CONFIG_I2C_DEBUG_INFO
++static ssize_t enable_debug(struct device *dev, struct device_attribute *attr,
++		                        const char *buf, size_t size)
++{
++	int rc;
++	unsigned long   enable;
++	struct i2c_ingenic *i2c = (struct i2c_ingenic *)dev_get_drvdata(dev);
++
++	rc = kstrtol(buf, 0, &enable);
++	if (rc)
++		return rc;
++
++	if ((enable >= 0) && (enable <= DEBUG_INFO + 1))
++		i2c->debug = enable;
++	else
++		goto err;
++
++	return size;
++err:
++	pr_err("Please input correct number(enable >= 0 && enable <= 5)"
++			" to disable or enable debug info print\n");
++	return -EAGAIN;
++}
++
++static struct device_attribute attributes[] = {
++	__ATTR(debug_info, 0200, NULL, enable_debug),
++};
++
++static int create_debug_sysfs_interface(struct device *dev)
++{
++	int i;
++	for (i = 0; i < ARRAY_SIZE(attributes); i++)
++		if (device_create_file(dev, attributes + i))
++			goto err;
++	return 0;
++
++err:
++	for( ; i >= 0; i--)
++		device_remove_file(dev, attributes + i);
++	return -1;
++}
++#endif
++
++static irqreturn_t i2c_ingenic_irq(int irqno, void *dev_id)
++{
++	unsigned short tmp, intst, intmsk;
++	struct i2c_ingenic *i2c = dev_id;
++
++	intst = i2c_readl(i2c, I2C_INTST);
++	intmsk = i2c_readl(i2c, I2C_INTM);
++
++#ifdef CONFIG_I2C_DEBUG_INFO
++	if (i2c->debug > DEBUG_INFO)
++		dev_info(&(i2c->adap.dev), "--I2C irq register INTST:0x%08x\n", intst);
++#endif
++
++	if ((intst & I2C_INTST_TXABT) && (intmsk & I2C_INTM_MTXABT)) {
++		dev_err(&(i2c->adap.dev),
++				"%s %d, I2C transfer error, ABORT interrupt\n",
++				__func__, __LINE__);
++		goto END_TRSF_IRQ_HND;
++	}
++
++	if ((intst & I2C_INTST_ISTP) && (intmsk & I2C_INTM_MISTP)) {
++		i2c_readl(i2c, I2C_CSTP);	/* clear STP bit */
++#ifdef CONFIG_I2C_DEBUG_INFO
++		if (i2c->debug > DEBUG_INFO) {
++			dev_info(&(i2c->adap.dev),
++					"%s, Now stop condition has occurred,"
++					"and left data length is %d\n",
++					__func__, i2c->len);
++		}
++#endif
++
++		if (i2c->len == 0)
++			goto END_TRSF_IRQ_HND;
++	}
++
++	if ((intmsk & I2C_INTM_MTXEMP) && (intst & I2C_INTST_TXEMP)) {
++		if (!i2c->len) {
++			if (i2c->w_end_type == MSG_END_REPEAT_START) {
++				goto END_TRSF_IRQ_HND;
++			} else {
++				tmp = i2c_readl(i2c, I2C_INTM);
++				tmp &= ~I2C_INTM_MTXEMP;
++				i2c_writel(i2c, I2C_INTM, tmp);
++			}
++		} else {
++			while ((i2c->len > 0) &&
++					(i2c_readl(i2c, I2C_STA) & I2C_STA_TFNF)) {
++				tmp = *i2c->wbuf++;
++				if (i2c->len == 1) {
++					if (i2c->w_end_type == MSG_END_STOP)
++						tmp |= I2C_DC_STP;
++				}
++
++				i2c_writel(i2c, I2C_DC, tmp);
++				i2c->len -= 1;
++			}
++
++			if (i2c->len == 0) {
++				i2c_writel(i2c, I2C_TXTL, 0);
++			}
++		}
++	}
++
++	if ((intst & I2C_INTST_RXFL) && (intmsk & I2C_INTM_MRXFL)) {
++#ifdef CONFIG_I2C_DEBUG_INFO
++		if (i2c->debug >= DEBUG_INFO) {
++			dev_info(&(i2c->adap.dev),
++					"%s, Before read I2C_DC, "
++					"left_send_cmd = %d, left_read_cnt = %d,"
++					" rx_valid = %d, tx_valid = %d\n",
++					__func__, i2c->rd_len, i2c->len,
++					i2c_readl(i2c, I2C_RXFLR), i2c_readl(i2c, I2C_TXFLR));
++		}
++#endif
++
++		while ((i2c_readl(i2c, I2C_STA) & I2C_STA_RFNE) &&
++				(i2c->len > 0)) {
++			tmp = i2c_readl(i2c, I2C_DC) & 0xff;
++			*i2c->rbuf++ = tmp;
++			i2c->len--;
++		}
++
++#ifdef CONFIG_I2C_DEBUG_INFO
++		if (i2c->debug >= DEBUG_INFO)
++			dev_info(&(i2c->adap.dev),
++					"%s, After read I2C_DC, "
++					"left_read_cnt = %d,"
++					" rx_valid = %d, tx_valid = %d\n",
++					__func__, i2c->len,
++					i2c_readl(i2c, I2C_RXFLR), i2c_readl(i2c, I2C_TXFLR));
++#endif
++
++		if (i2c->len == 0) {
++			goto END_RECE_IRQ_HND;
++		}
++
++		if (i2c->len <= I2C_FIFO_LEN) {
++			i2c_writel(i2c, I2C_RXTL, i2c->len - 1);
++		}
++
++		if (i2c_send_rcmd(i2c)) {
++			dev_err(&(i2c->adap.dev),
++					"%s %d, I2C controller has BUG,"
++					" RXFLR or TXFLR can not clear\n",
++					__func__, __LINE__);
++			BUG();
++		}
++
++#ifdef CONFIG_I2C_DEBUG_INFO
++		if (i2c->debug > DEBUG_INFO)
++			dev_info(&(i2c->adap.dev),
++					"%s, After send read command, "
++					"left_send_cmd = %d, "
++					"left_read_cnt = %d\n",
++					__func__, i2c->rd_len, i2c->len);
++#endif
++	}
++
++	if ((intst & I2C_INTST_RXOF) && (intmsk & I2C_INTM_MRXOF)) {
++		dev_err(&(i2c->adap.dev),
++				"%s %d, I2C transfer error, RXFIFO over full\n",
++				__func__, __LINE__);
++		i2c_readl(i2c, I2C_CRXOF);	/* clear RXOF bit */
++	}
++
++	if ((intst & I2C_INTST_TXOF) && (intmsk & I2C_INTM_MTXOF)) {
++		dev_err(&(i2c->adap.dev),
++				"%s %d, I2C transfer error, TXFIFO over full\n",
++				__func__, __LINE__);
++		i2c_readl(i2c, I2C_CTXOF);	/* clear TXOF bit */
++		goto END_TRSF_IRQ_HND;
++	}
++
++	return IRQ_HANDLED;
++END_RECE_IRQ_HND:
++END_TRSF_IRQ_HND:
++	i2c_writel(i2c, I2C_INTM, 0);
++	complete(&i2c->complete);
++	return IRQ_HANDLED;
++}
++
++static void txabrt(struct i2c_ingenic *i2c, int src)
++{
++	int i;
++
++	dev_err(&(i2c->adap.dev), "--I2C txabrt:\n");
++	for (i = 0; i < 16; i++) {
++		if (src & (0x1 << i))
++			dev_info(&(i2c->adap.dev), "--I2C TXABRT[%d]=%s\n", i,
++					abrt_src[i]);
++	}
++}
++
++static inline int xfer_read(struct i2c_ingenic *i2c, unsigned char *buf, int len,
++		enum msg_end_type end_type)
++{
++	int ret = 0;
++	long timeout;
++	unsigned short tmp;
++	unsigned int wait_complete_timeout_ms;
++
++	wait_complete_timeout_ms =
++		len * 1000 * 9 * 2 / i2c->rate + i2c->timeout_ms;
++
++#ifdef CONFIG_I2C_DEBUG_INFO
++	if (i2c->debug > DEBUG_WARN)
++		dev_info(&(i2c->adap.dev),
++				"%s, Begin read msg, want to read length is %d\n",
++				__func__, len);
++	memset(buf, 0, len);
++#endif
++
++	i2c->rd_len = len;
++	i2c->len = len;
++	i2c->rbuf = buf;
++	i2c->r_end_type = end_type;
++
++	i2c_readl(i2c, I2C_CSTP);	/* clear STP bit */
++	i2c_readl(i2c, I2C_CTXOF);	/* clear TXOF bit */
++	i2c_readl(i2c, I2C_CTXABRT);	/* clear TXABRT bit */
++
++	if (len <= I2C_FIFO_LEN) {
++		i2c_writel(i2c, I2C_RXTL, len - 1);
++	} else {
++		i2c_writel(i2c, I2C_RXTL, RX_LEVEL);
++	}
++
++	while (i2c_readl(i2c, I2C_STA) & I2C_STA_RFNE) {
++		i2c_readl(i2c, I2C_DC);
++	}
++	if (i2c_send_rcmd(i2c))
++		BUG();
++
++	tmp = I2C_INTM_MRXFL | I2C_INTM_MTXABT;
++	if (end_type == MSG_END_STOP)
++		tmp |= I2C_INTM_MISTP;
++	i2c_writel(i2c, I2C_INTM, tmp);
++
++
++	timeout = wait_for_completion_timeout(&i2c->complete,
++			msecs_to_jiffies
++			(wait_complete_timeout_ms));
++	if (!timeout) {
++		dev_err(&(i2c->adap.dev), "--I2C irq read timeout\n");
++		i2c_ingenic_dump_regs(i2c);
++		ret = -ETIMEDOUT;
++	}
++
++	tmp = i2c_readl(i2c, I2C_TXABRT);
++	if (tmp) {
++		txabrt(i2c, tmp);
++		if (tmp > 0x1 && tmp < 0x10)
++			ret = -ENXIO;
++		else
++			ret = -EIO;
++		// ABRT_GCALL_READ
++		if (tmp & (1 << 5)) {
++			ret = -EAGAIN;
++		}
++		i2c_readl(i2c, I2C_CTXABRT);
++	}
++
++	if (ret < 0)
++		i2c_ingenic_reset(i2c);
++
++#ifdef CONFIG_I2C_DEBUG_INFO
++	if (i2c->debug > DEBUG_WARN)
++		dev_info(&(i2c->adap.dev),
++				"%s, Reading msg over\n", __func__);
++#endif
++
++	return ret;
++}
++
++static inline int xfer_write(struct i2c_ingenic *i2c, unsigned char *buf, int len,
++		enum msg_end_type end_type)
++{
++	int ret = 0;
++	long timeout = TIMEOUT;
++	unsigned short reg_tmp;
++	unsigned int wait_complete_timeout_ms;
++
++	wait_complete_timeout_ms =
++		len * 1000 * 9 * 2 / i2c->rate + i2c->timeout_ms;
++
++#ifdef CONFIG_I2C_DEBUG_INFO
++	if (i2c->debug > DEBUG_WARN)
++		dev_info(&(i2c->adap.dev),
++				"%s, Begin write msg, want to write length is %d\n",
++				__func__, len);
++#endif
++	i2c->wbuf = buf;
++	i2c->len = len;
++
++	i2c_writel(i2c, I2C_TXTL, TX_LEVEL);
++
++	i2c_readl(i2c, I2C_CSTP);	/* clear STP bit */
++	i2c_readl(i2c, I2C_CTXOF);	/* clear TXOF bit */
++	i2c_readl(i2c, I2C_CTXABRT);	/* clear TXABRT bit */
++
++	i2c->w_end_type = end_type;
++	while ((i2c_readl(i2c, I2C_STA) & I2C_STA_TFNF) && (i2c->len > 0)) {
++		reg_tmp = *i2c->wbuf++;
++		if (i2c->len == 1) {
++			if (end_type == MSG_END_STOP) {
++				reg_tmp |= I2C_DC_STP;
++			}
++		}
++		i2c_writel(i2c, I2C_DC, reg_tmp);
++
++		i2c->len -= 1;
++	}
++
++	if (i2c->len == 0) {
++		i2c_writel(i2c, I2C_TXTL, 0);
++	}
++
++	reg_tmp = I2C_INTM_MTXEMP | I2C_INTM_MTXABT | I2C_INTM_MTXOF;
++	if (end_type == MSG_END_STOP)
++		reg_tmp |= I2C_INTM_MISTP;
++
++	i2c_writel(i2c, I2C_INTM, reg_tmp);
++
++	timeout = wait_for_completion_timeout(&i2c->complete,
++			msecs_to_jiffies
++			(wait_complete_timeout_ms));
++
++	if (!timeout) {
++		dev_err(&(i2c->adap.dev), "--I2C pio write wait timeout\n");
++		i2c_ingenic_dump_regs(i2c);
++		ret = -ETIMEDOUT;
++	}
++
++	reg_tmp = i2c_readl(i2c, I2C_TXABRT);
++	if (reg_tmp) {
++		txabrt(i2c, reg_tmp);
++		if (reg_tmp > 0x1 && reg_tmp < 0x10)
++			ret = -ENXIO;
++		else
++			ret = -EIO;
++		//after I2C_TXABRT_ABRT_XDATA_NOACK error,this required core to resend
++		if (reg_tmp & 8) {
++			ret = -EAGAIN;
++		}
++		i2c_readl(i2c, I2C_CTXABRT);
++	}
++
++#ifdef CONFIG_I2C_DEBUG_INFO
++	if (i2c->debug > DEBUG_WARN)
++		dev_info(&(i2c->adap.dev),
++				"%s, Write msg over\n", __func__);
++#endif
++	return ret;
++}
++
++static int i2c_disable_clk(struct i2c_ingenic *i2c)
++{
++	int timeout = 10;
++	int tmp = i2c_readl(i2c, I2C_STA);
++
++	while ((tmp & I2C_STA_MSTACT) && (--timeout > 0)) {
++		udelay(90);
++		tmp = i2c_readl(i2c, I2C_STA);
++	}
++	if (timeout > 0) {
++		if ((!IS_ERR(i2c->clk)) && (!i2c->clk_always_enable))
++			clk_disable_unprepare(i2c->clk);
++		return 0;
++	} else {
++		dev_err(&(i2c->adap.dev),
++				"--I2C disable clk timeout, I2C_STA = 0x%x\n", tmp);
++		i2c_ingenic_reset(i2c);
++		if ((!IS_ERR(i2c->clk)) && (!i2c->clk_always_enable))
++			clk_disable_unprepare(i2c->clk);
++		return -ETIMEDOUT;
++	}
++}
++
++static int i2c_ingenic_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int count)
++{
++	int i, ret = 0;
++	struct i2c_ingenic *i2c = adap->algo_data;
++
++#ifdef CONFIG_I2C_DEBUG_INFO
++	if (i2c->debug > DEBUG_WARN) {
++		dev_info(&(i2c->adap.dev),
++				 "\n\n\n%s, Begin master xfer, want to transfer msg count is %d\n",
++				__func__, count);
++	}
++#endif
++
++	if ((!IS_ERR(i2c->clk)) && (!i2c->clk_always_enable))
++		clk_prepare_enable(i2c->clk);
++
++	i2c_writel(i2c, I2C_TAR, msg->addr);
++
++	for (i = 0; i < count; i++, msg++) {
++		enum msg_end_type end_type = MSG_END_STOP;
++		if (i < (count - 1)) {
++			if (msg[i + 1].flags & I2C_M_NOSTART) {
++				end_type = MSG_END_CONTINUE;	/* have no STOP and START */
++			} else {
++				end_type = MSG_END_REPEAT_START;	/* have no STOP but have RESTART */
++			}
++		}
++
++		reinit_completion(&i2c->complete);
++
++#ifdef CONFIG_I2C_DEBUG_INFO
++		if (i2c->debug > DEBUG_WARN)
++			dev_info(&(i2c->adap.dev),
++					"%s, Now transfer msg: %d\n", __func__, i);
++#endif
++		if (msg->flags & I2C_M_RD) {
++			ret = xfer_read(i2c, msg->buf, msg->len, end_type);
++		} else {
++			ret = xfer_write(i2c, msg->buf, msg->len, end_type);
++		}
++		if (ret < 0) {
++			i2c_ingenic_reset(i2c);
++			if ((!IS_ERR(i2c->clk)) && (!i2c->clk_always_enable))
++				clk_disable_unprepare(i2c->clk);
++			goto ERR;
++		}
++	}
++
++	if (i2c_disable_clk(i2c)) {
++		ret = -ETIMEDOUT;
++		goto ERR;
++	}
++
++#ifdef CONFIG_I2C_DEBUG_INFO
++	if (i2c->debug > DEBUG_WARN)
++		dev_info(&(i2c->adap.dev),
++				"%s, Transfer msg over\n\n\n", __func__);
++#endif
++
++ERR:
++	return ret ? : i;
++}
++
++static u32 i2c_ingenic_functionality(struct i2c_adapter *adap)
++{
++	unsigned int ret;
++	ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
++
++	return ret;
++}
++
++static const struct i2c_algorithm i2c_ingenic_algorithm = {
++	.master_xfer = i2c_ingenic_xfer,
++	.functionality = i2c_ingenic_functionality,
++};
++
++static int i2c_set_speed(struct i2c_ingenic *i2c, int rate)
++{
++	long dev_clk = clk_get_rate(i2c->clk);
++	long cnt_high = 0;	/* HIGH period count of the SCL clock */
++	long cnt_low = 0;	/* LOW period count of the SCL clock */
++	long setup_time = 0;
++	long hold_time = 0;
++	unsigned short tmp;
++
++	i2c->rate = rate;
++	if (i2c_ingenic_enable(i2c, 0))
++		dev_info(&(i2c->adap.dev), "i2c not disable\n");
++	if (rate <= 100000) {
++		tmp = 0x43 | (1 << 5);	/* standard speed mode */
++		i2c_writel(i2c, I2C_CTRL, tmp);
++	} else {
++		tmp = 0x45 | (1 << 5);	/* fast speed mode */
++		i2c_writel(i2c, I2C_CTRL, tmp);
++	}
++
++	/*         high
++	 *         ____     ____      ____      ____
++	 *  clk __|  | |___|    |____|    |____|    |___
++	 *           | | |
++	 *           | | |
++	 *           |_|_|     _________      ____
++	 * data    __/ | |\___/         \____/    \____
++	 *    setup->| |<|
++	 *           ->| |<-hold
++	 */
++
++	//setup_time = (10 000 000/(rate*4)) + 1;
++	setup_time = (dev_clk / (rate * 4));
++	if (setup_time > 1)
++		setup_time -= 1;
++	//hold_time =  (10000000/(rate*4)) - 1;
++	hold_time = (dev_clk / (rate * 4));
++
++	/*         high
++	 *         ____     ____
++	 *  clk __|    |___|    |____
++	 *              low
++	 *        |<--period--->|
++	 *
++	 */
++	cnt_high = dev_clk / (rate * 2);
++	cnt_low = dev_clk / (rate * 2);
++
++	dev_info(&(i2c->adap.dev), "set:%ld  hold:%ld dev=%ld h=%ld l=%ld\n",
++			setup_time, hold_time, dev_clk, cnt_high, cnt_low);
++	if (setup_time > 255)
++		setup_time = 255;
++	if (setup_time <= 0)
++		setup_time = 1;
++	if (hold_time > 0xFFFF)
++		hold_time = 0xFFFF;
++
++	if (rate <= 100000) {
++		i2c_writel(i2c, I2C_SHCNT, I2CSHCNT_ADJUST(cnt_high));
++		i2c_writel(i2c, I2C_SLCNT, I2CSLCNT_ADJUST(cnt_low));
++	} else {
++		i2c_writel(i2c, I2C_FHCNT, I2CFHCNT_ADJUST(cnt_high));
++		i2c_writel(i2c, I2C_FLCNT, I2CFLCNT_ADJUST(cnt_low));
++	}
++
++	i2c_writel(i2c, I2C_SDASU, setup_time & 0xff);
++	i2c_writel(i2c, I2C_SDAHD, hold_time);
++
++	return 0;
++}
++
++#ifndef CONFIG_I2C_INGENICV10_WAIT_MS
++#define DEF_INGENIC_I2C_WAIT_TIMEOUT_MS (1000)
++#else
++#define DEF_INGENIC_I2C_WAIT_TIMEOUT_MS (CONFIG_I2C_INGENICV10_WAIT_MS)
++#endif
++
++#define DEF_INGENIC_I2C_SPEED_HZ	(100000)
++static void ingenic_i2c_parse_dt(struct device_node *np, struct i2c_ingenic *i2c)
++{
++	u32 timeout, speed;
++	int id;
++
++	if (!of_property_read_u32(np, "timeout", &timeout))
++		i2c->timeout_ms = timeout;
++	else
++		i2c->timeout_ms = DEF_INGENIC_I2C_WAIT_TIMEOUT_MS;
++
++	if (!of_property_read_u32(np, "clock-frequency", &speed))
++		i2c->speed_hz = speed;
++	else
++		i2c->speed_hz = DEF_INGENIC_I2C_SPEED_HZ;
++
++	if ((id = of_alias_get_id(np, "i2c")) >= 0)
++		i2c->id = id;
++	else
++		i2c->id = -1;
++}
++
++
++static int i2c_ingenic_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	struct i2c_ingenic *i2c;
++	struct resource *res;
++	unsigned int reg_tmp;
++	char name[20];
++	int i2c_id;
++
++	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
++	if (!i2c)
++		return -ENOMEM;
++
++	i2c->dev = &pdev->dev;
++	if (!pdev->dev.of_node) {
++		i2c->timeout_ms = DEF_INGENIC_I2C_WAIT_TIMEOUT_MS;
++		i2c->speed_hz = DEF_INGENIC_I2C_SPEED_HZ;
++		i2c->id = pdev->id;
++		res = platform_get_resource(pdev, IORESOURCE_BUS, 0);
++		if (res)
++			i2c->speed_hz = res->start * 1000;
++	} else
++		ingenic_i2c_parse_dt(pdev->dev.of_node, i2c);
++
++	i2c->clk_always_enable = of_property_read_bool(pdev->dev.of_node, "clk-always-enable");
++
++	i2c->adap.owner = THIS_MODULE;
++	i2c->adap.algo = &i2c_ingenic_algorithm;
++	i2c->adap.retries = 5;
++	i2c->adap.timeout = 5;
++	i2c->adap.algo_data = i2c;
++	i2c->adap.dev.parent = &pdev->dev;
++	i2c->adap.nr = i2c->id;
++
++	i2c->adap.dev.of_node = pdev->dev.of_node;
++
++	i2c_id = i2c->id;
++	if (i2c_id >= 0)
++		sprintf(i2c->adap.name, "i2c%u", i2c->id);
++	else
++		sprintf(i2c->adap.name, "%s", dev_name(&pdev->dev));
++
++	sprintf(name, "gate_%s", i2c->adap.name);
++
++	i2c->clk = devm_clk_get(&pdev->dev, name);
++	if (!i2c->clk)
++		return -ENODEV;
++
++	if(clk_prepare(i2c->clk) < 0) {
++		dev_err(&pdev->dev, "failed to prepare for clk %s\n", __clk_get_name(i2c->clk));
++		return -ENODEV;
++	}
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res)
++		return -ENOENT;
++
++	i2c->iomem = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(i2c->iomem))
++		return PTR_ERR(i2c->iomem);
++
++	i2c->irq = platform_get_irq(pdev, 0);
++	if (i2c->irq < 0)
++		return i2c->irq;
++
++	ret = devm_request_irq(&pdev->dev, i2c->irq,
++			i2c_ingenic_irq, 0, i2c->adap.name, i2c);
++	if (ret)
++		return -ENODEV;
++
++
++	clk_enable(i2c->clk);
++
++	i2c_set_speed(i2c, i2c->speed_hz);
++
++#if 0
++	reg_tmp = i2c_readl(i2c, I2C_DC);
++	reg_tmp &= ~I2C_DC_STP;
++	i2c_writel(i2c, I2C_DC, reg_tmp);
++#endif
++
++	reg_tmp = i2c_readl(i2c, I2C_CTRL);
++#if defined(CONFIG_I2C_NON_RESTART_MODE)
++        reg_tmp &= ~I2C_CTRL_REST;
++#else
++        reg_tmp |= I2C_CTRL_REST;
++#endif
++	i2c_writel(i2c, I2C_CTRL, reg_tmp);
++
++	// for jgao WHY?
++	//  i2c_writel(i2c, I2C_FLT, 0xF);      /*set filter*/
++
++	i2c_writel(i2c, I2C_INTM, 0x0);
++
++	platform_set_drvdata(pdev, i2c);
++
++	i2c_ingenic_enable(i2c, 1);
++
++	if ((!IS_ERR(i2c->clk)) && (!i2c->clk_always_enable))
++		clk_disable_unprepare(i2c->clk);
++
++	init_completion(&i2c->complete);
++
++	ret = i2c_add_numbered_adapter(&i2c->adap);
++	if (ret < 0) {
++		dev_err(&pdev->dev, KERN_INFO"I2C: Failed to add bus\n");
++		if ((!IS_ERR(i2c->clk)) && (!i2c->clk_always_enable))
++			clk_disable_unprepare(i2c->clk);
++		return ret;
++	}
++
++#ifdef CONFIG_I2C_DEBUG_INFO
++	ret = create_debug_sysfs_interface(&pdev->dev);
++	if (ret < 0)
++		dev_err(&pdev->dev, "create debug sysfs interface failed\n");
++#endif
++	dev_info(&pdev->dev, "%s success.\n", __func__);
++	return 0;
++}
++
++static int i2c_ingenic_remove(struct platform_device *pdev)
++{
++	struct i2c_ingenic *i2c = platform_get_drvdata(pdev);
++	if ((!IS_ERR(i2c->clk)) && (!i2c->clk_always_enable))
++		clk_disable_unprepare(i2c->clk);
++	i2c_del_adapter(&i2c->adap);
++	return 0;
++}
++
++static int i2c_ingenic_suspend(struct platform_device *pdev, pm_message_t state)
++{
++
++	struct i2c_ingenic *i2c = platform_get_drvdata(pdev);
++
++	if ((!IS_ERR(i2c->clk)) && (!i2c->clk_always_enable))
++		if(__clk_is_enabled(i2c->clk))
++			clk_disable_unprepare(i2c->clk);
++
++	return 0;
++}
++
++static int i2c_ingenic_resume(struct platform_device *pdev)
++{
++	struct i2c_ingenic *i2c = platform_get_drvdata(pdev);
++	unsigned int reg_tmp;
++
++	if ((!IS_ERR(i2c->clk)) && (!i2c->clk_always_enable))
++		clk_prepare_enable(i2c->clk);
++
++	i2c_set_speed(i2c, i2c->speed_hz);
++	reg_tmp = i2c_readl(i2c, I2C_CTRL);
++#if defined(CONFIG_I2C_NON_RESTART_MODE)
++	reg_tmp &= ~I2C_CTRL_REST;
++#else
++	reg_tmp |= I2C_CTRL_REST;
++#endif
++	i2c_writel(i2c, I2C_CTRL, reg_tmp);
++	i2c_writel(i2c, I2C_INTM, 0x0);
++
++	i2c_ingenic_reset(i2c);
++
++	if ((!IS_ERR(i2c->clk)) && (!i2c->clk_always_enable))
++		clk_disable_unprepare(i2c->clk);
++
++	return 0;
++}
++
++static const struct of_device_id ingenic_i2c_dt_match[] = {
++	{ .compatible = "ingenic,i2c" },
++	{ .compatible = "ingenic,x2000-i2c" },
++	{ .compatible = "ingenic,x2500-i2c" },
++	{ .compatible = "ingenic,x1600-i2c" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ingenic_i2c_dt_match);
++
++static struct platform_driver i2c_ingenic_driver = {
++	.probe = i2c_ingenic_probe,
++	.remove = i2c_ingenic_remove,
++	.driver = {
++		.name = "ingenic-i2c",
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(ingenic_i2c_dt_match),
++	},
++	.suspend = i2c_ingenic_suspend,
++	.resume = i2c_ingenic_resume,
++};
++
++static int __init i2c_ingenic_init(void)
++{
++	return platform_driver_register(&i2c_ingenic_driver);
++}
++subsys_initcall(i2c_ingenic_init);
++
++static void __exit i2c_ingenic_exit(void)
++{
++	platform_driver_unregister(&i2c_ingenic_driver);
++}
++module_exit(i2c_ingenic_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("i2c driver for INGENIC SoCs");
+diff --git a/module_drivers/drivers/input/Makefile b/module_drivers/drivers/input/Makefile
+new file mode 100644
+index 000000000..035a93f92
+--- /dev/null
++++ b/module_drivers/drivers/input/Makefile
+@@ -0,0 +1 @@
++obj-y += touchscreen/
+diff --git a/module_drivers/drivers/input/touchscreen/Kconfig b/module_drivers/drivers/input/touchscreen/Kconfig
+new file mode 100644
+index 000000000..5271c1495
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/Kconfig
+@@ -0,0 +1,17 @@
++
++#source "module_drivers/drivers/input/touchscreen/cyttsp5/Kconfig"
++source "module_drivers/drivers/input/touchscreen/focaltech_touch/Kconfig"
++#source "module_drivers/drivers/input/touchscreen/focaltech_ft5x16_touch/Kconfig"
++source "module_drivers/drivers/input/touchscreen/hyn_touch/Kconfig"
++#source "module_drivers/drivers/input/touchscreen/chipone_touch/Kconfig"
++#source "module_drivers/drivers/input/touchscreen/msm8909w/Kconfig"
++source "module_drivers/drivers/input/touchscreen/gt9xx_touch/Kconfig"
++source "module_drivers/drivers/input/touchscreen/ft6236_touch/Kconfig"
++
++
++config TOUCHSCREEN_MXT336U
++      tristate "MicroChip MXT336U TouchScreen driver"
++      depends on I2C
++      default n
++      help
++        MicroChip MXT336U TouchScreen driver implemented by Ingenic for Robam.
+diff --git a/module_drivers/drivers/input/touchscreen/Makefile b/module_drivers/drivers/input/touchscreen/Makefile
+new file mode 100644
+index 000000000..718ee4847
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/Makefile
+@@ -0,0 +1,11 @@
++
++#obj-$(CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5)       += cyttsp5/
++obj-$(CONFIG_TOUCHSCREEN_FTS)		+= focaltech_touch/
++#obj-$(CONFIG_TOUCHSCREEN_FT5X16)		+= focaltech_ft5x16_touch/
++obj-$(CONFIG_TOUCHSCREEN_HYN)		+= hyn_touch/
++#obj-$(CONFIG_TOUCHSCREEN_CHIPONE)		+= chipone_touch/
++obj-$(CONFIG_TOUCHSCREEN_GT9XX)		+= gt9xx_touch/
++obj-$(CONFIG_TOUCHSCREEN_FT6236)		+= ft6236_touch/
++#obj-$(CONFIG_TOUCHSCREEN_MSM8909W)		+= msm8909w/
++
++obj-$(CONFIG_TOUCHSCREEN_MXT336U) += mxt_336u_ts.o
+diff --git a/module_drivers/drivers/input/touchscreen/focaltech_touch/Kconfig b/module_drivers/drivers/input/touchscreen/focaltech_touch/Kconfig
+new file mode 100644
+index 000000000..e2bf1085b
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/focaltech_touch/Kconfig
+@@ -0,0 +1,16 @@
++#
++# Focaltech Touchscreen driver configuration
++#
++
++config TOUCHSCREEN_FTS
++    bool "Focaltech Touchscreen"
++    default n
++    help
++      Say Y here if you have Focaltech touch panel.
++      If unsure, say N.
++
++config TOUCHSCREEN_FTS_DIRECTORY
++    string "Focaltech ts directory name"
++    default "focaltech_touch"
++    depends on TOUCHSCREEN_FTS
++
+diff --git a/module_drivers/drivers/input/touchscreen/focaltech_touch/Makefile b/module_drivers/drivers/input/touchscreen/focaltech_touch/Makefile
+new file mode 100644
+index 000000000..b0d546e92
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/focaltech_touch/Makefile
+@@ -0,0 +1,13 @@
++# Makefile for the focaltech touchscreen drivers.
++
++
++obj-$(CONFIG_TOUCHSCREEN_FTS)	+=  focaltech_core.o
++#obj-$(CONFIG_TOUCHSCREEN_FTS)	+=  focaltech_ex_fun.o
++#obj-$(CONFIG_TOUCHSCREEN_FTS)	+=  focaltech_ex_mode.o
++#obj-$(CONFIG_TOUCHSCREEN_FTS)	+=  focaltech_gesture.o
++#obj-$(CONFIG_TOUCHSCREEN_FTS)	+=  focaltech_esdcheck.o
++#obj-$(CONFIG_TOUCHSCREEN_FTS)   +=  focaltech_point_report_check.o
++
++obj-$(CONFIG_TOUCHSCREEN_FTS)   +=  focaltech_i2c.o
++#obj-$(CONFIG_TOUCHSCREEN_FTS)	+=  focaltech_flash.o
++#obj-$(CONFIG_TOUCHSCREEN_FTS)   +=  focaltech_flash/
+diff --git a/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_common.h b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_common.h
+new file mode 100644
+index 000000000..d636d97dc
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_common.h
+@@ -0,0 +1,166 @@
++/*
++ *
++ * FocalTech fts TouchScreen driver.
++ *
++ * Copyright (c) 2012-2019, Focaltech Ltd. All rights reserved.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++/*****************************************************************************
++*
++* File Name: focaltech_common.h
++*
++* Author: Focaltech Driver Team
++*
++* Created: 2016-08-16
++*
++* Abstract:
++*
++* Reference:
++*
++*****************************************************************************/
++
++#ifndef __LINUX_FOCALTECH_COMMON_H__
++#define __LINUX_FOCALTECH_COMMON_H__
++
++#include "focaltech_config.h"
++
++/*****************************************************************************
++* Macro definitions using #define
++*****************************************************************************/
++#define FTS_DRIVER_VERSION                  "Focaltech V3.1 20190807"
++
++#define BYTE_OFF_0(x)           (u8)((x) & 0xFF)
++#define BYTE_OFF_8(x)           (u8)(((x) >> 8) & 0xFF)
++#define BYTE_OFF_16(x)          (u8)(((x) >> 16) & 0xFF)
++#define BYTE_OFF_24(x)          (u8)(((x) >> 24) & 0xFF)
++#define FLAGBIT(x)              (0x00000001 << (x))
++#define FLAGBITS(x, y)          ((0xFFFFFFFF >> (32 - (y) - 1)) & (0xFFFFFFFF << (x)))
++
++#define FLAG_ICSERIALS_LEN      8
++#define FLAG_HID_BIT            10
++#define FLAG_IDC_BIT            11
++
++#define IC_SERIALS              (FTS_CHIP_TYPE & FLAGBITS(0, FLAG_ICSERIALS_LEN-1))
++#define IC_TO_SERIALS(x)        ((x) & FLAGBITS(0, FLAG_ICSERIALS_LEN-1))
++#define FTS_CHIP_IDC            ((FTS_CHIP_TYPE & FLAGBIT(FLAG_IDC_BIT)) == FLAGBIT(FLAG_IDC_BIT))
++#define FTS_HID_SUPPORTTED      ((FTS_CHIP_TYPE & FLAGBIT(FLAG_HID_BIT)) == FLAGBIT(FLAG_HID_BIT))
++
++#define FTS_CHIP_TYPE_MAPPING {{0x02, 0x54, 0x22, 0x54, 0x22, 0x00, 0x00, 0x54, 0x2C}, {0x02, 0x64, 0x26, 0x64, 0x26, 0x00, 0x00, 0x54, 0x2C}}
++
++#define FILE_NAME_LENGTH                    128
++#define ENABLE                              1
++#define DISABLE                             0
++#define VALID                               1
++#define INVALID                             0
++#define FTS_CMD_START1                      0x55
++#define FTS_CMD_START2                      0xAA
++#define FTS_CMD_START_DELAY                 12
++#define FTS_CMD_READ_ID                     0x90
++#define FTS_CMD_READ_ID_LEN                 4
++#define FTS_CMD_READ_ID_LEN_INCELL          1
++/*register address*/
++#define FTS_REG_INT_CNT                     0x8F
++#define FTS_REG_FLOW_WORK_CNT               0x91
++#define FTS_REG_WORKMODE                    0x00
++#define FTS_REG_WORKMODE_FACTORY_VALUE      0x40
++#define FTS_REG_WORKMODE_WORK_VALUE         0x00
++#define FTS_REG_ESDCHECK_DISABLE            0x8D
++#define FTS_REG_CHIP_ID                     0xA3
++#define FTS_REG_CHIP_ID2                    0x9F
++#define FTS_REG_POWER_MODE                  0xA5
++#define FTS_REG_POWER_MODE_SLEEP            0x03
++#define FTS_REG_FW_VER                      0xA6
++#define FTS_REG_VENDOR_ID                   0xA8
++#define FTS_REG_LCD_BUSY_NUM                0xAB
++#define FTS_REG_FACE_DEC_MODE_EN            0xB0
++#define FTS_REG_FACTORY_MODE_DETACH_FLAG    0xB4
++#define FTS_REG_FACE_DEC_MODE_STATUS        0x01
++#define FTS_REG_IDE_PARA_VER_ID             0xB5
++#define FTS_REG_IDE_PARA_STATUS             0xB6
++#define FTS_REG_GLOVE_MODE_EN               0xC0
++#define FTS_REG_COVER_MODE_EN               0xC1
++#define FTS_REG_CHARGER_MODE_EN             0x8B
++#define FTS_REG_GESTURE_EN                  0xD0
++#define FTS_REG_GESTURE_OUTPUT_ADDRESS      0xD3
++#define FTS_REG_MODULE_ID                   0xE3
++#define FTS_REG_LIC_VER                     0xE4
++#define FTS_REG_ESD_SATURATE                0xED
++
++#define FTS_SYSFS_ECHO_ON(buf)      (buf[0] == '1')
++#define FTS_SYSFS_ECHO_OFF(buf)     (buf[0] == '0')
++
++#define kfree_safe(pbuf) do {\
++    if (pbuf) {\
++        kfree(pbuf);\
++        pbuf = NULL;\
++    }\
++} while(0)
++
++/*****************************************************************************
++*  Alternative mode (When something goes wrong, the modules may be able to solve the problem.)
++*****************************************************************************/
++/*
++ * point report check
++ * default: disable
++ */
++#define FTS_POINT_REPORT_CHECK_EN               0
++
++/*****************************************************************************
++* Global variable or extern global variabls/functions
++*****************************************************************************/
++struct ft_chip_t {
++    u64 type;
++    u8 chip_idh;
++    u8 chip_idl;
++    u8 rom_idh;
++    u8 rom_idl;
++    u8 pb_idh;
++    u8 pb_idl;
++    u8 bl_idh;
++    u8 bl_idl;
++};
++
++struct ts_ic_info {
++    bool is_incell;
++    bool hid_supported;
++    struct ft_chip_t ids;
++};
++
++/*****************************************************************************
++* DEBUG function define here
++*****************************************************************************/
++#if FTS_DEBUG_EN
++#define FTS_DEBUG(fmt, args...) do { \
++    printk("[FTS_TS]%s:"fmt"\n", __func__, ##args); \
++} while (0)
++
++#define FTS_FUNC_ENTER() do { \
++    printk("[FTS_TS]%s: Enter\n", __func__); \
++} while (0)
++
++#define FTS_FUNC_EXIT() do { \
++    printk("[FTS_TS]%s: Exit(%d)\n", __func__, __LINE__); \
++} while (0)
++#else /* #if FTS_DEBUG_EN*/
++#define FTS_DEBUG(fmt, args...)
++#define FTS_FUNC_ENTER()
++#define FTS_FUNC_EXIT()
++#endif
++
++#define FTS_INFO(fmt, args...) do { \
++    printk(KERN_INFO "[FTS_TS/I]%s:"fmt"\n", __func__, ##args); \
++} while (0)
++
++#define FTS_ERROR(fmt, args...) do { \
++    printk(KERN_ERR "[FTS_TS/E]%s:"fmt"\n", __func__, ##args); \
++} while (0)
++#endif /* __LINUX_FOCALTECH_COMMON_H__ */
+diff --git a/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_config.h b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_config.h
+new file mode 100644
+index 000000000..7b12417a8
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_config.h
+@@ -0,0 +1,165 @@
++/*
++ *
++ * FocalTech TouchScreen driver.
++ *
++ * Copyright (c) 2012-2019, FocalTech Systems, Ltd., all rights reserved.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++/************************************************************************
++*
++* File Name: focaltech_config.h
++*
++* Author: Focaltech Driver Team
++*
++* Created: 2016-08-08
++*
++* Abstract: global configurations
++*
++* Version: v1.0
++*
++************************************************************************/
++#ifndef _LINUX_FOCLATECH_CONFIG_H_
++#define _LINUX_FOCLATECH_CONFIG_H_
++
++/**************************************************/
++/****** G: A, I: B, S: C, U: D  ******************/
++/****** chip type defines, do not modify *********/
++
++#define _FT7511             0x75110402
++#define _FT7661             0x76610402
++/*************************************************/
++
++/*
++ * choose your ic chip type of focaltech
++ */
++//#define FTS_CHIP_TYPE   _FT7511
++#define FTS_CHIP_TYPE   0x0402
++
++/******************* Enables *********************/
++/*********** 1 to enable, 0 to disable ***********/
++
++/*
++ * show debug log info
++ * enable it for debug, disable it for release
++ */
++#define FTS_DEBUG_EN                            0
++
++/*
++ * Linux MultiTouch Protocol
++ * 1: Protocol B(default), 0: Protocol A
++ */
++#if defined (CONFIG_STAGE_TL040WVS03CT) || defined (CONFIG_STAGE_ST7701S_RGB666)
++#define FTS_MT_PROTOCOL_B_EN                    0
++#else
++#define FTS_MT_PROTOCOL_B_EN                    1
++#endif /*CONFIG_PANEL_V12_TL040WVS03CT*/
++
++
++/*
++ * Report Pressure in multitouch
++ * 1:enable(default),0:disable
++*/
++#define FTS_REPORT_PRESSURE_EN                  1
++
++/*
++ * Gesture function enable
++ * default: disable
++ */
++#define FTS_GESTURE_EN                          0
++
++/*
++ * ESD check & protection
++ * default: disable
++ */
++#define FTS_ESDCHECK_EN                         0
++
++
++/*
++ * Pinctrl enable
++ * default: disable
++ */
++#define FTS_PINCTRL_EN                          0
++
++
++/*
++ * Customer power enable
++ * enable it when customer need control TP power
++ * default: disable
++ */
++#define FTS_POWER_SOURCE_CUST_EN                0
++
++#define FTS_EX_MODE_EN				0
++#define FTS_EX_FUNC_EN				0
++
++/****************************************************/
++
++/********************** Upgrade ****************************/
++/*
++ * auto upgrade
++ */
++#define FTS_AUTO_UPGRADE_EN                     0
++
++/*
++ * auto upgrade for lcd cfg
++ */
++#define FTS_AUTO_LIC_UPGRADE_EN                 0
++
++/*
++ * Numbers of modules support
++ */
++#define FTS_GET_MODULE_NUM                      0
++
++/*
++ * module_id: mean vendor_id generally, also maybe gpio or lcm_id...
++ * If means vendor_id, the FTS_MODULE_ID = PANEL_ID << 8 + VENDOR_ID
++ * FTS_GET_MODULE_NUM == 0/1, no check module id, you may ignore them
++ * FTS_GET_MODULE_NUM >= 2, compatible with FTS_MODULE2_ID
++ * FTS_GET_MODULE_NUM >= 3, compatible with FTS_MODULE3_ID
++ */
++#define FTS_MODULE_ID                          0x0000
++#define FTS_MODULE2_ID                         0x0000
++#define FTS_MODULE3_ID                         0x0000
++
++/*
++ * Need set the following when get firmware via firmware_request()
++ * For example: if module'vendor is tianma,
++ * #define FTS_MODULE_NAME                        "tianma"
++ * then file_name will be "focaltech_ts_fw_tianma"
++ * You should rename fw to "focaltech_ts_fw_tianma", and push it into
++ * etc/firmware or by customers
++ */
++#define FTS_MODULE_NAME                        ""
++#define FTS_MODULE2_NAME                       ""
++#define FTS_MODULE3_NAME                       ""
++
++/*
++ * FW.i file for auto upgrade, you must replace it with your own
++ * define your own fw_file, the sample one to be replaced is invalid
++ * NOTE: if FTS_GET_MODULE_NUM > 1, it's the fw corresponding with FTS_VENDOR_ID
++ */
++#define FTS_UPGRADE_FW_FILE                      "include/firmware/fw_sample.i"
++
++/*
++ * if FTS_GET_MODULE_NUM >= 2, fw corrsponding with FTS_VENDOR_ID2
++ * define your own fw_file, the sample one is invalid
++ */
++#define FTS_UPGRADE_FW2_FILE                     "include/firmware/fw_sample.i"
++
++/*
++ * if FTS_GET_MODULE_NUM >= 3, fw corrsponding with FTS_VENDOR_ID3
++ * define your own fw_file, the sample one is invalid
++ */
++#define FTS_UPGRADE_FW3_FILE                     "include/firmware/fw_sample.i"
++
++/*********************************************************/
++
++#endif /* _LINUX_FOCLATECH_CONFIG_H_ */
+diff --git a/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_core.c b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_core.c
+new file mode 100644
+index 000000000..6cd45dffb
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_core.c
+@@ -0,0 +1,1723 @@
++/*
++ *
++ * FocalTech TouchScreen driver.
++ *
++ * Copyright (c) 2012-2019, FocalTech Systems, Ltd., all rights reserved.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++/*****************************************************************************
++*
++* File Name: focaltech_core.c
++*
++* Author: Focaltech Driver Team
++*
++* Created: 2016-08-08
++*
++* Abstract: entrance for focaltech ts driver
++*
++* Version: V1.0
++*
++*****************************************************************************/
++
++/*****************************************************************************
++* Included header files
++*****************************************************************************/
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_gpio.h>
++#include <linux/of_irq.h>
++#if defined(CONFIG_FB)
++#include <linux/notifier.h>
++#include <linux/fb.h>
++#elif defined(CONFIG_HAS_EARLYSUSPEND)
++#include <linux/earlysuspend.h>
++#define FTS_SUSPEND_LEVEL 1     /* Early-suspend level */
++#endif
++#include "focaltech_core.h"
++
++/*****************************************************************************
++* Private constant and macro definitions using #define
++*****************************************************************************/
++#define FTS_DRIVER_NAME                     "fts_ts"
++#define INTERVAL_READ_REG                   200  /* unit:ms */
++#define TIMEOUT_READ_REG                    600 /* unit:ms */
++#if FTS_POWER_SOURCE_CUST_EN
++#define FTS_VTG_MIN_UV                      2800000
++#define FTS_VTG_MAX_UV                      3300000
++#define FTS_I2C_VTG_MIN_UV                  1800000
++#define FTS_I2C_VTG_MAX_UV                  1800000
++#endif
++
++/*****************************************************************************
++* Global variable or extern global variabls/functions
++*****************************************************************************/
++struct fts_ts_data *fts_data;
++
++/*****************************************************************************
++* Static function prototypes
++*****************************************************************************/
++static int fts_ts_suspend(struct device *dev);
++static int fts_ts_resume(struct device *dev);
++
++/*****************************************************************************
++*  Name: fts_wait_tp_to_valid
++*  Brief: Read chip id until TP FW become valid(Timeout: TIMEOUT_READ_REG),
++*         need call when reset/power on/resume...
++*  Input:
++*  Output:
++*  Return: return 0 if tp valid, otherwise return error code
++*****************************************************************************/
++int fts_wait_tp_to_valid(void)
++{
++    int ret = 0;
++    int cnt = 0;
++    u8 idh = 0;
++    u8 idl = 0;
++    u8 chip_idh = fts_data->ic_info.ids.chip_idh;
++    u8 chip_idl = fts_data->ic_info.ids.chip_idl;
++
++    do {
++        ret = fts_read_reg(FTS_REG_CHIP_ID, &idh);
++        ret = fts_read_reg(FTS_REG_CHIP_ID2, &idl);
++        if ((ret < 0) || (idh != chip_idh) || (idl != chip_idl)) {
++            FTS_DEBUG("TP Not Ready,ReadData:0x%02x%02x", idh, idl);
++        } else if ((idh == chip_idh) && (idl == chip_idl)) {
++            FTS_INFO("TP Ready,Device ID:0x%02x%02x", idh, idl);
++            return 0;
++        }
++        cnt++;
++        msleep(INTERVAL_READ_REG);
++    } while ((cnt * INTERVAL_READ_REG) < TIMEOUT_READ_REG);
++
++    return -EIO;
++}
++
++/*****************************************************************************
++*  Name: fts_tp_state_recovery
++*  Brief: Need execute this function when reset
++*  Input:
++*  Output:
++*  Return:
++*****************************************************************************/
++void fts_tp_state_recovery(struct fts_ts_data *ts_data)
++{
++    FTS_FUNC_ENTER();
++    /* wait tp stable */
++    fts_wait_tp_to_valid();
++    /* recover TP charger state 0x8B */
++    /* recover TP glove state 0xC0 */
++    /* recover TP cover state 0xC1 */
++#if FTS_EX_MODE_EN
++    fts_ex_mode_recovery(ts_data);
++#endif
++#if FTS_GESTURE_EN
++    /* recover TP gesture state 0xD0 */
++    fts_gesture_recovery(ts_data);
++    FTS_FUNC_EXIT();
++#endif
++}
++
++int fts_reset_proc(int hdelayms)
++{
++    FTS_DEBUG("tp reset");
++    gpio_direction_output(fts_data->pdata->reset_gpio, 0);
++    msleep(1);
++    gpio_direction_output(fts_data->pdata->reset_gpio, 1);
++    if (hdelayms) {
++        msleep(hdelayms);
++    }
++
++    return 0;
++}
++
++void fts_irq_disable(void)
++{
++    unsigned long irqflags;
++
++    FTS_FUNC_ENTER();
++    spin_lock_irqsave(&fts_data->irq_lock, irqflags);
++
++    if (!fts_data->irq_disabled) {
++        disable_irq_nosync(fts_data->irq);
++        fts_data->irq_disabled = true;
++    }
++
++    spin_unlock_irqrestore(&fts_data->irq_lock, irqflags);
++    FTS_FUNC_EXIT();
++}
++
++void fts_irq_enable(void)
++{
++    unsigned long irqflags = 0;
++
++    FTS_FUNC_ENTER();
++    spin_lock_irqsave(&fts_data->irq_lock, irqflags);
++
++    if (fts_data->irq_disabled) {
++        enable_irq(fts_data->irq);
++        fts_data->irq_disabled = false;
++    }
++
++    spin_unlock_irqrestore(&fts_data->irq_lock, irqflags);
++    FTS_FUNC_EXIT();
++}
++
++void fts_hid2std(void)
++{
++    int ret = 0;
++    u8 buf[3] = {0xEB, 0xAA, 0x09};
++
++    ret = fts_write(buf, 3);
++    if (ret < 0) {
++        FTS_ERROR("hid2std cmd write fail");
++    } else {
++        msleep(10);
++        buf[0] = buf[1] = buf[2] = 0;
++        ret = fts_read(NULL, 0, buf, 3);
++        if (ret < 0) {
++            FTS_ERROR("hid2std cmd read fail");
++        } else if ((0xEB == buf[0]) && (0xAA == buf[1]) && (0x08 == buf[2])) {
++            FTS_DEBUG("hidi2c change to stdi2c successful");
++        } else {
++            FTS_DEBUG("hidi2c change to stdi2c not support or fail");
++        }
++    }
++}
++
++static int fts_get_chip_types(
++    struct fts_ts_data *ts_data,
++    u8 id_h, u8 id_l, bool fw_valid)
++{
++    int i = 0;
++    struct ft_chip_t ctype[] = FTS_CHIP_TYPE_MAPPING;
++    u32 ctype_entries = sizeof(ctype) / sizeof(struct ft_chip_t);
++
++    if ((0x0 == id_h) || (0x0 == id_l)) {
++        FTS_ERROR("id_h/id_l is 0");
++        return -EINVAL;
++    }
++
++    FTS_DEBUG("verify id:0x%02x%02x", id_h, id_l);
++    for (i = 0; i < ctype_entries; i++) {
++        if (VALID == fw_valid) {
++            if ((id_h == ctype[i].chip_idh) && (id_l == ctype[i].chip_idl))
++                break;
++        } else {
++            if (((id_h == ctype[i].rom_idh) && (id_l == ctype[i].rom_idl))
++                || ((id_h == ctype[i].pb_idh) && (id_l == ctype[i].pb_idl))
++                || ((id_h == ctype[i].bl_idh) && (id_l == ctype[i].bl_idl)))
++                break;
++        }
++    }
++
++    if (i >= ctype_entries) {
++        return -ENODATA;
++    }
++
++    ts_data->ic_info.ids = ctype[i];
++    return 0;
++}
++
++static int fts_read_bootid(struct fts_ts_data *ts_data, u8 *id)
++{
++    int ret = 0;
++    u8 chip_id[2] = { 0 };
++    u8 id_cmd[4] = { 0 };
++    u32 id_cmd_len = 0;
++
++    id_cmd[0] = FTS_CMD_START1;
++    id_cmd[1] = FTS_CMD_START2;
++    ret = fts_write(id_cmd, 2);
++    if (ret < 0) {
++        FTS_ERROR("start cmd write fail");
++        return ret;
++    }
++
++    msleep(FTS_CMD_START_DELAY);
++    id_cmd[0] = FTS_CMD_READ_ID;
++    id_cmd[1] = id_cmd[2] = id_cmd[3] = 0x00;
++    if (ts_data->ic_info.is_incell)
++        id_cmd_len = FTS_CMD_READ_ID_LEN_INCELL;
++    else
++        id_cmd_len = FTS_CMD_READ_ID_LEN;
++    ret = fts_read(id_cmd, id_cmd_len, chip_id, 2);
++    if ((ret < 0) || (0x0 == chip_id[0]) || (0x0 == chip_id[1])) {
++        FTS_ERROR("read boot id fail,read:0x%02x%02x", chip_id[0], chip_id[1]);
++        return -EIO;
++    }
++
++    id[0] = chip_id[0];
++    id[1] = chip_id[1];
++    return 0;
++}
++
++/*****************************************************************************
++* Name: fts_get_ic_information
++* Brief: read chip id to get ic information, after run the function, driver w-
++*        ill know which IC is it.
++*        If cant get the ic information, maybe not focaltech's touch IC, need
++*        unregister the driver
++* Input:
++* Output:
++* Return: return 0 if get correct ic information, otherwise return error code
++*****************************************************************************/
++static int fts_get_ic_information(struct fts_ts_data *ts_data)
++{
++    int ret = 0;
++    int cnt = 0;
++    u8 chip_id[2] = { 0 };
++
++    ts_data->ic_info.is_incell = FTS_CHIP_IDC;
++    ts_data->ic_info.hid_supported = FTS_HID_SUPPORTTED;
++
++
++    do {
++        ret = fts_read_reg(FTS_REG_CHIP_ID, &chip_id[0]);
++        ret = fts_read_reg(FTS_REG_CHIP_ID2, &chip_id[1]);
++        if ((ret < 0) || (0x0 == chip_id[0]) || (0x0 == chip_id[1])) {
++            FTS_DEBUG("i2c read invalid, read:0x%02x%02x",
++                      chip_id[0], chip_id[1]);
++	    if (((cnt + 1) * INTERVAL_READ_REG) >= TIMEOUT_READ_REG)
++		    return ret;
++        } else {
++            ret = fts_get_chip_types(ts_data, chip_id[0], chip_id[1], VALID);
++            if (!ret)
++                break;
++            else
++                FTS_DEBUG("TP not ready, read:0x%02x%02x",
++                          chip_id[0], chip_id[1]);
++        }
++
++        cnt++;
++        msleep(INTERVAL_READ_REG);
++    } while ((cnt * INTERVAL_READ_REG) < TIMEOUT_READ_REG);
++
++    if ((cnt * INTERVAL_READ_REG) >= TIMEOUT_READ_REG) {
++        FTS_INFO("fw is invalid, need read boot id");
++        if (ts_data->ic_info.hid_supported) {
++            fts_hid2std();
++        }
++
++        ret = fts_read_bootid(ts_data, &chip_id[0]);
++        if (ret <  0) {
++            FTS_ERROR("read boot id fail");
++            return ret;
++        }
++
++        ret = fts_get_chip_types(ts_data, chip_id[0], chip_id[1], INVALID);
++        if (ret < 0) {
++            FTS_ERROR("can't get ic informaton");
++            return ret;
++        }
++    }
++
++    FTS_INFO("get ic information, chip id = 0x%02x%02x",
++             ts_data->ic_info.ids.chip_idh, ts_data->ic_info.ids.chip_idl);
++
++    return 0;
++}
++
++/*****************************************************************************
++*  Reprot related
++*****************************************************************************/
++static void fts_show_touch_buffer(u8 *data, int datalen)
++{
++    int i = 0;
++    int count = 0;
++    char *tmpbuf = NULL;
++
++    tmpbuf = kzalloc(1024, GFP_KERNEL);
++    if (!tmpbuf) {
++        FTS_ERROR("tmpbuf zalloc fail");
++        return;
++    }
++
++    for (i = 0; i < datalen; i++) {
++        count += snprintf(tmpbuf + count, 1024 - count, "%02X,", data[i]);
++        if (count >= 1024)
++            break;
++    }
++    FTS_DEBUG("point buffer:%s", tmpbuf);
++
++    if (tmpbuf) {
++        kfree(tmpbuf);
++        tmpbuf = NULL;
++    }
++}
++
++void fts_release_all_finger(void)
++{
++    struct input_dev *input_dev = fts_data->input_dev;
++#if FTS_MT_PROTOCOL_B_EN
++    u32 finger_count = 0;
++    u32 max_touches = fts_data->pdata->max_touch_number;
++#endif
++
++    FTS_FUNC_ENTER();
++    mutex_lock(&fts_data->report_mutex);
++#if FTS_MT_PROTOCOL_B_EN
++    for (finger_count = 0; finger_count < max_touches; finger_count++) {
++        input_mt_slot(input_dev, finger_count);
++        input_mt_report_slot_state(input_dev, MT_TOOL_FINGER, false);
++    }
++#else
++    input_mt_sync(input_dev);
++#endif
++    input_report_key(input_dev, BTN_TOUCH, 0);
++    input_sync(input_dev);
++
++    fts_data->touchs = 0;
++    fts_data->key_state = 0;
++    mutex_unlock(&fts_data->report_mutex);
++    FTS_FUNC_EXIT();
++}
++
++/*****************************************************************************
++* Name: fts_input_report_key
++* Brief: process key events,need report key-event if key enable.
++*        if point's coordinate is in (x_dim-50,y_dim-50) ~ (x_dim+50,y_dim+50),
++*        need report it to key event.
++*        x_dim: parse from dts, means key x_coordinate, dimension:+-50
++*        y_dim: parse from dts, means key y_coordinate, dimension:+-50
++* Input:
++* Output:
++* Return: return 0 if it's key event, otherwise return error code
++*****************************************************************************/
++static int fts_input_report_key(struct fts_ts_data *data, int index)
++{
++    int i = 0;
++    int x = data->events[index].x;
++    int y = data->events[index].y;
++    int *x_dim = &data->pdata->key_x_coords[0];
++    int *y_dim = &data->pdata->key_y_coords[0];
++
++    if (!data->pdata->have_key) {
++        return -EINVAL;
++    }
++    for (i = 0; i < data->pdata->key_number; i++) {
++        if ((x >= x_dim[i] - FTS_KEY_DIM) && (x <= x_dim[i] + FTS_KEY_DIM) &&
++            (y >= y_dim[i] - FTS_KEY_DIM) && (y <= y_dim[i] + FTS_KEY_DIM)) {
++            if (EVENT_DOWN(data->events[index].flag)
++                && !(data->key_state & (1 << i))) {
++                input_report_key(data->input_dev, data->pdata->keys[i], 1);
++                data->key_state |= (1 << i);
++                FTS_DEBUG("Key%d(%d,%d) DOWN!", i, x, y);
++            } else if (EVENT_UP(data->events[index].flag)
++                       && (data->key_state & (1 << i))) {
++                input_report_key(data->input_dev, data->pdata->keys[i], 0);
++                data->key_state &= ~(1 << i);
++                FTS_DEBUG("Key%d(%d,%d) Up!", i, x, y);
++            }
++            return 0;
++        }
++    }
++    return -EINVAL;
++}
++
++#if FTS_MT_PROTOCOL_B_EN
++static int fts_input_report_b(struct fts_ts_data *data)
++{
++    int i = 0;
++    int uppoint = 0;
++    int touchs = 0;
++    bool va_reported = false;
++    u32 max_touch_num = data->pdata->max_touch_number;
++    struct ts_event *events = data->events;
++
++    for (i = 0; i < data->touch_point; i++) {
++        if (fts_input_report_key(data, i) == 0) {
++            continue;
++        }
++
++        va_reported = true;
++        input_mt_slot(data->input_dev, events[i].id);
++
++        if (EVENT_DOWN(events[i].flag)) {
++            input_mt_report_slot_state(data->input_dev, MT_TOOL_FINGER, true);
++
++#if FTS_REPORT_PRESSURE_EN
++            if (events[i].p <= 0) {
++                events[i].p = 0x3f;
++            }
++            input_report_abs(data->input_dev, ABS_MT_PRESSURE, events[i].p);
++#endif
++            if (events[i].area <= 0) {
++                events[i].area = 0x09;
++            }
++            input_report_abs(data->input_dev, ABS_MT_TOUCH_MAJOR, events[i].area);
++            input_report_abs(data->input_dev, ABS_MT_POSITION_X, events[i].x);
++            input_report_abs(data->input_dev, ABS_MT_POSITION_Y, events[i].y);
++
++            touchs |= BIT(events[i].id);
++            data->touchs |= BIT(events[i].id);
++
++            if ((data->log_level >= 2) ||
++                ((1 == data->log_level) && (FTS_TOUCH_DOWN == events[i].flag))) {
++                FTS_DEBUG("[B]P%d(%d, %d)[p:%d,tm:%d] DOWN!",
++                          events[i].id,
++                          events[i].x, events[i].y,
++                          events[i].p, events[i].area);
++            }
++        } else {
++            uppoint++;
++            input_mt_report_slot_state(data->input_dev, MT_TOOL_FINGER, false);
++            data->touchs &= ~BIT(events[i].id);
++            if (data->log_level >= 1) {
++                FTS_DEBUG("[B]P%d UP!", events[i].id);
++            }
++        }
++    }
++
++    if (unlikely(data->touchs ^ touchs)) {
++        for (i = 0; i < max_touch_num; i++)  {
++            if (BIT(i) & (data->touchs ^ touchs)) {
++                if (data->log_level >= 1) {
++                    FTS_DEBUG("[B]P%d UP!", i);
++                }
++                va_reported = true;
++                input_mt_slot(data->input_dev, i);
++                input_mt_report_slot_state(data->input_dev, MT_TOOL_FINGER, false);
++            }
++        }
++    }
++    data->touchs = touchs;
++
++    if (va_reported) {
++        /* touchs==0, there's no point but key */
++        if (EVENT_NO_DOWN(data) || (!touchs)) {
++            if (data->log_level >= 1) {
++                FTS_DEBUG("[B]Points All Up!");
++            }
++            input_report_key(data->input_dev, BTN_TOUCH, 0);
++        } else {
++            input_report_key(data->input_dev, BTN_TOUCH, 1);
++        }
++    }
++
++    input_sync(data->input_dev);
++    return 0;
++}
++
++#else
++static int fts_input_report_a(struct fts_ts_data *data)
++{
++    int i = 0;
++    int touchs = 0;
++    bool va_reported = false;
++    struct ts_event *events = data->events;
++
++    for (i = 0; i < data->touch_point; i++) {
++        if (fts_input_report_key(data, i) == 0) {
++            continue;
++        }
++
++        va_reported = true;
++        if (EVENT_DOWN(events[i].flag)) {
++            input_report_abs(data->input_dev, ABS_MT_TRACKING_ID, events[i].id);
++#if FTS_REPORT_PRESSURE_EN
++            if (events[i].p <= 0) {
++                events[i].p = 0x3f;
++            }
++            input_report_abs(data->input_dev, ABS_MT_PRESSURE, events[i].p);
++#endif
++            if (events[i].area <= 0) {
++                events[i].area = 0x09;
++            }
++            input_report_abs(data->input_dev, ABS_MT_TOUCH_MAJOR, events[i].area);
++
++            input_report_abs(data->input_dev, ABS_MT_POSITION_X, events[i].x);
++            input_report_abs(data->input_dev, ABS_MT_POSITION_Y, events[i].y);
++
++            input_mt_sync(data->input_dev);
++
++            if ((data->log_level >= 2) ||
++                ((1 == data->log_level) && (FTS_TOUCH_DOWN == events[i].flag))) {
++                FTS_DEBUG("[A]P%d(%d, %d)[p:%d,tm:%d] DOWN!",
++                          events[i].id,
++                          events[i].x, events[i].y,
++                          events[i].p, events[i].area);
++            }
++            touchs++;
++        }
++    }
++
++    /* last point down, current no point but key */
++    if (data->touchs && !touchs) {
++        va_reported = true;
++    }
++    data->touchs = touchs;
++
++    if (va_reported) {
++        if (EVENT_NO_DOWN(data)) {
++            if (data->log_level >= 1) {
++                FTS_DEBUG("[A]Points All Up!");
++            }
++            input_report_key(data->input_dev, BTN_TOUCH, 0);
++            input_mt_sync(data->input_dev);
++        } else {
++            input_report_key(data->input_dev, BTN_TOUCH, 1);
++        }
++    }
++
++    input_sync(data->input_dev);
++    return 0;
++}
++#endif
++
++static int fts_read_touchdata(struct fts_ts_data *data)
++{
++    int ret = 0;
++    u8 *buf = data->point_buf;
++
++    memset(buf, 0xFF, data->pnt_buf_size);
++    buf[0] = 0x01;
++
++
++#if FTS_GESTURE_EN
++    if (data->gesture_mode) {
++        if (0 == fts_gesture_readdata(data, NULL)) {
++            FTS_INFO("succuss to get gesture data in irq handler");
++            return 1;
++        }
++    }
++#endif
++
++    ret = fts_read(buf, 1, buf + 1, data->pnt_buf_size - 1);
++    if (ret < 0) {
++        FTS_ERROR("read touchdata failed, ret:%d", ret);
++        return ret;
++    }
++
++    if (data->log_level >= 3) {
++        fts_show_touch_buffer(buf, data->pnt_buf_size);
++    }
++
++    return 0;
++}
++
++static int fts_read_parse_touchdata(struct fts_ts_data *data)
++{
++    int ret = 0;
++    int i = 0;
++    u8 pointid = 0;
++    int base = 0;
++    struct ts_event *events = data->events;
++    int max_touch_num = data->pdata->max_touch_number;
++    u8 *buf = data->point_buf;
++
++    ret = fts_read_touchdata(data);
++    if (ret) {
++        return ret;
++    }
++
++    data->point_num = buf[FTS_TOUCH_POINT_NUM] & 0x0F;
++    data->touch_point = 0;
++
++    if (data->ic_info.is_incell) {
++        if ((data->point_num == 0x0F) && (buf[2] == 0xFF) && (buf[3] == 0xFF)
++            && (buf[4] == 0xFF) && (buf[5] == 0xFF) && (buf[6] == 0xFF)) {
++            FTS_DEBUG("touch buff is 0xff, need recovery state");
++            fts_release_all_finger();
++            fts_tp_state_recovery(data);
++            return -EIO;
++        }
++    }
++
++    if (data->point_num > max_touch_num) {
++        FTS_INFO("invalid point_num(%d)", data->point_num);
++        return -EIO;
++    }
++
++    for (i = 0; i < max_touch_num; i++) {
++        base = FTS_ONE_TCH_LEN * i;
++        pointid = (buf[FTS_TOUCH_ID_POS + base]) >> 4;
++        if (pointid >= FTS_MAX_ID)
++            break;
++        else if (pointid >= max_touch_num) {
++            FTS_ERROR("ID(%d) beyond max_touch_number", pointid);
++            return -EINVAL;
++        }
++
++        data->touch_point++;
++        events[i].x = ((buf[FTS_TOUCH_X_H_POS + base] & 0x0F) << 8) +
++                      (buf[FTS_TOUCH_X_L_POS + base] & 0xFF);
++        events[i].y = ((buf[FTS_TOUCH_Y_H_POS + base] & 0x0F) << 8) +
++                      (buf[FTS_TOUCH_Y_L_POS + base] & 0xFF);
++        events[i].flag = buf[FTS_TOUCH_EVENT_POS + base] >> 6;
++        events[i].id = buf[FTS_TOUCH_ID_POS + base] >> 4;
++        events[i].area = buf[FTS_TOUCH_AREA_POS + base] >> 4;
++        events[i].p =  buf[FTS_TOUCH_PRE_POS + base];
++
++        if (EVENT_DOWN(events[i].flag) && (data->point_num == 0)) {
++            FTS_INFO("abnormal touch data from fw");
++            return -EIO;
++        }
++    }
++
++    if (data->touch_point == 0) {
++        FTS_INFO("no touch point information");
++        return -EIO;
++    }
++
++    return 0;
++}
++
++static void fts_irq_read_report(void)
++{
++    int ret = 0;
++    struct fts_ts_data *ts_data = fts_data;
++
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_set_intr(1);
++#endif
++
++#if FTS_POINT_REPORT_CHECK_EN
++    fts_prc_queue_work(ts_data);
++#endif
++
++    ret = fts_read_parse_touchdata(ts_data);
++    if (ret == 0) {
++        mutex_lock(&ts_data->report_mutex);
++#if FTS_MT_PROTOCOL_B_EN
++        fts_input_report_b(ts_data);
++#else
++        fts_input_report_a(ts_data);
++#endif
++        mutex_unlock(&ts_data->report_mutex);
++    }
++
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_set_intr(0);
++#endif
++}
++
++static irqreturn_t fts_irq_handler(int irq, void *data)
++{
++    fts_irq_read_report();
++    return IRQ_HANDLED;
++}
++
++static int fts_irq_registration(struct fts_ts_data *ts_data)
++{
++    int ret = 0;
++    struct fts_ts_platform_data *pdata = ts_data->pdata;
++
++    ts_data->irq = gpio_to_irq(pdata->irq_gpio);
++    pdata->irq_gpio_flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
++    FTS_INFO("irq:%d, flag:%x", ts_data->irq, pdata->irq_gpio_flags);
++    ret = request_threaded_irq(ts_data->irq, NULL, fts_irq_handler,
++                               pdata->irq_gpio_flags,
++                               FTS_DRIVER_NAME, ts_data);
++
++    return ret;
++}
++
++static int fts_input_init(struct fts_ts_data *ts_data)
++{
++    int ret = 0;
++    int key_num = 0;
++    struct fts_ts_platform_data *pdata = ts_data->pdata;
++    struct input_dev *input_dev;
++
++    FTS_FUNC_ENTER();
++    input_dev = input_allocate_device();
++    if (!input_dev) {
++        FTS_ERROR("Failed to allocate memory for input device");
++        return -ENOMEM;
++    }
++
++    /* Init and register Input device */
++    input_dev->name = FTS_DRIVER_NAME;
++
++    input_dev->id.bustype = BUS_I2C;
++    input_dev->dev.parent = ts_data->dev;
++
++    input_set_drvdata(input_dev, ts_data);
++
++    __set_bit(EV_SYN, input_dev->evbit);
++    __set_bit(EV_ABS, input_dev->evbit);
++    __set_bit(EV_KEY, input_dev->evbit);
++    __set_bit(BTN_TOUCH, input_dev->keybit);
++    __set_bit(INPUT_PROP_DIRECT, input_dev->propbit);
++
++    if (pdata->have_key) {
++        FTS_INFO("set key capabilities");
++        for (key_num = 0; key_num < pdata->key_number; key_num++)
++            input_set_capability(input_dev, EV_KEY, pdata->keys[key_num]);
++    }
++
++#if FTS_MT_PROTOCOL_B_EN
++    input_mt_init_slots(input_dev, pdata->max_touch_number, INPUT_MT_DIRECT);
++#else
++    input_set_abs_params(input_dev, ABS_MT_TRACKING_ID, 0, 0x0F, 0, 0);
++#endif
++    input_set_abs_params(input_dev, ABS_MT_POSITION_X, pdata->x_min, pdata->x_max, 0, 0);
++    input_set_abs_params(input_dev, ABS_MT_POSITION_Y, pdata->y_min, pdata->y_max, 0, 0);
++    input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR, 0, 0xFF, 0, 0);
++#if FTS_REPORT_PRESSURE_EN
++    input_set_abs_params(input_dev, ABS_MT_PRESSURE, 0, 0xFF, 0, 0);
++#endif
++
++    ret = input_register_device(input_dev);
++    if (ret) {
++        FTS_ERROR("Input device registration failed");
++        input_set_drvdata(input_dev, NULL);
++        input_free_device(input_dev);
++        input_dev = NULL;
++        return ret;
++    }
++
++    ts_data->input_dev = input_dev;
++
++    FTS_FUNC_EXIT();
++    return 0;
++}
++
++static int fts_report_buffer_init(struct fts_ts_data *ts_data)
++{
++    int point_num = 0;
++    int events_num = 0;
++
++
++    point_num = ts_data->pdata->max_touch_number;
++    ts_data->pnt_buf_size = point_num * FTS_ONE_TCH_LEN + 3;
++    ts_data->point_buf = (u8 *)kzalloc(ts_data->pnt_buf_size + 1, GFP_KERNEL);
++    if (!ts_data->point_buf) {
++        FTS_ERROR("failed to alloc memory for point buf");
++        return -ENOMEM;
++    }
++
++    events_num = point_num * sizeof(struct ts_event);
++    ts_data->events = (struct ts_event *)kzalloc(events_num, GFP_KERNEL);
++    if (!ts_data->events) {
++        FTS_ERROR("failed to alloc memory for point events");
++        kfree_safe(ts_data->point_buf);
++        return -ENOMEM;
++    }
++
++    return 0;
++}
++
++#if FTS_POWER_SOURCE_CUST_EN
++/*****************************************************************************
++* Power Control
++*****************************************************************************/
++#if FTS_PINCTRL_EN
++static int fts_pinctrl_init(struct fts_ts_data *ts)
++{
++    int ret = 0;
++
++    ts->pinctrl = devm_pinctrl_get(ts->dev);
++    if (IS_ERR_OR_NULL(ts->pinctrl)) {
++        FTS_ERROR("Failed to get pinctrl, please check dts");
++        ret = PTR_ERR(ts->pinctrl);
++        goto err_pinctrl_get;
++    }
++
++    ts->pins_active = pinctrl_lookup_state(ts->pinctrl, "pmx_ts_active");
++    if (IS_ERR_OR_NULL(ts->pins_active)) {
++        FTS_ERROR("Pin state[active] not found");
++        ret = PTR_ERR(ts->pins_active);
++        goto err_pinctrl_lookup;
++    }
++
++    ts->pins_suspend = pinctrl_lookup_state(ts->pinctrl, "pmx_ts_suspend");
++    if (IS_ERR_OR_NULL(ts->pins_suspend)) {
++        FTS_ERROR("Pin state[suspend] not found");
++        ret = PTR_ERR(ts->pins_suspend);
++        goto err_pinctrl_lookup;
++    }
++
++    ts->pins_release = pinctrl_lookup_state(ts->pinctrl, "pmx_ts_release");
++    if (IS_ERR_OR_NULL(ts->pins_release)) {
++        FTS_ERROR("Pin state[release] not found");
++        ret = PTR_ERR(ts->pins_release);
++    }
++
++    return 0;
++err_pinctrl_lookup:
++    if (ts->pinctrl) {
++        devm_pinctrl_put(ts->pinctrl);
++    }
++err_pinctrl_get:
++    ts->pinctrl = NULL;
++    ts->pins_release = NULL;
++    ts->pins_suspend = NULL;
++    ts->pins_active = NULL;
++    return ret;
++}
++
++static int fts_pinctrl_select_normal(struct fts_ts_data *ts)
++{
++    int ret = 0;
++
++    if (ts->pinctrl && ts->pins_active) {
++        ret = pinctrl_select_state(ts->pinctrl, ts->pins_active);
++        if (ret < 0) {
++            FTS_ERROR("Set normal pin state error:%d", ret);
++        }
++    }
++
++    return ret;
++}
++
++static int fts_pinctrl_select_suspend(struct fts_ts_data *ts)
++{
++    int ret = 0;
++
++    if (ts->pinctrl && ts->pins_suspend) {
++        ret = pinctrl_select_state(ts->pinctrl, ts->pins_suspend);
++        if (ret < 0) {
++            FTS_ERROR("Set suspend pin state error:%d", ret);
++        }
++    }
++
++    return ret;
++}
++
++static int fts_pinctrl_select_release(struct fts_ts_data *ts)
++{
++    int ret = 0;
++
++    if (ts->pinctrl) {
++        if (IS_ERR_OR_NULL(ts->pins_release)) {
++            devm_pinctrl_put(ts->pinctrl);
++            ts->pinctrl = NULL;
++        } else {
++            ret = pinctrl_select_state(ts->pinctrl, ts->pins_release);
++            if (ret < 0)
++                FTS_ERROR("Set gesture pin state error:%d", ret);
++        }
++    }
++
++    return ret;
++}
++#endif /* FTS_PINCTRL_EN */
++
++static int fts_power_source_ctrl(struct fts_ts_data *ts_data, int enable)
++{
++    int ret = 0;
++
++    if (IS_ERR_OR_NULL(ts_data->vdd)) {
++        FTS_ERROR("vdd is invalid");
++        return -EINVAL;
++    }
++
++    FTS_FUNC_ENTER();
++    if (enable) {
++        if (ts_data->power_disabled) {
++            FTS_DEBUG("regulator enable !");
++            gpio_direction_output(ts_data->pdata->reset_gpio, 0);
++            msleep(1);
++            ret = regulator_enable(ts_data->vdd);
++            if (ret) {
++                FTS_ERROR("enable vdd regulator failed,ret=%d", ret);
++            }
++
++            if (!IS_ERR_OR_NULL(ts_data->vcc_i2c)) {
++                ret = regulator_enable(ts_data->vcc_i2c);
++                if (ret) {
++                    FTS_ERROR("enable vcc_i2c regulator failed,ret=%d", ret);
++                }
++            }
++            ts_data->power_disabled = false;
++        }
++    } else {
++        if (!ts_data->power_disabled) {
++            FTS_DEBUG("regulator disable !");
++            gpio_direction_output(ts_data->pdata->reset_gpio, 0);
++            msleep(1);
++            ret = regulator_disable(ts_data->vdd);
++            if (ret) {
++                FTS_ERROR("disable vdd regulator failed,ret=%d", ret);
++            }
++            if (!IS_ERR_OR_NULL(ts_data->vcc_i2c)) {
++                ret = regulator_disable(ts_data->vcc_i2c);
++                if (ret) {
++                    FTS_ERROR("disable vcc_i2c regulator failed,ret=%d", ret);
++                }
++            }
++            ts_data->power_disabled = true;
++        }
++    }
++
++    FTS_FUNC_EXIT();
++    return ret;
++}
++
++/*****************************************************************************
++* Name: fts_power_source_init
++* Brief: Init regulator power:vdd/vcc_io(if have), generally, no vcc_io
++*        vdd---->vdd-supply in dts, kernel will auto add "-supply" to parse
++*        Must be call after fts_gpio_configure() execute,because this function
++*        will operate reset-gpio which request gpio in fts_gpio_configure()
++* Input:
++* Output:
++* Return: return 0 if init power successfully, otherwise return error code
++*****************************************************************************/
++static int fts_power_source_init(struct fts_ts_data *ts_data)
++{
++    int ret = 0;
++
++    FTS_FUNC_ENTER();
++    ts_data->vdd = regulator_get(ts_data->dev, "vdd");
++    if (IS_ERR_OR_NULL(ts_data->vdd)) {
++        ret = PTR_ERR(ts_data->vdd);
++        FTS_ERROR("get vdd regulator failed,ret=%d", ret);
++        return ret;
++    }
++
++    if (regulator_count_voltages(ts_data->vdd) > 0) {
++        ret = regulator_set_voltage(ts_data->vdd, FTS_VTG_MIN_UV,
++                                    FTS_VTG_MAX_UV);
++        if (ret) {
++            FTS_ERROR("vdd regulator set_vtg failed ret=%d", ret);
++            regulator_put(ts_data->vdd);
++            return ret;
++        }
++    }
++
++    ts_data->vcc_i2c = regulator_get(ts_data->dev, "vcc_i2c");
++    if (!IS_ERR_OR_NULL(ts_data->vcc_i2c)) {
++        if (regulator_count_voltages(ts_data->vcc_i2c) > 0) {
++            ret = regulator_set_voltage(ts_data->vcc_i2c,
++                                        FTS_I2C_VTG_MIN_UV,
++                                        FTS_I2C_VTG_MAX_UV);
++            if (ret) {
++                FTS_ERROR("vcc_i2c regulator set_vtg failed,ret=%d", ret);
++                regulator_put(ts_data->vcc_i2c);
++            }
++        }
++    }
++
++#if FTS_PINCTRL_EN
++    fts_pinctrl_init(ts_data);
++    fts_pinctrl_select_normal(ts_data);
++#endif
++
++    ts_data->power_disabled = true;
++    ret = fts_power_source_ctrl(ts_data, ENABLE);
++    if (ret) {
++        FTS_ERROR("fail to enable power(regulator)");
++    }
++
++    FTS_FUNC_EXIT();
++    return ret;
++}
++
++static int fts_power_source_exit(struct fts_ts_data *ts_data)
++{
++#if FTS_PINCTRL_EN
++    fts_pinctrl_select_release(ts_data);
++#endif
++
++    fts_power_source_ctrl(ts_data, DISABLE);
++
++    if (!IS_ERR_OR_NULL(ts_data->vdd)) {
++        if (regulator_count_voltages(ts_data->vdd) > 0)
++            regulator_set_voltage(ts_data->vdd, 0, FTS_VTG_MAX_UV);
++        regulator_put(ts_data->vdd);
++    }
++
++    if (!IS_ERR_OR_NULL(ts_data->vcc_i2c)) {
++        if (regulator_count_voltages(ts_data->vcc_i2c) > 0)
++            regulator_set_voltage(ts_data->vcc_i2c, 0, FTS_I2C_VTG_MAX_UV);
++        regulator_put(ts_data->vcc_i2c);
++    }
++
++    return 0;
++}
++
++static int fts_power_source_suspend(struct fts_ts_data *ts_data)
++{
++    int ret = 0;
++
++#if FTS_PINCTRL_EN
++    fts_pinctrl_select_suspend(ts_data);
++#endif
++
++    ret = fts_power_source_ctrl(ts_data, DISABLE);
++    if (ret < 0) {
++        FTS_ERROR("power off fail, ret=%d", ret);
++    }
++
++    return ret;
++}
++
++static int fts_power_source_resume(struct fts_ts_data *ts_data)
++{
++    int ret = 0;
++
++#if FTS_PINCTRL_EN
++    fts_pinctrl_select_normal(ts_data);
++#endif
++
++    ret = fts_power_source_ctrl(ts_data, ENABLE);
++    if (ret < 0) {
++        FTS_ERROR("power on fail, ret=%d", ret);
++    }
++
++    return ret;
++}
++#endif /* FTS_POWER_SOURCE_CUST_EN */
++
++static int fts_gpio_configure(struct fts_ts_data *data)
++{
++    int ret = 0;
++
++    FTS_FUNC_ENTER();
++    /* request irq gpio */
++    if (gpio_is_valid(data->pdata->irq_gpio)) {
++        ret = gpio_request(data->pdata->irq_gpio, "fts_irq_gpio");
++        if (ret) {
++            FTS_ERROR("[GPIO]irq gpio request failed");
++            goto err_irq_gpio_req;
++        }
++
++        ret = gpio_direction_input(data->pdata->irq_gpio);
++        if (ret) {
++            FTS_ERROR("[GPIO]set_direction for irq gpio failed");
++            goto err_irq_gpio_dir;
++        }
++    }
++
++    /* request reset gpio */
++    if (gpio_is_valid(data->pdata->reset_gpio)) {
++        ret = gpio_request(data->pdata->reset_gpio, "fts_reset_gpio");
++        if (ret) {
++            FTS_ERROR("[GPIO]reset gpio request failed");
++            goto err_irq_gpio_dir;
++        }
++
++        ret = gpio_direction_output(data->pdata->reset_gpio, 1);
++        if (ret) {
++            FTS_ERROR("[GPIO]set_direction for reset gpio failed");
++            goto err_reset_gpio_dir;
++        }
++    }
++
++    FTS_FUNC_EXIT();
++    return 0;
++
++err_reset_gpio_dir:
++    if (gpio_is_valid(data->pdata->reset_gpio))
++        gpio_free(data->pdata->reset_gpio);
++err_irq_gpio_dir:
++    if (gpio_is_valid(data->pdata->irq_gpio))
++        gpio_free(data->pdata->irq_gpio);
++err_irq_gpio_req:
++    FTS_FUNC_EXIT();
++    return ret;
++}
++
++static int fts_get_dt_coords(struct device *dev, char *name,
++                             struct fts_ts_platform_data *pdata)
++{
++    int ret = 0;
++    u32 coords[FTS_COORDS_ARR_SIZE] = { 0 };
++    struct property *prop;
++    struct device_node *np = dev->of_node;
++    int coords_size;
++
++    prop = of_find_property(np, name, NULL);
++    if (!prop)
++        return -EINVAL;
++    if (!prop->value)
++        return -ENODATA;
++
++    coords_size = prop->length / sizeof(u32);
++    if (coords_size != FTS_COORDS_ARR_SIZE) {
++        FTS_ERROR("invalid:%s, size:%d", name, coords_size);
++        return -EINVAL;
++    }
++
++    ret = of_property_read_u32_array(np, name, coords, coords_size);
++    if (ret < 0) {
++        FTS_ERROR("Unable to read %s, please check dts", name);
++        pdata->x_min = FTS_X_MIN_DISPLAY_DEFAULT;
++        pdata->y_min = FTS_Y_MIN_DISPLAY_DEFAULT;
++        pdata->x_max = FTS_X_MAX_DISPLAY_DEFAULT;
++        pdata->y_max = FTS_Y_MAX_DISPLAY_DEFAULT;
++        return -ENODATA;
++    } else {
++        pdata->x_min = coords[0];
++        pdata->y_min = coords[1];
++        pdata->x_max = coords[2];
++        pdata->y_max = coords[3];
++    }
++
++    FTS_INFO("display x(%d %d) y(%d %d)", pdata->x_min, pdata->x_max,
++             pdata->y_min, pdata->y_max);
++    return 0;
++}
++
++static int fts_parse_dt(struct device *dev, struct fts_ts_platform_data *pdata)
++{
++    int ret = 0;
++    struct device_node *np = dev->of_node;
++    u32 temp_val = 0;
++
++    FTS_FUNC_ENTER();
++
++    ret = fts_get_dt_coords(dev, "focaltech,display-coords", pdata);
++    if (ret < 0)
++        FTS_ERROR("Unable to get display-coords");
++
++    /* key */
++    pdata->have_key = of_property_read_bool(np, "focaltech,have-key");
++    if (pdata->have_key) {
++        ret = of_property_read_u32(np, "focaltech,key-number", &pdata->key_number);
++        if (ret < 0)
++            FTS_ERROR("Key number undefined!");
++
++        ret = of_property_read_u32_array(np, "focaltech,keys",
++                                         pdata->keys, pdata->key_number);
++        if (ret < 0)
++            FTS_ERROR("Keys undefined!");
++        else if (pdata->key_number > FTS_MAX_KEYS)
++            pdata->key_number = FTS_MAX_KEYS;
++
++        ret = of_property_read_u32_array(np, "focaltech,key-x-coords",
++                                         pdata->key_x_coords,
++                                         pdata->key_number);
++        if (ret < 0)
++            FTS_ERROR("Key Y Coords undefined!");
++
++        ret = of_property_read_u32_array(np, "focaltech,key-y-coords",
++                                         pdata->key_y_coords,
++                                         pdata->key_number);
++        if (ret < 0)
++            FTS_ERROR("Key X Coords undefined!");
++
++        FTS_INFO("VK Number:%d, key:(%d,%d,%d), "
++                 "coords:(%d,%d),(%d,%d),(%d,%d)",
++                 pdata->key_number,
++                 pdata->keys[0], pdata->keys[1], pdata->keys[2],
++                 pdata->key_x_coords[0], pdata->key_y_coords[0],
++                 pdata->key_x_coords[1], pdata->key_y_coords[1],
++                 pdata->key_x_coords[2], pdata->key_y_coords[2]);
++    }
++
++    /* reset, irq gpio info */
++    pdata->reset_gpio = of_get_named_gpio_flags(np, "focaltech,reset-gpio",
++                        0, &pdata->reset_gpio_flags);
++    if (pdata->reset_gpio < 0)
++        FTS_ERROR("Unable to get reset_gpio");
++
++    pdata->irq_gpio = of_get_named_gpio_flags(np, "focaltech,irq-gpio",
++                      0, &pdata->irq_gpio_flags);
++    if (pdata->irq_gpio < 0)
++        FTS_ERROR("Unable to get irq_gpio");
++
++    ret = of_property_read_u32(np, "focaltech,max-touch-number", &temp_val);
++    if (ret < 0) {
++        FTS_ERROR("Unable to get max-touch-number, please check dts");
++        pdata->max_touch_number = FTS_MAX_POINTS_SUPPORT;
++    } else {
++        if (temp_val < 2)
++            pdata->max_touch_number = 2; /* max_touch_number must >= 2 */
++        else if (temp_val > FTS_MAX_POINTS_SUPPORT)
++            pdata->max_touch_number = FTS_MAX_POINTS_SUPPORT;
++        else
++            pdata->max_touch_number = temp_val;
++    }
++
++    FTS_INFO("max touch number:%d, irq gpio:%d, reset gpio:%d",
++             pdata->max_touch_number, pdata->irq_gpio, pdata->reset_gpio);
++
++    FTS_FUNC_EXIT();
++    return 0;
++}
++
++#if defined(CONFIG_FB)
++static void fts_resume_work(struct work_struct *work)
++{
++    struct fts_ts_data *ts_data = container_of(work, struct fts_ts_data,
++                                  resume_work);
++
++    fts_ts_resume(ts_data->dev);
++}
++
++static int fb_notifier_callback(struct notifier_block *self,
++                                unsigned long event, void *data)
++{
++    struct fb_event *evdata = data;
++    int *blank = NULL;
++    struct fts_ts_data *ts_data = container_of(self, struct fts_ts_data,
++                                  fb_notif);
++
++    if (!(event == FB_EVENT_BLANK)) {
++        FTS_INFO("event(%lu) do not need process\n", event);
++        return 0;
++    }
++
++    blank = evdata->data;
++    FTS_INFO("FB event:%lu,blank:%d", event, *blank);
++    switch (*blank) {
++    case FB_BLANK_UNBLANK:
++        if (FB_EVENT_BLANK == event) {
++            queue_work(fts_data->ts_workqueue, &fts_data->resume_work);
++        }
++        break;
++    case FB_BLANK_POWERDOWN:
++        if (FB_EVENT_BLANK == event) {
++            FTS_INFO("suspend: event = %lu, not care\n", event);
++        }
++        break;
++    default:
++        FTS_INFO("FB BLANK(%d) do not need process\n", *blank);
++        break;
++    }
++
++    return 0;
++}
++#elif defined(CONFIG_HAS_EARLYSUSPEND)
++static void fts_ts_early_suspend(struct early_suspend *handler)
++{
++    struct fts_ts_data *ts_data = container_of(handler, struct fts_ts_data,
++                                  early_suspend);
++
++    fts_ts_suspend(ts_data->dev);
++}
++
++static void fts_ts_late_resume(struct early_suspend *handler)
++{
++    struct fts_ts_data *ts_data = container_of(handler, struct fts_ts_data,
++                                  early_suspend);
++
++    fts_ts_resume(ts_data->dev);
++}
++#endif
++
++static int fts_ts_probe_entry(struct fts_ts_data *ts_data)
++{
++    int ret = 0;
++    int pdata_size = sizeof(struct fts_ts_platform_data);
++
++    FTS_FUNC_ENTER();
++    FTS_INFO("%s", FTS_DRIVER_VERSION);
++    ts_data->pdata = kzalloc(pdata_size, GFP_KERNEL);
++    if (!ts_data->pdata) {
++        FTS_ERROR("allocate memory for platform_data fail");
++        return -ENOMEM;
++    }
++
++    if (ts_data->dev->of_node) {
++        ret = fts_parse_dt(ts_data->dev, ts_data->pdata);
++        if (ret)
++            FTS_ERROR("device-tree parse fail");
++    } else {
++        if (ts_data->dev->platform_data) {
++            memcpy(ts_data->pdata, ts_data->dev->platform_data, pdata_size);
++        } else {
++            FTS_ERROR("platform_data is null");
++            return -ENODEV;
++        }
++    }
++
++    ts_data->ts_workqueue = create_singlethread_workqueue("fts_wq");
++    if (!ts_data->ts_workqueue) {
++        FTS_ERROR("create fts workqueue fail");
++    }
++
++    spin_lock_init(&ts_data->irq_lock);
++    mutex_init(&ts_data->report_mutex);
++    mutex_init(&ts_data->bus_lock);
++
++    /* Init communication interface */
++    ret = fts_bus_init(ts_data);
++    if (ret) {
++        FTS_ERROR("bus initialize fail");
++        goto err_bus_init;
++    }
++
++    ret = fts_input_init(ts_data);
++    if (ret) {
++        FTS_ERROR("input initialize fail");
++        goto err_input_init;
++    }
++
++    ret = fts_report_buffer_init(ts_data);
++    if (ret) {
++        FTS_ERROR("report buffer init fail");
++        goto err_report_buffer;
++    }
++
++    ret = fts_gpio_configure(ts_data);
++    if (ret) {
++        FTS_ERROR("configure the gpios fail");
++        goto err_gpio_config;
++    }
++
++#if FTS_POWER_SOURCE_CUST_EN
++    ret = fts_power_source_init(ts_data);
++    if (ret) {
++        FTS_ERROR("fail to get power(regulator)");
++        goto err_power_init;
++    }
++#endif
++
++#if (!FTS_CHIP_IDC)
++    fts_reset_proc(200);
++#endif
++
++    ret = fts_get_ic_information(ts_data);
++    if (ret) {
++        FTS_ERROR("not focal IC, unregister driver");
++        goto err_irq_req;
++    }
++
++#if FTS_EX_FUNC_EN
++    ret = fts_create_apk_debug_channel(ts_data);
++    if (ret) {
++        FTS_ERROR("create apk debug node fail");
++    }
++
++    ret = fts_create_sysfs(ts_data);
++    if (ret) {
++        FTS_ERROR("create sysfs node fail");
++    }
++#endif
++
++#if FTS_POINT_REPORT_CHECK_EN
++    ret = fts_point_report_check_init(ts_data);
++    if (ret) {
++        FTS_ERROR("init point report check fail");
++    }
++#endif
++
++#if FTS_EX_MODE_EN
++    ret = fts_ex_mode_init(ts_data);
++    if (ret) {
++        FTS_ERROR("init glove/cover/charger fail");
++    }
++#endif
++
++#if FTS_GESTURE_EN
++    ret = fts_gesture_init(ts_data);
++    if (ret) {
++        FTS_ERROR("init gesture fail");
++    }
++#endif
++
++
++#if FTS_ESDCHECK_EN
++    ret = fts_esdcheck_init(ts_data);
++    if (ret) {
++        FTS_ERROR("init esd check fail");
++    }
++#endif
++
++    ret = fts_irq_registration(ts_data);
++    if (ret) {
++        FTS_ERROR("request irq failed");
++        goto err_irq_req;
++    }
++
++#if FTS_AUTO_UPGRADE_EN
++    ret = fts_fwupg_init(ts_data);
++    if (ret) {
++        FTS_ERROR("init fw upgrade fail");
++    }
++#endif
++
++#if defined(CONFIG_FB)
++    /*if (ts_data->ts_workqueue) {
++        INIT_WORK(&ts_data->resume_work, fts_resume_work);
++    }
++    ts_data->fb_notif.notifier_call = fb_notifier_callback;
++    ret = fb_register_client(&ts_data->fb_notif);
++    if (ret) {
++        FTS_ERROR("[FB]Unable to register fb_notifier: %d", ret);
++    }*/
++#elif defined(CONFIG_HAS_EARLYSUSPEND)
++    ts_data->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + FTS_SUSPEND_LEVEL;
++    ts_data->early_suspend.suspend = fts_ts_early_suspend;
++    ts_data->early_suspend.resume = fts_ts_late_resume;
++    register_early_suspend(&ts_data->early_suspend);
++#endif
++
++    FTS_FUNC_EXIT();
++    return 0;
++
++err_irq_req:
++#if FTS_POWER_SOURCE_CUST_EN
++err_power_init:
++    fts_power_source_exit(ts_data);
++#endif
++    if (gpio_is_valid(ts_data->pdata->reset_gpio))
++        gpio_free(ts_data->pdata->reset_gpio);
++    if (gpio_is_valid(ts_data->pdata->irq_gpio))
++        gpio_free(ts_data->pdata->irq_gpio);
++err_gpio_config:
++    kfree_safe(ts_data->point_buf);
++    kfree_safe(ts_data->events);
++err_report_buffer:
++    input_unregister_device(ts_data->input_dev);
++err_input_init:
++    if (ts_data->ts_workqueue)
++        destroy_workqueue(ts_data->ts_workqueue);
++err_bus_init:
++    kfree_safe(ts_data->bus_tx_buf);
++    kfree_safe(ts_data->bus_rx_buf);
++    kfree_safe(ts_data->pdata);
++
++    FTS_FUNC_EXIT();
++    return ret;
++}
++
++static int fts_ts_remove_entry(struct fts_ts_data *ts_data)
++{
++    FTS_FUNC_ENTER();
++
++#if FTS_POINT_REPORT_CHECK_EN
++    fts_point_report_check_exit(ts_data);
++#endif
++
++#if FTS_EX_FUNC_EN
++    fts_release_apk_debug_channel(ts_data);
++    fts_remove_sysfs(ts_data);
++#endif
++#if FTS_EX_MODE_EN
++    fts_ex_mode_exit(ts_data);
++#endif
++
++#if FTS_AUTO_UPGRADE_EN
++    fts_fwupg_exit(ts_data);
++#endif
++
++
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_exit(ts_data);
++#endif
++
++#if FTS_GESTURE_EN
++    fts_gesture_exit(ts_data);
++#endif
++    fts_bus_exit(ts_data);
++
++    free_irq(ts_data->irq, ts_data);
++    input_unregister_device(ts_data->input_dev);
++
++    if (ts_data->ts_workqueue)
++        destroy_workqueue(ts_data->ts_workqueue);
++
++#if defined(CONFIG_FB)
++    if (fb_unregister_client(&ts_data->fb_notif))
++        FTS_ERROR("Error occurred while unregistering fb_notifier.");
++#elif defined(CONFIG_HAS_EARLYSUSPEND)
++    unregister_early_suspend(&ts_data->early_suspend);
++#endif
++
++    if (gpio_is_valid(ts_data->pdata->reset_gpio))
++        gpio_free(ts_data->pdata->reset_gpio);
++
++    if (gpio_is_valid(ts_data->pdata->irq_gpio))
++        gpio_free(ts_data->pdata->irq_gpio);
++
++#if FTS_POWER_SOURCE_CUST_EN
++    fts_power_source_exit(ts_data);
++#endif
++
++    kfree_safe(ts_data->point_buf);
++    kfree_safe(ts_data->events);
++
++    kfree_safe(ts_data->pdata);
++    kfree_safe(ts_data);
++
++    FTS_FUNC_EXIT();
++
++    return 0;
++}
++
++static int fts_ts_suspend(struct device *dev)
++{
++    int ret = 0;
++    struct fts_ts_data *ts_data = fts_data;
++
++    FTS_FUNC_ENTER();
++    if (ts_data->suspended) {
++        FTS_INFO("Already in suspend state");
++        return 0;
++    }
++
++    if (ts_data->fw_loading) {
++        FTS_INFO("fw upgrade in process, can't suspend");
++        return 0;
++    }
++
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_suspend();
++#endif
++
++    if (ts_data->gesture_mode) {
++#if FTS_GESTURE_EN
++        fts_gesture_suspend(ts_data);
++#endif
++    } else {
++        fts_irq_disable();
++
++        FTS_INFO("make TP enter into sleep mode");
++        ret = fts_write_reg(FTS_REG_POWER_MODE, FTS_REG_POWER_MODE_SLEEP);
++        if (ret < 0)
++            FTS_ERROR("set TP to sleep mode fail, ret=%d", ret);
++
++        if (!ts_data->ic_info.is_incell) {
++#if FTS_POWER_SOURCE_CUST_EN
++            ret = fts_power_source_suspend(ts_data);
++            if (ret < 0) {
++                FTS_ERROR("power enter suspend fail");
++            }
++#endif
++        }
++    }
++
++    fts_release_all_finger();
++    ts_data->suspended = true;
++    FTS_FUNC_EXIT();
++    return 0;
++}
++
++static int fts_ts_resume(struct device *dev)
++{
++    struct fts_ts_data *ts_data = fts_data;
++
++    FTS_FUNC_ENTER();
++    if (!ts_data->suspended) {
++        FTS_DEBUG("Already in awake state");
++        return 0;
++    }
++
++    fts_release_all_finger();
++
++    if (!ts_data->ic_info.is_incell) {
++#if FTS_POWER_SOURCE_CUST_EN
++        fts_power_source_resume(ts_data);
++#endif
++        fts_reset_proc(200);
++    }
++
++    fts_wait_tp_to_valid();
++#if FTS_EX_MODE_EN
++    fts_ex_mode_recovery(ts_data);
++#endif
++
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_resume();
++#endif
++
++    if (ts_data->gesture_mode) {
++#if FTS_GESTURE_EN
++        fts_gesture_resume(ts_data);
++#endif
++    } else {
++        fts_irq_enable();
++    }
++
++    ts_data->suspended = false;
++    FTS_FUNC_EXIT();
++    return 0;
++}
++
++static SIMPLE_DEV_PM_OPS(fts_pm_ops, fts_ts_suspend, fts_ts_resume);
++/*****************************************************************************
++* TP Driver
++*****************************************************************************/
++
++static int fts_ts_probe(struct i2c_client *client, const struct i2c_device_id *id)
++{
++    int ret = 0;
++    struct fts_ts_data *ts_data = NULL;
++
++    FTS_INFO("Touch Screen(I2C BUS) driver prboe...");
++    if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
++        FTS_ERROR("I2C not supported");
++        return -ENODEV;
++    }
++
++    /* malloc memory for global struct variable */
++    ts_data = (struct fts_ts_data *)kzalloc(sizeof(*ts_data), GFP_KERNEL);
++    if (!ts_data) {
++        FTS_ERROR("allocate memory for fts_data fail");
++        return -ENOMEM;
++    }
++
++    fts_data = ts_data;
++    ts_data->client = client;
++    ts_data->dev = &client->dev;
++    ts_data->log_level = 1;
++    ts_data->fw_is_running = 0;
++    i2c_set_clientdata(client, ts_data);
++
++    ret = fts_ts_probe_entry(ts_data);
++    if (ret) {
++        FTS_ERROR("Touch Screen(I2C BUS) driver probe fail");
++        kfree_safe(ts_data);
++        return ret;
++    }
++
++    FTS_INFO("Touch Screen(I2C BUS) driver prboe successfully");
++    return 0;
++}
++
++static int fts_ts_remove(struct i2c_client *client)
++{
++    return fts_ts_remove_entry(i2c_get_clientdata(client));
++}
++
++static const struct i2c_device_id fts_ts_id[] = {
++    {FTS_DRIVER_NAME, 0},
++    {},
++};
++static const struct of_device_id fts_dt_match[] = {
++    {.compatible = "focaltech,fts", },
++    {},
++};
++MODULE_DEVICE_TABLE(of, fts_dt_match);
++
++static struct i2c_driver fts_ts_driver = {
++    .probe = fts_ts_probe,
++    .remove = fts_ts_remove,
++    .driver = {
++        .name = FTS_DRIVER_NAME,
++        .owner = THIS_MODULE,
++        .of_match_table = of_match_ptr(fts_dt_match),
++	.pm = &fts_pm_ops,
++    },
++    .id_table = fts_ts_id,
++};
++
++static int __init fts_ts_init(void)
++{
++    int ret = 0;
++
++    FTS_FUNC_ENTER();
++    ret = i2c_add_driver(&fts_ts_driver);
++    if ( ret != 0 ) {
++        FTS_ERROR("Focaltech touch screen driver init failed!");
++    }
++    FTS_FUNC_EXIT();
++    return ret;
++}
++
++static void __exit fts_ts_exit(void)
++{
++    i2c_del_driver(&fts_ts_driver);
++}
++module_init(fts_ts_init);
++module_exit(fts_ts_exit);
++
++MODULE_AUTHOR("FocalTech Driver Team");
++MODULE_DESCRIPTION("FocalTech Touchscreen Driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_core.h b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_core.h
+new file mode 100644
+index 000000000..669561af4
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_core.h
+@@ -0,0 +1,260 @@
++/*
++ *
++ * FocalTech TouchScreen driver.
++ *
++ * Copyright (c) 2012-2019, Focaltech Ltd. All rights reserved.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++/*****************************************************************************
++*
++* File Name: focaltech_core.h
++
++* Author: Focaltech Driver Team
++*
++* Created: 2016-08-08
++*
++* Abstract:
++*
++* Reference:
++*
++*****************************************************************************/
++
++#ifndef __LINUX_FOCALTECH_CORE_H__
++#define __LINUX_FOCALTECH_CORE_H__
++/*****************************************************************************
++* Included header files
++*****************************************************************************/
++#include <linux/kernel.h>
++#include <linux/device.h>
++#include <linux/i2c.h>
++#include <linux/spi/spi.h>
++#include <linux/input.h>
++#include <linux/input/mt.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/vmalloc.h>
++#include <linux/gpio.h>
++#include <linux/regulator/consumer.h>
++#include <asm/uaccess.h>
++#include <linux/firmware.h>
++#include <linux/debugfs.h>
++#include <linux/mutex.h>
++#include <linux/workqueue.h>
++#include <linux/wait.h>
++#include <linux/time.h>
++#include <linux/jiffies.h>
++#include <linux/fs.h>
++#include <linux/proc_fs.h>
++#include <linux/version.h>
++#include <linux/types.h>
++#include <linux/sched.h>
++#include <linux/kthread.h>
++#include <linux/dma-mapping.h>
++#include "focaltech_common.h"
++
++/*****************************************************************************
++* Private constant and macro definitions using #define
++*****************************************************************************/
++#define FTS_MAX_POINTS_SUPPORT              10 /* constant value, can't be changed */
++#define FTS_MAX_KEYS                        4
++#define FTS_KEY_DIM                         10
++#define FTS_ONE_TCH_LEN                     6
++#define FTS_TOUCH_DATA_LEN  (FTS_MAX_POINTS_SUPPORT * FTS_ONE_TCH_LEN + 3)
++
++#define FTS_GESTURE_POINTS_MAX              6
++#define FTS_GESTURE_DATA_LEN               (FTS_GESTURE_POINTS_MAX * 4 + 4)
++
++#define FTS_MAX_ID                          0x0A
++#define FTS_TOUCH_X_H_POS                   3
++#define FTS_TOUCH_X_L_POS                   4
++#define FTS_TOUCH_Y_H_POS                   5
++#define FTS_TOUCH_Y_L_POS                   6
++#define FTS_TOUCH_PRE_POS                   7
++#define FTS_TOUCH_AREA_POS                  8
++#define FTS_TOUCH_POINT_NUM                 2
++#define FTS_TOUCH_EVENT_POS                 3
++#define FTS_TOUCH_ID_POS                    5
++#define FTS_COORDS_ARR_SIZE                 4
++#define FTS_X_MIN_DISPLAY_DEFAULT           0
++#define FTS_Y_MIN_DISPLAY_DEFAULT           0
++#define FTS_X_MAX_DISPLAY_DEFAULT           720
++#define FTS_Y_MAX_DISPLAY_DEFAULT           1280
++
++#define FTS_TOUCH_DOWN                      0
++#define FTS_TOUCH_UP                        1
++#define FTS_TOUCH_CONTACT                   2
++#define EVENT_DOWN(flag)                    ((FTS_TOUCH_DOWN == flag) || (FTS_TOUCH_CONTACT == flag))
++#define EVENT_UP(flag)                      (FTS_TOUCH_UP == flag)
++#define EVENT_NO_DOWN(data)                 (!data->point_num)
++
++#define FTX_MAX_COMPATIBLE_TYPE             4
++#define FTX_MAX_COMMMAND_LENGTH             16
++
++
++/*****************************************************************************
++* Private enumerations, structures and unions using typedef
++*****************************************************************************/
++struct ftxxxx_proc {
++    struct proc_dir_entry *proc_entry;
++    u8 opmode;
++    u8 cmd_len;
++    u8 cmd[FTX_MAX_COMMMAND_LENGTH];
++};
++
++struct fts_ts_platform_data {
++    u32 irq_gpio;
++    u32 irq_gpio_flags;
++    u32 reset_gpio;
++    u32 reset_gpio_flags;
++    bool have_key;
++    u32 key_number;
++    u32 keys[FTS_MAX_KEYS];
++    u32 key_y_coords[FTS_MAX_KEYS];
++    u32 key_x_coords[FTS_MAX_KEYS];
++    u32 x_max;
++    u32 y_max;
++    u32 x_min;
++    u32 y_min;
++    u32 max_touch_number;
++};
++
++struct ts_event {
++    int x;      /*x coordinate */
++    int y;      /*y coordinate */
++    int p;      /* pressure */
++    int flag;   /* touch event flag: 0 -- down; 1-- up; 2 -- contact */
++    int id;     /*touch ID */
++    int area;
++};
++
++struct fts_ts_data {
++    struct i2c_client *client;
++    struct spi_device *spi;
++    struct device *dev;
++    struct input_dev *input_dev;
++    struct fts_ts_platform_data *pdata;
++    struct ts_ic_info ic_info;
++    struct workqueue_struct *ts_workqueue;
++    struct work_struct fwupg_work;
++    struct delayed_work esdcheck_work;
++    struct delayed_work prc_work;
++    struct work_struct resume_work;
++    struct ftxxxx_proc proc;
++    spinlock_t irq_lock;
++    struct mutex report_mutex;
++    struct mutex bus_lock;
++    int irq;
++    int log_level;
++    int fw_is_running;      /* confirm fw is running when using spi:default 0 */
++    int dummy_byte;
++    bool suspended;
++    bool fw_loading;
++    bool irq_disabled;
++    bool power_disabled;
++    bool glove_mode;
++    bool cover_mode;
++    bool charger_mode;
++    bool gesture_mode;      /* gesture enable or disable, default: disable */
++    /* multi-touch */
++    struct ts_event *events;
++    u8 *bus_tx_buf;
++    u8 *bus_rx_buf;
++    u8 *point_buf;
++    int pnt_buf_size;
++    int touchs;
++    int key_state;
++    int touch_point;
++    int point_num;
++    struct regulator *vdd;
++    struct regulator *vcc_i2c;
++#if FTS_PINCTRL_EN
++    struct pinctrl *pinctrl;
++    struct pinctrl_state *pins_active;
++    struct pinctrl_state *pins_suspend;
++    struct pinctrl_state *pins_release;
++#endif
++#if defined(CONFIG_FB)
++    struct notifier_block fb_notif;
++#elif defined(CONFIG_HAS_EARLYSUSPEND)
++    struct early_suspend early_suspend;
++#endif
++};
++
++/*****************************************************************************
++* Global variable or extern global variabls/functions
++*****************************************************************************/
++extern struct fts_ts_data *fts_data;
++
++/* communication interface */
++int fts_read(u8 *cmd, u32 cmdlen, u8 *data, u32 datalen);
++int fts_read_reg(u8 addr, u8 *value);
++int fts_write(u8 *writebuf, u32 writelen);
++int fts_write_reg(u8 addr, u8 value);
++void fts_hid2std(void);
++int fts_bus_init(struct fts_ts_data *ts_data);
++int fts_bus_exit(struct fts_ts_data *ts_data);
++
++/* Gesture functions */
++int fts_gesture_init(struct fts_ts_data *ts_data);
++int fts_gesture_exit(struct fts_ts_data *ts_data);
++void fts_gesture_recovery(struct fts_ts_data *ts_data);
++int fts_gesture_readdata(struct fts_ts_data *ts_data, u8 *data);
++int fts_gesture_suspend(struct fts_ts_data *ts_data);
++int fts_gesture_resume(struct fts_ts_data *ts_data);
++
++/* Apk and functions */
++int fts_create_apk_debug_channel(struct fts_ts_data *);
++void fts_release_apk_debug_channel(struct fts_ts_data *);
++
++/* ADB functions */
++int fts_create_sysfs(struct fts_ts_data *ts_data);
++int fts_remove_sysfs(struct fts_ts_data *ts_data);
++
++/* ESD */
++#if FTS_ESDCHECK_EN
++int fts_esdcheck_init(struct fts_ts_data *ts_data);
++int fts_esdcheck_exit(struct fts_ts_data *ts_data);
++int fts_esdcheck_switch(bool enable);
++int fts_esdcheck_proc_busy(bool proc_debug);
++int fts_esdcheck_set_intr(bool intr);
++int fts_esdcheck_suspend(void);
++int fts_esdcheck_resume(void);
++#endif
++
++
++/* Point Report Check*/
++#if FTS_POINT_REPORT_CHECK_EN
++int fts_point_report_check_init(struct fts_ts_data *ts_data);
++int fts_point_report_check_exit(struct fts_ts_data *ts_data);
++void fts_prc_queue_work(struct fts_ts_data *ts_data);
++#endif
++
++/* FW upgrade */
++int fts_fwupg_init(struct fts_ts_data *ts_data);
++int fts_fwupg_exit(struct fts_ts_data *ts_data);
++int fts_upgrade_bin(char *fw_name, bool force);
++int fts_enter_test_environment(bool test_state);
++
++/* Other */
++int fts_reset_proc(int hdelayms);
++int fts_wait_tp_to_valid(void);
++void fts_release_all_finger(void);
++void fts_tp_state_recovery(struct fts_ts_data *ts_data);
++int fts_ex_mode_init(struct fts_ts_data *ts_data);
++int fts_ex_mode_exit(struct fts_ts_data *ts_data);
++int fts_ex_mode_recovery(struct fts_ts_data *ts_data);
++
++void fts_irq_disable(void);
++void fts_irq_enable(void);
++#endif /* __LINUX_FOCALTECH_CORE_H__ */
+diff --git a/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_esdcheck.c b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_esdcheck.c
+new file mode 100644
+index 000000000..b34bb26e8
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_esdcheck.c
+@@ -0,0 +1,464 @@
++/*
++ *
++ * FocalTech TouchScreen driver.
++ *
++ * Copyright (c) 2012-2019, FocalTech Systems, Ltd., all rights reserved.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++/*****************************************************************************
++*
++* File Name: focaltech_esdcheck.c
++*
++*    Author: Focaltech Driver Team
++*
++*   Created: 2016-08-03
++*
++*  Abstract: ESD check function
++*
++*   Version: v1.0
++*
++* Revision History:
++*        v1.0:
++*            First release. By luougojin 2016-08-03
++*        v1.1: By luougojin 2017-02-15
++*            1. Add LCD_ESD_PATCH to control idc_esdcheck_lcderror
++*****************************************************************************/
++
++/*****************************************************************************
++* Included header files
++*****************************************************************************/
++#include "focaltech_core.h"
++
++#if FTS_ESDCHECK_EN
++/*****************************************************************************
++* Private constant and macro definitions using #define
++*****************************************************************************/
++#define ESDCHECK_WAIT_TIME              1000    /* ms */
++#define LCD_ESD_PATCH                   0
++#define ESDCHECK_INTRCNT_MAX            2
++
++/*****************************************************************************
++* Private enumerations, structures and unions using typedef
++*****************************************************************************/
++struct fts_esdcheck_st {
++    u8      mode                : 1;    /* 1- need check esd 0- no esd check */
++    u8      suspend             : 1;
++    u8      proc_debug          : 1;    /* apk or adb use */
++    u8      intr                : 1;    /* 1- Interrupt trigger */
++    u8      unused              : 4;
++    u8      intr_cnt;
++    u8      flow_work_hold_cnt;         /* Flow Work Cnt(reg0x91) keep a same value for x times. >=5 times is ESD, need reset */
++    u8      flow_work_cnt_last;         /* Save Flow Work Cnt(reg0x91) value */
++    u32     hardware_reset_cnt;
++    u32     nack_cnt;
++    u32     dataerror_cnt;
++};
++
++/*****************************************************************************
++* Static variables
++*****************************************************************************/
++static struct fts_esdcheck_st fts_esdcheck_data;
++
++/*****************************************************************************
++* Global variable or extern global variabls/functions
++*****************************************************************************/
++
++/*****************************************************************************
++* Static function prototypes
++*****************************************************************************/
++
++/*****************************************************************************
++* functions body
++*****************************************************************************/
++#if LCD_ESD_PATCH
++int lcd_need_reset;
++static int tp_need_recovery; /* LCD reset cause Tp reset */
++int idc_esdcheck_lcderror(struct fts_ts_data *ts_data)
++{
++    int ret = 0;
++    u8 val = 0;
++
++    FTS_DEBUG("check LCD ESD");
++    if ( (tp_need_recovery == 1) && (lcd_need_reset == 0) ) {
++        tp_need_recovery = 0;
++        /* LCD reset, need recover TP state */
++        fts_release_all_finger();
++        fts_tp_state_recovery(ts_data);
++    }
++
++    ret = fts_read_reg(FTS_REG_ESD_SATURATE, &val);
++    if ( ret < 0) {
++        FTS_ERROR("read reg0xED fail,ret:%d", ret);
++        return -EIO;
++    }
++
++    if (val == 0xAA) {
++        /*
++        * 1. Set flag lcd_need_reset = 1;
++        * 2. LCD driver need reset(recovery) LCD and set lcd_need_reset to 0
++        * 3. recover TP state
++        */
++        FTS_INFO("LCD ESD, need execute LCD reset");
++        lcd_need_reset = 1;
++        tp_need_recovery = 1;
++    }
++
++    return 0;
++}
++#endif
++
++static int fts_esdcheck_tp_reset(struct fts_ts_data *ts_data)
++{
++    FTS_FUNC_ENTER();
++
++    fts_esdcheck_data.flow_work_hold_cnt = 0;
++    fts_esdcheck_data.hardware_reset_cnt++;
++
++    fts_reset_proc(200);
++    fts_release_all_finger();
++    fts_tp_state_recovery(ts_data);
++
++    FTS_FUNC_EXIT();
++    return 0;
++}
++
++static bool get_chip_id(struct fts_ts_data *ts_data)
++{
++    int ret = 0;
++    int i = 0;
++    u8 reg_value = 0;
++    u8 reg_addr = 0;
++    u8 chip_id = ts_data->ic_info.ids.chip_idh;
++
++    for (i = 0; i < 3; i++) {
++        reg_addr = FTS_REG_CHIP_ID;
++        ret = fts_read(&reg_addr, 1, &reg_value, 1);
++        if (ret < 0) {
++            FTS_ERROR("read chip id fail,ret:%d", ret);
++            fts_esdcheck_data.nack_cnt++;
++        } else {
++            if (reg_value == chip_id) {
++                break;
++            } else {
++                FTS_DEBUG("read chip_id:%x,retry:%d", reg_value, i);
++                fts_esdcheck_data.dataerror_cnt++;
++            }
++        }
++        msleep(10);
++    }
++
++    /* if can't get correct data in 3 times, then need hardware reset */
++    if (i >= 3) {
++        FTS_ERROR("read chip id 3 times fail, need execute TP reset");
++        return true;
++    }
++
++    return false;
++}
++
++/*****************************************************************************
++*  Name: get_flow_cnt
++*  Brief: Read flow cnt(0x91)
++*  Input:
++*  Output:
++*  Return:  1(true) - Reg 0x91(flow cnt) abnormal: hold a value for 5 times
++*           0(false) - Reg 0x91(flow cnt) normal
++*****************************************************************************/
++static bool get_flow_cnt(struct fts_ts_data *ts_data)
++{
++    int     ret = 0;
++    u8      reg_value = 0;
++    u8      reg_addr = 0;
++
++    reg_addr = FTS_REG_FLOW_WORK_CNT;
++    ret = fts_read(&reg_addr, 1, &reg_value, 1);
++    if (ret < 0) {
++        FTS_ERROR("read reg0x91 fail,ret:%d", ret);
++        fts_esdcheck_data.nack_cnt++;
++    } else {
++        if ( reg_value == fts_esdcheck_data.flow_work_cnt_last ) {
++            FTS_DEBUG("reg0x91,val:%x,last:%x", reg_value,
++                      fts_esdcheck_data.flow_work_cnt_last);
++            fts_esdcheck_data.flow_work_hold_cnt++;
++        } else {
++            fts_esdcheck_data.flow_work_hold_cnt = 0;
++        }
++
++        fts_esdcheck_data.flow_work_cnt_last = reg_value;
++    }
++
++    /* Flow Work Cnt keep a value for 5 times, need execute TP reset */
++    if (fts_esdcheck_data.flow_work_hold_cnt >= 5) {
++        FTS_DEBUG("reg0x91 keep a value for 5 times, need execute TP reset");
++        return true;
++    }
++
++    return false;
++}
++
++static int esdcheck_algorithm(struct fts_ts_data *ts_data)
++{
++    int     ret = 0;
++    u8      reg_value = 0;
++    u8      reg_addr = 0;
++    bool    hardware_reset = 0;
++
++    /* 1. esdcheck is interrupt, then return */
++    if (fts_esdcheck_data.intr == 1) {
++        fts_esdcheck_data.intr_cnt++;
++        if (fts_esdcheck_data.intr_cnt > ESDCHECK_INTRCNT_MAX)
++            fts_esdcheck_data.intr = 0;
++        else
++            return 0;
++    }
++
++    /* 2. check power state, if suspend, no need check esd */
++    if (fts_esdcheck_data.suspend == 1) {
++        FTS_DEBUG("In suspend, not check esd");
++        /* because in suspend state, adb can be used, when upgrade FW, will
++         * active ESD check(active = 1); But in suspend, then will don't
++         * queue_delayed_work, when resume, don't check ESD again
++         */
++        return 0;
++    }
++
++    /* 3. check fts_esdcheck_data.proc_debug state, if 1-proc busy, no need check esd*/
++    if (fts_esdcheck_data.proc_debug == 1) {
++        FTS_INFO("In apk/adb command mode, not check esd");
++        return 0;
++    }
++
++    /* 4. In factory mode, can't check esd */
++    reg_addr = FTS_REG_WORKMODE;
++    ret = fts_read_reg(reg_addr, &reg_value);
++    if ( ret < 0 ) {
++        fts_esdcheck_data.nack_cnt++;
++    } else if ( (reg_value & 0x70) !=  FTS_REG_WORKMODE_WORK_VALUE) {
++        FTS_DEBUG("not in work mode(%x), no check esd", reg_value);
++        return 0;
++    }
++
++    /* 5. IDC esd check lcd  default:close */
++#if LCD_ESD_PATCH
++    idc_esdcheck_lcderror(ts_data);
++#endif
++
++    /* 6. Get Chip ID */
++    hardware_reset = get_chip_id(ts_data);
++
++    /* 7. get Flow work cnt: 0x91 If no change for 5 times, then ESD and reset */
++    if (!hardware_reset) {
++        hardware_reset = get_flow_cnt(ts_data);
++    }
++
++    /* 8. If need hardware reset, then handle it here */
++    if (hardware_reset == 1) {
++        FTS_DEBUG("NoACK=%d, Error Data=%d, Hardware Reset=%d",
++                  fts_esdcheck_data.nack_cnt,
++                  fts_esdcheck_data.dataerror_cnt,
++                  fts_esdcheck_data.hardware_reset_cnt);
++        fts_esdcheck_tp_reset(ts_data);
++    }
++
++    return 0;
++}
++
++static void esdcheck_func(struct work_struct *work)
++{
++    struct fts_ts_data *ts_data = container_of(work,
++                                  struct fts_ts_data, esdcheck_work.work);
++
++    if (ENABLE == fts_esdcheck_data.mode) {
++        esdcheck_algorithm(ts_data);
++        queue_delayed_work(ts_data->ts_workqueue, &ts_data->esdcheck_work,
++                           msecs_to_jiffies(ESDCHECK_WAIT_TIME));
++    }
++
++}
++
++int fts_esdcheck_set_intr(bool intr)
++{
++    /* interrupt don't add debug message */
++    fts_esdcheck_data.intr = intr;
++    fts_esdcheck_data.intr_cnt = (u8)intr;
++    return 0;
++}
++
++static int fts_esdcheck_get_status(void)
++{
++    /* interrupt don't add debug message */
++    return fts_esdcheck_data.mode;
++}
++
++/*****************************************************************************
++*  Name: fts_esdcheck_proc_busy
++*  Brief: When APK or ADB command access TP via driver, then need set proc_debug,
++*         then will not check ESD.
++*  Input:
++*  Output:
++*  Return:
++*****************************************************************************/
++int fts_esdcheck_proc_busy(bool proc_debug)
++{
++    fts_esdcheck_data.proc_debug = proc_debug;
++    return 0;
++}
++
++/*****************************************************************************
++*  Name: fts_esdcheck_switch
++*  Brief: FTS esd check function switch.
++*  Input:   enable:  1 - Enable esd check
++*                    0 - Disable esd check
++*  Output:
++*  Return:
++*****************************************************************************/
++int fts_esdcheck_switch(bool enable)
++{
++    struct fts_ts_data *ts_data = fts_data;
++    FTS_FUNC_ENTER();
++    if (fts_esdcheck_data.mode == ENABLE) {
++        if (enable) {
++            FTS_DEBUG("ESD check start");
++            fts_esdcheck_data.flow_work_hold_cnt = 0;
++            fts_esdcheck_data.flow_work_cnt_last = 0;
++            fts_esdcheck_data.intr = 0;
++            fts_esdcheck_data.intr_cnt = 0;
++            queue_delayed_work(ts_data->ts_workqueue,
++                               &ts_data->esdcheck_work,
++                               msecs_to_jiffies(ESDCHECK_WAIT_TIME));
++        } else {
++            FTS_DEBUG("ESD check stop");
++            cancel_delayed_work_sync(&ts_data->esdcheck_work);
++        }
++    }
++
++    FTS_FUNC_EXIT();
++    return 0;
++}
++
++int fts_esdcheck_suspend(void)
++{
++    FTS_FUNC_ENTER();
++    fts_esdcheck_switch(DISABLE);
++    fts_esdcheck_data.suspend = 1;
++    fts_esdcheck_data.intr = 0;
++    fts_esdcheck_data.intr_cnt = 0;
++    FTS_FUNC_EXIT();
++    return 0;
++}
++
++int fts_esdcheck_resume( void )
++{
++    FTS_FUNC_ENTER();
++    fts_esdcheck_switch(ENABLE);
++    fts_esdcheck_data.suspend = 0;
++    fts_esdcheck_data.intr = 0;
++    fts_esdcheck_data.intr_cnt = 0;
++    FTS_FUNC_EXIT();
++    return 0;
++}
++
++static ssize_t fts_esdcheck_store(
++    struct device *dev,
++    struct device_attribute *attr, const char *buf, size_t count)
++{
++    struct input_dev *input_dev = fts_data->input_dev;
++
++    mutex_lock(&input_dev->mutex);
++    if (FTS_SYSFS_ECHO_ON(buf)) {
++        FTS_DEBUG("enable esdcheck");
++        fts_esdcheck_data.mode = ENABLE;
++        fts_esdcheck_switch(ENABLE);
++    } else if (FTS_SYSFS_ECHO_OFF(buf)) {
++        FTS_DEBUG("disable esdcheck");
++        fts_esdcheck_switch(DISABLE);
++        fts_esdcheck_data.mode = DISABLE;
++    }
++    mutex_unlock(&input_dev->mutex);
++
++    return count;
++}
++
++static ssize_t fts_esdcheck_show(
++    struct device *dev, struct device_attribute *attr, char *buf)
++{
++    int count;
++    struct input_dev *input_dev = fts_data->input_dev;
++
++    mutex_lock(&input_dev->mutex);
++    count = snprintf(buf, PAGE_SIZE, "Esd check: %s\n", \
++                     fts_esdcheck_get_status() ? "On" : "Off");
++    mutex_unlock(&input_dev->mutex);
++
++    return count;
++}
++
++/* sysfs esd node
++ *   read example: cat  fts_esd_mode        ---read esd mode
++ *   write example:echo 01 > fts_esd_mode   ---make esdcheck enable
++ *
++ */
++static DEVICE_ATTR (fts_esd_mode, S_IRUGO | S_IWUSR, fts_esdcheck_show, fts_esdcheck_store);
++
++static struct attribute *fts_esd_mode_attrs[] = {
++
++    &dev_attr_fts_esd_mode.attr,
++    NULL,
++};
++
++static struct attribute_group fts_esd_group = {
++    .attrs = fts_esd_mode_attrs,
++};
++
++int fts_create_esd_sysfs(struct device *dev)
++{
++    int ret = 0;
++
++    ret = sysfs_create_group(&dev->kobj, &fts_esd_group);
++    if ( ret != 0) {
++        FTS_ERROR("fts_create_esd_sysfs(sysfs) create fail");
++        sysfs_remove_group(&dev->kobj, &fts_esd_group);
++        return ret;
++    }
++    return 0;
++}
++
++int fts_esdcheck_init(struct fts_ts_data *ts_data)
++{
++    FTS_FUNC_ENTER();
++
++    if (ts_data->ts_workqueue) {
++        INIT_DELAYED_WORK(&ts_data->esdcheck_work, esdcheck_func);
++    } else {
++        FTS_ERROR("fts workqueue is NULL, can't run esd check function");
++        return -EINVAL;
++    }
++
++    memset((u8 *)&fts_esdcheck_data, 0, sizeof(struct fts_esdcheck_st));
++
++    fts_esdcheck_data.mode = ENABLE;
++    fts_esdcheck_data.intr = 0;
++    fts_esdcheck_data.intr_cnt = 0;
++    fts_esdcheck_switch(ENABLE);
++    fts_create_esd_sysfs(ts_data->dev);
++    FTS_FUNC_EXIT();
++    return 0;
++}
++
++int fts_esdcheck_exit(struct fts_ts_data *ts_data)
++{
++    sysfs_remove_group(&ts_data->dev->kobj, &fts_esd_group);
++    return 0;
++}
++#endif /* FTS_ESDCHECK_EN */
++
+diff --git a/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_ex_fun.c b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_ex_fun.c
+new file mode 100644
+index 000000000..75962a093
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_ex_fun.c
+@@ -0,0 +1,1187 @@
++/*
++ *
++ * FocalTech TouchScreen driver.
++ *
++ * Copyright (c) 2012-2019, Focaltech Ltd. All rights reserved.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++/*****************************************************************************
++*
++* File Name: Focaltech_ex_fun.c
++*
++* Author: Focaltech Driver Team
++*
++* Created: 2016-08-08
++*
++* Abstract:
++*
++* Reference:
++*
++*****************************************************************************/
++
++/*****************************************************************************
++* 1.Included header files
++*****************************************************************************/
++#include "focaltech_core.h"
++
++/*****************************************************************************
++* Private constant and macro definitions using #define
++*****************************************************************************/
++#define PROC_UPGRADE                            0
++#define PROC_READ_REGISTER                      1
++#define PROC_WRITE_REGISTER                     2
++#define PROC_AUTOCLB                            4
++#define PROC_UPGRADE_INFO                       5
++#define PROC_WRITE_DATA                         6
++#define PROC_READ_DATA                          7
++#define PROC_SET_TEST_FLAG                      8
++#define PROC_SET_SLAVE_ADDR                     10
++#define PROC_HW_RESET                           11
++#define PROC_READ_STATUS                        12
++#define PROC_SET_BOOT_MODE                      13
++#define PROC_ENTER_TEST_ENVIRONMENT             14
++#define PROC_NAME                               "ftxxxx-debug"
++#define PROC_BUF_SIZE                           256
++
++/*****************************************************************************
++* Private enumerations, structures and unions using typedef
++*****************************************************************************/
++enum {
++    RWREG_OP_READ = 0,
++    RWREG_OP_WRITE = 1,
++};
++
++/*****************************************************************************
++* Static variables
++*****************************************************************************/
++static struct rwreg_operation_t {
++    int type;           /*  0: read, 1: write */
++    int reg;            /*  register */
++    int len;            /*  read/write length */
++    int val;            /*  length = 1; read: return value, write: op return */
++    int res;            /*  0: success, otherwise: fail */
++    char *opbuf;        /*  length >= 1, read return value, write: op return */
++} rw_op;
++
++/*****************************************************************************
++* Global variable or extern global variabls/functions
++*****************************************************************************/
++
++/*****************************************************************************
++* Static function prototypes
++*****************************************************************************/
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
++static ssize_t fts_debug_write(
++    struct file *filp, const char __user *buff, size_t count, loff_t *ppos)
++{
++    u8 *writebuf = NULL;
++    u8 tmpbuf[PROC_BUF_SIZE] = { 0 };
++    int buflen = count;
++    int writelen = 0;
++    int ret = 0;
++    char tmp[PROC_BUF_SIZE];
++    struct fts_ts_data *ts_data = fts_data;
++    struct ftxxxx_proc *proc = &ts_data->proc;
++
++    if ((buflen <= 1) || (buflen > PAGE_SIZE)) {
++        FTS_ERROR("apk proc wirte count(%d>%d) fail", buflen, (int)PAGE_SIZE);
++        return -EINVAL;
++    }
++
++    if (buflen > PROC_BUF_SIZE) {
++        writebuf = (u8 *)kzalloc(buflen * sizeof(u8), GFP_KERNEL);
++        if (NULL == writebuf) {
++            FTS_ERROR("apk proc wirte buf zalloc fail");
++            return -ENOMEM;
++        }
++    } else {
++        writebuf = tmpbuf;
++    }
++
++    if (copy_from_user(writebuf, buff, buflen)) {
++        FTS_ERROR("[APK]: copy from user error!!");
++        ret = -EFAULT;
++        goto proc_write_err;
++    }
++
++    proc->opmode = writebuf[0];
++    switch (proc->opmode) {
++    case PROC_SET_TEST_FLAG:
++        FTS_DEBUG("[APK]: PROC_SET_TEST_FLAG = %x", writebuf[1]);
++        if (writebuf[1] == 0) {
++#if FTS_ESDCHECK_EN
++            fts_esdcheck_switch(ENABLE);
++#endif
++        } else {
++#if FTS_ESDCHECK_EN
++            fts_esdcheck_switch(DISABLE);
++#endif
++        }
++        break;
++
++    case PROC_READ_REGISTER:
++        proc->cmd[0] = writebuf[1];
++        break;
++
++    case PROC_WRITE_REGISTER:
++        ret = fts_write_reg(writebuf[1], writebuf[2]);
++        if (ret < 0) {
++            FTS_ERROR("PROC_WRITE_REGISTER write error");
++            goto proc_write_err;
++        }
++        break;
++
++    case PROC_READ_DATA:
++        writelen = buflen - 1;
++        if (writelen >= FTX_MAX_COMMMAND_LENGTH) {
++            FTS_ERROR("cmd(PROC_READ_DATA) length(%d) fail", writelen);
++            goto proc_write_err;
++        }
++        memcpy(proc->cmd, writebuf + 1, writelen);
++        proc->cmd_len = writelen;
++        ret = fts_write(writebuf + 1, writelen);
++        if (ret < 0) {
++            FTS_ERROR("PROC_READ_DATA write error");
++            goto proc_write_err;
++        }
++        break;
++
++    case PROC_WRITE_DATA:
++        writelen = buflen - 1;
++        ret = fts_write(writebuf + 1, writelen);
++        if (ret < 0) {
++            FTS_ERROR("PROC_WRITE_DATA write error");
++            goto proc_write_err;
++        }
++        break;
++
++    case PROC_SET_SLAVE_ADDR:
++        break;
++
++    case PROC_HW_RESET:
++        snprintf(tmp, PROC_BUF_SIZE, "%s", writebuf + 1);
++        tmp[buflen - 1] = '\0';
++        if (strncmp(tmp, "focal_driver", 12) == 0) {
++            FTS_INFO("APK execute HW Reset");
++            fts_reset_proc(0);
++        }
++        break;
++
++    case PROC_SET_BOOT_MODE:
++        FTS_DEBUG("[APK]: PROC_SET_BOOT_MODE = %x", writebuf[1]);
++        if (0 == writebuf[1]) {
++            ts_data->fw_is_running = true;
++        } else {
++            ts_data->fw_is_running = false;
++        }
++        break;
++    case PROC_ENTER_TEST_ENVIRONMENT:
++        FTS_DEBUG("[APK]: PROC_ENTER_TEST_ENVIRONMENT = %x", writebuf[1]);
++#if FTS_AUTO_UPGRADE_EN
++        if (0 == writebuf[1]) {
++            fts_enter_test_environment(0);
++        } else {
++            fts_enter_test_environment(1);
++        }
++#endif
++        break;
++
++    default:
++        break;
++    }
++
++    ret = buflen;
++proc_write_err:
++    if ((buflen > PROC_BUF_SIZE) && writebuf) {
++        kfree(writebuf);
++        writebuf = NULL;
++    }
++    return ret;
++}
++
++static ssize_t fts_debug_read(
++    struct file *filp, char __user *buff, size_t count, loff_t *ppos)
++{
++    int ret = 0;
++    int num_read_chars = 0;
++    int buflen = count;
++    u8 *readbuf = NULL;
++    u8 tmpbuf[PROC_BUF_SIZE] = { 0 };
++    struct fts_ts_data *ts_data = fts_data;
++    struct ftxxxx_proc *proc = &ts_data->proc;
++
++    if ((buflen <= 0) || (buflen > PAGE_SIZE)) {
++        FTS_ERROR("apk proc read count(%d>%d) fail", buflen, (int)PAGE_SIZE);
++        return -EINVAL;
++    }
++
++    if (buflen > PROC_BUF_SIZE) {
++        readbuf = (u8 *)kzalloc(buflen * sizeof(u8), GFP_KERNEL);
++        if (NULL == readbuf) {
++            FTS_ERROR("apk proc wirte buf zalloc fail");
++            return -ENOMEM;
++        }
++    } else {
++        readbuf = tmpbuf;
++    }
++
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_proc_busy(1);
++#endif
++
++    switch (proc->opmode) {
++    case PROC_READ_REGISTER:
++        num_read_chars = 1;
++        ret = fts_read_reg(proc->cmd[0], &readbuf[0]);
++        if (ret < 0) {
++            FTS_ERROR("PROC_READ_REGISTER read error");
++            goto proc_read_err;
++        }
++        break;
++    case PROC_WRITE_REGISTER:
++        break;
++
++    case PROC_READ_DATA:
++        num_read_chars = buflen;
++        ret = fts_read(NULL, 0, readbuf, num_read_chars);
++        if (ret < 0) {
++            FTS_ERROR("PROC_READ_DATA read error");
++            goto proc_read_err;
++        }
++        break;
++
++    case PROC_WRITE_DATA:
++        break;
++
++    default:
++        break;
++    }
++
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_proc_busy(0);
++#endif
++
++    if (copy_to_user(buff, readbuf, num_read_chars)) {
++        FTS_ERROR("copy to user error");
++        ret = -EFAULT;
++        goto proc_read_err;
++    }
++
++    ret = num_read_chars;
++proc_read_err:
++    if ((buflen > PROC_BUF_SIZE) && readbuf) {
++        kfree(readbuf);
++        readbuf = NULL;
++    }
++    return ret;
++}
++
++static const struct file_operations fts_proc_fops = {
++    .owner  = THIS_MODULE,
++    .read   = fts_debug_read,
++    .write  = fts_debug_write,
++};
++#else
++static int fts_debug_write(
++    struct file *filp, const char __user *buff, unsigned long len, void *data)
++{
++    u8 *writebuf = NULL;
++    u8 tmpbuf[PROC_BUF_SIZE] = { 0 };
++    int buflen = count;
++    int writelen = 0;
++    int ret = 0;
++    char tmp[PROC_BUF_SIZE];
++    struct fts_ts_data *ts_data = fts_data;
++    struct ftxxxx_proc *proc = &ts_data->proc;
++
++    if ((buflen <= 1) || (buflen > PAGE_SIZE)) {
++        FTS_ERROR("apk proc wirte count(%d>%d) fail", buflen, (int)PAGE_SIZE);
++        return -EINVAL;
++    }
++
++    if (buflen > PROC_BUF_SIZE) {
++        writebuf = (u8 *)kzalloc(buflen * sizeof(u8), GFP_KERNEL);
++        if (NULL == writebuf) {
++            FTS_ERROR("apk proc wirte buf zalloc fail");
++            return -ENOMEM;
++        }
++    } else {
++        writebuf = tmpbuf;
++    }
++
++    if (copy_from_user(writebuf, buff, buflen)) {
++        FTS_ERROR("[APK]: copy from user error!!");
++        ret = -EFAULT;
++        goto proc_write_err;
++    }
++
++    proc->opmode = writebuf[0];
++    switch (proc->opmode) {
++    case PROC_SET_TEST_FLAG:
++        FTS_DEBUG("[APK]: PROC_SET_TEST_FLAG = %x", writebuf[1]);
++        if (writebuf[1] == 0) {
++#if FTS_ESDCHECK_EN
++            fts_esdcheck_switch(ENABLE);
++#endif
++        } else {
++#if FTS_ESDCHECK_EN
++            fts_esdcheck_switch(DISABLE);
++#endif
++        }
++        break;
++
++    case PROC_READ_REGISTER:
++        proc->cmd[0] = writebuf[1];
++        break;
++
++    case PROC_WRITE_REGISTER:
++        ret = fts_write_reg(writebuf[1], writebuf[2]);
++        if (ret < 0) {
++            FTS_ERROR("PROC_WRITE_REGISTER write error");
++            goto proc_write_err;
++        }
++        break;
++
++    case PROC_READ_DATA:
++        writelen = buflen - 1;
++        if (writelen >= FTX_MAX_COMMMAND_LENGTH) {
++            FTS_ERROR("cmd(PROC_READ_DATA) length(%d) fail", writelen);
++            goto proc_write_err;
++        }
++        memcpy(proc->cmd, writebuf + 1, writelen);
++        proc->cmd_len = writelen;
++        ret = fts_write(writebuf + 1, writelen);
++        if (ret < 0) {
++            FTS_ERROR("PROC_READ_DATA write error");
++            goto proc_write_err;
++        }
++        break;
++
++    case PROC_WRITE_DATA:
++        writelen = buflen - 1;
++        ret = fts_write(writebuf + 1, writelen);
++        if (ret < 0) {
++            FTS_ERROR("PROC_WRITE_DATA write error");
++            goto proc_write_err;
++        }
++        break;
++
++    case PROC_SET_SLAVE_ADDR:
++        break;
++
++    case PROC_HW_RESET:
++        snprintf(tmp, PROC_BUF_SIZE, "%s", writebuf + 1);
++        tmp[buflen - 1] = '\0';
++        if (strncmp(tmp, "focal_driver", 12) == 0) {
++            FTS_INFO("APK execute HW Reset");
++            fts_reset_proc(0);
++        }
++        break;
++
++    case PROC_SET_BOOT_MODE:
++        FTS_DEBUG("[APK]: PROC_SET_BOOT_MODE = %x", writebuf[1]);
++        if (0 == writebuf[1]) {
++            ts_data->fw_is_running = true;
++        } else {
++            ts_data->fw_is_running = false;
++        }
++        break;
++    case PROC_ENTER_TEST_ENVIRONMENT:
++        FTS_DEBUG("[APK]: PROC_ENTER_TEST_ENVIRONMENT = %x", writebuf[1]);
++        if (0 == writebuf[1]) {
++            fts_enter_test_environment(0);
++        } else {
++            fts_enter_test_environment(1);
++        }
++        break;
++
++    default:
++        break;
++    }
++
++    ret = buflen;
++proc_write_err:
++    if ((buflen > PROC_BUF_SIZE) && writebuf) {
++        kfree(writebuf);
++        writebuf = NULL;
++    }
++    return ret;
++}
++
++static int fts_debug_read(
++    char *page, char **start, off_t off, int count, int *eof, void *data )
++{
++    int ret = 0;
++    int num_read_chars = 0;
++    int buflen = count;
++    u8 *readbuf = NULL;
++    u8 tmpbuf[PROC_BUF_SIZE] = { 0 };
++    struct fts_ts_data *ts_data = fts_data;
++    struct ftxxxx_proc *proc = &ts_data->proc;
++
++    if ((buflen <= 0) || (buflen > PAGE_SIZE)) {
++        FTS_ERROR("apk proc read count(%d>%d) fail", buflen, (int)PAGE_SIZE);
++        return -EINVAL;
++    }
++
++    if (buflen > PROC_BUF_SIZE) {
++        readbuf = (u8 *)kzalloc(buflen * sizeof(u8), GFP_KERNEL);
++        if (NULL == readbuf) {
++            FTS_ERROR("apk proc wirte buf zalloc fail");
++            return -ENOMEM;
++        }
++    } else {
++        readbuf = tmpbuf;
++    }
++
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_proc_busy(1);
++#endif
++
++    switch (proc->opmode) {
++    case PROC_READ_REGISTER:
++        num_read_chars = 1;
++        ret = fts_read_reg(proc->cmd[0], &readbuf[0]);
++        if (ret < 0) {
++            FTS_ERROR("PROC_READ_REGISTER read error");
++            goto proc_read_err;
++        }
++        break;
++    case PROC_WRITE_REGISTER:
++        break;
++
++    case PROC_READ_DATA:
++        num_read_chars = buflen;
++        ret = fts_read(NULL, 0, readbuf, num_read_chars);
++        if (ret < 0) {
++            FTS_ERROR("PROC_READ_DATA read error");
++            goto proc_read_err;
++        }
++        break;
++
++    case PROC_WRITE_DATA:
++        break;
++
++    default:
++        break;
++    }
++
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_proc_busy(0);
++#endif
++
++    if (copy_to_user(buff, readbuf, num_read_chars)) {
++        FTS_ERROR("copy to user error");
++        ret = -EFAULT;
++        goto proc_read_err;
++    }
++
++    ret = num_read_chars;
++proc_read_err:
++    if ((buflen > PROC_BUF_SIZE) && readbuf) {
++        kfree(readbuf);
++        readbuf = NULL;
++    }
++    return ret;
++}
++#endif
++
++int fts_create_apk_debug_channel(struct fts_ts_data *ts_data)
++{
++    struct ftxxxx_proc *proc = &ts_data->proc;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
++    proc->proc_entry = proc_create(PROC_NAME, 0777, NULL, &fts_proc_fops);
++    if (NULL == proc->proc_entry) {
++        FTS_ERROR("create proc entry fail");
++        return -ENOMEM;
++    }
++#else
++    proc->proc_entry = create_proc_entry(PROC_NAME, 0777, NULL);
++    if (NULL == proc->proc_entry) {
++        FTS_ERROR("create proc entry fail");
++        return -ENOMEM;
++    }
++    proc->proc_entry->write_proc = fts_debug_write;
++    proc->proc_entry->read_proc = fts_debug_read;
++#endif
++
++    FTS_INFO("Create proc entry success!");
++    return 0;
++}
++
++void fts_release_apk_debug_channel(struct fts_ts_data *ts_data)
++{
++    struct ftxxxx_proc *proc = &ts_data->proc;
++
++    if (proc->proc_entry) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
++        proc_remove(proc->proc_entry);
++#else
++        remove_proc_entry(PROC_NAME, NULL);
++#endif
++    }
++}
++
++/************************************************************************
++ * sysfs interface
++ ***********************************************************************/
++/* fts_hw_reset interface */
++static ssize_t fts_hw_reset_show(
++    struct device *dev, struct device_attribute *attr, char *buf)
++{
++    struct input_dev *input_dev = fts_data->input_dev;
++    ssize_t count = 0;
++
++    mutex_lock(&input_dev->mutex);
++    fts_reset_proc(0);
++    count = snprintf(buf, PAGE_SIZE, "hw reset executed\n");
++    mutex_unlock(&input_dev->mutex);
++
++    return count;
++}
++
++static ssize_t fts_hw_reset_store(
++    struct device *dev,
++    struct device_attribute *attr, const char *buf, size_t count)
++{
++    return -EPERM;
++}
++
++/* fts_irq interface */
++static ssize_t fts_irq_show(
++    struct device *dev, struct device_attribute *attr, char *buf)
++{
++    ssize_t count = 0;
++    struct irq_desc *desc = irq_to_desc(fts_data->irq);
++
++    count = snprintf(buf, PAGE_SIZE, "irq_depth:%d\n", desc->depth);
++
++    return count;
++}
++
++static ssize_t fts_irq_store(
++    struct device *dev,
++    struct device_attribute *attr, const char *buf, size_t count)
++{
++    struct input_dev *input_dev = fts_data->input_dev;
++
++    mutex_lock(&input_dev->mutex);
++    if (FTS_SYSFS_ECHO_ON(buf)) {
++        FTS_INFO("enable irq");
++        fts_irq_enable();
++    } else if (FTS_SYSFS_ECHO_OFF(buf)) {
++        FTS_INFO("disable irq");
++        fts_irq_disable();
++    }
++    mutex_unlock(&input_dev->mutex);
++    return count;
++}
++
++/* fts_boot_mode interface */
++static ssize_t fts_bootmode_store(
++    struct device *dev,
++    struct device_attribute *attr, const char *buf, size_t count)
++{
++    struct input_dev *input_dev = fts_data->input_dev;
++
++    FTS_FUNC_ENTER();
++    mutex_lock(&input_dev->mutex);
++    if (FTS_SYSFS_ECHO_ON(buf)) {
++        FTS_INFO("[EX-FUN]set to boot mode");
++        fts_data->fw_is_running = false;
++    } else if (FTS_SYSFS_ECHO_OFF(buf)) {
++        FTS_INFO("[EX-FUN]set to fw mode");
++        fts_data->fw_is_running = true;
++    }
++    mutex_unlock(&input_dev->mutex);
++    FTS_FUNC_EXIT();
++
++    return count;
++}
++
++static ssize_t fts_bootmode_show(
++    struct device *dev, struct device_attribute *attr, char *buf)
++{
++    ssize_t count = 0;
++    struct input_dev *input_dev = fts_data->input_dev;
++
++    FTS_FUNC_ENTER();
++    mutex_lock(&input_dev->mutex);
++    if (true == fts_data->fw_is_running) {
++        count = snprintf(buf, PAGE_SIZE, "tp is in fw mode\n");
++    } else {
++        count = snprintf(buf, PAGE_SIZE, "tp is in boot mode\n");
++    }
++    mutex_unlock(&input_dev->mutex);
++    FTS_FUNC_EXIT();
++
++    return count;
++}
++
++/* fts_tpfwver interface */
++static ssize_t fts_tpfwver_show(
++    struct device *dev, struct device_attribute *attr, char *buf)
++{
++    struct fts_ts_data *ts_data = fts_data;
++    struct input_dev *input_dev = ts_data->input_dev;
++    ssize_t num_read_chars = 0;
++    u8 fwver = 0;
++
++    mutex_lock(&input_dev->mutex);
++
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_proc_busy(1);
++#endif
++    fts_read_reg(FTS_REG_FW_VER, &fwver);
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_proc_busy(0);
++#endif
++    if ((fwver == 0xFF) || (fwver == 0x00))
++        num_read_chars = snprintf(buf, PAGE_SIZE, "get tp fw version fail!\n");
++    else
++        num_read_chars = snprintf(buf, PAGE_SIZE, "%02x\n", fwver);
++
++    mutex_unlock(&input_dev->mutex);
++    return num_read_chars;
++}
++
++static ssize_t fts_tpfwver_store(
++    struct device *dev,
++    struct device_attribute *attr, const char *buf, size_t count)
++{
++    return -EPERM;
++}
++
++/* fts_rw_reg */
++static ssize_t fts_tprwreg_show(
++    struct device *dev, struct device_attribute *attr, char *buf)
++{
++    int count;
++    int i;
++    struct input_dev *input_dev = fts_data->input_dev;
++
++    mutex_lock(&input_dev->mutex);
++
++    if (rw_op.len < 0) {
++        count = snprintf(buf, PAGE_SIZE, "Invalid cmd line\n");
++    } else if (rw_op.len == 1) {
++        if (RWREG_OP_READ == rw_op.type) {
++            if (rw_op.res == 0) {
++                count = snprintf(buf, PAGE_SIZE, "Read %02X: %02X\n", rw_op.reg, rw_op.val);
++            } else {
++                count = snprintf(buf, PAGE_SIZE, "Read %02X failed, ret: %d\n", rw_op.reg,  rw_op.res);
++            }
++        } else {
++            if (rw_op.res == 0) {
++                count = snprintf(buf, PAGE_SIZE, "Write %02X, %02X success\n", rw_op.reg,  rw_op.val);
++            } else {
++                count = snprintf(buf, PAGE_SIZE, "Write %02X failed, ret: %d\n", rw_op.reg,  rw_op.res);
++            }
++        }
++    } else {
++        if (RWREG_OP_READ == rw_op.type) {
++            count = snprintf(buf, PAGE_SIZE, "Read Reg: [%02X]-[%02X]\n", rw_op.reg, rw_op.reg + rw_op.len);
++            count += snprintf(buf + count, PAGE_SIZE, "Result: ");
++            if (rw_op.res) {
++                count += snprintf(buf + count, PAGE_SIZE, "failed, ret: %d\n", rw_op.res);
++            } else {
++                if (rw_op.opbuf) {
++                    for (i = 0; i < rw_op.len; i++) {
++                        count += snprintf(buf + count, PAGE_SIZE, "%02X ", rw_op.opbuf[i]);
++                    }
++                    count += snprintf(buf + count, PAGE_SIZE, "\n");
++                }
++            }
++        } else {
++            ;
++            count = snprintf(buf, PAGE_SIZE, "Write Reg: [%02X]-[%02X]\n", rw_op.reg, rw_op.reg + rw_op.len - 1);
++            count += snprintf(buf + count, PAGE_SIZE, "Write Data: ");
++            if (rw_op.opbuf) {
++                for (i = 1; i < rw_op.len; i++) {
++                    count += snprintf(buf + count, PAGE_SIZE, "%02X ", rw_op.opbuf[i]);
++                }
++                count += snprintf(buf + count, PAGE_SIZE, "\n");
++            }
++            if (rw_op.res) {
++                count += snprintf(buf + count, PAGE_SIZE, "Result: failed, ret: %d\n", rw_op.res);
++            } else {
++                count += snprintf(buf + count, PAGE_SIZE, "Result: success\n");
++            }
++        }
++        /*if (rw_op.opbuf) {
++            kfree(rw_op.opbuf);
++            rw_op.opbuf = NULL;
++        }*/
++    }
++    mutex_unlock(&input_dev->mutex);
++
++    return count;
++}
++
++static int shex_to_int(const char *hex_buf, int size)
++{
++    int i;
++    int base = 1;
++    int value = 0;
++    char single;
++
++    for (i = size - 1; i >= 0; i--) {
++        single = hex_buf[i];
++
++        if ((single >= '0') && (single <= '9')) {
++            value += (single - '0') * base;
++        } else if ((single >= 'a') && (single <= 'z')) {
++            value += (single - 'a' + 10) * base;
++        } else if ((single >= 'A') && (single <= 'Z')) {
++            value += (single - 'A' + 10) * base;
++        } else {
++            return -EINVAL;
++        }
++
++        base *= 16;
++    }
++
++    return value;
++}
++
++
++static u8 shex_to_u8(const char *hex_buf, int size)
++{
++    return (u8)shex_to_int(hex_buf, size);
++}
++/*
++ * Format buf:
++ * [0]: '0' write, '1' read(reserved)
++ * [1-2]: addr, hex
++ * [3-4]: length, hex
++ * [5-6]...[n-(n+1)]: data, hex
++ */
++static int fts_parse_buf(const char *buf, size_t cmd_len)
++{
++    int length;
++    int i;
++    char *tmpbuf;
++
++    rw_op.reg = shex_to_u8(buf + 1, 2);
++    length = shex_to_int(buf + 3, 2);
++
++    if (buf[0] == '1') {
++        rw_op.len = length;
++        rw_op.type = RWREG_OP_READ;
++        FTS_DEBUG("read %02X, %d bytes", rw_op.reg, rw_op.len);
++    } else {
++        if (cmd_len < (length * 2 + 5)) {
++            pr_err("data invalided!\n");
++            return -EINVAL;
++        }
++        FTS_DEBUG("write %02X, %d bytes", rw_op.reg, length);
++
++        /* first byte is the register addr */
++        rw_op.type = RWREG_OP_WRITE;
++        rw_op.len = length + 1;
++    }
++
++    if (rw_op.len > 0) {
++        tmpbuf = (char *)kzalloc(rw_op.len, GFP_KERNEL);
++        if (!tmpbuf) {
++            FTS_ERROR("allocate memory failed!\n");
++            return -ENOMEM;
++        }
++
++        if (RWREG_OP_WRITE == rw_op.type) {
++            tmpbuf[0] = rw_op.reg & 0xFF;
++            FTS_DEBUG("write buffer: ");
++            for (i = 1; i < rw_op.len; i++) {
++                tmpbuf[i] = shex_to_u8(buf + 5 + i * 2 - 2, 2);
++                FTS_DEBUG("buf[%d]: %02X", i, tmpbuf[i] & 0xFF);
++            }
++        }
++        rw_op.opbuf = tmpbuf;
++    }
++
++    return rw_op.len;
++}
++
++static ssize_t fts_tprwreg_store(
++    struct device *dev,
++    struct device_attribute *attr, const char *buf, size_t count)
++{
++    struct input_dev *input_dev = fts_data->input_dev;
++    ssize_t cmd_length = 0;
++
++    mutex_lock(&input_dev->mutex);
++    cmd_length = count - 1;
++
++    if (rw_op.opbuf) {
++        kfree(rw_op.opbuf);
++        rw_op.opbuf = NULL;
++    }
++
++    FTS_DEBUG("cmd len: %d, buf: %s", (int)cmd_length, buf);
++    /* compatible old ops */
++    if (2 == cmd_length) {
++        rw_op.type = RWREG_OP_READ;
++        rw_op.len = 1;
++        rw_op.reg = shex_to_int(buf, 2);
++    } else if (4 == cmd_length) {
++        rw_op.type = RWREG_OP_WRITE;
++        rw_op.len = 1;
++        rw_op.reg = shex_to_int(buf, 2);
++        rw_op.val = shex_to_int(buf + 2, 2);
++    } else if (cmd_length < 5) {
++        FTS_ERROR("Invalid cmd buffer");
++        mutex_unlock(&input_dev->mutex);
++        return -EINVAL;
++    } else {
++        rw_op.len = fts_parse_buf(buf, cmd_length);
++    }
++
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_proc_busy(1);
++#endif
++    if (rw_op.len < 0) {
++        FTS_ERROR("cmd buffer error!");
++
++    } else {
++        if (RWREG_OP_READ == rw_op.type) {
++            if (rw_op.len == 1) {
++                u8 reg, val;
++                reg = rw_op.reg & 0xFF;
++                rw_op.res = fts_read_reg(reg, &val);
++                rw_op.val = val;
++            } else {
++                char reg;
++                reg = rw_op.reg & 0xFF;
++
++                rw_op.res = fts_read(&reg, 1, rw_op.opbuf, rw_op.len);
++            }
++
++            if (rw_op.res < 0) {
++                FTS_ERROR("Could not read 0x%02x", rw_op.reg);
++            } else {
++                FTS_INFO("read 0x%02x, %d bytes successful", rw_op.reg, rw_op.len);
++                rw_op.res = 0;
++            }
++
++        } else {
++            if (rw_op.len == 1) {
++                u8 reg, val;
++                reg = rw_op.reg & 0xFF;
++                val = rw_op.val & 0xFF;
++                rw_op.res = fts_write_reg(reg, val);
++            } else {
++                rw_op.res = fts_write(rw_op.opbuf, rw_op.len);
++            }
++            if (rw_op.res < 0) {
++                FTS_ERROR("Could not write 0x%02x", rw_op.reg);
++
++            } else {
++                FTS_INFO("Write 0x%02x, %d bytes successful", rw_op.val, rw_op.len);
++                rw_op.res = 0;
++            }
++        }
++    }
++
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_proc_busy(0);
++#endif
++    mutex_unlock(&input_dev->mutex);
++
++    return count;
++}
++
++/* fts_upgrade_bin interface */
++static ssize_t fts_fwupgradebin_show(
++    struct device *dev, struct device_attribute *attr, char *buf)
++{
++    return -EPERM;
++}
++
++static ssize_t fts_fwupgradebin_store(
++    struct device *dev,
++    struct device_attribute *attr, const char *buf, size_t count)
++{
++    char fwname[FILE_NAME_LENGTH] = { 0 };
++    struct input_dev *input_dev = fts_data->input_dev;
++
++    if ((count <= 1) || (count >= FILE_NAME_LENGTH - 32)) {
++        FTS_ERROR("fw bin name's length(%d) fail", (int)count);
++        return -EINVAL;
++    }
++    memset(fwname, 0, sizeof(fwname));
++    snprintf(fwname, FILE_NAME_LENGTH, "%s", buf);
++    fwname[count - 1] = '\0';
++
++    FTS_INFO("upgrade with bin file through sysfs node");
++    mutex_lock(&input_dev->mutex);
++#if FTS_AUTO_UPGRADE_EN
++    fts_upgrade_bin(fwname, 0);
++#endif
++    mutex_unlock(&input_dev->mutex);
++
++    return count;
++}
++
++/* fts_force_upgrade interface */
++static ssize_t fts_fwforceupg_show(
++    struct device *dev, struct device_attribute *attr, char *buf)
++{
++    return -EPERM;
++}
++
++static ssize_t fts_fwforceupg_store(
++    struct device *dev,
++    struct device_attribute *attr, const char *buf, size_t count)
++{
++    char fwname[FILE_NAME_LENGTH];
++    struct input_dev *input_dev = fts_data->input_dev;
++
++    if ((count <= 1) || (count >= FILE_NAME_LENGTH - 32)) {
++        FTS_ERROR("fw bin name's length(%d) fail", (int)count);
++        return -EINVAL;
++    }
++    memset(fwname, 0, sizeof(fwname));
++    snprintf(fwname, FILE_NAME_LENGTH, "%s", buf);
++    fwname[count - 1] = '\0';
++
++    FTS_INFO("force upgrade through sysfs node");
++#if FTS_AUTO_UPGRADE_EN
++    mutex_lock(&input_dev->mutex);
++    fts_upgrade_bin(fwname, 1);
++    mutex_unlock(&input_dev->mutex);
++#endif
++
++    return count;
++}
++
++/* fts_driver_info interface */
++static ssize_t fts_driverinfo_show(
++    struct device *dev, struct device_attribute *attr, char *buf)
++{
++    int count = 0;
++    struct fts_ts_data *ts_data = fts_data;
++    struct fts_ts_platform_data *pdata = ts_data->pdata;
++    struct input_dev *input_dev = ts_data->input_dev;
++
++    mutex_lock(&input_dev->mutex);
++    count += snprintf(buf + count, PAGE_SIZE, "Driver Ver:%s\n", FTS_DRIVER_VERSION);
++
++    count += snprintf(buf + count, PAGE_SIZE, "Resolution:(%d,%d)~(%d,%d)\n",
++                      pdata->x_min, pdata->y_min, pdata->x_max, pdata->y_max);
++
++    count += snprintf(buf + count, PAGE_SIZE, "Max Touchs:%d\n", pdata->max_touch_number);
++
++    count += snprintf(buf + count, PAGE_SIZE, "reset gpio:%d,int gpio:%d,irq:%d\n",
++                      pdata->reset_gpio, pdata->irq_gpio, ts_data->irq);
++
++    count += snprintf(buf + count, PAGE_SIZE, "IC ID:0x%02x%02x\n",
++                      ts_data->ic_info.ids.chip_idh, ts_data->ic_info.ids.chip_idl);
++    mutex_unlock(&input_dev->mutex);
++
++    return count;
++}
++
++static ssize_t fts_driverinfo_store(struct device *dev,
++                                    struct device_attribute *attr, const char *buf, size_t count)
++{
++    return -EPERM;
++}
++
++/* fts_dump_reg interface */
++static ssize_t fts_dumpreg_show(
++    struct device *dev, struct device_attribute *attr, char *buf)
++{
++    int count = 0;
++    u8 val = 0;
++    struct input_dev *input_dev = fts_data->input_dev;
++
++    mutex_lock(&input_dev->mutex);
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_proc_busy(1);
++#endif
++    fts_read_reg(FTS_REG_POWER_MODE, &val);
++    count += snprintf(buf + count, PAGE_SIZE, "Power Mode:0x%02x\n", val);
++
++    fts_read_reg(FTS_REG_FW_VER, &val);
++    count += snprintf(buf + count, PAGE_SIZE, "FW Ver:0x%02x\n", val);
++
++    fts_read_reg(FTS_REG_LIC_VER, &val);
++    count += snprintf(buf + count, PAGE_SIZE, "LCD Initcode Ver:0x%02x\n", val);
++
++    fts_read_reg(FTS_REG_IDE_PARA_VER_ID, &val);
++    count += snprintf(buf + count, PAGE_SIZE, "Param Ver:0x%02x\n", val);
++
++    fts_read_reg(FTS_REG_IDE_PARA_STATUS, &val);
++    count += snprintf(buf + count, PAGE_SIZE, "Param status:0x%02x\n", val);
++
++    fts_read_reg(FTS_REG_VENDOR_ID, &val);
++    count += snprintf(buf + count, PAGE_SIZE, "Vendor ID:0x%02x\n", val);
++
++    fts_read_reg(FTS_REG_LCD_BUSY_NUM, &val);
++    count += snprintf(buf + count, PAGE_SIZE, "LCD Busy Number:0x%02x\n", val);
++
++    fts_read_reg(FTS_REG_GESTURE_EN, &val);
++    count += snprintf(buf + count, PAGE_SIZE, "Gesture Mode:0x%02x\n", val);
++
++    fts_read_reg(FTS_REG_CHARGER_MODE_EN, &val);
++    count += snprintf(buf + count, PAGE_SIZE, "charge stat:0x%02x\n", val);
++
++    fts_read_reg(FTS_REG_INT_CNT, &val);
++    count += snprintf(buf + count, PAGE_SIZE, "INT count:0x%02x\n", val);
++
++    fts_read_reg(FTS_REG_FLOW_WORK_CNT, &val);
++    count += snprintf(buf + count, PAGE_SIZE, "ESD count:0x%02x\n", val);
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_proc_busy(0);
++#endif
++
++    mutex_unlock(&input_dev->mutex);
++
++    return count;
++}
++
++static ssize_t fts_dumpreg_store(
++    struct device *dev,
++    struct device_attribute *attr, const char *buf, size_t count)
++{
++    return -EPERM;
++}
++
++/* fts_dump_reg interface */
++static ssize_t fts_tpbuf_show(
++    struct device *dev, struct device_attribute *attr, char *buf)
++{
++    int count = 0;
++    int i = 0;
++    struct input_dev *input_dev = fts_data->input_dev;
++
++    mutex_lock(&input_dev->mutex);
++    count += snprintf(buf + count, PAGE_SIZE, "touch point buffer:\n");
++    for (i = 0; i < fts_data->pnt_buf_size; i++) {
++        count += snprintf(buf + count, PAGE_SIZE, "%02x ", fts_data->point_buf[i]);
++    }
++    count += snprintf(buf + count, PAGE_SIZE, "\n");
++    mutex_unlock(&input_dev->mutex);
++
++    return count;
++}
++
++static ssize_t fts_tpbuf_store(
++    struct device *dev,
++    struct device_attribute *attr, const char *buf, size_t count)
++{
++    return -EPERM;
++}
++
++/* fts_log_level interface */
++static ssize_t fts_log_level_show(
++    struct device *dev, struct device_attribute *attr, char *buf)
++{
++    int count = 0;
++    struct input_dev *input_dev = fts_data->input_dev;
++
++    mutex_lock(&input_dev->mutex);
++    count += snprintf(buf + count, PAGE_SIZE, "log level:%d\n",
++                      fts_data->log_level);
++    mutex_unlock(&input_dev->mutex);
++
++    return count;
++}
++
++static ssize_t fts_log_level_store(
++    struct device *dev,
++    struct device_attribute *attr, const char *buf, size_t count)
++{
++    int value = 0;
++    struct input_dev *input_dev = fts_data->input_dev;
++
++    FTS_FUNC_ENTER();
++    mutex_lock(&input_dev->mutex);
++    sscanf(buf, "%d", &value);
++    FTS_DEBUG("log level:%d->%d", fts_data->log_level, value);
++    fts_data->log_level = value;
++    mutex_unlock(&input_dev->mutex);
++    FTS_FUNC_EXIT();
++
++    return count;
++}
++
++/* get the fw version  example:cat fw_version */
++static DEVICE_ATTR(fts_fw_version, S_IRUGO | S_IWUSR, fts_tpfwver_show, fts_tpfwver_store);
++
++/* read and write register(s)
++*   All data type is **HEX**
++*   Single Byte:
++*       read:   echo 88 > rw_reg ---read register 0x88
++*       write:  echo 8807 > rw_reg ---write 0x07 into register 0x88
++*   Multi-bytes:
++*       [0:rw-flag][1-2: reg addr, hex][3-4: length, hex][5-6...n-n+1: write data, hex]
++*       rw-flag: 0, write; 1, read
++*       read:  echo 10005           > rw_reg ---read reg 0x00-0x05
++*       write: echo 000050102030405 > rw_reg ---write reg 0x00-0x05 as 01,02,03,04,05
++*  Get result:
++*       cat rw_reg
++*/
++static DEVICE_ATTR(fts_rw_reg, S_IRUGO | S_IWUSR, fts_tprwreg_show, fts_tprwreg_store);
++/*  upgrade from fw bin file   example:echo "*.bin" > fts_upgrade_bin */
++static DEVICE_ATTR(fts_upgrade_bin, S_IRUGO | S_IWUSR, fts_fwupgradebin_show, fts_fwupgradebin_store);
++static DEVICE_ATTR(fts_force_upgrade, S_IRUGO | S_IWUSR, fts_fwforceupg_show, fts_fwforceupg_store);
++static DEVICE_ATTR(fts_driver_info, S_IRUGO | S_IWUSR, fts_driverinfo_show, fts_driverinfo_store);
++static DEVICE_ATTR(fts_dump_reg, S_IRUGO | S_IWUSR, fts_dumpreg_show, fts_dumpreg_store);
++static DEVICE_ATTR(fts_hw_reset, S_IRUGO | S_IWUSR, fts_hw_reset_show, fts_hw_reset_store);
++static DEVICE_ATTR(fts_irq, S_IRUGO | S_IWUSR, fts_irq_show, fts_irq_store);
++static DEVICE_ATTR(fts_boot_mode, S_IRUGO | S_IWUSR, fts_bootmode_show, fts_bootmode_store);
++static DEVICE_ATTR(fts_touch_point, S_IRUGO | S_IWUSR, fts_tpbuf_show, fts_tpbuf_store);
++static DEVICE_ATTR(fts_log_level, S_IRUGO | S_IWUSR, fts_log_level_show, fts_log_level_store);
++
++/* add your attr in here*/
++static struct attribute *fts_attributes[] = {
++    &dev_attr_fts_fw_version.attr,
++    &dev_attr_fts_rw_reg.attr,
++    &dev_attr_fts_dump_reg.attr,
++    &dev_attr_fts_upgrade_bin.attr,
++    &dev_attr_fts_force_upgrade.attr,
++    &dev_attr_fts_driver_info.attr,
++    &dev_attr_fts_hw_reset.attr,
++    &dev_attr_fts_irq.attr,
++    &dev_attr_fts_boot_mode.attr,
++    &dev_attr_fts_touch_point.attr,
++    &dev_attr_fts_log_level.attr,
++    NULL
++};
++
++static struct attribute_group fts_attribute_group = {
++    .attrs = fts_attributes
++};
++
++int fts_create_sysfs(struct fts_ts_data *ts_data)
++{
++    int ret = 0;
++
++    ret = sysfs_create_group(&ts_data->dev->kobj, &fts_attribute_group);
++    if (ret) {
++        FTS_ERROR("[EX]: sysfs_create_group() failed!!");
++        sysfs_remove_group(&ts_data->dev->kobj, &fts_attribute_group);
++        return -ENOMEM;
++    } else {
++        FTS_INFO("[EX]: sysfs_create_group() succeeded!!");
++    }
++
++    return ret;
++}
++
++int fts_remove_sysfs(struct fts_ts_data *ts_data)
++{
++    sysfs_remove_group(&ts_data->dev->kobj, &fts_attribute_group);
++    return 0;
++}
+diff --git a/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_ex_mode.c b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_ex_mode.c
+new file mode 100644
+index 000000000..c0c970b12
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_ex_mode.c
+@@ -0,0 +1,307 @@
++/*
++ *
++ * FocalTech ftxxxx TouchScreen driver.
++ *
++ * Copyright (c) 2012-2019, Focaltech Ltd. All rights reserved.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++/*****************************************************************************
++*
++* File Name: focaltech_ex_mode.c
++*
++* Author: Focaltech Driver Team
++*
++* Created: 2016-08-31
++*
++* Abstract:
++*
++* Reference:
++*
++*****************************************************************************/
++
++/*****************************************************************************
++* 1.Included header files
++*****************************************************************************/
++#include "focaltech_core.h"
++
++/*****************************************************************************
++* 2.Private constant and macro definitions using #define
++*****************************************************************************/
++
++/*****************************************************************************
++* 3.Private enumerations, structures and unions using typedef
++*****************************************************************************/
++enum _ex_mode {
++    MODE_GLOVE = 0,
++    MODE_COVER,
++    MODE_CHARGER,
++};
++
++/*****************************************************************************
++* 4.Static variables
++*****************************************************************************/
++
++/*****************************************************************************
++* 5.Global variable or extern global variabls/functions
++*****************************************************************************/
++
++/*****************************************************************************
++* 6.Static function prototypes
++*******************************************************************************/
++static int fts_ex_mode_switch(enum _ex_mode mode, u8 value)
++{
++    int ret = 0;
++    u8 m_val = 0;
++
++    if (value)
++        m_val = 0x01;
++    else
++        m_val = 0x00;
++
++    switch (mode) {
++    case MODE_GLOVE:
++        ret = fts_write_reg(FTS_REG_GLOVE_MODE_EN, m_val);
++        if (ret < 0) {
++            FTS_ERROR("MODE_GLOVE switch to %d fail", m_val);
++        }
++        break;
++    case MODE_COVER:
++        ret = fts_write_reg(FTS_REG_COVER_MODE_EN, m_val);
++        if (ret < 0) {
++            FTS_ERROR("MODE_COVER switch to %d fail", m_val);
++        }
++        break;
++    case MODE_CHARGER:
++        ret = fts_write_reg(FTS_REG_CHARGER_MODE_EN, m_val);
++        if (ret < 0) {
++            FTS_ERROR("MODE_CHARGER switch to %d fail", m_val);
++        }
++        break;
++    default:
++        FTS_ERROR("mode(%d) unsupport", mode);
++        ret = -EINVAL;
++        break;
++    }
++
++    return ret;
++}
++
++static ssize_t fts_glove_mode_show(
++    struct device *dev, struct device_attribute *attr, char *buf)
++{
++    int count = 0;
++    u8 val = 0;
++    struct fts_ts_data *ts_data = fts_data;
++    struct input_dev *input_dev = ts_data->input_dev;
++
++    mutex_lock(&input_dev->mutex);
++    fts_read_reg(FTS_REG_GLOVE_MODE_EN, &val);
++    count = snprintf(buf + count, PAGE_SIZE, "Glove Mode:%s\n",
++                     ts_data->glove_mode ? "On" : "Off");
++    count += snprintf(buf + count, PAGE_SIZE, "Glove Reg(0xC0):%d\n", val);
++    mutex_unlock(&input_dev->mutex);
++
++    return count;
++}
++
++static ssize_t fts_glove_mode_store(
++    struct device *dev,
++    struct device_attribute *attr, const char *buf, size_t count)
++{
++    int ret = 0;
++    struct fts_ts_data *ts_data = fts_data;
++
++    if (FTS_SYSFS_ECHO_ON(buf)) {
++        if (!ts_data->glove_mode) {
++            FTS_DEBUG("enter glove mode");
++            ret = fts_ex_mode_switch(MODE_GLOVE, ENABLE);
++            if (ret >= 0) {
++                ts_data->glove_mode = ENABLE;
++            }
++        }
++    } else if (FTS_SYSFS_ECHO_OFF(buf)) {
++        if (ts_data->glove_mode) {
++            FTS_DEBUG("exit glove mode");
++            ret = fts_ex_mode_switch(MODE_GLOVE, DISABLE);
++            if (ret >= 0) {
++                ts_data->glove_mode = DISABLE;
++            }
++        }
++    }
++
++    FTS_DEBUG("glove mode:%d", ts_data->glove_mode);
++    return count;
++}
++
++
++static ssize_t fts_cover_mode_show(
++    struct device *dev, struct device_attribute *attr, char *buf)
++{
++    int count = 0;
++    u8 val = 0;
++    struct fts_ts_data *ts_data = fts_data;
++    struct input_dev *input_dev = ts_data->input_dev;
++
++    mutex_lock(&input_dev->mutex);
++    fts_read_reg(FTS_REG_COVER_MODE_EN, &val);
++    count = snprintf(buf + count, PAGE_SIZE, "Cover Mode:%s\n",
++                     ts_data->cover_mode ? "On" : "Off");
++    count += snprintf(buf + count, PAGE_SIZE, "Cover Reg(0xC1):%d\n", val);
++    mutex_unlock(&input_dev->mutex);
++
++    return count;
++}
++
++static ssize_t fts_cover_mode_store(
++    struct device *dev,
++    struct device_attribute *attr, const char *buf, size_t count)
++{
++    int ret = 0;
++    struct fts_ts_data *ts_data = fts_data;
++
++    if (FTS_SYSFS_ECHO_ON(buf)) {
++        if (!ts_data->cover_mode) {
++            FTS_DEBUG("enter cover mode");
++            ret = fts_ex_mode_switch(MODE_COVER, ENABLE);
++            if (ret >= 0) {
++                ts_data->cover_mode = ENABLE;
++            }
++        }
++    } else if (FTS_SYSFS_ECHO_OFF(buf)) {
++        if (ts_data->cover_mode) {
++            FTS_DEBUG("exit cover mode");
++            ret = fts_ex_mode_switch(MODE_COVER, DISABLE);
++            if (ret >= 0) {
++                ts_data->cover_mode = DISABLE;
++            }
++        }
++    }
++
++    FTS_DEBUG("cover mode:%d", ts_data->cover_mode);
++    return count;
++}
++
++static ssize_t fts_charger_mode_show(
++    struct device *dev, struct device_attribute *attr, char *buf)
++{
++    int count = 0;
++    u8 val = 0;
++    struct fts_ts_data *ts_data = fts_data;
++    struct input_dev *input_dev = ts_data->input_dev;
++
++    mutex_lock(&input_dev->mutex);
++    fts_read_reg(FTS_REG_CHARGER_MODE_EN, &val);
++    count = snprintf(buf + count, PAGE_SIZE, "Charger Mode:%s\n",
++                     ts_data->charger_mode ? "On" : "Off");
++    count += snprintf(buf + count, PAGE_SIZE, "Charger Reg(0x8B):%d\n", val);
++    mutex_unlock(&input_dev->mutex);
++
++    return count;
++}
++
++static ssize_t fts_charger_mode_store(
++    struct device *dev,
++    struct device_attribute *attr, const char *buf, size_t count)
++{
++    int ret = 0;
++    struct fts_ts_data *ts_data = fts_data;
++
++    if (FTS_SYSFS_ECHO_ON(buf)) {
++        if (!ts_data->charger_mode) {
++            FTS_DEBUG("enter charger mode");
++            ret = fts_ex_mode_switch(MODE_CHARGER, ENABLE);
++            if (ret >= 0) {
++                ts_data->charger_mode = ENABLE;
++            }
++        }
++    } else if (FTS_SYSFS_ECHO_OFF(buf)) {
++        if (ts_data->charger_mode) {
++            FTS_DEBUG("exit charger mode");
++            ret = fts_ex_mode_switch(MODE_CHARGER, DISABLE);
++            if (ret >= 0) {
++                ts_data->charger_mode = DISABLE;
++            }
++        }
++    }
++
++    FTS_DEBUG("charger mode:%d", ts_data->glove_mode);
++    return count;
++}
++
++
++/* read and write charger mode
++ * read example: cat fts_glove_mode        ---read  glove mode
++ * write example:echo 1 > fts_glove_mode   ---write glove mode to 01
++ */
++static DEVICE_ATTR(fts_glove_mode, S_IRUGO | S_IWUSR,
++                   fts_glove_mode_show, fts_glove_mode_store);
++
++static DEVICE_ATTR(fts_cover_mode, S_IRUGO | S_IWUSR,
++                   fts_cover_mode_show, fts_cover_mode_store);
++
++static DEVICE_ATTR(fts_charger_mode, S_IRUGO | S_IWUSR,
++                   fts_charger_mode_show, fts_charger_mode_store);
++
++static struct attribute *fts_touch_mode_attrs[] = {
++    &dev_attr_fts_glove_mode.attr,
++    &dev_attr_fts_cover_mode.attr,
++    &dev_attr_fts_charger_mode.attr,
++    NULL,
++};
++
++static struct attribute_group fts_touch_mode_group = {
++    .attrs = fts_touch_mode_attrs,
++};
++
++int fts_ex_mode_recovery(struct fts_ts_data *ts_data)
++{
++    if (ts_data->glove_mode) {
++        fts_ex_mode_switch(MODE_GLOVE, ENABLE);
++    }
++
++    if (ts_data->cover_mode) {
++        fts_ex_mode_switch(MODE_COVER, ENABLE);
++    }
++
++    if (ts_data->charger_mode) {
++        fts_ex_mode_switch(MODE_CHARGER, ENABLE);
++    }
++
++    return 0;
++}
++
++int fts_ex_mode_init(struct fts_ts_data *ts_data)
++{
++    int ret = 0;
++
++    ts_data->glove_mode = DISABLE;
++    ts_data->cover_mode = DISABLE;
++    ts_data->charger_mode = DISABLE;
++
++    ret = sysfs_create_group(&ts_data->dev->kobj, &fts_touch_mode_group);
++    if (ret < 0) {
++        FTS_ERROR("create sysfs(ex_mode) fail");
++        sysfs_remove_group(&ts_data->dev->kobj, &fts_touch_mode_group);
++        return ret;
++    } else {
++        FTS_DEBUG("create sysfs(ex_mode) succeedfully");
++    }
++
++    return 0;
++}
++
++int fts_ex_mode_exit(struct fts_ts_data *ts_data)
++{
++    sysfs_remove_group(&ts_data->dev->kobj, &fts_touch_mode_group);
++    return 0;
++}
+diff --git a/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_flash.c b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_flash.c
+new file mode 100644
+index 000000000..d42540b01
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_flash.c
+@@ -0,0 +1,2011 @@
++/*
++ *
++ * FocalTech fts TouchScreen driver.
++ *
++ * Copyright (c) 2012-2019, Focaltech Ltd. All rights reserved.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++/*****************************************************************************
++*
++* File Name: focaltech_flash.c
++*
++* Author: Focaltech Driver Team
++*
++* Created: 2016-08-08
++*
++* Abstract:
++*
++* Reference:
++*
++*****************************************************************************/
++
++/*****************************************************************************
++* 1.Included header files
++*****************************************************************************/
++#include "focaltech_core.h"
++#include "focaltech_flash.h"
++
++/*****************************************************************************
++* Private constant and macro definitions using #define
++*****************************************************************************/
++#define FTS_FW_REQUEST_SUPPORT                      1
++/* Example: focaltech_ts_fw_tianma.bin */
++#define FTS_FW_NAME_PREX_WITH_REQUEST               "focaltech_ts_fw_"
++
++/*****************************************************************************
++* Global variable or extern global variabls/functions
++*****************************************************************************/
++u8 fw_file[] = {
++#include FTS_UPGRADE_FW_FILE
++};
++
++u8 fw_file2[] = {
++#include FTS_UPGRADE_FW2_FILE
++};
++
++u8 fw_file3[] = {
++#include FTS_UPGRADE_FW3_FILE
++};
++
++struct upgrade_module module_list[] = {
++    {FTS_MODULE_ID, FTS_MODULE_NAME, fw_file, sizeof(fw_file)},
++    {FTS_MODULE2_ID, FTS_MODULE2_NAME, fw_file2, sizeof(fw_file2)},
++    {FTS_MODULE3_ID, FTS_MODULE3_NAME, fw_file3, sizeof(fw_file3)},
++};
++
++struct upgrade_func *upgrade_func_list[] = {
++    &upgrade_func_ft7511,
++};
++
++struct fts_upgrade *fwupgrade;
++
++/*****************************************************************************
++* Static function prototypes
++*****************************************************************************/
++static bool fts_fwupg_check_state(
++    struct fts_upgrade *upg, enum FW_STATUS rstate);
++
++/************************************************************************
++* Name: fts_fwupg_get_boot_state
++* Brief: read boot id(rom/pram/bootloader), confirm boot environment
++* Input:
++* Output:
++* Return: return 0 if success, otherwise return error code
++***********************************************************************/
++static int fts_fwupg_get_boot_state(
++    struct fts_upgrade *upg,
++    enum FW_STATUS *fw_sts)
++{
++    int ret = 0;
++    u8 cmd[4] = { 0 };
++    u32 cmd_len = 0;
++    u8 val[2] = { 0 };
++    struct ft_chip_t *ids = NULL;
++
++    FTS_INFO("**********read boot id**********");
++    if ((!upg) || (!upg->func) || (!upg->ts_data) || (!fw_sts)) {
++        FTS_ERROR("upg/func/ts_data/fw_sts is null");
++        return -EINVAL;
++    }
++
++    if (upg->func->hid_supported)
++        fts_hid2std();
++
++    cmd[0] = FTS_CMD_START1;
++    cmd[1] = FTS_CMD_START2;
++    ret = fts_write(cmd, 2);
++    if (ret < 0) {
++        FTS_ERROR("write 55 aa cmd fail");
++        return ret;
++    }
++
++    msleep(FTS_CMD_START_DELAY);
++    cmd[0] = FTS_CMD_READ_ID;
++    cmd[1] = cmd[2] = cmd[3] = 0x00;
++    if (fts_data->ic_info.is_incell)
++        cmd_len = FTS_CMD_READ_ID_LEN_INCELL;
++    else
++        cmd_len = FTS_CMD_READ_ID_LEN;
++    ret = fts_read(cmd, cmd_len, val, 2);
++    if (ret < 0) {
++        FTS_ERROR("write 90 cmd fail");
++        return ret;
++    }
++    FTS_INFO("read boot id:0x%02x%02x", val[0], val[1]);
++
++    ids = &upg->ts_data->ic_info.ids;
++    if ((val[0] == ids->rom_idh) && (val[1] == ids->rom_idl)) {
++        FTS_INFO("tp run in romboot");
++        *fw_sts = FTS_RUN_IN_ROM;
++    } else if ((val[0] == ids->pb_idh) && (val[1] == ids->pb_idl)) {
++        FTS_INFO("tp run in pramboot");
++        *fw_sts = FTS_RUN_IN_PRAM;
++    } else if ((val[0] == ids->bl_idh) && (val[1] == ids->bl_idl)) {
++        FTS_INFO("tp run in bootloader");
++        *fw_sts = FTS_RUN_IN_BOOTLOADER;
++    }
++
++    return 0;
++}
++
++static int fts_fwupg_reset_to_boot(struct fts_upgrade *upg)
++{
++    int ret = 0;
++    u8 reg = FTS_REG_UPGRADE;
++
++    FTS_INFO("send 0xAA and 0x55 to FW, reset to boot environment");
++    if (upg && upg->func && upg->func->is_reset_register_BC) {
++        reg = FTS_REG_UPGRADE2;
++    }
++
++    ret = fts_write_reg(reg, FTS_UPGRADE_AA);
++    if (ret < 0) {
++        FTS_ERROR("write FC=0xAA fail");
++        return ret;
++    }
++    msleep(FTS_DELAY_UPGRADE_AA);
++
++    ret = fts_write_reg(reg, FTS_UPGRADE_55);
++    if (ret < 0) {
++        FTS_ERROR("write FC=0x55 fail");
++        return ret;
++    }
++
++    msleep(FTS_DELAY_UPGRADE_RESET);
++    return 0;
++}
++
++/************************************************************************
++* Name: fts_fwupg_reset_to_romboot
++* Brief: reset to romboot, to load pramboot
++* Input:
++* Output:
++* Return: return 0 if success, otherwise return error code
++***********************************************************************/
++static int fts_fwupg_reset_to_romboot(struct fts_upgrade *upg)
++{
++    int ret = 0;
++    int i = 0;
++    u8 cmd = FTS_CMD_RESET;
++    enum FW_STATUS state = FTS_RUN_IN_ERROR;
++
++    ret = fts_write(&cmd, 1);
++    if (ret < 0) {
++        FTS_ERROR("pram/rom/bootloader reset cmd write fail");
++        return ret;
++    }
++    mdelay(10);
++
++    for (i = 0; i < FTS_UPGRADE_LOOP; i++) {
++        ret = fts_fwupg_get_boot_state(upg, &state);
++        if (FTS_RUN_IN_ROM == state)
++            break;
++        mdelay(5);
++    }
++    if (i >= FTS_UPGRADE_LOOP) {
++        FTS_ERROR("reset to romboot fail");
++        return -EIO;
++    }
++
++    return 0;
++}
++
++static u16 fts_crc16_calc_host(u8 *pbuf, u16 length)
++{
++    u16 ecc = 0;
++    u16 i = 0;
++    u16 j = 0;
++
++    for ( i = 0; i < length; i += 2 ) {
++        ecc ^= ((pbuf[i] << 8) | (pbuf[i + 1]));
++        for (j = 0; j < 16; j ++) {
++            if (ecc & 0x01)
++                ecc = (u16)((ecc >> 1) ^ AL2_FCS_COEF);
++            else
++                ecc >>= 1;
++        }
++    }
++
++    return ecc;
++}
++
++static u16 fts_pram_ecc_calc_host(u8 *pbuf, u16 length)
++{
++    return fts_crc16_calc_host(pbuf, length);
++}
++
++static int fts_pram_ecc_cal_algo(
++    struct fts_upgrade *upg,
++    u32 start_addr,
++    u32 ecc_length)
++{
++    int ret = 0;
++    int i = 0;
++    int ecc = 0;
++    u8 val[2] = { 0 };
++    u8 tmp = 0;
++    u8 cmd[FTS_ROMBOOT_CMD_ECC_NEW_LEN] = { 0 };
++
++    FTS_INFO("read out pramboot checksum");
++    if ((!upg) || (!upg->func)) {
++        FTS_ERROR("upg/func is null");
++        return -EINVAL;
++    }
++
++    cmd[0] = FTS_ROMBOOT_CMD_ECC;
++    cmd[1] = BYTE_OFF_16(start_addr);
++    cmd[2] = BYTE_OFF_8(start_addr);
++    cmd[3] = BYTE_OFF_0(start_addr);
++    cmd[4] = BYTE_OFF_16(ecc_length);
++    cmd[5] = BYTE_OFF_8(ecc_length);
++    cmd[6] = BYTE_OFF_0(ecc_length);
++    ret = fts_write(cmd, FTS_ROMBOOT_CMD_ECC_NEW_LEN);
++    if (ret < 0) {
++        FTS_ERROR("write pramboot ecc cal cmd fail");
++        return ret;
++    }
++
++    cmd[0] = FTS_ROMBOOT_CMD_ECC_FINISH;
++    for (i = 0; i < FTS_ECC_FINISH_TIMEOUT; i++) {
++        msleep(1);
++        ret = fts_read(cmd, 1, val, 1);
++        if (ret < 0) {
++            FTS_ERROR("ecc_finish read cmd fail");
++            return ret;
++        }
++        if (upg->func->new_return_value_from_ic) {
++            tmp = FTS_ROMBOOT_CMD_ECC_FINISH_OK_A5;
++        } else {
++            tmp = FTS_ROMBOOT_CMD_ECC_FINISH_OK_00;
++        }
++        if (tmp == val[0])
++            break;
++    }
++    if (i >= 100) {
++        FTS_ERROR("wait ecc finish fail");
++        return -EIO;
++    }
++
++    cmd[0] = FTS_ROMBOOT_CMD_ECC_READ;
++    ret = fts_read(cmd, 1, val, 2);
++    if (ret < 0) {
++        FTS_ERROR("read pramboot ecc fail");
++        return ret;
++    }
++
++    ecc = ((u16)(val[0] << 8) + val[1]) & 0x0000FFFF;
++    return ecc;
++}
++
++static int fts_pram_ecc_cal_xor(void)
++{
++    int ret = 0;
++    u8 reg_val = 0;
++
++    FTS_INFO("read out pramboot checksum");
++
++    ret = fts_read_reg(FTS_ROMBOOT_CMD_ECC, &reg_val);
++    if (ret < 0) {
++        FTS_ERROR("read pramboot ecc fail");
++        return ret;
++    }
++
++    return (int)reg_val;
++}
++
++static int fts_pram_ecc_cal(struct fts_upgrade *upg, u32 saddr, u32 len)
++{
++    if ((!upg) || (!upg->func)) {
++        FTS_ERROR("upg/func is null");
++        return -EINVAL;
++    }
++
++    if (ECC_CHECK_MODE_CRC16 == upg->func->pram_ecc_check_mode) {
++        return fts_pram_ecc_cal_algo(upg, saddr, len);
++    } else {
++        return fts_pram_ecc_cal_xor();
++    }
++}
++
++static int fts_pram_write_buf(struct fts_upgrade *upg, u8 *buf, u32 len)
++{
++    int ret = 0;
++    u32 i = 0;
++    u32 j = 0;
++    u32 offset = 0;
++    u32 remainder = 0;
++    u32 packet_number;
++    u32 packet_len = 0;
++    u8 packet_buf[FTS_FLASH_PACKET_LENGTH + FTS_CMD_WRITE_LEN] = { 0 };
++    u8 ecc_tmp = 0;
++    int ecc_in_host = 0;
++
++    FTS_INFO("write pramboot to pram");
++    if ((!upg) || (!upg->func) || !buf) {
++        FTS_ERROR("upg/func/buf is null");
++        return -EINVAL;
++    }
++
++    FTS_INFO("pramboot len=%d", len);
++    if ((len < PRAMBOOT_MIN_SIZE) || (len > PRAMBOOT_MAX_SIZE)) {
++        FTS_ERROR("pramboot length(%d) fail", len);
++        return -EINVAL;
++    }
++
++    packet_number = len / FTS_FLASH_PACKET_LENGTH;
++    remainder = len % FTS_FLASH_PACKET_LENGTH;
++    if (remainder > 0)
++        packet_number++;
++    packet_len = FTS_FLASH_PACKET_LENGTH;
++
++    packet_buf[0] = FTS_ROMBOOT_CMD_WRITE;
++    for (i = 0; i < packet_number; i++) {
++        offset = i * FTS_FLASH_PACKET_LENGTH;
++        packet_buf[1] = BYTE_OFF_16(offset);
++        packet_buf[2] = BYTE_OFF_8(offset);
++        packet_buf[3] = BYTE_OFF_0(offset);
++
++        /* last packet */
++        if ((i == (packet_number - 1)) && remainder)
++            packet_len = remainder;
++
++        packet_buf[4] = BYTE_OFF_8(packet_len);
++        packet_buf[5] = BYTE_OFF_0(packet_len);
++
++        for (j = 0; j < packet_len; j++) {
++            packet_buf[FTS_CMD_WRITE_LEN + j] = buf[offset + j];
++            if (ECC_CHECK_MODE_XOR == upg->func->pram_ecc_check_mode) {
++                ecc_tmp ^= packet_buf[FTS_CMD_WRITE_LEN + j];
++            }
++        }
++
++        ret = fts_write(packet_buf, packet_len + FTS_CMD_WRITE_LEN);
++        if (ret < 0) {
++            FTS_ERROR("pramboot write data(%d) fail", i);
++            return ret;
++        }
++    }
++
++    if (ECC_CHECK_MODE_CRC16 == upg->func->pram_ecc_check_mode) {
++        ecc_in_host = (int)fts_pram_ecc_calc_host(buf, len);
++    } else {
++        ecc_in_host = (int)ecc_tmp;
++    }
++
++    return ecc_in_host;
++}
++
++static int fts_pram_start(void)
++{
++    u8 cmd = FTS_ROMBOOT_CMD_START_APP;
++    int ret = 0;
++
++    FTS_INFO("remap to start pramboot");
++
++    ret = fts_write(&cmd, 1);
++    if (ret < 0) {
++        FTS_ERROR("write start pram cmd fail");
++        return ret;
++    }
++    msleep(FTS_DELAY_PRAMBOOT_START);
++
++    return 0;
++}
++
++static int fts_pram_write_remap(struct fts_upgrade *upg)
++{
++    int ret = 0;
++    int ecc_in_host = 0;
++    int ecc_in_tp = 0;
++    u8 *pb_buf = NULL;
++    u32 pb_len = 0;
++
++    FTS_INFO("write pram and remap");
++    if (!upg || !upg->func || !upg->func->pramboot) {
++        FTS_ERROR("upg/func/pramboot is null");
++        return -EINVAL;
++    }
++
++    if (upg->func->pb_length < FTS_MIN_LEN) {
++        FTS_ERROR("pramboot length(%d) fail", upg->func->pb_length);
++        return -EINVAL;
++    }
++
++    pb_buf = upg->func->pramboot;
++    pb_len = upg->func->pb_length;
++
++    /* write pramboot to pram */
++    ecc_in_host = fts_pram_write_buf(upg, pb_buf, pb_len);
++    if (ecc_in_host < 0) {
++        FTS_ERROR( "write pramboot fail");
++        return ecc_in_host;
++    }
++
++    /* read out checksum */
++    ecc_in_tp = fts_pram_ecc_cal(upg, 0, pb_len);
++    if (ecc_in_tp < 0) {
++        FTS_ERROR( "read pramboot ecc fail");
++        return ecc_in_tp;
++    }
++
++    FTS_INFO("pram ecc in tp:%x, host:%x", ecc_in_tp, ecc_in_host);
++    /*  pramboot checksum != fw checksum, upgrade fail */
++    if (ecc_in_host != ecc_in_tp) {
++        FTS_ERROR("pramboot ecc check fail");
++        return -EIO;
++    }
++
++    /*start pram*/
++    ret = fts_pram_start();
++    if (ret < 0) {
++        FTS_ERROR("pram start fail");
++        return ret;
++    }
++
++    return 0;
++}
++
++static int fts_pram_init(void)
++{
++    int ret = 0;
++    u8 reg_val = 0;
++    u8 wbuf[3] = { 0 };
++
++    FTS_INFO("pramboot initialization");
++
++    /* read flash ID */
++    wbuf[0] = FTS_CMD_FLASH_TYPE;
++    ret = fts_read(wbuf, 1, &reg_val, 1);
++    if (ret < 0) {
++        FTS_ERROR("read flash type fail");
++        return ret;
++    }
++
++    /* set flash clk */
++    wbuf[0] = FTS_CMD_FLASH_TYPE;
++    wbuf[1] = reg_val;
++    wbuf[2] = 0x00;
++    ret = fts_write(wbuf, 3);
++    if (ret < 0) {
++        FTS_ERROR("write flash type fail");
++        return ret;
++    }
++
++    return 0;
++}
++
++static int fts_pram_write_init(struct fts_upgrade *upg)
++{
++    int ret = 0;
++    bool state = 0;
++    enum FW_STATUS status = FTS_RUN_IN_ERROR;
++
++    FTS_INFO("**********pram write and init**********");
++    if ((NULL == upg) || (NULL == upg->func)) {
++        FTS_ERROR("upgrade/func is null");
++        return -EINVAL;
++    }
++
++    if (!upg->func->pramboot_supported) {
++        FTS_ERROR("ic not support pram");
++        return -EINVAL;
++    }
++
++    FTS_DEBUG("check whether tp is in romboot or not ");
++    /* need reset to romboot when non-romboot state */
++    ret = fts_fwupg_get_boot_state(upg, &status);
++    if (status != FTS_RUN_IN_ROM) {
++        if (FTS_RUN_IN_PRAM == status) {
++            FTS_INFO("tp is in pramboot, need send reset cmd before upgrade");
++            ret = fts_pram_init();
++            if (ret < 0) {
++                FTS_ERROR("pramboot(before) init fail");
++                return ret;
++            }
++        }
++
++        FTS_INFO("tp isn't in romboot, need send reset to romboot");
++        ret = fts_fwupg_reset_to_romboot(upg);
++        if (ret < 0) {
++            FTS_ERROR("reset to romboot fail");
++            return ret;
++        }
++    }
++
++    /* check the length of the pramboot */
++    ret = fts_pram_write_remap(upg);
++    if (ret < 0) {
++        FTS_ERROR("pram write fail, ret=%d", ret);
++        return ret;
++    }
++
++    FTS_DEBUG("after write pramboot, confirm run in pramboot");
++    state = fts_fwupg_check_state(upg, FTS_RUN_IN_PRAM);
++    if (!state) {
++        FTS_ERROR("not in pramboot");
++        return -EIO;
++    }
++
++    ret = fts_pram_init();
++    if (ret < 0) {
++        FTS_ERROR("pramboot init fail");
++        return ret;
++    }
++
++    return 0;
++}
++
++static bool fts_fwupg_check_fw_valid(void)
++{
++    int ret = 0;
++
++    ret = fts_wait_tp_to_valid();
++    if (ret < 0) {
++        FTS_INFO("tp fw invaild");
++        return false;
++    }
++
++    FTS_INFO("tp fw vaild");
++    return true;
++}
++
++/************************************************************************
++* Name: fts_fwupg_check_state
++* Brief: confirm tp run in which mode: romboot/pramboot/bootloader
++* Input:
++* Output:
++* Return: return true if state is match, otherwise return false
++***********************************************************************/
++static bool fts_fwupg_check_state(
++    struct fts_upgrade *upg, enum FW_STATUS rstate)
++{
++    int ret = 0;
++    int i = 0;
++    enum FW_STATUS cstate = FTS_RUN_IN_ERROR;
++
++    for (i = 0; i < FTS_UPGRADE_LOOP; i++) {
++        ret = fts_fwupg_get_boot_state(upg, &cstate);
++        /* FTS_DEBUG("fw state=%d, retries=%d", cstate, i); */
++        if (cstate == rstate)
++            return true;
++        msleep(FTS_DELAY_READ_ID);
++    }
++
++    return false;
++}
++
++/************************************************************************
++* Name: fts_fwupg_reset_in_boot
++* Brief: RST CMD(07), reset to romboot(bootloader) in boot environment
++* Input:
++* Output:
++* Return: return 0 if success, otherwise return error code
++***********************************************************************/
++int fts_fwupg_reset_in_boot(void)
++{
++    int ret = 0;
++    u8 cmd = FTS_CMD_RESET;
++
++    FTS_INFO("reset in boot environment");
++    ret = fts_write(&cmd, 1);
++    if (ret < 0) {
++        FTS_ERROR("pram/rom/bootloader reset cmd write fail");
++        return ret;
++    }
++
++    msleep(FTS_DELAY_UPGRADE_RESET);
++    return 0;
++}
++
++/************************************************************************
++* Name: fts_fwupg_enter_into_boot
++* Brief: enter into boot environment, ready for upgrade
++* Input:
++* Output:
++* Return: return 0 if success, otherwise return error code
++***********************************************************************/
++int fts_fwupg_enter_into_boot(void)
++{
++    int ret = 0;
++    bool fwvalid = false;
++    bool state = false;
++    struct fts_upgrade *upg = fwupgrade;
++
++    FTS_INFO("***********enter into pramboot/bootloader***********");
++    if ((!upg) || (NULL == upg->func)) {
++        FTS_ERROR("upgrade/func is null");
++        return -EINVAL;
++    }
++
++    fwvalid = fts_fwupg_check_fw_valid();
++    if (fwvalid) {
++        ret = fts_fwupg_reset_to_boot(upg);
++        if (ret < 0) {
++            FTS_ERROR("enter into romboot/bootloader fail");
++            return ret;
++        }
++    } else if (upg->func->read_boot_id_need_reset) {
++        ret = fts_fwupg_reset_in_boot();
++        if (ret < 0) {
++            FTS_ERROR("reset before read boot id when fw invalid fail");
++            return ret;
++        }
++    }
++
++    if (upg->func->pramboot_supported) {
++        FTS_INFO("pram supported, write pramboot and init");
++        /* pramboot */
++        ret = fts_pram_write_init(upg);
++        if (ret < 0) {
++            FTS_ERROR("pram write_init fail");
++            return ret;
++        }
++    } else {
++        FTS_DEBUG("pram not supported, confirm in bootloader");
++        /* bootloader */
++        state = fts_fwupg_check_state(upg, FTS_RUN_IN_BOOTLOADER);
++        if (!state) {
++            FTS_ERROR("fw not in bootloader, fail");
++            return -EIO;
++        }
++    }
++
++    return 0;
++}
++
++/************************************************************************
++ * Name: fts_fwupg_check_flash_status
++ * Brief: read status from tp
++ * Input: flash_status: correct value from tp
++ *        retries: read retry times
++ *        retries_delay: retry delay
++ * Output:
++ * Return: return true if flash status check pass, otherwise return false
++***********************************************************************/
++static bool fts_fwupg_check_flash_status(
++    u16 flash_status,
++    int retries,
++    int retries_delay)
++{
++    int ret = 0;
++    int i = 0;
++    u8 cmd = 0;
++    u8 val[FTS_CMD_FLASH_STATUS_LEN] = { 0 };
++    u16 read_status = 0;
++
++    for (i = 0; i < retries; i++) {
++        cmd = FTS_CMD_FLASH_STATUS;
++        ret = fts_read(&cmd , 1, val, FTS_CMD_FLASH_STATUS_LEN);
++        read_status = (((u16)val[0]) << 8) + val[1];
++        if (flash_status == read_status) {
++            /* FTS_DEBUG("[UPGRADE]flash status ok"); */
++            return true;
++        }
++        /* FTS_DEBUG("flash status fail,ok:%04x read:%04x, retries:%d", flash_status, read_status, i); */
++        msleep(retries_delay);
++    }
++
++    return false;
++}
++
++/************************************************************************
++ * Name: fts_fwupg_erase
++ * Brief: erase flash area
++ * Input: delay - delay after erase
++ * Output:
++ * Return: return 0 if success, otherwise return error code
++ ***********************************************************************/
++int fts_fwupg_erase(u32 delay)
++{
++    int ret = 0;
++    u8 cmd = 0;
++    bool flag = false;
++
++    FTS_INFO("**********erase now**********");
++
++    /*send to erase flash*/
++    cmd = FTS_CMD_ERASE_APP;
++    ret = fts_write(&cmd, 1);
++    if (ret < 0) {
++        FTS_ERROR("erase cmd fail");
++        return ret;
++    }
++    msleep(delay);
++
++    /* read status 0xF0AA: success */
++    flag = fts_fwupg_check_flash_status(FTS_CMD_FLASH_STATUS_ERASE_OK,
++                                        FTS_RETRIES_REASE,
++                                        FTS_RETRIES_DELAY_REASE);
++    if (!flag) {
++        FTS_ERROR("ecc flash status check fail");
++        return -EIO;
++    }
++
++    return 0;
++}
++
++/************************************************************************
++ * Name: fts_fwupg_ecc_cal
++ * Brief: calculate and get ecc from tp
++ * Input: saddr - start address need calculate ecc
++ *        len - length need calculate ecc
++ * Output:
++ * Return: return data ecc of tp if success, otherwise return error code
++ ***********************************************************************/
++int fts_fwupg_ecc_cal(u32 saddr, u32 len)
++{
++    int ret = 0;
++    u32 i = 0;
++    u8 wbuf[FTS_CMD_ECC_CAL_LEN] = { 0 };
++    u8 val[FTS_CMD_FLASH_STATUS_LEN] = { 0 };
++    int ecc = 0;
++    int ecc_len = 0;
++    u32 packet_num = 0;
++    u32 packet_len = 0;
++    u32 remainder = 0;
++    u32 addr = 0;
++    u32 offset = 0;
++    struct fts_upgrade *upg = fwupgrade;
++
++    FTS_INFO( "**********read out checksum**********");
++    if ((NULL == upg) || (NULL == upg->func)) {
++        FTS_ERROR("upgrade/func is null");
++        return -EINVAL;
++    }
++
++    /* check sum init */
++    wbuf[0] = FTS_CMD_ECC_INIT;
++    ret = fts_write(wbuf, 1);
++    if (ret < 0) {
++        FTS_ERROR("ecc init cmd write fail");
++        return ret;
++    }
++
++    packet_num = len / FTS_MAX_LEN_ECC_CALC;
++    remainder = len % FTS_MAX_LEN_ECC_CALC;
++    if (remainder)
++        packet_num++;
++    packet_len = FTS_MAX_LEN_ECC_CALC;
++    FTS_INFO("ecc calc num:%d, remainder:%d", packet_num, remainder);
++
++    /* send commond to start checksum */
++    wbuf[0] = FTS_CMD_ECC_CAL;
++    for (i = 0; i < packet_num; i++) {
++        offset = FTS_MAX_LEN_ECC_CALC * i;
++        addr = saddr + offset;
++        wbuf[1] = BYTE_OFF_16(addr);
++        wbuf[2] = BYTE_OFF_8(addr);
++        wbuf[3] = BYTE_OFF_0(addr);
++
++        if ((i == (packet_num - 1)) && remainder)
++            packet_len = remainder;
++        wbuf[4] = BYTE_OFF_8(packet_len);
++        wbuf[5] = BYTE_OFF_0(packet_len);
++
++        FTS_DEBUG("ecc calc startaddr:0x%04x, len:%d", addr, packet_len);
++        ret = fts_write(wbuf, FTS_CMD_ECC_CAL_LEN);
++        if (ret < 0) {
++            FTS_ERROR("ecc calc cmd write fail");
++            return ret;
++        }
++
++        msleep(packet_len / 256);
++
++        /* read status if check sum is finished */
++        ret = fts_fwupg_check_flash_status(FTS_CMD_FLASH_STATUS_ECC_OK,
++                                           FTS_RETRIES_ECC_CAL,
++                                           FTS_RETRIES_DELAY_ECC_CAL);
++        if (ret < 0) {
++            FTS_ERROR("ecc flash status read fail");
++            return ret;
++        }
++    }
++
++    ecc_len = 1;
++    if (ECC_CHECK_MODE_CRC16 == upg->func->fw_ecc_check_mode) {
++        ecc_len = 2;
++    }
++
++    /* read out check sum */
++    wbuf[0] = FTS_CMD_ECC_READ;
++    ret = fts_read(wbuf, 1, val, ecc_len);
++    if (ret < 0) {
++        FTS_ERROR( "ecc read cmd write fail");
++        return ret;
++    }
++
++    if (ECC_CHECK_MODE_CRC16 == upg->func->fw_ecc_check_mode) {
++        ecc = (int)((u16)(val[0] << 8) + val[1]);
++    } else {
++        ecc = (int)val[0];
++    }
++
++    return ecc;
++}
++
++/************************************************************************
++ * Name: fts_flash_write_buf
++ * Brief: write buf data to flash address
++ * Input: saddr - start address data write to flash
++ *        buf - data buffer
++ *        len - data length
++ *        delay - delay after write
++ * Output:
++ * Return: return data ecc of host if success, otherwise return error code
++ ***********************************************************************/
++int fts_flash_write_buf(
++    u32 saddr,
++    u8 *buf,
++    u32 len,
++    u32 delay)
++{
++    int ret = 0;
++    u32 i = 0;
++    u32 j = 0;
++    u32 packet_number = 0;
++    u32 packet_len = 0;
++    u32 addr = 0;
++    u32 offset = 0;
++    u32 remainder = 0;
++    u8 packet_buf[FTS_FLASH_PACKET_LENGTH + FTS_CMD_WRITE_LEN] = { 0 };
++    u8 ecc_tmp = 0;
++    int ecc_in_host = 0;
++    u8 cmd = 0;
++    u8 val[FTS_CMD_FLASH_STATUS_LEN] = { 0 };
++    u16 read_status = 0;
++    u16 wr_ok = 0;
++    struct fts_upgrade *upg = fwupgrade;
++
++    FTS_INFO( "**********write data to flash**********");
++    if ((!upg) || (!upg->func || !buf || !len)) {
++        FTS_ERROR("upgrade/func/buf/len is invalid");
++        return -EINVAL;
++    }
++
++    FTS_INFO("data buf start addr=0x%x, len=0x%x", saddr, len);
++    packet_number = len / FTS_FLASH_PACKET_LENGTH;
++    remainder = len % FTS_FLASH_PACKET_LENGTH;
++    if (remainder > 0)
++        packet_number++;
++    packet_len = FTS_FLASH_PACKET_LENGTH;
++    FTS_INFO("write data, num:%d remainder:%d", packet_number, remainder);
++
++    packet_buf[0] = FTS_CMD_WRITE;
++    for (i = 0; i < packet_number; i++) {
++        offset = i * FTS_FLASH_PACKET_LENGTH;
++        addr = saddr + offset;
++        packet_buf[1] = BYTE_OFF_16(addr);
++        packet_buf[2] = BYTE_OFF_8(addr);
++        packet_buf[3] = BYTE_OFF_0(addr);
++
++        /* last packet */
++        if ((i == (packet_number - 1)) && remainder)
++            packet_len = remainder;
++
++        packet_buf[4] = BYTE_OFF_8(packet_len);
++        packet_buf[5] = BYTE_OFF_0(packet_len);
++
++        for (j = 0; j < packet_len; j++) {
++            packet_buf[FTS_CMD_WRITE_LEN + j] = buf[offset + j];
++            ecc_tmp ^= packet_buf[FTS_CMD_WRITE_LEN + j];
++        }
++
++        ret = fts_write(packet_buf, packet_len + FTS_CMD_WRITE_LEN);
++        if (ret < 0) {
++            FTS_ERROR("app write fail");
++            return ret;
++        }
++        mdelay(delay);
++
++        /* read status */
++        wr_ok = FTS_CMD_FLASH_STATUS_WRITE_OK + addr / packet_len;
++        for (j = 0; j < FTS_RETRIES_WRITE; j++) {
++            cmd = FTS_CMD_FLASH_STATUS;
++            ret = fts_read(&cmd , 1, val, FTS_CMD_FLASH_STATUS_LEN);
++            read_status = (((u16)val[0]) << 8) + val[1];
++            /*  FTS_INFO("%x %x", wr_ok, read_status); */
++            if (wr_ok == read_status) {
++                break;
++            }
++            mdelay(FTS_RETRIES_DELAY_WRITE);
++        }
++    }
++
++    ecc_in_host = (int)ecc_tmp;
++    if (ECC_CHECK_MODE_CRC16 == upg->func->fw_ecc_check_mode) {
++        ecc_in_host = (int)fts_crc16_calc_host(buf, len);
++    }
++
++    return ecc_in_host;
++}
++
++/************************************************************************
++ * Name: fts_flash_read_buf
++ * Brief: read data from flash
++ * Input: saddr - start address data write to flash
++ *        buf - buffer to store data read from flash
++ *        len - read length
++ * Output:
++ * Return: return 0 if success, otherwise return error code
++ *
++ * Warning: can't call this function directly, need call in boot environment
++ ***********************************************************************/
++static int fts_flash_read_buf(u32 saddr, u8 *buf, u32 len)
++{
++    int ret = 0;
++    u32 i = 0;
++    u32 packet_number = 0;
++    u32 packet_len = 0;
++    u32 addr = 0;
++    u32 offset = 0;
++    u32 remainder = 0;
++    u8 wbuf[FTS_CMD_READ_LEN] = { 0 };
++
++    if ((NULL == buf) || (0 == len)) {
++        FTS_ERROR("buf is NULL or len is 0");
++        return -EINVAL;
++    }
++
++    packet_number = len / FTS_FLASH_PACKET_LENGTH;
++    remainder = len % FTS_FLASH_PACKET_LENGTH;
++    if (remainder > 0) {
++        packet_number++;
++    }
++    packet_len = FTS_FLASH_PACKET_LENGTH;
++    FTS_INFO("read packet_number:%d, remainder:%d", packet_number, remainder);
++
++    wbuf[0] = FTS_CMD_READ;
++    for (i = 0; i < packet_number; i++) {
++        offset = i * FTS_FLASH_PACKET_LENGTH;
++        addr = saddr + offset;
++        wbuf[1] = BYTE_OFF_16(addr);
++        wbuf[2] = BYTE_OFF_8(addr);
++        wbuf[3] = BYTE_OFF_0(addr);
++
++        /* last packet */
++        if ((i == (packet_number - 1)) && remainder)
++            packet_len = remainder;
++
++        ret = fts_write(wbuf, FTS_CMD_READ_LEN);
++        if (ret < 0) {
++            FTS_ERROR("pram/bootloader write 03 command fail");
++            return ret;
++        }
++
++        msleep(FTS_CMD_READ_DELAY); /* must wait, otherwise read wrong data */
++        ret = fts_read(NULL, 0, buf + offset, packet_len);
++        if (ret < 0) {
++            FTS_ERROR("pram/bootloader read 03 command fail");
++            return ret;
++        }
++    }
++
++    return 0;
++}
++
++/************************************************************************
++ * Name: fts_flash_read
++ * Brief:
++ * Input:  addr  - address of flash
++ *         len   - length of read
++ * Output: buf   - data read from flash
++ * Return: return 0 if success, otherwise return error code
++ ***********************************************************************/
++static int fts_flash_read(u32 addr, u8 *buf, u32 len)
++{
++    int ret = 0;
++
++    FTS_INFO("***********read flash***********");
++    if ((NULL == buf) || (0 == len)) {
++        FTS_ERROR("buf is NULL or len is 0");
++        return -EINVAL;
++    }
++
++    ret = fts_fwupg_enter_into_boot();
++    if (ret < 0) {
++        FTS_ERROR("enter into pramboot/bootloader fail");
++        goto read_flash_err;
++    }
++
++    ret = fts_flash_read_buf(addr, buf, len);
++    if (ret < 0) {
++        FTS_ERROR("read flash fail");
++        goto read_flash_err;
++    }
++
++read_flash_err:
++    /* reset to normal boot */
++    ret = fts_fwupg_reset_in_boot();
++    if (ret < 0) {
++        FTS_ERROR("reset to normal boot fail");
++    }
++    return ret;
++}
++
++static int fts_read_file(char *file_name, u8 **file_buf)
++{
++    int ret = 0;
++    char file_path[FILE_NAME_LENGTH] = { 0 };
++    struct file *filp = NULL;
++    struct inode *inode;
++    mm_segment_t old_fs;
++    loff_t pos;
++    loff_t file_len = 0;
++
++    if ((NULL == file_name) || (NULL == file_buf)) {
++        FTS_ERROR("filename/filebuf is NULL");
++        return -EINVAL;
++    }
++
++    snprintf(file_path, FILE_NAME_LENGTH, "%s%s", FTS_FW_BIN_FILEPATH, file_name);
++    filp = filp_open(file_path, O_RDONLY, 0);
++    if (IS_ERR(filp)) {
++        FTS_ERROR("open %s file fail", file_path);
++        return -ENOENT;
++    }
++
++#if 1
++    inode = filp->f_inode;
++#else
++    /* reserved for linux earlier verion */
++    inode = filp->f_dentry->d_inode;
++#endif
++
++    file_len = inode->i_size;
++    *file_buf = (u8 *)vmalloc(file_len);
++    if (NULL == *file_buf) {
++        FTS_ERROR("file buf malloc fail");
++        filp_close(filp, NULL);
++        return -ENOMEM;
++    }
++    old_fs = get_fs();
++    set_fs(KERNEL_DS);
++    pos = 0;
++    ret = vfs_read(filp, *file_buf, file_len , &pos);
++    if (ret < 0)
++        FTS_ERROR("read file fail");
++    FTS_INFO("file len:%d read len:%d pos:%d", (u32)file_len, ret, (u32)pos);
++    filp_close(filp, NULL);
++    set_fs(old_fs);
++
++    return ret;
++}
++
++int fts_upgrade_bin(char *fw_name, bool force)
++{
++    int ret = 0;
++    u32 fw_file_len = 0;
++    u8 *fw_file_buf = NULL;
++    struct fts_upgrade *upg = fwupgrade;
++
++    FTS_INFO("start upgrade with fw bin");
++    if ((!upg) || (!upg->func) || !upg->ts_data) {
++        FTS_ERROR("upgrade/func/ts_data is null");
++        return -EINVAL;
++    }
++
++    upg->ts_data->fw_loading = 1;
++    fts_irq_disable();
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_switch(DISABLE);
++#endif
++
++    ret = fts_read_file(fw_name, &fw_file_buf);
++    if ((ret < 0) || (ret < FTS_MIN_LEN) || (ret > FTS_MAX_LEN_FILE)) {
++        FTS_ERROR("read fw bin file(sdcard) fail, len:%d", fw_file_len);
++        goto err_bin;
++    }
++
++    fw_file_len = ret;
++    FTS_INFO("fw bin file len:%d", fw_file_len);
++    if (force) {
++        if (upg->func->force_upgrade) {
++            ret = upg->func->force_upgrade(fw_file_buf, fw_file_len);
++        } else {
++            FTS_INFO("force_upgrade function is null, no upgrade");
++            goto err_bin;
++        }
++    } else {
++#if FTS_AUTO_LIC_UPGRADE_EN
++        if (upg->func->lic_upgrade) {
++            ret = upg->func->lic_upgrade(fw_file_buf, fw_file_len);
++        } else {
++            FTS_INFO("lic_upgrade function is null, no upgrade");
++        }
++#endif
++        if (upg->func->upgrade) {
++            ret = upg->func->upgrade(fw_file_buf, fw_file_len);
++        } else {
++            FTS_INFO("upgrade function is null, no upgrade");
++        }
++    }
++
++    if (ret < 0) {
++        FTS_ERROR("upgrade fw bin failed");
++        fts_fwupg_reset_in_boot();
++        goto err_bin;
++    }
++
++    FTS_INFO("upgrade fw bin success");
++    ret = 0;
++
++err_bin:
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_switch(ENABLE);
++#endif
++    fts_irq_enable();
++    upg->ts_data->fw_loading = 0;
++
++    if (fw_file_buf) {
++        vfree(fw_file_buf);
++        fw_file_buf = NULL;
++    }
++    return ret;
++}
++
++int fts_enter_test_environment(bool test_state)
++{
++    return 0;
++}
++#if FTS_AUTO_LIC_UPGRADE_EN
++static int fts_lic_get_vid_in_tp(u16 *vid)
++{
++    int ret = 0;
++    u8 val[2] = { 0 };
++
++    if (NULL == vid) {
++        FTS_ERROR("vid is NULL");
++        return -EINVAL;
++    }
++
++    ret = fts_read_reg(FTS_REG_VENDOR_ID, &val[0]);
++    if (fts_data->ic_info.is_incell)
++        ret = fts_read_reg(FTS_REG_MODULE_ID, &val[1]);
++    if (ret < 0) {
++        FTS_ERROR("read vid from tp fail");
++        return ret;
++    }
++
++    *vid = *(u16 *)val;
++    return 0;
++}
++
++static int fts_lic_get_vid_in_host(struct fts_upgrade *upg, u16 *vid)
++{
++    u8 val[2] = { 0 };
++    u8 *licbuf = NULL;
++    u32 conf_saddr = 0;
++
++    if (!upg || !upg->func || !upg->lic || !vid) {
++        FTS_ERROR("upgrade/func/get_hlic_ver/lic/vid is null");
++        return -EINVAL;
++    }
++
++    if (upg->lic_length < FTS_MAX_LEN_SECTOR) {
++        FTS_ERROR("lic length(%x) fail", upg->lic_length);
++        return -EINVAL;
++    }
++
++    licbuf  = upg->lic;
++    conf_saddr = upg->func->fwcfgoff;
++    val[0] = licbuf[conf_saddr + FTS_CONIFG_VENDORID_OFF];
++    if (fts_data->ic_info.is_incell)
++        val[1] = licbuf[conf_saddr + FTS_CONIFG_MODULEID_OFF];
++
++    *vid = *(u16 *)val;
++    return 0;
++}
++
++static int fts_lic_get_ver_in_tp(u8 *ver)
++{
++    int ret = 0;
++
++    if (NULL == ver) {
++        FTS_ERROR("ver is NULL");
++        return -EINVAL;
++    }
++
++    ret = fts_read_reg(FTS_REG_LIC_VER, ver);
++    if (ret < 0) {
++        FTS_ERROR("read lcd initcode ver from tp fail");
++        return ret;
++    }
++
++    return 0;
++}
++
++static int fts_lic_get_ver_in_host(struct fts_upgrade *upg, u8 *ver)
++{
++    int ret = 0;
++
++    if (!upg || !upg->func || !upg->func->get_hlic_ver || !upg->lic) {
++        FTS_ERROR("upgrade/func/get_hlic_ver/lic is null");
++        return -EINVAL;
++    }
++
++    ret = upg->func->get_hlic_ver(upg->lic);
++    if (ret < 0) {
++        FTS_ERROR("get host lcd initial code version fail");
++        return ret;
++    }
++
++    *ver = (u8)ret;
++    return ret;
++}
++
++static bool fts_lic_need_upgrade(struct fts_upgrade *upg)
++{
++    int ret = 0;
++    u8 initcode_ver_in_tp = 0;
++    u8 initcode_ver_in_host = 0;
++    u16 vid_in_tp = 0;
++    u16 vid_in_host = 0;
++    bool fwvalid = false;
++
++    fwvalid = fts_fwupg_check_fw_valid();
++    if ( !fwvalid) {
++        FTS_INFO("fw is invalid, no upgrade lcd init code");
++        return false;
++    }
++
++    ret = fts_lic_get_vid_in_host(upg, &vid_in_host);
++    if (ret < 0) {
++        FTS_ERROR("vendor id in host invalid");
++        return false;
++    }
++
++    ret = fts_lic_get_vid_in_tp(&vid_in_tp);
++    if (ret < 0) {
++        FTS_ERROR("vendor id in tp invalid");
++        return false;
++    }
++
++    FTS_DEBUG("vid in tp:0x%04x, host:0x%04x", vid_in_tp, vid_in_host);
++    if (vid_in_tp != vid_in_host) {
++        FTS_INFO("vendor id in tp&host are different, no upgrade lic");
++        return false;
++    }
++
++    ret = fts_lic_get_ver_in_host(upg, &initcode_ver_in_host);
++    if (ret < 0) {
++        FTS_ERROR("init code in host invalid");
++        return false;
++    }
++
++    ret = fts_lic_get_ver_in_tp(&initcode_ver_in_tp);
++    if (ret < 0) {
++        FTS_ERROR("read reg0xE4 fail");
++        return false;
++    }
++
++    FTS_DEBUG("lcd initial code version in tp:%x, host:%x",
++              initcode_ver_in_tp, initcode_ver_in_host);
++    if (0xA5 == initcode_ver_in_tp) {
++        FTS_INFO("lcd init code ver is 0xA5, don't upgade init code");
++        return false;
++    } else if (0xFF == initcode_ver_in_tp) {
++        FTS_DEBUG("lcd init code in tp is invalid, need upgrade init code");
++        return true;
++    } else if (initcode_ver_in_tp < initcode_ver_in_host)
++        return true;
++    else
++        return false;
++}
++
++static int fts_lic_upgrade(struct fts_upgrade *upg)
++{
++    int ret = 0;
++    bool hlic_upgrade = false;
++    int upgrade_count = 0;
++    u8 ver = 0;
++
++    FTS_INFO("lcd initial code auto upgrade function");
++    if ((!upg) || (!upg->func) || (!upg->func->lic_upgrade)) {
++        FTS_ERROR("lcd upgrade function is null");
++        return -EINVAL;
++    }
++
++    hlic_upgrade = fts_lic_need_upgrade(upg);
++    FTS_INFO("lcd init code upgrade flag:%d", hlic_upgrade);
++    if (hlic_upgrade) {
++        FTS_INFO("lcd initial code need upgrade, upgrade begin...");
++        do {
++            FTS_INFO("lcd initial code upgrade times:%d", upgrade_count);
++            upgrade_count++;
++
++            ret = upg->func->lic_upgrade(upg->lic, upg->lic_length);
++            if (ret < 0) {
++                fts_fwupg_reset_in_boot();
++            } else {
++                fts_lic_get_ver_in_tp(&ver);
++                FTS_INFO("success upgrade to lcd initcode ver:%02x", ver);
++                break;
++            }
++        } while (upgrade_count < 2);
++    } else {
++        FTS_INFO("lcd initial code don't need upgrade");
++    }
++
++    return ret;
++}
++#endif /* FTS_AUTO_LIC_UPGRADE_EN */
++
++
++static int fts_param_get_ver_in_tp(u8 *ver)
++{
++    int ret = 0;
++
++    if (NULL == ver) {
++        FTS_ERROR("ver is NULL");
++        return -EINVAL;
++    }
++
++    ret = fts_read_reg(FTS_REG_IDE_PARA_VER_ID, ver);
++    if (ret < 0) {
++        FTS_ERROR("read fw param ver from tp fail");
++        return ret;
++    }
++
++    if ((0x00 == *ver) || (0xFF == *ver)) {
++        FTS_INFO("param version in tp invalid");
++        return -EIO;
++    }
++
++    return 0;
++}
++
++static int fts_param_get_ver_in_host(struct fts_upgrade *upg, u8 *ver)
++{
++    if ((!upg) || (!upg->func) || (!upg->fw) || (!ver)) {
++        FTS_ERROR("fts_data/upgrade/func/fw/ver is NULL");
++        return -EINVAL;
++    }
++
++    if (upg->fw_length < upg->func->paramcfgveroff) {
++        FTS_ERROR("fw len(%x) < paramcfg ver offset(%x)",
++                  upg->fw_length, upg->func->paramcfgveroff);
++        return -EINVAL;
++    }
++
++    FTS_INFO("fw paramcfg version offset:%x", upg->func->paramcfgveroff);
++    *ver = upg->fw[upg->func->paramcfgveroff];
++
++    if ((0x00 == *ver) || (0xFF == *ver)) {
++        FTS_INFO("param version in host invalid");
++        return -EIO;
++    }
++
++    return 0;
++}
++
++/*
++ * return: < 0 : error
++ *         == 0: no ide
++ *         == 1: ide
++ */
++static int fts_param_ide_in_host(struct fts_upgrade *upg)
++{
++    u32 off = 0;
++
++    if ((!upg) || (!upg->func) || (!upg->fw)) {
++        FTS_ERROR("fts_data/upgrade/func/fw is NULL");
++        return -EINVAL;
++    }
++
++    if (upg->fw_length < upg->func->paramcfgoff + FTS_FW_IDE_SIG_LEN) {
++        FTS_INFO("fw len(%x) < paramcfg offset(%x), no IDE",
++                 upg->fw_length, upg->func->paramcfgoff + FTS_FW_IDE_SIG_LEN);
++        return 0;
++    }
++
++    off = upg->func->paramcfgoff;
++    if (0 == memcmp(&upg->fw[off], FTS_FW_IDE_SIG, FTS_FW_IDE_SIG_LEN)) {
++        FTS_INFO("fw in host is IDE version");
++        return 1;
++    }
++
++    FTS_INFO("fw in host isn't IDE version");
++    return 0;
++}
++
++/*
++ * return: < 0 : error
++ *         0   : no ide
++ *         1   : ide
++ */
++static int fts_param_ide_in_tp(u8 *val)
++{
++    int ret = 0;
++
++    ret = fts_read_reg(FTS_REG_IDE_PARA_STATUS, val);
++    if (ret < 0) {
++        FTS_ERROR("read IDE PARAM STATUS in tp fail");
++        return ret;
++    }
++
++    if ((*val != 0xFF) && ((*val & 0x80) == 0x80)) {
++        FTS_INFO("fw in tp is IDE version");
++        return 1;
++    }
++
++    FTS_INFO("fw in tp isn't IDE version");
++    return 0;
++}
++
++/************************************************************************
++ * fts_param_need_upgrade - check fw paramcfg need upgrade or not
++ *
++ * Return:  < 0 : error if paramcfg need upgrade
++ *          0   : no need upgrade
++ *          1   : need upgrade app + param
++ *          2   : need upgrade param
++ ***********************************************************************/
++static int fts_param_need_upgrade(struct fts_upgrade *upg)
++{
++    int ret = 0;
++    u8 val = 0;
++    int ide_in_host = 0;
++    int ide_in_tp = 0;
++    u8 ver_in_host = 0;
++    u8 ver_in_tp = 0;
++    bool fwvalid = false;
++
++    fwvalid = fts_fwupg_check_fw_valid();
++    if ( !fwvalid) {
++        FTS_INFO("fw is invalid, upgrade app+param");
++        return 1;
++    }
++
++    ide_in_host = fts_param_ide_in_host(upg);
++    if (ide_in_host < 0) {
++        FTS_INFO("fts_param_ide_in_host fail");
++        return ide_in_host;
++    }
++
++    ide_in_tp = fts_param_ide_in_tp(&val);
++    if (ide_in_tp < 0) {
++        FTS_INFO("fts_param_ide_in_tp fail");
++        return ide_in_tp;
++    }
++
++    if ((0 == ide_in_host) && (0 == ide_in_tp)) {
++        FTS_INFO("fw in host&tp are both no ide");
++        return 0;
++    } else if (ide_in_host != ide_in_tp) {
++        FTS_INFO("fw in host&tp not equal, need upgrade app+param");
++        return 1;
++    } else if ((1 == ide_in_host) && (1 == ide_in_tp)) {
++        FTS_INFO("fw in host&tp are both ide");
++        if ((val & 0x7F) != 0x00) {
++            FTS_INFO("param invalid, need upgrade param");
++            return 2;
++        }
++
++        ret = fts_param_get_ver_in_host(upg, &ver_in_host);
++        if (ret < 0) {
++            FTS_ERROR("param version in host invalid");
++            return ret;
++        }
++
++        ret = fts_param_get_ver_in_tp(&ver_in_tp);
++        if (ret < 0) {
++            FTS_ERROR("get IDE param ver in tp fail");
++            return ret;
++        }
++
++        FTS_INFO("fw paramcfg version in tp:%x, host:%x",
++                 ver_in_tp, ver_in_host);
++        if (ver_in_tp != ver_in_host) {
++            return 2;
++        }
++    }
++
++    return 0;
++}
++
++static int fts_fwupg_get_ver_in_tp(u8 *ver)
++{
++    int ret = 0;
++
++    if (NULL == ver) {
++        FTS_ERROR("ver is NULL");
++        return -EINVAL;
++    }
++
++    ret = fts_read_reg(FTS_REG_FW_VER, ver);
++    if (ret < 0) {
++        FTS_ERROR("read fw ver from tp fail");
++        return ret;
++    }
++
++    return 0;
++}
++
++static int fts_fwupg_get_ver_in_host(struct fts_upgrade *upg, u8 *ver)
++{
++    if ((!upg) || (!upg->func) || (!upg->fw) || (!ver)) {
++        FTS_ERROR("fts_data/upgrade/func/fw/ver is NULL");
++        return -EINVAL;
++    }
++
++    if (upg->fw_length < upg->func->fwveroff) {
++        FTS_ERROR("fw len(0x%0x) < fw ver offset(0x%x)",
++                  upg->fw_length, upg->func->fwveroff);
++        return -EINVAL;
++    }
++
++    FTS_INFO("fw version offset:0x%x", upg->func->fwveroff);
++    *ver = upg->fw[upg->func->fwveroff];
++    return 0;
++}
++
++static bool fts_fwupg_need_upgrade(struct fts_upgrade *upg)
++{
++    int ret = 0;
++    bool fwvalid = false;
++    u8 fw_ver_in_host = 0;
++    u8 fw_ver_in_tp = 0;
++
++    fwvalid = fts_fwupg_check_fw_valid();
++    if (fwvalid) {
++        ret = fts_fwupg_get_ver_in_host(upg, &fw_ver_in_host);
++        if (ret < 0) {
++            FTS_ERROR("get fw ver in host fail");
++            return false;
++        }
++
++        ret = fts_fwupg_get_ver_in_tp(&fw_ver_in_tp);
++        if (ret < 0) {
++            FTS_ERROR("get fw ver in tp fail");
++            return false;
++        }
++
++        FTS_INFO("fw version in tp:%x, host:%x", fw_ver_in_tp, fw_ver_in_host);
++        if (fw_ver_in_tp != fw_ver_in_host) {
++            return true;
++        }
++    } else {
++        FTS_INFO("fw invalid, need upgrade fw");
++        return true;
++    }
++
++    return false;
++}
++
++/************************************************************************
++ * Name: fts_fw_upgrade
++ * Brief: fw upgrade main entry, run in following steps
++ *        1. check fw version(A6), not equal, will upgrade app(+param)
++ *        2. if fw version equal, will check ide, will upgrade app(+param)
++ *        in the follow situation
++ *          a. host&tp IDE's type are not equal, will upgrade app+param
++ *          b. host&tp are both IDE's type, and param's version are not
++ *          equal, will upgrade param
++ * Input:
++ * Output:
++ * Return: return 0 if success, otherwise return error code
++ ***********************************************************************/
++int fts_fwupg_upgrade(struct fts_upgrade *upg)
++{
++    int ret = 0;
++    bool upgrade_flag = false;
++    int upgrade_count = 0;
++    u8 ver = 0;
++
++    FTS_INFO("fw auto upgrade function");
++    if ((NULL == upg) || (NULL == upg->func)) {
++        FTS_ERROR("upg/upg->func is null");
++        return -EINVAL;
++    }
++
++    upgrade_flag = fts_fwupg_need_upgrade(upg);
++    FTS_INFO("fw upgrade flag:%d", upgrade_flag);
++    do {
++        upgrade_count++;
++        if (upgrade_flag) {
++            FTS_INFO("upgrade fw app(times:%d)", upgrade_count);
++            if (upg->func->upgrade) {
++                ret = upg->func->upgrade(upg->fw, upg->fw_length);
++                if (ret < 0) {
++                    fts_fwupg_reset_in_boot();
++                } else {
++                    fts_fwupg_get_ver_in_tp(&ver);
++                    FTS_INFO("success upgrade to fw version %02x", ver);
++                    break;
++                }
++            } else {
++                FTS_ERROR("upgrade func/upgrade is null, return immediately");
++                ret = -ENODATA;
++                break;
++            }
++        } else {
++            if (upg->func->param_upgrade) {
++                ret = fts_param_need_upgrade(upg);
++                if (ret <= 0) {
++                    FTS_INFO("param don't need upgrade");
++                    break;
++                } else if (1 == ret) {
++                    FTS_INFO("force upgrade fw app(times:%d)", upgrade_count);
++                    if (upg->func->upgrade) {
++                        ret = upg->func->upgrade(upg->fw, upg->fw_length);
++                        if (ret < 0) {
++                            fts_fwupg_reset_in_boot();
++                        } else {
++                            break;
++                        }
++                    }
++                } else if (2 == ret) {
++                    FTS_INFO("upgrade param area(times:%d)", upgrade_count);
++                    ret = upg->func->param_upgrade(upg->fw, upg->fw_length);
++                    if (ret < 0) {
++                        fts_fwupg_reset_in_boot();
++                    } else {
++                        fts_param_get_ver_in_tp(&ver);
++                        FTS_INFO("success upgrade to fw param version %02x", ver);
++                        break;
++                    }
++                } else
++                    break;
++            } else {
++                break;
++            }
++        }
++    } while (upgrade_count < 2);
++
++    return ret;
++}
++
++/************************************************************************
++ * fts_fwupg_auto_upgrade - upgrade main entry
++ ***********************************************************************/
++static void fts_fwupg_auto_upgrade(struct fts_upgrade *upg)
++{
++    int ret = 0;
++
++    FTS_INFO("********************FTS enter upgrade********************");
++    if (!upg || !upg->ts_data) {
++        FTS_ERROR("upg/ts_data is null");
++        return ;
++    }
++
++    ret = fts_fwupg_upgrade(upg);
++    if (ret < 0)
++        FTS_ERROR("**********tp fw(app/param) upgrade failed**********");
++    else
++        FTS_INFO("**********tp fw(app/param) no upgrade/upgrade success**********");
++
++#if FTS_AUTO_LIC_UPGRADE_EN
++    ret = fts_lic_upgrade(upg);
++    if (ret < 0)
++        FTS_ERROR("**********lcd init code upgrade failed**********");
++    else
++        FTS_INFO("**********lcd init code no upgrade/upgrade success**********");
++#endif
++
++    FTS_INFO("********************FTS exit upgrade********************");
++}
++
++static int fts_fwupg_get_vendorid(struct fts_upgrade *upg, int *vid)
++{
++    int ret = 0;
++    bool fwvalid = false;
++    u8 vendor_id = 0;
++    u8 module_id = 0;
++    u32 fwcfg_addr = 0;
++    u8 cfgbuf[FTS_HEADER_LEN] = { 0 };
++
++    FTS_INFO("read vendor id from tp");
++    if ((!upg) || (!upg->func) || (!upg->ts_data) || (!vid)) {
++        FTS_ERROR("upgrade/func/ts_data/vid is null");
++        return -EINVAL;
++    }
++
++    fwvalid = fts_fwupg_check_fw_valid();
++    if (fwvalid) {
++        ret = fts_read_reg(FTS_REG_VENDOR_ID, &vendor_id);
++        if (upg->ts_data->ic_info.is_incell)
++            ret = fts_read_reg(FTS_REG_MODULE_ID, &module_id);
++    } else {
++        fwcfg_addr =  upg->func->fwcfgoff;
++        ret = fts_flash_read(fwcfg_addr, cfgbuf, FTS_HEADER_LEN);
++        vendor_id = cfgbuf[FTS_CONIFG_VENDORID_OFF];
++        if (upg->ts_data->ic_info.is_incell) {
++            if ((cfgbuf[FTS_CONIFG_MODULEID_OFF] +
++                 cfgbuf[FTS_CONIFG_MODULEID_OFF + 1]) == 0xFF)
++                module_id = cfgbuf[FTS_CONIFG_MODULEID_OFF];
++        }
++    }
++
++    if (ret < 0) {
++        FTS_ERROR("fail to get vendor id from tp");
++        return ret;
++    }
++
++    *vid = (int)((module_id << 8) + vendor_id);
++    return 0;
++}
++
++static int fts_fwupg_get_module_info(struct fts_upgrade *upg)
++{
++    int ret = 0;
++    int i = 0;
++    struct upgrade_module *info = &module_list[0];
++
++    if (!upg || !upg->ts_data) {
++        FTS_ERROR("upg/ts_data is null");
++        return -EINVAL;
++    }
++
++    if (FTS_GET_MODULE_NUM > 1) {
++        /* support multi modules, must read correct module id(vendor id) */
++        ret = fts_fwupg_get_vendorid(upg, &upg->module_id);
++        if (ret < 0) {
++            FTS_ERROR("get vendor id failed");
++            return ret;
++        }
++        FTS_INFO("module id:%04x", upg->module_id);
++        for (i = 0; i < FTS_GET_MODULE_NUM; i++) {
++            info = &module_list[i];
++            if (upg->module_id == info->id) {
++                FTS_INFO("module id match, get module info pass");
++                break;
++            }
++        }
++        if (i >= FTS_GET_MODULE_NUM) {
++            FTS_ERROR("no module id match, don't get file");
++            return -ENODATA;
++        }
++    }
++
++    upg->module_info = info;
++    return 0;
++}
++
++static int fts_get_fw_file_via_request_firmware(struct fts_upgrade *upg)
++{
++    int ret = 0;
++    const struct firmware *fw = NULL;
++    u8 *tmpbuf = NULL;
++    char fwname[FILE_NAME_LENGTH] = { 0 };
++
++    if (!upg || !upg->ts_data || !upg->ts_data->dev) {
++        FTS_ERROR("upg/ts_data/dev is null");
++        return -EINVAL;
++    }
++
++    snprintf(fwname, FILE_NAME_LENGTH, "%s%s.bin", \
++             FTS_FW_NAME_PREX_WITH_REQUEST, \
++             upg->module_info->vendor_name);
++
++    ret = request_firmware(&fw, fwname, upg->ts_data->dev);
++    if (0 == ret) {
++        FTS_INFO("firmware(%s) request successfully", fwname);
++        tmpbuf = vmalloc(fw->size);
++        if (NULL == tmpbuf) {
++            FTS_ERROR("fw buffer vmalloc fail");
++            ret = -ENOMEM;
++        } else {
++            memcpy(tmpbuf, fw->data, fw->size);
++            upg->fw = tmpbuf;
++            upg->fw_length = fw->size;
++            upg->fw_from_request = 1;
++        }
++    } else {
++        FTS_INFO("firmware(%s) request fail,ret=%d", fwname, ret);
++    }
++
++    if (fw != NULL) {
++        release_firmware(fw);
++        fw = NULL;
++    }
++
++    return ret;
++}
++
++static int fts_get_fw_file_via_i(struct fts_upgrade *upg)
++{
++    upg->fw = upg->module_info->fw_file;
++    upg->fw_length = upg->module_info->fw_len;
++    upg->fw_from_request = 0;
++
++    return 0;
++}
++
++/*****************************************************************************
++ *  Name: fts_fwupg_get_fw_file
++ *  Brief: get fw image/file,
++ *         If support muitl modules, please set FTS_GET_MODULE_NUM, and FTS_-
++ *         MODULE_ID/FTS_MODULE_NAME;
++ *         If get fw via .i file, please set FTS_FW_REQUEST_SUPPORT=0, and F-
++ *         TS_MODULE_ID; will use module id to distingwish different modules;
++ *         If get fw via reques_firmware(), please set FTS_FW_REQUEST_SUPPORT
++ *         =1, and FTS_MODULE_NAME; fw file name will be composed of "focalt-
++ *         ech_ts_fw_" & FTS_VENDOR_NAME;
++ *
++ *         If have flash, module_id=vendor_id, If non-flash,module_id need
++ *         transfer from LCD driver(gpio or lcm_id or ...);
++ *  Input:
++ *  Output:
++ *  Return: return 0 if success, otherwise return error code
++ *****************************************************************************/
++static int fts_fwupg_get_fw_file(struct fts_upgrade *upg)
++{
++    int ret = 0;
++    bool get_fw_i_flag = false;
++
++    FTS_DEBUG("get upgrade fw file");
++    if (!upg || !upg->ts_data) {
++        FTS_ERROR("upg/ts_data is null");
++        return -EINVAL;
++    }
++
++    ret = fts_fwupg_get_module_info(upg);
++    if ((ret < 0) || (!upg->module_info)) {
++        FTS_ERROR("get module info fail");
++        return ret;
++    }
++
++    if (FTS_FW_REQUEST_SUPPORT) {
++        ret = fts_get_fw_file_via_request_firmware(upg);
++        if (ret != 0) {
++            get_fw_i_flag = true;
++        }
++    } else {
++        get_fw_i_flag = true;
++    }
++
++    if (get_fw_i_flag) {
++        ret = fts_get_fw_file_via_i(upg);
++    }
++
++    upg->lic = upg->fw;
++    upg->lic_length = upg->fw_length;
++
++    FTS_INFO("upgrade fw file len:%d", upg->fw_length);
++    if ((upg->fw_length < FTS_MIN_LEN)
++        || (upg->fw_length > FTS_MAX_LEN_FILE)) {
++        FTS_ERROR("fw file len(%d) fail", upg->fw_length);
++        return -ENODATA;
++    }
++
++    return ret;
++}
++
++static void fts_fwupg_init_ic_detail(struct fts_upgrade *upg)
++{
++    if (upg && upg->func && upg->func->init) {
++        upg->func->init(upg->fw, upg->fw_length);
++    }
++}
++
++/*****************************************************************************
++ *  Name: fts_fwupg_work
++ *  Brief: 1. get fw image/file
++ *         2. ic init if have
++ *         3. call upgrade main function(fts_fwupg_auto_upgrade)
++ *  Input:
++ *  Output:
++ *  Return:
++ *****************************************************************************/
++static void fts_fwupg_work(struct work_struct *work)
++{
++    int ret = 0;
++    struct fts_upgrade *upg = fwupgrade;
++
++#if !FTS_AUTO_UPGRADE_EN
++    FTS_INFO("FTS_AUTO_UPGRADE_EN is disabled, not upgrade when power on");
++    return ;
++#endif
++
++    FTS_INFO("fw upgrade work function");
++    if (!upg || !upg->ts_data) {
++        FTS_ERROR("upg/ts_data is null");
++        return ;
++    }
++
++    upg->ts_data->fw_loading = 1;
++    fts_irq_disable();
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_switch(DISABLE);
++#endif
++
++    /* get fw */
++    ret = fts_fwupg_get_fw_file(upg);
++    if (ret < 0) {
++        FTS_ERROR("get file fail, can't upgrade");
++    } else {
++        /* ic init if have */
++        fts_fwupg_init_ic_detail(upg);
++        /* run auto upgrade */
++        fts_fwupg_auto_upgrade(upg);
++    }
++
++#if FTS_ESDCHECK_EN
++    fts_esdcheck_switch(ENABLE);
++#endif
++    fts_irq_enable();
++    upg->ts_data->fw_loading = 0;
++}
++
++int fts_fwupg_init(struct fts_ts_data *ts_data)
++{
++    int i = 0;
++    int j = 0;
++    int ic_stype = 0;
++    struct upgrade_func *func = upgrade_func_list[0];
++    int func_count = sizeof(upgrade_func_list) / sizeof(upgrade_func_list[0]);
++
++    FTS_INFO("fw upgrade init function");
++
++    if (!ts_data || !ts_data->ts_workqueue) {
++        FTS_ERROR("ts_data/workqueue is NULL, can't run upgrade function");
++        return -EINVAL;
++    }
++
++    if (0 == func_count) {
++        FTS_ERROR("no upgrade function in tp driver");
++        return -ENODATA;
++    }
++
++    fwupgrade = (struct fts_upgrade *)kzalloc(sizeof(*fwupgrade), GFP_KERNEL);
++    if (NULL == fwupgrade) {
++        FTS_ERROR("malloc memory for upgrade fail");
++        return -ENOMEM;
++    }
++
++    ic_stype = ts_data->ic_info.ids.type;
++    if (1 == func_count) {
++        fwupgrade->func = func;
++    } else {
++        for (i = 0; i < func_count; i++) {
++            func = upgrade_func_list[i];
++            for (j = 0; j < FTX_MAX_COMPATIBLE_TYPE; j++) {
++                if (0 == func->ctype[j])
++                    break;
++                else if (func->ctype[j] == ic_stype) {
++                    FTS_INFO("match upgrade function,type:%x", (int)func->ctype[j]);
++                    fwupgrade->func = func;
++                }
++            }
++        }
++    }
++
++    if (NULL == fwupgrade->func) {
++        FTS_ERROR("no upgrade function match, can't upgrade");
++        kfree(fwupgrade);
++        fwupgrade = NULL;
++        return -ENODATA;
++    }
++
++    fwupgrade->ts_data = ts_data;
++    INIT_WORK(&ts_data->fwupg_work, fts_fwupg_work);
++    queue_work(ts_data->ts_workqueue, &ts_data->fwupg_work);
++
++    return 0;
++}
++
++int fts_fwupg_exit(struct fts_ts_data *ts_data)
++{
++    FTS_FUNC_ENTER();
++    if (fwupgrade) {
++        if (fwupgrade->fw_from_request) {
++            vfree(fwupgrade->fw);
++            fwupgrade->fw = NULL;
++        }
++
++        kfree(fwupgrade);
++        fwupgrade = NULL;
++    }
++    FTS_FUNC_EXIT();
++    return 0;
++}
+diff --git a/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_flash.h b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_flash.h
+new file mode 100644
+index 000000000..fc6050272
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_flash.h
+@@ -0,0 +1,205 @@
++/************************************************************************
++* Copyright (C) 2012-2019, Focaltech Systems (R)£¬All Rights Reserved.
++*
++* File Name: focaltech_flash.h
++*
++* Author: Focaltech Driver Team
++*
++* Created: 2016-08-07
++*
++* Abstract:
++*
++************************************************************************/
++#ifndef __LINUX_FOCALTECH_FLASH_H__
++#define __LINUX_FOCALTECH_FLASH_H__
++
++/*****************************************************************************
++* 1.Included header files
++*****************************************************************************/
++#include "focaltech_core.h"
++
++/*****************************************************************************
++* Private constant and macro definitions using #define
++*****************************************************************************/
++#define FTS_CMD_RESET                               0x07
++#define FTS_ROMBOOT_CMD_SET_PRAM_ADDR               0xAD
++#define FTS_ROMBOOT_CMD_SET_PRAM_ADDR_LEN           4
++#define FTS_ROMBOOT_CMD_WRITE                       0xAE
++#define FTS_ROMBOOT_CMD_START_APP                   0x08
++#define FTS_DELAY_PRAMBOOT_START                    10
++#define FTS_ROMBOOT_CMD_ECC                         0xCC
++#define FTS_PRAM_SADDR                              0x000000
++#define FTS_DRAM_SADDR                              0xD00000
++
++#define FTS_CMD_READ                                0x03
++#define FTS_CMD_READ_DELAY                          1
++#define FTS_CMD_READ_LEN                            4
++#define FTS_CMD_FLASH_TYPE                          0x05
++#define FTS_CMD_FLASH_MODE                          0x09
++#define FLASH_MODE_WRITE_FLASH_VALUE                0x0A
++#define FLASH_MODE_UPGRADE_VALUE                    0x0B
++#define FLASH_MODE_LIC_VALUE                        0x0C
++#define FLASH_MODE_PARAM_VALUE                      0x0D
++#define FTS_CMD_ERASE_APP                           0x61
++#define FTS_REASE_APP_DELAY                         1350
++#define FTS_ERASE_SECTOR_DELAY                      60
++#define FTS_RETRIES_REASE                           50
++#define FTS_RETRIES_DELAY_REASE                     200
++#define FTS_CMD_FLASH_STATUS                        0x6A
++#define FTS_CMD_FLASH_STATUS_LEN                    2
++#define FTS_CMD_FLASH_STATUS_NOP                    0x0000
++#define FTS_CMD_FLASH_STATUS_ECC_OK                 0xF055
++#define FTS_CMD_FLASH_STATUS_ERASE_OK               0xF0AA
++#define FTS_CMD_FLASH_STATUS_WRITE_OK               0x1000
++#define FTS_CMD_ECC_INIT                            0x64
++#define FTS_CMD_ECC_CAL                             0x65
++#define FTS_CMD_ECC_CAL_LEN                         6
++#define FTS_RETRIES_ECC_CAL                         10
++#define FTS_RETRIES_DELAY_ECC_CAL                   50
++#define FTS_CMD_ECC_READ                            0x66
++#define FTS_CMD_DATA_LEN                            0xB0
++#define FTS_CMD_APP_DATA_LEN_INCELL                 0x7A
++#define FTS_CMD_DATA_LEN_LEN                        4
++#define FTS_CMD_WRITE                               0xBF
++#define FTS_RETRIES_WRITE                           100
++#define FTS_RETRIES_DELAY_WRITE                     1
++#define FTS_CMD_WRITE_LEN                           6
++#define FTS_DELAY_READ_ID                           20
++#define FTS_DELAY_UPGRADE_RESET                     80
++#define PRAMBOOT_MIN_SIZE                           0x120
++#define PRAMBOOT_MAX_SIZE                           (64*1024)
++#define FTS_FLASH_PACKET_LENGTH                     32     /* max=128 */
++#define FTS_MAX_LEN_ECC_CALC                        0xFFFE /* must be even */
++#define FTS_MIN_LEN                                 0x120
++#define FTS_MAX_LEN_FILE                            (128 * 1024)
++#define FTS_MAX_LEN_APP                             (64 * 1024)
++#define FTS_MAX_LEN_SECTOR                          (4 * 1024)
++#define FTS_CONIFG_VENDORID_OFF                     0x04
++#define FTS_CONIFG_MODULEID_OFF                     0x1E
++#define FTS_CONIFG_PROJECTID_OFF                    0x20
++#define FTS_APPINFO_OFF                             0x100
++#define FTS_APPINFO_APPLEN_OFF                      0x00
++#define FTS_APPINFO_APPLEN2_OFF                     0x12
++#define FTS_REG_UPGRADE                             0xFC
++#define FTS_REG_UPGRADE2                            0xBC
++#define FTS_UPGRADE_AA                              0xAA
++#define FTS_UPGRADE_55                              0x55
++#define FTS_DELAY_UPGRADE_AA                        10
++#define FTS_UPGRADE_LOOP                            30
++#define FTS_HEADER_LEN                              32
++#define FTS_FW_BIN_FILEPATH                         "/sdcard/"
++#define FTS_FW_IDE_SIG                              "IDE_"
++#define FTS_FW_IDE_SIG_LEN                          4
++#define MAX_MODULE_VENDOR_NAME_LEN                  16
++
++#define FTS_ROMBOOT_CMD_ECC_NEW_LEN                 7
++#define FTS_ECC_FINISH_TIMEOUT                      100
++#define FTS_ROMBOOT_CMD_ECC_FINISH                  0xCE
++#define FTS_ROMBOOT_CMD_ECC_FINISH_OK_A5            0xA5
++#define FTS_ROMBOOT_CMD_ECC_FINISH_OK_00            0x00
++#define FTS_ROMBOOT_CMD_ECC_READ                    0xCD
++#define AL2_FCS_COEF                ((1 << 15) + (1 << 10) + (1 << 3))
++
++#define FTS_APP_INFO_OFFSET                         0x100
++
++enum FW_STATUS {
++    FTS_RUN_IN_ERROR,
++    FTS_RUN_IN_APP,
++    FTS_RUN_IN_ROM,
++    FTS_RUN_IN_PRAM,
++    FTS_RUN_IN_BOOTLOADER,
++};
++
++enum FW_FLASH_MODE {
++    FLASH_MODE_APP,
++    FLASH_MODE_LIC,
++    FLASH_MODE_PARAM,
++    FLASH_MODE_ALL,
++};
++
++enum ECC_CHECK_MODE {
++    ECC_CHECK_MODE_XOR,
++    ECC_CHECK_MODE_CRC16,
++};
++
++/*****************************************************************************
++* Private enumerations, structures and unions using typedef
++*****************************************************************************/
++/* IC info */
++struct upgrade_func {
++    u64 ctype[FTX_MAX_COMPATIBLE_TYPE];
++    u32 fwveroff;
++    u32 fwcfgoff;
++    u32 appoff;
++    u32 licoff;
++    u32 paramcfgoff;
++    u32 paramcfgveroff;
++    u32 paramcfg2off;
++    int pram_ecc_check_mode;
++    int fw_ecc_check_mode;
++    bool new_return_value_from_ic;
++    bool appoff_handle_in_ic;
++    bool is_reset_register_BC;
++    bool read_boot_id_need_reset;
++    bool hid_supported;
++    bool pramboot_supported;
++    u8 *pramboot;
++    u32 pb_length;
++    int (*init)(u8 *, u32);
++    int (*upgrade)(u8 *, u32);
++    int (*get_hlic_ver)(u8 *);
++    int (*lic_upgrade)(u8 *, u32);
++    int (*param_upgrade)(u8 *, u32);
++    int (*force_upgrade)(u8 *, u32);
++};
++
++struct upgrade_setting_nf {
++    u8 rom_idh;
++    u8 rom_idl;
++    u16 reserved;
++    u32 app2_offset;
++    u32 ecclen_max;
++    u8 eccok_val;
++    u8 upgsts_boot;
++    u8 delay_init;
++    bool spi_pe;
++    bool half_length;
++    bool fd_check;
++    bool drwr_support;
++};
++
++struct upgrade_module {
++    int id;
++    char vendor_name[MAX_MODULE_VENDOR_NAME_LEN];
++    u8 *fw_file;
++    u32 fw_len;
++};
++
++struct fts_upgrade {
++    struct fts_ts_data *ts_data;
++    struct upgrade_module *module_info;
++    struct upgrade_func *func;
++    struct upgrade_setting_nf *setting_nf;
++    int module_id;
++    bool fw_from_request;
++    u8 *fw;
++    u32 fw_length;
++    u8 *lic;
++    u32 lic_length;
++};
++
++/*****************************************************************************
++* Global variable or extern global variabls/functions
++*****************************************************************************/
++extern struct upgrade_func upgrade_func_ft7511;
++
++/*****************************************************************************
++* Static function prototypes
++*****************************************************************************/
++int fts_fwupg_reset_in_boot(void);
++int fts_fwupg_enter_into_boot(void);
++int fts_fwupg_erase(u32 delay);
++int fts_fwupg_ecc_cal(u32 saddr, u32 len);
++int fts_flash_write_buf(u32 saddr, u8 *buf, u32 len, u32 delay);
++int fts_fwupg_upgrade(struct fts_upgrade *upg);
++#endif
+diff --git a/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_flash/Makefile b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_flash/Makefile
+new file mode 100644
+index 000000000..46829118f
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_flash/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_TOUCHSCREEN_FTS) += focaltech_upgrade_ft7511.o
+\ No newline at end of file
+diff --git a/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_flash/focaltech_upgrade_ft7511.c b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_flash/focaltech_upgrade_ft7511.c
+new file mode 100644
+index 000000000..f5d0e06e3
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_flash/focaltech_upgrade_ft7511.c
+@@ -0,0 +1,154 @@
++/*
++ *
++ * FocalTech fts TouchScreen driver.
++ *
++ * Copyright (c) 2012-2019, Focaltech Ltd. All rights reserved.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++/*****************************************************************************
++*
++* File Name: focaltech_upgrade_ft7511.c
++*
++* Author: Focaltech Driver Team
++*
++* Created: 2016-08-15
++*
++* Abstract:
++*
++* Reference:
++*
++*****************************************************************************/
++/*****************************************************************************
++* 1.Included header files
++*****************************************************************************/
++#include "../focaltech_flash.h"
++
++/*****************************************************************************
++* Static function prototypes
++*****************************************************************************/
++static int fts_ft7511_init(u8 *buf, u32 len)
++{
++    if ((!buf) || (len < FTS_MIN_LEN)) {
++        FTS_ERROR("upg is null/fw length fail");
++        return -EINVAL;
++    }
++
++    upgrade_func_ft7511.fwveroff = len - 2;
++    return 0;
++}
++
++/************************************************************************
++* Name: fts_ft7511_upgrade
++* Brief:
++* Input:
++* Output:
++* Return: return 0 if success, otherwise return error code
++***********************************************************************/
++static int fts_ft7511_upgrade(u8 *buf, u32 len)
++{
++    int ret = 0;
++    u32 start_addr = 0;
++    u8 cmd[4] = { 0 };
++    int ecc_in_host = 0;
++    int ecc_in_tp = 0;
++
++    if (NULL == buf) {
++        FTS_ERROR("fw buf is null");
++        return -EINVAL;
++    }
++
++    if ((len < FTS_MIN_LEN) || (len > (60 * 1024))) {
++        FTS_ERROR("fw buffer len(%x) fail", len);
++        return -EINVAL;
++    }
++
++    /* enter into upgrade environment */
++    ret = fts_fwupg_enter_into_boot();
++    if (ret < 0) {
++        FTS_ERROR("enter into pramboot/bootloader fail,ret=%d", ret);
++        goto fw_reset;
++    }
++
++    cmd[0] = FTS_CMD_FLASH_MODE;
++    cmd[1] = FLASH_MODE_UPGRADE_VALUE;
++    ret = fts_write(cmd, 2);
++    if (ret < 0) {
++        FTS_ERROR("upgrade mode(09) cmd write fail");
++        goto fw_reset;
++    }
++
++    cmd[0] = FTS_CMD_DATA_LEN;
++    cmd[1] = BYTE_OFF_16(len);
++    cmd[2] = BYTE_OFF_8(len);
++    cmd[3] = BYTE_OFF_0(len);
++    ret = fts_write(cmd, FTS_CMD_DATA_LEN_LEN);
++    if (ret < 0) {
++        FTS_ERROR("data len cmd write fail");
++        goto fw_reset;
++    }
++
++    ret = fts_fwupg_erase(FTS_REASE_APP_DELAY);
++    if (ret < 0) {
++        FTS_ERROR("erase cmd write fail");
++        goto fw_reset;
++    }
++
++    /* write app */
++    start_addr = upgrade_func_ft7511.appoff;
++    ecc_in_host = fts_flash_write_buf(start_addr, buf, len, 1);
++    if (ecc_in_host < 0 ) {
++        FTS_ERROR("lcd initial code write fail");
++        goto fw_reset;
++    }
++
++    /* ecc */
++    ecc_in_tp = fts_fwupg_ecc_cal(start_addr, len);
++    if (ecc_in_tp < 0 ) {
++        FTS_ERROR("ecc read fail");
++        goto fw_reset;
++    }
++
++    FTS_INFO("ecc in tp:%x, host:%x", ecc_in_tp, ecc_in_host);
++    if (ecc_in_tp != ecc_in_host) {
++        FTS_ERROR("ecc check fail");
++        goto fw_reset;
++    }
++
++    FTS_INFO("upgrade success, reset to normal boot");
++    ret = fts_fwupg_reset_in_boot();
++    if (ret < 0) {
++        FTS_ERROR("reset to normal boot fail");
++    }
++
++    msleep(200);
++    return 0;
++
++fw_reset:
++    FTS_INFO("upgrade fail, reset to normal boot");
++    ret = fts_fwupg_reset_in_boot();
++    if (ret < 0) {
++        FTS_ERROR("reset to normal boot fail");
++    }
++    return -EIO;
++}
++
++struct upgrade_func upgrade_func_ft7511 = {
++    .ctype = {0x02},
++    .fwveroff = 0x0000,
++    .fwcfgoff = 0xD780,
++    .appoff = 0x0000,
++    .pramboot_supported = false,
++    .hid_supported = true,
++    .init = fts_ft7511_init,
++    .upgrade = fts_ft7511_upgrade,
++};
+diff --git a/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_gesture.c b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_gesture.c
+new file mode 100644
+index 000000000..b65cf3945
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_gesture.c
+@@ -0,0 +1,460 @@
++/*
++ *
++ * FocalTech TouchScreen driver.
++ *
++ * Copyright (c) 2012-2019, Focaltech Ltd. All rights reserved.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++/*****************************************************************************
++*
++* File Name: focaltech_gestrue.c
++*
++* Author: Focaltech Driver Team
++*
++* Created: 2016-08-08
++*
++* Abstract:
++*
++* Reference:
++*
++*****************************************************************************/
++
++/*****************************************************************************
++* 1.Included header files
++*****************************************************************************/
++#include "focaltech_core.h"
++
++/******************************************************************************
++* Private constant and macro definitions using #define
++*****************************************************************************/
++#define KEY_GESTURE_U                           KEY_U
++#define KEY_GESTURE_UP                          KEY_UP
++#define KEY_GESTURE_DOWN                        KEY_DOWN
++#define KEY_GESTURE_LEFT                        KEY_LEFT
++#define KEY_GESTURE_RIGHT                       KEY_RIGHT
++#define KEY_GESTURE_O                           KEY_O
++#define KEY_GESTURE_E                           KEY_E
++#define KEY_GESTURE_M                           KEY_M
++#define KEY_GESTURE_L                           KEY_L
++#define KEY_GESTURE_W                           KEY_W
++#define KEY_GESTURE_S                           KEY_S
++#define KEY_GESTURE_V                           KEY_V
++#define KEY_GESTURE_C                           KEY_C
++#define KEY_GESTURE_Z                           KEY_Z
++
++#define GESTURE_LEFT                            0x20
++#define GESTURE_RIGHT                           0x21
++#define GESTURE_UP                              0x22
++#define GESTURE_DOWN                            0x23
++#define GESTURE_DOUBLECLICK                     0x24
++#define GESTURE_O                               0x30
++#define GESTURE_W                               0x31
++#define GESTURE_M                               0x32
++#define GESTURE_E                               0x33
++#define GESTURE_L                               0x44
++#define GESTURE_S                               0x46
++#define GESTURE_V                               0x54
++#define GESTURE_Z                               0x41
++#define GESTURE_C                               0x34
++
++/*****************************************************************************
++* Private enumerations, structures and unions using typedef
++*****************************************************************************/
++/*
++* gesture_id    - mean which gesture is recognised
++* point_num     - points number of this gesture
++* coordinate_x  - All gesture point x coordinate
++* coordinate_y  - All gesture point y coordinate
++* mode          - gesture enable/disable, need enable by host
++*               - 1:enable gesture function(default)  0:disable
++* active        - gesture work flag,
++*                 always set 1 when suspend, set 0 when resume
++*/
++struct fts_gesture_st {
++    u8 gesture_id;
++    u8 point_num;
++    u16 coordinate_x[FTS_GESTURE_POINTS_MAX];
++    u16 coordinate_y[FTS_GESTURE_POINTS_MAX];
++};
++
++/*****************************************************************************
++* Static variables
++*****************************************************************************/
++static struct fts_gesture_st fts_gesture_data;
++
++/*****************************************************************************
++* Global variable or extern global variabls/functions
++*****************************************************************************/
++
++/*****************************************************************************
++* Static function prototypes
++*****************************************************************************/
++static ssize_t fts_gesture_show(
++    struct device *dev, struct device_attribute *attr, char *buf)
++{
++    int count = 0;
++    u8 val = 0;
++    struct fts_ts_data *ts_data = fts_data;
++
++    mutex_lock(&ts_data->input_dev->mutex);
++    fts_read_reg(FTS_REG_GESTURE_EN, &val);
++    count = snprintf(buf, PAGE_SIZE, "Gesture Mode:%s\n",
++                     ts_data->gesture_mode ? "On" : "Off");
++    count += snprintf(buf + count, PAGE_SIZE, "Reg(0xD0)=%d\n", val);
++    mutex_unlock(&ts_data->input_dev->mutex);
++
++    return count;
++}
++
++static ssize_t fts_gesture_store(
++    struct device *dev,
++    struct device_attribute *attr, const char *buf, size_t count)
++{
++    struct fts_ts_data *ts_data = fts_data;
++
++    mutex_lock(&ts_data->input_dev->mutex);
++    if (FTS_SYSFS_ECHO_ON(buf)) {
++        FTS_DEBUG("enable gesture");
++        ts_data->gesture_mode = ENABLE;
++    } else if (FTS_SYSFS_ECHO_OFF(buf)) {
++        FTS_DEBUG("disable gesture");
++        ts_data->gesture_mode = DISABLE;
++    }
++    mutex_unlock(&ts_data->input_dev->mutex);
++
++    return count;
++}
++
++static ssize_t fts_gesture_buf_show(
++    struct device *dev, struct device_attribute *attr, char *buf)
++{
++    int count = 0;
++    int i = 0;
++    struct input_dev *input_dev = fts_data->input_dev;
++    struct fts_gesture_st *gesture = &fts_gesture_data;
++
++    mutex_lock(&input_dev->mutex);
++    count = snprintf(buf, PAGE_SIZE, "Gesture ID:%d\n", gesture->gesture_id);
++    count += snprintf(buf + count, PAGE_SIZE, "Gesture PointNum:%d\n",
++                      gesture->point_num);
++    count += snprintf(buf + count, PAGE_SIZE, "Gesture Points Buffer:\n");
++
++    /* save point data,max:6 */
++    for (i = 0; i < FTS_GESTURE_POINTS_MAX; i++) {
++        count += snprintf(buf + count, PAGE_SIZE, "%3d(%4d,%4d) ", i,
++                          gesture->coordinate_x[i], gesture->coordinate_y[i]);
++        if ((i + 1) % 4 == 0)
++            count += snprintf(buf + count, PAGE_SIZE, "\n");
++    }
++    count += snprintf(buf + count, PAGE_SIZE, "\n");
++    mutex_unlock(&input_dev->mutex);
++
++    return count;
++}
++
++static ssize_t fts_gesture_buf_store(
++    struct device *dev,
++    struct device_attribute *attr, const char *buf, size_t count)
++{
++    return -EPERM;
++}
++
++
++/* sysfs gesture node
++ *   read example: cat  fts_gesture_mode       ---read gesture mode
++ *   write example:echo 1 > fts_gesture_mode   --- write gesture mode to 1
++ *
++ */
++static DEVICE_ATTR(fts_gesture_mode, S_IRUGO | S_IWUSR, fts_gesture_show,
++                   fts_gesture_store);
++/*
++ *   read example: cat fts_gesture_buf        --- read gesture buf
++ */
++static DEVICE_ATTR(fts_gesture_buf, S_IRUGO | S_IWUSR,
++                   fts_gesture_buf_show, fts_gesture_buf_store);
++
++static struct attribute *fts_gesture_mode_attrs[] = {
++    &dev_attr_fts_gesture_mode.attr,
++    &dev_attr_fts_gesture_buf.attr,
++    NULL,
++};
++
++static struct attribute_group fts_gesture_group = {
++    .attrs = fts_gesture_mode_attrs,
++};
++
++static int fts_create_gesture_sysfs(struct device *dev)
++{
++    int ret = 0;
++
++    ret = sysfs_create_group(&dev->kobj, &fts_gesture_group);
++    if (ret) {
++        FTS_ERROR("gesture sys node create fail");
++        sysfs_remove_group(&dev->kobj, &fts_gesture_group);
++        return ret;
++    }
++
++    return 0;
++}
++
++static void fts_gesture_report(struct input_dev *input_dev, int gesture_id)
++{
++    int gesture;
++
++    FTS_DEBUG("gesture_id:0x%x", gesture_id);
++    switch (gesture_id) {
++    case GESTURE_LEFT:
++        gesture = KEY_GESTURE_LEFT;
++        break;
++    case GESTURE_RIGHT:
++        gesture = KEY_GESTURE_RIGHT;
++        break;
++    case GESTURE_UP:
++        gesture = KEY_GESTURE_UP;
++        break;
++    case GESTURE_DOWN:
++        gesture = KEY_GESTURE_DOWN;
++        break;
++    case GESTURE_DOUBLECLICK:
++        gesture = KEY_GESTURE_U;
++        break;
++    case GESTURE_O:
++        gesture = KEY_GESTURE_O;
++        break;
++    case GESTURE_W:
++        gesture = KEY_GESTURE_W;
++        break;
++    case GESTURE_M:
++        gesture = KEY_GESTURE_M;
++        break;
++    case GESTURE_E:
++        gesture = KEY_GESTURE_E;
++        break;
++    case GESTURE_L:
++        gesture = KEY_GESTURE_L;
++        break;
++    case GESTURE_S:
++        gesture = KEY_GESTURE_S;
++        break;
++    case GESTURE_V:
++        gesture = KEY_GESTURE_V;
++        break;
++    case GESTURE_Z:
++        gesture = KEY_GESTURE_Z;
++        break;
++    case  GESTURE_C:
++        gesture = KEY_GESTURE_C;
++        break;
++    default:
++        gesture = -1;
++        break;
++    }
++    /* report event key */
++    if (gesture != -1) {
++        FTS_DEBUG("Gesture Code=%d", gesture);
++        input_report_key(input_dev, gesture, 1);
++        input_sync(input_dev);
++        input_report_key(input_dev, gesture, 0);
++        input_sync(input_dev);
++    }
++}
++
++/*****************************************************************************
++* Name: fts_gesture_readdata
++* Brief: Read information about gesture: enable flag/gesture points..., if ges-
++*        ture enable, save gesture points' information, and report to OS.
++*        It will be called this function every intrrupt when FTS_GESTURE_EN = 1
++*
++*        gesture data length: 1(enable) + 1(reserve) + 2(header) + 6 * 4
++* Input: ts_data - global struct data
++*        data    - gesture data buffer if non-flash, else NULL
++* Output:
++* Return: 0 - read gesture data successfully, the report data is gesture data
++*         1 - tp not in suspend/gesture not enable in TP FW
++*         -Exx - error
++*****************************************************************************/
++int fts_gesture_readdata(struct fts_ts_data *ts_data, u8 *data)
++{
++    int ret = 0;
++    int i = 0;
++    int index = 0;
++    u8 buf[FTS_GESTURE_DATA_LEN] = { 0 };
++    struct input_dev *input_dev = ts_data->input_dev;
++    struct fts_gesture_st *gesture = &fts_gesture_data;
++
++    if (!ts_data->suspended || !ts_data->gesture_mode) {
++        return 1;
++    }
++
++
++    ret = fts_read_reg(FTS_REG_GESTURE_EN, &buf[0]);
++    if ((ret < 0) || (buf[0] != ENABLE)) {
++        FTS_DEBUG("gesture not enable in fw, don't process gesture");
++        return 1;
++    }
++
++    buf[2] = FTS_REG_GESTURE_OUTPUT_ADDRESS;
++    ret = fts_read(&buf[2], 1, &buf[2], FTS_GESTURE_DATA_LEN - 2);
++    if (ret < 0) {
++        FTS_ERROR("read gesture header data fail");
++        return ret;
++    }
++
++    /* init variable before read gesture point */
++    memset(gesture->coordinate_x, 0, FTS_GESTURE_POINTS_MAX * sizeof(u16));
++    memset(gesture->coordinate_y, 0, FTS_GESTURE_POINTS_MAX * sizeof(u16));
++    gesture->gesture_id = buf[2];
++    gesture->point_num = buf[3];
++    FTS_DEBUG("gesture_id=%d, point_num=%d",
++              gesture->gesture_id, gesture->point_num);
++
++    /* save point data,max:6 */
++    for (i = 0; i < FTS_GESTURE_POINTS_MAX; i++) {
++        index = 4 * i + 4;
++        gesture->coordinate_x[i] = (u16)(((buf[0 + index] & 0x0F) << 8)
++                                         + buf[1 + index]);
++        gesture->coordinate_y[i] = (u16)(((buf[2 + index] & 0x0F) << 8)
++                                         + buf[3 + index]);
++    }
++
++    /* report gesture to OS */
++    fts_gesture_report(input_dev, gesture->gesture_id);
++    return 0;
++}
++
++void fts_gesture_recovery(struct fts_ts_data *ts_data)
++{
++    if (ts_data->gesture_mode && ts_data->suspended) {
++        FTS_DEBUG("gesture recovery...");
++        fts_write_reg(0xD1, 0xFF);
++        fts_write_reg(0xD2, 0xFF);
++        fts_write_reg(0xD5, 0xFF);
++        fts_write_reg(0xD6, 0xFF);
++        fts_write_reg(0xD7, 0xFF);
++        fts_write_reg(0xD8, 0xFF);
++        fts_write_reg(FTS_REG_GESTURE_EN, ENABLE);
++    }
++}
++
++int fts_gesture_suspend(struct fts_ts_data *ts_data)
++{
++    int i = 0;
++    u8 state = 0xFF;
++
++    FTS_FUNC_ENTER();
++    if (enable_irq_wake(ts_data->irq)) {
++        FTS_DEBUG("enable_irq_wake(irq:%d) fail", ts_data->irq);
++    }
++
++    for (i = 0; i < 5; i++) {
++        fts_write_reg(0xD1, 0xFF);
++        fts_write_reg(0xD2, 0xFF);
++        fts_write_reg(0xD5, 0xFF);
++        fts_write_reg(0xD6, 0xFF);
++        fts_write_reg(0xD7, 0xFF);
++        fts_write_reg(0xD8, 0xFF);
++        fts_write_reg(FTS_REG_GESTURE_EN, ENABLE);
++        msleep(1);
++        fts_read_reg(FTS_REG_GESTURE_EN, &state);
++        if (state == ENABLE)
++            break;
++    }
++
++    if (i >= 5)
++        FTS_ERROR("make IC enter into gesture(suspend) fail,state:%x", state);
++    else
++        FTS_INFO("Enter into gesture(suspend) successfully");
++
++    FTS_FUNC_EXIT();
++    return 0;
++}
++
++int fts_gesture_resume(struct fts_ts_data *ts_data)
++{
++    int i = 0;
++    u8 state = 0xFF;
++
++    FTS_FUNC_ENTER();
++    if (disable_irq_wake(ts_data->irq)) {
++        FTS_DEBUG("disable_irq_wake(irq:%d) fail", ts_data->irq);
++    }
++
++    for (i = 0; i < 5; i++) {
++        fts_write_reg(FTS_REG_GESTURE_EN, DISABLE);
++        msleep(1);
++        fts_read_reg(FTS_REG_GESTURE_EN, &state);
++        if (state == DISABLE)
++            break;
++    }
++
++    if (i >= 5)
++        FTS_ERROR("make IC exit gesture(resume) fail,state:%x", state);
++    else
++        FTS_INFO("resume from gesture successfully");
++
++    FTS_FUNC_EXIT();
++    return 0;
++}
++
++int fts_gesture_init(struct fts_ts_data *ts_data)
++{
++    struct input_dev *input_dev = ts_data->input_dev;
++
++    FTS_FUNC_ENTER();
++    input_set_capability(input_dev, EV_KEY, KEY_POWER);
++    input_set_capability(input_dev, EV_KEY, KEY_GESTURE_U);
++    input_set_capability(input_dev, EV_KEY, KEY_GESTURE_UP);
++    input_set_capability(input_dev, EV_KEY, KEY_GESTURE_DOWN);
++    input_set_capability(input_dev, EV_KEY, KEY_GESTURE_LEFT);
++    input_set_capability(input_dev, EV_KEY, KEY_GESTURE_RIGHT);
++    input_set_capability(input_dev, EV_KEY, KEY_GESTURE_O);
++    input_set_capability(input_dev, EV_KEY, KEY_GESTURE_E);
++    input_set_capability(input_dev, EV_KEY, KEY_GESTURE_M);
++    input_set_capability(input_dev, EV_KEY, KEY_GESTURE_L);
++    input_set_capability(input_dev, EV_KEY, KEY_GESTURE_W);
++    input_set_capability(input_dev, EV_KEY, KEY_GESTURE_S);
++    input_set_capability(input_dev, EV_KEY, KEY_GESTURE_V);
++    input_set_capability(input_dev, EV_KEY, KEY_GESTURE_Z);
++    input_set_capability(input_dev, EV_KEY, KEY_GESTURE_C);
++
++    __set_bit(KEY_GESTURE_RIGHT, input_dev->keybit);
++    __set_bit(KEY_GESTURE_LEFT, input_dev->keybit);
++    __set_bit(KEY_GESTURE_UP, input_dev->keybit);
++    __set_bit(KEY_GESTURE_DOWN, input_dev->keybit);
++    __set_bit(KEY_GESTURE_U, input_dev->keybit);
++    __set_bit(KEY_GESTURE_O, input_dev->keybit);
++    __set_bit(KEY_GESTURE_E, input_dev->keybit);
++    __set_bit(KEY_GESTURE_M, input_dev->keybit);
++    __set_bit(KEY_GESTURE_W, input_dev->keybit);
++    __set_bit(KEY_GESTURE_L, input_dev->keybit);
++    __set_bit(KEY_GESTURE_S, input_dev->keybit);
++    __set_bit(KEY_GESTURE_V, input_dev->keybit);
++    __set_bit(KEY_GESTURE_C, input_dev->keybit);
++    __set_bit(KEY_GESTURE_Z, input_dev->keybit);
++
++    fts_create_gesture_sysfs(ts_data->dev);
++
++    memset(&fts_gesture_data, 0, sizeof(struct fts_gesture_st));
++    ts_data->gesture_mode = FTS_GESTURE_EN;
++
++    FTS_FUNC_EXIT();
++    return 0;
++}
++
++int fts_gesture_exit(struct fts_ts_data *ts_data)
++{
++    FTS_FUNC_ENTER();
++    sysfs_remove_group(&ts_data->dev->kobj, &fts_gesture_group);
++    FTS_FUNC_EXIT();
++    return 0;
++}
+diff --git a/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_i2c.c b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_i2c.c
+new file mode 100644
+index 000000000..ef129824a
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_i2c.c
+@@ -0,0 +1,193 @@
++/*
++ *
++ * FocalTech TouchScreen driver.
++ *
++ * Copyright (c) 2012-2019, FocalTech Systems, Ltd., all rights reserved.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++/************************************************************************
++*
++* File Name: focaltech_i2c.c
++*
++* Author: Focaltech Driver Team
++*
++* Created: 2016-08-04
++*
++* Abstract: i2c communication with TP
++*
++* Version: v1.0
++*
++* Revision History:
++*
++************************************************************************/
++
++/*****************************************************************************
++* Included header files
++*****************************************************************************/
++#include "focaltech_core.h"
++
++/*****************************************************************************
++* Private constant and macro definitions using #define
++*****************************************************************************/
++#define I2C_RETRY_NUMBER                    1
++#define I2C_BUF_LENGTH                      256
++
++/*****************************************************************************
++* Private enumerations, structures and unions using typedef
++*****************************************************************************/
++
++/*****************************************************************************
++* Static variables
++*****************************************************************************/
++
++/*****************************************************************************
++* Global variable or extern global variabls/functions
++*****************************************************************************/
++
++/*****************************************************************************
++* Static function prototypes
++*****************************************************************************/
++
++/*****************************************************************************
++* functions body
++*****************************************************************************/
++int fts_read(u8 *cmd, u32 cmdlen, u8 *data, u32 datalen)
++{
++    int ret = 0;
++    int i = 0;
++    struct fts_ts_data *ts_data = fts_data;
++    struct i2c_msg msg_list[2];
++    struct i2c_msg *msg = NULL;
++    int msg_num = 0;
++
++    /* must have data when read */
++    if (!ts_data || !ts_data->client || !data || !datalen
++        || (datalen >= I2C_BUF_LENGTH) || (cmdlen >= I2C_BUF_LENGTH)) {
++        FTS_ERROR("fts_data/client/cmdlen(%d)/data/datalen(%d) is invalid",
++                  cmdlen, datalen);
++        return -EINVAL;
++    }
++
++    mutex_lock(&ts_data->bus_lock);
++    memset(&msg_list[0], 0, sizeof(struct i2c_msg));
++    memset(&msg_list[1], 0, sizeof(struct i2c_msg));
++    memcpy(ts_data->bus_tx_buf, cmd, cmdlen);
++    msg_list[0].addr = ts_data->client->addr;
++    msg_list[0].flags = 0;
++    msg_list[0].len = cmdlen;
++    msg_list[0].buf = ts_data->bus_tx_buf;
++    msg_list[1].addr = ts_data->client->addr;
++    msg_list[1].flags = I2C_M_RD;
++    msg_list[1].len = datalen;
++    msg_list[1].buf = ts_data->bus_rx_buf;
++    if (cmd && cmdlen) {
++        msg = &msg_list[0];
++        msg_num = 2;
++    } else {
++        msg = &msg_list[1];
++        msg_num = 1;
++    }
++
++    for (i = 0; i < I2C_RETRY_NUMBER; i++) {
++        ret = i2c_transfer(ts_data->client->adapter, msg, msg_num);
++        if (ret < 0) {
++            FTS_ERROR("i2c_transfer(read) fail,ret:%d", ret);
++        } else {
++            memcpy(data, ts_data->bus_rx_buf, datalen);
++            break;
++        }
++    }
++
++    mutex_unlock(&ts_data->bus_lock);
++    return ret;
++}
++
++int fts_write(u8 *writebuf, u32 writelen)
++{
++    int ret = 0;
++    int i = 0;
++    struct fts_ts_data *ts_data = fts_data;
++    struct i2c_msg msgs;
++
++    if (!ts_data || !ts_data->client || !writebuf || !writelen
++        || (writelen >= I2C_BUF_LENGTH)) {
++        FTS_ERROR("fts_data/client/data/datalen(%d) is invalid", writelen);
++        return -EINVAL;
++    }
++
++    mutex_lock(&ts_data->bus_lock);
++    memset(&msgs, 0, sizeof(struct i2c_msg));
++    memcpy(ts_data->bus_tx_buf, writebuf, writelen);
++    msgs.addr = ts_data->client->addr;
++    msgs.flags = 0;
++    msgs.len = writelen;
++    msgs.buf = ts_data->bus_tx_buf;
++    for (i = 0; i < I2C_RETRY_NUMBER; i++) {
++        ret = i2c_transfer(ts_data->client->adapter, &msgs, 1);
++        if (ret < 0) {
++            FTS_ERROR("i2c_transfer(write) fail,ret:%d", ret);
++        } else {
++            break;
++        }
++    }
++    mutex_unlock(&ts_data->bus_lock);
++    return ret;
++}
++
++int fts_read_reg(u8 addr, u8 *value)
++{
++    return fts_read(&addr, 1, value, 1);
++}
++
++int fts_write_reg(u8 addr, u8 value)
++{
++    u8 buf[2] = { 0 };
++
++    buf[0] = addr;
++    buf[1] = value;
++    return fts_write(buf, sizeof(buf));
++}
++
++int fts_bus_init(struct fts_ts_data *ts_data)
++{
++    FTS_FUNC_ENTER();
++    ts_data->bus_tx_buf = kzalloc(I2C_BUF_LENGTH, GFP_KERNEL);
++    if (NULL == ts_data->bus_tx_buf) {
++        FTS_ERROR("failed to allocate memory for bus_tx_buf");
++        return -ENOMEM;
++    }
++
++    ts_data->bus_rx_buf = kzalloc(I2C_BUF_LENGTH, GFP_KERNEL);
++    if (NULL == ts_data->bus_rx_buf) {
++        FTS_ERROR("failed to allocate memory for bus_rx_buf");
++        return -ENOMEM;
++    }
++    FTS_FUNC_EXIT();
++    return 0;
++}
++
++int fts_bus_exit(struct fts_ts_data *ts_data)
++{
++    FTS_FUNC_ENTER();
++    if (ts_data && ts_data->bus_tx_buf) {
++        kfree(ts_data->bus_tx_buf);
++        ts_data->bus_tx_buf = NULL;
++    }
++
++    if (ts_data && ts_data->bus_rx_buf) {
++        kfree(ts_data->bus_rx_buf);
++        ts_data->bus_rx_buf = NULL;
++    }
++    FTS_FUNC_EXIT();
++    return 0;
++}
+diff --git a/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_point_report_check.c b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_point_report_check.c
+new file mode 100644
+index 000000000..1296af155
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/focaltech_touch/focaltech_point_report_check.c
+@@ -0,0 +1,135 @@
++/*
++ *
++ * FocalTech TouchScreen driver.
++ *
++ * Copyright (c) 2012-2019, FocalTech Systems, Ltd., all rights reserved.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++/*****************************************************************************
++*
++* File Name: focaltech_point_report_check.c
++*
++* Author: Focaltech Driver Team
++*
++* Created: 2016-11-16
++*
++* Abstract: point report check function
++*
++* Version: v1.0
++*
++* Revision History:
++*
++*****************************************************************************/
++
++/*****************************************************************************
++* Included header files
++*****************************************************************************/
++#include "focaltech_core.h"
++
++#if FTS_POINT_REPORT_CHECK_EN
++/*****************************************************************************
++* Private constant and macro definitions using #define
++*****************************************************************************/
++#define POINT_REPORT_CHECK_WAIT_TIME              200    /* unit:ms */
++
++/*****************************************************************************
++* functions body
++*****************************************************************************/
++/*****************************************************************************
++*  Name: fts_prc_func
++*  Brief: fts point report check work func, report whole up of points
++*  Input:
++*  Output:
++*  Return:
++*****************************************************************************/
++static void fts_prc_func(struct work_struct *work)
++{
++    struct fts_ts_data *ts_data = container_of(work,
++                                  struct fts_ts_data, prc_work.work);
++    struct input_dev *input_dev = ts_data->input_dev;
++#if FTS_MT_PROTOCOL_B_EN
++    u32 finger_count = 0;
++    u32 max_touches = fts_data->pdata->max_touch_number;
++#endif
++
++    FTS_FUNC_ENTER();
++    mutex_lock(&ts_data->report_mutex);
++
++#if FTS_MT_PROTOCOL_B_EN
++    for (finger_count = 0; finger_count < max_touches; finger_count++) {
++        input_mt_slot(input_dev, finger_count);
++        input_mt_report_slot_state(input_dev, MT_TOOL_FINGER, false);
++    }
++#else
++    input_mt_sync(input_dev);
++#endif
++    input_report_key(input_dev, BTN_TOUCH, 0);
++    input_sync(input_dev);
++
++    mutex_unlock(&ts_data->report_mutex);
++
++    FTS_FUNC_EXIT();
++}
++
++/*****************************************************************************
++*  Name: fts_prc_queue_work
++*  Brief: fts point report check queue work, call it when interrupt comes
++*  Input:
++*  Output:
++*  Return:
++*****************************************************************************/
++void fts_prc_queue_work(struct fts_ts_data *ts_data)
++{
++    cancel_delayed_work_sync(&ts_data->prc_work);
++    queue_delayed_work(ts_data->ts_workqueue, &ts_data->prc_work,
++                       msecs_to_jiffies(POINT_REPORT_CHECK_WAIT_TIME));
++}
++
++/*****************************************************************************
++*  Name: fts_point_report_check_init
++*  Brief:
++*  Input:
++*  Output:
++*  Return: < 0: Fail to create esd check queue
++*****************************************************************************/
++int fts_point_report_check_init(struct fts_ts_data *ts_data)
++{
++    FTS_FUNC_ENTER();
++
++    if (ts_data->ts_workqueue) {
++        INIT_DELAYED_WORK(&ts_data->prc_work, fts_prc_func);
++    } else {
++        FTS_ERROR("fts workqueue is NULL, can't run point report check function");
++        return -EINVAL;
++    }
++
++    FTS_FUNC_EXIT();
++    return 0;
++}
++
++/*****************************************************************************
++*  Name: fts_point_report_check_exit
++*  Brief:
++*  Input:
++*  Output:
++*  Return:
++*****************************************************************************/
++int fts_point_report_check_exit(struct fts_ts_data *ts_data)
++{
++    FTS_FUNC_ENTER();
++
++    FTS_FUNC_EXIT();
++    return 0;
++}
++#endif /* FTS_POINT_REPORT_CHECK_EN */
++
+diff --git a/module_drivers/drivers/input/touchscreen/ft6236_touch/Kconfig b/module_drivers/drivers/input/touchscreen/ft6236_touch/Kconfig
+new file mode 100644
+index 000000000..80ce09e7f
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/ft6236_touch/Kconfig
+@@ -0,0 +1,10 @@
++#
++# Focaltech Touchscreen driver configuration
++#
++
++config TOUCHSCREEN_FT6236
++    bool "FT6236 Touchscreen"
++    default n
++    help
++      Say Y here if you have Focaltech touch panel.
++      If unsure, say N.
+diff --git a/module_drivers/drivers/input/touchscreen/ft6236_touch/Makefile b/module_drivers/drivers/input/touchscreen/ft6236_touch/Makefile
+new file mode 100644
+index 000000000..2bb05d5fd
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/ft6236_touch/Makefile
+@@ -0,0 +1,6 @@
++# Makefile for the focaltech touchscreen drivers.
++#EXTRA_CFLAGS  +=-Wno-error=date-time
++# EXTRA_CFLAGS  += -Wno-date-time
++obj-$(CONFIG_TOUCHSCREEN_FT6236)	+=  ft6236_touch.o
++# obj-$(CONFIG_TOUCHSCREEN_GT9XX)	+=  gt9xx_update.o
++# obj-$(CONFIG_TOUCHSCREEN_GT9XX)	+=  goodix_tool.o
+diff --git a/module_drivers/drivers/input/touchscreen/ft6236_touch/ft6236_touch.c b/module_drivers/drivers/input/touchscreen/ft6236_touch/ft6236_touch.c
+new file mode 100644
+index 000000000..8960d23fa
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/ft6236_touch/ft6236_touch.c
+@@ -0,0 +1,592 @@
++#include <linux/init.h>
++#include <linux/i2c.h>
++#include <linux/input.h>
++#include <linux/gpio.h>
++#include <linux/irq.h>
++#include <linux/module.h>
++#include <linux/string.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/input/mt.h>
++#include <linux/of_gpio.h>
++#include <linux/platform_device.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/kernel.h>
++#include <linux/regulator/consumer.h>
++
++#include "ft6236_touch.h"
++
++static const struct i2c_device_id ft6236_tpd_id[] = {{TPD_DRIVER_NAME,0},{}};
++
++static int ft_parse_dt(struct device *dev,
++			struct ft6236_platform_data *pdata)
++{
++	int ret;
++	struct device_node *np = dev->of_node;
++
++	ret = of_property_read_u32(np, "irq-flags",
++				   &pdata->irq_flags);
++	if (ret) {
++		dev_info(dev,
++			 "Failed get int-trigger-type from dts,set default\n");
++	}
++
++	ret = of_property_read_u32(np, "touchscreen-max-x",
++				   &pdata->max_x);
++	if (ret) {
++		dev_info(dev,
++			 "Failed get max_x from dts,set default\n");
++	}
++
++	ret = of_property_read_u32(np, "touchscreen-max-y",
++				   &pdata->max_y);
++	if (ret) {
++		dev_info(dev,
++			 "Failed get max_y from dts,set default\n");
++	}
++
++	ret = of_property_read_u32(np, "touchscreen-invert-x",
++				   &pdata->invert_x);
++	if (ret) {
++		dev_info(dev,
++			 "Failed get invert_x from dts,set default\n");
++	}
++
++	ret = of_property_read_u32(np, "touchscreen-invert-y",
++				   &pdata->invert_y);
++	if (ret) {
++		dev_info(dev,
++			 "Failed get invert_y from dts,set default\n");
++	}
++
++	of_property_read_u32(np, "ft6236,swap-xy", &pdata->swap_xy);
++	if (pdata->swap_xy)
++		dev_info(dev, "swap-xy enabled\n");
++
++	pdata->irq_gpio = of_get_named_gpio(np, "irq-gpios", 0);
++	if (!gpio_is_valid(pdata->irq_gpio))
++		dev_err(dev, "No valid irq gpio");
++
++	pdata->rst_gpio = of_get_named_gpio(np, "reset-gpios", 0);
++	if (!gpio_is_valid(pdata->rst_gpio))
++		dev_err(dev, "No valid rst gpio");
++
++	return 0;
++}
++
++static int ft_power_init(struct ft6236_data *ts)
++{
++	int ret;
++
++	ts->vdd_ana = regulator_get(&ts->client->dev, "vdd_ana");
++	if (IS_ERR(ts->vdd_ana)) {
++		ts->vdd_ana = NULL;
++		ret = PTR_ERR(ts->vdd_ana);
++		dev_info(&ts->client->dev,
++			 "Regulator get failed vdd ret=%d\n", ret);
++	}
++
++	ts->vcc_i2c = regulator_get(&ts->client->dev, "vcc_i2c");
++	if (IS_ERR(ts->vcc_i2c)) {
++		ts->vcc_i2c = NULL;
++		ret = PTR_ERR(ts->vcc_i2c);
++		dev_info(&ts->client->dev,
++			 "Regulator get failed vcc_i2c ret=%d\n", ret);
++	}
++	return 0;
++}
++
++static int ft_power_deinit(struct ft6236_data *ts)
++{
++	if (ts->vdd_ana)
++		regulator_put(ts->vdd_ana);
++	if (ts->vcc_i2c)
++		regulator_put(ts->vcc_i2c);
++
++	return 0;
++}
++
++static int ft_power_on(struct ft6236_data *ts)
++{
++	int ret = 0;
++
++	if (ts->vdd_ana) {
++		ret = regulator_enable(ts->vdd_ana);
++		if (ret) {
++			dev_err(&ts->client->dev,
++				"Regulator vdd enable failed ret=%d\n",
++				ret);
++			goto err_enable_vdd_ana;
++		}
++	}
++
++	if (ts->vcc_i2c) {
++		ret = regulator_enable(ts->vcc_i2c);
++		if (ret) {
++			dev_err(&ts->client->dev,
++				"Regulator vcc_i2c enable failed ret=%d\n",
++				ret);
++			goto err_enable_vcc_i2c;
++		}
++	}
++	clear_bit(6, &ts->flags);
++	return 0;
++
++err_enable_vcc_i2c:
++	if (ts->vdd_ana)
++		regulator_disable(ts->vdd_ana);
++err_enable_vdd_ana:
++	set_bit(6, &ts->flags);
++	return ret;
++}
++
++static int ft6236_chip_power(struct ft6236_data *ft6236)
++{
++	int ret = 0;
++
++	if (NULL != ft6236->vdd_ana){
++		ret = regulator_enable(ft6236->vdd_ana);
++		if(ret){
++			dev_err(&ft6236->client->dev,
++				"Regulator vdd enable failed ret=%d\n",
++				ret);
++			goto err_enable_vdd_ana;
++		}
++	}
++	if (NULL != ft6236->vcc_i2c) {
++		ret = regulator_enable(ft6236->vcc_i2c);
++		if (ret) {
++			dev_err(&ft6236->client->dev,
++				"Regulator vcc_i2c enable failed ret=%d\n",
++				ret);
++			goto err_enable_vcc_i2c;
++		}
++	}
++
++	return 0;
++
++err_enable_vcc_i2c:
++	if (ft6236->vdd_ana)
++		regulator_disable(ft6236->vdd_ana);
++err_enable_vdd_ana:
++/*	set_bit(POWER_OFF_MODE, &ft6236->flags);*/
++	return ret;
++}
++
++static void ft6236_chip_reset(struct ft6236_data *ft6236)
++{
++	if (ft6236->pdata->rst_gpio) {
++		gpio_direction_output(ft6236->pdata->rst_gpio, 0);
++		msleep(50);
++		gpio_direction_output(ft6236->pdata->rst_gpio, 1);
++		msleep(300);
++	}
++}
++
++
++static int ft6236_read(struct i2c_client *client, u8 address, u8 len, u8 *buf)
++{
++	unsigned int transfer_length = 0;
++	unsigned int pos = 0;
++	unsigned char get_buf[64], addr_buf[2];
++	int retry, r = 2;
++	struct i2c_msg msgs[] = {
++		{
++			.addr = client->addr,
++			.flags = !I2C_M_RD,
++			.buf = &addr_buf[0],
++			.len = 1,
++		}, {
++			.addr = client->addr,
++			.flags = I2C_M_RD,
++		}
++	};
++
++	if (likely(len < sizeof(get_buf))) {
++		/* code optimize, use stack memory */
++		msgs[1].buf = &get_buf[0];
++	} else {
++		msgs[1].buf = kzalloc(len > I2C_MAX_TRANSFER_SIZE
++				? I2C_MAX_TRANSFER_SIZE : len, GFP_KERNEL);
++		if (!msgs[1].buf)
++			return -ENOMEM;
++	}
++
++	while (pos != len) {
++		if (unlikely(len - pos > I2C_MAX_TRANSFER_SIZE))
++			transfer_length = I2C_MAX_TRANSFER_SIZE;
++		else
++			transfer_length = len - pos;
++		msgs[0].buf[0] = address;
++		msgs[1].len = transfer_length;
++		for (retry = 0; retry < RETRY_MAX_TIMES; retry++) {
++			if (likely(i2c_transfer(client->adapter, msgs, 2) == 2)) {
++				memcpy(&buf[pos], msgs[1].buf, transfer_length);
++				pos += transfer_length;
++				address += transfer_length;
++				break;
++			}
++			dev_dbg(&client->dev, "I2c read retry[%d]:0x%x\n",
++				retry + 1, address);
++			usleep_range(2000, 2100);
++		}
++		if (unlikely(retry == RETRY_MAX_TIMES)) {
++			dev_err(&client->dev,
++				"I2c read failed,dev:%02x,reg:%04x,size:%u\n",
++				client->addr, address, len);
++			r = -EAGAIN;
++			goto read_exit;
++		}
++	}
++read_exit:
++	if (len >= sizeof(get_buf))
++		kfree(msgs[1].buf);
++
++	return r;
++}
++
++static int ft6236_i2c_test(struct i2c_client *client)
++{
++	u8 test;
++
++	ft6236_read(client, 0xa8, 1, &test);
++	if (0x11 == test)
++		return 0;
++
++	return -EAGAIN;
++}
++static int ft_request_io_port(struct ft6236_data *ts)
++{
++	int ret;
++
++	if (gpio_is_valid(ts->pdata->irq_gpio)) {
++		ret = gpio_request(ts->pdata->irq_gpio, "ft6236_ts_int");
++		if (ret < 0) {
++			dev_err(&ts->client->dev,
++				"Failed to request GPIO:%d, ERRNO:%d\n",
++				(s32)ts->pdata->irq_gpio, ret);
++			return -ENODEV;
++		}
++		gpio_direction_input(ts->pdata->irq_gpio);
++		dev_info(&ts->client->dev, "Success request irq-gpio\n");
++	}
++	if (gpio_is_valid(ts->pdata->rst_gpio)) {
++		ret = gpio_request(ts->pdata->rst_gpio, "ft6236_ts_rst");
++		if (ret < 0) {
++			dev_err(&ts->client->dev,
++				"Failed to request GPIO:%d, ERRNO:%d\n",
++				(s32)ts->pdata->rst_gpio, ret);
++
++			if (gpio_is_valid(ts->pdata->irq_gpio))
++				gpio_free(ts->pdata->irq_gpio);
++
++			return -ENODEV;
++		}
++
++		gpio_direction_input(ts->pdata->rst_gpio);
++		dev_info(&ts->client->dev,  "Success request rst-gpio\n");
++	}
++	return 0;
++}
++
++static void ft6236_touch_report(struct ft6236_data *ft6236)
++{
++	u8 touches;
++	int i, error;
++	struct ft6236_packet buf;
++
++	struct input_dev *input = ft6236->input;
++
++	error = ft6236_read(ft6236->client, 0, sizeof(buf), (u8 *)&buf);
++	if (error < 0) {
++		printk(KERN_ERR "ft6236_touch: read touchdata failed %d\n", error);
++		return;
++	}
++
++	touches = buf.touches & 0xf;
++
++	for (i = 0; i < touches; i++) {
++		struct ft6236_touchpoint *point = &buf.points[i];
++		u16 x = ((point->xhi & 0xf) << 8) | buf.points[i].xlo;
++		u16 y = ((point->yhi & 0xf) << 8) | buf.points[i].ylo;
++		u8 id = point->id >> 4;
++
++		if (ft6236->pdata->invert_x)
++			x = ft6236->pdata->max_x - x;
++
++		if (ft6236->pdata->invert_y)
++			y = ft6236->pdata->max_y - y;
++
++		input_report_key(input, BTN_TOUCH, 1);
++		input_report_abs(input, ABS_MT_TOOL_TYPE, 1);
++		input_report_abs(input, ABS_MT_TRACKING_ID, id);
++		input_report_abs(input, ABS_MT_PRESSURE, 20);
++		input_report_abs(input, ABS_MT_TOUCH_MAJOR, 20);
++		input_report_abs(input, ABS_MT_WIDTH_MAJOR, 20);
++
++		input_report_key(input, BTN_TOOL_FINGER, true);
++
++		if (ft6236->pdata->swap_xy) {
++			input_report_abs(input, ABS_MT_POSITION_X, y);
++			input_report_abs(input, ABS_MT_POSITION_Y, x);
++		} else {
++			input_report_abs(input, ABS_MT_POSITION_X, x);
++			input_report_abs(input, ABS_MT_POSITION_Y, y);
++		}
++
++		input_mt_sync(input);
++	}
++
++	if (touches == 0) {
++		input_report_key(input, BTN_TOUCH, 0);
++		input_mt_sync(input);
++	}
++
++	input_sync(input);
++}
++
++static irqreturn_t ft6236_ts_irq_handler(int irq, void *dev_id)
++{
++	struct ft6236_data *ft6236 = dev_id;
++
++	ft6236_touch_report(ft6236);
++
++	return IRQ_HANDLED;
++}
++
++static int ft_request_irq(struct ft6236_data *ts)
++{
++	int ret = -1;
++
++	if (gpio_is_valid(ts->pdata->irq_gpio))
++		ts->client->irq = gpio_to_irq(ts->pdata->irq_gpio);
++
++	dev_info(&ts->client->dev, "INT num %d, trigger type:%d\n",
++		 ts->client->irq, ts->pdata->irq_flags);
++	ret = request_threaded_irq(ts->client->irq, NULL,
++			ft6236_ts_irq_handler,
++			ts->pdata->irq_flags | IRQF_ONESHOT,
++			ts->client->name,
++			ts);
++	if (ret < 0) {
++		dev_err(&ts->client->dev,
++			"Failed to request irq %d\n", ts->client->irq);
++		return ret;
++	}
++	return ret;
++}
++
++static int ft6236_tpd_probe(struct i2c_client *client, const struct i2c_device_id *id)
++{
++	int ret;
++	struct input_dev *input;
++	struct device *dev = &client->dev;
++	struct ft6236_platform_data *pdata;
++	struct ft6236_data *ft6236;
++
++	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
++		dev_err(&client->dev, "Failed check I2C functionality");
++		return -ENODEV;
++	}
++
++	ft6236 = devm_kzalloc(&client->dev, sizeof(*ft6236), GFP_KERNEL);
++	if (ft6236 == NULL) {
++		printk(KERN_ERR "ft6236_touch: alloc ft6236 memory failed.");
++		return -ENOMEM;
++	}
++
++	pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
++	if (ft6236 == NULL) {
++		printk(KERN_ERR "ft6236_touch: alloc ft6236_platform_data memory failed.");
++		devm_kfree(&client->dev, ft6236);
++		return -EINVAL;
++	}
++
++	ret = ft_parse_dt(&client->dev, pdata);
++	if (ret) {
++		dev_err(&client->dev, "Failed parse dts\n");
++		goto exit_free_client_data;
++	}
++
++	ft6236->client = client;
++	ft6236->pdata = pdata;
++
++	ret = ft_request_io_port(ft6236);
++	if (ret < 0) {
++		dev_err(&client->dev, "Failed request IO port\n");
++		goto free_gpio;
++	}
++
++	ret = ft_power_init(ft6236);
++	if (ret) {
++		dev_err(&client->dev, "Failed get regulator\n");
++		ret = -EINVAL;
++		goto free_gpio;
++	}
++
++	i2c_set_clientdata(client, ft6236);
++	ft6236_chip_power(ft6236);
++	ft6236_chip_reset(ft6236);
++
++	input = devm_input_allocate_device(dev);
++	if (input == NULL) {
++		ret = -ENOMEM;
++		goto exit_deinit_power;
++	}
++
++	ft6236->input = input;
++	input->name = TPD_DRIVER_NAME;
++	input->phys = TPD_DRIVER_PHY;
++	input->id.bustype = BUS_I2C;
++
++	__set_bit(EV_SYN, input->evbit);
++	__set_bit(EV_KEY, input->evbit);
++	__set_bit(EV_ABS, input->evbit);
++	__set_bit(BTN_TOUCH, input->keybit);
++	__set_bit(INPUT_PROP_DIRECT, input->propbit);
++
++	if (ft6236->pdata->swap_xy) {
++		input_set_abs_params(input, ABS_MT_POSITION_X, 0, pdata->max_y, 0, 0);
++		input_set_abs_params(input, ABS_MT_POSITION_Y, 0, pdata->max_x, 0, 0);
++	} else {
++		input_set_abs_params(input, ABS_MT_POSITION_X, 0, pdata->max_x, 0, 0);
++		input_set_abs_params(input, ABS_MT_POSITION_Y, 0, pdata->max_y, 0, 0);
++	}
++
++	input_set_abs_params(input, ABS_MT_WIDTH_MAJOR, 0, 255, 0, 0);
++	input_set_abs_params(input, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0);
++	input_set_abs_params(input, ABS_MT_TRACKING_ID, 0, 255, 0, 0);
++
++	input_set_abs_params(input, ABS_MT_TOOL_TYPE, 0, MT_TOOL_MAX, 0, 0);
++	input_set_abs_params(input, ABS_MT_PRESSURE, 0, 479, 0, 0);
++
++	ret = ft_request_irq(ft6236);
++	if (ret < 0) {
++		dev_err(&client->dev, "Failed create work thread");
++		goto free_input;
++	}
++
++	ret = input_register_device(input);
++	if (ret) {
++		printk(KERN_ERR "ft6236_touch: failed to register input device: %d\n", ret);
++		goto free_irq;
++	}
++
++	spin_lock_init(&ft6236->irq_lock);
++
++	ret = ft6236_i2c_test(client);
++	if (ret) {
++		dev_err(&client->dev, "Failed communicate with IC use I2C\n");
++		goto free_input_dev;
++	}
++
++	return 0;
++
++free_input_dev:
++	input_unregister_device(ft6236->input);
++free_irq:
++	free_irq(ft6236->client->irq, ft6236);
++free_input:
++	input_free_device(ft6236->input);
++exit_deinit_power:
++	ft_power_deinit(ft6236);
++free_gpio:
++	if (gpio_is_valid(ft6236->pdata->rst_gpio))
++		gpio_free(ft6236->pdata->rst_gpio);
++	if (gpio_is_valid(ft6236->pdata->irq_gpio))
++		gpio_free(ft6236->pdata->irq_gpio);
++exit_free_client_data:
++	devm_kfree(&client->dev, pdata);
++	devm_kfree(&client->dev, ft6236);
++	i2c_set_clientdata(client, NULL);
++
++	return ret;
++}
++
++static int ft6236_tpd_remove(struct i2c_client *client)
++{
++	struct ft6236_data *ft6236 = i2c_get_clientdata(client);
++
++	free_irq(ft6236->client->irq, ft6236);
++
++	if (gpio_is_valid(ft6236->pdata->rst_gpio))
++		gpio_free(ft6236->pdata->rst_gpio);
++	if (gpio_is_valid(ft6236->pdata->irq_gpio))
++		gpio_free(ft6236->pdata->irq_gpio);
++
++	input_unregister_device(ft6236->input);
++	input_free_device(ft6236->input);
++	kfree(ft6236);
++
++	return 0;
++}
++
++static int ft6236_tpd_suspend(struct device *device)
++{
++	struct i2c_client *client = to_i2c_client(device);
++	struct ft6236_data *ft6236 = i2c_get_clientdata(client);
++    unsigned long irqflags;
++
++    spin_lock_irqsave(&ft6236->irq_lock, irqflags);
++    disable_irq(client->irq);
++    spin_unlock_irqrestore(&ft6236->irq_lock, irqflags);
++	return 0;
++}
++
++static int ft6236_tpd_resume(struct device *device)
++{
++	struct i2c_client *client = to_i2c_client(device);
++	struct ft6236_data *ft6236 = i2c_get_clientdata(client);
++    unsigned long irqflags;
++
++    spin_lock_irqsave(&ft6236->irq_lock, irqflags);
++    enable_irq(client->irq);
++    spin_unlock_irqrestore(&ft6236->irq_lock, irqflags);
++	return 0;
++}
++
++static const struct dev_pm_ops ft6236_pm_ops = {
++	.suspend = ft6236_tpd_suspend,
++	.resume  = ft6236_tpd_resume,
++};
++
++static const struct of_device_id ft_match_table[] = {
++	{.compatible = "goodix,ft6236",},
++	{ },
++};
++
++static struct i2c_driver ft6236_ts_driver = {
++	.driver = {
++		.name = TPD_DRIVER_NAME,
++		.owner    = THIS_MODULE,
++		.of_match_table = ft_match_table,
++		.pm = &ft6236_pm_ops,
++	},
++
++	.probe    = ft6236_tpd_probe,
++	.remove   = ft6236_tpd_remove,
++	.id_table = ft6236_tpd_id,
++};
++
++static int __init ft6236_touch_init(void)
++{
++	int ret = i2c_add_driver(&ft6236_ts_driver);
++	if (ret) {
++		printk(KERN_ERR "ft6236_touch: failed to register i2c driver\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static void __exit ft6236_touch_exit(void)
++{
++	i2c_del_driver(&ft6236_ts_driver);
++}
++
++module_init(ft6236_touch_init);
++module_exit(ft6236_touch_exit);
++
++MODULE_DESCRIPTION("Ft6236 Series Driver");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/input/touchscreen/ft6236_touch/ft6236_touch.h b/module_drivers/drivers/input/touchscreen/ft6236_touch/ft6236_touch.h
+new file mode 100644
+index 000000000..fd090df00
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/ft6236_touch/ft6236_touch.h
+@@ -0,0 +1,52 @@
++#ifndef __TOUCH_FT6236_H_
++#define __TOUCH_FT6236_H_
++
++#define I2C_ADDR                    0x38
++#define I2C_MAX_TRANSFER_SIZE		255
++#define RETRY_MAX_TIMES			5
++#define TPD_DRIVER_NAME     "ft6236-ts"
++#define TPD_DRIVER_PHY     "input/ts"
++
++struct ft6236_platform_data {
++	int irq_gpio;
++	int rst_gpio;
++	u32 irq_flags;
++	u32 max_x;
++	u32 max_y;
++	u32 invert_x;
++	u32 invert_y;
++	u32 swap_xy;
++};
++
++struct ft6236_data {
++	unsigned long flags; /* This member record the device status */
++	struct i2c_client *client;
++	struct input_dev *input;
++	struct ft6236_platform_data *pdata;
++	struct mutex lock;
++	struct regulator *vdd_ana;
++	struct regulator *vcc_i2c;
++	spinlock_t irq_lock;
++};
++
++struct ft6236_touchpoint {
++	union {
++		u8 xhi;
++		u8 event;
++	};
++	u8 xlo;
++	union {
++		u8 yhi;
++		u8 id;
++	};
++	u8 ylo;
++};
++
++struct ft6236_packet {
++	u8 dev_mode;
++	u8 gest_id;
++	u8 touches;
++	struct ft6236_touchpoint points[2];
++};
++
++#endif //__TOUCH_FT6236_h_
+diff --git a/module_drivers/drivers/input/touchscreen/gt9xx_touch/Kconfig b/module_drivers/drivers/input/touchscreen/gt9xx_touch/Kconfig
+new file mode 100644
+index 000000000..f857fea85
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/gt9xx_touch/Kconfig
+@@ -0,0 +1,16 @@
++#
++# Focaltech Touchscreen driver configuration
++#
++
++config TOUCHSCREEN_GT9XX
++    bool "GT9XX Touchscreen"
++    default n
++    help
++      Say Y here if you have Focaltech touch panel.
++      If unsure, say N.
++
++config TOUCHSCREEN_GT9XX_DIRECTORY
++    string "gt ts directory name"
++    default "gt9xx_touch"
++    depends on TOUCHSCREEN_GT9XX
++
+diff --git a/module_drivers/drivers/input/touchscreen/gt9xx_touch/Makefile b/module_drivers/drivers/input/touchscreen/gt9xx_touch/Makefile
+new file mode 100644
+index 000000000..2da8bc005
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/gt9xx_touch/Makefile
+@@ -0,0 +1,6 @@
++# Makefile for the focaltech touchscreen drivers.
++#EXTRA_CFLAGS  +=-Wno-error=date-time
++EXTRA_CFLAGS  += -Wno-date-time
++obj-$(CONFIG_TOUCHSCREEN_GT9XX)	+=  gt9xx.o
++obj-$(CONFIG_TOUCHSCREEN_GT9XX)	+=  gt9xx_update.o
++obj-$(CONFIG_TOUCHSCREEN_GT9XX)	+=  goodix_tool.o
+diff --git a/module_drivers/drivers/input/touchscreen/gt9xx_touch/goodix.h b/module_drivers/drivers/input/touchscreen/gt9xx_touch/goodix.h
+new file mode 100644
+index 000000000..b7c6f2e6e
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/gt9xx_touch/goodix.h
+@@ -0,0 +1,69 @@
++#ifndef TOUCHSCREEN_GT9XX__H
++#define TOUCHSCREEN_GT9XX__H
++
++/*****************************************************************************
++* Included header files
++*****************************************************************************/
++#include <linux/kernel.h>
++#include <linux/device.h>
++#include <linux/i2c.h>
++#include <linux/spi/spi.h>
++#include <linux/input.h>
++#include <linux/input/mt.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/vmalloc.h>
++#include <linux/gpio.h>
++#include <linux/regulator/consumer.h>
++#include <asm/uaccess.h>
++#include <linux/firmware.h>
++#include <linux/debugfs.h>
++#include <linux/mutex.h>
++#include <linux/workqueue.h>
++#include <linux/wait.h>
++#include <linux/time.h>
++#include <linux/jiffies.h>
++#include <linux/fs.h>
++#include <linux/proc_fs.h>
++#include <linux/version.h>
++#include <linux/types.h>
++#include <linux/sched.h>
++#include <linux/kthread.h>
++#include <linux/dma-mapping.h>
++
++/*****************************************************************************
++* Debug interface.
++*****************************************************************************/
++
++#if GT9_DEBUG_EN
++
++#define GT9_DEBUG(fmt, args...) do { \
++    printk("[GT9_TS]%s:"fmt"\n", __func__, ##args); \
++} while (0)
++
++#define GT9_FUNC_ENTER() do { \
++    printk("[GT9_TS]%s: Enter(%d)\n", __func__,__LINE__); \
++} while (0)
++
++#define GT9_FUNC_EXIT() do { \
++    printk("[GT9_TS]%s: Exit(%d)\n", __func__, __LINE__); \
++} while (0)
++#else /* #if GT9_DEBUG_EN*/
++#define GT9_DEBUG(fmt, args...)
++#define GT9_FUNC_ENTER()
++#define GT9_FUNC_EXIT()
++#endif
++
++#define GT9_INFO(fmt, args...) do { \
++    printk(KERN_INFO "[GT9_TS/I]%s:"fmt"\n", __func__, ##args); \
++} while (0)
++
++#define GT9_ERROR(fmt, args...) do { \
++    printk(KERN_ERR "[GT9_TS/E]%s:"fmt"\n", __func__, ##args); \
++} while (0)
++
++#endif /* TOUCHSCREEN_CST3XX__H  */
++
++
+diff --git a/module_drivers/drivers/input/touchscreen/gt9xx_touch/goodix_tool.c b/module_drivers/drivers/input/touchscreen/gt9xx_touch/goodix_tool.c
+new file mode 100644
+index 000000000..a1828f972
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/gt9xx_touch/goodix_tool.c
+@@ -0,0 +1,529 @@
++/*
++ * Goodix GT9xx touchscreen driver
++ *
++ * Copyright  (C)  2016 - 2017 Goodix. Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be a reference
++ * to you, when you are integrating the GOODiX's CTP IC into your system,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * Version: 2.8.0.1
++ * Release Date: 2017/11/24
++ */
++
++#include "gt9xx.h"
++
++#define DATA_LENGTH_UINT	512
++#define CMD_HEAD_LENGTH		(sizeof(struct st_cmd_head) - sizeof(u8 *))
++static char procname[20] = {0};
++
++#pragma pack(1)
++struct st_cmd_head {
++	u8	wr;		/*write read flag 0:R 1:W 2:PID 3:*/
++	u8	flag;		/*0:no need flag/int 1: need flag 2:need int*/
++	u8	flag_addr[2];	/*flag address*/
++	u8	flag_val;	/*flag val*/
++	u8	flag_relation;	/*flag_val:flag 0:not equal 1:equal 2:> 3:<*/
++	u16	circle;		/*polling cycle*/
++	u8	times;		/*plling times*/
++	u8	retry;		/*I2C retry times*/
++	u16	delay;		/*delay before read or after write*/
++	u16	data_len;	/*data length*/
++	u8	addr_len;	/*address length*/
++	u8	addr[2];	/*address*/
++	u8	res[3];		/*reserved*/
++	u8	*data; };	/*data pointer*/
++#pragma pack()
++struct st_cmd_head cmd_head;
++
++static struct i2c_client *gt_client;
++static struct proc_dir_entry *goodix_proc_entry;
++
++static ssize_t goodix_tool_read(struct file *, char __user *, size_t, loff_t *);
++static ssize_t goodix_tool_write(struct file *, const char __user *, size_t, loff_t *);
++static const struct proc_ops gtp_proc_ops = {
++	.proc_read = goodix_tool_read,
++	.proc_write = goodix_tool_write,
++};
++
++/* static s32 goodix_tool_write(struct file *filp,
++ * const char __user *buff, unsigned long len, void *data);
++ */
++/*static s32 goodix_tool_read( char *page, char
++ **start, off_t off, int count, int *eof, void *data );
++ */
++static s32 (*tool_i2c_read)(u8 *, u16);
++static s32 (*tool_i2c_write)(u8 *, u16);
++
++static s32 DATA_LENGTH = (s32)0;
++static s8 IC_TYPE[16] = "GT9XX";
++
++static void tool_set_proc_name(char *procname)
++{
++	snprintf(procname, 20, "gmnode"); /* modify for moto */
++}
++
++static s32 tool_i2c_read_no_extra(u8 *buf, u16 len)
++{
++	s32 ret = -1;
++	s32 i = 0;
++	struct goodix_ts_data *ts = i2c_get_clientdata(i2c_connect_client);
++
++	for (i = 0; i < cmd_head.retry; i++) {
++		ret = gtp_i2c_read(ts->client, buf, len + GTP_ADDR_LENGTH);
++		if (ret > 0)
++			break;
++	}
++	return ret;
++}
++
++static s32 tool_i2c_write_no_extra(u8 *buf, u16 len)
++{
++	s32 ret = -1;
++	s32 i = 0;
++	struct goodix_ts_data *ts = i2c_get_clientdata(i2c_connect_client);
++
++	for (i = 0; i < cmd_head.retry; i++) {
++		ret = gtp_i2c_write(ts->client, buf, len);
++		if (ret > 0)
++			break;
++	}
++
++	return ret;
++}
++
++static s32 tool_i2c_read_with_extra(u8 *buf, u16 len)
++{
++	s32 ret = -1;
++	u8 pre[2] = {0x0f, 0xff};
++	u8 end[2] = {0x80, 0x00};
++
++	tool_i2c_write_no_extra(pre, 2);
++	ret = tool_i2c_read_no_extra(buf, len);
++	tool_i2c_write_no_extra(end, 2);
++
++	return ret;
++}
++
++static s32 tool_i2c_write_with_extra(u8 *buf, u16 len)
++{
++	s32 ret = -1;
++	u8 pre[2] = {0x0f, 0xff};
++	u8 end[2] = {0x80, 0x00};
++
++	tool_i2c_write_no_extra(pre, 2);
++	ret = tool_i2c_write_no_extra(buf, len);
++	tool_i2c_write_no_extra(end, 2);
++
++	return ret;
++}
++
++static void register_i2c_func(void)
++{
++	/* if (!strncmp(IC_TYPE, "GT818", 5)
++	 *  || !strncmp(IC_TYPE, "GT816", 5)
++	 *  || !strncmp(IC_TYPE, "GT811", 5)
++	 *  || !strncmp(IC_TYPE, "GT818F", 6)
++	 *  || !strncmp(IC_TYPE, "GT827", 5)
++	 *  || !strncmp(IC_TYPE,"GT828", 5)
++	 *  || !strncmp(IC_TYPE, "GT813", 5))
++	 */
++	if (strncmp(IC_TYPE, "GT8110", 6) &&
++	    strncmp(IC_TYPE, "GT8105", 6) &&
++	    strncmp(IC_TYPE, "GT801", 5) &&
++	    strncmp(IC_TYPE, "GT800", 5) &&
++	    strncmp(IC_TYPE, "GT801PLUS", 9) &&
++	    strncmp(IC_TYPE, "GT811", 5) &&
++	    strncmp(IC_TYPE, "GTxxx", 5) &&
++	    strncmp(IC_TYPE, "GT9XX", 5)) {
++		tool_i2c_read = tool_i2c_read_with_extra;
++		tool_i2c_write = tool_i2c_write_with_extra;
++		dev_dbg(&gt_client->dev, "I2C function: with pre and end cmd!");
++	} else {
++		tool_i2c_read = tool_i2c_read_no_extra;
++		tool_i2c_write = tool_i2c_write_no_extra;
++		dev_info(&gt_client->dev, "I2C function: without pre and end cmd!");
++	}
++}
++
++static void unregister_i2c_func(void)
++{
++	tool_i2c_read = NULL;
++	tool_i2c_write = NULL;
++	dev_info(&gt_client->dev, "I2C function: unregister i2c transfer function!");
++}
++
++s32 init_wr_node(struct i2c_client *client)
++{
++	s32 i;
++
++	gt_client = client;
++	memset(&cmd_head, 0, sizeof(cmd_head));
++	cmd_head.data = NULL;
++
++	i = 6;
++	while ((!cmd_head.data) && i) {
++		cmd_head.data = kzalloc(i * DATA_LENGTH_UINT, GFP_KERNEL);
++		if (cmd_head.data)
++			break;
++		i--;
++	}
++	if (i) {
++		DATA_LENGTH = i * DATA_LENGTH_UINT - GTP_ADDR_LENGTH;
++		dev_info(&gt_client->dev,
++			 "Alloc memory size:%d.", DATA_LENGTH);
++	} else {
++		dev_err(&gt_client->dev, "Apply for memory failed.");
++		return FAIL;
++	}
++
++	cmd_head.addr_len = 2;
++	cmd_head.retry = 5;
++
++	register_i2c_func();
++
++	tool_set_proc_name(procname);
++	goodix_proc_entry = proc_create(procname, 0666, NULL, &gtp_proc_ops);
++	if (!goodix_proc_entry) {
++		dev_err(&gt_client->dev, "Couldn't create proc entry!");
++		return FAIL;
++	}
++
++	dev_info(&gt_client->dev, "Create proc entry success!");
++	return SUCCESS;
++}
++
++void uninit_wr_node(void)
++{
++	kfree(cmd_head.data);
++	cmd_head.data = NULL;
++	unregister_i2c_func();
++	remove_proc_entry(procname, NULL);
++}
++
++static u8 relation(u8 src, u8 dst, u8 rlt)
++{
++	u8 ret = 0;
++
++	switch (rlt) {
++	case 0:
++		ret = (src != dst) ? true : false;
++		break;
++
++	case 1:
++		ret = (src == dst) ? true : false;
++		dev_dbg(&gt_client->dev,
++			"equal:src:0x%02x  dst:0x%02x  ret:%d.",
++			src, dst, (s32)ret);
++		break;
++
++	case 2:
++		ret = (src > dst) ? true : false;
++		break;
++
++	case 3:
++		ret = (src < dst) ? true : false;
++		break;
++
++	case 4:
++		ret = (src & dst) ? true : false;
++		break;
++
++	case 5:
++		ret = (!(src | dst)) ? true : false;
++		break;
++
++	default:
++		ret = false;
++		break;
++	}
++
++	return ret;
++}
++
++/*******************************************************
++ * Function:
++ *	Comfirm function.
++ * Input:
++ *	None.
++ * Output:
++ *	Return write length.
++ ********************************************************/
++static u8 comfirm(void)
++{
++	s32 i = 0;
++	u8 buf[32];
++
++	memcpy(buf, cmd_head.flag_addr, cmd_head.addr_len);
++
++	for (i = 0; i < cmd_head.times; i++) {
++		if (tool_i2c_read(buf, 1) <= 0) {
++			dev_err(&gt_client->dev, "Read flag data failed!");
++			return FAIL;
++		}
++		if (true == relation(buf[GTP_ADDR_LENGTH],
++		 cmd_head.flag_val, cmd_head.flag_relation)) {
++			dev_dbg(&gt_client->dev, "value at flag addr:0x%02x.",
++				buf[GTP_ADDR_LENGTH]);
++			dev_dbg(&gt_client->dev, "flag value:0x%02x.",
++				cmd_head.flag_val);
++			break;
++		}
++
++		msleep(cmd_head.circle);
++	}
++
++	if (i >= cmd_head.times) {
++		dev_err(&gt_client->dev, "Can't get the continue flag!");
++		return FAIL;
++	}
++
++	return SUCCESS;
++}
++
++ssize_t goodix_tool_write(struct file *filp, const char __user *buff,
++			  size_t len, loff_t *off)
++{
++	s32 ret = 0;
++	struct goodix_ts_data *ts = i2c_get_clientdata(gt_client);
++
++	ret = copy_from_user(&cmd_head, buff, CMD_HEAD_LENGTH);
++	if (ret) {
++		dev_err(&gt_client->dev, "copy_from_user failed.");
++		return -EPERM;
++	}
++
++	dev_dbg(&gt_client->dev, "[Operation]wr: %02X", cmd_head.wr);
++	dev_dbg(&gt_client->dev,
++		"[Flag]flag: %02X,addr: %02X%02X,value: %02X,relation: %02X",
++		cmd_head.flag, cmd_head.flag_addr[0],
++		cmd_head.flag_addr[1], cmd_head.flag_val,
++		cmd_head.flag_relation);
++	dev_dbg(&gt_client->dev,
++		"[Retry]circle: %d,times: %d,retry: %d, delay: %d",
++		(s32)cmd_head.circle,
++		(s32)cmd_head.times, (s32)cmd_head.retry,
++		(s32)cmd_head.delay);
++
++	if (1 == cmd_head.wr) {
++		if (cmd_head.data_len > DATA_LENGTH) {
++			dev_err(&gt_client->dev,
++				"Tool write failed data too long");
++			return -EPERM;
++		}
++		ret = copy_from_user(&cmd_head.data[GTP_ADDR_LENGTH],
++				     &buff[CMD_HEAD_LENGTH],
++				     cmd_head.data_len);
++		if (ret) {
++			dev_err(&gt_client->dev, "copy_from_user failed.");
++			return -EPERM;
++		}
++		memcpy(&cmd_head.data[GTP_ADDR_LENGTH - cmd_head.addr_len],
++		       cmd_head.addr, cmd_head.addr_len);
++
++		GTP_DEBUG_ARRAY(cmd_head.data, cmd_head.data_len +
++				cmd_head.addr_len);
++
++		if (1 == cmd_head.flag) {
++			if (FAIL == comfirm()) {
++				dev_err(&gt_client->dev,
++					"[WRITE]Comfirm fail!");
++				return -EPERM;
++			}
++		} else if (2 == cmd_head.flag) {
++			/*Need interrupt!*/
++		}
++		if (tool_i2c_write(&cmd_head.data[GTP_ADDR_LENGTH -
++				   cmd_head.addr_len], cmd_head.data_len +
++				   cmd_head.addr_len) <= 0) {
++			dev_err(&gt_client->dev, "[WRITE]Write data failed!");
++			return -EPERM;
++		}
++
++		GTP_DEBUG_ARRAY(&cmd_head.data[GTP_ADDR_LENGTH -
++				cmd_head.addr_len],
++				cmd_head.data_len + cmd_head.addr_len);
++		if (cmd_head.delay)
++			msleep(cmd_head.delay);
++	} else if (3 == cmd_head.wr) {
++		if (cmd_head.data_len > DATA_LENGTH) {
++			dev_err(&gt_client->dev,
++				"Tool write failed data too long");
++			return -EPERM;
++		}
++		ret = copy_from_user(&cmd_head.data[0], &buff[CMD_HEAD_LENGTH],
++				     cmd_head.data_len);
++		if (ret) {
++			dev_err(&gt_client->dev, "copy_from_user failed.");
++			return -EPERM;
++		}
++		memcpy(IC_TYPE, cmd_head.data, cmd_head.data_len);
++
++		register_i2c_func();
++	} else if (5 == cmd_head.wr) {
++		/*memcpy(IC_TYPE, cmd_head.data, cmd_head.data_len);*/
++	} else if (7 == cmd_head.wr) {/*disable irq!*/
++		gtp_work_control_enable(i2c_get_clientdata(gt_client), false);
++
++		if (ts->pdata->esd_protect)
++			gtp_esd_off(ts);
++	} else if (9 == cmd_head.wr) {/*enable irq!*/
++		gtp_work_control_enable(i2c_get_clientdata(gt_client), true);
++
++		if (ts->pdata->esd_protect)
++			gtp_esd_on(ts);
++	} else if (17 == cmd_head.wr) {
++		if (cmd_head.data_len > DATA_LENGTH) {
++			dev_err(&gt_client->dev,
++				"Tool write failed data too long");
++			return -EPERM;
++		}
++		ret = copy_from_user(&cmd_head.data[GTP_ADDR_LENGTH],
++				     &buff[CMD_HEAD_LENGTH],
++				     cmd_head.data_len);
++		if (ret) {
++			dev_dbg(&gt_client->dev, "copy_from_user failed.");
++			return -EPERM;
++		}
++		if (cmd_head.data[GTP_ADDR_LENGTH]) {
++			dev_info(&gt_client->dev, "gtp enter rawdiff.");
++			set_bit(RAW_DATA_MODE, &ts->flags);
++		} else {
++			clear_bit(RAW_DATA_MODE, &ts->flags);
++			dev_info(&gt_client->dev, "gtp leave rawdiff.");
++		}
++	} else if (19 == cmd_head.wr) {
++		/* add new command: reset guitar */
++		gtp_reset_guitar(gt_client, 20);
++	}
++#ifdef CONFIG_TOUCHSCREEN_GT9XX_UPDATE
++	else if (11 == cmd_head.wr) {/*Enter update mode!*/
++		if (FAIL == gup_enter_update_mode(gt_client))
++			return -EPERM;
++	} else if (13 == cmd_head.wr) {/*Leave update mode!*/
++		gup_leave_update_mode(gt_client);
++	} else if (15 == cmd_head.wr) {/*Update firmware!*/
++		show_len = 0;
++		total_len = 0;
++		if (cmd_head.data_len > DATA_LENGTH) {
++			dev_err(&gt_client->dev,
++				"Tool write failed data too long");
++			return -EPERM;
++		}
++		memset(cmd_head.data, 0, DATA_LENGTH);
++		ret = copy_from_user(cmd_head.data,
++				     &buff[CMD_HEAD_LENGTH],
++				     cmd_head.data_len);
++		if (ret) {
++			dev_dbg(&gt_client->dev, "copy_from_user failed.");
++			return -EPERM;
++		}
++
++		if (FAIL == gup_update_proc((void *)cmd_head.data))
++			return -EPERM;
++	}
++#endif
++
++	return len;
++}
++
++/*******************************************************
++ * Function:
++ *	Goodix tool read function.
++ * Input:
++ *	standard proc read function param.
++ * Output:
++ *	Return read length.
++ ********************************************************/
++ssize_t goodix_tool_read(struct file *file, char __user *page,
++			 size_t size, loff_t *ppos)
++{
++	s32 ret = 0;
++
++	if (*ppos) {
++		/* ADB call again
++		 * dev_dbg(&gt_client->dev, "[HEAD]wr: %d", cmd_head.wr);
++		 * dev_dbg(&gt_client->dev,
++		 * "[PARAM]size: %d, *ppos: %d", size, (int)*ppos);
++		 * dev_dbg(&gt_client->dev,
++		 * "[TOOL_READ]ADB call again, return it.");
++		 */
++		*ppos = 0;
++		return 0;
++	}
++
++	if (cmd_head.wr % 2) {
++		return -EPERM;
++	} else if (!cmd_head.wr) {
++		u16 len, data_len, loc, addr;
++
++		if (1 == cmd_head.flag) {
++			if (FAIL == comfirm()) {
++				dev_err(&gt_client->dev, "[READ]Comfirm fail!");
++				return -EPERM;
++			}
++		} else if (2 == cmd_head.flag) {
++			/*Need interrupt!*/
++		}
++
++		if (cmd_head.delay)
++			msleep(cmd_head.delay);
++
++		data_len = cmd_head.data_len;
++		addr = (cmd_head.addr[0] << 8) + cmd_head.addr[1];
++		loc = 0;
++
++		while (data_len > 0) {
++			len = data_len > DATA_LENGTH ? DATA_LENGTH : data_len;
++			cmd_head.data[0] = (addr >> 8) & 0xFF;
++			cmd_head.data[1] = (addr & 0xFF);
++			if (tool_i2c_read(cmd_head.data, len) <= 0) {
++				dev_err(&gt_client->dev, "[READ]Read data failed!");
++				return -EPERM;
++			}
++			ret = simple_read_from_buffer(&page[loc], size, ppos,
++					&cmd_head.data[GTP_ADDR_LENGTH], len);
++			if (ret < 0)
++				return ret;
++			loc += len;
++			addr += len;
++			data_len -= len;
++		}
++		return cmd_head.data_len;
++	} else if (2 == cmd_head.wr) {
++		ret = simple_read_from_buffer(page, size, ppos,
++					      IC_TYPE, sizeof(IC_TYPE));
++		return ret;
++	}
++#ifdef CONFIG_TOUCHSCREEN_GT9XX_UPDATE
++	else if (4 == cmd_head.wr) {
++		u8 progress_buf[4];
++
++		progress_buf[0] = show_len >> 8;
++		progress_buf[1] = show_len & 0xff;
++		progress_buf[2] = total_len >> 8;
++		progress_buf[3] = total_len & 0xff;
++
++		ret = simple_read_from_buffer(page, size, ppos,
++					      progress_buf, 4);
++		return ret;
++	}
++#endif
++	else if (6 == cmd_head.wr) {
++		/*Read error code!*/
++	} else if (8 == cmd_head.wr) {	/*Read driver version*/
++		ret = simple_read_from_buffer(page, size, ppos,
++					      GTP_DRIVER_VERSION,
++					      strlen(GTP_DRIVER_VERSION));
++		return ret;
++	}
++
++	return -EPERM;
++}
+diff --git a/module_drivers/drivers/input/touchscreen/gt9xx_touch/gt9xx.c b/module_drivers/drivers/input/touchscreen/gt9xx_touch/gt9xx.c
+new file mode 100644
+index 000000000..4c2005e93
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/gt9xx_touch/gt9xx.c
+@@ -0,0 +1,2576 @@
++/*
++ * Goodix GT9xx touchscreen driver
++ *
++ * Copyright  (C)  2016 - 2017 Goodix. Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be a reference
++ * to you, when you are integrating the GOODiX's CTP IC into your system,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * Version: 2.8.0.1
++ * Release Date: 2017/11/24
++ */
++
++#include <linux/irq.h>
++#include <linux/platform_device.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/input/mt.h>
++#include "gt9xx.h"
++
++#define GOODIX_COORDS_ARR_SIZE	4
++#define PROP_NAME_SIZE		24
++#define I2C_MAX_TRANSFER_SIZE   255
++#define GTP_PEN_BUTTON1		BTN_STYLUS
++#define GTP_PEN_BUTTON2		BTN_STYLUS2
++
++static const char *goodix_ts_name = "goodix-ts";
++static const char *goodix_input_phys = "input/ts";
++struct i2c_client *i2c_connect_client;
++static struct proc_dir_entry *gtp_config_proc;
++
++enum doze {
++	DOZE_DISABLED = 0,
++	DOZE_ENABLED = 1,
++	DOZE_WAKEUP = 2,
++};
++
++static enum doze doze_status = DOZE_DISABLED;
++
++static int gtp_i2c_test(struct i2c_client *client);
++static int gtp_enter_doze(struct goodix_ts_data *ts);
++
++static int gtp_unregister_powermanager(struct goodix_ts_data *ts);
++static int gtp_register_powermanager(struct goodix_ts_data *ts);
++
++static int gtp_esd_init(struct goodix_ts_data *ts);
++static void gtp_esd_check_func(struct work_struct *);
++static int gtp_init_ext_watchdog(struct i2c_client *client);
++
++/*
++ * return: 2 - ok, < 0 - i2c transfer error
++ */
++int gtp_i2c_read(struct i2c_client *client, u8 *buf, int len)
++{
++	unsigned int transfer_length = 0;
++	unsigned int pos = 0, address = (buf[0] << 8) + buf[1];
++	unsigned char get_buf[64], addr_buf[2];
++	int retry, r = 2;
++	struct i2c_msg msgs[] = {
++		{
++			.addr = client->addr,
++			.flags = !I2C_M_RD,
++			.buf = &addr_buf[0],
++			.len = GTP_ADDR_LENGTH,
++		}, {
++			.addr = client->addr,
++			.flags = I2C_M_RD,
++		}
++	};
++
++	len -= GTP_ADDR_LENGTH;
++	if (likely(len < sizeof(get_buf))) {
++		/* code optimize, use stack memory */
++		msgs[1].buf = &get_buf[0];
++	} else {
++		msgs[1].buf = kzalloc(len > I2C_MAX_TRANSFER_SIZE
++				? I2C_MAX_TRANSFER_SIZE : len, GFP_KERNEL);
++		if (!msgs[1].buf)
++			return -ENOMEM;
++	}
++
++	while (pos != len) {
++		if (unlikely(len - pos > I2C_MAX_TRANSFER_SIZE))
++			transfer_length = I2C_MAX_TRANSFER_SIZE;
++		else
++			transfer_length = len - pos;
++		msgs[0].buf[0] = (address >> 8) & 0xFF;
++		msgs[0].buf[1] = address & 0xFF;
++		msgs[1].len = transfer_length;
++		for (retry = 0; retry < RETRY_MAX_TIMES; retry++) {
++			if (likely(i2c_transfer(client->adapter, msgs, 2) == 2)) {
++				memcpy(&buf[2 + pos], msgs[1].buf, transfer_length);
++				pos += transfer_length;
++				address += transfer_length;
++				break;
++			}
++			dev_dbg(&client->dev, "I2c read retry[%d]:0x%x\n",
++				retry + 1, address);
++			usleep_range(2000, 2100);
++		}
++		if (unlikely(retry == RETRY_MAX_TIMES)) {
++			dev_err(&client->dev,
++				"I2c read failed,dev:%02x,reg:%04x,size:%u\n",
++				client->addr, address, len);
++			r = -EAGAIN;
++			goto read_exit;
++		}
++	}
++read_exit:
++	if (len >= sizeof(get_buf))
++		kfree(msgs[1].buf);
++	return r;
++}
++
++/*******************************************************
++ * Function:
++ *	Write data to the i2c slave device.
++ * Input:
++ *	client: i2c device.
++ *	buf[0~1]: write start address.
++ *	buf[2~len-1]: data buffer
++ *	len: GTP_ADDR_LENGTH + write bytes count
++ * Output:
++ *	numbers of i2c_msgs to transfer:
++ *		1: succeed, otherwise: failed
++ *********************************************************/
++int gtp_i2c_write(struct i2c_client *client, u8 *buf, int len)
++
++{
++	unsigned int pos = 0, transfer_length = 0;
++	unsigned int address = (buf[0] << 8) + buf[1];
++	unsigned char put_buf[64];
++	int retry, r = 1;
++	struct i2c_msg msg = {
++			.addr = client->addr,
++			.flags = !I2C_M_RD,
++	};
++
++	if (likely(len < sizeof(put_buf))) {
++		/* code optimize,use stack memory*/
++		msg.buf = &put_buf[0];
++	} else {
++		msg.buf = kmalloc(len > I2C_MAX_TRANSFER_SIZE
++				  ? I2C_MAX_TRANSFER_SIZE : len, GFP_KERNEL);
++		if (!msg.buf)
++			return -ENOMEM;
++	}
++
++	len -= GTP_ADDR_LENGTH;
++	while (pos != len) {
++		if (unlikely(len - pos > I2C_MAX_TRANSFER_SIZE - GTP_ADDR_LENGTH))
++			transfer_length = I2C_MAX_TRANSFER_SIZE - GTP_ADDR_LENGTH;
++		else
++			transfer_length = len - pos;
++		msg.buf[0] = (unsigned char)((address >> 8) & 0xFF);
++		msg.buf[1] = (unsigned char)(address & 0xFF);
++		msg.len = transfer_length + 2;
++		memcpy(&msg.buf[2], &buf[2 + pos], transfer_length);
++		for (retry = 0; retry < RETRY_MAX_TIMES; retry++) {
++			if (likely(i2c_transfer(client->adapter, &msg, 1) == 1)) {
++				pos += transfer_length;
++				address += transfer_length;
++				break;
++			}
++			dev_dbg(&client->dev, "I2C write retry[%d]\n", retry + 1);
++			usleep_range(2000, 2100);
++		}
++		if (unlikely(retry == RETRY_MAX_TIMES)) {
++			dev_err(&client->dev,
++				"I2c write failed,dev:%02x,reg:%04x,size:%u\n",
++				client->addr, address, len);
++			r = -EAGAIN;
++			goto write_exit;
++		}
++	}
++write_exit:
++	if (len + GTP_ADDR_LENGTH >= sizeof(put_buf))
++		kfree(msg.buf);
++	return r;
++}
++
++/*******************************************************
++ * Function:
++ *	i2c read twice, compare the results
++ * Input:
++ *	client:	i2c device
++ *	addr: operate address
++ *	rxbuf: read data to store, if compare successful
++ *	len: bytes to read
++ * Output:
++ *	FAIL: read failed
++ *	SUCCESS: read successful
++ *********************************************************/
++s32 gtp_i2c_read_dbl_check(struct i2c_client *client,
++			   u16 addr, u8 *rxbuf, int len)
++{
++	u8 buf[16] = {0};
++	u8 confirm_buf[16] = {0};
++	u8 retry = 0;
++
++	if (len + 2 > sizeof(buf)) {
++		dev_warn(&client->dev,
++			 "%s, only support length less then %zu\n",
++			 __func__, sizeof(buf) - 2);
++		return FAIL;
++	}
++	while (retry++ < 3) {
++		memset(buf, 0xAA, 16);
++		buf[0] = (u8)(addr >> 8);
++		buf[1] = (u8)(addr & 0xFF);
++		gtp_i2c_read(client, buf, len + 2);
++
++		memset(confirm_buf, 0xAB, 16);
++		confirm_buf[0] = (u8)(addr >> 8);
++		confirm_buf[1] = (u8)(addr & 0xFF);
++		gtp_i2c_read(client, confirm_buf, len + 2);
++
++		if (!memcmp(buf, confirm_buf, len + 2)) {
++			memcpy(rxbuf, confirm_buf + 2, len);
++			return SUCCESS;
++		}
++	}
++	dev_err(&client->dev,
++		"I2C read 0x%04X, %d bytes, double check failed!\n",
++		addr, len);
++
++	return FAIL;
++}
++
++/*******************************************************
++ * Function:
++ *      Send config.
++ * Input:
++ *      client: i2c device.
++ * Output:
++ *      result of i2c write operation.
++ *              1: succeed, otherwise
++ *              0: Not executed
++ *		< 0: failed
++ *********************************************************/
++s32 gtp_send_cfg(struct i2c_client *client)
++{
++	s32 ret, i;
++	u8 check_sum;
++	s32 retry = 0;
++	struct goodix_ts_data *ts = i2c_get_clientdata(client);
++	struct goodix_config_data *cfg = &ts->pdata->config;
++
++	if (!cfg->length || !ts->pdata->driver_send_cfg) {
++		dev_info(&ts->client->dev,
++			 "No config data or error occurred in panel_init\n");
++		return 0;
++	}
++
++	check_sum = 0;
++	for (i = GTP_ADDR_LENGTH; i < cfg->length; i++)
++		check_sum += cfg->data[i];
++	cfg->data[cfg->length] = (~check_sum) + 1;
++
++	dev_info(&ts->client->dev, "Driver send config\n");
++	for (retry = 0; retry < RETRY_MAX_TIMES; retry++) {
++		ret = gtp_i2c_write(client, cfg->data,
++			GTP_CONFIG_MAX_LENGTH + GTP_ADDR_LENGTH);
++		if (ret > 0)
++			break;
++	}
++
++	return ret;
++}
++
++/*******************************************************
++ * Function:
++ *	Control enable or disable of work thread.
++ * Input:
++ *      ts: goodix i2c_client private data
++ *	enable: enable var.
++ *********************************************************/
++void gtp_work_control_enable(struct goodix_ts_data *ts, bool enable)
++{
++	if (enable) {
++		set_bit(WORK_THREAD_ENABLED, &ts->flags);
++		dev_dbg(&ts->client->dev, "Input report thread enabled!\n");
++	} else {
++		clear_bit(WORK_THREAD_ENABLED, &ts->flags);
++		dev_dbg(&ts->client->dev, "Input report thread disabled!\n");
++	}
++}
++
++static int gtp_gesture_handler(struct goodix_ts_data *ts)
++{
++	u8 doze_buf[3] = {GTP_REG_DOZE_BUF >> 8, GTP_REG_DOZE_BUF & 0xFF};
++	int ret;
++
++	ret = gtp_i2c_read(ts->client, doze_buf, 3);
++	if (ret < 0) {
++		dev_err(&ts->client->dev, "Failed read doze buf");
++		return -EINVAL;
++	}
++
++	dev_dbg(&ts->client->dev, "0x814B = 0x%02X", doze_buf[2]);
++	if ((doze_buf[2] == 'a') || (doze_buf[2] == 'b') ||
++	    (doze_buf[2] == 'c') || (doze_buf[2] == 'd') ||
++	    (doze_buf[2] == 'e') || (doze_buf[2] == 'g') ||
++	    (doze_buf[2] == 'h') || (doze_buf[2] == 'm') ||
++	    (doze_buf[2] == 'o') || (doze_buf[2] == 'q') ||
++	    (doze_buf[2] == 's') || (doze_buf[2] == 'v') ||
++	    (doze_buf[2] == 'w') || (doze_buf[2] == 'y') ||
++	    (doze_buf[2] == 'z') || (doze_buf[2] == 0x5E) ||
++	    (doze_buf[2] == 0xAA) || (doze_buf[2] == 0xAB) ||
++	    (doze_buf[2] == 0xBA) || (doze_buf[2] == 0xBB) ||
++	    (doze_buf[2] == 0xCC)) {
++		doze_status = DOZE_WAKEUP;
++		input_report_key(ts->input_dev, KEY_POWER, 1);
++		input_sync(ts->input_dev);
++		input_report_key(ts->input_dev, KEY_POWER, 0);
++		input_sync(ts->input_dev);
++		/*  clear 0x814B */
++		doze_buf[2] = 0x00;
++		gtp_i2c_write(ts->client, doze_buf, 3);
++	} else {
++		/*  clear 0x814B */
++		doze_buf[2] = 0x00;
++		gtp_i2c_write(ts->client, doze_buf, 3);
++		gtp_enter_doze(ts);
++	}
++	return 0;
++}
++
++/*
++ * return touch state register value
++ * pen event id fixed with 9 and set tool type TOOL_PEN
++ *
++ */
++static u8 gtp_get_points(struct goodix_ts_data *ts,
++			 struct goodix_point_t *points,
++			 u8 *key_value)
++{
++	int ret;
++	int i;
++	u8 *coor_data = NULL;
++	u8 finger_state = 0;
++	u8 touch_num = 0;
++	u8 end_cmd[3] = { GTP_READ_COOR_ADDR >> 8,
++			  GTP_READ_COOR_ADDR & 0xFF, 0 };
++	u8 point_data[2 + 1 + 8 * GTP_MAX_TOUCH_ID + 1] = {
++			GTP_READ_COOR_ADDR >> 8, GTP_READ_COOR_ADDR & 0xFF };
++
++	ret = gtp_i2c_read(ts->client, point_data, 12);
++	if (ret < 0) {
++		dev_err(&ts->client->dev,
++			"I2C transfer error. errno:%d\n ", ret);
++		return 0;
++	}
++	finger_state = point_data[GTP_ADDR_LENGTH];
++	if (finger_state == 0x00)
++		return 0;
++
++	touch_num = finger_state & 0x0f;
++	if ((finger_state & MASK_BIT_8) == 0 ||
++	    touch_num > ts->pdata->max_touch_id) {
++		dev_err(&ts->client->dev,
++			"Invalid touch state: 0x%x", finger_state);
++		finger_state = 0;
++		goto exit_get_point;
++	}
++
++	if (touch_num > 1) {
++		u8 buf[8 * GTP_MAX_TOUCH_ID] = {
++					  (GTP_READ_COOR_ADDR + 10) >> 8,
++					  (GTP_READ_COOR_ADDR + 10) & 0xff };
++
++		ret = gtp_i2c_read(ts->client, buf, 2 + 8 * (touch_num - 1));
++		if (ret < 0) {
++			dev_err(&ts->client->dev, "I2C error. %d\n", ret);
++			finger_state = 0;
++			goto exit_get_point;
++		}
++		memcpy(&point_data[12], &buf[2], 8 * (touch_num - 1));
++	}
++
++	/* panel have touch key */
++	/* 0x20_UPKEY 0X10_DOWNKEY 0X40_ALLKEYDOWN */
++	*key_value = point_data[3 + 8 * touch_num];
++
++	memset(points, 0, sizeof(*points) * GTP_MAX_TOUCH_ID);
++	for (i = 0; i < touch_num; i++) {
++		coor_data = &point_data[i * 8 + 3];
++		points[i].id = coor_data[0];
++		points[i].x = coor_data[1] | (coor_data[2] << 8);
++		points[i].y = coor_data[3] | (coor_data[4] << 8);
++		points[i].w = coor_data[5] | (coor_data[6] << 8);
++		/* if pen hover points[].p must set to zero */
++		points[i].p = coor_data[5] | (coor_data[6] << 8);
++
++		if (ts->pdata->swap_x2y)
++			GTP_SWAP(points[i].x, points[i].y);
++
++		dev_dbg(&ts->client->dev, "[%d][%d %d %d]\n",
++			points[i].id, points[i].x, points[i].y, points[i].p);
++
++		/* pen device coordinate */
++		if (points[i].id & 0x80) {
++			points[i].tool_type = GTP_TOOL_PEN;
++			points[i].id = 10;
++			if (ts->pdata->pen_suppress_finger) {
++				points[0] = points[i];
++				memset(++points, 0, sizeof(*points) * (GTP_MAX_TOUCH_ID - 1));
++				finger_state &= 0xf0;
++				finger_state |= 0x01;
++				break;
++			}
++		} else {
++			points[i].tool_type = GTP_TOOL_FINGER;
++		}
++	}
++
++exit_get_point:
++	if (!test_bit(RAW_DATA_MODE, &ts->flags)) {
++		ret = gtp_i2c_write(ts->client, end_cmd, 3);
++		if (ret < 0)
++			dev_info(&ts->client->dev, "I2C write end_cmd error!");
++	}
++	return finger_state;
++}
++
++static void gtp_type_a_report(struct goodix_ts_data *ts, u8 touch_num,
++			      struct goodix_point_t *points)
++{
++	int i;
++	u16 cur_touch = 0;
++	static u16 pre_touch;
++	static u8 pre_pen_id;
++
++	if (touch_num)
++		input_report_key(ts->input_dev, BTN_TOUCH, 1);
++
++	for (i = 0; i < ts->pdata->max_touch_id; i++) {
++		if (touch_num && i == points->id) {
++			input_report_abs(ts->input_dev, ABS_MT_TRACKING_ID, points->id);
++
++			if (points->tool_type == GTP_TOOL_PEN) {
++				input_report_key(ts->input_dev, BTN_TOOL_PEN, true);
++				pre_pen_id = points->id;
++			} else {
++				input_report_key(ts->input_dev, BTN_TOOL_FINGER, true);
++			}
++			input_report_abs(ts->input_dev, ABS_MT_POSITION_X,
++					 points->x);
++			input_report_abs(ts->input_dev, ABS_MT_POSITION_Y,
++					 points->y);
++			input_report_abs(ts->input_dev, ABS_MT_TOUCH_MAJOR,
++					 points->w);
++			input_report_abs(ts->input_dev, ABS_MT_PRESSURE,
++					 points->p);
++			input_mt_sync(ts->input_dev);
++
++			cur_touch |= 0x01 << points->id;
++			points++;
++		} else if (pre_touch & 0x01 << i) {
++			if (pre_pen_id == i) {
++				input_report_key(ts->input_dev, BTN_TOOL_PEN, false);
++				/* valid id will < 10, so id to 0xff to indicate a invalid state */
++				pre_pen_id = 0xff;
++			} else {
++				input_report_key(ts->input_dev, BTN_TOOL_FINGER, false);
++			}
++		}
++	}
++
++	pre_touch = cur_touch;
++	if (!pre_touch) {
++		input_mt_sync(ts->input_dev);
++		input_report_key(ts->input_dev, BTN_TOUCH, 0);
++	}
++	input_sync(ts->input_dev);
++}
++
++static void gtp_mt_slot_report(struct goodix_ts_data *ts, u8 touch_num,
++			       struct goodix_point_t *points)
++{
++	int i;
++	u16 cur_touch = 0;
++	static u16 pre_touch;
++	static u8 pre_pen_id;
++
++	for (i = 0; i < ts->pdata->max_touch_id; i++) {
++		if (touch_num && i == points->id) {
++			input_mt_slot(ts->input_dev, points->id);
++
++			if (points->tool_type == GTP_TOOL_PEN) {
++				input_mt_report_slot_state(ts->input_dev,
++							   MT_TOOL_PEN, true);
++				pre_pen_id = points->id;
++			} else {
++				input_mt_report_slot_state(ts->input_dev,
++							   MT_TOOL_FINGER, true);
++			}
++			input_report_abs(ts->input_dev, ABS_MT_POSITION_X,
++					 points->x);
++			input_report_abs(ts->input_dev, ABS_MT_POSITION_Y,
++					 points->y);
++			input_report_abs(ts->input_dev, ABS_MT_TOUCH_MAJOR,
++					 points->w);
++			input_report_abs(ts->input_dev, ABS_MT_PRESSURE,
++					 points->p);
++
++			cur_touch |= 0x01 << points->id;
++			points++;
++		} else if (pre_touch & 0x01 << i) {
++			input_mt_slot(ts->input_dev, i);
++			if (pre_pen_id == i) {
++				input_mt_report_slot_state(ts->input_dev,
++							   MT_TOOL_PEN, false);
++				/* valid id will < 10, so set id to 0xff to
++				 * indicate a invalid state
++				 */
++				pre_pen_id = 0xff;
++			} else {
++				input_mt_report_slot_state(ts->input_dev,
++							   MT_TOOL_FINGER, false);
++			}
++		}
++	}
++
++	pre_touch = cur_touch;
++	/* report BTN_TOUCH event */
++	input_mt_sync_frame(ts->input_dev);
++	input_sync(ts->input_dev);
++}
++
++/*******************************************************
++ * Function:
++ *	Goodix touchscreen sensor report function
++ * Input:
++ *	ts: goodix tp private data
++ * Output:
++ *	None.
++ *********************************************************/
++static void gtp_work_func(struct goodix_ts_data *ts)
++{
++	u8 point_state = 0;
++	u8 key_value = 0;
++	s32 i = 0;
++	s32 ret = -1;
++	static u8 pre_key;
++	struct goodix_point_t points[GTP_MAX_TOUCH_ID];
++
++	if (test_bit(PANEL_RESETTING, &ts->flags))
++		return;
++	if (!test_bit(WORK_THREAD_ENABLED, &ts->flags))
++		return;
++
++	/* gesture event */
++	if (ts->pdata->slide_wakeup && test_bit(DOZE_MODE, &ts->flags)) {
++		ret =  gtp_gesture_handler(ts);
++		if (ret)
++			dev_err(&ts->client->dev,
++				"Failed handler gesture event %d\n", ret);
++		return;
++	}
++
++	point_state = gtp_get_points(ts, points, &key_value);
++	if (!point_state) {
++		dev_dbg(&ts->client->dev, "Invalid finger points\n");
++		return;
++	}
++
++	/* touch key event */
++	if (key_value & 0xf0 || pre_key & 0xf0) {
++		/* pen button */
++		switch (key_value) {
++		case 0x40:
++			input_report_key(ts->input_dev, GTP_PEN_BUTTON1, 1);
++			input_report_key(ts->input_dev, GTP_PEN_BUTTON2, 1);
++			break;
++		case 0x10:
++			input_report_key(ts->input_dev, GTP_PEN_BUTTON1, 1);
++			input_report_key(ts->input_dev, GTP_PEN_BUTTON2, 0);
++			dev_dbg(&ts->client->dev, "pen button1 down\n");
++			break;
++		case 0x20:
++			input_report_key(ts->input_dev, GTP_PEN_BUTTON1, 0);
++			input_report_key(ts->input_dev, GTP_PEN_BUTTON2, 1);
++			break;
++		default:
++			input_report_key(ts->input_dev, GTP_PEN_BUTTON1, 0);
++			input_report_key(ts->input_dev, GTP_PEN_BUTTON2, 0);
++			dev_dbg(&ts->client->dev, "button1 up\n");
++			break;
++		}
++		input_sync(ts->input_dev);
++		pre_key = key_value;
++	} else if (key_value & 0x0f || pre_key & 0x0f) {
++		/* panel key */
++		for (i = 0; i < ts->pdata->key_nums; i++) {
++			if ((pre_key | key_value) & (0x01 << i))
++				input_report_key(ts->input_dev,
++						 ts->pdata->key_map[i],
++						 key_value & (0x01 << i));
++		}
++		input_sync(ts->input_dev);
++		pre_key = key_value;
++	}
++
++	if (!ts->pdata->type_a_report)
++		gtp_mt_slot_report(ts, point_state & 0x0f, points);
++	else
++		gtp_type_a_report(ts, point_state & 0x0f, points);
++}
++
++/*******************************************************
++ * Function:
++ *	Timer interrupt service routine for polling mode.
++ * Input:
++ *	timer: timer struct pointer
++ * Output:
++ *	Timer work mode.
++ * HRTIMER_NORESTART:
++ *	no restart mode
++ *********************************************************/
++static enum hrtimer_restart gtp_timer_handler(struct hrtimer *timer)
++{
++	struct goodix_ts_data *ts =
++		container_of(timer, struct goodix_ts_data, timer);
++
++	gtp_work_func(ts);
++	hrtimer_start(&ts->timer, ktime_set(0, (GTP_POLL_TIME + 6) * 1000000),
++		      HRTIMER_MODE_REL);
++
++	return HRTIMER_NORESTART;
++}
++
++static irqreturn_t gtp_irq_handler(int irq, void *dev_id)
++{
++	struct goodix_ts_data *ts = dev_id;
++
++	gtp_work_func(ts);
++	return IRQ_HANDLED;
++}
++
++void gtp_int_output(struct goodix_ts_data *ts, int level)
++{
++	if (!ts->pdata->int_sync)
++		return;
++
++	if (level == 0) {
++		if (ts->pinctrl.pinctrl)
++			pinctrl_select_state(ts->pinctrl.pinctrl,
++					     ts->pinctrl.int_out_low);
++		else if (gpio_is_valid(ts->pdata->irq_gpio))
++			gpio_direction_output(ts->pdata->irq_gpio, 0);
++		else
++			dev_err(&ts->client->dev,
++				"Failed set int pin output low\n");
++	} else {
++		if (ts->pinctrl.pinctrl)
++			pinctrl_select_state(ts->pinctrl.pinctrl,
++					     ts->pinctrl.int_out_high);
++		else if (gpio_is_valid(ts->pdata->irq_gpio))
++			gpio_direction_output(ts->pdata->irq_gpio, 1);
++		else
++			dev_err(&ts->client->dev,
++				"Failed set int pin output high\n");
++	}
++}
++
++void gtp_int_sync(struct goodix_ts_data *ts, s32 ms)
++{
++	if (!ts->pdata->int_sync)
++		return;
++
++	if (ts->pinctrl.pinctrl) {
++		gtp_int_output(ts, 0);
++		msleep(ms);
++		pinctrl_select_state(ts->pinctrl.pinctrl,
++				     ts->pinctrl.int_input);
++	} else if (gpio_is_valid(ts->pdata->irq_gpio)) {
++		gpio_direction_output(ts->pdata->irq_gpio, 0);
++		msleep(ms);
++		gpio_direction_input(ts->pdata->irq_gpio);
++	} else {
++		dev_err(&ts->client->dev, "Failed sync int pin\n");
++	}
++}
++
++/*******************************************************
++ * Function:
++ *	Reset chip. Control the reset pin and int-pin(if
++ *	defined),
++ * Input:
++ *	client:	i2c device.
++ *	ms: reset time in millisecond
++ * Output:
++ *	None.
++ *******************************************************/
++void gtp_reset_guitar(struct i2c_client *client, s32 ms)
++{
++	struct goodix_ts_data *ts = i2c_get_clientdata(client);
++
++	dev_info(&client->dev, "Guitar reset");
++	set_bit(PANEL_RESETTING, &ts->flags);
++	if (!gpio_is_valid(ts->pdata->rst_gpio)) {
++		dev_warn(&client->dev, "reset failed no valid reset gpio");
++		return;
++	}
++
++	gpio_direction_output(ts->pdata->rst_gpio, 0);
++	usleep_range(ms * 1000, ms * 1000 + 100);	/*  T2: > 10ms */
++
++	gtp_int_output(ts, client->addr == 0x14);
++
++	usleep_range(2000, 3000);		/*  T3: > 100us (2ms)*/
++	gpio_direction_output(ts->pdata->rst_gpio, 1);
++
++	usleep_range(6000, 7000);		/*  T4: > 5ms */
++	gpio_direction_output(ts->pdata->rst_gpio, 1);
++
++	gtp_int_sync(ts, 50);
++	if (ts->pdata->esd_protect)
++		gtp_init_ext_watchdog(client);
++
++	clear_bit(PANEL_RESETTING, &ts->flags);
++}
++
++/*******************************************************
++ * Function:
++ *	Enter doze mode for sliding wakeup.
++ * Input:
++ *	ts: goodix tp private data
++ * Output:
++ *	1: succeed, otherwise failed
++ *******************************************************/
++static int gtp_enter_doze(struct goodix_ts_data *ts)
++{
++	int ret = -1;
++	int retry = 0;
++	u8 i2c_control_buf[3] = { (u8)(GTP_REG_COMMAND >> 8),
++				  (u8)GTP_REG_COMMAND, 8 };
++
++	/*  resend doze command
++	 * if (test_and_set_bit(DOZE_MODE, &ts->flags)) {
++	 *	dev_info(&ts->client->dev, "Already in doze mode\n");
++	 *	return SUCCESS;
++	 * }
++	 */
++	set_bit(DOZE_MODE, &ts->flags);
++	dev_dbg(&ts->client->dev, "Entering gesture mode.");
++	while (retry++ < 5) {
++		i2c_control_buf[0] = (u8)(GTP_REG_COMMAND_CHECK >> 8);
++		i2c_control_buf[1] = (u8)GTP_REG_COMMAND_CHECK;
++		ret = gtp_i2c_write(ts->client, i2c_control_buf, 3);
++		if (ret < 0) {
++			dev_dbg(&ts->client->dev,
++				"failed to set doze flag into 0x8046, %d\n",
++				retry);
++			continue;
++		}
++		i2c_control_buf[0] = (u8)(GTP_REG_COMMAND >> 8);
++		i2c_control_buf[1] = (u8)GTP_REG_COMMAND;
++		ret = gtp_i2c_write(ts->client, i2c_control_buf, 3);
++		if (ret > 0) {
++			dev_dbg(&ts->client->dev, "Gesture mode enabled\n");
++			return ret;
++		}
++		usleep_range(10000, 11000);
++	}
++
++	dev_err(&ts->client->dev, "Failed enter doze mode\n");
++	clear_bit(DOZE_MODE, &ts->flags);
++	return ret;
++}
++
++static s8 gtp_enter_sleep(struct goodix_ts_data *ts)
++{
++	s8 ret = -1;
++	s8 retry = 0;
++	u8 i2c_control_buf[3] = { (u8)(GTP_REG_COMMAND >> 8),
++				  (u8)GTP_REG_COMMAND, 5 };
++
++	gtp_int_output(ts, 0);
++//	usleep_range(5000, 6000);
++
++	while (retry++ < 5) {
++		ret = gtp_i2c_write(ts->client, i2c_control_buf, 3);
++		if (ret > 0) {
++			dev_info(&ts->client->dev, "Enter sleep mode\n");
++
++			return ret;
++		}
++		usleep_range(10000, 11000);
++	}
++	dev_err(&ts->client->dev, "Failed send sleep cmd\n");
++
++	return ret;
++}
++
++static int gtp_wakeup_sleep(struct goodix_ts_data *ts)
++{
++	u8 retry = 0;
++	int ret = -1;
++
++	while (retry++ < 10) {
++		gtp_int_output(ts, 1);
++		usleep_range(5000, 6000);
++
++		ret = gtp_i2c_test(ts->client);
++		if (!ret) {
++			dev_dbg(&ts->client->dev, "Success wakeup sleep\n");
++
++			gtp_int_sync(ts, 25);
++			if (ts->pdata->esd_protect)
++				gtp_init_ext_watchdog(ts->client);
++
++			return ret;
++		}
++		gtp_reset_guitar(ts->client, 20);
++	}
++
++	dev_err(&ts->client->dev, "Failed wakeup from sleep mode\n");
++	return -EINVAL;
++}
++
++static int gtp_find_valid_cfg_data(struct goodix_ts_data *ts)
++{
++	int ret = -1;
++	u8 sensor_id = 0;
++	struct goodix_config_data *cfg = &ts->pdata->config;
++
++	/* if defined CONFIG_OF, parse config data from dtsi
++	 * else parse config data form header file.
++	 */
++	cfg->length = 0;
++
++#ifndef	CONFIG_OF
++	u8 cfg_info_group0[] = CTP_CFG_GROUP0;
++	u8 cfg_info_group1[] = CTP_CFG_GROUP1;
++	u8 cfg_info_group2[] = CTP_CFG_GROUP2;
++	u8 cfg_info_group3[] = CTP_CFG_GROUP3;
++	u8 cfg_info_group4[] = CTP_CFG_GROUP4;
++	u8 cfg_info_group5[] = CTP_CFG_GROUP5;
++
++	u8 *send_cfg_buf[] = { cfg_info_group0, cfg_info_group1,
++			       cfg_info_group2, cfg_info_group3,
++			       cfg_info_group4, cfg_info_group5 };
++	u8 cfg_info_len[] = { CFG_GROUP_LEN(cfg_info_group0),
++			      CFG_GROUP_LEN(cfg_info_group1),
++			      CFG_GROUP_LEN(cfg_info_group2),
++			      CFG_GROUP_LEN(cfg_info_group3),
++			      CFG_GROUP_LEN(cfg_info_group4),
++			      CFG_GROUP_LEN(cfg_info_group5)};
++
++	dev_dbg(&ts->client->dev,
++		"Config Groups\' Lengths: %d, %d, %d, %d, %d, %d",
++		cfg_info_len[0], cfg_info_len[1], cfg_info_len[2],
++		cfg_info_len[3], cfg_info_len[4], cfg_info_len[5]);
++#endif
++
++	/* read sensor id */
++	ret = gtp_i2c_read_dbl_check(ts->client, GTP_REG_SENSOR_ID,
++				     &sensor_id, 1);
++	if (SUCCESS != ret || sensor_id >= 0x06) {
++		dev_err(&ts->client->dev,
++			"Failed get valid sensor_id(0x%02X), No Config Sent\n",
++			sensor_id);
++		return -EINVAL;
++	}
++
++	dev_dbg(&ts->client->dev, "Sensor_ID: %d", sensor_id);
++	/* parse config data */
++#ifdef CONFIG_OF
++	dev_dbg(&ts->client->dev, "Get config data from device tree\n");
++	ret = gtp_parse_dt_cfg(&ts->client->dev,
++			       &cfg->data[GTP_ADDR_LENGTH],
++			       &cfg->length, sensor_id);
++	if (ret < 0) {
++		dev_err(&ts->client->dev,
++			"Failed to parse config data form device tree\n");
++		cfg->length = 0;
++		return -EPERM;
++	}
++#else
++	dev_dbg(&ts->client->dev, "Get config data from header file\n");
++	if ((!cfg_info_len[1]) && (!cfg_info_len[2]) &&
++	    (!cfg_info_len[3]) && (!cfg_info_len[4]) &&
++	    (!cfg_info_len[5])) {
++		sensor_id = 0;
++	}
++	cfg->length = cfg_info_len[sensor_id];
++	memset(&cfg->data[GTP_ADDR_LENGTH], 0, GTP_CONFIG_MAX_LENGTH);
++	memcpy(&cfg->data[GTP_ADDR_LENGTH], send_cfg_buf[sensor_id],
++	       cfg->length);
++#endif
++
++	if (cfg->length < GTP_CONFIG_MIN_LENGTH) {
++		dev_err(&ts->client->dev,
++			"Failed get valid config data with sensor id %d\n",
++			sensor_id);
++		cfg->length = 0;
++		return -EPERM;
++	}
++
++	dev_info(&ts->client->dev, "Config group%d used,length: %d\n",
++		 sensor_id, cfg->length);
++
++	return 0;
++}
++
++/*******************************************************
++ * Function:
++ *	Get valid config data from dts or .h file.
++ *	Read firmware version info and judge firmware
++ *	working state
++ * Input:
++ *	ts: goodix private data
++ * Output:
++ *	Executive outcomes.
++ *		0: succeed, otherwise: failed
++ *******************************************************/
++static s32 gtp_init_panel(struct goodix_ts_data *ts)
++{
++	s32 ret = -1;
++	u8 opr_buf[16] = {0};
++	u8 drv_cfg_version = 0;
++	u8 flash_cfg_version = 0;
++	struct goodix_config_data *cfg = &ts->pdata->config;
++
++	if (!ts->pdata->driver_send_cfg) {
++		dev_info(&ts->client->dev, "Driver set not send config\n");
++		cfg->length = GTP_CONFIG_MAX_LENGTH;
++		ret = gtp_i2c_read(ts->client,
++				   cfg->data, cfg->length +
++				   GTP_ADDR_LENGTH);
++		if (ret < 0)
++			dev_err(&ts->client->dev, "Read origin Config Failed\n");
++
++		return 0;
++	}
++
++	gtp_find_valid_cfg_data(ts);
++
++	/* check firmware */
++	ret = gtp_i2c_read_dbl_check(ts->client, 0x41E4, opr_buf, 1);
++	if (SUCCESS == ret) {
++		if (opr_buf[0] != 0xBE) {
++			set_bit(FW_ERROR, &ts->flags);
++			dev_err(&ts->client->dev,
++				"Firmware error, no config sent!\n");
++			return -EINVAL;
++		}
++	}
++
++	ret = gtp_i2c_read_dbl_check(ts->client, GTP_REG_CONFIG_DATA,
++				     &opr_buf[0], 1);
++	if (ret == SUCCESS) {
++		dev_dbg(&ts->client->dev,
++			"Config Version: %d; IC Config Version: %d\n",
++			cfg->data[GTP_ADDR_LENGTH], opr_buf[0]);
++		flash_cfg_version = opr_buf[0];
++		drv_cfg_version = cfg->data[GTP_ADDR_LENGTH];
++
++		if (flash_cfg_version < 90 &&
++		    flash_cfg_version > drv_cfg_version)
++			cfg->data[GTP_ADDR_LENGTH] = 0x00;
++	} else {
++		dev_err(&ts->client->dev,
++			"Failed to get ic config version!No config sent\n");
++		return -EPERM;
++	}
++
++	ret = gtp_send_cfg(ts->client);
++	if (ret < 0)
++		dev_err(&ts->client->dev, "Send config error\n");
++	else
++		usleep_range(10000, 11000); /* 10 ms */
++
++	/* restore config version */
++	cfg->data[GTP_ADDR_LENGTH] = drv_cfg_version;
++
++	return 0;
++}
++
++static ssize_t gtp_config_read_proc(struct file *file, char __user *page,
++				    size_t size, loff_t *ppos)
++{
++	int i, ret;
++	char *ptr;
++	size_t data_len = 0;
++	char temp_data[GTP_CONFIG_MAX_LENGTH + 2] = {
++					(u8)(GTP_REG_CONFIG_DATA >> 8),
++					(u8)GTP_REG_CONFIG_DATA };
++	struct goodix_ts_data *ts = i2c_get_clientdata(i2c_connect_client);
++	struct goodix_config_data *cfg = &ts->pdata->config;
++
++	ptr = kzalloc(4096, GFP_KERNEL);
++	if (!ptr) {
++		dev_err(&ts->client->dev, "Failed alloc memory for config\n");
++		return -ENOMEM;
++	}
++
++	data_len += snprintf(ptr + data_len, 4096 - data_len,
++			     "====init value====\n");
++	for (i = 0 ; i < GTP_CONFIG_MAX_LENGTH ; i++) {
++		data_len += snprintf(ptr + data_len, 4096 - data_len,
++				     "0x%02X ", cfg->data[i + 2]);
++
++		if (i % 8 == 7)
++			data_len += snprintf(ptr + data_len,
++					     4096 - data_len, "\n");
++	}
++	data_len += snprintf(ptr + data_len, 4096 - data_len, "\n");
++
++	data_len += snprintf(ptr + data_len, 4096 - data_len,
++			     "====real value====\n");
++	ret = gtp_i2c_read(i2c_connect_client, temp_data,
++			   GTP_CONFIG_MAX_LENGTH + 2);
++	if (ret < 0) {
++		data_len += snprintf(ptr + data_len, 4096 - data_len,
++				     "Failed read real config data\n");
++	} else {
++		for (i = 0; i < GTP_CONFIG_MAX_LENGTH; i++) {
++			data_len += snprintf(ptr + data_len, 4096 - data_len,
++					     "0x%02X ", temp_data[i + 2]);
++
++			if (i % 8 == 7)
++				data_len += snprintf(ptr + data_len,
++						     4096 - data_len, "\n");
++		}
++	}
++
++	data_len = simple_read_from_buffer(page, size, ppos, ptr, data_len);
++	kfree(ptr);
++	ptr = NULL;
++	return data_len;
++}
++
++static u8 ascii2hex(u8 a)
++{
++	s8 value = 0;
++
++	if (a >= '0' && a <= '9')
++		value = a - '0';
++	else if (a >= 'A' && a <= 'F')
++		value = a - 'A' + 0x0A;
++	else if (a >= 'a' && a <= 'f')
++		value = a - 'a' + 0x0A;
++	else
++		value = 0xff;
++
++	return value;
++}
++
++int gtp_ascii_to_array(const u8 *src_buf, int src_len, u8 *dst_buf)
++{
++	int i, ret;
++	int cfg_len = 0;
++	u8 high, low;
++
++	for (i = 0; i < src_len;) {
++		if (src_buf[i] == ' ' || src_buf[i] == '\r' ||
++		    src_buf[i] == '\n') {
++			i++;
++			continue;
++		}
++
++		if ((src_buf[i] == '0') && ((src_buf[i + 1] == 'x') ||
++					    (src_buf[i + 1] == 'X'))) {
++			high = ascii2hex(src_buf[i + 2]);
++			low = ascii2hex(src_buf[i + 3]);
++
++			if ((high == 0xFF) || (low == 0xFF)) {
++				ret = -1;
++				goto convert_failed;
++			}
++
++			if (cfg_len < GTP_CONFIG_MAX_LENGTH) {
++				dst_buf[cfg_len++] = (high << 4) + low;
++				i += 5;
++			} else {
++				ret = -2;
++				goto convert_failed;
++			}
++		} else {
++			ret = -3;
++			goto convert_failed;
++		}
++	}
++	return cfg_len;
++
++convert_failed:
++	return ret;
++}
++
++static ssize_t gtp_config_write_proc(struct file *filp,
++				     const char __user *buffer,
++				     size_t count, loff_t *off)
++{
++	u8 *temp_buf;
++	u8 *file_config;
++	int file_cfg_len;
++	s32 ret = 0, i;
++	struct goodix_ts_data *ts = i2c_get_clientdata(i2c_connect_client);
++
++	dev_dbg(&ts->client->dev, "write count %zu\n", count);
++
++	if (count > PAGE_SIZE) {
++		dev_err(&ts->client->dev, "config to long %zu\n", count);
++		return -EFAULT;
++	}
++
++	temp_buf = kzalloc(count, GFP_KERNEL);
++	if (!temp_buf) {
++		dev_err(&ts->client->dev, "failed alloc temp memory");
++		return -ENOMEM;
++	}
++
++	file_config = kzalloc(GTP_CONFIG_MAX_LENGTH + GTP_ADDR_LENGTH,
++			      GFP_KERNEL);
++	if (!file_config) {
++		dev_err(&ts->client->dev, "failed alloc config memory");
++		kfree(temp_buf);
++		return -ENOMEM;
++	}
++	file_config[0] = GTP_REG_CONFIG_DATA >> 8;
++	file_config[1] = GTP_REG_CONFIG_DATA & 0xff;
++
++	if (copy_from_user(temp_buf, buffer, count)) {
++		dev_err(&ts->client->dev, "Failed copy from user\n");
++		ret = -EFAULT;
++		goto send_cfg_err;
++	}
++
++	file_cfg_len = gtp_ascii_to_array(temp_buf, (int)count,
++					  &file_config[GTP_ADDR_LENGTH]);
++	if (file_cfg_len < 0) {
++		dev_err(&ts->client->dev, "failed covert ascii to hex");
++		ret = -EFAULT;
++		goto send_cfg_err;
++	}
++
++	GTP_DEBUG_ARRAY(file_config + GTP_ADDR_LENGTH, file_cfg_len);
++
++	i = 0;
++	while (i++ < 5) {
++		ret = gtp_i2c_write(ts->client, file_config, file_cfg_len + 2);
++		if (ret > 0) {
++			dev_info(&ts->client->dev, "Send config SUCCESS.");
++			break;
++		}
++		dev_err(&ts->client->dev, "Send config i2c error.");
++		ret = -EFAULT;
++		goto send_cfg_err;
++	}
++
++	ret = count;
++send_cfg_err:
++	kfree(temp_buf);
++	kfree(file_config);
++	return ret;
++}
++
++static const struct proc_ops config_proc_ops = {
++	.proc_read = gtp_config_read_proc,
++	.proc_write = gtp_config_write_proc,
++};
++
++static ssize_t gtp_workmode_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	size_t data_len = 0;
++	struct goodix_ts_data *data = dev_get_drvdata(dev);
++
++	if (test_bit(DOZE_MODE, &data->flags))
++		data_len = scnprintf(buf, PAGE_SIZE, "%s\n",
++				     "doze_mode");
++	else if (test_bit(SLEEP_MODE, &data->flags))
++		data_len = scnprintf(buf, PAGE_SIZE, "%s\n",
++				     "sleep_mode");
++	else
++		data_len = scnprintf(buf, PAGE_SIZE, "%s\n",
++				     "normal_mode");
++
++	return data_len;
++}
++static DEVICE_ATTR(workmode, 0444, gtp_workmode_show, NULL);
++
++#ifdef CONFIG_TOUCHSCREEN_GT9XX_UPDATE
++#define FW_NAME_MAX_LEN	80
++static ssize_t gtp_dofwupdate_store(struct device *dev,
++				    struct device_attribute *attr,
++				    const char *buf, size_t count)
++{
++	struct goodix_ts_data *ts = dev_get_drvdata(dev);
++	char update_file_name[FW_NAME_MAX_LEN];
++	int retval;
++
++	if (count > FW_NAME_MAX_LEN) {
++		dev_info(&ts->client->dev, "FW filename is too long\n");
++		retval = -EINVAL;
++		goto exit;
++	}
++
++	strlcpy(update_file_name, buf, count);
++
++	ts->force_update = true;
++	retval = gup_update_proc(update_file_name);
++	if (retval == FAIL)
++		dev_err(&ts->client->dev, "Fail to update GTP firmware.\n");
++	else
++		dev_info(&ts->client->dev, "Update success\n");
++
++	return count;
++
++exit:
++	return retval;
++}
++static DEVICE_ATTR(dofwupdate, 0664, NULL, gtp_dofwupdate_store);
++#endif
++
++static ssize_t gtp_productinfo_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct goodix_ts_data *data = dev_get_drvdata(dev);
++	struct goodix_fw_info *fw_info = &data->fw_info;
++
++	return scnprintf(buf, PAGE_SIZE, "GT%s_%x_%d\n",
++			 fw_info->pid, fw_info->version, fw_info->sensor_id);
++}
++static DEVICE_ATTR(productinfo, 0444, gtp_productinfo_show, NULL);
++
++static ssize_t gtp_drv_irq_store(struct device *dev,
++				 struct device_attribute *attr,
++				 const char *buf, size_t count)
++{
++	unsigned long value = 0;
++	int err = 0;
++	struct goodix_ts_data *data = dev_get_drvdata(dev);
++
++	err = kstrtoul(buf, 10, &value);
++	if (err < 0) {
++		dev_err(dev, "Failed to convert value\n");
++		return -EINVAL;
++	}
++
++	switch (value) {
++	case 0:
++		/* Disable irq */
++		gtp_work_control_enable(data, false);
++		break;
++	case 1:
++		/* Enable irq */
++		gtp_work_control_enable(data, true);
++		break;
++	default:
++		dev_err(dev, "Invalid value\n");
++		return -EINVAL;
++	}
++
++	return count;
++}
++
++static ssize_t gtp_drv_irq_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct goodix_ts_data *data = dev_get_drvdata(dev);
++
++	return scnprintf(buf, PAGE_SIZE, "%s\n",
++			 test_bit(WORK_THREAD_ENABLED, &data->flags)
++			 ? "enabled" : "disabled");
++}
++static DEVICE_ATTR(drv_irq, 0664, gtp_drv_irq_show, gtp_drv_irq_store);
++
++static ssize_t gtp_reset_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct goodix_ts_data *data = dev_get_drvdata(dev);
++
++	if ('1' != buf[0]) {
++		dev_err(dev, "Invalid argument for reset\n");
++		return -EINVAL;
++	}
++
++	gtp_reset_guitar(data->client, 20);
++
++	return count;
++}
++static DEVICE_ATTR(reset, 0220, NULL, gtp_reset_store);
++
++static struct attribute *gtp_attrs[] = {
++	&dev_attr_workmode.attr,
++	&dev_attr_productinfo.attr,
++
++#ifdef CONFIG_TOUCHSCREEN_GT9XX_UPDATE
++	&dev_attr_dofwupdate.attr,
++#endif
++
++	&dev_attr_drv_irq.attr,
++	&dev_attr_reset.attr,
++	NULL
++};
++
++static const struct attribute_group gtp_attr_group = {
++	.attrs = gtp_attrs,
++};
++
++static int gtp_create_file(struct goodix_ts_data *ts)
++{
++	int ret;
++	struct i2c_client *client = ts->client;
++
++	/*  Create proc file system */
++	gtp_config_proc = NULL;
++	gtp_config_proc = proc_create(GT91XX_CONFIG_PROC_FILE, 0664,
++				      NULL, &config_proc_ops);
++	if (!gtp_config_proc)
++		dev_err(&client->dev, "create_proc_entry %s failed\n",
++			GT91XX_CONFIG_PROC_FILE);
++	else
++		dev_info(&client->dev, "create proc entry %s success\n",
++			 GT91XX_CONFIG_PROC_FILE);
++
++	ret = sysfs_create_group(&client->dev.kobj, &gtp_attr_group);
++	if (ret) {
++		dev_err(&client->dev, "Failure create sysfs group %d\n", ret);
++		/*TODO: debug change */
++		goto exit_free_config_proc;
++	}
++	return 0;
++
++exit_free_config_proc:
++	remove_proc_entry(GT91XX_CONFIG_PROC_FILE, gtp_config_proc);
++	return -ENODEV;
++}
++
++s32 gtp_get_fw_info(struct i2c_client *client, struct goodix_fw_info *fw_info)
++{
++	s32 ret = -1;
++	u8 buf[8] = {GTP_REG_VERSION >> 8, GTP_REG_VERSION & 0xff};
++
++	ret = gtp_i2c_read(client, buf, sizeof(buf));
++	if (ret < 0) {
++		dev_err(&client->dev, "Failed read fw_info\n");
++		return ret;
++	}
++
++	/* product id */
++	memset(fw_info, 0, sizeof(*fw_info));
++
++	if (buf[5] == 0x00) {
++		memcpy(fw_info->pid, buf + GTP_ADDR_LENGTH, 3);
++		dev_info(&client->dev, "IC Version: %c%c%c_%02X%02X\n",
++			 buf[2], buf[3], buf[4], buf[7], buf[6]);
++	} else {
++		memcpy(fw_info->pid, buf + GTP_ADDR_LENGTH, 4);
++		dev_info(&client->dev, "IC Version: %c%c%c%c_%02X%02X\n",
++			 buf[2], buf[3], buf[4], buf[5], buf[7], buf[6]);
++	}
++
++	/* current firmware version */
++	fw_info->version = (buf[7] << 8) | buf[6];
++
++	/* read sensor id */
++	fw_info->sensor_id = 0xff;
++	ret = gtp_i2c_read_dbl_check(client, GTP_REG_SENSOR_ID,
++				     &fw_info->sensor_id, 1);
++	if (SUCCESS != ret || fw_info->sensor_id >= 0x06) {
++		dev_err(&client->dev,
++			"Failed get valid sensor_id(0x%02X), No Config Sent\n",
++			fw_info->sensor_id);
++
++		fw_info->sensor_id = 0xff;
++	}
++
++	return ret;
++}
++
++static int gtp_i2c_test(struct i2c_client *client)
++{
++	u8 test[3] = {GTP_REG_CONFIG_DATA >> 8, GTP_REG_CONFIG_DATA & 0xff};
++	u8 retry = 0;
++	int ret = -1;
++
++	while (retry++ < 3) {
++		ret = gtp_i2c_read(client, test, 3);
++		if (ret == 2)
++			return 0;
++
++		dev_err(&client->dev, "GTP i2c test failed time %d\n", retry);
++		usleep_range(10000, 11000); /* 10 ms */
++	}
++
++	return -EAGAIN;
++}
++
++static int gtp_pinctrl_init(struct goodix_ts_data *ts)
++{
++	struct goodix_pinctrl *pinctrl = &ts->pinctrl;
++
++	pinctrl->pinctrl = devm_pinctrl_get(&ts->client->dev);
++	if (IS_ERR_OR_NULL(pinctrl->pinctrl)) {
++		dev_info(&ts->client->dev, "No pinctrl found\n");
++		pinctrl->pinctrl = NULL;
++		return 0;
++	}
++
++	pinctrl->default_sta = pinctrl_lookup_state(pinctrl->pinctrl,
++						    "default");
++	if (IS_ERR_OR_NULL(pinctrl->default_sta)) {
++		dev_info(&ts->client->dev,
++			 "Failed get pinctrl state:default state\n");
++		goto exit_pinctrl_init;
++	}
++
++	pinctrl->int_out_high = pinctrl_lookup_state(pinctrl->pinctrl,
++						     "int-output-high");
++	if (IS_ERR_OR_NULL(pinctrl->int_out_high)) {
++		dev_info(&ts->client->dev,
++			 "Failed get pinctrl state:output_high\n");
++		goto exit_pinctrl_init;
++	}
++
++	pinctrl->int_out_low = pinctrl_lookup_state(pinctrl->pinctrl,
++						    "int-output-low");
++	if (IS_ERR_OR_NULL(pinctrl->int_out_low)) {
++		dev_info(&ts->client->dev,
++			 "Failed get pinctrl state:output_low\n");
++		goto exit_pinctrl_init;
++	}
++
++	pinctrl->int_input = pinctrl_lookup_state(pinctrl->pinctrl,
++						  "int-input");
++	if (IS_ERR_OR_NULL(pinctrl->int_input)) {
++		dev_info(&ts->client->dev,
++			 "Failed get pinctrl state:int-input\n");
++		goto exit_pinctrl_init;
++	}
++	dev_info(&ts->client->dev, "Success init pinctrl\n");
++	return 0;
++exit_pinctrl_init:
++	devm_pinctrl_put(pinctrl->pinctrl);
++	pinctrl->pinctrl = NULL;
++	pinctrl->int_out_high = NULL;
++	pinctrl->int_out_low = NULL;
++	pinctrl->int_input = NULL;
++	return 0;
++}
++
++static void gtp_pinctrl_deinit(struct goodix_ts_data *ts)
++{
++	if (ts->pinctrl.pinctrl)
++		devm_pinctrl_put(ts->pinctrl.pinctrl);
++}
++
++static int gtp_request_io_port(struct goodix_ts_data *ts)
++{
++	int ret = 0;
++
++	if (!ts->pinctrl.pinctrl) {
++		if (gpio_is_valid(ts->pdata->irq_gpio)) {
++			ret = gpio_request(ts->pdata->irq_gpio, "goodix_ts_int");
++			if (ret < 0) {
++				dev_err(&ts->client->dev,
++					"Failed to request GPIO:%d, ERRNO:%d\n",
++					(s32)ts->pdata->irq_gpio, ret);
++				return -ENODEV;
++			}
++
++			gpio_direction_input(ts->pdata->irq_gpio);
++			dev_info(&ts->client->dev, "Success request irq-gpio\n");
++		}
++	}
++
++	if (gpio_is_valid(ts->pdata->rst_gpio)) {
++		ret = gpio_request(ts->pdata->rst_gpio, "goodix_ts_rst");
++		if (ret < 0) {
++			dev_err(&ts->client->dev,
++				"Failed to request GPIO:%d, ERRNO:%d\n",
++				(s32)ts->pdata->rst_gpio, ret);
++
++			if (gpio_is_valid(ts->pdata->irq_gpio))
++				gpio_free(ts->pdata->irq_gpio);
++
++			return -ENODEV;
++		}
++
++		gpio_direction_input(ts->pdata->rst_gpio);
++		dev_info(&ts->client->dev,  "Success request rst-gpio\n");
++	}
++
++	return 0;
++}
++
++/*******************************************************
++ * Function:
++ *	Request interrupt if define irq pin, else use hrtimer
++ *	as interrupt source
++ * Input:
++ *	ts: private data.
++ * Output:
++ *	Executive outcomes.
++ *		0: succeed, -1: failed.
++ *******************************************************/
++static int gtp_request_irq(struct goodix_ts_data *ts)
++{
++	int ret = -1;
++
++	/* use irq */
++	if (gpio_is_valid(ts->pdata->irq_gpio) || ts->client->irq > 0) {
++		if (gpio_is_valid(ts->pdata->irq_gpio))
++			ts->client->irq = gpio_to_irq(ts->pdata->irq_gpio);
++
++		dev_info(&ts->client->dev, "INT num %d, trigger type:%d\n",
++			 ts->client->irq, ts->pdata->irq_flags);
++		ret = request_threaded_irq(ts->client->irq, NULL,
++				gtp_irq_handler,
++				ts->pdata->irq_flags | IRQF_ONESHOT,
++				ts->client->name,
++				ts);
++		if (ret < 0) {
++			dev_err(&ts->client->dev,
++				"Failed to request irq %d\n", ts->client->irq);
++			return ret;
++		}
++	} else { /* use hrtimer */
++		dev_info(&ts->client->dev, "No hardware irq, use hrtimer\n");
++		hrtimer_init(&ts->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
++		ts->timer.function = gtp_timer_handler;
++		hrtimer_start(&ts->timer,
++			      ktime_set(0, (GTP_POLL_TIME + 6) * 1000000),
++			      HRTIMER_MODE_REL);
++		set_bit(HRTIMER_USED, &ts->flags);
++		ret = 0;
++	}
++	return ret;
++}
++
++static s8 gtp_request_input_dev(struct goodix_ts_data *ts)
++{
++	s8 ret = -1;
++	u8 index = 0;
++
++	ts->input_dev = input_allocate_device();
++	if (!ts->input_dev) {
++		dev_err(&ts->client->dev, "Failed to allocate input device\n");
++		return -ENOMEM;
++	}
++
++	ts->input_dev->evbit[0] = BIT_MASK(EV_SYN) | BIT_MASK(EV_KEY)
++		| BIT_MASK(EV_ABS);
++	if (!ts->pdata->type_a_report) {
++		input_mt_init_slots(ts->input_dev, 16, INPUT_MT_DIRECT);
++		dev_info(&ts->client->dev, "Use slot report protocol\n");
++	} else {
++		__set_bit(INPUT_PROP_DIRECT, ts->input_dev->propbit);
++		__set_bit(BTN_TOUCH, ts->input_dev->keybit);
++		dev_info(&ts->client->dev, "Use type A report protocol\n");
++	}
++
++	input_set_capability(ts->input_dev, EV_KEY, GTP_PEN_BUTTON1);
++	input_set_capability(ts->input_dev, EV_KEY, GTP_PEN_BUTTON2);
++
++	/* touch key register */
++	for (index = 0; index < ts->pdata->key_nums; index++)
++		input_set_capability(ts->input_dev, EV_KEY,
++				     ts->pdata->key_map[index]);
++
++	if (ts->pdata->slide_wakeup)
++		input_set_capability(ts->input_dev, EV_KEY, KEY_POWER);
++
++	if (ts->pdata->swap_x2y)
++		GTP_SWAP(ts->pdata->abs_size_x, ts->pdata->abs_size_y);
++
++	input_set_abs_params(ts->input_dev, ABS_MT_POSITION_X, 0,
++			     ts->pdata->abs_size_x, 0, 0);
++	input_set_abs_params(ts->input_dev, ABS_MT_POSITION_Y, 0,
++			     ts->pdata->abs_size_y, 0, 0);
++	input_set_abs_params(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0,
++			     ts->pdata->max_touch_width, 0, 0);
++	input_set_abs_params(ts->input_dev, ABS_MT_PRESSURE, 0,
++			     ts->pdata->max_touch_pressure, 0, 0);
++	input_set_abs_params(ts->input_dev, ABS_MT_TRACKING_ID, 0,
++			     ts->pdata->max_touch_id, 0, 0);
++	if (!ts->pdata->type_a_report) {
++		input_set_abs_params(ts->input_dev, ABS_MT_TOOL_TYPE,
++				     0, MT_TOOL_MAX, 0, 0);
++	} else {
++		__set_bit(BTN_TOOL_PEN, ts->input_dev->keybit);
++		__set_bit(BTN_TOOL_FINGER, ts->input_dev->keybit);
++	}
++
++	ts->input_dev->name = goodix_ts_name;
++	ts->input_dev->phys = goodix_input_phys;
++	ts->input_dev->id.bustype = BUS_I2C;
++	ts->input_dev->id.vendor = 0xDEAD;
++	ts->input_dev->id.product = 0xBEEF;
++	ts->input_dev->id.version = 10427;
++
++	ret = input_register_device(ts->input_dev);
++	if (ret) {
++		dev_err(&ts->client->dev, "Register %s input device failed\n",
++			ts->input_dev->name);
++		input_free_device(ts->input_dev);
++		return -ENODEV;
++	}
++
++	return 0;
++}
++
++/*
++ * Devices Tree support
++ */
++#ifdef CONFIG_OF
++static void gtp_parse_dt_coords(struct device *dev,
++				struct goodix_ts_platform_data *pdata)
++{
++	struct device_node *np = dev->of_node;
++	int ret;
++
++	ret = of_property_read_u32(np, "touchscreen-max-id",
++				   &pdata->max_touch_id);
++	if (ret || pdata->max_touch_id > GTP_MAX_TOUCH_ID) {
++		dev_info(dev, "Unset touchscreen-max-id, use default\n");
++		pdata->max_touch_id = GTP_MAX_TOUCH_ID;
++	}
++
++	ret = of_property_read_u32(np, "touchscreen-size-x",
++				   &pdata->abs_size_x);
++	if (ret) {
++		dev_info(dev, "Unset touchscreen-size-x, use default\n");
++		pdata->abs_size_x = GTP_DEFAULT_MAX_X;
++	}
++
++	ret = of_property_read_u32(np, "touchscreen-size-y",
++				   &pdata->abs_size_y);
++	if (ret) {
++		dev_info(dev, "Unset touchscreen-size-y, use default\n");
++		pdata->abs_size_y = GTP_DEFAULT_MAX_Y;
++	}
++
++	ret = of_property_read_u32(np, "touchscreen-max-w",
++				   &pdata->max_touch_width);
++	if (ret) {
++		dev_info(dev, "Unset touchscreen-max-w, use default\n");
++		pdata->max_touch_width = GTP_DEFAULT_MAX_WIDTH;
++	}
++
++	ret = of_property_read_u32(np, "touchscreen-max-p",
++				   &pdata->max_touch_pressure);
++	if (ret) {
++		dev_info(dev, "Unset touchscreen-max-p, use default\n");
++		pdata->max_touch_pressure = GTP_DEFAULT_MAX_PRESSURE;
++	}
++	dev_info(dev, "touch input parameters is [id x y w p]<%d %d %d %d %d>\n",
++		 pdata->max_touch_id, pdata->abs_size_x, pdata->abs_size_y,
++		 pdata->max_touch_width, pdata->max_touch_pressure);
++}
++
++static int gtp_parse_dt(struct device *dev,
++			struct goodix_ts_platform_data *pdata)
++{
++	int ret;
++	u32  key_nums;
++	struct property *prop;
++	u32 key_map[MAX_KEY_NUMS];
++	struct device_node *np = dev->of_node;
++
++	gtp_parse_dt_coords(dev, pdata);
++
++	ret = of_property_read_u32(np, "irq-flags",
++				   &pdata->irq_flags);
++	if (ret) {
++		dev_info(dev,
++			 "Failed get int-trigger-type from dts,set default\n");
++		pdata->irq_flags = GTP_DEFAULT_INT_TRIGGER;
++	}
++	of_property_read_u32(np, "goodix,int-sync", &pdata->int_sync);
++	if (pdata->int_sync)
++		dev_info(dev, "int-sync enabled\n");
++
++	of_property_read_u32(np, "goodix,driver-send-cfg",
++			     &pdata->driver_send_cfg);
++	if (pdata->driver_send_cfg)
++		dev_info(dev, "driver-send-cfg enabled\n");
++
++	of_property_read_u32(np, "goodix,swap-x2y", &pdata->swap_x2y);
++	if (pdata->swap_x2y)
++		dev_info(dev, "swap-x2y enabled\n");
++
++	of_property_read_u32(np, "goodix,slide-wakeup", &pdata->slide_wakeup);
++	if (pdata->slide_wakeup)
++		dev_info(dev, "slide-wakeup enabled\n");
++
++	of_property_read_u32(np, "goodix,auto-update", &pdata->auto_update);
++	if (pdata->auto_update)
++		dev_info(dev, "auto-update enabled\n");
++
++	of_property_read_u32(np, "goodix,auto-update-cfg",
++			     &pdata->auto_update_cfg);
++	if (pdata->auto_update_cfg)
++		dev_info(dev, "auto-update-cfg enabled\n");
++
++	of_property_read_u32(np, "goodix,esd-protect", &pdata->esd_protect);
++	if (pdata->esd_protect)
++		dev_info(dev, "esd-protect enabled\n");
++
++	of_property_read_u32(np, "goodix,type-a-report",
++			     &pdata->type_a_report);
++	if (pdata->type_a_report)
++		dev_info(dev, "type-a-report enabled\n");
++
++	of_property_read_u32(np, "goodix,resume-in-workqueue",
++			     &pdata->resume_in_workqueue);
++	if (pdata->resume_in_workqueue)
++		dev_info(dev, "resume-in-workqueue enabled\n");
++
++	of_property_read_u32(np, "goodix,power-off-sleep",
++			     &pdata->power_off_sleep);
++	if (pdata->power_off_sleep)
++		dev_info(dev, "power-off-sleep enabled\n");
++
++	of_property_read_u32(np, "goodix,pen-suppress-finger",
++			     &pdata->pen_suppress_finger);
++	if (pdata->pen_suppress_finger)
++		dev_info(dev, "pen-suppress-finger enabled\n");
++
++	prop = of_find_property(np, "touchscreen-key-map", NULL);
++	if (prop) {
++		key_nums = prop->length / sizeof(key_map[0]);
++		key_nums = key_nums > MAX_KEY_NUMS ? MAX_KEY_NUMS : key_nums;
++
++		dev_dbg(dev, "key nums %d\n", key_nums);
++		ret = of_property_read_u32_array(np,
++				"touchscreen-key-map", key_map,
++				key_nums);
++		if (ret) {
++			dev_err(dev, "Unable to read key codes\n");
++			pdata->key_nums = 0;
++			memset(pdata->key_map, 0,
++			       MAX_KEY_NUMS * sizeof(pdata->key_map[0]));
++		}
++		pdata->key_nums = key_nums;
++		memcpy(pdata->key_map, key_map,
++		       key_nums * sizeof(pdata->key_map[0]));
++		dev_info(dev, "key-map is [%x %x %x %x]\n",
++			 pdata->key_map[0], pdata->key_map[1],
++			 pdata->key_map[2], pdata->key_map[3]);
++	}
++
++	pdata->irq_gpio = of_get_named_gpio(np, "irq-gpios", 0);
++	if (!gpio_is_valid(pdata->irq_gpio))
++		dev_err(dev, "No valid irq gpio");
++
++	pdata->rst_gpio = of_get_named_gpio(np, "reset-gpios", 0);
++	if (!gpio_is_valid(pdata->rst_gpio))
++		dev_err(dev, "No valid rst gpio");
++
++	return 0;
++}
++
++/*******************************************************
++ * Function:
++ *	parse config data from devices tree.
++ * Input:
++ *	dev: device that this driver attached.
++ *	cfg: pointer of the config array.
++ *	cfg_len: pointer of the config length.
++ *	sid: sensor id.
++ * Output:
++ *	Executive outcomes.
++ *		0-succeed, -1-faileds.
++ *******************************************************/
++int gtp_parse_dt_cfg(struct device *dev, u8 *cfg, int *cfg_len, u8 sid)
++{
++	struct device_node *np = dev->of_node;
++	struct property *prop;
++	char cfg_name[18];
++	int ret;
++
++	snprintf(cfg_name, sizeof(cfg_name), "goodix,cfg-group%d", sid);
++	prop = of_find_property(np, cfg_name, cfg_len);
++
++	if (!prop || !prop->value || *cfg_len == 0 ||
++	    *cfg_len > GTP_CONFIG_MAX_LENGTH) {
++		*cfg_len = 0;
++		ret = -EPERM;/* failed */
++	} else {
++		memcpy(cfg, prop->value, *cfg_len);
++		ret = 0;
++	}
++
++	return ret;
++}
++
++#endif
++
++static int gtp_power_on(struct goodix_ts_data *ts)
++{
++	int ret = 0;
++
++	if (ts->vdd_ana) {
++		ret = regulator_enable(ts->vdd_ana);
++		if (ret) {
++			dev_err(&ts->client->dev,
++				"Regulator vdd enable failed ret=%d\n",
++				ret);
++			goto err_enable_vdd_ana;
++		}
++	}
++
++	if (ts->vcc_i2c) {
++		ret = regulator_enable(ts->vcc_i2c);
++		if (ret) {
++			dev_err(&ts->client->dev,
++				"Regulator vcc_i2c enable failed ret=%d\n",
++				ret);
++			goto err_enable_vcc_i2c;
++		}
++	}
++	clear_bit(POWER_OFF_MODE, &ts->flags);
++	return 0;
++
++err_enable_vcc_i2c:
++	if (ts->vdd_ana)
++		regulator_disable(ts->vdd_ana);
++err_enable_vdd_ana:
++	set_bit(POWER_OFF_MODE, &ts->flags);
++	return ret;
++}
++
++static int gtp_power_off(struct goodix_ts_data *ts)
++{
++	int ret = 0;
++
++	if (ts->vcc_i2c) {
++		set_bit(POWER_OFF_MODE, &ts->flags);
++		ret = regulator_disable(ts->vcc_i2c);
++		if (ret) {
++			dev_err(&ts->client->dev,
++				"Regulator vcc_i2c disable failed ret=%d\n",
++				ret);
++			goto err_disable_vcc_i2c;
++		}
++		dev_info(&ts->client->dev,
++			 "Regulator vcc_i2c disabled\n");
++	}
++
++	if (ts->vdd_ana) {
++		set_bit(POWER_OFF_MODE, &ts->flags);
++		ret = regulator_disable(ts->vdd_ana);
++		if (ret) {
++			dev_err(&ts->client->dev,
++					"Regulator vdd disable failed ret=%d\n",
++					ret);
++			goto err_disable_vdd_ana;
++		}
++		dev_info(&ts->client->dev,
++			 "Regulator vdd_ana disabled\n");
++	}
++	return ret;
++
++err_disable_vdd_ana:
++	if (ts->vcc_i2c)
++		ret = regulator_enable(ts->vcc_i2c);
++err_disable_vcc_i2c:
++	clear_bit(POWER_OFF_MODE, &ts->flags);
++	return ret;
++}
++
++static int gtp_power_init(struct goodix_ts_data *ts)
++{
++	int ret;
++
++	ts->vdd_ana = regulator_get(&ts->client->dev, "vdd_ana");
++	if (IS_ERR(ts->vdd_ana)) {
++		ts->vdd_ana = NULL;
++		ret = PTR_ERR(ts->vdd_ana);
++		dev_info(&ts->client->dev,
++			 "Regulator get failed vdd ret=%d\n", ret);
++	}
++
++	ts->vcc_i2c = regulator_get(&ts->client->dev, "vcc_i2c");
++	if (IS_ERR(ts->vcc_i2c)) {
++		ts->vcc_i2c = NULL;
++		ret = PTR_ERR(ts->vcc_i2c);
++		dev_info(&ts->client->dev,
++			 "Regulator get failed vcc_i2c ret=%d\n", ret);
++	}
++	return 0;
++}
++
++static int gtp_power_deinit(struct goodix_ts_data *ts)
++{
++	if (ts->vdd_ana)
++		regulator_put(ts->vdd_ana);
++	if (ts->vcc_i2c)
++		regulator_put(ts->vcc_i2c);
++
++	return 0;
++}
++
++static void gtp_shutdown(struct i2c_client *client)
++{
++	struct goodix_ts_data *data = i2c_get_clientdata(client);
++
++	if (!data->init_done)
++		return;
++
++	gtp_work_control_enable(data, false);
++	gtp_power_off(data);
++
++	return;
++}
++
++static int gtp_probe(struct i2c_client *client, const struct i2c_device_id *id)
++{
++	int ret = -1;
++	struct goodix_ts_data *ts;
++	struct goodix_ts_platform_data *pdata;
++
++	/* do NOT remove these logs */
++	dev_info(&client->dev, "GTP Driver Version: %s\n", GTP_DRIVER_VERSION);
++	dev_info(&client->dev, "GTP I2C Address: 0x%02x\n", client->addr);
++
++	i2c_connect_client = client;
++	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
++		dev_err(&client->dev, "Failed check I2C functionality");
++		return -ENODEV;
++	}
++
++	ts = devm_kzalloc(&client->dev, sizeof(*ts), GFP_KERNEL);
++	if (!ts) {
++		dev_err(&client->dev, "Failed alloc ts memory");
++		return -ENOMEM;
++	}
++
++	pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
++	if (!pdata) {
++		dev_err(&client->dev, "Failed alloc pdata memory\n");
++		devm_kfree(&client->dev, ts);
++		return -EINVAL;
++	}
++
++	ts->init_done = false;
++
++#ifdef CONFIG_OF
++	if (client->dev.of_node) {
++		ret = gtp_parse_dt(&client->dev, pdata);
++		if (ret) {
++			dev_err(&client->dev, "Failed parse dts\n");
++			goto exit_free_client_data;
++		}
++	}
++#else
++	/* set parameters at here if you platform doesn't DTS */
++	pdata->rst_gpio = GTP_RST_PORT;
++	pdata->irq_gpio = GTP_INT_PORT;
++	pdata->slide_wakeup = false;
++	pdata->auto_update = true;
++	pdata->auto_update_cfg = false;
++	pdata->type_a_report = false;
++	pdata->esd_protect = false;
++	pdata->max_touch_id = GTP_MAX_TOUCH_ID;
++	pdata->abs_size_x = GTP_DEFAULT_MAX_X;
++	pdata->abs_size_y = GTP_DEFAULT_MAX_Y;
++	pdata->max_touch_width = GTP_DEFAULT_MAX_WIDTH;
++	pdata->max_touch_pressure = GTP_DEFAULT_MAX_PRESSURE;
++#endif
++
++	ts->client = client;
++	ts->pdata = pdata;
++
++	i2c_set_clientdata(client, ts);
++
++	ret = gtp_power_init(ts);
++	if (ret) {
++		dev_err(&client->dev, "Failed get regulator\n");
++		ret = -EINVAL;
++		goto exit_free_client_data;
++	}
++
++	ret = gtp_power_on(ts);
++	if (ret) {
++		dev_err(&client->dev, "Failed power on device\n");
++		ret = -EINVAL;
++		goto exit_deinit_power;
++	}
++
++	ret = gtp_pinctrl_init(ts);
++	if (ret < 0) {
++		/* if define pinctrl must define the following state
++		 * to let int-pin work normally: default, int_output_high,
++		 * int_output_low, int_input
++		 */
++		dev_err(&client->dev, "Failed get wanted pinctrl state\n");
++		goto exit_deinit_power;
++	}
++
++	ret = gtp_request_io_port(ts);
++	if (ret < 0) {
++		dev_err(&client->dev, "Failed request IO port\n");
++		goto exit_power_off;
++	}
++
++	gtp_reset_guitar(ts->client, 20);
++
++	/* During the first initialization, the input status is configured
++	 * to ensure that no abnormal interrupt will be triggered when the
++	 * screen is not connected.
++	 */
++	pinctrl_select_state(ts->pinctrl.pinctrl, ts->pinctrl.default_sta);
++
++	ret = gtp_i2c_test(client);
++	if (ret) {
++		dev_err(&client->dev, "Failed communicate with IC use I2C\n");
++		goto exit_free_io_port;
++	}
++
++	dev_info(&client->dev, "I2C Addr is %x\n", client->addr);
++
++	ret = gtp_get_fw_info(client, &ts->fw_info);
++	if (ret < 0) {
++		dev_err(&client->dev, "Failed read FW version\n");
++		goto exit_free_io_port;
++	}
++
++	pdata->config.data[0] = GTP_REG_CONFIG_DATA >> 8;
++	pdata->config.data[1] = GTP_REG_CONFIG_DATA & 0xff;
++	ret = gtp_init_panel(ts);
++	if (ret < 0)
++		dev_info(&client->dev, "Panel un-initialize\n");
++
++#ifdef CONFIG_TOUCHSCREEN_GT9XX_UPDATE
++	if (ts->pdata->auto_update) {
++		ret = gup_init_update_proc(ts);
++		if (ret < 0)
++			dev_err(&client->dev, "Failed create update thread\n");
++	}
++#endif
++	ret = gtp_request_input_dev(ts);
++	if (ret < 0) {
++		dev_err(&client->dev, "Failed request input device\n");
++		goto exit_power_off;
++	}
++	mutex_init(&ts->lock);
++	ret = gtp_request_irq(ts);
++	if (ret < 0) {
++		dev_err(&client->dev, "Failed create work thread");
++		goto exit_unreg_input_dev;
++	}
++
++	gtp_work_control_enable(ts, false);
++	if (ts->pdata->slide_wakeup) {
++		dev_info(&client->dev, "slide wakeup enabled\n");
++		ret = enable_irq_wake(client->irq);
++		if (ret < 0)
++			dev_err(&client->dev, "Failed set irq wake\n");
++	}
++
++	gtp_register_powermanager(ts);
++
++	ret = gtp_create_file(ts);
++	if (ret) {
++		dev_info(&client->dev, "Failed create attributes file");
++		goto exit_powermanager;
++	}
++
++#ifdef CONFIG_TOUCHSCREEN_GT9XX_TOOL
++	init_wr_node(client);/*TODO judge return value */
++#endif
++
++	gtp_esd_init(ts);
++	gtp_esd_on(ts);
++	/* probe init finished */
++	ts->init_done = true;
++	gtp_work_control_enable(ts, true);
++
++	return 0;
++
++exit_powermanager:
++	gtp_unregister_powermanager(ts);
++exit_unreg_input_dev:
++	input_unregister_device(ts->input_dev);
++exit_free_io_port:
++	if (gpio_is_valid(ts->pdata->rst_gpio))
++		gpio_free(ts->pdata->rst_gpio);
++	if (gpio_is_valid(ts->pdata->irq_gpio))
++		gpio_free(ts->pdata->irq_gpio);
++exit_power_off:
++	gtp_power_off(ts);
++	gtp_pinctrl_deinit(ts);
++exit_deinit_power:
++	gtp_power_deinit(ts);
++exit_free_client_data:
++	devm_kfree(&client->dev, pdata);
++	devm_kfree(&client->dev, ts);
++	i2c_set_clientdata(client, NULL);
++
++	return ret;
++}
++
++static int gtp_drv_remove(struct i2c_client *client)
++{
++	struct goodix_ts_data *ts = i2c_get_clientdata(client);
++
++	gtp_work_control_enable(ts, false);
++	gtp_unregister_powermanager(ts);
++
++	remove_proc_entry(GT91XX_CONFIG_PROC_FILE, gtp_config_proc);
++
++	sysfs_remove_group(&client->dev.kobj, &gtp_attr_group);
++
++#ifdef CONFIG_TOUCHSCREEN_GT9XX_TOOL
++	uninit_wr_node();
++#endif
++
++	if (ts->pdata->esd_protect)
++		gtp_esd_off(ts);
++
++	/* TODO: how to judge a irq numbers validity */
++	if (ts->client->irq)
++		free_irq(client->irq, ts);
++	else
++		hrtimer_cancel(&ts->timer);
++
++	if (gpio_is_valid(ts->pdata->rst_gpio))
++		gpio_free(ts->pdata->rst_gpio);
++
++	if (gpio_is_valid(ts->pdata->irq_gpio))
++		gpio_free(ts->pdata->irq_gpio);
++
++	gtp_power_off(ts);
++	gtp_power_deinit(ts);
++	gtp_pinctrl_deinit(ts);
++	dev_info(&client->dev, "goodix ts driver removed");
++	i2c_set_clientdata(client, NULL);
++	input_unregister_device(ts->input_dev);
++	mutex_destroy(&ts->lock);
++
++	devm_kfree(&client->dev, ts->pdata);
++	devm_kfree(&client->dev, ts);
++
++	return 0;
++}
++
++static void gtp_suspend(struct goodix_ts_data *ts)
++{
++	int ret = -1;
++
++	if (test_bit(FW_UPDATE_RUNNING, &ts->flags)) {
++		dev_warn(&ts->client->dev,
++			 "Fw upgrade in progress, can't go to suspend\n");
++		return;
++	}
++
++	if (test_and_set_bit(SLEEP_MODE, &ts->flags)) {
++		dev_info(&ts->client->dev, "Already in suspend state\n");
++		return;
++	}
++
++	dev_dbg(&ts->client->dev, "Try enter suspend mode\n");
++
++	gtp_esd_off(ts);
++	gtp_work_control_enable(ts, false);
++	if (ts->pdata->slide_wakeup) {
++		ret = gtp_enter_doze(ts);
++		gtp_work_control_enable(ts, true);
++	} else if (ts->pdata->power_off_sleep) {
++		/*TODO: power off routine */
++		gtp_power_off(ts);
++		ret = SUCCESS;
++	} else {
++		ret = gtp_enter_sleep(ts);
++	}
++
++	if (ret < 0)
++		dev_err(&ts->client->dev, "Failed enter suspend\n");
++
++	/*  to avoid waking up while not sleeping */
++	/*	delay 48 + 10ms to ensure reliability */
++	msleep(GTP_58_DLY_MS);
++}
++
++static int gtp_gesture_wakeup(struct goodix_ts_data *ts)
++{
++	int ret;
++	int retry = 10;
++
++	do {
++		gtp_reset_guitar(ts->client, 10);
++		ret = gtp_i2c_test(ts->client);
++		if (!ret)
++			break;
++	} while (--retry);
++
++	if (!retry)
++		ret = -EIO;
++
++	clear_bit(DOZE_MODE, &ts->flags);
++	return ret;
++}
++
++static void gtp_resume(struct goodix_ts_data *ts)
++{
++	int ret = 0;
++
++	if (test_bit(FW_UPDATE_RUNNING, &ts->flags)) {
++		dev_info(&ts->client->dev,
++			 "Fw upgrade in progress, can't do resume\n");
++		return;
++	}
++
++	if (!test_bit(SLEEP_MODE, &ts->flags)) {
++		dev_dbg(&ts->client->dev, "Already in awake state\n");
++		return;
++	}
++
++	dev_info(&ts->client->dev, "Try resume from sleep mode\n");
++
++	gtp_work_control_enable(ts, false);
++
++	if (ts->pdata->slide_wakeup && test_bit(DOZE_MODE, &ts->flags)) {
++		ret = gtp_gesture_wakeup(ts);
++		if (ret)
++			dev_warn(&ts->client->dev, "Failed wake up from gesture mode\n");
++	} else if (ts->pdata->power_off_sleep) {
++		ret = gtp_power_on(ts);
++		if (ret) {
++			dev_warn(&ts->client->dev, "Failed wake up from gesture mode\n");
++		} else {
++			gtp_reset_guitar(ts->client, 20);
++			ret = gtp_i2c_test(ts->client);
++			if (ret)
++				dev_warn(&ts->client->dev,
++					 "I2C communicate failed after power on\n");
++		}
++	} else {
++		gtp_reset_guitar(ts->client, 20);
++		ret = gtp_wakeup_sleep(ts);
++		if (ret)
++			dev_warn(&ts->client->dev,
++				 "Failed wakeup from sleep mode\n");
++	}
++
++	if (ret)
++		dev_warn(&ts->client->dev, "Later resume failed\n");
++	else
++		gtp_esd_on(ts);
++
++	clear_bit(SLEEP_MODE, &ts->flags);
++	gtp_work_control_enable(ts, true);
++}
++#if 0
++#if defined(CONFIG_FB)
++static void fb_notify_resume_work(struct work_struct *work)
++{
++	struct goodix_ts_data *ts =
++		container_of(work, struct goodix_ts_data, fb_notify_work);
++	dev_info(&ts->client->dev, "try resume in workqueue\n");
++	gtp_resume(ts);
++}
++
++/* frame buffer notifier block control the suspend/resume procedure */
++static int gtp_fb_notifier_callback(struct notifier_block *noti,
++				    unsigned long event, void *data)
++{
++	struct fb_event *ev_data = data;
++	struct goodix_ts_data *ts = container_of(noti,
++			struct goodix_ts_data, notifier);
++	int *blank;
++
++	if (ev_data && ev_data->data && event == FB_EVENT_BLANK && ts) {
++		blank = ev_data->data;
++		if (*blank == FB_BLANK_UNBLANK ||
++		    *blank == FB_BLANK_NORMAL) {
++			dev_dbg(&ts->client->dev, "ts_resume");
++			if (ts->pdata->resume_in_workqueue)
++				schedule_work(&ts->fb_notify_work);
++			else
++				gtp_resume(ts);
++		} else if (*blank == FB_BLANK_POWERDOWN) {
++			dev_dbg(&ts->client->dev, "ts_suspend");
++			if (ts->pdata->resume_in_workqueue)
++				flush_work(&ts->fb_notify_work);
++			gtp_suspend(ts);
++		}
++	}
++
++	return 0;
++}
++
++#endif
++#endif
++
++#if defined(CONFIG_PM)
++static int gtp_pm_suspend(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct goodix_ts_data *ts = i2c_get_clientdata(client);
++
++	if (ts) {
++		dev_dbg(&ts->client->dev, "Suspend by i2c pm.");
++		gtp_suspend(ts);
++	}
++
++	return 0;
++}
++
++static int gtp_pm_resume(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct goodix_ts_data *ts = i2c_get_clientdata(client);
++
++	if (ts) {
++		dev_dbg(&ts->client->dev, "Resume by i2c pm.");
++		gtp_resume(ts);
++	}
++
++	return 0;
++}
++
++static const struct dev_pm_ops gtp_pm_ops = {
++	.suspend = gtp_pm_suspend,
++	.resume  = gtp_pm_resume,
++};
++
++#elif defined(CONFIG_HAS_EARLYSUSPEND)
++static void gtp_early_suspend(struct early_suspend *h)
++{
++	struct goodix_ts_data *ts = container_of(h,
++			struct goodix_ts_data, early_suspend);
++
++	if (ts) {
++		dev_dbg(&ts->client->dev, "Suspend by earlysuspend module.");
++		gtp_suspend(ts);
++	}
++}
++
++static void gtp_late_resume(struct early_suspend *h)
++{
++	struct goodix_ts_data *ts = container_of(h,
++			struct goodix_ts_data, early_suspend);
++
++	if (ts) {
++		dev_dbg(&ts->client->dev, "Resume by earlysuspend module.");
++		gtp_resume(ts);
++	}
++}
++#endif
++
++static int gtp_register_powermanager(struct goodix_ts_data *ts)
++{
++	int ret;
++#if defined(CONFIG_FB)
++/*	INIT_WORK(&ts->fb_notify_work, fb_notify_resume_work);
++	ts->notifier.notifier_call = gtp_fb_notifier_callback;
++	ret = fb_register_client(&ts->notifier);
++	if (ret)
++		dev_err(&ts->client->dev,
++			"Unable to register fb_notifier: %d\n", ret);
++*/
++#elif defined(CONFIG_HAS_EARLYSUSPEND)
++	ts->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1;
++	ts->early_suspend.suspend = goodix_ts_early_suspend;
++	ts->early_suspend.resume = goodix_ts_late_resume;
++	register_early_suspend(&ts->early_suspend);
++#endif
++
++	return ret;
++}
++
++static int gtp_unregister_powermanager(struct goodix_ts_data *ts)
++{
++#if defined(CONFIG_FB)
++		fb_unregister_client(&ts->notifier);
++#elif defined(CONFIG_HAS_EARLYSUSPEND)
++		unregister_early_suspend(&ts->early_suspend);
++#endif
++
++	return 0;
++}
++
++/*******************************************************
++ * Function:
++ *	Initialize external watchdog for esd protect
++ * Input:
++ *	client: i2c device.
++ * Output:
++ *	result of i2c write operation.
++ *		0: succeed, otherwise: failed
++ ********************************************************/
++static int gtp_init_ext_watchdog(struct i2c_client *client)
++{
++	int ret;
++	u8 opr_buffer[3] = { (u8)(GTP_REG_ESD_CHECK >> 8),
++			     (u8)GTP_REG_ESD_CHECK,
++			     (u8)GTP_ESD_CHECK_VALUE };
++
++	dev_dbg(&client->dev, "[Esd]Init external watchdog\n");
++	ret = gtp_i2c_write(client, opr_buffer, 3);
++	if (ret == 1)
++		return 0;
++
++	dev_err(&client->dev, "Failed init ext watchdog\n");
++	return -EINVAL;
++}
++
++static void gtp_esd_check_func(struct work_struct *work)
++{
++	s32 i;
++	s32 ret = -1;
++	u8 esd_buf[5] = { (u8)(GTP_REG_COMMAND >> 8), (u8)GTP_REG_COMMAND };
++	struct delayed_work *dwork = to_delayed_work(work);
++	struct goodix_ts_esd *ts_esd = container_of(dwork, struct goodix_ts_esd,
++						    delayed_work);
++	struct goodix_ts_data *ts = container_of(ts_esd, struct goodix_ts_data,
++						 ts_esd);
++
++	if (test_bit(SLEEP_MODE, &ts->flags) ||
++	    test_bit(FW_UPDATE_RUNNING, &ts->flags)) {
++		dev_dbg(&ts->client->dev,
++			"Esd cancled by power_suspend or fw_update!");
++		return;
++	}
++
++	if (ts_esd->esd_on == false)
++		return;
++
++	for (i = 0; i < 3; i++) {
++		ret = gtp_i2c_read(ts->client, esd_buf, 4);
++		if (ret < 0)
++			continue;
++
++		dev_dbg(&ts->client->dev,
++			"[Esd]0x8040 = 0x%02X, 0x8041 = 0x%02X",
++			esd_buf[2], esd_buf[3]);
++		if (esd_buf[2] == (u8)GTP_ESD_CHECK_VALUE ||
++		    esd_buf[3] != (u8)GTP_ESD_CHECK_VALUE) {
++			gtp_i2c_read(ts->client, esd_buf, 4);
++			if (ret < 0)
++				continue;
++
++			if (esd_buf[2] == (u8)GTP_ESD_CHECK_VALUE ||
++			    esd_buf[3] != (u8)GTP_ESD_CHECK_VALUE) {
++				i = 3;
++				break;
++			}
++		} else {
++			/* IC works normally, Write 0x8040 0xAA, feed the dog */
++			esd_buf[2] = (u8)GTP_ESD_CHECK_VALUE;
++			gtp_i2c_write(ts->client, esd_buf, 3);
++			break;
++		}
++	}
++	if (i >= 3) {
++		dev_err(&ts->client->dev, "IC working abnormally! Reset IC\n");
++		esd_buf[0] = 0x42;
++		esd_buf[1] = 0x26;
++		esd_buf[2] = 0x01;
++		esd_buf[3] = 0x01;
++		esd_buf[4] = 0x01;
++		gtp_i2c_write(ts->client, esd_buf, 5);
++		/* TODO: Is power off really need? */
++		msleep(GTP_50_DLY_MS);
++		gtp_power_off(ts);
++		msleep(GTP_20_DLY_MS);
++		gtp_power_on(ts);
++		msleep(GTP_20_DLY_MS);
++
++		gtp_reset_guitar(ts->client, 50);
++		msleep(GTP_50_DLY_MS);
++		gtp_send_cfg(ts->client);
++	}
++
++	if (ts_esd->esd_on == true && !test_bit(SLEEP_MODE, &ts->flags)) {
++		schedule_delayed_work(&ts_esd->delayed_work, 2 * HZ);
++		dev_dbg(&ts->client->dev, "ESD work rescheduled\n");
++	}
++}
++
++static int gtp_esd_init(struct goodix_ts_data *ts)
++{
++	struct goodix_ts_esd *ts_esd = &ts->ts_esd;
++
++	INIT_DELAYED_WORK(&ts_esd->delayed_work, gtp_esd_check_func);
++	mutex_init(&ts_esd->mutex);
++	ts_esd->esd_on = false;
++
++	return 0;
++}
++
++void gtp_esd_on(struct goodix_ts_data *ts)
++{
++	struct goodix_ts_esd *ts_esd = &ts->ts_esd;
++
++	if (!ts->pdata->esd_protect)
++		return;
++	mutex_lock(&ts_esd->mutex);
++	if (ts_esd->esd_on == false) {
++		ts_esd->esd_on = true;
++		schedule_delayed_work(&ts_esd->delayed_work, 2 * HZ);
++		dev_info(&ts->client->dev, "ESD on");
++	}
++	mutex_unlock(&ts_esd->mutex);
++}
++
++void gtp_esd_off(struct goodix_ts_data *ts)
++{
++	struct goodix_ts_esd *ts_esd = &ts->ts_esd;
++
++	if (!ts->pdata->esd_protect)
++		return;
++	mutex_lock(&ts_esd->mutex);
++	if (ts_esd->esd_on == true) {
++		ts_esd->esd_on = false;
++		cancel_delayed_work_sync(&ts_esd->delayed_work);
++		dev_info(&ts->client->dev, "ESD off");
++	}
++	mutex_unlock(&ts_esd->mutex);
++}
++
++#ifdef CONFIG_OF
++static const struct of_device_id gtp_match_table[] = {
++	{.compatible = "goodix,gt9xx",},
++	{ },
++};
++#endif
++
++static const struct i2c_device_id gtp_device_id[] = {
++	{ GTP_I2C_NAME, 0 },
++	{ }
++};
++
++static struct i2c_driver goodix_ts_driver = {
++	.probe		= gtp_probe,
++	.remove		= gtp_drv_remove,
++	.id_table	= gtp_device_id,
++	.shutdown	= gtp_shutdown,
++	.driver = {
++		.name	  = GTP_I2C_NAME,
++		.owner	  = THIS_MODULE,
++#ifdef CONFIG_OF
++		.of_match_table = gtp_match_table,
++#endif
++#if defined(CONFIG_PM)
++		.pm		  = &gtp_pm_ops,
++#endif
++	},
++};
++
++static int __init gtp_init(void)
++{
++	s32 ret;
++
++	pr_info("Gt9xx driver installing..\n");
++	ret = i2c_add_driver(&goodix_ts_driver);
++
++	return ret;
++}
++
++static void __exit gtp_exit(void)
++{
++	pr_info("Gt9xx driver exited\n");
++	i2c_del_driver(&goodix_ts_driver);
++}
++
++module_init(gtp_init);
++module_exit(gtp_exit);
++
++MODULE_DESCRIPTION("GT9 serials touch controller Driver");
++MODULE_LICENSE("GPL v2");
++
+diff --git a/module_drivers/drivers/input/touchscreen/gt9xx_touch/gt9xx.h b/module_drivers/drivers/input/touchscreen/gt9xx_touch/gt9xx.h
+new file mode 100644
+index 000000000..2e1c66587
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/gt9xx_touch/gt9xx.h
+@@ -0,0 +1,384 @@
++/*
++ * Goodix GT9xx touchscreen driver
++ *
++ * Copyright  (C)  2016 - 2017 Goodix. Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be a reference
++ * to you, when you are integrating the GOODiX's CTP IC into your system,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * Version: 2.8.0.2
++ * Release Date: 2017/12/14
++ */
++
++#ifndef _GOODIX_GT9XX_H_
++#define _GOODIX_GT9XX_H_
++
++#include <linux/kernel.h>
++#include <linux/hrtimer.h>
++#include <linux/i2c.h>
++#include <linux/input.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/i2c.h>
++#include <linux/proc_fs.h>
++#include <linux/string.h>
++#include <linux/uaccess.h>
++#include <linux/vmalloc.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/gpio.h>
++#include <linux/regulator/consumer.h>
++#include <linux/major.h>
++#include <linux/kdev_t.h>
++#ifdef CONFIG_OF
++#include <linux/of_gpio.h>
++#endif
++#ifdef CONFIG_FB
++#include <linux/notifier.h>
++#include <linux/fb.h>
++#endif
++#ifdef CONFIG_HAS_EARLYSUSPEND
++#include <linux/earlysuspend.h>
++#endif
++#include <linux/usb.h>
++#include <linux/power_supply.h>
++
++#define GTP_TOOL_PEN	1
++#define GTP_TOOL_FINGER 2
++
++#define MAX_KEY_NUMS 4
++#define GTP_CONFIG_MAX_LENGTH 240
++#define GTP_ADDR_LENGTH       2
++
++/***************************PART1:ON/OFF define*******************************/
++#define GTP_DEBUG_ON          1
++#define GTP_DEBUG_ARRAY_ON    0
++#define GTP_DEBUG_FUNC_ON     0
++
++struct goodix_point_t {
++	int id;
++	int x;
++	int y;
++	int w;
++	int p;
++	int tool_type;
++};
++
++struct goodix_config_data {
++	int length;
++	u8 data[GTP_CONFIG_MAX_LENGTH + GTP_ADDR_LENGTH];
++};
++
++struct goodix_ts_platform_data {
++	int irq_gpio;
++	int rst_gpio;
++	u32 irq_flags;
++	u32 abs_size_x;
++	u32 abs_size_y;
++	u32 max_touch_id;
++	u32 max_touch_width;
++	u32 max_touch_pressure;
++	u32 key_map[MAX_KEY_NUMS];
++	u32 key_nums;
++	u32 int_sync;
++	u32 driver_send_cfg;
++	u32 swap_x2y;
++	u32 slide_wakeup;
++	u32 auto_update;
++	u32 auto_update_cfg;
++	u32 esd_protect;
++	u32 type_a_report;
++	u32 power_off_sleep;
++	u32 resume_in_workqueue;
++	u32 pen_suppress_finger;
++	struct goodix_config_data config;
++};
++
++struct goodix_ts_esd {
++	struct delayed_work delayed_work;
++	struct mutex mutex;
++	bool esd_on;
++};
++
++enum {
++	WORK_THREAD_ENABLED = 0,
++	HRTIMER_USED,
++	FW_ERROR,
++
++	DOZE_MODE,
++	SLEEP_MODE,
++	POWER_OFF_MODE,
++	RAW_DATA_MODE,
++
++	FW_UPDATE_RUNNING,
++	PANEL_RESETTING
++};
++
++struct goodix_pinctrl {
++	struct pinctrl *pinctrl;
++	struct pinctrl_state *default_sta;
++	struct pinctrl_state *int_out_high;
++	struct pinctrl_state *int_out_low;
++	struct pinctrl_state *int_input;
++};
++
++struct goodix_fw_info {
++	u8 pid[6];
++	u16 version;
++	u8 sensor_id;
++};
++
++struct goodix_ts_data {
++	unsigned long flags; /* This member record the device status */
++
++	struct goodix_ts_esd ts_esd;
++	struct i2c_client *client;
++	struct input_dev *input_dev;
++	struct input_dev *pen_dev;
++	struct goodix_ts_platform_data *pdata;
++	/* use pinctrl control int-pin output low or high */
++	struct goodix_pinctrl pinctrl;
++	struct hrtimer timer;
++	struct mutex lock;
++	struct notifier_block ps_notif;
++	struct regulator *vdd_ana;
++	struct regulator *vcc_i2c;
++#if defined(CONFIG_FB)
++	struct notifier_block notifier;
++	struct work_struct fb_notify_work;
++#elif defined(CONFIG_HAS_EARLYSUSPEND)
++	struct early_suspend early_suspend;
++#endif
++	struct goodix_fw_info fw_info;
++	bool force_update;
++	bool init_done;
++};
++
++/************************* PART2:TODO define *******************************/
++/* STEP_1(REQUIRED): Define Configuration Information Group(s)
++ Sensor_ID Map:
++	 sensor_opt1 sensor_opt2 Sensor_ID
++		GND         GND          0
++		VDDIO      GND          1
++		NC           GND          2
++		GND         NC/300K    3
++		VDDIO      NC/300K    4
++		NC           NC/300K    5
++*/
++/* TODO: define your own default or for Sensor_ID == 0 config here.
++	 The predefined one is just a sample config,
++	 which is not suitable for your tp in most cases. */
++#define CTP_CFG_GROUP0 {\
++	0x41, 0xD0, 0x02, 0x00, 0x05, 0x0A, 0x34, \
++	0x00, 0x01, 0x08, 0x28, 0x05, 0x50, 0x32, \
++	0x03, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, \
++	0x00, 0x00, 0x17, 0x19, 0x1E, 0x14, 0x8C, \
++	0x2D, 0x0E, 0x3C, 0x3E, 0x82, 0x0A, 0x82, \
++	0x0A, 0x00, 0x99, 0x33, 0x1D, 0x00, 0x00, \
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
++	0x00, 0x2B, 0x19, 0x64, 0x94, 0xC0, 0x02, \
++	0x08, 0x00, 0x00, 0x04,	0xF2, 0x1C, 0x00, \
++	0xB9, 0x26, 0x00, 0x93, 0x32, 0x00, 0x77, \
++	0x42, 0x00, 0x62, 0x57, 0x00, 0x62, 0x00, \
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
++	0x00, 0x00, 0x00, 0xFF, 0x65, 0x00, 0x00, \
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
++	0x19, 0x46, 0x00, 0x00, 0x00, 0x00, 0x32, \
++	0x1C, 0x1A, 0x18, 0x16, 0x14, 0x12, 0x10, \
++	0x0E, 0x0C, 0x0A, 0x08, 0x06, 0x04, 0x02, \
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
++	0x00, 0x00, 0x00, 0x02,	0x04, 0x06, 0x08, \
++	0x0A, 0x0C, 0x0F, 0x10, 0x12, 0x13, 0x14, \
++	0x18, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, \
++	0x22, 0x24, 0x26, 0x28, 0x29, 0x2A, 0xFF, \
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
++	0x00, 0x00, 0xB8, 0x01\
++}
++
++/* TODO: define your config for Sensor_ID == 1 here, if needed */
++#define CTP_CFG_GROUP1 {\
++}
++
++/* TODO: define your config for Sensor_ID == 2 here, if needed */
++#define CTP_CFG_GROUP2 {\
++}
++
++/* TODO: define your config for Sensor_ID == 3 here, if needed */
++#define CTP_CFG_GROUP3 {\
++}
++/* TODO: define your config for Sensor_ID == 4 here, if needed */
++#define CTP_CFG_GROUP4 {\
++	0x53,0xD0,0x02,0x00,0x05,0x05,0xF5,0xD5,0x21,0x48,0x2D,0x0F,\
++	0x5A,0x41,0x0E,0x05,0x00,0x00,0x32,0x32,0x20,0x00,0x05,0x14,\
++	0x14,0x1A,0x14,0x8B,0x2B,0x0C,0xB5,0xB7,0xEB,0x04,0xFF,0xFE,\
++	0x00,0x22,0x33,0x10,0x3C,0x80,0x00,0x00,0x00,0x1E,0x12,0x41,\
++	0x23,0x12,0x5A,0xAA,0xBE,0x4A,0x55,0x04,0x00,0x14,0x19,0x04,\
++	0x80,0xAB,0x00,0x7F,0xAF,0x64,0x7E,0xB3,0x00,0x7E,0xB7,0x00,\
++	0x7B,0xBB,0x3C,0x7B,0x08,0x30,0x00,0x00,0xF8,0x70,0x50,0xFF,\
++	0xFF,0x17,0x00,0x46,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1E,\
++	0x08,0x46,0x80,0x08,0x0A,0x00,0xA0,0x00,0x3C,0x28,0x19,0x19,\
++	0x80,0x11,0x00,0x00,0x18,0x16,0x14,0x12,0x10,0x0E,0x0C,0x0A,\
++	0x08,0x06,0x04,0x02,0xFF,0xFF,0x28,0x00,0x32,0x20,0x00,0x06,\
++	0x00,0x00,0x0A,0x06,0x10,0x08,0x0A,0x22,0xEB,0x04,0x26,0x24,\
++	0x22,0x21,0x20,0x1F,0x1E,0x1D,0x1C,0x18,0x16,0x12,0x10,0x0F,\
++	0x0C,0x0A,0x08,0x06,0x04,0x02,0x00,0x13,0xFF,0xFF,0xFF,0xFF,\
++	0x00,0x00,0x00,0x02,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,\
++	0x00,0x00,0x00,0x00,0x28,0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,\
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE6,0x10,0xEF,0x01\
++}
++
++/* TODO: define your config for Sensor_ID == 5 here, if needed */
++#define CTP_CFG_GROUP5 {\
++}
++
++/* STEP_2(REQUIRED): Customize your I/O ports & I/O operations */
++#define GTP_RST_PORT    64 /* EXYNOS4_GPX2(0) */
++#define GTP_INT_PORT    65 /* EXYNOS4_GPX2(1) */
++
++#define GTP_GPIO_AS_INPUT(pin)          (gpio_direction_input(pin))
++#define GTP_GPIO_AS_INT(pin)            (GTP_GPIO_AS_INPUT(pin))
++#define GTP_GPIO_GET_VALUE(pin)         gpio_get_value(pin)
++#define GTP_GPIO_OUTPUT(pin, level)      gpio_direction_output(pin, level)
++#define GTP_GPIO_REQUEST(pin, label)    gpio_request(pin, label)
++#define GTP_GPIO_FREE(pin)              gpio_free(pin)
++
++/* STEP_3(optional): Specify your special config info if needed */
++#define GTP_DEFAULT_MAX_X	 720    /* default coordinate max values */
++#define GTP_DEFAULT_MAX_Y	 1080
++#define GTP_DEFAULT_MAX_WIDTH	 1024
++#define GTP_DEFAULT_MAX_PRESSURE 1024
++#define GTP_DEFAULT_INT_TRIGGER	 1 /* 1 rising, 2 falling */
++#define GTP_MAX_TOUCH_ID	 16
++
++/* STEP_4(optional): If keys are available and reported as keys,
++config your key info here */
++#define GTP_KEY_TAB {KEY_MENU, KEY_HOME, KEY_BACK, KEY_HOMEPAGE, \
++	KEY_F1, KEY_F2, KEY_F3}
++
++/**************************PART3:OTHER define*******************************/
++#define GTP_DRIVER_VERSION	"V2.8.0.2<2017/12/14>"
++#define GTP_I2C_NAME		"goodix-ts"
++#define GT91XX_CONFIG_PROC_FILE	"gt9xx_config"
++#define GTP_POLL_TIME		10
++#define GTP_CONFIG_MIN_LENGTH	186
++#define GTP_ESD_CHECK_VALUE	0xAA
++#define RETRY_MAX_TIMES		5
++#define PEN_TRACK_ID		9
++#define MASK_BIT_8		0x80
++#define FAIL			0
++#define SUCCESS			1
++
++/* Registers define */
++#define GTP_REG_COMMAND		0x8040
++#define GTP_REG_ESD_CHECK	0x8041
++#define GTP_REG_COMMAND_CHECK	0x8046
++#define GTP_REG_CONFIG_DATA	0x8047
++#define GTP_REG_VERSION		0x8140
++#define GTP_REG_SENSOR_ID	0x814A
++#define GTP_REG_DOZE_BUF	0x814B
++#define GTP_READ_COOR_ADDR	0x814E
++
++/* Sleep time define */
++#define GTP_1_DLY_MS		1
++#define GTP_2_DLY_MS		2
++#define GTP_10_DLY_MS		10
++#define GTP_20_DLY_MS		20
++#define GTP_50_DLY_MS		50
++#define GTP_58_DLY_MS		58
++#define GTP_100_DLY_MS		100
++#define GTP_500_DLY_MS		500
++#define GTP_1000_DLY_MS		1000
++#define GTP_3000_DLY_MS		3000
++
++#define RESOLUTION_LOC        3
++#define TRIGGER_LOC           8
++
++#define CFG_GROUP_LEN(p_cfg_grp)  (sizeof(p_cfg_grp) / sizeof(p_cfg_grp[0]))
++/* Log define */
++#define GTP_DEBUG(fmt, arg...) \
++do { \
++	if (GTP_DEBUG_ON) {\
++		pr_info("<<-GTP-DEBUG->> [%d]"fmt"\n", __LINE__, ##arg);\
++	} \
++} while (0)
++#define GTP_DEBUG_ARRAY(array, num) \
++do { \
++	s32 i;\
++	u8 *a = array;\
++	if (GTP_DEBUG_ARRAY_ON) {\
++		pr_warn("<<-GTP-DEBUG-ARRAY->>\n");\
++		for (i = 0; i < (num); i++) {\
++			pr_warn("%02x  ", (a)[i]);\
++			if ((i + 1) % 10 == 0) {\
++				pr_warn("\n");\
++			} \
++		} \
++		pr_warn("\n");\
++	} \
++} while (0)
++#define GTP_DEBUG_FUNC() \
++do {\
++	if (GTP_DEBUG_FUNC_ON) {\
++		pr_warn("<<-GTP-FUNC->>  Func:%s@Line:%d\n", \
++		__func__, __LINE__);\
++	} \
++} while (0)
++#define GTP_SWAP(x, y) \
++do {\
++	typeof(x) z = x;\
++	x = y;\
++	y = z;\
++} while (0)
++
++/******************************End of Part III********************************/
++#ifdef CONFIG_OF
++extern int gtp_parse_dt_cfg(struct device *dev, u8 *cfg, int *cfg_len, u8 sid);
++#endif
++
++extern void gtp_reset_guitar(struct i2c_client *client, s32 ms);
++extern void gtp_int_sync(struct goodix_ts_data *ts, s32 ms);
++extern void gtp_esd_on(struct goodix_ts_data *ts);
++extern void gtp_esd_off(struct goodix_ts_data *ts);
++extern void gtp_work_control_enable(struct goodix_ts_data *ts, bool enable);
++
++#ifdef CONFIG_TOUCHSCREEN_GT9XX_UPDATE
++extern u16 show_len;
++extern u16 total_len;
++extern u8 gup_init_update_proc(struct goodix_ts_data *);
++extern s32 gup_update_proc(void *dir);
++extern s32 gup_enter_update_mode(struct i2c_client *client);
++extern void gup_leave_update_mode(struct i2c_client *client);
++#endif
++
++#ifdef CONFIG_TOUCHSCREEN_GT9XX_TOOL
++extern s32 init_wr_node(struct i2c_client *);
++extern void uninit_wr_node(void);
++#endif
++
++/*********** For gt9xx_update Start *********/
++extern struct i2c_client *i2c_connect_client;
++extern void gtp_reset_guitar(struct i2c_client *client, s32 ms);
++extern void gtp_int_output(struct goodix_ts_data *ts, int level);
++extern s32 gtp_send_cfg(struct i2c_client *client);
++extern s32 gtp_get_fw_info(struct i2c_client *, struct goodix_fw_info *fw_info);
++extern s32 gtp_i2c_read_dbl_check(struct i2c_client *, u16, u8 *, int);
++extern int gtp_i2c_read(struct i2c_client *, u8 *, int);
++extern int gtp_i2c_write(struct i2c_client *, u8 *, int);
++extern s32 gtp_fw_startup(struct i2c_client *client);
++extern int gtp_ascii_to_array(const u8 *src_buf, int src_len, u8 *dst_buf);
++/*********** For gt9xx_update End *********/
++
++#endif /* _GOODIX_GT9XX_H_ */
+diff --git a/module_drivers/drivers/input/touchscreen/gt9xx_touch/gt9xx_firmware.h b/module_drivers/drivers/input/touchscreen/gt9xx_touch/gt9xx_firmware.h
+new file mode 100644
+index 000000000..d8ac62f4f
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/gt9xx_touch/gt9xx_firmware.h
+@@ -0,0 +1,2338 @@
++/* Copyright Statement:
++*This firmware are protected under relevant copyright laws,this information contained
++*herein is confidential and proprietary to Goodix.
++*
++* Copyright  (C)  2010 - 2014 Goodix. Ltd.
++*
++*WARNING:The GTP_COMPATIBLE_MODE part of this file was generated by the specialized tools,
++*please do not modify it manually!
++*
++*/
++
++#ifndef _GT9XX_FIRMWARE_H_
++#define _GT9XX_FIRMWARE_H_
++
++#if GTP_HEADER_FW_UPDATE
++unsigned char gtp_default_FW[] = 
++{
++            //TODO:Puts your update firmware data here!
++};
++#endif
++
++/*
++*[HW INFO]00900600
++*[PID]910
++*[VID]1010
++*[GENERATED]2013/08/27 20:59:13
++*/
++#if GTP_COMPATIBLE_MODE
++unsigned char gtp_default_FW_fl[] = {
++/*            0x00,0x90,0x06,0x00,0x39,0x31,0x30,0x00,0x00,0x00,0x00,0x00,0x10,0x10,0x80,0x00,
++            0x55,0x40,0xf8,0x86,0x98,0x71,0x69,0xf0,0x0c,0xc1,0x78,0x1e,0xd2,0x48,0x88,0x58,
++            0xa3,0x41,0xd2,0xeb,0xb2,0x63,0x32,0xe0,0x1d,0xc9,0xf8,0x75,0x15,0x6e,0x01,0x8d,
++            0x05,0x02,0xf9,0x87,0x18,0x7a,0x12,0x6b,0x4d,0x21,0x17,0xd5,0x94,0x6d,0x09,0x0d,
++            0x87,0x03,0x4f,0xc2,0x13,0x0b,0x09,0x7b,0x4d,0x4b,0xf9,0x74,0x99,0xe8,0x38,0xa8,
++            0x3d,0xc9,0xa2,0x4d,0x13,0x74,0xab,0x47,0xe3,0xe5,0xee,0x49,0xdf,0xd2,0x00,0x54,
++            0x8b,0xfb,0x48,0x94,0x1f,0x67,0x8b,0x8e,0xbe,0xe4,0xce,0x59,0x55,0x46,0xbe,0x86,
++            0x40,0x06,0x98,0xb8,0x77,0xa0,0x85,0x9e,0x2b,0x05,0x99,0xfd,0xb1,0xd4,0xf6,0xb9,
++            0x40,0x9c,0x50,0x1d,0x4e,0x1a,0x0d,0x82,0xe9,0x9a,0x5d,0x17,0xba,0x86,0x47,0xac,
++            0x2c,0x48,0x26,0x6e,0x59,0x38,0x10,0xda,0x0f,0x4c,0x15,0xce,0xda,0x40,0x9a,0x3c,
++            0x2f,0x49,0xd0,0x18,0xba,0x2f,0x20,0x3a,0x55,0x69,0xea,0x5c,0x4f,0x62,0x98,0xcc,
++            0x0f,0x7a,0xfb,0x8f,0x99,0x52,0x17,0x7d,0x2f,0xb4,0x91,0xcf,0xde,0x32,0x48,0x6c,
++            0xaf,0x48,0x83,0x51,0xdb,0x24,0x9b,0x29,0xd9,0x49,0xda,0xc2,0x2e,0x29,0xa5,0xcc,
++            0x28,0x7a,0x6d,0x4e,0x1e,0xd7,0x04,0xc8,0xa1,0x4f,0x8a,0x74,0x39,0x55,0xf0,0xa7,
++            0xb2,0x61,0xcf,0x1d,0x5d,0xa0,0x5c,0x41,0xa2,0xfc,0x2f,0x1e,0x1b,0x62,0x79,0xa2,
++            0xb9,0xf5,0x44,0xc9,0xf3,0x59,0x55,0x44,0x82,0x7f,0xc5,0x40,0xdc,0x6d,0xac,0x19,
++            0x8f,0x26,0xb6,0xb5,0xa4,0xe2,0x03,0xd6,0x83,0xde,0xfb,0x6d,0x93,0x1e,0x04,0x80,
++            0x78,0xf8,0x88,0x83,0x91,0xba,0x2c,0xc0,0xd0,0x58,0x9c,0xb7,0x63,0x58,0xde,0xb0,
++            0x26,0xe9,0x6a,0x64,0x85,0x3e,0xe5,0xc2,0xef,0x34,0x5c,0x69,0x02,0xaa,0x4f,0x28,
++            0x82,0x11,0x7b,0x67,0x32,0x38,0x64,0xd3,0x6e,0x37,0x48,0x25,0xc7,0x77,0x02,0x1d,
++            0x24,0xe6,0x65,0xb8,0xb7,0x22,0x64,0xc3,0x6f,0x36,0xa8,0x48,0xc1,0x06,0x22,0x10,
++            0x21,0x5d,0x8e,0x84,0x36,0x1d,0x74,0xa0,0x61,0x4f,0xe4,0x60,0x50,0x10,0x34,0xe2,
++            0xd7,0x1a,0x06,0x36,0xd3,0xca,0x5c,0xb0,0x79,0xf8,0x4f,0xe7,0x5d,0x84,0x7b,0xe9,
++            0x6a,0xdc,0xfc,0xb6,0x82,0x92,0x8b,0x97,0x6d,0xd0,0xdd,0xf1,0x3a,0x35,0x16,0xd1,
++            0xcb,0x3d,0x7e,0x37,0x5a,0x1d,0xca,0xc0,0x42,0xa8,0xe3,0x50,0x9b,0x54,0xc6,0x69,
++            0x14,0xb3,0x86,0xca,0xc4,0x3e,0x3f,0xfb,0xec,0x44,0xdf,0x82,0x37,0xc3,0x79,0x69,
++            0x44,0x1c,0x3a,0x8c,0x9a,0x7b,0x66,0x9f,0xf8,0xf5,0x43,0x0c,0x12,0xea,0x37,0x37,
++            0xc3,0xd3,0x0f,0x21,0x59,0x35,0xbe,0xfa,0x64,0x06,0x68,0x29,0xc1,0x20,0x51,0xfc,
++            0xcc,0xb0,0x14,0x4a,0x65,0x72,0xbf,0xf3,0x7c,0xf7,0x0c,0x86,0xea,0xee,0x38,0xf1,
++            0xdb,0xcf,0x1f,0xcc,0x46,0x93,0x68,0xd4,0x44,0x83,0xa8,0x4d,0x93,0x3f,0x5b,0xab,
++            0x13,0x73,0xdd,0xcf,0x30,0x0c,0xbc,0x70,0x8e,0xd4,0xd8,0xd5,0x33,0xcc,0x39,0xf1,
++            0x62,0x34,0xd0,0xa3,0xcc,0x91,0xfb,0x96,0xd9,0xd5,0x81,0x4d,0x11,0x7d,0x29,0x1d,
++            0xa8,0x57,0xf1,0xf4,0x34,0x99,0x7f,0x13,0x1e,0xd6,0xe1,0xc4,0xd8,0x3f,0x20,0x02,
++            0x04,0xc0,0xff,0x26,0x67,0xa0,0x20,0x62,0xc4,0xc6,0x2f,0xd9,0xb5,0x1f,0x28,0x12,
++            0x05,0xc1,0x68,0xdf,0xca,0x5c,0x3c,0xb5,0x64,0x56,0x82,0xc9,0xa2,0xa3,0x79,0xfa,
++            0x84,0x82,0x7e,0x07,0xe3,0xae,0xac,0xd1,0x25,0x19,0x4a,0xa3,0xa1,0x01,0x29,0x8f,
++            0x85,0x83,0x22,0x77,0xcd,0xa5,0x8d,0xcc,0x86,0x30,0xa7,0x31,0x34,0x5c,0xa5,0xb2,
++            0x3d,0xb5,0x1f,0x2d,0x9b,0x52,0x50,0xd5,0x0e,0xd5,0xd0,0xb8,0xbf,0x95,0x10,0x39,
++            0x6f,0x88,0xb6,0xb4,0x57,0x98,0xc2,0x8d,0xc8,0x68,0xbf,0x4f,0x51,0xc6,0xa1,0xe3,
++            0x39,0x0b,0xe9,0x43,0x1e,0x58,0x7d,0xda,0xf5,0x1d,0xee,0x87,0xd4,0x6d,0x7f,0x31,
++            0xe7,0x78,0xdb,0x67,0x54,0x08,0xee,0xec,0xa4,0xc3,0x7d,0x04,0xbb,0xe8,0x22,0x0a,
++            0x0c,0xc8,0xae,0x79,0x7f,0x37,0x62,0x59,0x54,0x42,0x4d,0xd0,0x5a,0x01,0x2a,0x1a,
++            0x0d,0xc9,0xe7,0x19,0x9d,0xe7,0x8e,0x5a,0x45,0x19,0x65,0x62,0x2e,0xee,0x23,0x96,
++            0x8c,0x8a,0xdb,0xf2,0x90,0xe8,0xf4,0xd5,0x2d,0xac,0x02,0x0b,0xab,0x5f,0xb6,0xda,
++            0x8d,0x8b,0x6b,0xfe,0xa1,0xad,0x94,0xeb,0x4c,0x6a,0xe4,0x0b,0x15,0x01,0x1c,0x4c,
++            0xef,0x0f,0x42,0x3d,0xbd,0x2f,0x0b,0x1b,0x3a,0xda,0x32,0xce,0xec,0x67,0x14,0x77,
++            0xc7,0xe7,0x95,0x4d,0x10,0xbc,0x2e,0xe8,0x4f,0x60,0xae,0xda,0x3c,0xef,0x93,0xcf,
++            0xac,0x14,0x04,0xcb,0xbc,0x34,0x7b,0xb2,0x41,0x63,0xf7,0x8d,0x86,0xac,0x7a,0x28,
++            0xbf,0xe1,0xd5,0x77,0x10,0x09,0x2b,0x0b,0x4f,0x49,0x6c,0x8c,0x5b,0x64,0x01,0x82,
++            0x4f,0xb4,0xc4,0x84,0x6a,0x1d,0x90,0xec,0xbb,0xed,0x7a,0x5b,0x76,0x2b,0xac,0x92,
++            0x94,0x1c,0x82,0x12,0x1e,0x43,0x94,0x9f,0x1e,0xc9,0xe5,0x57,0x90,0x0e,0xda,0x87,
++            0xa4,0xf7,0x3d,0x65,0xb2,0x99,0xde,0xd4,0x64,0x05,0x85,0x23,0xd9,0xd7,0xc9,0xb4,
++            0x16,0x1e,0x72,0x3a,0xb3,0x98,0xe2,0xb2,0xe3,0x9a,0x51,0xc4,0x9f,0x05,0xa4,0x63,
++            0x00,0x1f,0x2c,0x86,0x32,0x9d,0x54,0x68,0x67,0x57,0xf2,0xde,0x5f,0x6e,0x36,0xe9,
++            0x21,0x96,0xfb,0x25,0xb3,0x3e,0x26,0x64,0x75,0x18,0x10,0x85,0x0b,0x73,0xee,0xfe,
++            0x4d,0xd2,0xdf,0x37,0x86,0x17,0x99,0x90,0x9a,0xcd,0xf3,0xcf,0xdf,0x65,0xc9,0x93,
++            0xe3,0x33,0xd8,0x66,0xc7,0x18,0x67,0xf1,0x54,0x7a,0x02,0x84,0x83,0x7e,0xc2,0xad,
++            0x2d,0xf8,0x4b,0x7f,0x8e,0x28,0x20,0xd8,0xee,0xdc,0xec,0xac,0xcf,0x51,0x2f,0x45,
++            0xce,0x9d,0x56,0x6e,0x35,0xb6,0xb2,0x4a,0x92,0xd6,0xe7,0x47,0x1a,0xf8,0xdd,0x89,
++            0xa4,0xd5,0x4f,0xa5,0x3e,0xb2,0x3b,0x49,0x6e,0xde,0xe5,0x25,0xfd,0x7a,0x3a,0xe9,
++            0x23,0xfe,0x07,0xa1,0x3a,0xce,0x05,0x9c,0x4e,0xbe,0x85,0x3d,0x1f,0xe0,0xb6,0xf6,
++            0xe6,0xff,0x42,0xac,0xd5,0x5d,0xe5,0x9a,0xee,0xca,0xd6,0x7c,0xfe,0xf4,0x10,0xdc,
++            0x4c,0x98,0xd0,0xeb,0xdc,0xb4,0xcc,0xc6,0x7f,0x18,0xde,0xfb,0xb7,0x0c,0xf0,0x3b,
++            0xac,0x6f,0xfd,0xd2,0x9f,0xb7,0x7f,0xfe,0xdd,0xb5,0xf1,0x1e,0xc6,0x01,0xbc,0x28,
++            0x23,0x92,0x3e,0xad,0x54,0xce,0xe8,0x88,0xd3,0xb1,0xea,0x84,0x70,0x79,0x00,0x40,
++            0x3f,0x8d,0xda,0x06,0xa3,0xb9,0xaa,0xdf,0xa9,0x71,0xa8,0x20,0xd5,0xb2,0x58,0xba,
++            0xa0,0xfe,0x9a,0x15,0x17,0x22,0x08,0xbd,0x4a,0x5a,0xd9,0xd4,0x59,0xa3,0x7f,0x2c,
++            0xda,0x40,0xe0,0x45,0xa2,0xdf,0xfd,0xbe,0xc3,0xc0,0xc8,0xcc,0x35,0xa0,0xe5,0x82,
++            0xbd,0x0b,0x98,0xd5,0xdb,0x38,0x45,0x47,0xbd,0xbc,0xc0,0xdc,0x34,0x71,0xfa,0xbf,
++            0x8d,0x82,0xd6,0x26,0xa9,0x99,0xe8,0x80,0x46,0x69,0x77,0xa5,0xbb,0x4e,0x11,0xbd,
++            0x66,0x0c,0x08,0xf4,0x19,0xd8,0x85,0x06,0xbc,0xd8,0x5c,0x06,0xb8,0x4f,0x41,0x01,
++            0xde,0xfb,0x6d,0xce,0x91,0x56,0x2c,0x13,0x31,0x5d,0x3d,0xf7,0x84,0x6e,0x4c,0xb9,
++            0xa4,0xca,0xb1,0x4c,0x13,0x48,0xf5,0xee,0xc2,0x07,0x19,0xd5,0x92,0x25,0x00,0x17,
++            0x34,0xbc,0x5f,0x7a,0x79,0x08,0x28,0x8d,0xbf,0x0a,0x18,0xcc,0x3e,0x6e,0x34,0x31,
++            0x86,0x12,0x18,0x9e,0x99,0x22,0x4a,0x04,0x48,0x41,0x5e,0xb9,0x1a,0x9a,0x95,0x72,
++            0xab,0xd7,0xdb,0x24,0xb8,0x98,0x43,0xc1,0x69,0x08,0xb3,0x74,0x79,0xb5,0xd0,0x8f,
++            0x88,0x6b,0xb3,0x98,0x97,0xa1,0x21,0xd1,0xa2,0x84,0x5f,0xbb,0x97,0x96,0x20,0x4d,
++            0x09,0x4c,0xc1,0x0f,0xd6,0x37,0x6e,0xed,0xbb,0xed,0x82,0x16,0xd5,0xc1,0x92,0xae,
++            0x38,0xb6,0x4a,0x3f,0xa0,0x36,0x48,0x72,0x4d,0x4e,0xd2,0x6c,0xa7,0x27,0xc1,0x6d,
++            0x6b,0x15,0x1e,0x3b,0xeb,0x25,0x6b,0x58,0x6b,0xf1,0x1b,0xe9,0xf8,0x9f,0xf1,0xa6,
++            0x06,0x89,0x16,0xc9,0x7a,0xb0,0x4b,0x1b,0x34,0x0d,0xfb,0x6c,0xdd,0x6c,0x7a,0xa8,
++            0xdd,0x19,0xdd,0x86,0xd7,0x31,0xd4,0x00,0x53,0x5d,0x1f,0x2e,0x71,0xd0,0x34,0x63,
++            0x11,0x17,0xd7,0x26,0x06,0xc7,0x14,0xb4,0xbd,0x60,0xf6,0x36,0x93,0x6a,0x06,0x05,
++            0x8a,0x62,0x40,0x04,0x83,0x26,0xea,0x66,0x2a,0x63,0xaf,0x5a,0xf6,0x59,0x7f,0x79,
++            0x00,0x91,0xd0,0x47,0xc6,0x33,0x7d,0x03,0xd2,0x5e,0xa5,0x4a,0xd2,0xd3,0x34,0x39,
++            0x46,0x61,0xf8,0x32,0x34,0x37,0x66,0x1f,0x51,0x9f,0xee,0x17,0x7d,0x36,0xd0,0x0f,
++            0xc2,0x0e,0xf2,0x10,0xbe,0xc3,0xb9,0x00,0xe3,0x4a,0xe7,0x33,0x9a,0xff,0x0c,0xef,
++            0xed,0x54,0x82,0xa7,0xf0,0xc9,0xed,0x0e,0x6f,0xab,0x85,0x4d,0xf4,0x75,0x12,0x27,
++            0x90,0xbc,0x85,0xd1,0x1a,0xf8,0x43,0x13,0x71,0x5f,0x1d,0x55,0x8f,0x7f,0x7e,0x0c,
++            0x0a,0x03,0x59,0x34,0x3e,0x1b,0xe9,0x98,0x3c,0x1a,0xcf,0x5d,0x3c,0x7c,0x1b,0xd8,
++            0x2d,0xed,0x50,0xea,0xb6,0xbf,0x66,0x3c,0x10,0x34,0x64,0x54,0x52,0xb4,0x3f,0x76,
++            0x27,0xbc,0x41,0xce,0xfe,0x21,0x47,0x44,0x01,0x6b,0x95,0xdf,0xcb,0xd1,0x1a,0x69,
++            0xfd,0xba,0x8f,0xdd,0xb5,0xf9,0x1a,0xd8,0xb3,0x5d,0xe0,0x7a,0x10,0xd8,0xfc,0x0f,
++            0xe8,0x95,0x06,0x6c,0x08,0x7e,0x81,0x6c,0x48,0xee,0xd4,0xd3,0x39,0x78,0xb1,0x5c,
++            0x00,0x93,0x02,0x58,0x19,0xcc,0xb2,0x6a,0x3d,0x55,0xdc,0x03,0xa7,0xf7,0x4f,0xc4,
++            0x4b,0xd1,0x97,0xb7,0x35,0x93,0x6f,0x79,0x01,0x74,0xd1,0x69,0xd8,0x6d,0x6f,0xdc,
++            0x98,0xa4,0xc7,0xd9,0x12,0xf0,0xdb,0x8b,0x00,0x75,0x86,0x10,0xbd,0xb2,0x06,0x2b,
++            0x38,0x0b,0x77,0x26,0xb5,0xd2,0x0e,0x0b,0x2f,0xcf,0x74,0xa0,0x02,0xe6,0x7c,0x17,
++            0xa4,0x2e,0x44,0x84,0x19,0xa9,0x6e,0x41,0x27,0x48,0x43,0xd4,0xd0,0x93,0x66,0x32,
++            0xe8,0xc0,0xf8,0x05,0xd0,0x6f,0xb1,0x11,0x49,0x64,0x91,0x76,0x75,0x68,0xbf,0x23,
++            0xbe,0xc1,0x6b,0xff,0xa6,0x68,0x19,0xd9,0x2c,0xcc,0x11,0xbe,0x57,0x64,0x70,0x82,
++            0x1e,0x79,0xb9,0xab,0xf3,0x5b,0x20,0x32,0xcb,0x32,0xfa,0x76,0xa9,0x10,0x3e,0xf2,
++            0x1d,0xc6,0x68,0x15,0xdf,0x38,0x30,0x8d,0x41,0xc6,0xba,0x89,0xbe,0x8f,0xcd,0xd1,
++            0x96,0x8e,0xda,0x00,0x48,0xae,0x73,0x88,0xc0,0xc5,0x39,0xe3,0xf4,0xec,0x09,0xe1,
++            0xb4,0x8a,0xff,0x35,0xff,0xaa,0x28,0x34,0x19,0x47,0x55,0xe8,0xd4,0x07,0x72,0xe5,
++            0xad,0x77,0x27,0x06,0x7b,0xbf,0x28,0x28,0xde,0xc2,0xeb,0x4c,0x7f,0x4a,0x62,0x1e,
++            0x85,0x17,0xa4,0x7c,0x5c,0x89,0x63,0xdb,0x8b,0xc3,0x56,0x4d,0x00,0x1f,0x1d,0x26,
++            0x03,0x7c,0x4b,0x82,0x1e,0xae,0xb6,0x58,0xf4,0xa6,0xea,0xd3,0x39,0x15,0x4b,0xa9,
++            0xbe,0x86,0xd3,0x1d,0xdd,0x26,0xbf,0x1b,0xd3,0x59,0xe1,0x3d,0x6e,0x42,0x3b,0xb7,
++            0xe9,0x41,0x9d,0x7e,0x86,0xee,0x8d,0x01,0xc3,0x4a,0x41,0xab,0x83,0x31,0xaa,0xfa,
++            0x91,0x56,0xd1,0x2d,0x14,0xef,0xd6,0xe8,0x5f,0xc7,0x36,0x0d,0x50,0x83,0x3a,0xb4,
++            0xfd,0xc9,0xb3,0x1a,0x98,0xad,0x72,0xab,0xd8,0x33,0x5c,0x6d,0xde,0x1a,0x5c,0xa6,
++            0xda,0x14,0xbb,0x63,0x9e,0xef,0x39,0x10,0x13,0xc0,0x99,0x53,0xde,0x8f,0x35,0x06,
++            0x06,0xeb,0x84,0x92,0xd5,0xab,0x46,0x4a,0xc5,0x2f,0xd3,0x56,0xf4,0xef,0x3d,0x16,
++            0x5c,0xfc,0x96,0x7e,0x3a,0xfe,0xdb,0x41,0x51,0xca,0x3f,0xc9,0x15,0xb1,0x1b,0xaa,
++            0x07,0x67,0x79,0x71,0xa4,0x7d,0x99,0x4b,0xdb,0x1f,0xab,0x17,0x66,0xfa,0x77,0x7a,
++            0xcd,0x72,0xcd,0x95,0xe0,0xbe,0xe1,0xd5,0x16,0xc3,0x7d,0x17,0xc5,0xfb,0xe6,0x2a,
++            0x55,0x59,0x24,0x66,0x35,0x36,0xb4,0x42,0x27,0x54,0xe2,0x84,0x1e,0xf9,0x68,0x46,
++            0x03,0x8e,0x0b,0x16,0x33,0x98,0x34,0x62,0x8c,0xbf,0xb4,0xfe,0x71,0xf6,0x89,0x51,
++            0xa6,0x9e,0x1a,0xb4,0xf5,0xda,0x0b,0x27,0xe0,0xd5,0x88,0x9c,0x7b,0xc0,0xcb,0xb5,
++            0x28,0x11,0x17,0x53,0x95,0x05,0x91,0x61,0xd3,0xdf,0xb9,0x88,0x54,0x47,0xe6,0x2a,
++            0x93,0x35,0x8c,0x5e,0x60,0xb9,0x8e,0x51,0xe1,0x55,0x34,0x68,0x66,0xe3,0xab,0xe9,
++            0x1d,0x96,0xce,0x9c,0x1e,0xb4,0x45,0x52,0x1a,0x14,0xcc,0x56,0xdc,0xe2,0xb2,0x69,
++            0xaa,0xb9,0x9f,0x8b,0x39,0x58,0x50,0x50,0x0d,0x4c,0x69,0x5b,0xbe,0xfc,0x0f,0x47,
++            0x9e,0x40,0x50,0xd8,0xb3,0xba,0xc2,0x7c,0x14,0xad,0x62,0x49,0xce,0x30,0x66,0x8a,
++            0x32,0xd1,0xde,0x5e,0xc1,0x11,0xf2,0x98,0x85,0xb6,0xd6,0x09,0x9f,0x63,0xd4,0x3a,
++            0x23,0x86,0x68,0xe0,0x34,0x41,0x00,0x2a,0x5c,0xa6,0xee,0xda,0x4c,0xef,0x25,0x2d,
++            0x9d,0xe5,0xab,0x88,0x60,0xb4,0xb7,0x4b,0xdc,0x5e,0xcb,0xcf,0xae,0xd3,0xc9,0x3d,
++            0x9c,0xf5,0x54,0x80,0x3f,0xbf,0xc5,0x6b,0x87,0xd2,0x47,0xef,0x58,0xbe,0xa8,0x38,
++            0xe1,0x1b,0xcd,0x44,0x92,0x24,0x5a,0xbd,0x4e,0x06,0xd6,0x03,0xf1,0x25,0xe0,0x0d,
++            0x13,0x4e,0xa2,0x91,0x1f,0xab,0x20,0xe0,0x1d,0x5a,0x3e,0xc0,0x59,0x7a,0xa3,0xe7,
++            0x05,0xb0,0xc9,0x67,0xd3,0x2e,0xd6,0xa3,0x40,0xda,0xaf,0xa3,0x88,0x79,0xa1,0x81,
++            0x04,0xa3,0x0d,0xfd,0x15,0x6c,0x39,0xd7,0x64,0x2d,0x5a,0x53,0x2e,0x6a,0x02,0xa6,
++            0x31,0xd6,0x98,0x5d,0xb3,0x46,0xa8,0xe2,0xc2,0x9e,0x2f,0x5a,0x3e,0x26,0x36,0x84,
++            0x05,0xed,0x4a,0x36,0x9e,0x47,0x20,0xf2,0xc3,0xbf,0xdd,0x07,0x6b,0x6a,0xf9,0xa9,
++            0x1a,0xc7,0x21,0xd5,0xb0,0xa4,0x69,0xe3,0x2c,0x0b,0xca,0x5e,0x50,0x65,0x5a,0x23,
++            0x7c,0x45,0x0d,0xd3,0xd7,0x21,0x61,0xf3,0x2d,0x2a,0x89,0x6c,0x8b,0x61,0xaa,0x1c,
++            0x8d,0x28,0xe2,0x0e,0x43,0x25,0x70,0x39,0x49,0x28,0x16,0xc4,0x94,0xa8,0xf5,0xf5,
++            0x01,0x52,0x72,0x7a,0x94,0xaf,0x3a,0x65,0xe8,0xc3,0x8e,0x5a,0xae,0x72,0xf8,0xf4,
++            0x9f,0xb1,0xc9,0x10,0xab,0x3e,0x49,0x38,0x6f,0x4c,0x83,0x34,0x80,0x71,0x79,0xf0,
++            0x06,0x49,0x89,0xdd,0x95,0xa0,0x9c,0xd1,0xa6,0x04,0x8b,0x5b,0xad,0x24,0xdc,0xbc,
++            0xe3,0xa6,0xe2,0xe8,0xbb,0x83,0x2a,0xea,0xca,0x45,0x82,0x71,0xb3,0x3d,0x6c,0xba,
++            0x44,0xa2,0x5b,0xde,0x9b,0x76,0x22,0xfa,0xcb,0x64,0xe0,0x9e,0xdb,0x5d,0x65,0x9d,
++            0x29,0x8b,0xd6,0x6a,0x3b,0x81,0x6b,0xeb,0x24,0xc3,0xab,0xef,0xf8,0xde,0x02,0x2a,
++            0xc0,0xae,0xf3,0xb5,0x5b,0xe0,0x63,0xfb,0x25,0x60,0xfd,0x54,0xef,0x69,0x64,0x82,
++            0x39,0x1d,0xa4,0x6d,0xfb,0xef,0xb0,0xd2,0xc3,0xdb,0xac,0x21,0x7e,0xfa,0x6c,0x92,
++            0x34,0x1c,0x4a,0x7c,0x41,0xaa,0x26,0x00,0xcf,0xfe,0xda,0x25,0x42,0x50,0x65,0x82,
++            0xed,0x1d,0x5a,0xcd,0xb6,0x11,0xfd,0x9d,0x0b,0x16,0x52,0x56,0x99,0x73,0x6d,0x92,
++            0xb0,0x1c,0x7e,0x6c,0x46,0x48,0xb9,0x41,0x1e,0x5c,0x25,0x4a,0xc2,0x72,0x24,0xc2,
++            0x63,0x19,0x23,0x84,0x7a,0x76,0x50,0x06,0x83,0x4f,0x92,0x96,0x5c,0xfc,0x86,0x3a,
++            0xc2,0x2e,0x0c,0xb1,0x1e,0x3f,0x24,0x4d,0x83,0xaa,0x64,0xa6,0x5d,0x16,0x4f,0xc9,
++            0x01,0xbb,0x9d,0x12,0x32,0xd6,0x95,0x07,0x1f,0xfd,0xf5,0x1a,0xc1,0xe4,0x94,0x36,
++            0x12,0xb6,0x4d,0x13,0xc3,0x31,0xee,0x13,0xe5,0x8e,0x97,0xb7,0xae,0x88,0x66,0x8a,
++            0x35,0x15,0x82,0x60,0xb8,0x03,0x4c,0xd8,0x14,0x47,0x2e,0x52,0xf7,0x8e,0xd5,0x98,
++            0x56,0x92,0x9e,0x18,0x61,0xbd,0x1c,0x84,0x9e,0x5d,0x31,0xbe,0x79,0x8d,0x67,0x8a,
++            0xb1,0x15,0x71,0x71,0xb8,0xc1,0x2d,0x4f,0xb4,0xd1,0x9f,0xbc,0x25,0xa7,0x50,0x99,
++            0x96,0x3b,0xef,0x9f,0x9c,0x36,0xb2,0x51,0x61,0xd0,0x81,0xbf,0xed,0xd6,0x7e,0x41,
++            0x85,0xb1,0xe6,0xa4,0x9b,0xe3,0x73,0x6a,0x6b,0xbb,0xe8,0x88,0x12,0x71,0x15,0x3f,
++            0x9a,0xbc,0xb1,0xa2,0xd0,0xdc,0x56,0x57,0x8a,0x52,0xe4,0x59,0x8c,0xf1,0x09,0x23,
++            0x4b,0x25,0xa7,0xcf,0xd7,0x33,0x0d,0xe8,0x49,0x58,0x58,0x12,0x5e,0x6e,0x77,0x50,
++            0x04,0x19,0xf0,0x2e,0x8b,0x3e,0xf7,0xd7,0x69,0x5c,0x0b,0x2d,0x5a,0x87,0x60,0x38,
++            0xe5,0x9b,0xa2,0xe0,0x96,0xa4,0x88,0xc2,0x40,0x40,0x8a,0xce,0x7c,0xaf,0x56,0x4b,
++            0x36,0xb5,0x50,0x94,0x95,0x2b,0x87,0x75,0x87,0x31,0xe1,0x3d,0xb0,0x3e,0x85,0xe5,
++            0x94,0xcd,0xed,0x65,0xa7,0x69,0xc9,0x51,0x3b,0x1d,0xe8,0x29,0xb3,0xc2,0xd1,0xfb,
++            0xb2,0x4c,0x91,0xff,0xe2,0x6c,0x71,0x0e,0xa6,0xd7,0x55,0xa8,0xd4,0x43,0xaa,0xaa,
++            0x71,0xcb,0x54,0x24,0x25,0x60,0x08,0x24,0xba,0x88,0xa0,0x7f,0x35,0xc4,0x56,0x9a,
++            0x4e,0x6f,0x17,0x25,0x2f,0xc9,0x42,0x9a,0x55,0x8a,0xed,0x90,0x64,0x27,0x5b,0xe6,
++            0x94,0xc9,0x1b,0xaf,0x56,0x6b,0xb3,0xe7,0xd5,0xda,0x89,0x8f,0x9c,0x4b,0x71,0x5e,
++            0x08,0x2a,0x0e,0x17,0xd5,0x0a,0x20,0x63,0x60,0xdc,0xc7,0x5b,0x70,0xa5,0x7b,0x0a,
++            0xab,0x93,0xc2,0x0c,0x13,0xa5,0xa1,0xae,0x6e,0xc9,0x1d,0x50,0x81,0xec,0x4a,0x18,
++            0x1c,0x84,0xf3,0x09,0xba,0xb2,0x10,0x07,0xa6,0x8d,0x45,0xd6,0x0d,0x14,0x36,0xfb,
++            0x80,0xc5,0xfa,0xee,0x7b,0x27,0x69,0xd4,0x6f,0x41,0xb1,0xc7,0x8a,0xa7,0x4b,0x18,
++            0xc8,0x84,0x32,0xe7,0x73,0xf0,0x01,0x8b,0x2f,0x64,0x43,0xbd,0x5d,0x32,0x2b,0xd8,
++            0x0e,0x21,0x73,0xd1,0x1f,0x5c,0xd3,0x8c,0xcc,0xc8,0x3c,0xc4,0x58,0xe4,0xec,0xa7,
++            0x03,0xcf,0xd4,0x77,0x90,0x5b,0x68,0x6b,0x7c,0xbf,0x3a,0xa7,0x38,0xf6,0xad,0xd9,
++            0x82,0x86,0xba,0x59,0x7b,0x51,0xb9,0x09,0x8d,0x3e,0xf3,0xeb,0xac,0x61,0x26,0x5c,
++            0x87,0x9c,0xa3,0x4e,0x76,0xfe,0x83,0x1d,0x30,0xd4,0xf8,0x19,0x24,0xaa,0xfd,0x81,
++            0x1f,0x08,0xee,0x1b,0x07,0xb1,0xb4,0x44,0x57,0x3b,0xaa,0x61,0xb6,0x80,0x74,0xbc,
++            0xa7,0x95,0x6b,0x7e,0x1d,0xfe,0x44,0x5a,0x62,0x9e,0x39,0x5e,0x55,0xbc,0xe5,0x03,
++            0x54,0xd0,0x5d,0xa0,0x15,0x38,0x8d,0xb3,0x25,0x58,0xbd,0xa2,0x9f,0x5b,0x22,0xf1,
++            0xab,0xf1,0x19,0xf5,0xf6,0x43,0x5d,0xb1,0xe6,0xde,0x42,0x86,0x9c,0x71,0x44,0x8b,
++            0x87,0x4b,0xf7,0xdf,0x30,0xbf,0xf0,0x00,0xe4,0xd0,0x8a,0xaa,0x49,0xd4,0x13,0xac,
++            0x14,0x0d,0xd4,0x25,0x0f,0xd0,0xfc,0x34,0x2f,0xd3,0x26,0x1e,0xef,0x38,0x05,0xc1,
++            0xb7,0x9b,0x0b,0x45,0x36,0x1f,0x2a,0x81,0xc4,0x1b,0x42,0x96,0xf0,0xaf,0x95,0xa8,
++            0xb7,0xd8,0xd5,0x24,0x83,0x4c,0x5d,0x0a,0x46,0xb4,0x00,0x1f,0xa1,0xba,0x6c,0x37,
++            0x22,0xde,0xff,0x85,0xdb,0xb5,0x7c,0x17,0x87,0xe2,0x90,0xdf,0xdf,0x7c,0x16,0x1f,
++            0xab,0x4b,0x6d,0x78,0xbf,0xbd,0x40,0x73,0xe2,0x5f,0xaa,0xd8,0x8a,0x04,0xe1,0x09,
++            0x2c,0x91,0x8d,0x5f,0xe0,0xa1,0x21,0xc9,0x84,0xd7,0xee,0xa9,0x1b,0xe1,0x17,0x1e,
++            0xa3,0xf9,0x37,0xfd,0x93,0xfd,0x37,0xfb,0xe1,0x70,0x2c,0x4c,0xb6,0xe0,0x06,0xc8,
++            0x33,0x91,0xfc,0x32,0x3e,0xfe,0x96,0xe3,0x4c,0xec,0xe6,0xf7,0x3a,0x53,0x56,0x21,
++            0xda,0x86,0x01,0xad,0x53,0xf2,0x46,0x08,0x90,0xdb,0xfc,0x0d,0x6a,0x48,0x9c,0x49,
++            0x2e,0xc6,0x7c,0x71,0xb8,0xbd,0xbe,0x69,0x6e,0x2f,0x7e,0x9d,0x05,0xfa,0x27,0x3d,
++            0x56,0x8f,0xee,0xac,0x8f,0xf0,0x5f,0xc7,0x4e,0x26,0xe1,0xc0,0x96,0xbd,0x99,0x8c,
++            0x82,0x03,0x6f,0xea,0x90,0xb8,0x70,0x96,0x15,0x4d,0x7f,0xcf,0xd0,0xfc,0xc8,0xf0,
++            0x1e,0x02,0xa8,0x42,0x91,0xaf,0x45,0xad,0xee,0xcc,0x9c,0x28,0x04,0x68,0x85,0xf1,
++            0x88,0x0d,0xa1,0xc3,0x10,0x7d,0xbd,0xc9,0x00,0x84,0xb0,0xc7,0x2d,0x6b,0x0c,0xe8,
++            0x03,0x07,0xa9,0x7c,0x11,0x6c,0xe6,0xb5,0xea,0xa0,0x35,0x3f,0x72,0xde,0x7a,0x1e,
++            0xf9,0x45,0xbf,0x2f,0xce,0x2b,0x81,0x93,0xce,0x49,0x6b,0xc1,0xa5,0xd9,0xf3,0x42,
++            0x23,0x4b,0xb0,0xae,0xae,0xf1,0xc8,0xb0,0x5b,0x78,0xa3,0x1b,0x7d,0x1a,0x7e,0xab,
++            0x69,0x09,0xf3,0x7d,0x4b,0x85,0x2f,0x83,0x6e,0x4b,0x05,0x9e,0x23,0x05,0x0a,0xaf,
++            0x7b,0x08,0xb1,0x67,0x64,0x12,0x4f,0x77,0x70,0x83,0x99,0xa2,0xdf,0x51,0x59,0x6a,
++            0xc9,0x6a,0xa2,0xa9,0x98,0x2a,0x28,0xc0,0x37,0x87,0x80,0x28,0xba,0xe8,0xcc,0xfe,
++            0x3a,0xed,0xaa,0x92,0x99,0x3c,0xe0,0xd0,0x22,0x86,0x3a,0x53,0x39,0x29,0xc7,0xd9,
++            0x84,0x11,0xa3,0x3b,0x18,0x77,0x4a,0xc1,0x2f,0x5a,0x93,0xed,0x62,0xc5,0xb1,0xde,
++            0x4b,0x2b,0xab,0xd3,0x19,0x66,0x1a,0xcf,0xfa,0xf0,0xe9,0x2d,0xd9,0x61,0x1c,0xaa,
++            0x1a,0xf1,0xba,0x23,0xc6,0x23,0x2a,0x60,0xaf,0x0d,0xda,0x7c,0xe7,0x5a,0x35,0x18,
++            0x47,0x1b,0x59,0x07,0x21,0xf2,0x4c,0x7e,0xf8,0x00,0xe0,0x97,0xec,0x2c,0xd4,0xb6,
++            0x73,0x6d,0xf1,0x12,0x53,0x21,0xa6,0x97,0xde,0x73,0x2e,0x70,0x49,0xc3,0x03,0x4d,
++            0x40,0x00,0xf1,0xe5,0x68,0x72,0x25,0x9b,0xdb,0x02,0x82,0xf5,0x26,0x9e,0x24,0x79,
++            0x81,0x9a,0xb9,0x5a,0xdd,0x34,0xfb,0x4e,0xe0,0x83,0xae,0x23,0x54,0x8d,0xb8,0xf2,
++            0xde,0x9d,0x28,0xe6,0xbf,0x54,0xa2,0xb9,0xc2,0x34,0xe4,0xeb,0xa1,0x7e,0x82,0x69,
++            0x90,0x5d,0x82,0x8e,0x34,0x66,0x34,0xa7,0x30,0x36,0xb2,0x47,0x10,0x67,0x47,0x8c,
++            0x92,0x71,0x77,0x9d,0x6e,0x0c,0xf2,0x5f,0x61,0x10,0xaf,0x9d,0x24,0xc7,0xe8,0x5f,
++            0xdd,0x99,0x64,0x4b,0xcb,0x62,0xe0,0x02,0x46,0x5e,0x2d,0x96,0xa3,0x0b,0x22,0x97,
++            0xc2,0xa3,0xad,0x94,0x63,0x9a,0x75,0x06,0x73,0x90,0x63,0xc9,0x8c,0xa8,0xa6,0x3f,
++            0xa4,0xa6,0xfe,0x4e,0x5b,0x72,0x50,0x8a,0x8a,0x12,0x45,0x14,0x51,0x74,0x32,0xa3,
++            0x71,0x88,0x6d,0xab,0x2d,0xe8,0x25,0xd5,0x5d,0x88,0x09,0x0b,0x0a,0x14,0xfe,0xee,
++            0xa5,0x9e,0xbd,0x62,0x80,0x37,0xaa,0xa1,0x8f,0x48,0xee,0x9e,0x0c,0xa7,0x08,0x7e,
++            0xab,0x1d,0x2e,0x92,0xb5,0xa4,0xa2,0xb1,0xce,0x49,0x6d,0xbc,0x41,0x84,0x01,0x49,
++            0xa4,0x91,0xb8,0x62,0x9c,0x0e,0xf8,0x47,0x68,0x41,0x07,0x17,0xf8,0x0a,0xd4,0xfb,
++            0xea,0xeb,0x76,0xff,0x15,0x27,0xf0,0x57,0x69,0x50,0xb8,0x5f,0x39,0x84,0x66,0xcd,
++            0x2c,0xac,0xf9,0x42,0xc1,0xa1,0x53,0x83,0x02,0x18,0xa9,0xb6,0x54,0xe0,0xe2,0xaa,
++            0xf5,0xe2,0xb6,0x0a,0xda,0xe1,0x5f,0x1e,0x4f,0x40,0x30,0xe9,0xe5,0xe0,0x29,0x69,
++            0x61,0xfe,0xa2,0x37,0xe6,0x90,0x7e,0x0f,0x03,0x51,0xfe,0x48,0x6b,0x7c,0x75,0x47,
++            0x5c,0x5e,0x32,0xaf,0x62,0x60,0xf8,0x1b,0x0b,0xc3,0x3e,0x97,0x61,0x77,0x28,0x17,
++            0x37,0x62,0x80,0x48,0x94,0xc3,0xca,0x64,0x5e,0x8c,0x07,0x03,0x78,0x48,0xd0,0x90,
++            0x85,0x1a,0x93,0xf8,0xf4,0xc7,0x8f,0xb6,0x6e,0x28,0xba,0xd3,0xeb,0xc1,0x99,0xfc,
++            0x21,0x73,0x84,0x01,0x00,0xc6,0xf4,0x65,0xc0,0x8c,0x11,0x02,0x56,0x52,0x11,0xc3,
++            0xfb,0x98,0x1d,0x5d,0x5c,0xe7,0x60,0x2f,0x30,0x8c,0x3b,0x3c,0x51,0xb7,0x98,0x66,
++            0x8b,0x92,0xd2,0x7f,0xc3,0x07,0xe0,0x11,0xca,0x95,0x0f,0x18,0x78,0x3b,0xd1,0x76,
++            0x82,0x2b,0x93,0x72,0x7c,0xaa,0x06,0x90,0xeb,0xf8,0x2c,0x8c,0xce,0x86,0x1e,0x5e,
++            0x4d,0x89,0x99,0xbc,0x77,0x35,0x0f,0x64,0x7f,0xa0,0xce,0xc2,0x2d,0x7b,0x52,0xf3,
++            0x6a,0xb7,0xe8,0xa6,0x13,0xa7,0x9d,0x57,0x74,0xb0,0xd4,0xf7,0x18,0x47,0xb7,0xec,
++            0xa9,0x23,0x8b,0x54,0xd5,0xcc,0x33,0x55,0xeb,0x89,0x16,0x4c,0x78,0xe2,0x52,0x0b,
++            0xcd,0x8f,0x84,0x18,0x8c,0x35,0xd5,0xd4,0xcd,0x01,0x41,0x3a,0xf0,0xa8,0x5b,0x0e,
++            0x6c,0x21,0x88,0xed,0x30,0xb6,0x8d,0x22,0x2b,0xda,0x33,0x58,0xf8,0x9d,0xd9,0xdb,
++            0x2e,0x8d,0x85,0x18,0x4c,0x55,0x85,0x32,0x6a,0xdb,0x9e,0x39,0x49,0x8f,0x92,0x99,
++            0xef,0xe0,0x5d,0x73,0xe1,0x71,0x76,0xeb,0xa7,0x88,0x17,0x05,0xc8,0xe4,0x11,0x24,
++            0x2d,0x60,0xc5,0x04,0x31,0x31,0xde,0xd6,0xa4,0xa9,0xc7,0xf0,0xe4,0x1d,0x04,0xb0,
++            0x6f,0x18,0x37,0xb1,0x47,0xcd,0x66,0x98,0x4a,0x63,0x75,0x15,0x40,0x71,0x2d,0xfd,
++            0x44,0x02,0xc5,0x59,0xb1,0x03,0x42,0x99,0x26,0xc0,0x92,0x1d,0x3e,0xd3,0x32,0xe0,
++            0x4c,0x9d,0x8a,0x80,0xa5,0x2c,0x15,0xa4,0xb4,0xb4,0x83,0x44,0x50,0x7d,0x14,0x7a,
++            0x33,0xde,0x18,0xdc,0xfc,0xf5,0xd3,0x5c,0xe5,0x58,0xbd,0xc9,0x09,0x0e,0x7c,0xaf,
++            0x03,0xf7,0x8b,0x80,0x65,0xbd,0x89,0xaa,0x47,0xb7,0x9e,0x4d,0x9f,0xfd,0xed,0xff,
++            0x26,0xd1,0x84,0xcd,0x7c,0xd7,0x18,0xb5,0x71,0xb7,0x06,0x12,0x02,0x6e,0x4a,0x20,
++            0x95,0xf1,0xde,0x9c,0x8d,0xa1,0xd1,0x00,0x86,0x45,0x75,0x9d,0xe8,0x4b,0x14,0x38,
++            0xce,0xd1,0xc0,0x7d,0x37,0x8f,0x4e,0xca,0x94,0x81,0x99,0x1c,0x2b,0x5b,0x5d,0xeb,
++            0x05,0x3a,0x45,0xe3,0x04,0xb6,0x0e,0x88,0x32,0xd9,0xce,0x69,0x05,0xeb,0x2b,0xd5,
++            0x84,0xd7,0x1c,0xd7,0xcf,0x2a,0x05,0x88,0x07,0x46,0x85,0x39,0x16,0x4b,0xe4,0xa7,
++            0x2a,0xb3,0x8d,0x51,0x89,0x66,0x0e,0x8d,0x8b,0xc8,0x62,0x54,0x89,0x4e,0x77,0x07,
++            0x4e,0x66,0x0e,0x90,0xb1,0x34,0x1b,0xbc,0xf9,0xbd,0xc5,0xc0,0xa7,0x26,0xa8,0x0f,
++            0xef,0xa6,0x9e,0x8d,0x23,0x8e,0xd8,0x45,0x6c,0xc0,0x8c,0x25,0xfd,0x5a,0xd7,0x3b,
++            0xe5,0xeb,0x4b,0xb8,0x1a,0xab,0x07,0x9c,0x4a,0xcb,0x38,0x6c,0x5e,0xc6,0x20,0xcd,
++            0x8f,0x8f,0x43,0x2c,0xfe,0x40,0x0d,0x84,0xba,0xd3,0x0b,0x9c,0xaf,0xa3,0x2e,0xa9,
++            0xab,0xac,0x96,0x91,0x84,0xa6,0xdb,0x18,0x8f,0x6c,0x43,0x61,0x94,0xf2,0x1f,0xef,
++            0x10,0xbe,0x4c,0x94,0x4d,0x13,0x45,0xb0,0x5e,0xd1,0xcd,0xa5,0x45,0xbf,0x11,0xdd,
++            0x46,0xfb,0xae,0xa0,0xc3,0x40,0x54,0x53,0x87,0xd0,0x46,0x61,0xfa,0xf0,0x3d,0x9b,
++            0x05,0x0f,0x27,0xa0,0xe4,0xa3,0xb2,0xa4,0x42,0x84,0x90,0x64,0x54,0x48,0x98,0x7a,
++            0x20,0xf1,0xa7,0xec,0x11,0x63,0xac,0x63,0xcd,0xed,0x8e,0x56,0x7e,0x40,0x38,0x9b,
++            0xc9,0x0d,0x36,0xb4,0x49,0x5f,0x2b,0xc4,0x21,0x24,0xea,0xa7,0xda,0x16,0x32,0x56,
++            0x8f,0x9c,0x0a,0x39,0x49,0x00,0x61,0x62,0x4d,0x5f,0x7c,0x14,0x2f,0x42,0x4c,0xba,
++            0xeb,0xa7,0xda,0x45,0x31,0x64,0xfc,0xff,0x41,0xd6,0x10,0xe1,0x84,0x91,0x76,0xe0,
++            0xc1,0x05,0x8b,0x14,0x4f,0x3e,0x66,0xd4,0xce,0xb3,0xc3,0x0f,0xd3,0xd5,0x27,0x95,
++            0x69,0xe5,0xdd,0xce,0x94,0xac,0x6f,0xb0,0x80,0xb9,0x87,0x5b,0xb0,0x24,0x37,0xe5,
++            0x8a,0x98,0x90,0x33,0x6c,0x8a,0x11,0xf5,0xc5,0xcd,0xe7,0xd5,0x5c,0xc1,0x3d,0x8d,
++            0xf3,0xd5,0xd2,0x85,0x0e,0x33,0x3c,0x2e,0xd9,0x47,0xaf,0x6d,0x5e,0x40,0xf5,0xd2,
++            0xa2,0x48,0x0a,0xdc,0x1f,0x92,0x62,0x6b,0xc5,0x55,0x2a,0x7d,0xc8,0x2b,0xc7,0xf7,
++            0x75,0x68,0x5c,0x7b,0x15,0xac,0xa7,0x7a,0x44,0xe6,0xc5,0x6c,0xff,0x42,0x32,0x79,
++            0xd5,0xf6,0x09,0x99,0xda,0xf8,0x35,0x3f,0x58,0x0a,0xd1,0x3d,0x30,0xc1,0x44,0x75,
++            0xe3,0xc6,0x92,0x8b,0xc4,0x24,0xd5,0x2f,0xa3,0xef,0x41,0x2c,0x1e,0x2e,0x18,0xa7,
++            0xfc,0x4f,0xd6,0xb1,0xf2,0x2e,0x64,0xc8,0x89,0x4d,0x39,0x6d,0x27,0x4c,0x51,0xb6,
++            0x75,0x83,0x47,0x3e,0xb8,0x61,0x35,0xbd,0x21,0x7d,0x1f,0x1e,0xdc,0x0c,0x01,0x49,
++            0x62,0x2c,0x27,0xce,0xef,0x27,0x25,0xd1,0xe2,0x8c,0xc4,0x59,0xb8,0x4f,0xb0,0xe2,
++            0xd7,0x75,0x84,0x00,0x68,0x5c,0xff,0x4e,0x44,0x64,0x5e,0x94,0x8f,0x8f,0xe8,0x6a,
++            0x42,0x31,0x1d,0x8b,0x49,0x2a,0x19,0x6f,0x92,0x64,0x50,0x53,0x77,0xfb,0x3d,0x7e,
++            0x84,0x9f,0xda,0x8d,0xb6,0xe2,0x6d,0x61,0xac,0xbd,0xaf,0x15,0x0f,0x30,0xe9,0x6a,
++            0xc2,0x53,0x2b,0xf3,0x3e,0xb5,0x65,0x95,0x5f,0x8c,0xd1,0xf2,0x2f,0x79,0x0e,0x5d,
++            0xdd,0x78,0x53,0x34,0x02,0x95,0x43,0x13,0x58,0xc9,0x46,0xe1,0x50,0x15,0x5f,0x54,
++            0x60,0x15,0x7e,0x65,0x01,0x9a,0x06,0x0e,0x0b,0xf6,0x70,0x1c,0xd9,0x38,0x7b,0xf9,
++            0x7c,0xb9,0x90,0x36,0x36,0xbd,0x75,0x41,0xaa,0xa7,0x56,0x96,0xce,0xc9,0x73,0x70,
++            0x2c,0x91,0x69,0xb7,0x44,0x9a,0x23,0x40,0x80,0xa8,0xba,0x13,0xe1,0x3a,0xe2,0x76,
++            0x4b,0x78,0x86,0x4c,0x20,0x23,0x6d,0x4f,0x70,0xa6,0x54,0xdf,0x3f,0xf9,0xf4,0x90,
++            0xd0,0xd6,0xc6,0x03,0x38,0xf9,0x20,0x74,0xe6,0xdf,0x32,0x23,0x78,0x39,0xe3,0x76,
++            0x8c,0x87,0x5d,0xeb,0x47,0x97,0x6c,0x82,0x4b,0x1b,0x6c,0x52,0x11,0x59,0x0e,0xe7,
++            0x4e,0x0b,0xb1,0xa4,0x34,0x59,0x1f,0x79,0xed,0x72,0x93,0x47,0xff,0xf1,0x46,0x88,
++            0x70,0xb1,0x12,0x0b,0xe4,0x34,0x00,0x58,0x81,0xdf,0xb4,0xec,0xdd,0x67,0x9e,0x43,
++            0x28,0x9f,0x2d,0x9c,0x4d,0xe0,0x5e,0x38,0x6f,0x74,0x60,0x7c,0x59,0xbc,0x09,0x59,
++            0x51,0xb3,0xcd,0xbe,0x94,0x50,0x69,0x48,0x65,0xd8,0xa7,0x8b,0xea,0x7d,0x8f,0x09,
++            0xb2,0xbc,0x0b,0x23,0x46,0x53,0x3a,0x8a,0xcd,0x31,0x5f,0x3b,0x93,0x31,0x8c,0xa7,
++            0xfb,0x5d,0xff,0x0e,0x12,0x70,0x02,0x13,0xc0,0x6f,0xf2,0xdd,0xbd,0xa3,0x57,0x68,
++            0x2b,0x1e,0xa8,0xef,0x19,0xa5,0x9c,0xc1,0xc9,0x80,0x86,0xe7,0x35,0x3e,0xf5,0xfd,
++            0x7d,0xe1,0x30,0x18,0xe4,0x39,0x91,0x50,0x67,0x61,0x1d,0xbc,0xd7,0x40,0x40,0xf0,
++            0xa1,0x4e,0x2e,0xee,0xd9,0xe1,0x86,0x6f,0xe4,0x81,0xc6,0x44,0xf3,0x8f,0x8c,0xd0,
++            0x06,0x8c,0xb9,0x35,0x78,0x2b,0x76,0x5f,0xaf,0x0e,0x88,0x59,0x3c,0x31,0x0a,0x53,
++            0x04,0xc5,0x92,0x36,0x0f,0xe7,0x40,0x8d,0xb6,0x87,0x68,0x04,0xbc,0x94,0xe2,0x30,
++            0xac,0xe8,0xb9,0x42,0x7f,0x65,0x0e,0x9b,0xc6,0x67,0xa3,0xe3,0xff,0x1c,0x65,0xa9,
++            0x81,0x0d,0xa3,0x6a,0x7e,0xa4,0xb5,0x95,0x2e,0x84,0x06,0x9f,0xa0,0x2a,0x59,0x02,
++            0xe9,0x37,0xe8,0xb2,0x44,0xea,0x8d,0x4a,0x44,0x18,0xd5,0x6e,0x58,0xc0,0x90,0xe5,
++            0x29,0x84,0xf1,0x1e,0x66,0x09,0x1f,0x3c,0xd9,0xad,0xc4,0x8b,0xa8,0xed,0x22,0x7d,
++            0x7b,0x9a,0x20,0x23,0x40,0x3b,0x0c,0x84,0xc4,0xba,0xc8,0x5c,0xb6,0x1b,0x50,0x3c,
++            0x2c,0x34,0x04,0x70,0x40,0x70,0x43,0x1c,0x12,0x54,0xa9,0x2e,0xa1,0x46,0xe5,0x0b,
++            0xfd,0x2c,0x0e,0xd1,0x1f,0x05,0x9e,0xf8,0x4e,0xc4,0x09,0x29,0x50,0x43,0xae,0xa9,
++            0x7b,0x20,0xd4,0x3c,0x7e,0x8d,0x9d,0xba,0x53,0x8f,0xe2,0x6f,0x34,0x9c,0xf4,0x38,
++            0xfe,0xe2,0xff,0xc8,0x98,0xc4,0x37,0xef,0x8d,0xe4,0xe0,0x87,0x4a,0xa3,0x78,0xde,
++            0x81,0xed,0xf3,0x92,0x99,0x25,0x31,0x66,0x26,0x6c,0xff,0x82,0xdb,0xec,0x9b,0x74,
++            0x00,0x0d,0xda,0xbf,0xdd,0x21,0x53,0x26,0x19,0xf1,0xb9,0x17,0x16,0x5f,0x98,0xec,
++            0x86,0xf4,0xd2,0xaa,0xd4,0x1e,0x66,0x9a,0x19,0x7e,0x2b,0xc5,0x32,0x70,0x5d,0xa4,
++            0x5d,0x9d,0x61,0x02,0xf7,0x41,0x96,0x13,0x38,0x71,0x67,0xe6,0x07,0x52,0x92,0x71,
++            0x81,0x86,0x3a,0xe4,0xc9,0xdf,0x9d,0x43,0x01,0x00,0xb9,0x48,0x14,0xb1,0x36,0x31,
++            0x40,0xf8,0x20,0xfa,0xdd,0xb7,0x16,0xe2,0x65,0x94,0x66,0x0e,0xd4,0x7f,0x39,0xa1,
++            0x45,0x43,0xbc,0x52,0x74,0x27,0x71,0x43,0x05,0x7a,0xef,0x10,0x57,0xe4,0x5b,0x72,
++            0x78,0x39,0x09,0x54,0xce,0xbe,0x69,0x68,0xe0,0x5c,0xf1,0x01,0xe6,0x7d,0x13,0x7b,
++            0x8e,0x54,0xe5,0x4b,0x84,0xac,0xaf,0x0f,0xe7,0x7a,0x37,0x1f,0xa2,0xba,0x86,0x99,
++            0xa0,0x97,0xc4,0x86,0x3d,0xf8,0x48,0xad,0xcd,0x77,0x7a,0x48,0x95,0xbb,0xee,0x1a,
++            0xe9,0xdb,0xd0,0x2a,0xd6,0x5a,0xe7,0xba,0x96,0x42,0x78,0xcd,0x5b,0x97,0x4f,0x8c,
++            0x2f,0xde,0xa3,0x45,0xdf,0x45,0xe3,0xd8,0xab,0xa5,0x5b,0x3d,0xfc,0xf2,0x6f,0x8d,
++            0xab,0x99,0x91,0xa2,0x5f,0xab,0x3f,0x3f,0xb9,0x8a,0xdd,0xbe,0xfe,0xbb,0x60,0xf7,
++            0x4d,0xdc,0x5e,0x31,0xd7,0xbf,0x20,0xdb,0x29,0x73,0x0d,0x1f,0xdd,0x5c,0x54,0x6b,
++            0x4d,0x32,0xd0,0x7e,0x98,0x1d,0x00,0x52,0xef,0x8e,0xa7,0x2e,0xda,0x62,0x71,0x7a,
++            0x45,0x3d,0x0b,0x50,0xbf,0xde,0x22,0x95,0x84,0x5d,0xc5,0xdf,0xb6,0x41,0x3d,0x5f,
++            0xec,0xb5,0xa7,0x5b,0xb0,0x12,0xbf,0x3e,0x06,0xd2,0x13,0x64,0xfe,0x6f,0x59,0xb7,
++            0xa5,0x6e,0x6b,0x44,0x1c,0x21,0xa8,0xde,0x50,0x0d,0xc9,0xd8,0xb5,0x9f,0x52,0x11,
++            0x81,0xc3,0xab,0x62,0xdb,0x50,0x9e,0x77,0xa0,0xb7,0x58,0x88,0x4f,0x6b,0x63,0x00,
++            0x83,0x43,0x17,0xd0,0x1d,0x39,0xee,0x5f,0xe2,0xaf,0xee,0xdd,0xd0,0x0c,0x32,0xe0,
++            0x22,0xa3,0x73,0xf5,0x95,0x6d,0xe6,0x43,0x17,0x9c,0x9f,0xb1,0xab,0xbd,0xfa,0xa0,
++            0x42,0x14,0x99,0xdd,0xb7,0xdb,0x28,0xe2,0x60,0x74,0x90,0xfc,0xd1,0x69,0x93,0x26,
++            0x8e,0x47,0xea,0xa7,0x31,0x88,0xf0,0x60,0xa2,0x5e,0x65,0x29,0xac,0x38,0x9b,0x45,
++            0xa6,0x1d,0xff,0x91,0x4e,0x29,0x69,0x89,0x4e,0x89,0xac,0xa7,0x73,0x79,0x9a,0xd8,
++            0x80,0xc5,0x03,0x4a,0x30,0xa3,0x4f,0x97,0xe1,0xf7,0x52,0x8b,0x6a,0xdf,0x30,0x38,
++            0x40,0xb7,0x13,0xac,0x2c,0x21,0xbe,0x57,0x82,0xb0,0xda,0x25,0x6b,0xfc,0x4f,0xf0,
++            0xe7,0x44,0xfb,0x7a,0xea,0x39,0x5e,0xf8,0x09,0x9c,0xfc,0x11,0xbe,0x72,0xb8,0xce,
++            0x52,0x02,0x43,0xb4,0x77,0x31,0x2d,0x75,0xce,0x99,0x29,0x4d,0x98,0x06,0x11,0x18,
++            0xa8,0x5b,0x33,0xe6,0x14,0xd6,0x90,0x06,0x94,0x50,0xb8,0x4b,0xfa,0x2b,0x82,0xf1,
++            0xdd,0x06,0xfc,0xae,0x3b,0x6c,0x46,0xea,0x68,0xbc,0xad,0x06,0x0b,0xf3,0x5c,0x75,
++            0xac,0x40,0xdc,0xfc,0x59,0x89,0xb8,0x91,0x2f,0x22,0x1a,0xfc,0x76,0xcd,0x07,0xa1,
++            0x3c,0x43,0xc5,0xed,0x73,0xe4,0x6b,0x2e,0xf9,0x2a,0xbb,0x6b,0x59,0x0a,0xe7,0xcb,
++            0xc3,0x07,0x9b,0xbf,0x5b,0x34,0x02,0x4d,0x6e,0xb0,0x8f,0x6c,0xa7,0x6b,0x5d,0x36,
++            0x87,0x0b,0x97,0x00,0x46,0x20,0xc7,0x92,0x53,0x3c,0x54,0x1d,0xcb,0x1e,0x8d,0xd0,
++            0x61,0x5f,0xf9,0xf2,0xfb,0xa0,0xa4,0x77,0xa3,0x01,0x99,0x30,0x07,0x79,0xf7,0xe7,
++            0x2f,0x94,0xcd,0x05,0x3d,0x29,0xad,0x90,0xdc,0x1d,0x55,0x19,0xa4,0x7a,0x1c,0xe3,
++            0x06,0x10,0x75,0x1d,0x14,0xb5,0x15,0x30,0x00,0x1c,0xc4,0xaf,0x96,0xb5,0xd2,0x26,
++            0xaf,0x2f,0x3b,0xb7,0x18,0x5a,0xea,0x08,0xa2,0x92,0xd5,0x86,0xf0,0xe1,0xae,0x23,
++            0x57,0x13,0x98,0xa6,0xd8,0xc4,0x64,0x0e,0x9e,0x81,0x9a,0x96,0x8c,0x73,0xe7,0xb6,
++            0x91,0x92,0x22,0x85,0xb6,0xc2,0xaa,0x63,0xc0,0x46,0x8f,0x07,0xf4,0x5c,0xbf,0xc7,
++            0xa5,0x3d,0xf3,0xe8,0x3e,0x91,0x25,0xe3,0x08,0x86,0x2f,0x78,0x52,0xa8,0x17,0x14,
++            0x1b,0xdf,0x86,0x6a,0x0b,0xac,0x46,0x89,0x38,0x1a,0xb6,0x94,0xf7,0x85,0x57,0x74,
++            0xcc,0x10,0x34,0x7c,0x23,0x15,0x47,0xa3,0x0e,0xd9,0xe7,0xc0,0xeb,0x71,0xbf,0xb8,
++            0x94,0x55,0x5d,0x11,0x8b,0xae,0xc7,0x74,0xeb,0xba,0xf1,0x95,0x9b,0x7e,0x0d,0xeb,
++            0x9a,0xdc,0x0b,0x19,0xc3,0xd4,0xb7,0x09,0xcd,0x58,0x9a,0x39,0x8f,0x73,0x5e,0xdb,
++            0x89,0x1f,0x96,0x0c,0x6f,0x7e,0x36,0x5e,0x38,0x1e,0x69,0xd0,0xf8,0xe9,0xc9,0x3a,
++            0xc2,0x1e,0xe6,0xda,0x9a,0x22,0x9b,0x8b,0xc8,0x52,0xfa,0xbc,0x18,0x4e,0x27,0x7a,
++            0x36,0x95,0x8b,0xe8,0x3b,0x5a,0x1b,0x89,0x68,0x99,0x89,0x0f,0xde,0x78,0x57,0xcc,
++            0x08,0x19,0x7b,0xbf,0x00,0x5a,0x9f,0x90,0x56,0x59,0xa7,0xda,0x98,0x5c,0x7a,0x06,
++            0xa3,0x92,0xc7,0xf9,0xe1,0x36,0x43,0xa6,0x3e,0xdd,0x58,0x0a,0x76,0xb1,0x08,0x9b,
++            0xe4,0x9a,0xa8,0xd1,0xe8,0x17,0x39,0x4d,0xe2,0xc2,0xe0,0xb2,0x66,0x8b,0x99,0x32,
++            0xb8,0xcd,0x5a,0x3c,0xe4,0x39,0x79,0xa7,0x31,0x8d,0x29,0xcf,0xe3,0x2f,0xdf,0xf5,
++            0x97,0xcc,0xf3,0x15,0x26,0x7a,0x2d,0x3f,0xc3,0x80,0x01,0xd7,0x8d,0xf8,0x65,0xaa,
++            0xde,0x4f,0xa7,0xa0,0xf7,0x0b,0x20,0x15,0x5e,0x4b,0x45,0x77,0x22,0xc9,0x99,0xb4,
++            0x23,0x9e,0xaf,0x30,0xe8,0x08,0xdc,0x84,0xc0,0x45,0x98,0x4c,0x74,0xea,0xe5,0x67,
++            0x67,0x9d,0xb5,0xb4,0xe2,0xbd,0x73,0x85,0x67,0xdd,0x67,0x8f,0x16,0x2b,0x99,0xab,
++            0x69,0x3c,0x7a,0x10,0x49,0xad,0x20,0x47,0x62,0xdc,0xa0,0x61,0x32,0x82,0x02,0x8b,
++            0x3f,0x4f,0xc3,0x4e,0x08,0xb3,0xfd,0xea,0x04,0x8a,0xee,0x58,0xa3,0x84,0x22,0x0b,
++            0xf8,0x7f,0xeb,0x78,0x6f,0xad,0x63,0x7d,0x2e,0xb9,0x69,0xa2,0x5c,0xa9,0x9b,0xf5,
++            0x03,0x7c,0xd6,0x69,0xe4,0xe5,0xe0,0x19,0x4c,0xcb,0x8d,0x72,0x02,0xa8,0xd3,0x19,
++            0xcd,0x06,0xe9,0x58,0x7c,0x0d,0xc3,0x39,0xed,0x89,0x9b,0x87,0xee,0xfc,0x66,0xa7,
++            0x06,0xd7,0xb8,0xca,0x15,0xcd,0x64,0x8c,0xaf,0xca,0x8a,0x86,0x4a,0xa1,0x6a,0xa7,
++            0x2f,0xcf,0xea,0x5e,0x1f,0xc1,0x3f,0x9c,0x49,0xc6,0xc1,0x59,0xfc,0x88,0x43,0xa2,
++            0x60,0x55,0x23,0xcf,0xe3,0xae,0x05,0x21,0x6d,0xd5,0x88,0x67,0x7b,0x51,0x6c,0x49,
++            0x6e,0x94,0xd5,0x8b,0x55,0xac,0xb6,0x3c,0xf4,0xab,0xc4,0x9d,0x5d,0xec,0xdc,0x6a,
++            0xc2,0xdd,0xfd,0x98,0xd1,0xdc,0x26,0xa6,0xcc,0x5b,0xed,0xbc,0x13,0x22,0xaa,0xe0,
++            0x82,0x8a,0xcb,0x66,0xb5,0xae,0x90,0xc1,0x38,0x27,0x7c,0x0f,0xce,0xea,0xc9,0x11,
++            0xb4,0x9a,0x61,0x7c,0x39,0x4f,0x6c,0x42,0x01,0x2d,0x95,0x2f,0xc7,0xe5,0x0a,0x67,
++            0xad,0xd2,0x36,0x1d,0xb6,0x33,0xfd,0x0f,0xb3,0xd9,0x66,0xc1,0x0e,0x9f,0x96,0xd4,
++            0x87,0x14,0xdc,0x28,0x9a,0xb9,0x86,0x6b,0x9b,0xdb,0x8c,0xc1,0x34,0xfb,0x54,0x15,
++            0xe5,0xc5,0xd1,0x94,0x96,0x38,0x04,0x70,0xe7,0x91,0xa6,0x76,0xd4,0x90,0x1d,0x41,
++            0x40,0x52,0x18,0xad,0x37,0xbb,0x4f,0x61,0x00,0xfc,0xcf,0xc0,0x55,0x93,0x65,0xda,
++            0xc4,0xc7,0x32,0xd6,0x40,0x08,0x45,0x1b,0xbd,0x98,0x85,0x1f,0xf7,0x6c,0x36,0xba,
++            0x20,0x9b,0xff,0x94,0x5b,0x7e,0x2d,0x42,0xb8,0x15,0x8c,0x35,0x7a,0x2b,0xd0,0x72,
++            0x1a,0x54,0x3f,0xd9,0x0e,0x2d,0xd2,0x3e,0x1b,0xeb,0x6d,0xfe,0x4e,0x6d,0x32,0xe2,
++            0xaa,0xe2,0xb7,0xbf,0xb8,0x96,0xf3,0x2e,0xaf,0x29,0xb6,0x6f,0xb0,0xb8,0x77,0xda,
++            0x9e,0xf0,0x15,0x0c,0x81,0x74,0x77,0xb3,0xeb,0x68,0x65,0xb3,0xce,0x6f,0x1e,0x48,
++            0xc4,0xe8,0x9d,0x3e,0x98,0x1d,0xce,0x0a,0x6a,0x5c,0xd6,0x17,0x76,0x87,0x3e,0xd2,
++            0x4c,0xbd,0xbc,0x69,0xd4,0xd9,0x92,0x68,0x33,0xd5,0x86,0x02,0x7f,0x06,0x3d,0xd6,
++            0x0d,0x98,0xb3,0x3c,0x3a,0x33,0x8f,0x03,0xb4,0x93,0x08,0x03,0x8b,0xc5,0x17,0x59,
++            0x8d,0x4f,0xd7,0x34,0x0c,0xfd,0xfb,0x0b,0xb3,0x90,0xef,0xfb,0xa7,0x7b,0x5e,0xa5,
++            0xe4,0xab,0xb1,0x28,0x00,0x24,0xcf,0xf2,0x37,0xb6,0x93,0x65,0x50,0xc4,0x9e,0x63,
++            0x6d,0x6d,0x4c,0x4a,0x1f,0x3f,0x90,0xdc,0x41,0xcc,0x48,0x75,0x51,0xec,0x53,0x29,
++            0x61,0xad,0x03,0x5b,0x34,0xcf,0xd1,0x44,0xa0,0x39,0x06,0x84,0x18,0x61,0x6f,0xc0,
++            0x80,0x43,0xf0,0xea,0x1c,0xa5,0x66,0xcc,0xc3,0x98,0xe7,0x94,0x3a,0x20,0x80,0xf0,
++            0x21,0xb1,0x3f,0xac,0x65,0xe9,0x0b,0x42,0x39,0x64,0xb0,0x46,0x91,0x69,0x89,0x95,
++            0xea,0xcf,0x08,0xe4,0x9b,0x2d,0x05,0xa2,0x45,0xf5,0x74,0x0b,0x89,0x9a,0x91,0x7b,
++            0xa8,0x44,0x6d,0xc0,0x69,0x48,0x8c,0x60,0xf5,0xb0,0xaa,0x42,0x73,0xd9,0x17,0xb3,
++            0x87,0x82,0x49,0x44,0xeb,0x87,0x7b,0x99,0xb4,0x8a,0x62,0xef,0x24,0xca,0x0e,0x95,
++            0xe1,0xc2,0x8a,0x4c,0x1c,0xd3,0x22,0xac,0x71,0x12,0xec,0x04,0xb1,0x79,0x9f,0xe9,
++            0x7b,0xb8,0x1b,0xe3,0x45,0x94,0x0b,0x7f,0x83,0x83,0x1c,0xb8,0x77,0x9e,0x7c,0xf1,
++            0x88,0x71,0x54,0x7f,0x6f,0x81,0x29,0xda,0xf8,0xe7,0x3f,0xbe,0x9f,0x60,0xbc,0xa9,
++            0x7d,0x68,0x89,0xee,0xa9,0x86,0x53,0x25,0xcf,0xc8,0x9d,0x15,0x59,0x24,0xf1,0xaa,
++            0x62,0x8f,0x54,0x0d,0xa2,0x37,0xad,0x93,0xc7,0xe1,0x9c,0x5c,0xad,0xd3,0x9e,0xab,
++            0x25,0xad,0x96,0x2a,0xa4,0x76,0x23,0x09,0x1e,0x5b,0x1a,0x60,0x6f,0xe0,0x3d,0xf9,
++            0x7f,0xad,0x18,0x3b,0x65,0x35,0xdc,0xf2,0xa9,0x4a,0xe9,0xdd,0x25,0xf1,0xdd,0x58,
++            0x93,0x09,0xcb,0x60,0x70,0xbe,0x13,0x71,0x36,0x23,0xa5,0x50,0x30,0xfe,0x5f,0x80,
++            0x5b,0x18,0xba,0xac,0x72,0x9f,0xef,0x87,0xc1,0xaf,0xf2,0x04,0xf2,0x97,0x0e,0x63,
++            0x19,0x9c,0x66,0xe6,0xda,0x12,0x22,0x11,0x17,0xfe,0xd4,0x14,0x77,0xf2,0xc5,0x9d,
++            0x94,0xef,0x14,0x94,0x80,0x36,0x03,0x05,0x0b,0xc3,0x6c,0xc7,0x3a,0x83,0x73,0xbd,
++            0x69,0x22,0xf3,0x31,0x5a,0x02,0x88,0xf6,0x08,0x10,0x91,0x5d,0x86,0xbe,0xfb,0x45,
++            0xdd,0x12,0x7b,0xe9,0xcd,0xe9,0x6c,0x1b,0x9f,0x16,0x14,0x54,0xee,0xc2,0xf8,0xaf,
++            0x80,0x98,0xac,0x67,0xff,0x38,0xf9,0x6b,0x92,0xdc,0xa2,0xdd,0x75,0xf6,0xb3,0x3b,
++            0x57,0x19,0x14,0x3b,0x53,0x89,0x81,0xf3,0xe4,0xd5,0xab,0xc9,0x47,0xe0,0x2d,0x66,
++            0x14,0x18,0xb4,0xf2,0x12,0x08,0x7d,0x1b,0x56,0xde,0x93,0x71,0xdd,0x23,0x17,0xfb,
++            0x18,0x76,0xf8,0xa4,0xd1,0x29,0xf1,0x5b,0x1c,0xf5,0x3a,0x29,0x83,0x14,0x30,0xb0,
++            0x27,0xb6,0xcd,0x18,0x5b,0xd8,0x4e,0xcf,0x21,0xd4,0xe7,0xc0,0xeb,0x73,0x65,0x89,
++            0xa9,0x2a,0x2b,0x1e,0xff,0x30,0x43,0x37,0x03,0xeb,0x28,0x36,0x9b,0x7e,0x1e,0x88,
++            0x9d,0x1f,0x70,0xda,0x73,0x6a,0x61,0x80,0x02,0x8a,0xd8,0xce,0x85,0x74,0xf2,0x2a,
++            0x0e,0x69,0x72,0x48,0x58,0x48,0x76,0x62,0x69,0x1d,0xee,0x16,0xd6,0x71,0x1c,0xe6,
++            0x05,0x5f,0x8e,0x34,0x34,0x70,0x0c,0xa1,0x6d,0x3e,0xe5,0x72,0xcc,0x11,0x15,0xe7,
++            0x84,0xeb,0x07,0xd0,0x09,0x34,0x97,0x4c,0x6e,0x1c,0xa8,0xaa,0x64,0x01,0xd7,0xea,
++            0x8f,0x92,0x97,0xd0,0x39,0x98,0xff,0x97,0x48,0x3a,0xe1,0xd1,0x25,0xd2,0xe0,0x67,
++            0xac,0x0b,0xb1,0xc1,0xca,0xaa,0xa6,0x12,0x4e,0x82,0x87,0xf2,0x52,0x63,0x88,0x60,
++            0x67,0xb7,0x7c,0xd9,0xee,0x2a,0x3e,0x1a,0xc5,0xbc,0x9e,0x92,0x77,0x4c,0x79,0x32,
++            0xe8,0x2d,0xb3,0xf7,0x96,0xe0,0xe5,0xf8,0x84,0xcd,0xb2,0x34,0xfe,0x13,0x57,0x14,
++            0x24,0x88,0x2e,0x93,0xbb,0xdd,0x95,0x41,0x0f,0x12,0x2e,0x97,0x38,0x93,0x96,0xa9,
++            0xa7,0xea,0x59,0xe3,0xfd,0xd5,0xb4,0x93,0x3f,0xc4,0xae,0x53,0x5e,0x49,0x52,0xb0,
++            0x85,0x62,0xed,0xbe,0x18,0xe8,0xee,0x01,0x2b,0xa9,0x6e,0x31,0x8d,0xef,0x03,0x09,
++            0x87,0xd7,0xb8,0xab,0x73,0xad,0x0f,0x1f,0x27,0x69,0xbf,0xf7,0x2d,0x4b,0x12,0x31,
++            0x70,0xe2,0xb1,0x47,0x12,0x44,0x1f,0xa2,0xc4,0xae,0xb2,0x86,0x74,0xa7,0xa2,0x2b,
++            0x90,0xca,0xb5,0xf5,0x7f,0x8a,0x4c,0x8e,0xad,0x6e,0x1e,0x5c,0x96,0xeb,0x19,0x23,
++            0x0b,0xdb,0xd4,0x37,0x92,0x7f,0xad,0x29,0x6b,0xca,0x2d,0xcd,0x21,0x85,0x71,0xeb,
++            0x74,0x5b,0x63,0xaa,0x03,0x1b,0x24,0xd8,0xe6,0x65,0xcd,0x8f,0x3d,0x4c,0xe7,0x9f,
++            0xef,0xa3,0xa3,0x0a,0x69,0x9a,0x5b,0x8c,0x3e,0xc6,0xdb,0x88,0x62,0xe6,0x5a,0xb5,
++            0x8c,0x6b,0xc2,0x76,0x3e,0x4f,0x4c,0x5f,0x0e,0x33,0xcc,0x5b,0xbe,0x6d,0x0a,0xed,
++            0xb8,0x80,0xf9,0xa6,0x1f,0x16,0x32,0xc7,0x49,0xae,0xc2,0x84,0xf3,0xe0,0x9e,0x29,
++            0xf2,0x71,0xb1,0x71,0xa2,0x5b,0xcc,0x2c,0x04,0x64,0x1b,0xeb,0xf0,0xba,0xb8,0x1c,
++            0x81,0x50,0xed,0xdb,0xc7,0xc3,0xdb,0x19,0x3c,0xaa,0x84,0xfb,0xf1,0xab,0x5c,0x06,
++            0x0a,0x5d,0xac,0x9b,0xdd,0xe1,0x0a,0x8f,0x46,0x3d,0x00,0xd5,0x56,0xff,0x9f,0x37,
++            0x23,0xf8,0x40,0x08,0x36,0x11,0x42,0x8a,0x8c,0x00,0x84,0x25,0x57,0xf7,0x7e,0x1c,
++            0x58,0x11,0xb7,0x83,0x43,0x4f,0x33,0xd1,0x0f,0xa3,0x19,0x25,0x1a,0x4d,0xc2,0xe0,
++            0xe2,0xec,0x6d,0x32,0x4b,0x13,0x8e,0x8a,0x55,0x82,0x4b,0x4d,0x54,0x55,0x1a,0xea,
++            0xcd,0x25,0x42,0x42,0x34,0x4d,0xc9,0x00,0x0d,0xdb,0xe1,0x78,0x75,0xd5,0xa6,0xa0,
++            0xcc,0x4d,0x7c,0x54,0xdd,0x51,0xda,0x81,0x5b,0xda,0x1f,0xb6,0x61,0xb7,0x75,0x5f,
++            0xa2,0xb2,0xe5,0xc7,0xb6,0xb6,0xf5,0x9c,0xe0,0xb5,0x59,0x88,0x28,0xab,0x13,0x8e,
++            0xd8,0x86,0x2d,0x57,0xca,0xb7,0xc9,0x80,0x97,0xd8,0x29,0xf1,0xf1,0x74,0xff,0x8a,
++            0xd4,0xc9,0xb3,0x9f,0x0c,0xbc,0x37,0xa8,0x28,0x04,0x21,0x6e,0x30,0x55,0xee,0xeb,
++            0x75,0xdb,0xcc,0x9e,0x3c,0x59,0xfa,0x70,0xde,0x66,0xee,0x5c,0xff,0x1e,0xf8,0x59,
++            0xdb,0x6c,0xc8,0xfc,0x84,0xd4,0x87,0xdc,0xe2,0x06,0x20,0x4d,0x50,0x57,0xfb,0xed,
++            0xde,0x6d,0x98,0xb6,0xbb,0x38,0x01,0x83,0x19,0xaa,0xc2,0xdd,0xbd,0xf4,0xbd,0xfc,
++            0x28,0xcf,0xe6,0xce,0x3e,0x11,0x48,0xdf,0x4d,0x9c,0xf9,0x06,0x09,0x31,0x16,0xde,
++            0xcf,0x62,0x2e,0x7b,0xab,0xb0,0x0c,0x7e,0x41,0x99,0xb6,0xe3,0x79,0x7e,0x9c,0xb8,
++            0xe5,0x35,0xa9,0x4b,0xdc,0x87,0xd0,0xc3,0xb2,0xf6,0x5b,0x6b,0x9c,0x24,0xdc,0x39,
++            0x9c,0x11,0x14,0xf8,0x1e,0x40,0x47,0x05,0x43,0xd2,0xb1,0x7b,0xd1,0xab,0xc0,0xb0,
++            0x59,0x04,0x19,0x88,0x23,0xf2,0x24,0xde,0xa9,0xc9,0xb0,0x21,0x3b,0xa8,0xbc,0xd7,
++            0xe8,0x90,0x32,0xfb,0x6d,0x9e,0x2c,0x49,0x72,0xd3,0x67,0x12,0x1d,0x06,0x03,0x10,
++            0xec,0x2b,0x39,0xfa,0xa3,0x16,0x0b,0x20,0xe1,0x02,0x95,0x56,0xb1,0xe0,0x6f,0x6d,
++            0x68,0x72,0xb3,0xb0,0x62,0x38,0xa1,0xd1,0xd3,0x58,0x79,0x08,0x75,0x33,0x9b,0xa8,
++            0x4c,0x49,0xd0,0xc4,0xb3,0xa6,0xe8,0x24,0x7a,0x40,0xc0,0x21,0xaf,0x6b,0xe4,0xcf,
++            0x00,0xc4,0xd9,0xd0,0x33,0x27,0x62,0x8f,0xc3,0x27,0x18,0x54,0x51,0xee,0xbe,0xa9,
++            0xee,0x4b,0xb9,0xb5,0x35,0x87,0x90,0x90,0xfa,0x66,0x8b,0x83,0xba,0x77,0x10,0x46,
++            0x66,0x81,0xf1,0x45,0x30,0x92,0x67,0x58,0x80,0x48,0xdd,0x97,0xb8,0x68,0x64,0x71,
++            0x09,0x2a,0xa6,0x7a,0xaf,0x85,0x02,0x4e,0xb7,0x0a,0x72,0x8c,0x6b,0xa8,0xf5,0x6b,
++            0x35,0xaa,0x75,0x22,0xba,0x6b,0xa5,0xde,0x7a,0x68,0x22,0xcf,0x4c,0x72,0x3d,0x31,
++            0xe0,0xd3,0x9d,0x03,0x3b,0xaf,0xd4,0x5b,0xfb,0x2a,0x2b,0xde,0xc1,0x7a,0x14,0x5e,
++            0x87,0xa4,0x8c,0x5a,0xaa,0xeb,0xa3,0xc6,0xcf,0xf2,0x9a,0x5b,0x32,0x13,0x46,0x08,
++            0x0e,0x4b,0x54,0x73,0x2a,0x6e,0x4a,0x71,0xab,0xe3,0x52,0x1f,0x36,0x2e,0x1a,0xd9,
++            0x43,0x09,0xca,0xd8,0x3b,0x45,0x4c,0x4d,0x4d,0x4c,0xcb,0xf8,0x7b,0xcb,0xc2,0xe9,
++            0x9e,0xae,0x59,0x3d,0x9c,0x2f,0x46,0x96,0xa9,0xc2,0xc3,0x49,0x25,0xc3,0x4a,0xf9,
++            0x81,0xaf,0x74,0xbf,0xf8,0xa3,0x56,0x0b,0x68,0xc4,0x85,0x9f,0xdf,0xc2,0xe7,0x04,
++            0x72,0xfa,0x84,0x00,0x68,0x5c,0x4d,0xb8,0xc5,0xef,0xb2,0xb0,0xf7,0x32,0x42,0x50,
++            0x39,0xe4,0xb7,0x28,0xc2,0x6c,0x16,0xb2,0x9e,0x4a,0x22,0xf3,0x42,0x95,0x3b,0xb4,
++            0x2d,0xb4,0x3a,0xb4,0xf9,0x8d,0xa5,0x30,0x01,0x31,0x7d,0xa1,0xcb,0xd6,0x9b,0x15,
++            0x8b,0x80,0x9b,0xf7,0x79,0x9a,0x5e,0xd7,0x20,0x30,0x7f,0xf5,0x8c,0x3f,0x2c,0xc6,
++            0xa1,0x70,0x6b,0x40,0x5f,0xea,0x94,0xc0,0x32,0x59,0xc2,0xcc,0xc1,0x69,0x9c,0xa2,
++            0xc8,0xf4,0x5a,0x50,0x68,0xb9,0x9c,0xd0,0x1b,0x58,0x85,0x30,0xd6,0xaa,0x2d,0x23,
++            0x21,0x1b,0xea,0xae,0x6b,0xc3,0x0d,0xe5,0x4b,0xa8,0xfd,0x87,0x57,0x89,0x17,0x83,
++            0xcb,0xf6,0x0d,0xf5,0xe3,0x3a,0x20,0x03,0xc0,0x17,0x62,0xa9,0x0c,0x79,0x00,0xbd,
++            0xa8,0x17,0xfe,0xbe,0xc7,0x54,0xc2,0x78,0xe9,0xa0,0x17,0x44,0xb0,0xb3,0xf5,0xbf,
++            0x88,0xe6,0xe8,0x7e,0xce,0x22,0x26,0xe5,0x96,0x1c,0xc3,0xbf,0x94,0x62,0xef,0x3c,
++            0x8c,0x17,0xb8,0x12,0x47,0xa7,0xe8,0xda,0xcd,0xfb,0x97,0x45,0x70,0xba,0x50,0x4b,
++            0xda,0x3e,0x4c,0xfb,0x85,0x84,0x1e,0xcb,0xc7,0x84,0x3f,0x2b,0xf8,0xa1,0x86,0xe8,
++            0x33,0x11,0x39,0x3c,0xfb,0x0d,0x6a,0x8c,0x09,0xd5,0xee,0x06,0x87,0x33,0x82,0x28,
++            0x8c,0x5f,0xb6,0x2c,0x5a,0x0c,0x4b,0x10,0xeb,0x10,0xe0,0xd4,0xf6,0xfb,0xab,0x5b,
++            0xaa,0x16,0x07,0xed,0xa3,0xc3,0x42,0x03,0x4f,0xf1,0xf7,0xe4,0xb2,0x6f,0x5f,0xc5,
++            0x0a,0x14,0xb6,0xae,0x83,0x70,0xa0,0x92,0x66,0xa9,0x58,0xbd,0x35,0xdf,0x3f,0x7d,
++            0x0a,0x2f,0x1b,0xe0,0x04,0x5d,0x27,0xca,0x0c,0x3d,0xb1,0x40,0xbf,0x78,0xe8,0xb7,
++            0xd3,0xc3,0xf0,0x06,0x26,0xa0,0x2c,0x54,0xba,0x83,0x84,0xb2,0x68,0x44,0xba,0x87,
++            0xaa,0x5f,0x59,0xef,0xc6,0xef,0xc9,0x21,0x82,0xd9,0x86,0x73,0xd2,0x98,0x6a,0xc6,
++            0x6c,0x62,0x89,0x13,0xa6,0x82,0xfe,0x41,0xf6,0x63,0x87,0x47,0x5a,0x45,0xa0,0xa3,
++            0x71,0x80,0xf5,0xc2,0x36,0x9c,0x6a,0x53,0x2a,0xdb,0x66,0xe4,0xf6,0x9e,0xa8,0x86,
++            0x4d,0x9e,0x6a,0xd2,0x37,0x14,0x68,0x97,0xba,0xca,0xc6,0x5e,0x51,0xe4,0xe5,0xc7,
++            0xad,0xed,0xdb,0xa5,0xa5,0xfd,0x4f,0x4a,0x61,0x84,0x31,0x47,0xbe,0x19,0xff,0x35,
++            0xc7,0xc8,0xb3,0xa8,0x34,0x8a,0x7f,0x46,0x2e,0x26,0x8d,0xf3,0xf7,0xe2,0x3a,0x03,
++            0x46,0x69,0x1a,0xfd,0x55,0xb3,0x8d,0xcc,0x7f,0xc9,0xac,0xee,0x58,0xc4,0x79,0x18,
++            0xa2,0xcb,0x55,0x6c,0x7f,0x56,0x2d,0xd2,0x41,0x34,0xe6,0x8b,0x36,0x60,0x94,0x3e,
++            0x8a,0xa9,0x03,0x79,0xfc,0x55,0x8b,0xd4,0xca,0x73,0x60,0x5d,0x23,0xa8,0xff,0x65,
++            0x8b,0xe8,0x50,0x24,0xf4,0x30,0xc3,0xbf,0xbf,0x44,0xbb,0x99,0xc9,0xf0,0x42,0x43,
++            0x3d,0x6d,0x0d,0x5f,0x2e,0x80,0x68,0x77,0x6d,0xda,0xa8,0x87,0x58,0xed,0xaa,0x32,
++            0xc9,0xcf,0x6d,0x3e,0x13,0xc7,0xec,0x3d,0x85,0x75,0x5f,0x4f,0x6f,0xf2,0x59,0xad,
++            0x09,0xce,0x5a,0x3c,0xa6,0x24,0x49,0x98,0xa2,0x63,0x64,0x0d,0x21,0x65,0xe4,0x2f,
++            0x0c,0x81,0xfe,0xbd,0x42,0x92,0x73,0x7f,0x66,0xa2,0x44,0x99,0xbc,0x66,0xe4,0xe7,
++            0xfb,0x34,0x9e,0x23,0xc7,0xf2,0x1e,0x07,0x27,0xdd,0xed,0xa5,0x13,0xf0,0x14,0xd0,
++            0x86,0x9d,0x17,0x70,0x25,0x4c,0x38,0x8d,0x0c,0x93,0xb9,0x66,0x4e,0xe5,0x34,0xb6,
++            0x80,0x9e,0xa2,0xc0,0x87,0xa2,0xba,0x50,0xf1,0xa9,0xec,0xad,0xb0,0xf1,0x89,0xd1,
++            0x21,0x9f,0x55,0xe4,0xd4,0x34,0xa4,0x47,0xd6,0xb3,0x03,0x5f,0x61,0x35,0xe9,0x32,
++            0x47,0x35,0xd8,0x19,0x30,0xb5,0x7c,0x27,0x8f,0xe5,0x62,0xa5,0x98,0xb5,0x79,0x56,
++            0x07,0xfe,0x36,0x52,0x17,0x25,0x02,0xda,0x54,0xd1,0xc2,0x87,0xa3,0xfa,0xf3,0x29,
++            0x03,0x39,0xf2,0xa5,0x55,0xbd,0x3f,0x01,0xc5,0x6e,0xac,0xe4,0x13,0x29,0x55,0x2c,
++            0x4e,0xa6,0xd5,0x10,0x84,0x9c,0xc5,0x0c,0x0e,0xc6,0x3d,0xaa,0x0e,0xff,0x4e,0x7b,
++            0xaf,0x9a,0xa2,0x9f,0x57,0x70,0x8e,0x55,0x5f,0x78,0xbe,0xf6,0x4f,0x19,0xaa,0xd9,
++            0x5b,0x82,0xb4,0xef,0x54,0xb2,0x84,0x55,0x5e,0x0b,0x3e,0x3a,0x00,0x22,0x37,0x83,
++            0xec,0xd4,0xa7,0x8d,0xe8,0x17,0x8f,0x50,0xdf,0xee,0xed,0xae,0x5b,0xb6,0xb9,0xfd,
++            0x8c,0xdb,0xa9,0x6e,0xf8,0xdb,0x87,0x48,0xf8,0x99,0x9f,0xff,0xfb,0x02,0x3e,0x46,
++            0x1d,0x18,0x04,0x8e,0x4f,0x31,0xda,0x75,0x6f,0x9c,0x72,0xd1,0x17,0xbd,0xd6,0xba,
++            0x23,0x60,0xe0,0xbc,0x1c,0xe7,0x70,0x98,0x4c,0x7e,0xfc,0x81,0xa9,0x02,0xdf,0x2b,
++            0xaa,0x8c,0x99,0xe7,0xb8,0xbf,0x4b,0x34,0xe8,0xdf,0x48,0xa8,0x28,0xf6,0x77,0xce,
++            0x9c,0xbb,0x2f,0xff,0xbf,0xfd,0x25,0x1d,0xd7,0x9d,0x6f,0x02,0xff,0xbe,0x37,0x28,
++            0xfc,0xe1,0xb0,0x66,0xeb,0x62,0x49,0x0d,0xab,0x04,0x64,0xd7,0xdc,0x21,0x19,0x94,
++            0x6c,0xdf,0xf0,0x26,0x35,0x8c,0xbc,0x14,0x22,0xa5,0xa2,0x84,0xff,0xce,0xc1,0xd8,
++            0x41,0xf7,0xdd,0x00,0x6d,0x8d,0x2b,0x91,0x6e,0xed,0x83,0xe9,0x3b,0x26,0x53,0x76,
++            0xe9,0xe2,0x1a,0x25,0x95,0xdc,0x8c,0xc2,0x45,0xce,0x3d,0x11,0xba,0x52,0x20,0x42,
++            0x79,0x09,0xc8,0x55,0xf3,0x6b,0xa8,0x1e,0x29,0x4b,0x5e,0xec,0xaa,0xb5,0xdc,0x58,
++            0x05,0x2e,0x17,0x50,0x15,0x0e,0xaa,0xfd,0xe2,0xb4,0xf8,0xe1,0xea,0xc4,0x51,0x32,
++            0x8e,0x44,0x01,0x34,0x71,0x67,0xd6,0x53,0x3d,0x40,0xe2,0x5c,0xa5,0x46,0xc6,0xd5,
++            0xea,0x88,0xa3,0xa8,0x97,0x65,0xa6,0xf5,0xf2,0x47,0xe1,0x9e,0x1b,0x16,0x7c,0x0e,
++            0xe9,0x8b,0x42,0x75,0xe7,0xd5,0x40,0x8f,0xa3,0x2c,0x6d,0xae,0xbe,0x5a,0x21,0x63,
++            0xd8,0x75,0xb0,0xac,0xb7,0x86,0x28,0x08,0x82,0xe6,0xc5,0xbd,0x5f,0x71,0xe4,0xfa,
++            0x04,0x4b,0x2f,0x29,0x73,0x6e,0x83,0xd8,0x6b,0x8a,0xab,0xd2,0xe7,0x5b,0xb4,0x56,
++            0x34,0xa0,0x2f,0x39,0x72,0x6f,0xbb,0x4b,0xab,0xcc,0x9b,0x22,0xe9,0x6d,0x78,0xa0,
++            0x10,0x43,0x9e,0xea,0x3e,0x37,0xe9,0x9b,0x26,0x57,0x44,0x7f,0x2a,0x7d,0x3c,0x12,
++            0xa8,0x16,0xaa,0xeb,0x22,0x20,0xa5,0x0b,0x27,0x23,0x1a,0x29,0x49,0xf8,0x63,0x58,
++            0x6b,0x08,0x1a,0x3b,0xbb,0x1e,0xc2,0x0f,0xa2,0x7f,0x6a,0xe9,0x9f,0x0a,0xde,0x3f,
++            0x74,0x14,0xd9,0x51,0x38,0x2b,0xbc,0x39,0xff,0x54,0x4c,0x46,0xf9,0xe2,0x84,0x00,
++            0x80,0x1d,0xfa,0x82,0xd1,0xb3,0x6a,0xa6,0x81,0xd3,0x73,0x64,0x74,0x84,0x1d,0x63,
++            0xa5,0x9c,0x1c,0x64,0xa5,0xc0,0x62,0xb7,0x0a,0x5e,0xe4,0xa4,0x91,0x8e,0xfa,0x71,
++            0x61,0xb3,0xf7,0x76,0x3c,0x3f,0xe3,0x52,0x6c,0x13,0x80,0xd6,0xc8,0xd9,0x5f,0x23,
++            0x4a,0x77,0xf3,0x93,0x50,0xb0,0x9d,0xc2,0xd9,0x11,0x71,0xc6,0xcd,0x85,0x45,0x42,
++            0xc4,0x46,0x86,0xa4,0x62,0xb5,0x44,0x93,0x6e,0x16,0xd4,0xe6,0x68,0x89,0xb3,0xaf,
++            0xac,0x93,0x17,0xd6,0x6b,0xce,0xd3,0x72,0x89,0x49,0xcf,0x07,0xf7,0xd8,0x7d,0x86,
++            0x68,0x07,0x45,0x25,0xe2,0xcd,0xc1,0xe9,0xe4,0x7d,0x8b,0xe2,0xf2,0xd7,0xcd,0x91,
++            0xbb,0xea,0x04,0xd7,0xab,0xcc,0x65,0x11,0xf9,0x4c,0x79,0x44,0xcf,0x35,0x96,0xe7,
++            0x43,0x17,0xf4,0x7f,0xb4,0x35,0x56,0x8a,0xc9,0xc7,0xa8,0x80,0xb2,0x77,0x9e,0x68,
++            0xb9,0xe8,0xf0,0x9a,0xd8,0xba,0x08,0xda,0x4d,0xa6,0x24,0x43,0x4a,0xbd,0x87,0x0b,
++            0x08,0x60,0x17,0x7d,0x24,0xcb,0xa3,0xcb,0x13,0xa7,0x9f,0xed,0xcb,0xfe,0x71,0x9f,
++            0x48,0x98,0xfd,0x6e,0x35,0x36,0x46,0xbe,0x4c,0x83,0x25,0x22,0x0e,0x60,0x24,0x36,
++            0x29,0x9c,0x14,0xce,0x72,0x91,0x16,0x8e,0x49,0xde,0x58,0xf0,0x79,0xac,0x2e,0x6e,
++            0x3d,0xb0,0xae,0x6b,0x02,0x30,0xc8,0x7a,0x8d,0x6f,0xcd,0x8e,0x11,0x0c,0x7d,0x21,
++            0xa8,0x51,0x8a,0x8a,0xb4,0xc1,0x97,0x80,0x57,0xaa,0x68,0xdc,0x8a,0xd1,0x5e,0x3b,
++            0xc0,0x10,0x63,0x4f,0x88,0x35,0x67,0x88,0x87,0x56,0xa1,0xd0,0x62,0xf7,0x58,0x06,
++            0x86,0x85,0x9a,0xb6,0xba,0x0f,0x4e,0x25,0xb1,0xcf,0x42,0xbe,0xf5,0x1f,0x10,0xec,
++            0xa9,0x8c,0xd6,0xf4,0xf5,0x10,0x40,0x49,0x2e,0xce,0xb8,0x29,0x65,0xe7,0x76,0x87,
++            0x86,0x87,0x05,0x23,0x64,0xad,0x85,0x5c,0x67,0x83,0x8b,0xdc,0xd2,0xfa,0xb9,0xe3,
++            0xdb,0x22,0x56,0x64,0x36,0x30,0xb9,0xb1,0x65,0xb9,0x4b,0xba,0x74,0xa1,0x25,0x24,
++            0x46,0xcb,0xe6,0x34,0x94,0x43,0x30,0x04,0x65,0xa4,0x0b,0x19,0x2e,0x4b,0x64,0x19,
++            0xe6,0xca,0x29,0xa6,0x5c,0xf4,0x38,0x14,0x07,0x8a,0x5c,0xb1,0xbe,0x74,0x8d,0xdc,
++            0x85,0xc6,0xfc,0xa5,0xa1,0x56,0xc9,0x73,0x61,0xdd,0x51,0x15,0xa4,0x49,0xa9,0x8b,
++            0x4f,0x53,0x90,0x31,0xb4,0xe7,0xd5,0xe1,0x87,0xcf,0x9f,0x71,0x3e,0x96,0xb4,0xf9,
++            0x88,0x05,0x59,0x2a,0x67,0x88,0xa2,0xdb,0xef,0x08,0xfe,0x27,0xfd,0x47,0xba,0x65,
++            0x66,0x86,0x75,0x03,0x19,0x19,0x9a,0x48,0x2f,0x6e,0x2f,0xd6,0x53,0xa4,0x71,0x29,
++            0x67,0xee,0x7e,0x0e,0xeb,0xaa,0x01,0x1b,0xb0,0x65,0x22,0x08,0x7d,0x45,0xab,0x99,
++            0x2d,0xab,0x89,0xef,0x05,0x5a,0xab,0xcb,0x42,0xfa,0x44,0x4c,0xe5,0x87,0xf3,0x55,
++            0x32,0x28,0xc6,0x51,0xe2,0x96,0x33,0x18,0xe9,0x61,0x94,0x69,0x5f,0x1c,0x14,0x72,
++            0xee,0x72,0xb2,0x73,0x2c,0xe9,0x85,0xfe,0x48,0x56,0xe9,0xed,0xdb,0x42,0xf6,0x62,
++            0x67,0xdf,0x23,0x1b,0x01,0xa3,0x62,0x83,0x0e,0x0f,0x4c,0x9c,0x5a,0x43,0x32,0xdb,
++            0x2a,0x86,0x53,0xcf,0xbe,0xdf,0x1b,0x79,0xb4,0xc2,0xe8,0x0c,0xe3,0x69,0x56,0x71,
++            0xa8,0xd1,0x34,0x02,0x23,0x5d,0xcc,0xaa,0xc1,0x28,0xa2,0xc0,0x8f,0x9c,0x71,0x74,
++            0x52,0x91,0x17,0x04,0x35,0xf0,0x04,0x48,0xc9,0xdc,0x82,0x9e,0xf8,0x57,0x7a,0x83,
++            0x93,0x64,0x09,0xf8,0x76,0xba,0xcd,0x87,0x0f,0xb6,0x0e,0x3c,0x1f,0x13,0xf2,0x8e,
++            0x9a,0xb3,0x82,0xe8,0x6c,0x2f,0x42,0x37,0x9c,0x6f,0x2b,0x77,0x85,0xf5,0xe3,0xd0,
++            0xcd,0x75,0xe6,0x36,0x47,0x45,0xf2,0x91,0x0a,0xdb,0xf0,0xad,0x83,0x7d,0x97,0xa3,
++            0x4b,0x9c,0xd4,0x25,0x4f,0xd0,0x25,0x1e,0x82,0xdc,0x76,0x39,0xd6,0xcd,0x05,0x75,
++            0xf4,0x9b,0x1a,0x43,0xf3,0xa3,0x4f,0x0b,0xe2,0x99,0xf1,0x87,0x5a,0xb4,0x2f,0x51,
++            0x41,0xa5,0xd5,0x24,0xc3,0xf5,0x78,0x1b,0x73,0x9a,0x85,0xe4,0xcb,0xc6,0xa6,0x0a,
++            0xdc,0x13,0x1d,0xd4,0x18,0x13,0xda,0xd5,0xae,0xd8,0xc0,0xe4,0xdd,0x78,0x8e,0xe8,
++            0x4f,0xfe,0x63,0xba,0x5d,0x2a,0x60,0x58,0x69,0xdf,0x2e,0xcd,0x4d,0x08,0x8b,0xba,
++            0xc0,0x35,0xdf,0x8b,0x3e,0xbf,0x8c,0x39,0xe8,0x9b,0xcf,0x3d,0xf4,0xf2,0x51,0x9c,
++            0x89,0x10,0xd1,0x99,0x5c,0x38,0x0f,0x02,0xe9,0xd9,0x40,0x3b,0xfa,0x60,0x5e,0xbb,
++            0x42,0x95,0x6c,0x7d,0x9f,0x13,0x89,0x02,0x6a,0x91,0xd0,0xd6,0x4a,0xc1,0x6a,0x3c,
++            0xc6,0x7c,0xbe,0xac,0x84,0xe0,0x36,0x98,0x90,0xc6,0x68,0xed,0x0b,0xec,0x64,0x23,
++            0xac,0x15,0x70,0xe8,0x1f,0x11,0xe0,0x0d,0x6c,0x19,0xaf,0xf3,0x36,0x4f,0x17,0xa9,
++            0x9c,0xdf,0x2f,0x8b,0xd8,0xfd,0xff,0x9d,0x62,0x29,0xd9,0xc2,0xc7,0x5b,0x50,0x2c,
++            0x80,0xd1,0xd6,0x28,0x16,0xaa,0xbc,0xa5,0xff,0x02,0xae,0xf4,0x9a,0x0a,0x51,0x1a,
++            0xa4,0x7e,0x75,0x67,0x5a,0xa3,0x64,0xc0,0xdd,0x10,0x40,0x73,0xb8,0x2b,0x3c,0x21,
++            0x21,0x60,0x60,0xc5,0x94,0x07,0x8b,0xf3,0xc6,0x8a,0x7d,0xb7,0x90,0x68,0x3e,0xb1,
++            0x71,0xf2,0x97,0x20,0xb0,0x01,0x60,0x4e,0x66,0x1e,0xff,0xf4,0x2e,0x0d,0xd5,0x20,
++            0x06,0x20,0x99,0x4f,0xb7,0xdb,0x6e,0x4d,0x2a,0x49,0x40,0x16,0xb9,0x85,0xe6,0x41,
++            0x6f,0x21,0x80,0xa0,0x5b,0x94,0x98,0x51,0x1f,0xc3,0xd7,0xb4,0x30,0xee,0xef,0x50,
++            0xb6,0x22,0xff,0x1c,0x1d,0xd0,0x47,0x03,0x29,0x97,0xef,0x50,0x5f,0xc0,0x79,0x75,
++            0x5f,0x76,0xe5,0x88,0xdb,0xb6,0x5f,0xb1,0x8f,0x05,0x65,0x44,0xbf,0x25,0xb5,0x24,
++            0xfc,0x39,0xbc,0xd8,0x6b,0x28,0x0a,0x2c,0x61,0x59,0xf0,0x3c,0x59,0xa8,0x1f,0x07,
++            0x3d,0x34,0xdc,0x30,0x1f,0xa3,0x43,0xd5,0xae,0x52,0x82,0x5d,0xd4,0xc4,0xc3,0x7d,
++            0x4b,0xde,0x95,0x20,0x63,0xb7,0x83,0x5b,0x23,0x7b,0xad,0xfd,0xb1,0x00,0x1b,0x7a,
++            0x87,0x10,0xef,0xdd,0x9d,0x0e,0xd7,0xdf,0x22,0xaa,0xd1,0xae,0xd6,0xeb,0xaa,0x70,
++            0x69,0x85,0xee,0x10,0x38,0xbd,0x46,0x65,0x88,0xec,0xc2,0xec,0xfb,0x65,0x32,0x9f,
++            0xc9,0x0f,0x35,0x2f,0x67,0xa2,0x38,0x3a,0xba,0xcb,0x4c,0xf8,0x7b,0x4e,0xd4,0xa3,
++            0x2f,0x84,0x03,0x3e,0xb8,0xa1,0x5b,0x70,0x47,0xf3,0x49,0x9d,0x84,0xcf,0x43,0x5d,
++            0x22,0x0b,0x30,0xb5,0x17,0x62,0x5b,0xb9,0x97,0x03,0xe3,0x8f,0xf8,0x15,0xc4,0xd4,
++            0xac,0xbf,0xe3,0x7f,0xd9,0x61,0x6c,0x8c,0x8b,0x21,0xcd,0x5c,0xb6,0x78,0xb8,0xe3,
++            0x15,0x1e,0xe8,0x54,0x35,0x14,0x0d,0xf7,0xab,0x9b,0xc5,0xd2,0x8e,0x6a,0xa1,0xf2,
++            0x98,0x1d,0xe7,0x85,0xb6,0xb8,0x2f,0x52,0xd0,0xff,0x15,0x93,0xf3,0x69,0xcd,0xc5,
++            0x11,0xbe,0x70,0x11,0xf2,0xa4,0x15,0xb5,0x68,0x63,0x40,0xc3,0x91,0xa3,0x14,0x30,
++            0x85,0xb5,0xd3,0x3f,0xce,0xe5,0x40,0xed,0xa0,0xd4,0x9c,0x55,0x8a,0x95,0x74,0x23,
++            0x09,0x98,0x70,0xe5,0x4b,0x77,0x3e,0x21,0x92,0xd3,0x69,0x04,0xde,0xd4,0xd0,0x45,
++            0x82,0x14,0x05,0x78,0x0e,0xbd,0x5d,0x61,0x6d,0xeb,0x62,0xcd,0xf4,0x85,0x33,0xe9,
++            0x4a,0x34,0xdd,0x55,0x52,0x38,0x5d,0xb1,0xdd,0xfa,0x4b,0x71,0xd3,0x75,0x90,0x6a,
++            0x84,0xb5,0xdc,0x8d,0x9b,0x9c,0xd6,0x78,0x9a,0x55,0xe8,0xaa,0x99,0xfb,0x78,0xeb,
++            0x11,0x16,0x46,0x8f,0x55,0x53,0x44,0x90,0x01,0x28,0xe6,0x54,0x72,0x3b,0x16,0x6b,
++            0xae,0xd2,0x96,0x4c,0x70,0x2b,0x0f,0xad,0x40,0x25,0xe5,0x5e,0x74,0x87,0xbb,0xea,
++            0x9d,0x14,0xa9,0xa8,0xfa,0x94,0x61,0xbf,0x8a,0x9e,0xdf,0x80,0x9a,0x6f,0x04,0x37,
++            0xc3,0x8d,0x9c,0x51,0x52,0x8d,0x06,0xb9,0x16,0x57,0xec,0x0e,0x86,0x6d,0x72,0x5c,
++            0xc2,0x8c,0x31,0x3e,0x58,0x72,0x3c,0xb8,0x9a,0xdb,0x19,0xcd,0x4b,0x3f,0xeb,0x56,
++            0xab,0x5e,0x07,0xed,0x90,0xb5,0x01,0xcd,0x65,0xe3,0x17,0x81,0x45,0xf5,0x4d,0x2a,
++            0xd3,0xb2,0xd9,0xf0,0xbd,0x3e,0x5f,0xb9,0xd7,0xf2,0xcf,0x5c,0x5a,0x80,0x01,0x64,
++            0xbb,0x35,0x5d,0x75,0x24,0xa9,0x0e,0x17,0xc9,0x66,0x4b,0x59,0x14,0x34,0x39,0x2c,
++            0x69,0xc3,0x3d,0xe5,0x91,0x2a,0x3f,0xc2,0x66,0x60,0x62,0x50,0xae,0x8d,0xb2,0x39,
++            0xfc,0x77,0xe5,0xf7,0xf8,0x03,0x7f,0x63,0xc0,0xee,0xc9,0x15,0x2b,0xf9,0xb3,0xc1,
++            0x51,0x62,0x1b,0xa6,0xa1,0xe1,0xaf,0xc0,0x41,0x4e,0x06,0xac,0x34,0x65,0xd7,0x6f,
++            0x00,0x5e,0x2b,0xa0,0x06,0xe9,0x63,0x60,0x5a,0xa8,0x8e,0x4e,0xbf,0xf5,0x68,0x78,
++            0x3b,0x95,0x0f,0x84,0xb6,0x0a,0x1a,0x72,0x44,0x85,0x30,0x05,0x3b,0x4c,0x54,0xb3,
++            0x8e,0x5d,0x2e,0xa1,0xb2,0xa0,0x4e,0xf1,0xe5,0x5b,0x5d,0xf4,0x8f,0xec,0x49,0x42,
++            0x0a,0xe4,0x7a,0xa6,0xe7,0x87,0xd1,0x4b,0x2e,0xe4,0xe8,0x17,0xc6,0x6c,0x85,0x22,
++            0xb9,0xca,0xe8,0x80,0x1f,0xe8,0x60,0xa1,0xa7,0xac,0xb2,0x6e,0x48,0xf3,0x14,0x2f,
++            0xae,0xec,0xb2,0x9b,0xf4,0x63,0x3f,0x49,0x21,0x6d,0xe3,0x29,0x3e,0x6b,0xa9,0xff,
++            0x67,0xee,0x97,0xe0,0x75,0x4b,0x0b,0xcb,0xc8,0xe6,0x7f,0xdf,0xd4,0xa5,0x15,0x33,
++            0x2e,0xd6,0xd4,0x58,0x74,0xda,0xf1,0xd9,0x2d,0x6f,0x43,0x4c,0xde,0x85,0xc9,0xef,
++            0xdb,0x92,0xdc,0x76,0x93,0x0a,0x68,0x6e,0x6d,0x8f,0x4e,0x5f,0x6e,0xae,0xd2,0x86,
++            0xe4,0x7c,0x80,0x6f,0x6f,0xef,0x85,0x05,0xc2,0x4b,0x29,0x45,0x6f,0x18,0x1e,0xb4,
++            0xbd,0xea,0xb7,0x8f,0xb4,0x25,0xc4,0x57,0xc8,0x77,0xe3,0xef,0x7f,0xe7,0x6a,0x3d,
++            0xd0,0x20,0xfb,0xdf,0x3e,0x00,0x79,0x3b,0x81,0x8d,0x6d,0xfb,0xf7,0xc6,0x7e,0x8d,
++            0x10,0x8f,0xec,0x6e,0x07,0x4d,0x62,0x8e,0x8f,0xb4,0xa2,0x8f,0x9f,0xb4,0x76,0x43,
++            0x11,0x8e,0x1b,0xbb,0xc1,0xe0,0x86,0x4c,0x98,0xbd,0x18,0x32,0x77,0x98,0x9d,0xc4,
++            0xaa,0x6d,0x5d,0xf5,0x5f,0xe8,0x0d,0x5c,0xd7,0x09,0x8f,0x17,0x16,0x5d,0x95,0xd4,
++            0xab,0x62,0x6d,0xef,0x4c,0xf1,0xde,0x73,0xe1,0xf6,0xe7,0xa7,0x9d,0xc2,0x73,0x85,
++            0xec,0xb7,0xa4,0xa4,0x74,0xbb,0x24,0xb3,0x1a,0xdf,0x8e,0x86,0x34,0x7f,0x36,0x00,
++            0x4f,0x04,0x5b,0xea,0x31,0xec,0x1e,0xf0,0x96,0x53,0x43,0xbc,0x67,0xf1,0x6d,0xc7,
++            0x0f,0x46,0xe3,0xff,0x36,0xaa,0x63,0xc7,0x69,0x6b,0xf1,0x1b,0xf6,0xea,0xad,0xf3,
++            0xa5,0x9a,0x10,0x27,0xbf,0x6c,0x7d,0xb3,0xf7,0x7a,0xfb,0xb0,0xd9,0x2b,0xd9,0x0e,
++            0x69,0xb7,0xe6,0x44,0x0f,0xa3,0xcb,0xd9,0x2b,0x5a,0xc8,0x87,0x4f,0x83,0xbf,0x70,
++            0x88,0x26,0x53,0xed,0x3a,0x10,0x64,0x93,0x05,0xa8,0x39,0x7e,0x7b,0x59,0xfc,0x8b,
++            0xcf,0xee,0x1f,0x6f,0xb8,0x9f,0x29,0x83,0xcd,0xf8,0x35,0xd9,0x71,0x7c,0x74,0x9b,
++            0x44,0xa1,0xe3,0x7f,0xa9,0xd7,0x41,0xbd,0x8e,0x1e,0xae,0xae,0xc1,0x56,0x99,0x3a,
++            0xed,0x3d,0xe6,0xe4,0x02,0xac,0x26,0xbb,0x12,0xd7,0x22,0xb0,0xed,0xc3,0x56,0x21,
++            0x29,0xc7,0x45,0x7b,0xea,0xa3,0x41,0x68,0x6f,0x40,0xef,0xfc,0x93,0x5d,0x70,0x4f,
++            0x8e,0x9c,0xc7,0xde,0x33,0xdd,0xf7,0x88,0x6e,0xb0,0x37,0xcf,0x61,0x5e,0xd1,0x5f,
++            0x87,0x06,0x92,0x5b,0x9f,0xc1,0x1d,0xfa,0xee,0x8f,0x69,0x9c,0x3f,0xbe,0x60,0x44,
++            0x71,0x8d,0x8a,0x00,0xb3,0x26,0x4a,0x21,0xe3,0x46,0x6f,0x24,0xaf,0x9f,0x70,0x92,
++            0x04,0x6b,0x73,0xf6,0xb0,0xa9,0x67,0xd2,0xc3,0x42,0x67,0xcb,0x51,0x41,0x79,0x83,
++            0x85,0x3b,0x09,0x1c,0x31,0xa8,0x1d,0x27,0x61,0xc8,0x6a,0xda,0xd8,0x62,0x31,0xc1,
++            0x76,0x0c,0x09,0xf7,0xee,0xaa,0xac,0x53,0x80,0xc3,0x66,0xcb,0x2e,0x43,0x40,0xbf,
++            0x02,0xfb,0x62,0x22,0x31,0x06,0x50,0x60,0x42,0x75,0xa8,0x94,0x19,0xc5,0x4c,0xaf,
++            0xfc,0xfa,0x4c,0x50,0x30,0x70,0x06,0x59,0xcf,0x74,0xd8,0x0b,0xf0,0xc5,0xbe,0xbe,
++            0x7d,0x26,0x98,0x6c,0x37,0x2d,0x4f,0x48,0xff,0x77,0x47,0x8f,0xd4,0x65,0xb6,0x50,
++            0x7c,0x27,0x21,0xdd,0xa0,0x16,0x3f,0x58,0x7f,0x76,0xc8,0x64,0xe3,0x25,0x3a,0xd8,
++            0xf3,0x07,0x42,0x71,0xda,0x2e,0x6a,0x4a,0x09,0x40,0x92,0xd3,0xa7,0x68,0x40,0xe3,
++            0xaa,0x0f,0xa0,0x99,0x17,0xa3,0x62,0xba,0x4c,0xad,0x65,0x3c,0xa6,0x96,0x63,0x4d,
++            0x00,0x07,0x0b,0x98,0x39,0xd5,0x6b,0x4b,0x8b,0x35,0x97,0x2d,0x27,0x95,0x5b,0x36,
++            0x28,0x81,0x0f,0xbd,0x38,0x5b,0x41,0x38,0x6a,0x4d,0x9b,0xc2,0xd9,0x6b,0xbd,0x49,
++            0x02,0x2c,0x7a,0xdc,0xbd,0x28,0x7c,0x41,0xe7,0x1d,0x82,0x2b,0xfb,0xf3,0xb5,0xa7,
++            0x03,0x2d,0x4e,0xba,0x70,0x3c,0x14,0x78,0x4b,0x4d,0x4f,0x42,0x6f,0x2f,0x47,0xb6,
++            0x75,0x2e,0xc5,0xa5,0xa2,0xa5,0x55,0x45,0xf6,0x1f,0x67,0x0f,0x21,0x9b,0xb4,0xa6,
++            0x74,0xf0,0x4c,0x2f,0x70,0x1e,0x5d,0x79,0xcb,0x4f,0xc4,0x26,0x59,0x6b,0x7c,0x02,
++            0x21,0x52,0xe4,0xc0,0x76,0x3d,0xef,0x42,0xc1,0xda,0x94,0xa4,0x8f,0x70,0x34,0x40,
++            0xda,0x1e,0xec,0xd0,0x29,0x3c,0x9c,0xd2,0x22,0xee,0x9c,0xb4,0x8e,0x71,0x3d,0x51,
++            0x1f,0x1d,0x7a,0x25,0x11,0x42,0x6a,0x43,0x62,0x1a,0x95,0x5a,0x0f,0x72,0xb9,0xf3,
++            0xe2,0xe4,0xc7,0x6e,0x12,0x3e,0x65,0x33,0xe4,0x93,0x9d,0x4a,0x0e,0x73,0x44,0xc0,
++            0x22,0x14,0x55,0xdb,0x0e,0x8f,0x1c,0xe0,0x55,0xc8,0x6b,0x7f,0x87,0xf2,0x4c,0xd1,
++            0x23,0x15,0x9e,0x52,0xe7,0xa4,0x64,0x90,0x67,0x71,0x9d,0x70,0x51,0x19,0x41,0xc1,
++            0xaa,0x16,0xc1,0xfa,0xde,0x74,0x65,0x63,0x6a,0x8e,0xd5,0xa5,0xb4,0x38,0x49,0xd0,
++            0xa3,0x17,0x6a,0xec,0xd0,0x9d,0x5f,0x51,0xed,0xc7,0xe3,0xd9,0x50,0x12,0x7e,0xea,
++            0x6b,0xe6,0x8c,0x8d,0x9b,0xc5,0x2e,0x78,0x93,0x57,0x69,0xac,0x87,0x87,0x36,0x48,
++            0xde,0x16,0x0b,0x1e,0x3c,0x89,0x54,0x43,0xca,0x5f,0x9e,0x43,0x79,0x79,0x7f,0x0b,
++            0xa9,0x58,0x2b,0x08,0x9a,0x37,0x77,0xed,0xfc,0x57,0x68,0x52,0xf8,0x7a,0xbb,0xfb,
++            0xea,0x64,0xb7,0x4d,0x42,0x34,0x97,0xa5,0x48,0xd1,0x60,0x42,0xf9,0x84,0x42,0xc8,
++            0x22,0x3c,0xd0,0xf9,0x89,0x71,0x36,0xea,0x67,0xd7,0xe8,0xc1,0xd9,0x3e,0xb1,0x27,
++            0x2b,0xe2,0xc8,0xf5,0xc7,0x2c,0xb6,0x70,0xe3,0xdd,0xa6,0xdb,0x92,0xcc,0x47,0x36,
++            0x55,0xe1,0x9f,0xc9,0x93,0x80,0xd7,0x0b,0x6f,0x3c,0x87,0x2e,0x13,0xef,0x4f,0x26,
++            0x54,0x1f,0xc9,0xf5,0xd8,0x37,0xf7,0x71,0xd8,0x04,0xa7,0xec,0x97,0x56,0xd7,0xe0,
++            0x86,0xc8,0xc0,0x42,0x1c,0xad,0x60,0x33,0xa5,0xcf,0xb0,0xd9,0xab,0x1f,0x9c,0xe2,
++            0x09,0x8e,0xa2,0x17,0xb6,0x5c,0x58,0x92,0x1f,0xce,0x47,0x36,0x55,0x1e,0x39,0xf3,
++            0x85,0x8d,0xeb,0xfc,0x37,0xaf,0x51,0x83,0xfe,0xcd,0xb1,0xd8,0x2b,0xe2,0x49,0x57,
++            0x92,0x0e,0x83,0x92,0x9b,0xc1,0x59,0x93,0xd9,0xcc,0x46,0xc8,0x2a,0xe3,0x64,0xbd,
++            0x0e,0x7b,0x9e,0x73,0x25,0xa0,0x36,0x62,0x46,0xc4,0x3e,0x04,0xad,0x88,0x97,0xad,
++            0x0f,0x85,0x44,0xc9,0x16,0xe5,0x61,0x72,0x47,0x05,0xf8,0xb6,0x05,0xa7,0x65,0x42,
++            0x8e,0xa6,0x59,0xb8,0x7f,0x47,0x62,0x63,0xc6,0xe6,0x4e,0xfc,0x23,0x60,0x69,0x53,
++            0x87,0xa7,0xf5,0x34,0xf4,0x0d,0x1d,0x73,0xc7,0x95,0xa9,0xb4,0x76,0x78,0x5a,0x88,
++            0x09,0x42,0xe8,0x0f,0x3e,0xa5,0x52,0x8a,0x20,0xc7,0xb2,0xd1,0x5c,0xe8,0x12,0xca,
++            0x72,0x86,0x92,0xce,0xe6,0xa6,0x70,0xc1,0xee,0xcf,0x45,0xc1,0xa2,0x16,0x5b,0x89,
++            0x89,0x8e,0x26,0x8d,0x99,0x0a,0x53,0x6a,0x79,0xc7,0xb3,0xd0,0xdc,0xea,0x9f,0x79,
++            0xce,0x54,0x93,0x4f,0x95,0xa4,0x37,0x50,0x6c,0x41,0xbb,0x3f,0x22,0xeb,0x62,0x4b,
++            0x0e,0x8c,0xf4,0x7b,0xad,0xe1,0x02,0x6a,0x4e,0x4e,0x46,0x0c,0xa5,0x19,0x6e,0x5a,
++            0x0f,0xad,0xd0,0xa5,0xe3,0x4c,0x43,0x7a,0x0f,0x62,0xe5,0x25,0xdd,0xe9,0x67,0x4b,
++            0x8e,0xae,0xbb,0x4b,0xb7,0x10,0x18,0x6b,0xce,0x54,0xe4,0x51,0xae,0xac,0x6b,0x5a,
++            0x87,0x8f,0x2b,0xef,0x19,0x7b,0x78,0x7b,0x93,0xa4,0xb2,0x1d,0x24,0x83,0x5c,0xe0,
++            0x67,0x2f,0x9c,0xd6,0x3c,0xbf,0x4b,0x40,0xe6,0x98,0xb4,0x59,0x8b,0xf0,0x16,0x70,
++            0x89,0x9e,0xa8,0x96,0x3d,0x91,0x44,0xd0,0x24,0x91,0xbc,0xb6,0x75,0x0e,0x5d,0x01,
++            0xa1,0x13,0x35,0x86,0xb4,0x92,0x31,0xc1,0xa7,0x0d,0x4a,0x58,0xf4,0x0d,0x4d,0xd3,
++            0x09,0x13,0xad,0x97,0xb5,0x93,0x45,0x31,0xe0,0x73,0x42,0xb7,0xf5,0xf3,0x64,0x3d,
++            0xd9,0x94,0x73,0x42,0x14,0x84,0xce,0x1d,0xe4,0x93,0x64,0x0e,0xb2,0xb6,0x6c,0xd2,
++            0x27,0x6a,0xbc,0xd2,0xde,0xc4,0xfc,0xf0,0x7b,0xce,0xc2,0xdf,0x36,0xf1,0x65,0x3c,
++            0xa6,0x69,0xdb,0xf2,0x15,0xf4,0x8e,0x81,0x9b,0xdf,0xa5,0xe7,0x0b,0xf9,0x92,0x2c,
++            0x58,0x68,0x95,0xa4,0x83,0xf5,0xdf,0x95,0x18,0xd1,0x83,0xc2,0x0a,0xfe,0x5e,0x08,
++            0x29,0xc1,0xa2,0x8e,0x3c,0xb8,0x0e,0x7a,0x9b,0xd7,0x49,0xae,0x83,0x07,0x8e,0xf8,
++            0x6c,0xd9,0xae,0x61,0x3d,0x46,0x5e,0xfe,0x75,0xd4,0x41,0xbe,0x7d,0xf9,0x1d,0x69,
++            0x2e,0xb2,0xa3,0x70,0x43,0xba,0x0f,0xfb,0xe8,0xd5,0xb7,0x50,0x03,0xfa,0x57,0x19,
++            0xac,0xf8,0x50,0x60,0xbd,0xbb,0x75,0x45,0x4e,0xd6,0x40,0x40,0xfd,0xfb,0x66,0x35,
++            0x2e,0x63,0xb6,0xcf,0xc3,0xb3,0x82,0x47,0xcf,0x25,0x72,0xab,0x12,0xfe,0x91,0xda,
++            0x2f,0x62,0xf9,0x3c,0xd6,0x2c,0x96,0x72,0x5c,0x86,0xda,0xa2,0x96,0x1c,0x98,0xcb,
++            0xae,0x61,0x27,0x6f,0xba,0x13,0x6f,0xfb,0x13,0xd1,0xa7,0x67,0xee,0xf8,0x6f,0x24,
++            0xaf,0x9f,0x2f,0x7f,0xb7,0x42,0xc5,0x1b,0xa9,0xc4,0x87,0xfd,0xb7,0x72,0x60,0x03,
++            0x55,0x0f,0x15,0x35,0x64,0x8f,0xcf,0xde,0x64,0x5b,0x0f,0x24,0x50,0x60,0x49,0x0d,
++            0x32,0x5a,0xf6,0x2d,0xe0,0xa1,0xe0,0xb4,0x18,0x29,0x58,0xb4,0x2c,0x61,0x51,0x1c,
++            0x8c,0x03,0x12,0x77,0xfa,0x93,0xf2,0x47,0xf3,0x27,0x91,0xa7,0x3e,0xdf,0xb3,0xf1,
++            0xd9,0x18,0xf4,0x66,0xad,0x17,0xa0,0xd3,0x6d,0x3e,0x99,0x35,0xd1,0x65,0x0a,0x80,
++            0x3a,0xa9,0xc0,0x84,0x16,0x09,0x1a,0x19,0xc0,0xe3,0xc3,0xa3,0x90,0xe5,0x03,0xbd,
++            0xfc,0x88,0x52,0x6c,0x9c,0x88,0x62,0x8d,0xe2,0x9e,0xe6,0x4c,0xdc,0xe3,0x0d,0x21,
++            0x9e,0xa9,0xf7,0x7a,0xaa,0x64,0xf7,0xe5,0xc0,0x2f,0xd9,0xf8,0x52,0x86,0x36,0xac,
++            0x7c,0x45,0x5c,0xc7,0x30,0x8a,0xde,0x8a,0x30,0x05,0xb9,0x35,0x95,0xec,0xa0,0x6e,
++            0x2b,0x18,0xfa,0x3e,0xec,0x27,0x6a,0xc0,0xac,0x05,0x64,0x5f,0x5e,0x6a,0x8e,0x9c,
++            0x2a,0x15,0x31,0xad,0x65,0x86,0x28,0xc7,0x6d,0x52,0x9a,0x2f,0x56,0x13,0x5a,0x20,
++            0x2d,0x03,0x95,0xad,0x73,0x29,0x11,0xd8,0x6b,0x5a,0x0c,0x2d,0xd8,0x6a,0x9b,0xf1,
++            0x1f,0x46,0x1c,0x05,0x19,0xe5,0xa9,0x5f,0x36,0x30,0xa5,0xf0,0x56,0xcd,0x5e,0x3a,
++            0xe3,0xc6,0x53,0xde,0x1a,0x26,0x18,0xb4,0xc7,0x0e,0x2a,0x5d,0x62,0x2e,0xe6,0xc7,
++            0x08,0x9d,0x71,0xce,0x1b,0x25,0x04,0xa1,0xb4,0x0c,0xa2,0x8c,0x05,0xcc,0x01,0xb6,
++            0x63,0x44,0xc2,0x32,0x58,0x21,0xd4,0x83,0xcb,0xce,0xc3,0xed,0x7b,0xec,0x6d,0x9d,
++            0xd8,0x74,0x4b,0x9b,0x8d,0x82,0x9b,0xa9,0xb2,0x54,0x4d,0xf9,0xfb,0x4c,0x1f,0x0a,
++            0x23,0x00,0xbc,0x7b,0xb3,0x3d,0x2e,0x5a,0x91,0x3c,0x59,0xa6,0xeb,0xd4,0x88,0x6d,
++            0xde,0x50,0x2f,0xa9,0xed,0x32,0xdc,0xe9,0x5d,0x13,0x70,0x27,0x76,0x7b,0x5c,0xba,
++            0x05,0x19,0x7e,0x01,0xec,0xfb,0x73,0x99,0xe3,0x82,0xd9,0x7d,0x19,0xe8,0x1d,0x34,
++            0xf0,0x08,0xd4,0x0b,0x14,0xcc,0x12,0xec,0xe0,0x33,0x8e,0xc6,0xfe,0x7a,0x1c,0x44,
++            0x7e,0xdd,0xa6,0xa4,0xdb,0x65,0x84,0x92,0x89,0xb5,0xee,0x17,0x1e,0xff,0xf7,0x60,
++            0x2b,0xba,0xec,0x85,0xbe,0xc8,0x53,0xb0,0x67,0x78,0xcc,0x55,0xd2,0x7c,0x7f,0xfc,
++            0x49,0xec,0xa7,0xcc,0xb3,0x76,0x6b,0xd4,0x6f,0xf0,0xf4,0xd4,0x9e,0x34,0x86,0x53,
++            0x4d,0xaa,0xaf,0xf7,0x46,0xb1,0x75,0x01,0xbd,0xf6,0x9f,0x05,0x54,0xd6,0x32,0xee,
++            0x6b,0xe8,0xdf,0xab,0x9f,0x28,0xc9,0x56,0x4c,0xc8,0x15,0x5f,0x67,0xd5,0x3c,0xfe,
++            0x9e,0x09,0xf1,0xe3,0x3f,0x81,0x25,0x7f,0xb3,0x51,0xa4,0x53,0x02,0x86,0xf8,0x75,
++            0xa8,0x01,0x3f,0x77,0xa8,0x77,0x37,0xd3,0x9b,0xea,0x5d,0x5f,0xb8,0x85,0xb7,0x76,
++            0x52,0x87,0x03,0xe7,0x1a,0x5e,0x9c,0x3d,0xb0,0x2a,0x5f,0xdc,0x18,0xd6,0x86,0x18,
++            0x09,0x07,0xc6,0x0c,0x6a,0x91,0xc0,0x6c,0x4a,0x7f,0x40,0x68,0x5a,0x7e,0x8e,0x08,
++            0x38,0x1b,0x5f,0x4e,0x37,0x35,0x06,0xfc,0xc2,0xca,0x32,0xcd,0x17,0x3f,0x42,0x4d,
++            0xa8,0x8c,0x52,0x5f,0x3b,0x93,0x6f,0x1a,0xd2,0xd1,0xef,0x0d,0xee,0xf5,0xb9,0xa2,
++            0xad,0x95,0x4f,0xdf,0x99,0x51,0x05,0x89,0x83,0x6e,0xcf,0xbf,0x98,0x5f,0xdf,0xea,
++            0xe4,0xcd,0x13,0x3b,0xe8,0xa3,0xcf,0x50,0xbf,0x82,0xfa,0xe6,0x74,0x44,0x84,0x8d,
++            0x66,0x85,0x2c,0x92,0x17,0x33,0x80,0xcd,0x7a,0xe1,0x54,0xa5,0x52,0xeb,0x5a,0x0b,
++            0x21,0x3d,0x9b,0xfd,0x6f,0xb9,0xf9,0xd0,0x18,0x53,0xfd,0xff,0x3d,0x78,0x50,0x69,
++            0xe4,0x87,0x12,0x55,0x34,0x5e,0x66,0x2a,0xc3,0x89,0x79,0x0c,0x86,0x16,0x64,0x30,
++            0xfd,0x7f,0xf1,0x96,0xb5,0x1b,0x72,0xe6,0x44,0xf4,0xaa,0x99,0xf5,0xe0,0x6e,0x9f,
++            0x87,0x8b,0x50,0x66,0xb6,0x3a,0xe8,0xd2,0x59,0x95,0xa0,0xf2,0xe8,0x50,0x65,0xc7,
++            0xaf,0x0b,0xf9,0xd2,0xa5,0xec,0xd6,0xba,0x8e,0x7c,0x37,0x0c,0x95,0x76,0x09,0xe4,
++            0x3e,0xc5,0xd6,0x10,0x45,0xaf,0x20,0x8b,0x22,0xa9,0xec,0x48,0xbb,0xa5,0x43,0xca,
++            0x00,0x73,0x8a,0x6c,0xe8,0x19,0x4c,0x71,0xb1,0x74,0x7f,0xaa,0x77,0x92,0x92,0xe5,
++            0x80,0x34,0x07,0x50,0xe8,0xf5,0xd6,0xa8,0x41,0xc1,0x7a,0xf3,0x89,0x49,0xdc,0x2f,
++            0xbf,0x3c,0x14,0x33,0x01,0x57,0x9f,0x50,0x06,0x5b,0x73,0xff,0x78,0x15,0xcc,0xeb,
++            0x0d,0x94,0x91,0xf4,0x2e,0xa5,0xbf,0xc6,0x3a,0x8a,0xf0,0x3d,0x30,0x4b,0x28,0xaa,
++            0x3d,0xbc,0xe1,0x31,0xdc,0x3e,0x10,0x63,0x4f,0x8c,0xfc,0xd0,0x5f,0xfc,0x9c,0x31,
++            0x09,0x07,0xe8,0xa2,0x1f,0x56,0x21,0x58,0x78,0x3b,0x6c,0xfa,0x16,0x3a,0xa3,0xcb,
++            0xdc,0x88,0x58,0xdd,0x9e,0xa4,0x4f,0x01,0xfd,0xda,0x76,0x54,0xe6,0x1b,0xa6,0x7c,
++            0x89,0x05,0xa8,0x98,0x76,0xde,0x26,0x9d,0xc9,0xee,0xfd,0x4a,0x56,0x63,0x9d,0xd8,
++            0x22,0x20,0x9b,0x64,0xc8,0xb3,0xf4,0xfb,0x39,0xd8,0xfa,0x36,0x8b,0x5d,0x66,0x70,
++            0xb4,0x6c,0xba,0xf4,0x55,0xa5,0x7f,0xb0,0x9c,0x5c,0xbf,0xa5,0x36,0x8b,0x89,0xfd,
++            0x65,0x8d,0x35,0xf8,0xdc,0xbf,0xb1,0x5e,0x13,0x93,0xff,0xe0,0x2a,0xf8,0x07,0x43,
++            0xf9,0x8b,0xd3,0x91,0x54,0x30,0x43,0x8a,0x0e,0x02,0x87,0x58,0x8e,0xd3,0x3c,0x46,
++            0x7a,0x5d,0xda,0xeb,0xe8,0x19,0x0d,0x84,0x8d,0xc5,0x8c,0xf7,0x1a,0x59,0xd7,0x62,
++            0x2f,0x3a,0x2c,0xf7,0x46,0x40,0xbc,0xd2,0x08,0xd8,0x6c,0x07,0x22,0xf1,0x5f,0xfe,
++            0x4d,0xbf,0x74,0x59,0xb7,0x86,0x2f,0xa4,0x8e,0xe7,0x63,0x55,0xaa,0x88,0x75,0x57,
++            0x86,0x2f,0x78,0xe9,0x83,0xb3,0x00,0xc8,0xdf,0x22,0xa3,0xaa,0xf7,0xec,0x58,0xa7,
++            0x1f,0x7d,0xd4,0x7d,0xb0,0xfa,0x48,0x97,0x87,0xdb,0x01,0x7a,0x7a,0xd1,0xbb,0x5a,
++            0x65,0xdb,0x6e,0x1e,0x72,0xbf,0x59,0x7a,0x05,0x9b,0x91,0xad,0x72,0x83,0x9f,0x74,
++            0x23,0x3c,0xed,0x6f,0x8f,0x90,0x04,0x93,0x1d,0xb4,0x8d,0xbe,0xaf,0xfe,0x20,0x5a,
++            0xac,0xfb,0x59,0xf4,0xbb,0xb9,0x30,0x96,0x4c,0x74,0x81,0x72,0x72,0x5d,0xa6,0x1a,
++            0x57,0x9a,0xe4,0xf5,0x02,0x29,0xe0,0x6e,0x07,0xc4,0x2a,0x1e,0x01,0xb3,0x72,0x9d,
++            0x29,0x6d,0x49,0xe6,0x86,0x37,0xd2,0x89,0x53,0x5b,0xc4,0x16,0x3c,0xb2,0x11,0xdc,
++            0xa8,0x14,0x76,0x4b,0xf3,0x60,0xd4,0xc7,0x32,0xaf,0xf6,0x1f,0x01,0xb1,0x16,0x1b,
++            0xb7,0xdd,0xec,0x3f,0xa7,0x12,0x77,0x88,0xdb,0x59,0xa6,0xa3,0x58,0xbe,0xb8,0xff,
++            0xf4,0x11,0xfe,0x03,0x34,0x8f,0x6e,0x27,0x64,0x93,0x93,0xa0,0x7e,0x86,0x9b,0xe3,
++            0x85,0x8c,0xf6,0x13,0x35,0xaa,0xc8,0x17,0xe0,0xee,0xa0,0xc7,0x77,0x65,0x07,0x29,
++            0xe3,0x0a,0x21,0x77,0xf2,0xa5,0x6f,0x26,0x61,0xed,0xa9,0xd6,0xfa,0x07,0x5b,0x12,
++            0x6a,0x67,0x6b,0x24,0xfd,0x8c,0xcd,0xf6,0x0b,0xb2,0xcf,0xb1,0xff,0x85,0xa4,0x22,
++            0xf5,0x61,0x57,0x37,0x30,0x87,0x28,0x64,0xa2,0xc5,0x7c,0x40,0xbb,0x85,0x48,0x2e,
++            0x62,0x01,0xe8,0xd2,0x15,0xf6,0x20,0xc0,0xd9,0xb0,0xca,0xa6,0xb8,0x21,0x79,0xbe,
++            0x0d,0x80,0x52,0xb6,0xe6,0x16,0x39,0x92,0x46,0xeb,0x8f,0x87,0xd6,0xe3,0x2b,0x53,
++            0x82,0x65,0x19,0x37,0x60,0x42,0xf9,0x82,0xe5,0xb3,0xe7,0x97,0xb1,0x62,0x92,0xf8,
++            0xd8,0xb9,0x22,0x7e,0x7a,0x4f,0x2c,0x14,0x29,0x4c,0xaa,0xd2,0xf4,0x65,0x78,0xeb,
++            0x85,0x04,0x8e,0xf1,0x11,0x69,0x3a,0xb2,0x6d,0xe2,0x29,0x45,0xa5,0xb0,0x7d,0x0f,
++            0x69,0x89,0xfd,0x0a,0xbc,0x91,0x6a,0x5a,0xee,0xc3,0x6e,0xa9,0xba,0x81,0xf4,0xe9,
++            0x19,0xba,0x8c,0x0f,0x72,0x4f,0x63,0x29,0x29,0xb4,0x20,0x98,0x13,0x66,0x1b,0xa9,
++            0xef,0xb3,0xfa,0xb7,0xeb,0x40,0x86,0x94,0x94,0xb7,0xac,0x6b,0x7e,0xb7,0xcb,0x27,
++            0x63,0x8e,0x35,0x1b,0xf2,0xdc,0xc4,0x74,0xaa,0x72,0x49,0x83,0xae,0xce,0x83,0xf9,
++            0x02,0x04,0x07,0xb3,0x63,0x4c,0x39,0x52,0xb2,0x0c,0xd3,0x1e,0xbc,0xcf,0x35,0xe9,
++            0x7e,0xac,0x2c,0x2e,0xef,0xf9,0x65,0xad,0xab,0x90,0x8d,0x83,0x26,0xce,0x7a,0x87,
++            0x81,0x51,0xfa,0x21,0xdb,0xb3,0x6a,0xa7,0x44,0xfd,0x33,0x00,0x76,0x13,0xac,0xe2,
++            0x43,0x96,0xbe,0x87,0x92,0x92,0x0f,0x43,0xe5,0xdc,0x3c,0xd6,0xc6,0x14,0x5f,0x8a,
++            0xd8,0xbd,0xba,0x96,0xf7,0x3d,0x83,0x90,0x41,0xd3,0x71,0xe7,0x7c,0x7e,0x73,0x96,
++            0x00,0x52,0xf3,0x21,0xda,0x3c,0x4f,0x03,0x0a,0x37,0xa5,0x5a,0x9a,0x7c,0x44,0x44,
++            0x76,0x45,0xbd,0xb7,0x10,0xbd,0xf4,0x93,0xc1,0xd7,0x86,0xe2,0xba,0x17,0x8c,0x60,
++            0x41,0x6a,0x0c,0x68,0x15,0x38,0x27,0xd7,0xc2,0xea,0xe2,0xdc,0x75,0x77,0xe6,0x64,
++            0x7e,0x95,0xe5,0x4f,0xb3,0xa4,0xb2,0x12,0x6e,0x5b,0x71,0x14,0x51,0x36,0xf6,0x61,
++            0x47,0x48,0x36,0xf2,0x12,0x2c,0x03,0x13,0xe7,0x6a,0xed,0x97,0x04,0x12,0x5c,0x86,
++            0x50,0xb7,0x06,0xf7,0x3e,0x5b,0x86,0xdb,0x04,0xf9,0x16,0xdf,0x0c,0xfd,0x70,0x9f,
++            0x88,0x58,0x3a,0xfe,0xd2,0x3a,0xbe,0xca,0x0b,0xde,0xa0,0x5e,0x1b,0x5c,0xa7,0xfb,
++            0xca,0x9d,0x73,0xef,0x53,0xcb,0x2f,0x99,0xfd,0xf5,0x85,0x7f,0x13,0x3e,0x71,0x9e,
++            0x08,0x84,0x4f,0x2d,0xdb,0xc4,0x61,0xbe,0xcd,0x5d,0xe1,0xba,0x58,0xa4,0xe9,0xa7,
++            0xf7,0xc3,0x46,0x92,0xb7,0x5e,0x64,0xd8,0xf9,0xf3,0xee,0xdd,0x5c,0xd3,0x1c,0xe2,
++            0x05,0x5f,0x31,0x1b,0xd2,0x1e,0xb9,0x0b,0xe7,0x50,0xa0,0x5d,0x5f,0xdc,0x87,0x79,
++            0x89,0xab,0x6c,0x48,0x29,0x01,0xf7,0x9a,0x49,0xdd,0x07,0x93,0x90,0x5d,0xd7,0xea,
++            0x8f,0x53,0x28,0xae,0x99,0xe9,0xa6,0xde,0x4a,0x33,0xce,0x0e,0x7f,0xf2,0x5e,0x04,
++            0xe5,0x03,0x98,0xf5,0x32,0xc5,0x83,0xc0,0x3f,0xe0,0xcf,0xdc,0x52,0x30,0xd7,0x60,
++            0x2b,0x5e,0x05,0x69,0x88,0xfd,0x65,0x38,0x41,0x71,0x07,0x74,0xf4,0x34,0x53,0xf0,
++            0x08,0xc3,0x99,0xf4,0xba,0xe3,0xec,0x22,0xf3,0x45,0x5c,0x59,0x55,0xef,0x17,0x3f,
++            0x0a,0x75,0x12,0x59,0x74,0x9c,0x1b,0xcf,0x45,0x38,0x2e,0x08,0xf7,0x9f,0xb4,0xb1,
++            0x28,0x24,0xa8,0x42,0x91,0x15,0x8f,0x09,0xcb,0x32,0xc8,0x99,0xa3,0x87,0xa8,0xf7,
++            0xfc,0x8f,0x96,0xf7,0xe6,0x03,0xd8,0x61,0x61,0xa1,0x86,0x70,0x34,0x20,0xf2,0x62,
++            0xfb,0xe8,0x4d,0x3c,0x5c,0x57,0x39,0x13,0x0e,0xa5,0x0a,0x97,0xe6,0x17,0x6a,0xd7,
++            0xa9,0x4a,0x7a,0xa4,0xb5,0xbc,0x27,0x91,0xc3,0xfa,0x2a,0x84,0x5b,0xa6,0x99,0x7a,
++            0x8c,0x97,0xdb,0x2a,0xf5,0x19,0xbc,0xd3,0xe1,0x8a,0x0d,0x61,0x5a,0x6b,0x70,0x15,
++            0x75,0x26,0xb9,0xbb,0xea,0xe8,0x60,0x53,0x35,0x66,0xd2,0x5c,0xaa,0xab,0x79,0x09,
++            0x1e,0xcb,0xb5,0x6d,0x63,0x07,0xac,0xf8,0x31,0x8b,0x6d,0xed,0x7d,0x15,0x8b,0x69,
++            0xef,0x0c,0x84,0x60,0x44,0x26,0x9b,0x49,0xaf,0x4c,0xa7,0xb2,0x09,0xc8,0x39,0x69,
++            0x71,0x02,0x39,0x38,0xe5,0x07,0xb2,0xea,0xee,0xc1,0xac,0x8c,0x5a,0x69,0x85,0x64,
++            0x21,0x78,0x06,0x2d,0x35,0x5b,0x24,0x98,0x4b,0xf0,0xc4,0x9c,0x3d,0x1b,0xb8,0x6d,
++            0x8a,0xe7,0x9b,0x4b,0x7e,0x51,0x88,0x4c,0x6f,0x31,0xe1,0xbd,0x35,0xaa,0x39,0x60,
++            0xc8,0x14,0xd5,0xbd,0xfe,0xab,0x49,0x4b,0x0c,0x60,0x85,0x78,0xfb,0x4b,0x90,0xe0,
++            0xdf,0xf5,0x1f,0x36,0xd0,0x6f,0x14,0xdb,0xc5,0x5a,0x00,0xc4,0x1c,0xb3,0xd3,0x7a,
++            0x2e,0xd3,0x1c,0x12,0x18,0x4f,0x44,0x5a,0x71,0x90,0x47,0x4e,0x75,0x4a,0x1d,0x7d,
++            0x08,0x9f,0x65,0x22,0x51,0x29,0xb2,0x21,0xc6,0xa0,0x4a,0xd4,0xde,0x21,0x6d,0x46,
++            0x44,0x3c,0x97,0x64,0xc1,0x1e,0x2f,0xb2,0x1a,0x5e,0x3d,0x33,0xa1,0xa2,0x73,0x2a,
++            0x59,0xd9,0xec,0xc2,0xb1,0x05,0x13,0x19,0xd3,0x42,0xa6,0xc4,0x9d,0x90,0x94,0xa1,
++            0x5f,0xf9,0x13,0x3e,0x99,0xf8,0x28,0x89,0xb1,0x7a,0x01,0x1a,0x77,0x4e,0x1b,0xfa,
++            0xc5,0x69,0xb5,0xfe,0xac,0x0b,0x5a,0xa4,0x38,0x79,0xcd,0xc3,0x1f,0x3c,0x0b,0x02,
++            0xa6,0xb7,0x7a,0x28,0xa5,0xfa,0x2d,0x53,0x0a,0xa7,0x97,0xd3,0x0b,0xe6,0xb5,0x79,
++            0x50,0x37,0x35,0xc9,0xf6,0x72,0xe2,0x54,0x48,0xde,0x1a,0xc1,0xa2,0x07,0x74,0x86,
++            0x15,0x36,0x6e,0x3b,0xc6,0x62,0xba,0x45,0x49,0x76,0xd6,0xb9,0xde,0x9c,0x77,0x78,
++            0x86,0xdb,0xaf,0x8b,0xb5,0x5b,0x17,0xf2,0x4d,0x50,0x0e,0x31,0x7f,0xbe,0x8f,0xe9,
++            0xcf,0x1c,0xaf,0xec,0xdb,0xb1,0x9f,0xc9,0x8f,0x5c,0x00,0x5d,0xfb,0x98,0xf6,0xb8,
++            0xc5,0x4d,0xb4,0xce,0xc9,0xd2,0xda,0x98,0xa4,0xff,0x2d,0xee,0x97,0x36,0x7c,0x24,
++            0x94,0x39,0xaf,0xb8,0xe9,0xb5,0x2e,0x09,0x4d,0x70,0xa5,0xfe,0x7b,0x4d,0x19,0xf6,
++            0x47,0x54,0xbe,0x7c,0x1b,0x48,0x09,0x4a,0x0f,0x78,0x0a,0x03,0xfe,0x41,0x78,0x39,
++            0x4f,0x34,0xeb,0xfb,0x30,0xfe,0x2b,0xca,0x93,0x70,0x53,0x8c,0xdd,0x59,0x9b,0x73,
++            0x79,0x89,0xbe,0xb5,0xda,0x03,0x80,0x5f,0x9a,0xcb,0x42,0x1b,0x3e,0xff,0x12,0x12,
++            0x93,0x40,0xee,0xb4,0xfa,0xa2,0x38,0xba,0x65,0x4c,0x23,0x76,0xf0,0x9c,0x21,0xeb,
++            0x69,0xf3,0xff,0xb4,0x79,0xa1,0x31,0xcb,0x35,0xcb,0xee,0xa1,0x84,0x1c,0xba,0xb0,
++            0x7d,0x40,0xb7,0xb0,0xf1,0x3f,0xe0,0x16,0x60,0x3c,0xb1,0x57,0x25,0xe0,0xc8,0x2c,
++            0x61,0x24,0x16,0xd3,0x30,0x29,0xa7,0x82,0xc0,0x0c,0xc8,0x71,0xd0,0x4c,0x70,0x00,
++            0x07,0x0a,0xe2,0xd1,0x50,0xc5,0x20,0x12,0x02,0x65,0xa0,0x07,0x63,0xe2,0x39,0xc3,
++            0x83,0x64,0x41,0x54,0xe2,0xdb,0x9d,0x03,0x83,0x06,0xae,0x07,0x93,0x26,0x71,0x01,
++            0xc3,0x08,0x99,0x37,0x97,0x87,0x21,0xf3,0xc6,0x7e,0x26,0x70,0xac,0x98,0x59,0x08,
++            0x0e,0xd8,0x7d,0x7e,0x72,0x6b,0xbe,0x0c,0x99,0xb5,0x25,0x9d,0x5e,0x4b,0xda,0x3c,
++            0xa8,0x96,0x1d,0x62,0xd3,0xf8,0x43,0xf8,0xec,0xe6,0xf2,0x5e,0xae,0x2b,0x92,0x17,
++            0xa2,0xfe,0x78,0x4a,0x65,0x8c,0x38,0x52,0xe9,0x9a,0x82,0xef,0x79,0x95,0xbf,0x7b,
++            0x06,0x8d,0x83,0x99,0x70,0x88,0xc9,0x31,0x6c,0xe4,0x1c,0x49,0xfd,0x6d,0x22,0x08,
++            0x0c,0x01,0xd5,0x9f,0x76,0x51,0x08,0x69,0xe9,0x4a,0x42,0x1f,0x62,0xcd,0x72,0x08,
++            0x2b,0x02,0x80,0xa2,0xb8,0x2b,0x56,0xef,0x0b,0x42,0xc0,0xf8,0x26,0xeb,0x49,0x48,
++            0x29,0x6b,0xa3,0x0c,0x21,0x23,0xdb,0x11,0x69,0x48,0xc2,0x92,0xfe,0x95,0x73,0x09,
++            0x8a,0x00,0xc7,0xa6,0x3a,0xa5,0x3b,0x3d,0xf7,0xcd,0xbb,0x39,0x95,0x62,0x94,0xc7,
++            0xc9,0x81,0x87,0xf7,0x5a,0xb1,0x29,0x70,0x3c,0xfb,0xf4,0xe5,0x89,0x7d,0x99,0x03,
++            0x59,0xce,0xde,0x24,0xce,0x9e,0x64,0x10,0x8a,0x72,0x96,0xb0,0xd2,0x77,0x63,0xbd,
++            0x5f,0xbf,0x7a,0x76,0x9e,0x9f,0x6d,0x81,0x00,0xf6,0xdf,0x5b,0x53,0x7f,0x9d,0xf3,
++            0x4a,0x62,0x5d,0xd2,0x58,0x50,0x7d,0xb3,0xb8,0x5e,0x91,0x56,0x50,0xf9,0xb4,0xa2,
++            0x61,0xe4,0xfa,0xfc,0xbf,0xb2,0x34,0xa1,0x95,0x59,0xea,0x99,0xd1,0x11,0x44,0x72,
++            0xd2,0x1a,0xdd,0xd5,0xb3,0x55,0x50,0x0b,0xc2,0xdd,0xb9,0x09,0xf0,0xd8,0x4f,0xe1,
++            0x01,0x10,0xc4,0x85,0xfa,0x9d,0x1f,0x1a,0x41,0x50,0xeb,0x05,0x51,0xad,0xf9,0xaa,
++            0x00,0x11,0x93,0xfd,0x4c,0x9a,0xdd,0x13,0x88,0xb6,0x4e,0xc5,0xfb,0xc8,0xb2,0xea,
++            0xc3,0x89,0xe0,0xb1,0xd1,0x7b,0xd2,0x2d,0x66,0xd2,0x6d,0x4e,0xd9,0xf2,0x76,0x9c,
++            0xc9,0x98,0xa8,0xa0,0x1f,0x9d,0x25,0x89,0xc8,0xd8,0xe0,0xde,0x3a,0xa6,0x97,0xfa,
++            0xc4,0xb1,0xe1,0xb1,0xbb,0xfa,0x13,0xd0,0xc9,0x78,0xe8,0x4f,0x7a,0x52,0xe5,0xbd,
++            0x16,0xa6,0x18,0x38,0x34,0x96,0xd6,0x4a,0x6d,0xd6,0xe7,0xdf,0xba,0xc4,0x4e,0x5d,
++            0xd7,0x13,0x53,0x8b,0xf8,0x2c,0xd7,0x6c,0x04,0xba,0xec,0x5d,0x02,0xe3,0x36,0x5a,
++            0x2e,0x39,0xac,0xd4,0x3a,0x9d,0xcf,0x87,0xaa,0x3f,0x84,0xfd,0xa5,0xc2,0x27,0x8d,
++            0xf5,0x93,0xcf,0x4d,0x53,0x8f,0x47,0x8b,0xee,0xfe,0x17,0x98,0xfb,0x12,0x77,0x89,
++            0xa3,0x10,0x91,0xf4,0xb7,0x3b,0x15,0xec,0xcb,0x52,0xe5,0x63,0x08,0xd2,0x21,0x78,
++            0x65,0x84,0xb2,0x4c,0xeb,0x2d,0xe6,0xa0,0xc4,0xba,0x38,0x31,0xb5,0xef,0x42,0x23,
++            0x35,0x2e,0x96,0xb3,0xcb,0x0c,0x80,0xc1,0x23,0xd1,0xf2,0xcd,0xf6,0xe7,0x43,0x01,
++            0xa0,0x09,0xf7,0xb7,0x63,0xcc,0x11,0x3b,0xf7,0x5a,0xd1,0x66,0x21,0xef,0x89,0x61,
++            0xe7,0x75,0x79,0x89,0x94,0x63,0x81,0xc0,0xab,0xc5,0xb5,0xd1,0x74,0x69,0x00,0x02,
++            0x00,0x89,0x1b,0xa4,0xff,0xf5,0x08,0x46,0xa7,0x6b,0x0f,0x34,0x15,0x14,0x62,0x42,
++            0xa4,0x83,0x6d,0x25,0x67,0x23,0x6b,0x81,0x3f,0xc3,0x86,0x4f,0x47,0xa8,0x6b,0x47,
++            0x25,0x8b,0x4d,0xd5,0x86,0xae,0xe0,0x90,0xfa,0x69,0x61,0x8f,0x17,0xab,0xe1,0x63,
++            0xe4,0xa7,0xe8,0x17,0xdf,0x0c,0xf1,0x36,0x66,0x4d,0x87,0x4b,0x9f,0xec,0x5c,0x0d,
++            0xad,0xc9,0xf8,0xdf,0x6c,0xb7,0x12,0xf2,0xed,0xf7,0xcd,0xcc,0xde,0xc0,0xd5,0x69,
++            0x67,0xea,0x7e,0x8d,0x77,0x04,0x42,0x1a,0xad,0x6d,0xc2,0xbc,0x54,0x36,0x1d,0xbf,
++            0xe4,0x87,0x99,0xe9,0x11,0x07,0x19,0xfb,0x90,0x61,0x49,0x4d,0x9f,0x55,0xd0,0x64,
++            0xed,0x9a,0x7b,0x8c,0xff,0xa3,0x43,0x07,0x26,0x3a,0x83,0xef,0x26,0xe4,0x1a,0xc8,
++            0x0f,0xe1,0xf3,0x4a,0x9e,0xde,0x89,0x88,0xcc,0xe4,0xcc,0x8e,0x7d,0xac,0x50,0xb8,
++            0x8d,0x85,0xeb,0x1e,0x57,0x20,0x02,0xf8,0x46,0xf2,0xec,0x1c,0xa0,0x40,0x1b,0xc9,
++            0x8f,0xeb,0xdd,0x63,0x13,0x28,0x8a,0x09,0x8d,0x71,0xf5,0x12,0x37,0x3f,0x9f,0xb9,
++            0x0d,0x87,0x95,0x77,0x1f,0x5f,0x43,0x2b,0xcb,0xc0,0xec,0xfb,0xa9,0x4e,0xc1,0x72,
++            0xa4,0x8f,0x70,0x15,0x48,0x1f,0x66,0x05,0x62,0xf3,0xcc,0x24,0x7d,0x4f,0xbc,0x63,
++            0x86,0xd1,0x3f,0x65,0x13,0xdd,0xbb,0xc8,0x0d,0xdc,0x84,0x66,0x8e,0xfe,0x1e,0xf3,
++            0x24,0x84,0x71,0xf4,0x92,0x14,0xf6,0x4b,0xdb,0xd6,0x8d,0x77,0x03,0xfd,0x1f,0xa3,
++            0x22,0xd2,0x93,0x26,0x7f,0x42,0x2f,0x0b,0x0e,0x97,0xdd,0xf6,0x71,0xfe,0x04,0x86,
++            0xa6,0x99,0x61,0xb4,0xdd,0x85,0xf4,0xf3,0x5a,0x7a,0x67,0xd7,0xd7,0x0b,0xe4,0x06,
++            0x44,0xf5,0x13,0x27,0x0f,0x4a,0x01,0x90,0x24,0x6a,0xa6,0x30,0x0b,0x5a,0x6f,0xc1,
++            0x05,0x90,0xc5,0xd3,0xdd,0xa7,0xe3,0x8c,0x64,0xfe,0xcb,0xde,0xd8,0x29,0x15,0x51,
++            0xa2,0xcd,0xd3,0xff,0xd6,0xf7,0x05,0x91,0xa6,0xf7,0x5d,0x07,0x6d,0x24,0x78,0x33,
++            0x2c,0x3c,0xd8,0x3f,0xd5,0x3b,0x0c,0x1a,0xc2,0x9a,0xbc,0xaa,0xdf,0xfe,0x95,0xd4,
++            0x98,0xfa,0x1d,0x3a,0xc1,0xda,0x86,0x49,0x0f,0xc9,0xde,0xff,0xf9,0xf4,0xed,0x37,
++            0x88,0xc6,0xc1,0xb3,0x57,0x39,0x63,0x37,0xdf,0xe1,0xbf,0x0a,0x1d,0xf5,0x49,0xf9,
++            0x16,0x84,0x6f,0x3e,0x8d,0x6e,0x87,0x48,0x87,0xb7,0xf5,0x44,0x5e,0xfd,0x1e,0x48,
++            0x2b,0x95,0xfe,0xde,0xd7,0xad,0x0e,0x68,0x67,0x63,0x88,0xe9,0x8f,0xf3,0x34,0x25,
++            0x8c,0x9b,0x93,0xbc,0x7e,0xfd,0x46,0xaa,0x67,0xd2,0xde,0xae,0xde,0x75,0x3d,0x36,
++            0x0d,0xfb,0xbf,0xda,0x3c,0x96,0x4f,0x3b,0x15,0xd1,0x43,0x94,0x5d,0xf8,0x3f,0xf4,
++            0x0e,0x15,0x97,0xac,0x87,0x30,0x21,0xce,0xfb,0x9d,0xdf,0x1d,0xdb,0xff,0xa8,0x38,
++            0x33,0x12,0x6c,0x84,0xec,0x00,0x12,0x46,0x3c,0x0f,0x37,0xbb,0xbb,0xd6,0xc8,0x76,
++            0x20,0xeb,0x59,0x0b,0x2f,0x95,0x41,0x20,0xe4,0x2f,0x2a,0x2b,0xbd,0xce,0xb9,0xe1,
++            0xa9,0x19,0x2d,0x47,0x13,0xf6,0x2b,0xc9,0xd2,0x0d,0xcf,0xbf,0xd4,0xb6,0x59,0x11,
++            0xc2,0x02,0x29,0x0f,0x1d,0xae,0x7b,0x41,0xc0,0xd1,0xaf,0xc4,0x31,0x23,0xe7,0x6d,
++            0xda,0x95,0x67,0x79,0xf3,0x8b,0x31,0x20,0x52,0xd0,0x43,0x63,0xf3,0xfb,0xdb,0xa3,
++            0x7f,0xaa,0xae,0x85,0x12,0x65,0xbb,0x1b,0xe4,0x29,0x8c,0x0e,0x25,0xca,0x7b,0xb2,
++            0xfa,0xa9,0x93,0x36,0xf0,0x4a,0x46,0x7a,0xb6,0x5d,0x65,0x07,0xae,0xc9,0x19,0xd5,
++            0xda,0xce,0xd5,0xba,0x7a,0xed,0x66,0xe2,0xe1,0xea,0x89,0x9d,0xa4,0xaa,0x11,0xc9,
++            0x8f,0x99,0xfc,0x9a,0xf3,0xce,0xaa,0x18,0x9a,0x07,0x3a,0xa6,0xcc,0xfc,0x0e,0xe4,
++            0x81,0xf2,0xe8,0x02,0xcf,0xdd,0xe2,0xd0,0x49,0x04,0x1e,0xfa,0xcb,0x6a,0xc3,0x69,
++            0x98,0x44,0xdd,0x9e,0x88,0x85,0x4a,0x27,0xab,0x6a,0x36,0x36,0xb3,0x1e,0x23,0xf5,
++            0x6d,0x70,0x6c,0xee,0x43,0x80,0x19,0xdf,0xe9,0x9b,0x78,0xc6,0x11,0x9c,0x3c,0xec,
++            0xff,0x8f,0xbd,0xb4,0x1a,0x57,0xc5,0x18,0xca,0x53,0x2d,0x97,0xd5,0xc1,0x62,0x65,
++            0xe0,0x49,0x94,0xf1,0x1f,0xd8,0x12,0x70,0x9b,0xbc,0xa3,0x0d,0x79,0x7b,0xe5,0xba,
++            0xa0,0x85,0x13,0xbc,0xac,0x2d,0x68,0x19,0x4a,0x58,0x87,0xf6,0xb9,0x6a,0x11,0x5a,
++            0xfd,0xfa,0x5c,0x63,0xef,0x6d,0x7c,0xd9,0xf8,0xd9,0xd3,0x6d,0xe8,0xe5,0x1a,0xdc,
++            0xb2,0x1a,0x66,0x97,0x0e,0xd6,0x44,0x39,0x6a,0xdd,0x14,0x55,0xa2,0x30,0xd3,0xa5,
++            0x5a,0x20,0xee,0x90,0xcd,0x75,0x8c,0xd6,0x9a,0xaa,0xc2,0x87,0x75,0xda,0x91,0x21,
++            0xca,0x60,0xbf,0x76,0x7a,0x99,0x4c,0xa1,0x47,0x49,0x36,0x93,0x2c,0x97,0xcd,0x3d,
++            0xa1,0x08,0x3e,0x92,0x65,0xe5,0x19,0x35,0xc4,0xf2,0xaf,0xb1,0x74,0x65,0xab,0xd3,
++            0x04,0x50,0xfa,0x64,0x53,0x30,0x2d,0x1b,0xb3,0x89,0x00,0x77,0x2f,0xd9,0x34,0xd4,
++            0x96,0x57,0x9c,0x70,0xfb,0x16,0x5e,0x82,0xdc,0x51,0xe2,0x50,0x12,0x71,0x63,0x60,
++            0x2e,0xbd,0xa4,0x85,0xf6,0x92,0x7e,0x9b,0xc0,0xbb,0x5e,0x95,0x72,0x69,0x0d,0xf3,
++            0x02,0xc8,0x19,0x3d,0x98,0xfa,0x9d,0x36,0x1a,0xd1,0xbc,0xb5,0xef,0xd3,0xe7,0xee,
++            0xd7,0x76,0x21,0x13,0x53,0x8e,0x2c,0x57,0xe8,0x79,0x37,0xb6,0xe4,0xcc,0x2e,0x72,
++            0x40,0xf8,0x2d,0xaa,0xe5,0xdc,0xd9,0x3a,0xe9,0xf3,0xff,0x1c,0xaf,0xc6,0x39,0xa1,
++            0x76,0x91,0x07,0x7c,0x6a,0x7a,0x4e,0x2d,0x4d,0x51,0xc9,0xa2,0xbe,0x34,0x6e,0xd9,
++            0xe9,0x55,0xd1,0xae,0xbd,0x90,0x27,0x69,0xb5,0xf0,0xa1,0x00,0x91,0x8c,0xf2,0xaa,
++            0xd5,0xb8,0x39,0x8b,0xd3,0x5f,0xa9,0x92,0x0b,0x58,0x06,0xb0,0xb2,0x1f,0xea,0x29,
++            0x88,0x5d,0xd0,0x78,0xa9,0x37,0x83,0x07,0xeb,0x3d,0x8c,0x1a,0x92,0xfe,0x15,0xcf,
++            0x62,0x7d,0x20,0x3d,0x3a,0x21,0x35,0xeb,0xeb,0xde,0x58,0x05,0x85,0xd3,0xf6,0x5d,
++            0xa9,0x1a,0xd3,0xae,0xfc,0xbe,0xf2,0x82,0x76,0xf2,0x1f,0x58,0x59,0xd2,0x31,0x11,
++            0x4b,0x88,0xc3,0x02,0xe8,0xe4,0xb7,0x50,0xbb,0x82,0x67,0x35,0xa2,0x33,0x00,0xea,
++            0xc9,0xc3,0x0f,0x21,0x7e,0x04,0xd0,0xb7,0xc5,0x41,0xcb,0x8e,0x9d,0xb2,0x07,0xcb,
++            0x8d,0x39,0x12,0x00,0x40,0x67,0xa9,0x52,0xc5,0xd2,0x97,0x9c,0xae,0x46,0xe6,0xeb,
++            0xf2,0x46,0x29,0xe6,0x75,0xe3,0x03,0xdb,0x51,0x8c,0x5b,0x24,0xeb,0x05,0xc0,0xb1,
++            0x28,0x70,0x2a,0x29,0x9b,0x09,0x4d,0x84,0x66,0xa7,0xd0,0xef,0xdb,0x69,0xd1,0x0d,
++            0x01,0x7f,0xc8,0x96,0x33,0xc9,0x06,0x74,0xa6,0x46,0xf8,0x88,0xda,0x48,0x33,0x31,
++            0x31,0x7a,0xb1,0x37,0x16,0x20,0x61,0x93,0x51,0xf7,0x16,0x98,0x37,0x60,0xbb,0x18,
++            0x7a,0xbb,0xd3,0xc4,0xbd,0x08,0x8b,0x80,0x4b,0xca,0xad,0xe8,0x22,0x6e,0xfd,0x22,
++            0x0a,0xdb,0x0a,0x84,0x88,0x3c,0x6b,0xd6,0xa9,0x37,0x88,0xdd,0x96,0x43,0xd5,0xdd,
++            0xe4,0x71,0xee,0xd8,0x8f,0xaa,0x60,0x38,0xfe,0x60,0x09,0x39,0x89,0x3f,0xd8,0xe3,
++            0xfb,0x47,0x06,0x14,0xf7,0xde,0xdf,0x58,0x91,0x3c,0xd1,0x2b,0x20,0xae,0xcc,0xeb,
++            0x0d,0x94,0x48,0xe4,0x55,0xf8,0xb0,0xb1,0xce,0xab,0x1c,0xa0,0xb6,0x5d,0x5f,0x8d,
++            0xcc,0xec,0xb6,0x3c,0xd4,0xaf,0x8d,0x96,0x4e,0x8e,0xd2,0x84,0xb7,0xef,0xaa,0x03,
++            0x69,0x00,0xbe,0xcd,0x31,0x00,0x78,0x24,0xeb,0x20,0xfc,0x96,0x0a,0xa0,0x6b,0x46,
++            0x6f,0xf1,0x9d,0xef,0x11,0x03,0x74,0x2c,0x33,0xd5,0xe9,0x6d,0x4c,0xe4,0x13,0x7c,
++            0x2c,0xa7,0x3b,0x2f,0x1f,0xb0,0xbf,0x25,0xc1,0xd1,0xf9,0x99,0x50,0x42,0x63,0x80,
++            0x6c,0xd2,0x96,0x82,0xb1,0xa6,0x4c,0xae,0x84,0x2f,0xca,0x1b,0x9d,0x23,0x75,0x16,
++            0x80,0x9a,0xf2,0x99,0x7b,0xff,0xdb,0xc1,0xc6,0x58,0x82,0x0f,0x1f,0x46,0x7d,0xcf,
++            0x24,0xc4,0x04,0x9d,0x28,0x06,0x6c,0xa3,0x41,0xbc,0xe3,0x19,0x1f,0x21,0xaf,0x7b,
++            0xbb,0xde,0xcc,0x37,0x63,0x0c,0x1d,0x59,0x86,0xd7,0xc3,0x0e,0x1c,0x60,0x5c,0x38,
++            0x8a,0x99,0x1b,0x39,0xd7,0x37,0x6f,0xce,0x60,0x6c,0x24,0x04,0xda,0x59,0x8f,0x89,
++            0xda,0x29,0xd4,0x29,0xc2,0xd6,0xc5,0x82,0x33,0xdc,0xa2,0x14,0x73,0x70,0xc9,0x5c,
++            0x59,0x0b,0x1a,0x39,0x4b,0x17,0xe6,0x8c,0x45,0x86,0x21,0x05,0x1f,0x3c,0x16,0x57,
++            0xfe,0x54,0x16,0xa4,0xcb,0x46,0xfd,0xb2,0x8b,0xc2,0x4e,0x15,0x9f,0x06,0xd9,0x88,
++            0x28,0x63,0x9c,0x7d,0xfa,0x17,0x57,0xea,0x24,0x23,0xe0,0x14,0x97,0x6b,0x89,0x78,
++            0xcd,0x66,0xd0,0x0c,0xc1,0xfd,0x2e,0xa7,0x2d,0x54,0x89,0x07,0x8e,0xf7,0x36,0x63,
++            0xbe,0xd7,0x41,0x7e,0x76,0xaa,0x33,0x2f,0xdd,0x73,0x00,0x12,0x08,0x29,0x76,0x9a,
++            0x0a,0x80,0x1c,0x98,0x69,0x6d,0x66,0xbb,0x4a,0x9a,0xd7,0x39,0x01,0xba,0x5d,0x28,
++            0x82,0x21,0x98,0xc8,0xd7,0x6d,0xe3,0xdc,0x16,0xcc,0x88,0xd3,0x8b,0x5f,0x50,0xe3,
++            0x4e,0x99,0x15,0xf9,0x9e,0x42,0xcc,0xc7,0x7f,0x18,0xac,0x9f,0x37,0xbc,0x1f,0x0c,
++            0x64,0x4f,0x34,0x3c,0x32,0xb3,0xc5,0xd7,0x5e,0x4f,0x64,0x1c,0x8a,0x5e,0x16,0xa1,
++            0xce,0x9b,0xc9,0xe2,0x3b,0x1b,0x2f,0xdf,0x3b,0x0e,0x58,0xd2,0x7a,0x6e,0x59,0x9f,
++            0xa5,0x0b,0xe3,0xc4,0x14,0xb4,0x06,0x18,0x46,0xf8,0xee,0x22,0xdd,0xdd,0xf7,0x98,
++            0xa4,0xbe,0x9b,0x72,0xea,0x20,0x5e,0x0b,0x7d,0x03,0xe1,0x4c,0xc3,0x6b,0x52,0xe9,
++            0x2c,0x4f,0x0f,0xc3,0x9a,0x39,0x36,0x43,0x3f,0x4b,0xf7,0x23,0xb3,0x66,0x96,0xf1,
++            0xa7,0x05,0xb1,0x11,0x14,0x01,0x45,0x34,0xf2,0x35,0x5a,0xc5,0xed,0x52,0xcf,0xdf,
++            0xfd,0xa9,0xf8,0x14,0x1a,0x2b,0x06,0x1d,0xa9,0xbd,0xe8,0xb4,0xed,0x6b,0x37,0x22,
++            0xc1,0x05,0xc2,0x14,0xb0,0x23,0x60,0x20,0x63,0x4a,0xe0,0x24,0x57,0x6a,0xca,0xdf,
++            0x75,0x47,0xa1,0xe5,0x2e,0x2b,0xc1,0xe3,0x42,0xce,0xe9,0x35,0xda,0x69,0x32,0x16,
++            0x7e,0xb1,0x99,0x44,0x32,0xaf,0xc9,0x0e,0xcd,0x25,0x06,0x9b,0xd5,0x9e,0x22,0xcc,
++            0xa9,0x82,0xdb,0x1b,0xfd,0x46,0xaa,0xd6,0xb5,0x26,0xeb,0x4a,0xa7,0xe3,0x38,0xe7,
++            0xf0,0x4b,0xbe,0x22,0x39,0x0b,0x09,0x28,0xa2,0xf8,0xca,0xbd,0x11,0xe2,0x84,0xf8,
++            0x2b,0x4a,0xe1,0x0c,0x9b,0x6a,0xf0,0xe9,0x84,0xe7,0x84,0xa9,0xdb,0x11,0x04,0x8a,
++            0x28,0x94,0x0c,0x66,0x97,0x2d,0x3b,0x30,0x81,0xda,0xd3,0x10,0x59,0xab,0x79,0x38,
++            0x8a,0x13,0xc3,0xae,0xb6,0xa7,0x18,0xd5,0xb5,0x20,0xb0,0xe8,0x71,0xba,0xda,0xa7,
++            0xf0,0xa0,0x4f,0x3e,0x58,0x22,0xca,0xdd,0xbc,0xb0,0x8a,0x58,0xba,0x62,0xf8,0x39,
++            0x0a,0x18,0x44,0xaf,0x18,0x2d,0x0a,0xd7,0x6f,0xb8,0x13,0x8c,0x42,0x68,0xc4,0xc2,
++            0xe8,0x0b,0xb3,0xdf,0xb9,0x0d,0x49,0xab,0x34,0x92,0xbb,0x3d,0xca,0xef,0x17,0x68,
++            0xfe,0x5d,0xe1,0x44,0x91,0xb8,0x1c,0xb0,0x81,0x42,0xce,0x89,0x4c,0x6f,0x8e,0xb0,
++            0x51,0x71,0x31,0xd3,0xfb,0xd9,0x1a,0x58,0x99,0xfc,0x09,0x5e,0xd4,0x1d,0x5d,0x84,
++            0x82,0x83,0x8d,0x67,0x8f,0x12,0xed,0x85,0x1d,0x59,0x2d,0x5a,0x93,0xe3,0xcd,0xe8,
++            0x35,0xbe,0x85,0x91,0x19,0x8d,0x0a,0x57,0xd2,0xe6,0x7a,0x4b,0x55,0x9e,0x1d,0x6a,
++            0xcb,0xcc,0xfc,0x14,0xff,0xbc,0xad,0x93,0x58,0x36,0x78,0x7a,0x71,0x64,0xb4,0xf4,
++            0x54,0x23,0xb5,0x36,0xb1,0xd6,0x98,0x92,0x20,0xea,0xcc,0x74,0x86,0x7a,0xbd,0xc9,
++            0x4b,0xee,0xc4,0x27,0x13,0xbc,0xa8,0xc5,0x60,0x5e,0x8f,0x82,0x8e,0x34,0x92,0x13,
++            0x90,0xbb,0x19,0xb7,0xf0,0xc9,0x25,0x93,0xa0,0x28,0x62,0xc4,0x52,0xd6,0x93,0x3a,
++            0xd7,0x08,0x3b,0xbd,0x99,0x07,0xae,0xd9,0x10,0x51,0x52,0x53,0x1b,0x72,0xbb,0x7e,
++            0xa9,0x61,0x4d,0x6c,0x0d,0x08,0x1f,0x48,0x2d,0x16,0x21,0x5e,0x65,0x7d,0x3d,0x7a,
++            0xd0,0x01,0x2b,0x1e,0xff,0x30,0x16,0xdb,0xfa,0x15,0x02,0x29,0xfb,0x0b,0x31,0xb4,
++            0x4b,0xc4,0xf6,0xfb,0x46,0xb0,0x8f,0x51,0x19,0x16,0xf4,0x99,0x74,0xf6,0xfe,0xf8,
++            0x2e,0xa3,0xbe,0x4e,0x3f,0x35,0x2e,0x6a,0x48,0x29,0xee,0x13,0x83,0xdd,0x35,0xfc,
++            0xc2,0xd7,0xae,0x98,0x6c,0xbd,0x66,0x28,0xd4,0x52,0x05,0xec,0x18,0x69,0x06,0xaf,
++            0xc8,0x1e,0xfd,0x2f,0x16,0x31,0x6f,0xb9,0xaa,0x51,0xef,0xdc,0x5b,0xc1,0x11,0x3b,
++            0xaf,0x9a,0xb7,0xfa,0x1a,0xb7,0x3f,0x59,0xe9,0xd4,0xc8,0x79,0xdb,0xe5,0x94,0x60,
++            0x89,0x76,0xc5,0xc6,0xb7,0xbb,0x0e,0x1a,0xc9,0x46,0xe9,0x2d,0xb1,0x91,0xd3,0x96,
++            0x26,0x92,0x97,0xf4,0x95,0xc3,0x2f,0x52,0x0d,0xaf,0x2d,0x48,0xf6,0x91,0xde,0x79,
++            0x4e,0x8d,0xb6,0x83,0x97,0xe3,0x33,0x63,0x0b,0x6f,0xa3,0xe7,0xd2,0xe8,0x70,0x34,
++            0x20,0xc1,0xf0,0x2f,0x93,0xa9,0x5b,0x23,0xc4,0xf3,0x99,0xb9,0xe6,0x72,0x19,0x33,
++            0x53,0x92,0xba,0xdf,0xb5,0xa2,0x22,0xfd,0xb1,0x85,0x88,0x14,0xa9,0xa6,0x00,0x6f,
++            0xec,0xc1,0x13,0xb4,0xb6,0x2f,0x79,0x94,0x63,0xb9,0x78,0x97,0x5a,0xe3,0xf1,0xe6,
++            0x71,0x0d,0x69,0x82,0x37,0x2c,0x4b,0x8b,0x78,0x89,0xad,0xd2,0x37,0x19,0x33,0xd8,
++            0xf1,0x28,0x96,0xb5,0x15,0xef,0xc6,0x3c,0x52,0x1a,0x0f,0xb1,0x76,0x65,0x2d,0x4f,
++            0xad,0x17,0x32,0x75,0xbf,0xb3,0x08,0xc2,0xbc,0x87,0x0a,0x69,0x52,0xee,0x11,0x84,
++            0x0e,0x29,0xca,0x95,0x1e,0xa6,0xaa,0xd2,0xb5,0x84,0xbe,0x51,0xd0,0xf2,0x97,0x69,
++            0x01,0x7c,0xb4,0x69,0x11,0xc8,0x32,0x58,0xb4,0x85,0xd6,0xef,0x7f,0x91,0xeb,0x62,
++            0x19,0xc5,0xa1,0x1d,0x3e,0xad,0xc4,0xfc,0x0f,0x4b,0x9e,0xa9,0xde,0x59,0xc6,0x6e,
++            0xe7,0x3d,0x28,0x3c,0xbd,0xaa,0xdb,0x4e,0xc3,0x61,0x8a,0x9e,0xf3,0x5d,0x14,0x5c,
++            0xee,0x0e,0x62,0xab,0x7c,0xdc,0xe5,0xe8,0x4f,0x8c,0x01,0x8e,0xf2,0x1c,0x75,0x29,
++            0xee,0x88,0x6b,0x83,0x3d,0xa8,0x2b,0xf9,0x86,0x63,0x33,0x4f,0xdc,0xe3,0x0e,0xa8,
++            0x03,0xce,0x93,0xdd,0xbe,0x5e,0x45,0xd3,0x42,0xad,0x3b,0x5f,0xdd,0xe2,0xe2,0x73,
++            0x5c,0x30,0xb7,0x02,0x37,0xcb,0x24,0xd5,0x68,0x9d,0x53,0x59,0x95,0x76,0xff,0x16,
++            0x7c,0x24,0xe4,0xbb,0xb5,0x71,0x84,0x4d,0xea,0x57,0x10,0xd0,0xab,0x2c,0x7c,0x1c,
++            0x01,0x99,0xb5,0x06,0xfc,0x39,0x37,0x45,0xd7,0x47,0xb5,0x59,0xc7,0x79,0x95,0xd4,
++            0x67,0x11,0xf4,0x9c,0x50,0xc2,0xbd,0xf3,0xa5,0x2e,0xa7,0xb5,0x1e,0xfc,0xd7,0x20,
++            0x02,0xda,0x64,0x24,0xb4,0xfc,0xf3,0x00,0xe4,0xd7,0xcc,0x1c,0x70,0xf5,0x35,0xdd,
++            0xc0,0xd4,0x8c,0x92,0x0c,0xba,0x76,0xe7,0xc4,0xd3,0xf4,0xe6,0x48,0xd5,0x71,0x05,
++            0xca,0x1b,0x3c,0x37,0xbe,0xb9,0xc4,0x81,0xa5,0xd9,0xb8,0x85,0x79,0x60,0xd6,0x35,
++            0xb7,0x6a,0x8d,0x93,0xc8,0x3a,0x2d,0x62,0x84,0xf7,0xdd,0xf3,0xc8,0xf7,0x2e,0x3b,
++            0xa9,0x1b,0xb4,0x4e,0x3a,0xb2,0x3c,0xa8,0xcb,0x99,0xf7,0xc8,0x1d,0xfc,0x70,0xa3,
++            0x69,0x14,0xbc,0x9f,0xc6,0x34,0x40,0xef,0x5e,0x0b,0x62,0xd8,0x8a,0xe9,0x1d,0x6d,
++            0x2c,0x6b,0x32,0xf1,0x1f,0x87,0x6e,0xa0,0x09,0x65,0xd1,0x4d,0xd8,0xe1,0x51,0xa3,
++            0xce,0xc9,0x7b,0x65,0x54,0x71,0x87,0x41,0x14,0xb7,0x07,0x40,0x70,0x56,0x9e,0x22,
++            0x88,0x41,0x9e,0x4c,0x3b,0x67,0x0e,0x68,0x4c,0xbe,0x4d,0x3e,0x76,0x85,0xfe,0xa8,
++            0x47,0x96,0xce,0xbc,0x7c,0x43,0x2e,0xe2,0x0c,0xbd,0xb3,0x84,0xdc,0x0d,0x9f,0xc3,
++            0x53,0xd1,0xe5,0x2d,0x3c,0xf6,0x2d,0xfe,0x4d,0xd8,0xef,0xfe,0xf8,0xff,0x11,0x3b,
++            0xcc,0xbf,0x97,0x5d,0xd1,0xdc,0x07,0x79,0xea,0x25,0xf8,0x21,0x60,0xbe,0x3a,0xe8,
++            0x52,0x4f,0xf3,0x42,0x16,0x1b,0xc9,0x96,0x7b,0xf2,0xe8,0xa6,0x51,0xe7,0xfe,0x7c,
++            0xa0,0x6d,0x29,0x82,0x12,0x61,0x1f,0x89,0xa0,0xee,0x34,0xab,0xae,0xfc,0x51,0x18,
++            0xd0,0x04,0xa0,0x72,0x1d,0x39,0xd1,0xa1,0x30,0x41,0xa9,0xdf,0x7c,0x6f,0x6b,0x80,
++            0x80,0x63,0x9d,0xb7,0xb3,0x13,0x8e,0xd9,0x83,0x0e,0x7a,0xcb,0x2c,0x78,0x11,0x33,
++            0x2c,0x85,0xb8,0x02,0x72,0x66,0xfc,0x13,0x28,0xe2,0xae,0xc5,0xb9,0x27,0x98,0xaa,
++            0x68,0x0d,0xd8,0x61,0x1c,0x26,0x8a,0xb0,0x07,0xce,0x82,0x26,0x6b,0x27,0xc1,0xba,
++            0x63,0xa5,0x12,0xe3,0x93,0x6c,0x87,0x12,0xa0,0xe0,0xaf,0xc0,0x33,0x59,0x49,0x42,
++            0xf7,0x2f,0x5b,0x71,0xa0,0xf3,0xa6,0x82,0xa1,0xe8,0xc9,0x3c,0x72,0x6e,0x58,0x09,
++            0xaf,0x0b,0xc6,0x88,0x18,0xea,0xed,0x5b,0x34,0x24,0x12,0x72,0xd5,0x0a,0x18,0xe3,
++            0xf6,0x65,0xda,0x15,0xba,0x32,0x52,0x9d,0xb6,0x25,0x65,0xbe,0x58,0xee,0x45,0xd5,
++            0x61,0xa3,0xda,0x9c,0x3d,0x2c,0xf4,0xe9,0xd5,0x08,0x38,0xa8,0x4b,0x55,0xcf,0x28,
++            0x28,0xaa,0x49,0x7b,0x1b,0x28,0x79,0xa8,0xca,0x8b,0x20,0xdf,0x75,0x96,0xf7,0xe9,
++            0xbe,0x0f,0x78,0xbd,0xb9,0x4c,0x04,0x56,0x28,0xb9,0x85,0xe8,0x7a,0xdb,0x8a,0x85,
++            0x78,0xa0,0x26,0x33,0xc5,0xa6,0xf2,0x5d,0xce,0x7c,0x22,0x55,0x5d,0x6c,0xf4,0xec,
++            0x7e,0x4d,0xf1,0x0a,0x94,0xd1,0x05,0x4d,0x4f,0x6f,0xeb,0x8d,0xb4,0xe5,0xd8,0xdd,
++            0xfd,0x95,0xeb,0xb7,0xae,0x39,0xb3,0x49,0x49,0x4b,0x9b,0x1f,0xf8,0xbe,0x97,0x50,
++            0x28,0xef,0x48,0xe6,0x71,0x10,0xb0,0xdf,0xc3,0xf0,0xaa,0x70,0x32,0xdf,0x47,0xa1,
++            0x5d,0x53,0xb4,0xc4,0x33,0x3e,0x62,0x8d,0x52,0xd3,0xe2,0x89,0x98,0xbb,0xba,0x91,
++            0x1f,0x99,0xfd,0x07,0xb9,0x56,0x82,0xa3,0x25,0xdf,0x06,0xd6,0xbb,0xf0,0x45,0x74,
++            0x1c,0x1c,0xed,0xd5,0xbf,0x3e,0xa5,0x4e,0x08,0xa2,0xc3,0x57,0xf5,0xf6,0x3c,0x68,
++            0xc9,0x27,0x83,0x40,0x44,0x80,0xd0,0x64,0x37,0x5e,0x6b,0x77,0x5c,0xa9,0x8c,0x6c,
++            0xd1,0xee,0x77,0x14,0x3d,0x59,0x58,0x83,0x1e,0xd3,0x7f,0x50,0xaf,0x16,0x1e,0xfa,
++            0xd9,0xce,0x9f,0xc7,0xb4,0x85,0xb9,0x92,0xc1,0xd0,0xb3,0x41,0xf1,0xb6,0x27,0x2d,
++            0x7d,0x55,0xf3,0xa8,0x71,0x17,0x5d,0x31,0xe7,0x7e,0xf8,0xc8,0xeb,0x40,0x38,0xb5,
++            0x40,0xb1,0x8c,0x88,0x9b,0x35,0xba,0x37,0x6b,0x88,0x03,0x57,0x91,0x77,0xd2,0xf7,
++            0x8a,0xec,0x84,0xbc,0x9a,0x34,0x56,0x7d,0x82,0x3d,0xb8,0x68,0xda,0xfc,0x15,0x51,
++            0xae,0x10,0x8d,0x9d,0x1b,0x37,0xd7,0x69,0xc6,0x18,0x46,0x57,0x11,0x8b,0x9c,0xa7,
++            0xd1,0xae,0x85,0xdd,0x1a,0x3d,0xa0,0x5b,0xa1,0xaa,0xb9,0x5f,0xf8,0xd4,0x13,0xc8,
++            0xfe,0x9f,0xce,0xd4,0x3c,0xef,0x9d,0x2e,0x42,0x47,0x51,0x5a,0x93,0x5f,0x9c,0xcb,
++            0x41,0xfe,0xee,0xcc,0x08,0x49,0x07,0xbb,0xce,0x02,0x8e,0x0e,0x5a,0xb4,0xe0,0x78,
++            0x62,0x9d,0x5b,0x49,0xcc,0x9a,0xf4,0x9f,0x15,0xe1,0xad,0x0d,0xf6,0xd3,0x8f,0x65,
++            0x59,0xbe,0x15,0xdc,0x36,0x92,0x5e,0x9f,0x54,0xe9,0x33,0x8e,0xd1,0xf9,0x18,0x32,
++            0x9e,0x2f,0x27,0xe4,0x93,0xa0,0x8f,0xa6,0x47,0xaa,0xc8,0xa4,0x55,0x07,0x56,0x15,
++            0x03,0x83,0xec,0xf0,0x97,0xe9,0xec,0xcd,0xc8,0x47,0xc7,0xc9,0x53,0xa8,0x81,0x71,
++            0xe6,0xd3,0x09,0x03,0x75,0xb9,0x11,0xaa,0xc2,0xc8,0xeb,0x26,0x77,0x6f,0xa7,0x0c,
++            0xf1,0x57,0x63,0xe7,0x99,0xac,0xac,0xf3,0x87,0x3e,0xaf,0x71,0x93,0xa2,0x76,0xe3,
++            0xed,0xa7,0xe8,0x42,0x96,0x67,0x7a,0x00,0x05,0x33,0xdf,0x0d,0x8f,0x11,0x38,0xd6,
++            0x71,0xdf,0x8a,0x52,0x14,0xe6,0x64,0x0a,0x41,0x9f,0x54,0x09,0x9d,0xc6,0xda,0xf2,
++            0xa4,0x29,0xb8,0x48,0x73,0xca,0x09,0x43,0x92,0x86,0xe2,0xe3,0x9d,0xd5,0x7f,0xf6,
++            0x6c,0xe4,0x33,0x53,0x17,0x76,0x99,0xf7,0x8e,0xe7,0x42,0xe4,0xf5,0xed,0x35,0x11,
++            0x7c,0x1c,0xc2,0x4a,0x0b,0xa7,0x28,0x2f,0xb3,0x1d,0x8c,0x5e,0x7f,0x88,0x14,0x27,
++            0x80,0x2f,0x75,0xfc,0xb1,0x22,0xee,0x06,0xa6,0x8d,0x27,0x0d,0xd8,0xa9,0xb6,0x79,
++            0x67,0x7b,0xc3,0x4b,0xbd,0x21,0x67,0x3a,0xe6,0x41,0x73,0x47,0x11,0xa8,0x35,0xdb,
++            0xe7,0x26,0x54,0xfd,0x1f,0xe3,0x01,0x8b,0x2b,0x64,0x2b,0xbb,0xab,0x9e,0xd9,0xfb,
++            0x28,0x23,0xbb,0x50,0xfb,0x53,0x2b,0x71,0xab,0xa0,0x70,0x70,0x7c,0x18,0x40,0x29,
++            0x7b,0x29,0x57,0xc5,0x7c,0xa9,0x2a,0x4b,0x57,0xcc,0xc7,0x25,0xa3,0x5c,0xb3,0xda,
++            0xf6,0x8a,0x4f,0xca,0x65,0xc2,0x11,0x6e,0xcd,0x5e,0xa7,0x64,0xaa,0x52,0xfc,0xb9,
++            0x6f,0x2b,0x92,0x33,0x0d,0xa5,0xed,0x6f,0xef,0x0f,0x3b,0xae,0xe5,0x83,0x37,0xb8,
++            0x18,0x8b,0x2c,0x85,0x95,0x38,0x14,0xc8,0x40,0xd1,0xb8,0xf9,0xc9,0x0c,0x8b,0xae,
++            0xf1,0x20,0x8c,0xf4,0x74,0xb5,0x65,0x87,0xc0,0xd8,0xd6,0x5a,0xab,0xb3,0x21,0x07,
++            0xa6,0xa2,0xa1,0x65,0x36,0xfa,0xb5,0xa7,0xcc,0x45,0x1e,0xc9,0x21,0x89,0x0a,0xab,
++            0x75,0xe2,0xd5,0x7f,0xb3,0xfe,0xbd,0x92,0x17,0xd0,0x72,0x4f,0x9e,0xf0,0x5c,0x3d,
++            0x93,0xd6,0x7b,0x54,0x3e,0xbc,0x2e,0xe0,0xd5,0x89,0xe4,0x95,0x54,0x72,0x33,0x8e,
++            0xaa,0x38,0xf4,0xd2,0xb0,0xd4,0xbd,0x8d,0xea,0xb7,0x28,0x64,0x57,0x58,0xb6,0x48,
++            0xd5,0x23,0xe3,0x2f,0x2a,0x7b,0x6f,0xe1,0x74,0xdc,0xf1,0x27,0xe9,0x5b,0x38,0x5c,
++            0x18,0x3a,0x7d,0xc8,0x8b,0xf5,0x82,0x34,0x5a,0x21,0x2d,0x65,0xff,0xfd,0x20,0xb7,
++            0xac,0x14,0xbc,0x8f,0x1f,0x8b,0xf6,0x2b,0xee,0x24,0x51,0x5f,0x56,0x76,0x7a,0x64,
++            0x52,0x08,0x55,0xb9,0x9c,0x46,0xba,0x7d,0xed,0xf9,0x6a,0x6c,0xb5,0x08,0x1d,0x78,
++            0x8e,0x35,0xc7,0xcf,0x3d,0xb7,0x4f,0xc9,0x0e,0xba,0xe9,0x0b,0x22,0x51,0x70,0x64,
++            0x92,0xbb,0xcf,0xdf,0x53,0x36,0x93,0xfb,0xe9,0xfa,0xa8,0xcc,0x85,0xf2,0x37,0x44,
++            0x99,0xde,0x2d,0xe5,0xbc,0x4a,0xcf,0x9a,0xee,0xca,0xba,0x1f,0xdd,0xbc,0x38,0x29,
++            0x45,0x40,0x5a,0xbc,0xd4,0x0c,0x5e,0xef,0xed,0xd9,0xfa,0x7a,0x5f,0x5c,0x32,0xcb,
++            0x53,0x3f,0x8d,0xad,0x55,0x2f,0x7f,0xfb,0x69,0xef,0xc9,0xd6,0x7c,0xfb,0x39,0x6b,
++            0x44,0x1c,0xb5,0x20,0x54,0xbc,0x75,0x99,0xae,0xd7,0xe9,0x5e,0x00,0x52,0x50,0xbc,
++            0xf7,0xab,0x10,0x76,0xfb,0x91,0xe8,0x23,0xf3,0x02,0xae,0x84,0xf7,0xcd,0xc8,0x30,
++            0x7b,0x0c,0x70,0x1c,0xb6,0xfa,0x70,0xc3,0xcd,0x4c,0x0b,0x46,0x3b,0xd0,0x79,0x05,
++            0x69,0x93,0xff,0x39,0xa3,0x0e,0x9b,0x3e,0xc6,0x8a,0x82,0x14,0xa4,0xcd,0x72,0x36,
++            0x20,0xa2,0xec,0xe8,0x13,0x58,0x67,0x19,0x6d,0x4e,0xe7,0x0c,0x99,0x12,0x1a,0xf2,
++            0x7a,0xab,0xf8,0xbe,0xbe,0x29,0x22,0x44,0xfb,0xef,0x6f,0x34,0x73,0x2b,0x36,0x57,
++            0xa2,0x5a,0x73,0xb6,0xbf,0xd8,0x4f,0x83,0xc7,0xc8,0xb8,0xc2,0xc4,0x27,0xe1,0x33,
++            0xe0,0x61,0xbe,0x61,0x79,0x42,0x29,0x75,0x22,0xc7,0xb1,0x67,0x44,0x6b,0x72,0x61,
++            0x8f,0xf8,0xb1,0x71,0x78,0x43,0x0b,0xc2,0xe7,0x7a,0xd6,0xbc,0x51,0x63,0xd6,0xf3,
++            0xe1,0x4b,0x8a,0xe2,0xe3,0x6a,0x6c,0x01,0x90,0x0c,0xb2,0x1f,0x2f,0x5e,0xed,0x62,
++            0xdf,0x01,0xd5,0xde,0x2a,0xa5,0xae,0x5a,0xaa,0x42,0xc1,0x3c,0x5f,0x80,0x50,0xf3,
++            0x07,0xb7,0x9e,0xc1,0xeb,0x1c,0x30,0x2e,0x69,0x15,0x4c,0xaf,0x20,0xc0,0x0c,0x0a,
++            0xf1,0x18,0x33,0xee,0x98,0x3b,0x9b,0x57,0x2a,0x40,0x93,0x22,0xbb,0xbf,0x7f,0x8f,
++            0xd4,0x04,0x6e,0x3f,0x9e,0x9a,0x44,0x0a,0x2a,0xdf,0x37,0x0e,0xd8,0xab,0xb1,0x22,
++            0x84,0xdb,0xb4,0x5b,0xba,0x82,0xae,0x8b,0xc7,0x40,0xe0,0x83,0xa6,0xf6,0x46,0x27,
++            0xea,0x6e,0xfd,0x4a,0x48,0x6f,0x2d,0x6f,0x2b,0xcd,0xb8,0xe9,0x83,0x54,0x03,0x45,
++            0x32,0x8e,0x5e,0x7a,0x3a,0x80,0xa0,0x5e,0x6a,0xb0,0xdb,0x90,0xd3,0xee,0x00,0x62,
++            0x04,0x9d,0x92,0xe6,0xcf,0x9d,0x4e,0x71,0x58,0x4f,0x29,0x44,0x5c,0xdb,0x3b,0x96,
++            0xd2,0x53,0xb2,0xac,0x8e,0x6a,0x09,0x5a,0x98,0x1e,0x8c,0x90,0x42,0x91,0x78,0x05,
++            0xe5,0xb9,0x92,0x01,0xc6,0x04,0xad,0x5a,0x83,0x26,0xed,0xa1,0x0d,0x30,0x87,0x97,
++            0x5d,0x57,0x8d,0x6c,0x41,0xa8,0x47,0x2d,0xd9,0x11,0x36,0xf2,0xff,0xaf,0xe8,0x45,
++            0xb1,0x8b,0x14,0xb6,0x01,0x31,0xf0,0xc4,0x28,0xb5,0xc4,0x41,0x32,0xf9,0x5c,0xa6,
++            0x67,0xe9,0xac,0xd6,0x66,0x38,0x02,0x12,0x67,0xf8,0x92,0x87,0x38,0xd1,0xba,0x61,
++            0xd2,0xe6,0x3d,0x41,0x91,0xb4,0x72,0xe7,0x32,0x32,0x8c,0x6a,0x55,0xd4,0x47,0x91,
++            0x7e,0x13,0x09,0x53,0xd9,0x36,0xcb,0xf5,0xe1,0x52,0x17,0x17,0x13,0xf6,0x78,0xa4,
++            0xf4,0x69,0xb3,0x08,0x02,0x38,0x9c,0x76,0x89,0x57,0x52,0x66,0xc3,0x47,0xb6,0x78,
++            0x19,0xad,0xdc,0xe2,0x9a,0x5c,0xa5,0x5a,0xc5,0xa4,0x8e,0xba,0xd8,0xe6,0x5d,0x58,
++            0x90,0x05,0xb9,0xa0,0xbe,0xe9,0x2a,0x2d,0xad,0x6f,0xcd,0x45,0x80,0x38,0xaf,0x83,
++            0x25,0x16,0x30,0x7f,0x50,0xaa,0x67,0xd2,0xef,0x93,0xc5,0x8e,0x81,0xd4,0xc7,0x97,
++            0x6b,0x9c,0x90,0xc8,0x93,0x82,0x6b,0xd9,0xcb,0xdd,0xc7,0x1f,0xfe,0xf7,0x04,0x67,
++            0xf6,0xc1,0x97,0x47,0x9c,0x58,0x0c,0x5f,0x4f,0xd6,0x7e,0x0f,0x46,0x89,0xe8,0xcb,
++            0xea,0xe2,0xa7,0xcf,0x28,0x33,0x9e,0x1a,0x6e,0xd3,0xe2,0x5c,0x59,0x8b,0xf2,0x87,
++            0x56,0x03,0xf7,0x35,0x2d,0x70,0x9c,0xd5,0x00,0x1b,0xc4,0xd9,0x06,0xa7,0x95,0x3e,
++            0xfc,0xa3,0x18,0xf5,0x1d,0xdb,0x3d,0xd3,0x28,0xa0,0x64,0x3d,0x72,0x74,0x08,0x1f,
++            0xcd,0x10,0xc2,0xea,0xcb,0xe3,0x40,0x15,0xb8,0xce,0xf1,0xb2,0x23,0x94,0x12,0xa3,
++            0x78,0x13,0xcb,0xeb,0x4a,0x59,0xf1,0x77,0x41,0x1f,0xe5,0x19,0x9b,0x17,0x78,0x3c,
++            0xf9,0x36,0x66,0xef,0x7c,0x69,0x1f,0x1e,0x41,0x67,0x83,0xdc,0x66,0x16,0xe4,0xbc,
++            0xf7,0xea,0xf3,0x62,0xb7,0x3b,0xe0,0x71,0x3a,0x80,0x14,0x8d,0xa7,0x67,0x84,0xcd,
++            0x06,0x05,0xd3,0xea,0xe0,0xe4,0xc1,0x43,0xe6,0x44,0x49,0x8d,0x14,0x05,0x82,0x03,
++            0x9e,0xdb,0x55,0x25,0xea,0x59,0x57,0x5f,0x4a,0x87,0xd1,0x89,0xd0,0x56,0x81,0x6b,
++            0x07,0xc7,0x32,0x57,0xe8,0x37,0x6e,0x80,0x43,0x4a,0xe1,0x63,0x2e,0x68,0xf6,0x30,
++            0x2a,0x7d,0xb0,0xf0,0xf7,0x39,0xa3,0x2d,0x4a,0x00,0xe0,0x10,0x72,0xaa,0x70,0xfc,
++            0x65,0xf8,0x3f,0x59,0xd7,0x03,0x8e,0x49,0x75,0xc6,0x01,0xd8,0x4d,0x14,0x34,0x8f,
++            0xc3,0xc0,0x99,0xfc,0xa0,0x07,0x1a,0x58,0xfc,0xc5,0x34,0x5b,0xef,0x5d,0xeb,0x3b,
++            0x8f,0x00,0xe3,0xcf,0x74,0x7a,0x05,0x0e,0xee,0x46,0x43,0x1b,0x01,0x5a,0xca,0x72,
++            0x6d,0xe0,0xbd,0x4e,0x21,0x73,0x20,0xdd,0xa5,0xa8,0xea,0x6a,0xd9,0x8f,0x52,0xa5,
++            0x9e,0xf0,0x2a,0xde,0xef,0xe1,0x68,0x37,0xa4,0x89,0xf5,0x65,0xa6,0xe2,0x74,0xcf,
++            0xae,0x65,0x3a,0xf1,0xa5,0x2b,0xe3,0x05,0xa6,0xc3,0xa9,0xe3,0xa2,0xac,0x42,0x53,
++            0x0f,0xcf,0xb9,0x19,0xb1,0xe3,0x41,0xcb,0x21,0x60,0x7c,0xc0,0x9f,0xb1,0xdf,0xa5,
++            0x85,0x1f,0xdb,0x7e,0x34,0xcb,0xc6,0xd1,0x54,0xdf,0x14,0xd4,0x16,0x97,0x74,0x96,
++            0xad,0x8e,0x73,0xac,0x42,0x84,0x1c,0xae,0x63,0xe9,0x7c,0x97,0x5a,0xb3,0x7d,0x87,
++            0x51,0x1d,0x32,0x76,0xc6,0x11,0x81,0xd0,0xdc,0xdd,0x95,0x83,0x1d,0x43,0x73,0xa6,
++            0xa9,0xd1,0x6d,0xf2,0x1d,0xdf,0x76,0x88,0xd9,0x46,0xad,0x86,0xc6,0x13,0xdf,0x88,
++            0x36,0x90,0x84,0xc4,0xf8,0xb9,0x4e,0x52,0x88,0x7b,0xac,0xf7,0x2a,0x03,0x17,0x2d,
++            0x44,0xf9,0xd4,0x84,0x74,0x45,0xdd,0xf5,0xcb,0xb0,0xf7,0x16,0x3f,0x45,0xe5,0x84,
++            0x88,0x88,0xaf,0xda,0xa6,0xf9,0xd1,0xc7,0x7a,0x92,0xf5,0xe6,0xa2,0x4b,0x7a,0x57,
++            0x87,0x7c,0xb3,0x35,0xa3,0x32,0x45,0x0d,0x4b,0xda,0x8a,0xf7,0xff,0x67,0xac,0xcc,
++            0x4f,0x67,0xff,0xc8,0x99,0x1e,0xa7,0x95,0x54,0x0d,0x1d,0xe9,0x72,0x24,0xb8,0x7a,
++            0xce,0x12,0xf9,0xe4,0x3e,0x59,0x3b,0xd1,0x0c,0x29,0xe4,0xa9,0x05,0xbb,0x5f,0xac,
++            0x0f,0x37,0xf7,0xfc,0xc0,0xf8,0x26,0x2f,0xf5,0x40,0x73,0x65,0x47,0xc5,0x8a,0xb2,
++            0x1e,0x16,0x91,0xa2,0x1a,0xab,0x27,0xbf,0x65,0x73,0xaf,0xa4,0x5c,0x64,0xd9,0x28,
++            0x8a,0x0d,0xbf,0x51,0x99,0xba,0xe6,0x1a,0x25,0x8d,0x36,0xf7,0xb5,0x92,0xec,0xe8,
++            0x4f,0xf3,0xda,0x38,0x9a,0x42,0x30,0xd6,0xdc,0x90,0x9c,0xfe,0x7e,0x9d,0xf7,0xa0,
++            0xc5,0x91,0xc7,0x55,0x1f,0xa5,0x0e,0x94,0x49,0x55,0x48,0x7d,0x01,0x23,0x11,0xdd,
++            0x4e,0x1c,0xa5,0x3d,0x9c,0x3f,0x80,0xdf,0x43,0xba,0x20,0x00,0xdb,0xbe,0xa7,0x38,
++            0xd8,0xb1,0xbf,0x5b,0xc5,0xbd,0x68,0xa4,0x4b,0x23,0xd8,0xbd,0x56,0xa8,0x44,0x9d,
++            0xa0,0xae,0x46,0x90,0x3c,0xa0,0x31,0x46,0xb6,0xbc,0xa0,0xcb,0xdc,0xc7,0x5b,0x1d,
++            0xfc,0x40,0x2a,0x2a,0x83,0x77,0x29,0xde,0x51,0x3f,0xa5,0x47,0x27,0x07,0x5d,0xe0,
++            0xfd,0xf3,0x99,0x08,0x9d,0x61,0xb5,0xaf,0xc2,0xe3,0x8e,0x4b,0x1b,0xf2,0xca,0x63,
++            0xf7,0x0b,0x68,0x49,0x97,0x24,0x28,0x1d,0x61,0x55,0xc0,0x91,0xb3,0x6b,0xef,0x78,
++            0x60,0x4a,0x37,0xb6,0x91,0xa2,0x66,0x58,0x45,0x44,0x92,0x96,0x72,0x8f,0xf5,0x3e,
++            0x21,0x47,0xa1,0xf7,0xa3,0xad,0x91,0x41,0x94,0xb9,0xcd,0x02,0x3b,0x77,0xde,0xd5,
++            0xa3,0x05,0xd0,0x37,0x71,0xd8,0x3f,0xf5,0xe3,0x6d,0x6e,0x40,0xd5,0xbd,0x62,0xbe,
++            0xcc,0x05,0x99,0x4c,0x6f,0x1d,0xb8,0x57,0x8d,0x1c,0xda,0x31,0x5e,0xa0,0x88,0x9a,
++            0xe3,0x7d,0x3b,0xc9,0xf8,0x96,0x1e,0x11,0x4f,0x63,0x36,0x43,0x83,0xb4,0x41,0x78,
++            0xf8,0x01,0x5c,0x25,0x24,0x30,0x43,0x38,0xbc,0x1a,0xa7,0xa9,0x9d,0xb5,0x33,0xea,
++            0xf5,0x67,0x4b,0x74,0x8e,0x69,0xc8,0x5b,0x36,0x57,0xf8,0xfd,0xdd,0x6f,0x7a,0xbb,
++            0x32,0x4e,0x43,0xc8,0x7c,0x69,0x92,0x48,0x22,0xb3,0xe7,0x23,0xa7,0x10,0xe7,0x2a,
++            0xbc,0x50,0xb2,0x5e,0xe6,0x2b,0x2e,0xfc,0x6b,0x48,0xca,0xdd,0x38,0x92,0x88,0x62,
++            0x17,0xf3,0xa3,0xff,0xab,0xd3,0x6d,0x41,0xcc,0x4f,0x89,0xf0,0xe6,0x2c,0xe7,0xca,
++            0xb3,0x05,0xb9,0x35,0x3a,0x29,0x01,0x90,0xf7,0x0d,0xa3,0x8d,0x78,0xce,0xbd,0xc7,
++            0xfa,0x18,0xdd,0x70,0xd7,0x72,0xcf,0xa3,0x1f,0x5c,0x45,0x5a,0x8d,0x01,0x55,0xbc,
++            0x84,0xe0,0xaa,0x10,0x70,0x59,0x3a,0x65,0x60,0xf5,0xe2,0x14,0x77,0xb9,0x80,0xa1,
++            0xe2,0x02,0x07,0xe8,0xb6,0x38,0xcc,0x97,0xdf,0x43,0xeb,0x04,0x05,0x21,0xf2,0xe3,
++            0xd7,0xcc,0x4d,0xb0,0xbf,0x71,0x54,0xf0,0x9a,0x5f,0xa9,0xd7,0x02,0x16,0x64,0x0b,
++            0xc3,0x4b,0x7c,0x83,0xf0,0x64,0x6c,0x30,0x99,0x5b,0x14,0xc4,0x1a,0x8b,0x04,0xa1,
++            0x40,0x9b,0xae,0x50,0x10,0x9a,0x56,0xf4,0xc0,0xae,0xa8,0x70,0x53,0xb8,0xfc,0x86,
++            0x68,0x27,0xcd,0x23,0xb4,0x1d,0x35,0xa0,0x1b,0x5b,0xeb,0xd0,0xf4,0x77,0xdc,0x55,
++            0x83,0x15,0x0d,0x34,0x41,0x75,0x8d,0x75,0x9e,0xd1,0xd5,0xed,0x88,0x57,0x2d,0xf7,
++            0xf9,0xc5,0x9c,0x1a,0x3e,0x71,0x4d,0xbf,0x6e,0xa2,0xae,0x57,0x7e,0x81,0xb7,0xdf,
++            0xf3,0x13,0x4e,0xe4,0x2f,0x78,0xde,0xc4,0x77,0x1b,0x33,0xc3,0xe4,0xec,0x1f,0x8d,
++            0xdb,0xe5,0xb9,0x09,0x93,0x2f,0x4c,0x09,0xb4,0x3a,0xdb,0xe3,0x0d,0x26,0xcb,0x71,
++            0x69,0xd6,0x2c,0xa5,0x65,0x8a,0xd3,0xc5,0x96,0x1b,0x8c,0x86,0x81,0x8e,0x7e,0x39,
++            0x89,0x5c,0xc6,0xd8,0x3c,0x2f,0x36,0xac,0x24,0x51,0x61,0xd9,0x7c,0xf5,0x5e,0xe9,
++            0xd4,0xb6,0xb0,0xe9,0x58,0xb4,0x66,0x70,0xe9,0x75,0xfe,0xf5,0x18,0x8f,0x27,0xeb,
++            0xa2,0x5c,0xc7,0xcf,0x13,0xb3,0xa8,0xae,0xe4,0x5d,0x90,0x05,0xcd,0xbe,0x37,0xdd,
++            0x16,0x5d,0xd9,0xe8,0x08,0x72,0xe4,0x9b,0xa8,0xe0,0x4a,0x79,0xdb,0x5c,0x1e,0xa3,
++            0x37,0x04,0xb2,0x95,0x96,0xa4,0x8d,0x68,0xa1,0x1f,0xbb,0x55,0x28,0x61,0xbb,0x61,
++            0x71,0xed,0x6c,0x93,0x56,0x53,0xf8,0xf3,0x33,0x1c,0xee,0x0a,0x53,0x29,0xc3,0xed,
++            0x65,0x2d,0x2a,0x65,0x6b,0xc0,0xdd,0xbc,0xc5,0x62,0xb3,0xd4,0x50,0x6f,0x4f,0x2e,
++            0x86,0xda,0xb9,0x75,0xd7,0xe1,0x41,0x0c,0xe7,0x82,0xdc,0xb3,0x90,0xc6,0x74,0xb2,
++            0xc5,0xd5,0xc4,0x0a,0xb5,0xa2,0x60,0xc3,0xe7,0x3b,0xe1,0x95,0x66,0x6e,0x97,0x3f,
++            0x26,0xe7,0xec,0xb4,0x11,0xfc,0x01,0x0d,0xe0,0x84,0xe8,0xea,0xa8,0x48,0xa1,0x63,
++            0x84,0x8b,0xc1,0x17,0x37,0x2e,0x2b,0x6c,0xae,0xd7,0x89,0x87,0xa4,0xa4,0x33,0xce,
++            0xfb,0xc5,0x5d,0xd3,0xc0,0xa8,0xf8,0x32,0x86,0x86,0x6f,0x86,0x74,0x27,0x1c,0x33,
++            0x64,0x59,0xa6,0xb8,0x2f,0xe3,0x22,0x2b,0x40,0x8a,0x72,0x7a,0xab,0x84,0xd1,0x3d,
++            0xac,0x76,0xa2,0x1b,0x3d,0x59,0xe5,0x3b,0x4b,0x20,0x17,0x41,0xc0,0xb6,0xe3,0xca,
++            0x94,0x87,0x19,0xc8,0x5e,0xaa,0x2b,0x23,0x49,0xea,0x54,0xd0,0x2d,0x3c,0x72,0x86,
++            0x28,0x34,0x68,0xf7,0xa2,0x66,0xe1,0xbf,0xac,0x91,0x84,0x12,0x22,0x76,0x72,0xeb,
++            0x6d,0x73,0x3d,0x4f,0x18,0xe5,0xad,0x6a,0x39,0x4c,0xc0,0x5e,0x95,0x43,0x7b,0xde,
++            0x2f,0x8f,0xfa,0x5e,0x03,0xef,0x72,0xdd,0x2c,0xed,0x3a,0x5e,0xba,0xe7,0x1b,0xbb,
++            0x29,0x2f,0xfd,0xcb,0xeb,0xdc,0xb3,0x17,0xbb,0xc8,0x53,0x1d,0xbc,0x69,0x53,0xcb,
++            0x2c,0xdf,0xb3,0x13,0xac,0xbd,0x03,0xf9,0xc6,0x12,0xbf,0xfb,0xff,0xc5,0x07,0x60,
++            0xc4,0x6f,0x87,0xba,0xec,0x41,0xf4,0xd7,0x03,0x92,0xe0,0x98,0x56,0xb2,0x77,0x92,
++            0x23,0x21,0x57,0xb1,0x94,0x4e,0x8d,0x36,0x46,0xe6,0x5b,0xd8,0xa3,0xf9,0x96,0x61,
++            0x5c,0xb1,0x65,0xd3,0x1c,0xbf,0xf4,0x7e,0xe2,0x2b,0x2a,0x66,0x79,0x8f,0x43,0xc9,
++            0x58,0x0f,0x41,0x04,0xcd,0x6e,0xe6,0x85,0x9a,0xc2,0x7c,0x33,0xb0,0xd6,0x74,0x7b,
++            0x87,0x0b,0x9a,0xee,0x75,0x44,0x0c,0x60,0x6f,0x69,0xca,0xd3,0xd5,0x7f,0x73,0x89,
++            0xaa,0x68,0xd2,0xfe,0x74,0x45,0xa3,0x56,0x61,0x2c,0xc2,0xde,0xd0,0x55,0xd1,0xa1,
++            0x5d,0xd4,0xfd,0xe7,0xfc,0xa7,0x4d,0xb3,0xe2,0xd9,0xef,0xd6,0x9a,0xe9,0x0f,0xfb,
++            0x52,0x11,0xf5,0xc7,0x56,0x08,0x1f,0x77,0xcc,0x51,0x6b,0x84,0x9b,0x9b,0x20,0x2b,
++            0x2a,0xb2,0xc0,0xb6,0x3d,0x68,0x6d,0x91,0x17,0x00,0x76,0xfa,0xc9,0x59,0xc2,0x05,
++            0x2c,0x39,0x6e,0xca,0xca,0xd7,0xfe,0xdf,0xb2,0x42,0x6d,0xf9,0x73,0x26,0xf3,0xe9,
++            0x53,0x07,0x80,0x89,0x6c,0xde,0x82,0x63,0x58,0x30,0xa0,0x50,0x15,0x6b,0xef,0x5a,
++            0x83,0x06,0x10,0x04,0x48,0x2d,0x8d,0x42,0xdd,0x27,0x00,0x3a,0x02,0xb9,0x66,0x0a,
++            0x14,0x17,0xfa,0x0c,0x5d,0x30,0x56,0x34,0xec,0xf4,0x94,0xf3,0x7d,0xbc,0xd6,0x0a,
++            0x8c,0x62,0xe3,0xac,0x9c,0x36,0x06,0x78,0xef,0x55,0x19,0x03,0xbc,0xbf,0x7d,0xfa,
++            0x9e,0x81,0xf1,0xfa,0xb8,0xbf,0x48,0x89,0xad,0x61,0xeb,0x23,0xda,0x25,0x36,0x1f,
++            0x0a,0x1e,0x43,0xee,0xd3,0xfd,0x47,0xab,0xeb,0xd0,0x64,0xcd,0x88,0x09,0xdf,0xd2,
++            0x06,0x28,0x16,0x80,0x30,0x22,0xef,0x07,0xe1,0xbc,0x2f,0x15,0xf1,0xe1,0xf0,0x18,
++            0xfc,0x4e,0x80,0x05,0xed,0xc0,0xd8,0xe8,0x6f,0x4b,0xca,0x82,0xba,0x05,0x76,0xe9,
++            0x62,0xdf,0xb9,0xc2,0x52,0x02,0xe9,0x29,0x3d,0x0d,0x7a,0xd6,0x54,0xef,0x69,0xa6,
++            0x62,0x0e,0x49,0x21,0xc5,0xa8,0x9b,0xd9,0x19,0x88,0x09,0xc6,0x55,0xee,0xd3,0x7f,
++            0x7a,0x46,0x55,0xa2,0xb7,0x4a,0xf0,0x13,0x7e,0x97,0x10,0xa5,0x23,0xe5,0x5e,0x6c,
++            0x05,0x04,0x60,0xe4,0x20,0xb3,0xe6,0xf5,0xf4,0x20,0x8a,0xfe,0x55,0x9d,0x96,0x6e,
++            0xe1,0x6b,0xa3,0x54,0x93,0x9c,0x2f,0x66,0x63,0x03,0x81,0x96,0x56,0xeb,0x09,0x23,
++            0x20,0x8c,0x71,0xbd,0x37,0x68,0x61,0xf4,0x7c,0xfa,0x61,0xf1,0xd8,0x87,0xae,0x9a,
++            0x0a,0x02,0x7a,0x3d,0x74,0x6a,0x90,0x6e,0x2a,0x09,0xc0,0x9b,0xb3,0x0c,0xbe,0x7a,
++            0xba,0x6c,0x0a,0x0d,0xe5,0xc8,0xe2,0x09,0x25,0x0b,0x39,0xcf,0xdd,0xe4,0x57,0x6b,
++            0xc8,0x05,0x93,0x8d,0x39,0xad,0x29,0xda,0xa4,0xc1,0x03,0x1c,0x79,0xeb,0x33,0xf2,
++            0x25,0x06,0x4b,0x58,0xe0,0x8b,0x0b,0xb9,0x68,0x25,0xc9,0x8b,0x32,0x0f,0x85,0x79,
++            0x7e,0x4e,0x02,0x15,0xd0,0xb1,0x44,0x0a,0xb5,0xd1,0xea,0x96,0xf6,0x61,0x32,0x67,
++            0x73,0x4f,0x5a,0x37,0x15,0x4f,0xff,0x9a,0x4d,0x9d,0x92,0x74,0x5d,0x47,0x53,0xe8,
++            0xe9,0xf1,0xbb,0x6a,0x63,0x21,0x93,0xd5,0xa2,0x13,0x7f,0xf2,0x2b,0xb8,0xd2,0xb6,
++            0x62,0xbe,0x81,0xe0,0x24,0x74,0x43,0x02,0x9a,0x44,0x5d,0x03,0x78,0x0a,0x64,0x37,
++            0xcb,0x50,0xfa,0x83,0x14,0x91,0x72,0xf9,0x63,0x63,0x04,0xbb,0x4c,0xc4,0x72,0xf2,
++            0xd2,0x74,0x2c,0xe6,0x53,0xf6,0x0c,0x11,0xc0,0xf8,0xa2,0xed,0x33,0x8e,0x45,0xe4,
++            0x22,0xf5,0xbd,0xb5,0x76,0x9d,0x4f,0x3c,0x9c,0x10,0x86,0xd7,0x1b,0xc3,0x35,0x6a,
++            0x0d,0x1e,0xf3,0x92,0x95,0x3e,0x8b,0x51,0xdd,0x11,0xa3,0x8c,0x7c,0x85,0xd1,0x44,
++            0x02,0x16,0x28,0x56,0x64,0x3c,0x0d,0xef,0x87,0x38,0x14,0x25,0x41,0x36,0xdf,0xf3,
++            0x8e,0xb5,0x60,0xab,0xe9,0xca,0xde,0xf2,0x61,0x17,0x63,0x6f,0x86,0xd3,0x7d,0x51,
++            0x01,0xb6,0xd5,0x83,0xd0,0x77,0x37,0xe4,0xe1,0x36,0x56,0x11,0x09,0x18,0x5a,0xf2,
++            0x32,0x56,0x76,0x4f,0x44,0x2c,0x8e,0x94,0x6e,0xfa,0xa5,0xb5,0xeb,0x35,0xfd,0xaf,
++            0x89,0xe7,0x79,0x64,0xe2,0x75,0x06,0x01,0xc9,0xc7,0xde,0x55,0x1b,0x8a,0x0b,0x1a,
++            0xc7,0x56,0x1e,0x67,0xf8,0xb3,0x8f,0x88,0xe8,0x26,0xca,0xde,0x10,0x08,0x5e,0x99,
++            0xae,0x18,0x7c,0xf2,0x35,0xec,0xa3,0xcb,0x13,0xf7,0x81,0x94,0xfe,0x7b,0xb4,0x7b,
++            0x1e,0x7e,0x08,0x8d,0x1a,0x86,0x25,0x08,0xd1,0x04,0xc7,0xc4,0x10,0xca,0x18,0xe5,
++            0xf4,0xb7,0x27,0xaa,0xb7,0x5e,0xc9,0x7a,0x62,0x56,0x9a,0x04,0x8f,0x88,0x70,0x38,
++            0x62,0xe4,0x94,0xde,0x88,0xe4,0x9e,0x44,0xa3,0x1d,0xd8,0xa9,0x92,0x95,0x54,0x1b,
++            0x2f,0xbf,0xb8,0x8a,0x47,0x88,0xd3,0x6d,0x9c,0x65,0xaf,0x69,0xae,0xab,0x17,0xd1,
++            0xad,0x45,0xae,0x1d,0xff,0xb2,0x89,0xca,0xd8,0xea,0x73,0x6f,0xa7,0x77,0xd9,0x25,
++            0xa5,0xff,0x36,0x75,0x78,0xcc,0x52,0x23,0x45,0xbb,0x20,0x55,0x25,0x51,0x5a,0x74,
++            0xf2,0x91,0x8c,0x81,0x31,0x0c,0x0d,0x2d,0x75,0x83,0xeb,0xc5,0xd9,0xec,0x18,0x41,
++            0x25,0x99,0xc3,0x1a,0x97,0xe2,0x86,0x16,0xc2,0x18,0xcf,0x21,0x3d,0x9b,0x91,0xec,
++            0x64,0x1c,0xb2,0x2f,0x7e,0xe7,0x29,0x9a,0x64,0x6c,0x29,0xdf,0x41,0xae,0x7e,0x7a,
++            0x27,0x44,0xe0,0x81,0xeb,0xd2,0xdf,0xe6,0x30,0x83,0x4f,0x84,0xbf,0xfc,0x30,0xd7,
++            0x64,0xa5,0x89,0x96,0x0b,0xd8,0xc2,0x8d,0x49,0x7a,0x86,0x70,0xb6,0x66,0x5f,0x7f,
++            0xef,0x17,0xbb,0x45,0x25,0x7f,0x79,0xd2,0xf5,0x12,0xe7,0x05,0xb6,0xec,0xb2,0x53,
++            0x37,0xf6,0xfe,0x39,0xe5,0xcb,0xd5,0x9b,0x42,0x8a,0x98,0xf3,0xdc,0x7e,0x5d,0xc8,
++            0xad,0x97,0x98,0xbf,0x21,0x07,0x27,0x0d,0xed,0x67,0x4d,0xc6,0xe0,0xa5,0xf9,0xe4,
++            0xf4,0xba,0x92,0x2e,0xcb,0x06,0xac,0xbe,0x14,0xe5,0x81,0x4e,0xdd,0xf6,0x9e,0x36,
++            0x73,0xd7,0x07,0x2b,0x29,0x0b,0xa2,0x10,0xfc,0x3f,0x24,0xc9,0xf8,0x5c,0x54,0x61,
++            0xbf,0x14,0x0b,0x6d,0xff,0x6c,0x01,0xc4,0x30,0xa7,0x02,0x4f,0x5d,0xfd,0x63,0x48,
++            0x46,0xe0,0xf8,0x4c,0xdc,0xa8,0x15,0x9a,0xce,0x8e,0xe0,0x8e,0xb5,0xa8,0x03,0xb1,
++            0x09,0x8c,0x52,0xb1,0x2c,0x58,0xba,0xc6,0x97,0x8f,0x75,0x18,0x60,0xcd,0xb7,0x15,
++            0xa0,0x52,0xab,0xcb,0xad,0xfa,0x24,0x15,0xcd,0xaf,0xc9,0xdf,0x4c,0xac,0x86,0xab,
++            0x28,0x2e,0x53,0x72,0x38,0xe2,0x2c,0x99,0xcc,0xbd,0x22,0xcc,0xe4,0x92,0x9b,0x60,
++            0x9b,0x96,0xee,0x9b,0x74,0xd5,0xd8,0xd9,0xfa,0x4d,0xb6,0x55,0x00,0x5d,0xb3,0x92,
++            0x25,0x91,0xba,0xf4,0xca,0x1c,0xfb,0x8f,0x63,0xd0,0xf4,0xd7,0x16,0x03,0xd3,0x70,
++            0xa2,0x90,0xdd,0xa3,0x5d,0xa8,0xd4,0xe3,0xea,0x59,0x26,0xe0,0x3e,0x4a,0x2d,0xe1,
++            0x27,0x74,0x63,0x32,0x42,0x4e,0x69,0x43,0x1a,0xdc,0xab,0x8b,0xf3,0xf2,0x84,0x46,
++            0x05,0x55,0xbd,0xf8,0x91,0xa4,0xcc,0x82,0x62,0xf9,0xd5,0xc2,0x9d,0x90,0xd4,0x2c,
++            0x37,0xd8,0x62,0xc5,0x7a,0xad,0x24,0x1f,0x54,0xbf,0x83,0x72,0x24,0x3b,0x49,0x0c,
++            0x95,0x1a,0x1d,0xe3,0x57,0x19,0x6b,0x0b,0xd1,0x1b,0xcd,0x1d,0x5a,0xfb,0x12,0x89,
++            0x52,0x0b,0xbd,0xc2,0xf3,0x3c,0xc5,0x13,0x80,0xcc,0x6d,0xc5,0x00,0x56,0x5c,0x68,
++            0xa3,0x83,0xb4,0xcc,0x18,0xc5,0x6c,0x4c,0x04,0x39,0xe2,0xcc,0x15,0x89,0x96,0x14,
++            0x2c,0x09,0xd5,0xe1,0x45,0x06,0x7c,0x58,0x31,0xdd,0x09,0x87,0x7b,0xd8,0x0f,0xed,
++            0x32,0x88,0xd8,0x2a,0x76,0xb7,0xf7,0x8b,0xee,0xd7,0xef,0x6e,0x04,0x2b,0x4f,0x2c,
++            0x0a,0x96,0x95,0x27,0x4e,0xfa,0x13,0x4b,0x4a,0x7a,0xa3,0x7f,0xec,0x4e,0x59,0x53,
++            0x0d,0xbc,0xee,0xff,0x2f,0x13,0x97,0x8c,0xd5,0x6d,0xe8,0x15,0x9f,0x9f,0x91,0xa0,
++            0x01,0x42,0xd6,0xee,0x3d,0x12,0x6e,0x12,0xfb,0x90,0xc5,0x8e,0xff,0xe2,0x24,0xb0,
++            0xc6,0x93,0xee,0xbc,0xaf,0x1f,0x4d,0x53,0xcc,0x33,0x8c,0x90,0x73,0x48,0x51,0xe3,
++            0xd3,0x30,0x4f,0xad,0xdd,0xa9,0x82,0x13,0x1b,0x92,0xa5,0xfd,0x6d,0xbe,0x12,0xff,
++            0xfb,0x8d,0x76,0xc2,0xb1,0x3b,0xa0,0x57,0x4e,0x9f,0xb6,0xc6,0xdc,0x21,0x1f,0xe3,
++            0x85,0xdc,0x06,0x25,0xb0,0xa0,0x66,0x69,0xc3,0xa6,0x67,0xd8,0xf1,0x5a,0x53,0xfe,
++            0x73,0xff,0xa4,0xe3,0xb4,0x8f,0x81,0xc9,0xff,0x8f,0x51,0x05,0xb1,0xd9,0x5a,0xe2,
++            0x0d,0x0e,0xa4,0xe6,0x15,0xae,0xf1,0xd3,0xb6,0x43,0x5e,0xb1,0xf1,0x3a,0x9b,0xcb,
++            0x7d,0x0f,0xfe,0x3c,0x6e,0x66,0x0a,0x29,0x3e,0x06,0x89,0xba,0x21,0xa3,0x48,0x22,
++            0xf8,0x47,0x0c,0xd1,0x1d,0xaf,0x66,0x48,0xce,0x93,0x01,0xc2,0x68,0xb3,0x7f,0x90,
++            0x3d,0x5d,0xce,0x79,0x33,0x19,0x1d,0xa9,0x63,0x99,0x8e,0x64,0xed,0x46,0x54,0x9d,
++            0x62,0xf8,0x0e,0xa6,0xb5,0x4b,0x51,0x61,0x9f,0xb0,0x22,0x88,0x81,0x25,0x7d,0xad,
++            0xc2,0x05,0xd0,0xbf,0xf3,0x4c,0xcd,0x35,0x33,0x48,0xa8,0xdf,0x34,0xc5,0x31,0xa8,
++            0x2f,0xbd,0xb2,0x2c,0x4d,0x86,0x47,0xe9,0x4f,0x4b,0xd2,0x4d,0x3a,0x04,0x78,0x7b,
++            0xf0,0xb5,0x13,0x8f,0x7e,0xb8,0xce,0xd7,0xff,0x9d,0x05,0x6a,0x12,0xd2,0xab,0xea,
++            0x05,0x86,0x2b,0x6f,0xfb,0xec,0x28,0x4a,0x90,0x40,0x8d,0x08,0xdf,0x6a,0xfd,0x0f,
++            0xc0,0xa6,0xff,0xdf,0x3c,0x83,0xd0,0x16,0x29,0xa8,0xd5,0x7e,0xdd,0x2f,0x9e,0xfa,
++            0xaa,0x92,0x1d,0xaf,0x35,0x6f,0x62,0xfa,0xad,0xfd,0xea,0x1a,0x1b,0x22,0x0b,0x38,
++            0x77,0x4c,0x13,0xc8,0x94,0xa4,0xc4,0xed,0xc1,0xf6,0x13,0x8d,0x98,0x75,0xff,0x3b,
++            0x70,0x14,0xc4,0xb8,0x9d,0x97,0x23,0xd9,0x93,0x0d,0x63,0xcf,0x9b,0x8f,0x64,0xc4,
++            0x5b,0x9b,0x92,0xbc,0xdb,0x74,0x49,0xbc,0x66,0x71,0x23,0x91,0x76,0xda,0xac,0xe2,
++            0x82,0x17,0x28,0xb0,0x52,0xd5,0xdc,0x71,0xa1,0x13,0x0d,0xca,0xbb,0x40,0x85,0x63,
++            0x22,0x5a,0xbf,0x35,0x56,0x9d,0xc5,0x25,0xc9,0x17,0xc0,0xe2,0x0d,0xd4,0xdd,0xd5,
++            0x02,0x76,0x9a,0x66,0x35,0xbe,0x16,0x23,0xe7,0x49,0xd5,0xa1,0x25,0x42,0x59,0x44,
++            0x0c,0xd3,0xcb,0x21,0x8f,0x9b,0x6a,0xd9,0xc5,0x52,0xe7,0x82,0x8d,0xf5,0x4b,0x20,
++            0x5e,0xe4,0xb2,0xd3,0xca,0x94,0xdd,0x96,0x94,0x45,0x8c,0x83,0x69,0x6e,0x85,0x71,
++            0xb4,0x1e,0x65,0x60,0x78,0x3b,0x05,0xfc,0x41,0x4d,0x2a,0x63,0xa8,0x8b,0x33,0xd7,
++            0x42,0x94,0x6d,0x2e,0x42,0x94,0xe5,0x0e,0xe5,0xce,0x11,0x93,0xd0,0xf5,0x7e,0xaf,
++            0x0c,0x91,0xd4,0x3a,0xd3,0x5c,0x8c,0x2c,0x1c,0x6d,0x31,0x80,0xe0,0x69,0x08,0x38,
++            0x4a,0xab,0xf0,0x9a,0xd8,0xba,0x88,0xbb,0xe9,0x39,0xa0,0x94,0x9a,0x70,0x83,0x76,
++            0x5c,0x19,0x17,0x7d,0xa1,0x8b,0xd7,0xd0,0xd5,0x18,0x92,0x06,0xa4,0xb4,0x9c,0x6a,
++            0x2d,0x96,0x7d,0x6e,0x35,0x7a,0xdf,0x99,0x88,0xd6,0x0f,0x4d,0xa7,0xda,0x23,0x3b,
++            0xa6,0x97,0x62,0x36,0x3c,0x84,0x61,0x6c,0x2c,0x2d,0x8f,0xd7,0xdf,0xfe,0x0c,0x26,
++            0xd6,0x71,0x2d,0x9c,0x3d,0x39,0x5f,0x9e,0xe9,0x59,0x61,0xb6,0x6b,0x79,0x43,0x2b,
++            0x43,0xb4,0xf3,0x33,0x03,0x50,0x0e,0xe5,0x4f,0xa1,0x28,0x1d,0xf2,0x62,0xac,0x19,
++            0xb1,0xe2,0x4d,0xb6,0x34,0x99,0x0f,0xa6,0x48,0x3a,0x5f,0xba,0xd5,0x61,0x58,0x26,
++            0xa1,0xec,0xde,0x01,0x30,0x0d,0x74,0xca,0x73,0x0d,0xf0,0x44,0x75,0x0a,0x92,0x22,
++            0x06,0x2e,0x90,0x26,0xc5,0x0e,0x80,0xd2,0x09,0xda,0xc6,0x1a,0xbe,0xf0,0xe5,0xf8,
++            0xb7,0xb6,0x32,0x36,0x35,0x03,0x69,0x3b,0xf7,0xf6,0xeb,0xd8,0x3f,0xd3,0x89,0x61,
++            0xe7,0xb5,0x09,0x65,0xf7,0x04,0x9d,0xd5,0xd5,0x8c,0x83,0xdc,0xb6,0x6f,0xbb,0x34,
++            0x8b,0xe6,0xd4,0xad,0x9b,0x02,0x29,0x56,0xe3,0x65,0x30,0xaa,0x6c,0x69,0x60,0x0e,
++            0x64,0x8e,0xfb,0x42,0xea,0xc9,0x7a,0x7f,0xbb,0x54,0x69,0x4c,0x6f,0x10,0x8d,0xc7,
++            0xe4,0x5c,0x31,0x87,0x9f,0xa5,0x62,0x90,0xbe,0xc5,0xa8,0x45,0x71,0x53,0xfe,0xa0,
++            0x03,0x0a,0x8b,0x53,0x94,0x97,0x07,0x4b,0x1b,0x76,0xe8,0x49,0xbb,0xa5,0x5c,0x0d,
++            0x28,0x03,0xdc,0x09,0x38,0x23,0x9a,0xb2,0xad,0xd3,0xa7,0xaa,0x7c,0xd0,0x8a,0x68,
++            0x6f,0x6e,0x90,0xae,0xed,0x06,0x22,0x1e,0x7e,0xa4,0xaa,0x85,0xfc,0xe2,0xba,0x3a,
++            0xf0,0x25,0x79,0x23,0x77,0xee,0xea,0xdd,0x25,0x72,0x8b,0x4f,0x86,0xa8,0x55,0x1c,
++            0x2c,0xca,0x0f,0x3b,0xfe,0xe1,0x60,0xa4,0xfa,0x4c,0x7d,0x64,0x64,0x57,0x30,0xc1,
++            0xe5,0xe8,0xf2,0x76,0x2a,0x51,0x52,0x6f,0x86,0x5d,0x79,0xb0,0x58,0x96,0x86,0xc8,
++            0x0f,0x85,0xf8,0x35,0x90,0x0b,0x69,0x9c,0xcd,0xce,0x3a,0xd3,0xac,0x60,0x39,0x4a,
++            0x2d,0x73,0x0f,0xdd,0x82,0xa4,0x64,0x83,0x84,0x63,0x26,0xeb,0xae,0x5c,0x2e,0x24,
++            0x89,0x0c,0x3f,0x1f,0xeb,0xed,0x7e,0x99,0xfc,0x0d,0xa2,0x69,0x78,0xf4,0x76,0x34,
++            0x00,0x2f,0xfa,0x64,0x68,0x34,0xcb,0x52,0xa5,0x21,0x22,0x22,0x54,0xd3,0x13,0xe2,
++            0x29,0x3e,0xd4,0x8b,0xf5,0xf0,0x64,0xba,0x06,0xbf,0x44,0x32,0x55,0xf3,0x1f,0x33,
++            0x82,0x0d,0xdd,0xf4,0xc0,0x19,0xf5,0x83,0xfd,0xdf,0x8b,0x8f,0x57,0x73,0x8d,0x89,
++            0x29,0x6e,0xd3,0x90,0x14,0x6c,0xaa,0x37,0xc5,0xdf,0x85,0xa7,0x56,0x5e,0xa4,0x72,
++            0x69,0xd6,0x30,0x86,0x22,0xc9,0xcb,0x00,0xca,0x79,0x8f,0x0e,0xb2,0xbb,0xad,0x92,
++            0x7f,0x1e,0x51,0xeb,0xc8,0x9d,0x6b,0x10,0x61,0xec,0xaa,0x05,0xf3,0x7e,0xb1,0x75,
++            0xa0,0x15,0x72,0x38,0x36,0x16,0x66,0x01,0x4a,0x7b,0x65,0x17,0xc6,0x57,0x31,0xee,
++            0x4c,0xd3,0x10,0xf3,0x95,0x14,0x68,0x77,0x9a,0x8a,0xc8,0x46,0x95,0x58,0x5e,0x96,
++            0x08,0x37,0x12,0xec,0xc3,0x15,0x0c,0x48,0x30,0x2f,0x20,0x2a,0x5c,0xab,0x50,0x9d,
++            0x09,0xa8,0xf0,0x7c,0x39,0x14,0x33,0x3e,0x70,0x33,0x80,0x92,0xde,0x59,0x87,0xf9,
++            0xce,0x5d,0xae,0xbe,0x1d,0xfb,0xb0,0xc4,0xea,0x08,0x89,0x86,0x5f,0x9f,0x56,0xfd,
++            0x20,0x6d,0x21,0xad,0x56,0xff,0xff,0xc3,0x34,0xdd,0x29,0x9e,0x73,0xba,0x5c,0x7a,
++            0xb4,0x33,0x3a,0x33,0x52,0x07,0x3e,0xee,0xeb,0x3d,0x52,0xca,0x50,0x23,0xe9,0x9b,
++            0x2d,0xdc,0xb7,0x41,0x9a,0xb6,0xaa,0x7c,0x1f,0x20,0x80,0x4f,0x96,0x7e,0xc3,0x3b,
++            0xa6,0x91,0xf2,0x4b,0x88,0xbe,0xe7,0xf0,0xc4,0xa3,0x5b,0x9c,0x94,0x08,0xc8,0xe3,
++            0xd0,0xbf,0x7e,0xff,0x99,0x5d,0x61,0x5a,0xce,0x66,0x1c,0x0c,0x9d,0xbe,0xb7,0xd4,
++            0x77,0x00,0xfe,0x03,0xb1,0x5f,0x2a,0xda,0xbb,0x3d,0x6f,0x5e,0x26,0xbf,0x5e,0x6e,
++            0x6b,0x82,0x48,0xd5,0x5a,0xbc,0x60,0xce,0xb8,0x72,0x87,0x62,0x57,0x40,0xbe,0x30,
++            0xea,0xad,0x2d,0x7f,0x0e,0xbd,0x86,0xde,0x75,0xe1,0x51,0x05,0x44,0x20,0x77,0xa1,
++            0xa5,0xae,0xf1,0x0c,0xf2,0x43,0x66,0x4b,0xf3,0xdc,0x82,0xb1,0x89,0x0f,0x0a,0xbb,
++            0xa1,0x02,0xd6,0xf0,0xed,0x89,0xf3,0xc5,0x9e,0xc7,0xf8,0x17,0xde,0xe2,0xb3,0xb2,
++            0xa2,0x8f,0x2a,0x4b,0xdd,0xa8,0x62,0x41,0x25,0xea,0x1f,0x45,0x61,0x27,0x61,0x7d,
++            0x23,0x8c,0xb9,0xf4,0xf8,0x89,0x72,0xd0,0x1a,0x85,0xd1,0xa5,0xc0,0xed,0x36,0xb3,
++            0x22,0x88,0xb7,0xc6,0xf8,0xa1,0x08,0x02,0xa9,0xc4,0xc9,0xd4,0xb0,0x98,0x54,0x38,
++            0xf7,0xa7,0x15,0xf3,0xf9,0xfb,0x82,0xd2,0x2b,0x59,0x3b,0x52,0xcd,0x14,0xf5,0xeb,
++            0x6f,0x48,0x28,0x6a,0x9b,0xee,0xa8,0x80,0xa2,0x2d,0xad,0x8d,0xad,0xea,0xd5,0x7a,
++            0xea,0x89,0x78,0x0f,0x51,0x31,0x04,0xda,0x4c,0xc1,0x2c,0x62,0x28,0xe9,0x51,0x31,
++            0xe1,0xa8,0x04,0xff,0xe2,0x0b,0x23,0xc7,0x34,0x27,0x2c,0x8c,0xdf,0xdb,0x22,0x4a,
++            0x76,0x03,0x42,0x5f,0x70,0xfa,0x29,0x9b,0x24,0x20,0xaa,0x9d,0xf9,0x2c,0x72,0xda,
++            0x29,0x3d,0xad,0xad,0xc9,0x6d,0x12,0xe1,0xc6,0xc0,0x8d,0x8c,0xa4,0x62,0xd3,0xcd,
++            0x81,0xac,0xe5,0xf9,0x44,0x81,0x6d,0xcc,0x08,0xce,0xed,0xc5,0xdc,0x6f,0x33,0xdb,
++            0x6d,0x3d,0xb5,0x6b,0x70,0xca,0x3d,0xc9,0x34,0xc4,0x6f,0x9f,0xff,0xe4,0xf9,0x78,
++            0x20,0xef,0x44,0xa4,0x6e,0x2b,0x6a,0xa6,0x03,0x65,0x7a,0x87,0xe7,0x55,0xa0,0xe3,
++            0x4b,0x90,0x27,0x11,0xa2,0x0e,0x8c,0x4c,0xe1,0xaa,0x1b,0x90,0xf4,0x81,0xde,0x81,
++            0xa4,0xa2,0x03,0xdb,0x3d,0x50,0x43,0x8d,0x0b,0x36,0x29,0x86,0x47,0x3c,0x09,0x62,
++            0xcf,0x9e,0x72,0x65,0x59,0x42,0xbd,0x33,0x07,0xb7,0x0d,0xc7,0x0e,0x31,0x1d,0x59,
++            0x87,0xcb,0xb6,0xcc,0xd6,0x93,0x5c,0xc8,0x8b,0xd7,0x73,0xe2,0xa6,0x10,0x6e,0x2b,
++            0xca,0xdf,0xcd,0xe2,0xcb,0xce,0x88,0x63,0x0d,0x8a,0x18,0x24,0x7f,0x73,0x7b,0x15,
++            0x76,0x19,0xf4,0x69,0x56,0xa3,0x33,0x49,0x1d,0xfb,0xed,0x0a,0xfc,0x14,0xee,0x33,
++            0x63,0xba,0xcd,0x17,0x30,0x71,0x9d,0x39,0xe3,0xfa,0x55,0x38,0x50,0x0a,0x96,0xfb,
++            0x6f,0x9a,0x46,0xad,0x7e,0x35,0x4c,0xaa,0xcb,0x43,0xca,0x7e,0x99,0x87,0x6e,0x2f,
++            0xd0,0x5b,0xb5,0x20,0xce,0x7b,0x13,0x5a,0x12,0x79,0x85,0xc8,0x02,0x79,0xf8,0xfa,
++            0x82,0x5b,0xdc,0x8d,0xc4,0xc5,0x35,0xdf,0x6a,0x9d,0x17,0x4c,0x5e,0x3a,0x4f,0xfc,
++            0x2b,0xfc,0x9f,0x60,0xbf,0x82,0x20,0xfe,0x2b,0xbb,0xc4,0xdd,0x86,0x5b,0x3e,0xa8,
++            0x22,0xac,0x71,0xe8,0x51,0x33,0x07,0xd5,0x95,0xf1,0x9c,0xf9,0xf8,0x7f,0x2e,0x6e,
++            0x20,0x12,0xde,0x65,0x9a,0x22,0xe1,0x6b,0x0d,0x80,0x92,0x0c,0x77,0x72,0xf8,0xd2,
++            0x09,0x9a,0x47,0xbe,0x88,0x7c,0x81,0x55,0x1d,0x32,0x94,0x0f,0x78,0x36,0x16,0x40,
++            0x0e,0xe0,0x7b,0xbf,0x50,0x7b,0x39,0x48,0xea,0x0f,0xf8,0xfb,0x2b,0x1b,0x5e,0x04,
++            0x67,0x45,0x60,0xc7,0x5f,0xad,0xd3,0x06,0x27,0xd1,0x1c,0x59,0x68,0x1f,0x10,0xe1,
++            0x27,0xef,0x04,0x89,0x14,0x21,0x8a,0x8e,0xae,0xa5,0xd8,0x34,0x54,0xec,0x77,0xb3,
++            0x6f,0xe6,0x5e,0xef,0x18,0x6f,0xa6,0xd0,0x40,0x49,0x0a,0x8b,0x23,0xa3,0x4f,0x2b,
++            0xa1,0x08,0xae,0xac,0xd1,0xac,0x01,0x17,0x32,0xce,0xcb,0x3f,0xd5,0xe9,0xa0,0x83,
++            0x14,0x89,0xbe,0x75,0x06,0x0b,0x72,0xf1,0x68,0x1b,0x37,0x5b,0x50,0xe5,0x08,0x50,
++            0x7e,0x88,0xd6,0xfe,0xdd,0xd6,0x42,0xed,0xb8,0x4e,0x00,0xf2,0x77,0xe7,0x01,0xe3,
++            0xda,0x89,0xd3,0x01,0x04,0xca,0xb1,0xab,0xc6,0xaa,0xa5,0x08,0x75,0x67,0x7b,0x57,
++            0x05,0x84,0x97,0x4c,0x7e,0x44,0x7b,0xed,0x30,0xc4,0xa3,0x76,0x74,0xa5,0x33,0x3b,
++            0x62,0x27,0x62,0xcf,0x09,0xa5,0x4d,0xd2,0x4c,0x8a,0x2e,0xac,0x17,0x0f,0xf8,0xe9,
++            0x81,0x84,0x3a,0x51,0xe4,0xd5,0x46,0x58,0xb6,0x88,0x14,0x1d,0xc8,0xcc,0x83,0xfb,
++            0x68,0x29,0xc3,0xb9,0xc4,0xa5,0x34,0x6c,0x4e,0x2d,0xa5,0x4d,0xf3,0xcf,0xd4,0x3f,
++            0x64,0xe8,0x02,0x60,0x08,0xf6,0x61,0x13,0xa5,0xba,0x12,0x1c,0x04,0xce,0xa7,0xa8,
++            0x8c,0x4b,0x80,0x4e,0xf5,0x38,0xcc,0xc2,0xaf,0x13,0xe2,0xc7,0xaf,0xe3,0x0a,0xec,
++            0x1d,0x80,0x8b,0xfe,0xc9,0x12,0x44,0xca,0x85,0xde,0x21,0x7c,0x20,0x94,0x2f,0x29,
++            0xce,0x81,0xbd,0x40,0x92,0xe0,0x8c,0x69,0xe0,0xa0,0x47,0x14,0x7d,0xaf,0x94,0xa9,
++            0xae,0x1d,0xc2,0x30,0x0e,0x6a,0x45,0xde,0x05,0x2c,0xa0,0x7d,0xa4,0x76,0x1a,0xe0,
++            0x97,0xf5,0x0e,0x98,0x56,0x44,0x7c,0x13,0xb8,0x94,0x34,0x17,0xaa,0xbe,0xd5,0xb5,
++            0x84,0xee,0x64,0x12,0x15,0x10,0x47,0x36,0x6e,0x89,0x9c,0xe7,0xd4,0x79,0x1d,0x68,
++            0x08,0x9f,0xf3,0xe9,0xb2,0xb3,0x96,0xa4,0x48,0xdf,0xf7,0x61,0xb0,0xf4,0xbd,0x11,
++            0x4b,0x3e,0xf4,0x82,0x60,0xdf,0x06,0x51,0x39,0x97,0x3d,0x55,0x77,0xf7,0x04,0x74,
++            0x2d,0x99,0xc5,0xc1,0xbb,0x32,0x4a,0x56,0x06,0x2b,0xcc,0x19,0xb7,0x96,0x14,0x56,
++            0x2c,0x34,0xec,0x96,0x55,0x08,0x83,0x0c,0x43,0xbb,0x9c,0xb2,0x24,0xfa,0xc2,0x21,
++            0x66,0x3b,0x85,0xb4,0x3a,0x30,0x8a,0x90,0x8c,0x55,0x31,0x62,0xb5,0xd6,0x55,0x29,
++            0x0b,0x9a,0x8f,0x55,0x46,0x31,0x3d,0xcc,0xef,0xbb,0x42,0xa5,0xf9,0x7d,0x1e,0x70,
++            0x80,0x95,0x62,0xd0,0x32,0xa6,0x95,0xad,0xc0,0xbd,0x25,0xcc,0x3d,0xd8,0x9a,0xf8,
++            0xd2,0xd8,0x3b,0x1a,0x15,0x6b,0x64,0xf2,0x15,0x76,0x9e,0x3b,0xf8,0x7b,0x58,0xac,
++            0x0d,0x45,0xda,0x70,0xdf,0x3d,0x0f,0x9a,0x4d,0x45,0xcf,0xcd,0xbd,0xba,0x11,0x2f,
++            0x4d,0x64,0x97,0x67,0xbd,0x4a,0x9f,0xc9,0x8f,0x1c,0xdf,0xbd,0xb4,0xf6,0x19,0xed,
++            0x8f,0x43,0xe6,0x8e,0x4e,0xfe,0x5e,0x28,0xba,0x7f,0x72,0xc9,0xdd,0x48,0xbe,0x8a,
++            0x29,0x9f,0x5a,0xbc,0xd4,0xf9,0x59,0x52,0x86,0xae,0xb4,0xeb,0xfd,0xb5,0xd3,0xa9,
++            0x51,0x98,0xf7,0x66,0x1f,0xa1,0xd0,0x5f,0x3e,0x3d,0x57,0xf5,0x72,0xf3,0xf3,0xdf,
++            0x8c,0x0b,0xce,0xd8,0x30,0x39,0x21,0x19,0xeb,0x5a,0x67,0x1d,0xdb,0xff,0x2f,0x7f,
++            0xd9,0x9c,0x08,0x06,0xb1,0xaa,0x06,0x15,0x46,0x41,0x27,0x08,0x74,0x94,0xf1,0xd7,
++            0xf8,0x87,0xc2,0xea,0xb2,0x27,0xd8,0x10,0x5a,0x4c,0xa0,0x64,0x53,0x6e,0xba,0x5b,
++            0x61,0x7d,0x5e,0xe7,0x3c,0x2f,0x51,0x43,0xe1,0x31,0x82,0xa7,0x50,0xca,0x09,0x6b,
++            0x43,0x43,0x81,0x90,0x30,0xa9,0x01,0x25,0xc7,0x42,0xa3,0xb7,0x59,0xbb,0xc1,0xb3,
++            0xe2,0x48,0x6b,0xc1,0x81,0x1b,0xa6,0xa0,0x52,0x06,0xd8,0x71,0x61,0x81,0xe3,0xb8,
++            0x47,0x69,0x08,0xb5,0x1f,0x19,0xec,0x0b,0xe0,0xb5,0x20,0x69,0xad,0xb5,0x20,0x3a,
++            0x57,0x9b,0xbe,0x1a,0x27,0xda,0x5e,0x63,0x33,0x49,0xee,0x83,0xc2,0x9b,0x9d,0x0f,
++            0xad,0xdb,0x76,0x1e,0x95,0x26,0xe6,0x01,0x97,0x4c,0x2c,0x51,0x0f,0xa4,0x0a,0x81,
++            0xe9,0xb9,0x75,0xee,0xb9,0xa2,0x5f,0x4a,0x0a,0x47,0xea,0xae,0xd8,0x00,0x6a,0xaf,
++            0xe8,0x4b,0x77,0xfe,0xb8,0xa3,0xda,0x19,0x33,0x25,0xa3,0xc0,0x55,0x2b,0xfc,0x73,
++            0xea,0xd5,0x6c,0xef,0x39,0xa0,0x2d,0xfd,0x8a,0x95,0xad,0x15,0x7b,0x91,0x41,0x27,
++            0x8f,0xbb,0xf4,0xff,0x1b,0x03,0xf8,0xf9,0x81,0x09,0x06,0x66,0xdf,0x92,0x2b,0xa3,
++            0xe1,0xb8,0x8e,0xc8,0x3a,0x8d,0xe3,0x4c,0x21,0xfd,0x8c,0xd9,0x52,0x6a,0xca,0x9e,
++            0x99,0x0e,0x0e,0x02,0x15,0x33,0x04,0x45,0x95,0xe6,0x5d,0x83,0xb2,0xae,0xe0,0x53,
++            0xe1,0x7a,0x9a,0x58,0x4f,0x42,0x77,0x98,0xbe,0x42,0xf3,0xa9,0x7b,0xe4,0xa8,0xa2,
++            0x62,0xa8,0xb6,0xb2,0x6a,0x6d,0x0b,0xab,0x22,0x85,0x77,0xe2,0xd8,0xcf,0xc4,0x99,
++            0xeb,0xed,0xbe,0x28,0xdb,0x54,0x94,0xcc,0xdf,0xf0,0xb4,0xe1,0xd1,0x79,0xf5,0x68,
++            0x29,0xaa,0x8c,0x6d,0x3d,0x73,0x0c,0x24,0x76,0x1f,0x18,0x30,0x4c,0xcd,0x90,0x6e,
++            0x55,0x41,0x45,0xd0,0x94,0xa9,0x83,0xa0,0xc3,0x13,0x10,0x58,0x41,0xa9,0x0d,0x13,
++            0x4f,0x5e,0x8a,0x46,0x65,0x02,0xdf,0x59,0xe7,0x1e,0x9b,0x8c,0x71,0x6e,0x3f,0xe7,
++            0x83,0xab,0x3c,0xcc,0x95,0x24,0xc3,0xdb,0x16,0xc1,0xe9,0x60,0x70,0x1d,0xb1,0x3c,
++            0x23,0xa8,0xf2,0xac,0x4f,0x77,0x62,0x54,0x65,0x86,0x96,0x95,0xbb,0x0f,0x1c,0x4f,
++            0x07,0xc9,0x3d,0xcd,0x15,0xc9,0x42,0x65,0xbd,0xcd,0xb5,0x52,0x0b,0x34,0xd8,0x2a,
++            0x16,0x84,0xc2,0xe9,0x12,0x88,0x16,0xc0,0xc1,0xf8,0xa5,0x71,0xb0,0xec,0x3e,0x77,
++            0x5f,0x18,0x21,0xa0,0x3e,0xf0,0x64,0xa9,0x2e,0x43,0xf6,0xae,0x75,0xf3,0x0e,0x1c,
++            0x71,0xb7,0x8c,0x6f,0xbd,0xb4,0x1a,0x3c,0x4c,0xf8,0x90,0xde,0x3a,0x84,0xc7,0x59,
++            0x06,0x81,0x3d,0x72,0x05,0xbb,0x87,0xcf,0x13,0xa1,0x68,0x4f,0x7a,0x7e,0xb0,0xb4,
++            0x16,0xc6,0x5e,0x19,0xf4,0xfb,0xc0,0x73,0x9e,0x6b,0xe7,0x7a,0xdd,0x15,0x3d,0x4c,
++            0x73,0x18,0x9d,0xcc,0xb7,0x27,0x06,0x96,0x00,0xad,0x16,0x3c,0x69,0xd1,0xb3,0x1f,
++            0x2d,0xa5,0xee,0x2f,0x98,0x2f,0x97,0xc9,0x1f,0xf2,0x1e,0x2c,0x0c,0x7b,0x7f,0x27,
++            0x06,0x13,0xf1,0xab,0x60,0xb5,0x29,0xd4,0xec,0x8d,0x05,0xfe,0x94,0x71,0xb9,0x99,
++            0xe9,0xc2,0x77,0xad,0x3b,0x99,0xcc,0x87,0x81,0xee,0x29,0x8e,0xff,0x7d,0x4e,0x6d,
++            0x78,0xff,0x04,0x64,0x57,0x5d,0x24,0x9b,0x04,0xcf,0xb5,0xdb,0xe5,0x3b,0xa8,0xeb,
++            0x05,0xef,0x0f,0x3e,0x88,0x1c,0x3e,0xb6,0x6d,0xf9,0x78,0xd6,0xcb,0xa3,0x98,0xbf,
++            0x33,0x19,0xd9,0x23,0x40,0x43,0xf1,0x02,0xdd,0xcb,0x35,0xa3,0xe9,0x5e,0x16,0x81,
++            0x85,0x1e,0x04,0x59,0x64,0xff,0x7b,0xd1,0x2c,0x69,0xe5,0xa5,0x3c,0x72,0x6e,0xf0,
++            0x25,0x44,0xf0,0x68,0x10,0xa5,0x62,0x9c,0xad,0x87,0xca,0x95,0x30,0xe0,0x48,0x42,
++            0xb3,0x52,0x44,0xd3,0xc2,0xc7,0x2c,0x35,0x8d,0x6f,0xc0,0xa6,0x0b,0x1a,0x3b,0x19,
++            0x31,0xf9,0xf7,0xaf,0xda,0x7a,0x4b,0x90,0xec,0x6b,0xf6,0xe5,0x56,0xac,0xdc,0xec,
++            0x5a,0xfa,0x80,0xbc,0x6c,0x5b,0x31,0xdb,0x2e,0x16,0x55,0x04,0xb1,0x11,0x40,0x0b,
++            0x0d,0xba,0x62,0x5a,0xf9,0x57,0x70,0xd4,0x4a,0xe9,0xc0,0x2a,0x58,0x84,0x78,0xe5,
++            0x8f,0x6e,0x6a,0x4b,0x39,0xd4,0x3c,0xbe,0x65,0x63,0x84,0x07,0xd0,0x6f,0x19,0x32,
++            0x73,0x17,0x06,0x09,0x08,0xce,0x7d,0x6c,0x1a,0xc0,0x23,0x5d,0x37,0x5b,0x97,0x9f,
++            0xce,0x5e,0xb9,0x0f,0x76,0xef,0x39,0xd9,0x31,0x2a,0xf9,0xff,0x5a,0xed,0xcd,0x14,
++            0xbb,0x50,0x5f,0x11,0x18,0x8d,0x60,0x7a,0xb1,0x41,0x8c,0xda,0xdc,0x0b,0xfa,0x28,
++            0xf0,0x70,0xfe,0x6a,0x3b,0x20,0x72,0x7a,0x87,0x8e,0xdc,0xa6,0xfc,0xaf,0x0b,0x89,
++            0x08,0x7b,0x67,0xb4,0x27,0xec,0x25,0x52,0x39,0x65,0xce,0xeb,0x9d,0xc7,0xab,0x02,
++            0xe1,0x82,0xb2,0x6d,0x38,0xbf,0x77,0x54,0xed,0x9a,0xb1,0x87,0x5d,0x08,0xf5,0x7c,
++            0xf9,0xed,0x01,0x80,0xa0,0xd4,0xf4,0xde,0xfc,0xd6,0xf4,0x99,0x7c,0x9c,0xc4,0xf0,
++            0x44,0xb1,0x09,0x90,0xa1,0xd5,0x44,0x30,0x60,0xbb,0x1b,0x21,0x1e,0x57,0x8a,0xa7,
++            0x26,0x75,0x9d,0x78,0x18,0xbf,0x3d,0x14,0x87,0xf2,0x9d,0x65,0x20,0x34,0x75,0x5a,
++            0x4e,0x72,0x19,0xb0,0x68,0xbc,0x05,0x63,0x12,0xdc,0x3d,0x46,0x37,0xb3,0x1b,0x05,
++            0x9b,0x22,0x9c,0x06,0x3c,0xa4,0x0a,0xdb,0x2e,0xf7,0x68,0x64,0xab,0xfb,0x76,0xd0,
++            0xb5,0x9d,0xad,0xb0,0x04,0xa0,0x6c,0x7a,0x54,0x35,0x53,0x04,0x14,0x6b,0x3f,0xc1,
++            0x15,0xcb,0x5d,0x2f,0x5a,0xf9,0x55,0xa0,0xc2,0x94,0xaf,0xe6,0x55,0xf0,0xae,0x95,
++            0xc5,0xdb,0x15,0x3f,0x57,0x2a,0xd6,0xb4,0xe9,0x0b,0x85,0x75,0x2a,0x88,0x18,0xbf,
++            0xa1,0x3e,0x12,0xf1,0x9f,0xcc,0x56,0xee,0x4d,0x55,0x8c,0x5d,0xaa,0x57,0xb8,0xab,
++            0x8c,0x38,0x38,0x7c,0x91,0x14,0xb6,0x76,0xce,0xdf,0xc0,0x24,0x96,0x3c,0x28,0x4b,
++            0xaf,0x37,0x07,0x81,0x30,0x17,0x4f,0x8c,0x4f,0xdc,0x50,0x5e,0x26,0xea,0x17,0x64,
++            0xce,0xf6,0xbe,0x7d,0x49,0x8a,0xb7,0x6f,0x4e,0xdd,0xc1,0x88,0x96,0x5e,0xb6,0xc8,
++            0x3c,0x61,0x1e,0xc6,0xbe,0xbe,0xb2,0x20,0xd5,0x83,0x49,0x0c,0xda,0x0d,0x15,0xfd,
++            0x8e,0x22,0x02,0xa5,0xa1,0x36,0xbe,0xda,0x4b,0xc6,0x2a,0x2e,0xfe,0x45,0xa7,0x92,
++            0xc0,0x93,0xbe,0xf8,0x1b,0xc1,0x29,0x09,0xea,0x43,0xcd,0x4a,0x3f,0x9d,0xc3,0xb4,
++            0xa9,0x27,0xcf,0x35,0xce,0xa9,0xf9,0xa5,0x62,0xbd,0x00,0xd9,0xdd,0x72,0xd4,0x52,
++            0x2e,0x8a,0xd0,0xfa,0x1c,0x8b,0x90,0xe7,0x64,0x2c,0xee,0x22,0xb1,0xe3,0xf1,0xf2,
++            0x83,0xfd,0x48,0xe5,0xae,0x83,0x42,0xcf,0xaa,0x90,0x7c,0xca,0x32,0x41,0x39,0x5c,
++            0x02,0xfe,0x7c,0x15,0xfb,0x5d,0x81,0xd0,0xb8,0x62,0x00,0xd6,0x5c,0xef,0x74,0x62,
++            0x98,0x0c,0xd7,0xfa,0xc5,0x20,0x67,0x0c,0x43,0x84,0x7d,0x2b,0xed,0xcc,0x95,0x2f,
++            0x6a,0x09,0xbe,0x42,0xf3,0xa7,0xd0,0xbc,0x44,0x5f,0x7c,0x26,0xd1,0xb0,0x36,0x56,
++            0xe2,0x86,0x57,0xb4,0x73,0xd8,0x42,0x37,0x9d,0x4f,0xa6,0xe7,0x38,0xe3,0x57,0x23,
++            0xe2,0x48,0xe1,0xb6,0x1e,0x2b,0x41,0x07,0x3d,0xeb,0x33,0x7a,0x1c,0xeb,0xbd,0xa2,
++            0x0f,0x47,0x5a,0xab,0xcb,0x90,0xdf,0x8d,0x25,0xbc,0x59,0x2b,0x22,0xbb,0x62,0x57,
++            0xbb,0xa5,0xfb,0xf7,0x73,0x57,0xb0,0x4a,0x23,0x47,0x81,0x5e,0xa3,0xc5,0xf0,0x6b,
++            0x14,0x06,0xd4,0xf3,0x3b,0x2a,0x6c,0x37,0xe8,0xb8,0xa8,0xc3,0xa0,0x05,0x8a,0xeb,
++            0x0a,0xf6,0xc0,0xfc,0x27,0x4a,0x94,0x1b,0x37,0x4c,0x8d,0xdc,0x7b,0x2a,0xbf,0x6a,
++            0xd8,0x04,0xf2,0xe6,0x6d,0xf4,0x09,0xdb,0x22,0xda,0x7c,0x4e,0x7a,0xe2,0x02,0x2d,
++            0xde,0xe4,0xc4,0x23,0x98,0x28,0x15,0xec,0x7b,0x2f,0x7d,0x17,0x87,0xb8,0x4c,0xb0,
++            0x83,0xc0,0x08,0x23,0x96,0xab,0x4e,0x1e,0xb4,0xe0,0xbd,0x8d,0x89,0x2d,0xe4,0x01,
++            0xaa,0xff,0xd5,0x2f,0xee,0x25,0x03,0x70,0xc0,0x55,0x30,0x72,0x04,0xc1,0x6b,0x51,
++            0xb8,0x4b,0x1b,0x1d,0x99,0xd2,0x41,0x3e,0x15,0x45,0x70,0x13,0x0e,0x93,0x3c,0x7f,
++            0xad,0xa6,0xf3,0x6c,0xd2,0x72,0x72,0x9c,0x63,0x90,0x93,0xa6,0xf3,0x31,0xcc,0xe9,
++            0xf8,0x7f,0xc8,0x10,0x47,0x69,0x39,0x89,0x79,0x55,0x23,0xef,0x1a,0x7e,0xbe,0x1b,
++            0xa3,0x30,0x56,0xfd,0x92,0xe2,0xb6,0x9d,0x3c,0xa3,0x38,0xde,0x6d,0xce,0xb2,0x03,
++            0xb2,0xce,0x4d,0xe0,0xb0,0xce,0xa5,0xc2,0x99,0xcc,0x1d,0xce,0xf7,0x72,0x3e,0xa0,
++            0x3c,0x9f,0xdc,0x60,0xbf,0xb2,0x44,0x41,0xc3,0x6d,0x63,0xc0,0xfd,0x76,0x90,0xb2,
++            0xd4,0x28,0xcc,0xd6,0x73,0x88,0x5a,0x40,0x00,0xdb,0xb4,0xea,0xb5,0x81,0x0e,0xfc,
++            0xa4,0x1c,0xc7,0x05,0xf2,0xad,0x0d,0xc4,0x5e,0xd5,0x62,0xe4,0x7f,0x7a,0x5f,0xd1,
++            0x1c,0x9a,0xdf,0x2f,0x40,0xaa,0xc8,0x75,0xc3,0x55,0x3b,0x04,0x39,0x37,0x64,0x8c,
++            0x29,0xb8,0x9c,0x8d,0x6d,0x31,0x28,0x94,0x97,0xc5,0x06,0x44,0x34,0xa4,0x9e,0x70,
++            0xd7,0x54,0xc3,0x9b,0x3f,0x71,0xa9,0xb9,0xe4,0x55,0xf7,0x57,0x86,0x3b,0x17,0x04,
++            0xac,0x74,0x81,0x70,0xb4,0x78,0xec,0x8d,0x67,0x58,0x3b,0x28,0x2d,0x18,0xf4,0x91,
++            0x0c,0xe4,0x6d,0x19,0xc4,0x08,0x77,0xa7,0x1e,0xaf,0x8f,0x40,0x04,0x39,0x14,0x6c,
++            0xb6,0x58,0x02,0x49,0x34,0xb6,0x6d,0x0a,0x6c,0x5d,0x88,0x7e,0x7e,0x80,0x08,0x91,
++            0x73,0xed,0x08,0x26,0xb6,0xbb,0x66,0x17,0xe6,0xab,0xde,0xe3,0xa5,0xd6,0x39,0xce,
++            0x5f,0x11,0x00,0x36,0x98,0x5d,0x86,0x8b,0x5d,0x3b,0xe8,0xb2,0x91,0xa8,0x6f,0x1f,
++            0x8f,0x1c,0xc8,0x1d,0xb3,0xaf,0xe6,0x67,0xe8,0x6f,0xb8,0xf0,0x1a,0xd0,0x40,0x42,
++            0xb9,0x0b,0x17,0xf9,0x97,0xae,0x60,0x3b,0x50,0xdb,0x90,0xcc,0x37,0xe4,0x57,0x90,
++            0x04,0x7e,0x8f,0x60,0x34,0x99,0x06,0x0a,0x9b,0x6e,0xab,0x0f,0xbe,0xa5,0x25,0xe1,
++            0xa6,0x7d,0x41,0x38,0xb0,0xb9,0x27,0x45,0x3b,0xae,0xd0,0xe7,0x86,0x4f,0x11,0x33,
++            0x24,0xbc,0x45,0x85,0xd9,0xab,0x2a,0xda,0xcd,0xfe,0x83,0x86,0xe9,0x4c,0xda,0x05,
++            0x35,0xa0,0x0c,0xd4,0x25,0xae,0xf6,0x9e,0xa0,0x3f,0x4d,0x39,0x82,0x21,0x10,0x60,
++            0xfc,0x70,0x10,0xad,0x68,0x85,0xe8,0x39,0xba,0xf9,0xa6,0x44,0x53,0xa9,0x83,0xd3,
++            0x4e,0x2f,0x60,0xaf,0xb2,0x5b,0xa5,0xe7,0xf7,0xa5,0x56,0x50,0x3d,0x43,0x73,0x40,
++            0xee,0xbf,0x69,0x33,0xff,0x5c,0x23,0x8c,0x38,0x18,0x98,0x64,0xd6,0x73,0xfd,0x0a,
++            0x28,0x93,0x22,0x9a,0x38,0x73,0x9e,0xb9,0x3c,0xc2,0x16,0x5c,0xd2,0x17,0x92,0xe1,
++            0x8f,0x6e,0x31,0x2c,0x6a,0x8d,0xfa,0x52,0x4d,0xa5,0x1a,0x4c,0x3f,0xdf,0xd3,0x6d,
++            0x7f,0x9a,0x87,0xf2,0x1d,0xe8,0x72,0x74,0x75,0x36,0xe9,0xaf,0xa4,0x45,0xd3,0x79,
++            0x7a,0xee,0x74,0x5d,0x9b,0x83,0x84,0xa8,0xb1,0x16,0xc5,0x38,0x20,0xe4,0x5c,0x03,
++            0x2f,0xdd,0xe0,0xca,0x05,0xc8,0x45,0x33,0xaf,0x53,0xd4,0x2f,0x86,0x47,0xca,0x28,
++            0x65,0x65,0xb0,0xd2,0x6b,0xef,0x1c,0x23,0x4c,0xce,0xaa,0xe0,0xa4,0x16,0x5d,0x03,
++            0xf6,0x21,0xc3,0xf0,0x7f,0x71,0x0d,0xdb,0x3f,0xa2,0x56,0x6a,0x59,0xf8,0x15,0x5c,
++            0x2e,0xb0,0xe4,0x44,0x3e,0x10,0x21,0xe6,0xbf,0x8d,0xfb,0xbd,0x5c,0xa9,0x44,0x35,
++            0x83,0x9d,0xf4,0xa7,0x36,0xb1,0xcb,0x53,0xdb,0xe3,0xa4,0x8c,0x72,0xf1,0xec,0xeb,
++            0xfc,0xfd,0x2a,0x7e,0x06,0x7a,0xc1,0xa2,0x0e,0xae,0x10,0x33,0xa0,0x93,0x5e,0xa4,
++            0x05,0x2d,0xb7,0x9e,0x96,0xc0,0x65,0x5d,0xe8,0x79,0xa3,0x4f,0xb8,0x2e,0x92,0x01,
++            0xd5,0x4e,0xad,0x9f,0xd2,0x93,0xfd,0x42,0x5a,0x71,0xd4,0x5c,0x0a,0xb1,0x22,0xe3,
++            0x51,0x53,0xdb,0xa6,0x3e,0x06,0xdf,0x8c,0xb3,0x28,0x97,0xb8,0xc3,0x28,0xd4,0xe2,
++            0xd8,0xd3,0x69,0xa9,0xb8,0x23,0x53,0xea,0xe7,0x89,0x4e,0xe9,0x9b,0x5e,0xba,0x5a,
++            0x95,0x04,0x5a,0x80,0x6c,0xbe,0xc8,0xbc,0x3f,0x4b,0x5a,0x88,0x2b,0x22,0xfa,0x57,
++            0xf0,0xd5,0xa5,0xc3,0x37,0xa7,0xd2,0x88,0x3a,0x96,0xcb,0xf5,0x9c,0x72,0x44,0x8b,
++            0x2f,0x68,0x0e,0xae,0x18,0xf6,0x68,0x45,0x3c,0xdb,0xa6,0xa0,0x81,0xf7,0x2a,0x5a,
++            0x69,0x82,0xbc,0x65,0xb0,0xdb,0xff,0xa0,0x9a,0x6d,0x86,0x8e,0xed,0xbb,0x7e,0x67,
++            0x49,0x1c,0xb7,0xab,0x55,0x13,0x4e,0x50,0x87,0xa5,0x88,0x9e,0x5d,0x5b,0xe3,0xfd,
++            0x4f,0xbb,0xb9,0xfd,0xdd,0xdf,0xc0,0x4a,0x52,0xe8,0xaf,0x67,0xfb,0xf9,0x36,0xd3,
++            0x44,0x47,0x59,0xb7,0x1f,0x3c,0x2f,0xce,0x0d,0xc4,0xf4,0xa8,0xec,0x58,0x2d,0xbc,
++            0x4e,0xbd,0x41,0xa0,0xe2,0xfc,0x46,0x05,0x98,0x66,0xd9,0x0f,0xe3,0x3d,0x95,0x36,
++            0x80,0x85,0x64,0x71,0xfe,0xb2,0x8f,0x69,0x6e,0xdf,0x27,0xf5,0x36,0x9d,0x7d,0x24,
++            0x29,0x6e,0x03,0x5f,0x43,0x9f,0x7b,0x0b,0xcf,0x6e,0x17,0x75,0xdd,0x29,0x7f,0xfd,
++            0x00,0x0e,0xe0,0x40,0x2d,0x2f,0xcd,0x46,0xb3,0x50,0x5a,0xdf,0x23,0x60,0x58,0x19,
++            0x08,0x07,0x77,0x53,0xd3,0x11,0xab,0x50,0x47,0x8b,0x25,0x6b,0x57,0xd1,0x69,0x87,
++            0x7c,0x43,0xe1,0x07,0x58,0x2f,0xa9,0xda,0x3c,0x6b,0x3a,0x4b,0x05,0x9e,0xfb,0x08,
++            0x20,0xbc,0x81,0x01,0x6c,0x4d,0x39,0x2f,0xe0,0xb7,0xf7,0x6a,0x28,0x9f,0xbf,0x2e,
++            0x74,0xdb,0x0c,0x22,0x33,0xa4,0xfc,0x44,0xc5,0x94,0x70,0x16,0x30,0x60,0xe4,0xcb,
++            0xd6,0x0f,0x91,0x77,0xb6,0xa9,0x60,0x8f,0x59,0x28,0xc0,0x70,0xde,0x24,0x81,0x91,
++            0x26,0xf9,0xfb,0xad,0x2a,0x69,0x0c,0x32,0x6f,0xe7,0xaf,0x62,0x73,0xbf,0x4b,0x2e,
++            0x56,0x03,0x83,0x48,0x6c,0x3c,0x99,0xcd,0xab,0x4a,0x66,0x95,0x72,0xbc,0x1a,0xa4,
++            0x3b,0x8a,0xe0,0xe6,0x19,0xe8,0x0e,0x0c,0xc7,0x4a,0x2d,0xeb,0x92,0x22,0xad,0xfa,
++            0xe9,0xad,0x1d,0xfe,0x3d,0x65,0x72,0x47,0x29,0x09,0x0a,0x43,0xd4,0xcf,0xbb,0xf6,
++            0x61,0xc0,0xe3,0x49,0xa5,0x27,0xa4,0x28,0x45,0x46,0x9b,0x28,0x04,0x20,0x73,0x34,
++            0x62,0x9a,0xe5,0x77,0xbb,0xc6,0x65,0xae,0x28,0x98,0xd7,0xfd,0xdd,0x9f,0xc2,0x33,
++            0xdf,0xf0,0xf7,0x2a,0x97,0xda,0x2c,0x15,0xe6,0x41,0xf2,0x91,0x78,0xd7,0x5c,0x95,
++            0xe0,0x77,0x72,0xa3,0x28,0x18,0xd6,0x88,0xb4,0x42,0xd2,0x03,0x0e,0x64,0xf8,0x16,
++            0x63,0x8d,0x8b,0x54,0xa9,0x7a,0x2d,0x89,0x48,0x4a,0xd1,0x97,0xdc,0x87,0x75,0xe8,
++            0xe3,0x95,0x73,0x60,0x3c,0xa2,0x3b,0x7b,0x82,0x42,0x5b,0x3a,0xff,0x01,0x6e,0xaf,
++            0x50,0x45,0xbe,0x0a,0x87,0xbd,0x26,0xa4,0xe5,0x46,0xea,0xa2,0x91,0xf3,0xaa,0x14,
++            0x00,0x57,0xf5,0x96,0x3d,0x73,0x42,0xbf,0x65,0x1f,0x84,0xa5,0x8d,0x90,0x90,0x78,
++            0x21,0x89,0xe0,0x6e,0x51,0x24,0xb4,0xbb,0x7c,0xe6,0x72,0x56,0x7c,0x7f,0x9d,0x13,
++            0x21,0xab,0x0a,0xe1,0x93,0x9d,0x7c,0x11,0x37,0xec,0x5d,0xd9,0x4e,0xd3,0x40,0x22,
++            0xa0,0x5c,0x6f,0x9b,0xcb,0xc8,0xed,0xbe,0xbf,0x29,0xf3,0x15,0xee,0x66,0xc4,0xb9,
++            0x80,0x70,0x92,0xe7,0x3f,0x9e,0xea,0x03,0x8b,0xfe,0xa3,0xbe,0xce,0x69,0x5e,0xb3,
++            0x01,0x10,0x66,0xf3,0x6e,0xd3,0xfa,0xff,0x06,0xa2,0x3d,0x6f,0xd0,0xa0,0x35,0x53,
++            0xa6,0x7d,0xff,0xd4,0x36,0x21,0x6f,0xf5,0x66,0x41,0x6f,0x47,0xe3,0xb2,0x3e,0xda,
++            0x6b,0x78,0x81,0xfe,0xb5,0xce,0xc9,0xa8,0xeb,0x56,0x00,0xae,0xd1,0x7e,0x4c,0x1a,
++            0xc7,0x54,0xb4,0x07,0xc2,0xb4,0xa1,0xe3,0x90,0xd3,0xe6,0x54,0x46,0xb4,0xeb,0x1b,
++            0xac,0x10,0x78,0xff,0x6e,0xe5,0xf7,0x96,0xcc,0xe6,0x65,0x25,0x9b,0x85,0x55,0x0c,
++            0x0a,0x7e,0xec,0x67,0x9d,0x47,0x9b,0x48,0x4a,0x59,0x87,0xac,0x10,0xa1,0x7e,0x18,
++            0xdd,0x13,0x67,0xd6,0xa6,0x88,0x70,0x51,0xba,0xf8,0xa0,0xc6,0x08,0xb9,0xe1,0xa6,
++            0xf6,0x5f,0xaf,0x7c,0xed,0x82,0xda,0x3e,0xf9,0x5e,0x01,0xfc,0xf8,0x73,0x7f,0x19,
++            0x51,0x11,0x99,0xc2,0xbe,0x70,0x84,0xf2,0x81,0x2a,0xe4,0xe5,0x1e,0xcb,0x57,0x0e,
++            0x29,0x17,0x10,0xdd,0x38,0x31,0xbc,0x02,0x94,0x5f,0x3f,0xc2,0xdf,0x11,0xf9,0x9d,
++            0x3b,0x0e,0x27,0xa0,0xdf,0x2d,0x4e,0xb4,0x2f,0x66,0xfc,0x02,0x23,0xe0,0xfc,0xef,
++            0x84,0x5a,0x49,0xf8,0xf4,0x97,0x02,0xc1,0x93,0x6e,0x65,0x37,0x62,0xe4,0x07,0x2e,
++            0xa2,0x2d,0x0d,0x88,0x2b,0x2f,0xb1,0xd2,0x06,0x42,0x6e,0x3a,0xaf,0xe2,0x8f,0x97,
++            0xda,0xcf,0xd4,0x65,0x07,0xbc,0xde,0xc2,0x1f,0xd3,0xe4,0xde,0xd3,0xe1,0x1e,0x9a,
++            0x02,0xfe,0xb9,0x7c,0xb1,0xe5,0x3a,0x1d,0xe5,0xaa,0x60,0xa1,0x54,0x11,0xd7,0xc2,
++            0x26,0xb5,0x44,0x14,0x94,0x71,0x7c,0x35,0xc6,0xcb,0x5b,0xe0,0x8b,0x03,0xc2,0x1d,
++            0x7f,0x5a,0x0d,0xc7,0x6a,0x86,0xe1,0xa4,0xc4,0x33,0xf5,0x20,0x57,0xe8,0x6b,0xb3,
++            0xed,0x81,0x0b,0x48,0x59,0x2a,0xda,0xe5,0x1b,0x21,0xc3,0x84,0x1d,0x4c,0xf9,0x95,
++            0x73,0x06,0x99,0xae,0xf1,0x4a,0x4c,0xb0,0x99,0x55,0x81,0x5c,0xb7,0x09,0x75,0x0f,
++            0x0b,0xb0,0xe6,0x9a,0x41,0x60,0x99,0x0c,0x91,0x2c,0x67,0xa8,0x5e,0x0b,0x96,0x33,
++            0x38,0xfb,0x53,0xdc,0x9a,0x83,0x98,0x74,0x35,0x36,0x8d,0x1a,0x51,0xf1,0x8e,0xe7,
++            0x53,0x70,0x91,0x58,0x03,0xd4,0x65,0x08,0xc9,0x60,0xe1,0x58,0xb5,0x0a,0x6a,0xef,
++            0xef,0x83,0x9c,0xdd,0x75,0x2a,0x48,0x99,0x84,0x67,0x90,0x6a,0xb5,0x29,0x52,0x8a,
++            0xd0,0x82,0x0d,0xaf,0xc5,0xbd,0x5d,0xe5,0x24,0x7b,0xfb,0x8d,0xbf,0xa1,0xf3,0xc9,
++            0x8b,0xe4,0x63,0xbc,0x48,0x01,0x11,0x6f,0x1e,0x18,0x8d,0x58,0xb5,0x4b,0x0b,0x1f,
++            0xa0,0x04,0x95,0xc5,0x4a,0x32,0x7a,0x88,0x1d,0x13,0x9a,0x65,0x0f,0x5b,0x7e,0x0b,
++            0x87,0xf5,0x1b,0xc9,0xa1,0x6d,0x06,0x5d,0xe6,0x98,0x18,0x23,0xd7,0xb1,0xda,0x71,
++            0x46,0x13,0xf7,0x96,0x33,0x01,0x04,0x62,0xb8,0xae,0x19,0x07,0x8d,0x6b,0x7f,0x1b,
++            0x07,0x94,0x0c,0xf4,0xf3,0x0d,0x15,0xc1,0x53,0xb7,0x12,0x02,0x2c,0x71,0x55,0x7b,
++            0x9e,0xde,0xc3,0xe8,0x3a,0x15,0x84,0xe2,0x46,0x0c,0x0a,0x7a,0xf3,0xd8,0xb0,0x32,
++            0x2e,0x9b,0x04,0xf9,0x12,0xb2,0x1c,0x20,0xe0,0x21,0xb4,0xd9,0x7e,0x98,0x30,0x89,
++            0xda,0x1c,0x5d,0xb6,0x33,0xd9,0x25,0xe4,0xc2,0xdc,0x5b,0x61,0x96,0x5a,0xf5,0xdc,
++            0x9a,0xd4,0xc5,0x77,0x17,0x3f,0xe5,0x43,0x8c,0xa5,0xdd,0x25,0x22,0x30,0x69,0x8f,
++            0x86,0xd5,0x7d,0x2a,0xa7,0x45,0xfb,0x1b,0x8c,0x9a,0x9b,0x06,0x35,0xb7,0x5d,0x82,
++            0x89,0x27,0xec,0xce,0x7c,0x4c,0x8b,0xf7,0x93,0xde,0x7b,0x2a,0x3f,0xbd,0xee,0x4e,
++            0xad,0x4d,0x02,0x0d,0x32,0xb3,0x8a,0xc5,0xce,0x64,0x6a,0x51,0x53,0x5f,0x90,0x56,
++            0x58,0x40,0xed,0x8d,0xac,0x47,0xbf,0xa9,0x19,0xd5,0x1b,0x2a,0x07,0x57,0xe4,0x84,
++            0xf2,0x80,0x2f,0x80,0xb2,0x16,0xfb,0x3e,0xae,0x28,0x87,0x51,0x40,0x0a,0x58,0xe7,
++            0x0f,0x3c,0xbc,0x66,0x42,0x13,0x7c,0xee,0xc9,0x9d,0x88,0x70,0x95,0x0a,0xca,0x9c,
++            0x7b,0x10,0x90,0xd9,0x9e,0x62,0x01,0x1c,0x5c,0x86,0x9d,0xa0,0x8e,0x21,0xb8,0xcf,
++            0xa8,0xa4,0x47,0xbd,0xdc,0xba,0x2e,0x1a,0x4b,0x54,0xa9,0x74,0xee,0x51,0x11,0xa6,
++            0x44,0x94,0xb5,0x7f,0xc3,0x10,0xc5,0x1b,0xa7,0xc4,0x50,0x84,0x22,0x2b,0xb2,0x1f,
++            0xec,0xaf,0xbf,0x81,0xeb,0xbd,0xcb,0x20,0x3f,0xd2,0x02,0x00,0xdf,0x62,0xa0,0x9a,
++            0x95,0x95,0x18,0x4b,0xe8,0xdd,0xa9,0x56,0xa3,0x51,0xf0,0x2a,0x68,0x95,0x37,0xf0,
++            0x60,0x42,0x99,0x00,0xef,0xdd,0xd1,0x38,0x00,0x59,0x26,0x24,0x5d,0x6e,0xac,0x0a,
++            0xea,0x77,0x19,0xd2,0x93,0xd6,0x9d,0xf7,0xa3,0x02,0x00,0xb1,0xa8,0xfb,0x38,0x59,
++            0xf8,0x54,0x3b,0x46,0x56,0xf8,0x68,0x8f,0xbf,0xe5,0x92,0x04,0x7a,0xe5,0x92,0x69,
++            0x05,0x2f,0x67,0x70,0xc7,0xa6,0xe1,0x92,0xef,0x38,0x42,0xee,0xd3,0x17,0x3d,0x33,
++            0x79,0x8d,0xfa,0x1b,0x4f,0x9b,0x69,0xe5,0xea,0xc2,0xd3,0x85,0xf2,0x24,0x9b,0x33,
++            0x70,0xac,0x6e,0xe4,0x7a,0xed,0x21,0x81,0xf8,0xf6,0xc9,0x51,0xc1,0x25,0x82,0xce,
++            0x9a,0x0b,0x86,0x4b,0x99,0x26,0x4b,0x06,0xed,0xc8,0x2d,0x4c,0xef,0xcc,0x62,0xda,
++            0x8f,0xfc,0xac,0x1b,0xdf,0x8d,0x40,0xe9,0x71,0x56,0x3e,0x5e,0x7a,0x09,0xe0,0xf2,
++            0xf7,0x0a,0x24,0x0b,0x4c,0x4e,0xeb,0x0d,0x29,0x75,0x0a,0x2b,0x10,0x53,0x9b,0x02,
++            0xb1,0xf6,0x2b,0x8a,0x60,0xa7,0xa3,0x59,0xbd,0x09,0x77,0x3f,0xd1,0x07,0x3a,0x5d,
++            0xea,0xd9,0xe5,0xae,0xfa,0x8d,0x92,0x48,0x60,0x41,0xcd,0x46,0xda,0x0e,0xe6,0xdd,
++            0xde,0x6f,0x1e,0xa2,0xe6,0xac,0x23,0x06,0xec,0x0c,0x1e,0x57,0x5d,0xd7,0x3b,0xa1,
++            0x86,0xd2,0xfb,0xb2,0x73,0x21,0xa8,0x99,0x81,0xbf,0x83,0x49,0xd8,0x2c,0x22,0xb2,
++            0x74,0x84,0xda,0xae,0xf5,0xf2,0xf3,0x5d,0x4e,0xae,0x4d,0x7f,0xcb,0x2d,0x56,0x33,
++            0x26,0x11,0xfb,0x79,0x30,0x3e,0xb4,0x9b,0xe4,0xcf,0xaf,0x63,0xba,0xfa,0x37,0x72,
++            0x8d,0xac,0x4c,0xb4,0x23,0x2a,0x96,0x72,0x67,0xb9,0x56,0x56,0x91,0x2a,0x2c,0x05,
++            0x88,0x96,0xed,0x03,0x4c,0x73,0xd5,0x68,0x84,0x10,0xdd,0x9c,0x01,0xd6,0x75,0x61,
++            0x3d,0xe2,0x0b,0xcb,0x3c,0x51,0x9f,0xb8,0x5b,0xa3,0x9d,0x84,0xfa,0x8c,0x18,0xc5,
++            0xf3,0xe9,0x28,0x44,0xce,0x14,0x6a,0x34,0x02,0x8b,0xe2,0xec,0x99,0xf1,0x8c,0xf1,
++            0x75,0x18,0x2e,0xcb,0xfd,0x9e,0x24,0xc2,0x9c,0x4e,0x73,0x07,0xa3,0x81,0x6e,0x31,
++            0x40,0xc7,0x69,0x87,0x31,0xe2,0xaa,0x92,0xa9,0xa2,0x7d,0x6f,0x2f,0xcb,0xb2,0x21,
++            0x6f,0xc6,0xab,0xd1,0xd8,0xb1,0x77,0x82,0x40,0x18,0xfa,0x04,0x6f,0x65,0x7f,0xee,
++            0xdf,0x93,0x2d,0x09,0xab,0x07,0xb8,0x8c,0x1f,0x58,0x2f,0x1d,0xdb,0xa7,0xf6,0xbc,
++            0x0b,0xba,0x4e,0xbc,0xbd,0x34,0xa5,0x08,0x99,0x86,0xf8,0x78,0x7a,0xfb,0x49,0xb4,
++            0x1b,0xc7,0x78,0x7d,0x8b,0xab,0x4d,0x58,0x94,0xa5,0x22,0x6c,0x45,0x14,0x5e,0xb9,
++            0xcb,0xb8,0xf0,0x19,0x92,0x5b,0xb8,0xbf,0x02,0x3f,0xc5,0x95,0x85,0xd4,0x86,0xe8,
++            0xf2,0x5e,0x46,0xbe,0xd1,0xf9,0x57,0x97,0xcd,0x1d,0x3e,0x66,0x58,0xaa,0x36,0xa2,
++            0xc0,0x12,0x4f,0x2f,0xdb,0x71,0x64,0x40,0x80,0x39,0x29,0x3e,0xf8,0x3b,0x53,0xc8,
++            0x15,0x4b,0xb9,0xfa,0xd1,0x9b,0xea,0xd0,0x01,0x1a,0xa8,0xd3,0x0c,0x8b,0x7d,0xf4,
++            0x54,0xb2,0xae,0xc7,0x6b,0x8b,0xb3,0x86,0x21,0x1b,0x68,0xd9,0x98,0x64,0x7e,0xe0,
++            0x40,0x05,0xea,0xe4,0x55,0xe0,0xba,0x3d,0x42,0x08,0x50,0x92,0x76,0x23,0x12,0xa2,
++            0xe7,0xc3,0x28,0x08,0xf1,0x55,0xf8,0xfb,0x21,0xfc,0x9e,0x5f,0xd9,0x6a,0x33,0xc4,
++            0x6f,0xc6,0xdf,0x94,0xff,0x24,0x6f,0x18,0x40,0x5d,0xb4,0x34,0xe1,0xa6,0x39,0x59,
++            0x83,0xa2,0x1f,0xe6,0x7d,0xe3,0x2f,0x51,0xa5,0x50,0xbd,0xd5,0xd3,0xc8,0xba,0x7b,
++            0x00,0xae,0xb2,0x70,0xfd,0x67,0xd8,0x56,0xc3,0x65,0xeb,0x12,0xd6,0x84,0x1f,0xc4,
++            0xd4,0xc4,0x48,0xa6,0x9f,0x76,0xd2,0x94,0x74,0xc2,0xf8,0x52,0xd8,0xe7,0xb3,0x3c,
++            0x25,0x36,0xbb,0x05,0xea,0x09,0xb1,0xdf,0x26,0xdd,0x31,0x87,0xa7,0x1d,0xc2,0x2c,
++            0x52,0x0c,0x5e,0x51,0x60,0x0c,0x23,0x77,0x60,0xd7,0x4e,0x76,0x5a,0xeb,0xfb,0x70,
++            0xaf,0xed,0xfc,0x3c,0x18,0xe4,0x4c,0x2c,0xad,0x4b,0x8e,0x08,0x3a,0x65,0x52,0x0e,
++            0xed,0x08,0x8d,0xef,0x81,0xbb,0xfa,0x6e,0xce,0x8b,0x5a,0x01,0x79,0x55,0x1c,0xe9,
++            0x71,0x21,0xc2,0x01,0x4c,0xde,0xc7,0xaf,0x81,0x0a,0x67,0xd0,0x5f,0xe4,0x3c,0xe8,
++            0x09,0x06,0x43,0x95,0xbf,0x7d,0xb1,0xb0,0xcb,0x03,0x04,0x64,0x2d,0x81,0x54,0x76,
++            0x08,0xad,0xea,0x4e,0xd6,0x66,0x28,0xa2,0xe9,0x41,0x9a,0x70,0x98,0x18,0x33,0x66,
++            0x09,0x8c,0xb8,0x65,0x71,0x38,0xa1,0x0c,0x7c,0x19,0xa4,0xec,0x1f,0x42,0xa1,0x29,
++            0x71,0x05,0xef,0x60,0xf4,0xfb,0x2a,0x64,0x29,0xd5,0x15,0x1d,0x35,0x48,0xcb,0x39,
++            0x74,0xcd,0x39,0x5b,0xc0,0x34,0x81,0xff,0xb2,0xfc,0x49,0x8c,0x33,0x44,0xe4,0xdb,
++            0x41,0x2f,0x0d,0xf9,0xa1,0xf2,0x0c,0xe5,0x6a,0x6f,0x14,0x56,0xcc,0x23,0x01,0xe9,
++            0xbc,0xea,0xba,0x7e,0x79,0x6d,0x06,0x17,0x96,0x25,0x39,0xab,0x8b,0xf1,0x9e,0x33,
++            0x68,0xcd,0xb5,0x46,0xb2,0xb3,0x81,0xc1,0x9c,0x6d,0xcb,0xa0,0x0d,0xfd,0x29,0xf8,
++            0x24,0x9e,0x01,0x12,0x60,0xd1,0x9d,0xad,0x69,0xb6,0xb9,0xab,0x75,0x3e,0x1c,0x6e,
++            0xd1,0xd5,0xc3,0x37,0xaa,0xa6,0xcf,0x71,0xea,0xdc,0x63,0x62,0x56,0xb0,0x54,0x3c,
++            0x8b,0x98,0x93,0xe9,0xc9,0x60,0x1b,0x0d,0x92,0x53,0x6b,0x72,0x5f,0x37,0x5a,0x47,
++            0x86,0x89,0x0d,0x4d,0x94,0x60,0xf0,0x8c,0x1d,0x2b,0xcd,0x19,0x95,0x53,0x90,0xac,
++            0xcf,0x9a,0x1e,0xec,0x4d,0x22,0x7d,0x0d,0x67,0xe5,0x46,0x15,0x94,0x13,0x7c,0xc8,
++            0x50,0xa7,0xcf,0x65,0xc3,0x33,0x82,0xc8,0xe1,0xba,0xb5,0xac,0xa5,0xb9,0x13,0xd0,
++            0xde,0x22,0x89,0x1a,0x15,0x99,0x85,0x02,0xb4,0x24,0xa9,0x3a,0x76,0xb1,0x7d,0x88,
++            0xda,0x86,0x01,0xb7,0xba,0xbb,0xec,0xab,0x94,0x25,0x8d,0x54,0x9f,0xb0,0x2b,0x59,
++            0x0c,0xa4,0xd0,0xf1,0xbb,0x9a,0x10,0xfc,0xe3,0x44,0x87,0x40,0x70,0x99,0xa6,0xeb,
++            0x19,0xc1,0x95,0x0c,0xbd,0xfa,0xcb,0xd7,0x85,0x98,0x61,0x6a,0x5e,0x48,0x7e,0xf0,
++            0x29,0x9f,0xf6,0x5a,0x7d,0xb4,0xfd,0x3a,0x7f,0xa0,0x69,0x7a,0x57,0x2f,0x1f,0xec,
++            0x13,0xdc,0x50,0xeb,0x43,0x3c,0x4d,0x57,0xe8,0x36,0xcf,0x11,0x9d,0x79,0x5f,0xb9,
++            0x18,0xfa,0x29,0x4f,0x9e,0x4d,0xe8,0x04,0x0e,0x0c,0x44,0x1d,0xdb,0xff,0xad,0x7f,
++            0x9d,0x42,0xce,0x2e,0x92,0x24,0x62,0x21,0x18,0xbb,0xf1,0x84,0x86,0xdf,0xa1,0x7e,
++            0x6a,0x22,0x90,0x11,0x72,0xde,0x83,0x3b,0xc3,0x49,0x78,0x0b,0x75,0x0f,0x1b,0xc7,
++            0x15,0xff,0x89,0x67,0xf1,0x77,0x31,0xdd,0xc4,0x00,0x4e,0x25,0x53,0x6c,0x09,0xe2,
++            0xa3,0x00,0xf1,0x97,0x19,0x72,0xef,0xc1,0xc9,0x4c,0xd9,0x0a,0xd9,0x0f,0x80,0xb0,
++            0x05,0xb5,0xfe,0xe0,0x14,0x25,0x30,0x3f,0xf5,0xf9,0xcb,0xec,0xf7,0xe2,0x33,0x17,
++            0xdd,0x0f,0x7c,0x27,0x4c,0x2a,0xe5,0x92,0xc1,0xb9,0x18,0x95,0x8a,0x98,0x81,0x80,
++            0x87,0x0b,0xb8,0x36,0xc5,0x29,0x29,0xe3,0x1f,0x79,0xd5,0x25,0xda,0x27,0xcb,0x0e,
++            0x72,0xfb,0xf7,0xf1,0x95,0x06,0x20,0x02,0xd6,0x48,0xc3,0x74,0x86,0x6e,0x05,0x90,
++            0x3b,0xa9,0xba,0xbe,0x10,0xaa,0x4b,0xac,0xa1,0x39,0xba,0xee,0xa1,0xe4,0x10,0xde,
++            0xd0,0xf4,0xf2,0x98,0x3b,0x9c,0xdd,0x5a,0x0a,0x96,0xe4,0xaf,0x32,0xdf,0xbb,0x24,
++            0x77,0x48,0xb9,0x8f,0x10,0x7b,0xeb,0x0d,0x4a,0x49,0xd9,0xcf,0x99,0x7a,0x24,0x77,
++            0x06,0xbd,0xd3,0x18,0x9d,0x3b,0x63,0xbb,0xcc,0x81,0x9a,0x23,0x3d,0x9f,0xe9,0x33,
++            0xdf,0xbc,0x1e,0xc8,0x18,0x29,0x32,0x28,0xf7,0xc7,0x52,0x2b,0x7e,0x2e,0xe5,0x7c,
++            0x89,0xf1,0xf4,0x3d,0xb8,0xa6,0x25,0xfa,0x4a,0xb2,0x62,0x01,0x78,0x0d,0x63,0x87,
++            0x57,0xd3,0xfd,0x2d,0x39,0x4b,0x57,0x8b,0xe8,0xb1,0x8f,0x18,0xe9,0x9e,0x31,0xa9,
++            0x83,0x00,0x96,0x6c,0xbd,0x6d,0x63,0x59,0x6a,0x70,0x9a,0x1b,0xae,0x66,0xa0,0x82,
++            0x74,0xbd,0xe4,0x86,0x56,0x3f,0x54,0xdd,0x2a,0xfa,0x9e,0xa0,0xd3,0x76,0xb3,0xa1,
++            0x40,0xbe,0xac,0x7d,0x13,0x4a,0x1d,0x32,0x64,0xab,0xe4,0x36,0x53,0x83,0x1f,0x05,
++            0xa3,0x12,0x31,0xfa,0x13,0x69,0x5b,0x70,0xc4,0x1c,0xc5,0x3c,0x93,0x52,0xad,0xe3,
++            0xd7,0xbc,0x89,0x7d,0x83,0xa8,0x47,0xb4,0x42,0x11,0xa5,0xe5,0xf9,0x7c,0xbb,0xa2,
++            0x02,0x19,0xbc,0x46,0xdc,0x9b,0x55,0x92,0xe0,0x70,0x88,0x01,0x74,0xae,0x1c,0x5d,
++            0x17,0xb8,0xcc,0xd4,0x33,0xb8,0x5c,0x0d,0x6b,0x17,0x2c,0xe1,0x3b,0xfc,0x38,0x3c,
++            0xa2,0x57,0x05,0x45,0xcf,0x36,0xc4,0x03,0xe6,0x46,0x1a,0x61,0xd1,0xe2,0x01,0x16,
++            0x61,0x17,0xad,0x62,0x50,0x38,0x10,0xf6,0x63,0x69,0x4d,0xae,0x0e,0xcb,0xa2,0xea,
++            0xd7,0x7b,0xa6,0x75,0x30,0xe3,0x46,0x77,0xcd,0x87,0xf6,0x0c,0x2e,0xf5,0x99,0x67,
++            0xdc,0x9a,0x89,0x8e,0xb6,0x3b,0x05,0x83,0x5a,0xfb,0xc4,0xb9,0xda,0xf4,0x61,0xeb,
++            0x5f,0x97,0x87,0x70,0xa8,0x7a,0x16,0xcf,0x17,0x18,0xef,0x2f,0xfd,0xb0,0xdf,0x86,
++            0x2d,0xb4,0x38,0x9c,0x34,0x37,0xa7,0x3b,0xcb,0x6b,0x60,0x39,0xd2,0x98,0x4e,0xcc,
++            0x60,0x36,0x56,0x8e,0x9b,0x30,0x0f,0xfa,0x8f,0xa3,0xfd,0x92,0xab,0x3e,0x70,0x1c,
++            0xa6,0xeb,0x6e,0x9e,0xb8,0x96,0xcd,0x7c,0x60,0x2f,0x73,0xb2,0x8e,0x21,0x79,0x1d,
++            0xe8,0xe1,0xbf,0x8f,0x36,0x32,0x6d,0x17,0x89,0x8e,0x48,0xaf,0x67,0x83,0x07,0xdd,
++            0xe3,0x55,0xa7,0x55,0xbd,0x3f,0xe0,0x1b,0x88,0x15,0x1f,0x80,0x7a,0x13,0x28,0x07,
++            0xb1,0x84,0xa0,0xfb,0x1c,0xe2,0x0a,0xc0,0xc6,0xc3,0x06,0xd7,0xbc,0xa4,0x07,0xe1,
++            0x27,0x3c,0x38,0x94,0x95,0x22,0x40,0xb0,0x67,0x73,0xd9,0x38,0x85,0x95,0x23,0x78,
++            0x5d,0xdf,0xec,0x00,0x14,0x3f,0xf6,0x41,0x87,0x7d,0xef,0x15,0x94,0xae,0x57,0xb2,
++            0x71,0x80,0xf3,0x39,0x36,0x78,0x03,0xd1,0x47,0xc7,0x9e,0xc6,0x49,0x71,0x00,0x1d,
++            0xb9,0x79,0xf0,0xe7,0xff,0x1e,0xaf,0x62,0x62,0xc2,0x70,0x21,0x72,0x8a,0x57,0xb0,
++            0x85,0x79,0x37,0x14,0x11,0x8d,0x00,0xf6,0x65,0x70,0x9e,0x07,0x54,0x37,0x19,0xc1,
++            0x5b,0xd9,0x99,0x63,0xe1,0x82,0x51,0x23,0xa5,0x39,0x61,0x14,0xb7,0x8a,0x14,0x3c,
++            0x24,0x81,0x9e,0xbf,0x75,0x7a,0x21,0xfe,0x45,0xc3,0x39,0x0a,0xe6,0xe4,0x95,0xab,
++            0x28,0x25,0x82,0xf3,0x3e,0x13,0x2d,0x48,0xce,0xcb,0x5a,0xa4,0x7e,0x3e,0x3a,0x7c,
++            0x0b,0x83,0x34,0x5e,0x90,0x24,0x65,0xca,0x49,0xc6,0xd2,0xb8,0xa1,0xa8,0x39,0xeb,
++            0xdc,0x91,0x27,0xf7,0x9c,0xe8,0xf6,0xc9,0x4e,0x82,0xcc,0xd2,0xdc,0xe4,0x2b,0x04,
++            0x09,0x5f,0x4c,0xe0,0x7c,0x7d,0x5b,0x9f,0x8c,0x89,0xdb,0x9f,0x83,0xe6,0xcd,0xa0,
++            0xe7,0xd4,0x1a,0x46,0xe3,0xe3,0x6c,0x08,0x6f,0x6e,0x73,0x7f,0x7c,0xce,0x30,0x5b,
++            0xac,0x8e,0xf1,0xdc,0xf1,0xe2,0x60,0x7b,0x6e,0x6d,0xbe,0x6f,0x59,0xc6,0x1b,0xc9,
++            0x8f,0xf3,0xba,0xf0,0x98,0x7d,0x13,0x68,0xfa,0xc3,0xf5,0x6d,0xce,0xed,0x94,0xa0,
++            0x0d,0x87,0x50,0xbd,0x33,0x52,0xbb,0x16,0xf0,0xc5,0x20,0x7d,0xd3,0xad,0x80,0x72,
++            0x20,0x9f,0xcc,0x77,0xf2,0xb0,0x4c,0x20,0x46,0x60,0x6b,0xf6,0xf6,0x57,0xec,0xf4,
++            0x4c,0xe0,0x29,0xe4,0xde,0x37,0x44,0xb0,0x69,0x5a,0x53,0x4c,0x51,0x0a,0xb5,0x9c,
++            0x98,0x89,0x82,0x10,0xdf,0x14,0x65,0xba,0xa4,0x5f,0x98,0xd5,0x57,0x97,0x35,0xa6,
++            0x4c,0xe2,0x0e,0xa1,0x69,0x56,0x39,0x51,0xe3,0x39,0x42,0xc5,0x02,0x4c,0x5a,0x07,
++            0xa9,0x12,0x24,0x42,0x1d,0x32,0xe7,0x66,0x6d,0x9c,0x4b,0x69,0x89,0x29,0xa0,0xa1,
++            0x6c,0x17,0x94,0x54,0x3e,0xd1,0xeb,0x0d,0x33,0x02,0x9b,0x88,0xa5,0xfd,0x65,0x83,
++            0xa2,0x34,0x85,0x87,0x18,0x3b,0x4f,0x01,0x85,0x26,0x14,0x19,0x7b,0x0b,0x92,0xa0,
++            0xe4,0xfb,0xd5,0x87,0xbf,0xb8,0xfc,0x99,0x90,0x42,0x79,0x30,0x77,0xd7,0x7e,0x92,
++            0x1f,0xea,0xf8,0xbd,0x30,0x13,0x47,0x28,0x69,0xbc,0xd6,0x18,0xb8,0xf5,0x1c,0x65,
++            0xd9,0x96,0x0f,0x84,0xa1,0x0d,0x5e,0xb8,0x6c,0xd4,0xf6,0x26,0xff,0x3e,0x9f,0x7a,
++            0x0f,0x69,0x95,0x8e,0x39,0xac,0x6d,0xbb,0x4f,0x9b,0xcc,0xd4,0x71,0x6c,0x0f,0x92,
++            0x44,0xea,0xf1,0x90,0xaf,0xf5,0x45,0xdb,0xb9,0x99,0xfc,0xdd,0x84,0xf2,0x81,0x0a,
++            0x2a,0x3c,0x8e,0x0c,0xbd,0xf8,0xa9,0x1e,0x51,0x1a,0x5a,0x2e,0xc7,0xbd,0x14,0xa8,
++            0x8c,0x9b,0x86,0xbc,0x19,0xd3,0xfe,0x93,0x78,0x29,0xd2,0x7b,0xf6,0x9d,0x2d,0xef,
++            0x2c,0x62,0x8f,0xc8,0x3d,0xb1,0xae,0xeb,0x0f,0x61,0xdb,0xfa,0x77,0xae,0xc0,0x34,
++            0x52,0x90,0xb6,0x8c,0x1a,0x39,0xaf,0x7f,0x97,0x76,0xd3,0xe7,0x77,0xdd,0x00,0x43,
++            0x04,0x24,0x20,0x77,0xb3,0xa3,0xd0,0x9c,0x88,0xc8,0x96,0x11,0xb9,0x81,0x08,0x54,
++            0xef,0x9e,0xf0,0x33,0xec,0x2e,0x60,0x14,0xc3,0x65,0xa6,0x10,0x57,0xd9,0x5f,0x01,
++            0x08,0x68,0xb7,0xf6,0x1c,0xff,0x19,0xc3,0x81,0x46,0x3d,0xb7,0x8c,0x6a,0x09,0x11,
++            0x84,0xe4,0x19,0xe9,0x75,0xd8,0x92,0x53,0x80,0x47,0xae,0xdd,0x0f,0x2e,0xa8,0x7d,
++            0xe9,0x40,0x95,0xe5,0x30,0xde,0x30,0x20,0xe0,0x99,0xc9,0xc2,0x1e,0xc9,0xec,0x32,
++            0xf4,0x8e,0xc8,0xd6,0x1a,0x98,0xc8,0xf2,0x42,0xa2,0xc2,0x8b,0x55,0x5c,0x7b,0xf1,
++            0x2c,0xa9,0x95,0xe5,0xb8,0x25,0x29,0x46,0x3f,0x49,0xcb,0x85,0x82,0xcd,0xa5,0x6c,
++            0x68,0x43,0xf1,0x85,0x64,0x28,0x63,0x93,0x41,0x4f,0xaa,0xf1,0xf8,0x0c,0xfb,0x08,
++            0x08,0x20,0x93,0xe1,0x74,0x83,0x6a,0xac,0x6b,0x54,0x6d,0xcc,0x4c,0x73,0xdc,0x18,
++            0x0f,0x0a,0xb9,0xc9,0x1f,0x40,0xf6,0xaa,0x49,0x41,0xd8,0x7c,0x09,0x6d,0xf5,0xe2,
++            0x88,0x26,0xd0,0x24,0x60,0x30,0x73,0x2a,0x9d,0x47,0x26,0x4b,0x55,0xec,0x3c,0x79,
++            0xdb,0x10,0xbf,0x0e,0xf5,0xf3,0x1c,0xd1,0xdb,0x06,0x1d,0xd5,0x65,0x26,0x78,0xf8,
++            0xa4,0xa3,0x76,0x2e,0x59,0xf3,0xa0,0x0a,0x09,0x93,0x12,0xb8,0x10,0x2d,0x48,0xa7,
++            0x2f,0x4f,0xb2,0xde,0x12,0xf0,0x50,0x38,0xe8,0x4b,0x21,0xfe,0x5a,0x88,0xe7,0x2b,
++            0x07,0xd8,0xbb,0x6a,0xf9,0xde,0x2b,0x0b,0x89,0xbe,0xb3,0x2d,0x36,0x63,0x02,0x13,
++            0x6a,0xa0,0xf3,0x0d,0x9f,0x20,0x53,0xcb,0x3e,0x40,0xe3,0x3a,0x0d,0x03,0x54,0x31,
++            0x04,0x45,0x3b,0xc3,0xe6,0x38,0x14,0x24,0x49,0x22,0x54,0xc9,0x14,0x3e,0x08,0xfb,
++            0xa0,0x1c,0x1c,0x69,0x31,0x70,0x64,0x97,0x9c,0x5e,0xa4,0x4f,0x90,0x12,0x98,0xaa,
++            0xd1,0x69,0x87,0xfa,0x66,0xcd,0x75,0x01,0xa6,0xdf,0x05,0x81,0x51,0xd3,0x57,0xb9,
++            0xc9,0x09,0x61,0x15,0x4d,0x13,0x8d,0xc3,0x12,0xce,0xe6,0x72,0x0c,0xc5,0xc0,0xa0,
++            0x3e,0x9f,0x6c,0xec,0x22,0x7b,0xa1,0x92,0xc1,0x52,0x38,0x64,0x8e,0x54,0x9f,0x2e,
++            0xfe,0x9f,0xcd,0x32,0xb6,0x64,0xa7,0x12,0xc2,0xdf,0xe4,0x07,0x07,0xd1,0xc1,0xfc,
++            0x5d,0x9b,0xc4,0x23,0xa2,0x79,0x5d,0x4f,0x43,0xdc,0x79,0x67,0xf3,0xb3,0x36,0x8e,
++            0x20,0x19,0x94,0xcf,0xd4,0xf1,0xda,0x13,0x61,0x5f,0x32,0xc8,0x75,0x82,0x7b,0x78,
++            0xcc,0xbb,0x2a,0xce,0xbb,0x3e,0xba,0x3b,0x31,0x52,0x2d,0x36,0x79,0x98,0x75,0x61,
++            0x21,0x17,0xf6,0x1e,0x38,0x86,0xde,0x98,0x43,0x54,0xfd,0x42,0x5d,0x15,0xc9,0xc3,
++            0x11,0x06,0x8f,0x52,0xdb,0xaa,0xd1,0x59,0xb6,0xcb,0x28,0x36,0x07,0xa7,0x37,0x72,
++            0xde,0x1b,0xb7,0x2f,0xe9,0xbb,0xe0,0x4b,0xc8,0x6b,0xa0,0x22,0x06,0xe6,0xa6,0xf7,
++            0x0e,0x10,0x56,0x8b,0xc7,0x8a,0x27,0x96,0xc9,0x39,0x65,0xd0,0x86,0x8d,0xea,0x9a,
++            0xaf,0x11,0x62,0xac,0xbb,0xbb,0x52,0x9f,0xca,0xd5,0x61,0xc5,0x90,0x39,0x7f,0x8b,
++            0x09,0x12,0x38,0xb3,0x68,0xe1,0xe8,0x0b,0xce,0x58,0x47,0x9f,0x09,0xcc,0x27,0x28,
++            0x28,0x1d,0xef,0x1d,0xab,0x53,0x5b,0x1b,0x94,0xd6,0xe5,0x41,0x10,0x1b,0x81,0x64,
++            0xfb,0x9b,0x86,0x2e,0x49,0xbb,0xdc,0xb0,0x25,0xca,0x1c,0xb9,0x55,0x80,0x90,0xd5,
++            0xc7,0x03,0xa9,0x65,0x21,0xee,0x18,0x5c,0x41,0x18,0xe1,0x60,0xf0,0x61,0x07,0x65,
++            0xf8,0xcd,0x7d,0x74,0xac,0xed,0x37,0xa7,0xef,0x44,0x71,0xc6,0xde,0xa3,0x21,0x92,
++            0xfa,0xe3,0x39,0x50,0xae,0xe7,0xfc,0x41,0x36,0x7c,0x41,0xb3,0xf6,0x2e,0x7a,0xaa,
++            0xce,0x4b,0x70,0xd7,0x01,0x0f,0xc4,0x1d,0xe5,0x85,0x17,0x26,0x5a,0x8a,0x92,0x14,
++            0x4b,0xc9,0xda,0x66,0xd4,0x0a,0x6f,0x71,0x2c,0x14,0x80,0x52,0x51,0x14,0xc9,0x4f,
++            0xb5,0xa2,0x99,0x43,0x7f,0xfc,0xb1,0xdf,0x7a,0x6d,0xd1,0x66,0x5b,0xec,0xa9,0xbb,
++            0x17,0x48,0x49,0x24,0x34,0x24,0x51,0x8a,0xf7,0x5c,0xc4,0x8a,0xe7,0x3c,0xe2,0xc3,
++            0x80,0x8e,0x1c,0xe6,0x94,0x6e,0xef,0xaa,0x7b,0x29,0xeb,0x78,0xf9,0x86,0x2e,0xf8,
++            0x29,0x04,0x6a,0x43,0xe4,0xa1,0xd7,0xd7,0x35,0x92,0x65,0x3f,0x5b,0xa0,0x2f,0x0c,
++            0x2d,0x02,0xe1,0x1c,0xf5,0xa5,0x4e,0xc1,0xca,0x1a,0xd1,0x27,0xdd,0x5a,0x72,0x08,
++            0x2a,0xca,0x2f,0x20,0xf4,0xea,0xce,0xd2,0xdd,0xd0,0xa5,0xbb,0xd8,0x2d,0xca,0x52,
++            0x8b,0x8c,0xd4,0xbd,0x92,0xa1,0xc0,0x79,0x01,0xc4,0x40,0xea,0x68,0x33,0x2a,0x65,
++            0x07,0xe1,0x7a,0x2c,0x2c,0x19,0xe9,0x44,0x37,0x8d,0x3c,0x7b,0x59,0xff,0x8b,0x4f,
++            0xaa,0xe0,0x18,0x68,0x3f,0x51,0x55,0xa3,0xc7,0x3b,0x33,0xab,0xde,0xed,0x43,0x99,
++            0x72,0x05,0x11,0xb7,0x79,0xe0,0xb4,0x83,0x4d,0xc7,0xfb,0x7b,0xa6,0x5f,0xfb,0x9e,
++            0x22,0x20,0x7b,0x87,0xb4,0xf0,0x1b,0xd8,0xbd,0x92,0x57,0x58,0x50,0x8c,0xb3,0x00,
++            0x2d,0x9b,0x4c,0xa9,0x11,0x3c,0xbe,0xaa,0xe5,0xbc,0x7c,0x36,0x09,0x8c,0x07,0xa7,
++            0x29,0x3f,0x7a,0x87,0x37,0xbc,0xaf,0xd3,0xd7,0x89,0x0a,0xe8,0xc7,0xd8,0xa9,0x17,
++            0xd3,0xa8,0xd3,0xa2,0xd6,0xfc,0xad,0xc0,0xf2,0xbf,0xab,0xd5,0x9d,0xfe,0xa4,0x82,
++            0x8b,0x9a,0xde,0x59,0xc9,0x39,0xb4,0x9f,0xa4,0xd2,0xcc,0xde,0x85,0x49,0xc8,0x10,
++            0x84,0x9b,0x8c,0x76,0x25,0xb6,0x1c,0xb3,0xca,0xd8,0x53,0xd2,0x57,0x34,0x0d,0x01,
++            0x22,0x98,0x06,0x39,0x92,0xf7,0x7d,0x36,0x47,0x29,0xad,0x04,0x2b,0x6b,0x55,0x77,
++            0x25,0x9f,0x6b,0xdf,0xd4,0xa1,0x37,0x0d,0x44,0x96,0xbd,0x30,0xc4,0xd0,0x8e,0xba,
++            0xa9,0xf9,0xb0,0xbb,0x3a,0xb9,0x54,0x36,0x6f,0xca,0xa4,0xa4,0x7a,0xfb,0xe7,0x1c,
++            0x2b,0x92,0xaa,0xde,0x75,0x4c,0x60,0x58,0x69,0x64,0xde,0x0c,0x4e,0xf4,0xe7,0x37,
++            0x81,0xd8,0xe7,0xed,0x33,0x3c,0x00,0x67,0xa4,0x80,0xa7,0x2b,0xfe,0x93,0xbd,0x1f,
++            0xc3,0x3e,0x39,0x1b,0xa8,0xab,0x0d,0x8b,0x2e,0x74,0xbd,0x5d,0xd9,0x70,0x92,0xb8,
++            0x8d,0x9a,0x9e,0xe9,0x5d,0xba,0xf8,0x3a,0x54,0xdf,0x4e,0x7c,0x0e,0xee,0x6a,0x38,
++            0x8e,0x17,0x96,0xf9,0x5c,0xbf,0x72,0x3f,0x7e,0x45,0xda,0xbe,0x7b,0x93,0x6f,0x6d,
++            0x0f,0x16,0x9f,0xeb,0xdd,0xa8,0x27,0x36,0xab,0x46,0x4f,0x9f,0x7e,0x78,0xe8,0x8b,
++            0x0f,0x90,0x97,0xfb,0xb9,0x46,0x71,0x3e,0xe0,0x25,0x6f,0xb8,0xdb,0x91,0x40,0x3f,
++            0x08,0x6c,0x7f,0xe6,0x34,0xdd,0x78,0xd1,0xc3,0x50,0x98,0xa0,0x52,0x99,0x30,0x01,
++            0x5d,0xf6,0x37,0x8f,0xee,0x60,0x70,0xf2,0xe0,0x02,0x08,0xb6,0x3f,0xa0,0x29,0xc3,
++            0x7d,0x01,0x6d,0x9e,0x91,0xa2,0xd1,0x34,0x77,0x4c,0x00,0x0b,0x64,0x37,0x09,0x10,
++            0xd5,0x0d,0x25,0x6e,0x4f,0xdc,0x79,0x91,0xcd,0xce,0xc3,0x20,0x72,0x06,0xbf,0xbf,
++            0xfd,0xfb,0x3f,0xbb,0xed,0xdb,0xaf,0x9f,0xbd,0xbb,0x2f,0x9b,0xad,0x9b,0xb7,0xaf,
++            0xfc,0xfa,0x37,0xab,0xec,0xda,0xa7,0x8f,0xbc,0xba,0x27,0x8b,0xac,0x9a,0xbe,0xbe,
++            0x7d,0xf9,0x3e,0xba,0x6d,0xd9,0xae,0x9e,0x3d,0xb9,0x2e,0x9a,0x2d,0x99,0xb6,0xae,
++            0x7c,0xf8,0x36,0xaa,0x6c,0xd8,0xa6,0x8e,0x3c,0xb8,0x26,0x8a,0x2c,0x98,0x6a,0x8e,
++            0xf4,0x49,0x12,0x7e,0x2b,0xbd,0x6a,0x88,0xb7,0xf7,0xc8,0xd3,0xfb,0x29,0xf2,0x6a,
++            0x3a,0xdf,0x3f,0xfa,0x9c,0xaa,0x1e,0xda,0x6d,0x4f,0x65,0x4e,0xfa,0x94,0x5a,0x93,
++            0xeb,0xf5,0x7b,0x05,0x3f,0x31,0x73,0x89,0xc4,0xc1,0xf3,0x6d,0x76,0x67,0xf3,0xf1,
++            0x2d,0x80,0x0b,0xfd,0xdb,0x65,0x17,0x47,0x68,0xc1,0xe3,0x19,0x5b,0x88,0xbd,0xb7,
++            0xf5,0xf3,0x3d,0xb3,0xe5,0xd3,0xad,0x97,0xb5,0xb3,0x2d,0x93,0xa5,0x93,0xb5,0xa7,
++            0xf4,0xf2,0x35,0xa3,0xe4,0xd2,0xa5,0x87,0xb4,0xb2,0x25,0x83,0xa4,0x92,0xbc,0xb6,
++            0x75,0xf1,0x3c,0xb2,0x65,0xd1,0xac,0x96,0x35,0xb1,0x2c,0x92,0x25,0x91,0xb4,0xa6,
++            0x74,0xf0,0x34,0xa2,0x64,0xd0,0xa4,0x86,0x34,0xb0,0x24,0x82,0x24,0x90,0x24,0x95,
++            0xad,0x9d,0x11,0x73,0x14,0xbd,0x11,0x1f,0x68,0x30,0x11,0x20,0x58,0xa4,0xf7,0xb4,
++            0xae,0x13,0x4c,0x54,0x1c,0xe6,0xdc,0x10,0xce,0x58,0xa4,0xe4,0x31,0x7e,0xe2,0x7e,
++            0x41,0xc4,0x7e,0xfb,0xd0,0xa3,0xd5,0x41,0x7e,0x13,0x05,0x27,0x70,0xfa,0xba,0x90,
++            0x2c,0x1f,0xcd,0x62,0x95,0xbe,0x99,0x0e,0xed,0x33,0x0d,0x31,0x87,0x2b,0xbb,0x3f,
++            0xdd,0xeb,0x3b,0x3b,0xcd,0xcb,0xab,0x1f,0x9d,0xab,0x2b,0x1b,0x8d,0x8b,0xb3,0x2f,
++            0xdc,0xea,0x33,0x2b,0xcc,0xca,0xa3,0x0f,0x9c,0xaa,0x23,0x0b,0x8c,0x8a,0xba,0x3e,
++            0x5d,0xe9,0x3a,0x3a,0x4d,0xc9,0xaa,0x1e,0x1d,0xa9,0x2a,0x1a,0x0d,0x89,0xb2,0x2e,
++            0x5c,0xe8,0x32,0x2a,0x4c,0xc8,0xa2,0x0e,0x1c,0xa8,0x22,0x0a,0x0c,0x88,0x6e,0x88,
++            0x43,0xfc,0xdf,0x0c,0x9f,0x3e,0x96,0x48,0xf6,0x1a,0x56,0xd9,0x79,0x39,0xee,0xa7,
++            0x0d,0x57,0xcb,0x7a,0x1d,0xc4,0x1e,0x45,0x79,0xe2,0xb9,0x4a,0x5d,0x7f,0x03,0x89,
++            0x2b,0x14,0xf1,0xc7,0x1b,0x21,0x88,0xa0,0xcc,0x81,0x28,0x9d,0xb4,0x61,0x4f,0xeb,
++            0x42,0x92,0xa9,0x49,0x1a,0xbe,0x51,0x55,0x69,0x60,0x97,0xda,0x04,0x74,0xb9,0x37,
++            0xd5,0xe3,0x39,0x33,0xc5,0xc3,0xa9,0x17,0x95,0xa3,0x29,0x13,0x85,0x83,0xb1,0x27,
++            0xd4,0xe2,0x31,0x23,0xc4,0xc2,0xa1,0x07,0x94,0xa2,0x21,0x03,0x84,0x82,0xb8,0x36,
++            0x55,0xe1,0x38,0x32,0x45,0xc1,0xa8,0x16,0x15,0xa1,0x28,0x12,0x05,0x81,0xb0,0x26,
++            0x54,0xe0,0x30,0x22,0x44,0xc0,0xa0,0x06,0x14,0xa0,0x20,0x02,0x04,0x80,0xdf,0xe4,
++            0xe5,0x90,0xa1,0x82,0x62,0x6c,0x4f,0xc0,0xc6,0xe8,0xa2,0x54,0xf7,0x85,0x77,0xd0,
++            0x36,0x0d,0x28,0x6a,0xe3,0xa7,0x40,0x16,0x43,0xc2,0x78,0x1a,0x9c,0xe0,0xd9,0x27,
++            0xf7,0xb4,0x7e,0xf3,0xe3,0xe2,0x0e,0x41,0x85,0xe2,0xeb,0xd8,0x77,0xa3,0x91,0xfd,
++            0x95,0xce,0xa1,0x5a,0xf6,0xc3,0xc5,0x53,0xc9,0x34,0x3e,0x32,0xd3,0x7a,0x9f,0xbd,
++            0xf9,0x7b,0x1f,0xb9,0xe9,0x5b,0x8f,0x9d,0xb9,0x3b,0x0f,0x99,0xa9,0x1b,0x97,0xad,
++            0xf8,0x7a,0x17,0xa9,0xe8,0x5a,0x87,0x8d,0xb8,0x3a,0x07,0x89,0xa8,0x1a,0x9e,0xbc,
++            0x79,0x79,0x1e,0xb8,0x69,0x59,0x8e,0x9c,0x39,0x39,0x0e,0x98,0x29,0x19,0x96,0xac,
++            0x78,0x78,0x16,0xa8,0x68,0x58,0x86,0x8c,0x38,0x38,0x06,0x88,0x28,0x18,0xdf,0xf7,
++            0xcf,0x53,0xda,0x8c,0x1d,0xf0,0xb6,0x2f,0x48,0x31,0x13,0x0a,0xd9,0x6b,0x86,0x64,
++            0x6c,0x8d,0x51,0x60,0x7d,0xa9,0xaa,0xbe,0x6f,0xa6,0xe3,0x10,0xfa,0xa8,0xc4,0x0f,
++            0xa1,0x74,0x99,0xed,0xb8,0x27,0x36,0xaf,0xef,0xbc,0x1f,0xdf,0xcc,0x1c,0x49,0x19,
++            0x8c,0xcb,0x6b,0xdf,0xb0,0x7c,0x63,0x3e,0xc9,0x32,0xeb,0x32,0x95,0xa7,0x9d,0xb5,
++            0xf1,0x73,0x1d,0xb1,0xe1,0x53,0x8d,0x95,0xb1,0x33,0x0d,0x91,0xa1,0x13,0x95,0xa5,
++            0xf0,0x72,0x15,0xa1,0xe0,0x52,0x85,0x85,0xb0,0x32,0x05,0x81,0xa0,0x12,0x9c,0xb4,
++            0x71,0x71,0x1c,0xb0,0x61,0x51,0x8c,0x94,0x31,0x31,0x0c,0x90,0x21,0x11,0x94,0xa4,
++            0x70,0x70,0x14,0xa0,0x60,0x50,0x84,0x84,0x30,0x30,0x04,0x80,0x20,0x10,0x7d,0x81,
++            0xc3,0x96,0xb3,0x79,0xd5,0x13,0x64,0x4f,0x6c,0x90,0x24,0x24,0x75,0x0e,0x54,0x54,
++            0x91,0xd0,0x8c,0x6b,0x24,0x0a,0x63,0xf0,0xd9,0xcb,0x43,0x49,0x8a,0x0e,0x2d,0x2c,
++            0x07,0x12,0xdd,0x79,0x90,0x69,0x75,0x99,0x97,0xf6,0x8f,0x45,0xd0,0x0d,0x17,0x60,
++            0xd8,0x3c,0xf8,0x6f,0xb5,0xf1,0x8c,0x66,0x9a,0xdf,0x42,0x48,0x0a,0x0c,0x9b,0x3d,
++            0xd9,0x6b,0x1b,0x39,0xc9,0x4b,0x8b,0x1d,0x99,0x2b,0x0b,0x19,0x89,0x0b,0x93,0x2d,
++            0xd8,0x6a,0x13,0x29,0xc8,0x4a,0x83,0x0d,0x98,0x2a,0x03,0x09,0x88,0x0a,0x9a,0x3c,
++            0x59,0x69,0x1a,0x38,0x49,0x49,0x8a,0x1c,0x19,0x29,0x0a,0x18,0x09,0x09,0x92,0x2c,
++            0x58,0x68,0x12,0x28,0x48,0x48,0x82,0x0c,0x18,0x28,0x02,0x08,0x08,0x08,0x7e,0xcc,
++            0x04,0xd4,0x38,0xce,0x18,0xfa,0xed,0xbd,0x68,0xb1,0x49,0x51,0x83,0x07,0x16,0xca,
++            0xad,0x96,0x31,0x0f,0x76,0x13,0x5e,0xb8,0x6c,0xd4,0x41,0x41,0x82,0x06,0xb1,0x09,
++            0x2c,0x12,0xef,0xcf,0xba,0xb8,0xd8,0x2f,0xdd,0xc5,0x48,0x50,0x03,0x05,0xbf,0xd9,
++            0x0c,0x97,0xe1,0xbb,0xbb,0xb1,0x4d,0x95,0xe1,0x50,0x40,0x40,0x02,0x04,0x99,0x35,
++            0xd1,0x63,0x19,0x31,0xc1,0x43,0x89,0x15,0x91,0x23,0x09,0x11,0x81,0x03,0x91,0x25,
++            0xd0,0x62,0x11,0x21,0xc0,0x42,0x81,0x05,0x90,0x22,0x01,0x01,0x80,0x02,0x98,0x34,
++            0x51,0x61,0x18,0x30,0x41,0x41,0x88,0x14,0x11,0x21,0x08,0x10,0x01,0x01,0x90,0x24,
++            0x50,0x60,0x10,0x20,0x40,0x40,0x80,0x04,0x10,0x20,0x00,0x00,0x00,0x00,0xff,0xff,
++            0xff,0xff,0x7f,0xfb,0xef,0xdf,0xef,0xdf,0xbf,0xbf,0x6f,0xdb,0xaf,0x9f,0xf7,0xef,
++            0xfe,0xfe,0x77,0xeb,0xee,0xde,0xe7,0xcf,0xbe,0xbe,0x67,0xcb,0xae,0x9e,0xfe,0xfe,
++            0x7f,0xfd,0x7e,0xfa,0x6f,0xdd,0xee,0xde,0x3f,0xbd,0x6e,0xda,0x2f,0x9d,0xf6,0xee,
++            0x7e,0xfc,0x76,0xea,0x6e,0xdc,0xe6,0xce,0x3e,0xbc,0x66,0xca,0x2e,0x9c,0xbf,0xbf,
++            0xfd,0xfb,0x3f,0xbb,0xed,0xdb,0xaf,0x9f,0xbd,0xbb,0x2f,0x9b,0xad,0x9b,0xb7,0xaf,
++            0xfc,0xfa,0x37,0xab,0xec,0xda,0xa7,0x8f,0xbc,0xba,0x27,0x8b,0xac,0x9a,0xbe,0xbe,
++            0x7d,0xf9,0x3e,0xba,0x6d,0xd9,0xae,0x9e,0x3d,0xb9,0x2e,0x9a,0x2d,0x99,0xb6,0xae,
++            0x7c,0xf8,0x36,0xaa,0x6c,0xd8,0xa6,0x8e,0x3c,0xb8,0x26,0x8a,0x2c,0x98,0xfd,0xf7,
++            0xf7,0xf7,0x7d,0xf3,0xe7,0xd7,0xed,0xd7,0xb7,0xb7,0x6d,0xd3,0xa7,0x97,0xf5,0xe7,
++            0xf6,0xf6,0x75,0xe3,0xe6,0xd6,0xe5,0xc7,0xb6,0xb6,0x65,0xc3,0xa6,0x96,0xfc,0xf6,
++            0x77,0xf5,0x7c,0xf2,0x67,0xd5,0xec,0xd6,0x37,0xb5,0x6c,0xd2,0x27,0x95,0xf4,0xe6,
++            0x76,0xf4,0x74,0xe2,0x66,0xd4,0xe4,0xc6,0x36,0xb4,0x64,0xc2,0x26,0x94,0xbd,0xb7,
++            0xf5,0xf3,0x3d,0xb3,0xe5,0xd3,0xad,0x97,0xb5,0xb3,0x2d,0x93,0xa5,0x93,0xb5,0xa7,
++            0xf4,0xf2,0x35,0xa3,0xe4,0xd2,0xa5,0x87,0xb4,0xb2,0x25,0x83,0xa4,0x92,0xbc,0xb6,
++            0x75,0xf1,0x3c,0xb2,0x65,0xd1,0xac,0x96,0x35,0xb1,0x2c,0x92,0x25,0x91,0xb4,0xa6,
++            0x74,0xf0,0x34,0xa2,0x64,0xd0,0xa4,0x86,0x34,0xb0,0x24,0x82,0x24,0x90,0xfb,0x7f,
++            0xdf,0xef,0x7b,0x7b,0xcf,0xcf,0xeb,0x5f,0x9f,0xaf,0x6b,0x5b,0x8f,0x8f,0xf3,0x6f,
++            0xde,0xee,0x73,0x6b,0xce,0xce,0xe3,0x4f,0x9e,0xae,0x63,0x4b,0x8e,0x8e,0xfa,0x7e,
++            0x5f,0xed,0x7a,0x7a,0x4f,0xcd,0xea,0x5e,0x1f,0xad,0x6a,0x5a,0x0f,0x8d,0xf2,0x6e,
++            0x5e,0xec,0x72,0x6a,0x4e,0xcc,0xe2,0x4e,0x1e,0xac,0x62,0x4a,0x0e,0x8c,0xbb,0x3f,
++            0xdd,0xeb,0x3b,0x3b,0xcd,0xcb,0xab,0x1f,0x9d,0xab,0x2b,0x1b,0x8d,0x8b,0xb3,0x2f,
++            0xdc,0xea,0x33,0x2b,0xcc,0xca,0xa3,0x0f,0x9c,0xaa,0x23,0x0b,0x8c,0x8a,0xba,0x3e,
++            0x5d,0xe9,0x3a,0x3a,0x4d,0xc9,0xaa,0x1e,0x1d,0xa9,0x2a,0x1a,0x0d,0x89,0xb2,0x2e,
++            0x5c,0xe8,0x32,0x2a,0x4c,0xc8,0xa2,0x0e,0x1c,0xa8,0x22,0x0a,0x0c,0x88,0xf9,0x77,
++            0xd7,0xe7,0x79,0x73,0xc7,0xc7,0xe9,0x57,0x97,0xa7,0x69,0x53,0x87,0x87,0xf1,0x67,
++            0xd6,0xe6,0x71,0x63,0xc6,0xc6,0xe1,0x47,0x96,0xa6,0x61,0x43,0x86,0x86,0xf8,0x76,
++            0x57,0xe5,0x78,0x72,0x47,0xc5,0xe8,0x56,0x17,0xa5,0x68,0x52,0x07,0x85,0xf0,0x66,
++            0x56,0xe4,0x70,0x62,0x46,0xc4,0xe0,0x46,0x16,0xa4,0x60,0x42,0x06,0x84,0xb9,0x37,
++            0xd5,0xe3,0x39,0x33,0xc5,0xc3,0xa9,0x17,0x95,0xa3,0x29,0x13,0x85,0x83,0xb1,0x27,
++            0xd4,0xe2,0x31,0x23,0xc4,0xc2,0xa1,0x07,0x94,0xa2,0x21,0x03,0x84,0x82,0xb8,0x36,
++            0x55,0xe1,0x38,0x32,0x45,0xc1,0xa8,0x16,0x15,0xa1,0x28,0x12,0x05,0x81,0xb0,0x26,
++            0x54,0xe0,0x30,0x22,0x44,0xc0,0xa0,0x06,0x14,0xa0,0x20,0x02,0x04,0x80,0xdf,0xfd,
++            0xfb,0x7f,0x5f,0xf9,0xeb,0x5f,0xcf,0xdd,0xbb,0x3f,0x4f,0xd9,0xab,0x1f,0xd7,0xed,
++            0xfa,0x7e,0x57,0xe9,0xea,0x5e,0xc7,0xcd,0xba,0x3e,0x47,0xc9,0xaa,0x1e,0xde,0xfc,
++            0x7b,0x7d,0x5e,0xf8,0x6b,0x5d,0xce,0xdc,0x3b,0x3d,0x4e,0xd8,0x2b,0x1d,0xd6,0xec,
++            0x7a,0x7c,0x56,0xe8,0x6a,0x5c,0xc6,0xcc,0x3a,0x3c,0x46,0xc8,0x2a,0x1c,0x9f,0xbd,
++            0xf9,0x7b,0x1f,0xb9,0xe9,0x5b,0x8f,0x9d,0xb9,0x3b,0x0f,0x99,0xa9,0x1b,0x97,0xad,
++            0xf8,0x7a,0x17,0xa9,0xe8,0x5a,0x87,0x8d,0xb8,0x3a,0x07,0x89,0xa8,0x1a,0x9e,0xbc,
++            0x79,0x79,0x1e,0xb8,0x69,0x59,0x8e,0x9c,0x39,0x39,0x0e,0x98,0x29,0x19,0x96,0xac,
++            0x78,0x78,0x16,0xa8,0x68,0x58,0x86,0x8c,0x38,0x38,0x06,0x88,0x28,0x18,0xdd,0xf5,
++            0xf3,0x77,0x5d,0xf1,0xe3,0x57,0xcd,0xd5,0xb3,0x37,0x4d,0xd1,0xa3,0x17,0xd5,0xe5,
++            0xf2,0x76,0x55,0xe1,0xe2,0x56,0xc5,0xc5,0xb2,0x36,0x45,0xc1,0xa2,0x16,0xdc,0xf4,
++            0x73,0x75,0x5c,0xf0,0x63,0x55,0xcc,0xd4,0x33,0x35,0x4c,0xd0,0x23,0x15,0xd4,0xe4,
++            0x72,0x74,0x54,0xe0,0x62,0x54,0xc4,0xc4,0x32,0x34,0x44,0xc0,0x22,0x14,0x9d,0xb5,
++            0xf1,0x73,0x1d,0xb1,0xe1,0x53,0x8d,0x95,0xb1,0x33,0x0d,0x91,0xa1,0x13,0x95,0xa5,
++            0xf0,0x72,0x15,0xa1,0xe0,0x52,0x85,0x85,0xb0,0x32,0x05,0x81,0xa0,0x12,0x9c,0xb4,
++            0x71,0x71,0x1c,0xb0,0x61,0x51,0x8c,0x94,0x31,0x31,0x0c,0x90,0x21,0x11,0x94,0xa4,
++            0x70,0x70,0x14,0xa0,0x60,0x50,0x84,0x84,0x30,0x30,0x04,0x80,0x20,0x10,0xdb,0x7d,
++            0xdb,0x6f,0x5b,0x79,0xcb,0x4f,0xcb,0x5d,0x9b,0x2f,0x4b,0x59,0x8b,0x0f,0xd3,0x6d,
++            0xda,0x6e,0x53,0x69,0xca,0x4e,0xc3,0x4d,0x9a,0x2e,0x43,0x49,0x8a,0x0e,0xda,0x7c,
++            0x5b,0x6d,0x5a,0x78,0x4b,0x4d,0xca,0x5c,0x1b,0x2d,0x4a,0x58,0x0b,0x0d,0xd2,0x6c,
++            0x5a,0x6c,0x52,0x68,0x4a,0x4c,0xc2,0x4c,0x1a,0x2c,0x42,0x48,0x0a,0x0c,0x9b,0x3d,
++            0xd9,0x6b,0x1b,0x39,0xc9,0x4b,0x8b,0x1d,0x99,0x2b,0x0b,0x19,0x89,0x0b,0x93,0x2d,
++            0xd8,0x6a,0x13,0x29,0xc8,0x4a,0x83,0x0d,0x98,0x2a,0x03,0x09,0x88,0x0a,0x9a,0x3c,
++            0x59,0x69,0x1a,0x38,0x49,0x49,0x8a,0x1c,0x19,0x29,0x0a,0x18,0x09,0x09,0x92,0x2c,
++            0x58,0x68,0x12,0x28,0x48,0x48,0x82,0x0c,0x18,0x28,0x02,0x08,0x08,0x08,0xd9,0x75,
++            0xd3,0x67,0x59,0x71,0xc3,0x47,0xc9,0x55,0x93,0x27,0x49,0x51,0x83,0x07,0xd1,0x65,
++            0xd2,0x66,0x51,0x61,0xc2,0x46,0xc1,0x45,0x92,0x26,0x41,0x41,0x82,0x06,0xd8,0x74,
++            0x53,0x65,0x58,0x70,0x43,0x45,0xc8,0x54,0x13,0x25,0x48,0x50,0x03,0x05,0xd0,0x64,
++            0x52,0x64,0x50,0x60,0x42,0x44,0xc0,0x44,0x12,0x24,0x40,0x40,0x02,0x04,0x99,0x35,
++            0xd1,0x63,0x19,0x31,0xc1,0x43,0x89,0x15,0x91,0x23,0x09,0x11,0x81,0x03,0x91,0x25,
++            0xd0,0x62,0x11,0x21,0xc0,0x42,0x81,0x05,0x90,0x22,0x01,0x01,0x80,0x02,0x98,0x34,
++            0x51,0x61,0x18,0x30,0x41,0x41,0x88,0x14,0x11,0x21,0x08,0x10,0x01,0x01,0x90,0x24,
++            0x50,0x60,0x10,0x20,0x40,0x40,0x80,0x04,0x10,0x20,0x00,0x00,0x00,0x00,0xff,0xff,
++            0xff,0xff,0x7f,0xfb,0xef,0xdf,0xef,0xdf,0xbf,0xbf,0x6f,0xdb,0xaf,0x9f,0xf7,0xef,
++            0xfe,0xfe,0x77,0xeb,0xee,0xde,0xe7,0xcf,0xbe,0xbe,0x67,0xcb,0xae,0x9e,0xfe,0xfe,
++            0x7f,0xfd,0x7e,0xfa,0x6f,0xdd,0xee,0xde,0x3f,0xbd,0x6e,0xda,0x2f,0x9d,0xf6,0xee,
++            0x7e,0xfc,0x76,0xea,0x6e,0xdc,0xe6,0xce,0x3e,0xbc,0x66,0xca,0x2e,0x9c,0xbf,0xbf,
++            0xfd,0xfb,0x3f,0xbb,0xed,0xdb,0xaf,0x9f,0xbd,0xbb,0x2f,0x9b,0xad,0x9b,0xb7,0xaf,
++            0xfc,0xfa,0x37,0xab,0xec,0xda,0xa7,0x8f,0xbc,0xba,0x27,0x8b,0xac,0x9a,0xbe,0xbe,
++            0x7d,0xf9,0x3e,0xba,0x6d,0xd9,0xae,0x9e,0x3d,0xb9,0x2e,0x9a,0x2d,0x99,0xb6,0xae,
++            0x7c,0xf8,0x36,0xaa,0x6c,0xd8,0xa6,0x8e,0x3c,0xb8,0x26,0x8a,0x2c,0x98,0xfd,0xf7,
++            0xf7,0xf7,0x7d,0xf3,0xe7,0xd7,0xed,0xd7,0xb7,0xb7,0x6d,0xd3,0xa7,0x97,0xf5,0xe7,
++            0xf6,0xf6,0x75,0xe3,0xe6,0xd6,0xe5,0xc7,0xb6,0xb6,0x65,0xc3,0xa6,0x96,0xfc,0xf6,
++            0x77,0xf5,0x7c,0xf2,0x67,0xd5,0xec,0xd6,0x37,0xb5,0x6c,0xd2,0x27,0x95,0xf4,0xe6,
++            0x76,0xf4,0x74,0xe2,0x66,0xd4,0xe4,0xc6,0x36,0xb4,0x64,0xc2,0x26,0x94,0xbd,0xb7,
++            0xf5,0xf3,0x3d,0xb3,0xe5,0xd3,0xad,0x97,0xb5,0xb3,0x2d,0x93,0xa5,0x93,0xb5,0xa7,
++            0xf4,0xf2,0x35,0xa3,0xe4,0xd2,0xa5,0x87,0xb4,0xb2,0x25,0x83,0xa4,0x92,0xbc,0xb6,
++            0x75,0xf1,0x3c,0xb2,0x65,0xd1,0xac,0x96,0x35,0xb1,0x2c,0x92,0x25,0x91,0xb4,0xa6,
++            0x74,0xf0,0x34,0xa2,0x64,0xd0,0xa4,0x86,0x34,0xb0,0x24,0x82,0x24,0x90,0xfb,0x7f,
++            0xdf,0xef,0x7b,0x7b,0xcf,0xcf,0xeb,0x5f,0x9f,0xaf,0x6b,0x5b,0x8f,0x8f,0xf3,0x6f,
++            0xde,0xee,0x73,0x6b,0xce,0xce,0xe3,0x4f,0x9e,0xae,0x63,0x4b,0x8e,0x8e,0xfa,0x7e,
++            0x5f,0xed,0x7a,0x7a,0x4f,0xcd,0xea,0x5e,0x1f,0xad,0x6a,0x5a,0x0f,0x8d,0xf2,0x6e,
++            0x5e,0xec,0x72,0x6a,0x4e,0xcc,0xe2,0x4e,0x1e,0xac,0x62,0x4a,0x0e,0x8c,0xbb,0x3f,
++            0xdd,0xeb,0x3b,0x3b,0xcd,0xcb,0xab,0x1f,0x9d,0xab,0x2b,0x1b,0x8d,0x8b,0xb3,0x2f,
++            0xdc,0xea,0x33,0x2b,0xcc,0xca,0xa3,0x0f,0x9c,0xaa,0x23,0x0b,0x8c,0x8a,0xba,0x3e,
++            0x5d,0xe9,0x3a,0x3a,0x4d,0xc9,0xaa,0x1e,0x1d,0xa9,0x2a,0x1a,0x0d,0x89,0xb2,0x2e,
++            0x5c,0xe8,0x32,0x2a,0x4c,0xc8,0xa2,0x0e,0x1c,0xa8,0x22,0x0a,0x0c,0x88,0xf9,0x77,
++            0xd7,0xe7,0x79,0x73,0xc7,0xc7,0xe9,0x57,0x97,0xa7,0x69,0x53,0x87,0x87,0xf1,0x67,
++            0xd6,0xe6,0x71,0x63,0xc6,0xc6,0xe1,0x47,0x96,0xa6,0x61,0x43,0x86,0x86,0xf8,0x76,
++            0x57,0xe5,0x78,0x72,0x47,0xc5,0xe8,0x56,0x17,0xa5,0x68,0x52,0x07,0x85,0xf0,0x66,
++            0x56,0xe4,0x70,0x62,0x46,0xc4,0xe0,0x46,0x16,0xa4,0x60,0x42,0x06,0x84,0xb9,0x37,
++            0xd5,0xe3,0x39,0x33,0xc5,0xc3,0xa9,0x17,0x95,0xa3,0x29,0x13,0x85,0x83,0xb1,0x27,
++            0xd4,0xe2,0x31,0x23,0xc4,0xc2,0xa1,0x07,0x94,0xa2,0x21,0x03,0x84,0x82,0xb8,0x36,
++            0x55,0xe1,0x38,0x32,0x45,0xc1,0xa8,0x16,0x15,0xa1,0x28,0x12,0x05,0x81,0xb0,0x26,
++            0x54,0xe0,0x30,0x22,0x44,0xc0,0xa0,0x06,0x14,0xa0,0x20,0x02,0x04,0x80,0xdf,0xfd,
++            0xfb,0x7f,0x5f,0xf9,0xeb,0x5f,0xcf,0xdd,0xbb,0x3f,0x4f,0xd9,0xab,0x1f,0xd7,0xed,
++            0xfa,0x7e,0x57,0xe9,0xea,0x5e,0xc7,0xcd,0xba,0x3e,0x47,0xc9,0xaa,0x1e,0xde,0xfc,
++            0x7b,0x7d,0x5e,0xf8,0x6b,0x5d,0xce,0xdc,0x3b,0x3d,0x4e,0xd8,0x2b,0x1d,0xd6,0xec,
++            0x7a,0x7c,0x56,0xe8,0x6a,0x5c,0xc6,0xcc,0x3a,0x3c,0x46,0xc8,0x2a,0x1c,0x9f,0xbd,
++            0xf9,0x7b,0x1f,0xb9,0xe9,0x5b,0x8f,0x9d,0xb9,0x3b,0x0f,0x99,0xa9,0x1b,0x97,0xad,
++            0xf8,0x7a,0x17,0xa9,0xe8,0x5a,0x87,0x8d,0xb8,0x3a,0x07,0x89,0xa8,0x1a,0x9e,0xbc,
++            0x79,0x79,0x1e,0xb8,0x69,0x59,0x8e,0x9c,0x39,0x39,0x0e,0x98,0x29,0x19,0x96,0xac,
++            0x78,0x78,0x16,0xa8,0x68,0x58,0x86,0x8c,0x38,0x38,0x06,0x88,0x28,0x18,0xdd,0xf5,
++            0xf3,0x77,0x5d,0xf1,0xe3,0x57,0xcd,0xd5,0xb3,0x37,0x4d,0xd1,0xa3,0x17,0xd5,0xe5,
++            0xf2,0x76,0x55,0xe1,0xe2,0x56,0xc5,0xc5,0xb2,0x36,0x45,0xc1,0xa2,0x16,0xdc,0xf4,
++            0x73,0x75,0x5c,0xf0,0x63,0x55,0xcc,0xd4,0x33,0x35,0x4c,0xd0,0x23,0x15,0xd4,0xe4,
++            0x72,0x74,0x54,0xe0,0x62,0x54,0xc4,0xc4,0x32,0x34,0x44,0xc0,0x22,0x14,0x9d,0xb5,
++            0xf1,0x73,0x1d,0xb1,0xe1,0x53,0x8d,0x95,0xb1,0x33,0x0d,0x91,0xa1,0x13,0x95,0xa5,
++            0xf0,0x72,0x15,0xa1,0xe0,0x52,0x85,0x85,0xb0,0x32,0x05,0x81,0xa0,0x12,0x9c,0xb4,
++            0x71,0x71,0x1c,0xb0,0x61,0x51,0x8c,0x94,0x31,0x31,0x0c,0x90,0x21,0x11,0x94,0xa4,
++            0x70,0x70,0x14,0xa0,0x60,0x50,0x84,0x84,0x30,0x30,0x04,0x80,0x20,0x10,0xdb,0x7d,
++            0xdb,0x6f,0x5b,0x79,0xcb,0x4f,0xcb,0x5d,0x9b,0x2f,0x4b,0x59,0x8b,0x0f,0xd3,0x6d,
++            0xda,0x6e,0x53,0x69,0xca,0x4e,0xc3,0x4d,0x9a,0x2e,0x43,0x49,0x8a,0x0e,0xda,0x7c,
++            0x5b,0x6d,0x5a,0x78,0x4b,0x4d,0xca,0x5c,0x1b,0x2d,0x4a,0x58,0x0b,0x0d,0xd2,0x6c,
++            0x5a,0x6c,0x52,0x68,0x4a,0x4c,0xc2,0x4c,0x1a,0x2c,0x42,0x48,0x0a,0x0c,0x9b,0x3d,
++            0xd9,0x6b,0x1b,0x39,0xc9,0x4b,0x8b,0x1d,0x99,0x2b,0x0b,0x19,0x89,0x0b,0x93,0x2d,
++            0xd8,0x6a,0x13,0x29,0xc8,0x4a,0x83,0x0d,0x98,0x2a,0x03,0x09,0x88,0x0a,0x9a,0x3c,
++            0x59,0x69,0x1a,0x38,0x49,0x49,0x8a,0x1c,0x19,0x29,0x0a,0x18,0x09,0x09,0x92,0x2c,
++            0x58,0x68,0x12,0x28,0x48,0x48,0x82,0x0c,0x18,0x28,0x02,0x08,0x08,0x08,0xd9,0x75,
++            0xd3,0x67,0x59,0x71,0xc3,0x47,0xc9,0x55,0x93,0x27,0x49,0x51,0x83,0x07,0xd1,0x65,
++            0xd2,0x66,0x51,0x61,0xc2,0x46,0xc1,0x45,0x92,0x26,0x41,0x41,0x82,0x06,0xd8,0x74,
++            0x53,0x65,0x58,0x70,0x43,0x45,0xc8,0x54,0x13,0x25,0x48,0x50,0x03,0x05,0xd0,0x64,
++            0x52,0x64,0x50,0x60,0x42,0x44,0xc0,0x44,0x12,0x24,0x40,0x40,0x02,0x04,0x99,0x35,
++            0xd1,0x63,0x19,0x31,0xc1,0x43,0x89,0x15,0x91,0x23,0x09,0x11,0x81,0x03,0x91,0x25,
++            0xd0,0x62,0x11,0x21,0xc0,0x42,0x81,0x05,0x90,0x22,0x01,0x01,0x80,0x02,0x98,0x34,
++            0x51,0x61,0x18,0x30,0x41,0x41,0x88,0x14,0x11,0x21,0x08,0x10,0x01,0x01,0x90,0x24,
++            0x50,0x60,0x10,0x20,0x40,0x40,0x80,0x04,0x10,0x20,0x00,0x00,0x00,0x00,0xff,0xff,
++            0xff,0xff,0x7f,0xfb,0xef,0xdf,0xef,0xdf,0xbf,0xbf,0x6f,0xdb,0xaf,0x9f,0xf7,0xef,
++            0xfe,0xfe,0x77,0xeb,0xee,0xde,0xe7,0xcf,0xbe,0xbe,0x67,0xcb,0xae,0x9e,0xfe,0xfe,
++            0x7f,0xfd,0x7e,0xfa,0x6f,0xdd,0xee,0xde,0x3f,0xbd,0x6e,0xda,0x2f,0x9d,0xf6,0xee,
++            0x7e,0xfc,0x76,0xea,0x6e,0xdc,0xe6,0xce,0x3e,0xbc,0x66,0xca,0x2e,0x9c,0xbf,0xbf,
++            0xfd,0xfb,0x3f,0xbb,0xed,0xdb,0xaf,0x9f,0xbd,0xbb,0x2f,0x9b,0xad,0x9b,0xb7,0xaf,
++            0xfc,0xfa,0x37,0xab,0xec,0xda,0xa7,0x8f,0xbc,0xba,0x27,0x8b,0xac,0x9a,0xbe,0xbe,
++            0x7d,0xf9,0x3e,0xba,0x6d,0xd9,0xae,0x9e,0x3d,0xb9,0x2e,0x9a,0x2d,0x99,0xb6,0xae,
++            0x7c,0xf8,0x36,0xaa,0x6c,0xd8,0xa6,0x8e,0x3c,0xb8,0x26,0x8a,0x2c,0x98,0xfd,0xf7,
++            0xf7,0xf7,0x7d,0xf3,0xe7,0xd7,0xed,0xd7,0xb7,0xb7,0x6d,0xd3,0xa7,0x97,0xf5,0xe7,
++            0xf6,0xf6,0x75,0xe3,0xe6,0xd6,0xe5,0xc7,0xb6,0xb6,0x65,0xc3,0xa6,0x96,0xfc,0xf6,
++            0x77,0xf5,0x7c,0xf2,0x67,0xd5,0xec,0xd6,0x37,0xb5,0x6c,0xd2,0x27,0x95,0xf4,0xe6,
++            0x76,0xf4,0x74,0xe2,0x66,0xd4,0xe4,0xc6,0x36,0xb4,0x64,0xc2,0x26,0x94,0xbd,0xb7,
++            0xf5,0xf3,0x3d,0xb3,0xe5,0xd3,0xad,0x97,0xb5,0xb3,0x2d,0x93,0xa5,0x93,0xb5,0xa7,
++            0xf4,0xf2,0x35,0xa3,0xe4,0xd2,0xa5,0x87,0xb4,0xb2,0x25,0x83,0xa4,0x92,0xbc,0xb6,
++            0x75,0xf1,0x3c,0xb2,0x65,0xd1,0xac,0x96,0x35,0xb1,0x2c,0x92,0x25,0x91,0xb4,0xa6,
++            0x74,0xf0,0x34,0xa2,0x64,0xd0,0xa4,0x86,0x34,0xb0,0x24,0x82,0x24,0x90,0xfb,0x7f,
++            0xdf,0xef,0x7b,0x7b,0xcf,0xcf,0xeb,0x5f,0x9f,0xaf,0x6b,0x5b,0x8f,0x8f,0xf3,0x6f,
++            0xde,0xee,0x73,0x6b,0xce,0xce,0xe3,0x4f,0x9e,0xae,0x63,0x4b,0x8e,0x8e,0xfa,0x7e,
++            0x5f,0xed,0x7a,0x7a,0x4f,0xcd,0xea,0x5e,0x1f,0xad,0x6a,0x5a,0x0f,0x8d,0xf2,0x6e,
++            0x5e,0xec,0x72,0x6a,0x4e,0xcc,0xe2,0x4e,0x1e,0xac,0x62,0x4a,0x0e,0x8c,0xbb,0x3f,
++            0xdd,0xeb,0x3b,0x3b,0xcd,0xcb,0xab,0x1f,0x9d,0xab,0x2b,0x1b,0x8d,0x8b,0xb3,0x2f,
++            0xdc,0xea,0x33,0x2b,0xcc,0xca,0xa3,0x0f,0x9c,0xaa,0x23,0x0b,0x8c,0x8a,0xba,0x3e,
++            0x5d,0xe9,0x3a,0x3a,0x4d,0xc9,0xaa,0x1e,0x1d,0xa9,0x2a,0x1a,0x0d,0x89,0xb2,0x2e,
++            0x5c,0xe8,0x32,0x2a,0x4c,0xc8,0xa2,0x0e,0x1c,0xa8,0x22,0x0a,0x0c,0x88,0xf9,0x77,
++            0xd7,0xe7,0x79,0x73,0xc7,0xc7,0xe9,0x57,0x97,0xa7,0x69,0x53,0x87,0x87,0xf1,0x67,
++            0xd6,0xe6,0x71,0x63,0xc6,0xc6,0xe1,0x47,0x96,0xa6,0x61,0x43,0x86,0x86,0xf8,0x76,
++            0x57,0xe5,0x78,0x72,0x47,0xc5,0xe8,0x56,0x17,0xa5,0x68,0x52,0x07,0x85,0xf0,0x66,
++            0x56,0xe4,0x70,0x62,0x46,0xc4,0xe0,0x46,0x16,0xa4,0x60,0x42,0x06,0x84,0xb9,0x37,
++            0xd5,0xe3,0x39,0x33,0xc5,0xc3,0xa9,0x17,0x95,0xa3,0x29,0x13,0x85,0x83,0xb1,0x27,
++            0xd4,0xe2,0x31,0x23,0xc4,0xc2,0xa1,0x07,0x94,0xa2,0x21,0x03,0x84,0x82,0xb8,0x36,
++            0x55,0xe1,0x38,0x32,0x45,0xc1,0xa8,0x16,0x15,0xa1,0x28,0x12,0x05,0x81,0xb0,0x26,
++            0x54,0xe0,0x30,0x22,0x44,0xc0,0xa0,0x06,0x14,0xa0,0x20,0x02,0x04,0x80,0xdf,0xfd,
++            0xfb,0x7f,0x5f,0xf9,0xeb,0x5f,0xcf,0xdd,0xbb,0x3f,0x4f,0xd9,0xab,0x1f,0xd7,0xed,
++            0xfa,0x7e,0x57,0xe9,0xea,0x5e,0xc7,0xcd,0xba,0x3e,0x47,0xc9,0xaa,0x1e,0xde,0xfc,
++            0x7b,0x7d,0x5e,0xf8,0x6b,0x5d,0xce,0xdc,0x3b,0x3d,0x4e,0xd8,0x2b,0x1d,0xd6,0xec,
++            0x7a,0x7c,0x56,0xe8,0x6a,0x5c,0xc6,0xcc,0x3a,0x3c,0x46,0xc8,0x2a,0x1c,0x9f,0xbd,
++            0xf9,0x7b,0x1f,0xb9,0xe9,0x5b,0x8f,0x9d,0xb9,0x3b,0x0f,0x99,0xa9,0x1b,0x97,0xad,
++            0xf8,0x7a,0x17,0xa9,0xe8,0x5a,0x87,0x8d,0xb8,0x3a,0x07,0x89,0xa8,0x1a,0x9e,0xbc,
++            0x79,0x79,0x1e,0xb8,0x69,0x59,0x8e,0x9c,0x39,0x39,0x0e,0x98,0x29,0x19,0x96,0xac,
++            0x78,0x78,0x16,0xa8,0x68,0x58,0x86,0x8c,0x38,0x38,0x06,0x88,0x28,0x18,0xdd,0xf5,
++            0xf3,0x77,0x5d,0xf1,0xe3,0x57,0xcd,0xd5,0xb3,0x37,0x4d,0xd1,0xa3,0x17,0xd5,0xe5,
++            0xf2,0x76,0x55,0xe1,0xe2,0x56,0xc5,0xc5,0xb2,0x36,0x45,0xc1,0xa2,0x16,0xdc,0xf4,
++            0x73,0x75,0x5c,0xf0,0x63,0x55,0xcc,0xd4,0x33,0x35,0x4c,0xd0,0x23,0x15,0xd4,0xe4,
++            0x72,0x74,0x54,0xe0,0x62,0x54,0xc4,0xc4,0x32,0x34,0x44,0xc0,0x22,0x14,0x9d,0xb5,
++            0xf1,0x73,0x1d,0xb1,0xe1,0x53,0x8d,0x95,0xb1,0x33,0x0d,0x91,0xa1,0x13,0x95,0xa5,
++            0xf0,0x72,0x15,0xa1,0xe0,0x52,0x85,0x85,0xb0,0x32,0x05,0x81,0xa0,0x12,0x9c,0xb4,
++            0x71,0x71,0x1c,0xb0,0x61,0x51,0x8c,0x94,0x31,0x31,0x0c,0x90,0x21,0x11,0x94,0xa4,
++            0x70,0x70,0x14,0xa0,0x60,0x50,0x84,0x84,0x30,0x30,0x04,0x80,0x20,0x10,0xdb,0x7d,
++            0xdb,0x6f,0x5b,0x79,0xcb,0x4f,0xcb,0x5d,0x9b,0x2f,0x4b,0x59,0x8b,0x0f,0xd3,0x6d,
++            0xda,0x6e,0x53,0x69,0xca,0x4e,0xc3,0x4d,0x9a,0x2e,0x43,0x49,0x8a,0x0e,0xda,0x7c,
++            0x5b,0x6d,0x5a,0x78,0x4b,0x4d,0xca,0x5c,0x1b,0x2d,0x4a,0x58,0x0b,0x0d,0xd2,0x6c,
++            0x5a,0x6c,0x52,0x68,0x4a,0x4c,0xc2,0x4c,0x1a,0x2c,0x42,0x48,0x0a,0x0c,0x9b,0x3d,
++            0xd9,0x6b,0x1b,0x39,0xc9,0x4b,0x8b,0x1d,0x99,0x2b,0x0b,0x19,0x89,0x0b,0x93,0x2d,
++            0xd8,0x6a,0x13,0x29,0xc8,0x4a,0x83,0x0d,0x98,0x2a,0x03,0x09,0x88,0x0a,0x9a,0x3c,
++            0x59,0x69,0x1a,0x38,0x49,0x49,0x8a,0x1c,0x19,0x29,0x0a,0x18,0x09,0x09,0x92,0x2c,
++            0x58,0x68,0x12,0x28,0x48,0x48,0x82,0x0c,0x18,0x28,0x02,0x08,0x08,0x08,0xd9,0x75,
++            0xd3,0x67,0x59,0x71,0xc3,0x47,0xc9,0x55,0x93,0x27,0x49,0x51,0x83,0x07,0xd1,0x65,
++            0xd2,0x66,0x51,0x61,0xc2,0x46,0xc1,0x45,0x92,0x26,0x41,0x41,0x82,0x06,0xd8,0x74,
++            0x53,0x65,0x58,0x70,0x43,0x45,0xc8,0x54,0x13,0x25,0x48,0x50,0x03,0x05,0xd0,0x64,
++            0x52,0x64,0x50,0x60,0x42,0x44,0xc0,0x44,0x12,0x24,0x40,0x40,0x02,0x04,0x99,0x35,
++            0xd1,0x63,0x19,0x31,0xc1,0x43,0x89,0x15,0x91,0x23,0x09,0x11,0x81,0x03,0x91,0x25,
++            0xd0,0x62,0x11,0x21,0xc0,0x42,0x81,0x05,0x90,0x22,0x01,0x01,0x80,0x02,0x98,0x34,
++            0x51,0x61,0x18,0x30,0x41,0x41,0x88,0x14,0x11,0x21,0x08,0x10,0x01,0x01,0x90,0x24,
++            0x50,0x60,0x10,0x20,0x40,0x40,0x80,0x04,0x10,0x20,0x00,0x00,0x68,0xf7,0x80,0x0c,
++            0xcc,0x40,0x3b,0xa1,0xe7,0xdd,0x4e,0xb6,0x98,0xeb,0xa8,0xdb,0xa5,0x03,0xbf,0x11,
++            0x8c,0x0d,0x33,0xa5,0x1f,0x8e,0x7e,0xc1,0x83,0xc1,0xe6,0xa4,0xa4,0xc2,0x04,0x19,
++            0x0f,0x00,0x97,0x95,0x7b,0xa0,0xf7,0x67,0x21,0xed,0x6a,0x5a,0xb8,0xe0,0x61,0x6e,
++            0xc2,0x63,0x4d,0x17,0x9f,0x8e,0x67,0xaf,0x2a,0xb5,0x5d,0xc6,0xdf,0x67,0x1e,0x4f,
++            0x46,0x4a,0x6c,0x06,0x91,0xd0,0x76,0x4c,0x0c,0xe9,0xe8,0x9b,0xa7,0x07,0x6e,0xef,
++            0xfc,0xa1,0x17,0x54,0x93,0x65,0x6a,0x4e,0xe0,0xe4,0xa6,0xf9,0xa6,0xe6,0x20,0xe1,
++            0x54,0xb9,0x81,0xe5,0x82,0xa6,0x43,0x90,0x61,0x06,0x2a,0x1a,0xb2,0x6a,0xba,0xaf,
++            0x4b,0xb0,0x16,0x54,0x4f,0x45,0x1b,0x82,0x81,0x9a,0x7f,0x86,0xc5,0x63,0x1a,0x05,
++            0x6b,0x68,0xd4,0x3d,0xb9,0xd7,0x4c,0xb3,0x58,0xe7,0x56,0x5f,0x32,0xc9,0xf1,0x47,
++            0x4a,0x96,0x35,0x2d,0x5b,0x86,0x44,0x0f,0xc8,0xe6,0x4e,0xc2,0xa4,0xc8,0x94,0xf6,
++            0x69,0xd9,0xbd,0xbd,0xb6,0xf5,0x70,0xd8,0x2c,0xfe,0xab,0xd2,0x31,0xe9,0xa4,0xdb,
++            0x0a,0x4d,0xc9,0x63,0xf3,0x49,0x2d,0xc8,0x29,0x0b,0xd9,0xce,0x9b,0xb6,0x3d,0x5b,
++            0xf8,0x93,0x92,0x40,0x5a,0xd7,0x04,0xed,0xa1,0x2e,0x91,0x53,0x58,0xb7,0x28,0x58,
++            0x08,0x6d,0xce,0x43,0x59,0x86,0x3c,0x1a,0xbc,0xb0,0xda,0xf8,0x47,0xee,0x76,0xc1,
++            0x33,0x60,0x43,0x4f,0x9e,0xd5,0xe4,0xe5,0x37,0x2d,0xd3,0x56,0xba,0xf5,0xcb,0x5d,
++            0x16,0x5a,0x0b,0x59,0x72,0x6d,0x4d,0x1b,0x34,0x92,0x64,0x4c,0x7a,0x90,0x12,0x78,
++            0x20,0x52,0x84,0xbf,0x58,0xab,0xcb,0xa1,0xbc,0x52,0x2b,0x01,0xba,0x7d,0x34,0x6f,
++            0xd4,0x72,0x33,0x7c,0x35,0x5d,0x7a,0x39,0x62,0x31,0x63,0xca,0x5f,0xae,0x80,0x31,
++            0x5d,0xb3,0x85,0x01,0xac,0xb1,0xc8,0xa5,0x5d,0x3c,0x6e,0xda,0x98,0x7f,0x22,0xee,
++            0x78,0x8c,0x59,0xcb,0x9f,0xef,0x9d,0xb5,0x0e,0xfe,0x22,0x84,0xf7,0xdc,0x7a,0x55,
++            0xad,0x92,0xa2,0xf9,0x33,0x54,0x0a,0x0f,0x70,0x06,0x6f,0x55,0x64,0xdb,0xdc,0xb0,
++            0x21,0xb1,0x98,0x74,0x92,0x17,0xdc,0xf4,0x25,0xf8,0xe2,0x74,0xfe,0xd3,0x45,0x81,
++            0xc0,0xbb,0x45,0xd4,0xd8,0x9b,0xd5,0xe5,0xca,0x64,0x14,0xe1,0xb2,0x7c,0x8d,0xd7,
++            0x6b,0x35,0x93,0x44,0x21,0x9c,0x9b,0x36,0x21,0x57,0x8d,0xb5,0xff,0x37,0x56,0x80,
++            0x64,0xa5,0xef,0x67,0x50,0xfa,0xc6,0x08,0xc9,0xf8,0x56,0xd2,0x12,0x5a,0xda,0x62,
++            0xc0,0xa8,0xc8,0x6f,0x73,0x9d,0x9a,0xca,0x82,0x0b,0x58,0x82,0x33,0x8c,0x11,0xeb,
++            0x53,0x87,0xf9,0x19,0x4d,0x99,0x49,0x25,0xe0,0x5e,0xe9,0x2c,0x30,0x2b,0x25,0x49,
++            0x0a,0x93,0xdf,0x15,0x9b,0x4b,0xa2,0xc9,0xed,0x50,0x5d,0xa3,0x3f,0x8f,0xe2,0xbb,
++            0xdf,0xb8,0x04,0x4e,0x51,0xde,0x5e,0xc9,0x83,0x1d,0xd0,0x40,0x93,0x5f,0xc4,0xda,
++            0x73,0xb9,0x90,0x55,0x99,0x39,0xfe,0xeb,0x61,0x39,0x98,0x76,0x10,0xbf,0xf8,0x2b,
++            0xac,0x6e,0xc3,0x3c,0xa8,0x28,0x4f,0x69,0x22,0x1c,0x87,0x8f,0xf0,0xd5,0x8f,0xdf,
++            0x63,0x3d,0x48,0x2c,0xf1,0x29,0x61,0x87,0x23,0xa2,0xb7,0x0c,0xb5,0x5f,0x97,0x26,
++            0x22,0xc0,0xde,0x83,0xfd,0x43,0x98,0xa8,0x94,0x54,0xe6,0xa3,0xbf,0x82,0x9f,0x13,
++            0x88,0x8d,0x7a,0xb3,0xe2,0x5c,0xb8,0xf4,0xd7,0xc2,0x47,0x45,0x33,0x82,0x21,0x27,
++            0x0b,0x80,0xb7,0x65,0x6b,0x0f,0x16,0x38,0xaf,0xb6,0x8f,0x92,0xbc,0xef,0x41,0xe2,
++            0x8f,0x67,0xbf,0x87,0x7e,0x21,0xda,0xc8,0xe7,0xd3,0x42,0x48,0xbd,0x61,0x76,0x2c,
++            0x89,0x02,0x0c,0xd5,0x18,0xae,0xa4,0x9c,0xbb,0x65,0x4b,0xc3,0xa1,0x19,0xe8,0x05,
++            0x6c,0xfa,0xd6,0xf2,0x36,0x05,0x2e,0xf7,0xac,0xe7,0x43,0xc6,0x9b,0x4a,0x61,0x83,
++            0x8a,0xc6,0x65,0x43,0xde,0xf5,0x33,0x90,0xc0,0x1b,0xe3,0x25,0x3d,0x94,0xed,0xa2,
++            0x38,0x84,0xb7,0xcf,0x9f,0xa3,0x91,0x6e,0xe5,0x11,0x38,0x48,0x85,0x1a,0x7c,0x8e,
++            0x8d,0x23,0x19,0xbf,0x12,0x07,0x30,0xd7,0x4c,0xcc,0xcc,0xbe,0xa9,0x4b,0x02,0x5c,
++            0x51,0x7c,0xe8,0x9a,0x19,0x89,0x7f,0x9a,0x59,0x49,0xfe,0x2d,0x1f,0xab,0xe7,0x1c,
++            0xe7,0x08,0x67,0xfc,0x96,0x0e,0xb3,0xd6,0xc4,0x3e,0x77,0xdc,0xd2,0x45,0xbd,0xe7,
++            0x8d,0x3e,0x58,0x20,0xf1,0x70,0xe4,0x3f,0x4d,0x8b,0x13,0x22,0x21,0xb9,0xca,0xc0,
++            0x65,0x18,0x66,0x3c,0xf5,0x3e,0x0d,0xca,0xfd,0x73,0x26,0xfd,0xff,0x33,0x34,0x55,
++            0x4b,0xc3,0xf2,0x5b,0x1b,0xcd,0x89,0x04,0x87,0x7a,0x41,0xdb,0xa8,0x10,0x63,0xba,
++            0x56,0xce,0xdd,0xcb,0xff,0xee,0x55,0xd4,0x33,0x6a,0x4c,0x5e,0x7f,0x11,0x0a,0xfb,
++            0xd3,0x16,0xc2,0x2c,0x9d,0xc3,0x44,0x68,0x3d,0x52,0xed,0xf2,0x34,0x9d,0x25,0x71,
++            0xee,0x3b,0xa5,0x77,0x3a,0x54,0x7f,0x53,0x2e,0x64,0x52,0xd4,0x9f,0x56,0x0b,0x63,
++            0xc9,0x9d,0x79,0x67,0x3b,0x55,0xab,0x3a,0x47,0xa1,0x5f,0xa9,0xab,0x5e,0x42,0x8b,
++            0xcf,0x57,0xfb,0x17,0x35,0xb6,0x6b,0x37,0x65,0x76,0xeb,0x35,0xf0,0x26,0x73,0xa0,
++            0x25,0x38,0xf3,0x07,0x34,0x1e,0x6b,0xc0,0x8f,0x7b,0xda,0x46,0x27,0xb3,0xc0,0xb1,
++            0xd3,0x9b,0xba,0x52,0x34,0x1f,0x0c,0x66,0x7a,0x1c,0xaa,0x6e,0xe4,0x5f,0x2a,0x47,
++            0xce,0x97,0x8d,0x27,0x2d,0xb6,0xdc,0xe1,0x6d,0xb1,0xa2,0x67,0xe5,0x5e,0xd1,0xb0,
++            0x5b,0x99,0x23,0xc6,0xdd,0xa4,0x55,0xfa,0x2e,0x94,0xb0,0x05,0x76,0x06,0x33,0x31,
++            0xa3,0x12,0xbd,0xda,0x93,0x1a,0x43,0x8d,0x44,0xb2,0x3f,0x37,0x9c,0x15,0x14,0x9a,
++            0xa9,0x8e,0xf0,0xdf,0x5e,0xb3,0x64,0x4a,0x3e,0x2d,0xc8,0x98,0x97,0x1d,0x70,0x95,
++            0x7f,0xd7,0x99,0xa3,0xce,0xfb,0x45,0x3e,0x71,0x5a,0x8c,0xf8,0xef,0x56,0x04,0x91,
++            0x74,0x2e,0xe4,0xb0,0xdc,0x65,0x25,0x55,0x14,0xd9,0xe9,0x9c,0xec,0x55,0x4e,0x3b,
++            0x7b,0x24,0x2a,0x2f,0x40,0x1a,0x80,0x8a,0x4c,0x24,0x9c,0x4e,0x25,0xbb,0xd5,0x28,
++            0x46,0xde,0xa6,0xff,0x1c,0x43,0x48,0x95,0xcd,0xae,0xf2,0x1f,0x6c,0xea,0x2a,0x29,
++            0x25,0xc0,0xfc,0x26,0x3f,0xff,0x16,0x7c,0x93,0x9c,0x7b,0x62,0x83,0xff,0x19,0x4f,
++            0x5b,0x3d,0xdd,0x6a,0x49,0x0b,0xf7,0xeb,0x2b,0xd0,0xa9,0x66,0xdd,0xfd,0x71,0xea,
++            0x8c,0x0e,0x6a,0x6f,0x42,0x1e,0x93,0x7b,0x13,0xff,0x24,0xff,0x07,0x7e,0x5b,0x00,
++            0x06,0x70,0x7f,0xa1,0xda,0x2d,0x75,0xce,0xd9,0xbd,0x55,0x57,0x7a,0x63,0xf7,0x6e,
++            0x2f,0xde,0x77,0x6a,0x3f,0xfe,0x9a,0xdd,0x49,0x1a,0x47,0xb6,0xd1,0xe1,0x53,0x7e,
++            0xe8,0x0f,0x7a,0x7a,0xf8,0x2f,0x3c,0xcc,0xc8,0x46,0xa9,0x31,0xa7,0x74,0xb6,0x21,
++            0x00,0xac,0x36,0x24,0xd7,0x8c,0x7c,0xd8,0xc2,0x37,0x42,0xbf,0xae,0x61,0xc0,0x07,
++            0x2c,0xd8,0x82,0xb7,0x50,0xaf,0x94,0x5a,0x2a,0xd9,0x11,0x7e,0x39,0x06,0x5a,0x02,
++            0xe8,0xe7,0x0e,0x26,0x79,0xe7,0xdc,0x74,0x0f,0x04,0x18,0x68,0x38,0x57,0x95,0x1f,
++            0x11,0x39,0xc0,0x74,0xdc,0x89,0xbd,0xf3,0xc2,0x4c,0xd5,0x67,0xe2,0xcd,0xf2,0xe1,
++            0x5b,0xa8,0xb7,0xc1,0x5b,0x85,0x7f,0xf9,0x05,0xe3,0xea,0x84,0xc5,0x32,0xc7,0x76,
++            0x6a,0xec,0x40,0x72,0x72,0x8a,0x55,0x26,0x1e,0x7c,0x31,0xbc,0x84,0xca,0x34,0x98,
++            0x61,0xf8,0xcf,0xef,0x03,0xf4,0xd9,0x13,0x17,0x0b,0x5c,0x7e,0xd9,0xc2,0x7d,0x85,
++            0x08,0x0b,0xfd,0x9c,0x65,0x8b,0xd4,0x06,0x92,0x1f,0xcd,0xb9,0x00,0xc1,0xf4,0x6b,
++            0xa7,0xd4,0xdd,0x95,0x72,0x39,0x9e,0xb4,0x36,0x28,0xec,0x38,0xc7,0xc6,0x80,0x3b,
++            0x2c,0x0f,0x62,0x5f,0x58,0x48,0x17,0xff,0x21,0xea,0x8c,0xe9,0x52,0x68,0x4b,0xb5,
++            0x03,0x56,0xf2,0xaf,0x15,0x2e,0x7c,0xfc,0x9d,0xe9,0x84,0xf5,0xab,0xc6,0x7b,0x68,
++            0xa8,0x9e,0xfb,0xbe,0x9c,0x4b,0x57,0x98,0x08,0x6e,0x12,0x9c,0xdc,0x9e,0x2e,0xb0,
++            0x88,0x0b,0x28,0xa6,0xc9,0x6f,0x9f,0xe6,0xa0,0xf9,0x1a,0x2b,0xb0,0x0d,0x12,0xe2,
++            0xdf,0xcd,0xc4,0xbb,0x38,0x5c,0x50,0xd3,0x6a,0x3e,0xac,0xb0,0x07,0x66,0xc9,0x63,
++            0x3f,0xcc,0xab,0x15,0xcc,0xb0,0x3a,0x24,0xe5,0xf5,0x47,0x3e,0x0e,0x7b,0xd1,0x7f,
++            0x5d,0xb3,0xad,0x47,0x6c,0x30,0x77,0xa1,0xe1,0xeb,0x4a,0x67,0x70,0xf2,0x5b,0x1d,
++            0x4a,0x41,0xcd,0x66,0xab,0xbe,0x5b,0xb6,0x40,0x8c,0x3e,0x25,0x2d,0xd1,0x16,0x4b,
++            0x95,0x28,0x06,0xc5,0x59,0xd6,0x0a,0xfa,0x62,0xf0,0x2f,0xc3,0xd3,0x8b,0x6c,0xc4,
++            0x1c,0x35,0xec,0xc9,0x58,0xb7,0xde,0x36,0xf1,0x51,0xe9,0x7c,0x75,0x05,0xfa,0x8a,
++            0x9d,0x36,0xa4,0x34,0xa0,0x31,0xc3,0xfa,0x89,0x22,0x60,0x71,0x46,0x94,0x94,0x5a,
++            0x98,0x1d,0xac,0x24,0xf9,0x35,0x5a,0xb7,0x71,0xfc,0x96,0x0e,0x03,0x78,0x38,0x2c,
++            0x0a,0x15,0xd4,0x07,0xd3,0x2a,0xa2,0xca,0x97,0x2d,0xa8,0x34,0x8c,0x0a,0xd3,0x99,
++            0x1e,0x2f,0x8e,0x9e,0x3d,0xc2,0x5b,0x3c,0x75,0xc3,0x35,0x19,0xac,0x67,0x13,0x29,
++            0xf8,0x0a,0xd7,0x85,0xf8,0xc1,0xd1,0x87,0xfa,0x6f,0xce,0xa9,0x75,0x19,0x52,0x59,
++            0x29,0xcb,0x0f,0x82,0xaf,0xce,0x60,0x83,0x4a,0x19,0xe2,0x8d,0x78,0xd4,0xe3,0x51,
++            0xbe,0xce,0x98,0x58,0x32,0x97,0x75,0xe8,0xa2,0xbd,0x16,0xf4,0x29,0xd8,0xff,0x44,
++            0x93,0xef,0x9e,0xaf,0x39,0xbf,0xb6,0x72,0x08,0x7d,0x7a,0x82,0xd8,0x18,0x62,0x54,
++            0x16,0xac,0x01,0x47,0xd1,0x2c,0x70,0x18,0x76,0xbe,0x16,0xeb,0x32,0x4c,0x8f,0xd4,
++            0xb5,0xe0,0xd7,0x50,0xf9,0x36,0x49,0x64,0x00,0xad,0x60,0x1f,0x98,0x3f,0x17,0x32,
++            0x77,0x80,0x9e,0x96,0x7f,0xaf,0x56,0x40,0xb3,0x3d,0xe4,0x86,0xf5,0x20,0x3e,0x70,
++            0xfa,0x5c,0xbe,0x9b,0xfe,0xd3,0xec,0xcc,0xb8,0x60,0x98,0x26,0x22,0xf7,0xe1,0x0e,
++            0xe6,0x7f,0x21,0x35,0x60,0xad,0x27,0x41,0x3b,0x1f,0x6a,0xad,0xab,0xe5,0xfd,0xed,
++            0x78,0x02,0x12,0xa6,0x83,0x0c,0xfb,0xc0,0x83,0x1e,0x66,0x97,0x01,0x61,0xe3,0x31,
++            0x3a,0x05,0x62,0x41,0x4c,0xe4,0x71,0x10,0xad,0x52,0x70,0x64,0x06,0x4f,0x0d,0xbc,
++            0x9e,0x78,0x08,0x69,0x33,0xcb,0xbe,0x45,0x2c,0x60,0xcb,0x87,0x41,0xf9,0x29,0xbc,
++            0x67,0x05,0xe7,0xb6,0x15,0xa8,0x57,0xf7,0x22,0x62,0x31,0x7a,0xbd,0xd4,0x44,0xbe,
++            0x8f,0xf3,0xa9,0x68,0x9f,0xcb,0x59,0x00,0xaf,0x6c,0xa7,0xf2,0xd3,0x6a,0x0a,0xf9,
++            0x12,0x55,0x63,0x9f,0x16,0xac,0x64,0xbb,0xa7,0x6a,0x15,0xbf,0x37,0x2a,0x9d,0x82,
++            0xf0,0xea,0x2e,0x82,0x9e,0xa7,0x7f,0x44,0x27,0xdb,0x9a,0xeb,0xa7,0xa9,0x71,0x1c,
++            0x67,0xd8,0x80,0x9e,0x9a,0xea,0x8c,0x1a,0xd6,0x65,0x94,0xde,0x92,0x66,0x4d,0x79,
++            0x7a,0x76,0x4b,0x20,0xb9,0xc5,0x45,0xb3,0x05,0x9a,0x2e,0x4c,0xf7,0xe8,0x25,0x44,
++            0x58,0xb8,0xca,0x8c,0xc2,0xae,0x0a,0x62,0xae,0x63,0x8c,0xef,0xb7,0xce,0x69,0xda,
++            0xe6,0xfc,0xae,0xaf,0x5d,0xbb,0x38,0x09,0x45,0xcc,0xb2,0x6d,0x15,0xa9,0xa4,0x49,
++            0xd0,0x8d,0xdd,0xee,0xbc,0xa3,0x41,0x18,0xcc,0xc5,0x5f,0xfc,0xd8,0xe4,0x79,0x9b,
++            0x70,0x02,0xb5,0xce,0x1d,0x04,0x43,0x66,0x4a,0xd9,0xdd,0xef,0x53,0xe2,0x1a,0xaf,
++            0x44,0x9a,0x32,0x7a,0x34,0x05,0x37,0x7a,0xac,0xa2,0x72,0xd8,0x16,0x44,0xd5,0xd9,
++            0xd8,0xad,0x29,0x26,0xc8,0x10,0x87,0x50,0xc9,0x2c,0x82,0x17,0x57,0xfc,0xda,0xf1,
++            0xc6,0xa4,0xb3,0x7f,0xb4,0xf0,0x95,0xb0,0xf2,0xb6,0xcb,0x33,0x74,0xc3,0xf0,0x92,
++            0x39,0x21,0x95,0x64,0xe7,0x6e,0x45,0x43,0xed,0x72,0x3f,0x4b,0x67,0x08,0xb0,0x51,
++            0x87,0x4b,0x76,0x56,0x17,0x97,0x4e,0x53,0x30,0x7b,0xe2,0x77,0x9d,0x56,0xd7,0x77,
++            0xd0,0x68,0xee,0x36,0x76,0x1e,0x49,0x6f,0x61,0xa5,0xbe,0x06,0x73,0x54,0xda,0xf2,
++            0x07,0x69,0xa7,0xa7,0xc4,0x37,0xb6,0xcc,0xbc,0x89,0xcf,0x56,0xb4,0x59,0x7b,0x42,
++            0x4c,0x35,0x2d,0xcb,0xdc,0x85,0xb8,0x0c,0xc9,0x71,0xbc,0x04,0xe5,0x7a,0x87,0x16,
++            0xb4,0x6a,0x72,0x7d,0x22,0x03,0xf1,0x59,0x32,0x55,0xce,0xac,0x3c,0x23,0x6e,0xe9,
++            0x11,0x18,0x6f,0x5e,0x31,0xf9,0x8b,0x23,0xda,0xec,0xfc,0xa1,0x37,0x54,0x07,0x16,
++            0x8e,0x0a,0xa5,0xf4,0x33,0x1c,0x61,0x37,0x07,0x08,0xd6,0x52,0xdf,0x2e,0x67,0x64,
++            0x4c,0x18,0x29,0xab,0x47,0x3b,0xf8,0x3f,0xf1,0xa9,0xfc,0x81,0xe3,0xe0,0xdd,0x7b,
++            0x6c,0x33,0xd5,0x3f,0x28,0xb7,0x4e,0x14,0x93,0x7d,0xa0,0x7b,0x95,0x1e,0x10,0xdd,
++            0x8e,0x32,0x3c,0x2f,0x39,0x4d,0x85,0x85,0x07,0x7f,0x7e,0xcc,0x8b,0xf2,0x25,0xd8,
++            0xe4,0xda,0xb9,0x4a,0xb6,0xba,0x4f,0x14,0x1b,0xbd,0xc9,0x6a,0x95,0xf1,0xaf,0xfc,
++            0x0e,0x30,0xb1,0x56,0x4f,0x14,0x01,0x6a,0x1a,0x7c,0xe9,0x73,0x14,0xad,0xbb,0xb1,
++            0x1a,0xaf,0x9a,0x00,0x31,0x40,0x06,0xb8,0xab,0xd2,0x38,0x3c,0xd2,0x56,0x3d,0x63,
++            0x03,0x88,0xe0,0x92,0xed,0x60,0xdd,0x43,0x7d,0xe0,0x9a,0xf2,0x45,0x65,0x44,0x10,
++            0x8a,0x06,0x01,0x0d,0x9e,0x2c,0xaa,0x90,0xde,0xed,0xd9,0x47,0xf2,0xaf,0x0b,0x71,
++            0x8d,0x43,0xa1,0x77,0x10,0x2c,0x0a,0xc2,0xc7,0xce,0x19,0x73,0xc5,0x65,0x10,0x5f,
++            0x6e,0x1f,0xfa,0xc3,0xbe,0x38,0x38,0x67,0xc1,0x4b,0x34,0x97,0xf1,0xef,0xd1,0xb8,
++            0xbc,0x48,0xe6,0x53,0x86,0x2a,0xef,0x98,0xbc,0xc8,0x3f,0x87,0xf0,0x38,0x39,0x33,
++            0x25,0x02,0xef,0x43,0x03,0x7a,0x39,0x03,0xe4,0x0a,0xd5,0xe2,0xf6,0x1b,0x37,0xf4,
++            0x91,0x4a,0x7d,0x1f,0x5a,0x63,0xa3,0xbb,0x38,0xec,0x3a,0x31,0x70,0x5a,0x07,0x1d,
++            0xf3,0xb5,0xaa,0x0b,0x99,0x6c,0x6c,0xa9,0xa1,0x6a,0xf7,0xec,0xf9,0xe2,0x39,0xe9,
++            0x5f,0x18,0x8b,0x9e,0x18,0xd6,0x04,0x4b,0x6d,0x42,0x41,0x28,0x22,0x6f,0x5b,0x45,
++            0xe3,0xb8,0xab,0xcf,0xf3,0x24,0xbf,0xba,0xce,0x40,0x44,0xcf,0xa7,0x6a,0x55,0x94,
++            0x79,0xa0,0xb3,0x3d,0x38,0x4b,0xdd,0x2a,0x9b,0x0f,0xc0,0x3d,0x5b,0x23,0xbd,0xe8,
++            0xe7,0x8c,0xeb,0x02,0xd3,0x48,0x62,0x37,0x21,0x78,0xb5,0x28,0xf9,0x71,0x91,0x58,
++            0xdf,0x4c,0x74,0x5e,0xed,0x5a,0xda,0x74,0x8c,0x0d,0x36,0xfc,0xa7,0x4d,0x98,0x48,
++            0x0a,0x4e,0x6a,0x92,0x23,0xf0,0x53,0x98,0x42,0xb1,0xb0,0x3c,0x79,0x2f,0xf4,0xf9,
++            0x6e,0x8f,0xcf,0x49,0x03,0x6b,0x58,0x78,0x2a,0x29,0x77,0x3f,0x58,0xbb,0x41,0x1f,
++            0x4b,0x42,0x3c,0x77,0x58,0x22,0xd5,0xa6,0xa8,0x62,0x84,0xc6,0xc3,0x15,0x34,0x6f,
++            0xc8,0xd2,0x34,0x6b,0x3f,0x77,0xdc,0xbd,0x24,0xf1,0x65,0x93,0xd0,0x0e,0x6f,0xf2,
++            0xce,0xb3,0x3d,0x76,0xc8,0x20,0xb1,0xdf,0x3c,0x5d,0xad,0x4e,0x5c,0x7f,0xd9,0x6f,
++            0x5c,0xb2,0x8a,0xea,0x93,0xde,0xde,0xc2,0xb7,0x58,0x31,0x31,0xed,0x97,0x96,0x48,
++            0x87,0xbb,0xe3,0x26,0xd2,0xe5,0x7d,0xe7,0x63,0xd4,0x5b,0x60,0x2a,0x66,0x32,0x60,
++            0x33,0x58,0xb5,0xf3,0x92,0x24,0xd6,0x06,0xbc,0xd8,0x9d,0xcb,0x45,0x37,0x93,0x29,
++            0x45,0x5b,0x3e,0xe1,0x7b,0x39,0x2f,0x35,0x62,0x76,0x62,0x4c,0xf4,0xc6,0x33,0x60,
++            0x81,0x07,0xb5,0x86,0x10,0x28,0x7d,0xfc,0xeb,0x17,0xda,0x7d,0x0f,0xe4,0xc7,0x7b,
++            0x3e,0xc5,0x02,0x4b,0xb8,0x18,0x96,0xb9,0x32,0xf7,0xce,0x0d,0x13,0x49,0x30,0xa5,
++            0x41,0x1a,0xde,0xea,0x35,0x57,0x26,0x47,0x47,0xff,0x63,0xda,0x92,0x88,0x51,0x00,
++            0x43,0x28,0x2b,0x0b,0xa8,0xc7,0xb7,0xba,0xb2,0x3e,0x93,0xaf,0x88,0x61,0x71,0x1d,
++            0x29,0xea,0xaf,0x9c,0x34,0x7d,0x27,0x47,0x14,0xfa,0xde,0xdb,0x12,0x78,0x87,0xbb,
++            0x0c,0x1f,0xf8,0xca,0x70,0x78,0x54,0xe0,0x68,0x5d,0xf6,0x65,0x86,0x0f,0xdd,0x78,
++            0x7b,0x0d,0xf6,0x74,0x98,0x7c,0x32,0x8a,0x1c,0x7d,0x18,0xd3,0x2a,0xdd,0x7f,0xc1,
++            0x62,0x1d,0x9f,0xc9,0xf0,0x5a,0x5f,0xeb,0x68,0xee,0x91,0x40,0x07,0x77,0x6f,0x59,
++            0x63,0xee,0x3a,0xdc,0xaf,0x0b,0xbb,0x99,0x19,0x3a,0x54,0x8e,0xae,0x2a,0x63,0xe2,
++            0xcc,0x52,0x20,0x0a,0x67,0xbb,0x16,0xaf,0xc8,0xcd,0xa0,0x44,0xe7,0x85,0x10,0xed,
++            0x2b,0x27,0x2c,0x12,0x0d,0x4f,0xf9,0x34,0x8d,0xf3,0x41,0x11,0xf4,0x9e,0x81,0x10,
++            0xde,0xe6,0xdb,0x61,0xd6,0xa9,0xce,0x04,0x65,0x66,0x89,0xcc,0x78,0xef,0x11,0xed,
++            0x78,0x22,0xbb,0x26,0xb6,0xc3,0x9d,0x6c,0x66,0xa6,0x15,0xb3,0xc9,0x07,0xbf,0x43,
++            0x86,0xc4,0x41,0x41,0xb7,0xe5,0xc4,0x88,0xa7,0xa2,0xa5,0x79,0x60,0x50,0x31,0xbc,
++            0xa2,0x7a,0x1d,0xa8,0x13,0xc8,0x58,0x73,0xe0,0xd5,0xf3,0x76,0x3c,0x5d,0xbe,0x43,
++            0x5a,0xa5,0xa9,0x43,0x7b,0xe7,0xc5,0x23,0xca,0x09,0x24,0x68,0xa4,0x4d,0x39,0x20,
++            0xc7,0x5c,0x79,0x5c,0x13,0xf3,0x96,0x81,0x47,0xf6,0xf9,0x86,0x82,0x54,0x1a,0xf5,
++            0xf9,0xeb,0x22,0x02,0x04,0x29,0x8d,0xc8,0xcc,0x2a,0xea,0x3e,0xb7,0xd9,0x54,0x82,
++            0xf8,0x2a,0x2b,0xfb,0x2e,0xd6,0xff,0x3d,0xec,0x16,0x61,0x2a,0x26,0xef,0xd8,0x74,
++            0xe4,0x18,0xc8,0x6f,0x90,0xea,0x15,0xb3,0x48,0x6e,0x93,0x76,0xa3,0xca,0xee,0xe8,
++            0x93,0x20,0x13,0xec,0xad,0xb9,0x8f,0x59,0x32,0x6f,0xe0,0x3f,0x5f,0xa3,0x66,0x48,
++            0x0a,0x57,0x46,0x3c,0x90,0xed,0x48,0xed,0xe2,0xd3,0x2d,0x90,0x29,0x1b,0x20,0xc7,
++            0xe4,0x9e,0xdb,0xbc,0xc2,0x39,0x53,0x3d,0x61,0x41,0xe2,0x88,0xb6,0x9e,0x63,0x55,
++            0xa8,0x73,0x5c,0x54,0x3d,0x2b,0x39,0x7e,0xae,0x5e,0x33,0x77,0x26,0x13,0x32,0xb0,
++            0x2a,0x20,0x93,0x6d,0xaf,0x73,0x31,0x66,0x8e,0xce,0xe9,0x18,0x20,0x40,0x7a,0x1b,
++            0xd4,0x3b,0x21,0x6e,0x87,0xfd,0x0c,0x5d,0x91,0xb3,0xf5,0xc0,0x9f,0x81,0x1f,0x63,
++            0x77,0x5d,0x40,0x94,0x3d,0xdd,0x42,0x2a,0x90,0x72,0x82,0x8b,0x1d,0xf2,0xe6,0x47,
++            0xcf,0xe0,0x5a,0x27,0x5d,0xd2,0xce,0xdc,0x8c,0x40,0xf4,0xc1,0x1f,0x63,0x0b,0x0f,
++            0x21,0x37,0x4d,0x9e,0x48,0x39,0xf8,0x40,0xfb,0x58,0xc3,0x83,0x1c,0x82,0xf7,0x62,
++            0x76,0x34,0x44,0xc8,0xba,0xb9,0x8b,0x32,0x18,0xd7,0xfb,0x06,0x72,0x54,0x6d,0xd0,
++            0x2b,0x31,0x7c,0x16,0x73,0x51,0x87,0x80,0xe9,0xb0,0x79,0x7b,0x88,0xb7,0x43,0xfb,
++            0x92,0x92,0x9b,0x25,0x1a,0xbb,0x4b,0xea,0xa5,0x24,0xfa,0x77,0x4d,0xb4,0xfa,0xef,
++            0x6f,0xe6,0x95,0xde,0x5a,0x85,0x65,0xf2,0xb3,0x2b,0xfa,0x7f,0x77,0xba,0x61,0x8d,
++            0x8d,0x67,0x65,0xc9,0x32,0x17,0xb6,0x9b,0x7a,0x77,0xa0,0x96,0x97,0x79,0x91,0xab,
++            0x8c,0x66,0x96,0x3e,0xd0,0x39,0x40,0x33,0x25,0xfb,0xee,0xfe,0x3d,0x0c,0xf3,0x18,
++            0x0d,0x45,0x33,0x0d,0x26,0xb0,0xf6,0xd9,0x86,0xe8,0x89,0x92,0x73,0x5c,0x94,0x3e,
++            0x5a,0x66,0x47,0x87,0x3d,0xfb,0x1f,0x29,0xb5,0x66,0x28,0xbd,0xf9,0x0e,0xf7,0x0c,
++            0x2e,0x9a,0x76,0x61,0xc9,0x5c,0x3c,0xa8,0x06,0xd1,0xc8,0xb3,0x9d,0x03,0x16,0x7a,
++            0xd0,0x22,0x52,0x57,0x1b,0x89,0x44,0x7d,0xc3,0x82,0x09,0x00,0x9e,0xf2,0x6f,0xa5,
++            0xcd,0xbe,0x5b,0x3c,0x1d,0x8e,0x6f,0xc1,0xef,0xc9,0x37,0xf6,0xec,0xf8,0x07,0x19,
++            0x2c,0xdb,0x4f,0xd1,0x33,0x32,0x45,0x7c,0x43,0xc0,0x97,0x3d,0x79,0x0a,0x90,0x46,
++            0xfc,0xab,0xc4,0x80,0x10,0xe1,0xeb,0x3b,0xbf,0xeb,0x26,0x46,0xa7,0x66,0xf4,0xe0,
++            0x09,0x0e,0x48,0x10,0xe2,0x25,0x9c,0xc1,0xfe,0xc1,0x7b,0x73,0x8f,0x69,0x70,0x00,
++            0x02,0x0a,0xa1,0x1d,0x6c,0x41,0xec,0x88,0xe2,0x9d,0x99,0x12,0x71,0x0e,0xe1,0x3b,
++            0x06,0xf6,0x8f,0x2a,0xbf,0x61,0x47,0xde,0xc7,0xe8,0x1d,0xf2,0x51,0x43,0x40,0x40,
++            0x02,0x04,0xc0,0x44,0x12,0x24,0x50,0x60,0x42,0x44,0xd0,0x64,0x52,0x64,0x48,0x50,
++            0x03,0x05,0xc8,0x54,0x13,0x25,0x58,0x70,0x43,0x45,0xd8,0x74,0x53,0x65,0x41,0x41,
++            0x82,0x06,0xc1,0x45,0x92,0x26,0x51,0x61,0xc2,0x46,0xd1,0x65,0xd2,0x66,0x49,0x51,
++            0x83,0x07,0xc9,0x55,0x93,0x27,0x59,0x71,0xc3,0x47,0xd9,0x75,0xd3,0x67,0x62,0x4c,
++            0x04,0x83,0x04,0x21,0x2b,0x27,0xef,0xb9,0x23,0x37,0x3e,0xec,0xfb,0x29,0x8a,0x7a,
++            0x48,0x49,0xea,0x7c,0x53,0x24,0x44,0xd7,0x1b,0xe2,0x36,0x7e,0xda,0xc4,0x84,0xeb,
++            0x0a,0x42,0xd9,0x08,0x3f,0x6b,0x90,0x89,0x7b,0xf5,0x7f,0xad,0x24,0x4a,0x73,0x7b,
++            0xca,0xd4,0x27,0x8f,0x98,0x21,0xe6,0x3c,0xa2,0x34,0x8b,0xdd,0x91,0x6b,0x42,0x48,
++            0x0a,0x0c,0xc2,0x4c,0x1a,0x2c,0x52,0x68,0x4a,0x4c,0xd2,0x6c,0x5a,0x6c,0x4a,0x58,
++            0x0b,0x0d,0xca,0x5c,0x1b,0x2d,0x5a,0x78,0x4b,0x4d,0xda,0x7c,0x5b,0x6d,0x43,0x49,
++            0x8a,0x0e,0xc3,0x4d,0x9a,0x2e,0x53,0x69,0xca,0x4e,0xd3,0x6d,0xda,0x6e,0x4b,0x59,
++            0x8b,0x0f,0xcb,0x5d,0x9b,0x2f,0x5b,0x79,0xcb,0x4f,0xdb,0x7d,0xdb,0x6f,0xdf,0xf2,
++            0x9f,0xaf,0x68,0x04,0xcc,0x10,0xb4,0xb3,0x63,0x34,0xf6,0x24,0x70,0x30,0x6d,0xe2,
++            0xde,0xce,0xb4,0x67,0x33,0x95,0x3c,0xb1,0xec,0x17,0x26,0xb6,0xde,0x77,0xfa,0x7f,
++            0xa6,0x62,0x29,0x07,0xb1,0x27,0x2d,0x41,0xec,0x3c,0xb5,0x4f,0xf6,0xe2,0xcd,0x89,
++            0x59,0x9e,0xe2,0x14,0x79,0xed,0x9e,0x11,0xb5,0x63,0x95,0x6a,0x10,0x7c,0x44,0xc0,
++            0x22,0x14,0xc4,0xc4,0x32,0x34,0x54,0xe0,0x62,0x54,0xd4,0xe4,0x72,0x74,0x4c,0xd0,
++            0x23,0x15,0xcc,0xd4,0x33,0x35,0x5c,0xf0,0x63,0x55,0xdc,0xf4,0x73,0x75,0x45,0xc1,
++            0xa2,0x16,0xc5,0xc5,0xb2,0x36,0x55,0xe1,0xe2,0x56,0xd5,0xe5,0xf2,0x76,0x4d,0xd1,
++            0xa3,0x17,0xcd,0xd5,0xb3,0x37,0x5d,0xf1,0xe3,0x57,0xdd,0xf5,0xf3,0x77,0xf9,0x76,
++            0x2e,0xa8,0x46,0x9f,0xe7,0x5a,0x30,0x69,0xec,0xfc,0x06,0xad,0x58,0x78,0xce,0x98,
++            0x6d,0x58,0x3d,0x18,0xc1,0x1b,0x66,0x3c,0x31,0x25,0x9e,0xbc,0x79,0x79,0x32,0xfb,
++            0x57,0xc5,0x67,0xb2,0x44,0x58,0x5f,0xae,0x8b,0x7a,0x97,0xad,0xf8,0x7a,0xe3,0x19,
++            0x55,0x3b,0xbc,0x1d,0x9d,0x55,0xaf,0xa5,0x08,0x38,0x9f,0xbd,0xf9,0x7b,0x46,0xc8,
++            0x2a,0x1c,0xc6,0xcc,0x3a,0x3c,0x56,0xe8,0x6a,0x5c,0xd6,0xec,0x7a,0x7c,0x4e,0xd8,
++            0x2b,0x1d,0xce,0xdc,0x3b,0x3d,0x5e,0xf8,0x6b,0x5d,0xde,0xfc,0x7b,0x7d,0x47,0xc9,
++            0xaa,0x1e,0xc7,0xcd,0xba,0x3e,0x57,0xe9,0xea,0x5e,0xd7,0xed,0xfa,0x7e,0x4f,0xd9,
++            0xab,0x1f,0xcf,0xdd,0xbb,0x3f,0x5f,0xf9,0xeb,0x5f,0xdf,0xfd,0xfb,0x7f,0x58,0x80,
++            0x01,0x60,0x5e,0x84,0xea,0x1f,0x60,0x82,0xf7,0x7f,0xee,0x31,0x5c,0xe0,0xa0,0x06,
++            0xa4,0x09,0xd6,0x10,0xf4,0x22,0x50,0xf0,0xc3,0x34,0x28,0xf1,0x57,0x14,0x7b,0x1e,
++            0x27,0x84,0x99,0xf9,0xf4,0xae,0x82,0xdd,0x38,0x3d,0xd9,0xe5,0x52,0x17,0xa9,0xf1,
++            0x24,0x09,0xde,0xe4,0x19,0x5e,0xa9,0xf4,0xc7,0x36,0xbd,0x70,0x54,0xed,0x60,0x42,
++            0x06,0x84,0xe0,0x46,0x16,0xa4,0x70,0x62,0x46,0xc4,0xf0,0x66,0x56,0xe4,0x68,0x52,
++            0x07,0x85,0xe8,0x56,0x17,0xa5,0x78,0x72,0x47,0xc5,0xf8,0x76,0x57,0xe5,0x61,0x43,
++            0x86,0x86,0xe1,0x47,0x96,0xa6,0x71,0x63,0xc6,0xc6,0xf1,0x67,0xd6,0xe6,0x69,0x53,
++            0x87,0x87,0xe9,0x57,0x97,0xa7,0x79,0x73,0xc7,0xc7,0xf9,0x77,0xd7,0xe7,0xd9,0xe8,
++            0x0a,0x38,0xda,0x70,0x5c,0x22,0x36,0x6d,0xcd,0xc6,0x0d,0x8e,0xfd,0x48,0xba,0x9e,
++            0x55,0x81,0xd2,0x9c,0x3c,0xdb,0xfa,0x23,0x12,0x34,0x39,0xfc,0xde,0xaf,0xd0,0x6b,
++            0xec,0x81,0x74,0x8d,0x62,0x15,0x90,0xeb,0x10,0xe0,0x34,0x90,0xdc,0xca,0xf4,0x17,
++            0x8b,0x3b,0xf1,0x1e,0x3e,0xea,0x23,0xd5,0x05,0xe1,0x0c,0x1b,0xdb,0x5b,0x62,0x4a,
++            0x0e,0x8c,0xe2,0x4e,0x1e,0xac,0x72,0x6a,0x4e,0xcc,0xf2,0x6e,0x5e,0xec,0x6a,0x5a,
++            0x0f,0x8d,0xea,0x5e,0x1f,0xad,0x7a,0x7a,0x4f,0xcd,0xfa,0x7e,0x5f,0xed,0x63,0x4b,
++            0x8e,0x8e,0xe3,0x4f,0x9e,0xae,0x73,0x6b,0xce,0xce,0xf3,0x6f,0xde,0xee,0x6b,0x5b,
++            0x8f,0x8f,0xeb,0x5f,0x9f,0xaf,0x7b,0x7b,0xcf,0xcf,0xfb,0x7f,0xdf,0xef,0x88,0xc0,
++            0xa7,0x44,0xe4,0xb9,0x3c,0xdc,0xcb,0x60,0xe7,0x96,0xb4,0xa6,0x74,0xf0,0xd1,0x3b,
++            0x07,0x4e,0x43,0x66,0x6d,0xbe,0x2e,0x12,0x3d,0x83,0xbc,0xb6,0x75,0xf1,0xde,0x9c,
++            0x5b,0x39,0x8d,0x45,0x36,0xba,0x82,0x87,0xc6,0xe2,0xb5,0xa7,0xf4,0xf2,0xa9,0x62,
++            0x1a,0x13,0xcd,0xd7,0x4e,0xbe,0x0a,0x1b,0x19,0xb0,0xbd,0xb7,0xf5,0xf3,0x64,0xc2,
++            0x26,0x94,0xe4,0xc6,0x36,0xb4,0x74,0xe2,0x66,0xd4,0xf4,0xe6,0x76,0xf4,0x6c,0xd2,
++            0x27,0x95,0xec,0xd6,0x37,0xb5,0x7c,0xf2,0x67,0xd5,0xfc,0xf6,0x77,0xf5,0x65,0xc3,
++            0xa6,0x96,0xe5,0xc7,0xb6,0xb6,0x75,0xe3,0xe6,0xd6,0xf5,0xe7,0xf6,0xf6,0x6d,0xd3,
++            0xa7,0x97,0xed,0xd7,0xb7,0xb7,0x7d,0xf3,0xe7,0xd7,0xfd,0xf7,0xf7,0xf7,0x78,0x65,
++            0x2a,0x33,0xd4,0x97,0x7c,0x43,0xf6,0xbb,0x12,0x75,0xb6,0xae,0x7c,0xf8,0x2d,0x3a,
++            0x9e,0x26,0xae,0x5c,0xbe,0xff,0x66,0x32,0x84,0xca,0xbe,0xbe,0x7d,0xf9,0xda,0x1a,
++            0xc7,0xe5,0xa3,0x8d,0xb8,0x41,0x26,0x3b,0x85,0xb9,0xb7,0xaf,0xfc,0xfa,0x71,0x74,
++            0xbb,0x0f,0x18,0xbb,0x3f,0xb3,0x93,0x29,0xe9,0xd3,0xbf,0xbf,0xfd,0xfb,0x66,0xca,
++            0x2e,0x9c,0xe6,0xce,0x3e,0xbc,0x76,0xea,0x6e,0xdc,0xf6,0xee,0x7e,0xfc,0x6e,0xda,
++            0x2f,0x9d,0xee,0xde,0x3f,0xbd,0x7e,0xfa,0x6f,0xdd,0xfe,0xfe,0x7f,0xfd,0x67,0xcb,
++            0xae,0x9e,0xe7,0xcf,0xbe,0xbe,0x77,0xeb,0xee,0xde,0xf7,0xef,0xfe,0xfe,0x6f,0xdb,
++            0xaf,0x9f,0xef,0xdf,0xbf,0xbf,0x7f,0xfb,0xef,0xdf,0xff,0xff,0x88,0x9f,*/
++};
++#endif
++
++#endif
+\ No newline at end of file
+diff --git a/module_drivers/drivers/input/touchscreen/gt9xx_touch/gt9xx_update.c b/module_drivers/drivers/input/touchscreen/gt9xx_touch/gt9xx_update.c
+new file mode 100644
+index 000000000..499599af3
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/gt9xx_touch/gt9xx_update.c
+@@ -0,0 +1,2092 @@
++/*
++ * Goodix GT9xx touchscreen driver
++ *
++ * Copyright  (C)  2016 - 2017 Goodix. Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be a reference
++ * to you, when you are integrating the GOODiX's CTP IC into your system,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * Version: 2.8.0.1
++ * Release Date: 2017/11/24
++ */
++
++#include <linux/kthread.h>
++#include "gt9xx.h"
++
++#include <linux/namei.h>
++#include <linux/mount.h>
++#include <linux/firmware.h>
++#include <linux/ctype.h>
++
++#define GUP_REG_HW_INFO		0x4220
++#define GUP_REG_FW_MSG		0x41E4
++#define GUP_REG_PID_VID		0x8140
++
++#define FIRMWARE_NAME_LEN_MAX		256
++#define GOODIX_FIRMWARE_FILE_NAME	"goodix_firmware.bin"
++#define GOODIX_CONFIG_FILE_NAME		"goodix_config.cfg"
++
++#define FW_HEAD_LENGTH			14
++#define FW_SECTION_LENGTH		0x2000	/*  8K */
++#define FW_DSP_ISP_LENGTH		0x1000	/*  4K */
++#define FW_DSP_LENGTH			0x1000	/*  4K */
++#define FW_BOOT_LENGTH			0x800	/*  2K */
++#define FW_SS51_LENGTH		(4 * FW_SECTION_LENGTH)	/*  32K */
++#define FW_BOOT_ISP_LENGTH		0x800	/*  2k */
++#define FW_GLINK_LENGTH			0x3000	/*  12k */
++#define FW_GWAKE_LENGTH		(4 * FW_SECTION_LENGTH) /*  32k */
++
++#define PACK_SIZE			256
++#define MAX_FRAME_CHECK_TIME		5
++
++
++#define _bRW_MISCTL__SRAM_BANK		0x4048
++#define _bRW_MISCTL__MEM_CD_EN		0x4049
++#define _bRW_MISCTL__CACHE_EN		0x404B
++#define _bRW_MISCTL__TMR0_EN		0x40B0
++#define _rRW_MISCTL__SWRST_B0_		0x4180
++#define _bWO_MISCTL__CPU_SWRST_PULSE	0x4184
++#define _rRW_MISCTL__BOOTCTL_B0_	0x4190
++#define _rRW_MISCTL__BOOT_OPT_B0_	0x4218
++#define _rRW_MISCTL__BOOT_CTL_		0x5094
++
++#pragma pack(1)
++struct st_fw_head {
++	u8	hw_info[4];			 /* hardware info */
++	u8	pid[8];				 /* product id */
++	u16 vid;				 /* version id */
++};
++#pragma pack()
++
++struct st_update_msg {
++	u8 fw_damaged;
++	u8 fw_flag;
++	const u8 *fw_data;
++	struct file *cfg_file;
++	struct st_fw_head ic_fw_msg;
++	u32 fw_total_len;
++	u32 fw_burned_len;
++	const struct firmware *fw;
++} update_msg;
++
++struct st_update_msg update_msg;
++
++u16 show_len;
++u16 total_len;
++
++static u8 gup_burn_fw_gwake_section(struct i2c_client *client,
++				    u8 *fw_section, u16 start_addr,
++				    u32 len, u8 bank_cmd);
++
++static s32 gup_init_panel(struct goodix_ts_data *ts)
++{
++	s32 ret = 0;
++	u8 opr_buf[16];
++	u8 sensor_id = 0;
++	u8 drv_cfg_version;
++	u8 flash_cfg_version;
++	struct goodix_config_data *cfg = &ts->pdata->config;
++
++	if (cfg->length < GTP_CONFIG_MIN_LENGTH) {
++		dev_err(&ts->client->dev,
++			"No valid config with sensor_ID(%d) ",
++			sensor_id);
++
++		return -EPERM;
++	}
++
++	ret = gtp_i2c_read_dbl_check(ts->client, GTP_REG_CONFIG_DATA,
++				     &opr_buf[0], 1);
++	if (ret == SUCCESS) {
++		dev_dbg(&ts->client->dev,
++			"CFG_GROUP%d Config Version: %d, IC Config Version: %d",
++			sensor_id, cfg->data[GTP_ADDR_LENGTH], opr_buf[0]);
++
++		flash_cfg_version = opr_buf[0];
++		drv_cfg_version = cfg->data[GTP_ADDR_LENGTH];
++
++		if (flash_cfg_version < 90 &&
++		    flash_cfg_version > drv_cfg_version)
++			cfg->data[GTP_ADDR_LENGTH] = 0x00;
++	} else {
++		dev_err(&ts->client->dev,
++			"Failed to get ic config version!No config sent!");
++		return -EPERM;
++	}
++
++	ret = gtp_send_cfg(ts->client);
++	if (ret < 0)
++		dev_err(&ts->client->dev, "Send config error.");
++	else
++		usleep_range(10000, 11000);
++
++	/* restore config vrsion */
++	cfg->data[GTP_ADDR_LENGTH] = drv_cfg_version;
++
++	return 0;
++}
++
++
++static u8 gup_get_ic_msg(struct i2c_client *client, u16 addr, u8 *msg, s32 len)
++{
++	s32 i = 0;
++
++	msg[0] = (addr >> 8) & 0xff;
++	msg[1] = addr & 0xff;
++
++	for (i = 0; i < 5; i++) {
++		if (gtp_i2c_read(client, msg, GTP_ADDR_LENGTH + len) > 0)
++			break;
++	}
++
++	if (i >= 5) {
++		dev_err(&client->dev,
++				"Read data from 0x%02x%02x failed!",
++				msg[0], msg[1]);
++		return FAIL;
++	}
++
++	return SUCCESS;
++}
++
++static u8 gup_set_ic_msg(struct i2c_client *client, u16 addr, u8 val)
++{
++	s32 i = 0;
++	u8 msg[3];
++
++	msg[0] = (addr >> 8) & 0xff;
++	msg[1] = addr & 0xff;
++	msg[2] = val;
++
++	for (i = 0; i < 5; i++) {
++		if (gtp_i2c_write(client, msg, GTP_ADDR_LENGTH + 1) > 0)
++			break;
++	}
++
++	if (i >= 5) {
++		dev_err(&client->dev,
++			"Set data to 0x%02x%02x failed!", msg[0], msg[1]);
++		return FAIL;
++	}
++
++	return SUCCESS;
++}
++
++static u8 gup_get_ic_fw_msg(struct i2c_client *client)
++{
++	s32 ret = -1;
++	u8	retry = 0;
++	u8	buf[16];
++	u8	i;
++
++	/*  step1:get hardware info */
++	ret = gtp_i2c_read_dbl_check(client, GUP_REG_HW_INFO,
++				     &buf[GTP_ADDR_LENGTH], 4);
++	if (FAIL == ret) {
++		dev_err(&client->dev, "[get_ic_fw_msg]get hw_info failed,exit");
++		return FAIL;
++	}
++
++	/*  buf[2~5]: 00 06 90 00
++	 *  hw_info: 00 90 06 00
++	 */
++	for (i = 0; i < 4; i++)
++		update_msg.ic_fw_msg.hw_info[i] = buf[GTP_ADDR_LENGTH + 3 - i];
++		dev_dbg(&client->dev,
++			"IC Hardware info:%02x%02x%02x%02x",
++			update_msg.ic_fw_msg.hw_info[0],
++			update_msg.ic_fw_msg.hw_info[1],
++			update_msg.ic_fw_msg.hw_info[2],
++			update_msg.ic_fw_msg.hw_info[3]);
++	/*  step2:get firmware message */
++	for (retry = 0; retry < 2; retry++) {
++		ret = gup_get_ic_msg(client, GUP_REG_FW_MSG, buf, 1);
++		if (FAIL == ret) {
++			dev_err(&client->dev, "Read firmware message fail.");
++			return ret;
++		}
++
++		update_msg.fw_damaged = buf[GTP_ADDR_LENGTH];
++		if ((0xBE != update_msg.fw_damaged) && (!retry)) {
++			dev_info(&client->dev, "The check sum in ic is error.");
++			dev_info(&client->dev, "The IC will be updated by force.");
++			continue;
++		}
++		break;
++	}
++	dev_dbg(&client->dev,
++		"IC force update flag:0x%x", update_msg.fw_damaged);
++
++	/*  step3:get pid & vid */
++	ret = gtp_i2c_read_dbl_check(client, GUP_REG_PID_VID,
++				     &buf[GTP_ADDR_LENGTH], 6);
++	if (FAIL == ret) {
++		dev_err(&client->dev, "[get_ic_fw_msg]get pid & vid failed,exit");
++		return FAIL;
++	}
++
++	memset(update_msg.ic_fw_msg.pid, 0, sizeof(update_msg.ic_fw_msg.pid));
++	memcpy(update_msg.ic_fw_msg.pid, &buf[GTP_ADDR_LENGTH], 4);
++	dev_dbg(&client->dev, "IC Product id:%s", update_msg.ic_fw_msg.pid);
++
++	/* GT9XX PID MAPPING */
++	/*|-----FLASH-----RAM-----|
++	 *|------918------918-----|
++	 *|------968------968-----|
++	 *|------913------913-----|
++	 *|------913P-----913P----|
++	 *|------927------927-----|
++	 *|------927P-----927P----|
++	 *|------9110-----9110----|
++	 *|------9110P----9111----|*/
++	if (update_msg.ic_fw_msg.pid[0] != 0) {
++		if (!memcmp(update_msg.ic_fw_msg.pid, "9111", 4)) {
++			dev_dbg(&client->dev, "IC Mapping Product id:%s",
++					update_msg.ic_fw_msg.pid);
++			memcpy(update_msg.ic_fw_msg.pid, "9110P", 5);
++		}
++	}
++
++	update_msg.ic_fw_msg.vid = buf[GTP_ADDR_LENGTH + 4] +
++				   (buf[GTP_ADDR_LENGTH + 5] << 8);
++	dev_dbg(&client->dev, "IC version id:%04x", update_msg.ic_fw_msg.vid);
++
++	return SUCCESS;
++}
++
++s32 gup_enter_update_mode(struct i2c_client *client)
++{
++	s32 ret = -1;
++	s32 retry = 0;
++	u8 rd_buf[3];
++
++	struct goodix_ts_data *ts = i2c_get_clientdata(client);
++
++	/* step1:RST output low last at least 2ms */
++	if (!gpio_is_valid(ts->pdata->rst_gpio)) {
++		dev_err(&ts->client->dev, "update failed, no rst pin\n");
++		return FAIL;
++	}
++	gpio_direction_output(ts->pdata->rst_gpio, 0);
++	usleep_range(2000, 3000);
++
++	/* step2:select I2C slave addr,INT:0--0xBA;1--0x28. */
++	gtp_int_output(ts, client->addr == 0x14);
++	usleep_range(2000, 3000);
++
++	/* step3:RST output high reset guitar */
++	gpio_direction_output(ts->pdata->rst_gpio, 1);
++
++	/* 20121211 modify start */
++	usleep_range(5000, 6000);
++	while (retry++ < 200) {
++		/* step4:Hold ss51 & dsp */
++		ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
++		if (ret <= 0) {
++			dev_dbg(&client->dev,
++				"Hold ss51 & dsp I2C error,retry:%d",
++				retry);
++			continue;
++		}
++
++		/* step5:Confirm hold */
++		ret = gup_get_ic_msg(client, _rRW_MISCTL__SWRST_B0_, rd_buf, 1);
++		if (ret <= 0) {
++			dev_dbg(&client->dev,
++				"Hold ss51 & dsp I2C error,retry:%d",
++				retry);
++			continue;
++		}
++		if (0x0C == rd_buf[GTP_ADDR_LENGTH]) {
++			dev_dbg(&client->dev, "Hold ss51 & dsp confirm SUCCESS");
++			break;
++		}
++		dev_dbg(&client->dev,
++			"Hold ss51 & dsp confirm 0x4180 failed,value:%d",
++			rd_buf[GTP_ADDR_LENGTH]);
++	}
++	if (retry >= 200) {
++		dev_err(&client->dev, "Enter update Hold ss51 failed.");
++		return FAIL;
++	}
++
++	/* step6:DSP_CK and DSP_ALU_CK PowerOn */
++	ret = gup_set_ic_msg(client, 0x4010, 0x00);
++
++	/* 20121211 modify end */
++	return ret;
++}
++
++void gup_leave_update_mode(struct i2c_client *client)
++{
++	struct goodix_ts_data *ts = i2c_get_clientdata(client);
++
++	if (ts->pdata->int_sync && ts->pinctrl.pinctrl)
++		pinctrl_select_state(ts->pinctrl.pinctrl,
++				     ts->pinctrl.int_input);
++	else if (ts->pdata->int_sync && gpio_is_valid(ts->pdata->irq_gpio))
++		gpio_direction_input(ts->pdata->irq_gpio);
++	dev_dbg(&client->dev, "[leave_update_mode]reset chip.");
++	gtp_reset_guitar(i2c_connect_client, 20);
++}
++
++static u8 gup_enter_update_judge(struct i2c_client *client,
++				 struct st_fw_head *fw_head)
++{
++	u16 u16_tmp;
++	s32 i = 0;
++	u32 fw_len = 0;
++	s32 pid_cmp_len = 0;
++
++	u16_tmp = fw_head->vid;
++	fw_head->vid = (u16)(u16_tmp>>8) + (u16)(u16_tmp<<8);
++
++	dev_info(&client->dev, "FILE HARDWARE INFO:%*ph\n", 4,
++		 &fw_head->hw_info[0]);
++	dev_info(&client->dev, "FILE PID:%s\n", fw_head->pid);
++	dev_info(&client->dev, "FILE VID:%04x\n", fw_head->vid);
++
++	dev_info(&client->dev, "IC HARDWARE INFO:%*ph\n", 4,
++		 &update_msg.ic_fw_msg.hw_info[0]);
++	dev_info(&client->dev, "IC PID:%s\n", update_msg.ic_fw_msg.pid);
++	dev_info(&client->dev, "IC VID:%04x\n", update_msg.ic_fw_msg.vid);
++
++	if (!memcmp(fw_head->pid, "9158", 4) &&
++	    !memcmp(update_msg.ic_fw_msg.pid, "915S", 4)) {
++		dev_info(&client->dev, "Update GT915S to GT9158 directly!");
++		return SUCCESS;
++	}
++	/* First two conditions */
++	if (!memcmp(fw_head->hw_info, update_msg.ic_fw_msg.hw_info,
++	sizeof(update_msg.ic_fw_msg.hw_info))) {
++		fw_len = 42 * 1024;
++	} else {
++		fw_len = fw_head->hw_info[3];
++		fw_len += (((u32)fw_head->hw_info[2]) << 8);
++		fw_len += (((u32)fw_head->hw_info[1]) << 16);
++		fw_len += (((u32)fw_head->hw_info[0]) << 24);
++	}
++	if (update_msg.fw_total_len != fw_len) {
++		dev_err(&client->dev,
++			"Inconsistent firmware size, Update aborted!");
++		dev_err(&client->dev,
++			" Default size: %d(%dK), actual size: %d(%dK)",
++			fw_len, fw_len/1024, update_msg.fw_total_len,
++			update_msg.fw_total_len/1024);
++		return FAIL;
++	}
++	dev_info(&client->dev, "Firmware length:%d(%dK)",
++		 update_msg.fw_total_len,
++		 update_msg.fw_total_len/1024);
++
++	if (update_msg.fw_damaged != 0xBE) {
++		dev_info(&client->dev, "FW chksum error,need enter update.");
++		return SUCCESS;
++	}
++
++	/*  20130523 start */
++	if (strlen(update_msg.ic_fw_msg.pid) < 3) {
++		dev_info(&client->dev, "Illegal IC pid, need enter update");
++		return SUCCESS;
++	}
++
++	/* check pid legality */
++	for (i = 0; i < 3; i++) {
++		if (!isdigit(update_msg.ic_fw_msg.pid[i])) {
++			dev_info(&client->dev,
++				 "Illegal IC pid, need enter update");
++			return SUCCESS;
++		}
++	}
++	/*  20130523 end */
++
++	pid_cmp_len = strlen(fw_head->pid);
++	if (pid_cmp_len < strlen(update_msg.ic_fw_msg.pid))
++		pid_cmp_len = strlen(update_msg.ic_fw_msg.pid);
++
++	if ((!memcmp(fw_head->pid, update_msg.ic_fw_msg.pid, pid_cmp_len)) ||
++			(!memcmp(update_msg.ic_fw_msg.pid, "91XX", 4)) ||
++			(!memcmp(fw_head->pid, "91XX", 4))) {
++		if (!memcmp(fw_head->pid, "91XX", 4))
++			dev_dbg(&client->dev,
++				"Force none same pid update mode.");
++		else
++			dev_dbg(&client->dev, "Get the same pid.");
++
++		/* The third condition */
++		if (fw_head->vid != update_msg.ic_fw_msg.vid) {
++			dev_info(&client->dev, "Need enter update.");
++			return SUCCESS;
++		}
++		dev_err(&client->dev, "File VID == Ic VID, update aborted!");
++	} else {
++		dev_err(&client->dev, "File PID != Ic PID, update aborted!");
++	}
++
++	return FAIL;
++}
++
++static int gup_update_config(struct i2c_client *client)
++{
++	s32 ret = 0;
++	s32 i = 0;
++	s32 file_cfg_len = 0;
++	u8 *file_config;
++	const struct firmware *fw_cfg;
++
++	struct goodix_ts_data *ts = i2c_get_clientdata(client);
++
++	ret = request_firmware(&fw_cfg, GOODIX_CONFIG_FILE_NAME,
++			       &client->dev);
++	if (ret < 0) {
++		dev_err(&client->dev,
++			"Cannot get config file - %s (%d)\n",
++			GOODIX_CONFIG_FILE_NAME, ret);
++		return -EFAULT;
++	}
++	if (!fw_cfg || !fw_cfg->data || fw_cfg->size > PAGE_SIZE) {
++		dev_err(&client->dev, "config file illegal");
++		ret = -EFAULT;
++		goto cfg_fw_err;
++	}
++
++	dev_dbg(&client->dev, "config firmware file len:%zu", fw_cfg->size);
++
++	file_config = kzalloc(GTP_CONFIG_MAX_LENGTH + GTP_ADDR_LENGTH,
++			      GFP_KERNEL);
++	if (!file_config) {
++		dev_err(&ts->client->dev, "failed alloc memory");
++		ret = -ENOMEM;
++		goto cfg_fw_err;
++	}
++	file_config[0] = GTP_REG_CONFIG_DATA >> 8;
++	file_config[1] = GTP_REG_CONFIG_DATA & 0xff;
++	file_cfg_len = gtp_ascii_to_array(fw_cfg->data, fw_cfg->size,
++					  &file_config[GTP_ADDR_LENGTH]);
++	if (file_cfg_len < 0) {
++		dev_err(&client->dev, "failed covert ascii to hex");
++		ret = -EFAULT;
++		goto update_cfg_file_failed;
++	}
++
++	GTP_DEBUG_ARRAY(file_config + GTP_ADDR_LENGTH, file_cfg_len);
++
++	i = 0;
++	while (i++ < 5) {
++		ret = gtp_i2c_write(client, file_config, file_cfg_len + 2);
++		if (ret > 0) {
++			dev_info(&client->dev, "Send config SUCCESS.");
++			msleep(500);
++			break;
++		}
++		dev_err(&ts->client->dev, "Send config i2c error.");
++	}
++
++update_cfg_file_failed:
++	kfree(file_config);
++cfg_fw_err:
++	release_firmware(fw_cfg);
++	return ret;
++}
++
++static u8 gup_check_firmware_name(struct i2c_client *client,
++		u8 **path_p)
++{
++	u8 len;
++	u8 *fname;
++
++	if (!(*path_p)) {
++		*path_p = GOODIX_FIRMWARE_FILE_NAME;
++		return 0;
++	}
++
++	len = strnlen(*path_p, FIRMWARE_NAME_LEN_MAX);
++	if (len >= FIRMWARE_NAME_LEN_MAX) {
++		dev_err(&client->dev, "firmware name too long!");
++		return -EINVAL;
++	}
++
++	fname = strrchr(*path_p, '/');
++	if (fname) {
++		fname = fname + 1;
++		*path_p = fname;
++	}
++
++	return 0;
++}
++
++static u8 gup_get_update_file(struct i2c_client *client,
++				struct st_fw_head *fw_head, u8 *path)
++{
++	s32 ret = 0;
++	s32 i = 0;
++	s32 fw_checksum = 0;
++	struct goodix_ts_data *ts = i2c_get_clientdata(client);
++
++	if (ts->pdata->auto_update_cfg) {
++		ret = gup_update_config(client);
++		if (ret <= 0)
++			dev_err(&client->dev, "Update config failed.");
++	}
++
++	ret = gup_check_firmware_name(client, &path);
++	if (ret < 0)
++		return FAIL;
++
++	ret = request_firmware(&update_msg.fw, path, &client->dev);
++	if (ret < 0) {
++		dev_err(&client->dev, "Failed get firmware:%d\n", ret);
++		return FAIL;
++	}
++
++	dev_info(&client->dev, "FW File: %s size=%zu",
++		 path, update_msg.fw->size);
++	update_msg.fw_data = update_msg.fw->data;
++	update_msg.fw_total_len = update_msg.fw->size;
++
++	if (update_msg.fw_total_len <
++	    FW_HEAD_LENGTH + FW_SECTION_LENGTH * 4 + FW_DSP_ISP_LENGTH +
++	    FW_DSP_LENGTH + FW_BOOT_LENGTH) {
++		dev_err(&client->dev,
++			"INVALID bin file(size: %d), update aborted.",
++			update_msg.fw_total_len);
++		goto invalied_fw;
++	}
++
++	update_msg.fw_total_len -= FW_HEAD_LENGTH;
++
++	dev_dbg(&client->dev, "Bin firmware actual size: %d(%dK)",
++		update_msg.fw_total_len, update_msg.fw_total_len/1024);
++
++	memcpy(fw_head, update_msg.fw_data, FW_HEAD_LENGTH);
++
++	/* check firmware legality */
++	fw_checksum = 0;
++	for (i = 0; i < update_msg.fw_total_len; i += 2) {
++		u16 temp;
++
++		temp = (update_msg.fw_data[FW_HEAD_LENGTH + i] << 8) +
++			update_msg.fw_data[FW_HEAD_LENGTH + i + 1];
++		fw_checksum += temp;
++	}
++
++	dev_dbg(&client->dev, "firmware checksum:%x", fw_checksum&0xFFFF);
++	if (fw_checksum & 0xFFFF) {
++		dev_err(&client->dev, "Illegal firmware file.");
++		goto invalied_fw;
++	}
++
++	return SUCCESS;
++
++invalied_fw:
++	update_msg.fw_data = NULL;
++	update_msg.fw_total_len = 0;
++	release_firmware(update_msg.fw);
++	return FAIL;
++}
++
++static u8 gup_burn_proc(struct i2c_client *client, u8 *burn_buf,
++		u16 start_addr, u16 total_length)
++{
++	s32 ret = 0;
++	u16 burn_addr = start_addr;
++	u16 frame_length = 0;
++	u16 burn_length = 0;
++	u8 wr_buf[PACK_SIZE + GTP_ADDR_LENGTH];
++	u8 rd_buf[PACK_SIZE + GTP_ADDR_LENGTH];
++	u8 retry = 0;
++
++	dev_dbg(&client->dev, "Begin burn %dk data to addr 0x%x",
++		total_length / 1024, start_addr);
++	while (burn_length < total_length) {
++		dev_dbg(&client->dev,
++			"B/T:%04d/%04d", burn_length, total_length);
++		frame_length = ((total_length - burn_length)
++		> PACK_SIZE) ? PACK_SIZE : (total_length - burn_length);
++		wr_buf[0] = (u8)(burn_addr>>8);
++		rd_buf[0] = wr_buf[0];
++		wr_buf[1] = (u8)burn_addr;
++		rd_buf[1] = wr_buf[1];
++		memcpy(&wr_buf[GTP_ADDR_LENGTH],
++		&burn_buf[burn_length], frame_length);
++
++		for (retry = 0; retry < MAX_FRAME_CHECK_TIME; retry++) {
++			ret = gtp_i2c_write(client,
++			wr_buf, GTP_ADDR_LENGTH + frame_length);
++			if (ret <= 0) {
++				dev_err(&client->dev,
++					"Write frame data i2c error.");
++				continue;
++			}
++			ret = gtp_i2c_read(client, rd_buf,
++					   GTP_ADDR_LENGTH + frame_length);
++			if (ret <= 0) {
++				dev_err(&client->dev,
++					"Read back frame data i2c error.");
++				continue;
++			}
++			if (memcmp(&wr_buf[GTP_ADDR_LENGTH],
++				&rd_buf[GTP_ADDR_LENGTH], frame_length)) {
++				dev_err(&client->dev,
++					"Check frame data fail,not equal.");
++				dev_dbg(&client->dev, "write array:");
++				GTP_DEBUG_ARRAY(&wr_buf[GTP_ADDR_LENGTH],
++				frame_length);
++				dev_dbg(&client->dev, "read array:");
++				GTP_DEBUG_ARRAY(&rd_buf[GTP_ADDR_LENGTH],
++				frame_length);
++				continue;
++			} else {
++				/* dev_dbg(&client->dev,
++				 * "Check frame data success.");
++				 */
++				break;
++			}
++		}
++		if (retry >= MAX_FRAME_CHECK_TIME) {
++			dev_err(&client->dev,
++				"Burn frame data time out,exit.");
++			return FAIL;
++		}
++		burn_length += frame_length;
++		burn_addr += frame_length;
++	}
++
++	return SUCCESS;
++}
++
++static u8 gup_load_section_file(u8 *buf, u32 offset, u16 length, u8 set_or_end)
++{
++	if (!update_msg.fw_data ||
++	    update_msg.fw_total_len < offset + length) {
++		dev_err(&i2c_connect_client->dev,
++			"cannot load section data. fw_len=%d read end=%d\n",
++			update_msg.fw_total_len,
++			FW_HEAD_LENGTH + offset + length);
++		return FAIL;
++	}
++
++	if (SEEK_SET == set_or_end) {
++		memcpy(buf, &update_msg.fw_data[FW_HEAD_LENGTH + offset],
++		       length);
++	} else {
++		/* seek end */
++		memcpy(buf, &update_msg.fw_data[update_msg.fw_total_len +
++		       FW_HEAD_LENGTH - offset], length);
++	}
++
++	return SUCCESS;
++}
++
++static u8 gup_recall_check(struct i2c_client *client, u8 *chk_src,
++			   u16 start_rd_addr, u16 chk_length)
++{
++	u8 rd_buf[PACK_SIZE + GTP_ADDR_LENGTH];
++	s32 ret = 0;
++	u16 recall_addr = start_rd_addr;
++	u16 recall_length = 0;
++	u16 frame_length = 0;
++
++	while (recall_length < chk_length) {
++		frame_length = ((chk_length - recall_length)
++				> PACK_SIZE) ? PACK_SIZE :
++				(chk_length - recall_length);
++		ret = gup_get_ic_msg(client, recall_addr, rd_buf, frame_length);
++		if (ret <= 0) {
++			dev_err(&client->dev, "recall i2c error,exit");
++			return FAIL;
++		}
++
++		if (memcmp(&rd_buf[GTP_ADDR_LENGTH],
++		&chk_src[recall_length], frame_length)) {
++			dev_err(&client->dev, "Recall frame data fail,not equal.");
++			dev_dbg(&client->dev, "chk_src array:");
++			GTP_DEBUG_ARRAY(&chk_src[recall_length], frame_length);
++			dev_dbg(&client->dev, "recall array:");
++			GTP_DEBUG_ARRAY(&rd_buf[GTP_ADDR_LENGTH], frame_length);
++			return FAIL;
++		}
++
++		recall_length += frame_length;
++		recall_addr += frame_length;
++	}
++	dev_dbg(&client->dev,
++			"Recall check %dk firmware success.",
++			(chk_length/1024));
++
++	return SUCCESS;
++}
++
++static u8 gup_burn_fw_section(struct i2c_client *client, u8 *fw_section,
++			      u16 start_addr, u8 bank_cmd)
++{
++	s32 ret = 0;
++	u8	rd_buf[5];
++
++	/* step1:hold ss51 & dsp */
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_section]hold ss51 & dsp fail.");
++		return FAIL;
++	}
++
++	/* step2:set scramble */
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_section]set scramble fail.");
++		return FAIL;
++	}
++
++	/* step3:select bank */
++	ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK,
++	(bank_cmd >> 4)&0x0F);
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_fw_section]select bank %d fail.",
++			(bank_cmd >> 4)&0x0F);
++		return FAIL;
++	}
++
++	/* step4:enable accessing code */
++	ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_fw_section]enable accessing code fail.");
++		return FAIL;
++	}
++
++	/* step5:burn 8k fw section */
++	ret = gup_burn_proc(client, fw_section, start_addr, FW_SECTION_LENGTH);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_section]burn fw_section fail.");
++		return FAIL;
++	}
++
++	/* step6:hold ss51 & release dsp */
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04);
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_fw_section]hold ss51 & release dsp fail.");
++		return FAIL;
++	}
++	/* must delay */
++	usleep_range(1000, 2000);
++
++	/* step7:send burn cmd to move data to flash from sram */
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, bank_cmd&0x0f);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_section]send burn cmd fail.");
++		return FAIL;
++	}
++	dev_dbg(&client->dev,
++		"[burn_fw_section]Wait for the burn is complete......");
++	do {
++		ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
++		if (ret <= 0) {
++			dev_err(&client->dev,
++				"[burn_fw_section]Get burn state fail");
++			return FAIL;
++		}
++		usleep_range(10000, 11000);
++	/* dev_dbg(&client->dev, "[burn_fw_section]Get burn state:%d.",
++	 * rd_buf[GTP_ADDR_LENGTH]);
++	 */
++	} while (rd_buf[GTP_ADDR_LENGTH]);
++
++	/* step8:select bank */
++	ret = gup_set_ic_msg(client,
++			     _bRW_MISCTL__SRAM_BANK, (bank_cmd >> 4) & 0x0F);
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_fw_section]select bank %d fail.",
++			(bank_cmd >> 4)&0x0F);
++		return FAIL;
++	}
++
++	/* step9:enable accessing code */
++	ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_fw_section]enable accessing code fail.");
++		return FAIL;
++	}
++
++	/* step10:recall 8k fw section */
++	ret = gup_recall_check(client,
++	fw_section, start_addr, FW_SECTION_LENGTH);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_section]recall check %dk firmware fail.",
++			FW_SECTION_LENGTH / 1024);
++		return FAIL;
++	}
++
++	/* step11:disable accessing code */
++	ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x00);
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_fw_section]disable accessing code fail.");
++		return FAIL;
++	}
++
++	return SUCCESS;
++}
++
++static u8 gup_burn_dsp_isp(struct i2c_client *client)
++{
++	s32 ret = 0;
++	u8 *fw_dsp_isp = NULL;
++	u8	retry = 0;
++
++	dev_info(&client->dev, "[burn_dsp_isp]Begin burn dsp isp---->>");
++
++	/* step1:alloc memory */
++	dev_dbg(&client->dev, "[burn_dsp_isp]step1:alloc memory");
++	while (retry++ < 5) {
++		fw_dsp_isp = kzalloc(FW_DSP_ISP_LENGTH, GFP_KERNEL);
++		if (fw_dsp_isp == NULL) {
++			continue;
++		} else {
++			dev_info(&client->dev,
++				"[burn_dsp_isp]Alloc %dk byte memory success.",
++				FW_DSP_ISP_LENGTH / 1024);
++			break;
++		}
++	}
++	if (retry >= 5) {
++		dev_err(&client->dev, "[burn_dsp_isp]Alloc memory fail,exit.");
++		return FAIL;
++	}
++
++	/* step2:load dsp isp file data */
++	dev_dbg(&client->dev, "[burn_dsp_isp]step2:load dsp isp file data");
++	ret = gup_load_section_file(fw_dsp_isp, FW_DSP_ISP_LENGTH,
++				    FW_DSP_ISP_LENGTH, SEEK_END);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_dsp_isp]load firmware dsp_isp fail.");
++		goto exit_burn_dsp_isp;
++	}
++
++	/* step3:disable wdt,clear cache enable */
++	dev_dbg(&client->dev,
++		"[burn_dsp_isp]step3:disable wdt,clear cache enable");
++	ret = gup_set_ic_msg(client, _bRW_MISCTL__TMR0_EN, 0x00);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_dsp_isp]disable wdt fail.");
++		ret = FAIL;
++		goto exit_burn_dsp_isp;
++	}
++	ret = gup_set_ic_msg(client, _bRW_MISCTL__CACHE_EN, 0x00);
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_dsp_isp]clear cache enable fail.");
++		ret = FAIL;
++		goto exit_burn_dsp_isp;
++	}
++
++	/* step4:hold ss51 & dsp */
++	dev_dbg(&client->dev, "[burn_dsp_isp]step4:hold ss51 & dsp");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_dsp_isp]hold ss51 & dsp fail.");
++		ret = FAIL;
++		goto exit_burn_dsp_isp;
++	}
++
++	/* step5:set boot from sram */
++	dev_dbg(&client->dev, "[burn_dsp_isp]step5:set boot from sram");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOTCTL_B0_, 0x02);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_dsp_isp]set boot from sram fail");
++		ret = FAIL;
++		goto exit_burn_dsp_isp;
++	}
++
++	/* step6:software reboot */
++	dev_dbg(&client->dev, "[burn_dsp_isp]step6:software reboot");
++	ret = gup_set_ic_msg(client, _bWO_MISCTL__CPU_SWRST_PULSE, 0x01);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_dsp_isp]software reboot fail.");
++		ret = FAIL;
++		goto exit_burn_dsp_isp;
++	}
++
++	/* step7:select bank2 */
++	dev_dbg(&client->dev, "[burn_dsp_isp]step7:select bank2");
++	ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x02);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_dsp_isp]select bank2 fail");
++		ret = FAIL;
++		goto exit_burn_dsp_isp;
++	}
++
++	/* step8:enable accessing code */
++	dev_dbg(&client->dev, "[burn_dsp_isp]step8:enable accessing code");
++	ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_dsp_isp]enable accessing code fail.");
++		ret = FAIL;
++		goto exit_burn_dsp_isp;
++	}
++
++	/* step9:burn 4k dsp_isp */
++	dev_dbg(&client->dev, "[burn_dsp_isp]step9:burn 4k dsp_isp");
++	ret = gup_burn_proc(client, fw_dsp_isp, 0xC000, FW_DSP_ISP_LENGTH);
++	if (FAIL == ret) {
++		dev_err(&client->dev, "[burn_dsp_isp]burn dsp_isp fail.");
++		goto exit_burn_dsp_isp;
++	}
++
++	/* step10:set scramble */
++	dev_dbg(&client->dev, "[burn_dsp_isp]step10:set scramble");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_dsp_isp]set scramble fail.");
++		ret = FAIL;
++		goto exit_burn_dsp_isp;
++	}
++	update_msg.fw_burned_len += FW_DSP_ISP_LENGTH;
++	dev_dbg(&client->dev, "[burn_dsp_isp]Burned length:%d",
++			update_msg.fw_burned_len);
++	ret = SUCCESS;
++
++exit_burn_dsp_isp:
++	kfree(fw_dsp_isp);
++
++	return ret;
++}
++
++static u8 gup_burn_fw_ss51(struct i2c_client *client)
++{
++	u8 *fw_ss51 = NULL;
++	u8	retry = 0;
++	s32 ret = 0;
++
++	dev_info(&client->dev, "[burn_fw_ss51]Begin burn ss51 firmware---->>");
++
++	/* step1:alloc memory */
++	dev_dbg(&client->dev, "[burn_fw_ss51]step1:alloc memory");
++	while (retry++ < 5) {
++		fw_ss51 = kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
++		if (fw_ss51 == NULL) {
++			continue;
++		} else {
++			dev_dbg(&client->dev,
++				"[burn_fw_ss51]Alloc %dk byte memory success.",
++				(FW_SECTION_LENGTH / 1024));
++			break;
++		}
++	}
++	if (retry >= 5) {
++		dev_err(&client->dev, "[burn_fw_ss51]Alloc memory fail,exit.");
++		return FAIL;
++	}
++
++	dev_info(&client->dev, "[burn_fw_ss51]Reset first 8K of ss51 to 0xFF.");
++	dev_dbg(&client->dev, "[burn_fw_ss51]step2: reset bank0 0xC000~0xD000");
++	memset(fw_ss51, 0xFF, FW_SECTION_LENGTH);
++
++	/* step3:clear control flag */
++	dev_dbg(&client->dev, "[burn_fw_ss51]step3:clear control flag");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x00);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_ss51]clear control flag fail.");
++		ret = FAIL;
++		goto exit_burn_fw_ss51;
++	}
++
++	/* step4:burn ss51 firmware section 1 */
++	dev_dbg(&client->dev,
++		"[burn_fw_ss51]step4:burn ss51 firmware section 1");
++	ret = gup_burn_fw_section(client, fw_ss51, 0xC000, 0x01);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_ss51]burn ss51 firmware section 1 fail.");
++		goto exit_burn_fw_ss51;
++	}
++
++	/* step5:load ss51 firmware section 2 file data */
++	dev_dbg(&client->dev,
++		"[burn_fw_ss51]step5:load ss51 firmware section 2 file data");
++	ret = gup_load_section_file(fw_ss51, FW_SECTION_LENGTH,
++				    FW_SECTION_LENGTH, SEEK_SET);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_ss51]load ss51 firmware section 2 fail.");
++		goto exit_burn_fw_ss51;
++	}
++
++	/* step6:burn ss51 firmware section 2 */
++	dev_dbg(&client->dev,
++		"[burn_fw_ss51]step6:burn ss51 firmware section 2");
++	ret = gup_burn_fw_section(client, fw_ss51, 0xE000, 0x02);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_ss51]burn ss51 firmware section 2 fail.");
++		goto exit_burn_fw_ss51;
++	}
++
++	/* step7:load ss51 firmware section 3 file data */
++	dev_dbg(&client->dev,
++		"[burn_fw_ss51]step7:load ss51 firmware section 3 file data");
++	ret = gup_load_section_file(fw_ss51, 2 * FW_SECTION_LENGTH,
++				    FW_SECTION_LENGTH, SEEK_SET);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_ss51]load ss51 firmware section 3 fail.");
++		goto exit_burn_fw_ss51;
++	}
++
++	/* step8:burn ss51 firmware section 3 */
++	dev_dbg(&client->dev,
++		"[burn_fw_ss51]step8:burn ss51 firmware section 3");
++	ret = gup_burn_fw_section(client, fw_ss51, 0xC000, 0x13);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_ss51]burn ss51 firmware section 3 fail.");
++		goto exit_burn_fw_ss51;
++	}
++
++	/* step9:load ss51 firmware section 4 file data */
++	dev_dbg(&client->dev,
++		"[burn_fw_ss51]step9:load ss51 firmware section 4 file data");
++	ret = gup_load_section_file(fw_ss51, 3 * FW_SECTION_LENGTH,
++				    FW_SECTION_LENGTH, SEEK_SET);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_ss51]load ss51 firmware section 4 fail.");
++		goto exit_burn_fw_ss51;
++	}
++
++	/* step10:burn ss51 firmware section 4 */
++	dev_dbg(&client->dev,
++		"[burn_fw_ss51]step10:burn ss51 firmware section 4");
++	ret = gup_burn_fw_section(client, fw_ss51, 0xE000, 0x14);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_ss51]burn ss51 firmware section 4 fail.");
++		goto exit_burn_fw_ss51;
++	}
++
++	update_msg.fw_burned_len += (FW_SECTION_LENGTH*4);
++	dev_dbg(&client->dev, "[burn_fw_ss51]Burned length:%d",
++		update_msg.fw_burned_len);
++	ret = SUCCESS;
++
++exit_burn_fw_ss51:
++	kfree(fw_ss51);
++	return ret;
++}
++
++static u8 gup_burn_fw_dsp(struct i2c_client *client)
++{
++	s32 ret = 0;
++	u8 *fw_dsp = NULL;
++	u8 retry = 0;
++	u8 rd_buf[5];
++
++	dev_info(&client->dev, "[burn_fw_dsp]Begin burn dsp firmware---->>");
++	/* step1:alloc memory */
++	dev_dbg(&client->dev, "[burn_fw_dsp]step1:alloc memory");
++	while (retry++ < 5) {
++		fw_dsp = kzalloc(FW_DSP_LENGTH, GFP_KERNEL);
++		if (fw_dsp == NULL) {
++			continue;
++		} else {
++			dev_dbg(&client->dev,
++				"[burn_fw_dsp]Alloc %dk byte memory success.",
++				FW_SECTION_LENGTH / 1024);
++			break;
++		}
++	}
++	if (retry >= 5) {
++		dev_err(&client->dev, "[burn_fw_dsp]Alloc memory fail,exit.");
++		return FAIL;
++	}
++
++	/* step2:load firmware dsp */
++	dev_dbg(&client->dev, "[burn_fw_dsp]step2:load firmware dsp");
++	ret = gup_load_section_file(fw_dsp, 4 * FW_SECTION_LENGTH,
++				    FW_DSP_LENGTH, SEEK_SET);
++	if (FAIL == ret) {
++		dev_err(&client->dev, "[burn_fw_dsp]load firmware dsp fail.");
++		goto exit_burn_fw_dsp;
++	}
++
++	/* step3:select bank3 */
++	dev_dbg(&client->dev, "[burn_fw_dsp]step3:select bank3");
++	ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x03);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_dsp]select bank3 fail.");
++		ret = FAIL;
++		goto exit_burn_fw_dsp;
++	}
++
++	/* step4:hold ss51 & dsp */
++	dev_dbg(&client->dev, "[burn_fw_dsp]step4:hold ss51 & dsp");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_dsp]hold ss51 & dsp fail.");
++		ret = FAIL;
++		goto exit_burn_fw_dsp;
++	}
++
++	/* step5:set scramble */
++	dev_dbg(&client->dev, "[burn_fw_dsp]step5:set scramble");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_dsp]set scramble fail.");
++		ret = FAIL;
++		goto exit_burn_fw_dsp;
++	}
++
++	/* step6:release ss51 & dsp */
++	dev_dbg(&client->dev, "[burn_fw_dsp]step6:release ss51 & dsp");
++	ret = gup_set_ic_msg(
++	client, _rRW_MISCTL__SWRST_B0_, 0x04);/* 20121211 */
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_dsp]release ss51 & dsp fail.");
++		ret = FAIL;
++		goto exit_burn_fw_dsp;
++	}
++	/* must delay */
++	usleep_range(1000, 1100);
++
++	/* step7:burn 4k dsp firmware */
++	dev_dbg(&client->dev, "[burn_fw_dsp]step7:burn 4k dsp firmware");
++	ret = gup_burn_proc(client, fw_dsp, 0x9000, FW_DSP_LENGTH);
++	if (FAIL == ret) {
++		dev_err(&client->dev, "[burn_fw_dsp]burn fw_section fail.");
++		goto exit_burn_fw_dsp;
++	}
++
++	/* step8:send burn cmd to move data to flash from sram */
++	dev_dbg(&client->dev,
++	"[burn_fw_dsp]step8:send burn cmd to move data to flash from sram");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x05);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_dsp]send burn cmd fail.");
++		goto exit_burn_fw_dsp;
++	}
++	dev_dbg(&client->dev, "[burn_fw_dsp]Wait for the burn is complete......");
++	do {
++		ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
++		if (ret <= 0) {
++			dev_err(&client->dev, "[burn_fw_dsp]Get burn state fail");
++			goto exit_burn_fw_dsp;
++		}
++		usleep_range(10000, 11000);
++	/* dev_dbg(&client->dev, "[burn_fw_dsp]Get burn state:%d.",
++	rd_buf[GTP_ADDR_LENGTH]); */
++	} while (rd_buf[GTP_ADDR_LENGTH]);
++
++	/* step9:recall check 4k dsp firmware */
++	dev_dbg(&client->dev,
++		"[burn_fw_dsp]step9:recall check 4k dsp firmware");
++	ret = gup_recall_check(client, fw_dsp, 0x9000, FW_DSP_LENGTH);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_dsp]recall check 4k dsp firmware fail.");
++		goto exit_burn_fw_dsp;
++	}
++
++	update_msg.fw_burned_len += FW_DSP_LENGTH;
++	dev_dbg(&client->dev, "[burn_fw_dsp]Burned length:%d",
++			update_msg.fw_burned_len);
++	ret = SUCCESS;
++
++exit_burn_fw_dsp:
++	kfree(fw_dsp);
++
++	return ret;
++}
++
++static u8 gup_burn_fw_boot(struct i2c_client *client)
++{
++	s32 ret = 0;
++	u8 *fw_boot = NULL;
++	u8	retry = 0;
++	u8	rd_buf[5];
++
++	dev_info(&client->dev,
++		 "[burn_fw_boot]Begin burn bootloader firmware---->>");
++
++	/* step1:Alloc memory */
++	dev_dbg(&client->dev, "[burn_fw_boot]step1:Alloc memory");
++	while (retry++ < 5) {
++		fw_boot = kzalloc(FW_BOOT_LENGTH, GFP_KERNEL);
++		if (fw_boot == NULL) {
++			continue;
++		} else {
++			dev_dbg(&client->dev,
++				"[burn_fw_boot]Alloc %dk byte memory success.",
++				FW_BOOT_LENGTH / 1024);
++			break;
++		}
++	}
++	if (retry >= 5) {
++		dev_err(&client->dev, "[burn_fw_boot]Alloc memory fail,exit.");
++		return FAIL;
++	}
++
++	/* step2:load firmware bootloader */
++	dev_dbg(&client->dev, "[burn_fw_boot]step2:load firmware bootloader");
++	ret = gup_load_section_file(fw_boot,
++				    4 * FW_SECTION_LENGTH + FW_DSP_LENGTH,
++				    FW_BOOT_LENGTH, SEEK_SET);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_boot]load firmware bootcode fail.");
++		goto exit_burn_fw_boot;
++	}
++
++	/* step3:hold ss51 & dsp */
++	dev_dbg(&client->dev, "[burn_fw_boot]step3:hold ss51 & dsp");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_boot]hold ss51 & dsp fail.");
++		ret = FAIL;
++		goto exit_burn_fw_boot;
++	}
++
++	/* step4:set scramble */
++	dev_dbg(&client->dev, "[burn_fw_boot]step4:set scramble");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_boot]set scramble fail.");
++		ret = FAIL;
++		goto exit_burn_fw_boot;
++	}
++
++	/* step5:hold ss51 & release dsp */
++	dev_dbg(&client->dev, "[burn_fw_boot]step5:hold ss51 & release dsp");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04);
++	/* 20121211 */
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_boot]release ss51 & dsp fail");
++		ret = FAIL;
++		goto exit_burn_fw_boot;
++	}
++	/* must delay */
++	usleep_range(1000, 1100);
++
++	/* step6:select bank3 */
++	dev_dbg(&client->dev, "[burn_fw_boot]step6:select bank3");
++	ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x03);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_boot]select bank3 fail.");
++		ret = FAIL;
++		goto exit_burn_fw_boot;
++	}
++
++	/* step6:burn 2k bootloader firmware */
++	dev_dbg(&client->dev,
++		"[burn_fw_boot]step6:burn 2k bootloader firmware");
++	ret = gup_burn_proc(client, fw_boot, 0x9000, FW_BOOT_LENGTH);
++	if (FAIL == ret) {
++		dev_err(&client->dev, "[burn_fw_boot]burn fw_boot fail.");
++		goto exit_burn_fw_boot;
++	}
++
++	/* step7:send burn cmd to move data to flash from sram */
++	dev_dbg(&client->dev,
++	"[burn_fw_boot]step7:send burn cmd to move data to flash from sram");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x06);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_boot]send burn cmd fail.");
++		goto exit_burn_fw_boot;
++	}
++	dev_dbg(&client->dev,
++		"[burn_fw_boot]Wait for the burn is complete......");
++	do {
++		ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
++		if (ret <= 0) {
++			dev_err(&client->dev,
++				"[burn_fw_boot]Get burn state fail");
++			goto exit_burn_fw_boot;
++		}
++		usleep_range(10000, 11000);
++	/* dev_dbg(&client->dev, "[burn_fw_boot]Get burn state:%d.",
++	 * rd_buf[GTP_ADDR_LENGTH]);
++	 */
++	} while (rd_buf[GTP_ADDR_LENGTH]);
++
++	/* step8:recall check 2k bootloader firmware */
++	dev_dbg(&client->dev,
++		"[burn_fw_boot]step8:recall check 2k bootloader firmware");
++	ret = gup_recall_check(client, fw_boot, 0x9000, FW_BOOT_LENGTH);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_boot]recall check 2k bootcode firmware fail");
++		goto exit_burn_fw_boot;
++	}
++
++	update_msg.fw_burned_len += FW_BOOT_LENGTH;
++	dev_dbg(&client->dev, "[burn_fw_boot]Burned length:%d",
++		update_msg.fw_burned_len);
++	ret = SUCCESS;
++
++exit_burn_fw_boot:
++	kfree(fw_boot);
++
++	return ret;
++}
++static u8 gup_burn_fw_boot_isp(struct i2c_client *client)
++{
++	s32 ret = 0;
++	u8 *fw_boot_isp = NULL;
++	u8	retry = 0;
++	u8	rd_buf[5];
++
++	if (update_msg.fw_burned_len >= update_msg.fw_total_len) {
++		dev_dbg(&client->dev, "No need to upgrade the boot_isp code!");
++		return SUCCESS;
++	}
++	dev_info(&client->dev,
++		"[burn_fw_boot_isp]Begin burn boot_isp firmware---->>");
++
++	/* step1:Alloc memory */
++	dev_dbg(&client->dev, "[burn_fw_boot_isp]step1:Alloc memory");
++	while (retry++ < 5) {
++		fw_boot_isp = kzalloc(FW_BOOT_ISP_LENGTH, GFP_KERNEL);
++		if (fw_boot_isp == NULL) {
++			continue;
++		} else {
++			dev_dbg(&client->dev,
++				"[burn_fw_boot_isp]Alloc %dk byte memory success.",
++				(FW_BOOT_ISP_LENGTH/1024));
++			break;
++		}
++	}
++	if (retry >= 5) {
++		dev_err(&client->dev,
++			"[burn_fw_boot_isp]Alloc memory fail,exit.");
++		return FAIL;
++	}
++
++	/* step2:load firmware bootloader */
++	dev_dbg(&client->dev,
++		"[burn_fw_boot_isp]step2:load firmware bootloader isp");
++	/* ret = gup_load_section_file(fw_boot_isp,
++	 * (4*FW_SECTION_LENGTH+FW_DSP_LENGTH +
++	 * FW_BOOT_LENGTH+FW_DSP_ISP_LENGTH), FW_BOOT_ISP_LENGTH, SEEK_SET);
++	 */
++	ret = gup_load_section_file(fw_boot_isp, (update_msg.fw_burned_len - FW_DSP_ISP_LENGTH),
++				    FW_BOOT_ISP_LENGTH, SEEK_SET);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_boot_isp]load firmware boot_isp fail.");
++		goto exit_burn_fw_boot_isp;
++	}
++
++	/* step3:hold ss51 & dsp */
++	dev_dbg(&client->dev, "[burn_fw_boot_isp]step3:hold ss51 & dsp");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_boot_isp]hold ss51 & dsp fail");
++		ret = FAIL;
++		goto exit_burn_fw_boot_isp;
++	}
++
++	/* step4:set scramble */
++	dev_dbg(&client->dev, "[burn_fw_boot_isp]step4:set scramble");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_boot_isp]set scramble fail.");
++		ret = FAIL;
++		goto exit_burn_fw_boot_isp;
++	}
++
++
++	/* step5:hold ss51 & release dsp */
++	dev_dbg(&client->dev,
++		"[burn_fw_boot_isp]step5:hold ss51 & release dsp");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04);
++	/* 20121211 */
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_fw_boot_isp]release ss51 & dsp fail.");
++		ret = FAIL;
++		goto exit_burn_fw_boot_isp;
++	}
++	/* must delay */
++	usleep_range(1000, 2000);
++
++	/* step6:select bank3 */
++	dev_dbg(&client->dev, "[burn_fw_boot_isp]step6:select bank3");
++	ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x03);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_boot_isp]select bank3 fail.");
++		ret = FAIL;
++		goto exit_burn_fw_boot_isp;
++	}
++
++	/* step7:burn 2k bootload_isp firmware */
++	dev_dbg(&client->dev,
++		"[burn_fw_boot_isp]step7:burn 2k bootloader firmware");
++	ret = gup_burn_proc(client, fw_boot_isp, 0x9000, FW_BOOT_ISP_LENGTH);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_boot_isp]burn fw_section fail.");
++		goto exit_burn_fw_boot_isp;
++	}
++
++	/* step7:send burn cmd to move data to flash from sram */
++	dev_dbg(&client->dev,
++	"[burn_fw_boot_isp]step8:send burn cmd to move data to flash from sram");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x07);
++	if (ret <= 0) {
++		dev_err(&client->dev, "[burn_fw_boot_isp]send burn cmd fail.");
++		goto exit_burn_fw_boot_isp;
++	}
++	dev_dbg(&client->dev,
++		"[burn_fw_boot_isp]Wait for the burn is complete......");
++	do {
++		ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
++		if (ret <= 0) {
++			dev_err(&client->dev,
++				"[burn_fw_boot_isp]Get burn state fail");
++			goto exit_burn_fw_boot_isp;
++		}
++		usleep_range(10000, 11000);
++	/* dev_dbg(&client->dev, "[burn_fw_boot_isp]Get
++	 * burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
++	 */
++	} while (rd_buf[GTP_ADDR_LENGTH]);
++
++	/* step8:recall check 2k bootload_isp firmware */
++	dev_dbg(&client->dev,
++		"[burn_fw_boot_isp]step9:recall check 2k bootloader firmware");
++	ret = gup_recall_check(client, fw_boot_isp, 0x9000, FW_BOOT_ISP_LENGTH);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++		"[burn_fw_boot_isp]recall check 2k bootcode_isp firmware fail.");
++		goto exit_burn_fw_boot_isp;
++	}
++
++	update_msg.fw_burned_len += FW_BOOT_ISP_LENGTH;
++	dev_dbg(&client->dev,
++		"[burn_fw_boot_isp]Burned length:%d", update_msg.fw_burned_len);
++	ret = SUCCESS;
++
++exit_burn_fw_boot_isp:
++	kfree(fw_boot_isp);
++
++	return ret;
++}
++
++static u8 gup_burn_fw_link(struct i2c_client *client)
++{
++	u8 *fw_link = NULL;
++	u8	retry = 0;
++	s32 ret = 0;
++	u32 offset;
++
++	if (update_msg.fw_burned_len >= update_msg.fw_total_len) {
++		dev_dbg(&client->dev, "No need to upgrade the link code!");
++		return SUCCESS;
++	}
++	dev_info(&client->dev, "[burn_fw_link]Begin burn link firmware---->>");
++
++	/* step1:Alloc memory */
++	dev_dbg(&client->dev, "[burn_fw_link]step1:Alloc memory");
++	while (retry++ < 5) {
++		fw_link = kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
++		if (fw_link == NULL) {
++			continue;
++		} else {
++			dev_dbg(&client->dev,
++				"[burn_fw_link]Alloc %dk byte memory success.",
++				(FW_SECTION_LENGTH/1024));
++			break;
++		}
++	}
++	if (retry >= 5) {
++		dev_err(&client->dev, "[burn_fw_link]Alloc memory fail,exit.");
++		return FAIL;
++	}
++
++	/* step2:load firmware link section 1 */
++	dev_dbg(&client->dev,
++		"[burn_fw_link]step2:load firmware link section 1");
++	offset = update_msg.fw_burned_len - FW_DSP_ISP_LENGTH;
++	ret = gup_load_section_file(fw_link, offset, FW_SECTION_LENGTH, SEEK_SET);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_link]load firmware link section 1 fail.");
++		goto exit_burn_fw_link;
++	}
++
++	/* step3:burn link firmware section 1 */
++	dev_dbg(&client->dev,
++		"[burn_fw_link]step3:burn link firmware section 1");
++	ret = gup_burn_fw_gwake_section(
++	client, fw_link, 0x9000, FW_SECTION_LENGTH, 0x38);
++
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_link]burn link firmware section 1 fail.");
++		goto exit_burn_fw_link;
++	}
++
++	/* step4:load link firmware section 2 file data */
++	dev_dbg(&client->dev,
++		"[burn_fw_link]step4:load link firmware section 2 file data");
++	offset += FW_SECTION_LENGTH;
++	ret = gup_load_section_file(fw_link, offset,
++				    FW_GLINK_LENGTH - FW_SECTION_LENGTH, SEEK_SET);
++
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_link]load link firmware section 2 fail.");
++		goto exit_burn_fw_link;
++	}
++
++	/* step5:burn link firmware section 2 */
++	dev_dbg(&client->dev,
++		"[burn_fw_link]step4:burn link firmware section 2");
++	ret = gup_burn_fw_gwake_section(client,
++	fw_link, 0x9000, FW_GLINK_LENGTH - FW_SECTION_LENGTH, 0x39);
++
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_link]burn link firmware section 2 fail.");
++		goto exit_burn_fw_link;
++	}
++
++	update_msg.fw_burned_len += FW_GLINK_LENGTH;
++	dev_dbg(&client->dev,
++		"[burn_fw_link]Burned length:%d", update_msg.fw_burned_len);
++	ret = SUCCESS;
++
++exit_burn_fw_link:
++	kfree(fw_link);
++
++	return ret;
++}
++
++static u8 gup_burn_fw_gwake_section(struct i2c_client *client,
++		u8 *fw_section, u16 start_addr, u32 len, u8 bank_cmd)
++{
++	s32 ret = 0;
++	u8	rd_buf[5];
++
++	/* step1:hold ss51 & dsp */
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_fw_app_section]hold ss51 & dsp fail.");
++		return FAIL;
++	}
++
++	/* step2:set scramble */
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_fw_app_section]set scramble fail.");
++		return FAIL;
++	}
++
++	/* step3:hold ss51 & release dsp */
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04);
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_fw_app_section]hold ss51 & release dsp fail.");
++		return FAIL;
++	}
++	/* must delay */
++	usleep_range(1000, 2000);
++
++	/* step4:select bank */
++	ret = gup_set_ic_msg(
++	client, _bRW_MISCTL__SRAM_BANK, (bank_cmd >> 4)&0x0F);
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_fw_section]select bank %d fail.",
++			(bank_cmd >> 4)&0x0F);
++		return FAIL;
++	}
++
++	/* step5:burn fw section */
++	ret = gup_burn_proc(client, fw_section, start_addr, len);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_app_section]burn fw_section fail.");
++		return FAIL;
++	}
++
++	/* step6:send burn cmd to move data to flash from sram */
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, bank_cmd&0x0F);
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_fw_app_section]send burn cmd fail.");
++		return FAIL;
++	}
++	dev_dbg(&client->dev,
++		"[burn_fw_section]Wait for the burn is complete......");
++	do {
++		ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
++		if (ret <= 0) {
++			dev_err(&client->dev,
++				"[burn_fw_app_section]Get burn state fail");
++			return FAIL;
++		}
++		usleep_range(10000, 11000);
++	/* dev_dbg(&client->dev, "[burn_fw_app_section]Get burn state:%d."
++	 * rd_buf[GTP_ADDR_LENGTH]);
++	 */
++	} while (rd_buf[GTP_ADDR_LENGTH]);
++
++	/* step7:recall fw section */
++	ret = gup_recall_check(client, fw_section, start_addr, len);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_app_section]recall check %dk firmware fail.",
++			len/1024);
++		return FAIL;
++	}
++
++	return SUCCESS;
++}
++
++static u8 gup_burn_fw_gwake(struct i2c_client *client)
++{
++	u8 *fw_gwake = NULL;
++	u8	retry = 0;
++	s32 ret = 0;
++	u16 start_index = 4*FW_SECTION_LENGTH +
++	FW_DSP_LENGTH + FW_BOOT_LENGTH +
++	FW_BOOT_ISP_LENGTH + FW_GLINK_LENGTH;/* 32 + 4 + 2 + 4 = 42K */
++	/* u16 start_index; */
++
++	if (start_index >= update_msg.fw_total_len) {
++		dev_dbg(&client->dev, "No need to upgrade the gwake code!");
++		return SUCCESS;
++	}
++	/* start_index = update_msg.fw_burned_len - FW_DSP_ISP_LENGTH; */
++	dev_info(&client->dev,
++		 "[burn_fw_gwake]Begin burn gwake firmware---->>");
++
++	/* step1:alloc memory */
++	dev_dbg(&client->dev, "[burn_fw_gwake]step1:alloc memory");
++	while (retry++ < 5) {
++		fw_gwake =
++	kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
++		if (fw_gwake == NULL) {
++			continue;
++		} else {
++			dev_dbg(&client->dev,
++				"[burn_fw_gwake]Alloc %dk byte memory success.",
++				(FW_SECTION_LENGTH/1024));
++			break;
++		}
++	}
++	if (retry >= 5) {
++		dev_err(&client->dev, "[burn_fw_gwake]Alloc memory fail,exit.");
++		return FAIL;
++	}
++
++	/* clear control flag */
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x00);
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_fw_finish]clear control flag fail.");
++		goto exit_burn_fw_gwake;
++	}
++
++	/* step2:load app_code firmware section 1 file data */
++	dev_dbg(&client->dev,
++		"[burn_fw_gwake]step2:load app_code firmware section 1 file data");
++	ret = gup_load_section_file(fw_gwake, start_index,
++				    FW_SECTION_LENGTH, SEEK_SET);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_gwake]load app_code firmware section 1 fail.");
++		goto exit_burn_fw_gwake;
++	}
++
++	/* step3:burn app_code firmware section 1 */
++	dev_dbg(&client->dev,
++		"[burn_fw_gwake]step3:burn app_code firmware section 1");
++	ret = gup_burn_fw_gwake_section(client,
++	fw_gwake, 0x9000, FW_SECTION_LENGTH, 0x3A);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_gwake]burn app_code firmware section 1 fail.");
++		goto exit_burn_fw_gwake;
++	}
++
++	/* step5:load app_code firmware section 2 file data */
++	dev_dbg(&client->dev,
++		"[burn_fw_gwake]step5:load app_code firmware section 2 file data");
++	ret = gup_load_section_file(fw_gwake, start_index+FW_SECTION_LENGTH,
++				    FW_SECTION_LENGTH, SEEK_SET);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_gwake]load app_code firmware section 2 fail.");
++		goto exit_burn_fw_gwake;
++	}
++
++	/* step6:burn app_code firmware section 2 */
++	dev_dbg(&client->dev,
++		"[burn_fw_gwake]step6:burn app_code firmware section 2");
++	ret = gup_burn_fw_gwake_section(client,
++	fw_gwake, 0x9000, FW_SECTION_LENGTH, 0x3B);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_gwake]burn app_code firmware section 2 fail.");
++		goto exit_burn_fw_gwake;
++	}
++
++	/* step7:load app_code firmware section 3 file data */
++	dev_dbg(&client->dev,
++		"[burn_fw_gwake]step7:load app_code firmware section 3 file data");
++	ret = gup_load_section_file(fw_gwake,
++				    start_index + 2 * FW_SECTION_LENGTH,
++				    FW_SECTION_LENGTH, SEEK_SET);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_gwake]load app_code firmware section 3 fail.");
++		goto exit_burn_fw_gwake;
++	}
++
++	/* step8:burn app_code firmware section 3 */
++	dev_dbg(&client->dev,
++		"[burn_fw_gwake]step8:burn app_code firmware section 3");
++	ret = gup_burn_fw_gwake_section(
++	client, fw_gwake, 0x9000, FW_SECTION_LENGTH, 0x3C);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_gwake]burn app_code firmware section 3 fail.");
++		goto exit_burn_fw_gwake;
++	}
++
++	/* step9:load app_code firmware section 4 file data */
++	dev_dbg(&client->dev,
++		"[burn_fw_gwake]step9:load app_code firmware section 4 file data");
++	ret = gup_load_section_file(fw_gwake,
++				    start_index + 3 * FW_SECTION_LENGTH,
++				    FW_SECTION_LENGTH, SEEK_SET);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_gwake]load app_code firmware section 4 fail.");
++		goto exit_burn_fw_gwake;
++	}
++
++	/* step10:burn app_code firmware section 4 */
++	dev_dbg(&client->dev,
++		"[burn_fw_gwake]step10:burn app_code firmware section 4");
++	ret = gup_burn_fw_gwake_section(
++	client, fw_gwake, 0x9000, FW_SECTION_LENGTH, 0x3D);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_gwake]burn app_code firmware section 4 fail.");
++		goto exit_burn_fw_gwake;
++	}
++
++	/* update_msg.fw_burned_len += FW_GWAKE_LENGTH; */
++	dev_dbg(&client->dev,
++		"[burn_fw_gwake]Burned length:%d", update_msg.fw_burned_len);
++	ret = SUCCESS;
++
++exit_burn_fw_gwake:
++	kfree(fw_gwake);
++
++	return ret;
++}
++
++static u8 gup_burn_fw_finish(struct i2c_client *client)
++{
++	u8 *fw_ss51 = NULL;
++	u8	retry = 0;
++	s32 ret = 0;
++
++	dev_info(&client->dev,
++		 "[burn_fw_finish]burn first 8K of ss51 and finish update.");
++	/* step1:alloc memory */
++	dev_dbg(&client->dev, "[burn_fw_finish]step1:alloc memory");
++	while (retry++ < 5) {
++		fw_ss51 = kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
++		if (fw_ss51 == NULL) {
++			continue;
++		} else {
++			dev_dbg(&client->dev,
++				"[burn_fw_finish]Alloc %dk byte memory success.",
++				(FW_SECTION_LENGTH/1024));
++			break;
++		}
++	}
++	if (retry >= 5) {
++		dev_err(&client->dev,
++			"[burn_fw_finish]Alloc memory fail,exit.");
++		return FAIL;
++	}
++
++	dev_dbg(&client->dev, "[burn_fw_finish]step2: burn ss51 first 8K.");
++	ret = gup_load_section_file(fw_ss51, 0, FW_SECTION_LENGTH, SEEK_SET);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_finish]load ss51 firmware section 1 fail.");
++		goto exit_burn_fw_finish;
++	}
++
++	dev_dbg(&client->dev, "[burn_fw_finish]step3:clear control flag");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x00);
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_fw_finish]clear control flag fail.");
++		goto exit_burn_fw_finish;
++	}
++
++	dev_dbg(&client->dev,
++		"[burn_fw_finish]step4:burn ss51 firmware section 1");
++	ret = gup_burn_fw_section(client, fw_ss51, 0xC000, 0x01);
++	if (FAIL == ret) {
++		dev_err(&client->dev,
++			"[burn_fw_finish]burn ss51 firmware section 1 fail.");
++		goto exit_burn_fw_finish;
++	}
++
++	/* step11:enable download DSP code */
++	dev_dbg(&client->dev,
++		"[burn_fw_finish]step5:enable download DSP code ");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x99);
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_fw_finish]enable download DSP code fail.");
++		goto exit_burn_fw_finish;
++	}
++
++	/* step12:release ss51 & hold dsp */
++	dev_dbg(&client->dev, "[burn_fw_finish]step6:release ss51 & hold dsp");
++	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x08);
++	if (ret <= 0) {
++		dev_err(&client->dev,
++			"[burn_fw_finish]release ss51 & hold dsp fail.");
++		goto exit_burn_fw_finish;
++	}
++
++	if (fw_ss51 != NULL)
++		kfree(fw_ss51);
++	return SUCCESS;
++
++exit_burn_fw_finish:
++	if (fw_ss51 != NULL)
++		kfree(fw_ss51);
++
++	return FAIL;
++}
++
++/* return 0 can update, else no update condition */
++static int gup_update_condition_check(struct goodix_ts_data *ts)
++{
++	if (test_bit(SLEEP_MODE, &ts->flags)) {
++		dev_info(&ts->client->dev, "Update abort, tp in sleep mode\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++s32 gup_update_proc(void *dir)
++{
++	s32 ret = 0;
++	s32 update_ret = FAIL;
++	u8	retry = 0;
++	struct st_fw_head fw_head;
++	struct goodix_ts_data *ts = NULL;
++
++	ts = i2c_get_clientdata(i2c_connect_client);
++
++	dev_dbg(&ts->client->dev, "[update_proc]Begin update ......\n");
++
++	show_len = 1;
++	total_len = 100;
++
++	ret = gup_update_condition_check(ts);
++	if (ret) {
++		dev_warn(&ts->client->dev, "Update start failed\n");
++		return FAIL;
++	}
++
++	if (test_and_set_bit(FW_UPDATE_RUNNING, &ts->flags)) {
++		dev_warn(&ts->client->dev, "FW update may already running\n");
++		return FAIL;
++	}
++
++	ret = gup_get_update_file(i2c_connect_client, &fw_head, (u8 *)dir);
++	if (FAIL == ret) {
++		dev_err(&ts->client->dev,
++			"Failed get valied firmware data\n");
++		clear_bit(FW_UPDATE_RUNNING, &ts->flags);
++		return FAIL;
++	}
++
++	gtp_work_control_enable(ts, false);
++	gtp_esd_off(ts);
++
++	ret = gup_get_ic_fw_msg(i2c_connect_client);
++	if (FAIL == ret) {
++		dev_err(&ts->client->dev, "[update_proc]get ic message fail.");
++		goto file_fail;
++	}
++
++	if (ts->force_update || dir) {
++		dev_dbg(&ts->client->dev, "Enter force update.");
++	} else {
++		ret = gup_enter_update_judge(i2c_connect_client, &fw_head);
++		if (FAIL == ret) {
++			dev_err(&ts->client->dev,
++				"[update_proc]Doesn't meet update condition\n");
++			goto file_fail;
++		}
++	}
++
++	ret = gup_enter_update_mode(ts->client);
++	if (FAIL == ret) {
++		dev_err(&ts->client->dev,
++			"[update_proc]enter update mode fail.");
++		goto update_fail;
++	}
++
++	while (retry++ < 5) {
++		show_len = 10;
++		total_len = 100;
++		update_msg.fw_burned_len = 0;
++		ret = gup_burn_dsp_isp(i2c_connect_client);
++		if (FAIL == ret) {
++			dev_err(&ts->client->dev,
++				"[update_proc]burn dsp isp fail.");
++			continue;
++		}
++
++		show_len = 20;
++		ret = gup_burn_fw_gwake(i2c_connect_client);
++		if (FAIL == ret) {
++			dev_err(&ts->client->dev,
++				"[update_proc]burn app_code firmware fail.");
++			continue;
++		}
++
++		show_len = 30;
++		ret = gup_burn_fw_ss51(i2c_connect_client);
++		if (FAIL == ret) {
++			dev_err(&ts->client->dev,
++				"[update_proc]burn ss51 firmware fail.");
++			continue;
++		}
++
++		show_len = 40;
++		ret = gup_burn_fw_dsp(i2c_connect_client);
++		if (FAIL == ret) {
++			dev_err(&ts->client->dev,
++				"[update_proc]burn dsp firmware fail.");
++			continue;
++		}
++
++		show_len = 50;
++		ret = gup_burn_fw_boot(i2c_connect_client);
++		if (FAIL == ret) {
++			dev_err(&ts->client->dev,
++				"[update_proc]burn bootloader firmware fail.");
++			continue;
++		}
++		show_len = 60;
++
++		ret = gup_burn_fw_boot_isp(i2c_connect_client);
++		if (FAIL == ret) {
++			dev_err(&ts->client->dev,
++				"[update_proc]burn boot_isp firmware fail.");
++			continue;
++		}
++
++		show_len = 70;
++		ret = gup_burn_fw_link(i2c_connect_client);
++		if (FAIL == ret) {
++			dev_err(&ts->client->dev,
++				"[update_proc]burn link firmware fail.");
++			continue;
++		}
++
++		show_len = 80;
++		ret = gup_burn_fw_finish(i2c_connect_client);
++		if (FAIL == ret) {
++			dev_err(&ts->client->dev,
++				"[update_proc]burn finish fail.");
++			continue;
++		}
++		show_len = 90;
++		dev_info(&ts->client->dev, "[update_proc]UPDATE SUCCESS.");
++		retry = 0;
++		break;
++	}
++
++	if (retry >= 5) {
++		dev_err(&ts->client->dev,
++			"[update_proc]retry timeout,UPDATE FAIL.");
++		update_ret = FAIL;
++	} else {
++		update_ret = SUCCESS;
++	}
++
++update_fail:
++	dev_dbg(&ts->client->dev, "[update_proc]leave update mode.");
++	gup_leave_update_mode(i2c_connect_client);
++
++	msleep(GTP_100_DLY_MS);
++
++	if (SUCCESS == update_ret) {
++		dev_info(&ts->client->dev,
++			"firmware error auto update, resent config!\n");
++		gup_init_panel(ts);
++	}
++	gtp_get_fw_info(ts->client, &ts->fw_info);
++
++file_fail:
++
++	update_msg.fw_data = NULL;
++	update_msg.fw_total_len = 0;
++	release_firmware(update_msg.fw);
++
++	clear_bit(FW_UPDATE_RUNNING, &ts->flags);
++	gtp_work_control_enable(ts, true);
++	gtp_esd_on(ts);
++	total_len = 100;
++	ts->force_update = false;
++	if (SUCCESS == update_ret) {
++		show_len = 100;
++		clear_bit(FW_ERROR, &ts->flags);
++		return SUCCESS;
++	} else {
++		show_len = 200;
++		return FAIL;
++	}
++}
++
++u8 gup_init_update_proc(struct goodix_ts_data *ts)
++{
++	struct task_struct *thread = NULL;
++
++	dev_info(&ts->client->dev, "Ready to run update thread.");
++
++	thread = kthread_run(gup_update_proc,
++			(void *)NULL, "guitar_update");
++
++	if (IS_ERR(thread)) {
++		dev_err(&ts->client->dev,
++				"Failed to create update thread.\n");
++		return -EPERM;
++	}
++
++	return 0;
++}
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Debug_driver/ref_cst3xx_MCU_driver_0729_update1/hyn_cst3xx_0729_update1ok.c b/module_drivers/drivers/input/touchscreen/hyn_touch/Debug_driver/ref_cst3xx_MCU_driver_0729_update1/hyn_cst3xx_0729_update1ok.c
+new file mode 100644
+index 000000000..84b31238f
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Debug_driver/ref_cst3xx_MCU_driver_0729_update1/hyn_cst3xx_0729_update1ok.c
+@@ -0,0 +1,1602 @@
++/*
++ * cst3xx Touchscreen Controller Driver
++ */
++
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/i2c.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of_gpio.h>
++#include <linux/pm_qos.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include "hyn_cst3xx.h"
++#include "hyn_cst3xx_RS659_fw.h"
++#include <soc/gpio.h>
++
++#define HYN_DEBUG_EN  1
++
++struct st1615_ts_finger {
++	u16 x;
++	u16 y;
++	u8 t;
++	bool is_valid;
++};
++
++
++static int cst3xx_into_program_mode(struct i2c_client * client);
++static int cst3xx_erase_program_area(struct i2c_client * client);
++static void cst3xx_reset_ic(struct cst3xx_ts_data *ts,unsigned int ms);
++static int cst3xx_write_program_data(struct i2c_client * client,const unsigned char *pdata);
++
++static int cst3xx_check_checksum(struct i2c_client * client);
++
++static int cst3xx_exit_program_mode(struct i2c_client * client);
++
++static int cst3xx_update_firmware(struct cst3xx_ts_data *ts, const unsigned char *pdata);
++
++static int cst3xx_firmware_info(struct i2c_client * client);
++
++static int cst3xx_update_judge( unsigned char *pdata, int strict);
++
++static int cst3xx_boot_update_fw(struct cst3xx_ts_data *ts,  unsigned char *pdata);
++
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_test(struct i2c_client *client);
++static void cst3xx_reset(struct cst3xx_ts_data *ts) ;
++extern  void close_vcc3v3Power(void);
++extern  void open_vcc3v3Power(void);
++
++static unsigned char *pcst3xx_update_firmware = (unsigned char *)cst3_fw ; //the updating firmware
++static unsigned int   g_cst3xx_ic_version  = 0;
++static unsigned int   g_cst3xx_ic_checksum = 0;
++static unsigned int   g_cst3xx_ic_checkcode =0;
++static unsigned int   g_cst3xx_ic_project_id  = 0;
++static unsigned int   g_cst3xx_ic_type  = 0;
++
++static unsigned char  report_flag = 0;
++static unsigned int x_temp_pos = 0;
++static unsigned int y_temp_pos = 0;
++
++#define HYN_DRAW_POINT
++
++//#define USE_ANALOG_I2C     1 //i2c analog -->defconfig i2c.
++#define USE_HIGHEST_I2CA  1// x1000 highest i2c
++//#define USE_LOWEST_I2CA   1 // x1000 lowest i2c
++#define HYN_UPDATE_FIRMWARE_POWERON_ENABLE
++//#define HYN_UPDATE_FIRMWARE_ENABLE
++
++#pragma pack(1)
++typedef struct
++{
++    u16 pid;                 //product id   //
++    u16 vid;                 //version id   //
++} st_tpd_info;
++#pragma pack()
++
++st_tpd_info tpd_info;
++
++#define CST3XX_BIN_SIZE    (24*1024 + 24)
++//#define CST3XX_MAX_X  340
++#define CST3XX_MAX_X  480
++#define CST3XX_MAX_Y  800
++#define ERROR_TOUCH   1
++
++static void cst3xx_ts_power(struct cst3xx_ts_data *ts, bool poweron)
++{
++	if (gpio_is_valid(ts->pdata->reset_gpio))
++		gpio_direction_output(ts->pdata->reset_gpio, poweron);
++}
++
++static int cst3xx_into_program_mode(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[4];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x01;
++	buf[2] = 0xAA;	//set cmd to enter program mode
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0)  return -1;
++
++	mdelay(2);
++
++	buf[0] = 0xA0;
++	buf[1] = 0x02;	//check whether into program mode
++	ret = cst3xx_i2c_read_register(client, buf, 1);
++	if (ret < 0)  return -1;
++
++	if (buf[0] != 0x55) return -1;
++
++	return 0;
++}
++static int cst3xx_erase_program_area(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[3];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x02;
++	buf[2] = 0x00;		//set cmd to erase main area
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0) return -1;
++
++	mdelay(5);
++
++	buf[0] = 0xA0;
++	buf[1] = 0x03;
++	ret = cst3xx_i2c_read_register(client, buf, 1);
++	if (ret < 0)  return -1;
++
++	if (buf[0] != 0x55) return -1;
++
++	return 0;
++}
++
++
++static void cst3xx_reset_ic(struct cst3xx_ts_data *ts,unsigned int ms)
++{
++
++	unsigned char buf[4];
++	buf[0] = 0xD1;
++	buf[1] = 0x0E;
++	cst3xx_i2c_write(ts->client, buf, 2);
++/*
++	gpio_direction_output(ts->pdata->reset_gpio,0);
++	mdelay(2);
++	gpio_direction_output(ts->pdata->reset_gpio,1);
++*/
++	mdelay(ms);
++}
++
++
++static int cst3xx_write_program_data(struct i2c_client * client,
++		const unsigned char *pdata)
++{
++	int i, ret;
++	unsigned char *i2c_buf;
++	unsigned short eep_addr;
++	int total_kbyte;
++
++	unsigned char temp_buf[8];
++	unsigned short iic_addr;
++	int  j;
++
++
++	i2c_buf = kmalloc(sizeof(unsigned char)*(1024 + 2), GFP_KERNEL);
++	if (i2c_buf == NULL)
++		return -1;
++
++	//make sure fwbin len is N*1K
++	//total_kbyte = len / 1024;
++	total_kbyte = 24;
++	for (i=0; i<total_kbyte; i++) {
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x14;
++		eep_addr = i << 10;		//i * 1024
++		i2c_buf[2] = eep_addr;
++		i2c_buf[3] = eep_addr>>8;
++		ret = cst3xx_i2c_write(client, i2c_buf, 4);
++		if (ret < 0)
++			goto error_out;
++
++		memcpy(i2c_buf, pdata + eep_addr, 1024);
++		for(j=0; j<256; j++) {
++			iic_addr = (j<<2);
++    	temp_buf[0] = (iic_addr+0xA018)>>8;
++    	temp_buf[1] = (iic_addr+0xA018)&0xFF;
++		temp_buf[2] = i2c_buf[iic_addr+0];
++		temp_buf[3] = i2c_buf[iic_addr+1];
++		temp_buf[4] = i2c_buf[iic_addr+2];
++		temp_buf[5] = i2c_buf[iic_addr+3];
++    	      ret = cst3xx_i2c_write(client, temp_buf, 6);
++    		if (ret < 0)
++    			goto error_out;
++		}
++
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x04;
++		i2c_buf[2] = 0xEE;
++		ret = cst3xx_i2c_write(client, i2c_buf, 3);
++		if (ret < 0)
++			goto error_out;
++
++		mdelay(60);
++
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x05;
++		ret = cst3xx_i2c_read_register(client, i2c_buf, 1);
++		if (ret < 0)
++			goto error_out;
++
++		if (i2c_buf[0] != 0x55)
++			goto error_out;
++
++	}
++
++	i2c_buf[0] = 0xA0;
++	i2c_buf[1] = 0x03;
++	i2c_buf[2] = 0x00;
++	ret = cst3xx_i2c_write(client, i2c_buf, 3);
++	if (ret < 0)
++		goto error_out;
++
++	mdelay(8);
++
++	if (i2c_buf != NULL) {
++		kfree(i2c_buf);
++		i2c_buf = NULL;
++	}
++
++	return 0;
++
++error_out:
++	if (i2c_buf != NULL) {
++		kfree(i2c_buf);
++		i2c_buf = NULL;
++	}
++	return -1;
++}
++
++
++static int cst3xx_check_checksum(struct i2c_client * client)
++{
++	int ret;
++	int i;
++	unsigned int  checksum;
++	unsigned int  bin_checksum;
++	unsigned char buf[4];
++	const unsigned char *pData;
++
++	for(i=0; i<5; i++)
++	{
++		buf[0] = 0xA0;
++		buf[1] = 0x00;
++		ret = cst3xx_i2c_read_register(client, buf, 1);
++		if(ret < 0)
++		{
++			mdelay(2);
++			continue;
++		}
++
++		if(buf[0]!=0)
++			break;
++		else
++		mdelay(2);
++	}
++    mdelay(2);
++
++
++    if(buf[0]==0x01)
++	{
++		buf[0] = 0xA0;
++		buf[1] = 0x08;
++		ret = cst3xx_i2c_read_register(client, buf, 4);
++
++		if(ret < 0)	return -1;
++
++		// read chip checksum
++		checksum = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24);
++
++        pData=(unsigned char  *)pcst3xx_update_firmware +24*1024+16;   //7*1024 +512
++		bin_checksum = pData[0] + (pData[1]<<8) + (pData[2]<<16) + (pData[3]<<24);
++
++        printk("  hyn the updated ic checksum is :0x%x. the updating firmware checksum is:0x%x------\n", checksum, bin_checksum);
++
++        if(checksum!=bin_checksum)
++		{
++			printk(" cst3xx hyn check sum error.\n");
++			return -1;
++
++		}
++
++	}
++	else
++	{
++		printk(" cst3xx hyn No checksum.\n");
++		return -1;
++	}
++	return 0;
++}
++
++static int cst3xx_exit_program_mode(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[3];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x06;
++	buf[2] = 0xEE;
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0)
++		return -1;
++
++	mdelay(10);	//wait for restart
++
++
++	return 0;
++}
++
++
++static int cst3xx_update_firmware(struct cst3xx_ts_data *ts, const unsigned char *pdata)
++{
++	int ret;
++	int retry = 0;
++
++	printk(" cst3xx----------upgrade cst3xx begain------------\n");
++	disable_irq(ts->irq);
++	mdelay(20);
++START_FLOW:
++
++#ifdef HYN_UPDATE_FIRMWARE_POWERON_ENABLE
++	close_vcc3v3Power();
++	mdelay(20);
++	open_vcc3v3Power();
++	mdelay(5+retry);
++#else
++	cst3xx_reset_ic(ts,5+retry);
++#endif
++	ret = cst3xx_into_program_mode(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]into program mode failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_erase_program_area(ts->client);
++	if (ret) {
++		printk(" cst3xx[cst3xx]erase main area failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_write_program_data(ts->client, pdata);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]write program data into cstxxx failed.\n");
++		goto err_out;
++	}
++
++    ret =cst3xx_check_checksum(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx] after write program cst3xx_check_checksum failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_exit_program_mode(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]exit program mode failed.\n");
++		goto err_out;
++	}
++
++	cst3xx_reset_ic(ts,20);
++
++	printk(" cst3xx hyn----------cst3xx_update_firmware  end------------\n");
++
++	enable_irq(ts->irq);
++
++	return 0;
++
++err_out:
++	if (retry < 30) {
++		retry++;
++		mdelay(20);
++		goto START_FLOW;
++	}
++	else {
++		enable_irq(ts->irq);
++		return -1;
++	}
++}
++
++
++
++
++/*******************************************************
++Function:
++    get firmware version, ic type...
++Input:
++    client: i2c client
++Output:
++    success: 0
++    fail:	-1
++*******************************************************/
++static int cst3xx_firmware_info(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[28];
++//	unsigned short ic_type, project_id;
++
++
++	buf[0] = 0xD1;
++	buf[1] = 0x01;
++	ret = cst3xx_i2c_write(client, buf, 2);
++	if (ret < 0) return -1;
++
++	mdelay(40);
++
++	buf[0] = 0xD1;
++	buf[1] = 0xFC;
++	ret = cst3xx_i2c_read_register(client, buf, 4);
++	if (ret < 0) return -1;
++
++	//0xCACA0000
++	g_cst3xx_ic_checkcode = buf[3];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[2];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[1];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[0];
++
++	printk("linc cst3xx [cst3xx] the chip g_cst3xx_ic_checkcode:0x%x.\r\n",g_cst3xx_ic_checkcode);
++
++	mdelay(2);
++
++	buf[0] = 0xD2;
++	buf[1] = 0x04;
++	ret = cst3xx_i2c_read_register(client, buf, 4);
++	if (ret < 0) return -1;
++	g_cst3xx_ic_type = buf[3];
++	g_cst3xx_ic_type <<= 8;
++	g_cst3xx_ic_type |= buf[2];
++
++
++	g_cst3xx_ic_project_id = buf[1];
++	g_cst3xx_ic_project_id <<= 8;
++	g_cst3xx_ic_project_id |= buf[0];
++
++	printk("linc cst3xx [cst3xx] the chip ic g_cst3xx_ic_type :0x%x, g_cst3xx_ic_project_id:0x%x\r\n",
++		g_cst3xx_ic_type, g_cst3xx_ic_project_id);
++
++	mdelay(2);
++
++	buf[0] = 0xD2;
++	buf[1] = 0x08;
++	ret = cst3xx_i2c_read_register(client, buf, 8);
++	if (ret < 0) return -1;
++
++	g_cst3xx_ic_version = buf[3];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[2];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[1];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[0];
++
++	g_cst3xx_ic_checksum = buf[7];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[6];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[5];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[4];
++
++	tpd_info.vid = g_cst3xx_ic_version;
++    tpd_info.pid = 0x00;
++
++
++	printk(" cst3xx [cst3xx] the chip ic version:0x%x, checksum:0x%x\r\n",
++		g_cst3xx_ic_version, g_cst3xx_ic_checksum);
++
++	if(g_cst3xx_ic_version==0xA5A5A5A5)
++	{
++		printk(" cst3xx [cst3xx] the chip ic don't have firmware. \n");
++		return -1;
++	}
++	if((g_cst3xx_ic_checkcode&0xffff0000)!=0xCACA0000){
++		printk("linc cst3xx [cst3xx] cst3xx_firmware_info read error .\r\n");
++		return -1;
++	}
++
++    buf[0] = 0xD1;
++	buf[1] = 0x09;
++	ret = cst3xx_i2c_write(client, buf, 2);
++	if (ret < 0) return -1;
++    mdelay(5);
++
++
++	return 0;
++}
++
++static int cst3xx_update_judge( unsigned char *pdata, int strict)
++{
++	unsigned short ic_type, project_id;
++	unsigned int fw_checksum, fw_version;
++	const unsigned int *p;
++	int i;
++	unsigned char *pBuf;
++
++	fw_checksum = 0x55;
++	p = (const unsigned int *)pdata;
++	for (i=0; i<(CST3XX_BIN_SIZE-4); i+=4) {
++		fw_checksum += (*p);
++		p++;
++	}
++
++	if (fw_checksum != (*p)) {
++		printk(" cst3xx[cst3xx]calculated checksum error:0x%x not equal 0x%x.\n", fw_checksum, *p);
++		return -1;	//bad fw, so do not update
++	}
++
++	pBuf = &pdata[CST3XX_BIN_SIZE-16];
++
++	project_id = pBuf[1];
++	project_id <<= 8;
++	project_id |= pBuf[0];
++
++	ic_type = pBuf[3];
++	ic_type <<= 8;
++	ic_type |= pBuf[2];
++
++	fw_version = pBuf[7];
++	fw_version <<= 8;
++	fw_version |= pBuf[6];
++	fw_version <<= 8;
++	fw_version |= pBuf[5];
++	fw_version <<= 8;
++	fw_version |= pBuf[4];
++
++	fw_checksum = pBuf[11];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[10];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[9];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[8];
++
++	printk(" cst3xx[cst3xx]the updating firmware:project_id:0x%04x,ic type:0x%04x,version:0x%x,checksum:0x%x\n",
++			project_id, ic_type, fw_version, fw_checksum);
++
++	if (strict > 0) {
++
++		if (g_cst3xx_ic_checksum != fw_checksum){
++			if (g_cst3xx_ic_version >fw_version){
++				printk("[cst3xx]fw version(0x%x), ic version(0x%x).\n",fw_version, g_cst3xx_ic_version);
++				return -1;
++			}
++		}else{
++			printk("[cst3xx]fw checksum(0x%x), ic checksum(0x%x).\n",fw_checksum, g_cst3xx_ic_checksum);
++			return -1;
++		}
++	}
++
++	return 0;
++}
++static int cst3xx_boot_update_fw(struct cst3xx_ts_data *ts,  unsigned char *pdata)
++{
++	int ret;
++	int retry = 0;
++	int flag = 0;
++
++	while (retry++ < 3) {
++		ret = cst3xx_firmware_info(ts->client);
++		if (ret == 0) {
++			flag = 1;
++			break;
++		}
++	}
++
++	if (flag == 1) {
++		ret = cst3xx_update_judge(pdata, 1);
++		if (ret < 0) {
++			printk(" cst3xx[cst3xx] no need to update firmware.\n");
++			return 0;
++		}
++	}
++
++	ret = cst3xx_update_firmware(ts, pdata);
++	if (ret < 0){
++		printk(" cst3xx [cst3xx] update firmware failed.\n");
++		return -1;
++	}
++
++    mdelay(50);
++
++	ret = cst3xx_firmware_info(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx [cst3xx] after update read version and checksum fail.\n");
++		return -1;
++	}
++
++	return 0;
++}
++
++
++/*******************************Chose which I2C interface ********************************************/
++
++#if USE_ANALOG_I2C
++
++#define I2CSDA  GPIO_PB(23)
++#define I2CSCL   GPIO_PB(22)
++
++#define I2CSDA_HIGH gpio_direction_output(I2CSDA,1)
++#define I2CSDA_LOW  gpio_direction_output(I2CSDA,0)
++
++#define I2CSCL_HIGH  gpio_direction_output(I2CSCL,1)
++#define I2CSCL_LOW  gpio_direction_output(I2CSCL,0)
++
++#define delay_data 2
++static void iicstart(void)
++{
++     I2CSDA_HIGH;
++      I2CSCL_HIGH;
++      __udelay(2);
++      I2CSDA_LOW;
++      __udelay(2);
++       I2CSCL_LOW;
++       __udelay(2);
++}
++static void iicstop(void)
++{
++     I2CSDA_LOW;
++     I2CSCL_HIGH;
++     __udelay(2);
++     I2CSDA_HIGH;
++     __udelay(2);
++
++}
++static unsigned char waitack(void)
++{
++   u8 ucErrTime=0;
++
++//    gpio_direction_input(GPIO_PC(27));
++    gpio_direction_input(GPIO_PB(23));
++   //  __udelay(2);
++
++  //  I2CSDA_HIGH;
++  //  __udelay(2);
++     I2CSCL_HIGH;
++     __udelay(2);
++
++//    while(__gpio_get_value(GPIO_PC(27)))
++    while(__gpio_get_value(GPIO_PB(23)))
++    {
++        ucErrTime++;
++     //   printk("time out ++ \n");
++        if(ucErrTime>250)
++         {
++                iicstop();
++                return 1;
++        }
++    }
++    I2CSCL_LOW;
++     __udelay(2);
++    return 0;
++}
++static void sendack(void)
++{
++     I2CSCL_LOW;
++     __udelay(delay_data);
++     I2CSDA_LOW;
++     __udelay(delay_data);
++
++     I2CSCL_HIGH;
++     __udelay(delay_data);
++     I2CSCL_LOW;
++     __udelay(delay_data);
++
++}
++static void sendnotack(void)
++{
++     I2CSCL_LOW;
++     __udelay(delay_data);
++    I2CSDA_HIGH;
++    __udelay(delay_data);
++
++    I2CSCL_HIGH;
++    __udelay(delay_data);
++    I2CSCL_LOW;
++    __udelay(delay_data);
++}
++static void iicsendbyte(unsigned char ch)
++{
++     unsigned char i;
++     I2CSCL_LOW;
++     for(i = 0;i<8;i++)
++     {
++          if(ch&0x80)
++          {
++              I2CSDA_HIGH;
++          }
++          else
++          {
++              I2CSDA_LOW;
++          }
++           __udelay(delay_data);
++          ch<<=1;
++          I2CSCL_HIGH;
++          __udelay(delay_data);
++               I2CSCL_LOW;
++          __udelay(delay_data);
++     }
++}
++static unsigned char iicreceivebyte(unsigned char ack)
++{
++    unsigned char i=8;
++    unsigned char ddata=0;
++
++    gpio_direction_input(GPIO_PC(27));
++    __udelay(delay_data);
++
++     for(i = 0;i<8;i++)
++     {
++         I2CSCL_LOW;
++         __udelay(delay_data);
++         I2CSCL_HIGH;
++         __udelay(delay_data);
++
++         ddata<<=1;
++         if(gpio_get_value(GPIO_PC(27))) ddata++;
++    }
++
++    if(!ack)
++        sendnotack();
++     else
++        sendack();
++
++    return ddata;
++}
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++    int count = len;
++     iicstart();
++     __udelay(delay_data);
++
++/*
++	 iicsendbyte( (0x1a<<1) | 0);
++     __udelay(delay_data);
++
++     if(waitack())
++     {
++        iicstop();
++                printk(" cst3xx_i2c_read wait ack timeoue \n");
++        return 1;
++     }
++
++     iicsendbyte(buf[0]);
++     __udelay(delay_data);
++     waitack();
++     __udelay(delay_data);
++*/
++     iicstart();
++     __udelay(delay_data);
++
++     iicsendbyte((0x1a << 1 ) | 1);
++     __udelay(delay_data);
++     if(waitack())
++     {
++        iicstop();
++                printk(" cst3xx_i2c_read wait ack timeoue \n");
++        return 1;
++     }
++     __udelay(delay_data);
++
++    while(count)
++    {
++         if(count == 1) *buf = iicreceivebyte(0);
++         else *buf = iicreceivebyte(1);
++         count --;
++         buf++;
++    }
++     iicstop();
++     __udelay(delay_data);
++     return 0;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++     int count = len;
++      iicstart();
++   //   __udelay(delay_data);
++
++      iicsendbyte((0x1A << 1) | 0);
++//      __udelay(delay_data);
++
++     if(waitack())
++     {
++        iicstop();
++        printk(" cst3xx_i2c_write send address wait ack timeoue \n");
++        return 1;
++     }
++
++      while(count--)
++      {
++            iicsendbyte(*(buf++));
++            __udelay(delay_data);
++             if(waitack())
++             {
++                iicstop();
++               printk(" cst3xx_i2c_write wait ack timeoue \n");
++                return 1;
++             }
++            __udelay(delay_data);
++      }
++
++      iicstop();
++      __udelay(delay_data);
++
++	return 0;
++}
++
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	int ret = -1;
++
++    ret = cst3xx_i2c_write(client, buf, 2);
++    if(ret) printk("failed to write cst3xx\n");
++
++    ret = cst3xx_i2c_read(client, buf, len);
++    if(ret) printk("failed to write cst3xx\n");
++    return ret;
++}
++
++#elif  USE_LOWEST_I2CA
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	int ret = -1;
++	int retries = 0;
++
++	while (retries < 2) {
++		ret = i2c_master_recv(client, buf, len);
++		if(ret<=0)
++		    retries++;
++        else
++            break;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	int ret = -1;
++	int retries = 0;
++
++	while (retries < 2) {
++		ret = i2c_master_send(client, buf, len);
++		if(ret<=0)
++		    retries++;
++        else
++            break;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	int ret = -1;
++
++    ret = cst3xx_i2c_write(client, buf, 2);
++
++    ret = cst3xx_i2c_read(client, buf, len);
++
++    return ret;
++}
++
++#elif USE_HIGHEST_I2CA
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++	struct i2c_msg msg;
++	int ret = -1;
++	int retries = 0;
++
++	msg.flags |= I2C_M_RD;
++	msg.addr   = client->addr;
++	msg.len    = len;
++	msg.buf    = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == 1)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++/*******************************************************
++Function:
++    read data from register.
++Input:
++    buf: first two byte is register addr, then read data store into buf
++    len: length of data that to read
++Output:
++    success: number of messages
++    fail:	negative errno
++*******************************************************/
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++//	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	struct i2c_msg msgs[2];
++	int ret = -1;
++	int retries = 0;
++
++	msgs[0].flags = 0;
++	msgs[0].addr  = client->addr;
++	msgs[0].len   = 2;
++	msgs[0].buf   = buf;
++
++	msgs[1].flags |= I2C_M_RD;
++	msgs[1].addr   = client->addr;
++	msgs[1].len    = len;
++	msgs[1].buf    = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, msgs, 2);
++		if(ret == 2)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++//	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	struct i2c_msg msg;
++	int ret = -1;
++	int retries = 0;
++
++	msg.flags = 0;
++	msg.addr  = client->addr;
++	msg.len   = len;
++	msg.buf   = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == 1)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++#else
++#endif
++/*********************************i2c end********************************/
++
++
++static int cst3xx_i2c_test(struct i2c_client *client)
++{
++	int retry = 0;
++	int ret;
++	unsigned char buf[4];
++
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	while (retry++ < 5) {
++		ret = cst3xx_i2c_write(client, buf, 2);
++		if (ret == 0)
++			return ret;
++
++		mdelay(2);
++	}
++
++    if(retry==5) printk(" cst3xx hyn I2C TEST error.ret:%d;\n", ret);
++
++	return ret;
++}
++
++
++static void cst3xx_reset(struct cst3xx_ts_data *ts) {
++	if(gpio_is_valid(ts->pdata->reset_gpio)) {
++		gpio_direction_output(ts->pdata->reset_gpio,0);
++		mdelay(100);
++		gpio_direction_output(ts->pdata->reset_gpio,1);
++		mdelay(100);
++	}
++}
++/****************************  basic communication end*******************************/
++
++
++static void cst3xx_touch_report(struct cst3xx_ts_data *ts)
++{
++	unsigned char buf[30];
++	unsigned char i2c_buf[8];
++	unsigned char key_status, key_id = 0, finger_id, sw;
++	unsigned int  input_x = 0;
++	unsigned int  input_y = 0;
++	unsigned int  input_w = 0;
++	unsigned int input_x_delta = 0;
++	unsigned int input_y_delta = 0;
++       unsigned char cnt_up, cnt_down;
++	int   i, ret, idx;
++	int cnt, i2c_len;
++
++	int  len_1, len_2;
++
++      key_status = 0;
++
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	ret = cst3xx_i2c_read_register(ts->client, buf, 7);
++	if(ret < 0) {
++		printk("  iic read touch point data failed.\n");
++		goto OUT_PROCESS;
++	}
++  //   printk(" read buf : buf[0]: %x ,buf[1]: %x ,buf[2]: %x, buf[3]: %x,buf[4]: %x ,buf[5]: %x ,buf[6]: %x, buf[7]: %x,\n",buf[0],buf[1],buf[2],buf[3],buf[4],buf[5],buf[6],buf[7]);
++
++	if(buf[6] != 0xAB) {
++		printk(KERN_INFO " data is not valid..\r\n");
++		goto OUT_PROCESS;
++	}
++
++    	cnt = buf[5] & 0x7F;
++	if(cnt > 1) goto OUT_PROCESS;
++	else if(cnt==0)     goto CLR_POINT;
++
++	if(cnt == 0x01) {
++		goto FINGER_PROCESS;
++	}
++
++FINGER_PROCESS:
++
++    /*
++     *  sw: buf[0] low 4 bit
++     *  x pos:  buf[1] low 4 bit | buf[3] high 4 bit
++     *  y pos:  buf[2] low 4 bit | buf[3] low  4 bit
++     *  z press : buf[4]
++     *  finger_id:buf[0] high 4 bit
++     */
++	i2c_buf[0] = 0xD0;
++	i2c_buf[1] = 0x00;
++	i2c_buf[2] = 0xAB;
++
++	ret = cst3xx_i2c_write(ts->client, i2c_buf, 3);
++	if(ret < 0) {
++		printk(" cst3xx hyn send read touch info ending failed.\r\n");
++		cst3xx_reset_ic(ts,20);
++              goto END;
++	}
++
++	idx = 0;
++       cnt_up = 0;
++       cnt_down = 0;
++	input_x = (unsigned int)((buf[idx + 1] << 4) | ((buf[idx + 3] >> 4) & 0x0F));
++	input_y = (unsigned int)((buf[idx + 2] << 4) | (buf[idx + 3] & 0x0F));
++	input_w = (unsigned int)(buf[idx + 4]);
++	sw = (buf[idx] & 0x0F) >> 1;
++	finger_id = (buf[idx] >> 4) & 0x0F;
++
++    printk(" no handle : cst3xxPoint x:%d, y:%d, w:%d, id:%d, sw:%d. \n", input_x, input_y, input_w,finger_id, sw);
++
++//	input_x=input_x*CST3XX_MAX_X/268;  //update 0729 no handle == handle
++//	input_x=input_x*CST3XX_MAX_X/360;  //update 0729 no handle == handle
++//	input_y=input_y*CST3XX_MAX_Y/800;
++
++//	if(input_x >= CST3XX_MAX_X) input_x = CST3XX_MAX_X;
++//	if(input_y >= CST3XX_MAX_Y) input_y = CST3XX_MAX_Y;
++
++//	input_x = CST3XX_MAX_X-input_x;
++//	input_y = CST3XX_MAX_Y-input_y;
++
++#ifdef HYN_DRAW_POINT
++	if(input_x > 300){
++		input_x_delta = input_x - (CST3XX_MAX_X/2);
++		input_x = input_x + input_x_delta/((CST3XX_MAX_X/2)/20);
++		if(input_x > CST3XX_MAX_X) input_x = CST3XX_MAX_X;
++		}
++	if(input_x < 40){
++		input_x_delta = (CST3XX_MAX_X/2) - input_x;
++		input_x = input_x - input_x_delta/((CST3XX_MAX_X/2)/12);
++		if(input_x < 0) input_x = 0;
++		}
++	if(input_y > 760){
++		input_y_delta = input_y - (CST3XX_MAX_Y/2);
++		input_y = input_y + input_y_delta/((CST3XX_MAX_Y/2)/12);
++		if(input_y > CST3XX_MAX_Y) input_y = CST3XX_MAX_Y;
++		}
++	if(input_y < 40){
++		input_y_delta = (CST3XX_MAX_Y/2) - input_y;
++		input_y = input_y - input_y_delta/((CST3XX_MAX_Y/2)/25);
++		if(input_y < 0) input_y = 0;
++		}
++#endif
++
++    printk(" handle : cst3xxPoint x:%d, y:%d, w:%d, id:%d, sw:%d. \n\n", input_x, input_y, input_w,finger_id, sw);
++
++	if (sw == 0x03 ) {
++         	   if((input_x > x_temp_pos + ERROR_TOUCH) || (input_x < x_temp_pos -ERROR_TOUCH)  || (input_y > y_temp_pos + ERROR_TOUCH) || (input_y < y_temp_pos -ERROR_TOUCH))
++               {
++          //           printk(" REPORT TOUCH DOWM Handle \n");
++                     x_temp_pos = input_x;
++                     y_temp_pos = input_y;
++                     input_report_key(ts->input_dev, BTN_TOUCH, 1);
++    		        input_report_abs(ts->input_dev, ABS_X, input_x);
++    	               input_report_abs(ts->input_dev, ABS_Y, input_y);
++    		        input_report_abs(ts->input_dev, ABS_PRESSURE, 1);
++    		        input_sync(ts->input_dev);
++                 }
++                cnt_down++;
++       }
++      else if(sw == 0) {
++                cnt_up++;
++        }
++
++        if((cnt_up>0) && (cnt_down==0) ){
++      //      printk(" REPORT TOUCH UP Handle \n");
++            x_temp_pos = 0;
++            y_temp_pos = 0;
++            input_report_key(ts->input_dev, BTN_TOUCH, 0);
++            input_report_abs(ts->input_dev, ABS_PRESSURE, 0);
++            input_mt_sync(ts->input_dev);
++        }
++       input_sync(ts->input_dev);
++	goto END;
++CLR_POINT:
++
++	    input_report_key(ts->input_dev, BTN_TOUCH, 0);
++           input_mt_sync(ts->input_dev);
++           input_sync(ts->input_dev);
++
++OUT_PROCESS:
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	buf[2] = 0xAB;
++	ret = cst3xx_i2c_write(ts->client, buf, 3);
++	if (ret < 0) {
++		printk("  send read touch info ending failed.\n");
++		cst3xx_reset_ic(ts,20);
++	}
++END:
++	return;
++}
++
++
++/******************************* irq handle  begin************************************/
++static void cst3xx_work_handler(struct work_struct *work)
++{
++	struct cst3xx_ts_data *cst3xx_ts = container_of(work, struct cst3xx_ts_data, work);
++	int ret = 0;
++    /******************here handle touch *******************/
++    //    printk(KERN_INFO "-----------enter cst3xx_work_handler------------\n");
++         cst3xx_touch_report(cst3xx_ts);
++	  enable_irq(cst3xx_ts->irq);
++}
++
++static irqreturn_t cst3xx_ts_irq_handler(int irq, void *dev_id)
++{
++	struct cst3xx_ts_data *ts = dev_id;
++
++   //    printk( KERN_INFO "-----------enter cst3xx_ts_irq_handler------------\n");
++
++	disable_irq_nosync(ts->irq);//use in interrupt,disable_irq will make dead lock.
++
++	if (!work_pending(&ts->work)) {
++		queue_work(ts->workqueue, &ts->work);
++	//    queue_delayed_work(ts->workqueue,&ts->dwork,1);//10ms * x
++	} else {
++		enable_irq(ts->irq);
++	}
++
++	return IRQ_HANDLED;
++}
++/******************************* irq handle  end************************************/
++static int cst3xx_parse_dt(struct device *dev, struct cst3xx_platform_data *pdata)
++{
++    int ret = 0;
++    struct device_node *np = dev->of_node;
++    u32 temp_val = 0;
++
++    HYN_FUNC_ENTER();
++
++    /* reset, irq gpio info */
++    pdata->reset_gpio = of_get_named_gpio_flags(np, "hyn,reset-gpio",
++                        0, &pdata->reset_gpio_flags);
++    if (pdata->reset_gpio < 0)
++        HYN_ERROR("Unable to get reset_gpio");
++
++    pdata->int_gpio = of_get_named_gpio_flags(np, "hyn,irq-gpio",
++                      0, &pdata->irqflags);
++    if (pdata->int_gpio < 0)
++        HYN_ERROR("Unable to get irq_gpio");
++
++    HYN_INFO(" irq gpio:%d, reset gpio:%d",
++              pdata->int_gpio, pdata->reset_gpio);
++
++    HYN_FUNC_EXIT();
++    return 0;
++}
++static int cst3xx_gpio_configure(struct cst3xx_ts_data *data)
++{
++    int ret = 0;
++
++    HYN_FUNC_ENTER();
++    /* request irq gpio */
++    if (gpio_is_valid(data->pdata->int_gpio)) {
++        ret = gpio_request(data->pdata->int_gpio, "cst3xx_irq_gpio");
++        if (ret) {
++            HYN_ERROR("[GPIO]irq gpio request failed");
++            goto err_irq_gpio_req;
++        }
++
++        ret = gpio_direction_input(data->pdata->int_gpio);
++        if (ret) {
++            HYN_ERROR("[GPIO]set_direction for irq gpio failed");
++            goto err_irq_gpio_dir;
++        }
++    }
++
++    /* request reset gpio */
++    if (gpio_is_valid(data->pdata->reset_gpio)) {
++        ret = gpio_request(data->pdata->reset_gpio, "cst3xx_reset_gpio");
++        if (ret) {
++            HYN_ERROR("[GPIO]reset gpio request failed");
++            goto err_irq_gpio_dir;
++        }
++
++//        ret = gpio_direction_output(data->pdata->reset_gpio, 1);
++//        if (ret) {
++//            HYN_ERROR("[GPIO]set_direction for reset gpio failed");
++//            goto err_reset_gpio_dir;
++//        }
++    }
++
++    HYN_FUNC_EXIT();
++    return 0;
++
++err_reset_gpio_dir:
++    if (gpio_is_valid(data->pdata->reset_gpio))
++        gpio_free(data->pdata->reset_gpio);
++err_irq_gpio_dir:
++    if (gpio_is_valid(data->pdata->int_gpio))
++        gpio_free(data->pdata->int_gpio);
++err_irq_gpio_req:
++    HYN_FUNC_EXIT();
++    return ret;
++}
++
++static int cst3xx_input_init(struct cst3xx_ts_data *ts_data)
++{
++    int ret = 0;
++    int key_num = 0;
++    struct cst3xx_platform_data *pdata = ts_data->pdata;
++    struct input_dev *input_dev;
++
++    HYN_FUNC_ENTER();
++    input_dev = input_allocate_device();
++    if (!input_dev) {
++        HYN_ERROR("Failed to allocate memory for input device");
++        return -ENOMEM;
++    }
++
++    /* Init and register Input device */
++    input_dev->name = CST3XX_NAME;
++
++    input_dev->id.bustype = BUS_I2C;
++    input_dev->dev.parent = ts_data->dev;
++
++    input_set_drvdata(input_dev, ts_data);
++
++    __set_bit(EV_SYN, input_dev->evbit);
++    __set_bit(EV_ABS, input_dev->evbit);
++    __set_bit(EV_KEY, input_dev->evbit);
++    __set_bit(BTN_TOUCH, input_dev->keybit);
++//    __set_bit(INPUT_PROP_DIRECT, input_dev->propbit);
++    set_bit(ABS_X, input_dev->absbit); //add from hyn
++	set_bit(ABS_Y, input_dev->absbit);
++    set_bit(ABS_PRESSURE, input_dev->absbit);
++
++/*---add from hyn*/
++	input_set_abs_params(input_dev, ABS_X, ts_data->pdata->x_min, ts_data->pdata->x_max, 0, 0);
++	input_set_abs_params(input_dev, ABS_Y, ts_data->pdata->y_min, ts_data->pdata->y_max, 0, 0);
++    input_set_abs_params(input_dev, ABS_PRESSURE, 0, 1, 0 , 0);
++/*add from hyn---*/
++
++    ret = input_register_device(input_dev);
++    if (ret) {
++        HYN_ERROR("Input device registration failed");
++        input_set_drvdata(input_dev, NULL);
++        input_free_device(input_dev);
++        input_dev = NULL;
++        return ret;
++    }
++
++    ts_data->input_dev = input_dev;
++
++    HYN_FUNC_EXIT();
++    return 0;
++}
++
++static int cst3xx_irq_registration(struct cst3xx_ts_data *ts_data)
++{
++    int ret = 0;
++    struct cst3xx_platform_data *pdata = ts_data->pdata;
++
++    ts_data->irq = gpio_to_irq(pdata->int_gpio);
++    pdata->irqflags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
++    HYN_INFO("irq:%d, flag:%x", ts_data->irq, pdata->irqflags);
++    ret = request_threaded_irq(ts_data->irq, NULL, cst3xx_ts_irq_handler,
++                               pdata->irqflags,
++                               CST3XX_NAME, ts_data);
++
++    return ret;
++}
++
++static int cst3xx_ts_probe_entry(struct cst3xx_ts_data *ts_data)
++{
++    int ret = 0;
++    int pdata_size = sizeof(struct cst3xx_platform_data);
++
++    HYN_FUNC_ENTER();
++    ts_data->pdata = kzalloc(pdata_size, GFP_KERNEL);
++    if (!ts_data->pdata) {
++        HYN_ERROR("allocate memory for platform_data fail");
++        return -ENOMEM;
++    }
++
++    if (ts_data->dev->of_node) {
++        ret = cst3xx_parse_dt(ts_data->dev, ts_data->pdata);
++        if (ret)
++            HYN_ERROR("device-tree parse fail");
++    } else {
++        if (ts_data->dev->platform_data) {
++            memcpy(ts_data->pdata, ts_data->dev->platform_data, pdata_size);
++        } else {
++            HYN_ERROR("platform_data is null");
++            return -ENODEV;
++        }
++    }
++    //init work for cst3xx..
++
++	INIT_WORK(&ts_data->work, cst3xx_work_handler);
++
++    ts_data->workqueue = create_singlethread_workqueue("cst3xx_wq");
++    if (!ts_data->workqueue) {
++        HYN_ERROR("create cst3xx workqueue fail");
++    }
++
++//    spin_lock_init(&ts_data->irq_lock);
++//    mutex_init(&ts_data->report_mutex);
++//    mutex_init(&ts_data->bus_lock);
++
++    /* Init communication interface */
++    ret = cst3xx_bus_init(ts_data);
++    if (ret) {
++        HYN_ERROR("bus initialize fail");
++        goto err_bus_init;
++    }
++#if USE_ANALOG_I2C
++        if (gpio_is_valid(I2CSDA)
++        {
++            gpio_free(I2CSDA);
++            ret = gpio_request(GPIO_PB(23),"I2C2-SDA");
++            if(ret < 0){
++                printk("I2C2-SDA gpio request failed\n");
++                return ret;
++            }
++        }
++         if (gpio_is_valid(I2CSCL))
++        {
++            gpio_free(I2CSCL);
++            ret = gpio_request(GPIO_PB(22),"I2C2-SCL");
++            if(ret < 0){
++                printk("I2C2-SCL gpio request failed\n");
++                return ret;
++            }
++         }
++#endif
++       ret =  cst3xx_i2c_test(ts_data->client);
++       if(ret>=0){
++
++          mdelay(100);
++
++          printk( KERN_INFO "cst3xx test OK -------------------\n");
++#ifdef HYN_UPDATE_FIRMWARE_ENABLE
++	        ret = cst3xx_boot_update_fw(ts_data,pcst3xx_update_firmware);//
++			if(ret < 0){
++			printk(" cst3xx hyn_boot_update_fw failed.\n");
++			return -1;
++			}
++#endif
++
++       }else{
++          printk( KERN_INFO "cst3xx hyn i2c communication failed.---------------\n");
++		  return -1;
++       }
++
++    ret = cst3xx_input_init(ts_data);
++    if (ret) {
++        HYN_ERROR("input initialize fail");
++        goto err_input_init;
++    }
++
++    ret = cst3xx_gpio_configure(ts_data);
++    if (ret) {
++        HYN_ERROR("configure the gpios fail");
++        goto err_gpio_config;
++    }
++       printk( KERN_INFO "cst3xx reset ----before---------------\n");
++       cst3xx_reset(ts_data);
++       printk( KERN_INFO "cst3xx reset ----after--------------\n");
++
++    ret = cst3xx_irq_registration(ts_data);
++    if (ret) {
++        HYN_ERROR("request irq failed");
++        goto err_irq_req;
++    }
++
++    HYN_FUNC_EXIT();
++    return 0;
++
++err_irq_req:
++    if (gpio_is_valid(ts_data->pdata->reset_gpio))
++        gpio_free(ts_data->pdata->reset_gpio);
++    if (gpio_is_valid(ts_data->pdata->int_gpio))
++        gpio_free(ts_data->pdata->int_gpio);
++err_gpio_config:
++    kfree_safe(ts_data->point_buf);
++    kfree_safe(ts_data->events);
++err_input_init:
++    if (ts_data->workqueue)
++        destroy_workqueue(ts_data->workqueue);
++err_bus_init:
++    kfree_safe(ts_data->bus_tx_buf);
++    kfree_safe(ts_data->bus_rx_buf);
++    kfree_safe(ts_data->pdata);
++
++    HYN_FUNC_EXIT();
++    return ret;
++}
++static int cst3xx_ts_probe(struct i2c_client *client, const struct i2c_device_id *id)
++{
++    int ret = 0;
++    struct cst3xx_ts_data *ts_data = NULL;
++	struct input_dev *input_dev;
++
++	struct cst3xx_platform_data *pdata = (struct cst3xx_platform_data*)client->dev.platform_data;
++
++    HYN_INFO("Touch Screen(I2C BUS) driver prboe...");
++    if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
++        HYN_ERROR("I2C not supported");
++        return -ENODEV;
++    }
++
++    /* malloc memory for global struct variable */
++    ts_data = (struct cst3xx_ts_data *)kzalloc(sizeof(*ts_data), GFP_KERNEL);
++    if (!ts_data) {
++        HYN_ERROR("allocate memory for cst3xx_data fail");
++        return -ENOMEM;
++    }
++    ts_data->client = client;
++    ts_data->dev = &client->dev;
++    ts_data->pdata = pdata;
++    i2c_set_clientdata(client, ts_data);
++
++    ret = cst3xx_ts_probe_entry(ts_data);
++    if (ret) {
++        HYN_ERROR("Touch Screen(I2C BUS) driver probe fail");
++        kfree_safe(ts_data);
++        return ret;
++    }
++	if(client->addr != 0x1A) //check address
++	{
++		client->addr = 0x1A;
++		printk(">>>>>>>>>>>>>1>>>xtang:i2c_client_HYN->addr=%d.\n",client->addr);
++
++	}else
++		printk(">>>>>>>>>>>>2>>>>xtang:i2c_client_HYN->addr=%d.\n",client->addr);
++
++
++    HYN_INFO("Touch Screen(I2C BUS) driver prboe successfully");
++    return 0;
++}
++
++
++static int cst3xx_ts_remove(struct i2c_client *client)
++{
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++        free_irq(ts->irq,ts);
++        devm_free_irq(&ts->client->dev, ts->client->irq,ts);
++        destroy_workqueue(ts->workqueue);
++        input_unregister_device(ts->input_dev);
++        devm_gpio_free(&ts->client->dev, ts->pdata->reset_gpio);
++        gpio_free(ts->pdata->int_gpio);
++
++#if USE_ANALOG_I2C
++         gpio_free(I2CSDA);
++        gpio_free(I2CSCL);
++#endif
++//i2c bus init.
++	cst3xx_bus_exit(ts);
++
++	return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int cst3xx_ts_suspend(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++
++	if (device_may_wakeup(&client->dev)) {
++		enable_irq_wake(client->irq);
++	} else {
++		disable_irq(client->irq);
++		cst3xx_ts_power(ts, false);//reset
++	}
++
++	return 0;
++}
++
++static int cst3xx_ts_resume(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++
++	if (device_may_wakeup(&client->dev)) {
++		disable_irq_wake(client->irq);
++	} else {
++		cst3xx_ts_power(ts, true);
++		enable_irq(client->irq);
++	}
++	return 0;
++}
++
++#endif
++
++static SIMPLE_DEV_PM_OPS(cst3xx_ts_pm_ops,
++			 cst3xx_ts_suspend, cst3xx_ts_resume);
++
++static const struct i2c_device_id cst3xx_ts_id[] = {
++	{ CST3XX_NAME, 0 },
++	{ }
++};
++static const struct of_device_id cst3xx_dt_match[] = {
++    {.compatible = "hyn,cst3xx", },
++    {},
++};
++MODULE_DEVICE_TABLE(of, cst3xx_dt_match);
++
++static struct i2c_driver cst3xx_ts_driver = {
++    .probe = cst3xx_ts_probe,
++    .remove = cst3xx_ts_remove,
++    .driver = {
++        .name = CST3XX_NAME,
++        .owner = THIS_MODULE,
++        .of_match_table = of_match_ptr(cst3xx_dt_match),
++	.pm	= &cst3xx_ts_pm_ops,
++    },
++    .id_table = cst3xx_ts_id,
++};
++
++static int __init cst3xx_ts_init(void)
++{
++    int ret = 0;
++
++    HYN_FUNC_ENTER();
++    ret = i2c_add_driver(&cst3xx_ts_driver);
++    if ( ret != 0 ) {
++        HYN_ERROR("hyn touch screen driver init failed!");
++    }
++    HYN_FUNC_EXIT();
++    return ret;
++}
++
++static void __exit cst3xx_ts_exit(void)
++{
++    i2c_del_driver(&cst3xx_ts_driver);
++}
++module_init(cst3xx_ts_init);
++module_exit(cst3xx_ts_exit);
++
++MODULE_AUTHOR("HYN Driver Team");
++MODULE_DESCRIPTION("HYN Touchscreen Driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Debug_driver/ref_cst3xx_MCU_driver_0729_update1/hyn_cst3xx_RS659_fw.h b/module_drivers/drivers/input/touchscreen/hyn_touch/Debug_driver/ref_cst3xx_MCU_driver_0729_update1/hyn_cst3xx_RS659_fw.h
+new file mode 100644
+index 000000000..006c36c81
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Debug_driver/ref_cst3xx_MCU_driver_0729_update1/hyn_cst3xx_RS659_fw.h
+@@ -0,0 +1,1553 @@
++
++#ifndef __CST3xx_FW_H__
++#define __CST3xx_FW_H__
++
++  unsigned char cst3_fw[] ={
++    0x98,0xE0,0x07,0x01,0xB0,0x88,0x01,0x00,0x00,0x00,0x00,0x00,0xB0,0x48,0x01,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x80,0x68,0x06,0x00,0x80,0x68,0x07,0x00,0x00,0x00,0x00,0x00,
++    0x88,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x88,0xD8,0x00,0x00,0x80,0x07,0xC0,0x17,
++    0x82,0x07,0xC0,0x07,0x01,0x65,0x40,0x86,0xC1,0x41,0xC0,0x20,0xC5,0x68,0x31,0x12,
++    0xF5,0x38,0x33,0x5A,0x32,0xA2,0x32,0xEA,0x10,0x62,0x8D,0x0E,0x81,0x07,0xC0,0x97,
++    0x30,0xF2,0xF3,0x79,0x65,0x7E,0x30,0xB2,0x31,0x09,0x10,0x9A,0x87,0x06,0xD0,0xD8,
++    0x35,0x12,0x35,0x5A,0x18,0x9A,0x39,0xC2,0xE0,0xE2,0x03,0x00,0xE0,0xE2,0x04,0x00,
++    0xD0,0x81,0x98,0x16,0x43,0xC6,0x0B,0xC6,0xC2,0xD6,0x3F,0x90,0x99,0x0E,0x40,0x86,
++    0x08,0x86,0xA9,0x0E,0x40,0x23,0x00,0x63,0x38,0x82,0x03,0x00,0x18,0x01,0x20,0x01,
++    0x28,0x01,0x30,0x01,0xD0,0x81,0x98,0x0E,0x0F,0xC6,0xC3,0xDE,0x38,0x90,0x9A,0x06,
++    0x08,0x86,0xA9,0x06,0x03,0x5B,0x38,0x82,0xAE,0xFD,0x30,0x02,0x30,0x02,0xEE,0xFD,
++    0xA8,0x85,0xE8,0x85,0x86,0x2F,0xE0,0x1F,0x37,0x8A,0xB8,0xFF,0xF8,0xAF,0x87,0x0F,
++    0xC0,0xCF,0x85,0x2F,0xE7,0xDF,0xBE,0xFF,0xF8,0x9F,0x87,0x2F,0xE0,0x0F,0x07,0x00,
++    0xAF,0x85,0x6F,0xD2,0xE1,0x43,0x31,0x4A,0xCA,0x01,0x3E,0x30,0x34,0x42,0x80,0x01,
++    0xF6,0x1B,0xF4,0x23,0xF3,0x53,0xC2,0x01,0x70,0x01,0xD8,0x16,0xE7,0x6B,0x4D,0x68,
++    0x80,0x4E,0x28,0x01,0x10,0x6C,0xAE,0x6B,0xA4,0x2B,0x12,0xD2,0x8A,0x16,0xB0,0x63,
++    0x00,0x09,0xB0,0x43,0xE8,0x85,0x37,0x72,0xEA,0x4B,0xE0,0x48,0x91,0x4D,0xAE,0x8B,
++    0x57,0xAC,0x7F,0x5A,0x10,0xEA,0x95,0x0E,0xE7,0x68,0x13,0xAC,0x48,0xF9,0x8F,0x0E,
++    0x10,0x12,0x85,0x16,0xE0,0x0B,0x4A,0x09,0x8B,0x26,0xB0,0x9B,0x09,0x01,0xA8,0x8B,
++    0xA7,0x0B,0xEA,0x85,0x4F,0x09,0x8C,0xE6,0x0A,0x09,0xA0,0x0B,0xE8,0x85,0xAF,0x85,
++    0x66,0xF2,0xE6,0x01,0x00,0x0F,0x80,0x0F,0xE1,0xAF,0xF7,0x03,0x47,0x01,0x80,0xD6,
++    0xEB,0x85,0xA8,0x85,0x70,0xDA,0x2E,0x09,0x1E,0xAB,0x65,0xC2,0xE7,0x03,0x09,0x79,
++    0x01,0x42,0xA0,0x03,0x00,0x0F,0x80,0x0F,0xE1,0x2F,0xE7,0x03,0x37,0x00,0xAE,0xD6,
++    0x05,0x01,0x18,0x83,0xE1,0x03,0x19,0x42,0xA3,0x03,0xE9,0x85,0x42,0x7A,0xC6,0x01,
++    0xE6,0x0B,0x44,0x8A,0x48,0x01,0x80,0x3E,0x4A,0x82,0x06,0x0B,0x0E,0xF9,0x57,0x72,
++    0x8A,0x89,0x97,0x01,0x10,0x8B,0x00,0x17,0x48,0x62,0xCE,0xE1,0x07,0x0B,0x0A,0xF9,
++    0x8E,0x21,0x01,0x0B,0x08,0x09,0x08,0x0B,0x08,0x0B,0x0C,0x31,0x08,0x0B,0x0A,0x59,
++    0x18,0x0B,0x0C,0x81,0x18,0x0B,0x0A,0x01,0x1B,0x0B,0x38,0x82,0xAD,0x85,0x40,0xFA,
++    0xE6,0x03,0x38,0x00,0x81,0x8E,0x00,0xE1,0x83,0x0F,0xC8,0x0F,0x40,0xDA,0x0D,0x01,
++    0xC4,0x01,0xA9,0x0B,0xBE,0xFF,0xFF,0x97,0x4D,0xC2,0x55,0xEA,0xCD,0x01,0x46,0xEA,
++    0x84,0x1F,0xD8,0xCF,0x00,0x01,0x80,0x0F,0xC8,0x77,0xE9,0x85,0xAD,0x85,0x40,0x9A,
++    0xC6,0x01,0xE9,0x03,0x40,0x01,0x88,0x36,0x46,0x82,0xC5,0x01,0xE0,0x03,0x44,0x29,
++    0xCF,0x0E,0xB8,0xFF,0xFD,0xE7,0x64,0x6A,0xE0,0x03,0x39,0x00,0xAF,0x0E,0xB8,0xFF,
++    0xFB,0x07,0xE5,0x03,0x38,0x00,0xAC,0x2E,0x42,0x5A,0xC5,0x01,0x42,0x0B,0x40,0x48,
++    0x00,0x48,0x02,0x0B,0xE7,0x03,0x0B,0xE9,0x03,0x42,0xA0,0x03,0x40,0x52,0xC5,0x03,
++    0x40,0x01,0x80,0x16,0x83,0x0F,0xE0,0xF7,0x38,0xE7,0xEF,0x85,0xAD,0x85,0x48,0x3A,
++    0x04,0x01,0x00,0x43,0x4E,0xEA,0xCC,0x01,0xB2,0x43,0xF0,0x43,0x80,0x0F,0xC8,0xFF,
++    0xEB,0x85,0xA8,0x85,0x30,0x2A,0x20,0x49,0x18,0x22,0x4F,0x01,0x80,0x46,0x68,0x01,
++    0x80,0x16,0x30,0x82,0xC0,0x61,0x00,0x4F,0x30,0x82,0x80,0x61,0x20,0x51,0x00,0x2F,
++    0x68,0x01,0x80,0x0E,0xF0,0x80,0x04,0x0F,0xE0,0x80,0x24,0x51,0x0A,0x01,0xF0,0x0A,
++    0x48,0x01,0xD0,0x06,0x16,0x4A,0x0A,0x40,0x0A,0x01,0xF0,0x8A,0x81,0x2F,0xD8,0xA7,
++    0x40,0xF9,0xEB,0x06,0x00,0xF9,0x6B,0x01,0x87,0x16,0x08,0xF9,0x88,0x09,0xD0,0x40,
++    0xCB,0x00,0xE8,0x85,0xAC,0x85,0x6B,0x2A,0xED,0x01,0xE4,0x43,0x41,0x01,0x80,0x26,
++    0x32,0x62,0xA1,0x01,0x40,0x03,0x41,0x01,0x81,0xFE,0x30,0x0A,0xCC,0x01,0x44,0x2A,
++    0x81,0x17,0xC8,0x3F,0x0F,0x01,0x40,0xF9,0x8D,0xC6,0xF0,0x03,0xE3,0x01,0xB4,0x03,
++    0x11,0x11,0x30,0x02,0x82,0x01,0xA1,0x13,0xA8,0x0B,0x01,0x01,0x12,0x79,0x28,0x29,
++    0x5B,0xE2,0x0B,0x68,0xF8,0x23,0x03,0x37,0x0A,0x21,0x19,0x0A,0xC2,0x48,0xCE,0x48,
++    0x92,0x53,0xE0,0x00,0x94,0x05,0x16,0x22,0xC3,0xB6,0xEF,0x85,0x47,0xF1,0x87,0xE6,
++    0x47,0x01,0x80,0xD6,0xF0,0x00,0x12,0x09,0x44,0x1B,0x01,0x12,0x17,0x9A,0x80,0xA6,
++    0xA3,0x4B,0xED,0x85,0xAB,0x85,0x51,0x92,0x28,0x01,0x20,0x01,0x08,0x01,0x00,0x01,
++    0xC4,0x9B,0x10,0x5A,0xC8,0x06,0x30,0xCA,0x58,0xD1,0x9F,0x0E,0x28,0x09,0x00,0x27,
++    0xE2,0x90,0xE2,0x00,0x90,0x05,0x46,0x31,0x99,0x96,0x4F,0xE1,0x92,0x5E,0x40,0xFA,
++    0xC4,0x01,0xE6,0x03,0x40,0x29,0xC8,0x36,0x41,0x12,0x0B,0x81,0xF3,0x0A,0x4A,0xC1,
++    0xD8,0x0E,0x28,0x09,0x03,0x1F,0xE0,0x20,0x90,0x25,0x67,0x71,0x98,0xF6,0x16,0x01,
++    0x48,0x02,0x6B,0x01,0x82,0x7E,0x40,0x44,0xE4,0x00,0x92,0x05,0x00,0x44,0x42,0xA1,
++    0xCC,0x46,0x40,0x44,0xE4,0x00,0x02,0x44,0x02,0x54,0x42,0x82,0x10,0x09,0xE0,0x0B,
++    0x18,0x8A,0xA0,0x0B,0xEA,0x85,0x01,0x54,0xEF,0x85,0xA9,0x85,0x80,0x3D,0x04,0x01,
++    0x80,0x14,0x80,0x1C,0x00,0x01,0x08,0x01,0x10,0x01,0x90,0x0C,0xD2,0x1C,0x58,0x6A,
++    0x06,0x90,0x32,0x09,0xC5,0x90,0x06,0xB0,0xC9,0xA0,0x34,0x2A,0x18,0x01,0x10,0x01,
++    0xF0,0x12,0xC5,0x80,0x92,0x05,0xE0,0x48,0x90,0x4D,0xF8,0x0C,0x10,0xD2,0xED,0x06,
++    0x90,0x0C,0xA0,0x61,0xE6,0xD8,0x92,0xDD,0x5F,0x71,0x98,0x86,0x84,0x2F,0xD0,0xA7,
++    0x90,0x25,0xC0,0x14,0x10,0x02,0xD5,0x06,0xA0,0x14,0x38,0x01,0x60,0x01,0xE8,0xAE,
++    0x35,0x01,0xF8,0x72,0x10,0x32,0xDD,0x66,0xC6,0x0C,0x78,0x08,0xC2,0x40,0x80,0x00,
++    0x10,0x32,0xD4,0x8E,0x09,0x19,0x30,0x82,0x83,0x2F,0xD0,0xF7,0xD1,0x80,0x01,0x44,
++    0x00,0x57,0x70,0x01,0xE8,0x46,0x00,0x09,0x00,0x44,0x01,0x2F,0x01,0x01,0xF0,0x42,
++    0x10,0x02,0xE5,0x0E,0xD9,0x00,0x00,0x44,0xAB,0x61,0xE0,0xF8,0x90,0xFD,0x7F,0x71,
++    0x98,0xE6,0xC6,0x1C,0xE6,0x00,0x92,0x05,0x80,0x1C,0xC0,0x1C,0x45,0x31,0x98,0x8E,
++    0x00,0x01,0x80,0x24,0x00,0x01,0x08,0x01,0x38,0x01,0xD0,0x24,0x1A,0x61,0x18,0xD2,
++    0x5E,0x22,0xC1,0x98,0x14,0x09,0x06,0x90,0xC0,0xD0,0x34,0xA2,0x18,0x01,0x30,0x01,
++    0xF9,0xB2,0xC4,0x80,0x92,0x05,0xE0,0x48,0x95,0x4D,0x10,0xF2,0xE9,0x06,0x30,0xBA,
++    0xE2,0x90,0xE4,0xD8,0x90,0xDD,0x5E,0x31,0x98,0x8E,0x87,0x2F,0xD0,0x2F,0x92,0x2D,
++    0xC5,0x14,0x10,0x42,0xD0,0x06,0xA8,0x14,0x30,0x01,0x68,0x01,0xE8,0xA6,0x01,0x01,
++    0xF0,0x02,0x81,0x34,0x10,0x42,0xDD,0x9E,0x09,0x19,0x30,0x42,0x81,0x2F,0xD0,0xA7,
++    0xC8,0x34,0xD0,0x40,0x91,0x05,0x00,0x04,0x83,0x2C,0xD8,0xC0,0x41,0x41,0xD1,0x4E,
++    0x00,0x40,0x0B,0x19,0x81,0x2F,0xD0,0x47,0xC8,0x2C,0xD0,0x40,0x01,0x04,0x01,0x0F,
++    0xC0,0x34,0x40,0x01,0xE8,0xF6,0x00,0x09,0x00,0x04,0x01,0xDF,0x00,0xC0,0x06,0x01,
++    0x50,0x07,0x03,0x00,0x18,0x00,0x02,0x42,0x00,0x01,0x00,0x42,0x80,0x60,0x05,0x00,
++    0x58,0xC0,0x02,0x01,0x00,0xA0,0x07,0x01,0x00,0x80,0x00,0x01,0x10,0x00,0x00,0x42,
++    0x10,0xC0,0x00,0x01,0x00,0x00,0x00,0x01,0x01,0x01,0xF0,0x02,0x10,0x42,0xE5,0x0E,
++    0xD9,0x00,0x02,0x04,0xE3,0x20,0xE5,0xB0,0x90,0xB5,0x77,0x31,0x98,0xEE,0xC5,0x24,
++    0xE6,0x00,0x92,0x05,0x80,0x24,0xC0,0x24,0x44,0x71,0x98,0x9E,0xC5,0x14,0x50,0xD2,
++    0x40,0xE1,0xD1,0x26,0x7A,0x40,0xCF,0x00,0x82,0x00,0x82,0x83,0x00,0x0F,0x00,0xF1,
++    0x82,0x83,0xC2,0x8B,0x40,0xAA,0x4D,0x01,0x82,0x4E,0xF0,0x48,0x81,0x8B,0x8A,0x41,
++    0x32,0x12,0xD0,0x01,0x88,0x8B,0x08,0x31,0x98,0x0B,0x86,0x3D,0xE8,0x85,0x0F,0x11,
++    0x9F,0x0B,0x3E,0xD7,0xAD,0x85,0x47,0x6A,0x72,0x6A,0xC5,0x01,0xF1,0x2B,0x04,0x09,
++    0x09,0x00,0xC4,0xA0,0x69,0x09,0xC8,0x66,0x1F,0x01,0x10,0xF9,0x02,0x01,0x38,0x19,
++    0x08,0xF8,0x03,0x57,0x0A,0x31,0x18,0x0A,0xCE,0x48,0xCC,0x48,0x54,0x4C,0x10,0xCA,
++    0xC8,0x0E,0x30,0x5A,0x32,0x12,0xE0,0x00,0x94,0x05,0x16,0x2A,0xC7,0x96,0x57,0xF9,
++    0x82,0xBE,0x00,0x80,0xC9,0x08,0x04,0x09,0x08,0x00,0xC4,0x40,0xF1,0x0B,0xB0,0x0B,
++    0xF3,0x03,0xB2,0x03,0x02,0x31,0x18,0x12,0xCE,0x80,0xCC,0x00,0x4C,0xCA,0x4C,0x14,
++    0x0E,0x54,0x4C,0x14,0x08,0x54,0x56,0x04,0x14,0x44,0x48,0xA2,0x02,0x09,0xC8,0x01,
++    0xB4,0x43,0x44,0x92,0x3A,0x01,0xC0,0x01,0xF4,0x03,0x6C,0x7A,0x41,0x01,0x80,0x8E,
++    0xF3,0x03,0xF1,0x13,0x48,0x5C,0x0B,0x61,0x19,0xCA,0x4A,0x64,0xCB,0x48,0x04,0x30,
++    0xC8,0x48,0x34,0x19,0x14,0xB0,0xC9,0x70,0x0B,0x21,0xF0,0x8A,0x48,0x81,0xDA,0x06,
++    0x00,0x7C,0x47,0x01,0x80,0x0E,0x40,0x29,0x8D,0xCE,0x10,0x02,0x8C,0xBE,0x10,0xD2,
++    0x88,0xAE,0x18,0x61,0xF6,0x5A,0xD7,0x58,0x98,0x49,0x58,0x91,0xC7,0x7E,0x40,0x5C,
++    0x65,0x0A,0x14,0x1A,0x92,0x0E,0xE0,0xD8,0x07,0x5C,0x47,0x5C,0x58,0x41,0xCE,0x36,
++    0x03,0x7C,0x5F,0xD2,0x34,0x09,0x98,0x01,0xE1,0xE3,0x18,0xA2,0xA1,0xE3,0x08,0x44,
++    0x0D,0x54,0x0B,0x4C,0x42,0xAA,0xC3,0x01,0x51,0x04,0x46,0x91,0xCF,0x06,0x00,0x7C,
++    0xEF,0x85,0xAF,0x85,0x80,0x3D,0x2C,0x01,0x20,0x01,0x00,0x61,0x4B,0x82,0x1B,0x42,
++    0xC0,0x00,0x82,0x34,0x30,0x01,0x38,0x01,0x00,0x01,0x80,0x1C,0x80,0x14,0xC0,0x34,
++    0x00,0x08,0x13,0x19,0xC0,0x00,0x12,0x90,0xC0,0x10,0x04,0x21,0x90,0x2C,0xF0,0x82,
++    0x80,0x24,0x60,0x01,0x83,0x46,0xF0,0x10,0xDA,0x34,0x00,0x90,0xC0,0xD0,0x1C,0x19,
++    0x16,0xD8,0xC0,0x90,0x34,0x21,0xF8,0xB2,0x68,0x01,0x80,0x56,0xF0,0x50,0x1B,0x61,
++    0x1A,0xD2,0x5A,0xFA,0xC0,0x90,0x1E,0x19,0xC0,0x90,0x12,0xD8,0xC0,0x90,0x3E,0x21,
++    0xF8,0xBA,0x66,0x29,0x83,0x4E,0xE0,0x18,0xD2,0x34,0x00,0xD8,0xC0,0x90,0x1E,0x19,
++    0x16,0xD8,0xC0,0x90,0x1E,0x21,0xF0,0x9A,0x98,0x1C,0x68,0x69,0x83,0x5E,0xE0,0x50,
++    0x1A,0x61,0x18,0xD2,0x5E,0x92,0xC2,0x90,0xC0,0x88,0x12,0x19,0x14,0x90,0xC0,0x50,
++    0x0A,0x21,0xF0,0x8A,0x88,0x14,0x08,0x09,0x89,0x0C,0x70,0x41,0xD1,0x3E,0x78,0x41,
++    0xD0,0x2E,0xC8,0x1C,0x48,0x41,0xD1,0x16,0xC9,0x14,0x48,0x41,0xD8,0x0E,0x08,0x01,
++    0x88,0x0C,0x08,0x19,0x80,0x2F,0xC8,0x47,0x10,0x82,0xED,0x3E,0x10,0xC2,0xED,0x2E,
++    0xCC,0x1C,0x10,0x42,0xE8,0x16,0xC8,0x14,0x10,0x42,0xE4,0x0E,0x00,0x01,0x80,0x0C,
++    0xC0,0x0C,0x40,0x01,0x80,0x36,0xC0,0x24,0x78,0x08,0xC6,0x48,0x82,0x48,0xD2,0x00,
++    0xCC,0x2C,0x00,0x44,0xE7,0x20,0x93,0x25,0x64,0x31,0x98,0x9E,0xE7,0x68,0x93,0x6D,
++    0x6C,0x71,0x98,0x4E,0x3B,0x4F,0xA8,0x85,0x48,0x9A,0x01,0x01,0x06,0x44,0x04,0x44,
++    0x82,0x43,0x80,0x43,0x40,0x8A,0x29,0x09,0x80,0x01,0xE4,0x0B,0x18,0x4A,0xA1,0x0B,
++    0x31,0x22,0xE0,0x01,0x07,0x9F,0xBA,0xFF,0xE9,0xCF,0x43,0x82,0xC0,0x03,0x40,0x01,
++    0x81,0x1E,0x48,0x52,0x02,0xC1,0xC8,0x01,0xB1,0x43,0x40,0x42,0x51,0x62,0x49,0x42,
++    0xC0,0x01,0x82,0x1F,0xF7,0x0F,0xBD,0xFF,0xE9,0x4F,0x49,0x22,0x52,0x42,0xC9,0x01,
++    0x40,0x1A,0x81,0x27,0xC1,0x17,0x4C,0x0A,0x52,0x2A,0xC9,0x01,0x40,0x02,0x81,0x27,
++    0xFF,0x0F,0xBC,0xFF,0xEF,0x3F,0xEE,0x03,0x40,0x01,0x80,0x16,0xE8,0x03,0x47,0x11,
++    0x89,0x1E,0x40,0x02,0x41,0x0B,0x18,0x4A,0x00,0x0B,0x40,0xC2,0x0E,0x11,0x98,0x0B,
++    0x32,0x0A,0xC8,0x01,0x40,0xB2,0x80,0x27,0xE8,0xC7,0x4D,0xA2,0x42,0xA2,0xC8,0x01,
++    0x86,0x27,0xE0,0x7F,0xBF,0xFF,0xEF,0x4F,0xB9,0xFF,0xFF,0xDF,0x48,0x7A,0x40,0x82,
++    0xC8,0x01,0x82,0x27,0xE0,0xF7,0x4A,0x6A,0x12,0x01,0xC8,0x01,0x40,0x62,0x58,0x92,
++    0x85,0x17,0xE8,0x57,0xBD,0xFF,0xF7,0xB7,0xBB,0xFF,0xE7,0xD7,0x48,0x3A,0x40,0x42,
++    0xC8,0x01,0x82,0x0F,0xF0,0x6F,0x80,0x07,0xDF,0x47,0xB8,0xFF,0xE7,0xFF,0xEF,0x03,
++    0x45,0x31,0x88,0x46,0xE8,0x85,0x03,0x00,0x00,0x00,0x00,0x01,0x00,0xC0,0x02,0x01,
++    0x00,0xA0,0x07,0x01,0x48,0xA0,0x02,0x01,0x38,0x81,0x00,0x00,0x00,0x80,0x00,0x01,
++    0x58,0xC0,0x02,0x01,0xF8,0x00,0x06,0x42,0x18,0xD8,0x05,0x00,0xA8,0x85,0x33,0x22,
++    0xF0,0x03,0x83,0x07,0xF1,0xA7,0x41,0x9A,0x2C,0x01,0x00,0x2B,0xB5,0x2B,0x01,0xB1,
++    0xAF,0x2A,0xB8,0xFF,0xE4,0x1F,0xA5,0x01,0xFA,0x03,0x31,0x08,0x42,0x72,0x71,0x48,
++    0x1C,0x0B,0x5C,0x0B,0x02,0x48,0x1A,0x0B,0x09,0x2B,0xFE,0x0B,0x30,0x48,0xA8,0x16,
++    0x0E,0x09,0x04,0x0B,0x1B,0x2B,0xE8,0x85,0xAD,0x85,0x87,0x9D,0x42,0x32,0xC1,0x01,
++    0x42,0x0B,0x40,0x48,0x00,0x48,0x02,0x0B,0x51,0x22,0x49,0x2A,0x40,0x2A,0x81,0x0F,
++    0xC1,0x97,0x67,0x1A,0x35,0x2A,0xA9,0x01,0x01,0xBF,0x41,0x0A,0xBE,0xFF,0xFF,0x77,
++    0x52,0x03,0x81,0x01,0xE7,0x03,0x40,0x79,0x80,0x0E,0x51,0xEA,0x48,0xEA,0x00,0x01,
++    0x58,0xD2,0x80,0x07,0xF8,0x2F,0x51,0xD2,0x48,0xD2,0x00,0x09,0x58,0xBA,0x80,0x07,
++    0xF9,0xFF,0x50,0x03,0x80,0x01,0xE2,0x03,0x40,0x59,0x8D,0x86,0x40,0xB2,0x48,0xAA,
++    0x88,0xA1,0x11,0x01,0xD5,0x3B,0xD7,0x1B,0x18,0xFA,0x42,0x5C,0x44,0x34,0xD8,0xD8,
++    0x04,0x1C,0xE0,0x00,0xE2,0x48,0xE4,0x90,0x95,0x95,0x14,0xD2,0x99,0xAE,0x57,0x03,
++    0x80,0x01,0xE2,0x03,0x40,0x59,0x85,0x2E,0x50,0x42,0x48,0x4A,0x40,0x4A,0x58,0x0D,
++    0x80,0x0F,0xC0,0xBF,0x40,0x0D,0x80,0x07,0xDF,0xFF,0xE9,0x43,0x46,0x31,0x80,0x26,
++    0x87,0x9D,0xE9,0x85,0x10,0x00,0x00,0x42,0x00,0x01,0x00,0x42,0x58,0xC0,0x02,0x01,
++    0x00,0xC0,0x00,0x01,0x00,0xA0,0x07,0x01,0x18,0xC0,0x07,0x01,0x4C,0xFA,0x6F,0x54,
++    0x82,0x13,0x68,0x54,0x80,0x13,0x32,0x52,0x92,0x01,0xF5,0x93,0x80,0x13,0xCC,0x4B,
++    0x83,0x0B,0x3E,0x82,0xA8,0x85,0xF3,0x24,0x63,0xC2,0xFF,0x23,0x11,0x22,0xCC,0x56,
++    0x23,0x21,0x19,0x02,0x60,0xB2,0xCF,0x00,0x23,0x29,0x0A,0x20,0xCE,0x00,0x50,0x24,
++    0x58,0x2C,0x48,0x09,0x8E,0x26,0x50,0x0C,0x23,0xF9,0xA7,0x49,0xD4,0x08,0x93,0x65,
++    0x50,0x09,0x88,0x26,0x58,0x0C,0x10,0xC9,0x0A,0x90,0xD2,0x88,0x90,0x6D,0xD4,0x0B,
++    0xD0,0x13,0x0A,0x48,0x00,0x90,0x1A,0x8A,0x81,0xCB,0x48,0x08,0x81,0xCB,0x4A,0x48,
++    0x81,0xCB,0x0C,0x08,0x38,0x50,0x79,0x90,0x1E,0x8A,0x80,0xCB,0x58,0x04,0x8A,0xC3,
++    0xC2,0x83,0xE9,0x00,0x83,0x83,0xE9,0x85,0xAC,0x85,0x87,0x2D,0x0F,0x01,0x00,0x0D,
++    0x40,0x2E,0x90,0x24,0x86,0x1C,0x40,0xEA,0xFA,0x2B,0xF8,0x1B,0x06,0x01,0x60,0xFA,
++    0x51,0xFA,0xC6,0x33,0x70,0x59,0x85,0x1E,0xE4,0x00,0x92,0x05,0x17,0x82,0x9C,0xC6,
++    0x50,0xE2,0x46,0x83,0x31,0x09,0x18,0x82,0x07,0x83,0x00,0xF9,0x80,0x03,0x69,0x01,
++    0x80,0xBE,0x08,0x01,0x50,0x1D,0x00,0x01,0x2E,0x29,0x62,0x8A,0x08,0x68,0x03,0x77,
++    0x32,0x21,0x19,0x32,0xCB,0xB0,0xC9,0xB0,0xD0,0xB3,0x75,0x09,0x88,0x2E,0x80,0x83,
++    0xE6,0x48,0x92,0x4D,0xE0,0x90,0x4A,0x29,0x82,0x1E,0xE0,0x00,0x94,0x05,0x16,0xC2,
++    0x98,0x76,0x8F,0x0C,0x60,0x4A,0x6E,0x1D,0x36,0x01,0x78,0x22,0xB9,0x01,0x06,0x0F,
++    0x70,0x01,0x88,0x9E,0x50,0x15,0x90,0x04,0x11,0x01,0xC0,0x43,0x30,0x1A,0x31,0x8A,
++    0xBC,0xFF,0xFF,0x47,0xE5,0x68,0xE3,0xC3,0xCE,0x0C,0x48,0x00,0x08,0x00,0x1E,0x42,
++    0x8D,0x03,0x03,0x59,0x8D,0x03,0xED,0x20,0xE0,0x20,0x03,0x4F,0x50,0x15,0x90,0x04,
++    0x11,0x01,0xC0,0x43,0x30,0x1A,0x31,0x8A,0xBB,0xFF,0xFF,0xA7,0xE3,0x68,0xEB,0x20,
++    0xE7,0xB0,0x93,0xB5,0xC4,0x0C,0x10,0x32,0x9D,0xD6,0xE6,0xC3,0x1E,0x01,0x4C,0x08,
++    0x48,0x01,0x80,0x96,0xC8,0x0C,0x48,0x01,0x81,0x36,0x80,0x03,0xEB,0xC3,0x81,0x03,
++    0x05,0x59,0x85,0x03,0xE0,0x20,0x05,0x37,0x81,0x03,0xE9,0xC3,0x83,0x03,0x8B,0x1B,
++    0x05,0x59,0x8D,0x03,0xEB,0x20,0xE5,0x20,0x00,0x2F,0xC0,0x0C,0x40,0x09,0xC8,0x16,
++    0x01,0x59,0x85,0x03,0xE1,0x20,0x33,0x02,0xBA,0xFF,0xFF,0x07,0x4A,0x32,0x45,0x43,
++    0x10,0x01,0x1A,0x82,0x05,0x43,0x4A,0x2A,0x40,0x43,0x1A,0xC2,0x03,0x43,0xE2,0xC3,
++    0x08,0x11,0x18,0x42,0xA0,0xC3,0x83,0x2D,0xEF,0x85,0xAF,0xFD,0x80,0x0D,0xFC,0x54,
++    0x30,0x32,0x30,0x62,0x6E,0xAA,0xAC,0x01,0x50,0x09,0x88,0x4E,0x00,0x0F,0x80,0x0F,
++    0xC1,0xCF,0xE1,0x43,0x37,0x00,0xAA,0xD6,0xE5,0x43,0x09,0xF9,0x01,0x42,0xA0,0x43,
++    0x04,0x09,0x30,0x22,0x51,0xAA,0x04,0x8F,0x60,0x01,0xC1,0x2E,0xF7,0x00,0x0B,0x01,
++    0x1A,0x42,0x08,0x83,0x30,0x0A,0x01,0x17,0x02,0xF9,0x0F,0x83,0x08,0x01,0x19,0x01,
++    0x08,0x9B,0x04,0x01,0x00,0x4F,0x78,0x01,0x88,0x16,0x18,0x01,0x00,0x9B,0x06,0x17,
++    0xC6,0x9B,0x01,0x9B,0xCA,0xB0,0xE7,0x00,0x94,0x05,0x14,0x42,0x9B,0x9E,0x37,0x02,
++    0x40,0x01,0x80,0x26,0x04,0xA1,0x00,0x83,0x04,0x01,0x30,0x22,0x00,0x0F,0x00,0x21,
++    0x03,0x83,0xD4,0x00,0x92,0x25,0x44,0x83,0x08,0x01,0x1C,0x42,0x01,0x83,0xE2,0x43,
++    0x37,0x00,0xAA,0xE6,0xE5,0x43,0x09,0xF9,0x01,0x42,0xA0,0x43,0x66,0x01,0x88,0x5E,
++    0xC0,0x24,0x40,0x09,0x88,0x7E,0x05,0x01,0x02,0x83,0x44,0x83,0x08,0x01,0x1C,0x42,
++    0x05,0x83,0x3A,0x47,0xAC,0x9D,0x87,0x1D,0x20,0x01,0x00,0x01,0x80,0x0C,0x70,0x15,
++    0x40,0x52,0xF3,0x03,0xEE,0x00,0x92,0x3D,0x6E,0x42,0xAB,0x01,0x00,0xAF,0x81,0x07,
++    0xF9,0x0F,0xE7,0x43,0x30,0x00,0xA2,0x1E,0x40,0x22,0xF3,0x03,0x17,0xC2,0x9D,0xB6,
++    0x40,0x12,0xF3,0x03,0x10,0xC2,0x9D,0x06,0x21,0x11,0xE0,0x43,0x08,0xF9,0x05,0x42,
++    0xA3,0x43,0x41,0x32,0x46,0x0B,0x14,0x79,0x00,0x8A,0x48,0x09,0x88,0x9E,0x08,0x01,
++    0x0E,0x0B,0x44,0x0B,0x83,0x8B,0xE1,0xB0,0xE7,0x20,0x93,0x25,0x60,0x11,0x88,0x56,
++    0x30,0x5A,0xD3,0xCB,0xD4,0x1C,0x10,0x8A,0x8A,0x2E,0xD0,0xCB,0xD4,0x24,0x10,0x8A,
++    0x88,0x0E,0x08,0x09,0x8F,0x0C,0x08,0x01,0x08,0x0B,0x0A,0x01,0x08,0x0B,0x0C,0x81,
++    0x02,0x0B,0x44,0x0B,0x10,0x01,0x1C,0x8A,0x00,0x0B,0x62,0x11,0x88,0x4E,0xC6,0x0C,
++    0x3A,0x0F,0x4B,0x52,0x58,0x54,0x86,0x13,0x12,0x01,0x80,0x13,0xE4,0x4B,0x82,0x0B,
++    0x4A,0x62,0x8A,0x01,0x5E,0x53,0x84,0x13,0x58,0x53,0x8A,0x13,0x12,0x91,0x88,0x13,
++    0x14,0x19,0x88,0x13,0x4E,0x53,0x8E,0x13,0x48,0x53,0x94,0x13,0x4A,0x4B,0x92,0x0B,
++    0x0C,0x09,0x90,0x0B,0x3F,0x82,0xAB,0x85,0x80,0x4D,0x34,0x22,0x30,0x01,0x00,0x01,
++    0x80,0x2C,0x38,0x01,0x4C,0xCA,0xD1,0x43,0xD2,0x4B,0x1E,0x42,0x81,0x14,0x40,0xC2,
++    0x80,0x61,0x80,0x24,0xC0,0x61,0x80,0x1C,0x60,0x09,0x80,0x0E,0x60,0x29,0x88,0x76,
++    0x60,0x09,0x88,0x1E,0x70,0xD2,0xB1,0x2C,0x78,0xD2,0x01,0x27,0x73,0xD2,0xE1,0x80,
++    0x81,0x2C,0x78,0xC2,0xF8,0x81,0x41,0x35,0xBA,0xFF,0xF7,0xC7,0x00,0x3F,0x60,0x21,
++    0x89,0x2E,0x70,0xB2,0x47,0x35,0xB8,0xFF,0xF9,0xE7,0x7D,0x92,0xB9,0xA1,0x6A,0x3A,
++    0xA9,0x01,0xE6,0x43,0x08,0xF9,0x05,0x42,0xA1,0x43,0xE1,0x43,0x08,0x01,0x19,0x42,
++    0xA1,0x43,0x41,0x4A,0x42,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,0x4A,0x3A,0x41,0x43,
++    0x10,0x01,0x1C,0x82,0x01,0x43,0x4A,0x1A,0x40,0x43,0x10,0x09,0x18,0x82,0x00,0x43,
++    0x0C,0x09,0x00,0x01,0xBA,0xFF,0xFF,0xB7,0x42,0x09,0x88,0x66,0x62,0x21,0x88,0x5E,
++    0x10,0x09,0x90,0x04,0x30,0x82,0x19,0x01,0xCF,0x14,0xB8,0xFF,0xF0,0xB7,0x17,0x09,
++    0x90,0x04,0x10,0x01,0x08,0x59,0x40,0x35,0x37,0x9A,0xB8,0xFF,0xF0,0x77,0x17,0x09,
++    0x90,0x04,0x10,0x01,0x09,0x31,0x30,0xC2,0x37,0x9A,0xB8,0xFF,0xF0,0x37,0x17,0x09,
++    0x90,0x04,0x40,0xA2,0x10,0x01,0x08,0x71,0xC0,0x21,0x32,0x9A,0xBE,0xFF,0xF7,0xEF,
++    0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x31,0x30,0x9A,0xC0,0x24,0xBE,0xFF,0xF7,0xAF,
++    0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x31,0x18,0x09,0x00,0xCF,0x00,0xC0,0x00,0x01,
++    0x00,0xA0,0x07,0x01,0xFF,0xFF,0xFF,0xFF,0x00,0xF8,0x07,0x00,0x58,0x20,0x00,0x01,
++    0x90,0xE4,0x03,0x00,0xF8,0x00,0x06,0x42,0x00,0x00,0x06,0x42,0x80,0x01,0x06,0x42,
++    0x10,0xC0,0x00,0x01,0x40,0x60,0x07,0x01,0x18,0xC0,0x07,0x01,0x38,0xC0,0x05,0x01,
++    0xC7,0x1C,0xB8,0xFF,0xF2,0x97,0x05,0x27,0x60,0x09,0x80,0x0E,0x62,0x29,0x88,0x06,
++    0x60,0x09,0x88,0x76,0x10,0x09,0x90,0x04,0x30,0x82,0x19,0x01,0xCF,0x14,0xB8,0xFF,
++    0xF0,0x27,0x15,0x01,0x90,0x04,0x30,0x9A,0xC8,0x14,0xC0,0x2C,0xBC,0xFF,0xF7,0xEF,
++    0x00,0x7F,0x10,0x11,0x90,0x04,0x10,0x09,0x30,0x82,0x19,0x01,0xCF,0x14,0xB8,0xFF,
++    0xF0,0xA7,0x14,0x11,0x90,0x04,0x10,0x01,0x30,0x9A,0xC8,0x14,0xC7,0x2C,0xB8,0xFF,
++    0xF0,0x67,0x14,0x09,0x90,0x04,0x10,0x01,0x08,0x21,0x40,0x35,0x37,0x9A,0xB8,0xFF,
++    0xF0,0x27,0x14,0x09,0x90,0x04,0x10,0x01,0x09,0x41,0x31,0xC2,0x37,0x9A,0xB8,0xFF,
++    0xF0,0xE7,0x13,0x09,0x90,0x04,0x10,0x01,0x08,0x31,0x30,0x9A,0xC7,0x24,0xB8,0xFF,
++    0xF0,0xA7,0x13,0x09,0x90,0x04,0x10,0x01,0x08,0x31,0x18,0x09,0xC7,0x1C,0xB8,0xFF,
++    0xF1,0x67,0xE3,0x43,0x08,0xF9,0x06,0x42,0xA5,0x43,0x41,0x32,0x42,0x0B,0x40,0x48,
++    0x00,0x48,0x02,0x0B,0x47,0x22,0x0D,0x01,0x08,0x0B,0x0A,0x01,0x02,0x0B,0x44,0x0B,
++    0x10,0x01,0x1C,0x8A,0x00,0x0B,0x82,0x4D,0xEB,0x85,0xAF,0x85,0x67,0xFA,0xEC,0x03,
++    0x28,0x01,0x40,0x09,0x87,0x16,0xE8,0x03,0x40,0x29,0x88,0x5E,0x71,0xE2,0xC4,0x83,
++    0x40,0x11,0x98,0x26,0xEF,0x03,0xBF,0xFF,0xF1,0xF7,0x87,0xAB,0xEA,0x85,0xE3,0x00,
++    0x83,0x83,0xE9,0x85,0xE8,0x03,0x47,0x21,0x8F,0x26,0xB8,0xFF,0xF0,0xA7,0x07,0x19,
++    0xAB,0x03,0xEF,0x85,0xE8,0x03,0x47,0x19,0x87,0xDE,0xEF,0x03,0x47,0x31,0x80,0xC6,
++    0x4D,0x72,0xCC,0x01,0xF8,0x43,0x40,0x01,0x88,0x3E,0x30,0x42,0x80,0x01,0xF6,0x13,
++    0x50,0x31,0x98,0x3E,0xE0,0x03,0x34,0x00,0xAC,0x26,0x40,0x42,0xC4,0x01,0xE3,0x03,
++    0x40,0x01,0x80,0xA6,0xE8,0x03,0x47,0x01,0x8E,0x1E,0x57,0x44,0x47,0x31,0x88,0x06,
++    0x45,0x22,0x0C,0x59,0x82,0x0B,0x80,0x2B,0x86,0x2B,0x84,0x2B,0x8A,0x2B,0x88,0x2B,
++    0x8B,0x0B,0x44,0xE2,0x42,0x0B,0x40,0x48,0x00,0x48,0x02,0x0B,0xEF,0x85,0xBB,0xFF,
++    0xEB,0xDF,0xEB,0x85,0xA8,0xC5,0x27,0x01,0x30,0x1A,0x00,0x09,0x4B,0xBA,0x6B,0xD2,
++    0x30,0x01,0x59,0x51,0x80,0xE6,0xE1,0x4E,0x79,0xC2,0xE3,0xD3,0x87,0x27,0xE8,0xDF,
++    0x61,0x52,0x20,0x09,0x39,0x61,0x62,0x52,0x71,0x61,0x62,0x92,0x40,0x7A,0x13,0x31,
++    0xC0,0x01,0x55,0x03,0x80,0x01,0x5A,0xC9,0x80,0xAE,0xE1,0x4E,0x59,0x59,0x80,0x56,
++    0x59,0x61,0x80,0x66,0x59,0x69,0x88,0xBE,0x06,0x29,0xA8,0x43,0x21,0x09,0x00,0x9F,
++    0x59,0xD1,0x80,0x6E,0x59,0x01,0x89,0x7E,0xA8,0x53,0x26,0x09,0x08,0x59,0xA5,0x0B,
++    0x00,0x57,0x01,0x39,0xA9,0x43,0x06,0x3F,0x86,0x07,0xE8,0xF7,0x00,0x27,0x19,0x12,
++    0xA1,0xD3,0x01,0x0F,0x00,0x41,0x18,0x12,0xA0,0xD3,0x01,0xEF,0x06,0x11,0xA8,0x43,
++    0x20,0x09,0x00,0xCF,0x06,0x01,0xA8,0x43,0x41,0x43,0x19,0x82,0x00,0x43,0x01,0x9F,
++    0xA8,0x43,0x26,0x09,0x00,0x87,0x00,0x19,0xA8,0x43,0x26,0x09,0x00,0x67,0x00,0x21,
++    0xA8,0x43,0x26,0x09,0x06,0x47,0xA8,0x53,0x26,0x09,0x08,0x69,0xA0,0x0B,0x00,0x1F,
++    0xA8,0x53,0x26,0x09,0x08,0x79,0xA7,0x0B,0x60,0x01,0x80,0x66,0x40,0x82,0x42,0x0B,
++    0x30,0x48,0xA8,0x2E,0x08,0x81,0x06,0x0B,0x08,0x81,0x02,0x0B,0x08,0x81,0x00,0x0B,
++    0x45,0x43,0x19,0x82,0x07,0x43,0xE9,0xC5,0xAC,0x8D,0x87,0x25,0x40,0x4A,0x82,0x14,
++    0x45,0x12,0xC2,0x01,0xD6,0x2B,0xD4,0x33,0x08,0x01,0xB0,0x0B,0x61,0x1A,0xE2,0x0B,
++    0x10,0xF9,0x05,0x8A,0xA1,0x0B,0xE1,0x0B,0x10,0x01,0x19,0x8A,0xA2,0x0B,0x51,0x02,
++    0x92,0x01,0x46,0x8B,0x18,0x01,0x1A,0xCA,0x01,0x8B,0x52,0xBA,0x44,0x8B,0x1A,0x01,
++    0x1A,0xCA,0x00,0x8B,0x79,0x9A,0x41,0xCB,0x10,0x09,0x18,0x8A,0x00,0xCB,0x51,0x03,
++    0x80,0x01,0xE2,0x0B,0x49,0x79,0x87,0xDE,0xE6,0x03,0x40,0x69,0x88,0x46,0x09,0xA9,
++    0x07,0x91,0xB8,0xFF,0xE8,0x3F,0x46,0x09,0x89,0x0E,0x32,0x42,0x1A,0x82,0x03,0x08,
++    0x10,0x09,0x88,0x1C,0x94,0x04,0x90,0x4D,0x18,0x01,0xC0,0x14,0xBB,0xFF,0xEF,0x2F,
++    0x42,0xC3,0x41,0x00,0x01,0x00,0x02,0xC3,0x40,0x5A,0x11,0x09,0x90,0x04,0xC8,0x1C,
++    0x14,0x01,0x90,0x4D,0x37,0x9A,0xB8,0xFF,0xE8,0xC7,0xC2,0x24,0x15,0x09,0xC8,0x48,
++    0xE8,0x48,0x90,0x04,0x00,0x48,0x12,0x01,0x1F,0x09,0xB8,0xFF,0xE8,0x77,0x02,0xF7,
++    0x08,0xA1,0x00,0x91,0xBC,0xFF,0xEF,0xF7,0x40,0x09,0x88,0xC6,0x18,0xAA,0x13,0x09,
++    0x20,0x40,0x63,0x08,0x90,0x04,0x30,0x9A,0xC7,0x14,0xB8,0xFF,0xE8,0xF7,0x01,0x77,
++    0x08,0xB1,0x00,0x91,0xBC,0xFF,0xEF,0x77,0x40,0x09,0x88,0x46,0xC0,0x24,0x10,0x09,
++    0xC8,0x48,0xED,0x48,0x00,0x48,0x32,0x9A,0x97,0x04,0xB8,0xFF,0xE9,0x77,0xE1,0x03,
++    0x08,0xF9,0x06,0x42,0xA1,0x03,0x41,0xC3,0x42,0x00,0x02,0x00,0x00,0xC3,0x41,0x32,
++    0x0A,0x01,0x0F,0x0B,0x0C,0x01,0x00,0x0B,0x44,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,
++    0x28,0xCF,0x00,0x00,0xF8,0x00,0x06,0x42,0x80,0x01,0x06,0x42,0x00,0xC0,0x05,0x01,
++    0x00,0x70,0x00,0x01,0x58,0x20,0x00,0x01,0x10,0x00,0x00,0x42,0x00,0xC0,0x06,0x01,
++    0x00,0x00,0x00,0x42,0x18,0xC0,0x07,0x01,0x08,0x40,0x01,0x01,0x52,0xCA,0x42,0x83,
++    0x02,0x83,0x42,0xCA,0xF7,0x0B,0x48,0xF9,0x90,0x16,0xF0,0x0B,0xE0,0x48,0xB2,0x0B,
++    0xF0,0x03,0x40,0xC1,0x90,0x0E,0x00,0x01,0x03,0x83,0x3C,0x82,0x4C,0x9A,0x4A,0x53,
++    0x58,0x8A,0xE2,0xC3,0x1C,0x12,0x0C,0x53,0x10,0x43,0x02,0x09,0xB3,0xC3,0x38,0x82,
++    0xAA,0x85,0x40,0x72,0x84,0x01,0x42,0x0B,0x10,0x01,0x1C,0x8A,0x02,0x0B,0x54,0x62,
++    0x4A,0x4A,0x42,0x62,0x85,0x27,0xC0,0xAF,0xEF,0x85,0xA8,0xC5,0x46,0x32,0x82,0x01,
++    0xE2,0x0B,0x78,0x4A,0x30,0x48,0xAC,0x46,0xE2,0x0B,0x10,0x01,0x18,0x8A,0xA0,0x0B,
++    0x44,0xC3,0x0B,0x01,0x1B,0x42,0x04,0xC3,0xE8,0xC5,0x17,0x01,0x0D,0xD3,0x45,0xCB,
++    0x6E,0xEA,0x01,0x79,0x01,0x0A,0x30,0x72,0x59,0x02,0xB2,0x01,0x61,0x44,0x57,0x63,
++    0x48,0x09,0x80,0xDE,0x48,0x29,0x80,0x46,0x4B,0x41,0x88,0x46,0x8F,0x93,0x43,0xCB,
++    0x38,0x48,0x8E,0x16,0x05,0x81,0x00,0xC3,0xED,0xC5,0x0F,0xD3,0x10,0xC2,0x8C,0x16,
++    0x07,0x29,0x05,0xC3,0x01,0x3F,0xE0,0x0A,0x02,0xCB,0xE7,0x00,0x97,0x05,0x24,0x44,
++    0x40,0x89,0x9A,0x06,0x20,0x5C,0x07,0xA1,0x07,0xC3,0xED,0xC5,0xC8,0x8B,0x4B,0x11,
++    0x91,0xE6,0x61,0x7A,0x48,0x01,0x88,0x2E,0x43,0xC3,0x07,0x04,0x41,0x6A,0x11,0x43,
++    0x21,0x54,0x07,0xF7,0x43,0xC3,0x47,0x0C,0x10,0x48,0xC0,0x40,0x96,0x25,0x04,0x89,
++    0x11,0x00,0xD0,0x00,0x40,0x01,0xC1,0x76,0x97,0x05,0xBF,0xFF,0xF1,0x1F,0x44,0x32,
++    0x11,0x22,0x8C,0x76,0x00,0x09,0x80,0x07,0xC8,0xD7,0x03,0xC1,0xB1,0x43,0x49,0x02,
++    0x00,0x09,0x80,0x43,0x00,0x2F,0x41,0xC2,0x86,0x01,0xED,0x03,0x08,0x69,0x18,0x48,
++    0x40,0x01,0x88,0x36,0xD2,0x00,0x43,0x81,0xC7,0x0E,0x20,0x44,0x07,0xCF,0x20,0x5C,
++    0x00,0xBF,0x40,0xD2,0xC1,0x00,0x41,0x19,0xC7,0x1E,0x20,0x44,0x41,0xC2,0x10,0x43,
++    0x03,0x7F,0xD0,0x00,0x40,0xB1,0xC1,0x66,0x20,0x44,0x07,0x57,0x10,0xC2,0x84,0x46,
++    0x41,0xCB,0xA7,0x0A,0x62,0x44,0xE7,0x00,0x97,0x05,0x24,0x44,0x40,0x89,0x9A,0x06,
++    0x23,0x5C,0xCF,0x83,0xE3,0x00,0x8A,0x83,0x05,0x81,0x00,0xC3,0xED,0xC5,0x07,0xD3,
++    0xE8,0xC5,0x07,0x00,0x10,0x00,0x00,0x42,0x00,0xC0,0x00,0x01,0xF8,0x00,0x06,0x42,
++    0x58,0xC0,0x02,0x01,0x00,0xA0,0x07,0x01,0x80,0x01,0x06,0x42,0xF8,0xFF,0x07,0x00,
++    0x00,0x80,0x00,0x01,0x58,0x20,0x00,0x01,0x88,0x76,0x00,0x00,0x77,0x81,0xF8,0xFF,
++    0xF8,0x02,0x07,0x00,0xA8,0x85,0x80,0x07,0xC8,0x77,0x65,0x32,0xE8,0x03,0x47,0x01,
++    0x80,0x26,0x40,0x31,0x8F,0xD6,0xBF,0xFF,0xDF,0x3F,0x38,0xBF,0xBB,0xFF,0xD7,0x5F,
++    0x38,0xA7,0x07,0x00,0x00,0xC0,0x05,0x01,0xAE,0xC5,0x6F,0xDA,0x03,0x41,0x83,0x43,
++    0x01,0x09,0x80,0x43,0x0F,0x01,0x81,0x4B,0x15,0x19,0x80,0x53,0x13,0x41,0x89,0x53,
++    0x17,0x69,0x89,0x53,0x15,0x69,0x88,0x53,0x11,0x92,0x32,0x7A,0xBD,0x01,0x15,0xD4,
++    0x17,0xA1,0x1D,0x54,0x32,0x62,0xA1,0x01,0x8D,0x03,0x8B,0x03,0x07,0x41,0x88,0x03,
++    0x11,0x51,0x90,0x13,0x13,0xA1,0x90,0x13,0x90,0x0B,0x0F,0x81,0x9B,0x0B,0x99,0x03,
++    0x0F,0x01,0x98,0x4B,0x0D,0x71,0x90,0x4B,0x17,0x31,0x90,0x53,0x98,0x4B,0x0B,0x31,
++    0x98,0x4B,0x09,0x01,0x99,0x4B,0xA5,0x43,0x03,0x81,0xA1,0x43,0x03,0x51,0x80,0x03,
++    0x05,0xB1,0x87,0x03,0x07,0x51,0x80,0x03,0x01,0xB1,0x8F,0x03,0x05,0x29,0x94,0x03,
++    0x01,0x51,0x28,0x44,0x03,0xF9,0x87,0x49,0x34,0x32,0xB1,0x01,0x00,0x84,0x01,0xC9,
++    0x0B,0x00,0x02,0x84,0x04,0x79,0x10,0x00,0x05,0x83,0x43,0xC2,0x00,0x83,0x05,0x01,
++    0x99,0x83,0x31,0x02,0x0C,0x51,0x80,0x91,0x87,0x27,0xD0,0x87,0x05,0xB1,0xB7,0xC3,
++    0x07,0xA1,0xB0,0xC3,0x07,0x01,0xA8,0xC3,0x09,0x01,0x30,0x02,0x80,0x01,0xA2,0x0B,
++    0xA0,0x0B,0x0E,0xC1,0xA8,0x0B,0x08,0x51,0xAE,0x0B,0x0A,0x41,0x1F,0x0C,0x0E,0xF9,
++    0x89,0x21,0x00,0xCC,0x0E,0x99,0x18,0x4A,0xA8,0x0B,0x14,0xA1,0xA8,0x13,0xB6,0x0B,
++    0x0A,0xA1,0xB0,0x0B,0x0A,0x51,0x88,0x0B,0x14,0xF1,0x88,0x13,0x0E,0x21,0x8B,0x0B,
++    0x0A,0x59,0x0D,0x0C,0x08,0xE1,0x90,0x0B,0x08,0xC9,0x99,0x0B,0x0A,0x31,0x98,0x0B,
++    0x08,0xF9,0x8F,0x09,0x08,0x0C,0x0E,0x51,0xB8,0x4B,0x0B,0x01,0x32,0x4C,0xA3,0x0B,
++    0x0D,0x21,0xB0,0x8B,0x0B,0x31,0xB0,0x8B,0x09,0x19,0x0D,0x4C,0x0C,0xA1,0xB0,0x0B,
++    0x0E,0x51,0xB0,0x0B,0x0C,0x01,0xA0,0x0B,0x08,0x19,0xBC,0x0B,0x09,0x31,0x80,0x0B,
++    0x18,0x01,0x30,0x0A,0xCE,0x01,0x9B,0x5B,0xA2,0x5B,0x88,0x01,0xB2,0x53,0xB0,0x53,
++    0x14,0xE1,0xB1,0x53,0x16,0x41,0xB0,0x53,0x10,0x11,0xB8,0x53,0x12,0xB1,0xB8,0x53,
++    0x14,0x19,0xB8,0x53,0x48,0x52,0x04,0x0B,0x8C,0x1B,0x48,0x52,0xC6,0x01,0x34,0x0B,
++    0x88,0x91,0x38,0x0B,0x8A,0xE1,0x3E,0x0B,0x0C,0xC1,0x40,0x3A,0x84,0x27,0xD0,0x77,
++    0x40,0x2A,0x0C,0xC1,0xC0,0x81,0x81,0x27,0xD4,0x4F,0x4C,0x12,0x43,0x1A,0xCC,0x31,
++    0x00,0x0B,0xCE,0x71,0x00,0x0B,0x8C,0xA1,0x08,0x0B,0x88,0xC1,0x0A,0x0B,0xCA,0x21,
++    0x01,0x0B,0xCA,0xC1,0x05,0x0B,0x88,0xA1,0x0D,0x0B,0xCC,0xC1,0x10,0x0B,0xFA,0x48,
++    0x10,0x0B,0xF8,0x48,0x0F,0x0B,0xEE,0xC5,0xA8,0x85,0x09,0x01,0x63,0x92,0x43,0x92,
++    0xA2,0xE1,0xFE,0x1B,0x01,0x77,0x00,0x21,0x18,0x42,0xCA,0x28,0x00,0x29,0x12,0x79,
++    0x09,0x00,0xC2,0x40,0x90,0x13,0x10,0x01,0x94,0x13,0x92,0x13,0x10,0x14,0x1E,0x14,
++    0xE6,0x48,0x92,0x4D,0x17,0x5A,0xC4,0x76,0x07,0x01,0x10,0xF9,0x2D,0x09,0x09,0x68,
++    0x02,0x37,0x00,0x08,0xCA,0x48,0xC8,0x48,0xB2,0x53,0xB0,0x53,0xE6,0x00,0x92,0x05,
++    0x17,0x1A,0xC4,0xB6,0xE9,0x85,0xA1,0x85,0x56,0xFA,0x92,0x01,0x08,0x01,0x10,0x8C,
++    0xD4,0x01,0xB6,0x8B,0xB8,0x8B,0x30,0x9A,0x98,0x01,0xB5,0xCB,0x1C,0xCC,0xBC,0xCB,
++    0xB0,0xCB,0x22,0x09,0xB0,0xA3,0xA8,0x8B,0xDE,0x01,0xF1,0xDB,0xB0,0x9B,0x32,0x9A,
++    0x9A,0x01,0xA1,0xCB,0x9A,0x01,0xA1,0xE3,0xA4,0xCB,0xA0,0xA3,0x20,0x41,0x89,0xA3,
++    0x40,0x09,0x88,0x16,0xA1,0xCB,0xE4,0x85,0x39,0xB7,0xE5,0x85,0x3A,0x82,0x0B,0x08,
++    0x40,0x9A,0x42,0x13,0x18,0x01,0x01,0xD2,0x90,0x41,0x04,0x13,0x10,0xD0,0x1C,0x8A,
++    0x0A,0x0B,0x42,0x0B,0x40,0x0B,0x10,0x41,0x18,0x8A,0x04,0x0B,0x0C,0x01,0x00,0x0B,
++    0x38,0x82,0xAB,0x85,0x40,0x5A,0x42,0x0B,0x30,0x48,0xA8,0x2E,0x08,0x81,0x06,0x0B,
++    0x08,0x81,0x02,0x0B,0x08,0x81,0x00,0x0B,0x4E,0x32,0x8A,0x01,0x40,0x53,0x3C,0x90,
++    0x7C,0x90,0x00,0x53,0x41,0x53,0x1C,0x81,0x1C,0xD2,0x00,0x53,0x5E,0x12,0x12,0x09,
++    0x01,0xD3,0x12,0x91,0x02,0x13,0x46,0x0A,0x40,0x23,0x14,0x61,0x1C,0xA2,0x00,0x23,
++    0x40,0x23,0x1A,0xA2,0x02,0x23,0x4A,0x23,0x1A,0xA2,0x08,0x23,0x48,0x23,0x18,0xA2,
++    0x0E,0x23,0x40,0x23,0x1E,0xA2,0x00,0x23,0x42,0x43,0x12,0x01,0x1A,0x82,0x00,0x43,
++    0x00,0xD1,0x04,0xC3,0x02,0x01,0x0F,0xC3,0xE9,0x85,0x40,0xA2,0x40,0x13,0x08,0x09,
++    0x18,0x52,0x00,0x13,0x4C,0x13,0x18,0x52,0x0A,0x13,0x48,0x13,0x1A,0x52,0x0C,0x13,
++    0x40,0x13,0x1E,0x52,0x03,0x13,0x3E,0x82,0x40,0x6A,0x59,0x0B,0x10,0x21,0x18,0x8A,
++    0x18,0x0B,0x58,0x0B,0x10,0x01,0x1A,0x8A,0x18,0x0B,0x58,0x13,0x08,0x01,0x1C,0x52,
++    0x19,0x13,0x40,0x22,0x16,0x01,0x80,0x01,0x02,0x13,0x40,0x13,0x1A,0x52,0x00,0x13,
++    0x48,0xFA,0x40,0x43,0x10,0x01,0x19,0x82,0x03,0x43,0x38,0x82,0xA8,0x85,0x08,0x09,
++    0x00,0x31,0x80,0x07,0xD0,0x3F,0x0D,0x11,0x00,0x21,0x80,0x07,0xD0,0x1F,0x05,0x09,
++    0x85,0x07,0xD0,0xFF,0x00,0x31,0x80,0x07,0xD0,0xE7,0x05,0x21,0x85,0x07,0xD0,0xCF,
++    0x86,0x07,0xD0,0x77,0xE8,0x85,0xA8,0x85,0x40,0x82,0x48,0x5A,0xC0,0xA1,0x12,0x43,
++    0xBA,0xFF,0xF7,0xD7,0x07,0x09,0xB8,0xFF,0xF8,0x77,0x02,0xA1,0xBB,0xFF,0xFF,0x7F,
++    0xBB,0xFF,0xFF,0xFF,0xBE,0xFF,0xFF,0x07,0xBD,0xFF,0xFF,0x7F,0xBE,0xFF,0xFF,0xB7,
++    0x48,0x62,0x00,0x01,0x80,0x43,0xE8,0x85,0x00,0xC0,0x00,0x01,0xC8,0x21,0x01,0x00,
++    0xF8,0xFF,0x07,0x04,0xD8,0x02,0x06,0x00,0x40,0x60,0x07,0x01,0x58,0xC0,0x02,0x01,
++    0x10,0x00,0x00,0x42,0x00,0x00,0x00,0x42,0x80,0x01,0x06,0x42,0xF8,0x00,0x06,0x42,
++    0x18,0x00,0x02,0x42,0x00,0x80,0x00,0x01,0xA8,0x85,0x80,0x07,0xD0,0xEF,0xEA,0x85,
++    0xAF,0x85,0xB8,0xFF,0xF0,0xBF,0xE8,0x85,0xA8,0x7D,0x80,0x04,0x88,0x0C,0xC0,0x0C,
++    0x80,0x14,0xC0,0x04,0x83,0x1C,0x30,0x42,0x40,0x7E,0x80,0x25,0xE8,0x05,0x00,0x00,
++    0xAC,0xFD,0x87,0x1D,0x30,0x32,0x00,0x01,0x82,0x14,0x00,0x9F,0x44,0xFA,0x0F,0x01,
++    0x0C,0x0B,0x26,0x01,0xC2,0x14,0x00,0x28,0x7F,0xE2,0x4F,0xC3,0x1F,0x02,0x09,0xC3,
++    0xD0,0x6C,0x90,0x04,0x14,0x09,0x08,0x01,0x30,0x82,0xD9,0x64,0x86,0x1F,0xD8,0x37,
++    0xF8,0x82,0x33,0x0A,0xCF,0x99,0x49,0xC9,0x99,0x3E,0x40,0x91,0xE7,0x16,0x48,0xC3,
++    0x1F,0x02,0x0D,0xC3,0x40,0x20,0x63,0x01,0x88,0x36,0xD7,0x6C,0x90,0x04,0x10,0x09,
++    0x09,0x01,0x34,0x82,0xD8,0x64,0x80,0x1F,0xDB,0x8F,0xFD,0xA2,0xD0,0x6C,0x90,0x04,
++    0x14,0x09,0x08,0x01,0x30,0x82,0xD9,0x64,0x85,0x1F,0xD8,0x47,0xF8,0xBA,0xD3,0x6C,
++    0x90,0x04,0x10,0x09,0x09,0x01,0x34,0x82,0xD8,0x64,0x80,0x1F,0xDD,0xFF,0x14,0x3A,
++    0xE9,0x16,0x30,0x02,0x30,0xE2,0x31,0x3A,0xFD,0x82,0x13,0xC2,0xE3,0x0E,0x98,0xBA,
++    0x05,0x17,0x10,0x02,0xDB,0x06,0x98,0xA2,0x46,0xE2,0x4E,0x03,0xDE,0x8A,0x0B,0x00,
++    0xC0,0x00,0xCA,0x24,0x00,0x44,0xC0,0x24,0xE0,0x00,0x84,0x24,0xC2,0x14,0xE0,0x00,
++    0x90,0x05,0x86,0x14,0xC8,0x2C,0xC0,0x14,0x15,0x42,0x9C,0x3E,0x87,0x3D,0xE8,0x85,
++    0xAC,0xFD,0x87,0x7D,0x30,0xA2,0x30,0xEA,0xD8,0x0B,0x8B,0x6C,0xD0,0x0B,0x8F,0x64,
++    0x40,0x01,0x80,0x6E,0x48,0x72,0x06,0x99,0x07,0x43,0x12,0xF9,0x58,0x5A,0x96,0x81,
++    0x10,0xD3,0x06,0x43,0x00,0xC1,0x83,0x1F,0xF8,0x77,0xFF,0x84,0xB8,0xA1,0x01,0xD7,
++    0x40,0x3A,0x0E,0x19,0x04,0x0B,0x0A,0x19,0x06,0x0B,0x08,0x09,0xC4,0x84,0x00,0x48,
++    0xC0,0x38,0x12,0x01,0x30,0x5A,0x31,0x8A,0x00,0x09,0x80,0x17,0xD0,0xE7,0x31,0x01,
++    0x30,0x1A,0x11,0x09,0x08,0x01,0x44,0x1D,0xA8,0x04,0x80,0x1F,0xDB,0x7F,0xE2,0xB0,
++    0x91,0xB5,0x77,0x91,0x9D,0xA6,0x47,0xD2,0x40,0x0B,0x10,0x11,0x18,0x8A,0x00,0x0B,
++    0x00,0xE1,0xEC,0x02,0x33,0x00,0xA8,0xE6,0x40,0xB2,0x0D,0x01,0x81,0x0B,0x30,0x12,
++    0x30,0x4A,0x01,0x11,0x84,0x17,0xC8,0x27,0x30,0x1A,0xA9,0x04,0x08,0x01,0x00,0x11,
++    0xD0,0x84,0x80,0x17,0xD0,0x77,0x33,0x01,0xC2,0x64,0x00,0x00,0x80,0x74,0x00,0xBF,
++    0x31,0x5A,0x31,0x92,0x08,0x01,0x00,0x09,0x80,0x17,0xD0,0x6F,0xA8,0x0C,0xA0,0x04,
++    0x30,0xCA,0x41,0x1D,0xD8,0x84,0xD0,0x64,0xBA,0xFF,0xFF,0x17,0xC6,0x74,0xC8,0x38,
++    0x09,0x09,0x30,0x5A,0x30,0x92,0x31,0x42,0x87,0x17,0xC8,0xEF,0xE7,0xB0,0x93,0xB5,
++    0xC4,0x6C,0x10,0x32,0x99,0x26,0x37,0x1A,0xA8,0x04,0x08,0x01,0x00,0x19,0xD0,0x84,
++    0x82,0x17,0xD0,0x3F,0x31,0x12,0x31,0x4A,0x00,0x01,0x80,0x17,0xCD,0x8F,0xDA,0x03,
++    0x41,0x01,0x80,0xF6,0x40,0xBA,0x0C,0x09,0x81,0x0B,0x30,0x12,0x30,0x4A,0x01,0x11,
++    0x82,0x17,0xC8,0x37,0x30,0x5A,0x09,0x01,0x00,0x09,0xD0,0x6C,0x86,0x17,0xC8,0xDF,
++    0x30,0x1A,0xA9,0x04,0x00,0x11,0xD0,0x84,0xC8,0x6C,0x80,0x17,0xD0,0x57,0xA9,0x0C,
++    0xA5,0x04,0xD8,0x13,0x30,0xCA,0x41,0x1D,0xDF,0x84,0xB8,0xFF,0xFD,0x4F,0xD8,0x03,
++    0x06,0x00,0xCA,0x30,0x30,0x1A,0xA9,0x04,0x00,0x19,0xD0,0x84,0xC8,0x6C,0x80,0x17,
++    0xD0,0xC7,0x08,0x09,0x30,0x5A,0x31,0x42,0xD0,0x6C,0x80,0x17,0xC9,0xE7,0x35,0x12,
++    0x30,0x4A,0x01,0x01,0x80,0x17,0xC8,0xE7,0x40,0xF2,0x0B,0x01,0x85,0x0B,0xD8,0x03,
++    0x00,0x27,0x00,0x37,0x05,0x8C,0xE1,0xB0,0xE6,0x00,0x92,0x05,0xD4,0x64,0x10,0x82,
++    0x9B,0xC6,0x57,0xBA,0x40,0x83,0x08,0x11,0x18,0x42,0x04,0x83,0x87,0x9D,0xE8,0x85,
++    0xAC,0xFD,0x87,0x1D,0x30,0x7A,0x50,0x01,0x80,0x16,0x00,0x01,0x80,0x0C,0x00,0x0F,
++    0x00,0x09,0x80,0x0C,0x2A,0x01,0x00,0x47,0xCD,0x64,0x00,0x40,0xC1,0x30,0x32,0x52,
++    0x08,0x19,0xD8,0x6C,0xC0,0x0C,0x80,0x17,0xC9,0x77,0x04,0x41,0x81,0x1F,0xF8,0x5F,
++    0x20,0x09,0xC0,0x34,0x80,0x01,0x84,0x14,0x60,0x81,0x99,0x36,0x0B,0xF9,0x47,0x1A,
++    0x88,0x11,0x18,0x0B,0x42,0x08,0x1B,0x0B,0x03,0x0F,0x40,0x02,0x1F,0x23,0x02,0xF9,
++    0x4F,0xF2,0x82,0x89,0x88,0x01,0x12,0x43,0x00,0x11,0x80,0x1F,0xF8,0xA7,0xC0,0x14,
++    0xE0,0x03,0x44,0x01,0x80,0x3E,0x00,0x51,0x80,0x1F,0xF8,0x6F,0x40,0x83,0x41,0x03,
++    0x30,0x00,0xA8,0x86,0x07,0x5F,0x00,0xF9,0x4C,0xA2,0x82,0x89,0x88,0x01,0x12,0x43,
++    0x00,0x09,0x80,0x1F,0xF9,0x07,0x40,0x83,0x40,0x03,0x30,0x00,0xA3,0x1E,0xE0,0x20,
++    0x93,0x25,0x67,0xF9,0xC9,0x86,0x06,0xE4,0xE1,0xF8,0x35,0x52,0x08,0x09,0xD8,0x6C,
++    0xC0,0x0C,0x80,0x17,0xCB,0x87,0xE2,0x68,0x90,0x6D,0xC7,0x1C,0x15,0x2A,0x9C,0x9E,
++    0x37,0x27,0xAF,0x85,0x80,0x4D,0x34,0x6A,0x34,0xA2,0x00,0x91,0xEF,0x02,0x0A,0xF9,
++    0x88,0x09,0x40,0x01,0x80,0x0E,0x30,0x7A,0x00,0x0F,0x38,0x19,0x17,0xF8,0xD1,0x43,
++    0x85,0x44,0xD0,0x53,0x90,0x3C,0x98,0x24,0xC2,0x44,0x00,0x00,0xC0,0x00,0x86,0x2C,
++    0xD2,0x3C,0x00,0x90,0xC0,0x00,0x84,0x1C,0x45,0xC2,0x11,0x81,0x00,0x13,0x1A,0x0B,
++    0x30,0x01,0x00,0x67,0x4D,0x03,0x01,0x88,0xC0,0x00,0x42,0x03,0x01,0x3B,0x30,0x1A,
++    0x30,0x92,0x09,0x09,0x00,0x01,0x80,0x17,0xCB,0xF7,0xE0,0xB0,0x90,0xB5,0xC7,0x44,
++    0x17,0x32,0x9C,0x7E,0x30,0x01,0x00,0x67,0x4D,0x03,0x03,0x88,0xC0,0x00,0x42,0x03,
++    0x00,0x3B,0x08,0x09,0x31,0x1A,0x31,0x92,0x30,0x42,0x80,0x17,0xCB,0x67,0xE0,0xB0,
++    0x90,0xB5,0xC7,0x3C,0x17,0x32,0x9C,0x7E,0xD8,0x43,0x45,0x01,0x81,0x16,0x41,0x1A,
++    0x44,0x0B,0x96,0x4D,0x89,0x14,0x48,0x4C,0x01,0x0B,0x4E,0x12,0x00,0x09,0x80,0x43,
++    0xD8,0x43,0x85,0x34,0x30,0x01,0x00,0x67,0x55,0x03,0x01,0x88,0xC0,0x00,0x42,0x03,
++    0x01,0x3B,0x30,0x1A,0x30,0x92,0x09,0x09,0x00,0x01,0x80,0x17,0xC3,0x67,0xE7,0xB0,
++    0x90,0xB5,0xC7,0x34,0x17,0x32,0x9C,0x7E,0x48,0xB2,0x00,0x01,0x80,0x43,0x40,0x9A,
++    0xCE,0x14,0x00,0x0B,0x48,0x0B,0x89,0x04,0x30,0x5A,0x11,0x09,0xA0,0x0C,0xC8,0x24,
++    0xC7,0x44,0xB8,0xFF,0xFB,0xAF,0x49,0x0B,0x89,0x04,0x30,0x5A,0x10,0x01,0xA0,0x0C,
++    0xC8,0x2C,0xC0,0x3C,0xB9,0xFF,0xFF,0x67,0xD8,0x43,0x45,0x01,0x80,0xDE,0x70,0x3A,
++    0x44,0x83,0x97,0x3D,0x4F,0x44,0x01,0x83,0x40,0x32,0x08,0x09,0x85,0x0B,0xD8,0x43,
++    0x51,0x0B,0x31,0x5A,0x10,0x09,0xA0,0x0C,0x88,0x04,0x00,0x2F,0x00,0x01,0x00,0x42,
++    0x18,0x00,0x04,0x42,0x00,0xB0,0x00,0x01,0xCF,0x1C,0xB8,0xFF,0xF8,0x8F,0x40,0xDA,
++    0x08,0x01,0x80,0x0B,0x00,0xBB,0x4F,0xD2,0x00,0x01,0x10,0x43,0x4A,0xC2,0xC8,0x01,
++    0x18,0x43,0x80,0x4D,0xEF,0x85,0xAF,0xC5,0x30,0x1A,0x30,0x42,0x34,0xBA,0xD0,0x23,
++    0xD0,0x2B,0x4E,0xA2,0xC0,0xC8,0x8A,0x04,0x30,0xD2,0x31,0xCA,0x80,0x17,0xE8,0xE7,
++    0x30,0x01,0x00,0x3F,0x09,0x09,0x30,0xDA,0x30,0x92,0x31,0x42,0x84,0x17,0xC0,0x9F,
++    0xE7,0xB0,0x93,0xB5,0x17,0x32,0x9D,0xAE,0xC8,0x04,0x10,0x01,0x18,0x01,0x00,0x4F,
++    0x00,0x01,0x00,0x1F,0x82,0x5B,0xE0,0x48,0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0xCE,
++    0xE6,0x90,0x92,0x95,0x17,0x12,0x9D,0x9E,0xE8,0xC5,0x07,0x00,0x00,0xB0,0x00,0x01,
++    0x00,0x01,0x02,0x42,0x30,0x20,0x06,0x00,0x49,0x32,0x41,0x2A,0x05,0x43,0x9E,0xFF,
++    0x7F,0x04,0x3A,0xF7,0x94,0x15,0x3A,0x00,0x77,0x18,0x06,0xF9,0x04,0xC2,0x3C,0x48,
++    0x74,0x48,0x00,0xCA,0x50,0x01,0xD0,0x5E,0x38,0x90,0x78,0x90,0xD4,0x41,0x40,0x98,
++    0x54,0xE2,0x00,0xD8,0xC6,0xD0,0x4C,0x9B,0x18,0x1A,0x1C,0x5A,0x0B,0x9B,0x3E,0x82,
++    0x40,0x98,0x54,0xCA,0x04,0xD8,0xC4,0xD0,0x44,0x9B,0x18,0x1A,0x18,0x5A,0x00,0x9B,
++    0x3A,0x82,0x93,0x05,0x36,0x10,0x76,0x90,0x0C,0x09,0x00,0x8A,0x48,0x00,0x52,0x9A,
++    0x04,0x00,0xC4,0x00,0x03,0x0B,0x38,0x82,0x96,0x05,0x32,0x10,0x70,0x90,0x0E,0x09,
++    0x00,0x8A,0x54,0x72,0x4C,0x00,0x02,0x00,0x94,0x01,0xC4,0x00,0x03,0x0B,0x38,0x82,
++    0xB3,0x15,0x3B,0x82,0xFB,0x85,0x39,0x82,0x40,0x32,0x48,0x0B,0x10,0x21,0x18,0x8A,
++    0x0B,0x0B,0x38,0x82,0x48,0x1A,0x48,0x43,0x14,0x21,0x18,0x82,0x0B,0x43,0x38,0x82,
++    0x07,0x20,0x28,0xD0,0x68,0x07,0x00,0x07,0x20,0x07,0x00,0x07,0x08,0x07,0x00,0x07,
++    0xAC,0xFD,0x87,0x4D,0xD0,0x94,0x30,0x22,0xF0,0x43,0x84,0x0C,0xF8,0x6B,0xC2,0x64,
++    0x08,0x01,0x80,0x0B,0x00,0x01,0x00,0x8F,0x0A,0x21,0x19,0x0A,0x18,0x29,0xCA,0x48,
++    0x0E,0xD8,0xC2,0x48,0xD0,0x4B,0x48,0x79,0x80,0x36,0x80,0x83,0xE0,0x90,0xCA,0x64,
++    0xD8,0x64,0xC0,0x4B,0xE0,0x48,0x82,0xCB,0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0x5E,
++    0xC0,0x64,0xC0,0x03,0x80,0x44,0x40,0x01,0x88,0x0E,0x80,0x6D,0xE8,0x85,0xC7,0x44,
++    0x40,0x09,0x88,0x1E,0xC0,0x0C,0x40,0x09,0x8F,0x06,0x38,0xB7,0x00,0x01,0x80,0x34,
++    0x80,0x2C,0xC8,0x44,0xC4,0x0C,0x10,0x0A,0x88,0x8E,0x02,0x01,0x30,0x01,0x08,0x01,
++    0x88,0x1C,0x88,0x14,0x1A,0x19,0x0A,0xD8,0x00,0x4F,0x10,0x31,0x18,0x52,0xCA,0x90,
++    0xC4,0x90,0x4E,0xBC,0xC6,0xC0,0x49,0x94,0xCA,0xB0,0xE4,0x48,0x90,0x4D,0xD6,0x0C,
++    0x17,0x8A,0x9C,0x96,0xC8,0x0C,0x80,0x1F,0xF0,0xFF,0x83,0x24,0x30,0x82,0xC9,0x0C,
++    0x83,0x1F,0xF0,0xD7,0x30,0x32,0x08,0x01,0x00,0x01,0x00,0xFF,0x1A,0x29,0x0A,0xD8,
++    0x02,0x0F,0xE0,0x48,0x91,0x4D,0x16,0x21,0x18,0x52,0xCA,0x90,0xC0,0x90,0xD6,0x93,
++    0x57,0x79,0x80,0xB6,0x12,0x21,0x19,0x52,0x18,0x19,0xC9,0x90,0x0E,0xD8,0xC4,0x90,
++    0x1E,0x01,0xF0,0x9A,0xFE,0x1C,0xC8,0xD8,0x98,0x1C,0x18,0x11,0xF0,0x9A,0xD6,0x14,
++    0xC0,0xD0,0x94,0x14,0xE6,0x48,0x92,0x4D,0xE6,0x00,0x92,0x05,0xD4,0x44,0x10,0x12,
++    0xC0,0xE6,0xCE,0x44,0xC0,0x1C,0x80,0x1F,0xF0,0x7F,0x32,0x3A,0xC8,0x44,0xC0,0x14,
++    0x82,0x1F,0xF0,0x57,0xCE,0x24,0xD8,0x48,0x89,0x34,0xD0,0x80,0x80,0x2C,0x08,0x01,
++    0x10,0x01,0x00,0x77,0x00,0x01,0x30,0x5A,0x18,0x5A,0xF3,0x5C,0x04,0xD8,0xCA,0xD8,
++    0x02,0x1F,0x00,0x30,0x9A,0xD2,0xE4,0x00,0x95,0x05,0x16,0x42,0x9A,0xCE,0xE7,0x48,
++    0x95,0x4D,0x16,0x4A,0x98,0x76,0x0F,0x01,0x11,0x01,0x00,0xF7,0x1A,0x29,0x0A,0xD8,
++    0x02,0x0F,0xE0,0x48,0x91,0x4D,0x06,0x21,0x18,0x42,0xCA,0x00,0x86,0x3C,0xC0,0x00,
++    0xD0,0x03,0x40,0x79,0x80,0xAE,0x07,0x01,0x01,0x47,0x19,0x19,0xF4,0x3C,0x08,0xD8,
++    0xC0,0x98,0x37,0x01,0x34,0xE2,0xFC,0xF2,0xDA,0x34,0x38,0x19,0xC0,0x98,0x37,0x31,
++    0x19,0x32,0xCA,0xB0,0x0F,0xF8,0xCB,0xB0,0x35,0xB2,0x4D,0xB4,0xD8,0xD8,0xAC,0x06,
++    0x14,0xDA,0x92,0xDD,0x30,0x32,0x3B,0x11,0xF8,0xBA,0xF7,0x2C,0xCB,0xF0,0x35,0xBA,
++    0x4F,0xFC,0xDF,0xB0,0xAB,0x06,0x10,0xB2,0xC8,0xD8,0x34,0xB2,0x18,0x72,0xFB,0x5C,
++    0x07,0xB0,0xCB,0xB0,0x07,0x38,0x9A,0x9A,0xE6,0x00,0x92,0x05,0xDC,0x0C,0x10,0xC2,
++    0x9A,0x9E,0xE6,0x48,0x92,0x4D,0xE6,0x90,0x90,0x95,0xC6,0x64,0xC4,0x03,0x10,0x82,
++    0xC0,0xE6,0xC5,0x64,0xC8,0x0C,0xC0,0x03,0x10,0x42,0xCC,0x06,0x38,0xEF,0xC1,0x0C,
++    0x3F,0xDF,0xA9,0x85,0x80,0x4D,0x34,0x22,0x04,0x71,0xD4,0x1A,0x01,0xC1,0xF0,0x02,
++    0x28,0x71,0x80,0x44,0xF8,0x2A,0xAB,0x3C,0xD8,0x00,0x92,0x05,0x2B,0xD1,0xF8,0x2A,
++    0x30,0x81,0xA8,0x34,0xF8,0x32,0xB5,0x2C,0xD9,0x68,0x95,0x6D,0xC0,0x33,0x77,0x09,
++    0x8D,0x16,0x10,0x04,0x10,0x2C,0x07,0x7F,0x55,0x3C,0x05,0xF0,0x31,0xE2,0xC5,0xB0,
++    0x54,0x04,0x07,0x38,0xCB,0xE8,0x33,0x3A,0xD9,0xB0,0x97,0xB5,0xD0,0x40,0x91,0x2D,
++    0x85,0x80,0x85,0x68,0x17,0x04,0x15,0x2C,0xF1,0x3C,0xC0,0x80,0x04,0x30,0xCA,0x00,
++    0xF4,0x44,0xC8,0x00,0x80,0x00,0x94,0x05,0xF3,0x2C,0xC8,0xA8,0x05,0x70,0xCB,0x68,
++    0xF5,0x34,0xC8,0x68,0x81,0x68,0x95,0x75,0x90,0x01,0x46,0x01,0xD0,0x0E,0x00,0x01,
++    0x00,0x27,0x40,0xAC,0x10,0x2A,0xD4,0x0E,0x00,0x01,0xF0,0x82,0x70,0x01,0xD0,0x0E,
++    0x30,0x01,0x00,0x27,0x45,0xAC,0x12,0xAA,0xD0,0x0E,0x30,0x11,0xF8,0xB2,0x4C,0x41,
++    0x80,0x0E,0x48,0x49,0x88,0xBE,0xD0,0x3C,0xD0,0x90,0xA8,0x06,0x14,0x92,0x92,0xAD,
++    0xD4,0x2C,0xD8,0x90,0xAA,0x06,0x10,0x92,0xCC,0x90,0x92,0xAD,0x10,0xEA,0xCC,0x06,
++    0x30,0xEA,0x48,0x49,0x8B,0x16,0x20,0x48,0x60,0x68,0x00,0x37,0x4D,0xC8,0x10,0x4A,
++    0xC8,0x1E,0x30,0x6A,0x00,0x0F,0x30,0xEA,0x00,0x6A,0xD6,0x3C,0xD8,0xC8,0x8A,0x24,
++    0x1C,0x8A,0x02,0x50,0xC4,0x48,0x34,0x62,0xC8,0x24,0x10,0x51,0x05,0x78,0xF2,0x12,
++    0xCA,0x48,0x1E,0x52,0x20,0x12,0x8B,0x1C,0x43,0xC8,0x1A,0x42,0xC6,0x00,0x02,0x00,
++    0xC0,0x00,0x8C,0x14,0x00,0xC8,0x8E,0x0C,0x82,0x1F,0xE8,0xA7,0x30,0x3A,0xC0,0x2C,
++    0xCA,0x24,0x18,0x0A,0x00,0x40,0xC4,0x40,0x15,0x61,0xF0,0x12,0xCA,0x1C,0x18,0x52,
++    0xC0,0x80,0xC8,0x14,0x1B,0x72,0xC3,0x88,0x00,0x48,0xC6,0x40,0xC8,0x0C,0x80,0x1F,
++    0xE8,0x0F,0xCA,0x3C,0x08,0x0C,0xCB,0x2C,0x08,0x0C,0xCD,0x44,0xD0,0xC8,0xAB,0x06,
++    0x10,0x4A,0x92,0x55,0xCA,0x34,0xD0,0x08,0xAA,0x06,0x10,0x4A,0x90,0x4D,0x50,0x19,
++    0xD8,0x46,0xD0,0x44,0x10,0xD2,0xCD,0x0E,0xE0,0xF8,0x03,0x1F,0xD5,0x44,0x10,0xD2,
++    0x93,0x06,0xF0,0xF8,0x48,0x19,0xD8,0x46,0xCC,0x34,0x10,0x0A,0xCA,0x0E,0xE0,0x00,
++    0x00,0x1F,0xC8,0x34,0x10,0x0A,0x94,0x06,0xF7,0x00,0x0A,0x3C,0x10,0x04,0x81,0x4D,
++    0xEF,0x85,0xAF,0xF5,0x30,0xB2,0xD0,0x44,0x60,0xCA,0xCF,0xE0,0x2F,0x31,0x78,0xC2,
++    0x1F,0xAA,0xC3,0x68,0xFF,0xE1,0xC9,0x68,0x07,0xB0,0xC3,0x98,0x72,0xA2,0xF7,0x81,
++    0xCA,0xF0,0xFC,0x9B,0x36,0xBA,0xB8,0x01,0x32,0xE2,0xFD,0x01,0xBA,0x0C,0xF8,0x01,
++    0xB8,0x04,0x40,0x09,0x88,0x36,0x01,0x01,0x01,0xFF,0xC0,0x0B,0x48,0x79,0x88,0xCE,
++    0x47,0x4C,0x09,0x0C,0x41,0x7C,0x13,0x3C,0xC1,0x93,0x89,0x13,0xC3,0x93,0x8B,0x13,
++    0x1F,0x0C,0x1D,0x3C,0x23,0x0C,0x21,0x3C,0x0D,0x0C,0x0B,0x3C,0x41,0x4C,0x19,0x0C,
++    0x43,0x4C,0x1B,0x0C,0x80,0x03,0x09,0x09,0x85,0x0B,0x8F,0x0B,0x30,0x0A,0xDB,0x4B,
++    0x90,0x0B,0x01,0x27,0xA2,0x21,0xE1,0x00,0x94,0x05,0x16,0xC2,0x9C,0xEE,0x16,0xC2,
++    0x92,0x9E,0x03,0x87,0x02,0x21,0x19,0x0A,0xC8,0x60,0x08,0x41,0x41,0x44,0x19,0x04,
++    0x01,0x11,0xF0,0x42,0x1D,0x04,0xCB,0x1B,0x58,0x09,0x88,0xA6,0x18,0xC1,0x38,0xE1,
++    0xF7,0x1A,0xFF,0x3A,0xD8,0xD8,0xAE,0x06,0x14,0xDA,0x92,0xFD,0x1F,0xF1,0xF0,0x1A,
++    0xD0,0x00,0xAE,0x06,0x14,0x02,0x92,0x05,0xD9,0x0C,0xC0,0xC0,0xDC,0xDB,0x10,0xC2,
++    0xC8,0x0E,0x00,0x01,0x88,0x03,0x05,0xC1,0x19,0x01,0xF1,0x02,0xF6,0x1A,0xD7,0x00,
++    0xAA,0x06,0x10,0x02,0x90,0x3D,0x04,0xD1,0x19,0x11,0xF1,0x02,0xF6,0x1A,0xD7,0x00,
++    0xAA,0x06,0x10,0x02,0xCC,0x00,0x96,0x05,0xD4,0x1B,0x11,0x1A,0xC8,0x2E,0xD8,0x04,
++    0xC6,0x03,0xDF,0xDB,0xE4,0xD8,0x12,0xC2,0xC0,0x86,0xD8,0x04,0xC6,0x03,0xDF,0xDB,
++    0xE4,0xD8,0x12,0xC2,0xCB,0x1E,0x30,0x02,0xD8,0x03,0x48,0x00,0x91,0x03,0x59,0x04,
++    0x23,0x04,0x59,0x04,0x21,0x04,0x33,0x02,0xBD,0xFF,0xF7,0x9F,0xC3,0x03,0x47,0xF9,
++    0x92,0x0E,0xE0,0x00,0x85,0x03,0x47,0x44,0x10,0x04,0x03,0x19,0x80,0x03,0xC3,0x0C,
++    0xDC,0x03,0x82,0x01,0x89,0x03,0xCF,0x03,0xC2,0x8B,0xD1,0x00,0xE0,0x00,0x42,0x11,
++    0xC3,0x2E,0xC8,0x03,0xC2,0x8B,0xD3,0x00,0xE0,0x00,0x42,0x11,0xCF,0x4E,0xC0,0x03,
++    0x40,0x11,0x98,0x36,0xCC,0x04,0xD8,0x4B,0x10,0x42,0xC4,0x16,0x07,0x01,0x80,0x03,
++    0x89,0x03,0xC7,0x83,0x8B,0x03,0xC1,0x83,0x8F,0x03,0xEB,0xF5,0xAF,0x85,0x47,0xF9,
++    0x88,0x0E,0x00,0x01,0xE9,0x85,0x27,0x21,0x1C,0x02,0x63,0xEA,0xC0,0x00,0xCC,0x00,
++    0x23,0x31,0x18,0x0A,0xC4,0x48,0x54,0xD2,0xD4,0xE1,0xC1,0x50,0x0A,0xA1,0xF0,0x0A,
++    0x48,0x01,0xD0,0x06,0x10,0x4A,0x22,0xB1,0xF8,0x22,0x60,0x01,0xD3,0x06,0x10,0x22,
++    0xCC,0x48,0x60,0xA2,0x10,0x0A,0x9D,0x06,0x08,0x01,0x28,0x71,0x42,0xA4,0xF8,0x2A,
++    0xD8,0x20,0xAB,0x06,0x10,0x22,0x2B,0x81,0x42,0x94,0xFA,0x2A,0xD8,0x90,0xAA,0x06,
++    0x15,0x92,0xC2,0x28,0x34,0xE2,0xA0,0x01,0x4C,0x14,0x33,0xA2,0x10,0x52,0xC5,0xF6,
++    0xC8,0x13,0x54,0x09,0x8B,0x26,0xD8,0x3B,0xCB,0x33,0xF6,0xF8,0x10,0xF2,0xDD,0xA6,
++    0x50,0x09,0x88,0x3E,0xD4,0x23,0x11,0x62,0x9E,0x26,0xC0,0x03,0x40,0xF1,0xC0,0x0E,
++    0x40,0x29,0x90,0x56,0x50,0x09,0x88,0x16,0x51,0xC4,0x46,0x81,0x98,0x2E,0x50,0x09,
++    0x8B,0x2E,0x30,0x02,0x05,0x00,0x12,0x42,0xC0,0x0E,0x00,0x01,0xE8,0x85,0x07,0x09,
++    0xEF,0x85,0xAF,0xFD,0x84,0x65,0x34,0xB2,0x08,0x01,0x28,0x01,0x00,0x01,0x80,0x1C,
++    0xC2,0xAC,0xF8,0x23,0x04,0x01,0x30,0x22,0x80,0x3C,0x00,0x27,0xD7,0x6C,0x00,0xF9,
++    0xA2,0x82,0xE2,0x48,0x95,0x4D,0x16,0x0A,0x98,0xC6,0xD7,0x7C,0x28,0x92,0xC3,0x26,
++    0xC0,0x7C,0x80,0x2C,0x30,0x82,0x83,0x24,0x03,0x1F,0x30,0x82,0x80,0x2C,0xC0,0x7C,
++    0x80,0x24,0x00,0x01,0x82,0x34,0x00,0xD7,0x1A,0x01,0x00,0xB7,0x36,0x02,0x03,0xC2,
++    0x3A,0x00,0x8E,0x86,0x40,0x1A,0x83,0x44,0x00,0x01,0xD0,0xAC,0xF4,0x64,0xF0,0x93,
++    0x90,0x5C,0x30,0xD2,0x1A,0x12,0x03,0xB8,0xC8,0xD0,0x95,0x54,0x00,0x6F,0xF0,0x3C,
++    0x07,0x32,0x3E,0x90,0x88,0x3E,0xF0,0x54,0x07,0x38,0xDA,0xB2,0xFD,0x44,0x10,0xF2,
++    0x90,0x0E,0xB0,0x44,0x32,0x0A,0xE0,0x00,0x90,0x05,0xD6,0x5C,0x17,0x12,0xC4,0x76,
++    0x70,0xA2,0x02,0x01,0x00,0x78,0xBA,0x4C,0x03,0x87,0x30,0x3A,0x07,0x3A,0x3E,0xF8,
++    0x88,0x56,0x30,0x3A,0x18,0x3A,0xD3,0x64,0x05,0xF8,0xC3,0xF8,0xD5,0x4C,0xD0,0xFA,
++    0x10,0xBA,0xC5,0x0E,0x30,0xF2,0x31,0x2A,0xE6,0x00,0x92,0x05,0x2F,0x82,0x9B,0x66,
++    0x10,0xEA,0x8C,0xA6,0xC4,0x1C,0xC8,0x00,0x80,0x1C,0xC0,0x34,0xE6,0x00,0x92,0x05,
++    0x80,0x34,0xC0,0x6C,0xA0,0x2A,0x32,0x09,0x30,0x82,0xD1,0x3C,0x00,0x42,0x1C,0x82,
++    0x90,0x05,0x84,0x3C,0x03,0x72,0x35,0x02,0x1D,0x32,0x90,0x85,0x30,0x22,0xD4,0x2C,
++    0xC4,0x34,0x10,0x82,0x82,0x1E,0xE0,0xD8,0x93,0xDD,0x2E,0x9A,0x98,0x36,0xD5,0x2C,
++    0xC4,0x34,0x10,0x82,0x98,0x06,0xC5,0x1C,0x80,0x44,0x10,0x01,0x00,0x01,0x08,0x01,
++    0x30,0x5A,0x83,0xCB,0x18,0x01,0x08,0x01,0x33,0x62,0x34,0x4A,0xE0,0x4A,0x00,0x0F,
++    0xE6,0x48,0x92,0x4D,0x36,0xEA,0x00,0x6A,0x3F,0x68,0x8F,0xCE,0xED,0x24,0x10,0x4A,
++    0x98,0xD6,0x40,0x01,0x8F,0x8E,0x08,0xF9,0x00,0x5F,0xD0,0x6C,0xE3,0x9A,0x28,0x9A,
++    0x90,0x1E,0xD0,0xAC,0xF4,0x93,0x14,0x12,0xC0,0x0E,0xD0,0x6C,0xA2,0x8A,0xE0,0x00,
++    0x95,0x05,0x16,0x02,0x98,0x8E,0x87,0x85,0xEA,0x85,0xF7,0x00,0x93,0x05,0x36,0x4A,
++    0xE0,0x4A,0x28,0x09,0x31,0x62,0x05,0x47,0x33,0x6A,0x18,0x2A,0xFB,0x64,0x00,0x70,
++    0xCA,0xB0,0x07,0x38,0xDD,0xAA,0xC7,0x50,0x2C,0x09,0x00,0x6A,0x1D,0xEA,0x90,0x5D,
++    0x31,0x72,0xA3,0x8A,0xED,0x44,0x10,0x52,0x98,0x16,0x28,0x11,0x30,0x62,0x05,0xA7,
++    0xFA,0x7C,0xE0,0x28,0x10,0xEA,0x9D,0x6E,0x90,0x44,0x08,0x01,0x00,0x27,0xF8,0x6C,
++    0xE3,0xAA,0xA3,0xEA,0xE6,0x48,0x92,0x4D,0x17,0x0A,0x9D,0xC6,0xE0,0x8A,0x29,0x09,
++    0x30,0x62,0x05,0x17,0x90,0x45,0x2F,0x01,0xA3,0xAA,0x31,0x2A,0x6D,0x01,0x80,0x56,
++    0x33,0x6A,0x18,0x2A,0xFB,0x64,0x00,0x70,0xCA,0xB0,0x07,0x38,0xDA,0xAA,0xDF,0x90,
++    0x2C,0x09,0x00,0x6A,0x1B,0x5A,0x35,0x6A,0xE2,0x4A,0xE1,0x48,0xA4,0x4A,0x39,0xD7,
++    0x40,0x40,0x05,0x00,0xF8,0xFF,0x07,0x00,0xAC,0x85,0x87,0x2D,0x33,0x72,0xF8,0x8B,
++    0x8C,0x14,0x50,0xCA,0xC0,0x20,0xA4,0x24,0xC9,0x14,0x18,0x21,0x31,0xBA,0x31,0xAA,
++    0x1A,0xCA,0xBA,0x01,0xA8,0x01,0xC6,0x40,0xC0,0x00,0x84,0x1C,0x01,0x67,0xC2,0x03,
++    0x42,0x79,0x80,0x46,0xC8,0x03,0x37,0x08,0xA0,0xA6,0x41,0x21,0x88,0x16,0x01,0x71,
++    0xF0,0x02,0x81,0x0C,0x01,0x81,0xF0,0x02,0x81,0x04,0x30,0x92,0x09,0x49,0x30,0x02,
++    0xB8,0xFF,0xEF,0xFF,0x0B,0x71,0xF0,0x0A,0xC0,0x0C,0xD0,0x40,0xAA,0x06,0x10,0x02,
++    0x90,0x0D,0x00,0x81,0xF0,0x02,0xD1,0x04,0xD0,0x00,0xAC,0x06,0x12,0x02,0xC2,0x00,
++    0x91,0x05,0xD8,0x4B,0x44,0x48,0x14,0x0A,0xE8,0x5E,0xC0,0x0C,0x08,0x04,0xC7,0x04,
++    0x10,0x04,0x01,0x37,0x40,0x21,0x90,0x26,0xF8,0x83,0x41,0x11,0x91,0x0E,0x00,0x01,
++    0x87,0x03,0x05,0xF9,0x8B,0x03,0x89,0x03,0xC7,0x03,0xDF,0xCB,0x10,0x42,0xC4,0x0E,
++    0x07,0x01,0x88,0x03,0xCA,0x03,0x37,0x00,0x77,0x00,0x8A,0x03,0x40,0x01,0x80,0x0E,
++    0xF7,0x00,0x8A,0x03,0xC8,0x03,0x47,0x01,0x8B,0x2E,0xC0,0x03,0x44,0x00,0x04,0x00,
++    0x80,0x03,0x03,0x01,0x81,0x03,0xA5,0x21,0xC5,0x1C,0x10,0x02,0xC0,0x7E,0x0D,0x01,
++    0x11,0x01,0xB8,0x93,0xC0,0x24,0x00,0x87,0xC0,0x1B,0xE0,0x14,0x10,0x1A,0x95,0x56,
++    0xC7,0x1B,0xDE,0xE3,0x32,0xD8,0x72,0xD8,0x10,0x1A,0xCD,0x26,0xC1,0x1B,0x5C,0x01,
++    0x80,0x0E,0x08,0x09,0x04,0x27,0x80,0x13,0x80,0x21,0xD9,0x1C,0x17,0x1A,0xC4,0x5E,
++    0x49,0x01,0x80,0x5E,0xC1,0x24,0x00,0x37,0x80,0x13,0xC4,0x0B,0xDC,0x14,0x10,0xCA,
++    0x96,0x06,0xC1,0x0B,0xDA,0xDB,0x37,0x48,0x74,0x48,0x12,0xCA,0xC8,0xD6,0x08,0x09,
++    0x81,0x0B,0xFC,0x8B,0xE1,0x48,0xBA,0x8B,0x0A,0x71,0xF0,0x0A,0x48,0x01,0xD0,0x0E,
++    0x08,0x14,0x06,0x27,0x44,0x5C,0x11,0xCA,0xE9,0x0E,0x40,0x4C,0x08,0x0C,0x0E,0x81,
++    0xF0,0x0A,0x4A,0x01,0xD0,0x0E,0x10,0x14,0x03,0x27,0x40,0x5C,0x10,0xCA,0xEC,0x0E,
++    0x40,0x4C,0x13,0x0C,0x80,0x21,0xC9,0x1C,0x16,0x0A,0xC4,0xAE,0x87,0x2D,0xE8,0x85,
++    0xAC,0x85,0x87,0x3D,0x30,0x2A,0x30,0x62,0x41,0x1A,0xC2,0x40,0x08,0xB9,0xED,0x4A,
++    0x4B,0x29,0x80,0xE6,0x0C,0x09,0x06,0x48,0xC2,0x70,0x4B,0x02,0xC0,0x48,0x8B,0x1C,
++    0x0E,0x19,0x03,0x48,0xC0,0x48,0x8B,0x14,0x0F,0x01,0x10,0xF9,0x18,0x79,0x00,0x3F,
++    0xA6,0x92,0xCB,0x3B,0x78,0x01,0x88,0x06,0x82,0x1B,0xE0,0x48,0x91,0x4D,0x86,0x21,
++    0xFC,0x3B,0x13,0x7A,0xC0,0xA6,0x07,0x01,0x85,0x34,0xF0,0x03,0x42,0x01,0x80,0xCE,
++    0xB1,0x04,0x30,0x0A,0x30,0x42,0x59,0x2D,0xD7,0x14,0xB8,0xFF,0xD8,0x0F,0x84,0x34,
++    0xC0,0x34,0x40,0x01,0x88,0x76,0x30,0x01,0x01,0x47,0x30,0x5A,0x37,0x92,0x09,0xF9,
++    0x00,0x09,0xA0,0x04,0xB8,0xFF,0xEF,0xEF,0xE7,0xB0,0x93,0xB5,0xF5,0x03,0x15,0x82,
++    0xC1,0x9E,0x07,0xFF,0xC0,0x34,0x40,0x09,0x89,0x96,0xC0,0xB3,0x31,0x1A,0x31,0x52,
++    0x09,0x01,0x30,0x82,0xBE,0xFF,0xEF,0x17,0x40,0x01,0x80,0x0E,0x00,0x01,0x00,0x07,
++    0x01,0x09,0x30,0x5A,0x11,0x01,0x30,0x8A,0xA7,0x04,0xB8,0xFF,0xE9,0x17,0x00,0x4F,
++    0xA5,0x04,0xF0,0x3B,0x30,0x5A,0xEB,0xD3,0x30,0xDA,0xC9,0x1C,0xC7,0x14,0xB8,0xFF,
++    0xF0,0x07,0x38,0x01,0x00,0xDF,0xC0,0x1C,0xEF,0x02,0x46,0xF9,0x81,0x16,0xE0,0x82,
++    0x80,0x24,0x00,0x0F,0x00,0xF9,0x87,0x24,0x31,0x1A,0x31,0x52,0x30,0xCA,0xC1,0x24,
++    0xBC,0xFF,0xEF,0xE7,0x40,0x01,0x80,0x0E,0x00,0x01,0x00,0x07,0x01,0x09,0x30,0x5A,
++    0x30,0xD2,0xA1,0x04,0xCF,0x24,0xB8,0xFF,0xE3,0xE7,0xE6,0xF8,0x95,0xFD,0xF7,0x03,
++    0x17,0xC2,0xC5,0x06,0x31,0x0A,0x31,0x42,0xD7,0x34,0xB8,0xFF,0xF0,0x6F,0x86,0x3D,
++    0xE8,0x85,0x07,0x01,0x38,0x82,0x03,0x00,0x40,0x40,0x05,0x00,0x18,0x70,0x00,0x00,
++    0xAE,0xFD,0x87,0x5D,0xC2,0xAC,0xDA,0x03,0x82,0xD4,0xC1,0xAC,0xD9,0x03,0x80,0xCC,
++    0x01,0x09,0x58,0x45,0x89,0xC3,0xC0,0xCC,0xE2,0x00,0x8A,0xC3,0xC4,0xCC,0x89,0xC3,
++    0xC2,0xCC,0xF1,0x00,0x8A,0xC3,0xC6,0xAC,0x82,0x01,0x86,0x54,0xE0,0x0B,0x00,0x21,
++    0x1A,0x0A,0xC0,0x54,0xA2,0x0B,0xC0,0xAC,0xCA,0x03,0x42,0x00,0x80,0xDC,0x09,0x01,
++    0x40,0xBD,0x31,0x52,0x00,0x36,0x00,0x01,0x82,0xFC,0xC0,0xAC,0xCD,0xB4,0x82,0x01,
++    0x82,0x4C,0xC2,0xAC,0x82,0x01,0x84,0x44,0xC0,0x74,0x4A,0x11,0x92,0x05,0x82,0x3C,
++    0xC2,0x6C,0x92,0x05,0x83,0x34,0x82,0xBE,0x10,0x01,0x00,0x01,0x4C,0x4D,0xB1,0x4A,
++    0x8F,0x2C,0x4A,0xF2,0xB2,0x4A,0x8C,0x24,0x48,0xE2,0xEF,0x48,0xB2,0x4A,0x8C,0x1C,
++    0x04,0x08,0xC4,0x48,0x91,0x4D,0x66,0xA5,0xDB,0x74,0xA2,0x1A,0x62,0x8D,0xD9,0x6C,
++    0xA2,0x1A,0xDB,0x24,0x9A,0x3C,0xD9,0x1C,0x9A,0x34,0xD9,0x2C,0x98,0x2C,0x41,0x09,
++    0x89,0x5E,0xD8,0x3C,0x12,0xDA,0x92,0xDD,0x99,0x3C,0xD9,0x34,0x12,0xDA,0x92,0xDD,
++    0x99,0x34,0xD9,0x2C,0x12,0xDA,0x92,0xDD,0x9A,0x2C,0xD9,0x5C,0x32,0xE2,0xDC,0x64,
++    0x9A,0x64,0xD9,0x34,0xE1,0x3C,0xEA,0x34,0xCA,0xD8,0x92,0xDD,0xEB,0x3C,0xC9,0x20,
++    0x91,0x25,0xF3,0x2C,0xED,0x64,0xC9,0x68,0xA8,0x64,0x59,0x01,0xD9,0x86,0xEB,0xD4,
++    0x13,0x5A,0xD5,0x6E,0x63,0x01,0xD8,0x5E,0xED,0xCC,0x11,0x62,0xD1,0x46,0xEB,0x64,
++    0xC5,0x6B,0x49,0x68,0x8B,0x06,0x32,0x2A,0x3F,0x01,0xF8,0x7A,0xEB,0x2C,0x01,0x68,
++    0x23,0x62,0x35,0x32,0x2B,0x01,0xF8,0xAA,0xF5,0xDC,0x11,0xAA,0xEA,0xC6,0xF2,0xB4,
++    0x71,0x09,0x88,0x16,0xD9,0xF0,0x93,0xB5,0xB2,0x9C,0xF8,0x5C,0x35,0x01,0xF8,0xF2,
++    0x10,0x72,0xDD,0x06,0x35,0xAA,0x81,0x68,0x01,0x68,0x33,0x7A,0xF3,0x9C,0x10,0x6A,
++    0x12,0xAA,0xE5,0x2E,0x6B,0xA5,0xA1,0x62,0x6B,0x8D,0xA1,0x5A,0x01,0xA8,0x72,0xBD,
++    0xC9,0x68,0xE5,0x72,0xE1,0xB0,0xA3,0x72,0xEB,0xFC,0xE0,0x68,0x90,0x6D,0xAF,0xFC,
++    0xF5,0x9C,0x10,0xBA,0xD1,0xBE,0x05,0x9F,0x09,0xEF,0x6A,0xA5,0xA1,0x62,0x6B,0x8D,
++    0xA2,0x5A,0x03,0xB0,0x6B,0xBD,0xC9,0xA8,0xE3,0x72,0xE1,0xB0,0xA0,0x72,0xE9,0xFC,
++    0xE7,0x68,0x93,0x6D,0xAD,0xFC,0x38,0x37,0xE9,0x64,0xC1,0x6B,0x48,0x68,0x6D,0x19,
++    0x8A,0x6E,0x00,0xB0,0x7F,0xBD,0xC9,0xB0,0xE0,0xB2,0x71,0x09,0xC2,0x3E,0xC0,0x64,
++    0x08,0x01,0xC6,0x03,0x1A,0x42,0xC8,0x64,0x82,0x43,0x80,0x7D,0xE8,0x85,0x6F,0x11,
++    0x89,0x56,0x68,0xA5,0xA1,0x62,0x63,0x8D,0xA2,0x1A,0x03,0x98,0x4A,0xBD,0xC1,0xC8,
++    0xE2,0x5A,0xE0,0xD8,0xA0,0x5A,0x00,0x1F,0xCA,0x4C,0xF2,0x4B,0x4F,0x51,0x90,0x66,
++    0xE6,0x00,0x92,0x05,0x40,0x11,0x90,0x06,0x3A,0xD7,0xE2,0x90,0x90,0x95,0x56,0x21,
++    0x92,0x06,0x38,0x57,0x01,0x01,0x80,0x6C,0xC0,0xB4,0x42,0x09,0x88,0xF6,0x03,0x01,
++    0x80,0x84,0x01,0x01,0x81,0x7C,0xC9,0x84,0x42,0xBD,0x01,0x48,0xC2,0x40,0x80,0x14,
++    0xC1,0x7C,0xC9,0x84,0x02,0x00,0xC4,0x00,0x91,0x05,0x86,0x54,0xCA,0x7C,0xC1,0x14,
++    0xE0,0x2A,0x6A,0x09,0xC1,0x26,0xC0,0x6C,0xE6,0x00,0x92,0x05,0x87,0x6C,0x01,0x8F,
++    0xC0,0x7C,0x41,0x09,0x89,0x16,0xC0,0x84,0x47,0x01,0x88,0xC6,0x08,0x81,0x41,0x45,
++    0x86,0x1F,0xC0,0x77,0xC0,0x6C,0x82,0x3C,0xC0,0x74,0x82,0x34,0xC0,0x5C,0x82,0x0C,
++    0xC0,0x64,0x82,0x04,0xC4,0x84,0xE1,0x00,0x3C,0x00,0x7C,0x00,0x50,0x5A,0xB4,0xA2,
++    0xE8,0x98,0xB0,0xCA,0x31,0x62,0x74,0x4D,0xB1,0x8A,0xC1,0x84,0xB0,0x82,0x80,0x24,
++    0xC0,0x84,0xB1,0xC2,0x81,0x1C,0xD0,0x84,0xB0,0x82,0x85,0x14,0xC0,0x7C,0x41,0x09,
++    0x88,0x5E,0xC0,0x24,0x12,0x02,0x92,0x05,0x80,0x24,0xC0,0x1C,0x12,0x02,0x92,0x05,
++    0x80,0x1C,0xC0,0x14,0x12,0x02,0x92,0x05,0x80,0x14,0x00,0x01,0x83,0x2C,0xE0,0x68,
++    0xAD,0xF4,0x01,0x9F,0x40,0x61,0x98,0x66,0xC8,0x24,0xC0,0x34,0xD2,0x54,0xD1,0x00,
++    0x4C,0xA5,0xA1,0x42,0xC8,0x1C,0xC0,0x3C,0xD2,0x54,0xD1,0x00,0x4C,0x8D,0xA1,0x42,
++    0x00,0x47,0x15,0x01,0xDC,0x0C,0x00,0x28,0xF0,0xD2,0x5C,0x45,0x88,0xD2,0x12,0x01,
++    0x90,0x74,0xD1,0x3C,0x92,0x95,0x92,0x0C,0xD2,0x34,0x90,0x95,0x91,0x04,0xD2,0x74,
++    0x50,0x09,0x88,0x3E,0x12,0x12,0x93,0xA5,0x32,0x12,0x13,0x92,0x94,0x95,0x32,0xA2,
++    0x12,0x4A,0x92,0x4D,0xD2,0x0C,0xDA,0x04,0xF0,0x0C,0x00,0x07,0x01,0xEF,0xB4,0x24,
++    0xF1,0x04,0xB0,0x64,0x01,0x70,0xB2,0xFC,0x22,0x12,0x93,0x95,0xCA,0xD8,0x90,0xDD,
++    0xF9,0x24,0xF1,0xFC,0xC9,0xB0,0xB7,0x24,0xF3,0x64,0xC1,0xB0,0xB0,0x64,0x51,0x01,
++    0xD9,0xBE,0xF0,0xD4,0x10,0x92,0xD5,0xA6,0x58,0x01,0xD8,0x96,0xF5,0xCC,0x11,0x9A,
++    0xD1,0x7E,0xF8,0x24,0x35,0x01,0xF8,0xF2,0xF9,0x64,0xC1,0xFB,0x48,0xF8,0x8D,0x46,
++    0xFD,0xDC,0x11,0xF2,0xE8,0x2E,0x78,0x45,0xCD,0xFA,0xCB,0xF0,0x7B,0x45,0x88,0xF2,
++    0x39,0xD7,0xD6,0x74,0xE6,0x90,0x92,0x95,0x91,0x74,0xD1,0x74,0x55,0x11,0x98,0xF6,
++    0x41,0x01,0x80,0xF6,0xF2,0x10,0xF2,0x44,0x00,0x90,0x5C,0x45,0xC7,0xD2,0xCC,0xB3,
++    0xCC,0xDA,0xCA,0xB0,0x11,0xF2,0x94,0x86,0xD0,0x2C,0x50,0x09,0x88,0x8E,0xD1,0x24,
++    0xC1,0x34,0xD8,0x54,0xD1,0x00,0x54,0xA5,0xA0,0x82,0xDE,0x1C,0xD1,0x3C,0xE8,0x54,
++    0xD1,0x90,0x5E,0x8D,0xA8,0xD2,0xEA,0x14,0xDA,0x04,0xD8,0xE8,0x36,0x1A,0xD3,0x90,
++    0x90,0x95,0xDA,0x00,0x93,0x1D,0xD2,0x40,0x2C,0x01,0x30,0x01,0x50,0x01,0xD8,0x56,
++    0xFD,0xD4,0x11,0xD2,0xD0,0x3E,0x58,0x01,0xD9,0x2E,0xF8,0xCC,0x10,0xDA,0xD5,0x16,
++    0xC1,0x3B,0x18,0xBA,0x83,0x3B,0x20,0x12,0x90,0x95,0xCA,0xD8,0x92,0xDD,0xC2,0x00,
++    0xE7,0x68,0x93,0x6D,0x6F,0x11,0xC8,0x4E,0x04,0xE7,0x10,0x9A,0x90,0x0E,0x10,0x09,
++    0x90,0x2C,0xD8,0x24,0xD6,0x34,0xC0,0x90,0x90,0x95,0x96,0x34,0xD8,0x1C,0xD0,0x3C,
++    0xC6,0x90,0x96,0x95,0x90,0x3C,0xD0,0x14,0xDA,0x0C,0x00,0x90,0xC0,0x90,0x96,0x0C,
++    0xD8,0x14,0xD0,0x04,0xC0,0x90,0x96,0x04,0xE6,0x00,0x92,0x05,0xD4,0xF4,0x11,0x82,
++    0x92,0x06,0x38,0x3F,0xC2,0x7C,0xE1,0x00,0x91,0x05,0x86,0x7C,0xC0,0x7C,0x41,0x11,
++    0x97,0x06,0x30,0xAF,0xC2,0x84,0xE1,0x00,0x91,0x05,0x86,0x84,0xC0,0x84,0x41,0x21,
++    0x97,0x06,0x30,0x37,0x00,0x0F,0x00,0x41,0x81,0x6C,0xC1,0x6C,0x41,0x41,0x88,0xD6,
++    0x10,0x01,0x00,0x01,0x58,0x8A,0xE8,0xC8,0xB4,0xF2,0xB4,0x7A,0x31,0x8A,0x31,0xDA,
++    0x40,0x09,0x88,0x1E,0x12,0x4A,0x92,0x4D,0x12,0xDA,0x92,0xDD,0xE7,0x6C,0xC2,0x18,
++    0x92,0xDD,0xE2,0x74,0xC2,0x08,0x93,0x65,0x04,0x08,0xC4,0x48,0x90,0x4D,0x5E,0x01,
++    0xD9,0x76,0xE8,0xD4,0x10,0x5A,0xD5,0x5E,0x60,0x01,0xD8,0x4E,0xED,0xCC,0x11,0x62,
++    0xD1,0x36,0x68,0xA5,0xA1,0x62,0x63,0x8D,0xA0,0x1A,0x03,0x3F,0xE8,0x62,0x00,0x00,
++    0x62,0xA5,0xD9,0x74,0xA1,0x1A,0x63,0x8D,0xDB,0x6C,0xA2,0x1A,0xE6,0x00,0x92,0x05,
++    0x46,0x11,0x98,0x9E,0xE6,0x90,0x92,0x95,0x56,0x21,0x98,0x56,0x58,0x85,0xE1,0xC3,
++    0xB0,0xC3,0xC8,0xC3,0x98,0xC3,0x00,0x01,0x81,0x04,0x59,0x85,0xE0,0xC3,0xB0,0xC3,
++    0xC8,0xC3,0x98,0xC3,0x00,0x01,0x80,0xE4,0x80,0xEC,0x80,0xF4,0xC4,0xAC,0xCA,0x03,
++    0x80,0xDC,0x01,0x01,0x08,0x01,0x78,0xA5,0x06,0x18,0xCE,0xD0,0x32,0xA2,0x04,0x20,
++    0xC6,0x10,0x93,0x95,0x6D,0xA5,0xE1,0x72,0x33,0x2A,0xA3,0x72,0x6D,0x8D,0xE1,0x6A,
++    0x32,0x12,0xC3,0x90,0x8A,0xAB,0xE0,0x48,0x90,0x4D,0x4E,0x19,0x98,0x86,0x47,0x09,
++    0x80,0x0E,0x40,0x19,0x8F,0x66,0xE0,0xCA,0x33,0xE2,0x31,0x12,0xCB,0x93,0x30,0x2A,
++    0xC7,0x6B,0xA5,0x2A,0x34,0x1A,0xCB,0xE3,0x8C,0xE3,0x80,0xCB,0x34,0x0A,0x8B,0x53,
++    0x09,0x09,0x88,0x14,0x09,0x01,0x88,0x7C,0xD3,0x7C,0x31,0x0A,0xE1,0x4A,0xDC,0x7C,
++    0x36,0x12,0xC3,0x90,0xCA,0x9B,0xC0,0xAB,0xC9,0x93,0x92,0x1C,0xD0,0x7C,0x51,0x01,
++    0x88,0x16,0x41,0x01,0x80,0x0E,0x40,0x19,0x8D,0x5E,0x10,0x4A,0x98,0x4E,0x10,0x09,
++    0x90,0x0C,0x41,0x01,0x8A,0x16,0xF0,0x10,0x90,0x14,0x01,0xF7,0x11,0x09,0x90,0x14,
++    0x00,0xDF,0x40,0x09,0x80,0x0E,0x40,0x11,0x8D,0x5E,0x10,0x4A,0xC0,0x4E,0x10,0x09,
++    0x90,0x0C,0x41,0x09,0x8C,0x16,0xF0,0x10,0x90,0x14,0x01,0x77,0x11,0x09,0x90,0x14,
++    0x00,0x5F,0x10,0x01,0x90,0x0C,0x01,0x47,0x11,0x09,0x90,0x0C,0x40,0x11,0x90,0x16,
++    0xF1,0x90,0x94,0x14,0x00,0x0F,0x10,0x09,0x90,0x14,0x41,0x01,0x80,0x0E,0x40,0x19,
++    0x8D,0x0E,0x10,0x4A,0x90,0x2E,0x40,0x09,0x80,0x0E,0x40,0x11,0x8D,0x26,0x10,0x4A,
++    0xC0,0x16,0x10,0x09,0x94,0x5C,0x01,0x8F,0x11,0x01,0x90,0x5C,0x01,0x77,0xD4,0xCC,
++    0x32,0x3A,0x19,0xBA,0xD1,0xA4,0xF2,0xEC,0xC4,0xD0,0xCD,0x90,0x91,0x64,0xD1,0x64,
++    0xC1,0x93,0x90,0xE4,0x31,0x90,0xA2,0xD6,0xF3,0xA4,0x02,0xD0,0xC9,0x90,0xF4,0x44,
++    0x04,0xB0,0xCB,0x90,0x31,0x19,0x10,0xB0,0xC8,0xB0,0x14,0x21,0xF1,0x92,0xF5,0xDC,
++    0x10,0x92,0xD5,0x26,0xF0,0x6C,0x71,0x41,0x88,0xC6,0x50,0x01,0xD9,0xB6,0xF0,0xE4,
++    0x48,0xB0,0x87,0x06,0x80,0x90,0xF2,0xE4,0xC0,0xB0,0xB5,0xE4,0xF0,0x44,0xF9,0xF4,
++    0x1F,0xB2,0xCA,0xB0,0xB0,0xF4,0xF0,0xEC,0x1C,0x12,0xCB,0x90,0x91,0xEC,0xD0,0x04,
++    0xE4,0x90,0x92,0x95,0x91,0x04,0xD1,0xE4,0x48,0x90,0x8E,0xEE,0xD0,0x44,0xF2,0xFC,
++    0xCD,0x93,0x12,0x92,0xC1,0x2E,0xD0,0xE4,0x31,0x01,0x1E,0x92,0xF1,0x64,0x81,0x93,
++    0x01,0x47,0xD0,0xE4,0x31,0x01,0x1A,0x92,0xF1,0x64,0x81,0x93,0x01,0x17,0xD0,0x0C,
++    0x50,0x09,0x80,0x4E,0xD0,0x0C,0x51,0x09,0x8A,0x36,0xD0,0x6C,0x10,0xA2,0x84,0x1E,
++    0xD5,0x14,0xC1,0x10,0x95,0xA5,0x3A,0x57,0x10,0x4A,0x8D,0xDE,0xD4,0x1C,0x11,0x9A,
++    0x89,0xC6,0xC8,0x7C,0xE6,0x48,0x92,0x4D,0x89,0x7C,0xC9,0x7C,0x48,0x11,0x90,0x06,
++    0x3A,0x97,0xE2,0x00,0x90,0x05,0x46,0x21,0x91,0x06,0x38,0x1F,0xC2,0x4C,0xF2,0x03,
++    0x42,0x01,0x88,0x5E,0xC9,0xAC,0x8A,0x01,0xD8,0x43,0x36,0x10,0xAA,0x36,0x31,0x00,
++    0x71,0x00,0x04,0x27,0xD0,0x5C,0x51,0x01,0x8D,0x5E,0x10,0x4A,0xCA,0x16,0xF0,0x48,
++    0x90,0x4D,0x06,0x1F,0x10,0x4A,0x95,0x0E,0xE6,0x48,0x92,0x4D,0x11,0x09,0x90,0x5C,
++    0x01,0x67,0xD0,0x1C,0x10,0x9A,0xCC,0x16,0xF6,0xD8,0x92,0xDD,0x01,0x27,0xD0,0x1C,
++    0x10,0x9A,0x94,0x0E,0xE6,0xD8,0x92,0xDD,0x11,0x01,0x90,0x5C,0x91,0x55,0x92,0x44,
++    0x97,0xE5,0x72,0xFA,0xD4,0x44,0xC9,0x90,0x93,0xEC,0x39,0x47,0x02,0x01,0xD0,0xAC,
++    0x6C,0x94,0x12,0x12,0x9A,0xD6,0xC0,0xAC,0xE4,0x4B,0x68,0x04,0x10,0x42,0x9C,0x26,
++    0xC4,0x44,0xCA,0x03,0xF6,0x00,0x94,0x05,0x02,0x1F,0xC0,0x44,0xCC,0x03,0xE4,0x00,
++    0x91,0x05,0xCE,0x04,0x10,0x0A,0x9C,0x4E,0xC0,0xAC,0x0A,0x01,0xB2,0x0B,0xC4,0x54,
++    0x08,0xD9,0xE7,0x03,0x02,0x42,0xC8,0x54,0xA2,0x43,0x28,0x37,0x27,0x01,0x30,0xF9,
++    0xB0,0x09,0x60,0x01,0x8A,0x4E,0xC0,0x3C,0xC8,0xCC,0xF9,0xF4,0xD2,0x54,0x42,0x93,
++    0x97,0x9C,0x50,0x42,0xDE,0x74,0xB2,0xAA,0x02,0x47,0xC0,0x34,0xC8,0xD4,0xF9,0xEC,
++    0xD4,0x54,0x42,0x93,0x97,0x9C,0x50,0x22,0xDE,0x6C,0xB2,0xAA,0x40,0x01,0x80,0x16,
++    0xF4,0x48,0x12,0x42,0x8A,0x8E,0xD0,0x74,0x96,0x04,0x90,0x05,0x32,0x0A,0xD9,0x6C,
++    0xD7,0x5C,0xBA,0xEF,0xD1,0x77,0x37,0x8A,0x10,0x82,0xED,0x0E,0x30,0x42,0x00,0x17,
++    0x40,0x01,0xD0,0x06,0x02,0x01,0xC8,0x28,0x04,0x07,0xA8,0x01,0x10,0xC0,0xC9,0xE4,
++    0x81,0x17,0xF0,0x47,0xCA,0x9C,0xC8,0x00,0x18,0x42,0x42,0x01,0xD0,0x06,0x00,0x01,
++    0xA0,0x00,0x60,0x01,0x8A,0x7E,0xC8,0x54,0x44,0x4C,0x10,0x0A,0xD0,0x06,0x30,0x42,
++    0xC8,0xAC,0x12,0x31,0xF2,0x4B,0x1C,0x8A,0xD4,0xA4,0xC2,0x48,0x12,0x19,0x0A,0x90,
++    0xC4,0x48,0x0C,0x44,0x02,0x77,0xC8,0x54,0x44,0x4C,0x12,0x0A,0xD0,0x06,0x30,0x42,
++    0xC8,0xAC,0x12,0x31,0xF2,0x4B,0x1C,0x8A,0xD4,0xA4,0xC2,0x48,0x12,0x19,0x0A,0x90,
++    0xC6,0x48,0x0C,0x44,0xE7,0x20,0x93,0x25,0x65,0x09,0xC8,0x16,0xC0,0xAC,0x12,0x31,
++    0xD8,0x0B,0xC6,0xE4,0x02,0x42,0xCE,0xAC,0xF2,0x4B,0x1C,0x8A,0xD4,0xA4,0xC2,0x48,
++    0x12,0x19,0x0A,0x90,0xC0,0x48,0x14,0x44,0xC2,0xAC,0xCA,0x74,0xF2,0x03,0x04,0x10,
++    0xC0,0xA4,0xC2,0x90,0x04,0x09,0x09,0x00,0xC0,0x90,0xB0,0x8B,0xCA,0xAC,0xD2,0x6C,
++    0xF2,0x4B,0x04,0x58,0xCA,0xA4,0xC2,0xC8,0xC2,0x40,0xB0,0x13,0xC2,0xAC,0xCA,0xAC,
++    0xF2,0x03,0xE4,0x00,0xB6,0x43,0x24,0x07,0xAC,0xFD,0x87,0xDD,0xF4,0x24,0x31,0xB2,
++    0x33,0xFA,0xD8,0x83,0x81,0x94,0xD8,0x83,0x81,0x8C,0xC8,0x83,0x80,0x84,0x00,0x01,
++    0x85,0x6C,0x40,0x32,0x41,0x0B,0x32,0x82,0x80,0x01,0x85,0xD4,0x48,0x01,0x80,0x1E,
++    0xC2,0x84,0x40,0x00,0x80,0x74,0x00,0x67,0xC2,0xD4,0xF0,0x03,0x40,0x51,0x98,0x26,
++    0xC8,0xD4,0x00,0xD9,0xB0,0x42,0x80,0x74,0x00,0x1F,0xC8,0xD4,0x00,0xD1,0xB0,0x42,
++    0x86,0x74,0x08,0x09,0x03,0x48,0xC4,0xC8,0xC0,0xDC,0x88,0xCC,0x41,0x01,0x80,0xEE,
++    0x04,0x29,0x04,0x00,0xC1,0xD8,0x31,0xCA,0x89,0xF9,0x8F,0x29,0xE0,0xCC,0xC0,0x84,
++    0x42,0x00,0x12,0x02,0x90,0x05,0x82,0x6C,0x04,0x01,0x30,0x22,0x00,0x8F,0x00,0x01,
++    0x00,0x47,0xC0,0xEB,0xC5,0x53,0xD0,0x68,0x05,0x2C,0xE1,0x20,0xE2,0xD8,0xE2,0x48,
++    0xE6,0x00,0x92,0x05,0xED,0x8C,0x10,0x42,0x9B,0x9E,0x37,0x02,0xE6,0x00,0x92,0x05,
++    0x30,0x22,0xC4,0x94,0x2F,0x22,0x9C,0x56,0x30,0x82,0x43,0x01,0x84,0x06,0x38,0x02,
++    0x06,0xC9,0x07,0x00,0xC7,0xD8,0x01,0xF9,0x01,0x00,0xC6,0xC0,0x4B,0x02,0xC4,0xC8,
++    0x10,0x01,0x00,0x47,0x40,0x24,0x40,0x6C,0xD8,0x20,0x03,0xE4,0xE4,0xD8,0xE4,0x00,
++    0xE2,0x48,0xE4,0x90,0x90,0x95,0xE6,0x8C,0x17,0x12,0x9D,0x9E,0x41,0xA2,0xC3,0xC0,
++    0x80,0x64,0xE8,0xCC,0x00,0x01,0x80,0x9C,0x34,0x82,0x81,0x01,0x83,0xC4,0xC0,0x01,
++    0x85,0xBC,0x80,0x01,0x85,0xB4,0x08,0x8F,0x25,0x01,0x08,0x3F,0xC0,0x64,0xC0,0x03,
++    0x4B,0x00,0x8C,0xF6,0xF0,0x42,0xC9,0x84,0x13,0x42,0xDC,0xD6,0xC3,0x8C,0x30,0x5A,
++    0x01,0x00,0xD2,0x48,0x31,0x52,0xD0,0x01,0x5C,0x94,0x1E,0xD4,0x46,0x54,0x18,0xD4,
++    0x40,0x4C,0x22,0xCC,0x31,0x4A,0xC9,0x01,0x5A,0x4C,0x26,0xCC,0x44,0x4C,0x21,0xCC,
++    0x46,0x4C,0x23,0xCC,0xC8,0x08,0x32,0x52,0xD6,0x01,0x59,0x94,0x29,0xD4,0xD0,0x42,
++    0x2A,0xC4,0x42,0x44,0x28,0xC4,0x44,0x3D,0x60,0x01,0x88,0x66,0x0C,0x01,0x18,0xCC,
++    0x20,0xCC,0x2A,0xCC,0x10,0xCC,0x0C,0xF9,0x0B,0x48,0xC4,0xC8,0x4E,0x54,0x10,0xD4,
++    0x48,0x4C,0x1A,0xCC,0x00,0x87,0xC9,0x8C,0xF4,0x48,0x12,0x62,0x88,0xC6,0x10,0x01,
++    0x30,0x5A,0x23,0xD4,0x24,0xD4,0x2E,0xD4,0xD0,0x8C,0x18,0xF9,0xF2,0x90,0x04,0x90,
++    0xCC,0x90,0x0E,0xD8,0xC0,0x90,0x4E,0x94,0x34,0x5A,0x13,0xD4,0x06,0x48,0xCA,0x50,
++    0x0C,0xF9,0x08,0x48,0xC0,0x88,0x4A,0x4C,0x10,0xCC,0x0E,0x01,0x18,0xCC,0x00,0x9F,
++    0xF2,0x08,0x03,0x48,0xC8,0x50,0x0E,0xF9,0x0A,0x48,0xC4,0x90,0x4B,0x94,0x30,0x5A,
++    0x13,0xD4,0x04,0x10,0xCA,0x90,0xC6,0x90,0x4E,0x94,0x10,0xD4,0xE2,0x10,0x03,0x90,
++    0xCA,0x90,0xC6,0x88,0x48,0x4C,0x18,0xCC,0xC8,0x9C,0x48,0x01,0x8B,0x26,0x30,0x5A,
++    0x1E,0xCC,0x1C,0xCC,0x20,0xCC,0x00,0x4F,0xC8,0x94,0xD0,0x9C,0xF4,0x48,0x12,0x52,
++    0x88,0x26,0x08,0x01,0x30,0x5A,0x2B,0xCC,0x2C,0xCC,0x2A,0xCC,0x0B,0x01,0xF0,0x4A,
++    0x33,0x62,0x34,0x5A,0x14,0xE1,0xF0,0xD2,0x10,0x52,0xE4,0x16,0x14,0xF1,0xF0,0xD2,
++    0x04,0x07,0x00,0x07,0x13,0x52,0xD4,0xF6,0x14,0x01,0xF1,0xD2,0x17,0x52,0xD4,0xD6,
++    0x14,0x11,0xF1,0xD2,0x17,0x52,0xE4,0x86,0x14,0x31,0xF1,0xD2,0x17,0x52,0xD4,0x96,
++    0x14,0x41,0xF1,0xD2,0x17,0x52,0xD4,0x76,0x14,0x51,0xF1,0xD2,0x17,0x52,0xE4,0x26,
++    0x14,0x61,0xF1,0xD2,0x17,0x52,0xE4,0x06,0xCA,0xC4,0xE0,0x4B,0x4B,0x01,0x80,0xCE,
++    0x0C,0x01,0x30,0x72,0x88,0x14,0x88,0x1C,0x88,0x7C,0x10,0x01,0xC8,0xDC,0x48,0x01,
++    0x88,0x96,0x8B,0x24,0x1E,0x01,0xF0,0x1A,0xE8,0xC8,0xD2,0x36,0xC0,0xC8,0x94,0x55,
++    0xCA,0x1C,0xE0,0x48,0x90,0x4D,0x8E,0x1C,0x00,0x2F,0x58,0x51,0xE8,0x1E,0xC8,0x14,
++    0xE6,0x48,0x92,0x4D,0x8C,0x14,0xE0,0x00,0xCA,0x24,0xE0,0x48,0x90,0x4D,0x8E,0x24,
++    0xC8,0x24,0x48,0x49,0x9B,0x36,0x37,0x02,0xC0,0x00,0x94,0x05,0xD5,0xBC,0x68,0x8C,
++    0xE4,0x93,0x10,0x8A,0x98,0x0E,0xC9,0x74,0x10,0x42,0xD4,0xF6,0xC8,0x14,0x48,0x39,
++    0x98,0x8E,0xC8,0x74,0x84,0x48,0x12,0x0A,0xD8,0xBE,0xC0,0x1C,0x40,0x01,0x00,0x4F,
++    0x30,0x20,0x06,0x00,0xE0,0xD2,0x07,0x00,0xE0,0xD2,0x06,0x00,0x58,0x80,0x04,0x01,
++    0x40,0x40,0x01,0x00,0x88,0x4E,0xC0,0xD4,0xF0,0x03,0x42,0x11,0x98,0x0E,0x00,0x09,
++    0x37,0x32,0x4C,0xFA,0xC2,0x43,0xE2,0x00,0x80,0x43,0xC2,0xC4,0xE0,0x03,0x40,0x01,
++    0x83,0xFE,0x30,0x82,0x40,0x01,0x88,0xE6,0xC2,0xD4,0xF0,0x03,0x40,0x51,0x98,0xC6,
++    0x30,0x5A,0x03,0xB1,0x08,0x91,0xF1,0xC2,0xF4,0x8A,0x13,0x42,0xD8,0x5E,0x08,0xA1,
++    0xF2,0xCA,0x82,0x48,0x04,0x07,0x00,0xDF,0x10,0x42,0xDC,0x26,0x0A,0xC1,0xF0,0xCA,
++    0x84,0x48,0x12,0x42,0xD0,0x2E,0x00,0x09,0x37,0x32,0x4C,0x6A,0xC2,0x43,0xE2,0x00,
++    0x87,0x43,0x52,0x5A,0xC0,0x83,0x40,0x81,0x97,0x16,0x4A,0x52,0xA2,0x62,0xE0,0x00,
++    0x81,0x83,0x00,0xEF,0x07,0x57,0x3A,0xFF,0x30,0x1A,0x9B,0x04,0x83,0xC8,0x24,0x0A,
++    0x90,0x4D,0x88,0x0C,0x08,0x01,0x88,0x24,0xCA,0x6C,0x80,0x48,0x88,0xAC,0x18,0x01,
++    0xF0,0x1A,0xCE,0xAC,0x9C,0xA4,0x10,0x5A,0xD0,0x6E,0xD8,0xA4,0xCA,0x04,0xC0,0xC8,
++    0x90,0x4D,0x88,0x04,0xD8,0xA4,0xC8,0x6C,0x10,0x5A,0xD4,0x26,0x32,0x1A,0x83,0xC8,
++    0x20,0x0A,0x93,0x4D,0x88,0x0C,0xC8,0xA4,0xC0,0x48,0x94,0x55,0xE0,0x00,0xCC,0x24,
++    0xE6,0x48,0x92,0x4D,0x88,0x24,0xC8,0x24,0x4F,0x49,0x98,0x06,0xC4,0x0C,0x10,0x12,
++    0xD8,0x66,0xC8,0x74,0xC4,0x04,0x10,0x42,0xD8,0x46,0xC0,0xC4,0xE0,0x03,0x40,0x01,
++    0x83,0x36,0x30,0x5A,0x00,0xB1,0xF0,0xC2,0x40,0x01,0xD0,0x0E,0x04,0x09,0x30,0x32,
++    0xC2,0xD4,0xF0,0x03,0x40,0x51,0x98,0x16,0xC0,0xDC,0x40,0x01,0x80,0x46,0x00,0x09,
++    0x30,0x8A,0x4B,0x01,0x80,0x06,0x00,0x01,0x80,0x7C,0x00,0x0F,0x00,0x09,0x80,0x7C,
++    0xC0,0x7C,0x40,0x01,0x80,0xA6,0x01,0x09,0xB5,0x83,0x47,0xFA,0x40,0x03,0x42,0x01,
++    0x88,0x5E,0xC0,0xD4,0xF0,0x03,0x42,0x51,0x90,0x3E,0xC0,0xBC,0x6E,0x8C,0xDB,0x03,
++    0x32,0x00,0x72,0x00,0x84,0x51,0x10,0x0A,0xC8,0x0E,0x10,0x01,0x00,0x07,0x10,0x09,
++    0xC0,0xE4,0x40,0x01,0x80,0x06,0x10,0x11,0x91,0x14,0x30,0x1A,0xB8,0x04,0xB0,0x0C,
++    0x30,0x42,0xD1,0x9C,0xCF,0x64,0xB8,0xFF,0xC8,0x5F,0xC7,0xB4,0xE2,0x03,0x38,0x00,
++    0xAD,0x1E,0xF0,0x83,0xFC,0x8B,0x13,0x42,0x98,0x56,0xC0,0xB4,0xE2,0x03,0x38,0x00,
++    0xA7,0x26,0x00,0xF1,0xA8,0x83,0xC9,0xB4,0x04,0x01,0xA0,0x43,0x87,0xFD,0xE8,0x85,
++    0xE0,0x68,0xC5,0x64,0xE0,0x00,0x82,0x64,0xE7,0x20,0x93,0x25,0xC4,0x8C,0x10,0x22,
++    0x92,0x06,0x30,0x9F,0xC2,0x9C,0xE0,0x00,0x90,0x05,0x86,0x9C,0xC8,0x94,0xC0,0x9C,
++    0x10,0x42,0x94,0x06,0x37,0x47,0x3A,0x4F,0xAC,0x9D,0x87,0x3D,0x30,0x3A,0xC0,0x44,
++    0xD0,0x03,0x84,0x24,0xC6,0x44,0xD0,0x23,0x41,0xC2,0xC4,0xE8,0x06,0xF9,0x07,0x00,
++    0xC0,0xF0,0xC1,0x44,0x08,0xF1,0xE8,0x03,0x84,0x17,0xD8,0xA7,0x04,0x29,0x04,0x00,
++    0xC4,0xD0,0x41,0x9A,0x37,0xDA,0x99,0xF9,0xC1,0xC0,0x99,0x29,0x80,0x34,0x48,0xE9,
++    0x88,0xDE,0x08,0x01,0x00,0x5F,0x00,0x01,0x00,0x2F,0xC0,0xFB,0x82,0xBB,0xE0,0x90,
++    0xE2,0xD8,0xE2,0x00,0x95,0x05,0x16,0x02,0x9A,0xBE,0xE7,0x48,0x90,0x4D,0xC6,0x24,
++    0x17,0x0A,0x9C,0x86,0x00,0x01,0x00,0x2F,0x41,0x8C,0x01,0x4C,0xE5,0x68,0xE5,0xB0,
++    0xE6,0x00,0x92,0x05,0x17,0x02,0x9D,0xBE,0x00,0xCF,0xC3,0x44,0x82,0x01,0xF5,0x03,
++    0x43,0x51,0x98,0xA6,0xC4,0x44,0xF0,0x03,0x80,0x2C,0x40,0x01,0x80,0x7E,0x9B,0x1C,
++    0xF3,0x34,0x08,0x21,0x1B,0x01,0x00,0x21,0x30,0x32,0x04,0x01,0x30,0x22,0x84,0x14,
++    0x29,0x01,0x00,0x1F,0x00,0x01,0x80,0x0C,0x01,0x97,0xC0,0xBB,0x48,0xF8,0x85,0x66,
++    0x10,0x0A,0xCC,0x0E,0x30,0x0A,0x00,0x17,0x10,0x1A,0x94,0x06,0x30,0x1A,0xF8,0x14,
++    0xE7,0xF8,0x93,0xFD,0xB8,0x14,0x38,0x09,0xBB,0x0C,0xE0,0xB0,0xE6,0x00,0x92,0x05,
++    0x17,0x02,0x9D,0x56,0xC0,0x0C,0x40,0x01,0x85,0x36,0x28,0x72,0xCD,0x0E,0x30,0x72,
++    0x05,0x17,0x28,0x62,0x95,0x06,0x30,0x62,0xE7,0x68,0x93,0x6D,0xC4,0x24,0x10,0x2A,
++    0x98,0xC6,0xC6,0x2C,0x2B,0x51,0x18,0x42,0xED,0x14,0x10,0x42,0xC8,0xB6,0x48,0x01,
++    0x82,0x0E,0xF0,0x48,0x93,0x4D,0xF6,0x00,0x10,0x1A,0xD4,0x0E,0xE6,0xD8,0x92,0xDD,
++    0x30,0x82,0x43,0x01,0x82,0x16,0xF0,0x00,0x94,0x05,0x36,0x32,0xEB,0x24,0xF0,0x68,
++    0x28,0x62,0xD5,0x1E,0x32,0x02,0xE3,0x00,0x94,0x05,0x36,0x22,0x28,0x01,0x00,0xDF,
++    0x00,0x01,0x00,0xAF,0x10,0x42,0x9C,0x2E,0x28,0xAA,0x9B,0x1E,0x10,0xC2,0xC4,0x0E,
++    0x28,0x2A,0xCB,0x3E,0xC1,0xB3,0x08,0xB8,0xD8,0xF8,0xF5,0x1C,0xC7,0xB3,0xC9,0xB0,
++    0x48,0xB0,0x81,0xB3,0xE0,0x90,0xF2,0x1C,0xE0,0xB0,0xB3,0x1C,0xE6,0x00,0x92,0x05,
++    0x17,0x02,0x9D,0x3E,0xE7,0x68,0x93,0x6D,0xC4,0x24,0x10,0x2A,0x98,0x06,0xC7,0x34,
++    0x10,0x01,0x00,0x67,0x08,0x01,0x00,0x37,0xC4,0x1B,0x30,0xD8,0x70,0xD8,0x84,0x1B,
++    0xE2,0x00,0xE2,0x48,0x95,0x4D,0x16,0x0A,0x9A,0xB6,0xE7,0x90,0x90,0x95,0xCE,0x24,
++    0x17,0x52,0x9C,0x7E,0x87,0x4D,0xE8,0x85,0xAC,0xFD,0x87,0x1D,0x30,0x2A,0x30,0x62,
++    0x05,0x01,0xB0,0x03,0xB1,0x03,0x37,0x02,0x80,0x01,0xE6,0x0B,0x10,0xE9,0x07,0x52,
++    0x3E,0x48,0x7A,0x48,0x00,0x48,0x1A,0x52,0xA0,0x13,0xE0,0x0B,0x10,0xD9,0x07,0x8A,
++    0xA1,0x0B,0x30,0x02,0x80,0x01,0x84,0x14,0xE1,0x03,0x7A,0x4A,0x40,0x01,0x80,0x56,
++    0x01,0x01,0x50,0x42,0x08,0xF9,0xA7,0x8A,0xE6,0x00,0x92,0x05,0x47,0x81,0x98,0xD6,
++    0x01,0x01,0x80,0xC3,0x80,0xC3,0xA3,0x04,0x30,0x5A,0x01,0x01,0xD0,0x34,0xC8,0x2C,
++    0xBE,0xFF,0xE7,0xD7,0x35,0x32,0xB1,0x01,0xF0,0x83,0x43,0x51,0x98,0x36,0xA0,0x04,
++    0x30,0x5A,0x01,0x09,0xD0,0x34,0xC8,0x2C,0xBE,0xFF,0xE7,0x77,0xC2,0x14,0xE0,0x03,
++    0x43,0x01,0x80,0xF6,0x45,0xB2,0xF0,0x0B,0xC2,0x03,0x02,0x00,0x10,0x0A,0xCC,0x1E,
++    0x48,0x9A,0x00,0x01,0x81,0x43,0x02,0xDF,0x48,0x8A,0xC0,0x43,0x30,0x22,0x44,0x21,
++    0xC0,0xB6,0x01,0x01,0x00,0x8F,0x59,0x7A,0xE7,0xCA,0x48,0xF9,0x80,0x5E,0x11,0x01,
++    0xE6,0x08,0x92,0x4D,0x00,0x97,0x78,0x5A,0xE3,0xDA,0xE1,0xFA,0xDA,0xD8,0xE6,0xD8,
++    0x58,0x11,0xC0,0x4E,0x5A,0x32,0xC0,0xD3,0x50,0x01,0x80,0x0E,0xF2,0x90,0x82,0xD3,
++    0x5F,0x22,0x10,0xF9,0xA0,0xD2,0x10,0x09,0xE6,0x48,0x92,0x4D,0x28,0x0A,0x03,0x4F,
++    0x00,0xA0,0x00,0x01,0x58,0x00,0x04,0x01,0x58,0x80,0x04,0x01,0x40,0x40,0x01,0x00,
++    0x30,0x20,0x06,0x00,0x98,0xFE,0x56,0x09,0x8B,0x2E,0x50,0x42,0xC0,0x8B,0x4A,0x01,
++    0x82,0x0E,0xF0,0x48,0x82,0x8B,0xE2,0x00,0x93,0x05,0x7E,0x22,0x2E,0x02,0x9B,0x56,
++    0x08,0x01,0xC0,0x14,0xE1,0x1B,0x32,0x02,0x80,0x01,0x59,0x09,0x8A,0x2E,0x50,0xFA,
++    0xC0,0x93,0x52,0x01,0x80,0x9E,0x08,0x09,0x02,0x8F,0x50,0xE2,0xC0,0x93,0x52,0x01,
++    0x8E,0x46,0xD8,0x3B,0x6B,0x14,0x33,0xF8,0x75,0xF8,0x13,0xD2,0x9F,0x3E,0xF0,0x13,
++    0x50,0x01,0x88,0x26,0x68,0x14,0xE5,0x3B,0x10,0xD2,0x9D,0x06,0x08,0x09,0x48,0x01,
++    0x83,0x2E,0xF0,0x8B,0x48,0x01,0x95,0x3E,0xE3,0x48,0xB2,0x8B,0x03,0x27,0xF0,0x8B,
++    0x48,0x51,0x90,0x0E,0x0B,0x01,0xB0,0x8B,0xF0,0x8B,0x4B,0x51,0x9A,0x0E,0x51,0x5A,
++    0xC0,0x93,0x52,0x01,0x8D,0x8E,0xF0,0x3B,0x78,0x01,0x88,0x76,0x58,0x09,0x88,0x26,
++    0x00,0x07,0x00,0xB7,0xF3,0x48,0xB2,0x8B,0x06,0x3F,0xD8,0x03,0x6A,0x1C,0x33,0x00,
++    0x74,0x00,0x14,0x1A,0x92,0x0E,0xF0,0x48,0xB0,0x8B,0x53,0x11,0x9D,0x16,0x00,0x01,
++    0xB0,0x83,0x03,0x37,0x50,0x09,0x88,0x26,0xF2,0x83,0x43,0x81,0x93,0x0E,0x00,0x21,
++    0xB5,0x83,0xF3,0x0B,0x4B,0x09,0xC8,0x5E,0x07,0x01,0xD0,0x13,0x90,0x04,0x10,0x01,
++    0x02,0xA7,0x00,0x98,0xC9,0xF0,0x1A,0x09,0x0F,0xD8,0xC4,0x98,0xF0,0xF3,0xF2,0xDB,
++    0xFA,0x04,0x00,0xD8,0x1B,0xF2,0x03,0xB0,0xCF,0xB0,0xC3,0x98,0x31,0x19,0x10,0xB0,
++    0xCC,0xD8,0x44,0xDC,0xC4,0xC0,0x90,0x05,0xE6,0x90,0x92,0x95,0x17,0x8A,0xC4,0x46,
++    0x87,0x17,0xC8,0x47,0x40,0x00,0x82,0x0C,0xC8,0x0B,0xC1,0x0C,0x12,0x0A,0x94,0x3E,
++    0x0A,0x01,0x00,0x17,0x02,0x40,0xCA,0x10,0x04,0x09,0x09,0x00,0xC2,0x80,0xF0,0x13,
++    0xF0,0x03,0xD8,0x04,0x02,0x00,0x1A,0xD2,0x02,0x90,0xCA,0x90,0xC0,0x80,0x10,0x19,
++    0x14,0x90,0xC0,0x10,0x00,0x21,0xF0,0x82,0xD4,0x0C,0x10,0x82,0xD0,0x5E,0x31,0x42,
++    0x02,0x17,0xE1,0x10,0x36,0xA2,0x94,0x95,0x01,0x98,0x3A,0x09,0xCD,0xD8,0x0A,0xF8,
++    0xCA,0xD8,0x06,0x30,0x33,0xF2,0xCC,0xB0,0xF7,0xDB,0xC8,0xB0,0xB3,0x9B,0x31,0x9A,
++    0xF3,0xDB,0xB2,0x9B,0x1A,0x31,0x18,0xD2,0x3A,0x19,0xCA,0x90,0x08,0xF8,0x33,0x31,
++    0xCB,0x90,0x1E,0x82,0xCC,0x00,0x4A,0x9C,0xCC,0x00,0x0E,0x1C,0x4E,0x9C,0x0E,0x1C,
++    0x50,0x94,0x10,0x14,0x36,0x12,0x93,0x85,0xF2,0x13,0xF5,0x90,0x16,0x12,0xE4,0xC6,
++    0xF2,0x03,0xF5,0x00,0xB2,0x03,0xE5,0x48,0x95,0x4D,0xF6,0x03,0x15,0x42,0xC4,0xCE,
++    0x31,0x0A,0x31,0x42,0xBF,0xFF,0xEF,0x87,0x87,0x3D,0xE8,0x85,0x00,0xA0,0x00,0x01,
++    0xAC,0xFD,0x87,0x2D,0xE0,0x74,0x00,0x01,0x80,0x1C,0xC0,0x3C,0xD0,0x33,0xC6,0x3C,
++    0x58,0x04,0x86,0x0C,0xC3,0x34,0x18,0x82,0x50,0xFA,0xCF,0x2C,0xC2,0x48,0xC4,0x08,
++    0x8F,0x24,0x40,0xF2,0xC0,0x03,0x40,0x09,0x88,0x0E,0xC0,0x3C,0xD8,0x33,0x04,0x01,
++    0x10,0x01,0x00,0x1F,0x82,0x53,0xE0,0x48,0xE6,0x00,0x92,0x05,0x17,0x82,0x9D,0xCE,
++    0x08,0x01,0x00,0x09,0xD8,0x44,0xD0,0x34,0x86,0x07,0xD0,0x6F,0x28,0x01,0x60,0x01,
++    0x8B,0x0E,0xE0,0x68,0x90,0x6D,0xFF,0x24,0x08,0x01,0x00,0x5F,0xC1,0xC3,0x19,0x02,
++    0x91,0x05,0x86,0xC3,0xD4,0x7C,0x10,0x82,0xCD,0x0E,0x18,0x02,0x83,0xC3,0xE1,0xF8,
++    0xE6,0x48,0x92,0x4D,0x17,0x8A,0x9D,0x8E,0x08,0x09,0xC6,0x2C,0x02,0x48,0xC4,0x00,
++    0x80,0x14,0xD0,0x44,0x90,0x04,0x00,0x11,0xD8,0x3C,0xD0,0x2C,0xC8,0x34,0x80,0x07,
++    0xD8,0x07,0xD0,0x44,0xC0,0x3C,0x90,0x04,0x82,0x01,0xCA,0x0B,0x00,0x01,0x1C,0x0A,
++    0x10,0x01,0xD8,0x3C,0xC0,0x14,0x80,0x0F,0xDD,0xCF,0xDD,0xC0,0x09,0x01,0x00,0x3F,
++    0xD0,0x14,0x18,0x01,0xF0,0x9A,0xD6,0x0C,0xD0,0xD0,0x94,0x95,0x68,0x01,0x88,0x2E,
++    0x50,0xC1,0xE8,0xBE,0xC5,0x13,0x18,0x12,0x80,0x13,0x00,0x9F,0x50,0x99,0xE8,0x2E,
++    0xC0,0x13,0x50,0x01,0x82,0x16,0xF0,0x90,0x80,0x13,0x00,0x5F,0x68,0x29,0x88,0x4E,
++    0x58,0xE1,0xEE,0x3E,0xC0,0x13,0x50,0x01,0x88,0x26,0xD0,0x1C,0x50,0x01,0x88,0x0E,
++    0x10,0x09,0x90,0x1C,0xD4,0x14,0xE0,0x90,0x92,0x14,0xE0,0x00,0xE6,0x48,0x92,0x4D,
++    0x16,0x8A,0x9D,0xAE,0x40,0x20,0x6B,0x21,0xC8,0x0E,0xD5,0x44,0x90,0x04,0x08,0x01,
++    0x00,0x19,0xD8,0x3C,0xD0,0x2C,0x80,0x07,0xD0,0xE7,0x0D,0x09,0x30,0x42,0xD8,0x44,
++    0xD0,0x34,0x80,0x07,0xD0,0x07,0xC3,0x1C,0x87,0x4D,0xE8,0x85,0xAC,0xFD,0x87,0x1D,
++    0xF0,0x64,0x30,0x7A,0x37,0xEA,0xD0,0xC3,0x86,0x14,0x08,0x09,0xC4,0x1C,0x00,0x48,
++    0xC5,0x20,0x42,0xB2,0xC0,0x03,0x40,0x09,0x8D,0x0E,0xD8,0xC3,0x80,0x14,0x08,0x01,
++    0x00,0x09,0xD8,0x2C,0xD0,0x6C,0x80,0x07,0xD0,0x37,0xD2,0x2C,0x91,0x04,0x30,0xDA,
++    0x00,0x11,0xD0,0x1C,0xC8,0x6C,0x80,0x07,0xD0,0xA7,0xD4,0x2C,0x92,0x04,0x00,0x29,
++    0xEC,0x0A,0x06,0x01,0x19,0x0A,0x30,0xDA,0x11,0x01,0x30,0x02,0x82,0x0F,0xD8,0x77,
++    0xD0,0x2C,0x90,0x04,0x30,0xDA,0x09,0x01,0x00,0x19,0xD0,0x1C,0x84,0x07,0xD0,0x0F,
++    0x08,0x09,0x30,0x42,0xD8,0x2C,0xD0,0x6C,0x81,0x07,0xD0,0x2F,0x41,0x02,0x05,0x44,
++    0x01,0x01,0x00,0x84,0x08,0x01,0x00,0x77,0x01,0x01,0xF0,0x02,0x15,0x01,0xF0,0x52,
++    0x10,0x12,0xEC,0x06,0x00,0x44,0x11,0x01,0xF4,0x92,0x15,0x12,0xD1,0x06,0x00,0x84,
++    0xE2,0x20,0xE5,0x48,0x90,0x4D,0xC6,0x14,0x17,0x0A,0x9C,0x6E,0x87,0x3D,0xE8,0x85,
++    0xAC,0xBD,0x87,0x45,0xC2,0x4C,0xD8,0x03,0x80,0x1C,0xC8,0x4C,0xD0,0x4B,0x8E,0x14,
++    0x50,0x6A,0xCC,0x44,0xC0,0x48,0x8C,0x3C,0x48,0x62,0xC4,0x4B,0x48,0x09,0x88,0x46,
++    0xCA,0x1C,0xE0,0x48,0x90,0x4D,0x8E,0x1C,0x80,0x34,0xC0,0x4C,0xD8,0x03,0x84,0x14,
++    0x00,0x0F,0x00,0x01,0x80,0x34,0xF8,0x34,0x04,0x3F,0x4B,0x32,0x04,0x01,0x00,0x43,
++    0xC0,0x4C,0xC8,0x3C,0xD3,0x03,0x1E,0xC2,0xC0,0x08,0x02,0x01,0x10,0xF9,0x01,0x1F,
++    0x82,0x53,0xE0,0x48,0xE6,0x00,0x92,0x05,0xDC,0x14,0x10,0xC2,0x9C,0xC6,0x27,0x01,
++    0x31,0x2A,0x31,0x32,0x03,0xC7,0x40,0xE2,0x08,0x23,0x4E,0x25,0xB8,0x0C,0x88,0x04,
++    0x40,0x45,0x40,0x3E,0x5F,0x2D,0xB8,0xFF,0xFB,0x8F,0x33,0x5A,0x00,0xA1,0xF0,0xC2,
++    0x40,0xE1,0xD1,0x1E,0x68,0x41,0x80,0x4E,0x18,0x62,0x05,0x1F,0x70,0x01,0x8C,0x0E,
++    0x30,0x72,0x01,0x1F,0x41,0x68,0x1B,0x62,0x6F,0x01,0x88,0x26,0xC0,0x4C,0xC8,0x3C,
++    0xD3,0x03,0x1E,0xC2,0xC0,0x08,0x02,0x01,0x10,0x01,0x00,0x1F,0x82,0x53,0xE0,0x48,
++    0xE6,0x00,0x92,0x05,0xDC,0x14,0x10,0xC2,0x99,0xC6,0x37,0xAA,0x20,0x01,0x00,0x0F,
++    0x1B,0xA2,0x41,0xB0,0x77,0x01,0x88,0xDE,0xC6,0x4C,0x58,0x04,0xC0,0x41,0x91,0x35,
++    0x05,0x8F,0x18,0x62,0x46,0x02,0x0B,0x23,0x48,0x25,0xB8,0x0C,0x88,0x04,0x40,0x45,
++    0x40,0x3E,0x58,0x2D,0xB9,0xFF,0xFF,0xD7,0x30,0x5A,0x03,0x81,0xF5,0xC2,0x10,0x82,
++    0xE9,0x06,0x18,0x62,0x40,0x68,0x6B,0x01,0x88,0x5E,0xC7,0x44,0x0E,0xE9,0xC9,0x00,
++    0x0A,0x48,0xC2,0x00,0xAB,0x23,0xE0,0xF8,0x90,0xFD,0xC7,0x1C,0x14,0x3A,0x9C,0xA6,
++    0xF1,0x34,0x00,0x9F,0xC1,0x44,0x08,0xE9,0xCA,0x00,0x0C,0x48,0xC1,0x38,0xEA,0xC3,
++    0x40,0x01,0x88,0x0E,0x01,0x09,0xA8,0xC3,0xE8,0xE3,0x29,0x01,0x01,0x01,0x00,0x07,
++    0xE7,0x68,0x93,0x6D,0x40,0x09,0x88,0x1E,0x60,0xF9,0x97,0x0E,0xE5,0x20,0x93,0x25,
++    0x48,0x22,0x02,0x01,0x00,0x43,0xAC,0x48,0x46,0x1A,0x0A,0x23,0x20,0x00,0x67,0x10,
++    0x02,0x07,0x40,0x48,0x30,0x82,0x10,0x42,0x81,0xDE,0x4F,0x01,0xC9,0x06,0x08,0x01,
++    0x88,0x04,0x90,0x0C,0x40,0x45,0x40,0x6E,0x37,0x8A,0xB9,0xFF,0xF0,0x0F,0x43,0x01,
++    0x80,0x0E,0x68,0x29,0x99,0xE6,0xAE,0xE3,0xE7,0xB0,0x93,0xB5,0xC4,0x1C,0x10,0x32,
++    0x98,0x46,0x86,0x5D,0xEF,0x85,0xAF,0xBD,0x80,0x15,0x34,0x62,0x31,0xB2,0x48,0x7A,
++    0x00,0x01,0x80,0x43,0x40,0x8A,0x41,0x0B,0x10,0x11,0x18,0x8A,0x00,0x0B,0x28,0x01,
++    0x00,0x3F,0x08,0x09,0x31,0x9A,0x31,0x52,0x30,0x42,0x80,0x07,0xCB,0xA7,0xE1,0x68,
++    0x95,0x6D,0xD7,0x03,0x17,0x42,0xC5,0xA6,0x31,0x12,0x31,0x8A,0x00,0x11,0x80,0x07,
++    0xC1,0x7F,0x34,0x92,0x30,0x0A,0xC1,0x14,0xB8,0xFF,0xFF,0xD7,0x31,0x12,0x31,0x8A,
++    0x00,0x01,0x80,0x07,0xC5,0x2F,0xDC,0x03,0x41,0x01,0x80,0x46,0x6F,0xF2,0x40,0x43,
++    0x91,0x3D,0x4C,0x04,0x00,0x43,0x47,0xCA,0x08,0x09,0x80,0x0B,0x31,0x12,0x31,0x8A,
++    0x00,0x11,0x80,0x07,0xC1,0xAF,0x33,0x1A,0xB0,0x04,0x08,0x01,0x00,0x09,0xD0,0x14,
++    0x82,0x07,0xC8,0xFF,0xB3,0x04,0xD8,0x0B,0x30,0x1A,0x01,0x11,0xD0,0x14,0x80,0x07,
++    0xC9,0xC7,0x32,0x92,0x30,0x0A,0xC1,0x14,0xBF,0xFF,0xF7,0x97,0x31,0x12,0x31,0x8A,
++    0x00,0x01,0x80,0x07,0xC0,0xEF,0x42,0x4A,0x08,0x01,0x80,0x0B,0x01,0x7B,0x37,0x1A,
++    0xB0,0x04,0x08,0x01,0x00,0x11,0xD0,0x14,0x82,0x07,0xC8,0x1F,0x31,0x12,0x31,0x8A,
++    0x00,0x11,0x80,0x07,0xC0,0x6F,0x02,0x5F,0x30,0x20,0x06,0x00,0x00,0xB0,0x00,0x01,
++    0xF8,0xFB,0x07,0x00,0x10,0x00,0x00,0x42,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,
++    0x50,0x1A,0x40,0x83,0x0C,0x11,0x18,0x42,0x00,0x83,0x80,0x2D,0xE8,0x85,0x07,0x00,
++    0x18,0x00,0x04,0x42,0xA8,0x85,0x31,0x12,0x90,0x01,0xE6,0x9B,0x32,0xD8,0x72,0xD8,
++    0xA7,0x9B,0x58,0xCA,0x41,0xE3,0x30,0x20,0xA2,0x16,0x40,0xE3,0x3F,0x20,0xAB,0xE6,
++    0x58,0xB2,0x27,0x41,0x00,0xE3,0x44,0xE3,0x28,0xF9,0xAF,0x19,0x18,0x62,0x01,0xE3,
++    0x20,0x81,0x48,0x01,0x83,0x76,0x00,0xE9,0x08,0x00,0xE4,0x8B,0x48,0x48,0x8E,0x1E,
++    0xF0,0x00,0x22,0x00,0x67,0x00,0x88,0xC6,0x40,0x01,0x88,0x16,0x41,0xC3,0x18,0x02,
++    0x01,0xC3,0xE8,0x85,0x80,0x01,0xE5,0x8B,0x48,0x48,0x8E,0x16,0xE8,0x0B,0x4E,0x31,
++    0x8E,0xCE,0xEF,0x03,0x47,0x31,0x88,0xA6,0x41,0xC3,0x18,0x02,0x01,0xC3,0xE8,0x85,
++    0xAA,0x85,0x47,0x63,0x46,0x5B,0xD6,0xAB,0x71,0x0A,0xC7,0xB3,0x70,0x09,0x88,0x16,
++    0x4A,0x63,0x56,0x5B,0xD8,0xAB,0x44,0x01,0x88,0x0E,0x11,0x01,0x01,0xE7,0x40,0x03,
++    0x30,0x32,0xB0,0x41,0x30,0xA2,0xED,0x08,0x32,0x42,0xC0,0x01,0x58,0x33,0xC4,0xFB,
++    0x1C,0xF2,0x19,0x33,0x58,0x33,0xC6,0xFB,0x1E,0xF2,0x1D,0x33,0x31,0x32,0x43,0x83,
++    0xC5,0xF3,0x18,0x82,0x31,0x32,0x03,0x83,0x40,0x73,0xC0,0xC3,0x18,0x32,0x04,0x73,
++    0xEA,0x20,0xE1,0xD8,0xE6,0x90,0x92,0x95,0x17,0x52,0x9D,0x06,0xE8,0x85,0x47,0x09,
++    0x88,0x0E,0x11,0x01,0x01,0xE7,0x40,0x03,0x30,0x32,0xB0,0x41,0x30,0xA2,0xED,0x08,
++    0x32,0x42,0xC0,0x01,0x58,0x33,0xC4,0xFB,0x1C,0xF2,0x1D,0x33,0x58,0x33,0xC6,0xFB,
++    0x1E,0xF2,0x1D,0x33,0x31,0x32,0x43,0x83,0xC5,0xF3,0x18,0x82,0x31,0x32,0x03,0x83,
++    0x40,0x73,0xC0,0xC3,0x18,0x32,0x00,0x73,0xEA,0x20,0xE1,0xD8,0xE6,0x90,0x92,0x95,
++    0x17,0x52,0x9D,0x06,0xE8,0x85,0x47,0x11,0x88,0x0E,0x11,0x01,0x01,0xE7,0x40,0x03,
++    0x30,0x32,0xB0,0x41,0x30,0xA2,0xED,0x08,0x32,0x42,0xC0,0x01,0x58,0x33,0xC4,0xFB,
++    0x1C,0xF2,0x1D,0x33,0x58,0x33,0xC6,0xFB,0x1E,0xF2,0x1D,0x33,0x31,0x32,0x43,0x83,
++    0xC1,0xF3,0x18,0x82,0x31,0x32,0x03,0x83,0x40,0x73,0xC0,0xC3,0x18,0x32,0x04,0x73,
++    0xEA,0x20,0xE1,0xD8,0xE6,0x90,0x92,0x95,0x17,0x52,0x9D,0x06,0xE8,0x85,0x47,0x19,
++    0x88,0xE6,0x17,0x01,0x01,0xE7,0x40,0x03,0x30,0x32,0xB0,0x41,0x30,0xA2,0xED,0x08,
++    0x32,0x42,0xC0,0x01,0x58,0x33,0xC4,0xFB,0x1C,0xF2,0x1D,0x33,0x58,0x33,0xC6,0xFB,
++    0x1E,0xF2,0x1D,0x33,0x31,0x32,0x43,0x83,0xC1,0xF3,0x18,0x82,0x31,0x32,0x03,0x83,
++    0x40,0x73,0xC0,0xC3,0x18,0x32,0x00,0x73,0xEA,0x20,0xE1,0xD8,0xE6,0x90,0x92,0x95,
++    0x17,0x52,0x9D,0x06,0xEF,0x85,0xAF,0x85,0x44,0xE3,0x02,0xB0,0xCE,0x20,0x45,0xEB,
++    0xC0,0x68,0x45,0x09,0x88,0x26,0x40,0xE3,0xCC,0x20,0x45,0xDB,0xC0,0xE8,0x04,0x3F,
++    0x79,0x7A,0xC4,0xFB,0x78,0x09,0x88,0x1E,0x4D,0xE3,0xCE,0x20,0x54,0xDB,0xC2,0xE8,
++    0x40,0x13,0xF9,0xA0,0xC0,0x5B,0x41,0x09,0x88,0x76,0x48,0x01,0x8A,0x66,0x40,0x83,
++    0x1A,0xC2,0x04,0x83,0x44,0x83,0x1C,0xC2,0x01,0x83,0x44,0x03,0x19,0xC2,0x04,0x03,
++    0x40,0x83,0x18,0xC2,0x07,0x83,0xE8,0x85,0x48,0x09,0x88,0x66,0x44,0x83,0x1A,0xC2,
++    0x04,0x83,0x42,0x83,0x1C,0xC2,0x04,0x83,0x44,0x83,0x18,0xC2,0x01,0x83,0x40,0x03,
++    0x19,0xC2,0x00,0x03,0xE8,0x85,0x4F,0x11,0x89,0x66,0x40,0x03,0x19,0xC2,0x04,0x03,
++    0x44,0x83,0x18,0xC2,0x02,0x83,0x40,0x83,0x1A,0xC2,0x00,0x83,0x44,0x83,0x1C,0xC2,
++    0x07,0x83,0xEC,0x85,0x4F,0x19,0x88,0xE6,0x44,0x03,0x19,0xC2,0x00,0x03,0x41,0x83,
++    0x18,0xC2,0x04,0x83,0x44,0x83,0x1A,0xC2,0x04,0x83,0x42,0x83,0x1C,0xC2,0x00,0x83,
++    0xEF,0x85,0xAF,0xFD,0xF4,0x4C,0x30,0x62,0x29,0x01,0x48,0x93,0x4C,0x8B,0x35,0x72,
++    0xD1,0xE3,0x36,0x3A,0x48,0x32,0xC3,0x4B,0x48,0x09,0x88,0x0E,0x54,0x93,0xD9,0xE3,
++    0x41,0x19,0x80,0x96,0x33,0x79,0x48,0x0A,0x10,0xB0,0x41,0x11,0x8B,0xB6,0x30,0x02,
++    0x1B,0x3A,0x5A,0x02,0xC6,0x14,0xC0,0x00,0xC3,0xC0,0x31,0x9A,0x32,0x2A,0xEB,0xDA,
++    0x08,0x5B,0x0A,0x01,0x00,0x3F,0xC0,0x1B,0x18,0x9A,0x41,0xAB,0x00,0x5B,0xE9,0x90,
++    0xE2,0x00,0xE2,0x48,0x95,0x4D,0x16,0x0A,0x9F,0xAE,0xEF,0xFD,0x40,0x01,0x88,0x8E,
++    0x1E,0x01,0x10,0x5B,0x40,0x82,0x42,0x33,0x45,0xB0,0x05,0xB0,0x02,0x33,0x00,0x1B,
++    0x00,0x5B,0x40,0x0B,0x1C,0x81,0x18,0xCA,0x00,0x0B,0x40,0x0B,0x18,0x01,0x1C,0xCA,
++    0x00,0x0B,0x00,0x17,0x40,0x09,0x88,0x06,0x30,0xAA,0x01,0x01,0x00,0x27,0x40,0x8B,
++    0x00,0x6B,0xE8,0x90,0xE6,0x00,0x92,0x05,0x17,0x02,0x9D,0xC6,0xEF,0xFD,0xAF,0x85,
++    0x30,0x72,0xCC,0x2C,0xD5,0x63,0x36,0x22,0x46,0xEB,0x42,0xE3,0x40,0x01,0x88,0x1E,
++    0xDC,0x43,0x32,0x22,0x44,0xEB,0x40,0xE3,0x51,0x19,0x88,0x16,0x00,0x01,0x00,0xEF,
++    0x3E,0x10,0x7E,0x90,0x28,0x92,0x8B,0xAE,0x40,0x53,0x31,0xB2,0xB0,0x41,0xE8,0x98,
++    0x32,0xD2,0xD0,0x01,0x59,0xBB,0xC4,0x0B,0x1C,0x7A,0x1C,0xBB,0x59,0xBB,0xC6,0x0B,
++    0x1E,0x7A,0x1C,0xBB,0x41,0x93,0xC1,0x3B,0x19,0xD2,0x01,0x93,0x41,0xCB,0xC0,0x13,
++    0x18,0x8A,0x00,0xCB,0xEB,0x68,0xE1,0x20,0xE6,0x00,0x92,0x05,0x2E,0x02,0x9B,0xFE,
++    0xE8,0x85,0x57,0x29,0x88,0xE6,0x07,0x01,0x06,0xEF,0x38,0x10,0x7B,0x90,0x2E,0x92,
++    0x89,0xAE,0x40,0x53,0x30,0xB2,0xB0,0x41,0xE8,0x98,0x30,0xD2,0xD4,0x01,0x5A,0xBB,
++    0xC0,0x0B,0x19,0x7A,0x1E,0xBB,0x5C,0xBB,0xC4,0x0B,0x19,0x7A,0x19,0xBB,0x46,0x93,
++    0xC5,0x3B,0x19,0xD2,0x00,0x93,0x41,0xCB,0xC4,0x13,0x19,0x8A,0x01,0xCB,0xE8,0x68,
++    0xE2,0x20,0xE3,0x00,0x93,0x05,0x2E,0x02,0x9F,0xFE,0xEE,0x85,0xA8,0x85,0xF7,0x2C,
++    0x37,0x22,0xD4,0xAB,0xC4,0x34,0x00,0xB8,0x4E,0x03,0xC8,0x20,0x44,0xB2,0xC0,0xD8,
++    0xC3,0xC0,0x30,0x1A,0x58,0x01,0x88,0x1E,0xD8,0xAB,0xDB,0x34,0x4E,0xDB,0xCA,0xE0,
++    0x48,0x11,0x88,0xA6,0xB5,0x01,0xE4,0x8B,0x48,0x01,0x80,0x16,0x18,0x69,0x10,0xD8,
++    0x00,0x57,0x18,0x79,0x10,0xD8,0x00,0x3F,0xC0,0x0B,0x18,0xCA,0x41,0x33,0x01,0x8B,
++    0xA4,0x41,0xE0,0x00,0xE6,0x90,0x94,0x95,0x17,0x52,0x9D,0xAE,0xE8,0x85,0x4F,0x19,
++    0x8F,0xE6,0x07,0xF9,0x18,0x02,0x06,0x77,0x18,0x00,0x04,0x42,0x00,0x01,0x00,0x42,
++    0x00,0xB0,0x00,0x01,0x30,0x20,0x06,0x00,0x40,0x60,0x02,0x00,0x40,0x0B,0x01,0x43,
++    0xA4,0x41,0xE0,0x90,0x95,0x95,0x16,0x52,0x9F,0xC6,0xEF,0x85,0xAC,0xFD,0x87,0x25,
++    0x30,0x6A,0x30,0xB2,0x31,0xE2,0x48,0x3B,0x06,0xC9,0x07,0x00,0xC0,0x40,0x81,0x1C,
++    0xD0,0x83,0x87,0x14,0xC0,0x24,0x40,0x01,0x8B,0x16,0xD8,0x83,0x83,0x14,0x48,0x3B,
++    0x30,0x1A,0x11,0x19,0x08,0x01,0xB0,0x04,0xC7,0x24,0xB8,0xFF,0xF9,0x87,0x32,0x1A,
++    0x10,0x19,0x08,0x09,0xB0,0x04,0xC0,0x24,0xBA,0xFF,0xFF,0x4F,0x30,0x5A,0x11,0x01,
++    0x08,0x11,0xB0,0x04,0xA0,0x0C,0xC0,0x24,0xBC,0xFF,0xFF,0xC7,0x30,0x5A,0x11,0x09,
++    0x08,0x11,0xB0,0x04,0xA0,0x0C,0xC0,0x24,0xBC,0xFF,0xFF,0x87,0x36,0x82,0x81,0x01,
++    0xE2,0x0B,0x30,0x48,0x70,0x48,0xA2,0x0B,0x57,0xFA,0x0F,0xC1,0x00,0x8B,0x44,0x8B,
++    0x18,0xF9,0x9F,0x19,0x18,0xCA,0x00,0x8B,0x35,0x8A,0x89,0x01,0x01,0x07,0xF8,0x85,
++    0xE6,0x1B,0x48,0xD8,0x8E,0x16,0xE8,0x5B,0x5F,0x31,0x88,0xC6,0xE8,0x43,0x46,0x31,
++    0x88,0x1E,0x40,0x83,0x08,0x81,0x18,0x42,0x00,0x83,0x00,0x01,0x04,0x3F,0x00,0x08,
++    0xC2,0xCA,0x43,0x4B,0xDA,0x1C,0x00,0x10,0x92,0xCA,0xE4,0x00,0x90,0x05,0xCE,0x14,
++    0x17,0x42,0x9C,0xA6,0x30,0x5A,0x11,0x01,0x08,0x19,0xB0,0x04,0xA0,0x0C,0xC0,0x24,
++    0xBA,0xFF,0xFF,0xE7,0x30,0x5A,0x11,0x09,0x08,0x19,0xB0,0x04,0xA0,0x0C,0xC0,0x24,
++    0xBA,0xFF,0xFF,0xA7,0x30,0x1A,0x11,0x29,0x08,0x09,0xB0,0x04,0xC7,0x24,0xB8,0xFF,
++    0xF1,0xB7,0x37,0x1A,0x10,0x29,0x08,0x01,0xB0,0x04,0xC0,0x24,0xBF,0xFF,0xF7,0x7F,
++    0x87,0x45,0xE8,0x85,0xAC,0xFD,0x87,0x35,0x08,0xC9,0xC7,0x3C,0x02,0x48,0xC6,0x28,
++    0x48,0xD2,0xC6,0x3C,0xC0,0x20,0xC2,0x44,0xD0,0x33,0xC6,0x34,0x40,0x01,0x88,0x0E,
++    0xC2,0x44,0xD8,0x33,0xC4,0x44,0x80,0x01,0x86,0x2C,0xE0,0x03,0x43,0x01,0x88,0xE6,
++    0x08,0xF9,0x01,0x17,0xA2,0x0A,0xE1,0x00,0x95,0x05,0x14,0x82,0x9C,0xD6,0x3F,0x01,
++    0xB8,0x24,0xB8,0x14,0x06,0x57,0x49,0x62,0xC6,0x24,0x08,0x43,0x40,0x35,0x40,0x7E,
++    0xBA,0xFF,0xFF,0xE7,0x48,0x52,0x1E,0x01,0x00,0x01,0x00,0x67,0x04,0x10,0x32,0xA2,
++    0xF4,0x52,0x15,0xD2,0xEB,0x0E,0x30,0x1A,0xD4,0x5A,0x17,0x52,0xD3,0x0E,0x30,0x0A,
++    0xD2,0x4A,0xE3,0x00,0x95,0x05,0x14,0x82,0x9A,0x86,0x4F,0x81,0x90,0x2E,0x78,0x41,
++    0x80,0x76,0xC0,0x24,0x18,0xC2,0x85,0x24,0x00,0x27,0xC0,0x14,0x40,0x01,0x8C,0x0E,
++    0xB8,0x14,0x00,0x2F,0x40,0xF8,0xC3,0x24,0x18,0xC2,0x81,0x24,0x7E,0x01,0x88,0x96,
++    0x00,0x01,0x08,0x01,0x01,0x17,0xA0,0x0A,0xE4,0x00,0x92,0x05,0x17,0x82,0x9D,0xD6,
++    0xC0,0x14,0x80,0x1C,0x38,0x01,0x00,0x27,0xC0,0x14,0x18,0x3A,0xC2,0x14,0x40,0x00,
++    0x80,0x14,0xC0,0x14,0x47,0x01,0x88,0xBE,0xC6,0x2C,0x58,0x04,0xC0,0x41,0x91,0x05,
++    0x81,0x0C,0x00,0x17,0xC4,0x1C,0x18,0x3A,0x46,0x3A,0x0D,0x3B,0x40,0x35,0x40,0x7E,
++    0xB8,0xFF,0xFF,0xA7,0x58,0x32,0x0D,0x01,0x00,0x01,0x00,0x67,0x04,0x10,0x32,0xA2,
++    0xF4,0x52,0x15,0x52,0xEB,0x0E,0x30,0x0A,0xD4,0x4A,0x13,0xD2,0xD3,0x0E,0x30,0x12,
++    0xD2,0x5A,0xE5,0x00,0x95,0x05,0x14,0x82,0x98,0x86,0xC7,0x0C,0x10,0x0A,0xEC,0x0E,
++    0xC0,0x1C,0x18,0x3A,0xC2,0x1C,0x40,0x00,0x80,0x1C,0xC0,0x1C,0x46,0x01,0x88,0xCE,
++    0x78,0x01,0x88,0x06,0x38,0x09,0xC0,0x2C,0xA0,0x3B,0xC6,0x2C,0xE4,0x0B,0x46,0x92,
++    0x08,0x0B,0xC6,0x2C,0xE0,0x03,0x3E,0x09,0x16,0xF8,0x07,0x00,0x80,0x24,0x00,0x07,
++    0x40,0xF8,0xC3,0x24,0x17,0xC2,0x81,0xDE,0x78,0x01,0xC9,0x06,0x38,0x01,0x01,0x01,
++    0x08,0x01,0x00,0x17,0xA2,0x0A,0xE1,0x00,0x95,0x05,0x14,0x82,0x98,0xD6,0x07,0x01,
++    0x80,0x04,0x78,0x01,0x88,0x1E,0xC0,0x04,0xE6,0x00,0x92,0x05,0x80,0x04,0x00,0x01,
++    0x01,0x57,0xE0,0x0A,0x1E,0xCA,0x91,0x4D,0xA0,0x0A,0xD1,0x24,0x10,0x8A,0xCC,0x0E,
++    0x19,0xCA,0xA5,0x0A,0xE4,0x00,0x92,0x05,0x17,0x82,0x9D,0x96,0x40,0x35,0x40,0x7E,
++    0xBD,0xFF,0xF7,0xE7,0x01,0x01,0x00,0x0F,0xD2,0x2C,0x00,0x08,0xD6,0x4A,0x5B,0x94,
++    0xD0,0x48,0x94,0x4D,0xD0,0x04,0x50,0x01,0x8B,0x2E,0x48,0x21,0xE9,0xA6,0xE0,0x0A,
++    0x19,0xCA,0xA5,0x0A,0x01,0x87,0x48,0x91,0xE9,0x2E,0xE0,0x12,0x50,0x01,0x80,0x16,
++    0xF1,0x90,0xA2,0x12,0x01,0x47,0x10,0x89,0x1C,0x92,0x16,0x8A,0xD1,0x26,0xE0,0x0A,
++    0x48,0xF9,0x91,0x0E,0xE1,0x48,0xA2,0x0A,0xE4,0x00,0x92,0x05,0x16,0x82,0x9D,0xDE,
++    0x40,0xF8,0xC3,0x04,0x45,0x21,0xC8,0xE6,0x87,0x55,0xE8,0x85,0xAC,0xBD,0x87,0x75,
++    0xCE,0x84,0xD0,0x6B,0x10,0xC9,0xCF,0x7C,0x04,0x90,0xC6,0x48,0x18,0xF9,0xD1,0x7C,
++    0x0E,0xD8,0xC2,0x90,0x20,0xF9,0xDF,0x7C,0x00,0x20,0xCF,0xE0,0x30,0x09,0xDC,0x7C,
++    0x0C,0xB0,0xC9,0xD8,0x99,0x14,0x30,0x09,0xDD,0x7C,0x08,0xB0,0xC8,0xD8,0x9C,0x0C,
++    0x78,0x1D,0x40,0x01,0x88,0x0E,0xC0,0x84,0xD8,0x2B,0xC2,0x84,0xE0,0x03,0x44,0x29,
++    0xC0,0x56,0x00,0x01,0x02,0x37,0x00,0x18,0xD6,0x72,0x96,0xB2,0xD7,0x72,0x96,0x32,
++    0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0xB6,0x04,0x01,0x30,0x22,0x18,0x01,0x00,0xCF,
++    0x01,0xC0,0xD2,0x32,0x30,0x32,0xB4,0x6C,0x30,0x01,0x00,0x01,0xF8,0xB2,0xF4,0x42,
++    0xC3,0xB0,0x81,0xB0,0x31,0x82,0x93,0x32,0x40,0x74,0x00,0xB4,0xD0,0x02,0xF1,0x6C,
++    0xD9,0x00,0x04,0xC4,0x20,0x02,0x93,0x05,0x34,0x22,0xE4,0x90,0xE5,0x48,0xE4,0xF8,
++    0xE6,0xD8,0x92,0xDD,0x17,0x5A,0x9D,0x1E,0x71,0x1D,0x30,0x4A,0x30,0x02,0x83,0x0F,
++    0xD8,0x5F,0x95,0x0D,0x10,0x01,0x00,0xCF,0x01,0x01,0xF0,0x82,0xE0,0xB0,0x45,0x01,
++    0xE8,0x2E,0x48,0x01,0xEC,0x1E,0x10,0x42,0xE8,0x56,0x30,0x42,0x00,0x47,0x40,0x01,
++    0xD0,0x2E,0x48,0x01,0xD4,0x1E,0x10,0x42,0xD0,0x16,0x30,0x42,0x00,0x07,0x00,0x01,
++    0x07,0x98,0xD2,0x3A,0xD7,0xC0,0x91,0x02,0xE6,0x90,0x92,0x95,0x17,0x52,0x9D,0x1E,
++    0xC4,0x84,0xE0,0x03,0x40,0x29,0xC0,0xEE,0x00,0x01,0x10,0x01,0x02,0x3F,0x00,0x08,
++    0xF3,0x14,0xD0,0x1A,0x90,0x9A,0xCB,0x0C,0xA2,0x52,0xE0,0x00,0x95,0x05,0x16,0x42,
++    0x98,0xAE,0x07,0x01,0x12,0xF9,0x09,0x90,0x1A,0x09,0x0A,0xD8,0x00,0x47,0xE0,0x7C,
++    0x00,0x08,0xCA,0x48,0xC1,0x60,0x5C,0x24,0xC0,0x48,0x0E,0x64,0xE6,0x00,0x92,0x05,
++    0x17,0x42,0x9D,0xA6,0x87,0x8D,0xE8,0x85,0xAE,0xE5,0xD7,0x9B,0x9F,0x0C,0x18,0xF9,
++    0x06,0xD8,0xC6,0x58,0x34,0xF2,0x1C,0x09,0x0E,0xD8,0xC0,0x68,0x1C,0x09,0x09,0xD8,
++    0xC4,0x58,0x36,0xE2,0x1E,0xC9,0x07,0xD8,0xC0,0x48,0x8E,0x04,0x40,0x01,0x88,0x0E,
++    0xD8,0x83,0x82,0x0C,0x00,0x01,0x30,0x9A,0x9A,0x01,0x14,0xC3,0x11,0xC3,0x04,0xCF,
++    0x03,0x20,0x32,0x8A,0xD9,0x4A,0xD8,0x72,0xD8,0x48,0x94,0x75,0xC8,0x04,0x98,0x72,
++    0x08,0x01,0x38,0xB1,0xBD,0xFA,0x16,0xBA,0xE8,0x66,0x08,0x09,0x3A,0x09,0x50,0xF3,
++    0x01,0x3A,0x1C,0xF2,0x10,0xF3,0x02,0x77,0x00,0x01,0x00,0x42,0x40,0x60,0x02,0x00,
++    0xF8,0xFF,0x07,0x00,0xED,0xFB,0x16,0xBA,0xD0,0x2E,0x08,0x09,0x3C,0x09,0x50,0xF3,
++    0x01,0x3A,0x1C,0xF2,0x10,0xF3,0x4C,0x01,0x8D,0x96,0x08,0xC1,0xE0,0x4A,0x4C,0x01,
++    0x89,0x76,0xF8,0x7A,0x13,0xF0,0x31,0x0A,0xE4,0x4A,0xC8,0x70,0x30,0x8A,0xFB,0x4A,
++    0x04,0x48,0xCC,0x70,0x03,0xC8,0xD5,0x88,0x91,0x70,0x98,0x72,0x31,0x22,0xA3,0x0A,
++    0xE6,0x00,0x92,0x05,0xCC,0x0C,0x10,0x42,0x9F,0x16,0xEE,0xE5,0xAC,0xBD,0x87,0x65,
++    0x30,0x62,0x30,0xB2,0x40,0xFA,0x47,0x03,0x90,0x05,0x84,0x5C,0x40,0xF2,0x47,0x0B,
++    0x90,0x4D,0x8C,0x54,0x44,0x0B,0x92,0x4D,0x8E,0x4C,0x40,0x0B,0x90,0x4D,0x8C,0x44,
++    0x4C,0x0B,0x90,0x4D,0x8A,0x3C,0x48,0x0B,0x90,0x4D,0x8C,0x34,0x4C,0x0B,0x94,0x4D,
++    0x8E,0x2C,0x50,0x0B,0x90,0x4D,0x8C,0x24,0x4C,0x0B,0x96,0x4D,0x8A,0x1C,0x58,0x0B,
++    0x90,0x4D,0x8C,0x14,0x5C,0x0B,0x94,0x4D,0x88,0x0C,0x08,0x21,0x0C,0x0B,0x08,0x0B,
++    0xE7,0x0B,0x53,0x72,0x1E,0x8A,0x10,0x0B,0x08,0x01,0xDD,0x4A,0x01,0x0B,0x36,0x2A,
++    0xA9,0x01,0xEC,0x4B,0x1B,0x0B,0xEA,0x4B,0x1F,0x0B,0xE4,0x4B,0x0D,0x0B,0xE6,0x43,
++    0x40,0x01,0x80,0x3E,0x47,0x22,0x4F,0x32,0x00,0x0B,0x0A,0xC9,0x00,0x0B,0x08,0x09,
++    0x08,0x0B,0x02,0x3F,0x4F,0x12,0x47,0x02,0xCA,0xE1,0x00,0x0B,0x08,0x89,0x00,0x0B,
++    0x0A,0x41,0x08,0x0B,0xE0,0x03,0x45,0x09,0x8B,0xB6,0xD8,0x03,0x80,0x04,0x38,0x01,
++    0x00,0x3F,0x08,0x09,0x31,0x9A,0x31,0xD2,0x37,0x42,0xB8,0xFF,0xE3,0x67,0xE0,0xF8,
++    0x90,0xFD,0xC7,0x04,0x17,0x3A,0x9C,0xA6,0x31,0x9A,0x31,0x12,0x00,0x09,0xC8,0x64,
++    0xBD,0xFF,0xEF,0xC7,0xF3,0x43,0xB7,0x03,0x31,0x9A,0x31,0x12,0x00,0x09,0xC8,0x64,
++    0xB9,0xFF,0xEF,0xA7,0x30,0x12,0x01,0x09,0xCF,0x64,0xB8,0xFF,0xF1,0xFF,0x34,0x12,
++    0x00,0x09,0xC8,0x64,0xB9,0xFF,0xFF,0x87,0x48,0x32,0xC6,0x5C,0x06,0x43,0x40,0x32,
++    0xC8,0x54,0x00,0x0B,0xCA,0x4C,0x00,0x0B,0xCE,0x44,0x00,0x0B,0xC8,0x3C,0x08,0x0B,
++    0xCA,0x34,0x08,0x0B,0xCC,0x2C,0x08,0x0B,0xCE,0x24,0x10,0x0B,0xCE,0x1C,0x08,0x0B,
++    0xCA,0x14,0x18,0x0B,0xCC,0x0C,0x18,0x0B,0xE6,0x43,0x31,0x00,0xAB,0x66,0xF1,0x03,
++    0xF4,0x4B,0x15,0x42,0x89,0x46,0x31,0x02,0x82,0x01,0xE1,0x13,0x50,0x11,0x88,0x46,
++    0xE8,0x13,0x51,0x51,0x88,0x16,0x10,0x01,0xA0,0x13,0x02,0x9F,0xE1,0x90,0xAA,0x13,
++    0x05,0x87,0x50,0x53,0x50,0x01,0x88,0x2E,0x50,0x53,0x53,0x01,0x89,0x16,0xE8,0x13,
++    0x50,0x01,0x89,0x2E,0xF3,0x53,0xB7,0x13,0x11,0x09,0xB0,0x13,0xA0,0x13,0x02,0x0F,
++    0xE1,0x90,0xAA,0x13,0xF4,0x03,0x13,0x42,0x88,0x36,0x08,0x01,0x30,0x1A,0xB1,0x04,
++    0x30,0x42,0xD0,0x64,0xBF,0xFF,0xDF,0xEF,0x31,0x12,0x31,0x8A,0x07,0x11,0xB8,0xFF,
++    0xD8,0x3F,0x80,0x7D,0xEF,0x85,0xAF,0x85,0x4E,0xA3,0xD0,0xEB,0x33,0x70,0x72,0xB0,
++    0x4F,0x78,0x0E,0xF8,0x48,0xFA,0xC4,0x4B,0x48,0x09,0x88,0x0E,0x54,0xA3,0xD8,0xEB,
++    0x0F,0x01,0x18,0xF9,0x01,0x6F,0x40,0x13,0x47,0x93,0x02,0x92,0x90,0x95,0x00,0x14,
++    0x78,0x01,0x88,0x16,0x50,0xF9,0xEF,0x06,0x01,0x1C,0xE8,0x20,0xE2,0x00,0xE4,0x48,
++    0x95,0x4D,0x16,0x4A,0x9F,0x7E,0xEF,0x85,0xA8,0xC5,0x33,0x2A,0x34,0xB2,0x60,0x6A,
++    0x44,0x03,0x11,0x01,0x19,0x82,0x04,0x03,0x40,0x03,0x11,0x81,0x19,0x82,0x00,0x03,
++    0x40,0x03,0x11,0x09,0x19,0x82,0x00,0x03,0xE7,0x53,0x03,0xF9,0x80,0x81,0x18,0x12,
++    0x46,0x2A,0x14,0x13,0x13,0x99,0x00,0x13,0x14,0x41,0x00,0x13,0x12,0x91,0xEC,0x92,
++    0x50,0x01,0x80,0x16,0x10,0xC9,0x00,0x13,0x00,0x0F,0x10,0x89,0x00,0x13,0x30,0x52,
++    0x30,0x5A,0x09,0x01,0x00,0x09,0xB0,0x04,0xBD,0xFF,0xDF,0x5F,0x31,0x52,0x31,0x8A,
++    0x07,0x11,0xB8,0xFF,0xD3,0xAF,0x45,0x03,0x3F,0x00,0xAA,0xE6,0xEF,0xC5,0xAB,0x9D,
++    0x80,0x8D,0xCC,0x94,0xC8,0x4B,0x8A,0x84,0xE2,0x94,0xA0,0x01,0xD3,0x1B,0xD1,0x0B,
++    0x88,0x0C,0xC8,0x94,0xD0,0x6B,0x36,0x0A,0x8C,0x61,0x30,0x62,0xC8,0x94,0x30,0x01,
++    0xE0,0x4B,0x4C,0x09,0x88,0x56,0x08,0x01,0x02,0x27,0xC0,0x38,0x9A,0xF3,0xA1,0x32,
++    0xE2,0x48,0x92,0x4D,0xD6,0x94,0xD0,0x93,0x17,0x52,0xE4,0xB6,0x52,0x52,0x03,0xB3,
++    0x06,0xB3,0x04,0xB3,0x0E,0x01,0x18,0x4A,0x00,0x8B,0xC8,0x94,0xD0,0x4B,0xB6,0x8B,
++    0x0B,0x01,0x50,0x2A,0x34,0x01,0x00,0x78,0xC1,0xF8,0x0D,0xF3,0xC2,0x90,0xB2,0xB3,
++    0xE2,0x48,0x92,0x4D,0x4F,0x11,0xD8,0xA6,0xCC,0x94,0xE0,0x4B,0x4B,0x29,0xC8,0xA6,
++    0x00,0x48,0xC5,0x48,0x04,0x50,0xC3,0x70,0x14,0x09,0x06,0x90,0xC0,0xB0,0xB5,0x1C,
++    0xC0,0x48,0x8C,0x14,0x30,0x12,0x33,0x32,0xB0,0xC1,0x08,0x01,0x8A,0x3C,0x48,0xBA,
++    0x88,0x6C,0x88,0x64,0x30,0x32,0x04,0x01,0x32,0x22,0x04,0x27,0xC8,0x1C,0x00,0x01,
++    0xF0,0x42,0xF8,0x14,0x0B,0x01,0xF0,0xCA,0x32,0x7A,0xD0,0x08,0x97,0x4D,0x48,0xF9,
++    0xEF,0x06,0x08,0xF9,0xCB,0x38,0x86,0xF8,0x78,0xF9,0xEF,0x06,0x3B,0xF9,0x37,0x82,
++    0x82,0x3B,0xE0,0x00,0x30,0x32,0xC4,0xBB,0x10,0xFA,0x9C,0x46,0x10,0xCA,0xDC,0x36,
++    0x46,0x84,0xD9,0x48,0xC0,0x00,0x92,0x05,0x04,0x84,0x81,0x08,0x04,0x37,0x10,0xCA,
++    0xDC,0x16,0x00,0x78,0x00,0xBC,0x01,0x0F,0x39,0x01,0x00,0xBC,0x10,0xCA,0xDC,0x0E,
++    0x38,0x09,0xB8,0x3C,0x43,0x78,0x2B,0x3A,0xE8,0x26,0xF8,0x6C,0x10,0x7A,0xEC,0x2E,
++    0x88,0x6C,0x00,0x1F,0xFC,0x64,0x10,0x7A,0xE8,0x06,0x88,0x64,0x82,0x8B,0xE0,0x90,
++    0xE0,0xB0,0xC5,0x1C,0xE0,0x00,0x84,0x1C,0xC4,0x14,0xE0,0x00,0x83,0x14,0x30,0x02,
++    0xE2,0x00,0x92,0x05,0x35,0x22,0x2C,0x62,0xD8,0xC6,0xC5,0x3C,0x40,0x01,0x80,0xA6,
++    0x08,0x01,0x00,0x01,0x80,0x5C,0xC0,0x0C,0xC2,0x00,0x46,0x00,0x80,0x7C,0xC0,0x0C,
++    0x30,0x00,0x72,0x00,0x80,0x74,0x00,0x01,0x30,0x22,0x84,0x34,0x80,0x2C,0x80,0x24,
++    0xF3,0x90,0xF2,0x40,0x94,0x05,0x32,0x32,0x05,0x7F,0x02,0x77,0x32,0x02,0x03,0x00,
++    0x30,0x22,0xC4,0x34,0x00,0x00,0x82,0x34,0xC2,0x2C,0x00,0x00,0x80,0x2C,0xC0,0x24,
++    0x00,0x00,0x82,0x24,0x43,0x40,0x2B,0x82,0xE8,0x26,0xC0,0x83,0xF4,0x6C,0xD8,0x00,
++    0x80,0x83,0x00,0x1F,0xC0,0x83,0xF0,0x64,0xD8,0x00,0x84,0x83,0xC0,0x83,0x70,0x45,
++    0x37,0xBA,0xAB,0x82,0xC4,0x83,0x10,0xC2,0xDA,0xDE,0xE0,0x48,0x90,0x4D,0xF2,0x5C,
++    0xC1,0xB0,0x91,0xB5,0xB3,0x5C,0x30,0x32,0x39,0x09,0x18,0xF2,0x30,0xA2,0xF5,0x7C,
++    0x10,0x82,0xDD,0x76,0xF1,0x34,0x18,0xF2,0xB0,0x34,0xF0,0x0C,0x10,0x82,0xDD,0x46,
++    0xF1,0x2C,0x18,0xF2,0xB0,0x2C,0xF0,0x74,0x10,0x82,0xDD,0x16,0xC1,0x24,0x18,0xC2,
++    0x80,0x24,0x00,0x6F,0x18,0x00,0x04,0x42,0x00,0x01,0x00,0x42,0x10,0x78,0x00,0x00,
++    0x88,0x60,0x05,0x00,0x00,0xB0,0x00,0x01,0x58,0x80,0x04,0x01,0x78,0xF8,0x07,0x00,
++    0xF3,0x90,0x32,0x82,0xF2,0x00,0x92,0x05,0x33,0x32,0x34,0x82,0x45,0x01,0xD0,0x6E,
++    0x42,0xFA,0xB7,0x0B,0xD0,0x50,0xB3,0x13,0x36,0x12,0x1B,0x92,0x03,0x13,0x30,0x12,
++    0x08,0x13,0xD0,0x34,0x00,0x13,0xD2,0x2C,0x00,0x13,0xD4,0x24,0x00,0x13,0x36,0x01,
++    0x00,0xA7,0xC1,0x5C,0x87,0x0F,0xC0,0x07,0x90,0x05,0x80,0x5C,0x4D,0xA2,0x07,0x80,
++    0xC0,0x00,0x4A,0x13,0x40,0x45,0x08,0x01,0x1C,0x01,0x30,0xF2,0x30,0xE2,0x04,0xCF,
++    0x38,0x98,0x86,0x7E,0xC0,0x1B,0xF8,0x5C,0xD8,0xD8,0x96,0xDD,0x58,0x01,0xE8,0x36,
++    0x83,0x1B,0x20,0x9A,0x94,0xDD,0x36,0xF2,0xE2,0x48,0x92,0x4D,0x00,0x27,0x18,0x01,
++    0x80,0x1B,0x00,0x0F,0x18,0x01,0x80,0x1B,0x42,0x90,0xE2,0x00,0x32,0x1A,0xE3,0xD8,
++    0x94,0xDD,0x32,0xE2,0x2F,0x62,0xDD,0x1E,0xE3,0xB0,0x93,0xB5,0x30,0x82,0x83,0x5C,
++    0x45,0xFA,0x06,0x98,0xC0,0xD8,0x08,0xD3,0xCA,0x00,0xB4,0x0B,0x48,0x21,0xD8,0x0E,
++    0x76,0x09,0xD8,0x36,0x06,0x01,0x50,0xD2,0x04,0x08,0xC4,0x58,0xE4,0x08,0x02,0x70,
++    0xC0,0xB0,0x4D,0xEB,0x4D,0xB3,0x19,0xAA,0x08,0xEB,0xC0,0x80,0xF4,0x1B,0xF2,0x2B,
++    0xDA,0xD8,0xB2,0x1B,0x90,0x45,0x42,0x09,0xD8,0x76,0x07,0x09,0x9E,0x03,0x45,0x82,
++    0x0E,0x19,0x40,0x13,0x50,0x01,0x80,0x16,0x05,0x29,0x98,0x0B,0x04,0xF7,0x40,0x13,
++    0x50,0x01,0x80,0x16,0x05,0x21,0x98,0x0B,0x02,0xC7,0x40,0x0B,0x48,0x01,0x80,0x1E,
++    0x00,0x19,0x08,0x11,0x98,0x0B,0x05,0x8F,0x48,0x03,0x40,0x01,0x88,0x26,0xC0,0x94,
++    0x82,0x01,0xF5,0x03,0x40,0x51,0x98,0x0E,0x00,0x11,0x00,0x3F,0xC1,0x94,0x80,0x01,
++    0xD8,0x03,0x44,0x01,0x80,0x0E,0x00,0x11,0x00,0x07,0x00,0x09,0xDC,0x0B,0xE5,0x50,
++    0x9D,0x13,0xD7,0x13,0x38,0x90,0xA2,0x0E,0xF5,0x48,0x9A,0x0B,0xE0,0x0B,0x13,0x29,
++    0x10,0x0A,0x94,0x0E,0xA0,0x13,0x01,0xEF,0x10,0x0A,0xCC,0x46,0x40,0x09,0x88,0x16,
++    0x09,0x81,0xA7,0x0B,0x00,0xB7,0xD0,0x48,0x01,0x52,0xA4,0x13,0x00,0x97,0x40,0x19,
++    0xC8,0x0E,0x08,0x19,0x02,0x07,0x90,0x0D,0xE0,0x13,0x51,0x01,0x82,0x16,0xF0,0x90,
++    0xA0,0x13,0x01,0x3F,0xD2,0x94,0xF0,0x48,0xCA,0x93,0x1C,0x52,0xCA,0x84,0xC0,0x88,
++    0xD0,0x94,0x88,0x8B,0xA0,0x03,0x83,0x9D,0xEF,0x85,0xAF,0xBD,0x80,0x6D,0x34,0x6A,
++    0xD1,0x63,0x37,0x42,0x80,0x01,0x82,0x64,0xC8,0x03,0x86,0x3C,0xC4,0x64,0xD0,0x03,
++    0x30,0x00,0xA8,0x1E,0x02,0x91,0xEC,0x02,0x40,0x01,0x80,0xAE,0xC5,0x6C,0x00,0x08,
++    0xC3,0x40,0x00,0x08,0x12,0x09,0xC6,0x08,0x04,0x90,0xC4,0x48,0xC0,0x10,0x04,0x01,
++    0x18,0x01,0x00,0x2F,0x00,0x5C,0x00,0x9C,0xE4,0x48,0xE4,0x90,0xE2,0x00,0x92,0x05,
++    0x17,0x02,0xDD,0xBE,0x87,0x85,0xE8,0x85,0x00,0xE9,0xC9,0x6C,0x08,0x00,0xC2,0x40,
++    0x70,0x82,0xEC,0x03,0x08,0x83,0xD7,0x7C,0x91,0x04,0x30,0x5A,0x08,0x01,0x00,0x11,
++    0xD7,0x6C,0xB8,0xFF,0xCC,0xB7,0x45,0x5A,0x80,0x01,0x42,0x0B,0x34,0x5A,0x0B,0xCC,
++    0x5E,0x8B,0x09,0xCC,0x58,0x8B,0x13,0xCC,0x5A,0x8B,0x15,0xCC,0x44,0x8B,0x17,0xCC,
++    0x48,0x2A,0x44,0x53,0x17,0xD4,0x4E,0x93,0x18,0xD4,0x10,0x89,0x00,0x93,0x17,0x19,
++    0x18,0x93,0x43,0x53,0x1C,0x11,0x18,0xD2,0x00,0x53,0x40,0x0B,0x18,0xCA,0x00,0x0B,
++    0x35,0x42,0xE1,0x4B,0x80,0x01,0x81,0x5C,0x4A,0x09,0x88,0x66,0x68,0x44,0x81,0x14,
++    0x34,0x8A,0x59,0x43,0x90,0x35,0xB6,0x0C,0x00,0x01,0x80,0x04,0xD6,0x6C,0x08,0x09,
++    0x04,0x00,0x07,0x48,0xC2,0x00,0xC4,0x00,0x83,0x54,0x40,0x92,0x18,0x33,0x0A,0x01,
++    0x37,0x42,0xB9,0xFF,0xC0,0xBF,0xFA,0x54,0xC1,0x64,0x30,0x5A,0xC9,0x0B,0x34,0xC2,
++    0xD7,0x7C,0xB8,0xFF,0xEB,0x07,0x4C,0x6A,0x10,0x01,0x00,0x01,0x02,0x67,0x00,0x18,
++    0x37,0xE2,0xF4,0xDA,0x10,0x5A,0xD4,0x0E,0x33,0x0A,0xD3,0xCA,0x10,0x9A,0xEC,0x0E,
++    0x35,0x12,0xD3,0xD2,0xE2,0x00,0x92,0x05,0x17,0x02,0xDD,0x86,0xC4,0x14,0xE0,0x00,
++    0x10,0x0A,0x9C,0x36,0xC0,0x04,0x40,0x01,0x8B,0x9E,0x40,0x80,0x40,0x08,0xC2,0x70,
++    0x00,0x3F,0xC0,0x14,0xF4,0x00,0x14,0x12,0xE0,0x5E,0x00,0x09,0x83,0x04,0xE0,0xB0,
++    0x90,0xB5,0x77,0x01,0x80,0x16,0xC0,0x0C,0x16,0x32,0x9C,0x36,0x70,0x01,0x88,0x06,
++    0x30,0x09,0xC0,0x5C,0x88,0x33,0xC0,0x5C,0xCA,0x0B,0x40,0x92,0x18,0x0B,0x32,0x01,
++    0x35,0x42,0x81,0x01,0x81,0x4C,0x80,0x01,0x83,0x44,0x00,0x4F,0xC4,0x3C,0x10,0x32,
++    0xD0,0x6E,0xC0,0x44,0xE0,0x03,0xC8,0x44,0x32,0x00,0x72,0x00,0xA2,0x43,0x40,0x4A,
++    0x0C,0x41,0x00,0x0B,0x47,0x0B,0x10,0xF9,0x90,0x21,0x18,0x8A,0x00,0x0B,0xC8,0x6C,
++    0x02,0x00,0xC5,0x08,0x06,0x00,0x13,0x09,0xC4,0x40,0x00,0x90,0xC4,0x00,0xC4,0x48,
++    0x70,0x01,0x88,0x66,0x12,0x01,0x78,0x0A,0x00,0x37,0x18,0x01,0x00,0x1C,0x00,0x7C,
++    0xE4,0x00,0xE4,0x48,0xE2,0x90,0x92,0x95,0x17,0x12,0xDD,0xB6,0x00,0x0F,0xD9,0x6C,
++    0x06,0x10,0xC7,0x90,0x1C,0x09,0x06,0xD8,0xC4,0x90,0x36,0xA2,0x18,0x01,0x00,0x9F,
++    0x30,0x3A,0x13,0x01,0xF0,0xD2,0x3D,0x01,0xFC,0x3A,0x16,0xBA,0xD0,0x06,0x00,0x14,
++    0x3E,0x01,0xF8,0x7A,0x10,0xBA,0xEC,0x06,0x04,0x54,0xE0,0x00,0xE3,0x48,0x34,0x12,
++    0xE4,0x90,0x34,0xA2,0xE2,0xD8,0x92,0xDD,0x17,0x1A,0xDD,0x4E,0xC4,0x3C,0x10,0x32,
++    0x80,0x0E,0xC1,0x44,0xE6,0x03,0x48,0x00,0x88,0x1E,0xC0,0x4C,0xE8,0x03,0x46,0x31,
++    0x88,0xBE,0xC7,0x4C,0xE8,0x03,0x46,0x31,0x89,0x26,0x40,0x12,0x40,0x0B,0x10,0x81,
++    0x18,0x8A,0x00,0x0B,0xCF,0x6C,0x00,0x00,0xC6,0x00,0x0A,0x09,0x02,0x48,0xC4,0x00,
++    0xC9,0x64,0x30,0x5A,0xC8,0x4B,0xD4,0x7C,0xBE,0xFF,0xE7,0xEF,0xE3,0xB0,0x93,0xB5,
++    0xC4,0x3C,0x10,0x32,0xE8,0x96,0x44,0xBA,0x34,0x5A,0x4B,0xCC,0x80,0x01,0x02,0x0B,
++    0x46,0xA2,0x48,0xCC,0x18,0x0B,0x50,0xCC,0x1A,0x0B,0x52,0xCC,0x1C,0x0B,0x54,0xCC,
++    0x00,0x0B,0x4E,0x8A,0x50,0xD4,0x06,0x53,0x5E,0xCC,0x08,0x0B,0x37,0x97,0xAF,0xFD,
++    0x81,0xED,0xE4,0x3C,0x30,0xAA,0x00,0x01,0x80,0x7C,0x80,0x74,0xC6,0x34,0xD1,0x03,
++    0x81,0x6C,0xC0,0x34,0xDA,0x03,0xF2,0x00,0x90,0x05,0x86,0x64,0x00,0x01,0x80,0x5C,
++    0x80,0x54,0x80,0x4C,0xC4,0x34,0xC9,0x03,0x00,0x00,0x82,0xBC,0x08,0xA1,0x05,0x3F,
++    0x58,0x80,0x04,0x01,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0xF8,0xFB,0x07,0x00,
++    0xC2,0x34,0xF1,0x0A,0x80,0x40,0x82,0xB4,0xC1,0x34,0xD9,0x04,0xE7,0x03,0x9C,0xF9,
++    0x98,0x29,0x41,0x09,0x88,0x76,0xC0,0x6C,0x1E,0x42,0xC3,0x08,0xD0,0xEC,0x00,0x01,
++    0x00,0x2F,0x40,0xB4,0x82,0x73,0xE0,0x48,0xE2,0x90,0xE4,0x00,0x90,0x05,0xF2,0x6C,
++    0x17,0x82,0xDD,0xB6,0x00,0x01,0x80,0x9C,0x80,0xA4,0x80,0xAC,0xC4,0xEC,0x30,0x32,
++    0x70,0x1D,0xC8,0x6C,0x32,0x42,0x19,0x42,0x86,0xE4,0xC0,0x00,0x30,0x22,0x84,0xDC,
++    0x40,0xAA,0x47,0x13,0x48,0x1B,0x08,0x01,0x03,0x1F,0x31,0x82,0x30,0x3A,0x43,0x04,
++    0xC6,0xFB,0xD9,0x00,0x91,0x05,0x00,0x84,0x38,0xB8,0x86,0x26,0xFE,0xAC,0xC8,0x00,
++    0x90,0x05,0x80,0xAC,0x06,0x57,0x38,0xF8,0x80,0x26,0xF8,0xA4,0xC8,0x00,0x96,0x05,
++    0x80,0xA4,0x00,0x1F,0xFE,0x9C,0xC8,0x00,0x90,0x05,0x80,0x9C,0xE3,0xB0,0x35,0x82,
++    0xE4,0x00,0x34,0x32,0x32,0x02,0xE3,0x00,0x32,0x22,0x44,0x90,0x42,0xD8,0xE2,0x48,
++    0x90,0x4D,0xC2,0x6C,0x16,0x0A,0xDC,0xC6,0x79,0xFA,0xF6,0xCB,0x48,0x01,0xE8,0x26,
++    0xC0,0xAC,0x80,0x07,0xF0,0x8F,0x94,0x05,0x83,0xAC,0xF0,0xCB,0x48,0x01,0xE8,0x56,
++    0x48,0x09,0x88,0x1E,0xC2,0xA4,0x80,0x00,0x80,0xA4,0x00,0x27,0xC0,0xA4,0x80,0x07,
++    0xF0,0x1F,0x94,0x05,0x85,0xA4,0xF0,0xCB,0x48,0x01,0xE8,0x56,0x48,0x09,0x88,0x1E,
++    0xC2,0x9C,0x80,0x00,0x80,0x9C,0x00,0x27,0xC0,0x9C,0x80,0x07,0xF0,0xAF,0x93,0x05,
++    0x80,0x9C,0xF0,0xEC,0x40,0x1D,0x80,0x04,0xC0,0xDC,0x80,0x14,0x40,0xC3,0x81,0x94,
++    0x48,0xC3,0x81,0x8C,0xC2,0x34,0x81,0x01,0x84,0xD4,0xD0,0x03,0x38,0x00,0x86,0x7E,
++    0x40,0xC3,0x83,0x84,0x40,0xC3,0x85,0x7C,0x40,0xC3,0x87,0x74,0xC6,0xD4,0xD0,0x03,
++    0x80,0x5C,0xC0,0xD4,0xD8,0x03,0x80,0x54,0xC2,0xD4,0xD8,0x03,0x80,0x4C,0x00,0x0F,
++    0x00,0x01,0x80,0x84,0xC0,0x04,0xC9,0xE4,0x80,0xA1,0xC1,0x40,0x80,0x0C,0xC0,0xE4,
++    0xCA,0x04,0x01,0x00,0xC5,0x00,0x4A,0xCA,0xC0,0x38,0x02,0x01,0x80,0xC4,0x00,0x09,
++    0x00,0x42,0x85,0xCC,0x00,0x5F,0xC5,0x94,0x38,0x00,0x86,0x0E,0xC0,0xAC,0x00,0x2F,
++    0xC6,0x8C,0x38,0x00,0x80,0x0E,0xC0,0xA4,0x00,0x07,0xC0,0x9C,0x40,0x01,0xE8,0x66,
++    0xD0,0x04,0x08,0x01,0xF0,0x8A,0x4A,0x01,0xEC,0x3E,0x10,0x0A,0xD0,0x06,0x30,0x42,
++    0x40,0x8C,0xD1,0x40,0x91,0x15,0x00,0x94,0x00,0x97,0xD1,0x04,0x0A,0x01,0xF0,0x8A,
++    0x49,0x01,0xD0,0x5E,0x40,0x01,0xD0,0x2E,0x10,0x0A,0xEC,0x06,0x31,0x42,0x40,0x8C,
++    0xD1,0x40,0x00,0x84,0x15,0x01,0xF0,0x92,0xC6,0x84,0x38,0x00,0x80,0x06,0xC1,0x14,
++    0xC4,0x0B,0xD0,0x40,0x90,0x05,0xD8,0x74,0x38,0xD8,0x86,0x36,0xDC,0x4C,0x10,0xC2,
++    0xE8,0xB6,0xC0,0x4C,0xD1,0x40,0x00,0x84,0x00,0x97,0xD8,0x7C,0x38,0xD8,0x86,0x36,
++    0xDC,0x54,0x10,0xC2,0xE8,0x66,0xC0,0x54,0xD1,0x40,0x00,0x84,0x00,0x47,0xD8,0x5C,
++    0x10,0xC2,0xEC,0x2E,0xC0,0x5C,0xD0,0x40,0x00,0x84,0x01,0x0F,0x15,0x01,0xF0,0x92,
++    0xC0,0x0C,0xC0,0x03,0xD0,0x00,0x94,0x05,0xC8,0xF4,0x48,0x01,0x88,0x06,0xC9,0xBC,
++    0x10,0x42,0xDC,0xAE,0x40,0x03,0xC9,0xCC,0x18,0x09,0x18,0x42,0x00,0x03,0x69,0x01,
++    0x83,0x26,0xF0,0x48,0x34,0xD2,0x00,0x52,0x19,0x82,0x00,0x03,0xC4,0x64,0x10,0x2A,
++    0x93,0x0E,0xE1,0x40,0x31,0xD2,0x40,0x0B,0x00,0x12,0x1C,0x8A,0x00,0x0B,0x01,0xD7,
++    0xCC,0xB4,0x10,0x42,0xE1,0xBE,0x40,0x03,0xC8,0xCC,0x18,0x42,0x00,0x03,0x01,0x97,
++    0xC0,0xF4,0x40,0x09,0x89,0x16,0x40,0x84,0x00,0xC4,0x01,0x67,0x41,0xC4,0x41,0x8C,
++    0xC4,0x00,0x92,0x05,0x00,0xC4,0xC9,0xD4,0xD0,0xF4,0xC0,0x4B,0x10,0x8A,0x8C,0x16,
++    0x85,0x07,0xE8,0x87,0x00,0x84,0xC9,0x14,0x40,0x84,0x81,0x43,0xE0,0xF8,0xC5,0x0C,
++    0xE0,0x00,0x82,0x0C,0xE0,0xB0,0xC5,0x14,0xE0,0x00,0x82,0x14,0xC4,0x04,0xE0,0x00,
++    0x80,0x04,0xC0,0x94,0x40,0x00,0x82,0x94,0xC2,0x8C,0x40,0x00,0x80,0x8C,0xC0,0x84,
++    0x40,0x01,0x80,0x46,0xC2,0x84,0x40,0x00,0x80,0x84,0xC0,0x7C,0x40,0x00,0x82,0x7C,
++    0xC2,0x74,0x40,0x00,0x80,0x74,0xC0,0xC4,0xE2,0x00,0x92,0x05,0x80,0xC4,0xC8,0x6C,
++    0xC4,0xC4,0x10,0x42,0xD2,0x06,0x38,0x77,0x87,0x0D,0xE9,0x85,0xA8,0x85,0x37,0x6A,
++    0xF0,0x2C,0x30,0x22,0x30,0x8A,0x30,0xFA,0x37,0xC2,0xB9,0xF7,0xF1,0x5F,0x30,0xDA,
++    0x31,0x92,0x31,0x4A,0x37,0x02,0xB9,0xFF,0xDF,0xB7,0xE9,0x85,0xAC,0xBD,0x87,0x45,
++    0x33,0x6A,0xD8,0x43,0x87,0x24,0xD0,0x43,0x85,0x1C,0xE0,0x43,0x40,0x29,0x90,0x2E,
++    0x06,0x01,0x18,0x02,0x18,0x43,0x03,0x01,0x18,0x43,0x05,0x6F,0x02,0x89,0xEE,0x02,
++    0x38,0x00,0xAA,0x26,0x4D,0x52,0x5A,0x43,0x1B,0x42,0x18,0x43,0x02,0x27,0x48,0x42,
++    0x5E,0x43,0x1D,0x4A,0x1B,0x42,0x18,0x43,0x39,0x01,0x30,0x42,0x80,0x01,0x85,0x3C,
++    0xC0,0x01,0x83,0x34,0x00,0xD7,0x03,0x01,0x1B,0x43,0x5F,0x73,0x20,0x01,0x00,0x17,
++    0x43,0xB0,0xE3,0x20,0x97,0x25,0x3F,0x80,0x88,0x16,0xC0,0x24,0x17,0x22,0x9C,0xBE,
++    0xC4,0x24,0x10,0x22,0x87,0xDE,0xA3,0x63,0xC1,0x44,0x08,0xE9,0xCA,0x00,0x08,0x48,
++    0xC1,0x00,0x4A,0xC2,0xEE,0x03,0x08,0x43,0x30,0x12,0x09,0x01,0x00,0x09,0xD8,0x54,
++    0xBC,0xF7,0xF7,0x8F,0xD0,0x54,0x90,0x04,0x31,0x5A,0x31,0x0A,0x00,0x11,0xD0,0x44,
++    0xBE,0xF7,0xF7,0xFF,0x42,0x82,0x41,0x0B,0x3F,0x48,0xAA,0xE6,0x40,0x0B,0x10,0x11,
++    0x18,0x8A,0x00,0x0B,0x40,0x5A,0x09,0x41,0x00,0x0B,0x44,0x0B,0x10,0xF9,0x97,0x19,
++    0x18,0x8A,0x00,0x0B,0x78,0x01,0x88,0x2E,0x30,0x4A,0xC1,0x44,0xB9,0xFF,0xDF,0x3F,
++    0x00,0x01,0x80,0x14,0xC3,0x1C,0x18,0x02,0x00,0x08,0xC2,0x44,0xC6,0x40,0x08,0x09,
++    0x02,0x48,0xC4,0x00,0x81,0x2C,0x00,0x47,0xC6,0x3C,0xE8,0x03,0x40,0x31,0x88,0x36,
++    0x48,0xE2,0x40,0x43,0x10,0x81,0x18,0x82,0x00,0x43,0x38,0x31,0x07,0x07,0x39,0x80,
++    0x80,0x9E,0x08,0x09,0x00,0x0A,0x05,0x07,0xFF,0x85,0x59,0x43,0x10,0x42,0x88,0x1E,
++    0xC6,0x3C,0xE8,0x03,0x47,0x31,0x88,0xBE,0x50,0x15,0xA8,0x04,0x91,0x0C,0x30,0x12,
++    0x30,0xCA,0xD9,0x44,0xC7,0x2C,0xB8,0xFF,0xE8,0x17,0xC7,0x1C,0xCA,0x2C,0x00,0x00,
++    0xC0,0x00,0x82,0x2C,0x43,0xB0,0xE3,0x20,0x90,0x25,0xC7,0x24,0x16,0x22,0x9C,0x9E,
++    0x78,0x01,0x88,0x0E,0xC3,0x14,0x18,0x43,0xE7,0xF8,0x93,0xFD,0xC0,0x34,0xC0,0x03,
++    0xE5,0x00,0x12,0xC2,0xCB,0x5E,0x38,0xF7,0x58,0x80,0x04,0x01,0x20,0x20,0x07,0x00,
++    0xAA,0xAA,0xAA,0xAA,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0x39,0xFF,0x37,0x52,
++    0x00,0x01,0xC8,0x54,0xBC,0xF7,0xEF,0x27,0x87,0x5D,0xE8,0x85,0xAC,0xBD,0x87,0x2D,
++    0x33,0x62,0xD8,0x03,0x87,0x14,0xD0,0x0B,0x88,0x0C,0xC8,0x0C,0xC2,0x14,0x18,0x42,
++    0xCA,0x2C,0x00,0x10,0xC6,0x90,0x0A,0x09,0x02,0x48,0xC4,0xA8,0xA8,0x24,0xC8,0x2C,
++    0x8A,0xA1,0xC1,0x30,0xCF,0x2C,0x88,0xF9,0x8A,0x29,0xC1,0x38,0xB8,0x1C,0xC8,0x2C,
++    0xC0,0x14,0xC0,0x40,0x0A,0xE9,0x09,0x48,0xC0,0x00,0xEA,0x03,0x4E,0xFA,0x0F,0x43,
++    0xD0,0x3C,0x90,0x04,0x30,0x1A,0x09,0x01,0x00,0x09,0xD0,0x2C,0xBA,0xF7,0xF7,0x4F,
++    0x30,0x12,0x01,0x11,0xCF,0x3C,0xB8,0xF7,0xE8,0x9F,0x0A,0x01,0x00,0x09,0xD8,0x3C,
++    0xD7,0x14,0xB8,0xF7,0xE8,0x47,0xD7,0x3C,0x91,0x04,0x30,0x1A,0x00,0x11,0xD0,0x2C,
++    0xCF,0x14,0xB8,0xF7,0xF0,0xB7,0xD1,0x3C,0x92,0x04,0x00,0x29,0xE9,0x0A,0x30,0x1A,
++    0x11,0x01,0x30,0x42,0xBF,0xFF,0xF7,0x97,0x08,0x09,0x30,0x42,0xD8,0x3C,0xD0,0x14,
++    0xBE,0xF7,0xEF,0x8F,0xD0,0x3C,0x90,0x04,0x30,0x1A,0x01,0x19,0xD0,0x2C,0xC8,0x14,
++    0xB8,0xF7,0xF7,0xFF,0x30,0x12,0x01,0x01,0xCF,0x3C,0xB8,0xF7,0xE8,0x4F,0xD1,0x3C,
++    0x90,0x04,0x08,0x01,0x30,0x1A,0x31,0x42,0xD7,0x2C,0xB8,0xF7,0xF5,0x97,0xE0,0x03,
++    0x40,0x29,0xC0,0x96,0x00,0x01,0x08,0x01,0x05,0x67,0xD8,0x13,0x10,0x12,0xC4,0x06,
++    0x01,0x4C,0x41,0x54,0x81,0x93,0x41,0x54,0x83,0xD3,0xE1,0xF8,0xE5,0xB0,0xE3,0x68,
++    0xE6,0x00,0x92,0x05,0xD4,0x0C,0x10,0x82,0x98,0x7E,0xCF,0x1C,0xC0,0x24,0x10,0x01,
++    0x00,0x57,0x40,0x1C,0xC2,0x6B,0xC8,0xD8,0x92,0xDD,0x80,0xD8,0x00,0x1C,0x80,0x5B,
++    0xE4,0x48,0xE2,0x00,0xE6,0x90,0x92,0x95,0xDC,0x1B,0x15,0x9A,0xC0,0x8E,0x87,0x45,
++    0xEB,0x85,0xAF,0x85,0x35,0x42,0x80,0xC1,0x34,0x6A,0xA8,0x01,0x5F,0x53,0x51,0x73,
++    0x53,0x5B,0x55,0x63,0xE0,0x6B,0x69,0x01,0x81,0xD6,0x32,0x2A,0x19,0xEA,0x18,0xAA,
++    0x18,0xAA,0x80,0x0E,0x28,0x19,0x80,0x2B,0xC0,0x2B,0x68,0x01,0x83,0x0E,0xF0,0x68,
++    0x81,0x2B,0x30,0x2A,0x10,0xAA,0x80,0x26,0x30,0xEA,0x10,0xAA,0x88,0x0E,0x10,0x09,
++    0x01,0x97,0x30,0x2A,0x10,0xAA,0x81,0x26,0x30,0xEA,0x10,0xAA,0x88,0x0E,0x10,0x11,
++    0x00,0x57,0x60,0x01,0x80,0x1E,0x10,0x9A,0x88,0x0E,0x10,0x79,0x01,0x27,0x10,0x9A,
++    0x80,0x0E,0x10,0x21,0x00,0x07,0x10,0x01,0xC8,0x1B,0x24,0x01,0x10,0x9A,0x8C,0x0E,
++    0x50,0x01,0x88,0x0E,0x01,0x24,0x04,0x57,0x40,0x1C,0x2C,0xC9,0x0D,0x68,0x13,0x5A,
++    0x92,0x0E,0xE0,0xD8,0x00,0x1C,0x34,0x5A,0x2D,0x09,0x98,0x01,0x50,0x11,0x80,0x26,
++    0xE0,0x8E,0x50,0x01,0x80,0xDE,0x50,0x09,0x8C,0xCE,0x40,0x34,0x70,0xE1,0xC9,0xB6,
++    0xF0,0xDB,0x5A,0x51,0x90,0x9E,0x30,0x5A,0x98,0x01,0xE6,0xF3,0x18,0x72,0xA1,0xF3,
++    0xA4,0x6B,0x04,0x24,0x00,0x5F,0x50,0x21,0x80,0x4E,0x50,0x79,0x8C,0x3E,0x40,0x34,
++    0x70,0xE1,0xC9,0x26,0xF0,0xDB,0x5A,0x51,0x94,0x0E,0xA0,0x6B,0x04,0x24,0x8C,0x13,
++    0xEF,0x85,0xAB,0x9D,0x80,0x4D,0x34,0x32,0xC4,0x54,0xD0,0x03,0x80,0x3C,0xC0,0x54,
++    0xD0,0x03,0x86,0x34,0xC0,0x54,0xE8,0x03,0x43,0xF1,0x98,0x8E,0xC5,0x54,0x80,0x01,
++    0xF0,0x03,0x40,0x01,0x88,0x66,0xC3,0x54,0xCA,0x03,0x34,0x00,0x70,0x00,0x80,0x2C,
++    0x04,0x09,0x06,0x00,0xC1,0xB8,0x31,0xA2,0xA1,0xA1,0x01,0x81,0xF7,0x82,0x41,0x81,
++    0xDF,0x26,0xC0,0x81,0x30,0x84,0x01,0x09,0x80,0x24,0x00,0x0F,0x00,0x01,0x80,0x24,
++    0x01,0x91,0xF1,0x82,0x0E,0x79,0x1F,0x4A,0x10,0x42,0xE4,0x26,0x83,0x81,0x37,0x84,
++    0x00,0x09,0x80,0x1C,0x00,0x0F,0x00,0x01,0x83,0x1C,0x40,0xEA,0x82,0x14,0x10,0x02,
++    0x80,0x0C,0x00,0x01,0x81,0x44,0x00,0xBF,0x29,0x01,0x00,0x77,0x01,0x01,0xF0,0xC2,
++    0xCC,0x2C,0x10,0x42,0xD0,0xCE,0x40,0x01,0xE8,0x56,0xC8,0x14,0x10,0x42,0xEC,0x06,
++    0x80,0x14,0xC0,0x24,0x40,0x01,0x80,0xE6,0xC2,0x03,0xF1,0x00,0x80,0x03,0x01,0xC7,
++    0x40,0x01,0xD0,0xB6,0xCC,0x0C,0x10,0x42,0xD0,0x06,0x80,0x0C,0xC0,0x1C,0x40,0x01,
++    0x81,0x7E,0xC0,0x03,0xE1,0x00,0x82,0x03,0x00,0x5F,0xC0,0x54,0x08,0x21,0xEB,0x03,
++    0x83,0x07,0xD8,0x47,0x48,0x19,0x8B,0x26,0xC9,0x2C,0xC0,0x03,0x42,0x48,0xD2,0x00,
++    0x85,0x03,0xE1,0xF8,0xE3,0x20,0xE3,0x68,0x90,0x6D,0xC7,0x34,0x16,0x2A,0x9C,0x6E,
++    0xC2,0x44,0xE0,0x00,0x90,0x05,0x86,0x44,0xC8,0x3C,0xC0,0x44,0x16,0x42,0x9C,0x1E,
++    0x70,0x8C,0xC1,0x14,0xC1,0x40,0x30,0x84,0x70,0x8C,0xC3,0x0C,0xC3,0x40,0x30,0x84,
++    0x37,0x57,0xAC,0xBD,0x80,0x15,0x34,0x62,0x37,0xBA,0xE0,0x2B,0xDF,0x33,0xD3,0x03,
++    0x1A,0x42,0x03,0x08,0xC0,0x14,0xC0,0x40,0x0C,0x09,0x06,0x48,0xC0,0x00,0x82,0x0C,
++    0x36,0x02,0x81,0x01,0xE4,0x0B,0x10,0x01,0x18,0x8A,0xA0,0x0B,0x00,0xB1,0xED,0x02,
++    0x42,0x01,0x80,0x46,0x09,0x09,0x30,0xDA,0x30,0x52,0x31,0x42,0xBC,0xF7,0xE7,0x5F,
++    0x30,0x1A,0xB9,0x04,0x08,0x01,0x00,0x19,0xD7,0x14,0xB8,0xF7,0xE2,0xD7,0x06,0x29,
++    0xE9,0x0A,0x30,0x1A,0x30,0xD2,0xC1,0x0C,0xBE,0xFF,0xC7,0xEF,0x58,0x03,0x17,0x09,
++    0x35,0x8A,0x00,0x4A,0x1F,0x42,0x18,0x03,0xE7,0x68,0x93,0x6D,0x58,0x0B,0x03,0x0F,
++    0xE7,0x68,0x93,0x6D,0x35,0x82,0x00,0x42,0x10,0x0A,0x88,0x0E,0x17,0xAA,0x9D,0xBE,
++    0x11,0xAA,0x85,0x06,0xA1,0x2B,0x37,0xDA,0x30,0x52,0x09,0x01,0x07,0x09,0xB8,0xF7,
++    0xE1,0x17,0x33,0x1A,0xB9,0x04,0x30,0x4A,0x00,0x11,0xD0,0x14,0xBD,0xF7,0xE7,0x8F,
++    0xC1,0x14,0x08,0xE9,0xCA,0x00,0x0A,0x48,0xC1,0x00,0x52,0x62,0xEE,0x03,0x08,0x83,
++    0x42,0x62,0x41,0x0B,0x3F,0x48,0xAA,0xE6,0x04,0x41,0x00,0x83,0x47,0x83,0x08,0xF9,
++    0x88,0x19,0x18,0x42,0x00,0x83,0x80,0x2D,0xEF,0x85,0xAF,0x85,0x84,0xBD,0x34,0x22,
++    0x37,0x6A,0xD0,0x7B,0xD0,0x43,0x85,0x6C,0x31,0x1A,0x9B,0xA1,0x9C,0xB4,0x08,0x29,
++    0x34,0x02,0x03,0x48,0xC6,0x20,0x0A,0x09,0x03,0x48,0x24,0x0A,0x8B,0xAC,0xC8,0x43,
++    0x02,0x00,0x92,0x05,0x80,0x2C,0x00,0x01,0x80,0x24,0x00,0x09,0x81,0x14,0x30,0x42,
++    0x80,0x01,0x86,0xA4,0xE3,0x03,0x5A,0x73,0x32,0x32,0x3C,0x10,0x58,0x43,0x1D,0x32,
++    0x50,0x01,0xD0,0x46,0x40,0xA2,0x18,0x32,0xB3,0x1C,0x30,0x82,0x10,0xD9,0x07,0x82,
++    0xD2,0xA4,0xA0,0x83,0x00,0x47,0x40,0x82,0x18,0x02,0x1E,0x32,0xB3,0x1C,0x30,0x82,
++    0x10,0x21,0x18,0x82,0xD2,0xA4,0xA0,0x83,0x35,0x01,0x18,0x73,0xD8,0x43,0x45,0x01,
++    0x80,0x36,0xD0,0x6C,0xC2,0x14,0xF0,0x90,0x00,0x82,0xD4,0x1C,0x18,0x82,0x80,0x1C,
++    0x34,0x52,0x91,0x01,0x92,0x9C,0xF0,0x83,0x80,0x8C,0x00,0x3F,0x00,0x01,0x00,0x42,
++    0xC7,0x87,0xF9,0xFF,0x18,0x00,0x04,0x42,0xAA,0xAA,0xAA,0xAA,0xC0,0x9C,0x10,0xC1,
++    0xB0,0x12,0x94,0x84,0xD0,0x9C,0x00,0x01,0x18,0x83,0x80,0x7C,0xD6,0x9C,0x10,0x83,
++    0x80,0x74,0x10,0x01,0x97,0x64,0x50,0xFA,0x90,0x5C,0x10,0x01,0x91,0x54,0x30,0x72,
++    0xB5,0x01,0x99,0x83,0xCA,0x43,0x45,0x00,0x85,0x4C,0x10,0xA1,0xFA,0x82,0x82,0x00,
++    0x85,0x44,0xE0,0x43,0x40,0x29,0xC0,0xCE,0x03,0x01,0x30,0x12,0x32,0x84,0x30,0x84,
++    0x30,0x22,0x04,0x87,0x10,0x01,0x00,0x47,0x41,0x44,0x80,0x03,0x40,0x44,0x80,0xC3,
++    0xE4,0xD8,0xE2,0x48,0xE2,0x20,0xE3,0x90,0x95,0x95,0x12,0xD2,0xDB,0xA6,0x37,0x02,
++    0xE2,0x00,0x92,0x05,0x30,0x22,0xC4,0x6C,0x2F,0x22,0xDC,0x5E,0xC0,0xB4,0x80,0x3C,
++    0xE0,0xAC,0x00,0x01,0x85,0x94,0x00,0xBF,0x00,0x01,0x80,0x34,0x30,0x32,0xCC,0x94,
++    0xC4,0x14,0x00,0x42,0xC8,0x1C,0x10,0x42,0x80,0x86,0x03,0x01,0x32,0x22,0x04,0xEF,
++    0xC1,0x3C,0x40,0x0C,0xC2,0x03,0xD0,0x00,0x91,0x05,0x00,0x04,0xCA,0x9C,0xE0,0x4B,
++    0x48,0x11,0x98,0xA6,0xCC,0x84,0x10,0x42,0xD5,0x8E,0xD8,0x8B,0xE5,0x48,0x9A,0x8B,
++    0xC8,0x64,0xC0,0x48,0x88,0x64,0xD8,0x5C,0x34,0x12,0x10,0x1A,0xD8,0x06,0xD0,0x5C,
++    0x90,0x5C,0xD8,0x54,0x34,0x12,0x10,0x1A,0xE0,0x06,0xD0,0x54,0x90,0x54,0xC8,0x2C,
++    0x10,0x42,0xD4,0x3E,0x32,0x8A,0xE3,0x48,0x94,0x4D,0x36,0x72,0xC8,0x34,0xC0,0x48,
++    0x90,0x4D,0x88,0x34,0xCC,0x4C,0x10,0x42,0xEB,0xBE,0xC8,0x4B,0x10,0x0A,0xE4,0x2E,
++    0xDD,0x94,0x58,0x53,0x0C,0x09,0x00,0xCA,0x1D,0x52,0x18,0x53,0xE0,0x8B,0x4B,0x09,
++    0x8C,0x0E,0x08,0x09,0xA0,0x8B,0xCB,0x8C,0x10,0x42,0xEC,0xBE,0x30,0x02,0x0B,0x09,
++    0x00,0x0A,0xC4,0x7C,0x18,0x0A,0x88,0x7C,0x00,0x87,0xC8,0x44,0x10,0x42,0xD4,0x6E,
++    0xE0,0x8B,0x4B,0x09,0x8C,0x0E,0x08,0x09,0xA0,0x8B,0xCB,0x84,0x10,0x42,0xD4,0x2E,
++    0x30,0x02,0x0B,0x09,0x00,0x0A,0xC4,0x74,0x18,0x0A,0x88,0x74,0xE0,0x20,0xC5,0x3C,
++    0xE0,0x00,0x82,0x3C,0x32,0x02,0xE3,0x00,0x94,0x05,0x32,0x22,0x2C,0xE2,0xDD,0xFE,
++    0x30,0x82,0x43,0x11,0xCB,0x2E,0x30,0x8A,0xC0,0x34,0x80,0x07,0xC8,0x6F,0x97,0x05,
++    0x00,0x07,0x00,0x01,0x03,0xC8,0xD3,0x20,0x11,0x01,0x00,0x57,0x00,0x67,0x41,0x01,
++    0xE8,0x7E,0x08,0x01,0xF0,0x0A,0xDB,0x2C,0x10,0xCA,0xD4,0xB6,0xE4,0x18,0x12,0xCA,
++    0xE8,0x16,0xD0,0x48,0x00,0x0C,0x01,0x87,0x48,0x01,0xE8,0x76,0x09,0x09,0x00,0x0C,
++    0x00,0x5F,0x08,0x01,0xF4,0x0A,0x13,0x0A,0xD0,0x16,0xD0,0x48,0x00,0x0C,0x01,0x27,
++    0x48,0x01,0xD0,0x16,0x0E,0x01,0x18,0x4A,0x00,0x0C,0x09,0x01,0xF0,0x0A,0xDB,0x44,
++    0x10,0xCA,0xD4,0x1E,0xCA,0x24,0xE0,0x48,0x90,0x4D,0x8E,0x24,0xE2,0x20,0xE5,0x90,
++    0x95,0x95,0x12,0xD2,0xD8,0x9E,0x06,0x5F,0x00,0x01,0x08,0x01,0x01,0x37,0x00,0x0C,
++    0xE0,0x20,0xD5,0x3C,0xE0,0x90,0x92,0x3C,0xE2,0x00,0x92,0x05,0x17,0xC2,0xDD,0xB6,
++    0xC2,0x94,0xE0,0x00,0x90,0x05,0x82,0x94,0xC8,0x6C,0xC0,0x94,0x10,0x42,0xD4,0x06,
++    0x39,0x17,0xCA,0x43,0x40,0x71,0xC9,0x0E,0x01,0x71,0x89,0x43,0xC9,0x24,0xC8,0x43,
++    0x42,0x48,0xC4,0x00,0x91,0x05,0x8E,0x43,0x40,0x81,0xCA,0x0E,0x01,0x81,0x8A,0x43,
++    0xC2,0x9C,0xE0,0x03,0x42,0x11,0x98,0x56,0xD8,0x83,0x45,0x11,0xCC,0x3E,0xF2,0x00,
++    0x90,0x05,0x86,0x04,0xC8,0x54,0xC0,0x5C,0xC0,0x08,0xC2,0x64,0xD0,0x00,0xCA,0x04,
++    0x84,0x07,0xC8,0x17,0x90,0x05,0x80,0x0C,0x05,0x01,0x28,0x44,0x08,0xE9,0x0B,0x48,
++    0x10,0x01,0xE0,0xAC,0x31,0x22,0x04,0x0F,0x18,0x01,0x00,0xCF,0x01,0x01,0xF0,0x02,
++    0xF5,0x84,0x10,0x82,0xD0,0x8E,0xF0,0x0C,0xD8,0x00,0xAC,0x06,0x10,0x02,0x92,0x05,
++    0x34,0x32,0x10,0x0A,0xE0,0x06,0x30,0x72,0x30,0x8A,0x31,0x32,0x10,0x12,0xDC,0x06,
++    0x31,0xB2,0x30,0x92,0x69,0x74,0xC5,0x80,0x2D,0x44,0xE5,0x20,0xE2,0xD8,0x92,0xDD,
++    0x17,0xDA,0xDD,0x1E,0x32,0x02,0xE3,0x00,0x94,0x05,0x32,0x22,0xDC,0x6C,0x28,0xE2,
++    0xDD,0xD6,0x6E,0x44,0xC2,0x48,0xD4,0x00,0x90,0x05,0xCC,0x04,0x82,0x07,0xC8,0x17,
++    0x28,0x44,0xC5,0x0C,0x40,0x01,0xD0,0x06,0x13,0x02,0x2A,0x44,0x00,0x17,0x00,0x01,
++    0x2D,0x44,0x2B,0x44,0xC8,0x9C,0xC0,0x7C,0x18,0x43,0xC8,0x9C,0xC6,0x74,0x10,0x43,
++    0x87,0xBD,0xE8,0x85,0xAC,0xBD,0x87,0x15,0x32,0x62,0x70,0x9A,0x29,0x01,0x80,0xAB,
++    0x09,0x11,0x30,0x02,0x80,0x01,0x35,0x3A,0xA9,0x0B,0x34,0x0A,0xD0,0x24,0xC0,0x14,
++    0xBD,0xFF,0xDF,0x67,0xAD,0xEB,0xDD,0x03,0x40,0x01,0x80,0x76,0x6F,0x5A,0x42,0x43,
++    0x91,0x3D,0x4C,0x04,0x00,0x43,0x07,0x09,0x81,0x83,0x31,0x0A,0xD0,0x24,0xC0,0x14,
++    0xBA,0xFF,0xE7,0xA7,0x01,0x01,0x80,0x83,0x00,0x7B,0xD7,0x24,0x90,0x04,0x08,0x01,
++    0x30,0x1A,0x31,0x42,0xD7,0x14,0xB8,0xF7,0xD5,0xE7,0xE5,0x03,0x40,0x41,0x96,0x0E,
++    0xE5,0x00,0xA2,0x03,0x30,0xBF,0x10,0x01,0x00,0x37,0x08,0x01,0xE4,0x48,0x92,0x4D,
++    0x4F,0xA1,0xC8,0xDE,0xE4,0x90,0x92,0x95,0x17,0x12,0xCC,0xB6,0x38,0x82,0x3B,0x18,
++    0x78,0xD8,0x10,0x09,0x06,0xD2,0x94,0x95,0x18,0xF9,0x0F,0xD8,0x01,0xC2,0x58,0xA2,
++    0xC0,0x00,0x4E,0x09,0x88,0x66,0x40,0x0B,0x18,0x8A,0x04,0x0B,0x44,0x0B,0x1A,0x8A,
++    0x04,0x0B,0x42,0x0B,0x1C,0x8A,0x04,0x0B,0x44,0x0B,0x1E,0x8A,0x03,0x0B,0x3E,0x82,
++    0x48,0x01,0x88,0x66,0x44,0x0B,0x1A,0x8A,0x04,0x0B,0x42,0x0B,0x1C,0x8A,0x04,0x0B,
++    0x44,0x0B,0x1E,0x8A,0x00,0x0B,0x46,0x0B,0x18,0x8A,0x00,0x0B,0x38,0x82,0x4B,0x11,
++    0x88,0x66,0x40,0x0B,0x18,0x8A,0x04,0x0B,0x44,0x0B,0x1A,0x8A,0x04,0x0B,0x42,0x0B,
++    0x1C,0x8A,0x04,0x0B,0x40,0x0B,0x1E,0x8A,0x03,0x0B,0x3E,0x82,0x4F,0x19,0x88,0xE6,
++    0x44,0x0B,0x18,0x8A,0x04,0x0B,0x40,0x0B,0x1C,0x8A,0x04,0x0B,0x44,0x0B,0x1E,0x8A,
++    0x02,0x0B,0x46,0x0B,0x1A,0x8A,0x00,0x0B,0x3F,0x82,0xAB,0x8D,0x80,0x3D,0xC4,0x3C,
++    0xC8,0x3C,0x48,0x00,0x02,0x00,0xC4,0x00,0x38,0x00,0x48,0x92,0x72,0x00,0xC2,0x28,
++    0x40,0x72,0x40,0x0B,0x90,0x4D,0x8C,0x34,0x5C,0x0B,0x90,0x4D,0x8A,0x2C,0x58,0x0B,
++    0x90,0x4D,0x8C,0x24,0x5C,0x0B,0x94,0x4D,0x8E,0x1C,0x50,0x0B,0x90,0x75,0x4C,0x52,
++    0x44,0x53,0x92,0x95,0x90,0x14,0x40,0x53,0x92,0xBD,0x44,0x13,0x90,0x95,0x94,0x0C,
++    0x58,0x12,0x00,0x5F,0xE7,0xC7,0xF8,0xFF,0x00,0xB0,0x00,0x01,0x00,0x01,0x00,0x42,
++    0x80,0x00,0x00,0x42,0x08,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0x98,0x01,0x52,0xD3,
++    0x90,0x95,0x94,0x04,0x10,0x09,0x00,0x13,0xA8,0x10,0x1C,0x13,0x12,0x81,0x18,0x13,
++    0x18,0x13,0x14,0x79,0x11,0x13,0x16,0x01,0x00,0x53,0x12,0x89,0x02,0x53,0x40,0x0B,
++    0x10,0x81,0x19,0x8A,0x07,0x0B,0x02,0xF9,0x80,0x89,0x17,0xC3,0x07,0x09,0xB8,0xFF,
++    0xFF,0x17,0x03,0xF9,0x80,0x89,0x14,0xC3,0x07,0x09,0xB8,0xFF,0xF8,0xE7,0x02,0x19,
++    0x11,0x00,0x00,0x43,0x07,0x09,0xB8,0xFF,0xF8,0xB7,0x0A,0x11,0xC7,0x3C,0xB8,0xFF,
++    0xF8,0xF7,0x22,0xA1,0x01,0x01,0x40,0x4B,0x30,0x48,0xA8,0x16,0xE7,0x20,0x93,0x25,
++    0x03,0x0F,0xF0,0x20,0x92,0x25,0xE7,0x00,0x90,0x05,0x46,0x51,0x98,0x9E,0x0F,0x09,
++    0xC7,0x3C,0xB8,0xFF,0xF8,0x67,0x42,0x6A,0xC8,0x34,0x00,0x0B,0xC8,0x2C,0x18,0x0B,
++    0xCA,0x24,0x18,0x0B,0xCC,0x1C,0x18,0x0B,0x10,0x33,0x4E,0x4A,0xD2,0x14,0x00,0x53,
++    0x00,0x7B,0xC8,0x0C,0x00,0x0B,0x4A,0x2A,0xC2,0x04,0x88,0x01,0x10,0x43,0x60,0xA1,
++    0xC8,0x16,0x00,0x09,0x87,0x45,0xE8,0x85,0x07,0x01,0x38,0xDF,0x00,0x01,0x00,0x42,
++    0x18,0x00,0x04,0x42,0x00,0x0F,0x00,0x26,0xF8,0x48,0x48,0x21,0x94,0xDE,0x3F,0x58,
++    0xA8,0x0E,0x00,0x14,0xE6,0x00,0x3C,0x48,0x80,0x06,0x80,0x13,0x38,0x82,0x4B,0x01,
++    0x86,0x5E,0x38,0x18,0x80,0x16,0x80,0x13,0xE2,0x00,0xF2,0x48,0x48,0x11,0x98,0x26,
++    0x38,0x18,0xAC,0x16,0x04,0x14,0xE0,0x00,0xF7,0x48,0x3C,0x1F,0x17,0x01,0x38,0x77,
++    0x16,0x01,0x38,0xFF,0x10,0x01,0x48,0x18,0x11,0x5A,0x9C,0x66,0x54,0x18,0x10,0x5A,
++    0x98,0x8E,0x18,0x01,0x32,0xE2,0x04,0x77,0x30,0x1A,0x18,0x5A,0xA0,0xE6,0x11,0x01,
++    0x44,0x18,0x12,0x5A,0x98,0x8E,0x49,0x18,0x10,0x5A,0x9C,0xE6,0x54,0x18,0x10,0x5A,
++    0x9C,0x0E,0x30,0xA2,0x06,0xFF,0x49,0x18,0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD6,0x00,
++    0x0C,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD4,0x00,0x0A,0x92,0x4A,0x18,
++    0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD2,0x00,0x08,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,
++    0x0E,0x58,0xD0,0x00,0x0E,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD6,0x00,
++    0x0C,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD4,0x00,0x0A,0x92,0x42,0x18,
++    0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD2,0x00,0x0A,0x92,0xD2,0x08,0x90,0x06,0x30,0x0A,
++    0x08,0x92,0x32,0x82,0x3A,0x82,0x03,0xEF,0x78,0x50,0x86,0x06,0x10,0x4A,0x82,0x18,
++    0x9A,0x06,0x10,0x02,0x00,0x9A,0x12,0x01,0x30,0xE2,0x4C,0x18,0x11,0x5A,0x9C,0x6E,
++    0x54,0x18,0x10,0x5A,0x9F,0x96,0x10,0xE1,0x08,0x48,0xD4,0x95,0x54,0x18,0x10,0x5A,
++    0x9C,0x66,0x08,0x48,0x8C,0x90,0x14,0x5A,0x9C,0x46,0x08,0x48,0x8C,0x90,0x14,0x5A,
++    0x9C,0x26,0x08,0x48,0x84,0xD6,0x89,0x90,0x04,0x07,0x48,0x48,0x4C,0x18,0x16,0x5A,
++    0x9E,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,0x4C,0x18,0x14,0x5A,0x9C,0x0E,0x08,0x58,
++    0xD2,0x00,0x0E,0x92,0x4C,0x18,0x12,0x5A,0x9A,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,
++    0x4C,0x18,0x10,0x5A,0x98,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,0x44,0x18,0x16,0x5A,
++    0x9E,0x0E,0x00,0x58,0xD2,0x00,0x0E,0x92,0x44,0x18,0x14,0x5A,0x9C,0x0E,0x00,0x58,
++    0xD2,0x00,0x0E,0x92,0x92,0xCE,0x46,0x18,0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD2,0x00,
++    0x0A,0x92,0xD2,0x08,0x90,0x06,0x30,0x0A,0x32,0x1A,0x0B,0x92,0x80,0xD8,0x32,0x82,
++    0x9A,0x0E,0x10,0x02,0x58,0x01,0xA8,0x06,0x13,0x4A,0x3A,0x82,0x32,0x1A,0x83,0xD8,
++    0x9A,0x06,0x10,0x02,0xA8,0x0D,0x00,0x01,0x36,0x02,0x36,0x02,0xEB,0x15,0x30,0xAA,
++    0x81,0x07,0xC0,0x17,0x30,0x72,0x05,0x28,0x32,0x4A,0x33,0x9A,0x46,0x00,0x06,0x00,
++    0x30,0x2A,0x84,0xC5,0xAF,0x05,0xB9,0xDF,0xEB,0xBF,0xE6,0x05,0x3A,0x01,0x40,0x48,
++    0x30,0xB2,0x35,0x01,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,
++    0x2E,0x06,0x2E,0x06,0xEA,0x01,0x02,0x48,0x33,0x6A,0x3C,0x82,0x36,0x22,0x30,0x02,
++    0x31,0x02,0x36,0x02,0xB8,0xD7,0xDF,0xFF,0x43,0x02,0x38,0x82,0x58,0x60,0x05,0x01,
++    0x40,0x12,0x48,0x1A,0xF3,0x5D,0x3D,0x82,0x00,0x68,0x00,0x00,0x00,0xC0,0x00,0x00,
++    0x00,0x30,0x01,0x10,0x39,0x82,0xA3,0x85,0x33,0xA2,0xF3,0x20,0xC3,0x2B,0xE1,0x20,
++    0x10,0x5A,0x95,0x06,0x33,0xEA,0xE8,0x1A,0x07,0xD8,0xC2,0x18,0xE0,0x85,0x39,0xC2,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x20,0x01,0x42,
++    0x80,0x20,0x01,0x42,0x80,0x20,0x01,0x42,0x80,0x20,0x01,0x42,0x80,0x20,0x03,0x42,
++    0x80,0xA0,0x00,0x42,0x80,0x20,0x03,0x42,0x80,0xA0,0x00,0x42,0x80,0x20,0x03,0x42,
++    0x80,0xA0,0x00,0x42,0x80,0x20,0x03,0x42,0x80,0xA0,0x00,0x42,0x80,0xA0,0x03,0x42,
++    0x80,0x20,0x00,0x42,0x80,0xA0,0x03,0x42,0x80,0xA0,0x03,0x42,0x80,0x20,0x04,0x42,
++    0x80,0x20,0x04,0x42,0x80,0x20,0x04,0x42,0x80,0xA0,0x04,0x42,0x10,0x20,0x08,0x40,
++    0x40,0x08,0x20,0x10,0x10,0x20,0x08,0x40,0x20,0x08,0x40,0x20,0x20,0x10,0x08,0x40,
++    0x08,0x81,0x03,0x42,0x08,0xC1,0x03,0x42,0x08,0x41,0x00,0x42,0x08,0x81,0x00,0x42,
++    0x08,0xC1,0x00,0x42,0x08,0x01,0x01,0x42,0x08,0x81,0x02,0x42,0x08,0x41,0x02,0x42,
++    0x08,0xC1,0x02,0x42,0x08,0x01,0x02,0x42,0x08,0x01,0x02,0x42,0x08,0xC1,0x01,0x42,
++    0x08,0x41,0x02,0x42,0x08,0x81,0x01,0x42,0x08,0x81,0x02,0x42,0x08,0x41,0x01,0x42,
++    0x08,0xC1,0x02,0x42,0x08,0x01,0x01,0x42,0x08,0x01,0x03,0x42,0x08,0x81,0x00,0x42,
++    0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x00,0x00,
++    0x00,0x08,0xF8,0x0F,0xFF,0x07,0xF8,0xFF,0x07,0xF8,0x0F,0xF8,0x08,0x00,0x08,0x08,
++    0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x28,0xB5,0x39,0xC5,0x08,0x1D,
++    0x1B,0x2B,0x3A,0x28,0x53,0xB5,0x0A,0xC5,0x00,0x08,0x01,0x00,0x01,0x00,0x50,0x0D,
++    0x52,0x1D,0x52,0xB5,0x39,0x0D,0x04,0x08,0x51,0x3D,0x53,0x1D,0x51,0x3D,0x54,0x95,
++    0x51,0x3D,0x54,0x95,0x51,0x3D,0x54,0x95,0x0B,0x3D,0x34,0x88,0x51,0x3D,0x54,0x1D,
++    0x51,0x3D,0x54,0x95,0x04,0x00,0x50,0x3D,0x50,0x1D,0x01,0x00,0x00,0x00,0x00,0x00,
++    0x54,0x2D,0x53,0x3D,0x32,0x8D,0x32,0x38,0x01,0x28,0x0A,0x45,0x50,0xB5,0x53,0x95,
++    0x00,0x00,0x00,0x00,0x52,0xA5,0x51,0xB5,0x09,0xC5,0x03,0x08,0x03,0x00,0x50,0x3D,
++    0x55,0x1D,0x51,0x0D,0x51,0x3D,0x54,0x95,0x51,0x3D,0x53,0x1D,0x51,0x3D,0x54,0x95,
++    0x51,0x0D,0x55,0x0D,0x54,0xB5,0x3A,0x0D,0x00,0x08,0x01,0x00,0x53,0xA5,0x51,0x2D,
++    0x52,0x3D,0x34,0x8A,0x1D,0x38,0x52,0x45,0x52,0x0D,0x51,0x1D,0x54,0xB5,0x3A,0x0D,
++    0x53,0xA5,0x29,0xB5,0x39,0xC5,0x08,0x1D,0x19,0x2D,0x22,0x1D,0x44,0x0D,0x31,0x3D,
++    0x23,0x95,0x09,0xC1,0x29,0xB5,0x0B,0x1D,0x1B,0x2B,0x3A,0x28,0x00,0x00,0x00,0x08,
++    0xFF,0x07,0x00,0xF8,0x08,0x00,0x10,0x10,0x08,0x10,0x10,0x10,0x08,0x08,0x10,0x08,
++    0x10,0x08,0x10,0x08,0x10,0x10,0x08,0x08,0x10,0x10,0x08,0x08,0x08,0x08,0x10,0x10,
++    0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x08,0xF8,0x07,
++    0x08,0x00,0x08,0x08,0xE8,0xA2,0x01,0x00,0x00,0x00,0x00,0x01,0x00,0xC0,0x00,0x00,
++    0x00,0x00,0x05,0x00,0xE8,0x62,0x02,0x00,0x00,0xC0,0x00,0x01,0x58,0xA0,0x07,0x00,
++    0x00,0xE0,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0x00,0x70,0x00,0x30,0x09,0x40,0x1B,0x00,0x06,0x78,0x50,0x56,
++    0xFF,0xFF,0xFF,0xFF,0x3C,0x50,0x00,0x10,0x00,0x20,0x18,0x00,0x1E,0xAC,0xE4,0x09,
++    0x0F,0x00,0xCA,0xCA,0xFF,0xFF,0xFF,0xFF,0x0A,0x07,0x82,0x00,0x04,0x00,0x00,0x03,
++    0x95,0x83,0xC1,0x3C,0xC8,0xB2,0xB5,0x47
++};
++
++
++
++#define FW_INFO_SIZE	(0x18)
++#define FW_REAL_SIZE	(sizeof(fwbin))
++#define FW_BIN_SIZE		(24*1024+24)	    //24K byte
++
++#endif
++
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Debug_driver/ref_cst3xx_MCU_driver_0729_update2/hyn_cst3xx_0729_update3_firmware.c b/module_drivers/drivers/input/touchscreen/hyn_touch/Debug_driver/ref_cst3xx_MCU_driver_0729_update2/hyn_cst3xx_0729_update3_firmware.c
+new file mode 100644
+index 000000000..7d1b08664
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Debug_driver/ref_cst3xx_MCU_driver_0729_update2/hyn_cst3xx_0729_update3_firmware.c
+@@ -0,0 +1,1626 @@
++/*
++ * cst3xx Touchscreen Controller Driver
++ */
++
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/i2c.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of_gpio.h>
++#include <linux/pm_qos.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include "hyn_cst3xx.h"
++#include "hyn_cst3xx_RS659_fw.h"
++//#include "hyn_cst3xx_RS659_fw_0729_update2.h"
++//#include "hyn_cst3xx_RS659_fw_0729_update3.h"
++#include <soc/gpio.h>
++
++
++#define HYN_DEBUG_EN  1
++
++struct st1615_ts_finger {
++	u16 x;
++	u16 y;
++	u8 t;
++	bool is_valid;
++};
++
++
++static int cst3xx_into_program_mode(struct i2c_client * client);
++static int cst3xx_erase_program_area(struct i2c_client * client);
++static void cst3xx_reset_ic(struct cst3xx_ts_data *ts,unsigned int ms);
++static int cst3xx_write_program_data(struct i2c_client * client,const unsigned char *pdata);
++
++static int cst3xx_check_checksum(struct i2c_client * client);
++
++static int cst3xx_exit_program_mode(struct i2c_client * client);
++
++static int cst3xx_update_firmware(struct cst3xx_ts_data *ts, const unsigned char *pdata);
++
++static int cst3xx_firmware_info(struct i2c_client * client);
++
++static int cst3xx_update_judge( unsigned char *pdata, int strict);
++
++static int cst3xx_boot_update_fw(struct cst3xx_ts_data *ts,  unsigned char *pdata);
++
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_test(struct i2c_client *client);
++static void cst3xx_reset(struct cst3xx_ts_data *ts) ;
++extern  void close_vcc3v3Power(void);
++extern  void open_vcc3v3Power(void);
++
++static unsigned char *pcst3xx_update_firmware = (unsigned char *)cst3_fw ; //the updating firmware
++static unsigned int   g_cst3xx_ic_version  = 0;
++static unsigned int   g_cst3xx_ic_checksum = 0;
++static unsigned int   g_cst3xx_ic_checkcode =0;
++static unsigned int   g_cst3xx_ic_project_id  = 0;
++static unsigned int   g_cst3xx_ic_type  = 0;
++
++static unsigned char  report_flag = 0;
++static unsigned int x_temp_pos = 0;
++static unsigned int y_temp_pos = 0;
++
++#define HYN_DRAW_POINT
++
++//#define USE_ANALOG_I2C     1 //i2c analog -->defconfig i2c.
++#define USE_HIGHEST_I2CA  1// x1000 highest i2c
++//#define USE_LOWEST_I2CA   1 // x1000 lowest i2c
++//#define HYN_UPDATE_FIRMWARE_POWERON_ENABLE
++#define HYN_UPDATE_FIRMWARE_ENABLE
++
++#pragma pack(1)
++typedef struct
++{
++    u16 pid;                 //product id   //
++    u16 vid;                 //version id   //
++} st_tpd_info;
++#pragma pack()
++
++st_tpd_info tpd_info;
++
++#define CST3XX_BIN_SIZE    (24*1024 + 24)
++//#define CST3XX_MAX_X  340
++#define CST3XX_MAX_X  480
++#define CST3XX_MAX_Y  800
++#define ERROR_TOUCH   1
++
++static void cst3xx_ts_power(struct cst3xx_ts_data *ts, bool poweron)
++{
++	if (gpio_is_valid(ts->pdata->reset_gpio))
++		gpio_direction_output(ts->pdata->reset_gpio, poweron);
++}
++
++static int cst3xx_into_program_mode(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[4];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x01;
++	buf[2] = 0xAA;	//set cmd to enter program mode
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0)  return -1;
++
++	mdelay(2);
++
++	buf[0] = 0xA0;
++	buf[1] = 0x02;	//check whether into program mode
++	ret = cst3xx_i2c_read_register(client, buf, 1);
++	if (ret < 0)  return -1;
++
++	if (buf[0] != 0x55) return -1;
++
++	return 0;
++}
++static int cst3xx_erase_program_area(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[3];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x02;
++	buf[2] = 0x00;		//set cmd to erase main area
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0) return -1;
++
++	mdelay(5);
++
++	buf[0] = 0xA0;
++	buf[1] = 0x03;
++	ret = cst3xx_i2c_read_register(client, buf, 1);
++	if (ret < 0)  return -1;
++
++	if (buf[0] != 0x55) return -1;
++
++	return 0;
++}
++
++
++static void cst3xx_reset_ic(struct cst3xx_ts_data *ts,unsigned int ms)
++{
++
++	unsigned char buf[4];
++	buf[0] = 0xD1;
++	buf[1] = 0x0E;
++	cst3xx_i2c_write(ts->client, buf, 2);
++/*
++	gpio_direction_output(ts->pdata->reset_gpio,0);
++	mdelay(2);
++	gpio_direction_output(ts->pdata->reset_gpio,1);
++*/
++	mdelay(ms);
++}
++
++
++static int cst3xx_write_program_data(struct i2c_client * client,
++		const unsigned char *pdata)
++{
++	int i, ret;
++	unsigned char *i2c_buf;
++	unsigned short eep_addr;
++	int total_kbyte;
++
++	unsigned char temp_buf[8];
++	unsigned short iic_addr;
++	int  j;
++
++
++	i2c_buf = kmalloc(sizeof(unsigned char)*(1024 + 2), GFP_KERNEL);
++	if (i2c_buf == NULL)
++		return -1;
++
++	//make sure fwbin len is N*1K
++	//total_kbyte = len / 1024;
++	total_kbyte = 24;
++	for (i=0; i<total_kbyte; i++) {
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x14;
++		eep_addr = i << 10;		//i * 1024
++		i2c_buf[2] = eep_addr;
++		i2c_buf[3] = eep_addr>>8;
++		ret = cst3xx_i2c_write(client, i2c_buf, 4);
++		if (ret < 0)
++			goto error_out;
++
++		memcpy(i2c_buf, pdata + eep_addr, 1024);
++		for(j=0; j<256; j++) {
++			iic_addr = (j<<2);
++    	temp_buf[0] = (iic_addr+0xA018)>>8;
++    	temp_buf[1] = (iic_addr+0xA018)&0xFF;
++		temp_buf[2] = i2c_buf[iic_addr+0];
++		temp_buf[3] = i2c_buf[iic_addr+1];
++		temp_buf[4] = i2c_buf[iic_addr+2];
++		temp_buf[5] = i2c_buf[iic_addr+3];
++    	      ret = cst3xx_i2c_write(client, temp_buf, 6);
++    		if (ret < 0)
++    			goto error_out;
++		}
++
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x04;
++		i2c_buf[2] = 0xEE;
++		ret = cst3xx_i2c_write(client, i2c_buf, 3);
++		if (ret < 0)
++			goto error_out;
++
++		mdelay(60);
++
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x05;
++		ret = cst3xx_i2c_read_register(client, i2c_buf, 1);
++		if (ret < 0)
++			goto error_out;
++
++		if (i2c_buf[0] != 0x55)
++			goto error_out;
++
++	}
++
++	i2c_buf[0] = 0xA0;
++	i2c_buf[1] = 0x03;
++	i2c_buf[2] = 0x00;
++	ret = cst3xx_i2c_write(client, i2c_buf, 3);
++	if (ret < 0)
++		goto error_out;
++
++	mdelay(8);
++
++	if (i2c_buf != NULL) {
++		kfree(i2c_buf);
++		i2c_buf = NULL;
++	}
++
++	return 0;
++
++error_out:
++	if (i2c_buf != NULL) {
++		kfree(i2c_buf);
++		i2c_buf = NULL;
++	}
++	return -1;
++}
++
++
++static int cst3xx_check_checksum(struct i2c_client * client)
++{
++	int ret;
++	int i;
++	unsigned int  checksum;
++	unsigned int  bin_checksum;
++	unsigned char buf[4];
++	const unsigned char *pData;
++
++	for(i=0; i<5; i++)
++	{
++		buf[0] = 0xA0;
++		buf[1] = 0x00;
++		ret = cst3xx_i2c_read_register(client, buf, 1);
++		if(ret < 0)
++		{
++			mdelay(2);
++			continue;
++		}
++
++		if(buf[0]!=0)
++			break;
++		else
++		mdelay(2);
++	}
++    mdelay(2);
++
++
++    if(buf[0]==0x01)
++	{
++		buf[0] = 0xA0;
++		buf[1] = 0x08;
++		ret = cst3xx_i2c_read_register(client, buf, 4);
++
++		if(ret < 0)	return -1;
++
++		// read chip checksum
++		checksum = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24);
++
++        pData=(unsigned char  *)pcst3xx_update_firmware +24*1024+16;   //7*1024 +512
++		bin_checksum = pData[0] + (pData[1]<<8) + (pData[2]<<16) + (pData[3]<<24);
++
++        printk("  hyn the updated ic checksum is :0x%x. the updating firmware checksum is:0x%x------\n", checksum, bin_checksum);
++
++        if(checksum!=bin_checksum)
++		{
++			printk(" cst3xx hyn check sum error.\n");
++			return -1;
++
++		}
++
++	}
++	else
++	{
++		printk(" cst3xx hyn No checksum.\n");
++		return -1;
++	}
++	return 0;
++}
++
++static int cst3xx_exit_program_mode(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[3];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x06;
++	buf[2] = 0xEE;
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0)
++		return -1;
++
++	mdelay(10);	//wait for restart
++
++
++	return 0;
++}
++
++
++static int cst3xx_update_firmware(struct cst3xx_ts_data *ts, const unsigned char *pdata)
++{
++	int ret;
++	int retry = 0;
++
++	printk(" cst3xx----------upgrade cst3xx begain------------\n");
++	disable_irq(ts->irq);
++	mdelay(20);
++START_FLOW:
++
++#ifdef HYN_UPDATE_FIRMWARE_POWERON_ENABLE
++	close_vcc3v3Power();
++	mdelay(20);
++	open_vcc3v3Power();
++	mdelay(5+retry);
++#else
++	cst3xx_reset_ic(ts,5+retry);
++#endif
++	ret = cst3xx_into_program_mode(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]into program mode failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_erase_program_area(ts->client);
++	if (ret) {
++		printk(" cst3xx[cst3xx]erase main area failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_write_program_data(ts->client, pdata);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]write program data into cstxxx failed.\n");
++		goto err_out;
++	}
++
++    ret =cst3xx_check_checksum(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx] after write program cst3xx_check_checksum failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_exit_program_mode(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]exit program mode failed.\n");
++		goto err_out;
++	}
++
++	cst3xx_reset_ic(ts,20);
++
++	printk(" cst3xx hyn----------cst3xx_update_firmware  end------------\n");
++
++	enable_irq(ts->irq);
++
++	return 0;
++
++err_out:
++	if (retry < 30) {
++		retry++;
++		mdelay(20);
++		goto START_FLOW;
++	}
++	else {
++		enable_irq(ts->irq);
++		return -1;
++	}
++}
++
++
++
++
++/*******************************************************
++Function:
++    get firmware version, ic type...
++Input:
++    client: i2c client
++Output:
++    success: 0
++    fail:	-1
++*******************************************************/
++static int cst3xx_firmware_info(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[28];
++//	unsigned short ic_type, project_id;
++
++
++	buf[0] = 0xD1;
++	buf[1] = 0x01;
++	ret = cst3xx_i2c_write(client, buf, 2);
++	if (ret < 0) return -1;
++
++	mdelay(40);
++
++	buf[0] = 0xD1;
++	buf[1] = 0xFC;
++	ret = cst3xx_i2c_read_register(client, buf, 4);
++	if (ret < 0) return -1;
++
++	//0xCACA0000
++	g_cst3xx_ic_checkcode = buf[3];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[2];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[1];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[0];
++
++	printk("linc cst3xx [cst3xx] the chip g_cst3xx_ic_checkcode:0x%x.\r\n",g_cst3xx_ic_checkcode);
++
++	mdelay(2);
++
++	buf[0] = 0xD2;
++	buf[1] = 0x04;
++	ret = cst3xx_i2c_read_register(client, buf, 4);
++	if (ret < 0) return -1;
++	g_cst3xx_ic_type = buf[3];
++	g_cst3xx_ic_type <<= 8;
++	g_cst3xx_ic_type |= buf[2];
++
++
++	g_cst3xx_ic_project_id = buf[1];
++	g_cst3xx_ic_project_id <<= 8;
++	g_cst3xx_ic_project_id |= buf[0];
++
++	printk("linc cst3xx [cst3xx] the chip ic g_cst3xx_ic_type :0x%x, g_cst3xx_ic_project_id:0x%x\r\n",
++		g_cst3xx_ic_type, g_cst3xx_ic_project_id);
++
++	mdelay(2);
++
++	buf[0] = 0xD2;
++	buf[1] = 0x08;
++	ret = cst3xx_i2c_read_register(client, buf, 8);
++	if (ret < 0) return -1;
++
++	g_cst3xx_ic_version = buf[3];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[2];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[1];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[0];
++
++	g_cst3xx_ic_checksum = buf[7];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[6];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[5];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[4];
++
++	tpd_info.vid = g_cst3xx_ic_version;
++    tpd_info.pid = 0x00;
++
++
++	printk(" cst3xx [cst3xx] the chip ic version:0x%x, checksum:0x%x\r\n",
++		g_cst3xx_ic_version, g_cst3xx_ic_checksum);
++
++	if(g_cst3xx_ic_version==0xA5A5A5A5)
++	{
++		printk(" cst3xx [cst3xx] the chip ic don't have firmware. \n");
++		return -1;
++	}
++	if((g_cst3xx_ic_checkcode&0xffff0000)!=0xCACA0000){
++		printk("linc cst3xx [cst3xx] cst3xx_firmware_info read error .\r\n");
++		return -1;
++	}
++
++    buf[0] = 0xD1;
++	buf[1] = 0x09;
++	ret = cst3xx_i2c_write(client, buf, 2);
++	if (ret < 0) return -1;
++    mdelay(5);
++
++
++	return 0;
++}
++
++static int cst3xx_update_judge( unsigned char *pdata, int strict)
++{
++	unsigned short ic_type, project_id;
++	unsigned int fw_checksum, fw_version;
++	const unsigned int *p;
++	int i;
++	unsigned char *pBuf;
++
++	fw_checksum = 0x55;
++	p = (const unsigned int *)pdata;
++	for (i=0; i<(CST3XX_BIN_SIZE-4); i+=4) {
++		fw_checksum += (*p);
++		p++;
++	}
++
++	if (fw_checksum != (*p)) {
++		printk(" cst3xx[cst3xx]calculated checksum error:0x%x not equal 0x%x.\n", fw_checksum, *p);
++		return -1;	//bad fw, so do not update
++	}
++
++	pBuf = &pdata[CST3XX_BIN_SIZE-16];
++
++	project_id = pBuf[1];
++	project_id <<= 8;
++	project_id |= pBuf[0];
++
++	ic_type = pBuf[3];
++	ic_type <<= 8;
++	ic_type |= pBuf[2];
++
++	fw_version = pBuf[7];
++	fw_version <<= 8;
++	fw_version |= pBuf[6];
++	fw_version <<= 8;
++	fw_version |= pBuf[5];
++	fw_version <<= 8;
++	fw_version |= pBuf[4];
++
++	fw_checksum = pBuf[11];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[10];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[9];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[8];
++
++	printk(" cst3xx[cst3xx]the updating firmware:project_id:0x%04x,ic type:0x%04x,version:0x%x,checksum:0x%x\n",
++			project_id, ic_type, fw_version, fw_checksum);
++
++	if (strict > 0) {
++
++		if (g_cst3xx_ic_checksum != fw_checksum){
++			if (g_cst3xx_ic_version >fw_version){
++				printk("[cst3xx]fw version(0x%x), ic version(0x%x).\n",fw_version, g_cst3xx_ic_version);
++			//	return -1;
++			}
++		}else{
++			printk("[cst3xx]fw checksum(0x%x), ic checksum(0x%x).\n",fw_checksum, g_cst3xx_ic_checksum);
++			return -1;
++		}
++	}
++
++	return 0;
++}
++static int cst3xx_boot_update_fw(struct cst3xx_ts_data *ts,  unsigned char *pdata)
++{
++	int ret;
++	int retry = 0;
++	int flag = 0;
++
++	while (retry++ < 3) {
++		ret = cst3xx_firmware_info(ts->client);
++		if (ret == 0) {
++			flag = 1;
++			break;
++		}
++	}
++
++	if (flag == 1) {
++		ret = cst3xx_update_judge(pdata, 1);
++		if (ret < 0) {
++			printk(" cst3xx[cst3xx] no need to update firmware.\n");
++			return 0;
++		}
++	}
++
++	ret = cst3xx_update_firmware(ts, pdata);
++	if (ret < 0){
++		printk(" cst3xx [cst3xx] update firmware failed.\n");
++		return -1;
++	}
++
++    mdelay(50);
++
++	ret = cst3xx_firmware_info(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx [cst3xx] after update read version and checksum fail.\n");
++		return -1;
++	}
++
++	return 0;
++}
++static int hyn_boot_update_fw(struct i2c_client * ts)
++{
++	unsigned char *ptr_fw;
++	int ret;
++	ptr_fw = pcst3xx_update_firmware;
++	ret = cst3xx_boot_update_fw(ts, ptr_fw);
++	return ret;
++
++}
++
++
++/*******************************Chose which I2C interface ********************************************/
++
++#if USE_ANALOG_I2C
++
++#define I2CSDA  GPIO_PB(23)
++#define I2CSCL   GPIO_PB(22)
++
++#define I2CSDA_HIGH gpio_direction_output(I2CSDA,1)
++#define I2CSDA_LOW  gpio_direction_output(I2CSDA,0)
++
++#define I2CSCL_HIGH  gpio_direction_output(I2CSCL,1)
++#define I2CSCL_LOW  gpio_direction_output(I2CSCL,0)
++
++#define delay_data 2
++static void iicstart(void)
++{
++     I2CSDA_HIGH;
++      I2CSCL_HIGH;
++      __udelay(2);
++      I2CSDA_LOW;
++      __udelay(2);
++       I2CSCL_LOW;
++       __udelay(2);
++}
++static void iicstop(void)
++{
++     I2CSDA_LOW;
++     I2CSCL_HIGH;
++     __udelay(2);
++     I2CSDA_HIGH;
++     __udelay(2);
++
++}
++static unsigned char waitack(void)
++{
++   u8 ucErrTime=0;
++
++//    gpio_direction_input(GPIO_PC(27));
++    gpio_direction_input(GPIO_PB(23));
++   //  __udelay(2);
++
++  //  I2CSDA_HIGH;
++  //  __udelay(2);
++     I2CSCL_HIGH;
++     __udelay(2);
++
++//    while(__gpio_get_value(GPIO_PC(27)))
++    while(__gpio_get_value(GPIO_PB(23)))
++    {
++        ucErrTime++;
++     //   printk("time out ++ \n");
++        if(ucErrTime>250)
++         {
++                iicstop();
++                return 1;
++        }
++    }
++    I2CSCL_LOW;
++     __udelay(2);
++    return 0;
++}
++static void sendack(void)
++{
++     I2CSCL_LOW;
++     __udelay(delay_data);
++     I2CSDA_LOW;
++     __udelay(delay_data);
++
++     I2CSCL_HIGH;
++     __udelay(delay_data);
++     I2CSCL_LOW;
++     __udelay(delay_data);
++
++}
++static void sendnotack(void)
++{
++     I2CSCL_LOW;
++     __udelay(delay_data);
++    I2CSDA_HIGH;
++    __udelay(delay_data);
++
++    I2CSCL_HIGH;
++    __udelay(delay_data);
++    I2CSCL_LOW;
++    __udelay(delay_data);
++}
++static void iicsendbyte(unsigned char ch)
++{
++     unsigned char i;
++     I2CSCL_LOW;
++     for(i = 0;i<8;i++)
++     {
++          if(ch&0x80)
++          {
++              I2CSDA_HIGH;
++          }
++          else
++          {
++              I2CSDA_LOW;
++          }
++           __udelay(delay_data);
++          ch<<=1;
++          I2CSCL_HIGH;
++          __udelay(delay_data);
++               I2CSCL_LOW;
++          __udelay(delay_data);
++     }
++}
++static unsigned char iicreceivebyte(unsigned char ack)
++{
++    unsigned char i=8;
++    unsigned char ddata=0;
++
++    gpio_direction_input(GPIO_PC(27));
++    __udelay(delay_data);
++
++     for(i = 0;i<8;i++)
++     {
++         I2CSCL_LOW;
++         __udelay(delay_data);
++         I2CSCL_HIGH;
++         __udelay(delay_data);
++
++         ddata<<=1;
++         if(gpio_get_value(GPIO_PC(27))) ddata++;
++    }
++
++    if(!ack)
++        sendnotack();
++     else
++        sendack();
++
++    return ddata;
++}
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++    int count = len;
++     iicstart();
++     __udelay(delay_data);
++
++/*
++	 iicsendbyte( (0x1a<<1) | 0);
++     __udelay(delay_data);
++
++     if(waitack())
++     {
++        iicstop();
++                printk(" cst3xx_i2c_read wait ack timeoue \n");
++        return 1;
++     }
++
++     iicsendbyte(buf[0]);
++     __udelay(delay_data);
++     waitack();
++     __udelay(delay_data);
++*/
++     iicstart();
++     __udelay(delay_data);
++
++     iicsendbyte((0x1a << 1 ) | 1);
++     __udelay(delay_data);
++     if(waitack())
++     {
++        iicstop();
++                printk(" cst3xx_i2c_read wait ack timeoue \n");
++        return 1;
++     }
++     __udelay(delay_data);
++
++    while(count)
++    {
++         if(count == 1) *buf = iicreceivebyte(0);
++         else *buf = iicreceivebyte(1);
++         count --;
++         buf++;
++    }
++     iicstop();
++     __udelay(delay_data);
++     return 0;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++     int count = len;
++      iicstart();
++   //   __udelay(delay_data);
++
++      iicsendbyte((0x1A << 1) | 0);
++//      __udelay(delay_data);
++
++     if(waitack())
++     {
++        iicstop();
++        printk(" cst3xx_i2c_write send address wait ack timeoue \n");
++        return 1;
++     }
++
++      while(count--)
++      {
++            iicsendbyte(*(buf++));
++            __udelay(delay_data);
++             if(waitack())
++             {
++                iicstop();
++               printk(" cst3xx_i2c_write wait ack timeoue \n");
++                return 1;
++             }
++            __udelay(delay_data);
++      }
++
++      iicstop();
++      __udelay(delay_data);
++
++	return 0;
++}
++
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	int ret = -1;
++
++    ret = cst3xx_i2c_write(client, buf, 2);
++    if(ret) printk("failed to write cst3xx\n");
++
++    ret = cst3xx_i2c_read(client, buf, len);
++    if(ret) printk("failed to write cst3xx\n");
++    return ret;
++}
++
++#elif  USE_LOWEST_I2CA
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	int ret = -1;
++	int retries = 0;
++
++	while (retries < 2) {
++		ret = i2c_master_recv(client, buf, len);
++		if(ret<=0)
++		    retries++;
++        else
++            break;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	int ret = -1;
++	int retries = 0;
++
++	while (retries < 2) {
++		ret = i2c_master_send(client, buf, len);
++		if(ret<=0)
++		    retries++;
++        else
++            break;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	int ret = -1;
++
++    ret = cst3xx_i2c_write(client, buf, 2);
++
++    ret = cst3xx_i2c_read(client, buf, len);
++
++    return ret;
++}
++
++#elif USE_HIGHEST_I2CA
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++	struct i2c_msg msg;
++	int ret = -1;
++	int retries = 0;
++
++	msg.flags |= I2C_M_RD;
++	msg.addr   = client->addr;
++	msg.len    = len;
++	msg.buf    = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == 1)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++/*******************************************************
++Function:
++    read data from register.
++Input:
++    buf: first two byte is register addr, then read data store into buf
++    len: length of data that to read
++Output:
++    success: number of messages
++    fail:	negative errno
++*******************************************************/
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++//	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	struct i2c_msg msgs[2];
++	int ret = -1;
++	int retries = 0;
++
++	msgs[0].flags = 0;
++	msgs[0].addr  = client->addr;
++	msgs[0].len   = 2;
++	msgs[0].buf   = buf;
++
++	msgs[1].flags |= I2C_M_RD;
++	msgs[1].addr   = client->addr;
++	msgs[1].len    = len;
++	msgs[1].buf    = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, msgs, 2);
++		if(ret == 2)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++//	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	struct i2c_msg msg;
++	int ret = -1;
++	int retries = 0;
++
++	msg.flags = 0;
++	msg.addr  = client->addr;
++	msg.len   = len;
++	msg.buf   = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == 1)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++#else
++#endif
++/*********************************i2c end********************************/
++
++
++static int cst3xx_i2c_test(struct i2c_client *client)
++{
++	int retry = 0;
++	int ret;
++	unsigned char buf[4];
++
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	while (retry++ < 5) {
++		ret = cst3xx_i2c_write(client, buf, 2);
++		if (ret == 0)
++			return ret;
++
++		mdelay(2);
++	}
++
++    if(retry==5) printk(" cst3xx hyn I2C TEST error.ret:%d;\n", ret);
++
++	return ret;
++}
++
++
++static void cst3xx_reset(struct cst3xx_ts_data *ts) {
++	if(gpio_is_valid(ts->pdata->reset_gpio)) {
++		gpio_direction_output(ts->pdata->reset_gpio,0);
++		mdelay(100);
++		gpio_direction_output(ts->pdata->reset_gpio,1);
++		mdelay(100);
++	}
++}
++/****************************  basic communication end*******************************/
++
++
++static void cst3xx_touch_report(struct cst3xx_ts_data *ts)
++{
++	unsigned char buf[30];
++	unsigned char i2c_buf[8];
++	unsigned char key_status, key_id = 0, finger_id, sw;
++	unsigned int  input_x = 0;
++	unsigned int  input_y = 0;
++	unsigned int  input_w = 0;
++	unsigned int input_x_delta = 0;
++	unsigned int input_y_delta = 0;
++       unsigned char cnt_up, cnt_down;
++	int   i, ret, idx;
++	int cnt, i2c_len;
++
++	int  len_1, len_2;
++
++      key_status = 0;
++
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	ret = cst3xx_i2c_read_register(ts->client, buf, 7);
++	if(ret < 0) {
++		printk("  iic read touch point data failed.\n");
++		goto OUT_PROCESS;
++	}
++  //   printk(" read buf : buf[0]: %x ,buf[1]: %x ,buf[2]: %x, buf[3]: %x,buf[4]: %x ,buf[5]: %x ,buf[6]: %x, buf[7]: %x,\n",buf[0],buf[1],buf[2],buf[3],buf[4],buf[5],buf[6],buf[7]);
++
++	if(buf[6] != 0xAB) {
++		printk(KERN_INFO " data is not valid..\r\n");
++		goto OUT_PROCESS;
++	}
++
++    	cnt = buf[5] & 0x7F;
++	if(cnt > 1) goto OUT_PROCESS;
++	else if(cnt==0)     goto CLR_POINT;
++
++	if(cnt == 0x01) {
++		goto FINGER_PROCESS;
++	}
++
++FINGER_PROCESS:
++
++    /*
++     *  sw: buf[0] low 4 bit
++     *  x pos:  buf[1] low 4 bit | buf[3] high 4 bit
++     *  y pos:  buf[2] low 4 bit | buf[3] low  4 bit
++     *  z press : buf[4]
++     *  finger_id:buf[0] high 4 bit
++     */
++	i2c_buf[0] = 0xD0;
++	i2c_buf[1] = 0x00;
++	i2c_buf[2] = 0xAB;
++
++	ret = cst3xx_i2c_write(ts->client, i2c_buf, 3);
++	if(ret < 0) {
++		printk(" cst3xx hyn send read touch info ending failed.\r\n");
++		cst3xx_reset_ic(ts,20);
++              goto END;
++	}
++
++	idx = 0;
++       cnt_up = 0;
++       cnt_down = 0;
++	input_x = (unsigned int)((buf[idx + 1] << 4) | ((buf[idx + 3] >> 4) & 0x0F));
++	input_y = (unsigned int)((buf[idx + 2] << 4) | (buf[idx + 3] & 0x0F));
++	input_w = (unsigned int)(buf[idx + 4]);
++	sw = (buf[idx] & 0x0F) >> 1;
++	finger_id = (buf[idx] >> 4) & 0x0F;
++
++    printk(" no handle : cst3xxPoint x:%d, y:%d, w:%d, id:%d, sw:%d. \n", input_x, input_y, input_w,finger_id, sw);
++
++	input_x=input_x*CST3XX_MAX_X/CST3XX_MAX_X;  //update 0729 no handle == handle
++//	input_x=input_x*CST3XX_MAX_X/268;  //update 0729 no handle == handle
++//	input_x=input_x*CST3XX_MAX_X/360;  //update 0729 no handle == handle
++//	input_y=input_y*CST3XX_MAX_Y/800;
++
++//	if(input_x >= CST3XX_MAX_X) input_x = CST3XX_MAX_X;
++//	if(input_y >= CST3XX_MAX_Y) input_y = CST3XX_MAX_Y;
++
++//	input_x = CST3XX_MAX_X-input_x;
++//	input_y = CST3XX_MAX_Y-input_y;
++
++#ifdef HYN_DRAW_POINT
++	if(input_x > 300){
++		input_x_delta = input_x - (CST3XX_MAX_X/2);
++		input_x = input_x + input_x_delta/((CST3XX_MAX_X/2)/20);
++		if(input_x > CST3XX_MAX_X) input_x = CST3XX_MAX_X;
++		}
++	if(input_x < 40){
++		input_x_delta = (CST3XX_MAX_X/2) - input_x;
++		input_x = input_x - input_x_delta/((CST3XX_MAX_X/2)/12);
++		if(input_x < 0) input_x = 0;
++		}
++	if(input_y > 760){
++		input_y_delta = input_y - (CST3XX_MAX_Y/2);
++		input_y = input_y + input_y_delta/((CST3XX_MAX_Y/2)/12);
++		if(input_y > CST3XX_MAX_Y) input_y = CST3XX_MAX_Y;
++		}
++	if(input_y < 40){
++		input_y_delta = (CST3XX_MAX_Y/2) - input_y;
++		input_y = input_y - input_y_delta/((CST3XX_MAX_Y/2)/25);
++		if(input_y < 0) input_y = 0;
++		}
++#endif
++
++    printk(" handle : cst3xxPoint x:%d, y:%d, w:%d, id:%d, sw:%d. \n\n", input_x, input_y, input_w,finger_id, sw);
++
++	if (sw == 0x03 ) {
++         	   if((input_x > x_temp_pos + ERROR_TOUCH) || (input_x < x_temp_pos -ERROR_TOUCH)  || (input_y > y_temp_pos + ERROR_TOUCH) || (input_y < y_temp_pos -ERROR_TOUCH))
++               {
++          //           printk(" REPORT TOUCH DOWM Handle \n");
++                     x_temp_pos = input_x;
++                     y_temp_pos = input_y;
++                     input_report_key(ts->input_dev, BTN_TOUCH, 1);
++    		        input_report_abs(ts->input_dev, ABS_X, input_x);
++    	               input_report_abs(ts->input_dev, ABS_Y, input_y);
++    		        input_report_abs(ts->input_dev, ABS_PRESSURE, 1);
++    		        input_sync(ts->input_dev);
++                 }
++                cnt_down++;
++       }
++      else if(sw == 0) {
++                cnt_up++;
++        }
++
++        if((cnt_up>0) && (cnt_down==0) ){
++      //      printk(" REPORT TOUCH UP Handle \n");
++            x_temp_pos = 0;
++            y_temp_pos = 0;
++            input_report_key(ts->input_dev, BTN_TOUCH, 0);
++            input_report_abs(ts->input_dev, ABS_PRESSURE, 0);
++            input_mt_sync(ts->input_dev);
++        }
++       input_sync(ts->input_dev);
++	goto END;
++CLR_POINT:
++
++	    input_report_key(ts->input_dev, BTN_TOUCH, 0);
++           input_mt_sync(ts->input_dev);
++           input_sync(ts->input_dev);
++
++OUT_PROCESS:
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	buf[2] = 0xAB;
++	ret = cst3xx_i2c_write(ts->client, buf, 3);
++	if (ret < 0) {
++		printk("  send read touch info ending failed.\n");
++		cst3xx_reset_ic(ts,20);
++	}
++END:
++	return;
++}
++
++
++/******************************* irq handle  begin************************************/
++static void cst3xx_work_handler(struct work_struct *work)
++{
++	struct cst3xx_ts_data *cst3xx_ts = container_of(work, struct cst3xx_ts_data, work);
++	int ret = 0;
++    /******************here handle touch *******************/
++    //    printk(KERN_INFO "-----------enter cst3xx_work_handler------------\n");
++         cst3xx_touch_report(cst3xx_ts);
++	  enable_irq(cst3xx_ts->irq);
++}
++
++static irqreturn_t cst3xx_ts_irq_handler(int irq, void *dev_id)
++{
++	struct cst3xx_ts_data *ts = dev_id;
++
++   //    printk( KERN_INFO "-----------enter cst3xx_ts_irq_handler------------\n");
++
++	disable_irq_nosync(ts->irq);//use in interrupt,disable_irq will make dead lock.
++
++	if (!work_pending(&ts->work)) {
++		queue_work(ts->workqueue, &ts->work);
++	//    queue_delayed_work(ts->workqueue,&ts->dwork,1);//10ms * x
++	} else {
++		enable_irq(ts->irq);
++	}
++
++	return IRQ_HANDLED;
++}
++/******************************* irq handle  end************************************/
++static int cst3xx_parse_dt(struct device *dev, struct cst3xx_platform_data *pdata)
++{
++    int ret = 0;
++    struct device_node *np = dev->of_node;
++    u32 temp_val = 0;
++
++    HYN_FUNC_ENTER();
++
++    /* reset, irq gpio info */
++    pdata->reset_gpio = of_get_named_gpio_flags(np, "hyn,reset-gpio",
++                        0, &pdata->reset_gpio_flags);
++    if (pdata->reset_gpio < 0)
++        HYN_ERROR("Unable to get reset_gpio");
++
++    pdata->int_gpio = of_get_named_gpio_flags(np, "hyn,irq-gpio",
++                      0, &pdata->irqflags);
++    if (pdata->int_gpio < 0)
++        HYN_ERROR("Unable to get irq_gpio");
++
++    HYN_INFO(" irq gpio:%d, reset gpio:%d",
++              pdata->int_gpio, pdata->reset_gpio);
++
++    HYN_FUNC_EXIT();
++    return 0;
++}
++static int cst3xx_gpio_configure(struct cst3xx_ts_data *data)
++{
++    int ret = 0;
++
++    HYN_FUNC_ENTER();
++    /* request irq gpio */
++    if (gpio_is_valid(data->pdata->int_gpio)) {
++        ret = gpio_request(data->pdata->int_gpio, "cst3xx_irq_gpio");
++        if (ret) {
++            HYN_ERROR("[GPIO]irq gpio request failed");
++            goto err_irq_gpio_req;
++        }
++
++        ret = gpio_direction_input(data->pdata->int_gpio);
++        if (ret) {
++            HYN_ERROR("[GPIO]set_direction for irq gpio failed");
++            goto err_irq_gpio_dir;
++        }
++    }
++
++    /* request reset gpio */
++    if (gpio_is_valid(data->pdata->reset_gpio)) {
++        ret = gpio_request(data->pdata->reset_gpio, "cst3xx_reset_gpio");
++        if (ret) {
++            HYN_ERROR("[GPIO]reset gpio request failed");
++            goto err_irq_gpio_dir;
++        }
++
++//        ret = gpio_direction_output(data->pdata->reset_gpio, 1);
++//        if (ret) {
++//            HYN_ERROR("[GPIO]set_direction for reset gpio failed");
++//            goto err_reset_gpio_dir;
++//        }
++    }
++
++    HYN_FUNC_EXIT();
++    return 0;
++
++err_reset_gpio_dir:
++    if (gpio_is_valid(data->pdata->reset_gpio))
++        gpio_free(data->pdata->reset_gpio);
++err_irq_gpio_dir:
++    if (gpio_is_valid(data->pdata->int_gpio))
++        gpio_free(data->pdata->int_gpio);
++err_irq_gpio_req:
++    HYN_FUNC_EXIT();
++    return ret;
++}
++
++static int cst3xx_input_init(struct cst3xx_ts_data *ts_data)
++{
++    int ret = 0;
++    int key_num = 0;
++    struct cst3xx_platform_data *pdata = ts_data->pdata;
++    struct input_dev *input_dev;
++
++    HYN_FUNC_ENTER();
++    input_dev = input_allocate_device();
++    if (!input_dev) {
++        HYN_ERROR("Failed to allocate memory for input device");
++        return -ENOMEM;
++    }
++
++    /* Init and register Input device */
++    input_dev->name = CST3XX_NAME;
++
++    input_dev->id.bustype = BUS_I2C;
++    input_dev->dev.parent = ts_data->dev;
++
++    input_set_drvdata(input_dev, ts_data);
++
++    __set_bit(EV_SYN, input_dev->evbit);
++    __set_bit(EV_ABS, input_dev->evbit);
++    __set_bit(EV_KEY, input_dev->evbit);
++    __set_bit(BTN_TOUCH, input_dev->keybit);
++//    __set_bit(INPUT_PROP_DIRECT, input_dev->propbit);
++    set_bit(ABS_X, input_dev->absbit); //add from hyn
++	set_bit(ABS_Y, input_dev->absbit);
++    set_bit(ABS_PRESSURE, input_dev->absbit);
++
++/*---add from hyn*/
++	input_set_abs_params(input_dev, ABS_X, ts_data->pdata->x_min, ts_data->pdata->x_max, 0, 0);
++	input_set_abs_params(input_dev, ABS_Y, ts_data->pdata->y_min, ts_data->pdata->y_max, 0, 0);
++    input_set_abs_params(input_dev, ABS_PRESSURE, 0, 1, 0 , 0);
++/*add from hyn---*/
++
++    ret = input_register_device(input_dev);
++    if (ret) {
++        HYN_ERROR("Input device registration failed");
++        input_set_drvdata(input_dev, NULL);
++        input_free_device(input_dev);
++        input_dev = NULL;
++        return ret;
++    }
++
++    ts_data->input_dev = input_dev;
++
++    HYN_FUNC_EXIT();
++    return 0;
++}
++
++static int cst3xx_irq_registration(struct cst3xx_ts_data *ts_data)
++{
++    int ret = 0;
++    struct cst3xx_platform_data *pdata = ts_data->pdata;
++
++    ts_data->irq = gpio_to_irq(pdata->int_gpio);
++    pdata->irqflags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
++    HYN_INFO("irq:%d, flag:%x", ts_data->irq, pdata->irqflags);
++    ret = request_threaded_irq(ts_data->irq, NULL, cst3xx_ts_irq_handler,
++                               pdata->irqflags,
++                               CST3XX_NAME, ts_data);
++
++    return ret;
++}
++
++static int cst3xx_ts_probe_entry(struct cst3xx_ts_data *ts_data)
++{
++    int ret = 0;
++    int rc=-1;
++    int pdata_size = sizeof(struct cst3xx_platform_data);
++
++    HYN_FUNC_ENTER();
++    ts_data->pdata = kzalloc(pdata_size, GFP_KERNEL);
++    if (!ts_data->pdata) {
++        HYN_ERROR("allocate memory for platform_data fail");
++        return -ENOMEM;
++    }
++
++    if (ts_data->dev->of_node) {
++        ret = cst3xx_parse_dt(ts_data->dev, ts_data->pdata);
++        if (ret)
++            HYN_ERROR("device-tree parse fail");
++    } else {
++        if (ts_data->dev->platform_data) {
++            memcpy(ts_data->pdata, ts_data->dev->platform_data, pdata_size);
++        } else {
++            HYN_ERROR("platform_data is null");
++            return -ENODEV;
++        }
++    }
++    //init work for cst3xx..
++
++	INIT_WORK(&ts_data->work, cst3xx_work_handler);
++
++    ts_data->workqueue = create_singlethread_workqueue("cst3xx_wq");
++    if (!ts_data->workqueue) {
++        HYN_ERROR("create cst3xx workqueue fail");
++    }
++
++//    spin_lock_init(&ts_data->irq_lock);
++//    mutex_init(&ts_data->report_mutex);
++//    mutex_init(&ts_data->bus_lock);
++
++    /* Init communication interface */
++    ret = cst3xx_bus_init(ts_data);
++    if (ret) {
++        HYN_ERROR("bus initialize fail");
++        goto err_bus_init;
++    }
++#if USE_ANALOG_I2C
++        if (gpio_is_valid(I2CSDA)
++        {
++            gpio_free(I2CSDA);
++            ret = gpio_request(GPIO_PB(23),"I2C2-SDA");
++            if(ret < 0){
++                printk("I2C2-SDA gpio request failed\n");
++                return ret;
++            }
++        }
++         if (gpio_is_valid(I2CSCL))
++        {
++            gpio_free(I2CSCL);
++            ret = gpio_request(GPIO_PB(22),"I2C2-SCL");
++            if(ret < 0){
++                printk("I2C2-SCL gpio request failed\n");
++                return ret;
++            }
++         }
++#endif
++       ret =  cst3xx_i2c_test(ts_data->client);
++      // if(ret>=0){
++	   if(ret<0){
++
++
++          mdelay(100);
++
++          printk( KERN_INFO "cst3xx test OK -------------------\n");
++#ifdef HYN_UPDATE_FIRMWARE_ENABLE
++	        ret = cst3xx_boot_update_fw(ts_data,pcst3xx_update_firmware);//
++			if(ret < 0){
++			printk(" cst3xx hyn_boot_update_fw failed.\n");
++			return -1;
++			}
++#endif
++
++       }else{
++         // printk( KERN_INFO "cst3xx hyn i2c communication failed.---------------\n");
++		  //return -1;
++
++          mdelay(20);
++//		  rc = hyn_boot_update_fw(ts);
++		  rc = hyn_boot_update_fw(ts_data);
++		  if(rc < 0){
++			printk(" cst3xx hyn_boot_update_fw failed.\n");
++			//return -1;
++		}
++       }
++
++    ret = cst3xx_input_init(ts_data);
++    if (ret) {
++        HYN_ERROR("input initialize fail");
++        goto err_input_init;
++    }
++
++    ret = cst3xx_gpio_configure(ts_data);
++    if (ret) {
++        HYN_ERROR("configure the gpios fail");
++        goto err_gpio_config;
++    }
++       printk( KERN_INFO "cst3xx reset ----before---------------\n");
++       cst3xx_reset(ts_data);
++       printk( KERN_INFO "cst3xx reset ----after--------------\n");
++
++    ret = cst3xx_irq_registration(ts_data);
++    if (ret) {
++        HYN_ERROR("request irq failed");
++        goto err_irq_req;
++    }
++
++    HYN_FUNC_EXIT();
++    return 0;
++
++err_irq_req:
++    if (gpio_is_valid(ts_data->pdata->reset_gpio))
++        gpio_free(ts_data->pdata->reset_gpio);
++    if (gpio_is_valid(ts_data->pdata->int_gpio))
++        gpio_free(ts_data->pdata->int_gpio);
++err_gpio_config:
++    kfree_safe(ts_data->point_buf);
++    kfree_safe(ts_data->events);
++err_input_init:
++    if (ts_data->workqueue)
++        destroy_workqueue(ts_data->workqueue);
++err_bus_init:
++    kfree_safe(ts_data->bus_tx_buf);
++    kfree_safe(ts_data->bus_rx_buf);
++    kfree_safe(ts_data->pdata);
++
++    HYN_FUNC_EXIT();
++    return ret;
++}
++static int cst3xx_ts_probe(struct i2c_client *client, const struct i2c_device_id *id)
++{
++    int ret = 0;
++    struct cst3xx_ts_data *ts_data = NULL;
++	struct input_dev *input_dev;
++
++	struct cst3xx_platform_data *pdata = (struct cst3xx_platform_data*)client->dev.platform_data;
++
++    HYN_INFO("Touch Screen(I2C BUS) driver prboe...");
++    if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
++        HYN_ERROR("I2C not supported");
++        return -ENODEV;
++    }
++
++    /* malloc memory for global struct variable */
++    ts_data = (struct cst3xx_ts_data *)kzalloc(sizeof(*ts_data), GFP_KERNEL);
++    if (!ts_data) {
++        HYN_ERROR("allocate memory for cst3xx_data fail");
++        return -ENOMEM;
++    }
++    ts_data->client = client;
++    ts_data->dev = &client->dev;
++    ts_data->pdata = pdata;
++    i2c_set_clientdata(client, ts_data);
++
++    ret = cst3xx_ts_probe_entry(ts_data);
++    if (ret) {
++        HYN_ERROR("Touch Screen(I2C BUS) driver probe fail");
++        kfree_safe(ts_data);
++        return ret;
++    }
++	if(client->addr != 0x1A) //check address
++	{
++		client->addr = 0x1A;
++		printk(">>>>>>>>>>>>>1>>>xtang:i2c_client_HYN->addr=%d.\n",client->addr);
++
++	}else
++		printk(">>>>>>>>>>>>2>>>>xtang:i2c_client_HYN->addr=%d.\n",client->addr);
++
++
++    HYN_INFO("Touch Screen(I2C BUS) driver prboe successfully");
++    return 0;
++}
++
++
++static int cst3xx_ts_remove(struct i2c_client *client)
++{
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++        free_irq(ts->irq,ts);
++        devm_free_irq(&ts->client->dev, ts->client->irq,ts);
++        destroy_workqueue(ts->workqueue);
++        input_unregister_device(ts->input_dev);
++        devm_gpio_free(&ts->client->dev, ts->pdata->reset_gpio);
++        gpio_free(ts->pdata->int_gpio);
++
++#if USE_ANALOG_I2C
++         gpio_free(I2CSDA);
++        gpio_free(I2CSCL);
++#endif
++//i2c bus init.
++	cst3xx_bus_exit(ts);
++
++	return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int cst3xx_ts_suspend(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++
++	if (device_may_wakeup(&client->dev)) {
++		enable_irq_wake(client->irq);
++	} else {
++		disable_irq(client->irq);
++		cst3xx_ts_power(ts, false);//reset
++	}
++
++	return 0;
++}
++
++static int cst3xx_ts_resume(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++
++	if (device_may_wakeup(&client->dev)) {
++		disable_irq_wake(client->irq);
++	} else {
++		cst3xx_ts_power(ts, true);
++		enable_irq(client->irq);
++	}
++	return 0;
++}
++
++#endif
++
++static SIMPLE_DEV_PM_OPS(cst3xx_ts_pm_ops,
++			 cst3xx_ts_suspend, cst3xx_ts_resume);
++
++static const struct i2c_device_id cst3xx_ts_id[] = {
++	{ CST3XX_NAME, 0 },
++	{ }
++};
++static const struct of_device_id cst3xx_dt_match[] = {
++    {.compatible = "hyn,cst3xx", },
++    {},
++};
++MODULE_DEVICE_TABLE(of, cst3xx_dt_match);
++
++static struct i2c_driver cst3xx_ts_driver = {
++    .probe = cst3xx_ts_probe,
++    .remove = cst3xx_ts_remove,
++    .driver = {
++        .name = CST3XX_NAME,
++        .owner = THIS_MODULE,
++        .of_match_table = of_match_ptr(cst3xx_dt_match),
++	.pm	= &cst3xx_ts_pm_ops,
++    },
++    .id_table = cst3xx_ts_id,
++};
++
++static int __init cst3xx_ts_init(void)
++{
++    int ret = 0;
++
++    HYN_FUNC_ENTER();
++    ret = i2c_add_driver(&cst3xx_ts_driver);
++    if ( ret != 0 ) {
++        HYN_ERROR("hyn touch screen driver init failed!");
++    }
++    HYN_FUNC_EXIT();
++    return ret;
++}
++
++static void __exit cst3xx_ts_exit(void)
++{
++    i2c_del_driver(&cst3xx_ts_driver);
++}
++module_init(cst3xx_ts_init);
++module_exit(cst3xx_ts_exit);
++
++MODULE_AUTHOR("HYN Driver Team");
++MODULE_DESCRIPTION("HYN Touchscreen Driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Debug_driver/ref_cst3xx_MCU_driver_0729_update2/hyn_cst3xx_RS659_fw_0729_update2.h b/module_drivers/drivers/input/touchscreen/hyn_touch/Debug_driver/ref_cst3xx_MCU_driver_0729_update2/hyn_cst3xx_RS659_fw_0729_update2.h
+new file mode 100644
+index 000000000..24cfbcfed
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Debug_driver/ref_cst3xx_MCU_driver_0729_update2/hyn_cst3xx_RS659_fw_0729_update2.h
+@@ -0,0 +1,1552 @@
++
++#ifndef __CST3xx_FW_H__
++#define __CST3xx_FW_H__
++
++  unsigned char cst3_fw[] ={
++    0x98,0xE0,0x07,0x01,0xC8,0x28,0x02,0x00,0x00,0x00,0x00,0x00,0xC8,0xE8,0x01,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x90,0x08,0x07,0x00,0x98,0x08,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x98,0xA8,0x00,0x00,0x00,0x00,0x00,0x00,0x98,0x78,0x01,0x00,0x80,0x07,0xC0,0x17,
++    0x82,0x07,0xC0,0x07,0x01,0x65,0x40,0x86,0xC1,0x41,0xC0,0x20,0xC5,0x68,0x31,0x12,
++    0xF5,0x38,0x33,0x5A,0x32,0xA2,0x32,0xEA,0x10,0x62,0x8D,0x0E,0x81,0x07,0xC0,0x97,
++    0x30,0xF2,0xF3,0x79,0x65,0x7E,0x30,0xB2,0x31,0x09,0x10,0x9A,0x87,0x06,0xD0,0xD8,
++    0x35,0x12,0x35,0x5A,0x18,0x9A,0x39,0xC2,0x70,0x82,0x02,0x00,0x70,0x82,0x03,0x00,
++    0xD0,0x81,0x98,0x16,0x43,0xC6,0x0B,0xC6,0xC2,0xD6,0x3F,0x90,0x99,0x0E,0x40,0x86,
++    0x08,0x86,0xA9,0x0E,0x40,0x23,0x00,0x63,0x38,0x82,0x03,0x00,0x18,0x01,0x20,0x01,
++    0x28,0x01,0x30,0x01,0xD0,0x81,0x98,0x0E,0x0F,0xC6,0xC3,0xDE,0x38,0x90,0x9A,0x06,
++    0x08,0x86,0xA9,0x06,0x03,0x5B,0x38,0x82,0xAE,0xFD,0x30,0x02,0x30,0x02,0xEE,0xFD,
++    0xA8,0x85,0xE8,0x85,0x84,0x27,0xE8,0xBF,0x37,0x8A,0xB8,0xFF,0xF8,0xAF,0x87,0x0F,
++    0xD0,0xFF,0x80,0x27,0xEF,0x7F,0xBD,0xFF,0xF8,0x9F,0x87,0x27,0xE8,0xAF,0x05,0x00,
++    0xAF,0x85,0x6F,0xFA,0x39,0x01,0xC0,0x43,0x37,0x4A,0xC9,0x01,0x38,0x30,0x32,0x42,
++    0x86,0x01,0xC5,0x1B,0xCE,0x23,0xF0,0x53,0xC0,0x01,0x74,0x01,0xDD,0x16,0xC0,0x6B,
++    0x48,0x68,0x87,0x3E,0xAA,0x7B,0xAC,0x3B,0x10,0xD2,0x8C,0x16,0xB0,0x63,0x06,0x09,
++    0xB7,0x43,0xEC,0x85,0x34,0x6A,0xE8,0x4B,0xE6,0x48,0x92,0x4D,0xAF,0x4B,0x4D,0xF9,
++    0x8D,0x0E,0x10,0x12,0x82,0x16,0xE8,0x0B,0x48,0x09,0x88,0x1E,0xB5,0x5B,0xAF,0x7B,
++    0xAF,0x3B,0xEA,0x85,0x4F,0x09,0x8C,0xE6,0x0A,0x09,0xA8,0x0B,0xE8,0x85,0xAF,0x85,
++    0x67,0x3A,0xE7,0x01,0x00,0x0F,0x80,0x0F,0xF5,0x1F,0xF0,0x03,0x47,0x01,0x80,0xD6,
++    0xEF,0x85,0xA8,0xC5,0x00,0x21,0x80,0x0F,0xE8,0x6F,0x07,0x09,0x87,0x0F,0xE8,0x57,
++    0x79,0x02,0x47,0xC3,0x0C,0x01,0x19,0x42,0x00,0xC3,0x01,0x11,0x86,0x0F,0xE8,0xBF,
++    0x61,0xEA,0x56,0x03,0x29,0x41,0x18,0x42,0x17,0x03,0x49,0x03,0x1F,0x42,0x09,0x03,
++    0x15,0x2B,0x4B,0x03,0x1D,0x42,0x09,0x03,0x4D,0x03,0x1B,0x42,0x0B,0x03,0x4B,0x03,
++    0x35,0x21,0x18,0x82,0x0B,0x03,0x4B,0x03,0x42,0x00,0x02,0x00,0x09,0x03,0x4B,0x03,
++    0x19,0x42,0x09,0x03,0x49,0x03,0x19,0x82,0x09,0x03,0x49,0x03,0x08,0x09,0x18,0x42,
++    0x0F,0x03,0x41,0x03,0x1F,0x42,0x05,0x03,0x45,0x03,0x1F,0x82,0x07,0x03,0x47,0x03,
++    0x1F,0x42,0x04,0x03,0x45,0x03,0x1D,0x42,0x05,0x03,0x45,0x03,0x1D,0x82,0x05,0x03,
++    0x45,0x03,0x1B,0x42,0x03,0x03,0x43,0x03,0x1B,0x82,0x05,0x03,0x44,0x03,0x1D,0x42,
++    0x03,0x03,0x45,0x03,0x1B,0x42,0x04,0x03,0x0E,0x81,0x42,0x02,0x82,0x27,0xE0,0x97,
++    0x85,0x0F,0xE8,0x87,0x85,0x0F,0xE8,0x67,0x85,0x0F,0xE8,0x97,0x48,0xE2,0x05,0x01,
++    0x1D,0x43,0x4C,0x03,0x1D,0x42,0x0D,0x03,0x10,0x2B,0x03,0x11,0x84,0x0F,0xE8,0x97,
++    0x41,0xC3,0x09,0x01,0x19,0x42,0x00,0xC3,0x00,0x21,0x80,0x0F,0xE8,0x07,0x04,0x09,
++    0x83,0x0F,0xE8,0xEF,0x42,0x03,0x41,0x00,0x01,0x00,0x02,0x03,0x40,0x03,0x0F,0x09,
++    0x1F,0x42,0x00,0x03,0x4C,0x03,0x1B,0x42,0x09,0x03,0x4B,0x03,0x19,0x42,0x0C,0x03,
++    0x41,0x03,0x1D,0x42,0x05,0x03,0x45,0x03,0x1D,0x82,0x01,0x03,0x41,0x03,0x1B,0x42,
++    0x03,0x03,0x43,0x03,0x1B,0x82,0x01,0x03,0x48,0x0B,0x03,0x61,0x1B,0x0A,0x08,0x0B,
++    0x48,0x0B,0x19,0x0A,0x0F,0x0B,0x41,0x0B,0x1F,0x0A,0x00,0x0B,0x48,0xE2,0x04,0x09,
++    0xC8,0x01,0xAF,0x43,0x82,0x0F,0xD0,0xD7,0xEC,0xC5,0x47,0xCA,0xC6,0x01,0xF3,0x0B,
++    0x42,0xCA,0x84,0x01,0x48,0x01,0x80,0x3E,0x4A,0xD2,0x04,0x0B,0x0C,0xF9,0x57,0xB2,
++    0x8C,0x89,0x97,0x01,0x10,0x8B,0x00,0x17,0x48,0xB2,0xCC,0xE1,0x07,0x0B,0x12,0xF9,
++    0x96,0xA1,0x02,0x13,0x08,0x31,0x08,0x0B,0x0C,0x11,0x08,0x0B,0x0A,0x51,0x08,0x0B,
++    0x0C,0x49,0x18,0x0B,0x18,0x0B,0x0A,0x01,0x1C,0x0B,0x40,0x4A,0xC2,0x01,0x0F,0x14,
++    0x3F,0x82,0xAB,0x85,0x70,0x62,0x0C,0x01,0x2C,0x01,0x60,0x62,0x50,0x62,0x04,0x01,
++    0xA4,0x82,0x02,0x40,0x50,0x5A,0xC4,0x40,0xC4,0x00,0x54,0x5A,0xC0,0x10,0x1C,0x01,
++    0xC6,0x83,0x01,0x38,0xC1,0x83,0xD0,0xC0,0x94,0x05,0x14,0x2A,0x90,0x06,0x30,0x2A,
++    0x10,0x22,0xCC,0x06,0x32,0x22,0xE0,0x90,0xE6,0xD8,0x92,0xDD,0x5F,0x29,0x98,0x8E,
++    0x59,0xFA,0xDB,0x40,0xA3,0xC2,0xE2,0xB0,0xE6,0x48,0x92,0x4D,0x4E,0x71,0x98,0xDE,
++    0x48,0xD2,0x03,0x01,0xE4,0xD2,0x10,0x52,0x90,0x06,0x30,0x8A,0xE6,0x00,0x92,0x05,
++    0x47,0x71,0x98,0xBE,0x50,0xCA,0x03,0x01,0x00,0x84,0xE0,0xE2,0x43,0xAC,0xD0,0x20,
++    0xC8,0x20,0x03,0xA4,0xE6,0x00,0x92,0x05,0x47,0x71,0x98,0xB6,0x47,0x84,0x40,0xF9,
++    0xCF,0x0E,0x00,0xF9,0x03,0x84,0x48,0x92,0x40,0x84,0x80,0x43,0xE8,0x85,0xAF,0x85,
++    0x40,0x1A,0xC3,0x03,0x38,0x00,0x86,0xAE,0x00,0x01,0x85,0x0F,0xD3,0x7F,0x60,0x02,
++    0x01,0x01,0xE0,0x01,0x8F,0x03,0xB9,0xFF,0xF9,0x47,0x34,0x0A,0x56,0x4A,0xCB,0x01,
++    0x40,0x22,0x83,0x1F,0xD0,0x3F,0x04,0x11,0x88,0x03,0x01,0x01,0x86,0x0F,0xC8,0xB7,
++    0xBC,0xFF,0xFF,0xFF,0xE8,0x85,0xA8,0x85,0x41,0xAA,0xC2,0x01,0xC8,0x03,0x42,0x01,
++    0x8A,0x36,0x40,0x9A,0xC0,0x01,0xEF,0x03,0x40,0x29,0xC8,0x0E,0xBE,0xFF,0xF7,0x7F,
++    0x61,0x7A,0xC2,0x03,0x38,0x00,0xA8,0x0E,0xBE,0xFF,0xF7,0x9F,0xC3,0x03,0xC3,0x03,
++    0x08,0xE9,0x07,0x42,0x82,0x03,0x43,0xC2,0xC0,0x03,0x40,0x01,0x80,0x16,0x80,0x0F,
++    0xE7,0x3F,0x3E,0xE7,0xE8,0x85,0xA8,0x85,0x48,0x32,0x02,0x01,0x02,0x43,0x4C,0x22,
++    0xCC,0x01,0xB7,0x43,0xF0,0x43,0x86,0x0F,0xC8,0x8F,0xEE,0x85,0xA8,0x85,0x33,0x2A,
++    0x48,0x01,0x80,0x4E,0x68,0x01,0x80,0x1E,0x30,0x82,0xC0,0x51,0x20,0x01,0x00,0x5F,
++    0x30,0x82,0x80,0x51,0x20,0x01,0x00,0x3F,0x68,0x01,0x80,0x1E,0xF0,0x80,0x24,0x49,
++    0x18,0x22,0x07,0x0F,0xE0,0x80,0x24,0x51,0x0A,0x01,0xF0,0x0A,0x48,0x01,0xD0,0x06,
++    0x16,0x4A,0x0A,0x40,0x0A,0x01,0xF0,0x8A,0x82,0x27,0xD8,0x57,0x40,0xF9,0xEB,0x06,
++    0x00,0xF9,0x6B,0x01,0x87,0x16,0x08,0xF9,0x88,0x09,0xD0,0x40,0xCB,0x00,0xE8,0x85,
++    0xAC,0x85,0x87,0x3D,0x28,0x01,0x20,0x01,0x01,0x51,0x48,0x92,0x1A,0x42,0xC3,0x00,
++    0x80,0x34,0xC0,0x34,0x01,0x08,0x13,0x39,0xC4,0x00,0x0A,0x90,0xC0,0x10,0x04,0xE1,
++    0x90,0x2C,0xF0,0x82,0x80,0x24,0x30,0x01,0x38,0x01,0x10,0x01,0x90,0x1C,0x90,0x14,
++    0x60,0x01,0x80,0x46,0xF0,0x10,0xDB,0x34,0x04,0x90,0xC2,0xD0,0x1C,0x39,0x09,0xD8,
++    0xC0,0x90,0x36,0xE1,0xF8,0xB2,0x6C,0x01,0x83,0x56,0xF0,0x50,0x1A,0x51,0x18,0xD2,
++    0x5E,0x02,0xC1,0x90,0x1A,0x39,0xC1,0x90,0x0E,0xD8,0xC4,0x90,0x3E,0xE1,0xF8,0xBA,
++    0x60,0x21,0x80,0x4E,0xE0,0x18,0xD3,0x34,0x06,0xD8,0xC2,0x90,0x1C,0x39,0x09,0xD8,
++    0xC0,0x90,0x1E,0xE1,0xF0,0x9A,0x9E,0x1C,0x68,0x69,0x80,0x5E,0xE0,0x50,0x1B,0x51,
++    0x18,0xD2,0x5A,0xA2,0xC2,0x90,0xC6,0x88,0x14,0x39,0x09,0x90,0xC0,0x50,0x0C,0xE1,
++    0xF0,0x8A,0x8A,0x14,0x08,0x09,0x88,0x0C,0x70,0x41,0xD1,0x3E,0x78,0x41,0xD1,0x2E,
++    0xC9,0x1C,0x48,0x41,0xD0,0x16,0xC8,0x14,0x49,0x41,0xD9,0x06,0x08,0x01,0x00,0xEF,
++    0x00,0xE0,0x07,0x01,0x10,0x00,0x00,0x42,0xF8,0x00,0x06,0x42,0x80,0x30,0x02,0x01,
++    0x18,0x00,0x02,0x42,0x80,0x60,0x05,0x00,0x70,0x00,0x04,0x01,0xF8,0xFF,0x07,0x00,
++    0x80,0x50,0x06,0x01,0x08,0x40,0x00,0x01,0x60,0x20,0x02,0x00,0x00,0x60,0x00,0x01,
++    0x00,0x28,0x00,0x01,0x80,0xC0,0x04,0x01,0x00,0x20,0x00,0x01,0x88,0x0C,0x08,0x19,
++    0x86,0x27,0xD0,0x37,0x10,0x82,0xED,0x3E,0x10,0xC2,0xED,0x2E,0xCC,0x1C,0x10,0x42,
++    0xE8,0x16,0xC8,0x14,0x10,0x42,0xE4,0x0E,0x00,0x01,0x80,0x0C,0xC0,0x0C,0x40,0x01,
++    0x80,0x86,0xC8,0x24,0xD6,0x2C,0x78,0x40,0xC2,0x00,0x82,0x00,0xD0,0x48,0x90,0x4D,
++    0x1F,0x8C,0x54,0xFA,0x58,0xFA,0xC7,0x93,0xC0,0xDB,0x18,0xD2,0x80,0x16,0xD0,0x40,
++    0xCC,0x2C,0x18,0x44,0xE7,0x20,0x93,0x25,0x60,0x29,0x90,0x06,0x3B,0x4F,0xE3,0x68,
++    0x90,0x6D,0x6F,0x71,0x92,0x06,0x38,0xF7,0x87,0x3D,0xE8,0x85,0xA8,0xC5,0x2F,0x01,
++    0x40,0xAA,0xFF,0x03,0x81,0x04,0x00,0x5F,0x07,0x31,0x48,0xA2,0x1A,0x42,0xC3,0x00,
++    0x0C,0xC9,0x09,0x48,0xC0,0x30,0x3A,0x11,0xF8,0xBA,0x07,0x21,0xF0,0x82,0x41,0x51,
++    0xD0,0x0E,0x20,0x51,0x00,0x0F,0xC0,0x51,0x96,0x25,0x00,0x19,0x04,0x00,0x14,0x22,
++    0xE8,0x06,0x30,0x22,0x37,0x02,0xC1,0xF9,0xC0,0x89,0x0C,0xF1,0x1F,0x42,0x0A,0xF9,
++    0x88,0x89,0x84,0x27,0xD0,0xAF,0xCB,0x00,0x90,0x05,0x40,0x51,0xD0,0x06,0x00,0x51,
++    0x4C,0x1A,0x17,0x42,0xE8,0x06,0x30,0x42,0x05,0xBC,0x03,0x84,0xE7,0x68,0x93,0x6D,
++    0xC5,0x04,0x10,0x42,0xC7,0x86,0xEE,0xC5,0xAC,0x85,0x87,0x3D,0x00,0xF9,0x87,0x0C,
++    0x00,0x01,0x80,0x04,0x81,0x14,0x18,0x39,0x09,0xD8,0x24,0x39,0x57,0xBA,0x1E,0x22,
++    0x04,0x08,0xC2,0x48,0xC0,0x68,0x0E,0xE1,0xF2,0x4A,0xE3,0x00,0x92,0x05,0x40,0x31,
++    0xD8,0xB6,0x07,0x01,0x80,0x24,0x00,0x01,0x38,0x01,0x28,0x01,0x30,0xF9,0xCF,0x24,
++    0x12,0x51,0x18,0x8A,0x54,0x6A,0xC6,0x48,0x54,0x72,0xC6,0x50,0x90,0x34,0x08,0x01,
++    0x20,0x01,0xF8,0xA2,0x60,0xA1,0xE8,0x0E,0xE1,0xF8,0x93,0xFD,0xC0,0x00,0x91,0x05,
++    0x10,0x62,0xED,0x06,0x35,0x2A,0x11,0xA2,0xD1,0x06,0x30,0x32,0xE2,0x90,0xE4,0x48,
++    0x90,0x4D,0x4E,0x29,0x99,0x66,0x6F,0xE1,0xED,0x16,0x50,0xFA,0x0C,0x01,0xA8,0x8B,
++    0x08,0x29,0x80,0x27,0xD0,0x2F,0x91,0x0D,0xD0,0x40,0x83,0x71,0x40,0xE1,0xC0,0x6E,
++    0xD0,0x80,0x83,0x71,0x40,0xE1,0xC0,0x4E,0x68,0xE1,0xE9,0x3E,0x78,0x21,0xE8,0x2E,
++    0x50,0xA2,0x05,0x01,0x85,0x83,0x40,0x92,0x10,0xD1,0x87,0x13,0xC4,0x14,0x10,0x42,
++    0xD0,0x06,0x88,0x14,0xC5,0x0C,0x10,0x82,0xE8,0x06,0xB0,0x0C,0xC5,0x04,0x10,0x42,
++    0xD0,0x06,0xA8,0x04,0x6D,0x6A,0x75,0x7A,0xC0,0x34,0x18,0x01,0x48,0x01,0xE8,0xBE,
++    0x14,0x01,0xF0,0x12,0x10,0x52,0xDC,0x76,0x61,0x2A,0xC5,0x23,0x60,0x01,0x80,0x16,
++    0xD0,0x90,0x02,0x14,0x01,0xC7,0x50,0xE1,0xD6,0xB6,0x78,0x60,0xC3,0x20,0x83,0x20,
++    0xD8,0x90,0x00,0x14,0x00,0x87,0x50,0x01,0xE8,0x76,0x10,0x09,0x00,0x14,0x00,0x5F,
++    0x14,0x01,0xF0,0x12,0x10,0x52,0xE4,0x16,0xD0,0x90,0x02,0x14,0x00,0x27,0x50,0x01,
++    0xD0,0x16,0x10,0x01,0x18,0x92,0x06,0x14,0xE2,0x00,0xE4,0xD8,0x90,0xDD,0x5E,0x29,
++    0x98,0xA6,0xC6,0x24,0xE6,0x00,0x92,0x05,0x80,0x24,0xC0,0x24,0x44,0x71,0x98,0x16,
++    0x20,0x01,0x00,0x01,0x08,0x01,0x10,0x01,0x94,0x1C,0x50,0x82,0x04,0x18,0xC3,0xD0,
++    0x5E,0x82,0xC4,0xA8,0x30,0x72,0x19,0x01,0x15,0x01,0xF0,0x52,0xC0,0x80,0x90,0x05,
++    0xE0,0x48,0x92,0x4D,0xFD,0x1C,0x10,0xD2,0xE8,0x06,0x90,0x1C,0xAA,0x51,0xE0,0xD8,
++    0x90,0xDD,0x5E,0x71,0x98,0x86,0x87,0x27,0xC8,0x9F,0x95,0x2D,0xC5,0x14,0x10,0x42,
++    0xD0,0x06,0xA8,0x14,0x00,0x01,0x80,0x24,0x68,0x01,0xE8,0xDE,0x3F,0x01,0xF8,0xBA,
++    0x10,0x7A,0xDD,0x96,0x60,0x01,0x80,0x0E,0x60,0x21,0x88,0x16,0xD9,0xC0,0x03,0x84,
++    0x00,0xB7,0x08,0x19,0xC0,0x1C,0x80,0x27,0xCD,0xDF,0x14,0x42,0xD7,0x86,0x78,0x40,
++    0xCA,0x00,0x82,0x00,0xD1,0xC0,0x01,0x84,0x00,0x57,0x78,0x01,0xE8,0x46,0x00,0x09,
++    0x00,0x84,0x01,0x2F,0x01,0x01,0xF0,0x82,0x10,0x42,0xE5,0x0E,0xD9,0x00,0x02,0x84,
++    0xB0,0x51,0xC0,0x24,0xE6,0x00,0x92,0x05,0x80,0x24,0xC0,0x24,0x46,0x71,0x98,0x9E,
++    0xE7,0x20,0x93,0x25,0x65,0x29,0x98,0x66,0x43,0x2A,0x4B,0x32,0xC0,0x03,0xC0,0x4B,
++    0x33,0x22,0x58,0x4A,0x50,0x4A,0x1B,0x62,0x88,0xB6,0x01,0x01,0x4A,0x1A,0x03,0x20,
++    0xC3,0x08,0x63,0x22,0xCB,0x60,0x68,0x1A,0xAA,0x51,0xC8,0x68,0x31,0xF9,0x0C,0xB0,
++    0xC8,0x78,0x34,0x01,0xF8,0xF2,0x3D,0x01,0xFD,0x7A,0x17,0xF2,0xD0,0x3E,0x28,0x01,
++    0xF8,0x2A,0x6B,0xA1,0xE8,0x1E,0x78,0x79,0xEB,0x0E,0x00,0x68,0x02,0x2C,0x61,0xD2,
++    0xA0,0x51,0xC8,0x60,0xC4,0x70,0xC6,0x68,0x0B,0x01,0xF0,0x4A,0x2B,0x01,0xF8,0xAA,
++    0x10,0x4A,0xD5,0x66,0x0B,0x01,0xF0,0x0A,0x48,0xA1,0xE8,0x46,0x68,0x79,0xE8,0x36,
++    0x7B,0x70,0xC6,0xA8,0x83,0x68,0x03,0x70,0xCB,0x68,0xC5,0x48,0x02,0x0C,0xE1,0x00,
++    0x90,0x05,0x46,0x29,0x9C,0x56,0x36,0xFF,0x47,0x01,0x80,0xE6,0x22,0x01,0x40,0x3A,
++    0x00,0x08,0xC3,0x68,0x41,0x3A,0xC2,0x70,0x40,0x32,0x82,0x51,0xC4,0x40,0x09,0xF9,
++    0x0B,0x48,0xC0,0x78,0x10,0x01,0x08,0x01,0xF2,0xD2,0xF5,0x0A,0x10,0x52,0xD4,0x6E,
++    0x01,0x01,0xF0,0x82,0x81,0x2C,0x40,0x41,0xE8,0x46,0x48,0x79,0xEC,0x36,0x00,0x00,
++    0x08,0x29,0x80,0x27,0xC8,0xEF,0xC8,0x2C,0xC1,0x00,0x02,0x84,0x40,0xD2,0x81,0x51,
++    0xC1,0x40,0x49,0xD2,0xC0,0x48,0x1B,0x01,0x17,0x01,0xF0,0xDA,0xF4,0x52,0x14,0x9A,
++    0xD0,0x3E,0x08,0x01,0xF1,0x0A,0x4A,0x41,0xE8,0x1E,0x50,0x79,0xEA,0x0E,0x00,0x48,
++    0x03,0x0C,0xE0,0x20,0x90,0x25,0x67,0x29,0x9B,0x4E,0x36,0x2F,0xA9,0xC5,0x47,0x52,
++    0x17,0x09,0x80,0x01,0xC0,0x0B,0x18,0x8A,0x81,0x0B,0x68,0x3A,0x79,0x22,0x31,0x62,
++    0xA4,0x01,0x06,0x27,0xBB,0xFF,0xEF,0xFF,0x48,0x4A,0x41,0x43,0xE0,0x00,0x02,0x43,
++    0x40,0x42,0xC1,0x03,0x40,0x01,0x80,0x0E,0x05,0xC1,0xB0,0x43,0x40,0xF2,0x80,0x1F,
++    0xE9,0xE7,0x50,0x2A,0x48,0xEA,0x40,0xE2,0x86,0x1F,0xC8,0x3F,0xB9,0xFF,0xEF,0x7F,
++    0x01,0x11,0x88,0x03,0x50,0x02,0x49,0xC2,0x40,0xC2,0x80,0x1F,0xD8,0x37,0x55,0xF2,
++    0x48,0xAA,0x40,0xB2,0x85,0x1F,0xF8,0xE7,0xC8,0x03,0x43,0x01,0x83,0x16,0xC8,0x03,
++    0x40,0x11,0x88,0x26,0x48,0xCA,0x40,0x43,0x10,0x09,0x18,0x82,0x00,0x43,0x48,0x72,
++    0x40,0x72,0x80,0x1F,0xF0,0x47,0x73,0x5A,0xC1,0xCB,0xC1,0x83,0x18,0x42,0x80,0x0E,
++    0x05,0x01,0xA8,0x43,0xBA,0xFF,0xF7,0xC7,0x41,0x8A,0xC0,0x8B,0x09,0x0C,0xC6,0xCB,
++    0x11,0x0C,0xC8,0x4B,0x10,0x0C,0x72,0x22,0xB5,0x01,0xE2,0x8B,0x10,0x0C,0x04,0xCF,
++    0x00,0x48,0x00,0x01,0x00,0x40,0x00,0x01,0x00,0xE0,0x00,0x01,0x08,0x40,0x00,0x01,
++    0x18,0x10,0x00,0x00,0x48,0xE0,0x06,0x00,0x50,0xA0,0x02,0x00,0x50,0x50,0x02,0x00,
++    0x00,0xA0,0x00,0x01,0x00,0x20,0x00,0x01,0x80,0xC0,0x04,0x01,0xF8,0x00,0x06,0x42,
++    0x70,0x40,0x04,0x01,0x48,0xA2,0x40,0x4C,0x10,0x0C,0x4E,0xA2,0x40,0x4B,0x18,0x0C,
++    0xA2,0x48,0x18,0x0C,0xEC,0x4B,0x1D,0x0C,0xBA,0xFF,0xEF,0x57,0x05,0x11,0xA0,0x83,
++    0x32,0x8A,0xC9,0x01,0x40,0x72,0x80,0x1F,0xE9,0x9F,0x31,0x8A,0x12,0x09,0xC8,0x01,
++    0x40,0x5A,0x58,0x62,0x80,0x17,0xE8,0xD7,0xBC,0xFF,0xDF,0x97,0x32,0x8A,0xC9,0x01,
++    0x40,0x3A,0x80,0x0F,0xF0,0xDF,0x82,0x07,0xDF,0x0F,0xBA,0xFF,0xE3,0xE7,0xCE,0x03,
++    0x40,0x31,0x80,0x06,0x3F,0xB7,0xEB,0xC5,0x00,0x60,0x00,0x01,0x00,0xA0,0x00,0x01,
++    0x08,0x40,0x00,0x01,0x30,0x48,0x00,0x00,0xA8,0x85,0x33,0x22,0xF0,0x03,0x87,0x07,
++    0xF2,0x2F,0x46,0x7A,0x2C,0x01,0x00,0x2B,0xB6,0x2B,0x05,0x21,0xAF,0x2A,0xB8,0xFF,
++    0xE5,0xE7,0xA1,0x01,0xCA,0x03,0x33,0x08,0x42,0x52,0x72,0x48,0x1C,0x0B,0x5C,0x0B,
++    0x02,0x48,0x1A,0x0B,0x0B,0x2B,0xCE,0x0B,0x30,0x48,0xA8,0x16,0x0E,0x09,0x04,0x0B,
++    0x1B,0x2B,0xE8,0x85,0xAD,0x85,0x87,0xAD,0x42,0x12,0xC2,0x01,0x42,0x0B,0x40,0x48,
++    0x00,0x48,0x02,0x0B,0x52,0x02,0x4A,0x0A,0x40,0x0A,0x82,0x0F,0xCA,0xB7,0x40,0x0A,
++    0x71,0xFA,0xC1,0x80,0x81,0xA4,0x41,0xEA,0xB6,0xE1,0x81,0x01,0x83,0x9C,0x01,0x47,
++    0x47,0xD2,0xB9,0xFF,0xF9,0x4F,0x66,0xCA,0x52,0x03,0x83,0x01,0xE7,0x03,0x40,0x79,
++    0x81,0x06,0x31,0x12,0x48,0xB2,0x01,0x01,0x58,0x9A,0x81,0x07,0xF9,0x5F,0x36,0x12,
++    0x48,0x9A,0x01,0x09,0x58,0x82,0x81,0x07,0xFB,0x2F,0x56,0x03,0x80,0x01,0xE2,0x03,
++    0x40,0x59,0x8D,0x7E,0xC1,0xA4,0x31,0x8A,0x13,0x01,0xD8,0x1B,0xDB,0x2B,0x19,0x5A,
++    0x40,0x6C,0x40,0x3C,0xD8,0x68,0x07,0x2C,0xE4,0x00,0xE4,0x48,0xE4,0x90,0x92,0x95,
++    0x17,0xD2,0x9C,0xAE,0x52,0x03,0x83,0x01,0xE5,0x03,0x40,0x59,0x81,0x2E,0x50,0x12,
++    0x49,0x12,0x41,0x1A,0x58,0x0D,0x80,0x0F,0xC1,0x07,0xEC,0xA4,0x30,0xA2,0x39,0x01,
++    0x01,0x01,0xF0,0x42,0x0A,0x99,0x18,0x42,0x08,0x51,0x80,0x1F,0xF9,0x8F,0x07,0x44,
++    0x01,0x01,0xF0,0x02,0x0A,0x99,0x18,0x42,0x08,0x51,0x80,0x1F,0xF9,0x4F,0x07,0x04,
++    0xE5,0x68,0xE5,0x20,0xE7,0xF8,0x93,0xFD,0x7F,0x29,0x98,0x4E,0x68,0xB2,0x60,0xA2,
++    0xA0,0xF1,0x3D,0x01,0x01,0x01,0xF0,0x42,0x08,0x51,0x08,0x00,0x86,0x1F,0xF8,0xC7,
++    0x00,0x44,0x01,0x01,0xF0,0x02,0x09,0x51,0x08,0x00,0x80,0x1F,0xF9,0x8F,0x06,0x04,
++    0xE5,0x68,0xE5,0x20,0xE7,0xF8,0x93,0xFD,0x7F,0x29,0x98,0x5E,0x40,0x0D,0x80,0x07,
++    0xD9,0xDF,0xC1,0x9C,0xC8,0x03,0x42,0x31,0x81,0x96,0x84,0xAD,0xE8,0x85,0x07,0x00,
++    0x10,0x00,0x00,0x42,0x00,0x01,0x00,0x42,0x80,0xC0,0x04,0x01,0x00,0xE0,0x00,0x01,
++    0x08,0x40,0x00,0x01,0x48,0xE0,0x06,0x00,0x58,0x30,0x03,0x01,0x48,0xFA,0xFF,0x53,
++    0x84,0x13,0xF8,0x53,0x80,0x13,0x32,0x52,0x96,0x01,0xCE,0x93,0x80,0x13,0xCC,0x4B,
++    0x83,0x0B,0x3E,0x82,0xA8,0xC5,0xF7,0x34,0x37,0x22,0x40,0xC2,0xFD,0x03,0x16,0x02,
++    0xC9,0xFE,0x01,0x21,0x6B,0xB2,0x1F,0x02,0xCB,0x28,0x02,0x99,0x09,0x00,0xC2,0x40,
++    0x2A,0xA1,0xF8,0x2A,0x3E,0xB1,0xF8,0x3A,0x48,0x09,0x88,0x1E,0x0F,0xF9,0x8F,0x09,
++    0xD8,0x48,0x92,0x6D,0x50,0x09,0x88,0x1E,0x0A,0xC9,0x08,0x48,0xD8,0x48,0x96,0x7D,
++    0xCE,0x0B,0xCC,0x13,0x0A,0x48,0x00,0x90,0x18,0x8A,0x80,0xCB,0x8A,0x48,0x81,0xCB,
++    0x8C,0xC8,0x81,0xCB,0x39,0xD0,0x09,0x48,0x78,0x90,0x18,0x8A,0x86,0xCB,0xE6,0xD8,
++    0xE0,0xE8,0x5A,0x04,0x08,0xA1,0x80,0x1F,0xF8,0x4F,0x83,0x51,0x97,0x05,0x46,0xF9,
++    0x97,0x56,0x58,0x02,0xE8,0xCA,0x30,0x52,0x94,0x51,0x10,0x12,0x91,0x16,0x80,0x43,
++    0xA8,0xC2,0x00,0x1F,0x80,0x4B,0x01,0x0F,0x01,0xF9,0x87,0x43,0xC2,0x83,0xE9,0x00,
++    0x87,0x83,0xE9,0xC5,0xAC,0x85,0x87,0x2D,0x36,0x01,0x00,0xBD,0x40,0x03,0x80,0x14,
++    0x44,0x92,0xFE,0x1B,0x10,0x09,0x00,0x01,0x4E,0xA2,0x66,0xAA,0xC5,0x6B,0x68,0x59,
++    0x82,0x16,0xE0,0x00,0x17,0x02,0x9D,0xCE,0x00,0xF9,0x87,0x43,0x58,0x01,0x80,0xBE,
++    0x30,0x01,0x48,0x15,0x03,0x01,0x20,0x99,0x5B,0x4A,0x0E,0x20,0x01,0x77,0x28,0x21,
++    0x1F,0x2A,0xC2,0x68,0xC9,0x68,0xD1,0x6B,0x68,0x09,0x88,0x2E,0x83,0x43,0xE0,0xB0,
++    0x92,0xB5,0xE7,0x48,0x70,0x09,0x80,0x1E,0xE6,0x00,0x92,0x05,0x17,0x82,0x9C,0x76,
++    0x73,0x01,0x80,0x16,0x60,0x0A,0x6E,0x15,0x3D,0x01,0x40,0xE2,0x80,0x01,0x87,0x1C,
++    0x00,0x0F,0x79,0x01,0x88,0x9E,0x50,0x0D,0x90,0x04,0x10,0x01,0xC1,0x43,0x31,0x1A,
++    0x37,0x8A,0xB8,0xFF,0xFB,0xBF,0xE3,0x68,0xC4,0x1C,0xC0,0x03,0x4E,0x00,0x0E,0x00,
++    0x1B,0x82,0x89,0x03,0x05,0x59,0x8D,0x03,0xEB,0x20,0xE5,0x20,0x00,0x4F,0x50,0x0D,
++    0x90,0x04,0x10,0x01,0xC1,0x43,0x31,0x1A,0x37,0x8A,0xB8,0xFF,0xFB,0x1F,0xE3,0x68,
++    0xEB,0x20,0xE3,0xF8,0x95,0xFD,0x17,0xBA,0x98,0xDE,0xC6,0x1C,0x1C,0x01,0xC4,0x03,
++    0x48,0x08,0x4E,0x01,0x80,0x9E,0x70,0x01,0x81,0x3E,0x80,0x03,0xC0,0x1C,0xC8,0x03,
++    0x85,0x03,0x03,0x59,0x85,0x03,0xE5,0x20,0x01,0x3F,0x80,0x03,0xC0,0x1C,0xC8,0x03,
++    0x83,0x03,0x8B,0x1B,0x05,0x59,0x8D,0x03,0xEB,0x20,0xE5,0x20,0x00,0x27,0x70,0x09,
++    0xCD,0x16,0x00,0x59,0x83,0x03,0xE1,0x20,0x37,0x02,0xB9,0xFF,0xFC,0x7F,0x41,0xEA,
++    0x42,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,0x4A,0xDA,0x44,0x43,0x1A,0xC2,0x00,0x43,
++    0x61,0xD2,0x44,0x03,0x42,0x00,0x02,0x00,0x07,0x03,0x01,0xF9,0x80,0x89,0x84,0x1F,
++    0xE9,0x6F,0x46,0x03,0x08,0x09,0x18,0x42,0x00,0x03,0x81,0x2D,0xEF,0x85,0xAF,0xFD,
++    0x80,0x0D,0xFC,0x54,0x30,0x32,0x30,0x62,0x6F,0x42,0xAC,0x01,0x50,0x09,0x88,0x4E,
++    0x00,0x0F,0x80,0x0F,0xC1,0x6F,0xC0,0x43,0x37,0x00,0xAA,0xD6,0xC5,0x43,0x09,0xF9,
++    0x01,0x42,0x80,0x43,0x04,0x09,0x30,0x22,0x51,0x3A,0x04,0x8F,0x60,0x01,0xC1,0x2E,
++    0xF7,0x00,0x0B,0x01,0x1A,0x42,0x08,0x83,0x30,0x0A,0x01,0x17,0x02,0xF9,0x0F,0x83,
++    0x08,0x01,0x19,0x01,0x08,0x9B,0x04,0x01,0x00,0x4F,0x78,0x01,0x88,0x16,0x18,0x01,
++    0x00,0x9B,0x06,0x17,0xC6,0x9B,0x01,0x9B,0xCA,0xB0,0xE7,0x00,0x94,0x05,0x14,0x42,
++    0x9B,0x9E,0x37,0x02,0x40,0x01,0x80,0x26,0x04,0xA1,0x00,0x83,0x04,0x01,0x30,0x22,
++    0x00,0x0F,0x00,0x21,0x03,0x83,0xD4,0x00,0x92,0x25,0x44,0x83,0x08,0x01,0x1C,0x42,
++    0x01,0x83,0xC2,0x43,0x37,0x00,0xAA,0xE6,0xC5,0x43,0x09,0xF9,0x01,0x42,0x80,0x43,
++    0x66,0x01,0x88,0x5E,0xC0,0x24,0x40,0x09,0x88,0x7E,0x05,0x01,0x02,0x83,0x44,0x83,
++    0x08,0x01,0x1C,0x42,0x05,0x83,0x3A,0x47,0xAC,0x9D,0x87,0x1D,0x20,0x01,0x00,0x01,
++    0x80,0x0C,0x70,0x15,0x44,0xEA,0xF2,0x03,0xEE,0x00,0x92,0x3D,0x6F,0xDA,0xAA,0x01,
++    0x00,0xAF,0x81,0x07,0xF9,0xAF,0xC5,0x43,0x30,0x00,0xA2,0x1E,0x44,0xBA,0xF2,0x03,
++    0x17,0xC2,0x9D,0xB6,0x44,0xAA,0xF2,0x03,0x10,0xC2,0x9D,0x06,0x21,0x11,0xC0,0x43,
++    0x08,0xF9,0x05,0x42,0x82,0x43,0x41,0xC2,0x46,0x0B,0x14,0x79,0x00,0x8A,0x48,0x09,
++    0x88,0x9E,0x08,0x01,0x0E,0x0B,0x44,0x0B,0x83,0x8B,0xE1,0xB0,0xE7,0x20,0x93,0x25,
++    0x60,0x11,0x88,0x56,0x30,0x5A,0xD3,0xCB,0xD4,0x1C,0x10,0x8A,0x8A,0x2E,0xD0,0xCB,
++    0xD4,0x24,0x10,0x8A,0x88,0x0E,0x08,0x09,0x8F,0x0C,0x08,0x01,0x08,0x0B,0x0A,0x01,
++    0x08,0x0B,0x0C,0x81,0x02,0x0B,0x44,0x0B,0x10,0x01,0x1C,0x8A,0x00,0x0B,0x62,0x11,
++    0x88,0x4E,0xC6,0x0C,0x39,0x0F,0x4B,0xEA,0x60,0x54,0x80,0x13,0x12,0x01,0x80,0x13,
++    0xE4,0x4B,0x86,0x0B,0x4A,0x0A,0x8A,0x01,0x5E,0x53,0x84,0x13,0x58,0x53,0x8A,0x13,
++    0x12,0xA9,0x88,0x13,0x14,0x19,0x88,0x13,0x4E,0x53,0x8E,0x13,0x48,0x53,0x94,0x13,
++    0x4A,0x4B,0x92,0x0B,0x0C,0x31,0x90,0x0B,0x3F,0x82,0xAB,0x85,0x80,0x4D,0x34,0x22,
++    0x30,0x01,0x00,0x01,0x80,0x2C,0x38,0x01,0x48,0x62,0xD9,0x43,0xDA,0x4B,0x1A,0x42,
++    0x81,0x14,0x40,0x5A,0x80,0x71,0x80,0x24,0xC0,0x71,0x80,0x1C,0x60,0x09,0x80,0x0E,
++    0x60,0x29,0x88,0x7E,0x60,0x09,0x88,0x26,0x73,0x6A,0xE1,0x80,0x81,0x2C,0x78,0x6A,
++    0x01,0x27,0x70,0x6A,0xE0,0x80,0x83,0x2C,0x79,0x52,0xF9,0xC1,0x47,0x35,0xB8,0xFF,
++    0xF0,0xEF,0x01,0x3F,0x60,0x21,0x88,0x2E,0x70,0x42,0x41,0x35,0xBD,0xFF,0xFF,0xDF,
++    0x7B,0x22,0xB9,0x11,0x6F,0xCA,0xA8,0x01,0xC5,0x43,0x09,0xF9,0x01,0x42,0x80,0x43,
++    0xC1,0x43,0x09,0x01,0x19,0x42,0x80,0x43,0x42,0xD2,0x40,0x0B,0x10,0x01,0x1A,0x8A,
++    0x00,0x0B,0x42,0xCA,0x44,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,0x48,0xBA,0x40,0x43,
++    0x10,0x09,0x18,0x82,0x00,0x43,0x08,0x09,0x07,0x01,0xBC,0xFF,0xF8,0xAF,0x42,0x09,
++    0x88,0x5E,0x62,0x21,0x88,0x56,0x12,0x09,0x91,0x04,0x30,0x82,0x18,0x01,0xC8,0x14,
++    0xBF,0xFF,0xF7,0xAF,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x59,0x40,0x35,0x30,0x9A,
++    0xBF,0xFF,0xF7,0x6F,0x10,0x09,0x90,0x04,0x10,0x01,0x00,0xCF,0x00,0xE0,0x00,0x01,
++    0x08,0x40,0x00,0x01,0x80,0x00,0x06,0x01,0x00,0xF8,0x07,0x00,0x80,0x30,0x02,0x01,
++    0x30,0x04,0x05,0x08,0x00,0x00,0x06,0x42,0x80,0x01,0x06,0x42,0xF8,0x00,0x06,0x42,
++    0x18,0x60,0x05,0x01,0x70,0x70,0x06,0x01,0x50,0x20,0x07,0x01,0x68,0x60,0x02,0x01,
++    0x09,0x29,0x30,0xC2,0x37,0x9A,0xB8,0xFF,0xF0,0x57,0x16,0x09,0x90,0x04,0x10,0x01,
++    0x0E,0x71,0x40,0x0A,0x37,0x9A,0xB8,0xFF,0xF0,0x17,0x16,0x09,0x90,0x04,0x10,0x01,
++    0x08,0x29,0x30,0x9A,0xC7,0x24,0xB8,0xFF,0xF0,0xD7,0x15,0x09,0x90,0x04,0x10,0x01,
++    0x08,0x29,0x18,0x09,0xC7,0x1C,0xB8,0xFF,0xF1,0x97,0x05,0x9F,0x60,0x09,0x80,0x0E,
++    0x61,0x29,0x88,0x7E,0x10,0x11,0x90,0x04,0x11,0x09,0x30,0x82,0x18,0x01,0xC8,0x14,
++    0xBD,0xFF,0xF7,0x2F,0x10,0x11,0x90,0x04,0x10,0x01,0x30,0x9A,0xC8,0x14,0xC0,0x2C,
++    0xBC,0xFF,0xF7,0xEF,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x21,0x40,0x35,0x30,0x9A,
++    0xBC,0xFF,0xF7,0xAF,0x10,0x09,0x90,0x04,0x11,0x01,0x08,0x31,0x30,0xC2,0x31,0x9A,
++    0xBC,0xFF,0xF7,0x6F,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x29,0x30,0x9A,0xC0,0x24,
++    0xBC,0xFF,0xF7,0x2F,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x29,0x18,0x09,0xC0,0x1C,
++    0xBB,0xFF,0xF7,0xEF,0xC6,0x43,0x09,0xF9,0x01,0x42,0x80,0x43,0x40,0xDA,0x44,0x0B,
++    0x42,0x48,0x02,0x48,0x04,0x0B,0x40,0xD2,0x0A,0x01,0x0F,0x0B,0x0C,0x01,0x00,0x0B,
++    0x44,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,0x87,0x4D,0xE8,0x85,0xAC,0x85,0x63,0xAA,
++    0xC8,0x03,0x43,0x09,0x83,0x16,0xC8,0x03,0x40,0x29,0x88,0x86,0x46,0x8A,0xC4,0x01,
++    0x82,0x1F,0xC8,0xDF,0x69,0x82,0xC4,0x43,0x40,0x11,0x98,0x2E,0xCF,0x03,0xBB,0xFF,
++    0xF8,0x67,0x00,0x01,0x83,0x43,0xE9,0x85,0xE1,0x00,0x82,0x43,0xEB,0x85,0xCB,0x03,
++    0x40,0x21,0x88,0x26,0xB8,0xFF,0xFF,0x0F,0x03,0x19,0x88,0x03,0xEB,0x85,0xCB,0x03,
++    0x47,0x19,0x80,0xDE,0xC8,0x03,0x43,0x31,0x84,0xC6,0x47,0x12,0xC4,0x01,0xFE,0x03,
++    0x40,0x01,0x88,0x3E,0x41,0xFA,0x83,0x01,0xD0,0x0B,0x48,0x31,0x9C,0x76,0xC7,0x03,
++    0x37,0x00,0xA8,0x5E,0x44,0xDA,0xC3,0x01,0xE8,0x03,0x44,0x01,0x8F,0x36,0xBF,0xFF,
++    0xEB,0xCF,0xEC,0x85,0xA8,0xC5,0x27,0x01,0x30,0x1A,0x00,0x09,0x4B,0xAA,0x6B,0xBA,
++    0x30,0x01,0x59,0x51,0x80,0xE6,0xE1,0x4E,0x79,0xAA,0xC3,0xD3,0x85,0x1F,0xE8,0xFF,
++    0x61,0x52,0x20,0x09,0x39,0x61,0x62,0x52,0x71,0x61,0x62,0x92,0x40,0x6A,0x13,0x31,
++    0xC2,0x01,0x56,0x03,0x80,0x01,0x5A,0xC9,0x80,0xAE,0xE1,0x4E,0x59,0x59,0x80,0x56,
++    0x59,0x61,0x80,0x66,0x59,0x69,0x88,0xBE,0x02,0x29,0x88,0x43,0x21,0x09,0x00,0x9F,
++    0x59,0xD1,0x80,0x6E,0x59,0x01,0x89,0x7E,0x88,0x53,0x22,0x09,0x08,0x59,0xA5,0x0B,
++    0x00,0x57,0x01,0x39,0x89,0x43,0x02,0x3F,0x86,0x07,0xE8,0xA7,0x00,0x27,0x19,0x12,
++    0x81,0xD3,0x01,0x0F,0x00,0x41,0x18,0x12,0x80,0xD3,0x01,0xEF,0x02,0x11,0x88,0x43,
++    0x20,0x09,0x00,0xCF,0x02,0x01,0x88,0x43,0x41,0x43,0x19,0x82,0x00,0x43,0x01,0x9F,
++    0x88,0x43,0x22,0x09,0x00,0x87,0x00,0x19,0x88,0x43,0x22,0x09,0x00,0x67,0x00,0x21,
++    0x88,0x43,0x22,0x09,0x02,0x47,0x88,0x53,0x26,0x09,0x08,0x69,0xA0,0x0B,0x00,0x1F,
++    0x88,0x53,0x22,0x09,0x08,0x79,0xA7,0x0B,0x60,0x01,0x80,0x66,0x40,0x6A,0x42,0x0B,
++    0x30,0x48,0xA8,0x2E,0x08,0x81,0x06,0x0B,0x08,0x81,0x02,0x0B,0x08,0x81,0x00,0x0B,
++    0x45,0x43,0x19,0x82,0x07,0x43,0xE9,0xC5,0xAC,0x8D,0x87,0x15,0x40,0x32,0x82,0x0C,
++    0x46,0x02,0xC2,0x01,0xDA,0x2B,0xD8,0x33,0x0C,0x01,0xB0,0x0B,0x61,0x02,0xC2,0x0B,
++    0x10,0xF9,0x05,0x8A,0x81,0x0B,0xC1,0x0B,0x10,0x01,0x19,0x8A,0x81,0x0B,0x49,0xEA,
++    0x8A,0x01,0x46,0x53,0x18,0x01,0x1A,0xD2,0x01,0x53,0x52,0xAA,0x44,0x8B,0x1A,0x01,
++    0x1A,0xCA,0x00,0x8B,0x48,0x8A,0x41,0x53,0x18,0x09,0x18,0xD2,0x02,0x53,0x50,0x03,
++    0x80,0x01,0xE2,0x0B,0x49,0x79,0x87,0xAE,0xE6,0x03,0x40,0x69,0x88,0x16,0x09,0xA9,
++    0x07,0x91,0xB8,0xFF,0xE8,0x4F,0x47,0x09,0x89,0xDE,0x31,0x42,0x1A,0x82,0x03,0x38,
++    0x15,0x09,0x90,0xCD,0x90,0x04,0x18,0x01,0xC7,0x0C,0xB8,0xFF,0xE9,0x47,0x44,0x5A,
++    0x10,0x09,0x90,0x04,0x15,0x01,0x90,0xCD,0x37,0x9A,0xB8,0xFF,0xE8,0x07,0xC4,0x14,
++    0x15,0x09,0xC8,0x48,0xE8,0x48,0x90,0x04,0x00,0x48,0x12,0x01,0x1F,0x09,0xB8,0xFF,
++    0xE8,0xB7,0x03,0xF7,0x08,0xA1,0x00,0x91,0xBE,0xFF,0xEF,0x37,0x40,0x09,0x88,0xC6,
++    0x18,0xAA,0x13,0x09,0x20,0x40,0x63,0x08,0x90,0x04,0x30,0x9A,0xC7,0x0C,0xB8,0xFF,
++    0xE8,0x37,0x03,0x77,0x08,0xB1,0x00,0x91,0xBD,0xFF,0xEF,0xB7,0x40,0x09,0x88,0x46,
++    0xC0,0x14,0x10,0x09,0xC8,0x48,0xED,0x48,0x00,0x48,0x32,0x9A,0x97,0x04,0xB8,0xFF,
++    0xE9,0xB7,0xC2,0x03,0x08,0xF9,0x06,0x42,0x80,0x03,0x41,0x42,0x42,0x0B,0x40,0x48,
++    0x00,0x48,0x02,0x0B,0x47,0x32,0x08,0x01,0x08,0x0B,0x0A,0x01,0x02,0x0B,0x44,0x0B,
++    0x10,0x01,0x1C,0x8A,0x07,0x0B,0xEA,0xF5,0x70,0x00,0x04,0x01,0xF8,0x00,0x06,0x42,
++    0x80,0x01,0x06,0x42,0x00,0xE0,0x06,0x01,0x00,0x00,0x00,0x01,0x10,0x00,0x00,0x42,
++    0x00,0xE0,0x07,0x01,0x00,0x00,0x00,0x42,0x50,0x20,0x07,0x01,0x08,0x20,0x02,0x01,
++    0x52,0x2A,0x44,0x83,0x04,0x83,0x42,0x2A,0xF7,0x0B,0x4C,0xF9,0x94,0x16,0xF0,0x0B,
++    0xE4,0x48,0xB2,0x0B,0xF0,0x03,0x44,0xC1,0x90,0x0E,0x00,0x01,0x03,0x83,0x3C,0x82,
++    0x4C,0xFA,0x4B,0x53,0x5C,0xEA,0xE3,0xC3,0x1C,0x12,0x0C,0x53,0x10,0x43,0x02,0x09,
++    0xB3,0xC3,0x3C,0x82,0xAB,0x85,0x40,0xD2,0x84,0x01,0x42,0x0B,0x10,0x01,0x1C,0x8A,
++    0x03,0x0B,0x54,0xC2,0x4B,0xAA,0x43,0xC2,0x87,0x1F,0xC0,0x27,0xEF,0x85,0xA8,0xC5,
++    0x47,0x92,0x83,0x01,0xC3,0x0B,0x70,0xAA,0x30,0x48,0xAC,0x46,0xC2,0x0B,0x10,0x01,
++    0x18,0x8A,0x80,0x0B,0x44,0x83,0x0B,0x01,0x1B,0x42,0x04,0x83,0xE8,0xC5,0x0F,0x01,
++    0x0D,0x8B,0x45,0x9B,0x66,0x4A,0x03,0x79,0x01,0x1A,0x30,0x2A,0xAB,0x01,0x69,0x04,
++    0x50,0x13,0x5B,0x09,0x80,0x6E,0x59,0x29,0x80,0x46,0x58,0x41,0x8B,0xDE,0x93,0x4B,
++    0x46,0x9B,0x3F,0xD8,0x88,0x16,0x00,0x81,0x07,0x83,0xED,0xC5,0x0B,0x8B,0x4D,0x22,
++    0x10,0x42,0x8C,0x16,0x07,0x29,0x05,0x83,0x00,0x3F,0xE0,0x92,0x02,0x93,0xE7,0x00,
++    0x93,0x05,0x2C,0x04,0x40,0x89,0x9A,0x06,0x2A,0x0C,0x43,0xCA,0x40,0x13,0x08,0x41,
++    0x18,0x52,0x04,0x13,0x44,0x13,0x1C,0x52,0x00,0x13,0x14,0xA1,0x04,0x93,0x45,0x13,
++    0x1C,0x52,0x04,0x13,0x44,0x13,0x1C,0x52,0x04,0x13,0x44,0x13,0x1C,0x52,0x00,0x13,
++    0xEA,0xC5,0x5F,0xA2,0xD0,0x7B,0x43,0xDC,0x7B,0x11,0x90,0x56,0x78,0x01,0x88,0x36,
++    0x42,0x83,0x57,0x82,0x02,0x84,0x40,0x82,0x13,0x03,0x2B,0x0C,0x07,0x1F,0x44,0x83,
++    0x12,0xD0,0x48,0x62,0xC4,0x80,0x90,0x3D,0x06,0x7C,0x00,0x89,0x11,0x00,0xD0,0xC0,
++    0x40,0x01,0xC1,0x96,0x97,0xC5,0xBF,0xFF,0xF2,0xAF,0x43,0x42,0x13,0x3A,0x84,0x96,
++    0x40,0x32,0x82,0x41,0x13,0x3A,0x8C,0x76,0x00,0x09,0x80,0x07,0xC8,0x3F,0x06,0xC1,
++    0xB2,0x03,0x4D,0x1A,0x00,0x09,0x80,0x43,0x01,0x2F,0x43,0xC2,0x82,0x01,0xCE,0x03,
++    0x41,0x01,0x88,0x2E,0x46,0xEA,0xC1,0x31,0x10,0x3A,0x8C,0xAE,0x40,0xEA,0x41,0x0B,
++    0x40,0xCA,0x71,0x50,0x80,0x01,0x82,0x13,0x62,0x50,0x80,0x13,0x54,0x50,0x80,0x13,
++    0x80,0x0B,0xC6,0x0B,0xC4,0x13,0xC2,0x48,0xC6,0x13,0xC4,0x1B,0xC4,0x90,0xC6,0x48,
++    0x88,0x29,0x55,0x50,0x8A,0x13,0x88,0x0B,0x00,0x69,0x18,0x00,0xD2,0xC0,0x41,0x81,
++    0xC3,0x16,0x28,0x04,0x02,0xFF,0x01,0x27,0x06,0x01,0x18,0x02,0x29,0x04,0x03,0xD7,
++    0x41,0x6A,0xC1,0xC0,0x40,0x19,0xC1,0x1E,0x29,0x04,0x43,0x62,0x11,0x03,0x03,0x97,
++    0x41,0x4A,0xC1,0x81,0xC1,0xC0,0x41,0x01,0xC3,0x26,0x28,0x04,0x41,0x3A,0xC1,0x01,
++    0x11,0x03,0x03,0x47,0x00,0x69,0x18,0x00,0xD1,0xC0,0x41,0xB1,0xC3,0x1E,0x29,0x04,
++    0x00,0x0F,0x79,0xDA,0x10,0xC2,0x85,0xF6,0x40,0xBB,0xA7,0xBA,0x45,0xDA,0xC0,0xD1,
++    0x10,0x1A,0x8C,0x7E,0x6A,0x04,0x43,0x61,0x8B,0x66,0x50,0x1B,0xE0,0xFA,0x50,0x7A,
++    0x94,0x01,0x7A,0x01,0x88,0x16,0x00,0x09,0xA8,0x83,0x04,0x1F,0xE0,0xC2,0x40,0x01,
++    0x8C,0x06,0xA8,0x8B,0x6A,0x04,0xE3,0x00,0x93,0x05,0x2C,0x04,0x40,0x89,0x9A,0x16,
++    0x06,0x01,0x18,0x02,0x2B,0x04,0xD3,0x43,0xE3,0x00,0x92,0x43,0x05,0x81,0x00,0x83,
++    0xED,0xC5,0x07,0x8B,0xE8,0xC5,0x07,0x00,0x10,0x00,0x00,0x42,0x00,0xE0,0x00,0x01,
++    0xF8,0x00,0x06,0x42,0x80,0xC0,0x04,0x01,0x08,0x40,0x00,0x01,0x80,0x01,0x06,0x42,
++    0xF8,0xFF,0x07,0x00,0x00,0x10,0x00,0x01,0x80,0x30,0x02,0x01,0x88,0x36,0x00,0x00,
++    0x00,0x20,0x00,0x01,0x00,0xA0,0x00,0x01,0x77,0x81,0xF8,0xFF,0xF8,0x02,0x07,0x00,
++    0xA8,0x85,0x80,0x07,0xC8,0xBF,0x65,0x32,0xC8,0x03,0x43,0x01,0x80,0x26,0x40,0x31,
++    0x8F,0xD6,0xBF,0xFF,0xD7,0xFF,0x3B,0xBF,0xBE,0xFF,0xCF,0x07,0x38,0xA7,0x07,0x00,
++    0x00,0xE0,0x06,0x01,0xAF,0xC5,0x77,0x62,0x03,0x01,0x87,0x83,0x01,0x09,0x80,0x83,
++    0x0F,0x01,0x81,0x8B,0x05,0x19,0x80,0x83,0x03,0x41,0x89,0x83,0x07,0x69,0x89,0x83,
++    0x05,0x69,0x88,0x83,0x11,0x02,0x32,0xAA,0xA9,0x01,0x06,0x44,0x04,0xF9,0x87,0x89,
++    0x20,0x84,0x01,0x09,0x34,0x62,0xE1,0x01,0x93,0x03,0x91,0x03,0x05,0x41,0x90,0x03,
++    0x17,0x51,0x90,0x13,0x11,0xA1,0x98,0x13,0x98,0x0B,0x0D,0x81,0x99,0x0B,0xA7,0x03,
++    0x3B,0x01,0xA0,0xBB,0x09,0x71,0x98,0x8B,0x0B,0x29,0x98,0x8B,0x17,0x71,0x98,0x93,
++    0x99,0x8B,0xA5,0xBB,0xA1,0x83,0x05,0x81,0xA0,0x83,0x07,0x51,0x8F,0x03,0x01,0xB1,
++    0x8D,0x03,0x8B,0x3B,0x8B,0x3B,0x9F,0x0B,0x05,0x99,0x28,0x84,0x07,0xF9,0x87,0x09,
++    0x10,0x44,0x01,0xC9,0x0B,0x00,0x12,0x44,0x02,0x19,0x18,0x00,0x0E,0x43,0x43,0x5A,
++    0x0A,0x43,0x05,0x01,0xB9,0x43,0x31,0x02,0x0D,0x51,0x80,0x11,0x83,0x1F,0xD0,0x17,
++    0x01,0xB1,0x97,0x43,0x1B,0xF1,0x90,0x5B,0x89,0x7B,0x33,0x02,0x82,0x01,0xB2,0x3B,
++    0xB8,0x3B,0x08,0xC1,0xB8,0x0B,0x0A,0x51,0xBE,0x0B,0x14,0x41,0x31,0x0A,0x88,0x01,
++    0x0F,0x54,0x12,0xF9,0x94,0x99,0x0A,0x54,0x16,0xC1,0xBE,0x13,0x10,0x41,0x81,0x53,
++    0x12,0x11,0x87,0x53,0x80,0x5B,0x14,0x51,0x91,0x13,0x12,0x41,0x93,0x13,0x14,0x21,
++    0x92,0x13,0x16,0xA9,0x08,0x14,0x16,0x71,0x9A,0x13,0x10,0x69,0xA0,0x13,0x10,0x21,
++    0xA6,0x13,0x12,0x41,0x10,0x14,0x12,0x31,0xBF,0x93,0x37,0xBC,0xB0,0x3B,0x1C,0x21,
++    0x33,0x12,0x90,0x01,0x90,0x9B,0x1C,0x31,0x96,0x9B,0x12,0x99,0x08,0x94,0x11,0xA1,
++    0x80,0x53,0x16,0x51,0x8E,0x53,0xB0,0x3B,0x12,0x21,0x8C,0x53,0x53,0x42,0x05,0x54,
++    0x14,0x09,0x88,0x53,0x10,0x51,0x90,0x53,0x17,0x11,0xA0,0x13,0x08,0x21,0xA8,0x0B,
++    0x0A,0xC1,0xAB,0x0B,0xA8,0x0B,0x1C,0x01,0x33,0x0A,0xC8,0x01,0xA0,0x5B,0xAE,0x5B,
++    0x22,0xF1,0x88,0x01,0xBA,0x63,0xB8,0x63,0x24,0xE1,0xB9,0x63,0x26,0x41,0xB8,0x63,
++    0x80,0x13,0x08,0xB1,0x80,0x0B,0x0A,0x19,0x84,0x0B,0x4C,0xD2,0x00,0x0B,0x92,0x1B,
++    0x4C,0xCA,0xC4,0x01,0x38,0x0B,0x88,0x91,0x3E,0x0B,0x8A,0xE1,0x38,0x0B,0x0C,0xE1,
++    0x40,0xB2,0x84,0x1F,0xCC,0xBF,0x47,0xAA,0x09,0xE1,0xC0,0xC1,0x87,0x1F,0xC8,0x97,
++    0x4C,0x8A,0x44,0x9A,0xCE,0x11,0x03,0x0B,0xCC,0x71,0x00,0x0B,0x88,0xA1,0x08,0x0B,
++    0x8A,0xA1,0x08,0x0B,0xCA,0xE1,0x01,0x0B,0xC8,0xC1,0x01,0x0B,0x8C,0x61,0x0D,0x0B,
++    0xCA,0x81,0x15,0x0B,0xF8,0x48,0x10,0x0B,0xFE,0x48,0x08,0x0B,0xE9,0xC5,0xAF,0x85,
++    0x0C,0x01,0x60,0x0A,0x47,0x02,0xA4,0x61,0xF8,0x1B,0x06,0x77,0x02,0x21,0x19,0x42,
++    0xCB,0x28,0x00,0x99,0x12,0x79,0x08,0x00,0xC4,0x40,0x89,0x13,0x16,0x01,0x88,0x13,
++    0x94,0x13,0x10,0x14,0x12,0x14,0xE6,0x48,0x94,0x4D,0x16,0x5A,0xC0,0x76,0x07,0x01,
++    0x13,0xF9,0x2F,0x89,0x08,0x68,0x03,0x37,0x00,0x08,0xCA,0x48,0xCC,0x48,0xAA,0x53,
++    0xAA,0x53,0xE6,0x00,0x94,0x05,0x16,0x1A,0xC1,0xB6,0xEF,0x85,0xA3,0x85,0x51,0x72,
++    0x90,0x01,0x0E,0x01,0x26,0x8C,0xD0,0x01,0xBC,0x8B,0xB8,0x8B,0x36,0x9A,0x98,0x01,
++    0x8A,0xCB,0x0C,0xCC,0x9E,0xCB,0x88,0xCB,0x2C,0x09,0xB0,0xAB,0xA8,0x8B,0x34,0xA2,
++    0xA1,0x01,0xCD,0x1B,0xB0,0x9B,0x36,0x9A,0x9A,0x01,0xA9,0xCB,0x9A,0x01,0xA9,0xEB,
++    0xA8,0xCB,0xA8,0xAB,0x28,0x41,0x89,0xAB,0x8B,0x0B,0x57,0x32,0x88,0x8B,0x46,0x09,
++    0x8C,0x16,0xA8,0xCB,0xE5,0x85,0x39,0x97,0xE3,0x85,0x39,0x82,0x0B,0x08,0x42,0x12,
++    0x41,0x13,0x18,0x01,0x04,0xD2,0x90,0x41,0x04,0x13,0x10,0xD0,0x1A,0x8A,0x08,0x0B,
++    0x40,0x0B,0x42,0x0B,0x14,0x41,0x18,0x8A,0x00,0x0B,0x08,0x01,0x03,0x0B,0x3C,0x82,
++    0xAA,0x85,0x40,0xD2,0x40,0x0B,0x30,0x48,0xAE,0x2E,0x08,0x81,0x02,0x0B,0x08,0x81,
++    0x00,0x0B,0x08,0x81,0x02,0x0B,0x48,0xAA,0x8C,0x01,0x46,0x53,0x38,0x90,0x78,0x90,
++    0x04,0x53,0x44,0x53,0x18,0x81,0x19,0xD2,0x02,0x53,0x5C,0x8A,0x12,0x09,0x06,0xD3,
++    0x16,0x91,0x01,0x13,0x44,0x7A,0x42,0x23,0x10,0x61,0x18,0xA2,0x02,0x23,0x44,0x23,
++    0x1A,0xA2,0x00,0x23,0x4C,0x23,0x1A,0xA2,0x08,0x23,0x4A,0x23,0x18,0xA2,0x08,0x23,
++    0x40,0x23,0x1E,0xA2,0x02,0x23,0x46,0x43,0x10,0x01,0x1A,0x82,0x04,0x43,0x02,0xD1,
++    0x07,0xC3,0x00,0x01,0x08,0xC3,0xEA,0x85,0x40,0x12,0x42,0x13,0x08,0x09,0x18,0x52,
++    0x00,0x13,0x48,0x13,0x18,0x52,0x0C,0x13,0x4C,0x13,0x1A,0x52,0x0E,0x13,0x42,0x13,
++    0x1E,0x52,0x00,0x13,0x39,0x82,0x43,0xE2,0x58,0x0B,0x10,0x21,0x18,0x8A,0x18,0x0B,
++    0x5A,0x0B,0x10,0x01,0x18,0x8A,0x18,0x0B,0x5C,0x13,0x08,0x01,0x18,0x52,0x18,0x13,
++    0x40,0x92,0x11,0x01,0x80,0x01,0x06,0x13,0x40,0x13,0x1A,0x52,0x01,0x13,0x4A,0x72,
++    0x41,0x43,0x10,0x01,0x18,0x82,0x00,0x43,0x38,0x82,0xAB,0x85,0x08,0x09,0x00,0x31,
++    0x81,0x07,0xD0,0xF7,0x08,0x11,0x00,0x21,0x81,0x07,0xD0,0xD7,0x00,0x09,0x80,0x07,
++    0xD0,0xB7,0x02,0x31,0x82,0x07,0xD0,0x9F,0x00,0x21,0x80,0x07,0xD0,0x87,0x82,0x07,
++    0xD0,0x2F,0xEB,0x85,0xA8,0x85,0x43,0xF2,0x4A,0xBA,0xC0,0x91,0x11,0x43,0x0A,0x91,
++    0x80,0x1F,0xC8,0x07,0x40,0xD2,0x08,0x51,0x80,0x41,0x81,0x1F,0xC7,0xEF,0xBF,0xFF,
++    0xF0,0x4F,0x02,0x09,0xBA,0xFF,0xFF,0x17,0x07,0xA1,0xB8,0xFF,0xFF,0x3F,0xBB,0xFF,
++    0xFF,0xBF,0xBB,0xFF,0xFF,0xC7,0xBD,0xFF,0xFF,0x3F,0xBD,0xFF,0xF8,0x77,0x66,0x8A,
++    0x29,0x01,0x80,0x2B,0x08,0x2B,0x41,0x72,0x09,0x71,0x80,0x91,0x87,0x1F,0xC0,0x17,
++    0x0B,0x2C,0x81,0x2B,0x87,0x2B,0x85,0x2B,0x8B,0x2B,0x89,0x2B,0x05,0x51,0x88,0x03,
++    0x0F,0x2C,0x8B,0x2B,0x0B,0x2C,0xED,0x85,0x00,0xE0,0x00,0x01,0xC8,0x21,0x01,0x00,
++    0x70,0x02,0x01,0x00,0xF8,0xFF,0x07,0x04,0x68,0x02,0x03,0x00,0x70,0x70,0x06,0x01,
++    0x80,0xC0,0x04,0x01,0x00,0x20,0x00,0x01,0x10,0x00,0x00,0x42,0x00,0x00,0x00,0x42,
++    0x80,0x01,0x06,0x42,0xF8,0x00,0x06,0x42,0x18,0x00,0x02,0x42,0xA8,0x85,0x80,0x07,
++    0xC8,0xCF,0xEE,0x85,0xAF,0x85,0xB8,0xFF,0xE8,0x9F,0xEF,0x85,0xA8,0x7D,0x80,0x04,
++    0x88,0x0C,0xC0,0x0C,0x80,0x14,0xC0,0x04,0x83,0x1C,0x30,0x42,0x40,0x7E,0x80,0x25,
++    0xE8,0x05,0x00,0x00,0xAC,0xFD,0x87,0x1D,0x30,0x32,0x00,0x01,0x82,0x14,0x00,0x9F,
++    0x44,0xDA,0x0E,0x01,0x0C,0x0B,0x26,0x01,0xC2,0x14,0x00,0x28,0x7F,0xC2,0x4E,0xC3,
++    0x1F,0x02,0x09,0xC3,0xD0,0x6C,0x90,0x04,0x14,0x09,0x08,0x01,0x30,0x82,0xD9,0x64,
++    0x86,0x17,0xE0,0x1F,0xF8,0x82,0x33,0x0A,0xCF,0x99,0x49,0xC9,0x99,0x3E,0x40,0x91,
++    0xE7,0x16,0x48,0xC3,0x1F,0x02,0x0D,0xC3,0x40,0x20,0x63,0x01,0x88,0x36,0xD7,0x6C,
++    0x90,0x04,0x10,0x09,0x09,0x01,0x34,0x82,0xD8,0x64,0x80,0x17,0xE3,0x77,0xFD,0xA2,
++    0xD0,0x6C,0x90,0x04,0x14,0x09,0x08,0x01,0x30,0x82,0xD9,0x64,0x85,0x17,0xE0,0x2F,
++    0xF8,0xBA,0xD3,0x6C,0x90,0x04,0x10,0x09,0x09,0x01,0x34,0x82,0xD8,0x64,0x80,0x17,
++    0xE5,0xE7,0x14,0x3A,0xE9,0x16,0x30,0x02,0x30,0xE2,0x31,0x3A,0xFD,0x82,0x13,0xC2,
++    0xE3,0x0E,0x98,0xBA,0x05,0x17,0x10,0x02,0xDB,0x06,0x98,0xA2,0x46,0xC2,0x4D,0x03,
++    0xDE,0x8A,0x0B,0x00,0xC0,0x00,0xCA,0x24,0x00,0x44,0xC0,0x24,0xE0,0x00,0x84,0x24,
++    0xC2,0x14,0xE0,0x00,0x90,0x05,0x86,0x14,0xC8,0x2C,0xC0,0x14,0x15,0x42,0x9C,0x3E,
++    0x87,0x3D,0xE8,0x85,0xAC,0xFD,0x87,0x7D,0x30,0xA2,0x30,0xFA,0xD8,0x0B,0x8F,0x6C,
++    0xD8,0x0B,0x8B,0x64,0x40,0x01,0x80,0x6E,0x48,0x52,0x05,0x99,0x07,0x43,0x12,0xF9,
++    0x58,0x3A,0x95,0x81,0x10,0xD3,0x06,0x43,0x00,0xC1,0x83,0x17,0xF8,0xFF,0xF1,0x84,
++    0xB0,0xE1,0x01,0xCF,0x40,0x1A,0x0D,0x19,0x04,0x0B,0x0A,0x19,0x05,0x0B,0x48,0x12,
++    0xC2,0x84,0xC0,0x30,0x11,0x01,0x30,0xDA,0x30,0x8A,0x00,0x09,0x82,0x17,0xC0,0xC7,
++    0x29,0x01,0x30,0x1A,0x14,0x09,0x08,0x01,0x40,0x1D,0xB8,0x04,0x82,0x17,0xE0,0x6F,
++    0xE7,0x68,0x93,0x6D,0x6F,0x91,0x99,0xA6,0x48,0xB2,0x44,0x43,0x10,0x11,0x18,0x82,
++    0x01,0x43,0x30,0x02,0x80,0x01,0x35,0x2A,0xC8,0x03,0x32,0x00,0xAC,0xEE,0x49,0x9A,
++    0x00,0x01,0x80,0x43,0x31,0x12,0x31,0xCA,0x00,0x11,0x80,0x0F,0xF9,0xF7,0x34,0x1A,
++    0xB8,0x04,0x08,0x01,0x00,0x11,0xD0,0x84,0x84,0x17,0xC0,0x47,0x49,0x42,0xD4,0x43,
++    0x08,0x43,0x2A,0x01,0xC2,0x64,0x00,0x00,0x80,0x74,0x00,0xBF,0x31,0xDA,0x31,0x52,
++    0x08,0x01,0x00,0x09,0x81,0x17,0xC0,0x27,0xB8,0x0C,0xA0,0x04,0x30,0x8A,0x41,0x1D,
++    0xD8,0x84,0xD0,0x64,0xB9,0xFF,0xFF,0xF7,0xC4,0x74,0xC8,0x30,0x09,0x09,0x30,0xDA,
++    0x30,0x52,0x31,0x42,0x80,0x17,0xC0,0xA7,0xE7,0x68,0x93,0x6D,0xC4,0x6C,0x10,0x2A,
++    0x99,0x26,0x37,0x1A,0xB8,0x04,0x08,0x01,0x00,0x19,0xD0,0x84,0x82,0x17,0xC0,0xF7,
++    0x31,0x12,0x31,0xCA,0x00,0x01,0x80,0x0F,0xFB,0x47,0x4B,0x92,0x40,0x43,0x10,0x11,
++    0x18,0x82,0x04,0x43,0x87,0x9D,0xE8,0x85,0xAC,0xFD,0x87,0x1D,0x30,0x7A,0x50,0x01,
++    0x80,0x16,0x00,0x01,0x80,0x0C,0x00,0x0F,0x00,0x09,0x80,0x0C,0x2A,0x01,0x00,0x47,
++    0xCD,0x64,0x00,0x40,0xC1,0x30,0x32,0x52,0x08,0x19,0xD8,0x6C,0xC0,0x0C,0x80,0x0F,
++    0xF9,0x3F,0x07,0x41,0x85,0x17,0xF0,0xD7,0x20,0x09,0xC0,0x34,0x80,0x01,0x84,0x14,
++    0x60,0x81,0x99,0x36,0x0A,0xF9,0x47,0xF2,0x88,0x11,0x18,0x0B,0x42,0x08,0x1B,0x0B,
++    0x02,0x0F,0x40,0xDA,0x1F,0x23,0x02,0xF9,0x4F,0xCA,0x82,0x89,0x88,0x01,0x12,0x43,
++    0x00,0x11,0x80,0x17,0xF0,0x1F,0xC5,0x14,0xF0,0x03,0x46,0x01,0x80,0x3E,0x00,0x51,
++    0x84,0x17,0xF0,0xE7,0x40,0x83,0x41,0x03,0x30,0x00,0xA8,0x86,0x07,0x5F,0x00,0xF9,
++    0x4C,0x7A,0x82,0x89,0x88,0x01,0x12,0x43,0x00,0x09,0x80,0x17,0xF1,0x7F,0x44,0x83,
++    0x40,0x03,0x30,0x00,0xA3,0x1E,0xE0,0x20,0x93,0x25,0x67,0xF9,0xC9,0x86,0x06,0xE4,
++    0xE1,0xF8,0x35,0x52,0x08,0x09,0xD8,0x6C,0xC0,0x0C,0x80,0x0F,0xFB,0x4F,0xE5,0x68,
++    0x90,0x6D,0xC7,0x1C,0x15,0x2A,0x9C,0x9E,0x3F,0x17,0xA9,0x85,0x80,0x3D,0x34,0x7A,
++    0x34,0xA2,0x00,0xD9,0xEF,0x02,0x0E,0xF9,0x88,0x09,0x40,0x01,0x80,0x0E,0x30,0x72,
++    0x00,0x0F,0x30,0x19,0x13,0xB0,0xD9,0xC3,0x81,0x34,0xD8,0xC3,0x80,0x2C,0x98,0x1C,
++    0xC2,0x34,0x00,0x00,0xC0,0x00,0x86,0x24,0x45,0xAA,0x11,0x81,0x00,0x13,0x1A,0x0B,
++    0x28,0x01,0x00,0x67,0x4D,0x03,0x01,0x48,0xC0,0x00,0x42,0x03,0x01,0x33,0x30,0x1A,
++    0x30,0x52,0x09,0x09,0x00,0x01,0x80,0x0F,0xFB,0xDF,0xE3,0x68,0x90,0x6D,0xC7,0x34,
++    0x17,0x2A,0x9C,0x7E,0x28,0x01,0x00,0x67,0x4D,0x03,0x03,0x48,0xC0,0x00,0x42,0x03,
++    0x00,0x33,0x08,0x09,0x31,0x1A,0x31,0x52,0x30,0x42,0x80,0x0F,0xFB,0x4F,0xE3,0x68,
++    0x90,0x6D,0xC7,0x2C,0x17,0x2A,0x9C,0x7E,0x48,0x0B,0xA1,0x0C,0x89,0x04,0x30,0xDA,
++    0x10,0x09,0xC8,0x1C,0xC7,0x34,0xB8,0xFF,0xFB,0xFF,0x4A,0x0B,0x89,0x04,0x30,0xDA,
++    0x10,0x01,0xA0,0x0C,0xC8,0x24,0xC0,0x2C,0xBA,0xFF,0xFF,0xB7,0x48,0xC2,0x00,0x01,
++    0x88,0x01,0x12,0x43,0x48,0xB2,0x18,0x43,0x37,0x57,0xAE,0xC5,0x30,0x1A,0x30,0x42,
++    0x30,0xBA,0xD8,0x23,0xD8,0x2B,0x4A,0xB2,0xC0,0xC8,0x8A,0x04,0x30,0xD2,0x31,0xCA,
++    0x87,0x0F,0xF8,0xDF,0x30,0x01,0x00,0x3F,0x09,0x09,0x30,0xDA,0x30,0x92,0x31,0x42,
++    0x81,0x0F,0xF8,0xB7,0xE7,0xB0,0x93,0xB5,0x17,0x32,0x9D,0xAE,0xC8,0x04,0x10,0x01,
++    0x18,0x01,0x00,0x4F,0x00,0x01,0x00,0x1F,0x82,0x5B,0xE0,0x48,0xE6,0x00,0x92,0x05,
++    0x17,0x42,0x9D,0xCE,0xE6,0x90,0x92,0x95,0x17,0x12,0x9D,0x9E,0xE8,0xC5,0x07,0x00,
++    0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0x48,0xE0,0x06,0x00,0x00,0xD0,0x00,0x01,
++    0x60,0x20,0x02,0x00,0x49,0x32,0x41,0x2A,0x05,0x43,0x9E,0xFF,0x7F,0x04,0x3A,0xF7,
++    0x94,0x15,0x3A,0x00,0x77,0x18,0x06,0xF9,0x04,0xC2,0x3C,0x48,0x74,0x48,0x00,0xCA,
++    0x50,0x01,0xD0,0x5E,0x38,0x90,0x78,0x90,0xD4,0x41,0x40,0x98,0x54,0xE2,0x00,0xD8,
++    0xC6,0xD0,0x4C,0x9B,0x18,0x1A,0x1C,0x5A,0x0B,0x9B,0x3E,0x82,0x40,0x98,0x54,0xCA,
++    0x04,0xD8,0xC4,0xD0,0x44,0x9B,0x18,0x1A,0x18,0x5A,0x00,0x9B,0x3A,0x82,0x93,0x05,
++    0x36,0x10,0x76,0x90,0x0C,0x09,0x00,0x8A,0x48,0x00,0x52,0x9A,0x04,0x00,0xC4,0x00,
++    0x03,0x0B,0x38,0x82,0x96,0x05,0x32,0x10,0x70,0x90,0x0E,0x09,0x00,0x8A,0x54,0x72,
++    0x4C,0x00,0x02,0x00,0x94,0x01,0xC4,0x00,0x03,0x0B,0x38,0x82,0xB3,0x15,0x3B,0x82,
++    0xFB,0x85,0x39,0x82,0x40,0x32,0x48,0x0B,0x10,0x21,0x18,0x8A,0x0B,0x0B,0x38,0x82,
++    0x48,0x1A,0x48,0x43,0x14,0x21,0x18,0x82,0x0B,0x43,0x38,0x82,0x07,0x20,0x28,0xD0,
++    0x68,0x07,0x00,0x07,0x20,0x07,0x00,0x07,0x08,0x07,0x00,0x07,0xAC,0xFD,0x87,0x4D,
++    0xD0,0x94,0x30,0x22,0xF8,0x43,0x80,0x0C,0xF8,0x6B,0xC6,0x64,0x08,0x01,0x80,0x0B,
++    0x00,0x01,0x00,0x8F,0x0A,0x21,0x19,0x0A,0x18,0x99,0xCB,0x48,0x0E,0xD8,0xC2,0x48,
++    0xC8,0x4B,0x4C,0x79,0x80,0x36,0x80,0x83,0xE0,0x90,0xCA,0x64,0xD8,0x64,0xC0,0x4B,
++    0xE0,0x48,0x82,0xCB,0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0x5E,0xC0,0x64,0xC0,0x03,
++    0x80,0x44,0x40,0x01,0x88,0x0E,0x80,0x6D,0xE8,0x85,0xC7,0x44,0x40,0x09,0x88,0x1E,
++    0xC0,0x0C,0x40,0x09,0x8F,0x06,0x38,0xB7,0x00,0x01,0x80,0x34,0x80,0x2C,0xC8,0x44,
++    0xC4,0x0C,0x10,0x0A,0x88,0x96,0x02,0x01,0x30,0x01,0x08,0x01,0x88,0x1C,0x88,0x14,
++    0x1C,0xC9,0x09,0xD8,0x00,0x4F,0x10,0x31,0x18,0x52,0xCA,0x90,0xC2,0x90,0x46,0xBC,
++    0xC4,0xC0,0x41,0x94,0xCA,0xB0,0xE4,0x48,0x90,0x4D,0xD6,0x0C,0x17,0x8A,0x9C,0x96,
++    0xC8,0x0C,0x80,0x17,0xF0,0x6F,0x82,0x24,0x30,0x82,0xC9,0x0C,0x82,0x17,0xF0,0x47,
++    0x30,0x32,0x08,0x01,0x01,0x01,0x00,0x07,0x1A,0x99,0x0B,0xD8,0x02,0x0F,0xE0,0x48,
++    0x91,0x4D,0x16,0x21,0x18,0x52,0xCA,0x90,0xC4,0x90,0xCE,0x93,0x57,0x79,0x80,0xB6,
++    0x12,0x21,0x19,0x52,0xCE,0x90,0xC0,0x98,0x3E,0xF1,0xF8,0xFA,0xDF,0x1C,0xC0,0xD8,
++    0x98,0x1C,0x18,0xE9,0x0E,0xD8,0xC6,0x98,0x14,0x01,0xF0,0xD2,0xDE,0x14,0xC0,0x90,
++    0x92,0x14,0xE0,0x48,0x92,0x4D,0xE6,0x00,0x90,0x05,0xD6,0x44,0x16,0x12,0xC4,0xDE,
++    0xC8,0x44,0xC0,0x1C,0x80,0x17,0xF0,0xE7,0x30,0x3A,0xC8,0x44,0xC0,0x14,0x80,0x17,
++    0xF0,0xBF,0xC8,0x24,0xD8,0x48,0x8E,0x34,0xD0,0x80,0x81,0x2C,0x08,0x01,0x10,0x01,
++    0x00,0x77,0x00,0x01,0x33,0x5A,0x18,0x5A,0xF2,0x5C,0x00,0xD8,0xC8,0xD8,0x04,0x1F,
++    0x04,0x30,0x9A,0xD2,0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0xCE,0xE6,0x48,0x92,0x4D,
++    0x17,0x4A,0x9D,0x76,0x08,0x01,0x10,0x01,0x03,0xE7,0x19,0x99,0x08,0xD8,0x02,0x0F,
++    0xE6,0x48,0x92,0x4D,0x02,0x21,0x19,0x42,0xCC,0x00,0x30,0x22,0xC0,0x00,0x86,0x3C,
++    0xC8,0x03,0x44,0x79,0x80,0xA6,0x07,0x01,0x00,0x2F,0xD9,0x3C,0x34,0xF1,0xF8,0xF2,
++    0xD9,0x34,0x38,0xC9,0xC0,0xB0,0x1F,0x31,0x18,0x1A,0xCA,0xD8,0x0E,0xF8,0xCD,0xD8,
++    0x47,0xFC,0xDA,0xB0,0xAB,0x06,0x10,0xB2,0x95,0xB5,0x35,0xB2,0x37,0xE9,0x08,0xB0,
++    0x20,0x32,0x3B,0x01,0xF8,0xBA,0xF7,0x2C,0x45,0xDC,0xCC,0xF0,0xD0,0x98,0xAF,0x06,
++    0x10,0xDA,0x32,0xB2,0x18,0x72,0xFB,0x5C,0x07,0xB0,0xCB,0xB0,0x22,0x9A,0x03,0x38,
++    0x9A,0x9A,0xE7,0x00,0x90,0x05,0xDE,0x0C,0x16,0xC2,0x9C,0xB6,0xE6,0x48,0x92,0x4D,
++    0xE6,0x90,0x92,0x95,0xC0,0x64,0xC0,0x03,0x15,0x82,0xC4,0xF6,0xC0,0x64,0xC8,0x0C,
++    0xC4,0x03,0x10,0x42,0xC9,0x06,0x38,0xF7,0xC1,0x0C,0x38,0xE7,0xAC,0x85,0x87,0x3D,
++    0x34,0x22,0x00,0x91,0xD4,0x02,0x34,0x22,0x01,0xC1,0xF0,0x02,0x18,0x71,0x80,0x34,
++    0xF0,0x1A,0x9F,0x2C,0xD0,0x00,0x96,0x05,0x1F,0xD1,0xF0,0x1A,0x2B,0x81,0xF8,0x2A,
++    0x32,0xF2,0xDC,0xD8,0x90,0xDD,0xA8,0x24,0xC0,0x2B,0x6F,0x09,0x8D,0x16,0x10,0x04,
++    0x10,0x1C,0x07,0x6F,0x55,0x3C,0x05,0xE8,0xC7,0x68,0x51,0x04,0x07,0x30,0xC4,0x98,
++    0xD9,0x68,0x97,0x6D,0xD0,0xC0,0x90,0x1D,0x84,0x40,0x85,0xD8,0x17,0x04,0x15,0x1C,
++    0x4B,0x81,0x80,0xF6,0xE9,0x2C,0xC0,0x40,0x02,0x28,0xCA,0x00,0xEA,0x34,0xC8,0x00,
++    0x80,0x00,0x94,0x05,0xEF,0x24,0xC0,0x58,0x02,0xE8,0xCA,0xE8,0x37,0x9A,0xC3,0x58,
++    0x80,0xD8,0x94,0xED,0x90,0x01,0x46,0x01,0xD0,0x0E,0x00,0x01,0x00,0x27,0x50,0x9C,
++    0x10,0x1A,0xD4,0x0E,0x00,0x81,0xF0,0x82,0x68,0x01,0xD0,0x0E,0x28,0x01,0x00,0x27,
++    0x55,0x9C,0x12,0x5A,0xD0,0x0E,0x28,0x91,0xF8,0xAA,0xD2,0x2C,0xD0,0x90,0xF0,0xB0,
++    0xD2,0x06,0x10,0x92,0x06,0x98,0xC2,0xB8,0xD2,0x24,0xD8,0x90,0xF0,0x98,0xD0,0x06,
++    0x15,0x92,0xC2,0xF8,0x7E,0xD0,0xCF,0x90,0x18,0x90,0x66,0x90,0x58,0x01,0xD0,0x06,
++    0x12,0xDA,0x02,0xF8,0xC8,0xD8,0x76,0x01,0xD3,0x06,0x10,0xB2,0xCE,0xD8,0x7C,0xF0,
++    0xC6,0x98,0x1F,0xD8,0x60,0xF0,0x48,0x41,0x80,0x0E,0x48,0x49,0x88,0x2E,0x48,0x49,
++    0x8A,0x1E,0x20,0x88,0x63,0x50,0x20,0x88,0x63,0x70,0x30,0x0A,0x8B,0x0C,0x28,0x12,
++    0xCB,0x06,0x30,0x12,0xCC,0x0C,0x10,0x72,0xC8,0x06,0xF0,0x0C,0xDB,0x2C,0x30,0x0A,
++    0xD0,0x48,0x34,0x7A,0x1C,0xCA,0x02,0x58,0xC4,0x48,0x36,0x72,0x19,0x51,0x30,0xCA,
++    0xF3,0x1A,0x07,0xF8,0xCA,0x48,0x1E,0x5A,0x32,0x8A,0xC3,0xC8,0x1B,0x82,0x32,0x12,
++    0x46,0xB8,0xCA,0x00,0x02,0x00,0xC6,0x00,0x36,0x0A,0x03,0x48,0x88,0x1C,0x80,0x17,
++    0xE8,0xBF,0x80,0x14,0xD0,0x24,0xC0,0x0C,0xD8,0x00,0x34,0x0A,0x1C,0x82,0x02,0x10,
++    0xC0,0x00,0x14,0x61,0xF2,0x12,0x05,0x58,0xC2,0x48,0x1E,0x52,0xC3,0x80,0x18,0xAA,
++    0x00,0x07,0x00,0x67,0xCE,0x48,0x07,0x48,0xC0,0x40,0xC8,0x1C,0x80,0x17,0xE8,0x07,
++    0xCB,0x2C,0x08,0x0C,0xCD,0x24,0x08,0x0C,0xCF,0x14,0x08,0x0C,0x10,0x04,0x81,0x3D,
++    0xEF,0x85,0xAF,0xF5,0x30,0x3A,0xC0,0x44,0x60,0xD2,0xCF,0xE0,0x2F,0x31,0x70,0xCA,
++    0x1F,0xAA,0xC2,0x68,0xF5,0x21,0xC9,0x68,0x06,0x90,0xC2,0x90,0x59,0xAA,0xDF,0x81,
++    0xC6,0xB0,0xFE,0x13,0x31,0xB2,0x34,0xDA,0x32,0x3A,0xB8,0x01,0x30,0x12,0xB8,0x0C,
++    0x92,0x01,0xBE,0x01,0x59,0x09,0x88,0x4E,0x01,0x01,0x00,0x17,0xC0,0x0B,0x49,0x79,
++    0x89,0xE6,0x40,0x4C,0x0B,0x0C,0x47,0x5C,0x14,0x1C,0x31,0xE2,0xC1,0x9B,0x89,0x1B,
++    0xC3,0x9B,0x8B,0x1B,0x1B,0x0C,0x35,0x1A,0x19,0x1C,0x27,0x0C,0x23,0x1C,0x0B,0x0C,
++    0x09,0x1C,0x45,0x4C,0x1B,0x0C,0x41,0x4C,0x19,0x0C,0x83,0x03,0x0F,0x09,0x80,0x0B,
++    0x88,0x0B,0xFD,0x8B,0x90,0x0B,0x09,0x01,0x90,0x0B,0x03,0x27,0xA2,0x21,0xE1,0x00,
++    0x93,0x05,0x2E,0x82,0x9B,0xD6,0x2E,0x82,0x94,0xF6,0x03,0x2F,0x1A,0x21,0x19,0xCA,
++    0xC8,0x60,0x08,0x41,0x89,0x04,0x40,0x4C,0x18,0x0C,0x09,0x11,0xF3,0x4A,0x1B,0x0C,
++    0x35,0x62,0xCC,0x0B,0x48,0x09,0x88,0xAE,0x08,0xC1,0x18,0xE1,0xF7,0x0A,0xF3,0x1A,
++    0xD0,0x48,0xAE,0x06,0x14,0x4A,0x92,0x4D,0x30,0x72,0x1C,0xF1,0xF3,0x1A,0x37,0x0A,
++    0xD0,0x48,0xAE,0x06,0x14,0x4A,0x92,0x4D,0xE3,0xDB,0x21,0x8A,0x10,0xCA,0xCC,0x0E,
++    0x0D,0x01,0x88,0x0B,0x09,0xC1,0x18,0x01,0xF7,0x0A,0xF3,0x1A,0xD0,0x48,0xAE,0x06,
++    0x14,0x4A,0x92,0x4D,0x30,0x62,0x0C,0xD1,0x1B,0x11,0xF1,0x0A,0xF6,0x1A,0xD7,0x48,
++    0xAA,0x06,0x10,0x4A,0x24,0x0A,0x93,0x4D,0x30,0x62,0xDC,0x0C,0xC4,0x0B,0xE7,0xDB,
++    0xE4,0xD8,0x12,0xCA,0xC8,0x7E,0xF8,0x8B,0xEE,0xDB,0x01,0xCA,0x28,0x0A,0xCB,0x56,
++    0xD6,0x0B,0x4B,0x41,0x92,0x0E,0xE0,0x48,0x91,0x0B,0xD3,0x0B,0xFC,0x9B,0x10,0xCA,
++    0x92,0x0E,0xE0,0x48,0x91,0x0B,0xD1,0x0B,0x28,0x0A,0xCB,0xA6,0xDF,0x0C,0xC0,0x0B,
++    0xE2,0xDB,0xE4,0xD8,0x10,0xCA,0xCC,0x76,0xCA,0x0B,0x37,0x50,0xE2,0xCB,0x73,0x90,
++    0xF4,0x48,0x12,0x52,0x89,0x0E,0x08,0x01,0x80,0x0B,0x35,0x12,0x09,0x81,0x30,0x02,
++    0xBC,0xFF,0xF7,0xE7,0x00,0xDF,0xD8,0x0C,0xC4,0x0B,0xE7,0xDB,0xE4,0xD8,0x12,0xCA,
++    0xC8,0x1E,0xF8,0x8B,0xEE,0xD3,0x01,0x8A,0x91,0x0B,0x59,0x0C,0x23,0x0C,0x59,0x0C,
++    0x20,0x0C,0x33,0x12,0x30,0x02,0xC9,0x04,0xBC,0xFF,0xF7,0x47,0x03,0x01,0x90,0x03,
++    0xD0,0x03,0x41,0x01,0x80,0x1E,0x00,0x07,0x02,0x3F,0xF1,0x00,0x97,0x03,0xC1,0x03,
++    0x40,0xF9,0x93,0x0E,0xE7,0x00,0x82,0x03,0x43,0x44,0x15,0x04,0x03,0x19,0x80,0x03,
++    0xE4,0xC3,0x83,0x01,0x89,0x03,0xCF,0x03,0xC2,0x8B,0xD1,0x00,0xE0,0x00,0x42,0x11,
++    0xC3,0x2E,0xC8,0x03,0xC2,0x8B,0xD3,0x00,0xE0,0x00,0x42,0x11,0xCF,0x4E,0xC0,0x03,
++    0x40,0x11,0x98,0x36,0xCA,0x0C,0xE0,0x4B,0x10,0x42,0xC4,0x16,0x07,0x01,0x80,0x03,
++    0x89,0x03,0xC7,0x83,0x8B,0x03,0xC1,0x83,0x8F,0x03,0xEB,0xF5,0xAC,0x85,0x37,0xE2,
++    0x34,0x2A,0xAB,0x01,0x4A,0x5C,0x27,0xD8,0x67,0xE0,0x40,0xF9,0x88,0x0E,0x00,0x01,
++    0xE9,0x85,0x1F,0x21,0x1B,0xC2,0x5A,0xFA,0xC6,0x00,0xC4,0x00,0x1A,0x31,0x18,0xCA,
++    0xC3,0x48,0x54,0xE2,0xD4,0x21,0xC1,0x50,0x0A,0xA1,0xF0,0x0A,0x48,0x01,0xD0,0x06,
++    0x10,0x4A,0x1A,0xB1,0xF0,0x1A,0x5E,0x01,0xD2,0x06,0x10,0xDA,0xC3,0x48,0x5E,0xB2,
++    0x10,0xCA,0x9C,0x06,0x08,0x01,0x30,0x71,0x44,0x9C,0xF8,0x32,0xD8,0xD8,0xAC,0x06,
++    0x10,0xDA,0x32,0x81,0x44,0x94,0xFA,0x32,0xD8,0x90,0xAC,0x06,0x14,0x92,0xC2,0xD0,
++    0x11,0x12,0x9D,0x0E,0xC8,0x33,0x74,0x09,0x8B,0x26,0xE0,0x5B,0xCA,0x3B,0xF6,0xD8,
++    0x10,0xFA,0xDC,0xBE,0x70,0x09,0x88,0x3E,0xDC,0x5B,0x11,0x5A,0x9E,0x26,0xC0,0x03,
++    0x40,0xF1,0xC0,0x0E,0x40,0x51,0x90,0x6E,0x70,0x09,0x88,0x1E,0x30,0x02,0x5B,0x04,
++    0x40,0xC1,0x98,0x3E,0x70,0x09,0x88,0x16,0x04,0x00,0x13,0x82,0xCD,0x16,0x00,0x00,
++    0x10,0x82,0xC4,0x0E,0x07,0x01,0xE8,0x85,0x07,0x09,0xE8,0x85,0xAC,0xFD,0x87,0x5D,
++    0x30,0xB2,0x0C,0x01,0x28,0x01,0x00,0x01,0x80,0x14,0xC0,0xA4,0xF8,0x23,0x06,0x01,
++    0x30,0x22,0x84,0x34,0x00,0x27,0xD0,0x64,0x02,0xF9,0xA7,0x82,0xE6,0x48,0x92,0x4D,
++    0x17,0x0A,0x9D,0xC6,0xD3,0x74,0x28,0x92,0xC0,0x26,0xC0,0x74,0x83,0x24,0x30,0x82,
++    0x80,0x1C,0x00,0x1F,0x30,0x82,0x83,0x24,0xC0,0x74,0x80,0x1C,0x00,0x01,0x80,0x2C,
++    0x00,0xD7,0x1A,0x01,0x03,0xB7,0x32,0x02,0x06,0xC2,0x3E,0x00,0x8A,0x86,0x42,0x32,
++    0x80,0x3C,0x00,0x01,0xD0,0xA4,0xF0,0x5C,0xF8,0x93,0x90,0x54,0x33,0xD2,0x18,0x12,
++    0x05,0xB8,0xCA,0xD0,0x90,0x4C,0x00,0x6F,0xF6,0x34,0x00,0x32,0x38,0x90,0x8F,0x3E,
++    0xF2,0x4C,0x00,0x38,0xD8,0xB2,0xFF,0x3C,0x10,0xF2,0x95,0x0E,0xB0,0x3C,0x30,0x0A,
++    0xE6,0x00,0x92,0x05,0xD4,0x54,0x10,0x12,0xC1,0x76,0x77,0xBA,0x02,0x01,0x00,0x78,
++    0xB8,0x44,0x00,0x87,0x36,0x3A,0x03,0x3A,0x38,0xF8,0x8F,0x56,0x33,0x3A,0x18,0x3A,
++    0xD3,0x5C,0x00,0xF8,0xC0,0xF8,0xD5,0x44,0xD5,0xFA,0x15,0xBA,0xC1,0x0E,0x30,0xF2,
++    0x32,0x2A,0xE0,0x00,0x93,0x05,0x2E,0x82,0x9C,0x66,0x17,0xEA,0x88,0xA6,0xC0,0x14,
++    0xC8,0x00,0x84,0x14,0xC2,0x2C,0xE0,0x00,0x90,0x05,0x86,0x2C,0xC2,0x64,0xA0,0x2A,
++    0x31,0x09,0x30,0x82,0xD4,0x34,0x00,0x42,0x1C,0x82,0x90,0x05,0x85,0x34,0x00,0x72,
++    0x30,0x02,0x1B,0x32,0x94,0x85,0x35,0x22,0xD0,0x24,0xC0,0x2C,0x10,0x82,0x84,0x1E,
++    0xE6,0xD8,0x92,0xDD,0x2D,0x9A,0x9B,0x36,0xD0,0x24,0xC0,0x2C,0x15,0x82,0x9C,0x06,
++    0xC0,0x14,0x80,0x3C,0x10,0x01,0x00,0x01,0x0B,0x01,0x30,0x5A,0x80,0xCB,0x18,0x01,
++    0x0C,0x01,0x30,0x62,0x30,0x4A,0xE3,0x4A,0x02,0x0F,0xE0,0x48,0x90,0x4D,0x36,0xEA,
++    0x07,0x6A,0x3E,0x68,0x88,0xCE,0xEF,0x1C,0x10,0x4A,0x9D,0xFE,0x40,0x01,0x88,0x8E,
++    0x08,0xF9,0x07,0x5F,0xD0,0x64,0xE0,0x9A,0x28,0x9A,0x93,0x1E,0xD0,0xA4,0xF8,0x93,
++    0x10,0x12,0xC4,0x0E,0xD0,0x64,0xA0,0x8A,0xE6,0x00,0x92,0x05,0x17,0x02,0x9D,0x8E,
++    0x87,0x7D,0xE8,0x85,0xF6,0x00,0x92,0x05,0x30,0x4A,0xE3,0x4A,0x2D,0x09,0x30,0x62,
++    0x00,0x6F,0x01,0x00,0x70,0x30,0x03,0x00,0xF8,0xFF,0x07,0x00,0x33,0x6A,0x18,0x2A,
++    0xFB,0x5C,0x00,0x70,0xCA,0xB0,0x07,0x38,0xDD,0xAA,0xC7,0x50,0x2C,0x09,0x00,0x6A,
++    0x1D,0xEA,0x90,0x5D,0x31,0x72,0xA3,0x8A,0xED,0x3C,0x10,0x52,0x98,0x16,0x28,0x11,
++    0x30,0x62,0x05,0xA7,0xFA,0x74,0xE0,0x28,0x10,0xEA,0x9D,0x6E,0x90,0x3C,0x08,0x01,
++    0x00,0x27,0xF8,0x64,0xE3,0xAA,0xA3,0xEA,0xE6,0x48,0x92,0x4D,0x17,0x0A,0x9D,0xC6,
++    0xE0,0x8A,0x29,0x09,0x30,0x62,0x05,0x17,0x90,0x45,0x2F,0x01,0xA3,0xAA,0x31,0x2A,
++    0x6D,0x01,0x80,0x2E,0x33,0x6A,0x18,0x2A,0xFB,0x5C,0x00,0x70,0xCA,0xB0,0x07,0x38,
++    0xDA,0xAA,0xDF,0x90,0x2C,0x09,0x00,0x6A,0x1B,0x5A,0x35,0x6A,0xE2,0x4A,0xE1,0x48,
++    0xA4,0x4A,0x39,0xAF,0xAC,0xC5,0x37,0x22,0xFC,0x73,0x5E,0xAA,0x36,0x02,0xC3,0x00,
++    0x31,0x32,0x34,0xAA,0x38,0x21,0x31,0x62,0x1A,0xEA,0xA3,0x01,0x13,0x01,0x20,0x2A,
++    0xC0,0x68,0x07,0xF7,0xC0,0x1B,0x58,0x79,0x86,0xD6,0xC8,0x1B,0x30,0xD8,0xA0,0x3E,
++    0x18,0xF9,0x8F,0x1B,0x8E,0x1B,0xC2,0x1B,0xE5,0x3B,0x15,0xDA,0xC6,0x06,0x88,0x13,
++    0xCA,0x1B,0x36,0xD8,0x76,0xD8,0x8A,0x1B,0x58,0x01,0x80,0x0E,0xF6,0xD8,0x8A,0x1B,
++    0xC8,0x1B,0x5E,0x01,0x8A,0x26,0xC0,0x1B,0x44,0xD8,0x04,0xD8,0x84,0x1B,0x82,0x13,
++    0x84,0x21,0x11,0x2A,0xC0,0xF6,0x06,0x01,0x84,0x04,0xB8,0x53,0x30,0x82,0x03,0x8F,
++    0xC5,0x13,0x10,0x92,0x96,0x5E,0xC0,0x13,0xE2,0x3B,0x35,0x98,0x75,0xD8,0x12,0xDA,
++    0xCC,0x2E,0xC0,0x13,0x50,0x01,0x81,0x16,0x00,0x09,0x80,0x04,0x00,0x27,0x10,0x01,
++    0x81,0x13,0x84,0x21,0x17,0x2A,0xC4,0x5E,0xC0,0x04,0x40,0x01,0x83,0x76,0x31,0x92,
++    0x36,0x5A,0x98,0x01,0x00,0x47,0x01,0x01,0x80,0x83,0xC4,0x83,0x11,0x82,0x95,0x16,
++    0xC2,0x83,0x36,0x38,0xE3,0x03,0x75,0xF8,0x10,0x3A,0xCC,0xE6,0x04,0x09,0x80,0x83,
++    0xFA,0x43,0xE4,0x00,0xB8,0x43,0x3C,0x71,0xF8,0xBA,0x7E,0x01,0xD0,0x16,0x00,0x01,
++    0x08,0x84,0x06,0x27,0x54,0xC4,0x10,0x3A,0xE8,0x0E,0x50,0xC4,0x08,0x84,0x3E,0x81,
++    0xF8,0xBA,0x7E,0x01,0xD0,0x16,0x00,0x01,0x10,0x84,0x00,0x27,0x54,0xC4,0x12,0x3A,
++    0xEA,0x0E,0x50,0xC4,0x11,0x84,0x90,0x21,0x16,0xAA,0xC4,0xA6,0xF8,0x43,0x40,0x01,
++    0x88,0x36,0x58,0x44,0x16,0xE9,0x03,0x90,0x10,0x82,0x94,0x0E,0xE0,0x00,0x1A,0x44,
++    0xF8,0x43,0x44,0x01,0x80,0xCE,0x10,0x01,0x03,0x01,0x28,0x99,0x0E,0x68,0xFB,0x63,
++    0x01,0x6F,0x18,0x21,0x1B,0x1A,0x22,0x1A,0xC8,0xD8,0xD2,0xF3,0x70,0x09,0x88,0x26,
++    0xC8,0xDB,0x5E,0x19,0x8A,0x0E,0xE0,0x90,0x92,0x95,0xE6,0x00,0x94,0x05,0x16,0x22,
++    0xC0,0x7E,0x57,0x01,0x88,0x0E,0x00,0x01,0x1F,0x44,0xE8,0xC5,0xAC,0x85,0x87,0x3D,
++    0x30,0x2A,0x30,0x62,0x41,0x12,0xC2,0x40,0x08,0x29,0xEE,0x4A,0x4B,0x29,0x80,0xDE,
++    0x4B,0x02,0xC2,0x70,0xEB,0x48,0xC4,0x48,0x89,0x1C,0x48,0xF2,0x8B,0x61,0xC0,0x48,
++    0x88,0x14,0x08,0x01,0x10,0xF9,0x1F,0x79,0x03,0x3F,0xA0,0x92,0xC8,0x3B,0x7E,0x01,
++    0x88,0x06,0x80,0x1B,0xE6,0x48,0x92,0x4D,0x87,0x21,0xF9,0x3B,0x17,0x7A,0xC4,0xA6,
++    0x00,0x01,0x80,0x34,0xF8,0x03,0x41,0x01,0x80,0xCE,0xB2,0x04,0x31,0x0A,0x31,0x42,
++    0x58,0x2D,0xD0,0x14,0xBA,0xFF,0xDF,0x97,0x80,0x34,0xC0,0x34,0x40,0x01,0x88,0x76,
++    0x30,0x01,0x00,0x47,0x31,0x5A,0x31,0x92,0x08,0xF9,0x07,0x09,0xA7,0x04,0xB8,0xFF,
++    0xE3,0x47,0xE7,0xB0,0x91,0xB5,0xFF,0x03,0x17,0x82,0xC5,0x9E,0x00,0xFF,0xC1,0x34,
++    0x40,0x09,0x88,0x96,0xC1,0xB3,0x31,0x1A,0x30,0x52,0x09,0x01,0x37,0x82,0xB9,0xFF,
++    0xE8,0x2F,0x46,0x01,0x80,0x0E,0x00,0x01,0x00,0x07,0x00,0x09,0x30,0x5A,0x11,0x01,
++    0x30,0x8A,0xA1,0x04,0xBE,0xFF,0xE7,0x6F,0x00,0x4F,0xA1,0x04,0xFB,0x3B,0x31,0x5A,
++    0xE9,0xD3,0x30,0xDA,0xC8,0x1C,0xC0,0x14,0xB8,0xFF,0xF7,0x47,0x38,0x01,0x00,0xDF,
++    0xC6,0x1C,0xE8,0x02,0x40,0xF9,0x87,0x16,0xE0,0x82,0x81,0x24,0x07,0x0F,0x00,0xF9,
++    0x81,0x24,0x30,0x1A,0x31,0x52,0x31,0xCA,0xC7,0x24,0xB8,0xFF,0xE8,0xFF,0x44,0x01,
++    0x80,0x0E,0x00,0x01,0x00,0x07,0x00,0x09,0x31,0x5A,0x31,0xD2,0xA0,0x04,0xC8,0x24,
++    0xBD,0xFF,0xE7,0x3F,0xE7,0xF8,0x93,0xFD,0xFD,0x03,0x11,0xC2,0xC1,0x06,0x37,0x0A,
++    0x30,0x42,0xD1,0x34,0xBE,0xFF,0xF7,0xB7,0x20,0xCF,0x04,0x01,0x38,0x82,0x03,0x00,
++    0x70,0x30,0x03,0x00,0x48,0xE0,0x06,0x00,0xAE,0xFD,0x87,0x5D,0xC6,0xAC,0xDA,0x03,
++    0x82,0xCC,0xC1,0xAC,0xD9,0x03,0x84,0xC4,0x01,0x09,0x58,0x45,0x81,0xC3,0xC0,0xC4,
++    0xE2,0x00,0x82,0xC3,0xC4,0xC4,0x81,0xC3,0xC2,0xC4,0xF1,0x00,0x82,0xC3,0xC6,0xAC,
++    0x82,0x01,0x87,0x54,0xC0,0x0B,0x00,0x21,0x1A,0x0A,0xC0,0x54,0x82,0x0B,0xC0,0xAC,
++    0xCA,0x03,0x42,0x00,0x80,0xD4,0x09,0x01,0x40,0xB5,0x31,0x52,0x00,0x36,0x00,0x01,
++    0x82,0xF4,0xC0,0xAC,0xCC,0xB4,0x82,0x01,0x82,0x4C,0xC2,0x74,0x92,0x05,0x82,0x44,
++    0xC2,0x6C,0x92,0x05,0x82,0x3C,0xC2,0xAC,0x82,0x01,0x86,0x34,0x4B,0x11,0x80,0xBE,
++    0x10,0x01,0x00,0x01,0x4C,0x45,0xB1,0x4A,0x8F,0x2C,0x4A,0xF2,0xB2,0x4A,0x8C,0x24,
++    0x48,0xE2,0xEF,0x48,0xB2,0x4A,0x8C,0x1C,0x04,0x08,0xC4,0x48,0x91,0x4D,0x66,0x9D,
++    0xDB,0x74,0xA2,0x1A,0x62,0x85,0xD9,0x6C,0xA2,0x1A,0xDB,0x24,0x9A,0x34,0xD9,0x1C,
++    0x9A,0x2C,0xD9,0x2C,0x98,0x24,0x41,0x09,0x89,0x5E,0xD8,0x34,0x12,0xDA,0x92,0xDD,
++    0x99,0x34,0xD9,0x2C,0x12,0xDA,0x92,0xDD,0x99,0x2C,0xD9,0x24,0x12,0xDA,0x92,0xDD,
++    0x9A,0x24,0xD9,0x5C,0x32,0xE2,0xDC,0x64,0x9A,0x5C,0xD9,0x3C,0xE1,0x44,0xEA,0x2C,
++    0xCA,0xD8,0x92,0xDD,0xEB,0x34,0xC9,0x20,0x91,0x25,0xF3,0x24,0xED,0x5C,0xC9,0x68,
++    0xA8,0x5C,0x59,0x01,0xD9,0x86,0xEB,0xCC,0x13,0x5A,0xD5,0x6E,0x63,0x01,0xD8,0x5E,
++    0xED,0xC4,0x11,0x62,0xD1,0x46,0xEB,0x5C,0xC5,0x6B,0x49,0x68,0x8B,0x06,0x32,0x2A,
++    0x3F,0x01,0xF8,0x7A,0xEB,0x24,0x01,0x68,0x23,0x62,0x35,0x32,0x2B,0x01,0xF8,0xAA,
++    0xF5,0xD4,0x11,0xAA,0xEA,0xC6,0xF2,0xB4,0x71,0x09,0x88,0x16,0xD9,0xF0,0x93,0xB5,
++    0xB2,0x9C,0xF8,0x5C,0x35,0x01,0xF8,0xF2,0x10,0x72,0xDD,0x06,0x37,0xAA,0x81,0x68,
++    0x01,0x68,0x33,0x7A,0xF3,0x9C,0x10,0x6A,0x12,0xAA,0xE5,0x2E,0x6B,0x9D,0xA1,0x62,
++    0x6B,0x85,0xA1,0x5A,0x01,0xA8,0x72,0xB5,0xC9,0x68,0xE5,0x72,0xE1,0xB0,0xA3,0x72,
++    0xEB,0xF4,0xE0,0x68,0x90,0x6D,0xAF,0xF4,0xF5,0x9C,0x10,0xBA,0xD1,0xBE,0x05,0x9F,
++    0x09,0xEF,0x6A,0x9D,0xA1,0x62,0x6B,0x85,0xA2,0x5A,0x03,0xA8,0x75,0xB5,0xC9,0x68,
++    0xE3,0x72,0xE1,0xB0,0xA0,0x72,0xE9,0xF4,0xE7,0x68,0x93,0x6D,0xAD,0xF4,0x38,0x37,
++    0xE9,0x5C,0xC1,0x6B,0x48,0x68,0x6D,0x19,0x8A,0x6E,0x00,0xB0,0x7F,0xB5,0xC9,0xB0,
++    0xE0,0xB2,0x71,0x09,0xC2,0x3E,0xC0,0x64,0x08,0x01,0xC6,0x03,0x1A,0x42,0xC8,0x64,
++    0x82,0x43,0x80,0x7D,0xE8,0x85,0x6F,0x11,0x89,0x56,0x68,0x9D,0xA1,0x62,0x63,0x85,
++    0xA2,0x1A,0x03,0x98,0x4A,0xB5,0xC1,0xC8,0xE2,0x5A,0xE0,0xD8,0xA0,0x5A,0x00,0x1F,
++    0xCE,0x34,0xCA,0x4B,0x4F,0x51,0x90,0x66,0xE6,0x00,0x92,0x05,0x40,0x11,0x90,0x06,
++    0x3A,0xD7,0xE2,0x90,0x90,0x95,0x56,0x21,0x92,0x06,0x38,0x57,0x01,0x01,0x80,0x64,
++    0xC0,0xB4,0x42,0x09,0x88,0xF6,0x03,0x01,0x80,0x7C,0x01,0x01,0x81,0x74,0xC9,0x7C,
++    0x42,0xB5,0x01,0x48,0xC2,0x40,0x80,0x14,0xC1,0x74,0xC9,0x7C,0x02,0x00,0xC4,0x00,
++    0x91,0x05,0x86,0x4C,0xCA,0x74,0xC1,0x14,0xE0,0x2A,0x6A,0x09,0xC1,0x26,0xC0,0x64,
++    0xE6,0x00,0x92,0x05,0x87,0x64,0x01,0x8F,0xC0,0x74,0x41,0x09,0x89,0x16,0xC0,0x7C,
++    0x47,0x01,0x88,0xC6,0x08,0x81,0x41,0x45,0x83,0x17,0xC0,0x77,0xC0,0x6C,0x82,0x3C,
++    0xC0,0x74,0x82,0x34,0xC0,0x5C,0x82,0x0C,0xC0,0x64,0x82,0x04,0xC4,0x7C,0xE1,0x00,
++    0x3C,0x00,0x7C,0x00,0x50,0x5A,0xB4,0xA2,0xE8,0x98,0xB0,0xCA,0x31,0x62,0x74,0x45,
++    0xB1,0x8A,0xC1,0x7C,0xB0,0x82,0x80,0x24,0xC0,0x7C,0xB1,0xC2,0x81,0x1C,0xD0,0x7C,
++    0xB0,0x82,0x85,0x14,0xC0,0x74,0x41,0x09,0x88,0x5E,0xC0,0x24,0x12,0x02,0x92,0x05,
++    0x80,0x24,0xC0,0x1C,0x12,0x02,0x92,0x05,0x80,0x1C,0xC0,0x14,0x12,0x02,0x92,0x05,
++    0x80,0x14,0x00,0x01,0x83,0x2C,0xE0,0x68,0xAD,0xF4,0x01,0x9F,0x40,0x61,0x98,0x66,
++    0xC8,0x24,0xC0,0x34,0xD2,0x4C,0xD1,0x00,0x4C,0x9D,0xA1,0x42,0xC8,0x1C,0xC0,0x3C,
++    0xD2,0x4C,0xD1,0x00,0x4C,0x85,0xA1,0x42,0x00,0x47,0x15,0x01,0xDC,0x0C,0x00,0x28,
++    0xF0,0xD2,0x5C,0x45,0x88,0xD2,0x12,0x01,0x90,0x6C,0xD1,0x3C,0x92,0x95,0x92,0x0C,
++    0xD2,0x34,0x90,0x95,0x91,0x04,0xD2,0x6C,0x50,0x09,0x88,0x3E,0x12,0x12,0x93,0xA5,
++    0x32,0x12,0x13,0x92,0x94,0x95,0x32,0xA2,0x12,0x4A,0x92,0x4D,0xD2,0x0C,0xDA,0x04,
++    0xF0,0x0C,0x00,0x07,0x01,0xEF,0xB4,0x1C,0xF1,0x04,0xB0,0x5C,0x01,0x70,0xB2,0xFC,
++    0x22,0x12,0x93,0x95,0xCA,0xD8,0x90,0xDD,0xF9,0x1C,0xF1,0xFC,0xC9,0xB0,0xB7,0x1C,
++    0xF3,0x5C,0xC1,0xB0,0xB0,0x5C,0x51,0x01,0xD9,0xBE,0xF0,0xCC,0x10,0x92,0xD5,0xA6,
++    0x58,0x01,0xD8,0x96,0xF5,0xC4,0x11,0x9A,0xD1,0x7E,0xF8,0x1C,0x35,0x01,0xF8,0xF2,
++    0xF9,0x5C,0xC1,0xFB,0x48,0xF8,0x8D,0x46,0xFD,0xD4,0x11,0xF2,0xE8,0x2E,0x78,0x45,
++    0xCD,0xFA,0xCB,0xF0,0x7B,0x45,0x88,0xF2,0x39,0xD7,0xD6,0x6C,0xE6,0x90,0x92,0x95,
++    0x91,0x6C,0xD1,0x6C,0x55,0x11,0x98,0xF6,0x41,0x01,0x80,0xF6,0xF2,0x10,0xF2,0x4C,
++    0x00,0x90,0x5C,0x45,0xC7,0xD2,0xD4,0xB3,0xCC,0xDA,0xCA,0xB0,0x11,0xF2,0x94,0x86,
++    0xD0,0x2C,0x50,0x09,0x88,0x8E,0xD1,0x24,0xC1,0x34,0xD8,0x4C,0xD1,0x00,0x54,0x9D,
++    0xA0,0x82,0xDE,0x1C,0xD1,0x3C,0xE8,0x4C,0xD1,0x90,0x5E,0x85,0xA8,0xD2,0xEA,0x14,
++    0xDA,0x04,0xD8,0xE8,0x36,0x1A,0xD3,0x90,0x90,0x95,0xDA,0x00,0x93,0x1D,0xD2,0x40,
++    0x2C,0x01,0x38,0x01,0x50,0x01,0xD8,0x56,0xF5,0xCC,0x11,0x92,0xD0,0x3E,0x58,0x01,
++    0xD9,0x2E,0xF0,0xC4,0x10,0x9A,0xD5,0x16,0xC1,0x33,0x18,0xF2,0x83,0x33,0x20,0x12,
++    0x90,0x95,0xCA,0xD8,0x92,0xDD,0xC2,0x00,0xE7,0x68,0x93,0x6D,0x6F,0x11,0xC8,0x4E,
++    0x04,0xE7,0x10,0x9A,0x90,0x0E,0x10,0x09,0x90,0x2C,0xD8,0x24,0xD6,0x34,0xC0,0x90,
++    0x90,0x95,0x96,0x34,0xD8,0x1C,0xD0,0x3C,0xC6,0x90,0x96,0x95,0x90,0x3C,0xD0,0x14,
++    0xDA,0x0C,0x00,0x90,0xC0,0x90,0x96,0x0C,0xD8,0x14,0xD0,0x04,0xC0,0x90,0x96,0x04,
++    0xE6,0x00,0x92,0x05,0xD4,0xF4,0x11,0x82,0x92,0x06,0x38,0x3F,0xC2,0x74,0xE1,0x00,
++    0x91,0x05,0x86,0x74,0xC0,0x74,0x41,0x11,0x97,0x06,0x30,0xAF,0xC2,0x7C,0xE1,0x00,
++    0x91,0x05,0x86,0x7C,0xC0,0x7C,0x41,0x21,0x97,0x06,0x30,0x37,0x00,0x0F,0x00,0x41,
++    0x81,0x64,0xC1,0x64,0x41,0x41,0x88,0xD6,0x10,0x01,0x00,0x01,0x58,0x8A,0xE8,0xC8,
++    0xB4,0xF2,0xB4,0x7A,0x31,0x8A,0x31,0xDA,0x40,0x09,0x88,0x1E,0x12,0x4A,0x92,0x4D,
++    0x12,0xDA,0x92,0xDD,0xE7,0x6C,0xC2,0x18,0x92,0xDD,0xE2,0x74,0xC2,0x08,0x93,0x65,
++    0x04,0x08,0xC4,0x48,0x90,0x4D,0x5E,0x01,0xD9,0x76,0xE8,0xCC,0x10,0x5A,0xD5,0x5E,
++    0x60,0x01,0xD8,0x4E,0xED,0xC4,0x11,0x62,0xD1,0x36,0x68,0x9D,0xA1,0x62,0x63,0x85,
++    0xA0,0x1A,0x03,0x3F,0x70,0xF2,0x06,0x00,0x62,0x9D,0xD9,0x74,0xA1,0x1A,0x63,0x85,
++    0xDB,0x6C,0xA2,0x1A,0xE6,0x00,0x92,0x05,0x46,0x11,0x98,0x9E,0xE6,0x90,0x92,0x95,
++    0x56,0x21,0x98,0x56,0x58,0x85,0xD9,0xC3,0xA8,0xC3,0xC0,0xC3,0x90,0xC3,0x00,0x01,
++    0x81,0xFC,0x58,0x85,0xD8,0xC3,0xA8,0xC3,0xC0,0xC3,0x90,0xC3,0x00,0x01,0x80,0xE4,
++    0x30,0x3A,0x80,0xEC,0xC4,0xAC,0xCA,0x03,0x80,0xD4,0x01,0x01,0x0E,0x01,0x00,0x18,
++    0x54,0xA5,0xC0,0xD0,0x32,0xA2,0x04,0x20,0xC6,0x10,0x93,0x95,0x6D,0x9D,0xE1,0x72,
++    0x33,0x2A,0xA3,0x72,0x6D,0x85,0xE1,0x6A,0x32,0x12,0xC3,0x90,0x8A,0xAB,0xE0,0x48,
++    0x90,0x4D,0x4E,0x19,0x98,0x86,0x47,0x09,0x80,0x0E,0x40,0x19,0x88,0x66,0x60,0xA5,
++    0xE3,0x0A,0x37,0x12,0xCB,0x93,0x30,0x2A,0xC7,0x6B,0xA5,0x2A,0x34,0x1A,0xCB,0xE3,
++    0x8C,0xE3,0x80,0xCB,0x34,0x0A,0x8B,0x53,0x09,0x09,0x88,0x0C,0x09,0x01,0x88,0x74,
++    0xD3,0x74,0x31,0x0A,0xE1,0x4A,0xDC,0x74,0x36,0x12,0xC3,0x90,0xCA,0x9B,0xC0,0xAB,
++    0xC9,0x93,0x92,0x14,0xD0,0x74,0x51,0x01,0x88,0x16,0x41,0x01,0x80,0x0E,0x40,0x19,
++    0x8D,0x5E,0x10,0x4A,0x98,0x4E,0x10,0x09,0x90,0x04,0x41,0x01,0x8A,0x16,0xF0,0x10,
++    0x90,0x0C,0x01,0xF7,0x11,0x09,0x90,0x0C,0x00,0xDF,0x40,0x09,0x80,0x0E,0x40,0x11,
++    0x8D,0x5E,0x10,0x4A,0xC0,0x4E,0x10,0x09,0x90,0x04,0x41,0x09,0x8C,0x16,0xF0,0x10,
++    0x90,0x0C,0x01,0x77,0x11,0x09,0x90,0x0C,0x00,0x5F,0x10,0x01,0x90,0x04,0x01,0x47,
++    0x11,0x09,0x90,0x04,0x40,0x11,0x90,0x16,0xF1,0x90,0x94,0x0C,0x00,0x0F,0x10,0x09,
++    0x90,0x0C,0x41,0x01,0x80,0x0E,0x40,0x19,0x8D,0x0E,0x10,0x4A,0x90,0x2E,0x40,0x09,
++    0x80,0x0E,0x40,0x11,0x8D,0x26,0x10,0x4A,0xC0,0x16,0x10,0x09,0x94,0x54,0x01,0x8F,
++    0x11,0x01,0x90,0x54,0x01,0x77,0xF4,0xC4,0x33,0x12,0x19,0x92,0xF1,0xA4,0x92,0xE4,
++    0xC9,0x90,0xF4,0xEC,0xC9,0x90,0x94,0x5C,0xD0,0x5C,0xC1,0x93,0x92,0xDC,0x31,0x90,
++    0xA1,0xCE,0xD1,0xE4,0xF2,0xA4,0x02,0x90,0xC9,0x90,0xF4,0x3C,0x04,0xB0,0xCB,0x90,
++    0x35,0x39,0x09,0xB0,0xC8,0xB0,0x14,0xE1,0xF1,0x92,0xF5,0xD4,0x10,0x92,0xD5,0x26,
++    0xF0,0x64,0x71,0x41,0x88,0xB6,0x50,0x01,0xD9,0xA6,0xF0,0xDC,0x48,0xB0,0x87,0x06,
++    0x80,0x90,0xF2,0xE4,0xC0,0xB0,0xB5,0xE4,0xF2,0x3C,0x19,0xB2,0xC8,0xB8,0xF7,0xEC,
++    0x1C,0x12,0xCB,0x90,0x90,0xEC,0xD0,0xFC,0xE4,0x90,0x92,0x95,0x91,0xFC,0xD0,0xDC,
++    0x48,0x90,0x8E,0xEE,0xD0,0x4C,0xF2,0xF4,0xD5,0x93,0x12,0x92,0xC1,0x2E,0xD0,0xDC,
++    0x31,0x01,0x1E,0x92,0xF1,0x5C,0x81,0x93,0x01,0x47,0xD0,0xDC,0x31,0x01,0x1A,0x92,
++    0xF1,0x5C,0x81,0x93,0x01,0x17,0xD0,0x04,0x50,0x09,0x80,0x4E,0xD0,0x04,0x51,0x09,
++    0x8A,0x36,0xD0,0x6C,0x10,0xA2,0x84,0x1E,0xD5,0x0C,0xC1,0x10,0x95,0xA5,0x3A,0x57,
++    0x10,0x4A,0x8D,0xDE,0xD4,0x14,0x11,0x9A,0x89,0xC6,0xC8,0x74,0xE6,0x48,0x92,0x4D,
++    0x89,0x74,0xC9,0x74,0x48,0x11,0x90,0x06,0x3A,0x97,0xE2,0x00,0x90,0x05,0x46,0x21,
++    0x91,0x06,0x38,0x1F,0xC6,0x34,0xCA,0x03,0x42,0x01,0x88,0x5E,0xC9,0xAC,0x8A,0x01,
++    0xE0,0x43,0x36,0x10,0xAA,0x36,0x31,0x00,0x71,0x00,0x04,0x27,0xD0,0x54,0x51,0x01,
++    0x8D,0x5E,0x10,0x4A,0xCA,0x16,0xF0,0x48,0x90,0x4D,0x06,0x1F,0x10,0x4A,0x95,0x0E,
++    0xE6,0x48,0x92,0x4D,0x11,0x09,0x90,0x54,0x01,0x67,0xD0,0x14,0x10,0x9A,0xCC,0x16,
++    0xF6,0xD8,0x92,0xDD,0x01,0x27,0xD0,0x14,0x10,0x9A,0x94,0x0E,0xE6,0xD8,0x92,0xDD,
++    0x11,0x01,0x90,0x54,0x91,0x55,0x92,0x3C,0x97,0xE5,0x72,0xFA,0xD4,0x3C,0xC9,0x90,
++    0x93,0xEC,0x39,0x47,0x02,0x01,0xD0,0xAC,0x6C,0x94,0x16,0x12,0x9A,0xD6,0xC0,0xAC,
++    0xE8,0x4B,0x70,0x04,0x10,0x42,0x9C,0x26,0xC4,0x4C,0xD2,0x03,0xF6,0x00,0x94,0x05,
++    0x02,0x1F,0xC0,0x4C,0xD4,0x03,0xE4,0x00,0x90,0x05,0xCE,0xFC,0x10,0x0A,0x9C,0x4E,
++    0xC0,0xAC,0x0A,0x01,0xBA,0x0B,0xC0,0x54,0x08,0xD9,0xC7,0x03,0x02,0x42,0xC8,0x54,
++    0x82,0x43,0x28,0x37,0x27,0x01,0x28,0xF9,0xA8,0x09,0x60,0x01,0x8A,0x56,0xC0,0x44,
++    0xC8,0xC4,0xB9,0x9C,0xD2,0x34,0x4A,0x93,0x92,0x94,0xD0,0x74,0x5A,0x3A,0x07,0x90,
++    0xF0,0xF2,0x04,0x57,0xC1,0x3C,0xCA,0xCC,0xD0,0xEC,0x90,0x9C,0xD4,0x34,0x4A,0x93,
++    0x92,0x94,0xD0,0x6C,0x5A,0x12,0x07,0x90,0xF0,0xF2,0x44,0x01,0x82,0x16,0xF0,0x48,
++    0x10,0x42,0x8C,0x8E,0xD0,0x74,0x92,0x04,0x91,0x05,0x36,0x0A,0xDA,0x6C,0xD2,0x5C,
++    0xBB,0xEF,0xD7,0xA7,0x35,0x4A,0x11,0x42,0xE8,0x0E,0x30,0x42,0x00,0x17,0x40,0x01,
++    0xD0,0x06,0x00,0x01,0xC8,0x30,0x04,0x07,0xB0,0x01,0xC4,0x9C,0xC8,0xE4,0x10,0x00,
++    0x86,0x0F,0xE8,0x27,0xCC,0x94,0xC8,0x00,0x18,0x42,0x42,0x01,0xD0,0x06,0x00,0x01,
++    0xA0,0x00,0x60,0x01,0x8A,0x7E,0xC8,0x34,0x54,0x4C,0x10,0x0A,0xD0,0x06,0x30,0x42,
++    0xC8,0xAC,0x12,0x31,0xFA,0x4B,0x18,0x8A,0xD4,0xA4,0xC2,0x48,0x14,0xC9,0x09,0x90,
++    0xC2,0x48,0x04,0x44,0x02,0x77,0xC8,0x34,0x54,0x4C,0x12,0x0A,0xD0,0x06,0x30,0x42,
++    0xC8,0xAC,0x12,0x31,0xFA,0x4B,0x18,0x8A,0xD4,0xA4,0xC2,0x48,0x14,0xC9,0x09,0x90,
++    0xC4,0x48,0x04,0x44,0xE7,0x20,0x93,0x25,0x64,0x09,0xC8,0xF6,0xC0,0xAC,0x12,0x31,
++    0xE0,0x0B,0xC2,0xE4,0x02,0x42,0xCE,0xAC,0xFA,0x4B,0x18,0x8A,0xD4,0xA4,0xC2,0x48,
++    0x14,0xC9,0x09,0x90,0xC6,0x48,0x04,0x44,0xC2,0xAC,0xCA,0x74,0xFA,0x03,0x00,0x10,
++    0xC0,0xA4,0xC2,0x90,0x02,0x89,0x0B,0x00,0xC4,0x90,0xA8,0x8B,0xCA,0xAC,0xD2,0x6C,
++    0xFA,0x4B,0x00,0x58,0xCA,0xA4,0xC2,0xC8,0xC6,0x40,0xA8,0x13,0xC2,0xAC,0xCA,0xAC,
++    0xFA,0x03,0xE0,0x00,0xBD,0x43,0x20,0xE7,0xAC,0xFD,0x87,0xBD,0xEC,0x04,0x31,0xA2,
++    0xD8,0x43,0x87,0x84,0xD8,0x43,0x85,0x7C,0xC8,0x43,0x81,0x74,0x00,0x01,0x80,0x54,
++    0x42,0x22,0x45,0x0B,0x36,0x42,0x81,0x01,0x80,0xB4,0x48,0x01,0x80,0x1E,0xC0,0x74,
++    0x40,0x00,0x82,0x5C,0x00,0x67,0xC0,0xB4,0xC8,0x03,0x46,0x51,0x98,0x26,0xC8,0xB4,
++    0x00,0x49,0xB0,0x42,0x80,0x5C,0x00,0x1F,0xC0,0xB4,0x08,0x41,0xB0,0x0A,0x8A,0x5C,
++    0x40,0xCA,0xD4,0xD4,0xC8,0xBC,0xC0,0x80,0x80,0xAC,0x48,0x01,0x84,0xF6,0x49,0xBA,
++    0xC2,0xD4,0xC0,0x08,0x10,0x49,0xC5,0xD4,0x04,0x90,0xC4,0x18,0xE0,0xAC,0xC0,0x74,
++    0x42,0x00,0x12,0x02,0x90,0x05,0x82,0x54,0x30,0x01,0x00,0x7F,0x00,0x01,0x00,0x47,
++    0x40,0x7C,0x40,0xD4,0xD1,0xD0,0x05,0x14,0xE4,0x20,0xE5,0x48,0xE2,0xD8,0xE4,0x00,
++    0x90,0x05,0xD6,0x7C,0x17,0x82,0x9C,0x9E,0xE7,0xB0,0x93,0xB5,0xC4,0x84,0x10,0x32,
++    0x9B,0x66,0x37,0x02,0x40,0x01,0x80,0x06,0x3C,0x02,0x4C,0x2A,0xC2,0xD4,0xC0,0x18,
++    0x48,0x1A,0xC4,0xD4,0x8A,0xC1,0xC1,0x00,0x50,0x0A,0xCC,0xD4,0x94,0x81,0xC3,0x48,
++    0x10,0x01,0x00,0x47,0x40,0x24,0x40,0x74,0xD8,0x20,0x05,0xE4,0xE4,0xD8,0xE4,0x00,
++    0xE2,0x48,0xE4,0x90,0x90,0x95,0xE6,0x7C,0x17,0x12,0x9D,0x9E,0x48,0x92,0xC3,0xD4,
++    0xC0,0x00,0x82,0x4C,0xE0,0xAC,0x00,0x01,0x81,0x8C,0x30,0x42,0x80,0x01,0x81,0xA4,
++    0x80,0x01,0x86,0x9C,0x08,0x97,0x32,0x01,0x08,0x47,0xC2,0x4C,0xC4,0x03,0x48,0x00,
++    0x89,0xF6,0xF3,0x02,0xCC,0x74,0x10,0x42,0xD8,0xD6,0xC3,0x7C,0x32,0x5A,0x03,0x00,
++    0xD0,0x08,0x31,0x52,0xD6,0x01,0x59,0x94,0x10,0xD4,0x40,0x54,0x12,0xD4,0x42,0x4C,
++    0x11,0xCC,0x34,0x0A,0xCE,0x01,0x59,0x4C,0x11,0xCC,0x46,0x0C,0x1B,0xCC,0x40,0x0C,
++    0x18,0xCC,0xCA,0x08,0x31,0x52,0xD0,0x01,0x5C,0x94,0x1E,0xD4,0xD6,0x02,0x19,0xC4,
++    0x40,0x44,0x22,0xC4,0x40,0x25,0x70,0x01,0x88,0x26,0x08,0x01,0x16,0xCC,0x10,0xCC,
++    0x18,0xCC,0x04,0x47,0xCA,0x7C,0xF0,0x48,0x10,0x72,0x8C,0x26,0x0B,0x01,0x30,0x5A,
++    0x12,0xCC,0x1C,0xCC,0x20,0xCC,0xC8,0x8C,0x48,0x01,0x88,0x26,0x30,0x5A,0x13,0xCC,
++    0x14,0xCC,0x12,0xCC,0x00,0x4F,0xC8,0x84,0xD2,0x8C,0xF0,0x48,0x10,0x52,0x8C,0x26,
++    0x0B,0x01,0x30,0x5A,0x1E,0xCC,0x1C,0xCC,0x20,0xCC,0x10,0x01,0xF3,0x12,0x35,0x5A,
++    0x0A,0x81,0xF0,0xCA,0x11,0x8A,0xD4,0x9E,0x0A,0x91,0xF0,0xCA,0x17,0x8A,0xD4,0xD6,
++    0x0A,0xA1,0xF0,0xCA,0x17,0x8A,0xD4,0xB6,0x0A,0xB1,0xF0,0xCA,0x17,0x8A,0xD4,0x96,
++    0x0A,0xD1,0xF0,0xCA,0x11,0x8A,0xE4,0x1E,0x0A,0xE1,0xF0,0xCA,0x17,0x8A,0xE4,0xD6,
++    0x0A,0xF1,0xF0,0xCA,0x17,0x8A,0xE4,0xB6,0x0A,0x01,0xF1,0xCA,0x17,0x8A,0xE4,0x96,
++    0x0A,0xD1,0xEC,0x4A,0x4B,0x01,0x80,0xCE,0x08,0x01,0x88,0x6C,0x30,0x72,0x8C,0x1C,
++    0x88,0x64,0xD8,0xBC,0x5A,0x01,0x88,0x1E,0x32,0xE2,0xFC,0x78,0x1E,0x01,0xF0,0x1A,
++    0x10,0xDA,0xD5,0x46,0xC0,0xC8,0x92,0x4D,0xDA,0x1C,0xE0,0xD8,0x90,0xDD,0x06,0x07,
++    0x00,0xF7,0x9D,0x1C,0x00,0x2F,0x58,0x51,0xEB,0x1E,0x30,0x9A,0xE6,0xD8,0x92,0xDD,
++    0x34,0xF2,0xE4,0x00,0x32,0x1A,0xE3,0xD8,0x94,0xDD,0x36,0xE2,0x30,0x1A,0x5B,0x49,
++    0x9A,0x26,0xC7,0x80,0x90,0x05,0xD0,0xA4,0x70,0x4C,0xE9,0x93,0x10,0x8A,0x9C,0xB6,
++    0xCC,0x5C,0x10,0x42,0xD3,0x9E,0x30,0x8A,0x48,0x39,0x98,0x36,0xCA,0x5C,0x80,0x48,
++    0x10,0x0A,0xDC,0x66,0xC0,0x1C,0x40,0x01,0x88,0x4E,0xC0,0xB4,0xC8,0x03,0x46,0x11,
++    0x98,0x0E,0x00,0x09,0x80,0x6C,0x48,0xDA,0xC2,0x43,0xE2,0x00,0x80,0x43,0x4A,0xCA,
++    0xC0,0x43,0x40,0x81,0x90,0x26,0x52,0xC2,0xA2,0xB2,0xE0,0x00,0x81,0x43,0x00,0xFF,
++    0x34,0xB2,0x84,0x98,0xC0,0x98,0x96,0xDD,0x98,0x14,0x18,0x01,0x30,0xE2,0xDC,0x54,
++    0x80,0xD8,0x9A,0x94,0x1E,0x01,0xF0,0x1A,0xFD,0x94,0x10,0xDA,0xD3,0x56,0x30,0xBA,
++    0xC9,0xF8,0x96,0xFD,0x30,0xF2,0xFD,0x54,0x10,0xDA,0xD5,0x1E,0x86,0xB8,0xCA,0xB8,
++    0x90,0xFD,0xB9,0x14,0xC0,0xC8,0x02,0x97,0x60,0x20,0x02,0x00,0x70,0xD2,0x05,0x00,
++    0x70,0xD2,0x03,0x00,0x80,0x40,0x07,0x01,0x48,0xE0,0x06,0x00,0x28,0x60,0x00,0x00,
++    0x68,0x70,0x04,0x00,0x00,0xC0,0x00,0x01,0x80,0xC0,0x06,0x01,0x00,0xF7,0x90,0x4D,
++    0xE3,0x00,0x34,0x1A,0xE6,0xD8,0x92,0xDD,0x33,0xE2,0x34,0x1A,0x5E,0x49,0x98,0x8E,
++    0xC4,0x14,0x10,0x0A,0xD8,0x16,0xC8,0x5C,0x28,0x72,0xD4,0x0E,0x00,0x09,0x80,0x6C,
++    0xC6,0xB4,0xC8,0x03,0x40,0x51,0x98,0x16,0xC0,0xBC,0x40,0x01,0x80,0x46,0xC8,0x6C,
++    0x00,0x09,0x48,0x01,0x80,0x06,0x00,0x01,0x80,0x64,0x00,0x0F,0x00,0x09,0x80,0x64,
++    0xC0,0x64,0x40,0x01,0x80,0xA6,0x01,0x09,0xBC,0x43,0x43,0x3A,0x40,0x03,0x42,0x01,
++    0x88,0x5E,0xC0,0xB4,0xC8,0x03,0x46,0x51,0x90,0x3E,0xC0,0xA4,0x6E,0x4C,0xE7,0x03,
++    0x32,0x00,0x72,0x00,0x84,0x51,0x10,0x0A,0xC8,0x0E,0x10,0x01,0x00,0x07,0x10,0x09,
++    0xC0,0xC4,0x40,0x01,0x80,0x06,0x10,0x11,0xC0,0xD4,0x90,0x14,0x81,0x04,0x30,0x9A,
++    0xA9,0x0C,0x30,0x02,0xD0,0x8C,0xC8,0x4C,0xBA,0xFF,0xD7,0x37,0xC0,0x9C,0xC0,0x03,
++    0x38,0x00,0xAA,0x1E,0xFF,0x43,0xF9,0x4B,0x10,0x42,0x9C,0x4E,0xC0,0x9C,0xC0,0x03,
++    0x38,0x00,0xA2,0x1E,0x05,0x01,0xA8,0x43,0xCC,0x9C,0x80,0x43,0x87,0xDD,0xE8,0x85,
++    0xE0,0x20,0xC5,0x4C,0xE0,0x00,0x82,0x4C,0xE7,0xB0,0x93,0xB5,0xC4,0x7C,0x10,0x32,
++    0x95,0x06,0x30,0x97,0xC2,0x8C,0xE0,0x00,0x90,0x05,0x86,0x8C,0xC8,0x84,0xC0,0x8C,
++    0x10,0x42,0x94,0x06,0x37,0x3F,0x3D,0x4F,0xAC,0x9D,0x87,0x0D,0xD8,0x43,0x80,0x04,
++    0xDB,0x63,0x52,0x12,0xC4,0x0C,0xC0,0x28,0x50,0x02,0xC3,0x0C,0xD4,0xC1,0xC1,0x30,
++    0xE8,0x43,0x0C,0xF1,0x84,0x0F,0xD8,0x97,0x49,0xE9,0x88,0x0E,0x48,0xE2,0xC2,0x0C,
++    0xC5,0x10,0x0A,0x49,0xC4,0x0C,0x00,0x48,0xC0,0x08,0x1A,0x01,0x00,0x5F,0x00,0x01,
++    0x00,0x2F,0x40,0x7C,0x04,0xBC,0xE0,0x90,0xE2,0x48,0xE4,0x00,0x95,0x05,0x16,0x02,
++    0x9A,0xBE,0xE7,0xD8,0x90,0xDD,0xC6,0x04,0x17,0x1A,0x9C,0x86,0x00,0x01,0x00,0x2F,
++    0x41,0x8C,0x01,0x4C,0xE5,0x68,0xE5,0xB0,0xE6,0x00,0x92,0x05,0x17,0x02,0x9D,0xBE,
++    0x48,0x62,0xC2,0x0C,0xC0,0x00,0x12,0x01,0x00,0x67,0x08,0x01,0x00,0x37,0xC0,0x1B,
++    0x34,0xD8,0x74,0xD8,0x82,0x1B,0xE0,0x00,0xE6,0x48,0x92,0x4D,0x17,0x0A,0x9D,0xB6,
++    0xE6,0x90,0x92,0x95,0xCC,0x04,0x10,0x52,0x9F,0x7E,0xEF,0xF5,0xAC,0xFD,0x87,0x1D,
++    0x30,0x6A,0x30,0x01,0xBB,0x73,0xB9,0x73,0x37,0x42,0x81,0x01,0xC7,0x0B,0x10,0xE9,
++    0x02,0x52,0x38,0x48,0x7A,0x48,0x06,0x48,0x18,0x52,0x80,0x13,0xC7,0x0B,0x10,0xD9,
++    0x00,0x8A,0x80,0x0B,0x34,0x42,0x81,0x01,0x84,0x14,0xF0,0x03,0x78,0xB2,0x41,0x01,
++    0x80,0x4E,0x00,0x01,0x57,0xAA,0x09,0xF9,0xA2,0x8A,0xE0,0x00,0x90,0x05,0x46,0x81,
++    0x99,0xD6,0x87,0xF3,0x80,0xF3,0xAB,0x04,0x00,0x01,0xD8,0x1C,0xD0,0x34,0xC8,0x2C,
++    0xBD,0xFF,0xEF,0xD7,0x36,0x62,0xA1,0x01,0xC8,0x03,0x47,0x51,0x98,0x36,0xA8,0x04,
++    0x00,0x09,0xD8,0x1C,0xD0,0x34,0xC8,0x2C,0xBD,0xFF,0xEF,0x77,0xC4,0x14,0xF0,0x0B,
++    0x49,0x01,0x80,0xD6,0x00,0x01,0x48,0x09,0x8B,0x5E,0xC0,0xD3,0x50,0x01,0x80,0x46,
++    0x50,0x1A,0xC1,0x93,0x50,0x01,0x88,0x26,0x50,0x12,0xC1,0x93,0x50,0x01,0x88,0x06,
++    0x00,0x09,0x40,0x01,0x87,0x2E,0xC8,0x13,0x50,0x01,0x95,0x36,0xE7,0x90,0x8A,0x13,
++    0x07,0x1F,0xC8,0x13,0x50,0x51,0x90,0x06,0x8F,0x33,0xCF,0x13,0x50,0x51,0x98,0xE6,
++    0x40,0x01,0x88,0x6E,0x48,0x09,0x88,0x16,0xF7,0x90,0x8A,0x13,0x01,0x47,0x00,0x99,
++    0xEF,0x02,0x6A,0x4C,0x34,0x00,0x72,0x00,0x10,0x0A,0x94,0x0E,0xF7,0x90,0x8A,0x13,
++    0xC0,0xC3,0x43,0x11,0x9D,0x16,0x00,0x01,0x88,0x03,0x07,0x37,0x40,0x09,0x88,0x26,
++    0xCA,0x03,0x47,0x81,0x93,0x0E,0x00,0x21,0x89,0x03,0x37,0x4A,0xC7,0x1C,0xB8,0xFF,
++    0xF8,0xDF,0x81,0x3D,0xE8,0x85,0x07,0x00,0x80,0x40,0x07,0x01,0x68,0xF0,0x07,0x00,
++    0x28,0x60,0x00,0x00,0x60,0x20,0x02,0x00,0x00,0xC0,0x00,0x01,0x80,0xC0,0x06,0x01,
++    0x00,0x40,0x00,0x01,0x00,0x48,0x00,0x01,0xAC,0xFD,0x87,0x3D,0xE0,0x84,0x30,0xB2,
++    0x00,0x01,0x80,0x2C,0xD8,0x83,0x83,0x1C,0x60,0x8C,0x89,0x14,0xCA,0x44,0x18,0x0A,
++    0x50,0xFA,0xC7,0x3C,0xC0,0x00,0xC4,0x48,0x8F,0x34,0x40,0xF2,0xC0,0x03,0x40,0x09,
++    0x89,0x0E,0xE0,0x83,0x80,0x1C,0x00,0x01,0x10,0x01,0x00,0x1F,0x82,0x53,0xE0,0x48,
++    0xE6,0x00,0x92,0x05,0xDC,0x1C,0x10,0xC2,0x98,0xC6,0x0F,0x01,0x00,0x09,0xD8,0x54,
++    0xD0,0x44,0x80,0x07,0xD0,0xAF,0x2E,0x01,0x60,0x01,0x88,0x0E,0xE7,0x68,0x93,0x6D,
++    0xF8,0x34,0x08,0x01,0x01,0x5F,0xC0,0xC3,0x1E,0x02,0x91,0x05,0x80,0xC3,0xD1,0x8C,
++    0x10,0x82,0xCC,0x0E,0x19,0x02,0x85,0xC3,0xE2,0xF8,0xE3,0x48,0x90,0x4D,0xC6,0x1C,
++    0x17,0x0A,0x9C,0x86,0x48,0x42,0xC7,0x3C,0xC0,0x00,0x82,0x24,0xD0,0x54,0x90,0x04,
++    0x30,0x9A,0x01,0x11,0xD0,0x3C,0xC8,0x44,0x80,0x07,0xD8,0x47,0xD0,0x54,0x90,0x04,
++    0x04,0x41,0xEA,0x0A,0x00,0x01,0x1C,0x0A,0x30,0x9A,0x11,0x01,0xC0,0x24,0x80,0x07,
++    0xF6,0x27,0x05,0x29,0xE8,0x02,0x44,0x31,0x88,0x16,0x00,0x01,0x87,0x5D,0xE8,0x85,
++    0xC1,0x1C,0xD0,0xC0,0x09,0x01,0x00,0x3F,0xD0,0x24,0x18,0x01,0xF0,0x9A,0xD6,0x14,
++    0xD0,0xD0,0x94,0x95,0x68,0x01,0x88,0x2E,0x50,0xC1,0xE8,0xBE,0xC5,0x13,0x18,0x12,
++    0x80,0x13,0x00,0x9F,0x50,0x99,0xE8,0x2E,0xC0,0x13,0x50,0x01,0x82,0x16,0xF0,0x90,
++    0x80,0x13,0x00,0x5F,0x68,0x29,0x88,0x4E,0x58,0xE1,0xEE,0x3E,0xC0,0x13,0x50,0x01,
++    0x88,0x26,0xD0,0x2C,0x50,0x01,0x88,0x0E,0x10,0x09,0x90,0x2C,0xD4,0x24,0xE0,0x90,
++    0x92,0x24,0xE0,0x00,0xE6,0x48,0x92,0x4D,0xD4,0x1C,0x10,0x8A,0x9B,0xA6,0x46,0x20,
++    0x6C,0x21,0xC8,0xCE,0xD0,0x54,0x90,0x04,0x30,0x9A,0x09,0x01,0x00,0x19,0xD0,0x3C,
++    0x85,0x07,0xD0,0xE7,0x08,0x09,0x30,0x42,0xD8,0x54,0xD0,0x44,0x83,0x07,0xD0,0x07,
++    0xC5,0x2C,0x38,0xDF,0xAC,0xFD,0x87,0x1D,0xF0,0x64,0x30,0x7A,0x33,0xEA,0xD8,0xC3,
++    0x85,0x14,0x48,0xAA,0xC2,0x1C,0xC0,0x20,0x40,0x92,0xC5,0x03,0x40,0x09,0x88,0x0E,
++    0xE0,0xC3,0x81,0x14,0x08,0x01,0x00,0x09,0xD8,0x2C,0xD0,0x6C,0x82,0x07,0xD0,0x47,
++    0xD0,0x2C,0x90,0x04,0x30,0xDA,0x01,0x11,0xD0,0x1C,0xC8,0x6C,0x84,0x07,0xD0,0xB7,
++    0xD0,0x2C,0x90,0x04,0x06,0x41,0xEA,0x0A,0x00,0x01,0x1C,0x0A,0x30,0xDA,0x11,0x01,
++    0x30,0x02,0x81,0x07,0xF0,0x97,0xD1,0x2C,0x91,0x04,0x30,0xDA,0x08,0x01,0x00,0x19,
++    0xD0,0x1C,0x80,0x07,0xD0,0x1F,0x0C,0x09,0x30,0x42,0xD8,0x2C,0xD0,0x6C,0x80,0x07,
++    0xD4,0x3F,0x41,0xF2,0x00,0x44,0x01,0x01,0x00,0x84,0x09,0x01,0x00,0x77,0x00,0x01,
++    0xF0,0x02,0x11,0x01,0xF4,0x52,0x15,0x12,0xE9,0x06,0x00,0x44,0x15,0x01,0xF0,0x92,
++    0x10,0x12,0xD4,0x06,0x05,0x84,0xE1,0x20,0xE6,0x48,0x92,0x4D,0xC4,0x14,0x10,0x0A,
++    0x98,0x6E,0x87,0x3D,0xEF,0x85,0xAF,0xBD,0x80,0x55,0xC4,0x5C,0xD8,0x03,0x86,0x24,
++    0xCA,0x5C,0xD8,0x4B,0x8C,0x1C,0x50,0x52,0xCC,0x54,0xC0,0x48,0x8C,0x4C,0x48,0x4A,
++    0xC0,0x4B,0x48,0x09,0x88,0x46,0xC8,0x24,0xE6,0x48,0x92,0x4D,0x88,0x24,0x80,0x3C,
++    0xC0,0x5C,0xE0,0x03,0x80,0x1C,0x00,0x0F,0x00,0x01,0x80,0x3C,0xF8,0x3C,0xC0,0x5C,
++    0x80,0x01,0x86,0x44,0x04,0x7F,0x4B,0x12,0x04,0x01,0x00,0x43,0xC0,0x5C,0xC8,0x4C,
++    0xDB,0x03,0x1A,0xC2,0xC0,0x08,0x02,0x01,0x10,0xF9,0x01,0x1F,0x82,0x53,0xE0,0x48,
++    0xE6,0x00,0x92,0x05,0xDC,0x1C,0x10,0xC2,0x9C,0xC6,0x27,0x01,0x31,0x2A,0x31,0x32,
++    0x03,0xE7,0x40,0xC2,0x08,0x23,0x4E,0x2D,0xB8,0x0C,0x88,0x04,0x40,0x55,0x40,0x3E,
++    0x5F,0x35,0xB8,0xFF,0xF8,0x7F,0xC3,0x44,0xC8,0x03,0x42,0x31,0x83,0x7E,0x33,0x5A,
++    0x00,0xC1,0xF0,0xC2,0x40,0xE1,0xD1,0x1E,0x68,0x41,0x80,0x4E,0x18,0x62,0x05,0x1F,
++    0x70,0x01,0x8C,0x0E,0x30,0x72,0x01,0x1F,0x41,0x68,0x1B,0x62,0x6F,0x01,0x88,0x06,
++    0xC0,0x5C,0xC8,0x4C,0xDB,0x03,0x1A,0xC2,0xC0,0x08,0x02,0x01,0x10,0x01,0x00,0x1F,
++    0x82,0x53,0xE0,0x48,0xE6,0x00,0x92,0x05,0xDC,0x1C,0x10,0xC2,0x99,0xC6,0x37,0xAA,
++    0x20,0x01,0x00,0x0F,0x1B,0xA2,0x41,0xB0,0x77,0x01,0x88,0xDE,0xC0,0x5C,0x60,0x04,
++    0xC0,0x41,0x91,0x35,0x05,0xAF,0x18,0x62,0x46,0xD2,0x0A,0x23,0x48,0x2D,0xB8,0x0C,
++    0x88,0x04,0x40,0x55,0x40,0x3E,0x58,0x35,0xB9,0xFF,0xFF,0xA7,0xC2,0x44,0xC8,0x03,
++    0x42,0x31,0x80,0x6E,0x30,0x5A,0x03,0xA1,0xF5,0xC2,0x10,0x82,0xE9,0x06,0x18,0x62,
++    0x40,0x68,0x6B,0x01,0x88,0x3E,0xC7,0x54,0x0E,0x59,0xCB,0x00,0x0A,0x48,0xC2,0x00,
++    0xB3,0x23,0xE0,0xF8,0x90,0xFD,0xC7,0x24,0x14,0x3A,0x9C,0x66,0xF1,0x3C,0x00,0xA7,
++    0xC3,0x54,0x08,0x59,0xCA,0x00,0x0C,0x48,0xC1,0x38,0xF2,0xC3,0x40,0x01,0x88,0x0E,
++    0x01,0x09,0xB0,0xC3,0xF0,0xE3,0x29,0x01,0x01,0x01,0x00,0x0F,0xE7,0x68,0x93,0x6D,
++    0x40,0x09,0x88,0x1E,0x60,0xF9,0x97,0x0E,0xE5,0x20,0x93,0x25,0x48,0xE2,0x01,0x01,
++    0x00,0x43,0xAC,0x48,0x46,0xDA,0x09,0x23,0x20,0x00,0x67,0x10,0x00,0x0F,0x00,0xBF,
++    0x40,0x48,0x32,0x82,0x17,0x42,0x80,0xDE,0x48,0x01,0xC9,0x06,0x08,0x01,0x89,0x04,
++    0x90,0x0C,0x40,0x55,0x41,0x6E,0x30,0x8A,0xBA,0xFF,0xF7,0x77,0x40,0x01,0x80,0x0E,
++    0x6E,0x29,0x98,0xDE,0xB3,0xE3,0xE1,0xB0,0x90,0xB5,0xC7,0x24,0x16,0x32,0x9C,0x3E,
++    0x87,0x6D,0xE8,0x85,0xAC,0xBD,0x87,0x15,0x30,0x62,0x30,0xB2,0x48,0x2A,0x01,0x01,
++    0x81,0x43,0x40,0x4A,0x40,0x0B,0x10,0x11,0x18,0x8A,0x00,0x0B,0x28,0x01,0x00,0x3F,
++    0x09,0x09,0x30,0x9A,0x30,0x52,0x31,0x42,0x81,0x07,0xC8,0x57,0xE7,0x68,0x93,0x6D,
++    0xDD,0x03,0x11,0x42,0xC1,0xA6,0x37,0x12,0x30,0x8A,0x01,0x11,0x84,0x07,0xC0,0x2F,
++    0x31,0x92,0x31,0x0A,0xC7,0x14,0xB8,0xFF,0xF9,0x77,0x30,0x12,0x30,0x8A,0x01,0x01,
++    0x83,0x07,0xC0,0xDF,0xE0,0x03,0x41,0x01,0x80,0xBE,0x69,0xB2,0x44,0x43,0x97,0x3D,
++    0x4F,0x04,0x01,0x43,0x40,0x7A,0x08,0x09,0x81,0x0B,0x30,0x12,0x30,0x8A,0x01,0x11,
++    0x83,0x07,0xC0,0x5F,0x30,0x1A,0xB1,0x04,0x08,0x01,0x00,0x09,0xD0,0x14,0x80,0x07,
++    0xC8,0xAF,0xB2,0x04,0xD9,0x0B,0x37,0x1A,0x00,0x11,0xD0,0x14,0x82,0x07,0xC8,0x77,
++    0x31,0x92,0x31,0x0A,0xC7,0x14,0xB8,0xFF,0xF1,0x37,0x37,0x12,0x30,0x8A,0x01,0x6F,
++    0x60,0x20,0x02,0x00,0x00,0xD0,0x00,0x01,0x48,0xE0,0x06,0x00,0xF8,0xFB,0x07,0x00,
++    0x10,0x00,0x00,0x42,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0x00,0x01,0x80,0x07,
++    0xC0,0x27,0x42,0x5A,0x08,0x01,0x80,0x0B,0x01,0x7B,0x37,0x1A,0xB0,0x04,0x08,0x01,
++    0x00,0x11,0xD0,0x14,0x81,0x07,0xC8,0x57,0x31,0x12,0x31,0x8A,0x00,0x11,0x80,0x07,
++    0xC0,0xA7,0x51,0x22,0x40,0x83,0x08,0x11,0x18,0x42,0x04,0x83,0x87,0x2D,0xE8,0x85,
++    0x00,0xD0,0x00,0x01,0x18,0x00,0x04,0x42,0xA8,0x85,0x31,0x12,0x92,0x01,0x46,0x8C,
++    0x80,0x01,0xC7,0x1B,0x32,0xD8,0x72,0xD8,0x87,0x1B,0x58,0xE2,0x41,0xE3,0x30,0x20,
++    0xA2,0x16,0x40,0xE3,0x3F,0x20,0xAB,0xE6,0x58,0xCA,0x27,0x41,0x00,0xE3,0x44,0xE3,
++    0x28,0xF9,0xAF,0x19,0x18,0x62,0x01,0xE3,0xC7,0x23,0x48,0x20,0x8A,0x1E,0xF0,0x48,
++    0x20,0x48,0x60,0x48,0x88,0xC6,0x4F,0x01,0x88,0x36,0x40,0xC3,0x08,0x81,0x18,0x42,
++    0x07,0xC3,0x00,0xF9,0x82,0x89,0x04,0x84,0xEF,0x85,0xA9,0x85,0x46,0x63,0x42,0x5B,
++    0xDF,0xAB,0x72,0x62,0xC0,0xB3,0x71,0x09,0x8E,0x16,0x48,0x63,0x50,0x5B,0xE2,0xAB,
++    0x41,0x01,0x88,0x0E,0x10,0x01,0x00,0xE7,0x40,0x03,0x31,0x32,0xB5,0x41,0x30,0xA2,
++    0xE8,0x08,0x30,0x42,0xC4,0x01,0x5A,0x33,0xC1,0xFB,0x18,0xF2,0x1E,0x33,0x5C,0x33,
++    0xC5,0xFB,0x18,0xF2,0x1B,0x33,0x36,0x32,0x40,0x83,0xC1,0xF3,0x1B,0x82,0x35,0x32,
++    0x00,0x83,0x41,0x73,0xC4,0xC3,0x18,0x32,0x01,0x73,0xE8,0x20,0xE2,0xD8,0xE2,0x90,
++    0x95,0x95,0x16,0x52,0x9F,0x06,0xEF,0x85,0x41,0x09,0x88,0x0E,0x10,0x01,0x00,0xE7,
++    0x40,0x03,0x31,0x32,0xB5,0x41,0x30,0xA2,0xE8,0x08,0x30,0x42,0xC4,0x01,0x5A,0x33,
++    0xC5,0xFB,0x18,0xF2,0x1E,0x33,0x5C,0x33,0xC5,0xFB,0x18,0xF2,0x1B,0x33,0x36,0x32,
++    0x40,0x83,0xC1,0xF3,0x1B,0x82,0x35,0x32,0x00,0x83,0x41,0x73,0xC0,0xC3,0x18,0x32,
++    0x01,0x73,0xE8,0x20,0xE2,0xD8,0xE2,0x90,0x95,0x95,0x16,0x52,0x9F,0x06,0xEF,0x85,
++    0x41,0x11,0x88,0x0E,0x10,0x01,0x00,0xE7,0x40,0x03,0x31,0x32,0xB5,0x41,0x30,0xA2,
++    0xE8,0x08,0x30,0x42,0xC4,0x01,0x5A,0x33,0xC5,0xFB,0x18,0xF2,0x1E,0x33,0x5C,0x33,
++    0xC5,0xFB,0x18,0xF2,0x1B,0x33,0x36,0x32,0x40,0x83,0xC1,0xF3,0x1B,0x82,0x31,0x32,
++    0x00,0x83,0x41,0x73,0xC4,0xC3,0x18,0x32,0x01,0x73,0xE8,0x20,0xE2,0xD8,0xE2,0x90,
++    0x95,0x95,0x16,0x52,0x9F,0x06,0xEF,0x85,0x47,0x19,0x88,0xE6,0x10,0x01,0x00,0xE7,
++    0x40,0x03,0x31,0x32,0xB5,0x41,0x30,0xA2,0xE8,0x08,0x30,0x42,0xC4,0x01,0x5A,0x33,
++    0xC5,0xFB,0x18,0xF2,0x1E,0x33,0x5C,0x33,0xC5,0xFB,0x18,0xF2,0x1B,0x33,0x36,0x32,
++    0x40,0x83,0xC1,0xF3,0x1B,0x82,0x31,0x32,0x00,0x83,0x41,0x73,0xC0,0xC3,0x18,0x32,
++    0x01,0x73,0xE8,0x20,0xE2,0xD8,0xE2,0x90,0x95,0x95,0x16,0x52,0x9F,0x06,0xEF,0x85,
++    0xAA,0x85,0x47,0xE3,0x05,0xB0,0xCC,0x20,0x45,0xEB,0xC6,0x68,0x40,0x09,0x88,0x26,
++    0x45,0xE3,0xC8,0x20,0x44,0xDB,0xC4,0xE8,0x04,0x3F,0x78,0xD2,0xC0,0xFB,0x79,0x09,
++    0x8E,0x1E,0x48,0xE3,0xCA,0x20,0x55,0xDB,0xC1,0xE8,0x44,0x13,0xF9,0xA0,0xC0,0x5B,
++    0x40,0x09,0x88,0x76,0x48,0x01,0x88,0x66,0x44,0x83,0x1A,0xC2,0x04,0x83,0x42,0x83,
++    0x1C,0xC2,0x04,0x83,0x44,0x03,0x19,0xC2,0x00,0x03,0x41,0x83,0x18,0xC2,0x00,0x83,
++    0xE8,0x85,0x4F,0x09,0x8A,0x66,0x40,0x83,0x1A,0xC2,0x04,0x83,0x44,0x83,0x1C,0xC2,
++    0x00,0x83,0x44,0x83,0x18,0xC2,0x04,0x83,0x40,0x03,0x19,0xC2,0x07,0x03,0xE9,0x85,
++    0x48,0x11,0x88,0x66,0x44,0x03,0x19,0xC2,0x00,0x03,0x41,0x83,0x18,0xC2,0x04,0x83,
++    0x40,0x83,0x1A,0xC2,0x04,0x83,0x42,0x83,0x1C,0xC2,0x04,0x83,0xE8,0x85,0x4F,0x19,
++    0x89,0xE6,0x47,0x03,0x19,0xC2,0x04,0x03,0x44,0x83,0x18,0xC2,0x02,0x83,0x40,0x83,
++    0x1A,0xC2,0x04,0x83,0x40,0x83,0x1C,0xC2,0x07,0x83,0xEC,0x85,0xA8,0xFD,0xF7,0x4C,
++    0x30,0x62,0x2C,0x01,0x4D,0x93,0x49,0x8B,0x32,0x72,0xDC,0xE3,0x33,0x3A,0x49,0x8A,
++    0xC0,0x4B,0x48,0x09,0x89,0x0E,0x50,0x93,0xE0,0xE3,0x40,0x19,0x80,0x96,0x31,0x79,
++    0x49,0x5A,0x13,0xB0,0x40,0x11,0x88,0xB6,0x32,0x02,0x1B,0x3A,0x58,0x52,0xC3,0x14,
++    0xC1,0x00,0xC6,0xC0,0x33,0x9A,0x33,0x2A,0xEA,0xDA,0x0A,0x5B,0x08,0x01,0x00,0x3F,
++    0xC1,0x1B,0x18,0x9A,0x41,0xAB,0x00,0x5B,0xEA,0x90,0xE0,0x00,0xE6,0x48,0x92,0x4D,
++    0x17,0x0A,0x9D,0xAE,0xE8,0xFD,0x47,0x01,0x88,0x8E,0x18,0x01,0x12,0x5B,0x46,0xDA,
++    0x45,0x33,0x40,0xB0,0x00,0xB0,0x05,0x33,0x00,0x1B,0x02,0x5B,0x40,0x0B,0x18,0x81,
++    0x18,0xCA,0x04,0x0B,0x44,0x0B,0x18,0x01,0x18,0xCA,0x00,0x0B,0x00,0x17,0x40,0x09,
++    0x89,0x06,0x30,0xAA,0x00,0x01,0x00,0x27,0x40,0x8B,0x00,0x6B,0xEA,0x90,0xE0,0x00,
++    0x95,0x05,0x16,0x02,0x9F,0xC6,0xEF,0xFD,0x3B,0x82,0xAB,0x85,0x4A,0xA3,0xD8,0xEB,
++    0x33,0x70,0x72,0xB0,0x48,0x5A,0xC2,0x4B,0x48,0x09,0x88,0x0E,0x50,0xA3,0xE0,0xEB,
++    0x08,0x01,0x00,0x3F,0x42,0x13,0x41,0x93,0x00,0x92,0x07,0x14,0xEC,0x20,0xE1,0x00,
++    0xE6,0x48,0x92,0x4D,0x17,0x4A,0x9D,0xAE,0xEB,0x85,0xAB,0xC5,0x30,0x2A,0x30,0xB2,
++    0x61,0xF2,0x41,0x03,0x14,0x01,0x1C,0x82,0x01,0x03,0x41,0x03,0x10,0x81,0x18,0x82,
++    0x01,0x03,0x41,0x03,0x10,0x09,0x18,0x82,0x07,0x03,0xE1,0x53,0x00,0xF9,0x87,0x81,
++    0x19,0x12,0x40,0xBA,0x10,0x13,0x16,0x99,0x00,0x13,0x13,0x41,0x04,0x13,0x14,0xD9,
++    0xE8,0x92,0x52,0x01,0x80,0x16,0x10,0xC9,0x00,0x13,0x00,0x0F,0x10,0x89,0x00,0x13,
++    0x31,0x52,0x30,0x5A,0x08,0x01,0x00,0x09,0xB7,0x04,0xB8,0xFF,0xF9,0x7F,0x33,0x52,
++    0x30,0x8A,0x01,0x11,0xBB,0xFF,0xF7,0xCF,0x42,0x03,0x3B,0x00,0xAB,0xE6,0xEF,0xC5,
++    0xAC,0x9D,0x87,0x8D,0xCA,0x94,0xC8,0x4B,0x88,0x84,0xE0,0x94,0xA7,0x01,0xD2,0x1B,
++    0xD8,0x0B,0x89,0x04,0xCA,0x94,0xD8,0x6B,0x30,0x0A,0x88,0x71,0x30,0x62,0xCC,0x94,
++    0x30,0x01,0xE8,0x4B,0x48,0x09,0x88,0x56,0x08,0x01,0x00,0x27,0xC5,0x38,0x9A,0xF3,
++    0xA2,0x32,0xE2,0x48,0x90,0x4D,0xD2,0x94,0xDC,0x93,0x12,0x52,0xE0,0xB6,0x57,0xDA,
++    0x04,0xB3,0x02,0xB3,0x00,0xB3,0x0E,0x01,0x18,0x4A,0x06,0x8B,0xCA,0x94,0xD8,0x4B,
++    0xB0,0x8B,0x08,0x01,0x50,0xAA,0x30,0x01,0x05,0x78,0xC4,0xF8,0x0A,0xF3,0xC1,0x90,
++    0xB2,0xB3,0xE2,0x48,0x90,0x4D,0x4A,0x11,0xD8,0xA6,0xCF,0x94,0xE8,0x4B,0x48,0x29,
++    0xCD,0xF6,0x03,0x48,0xC3,0x48,0x00,0x50,0xC0,0x70,0x54,0x6A,0xC0,0xB0,0xB5,0x14,
++    0xC0,0x48,0x8C,0x0C,0x30,0x12,0x33,0x32,0xB0,0xE1,0x08,0x01,0x88,0x34,0x48,0x4A,
++    0x88,0x6C,0x88,0x64,0x30,0x32,0x04,0x01,0x32,0x22,0x04,0x97,0x18,0x00,0x04,0x42,
++    0x00,0x01,0x00,0x42,0x00,0xD0,0x00,0x01,0x60,0x20,0x02,0x00,0x80,0x40,0x07,0x01,
++    0x48,0xE0,0x06,0x00,0x78,0xF8,0x07,0x00,0xC8,0x14,0x00,0x01,0xF0,0x42,0xF8,0x0C,
++    0x0B,0x01,0xF0,0xCA,0x32,0x7A,0xD0,0x08,0x97,0x4D,0x48,0xF9,0xEF,0x06,0x08,0xF9,
++    0xCB,0x38,0x86,0xF8,0x78,0xF9,0xEF,0x06,0x3B,0xF9,0x37,0x82,0x82,0x3B,0xE0,0x00,
++    0x30,0x32,0xC4,0xBB,0x10,0xFA,0x9C,0x46,0x10,0xCA,0xDC,0x36,0x46,0x84,0xD9,0x48,
++    0xC0,0x00,0x92,0x05,0x04,0x84,0x81,0x08,0x04,0x37,0x10,0xCA,0xDC,0x16,0x00,0x78,
++    0x00,0xBC,0x01,0x0F,0x39,0x01,0x00,0xBC,0x10,0xCA,0xDC,0x0E,0x38,0x09,0xB8,0x34,
++    0x43,0x78,0x2B,0x3A,0xE8,0x26,0xF8,0x6C,0x10,0x7A,0xEC,0x2E,0x88,0x6C,0x00,0x1F,
++    0xFC,0x64,0x10,0x7A,0xE8,0x06,0x88,0x64,0x82,0x8B,0xE0,0x90,0xE0,0xB0,0xC5,0x14,
++    0xE0,0x00,0x84,0x14,0xC4,0x0C,0xE0,0x00,0x83,0x0C,0x30,0x02,0xE2,0x00,0x92,0x05,
++    0x35,0x22,0x2C,0x62,0xD8,0xC6,0xC5,0x34,0x40,0x01,0x80,0x8E,0x08,0x01,0x00,0x01,
++    0x80,0x5C,0xC0,0x04,0xC2,0x00,0x46,0x00,0x80,0x7C,0xC0,0x04,0x30,0x00,0x72,0x00,
++    0x80,0x74,0x00,0x01,0x30,0x22,0x84,0x2C,0x80,0x24,0x80,0x1C,0xF0,0x90,0x02,0x07,
++    0x03,0x1F,0xF5,0x40,0x94,0x05,0x32,0x32,0x03,0xFF,0x31,0x02,0x04,0x00,0x32,0x22,
++    0xC2,0x2C,0x00,0x00,0x80,0x2C,0xC0,0x24,0x00,0x00,0x82,0x24,0xC2,0x1C,0x00,0x00,
++    0x83,0x1C,0x40,0x40,0x28,0x82,0xEB,0x26,0xC0,0x83,0xF0,0x6C,0xD8,0x00,0x84,0x83,
++    0x00,0x1F,0xC0,0x83,0xF4,0x64,0xD8,0x00,0x80,0x83,0xC0,0x83,0x73,0x3D,0x30,0xBA,
++    0xA8,0x82,0xC7,0x83,0x10,0xC2,0xDC,0xDE,0xE2,0x48,0x92,0x4D,0xF1,0x5C,0xC0,0xB0,
++    0x90,0xB5,0xB1,0x5C,0x30,0x32,0x3B,0x09,0x1D,0xF2,0x31,0xA2,0xF5,0x7C,0x10,0x82,
++    0xD8,0x76,0xF0,0x2C,0x18,0xF2,0xB1,0x2C,0xF5,0x04,0x10,0x82,0xD8,0x46,0xF0,0x24,
++    0x18,0xF2,0xB1,0x24,0xF5,0x74,0x10,0x82,0xD8,0x16,0xC0,0x1C,0x18,0xC2,0x81,0x1C,
++    0xF3,0x90,0x32,0x82,0xF2,0x00,0x92,0x05,0x33,0x32,0x34,0x82,0x45,0x01,0xD0,0xE6,
++    0x42,0xE2,0xB7,0x0B,0xD0,0x50,0xB3,0x13,0x36,0x12,0x1B,0x92,0x03,0x13,0x30,0x12,
++    0x08,0x13,0xD0,0x2C,0x00,0x13,0xD2,0x24,0x00,0x13,0xD4,0x1C,0x00,0x13,0x36,0x01,
++    0x00,0xA7,0xC1,0x5C,0x86,0x07,0xE8,0xA7,0x90,0x05,0x80,0x5C,0x4D,0x8A,0x07,0x80,
++    0xC0,0x00,0x4A,0x13,0x40,0x3D,0x08,0x01,0x1C,0x01,0x30,0xF2,0x30,0xE2,0x04,0xCF,
++    0x38,0x98,0x86,0x7E,0xC0,0x1B,0xF8,0x5C,0xD8,0xD8,0x96,0xDD,0x58,0x01,0xE8,0x36,
++    0x83,0x1B,0x20,0x9A,0x94,0xDD,0x36,0xF2,0xE2,0x48,0x92,0x4D,0x00,0x27,0x18,0x01,
++    0x80,0x1B,0x00,0x0F,0x18,0x01,0x80,0x1B,0x42,0x90,0xE2,0x00,0x32,0x1A,0xE3,0xD8,
++    0x94,0xDD,0x32,0xE2,0x2F,0x62,0xDD,0x1E,0xE3,0xB0,0x93,0xB5,0x30,0x82,0x83,0x5C,
++    0x45,0xE2,0x06,0x98,0xC0,0xD8,0x08,0xD3,0xCA,0x00,0xB4,0x0B,0x48,0x21,0xD8,0x0E,
++    0x76,0x09,0xD8,0x36,0x06,0x01,0x50,0xBA,0x04,0x08,0xC4,0x58,0xE4,0x08,0x02,0x70,
++    0xC0,0xB0,0x4D,0xEB,0x4D,0xB3,0x19,0xAA,0x08,0xEB,0xC0,0x80,0xF4,0x1B,0xF2,0x2B,
++    0xDA,0xD8,0xB2,0x1B,0x90,0x45,0x42,0x09,0xD8,0x76,0x07,0x09,0xA6,0x03,0x43,0x6A,
++    0x0E,0x19,0x40,0x13,0x50,0x01,0x80,0x16,0x03,0x29,0xA0,0x0B,0x04,0xF7,0x40,0x13,
++    0x50,0x01,0x80,0x16,0x03,0x21,0xA0,0x0B,0x02,0xC7,0x40,0x0B,0x48,0x01,0x80,0x1E,
++    0x00,0x19,0x08,0x11,0xA0,0x0B,0x03,0x8F,0x48,0x03,0x40,0x01,0x88,0x26,0xC0,0x94,
++    0x86,0x01,0xCE,0x03,0x40,0x51,0x98,0x0E,0x00,0x11,0x00,0x3F,0xC1,0x94,0x80,0x01,
++    0xE0,0x03,0x44,0x01,0x80,0x0E,0x00,0x11,0x00,0x07,0x00,0x09,0xE4,0x0B,0xE3,0x50,
++    0xA3,0x13,0xDD,0x13,0x38,0x90,0xA2,0x0E,0xF3,0x48,0xA2,0x0B,0xE8,0x0B,0x13,0x29,
++    0x10,0x0A,0x94,0x0E,0xA8,0x13,0x01,0xEF,0x10,0x0A,0xCC,0x46,0x40,0x09,0x88,0x16,
++    0x09,0x81,0xAF,0x0B,0x00,0xB7,0xD0,0x48,0x01,0x52,0xAC,0x13,0x00,0x97,0x40,0x19,
++    0xC8,0x0E,0x08,0x19,0x02,0x07,0x90,0x0D,0xE8,0x13,0x51,0x01,0x82,0x16,0xF0,0x90,
++    0xA8,0x13,0x01,0x3F,0xD2,0x94,0xF0,0x48,0xCA,0x93,0x1C,0x52,0xCA,0x84,0xC0,0x88,
++    0xD0,0x94,0x88,0x8B,0xA8,0x03,0x83,0x9D,0xEF,0x85,0xAF,0xBD,0x80,0x6D,0x34,0x6A,
++    0xD9,0x63,0x33,0x42,0x80,0x01,0x82,0x64,0xD0,0x03,0x84,0x3C,0xC2,0x64,0xD8,0x03,
++    0x30,0x00,0xA8,0x1E,0x02,0xD9,0xEC,0x02,0x40,0x01,0x80,0xA6,0xC5,0x6C,0x00,0x08,
++    0xC3,0x40,0x00,0x08,0x52,0xC2,0xC4,0x08,0xC4,0x48,0xC4,0x10,0x00,0x01,0x18,0x01,
++    0x00,0x2F,0x00,0x5C,0x04,0x9C,0xE0,0x48,0xE2,0x90,0xE4,0x00,0x95,0x05,0x12,0x02,
++    0xD8,0xBE,0x87,0x85,0xEB,0x85,0x07,0x59,0xCA,0x6C,0x08,0x00,0xC4,0x40,0x70,0x7A,
++    0xF7,0x03,0x08,0x83,0xD0,0x7C,0x90,0x04,0x30,0x5A,0x09,0x01,0x00,0x11,0xD0,0x6C,
++    0xBB,0xFF,0xEF,0xE7,0x42,0x4A,0x84,0x01,0x43,0x0B,0x30,0x5A,0x09,0xCC,0x5C,0x8B,
++    0x0B,0xCC,0x5E,0x8B,0x15,0xCC,0x58,0x8B,0x17,0xCC,0x42,0x8B,0x14,0xCC,0x4C,0x22,
++    0x46,0x53,0x10,0xD4,0x48,0x93,0x1F,0xD4,0x17,0x89,0x00,0x93,0x13,0x19,0x18,0x93,
++    0x40,0x53,0x18,0x11,0x18,0xD2,0x04,0x53,0x40,0x0B,0x18,0xCA,0x01,0x0B,0x30,0x42,
++    0xE9,0x4B,0x81,0x01,0x80,0x5C,0x48,0x09,0x8D,0x5E,0x6A,0x44,0x81,0x14,0x30,0x8A,
++    0x5E,0x43,0x94,0x35,0xB0,0x0C,0x00,0x01,0x80,0x04,0xD0,0x6C,0x4F,0x92,0x03,0x00,
++    0xC2,0x00,0xC4,0x00,0x83,0x54,0x40,0x8A,0x18,0x33,0x0A,0x01,0x37,0x42,0xB9,0xFF,
++    0xE0,0x5F,0xF9,0x54,0xC1,0x64,0x30,0x5A,0xD1,0x0B,0x32,0xC2,0xD7,0x7C,0xB8,0xFF,
++    0xEB,0x67,0x4C,0x62,0x10,0x01,0x00,0x01,0x02,0x67,0x00,0x18,0x37,0xE2,0xF4,0xDA,
++    0x10,0x5A,0xD4,0x0E,0x33,0x0A,0xD3,0xCA,0x10,0x9A,0xEC,0x0E,0x35,0x12,0xD3,0xD2,
++    0xE2,0x00,0x92,0x05,0x17,0x02,0xDD,0x86,0xC4,0x14,0xE0,0x00,0x10,0x0A,0x9C,0x36,
++    0xC0,0x04,0x40,0x01,0x8B,0x9E,0x40,0x80,0x40,0x08,0xC2,0x70,0x00,0x3F,0xC0,0x14,
++    0xF4,0x00,0x14,0x12,0xE0,0x5E,0x00,0x09,0x83,0x04,0xE0,0xB0,0x90,0xB5,0x77,0x01,
++    0x80,0x16,0xC0,0x0C,0x16,0x32,0x9C,0x36,0x70,0x01,0x88,0x06,0x30,0x09,0xC0,0x5C,
++    0x90,0x33,0xC0,0x5C,0xD2,0x0B,0x40,0x8A,0x18,0x0B,0x32,0x01,0x36,0x42,0x81,0x01,
++    0x81,0x4C,0x80,0x01,0x83,0x44,0x00,0x37,0xC4,0x3C,0x10,0x32,0xD0,0x6E,0xC0,0x44,
++    0xC0,0x03,0xC8,0x44,0x32,0x00,0x72,0x00,0x82,0x43,0x40,0x42,0x0C,0x41,0x00,0x0B,
++    0x47,0x0B,0x10,0xF9,0x90,0x21,0x18,0x8A,0x00,0x0B,0xC8,0x6C,0x02,0x00,0xC5,0x08,
++    0x02,0x00,0x53,0x0A,0xC4,0x40,0xC0,0x00,0xC0,0x48,0x74,0x01,0x88,0x66,0x10,0x01,
++    0x78,0x02,0x02,0x37,0x18,0x01,0x00,0x1C,0x04,0x7C,0xE0,0x00,0xE2,0x48,0xE4,0x90,
++    0x95,0x95,0x12,0x12,0xD9,0xB6,0x07,0x07,0xDF,0x6C,0x00,0x10,0xC1,0x90,0x5E,0xB2,
++    0xC4,0x90,0x36,0xA2,0x18,0x01,0x00,0x9F,0x30,0x3A,0x13,0x01,0xF0,0xD2,0x3D,0x01,
++    0xFC,0x3A,0x16,0xBA,0xD0,0x06,0x00,0x14,0x3E,0x01,0xF8,0x7A,0x10,0xBA,0xEC,0x06,
++    0x04,0x54,0xE0,0x00,0xE3,0x48,0x34,0x12,0xE4,0x90,0x34,0xA2,0xE2,0xD8,0x92,0xDD,
++    0x17,0x1A,0xDD,0x4E,0xC4,0x3C,0x10,0x32,0x80,0x06,0xC1,0x44,0xC6,0x03,0x48,0x00,
++    0x88,0x1E,0xC0,0x4C,0xC8,0x03,0x42,0x31,0x88,0xBE,0xC7,0x4C,0xC8,0x03,0x42,0x31,
++    0x89,0x26,0x40,0x12,0x40,0x0B,0x10,0x81,0x18,0x8A,0x00,0x0B,0xCF,0x6C,0x00,0x00,
++    0xC0,0x00,0x4A,0xEA,0xC0,0x00,0xCA,0x64,0x32,0x5A,0xD1,0x4B,0xD7,0x7C,0xB8,0xFF,
++    0xE3,0x67,0xE7,0xB0,0x90,0xB5,0xC3,0x3C,0x14,0x32,0xEC,0xAE,0x43,0xBA,0x30,0x5A,
++    0x4A,0xCC,0x84,0x01,0x00,0x0B,0x40,0xAA,0x48,0xCC,0x1E,0x0B,0x52,0xCC,0x18,0x0B,
++    0x54,0xCC,0x1A,0x0B,0x56,0xCC,0x04,0x0B,0x4E,0x8A,0x50,0xD4,0x00,0x53,0x58,0xCC,
++    0x0F,0x0B,0x36,0xB7,0xAA,0x85,0xD8,0xE3,0x1A,0x0A,0x03,0x48,0xC5,0x50,0x0C,0x49,
++    0x02,0x48,0xC4,0x88,0xE8,0xD3,0x50,0x11,0xC0,0x4E,0x10,0x01,0x00,0x2F,0x40,0x1C,
++    0x04,0x5C,0xE0,0x48,0xE2,0x00,0xE4,0x90,0x95,0x95,0x12,0x12,0xD8,0xBE,0x17,0x01,
++    0x00,0x87,0x00,0x00,0x80,0x40,0x07,0x01,0x48,0xE0,0x06,0x00,0x00,0x01,0x00,0x42,
++    0x18,0x00,0x04,0x42,0xF8,0xFB,0x07,0x00,0x40,0x1C,0x00,0x5C,0xE4,0x00,0xE4,0x48,
++    0xE2,0x90,0x92,0x95,0x17,0x12,0xDD,0xBE,0xEF,0x85,0xA8,0x85,0x30,0x6A,0xF0,0x2C,
++    0x30,0x22,0x30,0x8A,0x31,0xFA,0x30,0xC2,0xB9,0xFF,0xDF,0xB7,0x31,0xDA,0x31,0x92,
++    0x31,0x4A,0x31,0x02,0xBC,0xFF,0xE7,0xCF,0xE8,0x85,0x37,0x0A,0x8D,0x01,0x86,0x01,
++    0x02,0x5F,0xC8,0x5B,0x58,0x31,0x88,0x46,0x40,0xFA,0x47,0x0B,0x10,0x81,0x18,0x8A,
++    0x00,0x0B,0x40,0x0B,0x18,0x8A,0x00,0x0B,0x3E,0x82,0xCB,0x1B,0x5F,0x01,0x88,0x86,
++    0x38,0x82,0xAB,0x85,0xDA,0x5B,0xD8,0x4B,0x1F,0x5A,0x4A,0xC2,0xC7,0x08,0x52,0xC2,
++    0xC0,0x00,0x14,0x01,0x00,0x27,0x40,0x24,0x04,0x64,0xE0,0x00,0xE2,0x48,0xE4,0x90,
++    0x17,0xD2,0x9C,0xC6,0xEF,0x85,0xA8,0xBD,0x80,0x15,0x34,0x62,0x37,0xBA,0xD8,0x33,
++    0xE8,0x03,0x09,0x01,0x18,0x4A,0x2E,0x01,0x40,0x29,0x90,0x16,0x1F,0x0B,0x1D,0x2B,
++    0x07,0x6F,0x00,0x09,0xEA,0x02,0x38,0x00,0xAF,0x26,0x50,0x52,0x58,0x03,0x1F,0x82,
++    0x18,0x03,0x05,0x27,0x57,0x3A,0x5F,0x03,0x18,0x92,0x1E,0x82,0x1D,0x03,0x1D,0x0B,
++    0x30,0x0A,0xC1,0x14,0xBC,0xFF,0xE7,0xE7,0x25,0x2B,0x59,0x03,0x28,0x01,0x00,0x17,
++    0x43,0x00,0xE2,0x68,0x96,0x6D,0x3F,0x08,0x8D,0x0E,0x10,0xAA,0x9B,0xC6,0xAF,0x2B,
++    0x73,0xCA,0x4E,0x04,0x00,0x83,0xC7,0x14,0x0A,0x59,0xCB,0x00,0x0A,0x48,0xC2,0x00,
++    0xF7,0x03,0x08,0x83,0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,0xBC,0xFF,0xDF,0x87,
++    0x30,0x1A,0xB9,0x04,0x30,0x4A,0x01,0x11,0xD7,0x14,0xB8,0xFF,0xD8,0xFF,0x06,0x09,
++    0xA7,0x01,0x8D,0x03,0x48,0x82,0x46,0x43,0x10,0x11,0x18,0x82,0x00,0x43,0x00,0x41,
++    0x01,0x83,0x45,0x83,0x08,0xF9,0x8F,0x19,0x19,0x42,0x00,0x83,0x87,0x2D,0xE8,0x85,
++    0x3F,0x82,0xAB,0xC5,0xD8,0x53,0x90,0x04,0xDC,0x53,0x32,0xB2,0xE9,0x53,0x54,0x91,
++    0x9E,0xBE,0x12,0x31,0xE0,0x92,0x52,0x01,0x8E,0x9E,0x52,0x02,0xC0,0x28,0x34,0x12,
++    0x91,0xE1,0x19,0xC1,0x8E,0x01,0xF4,0x1A,0xE8,0x63,0x3A,0x11,0x10,0x1A,0xDD,0x16,
++    0xD8,0xD8,0x38,0x1C,0xA9,0x7B,0x1E,0xD1,0xEE,0x63,0xF4,0x1A,0x15,0x32,0x13,0x9A,
++    0xE0,0x16,0xC8,0xD8,0x38,0x1C,0xB2,0x7B,0x30,0x01,0x38,0x01,0x1C,0x01,0x30,0xE2,
++    0x00,0x27,0x21,0x01,0x00,0xE7,0x18,0x01,0xF0,0x5A,0x5F,0x01,0xED,0x4E,0x10,0x9A,
++    0xE8,0x06,0x30,0xF2,0xE8,0x5B,0x5E,0x01,0x80,0x76,0x40,0x9C,0xF0,0xD8,0x02,0x9C,
++    0x00,0x57,0x58,0x01,0xD5,0x46,0x10,0xDA,0xD0,0x06,0x30,0xFA,0xF0,0x5B,0x58,0x01,
++    0x80,0x16,0x40,0x9C,0xE0,0xD8,0x02,0x9C,0xE4,0x68,0xE5,0x90,0xE7,0x20,0x93,0x25,
++    0x2F,0xA2,0x9B,0x06,0x32,0x1A,0xE3,0xD8,0x94,0xDD,0x36,0xE2,0xE5,0x04,0x28,0x22,
++    0x98,0xBE,0x7E,0x14,0xC8,0x90,0x3C,0x14,0x7E,0x14,0xCA,0x90,0x3E,0x14,0xEA,0x43,
++    0x40,0x01,0x80,0x0E,0xF6,0x00,0xAA,0x43,0xF0,0x43,0x40,0x01,0x82,0x0E,0xF0,0x00,
++    0xB7,0x43,0xE8,0xC5,0xAC,0xBD,0x87,0x15,0x30,0x62,0x30,0xBA,0xEF,0x2B,0xDB,0x33,
++    0xDB,0x03,0x1B,0x42,0x00,0x08,0xC2,0x14,0xC4,0x40,0x48,0x8A,0xC0,0x00,0x82,0x0C,
++    0x37,0x02,0x81,0x01,0xC4,0x0B,0x10,0x01,0x18,0x8A,0x80,0x0B,0x00,0x21,0xEE,0x02,
++    0x44,0x01,0x80,0x1E,0x09,0x09,0x30,0xDA,0x30,0x52,0x31,0x42,0xBF,0xFF,0xD7,0xC7,
++    0x30,0x1A,0xB9,0x04,0x08,0x01,0x00,0x19,0xD7,0x14,0xB8,0xFF,0xDA,0x3F,0x02,0x41,
++    0xE9,0x0A,0x30,0x1A,0x30,0xD2,0xC1,0x0C,0xBC,0xFF,0xDF,0x7F,0x31,0x1A,0x31,0x4A,
++    0xD0,0x14,0xC0,0x0C,0xBD,0xFF,0xF7,0xB7,0x50,0x02,0x1C,0x09,0xC0,0x83,0x40,0x01,
++    0x8B,0x5E,0xE0,0x68,0x95,0x6D,0x5F,0x0B,0x03,0x0F,0xE0,0x68,0x90,0x6D,0x37,0xC2,
++    0x00,0x42,0x15,0x0A,0x8D,0x0E,0x10,0xAA,0x99,0xBE,0x37,0x82,0x74,0x92,0x13,0x2A,
++    0x93,0xE6,0xA8,0x2B,0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,0xBE,0xFF,0xD7,0x47,
++    0x30,0x1A,0xB9,0x04,0x30,0x4A,0x01,0x11,0xD7,0x14,0xB8,0xFF,0xD8,0xBF,0xC0,0x14,
++    0x0A,0x59,0xCB,0x00,0x0A,0x48,0xC2,0x00,0xF7,0x03,0x08,0x83,0x05,0x41,0x00,0x83,
++    0x47,0x83,0x09,0xF9,0x88,0x19,0x18,0x42,0x01,0x83,0x39,0xBF,0xE1,0x0B,0x31,0x02,
++    0x80,0x01,0x4D,0x01,0x86,0x1E,0xC9,0x0B,0x49,0x09,0x88,0x06,0x0E,0x11,0x88,0x0B,
++    0xA8,0x2B,0x83,0x9B,0x4F,0x04,0x01,0x83,0x50,0x0A,0xCB,0x14,0xDC,0x03,0xC1,0x48,
++    0xE7,0x02,0x0A,0x83,0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,0xBC,0xFF,0xD7,0xC7,
++    0x30,0x1A,0xB9,0x04,0x30,0x4A,0x01,0x11,0xD7,0x14,0xB8,0xFF,0xD0,0x3F,0x07,0x41,
++    0x01,0x83,0x45,0x83,0x08,0xF9,0x8F,0x19,0x19,0x42,0x00,0x83,0x38,0x77,0x08,0x01,
++    0x88,0x0B,0x86,0x8B,0x3F,0x57,0xA8,0x85,0x84,0x9D,0x34,0x22,0x33,0x6A,0xD8,0x73,
++    0xD8,0x43,0x81,0x34,0x31,0x12,0x93,0xE1,0x92,0x94,0x48,0x72,0x32,0x02,0xC3,0x18,
++    0x4B,0x32,0x22,0x0A,0x8B,0x8C,0xC8,0x43,0x00,0x00,0x82,0x1C,0x00,0x01,0x80,0x14,
++    0x37,0x42,0x81,0x01,0x82,0x84,0xC0,0x03,0x5C,0x7B,0x35,0x32,0x3F,0x20,0x5A,0x43,
++    0x18,0x3A,0x60,0x01,0xD1,0x46,0x40,0xFA,0x18,0x3A,0xB8,0x0C,0x37,0x82,0x23,0xD9,
++    0x00,0x02,0xE1,0x84,0x80,0x03,0x03,0x47,0x46,0xD2,0x19,0x02,0x18,0x3A,0xB8,0x0C,
++    0x30,0x82,0x23,0x21,0x18,0x02,0xE1,0x84,0x80,0x03,0x3B,0x01,0x19,0x7B,0x37,0x42,
++    0x80,0x01,0x85,0x7C,0xC0,0x03,0x84,0x54,0xC0,0x7C,0x20,0x09,0xB8,0x22,0xA0,0x4C,
++    0x34,0x42,0x81,0x01,0x86,0x74,0x18,0x3B,0xB8,0x44,0xC0,0x74,0x18,0x3B,0xBC,0x3C,
++    0x31,0x42,0x81,0x01,0x84,0x6C,0xA0,0x3B,0xCA,0x43,0x45,0x00,0x86,0x2C,0x00,0x01,
++    0xFB,0x22,0x82,0x00,0x81,0x24,0xE8,0x43,0x40,0x29,0xC0,0xBE,0x03,0x01,0x30,0x22,
++    0x3B,0x04,0x39,0x04,0x20,0x01,0x00,0x77,0x00,0x01,0x00,0x47,0x40,0x7C,0x00,0xFC,
++    0x40,0x7C,0x00,0xBC,0xE4,0x90,0xE4,0x48,0xE2,0xD8,0xE4,0x00,0x95,0x05,0x12,0x82,
++    0xDB,0xA6,0xE7,0x20,0x90,0x25,0xC3,0x34,0x17,0x22,0xDC,0x6E,0xF8,0x94,0xE0,0x8C,
++    0x00,0x01,0x80,0x5C,0x00,0xAF,0x05,0x01,0x34,0x32,0x34,0x22,0xC8,0x5C,0x00,0x09,
++    0x00,0x42,0xCC,0x0C,0x80,0x64,0x10,0x42,0x81,0x7E,0xE3,0x53,0x50,0x01,0x80,0x2E,
++    0xC8,0x34,0xC0,0x5C,0xF4,0x48,0x12,0x42,0x88,0x06,0x30,0xB2,0x1A,0x01,0x00,0x87,
++    0x41,0xCC,0x41,0x14,0xD0,0x40,0x94,0x15,0x00,0x14,0xC9,0x1C,0x10,0x52,0xD4,0x3E,
++    0x32,0x02,0xE3,0x00,0x94,0x05,0x36,0x22,0x34,0x82,0xC3,0x00,0x94,0x05,0x30,0x32,
++    0xCC,0x2C,0x10,0x52,0xE8,0x3E,0x01,0x7F,0x00,0x01,0x00,0x42,0x48,0xE0,0x06,0x00,
++    0x38,0xA0,0x03,0x00,0xAA,0xAA,0xAA,0xAA,0x18,0x00,0x04,0x42,0x00,0xD0,0x00,0x01,
++    0x68,0xB8,0x03,0x00,0x28,0x60,0x00,0x00,0xCC,0x4B,0x13,0x8A,0xE7,0x1E,0x58,0x43,
++    0xC8,0x64,0x18,0x0A,0x18,0x4B,0xCF,0x6C,0xE8,0x4B,0x4A,0x09,0x88,0x16,0xC8,0x6C,
++    0x02,0x09,0xAC,0x43,0xCC,0x54,0x10,0x52,0xE8,0xBE,0x08,0x09,0xD4,0x44,0x00,0xCA,
++    0x18,0x8A,0x88,0x44,0x00,0x8F,0xC8,0x24,0x10,0x52,0xD4,0x76,0xCA,0x6C,0xE8,0x4B,
++    0x48,0x09,0x88,0x16,0xCC,0x6C,0x00,0x09,0xA8,0x43,0xCA,0x4C,0x10,0x52,0xD4,0x26,
++    0x08,0x09,0xD0,0x3C,0x00,0xCA,0x1C,0x8A,0x8D,0x3C,0xE0,0x20,0xE2,0xF8,0xE5,0xD8,
++    0x95,0xDD,0x12,0x9A,0xD8,0x66,0xC5,0x7C,0xC8,0x03,0x44,0x01,0x83,0x2E,0x32,0x02,
++    0x40,0x11,0xC8,0x2E,0x33,0x0A,0x33,0x82,0x83,0x07,0xC8,0xD7,0x90,0x05,0x00,0x07,
++    0x03,0x01,0x00,0x88,0xD0,0x20,0x13,0x01,0x01,0x57,0x01,0x67,0x40,0x01,0xE8,0x7E,
++    0x0B,0x01,0xF0,0x0A,0xDC,0x1C,0x10,0xCA,0xD2,0xB6,0xE0,0x18,0x10,0xCA,0xEC,0x16,
++    0xD1,0x48,0x00,0x0C,0x00,0x87,0x48,0x01,0xE8,0x76,0x08,0x09,0x00,0x0C,0x01,0x5F,
++    0x0B,0x01,0xF0,0x0A,0x10,0x0A,0xD4,0x16,0xD1,0x48,0x00,0x0C,0x00,0x27,0x48,0x01,
++    0xD0,0x16,0x08,0x01,0x19,0x4A,0x06,0x0C,0x0B,0x01,0xF0,0x0A,0xDC,0x24,0x10,0xCA,
++    0xD0,0x1E,0xC8,0x14,0xE6,0x48,0x92,0x4D,0x8D,0x14,0xE0,0x20,0xE2,0x90,0x92,0x95,
++    0x16,0x92,0xDD,0x9E,0x00,0x4F,0x00,0x01,0x08,0x01,0x00,0x27,0x05,0x0C,0xE1,0x20,
++    0xE2,0xF8,0xE5,0x00,0x95,0x05,0x12,0x82,0xD8,0xC6,0xC7,0x5C,0xE2,0x00,0x92,0x05,
++    0x80,0x5C,0xC8,0x34,0xC4,0x5C,0x10,0x42,0xD2,0x06,0x38,0x27,0xC9,0x43,0x41,0x71,
++    0xC9,0x0E,0x00,0x71,0x88,0x43,0xC1,0x14,0xCC,0x4B,0x41,0x00,0xC6,0x40,0x90,0x05,
++    0x8A,0x43,0x41,0x81,0xCA,0x0E,0x00,0x81,0x88,0x43,0x01,0x01,0x29,0x44,0x37,0x44,
++    0xC0,0x74,0xC8,0x44,0x18,0x0B,0xCE,0x74,0xC4,0x3C,0x18,0x43,0x87,0x9D,0xE8,0x85,
++    0xA8,0x85,0x33,0x2A,0x30,0x62,0x30,0xB2,0x31,0x0A,0x31,0x42,0xBA,0xFF,0xEF,0xCF,
++    0x48,0x6A,0x03,0x01,0x81,0x43,0x30,0x92,0x31,0x0A,0x31,0x42,0xBB,0xFF,0xEF,0x1F,
++    0xEE,0x03,0x41,0x41,0x92,0x0E,0xE0,0x00,0xAB,0x03,0xE9,0x85,0x10,0x01,0x00,0x37,
++    0x0A,0x01,0xE0,0x48,0x90,0x4D,0x4C,0xA1,0xCA,0xDE,0xE7,0x90,0x94,0x95,0x14,0x12,
++    0xCB,0xB6,0x3F,0x82,0x38,0x18,0x78,0xD8,0x14,0x09,0x00,0xD2,0x97,0x95,0x1E,0xF9,
++    0x08,0xD8,0x00,0xC2,0x5E,0xEA,0xC2,0x00,0x48,0x09,0x88,0x66,0x44,0x0B,0x18,0x8A,
++    0x02,0x0B,0x40,0x0B,0x1A,0x8A,0x04,0x0B,0x44,0x0B,0x1C,0x8A,0x06,0x0B,0x44,0x0B,
++    0x1E,0x8A,0x04,0x0B,0x38,0x82,0x4B,0x01,0x8A,0x66,0x40,0x0B,0x1A,0x8A,0x04,0x0B,
++    0x44,0x0B,0x1C,0x8A,0x06,0x0B,0x44,0x0B,0x1E,0x8A,0x04,0x0B,0x40,0x0B,0x18,0x8A,
++    0x03,0x0B,0x38,0x82,0x48,0x11,0x88,0x66,0x44,0x0B,0x18,0x8A,0x02,0x0B,0x40,0x0B,
++    0x1A,0x8A,0x04,0x0B,0x44,0x0B,0x1C,0x8A,0x06,0x0B,0x44,0x0B,0x1E,0x8A,0x00,0x0B,
++    0x38,0x82,0x4B,0x19,0x88,0xE6,0x47,0x0B,0x18,0x8A,0x04,0x0B,0x44,0x0B,0x1C,0x8A,
++    0x06,0x0B,0x44,0x0B,0x1E,0x8A,0x04,0x0B,0x40,0x0B,0x1A,0x8A,0x03,0x0B,0x3A,0x82,
++    0xAC,0x8D,0x87,0x3D,0xC0,0x3C,0xC8,0x3C,0x4C,0x00,0x00,0x00,0xC0,0x00,0x3A,0x00,
++    0x4A,0xDA,0x71,0x00,0xC1,0x28,0x42,0xDA,0x44,0x0B,0x90,0x4D,0x88,0x34,0x58,0x0B,
++    0x90,0x4D,0x8C,0x2C,0x5C,0x0B,0x92,0x4D,0x8C,0x24,0x58,0x0B,0x90,0x4D,0x8C,0x1C,
++    0x54,0x0B,0x96,0x75,0x4A,0xA2,0x41,0x53,0x90,0x95,0x94,0x14,0x44,0x53,0x90,0xBD,
++    0x44,0x13,0x92,0x95,0x91,0x0C,0x58,0x7A,0x98,0x01,0x52,0xD3,0x90,0x95,0x94,0x04,
++    0x10,0x09,0x00,0x13,0xA8,0x10,0x1C,0x13,0x12,0x81,0x18,0x13,0x18,0x13,0x14,0x79,
++    0x11,0x13,0x16,0x01,0x00,0x53,0x12,0x89,0x02,0x53,0x40,0x0B,0x10,0x81,0x19,0x8A,
++    0x07,0x0B,0x02,0xF9,0x80,0x89,0x17,0xC3,0x07,0x09,0xB8,0xFF,0xFF,0x7F,0x03,0xF9,
++    0x80,0x89,0x14,0xC3,0x07,0x09,0xB8,0xFF,0xF8,0x4F,0x03,0x19,0x11,0x00,0x00,0x43,
++    0x07,0x09,0xB8,0xFF,0xF8,0x1F,0x0B,0x11,0xC7,0x3C,0xB8,0xFF,0xF8,0x5F,0x23,0xA1,
++    0x01,0x01,0x40,0x4B,0x30,0x48,0xA8,0x16,0xE7,0x20,0x93,0x25,0x03,0x0F,0xF0,0x20,
++    0x92,0x25,0xE7,0x00,0x90,0x05,0x46,0x51,0x98,0x9E,0x0F,0x09,0xC7,0x3C,0xB8,0xFF,
++    0xF8,0xCF,0x42,0x82,0xC8,0x34,0x00,0x0B,0xC8,0x2C,0x18,0x0B,0xCA,0x24,0x18,0x0B,
++    0xCC,0x1C,0x18,0x0B,0x10,0x33,0x4E,0x62,0xD2,0x14,0x00,0x53,0x00,0x7B,0xC8,0x0C,
++    0x00,0x0B,0x4A,0x42,0xC2,0x04,0x88,0x01,0x10,0x43,0x60,0xA1,0xC8,0x16,0x00,0x09,
++    0x87,0x45,0xE8,0x85,0x07,0x01,0x38,0xDF,0x00,0xD0,0x00,0x01,0x80,0x00,0x00,0x42,
++    0x08,0x01,0x00,0x42,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0x00,0x0F,0x00,0x26,
++    0xF8,0x48,0x48,0x21,0x94,0xDE,0x3F,0x58,0xA8,0x0E,0x00,0x14,0xE6,0x00,0x3C,0x48,
++    0x80,0x06,0x80,0x13,0x38,0x82,0x4B,0x01,0x86,0x5E,0x38,0x18,0x80,0x16,0x80,0x13,
++    0xE2,0x00,0xF2,0x48,0x48,0x11,0x98,0x26,0x38,0x18,0xAC,0x16,0x04,0x14,0xE0,0x00,
++    0xF7,0x48,0x3C,0x1F,0x17,0x01,0x38,0x77,0x16,0x01,0x38,0xFF,0x10,0x01,0x48,0x18,
++    0x11,0x5A,0x9C,0x66,0x54,0x18,0x10,0x5A,0x98,0x8E,0x18,0x01,0x32,0xE2,0x04,0x77,
++    0x30,0x1A,0x18,0x5A,0xA0,0xE6,0x11,0x01,0x44,0x18,0x12,0x5A,0x98,0x8E,0x49,0x18,
++    0x10,0x5A,0x9C,0xE6,0x54,0x18,0x10,0x5A,0x9C,0x0E,0x30,0xA2,0x06,0xFF,0x49,0x18,
++    0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD6,0x00,0x0C,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,
++    0x0E,0x58,0xD4,0x00,0x0A,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD2,0x00,
++    0x08,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD0,0x00,0x0E,0x92,0x42,0x18,
++    0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD6,0x00,0x0C,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,
++    0x06,0x58,0xD4,0x00,0x0A,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD2,0x00,
++    0x0A,0x92,0xD2,0x08,0x90,0x06,0x30,0x0A,0x08,0x92,0x32,0x82,0x3A,0x82,0x03,0xEF,
++    0x78,0x50,0x86,0x06,0x10,0x4A,0x82,0x18,0x9A,0x06,0x10,0x02,0x00,0x9A,0x12,0x01,
++    0x30,0xE2,0x4C,0x18,0x11,0x5A,0x9C,0x6E,0x54,0x18,0x10,0x5A,0x9F,0x96,0x10,0xE1,
++    0x08,0x48,0xD4,0x95,0x54,0x18,0x10,0x5A,0x9C,0x66,0x08,0x48,0x8C,0x90,0x14,0x5A,
++    0x9C,0x46,0x08,0x48,0x8C,0x90,0x14,0x5A,0x9C,0x26,0x08,0x48,0x84,0xD6,0x89,0x90,
++    0x04,0x07,0x48,0x48,0x4C,0x18,0x16,0x5A,0x9E,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,
++    0x4C,0x18,0x14,0x5A,0x9C,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,0x4C,0x18,0x12,0x5A,
++    0x9A,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,0x4C,0x18,0x10,0x5A,0x98,0x0E,0x08,0x58,
++    0xD2,0x00,0x0E,0x92,0x44,0x18,0x16,0x5A,0x9E,0x0E,0x00,0x58,0xD2,0x00,0x0E,0x92,
++    0x44,0x18,0x14,0x5A,0x9C,0x0E,0x00,0x58,0xD2,0x00,0x0E,0x92,0x92,0xCE,0x46,0x18,
++    0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD2,0x00,0x0A,0x92,0xD2,0x08,0x90,0x06,0x30,0x0A,
++    0x32,0x1A,0x0B,0x92,0x80,0xD8,0x32,0x82,0x9A,0x0E,0x10,0x02,0x58,0x01,0xA8,0x06,
++    0x13,0x4A,0x3A,0x82,0x32,0x1A,0x83,0xD8,0x9A,0x06,0x10,0x02,0xA8,0x0D,0x00,0x01,
++    0x36,0x02,0x36,0x02,0xEB,0x15,0x30,0xAA,0x81,0x07,0xC0,0x17,0x30,0x72,0x05,0x28,
++    0x32,0x4A,0x33,0x9A,0x46,0x00,0x06,0x00,0x30,0x2A,0x84,0xC5,0xAF,0x05,0xB9,0xE7,
++    0xF3,0x6F,0xE4,0x05,0x3A,0x01,0x40,0x48,0x30,0xB2,0x35,0x01,0x2E,0x06,0x2E,0x06,
++    0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0xEA,0x01,0x02,0x48,
++    0x33,0x6A,0x3C,0x82,0x36,0x22,0x30,0x02,0x31,0x02,0x36,0x02,0xBA,0xDF,0xD7,0x5F,
++    0x43,0x02,0x38,0x82,0x88,0x20,0x00,0x01,0x40,0x12,0x48,0x1A,0xF3,0x5D,0x3D,0x82,
++    0x00,0x68,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x30,0x01,0x10,0x39,0x82,0xA3,0x85,
++    0x33,0xA2,0xF3,0x20,0xC3,0x2B,0xE1,0x20,0x10,0x5A,0x95,0x06,0x33,0xEA,0xE8,0x1A,
++    0x07,0xD8,0xC2,0x18,0xE0,0x85,0x39,0xC2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x80,0x20,0x03,0x42,0x80,0x20,0x03,0x42,0x80,0x20,0x04,0x42,
++    0x80,0x20,0x03,0x42,0x80,0xA0,0x04,0x42,0x80,0xA0,0x02,0x42,0x80,0xA0,0x04,0x42,
++    0x80,0xA0,0x02,0x42,0x80,0xA0,0x04,0x42,0x80,0xA0,0x02,0x42,0x80,0x20,0x05,0x42,
++    0x80,0xA0,0x02,0x42,0x80,0xA0,0x05,0x42,0x80,0x20,0x02,0x42,0x80,0x20,0x01,0x42,
++    0x80,0x20,0x01,0x42,0x80,0xA0,0x01,0x42,0x80,0xA0,0x01,0x42,0x80,0xA0,0x01,0x42,
++    0x10,0x20,0x08,0x40,0x40,0x08,0x20,0x10,0x10,0x20,0x08,0x40,0x40,0x08,0x20,0x40,
++    0x10,0x20,0x00,0x08,0x08,0xC1,0x02,0x42,0x08,0x81,0x02,0x42,0x08,0x81,0x03,0x42,
++    0x08,0x41,0x03,0x42,0x08,0x01,0x03,0x42,0x08,0x81,0x02,0x42,0x08,0x41,0x02,0x42,
++    0x08,0xC1,0x00,0x42,0x08,0x01,0x02,0x42,0x08,0x01,0x01,0x42,0x08,0xC1,0x01,0x42,
++    0x08,0x41,0x01,0x42,0x08,0x81,0x01,0x42,0x08,0x81,0x01,0x42,0x08,0x41,0x01,0x42,
++    0x08,0xC1,0x02,0x42,0x08,0x01,0x01,0x42,0x08,0x01,0x03,0x42,0x08,0xC1,0x00,0x42,
++    0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x00,0x00,
++    0x00,0x08,0xF8,0x0F,0xFF,0x07,0xF8,0xFF,0x07,0xF8,0x0F,0xF8,0x08,0x00,0x08,0x08,
++    0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x28,0xB5,0x39,0xC5,0x08,0x1D,
++    0x1B,0x2B,0x3A,0x28,0x53,0xB5,0x0A,0xC5,0x00,0x08,0x01,0x00,0x01,0x00,0x50,0x0D,
++    0x52,0x1D,0x52,0xB5,0x39,0x0D,0x04,0x08,0x51,0x3D,0x53,0x1D,0x51,0x3D,0x54,0x95,
++    0x51,0x3D,0x54,0x95,0x51,0x3D,0x54,0x95,0x0B,0x3D,0x34,0x88,0x51,0x3D,0x54,0x1D,
++    0x51,0x3D,0x54,0x95,0x04,0x00,0x50,0x3D,0x50,0x1D,0x01,0x00,0x00,0x00,0x00,0x00,
++    0x54,0x2D,0x53,0x3D,0x32,0x8D,0x32,0x38,0x01,0x28,0x0A,0x45,0x50,0xB5,0x53,0x95,
++    0x00,0x00,0x00,0x00,0x52,0xA5,0x51,0xB5,0x09,0xC5,0x03,0x08,0x03,0x00,0x50,0x3D,
++    0x55,0x1D,0x51,0x0D,0x51,0x3D,0x54,0x95,0x51,0x3D,0x53,0x1D,0x51,0x3D,0x54,0x95,
++    0x51,0x0D,0x55,0x0D,0x54,0xB5,0x3A,0x0D,0x00,0x08,0x01,0x00,0x53,0xA5,0x51,0x2D,
++    0x52,0x3D,0x34,0x8A,0x1D,0x38,0x52,0x45,0x52,0x0D,0x51,0x1D,0x54,0xB5,0x3A,0x0D,
++    0x53,0xA5,0x29,0xB5,0x39,0xC5,0x08,0x1D,0x19,0x2D,0x22,0x1D,0x44,0x0D,0x31,0x3D,
++    0x23,0x95,0x09,0xC1,0x29,0xB5,0x0B,0x1D,0x1B,0x2B,0x3A,0x28,0x00,0x00,0x00,0x08,
++    0xFF,0x07,0x00,0xF8,0x08,0x00,0x10,0x10,0x08,0x10,0x10,0x10,0x08,0x08,0x10,0x08,
++    0x10,0x08,0x10,0x08,0x10,0x10,0x08,0x08,0x10,0x10,0x08,0x08,0x08,0x08,0x10,0x10,
++    0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x08,
++    0xF8,0x07,0x08,0x00,0x08,0x08,0x00,0x00,0x78,0x42,0x00,0x00,0x00,0x00,0x00,0x01,
++    0x00,0xE0,0x00,0x00,0x00,0x00,0x05,0x00,0x78,0x22,0x01,0x00,0x00,0xE0,0x00,0x01,
++    0x88,0x40,0x02,0x00,0x00,0xE0,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xD1,0xDA,0xAA,0xA9,0x2E,0x2D,0x55,0x56,0xBB,0x43,0xAC,0x32,
++    0x99,0x21,0x8A,0x10,0x00,0x70,0x00,0x28,0x09,0x00,0x1F,0x00,0x06,0x78,0x50,0x56,
++    0xFF,0xFF,0xFF,0xFF,0xB2,0x30,0x08,0x40,0x00,0x40,0x20,0x00,0x03,0x13,0x2A,0xC7,
++    0x0F,0x00,0xCA,0xCA,0xFF,0xFF,0xFF,0xFF,0x06,0x16,0x48,0x01,0x08,0x00,0x00,0x04,
++    0x42,0x60,0x78,0xE5,0xD8,0xB9,0xCC,0x04
++};
++
++
++#define FW_INFO_SIZE	(0x18)
++#define FW_REAL_SIZE	(sizeof(fwbin))
++#define FW_BIN_SIZE		(24*1024+24)	    //24K byte
++
++#endif
++
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Debug_driver/ref_cst3xx_MCU_driver_0729_update2/hyn_cst3xx_RS659_fw_0729_update3.h b/module_drivers/drivers/input/touchscreen/hyn_touch/Debug_driver/ref_cst3xx_MCU_driver_0729_update2/hyn_cst3xx_RS659_fw_0729_update3.h
+new file mode 100644
+index 000000000..636d31078
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Debug_driver/ref_cst3xx_MCU_driver_0729_update2/hyn_cst3xx_RS659_fw_0729_update3.h
+@@ -0,0 +1,1552 @@
++
++#ifndef __CST3xx_FW_H__
++#define __CST3xx_FW_H__
++
++  unsigned char cst3_fw[] ={
++    0x98,0xE0,0x07,0x01,0xC8,0x08,0x01,0x00,0x00,0x00,0x00,0x00,0xC8,0xC8,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x90,0x08,0x07,0x00,0x98,0x08,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x98,0xA8,0x00,0x00,0x00,0x00,0x00,0x00,0x98,0x78,0x01,0x00,0x80,0x07,0xC0,0x17,
++    0x82,0x07,0xC0,0x07,0x01,0x65,0x40,0x86,0xC1,0x41,0xC0,0x20,0xC5,0x68,0x31,0x12,
++    0xF5,0x38,0x33,0x5A,0x32,0xA2,0x32,0xEA,0x10,0x62,0x8D,0x0E,0x81,0x07,0xC0,0x97,
++    0x30,0xF2,0xF3,0x79,0x65,0x7E,0x30,0xB2,0x31,0x09,0x10,0x9A,0x87,0x06,0xD0,0xD8,
++    0x35,0x12,0x35,0x5A,0x18,0x9A,0x39,0xC2,0x70,0x62,0x01,0x00,0x70,0x62,0x02,0x00,
++    0xD0,0x81,0x98,0x16,0x43,0xC6,0x0B,0xC6,0xC2,0xD6,0x3F,0x90,0x99,0x0E,0x40,0x86,
++    0x08,0x86,0xA9,0x0E,0x40,0x23,0x00,0x63,0x38,0x82,0x03,0x00,0x18,0x01,0x20,0x01,
++    0x28,0x01,0x30,0x01,0xD0,0x81,0x98,0x0E,0x0F,0xC6,0xC3,0xDE,0x38,0x90,0x9A,0x06,
++    0x08,0x86,0xA9,0x06,0x03,0x5B,0x38,0x82,0xAE,0xFD,0x30,0x02,0x30,0x02,0xEE,0xFD,
++    0xA8,0x85,0xE8,0x85,0x84,0x27,0xE8,0x2F,0x37,0x8A,0xB8,0xFF,0xF8,0xAF,0x87,0x0F,
++    0xD0,0x6F,0x80,0x27,0xEF,0xEF,0xBC,0xFF,0xF8,0x9F,0x87,0x27,0xE8,0x1F,0x05,0x00,
++    0xAF,0x85,0x6F,0xFA,0x39,0x01,0xC0,0x43,0x37,0x4A,0xC9,0x01,0x38,0x30,0x32,0x42,
++    0x86,0x01,0xC5,0x1B,0xCE,0x23,0xF0,0x53,0xC0,0x01,0x74,0x01,0xDD,0x16,0xC0,0x6B,
++    0x48,0x68,0x87,0x3E,0xAA,0x7B,0xAC,0x3B,0x10,0xD2,0x8C,0x16,0xB0,0x63,0x06,0x09,
++    0xB7,0x43,0xEC,0x85,0x34,0x6A,0xE8,0x4B,0xE6,0x48,0x92,0x4D,0xAF,0x4B,0x4D,0xF9,
++    0x8D,0x0E,0x10,0x12,0x82,0x16,0xE8,0x0B,0x48,0x09,0x88,0x1E,0xB5,0x5B,0xAF,0x7B,
++    0xAF,0x3B,0xEA,0x85,0x4F,0x09,0x8C,0xE6,0x0A,0x09,0xA8,0x0B,0xE8,0x85,0xAF,0x85,
++    0x67,0x3A,0xE7,0x01,0x00,0x0F,0x80,0x0F,0xED,0x8F,0xF7,0x03,0x47,0x01,0x80,0xD6,
++    0xEF,0x85,0xA8,0xC5,0x00,0x21,0x80,0x0F,0xE8,0xDF,0x06,0x09,0x86,0x0F,0xE8,0xC7,
++    0x79,0x02,0x47,0xC3,0x0C,0x01,0x19,0x42,0x00,0xC3,0x01,0x11,0x86,0x0F,0xE8,0x2F,
++    0x61,0xEA,0x56,0x03,0x29,0x41,0x18,0x42,0x17,0x03,0x49,0x03,0x1F,0x42,0x09,0x03,
++    0x15,0x2B,0x4B,0x03,0x1D,0x42,0x09,0x03,0x4D,0x03,0x1B,0x42,0x0B,0x03,0x4B,0x03,
++    0x35,0x21,0x18,0x82,0x0B,0x03,0x4B,0x03,0x42,0x00,0x02,0x00,0x09,0x03,0x4B,0x03,
++    0x19,0x42,0x09,0x03,0x49,0x03,0x19,0x82,0x09,0x03,0x49,0x03,0x08,0x09,0x18,0x42,
++    0x0F,0x03,0x41,0x03,0x1F,0x42,0x05,0x03,0x45,0x03,0x1F,0x82,0x07,0x03,0x47,0x03,
++    0x1F,0x42,0x04,0x03,0x45,0x03,0x1D,0x42,0x05,0x03,0x45,0x03,0x1D,0x82,0x05,0x03,
++    0x45,0x03,0x1B,0x42,0x03,0x03,0x43,0x03,0x1B,0x82,0x05,0x03,0x44,0x03,0x1D,0x42,
++    0x03,0x03,0x45,0x03,0x1B,0x42,0x04,0x03,0x0E,0x81,0x42,0x02,0x82,0x27,0xE0,0x07,
++    0x84,0x0F,0xE8,0xF7,0x84,0x0F,0xE8,0xD7,0x85,0x0F,0xE8,0x07,0x48,0xE2,0x05,0x01,
++    0x1D,0x43,0x4C,0x03,0x1D,0x42,0x0D,0x03,0x10,0x2B,0x03,0x11,0x84,0x0F,0xE8,0x07,
++    0x41,0xC3,0x09,0x01,0x19,0x42,0x00,0xC3,0x00,0x21,0x80,0x0F,0xE8,0x77,0x03,0x09,
++    0x83,0x0F,0xE8,0x5F,0x42,0x03,0x41,0x00,0x01,0x00,0x02,0x03,0x40,0x03,0x0F,0x09,
++    0x1F,0x42,0x00,0x03,0x4C,0x03,0x1B,0x42,0x09,0x03,0x4B,0x03,0x19,0x42,0x0C,0x03,
++    0x41,0x03,0x1D,0x42,0x05,0x03,0x45,0x03,0x1D,0x82,0x01,0x03,0x41,0x03,0x1B,0x42,
++    0x03,0x03,0x43,0x03,0x1B,0x82,0x01,0x03,0x48,0x0B,0x03,0x61,0x1B,0x0A,0x08,0x0B,
++    0x48,0x0B,0x19,0x0A,0x0F,0x0B,0x41,0x0B,0x1F,0x0A,0x00,0x0B,0x48,0xE2,0x04,0x09,
++    0xC8,0x01,0xAF,0x43,0x82,0x0F,0xD0,0x47,0xEC,0xC5,0x47,0xCA,0xC6,0x01,0xF3,0x0B,
++    0x42,0xCA,0x84,0x01,0x48,0x01,0x80,0x3E,0x4A,0xD2,0x04,0x0B,0x0C,0xF9,0x57,0xB2,
++    0x8C,0x89,0x97,0x01,0x10,0x8B,0x00,0x17,0x48,0xB2,0xCC,0xE1,0x07,0x0B,0x12,0xF9,
++    0x96,0xA1,0x02,0x13,0x08,0x31,0x08,0x0B,0x0C,0x11,0x08,0x0B,0x0A,0x51,0x08,0x0B,
++    0x0C,0x49,0x18,0x0B,0x18,0x0B,0x0A,0x01,0x1C,0x0B,0x40,0x4A,0xC2,0x01,0x0F,0x14,
++    0x3F,0x82,0xAB,0x85,0x70,0x62,0x0C,0x01,0x2C,0x01,0x60,0x62,0x50,0x62,0x04,0x01,
++    0xA4,0x82,0x02,0x40,0x50,0x5A,0xC4,0x40,0xC4,0x00,0x54,0x5A,0xC0,0x10,0x1C,0x01,
++    0xC6,0x83,0x01,0x38,0xC1,0x83,0xD0,0xC0,0x94,0x05,0x14,0x2A,0x90,0x06,0x30,0x2A,
++    0x10,0x22,0xCC,0x06,0x32,0x22,0xE0,0x90,0xE6,0xD8,0x92,0xDD,0x5F,0x29,0x98,0x8E,
++    0x59,0xFA,0xDB,0x40,0xA3,0xC2,0xE2,0xB0,0xE6,0x48,0x92,0x4D,0x4E,0x71,0x98,0xDE,
++    0x48,0xD2,0x03,0x01,0xE4,0xD2,0x10,0x52,0x90,0x06,0x30,0x8A,0xE6,0x00,0x92,0x05,
++    0x47,0x71,0x98,0xBE,0x50,0xCA,0x03,0x01,0x00,0x84,0xE0,0xE2,0x43,0xAC,0xD0,0x20,
++    0xC8,0x20,0x03,0xA4,0xE6,0x00,0x92,0x05,0x47,0x71,0x98,0xB6,0x47,0x84,0x40,0xF9,
++    0xCF,0x0E,0x00,0xF9,0x03,0x84,0x48,0x92,0x40,0x84,0x80,0x43,0xE8,0x85,0xAF,0x85,
++    0x40,0x1A,0xC3,0x03,0x38,0x00,0x86,0xAE,0x00,0x01,0x85,0x0F,0xCB,0xEF,0x67,0x02,
++    0x01,0x01,0xE0,0x01,0x8F,0x03,0xB9,0xFF,0xF9,0x47,0x34,0x0A,0x56,0x4A,0xCB,0x01,
++    0x40,0x22,0x83,0x1F,0xD0,0xAF,0x03,0x11,0x88,0x03,0x01,0x01,0x86,0x0F,0xC8,0x27,
++    0xBC,0xFF,0xFF,0xFF,0xE8,0x85,0xA8,0x85,0x41,0xAA,0xC2,0x01,0xC8,0x03,0x42,0x01,
++    0x8A,0x36,0x40,0x9A,0xC0,0x01,0xEF,0x03,0x40,0x29,0xC8,0x0E,0xBE,0xFF,0xF7,0x7F,
++    0x61,0x7A,0xC2,0x03,0x38,0x00,0xA8,0x0E,0xBE,0xFF,0xF7,0x9F,0xC3,0x03,0xC3,0x03,
++    0x08,0xE9,0x07,0x42,0x82,0x03,0x43,0xC2,0xC0,0x03,0x40,0x01,0x80,0x16,0x80,0x0F,
++    0xE7,0xAF,0x3D,0xE7,0xE8,0x85,0xA8,0x85,0x48,0x32,0x02,0x01,0x02,0x43,0x4C,0x22,
++    0xCC,0x01,0xB7,0x43,0xF0,0x43,0x86,0x0F,0xC8,0xFF,0xED,0x85,0xA8,0x85,0x33,0x2A,
++    0x48,0x01,0x80,0x4E,0x68,0x01,0x80,0x1E,0x30,0x82,0xC0,0x51,0x20,0x01,0x00,0x5F,
++    0x30,0x82,0x80,0x51,0x20,0x01,0x00,0x3F,0x68,0x01,0x80,0x1E,0xF0,0x80,0x24,0x49,
++    0x18,0x22,0x07,0x0F,0xE0,0x80,0x24,0x51,0x0A,0x01,0xF0,0x0A,0x48,0x01,0xD0,0x06,
++    0x16,0x4A,0x0A,0x40,0x0A,0x01,0xF0,0x8A,0x81,0x27,0xD8,0xC7,0x40,0xF9,0xEB,0x06,
++    0x00,0xF9,0x6B,0x01,0x87,0x16,0x08,0xF9,0x88,0x09,0xD0,0x40,0xCB,0x00,0xE8,0x85,
++    0xAC,0x85,0x87,0x3D,0x28,0x01,0x20,0x01,0x01,0x51,0x48,0x92,0x1A,0x42,0xC3,0x00,
++    0x80,0x34,0xC0,0x34,0x01,0x08,0x13,0x39,0xC4,0x00,0x0A,0x90,0xC0,0x10,0x04,0xE1,
++    0x90,0x2C,0xF0,0x82,0x80,0x24,0x30,0x01,0x38,0x01,0x10,0x01,0x90,0x1C,0x90,0x14,
++    0x60,0x01,0x80,0x46,0xF0,0x10,0xDB,0x34,0x04,0x90,0xC2,0xD0,0x1C,0x39,0x09,0xD8,
++    0xC0,0x90,0x36,0xE1,0xF8,0xB2,0x6C,0x01,0x83,0x56,0xF0,0x50,0x1A,0x51,0x18,0xD2,
++    0x5E,0x02,0xC1,0x90,0x1A,0x39,0xC1,0x90,0x0E,0xD8,0xC4,0x90,0x3E,0xE1,0xF8,0xBA,
++    0x60,0x21,0x80,0x4E,0xE0,0x18,0xD3,0x34,0x06,0xD8,0xC2,0x90,0x1C,0x39,0x09,0xD8,
++    0xC0,0x90,0x1E,0xE1,0xF0,0x9A,0x9E,0x1C,0x68,0x69,0x80,0x5E,0xE0,0x50,0x1B,0x51,
++    0x18,0xD2,0x5A,0xA2,0xC2,0x90,0xC6,0x88,0x14,0x39,0x09,0x90,0xC0,0x50,0x0C,0xE1,
++    0xF0,0x8A,0x8A,0x14,0x08,0x09,0x88,0x0C,0x70,0x41,0xD1,0x3E,0x78,0x41,0xD1,0x2E,
++    0xC9,0x1C,0x48,0x41,0xD0,0x16,0xC8,0x14,0x49,0x41,0xD9,0x06,0x08,0x01,0x00,0xEF,
++    0x00,0xE0,0x07,0x01,0x10,0x00,0x00,0x42,0xF8,0x00,0x06,0x42,0x80,0x30,0x02,0x01,
++    0x18,0x00,0x02,0x42,0x80,0x60,0x05,0x00,0x70,0x00,0x04,0x01,0xF8,0xFF,0x07,0x00,
++    0x80,0x50,0x06,0x01,0x08,0x40,0x00,0x01,0x60,0x20,0x02,0x00,0x00,0x60,0x00,0x01,
++    0x00,0x28,0x00,0x01,0x80,0xC0,0x04,0x01,0x00,0x20,0x00,0x01,0x88,0x0C,0x08,0x19,
++    0x85,0x27,0xD0,0xA7,0x10,0x82,0xED,0x3E,0x10,0xC2,0xED,0x2E,0xCC,0x1C,0x10,0x42,
++    0xE8,0x16,0xC8,0x14,0x10,0x42,0xE4,0x0E,0x00,0x01,0x80,0x0C,0xC0,0x0C,0x40,0x01,
++    0x80,0x86,0xC8,0x24,0xD6,0x2C,0x78,0x40,0xC2,0x00,0x82,0x00,0xD0,0x48,0x90,0x4D,
++    0x1F,0x8C,0x54,0xFA,0x58,0xFA,0xC7,0x93,0xC0,0xDB,0x18,0xD2,0x80,0x16,0xD0,0x40,
++    0xCC,0x2C,0x18,0x44,0xE7,0x20,0x93,0x25,0x60,0x29,0x90,0x06,0x3B,0x4F,0xE3,0x68,
++    0x90,0x6D,0x6F,0x71,0x92,0x06,0x38,0xF7,0x87,0x3D,0xE8,0x85,0xA8,0xC5,0x2F,0x01,
++    0x40,0xAA,0xFF,0x03,0x81,0x04,0x00,0x5F,0x07,0x31,0x48,0xA2,0x1A,0x42,0xC3,0x00,
++    0x0C,0xC9,0x09,0x48,0xC0,0x30,0x3A,0x11,0xF8,0xBA,0x07,0x21,0xF0,0x82,0x41,0x51,
++    0xD0,0x0E,0x20,0x51,0x00,0x0F,0xC0,0x51,0x96,0x25,0x00,0x19,0x04,0x00,0x14,0x22,
++    0xE8,0x06,0x30,0x22,0x37,0x02,0xC1,0xF9,0xC0,0x89,0x0C,0xF1,0x1F,0x42,0x0A,0xF9,
++    0x88,0x89,0x84,0x27,0xD0,0x1F,0xCB,0x00,0x90,0x05,0x40,0x51,0xD0,0x06,0x00,0x51,
++    0x4C,0x1A,0x17,0x42,0xE8,0x06,0x30,0x42,0x05,0xBC,0x03,0x84,0xE7,0x68,0x93,0x6D,
++    0xC5,0x04,0x10,0x42,0xC7,0x86,0xEE,0xC5,0xAC,0x85,0x87,0x3D,0x00,0xF9,0x87,0x0C,
++    0x00,0x01,0x80,0x04,0x81,0x14,0x18,0x39,0x09,0xD8,0x24,0x39,0x57,0xBA,0x1E,0x22,
++    0x04,0x08,0xC2,0x48,0xC0,0x68,0x0E,0xE1,0xF2,0x4A,0xE3,0x00,0x92,0x05,0x40,0x31,
++    0xD8,0xB6,0x07,0x01,0x80,0x24,0x00,0x01,0x38,0x01,0x28,0x01,0x30,0xF9,0xCF,0x24,
++    0x12,0x51,0x18,0x8A,0x54,0x6A,0xC6,0x48,0x54,0x72,0xC6,0x50,0x90,0x34,0x08,0x01,
++    0x20,0x01,0xF8,0xA2,0x60,0xA1,0xE8,0x0E,0xE1,0xF8,0x93,0xFD,0xC0,0x00,0x91,0x05,
++    0x10,0x62,0xED,0x06,0x35,0x2A,0x11,0xA2,0xD1,0x06,0x30,0x32,0xE2,0x90,0xE4,0x48,
++    0x90,0x4D,0x4E,0x29,0x99,0x66,0x6F,0xE1,0xED,0x16,0x50,0xFA,0x0C,0x01,0xA8,0x8B,
++    0x08,0x29,0x80,0x27,0xD0,0x9F,0x90,0x0D,0xD0,0x40,0x83,0x71,0x40,0xE1,0xC0,0x6E,
++    0xD0,0x80,0x83,0x71,0x40,0xE1,0xC0,0x4E,0x68,0xE1,0xE9,0x3E,0x78,0x21,0xE8,0x2E,
++    0x50,0xA2,0x05,0x01,0x85,0x83,0x40,0x92,0x10,0xD1,0x87,0x13,0xC4,0x14,0x10,0x42,
++    0xD0,0x06,0x88,0x14,0xC5,0x0C,0x10,0x82,0xE8,0x06,0xB0,0x0C,0xC5,0x04,0x10,0x42,
++    0xD0,0x06,0xA8,0x04,0x6D,0x6A,0x75,0x7A,0xC0,0x34,0x18,0x01,0x48,0x01,0xE8,0xBE,
++    0x14,0x01,0xF0,0x12,0x10,0x52,0xDC,0x76,0x61,0x2A,0xC5,0x23,0x60,0x01,0x80,0x16,
++    0xD0,0x90,0x02,0x14,0x01,0xC7,0x50,0xE1,0xD6,0xB6,0x78,0x60,0xC3,0x20,0x83,0x20,
++    0xD8,0x90,0x00,0x14,0x00,0x87,0x50,0x01,0xE8,0x76,0x10,0x09,0x00,0x14,0x00,0x5F,
++    0x14,0x01,0xF0,0x12,0x10,0x52,0xE4,0x16,0xD0,0x90,0x02,0x14,0x00,0x27,0x50,0x01,
++    0xD0,0x16,0x10,0x01,0x18,0x92,0x06,0x14,0xE2,0x00,0xE4,0xD8,0x90,0xDD,0x5E,0x29,
++    0x98,0xA6,0xC6,0x24,0xE6,0x00,0x92,0x05,0x80,0x24,0xC0,0x24,0x44,0x71,0x98,0x16,
++    0x20,0x01,0x00,0x01,0x08,0x01,0x10,0x01,0x94,0x1C,0x50,0x82,0x04,0x18,0xC3,0xD0,
++    0x5E,0x82,0xC4,0xA8,0x30,0x72,0x19,0x01,0x15,0x01,0xF0,0x52,0xC0,0x80,0x90,0x05,
++    0xE0,0x48,0x92,0x4D,0xFD,0x1C,0x10,0xD2,0xE8,0x06,0x90,0x1C,0xAA,0x51,0xE0,0xD8,
++    0x90,0xDD,0x5E,0x71,0x98,0x86,0x87,0x27,0xC8,0x0F,0x95,0x2D,0xC5,0x14,0x10,0x42,
++    0xD0,0x06,0xA8,0x14,0x00,0x01,0x80,0x24,0x68,0x01,0xE8,0xDE,0x3F,0x01,0xF8,0xBA,
++    0x10,0x7A,0xDD,0x96,0x60,0x01,0x80,0x0E,0x60,0x21,0x88,0x16,0xD9,0xC0,0x03,0x84,
++    0x00,0xB7,0x08,0x19,0xC0,0x1C,0x80,0x27,0xCD,0x4F,0x14,0x42,0xD7,0x86,0x78,0x40,
++    0xCA,0x00,0x82,0x00,0xD1,0xC0,0x01,0x84,0x00,0x57,0x78,0x01,0xE8,0x46,0x00,0x09,
++    0x00,0x84,0x01,0x2F,0x01,0x01,0xF0,0x82,0x10,0x42,0xE5,0x0E,0xD9,0x00,0x02,0x84,
++    0xB0,0x51,0xC0,0x24,0xE6,0x00,0x92,0x05,0x80,0x24,0xC0,0x24,0x46,0x71,0x98,0x9E,
++    0xE7,0x20,0x93,0x25,0x65,0x29,0x98,0x66,0x43,0x2A,0x4B,0x32,0xC0,0x03,0xC0,0x4B,
++    0x33,0x22,0x58,0x4A,0x50,0x4A,0x1B,0x62,0x88,0xB6,0x01,0x01,0x4A,0x1A,0x03,0x20,
++    0xC3,0x08,0x63,0x22,0xCB,0x60,0x68,0x1A,0xAA,0x51,0xC8,0x68,0x31,0xF9,0x0C,0xB0,
++    0xC8,0x78,0x34,0x01,0xF8,0xF2,0x3D,0x01,0xFD,0x7A,0x17,0xF2,0xD0,0x3E,0x28,0x01,
++    0xF8,0x2A,0x6B,0xA1,0xE8,0x1E,0x78,0x79,0xEB,0x0E,0x00,0x68,0x02,0x2C,0x61,0xD2,
++    0xA0,0x51,0xC8,0x60,0xC4,0x70,0xC6,0x68,0x0B,0x01,0xF0,0x4A,0x2B,0x01,0xF8,0xAA,
++    0x10,0x4A,0xD5,0x66,0x0B,0x01,0xF0,0x0A,0x48,0xA1,0xE8,0x46,0x68,0x79,0xE8,0x36,
++    0x7B,0x70,0xC6,0xA8,0x83,0x68,0x03,0x70,0xCB,0x68,0xC5,0x48,0x02,0x0C,0xE1,0x00,
++    0x90,0x05,0x46,0x29,0x9C,0x56,0x36,0xFF,0x47,0x01,0x80,0xE6,0x22,0x01,0x40,0x3A,
++    0x00,0x08,0xC3,0x68,0x41,0x3A,0xC2,0x70,0x40,0x32,0x82,0x51,0xC4,0x40,0x09,0xF9,
++    0x0B,0x48,0xC0,0x78,0x10,0x01,0x08,0x01,0xF2,0xD2,0xF5,0x0A,0x10,0x52,0xD4,0x6E,
++    0x01,0x01,0xF0,0x82,0x81,0x2C,0x40,0x41,0xE8,0x46,0x48,0x79,0xEC,0x36,0x00,0x00,
++    0x08,0x29,0x80,0x27,0xC8,0x5F,0xC8,0x2C,0xC1,0x00,0x02,0x84,0x40,0xD2,0x81,0x51,
++    0xC1,0x40,0x49,0xD2,0xC0,0x48,0x1B,0x01,0x17,0x01,0xF0,0xDA,0xF4,0x52,0x14,0x9A,
++    0xD0,0x3E,0x08,0x01,0xF1,0x0A,0x4A,0x41,0xE8,0x1E,0x50,0x79,0xEA,0x0E,0x00,0x48,
++    0x03,0x0C,0xE0,0x20,0x90,0x25,0x67,0x29,0x9B,0x4E,0x36,0x2F,0xA9,0xC5,0x47,0x52,
++    0x17,0x09,0x80,0x01,0xC0,0x0B,0x18,0x8A,0x81,0x0B,0x68,0x3A,0x79,0x22,0x31,0x62,
++    0xA4,0x01,0x06,0x27,0xBB,0xFF,0xEF,0xFF,0x48,0x4A,0x41,0x43,0xE0,0x00,0x02,0x43,
++    0x40,0x42,0xC1,0x03,0x40,0x01,0x80,0x0E,0x05,0xC1,0xB0,0x43,0x40,0xF2,0x80,0x1F,
++    0xE9,0x57,0x50,0x2A,0x48,0xEA,0x40,0xE2,0x85,0x1F,0xC8,0xAF,0xB9,0xFF,0xEF,0x7F,
++    0x01,0x11,0x88,0x03,0x50,0x02,0x49,0xC2,0x40,0xC2,0x80,0x1F,0xD8,0xA7,0x54,0xF2,
++    0x48,0xAA,0x40,0xB2,0x85,0x1F,0xF8,0x57,0xC8,0x03,0x43,0x01,0x83,0x16,0xC8,0x03,
++    0x40,0x11,0x88,0x26,0x48,0xCA,0x40,0x43,0x10,0x09,0x18,0x82,0x00,0x43,0x48,0x72,
++    0x40,0x72,0x80,0x1F,0xF0,0xB7,0x72,0x5A,0xC1,0xCB,0xC1,0x83,0x18,0x42,0x80,0x0E,
++    0x05,0x01,0xA8,0x43,0xBA,0xFF,0xF7,0xC7,0x41,0x8A,0xC0,0x8B,0x09,0x0C,0xC6,0xCB,
++    0x11,0x0C,0xC8,0x4B,0x10,0x0C,0x72,0x22,0xB5,0x01,0xE2,0x8B,0x10,0x0C,0x04,0xCF,
++    0x00,0x48,0x00,0x01,0x00,0x40,0x00,0x01,0x00,0xE0,0x00,0x01,0x08,0x40,0x00,0x01,
++    0x18,0x10,0x00,0x00,0x48,0xE0,0x06,0x00,0x50,0xA0,0x02,0x00,0x50,0x50,0x02,0x00,
++    0x00,0xA0,0x00,0x01,0x00,0x20,0x00,0x01,0x80,0xC0,0x04,0x01,0xF8,0x00,0x06,0x42,
++    0x70,0x40,0x04,0x01,0x48,0xA2,0x40,0x4C,0x10,0x0C,0x4E,0xA2,0x40,0x4B,0x18,0x0C,
++    0xA2,0x48,0x18,0x0C,0xEC,0x4B,0x1D,0x0C,0xBA,0xFF,0xEF,0x57,0x05,0x11,0xA0,0x83,
++    0x32,0x8A,0xC9,0x01,0x40,0x72,0x80,0x1F,0xE9,0x0F,0x31,0x8A,0x12,0x09,0xC8,0x01,
++    0x40,0x5A,0x58,0x62,0x80,0x17,0xE8,0x47,0xBC,0xFF,0xDF,0x97,0x32,0x8A,0xC9,0x01,
++    0x40,0x3A,0x80,0x0F,0xF0,0x4F,0x82,0x07,0xDF,0x0F,0xBA,0xFF,0xE3,0xE7,0xCE,0x03,
++    0x40,0x31,0x80,0x06,0x3F,0xB7,0xEB,0xC5,0x00,0x60,0x00,0x01,0x00,0xA0,0x00,0x01,
++    0x08,0x40,0x00,0x01,0x30,0x48,0x00,0x00,0xA8,0x85,0x33,0x22,0xF0,0x03,0x87,0x07,
++    0xF2,0x9F,0x45,0x7A,0x2C,0x01,0x00,0x2B,0xB6,0x2B,0x05,0x21,0xAF,0x2A,0xB8,0xFF,
++    0xE5,0xE7,0xA1,0x01,0xCA,0x03,0x33,0x08,0x42,0x52,0x72,0x48,0x1C,0x0B,0x5C,0x0B,
++    0x02,0x48,0x1A,0x0B,0x0B,0x2B,0xCE,0x0B,0x30,0x48,0xA8,0x16,0x0E,0x09,0x04,0x0B,
++    0x1B,0x2B,0xE8,0x85,0xAD,0x85,0x87,0xAD,0x42,0x12,0xC2,0x01,0x42,0x0B,0x40,0x48,
++    0x00,0x48,0x02,0x0B,0x52,0x02,0x4A,0x0A,0x40,0x0A,0x82,0x0F,0xCA,0x27,0x40,0x0A,
++    0x71,0xFA,0xC1,0x80,0x81,0xA4,0x41,0xEA,0xB6,0xE1,0x81,0x01,0x83,0x9C,0x01,0x47,
++    0x47,0xD2,0xB9,0xFF,0xF9,0x4F,0x66,0xCA,0x52,0x03,0x83,0x01,0xE7,0x03,0x40,0x79,
++    0x81,0x06,0x31,0x12,0x48,0xB2,0x01,0x01,0x58,0x9A,0x81,0x07,0xF9,0xCF,0x35,0x12,
++    0x48,0x9A,0x01,0x09,0x58,0x82,0x81,0x07,0xFB,0x9F,0x55,0x03,0x80,0x01,0xE2,0x03,
++    0x40,0x59,0x8D,0x7E,0xC1,0xA4,0x31,0x8A,0x13,0x01,0xD8,0x1B,0xDB,0x2B,0x19,0x5A,
++    0x40,0x6C,0x40,0x3C,0xD8,0x68,0x07,0x2C,0xE4,0x00,0xE4,0x48,0xE4,0x90,0x92,0x95,
++    0x17,0xD2,0x9C,0xAE,0x52,0x03,0x83,0x01,0xE5,0x03,0x40,0x59,0x81,0x2E,0x50,0x12,
++    0x49,0x12,0x41,0x1A,0x58,0x0D,0x80,0x0F,0xC1,0x77,0xEB,0xA4,0x30,0xA2,0x39,0x01,
++    0x01,0x01,0xF0,0x42,0x0A,0x99,0x18,0x42,0x08,0x51,0x80,0x1F,0xF9,0xFF,0x06,0x44,
++    0x01,0x01,0xF0,0x02,0x0A,0x99,0x18,0x42,0x08,0x51,0x80,0x1F,0xF9,0xBF,0x06,0x04,
++    0xE5,0x68,0xE5,0x20,0xE7,0xF8,0x93,0xFD,0x7F,0x29,0x98,0x4E,0x68,0xB2,0x60,0xA2,
++    0xA0,0xF1,0x3D,0x01,0x01,0x01,0xF0,0x42,0x08,0x51,0x08,0x00,0x86,0x1F,0xF8,0x37,
++    0x00,0x44,0x01,0x01,0xF0,0x02,0x09,0x51,0x08,0x00,0x80,0x1F,0xF9,0xFF,0x05,0x04,
++    0xE5,0x68,0xE5,0x20,0xE7,0xF8,0x93,0xFD,0x7F,0x29,0x98,0x5E,0x40,0x0D,0x80,0x07,
++    0xD9,0xDF,0xC1,0x9C,0xC8,0x03,0x42,0x31,0x81,0x96,0x84,0xAD,0xE8,0x85,0x07,0x00,
++    0x10,0x00,0x00,0x42,0x00,0x01,0x00,0x42,0x80,0xC0,0x04,0x01,0x00,0xE0,0x00,0x01,
++    0x08,0x40,0x00,0x01,0x48,0xE0,0x06,0x00,0x58,0x30,0x03,0x01,0x48,0xFA,0xFF,0x53,
++    0x84,0x13,0xF8,0x53,0x80,0x13,0x32,0x52,0x96,0x01,0xCE,0x93,0x80,0x13,0xCC,0x4B,
++    0x83,0x0B,0x3E,0x82,0xA8,0xC5,0xF7,0x34,0x37,0x22,0x40,0xC2,0xFD,0x03,0x16,0x02,
++    0xC9,0xFE,0x01,0x21,0x6B,0xB2,0x1F,0x02,0xCB,0x28,0x02,0x99,0x09,0x00,0xC2,0x40,
++    0x2A,0xA1,0xF8,0x2A,0x3E,0xB1,0xF8,0x3A,0x48,0x09,0x88,0x1E,0x0F,0xF9,0x8F,0x09,
++    0xD8,0x48,0x92,0x6D,0x50,0x09,0x88,0x1E,0x0A,0xC9,0x08,0x48,0xD8,0x48,0x96,0x7D,
++    0xCE,0x0B,0xCC,0x13,0x0A,0x48,0x00,0x90,0x18,0x8A,0x80,0xCB,0x8A,0x48,0x81,0xCB,
++    0x8C,0xC8,0x81,0xCB,0x39,0xD0,0x09,0x48,0x78,0x90,0x18,0x8A,0x86,0xCB,0xE6,0xD8,
++    0xE0,0xE8,0x5A,0x04,0x08,0xA1,0x80,0x1F,0xF8,0xBF,0x82,0x51,0x97,0x05,0x46,0xF9,
++    0x97,0x56,0x58,0x02,0xE8,0xCA,0x30,0x52,0x94,0x51,0x10,0x12,0x91,0x16,0x80,0x43,
++    0xA8,0xC2,0x00,0x1F,0x80,0x4B,0x01,0x0F,0x01,0xF9,0x87,0x43,0xC2,0x83,0xE9,0x00,
++    0x87,0x83,0xE9,0xC5,0xAC,0x85,0x87,0x2D,0x36,0x01,0x00,0xBD,0x40,0x03,0x80,0x14,
++    0x44,0x92,0xFE,0x1B,0x10,0x09,0x00,0x01,0x4E,0xA2,0x66,0xAA,0xC5,0x6B,0x68,0x59,
++    0x82,0x16,0xE0,0x00,0x17,0x02,0x9D,0xCE,0x00,0xF9,0x87,0x43,0x58,0x01,0x80,0xBE,
++    0x30,0x01,0x48,0x15,0x03,0x01,0x20,0x99,0x5B,0x4A,0x0E,0x20,0x01,0x77,0x28,0x21,
++    0x1F,0x2A,0xC2,0x68,0xC9,0x68,0xD1,0x6B,0x68,0x09,0x88,0x2E,0x83,0x43,0xE0,0xB0,
++    0x92,0xB5,0xE7,0x48,0x70,0x09,0x80,0x1E,0xE6,0x00,0x92,0x05,0x17,0x82,0x9C,0x76,
++    0x73,0x01,0x80,0x16,0x60,0x0A,0x6E,0x15,0x3D,0x01,0x40,0xE2,0x80,0x01,0x87,0x1C,
++    0x00,0x0F,0x79,0x01,0x88,0x9E,0x50,0x0D,0x90,0x04,0x10,0x01,0xC1,0x43,0x31,0x1A,
++    0x37,0x8A,0xB8,0xFF,0xFB,0xBF,0xE3,0x68,0xC4,0x1C,0xC0,0x03,0x4E,0x00,0x0E,0x00,
++    0x1B,0x82,0x89,0x03,0x05,0x59,0x8D,0x03,0xEB,0x20,0xE5,0x20,0x00,0x4F,0x50,0x0D,
++    0x90,0x04,0x10,0x01,0xC1,0x43,0x31,0x1A,0x37,0x8A,0xB8,0xFF,0xFB,0x1F,0xE3,0x68,
++    0xEB,0x20,0xE3,0xF8,0x95,0xFD,0x17,0xBA,0x98,0xDE,0xC6,0x1C,0x1C,0x01,0xC4,0x03,
++    0x48,0x08,0x4E,0x01,0x80,0x9E,0x70,0x01,0x81,0x3E,0x80,0x03,0xC0,0x1C,0xC8,0x03,
++    0x85,0x03,0x03,0x59,0x85,0x03,0xE5,0x20,0x01,0x3F,0x80,0x03,0xC0,0x1C,0xC8,0x03,
++    0x83,0x03,0x8B,0x1B,0x05,0x59,0x8D,0x03,0xEB,0x20,0xE5,0x20,0x00,0x27,0x70,0x09,
++    0xCD,0x16,0x00,0x59,0x83,0x03,0xE1,0x20,0x37,0x02,0xB9,0xFF,0xFC,0x7F,0x41,0xEA,
++    0x42,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,0x4A,0xDA,0x44,0x43,0x1A,0xC2,0x00,0x43,
++    0x61,0xD2,0x44,0x03,0x42,0x00,0x02,0x00,0x07,0x03,0x01,0xF9,0x80,0x89,0x84,0x1F,
++    0xE9,0xDF,0x45,0x03,0x08,0x09,0x18,0x42,0x00,0x03,0x81,0x2D,0xEF,0x85,0xAF,0xFD,
++    0x80,0x0D,0xFC,0x54,0x30,0x32,0x30,0x62,0x6F,0x42,0xAC,0x01,0x50,0x09,0x88,0x4E,
++    0x00,0x0F,0x80,0x07,0xF9,0xDF,0xC7,0x43,0x37,0x00,0xAA,0xD6,0xC5,0x43,0x09,0xF9,
++    0x01,0x42,0x80,0x43,0x04,0x09,0x30,0x22,0x51,0x3A,0x04,0x8F,0x60,0x01,0xC1,0x2E,
++    0xF7,0x00,0x0B,0x01,0x1A,0x42,0x08,0x83,0x30,0x0A,0x01,0x17,0x02,0xF9,0x0F,0x83,
++    0x08,0x01,0x19,0x01,0x08,0x9B,0x04,0x01,0x00,0x4F,0x78,0x01,0x88,0x16,0x18,0x01,
++    0x00,0x9B,0x06,0x17,0xC6,0x9B,0x01,0x9B,0xCA,0xB0,0xE7,0x00,0x94,0x05,0x14,0x42,
++    0x9B,0x9E,0x37,0x02,0x40,0x01,0x80,0x26,0x04,0xA1,0x00,0x83,0x04,0x01,0x30,0x22,
++    0x00,0x0F,0x00,0x21,0x03,0x83,0xD4,0x00,0x92,0x25,0x44,0x83,0x08,0x01,0x1C,0x42,
++    0x01,0x83,0xC2,0x43,0x37,0x00,0xAA,0xE6,0xC5,0x43,0x09,0xF9,0x01,0x42,0x80,0x43,
++    0x66,0x01,0x88,0x5E,0xC0,0x24,0x40,0x09,0x88,0x7E,0x05,0x01,0x02,0x83,0x44,0x83,
++    0x08,0x01,0x1C,0x42,0x05,0x83,0x3A,0x47,0xAC,0x9D,0x87,0x1D,0x20,0x01,0x00,0x01,
++    0x80,0x0C,0x70,0x15,0x44,0xEA,0xF2,0x03,0xEE,0x00,0x92,0x3D,0x6F,0xDA,0xAA,0x01,
++    0x00,0xAF,0x81,0x07,0xF9,0x1F,0xC5,0x43,0x30,0x00,0xA2,0x1E,0x44,0xBA,0xF2,0x03,
++    0x17,0xC2,0x9D,0xB6,0x44,0xAA,0xF2,0x03,0x10,0xC2,0x9D,0x06,0x21,0x11,0xC0,0x43,
++    0x08,0xF9,0x05,0x42,0x82,0x43,0x41,0xC2,0x46,0x0B,0x14,0x79,0x00,0x8A,0x48,0x09,
++    0x88,0x9E,0x08,0x01,0x0E,0x0B,0x44,0x0B,0x83,0x8B,0xE1,0xB0,0xE7,0x20,0x93,0x25,
++    0x60,0x11,0x88,0x56,0x30,0x5A,0xD3,0xCB,0xD4,0x1C,0x10,0x8A,0x8A,0x2E,0xD0,0xCB,
++    0xD4,0x24,0x10,0x8A,0x88,0x0E,0x08,0x09,0x8F,0x0C,0x08,0x01,0x08,0x0B,0x0A,0x01,
++    0x08,0x0B,0x0C,0x81,0x02,0x0B,0x44,0x0B,0x10,0x01,0x1C,0x8A,0x00,0x0B,0x62,0x11,
++    0x88,0x4E,0xC6,0x0C,0x39,0x0F,0x4B,0xEA,0x60,0x54,0x80,0x13,0x12,0x01,0x80,0x13,
++    0xE4,0x4B,0x86,0x0B,0x4A,0x0A,0x8A,0x01,0x5E,0x53,0x84,0x13,0x58,0x53,0x8A,0x13,
++    0x12,0xA9,0x88,0x13,0x14,0x19,0x88,0x13,0x4E,0x53,0x8E,0x13,0x48,0x53,0x94,0x13,
++    0x4A,0x4B,0x92,0x0B,0x0C,0x31,0x90,0x0B,0x3F,0x82,0xAB,0x85,0x80,0x4D,0x34,0x22,
++    0x30,0x01,0x00,0x01,0x80,0x2C,0x38,0x01,0x48,0x62,0xD9,0x43,0xDA,0x4B,0x1A,0x42,
++    0x81,0x14,0x40,0x5A,0x80,0x71,0x80,0x24,0xC0,0x71,0x80,0x1C,0x60,0x09,0x80,0x0E,
++    0x60,0x29,0x88,0x7E,0x60,0x09,0x88,0x26,0x73,0x6A,0xE1,0x80,0x81,0x2C,0x78,0x6A,
++    0x01,0x27,0x70,0x6A,0xE0,0x80,0x83,0x2C,0x79,0x52,0xF9,0xC1,0x47,0x35,0xB8,0xFF,
++    0xF0,0xEF,0x01,0x3F,0x60,0x21,0x88,0x2E,0x70,0x42,0x41,0x35,0xBD,0xFF,0xFF,0xDF,
++    0x7B,0x22,0xB9,0x11,0x6F,0xCA,0xA8,0x01,0xC5,0x43,0x09,0xF9,0x01,0x42,0x80,0x43,
++    0xC1,0x43,0x09,0x01,0x19,0x42,0x80,0x43,0x42,0xD2,0x40,0x0B,0x10,0x01,0x1A,0x8A,
++    0x00,0x0B,0x42,0xCA,0x44,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,0x48,0xBA,0x40,0x43,
++    0x10,0x09,0x18,0x82,0x00,0x43,0x08,0x09,0x07,0x01,0xBC,0xFF,0xF8,0xAF,0x42,0x09,
++    0x88,0x5E,0x62,0x21,0x88,0x56,0x12,0x09,0x91,0x04,0x30,0x82,0x18,0x01,0xC8,0x14,
++    0xBF,0xFF,0xF7,0xAF,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x59,0x40,0x35,0x30,0x9A,
++    0xBF,0xFF,0xF7,0x6F,0x10,0x09,0x90,0x04,0x10,0x01,0x00,0xCF,0x00,0xE0,0x00,0x01,
++    0x08,0x40,0x00,0x01,0x80,0x00,0x06,0x01,0x00,0xF8,0x07,0x00,0x80,0x30,0x02,0x01,
++    0x30,0x04,0x05,0x08,0x00,0x00,0x06,0x42,0x80,0x01,0x06,0x42,0xF8,0x00,0x06,0x42,
++    0x18,0x60,0x05,0x01,0x70,0x70,0x06,0x01,0x50,0x20,0x07,0x01,0x68,0x60,0x02,0x01,
++    0x09,0x29,0x30,0xC2,0x37,0x9A,0xB8,0xFF,0xF0,0x57,0x16,0x09,0x90,0x04,0x10,0x01,
++    0x0E,0x71,0x40,0x0A,0x37,0x9A,0xB8,0xFF,0xF0,0x17,0x16,0x09,0x90,0x04,0x10,0x01,
++    0x08,0x29,0x30,0x9A,0xC7,0x24,0xB8,0xFF,0xF0,0xD7,0x15,0x09,0x90,0x04,0x10,0x01,
++    0x08,0x29,0x18,0x09,0xC7,0x1C,0xB8,0xFF,0xF1,0x97,0x05,0x9F,0x60,0x09,0x80,0x0E,
++    0x61,0x29,0x88,0x7E,0x10,0x11,0x90,0x04,0x11,0x09,0x30,0x82,0x18,0x01,0xC8,0x14,
++    0xBD,0xFF,0xF7,0x2F,0x10,0x11,0x90,0x04,0x10,0x01,0x30,0x9A,0xC8,0x14,0xC0,0x2C,
++    0xBC,0xFF,0xF7,0xEF,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x21,0x40,0x35,0x30,0x9A,
++    0xBC,0xFF,0xF7,0xAF,0x10,0x09,0x90,0x04,0x11,0x01,0x08,0x31,0x30,0xC2,0x31,0x9A,
++    0xBC,0xFF,0xF7,0x6F,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x29,0x30,0x9A,0xC0,0x24,
++    0xBC,0xFF,0xF7,0x2F,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x29,0x18,0x09,0xC0,0x1C,
++    0xBB,0xFF,0xF7,0xEF,0xC6,0x43,0x09,0xF9,0x01,0x42,0x80,0x43,0x40,0xDA,0x44,0x0B,
++    0x42,0x48,0x02,0x48,0x04,0x0B,0x40,0xD2,0x0A,0x01,0x0F,0x0B,0x0C,0x01,0x00,0x0B,
++    0x44,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,0x87,0x4D,0xE8,0x85,0xAC,0x85,0x63,0xAA,
++    0xC8,0x03,0x43,0x09,0x83,0x16,0xC8,0x03,0x40,0x29,0x88,0x86,0x46,0x8A,0xC4,0x01,
++    0x82,0x1F,0xC8,0x4F,0x69,0x82,0xC4,0x43,0x40,0x11,0x98,0x2E,0xCF,0x03,0xBB,0xFF,
++    0xF8,0x67,0x00,0x01,0x83,0x43,0xE9,0x85,0xE1,0x00,0x82,0x43,0xEB,0x85,0xCB,0x03,
++    0x40,0x21,0x88,0x26,0xB8,0xFF,0xFF,0x0F,0x03,0x19,0x88,0x03,0xEB,0x85,0xCB,0x03,
++    0x47,0x19,0x80,0xDE,0xC8,0x03,0x43,0x31,0x84,0xC6,0x47,0x12,0xC4,0x01,0xFE,0x03,
++    0x40,0x01,0x88,0x3E,0x41,0xFA,0x83,0x01,0xD0,0x0B,0x48,0x31,0x9C,0x76,0xC7,0x03,
++    0x37,0x00,0xA8,0x5E,0x44,0xDA,0xC3,0x01,0xE8,0x03,0x44,0x01,0x8F,0x36,0xBF,0xFF,
++    0xEB,0xCF,0xEC,0x85,0xA8,0xC5,0x27,0x01,0x30,0x1A,0x00,0x09,0x4B,0xAA,0x6B,0xBA,
++    0x30,0x01,0x59,0x51,0x80,0xE6,0xE1,0x4E,0x79,0xAA,0xC3,0xD3,0x85,0x1F,0xE8,0x6F,
++    0x61,0x52,0x20,0x09,0x39,0x61,0x62,0x52,0x71,0x61,0x62,0x92,0x40,0x6A,0x13,0x31,
++    0xC2,0x01,0x56,0x03,0x80,0x01,0x5A,0xC9,0x80,0xAE,0xE1,0x4E,0x59,0x59,0x80,0x56,
++    0x59,0x61,0x80,0x66,0x59,0x69,0x88,0xBE,0x02,0x29,0x88,0x43,0x21,0x09,0x00,0x9F,
++    0x59,0xD1,0x80,0x6E,0x59,0x01,0x89,0x7E,0x88,0x53,0x22,0x09,0x08,0x59,0xA5,0x0B,
++    0x00,0x57,0x01,0x39,0x89,0x43,0x02,0x3F,0x86,0x07,0xE8,0x17,0x00,0x27,0x19,0x12,
++    0x81,0xD3,0x01,0x0F,0x00,0x41,0x18,0x12,0x80,0xD3,0x01,0xEF,0x02,0x11,0x88,0x43,
++    0x20,0x09,0x00,0xCF,0x02,0x01,0x88,0x43,0x41,0x43,0x19,0x82,0x00,0x43,0x01,0x9F,
++    0x88,0x43,0x22,0x09,0x00,0x87,0x00,0x19,0x88,0x43,0x22,0x09,0x00,0x67,0x00,0x21,
++    0x88,0x43,0x22,0x09,0x02,0x47,0x88,0x53,0x26,0x09,0x08,0x69,0xA0,0x0B,0x00,0x1F,
++    0x88,0x53,0x22,0x09,0x08,0x79,0xA7,0x0B,0x60,0x01,0x80,0x66,0x40,0x6A,0x42,0x0B,
++    0x30,0x48,0xA8,0x2E,0x08,0x81,0x06,0x0B,0x08,0x81,0x02,0x0B,0x08,0x81,0x00,0x0B,
++    0x45,0x43,0x19,0x82,0x07,0x43,0xE9,0xC5,0xAC,0x8D,0x87,0x15,0x40,0x32,0x82,0x0C,
++    0x46,0x02,0xC2,0x01,0xDA,0x2B,0xD8,0x33,0x0C,0x01,0xB0,0x0B,0x61,0x02,0xC2,0x0B,
++    0x10,0xF9,0x05,0x8A,0x81,0x0B,0xC1,0x0B,0x10,0x01,0x19,0x8A,0x81,0x0B,0x49,0xEA,
++    0x8A,0x01,0x46,0x53,0x18,0x01,0x1A,0xD2,0x01,0x53,0x52,0xAA,0x44,0x8B,0x1A,0x01,
++    0x1A,0xCA,0x00,0x8B,0x48,0x8A,0x41,0x53,0x18,0x09,0x18,0xD2,0x02,0x53,0x50,0x03,
++    0x80,0x01,0xE2,0x0B,0x49,0x79,0x87,0xAE,0xE6,0x03,0x40,0x69,0x88,0x16,0x09,0xA9,
++    0x07,0x91,0xB8,0xFF,0xE8,0x4F,0x47,0x09,0x89,0xDE,0x31,0x42,0x1A,0x82,0x03,0x38,
++    0x15,0x09,0x90,0xCD,0x90,0x04,0x18,0x01,0xC7,0x0C,0xB8,0xFF,0xE9,0x47,0x44,0x5A,
++    0x10,0x09,0x90,0x04,0x15,0x01,0x90,0xCD,0x37,0x9A,0xB8,0xFF,0xE8,0x07,0xC4,0x14,
++    0x15,0x09,0xC8,0x48,0xE8,0x48,0x90,0x04,0x00,0x48,0x12,0x01,0x1F,0x09,0xB8,0xFF,
++    0xE8,0xB7,0x03,0xF7,0x08,0xA1,0x00,0x91,0xBE,0xFF,0xEF,0x37,0x40,0x09,0x88,0xC6,
++    0x18,0xAA,0x13,0x09,0x20,0x40,0x63,0x08,0x90,0x04,0x30,0x9A,0xC7,0x0C,0xB8,0xFF,
++    0xE8,0x37,0x03,0x77,0x08,0xB1,0x00,0x91,0xBD,0xFF,0xEF,0xB7,0x40,0x09,0x88,0x46,
++    0xC0,0x14,0x10,0x09,0xC8,0x48,0xED,0x48,0x00,0x48,0x32,0x9A,0x97,0x04,0xB8,0xFF,
++    0xE9,0xB7,0xC2,0x03,0x08,0xF9,0x06,0x42,0x80,0x03,0x41,0x42,0x42,0x0B,0x40,0x48,
++    0x00,0x48,0x02,0x0B,0x47,0x32,0x08,0x01,0x08,0x0B,0x0A,0x01,0x02,0x0B,0x44,0x0B,
++    0x10,0x01,0x1C,0x8A,0x07,0x0B,0xEA,0xF5,0x70,0x00,0x04,0x01,0xF8,0x00,0x06,0x42,
++    0x80,0x01,0x06,0x42,0x00,0xE0,0x06,0x01,0x00,0x00,0x00,0x01,0x10,0x00,0x00,0x42,
++    0x00,0xE0,0x07,0x01,0x00,0x00,0x00,0x42,0x50,0x20,0x07,0x01,0x08,0x20,0x02,0x01,
++    0x52,0xE2,0x43,0x83,0x03,0x83,0x42,0xE2,0xF7,0x0B,0x4C,0xF9,0x94,0x16,0xF0,0x0B,
++    0xE4,0x48,0xB2,0x0B,0xF0,0x03,0x44,0xC1,0x90,0x0E,0x00,0x01,0x03,0x83,0x3C,0x82,
++    0x4C,0xB2,0x4B,0x53,0x5C,0xA2,0xE3,0xC3,0x1C,0x12,0x0C,0x53,0x10,0x43,0x02,0x09,
++    0xB3,0xC3,0x3C,0x82,0xAB,0x85,0x40,0x8A,0x84,0x01,0x42,0x0B,0x10,0x01,0x1C,0x8A,
++    0x03,0x0B,0x54,0x7A,0x4B,0x62,0x43,0x7A,0x86,0x1F,0xC0,0x97,0xEF,0x85,0xA8,0xC5,
++    0x47,0x4A,0x83,0x01,0xC3,0x0B,0x70,0x62,0x30,0x48,0xAC,0x46,0xC2,0x0B,0x10,0x01,
++    0x18,0x8A,0x80,0x0B,0x44,0x83,0x0B,0x01,0x1B,0x42,0x04,0x83,0xE8,0xC5,0x0F,0x01,
++    0x0D,0x8B,0x45,0x9B,0x66,0x02,0x03,0x79,0x01,0x1A,0x30,0x2A,0xAB,0x01,0x69,0x04,
++    0x50,0x13,0x5B,0x09,0x80,0xE6,0x58,0x29,0x80,0x46,0x58,0x41,0x8B,0xB6,0x93,0x4B,
++    0x46,0x9B,0x3F,0xD8,0x88,0x16,0x00,0x81,0x07,0x83,0xED,0xC5,0x0A,0x8B,0x4D,0xDA,
++    0x10,0x42,0x8C,0x16,0x07,0x29,0x05,0x83,0x00,0x3F,0xE0,0x92,0x02,0x93,0xE7,0x00,
++    0x93,0x05,0x2C,0x04,0x40,0x89,0x9A,0x06,0x28,0x0C,0x03,0xA1,0x07,0x83,0xED,0xC5,
++    0x5B,0x9A,0xD2,0x7B,0x40,0xDC,0x78,0x11,0x90,0x56,0x7B,0x01,0x8F,0x36,0x40,0x83,
++    0x50,0x7A,0x02,0x84,0x43,0x7A,0x12,0x03,0x2C,0x0C,0x03,0x1F,0x40,0x83,0x17,0xD0,
++    0x48,0x5A,0xC2,0x80,0x90,0x3D,0x04,0x7C,0x00,0x89,0x16,0x00,0xD1,0xC0,0x41,0x01,
++    0xC7,0x96,0x90,0xC5,0xBC,0xFF,0xF7,0x37,0x44,0x3A,0x12,0x3A,0x82,0x96,0x43,0x32,
++    0x84,0x41,0x10,0x3A,0x88,0x76,0x03,0x09,0x86,0x07,0xC8,0x37,0x05,0xC1,0xB0,0x03,
++    0x40,0x12,0x0A,0x09,0x83,0x0B,0x00,0x2F,0x46,0xBA,0x81,0x01,0xC8,0x03,0x42,0x01,
++    0x89,0x26,0x41,0xEA,0xC4,0x31,0x16,0x3A,0x89,0xAE,0x40,0xEA,0x41,0x0B,0x40,0xCA,
++    0x72,0x50,0x80,0x01,0x80,0x13,0x60,0x50,0x80,0x13,0x52,0x50,0x86,0x13,0x84,0x0B,
++    0xC2,0x0B,0xC0,0x13,0xC4,0x48,0xC4,0x13,0xC6,0x1B,0xC6,0x90,0xC5,0x48,0x8C,0x29,
++    0x50,0x50,0x88,0x13,0x88,0x0B,0x02,0x69,0x19,0x00,0xD0,0xC0,0x40,0x81,0xC2,0x0E,
++    0x29,0x04,0x03,0xFF,0x06,0x01,0x18,0x02,0x29,0x04,0x03,0xDF,0x41,0x6A,0xC1,0xC0,
++    0x40,0x19,0xC1,0x26,0x29,0x04,0x43,0x62,0x11,0x03,0x03,0x9F,0x01,0xC7,0x41,0x4A,
++    0xC1,0x81,0xC1,0xC0,0x40,0x01,0xC1,0x26,0x29,0x04,0x43,0x3A,0xC3,0x01,0x11,0x03,
++    0x00,0x47,0x01,0x69,0x19,0x00,0xD0,0xC0,0x41,0xB1,0xC1,0x1E,0x29,0x04,0x03,0x0F,
++    0x7D,0xD2,0x10,0xC2,0x87,0xF6,0x40,0xBB,0xA0,0xBA,0x40,0xDA,0xC4,0xD1,0x15,0x1A,
++    0x8B,0x7E,0x68,0x04,0x40,0x61,0x8A,0x66,0x50,0x1B,0xE3,0xFA,0x52,0x72,0x90,0x01,
++    0x78,0x01,0x8C,0x16,0x04,0x09,0xA8,0x83,0x00,0x1F,0xE0,0xC2,0x40,0x01,0x88,0x06,
++    0xAB,0x8B,0x6C,0x04,0xE4,0x00,0x92,0x05,0x2A,0x04,0x43,0x89,0x98,0x16,0x00,0x01,
++    0x1B,0x02,0x2E,0x04,0xD2,0x43,0xE3,0x00,0x90,0x43,0x03,0x81,0x07,0x83,0xED,0xC5,
++    0x07,0x8B,0xED,0xC5,0x10,0x00,0x00,0x42,0x00,0xE0,0x00,0x01,0xF8,0x00,0x06,0x42,
++    0x80,0xC0,0x04,0x01,0x08,0x40,0x00,0x01,0x80,0x01,0x06,0x42,0xF8,0xFF,0x07,0x00,
++    0x00,0x10,0x00,0x01,0x80,0x30,0x02,0x01,0x88,0x36,0x00,0x00,0x00,0x20,0x00,0x01,
++    0x00,0xA0,0x00,0x01,0x77,0x81,0xF8,0xFF,0xF8,0x02,0x07,0x00,0xA8,0x85,0x80,0x07,
++    0xC8,0xBF,0x65,0x32,0xC8,0x03,0x43,0x01,0x80,0x26,0x40,0x31,0x8F,0xD6,0xBF,0xFF,
++    0xD7,0x8F,0x3C,0xBF,0xBE,0xFF,0xCF,0x97,0x38,0xA7,0x07,0x00,0x00,0xE0,0x06,0x01,
++    0xAF,0xC5,0x77,0x62,0x03,0x01,0x87,0x83,0x01,0x09,0x80,0x83,0x0F,0x01,0x81,0x8B,
++    0x05,0x19,0x80,0x83,0x03,0x41,0x89,0x83,0x07,0x69,0x89,0x83,0x05,0x69,0x88,0x83,
++    0x11,0x02,0x32,0xAA,0xA9,0x01,0x06,0x44,0x04,0xF9,0x87,0x89,0x20,0x84,0x01,0x09,
++    0x34,0x62,0xE1,0x01,0x93,0x03,0x91,0x03,0x05,0x41,0x90,0x03,0x17,0x51,0x90,0x13,
++    0x11,0xA1,0x98,0x13,0x98,0x0B,0x0D,0x81,0x99,0x0B,0xA7,0x03,0x3B,0x01,0xA0,0xBB,
++    0x09,0x71,0x98,0x8B,0x0B,0x29,0x98,0x8B,0x17,0x71,0x98,0x93,0x99,0x8B,0xA5,0xBB,
++    0xA1,0x83,0x05,0x81,0xA0,0x83,0x07,0x51,0x8F,0x03,0x01,0xB1,0x8D,0x03,0x8B,0x3B,
++    0x8B,0x3B,0x9F,0x0B,0x05,0x99,0x28,0x84,0x07,0xF9,0x87,0x09,0x10,0x44,0x01,0xC9,
++    0x0B,0x00,0x12,0x44,0x02,0x19,0x18,0x00,0x0E,0x43,0x43,0x5A,0x0A,0x43,0x05,0x01,
++    0xB9,0x43,0x31,0x02,0x0D,0x51,0x80,0x11,0x83,0x1F,0xD0,0x17,0x01,0xB1,0x97,0x43,
++    0x1B,0xF1,0x90,0x5B,0x89,0x7B,0x33,0x02,0x82,0x01,0xB2,0x3B,0xB8,0x3B,0x08,0xC1,
++    0xB8,0x0B,0x0A,0x51,0xBE,0x0B,0x14,0x41,0x31,0x0A,0x88,0x01,0x0F,0x54,0x12,0xF9,
++    0x94,0x99,0x0A,0x54,0x16,0xC1,0xBE,0x13,0x10,0x41,0x81,0x53,0x12,0x11,0x87,0x53,
++    0x80,0x5B,0x14,0x51,0x91,0x13,0x12,0x41,0x93,0x13,0x14,0x21,0x92,0x13,0x16,0xA9,
++    0x08,0x14,0x16,0x71,0x9A,0x13,0x10,0x69,0xA0,0x13,0x10,0x21,0xA6,0x13,0x12,0x41,
++    0x10,0x14,0x12,0x31,0xBF,0x93,0x37,0xBC,0xB0,0x3B,0x1C,0x21,0x33,0x12,0x90,0x01,
++    0x90,0x9B,0x1C,0x31,0x96,0x9B,0x12,0x99,0x08,0x94,0x11,0xA1,0x80,0x53,0x16,0x51,
++    0x8E,0x53,0xB0,0x3B,0x12,0x21,0x8C,0x53,0x53,0x42,0x05,0x54,0x14,0x09,0x88,0x53,
++    0x10,0x51,0x90,0x53,0x17,0x11,0xA0,0x13,0x08,0x21,0xA8,0x0B,0x0A,0xC1,0xAB,0x0B,
++    0xA8,0x0B,0x1C,0x01,0x33,0x0A,0xC8,0x01,0xA0,0x5B,0xAE,0x5B,0x22,0xF1,0x88,0x01,
++    0xBA,0x63,0xB8,0x63,0x24,0xE1,0xB9,0x63,0x26,0x41,0xB8,0x63,0x80,0x13,0x08,0xB1,
++    0x80,0x0B,0x0A,0x19,0x84,0x0B,0x4C,0xD2,0x00,0x0B,0x92,0x1B,0x4C,0xCA,0xC4,0x01,
++    0x38,0x0B,0x88,0x91,0x3E,0x0B,0x8A,0xE1,0x38,0x0B,0x0C,0xE1,0x40,0xB2,0x84,0x1F,
++    0xCC,0xBF,0x47,0xAA,0x09,0xE1,0xC0,0xC1,0x87,0x1F,0xC8,0x97,0x4C,0x8A,0x44,0x9A,
++    0xCE,0x11,0x03,0x0B,0xCC,0x71,0x00,0x0B,0x88,0xA1,0x08,0x0B,0x8A,0xA1,0x08,0x0B,
++    0xCA,0xE1,0x01,0x0B,0xC8,0xC1,0x01,0x0B,0x8C,0x61,0x0D,0x0B,0xCA,0x81,0x15,0x0B,
++    0xF8,0x48,0x10,0x0B,0xFE,0x48,0x08,0x0B,0xE9,0xC5,0xAF,0x85,0x0C,0x01,0x60,0x0A,
++    0x47,0x02,0xA4,0x61,0xF8,0x1B,0x06,0x77,0x02,0x21,0x19,0x42,0xCB,0x28,0x00,0x99,
++    0x12,0x79,0x08,0x00,0xC4,0x40,0x89,0x13,0x16,0x01,0x88,0x13,0x94,0x13,0x10,0x14,
++    0x12,0x14,0xE6,0x48,0x94,0x4D,0x16,0x5A,0xC0,0x76,0x07,0x01,0x13,0xF9,0x2F,0x89,
++    0x08,0x68,0x03,0x37,0x00,0x08,0xCA,0x48,0xCC,0x48,0xAA,0x53,0xAA,0x53,0xE6,0x00,
++    0x94,0x05,0x16,0x1A,0xC1,0xB6,0xEF,0x85,0xA3,0x85,0x51,0x72,0x90,0x01,0x0E,0x01,
++    0x26,0x8C,0xD0,0x01,0xBC,0x8B,0xB8,0x8B,0x36,0x9A,0x98,0x01,0x8A,0xCB,0x0C,0xCC,
++    0x9E,0xCB,0x88,0xCB,0x2C,0x09,0xB0,0xAB,0xA8,0x8B,0x34,0xA2,0xA1,0x01,0xCD,0x1B,
++    0xB0,0x9B,0x36,0x9A,0x9A,0x01,0xA9,0xCB,0x9A,0x01,0xA9,0xEB,0xA8,0xCB,0xA8,0xAB,
++    0x28,0x41,0x89,0xAB,0x8B,0x0B,0x57,0x32,0x88,0x8B,0x46,0x09,0x8C,0x16,0xA8,0xCB,
++    0xE5,0x85,0x39,0x97,0xE3,0x85,0x39,0x82,0x0B,0x08,0x42,0x12,0x41,0x13,0x18,0x01,
++    0x04,0xD2,0x90,0x41,0x04,0x13,0x10,0xD0,0x1A,0x8A,0x08,0x0B,0x40,0x0B,0x42,0x0B,
++    0x14,0x41,0x18,0x8A,0x00,0x0B,0x08,0x01,0x03,0x0B,0x3C,0x82,0xAA,0x85,0x40,0xD2,
++    0x40,0x0B,0x30,0x48,0xAE,0x2E,0x08,0x81,0x02,0x0B,0x08,0x81,0x00,0x0B,0x08,0x81,
++    0x02,0x0B,0x48,0xAA,0x8C,0x01,0x46,0x53,0x38,0x90,0x78,0x90,0x04,0x53,0x44,0x53,
++    0x18,0x81,0x19,0xD2,0x02,0x53,0x5C,0x8A,0x12,0x09,0x06,0xD3,0x16,0x91,0x01,0x13,
++    0x44,0x7A,0x42,0x23,0x10,0x61,0x18,0xA2,0x02,0x23,0x44,0x23,0x1A,0xA2,0x00,0x23,
++    0x4C,0x23,0x1A,0xA2,0x08,0x23,0x4A,0x23,0x18,0xA2,0x08,0x23,0x40,0x23,0x1E,0xA2,
++    0x02,0x23,0x46,0x43,0x10,0x01,0x1A,0x82,0x04,0x43,0x02,0xD1,0x07,0xC3,0x00,0x01,
++    0x08,0xC3,0xEA,0x85,0x40,0x12,0x42,0x13,0x08,0x09,0x18,0x52,0x00,0x13,0x48,0x13,
++    0x18,0x52,0x0C,0x13,0x4C,0x13,0x1A,0x52,0x0E,0x13,0x42,0x13,0x1E,0x52,0x00,0x13,
++    0x39,0x82,0x43,0xE2,0x58,0x0B,0x10,0x21,0x18,0x8A,0x18,0x0B,0x5A,0x0B,0x10,0x01,
++    0x18,0x8A,0x18,0x0B,0x5C,0x13,0x08,0x01,0x18,0x52,0x18,0x13,0x40,0x92,0x11,0x01,
++    0x80,0x01,0x06,0x13,0x40,0x13,0x1A,0x52,0x01,0x13,0x4A,0x72,0x41,0x43,0x10,0x01,
++    0x18,0x82,0x00,0x43,0x38,0x82,0xAB,0x85,0x08,0x09,0x00,0x31,0x81,0x07,0xD0,0xF7,
++    0x08,0x11,0x00,0x21,0x81,0x07,0xD0,0xD7,0x00,0x09,0x80,0x07,0xD0,0xB7,0x02,0x31,
++    0x82,0x07,0xD0,0x9F,0x00,0x21,0x80,0x07,0xD0,0x87,0x82,0x07,0xD0,0x2F,0xEB,0x85,
++    0xA8,0x85,0x43,0xF2,0x4A,0xBA,0xC0,0x91,0x11,0x43,0x0A,0x91,0x80,0x1F,0xC8,0x07,
++    0x40,0xD2,0x08,0x51,0x80,0x41,0x81,0x1F,0xC7,0xEF,0xBF,0xFF,0xF0,0x4F,0x02,0x09,
++    0xBA,0xFF,0xFF,0x17,0x07,0xA1,0xB8,0xFF,0xFF,0x3F,0xBB,0xFF,0xFF,0xBF,0xBB,0xFF,
++    0xFF,0xC7,0xBD,0xFF,0xFF,0x3F,0xBD,0xFF,0xF8,0x77,0x66,0x8A,0x29,0x01,0x80,0x2B,
++    0x08,0x2B,0x41,0x72,0x09,0x71,0x80,0x91,0x87,0x1F,0xC0,0x17,0x0B,0x2C,0x81,0x2B,
++    0x87,0x2B,0x85,0x2B,0x8B,0x2B,0x89,0x2B,0x05,0x51,0x88,0x03,0x0F,0x2C,0x8B,0x2B,
++    0x0B,0x2C,0xED,0x85,0x00,0xE0,0x00,0x01,0xC8,0x21,0x01,0x00,0x70,0x02,0x01,0x00,
++    0xF8,0xFF,0x07,0x04,0x68,0xE2,0x01,0x00,0x70,0x70,0x06,0x01,0x80,0xC0,0x04,0x01,
++    0x00,0x20,0x00,0x01,0x10,0x00,0x00,0x42,0x00,0x00,0x00,0x42,0x80,0x01,0x06,0x42,
++    0xF8,0x00,0x06,0x42,0x18,0x00,0x02,0x42,0xA8,0x85,0x80,0x07,0xC8,0xCF,0xEE,0x85,
++    0xAF,0x85,0xB8,0xFF,0xE8,0x9F,0xEF,0x85,0xA8,0x7D,0x80,0x04,0x88,0x0C,0xC0,0x0C,
++    0x80,0x14,0xC0,0x04,0x83,0x1C,0x30,0x42,0x40,0x7E,0x80,0x25,0xE8,0x05,0x00,0x00,
++    0xAC,0xFD,0x87,0x1D,0x30,0x32,0x00,0x01,0x82,0x14,0x00,0x9F,0x44,0xDA,0x0E,0x01,
++    0x0C,0x0B,0x26,0x01,0xC2,0x14,0x00,0x28,0x7F,0xC2,0x4E,0xC3,0x1F,0x02,0x09,0xC3,
++    0xD0,0x6C,0x90,0x04,0x14,0x09,0x08,0x01,0x30,0x82,0xD9,0x64,0x86,0x17,0xE0,0x1F,
++    0xF8,0x82,0x33,0x0A,0xCF,0x99,0x49,0xC9,0x99,0x3E,0x40,0x91,0xE7,0x16,0x48,0xC3,
++    0x1F,0x02,0x0D,0xC3,0x40,0x20,0x63,0x01,0x88,0x36,0xD7,0x6C,0x90,0x04,0x10,0x09,
++    0x09,0x01,0x34,0x82,0xD8,0x64,0x80,0x17,0xE3,0x77,0xFD,0xA2,0xD0,0x6C,0x90,0x04,
++    0x14,0x09,0x08,0x01,0x30,0x82,0xD9,0x64,0x85,0x17,0xE0,0x2F,0xF8,0xBA,0xD3,0x6C,
++    0x90,0x04,0x10,0x09,0x09,0x01,0x34,0x82,0xD8,0x64,0x80,0x17,0xE5,0xE7,0x14,0x3A,
++    0xE9,0x16,0x30,0x02,0x30,0xE2,0x31,0x3A,0xFD,0x82,0x13,0xC2,0xE3,0x0E,0x98,0xBA,
++    0x05,0x17,0x10,0x02,0xDB,0x06,0x98,0xA2,0x46,0xC2,0x4D,0x03,0xDE,0x8A,0x0B,0x00,
++    0xC0,0x00,0xCA,0x24,0x00,0x44,0xC0,0x24,0xE0,0x00,0x84,0x24,0xC2,0x14,0xE0,0x00,
++    0x90,0x05,0x86,0x14,0xC8,0x2C,0xC0,0x14,0x15,0x42,0x9C,0x3E,0x87,0x3D,0xE8,0x85,
++    0xAC,0xFD,0x87,0x7D,0x30,0xA2,0x30,0xFA,0xD8,0x0B,0x8F,0x6C,0xD8,0x0B,0x8B,0x64,
++    0x40,0x01,0x80,0x6E,0x48,0x52,0x05,0x99,0x07,0x43,0x12,0xF9,0x58,0x3A,0x95,0x81,
++    0x10,0xD3,0x06,0x43,0x00,0xC1,0x83,0x17,0xF8,0xFF,0xF1,0x84,0xB0,0xE1,0x01,0xCF,
++    0x40,0x1A,0x0D,0x19,0x04,0x0B,0x0A,0x19,0x05,0x0B,0x48,0x12,0xC2,0x84,0xC0,0x30,
++    0x11,0x01,0x30,0xDA,0x30,0x8A,0x00,0x09,0x82,0x17,0xC0,0xC7,0x29,0x01,0x30,0x1A,
++    0x14,0x09,0x08,0x01,0x40,0x1D,0xB8,0x04,0x82,0x17,0xE0,0x6F,0xE7,0x68,0x93,0x6D,
++    0x6F,0x91,0x99,0xA6,0x48,0xB2,0x44,0x43,0x10,0x11,0x18,0x82,0x01,0x43,0x30,0x02,
++    0x80,0x01,0x35,0x2A,0xC8,0x03,0x32,0x00,0xAC,0xEE,0x49,0x9A,0x00,0x01,0x80,0x43,
++    0x31,0x12,0x31,0xCA,0x00,0x11,0x80,0x0F,0xF9,0xF7,0x34,0x1A,0xB8,0x04,0x08,0x01,
++    0x00,0x11,0xD0,0x84,0x84,0x17,0xC0,0x47,0x49,0x42,0xD4,0x43,0x08,0x43,0x2A,0x01,
++    0xC2,0x64,0x00,0x00,0x80,0x74,0x00,0xBF,0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,
++    0x81,0x17,0xC0,0x27,0xB8,0x0C,0xA0,0x04,0x30,0x8A,0x41,0x1D,0xD8,0x84,0xD0,0x64,
++    0xB9,0xFF,0xFF,0xF7,0xC4,0x74,0xC8,0x30,0x09,0x09,0x30,0xDA,0x30,0x52,0x31,0x42,
++    0x80,0x17,0xC0,0xA7,0xE7,0x68,0x93,0x6D,0xC4,0x6C,0x10,0x2A,0x99,0x26,0x37,0x1A,
++    0xB8,0x04,0x08,0x01,0x00,0x19,0xD0,0x84,0x82,0x17,0xC0,0xF7,0x31,0x12,0x31,0xCA,
++    0x00,0x01,0x80,0x0F,0xFB,0x47,0x4B,0x92,0x40,0x43,0x10,0x11,0x18,0x82,0x04,0x43,
++    0x87,0x9D,0xE8,0x85,0xAC,0xFD,0x87,0x1D,0x30,0x7A,0x50,0x01,0x80,0x16,0x00,0x01,
++    0x80,0x0C,0x00,0x0F,0x00,0x09,0x80,0x0C,0x2A,0x01,0x00,0x47,0xCD,0x64,0x00,0x40,
++    0xC1,0x30,0x32,0x52,0x08,0x19,0xD8,0x6C,0xC0,0x0C,0x80,0x0F,0xF9,0x3F,0x07,0x41,
++    0x85,0x17,0xF0,0xD7,0x20,0x09,0xC0,0x34,0x80,0x01,0x84,0x14,0x60,0x81,0x99,0x36,
++    0x0A,0xF9,0x47,0xF2,0x88,0x11,0x18,0x0B,0x42,0x08,0x1B,0x0B,0x02,0x0F,0x40,0xDA,
++    0x1F,0x23,0x02,0xF9,0x4F,0xCA,0x82,0x89,0x88,0x01,0x12,0x43,0x00,0x11,0x80,0x17,
++    0xF0,0x1F,0xC5,0x14,0xF0,0x03,0x46,0x01,0x80,0x3E,0x00,0x51,0x84,0x17,0xF0,0xE7,
++    0x40,0x83,0x41,0x03,0x30,0x00,0xA8,0x86,0x07,0x5F,0x00,0xF9,0x4C,0x7A,0x82,0x89,
++    0x88,0x01,0x12,0x43,0x00,0x09,0x80,0x17,0xF1,0x7F,0x44,0x83,0x40,0x03,0x30,0x00,
++    0xA3,0x1E,0xE0,0x20,0x93,0x25,0x67,0xF9,0xC9,0x86,0x06,0xE4,0xE1,0xF8,0x35,0x52,
++    0x08,0x09,0xD8,0x6C,0xC0,0x0C,0x80,0x0F,0xFB,0x4F,0xE5,0x68,0x90,0x6D,0xC7,0x1C,
++    0x15,0x2A,0x9C,0x9E,0x3F,0x17,0xA9,0x85,0x80,0x3D,0x34,0x7A,0x34,0xA2,0x00,0xD9,
++    0xEF,0x02,0x0E,0xF9,0x88,0x09,0x40,0x01,0x80,0x0E,0x30,0x72,0x00,0x0F,0x30,0x19,
++    0x13,0xB0,0xD9,0xC3,0x81,0x34,0xD8,0xC3,0x80,0x2C,0x98,0x1C,0xC2,0x34,0x00,0x00,
++    0xC0,0x00,0x86,0x24,0x45,0xAA,0x11,0x81,0x00,0x13,0x1A,0x0B,0x28,0x01,0x00,0x67,
++    0x4D,0x03,0x01,0x48,0xC0,0x00,0x42,0x03,0x01,0x33,0x30,0x1A,0x30,0x52,0x09,0x09,
++    0x00,0x01,0x80,0x0F,0xFB,0xDF,0xE3,0x68,0x90,0x6D,0xC7,0x34,0x17,0x2A,0x9C,0x7E,
++    0x28,0x01,0x00,0x67,0x4D,0x03,0x03,0x48,0xC0,0x00,0x42,0x03,0x00,0x33,0x08,0x09,
++    0x31,0x1A,0x31,0x52,0x30,0x42,0x80,0x0F,0xFB,0x4F,0xE3,0x68,0x90,0x6D,0xC7,0x2C,
++    0x17,0x2A,0x9C,0x7E,0x48,0x0B,0xA1,0x0C,0x89,0x04,0x30,0xDA,0x10,0x09,0xC8,0x1C,
++    0xC7,0x34,0xB8,0xFF,0xFB,0xFF,0x4A,0x0B,0x89,0x04,0x30,0xDA,0x10,0x01,0xA0,0x0C,
++    0xC8,0x24,0xC0,0x2C,0xBA,0xFF,0xFF,0xB7,0x48,0xC2,0x00,0x01,0x88,0x01,0x12,0x43,
++    0x48,0xB2,0x18,0x43,0x37,0x57,0xAE,0xC5,0x30,0x1A,0x30,0x42,0x30,0xBA,0xD8,0x23,
++    0xD8,0x2B,0x4A,0xB2,0xC0,0xC8,0x8A,0x04,0x30,0xD2,0x31,0xCA,0x87,0x0F,0xF8,0xDF,
++    0x30,0x01,0x00,0x3F,0x09,0x09,0x30,0xDA,0x30,0x92,0x31,0x42,0x81,0x0F,0xF8,0xB7,
++    0xE7,0xB0,0x93,0xB5,0x17,0x32,0x9D,0xAE,0xC8,0x04,0x10,0x01,0x18,0x01,0x00,0x4F,
++    0x00,0x01,0x00,0x1F,0x82,0x5B,0xE0,0x48,0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0xCE,
++    0xE6,0x90,0x92,0x95,0x17,0x12,0x9D,0x9E,0xE8,0xC5,0x07,0x00,0x00,0x01,0x00,0x42,
++    0x18,0x00,0x04,0x42,0x48,0xE0,0x06,0x00,0x00,0xD0,0x00,0x01,0x60,0x20,0x02,0x00,
++    0x49,0x32,0x41,0x2A,0x05,0x43,0x9E,0xFF,0x7F,0x04,0x3A,0xF7,0x94,0x15,0x3A,0x00,
++    0x77,0x18,0x06,0xF9,0x04,0xC2,0x3C,0x48,0x74,0x48,0x00,0xCA,0x50,0x01,0xD0,0x5E,
++    0x38,0x90,0x78,0x90,0xD4,0x41,0x40,0x98,0x54,0xE2,0x00,0xD8,0xC6,0xD0,0x4C,0x9B,
++    0x18,0x1A,0x1C,0x5A,0x0B,0x9B,0x3E,0x82,0x40,0x98,0x54,0xCA,0x04,0xD8,0xC4,0xD0,
++    0x44,0x9B,0x18,0x1A,0x18,0x5A,0x00,0x9B,0x3A,0x82,0x93,0x05,0x36,0x10,0x76,0x90,
++    0x0C,0x09,0x00,0x8A,0x48,0x00,0x52,0x9A,0x04,0x00,0xC4,0x00,0x03,0x0B,0x38,0x82,
++    0x96,0x05,0x32,0x10,0x70,0x90,0x0E,0x09,0x00,0x8A,0x54,0x72,0x4C,0x00,0x02,0x00,
++    0x94,0x01,0xC4,0x00,0x03,0x0B,0x38,0x82,0xB3,0x15,0x3B,0x82,0xFB,0x85,0x39,0x82,
++    0x40,0x32,0x48,0x0B,0x10,0x21,0x18,0x8A,0x0B,0x0B,0x38,0x82,0x48,0x1A,0x48,0x43,
++    0x14,0x21,0x18,0x82,0x0B,0x43,0x38,0x82,0x07,0x20,0x28,0xD0,0x68,0x07,0x00,0x07,
++    0x20,0x07,0x00,0x07,0x08,0x07,0x00,0x07,0xAC,0xFD,0x87,0x4D,0xD0,0x94,0x30,0x22,
++    0xF8,0x43,0x80,0x0C,0xF8,0x6B,0xC6,0x64,0x08,0x01,0x80,0x0B,0x00,0x01,0x00,0x8F,
++    0x0A,0x21,0x19,0x0A,0x18,0x99,0xCB,0x48,0x0E,0xD8,0xC2,0x48,0xC8,0x4B,0x4C,0x79,
++    0x80,0x36,0x80,0x83,0xE0,0x90,0xCA,0x64,0xD8,0x64,0xC0,0x4B,0xE0,0x48,0x82,0xCB,
++    0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0x5E,0xC0,0x64,0xC0,0x03,0x80,0x44,0x40,0x01,
++    0x88,0x0E,0x80,0x6D,0xE8,0x85,0xC7,0x44,0x40,0x09,0x88,0x1E,0xC0,0x0C,0x40,0x09,
++    0x8F,0x06,0x38,0xB7,0x00,0x01,0x80,0x34,0x80,0x2C,0xC8,0x44,0xC4,0x0C,0x10,0x0A,
++    0x88,0x96,0x02,0x01,0x30,0x01,0x08,0x01,0x88,0x1C,0x88,0x14,0x1C,0xC9,0x09,0xD8,
++    0x00,0x4F,0x10,0x31,0x18,0x52,0xCA,0x90,0xC2,0x90,0x46,0xBC,0xC4,0xC0,0x41,0x94,
++    0xCA,0xB0,0xE4,0x48,0x90,0x4D,0xD6,0x0C,0x17,0x8A,0x9C,0x96,0xC8,0x0C,0x80,0x17,
++    0xF0,0x6F,0x82,0x24,0x30,0x82,0xC9,0x0C,0x82,0x17,0xF0,0x47,0x30,0x32,0x08,0x01,
++    0x01,0x01,0x00,0x07,0x1A,0x99,0x0B,0xD8,0x02,0x0F,0xE0,0x48,0x91,0x4D,0x16,0x21,
++    0x18,0x52,0xCA,0x90,0xC4,0x90,0xCE,0x93,0x57,0x79,0x80,0xB6,0x12,0x21,0x19,0x52,
++    0xCE,0x90,0xC0,0x98,0x3E,0xF1,0xF8,0xFA,0xDF,0x1C,0xC0,0xD8,0x98,0x1C,0x18,0xE9,
++    0x0E,0xD8,0xC6,0x98,0x14,0x01,0xF0,0xD2,0xDE,0x14,0xC0,0x90,0x92,0x14,0xE0,0x48,
++    0x92,0x4D,0xE6,0x00,0x90,0x05,0xD6,0x44,0x16,0x12,0xC4,0xDE,0xC8,0x44,0xC0,0x1C,
++    0x80,0x17,0xF0,0xE7,0x30,0x3A,0xC8,0x44,0xC0,0x14,0x80,0x17,0xF0,0xBF,0xC8,0x24,
++    0xD8,0x48,0x8E,0x34,0xD0,0x80,0x81,0x2C,0x08,0x01,0x10,0x01,0x00,0x77,0x00,0x01,
++    0x33,0x5A,0x18,0x5A,0xF2,0x5C,0x00,0xD8,0xC8,0xD8,0x04,0x1F,0x04,0x30,0x9A,0xD2,
++    0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0xCE,0xE6,0x48,0x92,0x4D,0x17,0x4A,0x9D,0x76,
++    0x08,0x01,0x10,0x01,0x03,0xE7,0x19,0x99,0x08,0xD8,0x02,0x0F,0xE6,0x48,0x92,0x4D,
++    0x02,0x21,0x19,0x42,0xCC,0x00,0x30,0x22,0xC0,0x00,0x86,0x3C,0xC8,0x03,0x44,0x79,
++    0x80,0xA6,0x07,0x01,0x00,0x2F,0xD9,0x3C,0x34,0xF1,0xF8,0xF2,0xD9,0x34,0x38,0xC9,
++    0xC0,0xB0,0x1F,0x31,0x18,0x1A,0xCA,0xD8,0x0E,0xF8,0xCD,0xD8,0x47,0xFC,0xDA,0xB0,
++    0xAB,0x06,0x10,0xB2,0x95,0xB5,0x35,0xB2,0x37,0xE9,0x08,0xB0,0x20,0x32,0x3B,0x01,
++    0xF8,0xBA,0xF7,0x2C,0x45,0xDC,0xCC,0xF0,0xD0,0x98,0xAF,0x06,0x10,0xDA,0x32,0xB2,
++    0x18,0x72,0xFB,0x5C,0x07,0xB0,0xCB,0xB0,0x22,0x9A,0x03,0x38,0x9A,0x9A,0xE7,0x00,
++    0x90,0x05,0xDE,0x0C,0x16,0xC2,0x9C,0xB6,0xE6,0x48,0x92,0x4D,0xE6,0x90,0x92,0x95,
++    0xC0,0x64,0xC0,0x03,0x15,0x82,0xC4,0xF6,0xC0,0x64,0xC8,0x0C,0xC4,0x03,0x10,0x42,
++    0xC9,0x06,0x38,0xF7,0xC1,0x0C,0x38,0xE7,0xAC,0x85,0x87,0x3D,0x34,0x22,0x00,0x91,
++    0xD4,0x02,0x34,0x22,0x01,0xC1,0xF0,0x02,0x18,0x71,0x80,0x34,0xF0,0x1A,0x9F,0x2C,
++    0xD0,0x00,0x96,0x05,0x1F,0xD1,0xF0,0x1A,0x2B,0x81,0xF8,0x2A,0x32,0xF2,0xDC,0xD8,
++    0x90,0xDD,0xA8,0x24,0xC0,0x2B,0x6F,0x09,0x8D,0x16,0x10,0x04,0x10,0x1C,0x07,0x6F,
++    0x55,0x3C,0x05,0xE8,0xC7,0x68,0x51,0x04,0x07,0x30,0xC4,0x98,0xD9,0x68,0x97,0x6D,
++    0xD0,0xC0,0x90,0x1D,0x84,0x40,0x85,0xD8,0x17,0x04,0x15,0x1C,0x4B,0x81,0x80,0xF6,
++    0xE9,0x2C,0xC0,0x40,0x02,0x28,0xCA,0x00,0xEA,0x34,0xC8,0x00,0x80,0x00,0x94,0x05,
++    0xEF,0x24,0xC0,0x58,0x02,0xE8,0xCA,0xE8,0x37,0x9A,0xC3,0x58,0x80,0xD8,0x94,0xED,
++    0x90,0x01,0x46,0x01,0xD0,0x0E,0x00,0x01,0x00,0x27,0x50,0x9C,0x10,0x1A,0xD4,0x0E,
++    0x00,0x81,0xF0,0x82,0x68,0x01,0xD0,0x0E,0x28,0x01,0x00,0x27,0x55,0x9C,0x12,0x5A,
++    0xD0,0x0E,0x28,0x91,0xF8,0xAA,0xD2,0x2C,0xD0,0x90,0xF0,0xB0,0xD2,0x06,0x10,0x92,
++    0x06,0x98,0xC2,0xB8,0xD2,0x24,0xD8,0x90,0xF0,0x98,0xD0,0x06,0x15,0x92,0xC2,0xF8,
++    0x7E,0xD0,0xCF,0x90,0x18,0x90,0x66,0x90,0x58,0x01,0xD0,0x06,0x12,0xDA,0x02,0xF8,
++    0xC8,0xD8,0x76,0x01,0xD3,0x06,0x10,0xB2,0xCE,0xD8,0x7C,0xF0,0xC6,0x98,0x1F,0xD8,
++    0x60,0xF0,0x48,0x41,0x80,0x0E,0x48,0x49,0x88,0x2E,0x48,0x49,0x8A,0x1E,0x20,0x88,
++    0x63,0x50,0x20,0x88,0x63,0x70,0x30,0x0A,0x8B,0x0C,0x28,0x12,0xCB,0x06,0x30,0x12,
++    0xCC,0x0C,0x10,0x72,0xC8,0x06,0xF0,0x0C,0xDB,0x2C,0x30,0x0A,0xD0,0x48,0x34,0x7A,
++    0x1C,0xCA,0x02,0x58,0xC4,0x48,0x36,0x72,0x19,0x51,0x30,0xCA,0xF3,0x1A,0x07,0xF8,
++    0xCA,0x48,0x1E,0x5A,0x32,0x8A,0xC3,0xC8,0x1B,0x82,0x32,0x12,0x46,0xB8,0xCA,0x00,
++    0x02,0x00,0xC6,0x00,0x36,0x0A,0x03,0x48,0x88,0x1C,0x80,0x17,0xE8,0xBF,0x80,0x14,
++    0xD0,0x24,0xC0,0x0C,0xD8,0x00,0x34,0x0A,0x1C,0x82,0x02,0x10,0xC0,0x00,0x14,0x61,
++    0xF2,0x12,0x05,0x58,0xC2,0x48,0x1E,0x52,0xC3,0x80,0x18,0xAA,0x00,0x07,0x00,0x67,
++    0xCE,0x48,0x07,0x48,0xC0,0x40,0xC8,0x1C,0x80,0x17,0xE8,0x07,0xCB,0x2C,0x08,0x0C,
++    0xCD,0x24,0x08,0x0C,0xCF,0x14,0x08,0x0C,0x10,0x04,0x81,0x3D,0xEF,0x85,0xAF,0xF5,
++    0x30,0x3A,0xC0,0x44,0x60,0xD2,0xCF,0xE0,0x2F,0x31,0x70,0xCA,0x1F,0xAA,0xC2,0x68,
++    0xF5,0x21,0xC9,0x68,0x06,0x90,0xC2,0x90,0x59,0xAA,0xDF,0x81,0xC6,0xB0,0xFE,0x13,
++    0x31,0xB2,0x34,0xDA,0x32,0x3A,0xB8,0x01,0x30,0x12,0xB8,0x0C,0x92,0x01,0xBE,0x01,
++    0x59,0x09,0x88,0x4E,0x01,0x01,0x00,0x17,0xC0,0x0B,0x49,0x79,0x89,0xE6,0x40,0x4C,
++    0x0B,0x0C,0x47,0x5C,0x14,0x1C,0x31,0xE2,0xC1,0x9B,0x89,0x1B,0xC3,0x9B,0x8B,0x1B,
++    0x1B,0x0C,0x35,0x1A,0x19,0x1C,0x27,0x0C,0x23,0x1C,0x0B,0x0C,0x09,0x1C,0x45,0x4C,
++    0x1B,0x0C,0x41,0x4C,0x19,0x0C,0x83,0x03,0x0F,0x09,0x80,0x0B,0x88,0x0B,0xFD,0x8B,
++    0x90,0x0B,0x09,0x01,0x90,0x0B,0x03,0x27,0xA2,0x21,0xE1,0x00,0x93,0x05,0x2E,0x82,
++    0x9B,0xD6,0x2E,0x82,0x94,0xF6,0x03,0x2F,0x1A,0x21,0x19,0xCA,0xC8,0x60,0x08,0x41,
++    0x89,0x04,0x40,0x4C,0x18,0x0C,0x09,0x11,0xF3,0x4A,0x1B,0x0C,0x35,0x62,0xCC,0x0B,
++    0x48,0x09,0x88,0xAE,0x08,0xC1,0x18,0xE1,0xF7,0x0A,0xF3,0x1A,0xD0,0x48,0xAE,0x06,
++    0x14,0x4A,0x92,0x4D,0x30,0x72,0x1C,0xF1,0xF3,0x1A,0x37,0x0A,0xD0,0x48,0xAE,0x06,
++    0x14,0x4A,0x92,0x4D,0xE3,0xDB,0x21,0x8A,0x10,0xCA,0xCC,0x0E,0x0D,0x01,0x88,0x0B,
++    0x09,0xC1,0x18,0x01,0xF7,0x0A,0xF3,0x1A,0xD0,0x48,0xAE,0x06,0x14,0x4A,0x92,0x4D,
++    0x30,0x62,0x0C,0xD1,0x1B,0x11,0xF1,0x0A,0xF6,0x1A,0xD7,0x48,0xAA,0x06,0x10,0x4A,
++    0x24,0x0A,0x93,0x4D,0x30,0x62,0xDC,0x0C,0xC4,0x0B,0xE7,0xDB,0xE4,0xD8,0x12,0xCA,
++    0xC8,0x7E,0xF8,0x8B,0xEE,0xDB,0x01,0xCA,0x28,0x0A,0xCB,0x56,0xD6,0x0B,0x4B,0x41,
++    0x92,0x0E,0xE0,0x48,0x91,0x0B,0xD3,0x0B,0xFC,0x9B,0x10,0xCA,0x92,0x0E,0xE0,0x48,
++    0x91,0x0B,0xD1,0x0B,0x28,0x0A,0xCB,0xA6,0xDF,0x0C,0xC0,0x0B,0xE2,0xDB,0xE4,0xD8,
++    0x10,0xCA,0xCC,0x76,0xCA,0x0B,0x37,0x50,0xE2,0xCB,0x73,0x90,0xF4,0x48,0x12,0x52,
++    0x89,0x0E,0x08,0x01,0x80,0x0B,0x35,0x12,0x09,0x81,0x30,0x02,0xBC,0xFF,0xF7,0xE7,
++    0x00,0xDF,0xD8,0x0C,0xC4,0x0B,0xE7,0xDB,0xE4,0xD8,0x12,0xCA,0xC8,0x1E,0xF8,0x8B,
++    0xEE,0xD3,0x01,0x8A,0x91,0x0B,0x59,0x0C,0x23,0x0C,0x59,0x0C,0x20,0x0C,0x33,0x12,
++    0x30,0x02,0xC9,0x04,0xBC,0xFF,0xF7,0x47,0x03,0x01,0x90,0x03,0xD0,0x03,0x41,0x01,
++    0x80,0x1E,0x00,0x07,0x02,0x3F,0xF1,0x00,0x97,0x03,0xC1,0x03,0x40,0xF9,0x93,0x0E,
++    0xE7,0x00,0x82,0x03,0x43,0x44,0x15,0x04,0x03,0x19,0x80,0x03,0xE4,0xC3,0x83,0x01,
++    0x89,0x03,0xCF,0x03,0xC2,0x8B,0xD1,0x00,0xE0,0x00,0x42,0x11,0xC3,0x2E,0xC8,0x03,
++    0xC2,0x8B,0xD3,0x00,0xE0,0x00,0x42,0x11,0xCF,0x4E,0xC0,0x03,0x40,0x11,0x98,0x36,
++    0xCA,0x0C,0xE0,0x4B,0x10,0x42,0xC4,0x16,0x07,0x01,0x80,0x03,0x89,0x03,0xC7,0x83,
++    0x8B,0x03,0xC1,0x83,0x8F,0x03,0xEB,0xF5,0xAC,0x85,0x37,0xE2,0x34,0x2A,0xAB,0x01,
++    0x4A,0x5C,0x27,0xD8,0x67,0xE0,0x40,0xF9,0x88,0x0E,0x00,0x01,0xE9,0x85,0x1F,0x21,
++    0x1B,0xC2,0x5A,0xFA,0xC6,0x00,0xC4,0x00,0x1A,0x31,0x18,0xCA,0xC3,0x48,0x54,0xE2,
++    0xD4,0x21,0xC1,0x50,0x0A,0xA1,0xF0,0x0A,0x48,0x01,0xD0,0x06,0x10,0x4A,0x1A,0xB1,
++    0xF0,0x1A,0x5E,0x01,0xD2,0x06,0x10,0xDA,0xC3,0x48,0x5E,0xB2,0x10,0xCA,0x9C,0x06,
++    0x08,0x01,0x30,0x71,0x44,0x9C,0xF8,0x32,0xD8,0xD8,0xAC,0x06,0x10,0xDA,0x32,0x81,
++    0x44,0x94,0xFA,0x32,0xD8,0x90,0xAC,0x06,0x14,0x92,0xC2,0xD0,0x11,0x12,0x9D,0x0E,
++    0xC8,0x33,0x74,0x09,0x8B,0x26,0xE0,0x5B,0xCA,0x3B,0xF6,0xD8,0x10,0xFA,0xDC,0xBE,
++    0x70,0x09,0x88,0x3E,0xDC,0x5B,0x11,0x5A,0x9E,0x26,0xC0,0x03,0x40,0xF1,0xC0,0x0E,
++    0x40,0x51,0x90,0x6E,0x70,0x09,0x88,0x1E,0x30,0x02,0x5B,0x04,0x40,0xC1,0x98,0x3E,
++    0x70,0x09,0x88,0x16,0x04,0x00,0x13,0x82,0xCD,0x16,0x00,0x00,0x10,0x82,0xC4,0x0E,
++    0x07,0x01,0xE8,0x85,0x07,0x09,0xE8,0x85,0xAC,0xFD,0x87,0x5D,0x30,0xB2,0x0C,0x01,
++    0x28,0x01,0x00,0x01,0x80,0x14,0xC0,0xA4,0xF8,0x23,0x06,0x01,0x30,0x22,0x84,0x34,
++    0x00,0x27,0xD0,0x64,0x02,0xF9,0xA7,0x82,0xE6,0x48,0x92,0x4D,0x17,0x0A,0x9D,0xC6,
++    0xD3,0x74,0x28,0x92,0xC0,0x26,0xC0,0x74,0x83,0x24,0x30,0x82,0x80,0x1C,0x00,0x1F,
++    0x30,0x82,0x83,0x24,0xC0,0x74,0x80,0x1C,0x00,0x01,0x80,0x2C,0x00,0xD7,0x1A,0x01,
++    0x03,0xB7,0x32,0x02,0x06,0xC2,0x3E,0x00,0x8A,0x86,0x42,0x32,0x80,0x3C,0x00,0x01,
++    0xD0,0xA4,0xF0,0x5C,0xF8,0x93,0x90,0x54,0x33,0xD2,0x18,0x12,0x05,0xB8,0xCA,0xD0,
++    0x90,0x4C,0x00,0x6F,0xF6,0x34,0x00,0x32,0x38,0x90,0x8F,0x3E,0xF2,0x4C,0x00,0x38,
++    0xD8,0xB2,0xFF,0x3C,0x10,0xF2,0x95,0x0E,0xB0,0x3C,0x30,0x0A,0xE6,0x00,0x92,0x05,
++    0xD4,0x54,0x10,0x12,0xC1,0x76,0x77,0xBA,0x02,0x01,0x00,0x78,0xB8,0x44,0x00,0x87,
++    0x36,0x3A,0x03,0x3A,0x38,0xF8,0x8F,0x56,0x33,0x3A,0x18,0x3A,0xD3,0x5C,0x00,0xF8,
++    0xC0,0xF8,0xD5,0x44,0xD5,0xFA,0x15,0xBA,0xC1,0x0E,0x30,0xF2,0x32,0x2A,0xE0,0x00,
++    0x93,0x05,0x2E,0x82,0x9C,0x66,0x17,0xEA,0x88,0xA6,0xC0,0x14,0xC8,0x00,0x84,0x14,
++    0xC2,0x2C,0xE0,0x00,0x90,0x05,0x86,0x2C,0xC2,0x64,0xA0,0x2A,0x31,0x09,0x30,0x82,
++    0xD4,0x34,0x00,0x42,0x1C,0x82,0x90,0x05,0x85,0x34,0x00,0x72,0x30,0x02,0x1B,0x32,
++    0x94,0x85,0x35,0x22,0xD0,0x24,0xC0,0x2C,0x10,0x82,0x84,0x1E,0xE6,0xD8,0x92,0xDD,
++    0x2D,0x9A,0x9B,0x36,0xD0,0x24,0xC0,0x2C,0x15,0x82,0x9C,0x06,0xC0,0x14,0x80,0x3C,
++    0x10,0x01,0x00,0x01,0x0B,0x01,0x30,0x5A,0x80,0xCB,0x18,0x01,0x0C,0x01,0x30,0x62,
++    0x30,0x4A,0xE3,0x4A,0x02,0x0F,0xE0,0x48,0x90,0x4D,0x36,0xEA,0x07,0x6A,0x3E,0x68,
++    0x88,0xCE,0xEF,0x1C,0x10,0x4A,0x9D,0xFE,0x40,0x01,0x88,0x8E,0x08,0xF9,0x07,0x5F,
++    0xD0,0x64,0xE0,0x9A,0x28,0x9A,0x93,0x1E,0xD0,0xA4,0xF8,0x93,0x10,0x12,0xC4,0x0E,
++    0xD0,0x64,0xA0,0x8A,0xE6,0x00,0x92,0x05,0x17,0x02,0x9D,0x8E,0x87,0x7D,0xE8,0x85,
++    0xF6,0x00,0x92,0x05,0x30,0x4A,0xE3,0x4A,0x2D,0x09,0x30,0x62,0x00,0x6F,0x01,0x00,
++    0x70,0x30,0x03,0x00,0xF8,0xFF,0x07,0x00,0x33,0x6A,0x18,0x2A,0xFB,0x5C,0x00,0x70,
++    0xCA,0xB0,0x07,0x38,0xDD,0xAA,0xC7,0x50,0x2C,0x09,0x00,0x6A,0x1D,0xEA,0x90,0x5D,
++    0x31,0x72,0xA3,0x8A,0xED,0x3C,0x10,0x52,0x98,0x16,0x28,0x11,0x30,0x62,0x05,0xA7,
++    0xFA,0x74,0xE0,0x28,0x10,0xEA,0x9D,0x6E,0x90,0x3C,0x08,0x01,0x00,0x27,0xF8,0x64,
++    0xE3,0xAA,0xA3,0xEA,0xE6,0x48,0x92,0x4D,0x17,0x0A,0x9D,0xC6,0xE0,0x8A,0x29,0x09,
++    0x30,0x62,0x05,0x17,0x90,0x45,0x2F,0x01,0xA3,0xAA,0x31,0x2A,0x6D,0x01,0x80,0x2E,
++    0x33,0x6A,0x18,0x2A,0xFB,0x5C,0x00,0x70,0xCA,0xB0,0x07,0x38,0xDA,0xAA,0xDF,0x90,
++    0x2C,0x09,0x00,0x6A,0x1B,0x5A,0x35,0x6A,0xE2,0x4A,0xE1,0x48,0xA4,0x4A,0x39,0xAF,
++    0xAC,0xC5,0x37,0x22,0xFC,0x73,0x5E,0xAA,0x36,0x02,0xC3,0x00,0x31,0x32,0x34,0xAA,
++    0x38,0x21,0x31,0x62,0x1A,0xEA,0xA3,0x01,0x13,0x01,0x20,0x2A,0xC0,0x68,0x07,0xF7,
++    0xC0,0x1B,0x58,0x79,0x86,0xD6,0xC8,0x1B,0x30,0xD8,0xA0,0x3E,0x18,0xF9,0x8F,0x1B,
++    0x8E,0x1B,0xC2,0x1B,0xE5,0x3B,0x15,0xDA,0xC6,0x06,0x88,0x13,0xCA,0x1B,0x36,0xD8,
++    0x76,0xD8,0x8A,0x1B,0x58,0x01,0x80,0x0E,0xF6,0xD8,0x8A,0x1B,0xC8,0x1B,0x5E,0x01,
++    0x8A,0x26,0xC0,0x1B,0x44,0xD8,0x04,0xD8,0x84,0x1B,0x82,0x13,0x84,0x21,0x11,0x2A,
++    0xC0,0xF6,0x06,0x01,0x84,0x04,0xB8,0x53,0x30,0x82,0x03,0x8F,0xC5,0x13,0x10,0x92,
++    0x96,0x5E,0xC0,0x13,0xE2,0x3B,0x35,0x98,0x75,0xD8,0x12,0xDA,0xCC,0x2E,0xC0,0x13,
++    0x50,0x01,0x81,0x16,0x00,0x09,0x80,0x04,0x00,0x27,0x10,0x01,0x81,0x13,0x84,0x21,
++    0x17,0x2A,0xC4,0x5E,0xC0,0x04,0x40,0x01,0x83,0x76,0x31,0x92,0x36,0x5A,0x98,0x01,
++    0x00,0x47,0x01,0x01,0x80,0x83,0xC4,0x83,0x11,0x82,0x95,0x16,0xC2,0x83,0x36,0x38,
++    0xE3,0x03,0x75,0xF8,0x10,0x3A,0xCC,0xE6,0x04,0x09,0x80,0x83,0xFA,0x43,0xE4,0x00,
++    0xB8,0x43,0x3C,0x71,0xF8,0xBA,0x7E,0x01,0xD0,0x16,0x00,0x01,0x08,0x84,0x06,0x27,
++    0x54,0xC4,0x10,0x3A,0xE8,0x0E,0x50,0xC4,0x08,0x84,0x3E,0x81,0xF8,0xBA,0x7E,0x01,
++    0xD0,0x16,0x00,0x01,0x10,0x84,0x00,0x27,0x54,0xC4,0x12,0x3A,0xEA,0x0E,0x50,0xC4,
++    0x11,0x84,0x90,0x21,0x16,0xAA,0xC4,0xA6,0xF8,0x43,0x40,0x01,0x88,0x36,0x58,0x44,
++    0x16,0xE9,0x03,0x90,0x10,0x82,0x94,0x0E,0xE0,0x00,0x1A,0x44,0xF8,0x43,0x44,0x01,
++    0x80,0xCE,0x10,0x01,0x03,0x01,0x28,0x99,0x0E,0x68,0xFB,0x63,0x01,0x6F,0x18,0x21,
++    0x1B,0x1A,0x22,0x1A,0xC8,0xD8,0xD2,0xF3,0x70,0x09,0x88,0x26,0xC8,0xDB,0x5E,0x19,
++    0x8A,0x0E,0xE0,0x90,0x92,0x95,0xE6,0x00,0x94,0x05,0x16,0x22,0xC0,0x7E,0x57,0x01,
++    0x88,0x0E,0x00,0x01,0x1F,0x44,0xE8,0xC5,0xAC,0x85,0x87,0x3D,0x30,0x2A,0x30,0x62,
++    0x41,0x12,0xC2,0x40,0x08,0x29,0xEE,0x4A,0x4B,0x29,0x80,0xDE,0x4B,0x02,0xC2,0x70,
++    0xEB,0x48,0xC4,0x48,0x89,0x1C,0x48,0xF2,0x8B,0x61,0xC0,0x48,0x88,0x14,0x08,0x01,
++    0x10,0xF9,0x1F,0x79,0x03,0x3F,0xA0,0x92,0xC8,0x3B,0x7E,0x01,0x88,0x06,0x80,0x1B,
++    0xE6,0x48,0x92,0x4D,0x87,0x21,0xF9,0x3B,0x17,0x7A,0xC4,0xA6,0x00,0x01,0x80,0x34,
++    0xF8,0x03,0x41,0x01,0x80,0xCE,0xB2,0x04,0x31,0x0A,0x31,0x42,0x58,0x2D,0xD0,0x14,
++    0xBA,0xFF,0xDF,0x97,0x80,0x34,0xC0,0x34,0x40,0x01,0x88,0x76,0x30,0x01,0x00,0x47,
++    0x31,0x5A,0x31,0x92,0x08,0xF9,0x07,0x09,0xA7,0x04,0xB8,0xFF,0xE3,0x47,0xE7,0xB0,
++    0x91,0xB5,0xFF,0x03,0x17,0x82,0xC5,0x9E,0x00,0xFF,0xC1,0x34,0x40,0x09,0x88,0x96,
++    0xC1,0xB3,0x31,0x1A,0x30,0x52,0x09,0x01,0x37,0x82,0xB9,0xFF,0xE8,0x2F,0x46,0x01,
++    0x80,0x0E,0x00,0x01,0x00,0x07,0x00,0x09,0x30,0x5A,0x11,0x01,0x30,0x8A,0xA1,0x04,
++    0xBE,0xFF,0xE7,0x6F,0x00,0x4F,0xA1,0x04,0xFB,0x3B,0x31,0x5A,0xE9,0xD3,0x30,0xDA,
++    0xC8,0x1C,0xC0,0x14,0xB8,0xFF,0xF7,0x47,0x38,0x01,0x00,0xDF,0xC6,0x1C,0xE8,0x02,
++    0x40,0xF9,0x87,0x16,0xE0,0x82,0x81,0x24,0x07,0x0F,0x00,0xF9,0x81,0x24,0x30,0x1A,
++    0x31,0x52,0x31,0xCA,0xC7,0x24,0xB8,0xFF,0xE8,0xFF,0x44,0x01,0x80,0x0E,0x00,0x01,
++    0x00,0x07,0x00,0x09,0x31,0x5A,0x31,0xD2,0xA0,0x04,0xC8,0x24,0xBD,0xFF,0xE7,0x3F,
++    0xE7,0xF8,0x93,0xFD,0xFD,0x03,0x11,0xC2,0xC1,0x06,0x37,0x0A,0x30,0x42,0xD1,0x34,
++    0xBE,0xFF,0xF7,0xB7,0x20,0xCF,0x04,0x01,0x38,0x82,0x03,0x00,0x70,0x30,0x03,0x00,
++    0x48,0xE0,0x06,0x00,0xAE,0xFD,0x87,0x5D,0xC6,0xAC,0xDA,0x03,0x82,0xCC,0xC1,0xAC,
++    0xD9,0x03,0x84,0xC4,0x01,0x09,0x58,0x45,0x81,0xC3,0xC0,0xC4,0xE2,0x00,0x82,0xC3,
++    0xC4,0xC4,0x81,0xC3,0xC2,0xC4,0xF1,0x00,0x82,0xC3,0xC6,0xAC,0x82,0x01,0x87,0x54,
++    0xC0,0x0B,0x00,0x21,0x1A,0x0A,0xC0,0x54,0x82,0x0B,0xC0,0xAC,0xCA,0x03,0x42,0x00,
++    0x80,0xD4,0x09,0x01,0x40,0xB5,0x31,0x52,0x00,0x36,0x00,0x01,0x82,0xF4,0xC0,0xAC,
++    0xCC,0xB4,0x82,0x01,0x82,0x4C,0xC2,0x74,0x92,0x05,0x82,0x44,0xC2,0x6C,0x92,0x05,
++    0x82,0x3C,0xC2,0xAC,0x82,0x01,0x86,0x34,0x4B,0x11,0x80,0xBE,0x10,0x01,0x00,0x01,
++    0x4C,0x45,0xB1,0x4A,0x8F,0x2C,0x4A,0xF2,0xB2,0x4A,0x8C,0x24,0x48,0xE2,0xEF,0x48,
++    0xB2,0x4A,0x8C,0x1C,0x04,0x08,0xC4,0x48,0x91,0x4D,0x66,0x9D,0xDB,0x74,0xA2,0x1A,
++    0x62,0x85,0xD9,0x6C,0xA2,0x1A,0xDB,0x24,0x9A,0x34,0xD9,0x1C,0x9A,0x2C,0xD9,0x2C,
++    0x98,0x24,0x41,0x09,0x89,0x5E,0xD8,0x34,0x12,0xDA,0x92,0xDD,0x99,0x34,0xD9,0x2C,
++    0x12,0xDA,0x92,0xDD,0x99,0x2C,0xD9,0x24,0x12,0xDA,0x92,0xDD,0x9A,0x24,0xD9,0x5C,
++    0x32,0xE2,0xDC,0x64,0x9A,0x5C,0xD9,0x3C,0xE1,0x44,0xEA,0x2C,0xCA,0xD8,0x92,0xDD,
++    0xEB,0x34,0xC9,0x20,0x91,0x25,0xF3,0x24,0xED,0x5C,0xC9,0x68,0xA8,0x5C,0x59,0x01,
++    0xD9,0x86,0xEB,0xCC,0x13,0x5A,0xD5,0x6E,0x63,0x01,0xD8,0x5E,0xED,0xC4,0x11,0x62,
++    0xD1,0x46,0xEB,0x5C,0xC5,0x6B,0x49,0x68,0x8B,0x06,0x32,0x2A,0x3F,0x01,0xF8,0x7A,
++    0xEB,0x24,0x01,0x68,0x23,0x62,0x35,0x32,0x2B,0x01,0xF8,0xAA,0xF5,0xD4,0x11,0xAA,
++    0xEA,0xC6,0xF2,0xB4,0x71,0x09,0x88,0x16,0xD9,0xF0,0x93,0xB5,0xB2,0x9C,0xF8,0x5C,
++    0x35,0x01,0xF8,0xF2,0x10,0x72,0xDD,0x06,0x37,0xAA,0x81,0x68,0x01,0x68,0x33,0x7A,
++    0xF3,0x9C,0x10,0x6A,0x12,0xAA,0xE5,0x2E,0x6B,0x9D,0xA1,0x62,0x6B,0x85,0xA1,0x5A,
++    0x01,0xA8,0x72,0xB5,0xC9,0x68,0xE5,0x72,0xE1,0xB0,0xA3,0x72,0xEB,0xF4,0xE0,0x68,
++    0x90,0x6D,0xAF,0xF4,0xF5,0x9C,0x10,0xBA,0xD1,0xBE,0x05,0x9F,0x09,0xEF,0x6A,0x9D,
++    0xA1,0x62,0x6B,0x85,0xA2,0x5A,0x03,0xA8,0x75,0xB5,0xC9,0x68,0xE3,0x72,0xE1,0xB0,
++    0xA0,0x72,0xE9,0xF4,0xE7,0x68,0x93,0x6D,0xAD,0xF4,0x38,0x37,0xE9,0x5C,0xC1,0x6B,
++    0x48,0x68,0x6D,0x19,0x8A,0x6E,0x00,0xB0,0x7F,0xB5,0xC9,0xB0,0xE0,0xB2,0x71,0x09,
++    0xC2,0x3E,0xC0,0x64,0x08,0x01,0xC6,0x03,0x1A,0x42,0xC8,0x64,0x82,0x43,0x80,0x7D,
++    0xE8,0x85,0x6F,0x11,0x89,0x56,0x68,0x9D,0xA1,0x62,0x63,0x85,0xA2,0x1A,0x03,0x98,
++    0x4A,0xB5,0xC1,0xC8,0xE2,0x5A,0xE0,0xD8,0xA0,0x5A,0x00,0x1F,0xCE,0x34,0xCA,0x4B,
++    0x4F,0x51,0x90,0x66,0xE6,0x00,0x92,0x05,0x40,0x11,0x90,0x06,0x3A,0xD7,0xE2,0x90,
++    0x90,0x95,0x56,0x21,0x92,0x06,0x38,0x57,0x01,0x01,0x80,0x64,0xC0,0xB4,0x42,0x09,
++    0x88,0xF6,0x03,0x01,0x80,0x7C,0x01,0x01,0x81,0x74,0xC9,0x7C,0x42,0xB5,0x01,0x48,
++    0xC2,0x40,0x80,0x14,0xC1,0x74,0xC9,0x7C,0x02,0x00,0xC4,0x00,0x91,0x05,0x86,0x4C,
++    0xCA,0x74,0xC1,0x14,0xE0,0x2A,0x6A,0x09,0xC1,0x26,0xC0,0x64,0xE6,0x00,0x92,0x05,
++    0x87,0x64,0x01,0x8F,0xC0,0x74,0x41,0x09,0x89,0x16,0xC0,0x7C,0x47,0x01,0x88,0xC6,
++    0x08,0x81,0x41,0x45,0x83,0x17,0xC0,0x77,0xC0,0x6C,0x82,0x3C,0xC0,0x74,0x82,0x34,
++    0xC0,0x5C,0x82,0x0C,0xC0,0x64,0x82,0x04,0xC4,0x7C,0xE1,0x00,0x3C,0x00,0x7C,0x00,
++    0x50,0x5A,0xB4,0xA2,0xE8,0x98,0xB0,0xCA,0x31,0x62,0x74,0x45,0xB1,0x8A,0xC1,0x7C,
++    0xB0,0x82,0x80,0x24,0xC0,0x7C,0xB1,0xC2,0x81,0x1C,0xD0,0x7C,0xB0,0x82,0x85,0x14,
++    0xC0,0x74,0x41,0x09,0x88,0x5E,0xC0,0x24,0x12,0x02,0x92,0x05,0x80,0x24,0xC0,0x1C,
++    0x12,0x02,0x92,0x05,0x80,0x1C,0xC0,0x14,0x12,0x02,0x92,0x05,0x80,0x14,0x00,0x01,
++    0x83,0x2C,0xE0,0x68,0xAD,0xF4,0x01,0x9F,0x40,0x61,0x98,0x66,0xC8,0x24,0xC0,0x34,
++    0xD2,0x4C,0xD1,0x00,0x4C,0x9D,0xA1,0x42,0xC8,0x1C,0xC0,0x3C,0xD2,0x4C,0xD1,0x00,
++    0x4C,0x85,0xA1,0x42,0x00,0x47,0x15,0x01,0xDC,0x0C,0x00,0x28,0xF0,0xD2,0x5C,0x45,
++    0x88,0xD2,0x12,0x01,0x90,0x6C,0xD1,0x3C,0x92,0x95,0x92,0x0C,0xD2,0x34,0x90,0x95,
++    0x91,0x04,0xD2,0x6C,0x50,0x09,0x88,0x3E,0x12,0x12,0x93,0xA5,0x32,0x12,0x13,0x92,
++    0x94,0x95,0x32,0xA2,0x12,0x4A,0x92,0x4D,0xD2,0x0C,0xDA,0x04,0xF0,0x0C,0x00,0x07,
++    0x01,0xEF,0xB4,0x1C,0xF1,0x04,0xB0,0x5C,0x01,0x70,0xB2,0xFC,0x22,0x12,0x93,0x95,
++    0xCA,0xD8,0x90,0xDD,0xF9,0x1C,0xF1,0xFC,0xC9,0xB0,0xB7,0x1C,0xF3,0x5C,0xC1,0xB0,
++    0xB0,0x5C,0x51,0x01,0xD9,0xBE,0xF0,0xCC,0x10,0x92,0xD5,0xA6,0x58,0x01,0xD8,0x96,
++    0xF5,0xC4,0x11,0x9A,0xD1,0x7E,0xF8,0x1C,0x35,0x01,0xF8,0xF2,0xF9,0x5C,0xC1,0xFB,
++    0x48,0xF8,0x8D,0x46,0xFD,0xD4,0x11,0xF2,0xE8,0x2E,0x78,0x45,0xCD,0xFA,0xCB,0xF0,
++    0x7B,0x45,0x88,0xF2,0x39,0xD7,0xD6,0x6C,0xE6,0x90,0x92,0x95,0x91,0x6C,0xD1,0x6C,
++    0x55,0x11,0x98,0xF6,0x41,0x01,0x80,0xF6,0xF2,0x10,0xF2,0x4C,0x00,0x90,0x5C,0x45,
++    0xC7,0xD2,0xD4,0xB3,0xCC,0xDA,0xCA,0xB0,0x11,0xF2,0x94,0x86,0xD0,0x2C,0x50,0x09,
++    0x88,0x8E,0xD1,0x24,0xC1,0x34,0xD8,0x4C,0xD1,0x00,0x54,0x9D,0xA0,0x82,0xDE,0x1C,
++    0xD1,0x3C,0xE8,0x4C,0xD1,0x90,0x5E,0x85,0xA8,0xD2,0xEA,0x14,0xDA,0x04,0xD8,0xE8,
++    0x36,0x1A,0xD3,0x90,0x90,0x95,0xDA,0x00,0x93,0x1D,0xD2,0x40,0x2C,0x01,0x38,0x01,
++    0x50,0x01,0xD8,0x56,0xF5,0xCC,0x11,0x92,0xD0,0x3E,0x58,0x01,0xD9,0x2E,0xF0,0xC4,
++    0x10,0x9A,0xD5,0x16,0xC1,0x33,0x18,0xF2,0x83,0x33,0x20,0x12,0x90,0x95,0xCA,0xD8,
++    0x92,0xDD,0xC2,0x00,0xE7,0x68,0x93,0x6D,0x6F,0x11,0xC8,0x4E,0x04,0xE7,0x10,0x9A,
++    0x90,0x0E,0x10,0x09,0x90,0x2C,0xD8,0x24,0xD6,0x34,0xC0,0x90,0x90,0x95,0x96,0x34,
++    0xD8,0x1C,0xD0,0x3C,0xC6,0x90,0x96,0x95,0x90,0x3C,0xD0,0x14,0xDA,0x0C,0x00,0x90,
++    0xC0,0x90,0x96,0x0C,0xD8,0x14,0xD0,0x04,0xC0,0x90,0x96,0x04,0xE6,0x00,0x92,0x05,
++    0xD4,0xF4,0x11,0x82,0x92,0x06,0x38,0x3F,0xC2,0x74,0xE1,0x00,0x91,0x05,0x86,0x74,
++    0xC0,0x74,0x41,0x11,0x97,0x06,0x30,0xAF,0xC2,0x7C,0xE1,0x00,0x91,0x05,0x86,0x7C,
++    0xC0,0x7C,0x41,0x21,0x97,0x06,0x30,0x37,0x00,0x0F,0x00,0x41,0x81,0x64,0xC1,0x64,
++    0x41,0x41,0x88,0xD6,0x10,0x01,0x00,0x01,0x58,0x8A,0xE8,0xC8,0xB4,0xF2,0xB4,0x7A,
++    0x31,0x8A,0x31,0xDA,0x40,0x09,0x88,0x1E,0x12,0x4A,0x92,0x4D,0x12,0xDA,0x92,0xDD,
++    0xE7,0x6C,0xC2,0x18,0x92,0xDD,0xE2,0x74,0xC2,0x08,0x93,0x65,0x04,0x08,0xC4,0x48,
++    0x90,0x4D,0x5E,0x01,0xD9,0x76,0xE8,0xCC,0x10,0x5A,0xD5,0x5E,0x60,0x01,0xD8,0x4E,
++    0xED,0xC4,0x11,0x62,0xD1,0x36,0x68,0x9D,0xA1,0x62,0x63,0x85,0xA0,0x1A,0x03,0x3F,
++    0x70,0xD2,0x05,0x00,0x62,0x9D,0xD9,0x74,0xA1,0x1A,0x63,0x85,0xDB,0x6C,0xA2,0x1A,
++    0xE6,0x00,0x92,0x05,0x46,0x11,0x98,0x9E,0xE6,0x90,0x92,0x95,0x56,0x21,0x98,0x56,
++    0x58,0x85,0xD9,0xC3,0xA8,0xC3,0xC0,0xC3,0x90,0xC3,0x00,0x01,0x81,0xFC,0x58,0x85,
++    0xD8,0xC3,0xA8,0xC3,0xC0,0xC3,0x90,0xC3,0x00,0x01,0x80,0xE4,0x30,0x3A,0x80,0xEC,
++    0xC4,0xAC,0xCA,0x03,0x80,0xD4,0x01,0x01,0x0E,0x01,0x00,0x18,0x54,0xA5,0xC0,0xD0,
++    0x32,0xA2,0x04,0x20,0xC6,0x10,0x93,0x95,0x6D,0x9D,0xE1,0x72,0x33,0x2A,0xA3,0x72,
++    0x6D,0x85,0xE1,0x6A,0x32,0x12,0xC3,0x90,0x8A,0xAB,0xE0,0x48,0x90,0x4D,0x4E,0x19,
++    0x98,0x86,0x47,0x09,0x80,0x0E,0x40,0x19,0x88,0x66,0x60,0xA5,0xE3,0x0A,0x37,0x12,
++    0xCB,0x93,0x30,0x2A,0xC7,0x6B,0xA5,0x2A,0x34,0x1A,0xCB,0xE3,0x8C,0xE3,0x80,0xCB,
++    0x34,0x0A,0x8B,0x53,0x09,0x09,0x88,0x0C,0x09,0x01,0x88,0x74,0xD3,0x74,0x31,0x0A,
++    0xE1,0x4A,0xDC,0x74,0x36,0x12,0xC3,0x90,0xCA,0x9B,0xC0,0xAB,0xC9,0x93,0x92,0x14,
++    0xD0,0x74,0x51,0x01,0x88,0x16,0x41,0x01,0x80,0x0E,0x40,0x19,0x8D,0x5E,0x10,0x4A,
++    0x98,0x4E,0x10,0x09,0x90,0x04,0x41,0x01,0x8A,0x16,0xF0,0x10,0x90,0x0C,0x01,0xF7,
++    0x11,0x09,0x90,0x0C,0x00,0xDF,0x40,0x09,0x80,0x0E,0x40,0x11,0x8D,0x5E,0x10,0x4A,
++    0xC0,0x4E,0x10,0x09,0x90,0x04,0x41,0x09,0x8C,0x16,0xF0,0x10,0x90,0x0C,0x01,0x77,
++    0x11,0x09,0x90,0x0C,0x00,0x5F,0x10,0x01,0x90,0x04,0x01,0x47,0x11,0x09,0x90,0x04,
++    0x40,0x11,0x90,0x16,0xF1,0x90,0x94,0x0C,0x00,0x0F,0x10,0x09,0x90,0x0C,0x41,0x01,
++    0x80,0x0E,0x40,0x19,0x8D,0x0E,0x10,0x4A,0x90,0x2E,0x40,0x09,0x80,0x0E,0x40,0x11,
++    0x8D,0x26,0x10,0x4A,0xC0,0x16,0x10,0x09,0x94,0x54,0x01,0x8F,0x11,0x01,0x90,0x54,
++    0x01,0x77,0xF4,0xC4,0x33,0x12,0x19,0x92,0xF1,0xA4,0x92,0xE4,0xC9,0x90,0xF4,0xEC,
++    0xC9,0x90,0x94,0x5C,0xD0,0x5C,0xC1,0x93,0x92,0xDC,0x31,0x90,0xA1,0xCE,0xD1,0xE4,
++    0xF2,0xA4,0x02,0x90,0xC9,0x90,0xF4,0x3C,0x04,0xB0,0xCB,0x90,0x35,0x39,0x09,0xB0,
++    0xC8,0xB0,0x14,0xE1,0xF1,0x92,0xF5,0xD4,0x10,0x92,0xD5,0x26,0xF0,0x64,0x71,0x41,
++    0x88,0xB6,0x50,0x01,0xD9,0xA6,0xF0,0xDC,0x48,0xB0,0x87,0x06,0x80,0x90,0xF2,0xE4,
++    0xC0,0xB0,0xB5,0xE4,0xF2,0x3C,0x19,0xB2,0xC8,0xB8,0xF7,0xEC,0x1C,0x12,0xCB,0x90,
++    0x90,0xEC,0xD0,0xFC,0xE4,0x90,0x92,0x95,0x91,0xFC,0xD0,0xDC,0x48,0x90,0x8E,0xEE,
++    0xD0,0x4C,0xF2,0xF4,0xD5,0x93,0x12,0x92,0xC1,0x2E,0xD0,0xDC,0x31,0x01,0x1E,0x92,
++    0xF1,0x5C,0x81,0x93,0x01,0x47,0xD0,0xDC,0x31,0x01,0x1A,0x92,0xF1,0x5C,0x81,0x93,
++    0x01,0x17,0xD0,0x04,0x50,0x09,0x80,0x4E,0xD0,0x04,0x51,0x09,0x8A,0x36,0xD0,0x6C,
++    0x10,0xA2,0x84,0x1E,0xD5,0x0C,0xC1,0x10,0x95,0xA5,0x3A,0x57,0x10,0x4A,0x8D,0xDE,
++    0xD4,0x14,0x11,0x9A,0x89,0xC6,0xC8,0x74,0xE6,0x48,0x92,0x4D,0x89,0x74,0xC9,0x74,
++    0x48,0x11,0x90,0x06,0x3A,0x97,0xE2,0x00,0x90,0x05,0x46,0x21,0x91,0x06,0x38,0x1F,
++    0xC6,0x34,0xCA,0x03,0x42,0x01,0x88,0x5E,0xC9,0xAC,0x8A,0x01,0xE0,0x43,0x36,0x10,
++    0xAA,0x36,0x31,0x00,0x71,0x00,0x04,0x27,0xD0,0x54,0x51,0x01,0x8D,0x5E,0x10,0x4A,
++    0xCA,0x16,0xF0,0x48,0x90,0x4D,0x06,0x1F,0x10,0x4A,0x95,0x0E,0xE6,0x48,0x92,0x4D,
++    0x11,0x09,0x90,0x54,0x01,0x67,0xD0,0x14,0x10,0x9A,0xCC,0x16,0xF6,0xD8,0x92,0xDD,
++    0x01,0x27,0xD0,0x14,0x10,0x9A,0x94,0x0E,0xE6,0xD8,0x92,0xDD,0x11,0x01,0x90,0x54,
++    0x91,0x55,0x92,0x3C,0x97,0xE5,0x72,0xFA,0xD4,0x3C,0xC9,0x90,0x93,0xEC,0x39,0x47,
++    0x02,0x01,0xD0,0xAC,0x6C,0x94,0x16,0x12,0x9A,0xD6,0xC0,0xAC,0xE8,0x4B,0x70,0x04,
++    0x10,0x42,0x9C,0x26,0xC4,0x4C,0xD2,0x03,0xF6,0x00,0x94,0x05,0x02,0x1F,0xC0,0x4C,
++    0xD4,0x03,0xE4,0x00,0x90,0x05,0xCE,0xFC,0x10,0x0A,0x9C,0x4E,0xC0,0xAC,0x0A,0x01,
++    0xBA,0x0B,0xC0,0x54,0x08,0xD9,0xC7,0x03,0x02,0x42,0xC8,0x54,0x82,0x43,0x28,0x37,
++    0x27,0x01,0x28,0xF9,0xA8,0x09,0x60,0x01,0x8A,0x56,0xC0,0x44,0xC8,0xC4,0xB9,0x9C,
++    0xD2,0x34,0x4A,0x93,0x92,0x94,0xD0,0x74,0x5A,0x3A,0x07,0x90,0xF0,0xF2,0x04,0x57,
++    0xC1,0x3C,0xCA,0xCC,0xD0,0xEC,0x90,0x9C,0xD4,0x34,0x4A,0x93,0x92,0x94,0xD0,0x6C,
++    0x5A,0x12,0x07,0x90,0xF0,0xF2,0x44,0x01,0x82,0x16,0xF0,0x48,0x10,0x42,0x8C,0x8E,
++    0xD0,0x74,0x92,0x04,0x91,0x05,0x36,0x0A,0xDA,0x6C,0xD2,0x5C,0xBC,0xEF,0xD7,0x37,
++    0x35,0x4A,0x11,0x42,0xE8,0x0E,0x30,0x42,0x00,0x17,0x40,0x01,0xD0,0x06,0x00,0x01,
++    0xC8,0x30,0x04,0x07,0xB0,0x01,0xC4,0x9C,0xC8,0xE4,0x10,0x00,0x86,0x0F,0xE8,0x27,
++    0xCC,0x94,0xC8,0x00,0x18,0x42,0x42,0x01,0xD0,0x06,0x00,0x01,0xA0,0x00,0x60,0x01,
++    0x8A,0x7E,0xC8,0x34,0x54,0x4C,0x10,0x0A,0xD0,0x06,0x30,0x42,0xC8,0xAC,0x12,0x31,
++    0xFA,0x4B,0x18,0x8A,0xD4,0xA4,0xC2,0x48,0x14,0xC9,0x09,0x90,0xC2,0x48,0x04,0x44,
++    0x02,0x77,0xC8,0x34,0x54,0x4C,0x12,0x0A,0xD0,0x06,0x30,0x42,0xC8,0xAC,0x12,0x31,
++    0xFA,0x4B,0x18,0x8A,0xD4,0xA4,0xC2,0x48,0x14,0xC9,0x09,0x90,0xC4,0x48,0x04,0x44,
++    0xE7,0x20,0x93,0x25,0x64,0x09,0xC8,0xF6,0xC0,0xAC,0x12,0x31,0xE0,0x0B,0xC2,0xE4,
++    0x02,0x42,0xCE,0xAC,0xFA,0x4B,0x18,0x8A,0xD4,0xA4,0xC2,0x48,0x14,0xC9,0x09,0x90,
++    0xC6,0x48,0x04,0x44,0xC2,0xAC,0xCA,0x74,0xFA,0x03,0x00,0x10,0xC0,0xA4,0xC2,0x90,
++    0x02,0x89,0x0B,0x00,0xC4,0x90,0xA8,0x8B,0xCA,0xAC,0xD2,0x6C,0xFA,0x4B,0x00,0x58,
++    0xCA,0xA4,0xC2,0xC8,0xC6,0x40,0xA8,0x13,0xC2,0xAC,0xCA,0xAC,0xFA,0x03,0xE0,0x00,
++    0xBD,0x43,0x20,0xE7,0xAC,0xFD,0x87,0xBD,0xEC,0x04,0x31,0xA2,0xD8,0x43,0x87,0x84,
++    0xD8,0x43,0x85,0x7C,0xC8,0x43,0x81,0x74,0x00,0x01,0x80,0x54,0x42,0x22,0x45,0x0B,
++    0x36,0x42,0x81,0x01,0x80,0xB4,0x48,0x01,0x80,0x1E,0xC0,0x74,0x40,0x00,0x82,0x5C,
++    0x00,0x67,0xC0,0xB4,0xC8,0x03,0x46,0x51,0x98,0x26,0xC8,0xB4,0x00,0x49,0xB0,0x42,
++    0x80,0x5C,0x00,0x1F,0xC0,0xB4,0x08,0x41,0xB0,0x0A,0x8A,0x5C,0x40,0xCA,0xD4,0xD4,
++    0xC8,0xBC,0xC0,0x80,0x80,0xAC,0x48,0x01,0x84,0xF6,0x49,0xBA,0xC2,0xD4,0xC0,0x08,
++    0x10,0x49,0xC5,0xD4,0x04,0x90,0xC4,0x18,0xE0,0xAC,0xC0,0x74,0x42,0x00,0x12,0x02,
++    0x90,0x05,0x82,0x54,0x30,0x01,0x00,0x7F,0x00,0x01,0x00,0x47,0x40,0x7C,0x40,0xD4,
++    0xD1,0xD0,0x05,0x14,0xE4,0x20,0xE5,0x48,0xE2,0xD8,0xE4,0x00,0x90,0x05,0xD6,0x7C,
++    0x17,0x82,0x9C,0x9E,0xE7,0xB0,0x93,0xB5,0xC4,0x84,0x10,0x32,0x9B,0x66,0x37,0x02,
++    0x40,0x01,0x80,0x06,0x3C,0x02,0x4C,0x2A,0xC2,0xD4,0xC0,0x18,0x48,0x1A,0xC4,0xD4,
++    0x8A,0xC1,0xC1,0x00,0x50,0x0A,0xCC,0xD4,0x94,0x81,0xC3,0x48,0x10,0x01,0x00,0x47,
++    0x40,0x24,0x40,0x74,0xD8,0x20,0x05,0xE4,0xE4,0xD8,0xE4,0x00,0xE2,0x48,0xE4,0x90,
++    0x90,0x95,0xE6,0x7C,0x17,0x12,0x9D,0x9E,0x48,0x92,0xC3,0xD4,0xC0,0x00,0x82,0x4C,
++    0xE0,0xAC,0x00,0x01,0x81,0x8C,0x30,0x42,0x80,0x01,0x81,0xA4,0x80,0x01,0x86,0x9C,
++    0x08,0x97,0x32,0x01,0x08,0x47,0xC2,0x4C,0xC4,0x03,0x48,0x00,0x89,0xF6,0xF3,0x02,
++    0xCC,0x74,0x10,0x42,0xD8,0xD6,0xC3,0x7C,0x32,0x5A,0x03,0x00,0xD0,0x08,0x31,0x52,
++    0xD6,0x01,0x59,0x94,0x10,0xD4,0x40,0x54,0x12,0xD4,0x42,0x4C,0x11,0xCC,0x34,0x0A,
++    0xCE,0x01,0x59,0x4C,0x11,0xCC,0x46,0x0C,0x1B,0xCC,0x40,0x0C,0x18,0xCC,0xCA,0x08,
++    0x31,0x52,0xD0,0x01,0x5C,0x94,0x1E,0xD4,0xD6,0x02,0x19,0xC4,0x40,0x44,0x22,0xC4,
++    0x40,0x25,0x70,0x01,0x88,0x26,0x08,0x01,0x16,0xCC,0x10,0xCC,0x18,0xCC,0x04,0x47,
++    0xCA,0x7C,0xF0,0x48,0x10,0x72,0x8C,0x26,0x0B,0x01,0x30,0x5A,0x12,0xCC,0x1C,0xCC,
++    0x20,0xCC,0xC8,0x8C,0x48,0x01,0x88,0x26,0x30,0x5A,0x13,0xCC,0x14,0xCC,0x12,0xCC,
++    0x00,0x4F,0xC8,0x84,0xD2,0x8C,0xF0,0x48,0x10,0x52,0x8C,0x26,0x0B,0x01,0x30,0x5A,
++    0x1E,0xCC,0x1C,0xCC,0x20,0xCC,0x10,0x01,0xF3,0x12,0x35,0x5A,0x0A,0x81,0xF0,0xCA,
++    0x11,0x8A,0xD4,0x9E,0x0A,0x91,0xF0,0xCA,0x17,0x8A,0xD4,0xD6,0x0A,0xA1,0xF0,0xCA,
++    0x17,0x8A,0xD4,0xB6,0x0A,0xB1,0xF0,0xCA,0x17,0x8A,0xD4,0x96,0x0A,0xD1,0xF0,0xCA,
++    0x11,0x8A,0xE4,0x1E,0x0A,0xE1,0xF0,0xCA,0x17,0x8A,0xE4,0xD6,0x0A,0xF1,0xF0,0xCA,
++    0x17,0x8A,0xE4,0xB6,0x0A,0x01,0xF1,0xCA,0x17,0x8A,0xE4,0x96,0x0A,0xD1,0xEC,0x4A,
++    0x4B,0x01,0x80,0xCE,0x08,0x01,0x88,0x6C,0x30,0x72,0x8C,0x1C,0x88,0x64,0xD8,0xBC,
++    0x5A,0x01,0x88,0x1E,0x32,0xE2,0xFC,0x78,0x1E,0x01,0xF0,0x1A,0x10,0xDA,0xD5,0x46,
++    0xC0,0xC8,0x92,0x4D,0xDA,0x1C,0xE0,0xD8,0x90,0xDD,0x06,0x07,0x00,0xF7,0x9D,0x1C,
++    0x00,0x2F,0x58,0x51,0xEB,0x1E,0x30,0x9A,0xE6,0xD8,0x92,0xDD,0x34,0xF2,0xE4,0x00,
++    0x32,0x1A,0xE3,0xD8,0x94,0xDD,0x36,0xE2,0x30,0x1A,0x5B,0x49,0x9A,0x26,0xC7,0x80,
++    0x90,0x05,0xD0,0xA4,0x70,0x4C,0xE9,0x93,0x10,0x8A,0x9C,0xB6,0xCC,0x5C,0x10,0x42,
++    0xD3,0x9E,0x30,0x8A,0x48,0x39,0x98,0x36,0xCA,0x5C,0x80,0x48,0x10,0x0A,0xDC,0x66,
++    0xC0,0x1C,0x40,0x01,0x88,0x4E,0xC0,0xB4,0xC8,0x03,0x46,0x11,0x98,0x0E,0x00,0x09,
++    0x80,0x6C,0x48,0xDA,0xC2,0x43,0xE2,0x00,0x80,0x43,0x4A,0xCA,0xC0,0x43,0x40,0x81,
++    0x90,0x26,0x52,0xC2,0xA2,0xB2,0xE0,0x00,0x81,0x43,0x00,0xFF,0x34,0xB2,0x84,0x98,
++    0xC0,0x98,0x96,0xDD,0x98,0x14,0x18,0x01,0x30,0xE2,0xDC,0x54,0x80,0xD8,0x9A,0x94,
++    0x1E,0x01,0xF0,0x1A,0xFD,0x94,0x10,0xDA,0xD3,0x56,0x30,0xBA,0xC9,0xF8,0x96,0xFD,
++    0x30,0xF2,0xFD,0x54,0x10,0xDA,0xD5,0x1E,0x86,0xB8,0xCA,0xB8,0x90,0xFD,0xB9,0x14,
++    0xC0,0xC8,0x02,0x97,0x60,0x20,0x02,0x00,0x70,0xB2,0x04,0x00,0x70,0xB2,0x02,0x00,
++    0x80,0x40,0x07,0x01,0x48,0xE0,0x06,0x00,0x28,0x60,0x00,0x00,0x68,0x70,0x04,0x00,
++    0x00,0xC0,0x00,0x01,0x80,0xC0,0x06,0x01,0x00,0xF7,0x90,0x4D,0xE3,0x00,0x34,0x1A,
++    0xE6,0xD8,0x92,0xDD,0x33,0xE2,0x34,0x1A,0x5E,0x49,0x98,0x8E,0xC4,0x14,0x10,0x0A,
++    0xD8,0x16,0xC8,0x5C,0x28,0x72,0xD4,0x0E,0x00,0x09,0x80,0x6C,0xC6,0xB4,0xC8,0x03,
++    0x40,0x51,0x98,0x16,0xC0,0xBC,0x40,0x01,0x80,0x46,0xC8,0x6C,0x00,0x09,0x48,0x01,
++    0x80,0x06,0x00,0x01,0x80,0x64,0x00,0x0F,0x00,0x09,0x80,0x64,0xC0,0x64,0x40,0x01,
++    0x80,0xA6,0x01,0x09,0xBC,0x43,0x43,0x3A,0x40,0x03,0x42,0x01,0x88,0x5E,0xC0,0xB4,
++    0xC8,0x03,0x46,0x51,0x90,0x3E,0xC0,0xA4,0x6E,0x4C,0xE7,0x03,0x32,0x00,0x72,0x00,
++    0x84,0x51,0x10,0x0A,0xC8,0x0E,0x10,0x01,0x00,0x07,0x10,0x09,0xC0,0xC4,0x40,0x01,
++    0x80,0x06,0x10,0x11,0xC0,0xD4,0x90,0x14,0x81,0x04,0x30,0x9A,0xA9,0x0C,0x30,0x02,
++    0xD0,0x8C,0xC8,0x4C,0xBA,0xFF,0xD7,0x37,0xC0,0x9C,0xC0,0x03,0x38,0x00,0xAA,0x1E,
++    0xFF,0x43,0xF9,0x4B,0x10,0x42,0x9C,0x4E,0xC0,0x9C,0xC0,0x03,0x38,0x00,0xA2,0x1E,
++    0x05,0x01,0xA8,0x43,0xCC,0x9C,0x80,0x43,0x87,0xDD,0xE8,0x85,0xE0,0x20,0xC5,0x4C,
++    0xE0,0x00,0x82,0x4C,0xE7,0xB0,0x93,0xB5,0xC4,0x7C,0x10,0x32,0x95,0x06,0x30,0x97,
++    0xC2,0x8C,0xE0,0x00,0x90,0x05,0x86,0x8C,0xC8,0x84,0xC0,0x8C,0x10,0x42,0x94,0x06,
++    0x37,0x3F,0x3D,0x4F,0xAC,0x9D,0x87,0x0D,0xD8,0x43,0x80,0x04,0xDB,0x63,0x52,0x12,
++    0xC4,0x0C,0xC0,0x28,0x50,0x02,0xC3,0x0C,0xD4,0xC1,0xC1,0x30,0xE8,0x43,0x0C,0xF1,
++    0x84,0x0F,0xD8,0x97,0x49,0xE9,0x88,0x0E,0x48,0xE2,0xC2,0x0C,0xC5,0x10,0x0A,0x49,
++    0xC4,0x0C,0x00,0x48,0xC0,0x08,0x1A,0x01,0x00,0x5F,0x00,0x01,0x00,0x2F,0x40,0x7C,
++    0x04,0xBC,0xE0,0x90,0xE2,0x48,0xE4,0x00,0x95,0x05,0x16,0x02,0x9A,0xBE,0xE7,0xD8,
++    0x90,0xDD,0xC6,0x04,0x17,0x1A,0x9C,0x86,0x00,0x01,0x00,0x2F,0x41,0x8C,0x01,0x4C,
++    0xE5,0x68,0xE5,0xB0,0xE6,0x00,0x92,0x05,0x17,0x02,0x9D,0xBE,0x48,0x62,0xC2,0x0C,
++    0xC0,0x00,0x12,0x01,0x00,0x67,0x08,0x01,0x00,0x37,0xC0,0x1B,0x34,0xD8,0x74,0xD8,
++    0x82,0x1B,0xE0,0x00,0xE6,0x48,0x92,0x4D,0x17,0x0A,0x9D,0xB6,0xE6,0x90,0x92,0x95,
++    0xCC,0x04,0x10,0x52,0x9F,0x7E,0xEF,0xF5,0xAC,0xFD,0x87,0x1D,0x30,0x6A,0x30,0x01,
++    0xBB,0x73,0xB9,0x73,0x37,0x42,0x81,0x01,0xC7,0x0B,0x10,0xE9,0x02,0x52,0x38,0x48,
++    0x7A,0x48,0x06,0x48,0x18,0x52,0x80,0x13,0xC7,0x0B,0x10,0xD9,0x00,0x8A,0x80,0x0B,
++    0x34,0x42,0x81,0x01,0x84,0x14,0xF0,0x03,0x78,0xB2,0x41,0x01,0x80,0x4E,0x00,0x01,
++    0x57,0xAA,0x09,0xF9,0xA2,0x8A,0xE0,0x00,0x90,0x05,0x46,0x81,0x99,0xD6,0x87,0xF3,
++    0x80,0xF3,0xAB,0x04,0x00,0x01,0xD8,0x1C,0xD0,0x34,0xC8,0x2C,0xBD,0xFF,0xEF,0xD7,
++    0x36,0x62,0xA1,0x01,0xC8,0x03,0x47,0x51,0x98,0x36,0xA8,0x04,0x00,0x09,0xD8,0x1C,
++    0xD0,0x34,0xC8,0x2C,0xBD,0xFF,0xEF,0x77,0xC4,0x14,0xF0,0x0B,0x49,0x01,0x80,0xD6,
++    0x00,0x01,0x48,0x09,0x8B,0x5E,0xC0,0xD3,0x50,0x01,0x80,0x46,0x50,0x1A,0xC1,0x93,
++    0x50,0x01,0x88,0x26,0x50,0x12,0xC1,0x93,0x50,0x01,0x88,0x06,0x00,0x09,0x40,0x01,
++    0x87,0x2E,0xC8,0x13,0x50,0x01,0x95,0x36,0xE7,0x90,0x8A,0x13,0x07,0x1F,0xC8,0x13,
++    0x50,0x51,0x90,0x06,0x8F,0x33,0xCF,0x13,0x50,0x51,0x98,0xE6,0x40,0x01,0x88,0x6E,
++    0x48,0x09,0x88,0x16,0xF7,0x90,0x8A,0x13,0x01,0x47,0x00,0x99,0xEF,0x02,0x6A,0x4C,
++    0x34,0x00,0x72,0x00,0x10,0x0A,0x94,0x0E,0xF7,0x90,0x8A,0x13,0xC0,0xC3,0x43,0x11,
++    0x9D,0x16,0x00,0x01,0x88,0x03,0x07,0x37,0x40,0x09,0x88,0x26,0xCA,0x03,0x47,0x81,
++    0x93,0x0E,0x00,0x21,0x89,0x03,0x37,0x4A,0xC7,0x1C,0xB8,0xFF,0xF8,0xDF,0x81,0x3D,
++    0xE8,0x85,0x07,0x00,0x80,0x40,0x07,0x01,0x68,0xF0,0x07,0x00,0x28,0x60,0x00,0x00,
++    0x60,0x20,0x02,0x00,0x00,0xC0,0x00,0x01,0x80,0xC0,0x06,0x01,0x00,0x40,0x00,0x01,
++    0x00,0x48,0x00,0x01,0xAC,0xFD,0x87,0x3D,0xE0,0x84,0x30,0xB2,0x00,0x01,0x80,0x2C,
++    0xD8,0x83,0x83,0x1C,0x60,0x8C,0x89,0x14,0xCA,0x44,0x18,0x0A,0x50,0xFA,0xC7,0x3C,
++    0xC0,0x00,0xC4,0x48,0x8F,0x34,0x40,0xF2,0xC0,0x03,0x40,0x09,0x89,0x0E,0xE0,0x83,
++    0x80,0x1C,0x00,0x01,0x10,0x01,0x00,0x1F,0x82,0x53,0xE0,0x48,0xE6,0x00,0x92,0x05,
++    0xDC,0x1C,0x10,0xC2,0x98,0xC6,0x0F,0x01,0x00,0x09,0xD8,0x54,0xD0,0x44,0x80,0x07,
++    0xD0,0xAF,0x2E,0x01,0x60,0x01,0x88,0x0E,0xE7,0x68,0x93,0x6D,0xF8,0x34,0x08,0x01,
++    0x01,0x5F,0xC0,0xC3,0x1E,0x02,0x91,0x05,0x80,0xC3,0xD1,0x8C,0x10,0x82,0xCC,0x0E,
++    0x19,0x02,0x85,0xC3,0xE2,0xF8,0xE3,0x48,0x90,0x4D,0xC6,0x1C,0x17,0x0A,0x9C,0x86,
++    0x48,0x42,0xC7,0x3C,0xC0,0x00,0x82,0x24,0xD0,0x54,0x90,0x04,0x30,0x9A,0x01,0x11,
++    0xD0,0x3C,0xC8,0x44,0x80,0x07,0xD8,0x47,0xD0,0x54,0x90,0x04,0x04,0x41,0xEA,0x0A,
++    0x00,0x01,0x1C,0x0A,0x30,0x9A,0x11,0x01,0xC0,0x24,0x80,0x07,0xF6,0x27,0x05,0x29,
++    0xE8,0x02,0x44,0x31,0x88,0x16,0x00,0x01,0x87,0x5D,0xE8,0x85,0xC1,0x1C,0xD0,0xC0,
++    0x09,0x01,0x00,0x3F,0xD0,0x24,0x18,0x01,0xF0,0x9A,0xD6,0x14,0xD0,0xD0,0x94,0x95,
++    0x68,0x01,0x88,0x2E,0x50,0xC1,0xE8,0xBE,0xC5,0x13,0x18,0x12,0x80,0x13,0x00,0x9F,
++    0x50,0x99,0xE8,0x2E,0xC0,0x13,0x50,0x01,0x82,0x16,0xF0,0x90,0x80,0x13,0x00,0x5F,
++    0x68,0x29,0x88,0x4E,0x58,0xE1,0xEE,0x3E,0xC0,0x13,0x50,0x01,0x88,0x26,0xD0,0x2C,
++    0x50,0x01,0x88,0x0E,0x10,0x09,0x90,0x2C,0xD4,0x24,0xE0,0x90,0x92,0x24,0xE0,0x00,
++    0xE6,0x48,0x92,0x4D,0xD4,0x1C,0x10,0x8A,0x9B,0xA6,0x46,0x20,0x6C,0x21,0xC8,0xCE,
++    0xD0,0x54,0x90,0x04,0x30,0x9A,0x09,0x01,0x00,0x19,0xD0,0x3C,0x85,0x07,0xD0,0xE7,
++    0x08,0x09,0x30,0x42,0xD8,0x54,0xD0,0x44,0x83,0x07,0xD0,0x07,0xC5,0x2C,0x38,0xDF,
++    0xAC,0xFD,0x87,0x1D,0xF0,0x64,0x30,0x7A,0x33,0xEA,0xD8,0xC3,0x85,0x14,0x48,0xAA,
++    0xC2,0x1C,0xC0,0x20,0x40,0x92,0xC5,0x03,0x40,0x09,0x88,0x0E,0xE0,0xC3,0x81,0x14,
++    0x08,0x01,0x00,0x09,0xD8,0x2C,0xD0,0x6C,0x82,0x07,0xD0,0x47,0xD0,0x2C,0x90,0x04,
++    0x30,0xDA,0x01,0x11,0xD0,0x1C,0xC8,0x6C,0x84,0x07,0xD0,0xB7,0xD0,0x2C,0x90,0x04,
++    0x06,0x41,0xEA,0x0A,0x00,0x01,0x1C,0x0A,0x30,0xDA,0x11,0x01,0x30,0x02,0x81,0x07,
++    0xF0,0x97,0xD1,0x2C,0x91,0x04,0x30,0xDA,0x08,0x01,0x00,0x19,0xD0,0x1C,0x80,0x07,
++    0xD0,0x1F,0x0C,0x09,0x30,0x42,0xD8,0x2C,0xD0,0x6C,0x80,0x07,0xD4,0x3F,0x41,0xF2,
++    0x00,0x44,0x01,0x01,0x00,0x84,0x09,0x01,0x00,0x77,0x00,0x01,0xF0,0x02,0x11,0x01,
++    0xF4,0x52,0x15,0x12,0xE9,0x06,0x00,0x44,0x15,0x01,0xF0,0x92,0x10,0x12,0xD4,0x06,
++    0x05,0x84,0xE1,0x20,0xE6,0x48,0x92,0x4D,0xC4,0x14,0x10,0x0A,0x98,0x6E,0x87,0x3D,
++    0xEF,0x85,0xAF,0xBD,0x80,0x55,0xC4,0x5C,0xD8,0x03,0x86,0x24,0xCA,0x5C,0xD8,0x4B,
++    0x8C,0x1C,0x50,0x52,0xCC,0x54,0xC0,0x48,0x8C,0x4C,0x48,0x4A,0xC0,0x4B,0x48,0x09,
++    0x88,0x46,0xC8,0x24,0xE6,0x48,0x92,0x4D,0x88,0x24,0x80,0x3C,0xC0,0x5C,0xE0,0x03,
++    0x80,0x1C,0x00,0x0F,0x00,0x01,0x80,0x3C,0xF8,0x3C,0xC0,0x5C,0x80,0x01,0x86,0x44,
++    0x04,0x7F,0x4B,0x12,0x04,0x01,0x00,0x43,0xC0,0x5C,0xC8,0x4C,0xDB,0x03,0x1A,0xC2,
++    0xC0,0x08,0x02,0x01,0x10,0xF9,0x01,0x1F,0x82,0x53,0xE0,0x48,0xE6,0x00,0x92,0x05,
++    0xDC,0x1C,0x10,0xC2,0x9C,0xC6,0x27,0x01,0x31,0x2A,0x31,0x32,0x03,0xE7,0x40,0xC2,
++    0x08,0x23,0x4E,0x2D,0xB8,0x0C,0x88,0x04,0x40,0x55,0x40,0x3E,0x5F,0x35,0xB8,0xFF,
++    0xF8,0x7F,0xC3,0x44,0xC8,0x03,0x42,0x31,0x83,0x7E,0x33,0x5A,0x00,0xC1,0xF0,0xC2,
++    0x40,0xE1,0xD1,0x1E,0x68,0x41,0x80,0x4E,0x18,0x62,0x05,0x1F,0x70,0x01,0x8C,0x0E,
++    0x30,0x72,0x01,0x1F,0x41,0x68,0x1B,0x62,0x6F,0x01,0x88,0x06,0xC0,0x5C,0xC8,0x4C,
++    0xDB,0x03,0x1A,0xC2,0xC0,0x08,0x02,0x01,0x10,0x01,0x00,0x1F,0x82,0x53,0xE0,0x48,
++    0xE6,0x00,0x92,0x05,0xDC,0x1C,0x10,0xC2,0x99,0xC6,0x37,0xAA,0x20,0x01,0x00,0x0F,
++    0x1B,0xA2,0x41,0xB0,0x77,0x01,0x88,0xDE,0xC0,0x5C,0x60,0x04,0xC0,0x41,0x91,0x35,
++    0x05,0xAF,0x18,0x62,0x46,0xD2,0x0A,0x23,0x48,0x2D,0xB8,0x0C,0x88,0x04,0x40,0x55,
++    0x40,0x3E,0x58,0x35,0xB9,0xFF,0xFF,0xA7,0xC2,0x44,0xC8,0x03,0x42,0x31,0x80,0x6E,
++    0x30,0x5A,0x03,0xA1,0xF5,0xC2,0x10,0x82,0xE9,0x06,0x18,0x62,0x40,0x68,0x6B,0x01,
++    0x88,0x3E,0xC7,0x54,0x0E,0x59,0xCB,0x00,0x0A,0x48,0xC2,0x00,0xB3,0x23,0xE0,0xF8,
++    0x90,0xFD,0xC7,0x24,0x14,0x3A,0x9C,0x66,0xF1,0x3C,0x00,0xA7,0xC3,0x54,0x08,0x59,
++    0xCA,0x00,0x0C,0x48,0xC1,0x38,0xF2,0xC3,0x40,0x01,0x88,0x0E,0x01,0x09,0xB0,0xC3,
++    0xF0,0xE3,0x29,0x01,0x01,0x01,0x00,0x0F,0xE7,0x68,0x93,0x6D,0x40,0x09,0x88,0x1E,
++    0x60,0xF9,0x97,0x0E,0xE5,0x20,0x93,0x25,0x48,0xE2,0x01,0x01,0x00,0x43,0xAC,0x48,
++    0x46,0xDA,0x09,0x23,0x20,0x00,0x67,0x10,0x00,0x0F,0x00,0xBF,0x40,0x48,0x32,0x82,
++    0x17,0x42,0x80,0xDE,0x48,0x01,0xC9,0x06,0x08,0x01,0x89,0x04,0x90,0x0C,0x40,0x55,
++    0x41,0x6E,0x30,0x8A,0xBA,0xFF,0xF7,0x77,0x40,0x01,0x80,0x0E,0x6E,0x29,0x98,0xDE,
++    0xB3,0xE3,0xE1,0xB0,0x90,0xB5,0xC7,0x24,0x16,0x32,0x9C,0x3E,0x87,0x6D,0xE8,0x85,
++    0xAC,0xBD,0x87,0x15,0x30,0x62,0x30,0xB2,0x48,0x2A,0x01,0x01,0x81,0x43,0x40,0x4A,
++    0x40,0x0B,0x10,0x11,0x18,0x8A,0x00,0x0B,0x28,0x01,0x00,0x3F,0x09,0x09,0x30,0x9A,
++    0x30,0x52,0x31,0x42,0x81,0x07,0xC8,0x57,0xE7,0x68,0x93,0x6D,0xDD,0x03,0x11,0x42,
++    0xC1,0xA6,0x37,0x12,0x30,0x8A,0x01,0x11,0x84,0x07,0xC0,0x2F,0x31,0x92,0x31,0x0A,
++    0xC7,0x14,0xB8,0xFF,0xF9,0x77,0x30,0x12,0x30,0x8A,0x01,0x01,0x83,0x07,0xC0,0xDF,
++    0xE0,0x03,0x41,0x01,0x80,0xBE,0x69,0xB2,0x44,0x43,0x97,0x3D,0x4F,0x04,0x01,0x43,
++    0x40,0x7A,0x08,0x09,0x81,0x0B,0x30,0x12,0x30,0x8A,0x01,0x11,0x83,0x07,0xC0,0x5F,
++    0x30,0x1A,0xB1,0x04,0x08,0x01,0x00,0x09,0xD0,0x14,0x80,0x07,0xC8,0xAF,0xB2,0x04,
++    0xD9,0x0B,0x37,0x1A,0x00,0x11,0xD0,0x14,0x82,0x07,0xC8,0x77,0x31,0x92,0x31,0x0A,
++    0xC7,0x14,0xB8,0xFF,0xF1,0x37,0x37,0x12,0x30,0x8A,0x01,0x6F,0x60,0x20,0x02,0x00,
++    0x00,0xD0,0x00,0x01,0x48,0xE0,0x06,0x00,0xF8,0xFB,0x07,0x00,0x10,0x00,0x00,0x42,
++    0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0x00,0x01,0x80,0x07,0xC0,0x27,0x42,0x5A,
++    0x08,0x01,0x80,0x0B,0x01,0x7B,0x37,0x1A,0xB0,0x04,0x08,0x01,0x00,0x11,0xD0,0x14,
++    0x81,0x07,0xC8,0x57,0x31,0x12,0x31,0x8A,0x00,0x11,0x80,0x07,0xC0,0xA7,0x51,0x22,
++    0x40,0x83,0x08,0x11,0x18,0x42,0x04,0x83,0x87,0x2D,0xE8,0x85,0x00,0xD0,0x00,0x01,
++    0x18,0x00,0x04,0x42,0xA8,0x85,0x31,0x12,0x92,0x01,0x46,0x8C,0x80,0x01,0xC7,0x1B,
++    0x32,0xD8,0x72,0xD8,0x87,0x1B,0x58,0xE2,0x41,0xE3,0x30,0x20,0xA2,0x16,0x40,0xE3,
++    0x3F,0x20,0xAB,0xE6,0x58,0xCA,0x27,0x41,0x00,0xE3,0x44,0xE3,0x28,0xF9,0xAF,0x19,
++    0x18,0x62,0x01,0xE3,0xC7,0x23,0x48,0x20,0x8A,0x1E,0xF0,0x48,0x20,0x48,0x60,0x48,
++    0x88,0xC6,0x4F,0x01,0x88,0x36,0x40,0xC3,0x08,0x81,0x18,0x42,0x07,0xC3,0x00,0xF9,
++    0x82,0x89,0x04,0x84,0xEF,0x85,0xA9,0x85,0x46,0x63,0x42,0x5B,0xDF,0xAB,0x72,0x62,
++    0xC0,0xB3,0x71,0x09,0x8E,0x16,0x48,0x63,0x50,0x5B,0xE2,0xAB,0x41,0x01,0x88,0x0E,
++    0x10,0x01,0x00,0xE7,0x40,0x03,0x31,0x32,0xB5,0x41,0x30,0xA2,0xE8,0x08,0x30,0x42,
++    0xC4,0x01,0x5A,0x33,0xC1,0xFB,0x18,0xF2,0x1E,0x33,0x5C,0x33,0xC5,0xFB,0x18,0xF2,
++    0x1B,0x33,0x36,0x32,0x40,0x83,0xC1,0xF3,0x1B,0x82,0x35,0x32,0x00,0x83,0x41,0x73,
++    0xC4,0xC3,0x18,0x32,0x01,0x73,0xE8,0x20,0xE2,0xD8,0xE2,0x90,0x95,0x95,0x16,0x52,
++    0x9F,0x06,0xEF,0x85,0x41,0x09,0x88,0x0E,0x10,0x01,0x00,0xE7,0x40,0x03,0x31,0x32,
++    0xB5,0x41,0x30,0xA2,0xE8,0x08,0x30,0x42,0xC4,0x01,0x5A,0x33,0xC5,0xFB,0x18,0xF2,
++    0x1E,0x33,0x5C,0x33,0xC5,0xFB,0x18,0xF2,0x1B,0x33,0x36,0x32,0x40,0x83,0xC1,0xF3,
++    0x1B,0x82,0x35,0x32,0x00,0x83,0x41,0x73,0xC0,0xC3,0x18,0x32,0x01,0x73,0xE8,0x20,
++    0xE2,0xD8,0xE2,0x90,0x95,0x95,0x16,0x52,0x9F,0x06,0xEF,0x85,0x41,0x11,0x88,0x0E,
++    0x10,0x01,0x00,0xE7,0x40,0x03,0x31,0x32,0xB5,0x41,0x30,0xA2,0xE8,0x08,0x30,0x42,
++    0xC4,0x01,0x5A,0x33,0xC5,0xFB,0x18,0xF2,0x1E,0x33,0x5C,0x33,0xC5,0xFB,0x18,0xF2,
++    0x1B,0x33,0x36,0x32,0x40,0x83,0xC1,0xF3,0x1B,0x82,0x31,0x32,0x00,0x83,0x41,0x73,
++    0xC4,0xC3,0x18,0x32,0x01,0x73,0xE8,0x20,0xE2,0xD8,0xE2,0x90,0x95,0x95,0x16,0x52,
++    0x9F,0x06,0xEF,0x85,0x47,0x19,0x88,0xE6,0x10,0x01,0x00,0xE7,0x40,0x03,0x31,0x32,
++    0xB5,0x41,0x30,0xA2,0xE8,0x08,0x30,0x42,0xC4,0x01,0x5A,0x33,0xC5,0xFB,0x18,0xF2,
++    0x1E,0x33,0x5C,0x33,0xC5,0xFB,0x18,0xF2,0x1B,0x33,0x36,0x32,0x40,0x83,0xC1,0xF3,
++    0x1B,0x82,0x31,0x32,0x00,0x83,0x41,0x73,0xC0,0xC3,0x18,0x32,0x01,0x73,0xE8,0x20,
++    0xE2,0xD8,0xE2,0x90,0x95,0x95,0x16,0x52,0x9F,0x06,0xEF,0x85,0xAA,0x85,0x47,0xE3,
++    0x05,0xB0,0xCC,0x20,0x45,0xEB,0xC6,0x68,0x40,0x09,0x88,0x26,0x45,0xE3,0xC8,0x20,
++    0x44,0xDB,0xC4,0xE8,0x04,0x3F,0x78,0xD2,0xC0,0xFB,0x79,0x09,0x8E,0x1E,0x48,0xE3,
++    0xCA,0x20,0x55,0xDB,0xC1,0xE8,0x44,0x13,0xF9,0xA0,0xC0,0x5B,0x40,0x09,0x88,0x76,
++    0x48,0x01,0x88,0x66,0x44,0x83,0x1A,0xC2,0x04,0x83,0x42,0x83,0x1C,0xC2,0x04,0x83,
++    0x44,0x03,0x19,0xC2,0x00,0x03,0x41,0x83,0x18,0xC2,0x00,0x83,0xE8,0x85,0x4F,0x09,
++    0x8A,0x66,0x40,0x83,0x1A,0xC2,0x04,0x83,0x44,0x83,0x1C,0xC2,0x00,0x83,0x44,0x83,
++    0x18,0xC2,0x04,0x83,0x40,0x03,0x19,0xC2,0x07,0x03,0xE9,0x85,0x48,0x11,0x88,0x66,
++    0x44,0x03,0x19,0xC2,0x00,0x03,0x41,0x83,0x18,0xC2,0x04,0x83,0x40,0x83,0x1A,0xC2,
++    0x04,0x83,0x42,0x83,0x1C,0xC2,0x04,0x83,0xE8,0x85,0x4F,0x19,0x89,0xE6,0x47,0x03,
++    0x19,0xC2,0x04,0x03,0x44,0x83,0x18,0xC2,0x02,0x83,0x40,0x83,0x1A,0xC2,0x04,0x83,
++    0x40,0x83,0x1C,0xC2,0x07,0x83,0xEC,0x85,0xA8,0xFD,0xF7,0x4C,0x30,0x62,0x2C,0x01,
++    0x4D,0x93,0x49,0x8B,0x32,0x72,0xDC,0xE3,0x33,0x3A,0x49,0x8A,0xC0,0x4B,0x48,0x09,
++    0x89,0x0E,0x50,0x93,0xE0,0xE3,0x40,0x19,0x80,0x96,0x31,0x79,0x49,0x5A,0x13,0xB0,
++    0x40,0x11,0x88,0xB6,0x32,0x02,0x1B,0x3A,0x58,0x52,0xC3,0x14,0xC1,0x00,0xC6,0xC0,
++    0x33,0x9A,0x33,0x2A,0xEA,0xDA,0x0A,0x5B,0x08,0x01,0x00,0x3F,0xC1,0x1B,0x18,0x9A,
++    0x41,0xAB,0x00,0x5B,0xEA,0x90,0xE0,0x00,0xE6,0x48,0x92,0x4D,0x17,0x0A,0x9D,0xAE,
++    0xE8,0xFD,0x47,0x01,0x88,0x8E,0x18,0x01,0x12,0x5B,0x46,0xDA,0x45,0x33,0x40,0xB0,
++    0x00,0xB0,0x05,0x33,0x00,0x1B,0x02,0x5B,0x40,0x0B,0x18,0x81,0x18,0xCA,0x04,0x0B,
++    0x44,0x0B,0x18,0x01,0x18,0xCA,0x00,0x0B,0x00,0x17,0x40,0x09,0x89,0x06,0x30,0xAA,
++    0x00,0x01,0x00,0x27,0x40,0x8B,0x00,0x6B,0xEA,0x90,0xE0,0x00,0x95,0x05,0x16,0x02,
++    0x9F,0xC6,0xEF,0xFD,0x3B,0x82,0xAB,0x85,0x4A,0xA3,0xD8,0xEB,0x33,0x70,0x72,0xB0,
++    0x48,0x5A,0xC2,0x4B,0x48,0x09,0x88,0x0E,0x50,0xA3,0xE0,0xEB,0x08,0x01,0x00,0x3F,
++    0x42,0x13,0x41,0x93,0x00,0x92,0x07,0x14,0xEC,0x20,0xE1,0x00,0xE6,0x48,0x92,0x4D,
++    0x17,0x4A,0x9D,0xAE,0xEB,0x85,0xAB,0xC5,0x30,0x2A,0x30,0xB2,0x61,0xF2,0x41,0x03,
++    0x14,0x01,0x1C,0x82,0x01,0x03,0x41,0x03,0x10,0x81,0x18,0x82,0x01,0x03,0x41,0x03,
++    0x10,0x09,0x18,0x82,0x07,0x03,0xE1,0x53,0x00,0xF9,0x87,0x81,0x19,0x12,0x40,0xBA,
++    0x10,0x13,0x16,0x99,0x00,0x13,0x13,0x41,0x04,0x13,0x14,0xD9,0xE8,0x92,0x52,0x01,
++    0x80,0x16,0x10,0xC9,0x00,0x13,0x00,0x0F,0x10,0x89,0x00,0x13,0x31,0x52,0x30,0x5A,
++    0x08,0x01,0x00,0x09,0xB7,0x04,0xB8,0xFF,0xF9,0x7F,0x33,0x52,0x30,0x8A,0x01,0x11,
++    0xBB,0xFF,0xF7,0xCF,0x42,0x03,0x3B,0x00,0xAB,0xE6,0xEF,0xC5,0xAC,0x9D,0x87,0x8D,
++    0xCA,0x94,0xC8,0x4B,0x88,0x84,0xE0,0x94,0xA7,0x01,0xD2,0x1B,0xD8,0x0B,0x89,0x04,
++    0xCA,0x94,0xD8,0x6B,0x30,0x0A,0x88,0x71,0x30,0x62,0xCC,0x94,0x30,0x01,0xE8,0x4B,
++    0x48,0x09,0x88,0x56,0x08,0x01,0x00,0x27,0xC5,0x38,0x9A,0xF3,0xA2,0x32,0xE2,0x48,
++    0x90,0x4D,0xD2,0x94,0xDC,0x93,0x12,0x52,0xE0,0xB6,0x57,0xDA,0x04,0xB3,0x02,0xB3,
++    0x00,0xB3,0x0E,0x01,0x18,0x4A,0x06,0x8B,0xCA,0x94,0xD8,0x4B,0xB0,0x8B,0x08,0x01,
++    0x50,0xAA,0x30,0x01,0x05,0x78,0xC4,0xF8,0x0A,0xF3,0xC1,0x90,0xB2,0xB3,0xE2,0x48,
++    0x90,0x4D,0x4A,0x11,0xD8,0xA6,0xCF,0x94,0xE8,0x4B,0x48,0x29,0xCD,0xF6,0x03,0x48,
++    0xC3,0x48,0x00,0x50,0xC0,0x70,0x54,0x6A,0xC0,0xB0,0xB5,0x14,0xC0,0x48,0x8C,0x0C,
++    0x30,0x12,0x33,0x32,0xB0,0xE1,0x08,0x01,0x88,0x34,0x48,0x4A,0x88,0x6C,0x88,0x64,
++    0x30,0x32,0x04,0x01,0x32,0x22,0x04,0x97,0x18,0x00,0x04,0x42,0x00,0x01,0x00,0x42,
++    0x00,0xD0,0x00,0x01,0x60,0x20,0x02,0x00,0x80,0x40,0x07,0x01,0x48,0xE0,0x06,0x00,
++    0x78,0xF8,0x07,0x00,0xC8,0x14,0x00,0x01,0xF0,0x42,0xF8,0x0C,0x0B,0x01,0xF0,0xCA,
++    0x32,0x7A,0xD0,0x08,0x97,0x4D,0x48,0xF9,0xEF,0x06,0x08,0xF9,0xCB,0x38,0x86,0xF8,
++    0x78,0xF9,0xEF,0x06,0x3B,0xF9,0x37,0x82,0x82,0x3B,0xE0,0x00,0x30,0x32,0xC4,0xBB,
++    0x10,0xFA,0x9C,0x46,0x10,0xCA,0xDC,0x36,0x46,0x84,0xD9,0x48,0xC0,0x00,0x92,0x05,
++    0x04,0x84,0x81,0x08,0x04,0x37,0x10,0xCA,0xDC,0x16,0x00,0x78,0x00,0xBC,0x01,0x0F,
++    0x39,0x01,0x00,0xBC,0x10,0xCA,0xDC,0x0E,0x38,0x09,0xB8,0x34,0x43,0x78,0x2B,0x3A,
++    0xE8,0x26,0xF8,0x6C,0x10,0x7A,0xEC,0x2E,0x88,0x6C,0x00,0x1F,0xFC,0x64,0x10,0x7A,
++    0xE8,0x06,0x88,0x64,0x82,0x8B,0xE0,0x90,0xE0,0xB0,0xC5,0x14,0xE0,0x00,0x84,0x14,
++    0xC4,0x0C,0xE0,0x00,0x83,0x0C,0x30,0x02,0xE2,0x00,0x92,0x05,0x35,0x22,0x2C,0x62,
++    0xD8,0xC6,0xC5,0x34,0x40,0x01,0x80,0x8E,0x08,0x01,0x00,0x01,0x80,0x5C,0xC0,0x04,
++    0xC2,0x00,0x46,0x00,0x80,0x7C,0xC0,0x04,0x30,0x00,0x72,0x00,0x80,0x74,0x00,0x01,
++    0x30,0x22,0x84,0x2C,0x80,0x24,0x80,0x1C,0xF0,0x90,0x02,0x07,0x03,0x1F,0xF5,0x40,
++    0x94,0x05,0x32,0x32,0x03,0xFF,0x31,0x02,0x04,0x00,0x32,0x22,0xC2,0x2C,0x00,0x00,
++    0x80,0x2C,0xC0,0x24,0x00,0x00,0x82,0x24,0xC2,0x1C,0x00,0x00,0x83,0x1C,0x40,0x40,
++    0x28,0x82,0xEB,0x26,0xC0,0x83,0xF0,0x6C,0xD8,0x00,0x84,0x83,0x00,0x1F,0xC0,0x83,
++    0xF4,0x64,0xD8,0x00,0x80,0x83,0xC0,0x83,0x73,0x3D,0x30,0xBA,0xA8,0x82,0xC7,0x83,
++    0x10,0xC2,0xDC,0xDE,0xE2,0x48,0x92,0x4D,0xF1,0x5C,0xC0,0xB0,0x90,0xB5,0xB1,0x5C,
++    0x30,0x32,0x3B,0x09,0x1D,0xF2,0x31,0xA2,0xF5,0x7C,0x10,0x82,0xD8,0x76,0xF0,0x2C,
++    0x18,0xF2,0xB1,0x2C,0xF5,0x04,0x10,0x82,0xD8,0x46,0xF0,0x24,0x18,0xF2,0xB1,0x24,
++    0xF5,0x74,0x10,0x82,0xD8,0x16,0xC0,0x1C,0x18,0xC2,0x81,0x1C,0xF3,0x90,0x32,0x82,
++    0xF2,0x00,0x92,0x05,0x33,0x32,0x34,0x82,0x45,0x01,0xD0,0xE6,0x42,0xE2,0xB7,0x0B,
++    0xD0,0x50,0xB3,0x13,0x36,0x12,0x1B,0x92,0x03,0x13,0x30,0x12,0x08,0x13,0xD0,0x2C,
++    0x00,0x13,0xD2,0x24,0x00,0x13,0xD4,0x1C,0x00,0x13,0x36,0x01,0x00,0xA7,0xC1,0x5C,
++    0x86,0x07,0xE8,0xA7,0x90,0x05,0x80,0x5C,0x4D,0x8A,0x07,0x80,0xC0,0x00,0x4A,0x13,
++    0x40,0x3D,0x08,0x01,0x1C,0x01,0x30,0xF2,0x30,0xE2,0x04,0xCF,0x38,0x98,0x86,0x7E,
++    0xC0,0x1B,0xF8,0x5C,0xD8,0xD8,0x96,0xDD,0x58,0x01,0xE8,0x36,0x83,0x1B,0x20,0x9A,
++    0x94,0xDD,0x36,0xF2,0xE2,0x48,0x92,0x4D,0x00,0x27,0x18,0x01,0x80,0x1B,0x00,0x0F,
++    0x18,0x01,0x80,0x1B,0x42,0x90,0xE2,0x00,0x32,0x1A,0xE3,0xD8,0x94,0xDD,0x32,0xE2,
++    0x2F,0x62,0xDD,0x1E,0xE3,0xB0,0x93,0xB5,0x30,0x82,0x83,0x5C,0x45,0xE2,0x06,0x98,
++    0xC0,0xD8,0x08,0xD3,0xCA,0x00,0xB4,0x0B,0x48,0x21,0xD8,0x0E,0x76,0x09,0xD8,0x36,
++    0x06,0x01,0x50,0xBA,0x04,0x08,0xC4,0x58,0xE4,0x08,0x02,0x70,0xC0,0xB0,0x4D,0xEB,
++    0x4D,0xB3,0x19,0xAA,0x08,0xEB,0xC0,0x80,0xF4,0x1B,0xF2,0x2B,0xDA,0xD8,0xB2,0x1B,
++    0x90,0x45,0x42,0x09,0xD8,0x76,0x07,0x09,0xA6,0x03,0x43,0x6A,0x0E,0x19,0x40,0x13,
++    0x50,0x01,0x80,0x16,0x03,0x29,0xA0,0x0B,0x04,0xF7,0x40,0x13,0x50,0x01,0x80,0x16,
++    0x03,0x21,0xA0,0x0B,0x02,0xC7,0x40,0x0B,0x48,0x01,0x80,0x1E,0x00,0x19,0x08,0x11,
++    0xA0,0x0B,0x03,0x8F,0x48,0x03,0x40,0x01,0x88,0x26,0xC0,0x94,0x86,0x01,0xCE,0x03,
++    0x40,0x51,0x98,0x0E,0x00,0x11,0x00,0x3F,0xC1,0x94,0x80,0x01,0xE0,0x03,0x44,0x01,
++    0x80,0x0E,0x00,0x11,0x00,0x07,0x00,0x09,0xE4,0x0B,0xE3,0x50,0xA3,0x13,0xDD,0x13,
++    0x38,0x90,0xA2,0x0E,0xF3,0x48,0xA2,0x0B,0xE8,0x0B,0x13,0x29,0x10,0x0A,0x94,0x0E,
++    0xA8,0x13,0x01,0xEF,0x10,0x0A,0xCC,0x46,0x40,0x09,0x88,0x16,0x09,0x81,0xAF,0x0B,
++    0x00,0xB7,0xD0,0x48,0x01,0x52,0xAC,0x13,0x00,0x97,0x40,0x19,0xC8,0x0E,0x08,0x19,
++    0x02,0x07,0x90,0x0D,0xE8,0x13,0x51,0x01,0x82,0x16,0xF0,0x90,0xA8,0x13,0x01,0x3F,
++    0xD2,0x94,0xF0,0x48,0xCA,0x93,0x1C,0x52,0xCA,0x84,0xC0,0x88,0xD0,0x94,0x88,0x8B,
++    0xA8,0x03,0x83,0x9D,0xEF,0x85,0xAF,0xBD,0x80,0x6D,0x34,0x6A,0xD9,0x63,0x33,0x42,
++    0x80,0x01,0x82,0x64,0xD0,0x03,0x84,0x3C,0xC2,0x64,0xD8,0x03,0x30,0x00,0xA8,0x1E,
++    0x02,0xD9,0xEC,0x02,0x40,0x01,0x80,0xA6,0xC5,0x6C,0x00,0x08,0xC3,0x40,0x00,0x08,
++    0x52,0xC2,0xC4,0x08,0xC4,0x48,0xC4,0x10,0x00,0x01,0x18,0x01,0x00,0x2F,0x00,0x5C,
++    0x04,0x9C,0xE0,0x48,0xE2,0x90,0xE4,0x00,0x95,0x05,0x12,0x02,0xD8,0xBE,0x87,0x85,
++    0xEB,0x85,0x07,0x59,0xCA,0x6C,0x08,0x00,0xC4,0x40,0x70,0x7A,0xF7,0x03,0x08,0x83,
++    0xD0,0x7C,0x90,0x04,0x30,0x5A,0x09,0x01,0x00,0x11,0xD0,0x6C,0xBB,0xFF,0xEF,0xE7,
++    0x42,0x4A,0x84,0x01,0x43,0x0B,0x30,0x5A,0x09,0xCC,0x5C,0x8B,0x0B,0xCC,0x5E,0x8B,
++    0x15,0xCC,0x58,0x8B,0x17,0xCC,0x42,0x8B,0x14,0xCC,0x4C,0x22,0x46,0x53,0x10,0xD4,
++    0x48,0x93,0x1F,0xD4,0x17,0x89,0x00,0x93,0x13,0x19,0x18,0x93,0x40,0x53,0x18,0x11,
++    0x18,0xD2,0x04,0x53,0x40,0x0B,0x18,0xCA,0x01,0x0B,0x30,0x42,0xE9,0x4B,0x81,0x01,
++    0x80,0x5C,0x48,0x09,0x8D,0x5E,0x6A,0x44,0x81,0x14,0x30,0x8A,0x5E,0x43,0x94,0x35,
++    0xB0,0x0C,0x00,0x01,0x80,0x04,0xD0,0x6C,0x4F,0x92,0x03,0x00,0xC2,0x00,0xC4,0x00,
++    0x83,0x54,0x40,0x8A,0x18,0x33,0x0A,0x01,0x37,0x42,0xB9,0xFF,0xE0,0x5F,0xF9,0x54,
++    0xC1,0x64,0x30,0x5A,0xD1,0x0B,0x32,0xC2,0xD7,0x7C,0xB8,0xFF,0xEB,0x67,0x4C,0x62,
++    0x10,0x01,0x00,0x01,0x02,0x67,0x00,0x18,0x37,0xE2,0xF4,0xDA,0x10,0x5A,0xD4,0x0E,
++    0x33,0x0A,0xD3,0xCA,0x10,0x9A,0xEC,0x0E,0x35,0x12,0xD3,0xD2,0xE2,0x00,0x92,0x05,
++    0x17,0x02,0xDD,0x86,0xC4,0x14,0xE0,0x00,0x10,0x0A,0x9C,0x36,0xC0,0x04,0x40,0x01,
++    0x8B,0x9E,0x40,0x80,0x40,0x08,0xC2,0x70,0x00,0x3F,0xC0,0x14,0xF4,0x00,0x14,0x12,
++    0xE0,0x5E,0x00,0x09,0x83,0x04,0xE0,0xB0,0x90,0xB5,0x77,0x01,0x80,0x16,0xC0,0x0C,
++    0x16,0x32,0x9C,0x36,0x70,0x01,0x88,0x06,0x30,0x09,0xC0,0x5C,0x90,0x33,0xC0,0x5C,
++    0xD2,0x0B,0x40,0x8A,0x18,0x0B,0x32,0x01,0x36,0x42,0x81,0x01,0x81,0x4C,0x80,0x01,
++    0x83,0x44,0x00,0x37,0xC4,0x3C,0x10,0x32,0xD0,0x6E,0xC0,0x44,0xC0,0x03,0xC8,0x44,
++    0x32,0x00,0x72,0x00,0x82,0x43,0x40,0x42,0x0C,0x41,0x00,0x0B,0x47,0x0B,0x10,0xF9,
++    0x90,0x21,0x18,0x8A,0x00,0x0B,0xC8,0x6C,0x02,0x00,0xC5,0x08,0x02,0x00,0x53,0x0A,
++    0xC4,0x40,0xC0,0x00,0xC0,0x48,0x74,0x01,0x88,0x66,0x10,0x01,0x78,0x02,0x02,0x37,
++    0x18,0x01,0x00,0x1C,0x04,0x7C,0xE0,0x00,0xE2,0x48,0xE4,0x90,0x95,0x95,0x12,0x12,
++    0xD9,0xB6,0x07,0x07,0xDF,0x6C,0x00,0x10,0xC1,0x90,0x5E,0xB2,0xC4,0x90,0x36,0xA2,
++    0x18,0x01,0x00,0x9F,0x30,0x3A,0x13,0x01,0xF0,0xD2,0x3D,0x01,0xFC,0x3A,0x16,0xBA,
++    0xD0,0x06,0x00,0x14,0x3E,0x01,0xF8,0x7A,0x10,0xBA,0xEC,0x06,0x04,0x54,0xE0,0x00,
++    0xE3,0x48,0x34,0x12,0xE4,0x90,0x34,0xA2,0xE2,0xD8,0x92,0xDD,0x17,0x1A,0xDD,0x4E,
++    0xC4,0x3C,0x10,0x32,0x80,0x06,0xC1,0x44,0xC6,0x03,0x48,0x00,0x88,0x1E,0xC0,0x4C,
++    0xC8,0x03,0x42,0x31,0x88,0xBE,0xC7,0x4C,0xC8,0x03,0x42,0x31,0x89,0x26,0x40,0x12,
++    0x40,0x0B,0x10,0x81,0x18,0x8A,0x00,0x0B,0xCF,0x6C,0x00,0x00,0xC0,0x00,0x4A,0xEA,
++    0xC0,0x00,0xCA,0x64,0x32,0x5A,0xD1,0x4B,0xD7,0x7C,0xB8,0xFF,0xE3,0x67,0xE7,0xB0,
++    0x90,0xB5,0xC3,0x3C,0x14,0x32,0xEC,0xAE,0x43,0xBA,0x30,0x5A,0x4A,0xCC,0x84,0x01,
++    0x00,0x0B,0x40,0xAA,0x48,0xCC,0x1E,0x0B,0x52,0xCC,0x18,0x0B,0x54,0xCC,0x1A,0x0B,
++    0x56,0xCC,0x04,0x0B,0x4E,0x8A,0x50,0xD4,0x00,0x53,0x58,0xCC,0x0F,0x0B,0x36,0xB7,
++    0xAA,0x85,0xD8,0xE3,0x1A,0x0A,0x03,0x48,0xC5,0x50,0x0C,0x49,0x02,0x48,0xC4,0x88,
++    0xE8,0xD3,0x50,0x11,0xC0,0x4E,0x10,0x01,0x00,0x2F,0x40,0x1C,0x04,0x5C,0xE0,0x48,
++    0xE2,0x00,0xE4,0x90,0x95,0x95,0x12,0x12,0xD8,0xBE,0x17,0x01,0x00,0x87,0x00,0x00,
++    0x80,0x40,0x07,0x01,0x48,0xE0,0x06,0x00,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,
++    0xF8,0xFB,0x07,0x00,0x40,0x1C,0x00,0x5C,0xE4,0x00,0xE4,0x48,0xE2,0x90,0x92,0x95,
++    0x17,0x12,0xDD,0xBE,0xEF,0x85,0xA8,0x85,0x30,0x6A,0xF0,0x2C,0x30,0x22,0x30,0x8A,
++    0x31,0xFA,0x30,0xC2,0xB9,0xFF,0xDF,0xB7,0x31,0xDA,0x31,0x92,0x31,0x4A,0x31,0x02,
++    0xBC,0xFF,0xE7,0xCF,0xE8,0x85,0x37,0x0A,0x8D,0x01,0x86,0x01,0x02,0x5F,0xC8,0x5B,
++    0x58,0x31,0x88,0x46,0x40,0xFA,0x47,0x0B,0x10,0x81,0x18,0x8A,0x00,0x0B,0x40,0x0B,
++    0x18,0x8A,0x00,0x0B,0x3E,0x82,0xCB,0x1B,0x5F,0x01,0x88,0x86,0x38,0x82,0xAB,0x85,
++    0xDA,0x5B,0xD8,0x4B,0x1F,0x5A,0x4A,0xC2,0xC7,0x08,0x52,0xC2,0xC0,0x00,0x14,0x01,
++    0x00,0x27,0x40,0x24,0x04,0x64,0xE0,0x00,0xE2,0x48,0xE4,0x90,0x17,0xD2,0x9C,0xC6,
++    0xEF,0x85,0xA8,0xBD,0x80,0x15,0x34,0x62,0x37,0xBA,0xD8,0x33,0xE8,0x03,0x09,0x01,
++    0x18,0x4A,0x2E,0x01,0x40,0x29,0x90,0x16,0x1F,0x0B,0x1D,0x2B,0x07,0x6F,0x00,0x09,
++    0xEA,0x02,0x38,0x00,0xAF,0x26,0x50,0x52,0x58,0x03,0x1F,0x82,0x18,0x03,0x05,0x27,
++    0x57,0x3A,0x5F,0x03,0x18,0x92,0x1E,0x82,0x1D,0x03,0x1D,0x0B,0x30,0x0A,0xC1,0x14,
++    0xBC,0xFF,0xE7,0xE7,0x25,0x2B,0x59,0x03,0x28,0x01,0x00,0x17,0x43,0x00,0xE2,0x68,
++    0x96,0x6D,0x3F,0x08,0x8D,0x0E,0x10,0xAA,0x9B,0xC6,0xAF,0x2B,0x73,0xCA,0x4E,0x04,
++    0x00,0x83,0xC7,0x14,0x0A,0x59,0xCB,0x00,0x0A,0x48,0xC2,0x00,0xF7,0x03,0x08,0x83,
++    0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,0xBC,0xFF,0xDF,0x87,0x30,0x1A,0xB9,0x04,
++    0x30,0x4A,0x01,0x11,0xD7,0x14,0xB8,0xFF,0xD8,0xFF,0x06,0x09,0xA7,0x01,0x8D,0x03,
++    0x48,0x82,0x46,0x43,0x10,0x11,0x18,0x82,0x00,0x43,0x00,0x41,0x01,0x83,0x45,0x83,
++    0x08,0xF9,0x8F,0x19,0x19,0x42,0x00,0x83,0x87,0x2D,0xE8,0x85,0x3F,0x82,0xAB,0xC5,
++    0xD8,0x53,0x90,0x04,0xDC,0x53,0x32,0xB2,0xE9,0x53,0x54,0x91,0x9E,0xBE,0x12,0x31,
++    0xE0,0x92,0x52,0x01,0x8E,0x9E,0x52,0x02,0xC0,0x28,0x34,0x12,0x91,0xE1,0x19,0xC1,
++    0x8E,0x01,0xF4,0x1A,0xE8,0x63,0x3A,0x11,0x10,0x1A,0xDD,0x16,0xD8,0xD8,0x38,0x1C,
++    0xA9,0x7B,0x1E,0xD1,0xEE,0x63,0xF4,0x1A,0x15,0x32,0x13,0x9A,0xE0,0x16,0xC8,0xD8,
++    0x38,0x1C,0xB2,0x7B,0x30,0x01,0x38,0x01,0x1C,0x01,0x30,0xE2,0x00,0x27,0x21,0x01,
++    0x00,0xE7,0x18,0x01,0xF0,0x5A,0x5F,0x01,0xED,0x4E,0x10,0x9A,0xE8,0x06,0x30,0xF2,
++    0xE8,0x5B,0x5E,0x01,0x80,0x76,0x40,0x9C,0xF0,0xD8,0x02,0x9C,0x00,0x57,0x58,0x01,
++    0xD5,0x46,0x10,0xDA,0xD0,0x06,0x30,0xFA,0xF0,0x5B,0x58,0x01,0x80,0x16,0x40,0x9C,
++    0xE0,0xD8,0x02,0x9C,0xE4,0x68,0xE5,0x90,0xE7,0x20,0x93,0x25,0x2F,0xA2,0x9B,0x06,
++    0x32,0x1A,0xE3,0xD8,0x94,0xDD,0x36,0xE2,0xE5,0x04,0x28,0x22,0x98,0xBE,0x7E,0x14,
++    0xC8,0x90,0x3C,0x14,0x7E,0x14,0xCA,0x90,0x3E,0x14,0xEA,0x43,0x40,0x01,0x80,0x0E,
++    0xF6,0x00,0xAA,0x43,0xF0,0x43,0x40,0x01,0x82,0x0E,0xF0,0x00,0xB7,0x43,0xE8,0xC5,
++    0xAC,0xBD,0x87,0x15,0x30,0x62,0x30,0xBA,0xEF,0x2B,0xDB,0x33,0xDB,0x03,0x1B,0x42,
++    0x00,0x08,0xC2,0x14,0xC4,0x40,0x48,0x8A,0xC0,0x00,0x82,0x0C,0x37,0x02,0x81,0x01,
++    0xC4,0x0B,0x10,0x01,0x18,0x8A,0x80,0x0B,0x00,0x21,0xEE,0x02,0x44,0x01,0x80,0x1E,
++    0x09,0x09,0x30,0xDA,0x30,0x52,0x31,0x42,0xBF,0xFF,0xD7,0xC7,0x30,0x1A,0xB9,0x04,
++    0x08,0x01,0x00,0x19,0xD7,0x14,0xB8,0xFF,0xDA,0x3F,0x02,0x41,0xE9,0x0A,0x30,0x1A,
++    0x30,0xD2,0xC1,0x0C,0xBC,0xFF,0xDF,0x7F,0x31,0x1A,0x31,0x4A,0xD0,0x14,0xC0,0x0C,
++    0xBD,0xFF,0xF7,0xB7,0x50,0x02,0x1C,0x09,0xC0,0x83,0x40,0x01,0x8B,0x5E,0xE0,0x68,
++    0x95,0x6D,0x5F,0x0B,0x03,0x0F,0xE0,0x68,0x90,0x6D,0x37,0xC2,0x00,0x42,0x15,0x0A,
++    0x8D,0x0E,0x10,0xAA,0x99,0xBE,0x37,0x82,0x74,0x92,0x13,0x2A,0x93,0xE6,0xA8,0x2B,
++    0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,0xBE,0xFF,0xD7,0x47,0x30,0x1A,0xB9,0x04,
++    0x30,0x4A,0x01,0x11,0xD7,0x14,0xB8,0xFF,0xD8,0xBF,0xC0,0x14,0x0A,0x59,0xCB,0x00,
++    0x0A,0x48,0xC2,0x00,0xF7,0x03,0x08,0x83,0x05,0x41,0x00,0x83,0x47,0x83,0x09,0xF9,
++    0x88,0x19,0x18,0x42,0x01,0x83,0x39,0xBF,0xE1,0x0B,0x31,0x02,0x80,0x01,0x4D,0x01,
++    0x86,0x1E,0xC9,0x0B,0x49,0x09,0x88,0x06,0x0E,0x11,0x88,0x0B,0xA8,0x2B,0x83,0x9B,
++    0x4F,0x04,0x01,0x83,0x50,0x0A,0xCB,0x14,0xDC,0x03,0xC1,0x48,0xE7,0x02,0x0A,0x83,
++    0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,0xBC,0xFF,0xD7,0xC7,0x30,0x1A,0xB9,0x04,
++    0x30,0x4A,0x01,0x11,0xD7,0x14,0xB8,0xFF,0xD0,0x3F,0x07,0x41,0x01,0x83,0x45,0x83,
++    0x08,0xF9,0x8F,0x19,0x19,0x42,0x00,0x83,0x38,0x77,0x08,0x01,0x88,0x0B,0x86,0x8B,
++    0x3F,0x57,0xA8,0x85,0x84,0x9D,0x34,0x22,0x33,0x6A,0xD8,0x73,0xD8,0x43,0x81,0x34,
++    0x31,0x12,0x93,0xE1,0x92,0x94,0x48,0x72,0x32,0x02,0xC3,0x18,0x4B,0x32,0x22,0x0A,
++    0x8B,0x8C,0xC8,0x43,0x00,0x00,0x82,0x1C,0x00,0x01,0x80,0x14,0x37,0x42,0x81,0x01,
++    0x82,0x84,0xC0,0x03,0x5C,0x7B,0x35,0x32,0x3F,0x20,0x5A,0x43,0x18,0x3A,0x60,0x01,
++    0xD1,0x46,0x40,0xFA,0x18,0x3A,0xB8,0x0C,0x37,0x82,0x23,0xD9,0x00,0x02,0xE1,0x84,
++    0x80,0x03,0x03,0x47,0x46,0xD2,0x19,0x02,0x18,0x3A,0xB8,0x0C,0x30,0x82,0x23,0x21,
++    0x18,0x02,0xE1,0x84,0x80,0x03,0x3B,0x01,0x19,0x7B,0x37,0x42,0x80,0x01,0x85,0x7C,
++    0xC0,0x03,0x84,0x54,0xC0,0x7C,0x20,0x09,0xB8,0x22,0xA0,0x4C,0x34,0x42,0x81,0x01,
++    0x86,0x74,0x18,0x3B,0xB8,0x44,0xC0,0x74,0x18,0x3B,0xBC,0x3C,0x31,0x42,0x81,0x01,
++    0x84,0x6C,0xA0,0x3B,0xCA,0x43,0x45,0x00,0x86,0x2C,0x00,0x01,0xFB,0x22,0x82,0x00,
++    0x81,0x24,0xE8,0x43,0x40,0x29,0xC0,0xBE,0x03,0x01,0x30,0x22,0x3B,0x04,0x39,0x04,
++    0x20,0x01,0x00,0x77,0x00,0x01,0x00,0x47,0x40,0x7C,0x00,0xFC,0x40,0x7C,0x00,0xBC,
++    0xE4,0x90,0xE4,0x48,0xE2,0xD8,0xE4,0x00,0x95,0x05,0x12,0x82,0xDB,0xA6,0xE7,0x20,
++    0x90,0x25,0xC3,0x34,0x17,0x22,0xDC,0x6E,0xF8,0x94,0xE0,0x8C,0x00,0x01,0x80,0x5C,
++    0x00,0xAF,0x05,0x01,0x34,0x32,0x34,0x22,0xC8,0x5C,0x00,0x09,0x00,0x42,0xCC,0x0C,
++    0x80,0x64,0x10,0x42,0x81,0x7E,0xE3,0x53,0x50,0x01,0x80,0x2E,0xC8,0x34,0xC0,0x5C,
++    0xF4,0x48,0x12,0x42,0x88,0x06,0x30,0xB2,0x1A,0x01,0x00,0x87,0x41,0xCC,0x41,0x14,
++    0xD0,0x40,0x94,0x15,0x00,0x14,0xC9,0x1C,0x10,0x52,0xD4,0x3E,0x32,0x02,0xE3,0x00,
++    0x94,0x05,0x36,0x22,0x34,0x82,0xC3,0x00,0x94,0x05,0x30,0x32,0xCC,0x2C,0x10,0x52,
++    0xE8,0x3E,0x01,0x7F,0x00,0x01,0x00,0x42,0x48,0xE0,0x06,0x00,0x38,0xA0,0x03,0x00,
++    0xAA,0xAA,0xAA,0xAA,0x18,0x00,0x04,0x42,0x00,0xD0,0x00,0x01,0x68,0xB8,0x03,0x00,
++    0x28,0x60,0x00,0x00,0xCC,0x4B,0x13,0x8A,0xE7,0x1E,0x58,0x43,0xC8,0x64,0x18,0x0A,
++    0x18,0x4B,0xCF,0x6C,0xE8,0x4B,0x4A,0x09,0x88,0x16,0xC8,0x6C,0x02,0x09,0xAC,0x43,
++    0xCC,0x54,0x10,0x52,0xE8,0xBE,0x08,0x09,0xD4,0x44,0x00,0xCA,0x18,0x8A,0x88,0x44,
++    0x00,0x8F,0xC8,0x24,0x10,0x52,0xD4,0x76,0xCA,0x6C,0xE8,0x4B,0x48,0x09,0x88,0x16,
++    0xCC,0x6C,0x00,0x09,0xA8,0x43,0xCA,0x4C,0x10,0x52,0xD4,0x26,0x08,0x09,0xD0,0x3C,
++    0x00,0xCA,0x1C,0x8A,0x8D,0x3C,0xE0,0x20,0xE2,0xF8,0xE5,0xD8,0x95,0xDD,0x12,0x9A,
++    0xD8,0x66,0xC5,0x7C,0xC8,0x03,0x44,0x01,0x83,0x2E,0x32,0x02,0x40,0x11,0xC8,0x2E,
++    0x33,0x0A,0x33,0x82,0x83,0x07,0xC8,0xD7,0x90,0x05,0x00,0x07,0x03,0x01,0x00,0x88,
++    0xD0,0x20,0x13,0x01,0x01,0x57,0x01,0x67,0x40,0x01,0xE8,0x7E,0x0B,0x01,0xF0,0x0A,
++    0xDC,0x1C,0x10,0xCA,0xD2,0xB6,0xE0,0x18,0x10,0xCA,0xEC,0x16,0xD1,0x48,0x00,0x0C,
++    0x00,0x87,0x48,0x01,0xE8,0x76,0x08,0x09,0x00,0x0C,0x01,0x5F,0x0B,0x01,0xF0,0x0A,
++    0x10,0x0A,0xD4,0x16,0xD1,0x48,0x00,0x0C,0x00,0x27,0x48,0x01,0xD0,0x16,0x08,0x01,
++    0x19,0x4A,0x06,0x0C,0x0B,0x01,0xF0,0x0A,0xDC,0x24,0x10,0xCA,0xD0,0x1E,0xC8,0x14,
++    0xE6,0x48,0x92,0x4D,0x8D,0x14,0xE0,0x20,0xE2,0x90,0x92,0x95,0x16,0x92,0xDD,0x9E,
++    0x00,0x4F,0x00,0x01,0x08,0x01,0x00,0x27,0x05,0x0C,0xE1,0x20,0xE2,0xF8,0xE5,0x00,
++    0x95,0x05,0x12,0x82,0xD8,0xC6,0xC7,0x5C,0xE2,0x00,0x92,0x05,0x80,0x5C,0xC8,0x34,
++    0xC4,0x5C,0x10,0x42,0xD2,0x06,0x38,0x27,0xC9,0x43,0x41,0x71,0xC9,0x0E,0x00,0x71,
++    0x88,0x43,0xC1,0x14,0xCC,0x4B,0x41,0x00,0xC6,0x40,0x90,0x05,0x8A,0x43,0x41,0x81,
++    0xCA,0x0E,0x00,0x81,0x88,0x43,0x01,0x01,0x29,0x44,0x37,0x44,0xC0,0x74,0xC8,0x44,
++    0x18,0x0B,0xCE,0x74,0xC4,0x3C,0x18,0x43,0x87,0x9D,0xE8,0x85,0xA8,0x85,0x33,0x2A,
++    0x30,0x62,0x30,0xB2,0x31,0x0A,0x31,0x42,0xBA,0xFF,0xEF,0xCF,0x48,0x6A,0x03,0x01,
++    0x81,0x43,0x30,0x92,0x31,0x0A,0x31,0x42,0xBB,0xFF,0xEF,0x1F,0xEE,0x03,0x41,0x41,
++    0x92,0x0E,0xE0,0x00,0xAB,0x03,0xE9,0x85,0x10,0x01,0x00,0x37,0x0A,0x01,0xE0,0x48,
++    0x90,0x4D,0x4C,0xA1,0xCA,0xDE,0xE7,0x90,0x94,0x95,0x14,0x12,0xCB,0xB6,0x3F,0x82,
++    0x38,0x18,0x78,0xD8,0x14,0x09,0x00,0xD2,0x97,0x95,0x1E,0xF9,0x08,0xD8,0x00,0xC2,
++    0x5E,0xEA,0xC2,0x00,0x48,0x09,0x88,0x66,0x44,0x0B,0x18,0x8A,0x02,0x0B,0x40,0x0B,
++    0x1A,0x8A,0x04,0x0B,0x44,0x0B,0x1C,0x8A,0x06,0x0B,0x44,0x0B,0x1E,0x8A,0x04,0x0B,
++    0x38,0x82,0x4B,0x01,0x8A,0x66,0x40,0x0B,0x1A,0x8A,0x04,0x0B,0x44,0x0B,0x1C,0x8A,
++    0x06,0x0B,0x44,0x0B,0x1E,0x8A,0x04,0x0B,0x40,0x0B,0x18,0x8A,0x03,0x0B,0x38,0x82,
++    0x48,0x11,0x88,0x66,0x44,0x0B,0x18,0x8A,0x02,0x0B,0x40,0x0B,0x1A,0x8A,0x04,0x0B,
++    0x44,0x0B,0x1C,0x8A,0x06,0x0B,0x44,0x0B,0x1E,0x8A,0x00,0x0B,0x38,0x82,0x4B,0x19,
++    0x88,0xE6,0x47,0x0B,0x18,0x8A,0x04,0x0B,0x44,0x0B,0x1C,0x8A,0x06,0x0B,0x44,0x0B,
++    0x1E,0x8A,0x04,0x0B,0x40,0x0B,0x1A,0x8A,0x03,0x0B,0x3A,0x82,0xAC,0x8D,0x87,0x3D,
++    0xC0,0x3C,0xC8,0x3C,0x4C,0x00,0x00,0x00,0xC0,0x00,0x3A,0x00,0x4A,0xDA,0x71,0x00,
++    0xC1,0x28,0x42,0xDA,0x44,0x0B,0x90,0x4D,0x88,0x34,0x58,0x0B,0x90,0x4D,0x8C,0x2C,
++    0x5C,0x0B,0x92,0x4D,0x8C,0x24,0x58,0x0B,0x90,0x4D,0x8C,0x1C,0x54,0x0B,0x96,0x75,
++    0x4A,0xA2,0x41,0x53,0x90,0x95,0x94,0x14,0x44,0x53,0x90,0xBD,0x44,0x13,0x92,0x95,
++    0x91,0x0C,0x58,0x7A,0x98,0x01,0x52,0xD3,0x90,0x95,0x94,0x04,0x10,0x09,0x00,0x13,
++    0xA8,0x10,0x1C,0x13,0x12,0x81,0x18,0x13,0x18,0x13,0x14,0x79,0x11,0x13,0x16,0x01,
++    0x00,0x53,0x12,0x89,0x02,0x53,0x40,0x0B,0x10,0x81,0x19,0x8A,0x07,0x0B,0x02,0xF9,
++    0x80,0x89,0x17,0xC3,0x07,0x09,0xB8,0xFF,0xFF,0x7F,0x03,0xF9,0x80,0x89,0x14,0xC3,
++    0x07,0x09,0xB8,0xFF,0xF8,0x4F,0x03,0x19,0x11,0x00,0x00,0x43,0x07,0x09,0xB8,0xFF,
++    0xF8,0x1F,0x0B,0x11,0xC7,0x3C,0xB8,0xFF,0xF8,0x5F,0x23,0xA1,0x01,0x01,0x40,0x4B,
++    0x30,0x48,0xA8,0x16,0xE7,0x20,0x93,0x25,0x03,0x0F,0xF0,0x20,0x92,0x25,0xE7,0x00,
++    0x90,0x05,0x46,0x51,0x98,0x9E,0x0F,0x09,0xC7,0x3C,0xB8,0xFF,0xF8,0xCF,0x42,0x82,
++    0xC8,0x34,0x00,0x0B,0xC8,0x2C,0x18,0x0B,0xCA,0x24,0x18,0x0B,0xCC,0x1C,0x18,0x0B,
++    0x10,0x33,0x4E,0x62,0xD2,0x14,0x00,0x53,0x00,0x7B,0xC8,0x0C,0x00,0x0B,0x4A,0x42,
++    0xC2,0x04,0x88,0x01,0x10,0x43,0x60,0xA1,0xC8,0x16,0x00,0x09,0x87,0x45,0xE8,0x85,
++    0x07,0x01,0x38,0xDF,0x00,0xD0,0x00,0x01,0x80,0x00,0x00,0x42,0x08,0x01,0x00,0x42,
++    0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0x00,0x0F,0x00,0x26,0xF8,0x48,0x48,0x21,
++    0x94,0xDE,0x3F,0x58,0xA8,0x0E,0x00,0x14,0xE6,0x00,0x3C,0x48,0x80,0x06,0x80,0x13,
++    0x38,0x82,0x4B,0x01,0x86,0x5E,0x38,0x18,0x80,0x16,0x80,0x13,0xE2,0x00,0xF2,0x48,
++    0x48,0x11,0x98,0x26,0x38,0x18,0xAC,0x16,0x04,0x14,0xE0,0x00,0xF7,0x48,0x3C,0x1F,
++    0x17,0x01,0x38,0x77,0x16,0x01,0x38,0xFF,0x10,0x01,0x48,0x18,0x11,0x5A,0x9C,0x66,
++    0x54,0x18,0x10,0x5A,0x98,0x8E,0x18,0x01,0x32,0xE2,0x04,0x77,0x30,0x1A,0x18,0x5A,
++    0xA0,0xE6,0x11,0x01,0x44,0x18,0x12,0x5A,0x98,0x8E,0x49,0x18,0x10,0x5A,0x9C,0xE6,
++    0x54,0x18,0x10,0x5A,0x9C,0x0E,0x30,0xA2,0x06,0xFF,0x49,0x18,0x10,0x5A,0x9C,0x0E,
++    0x0E,0x58,0xD6,0x00,0x0C,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD4,0x00,
++    0x0A,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD2,0x00,0x08,0x92,0x4A,0x18,
++    0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD0,0x00,0x0E,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,
++    0x06,0x58,0xD6,0x00,0x0C,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD4,0x00,
++    0x0A,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD2,0x00,0x0A,0x92,0xD2,0x08,
++    0x90,0x06,0x30,0x0A,0x08,0x92,0x32,0x82,0x3A,0x82,0x03,0xEF,0x78,0x50,0x86,0x06,
++    0x10,0x4A,0x82,0x18,0x9A,0x06,0x10,0x02,0x00,0x9A,0x12,0x01,0x30,0xE2,0x4C,0x18,
++    0x11,0x5A,0x9C,0x6E,0x54,0x18,0x10,0x5A,0x9F,0x96,0x10,0xE1,0x08,0x48,0xD4,0x95,
++    0x54,0x18,0x10,0x5A,0x9C,0x66,0x08,0x48,0x8C,0x90,0x14,0x5A,0x9C,0x46,0x08,0x48,
++    0x8C,0x90,0x14,0x5A,0x9C,0x26,0x08,0x48,0x84,0xD6,0x89,0x90,0x04,0x07,0x48,0x48,
++    0x4C,0x18,0x16,0x5A,0x9E,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,0x4C,0x18,0x14,0x5A,
++    0x9C,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,0x4C,0x18,0x12,0x5A,0x9A,0x0E,0x08,0x58,
++    0xD2,0x00,0x0E,0x92,0x4C,0x18,0x10,0x5A,0x98,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,
++    0x44,0x18,0x16,0x5A,0x9E,0x0E,0x00,0x58,0xD2,0x00,0x0E,0x92,0x44,0x18,0x14,0x5A,
++    0x9C,0x0E,0x00,0x58,0xD2,0x00,0x0E,0x92,0x92,0xCE,0x46,0x18,0x10,0x5A,0x9C,0x0E,
++    0x06,0x58,0xD2,0x00,0x0A,0x92,0xD2,0x08,0x90,0x06,0x30,0x0A,0x32,0x1A,0x0B,0x92,
++    0x80,0xD8,0x32,0x82,0x9A,0x0E,0x10,0x02,0x58,0x01,0xA8,0x06,0x13,0x4A,0x3A,0x82,
++    0x32,0x1A,0x83,0xD8,0x9A,0x06,0x10,0x02,0xA8,0x0D,0x00,0x01,0x36,0x02,0x36,0x02,
++    0xEB,0x15,0x30,0xAA,0x81,0x07,0xC0,0x17,0x30,0x72,0x05,0x28,0x32,0x4A,0x33,0x9A,
++    0x46,0x00,0x06,0x00,0x30,0x2A,0x84,0xC5,0xAF,0x05,0xB9,0xE7,0xF3,0x6F,0xE4,0x05,
++    0x3A,0x01,0x40,0x48,0x30,0xB2,0x35,0x01,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,
++    0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0xEA,0x01,0x02,0x48,0x33,0x6A,0x3C,0x82,
++    0x36,0x22,0x30,0x02,0x31,0x02,0x36,0x02,0xBA,0xDF,0xD7,0xEF,0x43,0x02,0x38,0x82,
++    0x88,0x20,0x00,0x01,0x40,0x12,0x48,0x1A,0xF3,0x5D,0x3D,0x82,0x00,0x68,0x00,0x00,
++    0x00,0xC0,0x00,0x00,0x00,0x30,0x01,0x10,0x39,0x82,0xA3,0x85,0x33,0xA2,0xF3,0x20,
++    0xC3,0x2B,0xE1,0x20,0x10,0x5A,0x95,0x06,0x33,0xEA,0xE8,0x1A,0x07,0xD8,0xC2,0x18,
++    0xE0,0x85,0x39,0xC2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x80,0x20,0x03,0x42,0x80,0x20,0x03,0x42,0x80,0x20,0x04,0x42,0x80,0x20,0x03,0x42,
++    0x80,0xA0,0x04,0x42,0x80,0xA0,0x02,0x42,0x80,0xA0,0x04,0x42,0x80,0xA0,0x02,0x42,
++    0x80,0xA0,0x04,0x42,0x80,0xA0,0x02,0x42,0x80,0x20,0x05,0x42,0x80,0xA0,0x02,0x42,
++    0x80,0xA0,0x05,0x42,0x80,0x20,0x02,0x42,0x80,0x20,0x01,0x42,0x80,0x20,0x01,0x42,
++    0x80,0xA0,0x01,0x42,0x80,0xA0,0x01,0x42,0x80,0xA0,0x01,0x42,0x10,0x20,0x08,0x40,
++    0x40,0x08,0x20,0x10,0x10,0x20,0x08,0x40,0x40,0x08,0x20,0x40,0x10,0x20,0x00,0x08,
++    0x08,0xC1,0x02,0x42,0x08,0x81,0x02,0x42,0x08,0x81,0x03,0x42,0x08,0x41,0x03,0x42,
++    0x08,0x01,0x03,0x42,0x08,0x81,0x02,0x42,0x08,0x41,0x02,0x42,0x08,0xC1,0x00,0x42,
++    0x08,0x01,0x02,0x42,0x08,0x01,0x01,0x42,0x08,0xC1,0x01,0x42,0x08,0x41,0x01,0x42,
++    0x08,0x81,0x01,0x42,0x08,0x81,0x01,0x42,0x08,0x41,0x01,0x42,0x08,0xC1,0x02,0x42,
++    0x08,0x01,0x01,0x42,0x08,0x01,0x03,0x42,0x08,0xC1,0x00,0x42,0x50,0x50,0x50,0x50,
++    0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x00,0x00,0x00,0x08,0xF8,0x0F,
++    0xFF,0x07,0xF8,0xFF,0x07,0xF8,0x0F,0xF8,0x08,0x00,0x08,0x08,0x00,0x00,0x00,0x08,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x28,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x03,0x00,0x28,0xB5,0x39,0xC5,0x08,0x1D,0x1B,0x2B,0x3A,0x28,
++    0x53,0xB5,0x0A,0xC5,0x00,0x08,0x01,0x00,0x01,0x00,0x50,0x0D,0x52,0x1D,0x52,0xB5,
++    0x39,0x0D,0x04,0x08,0x51,0x3D,0x53,0x1D,0x51,0x3D,0x54,0x95,0x51,0x3D,0x54,0x95,
++    0x51,0x3D,0x54,0x95,0x0B,0x3D,0x34,0x88,0x51,0x3D,0x54,0x1D,0x51,0x3D,0x54,0x95,
++    0x04,0x00,0x50,0x3D,0x50,0x1D,0x01,0x00,0x00,0x00,0x00,0x00,0x54,0x2D,0x53,0x3D,
++    0x32,0x8D,0x32,0x38,0x01,0x28,0x0A,0x45,0x50,0xB5,0x53,0x95,0x00,0x00,0x00,0x00,
++    0x52,0xA5,0x51,0xB5,0x09,0xC5,0x03,0x08,0x03,0x00,0x50,0x3D,0x55,0x1D,0x51,0x0D,
++    0x51,0x3D,0x54,0x95,0x51,0x3D,0x53,0x1D,0x51,0x3D,0x54,0x95,0x51,0x0D,0x55,0x0D,
++    0x54,0xB5,0x3A,0x0D,0x00,0x08,0x01,0x00,0x53,0xA5,0x51,0x2D,0x52,0x3D,0x34,0x8A,
++    0x1D,0x38,0x52,0x45,0x52,0x0D,0x51,0x1D,0x54,0xB5,0x3A,0x0D,0x53,0xA5,0x29,0xB5,
++    0x39,0xC5,0x08,0x1D,0x19,0x2D,0x22,0x1D,0x44,0x0D,0x31,0x3D,0x23,0x95,0x09,0xC1,
++    0x29,0xB5,0x0B,0x1D,0x1B,0x2B,0x3A,0x28,0x00,0x00,0x00,0x08,0xFF,0x07,0x00,0xF8,
++    0x08,0x00,0x10,0x10,0x08,0x10,0x10,0x10,0x08,0x08,0x10,0x08,0x10,0x08,0x10,0x08,
++    0x10,0x10,0x08,0x08,0x10,0x10,0x08,0x08,0x08,0x08,0x10,0x10,0x10,0x10,0x10,0x10,
++    0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x08,0xF8,0x07,0x08,0x00,
++    0x08,0x08,0x00,0x00,0x70,0x22,0x07,0x00,0x00,0x00,0x00,0x01,0x00,0xE0,0x00,0x00,
++    0x00,0x00,0x05,0x00,0x78,0x02,0x00,0x00,0x00,0xE0,0x00,0x01,0x88,0x40,0x02,0x00,
++    0x00,0xE0,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xD1,0xDA,0xAA,0xA9,0x2E,0x2D,0x55,0x56,0xBB,0x43,0xAC,0x32,
++    0x99,0x21,0x8A,0x10,0x00,0x70,0x00,0x28,0x09,0x00,0x1F,0x00,0x06,0x78,0x50,0x56,
++    0xFF,0xFF,0xFF,0xFF,0xB2,0x30,0x08,0x40,0x00,0x48,0x20,0x00,0xE7,0xF5,0x15,0x0F,
++    0x0F,0x00,0xCA,0xCA,0xFF,0xFF,0xFF,0xFF,0x06,0x16,0x48,0x01,0x09,0x00,0x00,0x04,
++    0xBE,0xBC,0xE1,0xE2,0x30,0x14,0xF6,0x81
++};
++
++
++#define FW_INFO_SIZE	(0x18)
++#define FW_REAL_SIZE	(sizeof(fwbin))
++#define FW_BIN_SIZE		(24*1024+24)	    //24K byte
++
++#endif
++
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Kconfig b/module_drivers/drivers/input/touchscreen/hyn_touch/Kconfig
+new file mode 100644
+index 000000000..10a4e4717
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Kconfig
+@@ -0,0 +1,16 @@
++#
++# Focaltech Touchscreen driver configuration
++#
++
++config TOUCHSCREEN_HYN
++    bool "hyn Touchscreen"
++    default n
++    help
++      Say Y here if you have Focaltech touch panel.
++      If unsure, say N.
++
++config TOUCHSCREEN_HYN_DIRECTORY
++    string "hyn ts directory name"
++    default "hyn_touch"
++    depends on TOUCHSCREEN_HYN
++
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Makefile b/module_drivers/drivers/input/touchscreen/hyn_touch/Makefile
+new file mode 100644
+index 000000000..f4c046d58
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Makefile
+@@ -0,0 +1,4 @@
++# Makefile for the focaltech touchscreen drivers.
++
++obj-$(CONFIG_TOUCHSCREEN_HYN)	+=  hyn_cst3xx.o
++obj-$(CONFIG_TOUCHSCREEN_HYN)	+=  hyn_i2c.o
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver-ori/cst3xx.c b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver-ori/cst3xx.c
+new file mode 100644
+index 000000000..f1e637caf
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver-ori/cst3xx.c
+@@ -0,0 +1,1422 @@
++/*
++ * cst3xx Touchscreen Controller Driver
++ */
++
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/i2c.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of_gpio.h>
++#include <linux/pm_qos.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include <linux/input/cst3xx.h>
++#include <linux/input/hyn_cst3xx_RS659_fw.h>
++#include "../../video/jz_fb_v13/jz_fb.h"
++
++struct st1615_ts_finger {
++	u16 x;
++	u16 y;
++	u8 t;
++	bool is_valid;
++};
++
++struct cst3xx_ts_data {
++	struct i2c_client *client;
++	struct input_dev *input_dev;
++	struct cst3xx_platform_data *pdata;
++	struct work_struct  work;
++       struct delayed_work dwork;
++	struct workqueue_struct *workqueue;
++	int irq;
++};
++
++static int cst3xx_into_program_mode(struct i2c_client * client);
++static int cst3xx_erase_program_area(struct i2c_client * client);
++static void cst3xx_reset_ic(struct cst3xx_ts_data *ts,unsigned int ms);
++static int cst3xx_write_program_data(struct i2c_client * client,const unsigned char *pdata);
++
++static int cst3xx_check_checksum(struct i2c_client * client);
++
++static int cst3xx_exit_program_mode(struct i2c_client * client);
++
++static int cst3xx_update_firmware(struct cst3xx_ts_data *ts, const unsigned char *pdata);
++
++static int cst3xx_firmware_info(struct i2c_client * client);
++
++static int cst3xx_update_judge( unsigned char *pdata, int strict);
++
++static int cst3xx_boot_update_fw(struct cst3xx_ts_data *ts,  unsigned char *pdata);
++
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_test(struct i2c_client *client);
++static void cst3xx_reset(struct cst3xx_ts_data *ts) ;
++extern  void close_vcc3v3Power(void);
++extern  void open_vcc3v3Power(void);
++
++static unsigned char *pcst3xx_update_firmware = (unsigned char *)cst3_fw ; //the updating firmware
++static unsigned int   g_cst3xx_ic_version  = 0;
++static unsigned int   g_cst3xx_ic_checksum = 0;
++static unsigned int   g_cst3xx_ic_checkcode =0;
++static unsigned int   g_cst3xx_ic_project_id  = 0;
++static unsigned int   g_cst3xx_ic_type  = 0;
++
++static unsigned char  report_flag = 0;
++static unsigned int x_temp_pos = 0;
++static unsigned int y_temp_pos = 0;
++
++#define HYN_DRAW_POINT
++
++#define USE_ANALOG_I2C     1 //i2c analog
++//#define USE_HIGHEST_I2CA  1// x1000 highest i2c
++//#define USE_LOWEST_I2CA   1 // x1000 lowest i2c
++#define HYN_UPDATE_FIRMWARE_POWERON_ENABLE
++//#define HYN_UPDATE_FIRMWARE_ENABLE
++
++#pragma pack(1)
++typedef struct
++{
++    u16 pid;                 //product id   //
++    u16 vid;                 //version id   //
++} st_tpd_info;
++#pragma pack()
++
++st_tpd_info tpd_info;
++
++#define CST3XX_BIN_SIZE    (24*1024 + 24)
++#define CST3XX_MAX_X  340
++#define CST3XX_MAX_Y  800
++#define ERROR_TOUCH   1
++
++static void cst3xx_ts_power(struct cst3xx_ts_data *ts, bool poweron)
++{
++	if (gpio_is_valid(ts->pdata->reset_gpio))
++		gpio_direction_output(ts->pdata->reset_gpio, poweron);
++}
++
++static int cst3xx_into_program_mode(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[4];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x01;
++	buf[2] = 0xAA;	//set cmd to enter program mode
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0)  return -1;
++
++	mdelay(2);
++
++	buf[0] = 0xA0;
++	buf[1] = 0x02;	//check whether into program mode
++	ret = cst3xx_i2c_read_register(client, buf, 1);
++	if (ret < 0)  return -1;
++
++	if (buf[0] != 0x55) return -1;
++
++	return 0;
++}
++static int cst3xx_erase_program_area(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[3];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x02;
++	buf[2] = 0x00;		//set cmd to erase main area
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0) return -1;
++
++	mdelay(5);
++
++	buf[0] = 0xA0;
++	buf[1] = 0x03;
++	ret = cst3xx_i2c_read_register(client, buf, 1);
++	if (ret < 0)  return -1;
++
++	if (buf[0] != 0x55) return -1;
++
++	return 0;
++}
++
++
++static void cst3xx_reset_ic(struct cst3xx_ts_data *ts,unsigned int ms)
++{
++
++	unsigned char buf[4];
++	buf[0] = 0xD1;
++	buf[1] = 0x0E;
++	cst3xx_i2c_write(ts->client, buf, 2);
++/*
++	gpio_direction_output(ts->pdata->reset_gpio,0);
++	mdelay(2);
++	gpio_direction_output(ts->pdata->reset_gpio,1);
++*/
++	mdelay(ms);
++}
++
++
++static int cst3xx_write_program_data(struct i2c_client * client,
++		const unsigned char *pdata)
++{
++	int i, ret;
++	unsigned char *i2c_buf;
++	unsigned short eep_addr;
++	int total_kbyte;
++
++	unsigned char temp_buf[8];
++	unsigned short iic_addr;
++	int  j;
++
++
++	i2c_buf = kmalloc(sizeof(unsigned char)*(1024 + 2), GFP_KERNEL);
++	if (i2c_buf == NULL)
++		return -1;
++
++	//make sure fwbin len is N*1K
++	//total_kbyte = len / 1024;
++	total_kbyte = 24;
++	for (i=0; i<total_kbyte; i++) {
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x14;
++		eep_addr = i << 10;		//i * 1024
++		i2c_buf[2] = eep_addr;
++		i2c_buf[3] = eep_addr>>8;
++		ret = cst3xx_i2c_write(client, i2c_buf, 4);
++		if (ret < 0)
++			goto error_out;
++
++		memcpy(i2c_buf, pdata + eep_addr, 1024);
++		for(j=0; j<256; j++) {
++			iic_addr = (j<<2);
++    	temp_buf[0] = (iic_addr+0xA018)>>8;
++    	temp_buf[1] = (iic_addr+0xA018)&0xFF;
++		temp_buf[2] = i2c_buf[iic_addr+0];
++		temp_buf[3] = i2c_buf[iic_addr+1];
++		temp_buf[4] = i2c_buf[iic_addr+2];
++		temp_buf[5] = i2c_buf[iic_addr+3];
++    	      ret = cst3xx_i2c_write(client, temp_buf, 6);
++    		if (ret < 0)
++    			goto error_out;
++		}
++
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x04;
++		i2c_buf[2] = 0xEE;
++		ret = cst3xx_i2c_write(client, i2c_buf, 3);
++		if (ret < 0)
++			goto error_out;
++
++		mdelay(60);
++
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x05;
++		ret = cst3xx_i2c_read_register(client, i2c_buf, 1);
++		if (ret < 0)
++			goto error_out;
++
++		if (i2c_buf[0] != 0x55)
++			goto error_out;
++
++	}
++
++	i2c_buf[0] = 0xA0;
++	i2c_buf[1] = 0x03;
++	i2c_buf[2] = 0x00;
++	ret = cst3xx_i2c_write(client, i2c_buf, 3);
++	if (ret < 0)
++		goto error_out;
++
++	mdelay(8);
++
++	if (i2c_buf != NULL) {
++		kfree(i2c_buf);
++		i2c_buf = NULL;
++	}
++
++	return 0;
++
++error_out:
++	if (i2c_buf != NULL) {
++		kfree(i2c_buf);
++		i2c_buf = NULL;
++	}
++	return -1;
++}
++
++
++static int cst3xx_check_checksum(struct i2c_client * client)
++{
++	int ret;
++	int i;
++	unsigned int  checksum;
++	unsigned int  bin_checksum;
++	unsigned char buf[4];
++	const unsigned char *pData;
++
++	for(i=0; i<5; i++)
++	{
++		buf[0] = 0xA0;
++		buf[1] = 0x00;
++		ret = cst3xx_i2c_read_register(client, buf, 1);
++		if(ret < 0)
++		{
++			mdelay(2);
++			continue;
++		}
++
++		if(buf[0]!=0)
++			break;
++		else
++		mdelay(2);
++	}
++    mdelay(2);
++
++
++    if(buf[0]==0x01)
++	{
++		buf[0] = 0xA0;
++		buf[1] = 0x08;
++		ret = cst3xx_i2c_read_register(client, buf, 4);
++
++		if(ret < 0)	return -1;
++
++		// read chip checksum
++		checksum = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24);
++
++        pData=(unsigned char  *)pcst3xx_update_firmware +24*1024+16;   //7*1024 +512
++		bin_checksum = pData[0] + (pData[1]<<8) + (pData[2]<<16) + (pData[3]<<24);
++
++        printk("  hyn the updated ic checksum is :0x%x. the updating firmware checksum is:0x%x------\n", checksum, bin_checksum);
++
++        if(checksum!=bin_checksum)
++		{
++			printk(" cst3xx hyn check sum error.\n");
++			return -1;
++
++		}
++
++	}
++	else
++	{
++		printk(" cst3xx hyn No checksum.\n");
++		return -1;
++	}
++	return 0;
++}
++
++static int cst3xx_exit_program_mode(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[3];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x06;
++	buf[2] = 0xEE;
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0)
++		return -1;
++
++	mdelay(10);	//wait for restart
++
++
++	return 0;
++}
++
++
++static int cst3xx_update_firmware(struct cst3xx_ts_data *ts, const unsigned char *pdata)
++{
++	int ret;
++	int retry = 0;
++
++	printk(" cst3xx----------upgrade cst3xx begain------------\n");
++	disable_irq(ts->irq);
++	mdelay(20);
++START_FLOW:
++
++#ifdef HYN_UPDATE_FIRMWARE_POWERON_ENABLE
++	close_vcc3v3Power();
++	mdelay(20);
++	open_vcc3v3Power();
++	mdelay(5+retry);
++#else
++	cst3xx_reset_ic(ts,5+retry);
++#endif
++	ret = cst3xx_into_program_mode(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]into program mode failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_erase_program_area(ts->client);
++	if (ret) {
++		printk(" cst3xx[cst3xx]erase main area failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_write_program_data(ts->client, pdata);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]write program data into cstxxx failed.\n");
++		goto err_out;
++	}
++
++    ret =cst3xx_check_checksum(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx] after write program cst3xx_check_checksum failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_exit_program_mode(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]exit program mode failed.\n");
++		goto err_out;
++	}
++
++	cst3xx_reset_ic(ts,20);
++
++	printk(" cst3xx hyn----------cst3xx_update_firmware  end------------\n");
++
++	enable_irq(ts->irq);
++
++	return 0;
++
++err_out:
++	if (retry < 30) {
++		retry++;
++		mdelay(20);
++		goto START_FLOW;
++	}
++	else {
++		enable_irq(ts->irq);
++		return -1;
++	}
++}
++
++
++
++
++/*******************************************************
++Function:
++    get firmware version, ic type...
++Input:
++    client: i2c client
++Output:
++    success: 0
++    fail:	-1
++*******************************************************/
++static int cst3xx_firmware_info(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[28];
++//	unsigned short ic_type, project_id;
++
++
++	buf[0] = 0xD1;
++	buf[1] = 0x01;
++	ret = cst3xx_i2c_write(client, buf, 2);
++	if (ret < 0) return -1;
++
++	mdelay(40);
++
++	buf[0] = 0xD1;
++	buf[1] = 0xFC;
++	ret = cst3xx_i2c_read_register(client, buf, 4);
++	if (ret < 0) return -1;
++
++	//0xCACA0000
++	g_cst3xx_ic_checkcode = buf[3];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[2];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[1];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[0];
++
++	printk("linc cst3xx [cst3xx] the chip g_cst3xx_ic_checkcode:0x%x.\r\n",g_cst3xx_ic_checkcode);
++	
++	mdelay(2);
++	
++	buf[0] = 0xD2;
++	buf[1] = 0x04;
++	ret = cst3xx_i2c_read_register(client, buf, 4);
++	if (ret < 0) return -1;
++	g_cst3xx_ic_type = buf[3];
++	g_cst3xx_ic_type <<= 8;
++	g_cst3xx_ic_type |= buf[2];
++
++	
++	g_cst3xx_ic_project_id = buf[1];
++	g_cst3xx_ic_project_id <<= 8;
++	g_cst3xx_ic_project_id |= buf[0];
++
++	printk("linc cst3xx [cst3xx] the chip ic g_cst3xx_ic_type :0x%x, g_cst3xx_ic_project_id:0x%x\r\n",
++		g_cst3xx_ic_type, g_cst3xx_ic_project_id);
++
++	mdelay(2);
++	
++	buf[0] = 0xD2;
++	buf[1] = 0x08;
++	ret = cst3xx_i2c_read_register(client, buf, 8);
++	if (ret < 0) return -1;	
++
++	g_cst3xx_ic_version = buf[3];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[2];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[1];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[0];
++
++	g_cst3xx_ic_checksum = buf[7];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[6];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[5];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[4];	
++
++	tpd_info.vid = g_cst3xx_ic_version;
++    tpd_info.pid = 0x00;
++
++
++	printk(" cst3xx [cst3xx] the chip ic version:0x%x, checksum:0x%x\r\n",
++		g_cst3xx_ic_version, g_cst3xx_ic_checksum);
++
++	if(g_cst3xx_ic_version==0xA5A5A5A5)
++	{
++		printk(" cst3xx [cst3xx] the chip ic don't have firmware. \n");
++		return -1;
++	}
++	if((g_cst3xx_ic_checkcode&0xffff0000)!=0xCACA0000){
++		printk("linc cst3xx [cst3xx] cst3xx_firmware_info read error .\r\n");
++		return -1;
++	}
++
++    buf[0] = 0xD1;
++	buf[1] = 0x09;
++	ret = cst3xx_i2c_write(client, buf, 2);
++	if (ret < 0) return -1;
++    mdelay(5);
++
++
++	return 0;
++}
++
++static int cst3xx_update_judge( unsigned char *pdata, int strict)
++{
++	unsigned short ic_type, project_id;
++	unsigned int fw_checksum, fw_version;
++	const unsigned int *p;
++	int i;
++	unsigned char *pBuf;
++
++	fw_checksum = 0x55;
++	p = (const unsigned int *)pdata;
++	for (i=0; i<(CST3XX_BIN_SIZE-4); i+=4) {
++		fw_checksum += (*p);
++		p++;
++	}
++
++	if (fw_checksum != (*p)) {
++		printk(" cst3xx[cst3xx]calculated checksum error:0x%x not equal 0x%x.\n", fw_checksum, *p);
++		return -1;	//bad fw, so do not update
++	}
++
++	pBuf = &pdata[CST3XX_BIN_SIZE-16];
++
++	project_id = pBuf[1];
++	project_id <<= 8;
++	project_id |= pBuf[0];
++
++	ic_type = pBuf[3];
++	ic_type <<= 8;
++	ic_type |= pBuf[2];
++
++	fw_version = pBuf[7];
++	fw_version <<= 8;
++	fw_version |= pBuf[6];
++	fw_version <<= 8;
++	fw_version |= pBuf[5];
++	fw_version <<= 8;
++	fw_version |= pBuf[4];
++
++	fw_checksum = pBuf[11];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[10];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[9];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[8];
++
++	printk(" cst3xx[cst3xx]the updating firmware:project_id:0x%04x,ic type:0x%04x,version:0x%x,checksum:0x%x\n",
++			project_id, ic_type, fw_version, fw_checksum);
++
++	if (strict > 0) {
++
++		if (g_cst3xx_ic_checksum != fw_checksum){
++			if (g_cst3xx_ic_version >fw_version){
++				printk("[cst3xx]fw version(0x%x), ic version(0x%x).\n",fw_version, g_cst3xx_ic_version);
++				return -1;
++			}
++		}else{
++			printk("[cst3xx]fw checksum(0x%x), ic checksum(0x%x).\n",fw_checksum, g_cst3xx_ic_checksum);
++			return -1;
++		}
++	}
++
++	return 0;
++}
++static int cst3xx_boot_update_fw(struct cst3xx_ts_data *ts,  unsigned char *pdata)
++{
++	int ret;
++	int retry = 0;
++	int flag = 0;
++
++	while (retry++ < 3) {
++		ret = cst3xx_firmware_info(ts->client);
++		if (ret == 0) {
++			flag = 1;
++			break;
++		}
++	}
++
++	if (flag == 1) {
++		ret = cst3xx_update_judge(pdata, 1);
++		if (ret < 0) {
++			printk(" cst3xx[cst3xx] no need to update firmware.\n");
++			return 0;
++		}
++	}
++
++	ret = cst3xx_update_firmware(ts, pdata);
++	if (ret < 0){
++		printk(" cst3xx [cst3xx] update firmware failed.\n");
++		return -1;
++	}
++
++    mdelay(50);
++
++	ret = cst3xx_firmware_info(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx [cst3xx] after update read version and checksum fail.\n");
++		return -1;
++	}
++
++	return 0;
++}
++
++
++/*******************************Chose which I2C interface ********************************************/
++
++#if USE_ANALOG_I2C
++
++#define I2CSDA  GPIO_PC(27)
++#define I2CSCL   GPIO_PC(26)
++
++#define I2CSDA_HIGH gpio_direction_output(GPIO_PC(27),1)
++#define I2CSDA_LOW  gpio_direction_output(GPIO_PC(27),0)
++
++#define I2CSCL_HIGH  gpio_direction_output(GPIO_PC(26),1)
++#define I2CSCL_LOW  gpio_direction_output(GPIO_PC(26),0)
++
++#define delay_data 2
++static void iicstart(void)
++{
++     I2CSDA_HIGH;
++      I2CSCL_HIGH;
++      __udelay(2);
++      I2CSDA_LOW;
++      __udelay(2);
++       I2CSCL_LOW;
++       __udelay(2);
++}
++static void iicstop(void)
++{
++     I2CSDA_LOW;
++     I2CSCL_HIGH;
++     __udelay(2);
++     I2CSDA_HIGH;
++     __udelay(2);
++
++}
++static unsigned char waitack(void)
++{
++   u8 ucErrTime=0;
++
++    gpio_direction_input(GPIO_PC(27));
++   //  __udelay(2);
++
++  //  I2CSDA_HIGH;
++  //  __udelay(2);
++     I2CSCL_HIGH;
++     __udelay(2);
++
++    while(__gpio_get_value(GPIO_PC(27)))
++    {
++        ucErrTime++;
++     //   printk("time out ++ \n");
++        if(ucErrTime>250)
++         {
++                iicstop();
++                return 1;
++        }
++    }
++    I2CSCL_LOW;
++     __udelay(2);
++    return 0;
++}
++static void sendack(void)
++{
++     I2CSCL_LOW;
++     __udelay(delay_data);
++     I2CSDA_LOW;
++     __udelay(delay_data);
++
++     I2CSCL_HIGH;
++     __udelay(delay_data);
++     I2CSCL_LOW;
++     __udelay(delay_data);
++
++}
++static void sendnotack(void)
++{
++     I2CSCL_LOW;
++     __udelay(delay_data);
++    I2CSDA_HIGH;
++    __udelay(delay_data);
++
++    I2CSCL_HIGH;
++    __udelay(delay_data);
++    I2CSCL_LOW;
++    __udelay(delay_data);
++}
++static void iicsendbyte(unsigned char ch)
++{
++     unsigned char i;
++     I2CSCL_LOW;
++     for(i = 0;i<8;i++)
++     {
++          if(ch&0x80)
++          {
++              I2CSDA_HIGH;
++          }
++          else
++          {
++              I2CSDA_LOW;
++          }
++           __udelay(delay_data);
++          ch<<=1;
++          I2CSCL_HIGH;
++          __udelay(delay_data);
++               I2CSCL_LOW;
++          __udelay(delay_data);
++     }
++}
++static unsigned char iicreceivebyte(unsigned char ack)
++{
++    unsigned char i=8;
++    unsigned char ddata=0;
++
++    gpio_direction_input(GPIO_PC(27));
++    __udelay(delay_data);
++
++     for(i = 0;i<8;i++)
++     {
++         I2CSCL_LOW;
++         __udelay(delay_data);
++         I2CSCL_HIGH;
++         __udelay(delay_data);
++
++         ddata<<=1;
++         if(gpio_get_value(GPIO_PC(27))) ddata++;
++    }
++
++    if(!ack)
++        sendnotack();
++     else
++        sendack();
++
++    return ddata;
++}
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++    int count = len;
++     iicstart();
++     __udelay(delay_data);
++
++/*
++	 iicsendbyte( (0x1a<<1) | 0);
++     __udelay(delay_data);
++
++     if(waitack())
++     {
++        iicstop();
++                printk(" cst3xx_i2c_read wait ack timeoue \n");
++        return 1;
++     }
++
++     iicsendbyte(buf[0]);
++     __udelay(delay_data);
++     waitack();
++     __udelay(delay_data);
++*/
++     iicstart();
++     __udelay(delay_data);
++
++     iicsendbyte((0x1a << 1 ) | 1);
++     __udelay(delay_data);
++     if(waitack())
++     {
++        iicstop();
++                printk(" cst3xx_i2c_read wait ack timeoue \n");
++        return 1;
++     }
++     __udelay(delay_data);
++
++    while(count)
++    {
++         if(count == 1) *buf = iicreceivebyte(0);
++         else *buf = iicreceivebyte(1);
++         count --;
++         buf++;
++    }
++     iicstop();
++     __udelay(delay_data);
++     return 0;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++     int count = len;
++      iicstart();
++   //   __udelay(delay_data);
++
++      iicsendbyte((0x1A << 1) | 0);
++//      __udelay(delay_data);
++
++     if(waitack())
++     {
++        iicstop();
++        printk(" cst3xx_i2c_write send address wait ack timeoue \n");
++        return 1;
++     }
++
++      while(count--)
++      {
++            iicsendbyte(*(buf++));
++            __udelay(delay_data);
++             if(waitack())
++             {
++                iicstop();
++               printk(" cst3xx_i2c_write wait ack timeoue \n");
++                return 1;
++             }
++            __udelay(delay_data);
++      }
++
++      iicstop();
++      __udelay(delay_data);
++
++	return 0;
++}
++
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	int ret = -1;
++
++    ret = cst3xx_i2c_write(client, buf, 2);
++    if(ret) printk("failed to write cst3xx\n");
++
++    ret = cst3xx_i2c_read(client, buf, len);
++    if(ret) printk("failed to write cst3xx\n");
++    return ret;
++}
++
++#elif  USE_LOWEST_I2CA
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++	int ret = -1;
++	int retries = 0;
++
++	while (retries < 2) {
++		ret = i2c_master_recv(client, buf, len);
++		if(ret<=0)
++		    retries++;
++        else
++            break;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++	int ret = -1;
++	int retries = 0;
++
++	while (retries < 2) {
++		ret = i2c_master_send(client, buf, len);
++		if(ret<=0)
++		    retries++;
++        else
++            break;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	int ret = -1;
++
++    ret = cst3xx_i2c_write(client, buf, 2);
++
++    ret = cst3xx_i2c_read(client, buf, len);
++
++    return ret;
++}
++
++#elif USE_HIGHEST_I2CA
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++	struct i2c_msg msg;
++	int ret = -1;
++	int retries = 0;
++
++	msg.flags |= I2C_M_RD;
++	msg.addr   = client->addr;
++	msg.len    = len;
++	msg.buf    = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == 1)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++/*******************************************************
++Function:
++    read data from register.
++Input:
++    buf: first two byte is register addr, then read data store into buf
++    len: length of data that to read
++Output:
++    success: number of messages
++    fail:	negative errno
++*******************************************************/
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	struct i2c_msg msgs[2];
++	int ret = -1;
++	int retries = 0;
++
++	msgs[0].flags = 0;
++	msgs[0].addr  = client->addr;
++	msgs[0].len   = 2;
++	msgs[0].buf   = buf;
++
++	msgs[1].flags |= I2C_M_RD;
++	msgs[1].addr   = client->addr;
++	msgs[1].len    = len;
++	msgs[1].buf    = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, msgs, 2);
++		if(ret == 2)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++	struct i2c_msg msg;
++	int ret = -1;
++	int retries = 0;
++
++	msg.flags = 0;
++	msg.addr  = client->addr;
++	msg.len   = len;
++	msg.buf   = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == 1)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++#else
++#endif
++/*********************************i2c end********************************/
++
++
++static int cst3xx_i2c_test(struct i2c_client *client)
++{
++	int retry = 0;
++	int ret;
++	unsigned char buf[4];
++
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	while (retry++ < 5) {
++		ret = cst3xx_i2c_write(client, buf, 2);
++		if (ret == 0)
++			return ret;
++
++		mdelay(2);
++	}
++
++    if(retry==5) printk(" cst3xx hyn I2C TEST error.ret:%d;\n", ret);
++
++	return ret;
++}
++
++
++static void cst3xx_reset(struct cst3xx_ts_data *ts) {
++	if(gpio_is_valid(ts->pdata->reset_gpio)) {
++		gpio_direction_output(ts->pdata->reset_gpio,0);
++		mdelay(100);
++		gpio_direction_output(ts->pdata->reset_gpio,1);
++		mdelay(100);
++	}
++}
++/****************************  basic communication end*******************************/
++
++
++static void cst3xx_touch_report(struct cst3xx_ts_data *ts)
++{
++	unsigned char buf[30];
++	unsigned char i2c_buf[8];
++	unsigned char key_status, key_id = 0, finger_id, sw;
++	unsigned int  input_x = 0;
++	unsigned int  input_y = 0;
++	unsigned int  input_w = 0;
++	unsigned int input_x_delta = 0;
++	unsigned int input_y_delta = 0;
++       unsigned char cnt_up, cnt_down;
++	int   i, ret, idx;
++	int cnt, i2c_len;
++
++	int  len_1, len_2;
++
++      key_status = 0;
++
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	ret = cst3xx_i2c_read_register(ts->client, buf, 7);
++	if(ret < 0) {
++		printk("  iic read touch point data failed.\n");
++		goto OUT_PROCESS;
++	}
++  //   printk(" read buf : buf[0]: %x ,buf[1]: %x ,buf[2]: %x, buf[3]: %x,buf[4]: %x ,buf[5]: %x ,buf[6]: %x, buf[7]: %x,\n",buf[0],buf[1],buf[2],buf[3],buf[4],buf[5],buf[6],buf[7]);
++
++	if(buf[6] != 0xAB) {
++		printk(KERN_INFO " data is not valid..\r\n");
++		goto OUT_PROCESS;
++	}
++
++    	cnt = buf[5] & 0x7F;
++	if(cnt > 1) goto OUT_PROCESS;
++	else if(cnt==0)     goto CLR_POINT;
++
++	if(cnt == 0x01) {
++		goto FINGER_PROCESS;
++	}
++
++FINGER_PROCESS:
++
++    /*
++     *  sw: buf[0] low 4 bit
++     *  x pos:  buf[1] low 4 bit | buf[3] high 4 bit
++     *  y pos:  buf[2] low 4 bit | buf[3] low  4 bit
++     *  z press : buf[4]
++     *  finger_id:buf[0] high 4 bit
++     */
++	i2c_buf[0] = 0xD0;
++	i2c_buf[1] = 0x00;
++	i2c_buf[2] = 0xAB;
++
++	ret = cst3xx_i2c_write(ts->client, i2c_buf, 3);
++	if(ret < 0) {
++		printk(" cst3xx hyn send read touch info ending failed.\r\n");
++		cst3xx_reset_ic(ts,20);
++              goto END;
++	}
++
++	idx = 0;
++       cnt_up = 0;
++       cnt_down = 0;
++	input_x = (unsigned int)((buf[idx + 1] << 4) | ((buf[idx + 3] >> 4) & 0x0F));
++	input_y = (unsigned int)((buf[idx + 2] << 4) | (buf[idx + 3] & 0x0F));
++	input_w = (unsigned int)(buf[idx + 4]);
++	sw = (buf[idx] & 0x0F) >> 1;
++	finger_id = (buf[idx] >> 4) & 0x0F;
++
++    printk(" no handle : cst3xxPoint x:%d, y:%d, w:%d, id:%d, sw:%d. \n", input_x, input_y, input_w,finger_id, sw);
++
++	input_x=input_x*CST3XX_MAX_X/360;
++	input_y=input_y*CST3XX_MAX_Y/800;
++	
++	if(input_x >= CST3XX_MAX_X) input_x = CST3XX_MAX_X;
++	if(input_y >= CST3XX_MAX_Y) input_y = CST3XX_MAX_Y;
++
++	input_x = CST3XX_MAX_X-input_x;
++	input_y = CST3XX_MAX_Y-input_y;
++
++#ifdef 0//HYN_DRAW_POINT
++	if(input_x > 300){
++		input_x_delta = input_x - (CST3XX_MAX_X/2);
++		input_x = input_x + input_x_delta/((CST3XX_MAX_X/2)/20);
++		if(input_x > CST3XX_MAX_X) input_x = CST3XX_MAX_X;
++		}
++	if(input_x < 40){
++		input_x_delta = (CST3XX_MAX_X/2) - input_x;
++		input_x = input_x - input_x_delta/((CST3XX_MAX_X/2)/12);
++		if(input_x < 0) input_x = 0;
++		}
++	if(input_y > 760){
++		input_y_delta = input_y - (CST3XX_MAX_Y/2);
++		input_y = input_y + input_y_delta/((CST3XX_MAX_Y/2)/12);
++		if(input_y > CST3XX_MAX_Y) input_y = CST3XX_MAX_Y;
++		}
++	if(input_y < 40){
++		input_y_delta = (CST3XX_MAX_Y/2) - input_y;
++		input_y = input_y - input_y_delta/((CST3XX_MAX_Y/2)/25);
++		if(input_y < 0) input_y = 0;
++		}
++#endif
++
++    printk(" handle : cst3xxPoint x:%d, y:%d, w:%d, id:%d, sw:%d. \n\n", input_x, input_y, input_w,finger_id, sw);
++
++	if (sw == 0x03 ) {
++         	   if((input_x > x_temp_pos + ERROR_TOUCH) || (input_x < x_temp_pos -ERROR_TOUCH)  || (input_y > y_temp_pos + ERROR_TOUCH) || (input_y < y_temp_pos -ERROR_TOUCH))
++               {
++          //           printk(" REPORT TOUCH DOWM Handle \n");
++                     x_temp_pos = input_x;
++                     y_temp_pos = input_y;
++                     input_report_key(ts->input_dev, BTN_TOUCH, 1);
++    		        input_report_abs(ts->input_dev, ABS_X, input_x);
++    	               input_report_abs(ts->input_dev, ABS_Y, input_y);
++    		        input_report_abs(ts->input_dev, ABS_PRESSURE, 1);
++    		        input_sync(ts->input_dev);
++                 }
++                cnt_down++;
++       }
++      else if(sw == 0) {
++                cnt_up++;
++        }
++
++        if((cnt_up>0) && (cnt_down==0) ){
++      //      printk(" REPORT TOUCH UP Handle \n");
++            x_temp_pos = 0;
++            y_temp_pos = 0;
++            input_report_key(ts->input_dev, BTN_TOUCH, 0);
++            input_report_abs(ts->input_dev, ABS_PRESSURE, 0);
++            input_mt_sync(ts->input_dev);
++        }
++       input_sync(ts->input_dev);
++	goto END;
++CLR_POINT:
++
++	    input_report_key(ts->input_dev, BTN_TOUCH, 0);
++           input_mt_sync(ts->input_dev);
++           input_sync(ts->input_dev);
++
++OUT_PROCESS:
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	buf[2] = 0xAB;
++	ret = cst3xx_i2c_write(ts->client, buf, 3);
++	if (ret < 0) {
++		printk("  send read touch info ending failed.\n");
++		cst3xx_reset_ic(ts,20);
++	}
++END:
++	return;
++}
++
++
++/******************************* irq handle  begin************************************/
++static void cst3xx_work_handler(struct work_struct *work)
++{
++	struct cst3xx_ts_data *cst3xx_ts = container_of(work, struct cst3xx_ts_data, work);
++	int ret = 0;
++    /******************here handle touch *******************/
++    //    printk(KERN_INFO "-----------enter cst3xx_work_handler------------\n");
++         cst3xx_touch_report(cst3xx_ts);
++	  enable_irq(cst3xx_ts->irq);
++}
++
++static irqreturn_t cst3xx_ts_irq_handler(int irq, void *dev_id)
++{
++	struct cst3xx_ts_data *ts = dev_id;
++
++   //    printk( KERN_INFO "-----------enter cst3xx_ts_irq_handler------------\n");
++
++	disable_irq_nosync(ts->irq);//use in interrupt,disable_irq will make dead lock.
++
++	if (!work_pending(&ts->work)) {
++		queue_work(ts->workqueue, &ts->work);
++	//    queue_delayed_work(ts->workqueue,&ts->dwork,1);//10ms * x
++	} else {
++		enable_irq(ts->irq);
++	}
++
++	return IRQ_HANDLED;
++}
++/******************************* irq handle  end************************************/
++
++static int cst3xx_ts_probe(struct i2c_client *client,
++					const struct i2c_device_id *id)
++{
++       printk( KERN_INFO "Enter cst3xx_ts_probe -------------------\n");
++
++       int ret;
++	struct cst3xx_ts_data *ts;
++
++	struct cst3xx_platform_data *pdata = (struct cst3xx_platform_data*)client->dev.platform_data;
++	struct input_dev *input_dev;
++	int error;
++
++#if USE_ANALOG_I2C
++        if (gpio_is_valid(I2CSDA))
++        {
++            gpio_free(I2CSDA);
++            ret = gpio_request(GPIO_PC(27),"I2C1-SDA");
++            if(ret < 0){
++                printk("I2C1-SDA gpio request failed\n");
++                return ret;
++            }
++        }
++         if (gpio_is_valid(I2CSCL))
++        {
++            gpio_free(I2CSCL);
++            ret = gpio_request(GPIO_PC(26),"I2C1-SCL");
++            if(ret < 0){
++                printk("I2C1-SCL gpio request failed\n");
++                return ret;
++            }
++         }
++#endif
++
++      ts = devm_kzalloc(&client->dev, sizeof(*ts), GFP_KERNEL);
++	if (!ts)
++		return -ENOMEM;
++      input_dev = input_allocate_device();
++      if(!input_dev)
++            return -ENOMEM;
++
++      ts->pdata = pdata;
++      ts->client = client;
++      ts->input_dev = input_dev;
++
++	if(client->addr != 0x1A) //check address
++	{
++		client->addr = 0x1A;
++		printk("Crystal_shen:i2c_client_HYN->addr=%d.\n",client->addr);
++
++	}
++
++	if (gpio_is_valid(ts->pdata->int_gpio)) {
++		//error = gpio_request(pdata->int_gpio,"cst3xx gpio irq");
++        	error = gpio_request_one(pdata->int_gpio, GPIOF_IN, "cst3xx gpio irq");
++		if (error < 0) {
++			dev_err(&client->dev, "Failed to request GPIO %d, error %d\n",
++				pdata->int_gpio, error);
++			return error;
++		}
++
++	/*	if (error < 0) {
++			dev_err(&client->dev, "%s:failed to set gpio irq.\n",__func__);
++			return error;
++		}*/
++		ts->irq = gpio_to_irq(pdata->int_gpio);
++             printk(" cst3xx ts -> irq = %d.\n",ts->irq);
++	}
++
++	if (gpio_is_valid(ts->pdata->reset_gpio)) {
++		error = devm_gpio_request(&client->dev, ts->pdata->reset_gpio, NULL);
++		if (error) {
++			dev_err(&client->dev,
++				"Unable to request GPIO pin %d.\n",
++				ts->pdata->reset_gpio);
++				return error;
++		}
++	}
++       cst3xx_reset(ts);
++       printk( KERN_INFO "cst3xx reset -------------------\n");
++       ret =  cst3xx_i2c_test(ts->client);
++       if(ret>=0){
++
++          mdelay(100);
++
++          printk( KERN_INFO "cst3xx test OK -------------------\n");
++#ifdef HYN_UPDATE_FIRMWARE_ENABLE
++	        ret = cst3xx_boot_update_fw(ts,pcst3xx_update_firmware);//
++			if(ret < 0){
++			printk(" cst3xx hyn_boot_update_fw failed.\n");
++			return -1;
++			}
++#endif
++
++       }else{
++          printk( KERN_INFO "cst3xx hyn i2c communication failed.---------------\n");
++		  return -1;
++       }
++
++	input_dev->name = "cst3xxx -touchscreen";
++	input_dev->id.bustype = BUS_I2C;
++	input_dev->dev.parent = &client->dev;
++
++	set_bit(EV_KEY, input_dev->evbit);
++	set_bit(EV_ABS, input_dev->evbit);
++	set_bit(EV_SYN, input_dev->evbit);
++	set_bit(BTN_TOUCH, input_dev->keybit);
++
++    set_bit(ABS_X, input_dev->absbit);
++	set_bit(ABS_Y, input_dev->absbit);
++    set_bit(ABS_PRESSURE, input_dev->absbit);
++
++
++	input_set_abs_params(input_dev, ABS_X, ts->pdata->x_min, ts->pdata->x_max, 0, 0);
++	input_set_abs_params(input_dev, ABS_Y, ts->pdata->y_min, ts->pdata->y_max, 0, 0);
++    input_set_abs_params(input_dev, ABS_PRESSURE, 0, 1, 0 , 0);
++
++  /*     input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR, 0, MAX_AREA, 0, 0);
++       input_set_abs_params(input_dev, ABS_MT_WIDTH_MAJOR, 0, MAX_AREA, 0, 0);
++       input_set_abs_params(input_dev, ABS_MT_POSITION_X, ts->pdata->x_min, ts->pdata->x_max, 0, 0);
++	input_set_abs_params(input_dev, ABS_MT_POSITION_Y, ts->pdata->y_min, ts->pdata->y_max, 0, 0);
++*/
++       error = input_register_device(input_dev);
++	if (error) {
++		dev_err(&client->dev, "Unable to register %s input device\n",
++			input_dev->name);
++		return error;
++	}
++
++  //    INIT_DELAYED_WORK(&ts->dwork, cst3xx_work_handler);
++
++	INIT_WORK(&ts->work, cst3xx_work_handler);
++	ts->workqueue = create_singlethread_workqueue("cst3xx_wq");
++
++	error = devm_request_threaded_irq(&client->dev, client->irq,
++					  NULL,
++					  cst3xx_ts_irq_handler,
++					  IRQF_ONESHOT,
++					  client->name, ts);
++	if (error) {
++		dev_err(&client->dev, "Failed to register interrupt\n");
++		return error;
++	}
++  	error = request_irq(ts->irq,
++				cst3xx_ts_irq_handler,
++				ts->pdata->irqflags,
++				client->dev.driver->name,
++				ts);
++	if (error < 0) {
++		dev_err(&client->dev, "%s: request irq failed\n",__func__);
++		return error;
++	}
++     printk(KERN_INFO "-----------CST3XX probe end ------------\n");
++       return 0;
++}
++
++static int cst3xx_ts_remove(struct i2c_client *client)
++{
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++        free_irq(ts->irq,ts);
++        devm_free_irq(&ts->client->dev, ts->client->irq,ts);
++        destroy_workqueue(ts->workqueue);
++        input_unregister_device(ts->input_dev);
++        devm_gpio_free(&ts->client->dev, ts->pdata->reset_gpio);
++        gpio_free(ts->pdata->int_gpio);
++
++#if USE_ANALOG_I2C
++         gpio_free(I2CSDA);
++        gpio_free(I2CSCL);
++#endif
++
++	return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int cst3xx_ts_suspend(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++
++	if (device_may_wakeup(&client->dev)) {
++		enable_irq_wake(client->irq);
++	} else {
++		disable_irq(client->irq);
++		cst3xx_ts_power(ts, false);//reset
++	}
++
++	return 0;
++}
++
++static int cst3xx_ts_resume(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++
++	if (device_may_wakeup(&client->dev)) {
++		disable_irq_wake(client->irq);
++	} else {
++		cst3xx_ts_power(ts, true);
++		enable_irq(client->irq);
++	}
++	return 0;
++}
++
++#endif
++
++static SIMPLE_DEV_PM_OPS(cst3xx_ts_pm_ops,
++			 cst3xx_ts_suspend, cst3xx_ts_resume);
++
++static const struct i2c_device_id cst3xx_ts_id[] = {
++	{ CST3XX_NAME, 0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, cst3xx_ts_id);
++
++
++#ifdef CONFIG_OF
++static const struct of_device_id cst3xx_ts_dt_ids[] = {
++	{ .compatible = "xxxxx,cst3xx", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, cst3xx_ts_dt_ids);
++#endif
++
++
++static struct i2c_driver cst3xx_ts_driver = {
++	.probe		= cst3xx_ts_probe,
++	.remove		= cst3xx_ts_remove,
++	.id_table	= cst3xx_ts_id,
++	.driver = {
++		.name	= CST3XX_NAME,
++		.owner	= THIS_MODULE,
++		.of_match_table = of_match_ptr(cst3xx_ts_dt_ids),
++		.pm	= &cst3xx_ts_pm_ops,
++	},
++};
++
++module_i2c_driver(cst3xx_ts_driver);
++
++
++MODULE_AUTHOR("Tiben");
++MODULE_DESCRIPTION("SITRONIX CST3XX Touchscreen Controller Driver");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver-ori/cst3xx.h b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver-ori/cst3xx.h
+new file mode 100644
+index 000000000..68791e6af
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver-ori/cst3xx.h
+@@ -0,0 +1,29 @@
++#ifndef TOUCHSCREEN_CST3XX__H
++#define TOUCHSCREEN_CST3XX__H
++
++
++/* -- dirver configure -- */
++#define CFG_MAX_TOUCH_POINTS	1
++#define MAX_AREA	0xff
++
++#define CST3XX_NAME 	"cst3xx"
++
++/*register address*/
++#define CST3XX_ADDRESS 	0x1A
++
++
++/* The platform data for the Focaltech ft5x0x touchscreen driver */
++struct cst3xx_platform_data {
++	unsigned int x_min;
++	unsigned int y_min;
++	unsigned int x_max;
++	unsigned int y_max;
++	unsigned long irqflags;
++	unsigned int int_gpio;
++	unsigned int reset_gpio;
++};
++
++
++
++#endif
++
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver-ori/hyn_cst3xx_RS659_fw.h b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver-ori/hyn_cst3xx_RS659_fw.h
+new file mode 100644
+index 000000000..006c36c81
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver-ori/hyn_cst3xx_RS659_fw.h
+@@ -0,0 +1,1553 @@
++
++#ifndef __CST3xx_FW_H__
++#define __CST3xx_FW_H__
++
++  unsigned char cst3_fw[] ={
++    0x98,0xE0,0x07,0x01,0xB0,0x88,0x01,0x00,0x00,0x00,0x00,0x00,0xB0,0x48,0x01,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x80,0x68,0x06,0x00,0x80,0x68,0x07,0x00,0x00,0x00,0x00,0x00,
++    0x88,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x88,0xD8,0x00,0x00,0x80,0x07,0xC0,0x17,
++    0x82,0x07,0xC0,0x07,0x01,0x65,0x40,0x86,0xC1,0x41,0xC0,0x20,0xC5,0x68,0x31,0x12,
++    0xF5,0x38,0x33,0x5A,0x32,0xA2,0x32,0xEA,0x10,0x62,0x8D,0x0E,0x81,0x07,0xC0,0x97,
++    0x30,0xF2,0xF3,0x79,0x65,0x7E,0x30,0xB2,0x31,0x09,0x10,0x9A,0x87,0x06,0xD0,0xD8,
++    0x35,0x12,0x35,0x5A,0x18,0x9A,0x39,0xC2,0xE0,0xE2,0x03,0x00,0xE0,0xE2,0x04,0x00,
++    0xD0,0x81,0x98,0x16,0x43,0xC6,0x0B,0xC6,0xC2,0xD6,0x3F,0x90,0x99,0x0E,0x40,0x86,
++    0x08,0x86,0xA9,0x0E,0x40,0x23,0x00,0x63,0x38,0x82,0x03,0x00,0x18,0x01,0x20,0x01,
++    0x28,0x01,0x30,0x01,0xD0,0x81,0x98,0x0E,0x0F,0xC6,0xC3,0xDE,0x38,0x90,0x9A,0x06,
++    0x08,0x86,0xA9,0x06,0x03,0x5B,0x38,0x82,0xAE,0xFD,0x30,0x02,0x30,0x02,0xEE,0xFD,
++    0xA8,0x85,0xE8,0x85,0x86,0x2F,0xE0,0x1F,0x37,0x8A,0xB8,0xFF,0xF8,0xAF,0x87,0x0F,
++    0xC0,0xCF,0x85,0x2F,0xE7,0xDF,0xBE,0xFF,0xF8,0x9F,0x87,0x2F,0xE0,0x0F,0x07,0x00,
++    0xAF,0x85,0x6F,0xD2,0xE1,0x43,0x31,0x4A,0xCA,0x01,0x3E,0x30,0x34,0x42,0x80,0x01,
++    0xF6,0x1B,0xF4,0x23,0xF3,0x53,0xC2,0x01,0x70,0x01,0xD8,0x16,0xE7,0x6B,0x4D,0x68,
++    0x80,0x4E,0x28,0x01,0x10,0x6C,0xAE,0x6B,0xA4,0x2B,0x12,0xD2,0x8A,0x16,0xB0,0x63,
++    0x00,0x09,0xB0,0x43,0xE8,0x85,0x37,0x72,0xEA,0x4B,0xE0,0x48,0x91,0x4D,0xAE,0x8B,
++    0x57,0xAC,0x7F,0x5A,0x10,0xEA,0x95,0x0E,0xE7,0x68,0x13,0xAC,0x48,0xF9,0x8F,0x0E,
++    0x10,0x12,0x85,0x16,0xE0,0x0B,0x4A,0x09,0x8B,0x26,0xB0,0x9B,0x09,0x01,0xA8,0x8B,
++    0xA7,0x0B,0xEA,0x85,0x4F,0x09,0x8C,0xE6,0x0A,0x09,0xA0,0x0B,0xE8,0x85,0xAF,0x85,
++    0x66,0xF2,0xE6,0x01,0x00,0x0F,0x80,0x0F,0xE1,0xAF,0xF7,0x03,0x47,0x01,0x80,0xD6,
++    0xEB,0x85,0xA8,0x85,0x70,0xDA,0x2E,0x09,0x1E,0xAB,0x65,0xC2,0xE7,0x03,0x09,0x79,
++    0x01,0x42,0xA0,0x03,0x00,0x0F,0x80,0x0F,0xE1,0x2F,0xE7,0x03,0x37,0x00,0xAE,0xD6,
++    0x05,0x01,0x18,0x83,0xE1,0x03,0x19,0x42,0xA3,0x03,0xE9,0x85,0x42,0x7A,0xC6,0x01,
++    0xE6,0x0B,0x44,0x8A,0x48,0x01,0x80,0x3E,0x4A,0x82,0x06,0x0B,0x0E,0xF9,0x57,0x72,
++    0x8A,0x89,0x97,0x01,0x10,0x8B,0x00,0x17,0x48,0x62,0xCE,0xE1,0x07,0x0B,0x0A,0xF9,
++    0x8E,0x21,0x01,0x0B,0x08,0x09,0x08,0x0B,0x08,0x0B,0x0C,0x31,0x08,0x0B,0x0A,0x59,
++    0x18,0x0B,0x0C,0x81,0x18,0x0B,0x0A,0x01,0x1B,0x0B,0x38,0x82,0xAD,0x85,0x40,0xFA,
++    0xE6,0x03,0x38,0x00,0x81,0x8E,0x00,0xE1,0x83,0x0F,0xC8,0x0F,0x40,0xDA,0x0D,0x01,
++    0xC4,0x01,0xA9,0x0B,0xBE,0xFF,0xFF,0x97,0x4D,0xC2,0x55,0xEA,0xCD,0x01,0x46,0xEA,
++    0x84,0x1F,0xD8,0xCF,0x00,0x01,0x80,0x0F,0xC8,0x77,0xE9,0x85,0xAD,0x85,0x40,0x9A,
++    0xC6,0x01,0xE9,0x03,0x40,0x01,0x88,0x36,0x46,0x82,0xC5,0x01,0xE0,0x03,0x44,0x29,
++    0xCF,0x0E,0xB8,0xFF,0xFD,0xE7,0x64,0x6A,0xE0,0x03,0x39,0x00,0xAF,0x0E,0xB8,0xFF,
++    0xFB,0x07,0xE5,0x03,0x38,0x00,0xAC,0x2E,0x42,0x5A,0xC5,0x01,0x42,0x0B,0x40,0x48,
++    0x00,0x48,0x02,0x0B,0xE7,0x03,0x0B,0xE9,0x03,0x42,0xA0,0x03,0x40,0x52,0xC5,0x03,
++    0x40,0x01,0x80,0x16,0x83,0x0F,0xE0,0xF7,0x38,0xE7,0xEF,0x85,0xAD,0x85,0x48,0x3A,
++    0x04,0x01,0x00,0x43,0x4E,0xEA,0xCC,0x01,0xB2,0x43,0xF0,0x43,0x80,0x0F,0xC8,0xFF,
++    0xEB,0x85,0xA8,0x85,0x30,0x2A,0x20,0x49,0x18,0x22,0x4F,0x01,0x80,0x46,0x68,0x01,
++    0x80,0x16,0x30,0x82,0xC0,0x61,0x00,0x4F,0x30,0x82,0x80,0x61,0x20,0x51,0x00,0x2F,
++    0x68,0x01,0x80,0x0E,0xF0,0x80,0x04,0x0F,0xE0,0x80,0x24,0x51,0x0A,0x01,0xF0,0x0A,
++    0x48,0x01,0xD0,0x06,0x16,0x4A,0x0A,0x40,0x0A,0x01,0xF0,0x8A,0x81,0x2F,0xD8,0xA7,
++    0x40,0xF9,0xEB,0x06,0x00,0xF9,0x6B,0x01,0x87,0x16,0x08,0xF9,0x88,0x09,0xD0,0x40,
++    0xCB,0x00,0xE8,0x85,0xAC,0x85,0x6B,0x2A,0xED,0x01,0xE4,0x43,0x41,0x01,0x80,0x26,
++    0x32,0x62,0xA1,0x01,0x40,0x03,0x41,0x01,0x81,0xFE,0x30,0x0A,0xCC,0x01,0x44,0x2A,
++    0x81,0x17,0xC8,0x3F,0x0F,0x01,0x40,0xF9,0x8D,0xC6,0xF0,0x03,0xE3,0x01,0xB4,0x03,
++    0x11,0x11,0x30,0x02,0x82,0x01,0xA1,0x13,0xA8,0x0B,0x01,0x01,0x12,0x79,0x28,0x29,
++    0x5B,0xE2,0x0B,0x68,0xF8,0x23,0x03,0x37,0x0A,0x21,0x19,0x0A,0xC2,0x48,0xCE,0x48,
++    0x92,0x53,0xE0,0x00,0x94,0x05,0x16,0x22,0xC3,0xB6,0xEF,0x85,0x47,0xF1,0x87,0xE6,
++    0x47,0x01,0x80,0xD6,0xF0,0x00,0x12,0x09,0x44,0x1B,0x01,0x12,0x17,0x9A,0x80,0xA6,
++    0xA3,0x4B,0xED,0x85,0xAB,0x85,0x51,0x92,0x28,0x01,0x20,0x01,0x08,0x01,0x00,0x01,
++    0xC4,0x9B,0x10,0x5A,0xC8,0x06,0x30,0xCA,0x58,0xD1,0x9F,0x0E,0x28,0x09,0x00,0x27,
++    0xE2,0x90,0xE2,0x00,0x90,0x05,0x46,0x31,0x99,0x96,0x4F,0xE1,0x92,0x5E,0x40,0xFA,
++    0xC4,0x01,0xE6,0x03,0x40,0x29,0xC8,0x36,0x41,0x12,0x0B,0x81,0xF3,0x0A,0x4A,0xC1,
++    0xD8,0x0E,0x28,0x09,0x03,0x1F,0xE0,0x20,0x90,0x25,0x67,0x71,0x98,0xF6,0x16,0x01,
++    0x48,0x02,0x6B,0x01,0x82,0x7E,0x40,0x44,0xE4,0x00,0x92,0x05,0x00,0x44,0x42,0xA1,
++    0xCC,0x46,0x40,0x44,0xE4,0x00,0x02,0x44,0x02,0x54,0x42,0x82,0x10,0x09,0xE0,0x0B,
++    0x18,0x8A,0xA0,0x0B,0xEA,0x85,0x01,0x54,0xEF,0x85,0xA9,0x85,0x80,0x3D,0x04,0x01,
++    0x80,0x14,0x80,0x1C,0x00,0x01,0x08,0x01,0x10,0x01,0x90,0x0C,0xD2,0x1C,0x58,0x6A,
++    0x06,0x90,0x32,0x09,0xC5,0x90,0x06,0xB0,0xC9,0xA0,0x34,0x2A,0x18,0x01,0x10,0x01,
++    0xF0,0x12,0xC5,0x80,0x92,0x05,0xE0,0x48,0x90,0x4D,0xF8,0x0C,0x10,0xD2,0xED,0x06,
++    0x90,0x0C,0xA0,0x61,0xE6,0xD8,0x92,0xDD,0x5F,0x71,0x98,0x86,0x84,0x2F,0xD0,0xA7,
++    0x90,0x25,0xC0,0x14,0x10,0x02,0xD5,0x06,0xA0,0x14,0x38,0x01,0x60,0x01,0xE8,0xAE,
++    0x35,0x01,0xF8,0x72,0x10,0x32,0xDD,0x66,0xC6,0x0C,0x78,0x08,0xC2,0x40,0x80,0x00,
++    0x10,0x32,0xD4,0x8E,0x09,0x19,0x30,0x82,0x83,0x2F,0xD0,0xF7,0xD1,0x80,0x01,0x44,
++    0x00,0x57,0x70,0x01,0xE8,0x46,0x00,0x09,0x00,0x44,0x01,0x2F,0x01,0x01,0xF0,0x42,
++    0x10,0x02,0xE5,0x0E,0xD9,0x00,0x00,0x44,0xAB,0x61,0xE0,0xF8,0x90,0xFD,0x7F,0x71,
++    0x98,0xE6,0xC6,0x1C,0xE6,0x00,0x92,0x05,0x80,0x1C,0xC0,0x1C,0x45,0x31,0x98,0x8E,
++    0x00,0x01,0x80,0x24,0x00,0x01,0x08,0x01,0x38,0x01,0xD0,0x24,0x1A,0x61,0x18,0xD2,
++    0x5E,0x22,0xC1,0x98,0x14,0x09,0x06,0x90,0xC0,0xD0,0x34,0xA2,0x18,0x01,0x30,0x01,
++    0xF9,0xB2,0xC4,0x80,0x92,0x05,0xE0,0x48,0x95,0x4D,0x10,0xF2,0xE9,0x06,0x30,0xBA,
++    0xE2,0x90,0xE4,0xD8,0x90,0xDD,0x5E,0x31,0x98,0x8E,0x87,0x2F,0xD0,0x2F,0x92,0x2D,
++    0xC5,0x14,0x10,0x42,0xD0,0x06,0xA8,0x14,0x30,0x01,0x68,0x01,0xE8,0xA6,0x01,0x01,
++    0xF0,0x02,0x81,0x34,0x10,0x42,0xDD,0x9E,0x09,0x19,0x30,0x42,0x81,0x2F,0xD0,0xA7,
++    0xC8,0x34,0xD0,0x40,0x91,0x05,0x00,0x04,0x83,0x2C,0xD8,0xC0,0x41,0x41,0xD1,0x4E,
++    0x00,0x40,0x0B,0x19,0x81,0x2F,0xD0,0x47,0xC8,0x2C,0xD0,0x40,0x01,0x04,0x01,0x0F,
++    0xC0,0x34,0x40,0x01,0xE8,0xF6,0x00,0x09,0x00,0x04,0x01,0xDF,0x00,0xC0,0x06,0x01,
++    0x50,0x07,0x03,0x00,0x18,0x00,0x02,0x42,0x00,0x01,0x00,0x42,0x80,0x60,0x05,0x00,
++    0x58,0xC0,0x02,0x01,0x00,0xA0,0x07,0x01,0x00,0x80,0x00,0x01,0x10,0x00,0x00,0x42,
++    0x10,0xC0,0x00,0x01,0x00,0x00,0x00,0x01,0x01,0x01,0xF0,0x02,0x10,0x42,0xE5,0x0E,
++    0xD9,0x00,0x02,0x04,0xE3,0x20,0xE5,0xB0,0x90,0xB5,0x77,0x31,0x98,0xEE,0xC5,0x24,
++    0xE6,0x00,0x92,0x05,0x80,0x24,0xC0,0x24,0x44,0x71,0x98,0x9E,0xC5,0x14,0x50,0xD2,
++    0x40,0xE1,0xD1,0x26,0x7A,0x40,0xCF,0x00,0x82,0x00,0x82,0x83,0x00,0x0F,0x00,0xF1,
++    0x82,0x83,0xC2,0x8B,0x40,0xAA,0x4D,0x01,0x82,0x4E,0xF0,0x48,0x81,0x8B,0x8A,0x41,
++    0x32,0x12,0xD0,0x01,0x88,0x8B,0x08,0x31,0x98,0x0B,0x86,0x3D,0xE8,0x85,0x0F,0x11,
++    0x9F,0x0B,0x3E,0xD7,0xAD,0x85,0x47,0x6A,0x72,0x6A,0xC5,0x01,0xF1,0x2B,0x04,0x09,
++    0x09,0x00,0xC4,0xA0,0x69,0x09,0xC8,0x66,0x1F,0x01,0x10,0xF9,0x02,0x01,0x38,0x19,
++    0x08,0xF8,0x03,0x57,0x0A,0x31,0x18,0x0A,0xCE,0x48,0xCC,0x48,0x54,0x4C,0x10,0xCA,
++    0xC8,0x0E,0x30,0x5A,0x32,0x12,0xE0,0x00,0x94,0x05,0x16,0x2A,0xC7,0x96,0x57,0xF9,
++    0x82,0xBE,0x00,0x80,0xC9,0x08,0x04,0x09,0x08,0x00,0xC4,0x40,0xF1,0x0B,0xB0,0x0B,
++    0xF3,0x03,0xB2,0x03,0x02,0x31,0x18,0x12,0xCE,0x80,0xCC,0x00,0x4C,0xCA,0x4C,0x14,
++    0x0E,0x54,0x4C,0x14,0x08,0x54,0x56,0x04,0x14,0x44,0x48,0xA2,0x02,0x09,0xC8,0x01,
++    0xB4,0x43,0x44,0x92,0x3A,0x01,0xC0,0x01,0xF4,0x03,0x6C,0x7A,0x41,0x01,0x80,0x8E,
++    0xF3,0x03,0xF1,0x13,0x48,0x5C,0x0B,0x61,0x19,0xCA,0x4A,0x64,0xCB,0x48,0x04,0x30,
++    0xC8,0x48,0x34,0x19,0x14,0xB0,0xC9,0x70,0x0B,0x21,0xF0,0x8A,0x48,0x81,0xDA,0x06,
++    0x00,0x7C,0x47,0x01,0x80,0x0E,0x40,0x29,0x8D,0xCE,0x10,0x02,0x8C,0xBE,0x10,0xD2,
++    0x88,0xAE,0x18,0x61,0xF6,0x5A,0xD7,0x58,0x98,0x49,0x58,0x91,0xC7,0x7E,0x40,0x5C,
++    0x65,0x0A,0x14,0x1A,0x92,0x0E,0xE0,0xD8,0x07,0x5C,0x47,0x5C,0x58,0x41,0xCE,0x36,
++    0x03,0x7C,0x5F,0xD2,0x34,0x09,0x98,0x01,0xE1,0xE3,0x18,0xA2,0xA1,0xE3,0x08,0x44,
++    0x0D,0x54,0x0B,0x4C,0x42,0xAA,0xC3,0x01,0x51,0x04,0x46,0x91,0xCF,0x06,0x00,0x7C,
++    0xEF,0x85,0xAF,0x85,0x80,0x3D,0x2C,0x01,0x20,0x01,0x00,0x61,0x4B,0x82,0x1B,0x42,
++    0xC0,0x00,0x82,0x34,0x30,0x01,0x38,0x01,0x00,0x01,0x80,0x1C,0x80,0x14,0xC0,0x34,
++    0x00,0x08,0x13,0x19,0xC0,0x00,0x12,0x90,0xC0,0x10,0x04,0x21,0x90,0x2C,0xF0,0x82,
++    0x80,0x24,0x60,0x01,0x83,0x46,0xF0,0x10,0xDA,0x34,0x00,0x90,0xC0,0xD0,0x1C,0x19,
++    0x16,0xD8,0xC0,0x90,0x34,0x21,0xF8,0xB2,0x68,0x01,0x80,0x56,0xF0,0x50,0x1B,0x61,
++    0x1A,0xD2,0x5A,0xFA,0xC0,0x90,0x1E,0x19,0xC0,0x90,0x12,0xD8,0xC0,0x90,0x3E,0x21,
++    0xF8,0xBA,0x66,0x29,0x83,0x4E,0xE0,0x18,0xD2,0x34,0x00,0xD8,0xC0,0x90,0x1E,0x19,
++    0x16,0xD8,0xC0,0x90,0x1E,0x21,0xF0,0x9A,0x98,0x1C,0x68,0x69,0x83,0x5E,0xE0,0x50,
++    0x1A,0x61,0x18,0xD2,0x5E,0x92,0xC2,0x90,0xC0,0x88,0x12,0x19,0x14,0x90,0xC0,0x50,
++    0x0A,0x21,0xF0,0x8A,0x88,0x14,0x08,0x09,0x89,0x0C,0x70,0x41,0xD1,0x3E,0x78,0x41,
++    0xD0,0x2E,0xC8,0x1C,0x48,0x41,0xD1,0x16,0xC9,0x14,0x48,0x41,0xD8,0x0E,0x08,0x01,
++    0x88,0x0C,0x08,0x19,0x80,0x2F,0xC8,0x47,0x10,0x82,0xED,0x3E,0x10,0xC2,0xED,0x2E,
++    0xCC,0x1C,0x10,0x42,0xE8,0x16,0xC8,0x14,0x10,0x42,0xE4,0x0E,0x00,0x01,0x80,0x0C,
++    0xC0,0x0C,0x40,0x01,0x80,0x36,0xC0,0x24,0x78,0x08,0xC6,0x48,0x82,0x48,0xD2,0x00,
++    0xCC,0x2C,0x00,0x44,0xE7,0x20,0x93,0x25,0x64,0x31,0x98,0x9E,0xE7,0x68,0x93,0x6D,
++    0x6C,0x71,0x98,0x4E,0x3B,0x4F,0xA8,0x85,0x48,0x9A,0x01,0x01,0x06,0x44,0x04,0x44,
++    0x82,0x43,0x80,0x43,0x40,0x8A,0x29,0x09,0x80,0x01,0xE4,0x0B,0x18,0x4A,0xA1,0x0B,
++    0x31,0x22,0xE0,0x01,0x07,0x9F,0xBA,0xFF,0xE9,0xCF,0x43,0x82,0xC0,0x03,0x40,0x01,
++    0x81,0x1E,0x48,0x52,0x02,0xC1,0xC8,0x01,0xB1,0x43,0x40,0x42,0x51,0x62,0x49,0x42,
++    0xC0,0x01,0x82,0x1F,0xF7,0x0F,0xBD,0xFF,0xE9,0x4F,0x49,0x22,0x52,0x42,0xC9,0x01,
++    0x40,0x1A,0x81,0x27,0xC1,0x17,0x4C,0x0A,0x52,0x2A,0xC9,0x01,0x40,0x02,0x81,0x27,
++    0xFF,0x0F,0xBC,0xFF,0xEF,0x3F,0xEE,0x03,0x40,0x01,0x80,0x16,0xE8,0x03,0x47,0x11,
++    0x89,0x1E,0x40,0x02,0x41,0x0B,0x18,0x4A,0x00,0x0B,0x40,0xC2,0x0E,0x11,0x98,0x0B,
++    0x32,0x0A,0xC8,0x01,0x40,0xB2,0x80,0x27,0xE8,0xC7,0x4D,0xA2,0x42,0xA2,0xC8,0x01,
++    0x86,0x27,0xE0,0x7F,0xBF,0xFF,0xEF,0x4F,0xB9,0xFF,0xFF,0xDF,0x48,0x7A,0x40,0x82,
++    0xC8,0x01,0x82,0x27,0xE0,0xF7,0x4A,0x6A,0x12,0x01,0xC8,0x01,0x40,0x62,0x58,0x92,
++    0x85,0x17,0xE8,0x57,0xBD,0xFF,0xF7,0xB7,0xBB,0xFF,0xE7,0xD7,0x48,0x3A,0x40,0x42,
++    0xC8,0x01,0x82,0x0F,0xF0,0x6F,0x80,0x07,0xDF,0x47,0xB8,0xFF,0xE7,0xFF,0xEF,0x03,
++    0x45,0x31,0x88,0x46,0xE8,0x85,0x03,0x00,0x00,0x00,0x00,0x01,0x00,0xC0,0x02,0x01,
++    0x00,0xA0,0x07,0x01,0x48,0xA0,0x02,0x01,0x38,0x81,0x00,0x00,0x00,0x80,0x00,0x01,
++    0x58,0xC0,0x02,0x01,0xF8,0x00,0x06,0x42,0x18,0xD8,0x05,0x00,0xA8,0x85,0x33,0x22,
++    0xF0,0x03,0x83,0x07,0xF1,0xA7,0x41,0x9A,0x2C,0x01,0x00,0x2B,0xB5,0x2B,0x01,0xB1,
++    0xAF,0x2A,0xB8,0xFF,0xE4,0x1F,0xA5,0x01,0xFA,0x03,0x31,0x08,0x42,0x72,0x71,0x48,
++    0x1C,0x0B,0x5C,0x0B,0x02,0x48,0x1A,0x0B,0x09,0x2B,0xFE,0x0B,0x30,0x48,0xA8,0x16,
++    0x0E,0x09,0x04,0x0B,0x1B,0x2B,0xE8,0x85,0xAD,0x85,0x87,0x9D,0x42,0x32,0xC1,0x01,
++    0x42,0x0B,0x40,0x48,0x00,0x48,0x02,0x0B,0x51,0x22,0x49,0x2A,0x40,0x2A,0x81,0x0F,
++    0xC1,0x97,0x67,0x1A,0x35,0x2A,0xA9,0x01,0x01,0xBF,0x41,0x0A,0xBE,0xFF,0xFF,0x77,
++    0x52,0x03,0x81,0x01,0xE7,0x03,0x40,0x79,0x80,0x0E,0x51,0xEA,0x48,0xEA,0x00,0x01,
++    0x58,0xD2,0x80,0x07,0xF8,0x2F,0x51,0xD2,0x48,0xD2,0x00,0x09,0x58,0xBA,0x80,0x07,
++    0xF9,0xFF,0x50,0x03,0x80,0x01,0xE2,0x03,0x40,0x59,0x8D,0x86,0x40,0xB2,0x48,0xAA,
++    0x88,0xA1,0x11,0x01,0xD5,0x3B,0xD7,0x1B,0x18,0xFA,0x42,0x5C,0x44,0x34,0xD8,0xD8,
++    0x04,0x1C,0xE0,0x00,0xE2,0x48,0xE4,0x90,0x95,0x95,0x14,0xD2,0x99,0xAE,0x57,0x03,
++    0x80,0x01,0xE2,0x03,0x40,0x59,0x85,0x2E,0x50,0x42,0x48,0x4A,0x40,0x4A,0x58,0x0D,
++    0x80,0x0F,0xC0,0xBF,0x40,0x0D,0x80,0x07,0xDF,0xFF,0xE9,0x43,0x46,0x31,0x80,0x26,
++    0x87,0x9D,0xE9,0x85,0x10,0x00,0x00,0x42,0x00,0x01,0x00,0x42,0x58,0xC0,0x02,0x01,
++    0x00,0xC0,0x00,0x01,0x00,0xA0,0x07,0x01,0x18,0xC0,0x07,0x01,0x4C,0xFA,0x6F,0x54,
++    0x82,0x13,0x68,0x54,0x80,0x13,0x32,0x52,0x92,0x01,0xF5,0x93,0x80,0x13,0xCC,0x4B,
++    0x83,0x0B,0x3E,0x82,0xA8,0x85,0xF3,0x24,0x63,0xC2,0xFF,0x23,0x11,0x22,0xCC,0x56,
++    0x23,0x21,0x19,0x02,0x60,0xB2,0xCF,0x00,0x23,0x29,0x0A,0x20,0xCE,0x00,0x50,0x24,
++    0x58,0x2C,0x48,0x09,0x8E,0x26,0x50,0x0C,0x23,0xF9,0xA7,0x49,0xD4,0x08,0x93,0x65,
++    0x50,0x09,0x88,0x26,0x58,0x0C,0x10,0xC9,0x0A,0x90,0xD2,0x88,0x90,0x6D,0xD4,0x0B,
++    0xD0,0x13,0x0A,0x48,0x00,0x90,0x1A,0x8A,0x81,0xCB,0x48,0x08,0x81,0xCB,0x4A,0x48,
++    0x81,0xCB,0x0C,0x08,0x38,0x50,0x79,0x90,0x1E,0x8A,0x80,0xCB,0x58,0x04,0x8A,0xC3,
++    0xC2,0x83,0xE9,0x00,0x83,0x83,0xE9,0x85,0xAC,0x85,0x87,0x2D,0x0F,0x01,0x00,0x0D,
++    0x40,0x2E,0x90,0x24,0x86,0x1C,0x40,0xEA,0xFA,0x2B,0xF8,0x1B,0x06,0x01,0x60,0xFA,
++    0x51,0xFA,0xC6,0x33,0x70,0x59,0x85,0x1E,0xE4,0x00,0x92,0x05,0x17,0x82,0x9C,0xC6,
++    0x50,0xE2,0x46,0x83,0x31,0x09,0x18,0x82,0x07,0x83,0x00,0xF9,0x80,0x03,0x69,0x01,
++    0x80,0xBE,0x08,0x01,0x50,0x1D,0x00,0x01,0x2E,0x29,0x62,0x8A,0x08,0x68,0x03,0x77,
++    0x32,0x21,0x19,0x32,0xCB,0xB0,0xC9,0xB0,0xD0,0xB3,0x75,0x09,0x88,0x2E,0x80,0x83,
++    0xE6,0x48,0x92,0x4D,0xE0,0x90,0x4A,0x29,0x82,0x1E,0xE0,0x00,0x94,0x05,0x16,0xC2,
++    0x98,0x76,0x8F,0x0C,0x60,0x4A,0x6E,0x1D,0x36,0x01,0x78,0x22,0xB9,0x01,0x06,0x0F,
++    0x70,0x01,0x88,0x9E,0x50,0x15,0x90,0x04,0x11,0x01,0xC0,0x43,0x30,0x1A,0x31,0x8A,
++    0xBC,0xFF,0xFF,0x47,0xE5,0x68,0xE3,0xC3,0xCE,0x0C,0x48,0x00,0x08,0x00,0x1E,0x42,
++    0x8D,0x03,0x03,0x59,0x8D,0x03,0xED,0x20,0xE0,0x20,0x03,0x4F,0x50,0x15,0x90,0x04,
++    0x11,0x01,0xC0,0x43,0x30,0x1A,0x31,0x8A,0xBB,0xFF,0xFF,0xA7,0xE3,0x68,0xEB,0x20,
++    0xE7,0xB0,0x93,0xB5,0xC4,0x0C,0x10,0x32,0x9D,0xD6,0xE6,0xC3,0x1E,0x01,0x4C,0x08,
++    0x48,0x01,0x80,0x96,0xC8,0x0C,0x48,0x01,0x81,0x36,0x80,0x03,0xEB,0xC3,0x81,0x03,
++    0x05,0x59,0x85,0x03,0xE0,0x20,0x05,0x37,0x81,0x03,0xE9,0xC3,0x83,0x03,0x8B,0x1B,
++    0x05,0x59,0x8D,0x03,0xEB,0x20,0xE5,0x20,0x00,0x2F,0xC0,0x0C,0x40,0x09,0xC8,0x16,
++    0x01,0x59,0x85,0x03,0xE1,0x20,0x33,0x02,0xBA,0xFF,0xFF,0x07,0x4A,0x32,0x45,0x43,
++    0x10,0x01,0x1A,0x82,0x05,0x43,0x4A,0x2A,0x40,0x43,0x1A,0xC2,0x03,0x43,0xE2,0xC3,
++    0x08,0x11,0x18,0x42,0xA0,0xC3,0x83,0x2D,0xEF,0x85,0xAF,0xFD,0x80,0x0D,0xFC,0x54,
++    0x30,0x32,0x30,0x62,0x6E,0xAA,0xAC,0x01,0x50,0x09,0x88,0x4E,0x00,0x0F,0x80,0x0F,
++    0xC1,0xCF,0xE1,0x43,0x37,0x00,0xAA,0xD6,0xE5,0x43,0x09,0xF9,0x01,0x42,0xA0,0x43,
++    0x04,0x09,0x30,0x22,0x51,0xAA,0x04,0x8F,0x60,0x01,0xC1,0x2E,0xF7,0x00,0x0B,0x01,
++    0x1A,0x42,0x08,0x83,0x30,0x0A,0x01,0x17,0x02,0xF9,0x0F,0x83,0x08,0x01,0x19,0x01,
++    0x08,0x9B,0x04,0x01,0x00,0x4F,0x78,0x01,0x88,0x16,0x18,0x01,0x00,0x9B,0x06,0x17,
++    0xC6,0x9B,0x01,0x9B,0xCA,0xB0,0xE7,0x00,0x94,0x05,0x14,0x42,0x9B,0x9E,0x37,0x02,
++    0x40,0x01,0x80,0x26,0x04,0xA1,0x00,0x83,0x04,0x01,0x30,0x22,0x00,0x0F,0x00,0x21,
++    0x03,0x83,0xD4,0x00,0x92,0x25,0x44,0x83,0x08,0x01,0x1C,0x42,0x01,0x83,0xE2,0x43,
++    0x37,0x00,0xAA,0xE6,0xE5,0x43,0x09,0xF9,0x01,0x42,0xA0,0x43,0x66,0x01,0x88,0x5E,
++    0xC0,0x24,0x40,0x09,0x88,0x7E,0x05,0x01,0x02,0x83,0x44,0x83,0x08,0x01,0x1C,0x42,
++    0x05,0x83,0x3A,0x47,0xAC,0x9D,0x87,0x1D,0x20,0x01,0x00,0x01,0x80,0x0C,0x70,0x15,
++    0x40,0x52,0xF3,0x03,0xEE,0x00,0x92,0x3D,0x6E,0x42,0xAB,0x01,0x00,0xAF,0x81,0x07,
++    0xF9,0x0F,0xE7,0x43,0x30,0x00,0xA2,0x1E,0x40,0x22,0xF3,0x03,0x17,0xC2,0x9D,0xB6,
++    0x40,0x12,0xF3,0x03,0x10,0xC2,0x9D,0x06,0x21,0x11,0xE0,0x43,0x08,0xF9,0x05,0x42,
++    0xA3,0x43,0x41,0x32,0x46,0x0B,0x14,0x79,0x00,0x8A,0x48,0x09,0x88,0x9E,0x08,0x01,
++    0x0E,0x0B,0x44,0x0B,0x83,0x8B,0xE1,0xB0,0xE7,0x20,0x93,0x25,0x60,0x11,0x88,0x56,
++    0x30,0x5A,0xD3,0xCB,0xD4,0x1C,0x10,0x8A,0x8A,0x2E,0xD0,0xCB,0xD4,0x24,0x10,0x8A,
++    0x88,0x0E,0x08,0x09,0x8F,0x0C,0x08,0x01,0x08,0x0B,0x0A,0x01,0x08,0x0B,0x0C,0x81,
++    0x02,0x0B,0x44,0x0B,0x10,0x01,0x1C,0x8A,0x00,0x0B,0x62,0x11,0x88,0x4E,0xC6,0x0C,
++    0x3A,0x0F,0x4B,0x52,0x58,0x54,0x86,0x13,0x12,0x01,0x80,0x13,0xE4,0x4B,0x82,0x0B,
++    0x4A,0x62,0x8A,0x01,0x5E,0x53,0x84,0x13,0x58,0x53,0x8A,0x13,0x12,0x91,0x88,0x13,
++    0x14,0x19,0x88,0x13,0x4E,0x53,0x8E,0x13,0x48,0x53,0x94,0x13,0x4A,0x4B,0x92,0x0B,
++    0x0C,0x09,0x90,0x0B,0x3F,0x82,0xAB,0x85,0x80,0x4D,0x34,0x22,0x30,0x01,0x00,0x01,
++    0x80,0x2C,0x38,0x01,0x4C,0xCA,0xD1,0x43,0xD2,0x4B,0x1E,0x42,0x81,0x14,0x40,0xC2,
++    0x80,0x61,0x80,0x24,0xC0,0x61,0x80,0x1C,0x60,0x09,0x80,0x0E,0x60,0x29,0x88,0x76,
++    0x60,0x09,0x88,0x1E,0x70,0xD2,0xB1,0x2C,0x78,0xD2,0x01,0x27,0x73,0xD2,0xE1,0x80,
++    0x81,0x2C,0x78,0xC2,0xF8,0x81,0x41,0x35,0xBA,0xFF,0xF7,0xC7,0x00,0x3F,0x60,0x21,
++    0x89,0x2E,0x70,0xB2,0x47,0x35,0xB8,0xFF,0xF9,0xE7,0x7D,0x92,0xB9,0xA1,0x6A,0x3A,
++    0xA9,0x01,0xE6,0x43,0x08,0xF9,0x05,0x42,0xA1,0x43,0xE1,0x43,0x08,0x01,0x19,0x42,
++    0xA1,0x43,0x41,0x4A,0x42,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,0x4A,0x3A,0x41,0x43,
++    0x10,0x01,0x1C,0x82,0x01,0x43,0x4A,0x1A,0x40,0x43,0x10,0x09,0x18,0x82,0x00,0x43,
++    0x0C,0x09,0x00,0x01,0xBA,0xFF,0xFF,0xB7,0x42,0x09,0x88,0x66,0x62,0x21,0x88,0x5E,
++    0x10,0x09,0x90,0x04,0x30,0x82,0x19,0x01,0xCF,0x14,0xB8,0xFF,0xF0,0xB7,0x17,0x09,
++    0x90,0x04,0x10,0x01,0x08,0x59,0x40,0x35,0x37,0x9A,0xB8,0xFF,0xF0,0x77,0x17,0x09,
++    0x90,0x04,0x10,0x01,0x09,0x31,0x30,0xC2,0x37,0x9A,0xB8,0xFF,0xF0,0x37,0x17,0x09,
++    0x90,0x04,0x40,0xA2,0x10,0x01,0x08,0x71,0xC0,0x21,0x32,0x9A,0xBE,0xFF,0xF7,0xEF,
++    0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x31,0x30,0x9A,0xC0,0x24,0xBE,0xFF,0xF7,0xAF,
++    0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x31,0x18,0x09,0x00,0xCF,0x00,0xC0,0x00,0x01,
++    0x00,0xA0,0x07,0x01,0xFF,0xFF,0xFF,0xFF,0x00,0xF8,0x07,0x00,0x58,0x20,0x00,0x01,
++    0x90,0xE4,0x03,0x00,0xF8,0x00,0x06,0x42,0x00,0x00,0x06,0x42,0x80,0x01,0x06,0x42,
++    0x10,0xC0,0x00,0x01,0x40,0x60,0x07,0x01,0x18,0xC0,0x07,0x01,0x38,0xC0,0x05,0x01,
++    0xC7,0x1C,0xB8,0xFF,0xF2,0x97,0x05,0x27,0x60,0x09,0x80,0x0E,0x62,0x29,0x88,0x06,
++    0x60,0x09,0x88,0x76,0x10,0x09,0x90,0x04,0x30,0x82,0x19,0x01,0xCF,0x14,0xB8,0xFF,
++    0xF0,0x27,0x15,0x01,0x90,0x04,0x30,0x9A,0xC8,0x14,0xC0,0x2C,0xBC,0xFF,0xF7,0xEF,
++    0x00,0x7F,0x10,0x11,0x90,0x04,0x10,0x09,0x30,0x82,0x19,0x01,0xCF,0x14,0xB8,0xFF,
++    0xF0,0xA7,0x14,0x11,0x90,0x04,0x10,0x01,0x30,0x9A,0xC8,0x14,0xC7,0x2C,0xB8,0xFF,
++    0xF0,0x67,0x14,0x09,0x90,0x04,0x10,0x01,0x08,0x21,0x40,0x35,0x37,0x9A,0xB8,0xFF,
++    0xF0,0x27,0x14,0x09,0x90,0x04,0x10,0x01,0x09,0x41,0x31,0xC2,0x37,0x9A,0xB8,0xFF,
++    0xF0,0xE7,0x13,0x09,0x90,0x04,0x10,0x01,0x08,0x31,0x30,0x9A,0xC7,0x24,0xB8,0xFF,
++    0xF0,0xA7,0x13,0x09,0x90,0x04,0x10,0x01,0x08,0x31,0x18,0x09,0xC7,0x1C,0xB8,0xFF,
++    0xF1,0x67,0xE3,0x43,0x08,0xF9,0x06,0x42,0xA5,0x43,0x41,0x32,0x42,0x0B,0x40,0x48,
++    0x00,0x48,0x02,0x0B,0x47,0x22,0x0D,0x01,0x08,0x0B,0x0A,0x01,0x02,0x0B,0x44,0x0B,
++    0x10,0x01,0x1C,0x8A,0x00,0x0B,0x82,0x4D,0xEB,0x85,0xAF,0x85,0x67,0xFA,0xEC,0x03,
++    0x28,0x01,0x40,0x09,0x87,0x16,0xE8,0x03,0x40,0x29,0x88,0x5E,0x71,0xE2,0xC4,0x83,
++    0x40,0x11,0x98,0x26,0xEF,0x03,0xBF,0xFF,0xF1,0xF7,0x87,0xAB,0xEA,0x85,0xE3,0x00,
++    0x83,0x83,0xE9,0x85,0xE8,0x03,0x47,0x21,0x8F,0x26,0xB8,0xFF,0xF0,0xA7,0x07,0x19,
++    0xAB,0x03,0xEF,0x85,0xE8,0x03,0x47,0x19,0x87,0xDE,0xEF,0x03,0x47,0x31,0x80,0xC6,
++    0x4D,0x72,0xCC,0x01,0xF8,0x43,0x40,0x01,0x88,0x3E,0x30,0x42,0x80,0x01,0xF6,0x13,
++    0x50,0x31,0x98,0x3E,0xE0,0x03,0x34,0x00,0xAC,0x26,0x40,0x42,0xC4,0x01,0xE3,0x03,
++    0x40,0x01,0x80,0xA6,0xE8,0x03,0x47,0x01,0x8E,0x1E,0x57,0x44,0x47,0x31,0x88,0x06,
++    0x45,0x22,0x0C,0x59,0x82,0x0B,0x80,0x2B,0x86,0x2B,0x84,0x2B,0x8A,0x2B,0x88,0x2B,
++    0x8B,0x0B,0x44,0xE2,0x42,0x0B,0x40,0x48,0x00,0x48,0x02,0x0B,0xEF,0x85,0xBB,0xFF,
++    0xEB,0xDF,0xEB,0x85,0xA8,0xC5,0x27,0x01,0x30,0x1A,0x00,0x09,0x4B,0xBA,0x6B,0xD2,
++    0x30,0x01,0x59,0x51,0x80,0xE6,0xE1,0x4E,0x79,0xC2,0xE3,0xD3,0x87,0x27,0xE8,0xDF,
++    0x61,0x52,0x20,0x09,0x39,0x61,0x62,0x52,0x71,0x61,0x62,0x92,0x40,0x7A,0x13,0x31,
++    0xC0,0x01,0x55,0x03,0x80,0x01,0x5A,0xC9,0x80,0xAE,0xE1,0x4E,0x59,0x59,0x80,0x56,
++    0x59,0x61,0x80,0x66,0x59,0x69,0x88,0xBE,0x06,0x29,0xA8,0x43,0x21,0x09,0x00,0x9F,
++    0x59,0xD1,0x80,0x6E,0x59,0x01,0x89,0x7E,0xA8,0x53,0x26,0x09,0x08,0x59,0xA5,0x0B,
++    0x00,0x57,0x01,0x39,0xA9,0x43,0x06,0x3F,0x86,0x07,0xE8,0xF7,0x00,0x27,0x19,0x12,
++    0xA1,0xD3,0x01,0x0F,0x00,0x41,0x18,0x12,0xA0,0xD3,0x01,0xEF,0x06,0x11,0xA8,0x43,
++    0x20,0x09,0x00,0xCF,0x06,0x01,0xA8,0x43,0x41,0x43,0x19,0x82,0x00,0x43,0x01,0x9F,
++    0xA8,0x43,0x26,0x09,0x00,0x87,0x00,0x19,0xA8,0x43,0x26,0x09,0x00,0x67,0x00,0x21,
++    0xA8,0x43,0x26,0x09,0x06,0x47,0xA8,0x53,0x26,0x09,0x08,0x69,0xA0,0x0B,0x00,0x1F,
++    0xA8,0x53,0x26,0x09,0x08,0x79,0xA7,0x0B,0x60,0x01,0x80,0x66,0x40,0x82,0x42,0x0B,
++    0x30,0x48,0xA8,0x2E,0x08,0x81,0x06,0x0B,0x08,0x81,0x02,0x0B,0x08,0x81,0x00,0x0B,
++    0x45,0x43,0x19,0x82,0x07,0x43,0xE9,0xC5,0xAC,0x8D,0x87,0x25,0x40,0x4A,0x82,0x14,
++    0x45,0x12,0xC2,0x01,0xD6,0x2B,0xD4,0x33,0x08,0x01,0xB0,0x0B,0x61,0x1A,0xE2,0x0B,
++    0x10,0xF9,0x05,0x8A,0xA1,0x0B,0xE1,0x0B,0x10,0x01,0x19,0x8A,0xA2,0x0B,0x51,0x02,
++    0x92,0x01,0x46,0x8B,0x18,0x01,0x1A,0xCA,0x01,0x8B,0x52,0xBA,0x44,0x8B,0x1A,0x01,
++    0x1A,0xCA,0x00,0x8B,0x79,0x9A,0x41,0xCB,0x10,0x09,0x18,0x8A,0x00,0xCB,0x51,0x03,
++    0x80,0x01,0xE2,0x0B,0x49,0x79,0x87,0xDE,0xE6,0x03,0x40,0x69,0x88,0x46,0x09,0xA9,
++    0x07,0x91,0xB8,0xFF,0xE8,0x3F,0x46,0x09,0x89,0x0E,0x32,0x42,0x1A,0x82,0x03,0x08,
++    0x10,0x09,0x88,0x1C,0x94,0x04,0x90,0x4D,0x18,0x01,0xC0,0x14,0xBB,0xFF,0xEF,0x2F,
++    0x42,0xC3,0x41,0x00,0x01,0x00,0x02,0xC3,0x40,0x5A,0x11,0x09,0x90,0x04,0xC8,0x1C,
++    0x14,0x01,0x90,0x4D,0x37,0x9A,0xB8,0xFF,0xE8,0xC7,0xC2,0x24,0x15,0x09,0xC8,0x48,
++    0xE8,0x48,0x90,0x04,0x00,0x48,0x12,0x01,0x1F,0x09,0xB8,0xFF,0xE8,0x77,0x02,0xF7,
++    0x08,0xA1,0x00,0x91,0xBC,0xFF,0xEF,0xF7,0x40,0x09,0x88,0xC6,0x18,0xAA,0x13,0x09,
++    0x20,0x40,0x63,0x08,0x90,0x04,0x30,0x9A,0xC7,0x14,0xB8,0xFF,0xE8,0xF7,0x01,0x77,
++    0x08,0xB1,0x00,0x91,0xBC,0xFF,0xEF,0x77,0x40,0x09,0x88,0x46,0xC0,0x24,0x10,0x09,
++    0xC8,0x48,0xED,0x48,0x00,0x48,0x32,0x9A,0x97,0x04,0xB8,0xFF,0xE9,0x77,0xE1,0x03,
++    0x08,0xF9,0x06,0x42,0xA1,0x03,0x41,0xC3,0x42,0x00,0x02,0x00,0x00,0xC3,0x41,0x32,
++    0x0A,0x01,0x0F,0x0B,0x0C,0x01,0x00,0x0B,0x44,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,
++    0x28,0xCF,0x00,0x00,0xF8,0x00,0x06,0x42,0x80,0x01,0x06,0x42,0x00,0xC0,0x05,0x01,
++    0x00,0x70,0x00,0x01,0x58,0x20,0x00,0x01,0x10,0x00,0x00,0x42,0x00,0xC0,0x06,0x01,
++    0x00,0x00,0x00,0x42,0x18,0xC0,0x07,0x01,0x08,0x40,0x01,0x01,0x52,0xCA,0x42,0x83,
++    0x02,0x83,0x42,0xCA,0xF7,0x0B,0x48,0xF9,0x90,0x16,0xF0,0x0B,0xE0,0x48,0xB2,0x0B,
++    0xF0,0x03,0x40,0xC1,0x90,0x0E,0x00,0x01,0x03,0x83,0x3C,0x82,0x4C,0x9A,0x4A,0x53,
++    0x58,0x8A,0xE2,0xC3,0x1C,0x12,0x0C,0x53,0x10,0x43,0x02,0x09,0xB3,0xC3,0x38,0x82,
++    0xAA,0x85,0x40,0x72,0x84,0x01,0x42,0x0B,0x10,0x01,0x1C,0x8A,0x02,0x0B,0x54,0x62,
++    0x4A,0x4A,0x42,0x62,0x85,0x27,0xC0,0xAF,0xEF,0x85,0xA8,0xC5,0x46,0x32,0x82,0x01,
++    0xE2,0x0B,0x78,0x4A,0x30,0x48,0xAC,0x46,0xE2,0x0B,0x10,0x01,0x18,0x8A,0xA0,0x0B,
++    0x44,0xC3,0x0B,0x01,0x1B,0x42,0x04,0xC3,0xE8,0xC5,0x17,0x01,0x0D,0xD3,0x45,0xCB,
++    0x6E,0xEA,0x01,0x79,0x01,0x0A,0x30,0x72,0x59,0x02,0xB2,0x01,0x61,0x44,0x57,0x63,
++    0x48,0x09,0x80,0xDE,0x48,0x29,0x80,0x46,0x4B,0x41,0x88,0x46,0x8F,0x93,0x43,0xCB,
++    0x38,0x48,0x8E,0x16,0x05,0x81,0x00,0xC3,0xED,0xC5,0x0F,0xD3,0x10,0xC2,0x8C,0x16,
++    0x07,0x29,0x05,0xC3,0x01,0x3F,0xE0,0x0A,0x02,0xCB,0xE7,0x00,0x97,0x05,0x24,0x44,
++    0x40,0x89,0x9A,0x06,0x20,0x5C,0x07,0xA1,0x07,0xC3,0xED,0xC5,0xC8,0x8B,0x4B,0x11,
++    0x91,0xE6,0x61,0x7A,0x48,0x01,0x88,0x2E,0x43,0xC3,0x07,0x04,0x41,0x6A,0x11,0x43,
++    0x21,0x54,0x07,0xF7,0x43,0xC3,0x47,0x0C,0x10,0x48,0xC0,0x40,0x96,0x25,0x04,0x89,
++    0x11,0x00,0xD0,0x00,0x40,0x01,0xC1,0x76,0x97,0x05,0xBF,0xFF,0xF1,0x1F,0x44,0x32,
++    0x11,0x22,0x8C,0x76,0x00,0x09,0x80,0x07,0xC8,0xD7,0x03,0xC1,0xB1,0x43,0x49,0x02,
++    0x00,0x09,0x80,0x43,0x00,0x2F,0x41,0xC2,0x86,0x01,0xED,0x03,0x08,0x69,0x18,0x48,
++    0x40,0x01,0x88,0x36,0xD2,0x00,0x43,0x81,0xC7,0x0E,0x20,0x44,0x07,0xCF,0x20,0x5C,
++    0x00,0xBF,0x40,0xD2,0xC1,0x00,0x41,0x19,0xC7,0x1E,0x20,0x44,0x41,0xC2,0x10,0x43,
++    0x03,0x7F,0xD0,0x00,0x40,0xB1,0xC1,0x66,0x20,0x44,0x07,0x57,0x10,0xC2,0x84,0x46,
++    0x41,0xCB,0xA7,0x0A,0x62,0x44,0xE7,0x00,0x97,0x05,0x24,0x44,0x40,0x89,0x9A,0x06,
++    0x23,0x5C,0xCF,0x83,0xE3,0x00,0x8A,0x83,0x05,0x81,0x00,0xC3,0xED,0xC5,0x07,0xD3,
++    0xE8,0xC5,0x07,0x00,0x10,0x00,0x00,0x42,0x00,0xC0,0x00,0x01,0xF8,0x00,0x06,0x42,
++    0x58,0xC0,0x02,0x01,0x00,0xA0,0x07,0x01,0x80,0x01,0x06,0x42,0xF8,0xFF,0x07,0x00,
++    0x00,0x80,0x00,0x01,0x58,0x20,0x00,0x01,0x88,0x76,0x00,0x00,0x77,0x81,0xF8,0xFF,
++    0xF8,0x02,0x07,0x00,0xA8,0x85,0x80,0x07,0xC8,0x77,0x65,0x32,0xE8,0x03,0x47,0x01,
++    0x80,0x26,0x40,0x31,0x8F,0xD6,0xBF,0xFF,0xDF,0x3F,0x38,0xBF,0xBB,0xFF,0xD7,0x5F,
++    0x38,0xA7,0x07,0x00,0x00,0xC0,0x05,0x01,0xAE,0xC5,0x6F,0xDA,0x03,0x41,0x83,0x43,
++    0x01,0x09,0x80,0x43,0x0F,0x01,0x81,0x4B,0x15,0x19,0x80,0x53,0x13,0x41,0x89,0x53,
++    0x17,0x69,0x89,0x53,0x15,0x69,0x88,0x53,0x11,0x92,0x32,0x7A,0xBD,0x01,0x15,0xD4,
++    0x17,0xA1,0x1D,0x54,0x32,0x62,0xA1,0x01,0x8D,0x03,0x8B,0x03,0x07,0x41,0x88,0x03,
++    0x11,0x51,0x90,0x13,0x13,0xA1,0x90,0x13,0x90,0x0B,0x0F,0x81,0x9B,0x0B,0x99,0x03,
++    0x0F,0x01,0x98,0x4B,0x0D,0x71,0x90,0x4B,0x17,0x31,0x90,0x53,0x98,0x4B,0x0B,0x31,
++    0x98,0x4B,0x09,0x01,0x99,0x4B,0xA5,0x43,0x03,0x81,0xA1,0x43,0x03,0x51,0x80,0x03,
++    0x05,0xB1,0x87,0x03,0x07,0x51,0x80,0x03,0x01,0xB1,0x8F,0x03,0x05,0x29,0x94,0x03,
++    0x01,0x51,0x28,0x44,0x03,0xF9,0x87,0x49,0x34,0x32,0xB1,0x01,0x00,0x84,0x01,0xC9,
++    0x0B,0x00,0x02,0x84,0x04,0x79,0x10,0x00,0x05,0x83,0x43,0xC2,0x00,0x83,0x05,0x01,
++    0x99,0x83,0x31,0x02,0x0C,0x51,0x80,0x91,0x87,0x27,0xD0,0x87,0x05,0xB1,0xB7,0xC3,
++    0x07,0xA1,0xB0,0xC3,0x07,0x01,0xA8,0xC3,0x09,0x01,0x30,0x02,0x80,0x01,0xA2,0x0B,
++    0xA0,0x0B,0x0E,0xC1,0xA8,0x0B,0x08,0x51,0xAE,0x0B,0x0A,0x41,0x1F,0x0C,0x0E,0xF9,
++    0x89,0x21,0x00,0xCC,0x0E,0x99,0x18,0x4A,0xA8,0x0B,0x14,0xA1,0xA8,0x13,0xB6,0x0B,
++    0x0A,0xA1,0xB0,0x0B,0x0A,0x51,0x88,0x0B,0x14,0xF1,0x88,0x13,0x0E,0x21,0x8B,0x0B,
++    0x0A,0x59,0x0D,0x0C,0x08,0xE1,0x90,0x0B,0x08,0xC9,0x99,0x0B,0x0A,0x31,0x98,0x0B,
++    0x08,0xF9,0x8F,0x09,0x08,0x0C,0x0E,0x51,0xB8,0x4B,0x0B,0x01,0x32,0x4C,0xA3,0x0B,
++    0x0D,0x21,0xB0,0x8B,0x0B,0x31,0xB0,0x8B,0x09,0x19,0x0D,0x4C,0x0C,0xA1,0xB0,0x0B,
++    0x0E,0x51,0xB0,0x0B,0x0C,0x01,0xA0,0x0B,0x08,0x19,0xBC,0x0B,0x09,0x31,0x80,0x0B,
++    0x18,0x01,0x30,0x0A,0xCE,0x01,0x9B,0x5B,0xA2,0x5B,0x88,0x01,0xB2,0x53,0xB0,0x53,
++    0x14,0xE1,0xB1,0x53,0x16,0x41,0xB0,0x53,0x10,0x11,0xB8,0x53,0x12,0xB1,0xB8,0x53,
++    0x14,0x19,0xB8,0x53,0x48,0x52,0x04,0x0B,0x8C,0x1B,0x48,0x52,0xC6,0x01,0x34,0x0B,
++    0x88,0x91,0x38,0x0B,0x8A,0xE1,0x3E,0x0B,0x0C,0xC1,0x40,0x3A,0x84,0x27,0xD0,0x77,
++    0x40,0x2A,0x0C,0xC1,0xC0,0x81,0x81,0x27,0xD4,0x4F,0x4C,0x12,0x43,0x1A,0xCC,0x31,
++    0x00,0x0B,0xCE,0x71,0x00,0x0B,0x8C,0xA1,0x08,0x0B,0x88,0xC1,0x0A,0x0B,0xCA,0x21,
++    0x01,0x0B,0xCA,0xC1,0x05,0x0B,0x88,0xA1,0x0D,0x0B,0xCC,0xC1,0x10,0x0B,0xFA,0x48,
++    0x10,0x0B,0xF8,0x48,0x0F,0x0B,0xEE,0xC5,0xA8,0x85,0x09,0x01,0x63,0x92,0x43,0x92,
++    0xA2,0xE1,0xFE,0x1B,0x01,0x77,0x00,0x21,0x18,0x42,0xCA,0x28,0x00,0x29,0x12,0x79,
++    0x09,0x00,0xC2,0x40,0x90,0x13,0x10,0x01,0x94,0x13,0x92,0x13,0x10,0x14,0x1E,0x14,
++    0xE6,0x48,0x92,0x4D,0x17,0x5A,0xC4,0x76,0x07,0x01,0x10,0xF9,0x2D,0x09,0x09,0x68,
++    0x02,0x37,0x00,0x08,0xCA,0x48,0xC8,0x48,0xB2,0x53,0xB0,0x53,0xE6,0x00,0x92,0x05,
++    0x17,0x1A,0xC4,0xB6,0xE9,0x85,0xA1,0x85,0x56,0xFA,0x92,0x01,0x08,0x01,0x10,0x8C,
++    0xD4,0x01,0xB6,0x8B,0xB8,0x8B,0x30,0x9A,0x98,0x01,0xB5,0xCB,0x1C,0xCC,0xBC,0xCB,
++    0xB0,0xCB,0x22,0x09,0xB0,0xA3,0xA8,0x8B,0xDE,0x01,0xF1,0xDB,0xB0,0x9B,0x32,0x9A,
++    0x9A,0x01,0xA1,0xCB,0x9A,0x01,0xA1,0xE3,0xA4,0xCB,0xA0,0xA3,0x20,0x41,0x89,0xA3,
++    0x40,0x09,0x88,0x16,0xA1,0xCB,0xE4,0x85,0x39,0xB7,0xE5,0x85,0x3A,0x82,0x0B,0x08,
++    0x40,0x9A,0x42,0x13,0x18,0x01,0x01,0xD2,0x90,0x41,0x04,0x13,0x10,0xD0,0x1C,0x8A,
++    0x0A,0x0B,0x42,0x0B,0x40,0x0B,0x10,0x41,0x18,0x8A,0x04,0x0B,0x0C,0x01,0x00,0x0B,
++    0x38,0x82,0xAB,0x85,0x40,0x5A,0x42,0x0B,0x30,0x48,0xA8,0x2E,0x08,0x81,0x06,0x0B,
++    0x08,0x81,0x02,0x0B,0x08,0x81,0x00,0x0B,0x4E,0x32,0x8A,0x01,0x40,0x53,0x3C,0x90,
++    0x7C,0x90,0x00,0x53,0x41,0x53,0x1C,0x81,0x1C,0xD2,0x00,0x53,0x5E,0x12,0x12,0x09,
++    0x01,0xD3,0x12,0x91,0x02,0x13,0x46,0x0A,0x40,0x23,0x14,0x61,0x1C,0xA2,0x00,0x23,
++    0x40,0x23,0x1A,0xA2,0x02,0x23,0x4A,0x23,0x1A,0xA2,0x08,0x23,0x48,0x23,0x18,0xA2,
++    0x0E,0x23,0x40,0x23,0x1E,0xA2,0x00,0x23,0x42,0x43,0x12,0x01,0x1A,0x82,0x00,0x43,
++    0x00,0xD1,0x04,0xC3,0x02,0x01,0x0F,0xC3,0xE9,0x85,0x40,0xA2,0x40,0x13,0x08,0x09,
++    0x18,0x52,0x00,0x13,0x4C,0x13,0x18,0x52,0x0A,0x13,0x48,0x13,0x1A,0x52,0x0C,0x13,
++    0x40,0x13,0x1E,0x52,0x03,0x13,0x3E,0x82,0x40,0x6A,0x59,0x0B,0x10,0x21,0x18,0x8A,
++    0x18,0x0B,0x58,0x0B,0x10,0x01,0x1A,0x8A,0x18,0x0B,0x58,0x13,0x08,0x01,0x1C,0x52,
++    0x19,0x13,0x40,0x22,0x16,0x01,0x80,0x01,0x02,0x13,0x40,0x13,0x1A,0x52,0x00,0x13,
++    0x48,0xFA,0x40,0x43,0x10,0x01,0x19,0x82,0x03,0x43,0x38,0x82,0xA8,0x85,0x08,0x09,
++    0x00,0x31,0x80,0x07,0xD0,0x3F,0x0D,0x11,0x00,0x21,0x80,0x07,0xD0,0x1F,0x05,0x09,
++    0x85,0x07,0xD0,0xFF,0x00,0x31,0x80,0x07,0xD0,0xE7,0x05,0x21,0x85,0x07,0xD0,0xCF,
++    0x86,0x07,0xD0,0x77,0xE8,0x85,0xA8,0x85,0x40,0x82,0x48,0x5A,0xC0,0xA1,0x12,0x43,
++    0xBA,0xFF,0xF7,0xD7,0x07,0x09,0xB8,0xFF,0xF8,0x77,0x02,0xA1,0xBB,0xFF,0xFF,0x7F,
++    0xBB,0xFF,0xFF,0xFF,0xBE,0xFF,0xFF,0x07,0xBD,0xFF,0xFF,0x7F,0xBE,0xFF,0xFF,0xB7,
++    0x48,0x62,0x00,0x01,0x80,0x43,0xE8,0x85,0x00,0xC0,0x00,0x01,0xC8,0x21,0x01,0x00,
++    0xF8,0xFF,0x07,0x04,0xD8,0x02,0x06,0x00,0x40,0x60,0x07,0x01,0x58,0xC0,0x02,0x01,
++    0x10,0x00,0x00,0x42,0x00,0x00,0x00,0x42,0x80,0x01,0x06,0x42,0xF8,0x00,0x06,0x42,
++    0x18,0x00,0x02,0x42,0x00,0x80,0x00,0x01,0xA8,0x85,0x80,0x07,0xD0,0xEF,0xEA,0x85,
++    0xAF,0x85,0xB8,0xFF,0xF0,0xBF,0xE8,0x85,0xA8,0x7D,0x80,0x04,0x88,0x0C,0xC0,0x0C,
++    0x80,0x14,0xC0,0x04,0x83,0x1C,0x30,0x42,0x40,0x7E,0x80,0x25,0xE8,0x05,0x00,0x00,
++    0xAC,0xFD,0x87,0x1D,0x30,0x32,0x00,0x01,0x82,0x14,0x00,0x9F,0x44,0xFA,0x0F,0x01,
++    0x0C,0x0B,0x26,0x01,0xC2,0x14,0x00,0x28,0x7F,0xE2,0x4F,0xC3,0x1F,0x02,0x09,0xC3,
++    0xD0,0x6C,0x90,0x04,0x14,0x09,0x08,0x01,0x30,0x82,0xD9,0x64,0x86,0x1F,0xD8,0x37,
++    0xF8,0x82,0x33,0x0A,0xCF,0x99,0x49,0xC9,0x99,0x3E,0x40,0x91,0xE7,0x16,0x48,0xC3,
++    0x1F,0x02,0x0D,0xC3,0x40,0x20,0x63,0x01,0x88,0x36,0xD7,0x6C,0x90,0x04,0x10,0x09,
++    0x09,0x01,0x34,0x82,0xD8,0x64,0x80,0x1F,0xDB,0x8F,0xFD,0xA2,0xD0,0x6C,0x90,0x04,
++    0x14,0x09,0x08,0x01,0x30,0x82,0xD9,0x64,0x85,0x1F,0xD8,0x47,0xF8,0xBA,0xD3,0x6C,
++    0x90,0x04,0x10,0x09,0x09,0x01,0x34,0x82,0xD8,0x64,0x80,0x1F,0xDD,0xFF,0x14,0x3A,
++    0xE9,0x16,0x30,0x02,0x30,0xE2,0x31,0x3A,0xFD,0x82,0x13,0xC2,0xE3,0x0E,0x98,0xBA,
++    0x05,0x17,0x10,0x02,0xDB,0x06,0x98,0xA2,0x46,0xE2,0x4E,0x03,0xDE,0x8A,0x0B,0x00,
++    0xC0,0x00,0xCA,0x24,0x00,0x44,0xC0,0x24,0xE0,0x00,0x84,0x24,0xC2,0x14,0xE0,0x00,
++    0x90,0x05,0x86,0x14,0xC8,0x2C,0xC0,0x14,0x15,0x42,0x9C,0x3E,0x87,0x3D,0xE8,0x85,
++    0xAC,0xFD,0x87,0x7D,0x30,0xA2,0x30,0xEA,0xD8,0x0B,0x8B,0x6C,0xD0,0x0B,0x8F,0x64,
++    0x40,0x01,0x80,0x6E,0x48,0x72,0x06,0x99,0x07,0x43,0x12,0xF9,0x58,0x5A,0x96,0x81,
++    0x10,0xD3,0x06,0x43,0x00,0xC1,0x83,0x1F,0xF8,0x77,0xFF,0x84,0xB8,0xA1,0x01,0xD7,
++    0x40,0x3A,0x0E,0x19,0x04,0x0B,0x0A,0x19,0x06,0x0B,0x08,0x09,0xC4,0x84,0x00,0x48,
++    0xC0,0x38,0x12,0x01,0x30,0x5A,0x31,0x8A,0x00,0x09,0x80,0x17,0xD0,0xE7,0x31,0x01,
++    0x30,0x1A,0x11,0x09,0x08,0x01,0x44,0x1D,0xA8,0x04,0x80,0x1F,0xDB,0x7F,0xE2,0xB0,
++    0x91,0xB5,0x77,0x91,0x9D,0xA6,0x47,0xD2,0x40,0x0B,0x10,0x11,0x18,0x8A,0x00,0x0B,
++    0x00,0xE1,0xEC,0x02,0x33,0x00,0xA8,0xE6,0x40,0xB2,0x0D,0x01,0x81,0x0B,0x30,0x12,
++    0x30,0x4A,0x01,0x11,0x84,0x17,0xC8,0x27,0x30,0x1A,0xA9,0x04,0x08,0x01,0x00,0x11,
++    0xD0,0x84,0x80,0x17,0xD0,0x77,0x33,0x01,0xC2,0x64,0x00,0x00,0x80,0x74,0x00,0xBF,
++    0x31,0x5A,0x31,0x92,0x08,0x01,0x00,0x09,0x80,0x17,0xD0,0x6F,0xA8,0x0C,0xA0,0x04,
++    0x30,0xCA,0x41,0x1D,0xD8,0x84,0xD0,0x64,0xBA,0xFF,0xFF,0x17,0xC6,0x74,0xC8,0x38,
++    0x09,0x09,0x30,0x5A,0x30,0x92,0x31,0x42,0x87,0x17,0xC8,0xEF,0xE7,0xB0,0x93,0xB5,
++    0xC4,0x6C,0x10,0x32,0x99,0x26,0x37,0x1A,0xA8,0x04,0x08,0x01,0x00,0x19,0xD0,0x84,
++    0x82,0x17,0xD0,0x3F,0x31,0x12,0x31,0x4A,0x00,0x01,0x80,0x17,0xCD,0x8F,0xDA,0x03,
++    0x41,0x01,0x80,0xF6,0x40,0xBA,0x0C,0x09,0x81,0x0B,0x30,0x12,0x30,0x4A,0x01,0x11,
++    0x82,0x17,0xC8,0x37,0x30,0x5A,0x09,0x01,0x00,0x09,0xD0,0x6C,0x86,0x17,0xC8,0xDF,
++    0x30,0x1A,0xA9,0x04,0x00,0x11,0xD0,0x84,0xC8,0x6C,0x80,0x17,0xD0,0x57,0xA9,0x0C,
++    0xA5,0x04,0xD8,0x13,0x30,0xCA,0x41,0x1D,0xDF,0x84,0xB8,0xFF,0xFD,0x4F,0xD8,0x03,
++    0x06,0x00,0xCA,0x30,0x30,0x1A,0xA9,0x04,0x00,0x19,0xD0,0x84,0xC8,0x6C,0x80,0x17,
++    0xD0,0xC7,0x08,0x09,0x30,0x5A,0x31,0x42,0xD0,0x6C,0x80,0x17,0xC9,0xE7,0x35,0x12,
++    0x30,0x4A,0x01,0x01,0x80,0x17,0xC8,0xE7,0x40,0xF2,0x0B,0x01,0x85,0x0B,0xD8,0x03,
++    0x00,0x27,0x00,0x37,0x05,0x8C,0xE1,0xB0,0xE6,0x00,0x92,0x05,0xD4,0x64,0x10,0x82,
++    0x9B,0xC6,0x57,0xBA,0x40,0x83,0x08,0x11,0x18,0x42,0x04,0x83,0x87,0x9D,0xE8,0x85,
++    0xAC,0xFD,0x87,0x1D,0x30,0x7A,0x50,0x01,0x80,0x16,0x00,0x01,0x80,0x0C,0x00,0x0F,
++    0x00,0x09,0x80,0x0C,0x2A,0x01,0x00,0x47,0xCD,0x64,0x00,0x40,0xC1,0x30,0x32,0x52,
++    0x08,0x19,0xD8,0x6C,0xC0,0x0C,0x80,0x17,0xC9,0x77,0x04,0x41,0x81,0x1F,0xF8,0x5F,
++    0x20,0x09,0xC0,0x34,0x80,0x01,0x84,0x14,0x60,0x81,0x99,0x36,0x0B,0xF9,0x47,0x1A,
++    0x88,0x11,0x18,0x0B,0x42,0x08,0x1B,0x0B,0x03,0x0F,0x40,0x02,0x1F,0x23,0x02,0xF9,
++    0x4F,0xF2,0x82,0x89,0x88,0x01,0x12,0x43,0x00,0x11,0x80,0x1F,0xF8,0xA7,0xC0,0x14,
++    0xE0,0x03,0x44,0x01,0x80,0x3E,0x00,0x51,0x80,0x1F,0xF8,0x6F,0x40,0x83,0x41,0x03,
++    0x30,0x00,0xA8,0x86,0x07,0x5F,0x00,0xF9,0x4C,0xA2,0x82,0x89,0x88,0x01,0x12,0x43,
++    0x00,0x09,0x80,0x1F,0xF9,0x07,0x40,0x83,0x40,0x03,0x30,0x00,0xA3,0x1E,0xE0,0x20,
++    0x93,0x25,0x67,0xF9,0xC9,0x86,0x06,0xE4,0xE1,0xF8,0x35,0x52,0x08,0x09,0xD8,0x6C,
++    0xC0,0x0C,0x80,0x17,0xCB,0x87,0xE2,0x68,0x90,0x6D,0xC7,0x1C,0x15,0x2A,0x9C,0x9E,
++    0x37,0x27,0xAF,0x85,0x80,0x4D,0x34,0x6A,0x34,0xA2,0x00,0x91,0xEF,0x02,0x0A,0xF9,
++    0x88,0x09,0x40,0x01,0x80,0x0E,0x30,0x7A,0x00,0x0F,0x38,0x19,0x17,0xF8,0xD1,0x43,
++    0x85,0x44,0xD0,0x53,0x90,0x3C,0x98,0x24,0xC2,0x44,0x00,0x00,0xC0,0x00,0x86,0x2C,
++    0xD2,0x3C,0x00,0x90,0xC0,0x00,0x84,0x1C,0x45,0xC2,0x11,0x81,0x00,0x13,0x1A,0x0B,
++    0x30,0x01,0x00,0x67,0x4D,0x03,0x01,0x88,0xC0,0x00,0x42,0x03,0x01,0x3B,0x30,0x1A,
++    0x30,0x92,0x09,0x09,0x00,0x01,0x80,0x17,0xCB,0xF7,0xE0,0xB0,0x90,0xB5,0xC7,0x44,
++    0x17,0x32,0x9C,0x7E,0x30,0x01,0x00,0x67,0x4D,0x03,0x03,0x88,0xC0,0x00,0x42,0x03,
++    0x00,0x3B,0x08,0x09,0x31,0x1A,0x31,0x92,0x30,0x42,0x80,0x17,0xCB,0x67,0xE0,0xB0,
++    0x90,0xB5,0xC7,0x3C,0x17,0x32,0x9C,0x7E,0xD8,0x43,0x45,0x01,0x81,0x16,0x41,0x1A,
++    0x44,0x0B,0x96,0x4D,0x89,0x14,0x48,0x4C,0x01,0x0B,0x4E,0x12,0x00,0x09,0x80,0x43,
++    0xD8,0x43,0x85,0x34,0x30,0x01,0x00,0x67,0x55,0x03,0x01,0x88,0xC0,0x00,0x42,0x03,
++    0x01,0x3B,0x30,0x1A,0x30,0x92,0x09,0x09,0x00,0x01,0x80,0x17,0xC3,0x67,0xE7,0xB0,
++    0x90,0xB5,0xC7,0x34,0x17,0x32,0x9C,0x7E,0x48,0xB2,0x00,0x01,0x80,0x43,0x40,0x9A,
++    0xCE,0x14,0x00,0x0B,0x48,0x0B,0x89,0x04,0x30,0x5A,0x11,0x09,0xA0,0x0C,0xC8,0x24,
++    0xC7,0x44,0xB8,0xFF,0xFB,0xAF,0x49,0x0B,0x89,0x04,0x30,0x5A,0x10,0x01,0xA0,0x0C,
++    0xC8,0x2C,0xC0,0x3C,0xB9,0xFF,0xFF,0x67,0xD8,0x43,0x45,0x01,0x80,0xDE,0x70,0x3A,
++    0x44,0x83,0x97,0x3D,0x4F,0x44,0x01,0x83,0x40,0x32,0x08,0x09,0x85,0x0B,0xD8,0x43,
++    0x51,0x0B,0x31,0x5A,0x10,0x09,0xA0,0x0C,0x88,0x04,0x00,0x2F,0x00,0x01,0x00,0x42,
++    0x18,0x00,0x04,0x42,0x00,0xB0,0x00,0x01,0xCF,0x1C,0xB8,0xFF,0xF8,0x8F,0x40,0xDA,
++    0x08,0x01,0x80,0x0B,0x00,0xBB,0x4F,0xD2,0x00,0x01,0x10,0x43,0x4A,0xC2,0xC8,0x01,
++    0x18,0x43,0x80,0x4D,0xEF,0x85,0xAF,0xC5,0x30,0x1A,0x30,0x42,0x34,0xBA,0xD0,0x23,
++    0xD0,0x2B,0x4E,0xA2,0xC0,0xC8,0x8A,0x04,0x30,0xD2,0x31,0xCA,0x80,0x17,0xE8,0xE7,
++    0x30,0x01,0x00,0x3F,0x09,0x09,0x30,0xDA,0x30,0x92,0x31,0x42,0x84,0x17,0xC0,0x9F,
++    0xE7,0xB0,0x93,0xB5,0x17,0x32,0x9D,0xAE,0xC8,0x04,0x10,0x01,0x18,0x01,0x00,0x4F,
++    0x00,0x01,0x00,0x1F,0x82,0x5B,0xE0,0x48,0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0xCE,
++    0xE6,0x90,0x92,0x95,0x17,0x12,0x9D,0x9E,0xE8,0xC5,0x07,0x00,0x00,0xB0,0x00,0x01,
++    0x00,0x01,0x02,0x42,0x30,0x20,0x06,0x00,0x49,0x32,0x41,0x2A,0x05,0x43,0x9E,0xFF,
++    0x7F,0x04,0x3A,0xF7,0x94,0x15,0x3A,0x00,0x77,0x18,0x06,0xF9,0x04,0xC2,0x3C,0x48,
++    0x74,0x48,0x00,0xCA,0x50,0x01,0xD0,0x5E,0x38,0x90,0x78,0x90,0xD4,0x41,0x40,0x98,
++    0x54,0xE2,0x00,0xD8,0xC6,0xD0,0x4C,0x9B,0x18,0x1A,0x1C,0x5A,0x0B,0x9B,0x3E,0x82,
++    0x40,0x98,0x54,0xCA,0x04,0xD8,0xC4,0xD0,0x44,0x9B,0x18,0x1A,0x18,0x5A,0x00,0x9B,
++    0x3A,0x82,0x93,0x05,0x36,0x10,0x76,0x90,0x0C,0x09,0x00,0x8A,0x48,0x00,0x52,0x9A,
++    0x04,0x00,0xC4,0x00,0x03,0x0B,0x38,0x82,0x96,0x05,0x32,0x10,0x70,0x90,0x0E,0x09,
++    0x00,0x8A,0x54,0x72,0x4C,0x00,0x02,0x00,0x94,0x01,0xC4,0x00,0x03,0x0B,0x38,0x82,
++    0xB3,0x15,0x3B,0x82,0xFB,0x85,0x39,0x82,0x40,0x32,0x48,0x0B,0x10,0x21,0x18,0x8A,
++    0x0B,0x0B,0x38,0x82,0x48,0x1A,0x48,0x43,0x14,0x21,0x18,0x82,0x0B,0x43,0x38,0x82,
++    0x07,0x20,0x28,0xD0,0x68,0x07,0x00,0x07,0x20,0x07,0x00,0x07,0x08,0x07,0x00,0x07,
++    0xAC,0xFD,0x87,0x4D,0xD0,0x94,0x30,0x22,0xF0,0x43,0x84,0x0C,0xF8,0x6B,0xC2,0x64,
++    0x08,0x01,0x80,0x0B,0x00,0x01,0x00,0x8F,0x0A,0x21,0x19,0x0A,0x18,0x29,0xCA,0x48,
++    0x0E,0xD8,0xC2,0x48,0xD0,0x4B,0x48,0x79,0x80,0x36,0x80,0x83,0xE0,0x90,0xCA,0x64,
++    0xD8,0x64,0xC0,0x4B,0xE0,0x48,0x82,0xCB,0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0x5E,
++    0xC0,0x64,0xC0,0x03,0x80,0x44,0x40,0x01,0x88,0x0E,0x80,0x6D,0xE8,0x85,0xC7,0x44,
++    0x40,0x09,0x88,0x1E,0xC0,0x0C,0x40,0x09,0x8F,0x06,0x38,0xB7,0x00,0x01,0x80,0x34,
++    0x80,0x2C,0xC8,0x44,0xC4,0x0C,0x10,0x0A,0x88,0x8E,0x02,0x01,0x30,0x01,0x08,0x01,
++    0x88,0x1C,0x88,0x14,0x1A,0x19,0x0A,0xD8,0x00,0x4F,0x10,0x31,0x18,0x52,0xCA,0x90,
++    0xC4,0x90,0x4E,0xBC,0xC6,0xC0,0x49,0x94,0xCA,0xB0,0xE4,0x48,0x90,0x4D,0xD6,0x0C,
++    0x17,0x8A,0x9C,0x96,0xC8,0x0C,0x80,0x1F,0xF0,0xFF,0x83,0x24,0x30,0x82,0xC9,0x0C,
++    0x83,0x1F,0xF0,0xD7,0x30,0x32,0x08,0x01,0x00,0x01,0x00,0xFF,0x1A,0x29,0x0A,0xD8,
++    0x02,0x0F,0xE0,0x48,0x91,0x4D,0x16,0x21,0x18,0x52,0xCA,0x90,0xC0,0x90,0xD6,0x93,
++    0x57,0x79,0x80,0xB6,0x12,0x21,0x19,0x52,0x18,0x19,0xC9,0x90,0x0E,0xD8,0xC4,0x90,
++    0x1E,0x01,0xF0,0x9A,0xFE,0x1C,0xC8,0xD8,0x98,0x1C,0x18,0x11,0xF0,0x9A,0xD6,0x14,
++    0xC0,0xD0,0x94,0x14,0xE6,0x48,0x92,0x4D,0xE6,0x00,0x92,0x05,0xD4,0x44,0x10,0x12,
++    0xC0,0xE6,0xCE,0x44,0xC0,0x1C,0x80,0x1F,0xF0,0x7F,0x32,0x3A,0xC8,0x44,0xC0,0x14,
++    0x82,0x1F,0xF0,0x57,0xCE,0x24,0xD8,0x48,0x89,0x34,0xD0,0x80,0x80,0x2C,0x08,0x01,
++    0x10,0x01,0x00,0x77,0x00,0x01,0x30,0x5A,0x18,0x5A,0xF3,0x5C,0x04,0xD8,0xCA,0xD8,
++    0x02,0x1F,0x00,0x30,0x9A,0xD2,0xE4,0x00,0x95,0x05,0x16,0x42,0x9A,0xCE,0xE7,0x48,
++    0x95,0x4D,0x16,0x4A,0x98,0x76,0x0F,0x01,0x11,0x01,0x00,0xF7,0x1A,0x29,0x0A,0xD8,
++    0x02,0x0F,0xE0,0x48,0x91,0x4D,0x06,0x21,0x18,0x42,0xCA,0x00,0x86,0x3C,0xC0,0x00,
++    0xD0,0x03,0x40,0x79,0x80,0xAE,0x07,0x01,0x01,0x47,0x19,0x19,0xF4,0x3C,0x08,0xD8,
++    0xC0,0x98,0x37,0x01,0x34,0xE2,0xFC,0xF2,0xDA,0x34,0x38,0x19,0xC0,0x98,0x37,0x31,
++    0x19,0x32,0xCA,0xB0,0x0F,0xF8,0xCB,0xB0,0x35,0xB2,0x4D,0xB4,0xD8,0xD8,0xAC,0x06,
++    0x14,0xDA,0x92,0xDD,0x30,0x32,0x3B,0x11,0xF8,0xBA,0xF7,0x2C,0xCB,0xF0,0x35,0xBA,
++    0x4F,0xFC,0xDF,0xB0,0xAB,0x06,0x10,0xB2,0xC8,0xD8,0x34,0xB2,0x18,0x72,0xFB,0x5C,
++    0x07,0xB0,0xCB,0xB0,0x07,0x38,0x9A,0x9A,0xE6,0x00,0x92,0x05,0xDC,0x0C,0x10,0xC2,
++    0x9A,0x9E,0xE6,0x48,0x92,0x4D,0xE6,0x90,0x90,0x95,0xC6,0x64,0xC4,0x03,0x10,0x82,
++    0xC0,0xE6,0xC5,0x64,0xC8,0x0C,0xC0,0x03,0x10,0x42,0xCC,0x06,0x38,0xEF,0xC1,0x0C,
++    0x3F,0xDF,0xA9,0x85,0x80,0x4D,0x34,0x22,0x04,0x71,0xD4,0x1A,0x01,0xC1,0xF0,0x02,
++    0x28,0x71,0x80,0x44,0xF8,0x2A,0xAB,0x3C,0xD8,0x00,0x92,0x05,0x2B,0xD1,0xF8,0x2A,
++    0x30,0x81,0xA8,0x34,0xF8,0x32,0xB5,0x2C,0xD9,0x68,0x95,0x6D,0xC0,0x33,0x77,0x09,
++    0x8D,0x16,0x10,0x04,0x10,0x2C,0x07,0x7F,0x55,0x3C,0x05,0xF0,0x31,0xE2,0xC5,0xB0,
++    0x54,0x04,0x07,0x38,0xCB,0xE8,0x33,0x3A,0xD9,0xB0,0x97,0xB5,0xD0,0x40,0x91,0x2D,
++    0x85,0x80,0x85,0x68,0x17,0x04,0x15,0x2C,0xF1,0x3C,0xC0,0x80,0x04,0x30,0xCA,0x00,
++    0xF4,0x44,0xC8,0x00,0x80,0x00,0x94,0x05,0xF3,0x2C,0xC8,0xA8,0x05,0x70,0xCB,0x68,
++    0xF5,0x34,0xC8,0x68,0x81,0x68,0x95,0x75,0x90,0x01,0x46,0x01,0xD0,0x0E,0x00,0x01,
++    0x00,0x27,0x40,0xAC,0x10,0x2A,0xD4,0x0E,0x00,0x01,0xF0,0x82,0x70,0x01,0xD0,0x0E,
++    0x30,0x01,0x00,0x27,0x45,0xAC,0x12,0xAA,0xD0,0x0E,0x30,0x11,0xF8,0xB2,0x4C,0x41,
++    0x80,0x0E,0x48,0x49,0x88,0xBE,0xD0,0x3C,0xD0,0x90,0xA8,0x06,0x14,0x92,0x92,0xAD,
++    0xD4,0x2C,0xD8,0x90,0xAA,0x06,0x10,0x92,0xCC,0x90,0x92,0xAD,0x10,0xEA,0xCC,0x06,
++    0x30,0xEA,0x48,0x49,0x8B,0x16,0x20,0x48,0x60,0x68,0x00,0x37,0x4D,0xC8,0x10,0x4A,
++    0xC8,0x1E,0x30,0x6A,0x00,0x0F,0x30,0xEA,0x00,0x6A,0xD6,0x3C,0xD8,0xC8,0x8A,0x24,
++    0x1C,0x8A,0x02,0x50,0xC4,0x48,0x34,0x62,0xC8,0x24,0x10,0x51,0x05,0x78,0xF2,0x12,
++    0xCA,0x48,0x1E,0x52,0x20,0x12,0x8B,0x1C,0x43,0xC8,0x1A,0x42,0xC6,0x00,0x02,0x00,
++    0xC0,0x00,0x8C,0x14,0x00,0xC8,0x8E,0x0C,0x82,0x1F,0xE8,0xA7,0x30,0x3A,0xC0,0x2C,
++    0xCA,0x24,0x18,0x0A,0x00,0x40,0xC4,0x40,0x15,0x61,0xF0,0x12,0xCA,0x1C,0x18,0x52,
++    0xC0,0x80,0xC8,0x14,0x1B,0x72,0xC3,0x88,0x00,0x48,0xC6,0x40,0xC8,0x0C,0x80,0x1F,
++    0xE8,0x0F,0xCA,0x3C,0x08,0x0C,0xCB,0x2C,0x08,0x0C,0xCD,0x44,0xD0,0xC8,0xAB,0x06,
++    0x10,0x4A,0x92,0x55,0xCA,0x34,0xD0,0x08,0xAA,0x06,0x10,0x4A,0x90,0x4D,0x50,0x19,
++    0xD8,0x46,0xD0,0x44,0x10,0xD2,0xCD,0x0E,0xE0,0xF8,0x03,0x1F,0xD5,0x44,0x10,0xD2,
++    0x93,0x06,0xF0,0xF8,0x48,0x19,0xD8,0x46,0xCC,0x34,0x10,0x0A,0xCA,0x0E,0xE0,0x00,
++    0x00,0x1F,0xC8,0x34,0x10,0x0A,0x94,0x06,0xF7,0x00,0x0A,0x3C,0x10,0x04,0x81,0x4D,
++    0xEF,0x85,0xAF,0xF5,0x30,0xB2,0xD0,0x44,0x60,0xCA,0xCF,0xE0,0x2F,0x31,0x78,0xC2,
++    0x1F,0xAA,0xC3,0x68,0xFF,0xE1,0xC9,0x68,0x07,0xB0,0xC3,0x98,0x72,0xA2,0xF7,0x81,
++    0xCA,0xF0,0xFC,0x9B,0x36,0xBA,0xB8,0x01,0x32,0xE2,0xFD,0x01,0xBA,0x0C,0xF8,0x01,
++    0xB8,0x04,0x40,0x09,0x88,0x36,0x01,0x01,0x01,0xFF,0xC0,0x0B,0x48,0x79,0x88,0xCE,
++    0x47,0x4C,0x09,0x0C,0x41,0x7C,0x13,0x3C,0xC1,0x93,0x89,0x13,0xC3,0x93,0x8B,0x13,
++    0x1F,0x0C,0x1D,0x3C,0x23,0x0C,0x21,0x3C,0x0D,0x0C,0x0B,0x3C,0x41,0x4C,0x19,0x0C,
++    0x43,0x4C,0x1B,0x0C,0x80,0x03,0x09,0x09,0x85,0x0B,0x8F,0x0B,0x30,0x0A,0xDB,0x4B,
++    0x90,0x0B,0x01,0x27,0xA2,0x21,0xE1,0x00,0x94,0x05,0x16,0xC2,0x9C,0xEE,0x16,0xC2,
++    0x92,0x9E,0x03,0x87,0x02,0x21,0x19,0x0A,0xC8,0x60,0x08,0x41,0x41,0x44,0x19,0x04,
++    0x01,0x11,0xF0,0x42,0x1D,0x04,0xCB,0x1B,0x58,0x09,0x88,0xA6,0x18,0xC1,0x38,0xE1,
++    0xF7,0x1A,0xFF,0x3A,0xD8,0xD8,0xAE,0x06,0x14,0xDA,0x92,0xFD,0x1F,0xF1,0xF0,0x1A,
++    0xD0,0x00,0xAE,0x06,0x14,0x02,0x92,0x05,0xD9,0x0C,0xC0,0xC0,0xDC,0xDB,0x10,0xC2,
++    0xC8,0x0E,0x00,0x01,0x88,0x03,0x05,0xC1,0x19,0x01,0xF1,0x02,0xF6,0x1A,0xD7,0x00,
++    0xAA,0x06,0x10,0x02,0x90,0x3D,0x04,0xD1,0x19,0x11,0xF1,0x02,0xF6,0x1A,0xD7,0x00,
++    0xAA,0x06,0x10,0x02,0xCC,0x00,0x96,0x05,0xD4,0x1B,0x11,0x1A,0xC8,0x2E,0xD8,0x04,
++    0xC6,0x03,0xDF,0xDB,0xE4,0xD8,0x12,0xC2,0xC0,0x86,0xD8,0x04,0xC6,0x03,0xDF,0xDB,
++    0xE4,0xD8,0x12,0xC2,0xCB,0x1E,0x30,0x02,0xD8,0x03,0x48,0x00,0x91,0x03,0x59,0x04,
++    0x23,0x04,0x59,0x04,0x21,0x04,0x33,0x02,0xBD,0xFF,0xF7,0x9F,0xC3,0x03,0x47,0xF9,
++    0x92,0x0E,0xE0,0x00,0x85,0x03,0x47,0x44,0x10,0x04,0x03,0x19,0x80,0x03,0xC3,0x0C,
++    0xDC,0x03,0x82,0x01,0x89,0x03,0xCF,0x03,0xC2,0x8B,0xD1,0x00,0xE0,0x00,0x42,0x11,
++    0xC3,0x2E,0xC8,0x03,0xC2,0x8B,0xD3,0x00,0xE0,0x00,0x42,0x11,0xCF,0x4E,0xC0,0x03,
++    0x40,0x11,0x98,0x36,0xCC,0x04,0xD8,0x4B,0x10,0x42,0xC4,0x16,0x07,0x01,0x80,0x03,
++    0x89,0x03,0xC7,0x83,0x8B,0x03,0xC1,0x83,0x8F,0x03,0xEB,0xF5,0xAF,0x85,0x47,0xF9,
++    0x88,0x0E,0x00,0x01,0xE9,0x85,0x27,0x21,0x1C,0x02,0x63,0xEA,0xC0,0x00,0xCC,0x00,
++    0x23,0x31,0x18,0x0A,0xC4,0x48,0x54,0xD2,0xD4,0xE1,0xC1,0x50,0x0A,0xA1,0xF0,0x0A,
++    0x48,0x01,0xD0,0x06,0x10,0x4A,0x22,0xB1,0xF8,0x22,0x60,0x01,0xD3,0x06,0x10,0x22,
++    0xCC,0x48,0x60,0xA2,0x10,0x0A,0x9D,0x06,0x08,0x01,0x28,0x71,0x42,0xA4,0xF8,0x2A,
++    0xD8,0x20,0xAB,0x06,0x10,0x22,0x2B,0x81,0x42,0x94,0xFA,0x2A,0xD8,0x90,0xAA,0x06,
++    0x15,0x92,0xC2,0x28,0x34,0xE2,0xA0,0x01,0x4C,0x14,0x33,0xA2,0x10,0x52,0xC5,0xF6,
++    0xC8,0x13,0x54,0x09,0x8B,0x26,0xD8,0x3B,0xCB,0x33,0xF6,0xF8,0x10,0xF2,0xDD,0xA6,
++    0x50,0x09,0x88,0x3E,0xD4,0x23,0x11,0x62,0x9E,0x26,0xC0,0x03,0x40,0xF1,0xC0,0x0E,
++    0x40,0x29,0x90,0x56,0x50,0x09,0x88,0x16,0x51,0xC4,0x46,0x81,0x98,0x2E,0x50,0x09,
++    0x8B,0x2E,0x30,0x02,0x05,0x00,0x12,0x42,0xC0,0x0E,0x00,0x01,0xE8,0x85,0x07,0x09,
++    0xEF,0x85,0xAF,0xFD,0x84,0x65,0x34,0xB2,0x08,0x01,0x28,0x01,0x00,0x01,0x80,0x1C,
++    0xC2,0xAC,0xF8,0x23,0x04,0x01,0x30,0x22,0x80,0x3C,0x00,0x27,0xD7,0x6C,0x00,0xF9,
++    0xA2,0x82,0xE2,0x48,0x95,0x4D,0x16,0x0A,0x98,0xC6,0xD7,0x7C,0x28,0x92,0xC3,0x26,
++    0xC0,0x7C,0x80,0x2C,0x30,0x82,0x83,0x24,0x03,0x1F,0x30,0x82,0x80,0x2C,0xC0,0x7C,
++    0x80,0x24,0x00,0x01,0x82,0x34,0x00,0xD7,0x1A,0x01,0x00,0xB7,0x36,0x02,0x03,0xC2,
++    0x3A,0x00,0x8E,0x86,0x40,0x1A,0x83,0x44,0x00,0x01,0xD0,0xAC,0xF4,0x64,0xF0,0x93,
++    0x90,0x5C,0x30,0xD2,0x1A,0x12,0x03,0xB8,0xC8,0xD0,0x95,0x54,0x00,0x6F,0xF0,0x3C,
++    0x07,0x32,0x3E,0x90,0x88,0x3E,0xF0,0x54,0x07,0x38,0xDA,0xB2,0xFD,0x44,0x10,0xF2,
++    0x90,0x0E,0xB0,0x44,0x32,0x0A,0xE0,0x00,0x90,0x05,0xD6,0x5C,0x17,0x12,0xC4,0x76,
++    0x70,0xA2,0x02,0x01,0x00,0x78,0xBA,0x4C,0x03,0x87,0x30,0x3A,0x07,0x3A,0x3E,0xF8,
++    0x88,0x56,0x30,0x3A,0x18,0x3A,0xD3,0x64,0x05,0xF8,0xC3,0xF8,0xD5,0x4C,0xD0,0xFA,
++    0x10,0xBA,0xC5,0x0E,0x30,0xF2,0x31,0x2A,0xE6,0x00,0x92,0x05,0x2F,0x82,0x9B,0x66,
++    0x10,0xEA,0x8C,0xA6,0xC4,0x1C,0xC8,0x00,0x80,0x1C,0xC0,0x34,0xE6,0x00,0x92,0x05,
++    0x80,0x34,0xC0,0x6C,0xA0,0x2A,0x32,0x09,0x30,0x82,0xD1,0x3C,0x00,0x42,0x1C,0x82,
++    0x90,0x05,0x84,0x3C,0x03,0x72,0x35,0x02,0x1D,0x32,0x90,0x85,0x30,0x22,0xD4,0x2C,
++    0xC4,0x34,0x10,0x82,0x82,0x1E,0xE0,0xD8,0x93,0xDD,0x2E,0x9A,0x98,0x36,0xD5,0x2C,
++    0xC4,0x34,0x10,0x82,0x98,0x06,0xC5,0x1C,0x80,0x44,0x10,0x01,0x00,0x01,0x08,0x01,
++    0x30,0x5A,0x83,0xCB,0x18,0x01,0x08,0x01,0x33,0x62,0x34,0x4A,0xE0,0x4A,0x00,0x0F,
++    0xE6,0x48,0x92,0x4D,0x36,0xEA,0x00,0x6A,0x3F,0x68,0x8F,0xCE,0xED,0x24,0x10,0x4A,
++    0x98,0xD6,0x40,0x01,0x8F,0x8E,0x08,0xF9,0x00,0x5F,0xD0,0x6C,0xE3,0x9A,0x28,0x9A,
++    0x90,0x1E,0xD0,0xAC,0xF4,0x93,0x14,0x12,0xC0,0x0E,0xD0,0x6C,0xA2,0x8A,0xE0,0x00,
++    0x95,0x05,0x16,0x02,0x98,0x8E,0x87,0x85,0xEA,0x85,0xF7,0x00,0x93,0x05,0x36,0x4A,
++    0xE0,0x4A,0x28,0x09,0x31,0x62,0x05,0x47,0x33,0x6A,0x18,0x2A,0xFB,0x64,0x00,0x70,
++    0xCA,0xB0,0x07,0x38,0xDD,0xAA,0xC7,0x50,0x2C,0x09,0x00,0x6A,0x1D,0xEA,0x90,0x5D,
++    0x31,0x72,0xA3,0x8A,0xED,0x44,0x10,0x52,0x98,0x16,0x28,0x11,0x30,0x62,0x05,0xA7,
++    0xFA,0x7C,0xE0,0x28,0x10,0xEA,0x9D,0x6E,0x90,0x44,0x08,0x01,0x00,0x27,0xF8,0x6C,
++    0xE3,0xAA,0xA3,0xEA,0xE6,0x48,0x92,0x4D,0x17,0x0A,0x9D,0xC6,0xE0,0x8A,0x29,0x09,
++    0x30,0x62,0x05,0x17,0x90,0x45,0x2F,0x01,0xA3,0xAA,0x31,0x2A,0x6D,0x01,0x80,0x56,
++    0x33,0x6A,0x18,0x2A,0xFB,0x64,0x00,0x70,0xCA,0xB0,0x07,0x38,0xDA,0xAA,0xDF,0x90,
++    0x2C,0x09,0x00,0x6A,0x1B,0x5A,0x35,0x6A,0xE2,0x4A,0xE1,0x48,0xA4,0x4A,0x39,0xD7,
++    0x40,0x40,0x05,0x00,0xF8,0xFF,0x07,0x00,0xAC,0x85,0x87,0x2D,0x33,0x72,0xF8,0x8B,
++    0x8C,0x14,0x50,0xCA,0xC0,0x20,0xA4,0x24,0xC9,0x14,0x18,0x21,0x31,0xBA,0x31,0xAA,
++    0x1A,0xCA,0xBA,0x01,0xA8,0x01,0xC6,0x40,0xC0,0x00,0x84,0x1C,0x01,0x67,0xC2,0x03,
++    0x42,0x79,0x80,0x46,0xC8,0x03,0x37,0x08,0xA0,0xA6,0x41,0x21,0x88,0x16,0x01,0x71,
++    0xF0,0x02,0x81,0x0C,0x01,0x81,0xF0,0x02,0x81,0x04,0x30,0x92,0x09,0x49,0x30,0x02,
++    0xB8,0xFF,0xEF,0xFF,0x0B,0x71,0xF0,0x0A,0xC0,0x0C,0xD0,0x40,0xAA,0x06,0x10,0x02,
++    0x90,0x0D,0x00,0x81,0xF0,0x02,0xD1,0x04,0xD0,0x00,0xAC,0x06,0x12,0x02,0xC2,0x00,
++    0x91,0x05,0xD8,0x4B,0x44,0x48,0x14,0x0A,0xE8,0x5E,0xC0,0x0C,0x08,0x04,0xC7,0x04,
++    0x10,0x04,0x01,0x37,0x40,0x21,0x90,0x26,0xF8,0x83,0x41,0x11,0x91,0x0E,0x00,0x01,
++    0x87,0x03,0x05,0xF9,0x8B,0x03,0x89,0x03,0xC7,0x03,0xDF,0xCB,0x10,0x42,0xC4,0x0E,
++    0x07,0x01,0x88,0x03,0xCA,0x03,0x37,0x00,0x77,0x00,0x8A,0x03,0x40,0x01,0x80,0x0E,
++    0xF7,0x00,0x8A,0x03,0xC8,0x03,0x47,0x01,0x8B,0x2E,0xC0,0x03,0x44,0x00,0x04,0x00,
++    0x80,0x03,0x03,0x01,0x81,0x03,0xA5,0x21,0xC5,0x1C,0x10,0x02,0xC0,0x7E,0x0D,0x01,
++    0x11,0x01,0xB8,0x93,0xC0,0x24,0x00,0x87,0xC0,0x1B,0xE0,0x14,0x10,0x1A,0x95,0x56,
++    0xC7,0x1B,0xDE,0xE3,0x32,0xD8,0x72,0xD8,0x10,0x1A,0xCD,0x26,0xC1,0x1B,0x5C,0x01,
++    0x80,0x0E,0x08,0x09,0x04,0x27,0x80,0x13,0x80,0x21,0xD9,0x1C,0x17,0x1A,0xC4,0x5E,
++    0x49,0x01,0x80,0x5E,0xC1,0x24,0x00,0x37,0x80,0x13,0xC4,0x0B,0xDC,0x14,0x10,0xCA,
++    0x96,0x06,0xC1,0x0B,0xDA,0xDB,0x37,0x48,0x74,0x48,0x12,0xCA,0xC8,0xD6,0x08,0x09,
++    0x81,0x0B,0xFC,0x8B,0xE1,0x48,0xBA,0x8B,0x0A,0x71,0xF0,0x0A,0x48,0x01,0xD0,0x0E,
++    0x08,0x14,0x06,0x27,0x44,0x5C,0x11,0xCA,0xE9,0x0E,0x40,0x4C,0x08,0x0C,0x0E,0x81,
++    0xF0,0x0A,0x4A,0x01,0xD0,0x0E,0x10,0x14,0x03,0x27,0x40,0x5C,0x10,0xCA,0xEC,0x0E,
++    0x40,0x4C,0x13,0x0C,0x80,0x21,0xC9,0x1C,0x16,0x0A,0xC4,0xAE,0x87,0x2D,0xE8,0x85,
++    0xAC,0x85,0x87,0x3D,0x30,0x2A,0x30,0x62,0x41,0x1A,0xC2,0x40,0x08,0xB9,0xED,0x4A,
++    0x4B,0x29,0x80,0xE6,0x0C,0x09,0x06,0x48,0xC2,0x70,0x4B,0x02,0xC0,0x48,0x8B,0x1C,
++    0x0E,0x19,0x03,0x48,0xC0,0x48,0x8B,0x14,0x0F,0x01,0x10,0xF9,0x18,0x79,0x00,0x3F,
++    0xA6,0x92,0xCB,0x3B,0x78,0x01,0x88,0x06,0x82,0x1B,0xE0,0x48,0x91,0x4D,0x86,0x21,
++    0xFC,0x3B,0x13,0x7A,0xC0,0xA6,0x07,0x01,0x85,0x34,0xF0,0x03,0x42,0x01,0x80,0xCE,
++    0xB1,0x04,0x30,0x0A,0x30,0x42,0x59,0x2D,0xD7,0x14,0xB8,0xFF,0xD8,0x0F,0x84,0x34,
++    0xC0,0x34,0x40,0x01,0x88,0x76,0x30,0x01,0x01,0x47,0x30,0x5A,0x37,0x92,0x09,0xF9,
++    0x00,0x09,0xA0,0x04,0xB8,0xFF,0xEF,0xEF,0xE7,0xB0,0x93,0xB5,0xF5,0x03,0x15,0x82,
++    0xC1,0x9E,0x07,0xFF,0xC0,0x34,0x40,0x09,0x89,0x96,0xC0,0xB3,0x31,0x1A,0x31,0x52,
++    0x09,0x01,0x30,0x82,0xBE,0xFF,0xEF,0x17,0x40,0x01,0x80,0x0E,0x00,0x01,0x00,0x07,
++    0x01,0x09,0x30,0x5A,0x11,0x01,0x30,0x8A,0xA7,0x04,0xB8,0xFF,0xE9,0x17,0x00,0x4F,
++    0xA5,0x04,0xF0,0x3B,0x30,0x5A,0xEB,0xD3,0x30,0xDA,0xC9,0x1C,0xC7,0x14,0xB8,0xFF,
++    0xF0,0x07,0x38,0x01,0x00,0xDF,0xC0,0x1C,0xEF,0x02,0x46,0xF9,0x81,0x16,0xE0,0x82,
++    0x80,0x24,0x00,0x0F,0x00,0xF9,0x87,0x24,0x31,0x1A,0x31,0x52,0x30,0xCA,0xC1,0x24,
++    0xBC,0xFF,0xEF,0xE7,0x40,0x01,0x80,0x0E,0x00,0x01,0x00,0x07,0x01,0x09,0x30,0x5A,
++    0x30,0xD2,0xA1,0x04,0xCF,0x24,0xB8,0xFF,0xE3,0xE7,0xE6,0xF8,0x95,0xFD,0xF7,0x03,
++    0x17,0xC2,0xC5,0x06,0x31,0x0A,0x31,0x42,0xD7,0x34,0xB8,0xFF,0xF0,0x6F,0x86,0x3D,
++    0xE8,0x85,0x07,0x01,0x38,0x82,0x03,0x00,0x40,0x40,0x05,0x00,0x18,0x70,0x00,0x00,
++    0xAE,0xFD,0x87,0x5D,0xC2,0xAC,0xDA,0x03,0x82,0xD4,0xC1,0xAC,0xD9,0x03,0x80,0xCC,
++    0x01,0x09,0x58,0x45,0x89,0xC3,0xC0,0xCC,0xE2,0x00,0x8A,0xC3,0xC4,0xCC,0x89,0xC3,
++    0xC2,0xCC,0xF1,0x00,0x8A,0xC3,0xC6,0xAC,0x82,0x01,0x86,0x54,0xE0,0x0B,0x00,0x21,
++    0x1A,0x0A,0xC0,0x54,0xA2,0x0B,0xC0,0xAC,0xCA,0x03,0x42,0x00,0x80,0xDC,0x09,0x01,
++    0x40,0xBD,0x31,0x52,0x00,0x36,0x00,0x01,0x82,0xFC,0xC0,0xAC,0xCD,0xB4,0x82,0x01,
++    0x82,0x4C,0xC2,0xAC,0x82,0x01,0x84,0x44,0xC0,0x74,0x4A,0x11,0x92,0x05,0x82,0x3C,
++    0xC2,0x6C,0x92,0x05,0x83,0x34,0x82,0xBE,0x10,0x01,0x00,0x01,0x4C,0x4D,0xB1,0x4A,
++    0x8F,0x2C,0x4A,0xF2,0xB2,0x4A,0x8C,0x24,0x48,0xE2,0xEF,0x48,0xB2,0x4A,0x8C,0x1C,
++    0x04,0x08,0xC4,0x48,0x91,0x4D,0x66,0xA5,0xDB,0x74,0xA2,0x1A,0x62,0x8D,0xD9,0x6C,
++    0xA2,0x1A,0xDB,0x24,0x9A,0x3C,0xD9,0x1C,0x9A,0x34,0xD9,0x2C,0x98,0x2C,0x41,0x09,
++    0x89,0x5E,0xD8,0x3C,0x12,0xDA,0x92,0xDD,0x99,0x3C,0xD9,0x34,0x12,0xDA,0x92,0xDD,
++    0x99,0x34,0xD9,0x2C,0x12,0xDA,0x92,0xDD,0x9A,0x2C,0xD9,0x5C,0x32,0xE2,0xDC,0x64,
++    0x9A,0x64,0xD9,0x34,0xE1,0x3C,0xEA,0x34,0xCA,0xD8,0x92,0xDD,0xEB,0x3C,0xC9,0x20,
++    0x91,0x25,0xF3,0x2C,0xED,0x64,0xC9,0x68,0xA8,0x64,0x59,0x01,0xD9,0x86,0xEB,0xD4,
++    0x13,0x5A,0xD5,0x6E,0x63,0x01,0xD8,0x5E,0xED,0xCC,0x11,0x62,0xD1,0x46,0xEB,0x64,
++    0xC5,0x6B,0x49,0x68,0x8B,0x06,0x32,0x2A,0x3F,0x01,0xF8,0x7A,0xEB,0x2C,0x01,0x68,
++    0x23,0x62,0x35,0x32,0x2B,0x01,0xF8,0xAA,0xF5,0xDC,0x11,0xAA,0xEA,0xC6,0xF2,0xB4,
++    0x71,0x09,0x88,0x16,0xD9,0xF0,0x93,0xB5,0xB2,0x9C,0xF8,0x5C,0x35,0x01,0xF8,0xF2,
++    0x10,0x72,0xDD,0x06,0x35,0xAA,0x81,0x68,0x01,0x68,0x33,0x7A,0xF3,0x9C,0x10,0x6A,
++    0x12,0xAA,0xE5,0x2E,0x6B,0xA5,0xA1,0x62,0x6B,0x8D,0xA1,0x5A,0x01,0xA8,0x72,0xBD,
++    0xC9,0x68,0xE5,0x72,0xE1,0xB0,0xA3,0x72,0xEB,0xFC,0xE0,0x68,0x90,0x6D,0xAF,0xFC,
++    0xF5,0x9C,0x10,0xBA,0xD1,0xBE,0x05,0x9F,0x09,0xEF,0x6A,0xA5,0xA1,0x62,0x6B,0x8D,
++    0xA2,0x5A,0x03,0xB0,0x6B,0xBD,0xC9,0xA8,0xE3,0x72,0xE1,0xB0,0xA0,0x72,0xE9,0xFC,
++    0xE7,0x68,0x93,0x6D,0xAD,0xFC,0x38,0x37,0xE9,0x64,0xC1,0x6B,0x48,0x68,0x6D,0x19,
++    0x8A,0x6E,0x00,0xB0,0x7F,0xBD,0xC9,0xB0,0xE0,0xB2,0x71,0x09,0xC2,0x3E,0xC0,0x64,
++    0x08,0x01,0xC6,0x03,0x1A,0x42,0xC8,0x64,0x82,0x43,0x80,0x7D,0xE8,0x85,0x6F,0x11,
++    0x89,0x56,0x68,0xA5,0xA1,0x62,0x63,0x8D,0xA2,0x1A,0x03,0x98,0x4A,0xBD,0xC1,0xC8,
++    0xE2,0x5A,0xE0,0xD8,0xA0,0x5A,0x00,0x1F,0xCA,0x4C,0xF2,0x4B,0x4F,0x51,0x90,0x66,
++    0xE6,0x00,0x92,0x05,0x40,0x11,0x90,0x06,0x3A,0xD7,0xE2,0x90,0x90,0x95,0x56,0x21,
++    0x92,0x06,0x38,0x57,0x01,0x01,0x80,0x6C,0xC0,0xB4,0x42,0x09,0x88,0xF6,0x03,0x01,
++    0x80,0x84,0x01,0x01,0x81,0x7C,0xC9,0x84,0x42,0xBD,0x01,0x48,0xC2,0x40,0x80,0x14,
++    0xC1,0x7C,0xC9,0x84,0x02,0x00,0xC4,0x00,0x91,0x05,0x86,0x54,0xCA,0x7C,0xC1,0x14,
++    0xE0,0x2A,0x6A,0x09,0xC1,0x26,0xC0,0x6C,0xE6,0x00,0x92,0x05,0x87,0x6C,0x01,0x8F,
++    0xC0,0x7C,0x41,0x09,0x89,0x16,0xC0,0x84,0x47,0x01,0x88,0xC6,0x08,0x81,0x41,0x45,
++    0x86,0x1F,0xC0,0x77,0xC0,0x6C,0x82,0x3C,0xC0,0x74,0x82,0x34,0xC0,0x5C,0x82,0x0C,
++    0xC0,0x64,0x82,0x04,0xC4,0x84,0xE1,0x00,0x3C,0x00,0x7C,0x00,0x50,0x5A,0xB4,0xA2,
++    0xE8,0x98,0xB0,0xCA,0x31,0x62,0x74,0x4D,0xB1,0x8A,0xC1,0x84,0xB0,0x82,0x80,0x24,
++    0xC0,0x84,0xB1,0xC2,0x81,0x1C,0xD0,0x84,0xB0,0x82,0x85,0x14,0xC0,0x7C,0x41,0x09,
++    0x88,0x5E,0xC0,0x24,0x12,0x02,0x92,0x05,0x80,0x24,0xC0,0x1C,0x12,0x02,0x92,0x05,
++    0x80,0x1C,0xC0,0x14,0x12,0x02,0x92,0x05,0x80,0x14,0x00,0x01,0x83,0x2C,0xE0,0x68,
++    0xAD,0xF4,0x01,0x9F,0x40,0x61,0x98,0x66,0xC8,0x24,0xC0,0x34,0xD2,0x54,0xD1,0x00,
++    0x4C,0xA5,0xA1,0x42,0xC8,0x1C,0xC0,0x3C,0xD2,0x54,0xD1,0x00,0x4C,0x8D,0xA1,0x42,
++    0x00,0x47,0x15,0x01,0xDC,0x0C,0x00,0x28,0xF0,0xD2,0x5C,0x45,0x88,0xD2,0x12,0x01,
++    0x90,0x74,0xD1,0x3C,0x92,0x95,0x92,0x0C,0xD2,0x34,0x90,0x95,0x91,0x04,0xD2,0x74,
++    0x50,0x09,0x88,0x3E,0x12,0x12,0x93,0xA5,0x32,0x12,0x13,0x92,0x94,0x95,0x32,0xA2,
++    0x12,0x4A,0x92,0x4D,0xD2,0x0C,0xDA,0x04,0xF0,0x0C,0x00,0x07,0x01,0xEF,0xB4,0x24,
++    0xF1,0x04,0xB0,0x64,0x01,0x70,0xB2,0xFC,0x22,0x12,0x93,0x95,0xCA,0xD8,0x90,0xDD,
++    0xF9,0x24,0xF1,0xFC,0xC9,0xB0,0xB7,0x24,0xF3,0x64,0xC1,0xB0,0xB0,0x64,0x51,0x01,
++    0xD9,0xBE,0xF0,0xD4,0x10,0x92,0xD5,0xA6,0x58,0x01,0xD8,0x96,0xF5,0xCC,0x11,0x9A,
++    0xD1,0x7E,0xF8,0x24,0x35,0x01,0xF8,0xF2,0xF9,0x64,0xC1,0xFB,0x48,0xF8,0x8D,0x46,
++    0xFD,0xDC,0x11,0xF2,0xE8,0x2E,0x78,0x45,0xCD,0xFA,0xCB,0xF0,0x7B,0x45,0x88,0xF2,
++    0x39,0xD7,0xD6,0x74,0xE6,0x90,0x92,0x95,0x91,0x74,0xD1,0x74,0x55,0x11,0x98,0xF6,
++    0x41,0x01,0x80,0xF6,0xF2,0x10,0xF2,0x44,0x00,0x90,0x5C,0x45,0xC7,0xD2,0xCC,0xB3,
++    0xCC,0xDA,0xCA,0xB0,0x11,0xF2,0x94,0x86,0xD0,0x2C,0x50,0x09,0x88,0x8E,0xD1,0x24,
++    0xC1,0x34,0xD8,0x54,0xD1,0x00,0x54,0xA5,0xA0,0x82,0xDE,0x1C,0xD1,0x3C,0xE8,0x54,
++    0xD1,0x90,0x5E,0x8D,0xA8,0xD2,0xEA,0x14,0xDA,0x04,0xD8,0xE8,0x36,0x1A,0xD3,0x90,
++    0x90,0x95,0xDA,0x00,0x93,0x1D,0xD2,0x40,0x2C,0x01,0x30,0x01,0x50,0x01,0xD8,0x56,
++    0xFD,0xD4,0x11,0xD2,0xD0,0x3E,0x58,0x01,0xD9,0x2E,0xF8,0xCC,0x10,0xDA,0xD5,0x16,
++    0xC1,0x3B,0x18,0xBA,0x83,0x3B,0x20,0x12,0x90,0x95,0xCA,0xD8,0x92,0xDD,0xC2,0x00,
++    0xE7,0x68,0x93,0x6D,0x6F,0x11,0xC8,0x4E,0x04,0xE7,0x10,0x9A,0x90,0x0E,0x10,0x09,
++    0x90,0x2C,0xD8,0x24,0xD6,0x34,0xC0,0x90,0x90,0x95,0x96,0x34,0xD8,0x1C,0xD0,0x3C,
++    0xC6,0x90,0x96,0x95,0x90,0x3C,0xD0,0x14,0xDA,0x0C,0x00,0x90,0xC0,0x90,0x96,0x0C,
++    0xD8,0x14,0xD0,0x04,0xC0,0x90,0x96,0x04,0xE6,0x00,0x92,0x05,0xD4,0xF4,0x11,0x82,
++    0x92,0x06,0x38,0x3F,0xC2,0x7C,0xE1,0x00,0x91,0x05,0x86,0x7C,0xC0,0x7C,0x41,0x11,
++    0x97,0x06,0x30,0xAF,0xC2,0x84,0xE1,0x00,0x91,0x05,0x86,0x84,0xC0,0x84,0x41,0x21,
++    0x97,0x06,0x30,0x37,0x00,0x0F,0x00,0x41,0x81,0x6C,0xC1,0x6C,0x41,0x41,0x88,0xD6,
++    0x10,0x01,0x00,0x01,0x58,0x8A,0xE8,0xC8,0xB4,0xF2,0xB4,0x7A,0x31,0x8A,0x31,0xDA,
++    0x40,0x09,0x88,0x1E,0x12,0x4A,0x92,0x4D,0x12,0xDA,0x92,0xDD,0xE7,0x6C,0xC2,0x18,
++    0x92,0xDD,0xE2,0x74,0xC2,0x08,0x93,0x65,0x04,0x08,0xC4,0x48,0x90,0x4D,0x5E,0x01,
++    0xD9,0x76,0xE8,0xD4,0x10,0x5A,0xD5,0x5E,0x60,0x01,0xD8,0x4E,0xED,0xCC,0x11,0x62,
++    0xD1,0x36,0x68,0xA5,0xA1,0x62,0x63,0x8D,0xA0,0x1A,0x03,0x3F,0xE8,0x62,0x00,0x00,
++    0x62,0xA5,0xD9,0x74,0xA1,0x1A,0x63,0x8D,0xDB,0x6C,0xA2,0x1A,0xE6,0x00,0x92,0x05,
++    0x46,0x11,0x98,0x9E,0xE6,0x90,0x92,0x95,0x56,0x21,0x98,0x56,0x58,0x85,0xE1,0xC3,
++    0xB0,0xC3,0xC8,0xC3,0x98,0xC3,0x00,0x01,0x81,0x04,0x59,0x85,0xE0,0xC3,0xB0,0xC3,
++    0xC8,0xC3,0x98,0xC3,0x00,0x01,0x80,0xE4,0x80,0xEC,0x80,0xF4,0xC4,0xAC,0xCA,0x03,
++    0x80,0xDC,0x01,0x01,0x08,0x01,0x78,0xA5,0x06,0x18,0xCE,0xD0,0x32,0xA2,0x04,0x20,
++    0xC6,0x10,0x93,0x95,0x6D,0xA5,0xE1,0x72,0x33,0x2A,0xA3,0x72,0x6D,0x8D,0xE1,0x6A,
++    0x32,0x12,0xC3,0x90,0x8A,0xAB,0xE0,0x48,0x90,0x4D,0x4E,0x19,0x98,0x86,0x47,0x09,
++    0x80,0x0E,0x40,0x19,0x8F,0x66,0xE0,0xCA,0x33,0xE2,0x31,0x12,0xCB,0x93,0x30,0x2A,
++    0xC7,0x6B,0xA5,0x2A,0x34,0x1A,0xCB,0xE3,0x8C,0xE3,0x80,0xCB,0x34,0x0A,0x8B,0x53,
++    0x09,0x09,0x88,0x14,0x09,0x01,0x88,0x7C,0xD3,0x7C,0x31,0x0A,0xE1,0x4A,0xDC,0x7C,
++    0x36,0x12,0xC3,0x90,0xCA,0x9B,0xC0,0xAB,0xC9,0x93,0x92,0x1C,0xD0,0x7C,0x51,0x01,
++    0x88,0x16,0x41,0x01,0x80,0x0E,0x40,0x19,0x8D,0x5E,0x10,0x4A,0x98,0x4E,0x10,0x09,
++    0x90,0x0C,0x41,0x01,0x8A,0x16,0xF0,0x10,0x90,0x14,0x01,0xF7,0x11,0x09,0x90,0x14,
++    0x00,0xDF,0x40,0x09,0x80,0x0E,0x40,0x11,0x8D,0x5E,0x10,0x4A,0xC0,0x4E,0x10,0x09,
++    0x90,0x0C,0x41,0x09,0x8C,0x16,0xF0,0x10,0x90,0x14,0x01,0x77,0x11,0x09,0x90,0x14,
++    0x00,0x5F,0x10,0x01,0x90,0x0C,0x01,0x47,0x11,0x09,0x90,0x0C,0x40,0x11,0x90,0x16,
++    0xF1,0x90,0x94,0x14,0x00,0x0F,0x10,0x09,0x90,0x14,0x41,0x01,0x80,0x0E,0x40,0x19,
++    0x8D,0x0E,0x10,0x4A,0x90,0x2E,0x40,0x09,0x80,0x0E,0x40,0x11,0x8D,0x26,0x10,0x4A,
++    0xC0,0x16,0x10,0x09,0x94,0x5C,0x01,0x8F,0x11,0x01,0x90,0x5C,0x01,0x77,0xD4,0xCC,
++    0x32,0x3A,0x19,0xBA,0xD1,0xA4,0xF2,0xEC,0xC4,0xD0,0xCD,0x90,0x91,0x64,0xD1,0x64,
++    0xC1,0x93,0x90,0xE4,0x31,0x90,0xA2,0xD6,0xF3,0xA4,0x02,0xD0,0xC9,0x90,0xF4,0x44,
++    0x04,0xB0,0xCB,0x90,0x31,0x19,0x10,0xB0,0xC8,0xB0,0x14,0x21,0xF1,0x92,0xF5,0xDC,
++    0x10,0x92,0xD5,0x26,0xF0,0x6C,0x71,0x41,0x88,0xC6,0x50,0x01,0xD9,0xB6,0xF0,0xE4,
++    0x48,0xB0,0x87,0x06,0x80,0x90,0xF2,0xE4,0xC0,0xB0,0xB5,0xE4,0xF0,0x44,0xF9,0xF4,
++    0x1F,0xB2,0xCA,0xB0,0xB0,0xF4,0xF0,0xEC,0x1C,0x12,0xCB,0x90,0x91,0xEC,0xD0,0x04,
++    0xE4,0x90,0x92,0x95,0x91,0x04,0xD1,0xE4,0x48,0x90,0x8E,0xEE,0xD0,0x44,0xF2,0xFC,
++    0xCD,0x93,0x12,0x92,0xC1,0x2E,0xD0,0xE4,0x31,0x01,0x1E,0x92,0xF1,0x64,0x81,0x93,
++    0x01,0x47,0xD0,0xE4,0x31,0x01,0x1A,0x92,0xF1,0x64,0x81,0x93,0x01,0x17,0xD0,0x0C,
++    0x50,0x09,0x80,0x4E,0xD0,0x0C,0x51,0x09,0x8A,0x36,0xD0,0x6C,0x10,0xA2,0x84,0x1E,
++    0xD5,0x14,0xC1,0x10,0x95,0xA5,0x3A,0x57,0x10,0x4A,0x8D,0xDE,0xD4,0x1C,0x11,0x9A,
++    0x89,0xC6,0xC8,0x7C,0xE6,0x48,0x92,0x4D,0x89,0x7C,0xC9,0x7C,0x48,0x11,0x90,0x06,
++    0x3A,0x97,0xE2,0x00,0x90,0x05,0x46,0x21,0x91,0x06,0x38,0x1F,0xC2,0x4C,0xF2,0x03,
++    0x42,0x01,0x88,0x5E,0xC9,0xAC,0x8A,0x01,0xD8,0x43,0x36,0x10,0xAA,0x36,0x31,0x00,
++    0x71,0x00,0x04,0x27,0xD0,0x5C,0x51,0x01,0x8D,0x5E,0x10,0x4A,0xCA,0x16,0xF0,0x48,
++    0x90,0x4D,0x06,0x1F,0x10,0x4A,0x95,0x0E,0xE6,0x48,0x92,0x4D,0x11,0x09,0x90,0x5C,
++    0x01,0x67,0xD0,0x1C,0x10,0x9A,0xCC,0x16,0xF6,0xD8,0x92,0xDD,0x01,0x27,0xD0,0x1C,
++    0x10,0x9A,0x94,0x0E,0xE6,0xD8,0x92,0xDD,0x11,0x01,0x90,0x5C,0x91,0x55,0x92,0x44,
++    0x97,0xE5,0x72,0xFA,0xD4,0x44,0xC9,0x90,0x93,0xEC,0x39,0x47,0x02,0x01,0xD0,0xAC,
++    0x6C,0x94,0x12,0x12,0x9A,0xD6,0xC0,0xAC,0xE4,0x4B,0x68,0x04,0x10,0x42,0x9C,0x26,
++    0xC4,0x44,0xCA,0x03,0xF6,0x00,0x94,0x05,0x02,0x1F,0xC0,0x44,0xCC,0x03,0xE4,0x00,
++    0x91,0x05,0xCE,0x04,0x10,0x0A,0x9C,0x4E,0xC0,0xAC,0x0A,0x01,0xB2,0x0B,0xC4,0x54,
++    0x08,0xD9,0xE7,0x03,0x02,0x42,0xC8,0x54,0xA2,0x43,0x28,0x37,0x27,0x01,0x30,0xF9,
++    0xB0,0x09,0x60,0x01,0x8A,0x4E,0xC0,0x3C,0xC8,0xCC,0xF9,0xF4,0xD2,0x54,0x42,0x93,
++    0x97,0x9C,0x50,0x42,0xDE,0x74,0xB2,0xAA,0x02,0x47,0xC0,0x34,0xC8,0xD4,0xF9,0xEC,
++    0xD4,0x54,0x42,0x93,0x97,0x9C,0x50,0x22,0xDE,0x6C,0xB2,0xAA,0x40,0x01,0x80,0x16,
++    0xF4,0x48,0x12,0x42,0x8A,0x8E,0xD0,0x74,0x96,0x04,0x90,0x05,0x32,0x0A,0xD9,0x6C,
++    0xD7,0x5C,0xBA,0xEF,0xD1,0x77,0x37,0x8A,0x10,0x82,0xED,0x0E,0x30,0x42,0x00,0x17,
++    0x40,0x01,0xD0,0x06,0x02,0x01,0xC8,0x28,0x04,0x07,0xA8,0x01,0x10,0xC0,0xC9,0xE4,
++    0x81,0x17,0xF0,0x47,0xCA,0x9C,0xC8,0x00,0x18,0x42,0x42,0x01,0xD0,0x06,0x00,0x01,
++    0xA0,0x00,0x60,0x01,0x8A,0x7E,0xC8,0x54,0x44,0x4C,0x10,0x0A,0xD0,0x06,0x30,0x42,
++    0xC8,0xAC,0x12,0x31,0xF2,0x4B,0x1C,0x8A,0xD4,0xA4,0xC2,0x48,0x12,0x19,0x0A,0x90,
++    0xC4,0x48,0x0C,0x44,0x02,0x77,0xC8,0x54,0x44,0x4C,0x12,0x0A,0xD0,0x06,0x30,0x42,
++    0xC8,0xAC,0x12,0x31,0xF2,0x4B,0x1C,0x8A,0xD4,0xA4,0xC2,0x48,0x12,0x19,0x0A,0x90,
++    0xC6,0x48,0x0C,0x44,0xE7,0x20,0x93,0x25,0x65,0x09,0xC8,0x16,0xC0,0xAC,0x12,0x31,
++    0xD8,0x0B,0xC6,0xE4,0x02,0x42,0xCE,0xAC,0xF2,0x4B,0x1C,0x8A,0xD4,0xA4,0xC2,0x48,
++    0x12,0x19,0x0A,0x90,0xC0,0x48,0x14,0x44,0xC2,0xAC,0xCA,0x74,0xF2,0x03,0x04,0x10,
++    0xC0,0xA4,0xC2,0x90,0x04,0x09,0x09,0x00,0xC0,0x90,0xB0,0x8B,0xCA,0xAC,0xD2,0x6C,
++    0xF2,0x4B,0x04,0x58,0xCA,0xA4,0xC2,0xC8,0xC2,0x40,0xB0,0x13,0xC2,0xAC,0xCA,0xAC,
++    0xF2,0x03,0xE4,0x00,0xB6,0x43,0x24,0x07,0xAC,0xFD,0x87,0xDD,0xF4,0x24,0x31,0xB2,
++    0x33,0xFA,0xD8,0x83,0x81,0x94,0xD8,0x83,0x81,0x8C,0xC8,0x83,0x80,0x84,0x00,0x01,
++    0x85,0x6C,0x40,0x32,0x41,0x0B,0x32,0x82,0x80,0x01,0x85,0xD4,0x48,0x01,0x80,0x1E,
++    0xC2,0x84,0x40,0x00,0x80,0x74,0x00,0x67,0xC2,0xD4,0xF0,0x03,0x40,0x51,0x98,0x26,
++    0xC8,0xD4,0x00,0xD9,0xB0,0x42,0x80,0x74,0x00,0x1F,0xC8,0xD4,0x00,0xD1,0xB0,0x42,
++    0x86,0x74,0x08,0x09,0x03,0x48,0xC4,0xC8,0xC0,0xDC,0x88,0xCC,0x41,0x01,0x80,0xEE,
++    0x04,0x29,0x04,0x00,0xC1,0xD8,0x31,0xCA,0x89,0xF9,0x8F,0x29,0xE0,0xCC,0xC0,0x84,
++    0x42,0x00,0x12,0x02,0x90,0x05,0x82,0x6C,0x04,0x01,0x30,0x22,0x00,0x8F,0x00,0x01,
++    0x00,0x47,0xC0,0xEB,0xC5,0x53,0xD0,0x68,0x05,0x2C,0xE1,0x20,0xE2,0xD8,0xE2,0x48,
++    0xE6,0x00,0x92,0x05,0xED,0x8C,0x10,0x42,0x9B,0x9E,0x37,0x02,0xE6,0x00,0x92,0x05,
++    0x30,0x22,0xC4,0x94,0x2F,0x22,0x9C,0x56,0x30,0x82,0x43,0x01,0x84,0x06,0x38,0x02,
++    0x06,0xC9,0x07,0x00,0xC7,0xD8,0x01,0xF9,0x01,0x00,0xC6,0xC0,0x4B,0x02,0xC4,0xC8,
++    0x10,0x01,0x00,0x47,0x40,0x24,0x40,0x6C,0xD8,0x20,0x03,0xE4,0xE4,0xD8,0xE4,0x00,
++    0xE2,0x48,0xE4,0x90,0x90,0x95,0xE6,0x8C,0x17,0x12,0x9D,0x9E,0x41,0xA2,0xC3,0xC0,
++    0x80,0x64,0xE8,0xCC,0x00,0x01,0x80,0x9C,0x34,0x82,0x81,0x01,0x83,0xC4,0xC0,0x01,
++    0x85,0xBC,0x80,0x01,0x85,0xB4,0x08,0x8F,0x25,0x01,0x08,0x3F,0xC0,0x64,0xC0,0x03,
++    0x4B,0x00,0x8C,0xF6,0xF0,0x42,0xC9,0x84,0x13,0x42,0xDC,0xD6,0xC3,0x8C,0x30,0x5A,
++    0x01,0x00,0xD2,0x48,0x31,0x52,0xD0,0x01,0x5C,0x94,0x1E,0xD4,0x46,0x54,0x18,0xD4,
++    0x40,0x4C,0x22,0xCC,0x31,0x4A,0xC9,0x01,0x5A,0x4C,0x26,0xCC,0x44,0x4C,0x21,0xCC,
++    0x46,0x4C,0x23,0xCC,0xC8,0x08,0x32,0x52,0xD6,0x01,0x59,0x94,0x29,0xD4,0xD0,0x42,
++    0x2A,0xC4,0x42,0x44,0x28,0xC4,0x44,0x3D,0x60,0x01,0x88,0x66,0x0C,0x01,0x18,0xCC,
++    0x20,0xCC,0x2A,0xCC,0x10,0xCC,0x0C,0xF9,0x0B,0x48,0xC4,0xC8,0x4E,0x54,0x10,0xD4,
++    0x48,0x4C,0x1A,0xCC,0x00,0x87,0xC9,0x8C,0xF4,0x48,0x12,0x62,0x88,0xC6,0x10,0x01,
++    0x30,0x5A,0x23,0xD4,0x24,0xD4,0x2E,0xD4,0xD0,0x8C,0x18,0xF9,0xF2,0x90,0x04,0x90,
++    0xCC,0x90,0x0E,0xD8,0xC0,0x90,0x4E,0x94,0x34,0x5A,0x13,0xD4,0x06,0x48,0xCA,0x50,
++    0x0C,0xF9,0x08,0x48,0xC0,0x88,0x4A,0x4C,0x10,0xCC,0x0E,0x01,0x18,0xCC,0x00,0x9F,
++    0xF2,0x08,0x03,0x48,0xC8,0x50,0x0E,0xF9,0x0A,0x48,0xC4,0x90,0x4B,0x94,0x30,0x5A,
++    0x13,0xD4,0x04,0x10,0xCA,0x90,0xC6,0x90,0x4E,0x94,0x10,0xD4,0xE2,0x10,0x03,0x90,
++    0xCA,0x90,0xC6,0x88,0x48,0x4C,0x18,0xCC,0xC8,0x9C,0x48,0x01,0x8B,0x26,0x30,0x5A,
++    0x1E,0xCC,0x1C,0xCC,0x20,0xCC,0x00,0x4F,0xC8,0x94,0xD0,0x9C,0xF4,0x48,0x12,0x52,
++    0x88,0x26,0x08,0x01,0x30,0x5A,0x2B,0xCC,0x2C,0xCC,0x2A,0xCC,0x0B,0x01,0xF0,0x4A,
++    0x33,0x62,0x34,0x5A,0x14,0xE1,0xF0,0xD2,0x10,0x52,0xE4,0x16,0x14,0xF1,0xF0,0xD2,
++    0x04,0x07,0x00,0x07,0x13,0x52,0xD4,0xF6,0x14,0x01,0xF1,0xD2,0x17,0x52,0xD4,0xD6,
++    0x14,0x11,0xF1,0xD2,0x17,0x52,0xE4,0x86,0x14,0x31,0xF1,0xD2,0x17,0x52,0xD4,0x96,
++    0x14,0x41,0xF1,0xD2,0x17,0x52,0xD4,0x76,0x14,0x51,0xF1,0xD2,0x17,0x52,0xE4,0x26,
++    0x14,0x61,0xF1,0xD2,0x17,0x52,0xE4,0x06,0xCA,0xC4,0xE0,0x4B,0x4B,0x01,0x80,0xCE,
++    0x0C,0x01,0x30,0x72,0x88,0x14,0x88,0x1C,0x88,0x7C,0x10,0x01,0xC8,0xDC,0x48,0x01,
++    0x88,0x96,0x8B,0x24,0x1E,0x01,0xF0,0x1A,0xE8,0xC8,0xD2,0x36,0xC0,0xC8,0x94,0x55,
++    0xCA,0x1C,0xE0,0x48,0x90,0x4D,0x8E,0x1C,0x00,0x2F,0x58,0x51,0xE8,0x1E,0xC8,0x14,
++    0xE6,0x48,0x92,0x4D,0x8C,0x14,0xE0,0x00,0xCA,0x24,0xE0,0x48,0x90,0x4D,0x8E,0x24,
++    0xC8,0x24,0x48,0x49,0x9B,0x36,0x37,0x02,0xC0,0x00,0x94,0x05,0xD5,0xBC,0x68,0x8C,
++    0xE4,0x93,0x10,0x8A,0x98,0x0E,0xC9,0x74,0x10,0x42,0xD4,0xF6,0xC8,0x14,0x48,0x39,
++    0x98,0x8E,0xC8,0x74,0x84,0x48,0x12,0x0A,0xD8,0xBE,0xC0,0x1C,0x40,0x01,0x00,0x4F,
++    0x30,0x20,0x06,0x00,0xE0,0xD2,0x07,0x00,0xE0,0xD2,0x06,0x00,0x58,0x80,0x04,0x01,
++    0x40,0x40,0x01,0x00,0x88,0x4E,0xC0,0xD4,0xF0,0x03,0x42,0x11,0x98,0x0E,0x00,0x09,
++    0x37,0x32,0x4C,0xFA,0xC2,0x43,0xE2,0x00,0x80,0x43,0xC2,0xC4,0xE0,0x03,0x40,0x01,
++    0x83,0xFE,0x30,0x82,0x40,0x01,0x88,0xE6,0xC2,0xD4,0xF0,0x03,0x40,0x51,0x98,0xC6,
++    0x30,0x5A,0x03,0xB1,0x08,0x91,0xF1,0xC2,0xF4,0x8A,0x13,0x42,0xD8,0x5E,0x08,0xA1,
++    0xF2,0xCA,0x82,0x48,0x04,0x07,0x00,0xDF,0x10,0x42,0xDC,0x26,0x0A,0xC1,0xF0,0xCA,
++    0x84,0x48,0x12,0x42,0xD0,0x2E,0x00,0x09,0x37,0x32,0x4C,0x6A,0xC2,0x43,0xE2,0x00,
++    0x87,0x43,0x52,0x5A,0xC0,0x83,0x40,0x81,0x97,0x16,0x4A,0x52,0xA2,0x62,0xE0,0x00,
++    0x81,0x83,0x00,0xEF,0x07,0x57,0x3A,0xFF,0x30,0x1A,0x9B,0x04,0x83,0xC8,0x24,0x0A,
++    0x90,0x4D,0x88,0x0C,0x08,0x01,0x88,0x24,0xCA,0x6C,0x80,0x48,0x88,0xAC,0x18,0x01,
++    0xF0,0x1A,0xCE,0xAC,0x9C,0xA4,0x10,0x5A,0xD0,0x6E,0xD8,0xA4,0xCA,0x04,0xC0,0xC8,
++    0x90,0x4D,0x88,0x04,0xD8,0xA4,0xC8,0x6C,0x10,0x5A,0xD4,0x26,0x32,0x1A,0x83,0xC8,
++    0x20,0x0A,0x93,0x4D,0x88,0x0C,0xC8,0xA4,0xC0,0x48,0x94,0x55,0xE0,0x00,0xCC,0x24,
++    0xE6,0x48,0x92,0x4D,0x88,0x24,0xC8,0x24,0x4F,0x49,0x98,0x06,0xC4,0x0C,0x10,0x12,
++    0xD8,0x66,0xC8,0x74,0xC4,0x04,0x10,0x42,0xD8,0x46,0xC0,0xC4,0xE0,0x03,0x40,0x01,
++    0x83,0x36,0x30,0x5A,0x00,0xB1,0xF0,0xC2,0x40,0x01,0xD0,0x0E,0x04,0x09,0x30,0x32,
++    0xC2,0xD4,0xF0,0x03,0x40,0x51,0x98,0x16,0xC0,0xDC,0x40,0x01,0x80,0x46,0x00,0x09,
++    0x30,0x8A,0x4B,0x01,0x80,0x06,0x00,0x01,0x80,0x7C,0x00,0x0F,0x00,0x09,0x80,0x7C,
++    0xC0,0x7C,0x40,0x01,0x80,0xA6,0x01,0x09,0xB5,0x83,0x47,0xFA,0x40,0x03,0x42,0x01,
++    0x88,0x5E,0xC0,0xD4,0xF0,0x03,0x42,0x51,0x90,0x3E,0xC0,0xBC,0x6E,0x8C,0xDB,0x03,
++    0x32,0x00,0x72,0x00,0x84,0x51,0x10,0x0A,0xC8,0x0E,0x10,0x01,0x00,0x07,0x10,0x09,
++    0xC0,0xE4,0x40,0x01,0x80,0x06,0x10,0x11,0x91,0x14,0x30,0x1A,0xB8,0x04,0xB0,0x0C,
++    0x30,0x42,0xD1,0x9C,0xCF,0x64,0xB8,0xFF,0xC8,0x5F,0xC7,0xB4,0xE2,0x03,0x38,0x00,
++    0xAD,0x1E,0xF0,0x83,0xFC,0x8B,0x13,0x42,0x98,0x56,0xC0,0xB4,0xE2,0x03,0x38,0x00,
++    0xA7,0x26,0x00,0xF1,0xA8,0x83,0xC9,0xB4,0x04,0x01,0xA0,0x43,0x87,0xFD,0xE8,0x85,
++    0xE0,0x68,0xC5,0x64,0xE0,0x00,0x82,0x64,0xE7,0x20,0x93,0x25,0xC4,0x8C,0x10,0x22,
++    0x92,0x06,0x30,0x9F,0xC2,0x9C,0xE0,0x00,0x90,0x05,0x86,0x9C,0xC8,0x94,0xC0,0x9C,
++    0x10,0x42,0x94,0x06,0x37,0x47,0x3A,0x4F,0xAC,0x9D,0x87,0x3D,0x30,0x3A,0xC0,0x44,
++    0xD0,0x03,0x84,0x24,0xC6,0x44,0xD0,0x23,0x41,0xC2,0xC4,0xE8,0x06,0xF9,0x07,0x00,
++    0xC0,0xF0,0xC1,0x44,0x08,0xF1,0xE8,0x03,0x84,0x17,0xD8,0xA7,0x04,0x29,0x04,0x00,
++    0xC4,0xD0,0x41,0x9A,0x37,0xDA,0x99,0xF9,0xC1,0xC0,0x99,0x29,0x80,0x34,0x48,0xE9,
++    0x88,0xDE,0x08,0x01,0x00,0x5F,0x00,0x01,0x00,0x2F,0xC0,0xFB,0x82,0xBB,0xE0,0x90,
++    0xE2,0xD8,0xE2,0x00,0x95,0x05,0x16,0x02,0x9A,0xBE,0xE7,0x48,0x90,0x4D,0xC6,0x24,
++    0x17,0x0A,0x9C,0x86,0x00,0x01,0x00,0x2F,0x41,0x8C,0x01,0x4C,0xE5,0x68,0xE5,0xB0,
++    0xE6,0x00,0x92,0x05,0x17,0x02,0x9D,0xBE,0x00,0xCF,0xC3,0x44,0x82,0x01,0xF5,0x03,
++    0x43,0x51,0x98,0xA6,0xC4,0x44,0xF0,0x03,0x80,0x2C,0x40,0x01,0x80,0x7E,0x9B,0x1C,
++    0xF3,0x34,0x08,0x21,0x1B,0x01,0x00,0x21,0x30,0x32,0x04,0x01,0x30,0x22,0x84,0x14,
++    0x29,0x01,0x00,0x1F,0x00,0x01,0x80,0x0C,0x01,0x97,0xC0,0xBB,0x48,0xF8,0x85,0x66,
++    0x10,0x0A,0xCC,0x0E,0x30,0x0A,0x00,0x17,0x10,0x1A,0x94,0x06,0x30,0x1A,0xF8,0x14,
++    0xE7,0xF8,0x93,0xFD,0xB8,0x14,0x38,0x09,0xBB,0x0C,0xE0,0xB0,0xE6,0x00,0x92,0x05,
++    0x17,0x02,0x9D,0x56,0xC0,0x0C,0x40,0x01,0x85,0x36,0x28,0x72,0xCD,0x0E,0x30,0x72,
++    0x05,0x17,0x28,0x62,0x95,0x06,0x30,0x62,0xE7,0x68,0x93,0x6D,0xC4,0x24,0x10,0x2A,
++    0x98,0xC6,0xC6,0x2C,0x2B,0x51,0x18,0x42,0xED,0x14,0x10,0x42,0xC8,0xB6,0x48,0x01,
++    0x82,0x0E,0xF0,0x48,0x93,0x4D,0xF6,0x00,0x10,0x1A,0xD4,0x0E,0xE6,0xD8,0x92,0xDD,
++    0x30,0x82,0x43,0x01,0x82,0x16,0xF0,0x00,0x94,0x05,0x36,0x32,0xEB,0x24,0xF0,0x68,
++    0x28,0x62,0xD5,0x1E,0x32,0x02,0xE3,0x00,0x94,0x05,0x36,0x22,0x28,0x01,0x00,0xDF,
++    0x00,0x01,0x00,0xAF,0x10,0x42,0x9C,0x2E,0x28,0xAA,0x9B,0x1E,0x10,0xC2,0xC4,0x0E,
++    0x28,0x2A,0xCB,0x3E,0xC1,0xB3,0x08,0xB8,0xD8,0xF8,0xF5,0x1C,0xC7,0xB3,0xC9,0xB0,
++    0x48,0xB0,0x81,0xB3,0xE0,0x90,0xF2,0x1C,0xE0,0xB0,0xB3,0x1C,0xE6,0x00,0x92,0x05,
++    0x17,0x02,0x9D,0x3E,0xE7,0x68,0x93,0x6D,0xC4,0x24,0x10,0x2A,0x98,0x06,0xC7,0x34,
++    0x10,0x01,0x00,0x67,0x08,0x01,0x00,0x37,0xC4,0x1B,0x30,0xD8,0x70,0xD8,0x84,0x1B,
++    0xE2,0x00,0xE2,0x48,0x95,0x4D,0x16,0x0A,0x9A,0xB6,0xE7,0x90,0x90,0x95,0xCE,0x24,
++    0x17,0x52,0x9C,0x7E,0x87,0x4D,0xE8,0x85,0xAC,0xFD,0x87,0x1D,0x30,0x2A,0x30,0x62,
++    0x05,0x01,0xB0,0x03,0xB1,0x03,0x37,0x02,0x80,0x01,0xE6,0x0B,0x10,0xE9,0x07,0x52,
++    0x3E,0x48,0x7A,0x48,0x00,0x48,0x1A,0x52,0xA0,0x13,0xE0,0x0B,0x10,0xD9,0x07,0x8A,
++    0xA1,0x0B,0x30,0x02,0x80,0x01,0x84,0x14,0xE1,0x03,0x7A,0x4A,0x40,0x01,0x80,0x56,
++    0x01,0x01,0x50,0x42,0x08,0xF9,0xA7,0x8A,0xE6,0x00,0x92,0x05,0x47,0x81,0x98,0xD6,
++    0x01,0x01,0x80,0xC3,0x80,0xC3,0xA3,0x04,0x30,0x5A,0x01,0x01,0xD0,0x34,0xC8,0x2C,
++    0xBE,0xFF,0xE7,0xD7,0x35,0x32,0xB1,0x01,0xF0,0x83,0x43,0x51,0x98,0x36,0xA0,0x04,
++    0x30,0x5A,0x01,0x09,0xD0,0x34,0xC8,0x2C,0xBE,0xFF,0xE7,0x77,0xC2,0x14,0xE0,0x03,
++    0x43,0x01,0x80,0xF6,0x45,0xB2,0xF0,0x0B,0xC2,0x03,0x02,0x00,0x10,0x0A,0xCC,0x1E,
++    0x48,0x9A,0x00,0x01,0x81,0x43,0x02,0xDF,0x48,0x8A,0xC0,0x43,0x30,0x22,0x44,0x21,
++    0xC0,0xB6,0x01,0x01,0x00,0x8F,0x59,0x7A,0xE7,0xCA,0x48,0xF9,0x80,0x5E,0x11,0x01,
++    0xE6,0x08,0x92,0x4D,0x00,0x97,0x78,0x5A,0xE3,0xDA,0xE1,0xFA,0xDA,0xD8,0xE6,0xD8,
++    0x58,0x11,0xC0,0x4E,0x5A,0x32,0xC0,0xD3,0x50,0x01,0x80,0x0E,0xF2,0x90,0x82,0xD3,
++    0x5F,0x22,0x10,0xF9,0xA0,0xD2,0x10,0x09,0xE6,0x48,0x92,0x4D,0x28,0x0A,0x03,0x4F,
++    0x00,0xA0,0x00,0x01,0x58,0x00,0x04,0x01,0x58,0x80,0x04,0x01,0x40,0x40,0x01,0x00,
++    0x30,0x20,0x06,0x00,0x98,0xFE,0x56,0x09,0x8B,0x2E,0x50,0x42,0xC0,0x8B,0x4A,0x01,
++    0x82,0x0E,0xF0,0x48,0x82,0x8B,0xE2,0x00,0x93,0x05,0x7E,0x22,0x2E,0x02,0x9B,0x56,
++    0x08,0x01,0xC0,0x14,0xE1,0x1B,0x32,0x02,0x80,0x01,0x59,0x09,0x8A,0x2E,0x50,0xFA,
++    0xC0,0x93,0x52,0x01,0x80,0x9E,0x08,0x09,0x02,0x8F,0x50,0xE2,0xC0,0x93,0x52,0x01,
++    0x8E,0x46,0xD8,0x3B,0x6B,0x14,0x33,0xF8,0x75,0xF8,0x13,0xD2,0x9F,0x3E,0xF0,0x13,
++    0x50,0x01,0x88,0x26,0x68,0x14,0xE5,0x3B,0x10,0xD2,0x9D,0x06,0x08,0x09,0x48,0x01,
++    0x83,0x2E,0xF0,0x8B,0x48,0x01,0x95,0x3E,0xE3,0x48,0xB2,0x8B,0x03,0x27,0xF0,0x8B,
++    0x48,0x51,0x90,0x0E,0x0B,0x01,0xB0,0x8B,0xF0,0x8B,0x4B,0x51,0x9A,0x0E,0x51,0x5A,
++    0xC0,0x93,0x52,0x01,0x8D,0x8E,0xF0,0x3B,0x78,0x01,0x88,0x76,0x58,0x09,0x88,0x26,
++    0x00,0x07,0x00,0xB7,0xF3,0x48,0xB2,0x8B,0x06,0x3F,0xD8,0x03,0x6A,0x1C,0x33,0x00,
++    0x74,0x00,0x14,0x1A,0x92,0x0E,0xF0,0x48,0xB0,0x8B,0x53,0x11,0x9D,0x16,0x00,0x01,
++    0xB0,0x83,0x03,0x37,0x50,0x09,0x88,0x26,0xF2,0x83,0x43,0x81,0x93,0x0E,0x00,0x21,
++    0xB5,0x83,0xF3,0x0B,0x4B,0x09,0xC8,0x5E,0x07,0x01,0xD0,0x13,0x90,0x04,0x10,0x01,
++    0x02,0xA7,0x00,0x98,0xC9,0xF0,0x1A,0x09,0x0F,0xD8,0xC4,0x98,0xF0,0xF3,0xF2,0xDB,
++    0xFA,0x04,0x00,0xD8,0x1B,0xF2,0x03,0xB0,0xCF,0xB0,0xC3,0x98,0x31,0x19,0x10,0xB0,
++    0xCC,0xD8,0x44,0xDC,0xC4,0xC0,0x90,0x05,0xE6,0x90,0x92,0x95,0x17,0x8A,0xC4,0x46,
++    0x87,0x17,0xC8,0x47,0x40,0x00,0x82,0x0C,0xC8,0x0B,0xC1,0x0C,0x12,0x0A,0x94,0x3E,
++    0x0A,0x01,0x00,0x17,0x02,0x40,0xCA,0x10,0x04,0x09,0x09,0x00,0xC2,0x80,0xF0,0x13,
++    0xF0,0x03,0xD8,0x04,0x02,0x00,0x1A,0xD2,0x02,0x90,0xCA,0x90,0xC0,0x80,0x10,0x19,
++    0x14,0x90,0xC0,0x10,0x00,0x21,0xF0,0x82,0xD4,0x0C,0x10,0x82,0xD0,0x5E,0x31,0x42,
++    0x02,0x17,0xE1,0x10,0x36,0xA2,0x94,0x95,0x01,0x98,0x3A,0x09,0xCD,0xD8,0x0A,0xF8,
++    0xCA,0xD8,0x06,0x30,0x33,0xF2,0xCC,0xB0,0xF7,0xDB,0xC8,0xB0,0xB3,0x9B,0x31,0x9A,
++    0xF3,0xDB,0xB2,0x9B,0x1A,0x31,0x18,0xD2,0x3A,0x19,0xCA,0x90,0x08,0xF8,0x33,0x31,
++    0xCB,0x90,0x1E,0x82,0xCC,0x00,0x4A,0x9C,0xCC,0x00,0x0E,0x1C,0x4E,0x9C,0x0E,0x1C,
++    0x50,0x94,0x10,0x14,0x36,0x12,0x93,0x85,0xF2,0x13,0xF5,0x90,0x16,0x12,0xE4,0xC6,
++    0xF2,0x03,0xF5,0x00,0xB2,0x03,0xE5,0x48,0x95,0x4D,0xF6,0x03,0x15,0x42,0xC4,0xCE,
++    0x31,0x0A,0x31,0x42,0xBF,0xFF,0xEF,0x87,0x87,0x3D,0xE8,0x85,0x00,0xA0,0x00,0x01,
++    0xAC,0xFD,0x87,0x2D,0xE0,0x74,0x00,0x01,0x80,0x1C,0xC0,0x3C,0xD0,0x33,0xC6,0x3C,
++    0x58,0x04,0x86,0x0C,0xC3,0x34,0x18,0x82,0x50,0xFA,0xCF,0x2C,0xC2,0x48,0xC4,0x08,
++    0x8F,0x24,0x40,0xF2,0xC0,0x03,0x40,0x09,0x88,0x0E,0xC0,0x3C,0xD8,0x33,0x04,0x01,
++    0x10,0x01,0x00,0x1F,0x82,0x53,0xE0,0x48,0xE6,0x00,0x92,0x05,0x17,0x82,0x9D,0xCE,
++    0x08,0x01,0x00,0x09,0xD8,0x44,0xD0,0x34,0x86,0x07,0xD0,0x6F,0x28,0x01,0x60,0x01,
++    0x8B,0x0E,0xE0,0x68,0x90,0x6D,0xFF,0x24,0x08,0x01,0x00,0x5F,0xC1,0xC3,0x19,0x02,
++    0x91,0x05,0x86,0xC3,0xD4,0x7C,0x10,0x82,0xCD,0x0E,0x18,0x02,0x83,0xC3,0xE1,0xF8,
++    0xE6,0x48,0x92,0x4D,0x17,0x8A,0x9D,0x8E,0x08,0x09,0xC6,0x2C,0x02,0x48,0xC4,0x00,
++    0x80,0x14,0xD0,0x44,0x90,0x04,0x00,0x11,0xD8,0x3C,0xD0,0x2C,0xC8,0x34,0x80,0x07,
++    0xD8,0x07,0xD0,0x44,0xC0,0x3C,0x90,0x04,0x82,0x01,0xCA,0x0B,0x00,0x01,0x1C,0x0A,
++    0x10,0x01,0xD8,0x3C,0xC0,0x14,0x80,0x0F,0xDD,0xCF,0xDD,0xC0,0x09,0x01,0x00,0x3F,
++    0xD0,0x14,0x18,0x01,0xF0,0x9A,0xD6,0x0C,0xD0,0xD0,0x94,0x95,0x68,0x01,0x88,0x2E,
++    0x50,0xC1,0xE8,0xBE,0xC5,0x13,0x18,0x12,0x80,0x13,0x00,0x9F,0x50,0x99,0xE8,0x2E,
++    0xC0,0x13,0x50,0x01,0x82,0x16,0xF0,0x90,0x80,0x13,0x00,0x5F,0x68,0x29,0x88,0x4E,
++    0x58,0xE1,0xEE,0x3E,0xC0,0x13,0x50,0x01,0x88,0x26,0xD0,0x1C,0x50,0x01,0x88,0x0E,
++    0x10,0x09,0x90,0x1C,0xD4,0x14,0xE0,0x90,0x92,0x14,0xE0,0x00,0xE6,0x48,0x92,0x4D,
++    0x16,0x8A,0x9D,0xAE,0x40,0x20,0x6B,0x21,0xC8,0x0E,0xD5,0x44,0x90,0x04,0x08,0x01,
++    0x00,0x19,0xD8,0x3C,0xD0,0x2C,0x80,0x07,0xD0,0xE7,0x0D,0x09,0x30,0x42,0xD8,0x44,
++    0xD0,0x34,0x80,0x07,0xD0,0x07,0xC3,0x1C,0x87,0x4D,0xE8,0x85,0xAC,0xFD,0x87,0x1D,
++    0xF0,0x64,0x30,0x7A,0x37,0xEA,0xD0,0xC3,0x86,0x14,0x08,0x09,0xC4,0x1C,0x00,0x48,
++    0xC5,0x20,0x42,0xB2,0xC0,0x03,0x40,0x09,0x8D,0x0E,0xD8,0xC3,0x80,0x14,0x08,0x01,
++    0x00,0x09,0xD8,0x2C,0xD0,0x6C,0x80,0x07,0xD0,0x37,0xD2,0x2C,0x91,0x04,0x30,0xDA,
++    0x00,0x11,0xD0,0x1C,0xC8,0x6C,0x80,0x07,0xD0,0xA7,0xD4,0x2C,0x92,0x04,0x00,0x29,
++    0xEC,0x0A,0x06,0x01,0x19,0x0A,0x30,0xDA,0x11,0x01,0x30,0x02,0x82,0x0F,0xD8,0x77,
++    0xD0,0x2C,0x90,0x04,0x30,0xDA,0x09,0x01,0x00,0x19,0xD0,0x1C,0x84,0x07,0xD0,0x0F,
++    0x08,0x09,0x30,0x42,0xD8,0x2C,0xD0,0x6C,0x81,0x07,0xD0,0x2F,0x41,0x02,0x05,0x44,
++    0x01,0x01,0x00,0x84,0x08,0x01,0x00,0x77,0x01,0x01,0xF0,0x02,0x15,0x01,0xF0,0x52,
++    0x10,0x12,0xEC,0x06,0x00,0x44,0x11,0x01,0xF4,0x92,0x15,0x12,0xD1,0x06,0x00,0x84,
++    0xE2,0x20,0xE5,0x48,0x90,0x4D,0xC6,0x14,0x17,0x0A,0x9C,0x6E,0x87,0x3D,0xE8,0x85,
++    0xAC,0xBD,0x87,0x45,0xC2,0x4C,0xD8,0x03,0x80,0x1C,0xC8,0x4C,0xD0,0x4B,0x8E,0x14,
++    0x50,0x6A,0xCC,0x44,0xC0,0x48,0x8C,0x3C,0x48,0x62,0xC4,0x4B,0x48,0x09,0x88,0x46,
++    0xCA,0x1C,0xE0,0x48,0x90,0x4D,0x8E,0x1C,0x80,0x34,0xC0,0x4C,0xD8,0x03,0x84,0x14,
++    0x00,0x0F,0x00,0x01,0x80,0x34,0xF8,0x34,0x04,0x3F,0x4B,0x32,0x04,0x01,0x00,0x43,
++    0xC0,0x4C,0xC8,0x3C,0xD3,0x03,0x1E,0xC2,0xC0,0x08,0x02,0x01,0x10,0xF9,0x01,0x1F,
++    0x82,0x53,0xE0,0x48,0xE6,0x00,0x92,0x05,0xDC,0x14,0x10,0xC2,0x9C,0xC6,0x27,0x01,
++    0x31,0x2A,0x31,0x32,0x03,0xC7,0x40,0xE2,0x08,0x23,0x4E,0x25,0xB8,0x0C,0x88,0x04,
++    0x40,0x45,0x40,0x3E,0x5F,0x2D,0xB8,0xFF,0xFB,0x8F,0x33,0x5A,0x00,0xA1,0xF0,0xC2,
++    0x40,0xE1,0xD1,0x1E,0x68,0x41,0x80,0x4E,0x18,0x62,0x05,0x1F,0x70,0x01,0x8C,0x0E,
++    0x30,0x72,0x01,0x1F,0x41,0x68,0x1B,0x62,0x6F,0x01,0x88,0x26,0xC0,0x4C,0xC8,0x3C,
++    0xD3,0x03,0x1E,0xC2,0xC0,0x08,0x02,0x01,0x10,0x01,0x00,0x1F,0x82,0x53,0xE0,0x48,
++    0xE6,0x00,0x92,0x05,0xDC,0x14,0x10,0xC2,0x99,0xC6,0x37,0xAA,0x20,0x01,0x00,0x0F,
++    0x1B,0xA2,0x41,0xB0,0x77,0x01,0x88,0xDE,0xC6,0x4C,0x58,0x04,0xC0,0x41,0x91,0x35,
++    0x05,0x8F,0x18,0x62,0x46,0x02,0x0B,0x23,0x48,0x25,0xB8,0x0C,0x88,0x04,0x40,0x45,
++    0x40,0x3E,0x58,0x2D,0xB9,0xFF,0xFF,0xD7,0x30,0x5A,0x03,0x81,0xF5,0xC2,0x10,0x82,
++    0xE9,0x06,0x18,0x62,0x40,0x68,0x6B,0x01,0x88,0x5E,0xC7,0x44,0x0E,0xE9,0xC9,0x00,
++    0x0A,0x48,0xC2,0x00,0xAB,0x23,0xE0,0xF8,0x90,0xFD,0xC7,0x1C,0x14,0x3A,0x9C,0xA6,
++    0xF1,0x34,0x00,0x9F,0xC1,0x44,0x08,0xE9,0xCA,0x00,0x0C,0x48,0xC1,0x38,0xEA,0xC3,
++    0x40,0x01,0x88,0x0E,0x01,0x09,0xA8,0xC3,0xE8,0xE3,0x29,0x01,0x01,0x01,0x00,0x07,
++    0xE7,0x68,0x93,0x6D,0x40,0x09,0x88,0x1E,0x60,0xF9,0x97,0x0E,0xE5,0x20,0x93,0x25,
++    0x48,0x22,0x02,0x01,0x00,0x43,0xAC,0x48,0x46,0x1A,0x0A,0x23,0x20,0x00,0x67,0x10,
++    0x02,0x07,0x40,0x48,0x30,0x82,0x10,0x42,0x81,0xDE,0x4F,0x01,0xC9,0x06,0x08,0x01,
++    0x88,0x04,0x90,0x0C,0x40,0x45,0x40,0x6E,0x37,0x8A,0xB9,0xFF,0xF0,0x0F,0x43,0x01,
++    0x80,0x0E,0x68,0x29,0x99,0xE6,0xAE,0xE3,0xE7,0xB0,0x93,0xB5,0xC4,0x1C,0x10,0x32,
++    0x98,0x46,0x86,0x5D,0xEF,0x85,0xAF,0xBD,0x80,0x15,0x34,0x62,0x31,0xB2,0x48,0x7A,
++    0x00,0x01,0x80,0x43,0x40,0x8A,0x41,0x0B,0x10,0x11,0x18,0x8A,0x00,0x0B,0x28,0x01,
++    0x00,0x3F,0x08,0x09,0x31,0x9A,0x31,0x52,0x30,0x42,0x80,0x07,0xCB,0xA7,0xE1,0x68,
++    0x95,0x6D,0xD7,0x03,0x17,0x42,0xC5,0xA6,0x31,0x12,0x31,0x8A,0x00,0x11,0x80,0x07,
++    0xC1,0x7F,0x34,0x92,0x30,0x0A,0xC1,0x14,0xB8,0xFF,0xFF,0xD7,0x31,0x12,0x31,0x8A,
++    0x00,0x01,0x80,0x07,0xC5,0x2F,0xDC,0x03,0x41,0x01,0x80,0x46,0x6F,0xF2,0x40,0x43,
++    0x91,0x3D,0x4C,0x04,0x00,0x43,0x47,0xCA,0x08,0x09,0x80,0x0B,0x31,0x12,0x31,0x8A,
++    0x00,0x11,0x80,0x07,0xC1,0xAF,0x33,0x1A,0xB0,0x04,0x08,0x01,0x00,0x09,0xD0,0x14,
++    0x82,0x07,0xC8,0xFF,0xB3,0x04,0xD8,0x0B,0x30,0x1A,0x01,0x11,0xD0,0x14,0x80,0x07,
++    0xC9,0xC7,0x32,0x92,0x30,0x0A,0xC1,0x14,0xBF,0xFF,0xF7,0x97,0x31,0x12,0x31,0x8A,
++    0x00,0x01,0x80,0x07,0xC0,0xEF,0x42,0x4A,0x08,0x01,0x80,0x0B,0x01,0x7B,0x37,0x1A,
++    0xB0,0x04,0x08,0x01,0x00,0x11,0xD0,0x14,0x82,0x07,0xC8,0x1F,0x31,0x12,0x31,0x8A,
++    0x00,0x11,0x80,0x07,0xC0,0x6F,0x02,0x5F,0x30,0x20,0x06,0x00,0x00,0xB0,0x00,0x01,
++    0xF8,0xFB,0x07,0x00,0x10,0x00,0x00,0x42,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,
++    0x50,0x1A,0x40,0x83,0x0C,0x11,0x18,0x42,0x00,0x83,0x80,0x2D,0xE8,0x85,0x07,0x00,
++    0x18,0x00,0x04,0x42,0xA8,0x85,0x31,0x12,0x90,0x01,0xE6,0x9B,0x32,0xD8,0x72,0xD8,
++    0xA7,0x9B,0x58,0xCA,0x41,0xE3,0x30,0x20,0xA2,0x16,0x40,0xE3,0x3F,0x20,0xAB,0xE6,
++    0x58,0xB2,0x27,0x41,0x00,0xE3,0x44,0xE3,0x28,0xF9,0xAF,0x19,0x18,0x62,0x01,0xE3,
++    0x20,0x81,0x48,0x01,0x83,0x76,0x00,0xE9,0x08,0x00,0xE4,0x8B,0x48,0x48,0x8E,0x1E,
++    0xF0,0x00,0x22,0x00,0x67,0x00,0x88,0xC6,0x40,0x01,0x88,0x16,0x41,0xC3,0x18,0x02,
++    0x01,0xC3,0xE8,0x85,0x80,0x01,0xE5,0x8B,0x48,0x48,0x8E,0x16,0xE8,0x0B,0x4E,0x31,
++    0x8E,0xCE,0xEF,0x03,0x47,0x31,0x88,0xA6,0x41,0xC3,0x18,0x02,0x01,0xC3,0xE8,0x85,
++    0xAA,0x85,0x47,0x63,0x46,0x5B,0xD6,0xAB,0x71,0x0A,0xC7,0xB3,0x70,0x09,0x88,0x16,
++    0x4A,0x63,0x56,0x5B,0xD8,0xAB,0x44,0x01,0x88,0x0E,0x11,0x01,0x01,0xE7,0x40,0x03,
++    0x30,0x32,0xB0,0x41,0x30,0xA2,0xED,0x08,0x32,0x42,0xC0,0x01,0x58,0x33,0xC4,0xFB,
++    0x1C,0xF2,0x19,0x33,0x58,0x33,0xC6,0xFB,0x1E,0xF2,0x1D,0x33,0x31,0x32,0x43,0x83,
++    0xC5,0xF3,0x18,0x82,0x31,0x32,0x03,0x83,0x40,0x73,0xC0,0xC3,0x18,0x32,0x04,0x73,
++    0xEA,0x20,0xE1,0xD8,0xE6,0x90,0x92,0x95,0x17,0x52,0x9D,0x06,0xE8,0x85,0x47,0x09,
++    0x88,0x0E,0x11,0x01,0x01,0xE7,0x40,0x03,0x30,0x32,0xB0,0x41,0x30,0xA2,0xED,0x08,
++    0x32,0x42,0xC0,0x01,0x58,0x33,0xC4,0xFB,0x1C,0xF2,0x1D,0x33,0x58,0x33,0xC6,0xFB,
++    0x1E,0xF2,0x1D,0x33,0x31,0x32,0x43,0x83,0xC5,0xF3,0x18,0x82,0x31,0x32,0x03,0x83,
++    0x40,0x73,0xC0,0xC3,0x18,0x32,0x00,0x73,0xEA,0x20,0xE1,0xD8,0xE6,0x90,0x92,0x95,
++    0x17,0x52,0x9D,0x06,0xE8,0x85,0x47,0x11,0x88,0x0E,0x11,0x01,0x01,0xE7,0x40,0x03,
++    0x30,0x32,0xB0,0x41,0x30,0xA2,0xED,0x08,0x32,0x42,0xC0,0x01,0x58,0x33,0xC4,0xFB,
++    0x1C,0xF2,0x1D,0x33,0x58,0x33,0xC6,0xFB,0x1E,0xF2,0x1D,0x33,0x31,0x32,0x43,0x83,
++    0xC1,0xF3,0x18,0x82,0x31,0x32,0x03,0x83,0x40,0x73,0xC0,0xC3,0x18,0x32,0x04,0x73,
++    0xEA,0x20,0xE1,0xD8,0xE6,0x90,0x92,0x95,0x17,0x52,0x9D,0x06,0xE8,0x85,0x47,0x19,
++    0x88,0xE6,0x17,0x01,0x01,0xE7,0x40,0x03,0x30,0x32,0xB0,0x41,0x30,0xA2,0xED,0x08,
++    0x32,0x42,0xC0,0x01,0x58,0x33,0xC4,0xFB,0x1C,0xF2,0x1D,0x33,0x58,0x33,0xC6,0xFB,
++    0x1E,0xF2,0x1D,0x33,0x31,0x32,0x43,0x83,0xC1,0xF3,0x18,0x82,0x31,0x32,0x03,0x83,
++    0x40,0x73,0xC0,0xC3,0x18,0x32,0x00,0x73,0xEA,0x20,0xE1,0xD8,0xE6,0x90,0x92,0x95,
++    0x17,0x52,0x9D,0x06,0xEF,0x85,0xAF,0x85,0x44,0xE3,0x02,0xB0,0xCE,0x20,0x45,0xEB,
++    0xC0,0x68,0x45,0x09,0x88,0x26,0x40,0xE3,0xCC,0x20,0x45,0xDB,0xC0,0xE8,0x04,0x3F,
++    0x79,0x7A,0xC4,0xFB,0x78,0x09,0x88,0x1E,0x4D,0xE3,0xCE,0x20,0x54,0xDB,0xC2,0xE8,
++    0x40,0x13,0xF9,0xA0,0xC0,0x5B,0x41,0x09,0x88,0x76,0x48,0x01,0x8A,0x66,0x40,0x83,
++    0x1A,0xC2,0x04,0x83,0x44,0x83,0x1C,0xC2,0x01,0x83,0x44,0x03,0x19,0xC2,0x04,0x03,
++    0x40,0x83,0x18,0xC2,0x07,0x83,0xE8,0x85,0x48,0x09,0x88,0x66,0x44,0x83,0x1A,0xC2,
++    0x04,0x83,0x42,0x83,0x1C,0xC2,0x04,0x83,0x44,0x83,0x18,0xC2,0x01,0x83,0x40,0x03,
++    0x19,0xC2,0x00,0x03,0xE8,0x85,0x4F,0x11,0x89,0x66,0x40,0x03,0x19,0xC2,0x04,0x03,
++    0x44,0x83,0x18,0xC2,0x02,0x83,0x40,0x83,0x1A,0xC2,0x00,0x83,0x44,0x83,0x1C,0xC2,
++    0x07,0x83,0xEC,0x85,0x4F,0x19,0x88,0xE6,0x44,0x03,0x19,0xC2,0x00,0x03,0x41,0x83,
++    0x18,0xC2,0x04,0x83,0x44,0x83,0x1A,0xC2,0x04,0x83,0x42,0x83,0x1C,0xC2,0x00,0x83,
++    0xEF,0x85,0xAF,0xFD,0xF4,0x4C,0x30,0x62,0x29,0x01,0x48,0x93,0x4C,0x8B,0x35,0x72,
++    0xD1,0xE3,0x36,0x3A,0x48,0x32,0xC3,0x4B,0x48,0x09,0x88,0x0E,0x54,0x93,0xD9,0xE3,
++    0x41,0x19,0x80,0x96,0x33,0x79,0x48,0x0A,0x10,0xB0,0x41,0x11,0x8B,0xB6,0x30,0x02,
++    0x1B,0x3A,0x5A,0x02,0xC6,0x14,0xC0,0x00,0xC3,0xC0,0x31,0x9A,0x32,0x2A,0xEB,0xDA,
++    0x08,0x5B,0x0A,0x01,0x00,0x3F,0xC0,0x1B,0x18,0x9A,0x41,0xAB,0x00,0x5B,0xE9,0x90,
++    0xE2,0x00,0xE2,0x48,0x95,0x4D,0x16,0x0A,0x9F,0xAE,0xEF,0xFD,0x40,0x01,0x88,0x8E,
++    0x1E,0x01,0x10,0x5B,0x40,0x82,0x42,0x33,0x45,0xB0,0x05,0xB0,0x02,0x33,0x00,0x1B,
++    0x00,0x5B,0x40,0x0B,0x1C,0x81,0x18,0xCA,0x00,0x0B,0x40,0x0B,0x18,0x01,0x1C,0xCA,
++    0x00,0x0B,0x00,0x17,0x40,0x09,0x88,0x06,0x30,0xAA,0x01,0x01,0x00,0x27,0x40,0x8B,
++    0x00,0x6B,0xE8,0x90,0xE6,0x00,0x92,0x05,0x17,0x02,0x9D,0xC6,0xEF,0xFD,0xAF,0x85,
++    0x30,0x72,0xCC,0x2C,0xD5,0x63,0x36,0x22,0x46,0xEB,0x42,0xE3,0x40,0x01,0x88,0x1E,
++    0xDC,0x43,0x32,0x22,0x44,0xEB,0x40,0xE3,0x51,0x19,0x88,0x16,0x00,0x01,0x00,0xEF,
++    0x3E,0x10,0x7E,0x90,0x28,0x92,0x8B,0xAE,0x40,0x53,0x31,0xB2,0xB0,0x41,0xE8,0x98,
++    0x32,0xD2,0xD0,0x01,0x59,0xBB,0xC4,0x0B,0x1C,0x7A,0x1C,0xBB,0x59,0xBB,0xC6,0x0B,
++    0x1E,0x7A,0x1C,0xBB,0x41,0x93,0xC1,0x3B,0x19,0xD2,0x01,0x93,0x41,0xCB,0xC0,0x13,
++    0x18,0x8A,0x00,0xCB,0xEB,0x68,0xE1,0x20,0xE6,0x00,0x92,0x05,0x2E,0x02,0x9B,0xFE,
++    0xE8,0x85,0x57,0x29,0x88,0xE6,0x07,0x01,0x06,0xEF,0x38,0x10,0x7B,0x90,0x2E,0x92,
++    0x89,0xAE,0x40,0x53,0x30,0xB2,0xB0,0x41,0xE8,0x98,0x30,0xD2,0xD4,0x01,0x5A,0xBB,
++    0xC0,0x0B,0x19,0x7A,0x1E,0xBB,0x5C,0xBB,0xC4,0x0B,0x19,0x7A,0x19,0xBB,0x46,0x93,
++    0xC5,0x3B,0x19,0xD2,0x00,0x93,0x41,0xCB,0xC4,0x13,0x19,0x8A,0x01,0xCB,0xE8,0x68,
++    0xE2,0x20,0xE3,0x00,0x93,0x05,0x2E,0x02,0x9F,0xFE,0xEE,0x85,0xA8,0x85,0xF7,0x2C,
++    0x37,0x22,0xD4,0xAB,0xC4,0x34,0x00,0xB8,0x4E,0x03,0xC8,0x20,0x44,0xB2,0xC0,0xD8,
++    0xC3,0xC0,0x30,0x1A,0x58,0x01,0x88,0x1E,0xD8,0xAB,0xDB,0x34,0x4E,0xDB,0xCA,0xE0,
++    0x48,0x11,0x88,0xA6,0xB5,0x01,0xE4,0x8B,0x48,0x01,0x80,0x16,0x18,0x69,0x10,0xD8,
++    0x00,0x57,0x18,0x79,0x10,0xD8,0x00,0x3F,0xC0,0x0B,0x18,0xCA,0x41,0x33,0x01,0x8B,
++    0xA4,0x41,0xE0,0x00,0xE6,0x90,0x94,0x95,0x17,0x52,0x9D,0xAE,0xE8,0x85,0x4F,0x19,
++    0x8F,0xE6,0x07,0xF9,0x18,0x02,0x06,0x77,0x18,0x00,0x04,0x42,0x00,0x01,0x00,0x42,
++    0x00,0xB0,0x00,0x01,0x30,0x20,0x06,0x00,0x40,0x60,0x02,0x00,0x40,0x0B,0x01,0x43,
++    0xA4,0x41,0xE0,0x90,0x95,0x95,0x16,0x52,0x9F,0xC6,0xEF,0x85,0xAC,0xFD,0x87,0x25,
++    0x30,0x6A,0x30,0xB2,0x31,0xE2,0x48,0x3B,0x06,0xC9,0x07,0x00,0xC0,0x40,0x81,0x1C,
++    0xD0,0x83,0x87,0x14,0xC0,0x24,0x40,0x01,0x8B,0x16,0xD8,0x83,0x83,0x14,0x48,0x3B,
++    0x30,0x1A,0x11,0x19,0x08,0x01,0xB0,0x04,0xC7,0x24,0xB8,0xFF,0xF9,0x87,0x32,0x1A,
++    0x10,0x19,0x08,0x09,0xB0,0x04,0xC0,0x24,0xBA,0xFF,0xFF,0x4F,0x30,0x5A,0x11,0x01,
++    0x08,0x11,0xB0,0x04,0xA0,0x0C,0xC0,0x24,0xBC,0xFF,0xFF,0xC7,0x30,0x5A,0x11,0x09,
++    0x08,0x11,0xB0,0x04,0xA0,0x0C,0xC0,0x24,0xBC,0xFF,0xFF,0x87,0x36,0x82,0x81,0x01,
++    0xE2,0x0B,0x30,0x48,0x70,0x48,0xA2,0x0B,0x57,0xFA,0x0F,0xC1,0x00,0x8B,0x44,0x8B,
++    0x18,0xF9,0x9F,0x19,0x18,0xCA,0x00,0x8B,0x35,0x8A,0x89,0x01,0x01,0x07,0xF8,0x85,
++    0xE6,0x1B,0x48,0xD8,0x8E,0x16,0xE8,0x5B,0x5F,0x31,0x88,0xC6,0xE8,0x43,0x46,0x31,
++    0x88,0x1E,0x40,0x83,0x08,0x81,0x18,0x42,0x00,0x83,0x00,0x01,0x04,0x3F,0x00,0x08,
++    0xC2,0xCA,0x43,0x4B,0xDA,0x1C,0x00,0x10,0x92,0xCA,0xE4,0x00,0x90,0x05,0xCE,0x14,
++    0x17,0x42,0x9C,0xA6,0x30,0x5A,0x11,0x01,0x08,0x19,0xB0,0x04,0xA0,0x0C,0xC0,0x24,
++    0xBA,0xFF,0xFF,0xE7,0x30,0x5A,0x11,0x09,0x08,0x19,0xB0,0x04,0xA0,0x0C,0xC0,0x24,
++    0xBA,0xFF,0xFF,0xA7,0x30,0x1A,0x11,0x29,0x08,0x09,0xB0,0x04,0xC7,0x24,0xB8,0xFF,
++    0xF1,0xB7,0x37,0x1A,0x10,0x29,0x08,0x01,0xB0,0x04,0xC0,0x24,0xBF,0xFF,0xF7,0x7F,
++    0x87,0x45,0xE8,0x85,0xAC,0xFD,0x87,0x35,0x08,0xC9,0xC7,0x3C,0x02,0x48,0xC6,0x28,
++    0x48,0xD2,0xC6,0x3C,0xC0,0x20,0xC2,0x44,0xD0,0x33,0xC6,0x34,0x40,0x01,0x88,0x0E,
++    0xC2,0x44,0xD8,0x33,0xC4,0x44,0x80,0x01,0x86,0x2C,0xE0,0x03,0x43,0x01,0x88,0xE6,
++    0x08,0xF9,0x01,0x17,0xA2,0x0A,0xE1,0x00,0x95,0x05,0x14,0x82,0x9C,0xD6,0x3F,0x01,
++    0xB8,0x24,0xB8,0x14,0x06,0x57,0x49,0x62,0xC6,0x24,0x08,0x43,0x40,0x35,0x40,0x7E,
++    0xBA,0xFF,0xFF,0xE7,0x48,0x52,0x1E,0x01,0x00,0x01,0x00,0x67,0x04,0x10,0x32,0xA2,
++    0xF4,0x52,0x15,0xD2,0xEB,0x0E,0x30,0x1A,0xD4,0x5A,0x17,0x52,0xD3,0x0E,0x30,0x0A,
++    0xD2,0x4A,0xE3,0x00,0x95,0x05,0x14,0x82,0x9A,0x86,0x4F,0x81,0x90,0x2E,0x78,0x41,
++    0x80,0x76,0xC0,0x24,0x18,0xC2,0x85,0x24,0x00,0x27,0xC0,0x14,0x40,0x01,0x8C,0x0E,
++    0xB8,0x14,0x00,0x2F,0x40,0xF8,0xC3,0x24,0x18,0xC2,0x81,0x24,0x7E,0x01,0x88,0x96,
++    0x00,0x01,0x08,0x01,0x01,0x17,0xA0,0x0A,0xE4,0x00,0x92,0x05,0x17,0x82,0x9D,0xD6,
++    0xC0,0x14,0x80,0x1C,0x38,0x01,0x00,0x27,0xC0,0x14,0x18,0x3A,0xC2,0x14,0x40,0x00,
++    0x80,0x14,0xC0,0x14,0x47,0x01,0x88,0xBE,0xC6,0x2C,0x58,0x04,0xC0,0x41,0x91,0x05,
++    0x81,0x0C,0x00,0x17,0xC4,0x1C,0x18,0x3A,0x46,0x3A,0x0D,0x3B,0x40,0x35,0x40,0x7E,
++    0xB8,0xFF,0xFF,0xA7,0x58,0x32,0x0D,0x01,0x00,0x01,0x00,0x67,0x04,0x10,0x32,0xA2,
++    0xF4,0x52,0x15,0x52,0xEB,0x0E,0x30,0x0A,0xD4,0x4A,0x13,0xD2,0xD3,0x0E,0x30,0x12,
++    0xD2,0x5A,0xE5,0x00,0x95,0x05,0x14,0x82,0x98,0x86,0xC7,0x0C,0x10,0x0A,0xEC,0x0E,
++    0xC0,0x1C,0x18,0x3A,0xC2,0x1C,0x40,0x00,0x80,0x1C,0xC0,0x1C,0x46,0x01,0x88,0xCE,
++    0x78,0x01,0x88,0x06,0x38,0x09,0xC0,0x2C,0xA0,0x3B,0xC6,0x2C,0xE4,0x0B,0x46,0x92,
++    0x08,0x0B,0xC6,0x2C,0xE0,0x03,0x3E,0x09,0x16,0xF8,0x07,0x00,0x80,0x24,0x00,0x07,
++    0x40,0xF8,0xC3,0x24,0x17,0xC2,0x81,0xDE,0x78,0x01,0xC9,0x06,0x38,0x01,0x01,0x01,
++    0x08,0x01,0x00,0x17,0xA2,0x0A,0xE1,0x00,0x95,0x05,0x14,0x82,0x98,0xD6,0x07,0x01,
++    0x80,0x04,0x78,0x01,0x88,0x1E,0xC0,0x04,0xE6,0x00,0x92,0x05,0x80,0x04,0x00,0x01,
++    0x01,0x57,0xE0,0x0A,0x1E,0xCA,0x91,0x4D,0xA0,0x0A,0xD1,0x24,0x10,0x8A,0xCC,0x0E,
++    0x19,0xCA,0xA5,0x0A,0xE4,0x00,0x92,0x05,0x17,0x82,0x9D,0x96,0x40,0x35,0x40,0x7E,
++    0xBD,0xFF,0xF7,0xE7,0x01,0x01,0x00,0x0F,0xD2,0x2C,0x00,0x08,0xD6,0x4A,0x5B,0x94,
++    0xD0,0x48,0x94,0x4D,0xD0,0x04,0x50,0x01,0x8B,0x2E,0x48,0x21,0xE9,0xA6,0xE0,0x0A,
++    0x19,0xCA,0xA5,0x0A,0x01,0x87,0x48,0x91,0xE9,0x2E,0xE0,0x12,0x50,0x01,0x80,0x16,
++    0xF1,0x90,0xA2,0x12,0x01,0x47,0x10,0x89,0x1C,0x92,0x16,0x8A,0xD1,0x26,0xE0,0x0A,
++    0x48,0xF9,0x91,0x0E,0xE1,0x48,0xA2,0x0A,0xE4,0x00,0x92,0x05,0x16,0x82,0x9D,0xDE,
++    0x40,0xF8,0xC3,0x04,0x45,0x21,0xC8,0xE6,0x87,0x55,0xE8,0x85,0xAC,0xBD,0x87,0x75,
++    0xCE,0x84,0xD0,0x6B,0x10,0xC9,0xCF,0x7C,0x04,0x90,0xC6,0x48,0x18,0xF9,0xD1,0x7C,
++    0x0E,0xD8,0xC2,0x90,0x20,0xF9,0xDF,0x7C,0x00,0x20,0xCF,0xE0,0x30,0x09,0xDC,0x7C,
++    0x0C,0xB0,0xC9,0xD8,0x99,0x14,0x30,0x09,0xDD,0x7C,0x08,0xB0,0xC8,0xD8,0x9C,0x0C,
++    0x78,0x1D,0x40,0x01,0x88,0x0E,0xC0,0x84,0xD8,0x2B,0xC2,0x84,0xE0,0x03,0x44,0x29,
++    0xC0,0x56,0x00,0x01,0x02,0x37,0x00,0x18,0xD6,0x72,0x96,0xB2,0xD7,0x72,0x96,0x32,
++    0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0xB6,0x04,0x01,0x30,0x22,0x18,0x01,0x00,0xCF,
++    0x01,0xC0,0xD2,0x32,0x30,0x32,0xB4,0x6C,0x30,0x01,0x00,0x01,0xF8,0xB2,0xF4,0x42,
++    0xC3,0xB0,0x81,0xB0,0x31,0x82,0x93,0x32,0x40,0x74,0x00,0xB4,0xD0,0x02,0xF1,0x6C,
++    0xD9,0x00,0x04,0xC4,0x20,0x02,0x93,0x05,0x34,0x22,0xE4,0x90,0xE5,0x48,0xE4,0xF8,
++    0xE6,0xD8,0x92,0xDD,0x17,0x5A,0x9D,0x1E,0x71,0x1D,0x30,0x4A,0x30,0x02,0x83,0x0F,
++    0xD8,0x5F,0x95,0x0D,0x10,0x01,0x00,0xCF,0x01,0x01,0xF0,0x82,0xE0,0xB0,0x45,0x01,
++    0xE8,0x2E,0x48,0x01,0xEC,0x1E,0x10,0x42,0xE8,0x56,0x30,0x42,0x00,0x47,0x40,0x01,
++    0xD0,0x2E,0x48,0x01,0xD4,0x1E,0x10,0x42,0xD0,0x16,0x30,0x42,0x00,0x07,0x00,0x01,
++    0x07,0x98,0xD2,0x3A,0xD7,0xC0,0x91,0x02,0xE6,0x90,0x92,0x95,0x17,0x52,0x9D,0x1E,
++    0xC4,0x84,0xE0,0x03,0x40,0x29,0xC0,0xEE,0x00,0x01,0x10,0x01,0x02,0x3F,0x00,0x08,
++    0xF3,0x14,0xD0,0x1A,0x90,0x9A,0xCB,0x0C,0xA2,0x52,0xE0,0x00,0x95,0x05,0x16,0x42,
++    0x98,0xAE,0x07,0x01,0x12,0xF9,0x09,0x90,0x1A,0x09,0x0A,0xD8,0x00,0x47,0xE0,0x7C,
++    0x00,0x08,0xCA,0x48,0xC1,0x60,0x5C,0x24,0xC0,0x48,0x0E,0x64,0xE6,0x00,0x92,0x05,
++    0x17,0x42,0x9D,0xA6,0x87,0x8D,0xE8,0x85,0xAE,0xE5,0xD7,0x9B,0x9F,0x0C,0x18,0xF9,
++    0x06,0xD8,0xC6,0x58,0x34,0xF2,0x1C,0x09,0x0E,0xD8,0xC0,0x68,0x1C,0x09,0x09,0xD8,
++    0xC4,0x58,0x36,0xE2,0x1E,0xC9,0x07,0xD8,0xC0,0x48,0x8E,0x04,0x40,0x01,0x88,0x0E,
++    0xD8,0x83,0x82,0x0C,0x00,0x01,0x30,0x9A,0x9A,0x01,0x14,0xC3,0x11,0xC3,0x04,0xCF,
++    0x03,0x20,0x32,0x8A,0xD9,0x4A,0xD8,0x72,0xD8,0x48,0x94,0x75,0xC8,0x04,0x98,0x72,
++    0x08,0x01,0x38,0xB1,0xBD,0xFA,0x16,0xBA,0xE8,0x66,0x08,0x09,0x3A,0x09,0x50,0xF3,
++    0x01,0x3A,0x1C,0xF2,0x10,0xF3,0x02,0x77,0x00,0x01,0x00,0x42,0x40,0x60,0x02,0x00,
++    0xF8,0xFF,0x07,0x00,0xED,0xFB,0x16,0xBA,0xD0,0x2E,0x08,0x09,0x3C,0x09,0x50,0xF3,
++    0x01,0x3A,0x1C,0xF2,0x10,0xF3,0x4C,0x01,0x8D,0x96,0x08,0xC1,0xE0,0x4A,0x4C,0x01,
++    0x89,0x76,0xF8,0x7A,0x13,0xF0,0x31,0x0A,0xE4,0x4A,0xC8,0x70,0x30,0x8A,0xFB,0x4A,
++    0x04,0x48,0xCC,0x70,0x03,0xC8,0xD5,0x88,0x91,0x70,0x98,0x72,0x31,0x22,0xA3,0x0A,
++    0xE6,0x00,0x92,0x05,0xCC,0x0C,0x10,0x42,0x9F,0x16,0xEE,0xE5,0xAC,0xBD,0x87,0x65,
++    0x30,0x62,0x30,0xB2,0x40,0xFA,0x47,0x03,0x90,0x05,0x84,0x5C,0x40,0xF2,0x47,0x0B,
++    0x90,0x4D,0x8C,0x54,0x44,0x0B,0x92,0x4D,0x8E,0x4C,0x40,0x0B,0x90,0x4D,0x8C,0x44,
++    0x4C,0x0B,0x90,0x4D,0x8A,0x3C,0x48,0x0B,0x90,0x4D,0x8C,0x34,0x4C,0x0B,0x94,0x4D,
++    0x8E,0x2C,0x50,0x0B,0x90,0x4D,0x8C,0x24,0x4C,0x0B,0x96,0x4D,0x8A,0x1C,0x58,0x0B,
++    0x90,0x4D,0x8C,0x14,0x5C,0x0B,0x94,0x4D,0x88,0x0C,0x08,0x21,0x0C,0x0B,0x08,0x0B,
++    0xE7,0x0B,0x53,0x72,0x1E,0x8A,0x10,0x0B,0x08,0x01,0xDD,0x4A,0x01,0x0B,0x36,0x2A,
++    0xA9,0x01,0xEC,0x4B,0x1B,0x0B,0xEA,0x4B,0x1F,0x0B,0xE4,0x4B,0x0D,0x0B,0xE6,0x43,
++    0x40,0x01,0x80,0x3E,0x47,0x22,0x4F,0x32,0x00,0x0B,0x0A,0xC9,0x00,0x0B,0x08,0x09,
++    0x08,0x0B,0x02,0x3F,0x4F,0x12,0x47,0x02,0xCA,0xE1,0x00,0x0B,0x08,0x89,0x00,0x0B,
++    0x0A,0x41,0x08,0x0B,0xE0,0x03,0x45,0x09,0x8B,0xB6,0xD8,0x03,0x80,0x04,0x38,0x01,
++    0x00,0x3F,0x08,0x09,0x31,0x9A,0x31,0xD2,0x37,0x42,0xB8,0xFF,0xE3,0x67,0xE0,0xF8,
++    0x90,0xFD,0xC7,0x04,0x17,0x3A,0x9C,0xA6,0x31,0x9A,0x31,0x12,0x00,0x09,0xC8,0x64,
++    0xBD,0xFF,0xEF,0xC7,0xF3,0x43,0xB7,0x03,0x31,0x9A,0x31,0x12,0x00,0x09,0xC8,0x64,
++    0xB9,0xFF,0xEF,0xA7,0x30,0x12,0x01,0x09,0xCF,0x64,0xB8,0xFF,0xF1,0xFF,0x34,0x12,
++    0x00,0x09,0xC8,0x64,0xB9,0xFF,0xFF,0x87,0x48,0x32,0xC6,0x5C,0x06,0x43,0x40,0x32,
++    0xC8,0x54,0x00,0x0B,0xCA,0x4C,0x00,0x0B,0xCE,0x44,0x00,0x0B,0xC8,0x3C,0x08,0x0B,
++    0xCA,0x34,0x08,0x0B,0xCC,0x2C,0x08,0x0B,0xCE,0x24,0x10,0x0B,0xCE,0x1C,0x08,0x0B,
++    0xCA,0x14,0x18,0x0B,0xCC,0x0C,0x18,0x0B,0xE6,0x43,0x31,0x00,0xAB,0x66,0xF1,0x03,
++    0xF4,0x4B,0x15,0x42,0x89,0x46,0x31,0x02,0x82,0x01,0xE1,0x13,0x50,0x11,0x88,0x46,
++    0xE8,0x13,0x51,0x51,0x88,0x16,0x10,0x01,0xA0,0x13,0x02,0x9F,0xE1,0x90,0xAA,0x13,
++    0x05,0x87,0x50,0x53,0x50,0x01,0x88,0x2E,0x50,0x53,0x53,0x01,0x89,0x16,0xE8,0x13,
++    0x50,0x01,0x89,0x2E,0xF3,0x53,0xB7,0x13,0x11,0x09,0xB0,0x13,0xA0,0x13,0x02,0x0F,
++    0xE1,0x90,0xAA,0x13,0xF4,0x03,0x13,0x42,0x88,0x36,0x08,0x01,0x30,0x1A,0xB1,0x04,
++    0x30,0x42,0xD0,0x64,0xBF,0xFF,0xDF,0xEF,0x31,0x12,0x31,0x8A,0x07,0x11,0xB8,0xFF,
++    0xD8,0x3F,0x80,0x7D,0xEF,0x85,0xAF,0x85,0x4E,0xA3,0xD0,0xEB,0x33,0x70,0x72,0xB0,
++    0x4F,0x78,0x0E,0xF8,0x48,0xFA,0xC4,0x4B,0x48,0x09,0x88,0x0E,0x54,0xA3,0xD8,0xEB,
++    0x0F,0x01,0x18,0xF9,0x01,0x6F,0x40,0x13,0x47,0x93,0x02,0x92,0x90,0x95,0x00,0x14,
++    0x78,0x01,0x88,0x16,0x50,0xF9,0xEF,0x06,0x01,0x1C,0xE8,0x20,0xE2,0x00,0xE4,0x48,
++    0x95,0x4D,0x16,0x4A,0x9F,0x7E,0xEF,0x85,0xA8,0xC5,0x33,0x2A,0x34,0xB2,0x60,0x6A,
++    0x44,0x03,0x11,0x01,0x19,0x82,0x04,0x03,0x40,0x03,0x11,0x81,0x19,0x82,0x00,0x03,
++    0x40,0x03,0x11,0x09,0x19,0x82,0x00,0x03,0xE7,0x53,0x03,0xF9,0x80,0x81,0x18,0x12,
++    0x46,0x2A,0x14,0x13,0x13,0x99,0x00,0x13,0x14,0x41,0x00,0x13,0x12,0x91,0xEC,0x92,
++    0x50,0x01,0x80,0x16,0x10,0xC9,0x00,0x13,0x00,0x0F,0x10,0x89,0x00,0x13,0x30,0x52,
++    0x30,0x5A,0x09,0x01,0x00,0x09,0xB0,0x04,0xBD,0xFF,0xDF,0x5F,0x31,0x52,0x31,0x8A,
++    0x07,0x11,0xB8,0xFF,0xD3,0xAF,0x45,0x03,0x3F,0x00,0xAA,0xE6,0xEF,0xC5,0xAB,0x9D,
++    0x80,0x8D,0xCC,0x94,0xC8,0x4B,0x8A,0x84,0xE2,0x94,0xA0,0x01,0xD3,0x1B,0xD1,0x0B,
++    0x88,0x0C,0xC8,0x94,0xD0,0x6B,0x36,0x0A,0x8C,0x61,0x30,0x62,0xC8,0x94,0x30,0x01,
++    0xE0,0x4B,0x4C,0x09,0x88,0x56,0x08,0x01,0x02,0x27,0xC0,0x38,0x9A,0xF3,0xA1,0x32,
++    0xE2,0x48,0x92,0x4D,0xD6,0x94,0xD0,0x93,0x17,0x52,0xE4,0xB6,0x52,0x52,0x03,0xB3,
++    0x06,0xB3,0x04,0xB3,0x0E,0x01,0x18,0x4A,0x00,0x8B,0xC8,0x94,0xD0,0x4B,0xB6,0x8B,
++    0x0B,0x01,0x50,0x2A,0x34,0x01,0x00,0x78,0xC1,0xF8,0x0D,0xF3,0xC2,0x90,0xB2,0xB3,
++    0xE2,0x48,0x92,0x4D,0x4F,0x11,0xD8,0xA6,0xCC,0x94,0xE0,0x4B,0x4B,0x29,0xC8,0xA6,
++    0x00,0x48,0xC5,0x48,0x04,0x50,0xC3,0x70,0x14,0x09,0x06,0x90,0xC0,0xB0,0xB5,0x1C,
++    0xC0,0x48,0x8C,0x14,0x30,0x12,0x33,0x32,0xB0,0xC1,0x08,0x01,0x8A,0x3C,0x48,0xBA,
++    0x88,0x6C,0x88,0x64,0x30,0x32,0x04,0x01,0x32,0x22,0x04,0x27,0xC8,0x1C,0x00,0x01,
++    0xF0,0x42,0xF8,0x14,0x0B,0x01,0xF0,0xCA,0x32,0x7A,0xD0,0x08,0x97,0x4D,0x48,0xF9,
++    0xEF,0x06,0x08,0xF9,0xCB,0x38,0x86,0xF8,0x78,0xF9,0xEF,0x06,0x3B,0xF9,0x37,0x82,
++    0x82,0x3B,0xE0,0x00,0x30,0x32,0xC4,0xBB,0x10,0xFA,0x9C,0x46,0x10,0xCA,0xDC,0x36,
++    0x46,0x84,0xD9,0x48,0xC0,0x00,0x92,0x05,0x04,0x84,0x81,0x08,0x04,0x37,0x10,0xCA,
++    0xDC,0x16,0x00,0x78,0x00,0xBC,0x01,0x0F,0x39,0x01,0x00,0xBC,0x10,0xCA,0xDC,0x0E,
++    0x38,0x09,0xB8,0x3C,0x43,0x78,0x2B,0x3A,0xE8,0x26,0xF8,0x6C,0x10,0x7A,0xEC,0x2E,
++    0x88,0x6C,0x00,0x1F,0xFC,0x64,0x10,0x7A,0xE8,0x06,0x88,0x64,0x82,0x8B,0xE0,0x90,
++    0xE0,0xB0,0xC5,0x1C,0xE0,0x00,0x84,0x1C,0xC4,0x14,0xE0,0x00,0x83,0x14,0x30,0x02,
++    0xE2,0x00,0x92,0x05,0x35,0x22,0x2C,0x62,0xD8,0xC6,0xC5,0x3C,0x40,0x01,0x80,0xA6,
++    0x08,0x01,0x00,0x01,0x80,0x5C,0xC0,0x0C,0xC2,0x00,0x46,0x00,0x80,0x7C,0xC0,0x0C,
++    0x30,0x00,0x72,0x00,0x80,0x74,0x00,0x01,0x30,0x22,0x84,0x34,0x80,0x2C,0x80,0x24,
++    0xF3,0x90,0xF2,0x40,0x94,0x05,0x32,0x32,0x05,0x7F,0x02,0x77,0x32,0x02,0x03,0x00,
++    0x30,0x22,0xC4,0x34,0x00,0x00,0x82,0x34,0xC2,0x2C,0x00,0x00,0x80,0x2C,0xC0,0x24,
++    0x00,0x00,0x82,0x24,0x43,0x40,0x2B,0x82,0xE8,0x26,0xC0,0x83,0xF4,0x6C,0xD8,0x00,
++    0x80,0x83,0x00,0x1F,0xC0,0x83,0xF0,0x64,0xD8,0x00,0x84,0x83,0xC0,0x83,0x70,0x45,
++    0x37,0xBA,0xAB,0x82,0xC4,0x83,0x10,0xC2,0xDA,0xDE,0xE0,0x48,0x90,0x4D,0xF2,0x5C,
++    0xC1,0xB0,0x91,0xB5,0xB3,0x5C,0x30,0x32,0x39,0x09,0x18,0xF2,0x30,0xA2,0xF5,0x7C,
++    0x10,0x82,0xDD,0x76,0xF1,0x34,0x18,0xF2,0xB0,0x34,0xF0,0x0C,0x10,0x82,0xDD,0x46,
++    0xF1,0x2C,0x18,0xF2,0xB0,0x2C,0xF0,0x74,0x10,0x82,0xDD,0x16,0xC1,0x24,0x18,0xC2,
++    0x80,0x24,0x00,0x6F,0x18,0x00,0x04,0x42,0x00,0x01,0x00,0x42,0x10,0x78,0x00,0x00,
++    0x88,0x60,0x05,0x00,0x00,0xB0,0x00,0x01,0x58,0x80,0x04,0x01,0x78,0xF8,0x07,0x00,
++    0xF3,0x90,0x32,0x82,0xF2,0x00,0x92,0x05,0x33,0x32,0x34,0x82,0x45,0x01,0xD0,0x6E,
++    0x42,0xFA,0xB7,0x0B,0xD0,0x50,0xB3,0x13,0x36,0x12,0x1B,0x92,0x03,0x13,0x30,0x12,
++    0x08,0x13,0xD0,0x34,0x00,0x13,0xD2,0x2C,0x00,0x13,0xD4,0x24,0x00,0x13,0x36,0x01,
++    0x00,0xA7,0xC1,0x5C,0x87,0x0F,0xC0,0x07,0x90,0x05,0x80,0x5C,0x4D,0xA2,0x07,0x80,
++    0xC0,0x00,0x4A,0x13,0x40,0x45,0x08,0x01,0x1C,0x01,0x30,0xF2,0x30,0xE2,0x04,0xCF,
++    0x38,0x98,0x86,0x7E,0xC0,0x1B,0xF8,0x5C,0xD8,0xD8,0x96,0xDD,0x58,0x01,0xE8,0x36,
++    0x83,0x1B,0x20,0x9A,0x94,0xDD,0x36,0xF2,0xE2,0x48,0x92,0x4D,0x00,0x27,0x18,0x01,
++    0x80,0x1B,0x00,0x0F,0x18,0x01,0x80,0x1B,0x42,0x90,0xE2,0x00,0x32,0x1A,0xE3,0xD8,
++    0x94,0xDD,0x32,0xE2,0x2F,0x62,0xDD,0x1E,0xE3,0xB0,0x93,0xB5,0x30,0x82,0x83,0x5C,
++    0x45,0xFA,0x06,0x98,0xC0,0xD8,0x08,0xD3,0xCA,0x00,0xB4,0x0B,0x48,0x21,0xD8,0x0E,
++    0x76,0x09,0xD8,0x36,0x06,0x01,0x50,0xD2,0x04,0x08,0xC4,0x58,0xE4,0x08,0x02,0x70,
++    0xC0,0xB0,0x4D,0xEB,0x4D,0xB3,0x19,0xAA,0x08,0xEB,0xC0,0x80,0xF4,0x1B,0xF2,0x2B,
++    0xDA,0xD8,0xB2,0x1B,0x90,0x45,0x42,0x09,0xD8,0x76,0x07,0x09,0x9E,0x03,0x45,0x82,
++    0x0E,0x19,0x40,0x13,0x50,0x01,0x80,0x16,0x05,0x29,0x98,0x0B,0x04,0xF7,0x40,0x13,
++    0x50,0x01,0x80,0x16,0x05,0x21,0x98,0x0B,0x02,0xC7,0x40,0x0B,0x48,0x01,0x80,0x1E,
++    0x00,0x19,0x08,0x11,0x98,0x0B,0x05,0x8F,0x48,0x03,0x40,0x01,0x88,0x26,0xC0,0x94,
++    0x82,0x01,0xF5,0x03,0x40,0x51,0x98,0x0E,0x00,0x11,0x00,0x3F,0xC1,0x94,0x80,0x01,
++    0xD8,0x03,0x44,0x01,0x80,0x0E,0x00,0x11,0x00,0x07,0x00,0x09,0xDC,0x0B,0xE5,0x50,
++    0x9D,0x13,0xD7,0x13,0x38,0x90,0xA2,0x0E,0xF5,0x48,0x9A,0x0B,0xE0,0x0B,0x13,0x29,
++    0x10,0x0A,0x94,0x0E,0xA0,0x13,0x01,0xEF,0x10,0x0A,0xCC,0x46,0x40,0x09,0x88,0x16,
++    0x09,0x81,0xA7,0x0B,0x00,0xB7,0xD0,0x48,0x01,0x52,0xA4,0x13,0x00,0x97,0x40,0x19,
++    0xC8,0x0E,0x08,0x19,0x02,0x07,0x90,0x0D,0xE0,0x13,0x51,0x01,0x82,0x16,0xF0,0x90,
++    0xA0,0x13,0x01,0x3F,0xD2,0x94,0xF0,0x48,0xCA,0x93,0x1C,0x52,0xCA,0x84,0xC0,0x88,
++    0xD0,0x94,0x88,0x8B,0xA0,0x03,0x83,0x9D,0xEF,0x85,0xAF,0xBD,0x80,0x6D,0x34,0x6A,
++    0xD1,0x63,0x37,0x42,0x80,0x01,0x82,0x64,0xC8,0x03,0x86,0x3C,0xC4,0x64,0xD0,0x03,
++    0x30,0x00,0xA8,0x1E,0x02,0x91,0xEC,0x02,0x40,0x01,0x80,0xAE,0xC5,0x6C,0x00,0x08,
++    0xC3,0x40,0x00,0x08,0x12,0x09,0xC6,0x08,0x04,0x90,0xC4,0x48,0xC0,0x10,0x04,0x01,
++    0x18,0x01,0x00,0x2F,0x00,0x5C,0x00,0x9C,0xE4,0x48,0xE4,0x90,0xE2,0x00,0x92,0x05,
++    0x17,0x02,0xDD,0xBE,0x87,0x85,0xE8,0x85,0x00,0xE9,0xC9,0x6C,0x08,0x00,0xC2,0x40,
++    0x70,0x82,0xEC,0x03,0x08,0x83,0xD7,0x7C,0x91,0x04,0x30,0x5A,0x08,0x01,0x00,0x11,
++    0xD7,0x6C,0xB8,0xFF,0xCC,0xB7,0x45,0x5A,0x80,0x01,0x42,0x0B,0x34,0x5A,0x0B,0xCC,
++    0x5E,0x8B,0x09,0xCC,0x58,0x8B,0x13,0xCC,0x5A,0x8B,0x15,0xCC,0x44,0x8B,0x17,0xCC,
++    0x48,0x2A,0x44,0x53,0x17,0xD4,0x4E,0x93,0x18,0xD4,0x10,0x89,0x00,0x93,0x17,0x19,
++    0x18,0x93,0x43,0x53,0x1C,0x11,0x18,0xD2,0x00,0x53,0x40,0x0B,0x18,0xCA,0x00,0x0B,
++    0x35,0x42,0xE1,0x4B,0x80,0x01,0x81,0x5C,0x4A,0x09,0x88,0x66,0x68,0x44,0x81,0x14,
++    0x34,0x8A,0x59,0x43,0x90,0x35,0xB6,0x0C,0x00,0x01,0x80,0x04,0xD6,0x6C,0x08,0x09,
++    0x04,0x00,0x07,0x48,0xC2,0x00,0xC4,0x00,0x83,0x54,0x40,0x92,0x18,0x33,0x0A,0x01,
++    0x37,0x42,0xB9,0xFF,0xC0,0xBF,0xFA,0x54,0xC1,0x64,0x30,0x5A,0xC9,0x0B,0x34,0xC2,
++    0xD7,0x7C,0xB8,0xFF,0xEB,0x07,0x4C,0x6A,0x10,0x01,0x00,0x01,0x02,0x67,0x00,0x18,
++    0x37,0xE2,0xF4,0xDA,0x10,0x5A,0xD4,0x0E,0x33,0x0A,0xD3,0xCA,0x10,0x9A,0xEC,0x0E,
++    0x35,0x12,0xD3,0xD2,0xE2,0x00,0x92,0x05,0x17,0x02,0xDD,0x86,0xC4,0x14,0xE0,0x00,
++    0x10,0x0A,0x9C,0x36,0xC0,0x04,0x40,0x01,0x8B,0x9E,0x40,0x80,0x40,0x08,0xC2,0x70,
++    0x00,0x3F,0xC0,0x14,0xF4,0x00,0x14,0x12,0xE0,0x5E,0x00,0x09,0x83,0x04,0xE0,0xB0,
++    0x90,0xB5,0x77,0x01,0x80,0x16,0xC0,0x0C,0x16,0x32,0x9C,0x36,0x70,0x01,0x88,0x06,
++    0x30,0x09,0xC0,0x5C,0x88,0x33,0xC0,0x5C,0xCA,0x0B,0x40,0x92,0x18,0x0B,0x32,0x01,
++    0x35,0x42,0x81,0x01,0x81,0x4C,0x80,0x01,0x83,0x44,0x00,0x4F,0xC4,0x3C,0x10,0x32,
++    0xD0,0x6E,0xC0,0x44,0xE0,0x03,0xC8,0x44,0x32,0x00,0x72,0x00,0xA2,0x43,0x40,0x4A,
++    0x0C,0x41,0x00,0x0B,0x47,0x0B,0x10,0xF9,0x90,0x21,0x18,0x8A,0x00,0x0B,0xC8,0x6C,
++    0x02,0x00,0xC5,0x08,0x06,0x00,0x13,0x09,0xC4,0x40,0x00,0x90,0xC4,0x00,0xC4,0x48,
++    0x70,0x01,0x88,0x66,0x12,0x01,0x78,0x0A,0x00,0x37,0x18,0x01,0x00,0x1C,0x00,0x7C,
++    0xE4,0x00,0xE4,0x48,0xE2,0x90,0x92,0x95,0x17,0x12,0xDD,0xB6,0x00,0x0F,0xD9,0x6C,
++    0x06,0x10,0xC7,0x90,0x1C,0x09,0x06,0xD8,0xC4,0x90,0x36,0xA2,0x18,0x01,0x00,0x9F,
++    0x30,0x3A,0x13,0x01,0xF0,0xD2,0x3D,0x01,0xFC,0x3A,0x16,0xBA,0xD0,0x06,0x00,0x14,
++    0x3E,0x01,0xF8,0x7A,0x10,0xBA,0xEC,0x06,0x04,0x54,0xE0,0x00,0xE3,0x48,0x34,0x12,
++    0xE4,0x90,0x34,0xA2,0xE2,0xD8,0x92,0xDD,0x17,0x1A,0xDD,0x4E,0xC4,0x3C,0x10,0x32,
++    0x80,0x0E,0xC1,0x44,0xE6,0x03,0x48,0x00,0x88,0x1E,0xC0,0x4C,0xE8,0x03,0x46,0x31,
++    0x88,0xBE,0xC7,0x4C,0xE8,0x03,0x46,0x31,0x89,0x26,0x40,0x12,0x40,0x0B,0x10,0x81,
++    0x18,0x8A,0x00,0x0B,0xCF,0x6C,0x00,0x00,0xC6,0x00,0x0A,0x09,0x02,0x48,0xC4,0x00,
++    0xC9,0x64,0x30,0x5A,0xC8,0x4B,0xD4,0x7C,0xBE,0xFF,0xE7,0xEF,0xE3,0xB0,0x93,0xB5,
++    0xC4,0x3C,0x10,0x32,0xE8,0x96,0x44,0xBA,0x34,0x5A,0x4B,0xCC,0x80,0x01,0x02,0x0B,
++    0x46,0xA2,0x48,0xCC,0x18,0x0B,0x50,0xCC,0x1A,0x0B,0x52,0xCC,0x1C,0x0B,0x54,0xCC,
++    0x00,0x0B,0x4E,0x8A,0x50,0xD4,0x06,0x53,0x5E,0xCC,0x08,0x0B,0x37,0x97,0xAF,0xFD,
++    0x81,0xED,0xE4,0x3C,0x30,0xAA,0x00,0x01,0x80,0x7C,0x80,0x74,0xC6,0x34,0xD1,0x03,
++    0x81,0x6C,0xC0,0x34,0xDA,0x03,0xF2,0x00,0x90,0x05,0x86,0x64,0x00,0x01,0x80,0x5C,
++    0x80,0x54,0x80,0x4C,0xC4,0x34,0xC9,0x03,0x00,0x00,0x82,0xBC,0x08,0xA1,0x05,0x3F,
++    0x58,0x80,0x04,0x01,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0xF8,0xFB,0x07,0x00,
++    0xC2,0x34,0xF1,0x0A,0x80,0x40,0x82,0xB4,0xC1,0x34,0xD9,0x04,0xE7,0x03,0x9C,0xF9,
++    0x98,0x29,0x41,0x09,0x88,0x76,0xC0,0x6C,0x1E,0x42,0xC3,0x08,0xD0,0xEC,0x00,0x01,
++    0x00,0x2F,0x40,0xB4,0x82,0x73,0xE0,0x48,0xE2,0x90,0xE4,0x00,0x90,0x05,0xF2,0x6C,
++    0x17,0x82,0xDD,0xB6,0x00,0x01,0x80,0x9C,0x80,0xA4,0x80,0xAC,0xC4,0xEC,0x30,0x32,
++    0x70,0x1D,0xC8,0x6C,0x32,0x42,0x19,0x42,0x86,0xE4,0xC0,0x00,0x30,0x22,0x84,0xDC,
++    0x40,0xAA,0x47,0x13,0x48,0x1B,0x08,0x01,0x03,0x1F,0x31,0x82,0x30,0x3A,0x43,0x04,
++    0xC6,0xFB,0xD9,0x00,0x91,0x05,0x00,0x84,0x38,0xB8,0x86,0x26,0xFE,0xAC,0xC8,0x00,
++    0x90,0x05,0x80,0xAC,0x06,0x57,0x38,0xF8,0x80,0x26,0xF8,0xA4,0xC8,0x00,0x96,0x05,
++    0x80,0xA4,0x00,0x1F,0xFE,0x9C,0xC8,0x00,0x90,0x05,0x80,0x9C,0xE3,0xB0,0x35,0x82,
++    0xE4,0x00,0x34,0x32,0x32,0x02,0xE3,0x00,0x32,0x22,0x44,0x90,0x42,0xD8,0xE2,0x48,
++    0x90,0x4D,0xC2,0x6C,0x16,0x0A,0xDC,0xC6,0x79,0xFA,0xF6,0xCB,0x48,0x01,0xE8,0x26,
++    0xC0,0xAC,0x80,0x07,0xF0,0x8F,0x94,0x05,0x83,0xAC,0xF0,0xCB,0x48,0x01,0xE8,0x56,
++    0x48,0x09,0x88,0x1E,0xC2,0xA4,0x80,0x00,0x80,0xA4,0x00,0x27,0xC0,0xA4,0x80,0x07,
++    0xF0,0x1F,0x94,0x05,0x85,0xA4,0xF0,0xCB,0x48,0x01,0xE8,0x56,0x48,0x09,0x88,0x1E,
++    0xC2,0x9C,0x80,0x00,0x80,0x9C,0x00,0x27,0xC0,0x9C,0x80,0x07,0xF0,0xAF,0x93,0x05,
++    0x80,0x9C,0xF0,0xEC,0x40,0x1D,0x80,0x04,0xC0,0xDC,0x80,0x14,0x40,0xC3,0x81,0x94,
++    0x48,0xC3,0x81,0x8C,0xC2,0x34,0x81,0x01,0x84,0xD4,0xD0,0x03,0x38,0x00,0x86,0x7E,
++    0x40,0xC3,0x83,0x84,0x40,0xC3,0x85,0x7C,0x40,0xC3,0x87,0x74,0xC6,0xD4,0xD0,0x03,
++    0x80,0x5C,0xC0,0xD4,0xD8,0x03,0x80,0x54,0xC2,0xD4,0xD8,0x03,0x80,0x4C,0x00,0x0F,
++    0x00,0x01,0x80,0x84,0xC0,0x04,0xC9,0xE4,0x80,0xA1,0xC1,0x40,0x80,0x0C,0xC0,0xE4,
++    0xCA,0x04,0x01,0x00,0xC5,0x00,0x4A,0xCA,0xC0,0x38,0x02,0x01,0x80,0xC4,0x00,0x09,
++    0x00,0x42,0x85,0xCC,0x00,0x5F,0xC5,0x94,0x38,0x00,0x86,0x0E,0xC0,0xAC,0x00,0x2F,
++    0xC6,0x8C,0x38,0x00,0x80,0x0E,0xC0,0xA4,0x00,0x07,0xC0,0x9C,0x40,0x01,0xE8,0x66,
++    0xD0,0x04,0x08,0x01,0xF0,0x8A,0x4A,0x01,0xEC,0x3E,0x10,0x0A,0xD0,0x06,0x30,0x42,
++    0x40,0x8C,0xD1,0x40,0x91,0x15,0x00,0x94,0x00,0x97,0xD1,0x04,0x0A,0x01,0xF0,0x8A,
++    0x49,0x01,0xD0,0x5E,0x40,0x01,0xD0,0x2E,0x10,0x0A,0xEC,0x06,0x31,0x42,0x40,0x8C,
++    0xD1,0x40,0x00,0x84,0x15,0x01,0xF0,0x92,0xC6,0x84,0x38,0x00,0x80,0x06,0xC1,0x14,
++    0xC4,0x0B,0xD0,0x40,0x90,0x05,0xD8,0x74,0x38,0xD8,0x86,0x36,0xDC,0x4C,0x10,0xC2,
++    0xE8,0xB6,0xC0,0x4C,0xD1,0x40,0x00,0x84,0x00,0x97,0xD8,0x7C,0x38,0xD8,0x86,0x36,
++    0xDC,0x54,0x10,0xC2,0xE8,0x66,0xC0,0x54,0xD1,0x40,0x00,0x84,0x00,0x47,0xD8,0x5C,
++    0x10,0xC2,0xEC,0x2E,0xC0,0x5C,0xD0,0x40,0x00,0x84,0x01,0x0F,0x15,0x01,0xF0,0x92,
++    0xC0,0x0C,0xC0,0x03,0xD0,0x00,0x94,0x05,0xC8,0xF4,0x48,0x01,0x88,0x06,0xC9,0xBC,
++    0x10,0x42,0xDC,0xAE,0x40,0x03,0xC9,0xCC,0x18,0x09,0x18,0x42,0x00,0x03,0x69,0x01,
++    0x83,0x26,0xF0,0x48,0x34,0xD2,0x00,0x52,0x19,0x82,0x00,0x03,0xC4,0x64,0x10,0x2A,
++    0x93,0x0E,0xE1,0x40,0x31,0xD2,0x40,0x0B,0x00,0x12,0x1C,0x8A,0x00,0x0B,0x01,0xD7,
++    0xCC,0xB4,0x10,0x42,0xE1,0xBE,0x40,0x03,0xC8,0xCC,0x18,0x42,0x00,0x03,0x01,0x97,
++    0xC0,0xF4,0x40,0x09,0x89,0x16,0x40,0x84,0x00,0xC4,0x01,0x67,0x41,0xC4,0x41,0x8C,
++    0xC4,0x00,0x92,0x05,0x00,0xC4,0xC9,0xD4,0xD0,0xF4,0xC0,0x4B,0x10,0x8A,0x8C,0x16,
++    0x85,0x07,0xE8,0x87,0x00,0x84,0xC9,0x14,0x40,0x84,0x81,0x43,0xE0,0xF8,0xC5,0x0C,
++    0xE0,0x00,0x82,0x0C,0xE0,0xB0,0xC5,0x14,0xE0,0x00,0x82,0x14,0xC4,0x04,0xE0,0x00,
++    0x80,0x04,0xC0,0x94,0x40,0x00,0x82,0x94,0xC2,0x8C,0x40,0x00,0x80,0x8C,0xC0,0x84,
++    0x40,0x01,0x80,0x46,0xC2,0x84,0x40,0x00,0x80,0x84,0xC0,0x7C,0x40,0x00,0x82,0x7C,
++    0xC2,0x74,0x40,0x00,0x80,0x74,0xC0,0xC4,0xE2,0x00,0x92,0x05,0x80,0xC4,0xC8,0x6C,
++    0xC4,0xC4,0x10,0x42,0xD2,0x06,0x38,0x77,0x87,0x0D,0xE9,0x85,0xA8,0x85,0x37,0x6A,
++    0xF0,0x2C,0x30,0x22,0x30,0x8A,0x30,0xFA,0x37,0xC2,0xB9,0xF7,0xF1,0x5F,0x30,0xDA,
++    0x31,0x92,0x31,0x4A,0x37,0x02,0xB9,0xFF,0xDF,0xB7,0xE9,0x85,0xAC,0xBD,0x87,0x45,
++    0x33,0x6A,0xD8,0x43,0x87,0x24,0xD0,0x43,0x85,0x1C,0xE0,0x43,0x40,0x29,0x90,0x2E,
++    0x06,0x01,0x18,0x02,0x18,0x43,0x03,0x01,0x18,0x43,0x05,0x6F,0x02,0x89,0xEE,0x02,
++    0x38,0x00,0xAA,0x26,0x4D,0x52,0x5A,0x43,0x1B,0x42,0x18,0x43,0x02,0x27,0x48,0x42,
++    0x5E,0x43,0x1D,0x4A,0x1B,0x42,0x18,0x43,0x39,0x01,0x30,0x42,0x80,0x01,0x85,0x3C,
++    0xC0,0x01,0x83,0x34,0x00,0xD7,0x03,0x01,0x1B,0x43,0x5F,0x73,0x20,0x01,0x00,0x17,
++    0x43,0xB0,0xE3,0x20,0x97,0x25,0x3F,0x80,0x88,0x16,0xC0,0x24,0x17,0x22,0x9C,0xBE,
++    0xC4,0x24,0x10,0x22,0x87,0xDE,0xA3,0x63,0xC1,0x44,0x08,0xE9,0xCA,0x00,0x08,0x48,
++    0xC1,0x00,0x4A,0xC2,0xEE,0x03,0x08,0x43,0x30,0x12,0x09,0x01,0x00,0x09,0xD8,0x54,
++    0xBC,0xF7,0xF7,0x8F,0xD0,0x54,0x90,0x04,0x31,0x5A,0x31,0x0A,0x00,0x11,0xD0,0x44,
++    0xBE,0xF7,0xF7,0xFF,0x42,0x82,0x41,0x0B,0x3F,0x48,0xAA,0xE6,0x40,0x0B,0x10,0x11,
++    0x18,0x8A,0x00,0x0B,0x40,0x5A,0x09,0x41,0x00,0x0B,0x44,0x0B,0x10,0xF9,0x97,0x19,
++    0x18,0x8A,0x00,0x0B,0x78,0x01,0x88,0x2E,0x30,0x4A,0xC1,0x44,0xB9,0xFF,0xDF,0x3F,
++    0x00,0x01,0x80,0x14,0xC3,0x1C,0x18,0x02,0x00,0x08,0xC2,0x44,0xC6,0x40,0x08,0x09,
++    0x02,0x48,0xC4,0x00,0x81,0x2C,0x00,0x47,0xC6,0x3C,0xE8,0x03,0x40,0x31,0x88,0x36,
++    0x48,0xE2,0x40,0x43,0x10,0x81,0x18,0x82,0x00,0x43,0x38,0x31,0x07,0x07,0x39,0x80,
++    0x80,0x9E,0x08,0x09,0x00,0x0A,0x05,0x07,0xFF,0x85,0x59,0x43,0x10,0x42,0x88,0x1E,
++    0xC6,0x3C,0xE8,0x03,0x47,0x31,0x88,0xBE,0x50,0x15,0xA8,0x04,0x91,0x0C,0x30,0x12,
++    0x30,0xCA,0xD9,0x44,0xC7,0x2C,0xB8,0xFF,0xE8,0x17,0xC7,0x1C,0xCA,0x2C,0x00,0x00,
++    0xC0,0x00,0x82,0x2C,0x43,0xB0,0xE3,0x20,0x90,0x25,0xC7,0x24,0x16,0x22,0x9C,0x9E,
++    0x78,0x01,0x88,0x0E,0xC3,0x14,0x18,0x43,0xE7,0xF8,0x93,0xFD,0xC0,0x34,0xC0,0x03,
++    0xE5,0x00,0x12,0xC2,0xCB,0x5E,0x38,0xF7,0x58,0x80,0x04,0x01,0x20,0x20,0x07,0x00,
++    0xAA,0xAA,0xAA,0xAA,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0x39,0xFF,0x37,0x52,
++    0x00,0x01,0xC8,0x54,0xBC,0xF7,0xEF,0x27,0x87,0x5D,0xE8,0x85,0xAC,0xBD,0x87,0x2D,
++    0x33,0x62,0xD8,0x03,0x87,0x14,0xD0,0x0B,0x88,0x0C,0xC8,0x0C,0xC2,0x14,0x18,0x42,
++    0xCA,0x2C,0x00,0x10,0xC6,0x90,0x0A,0x09,0x02,0x48,0xC4,0xA8,0xA8,0x24,0xC8,0x2C,
++    0x8A,0xA1,0xC1,0x30,0xCF,0x2C,0x88,0xF9,0x8A,0x29,0xC1,0x38,0xB8,0x1C,0xC8,0x2C,
++    0xC0,0x14,0xC0,0x40,0x0A,0xE9,0x09,0x48,0xC0,0x00,0xEA,0x03,0x4E,0xFA,0x0F,0x43,
++    0xD0,0x3C,0x90,0x04,0x30,0x1A,0x09,0x01,0x00,0x09,0xD0,0x2C,0xBA,0xF7,0xF7,0x4F,
++    0x30,0x12,0x01,0x11,0xCF,0x3C,0xB8,0xF7,0xE8,0x9F,0x0A,0x01,0x00,0x09,0xD8,0x3C,
++    0xD7,0x14,0xB8,0xF7,0xE8,0x47,0xD7,0x3C,0x91,0x04,0x30,0x1A,0x00,0x11,0xD0,0x2C,
++    0xCF,0x14,0xB8,0xF7,0xF0,0xB7,0xD1,0x3C,0x92,0x04,0x00,0x29,0xE9,0x0A,0x30,0x1A,
++    0x11,0x01,0x30,0x42,0xBF,0xFF,0xF7,0x97,0x08,0x09,0x30,0x42,0xD8,0x3C,0xD0,0x14,
++    0xBE,0xF7,0xEF,0x8F,0xD0,0x3C,0x90,0x04,0x30,0x1A,0x01,0x19,0xD0,0x2C,0xC8,0x14,
++    0xB8,0xF7,0xF7,0xFF,0x30,0x12,0x01,0x01,0xCF,0x3C,0xB8,0xF7,0xE8,0x4F,0xD1,0x3C,
++    0x90,0x04,0x08,0x01,0x30,0x1A,0x31,0x42,0xD7,0x2C,0xB8,0xF7,0xF5,0x97,0xE0,0x03,
++    0x40,0x29,0xC0,0x96,0x00,0x01,0x08,0x01,0x05,0x67,0xD8,0x13,0x10,0x12,0xC4,0x06,
++    0x01,0x4C,0x41,0x54,0x81,0x93,0x41,0x54,0x83,0xD3,0xE1,0xF8,0xE5,0xB0,0xE3,0x68,
++    0xE6,0x00,0x92,0x05,0xD4,0x0C,0x10,0x82,0x98,0x7E,0xCF,0x1C,0xC0,0x24,0x10,0x01,
++    0x00,0x57,0x40,0x1C,0xC2,0x6B,0xC8,0xD8,0x92,0xDD,0x80,0xD8,0x00,0x1C,0x80,0x5B,
++    0xE4,0x48,0xE2,0x00,0xE6,0x90,0x92,0x95,0xDC,0x1B,0x15,0x9A,0xC0,0x8E,0x87,0x45,
++    0xEB,0x85,0xAF,0x85,0x35,0x42,0x80,0xC1,0x34,0x6A,0xA8,0x01,0x5F,0x53,0x51,0x73,
++    0x53,0x5B,0x55,0x63,0xE0,0x6B,0x69,0x01,0x81,0xD6,0x32,0x2A,0x19,0xEA,0x18,0xAA,
++    0x18,0xAA,0x80,0x0E,0x28,0x19,0x80,0x2B,0xC0,0x2B,0x68,0x01,0x83,0x0E,0xF0,0x68,
++    0x81,0x2B,0x30,0x2A,0x10,0xAA,0x80,0x26,0x30,0xEA,0x10,0xAA,0x88,0x0E,0x10,0x09,
++    0x01,0x97,0x30,0x2A,0x10,0xAA,0x81,0x26,0x30,0xEA,0x10,0xAA,0x88,0x0E,0x10,0x11,
++    0x00,0x57,0x60,0x01,0x80,0x1E,0x10,0x9A,0x88,0x0E,0x10,0x79,0x01,0x27,0x10,0x9A,
++    0x80,0x0E,0x10,0x21,0x00,0x07,0x10,0x01,0xC8,0x1B,0x24,0x01,0x10,0x9A,0x8C,0x0E,
++    0x50,0x01,0x88,0x0E,0x01,0x24,0x04,0x57,0x40,0x1C,0x2C,0xC9,0x0D,0x68,0x13,0x5A,
++    0x92,0x0E,0xE0,0xD8,0x00,0x1C,0x34,0x5A,0x2D,0x09,0x98,0x01,0x50,0x11,0x80,0x26,
++    0xE0,0x8E,0x50,0x01,0x80,0xDE,0x50,0x09,0x8C,0xCE,0x40,0x34,0x70,0xE1,0xC9,0xB6,
++    0xF0,0xDB,0x5A,0x51,0x90,0x9E,0x30,0x5A,0x98,0x01,0xE6,0xF3,0x18,0x72,0xA1,0xF3,
++    0xA4,0x6B,0x04,0x24,0x00,0x5F,0x50,0x21,0x80,0x4E,0x50,0x79,0x8C,0x3E,0x40,0x34,
++    0x70,0xE1,0xC9,0x26,0xF0,0xDB,0x5A,0x51,0x94,0x0E,0xA0,0x6B,0x04,0x24,0x8C,0x13,
++    0xEF,0x85,0xAB,0x9D,0x80,0x4D,0x34,0x32,0xC4,0x54,0xD0,0x03,0x80,0x3C,0xC0,0x54,
++    0xD0,0x03,0x86,0x34,0xC0,0x54,0xE8,0x03,0x43,0xF1,0x98,0x8E,0xC5,0x54,0x80,0x01,
++    0xF0,0x03,0x40,0x01,0x88,0x66,0xC3,0x54,0xCA,0x03,0x34,0x00,0x70,0x00,0x80,0x2C,
++    0x04,0x09,0x06,0x00,0xC1,0xB8,0x31,0xA2,0xA1,0xA1,0x01,0x81,0xF7,0x82,0x41,0x81,
++    0xDF,0x26,0xC0,0x81,0x30,0x84,0x01,0x09,0x80,0x24,0x00,0x0F,0x00,0x01,0x80,0x24,
++    0x01,0x91,0xF1,0x82,0x0E,0x79,0x1F,0x4A,0x10,0x42,0xE4,0x26,0x83,0x81,0x37,0x84,
++    0x00,0x09,0x80,0x1C,0x00,0x0F,0x00,0x01,0x83,0x1C,0x40,0xEA,0x82,0x14,0x10,0x02,
++    0x80,0x0C,0x00,0x01,0x81,0x44,0x00,0xBF,0x29,0x01,0x00,0x77,0x01,0x01,0xF0,0xC2,
++    0xCC,0x2C,0x10,0x42,0xD0,0xCE,0x40,0x01,0xE8,0x56,0xC8,0x14,0x10,0x42,0xEC,0x06,
++    0x80,0x14,0xC0,0x24,0x40,0x01,0x80,0xE6,0xC2,0x03,0xF1,0x00,0x80,0x03,0x01,0xC7,
++    0x40,0x01,0xD0,0xB6,0xCC,0x0C,0x10,0x42,0xD0,0x06,0x80,0x0C,0xC0,0x1C,0x40,0x01,
++    0x81,0x7E,0xC0,0x03,0xE1,0x00,0x82,0x03,0x00,0x5F,0xC0,0x54,0x08,0x21,0xEB,0x03,
++    0x83,0x07,0xD8,0x47,0x48,0x19,0x8B,0x26,0xC9,0x2C,0xC0,0x03,0x42,0x48,0xD2,0x00,
++    0x85,0x03,0xE1,0xF8,0xE3,0x20,0xE3,0x68,0x90,0x6D,0xC7,0x34,0x16,0x2A,0x9C,0x6E,
++    0xC2,0x44,0xE0,0x00,0x90,0x05,0x86,0x44,0xC8,0x3C,0xC0,0x44,0x16,0x42,0x9C,0x1E,
++    0x70,0x8C,0xC1,0x14,0xC1,0x40,0x30,0x84,0x70,0x8C,0xC3,0x0C,0xC3,0x40,0x30,0x84,
++    0x37,0x57,0xAC,0xBD,0x80,0x15,0x34,0x62,0x37,0xBA,0xE0,0x2B,0xDF,0x33,0xD3,0x03,
++    0x1A,0x42,0x03,0x08,0xC0,0x14,0xC0,0x40,0x0C,0x09,0x06,0x48,0xC0,0x00,0x82,0x0C,
++    0x36,0x02,0x81,0x01,0xE4,0x0B,0x10,0x01,0x18,0x8A,0xA0,0x0B,0x00,0xB1,0xED,0x02,
++    0x42,0x01,0x80,0x46,0x09,0x09,0x30,0xDA,0x30,0x52,0x31,0x42,0xBC,0xF7,0xE7,0x5F,
++    0x30,0x1A,0xB9,0x04,0x08,0x01,0x00,0x19,0xD7,0x14,0xB8,0xF7,0xE2,0xD7,0x06,0x29,
++    0xE9,0x0A,0x30,0x1A,0x30,0xD2,0xC1,0x0C,0xBE,0xFF,0xC7,0xEF,0x58,0x03,0x17,0x09,
++    0x35,0x8A,0x00,0x4A,0x1F,0x42,0x18,0x03,0xE7,0x68,0x93,0x6D,0x58,0x0B,0x03,0x0F,
++    0xE7,0x68,0x93,0x6D,0x35,0x82,0x00,0x42,0x10,0x0A,0x88,0x0E,0x17,0xAA,0x9D,0xBE,
++    0x11,0xAA,0x85,0x06,0xA1,0x2B,0x37,0xDA,0x30,0x52,0x09,0x01,0x07,0x09,0xB8,0xF7,
++    0xE1,0x17,0x33,0x1A,0xB9,0x04,0x30,0x4A,0x00,0x11,0xD0,0x14,0xBD,0xF7,0xE7,0x8F,
++    0xC1,0x14,0x08,0xE9,0xCA,0x00,0x0A,0x48,0xC1,0x00,0x52,0x62,0xEE,0x03,0x08,0x83,
++    0x42,0x62,0x41,0x0B,0x3F,0x48,0xAA,0xE6,0x04,0x41,0x00,0x83,0x47,0x83,0x08,0xF9,
++    0x88,0x19,0x18,0x42,0x00,0x83,0x80,0x2D,0xEF,0x85,0xAF,0x85,0x84,0xBD,0x34,0x22,
++    0x37,0x6A,0xD0,0x7B,0xD0,0x43,0x85,0x6C,0x31,0x1A,0x9B,0xA1,0x9C,0xB4,0x08,0x29,
++    0x34,0x02,0x03,0x48,0xC6,0x20,0x0A,0x09,0x03,0x48,0x24,0x0A,0x8B,0xAC,0xC8,0x43,
++    0x02,0x00,0x92,0x05,0x80,0x2C,0x00,0x01,0x80,0x24,0x00,0x09,0x81,0x14,0x30,0x42,
++    0x80,0x01,0x86,0xA4,0xE3,0x03,0x5A,0x73,0x32,0x32,0x3C,0x10,0x58,0x43,0x1D,0x32,
++    0x50,0x01,0xD0,0x46,0x40,0xA2,0x18,0x32,0xB3,0x1C,0x30,0x82,0x10,0xD9,0x07,0x82,
++    0xD2,0xA4,0xA0,0x83,0x00,0x47,0x40,0x82,0x18,0x02,0x1E,0x32,0xB3,0x1C,0x30,0x82,
++    0x10,0x21,0x18,0x82,0xD2,0xA4,0xA0,0x83,0x35,0x01,0x18,0x73,0xD8,0x43,0x45,0x01,
++    0x80,0x36,0xD0,0x6C,0xC2,0x14,0xF0,0x90,0x00,0x82,0xD4,0x1C,0x18,0x82,0x80,0x1C,
++    0x34,0x52,0x91,0x01,0x92,0x9C,0xF0,0x83,0x80,0x8C,0x00,0x3F,0x00,0x01,0x00,0x42,
++    0xC7,0x87,0xF9,0xFF,0x18,0x00,0x04,0x42,0xAA,0xAA,0xAA,0xAA,0xC0,0x9C,0x10,0xC1,
++    0xB0,0x12,0x94,0x84,0xD0,0x9C,0x00,0x01,0x18,0x83,0x80,0x7C,0xD6,0x9C,0x10,0x83,
++    0x80,0x74,0x10,0x01,0x97,0x64,0x50,0xFA,0x90,0x5C,0x10,0x01,0x91,0x54,0x30,0x72,
++    0xB5,0x01,0x99,0x83,0xCA,0x43,0x45,0x00,0x85,0x4C,0x10,0xA1,0xFA,0x82,0x82,0x00,
++    0x85,0x44,0xE0,0x43,0x40,0x29,0xC0,0xCE,0x03,0x01,0x30,0x12,0x32,0x84,0x30,0x84,
++    0x30,0x22,0x04,0x87,0x10,0x01,0x00,0x47,0x41,0x44,0x80,0x03,0x40,0x44,0x80,0xC3,
++    0xE4,0xD8,0xE2,0x48,0xE2,0x20,0xE3,0x90,0x95,0x95,0x12,0xD2,0xDB,0xA6,0x37,0x02,
++    0xE2,0x00,0x92,0x05,0x30,0x22,0xC4,0x6C,0x2F,0x22,0xDC,0x5E,0xC0,0xB4,0x80,0x3C,
++    0xE0,0xAC,0x00,0x01,0x85,0x94,0x00,0xBF,0x00,0x01,0x80,0x34,0x30,0x32,0xCC,0x94,
++    0xC4,0x14,0x00,0x42,0xC8,0x1C,0x10,0x42,0x80,0x86,0x03,0x01,0x32,0x22,0x04,0xEF,
++    0xC1,0x3C,0x40,0x0C,0xC2,0x03,0xD0,0x00,0x91,0x05,0x00,0x04,0xCA,0x9C,0xE0,0x4B,
++    0x48,0x11,0x98,0xA6,0xCC,0x84,0x10,0x42,0xD5,0x8E,0xD8,0x8B,0xE5,0x48,0x9A,0x8B,
++    0xC8,0x64,0xC0,0x48,0x88,0x64,0xD8,0x5C,0x34,0x12,0x10,0x1A,0xD8,0x06,0xD0,0x5C,
++    0x90,0x5C,0xD8,0x54,0x34,0x12,0x10,0x1A,0xE0,0x06,0xD0,0x54,0x90,0x54,0xC8,0x2C,
++    0x10,0x42,0xD4,0x3E,0x32,0x8A,0xE3,0x48,0x94,0x4D,0x36,0x72,0xC8,0x34,0xC0,0x48,
++    0x90,0x4D,0x88,0x34,0xCC,0x4C,0x10,0x42,0xEB,0xBE,0xC8,0x4B,0x10,0x0A,0xE4,0x2E,
++    0xDD,0x94,0x58,0x53,0x0C,0x09,0x00,0xCA,0x1D,0x52,0x18,0x53,0xE0,0x8B,0x4B,0x09,
++    0x8C,0x0E,0x08,0x09,0xA0,0x8B,0xCB,0x8C,0x10,0x42,0xEC,0xBE,0x30,0x02,0x0B,0x09,
++    0x00,0x0A,0xC4,0x7C,0x18,0x0A,0x88,0x7C,0x00,0x87,0xC8,0x44,0x10,0x42,0xD4,0x6E,
++    0xE0,0x8B,0x4B,0x09,0x8C,0x0E,0x08,0x09,0xA0,0x8B,0xCB,0x84,0x10,0x42,0xD4,0x2E,
++    0x30,0x02,0x0B,0x09,0x00,0x0A,0xC4,0x74,0x18,0x0A,0x88,0x74,0xE0,0x20,0xC5,0x3C,
++    0xE0,0x00,0x82,0x3C,0x32,0x02,0xE3,0x00,0x94,0x05,0x32,0x22,0x2C,0xE2,0xDD,0xFE,
++    0x30,0x82,0x43,0x11,0xCB,0x2E,0x30,0x8A,0xC0,0x34,0x80,0x07,0xC8,0x6F,0x97,0x05,
++    0x00,0x07,0x00,0x01,0x03,0xC8,0xD3,0x20,0x11,0x01,0x00,0x57,0x00,0x67,0x41,0x01,
++    0xE8,0x7E,0x08,0x01,0xF0,0x0A,0xDB,0x2C,0x10,0xCA,0xD4,0xB6,0xE4,0x18,0x12,0xCA,
++    0xE8,0x16,0xD0,0x48,0x00,0x0C,0x01,0x87,0x48,0x01,0xE8,0x76,0x09,0x09,0x00,0x0C,
++    0x00,0x5F,0x08,0x01,0xF4,0x0A,0x13,0x0A,0xD0,0x16,0xD0,0x48,0x00,0x0C,0x01,0x27,
++    0x48,0x01,0xD0,0x16,0x0E,0x01,0x18,0x4A,0x00,0x0C,0x09,0x01,0xF0,0x0A,0xDB,0x44,
++    0x10,0xCA,0xD4,0x1E,0xCA,0x24,0xE0,0x48,0x90,0x4D,0x8E,0x24,0xE2,0x20,0xE5,0x90,
++    0x95,0x95,0x12,0xD2,0xD8,0x9E,0x06,0x5F,0x00,0x01,0x08,0x01,0x01,0x37,0x00,0x0C,
++    0xE0,0x20,0xD5,0x3C,0xE0,0x90,0x92,0x3C,0xE2,0x00,0x92,0x05,0x17,0xC2,0xDD,0xB6,
++    0xC2,0x94,0xE0,0x00,0x90,0x05,0x82,0x94,0xC8,0x6C,0xC0,0x94,0x10,0x42,0xD4,0x06,
++    0x39,0x17,0xCA,0x43,0x40,0x71,0xC9,0x0E,0x01,0x71,0x89,0x43,0xC9,0x24,0xC8,0x43,
++    0x42,0x48,0xC4,0x00,0x91,0x05,0x8E,0x43,0x40,0x81,0xCA,0x0E,0x01,0x81,0x8A,0x43,
++    0xC2,0x9C,0xE0,0x03,0x42,0x11,0x98,0x56,0xD8,0x83,0x45,0x11,0xCC,0x3E,0xF2,0x00,
++    0x90,0x05,0x86,0x04,0xC8,0x54,0xC0,0x5C,0xC0,0x08,0xC2,0x64,0xD0,0x00,0xCA,0x04,
++    0x84,0x07,0xC8,0x17,0x90,0x05,0x80,0x0C,0x05,0x01,0x28,0x44,0x08,0xE9,0x0B,0x48,
++    0x10,0x01,0xE0,0xAC,0x31,0x22,0x04,0x0F,0x18,0x01,0x00,0xCF,0x01,0x01,0xF0,0x02,
++    0xF5,0x84,0x10,0x82,0xD0,0x8E,0xF0,0x0C,0xD8,0x00,0xAC,0x06,0x10,0x02,0x92,0x05,
++    0x34,0x32,0x10,0x0A,0xE0,0x06,0x30,0x72,0x30,0x8A,0x31,0x32,0x10,0x12,0xDC,0x06,
++    0x31,0xB2,0x30,0x92,0x69,0x74,0xC5,0x80,0x2D,0x44,0xE5,0x20,0xE2,0xD8,0x92,0xDD,
++    0x17,0xDA,0xDD,0x1E,0x32,0x02,0xE3,0x00,0x94,0x05,0x32,0x22,0xDC,0x6C,0x28,0xE2,
++    0xDD,0xD6,0x6E,0x44,0xC2,0x48,0xD4,0x00,0x90,0x05,0xCC,0x04,0x82,0x07,0xC8,0x17,
++    0x28,0x44,0xC5,0x0C,0x40,0x01,0xD0,0x06,0x13,0x02,0x2A,0x44,0x00,0x17,0x00,0x01,
++    0x2D,0x44,0x2B,0x44,0xC8,0x9C,0xC0,0x7C,0x18,0x43,0xC8,0x9C,0xC6,0x74,0x10,0x43,
++    0x87,0xBD,0xE8,0x85,0xAC,0xBD,0x87,0x15,0x32,0x62,0x70,0x9A,0x29,0x01,0x80,0xAB,
++    0x09,0x11,0x30,0x02,0x80,0x01,0x35,0x3A,0xA9,0x0B,0x34,0x0A,0xD0,0x24,0xC0,0x14,
++    0xBD,0xFF,0xDF,0x67,0xAD,0xEB,0xDD,0x03,0x40,0x01,0x80,0x76,0x6F,0x5A,0x42,0x43,
++    0x91,0x3D,0x4C,0x04,0x00,0x43,0x07,0x09,0x81,0x83,0x31,0x0A,0xD0,0x24,0xC0,0x14,
++    0xBA,0xFF,0xE7,0xA7,0x01,0x01,0x80,0x83,0x00,0x7B,0xD7,0x24,0x90,0x04,0x08,0x01,
++    0x30,0x1A,0x31,0x42,0xD7,0x14,0xB8,0xF7,0xD5,0xE7,0xE5,0x03,0x40,0x41,0x96,0x0E,
++    0xE5,0x00,0xA2,0x03,0x30,0xBF,0x10,0x01,0x00,0x37,0x08,0x01,0xE4,0x48,0x92,0x4D,
++    0x4F,0xA1,0xC8,0xDE,0xE4,0x90,0x92,0x95,0x17,0x12,0xCC,0xB6,0x38,0x82,0x3B,0x18,
++    0x78,0xD8,0x10,0x09,0x06,0xD2,0x94,0x95,0x18,0xF9,0x0F,0xD8,0x01,0xC2,0x58,0xA2,
++    0xC0,0x00,0x4E,0x09,0x88,0x66,0x40,0x0B,0x18,0x8A,0x04,0x0B,0x44,0x0B,0x1A,0x8A,
++    0x04,0x0B,0x42,0x0B,0x1C,0x8A,0x04,0x0B,0x44,0x0B,0x1E,0x8A,0x03,0x0B,0x3E,0x82,
++    0x48,0x01,0x88,0x66,0x44,0x0B,0x1A,0x8A,0x04,0x0B,0x42,0x0B,0x1C,0x8A,0x04,0x0B,
++    0x44,0x0B,0x1E,0x8A,0x00,0x0B,0x46,0x0B,0x18,0x8A,0x00,0x0B,0x38,0x82,0x4B,0x11,
++    0x88,0x66,0x40,0x0B,0x18,0x8A,0x04,0x0B,0x44,0x0B,0x1A,0x8A,0x04,0x0B,0x42,0x0B,
++    0x1C,0x8A,0x04,0x0B,0x40,0x0B,0x1E,0x8A,0x03,0x0B,0x3E,0x82,0x4F,0x19,0x88,0xE6,
++    0x44,0x0B,0x18,0x8A,0x04,0x0B,0x40,0x0B,0x1C,0x8A,0x04,0x0B,0x44,0x0B,0x1E,0x8A,
++    0x02,0x0B,0x46,0x0B,0x1A,0x8A,0x00,0x0B,0x3F,0x82,0xAB,0x8D,0x80,0x3D,0xC4,0x3C,
++    0xC8,0x3C,0x48,0x00,0x02,0x00,0xC4,0x00,0x38,0x00,0x48,0x92,0x72,0x00,0xC2,0x28,
++    0x40,0x72,0x40,0x0B,0x90,0x4D,0x8C,0x34,0x5C,0x0B,0x90,0x4D,0x8A,0x2C,0x58,0x0B,
++    0x90,0x4D,0x8C,0x24,0x5C,0x0B,0x94,0x4D,0x8E,0x1C,0x50,0x0B,0x90,0x75,0x4C,0x52,
++    0x44,0x53,0x92,0x95,0x90,0x14,0x40,0x53,0x92,0xBD,0x44,0x13,0x90,0x95,0x94,0x0C,
++    0x58,0x12,0x00,0x5F,0xE7,0xC7,0xF8,0xFF,0x00,0xB0,0x00,0x01,0x00,0x01,0x00,0x42,
++    0x80,0x00,0x00,0x42,0x08,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0x98,0x01,0x52,0xD3,
++    0x90,0x95,0x94,0x04,0x10,0x09,0x00,0x13,0xA8,0x10,0x1C,0x13,0x12,0x81,0x18,0x13,
++    0x18,0x13,0x14,0x79,0x11,0x13,0x16,0x01,0x00,0x53,0x12,0x89,0x02,0x53,0x40,0x0B,
++    0x10,0x81,0x19,0x8A,0x07,0x0B,0x02,0xF9,0x80,0x89,0x17,0xC3,0x07,0x09,0xB8,0xFF,
++    0xFF,0x17,0x03,0xF9,0x80,0x89,0x14,0xC3,0x07,0x09,0xB8,0xFF,0xF8,0xE7,0x02,0x19,
++    0x11,0x00,0x00,0x43,0x07,0x09,0xB8,0xFF,0xF8,0xB7,0x0A,0x11,0xC7,0x3C,0xB8,0xFF,
++    0xF8,0xF7,0x22,0xA1,0x01,0x01,0x40,0x4B,0x30,0x48,0xA8,0x16,0xE7,0x20,0x93,0x25,
++    0x03,0x0F,0xF0,0x20,0x92,0x25,0xE7,0x00,0x90,0x05,0x46,0x51,0x98,0x9E,0x0F,0x09,
++    0xC7,0x3C,0xB8,0xFF,0xF8,0x67,0x42,0x6A,0xC8,0x34,0x00,0x0B,0xC8,0x2C,0x18,0x0B,
++    0xCA,0x24,0x18,0x0B,0xCC,0x1C,0x18,0x0B,0x10,0x33,0x4E,0x4A,0xD2,0x14,0x00,0x53,
++    0x00,0x7B,0xC8,0x0C,0x00,0x0B,0x4A,0x2A,0xC2,0x04,0x88,0x01,0x10,0x43,0x60,0xA1,
++    0xC8,0x16,0x00,0x09,0x87,0x45,0xE8,0x85,0x07,0x01,0x38,0xDF,0x00,0x01,0x00,0x42,
++    0x18,0x00,0x04,0x42,0x00,0x0F,0x00,0x26,0xF8,0x48,0x48,0x21,0x94,0xDE,0x3F,0x58,
++    0xA8,0x0E,0x00,0x14,0xE6,0x00,0x3C,0x48,0x80,0x06,0x80,0x13,0x38,0x82,0x4B,0x01,
++    0x86,0x5E,0x38,0x18,0x80,0x16,0x80,0x13,0xE2,0x00,0xF2,0x48,0x48,0x11,0x98,0x26,
++    0x38,0x18,0xAC,0x16,0x04,0x14,0xE0,0x00,0xF7,0x48,0x3C,0x1F,0x17,0x01,0x38,0x77,
++    0x16,0x01,0x38,0xFF,0x10,0x01,0x48,0x18,0x11,0x5A,0x9C,0x66,0x54,0x18,0x10,0x5A,
++    0x98,0x8E,0x18,0x01,0x32,0xE2,0x04,0x77,0x30,0x1A,0x18,0x5A,0xA0,0xE6,0x11,0x01,
++    0x44,0x18,0x12,0x5A,0x98,0x8E,0x49,0x18,0x10,0x5A,0x9C,0xE6,0x54,0x18,0x10,0x5A,
++    0x9C,0x0E,0x30,0xA2,0x06,0xFF,0x49,0x18,0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD6,0x00,
++    0x0C,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD4,0x00,0x0A,0x92,0x4A,0x18,
++    0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD2,0x00,0x08,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,
++    0x0E,0x58,0xD0,0x00,0x0E,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD6,0x00,
++    0x0C,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD4,0x00,0x0A,0x92,0x42,0x18,
++    0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD2,0x00,0x0A,0x92,0xD2,0x08,0x90,0x06,0x30,0x0A,
++    0x08,0x92,0x32,0x82,0x3A,0x82,0x03,0xEF,0x78,0x50,0x86,0x06,0x10,0x4A,0x82,0x18,
++    0x9A,0x06,0x10,0x02,0x00,0x9A,0x12,0x01,0x30,0xE2,0x4C,0x18,0x11,0x5A,0x9C,0x6E,
++    0x54,0x18,0x10,0x5A,0x9F,0x96,0x10,0xE1,0x08,0x48,0xD4,0x95,0x54,0x18,0x10,0x5A,
++    0x9C,0x66,0x08,0x48,0x8C,0x90,0x14,0x5A,0x9C,0x46,0x08,0x48,0x8C,0x90,0x14,0x5A,
++    0x9C,0x26,0x08,0x48,0x84,0xD6,0x89,0x90,0x04,0x07,0x48,0x48,0x4C,0x18,0x16,0x5A,
++    0x9E,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,0x4C,0x18,0x14,0x5A,0x9C,0x0E,0x08,0x58,
++    0xD2,0x00,0x0E,0x92,0x4C,0x18,0x12,0x5A,0x9A,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,
++    0x4C,0x18,0x10,0x5A,0x98,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,0x44,0x18,0x16,0x5A,
++    0x9E,0x0E,0x00,0x58,0xD2,0x00,0x0E,0x92,0x44,0x18,0x14,0x5A,0x9C,0x0E,0x00,0x58,
++    0xD2,0x00,0x0E,0x92,0x92,0xCE,0x46,0x18,0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD2,0x00,
++    0x0A,0x92,0xD2,0x08,0x90,0x06,0x30,0x0A,0x32,0x1A,0x0B,0x92,0x80,0xD8,0x32,0x82,
++    0x9A,0x0E,0x10,0x02,0x58,0x01,0xA8,0x06,0x13,0x4A,0x3A,0x82,0x32,0x1A,0x83,0xD8,
++    0x9A,0x06,0x10,0x02,0xA8,0x0D,0x00,0x01,0x36,0x02,0x36,0x02,0xEB,0x15,0x30,0xAA,
++    0x81,0x07,0xC0,0x17,0x30,0x72,0x05,0x28,0x32,0x4A,0x33,0x9A,0x46,0x00,0x06,0x00,
++    0x30,0x2A,0x84,0xC5,0xAF,0x05,0xB9,0xDF,0xEB,0xBF,0xE6,0x05,0x3A,0x01,0x40,0x48,
++    0x30,0xB2,0x35,0x01,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,
++    0x2E,0x06,0x2E,0x06,0xEA,0x01,0x02,0x48,0x33,0x6A,0x3C,0x82,0x36,0x22,0x30,0x02,
++    0x31,0x02,0x36,0x02,0xB8,0xD7,0xDF,0xFF,0x43,0x02,0x38,0x82,0x58,0x60,0x05,0x01,
++    0x40,0x12,0x48,0x1A,0xF3,0x5D,0x3D,0x82,0x00,0x68,0x00,0x00,0x00,0xC0,0x00,0x00,
++    0x00,0x30,0x01,0x10,0x39,0x82,0xA3,0x85,0x33,0xA2,0xF3,0x20,0xC3,0x2B,0xE1,0x20,
++    0x10,0x5A,0x95,0x06,0x33,0xEA,0xE8,0x1A,0x07,0xD8,0xC2,0x18,0xE0,0x85,0x39,0xC2,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x20,0x01,0x42,
++    0x80,0x20,0x01,0x42,0x80,0x20,0x01,0x42,0x80,0x20,0x01,0x42,0x80,0x20,0x03,0x42,
++    0x80,0xA0,0x00,0x42,0x80,0x20,0x03,0x42,0x80,0xA0,0x00,0x42,0x80,0x20,0x03,0x42,
++    0x80,0xA0,0x00,0x42,0x80,0x20,0x03,0x42,0x80,0xA0,0x00,0x42,0x80,0xA0,0x03,0x42,
++    0x80,0x20,0x00,0x42,0x80,0xA0,0x03,0x42,0x80,0xA0,0x03,0x42,0x80,0x20,0x04,0x42,
++    0x80,0x20,0x04,0x42,0x80,0x20,0x04,0x42,0x80,0xA0,0x04,0x42,0x10,0x20,0x08,0x40,
++    0x40,0x08,0x20,0x10,0x10,0x20,0x08,0x40,0x20,0x08,0x40,0x20,0x20,0x10,0x08,0x40,
++    0x08,0x81,0x03,0x42,0x08,0xC1,0x03,0x42,0x08,0x41,0x00,0x42,0x08,0x81,0x00,0x42,
++    0x08,0xC1,0x00,0x42,0x08,0x01,0x01,0x42,0x08,0x81,0x02,0x42,0x08,0x41,0x02,0x42,
++    0x08,0xC1,0x02,0x42,0x08,0x01,0x02,0x42,0x08,0x01,0x02,0x42,0x08,0xC1,0x01,0x42,
++    0x08,0x41,0x02,0x42,0x08,0x81,0x01,0x42,0x08,0x81,0x02,0x42,0x08,0x41,0x01,0x42,
++    0x08,0xC1,0x02,0x42,0x08,0x01,0x01,0x42,0x08,0x01,0x03,0x42,0x08,0x81,0x00,0x42,
++    0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x00,0x00,
++    0x00,0x08,0xF8,0x0F,0xFF,0x07,0xF8,0xFF,0x07,0xF8,0x0F,0xF8,0x08,0x00,0x08,0x08,
++    0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x28,0xB5,0x39,0xC5,0x08,0x1D,
++    0x1B,0x2B,0x3A,0x28,0x53,0xB5,0x0A,0xC5,0x00,0x08,0x01,0x00,0x01,0x00,0x50,0x0D,
++    0x52,0x1D,0x52,0xB5,0x39,0x0D,0x04,0x08,0x51,0x3D,0x53,0x1D,0x51,0x3D,0x54,0x95,
++    0x51,0x3D,0x54,0x95,0x51,0x3D,0x54,0x95,0x0B,0x3D,0x34,0x88,0x51,0x3D,0x54,0x1D,
++    0x51,0x3D,0x54,0x95,0x04,0x00,0x50,0x3D,0x50,0x1D,0x01,0x00,0x00,0x00,0x00,0x00,
++    0x54,0x2D,0x53,0x3D,0x32,0x8D,0x32,0x38,0x01,0x28,0x0A,0x45,0x50,0xB5,0x53,0x95,
++    0x00,0x00,0x00,0x00,0x52,0xA5,0x51,0xB5,0x09,0xC5,0x03,0x08,0x03,0x00,0x50,0x3D,
++    0x55,0x1D,0x51,0x0D,0x51,0x3D,0x54,0x95,0x51,0x3D,0x53,0x1D,0x51,0x3D,0x54,0x95,
++    0x51,0x0D,0x55,0x0D,0x54,0xB5,0x3A,0x0D,0x00,0x08,0x01,0x00,0x53,0xA5,0x51,0x2D,
++    0x52,0x3D,0x34,0x8A,0x1D,0x38,0x52,0x45,0x52,0x0D,0x51,0x1D,0x54,0xB5,0x3A,0x0D,
++    0x53,0xA5,0x29,0xB5,0x39,0xC5,0x08,0x1D,0x19,0x2D,0x22,0x1D,0x44,0x0D,0x31,0x3D,
++    0x23,0x95,0x09,0xC1,0x29,0xB5,0x0B,0x1D,0x1B,0x2B,0x3A,0x28,0x00,0x00,0x00,0x08,
++    0xFF,0x07,0x00,0xF8,0x08,0x00,0x10,0x10,0x08,0x10,0x10,0x10,0x08,0x08,0x10,0x08,
++    0x10,0x08,0x10,0x08,0x10,0x10,0x08,0x08,0x10,0x10,0x08,0x08,0x08,0x08,0x10,0x10,
++    0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x08,0xF8,0x07,
++    0x08,0x00,0x08,0x08,0xE8,0xA2,0x01,0x00,0x00,0x00,0x00,0x01,0x00,0xC0,0x00,0x00,
++    0x00,0x00,0x05,0x00,0xE8,0x62,0x02,0x00,0x00,0xC0,0x00,0x01,0x58,0xA0,0x07,0x00,
++    0x00,0xE0,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0x00,0x70,0x00,0x30,0x09,0x40,0x1B,0x00,0x06,0x78,0x50,0x56,
++    0xFF,0xFF,0xFF,0xFF,0x3C,0x50,0x00,0x10,0x00,0x20,0x18,0x00,0x1E,0xAC,0xE4,0x09,
++    0x0F,0x00,0xCA,0xCA,0xFF,0xFF,0xFF,0xFF,0x0A,0x07,0x82,0x00,0x04,0x00,0x00,0x03,
++    0x95,0x83,0xC1,0x3C,0xC8,0xB2,0xB5,0x47
++};
++
++
++
++#define FW_INFO_SIZE	(0x18)
++#define FW_REAL_SIZE	(sizeof(fwbin))
++#define FW_BIN_SIZE		(24*1024+24)	    //24K byte
++
++#endif
++
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update1/cst3xx.h b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update1/cst3xx.h
+new file mode 100644
+index 000000000..68791e6af
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update1/cst3xx.h
+@@ -0,0 +1,29 @@
++#ifndef TOUCHSCREEN_CST3XX__H
++#define TOUCHSCREEN_CST3XX__H
++
++
++/* -- dirver configure -- */
++#define CFG_MAX_TOUCH_POINTS	1
++#define MAX_AREA	0xff
++
++#define CST3XX_NAME 	"cst3xx"
++
++/*register address*/
++#define CST3XX_ADDRESS 	0x1A
++
++
++/* The platform data for the Focaltech ft5x0x touchscreen driver */
++struct cst3xx_platform_data {
++	unsigned int x_min;
++	unsigned int y_min;
++	unsigned int x_max;
++	unsigned int y_max;
++	unsigned long irqflags;
++	unsigned int int_gpio;
++	unsigned int reset_gpio;
++};
++
++
++
++#endif
++
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update1/cst3xx_1.c b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update1/cst3xx_1.c
+new file mode 100644
+index 000000000..0c7725e88
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update1/cst3xx_1.c
+@@ -0,0 +1,1422 @@
++/*
++ * cst3xx Touchscreen Controller Driver
++ */
++
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/i2c.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of_gpio.h>
++#include <linux/pm_qos.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include <linux/input/cst3xx.h>
++#include <linux/input/hyn_cst3xx_RS659_fw.h>
++#include "../../video/jz_fb_v13/jz_fb.h"
++
++struct st1615_ts_finger {
++	u16 x;
++	u16 y;
++	u8 t;
++	bool is_valid;
++};
++
++struct cst3xx_ts_data {
++	struct i2c_client *client;
++	struct input_dev *input_dev;
++	struct cst3xx_platform_data *pdata;
++	struct work_struct  work;
++       struct delayed_work dwork;
++	struct workqueue_struct *workqueue;
++	int irq;
++};
++
++static int cst3xx_into_program_mode(struct i2c_client * client);
++static int cst3xx_erase_program_area(struct i2c_client * client);
++static void cst3xx_reset_ic(struct cst3xx_ts_data *ts,unsigned int ms);
++static int cst3xx_write_program_data(struct i2c_client * client,const unsigned char *pdata);
++
++static int cst3xx_check_checksum(struct i2c_client * client);
++
++static int cst3xx_exit_program_mode(struct i2c_client * client);
++
++static int cst3xx_update_firmware(struct cst3xx_ts_data *ts, const unsigned char *pdata);
++
++static int cst3xx_firmware_info(struct i2c_client * client);
++
++static int cst3xx_update_judge( unsigned char *pdata, int strict);
++
++static int cst3xx_boot_update_fw(struct cst3xx_ts_data *ts,  unsigned char *pdata);
++
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_test(struct i2c_client *client);
++static void cst3xx_reset(struct cst3xx_ts_data *ts) ;
++extern  void close_vcc3v3Power(void);
++extern  void open_vcc3v3Power(void);
++
++static unsigned char *pcst3xx_update_firmware = (unsigned char *)cst3_fw ; //the updating firmware
++static unsigned int   g_cst3xx_ic_version  = 0;
++static unsigned int   g_cst3xx_ic_checksum = 0;
++static unsigned int   g_cst3xx_ic_checkcode =0;
++static unsigned int   g_cst3xx_ic_project_id  = 0;
++static unsigned int   g_cst3xx_ic_type  = 0;
++
++static unsigned char  report_flag = 0;
++static unsigned int x_temp_pos = 0;
++static unsigned int y_temp_pos = 0;
++
++#define HYN_DRAW_POINT
++
++#define USE_ANALOG_I2C     1 //i2c analog
++//#define USE_HIGHEST_I2CA  1// x1000 highest i2c
++//#define USE_LOWEST_I2CA   1 // x1000 lowest i2c
++#define HYN_UPDATE_FIRMWARE_POWERON_ENABLE
++//#define HYN_UPDATE_FIRMWARE_ENABLE
++
++#pragma pack(1)
++typedef struct
++{
++    u16 pid;                 //product id   //
++    u16 vid;                 //version id   //
++} st_tpd_info;
++#pragma pack()
++
++st_tpd_info tpd_info;
++
++#define CST3XX_BIN_SIZE    (24*1024 + 24)
++#define CST3XX_MAX_X  340
++#define CST3XX_MAX_Y  800
++#define ERROR_TOUCH   1
++
++static void cst3xx_ts_power(struct cst3xx_ts_data *ts, bool poweron)
++{
++	if (gpio_is_valid(ts->pdata->reset_gpio))
++		gpio_direction_output(ts->pdata->reset_gpio, poweron);
++}
++
++static int cst3xx_into_program_mode(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[4];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x01;
++	buf[2] = 0xAA;	//set cmd to enter program mode
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0)  return -1;
++
++	mdelay(2);
++
++	buf[0] = 0xA0;
++	buf[1] = 0x02;	//check whether into program mode
++	ret = cst3xx_i2c_read_register(client, buf, 1);
++	if (ret < 0)  return -1;
++
++	if (buf[0] != 0x55) return -1;
++
++	return 0;
++}
++static int cst3xx_erase_program_area(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[3];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x02;
++	buf[2] = 0x00;		//set cmd to erase main area
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0) return -1;
++
++	mdelay(5);
++
++	buf[0] = 0xA0;
++	buf[1] = 0x03;
++	ret = cst3xx_i2c_read_register(client, buf, 1);
++	if (ret < 0)  return -1;
++
++	if (buf[0] != 0x55) return -1;
++
++	return 0;
++}
++
++
++static void cst3xx_reset_ic(struct cst3xx_ts_data *ts,unsigned int ms)
++{
++
++	unsigned char buf[4];
++	buf[0] = 0xD1;
++	buf[1] = 0x0E;
++	cst3xx_i2c_write(ts->client, buf, 2);
++/*
++	gpio_direction_output(ts->pdata->reset_gpio,0);
++	mdelay(2);
++	gpio_direction_output(ts->pdata->reset_gpio,1);
++*/
++	mdelay(ms);
++}
++
++
++static int cst3xx_write_program_data(struct i2c_client * client,
++		const unsigned char *pdata)
++{
++	int i, ret;
++	unsigned char *i2c_buf;
++	unsigned short eep_addr;
++	int total_kbyte;
++
++	unsigned char temp_buf[8];
++	unsigned short iic_addr;
++	int  j;
++
++
++	i2c_buf = kmalloc(sizeof(unsigned char)*(1024 + 2), GFP_KERNEL);
++	if (i2c_buf == NULL)
++		return -1;
++
++	//make sure fwbin len is N*1K
++	//total_kbyte = len / 1024;
++	total_kbyte = 24;
++	for (i=0; i<total_kbyte; i++) {
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x14;
++		eep_addr = i << 10;		//i * 1024
++		i2c_buf[2] = eep_addr;
++		i2c_buf[3] = eep_addr>>8;
++		ret = cst3xx_i2c_write(client, i2c_buf, 4);
++		if (ret < 0)
++			goto error_out;
++
++		memcpy(i2c_buf, pdata + eep_addr, 1024);
++		for(j=0; j<256; j++) {
++			iic_addr = (j<<2);
++    	temp_buf[0] = (iic_addr+0xA018)>>8;
++    	temp_buf[1] = (iic_addr+0xA018)&0xFF;
++		temp_buf[2] = i2c_buf[iic_addr+0];
++		temp_buf[3] = i2c_buf[iic_addr+1];
++		temp_buf[4] = i2c_buf[iic_addr+2];
++		temp_buf[5] = i2c_buf[iic_addr+3];
++    	      ret = cst3xx_i2c_write(client, temp_buf, 6);
++    		if (ret < 0)
++    			goto error_out;
++		}
++
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x04;
++		i2c_buf[2] = 0xEE;
++		ret = cst3xx_i2c_write(client, i2c_buf, 3);
++		if (ret < 0)
++			goto error_out;
++
++		mdelay(60);
++
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x05;
++		ret = cst3xx_i2c_read_register(client, i2c_buf, 1);
++		if (ret < 0)
++			goto error_out;
++
++		if (i2c_buf[0] != 0x55)
++			goto error_out;
++
++	}
++
++	i2c_buf[0] = 0xA0;
++	i2c_buf[1] = 0x03;
++	i2c_buf[2] = 0x00;
++	ret = cst3xx_i2c_write(client, i2c_buf, 3);
++	if (ret < 0)
++		goto error_out;
++
++	mdelay(8);
++
++	if (i2c_buf != NULL) {
++		kfree(i2c_buf);
++		i2c_buf = NULL;
++	}
++
++	return 0;
++
++error_out:
++	if (i2c_buf != NULL) {
++		kfree(i2c_buf);
++		i2c_buf = NULL;
++	}
++	return -1;
++}
++
++
++static int cst3xx_check_checksum(struct i2c_client * client)
++{
++	int ret;
++	int i;
++	unsigned int  checksum;
++	unsigned int  bin_checksum;
++	unsigned char buf[4];
++	const unsigned char *pData;
++
++	for(i=0; i<5; i++)
++	{
++		buf[0] = 0xA0;
++		buf[1] = 0x00;
++		ret = cst3xx_i2c_read_register(client, buf, 1);
++		if(ret < 0)
++		{
++			mdelay(2);
++			continue;
++		}
++
++		if(buf[0]!=0)
++			break;
++		else
++		mdelay(2);
++	}
++    mdelay(2);
++
++
++    if(buf[0]==0x01)
++	{
++		buf[0] = 0xA0;
++		buf[1] = 0x08;
++		ret = cst3xx_i2c_read_register(client, buf, 4);
++
++		if(ret < 0)	return -1;
++
++		// read chip checksum
++		checksum = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24);
++
++        pData=(unsigned char  *)pcst3xx_update_firmware +24*1024+16;   //7*1024 +512
++		bin_checksum = pData[0] + (pData[1]<<8) + (pData[2]<<16) + (pData[3]<<24);
++
++        printk("  hyn the updated ic checksum is :0x%x. the updating firmware checksum is:0x%x------\n", checksum, bin_checksum);
++
++        if(checksum!=bin_checksum)
++		{
++			printk(" cst3xx hyn check sum error.\n");
++			return -1;
++
++		}
++
++	}
++	else
++	{
++		printk(" cst3xx hyn No checksum.\n");
++		return -1;
++	}
++	return 0;
++}
++
++static int cst3xx_exit_program_mode(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[3];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x06;
++	buf[2] = 0xEE;
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0)
++		return -1;
++
++	mdelay(10);	//wait for restart
++
++
++	return 0;
++}
++
++
++static int cst3xx_update_firmware(struct cst3xx_ts_data *ts, const unsigned char *pdata)
++{
++	int ret;
++	int retry = 0;
++
++	printk(" cst3xx----------upgrade cst3xx begain------------\n");
++	disable_irq(ts->irq);
++	mdelay(20);
++START_FLOW:
++
++#ifdef HYN_UPDATE_FIRMWARE_POWERON_ENABLE
++	close_vcc3v3Power();
++	mdelay(20);
++	open_vcc3v3Power();
++	mdelay(5+retry);
++#else
++	cst3xx_reset_ic(ts,5+retry);
++#endif
++	ret = cst3xx_into_program_mode(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]into program mode failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_erase_program_area(ts->client);
++	if (ret) {
++		printk(" cst3xx[cst3xx]erase main area failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_write_program_data(ts->client, pdata);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]write program data into cstxxx failed.\n");
++		goto err_out;
++	}
++
++    ret =cst3xx_check_checksum(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx] after write program cst3xx_check_checksum failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_exit_program_mode(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]exit program mode failed.\n");
++		goto err_out;
++	}
++
++	cst3xx_reset_ic(ts,20);
++
++	printk(" cst3xx hyn----------cst3xx_update_firmware  end------------\n");
++
++	enable_irq(ts->irq);
++
++	return 0;
++
++err_out:
++	if (retry < 30) {
++		retry++;
++		mdelay(20);
++		goto START_FLOW;
++	}
++	else {
++		enable_irq(ts->irq);
++		return -1;
++	}
++}
++
++
++
++
++/*******************************************************
++Function:
++    get firmware version, ic type...
++Input:
++    client: i2c client
++Output:
++    success: 0
++    fail:	-1
++*******************************************************/
++static int cst3xx_firmware_info(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[28];
++//	unsigned short ic_type, project_id;
++
++
++	buf[0] = 0xD1;
++	buf[1] = 0x01;
++	ret = cst3xx_i2c_write(client, buf, 2);
++	if (ret < 0) return -1;
++
++	mdelay(40);
++
++	buf[0] = 0xD1;
++	buf[1] = 0xFC;
++	ret = cst3xx_i2c_read_register(client, buf, 4);
++	if (ret < 0) return -1;
++
++	//0xCACA0000
++	g_cst3xx_ic_checkcode = buf[3];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[2];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[1];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[0];
++
++	printk("linc cst3xx [cst3xx] the chip g_cst3xx_ic_checkcode:0x%x.\r\n",g_cst3xx_ic_checkcode);
++	
++	mdelay(2);
++	
++	buf[0] = 0xD2;
++	buf[1] = 0x04;
++	ret = cst3xx_i2c_read_register(client, buf, 4);
++	if (ret < 0) return -1;
++	g_cst3xx_ic_type = buf[3];
++	g_cst3xx_ic_type <<= 8;
++	g_cst3xx_ic_type |= buf[2];
++
++	
++	g_cst3xx_ic_project_id = buf[1];
++	g_cst3xx_ic_project_id <<= 8;
++	g_cst3xx_ic_project_id |= buf[0];
++
++	printk("linc cst3xx [cst3xx] the chip ic g_cst3xx_ic_type :0x%x, g_cst3xx_ic_project_id:0x%x\r\n",
++		g_cst3xx_ic_type, g_cst3xx_ic_project_id);
++
++	mdelay(2);
++	
++	buf[0] = 0xD2;
++	buf[1] = 0x08;
++	ret = cst3xx_i2c_read_register(client, buf, 8);
++	if (ret < 0) return -1;	
++
++	g_cst3xx_ic_version = buf[3];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[2];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[1];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[0];
++
++	g_cst3xx_ic_checksum = buf[7];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[6];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[5];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[4];	
++
++	tpd_info.vid = g_cst3xx_ic_version;
++    tpd_info.pid = 0x00;
++
++
++	printk(" cst3xx [cst3xx] the chip ic version:0x%x, checksum:0x%x\r\n",
++		g_cst3xx_ic_version, g_cst3xx_ic_checksum);
++
++	if(g_cst3xx_ic_version==0xA5A5A5A5)
++	{
++		printk(" cst3xx [cst3xx] the chip ic don't have firmware. \n");
++		return -1;
++	}
++	if((g_cst3xx_ic_checkcode&0xffff0000)!=0xCACA0000){
++		printk("linc cst3xx [cst3xx] cst3xx_firmware_info read error .\r\n");
++		return -1;
++	}
++
++    buf[0] = 0xD1;
++	buf[1] = 0x09;
++	ret = cst3xx_i2c_write(client, buf, 2);
++	if (ret < 0) return -1;
++    mdelay(5);
++
++
++	return 0;
++}
++
++static int cst3xx_update_judge( unsigned char *pdata, int strict)
++{
++	unsigned short ic_type, project_id;
++	unsigned int fw_checksum, fw_version;
++	const unsigned int *p;
++	int i;
++	unsigned char *pBuf;
++
++	fw_checksum = 0x55;
++	p = (const unsigned int *)pdata;
++	for (i=0; i<(CST3XX_BIN_SIZE-4); i+=4) {
++		fw_checksum += (*p);
++		p++;
++	}
++
++	if (fw_checksum != (*p)) {
++		printk(" cst3xx[cst3xx]calculated checksum error:0x%x not equal 0x%x.\n", fw_checksum, *p);
++		return -1;	//bad fw, so do not update
++	}
++
++	pBuf = &pdata[CST3XX_BIN_SIZE-16];
++
++	project_id = pBuf[1];
++	project_id <<= 8;
++	project_id |= pBuf[0];
++
++	ic_type = pBuf[3];
++	ic_type <<= 8;
++	ic_type |= pBuf[2];
++
++	fw_version = pBuf[7];
++	fw_version <<= 8;
++	fw_version |= pBuf[6];
++	fw_version <<= 8;
++	fw_version |= pBuf[5];
++	fw_version <<= 8;
++	fw_version |= pBuf[4];
++
++	fw_checksum = pBuf[11];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[10];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[9];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[8];
++
++	printk(" cst3xx[cst3xx]the updating firmware:project_id:0x%04x,ic type:0x%04x,version:0x%x,checksum:0x%x\n",
++			project_id, ic_type, fw_version, fw_checksum);
++
++	if (strict > 0) {
++
++		if (g_cst3xx_ic_checksum != fw_checksum){
++			if (g_cst3xx_ic_version >fw_version){
++				printk("[cst3xx]fw version(0x%x), ic version(0x%x).\n",fw_version, g_cst3xx_ic_version);
++				return -1;
++			}
++		}else{
++			printk("[cst3xx]fw checksum(0x%x), ic checksum(0x%x).\n",fw_checksum, g_cst3xx_ic_checksum);
++			return -1;
++		}
++	}
++
++	return 0;
++}
++static int cst3xx_boot_update_fw(struct cst3xx_ts_data *ts,  unsigned char *pdata)
++{
++	int ret;
++	int retry = 0;
++	int flag = 0;
++
++	while (retry++ < 3) {
++		ret = cst3xx_firmware_info(ts->client);
++		if (ret == 0) {
++			flag = 1;
++			break;
++		}
++	}
++
++	if (flag == 1) {
++		ret = cst3xx_update_judge(pdata, 1);
++		if (ret < 0) {
++			printk(" cst3xx[cst3xx] no need to update firmware.\n");
++			return 0;
++		}
++	}
++
++	ret = cst3xx_update_firmware(ts, pdata);
++	if (ret < 0){
++		printk(" cst3xx [cst3xx] update firmware failed.\n");
++		return -1;
++	}
++
++    mdelay(50);
++
++	ret = cst3xx_firmware_info(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx [cst3xx] after update read version and checksum fail.\n");
++		return -1;
++	}
++
++	return 0;
++}
++
++
++/*******************************Chose which I2C interface ********************************************/
++
++#if USE_ANALOG_I2C
++
++#define I2CSDA  GPIO_PC(27)
++#define I2CSCL   GPIO_PC(26)
++
++#define I2CSDA_HIGH gpio_direction_output(GPIO_PC(27),1)
++#define I2CSDA_LOW  gpio_direction_output(GPIO_PC(27),0)
++
++#define I2CSCL_HIGH  gpio_direction_output(GPIO_PC(26),1)
++#define I2CSCL_LOW  gpio_direction_output(GPIO_PC(26),0)
++
++#define delay_data 2
++static void iicstart(void)
++{
++     I2CSDA_HIGH;
++      I2CSCL_HIGH;
++      __udelay(2);
++      I2CSDA_LOW;
++      __udelay(2);
++       I2CSCL_LOW;
++       __udelay(2);
++}
++static void iicstop(void)
++{
++     I2CSDA_LOW;
++     I2CSCL_HIGH;
++     __udelay(2);
++     I2CSDA_HIGH;
++     __udelay(2);
++
++}
++static unsigned char waitack(void)
++{
++   u8 ucErrTime=0;
++
++    gpio_direction_input(GPIO_PC(27));
++   //  __udelay(2);
++
++  //  I2CSDA_HIGH;
++  //  __udelay(2);
++     I2CSCL_HIGH;
++     __udelay(2);
++
++    while(__gpio_get_value(GPIO_PC(27)))
++    {
++        ucErrTime++;
++     //   printk("time out ++ \n");
++        if(ucErrTime>250)
++         {
++                iicstop();
++                return 1;
++        }
++    }
++    I2CSCL_LOW;
++     __udelay(2);
++    return 0;
++}
++static void sendack(void)
++{
++     I2CSCL_LOW;
++     __udelay(delay_data);
++     I2CSDA_LOW;
++     __udelay(delay_data);
++
++     I2CSCL_HIGH;
++     __udelay(delay_data);
++     I2CSCL_LOW;
++     __udelay(delay_data);
++
++}
++static void sendnotack(void)
++{
++     I2CSCL_LOW;
++     __udelay(delay_data);
++    I2CSDA_HIGH;
++    __udelay(delay_data);
++
++    I2CSCL_HIGH;
++    __udelay(delay_data);
++    I2CSCL_LOW;
++    __udelay(delay_data);
++}
++static void iicsendbyte(unsigned char ch)
++{
++     unsigned char i;
++     I2CSCL_LOW;
++     for(i = 0;i<8;i++)
++     {
++          if(ch&0x80)
++          {
++              I2CSDA_HIGH;
++          }
++          else
++          {
++              I2CSDA_LOW;
++          }
++           __udelay(delay_data);
++          ch<<=1;
++          I2CSCL_HIGH;
++          __udelay(delay_data);
++               I2CSCL_LOW;
++          __udelay(delay_data);
++     }
++}
++static unsigned char iicreceivebyte(unsigned char ack)
++{
++    unsigned char i=8;
++    unsigned char ddata=0;
++
++    gpio_direction_input(GPIO_PC(27));
++    __udelay(delay_data);
++
++     for(i = 0;i<8;i++)
++     {
++         I2CSCL_LOW;
++         __udelay(delay_data);
++         I2CSCL_HIGH;
++         __udelay(delay_data);
++
++         ddata<<=1;
++         if(gpio_get_value(GPIO_PC(27))) ddata++;
++    }
++
++    if(!ack)
++        sendnotack();
++     else
++        sendack();
++
++    return ddata;
++}
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++    int count = len;
++     iicstart();
++     __udelay(delay_data);
++
++/*
++	 iicsendbyte( (0x1a<<1) | 0);
++     __udelay(delay_data);
++
++     if(waitack())
++     {
++        iicstop();
++                printk(" cst3xx_i2c_read wait ack timeoue \n");
++        return 1;
++     }
++
++     iicsendbyte(buf[0]);
++     __udelay(delay_data);
++     waitack();
++     __udelay(delay_data);
++*/
++     iicstart();
++     __udelay(delay_data);
++
++     iicsendbyte((0x1a << 1 ) | 1);
++     __udelay(delay_data);
++     if(waitack())
++     {
++        iicstop();
++                printk(" cst3xx_i2c_read wait ack timeoue \n");
++        return 1;
++     }
++     __udelay(delay_data);
++
++    while(count)
++    {
++         if(count == 1) *buf = iicreceivebyte(0);
++         else *buf = iicreceivebyte(1);
++         count --;
++         buf++;
++    }
++     iicstop();
++     __udelay(delay_data);
++     return 0;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++     int count = len;
++      iicstart();
++   //   __udelay(delay_data);
++
++      iicsendbyte((0x1A << 1) | 0);
++//      __udelay(delay_data);
++
++     if(waitack())
++     {
++        iicstop();
++        printk(" cst3xx_i2c_write send address wait ack timeoue \n");
++        return 1;
++     }
++
++      while(count--)
++      {
++            iicsendbyte(*(buf++));
++            __udelay(delay_data);
++             if(waitack())
++             {
++                iicstop();
++               printk(" cst3xx_i2c_write wait ack timeoue \n");
++                return 1;
++             }
++            __udelay(delay_data);
++      }
++
++      iicstop();
++      __udelay(delay_data);
++
++	return 0;
++}
++
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	int ret = -1;
++
++    ret = cst3xx_i2c_write(client, buf, 2);
++    if(ret) printk("failed to write cst3xx\n");
++
++    ret = cst3xx_i2c_read(client, buf, len);
++    if(ret) printk("failed to write cst3xx\n");
++    return ret;
++}
++
++#elif  USE_LOWEST_I2CA
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++	int ret = -1;
++	int retries = 0;
++
++	while (retries < 2) {
++		ret = i2c_master_recv(client, buf, len);
++		if(ret<=0)
++		    retries++;
++        else
++            break;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++	int ret = -1;
++	int retries = 0;
++
++	while (retries < 2) {
++		ret = i2c_master_send(client, buf, len);
++		if(ret<=0)
++		    retries++;
++        else
++            break;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	int ret = -1;
++
++    ret = cst3xx_i2c_write(client, buf, 2);
++
++    ret = cst3xx_i2c_read(client, buf, len);
++
++    return ret;
++}
++
++#elif USE_HIGHEST_I2CA
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++	struct i2c_msg msg;
++	int ret = -1;
++	int retries = 0;
++
++	msg.flags |= I2C_M_RD;
++	msg.addr   = client->addr;
++	msg.len    = len;
++	msg.buf    = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == 1)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++/*******************************************************
++Function:
++    read data from register.
++Input:
++    buf: first two byte is register addr, then read data store into buf
++    len: length of data that to read
++Output:
++    success: number of messages
++    fail:	negative errno
++*******************************************************/
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	struct i2c_msg msgs[2];
++	int ret = -1;
++	int retries = 0;
++
++	msgs[0].flags = 0;
++	msgs[0].addr  = client->addr;
++	msgs[0].len   = 2;
++	msgs[0].buf   = buf;
++
++	msgs[1].flags |= I2C_M_RD;
++	msgs[1].addr   = client->addr;
++	msgs[1].len    = len;
++	msgs[1].buf    = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, msgs, 2);
++		if(ret == 2)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++	struct i2c_msg msg;
++	int ret = -1;
++	int retries = 0;
++
++	msg.flags = 0;
++	msg.addr  = client->addr;
++	msg.len   = len;
++	msg.buf   = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == 1)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++#else
++#endif
++/*********************************i2c end********************************/
++
++
++static int cst3xx_i2c_test(struct i2c_client *client)
++{
++	int retry = 0;
++	int ret;
++	unsigned char buf[4];
++
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	while (retry++ < 5) {
++		ret = cst3xx_i2c_write(client, buf, 2);
++		if (ret == 0)
++			return ret;
++
++		mdelay(2);
++	}
++
++    if(retry==5) printk(" cst3xx hyn I2C TEST error.ret:%d;\n", ret);
++
++	return ret;
++}
++
++
++static void cst3xx_reset(struct cst3xx_ts_data *ts) {
++	if(gpio_is_valid(ts->pdata->reset_gpio)) {
++		gpio_direction_output(ts->pdata->reset_gpio,0);
++		mdelay(100);
++		gpio_direction_output(ts->pdata->reset_gpio,1);
++		mdelay(100);
++	}
++}
++/****************************  basic communication end*******************************/
++
++
++static void cst3xx_touch_report(struct cst3xx_ts_data *ts)
++{
++	unsigned char buf[30];
++	unsigned char i2c_buf[8];
++	unsigned char key_status, key_id = 0, finger_id, sw;
++	unsigned int  input_x = 0;
++	unsigned int  input_y = 0;
++	unsigned int  input_w = 0;
++	unsigned int input_x_delta = 0;
++	unsigned int input_y_delta = 0;
++       unsigned char cnt_up, cnt_down;
++	int   i, ret, idx;
++	int cnt, i2c_len;
++
++	int  len_1, len_2;
++
++      key_status = 0;
++
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	ret = cst3xx_i2c_read_register(ts->client, buf, 7);
++	if(ret < 0) {
++		printk("  iic read touch point data failed.\n");
++		goto OUT_PROCESS;
++	}
++  //   printk(" read buf : buf[0]: %x ,buf[1]: %x ,buf[2]: %x, buf[3]: %x,buf[4]: %x ,buf[5]: %x ,buf[6]: %x, buf[7]: %x,\n",buf[0],buf[1],buf[2],buf[3],buf[4],buf[5],buf[6],buf[7]);
++
++	if(buf[6] != 0xAB) {
++		printk(KERN_INFO " data is not valid..\r\n");
++		goto OUT_PROCESS;
++	}
++
++    	cnt = buf[5] & 0x7F;
++	if(cnt > 1) goto OUT_PROCESS;
++	else if(cnt==0)     goto CLR_POINT;
++
++	if(cnt == 0x01) {
++		goto FINGER_PROCESS;
++	}
++
++FINGER_PROCESS:
++
++    /*
++     *  sw: buf[0] low 4 bit
++     *  x pos:  buf[1] low 4 bit | buf[3] high 4 bit
++     *  y pos:  buf[2] low 4 bit | buf[3] low  4 bit
++     *  z press : buf[4]
++     *  finger_id:buf[0] high 4 bit
++     */
++	i2c_buf[0] = 0xD0;
++	i2c_buf[1] = 0x00;
++	i2c_buf[2] = 0xAB;
++
++	ret = cst3xx_i2c_write(ts->client, i2c_buf, 3);
++	if(ret < 0) {
++		printk(" cst3xx hyn send read touch info ending failed.\r\n");
++		cst3xx_reset_ic(ts,20);
++              goto END;
++	}
++
++	idx = 0;
++       cnt_up = 0;
++       cnt_down = 0;
++	input_x = (unsigned int)((buf[idx + 1] << 4) | ((buf[idx + 3] >> 4) & 0x0F));
++	input_y = (unsigned int)((buf[idx + 2] << 4) | (buf[idx + 3] & 0x0F));
++	input_w = (unsigned int)(buf[idx + 4]);
++	sw = (buf[idx] & 0x0F) >> 1;
++	finger_id = (buf[idx] >> 4) & 0x0F;
++
++    printk(" no handle : cst3xxPoint x:%d, y:%d, w:%d, id:%d, sw:%d. \n", input_x, input_y, input_w,finger_id, sw);
++
++	input_x=input_x*CST3XX_MAX_X/360;
++	input_y=input_y*CST3XX_MAX_Y/800;
++	
++	if(input_x >= CST3XX_MAX_X) input_x = CST3XX_MAX_X;
++	if(input_y >= CST3XX_MAX_Y) input_y = CST3XX_MAX_Y;
++
++//	input_x = CST3XX_MAX_X-input_x;
++//	input_y = CST3XX_MAX_Y-input_y;
++
++#ifdef 0//HYN_DRAW_POINT
++	if(input_x > 300){
++		input_x_delta = input_x - (CST3XX_MAX_X/2);
++		input_x = input_x + input_x_delta/((CST3XX_MAX_X/2)/20);
++		if(input_x > CST3XX_MAX_X) input_x = CST3XX_MAX_X;
++		}
++	if(input_x < 40){
++		input_x_delta = (CST3XX_MAX_X/2) - input_x;
++		input_x = input_x - input_x_delta/((CST3XX_MAX_X/2)/12);
++		if(input_x < 0) input_x = 0;
++		}
++	if(input_y > 760){
++		input_y_delta = input_y - (CST3XX_MAX_Y/2);
++		input_y = input_y + input_y_delta/((CST3XX_MAX_Y/2)/12);
++		if(input_y > CST3XX_MAX_Y) input_y = CST3XX_MAX_Y;
++		}
++	if(input_y < 40){
++		input_y_delta = (CST3XX_MAX_Y/2) - input_y;
++		input_y = input_y - input_y_delta/((CST3XX_MAX_Y/2)/25);
++		if(input_y < 0) input_y = 0;
++		}
++#endif
++
++    printk(" handle : cst3xxPoint x:%d, y:%d, w:%d, id:%d, sw:%d. \n\n", input_x, input_y, input_w,finger_id, sw);
++
++	if (sw == 0x03 ) {
++         	   if((input_x > x_temp_pos + ERROR_TOUCH) || (input_x < x_temp_pos -ERROR_TOUCH)  || (input_y > y_temp_pos + ERROR_TOUCH) || (input_y < y_temp_pos -ERROR_TOUCH))
++               {
++          //           printk(" REPORT TOUCH DOWM Handle \n");
++                     x_temp_pos = input_x;
++                     y_temp_pos = input_y;
++                     input_report_key(ts->input_dev, BTN_TOUCH, 1);
++    		        input_report_abs(ts->input_dev, ABS_X, input_x);
++    	               input_report_abs(ts->input_dev, ABS_Y, input_y);
++    		        input_report_abs(ts->input_dev, ABS_PRESSURE, 1);
++    		        input_sync(ts->input_dev);
++                 }
++                cnt_down++;
++       }
++      else if(sw == 0) {
++                cnt_up++;
++        }
++
++        if((cnt_up>0) && (cnt_down==0) ){
++      //      printk(" REPORT TOUCH UP Handle \n");
++            x_temp_pos = 0;
++            y_temp_pos = 0;
++            input_report_key(ts->input_dev, BTN_TOUCH, 0);
++            input_report_abs(ts->input_dev, ABS_PRESSURE, 0);
++            input_mt_sync(ts->input_dev);
++        }
++       input_sync(ts->input_dev);
++	goto END;
++CLR_POINT:
++
++	    input_report_key(ts->input_dev, BTN_TOUCH, 0);
++           input_mt_sync(ts->input_dev);
++           input_sync(ts->input_dev);
++
++OUT_PROCESS:
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	buf[2] = 0xAB;
++	ret = cst3xx_i2c_write(ts->client, buf, 3);
++	if (ret < 0) {
++		printk("  send read touch info ending failed.\n");
++		cst3xx_reset_ic(ts,20);
++	}
++END:
++	return;
++}
++
++
++/******************************* irq handle  begin************************************/
++static void cst3xx_work_handler(struct work_struct *work)
++{
++	struct cst3xx_ts_data *cst3xx_ts = container_of(work, struct cst3xx_ts_data, work);
++	int ret = 0;
++    /******************here handle touch *******************/
++    //    printk(KERN_INFO "-----------enter cst3xx_work_handler------------\n");
++         cst3xx_touch_report(cst3xx_ts);
++	  enable_irq(cst3xx_ts->irq);
++}
++
++static irqreturn_t cst3xx_ts_irq_handler(int irq, void *dev_id)
++{
++	struct cst3xx_ts_data *ts = dev_id;
++
++   //    printk( KERN_INFO "-----------enter cst3xx_ts_irq_handler------------\n");
++
++	disable_irq_nosync(ts->irq);//use in interrupt,disable_irq will make dead lock.
++
++	if (!work_pending(&ts->work)) {
++		queue_work(ts->workqueue, &ts->work);
++	//    queue_delayed_work(ts->workqueue,&ts->dwork,1);//10ms * x
++	} else {
++		enable_irq(ts->irq);
++	}
++
++	return IRQ_HANDLED;
++}
++/******************************* irq handle  end************************************/
++
++static int cst3xx_ts_probe(struct i2c_client *client,
++					const struct i2c_device_id *id)
++{
++       printk( KERN_INFO "Enter cst3xx_ts_probe -------------------\n");
++
++       int ret;
++	struct cst3xx_ts_data *ts;
++
++	struct cst3xx_platform_data *pdata = (struct cst3xx_platform_data*)client->dev.platform_data;
++	struct input_dev *input_dev;
++	int error;
++
++#if USE_ANALOG_I2C
++        if (gpio_is_valid(I2CSDA))
++        {
++            gpio_free(I2CSDA);
++            ret = gpio_request(GPIO_PC(27),"I2C1-SDA");
++            if(ret < 0){
++                printk("I2C1-SDA gpio request failed\n");
++                return ret;
++            }
++        }
++         if (gpio_is_valid(I2CSCL))
++        {
++            gpio_free(I2CSCL);
++            ret = gpio_request(GPIO_PC(26),"I2C1-SCL");
++            if(ret < 0){
++                printk("I2C1-SCL gpio request failed\n");
++                return ret;
++            }
++         }
++#endif
++
++      ts = devm_kzalloc(&client->dev, sizeof(*ts), GFP_KERNEL);
++	if (!ts)
++		return -ENOMEM;
++      input_dev = input_allocate_device();
++      if(!input_dev)
++            return -ENOMEM;
++
++      ts->pdata = pdata;
++      ts->client = client;
++      ts->input_dev = input_dev;
++
++	if(client->addr != 0x1A) //check address
++	{
++		client->addr = 0x1A;
++		printk("Crystal_shen:i2c_client_HYN->addr=%d.\n",client->addr);
++
++	}
++
++	if (gpio_is_valid(ts->pdata->int_gpio)) {
++		//error = gpio_request(pdata->int_gpio,"cst3xx gpio irq");
++        	error = gpio_request_one(pdata->int_gpio, GPIOF_IN, "cst3xx gpio irq");
++		if (error < 0) {
++			dev_err(&client->dev, "Failed to request GPIO %d, error %d\n",
++				pdata->int_gpio, error);
++			return error;
++		}
++
++	/*	if (error < 0) {
++			dev_err(&client->dev, "%s:failed to set gpio irq.\n",__func__);
++			return error;
++		}*/
++		ts->irq = gpio_to_irq(pdata->int_gpio);
++             printk(" cst3xx ts -> irq = %d.\n",ts->irq);
++	}
++
++	if (gpio_is_valid(ts->pdata->reset_gpio)) {
++		error = devm_gpio_request(&client->dev, ts->pdata->reset_gpio, NULL);
++		if (error) {
++			dev_err(&client->dev,
++				"Unable to request GPIO pin %d.\n",
++				ts->pdata->reset_gpio);
++				return error;
++		}
++	}
++       cst3xx_reset(ts);
++       printk( KERN_INFO "cst3xx reset -------------------\n");
++       ret =  cst3xx_i2c_test(ts->client);
++       if(ret>=0){
++
++          mdelay(100);
++
++          printk( KERN_INFO "cst3xx test OK -------------------\n");
++#ifdef HYN_UPDATE_FIRMWARE_ENABLE
++	        ret = cst3xx_boot_update_fw(ts,pcst3xx_update_firmware);//
++			if(ret < 0){
++			printk(" cst3xx hyn_boot_update_fw failed.\n");
++			return -1;
++			}
++#endif
++
++       }else{
++          printk( KERN_INFO "cst3xx hyn i2c communication failed.---------------\n");
++		  return -1;
++       }
++
++	input_dev->name = "cst3xxx -touchscreen";
++	input_dev->id.bustype = BUS_I2C;
++	input_dev->dev.parent = &client->dev;
++
++	set_bit(EV_KEY, input_dev->evbit);
++	set_bit(EV_ABS, input_dev->evbit);
++	set_bit(EV_SYN, input_dev->evbit);
++	set_bit(BTN_TOUCH, input_dev->keybit);
++
++    set_bit(ABS_X, input_dev->absbit);
++	set_bit(ABS_Y, input_dev->absbit);
++    set_bit(ABS_PRESSURE, input_dev->absbit);
++
++
++	input_set_abs_params(input_dev, ABS_X, ts->pdata->x_min, ts->pdata->x_max, 0, 0);
++	input_set_abs_params(input_dev, ABS_Y, ts->pdata->y_min, ts->pdata->y_max, 0, 0);
++    input_set_abs_params(input_dev, ABS_PRESSURE, 0, 1, 0 , 0);
++
++  /*     input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR, 0, MAX_AREA, 0, 0);
++       input_set_abs_params(input_dev, ABS_MT_WIDTH_MAJOR, 0, MAX_AREA, 0, 0);
++       input_set_abs_params(input_dev, ABS_MT_POSITION_X, ts->pdata->x_min, ts->pdata->x_max, 0, 0);
++	input_set_abs_params(input_dev, ABS_MT_POSITION_Y, ts->pdata->y_min, ts->pdata->y_max, 0, 0);
++*/
++       error = input_register_device(input_dev);
++	if (error) {
++		dev_err(&client->dev, "Unable to register %s input device\n",
++			input_dev->name);
++		return error;
++	}
++
++  //    INIT_DELAYED_WORK(&ts->dwork, cst3xx_work_handler);
++
++	INIT_WORK(&ts->work, cst3xx_work_handler);
++	ts->workqueue = create_singlethread_workqueue("cst3xx_wq");
++
++	error = devm_request_threaded_irq(&client->dev, client->irq,
++					  NULL,
++					  cst3xx_ts_irq_handler,
++					  IRQF_ONESHOT,
++					  client->name, ts);
++	if (error) {
++		dev_err(&client->dev, "Failed to register interrupt\n");
++		return error;
++	}
++  	error = request_irq(ts->irq,
++				cst3xx_ts_irq_handler,
++				ts->pdata->irqflags,
++				client->dev.driver->name,
++				ts);
++	if (error < 0) {
++		dev_err(&client->dev, "%s: request irq failed\n",__func__);
++		return error;
++	}
++     printk(KERN_INFO "-----------CST3XX probe end ------------\n");
++       return 0;
++}
++
++static int cst3xx_ts_remove(struct i2c_client *client)
++{
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++        free_irq(ts->irq,ts);
++        devm_free_irq(&ts->client->dev, ts->client->irq,ts);
++        destroy_workqueue(ts->workqueue);
++        input_unregister_device(ts->input_dev);
++        devm_gpio_free(&ts->client->dev, ts->pdata->reset_gpio);
++        gpio_free(ts->pdata->int_gpio);
++
++#if USE_ANALOG_I2C
++         gpio_free(I2CSDA);
++        gpio_free(I2CSCL);
++#endif
++
++	return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int cst3xx_ts_suspend(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++
++	if (device_may_wakeup(&client->dev)) {
++		enable_irq_wake(client->irq);
++	} else {
++		disable_irq(client->irq);
++		cst3xx_ts_power(ts, false);//reset
++	}
++
++	return 0;
++}
++
++static int cst3xx_ts_resume(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++
++	if (device_may_wakeup(&client->dev)) {
++		disable_irq_wake(client->irq);
++	} else {
++		cst3xx_ts_power(ts, true);
++		enable_irq(client->irq);
++	}
++	return 0;
++}
++
++#endif
++
++static SIMPLE_DEV_PM_OPS(cst3xx_ts_pm_ops,
++			 cst3xx_ts_suspend, cst3xx_ts_resume);
++
++static const struct i2c_device_id cst3xx_ts_id[] = {
++	{ CST3XX_NAME, 0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, cst3xx_ts_id);
++
++
++#ifdef CONFIG_OF
++static const struct of_device_id cst3xx_ts_dt_ids[] = {
++	{ .compatible = "xxxxx,cst3xx", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, cst3xx_ts_dt_ids);
++#endif
++
++
++static struct i2c_driver cst3xx_ts_driver = {
++	.probe		= cst3xx_ts_probe,
++	.remove		= cst3xx_ts_remove,
++	.id_table	= cst3xx_ts_id,
++	.driver = {
++		.name	= CST3XX_NAME,
++		.owner	= THIS_MODULE,
++		.of_match_table = of_match_ptr(cst3xx_ts_dt_ids),
++		.pm	= &cst3xx_ts_pm_ops,
++	},
++};
++
++module_i2c_driver(cst3xx_ts_driver);
++
++
++MODULE_AUTHOR("Tiben");
++MODULE_DESCRIPTION("SITRONIX CST3XX Touchscreen Controller Driver");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update1/cst3xx_2.c b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update1/cst3xx_2.c
+new file mode 100644
+index 000000000..50f7df826
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update1/cst3xx_2.c
+@@ -0,0 +1,1422 @@
++/*
++ * cst3xx Touchscreen Controller Driver
++ */
++
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/i2c.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of_gpio.h>
++#include <linux/pm_qos.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include <linux/input/cst3xx.h>
++#include <linux/input/hyn_cst3xx_RS659_fw.h>
++#include "../../video/jz_fb_v13/jz_fb.h"
++
++struct st1615_ts_finger {
++	u16 x;
++	u16 y;
++	u8 t;
++	bool is_valid;
++};
++
++struct cst3xx_ts_data {
++	struct i2c_client *client;
++	struct input_dev *input_dev;
++	struct cst3xx_platform_data *pdata;
++	struct work_struct  work;
++       struct delayed_work dwork;
++	struct workqueue_struct *workqueue;
++	int irq;
++};
++
++static int cst3xx_into_program_mode(struct i2c_client * client);
++static int cst3xx_erase_program_area(struct i2c_client * client);
++static void cst3xx_reset_ic(struct cst3xx_ts_data *ts,unsigned int ms);
++static int cst3xx_write_program_data(struct i2c_client * client,const unsigned char *pdata);
++
++static int cst3xx_check_checksum(struct i2c_client * client);
++
++static int cst3xx_exit_program_mode(struct i2c_client * client);
++
++static int cst3xx_update_firmware(struct cst3xx_ts_data *ts, const unsigned char *pdata);
++
++static int cst3xx_firmware_info(struct i2c_client * client);
++
++static int cst3xx_update_judge( unsigned char *pdata, int strict);
++
++static int cst3xx_boot_update_fw(struct cst3xx_ts_data *ts,  unsigned char *pdata);
++
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_test(struct i2c_client *client);
++static void cst3xx_reset(struct cst3xx_ts_data *ts) ;
++extern  void close_vcc3v3Power(void);
++extern  void open_vcc3v3Power(void);
++
++static unsigned char *pcst3xx_update_firmware = (unsigned char *)cst3_fw ; //the updating firmware
++static unsigned int   g_cst3xx_ic_version  = 0;
++static unsigned int   g_cst3xx_ic_checksum = 0;
++static unsigned int   g_cst3xx_ic_checkcode =0;
++static unsigned int   g_cst3xx_ic_project_id  = 0;
++static unsigned int   g_cst3xx_ic_type  = 0;
++
++static unsigned char  report_flag = 0;
++static unsigned int x_temp_pos = 0;
++static unsigned int y_temp_pos = 0;
++
++#define HYN_DRAW_POINT
++
++#define USE_ANALOG_I2C     1 //i2c analog
++//#define USE_HIGHEST_I2CA  1// x1000 highest i2c
++//#define USE_LOWEST_I2CA   1 // x1000 lowest i2c
++#define HYN_UPDATE_FIRMWARE_POWERON_ENABLE
++//#define HYN_UPDATE_FIRMWARE_ENABLE
++
++#pragma pack(1)
++typedef struct
++{
++    u16 pid;                 //product id   //
++    u16 vid;                 //version id   //
++} st_tpd_info;
++#pragma pack()
++
++st_tpd_info tpd_info;
++
++#define CST3XX_BIN_SIZE    (24*1024 + 24)
++#define CST3XX_MAX_X  480
++#define CST3XX_MAX_Y  800
++#define ERROR_TOUCH   1
++
++static void cst3xx_ts_power(struct cst3xx_ts_data *ts, bool poweron)
++{
++	if (gpio_is_valid(ts->pdata->reset_gpio))
++		gpio_direction_output(ts->pdata->reset_gpio, poweron);
++}
++
++static int cst3xx_into_program_mode(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[4];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x01;
++	buf[2] = 0xAA;	//set cmd to enter program mode
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0)  return -1;
++
++	mdelay(2);
++
++	buf[0] = 0xA0;
++	buf[1] = 0x02;	//check whether into program mode
++	ret = cst3xx_i2c_read_register(client, buf, 1);
++	if (ret < 0)  return -1;
++
++	if (buf[0] != 0x55) return -1;
++
++	return 0;
++}
++static int cst3xx_erase_program_area(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[3];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x02;
++	buf[2] = 0x00;		//set cmd to erase main area
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0) return -1;
++
++	mdelay(5);
++
++	buf[0] = 0xA0;
++	buf[1] = 0x03;
++	ret = cst3xx_i2c_read_register(client, buf, 1);
++	if (ret < 0)  return -1;
++
++	if (buf[0] != 0x55) return -1;
++
++	return 0;
++}
++
++
++static void cst3xx_reset_ic(struct cst3xx_ts_data *ts,unsigned int ms)
++{
++
++	unsigned char buf[4];
++	buf[0] = 0xD1;
++	buf[1] = 0x0E;
++	cst3xx_i2c_write(ts->client, buf, 2);
++/*
++	gpio_direction_output(ts->pdata->reset_gpio,0);
++	mdelay(2);
++	gpio_direction_output(ts->pdata->reset_gpio,1);
++*/
++	mdelay(ms);
++}
++
++
++static int cst3xx_write_program_data(struct i2c_client * client,
++		const unsigned char *pdata)
++{
++	int i, ret;
++	unsigned char *i2c_buf;
++	unsigned short eep_addr;
++	int total_kbyte;
++
++	unsigned char temp_buf[8];
++	unsigned short iic_addr;
++	int  j;
++
++
++	i2c_buf = kmalloc(sizeof(unsigned char)*(1024 + 2), GFP_KERNEL);
++	if (i2c_buf == NULL)
++		return -1;
++
++	//make sure fwbin len is N*1K
++	//total_kbyte = len / 1024;
++	total_kbyte = 24;
++	for (i=0; i<total_kbyte; i++) {
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x14;
++		eep_addr = i << 10;		//i * 1024
++		i2c_buf[2] = eep_addr;
++		i2c_buf[3] = eep_addr>>8;
++		ret = cst3xx_i2c_write(client, i2c_buf, 4);
++		if (ret < 0)
++			goto error_out;
++
++		memcpy(i2c_buf, pdata + eep_addr, 1024);
++		for(j=0; j<256; j++) {
++			iic_addr = (j<<2);
++    	temp_buf[0] = (iic_addr+0xA018)>>8;
++    	temp_buf[1] = (iic_addr+0xA018)&0xFF;
++		temp_buf[2] = i2c_buf[iic_addr+0];
++		temp_buf[3] = i2c_buf[iic_addr+1];
++		temp_buf[4] = i2c_buf[iic_addr+2];
++		temp_buf[5] = i2c_buf[iic_addr+3];
++    	      ret = cst3xx_i2c_write(client, temp_buf, 6);
++    		if (ret < 0)
++    			goto error_out;
++		}
++
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x04;
++		i2c_buf[2] = 0xEE;
++		ret = cst3xx_i2c_write(client, i2c_buf, 3);
++		if (ret < 0)
++			goto error_out;
++
++		mdelay(60);
++
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x05;
++		ret = cst3xx_i2c_read_register(client, i2c_buf, 1);
++		if (ret < 0)
++			goto error_out;
++
++		if (i2c_buf[0] != 0x55)
++			goto error_out;
++
++	}
++
++	i2c_buf[0] = 0xA0;
++	i2c_buf[1] = 0x03;
++	i2c_buf[2] = 0x00;
++	ret = cst3xx_i2c_write(client, i2c_buf, 3);
++	if (ret < 0)
++		goto error_out;
++
++	mdelay(8);
++
++	if (i2c_buf != NULL) {
++		kfree(i2c_buf);
++		i2c_buf = NULL;
++	}
++
++	return 0;
++
++error_out:
++	if (i2c_buf != NULL) {
++		kfree(i2c_buf);
++		i2c_buf = NULL;
++	}
++	return -1;
++}
++
++
++static int cst3xx_check_checksum(struct i2c_client * client)
++{
++	int ret;
++	int i;
++	unsigned int  checksum;
++	unsigned int  bin_checksum;
++	unsigned char buf[4];
++	const unsigned char *pData;
++
++	for(i=0; i<5; i++)
++	{
++		buf[0] = 0xA0;
++		buf[1] = 0x00;
++		ret = cst3xx_i2c_read_register(client, buf, 1);
++		if(ret < 0)
++		{
++			mdelay(2);
++			continue;
++		}
++
++		if(buf[0]!=0)
++			break;
++		else
++		mdelay(2);
++	}
++    mdelay(2);
++
++
++    if(buf[0]==0x01)
++	{
++		buf[0] = 0xA0;
++		buf[1] = 0x08;
++		ret = cst3xx_i2c_read_register(client, buf, 4);
++
++		if(ret < 0)	return -1;
++
++		// read chip checksum
++		checksum = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24);
++
++        pData=(unsigned char  *)pcst3xx_update_firmware +24*1024+16;   //7*1024 +512
++		bin_checksum = pData[0] + (pData[1]<<8) + (pData[2]<<16) + (pData[3]<<24);
++
++        printk("  hyn the updated ic checksum is :0x%x. the updating firmware checksum is:0x%x------\n", checksum, bin_checksum);
++
++        if(checksum!=bin_checksum)
++		{
++			printk(" cst3xx hyn check sum error.\n");
++			return -1;
++
++		}
++
++	}
++	else
++	{
++		printk(" cst3xx hyn No checksum.\n");
++		return -1;
++	}
++	return 0;
++}
++
++static int cst3xx_exit_program_mode(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[3];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x06;
++	buf[2] = 0xEE;
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0)
++		return -1;
++
++	mdelay(10);	//wait for restart
++
++
++	return 0;
++}
++
++
++static int cst3xx_update_firmware(struct cst3xx_ts_data *ts, const unsigned char *pdata)
++{
++	int ret;
++	int retry = 0;
++
++	printk(" cst3xx----------upgrade cst3xx begain------------\n");
++	disable_irq(ts->irq);
++	mdelay(20);
++START_FLOW:
++
++#ifdef HYN_UPDATE_FIRMWARE_POWERON_ENABLE
++	close_vcc3v3Power();
++	mdelay(20);
++	open_vcc3v3Power();
++	mdelay(5+retry);
++#else
++	cst3xx_reset_ic(ts,5+retry);
++#endif
++	ret = cst3xx_into_program_mode(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]into program mode failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_erase_program_area(ts->client);
++	if (ret) {
++		printk(" cst3xx[cst3xx]erase main area failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_write_program_data(ts->client, pdata);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]write program data into cstxxx failed.\n");
++		goto err_out;
++	}
++
++    ret =cst3xx_check_checksum(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx] after write program cst3xx_check_checksum failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_exit_program_mode(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]exit program mode failed.\n");
++		goto err_out;
++	}
++
++	cst3xx_reset_ic(ts,20);
++
++	printk(" cst3xx hyn----------cst3xx_update_firmware  end------------\n");
++
++	enable_irq(ts->irq);
++
++	return 0;
++
++err_out:
++	if (retry < 30) {
++		retry++;
++		mdelay(20);
++		goto START_FLOW;
++	}
++	else {
++		enable_irq(ts->irq);
++		return -1;
++	}
++}
++
++
++
++
++/*******************************************************
++Function:
++    get firmware version, ic type...
++Input:
++    client: i2c client
++Output:
++    success: 0
++    fail:	-1
++*******************************************************/
++static int cst3xx_firmware_info(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[28];
++//	unsigned short ic_type, project_id;
++
++
++	buf[0] = 0xD1;
++	buf[1] = 0x01;
++	ret = cst3xx_i2c_write(client, buf, 2);
++	if (ret < 0) return -1;
++
++	mdelay(40);
++
++	buf[0] = 0xD1;
++	buf[1] = 0xFC;
++	ret = cst3xx_i2c_read_register(client, buf, 4);
++	if (ret < 0) return -1;
++
++	//0xCACA0000
++	g_cst3xx_ic_checkcode = buf[3];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[2];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[1];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[0];
++
++	printk("linc cst3xx [cst3xx] the chip g_cst3xx_ic_checkcode:0x%x.\r\n",g_cst3xx_ic_checkcode);
++	
++	mdelay(2);
++	
++	buf[0] = 0xD2;
++	buf[1] = 0x04;
++	ret = cst3xx_i2c_read_register(client, buf, 4);
++	if (ret < 0) return -1;
++	g_cst3xx_ic_type = buf[3];
++	g_cst3xx_ic_type <<= 8;
++	g_cst3xx_ic_type |= buf[2];
++
++	
++	g_cst3xx_ic_project_id = buf[1];
++	g_cst3xx_ic_project_id <<= 8;
++	g_cst3xx_ic_project_id |= buf[0];
++
++	printk("linc cst3xx [cst3xx] the chip ic g_cst3xx_ic_type :0x%x, g_cst3xx_ic_project_id:0x%x\r\n",
++		g_cst3xx_ic_type, g_cst3xx_ic_project_id);
++
++	mdelay(2);
++	
++	buf[0] = 0xD2;
++	buf[1] = 0x08;
++	ret = cst3xx_i2c_read_register(client, buf, 8);
++	if (ret < 0) return -1;	
++
++	g_cst3xx_ic_version = buf[3];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[2];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[1];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[0];
++
++	g_cst3xx_ic_checksum = buf[7];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[6];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[5];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[4];	
++
++	tpd_info.vid = g_cst3xx_ic_version;
++    tpd_info.pid = 0x00;
++
++
++	printk(" cst3xx [cst3xx] the chip ic version:0x%x, checksum:0x%x\r\n",
++		g_cst3xx_ic_version, g_cst3xx_ic_checksum);
++
++	if(g_cst3xx_ic_version==0xA5A5A5A5)
++	{
++		printk(" cst3xx [cst3xx] the chip ic don't have firmware. \n");
++		return -1;
++	}
++	if((g_cst3xx_ic_checkcode&0xffff0000)!=0xCACA0000){
++		printk("linc cst3xx [cst3xx] cst3xx_firmware_info read error .\r\n");
++		return -1;
++	}
++
++    buf[0] = 0xD1;
++	buf[1] = 0x09;
++	ret = cst3xx_i2c_write(client, buf, 2);
++	if (ret < 0) return -1;
++    mdelay(5);
++
++
++	return 0;
++}
++
++static int cst3xx_update_judge( unsigned char *pdata, int strict)
++{
++	unsigned short ic_type, project_id;
++	unsigned int fw_checksum, fw_version;
++	const unsigned int *p;
++	int i;
++	unsigned char *pBuf;
++
++	fw_checksum = 0x55;
++	p = (const unsigned int *)pdata;
++	for (i=0; i<(CST3XX_BIN_SIZE-4); i+=4) {
++		fw_checksum += (*p);
++		p++;
++	}
++
++	if (fw_checksum != (*p)) {
++		printk(" cst3xx[cst3xx]calculated checksum error:0x%x not equal 0x%x.\n", fw_checksum, *p);
++		return -1;	//bad fw, so do not update
++	}
++
++	pBuf = &pdata[CST3XX_BIN_SIZE-16];
++
++	project_id = pBuf[1];
++	project_id <<= 8;
++	project_id |= pBuf[0];
++
++	ic_type = pBuf[3];
++	ic_type <<= 8;
++	ic_type |= pBuf[2];
++
++	fw_version = pBuf[7];
++	fw_version <<= 8;
++	fw_version |= pBuf[6];
++	fw_version <<= 8;
++	fw_version |= pBuf[5];
++	fw_version <<= 8;
++	fw_version |= pBuf[4];
++
++	fw_checksum = pBuf[11];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[10];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[9];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[8];
++
++	printk(" cst3xx[cst3xx]the updating firmware:project_id:0x%04x,ic type:0x%04x,version:0x%x,checksum:0x%x\n",
++			project_id, ic_type, fw_version, fw_checksum);
++
++	if (strict > 0) {
++
++		if (g_cst3xx_ic_checksum != fw_checksum){
++			if (g_cst3xx_ic_version >fw_version){
++				printk("[cst3xx]fw version(0x%x), ic version(0x%x).\n",fw_version, g_cst3xx_ic_version);
++				return -1;
++			}
++		}else{
++			printk("[cst3xx]fw checksum(0x%x), ic checksum(0x%x).\n",fw_checksum, g_cst3xx_ic_checksum);
++			return -1;
++		}
++	}
++
++	return 0;
++}
++static int cst3xx_boot_update_fw(struct cst3xx_ts_data *ts,  unsigned char *pdata)
++{
++	int ret;
++	int retry = 0;
++	int flag = 0;
++
++	while (retry++ < 3) {
++		ret = cst3xx_firmware_info(ts->client);
++		if (ret == 0) {
++			flag = 1;
++			break;
++		}
++	}
++
++	if (flag == 1) {
++		ret = cst3xx_update_judge(pdata, 1);
++		if (ret < 0) {
++			printk(" cst3xx[cst3xx] no need to update firmware.\n");
++			return 0;
++		}
++	}
++
++	ret = cst3xx_update_firmware(ts, pdata);
++	if (ret < 0){
++		printk(" cst3xx [cst3xx] update firmware failed.\n");
++		return -1;
++	}
++
++    mdelay(50);
++
++	ret = cst3xx_firmware_info(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx [cst3xx] after update read version and checksum fail.\n");
++		return -1;
++	}
++
++	return 0;
++}
++
++
++/*******************************Chose which I2C interface ********************************************/
++
++#if USE_ANALOG_I2C
++
++#define I2CSDA  GPIO_PC(27)
++#define I2CSCL   GPIO_PC(26)
++
++#define I2CSDA_HIGH gpio_direction_output(GPIO_PC(27),1)
++#define I2CSDA_LOW  gpio_direction_output(GPIO_PC(27),0)
++
++#define I2CSCL_HIGH  gpio_direction_output(GPIO_PC(26),1)
++#define I2CSCL_LOW  gpio_direction_output(GPIO_PC(26),0)
++
++#define delay_data 2
++static void iicstart(void)
++{
++     I2CSDA_HIGH;
++      I2CSCL_HIGH;
++      __udelay(2);
++      I2CSDA_LOW;
++      __udelay(2);
++       I2CSCL_LOW;
++       __udelay(2);
++}
++static void iicstop(void)
++{
++     I2CSDA_LOW;
++     I2CSCL_HIGH;
++     __udelay(2);
++     I2CSDA_HIGH;
++     __udelay(2);
++
++}
++static unsigned char waitack(void)
++{
++   u8 ucErrTime=0;
++
++    gpio_direction_input(GPIO_PC(27));
++   //  __udelay(2);
++
++  //  I2CSDA_HIGH;
++  //  __udelay(2);
++     I2CSCL_HIGH;
++     __udelay(2);
++
++    while(__gpio_get_value(GPIO_PC(27)))
++    {
++        ucErrTime++;
++     //   printk("time out ++ \n");
++        if(ucErrTime>250)
++         {
++                iicstop();
++                return 1;
++        }
++    }
++    I2CSCL_LOW;
++     __udelay(2);
++    return 0;
++}
++static void sendack(void)
++{
++     I2CSCL_LOW;
++     __udelay(delay_data);
++     I2CSDA_LOW;
++     __udelay(delay_data);
++
++     I2CSCL_HIGH;
++     __udelay(delay_data);
++     I2CSCL_LOW;
++     __udelay(delay_data);
++
++}
++static void sendnotack(void)
++{
++     I2CSCL_LOW;
++     __udelay(delay_data);
++    I2CSDA_HIGH;
++    __udelay(delay_data);
++
++    I2CSCL_HIGH;
++    __udelay(delay_data);
++    I2CSCL_LOW;
++    __udelay(delay_data);
++}
++static void iicsendbyte(unsigned char ch)
++{
++     unsigned char i;
++     I2CSCL_LOW;
++     for(i = 0;i<8;i++)
++     {
++          if(ch&0x80)
++          {
++              I2CSDA_HIGH;
++          }
++          else
++          {
++              I2CSDA_LOW;
++          }
++           __udelay(delay_data);
++          ch<<=1;
++          I2CSCL_HIGH;
++          __udelay(delay_data);
++               I2CSCL_LOW;
++          __udelay(delay_data);
++     }
++}
++static unsigned char iicreceivebyte(unsigned char ack)
++{
++    unsigned char i=8;
++    unsigned char ddata=0;
++
++    gpio_direction_input(GPIO_PC(27));
++    __udelay(delay_data);
++
++     for(i = 0;i<8;i++)
++     {
++         I2CSCL_LOW;
++         __udelay(delay_data);
++         I2CSCL_HIGH;
++         __udelay(delay_data);
++
++         ddata<<=1;
++         if(gpio_get_value(GPIO_PC(27))) ddata++;
++    }
++
++    if(!ack)
++        sendnotack();
++     else
++        sendack();
++
++    return ddata;
++}
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++    int count = len;
++     iicstart();
++     __udelay(delay_data);
++
++/*
++	 iicsendbyte( (0x1a<<1) | 0);
++     __udelay(delay_data);
++
++     if(waitack())
++     {
++        iicstop();
++                printk(" cst3xx_i2c_read wait ack timeoue \n");
++        return 1;
++     }
++
++     iicsendbyte(buf[0]);
++     __udelay(delay_data);
++     waitack();
++     __udelay(delay_data);
++*/
++     iicstart();
++     __udelay(delay_data);
++
++     iicsendbyte((0x1a << 1 ) | 1);
++     __udelay(delay_data);
++     if(waitack())
++     {
++        iicstop();
++                printk(" cst3xx_i2c_read wait ack timeoue \n");
++        return 1;
++     }
++     __udelay(delay_data);
++
++    while(count)
++    {
++         if(count == 1) *buf = iicreceivebyte(0);
++         else *buf = iicreceivebyte(1);
++         count --;
++         buf++;
++    }
++     iicstop();
++     __udelay(delay_data);
++     return 0;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++     int count = len;
++      iicstart();
++   //   __udelay(delay_data);
++
++      iicsendbyte((0x1A << 1) | 0);
++//      __udelay(delay_data);
++
++     if(waitack())
++     {
++        iicstop();
++        printk(" cst3xx_i2c_write send address wait ack timeoue \n");
++        return 1;
++     }
++
++      while(count--)
++      {
++            iicsendbyte(*(buf++));
++            __udelay(delay_data);
++             if(waitack())
++             {
++                iicstop();
++               printk(" cst3xx_i2c_write wait ack timeoue \n");
++                return 1;
++             }
++            __udelay(delay_data);
++      }
++
++      iicstop();
++      __udelay(delay_data);
++
++	return 0;
++}
++
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	int ret = -1;
++
++    ret = cst3xx_i2c_write(client, buf, 2);
++    if(ret) printk("failed to write cst3xx\n");
++
++    ret = cst3xx_i2c_read(client, buf, len);
++    if(ret) printk("failed to write cst3xx\n");
++    return ret;
++}
++
++#elif  USE_LOWEST_I2CA
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++	int ret = -1;
++	int retries = 0;
++
++	while (retries < 2) {
++		ret = i2c_master_recv(client, buf, len);
++		if(ret<=0)
++		    retries++;
++        else
++            break;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++	int ret = -1;
++	int retries = 0;
++
++	while (retries < 2) {
++		ret = i2c_master_send(client, buf, len);
++		if(ret<=0)
++		    retries++;
++        else
++            break;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	int ret = -1;
++
++    ret = cst3xx_i2c_write(client, buf, 2);
++
++    ret = cst3xx_i2c_read(client, buf, len);
++
++    return ret;
++}
++
++#elif USE_HIGHEST_I2CA
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++	struct i2c_msg msg;
++	int ret = -1;
++	int retries = 0;
++
++	msg.flags |= I2C_M_RD;
++	msg.addr   = client->addr;
++	msg.len    = len;
++	msg.buf    = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == 1)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++/*******************************************************
++Function:
++    read data from register.
++Input:
++    buf: first two byte is register addr, then read data store into buf
++    len: length of data that to read
++Output:
++    success: number of messages
++    fail:	negative errno
++*******************************************************/
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	struct i2c_msg msgs[2];
++	int ret = -1;
++	int retries = 0;
++
++	msgs[0].flags = 0;
++	msgs[0].addr  = client->addr;
++	msgs[0].len   = 2;
++	msgs[0].buf   = buf;
++
++	msgs[1].flags |= I2C_M_RD;
++	msgs[1].addr   = client->addr;
++	msgs[1].len    = len;
++	msgs[1].buf    = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, msgs, 2);
++		if(ret == 2)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++	struct i2c_msg msg;
++	int ret = -1;
++	int retries = 0;
++
++	msg.flags = 0;
++	msg.addr  = client->addr;
++	msg.len   = len;
++	msg.buf   = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == 1)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++#else
++#endif
++/*********************************i2c end********************************/
++
++
++static int cst3xx_i2c_test(struct i2c_client *client)
++{
++	int retry = 0;
++	int ret;
++	unsigned char buf[4];
++
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	while (retry++ < 5) {
++		ret = cst3xx_i2c_write(client, buf, 2);
++		if (ret == 0)
++			return ret;
++
++		mdelay(2);
++	}
++
++    if(retry==5) printk(" cst3xx hyn I2C TEST error.ret:%d;\n", ret);
++
++	return ret;
++}
++
++
++static void cst3xx_reset(struct cst3xx_ts_data *ts) {
++	if(gpio_is_valid(ts->pdata->reset_gpio)) {
++		gpio_direction_output(ts->pdata->reset_gpio,0);
++		mdelay(100);
++		gpio_direction_output(ts->pdata->reset_gpio,1);
++		mdelay(100);
++	}
++}
++/****************************  basic communication end*******************************/
++
++
++static void cst3xx_touch_report(struct cst3xx_ts_data *ts)
++{
++	unsigned char buf[30];
++	unsigned char i2c_buf[8];
++	unsigned char key_status, key_id = 0, finger_id, sw;
++	unsigned int  input_x = 0;
++	unsigned int  input_y = 0;
++	unsigned int  input_w = 0;
++	unsigned int input_x_delta = 0;
++	unsigned int input_y_delta = 0;
++       unsigned char cnt_up, cnt_down;
++	int   i, ret, idx;
++	int cnt, i2c_len;
++
++	int  len_1, len_2;
++
++      key_status = 0;
++
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	ret = cst3xx_i2c_read_register(ts->client, buf, 7);
++	if(ret < 0) {
++		printk("  iic read touch point data failed.\n");
++		goto OUT_PROCESS;
++	}
++  //   printk(" read buf : buf[0]: %x ,buf[1]: %x ,buf[2]: %x, buf[3]: %x,buf[4]: %x ,buf[5]: %x ,buf[6]: %x, buf[7]: %x,\n",buf[0],buf[1],buf[2],buf[3],buf[4],buf[5],buf[6],buf[7]);
++
++	if(buf[6] != 0xAB) {
++		printk(KERN_INFO " data is not valid..\r\n");
++		goto OUT_PROCESS;
++	}
++
++    	cnt = buf[5] & 0x7F;
++	if(cnt > 1) goto OUT_PROCESS;
++	else if(cnt==0)     goto CLR_POINT;
++
++	if(cnt == 0x01) {
++		goto FINGER_PROCESS;
++	}
++
++FINGER_PROCESS:
++
++    /*
++     *  sw: buf[0] low 4 bit
++     *  x pos:  buf[1] low 4 bit | buf[3] high 4 bit
++     *  y pos:  buf[2] low 4 bit | buf[3] low  4 bit
++     *  z press : buf[4]
++     *  finger_id:buf[0] high 4 bit
++     */
++	i2c_buf[0] = 0xD0;
++	i2c_buf[1] = 0x00;
++	i2c_buf[2] = 0xAB;
++
++	ret = cst3xx_i2c_write(ts->client, i2c_buf, 3);
++	if(ret < 0) {
++		printk(" cst3xx hyn send read touch info ending failed.\r\n");
++		cst3xx_reset_ic(ts,20);
++              goto END;
++	}
++
++	idx = 0;
++       cnt_up = 0;
++       cnt_down = 0;
++	input_x = (unsigned int)((buf[idx + 1] << 4) | ((buf[idx + 3] >> 4) & 0x0F));
++	input_y = (unsigned int)((buf[idx + 2] << 4) | (buf[idx + 3] & 0x0F));
++	input_w = (unsigned int)(buf[idx + 4]);
++	sw = (buf[idx] & 0x0F) >> 1;
++	finger_id = (buf[idx] >> 4) & 0x0F;
++
++    printk(" no handle : cst3xxPoint x:%d, y:%d, w:%d, id:%d, sw:%d. \n", input_x, input_y, input_w,finger_id, sw);
++
++//	input_x=input_x*CST3XX_MAX_X/268;
++//	input_y=input_y*CST3XX_MAX_Y/800;
++	
++//	if(input_x >= CST3XX_MAX_X) input_x = CST3XX_MAX_X;
++//	if(input_y >= CST3XX_MAX_Y) input_y = CST3XX_MAX_Y;
++
++//	input_x = CST3XX_MAX_X-input_x;
++//	input_y = CST3XX_MAX_Y-input_y;
++
++#ifdef 0//HYN_DRAW_POINT
++	if(input_x > 300){
++		input_x_delta = input_x - (CST3XX_MAX_X/2);
++		input_x = input_x + input_x_delta/((CST3XX_MAX_X/2)/20);
++		if(input_x > CST3XX_MAX_X) input_x = CST3XX_MAX_X;
++		}
++	if(input_x < 40){
++		input_x_delta = (CST3XX_MAX_X/2) - input_x;
++		input_x = input_x - input_x_delta/((CST3XX_MAX_X/2)/12);
++		if(input_x < 0) input_x = 0;
++		}
++	if(input_y > 760){
++		input_y_delta = input_y - (CST3XX_MAX_Y/2);
++		input_y = input_y + input_y_delta/((CST3XX_MAX_Y/2)/12);
++		if(input_y > CST3XX_MAX_Y) input_y = CST3XX_MAX_Y;
++		}
++	if(input_y < 40){
++		input_y_delta = (CST3XX_MAX_Y/2) - input_y;
++		input_y = input_y - input_y_delta/((CST3XX_MAX_Y/2)/25);
++		if(input_y < 0) input_y = 0;
++		}
++#endif
++
++    printk(" handle : cst3xxPoint x:%d, y:%d, w:%d, id:%d, sw:%d. \n\n", input_x, input_y, input_w,finger_id, sw);
++
++	if (sw == 0x03 ) {
++         	   if((input_x > x_temp_pos + ERROR_TOUCH) || (input_x < x_temp_pos -ERROR_TOUCH)  || (input_y > y_temp_pos + ERROR_TOUCH) || (input_y < y_temp_pos -ERROR_TOUCH))
++               {
++          //           printk(" REPORT TOUCH DOWM Handle \n");
++                     x_temp_pos = input_x;
++                     y_temp_pos = input_y;
++                     input_report_key(ts->input_dev, BTN_TOUCH, 1);
++    		        input_report_abs(ts->input_dev, ABS_X, input_x);
++    	               input_report_abs(ts->input_dev, ABS_Y, input_y);
++    		        input_report_abs(ts->input_dev, ABS_PRESSURE, 1);
++    		        input_sync(ts->input_dev);
++                 }
++                cnt_down++;
++       }
++      else if(sw == 0) {
++                cnt_up++;
++        }
++
++        if((cnt_up>0) && (cnt_down==0) ){
++      //      printk(" REPORT TOUCH UP Handle \n");
++            x_temp_pos = 0;
++            y_temp_pos = 0;
++            input_report_key(ts->input_dev, BTN_TOUCH, 0);
++            input_report_abs(ts->input_dev, ABS_PRESSURE, 0);
++            input_mt_sync(ts->input_dev);
++        }
++       input_sync(ts->input_dev);
++	goto END;
++CLR_POINT:
++
++	    input_report_key(ts->input_dev, BTN_TOUCH, 0);
++           input_mt_sync(ts->input_dev);
++           input_sync(ts->input_dev);
++
++OUT_PROCESS:
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	buf[2] = 0xAB;
++	ret = cst3xx_i2c_write(ts->client, buf, 3);
++	if (ret < 0) {
++		printk("  send read touch info ending failed.\n");
++		cst3xx_reset_ic(ts,20);
++	}
++END:
++	return;
++}
++
++
++/******************************* irq handle  begin************************************/
++static void cst3xx_work_handler(struct work_struct *work)
++{
++	struct cst3xx_ts_data *cst3xx_ts = container_of(work, struct cst3xx_ts_data, work);
++	int ret = 0;
++    /******************here handle touch *******************/
++    //    printk(KERN_INFO "-----------enter cst3xx_work_handler------------\n");
++         cst3xx_touch_report(cst3xx_ts);
++	  enable_irq(cst3xx_ts->irq);
++}
++
++static irqreturn_t cst3xx_ts_irq_handler(int irq, void *dev_id)
++{
++	struct cst3xx_ts_data *ts = dev_id;
++
++   //    printk( KERN_INFO "-----------enter cst3xx_ts_irq_handler------------\n");
++
++	disable_irq_nosync(ts->irq);//use in interrupt,disable_irq will make dead lock.
++
++	if (!work_pending(&ts->work)) {
++		queue_work(ts->workqueue, &ts->work);
++	//    queue_delayed_work(ts->workqueue,&ts->dwork,1);//10ms * x
++	} else {
++		enable_irq(ts->irq);
++	}
++
++	return IRQ_HANDLED;
++}
++/******************************* irq handle  end************************************/
++
++static int cst3xx_ts_probe(struct i2c_client *client,
++					const struct i2c_device_id *id)
++{
++       printk( KERN_INFO "Enter cst3xx_ts_probe -------------------\n");
++
++       int ret;
++	struct cst3xx_ts_data *ts;
++
++	struct cst3xx_platform_data *pdata = (struct cst3xx_platform_data*)client->dev.platform_data;
++	struct input_dev *input_dev;
++	int error;
++
++#if USE_ANALOG_I2C
++        if (gpio_is_valid(I2CSDA))
++        {
++            gpio_free(I2CSDA);
++            ret = gpio_request(GPIO_PC(27),"I2C1-SDA");
++            if(ret < 0){
++                printk("I2C1-SDA gpio request failed\n");
++                return ret;
++            }
++        }
++         if (gpio_is_valid(I2CSCL))
++        {
++            gpio_free(I2CSCL);
++            ret = gpio_request(GPIO_PC(26),"I2C1-SCL");
++            if(ret < 0){
++                printk("I2C1-SCL gpio request failed\n");
++                return ret;
++            }
++         }
++#endif
++
++      ts = devm_kzalloc(&client->dev, sizeof(*ts), GFP_KERNEL);
++	if (!ts)
++		return -ENOMEM;
++      input_dev = input_allocate_device();
++      if(!input_dev)
++            return -ENOMEM;
++
++      ts->pdata = pdata;
++      ts->client = client;
++      ts->input_dev = input_dev;
++
++	if(client->addr != 0x1A) //check address
++	{
++		client->addr = 0x1A;
++		printk("Crystal_shen:i2c_client_HYN->addr=%d.\n",client->addr);
++
++	}
++
++	if (gpio_is_valid(ts->pdata->int_gpio)) {
++		//error = gpio_request(pdata->int_gpio,"cst3xx gpio irq");
++        	error = gpio_request_one(pdata->int_gpio, GPIOF_IN, "cst3xx gpio irq");
++		if (error < 0) {
++			dev_err(&client->dev, "Failed to request GPIO %d, error %d\n",
++				pdata->int_gpio, error);
++			return error;
++		}
++
++	/*	if (error < 0) {
++			dev_err(&client->dev, "%s:failed to set gpio irq.\n",__func__);
++			return error;
++		}*/
++		ts->irq = gpio_to_irq(pdata->int_gpio);
++             printk(" cst3xx ts -> irq = %d.\n",ts->irq);
++	}
++
++	if (gpio_is_valid(ts->pdata->reset_gpio)) {
++		error = devm_gpio_request(&client->dev, ts->pdata->reset_gpio, NULL);
++		if (error) {
++			dev_err(&client->dev,
++				"Unable to request GPIO pin %d.\n",
++				ts->pdata->reset_gpio);
++				return error;
++		}
++	}
++       cst3xx_reset(ts);
++       printk( KERN_INFO "cst3xx reset -------------------\n");
++       ret =  cst3xx_i2c_test(ts->client);
++       if(ret>=0){
++
++          mdelay(100);
++
++          printk( KERN_INFO "cst3xx test OK -------------------\n");
++#ifdef HYN_UPDATE_FIRMWARE_ENABLE
++	        ret = cst3xx_boot_update_fw(ts,pcst3xx_update_firmware);//
++			if(ret < 0){
++			printk(" cst3xx hyn_boot_update_fw failed.\n");
++			return -1;
++			}
++#endif
++
++       }else{
++          printk( KERN_INFO "cst3xx hyn i2c communication failed.---------------\n");
++		  return -1;
++       }
++
++	input_dev->name = "cst3xxx -touchscreen";
++	input_dev->id.bustype = BUS_I2C;
++	input_dev->dev.parent = &client->dev;
++
++	set_bit(EV_KEY, input_dev->evbit);
++	set_bit(EV_ABS, input_dev->evbit);
++	set_bit(EV_SYN, input_dev->evbit);
++	set_bit(BTN_TOUCH, input_dev->keybit);
++
++    set_bit(ABS_X, input_dev->absbit);
++	set_bit(ABS_Y, input_dev->absbit);
++    set_bit(ABS_PRESSURE, input_dev->absbit);
++
++
++	input_set_abs_params(input_dev, ABS_X, ts->pdata->x_min, ts->pdata->x_max, 0, 0);
++	input_set_abs_params(input_dev, ABS_Y, ts->pdata->y_min, ts->pdata->y_max, 0, 0);
++    input_set_abs_params(input_dev, ABS_PRESSURE, 0, 1, 0 , 0);
++
++  /*     input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR, 0, MAX_AREA, 0, 0);
++       input_set_abs_params(input_dev, ABS_MT_WIDTH_MAJOR, 0, MAX_AREA, 0, 0);
++       input_set_abs_params(input_dev, ABS_MT_POSITION_X, ts->pdata->x_min, ts->pdata->x_max, 0, 0);
++	input_set_abs_params(input_dev, ABS_MT_POSITION_Y, ts->pdata->y_min, ts->pdata->y_max, 0, 0);
++*/
++       error = input_register_device(input_dev);
++	if (error) {
++		dev_err(&client->dev, "Unable to register %s input device\n",
++			input_dev->name);
++		return error;
++	}
++
++  //    INIT_DELAYED_WORK(&ts->dwork, cst3xx_work_handler);
++
++	INIT_WORK(&ts->work, cst3xx_work_handler);
++	ts->workqueue = create_singlethread_workqueue("cst3xx_wq");
++
++	error = devm_request_threaded_irq(&client->dev, client->irq,
++					  NULL,
++					  cst3xx_ts_irq_handler,
++					  IRQF_ONESHOT,
++					  client->name, ts);
++	if (error) {
++		dev_err(&client->dev, "Failed to register interrupt\n");
++		return error;
++	}
++  	error = request_irq(ts->irq,
++				cst3xx_ts_irq_handler,
++				ts->pdata->irqflags,
++				client->dev.driver->name,
++				ts);
++	if (error < 0) {
++		dev_err(&client->dev, "%s: request irq failed\n",__func__);
++		return error;
++	}
++     printk(KERN_INFO "-----------CST3XX probe end ------------\n");
++       return 0;
++}
++
++static int cst3xx_ts_remove(struct i2c_client *client)
++{
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++        free_irq(ts->irq,ts);
++        devm_free_irq(&ts->client->dev, ts->client->irq,ts);
++        destroy_workqueue(ts->workqueue);
++        input_unregister_device(ts->input_dev);
++        devm_gpio_free(&ts->client->dev, ts->pdata->reset_gpio);
++        gpio_free(ts->pdata->int_gpio);
++
++#if USE_ANALOG_I2C
++         gpio_free(I2CSDA);
++        gpio_free(I2CSCL);
++#endif
++
++	return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int cst3xx_ts_suspend(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++
++	if (device_may_wakeup(&client->dev)) {
++		enable_irq_wake(client->irq);
++	} else {
++		disable_irq(client->irq);
++		cst3xx_ts_power(ts, false);//reset
++	}
++
++	return 0;
++}
++
++static int cst3xx_ts_resume(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++
++	if (device_may_wakeup(&client->dev)) {
++		disable_irq_wake(client->irq);
++	} else {
++		cst3xx_ts_power(ts, true);
++		enable_irq(client->irq);
++	}
++	return 0;
++}
++
++#endif
++
++static SIMPLE_DEV_PM_OPS(cst3xx_ts_pm_ops,
++			 cst3xx_ts_suspend, cst3xx_ts_resume);
++
++static const struct i2c_device_id cst3xx_ts_id[] = {
++	{ CST3XX_NAME, 0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, cst3xx_ts_id);
++
++
++#ifdef CONFIG_OF
++static const struct of_device_id cst3xx_ts_dt_ids[] = {
++	{ .compatible = "xxxxx,cst3xx", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, cst3xx_ts_dt_ids);
++#endif
++
++
++static struct i2c_driver cst3xx_ts_driver = {
++	.probe		= cst3xx_ts_probe,
++	.remove		= cst3xx_ts_remove,
++	.id_table	= cst3xx_ts_id,
++	.driver = {
++		.name	= CST3XX_NAME,
++		.owner	= THIS_MODULE,
++		.of_match_table = of_match_ptr(cst3xx_ts_dt_ids),
++		.pm	= &cst3xx_ts_pm_ops,
++	},
++};
++
++module_i2c_driver(cst3xx_ts_driver);
++
++
++MODULE_AUTHOR("Tiben");
++MODULE_DESCRIPTION("SITRONIX CST3XX Touchscreen Controller Driver");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update1/hyn_cst3xx_RS659_fw.h b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update1/hyn_cst3xx_RS659_fw.h
+new file mode 100644
+index 000000000..006c36c81
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update1/hyn_cst3xx_RS659_fw.h
+@@ -0,0 +1,1553 @@
++
++#ifndef __CST3xx_FW_H__
++#define __CST3xx_FW_H__
++
++  unsigned char cst3_fw[] ={
++    0x98,0xE0,0x07,0x01,0xB0,0x88,0x01,0x00,0x00,0x00,0x00,0x00,0xB0,0x48,0x01,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x80,0x68,0x06,0x00,0x80,0x68,0x07,0x00,0x00,0x00,0x00,0x00,
++    0x88,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x88,0xD8,0x00,0x00,0x80,0x07,0xC0,0x17,
++    0x82,0x07,0xC0,0x07,0x01,0x65,0x40,0x86,0xC1,0x41,0xC0,0x20,0xC5,0x68,0x31,0x12,
++    0xF5,0x38,0x33,0x5A,0x32,0xA2,0x32,0xEA,0x10,0x62,0x8D,0x0E,0x81,0x07,0xC0,0x97,
++    0x30,0xF2,0xF3,0x79,0x65,0x7E,0x30,0xB2,0x31,0x09,0x10,0x9A,0x87,0x06,0xD0,0xD8,
++    0x35,0x12,0x35,0x5A,0x18,0x9A,0x39,0xC2,0xE0,0xE2,0x03,0x00,0xE0,0xE2,0x04,0x00,
++    0xD0,0x81,0x98,0x16,0x43,0xC6,0x0B,0xC6,0xC2,0xD6,0x3F,0x90,0x99,0x0E,0x40,0x86,
++    0x08,0x86,0xA9,0x0E,0x40,0x23,0x00,0x63,0x38,0x82,0x03,0x00,0x18,0x01,0x20,0x01,
++    0x28,0x01,0x30,0x01,0xD0,0x81,0x98,0x0E,0x0F,0xC6,0xC3,0xDE,0x38,0x90,0x9A,0x06,
++    0x08,0x86,0xA9,0x06,0x03,0x5B,0x38,0x82,0xAE,0xFD,0x30,0x02,0x30,0x02,0xEE,0xFD,
++    0xA8,0x85,0xE8,0x85,0x86,0x2F,0xE0,0x1F,0x37,0x8A,0xB8,0xFF,0xF8,0xAF,0x87,0x0F,
++    0xC0,0xCF,0x85,0x2F,0xE7,0xDF,0xBE,0xFF,0xF8,0x9F,0x87,0x2F,0xE0,0x0F,0x07,0x00,
++    0xAF,0x85,0x6F,0xD2,0xE1,0x43,0x31,0x4A,0xCA,0x01,0x3E,0x30,0x34,0x42,0x80,0x01,
++    0xF6,0x1B,0xF4,0x23,0xF3,0x53,0xC2,0x01,0x70,0x01,0xD8,0x16,0xE7,0x6B,0x4D,0x68,
++    0x80,0x4E,0x28,0x01,0x10,0x6C,0xAE,0x6B,0xA4,0x2B,0x12,0xD2,0x8A,0x16,0xB0,0x63,
++    0x00,0x09,0xB0,0x43,0xE8,0x85,0x37,0x72,0xEA,0x4B,0xE0,0x48,0x91,0x4D,0xAE,0x8B,
++    0x57,0xAC,0x7F,0x5A,0x10,0xEA,0x95,0x0E,0xE7,0x68,0x13,0xAC,0x48,0xF9,0x8F,0x0E,
++    0x10,0x12,0x85,0x16,0xE0,0x0B,0x4A,0x09,0x8B,0x26,0xB0,0x9B,0x09,0x01,0xA8,0x8B,
++    0xA7,0x0B,0xEA,0x85,0x4F,0x09,0x8C,0xE6,0x0A,0x09,0xA0,0x0B,0xE8,0x85,0xAF,0x85,
++    0x66,0xF2,0xE6,0x01,0x00,0x0F,0x80,0x0F,0xE1,0xAF,0xF7,0x03,0x47,0x01,0x80,0xD6,
++    0xEB,0x85,0xA8,0x85,0x70,0xDA,0x2E,0x09,0x1E,0xAB,0x65,0xC2,0xE7,0x03,0x09,0x79,
++    0x01,0x42,0xA0,0x03,0x00,0x0F,0x80,0x0F,0xE1,0x2F,0xE7,0x03,0x37,0x00,0xAE,0xD6,
++    0x05,0x01,0x18,0x83,0xE1,0x03,0x19,0x42,0xA3,0x03,0xE9,0x85,0x42,0x7A,0xC6,0x01,
++    0xE6,0x0B,0x44,0x8A,0x48,0x01,0x80,0x3E,0x4A,0x82,0x06,0x0B,0x0E,0xF9,0x57,0x72,
++    0x8A,0x89,0x97,0x01,0x10,0x8B,0x00,0x17,0x48,0x62,0xCE,0xE1,0x07,0x0B,0x0A,0xF9,
++    0x8E,0x21,0x01,0x0B,0x08,0x09,0x08,0x0B,0x08,0x0B,0x0C,0x31,0x08,0x0B,0x0A,0x59,
++    0x18,0x0B,0x0C,0x81,0x18,0x0B,0x0A,0x01,0x1B,0x0B,0x38,0x82,0xAD,0x85,0x40,0xFA,
++    0xE6,0x03,0x38,0x00,0x81,0x8E,0x00,0xE1,0x83,0x0F,0xC8,0x0F,0x40,0xDA,0x0D,0x01,
++    0xC4,0x01,0xA9,0x0B,0xBE,0xFF,0xFF,0x97,0x4D,0xC2,0x55,0xEA,0xCD,0x01,0x46,0xEA,
++    0x84,0x1F,0xD8,0xCF,0x00,0x01,0x80,0x0F,0xC8,0x77,0xE9,0x85,0xAD,0x85,0x40,0x9A,
++    0xC6,0x01,0xE9,0x03,0x40,0x01,0x88,0x36,0x46,0x82,0xC5,0x01,0xE0,0x03,0x44,0x29,
++    0xCF,0x0E,0xB8,0xFF,0xFD,0xE7,0x64,0x6A,0xE0,0x03,0x39,0x00,0xAF,0x0E,0xB8,0xFF,
++    0xFB,0x07,0xE5,0x03,0x38,0x00,0xAC,0x2E,0x42,0x5A,0xC5,0x01,0x42,0x0B,0x40,0x48,
++    0x00,0x48,0x02,0x0B,0xE7,0x03,0x0B,0xE9,0x03,0x42,0xA0,0x03,0x40,0x52,0xC5,0x03,
++    0x40,0x01,0x80,0x16,0x83,0x0F,0xE0,0xF7,0x38,0xE7,0xEF,0x85,0xAD,0x85,0x48,0x3A,
++    0x04,0x01,0x00,0x43,0x4E,0xEA,0xCC,0x01,0xB2,0x43,0xF0,0x43,0x80,0x0F,0xC8,0xFF,
++    0xEB,0x85,0xA8,0x85,0x30,0x2A,0x20,0x49,0x18,0x22,0x4F,0x01,0x80,0x46,0x68,0x01,
++    0x80,0x16,0x30,0x82,0xC0,0x61,0x00,0x4F,0x30,0x82,0x80,0x61,0x20,0x51,0x00,0x2F,
++    0x68,0x01,0x80,0x0E,0xF0,0x80,0x04,0x0F,0xE0,0x80,0x24,0x51,0x0A,0x01,0xF0,0x0A,
++    0x48,0x01,0xD0,0x06,0x16,0x4A,0x0A,0x40,0x0A,0x01,0xF0,0x8A,0x81,0x2F,0xD8,0xA7,
++    0x40,0xF9,0xEB,0x06,0x00,0xF9,0x6B,0x01,0x87,0x16,0x08,0xF9,0x88,0x09,0xD0,0x40,
++    0xCB,0x00,0xE8,0x85,0xAC,0x85,0x6B,0x2A,0xED,0x01,0xE4,0x43,0x41,0x01,0x80,0x26,
++    0x32,0x62,0xA1,0x01,0x40,0x03,0x41,0x01,0x81,0xFE,0x30,0x0A,0xCC,0x01,0x44,0x2A,
++    0x81,0x17,0xC8,0x3F,0x0F,0x01,0x40,0xF9,0x8D,0xC6,0xF0,0x03,0xE3,0x01,0xB4,0x03,
++    0x11,0x11,0x30,0x02,0x82,0x01,0xA1,0x13,0xA8,0x0B,0x01,0x01,0x12,0x79,0x28,0x29,
++    0x5B,0xE2,0x0B,0x68,0xF8,0x23,0x03,0x37,0x0A,0x21,0x19,0x0A,0xC2,0x48,0xCE,0x48,
++    0x92,0x53,0xE0,0x00,0x94,0x05,0x16,0x22,0xC3,0xB6,0xEF,0x85,0x47,0xF1,0x87,0xE6,
++    0x47,0x01,0x80,0xD6,0xF0,0x00,0x12,0x09,0x44,0x1B,0x01,0x12,0x17,0x9A,0x80,0xA6,
++    0xA3,0x4B,0xED,0x85,0xAB,0x85,0x51,0x92,0x28,0x01,0x20,0x01,0x08,0x01,0x00,0x01,
++    0xC4,0x9B,0x10,0x5A,0xC8,0x06,0x30,0xCA,0x58,0xD1,0x9F,0x0E,0x28,0x09,0x00,0x27,
++    0xE2,0x90,0xE2,0x00,0x90,0x05,0x46,0x31,0x99,0x96,0x4F,0xE1,0x92,0x5E,0x40,0xFA,
++    0xC4,0x01,0xE6,0x03,0x40,0x29,0xC8,0x36,0x41,0x12,0x0B,0x81,0xF3,0x0A,0x4A,0xC1,
++    0xD8,0x0E,0x28,0x09,0x03,0x1F,0xE0,0x20,0x90,0x25,0x67,0x71,0x98,0xF6,0x16,0x01,
++    0x48,0x02,0x6B,0x01,0x82,0x7E,0x40,0x44,0xE4,0x00,0x92,0x05,0x00,0x44,0x42,0xA1,
++    0xCC,0x46,0x40,0x44,0xE4,0x00,0x02,0x44,0x02,0x54,0x42,0x82,0x10,0x09,0xE0,0x0B,
++    0x18,0x8A,0xA0,0x0B,0xEA,0x85,0x01,0x54,0xEF,0x85,0xA9,0x85,0x80,0x3D,0x04,0x01,
++    0x80,0x14,0x80,0x1C,0x00,0x01,0x08,0x01,0x10,0x01,0x90,0x0C,0xD2,0x1C,0x58,0x6A,
++    0x06,0x90,0x32,0x09,0xC5,0x90,0x06,0xB0,0xC9,0xA0,0x34,0x2A,0x18,0x01,0x10,0x01,
++    0xF0,0x12,0xC5,0x80,0x92,0x05,0xE0,0x48,0x90,0x4D,0xF8,0x0C,0x10,0xD2,0xED,0x06,
++    0x90,0x0C,0xA0,0x61,0xE6,0xD8,0x92,0xDD,0x5F,0x71,0x98,0x86,0x84,0x2F,0xD0,0xA7,
++    0x90,0x25,0xC0,0x14,0x10,0x02,0xD5,0x06,0xA0,0x14,0x38,0x01,0x60,0x01,0xE8,0xAE,
++    0x35,0x01,0xF8,0x72,0x10,0x32,0xDD,0x66,0xC6,0x0C,0x78,0x08,0xC2,0x40,0x80,0x00,
++    0x10,0x32,0xD4,0x8E,0x09,0x19,0x30,0x82,0x83,0x2F,0xD0,0xF7,0xD1,0x80,0x01,0x44,
++    0x00,0x57,0x70,0x01,0xE8,0x46,0x00,0x09,0x00,0x44,0x01,0x2F,0x01,0x01,0xF0,0x42,
++    0x10,0x02,0xE5,0x0E,0xD9,0x00,0x00,0x44,0xAB,0x61,0xE0,0xF8,0x90,0xFD,0x7F,0x71,
++    0x98,0xE6,0xC6,0x1C,0xE6,0x00,0x92,0x05,0x80,0x1C,0xC0,0x1C,0x45,0x31,0x98,0x8E,
++    0x00,0x01,0x80,0x24,0x00,0x01,0x08,0x01,0x38,0x01,0xD0,0x24,0x1A,0x61,0x18,0xD2,
++    0x5E,0x22,0xC1,0x98,0x14,0x09,0x06,0x90,0xC0,0xD0,0x34,0xA2,0x18,0x01,0x30,0x01,
++    0xF9,0xB2,0xC4,0x80,0x92,0x05,0xE0,0x48,0x95,0x4D,0x10,0xF2,0xE9,0x06,0x30,0xBA,
++    0xE2,0x90,0xE4,0xD8,0x90,0xDD,0x5E,0x31,0x98,0x8E,0x87,0x2F,0xD0,0x2F,0x92,0x2D,
++    0xC5,0x14,0x10,0x42,0xD0,0x06,0xA8,0x14,0x30,0x01,0x68,0x01,0xE8,0xA6,0x01,0x01,
++    0xF0,0x02,0x81,0x34,0x10,0x42,0xDD,0x9E,0x09,0x19,0x30,0x42,0x81,0x2F,0xD0,0xA7,
++    0xC8,0x34,0xD0,0x40,0x91,0x05,0x00,0x04,0x83,0x2C,0xD8,0xC0,0x41,0x41,0xD1,0x4E,
++    0x00,0x40,0x0B,0x19,0x81,0x2F,0xD0,0x47,0xC8,0x2C,0xD0,0x40,0x01,0x04,0x01,0x0F,
++    0xC0,0x34,0x40,0x01,0xE8,0xF6,0x00,0x09,0x00,0x04,0x01,0xDF,0x00,0xC0,0x06,0x01,
++    0x50,0x07,0x03,0x00,0x18,0x00,0x02,0x42,0x00,0x01,0x00,0x42,0x80,0x60,0x05,0x00,
++    0x58,0xC0,0x02,0x01,0x00,0xA0,0x07,0x01,0x00,0x80,0x00,0x01,0x10,0x00,0x00,0x42,
++    0x10,0xC0,0x00,0x01,0x00,0x00,0x00,0x01,0x01,0x01,0xF0,0x02,0x10,0x42,0xE5,0x0E,
++    0xD9,0x00,0x02,0x04,0xE3,0x20,0xE5,0xB0,0x90,0xB5,0x77,0x31,0x98,0xEE,0xC5,0x24,
++    0xE6,0x00,0x92,0x05,0x80,0x24,0xC0,0x24,0x44,0x71,0x98,0x9E,0xC5,0x14,0x50,0xD2,
++    0x40,0xE1,0xD1,0x26,0x7A,0x40,0xCF,0x00,0x82,0x00,0x82,0x83,0x00,0x0F,0x00,0xF1,
++    0x82,0x83,0xC2,0x8B,0x40,0xAA,0x4D,0x01,0x82,0x4E,0xF0,0x48,0x81,0x8B,0x8A,0x41,
++    0x32,0x12,0xD0,0x01,0x88,0x8B,0x08,0x31,0x98,0x0B,0x86,0x3D,0xE8,0x85,0x0F,0x11,
++    0x9F,0x0B,0x3E,0xD7,0xAD,0x85,0x47,0x6A,0x72,0x6A,0xC5,0x01,0xF1,0x2B,0x04,0x09,
++    0x09,0x00,0xC4,0xA0,0x69,0x09,0xC8,0x66,0x1F,0x01,0x10,0xF9,0x02,0x01,0x38,0x19,
++    0x08,0xF8,0x03,0x57,0x0A,0x31,0x18,0x0A,0xCE,0x48,0xCC,0x48,0x54,0x4C,0x10,0xCA,
++    0xC8,0x0E,0x30,0x5A,0x32,0x12,0xE0,0x00,0x94,0x05,0x16,0x2A,0xC7,0x96,0x57,0xF9,
++    0x82,0xBE,0x00,0x80,0xC9,0x08,0x04,0x09,0x08,0x00,0xC4,0x40,0xF1,0x0B,0xB0,0x0B,
++    0xF3,0x03,0xB2,0x03,0x02,0x31,0x18,0x12,0xCE,0x80,0xCC,0x00,0x4C,0xCA,0x4C,0x14,
++    0x0E,0x54,0x4C,0x14,0x08,0x54,0x56,0x04,0x14,0x44,0x48,0xA2,0x02,0x09,0xC8,0x01,
++    0xB4,0x43,0x44,0x92,0x3A,0x01,0xC0,0x01,0xF4,0x03,0x6C,0x7A,0x41,0x01,0x80,0x8E,
++    0xF3,0x03,0xF1,0x13,0x48,0x5C,0x0B,0x61,0x19,0xCA,0x4A,0x64,0xCB,0x48,0x04,0x30,
++    0xC8,0x48,0x34,0x19,0x14,0xB0,0xC9,0x70,0x0B,0x21,0xF0,0x8A,0x48,0x81,0xDA,0x06,
++    0x00,0x7C,0x47,0x01,0x80,0x0E,0x40,0x29,0x8D,0xCE,0x10,0x02,0x8C,0xBE,0x10,0xD2,
++    0x88,0xAE,0x18,0x61,0xF6,0x5A,0xD7,0x58,0x98,0x49,0x58,0x91,0xC7,0x7E,0x40,0x5C,
++    0x65,0x0A,0x14,0x1A,0x92,0x0E,0xE0,0xD8,0x07,0x5C,0x47,0x5C,0x58,0x41,0xCE,0x36,
++    0x03,0x7C,0x5F,0xD2,0x34,0x09,0x98,0x01,0xE1,0xE3,0x18,0xA2,0xA1,0xE3,0x08,0x44,
++    0x0D,0x54,0x0B,0x4C,0x42,0xAA,0xC3,0x01,0x51,0x04,0x46,0x91,0xCF,0x06,0x00,0x7C,
++    0xEF,0x85,0xAF,0x85,0x80,0x3D,0x2C,0x01,0x20,0x01,0x00,0x61,0x4B,0x82,0x1B,0x42,
++    0xC0,0x00,0x82,0x34,0x30,0x01,0x38,0x01,0x00,0x01,0x80,0x1C,0x80,0x14,0xC0,0x34,
++    0x00,0x08,0x13,0x19,0xC0,0x00,0x12,0x90,0xC0,0x10,0x04,0x21,0x90,0x2C,0xF0,0x82,
++    0x80,0x24,0x60,0x01,0x83,0x46,0xF0,0x10,0xDA,0x34,0x00,0x90,0xC0,0xD0,0x1C,0x19,
++    0x16,0xD8,0xC0,0x90,0x34,0x21,0xF8,0xB2,0x68,0x01,0x80,0x56,0xF0,0x50,0x1B,0x61,
++    0x1A,0xD2,0x5A,0xFA,0xC0,0x90,0x1E,0x19,0xC0,0x90,0x12,0xD8,0xC0,0x90,0x3E,0x21,
++    0xF8,0xBA,0x66,0x29,0x83,0x4E,0xE0,0x18,0xD2,0x34,0x00,0xD8,0xC0,0x90,0x1E,0x19,
++    0x16,0xD8,0xC0,0x90,0x1E,0x21,0xF0,0x9A,0x98,0x1C,0x68,0x69,0x83,0x5E,0xE0,0x50,
++    0x1A,0x61,0x18,0xD2,0x5E,0x92,0xC2,0x90,0xC0,0x88,0x12,0x19,0x14,0x90,0xC0,0x50,
++    0x0A,0x21,0xF0,0x8A,0x88,0x14,0x08,0x09,0x89,0x0C,0x70,0x41,0xD1,0x3E,0x78,0x41,
++    0xD0,0x2E,0xC8,0x1C,0x48,0x41,0xD1,0x16,0xC9,0x14,0x48,0x41,0xD8,0x0E,0x08,0x01,
++    0x88,0x0C,0x08,0x19,0x80,0x2F,0xC8,0x47,0x10,0x82,0xED,0x3E,0x10,0xC2,0xED,0x2E,
++    0xCC,0x1C,0x10,0x42,0xE8,0x16,0xC8,0x14,0x10,0x42,0xE4,0x0E,0x00,0x01,0x80,0x0C,
++    0xC0,0x0C,0x40,0x01,0x80,0x36,0xC0,0x24,0x78,0x08,0xC6,0x48,0x82,0x48,0xD2,0x00,
++    0xCC,0x2C,0x00,0x44,0xE7,0x20,0x93,0x25,0x64,0x31,0x98,0x9E,0xE7,0x68,0x93,0x6D,
++    0x6C,0x71,0x98,0x4E,0x3B,0x4F,0xA8,0x85,0x48,0x9A,0x01,0x01,0x06,0x44,0x04,0x44,
++    0x82,0x43,0x80,0x43,0x40,0x8A,0x29,0x09,0x80,0x01,0xE4,0x0B,0x18,0x4A,0xA1,0x0B,
++    0x31,0x22,0xE0,0x01,0x07,0x9F,0xBA,0xFF,0xE9,0xCF,0x43,0x82,0xC0,0x03,0x40,0x01,
++    0x81,0x1E,0x48,0x52,0x02,0xC1,0xC8,0x01,0xB1,0x43,0x40,0x42,0x51,0x62,0x49,0x42,
++    0xC0,0x01,0x82,0x1F,0xF7,0x0F,0xBD,0xFF,0xE9,0x4F,0x49,0x22,0x52,0x42,0xC9,0x01,
++    0x40,0x1A,0x81,0x27,0xC1,0x17,0x4C,0x0A,0x52,0x2A,0xC9,0x01,0x40,0x02,0x81,0x27,
++    0xFF,0x0F,0xBC,0xFF,0xEF,0x3F,0xEE,0x03,0x40,0x01,0x80,0x16,0xE8,0x03,0x47,0x11,
++    0x89,0x1E,0x40,0x02,0x41,0x0B,0x18,0x4A,0x00,0x0B,0x40,0xC2,0x0E,0x11,0x98,0x0B,
++    0x32,0x0A,0xC8,0x01,0x40,0xB2,0x80,0x27,0xE8,0xC7,0x4D,0xA2,0x42,0xA2,0xC8,0x01,
++    0x86,0x27,0xE0,0x7F,0xBF,0xFF,0xEF,0x4F,0xB9,0xFF,0xFF,0xDF,0x48,0x7A,0x40,0x82,
++    0xC8,0x01,0x82,0x27,0xE0,0xF7,0x4A,0x6A,0x12,0x01,0xC8,0x01,0x40,0x62,0x58,0x92,
++    0x85,0x17,0xE8,0x57,0xBD,0xFF,0xF7,0xB7,0xBB,0xFF,0xE7,0xD7,0x48,0x3A,0x40,0x42,
++    0xC8,0x01,0x82,0x0F,0xF0,0x6F,0x80,0x07,0xDF,0x47,0xB8,0xFF,0xE7,0xFF,0xEF,0x03,
++    0x45,0x31,0x88,0x46,0xE8,0x85,0x03,0x00,0x00,0x00,0x00,0x01,0x00,0xC0,0x02,0x01,
++    0x00,0xA0,0x07,0x01,0x48,0xA0,0x02,0x01,0x38,0x81,0x00,0x00,0x00,0x80,0x00,0x01,
++    0x58,0xC0,0x02,0x01,0xF8,0x00,0x06,0x42,0x18,0xD8,0x05,0x00,0xA8,0x85,0x33,0x22,
++    0xF0,0x03,0x83,0x07,0xF1,0xA7,0x41,0x9A,0x2C,0x01,0x00,0x2B,0xB5,0x2B,0x01,0xB1,
++    0xAF,0x2A,0xB8,0xFF,0xE4,0x1F,0xA5,0x01,0xFA,0x03,0x31,0x08,0x42,0x72,0x71,0x48,
++    0x1C,0x0B,0x5C,0x0B,0x02,0x48,0x1A,0x0B,0x09,0x2B,0xFE,0x0B,0x30,0x48,0xA8,0x16,
++    0x0E,0x09,0x04,0x0B,0x1B,0x2B,0xE8,0x85,0xAD,0x85,0x87,0x9D,0x42,0x32,0xC1,0x01,
++    0x42,0x0B,0x40,0x48,0x00,0x48,0x02,0x0B,0x51,0x22,0x49,0x2A,0x40,0x2A,0x81,0x0F,
++    0xC1,0x97,0x67,0x1A,0x35,0x2A,0xA9,0x01,0x01,0xBF,0x41,0x0A,0xBE,0xFF,0xFF,0x77,
++    0x52,0x03,0x81,0x01,0xE7,0x03,0x40,0x79,0x80,0x0E,0x51,0xEA,0x48,0xEA,0x00,0x01,
++    0x58,0xD2,0x80,0x07,0xF8,0x2F,0x51,0xD2,0x48,0xD2,0x00,0x09,0x58,0xBA,0x80,0x07,
++    0xF9,0xFF,0x50,0x03,0x80,0x01,0xE2,0x03,0x40,0x59,0x8D,0x86,0x40,0xB2,0x48,0xAA,
++    0x88,0xA1,0x11,0x01,0xD5,0x3B,0xD7,0x1B,0x18,0xFA,0x42,0x5C,0x44,0x34,0xD8,0xD8,
++    0x04,0x1C,0xE0,0x00,0xE2,0x48,0xE4,0x90,0x95,0x95,0x14,0xD2,0x99,0xAE,0x57,0x03,
++    0x80,0x01,0xE2,0x03,0x40,0x59,0x85,0x2E,0x50,0x42,0x48,0x4A,0x40,0x4A,0x58,0x0D,
++    0x80,0x0F,0xC0,0xBF,0x40,0x0D,0x80,0x07,0xDF,0xFF,0xE9,0x43,0x46,0x31,0x80,0x26,
++    0x87,0x9D,0xE9,0x85,0x10,0x00,0x00,0x42,0x00,0x01,0x00,0x42,0x58,0xC0,0x02,0x01,
++    0x00,0xC0,0x00,0x01,0x00,0xA0,0x07,0x01,0x18,0xC0,0x07,0x01,0x4C,0xFA,0x6F,0x54,
++    0x82,0x13,0x68,0x54,0x80,0x13,0x32,0x52,0x92,0x01,0xF5,0x93,0x80,0x13,0xCC,0x4B,
++    0x83,0x0B,0x3E,0x82,0xA8,0x85,0xF3,0x24,0x63,0xC2,0xFF,0x23,0x11,0x22,0xCC,0x56,
++    0x23,0x21,0x19,0x02,0x60,0xB2,0xCF,0x00,0x23,0x29,0x0A,0x20,0xCE,0x00,0x50,0x24,
++    0x58,0x2C,0x48,0x09,0x8E,0x26,0x50,0x0C,0x23,0xF9,0xA7,0x49,0xD4,0x08,0x93,0x65,
++    0x50,0x09,0x88,0x26,0x58,0x0C,0x10,0xC9,0x0A,0x90,0xD2,0x88,0x90,0x6D,0xD4,0x0B,
++    0xD0,0x13,0x0A,0x48,0x00,0x90,0x1A,0x8A,0x81,0xCB,0x48,0x08,0x81,0xCB,0x4A,0x48,
++    0x81,0xCB,0x0C,0x08,0x38,0x50,0x79,0x90,0x1E,0x8A,0x80,0xCB,0x58,0x04,0x8A,0xC3,
++    0xC2,0x83,0xE9,0x00,0x83,0x83,0xE9,0x85,0xAC,0x85,0x87,0x2D,0x0F,0x01,0x00,0x0D,
++    0x40,0x2E,0x90,0x24,0x86,0x1C,0x40,0xEA,0xFA,0x2B,0xF8,0x1B,0x06,0x01,0x60,0xFA,
++    0x51,0xFA,0xC6,0x33,0x70,0x59,0x85,0x1E,0xE4,0x00,0x92,0x05,0x17,0x82,0x9C,0xC6,
++    0x50,0xE2,0x46,0x83,0x31,0x09,0x18,0x82,0x07,0x83,0x00,0xF9,0x80,0x03,0x69,0x01,
++    0x80,0xBE,0x08,0x01,0x50,0x1D,0x00,0x01,0x2E,0x29,0x62,0x8A,0x08,0x68,0x03,0x77,
++    0x32,0x21,0x19,0x32,0xCB,0xB0,0xC9,0xB0,0xD0,0xB3,0x75,0x09,0x88,0x2E,0x80,0x83,
++    0xE6,0x48,0x92,0x4D,0xE0,0x90,0x4A,0x29,0x82,0x1E,0xE0,0x00,0x94,0x05,0x16,0xC2,
++    0x98,0x76,0x8F,0x0C,0x60,0x4A,0x6E,0x1D,0x36,0x01,0x78,0x22,0xB9,0x01,0x06,0x0F,
++    0x70,0x01,0x88,0x9E,0x50,0x15,0x90,0x04,0x11,0x01,0xC0,0x43,0x30,0x1A,0x31,0x8A,
++    0xBC,0xFF,0xFF,0x47,0xE5,0x68,0xE3,0xC3,0xCE,0x0C,0x48,0x00,0x08,0x00,0x1E,0x42,
++    0x8D,0x03,0x03,0x59,0x8D,0x03,0xED,0x20,0xE0,0x20,0x03,0x4F,0x50,0x15,0x90,0x04,
++    0x11,0x01,0xC0,0x43,0x30,0x1A,0x31,0x8A,0xBB,0xFF,0xFF,0xA7,0xE3,0x68,0xEB,0x20,
++    0xE7,0xB0,0x93,0xB5,0xC4,0x0C,0x10,0x32,0x9D,0xD6,0xE6,0xC3,0x1E,0x01,0x4C,0x08,
++    0x48,0x01,0x80,0x96,0xC8,0x0C,0x48,0x01,0x81,0x36,0x80,0x03,0xEB,0xC3,0x81,0x03,
++    0x05,0x59,0x85,0x03,0xE0,0x20,0x05,0x37,0x81,0x03,0xE9,0xC3,0x83,0x03,0x8B,0x1B,
++    0x05,0x59,0x8D,0x03,0xEB,0x20,0xE5,0x20,0x00,0x2F,0xC0,0x0C,0x40,0x09,0xC8,0x16,
++    0x01,0x59,0x85,0x03,0xE1,0x20,0x33,0x02,0xBA,0xFF,0xFF,0x07,0x4A,0x32,0x45,0x43,
++    0x10,0x01,0x1A,0x82,0x05,0x43,0x4A,0x2A,0x40,0x43,0x1A,0xC2,0x03,0x43,0xE2,0xC3,
++    0x08,0x11,0x18,0x42,0xA0,0xC3,0x83,0x2D,0xEF,0x85,0xAF,0xFD,0x80,0x0D,0xFC,0x54,
++    0x30,0x32,0x30,0x62,0x6E,0xAA,0xAC,0x01,0x50,0x09,0x88,0x4E,0x00,0x0F,0x80,0x0F,
++    0xC1,0xCF,0xE1,0x43,0x37,0x00,0xAA,0xD6,0xE5,0x43,0x09,0xF9,0x01,0x42,0xA0,0x43,
++    0x04,0x09,0x30,0x22,0x51,0xAA,0x04,0x8F,0x60,0x01,0xC1,0x2E,0xF7,0x00,0x0B,0x01,
++    0x1A,0x42,0x08,0x83,0x30,0x0A,0x01,0x17,0x02,0xF9,0x0F,0x83,0x08,0x01,0x19,0x01,
++    0x08,0x9B,0x04,0x01,0x00,0x4F,0x78,0x01,0x88,0x16,0x18,0x01,0x00,0x9B,0x06,0x17,
++    0xC6,0x9B,0x01,0x9B,0xCA,0xB0,0xE7,0x00,0x94,0x05,0x14,0x42,0x9B,0x9E,0x37,0x02,
++    0x40,0x01,0x80,0x26,0x04,0xA1,0x00,0x83,0x04,0x01,0x30,0x22,0x00,0x0F,0x00,0x21,
++    0x03,0x83,0xD4,0x00,0x92,0x25,0x44,0x83,0x08,0x01,0x1C,0x42,0x01,0x83,0xE2,0x43,
++    0x37,0x00,0xAA,0xE6,0xE5,0x43,0x09,0xF9,0x01,0x42,0xA0,0x43,0x66,0x01,0x88,0x5E,
++    0xC0,0x24,0x40,0x09,0x88,0x7E,0x05,0x01,0x02,0x83,0x44,0x83,0x08,0x01,0x1C,0x42,
++    0x05,0x83,0x3A,0x47,0xAC,0x9D,0x87,0x1D,0x20,0x01,0x00,0x01,0x80,0x0C,0x70,0x15,
++    0x40,0x52,0xF3,0x03,0xEE,0x00,0x92,0x3D,0x6E,0x42,0xAB,0x01,0x00,0xAF,0x81,0x07,
++    0xF9,0x0F,0xE7,0x43,0x30,0x00,0xA2,0x1E,0x40,0x22,0xF3,0x03,0x17,0xC2,0x9D,0xB6,
++    0x40,0x12,0xF3,0x03,0x10,0xC2,0x9D,0x06,0x21,0x11,0xE0,0x43,0x08,0xF9,0x05,0x42,
++    0xA3,0x43,0x41,0x32,0x46,0x0B,0x14,0x79,0x00,0x8A,0x48,0x09,0x88,0x9E,0x08,0x01,
++    0x0E,0x0B,0x44,0x0B,0x83,0x8B,0xE1,0xB0,0xE7,0x20,0x93,0x25,0x60,0x11,0x88,0x56,
++    0x30,0x5A,0xD3,0xCB,0xD4,0x1C,0x10,0x8A,0x8A,0x2E,0xD0,0xCB,0xD4,0x24,0x10,0x8A,
++    0x88,0x0E,0x08,0x09,0x8F,0x0C,0x08,0x01,0x08,0x0B,0x0A,0x01,0x08,0x0B,0x0C,0x81,
++    0x02,0x0B,0x44,0x0B,0x10,0x01,0x1C,0x8A,0x00,0x0B,0x62,0x11,0x88,0x4E,0xC6,0x0C,
++    0x3A,0x0F,0x4B,0x52,0x58,0x54,0x86,0x13,0x12,0x01,0x80,0x13,0xE4,0x4B,0x82,0x0B,
++    0x4A,0x62,0x8A,0x01,0x5E,0x53,0x84,0x13,0x58,0x53,0x8A,0x13,0x12,0x91,0x88,0x13,
++    0x14,0x19,0x88,0x13,0x4E,0x53,0x8E,0x13,0x48,0x53,0x94,0x13,0x4A,0x4B,0x92,0x0B,
++    0x0C,0x09,0x90,0x0B,0x3F,0x82,0xAB,0x85,0x80,0x4D,0x34,0x22,0x30,0x01,0x00,0x01,
++    0x80,0x2C,0x38,0x01,0x4C,0xCA,0xD1,0x43,0xD2,0x4B,0x1E,0x42,0x81,0x14,0x40,0xC2,
++    0x80,0x61,0x80,0x24,0xC0,0x61,0x80,0x1C,0x60,0x09,0x80,0x0E,0x60,0x29,0x88,0x76,
++    0x60,0x09,0x88,0x1E,0x70,0xD2,0xB1,0x2C,0x78,0xD2,0x01,0x27,0x73,0xD2,0xE1,0x80,
++    0x81,0x2C,0x78,0xC2,0xF8,0x81,0x41,0x35,0xBA,0xFF,0xF7,0xC7,0x00,0x3F,0x60,0x21,
++    0x89,0x2E,0x70,0xB2,0x47,0x35,0xB8,0xFF,0xF9,0xE7,0x7D,0x92,0xB9,0xA1,0x6A,0x3A,
++    0xA9,0x01,0xE6,0x43,0x08,0xF9,0x05,0x42,0xA1,0x43,0xE1,0x43,0x08,0x01,0x19,0x42,
++    0xA1,0x43,0x41,0x4A,0x42,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,0x4A,0x3A,0x41,0x43,
++    0x10,0x01,0x1C,0x82,0x01,0x43,0x4A,0x1A,0x40,0x43,0x10,0x09,0x18,0x82,0x00,0x43,
++    0x0C,0x09,0x00,0x01,0xBA,0xFF,0xFF,0xB7,0x42,0x09,0x88,0x66,0x62,0x21,0x88,0x5E,
++    0x10,0x09,0x90,0x04,0x30,0x82,0x19,0x01,0xCF,0x14,0xB8,0xFF,0xF0,0xB7,0x17,0x09,
++    0x90,0x04,0x10,0x01,0x08,0x59,0x40,0x35,0x37,0x9A,0xB8,0xFF,0xF0,0x77,0x17,0x09,
++    0x90,0x04,0x10,0x01,0x09,0x31,0x30,0xC2,0x37,0x9A,0xB8,0xFF,0xF0,0x37,0x17,0x09,
++    0x90,0x04,0x40,0xA2,0x10,0x01,0x08,0x71,0xC0,0x21,0x32,0x9A,0xBE,0xFF,0xF7,0xEF,
++    0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x31,0x30,0x9A,0xC0,0x24,0xBE,0xFF,0xF7,0xAF,
++    0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x31,0x18,0x09,0x00,0xCF,0x00,0xC0,0x00,0x01,
++    0x00,0xA0,0x07,0x01,0xFF,0xFF,0xFF,0xFF,0x00,0xF8,0x07,0x00,0x58,0x20,0x00,0x01,
++    0x90,0xE4,0x03,0x00,0xF8,0x00,0x06,0x42,0x00,0x00,0x06,0x42,0x80,0x01,0x06,0x42,
++    0x10,0xC0,0x00,0x01,0x40,0x60,0x07,0x01,0x18,0xC0,0x07,0x01,0x38,0xC0,0x05,0x01,
++    0xC7,0x1C,0xB8,0xFF,0xF2,0x97,0x05,0x27,0x60,0x09,0x80,0x0E,0x62,0x29,0x88,0x06,
++    0x60,0x09,0x88,0x76,0x10,0x09,0x90,0x04,0x30,0x82,0x19,0x01,0xCF,0x14,0xB8,0xFF,
++    0xF0,0x27,0x15,0x01,0x90,0x04,0x30,0x9A,0xC8,0x14,0xC0,0x2C,0xBC,0xFF,0xF7,0xEF,
++    0x00,0x7F,0x10,0x11,0x90,0x04,0x10,0x09,0x30,0x82,0x19,0x01,0xCF,0x14,0xB8,0xFF,
++    0xF0,0xA7,0x14,0x11,0x90,0x04,0x10,0x01,0x30,0x9A,0xC8,0x14,0xC7,0x2C,0xB8,0xFF,
++    0xF0,0x67,0x14,0x09,0x90,0x04,0x10,0x01,0x08,0x21,0x40,0x35,0x37,0x9A,0xB8,0xFF,
++    0xF0,0x27,0x14,0x09,0x90,0x04,0x10,0x01,0x09,0x41,0x31,0xC2,0x37,0x9A,0xB8,0xFF,
++    0xF0,0xE7,0x13,0x09,0x90,0x04,0x10,0x01,0x08,0x31,0x30,0x9A,0xC7,0x24,0xB8,0xFF,
++    0xF0,0xA7,0x13,0x09,0x90,0x04,0x10,0x01,0x08,0x31,0x18,0x09,0xC7,0x1C,0xB8,0xFF,
++    0xF1,0x67,0xE3,0x43,0x08,0xF9,0x06,0x42,0xA5,0x43,0x41,0x32,0x42,0x0B,0x40,0x48,
++    0x00,0x48,0x02,0x0B,0x47,0x22,0x0D,0x01,0x08,0x0B,0x0A,0x01,0x02,0x0B,0x44,0x0B,
++    0x10,0x01,0x1C,0x8A,0x00,0x0B,0x82,0x4D,0xEB,0x85,0xAF,0x85,0x67,0xFA,0xEC,0x03,
++    0x28,0x01,0x40,0x09,0x87,0x16,0xE8,0x03,0x40,0x29,0x88,0x5E,0x71,0xE2,0xC4,0x83,
++    0x40,0x11,0x98,0x26,0xEF,0x03,0xBF,0xFF,0xF1,0xF7,0x87,0xAB,0xEA,0x85,0xE3,0x00,
++    0x83,0x83,0xE9,0x85,0xE8,0x03,0x47,0x21,0x8F,0x26,0xB8,0xFF,0xF0,0xA7,0x07,0x19,
++    0xAB,0x03,0xEF,0x85,0xE8,0x03,0x47,0x19,0x87,0xDE,0xEF,0x03,0x47,0x31,0x80,0xC6,
++    0x4D,0x72,0xCC,0x01,0xF8,0x43,0x40,0x01,0x88,0x3E,0x30,0x42,0x80,0x01,0xF6,0x13,
++    0x50,0x31,0x98,0x3E,0xE0,0x03,0x34,0x00,0xAC,0x26,0x40,0x42,0xC4,0x01,0xE3,0x03,
++    0x40,0x01,0x80,0xA6,0xE8,0x03,0x47,0x01,0x8E,0x1E,0x57,0x44,0x47,0x31,0x88,0x06,
++    0x45,0x22,0x0C,0x59,0x82,0x0B,0x80,0x2B,0x86,0x2B,0x84,0x2B,0x8A,0x2B,0x88,0x2B,
++    0x8B,0x0B,0x44,0xE2,0x42,0x0B,0x40,0x48,0x00,0x48,0x02,0x0B,0xEF,0x85,0xBB,0xFF,
++    0xEB,0xDF,0xEB,0x85,0xA8,0xC5,0x27,0x01,0x30,0x1A,0x00,0x09,0x4B,0xBA,0x6B,0xD2,
++    0x30,0x01,0x59,0x51,0x80,0xE6,0xE1,0x4E,0x79,0xC2,0xE3,0xD3,0x87,0x27,0xE8,0xDF,
++    0x61,0x52,0x20,0x09,0x39,0x61,0x62,0x52,0x71,0x61,0x62,0x92,0x40,0x7A,0x13,0x31,
++    0xC0,0x01,0x55,0x03,0x80,0x01,0x5A,0xC9,0x80,0xAE,0xE1,0x4E,0x59,0x59,0x80,0x56,
++    0x59,0x61,0x80,0x66,0x59,0x69,0x88,0xBE,0x06,0x29,0xA8,0x43,0x21,0x09,0x00,0x9F,
++    0x59,0xD1,0x80,0x6E,0x59,0x01,0x89,0x7E,0xA8,0x53,0x26,0x09,0x08,0x59,0xA5,0x0B,
++    0x00,0x57,0x01,0x39,0xA9,0x43,0x06,0x3F,0x86,0x07,0xE8,0xF7,0x00,0x27,0x19,0x12,
++    0xA1,0xD3,0x01,0x0F,0x00,0x41,0x18,0x12,0xA0,0xD3,0x01,0xEF,0x06,0x11,0xA8,0x43,
++    0x20,0x09,0x00,0xCF,0x06,0x01,0xA8,0x43,0x41,0x43,0x19,0x82,0x00,0x43,0x01,0x9F,
++    0xA8,0x43,0x26,0x09,0x00,0x87,0x00,0x19,0xA8,0x43,0x26,0x09,0x00,0x67,0x00,0x21,
++    0xA8,0x43,0x26,0x09,0x06,0x47,0xA8,0x53,0x26,0x09,0x08,0x69,0xA0,0x0B,0x00,0x1F,
++    0xA8,0x53,0x26,0x09,0x08,0x79,0xA7,0x0B,0x60,0x01,0x80,0x66,0x40,0x82,0x42,0x0B,
++    0x30,0x48,0xA8,0x2E,0x08,0x81,0x06,0x0B,0x08,0x81,0x02,0x0B,0x08,0x81,0x00,0x0B,
++    0x45,0x43,0x19,0x82,0x07,0x43,0xE9,0xC5,0xAC,0x8D,0x87,0x25,0x40,0x4A,0x82,0x14,
++    0x45,0x12,0xC2,0x01,0xD6,0x2B,0xD4,0x33,0x08,0x01,0xB0,0x0B,0x61,0x1A,0xE2,0x0B,
++    0x10,0xF9,0x05,0x8A,0xA1,0x0B,0xE1,0x0B,0x10,0x01,0x19,0x8A,0xA2,0x0B,0x51,0x02,
++    0x92,0x01,0x46,0x8B,0x18,0x01,0x1A,0xCA,0x01,0x8B,0x52,0xBA,0x44,0x8B,0x1A,0x01,
++    0x1A,0xCA,0x00,0x8B,0x79,0x9A,0x41,0xCB,0x10,0x09,0x18,0x8A,0x00,0xCB,0x51,0x03,
++    0x80,0x01,0xE2,0x0B,0x49,0x79,0x87,0xDE,0xE6,0x03,0x40,0x69,0x88,0x46,0x09,0xA9,
++    0x07,0x91,0xB8,0xFF,0xE8,0x3F,0x46,0x09,0x89,0x0E,0x32,0x42,0x1A,0x82,0x03,0x08,
++    0x10,0x09,0x88,0x1C,0x94,0x04,0x90,0x4D,0x18,0x01,0xC0,0x14,0xBB,0xFF,0xEF,0x2F,
++    0x42,0xC3,0x41,0x00,0x01,0x00,0x02,0xC3,0x40,0x5A,0x11,0x09,0x90,0x04,0xC8,0x1C,
++    0x14,0x01,0x90,0x4D,0x37,0x9A,0xB8,0xFF,0xE8,0xC7,0xC2,0x24,0x15,0x09,0xC8,0x48,
++    0xE8,0x48,0x90,0x04,0x00,0x48,0x12,0x01,0x1F,0x09,0xB8,0xFF,0xE8,0x77,0x02,0xF7,
++    0x08,0xA1,0x00,0x91,0xBC,0xFF,0xEF,0xF7,0x40,0x09,0x88,0xC6,0x18,0xAA,0x13,0x09,
++    0x20,0x40,0x63,0x08,0x90,0x04,0x30,0x9A,0xC7,0x14,0xB8,0xFF,0xE8,0xF7,0x01,0x77,
++    0x08,0xB1,0x00,0x91,0xBC,0xFF,0xEF,0x77,0x40,0x09,0x88,0x46,0xC0,0x24,0x10,0x09,
++    0xC8,0x48,0xED,0x48,0x00,0x48,0x32,0x9A,0x97,0x04,0xB8,0xFF,0xE9,0x77,0xE1,0x03,
++    0x08,0xF9,0x06,0x42,0xA1,0x03,0x41,0xC3,0x42,0x00,0x02,0x00,0x00,0xC3,0x41,0x32,
++    0x0A,0x01,0x0F,0x0B,0x0C,0x01,0x00,0x0B,0x44,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,
++    0x28,0xCF,0x00,0x00,0xF8,0x00,0x06,0x42,0x80,0x01,0x06,0x42,0x00,0xC0,0x05,0x01,
++    0x00,0x70,0x00,0x01,0x58,0x20,0x00,0x01,0x10,0x00,0x00,0x42,0x00,0xC0,0x06,0x01,
++    0x00,0x00,0x00,0x42,0x18,0xC0,0x07,0x01,0x08,0x40,0x01,0x01,0x52,0xCA,0x42,0x83,
++    0x02,0x83,0x42,0xCA,0xF7,0x0B,0x48,0xF9,0x90,0x16,0xF0,0x0B,0xE0,0x48,0xB2,0x0B,
++    0xF0,0x03,0x40,0xC1,0x90,0x0E,0x00,0x01,0x03,0x83,0x3C,0x82,0x4C,0x9A,0x4A,0x53,
++    0x58,0x8A,0xE2,0xC3,0x1C,0x12,0x0C,0x53,0x10,0x43,0x02,0x09,0xB3,0xC3,0x38,0x82,
++    0xAA,0x85,0x40,0x72,0x84,0x01,0x42,0x0B,0x10,0x01,0x1C,0x8A,0x02,0x0B,0x54,0x62,
++    0x4A,0x4A,0x42,0x62,0x85,0x27,0xC0,0xAF,0xEF,0x85,0xA8,0xC5,0x46,0x32,0x82,0x01,
++    0xE2,0x0B,0x78,0x4A,0x30,0x48,0xAC,0x46,0xE2,0x0B,0x10,0x01,0x18,0x8A,0xA0,0x0B,
++    0x44,0xC3,0x0B,0x01,0x1B,0x42,0x04,0xC3,0xE8,0xC5,0x17,0x01,0x0D,0xD3,0x45,0xCB,
++    0x6E,0xEA,0x01,0x79,0x01,0x0A,0x30,0x72,0x59,0x02,0xB2,0x01,0x61,0x44,0x57,0x63,
++    0x48,0x09,0x80,0xDE,0x48,0x29,0x80,0x46,0x4B,0x41,0x88,0x46,0x8F,0x93,0x43,0xCB,
++    0x38,0x48,0x8E,0x16,0x05,0x81,0x00,0xC3,0xED,0xC5,0x0F,0xD3,0x10,0xC2,0x8C,0x16,
++    0x07,0x29,0x05,0xC3,0x01,0x3F,0xE0,0x0A,0x02,0xCB,0xE7,0x00,0x97,0x05,0x24,0x44,
++    0x40,0x89,0x9A,0x06,0x20,0x5C,0x07,0xA1,0x07,0xC3,0xED,0xC5,0xC8,0x8B,0x4B,0x11,
++    0x91,0xE6,0x61,0x7A,0x48,0x01,0x88,0x2E,0x43,0xC3,0x07,0x04,0x41,0x6A,0x11,0x43,
++    0x21,0x54,0x07,0xF7,0x43,0xC3,0x47,0x0C,0x10,0x48,0xC0,0x40,0x96,0x25,0x04,0x89,
++    0x11,0x00,0xD0,0x00,0x40,0x01,0xC1,0x76,0x97,0x05,0xBF,0xFF,0xF1,0x1F,0x44,0x32,
++    0x11,0x22,0x8C,0x76,0x00,0x09,0x80,0x07,0xC8,0xD7,0x03,0xC1,0xB1,0x43,0x49,0x02,
++    0x00,0x09,0x80,0x43,0x00,0x2F,0x41,0xC2,0x86,0x01,0xED,0x03,0x08,0x69,0x18,0x48,
++    0x40,0x01,0x88,0x36,0xD2,0x00,0x43,0x81,0xC7,0x0E,0x20,0x44,0x07,0xCF,0x20,0x5C,
++    0x00,0xBF,0x40,0xD2,0xC1,0x00,0x41,0x19,0xC7,0x1E,0x20,0x44,0x41,0xC2,0x10,0x43,
++    0x03,0x7F,0xD0,0x00,0x40,0xB1,0xC1,0x66,0x20,0x44,0x07,0x57,0x10,0xC2,0x84,0x46,
++    0x41,0xCB,0xA7,0x0A,0x62,0x44,0xE7,0x00,0x97,0x05,0x24,0x44,0x40,0x89,0x9A,0x06,
++    0x23,0x5C,0xCF,0x83,0xE3,0x00,0x8A,0x83,0x05,0x81,0x00,0xC3,0xED,0xC5,0x07,0xD3,
++    0xE8,0xC5,0x07,0x00,0x10,0x00,0x00,0x42,0x00,0xC0,0x00,0x01,0xF8,0x00,0x06,0x42,
++    0x58,0xC0,0x02,0x01,0x00,0xA0,0x07,0x01,0x80,0x01,0x06,0x42,0xF8,0xFF,0x07,0x00,
++    0x00,0x80,0x00,0x01,0x58,0x20,0x00,0x01,0x88,0x76,0x00,0x00,0x77,0x81,0xF8,0xFF,
++    0xF8,0x02,0x07,0x00,0xA8,0x85,0x80,0x07,0xC8,0x77,0x65,0x32,0xE8,0x03,0x47,0x01,
++    0x80,0x26,0x40,0x31,0x8F,0xD6,0xBF,0xFF,0xDF,0x3F,0x38,0xBF,0xBB,0xFF,0xD7,0x5F,
++    0x38,0xA7,0x07,0x00,0x00,0xC0,0x05,0x01,0xAE,0xC5,0x6F,0xDA,0x03,0x41,0x83,0x43,
++    0x01,0x09,0x80,0x43,0x0F,0x01,0x81,0x4B,0x15,0x19,0x80,0x53,0x13,0x41,0x89,0x53,
++    0x17,0x69,0x89,0x53,0x15,0x69,0x88,0x53,0x11,0x92,0x32,0x7A,0xBD,0x01,0x15,0xD4,
++    0x17,0xA1,0x1D,0x54,0x32,0x62,0xA1,0x01,0x8D,0x03,0x8B,0x03,0x07,0x41,0x88,0x03,
++    0x11,0x51,0x90,0x13,0x13,0xA1,0x90,0x13,0x90,0x0B,0x0F,0x81,0x9B,0x0B,0x99,0x03,
++    0x0F,0x01,0x98,0x4B,0x0D,0x71,0x90,0x4B,0x17,0x31,0x90,0x53,0x98,0x4B,0x0B,0x31,
++    0x98,0x4B,0x09,0x01,0x99,0x4B,0xA5,0x43,0x03,0x81,0xA1,0x43,0x03,0x51,0x80,0x03,
++    0x05,0xB1,0x87,0x03,0x07,0x51,0x80,0x03,0x01,0xB1,0x8F,0x03,0x05,0x29,0x94,0x03,
++    0x01,0x51,0x28,0x44,0x03,0xF9,0x87,0x49,0x34,0x32,0xB1,0x01,0x00,0x84,0x01,0xC9,
++    0x0B,0x00,0x02,0x84,0x04,0x79,0x10,0x00,0x05,0x83,0x43,0xC2,0x00,0x83,0x05,0x01,
++    0x99,0x83,0x31,0x02,0x0C,0x51,0x80,0x91,0x87,0x27,0xD0,0x87,0x05,0xB1,0xB7,0xC3,
++    0x07,0xA1,0xB0,0xC3,0x07,0x01,0xA8,0xC3,0x09,0x01,0x30,0x02,0x80,0x01,0xA2,0x0B,
++    0xA0,0x0B,0x0E,0xC1,0xA8,0x0B,0x08,0x51,0xAE,0x0B,0x0A,0x41,0x1F,0x0C,0x0E,0xF9,
++    0x89,0x21,0x00,0xCC,0x0E,0x99,0x18,0x4A,0xA8,0x0B,0x14,0xA1,0xA8,0x13,0xB6,0x0B,
++    0x0A,0xA1,0xB0,0x0B,0x0A,0x51,0x88,0x0B,0x14,0xF1,0x88,0x13,0x0E,0x21,0x8B,0x0B,
++    0x0A,0x59,0x0D,0x0C,0x08,0xE1,0x90,0x0B,0x08,0xC9,0x99,0x0B,0x0A,0x31,0x98,0x0B,
++    0x08,0xF9,0x8F,0x09,0x08,0x0C,0x0E,0x51,0xB8,0x4B,0x0B,0x01,0x32,0x4C,0xA3,0x0B,
++    0x0D,0x21,0xB0,0x8B,0x0B,0x31,0xB0,0x8B,0x09,0x19,0x0D,0x4C,0x0C,0xA1,0xB0,0x0B,
++    0x0E,0x51,0xB0,0x0B,0x0C,0x01,0xA0,0x0B,0x08,0x19,0xBC,0x0B,0x09,0x31,0x80,0x0B,
++    0x18,0x01,0x30,0x0A,0xCE,0x01,0x9B,0x5B,0xA2,0x5B,0x88,0x01,0xB2,0x53,0xB0,0x53,
++    0x14,0xE1,0xB1,0x53,0x16,0x41,0xB0,0x53,0x10,0x11,0xB8,0x53,0x12,0xB1,0xB8,0x53,
++    0x14,0x19,0xB8,0x53,0x48,0x52,0x04,0x0B,0x8C,0x1B,0x48,0x52,0xC6,0x01,0x34,0x0B,
++    0x88,0x91,0x38,0x0B,0x8A,0xE1,0x3E,0x0B,0x0C,0xC1,0x40,0x3A,0x84,0x27,0xD0,0x77,
++    0x40,0x2A,0x0C,0xC1,0xC0,0x81,0x81,0x27,0xD4,0x4F,0x4C,0x12,0x43,0x1A,0xCC,0x31,
++    0x00,0x0B,0xCE,0x71,0x00,0x0B,0x8C,0xA1,0x08,0x0B,0x88,0xC1,0x0A,0x0B,0xCA,0x21,
++    0x01,0x0B,0xCA,0xC1,0x05,0x0B,0x88,0xA1,0x0D,0x0B,0xCC,0xC1,0x10,0x0B,0xFA,0x48,
++    0x10,0x0B,0xF8,0x48,0x0F,0x0B,0xEE,0xC5,0xA8,0x85,0x09,0x01,0x63,0x92,0x43,0x92,
++    0xA2,0xE1,0xFE,0x1B,0x01,0x77,0x00,0x21,0x18,0x42,0xCA,0x28,0x00,0x29,0x12,0x79,
++    0x09,0x00,0xC2,0x40,0x90,0x13,0x10,0x01,0x94,0x13,0x92,0x13,0x10,0x14,0x1E,0x14,
++    0xE6,0x48,0x92,0x4D,0x17,0x5A,0xC4,0x76,0x07,0x01,0x10,0xF9,0x2D,0x09,0x09,0x68,
++    0x02,0x37,0x00,0x08,0xCA,0x48,0xC8,0x48,0xB2,0x53,0xB0,0x53,0xE6,0x00,0x92,0x05,
++    0x17,0x1A,0xC4,0xB6,0xE9,0x85,0xA1,0x85,0x56,0xFA,0x92,0x01,0x08,0x01,0x10,0x8C,
++    0xD4,0x01,0xB6,0x8B,0xB8,0x8B,0x30,0x9A,0x98,0x01,0xB5,0xCB,0x1C,0xCC,0xBC,0xCB,
++    0xB0,0xCB,0x22,0x09,0xB0,0xA3,0xA8,0x8B,0xDE,0x01,0xF1,0xDB,0xB0,0x9B,0x32,0x9A,
++    0x9A,0x01,0xA1,0xCB,0x9A,0x01,0xA1,0xE3,0xA4,0xCB,0xA0,0xA3,0x20,0x41,0x89,0xA3,
++    0x40,0x09,0x88,0x16,0xA1,0xCB,0xE4,0x85,0x39,0xB7,0xE5,0x85,0x3A,0x82,0x0B,0x08,
++    0x40,0x9A,0x42,0x13,0x18,0x01,0x01,0xD2,0x90,0x41,0x04,0x13,0x10,0xD0,0x1C,0x8A,
++    0x0A,0x0B,0x42,0x0B,0x40,0x0B,0x10,0x41,0x18,0x8A,0x04,0x0B,0x0C,0x01,0x00,0x0B,
++    0x38,0x82,0xAB,0x85,0x40,0x5A,0x42,0x0B,0x30,0x48,0xA8,0x2E,0x08,0x81,0x06,0x0B,
++    0x08,0x81,0x02,0x0B,0x08,0x81,0x00,0x0B,0x4E,0x32,0x8A,0x01,0x40,0x53,0x3C,0x90,
++    0x7C,0x90,0x00,0x53,0x41,0x53,0x1C,0x81,0x1C,0xD2,0x00,0x53,0x5E,0x12,0x12,0x09,
++    0x01,0xD3,0x12,0x91,0x02,0x13,0x46,0x0A,0x40,0x23,0x14,0x61,0x1C,0xA2,0x00,0x23,
++    0x40,0x23,0x1A,0xA2,0x02,0x23,0x4A,0x23,0x1A,0xA2,0x08,0x23,0x48,0x23,0x18,0xA2,
++    0x0E,0x23,0x40,0x23,0x1E,0xA2,0x00,0x23,0x42,0x43,0x12,0x01,0x1A,0x82,0x00,0x43,
++    0x00,0xD1,0x04,0xC3,0x02,0x01,0x0F,0xC3,0xE9,0x85,0x40,0xA2,0x40,0x13,0x08,0x09,
++    0x18,0x52,0x00,0x13,0x4C,0x13,0x18,0x52,0x0A,0x13,0x48,0x13,0x1A,0x52,0x0C,0x13,
++    0x40,0x13,0x1E,0x52,0x03,0x13,0x3E,0x82,0x40,0x6A,0x59,0x0B,0x10,0x21,0x18,0x8A,
++    0x18,0x0B,0x58,0x0B,0x10,0x01,0x1A,0x8A,0x18,0x0B,0x58,0x13,0x08,0x01,0x1C,0x52,
++    0x19,0x13,0x40,0x22,0x16,0x01,0x80,0x01,0x02,0x13,0x40,0x13,0x1A,0x52,0x00,0x13,
++    0x48,0xFA,0x40,0x43,0x10,0x01,0x19,0x82,0x03,0x43,0x38,0x82,0xA8,0x85,0x08,0x09,
++    0x00,0x31,0x80,0x07,0xD0,0x3F,0x0D,0x11,0x00,0x21,0x80,0x07,0xD0,0x1F,0x05,0x09,
++    0x85,0x07,0xD0,0xFF,0x00,0x31,0x80,0x07,0xD0,0xE7,0x05,0x21,0x85,0x07,0xD0,0xCF,
++    0x86,0x07,0xD0,0x77,0xE8,0x85,0xA8,0x85,0x40,0x82,0x48,0x5A,0xC0,0xA1,0x12,0x43,
++    0xBA,0xFF,0xF7,0xD7,0x07,0x09,0xB8,0xFF,0xF8,0x77,0x02,0xA1,0xBB,0xFF,0xFF,0x7F,
++    0xBB,0xFF,0xFF,0xFF,0xBE,0xFF,0xFF,0x07,0xBD,0xFF,0xFF,0x7F,0xBE,0xFF,0xFF,0xB7,
++    0x48,0x62,0x00,0x01,0x80,0x43,0xE8,0x85,0x00,0xC0,0x00,0x01,0xC8,0x21,0x01,0x00,
++    0xF8,0xFF,0x07,0x04,0xD8,0x02,0x06,0x00,0x40,0x60,0x07,0x01,0x58,0xC0,0x02,0x01,
++    0x10,0x00,0x00,0x42,0x00,0x00,0x00,0x42,0x80,0x01,0x06,0x42,0xF8,0x00,0x06,0x42,
++    0x18,0x00,0x02,0x42,0x00,0x80,0x00,0x01,0xA8,0x85,0x80,0x07,0xD0,0xEF,0xEA,0x85,
++    0xAF,0x85,0xB8,0xFF,0xF0,0xBF,0xE8,0x85,0xA8,0x7D,0x80,0x04,0x88,0x0C,0xC0,0x0C,
++    0x80,0x14,0xC0,0x04,0x83,0x1C,0x30,0x42,0x40,0x7E,0x80,0x25,0xE8,0x05,0x00,0x00,
++    0xAC,0xFD,0x87,0x1D,0x30,0x32,0x00,0x01,0x82,0x14,0x00,0x9F,0x44,0xFA,0x0F,0x01,
++    0x0C,0x0B,0x26,0x01,0xC2,0x14,0x00,0x28,0x7F,0xE2,0x4F,0xC3,0x1F,0x02,0x09,0xC3,
++    0xD0,0x6C,0x90,0x04,0x14,0x09,0x08,0x01,0x30,0x82,0xD9,0x64,0x86,0x1F,0xD8,0x37,
++    0xF8,0x82,0x33,0x0A,0xCF,0x99,0x49,0xC9,0x99,0x3E,0x40,0x91,0xE7,0x16,0x48,0xC3,
++    0x1F,0x02,0x0D,0xC3,0x40,0x20,0x63,0x01,0x88,0x36,0xD7,0x6C,0x90,0x04,0x10,0x09,
++    0x09,0x01,0x34,0x82,0xD8,0x64,0x80,0x1F,0xDB,0x8F,0xFD,0xA2,0xD0,0x6C,0x90,0x04,
++    0x14,0x09,0x08,0x01,0x30,0x82,0xD9,0x64,0x85,0x1F,0xD8,0x47,0xF8,0xBA,0xD3,0x6C,
++    0x90,0x04,0x10,0x09,0x09,0x01,0x34,0x82,0xD8,0x64,0x80,0x1F,0xDD,0xFF,0x14,0x3A,
++    0xE9,0x16,0x30,0x02,0x30,0xE2,0x31,0x3A,0xFD,0x82,0x13,0xC2,0xE3,0x0E,0x98,0xBA,
++    0x05,0x17,0x10,0x02,0xDB,0x06,0x98,0xA2,0x46,0xE2,0x4E,0x03,0xDE,0x8A,0x0B,0x00,
++    0xC0,0x00,0xCA,0x24,0x00,0x44,0xC0,0x24,0xE0,0x00,0x84,0x24,0xC2,0x14,0xE0,0x00,
++    0x90,0x05,0x86,0x14,0xC8,0x2C,0xC0,0x14,0x15,0x42,0x9C,0x3E,0x87,0x3D,0xE8,0x85,
++    0xAC,0xFD,0x87,0x7D,0x30,0xA2,0x30,0xEA,0xD8,0x0B,0x8B,0x6C,0xD0,0x0B,0x8F,0x64,
++    0x40,0x01,0x80,0x6E,0x48,0x72,0x06,0x99,0x07,0x43,0x12,0xF9,0x58,0x5A,0x96,0x81,
++    0x10,0xD3,0x06,0x43,0x00,0xC1,0x83,0x1F,0xF8,0x77,0xFF,0x84,0xB8,0xA1,0x01,0xD7,
++    0x40,0x3A,0x0E,0x19,0x04,0x0B,0x0A,0x19,0x06,0x0B,0x08,0x09,0xC4,0x84,0x00,0x48,
++    0xC0,0x38,0x12,0x01,0x30,0x5A,0x31,0x8A,0x00,0x09,0x80,0x17,0xD0,0xE7,0x31,0x01,
++    0x30,0x1A,0x11,0x09,0x08,0x01,0x44,0x1D,0xA8,0x04,0x80,0x1F,0xDB,0x7F,0xE2,0xB0,
++    0x91,0xB5,0x77,0x91,0x9D,0xA6,0x47,0xD2,0x40,0x0B,0x10,0x11,0x18,0x8A,0x00,0x0B,
++    0x00,0xE1,0xEC,0x02,0x33,0x00,0xA8,0xE6,0x40,0xB2,0x0D,0x01,0x81,0x0B,0x30,0x12,
++    0x30,0x4A,0x01,0x11,0x84,0x17,0xC8,0x27,0x30,0x1A,0xA9,0x04,0x08,0x01,0x00,0x11,
++    0xD0,0x84,0x80,0x17,0xD0,0x77,0x33,0x01,0xC2,0x64,0x00,0x00,0x80,0x74,0x00,0xBF,
++    0x31,0x5A,0x31,0x92,0x08,0x01,0x00,0x09,0x80,0x17,0xD0,0x6F,0xA8,0x0C,0xA0,0x04,
++    0x30,0xCA,0x41,0x1D,0xD8,0x84,0xD0,0x64,0xBA,0xFF,0xFF,0x17,0xC6,0x74,0xC8,0x38,
++    0x09,0x09,0x30,0x5A,0x30,0x92,0x31,0x42,0x87,0x17,0xC8,0xEF,0xE7,0xB0,0x93,0xB5,
++    0xC4,0x6C,0x10,0x32,0x99,0x26,0x37,0x1A,0xA8,0x04,0x08,0x01,0x00,0x19,0xD0,0x84,
++    0x82,0x17,0xD0,0x3F,0x31,0x12,0x31,0x4A,0x00,0x01,0x80,0x17,0xCD,0x8F,0xDA,0x03,
++    0x41,0x01,0x80,0xF6,0x40,0xBA,0x0C,0x09,0x81,0x0B,0x30,0x12,0x30,0x4A,0x01,0x11,
++    0x82,0x17,0xC8,0x37,0x30,0x5A,0x09,0x01,0x00,0x09,0xD0,0x6C,0x86,0x17,0xC8,0xDF,
++    0x30,0x1A,0xA9,0x04,0x00,0x11,0xD0,0x84,0xC8,0x6C,0x80,0x17,0xD0,0x57,0xA9,0x0C,
++    0xA5,0x04,0xD8,0x13,0x30,0xCA,0x41,0x1D,0xDF,0x84,0xB8,0xFF,0xFD,0x4F,0xD8,0x03,
++    0x06,0x00,0xCA,0x30,0x30,0x1A,0xA9,0x04,0x00,0x19,0xD0,0x84,0xC8,0x6C,0x80,0x17,
++    0xD0,0xC7,0x08,0x09,0x30,0x5A,0x31,0x42,0xD0,0x6C,0x80,0x17,0xC9,0xE7,0x35,0x12,
++    0x30,0x4A,0x01,0x01,0x80,0x17,0xC8,0xE7,0x40,0xF2,0x0B,0x01,0x85,0x0B,0xD8,0x03,
++    0x00,0x27,0x00,0x37,0x05,0x8C,0xE1,0xB0,0xE6,0x00,0x92,0x05,0xD4,0x64,0x10,0x82,
++    0x9B,0xC6,0x57,0xBA,0x40,0x83,0x08,0x11,0x18,0x42,0x04,0x83,0x87,0x9D,0xE8,0x85,
++    0xAC,0xFD,0x87,0x1D,0x30,0x7A,0x50,0x01,0x80,0x16,0x00,0x01,0x80,0x0C,0x00,0x0F,
++    0x00,0x09,0x80,0x0C,0x2A,0x01,0x00,0x47,0xCD,0x64,0x00,0x40,0xC1,0x30,0x32,0x52,
++    0x08,0x19,0xD8,0x6C,0xC0,0x0C,0x80,0x17,0xC9,0x77,0x04,0x41,0x81,0x1F,0xF8,0x5F,
++    0x20,0x09,0xC0,0x34,0x80,0x01,0x84,0x14,0x60,0x81,0x99,0x36,0x0B,0xF9,0x47,0x1A,
++    0x88,0x11,0x18,0x0B,0x42,0x08,0x1B,0x0B,0x03,0x0F,0x40,0x02,0x1F,0x23,0x02,0xF9,
++    0x4F,0xF2,0x82,0x89,0x88,0x01,0x12,0x43,0x00,0x11,0x80,0x1F,0xF8,0xA7,0xC0,0x14,
++    0xE0,0x03,0x44,0x01,0x80,0x3E,0x00,0x51,0x80,0x1F,0xF8,0x6F,0x40,0x83,0x41,0x03,
++    0x30,0x00,0xA8,0x86,0x07,0x5F,0x00,0xF9,0x4C,0xA2,0x82,0x89,0x88,0x01,0x12,0x43,
++    0x00,0x09,0x80,0x1F,0xF9,0x07,0x40,0x83,0x40,0x03,0x30,0x00,0xA3,0x1E,0xE0,0x20,
++    0x93,0x25,0x67,0xF9,0xC9,0x86,0x06,0xE4,0xE1,0xF8,0x35,0x52,0x08,0x09,0xD8,0x6C,
++    0xC0,0x0C,0x80,0x17,0xCB,0x87,0xE2,0x68,0x90,0x6D,0xC7,0x1C,0x15,0x2A,0x9C,0x9E,
++    0x37,0x27,0xAF,0x85,0x80,0x4D,0x34,0x6A,0x34,0xA2,0x00,0x91,0xEF,0x02,0x0A,0xF9,
++    0x88,0x09,0x40,0x01,0x80,0x0E,0x30,0x7A,0x00,0x0F,0x38,0x19,0x17,0xF8,0xD1,0x43,
++    0x85,0x44,0xD0,0x53,0x90,0x3C,0x98,0x24,0xC2,0x44,0x00,0x00,0xC0,0x00,0x86,0x2C,
++    0xD2,0x3C,0x00,0x90,0xC0,0x00,0x84,0x1C,0x45,0xC2,0x11,0x81,0x00,0x13,0x1A,0x0B,
++    0x30,0x01,0x00,0x67,0x4D,0x03,0x01,0x88,0xC0,0x00,0x42,0x03,0x01,0x3B,0x30,0x1A,
++    0x30,0x92,0x09,0x09,0x00,0x01,0x80,0x17,0xCB,0xF7,0xE0,0xB0,0x90,0xB5,0xC7,0x44,
++    0x17,0x32,0x9C,0x7E,0x30,0x01,0x00,0x67,0x4D,0x03,0x03,0x88,0xC0,0x00,0x42,0x03,
++    0x00,0x3B,0x08,0x09,0x31,0x1A,0x31,0x92,0x30,0x42,0x80,0x17,0xCB,0x67,0xE0,0xB0,
++    0x90,0xB5,0xC7,0x3C,0x17,0x32,0x9C,0x7E,0xD8,0x43,0x45,0x01,0x81,0x16,0x41,0x1A,
++    0x44,0x0B,0x96,0x4D,0x89,0x14,0x48,0x4C,0x01,0x0B,0x4E,0x12,0x00,0x09,0x80,0x43,
++    0xD8,0x43,0x85,0x34,0x30,0x01,0x00,0x67,0x55,0x03,0x01,0x88,0xC0,0x00,0x42,0x03,
++    0x01,0x3B,0x30,0x1A,0x30,0x92,0x09,0x09,0x00,0x01,0x80,0x17,0xC3,0x67,0xE7,0xB0,
++    0x90,0xB5,0xC7,0x34,0x17,0x32,0x9C,0x7E,0x48,0xB2,0x00,0x01,0x80,0x43,0x40,0x9A,
++    0xCE,0x14,0x00,0x0B,0x48,0x0B,0x89,0x04,0x30,0x5A,0x11,0x09,0xA0,0x0C,0xC8,0x24,
++    0xC7,0x44,0xB8,0xFF,0xFB,0xAF,0x49,0x0B,0x89,0x04,0x30,0x5A,0x10,0x01,0xA0,0x0C,
++    0xC8,0x2C,0xC0,0x3C,0xB9,0xFF,0xFF,0x67,0xD8,0x43,0x45,0x01,0x80,0xDE,0x70,0x3A,
++    0x44,0x83,0x97,0x3D,0x4F,0x44,0x01,0x83,0x40,0x32,0x08,0x09,0x85,0x0B,0xD8,0x43,
++    0x51,0x0B,0x31,0x5A,0x10,0x09,0xA0,0x0C,0x88,0x04,0x00,0x2F,0x00,0x01,0x00,0x42,
++    0x18,0x00,0x04,0x42,0x00,0xB0,0x00,0x01,0xCF,0x1C,0xB8,0xFF,0xF8,0x8F,0x40,0xDA,
++    0x08,0x01,0x80,0x0B,0x00,0xBB,0x4F,0xD2,0x00,0x01,0x10,0x43,0x4A,0xC2,0xC8,0x01,
++    0x18,0x43,0x80,0x4D,0xEF,0x85,0xAF,0xC5,0x30,0x1A,0x30,0x42,0x34,0xBA,0xD0,0x23,
++    0xD0,0x2B,0x4E,0xA2,0xC0,0xC8,0x8A,0x04,0x30,0xD2,0x31,0xCA,0x80,0x17,0xE8,0xE7,
++    0x30,0x01,0x00,0x3F,0x09,0x09,0x30,0xDA,0x30,0x92,0x31,0x42,0x84,0x17,0xC0,0x9F,
++    0xE7,0xB0,0x93,0xB5,0x17,0x32,0x9D,0xAE,0xC8,0x04,0x10,0x01,0x18,0x01,0x00,0x4F,
++    0x00,0x01,0x00,0x1F,0x82,0x5B,0xE0,0x48,0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0xCE,
++    0xE6,0x90,0x92,0x95,0x17,0x12,0x9D,0x9E,0xE8,0xC5,0x07,0x00,0x00,0xB0,0x00,0x01,
++    0x00,0x01,0x02,0x42,0x30,0x20,0x06,0x00,0x49,0x32,0x41,0x2A,0x05,0x43,0x9E,0xFF,
++    0x7F,0x04,0x3A,0xF7,0x94,0x15,0x3A,0x00,0x77,0x18,0x06,0xF9,0x04,0xC2,0x3C,0x48,
++    0x74,0x48,0x00,0xCA,0x50,0x01,0xD0,0x5E,0x38,0x90,0x78,0x90,0xD4,0x41,0x40,0x98,
++    0x54,0xE2,0x00,0xD8,0xC6,0xD0,0x4C,0x9B,0x18,0x1A,0x1C,0x5A,0x0B,0x9B,0x3E,0x82,
++    0x40,0x98,0x54,0xCA,0x04,0xD8,0xC4,0xD0,0x44,0x9B,0x18,0x1A,0x18,0x5A,0x00,0x9B,
++    0x3A,0x82,0x93,0x05,0x36,0x10,0x76,0x90,0x0C,0x09,0x00,0x8A,0x48,0x00,0x52,0x9A,
++    0x04,0x00,0xC4,0x00,0x03,0x0B,0x38,0x82,0x96,0x05,0x32,0x10,0x70,0x90,0x0E,0x09,
++    0x00,0x8A,0x54,0x72,0x4C,0x00,0x02,0x00,0x94,0x01,0xC4,0x00,0x03,0x0B,0x38,0x82,
++    0xB3,0x15,0x3B,0x82,0xFB,0x85,0x39,0x82,0x40,0x32,0x48,0x0B,0x10,0x21,0x18,0x8A,
++    0x0B,0x0B,0x38,0x82,0x48,0x1A,0x48,0x43,0x14,0x21,0x18,0x82,0x0B,0x43,0x38,0x82,
++    0x07,0x20,0x28,0xD0,0x68,0x07,0x00,0x07,0x20,0x07,0x00,0x07,0x08,0x07,0x00,0x07,
++    0xAC,0xFD,0x87,0x4D,0xD0,0x94,0x30,0x22,0xF0,0x43,0x84,0x0C,0xF8,0x6B,0xC2,0x64,
++    0x08,0x01,0x80,0x0B,0x00,0x01,0x00,0x8F,0x0A,0x21,0x19,0x0A,0x18,0x29,0xCA,0x48,
++    0x0E,0xD8,0xC2,0x48,0xD0,0x4B,0x48,0x79,0x80,0x36,0x80,0x83,0xE0,0x90,0xCA,0x64,
++    0xD8,0x64,0xC0,0x4B,0xE0,0x48,0x82,0xCB,0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0x5E,
++    0xC0,0x64,0xC0,0x03,0x80,0x44,0x40,0x01,0x88,0x0E,0x80,0x6D,0xE8,0x85,0xC7,0x44,
++    0x40,0x09,0x88,0x1E,0xC0,0x0C,0x40,0x09,0x8F,0x06,0x38,0xB7,0x00,0x01,0x80,0x34,
++    0x80,0x2C,0xC8,0x44,0xC4,0x0C,0x10,0x0A,0x88,0x8E,0x02,0x01,0x30,0x01,0x08,0x01,
++    0x88,0x1C,0x88,0x14,0x1A,0x19,0x0A,0xD8,0x00,0x4F,0x10,0x31,0x18,0x52,0xCA,0x90,
++    0xC4,0x90,0x4E,0xBC,0xC6,0xC0,0x49,0x94,0xCA,0xB0,0xE4,0x48,0x90,0x4D,0xD6,0x0C,
++    0x17,0x8A,0x9C,0x96,0xC8,0x0C,0x80,0x1F,0xF0,0xFF,0x83,0x24,0x30,0x82,0xC9,0x0C,
++    0x83,0x1F,0xF0,0xD7,0x30,0x32,0x08,0x01,0x00,0x01,0x00,0xFF,0x1A,0x29,0x0A,0xD8,
++    0x02,0x0F,0xE0,0x48,0x91,0x4D,0x16,0x21,0x18,0x52,0xCA,0x90,0xC0,0x90,0xD6,0x93,
++    0x57,0x79,0x80,0xB6,0x12,0x21,0x19,0x52,0x18,0x19,0xC9,0x90,0x0E,0xD8,0xC4,0x90,
++    0x1E,0x01,0xF0,0x9A,0xFE,0x1C,0xC8,0xD8,0x98,0x1C,0x18,0x11,0xF0,0x9A,0xD6,0x14,
++    0xC0,0xD0,0x94,0x14,0xE6,0x48,0x92,0x4D,0xE6,0x00,0x92,0x05,0xD4,0x44,0x10,0x12,
++    0xC0,0xE6,0xCE,0x44,0xC0,0x1C,0x80,0x1F,0xF0,0x7F,0x32,0x3A,0xC8,0x44,0xC0,0x14,
++    0x82,0x1F,0xF0,0x57,0xCE,0x24,0xD8,0x48,0x89,0x34,0xD0,0x80,0x80,0x2C,0x08,0x01,
++    0x10,0x01,0x00,0x77,0x00,0x01,0x30,0x5A,0x18,0x5A,0xF3,0x5C,0x04,0xD8,0xCA,0xD8,
++    0x02,0x1F,0x00,0x30,0x9A,0xD2,0xE4,0x00,0x95,0x05,0x16,0x42,0x9A,0xCE,0xE7,0x48,
++    0x95,0x4D,0x16,0x4A,0x98,0x76,0x0F,0x01,0x11,0x01,0x00,0xF7,0x1A,0x29,0x0A,0xD8,
++    0x02,0x0F,0xE0,0x48,0x91,0x4D,0x06,0x21,0x18,0x42,0xCA,0x00,0x86,0x3C,0xC0,0x00,
++    0xD0,0x03,0x40,0x79,0x80,0xAE,0x07,0x01,0x01,0x47,0x19,0x19,0xF4,0x3C,0x08,0xD8,
++    0xC0,0x98,0x37,0x01,0x34,0xE2,0xFC,0xF2,0xDA,0x34,0x38,0x19,0xC0,0x98,0x37,0x31,
++    0x19,0x32,0xCA,0xB0,0x0F,0xF8,0xCB,0xB0,0x35,0xB2,0x4D,0xB4,0xD8,0xD8,0xAC,0x06,
++    0x14,0xDA,0x92,0xDD,0x30,0x32,0x3B,0x11,0xF8,0xBA,0xF7,0x2C,0xCB,0xF0,0x35,0xBA,
++    0x4F,0xFC,0xDF,0xB0,0xAB,0x06,0x10,0xB2,0xC8,0xD8,0x34,0xB2,0x18,0x72,0xFB,0x5C,
++    0x07,0xB0,0xCB,0xB0,0x07,0x38,0x9A,0x9A,0xE6,0x00,0x92,0x05,0xDC,0x0C,0x10,0xC2,
++    0x9A,0x9E,0xE6,0x48,0x92,0x4D,0xE6,0x90,0x90,0x95,0xC6,0x64,0xC4,0x03,0x10,0x82,
++    0xC0,0xE6,0xC5,0x64,0xC8,0x0C,0xC0,0x03,0x10,0x42,0xCC,0x06,0x38,0xEF,0xC1,0x0C,
++    0x3F,0xDF,0xA9,0x85,0x80,0x4D,0x34,0x22,0x04,0x71,0xD4,0x1A,0x01,0xC1,0xF0,0x02,
++    0x28,0x71,0x80,0x44,0xF8,0x2A,0xAB,0x3C,0xD8,0x00,0x92,0x05,0x2B,0xD1,0xF8,0x2A,
++    0x30,0x81,0xA8,0x34,0xF8,0x32,0xB5,0x2C,0xD9,0x68,0x95,0x6D,0xC0,0x33,0x77,0x09,
++    0x8D,0x16,0x10,0x04,0x10,0x2C,0x07,0x7F,0x55,0x3C,0x05,0xF0,0x31,0xE2,0xC5,0xB0,
++    0x54,0x04,0x07,0x38,0xCB,0xE8,0x33,0x3A,0xD9,0xB0,0x97,0xB5,0xD0,0x40,0x91,0x2D,
++    0x85,0x80,0x85,0x68,0x17,0x04,0x15,0x2C,0xF1,0x3C,0xC0,0x80,0x04,0x30,0xCA,0x00,
++    0xF4,0x44,0xC8,0x00,0x80,0x00,0x94,0x05,0xF3,0x2C,0xC8,0xA8,0x05,0x70,0xCB,0x68,
++    0xF5,0x34,0xC8,0x68,0x81,0x68,0x95,0x75,0x90,0x01,0x46,0x01,0xD0,0x0E,0x00,0x01,
++    0x00,0x27,0x40,0xAC,0x10,0x2A,0xD4,0x0E,0x00,0x01,0xF0,0x82,0x70,0x01,0xD0,0x0E,
++    0x30,0x01,0x00,0x27,0x45,0xAC,0x12,0xAA,0xD0,0x0E,0x30,0x11,0xF8,0xB2,0x4C,0x41,
++    0x80,0x0E,0x48,0x49,0x88,0xBE,0xD0,0x3C,0xD0,0x90,0xA8,0x06,0x14,0x92,0x92,0xAD,
++    0xD4,0x2C,0xD8,0x90,0xAA,0x06,0x10,0x92,0xCC,0x90,0x92,0xAD,0x10,0xEA,0xCC,0x06,
++    0x30,0xEA,0x48,0x49,0x8B,0x16,0x20,0x48,0x60,0x68,0x00,0x37,0x4D,0xC8,0x10,0x4A,
++    0xC8,0x1E,0x30,0x6A,0x00,0x0F,0x30,0xEA,0x00,0x6A,0xD6,0x3C,0xD8,0xC8,0x8A,0x24,
++    0x1C,0x8A,0x02,0x50,0xC4,0x48,0x34,0x62,0xC8,0x24,0x10,0x51,0x05,0x78,0xF2,0x12,
++    0xCA,0x48,0x1E,0x52,0x20,0x12,0x8B,0x1C,0x43,0xC8,0x1A,0x42,0xC6,0x00,0x02,0x00,
++    0xC0,0x00,0x8C,0x14,0x00,0xC8,0x8E,0x0C,0x82,0x1F,0xE8,0xA7,0x30,0x3A,0xC0,0x2C,
++    0xCA,0x24,0x18,0x0A,0x00,0x40,0xC4,0x40,0x15,0x61,0xF0,0x12,0xCA,0x1C,0x18,0x52,
++    0xC0,0x80,0xC8,0x14,0x1B,0x72,0xC3,0x88,0x00,0x48,0xC6,0x40,0xC8,0x0C,0x80,0x1F,
++    0xE8,0x0F,0xCA,0x3C,0x08,0x0C,0xCB,0x2C,0x08,0x0C,0xCD,0x44,0xD0,0xC8,0xAB,0x06,
++    0x10,0x4A,0x92,0x55,0xCA,0x34,0xD0,0x08,0xAA,0x06,0x10,0x4A,0x90,0x4D,0x50,0x19,
++    0xD8,0x46,0xD0,0x44,0x10,0xD2,0xCD,0x0E,0xE0,0xF8,0x03,0x1F,0xD5,0x44,0x10,0xD2,
++    0x93,0x06,0xF0,0xF8,0x48,0x19,0xD8,0x46,0xCC,0x34,0x10,0x0A,0xCA,0x0E,0xE0,0x00,
++    0x00,0x1F,0xC8,0x34,0x10,0x0A,0x94,0x06,0xF7,0x00,0x0A,0x3C,0x10,0x04,0x81,0x4D,
++    0xEF,0x85,0xAF,0xF5,0x30,0xB2,0xD0,0x44,0x60,0xCA,0xCF,0xE0,0x2F,0x31,0x78,0xC2,
++    0x1F,0xAA,0xC3,0x68,0xFF,0xE1,0xC9,0x68,0x07,0xB0,0xC3,0x98,0x72,0xA2,0xF7,0x81,
++    0xCA,0xF0,0xFC,0x9B,0x36,0xBA,0xB8,0x01,0x32,0xE2,0xFD,0x01,0xBA,0x0C,0xF8,0x01,
++    0xB8,0x04,0x40,0x09,0x88,0x36,0x01,0x01,0x01,0xFF,0xC0,0x0B,0x48,0x79,0x88,0xCE,
++    0x47,0x4C,0x09,0x0C,0x41,0x7C,0x13,0x3C,0xC1,0x93,0x89,0x13,0xC3,0x93,0x8B,0x13,
++    0x1F,0x0C,0x1D,0x3C,0x23,0x0C,0x21,0x3C,0x0D,0x0C,0x0B,0x3C,0x41,0x4C,0x19,0x0C,
++    0x43,0x4C,0x1B,0x0C,0x80,0x03,0x09,0x09,0x85,0x0B,0x8F,0x0B,0x30,0x0A,0xDB,0x4B,
++    0x90,0x0B,0x01,0x27,0xA2,0x21,0xE1,0x00,0x94,0x05,0x16,0xC2,0x9C,0xEE,0x16,0xC2,
++    0x92,0x9E,0x03,0x87,0x02,0x21,0x19,0x0A,0xC8,0x60,0x08,0x41,0x41,0x44,0x19,0x04,
++    0x01,0x11,0xF0,0x42,0x1D,0x04,0xCB,0x1B,0x58,0x09,0x88,0xA6,0x18,0xC1,0x38,0xE1,
++    0xF7,0x1A,0xFF,0x3A,0xD8,0xD8,0xAE,0x06,0x14,0xDA,0x92,0xFD,0x1F,0xF1,0xF0,0x1A,
++    0xD0,0x00,0xAE,0x06,0x14,0x02,0x92,0x05,0xD9,0x0C,0xC0,0xC0,0xDC,0xDB,0x10,0xC2,
++    0xC8,0x0E,0x00,0x01,0x88,0x03,0x05,0xC1,0x19,0x01,0xF1,0x02,0xF6,0x1A,0xD7,0x00,
++    0xAA,0x06,0x10,0x02,0x90,0x3D,0x04,0xD1,0x19,0x11,0xF1,0x02,0xF6,0x1A,0xD7,0x00,
++    0xAA,0x06,0x10,0x02,0xCC,0x00,0x96,0x05,0xD4,0x1B,0x11,0x1A,0xC8,0x2E,0xD8,0x04,
++    0xC6,0x03,0xDF,0xDB,0xE4,0xD8,0x12,0xC2,0xC0,0x86,0xD8,0x04,0xC6,0x03,0xDF,0xDB,
++    0xE4,0xD8,0x12,0xC2,0xCB,0x1E,0x30,0x02,0xD8,0x03,0x48,0x00,0x91,0x03,0x59,0x04,
++    0x23,0x04,0x59,0x04,0x21,0x04,0x33,0x02,0xBD,0xFF,0xF7,0x9F,0xC3,0x03,0x47,0xF9,
++    0x92,0x0E,0xE0,0x00,0x85,0x03,0x47,0x44,0x10,0x04,0x03,0x19,0x80,0x03,0xC3,0x0C,
++    0xDC,0x03,0x82,0x01,0x89,0x03,0xCF,0x03,0xC2,0x8B,0xD1,0x00,0xE0,0x00,0x42,0x11,
++    0xC3,0x2E,0xC8,0x03,0xC2,0x8B,0xD3,0x00,0xE0,0x00,0x42,0x11,0xCF,0x4E,0xC0,0x03,
++    0x40,0x11,0x98,0x36,0xCC,0x04,0xD8,0x4B,0x10,0x42,0xC4,0x16,0x07,0x01,0x80,0x03,
++    0x89,0x03,0xC7,0x83,0x8B,0x03,0xC1,0x83,0x8F,0x03,0xEB,0xF5,0xAF,0x85,0x47,0xF9,
++    0x88,0x0E,0x00,0x01,0xE9,0x85,0x27,0x21,0x1C,0x02,0x63,0xEA,0xC0,0x00,0xCC,0x00,
++    0x23,0x31,0x18,0x0A,0xC4,0x48,0x54,0xD2,0xD4,0xE1,0xC1,0x50,0x0A,0xA1,0xF0,0x0A,
++    0x48,0x01,0xD0,0x06,0x10,0x4A,0x22,0xB1,0xF8,0x22,0x60,0x01,0xD3,0x06,0x10,0x22,
++    0xCC,0x48,0x60,0xA2,0x10,0x0A,0x9D,0x06,0x08,0x01,0x28,0x71,0x42,0xA4,0xF8,0x2A,
++    0xD8,0x20,0xAB,0x06,0x10,0x22,0x2B,0x81,0x42,0x94,0xFA,0x2A,0xD8,0x90,0xAA,0x06,
++    0x15,0x92,0xC2,0x28,0x34,0xE2,0xA0,0x01,0x4C,0x14,0x33,0xA2,0x10,0x52,0xC5,0xF6,
++    0xC8,0x13,0x54,0x09,0x8B,0x26,0xD8,0x3B,0xCB,0x33,0xF6,0xF8,0x10,0xF2,0xDD,0xA6,
++    0x50,0x09,0x88,0x3E,0xD4,0x23,0x11,0x62,0x9E,0x26,0xC0,0x03,0x40,0xF1,0xC0,0x0E,
++    0x40,0x29,0x90,0x56,0x50,0x09,0x88,0x16,0x51,0xC4,0x46,0x81,0x98,0x2E,0x50,0x09,
++    0x8B,0x2E,0x30,0x02,0x05,0x00,0x12,0x42,0xC0,0x0E,0x00,0x01,0xE8,0x85,0x07,0x09,
++    0xEF,0x85,0xAF,0xFD,0x84,0x65,0x34,0xB2,0x08,0x01,0x28,0x01,0x00,0x01,0x80,0x1C,
++    0xC2,0xAC,0xF8,0x23,0x04,0x01,0x30,0x22,0x80,0x3C,0x00,0x27,0xD7,0x6C,0x00,0xF9,
++    0xA2,0x82,0xE2,0x48,0x95,0x4D,0x16,0x0A,0x98,0xC6,0xD7,0x7C,0x28,0x92,0xC3,0x26,
++    0xC0,0x7C,0x80,0x2C,0x30,0x82,0x83,0x24,0x03,0x1F,0x30,0x82,0x80,0x2C,0xC0,0x7C,
++    0x80,0x24,0x00,0x01,0x82,0x34,0x00,0xD7,0x1A,0x01,0x00,0xB7,0x36,0x02,0x03,0xC2,
++    0x3A,0x00,0x8E,0x86,0x40,0x1A,0x83,0x44,0x00,0x01,0xD0,0xAC,0xF4,0x64,0xF0,0x93,
++    0x90,0x5C,0x30,0xD2,0x1A,0x12,0x03,0xB8,0xC8,0xD0,0x95,0x54,0x00,0x6F,0xF0,0x3C,
++    0x07,0x32,0x3E,0x90,0x88,0x3E,0xF0,0x54,0x07,0x38,0xDA,0xB2,0xFD,0x44,0x10,0xF2,
++    0x90,0x0E,0xB0,0x44,0x32,0x0A,0xE0,0x00,0x90,0x05,0xD6,0x5C,0x17,0x12,0xC4,0x76,
++    0x70,0xA2,0x02,0x01,0x00,0x78,0xBA,0x4C,0x03,0x87,0x30,0x3A,0x07,0x3A,0x3E,0xF8,
++    0x88,0x56,0x30,0x3A,0x18,0x3A,0xD3,0x64,0x05,0xF8,0xC3,0xF8,0xD5,0x4C,0xD0,0xFA,
++    0x10,0xBA,0xC5,0x0E,0x30,0xF2,0x31,0x2A,0xE6,0x00,0x92,0x05,0x2F,0x82,0x9B,0x66,
++    0x10,0xEA,0x8C,0xA6,0xC4,0x1C,0xC8,0x00,0x80,0x1C,0xC0,0x34,0xE6,0x00,0x92,0x05,
++    0x80,0x34,0xC0,0x6C,0xA0,0x2A,0x32,0x09,0x30,0x82,0xD1,0x3C,0x00,0x42,0x1C,0x82,
++    0x90,0x05,0x84,0x3C,0x03,0x72,0x35,0x02,0x1D,0x32,0x90,0x85,0x30,0x22,0xD4,0x2C,
++    0xC4,0x34,0x10,0x82,0x82,0x1E,0xE0,0xD8,0x93,0xDD,0x2E,0x9A,0x98,0x36,0xD5,0x2C,
++    0xC4,0x34,0x10,0x82,0x98,0x06,0xC5,0x1C,0x80,0x44,0x10,0x01,0x00,0x01,0x08,0x01,
++    0x30,0x5A,0x83,0xCB,0x18,0x01,0x08,0x01,0x33,0x62,0x34,0x4A,0xE0,0x4A,0x00,0x0F,
++    0xE6,0x48,0x92,0x4D,0x36,0xEA,0x00,0x6A,0x3F,0x68,0x8F,0xCE,0xED,0x24,0x10,0x4A,
++    0x98,0xD6,0x40,0x01,0x8F,0x8E,0x08,0xF9,0x00,0x5F,0xD0,0x6C,0xE3,0x9A,0x28,0x9A,
++    0x90,0x1E,0xD0,0xAC,0xF4,0x93,0x14,0x12,0xC0,0x0E,0xD0,0x6C,0xA2,0x8A,0xE0,0x00,
++    0x95,0x05,0x16,0x02,0x98,0x8E,0x87,0x85,0xEA,0x85,0xF7,0x00,0x93,0x05,0x36,0x4A,
++    0xE0,0x4A,0x28,0x09,0x31,0x62,0x05,0x47,0x33,0x6A,0x18,0x2A,0xFB,0x64,0x00,0x70,
++    0xCA,0xB0,0x07,0x38,0xDD,0xAA,0xC7,0x50,0x2C,0x09,0x00,0x6A,0x1D,0xEA,0x90,0x5D,
++    0x31,0x72,0xA3,0x8A,0xED,0x44,0x10,0x52,0x98,0x16,0x28,0x11,0x30,0x62,0x05,0xA7,
++    0xFA,0x7C,0xE0,0x28,0x10,0xEA,0x9D,0x6E,0x90,0x44,0x08,0x01,0x00,0x27,0xF8,0x6C,
++    0xE3,0xAA,0xA3,0xEA,0xE6,0x48,0x92,0x4D,0x17,0x0A,0x9D,0xC6,0xE0,0x8A,0x29,0x09,
++    0x30,0x62,0x05,0x17,0x90,0x45,0x2F,0x01,0xA3,0xAA,0x31,0x2A,0x6D,0x01,0x80,0x56,
++    0x33,0x6A,0x18,0x2A,0xFB,0x64,0x00,0x70,0xCA,0xB0,0x07,0x38,0xDA,0xAA,0xDF,0x90,
++    0x2C,0x09,0x00,0x6A,0x1B,0x5A,0x35,0x6A,0xE2,0x4A,0xE1,0x48,0xA4,0x4A,0x39,0xD7,
++    0x40,0x40,0x05,0x00,0xF8,0xFF,0x07,0x00,0xAC,0x85,0x87,0x2D,0x33,0x72,0xF8,0x8B,
++    0x8C,0x14,0x50,0xCA,0xC0,0x20,0xA4,0x24,0xC9,0x14,0x18,0x21,0x31,0xBA,0x31,0xAA,
++    0x1A,0xCA,0xBA,0x01,0xA8,0x01,0xC6,0x40,0xC0,0x00,0x84,0x1C,0x01,0x67,0xC2,0x03,
++    0x42,0x79,0x80,0x46,0xC8,0x03,0x37,0x08,0xA0,0xA6,0x41,0x21,0x88,0x16,0x01,0x71,
++    0xF0,0x02,0x81,0x0C,0x01,0x81,0xF0,0x02,0x81,0x04,0x30,0x92,0x09,0x49,0x30,0x02,
++    0xB8,0xFF,0xEF,0xFF,0x0B,0x71,0xF0,0x0A,0xC0,0x0C,0xD0,0x40,0xAA,0x06,0x10,0x02,
++    0x90,0x0D,0x00,0x81,0xF0,0x02,0xD1,0x04,0xD0,0x00,0xAC,0x06,0x12,0x02,0xC2,0x00,
++    0x91,0x05,0xD8,0x4B,0x44,0x48,0x14,0x0A,0xE8,0x5E,0xC0,0x0C,0x08,0x04,0xC7,0x04,
++    0x10,0x04,0x01,0x37,0x40,0x21,0x90,0x26,0xF8,0x83,0x41,0x11,0x91,0x0E,0x00,0x01,
++    0x87,0x03,0x05,0xF9,0x8B,0x03,0x89,0x03,0xC7,0x03,0xDF,0xCB,0x10,0x42,0xC4,0x0E,
++    0x07,0x01,0x88,0x03,0xCA,0x03,0x37,0x00,0x77,0x00,0x8A,0x03,0x40,0x01,0x80,0x0E,
++    0xF7,0x00,0x8A,0x03,0xC8,0x03,0x47,0x01,0x8B,0x2E,0xC0,0x03,0x44,0x00,0x04,0x00,
++    0x80,0x03,0x03,0x01,0x81,0x03,0xA5,0x21,0xC5,0x1C,0x10,0x02,0xC0,0x7E,0x0D,0x01,
++    0x11,0x01,0xB8,0x93,0xC0,0x24,0x00,0x87,0xC0,0x1B,0xE0,0x14,0x10,0x1A,0x95,0x56,
++    0xC7,0x1B,0xDE,0xE3,0x32,0xD8,0x72,0xD8,0x10,0x1A,0xCD,0x26,0xC1,0x1B,0x5C,0x01,
++    0x80,0x0E,0x08,0x09,0x04,0x27,0x80,0x13,0x80,0x21,0xD9,0x1C,0x17,0x1A,0xC4,0x5E,
++    0x49,0x01,0x80,0x5E,0xC1,0x24,0x00,0x37,0x80,0x13,0xC4,0x0B,0xDC,0x14,0x10,0xCA,
++    0x96,0x06,0xC1,0x0B,0xDA,0xDB,0x37,0x48,0x74,0x48,0x12,0xCA,0xC8,0xD6,0x08,0x09,
++    0x81,0x0B,0xFC,0x8B,0xE1,0x48,0xBA,0x8B,0x0A,0x71,0xF0,0x0A,0x48,0x01,0xD0,0x0E,
++    0x08,0x14,0x06,0x27,0x44,0x5C,0x11,0xCA,0xE9,0x0E,0x40,0x4C,0x08,0x0C,0x0E,0x81,
++    0xF0,0x0A,0x4A,0x01,0xD0,0x0E,0x10,0x14,0x03,0x27,0x40,0x5C,0x10,0xCA,0xEC,0x0E,
++    0x40,0x4C,0x13,0x0C,0x80,0x21,0xC9,0x1C,0x16,0x0A,0xC4,0xAE,0x87,0x2D,0xE8,0x85,
++    0xAC,0x85,0x87,0x3D,0x30,0x2A,0x30,0x62,0x41,0x1A,0xC2,0x40,0x08,0xB9,0xED,0x4A,
++    0x4B,0x29,0x80,0xE6,0x0C,0x09,0x06,0x48,0xC2,0x70,0x4B,0x02,0xC0,0x48,0x8B,0x1C,
++    0x0E,0x19,0x03,0x48,0xC0,0x48,0x8B,0x14,0x0F,0x01,0x10,0xF9,0x18,0x79,0x00,0x3F,
++    0xA6,0x92,0xCB,0x3B,0x78,0x01,0x88,0x06,0x82,0x1B,0xE0,0x48,0x91,0x4D,0x86,0x21,
++    0xFC,0x3B,0x13,0x7A,0xC0,0xA6,0x07,0x01,0x85,0x34,0xF0,0x03,0x42,0x01,0x80,0xCE,
++    0xB1,0x04,0x30,0x0A,0x30,0x42,0x59,0x2D,0xD7,0x14,0xB8,0xFF,0xD8,0x0F,0x84,0x34,
++    0xC0,0x34,0x40,0x01,0x88,0x76,0x30,0x01,0x01,0x47,0x30,0x5A,0x37,0x92,0x09,0xF9,
++    0x00,0x09,0xA0,0x04,0xB8,0xFF,0xEF,0xEF,0xE7,0xB0,0x93,0xB5,0xF5,0x03,0x15,0x82,
++    0xC1,0x9E,0x07,0xFF,0xC0,0x34,0x40,0x09,0x89,0x96,0xC0,0xB3,0x31,0x1A,0x31,0x52,
++    0x09,0x01,0x30,0x82,0xBE,0xFF,0xEF,0x17,0x40,0x01,0x80,0x0E,0x00,0x01,0x00,0x07,
++    0x01,0x09,0x30,0x5A,0x11,0x01,0x30,0x8A,0xA7,0x04,0xB8,0xFF,0xE9,0x17,0x00,0x4F,
++    0xA5,0x04,0xF0,0x3B,0x30,0x5A,0xEB,0xD3,0x30,0xDA,0xC9,0x1C,0xC7,0x14,0xB8,0xFF,
++    0xF0,0x07,0x38,0x01,0x00,0xDF,0xC0,0x1C,0xEF,0x02,0x46,0xF9,0x81,0x16,0xE0,0x82,
++    0x80,0x24,0x00,0x0F,0x00,0xF9,0x87,0x24,0x31,0x1A,0x31,0x52,0x30,0xCA,0xC1,0x24,
++    0xBC,0xFF,0xEF,0xE7,0x40,0x01,0x80,0x0E,0x00,0x01,0x00,0x07,0x01,0x09,0x30,0x5A,
++    0x30,0xD2,0xA1,0x04,0xCF,0x24,0xB8,0xFF,0xE3,0xE7,0xE6,0xF8,0x95,0xFD,0xF7,0x03,
++    0x17,0xC2,0xC5,0x06,0x31,0x0A,0x31,0x42,0xD7,0x34,0xB8,0xFF,0xF0,0x6F,0x86,0x3D,
++    0xE8,0x85,0x07,0x01,0x38,0x82,0x03,0x00,0x40,0x40,0x05,0x00,0x18,0x70,0x00,0x00,
++    0xAE,0xFD,0x87,0x5D,0xC2,0xAC,0xDA,0x03,0x82,0xD4,0xC1,0xAC,0xD9,0x03,0x80,0xCC,
++    0x01,0x09,0x58,0x45,0x89,0xC3,0xC0,0xCC,0xE2,0x00,0x8A,0xC3,0xC4,0xCC,0x89,0xC3,
++    0xC2,0xCC,0xF1,0x00,0x8A,0xC3,0xC6,0xAC,0x82,0x01,0x86,0x54,0xE0,0x0B,0x00,0x21,
++    0x1A,0x0A,0xC0,0x54,0xA2,0x0B,0xC0,0xAC,0xCA,0x03,0x42,0x00,0x80,0xDC,0x09,0x01,
++    0x40,0xBD,0x31,0x52,0x00,0x36,0x00,0x01,0x82,0xFC,0xC0,0xAC,0xCD,0xB4,0x82,0x01,
++    0x82,0x4C,0xC2,0xAC,0x82,0x01,0x84,0x44,0xC0,0x74,0x4A,0x11,0x92,0x05,0x82,0x3C,
++    0xC2,0x6C,0x92,0x05,0x83,0x34,0x82,0xBE,0x10,0x01,0x00,0x01,0x4C,0x4D,0xB1,0x4A,
++    0x8F,0x2C,0x4A,0xF2,0xB2,0x4A,0x8C,0x24,0x48,0xE2,0xEF,0x48,0xB2,0x4A,0x8C,0x1C,
++    0x04,0x08,0xC4,0x48,0x91,0x4D,0x66,0xA5,0xDB,0x74,0xA2,0x1A,0x62,0x8D,0xD9,0x6C,
++    0xA2,0x1A,0xDB,0x24,0x9A,0x3C,0xD9,0x1C,0x9A,0x34,0xD9,0x2C,0x98,0x2C,0x41,0x09,
++    0x89,0x5E,0xD8,0x3C,0x12,0xDA,0x92,0xDD,0x99,0x3C,0xD9,0x34,0x12,0xDA,0x92,0xDD,
++    0x99,0x34,0xD9,0x2C,0x12,0xDA,0x92,0xDD,0x9A,0x2C,0xD9,0x5C,0x32,0xE2,0xDC,0x64,
++    0x9A,0x64,0xD9,0x34,0xE1,0x3C,0xEA,0x34,0xCA,0xD8,0x92,0xDD,0xEB,0x3C,0xC9,0x20,
++    0x91,0x25,0xF3,0x2C,0xED,0x64,0xC9,0x68,0xA8,0x64,0x59,0x01,0xD9,0x86,0xEB,0xD4,
++    0x13,0x5A,0xD5,0x6E,0x63,0x01,0xD8,0x5E,0xED,0xCC,0x11,0x62,0xD1,0x46,0xEB,0x64,
++    0xC5,0x6B,0x49,0x68,0x8B,0x06,0x32,0x2A,0x3F,0x01,0xF8,0x7A,0xEB,0x2C,0x01,0x68,
++    0x23,0x62,0x35,0x32,0x2B,0x01,0xF8,0xAA,0xF5,0xDC,0x11,0xAA,0xEA,0xC6,0xF2,0xB4,
++    0x71,0x09,0x88,0x16,0xD9,0xF0,0x93,0xB5,0xB2,0x9C,0xF8,0x5C,0x35,0x01,0xF8,0xF2,
++    0x10,0x72,0xDD,0x06,0x35,0xAA,0x81,0x68,0x01,0x68,0x33,0x7A,0xF3,0x9C,0x10,0x6A,
++    0x12,0xAA,0xE5,0x2E,0x6B,0xA5,0xA1,0x62,0x6B,0x8D,0xA1,0x5A,0x01,0xA8,0x72,0xBD,
++    0xC9,0x68,0xE5,0x72,0xE1,0xB0,0xA3,0x72,0xEB,0xFC,0xE0,0x68,0x90,0x6D,0xAF,0xFC,
++    0xF5,0x9C,0x10,0xBA,0xD1,0xBE,0x05,0x9F,0x09,0xEF,0x6A,0xA5,0xA1,0x62,0x6B,0x8D,
++    0xA2,0x5A,0x03,0xB0,0x6B,0xBD,0xC9,0xA8,0xE3,0x72,0xE1,0xB0,0xA0,0x72,0xE9,0xFC,
++    0xE7,0x68,0x93,0x6D,0xAD,0xFC,0x38,0x37,0xE9,0x64,0xC1,0x6B,0x48,0x68,0x6D,0x19,
++    0x8A,0x6E,0x00,0xB0,0x7F,0xBD,0xC9,0xB0,0xE0,0xB2,0x71,0x09,0xC2,0x3E,0xC0,0x64,
++    0x08,0x01,0xC6,0x03,0x1A,0x42,0xC8,0x64,0x82,0x43,0x80,0x7D,0xE8,0x85,0x6F,0x11,
++    0x89,0x56,0x68,0xA5,0xA1,0x62,0x63,0x8D,0xA2,0x1A,0x03,0x98,0x4A,0xBD,0xC1,0xC8,
++    0xE2,0x5A,0xE0,0xD8,0xA0,0x5A,0x00,0x1F,0xCA,0x4C,0xF2,0x4B,0x4F,0x51,0x90,0x66,
++    0xE6,0x00,0x92,0x05,0x40,0x11,0x90,0x06,0x3A,0xD7,0xE2,0x90,0x90,0x95,0x56,0x21,
++    0x92,0x06,0x38,0x57,0x01,0x01,0x80,0x6C,0xC0,0xB4,0x42,0x09,0x88,0xF6,0x03,0x01,
++    0x80,0x84,0x01,0x01,0x81,0x7C,0xC9,0x84,0x42,0xBD,0x01,0x48,0xC2,0x40,0x80,0x14,
++    0xC1,0x7C,0xC9,0x84,0x02,0x00,0xC4,0x00,0x91,0x05,0x86,0x54,0xCA,0x7C,0xC1,0x14,
++    0xE0,0x2A,0x6A,0x09,0xC1,0x26,0xC0,0x6C,0xE6,0x00,0x92,0x05,0x87,0x6C,0x01,0x8F,
++    0xC0,0x7C,0x41,0x09,0x89,0x16,0xC0,0x84,0x47,0x01,0x88,0xC6,0x08,0x81,0x41,0x45,
++    0x86,0x1F,0xC0,0x77,0xC0,0x6C,0x82,0x3C,0xC0,0x74,0x82,0x34,0xC0,0x5C,0x82,0x0C,
++    0xC0,0x64,0x82,0x04,0xC4,0x84,0xE1,0x00,0x3C,0x00,0x7C,0x00,0x50,0x5A,0xB4,0xA2,
++    0xE8,0x98,0xB0,0xCA,0x31,0x62,0x74,0x4D,0xB1,0x8A,0xC1,0x84,0xB0,0x82,0x80,0x24,
++    0xC0,0x84,0xB1,0xC2,0x81,0x1C,0xD0,0x84,0xB0,0x82,0x85,0x14,0xC0,0x7C,0x41,0x09,
++    0x88,0x5E,0xC0,0x24,0x12,0x02,0x92,0x05,0x80,0x24,0xC0,0x1C,0x12,0x02,0x92,0x05,
++    0x80,0x1C,0xC0,0x14,0x12,0x02,0x92,0x05,0x80,0x14,0x00,0x01,0x83,0x2C,0xE0,0x68,
++    0xAD,0xF4,0x01,0x9F,0x40,0x61,0x98,0x66,0xC8,0x24,0xC0,0x34,0xD2,0x54,0xD1,0x00,
++    0x4C,0xA5,0xA1,0x42,0xC8,0x1C,0xC0,0x3C,0xD2,0x54,0xD1,0x00,0x4C,0x8D,0xA1,0x42,
++    0x00,0x47,0x15,0x01,0xDC,0x0C,0x00,0x28,0xF0,0xD2,0x5C,0x45,0x88,0xD2,0x12,0x01,
++    0x90,0x74,0xD1,0x3C,0x92,0x95,0x92,0x0C,0xD2,0x34,0x90,0x95,0x91,0x04,0xD2,0x74,
++    0x50,0x09,0x88,0x3E,0x12,0x12,0x93,0xA5,0x32,0x12,0x13,0x92,0x94,0x95,0x32,0xA2,
++    0x12,0x4A,0x92,0x4D,0xD2,0x0C,0xDA,0x04,0xF0,0x0C,0x00,0x07,0x01,0xEF,0xB4,0x24,
++    0xF1,0x04,0xB0,0x64,0x01,0x70,0xB2,0xFC,0x22,0x12,0x93,0x95,0xCA,0xD8,0x90,0xDD,
++    0xF9,0x24,0xF1,0xFC,0xC9,0xB0,0xB7,0x24,0xF3,0x64,0xC1,0xB0,0xB0,0x64,0x51,0x01,
++    0xD9,0xBE,0xF0,0xD4,0x10,0x92,0xD5,0xA6,0x58,0x01,0xD8,0x96,0xF5,0xCC,0x11,0x9A,
++    0xD1,0x7E,0xF8,0x24,0x35,0x01,0xF8,0xF2,0xF9,0x64,0xC1,0xFB,0x48,0xF8,0x8D,0x46,
++    0xFD,0xDC,0x11,0xF2,0xE8,0x2E,0x78,0x45,0xCD,0xFA,0xCB,0xF0,0x7B,0x45,0x88,0xF2,
++    0x39,0xD7,0xD6,0x74,0xE6,0x90,0x92,0x95,0x91,0x74,0xD1,0x74,0x55,0x11,0x98,0xF6,
++    0x41,0x01,0x80,0xF6,0xF2,0x10,0xF2,0x44,0x00,0x90,0x5C,0x45,0xC7,0xD2,0xCC,0xB3,
++    0xCC,0xDA,0xCA,0xB0,0x11,0xF2,0x94,0x86,0xD0,0x2C,0x50,0x09,0x88,0x8E,0xD1,0x24,
++    0xC1,0x34,0xD8,0x54,0xD1,0x00,0x54,0xA5,0xA0,0x82,0xDE,0x1C,0xD1,0x3C,0xE8,0x54,
++    0xD1,0x90,0x5E,0x8D,0xA8,0xD2,0xEA,0x14,0xDA,0x04,0xD8,0xE8,0x36,0x1A,0xD3,0x90,
++    0x90,0x95,0xDA,0x00,0x93,0x1D,0xD2,0x40,0x2C,0x01,0x30,0x01,0x50,0x01,0xD8,0x56,
++    0xFD,0xD4,0x11,0xD2,0xD0,0x3E,0x58,0x01,0xD9,0x2E,0xF8,0xCC,0x10,0xDA,0xD5,0x16,
++    0xC1,0x3B,0x18,0xBA,0x83,0x3B,0x20,0x12,0x90,0x95,0xCA,0xD8,0x92,0xDD,0xC2,0x00,
++    0xE7,0x68,0x93,0x6D,0x6F,0x11,0xC8,0x4E,0x04,0xE7,0x10,0x9A,0x90,0x0E,0x10,0x09,
++    0x90,0x2C,0xD8,0x24,0xD6,0x34,0xC0,0x90,0x90,0x95,0x96,0x34,0xD8,0x1C,0xD0,0x3C,
++    0xC6,0x90,0x96,0x95,0x90,0x3C,0xD0,0x14,0xDA,0x0C,0x00,0x90,0xC0,0x90,0x96,0x0C,
++    0xD8,0x14,0xD0,0x04,0xC0,0x90,0x96,0x04,0xE6,0x00,0x92,0x05,0xD4,0xF4,0x11,0x82,
++    0x92,0x06,0x38,0x3F,0xC2,0x7C,0xE1,0x00,0x91,0x05,0x86,0x7C,0xC0,0x7C,0x41,0x11,
++    0x97,0x06,0x30,0xAF,0xC2,0x84,0xE1,0x00,0x91,0x05,0x86,0x84,0xC0,0x84,0x41,0x21,
++    0x97,0x06,0x30,0x37,0x00,0x0F,0x00,0x41,0x81,0x6C,0xC1,0x6C,0x41,0x41,0x88,0xD6,
++    0x10,0x01,0x00,0x01,0x58,0x8A,0xE8,0xC8,0xB4,0xF2,0xB4,0x7A,0x31,0x8A,0x31,0xDA,
++    0x40,0x09,0x88,0x1E,0x12,0x4A,0x92,0x4D,0x12,0xDA,0x92,0xDD,0xE7,0x6C,0xC2,0x18,
++    0x92,0xDD,0xE2,0x74,0xC2,0x08,0x93,0x65,0x04,0x08,0xC4,0x48,0x90,0x4D,0x5E,0x01,
++    0xD9,0x76,0xE8,0xD4,0x10,0x5A,0xD5,0x5E,0x60,0x01,0xD8,0x4E,0xED,0xCC,0x11,0x62,
++    0xD1,0x36,0x68,0xA5,0xA1,0x62,0x63,0x8D,0xA0,0x1A,0x03,0x3F,0xE8,0x62,0x00,0x00,
++    0x62,0xA5,0xD9,0x74,0xA1,0x1A,0x63,0x8D,0xDB,0x6C,0xA2,0x1A,0xE6,0x00,0x92,0x05,
++    0x46,0x11,0x98,0x9E,0xE6,0x90,0x92,0x95,0x56,0x21,0x98,0x56,0x58,0x85,0xE1,0xC3,
++    0xB0,0xC3,0xC8,0xC3,0x98,0xC3,0x00,0x01,0x81,0x04,0x59,0x85,0xE0,0xC3,0xB0,0xC3,
++    0xC8,0xC3,0x98,0xC3,0x00,0x01,0x80,0xE4,0x80,0xEC,0x80,0xF4,0xC4,0xAC,0xCA,0x03,
++    0x80,0xDC,0x01,0x01,0x08,0x01,0x78,0xA5,0x06,0x18,0xCE,0xD0,0x32,0xA2,0x04,0x20,
++    0xC6,0x10,0x93,0x95,0x6D,0xA5,0xE1,0x72,0x33,0x2A,0xA3,0x72,0x6D,0x8D,0xE1,0x6A,
++    0x32,0x12,0xC3,0x90,0x8A,0xAB,0xE0,0x48,0x90,0x4D,0x4E,0x19,0x98,0x86,0x47,0x09,
++    0x80,0x0E,0x40,0x19,0x8F,0x66,0xE0,0xCA,0x33,0xE2,0x31,0x12,0xCB,0x93,0x30,0x2A,
++    0xC7,0x6B,0xA5,0x2A,0x34,0x1A,0xCB,0xE3,0x8C,0xE3,0x80,0xCB,0x34,0x0A,0x8B,0x53,
++    0x09,0x09,0x88,0x14,0x09,0x01,0x88,0x7C,0xD3,0x7C,0x31,0x0A,0xE1,0x4A,0xDC,0x7C,
++    0x36,0x12,0xC3,0x90,0xCA,0x9B,0xC0,0xAB,0xC9,0x93,0x92,0x1C,0xD0,0x7C,0x51,0x01,
++    0x88,0x16,0x41,0x01,0x80,0x0E,0x40,0x19,0x8D,0x5E,0x10,0x4A,0x98,0x4E,0x10,0x09,
++    0x90,0x0C,0x41,0x01,0x8A,0x16,0xF0,0x10,0x90,0x14,0x01,0xF7,0x11,0x09,0x90,0x14,
++    0x00,0xDF,0x40,0x09,0x80,0x0E,0x40,0x11,0x8D,0x5E,0x10,0x4A,0xC0,0x4E,0x10,0x09,
++    0x90,0x0C,0x41,0x09,0x8C,0x16,0xF0,0x10,0x90,0x14,0x01,0x77,0x11,0x09,0x90,0x14,
++    0x00,0x5F,0x10,0x01,0x90,0x0C,0x01,0x47,0x11,0x09,0x90,0x0C,0x40,0x11,0x90,0x16,
++    0xF1,0x90,0x94,0x14,0x00,0x0F,0x10,0x09,0x90,0x14,0x41,0x01,0x80,0x0E,0x40,0x19,
++    0x8D,0x0E,0x10,0x4A,0x90,0x2E,0x40,0x09,0x80,0x0E,0x40,0x11,0x8D,0x26,0x10,0x4A,
++    0xC0,0x16,0x10,0x09,0x94,0x5C,0x01,0x8F,0x11,0x01,0x90,0x5C,0x01,0x77,0xD4,0xCC,
++    0x32,0x3A,0x19,0xBA,0xD1,0xA4,0xF2,0xEC,0xC4,0xD0,0xCD,0x90,0x91,0x64,0xD1,0x64,
++    0xC1,0x93,0x90,0xE4,0x31,0x90,0xA2,0xD6,0xF3,0xA4,0x02,0xD0,0xC9,0x90,0xF4,0x44,
++    0x04,0xB0,0xCB,0x90,0x31,0x19,0x10,0xB0,0xC8,0xB0,0x14,0x21,0xF1,0x92,0xF5,0xDC,
++    0x10,0x92,0xD5,0x26,0xF0,0x6C,0x71,0x41,0x88,0xC6,0x50,0x01,0xD9,0xB6,0xF0,0xE4,
++    0x48,0xB0,0x87,0x06,0x80,0x90,0xF2,0xE4,0xC0,0xB0,0xB5,0xE4,0xF0,0x44,0xF9,0xF4,
++    0x1F,0xB2,0xCA,0xB0,0xB0,0xF4,0xF0,0xEC,0x1C,0x12,0xCB,0x90,0x91,0xEC,0xD0,0x04,
++    0xE4,0x90,0x92,0x95,0x91,0x04,0xD1,0xE4,0x48,0x90,0x8E,0xEE,0xD0,0x44,0xF2,0xFC,
++    0xCD,0x93,0x12,0x92,0xC1,0x2E,0xD0,0xE4,0x31,0x01,0x1E,0x92,0xF1,0x64,0x81,0x93,
++    0x01,0x47,0xD0,0xE4,0x31,0x01,0x1A,0x92,0xF1,0x64,0x81,0x93,0x01,0x17,0xD0,0x0C,
++    0x50,0x09,0x80,0x4E,0xD0,0x0C,0x51,0x09,0x8A,0x36,0xD0,0x6C,0x10,0xA2,0x84,0x1E,
++    0xD5,0x14,0xC1,0x10,0x95,0xA5,0x3A,0x57,0x10,0x4A,0x8D,0xDE,0xD4,0x1C,0x11,0x9A,
++    0x89,0xC6,0xC8,0x7C,0xE6,0x48,0x92,0x4D,0x89,0x7C,0xC9,0x7C,0x48,0x11,0x90,0x06,
++    0x3A,0x97,0xE2,0x00,0x90,0x05,0x46,0x21,0x91,0x06,0x38,0x1F,0xC2,0x4C,0xF2,0x03,
++    0x42,0x01,0x88,0x5E,0xC9,0xAC,0x8A,0x01,0xD8,0x43,0x36,0x10,0xAA,0x36,0x31,0x00,
++    0x71,0x00,0x04,0x27,0xD0,0x5C,0x51,0x01,0x8D,0x5E,0x10,0x4A,0xCA,0x16,0xF0,0x48,
++    0x90,0x4D,0x06,0x1F,0x10,0x4A,0x95,0x0E,0xE6,0x48,0x92,0x4D,0x11,0x09,0x90,0x5C,
++    0x01,0x67,0xD0,0x1C,0x10,0x9A,0xCC,0x16,0xF6,0xD8,0x92,0xDD,0x01,0x27,0xD0,0x1C,
++    0x10,0x9A,0x94,0x0E,0xE6,0xD8,0x92,0xDD,0x11,0x01,0x90,0x5C,0x91,0x55,0x92,0x44,
++    0x97,0xE5,0x72,0xFA,0xD4,0x44,0xC9,0x90,0x93,0xEC,0x39,0x47,0x02,0x01,0xD0,0xAC,
++    0x6C,0x94,0x12,0x12,0x9A,0xD6,0xC0,0xAC,0xE4,0x4B,0x68,0x04,0x10,0x42,0x9C,0x26,
++    0xC4,0x44,0xCA,0x03,0xF6,0x00,0x94,0x05,0x02,0x1F,0xC0,0x44,0xCC,0x03,0xE4,0x00,
++    0x91,0x05,0xCE,0x04,0x10,0x0A,0x9C,0x4E,0xC0,0xAC,0x0A,0x01,0xB2,0x0B,0xC4,0x54,
++    0x08,0xD9,0xE7,0x03,0x02,0x42,0xC8,0x54,0xA2,0x43,0x28,0x37,0x27,0x01,0x30,0xF9,
++    0xB0,0x09,0x60,0x01,0x8A,0x4E,0xC0,0x3C,0xC8,0xCC,0xF9,0xF4,0xD2,0x54,0x42,0x93,
++    0x97,0x9C,0x50,0x42,0xDE,0x74,0xB2,0xAA,0x02,0x47,0xC0,0x34,0xC8,0xD4,0xF9,0xEC,
++    0xD4,0x54,0x42,0x93,0x97,0x9C,0x50,0x22,0xDE,0x6C,0xB2,0xAA,0x40,0x01,0x80,0x16,
++    0xF4,0x48,0x12,0x42,0x8A,0x8E,0xD0,0x74,0x96,0x04,0x90,0x05,0x32,0x0A,0xD9,0x6C,
++    0xD7,0x5C,0xBA,0xEF,0xD1,0x77,0x37,0x8A,0x10,0x82,0xED,0x0E,0x30,0x42,0x00,0x17,
++    0x40,0x01,0xD0,0x06,0x02,0x01,0xC8,0x28,0x04,0x07,0xA8,0x01,0x10,0xC0,0xC9,0xE4,
++    0x81,0x17,0xF0,0x47,0xCA,0x9C,0xC8,0x00,0x18,0x42,0x42,0x01,0xD0,0x06,0x00,0x01,
++    0xA0,0x00,0x60,0x01,0x8A,0x7E,0xC8,0x54,0x44,0x4C,0x10,0x0A,0xD0,0x06,0x30,0x42,
++    0xC8,0xAC,0x12,0x31,0xF2,0x4B,0x1C,0x8A,0xD4,0xA4,0xC2,0x48,0x12,0x19,0x0A,0x90,
++    0xC4,0x48,0x0C,0x44,0x02,0x77,0xC8,0x54,0x44,0x4C,0x12,0x0A,0xD0,0x06,0x30,0x42,
++    0xC8,0xAC,0x12,0x31,0xF2,0x4B,0x1C,0x8A,0xD4,0xA4,0xC2,0x48,0x12,0x19,0x0A,0x90,
++    0xC6,0x48,0x0C,0x44,0xE7,0x20,0x93,0x25,0x65,0x09,0xC8,0x16,0xC0,0xAC,0x12,0x31,
++    0xD8,0x0B,0xC6,0xE4,0x02,0x42,0xCE,0xAC,0xF2,0x4B,0x1C,0x8A,0xD4,0xA4,0xC2,0x48,
++    0x12,0x19,0x0A,0x90,0xC0,0x48,0x14,0x44,0xC2,0xAC,0xCA,0x74,0xF2,0x03,0x04,0x10,
++    0xC0,0xA4,0xC2,0x90,0x04,0x09,0x09,0x00,0xC0,0x90,0xB0,0x8B,0xCA,0xAC,0xD2,0x6C,
++    0xF2,0x4B,0x04,0x58,0xCA,0xA4,0xC2,0xC8,0xC2,0x40,0xB0,0x13,0xC2,0xAC,0xCA,0xAC,
++    0xF2,0x03,0xE4,0x00,0xB6,0x43,0x24,0x07,0xAC,0xFD,0x87,0xDD,0xF4,0x24,0x31,0xB2,
++    0x33,0xFA,0xD8,0x83,0x81,0x94,0xD8,0x83,0x81,0x8C,0xC8,0x83,0x80,0x84,0x00,0x01,
++    0x85,0x6C,0x40,0x32,0x41,0x0B,0x32,0x82,0x80,0x01,0x85,0xD4,0x48,0x01,0x80,0x1E,
++    0xC2,0x84,0x40,0x00,0x80,0x74,0x00,0x67,0xC2,0xD4,0xF0,0x03,0x40,0x51,0x98,0x26,
++    0xC8,0xD4,0x00,0xD9,0xB0,0x42,0x80,0x74,0x00,0x1F,0xC8,0xD4,0x00,0xD1,0xB0,0x42,
++    0x86,0x74,0x08,0x09,0x03,0x48,0xC4,0xC8,0xC0,0xDC,0x88,0xCC,0x41,0x01,0x80,0xEE,
++    0x04,0x29,0x04,0x00,0xC1,0xD8,0x31,0xCA,0x89,0xF9,0x8F,0x29,0xE0,0xCC,0xC0,0x84,
++    0x42,0x00,0x12,0x02,0x90,0x05,0x82,0x6C,0x04,0x01,0x30,0x22,0x00,0x8F,0x00,0x01,
++    0x00,0x47,0xC0,0xEB,0xC5,0x53,0xD0,0x68,0x05,0x2C,0xE1,0x20,0xE2,0xD8,0xE2,0x48,
++    0xE6,0x00,0x92,0x05,0xED,0x8C,0x10,0x42,0x9B,0x9E,0x37,0x02,0xE6,0x00,0x92,0x05,
++    0x30,0x22,0xC4,0x94,0x2F,0x22,0x9C,0x56,0x30,0x82,0x43,0x01,0x84,0x06,0x38,0x02,
++    0x06,0xC9,0x07,0x00,0xC7,0xD8,0x01,0xF9,0x01,0x00,0xC6,0xC0,0x4B,0x02,0xC4,0xC8,
++    0x10,0x01,0x00,0x47,0x40,0x24,0x40,0x6C,0xD8,0x20,0x03,0xE4,0xE4,0xD8,0xE4,0x00,
++    0xE2,0x48,0xE4,0x90,0x90,0x95,0xE6,0x8C,0x17,0x12,0x9D,0x9E,0x41,0xA2,0xC3,0xC0,
++    0x80,0x64,0xE8,0xCC,0x00,0x01,0x80,0x9C,0x34,0x82,0x81,0x01,0x83,0xC4,0xC0,0x01,
++    0x85,0xBC,0x80,0x01,0x85,0xB4,0x08,0x8F,0x25,0x01,0x08,0x3F,0xC0,0x64,0xC0,0x03,
++    0x4B,0x00,0x8C,0xF6,0xF0,0x42,0xC9,0x84,0x13,0x42,0xDC,0xD6,0xC3,0x8C,0x30,0x5A,
++    0x01,0x00,0xD2,0x48,0x31,0x52,0xD0,0x01,0x5C,0x94,0x1E,0xD4,0x46,0x54,0x18,0xD4,
++    0x40,0x4C,0x22,0xCC,0x31,0x4A,0xC9,0x01,0x5A,0x4C,0x26,0xCC,0x44,0x4C,0x21,0xCC,
++    0x46,0x4C,0x23,0xCC,0xC8,0x08,0x32,0x52,0xD6,0x01,0x59,0x94,0x29,0xD4,0xD0,0x42,
++    0x2A,0xC4,0x42,0x44,0x28,0xC4,0x44,0x3D,0x60,0x01,0x88,0x66,0x0C,0x01,0x18,0xCC,
++    0x20,0xCC,0x2A,0xCC,0x10,0xCC,0x0C,0xF9,0x0B,0x48,0xC4,0xC8,0x4E,0x54,0x10,0xD4,
++    0x48,0x4C,0x1A,0xCC,0x00,0x87,0xC9,0x8C,0xF4,0x48,0x12,0x62,0x88,0xC6,0x10,0x01,
++    0x30,0x5A,0x23,0xD4,0x24,0xD4,0x2E,0xD4,0xD0,0x8C,0x18,0xF9,0xF2,0x90,0x04,0x90,
++    0xCC,0x90,0x0E,0xD8,0xC0,0x90,0x4E,0x94,0x34,0x5A,0x13,0xD4,0x06,0x48,0xCA,0x50,
++    0x0C,0xF9,0x08,0x48,0xC0,0x88,0x4A,0x4C,0x10,0xCC,0x0E,0x01,0x18,0xCC,0x00,0x9F,
++    0xF2,0x08,0x03,0x48,0xC8,0x50,0x0E,0xF9,0x0A,0x48,0xC4,0x90,0x4B,0x94,0x30,0x5A,
++    0x13,0xD4,0x04,0x10,0xCA,0x90,0xC6,0x90,0x4E,0x94,0x10,0xD4,0xE2,0x10,0x03,0x90,
++    0xCA,0x90,0xC6,0x88,0x48,0x4C,0x18,0xCC,0xC8,0x9C,0x48,0x01,0x8B,0x26,0x30,0x5A,
++    0x1E,0xCC,0x1C,0xCC,0x20,0xCC,0x00,0x4F,0xC8,0x94,0xD0,0x9C,0xF4,0x48,0x12,0x52,
++    0x88,0x26,0x08,0x01,0x30,0x5A,0x2B,0xCC,0x2C,0xCC,0x2A,0xCC,0x0B,0x01,0xF0,0x4A,
++    0x33,0x62,0x34,0x5A,0x14,0xE1,0xF0,0xD2,0x10,0x52,0xE4,0x16,0x14,0xF1,0xF0,0xD2,
++    0x04,0x07,0x00,0x07,0x13,0x52,0xD4,0xF6,0x14,0x01,0xF1,0xD2,0x17,0x52,0xD4,0xD6,
++    0x14,0x11,0xF1,0xD2,0x17,0x52,0xE4,0x86,0x14,0x31,0xF1,0xD2,0x17,0x52,0xD4,0x96,
++    0x14,0x41,0xF1,0xD2,0x17,0x52,0xD4,0x76,0x14,0x51,0xF1,0xD2,0x17,0x52,0xE4,0x26,
++    0x14,0x61,0xF1,0xD2,0x17,0x52,0xE4,0x06,0xCA,0xC4,0xE0,0x4B,0x4B,0x01,0x80,0xCE,
++    0x0C,0x01,0x30,0x72,0x88,0x14,0x88,0x1C,0x88,0x7C,0x10,0x01,0xC8,0xDC,0x48,0x01,
++    0x88,0x96,0x8B,0x24,0x1E,0x01,0xF0,0x1A,0xE8,0xC8,0xD2,0x36,0xC0,0xC8,0x94,0x55,
++    0xCA,0x1C,0xE0,0x48,0x90,0x4D,0x8E,0x1C,0x00,0x2F,0x58,0x51,0xE8,0x1E,0xC8,0x14,
++    0xE6,0x48,0x92,0x4D,0x8C,0x14,0xE0,0x00,0xCA,0x24,0xE0,0x48,0x90,0x4D,0x8E,0x24,
++    0xC8,0x24,0x48,0x49,0x9B,0x36,0x37,0x02,0xC0,0x00,0x94,0x05,0xD5,0xBC,0x68,0x8C,
++    0xE4,0x93,0x10,0x8A,0x98,0x0E,0xC9,0x74,0x10,0x42,0xD4,0xF6,0xC8,0x14,0x48,0x39,
++    0x98,0x8E,0xC8,0x74,0x84,0x48,0x12,0x0A,0xD8,0xBE,0xC0,0x1C,0x40,0x01,0x00,0x4F,
++    0x30,0x20,0x06,0x00,0xE0,0xD2,0x07,0x00,0xE0,0xD2,0x06,0x00,0x58,0x80,0x04,0x01,
++    0x40,0x40,0x01,0x00,0x88,0x4E,0xC0,0xD4,0xF0,0x03,0x42,0x11,0x98,0x0E,0x00,0x09,
++    0x37,0x32,0x4C,0xFA,0xC2,0x43,0xE2,0x00,0x80,0x43,0xC2,0xC4,0xE0,0x03,0x40,0x01,
++    0x83,0xFE,0x30,0x82,0x40,0x01,0x88,0xE6,0xC2,0xD4,0xF0,0x03,0x40,0x51,0x98,0xC6,
++    0x30,0x5A,0x03,0xB1,0x08,0x91,0xF1,0xC2,0xF4,0x8A,0x13,0x42,0xD8,0x5E,0x08,0xA1,
++    0xF2,0xCA,0x82,0x48,0x04,0x07,0x00,0xDF,0x10,0x42,0xDC,0x26,0x0A,0xC1,0xF0,0xCA,
++    0x84,0x48,0x12,0x42,0xD0,0x2E,0x00,0x09,0x37,0x32,0x4C,0x6A,0xC2,0x43,0xE2,0x00,
++    0x87,0x43,0x52,0x5A,0xC0,0x83,0x40,0x81,0x97,0x16,0x4A,0x52,0xA2,0x62,0xE0,0x00,
++    0x81,0x83,0x00,0xEF,0x07,0x57,0x3A,0xFF,0x30,0x1A,0x9B,0x04,0x83,0xC8,0x24,0x0A,
++    0x90,0x4D,0x88,0x0C,0x08,0x01,0x88,0x24,0xCA,0x6C,0x80,0x48,0x88,0xAC,0x18,0x01,
++    0xF0,0x1A,0xCE,0xAC,0x9C,0xA4,0x10,0x5A,0xD0,0x6E,0xD8,0xA4,0xCA,0x04,0xC0,0xC8,
++    0x90,0x4D,0x88,0x04,0xD8,0xA4,0xC8,0x6C,0x10,0x5A,0xD4,0x26,0x32,0x1A,0x83,0xC8,
++    0x20,0x0A,0x93,0x4D,0x88,0x0C,0xC8,0xA4,0xC0,0x48,0x94,0x55,0xE0,0x00,0xCC,0x24,
++    0xE6,0x48,0x92,0x4D,0x88,0x24,0xC8,0x24,0x4F,0x49,0x98,0x06,0xC4,0x0C,0x10,0x12,
++    0xD8,0x66,0xC8,0x74,0xC4,0x04,0x10,0x42,0xD8,0x46,0xC0,0xC4,0xE0,0x03,0x40,0x01,
++    0x83,0x36,0x30,0x5A,0x00,0xB1,0xF0,0xC2,0x40,0x01,0xD0,0x0E,0x04,0x09,0x30,0x32,
++    0xC2,0xD4,0xF0,0x03,0x40,0x51,0x98,0x16,0xC0,0xDC,0x40,0x01,0x80,0x46,0x00,0x09,
++    0x30,0x8A,0x4B,0x01,0x80,0x06,0x00,0x01,0x80,0x7C,0x00,0x0F,0x00,0x09,0x80,0x7C,
++    0xC0,0x7C,0x40,0x01,0x80,0xA6,0x01,0x09,0xB5,0x83,0x47,0xFA,0x40,0x03,0x42,0x01,
++    0x88,0x5E,0xC0,0xD4,0xF0,0x03,0x42,0x51,0x90,0x3E,0xC0,0xBC,0x6E,0x8C,0xDB,0x03,
++    0x32,0x00,0x72,0x00,0x84,0x51,0x10,0x0A,0xC8,0x0E,0x10,0x01,0x00,0x07,0x10,0x09,
++    0xC0,0xE4,0x40,0x01,0x80,0x06,0x10,0x11,0x91,0x14,0x30,0x1A,0xB8,0x04,0xB0,0x0C,
++    0x30,0x42,0xD1,0x9C,0xCF,0x64,0xB8,0xFF,0xC8,0x5F,0xC7,0xB4,0xE2,0x03,0x38,0x00,
++    0xAD,0x1E,0xF0,0x83,0xFC,0x8B,0x13,0x42,0x98,0x56,0xC0,0xB4,0xE2,0x03,0x38,0x00,
++    0xA7,0x26,0x00,0xF1,0xA8,0x83,0xC9,0xB4,0x04,0x01,0xA0,0x43,0x87,0xFD,0xE8,0x85,
++    0xE0,0x68,0xC5,0x64,0xE0,0x00,0x82,0x64,0xE7,0x20,0x93,0x25,0xC4,0x8C,0x10,0x22,
++    0x92,0x06,0x30,0x9F,0xC2,0x9C,0xE0,0x00,0x90,0x05,0x86,0x9C,0xC8,0x94,0xC0,0x9C,
++    0x10,0x42,0x94,0x06,0x37,0x47,0x3A,0x4F,0xAC,0x9D,0x87,0x3D,0x30,0x3A,0xC0,0x44,
++    0xD0,0x03,0x84,0x24,0xC6,0x44,0xD0,0x23,0x41,0xC2,0xC4,0xE8,0x06,0xF9,0x07,0x00,
++    0xC0,0xF0,0xC1,0x44,0x08,0xF1,0xE8,0x03,0x84,0x17,0xD8,0xA7,0x04,0x29,0x04,0x00,
++    0xC4,0xD0,0x41,0x9A,0x37,0xDA,0x99,0xF9,0xC1,0xC0,0x99,0x29,0x80,0x34,0x48,0xE9,
++    0x88,0xDE,0x08,0x01,0x00,0x5F,0x00,0x01,0x00,0x2F,0xC0,0xFB,0x82,0xBB,0xE0,0x90,
++    0xE2,0xD8,0xE2,0x00,0x95,0x05,0x16,0x02,0x9A,0xBE,0xE7,0x48,0x90,0x4D,0xC6,0x24,
++    0x17,0x0A,0x9C,0x86,0x00,0x01,0x00,0x2F,0x41,0x8C,0x01,0x4C,0xE5,0x68,0xE5,0xB0,
++    0xE6,0x00,0x92,0x05,0x17,0x02,0x9D,0xBE,0x00,0xCF,0xC3,0x44,0x82,0x01,0xF5,0x03,
++    0x43,0x51,0x98,0xA6,0xC4,0x44,0xF0,0x03,0x80,0x2C,0x40,0x01,0x80,0x7E,0x9B,0x1C,
++    0xF3,0x34,0x08,0x21,0x1B,0x01,0x00,0x21,0x30,0x32,0x04,0x01,0x30,0x22,0x84,0x14,
++    0x29,0x01,0x00,0x1F,0x00,0x01,0x80,0x0C,0x01,0x97,0xC0,0xBB,0x48,0xF8,0x85,0x66,
++    0x10,0x0A,0xCC,0x0E,0x30,0x0A,0x00,0x17,0x10,0x1A,0x94,0x06,0x30,0x1A,0xF8,0x14,
++    0xE7,0xF8,0x93,0xFD,0xB8,0x14,0x38,0x09,0xBB,0x0C,0xE0,0xB0,0xE6,0x00,0x92,0x05,
++    0x17,0x02,0x9D,0x56,0xC0,0x0C,0x40,0x01,0x85,0x36,0x28,0x72,0xCD,0x0E,0x30,0x72,
++    0x05,0x17,0x28,0x62,0x95,0x06,0x30,0x62,0xE7,0x68,0x93,0x6D,0xC4,0x24,0x10,0x2A,
++    0x98,0xC6,0xC6,0x2C,0x2B,0x51,0x18,0x42,0xED,0x14,0x10,0x42,0xC8,0xB6,0x48,0x01,
++    0x82,0x0E,0xF0,0x48,0x93,0x4D,0xF6,0x00,0x10,0x1A,0xD4,0x0E,0xE6,0xD8,0x92,0xDD,
++    0x30,0x82,0x43,0x01,0x82,0x16,0xF0,0x00,0x94,0x05,0x36,0x32,0xEB,0x24,0xF0,0x68,
++    0x28,0x62,0xD5,0x1E,0x32,0x02,0xE3,0x00,0x94,0x05,0x36,0x22,0x28,0x01,0x00,0xDF,
++    0x00,0x01,0x00,0xAF,0x10,0x42,0x9C,0x2E,0x28,0xAA,0x9B,0x1E,0x10,0xC2,0xC4,0x0E,
++    0x28,0x2A,0xCB,0x3E,0xC1,0xB3,0x08,0xB8,0xD8,0xF8,0xF5,0x1C,0xC7,0xB3,0xC9,0xB0,
++    0x48,0xB0,0x81,0xB3,0xE0,0x90,0xF2,0x1C,0xE0,0xB0,0xB3,0x1C,0xE6,0x00,0x92,0x05,
++    0x17,0x02,0x9D,0x3E,0xE7,0x68,0x93,0x6D,0xC4,0x24,0x10,0x2A,0x98,0x06,0xC7,0x34,
++    0x10,0x01,0x00,0x67,0x08,0x01,0x00,0x37,0xC4,0x1B,0x30,0xD8,0x70,0xD8,0x84,0x1B,
++    0xE2,0x00,0xE2,0x48,0x95,0x4D,0x16,0x0A,0x9A,0xB6,0xE7,0x90,0x90,0x95,0xCE,0x24,
++    0x17,0x52,0x9C,0x7E,0x87,0x4D,0xE8,0x85,0xAC,0xFD,0x87,0x1D,0x30,0x2A,0x30,0x62,
++    0x05,0x01,0xB0,0x03,0xB1,0x03,0x37,0x02,0x80,0x01,0xE6,0x0B,0x10,0xE9,0x07,0x52,
++    0x3E,0x48,0x7A,0x48,0x00,0x48,0x1A,0x52,0xA0,0x13,0xE0,0x0B,0x10,0xD9,0x07,0x8A,
++    0xA1,0x0B,0x30,0x02,0x80,0x01,0x84,0x14,0xE1,0x03,0x7A,0x4A,0x40,0x01,0x80,0x56,
++    0x01,0x01,0x50,0x42,0x08,0xF9,0xA7,0x8A,0xE6,0x00,0x92,0x05,0x47,0x81,0x98,0xD6,
++    0x01,0x01,0x80,0xC3,0x80,0xC3,0xA3,0x04,0x30,0x5A,0x01,0x01,0xD0,0x34,0xC8,0x2C,
++    0xBE,0xFF,0xE7,0xD7,0x35,0x32,0xB1,0x01,0xF0,0x83,0x43,0x51,0x98,0x36,0xA0,0x04,
++    0x30,0x5A,0x01,0x09,0xD0,0x34,0xC8,0x2C,0xBE,0xFF,0xE7,0x77,0xC2,0x14,0xE0,0x03,
++    0x43,0x01,0x80,0xF6,0x45,0xB2,0xF0,0x0B,0xC2,0x03,0x02,0x00,0x10,0x0A,0xCC,0x1E,
++    0x48,0x9A,0x00,0x01,0x81,0x43,0x02,0xDF,0x48,0x8A,0xC0,0x43,0x30,0x22,0x44,0x21,
++    0xC0,0xB6,0x01,0x01,0x00,0x8F,0x59,0x7A,0xE7,0xCA,0x48,0xF9,0x80,0x5E,0x11,0x01,
++    0xE6,0x08,0x92,0x4D,0x00,0x97,0x78,0x5A,0xE3,0xDA,0xE1,0xFA,0xDA,0xD8,0xE6,0xD8,
++    0x58,0x11,0xC0,0x4E,0x5A,0x32,0xC0,0xD3,0x50,0x01,0x80,0x0E,0xF2,0x90,0x82,0xD3,
++    0x5F,0x22,0x10,0xF9,0xA0,0xD2,0x10,0x09,0xE6,0x48,0x92,0x4D,0x28,0x0A,0x03,0x4F,
++    0x00,0xA0,0x00,0x01,0x58,0x00,0x04,0x01,0x58,0x80,0x04,0x01,0x40,0x40,0x01,0x00,
++    0x30,0x20,0x06,0x00,0x98,0xFE,0x56,0x09,0x8B,0x2E,0x50,0x42,0xC0,0x8B,0x4A,0x01,
++    0x82,0x0E,0xF0,0x48,0x82,0x8B,0xE2,0x00,0x93,0x05,0x7E,0x22,0x2E,0x02,0x9B,0x56,
++    0x08,0x01,0xC0,0x14,0xE1,0x1B,0x32,0x02,0x80,0x01,0x59,0x09,0x8A,0x2E,0x50,0xFA,
++    0xC0,0x93,0x52,0x01,0x80,0x9E,0x08,0x09,0x02,0x8F,0x50,0xE2,0xC0,0x93,0x52,0x01,
++    0x8E,0x46,0xD8,0x3B,0x6B,0x14,0x33,0xF8,0x75,0xF8,0x13,0xD2,0x9F,0x3E,0xF0,0x13,
++    0x50,0x01,0x88,0x26,0x68,0x14,0xE5,0x3B,0x10,0xD2,0x9D,0x06,0x08,0x09,0x48,0x01,
++    0x83,0x2E,0xF0,0x8B,0x48,0x01,0x95,0x3E,0xE3,0x48,0xB2,0x8B,0x03,0x27,0xF0,0x8B,
++    0x48,0x51,0x90,0x0E,0x0B,0x01,0xB0,0x8B,0xF0,0x8B,0x4B,0x51,0x9A,0x0E,0x51,0x5A,
++    0xC0,0x93,0x52,0x01,0x8D,0x8E,0xF0,0x3B,0x78,0x01,0x88,0x76,0x58,0x09,0x88,0x26,
++    0x00,0x07,0x00,0xB7,0xF3,0x48,0xB2,0x8B,0x06,0x3F,0xD8,0x03,0x6A,0x1C,0x33,0x00,
++    0x74,0x00,0x14,0x1A,0x92,0x0E,0xF0,0x48,0xB0,0x8B,0x53,0x11,0x9D,0x16,0x00,0x01,
++    0xB0,0x83,0x03,0x37,0x50,0x09,0x88,0x26,0xF2,0x83,0x43,0x81,0x93,0x0E,0x00,0x21,
++    0xB5,0x83,0xF3,0x0B,0x4B,0x09,0xC8,0x5E,0x07,0x01,0xD0,0x13,0x90,0x04,0x10,0x01,
++    0x02,0xA7,0x00,0x98,0xC9,0xF0,0x1A,0x09,0x0F,0xD8,0xC4,0x98,0xF0,0xF3,0xF2,0xDB,
++    0xFA,0x04,0x00,0xD8,0x1B,0xF2,0x03,0xB0,0xCF,0xB0,0xC3,0x98,0x31,0x19,0x10,0xB0,
++    0xCC,0xD8,0x44,0xDC,0xC4,0xC0,0x90,0x05,0xE6,0x90,0x92,0x95,0x17,0x8A,0xC4,0x46,
++    0x87,0x17,0xC8,0x47,0x40,0x00,0x82,0x0C,0xC8,0x0B,0xC1,0x0C,0x12,0x0A,0x94,0x3E,
++    0x0A,0x01,0x00,0x17,0x02,0x40,0xCA,0x10,0x04,0x09,0x09,0x00,0xC2,0x80,0xF0,0x13,
++    0xF0,0x03,0xD8,0x04,0x02,0x00,0x1A,0xD2,0x02,0x90,0xCA,0x90,0xC0,0x80,0x10,0x19,
++    0x14,0x90,0xC0,0x10,0x00,0x21,0xF0,0x82,0xD4,0x0C,0x10,0x82,0xD0,0x5E,0x31,0x42,
++    0x02,0x17,0xE1,0x10,0x36,0xA2,0x94,0x95,0x01,0x98,0x3A,0x09,0xCD,0xD8,0x0A,0xF8,
++    0xCA,0xD8,0x06,0x30,0x33,0xF2,0xCC,0xB0,0xF7,0xDB,0xC8,0xB0,0xB3,0x9B,0x31,0x9A,
++    0xF3,0xDB,0xB2,0x9B,0x1A,0x31,0x18,0xD2,0x3A,0x19,0xCA,0x90,0x08,0xF8,0x33,0x31,
++    0xCB,0x90,0x1E,0x82,0xCC,0x00,0x4A,0x9C,0xCC,0x00,0x0E,0x1C,0x4E,0x9C,0x0E,0x1C,
++    0x50,0x94,0x10,0x14,0x36,0x12,0x93,0x85,0xF2,0x13,0xF5,0x90,0x16,0x12,0xE4,0xC6,
++    0xF2,0x03,0xF5,0x00,0xB2,0x03,0xE5,0x48,0x95,0x4D,0xF6,0x03,0x15,0x42,0xC4,0xCE,
++    0x31,0x0A,0x31,0x42,0xBF,0xFF,0xEF,0x87,0x87,0x3D,0xE8,0x85,0x00,0xA0,0x00,0x01,
++    0xAC,0xFD,0x87,0x2D,0xE0,0x74,0x00,0x01,0x80,0x1C,0xC0,0x3C,0xD0,0x33,0xC6,0x3C,
++    0x58,0x04,0x86,0x0C,0xC3,0x34,0x18,0x82,0x50,0xFA,0xCF,0x2C,0xC2,0x48,0xC4,0x08,
++    0x8F,0x24,0x40,0xF2,0xC0,0x03,0x40,0x09,0x88,0x0E,0xC0,0x3C,0xD8,0x33,0x04,0x01,
++    0x10,0x01,0x00,0x1F,0x82,0x53,0xE0,0x48,0xE6,0x00,0x92,0x05,0x17,0x82,0x9D,0xCE,
++    0x08,0x01,0x00,0x09,0xD8,0x44,0xD0,0x34,0x86,0x07,0xD0,0x6F,0x28,0x01,0x60,0x01,
++    0x8B,0x0E,0xE0,0x68,0x90,0x6D,0xFF,0x24,0x08,0x01,0x00,0x5F,0xC1,0xC3,0x19,0x02,
++    0x91,0x05,0x86,0xC3,0xD4,0x7C,0x10,0x82,0xCD,0x0E,0x18,0x02,0x83,0xC3,0xE1,0xF8,
++    0xE6,0x48,0x92,0x4D,0x17,0x8A,0x9D,0x8E,0x08,0x09,0xC6,0x2C,0x02,0x48,0xC4,0x00,
++    0x80,0x14,0xD0,0x44,0x90,0x04,0x00,0x11,0xD8,0x3C,0xD0,0x2C,0xC8,0x34,0x80,0x07,
++    0xD8,0x07,0xD0,0x44,0xC0,0x3C,0x90,0x04,0x82,0x01,0xCA,0x0B,0x00,0x01,0x1C,0x0A,
++    0x10,0x01,0xD8,0x3C,0xC0,0x14,0x80,0x0F,0xDD,0xCF,0xDD,0xC0,0x09,0x01,0x00,0x3F,
++    0xD0,0x14,0x18,0x01,0xF0,0x9A,0xD6,0x0C,0xD0,0xD0,0x94,0x95,0x68,0x01,0x88,0x2E,
++    0x50,0xC1,0xE8,0xBE,0xC5,0x13,0x18,0x12,0x80,0x13,0x00,0x9F,0x50,0x99,0xE8,0x2E,
++    0xC0,0x13,0x50,0x01,0x82,0x16,0xF0,0x90,0x80,0x13,0x00,0x5F,0x68,0x29,0x88,0x4E,
++    0x58,0xE1,0xEE,0x3E,0xC0,0x13,0x50,0x01,0x88,0x26,0xD0,0x1C,0x50,0x01,0x88,0x0E,
++    0x10,0x09,0x90,0x1C,0xD4,0x14,0xE0,0x90,0x92,0x14,0xE0,0x00,0xE6,0x48,0x92,0x4D,
++    0x16,0x8A,0x9D,0xAE,0x40,0x20,0x6B,0x21,0xC8,0x0E,0xD5,0x44,0x90,0x04,0x08,0x01,
++    0x00,0x19,0xD8,0x3C,0xD0,0x2C,0x80,0x07,0xD0,0xE7,0x0D,0x09,0x30,0x42,0xD8,0x44,
++    0xD0,0x34,0x80,0x07,0xD0,0x07,0xC3,0x1C,0x87,0x4D,0xE8,0x85,0xAC,0xFD,0x87,0x1D,
++    0xF0,0x64,0x30,0x7A,0x37,0xEA,0xD0,0xC3,0x86,0x14,0x08,0x09,0xC4,0x1C,0x00,0x48,
++    0xC5,0x20,0x42,0xB2,0xC0,0x03,0x40,0x09,0x8D,0x0E,0xD8,0xC3,0x80,0x14,0x08,0x01,
++    0x00,0x09,0xD8,0x2C,0xD0,0x6C,0x80,0x07,0xD0,0x37,0xD2,0x2C,0x91,0x04,0x30,0xDA,
++    0x00,0x11,0xD0,0x1C,0xC8,0x6C,0x80,0x07,0xD0,0xA7,0xD4,0x2C,0x92,0x04,0x00,0x29,
++    0xEC,0x0A,0x06,0x01,0x19,0x0A,0x30,0xDA,0x11,0x01,0x30,0x02,0x82,0x0F,0xD8,0x77,
++    0xD0,0x2C,0x90,0x04,0x30,0xDA,0x09,0x01,0x00,0x19,0xD0,0x1C,0x84,0x07,0xD0,0x0F,
++    0x08,0x09,0x30,0x42,0xD8,0x2C,0xD0,0x6C,0x81,0x07,0xD0,0x2F,0x41,0x02,0x05,0x44,
++    0x01,0x01,0x00,0x84,0x08,0x01,0x00,0x77,0x01,0x01,0xF0,0x02,0x15,0x01,0xF0,0x52,
++    0x10,0x12,0xEC,0x06,0x00,0x44,0x11,0x01,0xF4,0x92,0x15,0x12,0xD1,0x06,0x00,0x84,
++    0xE2,0x20,0xE5,0x48,0x90,0x4D,0xC6,0x14,0x17,0x0A,0x9C,0x6E,0x87,0x3D,0xE8,0x85,
++    0xAC,0xBD,0x87,0x45,0xC2,0x4C,0xD8,0x03,0x80,0x1C,0xC8,0x4C,0xD0,0x4B,0x8E,0x14,
++    0x50,0x6A,0xCC,0x44,0xC0,0x48,0x8C,0x3C,0x48,0x62,0xC4,0x4B,0x48,0x09,0x88,0x46,
++    0xCA,0x1C,0xE0,0x48,0x90,0x4D,0x8E,0x1C,0x80,0x34,0xC0,0x4C,0xD8,0x03,0x84,0x14,
++    0x00,0x0F,0x00,0x01,0x80,0x34,0xF8,0x34,0x04,0x3F,0x4B,0x32,0x04,0x01,0x00,0x43,
++    0xC0,0x4C,0xC8,0x3C,0xD3,0x03,0x1E,0xC2,0xC0,0x08,0x02,0x01,0x10,0xF9,0x01,0x1F,
++    0x82,0x53,0xE0,0x48,0xE6,0x00,0x92,0x05,0xDC,0x14,0x10,0xC2,0x9C,0xC6,0x27,0x01,
++    0x31,0x2A,0x31,0x32,0x03,0xC7,0x40,0xE2,0x08,0x23,0x4E,0x25,0xB8,0x0C,0x88,0x04,
++    0x40,0x45,0x40,0x3E,0x5F,0x2D,0xB8,0xFF,0xFB,0x8F,0x33,0x5A,0x00,0xA1,0xF0,0xC2,
++    0x40,0xE1,0xD1,0x1E,0x68,0x41,0x80,0x4E,0x18,0x62,0x05,0x1F,0x70,0x01,0x8C,0x0E,
++    0x30,0x72,0x01,0x1F,0x41,0x68,0x1B,0x62,0x6F,0x01,0x88,0x26,0xC0,0x4C,0xC8,0x3C,
++    0xD3,0x03,0x1E,0xC2,0xC0,0x08,0x02,0x01,0x10,0x01,0x00,0x1F,0x82,0x53,0xE0,0x48,
++    0xE6,0x00,0x92,0x05,0xDC,0x14,0x10,0xC2,0x99,0xC6,0x37,0xAA,0x20,0x01,0x00,0x0F,
++    0x1B,0xA2,0x41,0xB0,0x77,0x01,0x88,0xDE,0xC6,0x4C,0x58,0x04,0xC0,0x41,0x91,0x35,
++    0x05,0x8F,0x18,0x62,0x46,0x02,0x0B,0x23,0x48,0x25,0xB8,0x0C,0x88,0x04,0x40,0x45,
++    0x40,0x3E,0x58,0x2D,0xB9,0xFF,0xFF,0xD7,0x30,0x5A,0x03,0x81,0xF5,0xC2,0x10,0x82,
++    0xE9,0x06,0x18,0x62,0x40,0x68,0x6B,0x01,0x88,0x5E,0xC7,0x44,0x0E,0xE9,0xC9,0x00,
++    0x0A,0x48,0xC2,0x00,0xAB,0x23,0xE0,0xF8,0x90,0xFD,0xC7,0x1C,0x14,0x3A,0x9C,0xA6,
++    0xF1,0x34,0x00,0x9F,0xC1,0x44,0x08,0xE9,0xCA,0x00,0x0C,0x48,0xC1,0x38,0xEA,0xC3,
++    0x40,0x01,0x88,0x0E,0x01,0x09,0xA8,0xC3,0xE8,0xE3,0x29,0x01,0x01,0x01,0x00,0x07,
++    0xE7,0x68,0x93,0x6D,0x40,0x09,0x88,0x1E,0x60,0xF9,0x97,0x0E,0xE5,0x20,0x93,0x25,
++    0x48,0x22,0x02,0x01,0x00,0x43,0xAC,0x48,0x46,0x1A,0x0A,0x23,0x20,0x00,0x67,0x10,
++    0x02,0x07,0x40,0x48,0x30,0x82,0x10,0x42,0x81,0xDE,0x4F,0x01,0xC9,0x06,0x08,0x01,
++    0x88,0x04,0x90,0x0C,0x40,0x45,0x40,0x6E,0x37,0x8A,0xB9,0xFF,0xF0,0x0F,0x43,0x01,
++    0x80,0x0E,0x68,0x29,0x99,0xE6,0xAE,0xE3,0xE7,0xB0,0x93,0xB5,0xC4,0x1C,0x10,0x32,
++    0x98,0x46,0x86,0x5D,0xEF,0x85,0xAF,0xBD,0x80,0x15,0x34,0x62,0x31,0xB2,0x48,0x7A,
++    0x00,0x01,0x80,0x43,0x40,0x8A,0x41,0x0B,0x10,0x11,0x18,0x8A,0x00,0x0B,0x28,0x01,
++    0x00,0x3F,0x08,0x09,0x31,0x9A,0x31,0x52,0x30,0x42,0x80,0x07,0xCB,0xA7,0xE1,0x68,
++    0x95,0x6D,0xD7,0x03,0x17,0x42,0xC5,0xA6,0x31,0x12,0x31,0x8A,0x00,0x11,0x80,0x07,
++    0xC1,0x7F,0x34,0x92,0x30,0x0A,0xC1,0x14,0xB8,0xFF,0xFF,0xD7,0x31,0x12,0x31,0x8A,
++    0x00,0x01,0x80,0x07,0xC5,0x2F,0xDC,0x03,0x41,0x01,0x80,0x46,0x6F,0xF2,0x40,0x43,
++    0x91,0x3D,0x4C,0x04,0x00,0x43,0x47,0xCA,0x08,0x09,0x80,0x0B,0x31,0x12,0x31,0x8A,
++    0x00,0x11,0x80,0x07,0xC1,0xAF,0x33,0x1A,0xB0,0x04,0x08,0x01,0x00,0x09,0xD0,0x14,
++    0x82,0x07,0xC8,0xFF,0xB3,0x04,0xD8,0x0B,0x30,0x1A,0x01,0x11,0xD0,0x14,0x80,0x07,
++    0xC9,0xC7,0x32,0x92,0x30,0x0A,0xC1,0x14,0xBF,0xFF,0xF7,0x97,0x31,0x12,0x31,0x8A,
++    0x00,0x01,0x80,0x07,0xC0,0xEF,0x42,0x4A,0x08,0x01,0x80,0x0B,0x01,0x7B,0x37,0x1A,
++    0xB0,0x04,0x08,0x01,0x00,0x11,0xD0,0x14,0x82,0x07,0xC8,0x1F,0x31,0x12,0x31,0x8A,
++    0x00,0x11,0x80,0x07,0xC0,0x6F,0x02,0x5F,0x30,0x20,0x06,0x00,0x00,0xB0,0x00,0x01,
++    0xF8,0xFB,0x07,0x00,0x10,0x00,0x00,0x42,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,
++    0x50,0x1A,0x40,0x83,0x0C,0x11,0x18,0x42,0x00,0x83,0x80,0x2D,0xE8,0x85,0x07,0x00,
++    0x18,0x00,0x04,0x42,0xA8,0x85,0x31,0x12,0x90,0x01,0xE6,0x9B,0x32,0xD8,0x72,0xD8,
++    0xA7,0x9B,0x58,0xCA,0x41,0xE3,0x30,0x20,0xA2,0x16,0x40,0xE3,0x3F,0x20,0xAB,0xE6,
++    0x58,0xB2,0x27,0x41,0x00,0xE3,0x44,0xE3,0x28,0xF9,0xAF,0x19,0x18,0x62,0x01,0xE3,
++    0x20,0x81,0x48,0x01,0x83,0x76,0x00,0xE9,0x08,0x00,0xE4,0x8B,0x48,0x48,0x8E,0x1E,
++    0xF0,0x00,0x22,0x00,0x67,0x00,0x88,0xC6,0x40,0x01,0x88,0x16,0x41,0xC3,0x18,0x02,
++    0x01,0xC3,0xE8,0x85,0x80,0x01,0xE5,0x8B,0x48,0x48,0x8E,0x16,0xE8,0x0B,0x4E,0x31,
++    0x8E,0xCE,0xEF,0x03,0x47,0x31,0x88,0xA6,0x41,0xC3,0x18,0x02,0x01,0xC3,0xE8,0x85,
++    0xAA,0x85,0x47,0x63,0x46,0x5B,0xD6,0xAB,0x71,0x0A,0xC7,0xB3,0x70,0x09,0x88,0x16,
++    0x4A,0x63,0x56,0x5B,0xD8,0xAB,0x44,0x01,0x88,0x0E,0x11,0x01,0x01,0xE7,0x40,0x03,
++    0x30,0x32,0xB0,0x41,0x30,0xA2,0xED,0x08,0x32,0x42,0xC0,0x01,0x58,0x33,0xC4,0xFB,
++    0x1C,0xF2,0x19,0x33,0x58,0x33,0xC6,0xFB,0x1E,0xF2,0x1D,0x33,0x31,0x32,0x43,0x83,
++    0xC5,0xF3,0x18,0x82,0x31,0x32,0x03,0x83,0x40,0x73,0xC0,0xC3,0x18,0x32,0x04,0x73,
++    0xEA,0x20,0xE1,0xD8,0xE6,0x90,0x92,0x95,0x17,0x52,0x9D,0x06,0xE8,0x85,0x47,0x09,
++    0x88,0x0E,0x11,0x01,0x01,0xE7,0x40,0x03,0x30,0x32,0xB0,0x41,0x30,0xA2,0xED,0x08,
++    0x32,0x42,0xC0,0x01,0x58,0x33,0xC4,0xFB,0x1C,0xF2,0x1D,0x33,0x58,0x33,0xC6,0xFB,
++    0x1E,0xF2,0x1D,0x33,0x31,0x32,0x43,0x83,0xC5,0xF3,0x18,0x82,0x31,0x32,0x03,0x83,
++    0x40,0x73,0xC0,0xC3,0x18,0x32,0x00,0x73,0xEA,0x20,0xE1,0xD8,0xE6,0x90,0x92,0x95,
++    0x17,0x52,0x9D,0x06,0xE8,0x85,0x47,0x11,0x88,0x0E,0x11,0x01,0x01,0xE7,0x40,0x03,
++    0x30,0x32,0xB0,0x41,0x30,0xA2,0xED,0x08,0x32,0x42,0xC0,0x01,0x58,0x33,0xC4,0xFB,
++    0x1C,0xF2,0x1D,0x33,0x58,0x33,0xC6,0xFB,0x1E,0xF2,0x1D,0x33,0x31,0x32,0x43,0x83,
++    0xC1,0xF3,0x18,0x82,0x31,0x32,0x03,0x83,0x40,0x73,0xC0,0xC3,0x18,0x32,0x04,0x73,
++    0xEA,0x20,0xE1,0xD8,0xE6,0x90,0x92,0x95,0x17,0x52,0x9D,0x06,0xE8,0x85,0x47,0x19,
++    0x88,0xE6,0x17,0x01,0x01,0xE7,0x40,0x03,0x30,0x32,0xB0,0x41,0x30,0xA2,0xED,0x08,
++    0x32,0x42,0xC0,0x01,0x58,0x33,0xC4,0xFB,0x1C,0xF2,0x1D,0x33,0x58,0x33,0xC6,0xFB,
++    0x1E,0xF2,0x1D,0x33,0x31,0x32,0x43,0x83,0xC1,0xF3,0x18,0x82,0x31,0x32,0x03,0x83,
++    0x40,0x73,0xC0,0xC3,0x18,0x32,0x00,0x73,0xEA,0x20,0xE1,0xD8,0xE6,0x90,0x92,0x95,
++    0x17,0x52,0x9D,0x06,0xEF,0x85,0xAF,0x85,0x44,0xE3,0x02,0xB0,0xCE,0x20,0x45,0xEB,
++    0xC0,0x68,0x45,0x09,0x88,0x26,0x40,0xE3,0xCC,0x20,0x45,0xDB,0xC0,0xE8,0x04,0x3F,
++    0x79,0x7A,0xC4,0xFB,0x78,0x09,0x88,0x1E,0x4D,0xE3,0xCE,0x20,0x54,0xDB,0xC2,0xE8,
++    0x40,0x13,0xF9,0xA0,0xC0,0x5B,0x41,0x09,0x88,0x76,0x48,0x01,0x8A,0x66,0x40,0x83,
++    0x1A,0xC2,0x04,0x83,0x44,0x83,0x1C,0xC2,0x01,0x83,0x44,0x03,0x19,0xC2,0x04,0x03,
++    0x40,0x83,0x18,0xC2,0x07,0x83,0xE8,0x85,0x48,0x09,0x88,0x66,0x44,0x83,0x1A,0xC2,
++    0x04,0x83,0x42,0x83,0x1C,0xC2,0x04,0x83,0x44,0x83,0x18,0xC2,0x01,0x83,0x40,0x03,
++    0x19,0xC2,0x00,0x03,0xE8,0x85,0x4F,0x11,0x89,0x66,0x40,0x03,0x19,0xC2,0x04,0x03,
++    0x44,0x83,0x18,0xC2,0x02,0x83,0x40,0x83,0x1A,0xC2,0x00,0x83,0x44,0x83,0x1C,0xC2,
++    0x07,0x83,0xEC,0x85,0x4F,0x19,0x88,0xE6,0x44,0x03,0x19,0xC2,0x00,0x03,0x41,0x83,
++    0x18,0xC2,0x04,0x83,0x44,0x83,0x1A,0xC2,0x04,0x83,0x42,0x83,0x1C,0xC2,0x00,0x83,
++    0xEF,0x85,0xAF,0xFD,0xF4,0x4C,0x30,0x62,0x29,0x01,0x48,0x93,0x4C,0x8B,0x35,0x72,
++    0xD1,0xE3,0x36,0x3A,0x48,0x32,0xC3,0x4B,0x48,0x09,0x88,0x0E,0x54,0x93,0xD9,0xE3,
++    0x41,0x19,0x80,0x96,0x33,0x79,0x48,0x0A,0x10,0xB0,0x41,0x11,0x8B,0xB6,0x30,0x02,
++    0x1B,0x3A,0x5A,0x02,0xC6,0x14,0xC0,0x00,0xC3,0xC0,0x31,0x9A,0x32,0x2A,0xEB,0xDA,
++    0x08,0x5B,0x0A,0x01,0x00,0x3F,0xC0,0x1B,0x18,0x9A,0x41,0xAB,0x00,0x5B,0xE9,0x90,
++    0xE2,0x00,0xE2,0x48,0x95,0x4D,0x16,0x0A,0x9F,0xAE,0xEF,0xFD,0x40,0x01,0x88,0x8E,
++    0x1E,0x01,0x10,0x5B,0x40,0x82,0x42,0x33,0x45,0xB0,0x05,0xB0,0x02,0x33,0x00,0x1B,
++    0x00,0x5B,0x40,0x0B,0x1C,0x81,0x18,0xCA,0x00,0x0B,0x40,0x0B,0x18,0x01,0x1C,0xCA,
++    0x00,0x0B,0x00,0x17,0x40,0x09,0x88,0x06,0x30,0xAA,0x01,0x01,0x00,0x27,0x40,0x8B,
++    0x00,0x6B,0xE8,0x90,0xE6,0x00,0x92,0x05,0x17,0x02,0x9D,0xC6,0xEF,0xFD,0xAF,0x85,
++    0x30,0x72,0xCC,0x2C,0xD5,0x63,0x36,0x22,0x46,0xEB,0x42,0xE3,0x40,0x01,0x88,0x1E,
++    0xDC,0x43,0x32,0x22,0x44,0xEB,0x40,0xE3,0x51,0x19,0x88,0x16,0x00,0x01,0x00,0xEF,
++    0x3E,0x10,0x7E,0x90,0x28,0x92,0x8B,0xAE,0x40,0x53,0x31,0xB2,0xB0,0x41,0xE8,0x98,
++    0x32,0xD2,0xD0,0x01,0x59,0xBB,0xC4,0x0B,0x1C,0x7A,0x1C,0xBB,0x59,0xBB,0xC6,0x0B,
++    0x1E,0x7A,0x1C,0xBB,0x41,0x93,0xC1,0x3B,0x19,0xD2,0x01,0x93,0x41,0xCB,0xC0,0x13,
++    0x18,0x8A,0x00,0xCB,0xEB,0x68,0xE1,0x20,0xE6,0x00,0x92,0x05,0x2E,0x02,0x9B,0xFE,
++    0xE8,0x85,0x57,0x29,0x88,0xE6,0x07,0x01,0x06,0xEF,0x38,0x10,0x7B,0x90,0x2E,0x92,
++    0x89,0xAE,0x40,0x53,0x30,0xB2,0xB0,0x41,0xE8,0x98,0x30,0xD2,0xD4,0x01,0x5A,0xBB,
++    0xC0,0x0B,0x19,0x7A,0x1E,0xBB,0x5C,0xBB,0xC4,0x0B,0x19,0x7A,0x19,0xBB,0x46,0x93,
++    0xC5,0x3B,0x19,0xD2,0x00,0x93,0x41,0xCB,0xC4,0x13,0x19,0x8A,0x01,0xCB,0xE8,0x68,
++    0xE2,0x20,0xE3,0x00,0x93,0x05,0x2E,0x02,0x9F,0xFE,0xEE,0x85,0xA8,0x85,0xF7,0x2C,
++    0x37,0x22,0xD4,0xAB,0xC4,0x34,0x00,0xB8,0x4E,0x03,0xC8,0x20,0x44,0xB2,0xC0,0xD8,
++    0xC3,0xC0,0x30,0x1A,0x58,0x01,0x88,0x1E,0xD8,0xAB,0xDB,0x34,0x4E,0xDB,0xCA,0xE0,
++    0x48,0x11,0x88,0xA6,0xB5,0x01,0xE4,0x8B,0x48,0x01,0x80,0x16,0x18,0x69,0x10,0xD8,
++    0x00,0x57,0x18,0x79,0x10,0xD8,0x00,0x3F,0xC0,0x0B,0x18,0xCA,0x41,0x33,0x01,0x8B,
++    0xA4,0x41,0xE0,0x00,0xE6,0x90,0x94,0x95,0x17,0x52,0x9D,0xAE,0xE8,0x85,0x4F,0x19,
++    0x8F,0xE6,0x07,0xF9,0x18,0x02,0x06,0x77,0x18,0x00,0x04,0x42,0x00,0x01,0x00,0x42,
++    0x00,0xB0,0x00,0x01,0x30,0x20,0x06,0x00,0x40,0x60,0x02,0x00,0x40,0x0B,0x01,0x43,
++    0xA4,0x41,0xE0,0x90,0x95,0x95,0x16,0x52,0x9F,0xC6,0xEF,0x85,0xAC,0xFD,0x87,0x25,
++    0x30,0x6A,0x30,0xB2,0x31,0xE2,0x48,0x3B,0x06,0xC9,0x07,0x00,0xC0,0x40,0x81,0x1C,
++    0xD0,0x83,0x87,0x14,0xC0,0x24,0x40,0x01,0x8B,0x16,0xD8,0x83,0x83,0x14,0x48,0x3B,
++    0x30,0x1A,0x11,0x19,0x08,0x01,0xB0,0x04,0xC7,0x24,0xB8,0xFF,0xF9,0x87,0x32,0x1A,
++    0x10,0x19,0x08,0x09,0xB0,0x04,0xC0,0x24,0xBA,0xFF,0xFF,0x4F,0x30,0x5A,0x11,0x01,
++    0x08,0x11,0xB0,0x04,0xA0,0x0C,0xC0,0x24,0xBC,0xFF,0xFF,0xC7,0x30,0x5A,0x11,0x09,
++    0x08,0x11,0xB0,0x04,0xA0,0x0C,0xC0,0x24,0xBC,0xFF,0xFF,0x87,0x36,0x82,0x81,0x01,
++    0xE2,0x0B,0x30,0x48,0x70,0x48,0xA2,0x0B,0x57,0xFA,0x0F,0xC1,0x00,0x8B,0x44,0x8B,
++    0x18,0xF9,0x9F,0x19,0x18,0xCA,0x00,0x8B,0x35,0x8A,0x89,0x01,0x01,0x07,0xF8,0x85,
++    0xE6,0x1B,0x48,0xD8,0x8E,0x16,0xE8,0x5B,0x5F,0x31,0x88,0xC6,0xE8,0x43,0x46,0x31,
++    0x88,0x1E,0x40,0x83,0x08,0x81,0x18,0x42,0x00,0x83,0x00,0x01,0x04,0x3F,0x00,0x08,
++    0xC2,0xCA,0x43,0x4B,0xDA,0x1C,0x00,0x10,0x92,0xCA,0xE4,0x00,0x90,0x05,0xCE,0x14,
++    0x17,0x42,0x9C,0xA6,0x30,0x5A,0x11,0x01,0x08,0x19,0xB0,0x04,0xA0,0x0C,0xC0,0x24,
++    0xBA,0xFF,0xFF,0xE7,0x30,0x5A,0x11,0x09,0x08,0x19,0xB0,0x04,0xA0,0x0C,0xC0,0x24,
++    0xBA,0xFF,0xFF,0xA7,0x30,0x1A,0x11,0x29,0x08,0x09,0xB0,0x04,0xC7,0x24,0xB8,0xFF,
++    0xF1,0xB7,0x37,0x1A,0x10,0x29,0x08,0x01,0xB0,0x04,0xC0,0x24,0xBF,0xFF,0xF7,0x7F,
++    0x87,0x45,0xE8,0x85,0xAC,0xFD,0x87,0x35,0x08,0xC9,0xC7,0x3C,0x02,0x48,0xC6,0x28,
++    0x48,0xD2,0xC6,0x3C,0xC0,0x20,0xC2,0x44,0xD0,0x33,0xC6,0x34,0x40,0x01,0x88,0x0E,
++    0xC2,0x44,0xD8,0x33,0xC4,0x44,0x80,0x01,0x86,0x2C,0xE0,0x03,0x43,0x01,0x88,0xE6,
++    0x08,0xF9,0x01,0x17,0xA2,0x0A,0xE1,0x00,0x95,0x05,0x14,0x82,0x9C,0xD6,0x3F,0x01,
++    0xB8,0x24,0xB8,0x14,0x06,0x57,0x49,0x62,0xC6,0x24,0x08,0x43,0x40,0x35,0x40,0x7E,
++    0xBA,0xFF,0xFF,0xE7,0x48,0x52,0x1E,0x01,0x00,0x01,0x00,0x67,0x04,0x10,0x32,0xA2,
++    0xF4,0x52,0x15,0xD2,0xEB,0x0E,0x30,0x1A,0xD4,0x5A,0x17,0x52,0xD3,0x0E,0x30,0x0A,
++    0xD2,0x4A,0xE3,0x00,0x95,0x05,0x14,0x82,0x9A,0x86,0x4F,0x81,0x90,0x2E,0x78,0x41,
++    0x80,0x76,0xC0,0x24,0x18,0xC2,0x85,0x24,0x00,0x27,0xC0,0x14,0x40,0x01,0x8C,0x0E,
++    0xB8,0x14,0x00,0x2F,0x40,0xF8,0xC3,0x24,0x18,0xC2,0x81,0x24,0x7E,0x01,0x88,0x96,
++    0x00,0x01,0x08,0x01,0x01,0x17,0xA0,0x0A,0xE4,0x00,0x92,0x05,0x17,0x82,0x9D,0xD6,
++    0xC0,0x14,0x80,0x1C,0x38,0x01,0x00,0x27,0xC0,0x14,0x18,0x3A,0xC2,0x14,0x40,0x00,
++    0x80,0x14,0xC0,0x14,0x47,0x01,0x88,0xBE,0xC6,0x2C,0x58,0x04,0xC0,0x41,0x91,0x05,
++    0x81,0x0C,0x00,0x17,0xC4,0x1C,0x18,0x3A,0x46,0x3A,0x0D,0x3B,0x40,0x35,0x40,0x7E,
++    0xB8,0xFF,0xFF,0xA7,0x58,0x32,0x0D,0x01,0x00,0x01,0x00,0x67,0x04,0x10,0x32,0xA2,
++    0xF4,0x52,0x15,0x52,0xEB,0x0E,0x30,0x0A,0xD4,0x4A,0x13,0xD2,0xD3,0x0E,0x30,0x12,
++    0xD2,0x5A,0xE5,0x00,0x95,0x05,0x14,0x82,0x98,0x86,0xC7,0x0C,0x10,0x0A,0xEC,0x0E,
++    0xC0,0x1C,0x18,0x3A,0xC2,0x1C,0x40,0x00,0x80,0x1C,0xC0,0x1C,0x46,0x01,0x88,0xCE,
++    0x78,0x01,0x88,0x06,0x38,0x09,0xC0,0x2C,0xA0,0x3B,0xC6,0x2C,0xE4,0x0B,0x46,0x92,
++    0x08,0x0B,0xC6,0x2C,0xE0,0x03,0x3E,0x09,0x16,0xF8,0x07,0x00,0x80,0x24,0x00,0x07,
++    0x40,0xF8,0xC3,0x24,0x17,0xC2,0x81,0xDE,0x78,0x01,0xC9,0x06,0x38,0x01,0x01,0x01,
++    0x08,0x01,0x00,0x17,0xA2,0x0A,0xE1,0x00,0x95,0x05,0x14,0x82,0x98,0xD6,0x07,0x01,
++    0x80,0x04,0x78,0x01,0x88,0x1E,0xC0,0x04,0xE6,0x00,0x92,0x05,0x80,0x04,0x00,0x01,
++    0x01,0x57,0xE0,0x0A,0x1E,0xCA,0x91,0x4D,0xA0,0x0A,0xD1,0x24,0x10,0x8A,0xCC,0x0E,
++    0x19,0xCA,0xA5,0x0A,0xE4,0x00,0x92,0x05,0x17,0x82,0x9D,0x96,0x40,0x35,0x40,0x7E,
++    0xBD,0xFF,0xF7,0xE7,0x01,0x01,0x00,0x0F,0xD2,0x2C,0x00,0x08,0xD6,0x4A,0x5B,0x94,
++    0xD0,0x48,0x94,0x4D,0xD0,0x04,0x50,0x01,0x8B,0x2E,0x48,0x21,0xE9,0xA6,0xE0,0x0A,
++    0x19,0xCA,0xA5,0x0A,0x01,0x87,0x48,0x91,0xE9,0x2E,0xE0,0x12,0x50,0x01,0x80,0x16,
++    0xF1,0x90,0xA2,0x12,0x01,0x47,0x10,0x89,0x1C,0x92,0x16,0x8A,0xD1,0x26,0xE0,0x0A,
++    0x48,0xF9,0x91,0x0E,0xE1,0x48,0xA2,0x0A,0xE4,0x00,0x92,0x05,0x16,0x82,0x9D,0xDE,
++    0x40,0xF8,0xC3,0x04,0x45,0x21,0xC8,0xE6,0x87,0x55,0xE8,0x85,0xAC,0xBD,0x87,0x75,
++    0xCE,0x84,0xD0,0x6B,0x10,0xC9,0xCF,0x7C,0x04,0x90,0xC6,0x48,0x18,0xF9,0xD1,0x7C,
++    0x0E,0xD8,0xC2,0x90,0x20,0xF9,0xDF,0x7C,0x00,0x20,0xCF,0xE0,0x30,0x09,0xDC,0x7C,
++    0x0C,0xB0,0xC9,0xD8,0x99,0x14,0x30,0x09,0xDD,0x7C,0x08,0xB0,0xC8,0xD8,0x9C,0x0C,
++    0x78,0x1D,0x40,0x01,0x88,0x0E,0xC0,0x84,0xD8,0x2B,0xC2,0x84,0xE0,0x03,0x44,0x29,
++    0xC0,0x56,0x00,0x01,0x02,0x37,0x00,0x18,0xD6,0x72,0x96,0xB2,0xD7,0x72,0x96,0x32,
++    0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0xB6,0x04,0x01,0x30,0x22,0x18,0x01,0x00,0xCF,
++    0x01,0xC0,0xD2,0x32,0x30,0x32,0xB4,0x6C,0x30,0x01,0x00,0x01,0xF8,0xB2,0xF4,0x42,
++    0xC3,0xB0,0x81,0xB0,0x31,0x82,0x93,0x32,0x40,0x74,0x00,0xB4,0xD0,0x02,0xF1,0x6C,
++    0xD9,0x00,0x04,0xC4,0x20,0x02,0x93,0x05,0x34,0x22,0xE4,0x90,0xE5,0x48,0xE4,0xF8,
++    0xE6,0xD8,0x92,0xDD,0x17,0x5A,0x9D,0x1E,0x71,0x1D,0x30,0x4A,0x30,0x02,0x83,0x0F,
++    0xD8,0x5F,0x95,0x0D,0x10,0x01,0x00,0xCF,0x01,0x01,0xF0,0x82,0xE0,0xB0,0x45,0x01,
++    0xE8,0x2E,0x48,0x01,0xEC,0x1E,0x10,0x42,0xE8,0x56,0x30,0x42,0x00,0x47,0x40,0x01,
++    0xD0,0x2E,0x48,0x01,0xD4,0x1E,0x10,0x42,0xD0,0x16,0x30,0x42,0x00,0x07,0x00,0x01,
++    0x07,0x98,0xD2,0x3A,0xD7,0xC0,0x91,0x02,0xE6,0x90,0x92,0x95,0x17,0x52,0x9D,0x1E,
++    0xC4,0x84,0xE0,0x03,0x40,0x29,0xC0,0xEE,0x00,0x01,0x10,0x01,0x02,0x3F,0x00,0x08,
++    0xF3,0x14,0xD0,0x1A,0x90,0x9A,0xCB,0x0C,0xA2,0x52,0xE0,0x00,0x95,0x05,0x16,0x42,
++    0x98,0xAE,0x07,0x01,0x12,0xF9,0x09,0x90,0x1A,0x09,0x0A,0xD8,0x00,0x47,0xE0,0x7C,
++    0x00,0x08,0xCA,0x48,0xC1,0x60,0x5C,0x24,0xC0,0x48,0x0E,0x64,0xE6,0x00,0x92,0x05,
++    0x17,0x42,0x9D,0xA6,0x87,0x8D,0xE8,0x85,0xAE,0xE5,0xD7,0x9B,0x9F,0x0C,0x18,0xF9,
++    0x06,0xD8,0xC6,0x58,0x34,0xF2,0x1C,0x09,0x0E,0xD8,0xC0,0x68,0x1C,0x09,0x09,0xD8,
++    0xC4,0x58,0x36,0xE2,0x1E,0xC9,0x07,0xD8,0xC0,0x48,0x8E,0x04,0x40,0x01,0x88,0x0E,
++    0xD8,0x83,0x82,0x0C,0x00,0x01,0x30,0x9A,0x9A,0x01,0x14,0xC3,0x11,0xC3,0x04,0xCF,
++    0x03,0x20,0x32,0x8A,0xD9,0x4A,0xD8,0x72,0xD8,0x48,0x94,0x75,0xC8,0x04,0x98,0x72,
++    0x08,0x01,0x38,0xB1,0xBD,0xFA,0x16,0xBA,0xE8,0x66,0x08,0x09,0x3A,0x09,0x50,0xF3,
++    0x01,0x3A,0x1C,0xF2,0x10,0xF3,0x02,0x77,0x00,0x01,0x00,0x42,0x40,0x60,0x02,0x00,
++    0xF8,0xFF,0x07,0x00,0xED,0xFB,0x16,0xBA,0xD0,0x2E,0x08,0x09,0x3C,0x09,0x50,0xF3,
++    0x01,0x3A,0x1C,0xF2,0x10,0xF3,0x4C,0x01,0x8D,0x96,0x08,0xC1,0xE0,0x4A,0x4C,0x01,
++    0x89,0x76,0xF8,0x7A,0x13,0xF0,0x31,0x0A,0xE4,0x4A,0xC8,0x70,0x30,0x8A,0xFB,0x4A,
++    0x04,0x48,0xCC,0x70,0x03,0xC8,0xD5,0x88,0x91,0x70,0x98,0x72,0x31,0x22,0xA3,0x0A,
++    0xE6,0x00,0x92,0x05,0xCC,0x0C,0x10,0x42,0x9F,0x16,0xEE,0xE5,0xAC,0xBD,0x87,0x65,
++    0x30,0x62,0x30,0xB2,0x40,0xFA,0x47,0x03,0x90,0x05,0x84,0x5C,0x40,0xF2,0x47,0x0B,
++    0x90,0x4D,0x8C,0x54,0x44,0x0B,0x92,0x4D,0x8E,0x4C,0x40,0x0B,0x90,0x4D,0x8C,0x44,
++    0x4C,0x0B,0x90,0x4D,0x8A,0x3C,0x48,0x0B,0x90,0x4D,0x8C,0x34,0x4C,0x0B,0x94,0x4D,
++    0x8E,0x2C,0x50,0x0B,0x90,0x4D,0x8C,0x24,0x4C,0x0B,0x96,0x4D,0x8A,0x1C,0x58,0x0B,
++    0x90,0x4D,0x8C,0x14,0x5C,0x0B,0x94,0x4D,0x88,0x0C,0x08,0x21,0x0C,0x0B,0x08,0x0B,
++    0xE7,0x0B,0x53,0x72,0x1E,0x8A,0x10,0x0B,0x08,0x01,0xDD,0x4A,0x01,0x0B,0x36,0x2A,
++    0xA9,0x01,0xEC,0x4B,0x1B,0x0B,0xEA,0x4B,0x1F,0x0B,0xE4,0x4B,0x0D,0x0B,0xE6,0x43,
++    0x40,0x01,0x80,0x3E,0x47,0x22,0x4F,0x32,0x00,0x0B,0x0A,0xC9,0x00,0x0B,0x08,0x09,
++    0x08,0x0B,0x02,0x3F,0x4F,0x12,0x47,0x02,0xCA,0xE1,0x00,0x0B,0x08,0x89,0x00,0x0B,
++    0x0A,0x41,0x08,0x0B,0xE0,0x03,0x45,0x09,0x8B,0xB6,0xD8,0x03,0x80,0x04,0x38,0x01,
++    0x00,0x3F,0x08,0x09,0x31,0x9A,0x31,0xD2,0x37,0x42,0xB8,0xFF,0xE3,0x67,0xE0,0xF8,
++    0x90,0xFD,0xC7,0x04,0x17,0x3A,0x9C,0xA6,0x31,0x9A,0x31,0x12,0x00,0x09,0xC8,0x64,
++    0xBD,0xFF,0xEF,0xC7,0xF3,0x43,0xB7,0x03,0x31,0x9A,0x31,0x12,0x00,0x09,0xC8,0x64,
++    0xB9,0xFF,0xEF,0xA7,0x30,0x12,0x01,0x09,0xCF,0x64,0xB8,0xFF,0xF1,0xFF,0x34,0x12,
++    0x00,0x09,0xC8,0x64,0xB9,0xFF,0xFF,0x87,0x48,0x32,0xC6,0x5C,0x06,0x43,0x40,0x32,
++    0xC8,0x54,0x00,0x0B,0xCA,0x4C,0x00,0x0B,0xCE,0x44,0x00,0x0B,0xC8,0x3C,0x08,0x0B,
++    0xCA,0x34,0x08,0x0B,0xCC,0x2C,0x08,0x0B,0xCE,0x24,0x10,0x0B,0xCE,0x1C,0x08,0x0B,
++    0xCA,0x14,0x18,0x0B,0xCC,0x0C,0x18,0x0B,0xE6,0x43,0x31,0x00,0xAB,0x66,0xF1,0x03,
++    0xF4,0x4B,0x15,0x42,0x89,0x46,0x31,0x02,0x82,0x01,0xE1,0x13,0x50,0x11,0x88,0x46,
++    0xE8,0x13,0x51,0x51,0x88,0x16,0x10,0x01,0xA0,0x13,0x02,0x9F,0xE1,0x90,0xAA,0x13,
++    0x05,0x87,0x50,0x53,0x50,0x01,0x88,0x2E,0x50,0x53,0x53,0x01,0x89,0x16,0xE8,0x13,
++    0x50,0x01,0x89,0x2E,0xF3,0x53,0xB7,0x13,0x11,0x09,0xB0,0x13,0xA0,0x13,0x02,0x0F,
++    0xE1,0x90,0xAA,0x13,0xF4,0x03,0x13,0x42,0x88,0x36,0x08,0x01,0x30,0x1A,0xB1,0x04,
++    0x30,0x42,0xD0,0x64,0xBF,0xFF,0xDF,0xEF,0x31,0x12,0x31,0x8A,0x07,0x11,0xB8,0xFF,
++    0xD8,0x3F,0x80,0x7D,0xEF,0x85,0xAF,0x85,0x4E,0xA3,0xD0,0xEB,0x33,0x70,0x72,0xB0,
++    0x4F,0x78,0x0E,0xF8,0x48,0xFA,0xC4,0x4B,0x48,0x09,0x88,0x0E,0x54,0xA3,0xD8,0xEB,
++    0x0F,0x01,0x18,0xF9,0x01,0x6F,0x40,0x13,0x47,0x93,0x02,0x92,0x90,0x95,0x00,0x14,
++    0x78,0x01,0x88,0x16,0x50,0xF9,0xEF,0x06,0x01,0x1C,0xE8,0x20,0xE2,0x00,0xE4,0x48,
++    0x95,0x4D,0x16,0x4A,0x9F,0x7E,0xEF,0x85,0xA8,0xC5,0x33,0x2A,0x34,0xB2,0x60,0x6A,
++    0x44,0x03,0x11,0x01,0x19,0x82,0x04,0x03,0x40,0x03,0x11,0x81,0x19,0x82,0x00,0x03,
++    0x40,0x03,0x11,0x09,0x19,0x82,0x00,0x03,0xE7,0x53,0x03,0xF9,0x80,0x81,0x18,0x12,
++    0x46,0x2A,0x14,0x13,0x13,0x99,0x00,0x13,0x14,0x41,0x00,0x13,0x12,0x91,0xEC,0x92,
++    0x50,0x01,0x80,0x16,0x10,0xC9,0x00,0x13,0x00,0x0F,0x10,0x89,0x00,0x13,0x30,0x52,
++    0x30,0x5A,0x09,0x01,0x00,0x09,0xB0,0x04,0xBD,0xFF,0xDF,0x5F,0x31,0x52,0x31,0x8A,
++    0x07,0x11,0xB8,0xFF,0xD3,0xAF,0x45,0x03,0x3F,0x00,0xAA,0xE6,0xEF,0xC5,0xAB,0x9D,
++    0x80,0x8D,0xCC,0x94,0xC8,0x4B,0x8A,0x84,0xE2,0x94,0xA0,0x01,0xD3,0x1B,0xD1,0x0B,
++    0x88,0x0C,0xC8,0x94,0xD0,0x6B,0x36,0x0A,0x8C,0x61,0x30,0x62,0xC8,0x94,0x30,0x01,
++    0xE0,0x4B,0x4C,0x09,0x88,0x56,0x08,0x01,0x02,0x27,0xC0,0x38,0x9A,0xF3,0xA1,0x32,
++    0xE2,0x48,0x92,0x4D,0xD6,0x94,0xD0,0x93,0x17,0x52,0xE4,0xB6,0x52,0x52,0x03,0xB3,
++    0x06,0xB3,0x04,0xB3,0x0E,0x01,0x18,0x4A,0x00,0x8B,0xC8,0x94,0xD0,0x4B,0xB6,0x8B,
++    0x0B,0x01,0x50,0x2A,0x34,0x01,0x00,0x78,0xC1,0xF8,0x0D,0xF3,0xC2,0x90,0xB2,0xB3,
++    0xE2,0x48,0x92,0x4D,0x4F,0x11,0xD8,0xA6,0xCC,0x94,0xE0,0x4B,0x4B,0x29,0xC8,0xA6,
++    0x00,0x48,0xC5,0x48,0x04,0x50,0xC3,0x70,0x14,0x09,0x06,0x90,0xC0,0xB0,0xB5,0x1C,
++    0xC0,0x48,0x8C,0x14,0x30,0x12,0x33,0x32,0xB0,0xC1,0x08,0x01,0x8A,0x3C,0x48,0xBA,
++    0x88,0x6C,0x88,0x64,0x30,0x32,0x04,0x01,0x32,0x22,0x04,0x27,0xC8,0x1C,0x00,0x01,
++    0xF0,0x42,0xF8,0x14,0x0B,0x01,0xF0,0xCA,0x32,0x7A,0xD0,0x08,0x97,0x4D,0x48,0xF9,
++    0xEF,0x06,0x08,0xF9,0xCB,0x38,0x86,0xF8,0x78,0xF9,0xEF,0x06,0x3B,0xF9,0x37,0x82,
++    0x82,0x3B,0xE0,0x00,0x30,0x32,0xC4,0xBB,0x10,0xFA,0x9C,0x46,0x10,0xCA,0xDC,0x36,
++    0x46,0x84,0xD9,0x48,0xC0,0x00,0x92,0x05,0x04,0x84,0x81,0x08,0x04,0x37,0x10,0xCA,
++    0xDC,0x16,0x00,0x78,0x00,0xBC,0x01,0x0F,0x39,0x01,0x00,0xBC,0x10,0xCA,0xDC,0x0E,
++    0x38,0x09,0xB8,0x3C,0x43,0x78,0x2B,0x3A,0xE8,0x26,0xF8,0x6C,0x10,0x7A,0xEC,0x2E,
++    0x88,0x6C,0x00,0x1F,0xFC,0x64,0x10,0x7A,0xE8,0x06,0x88,0x64,0x82,0x8B,0xE0,0x90,
++    0xE0,0xB0,0xC5,0x1C,0xE0,0x00,0x84,0x1C,0xC4,0x14,0xE0,0x00,0x83,0x14,0x30,0x02,
++    0xE2,0x00,0x92,0x05,0x35,0x22,0x2C,0x62,0xD8,0xC6,0xC5,0x3C,0x40,0x01,0x80,0xA6,
++    0x08,0x01,0x00,0x01,0x80,0x5C,0xC0,0x0C,0xC2,0x00,0x46,0x00,0x80,0x7C,0xC0,0x0C,
++    0x30,0x00,0x72,0x00,0x80,0x74,0x00,0x01,0x30,0x22,0x84,0x34,0x80,0x2C,0x80,0x24,
++    0xF3,0x90,0xF2,0x40,0x94,0x05,0x32,0x32,0x05,0x7F,0x02,0x77,0x32,0x02,0x03,0x00,
++    0x30,0x22,0xC4,0x34,0x00,0x00,0x82,0x34,0xC2,0x2C,0x00,0x00,0x80,0x2C,0xC0,0x24,
++    0x00,0x00,0x82,0x24,0x43,0x40,0x2B,0x82,0xE8,0x26,0xC0,0x83,0xF4,0x6C,0xD8,0x00,
++    0x80,0x83,0x00,0x1F,0xC0,0x83,0xF0,0x64,0xD8,0x00,0x84,0x83,0xC0,0x83,0x70,0x45,
++    0x37,0xBA,0xAB,0x82,0xC4,0x83,0x10,0xC2,0xDA,0xDE,0xE0,0x48,0x90,0x4D,0xF2,0x5C,
++    0xC1,0xB0,0x91,0xB5,0xB3,0x5C,0x30,0x32,0x39,0x09,0x18,0xF2,0x30,0xA2,0xF5,0x7C,
++    0x10,0x82,0xDD,0x76,0xF1,0x34,0x18,0xF2,0xB0,0x34,0xF0,0x0C,0x10,0x82,0xDD,0x46,
++    0xF1,0x2C,0x18,0xF2,0xB0,0x2C,0xF0,0x74,0x10,0x82,0xDD,0x16,0xC1,0x24,0x18,0xC2,
++    0x80,0x24,0x00,0x6F,0x18,0x00,0x04,0x42,0x00,0x01,0x00,0x42,0x10,0x78,0x00,0x00,
++    0x88,0x60,0x05,0x00,0x00,0xB0,0x00,0x01,0x58,0x80,0x04,0x01,0x78,0xF8,0x07,0x00,
++    0xF3,0x90,0x32,0x82,0xF2,0x00,0x92,0x05,0x33,0x32,0x34,0x82,0x45,0x01,0xD0,0x6E,
++    0x42,0xFA,0xB7,0x0B,0xD0,0x50,0xB3,0x13,0x36,0x12,0x1B,0x92,0x03,0x13,0x30,0x12,
++    0x08,0x13,0xD0,0x34,0x00,0x13,0xD2,0x2C,0x00,0x13,0xD4,0x24,0x00,0x13,0x36,0x01,
++    0x00,0xA7,0xC1,0x5C,0x87,0x0F,0xC0,0x07,0x90,0x05,0x80,0x5C,0x4D,0xA2,0x07,0x80,
++    0xC0,0x00,0x4A,0x13,0x40,0x45,0x08,0x01,0x1C,0x01,0x30,0xF2,0x30,0xE2,0x04,0xCF,
++    0x38,0x98,0x86,0x7E,0xC0,0x1B,0xF8,0x5C,0xD8,0xD8,0x96,0xDD,0x58,0x01,0xE8,0x36,
++    0x83,0x1B,0x20,0x9A,0x94,0xDD,0x36,0xF2,0xE2,0x48,0x92,0x4D,0x00,0x27,0x18,0x01,
++    0x80,0x1B,0x00,0x0F,0x18,0x01,0x80,0x1B,0x42,0x90,0xE2,0x00,0x32,0x1A,0xE3,0xD8,
++    0x94,0xDD,0x32,0xE2,0x2F,0x62,0xDD,0x1E,0xE3,0xB0,0x93,0xB5,0x30,0x82,0x83,0x5C,
++    0x45,0xFA,0x06,0x98,0xC0,0xD8,0x08,0xD3,0xCA,0x00,0xB4,0x0B,0x48,0x21,0xD8,0x0E,
++    0x76,0x09,0xD8,0x36,0x06,0x01,0x50,0xD2,0x04,0x08,0xC4,0x58,0xE4,0x08,0x02,0x70,
++    0xC0,0xB0,0x4D,0xEB,0x4D,0xB3,0x19,0xAA,0x08,0xEB,0xC0,0x80,0xF4,0x1B,0xF2,0x2B,
++    0xDA,0xD8,0xB2,0x1B,0x90,0x45,0x42,0x09,0xD8,0x76,0x07,0x09,0x9E,0x03,0x45,0x82,
++    0x0E,0x19,0x40,0x13,0x50,0x01,0x80,0x16,0x05,0x29,0x98,0x0B,0x04,0xF7,0x40,0x13,
++    0x50,0x01,0x80,0x16,0x05,0x21,0x98,0x0B,0x02,0xC7,0x40,0x0B,0x48,0x01,0x80,0x1E,
++    0x00,0x19,0x08,0x11,0x98,0x0B,0x05,0x8F,0x48,0x03,0x40,0x01,0x88,0x26,0xC0,0x94,
++    0x82,0x01,0xF5,0x03,0x40,0x51,0x98,0x0E,0x00,0x11,0x00,0x3F,0xC1,0x94,0x80,0x01,
++    0xD8,0x03,0x44,0x01,0x80,0x0E,0x00,0x11,0x00,0x07,0x00,0x09,0xDC,0x0B,0xE5,0x50,
++    0x9D,0x13,0xD7,0x13,0x38,0x90,0xA2,0x0E,0xF5,0x48,0x9A,0x0B,0xE0,0x0B,0x13,0x29,
++    0x10,0x0A,0x94,0x0E,0xA0,0x13,0x01,0xEF,0x10,0x0A,0xCC,0x46,0x40,0x09,0x88,0x16,
++    0x09,0x81,0xA7,0x0B,0x00,0xB7,0xD0,0x48,0x01,0x52,0xA4,0x13,0x00,0x97,0x40,0x19,
++    0xC8,0x0E,0x08,0x19,0x02,0x07,0x90,0x0D,0xE0,0x13,0x51,0x01,0x82,0x16,0xF0,0x90,
++    0xA0,0x13,0x01,0x3F,0xD2,0x94,0xF0,0x48,0xCA,0x93,0x1C,0x52,0xCA,0x84,0xC0,0x88,
++    0xD0,0x94,0x88,0x8B,0xA0,0x03,0x83,0x9D,0xEF,0x85,0xAF,0xBD,0x80,0x6D,0x34,0x6A,
++    0xD1,0x63,0x37,0x42,0x80,0x01,0x82,0x64,0xC8,0x03,0x86,0x3C,0xC4,0x64,0xD0,0x03,
++    0x30,0x00,0xA8,0x1E,0x02,0x91,0xEC,0x02,0x40,0x01,0x80,0xAE,0xC5,0x6C,0x00,0x08,
++    0xC3,0x40,0x00,0x08,0x12,0x09,0xC6,0x08,0x04,0x90,0xC4,0x48,0xC0,0x10,0x04,0x01,
++    0x18,0x01,0x00,0x2F,0x00,0x5C,0x00,0x9C,0xE4,0x48,0xE4,0x90,0xE2,0x00,0x92,0x05,
++    0x17,0x02,0xDD,0xBE,0x87,0x85,0xE8,0x85,0x00,0xE9,0xC9,0x6C,0x08,0x00,0xC2,0x40,
++    0x70,0x82,0xEC,0x03,0x08,0x83,0xD7,0x7C,0x91,0x04,0x30,0x5A,0x08,0x01,0x00,0x11,
++    0xD7,0x6C,0xB8,0xFF,0xCC,0xB7,0x45,0x5A,0x80,0x01,0x42,0x0B,0x34,0x5A,0x0B,0xCC,
++    0x5E,0x8B,0x09,0xCC,0x58,0x8B,0x13,0xCC,0x5A,0x8B,0x15,0xCC,0x44,0x8B,0x17,0xCC,
++    0x48,0x2A,0x44,0x53,0x17,0xD4,0x4E,0x93,0x18,0xD4,0x10,0x89,0x00,0x93,0x17,0x19,
++    0x18,0x93,0x43,0x53,0x1C,0x11,0x18,0xD2,0x00,0x53,0x40,0x0B,0x18,0xCA,0x00,0x0B,
++    0x35,0x42,0xE1,0x4B,0x80,0x01,0x81,0x5C,0x4A,0x09,0x88,0x66,0x68,0x44,0x81,0x14,
++    0x34,0x8A,0x59,0x43,0x90,0x35,0xB6,0x0C,0x00,0x01,0x80,0x04,0xD6,0x6C,0x08,0x09,
++    0x04,0x00,0x07,0x48,0xC2,0x00,0xC4,0x00,0x83,0x54,0x40,0x92,0x18,0x33,0x0A,0x01,
++    0x37,0x42,0xB9,0xFF,0xC0,0xBF,0xFA,0x54,0xC1,0x64,0x30,0x5A,0xC9,0x0B,0x34,0xC2,
++    0xD7,0x7C,0xB8,0xFF,0xEB,0x07,0x4C,0x6A,0x10,0x01,0x00,0x01,0x02,0x67,0x00,0x18,
++    0x37,0xE2,0xF4,0xDA,0x10,0x5A,0xD4,0x0E,0x33,0x0A,0xD3,0xCA,0x10,0x9A,0xEC,0x0E,
++    0x35,0x12,0xD3,0xD2,0xE2,0x00,0x92,0x05,0x17,0x02,0xDD,0x86,0xC4,0x14,0xE0,0x00,
++    0x10,0x0A,0x9C,0x36,0xC0,0x04,0x40,0x01,0x8B,0x9E,0x40,0x80,0x40,0x08,0xC2,0x70,
++    0x00,0x3F,0xC0,0x14,0xF4,0x00,0x14,0x12,0xE0,0x5E,0x00,0x09,0x83,0x04,0xE0,0xB0,
++    0x90,0xB5,0x77,0x01,0x80,0x16,0xC0,0x0C,0x16,0x32,0x9C,0x36,0x70,0x01,0x88,0x06,
++    0x30,0x09,0xC0,0x5C,0x88,0x33,0xC0,0x5C,0xCA,0x0B,0x40,0x92,0x18,0x0B,0x32,0x01,
++    0x35,0x42,0x81,0x01,0x81,0x4C,0x80,0x01,0x83,0x44,0x00,0x4F,0xC4,0x3C,0x10,0x32,
++    0xD0,0x6E,0xC0,0x44,0xE0,0x03,0xC8,0x44,0x32,0x00,0x72,0x00,0xA2,0x43,0x40,0x4A,
++    0x0C,0x41,0x00,0x0B,0x47,0x0B,0x10,0xF9,0x90,0x21,0x18,0x8A,0x00,0x0B,0xC8,0x6C,
++    0x02,0x00,0xC5,0x08,0x06,0x00,0x13,0x09,0xC4,0x40,0x00,0x90,0xC4,0x00,0xC4,0x48,
++    0x70,0x01,0x88,0x66,0x12,0x01,0x78,0x0A,0x00,0x37,0x18,0x01,0x00,0x1C,0x00,0x7C,
++    0xE4,0x00,0xE4,0x48,0xE2,0x90,0x92,0x95,0x17,0x12,0xDD,0xB6,0x00,0x0F,0xD9,0x6C,
++    0x06,0x10,0xC7,0x90,0x1C,0x09,0x06,0xD8,0xC4,0x90,0x36,0xA2,0x18,0x01,0x00,0x9F,
++    0x30,0x3A,0x13,0x01,0xF0,0xD2,0x3D,0x01,0xFC,0x3A,0x16,0xBA,0xD0,0x06,0x00,0x14,
++    0x3E,0x01,0xF8,0x7A,0x10,0xBA,0xEC,0x06,0x04,0x54,0xE0,0x00,0xE3,0x48,0x34,0x12,
++    0xE4,0x90,0x34,0xA2,0xE2,0xD8,0x92,0xDD,0x17,0x1A,0xDD,0x4E,0xC4,0x3C,0x10,0x32,
++    0x80,0x0E,0xC1,0x44,0xE6,0x03,0x48,0x00,0x88,0x1E,0xC0,0x4C,0xE8,0x03,0x46,0x31,
++    0x88,0xBE,0xC7,0x4C,0xE8,0x03,0x46,0x31,0x89,0x26,0x40,0x12,0x40,0x0B,0x10,0x81,
++    0x18,0x8A,0x00,0x0B,0xCF,0x6C,0x00,0x00,0xC6,0x00,0x0A,0x09,0x02,0x48,0xC4,0x00,
++    0xC9,0x64,0x30,0x5A,0xC8,0x4B,0xD4,0x7C,0xBE,0xFF,0xE7,0xEF,0xE3,0xB0,0x93,0xB5,
++    0xC4,0x3C,0x10,0x32,0xE8,0x96,0x44,0xBA,0x34,0x5A,0x4B,0xCC,0x80,0x01,0x02,0x0B,
++    0x46,0xA2,0x48,0xCC,0x18,0x0B,0x50,0xCC,0x1A,0x0B,0x52,0xCC,0x1C,0x0B,0x54,0xCC,
++    0x00,0x0B,0x4E,0x8A,0x50,0xD4,0x06,0x53,0x5E,0xCC,0x08,0x0B,0x37,0x97,0xAF,0xFD,
++    0x81,0xED,0xE4,0x3C,0x30,0xAA,0x00,0x01,0x80,0x7C,0x80,0x74,0xC6,0x34,0xD1,0x03,
++    0x81,0x6C,0xC0,0x34,0xDA,0x03,0xF2,0x00,0x90,0x05,0x86,0x64,0x00,0x01,0x80,0x5C,
++    0x80,0x54,0x80,0x4C,0xC4,0x34,0xC9,0x03,0x00,0x00,0x82,0xBC,0x08,0xA1,0x05,0x3F,
++    0x58,0x80,0x04,0x01,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0xF8,0xFB,0x07,0x00,
++    0xC2,0x34,0xF1,0x0A,0x80,0x40,0x82,0xB4,0xC1,0x34,0xD9,0x04,0xE7,0x03,0x9C,0xF9,
++    0x98,0x29,0x41,0x09,0x88,0x76,0xC0,0x6C,0x1E,0x42,0xC3,0x08,0xD0,0xEC,0x00,0x01,
++    0x00,0x2F,0x40,0xB4,0x82,0x73,0xE0,0x48,0xE2,0x90,0xE4,0x00,0x90,0x05,0xF2,0x6C,
++    0x17,0x82,0xDD,0xB6,0x00,0x01,0x80,0x9C,0x80,0xA4,0x80,0xAC,0xC4,0xEC,0x30,0x32,
++    0x70,0x1D,0xC8,0x6C,0x32,0x42,0x19,0x42,0x86,0xE4,0xC0,0x00,0x30,0x22,0x84,0xDC,
++    0x40,0xAA,0x47,0x13,0x48,0x1B,0x08,0x01,0x03,0x1F,0x31,0x82,0x30,0x3A,0x43,0x04,
++    0xC6,0xFB,0xD9,0x00,0x91,0x05,0x00,0x84,0x38,0xB8,0x86,0x26,0xFE,0xAC,0xC8,0x00,
++    0x90,0x05,0x80,0xAC,0x06,0x57,0x38,0xF8,0x80,0x26,0xF8,0xA4,0xC8,0x00,0x96,0x05,
++    0x80,0xA4,0x00,0x1F,0xFE,0x9C,0xC8,0x00,0x90,0x05,0x80,0x9C,0xE3,0xB0,0x35,0x82,
++    0xE4,0x00,0x34,0x32,0x32,0x02,0xE3,0x00,0x32,0x22,0x44,0x90,0x42,0xD8,0xE2,0x48,
++    0x90,0x4D,0xC2,0x6C,0x16,0x0A,0xDC,0xC6,0x79,0xFA,0xF6,0xCB,0x48,0x01,0xE8,0x26,
++    0xC0,0xAC,0x80,0x07,0xF0,0x8F,0x94,0x05,0x83,0xAC,0xF0,0xCB,0x48,0x01,0xE8,0x56,
++    0x48,0x09,0x88,0x1E,0xC2,0xA4,0x80,0x00,0x80,0xA4,0x00,0x27,0xC0,0xA4,0x80,0x07,
++    0xF0,0x1F,0x94,0x05,0x85,0xA4,0xF0,0xCB,0x48,0x01,0xE8,0x56,0x48,0x09,0x88,0x1E,
++    0xC2,0x9C,0x80,0x00,0x80,0x9C,0x00,0x27,0xC0,0x9C,0x80,0x07,0xF0,0xAF,0x93,0x05,
++    0x80,0x9C,0xF0,0xEC,0x40,0x1D,0x80,0x04,0xC0,0xDC,0x80,0x14,0x40,0xC3,0x81,0x94,
++    0x48,0xC3,0x81,0x8C,0xC2,0x34,0x81,0x01,0x84,0xD4,0xD0,0x03,0x38,0x00,0x86,0x7E,
++    0x40,0xC3,0x83,0x84,0x40,0xC3,0x85,0x7C,0x40,0xC3,0x87,0x74,0xC6,0xD4,0xD0,0x03,
++    0x80,0x5C,0xC0,0xD4,0xD8,0x03,0x80,0x54,0xC2,0xD4,0xD8,0x03,0x80,0x4C,0x00,0x0F,
++    0x00,0x01,0x80,0x84,0xC0,0x04,0xC9,0xE4,0x80,0xA1,0xC1,0x40,0x80,0x0C,0xC0,0xE4,
++    0xCA,0x04,0x01,0x00,0xC5,0x00,0x4A,0xCA,0xC0,0x38,0x02,0x01,0x80,0xC4,0x00,0x09,
++    0x00,0x42,0x85,0xCC,0x00,0x5F,0xC5,0x94,0x38,0x00,0x86,0x0E,0xC0,0xAC,0x00,0x2F,
++    0xC6,0x8C,0x38,0x00,0x80,0x0E,0xC0,0xA4,0x00,0x07,0xC0,0x9C,0x40,0x01,0xE8,0x66,
++    0xD0,0x04,0x08,0x01,0xF0,0x8A,0x4A,0x01,0xEC,0x3E,0x10,0x0A,0xD0,0x06,0x30,0x42,
++    0x40,0x8C,0xD1,0x40,0x91,0x15,0x00,0x94,0x00,0x97,0xD1,0x04,0x0A,0x01,0xF0,0x8A,
++    0x49,0x01,0xD0,0x5E,0x40,0x01,0xD0,0x2E,0x10,0x0A,0xEC,0x06,0x31,0x42,0x40,0x8C,
++    0xD1,0x40,0x00,0x84,0x15,0x01,0xF0,0x92,0xC6,0x84,0x38,0x00,0x80,0x06,0xC1,0x14,
++    0xC4,0x0B,0xD0,0x40,0x90,0x05,0xD8,0x74,0x38,0xD8,0x86,0x36,0xDC,0x4C,0x10,0xC2,
++    0xE8,0xB6,0xC0,0x4C,0xD1,0x40,0x00,0x84,0x00,0x97,0xD8,0x7C,0x38,0xD8,0x86,0x36,
++    0xDC,0x54,0x10,0xC2,0xE8,0x66,0xC0,0x54,0xD1,0x40,0x00,0x84,0x00,0x47,0xD8,0x5C,
++    0x10,0xC2,0xEC,0x2E,0xC0,0x5C,0xD0,0x40,0x00,0x84,0x01,0x0F,0x15,0x01,0xF0,0x92,
++    0xC0,0x0C,0xC0,0x03,0xD0,0x00,0x94,0x05,0xC8,0xF4,0x48,0x01,0x88,0x06,0xC9,0xBC,
++    0x10,0x42,0xDC,0xAE,0x40,0x03,0xC9,0xCC,0x18,0x09,0x18,0x42,0x00,0x03,0x69,0x01,
++    0x83,0x26,0xF0,0x48,0x34,0xD2,0x00,0x52,0x19,0x82,0x00,0x03,0xC4,0x64,0x10,0x2A,
++    0x93,0x0E,0xE1,0x40,0x31,0xD2,0x40,0x0B,0x00,0x12,0x1C,0x8A,0x00,0x0B,0x01,0xD7,
++    0xCC,0xB4,0x10,0x42,0xE1,0xBE,0x40,0x03,0xC8,0xCC,0x18,0x42,0x00,0x03,0x01,0x97,
++    0xC0,0xF4,0x40,0x09,0x89,0x16,0x40,0x84,0x00,0xC4,0x01,0x67,0x41,0xC4,0x41,0x8C,
++    0xC4,0x00,0x92,0x05,0x00,0xC4,0xC9,0xD4,0xD0,0xF4,0xC0,0x4B,0x10,0x8A,0x8C,0x16,
++    0x85,0x07,0xE8,0x87,0x00,0x84,0xC9,0x14,0x40,0x84,0x81,0x43,0xE0,0xF8,0xC5,0x0C,
++    0xE0,0x00,0x82,0x0C,0xE0,0xB0,0xC5,0x14,0xE0,0x00,0x82,0x14,0xC4,0x04,0xE0,0x00,
++    0x80,0x04,0xC0,0x94,0x40,0x00,0x82,0x94,0xC2,0x8C,0x40,0x00,0x80,0x8C,0xC0,0x84,
++    0x40,0x01,0x80,0x46,0xC2,0x84,0x40,0x00,0x80,0x84,0xC0,0x7C,0x40,0x00,0x82,0x7C,
++    0xC2,0x74,0x40,0x00,0x80,0x74,0xC0,0xC4,0xE2,0x00,0x92,0x05,0x80,0xC4,0xC8,0x6C,
++    0xC4,0xC4,0x10,0x42,0xD2,0x06,0x38,0x77,0x87,0x0D,0xE9,0x85,0xA8,0x85,0x37,0x6A,
++    0xF0,0x2C,0x30,0x22,0x30,0x8A,0x30,0xFA,0x37,0xC2,0xB9,0xF7,0xF1,0x5F,0x30,0xDA,
++    0x31,0x92,0x31,0x4A,0x37,0x02,0xB9,0xFF,0xDF,0xB7,0xE9,0x85,0xAC,0xBD,0x87,0x45,
++    0x33,0x6A,0xD8,0x43,0x87,0x24,0xD0,0x43,0x85,0x1C,0xE0,0x43,0x40,0x29,0x90,0x2E,
++    0x06,0x01,0x18,0x02,0x18,0x43,0x03,0x01,0x18,0x43,0x05,0x6F,0x02,0x89,0xEE,0x02,
++    0x38,0x00,0xAA,0x26,0x4D,0x52,0x5A,0x43,0x1B,0x42,0x18,0x43,0x02,0x27,0x48,0x42,
++    0x5E,0x43,0x1D,0x4A,0x1B,0x42,0x18,0x43,0x39,0x01,0x30,0x42,0x80,0x01,0x85,0x3C,
++    0xC0,0x01,0x83,0x34,0x00,0xD7,0x03,0x01,0x1B,0x43,0x5F,0x73,0x20,0x01,0x00,0x17,
++    0x43,0xB0,0xE3,0x20,0x97,0x25,0x3F,0x80,0x88,0x16,0xC0,0x24,0x17,0x22,0x9C,0xBE,
++    0xC4,0x24,0x10,0x22,0x87,0xDE,0xA3,0x63,0xC1,0x44,0x08,0xE9,0xCA,0x00,0x08,0x48,
++    0xC1,0x00,0x4A,0xC2,0xEE,0x03,0x08,0x43,0x30,0x12,0x09,0x01,0x00,0x09,0xD8,0x54,
++    0xBC,0xF7,0xF7,0x8F,0xD0,0x54,0x90,0x04,0x31,0x5A,0x31,0x0A,0x00,0x11,0xD0,0x44,
++    0xBE,0xF7,0xF7,0xFF,0x42,0x82,0x41,0x0B,0x3F,0x48,0xAA,0xE6,0x40,0x0B,0x10,0x11,
++    0x18,0x8A,0x00,0x0B,0x40,0x5A,0x09,0x41,0x00,0x0B,0x44,0x0B,0x10,0xF9,0x97,0x19,
++    0x18,0x8A,0x00,0x0B,0x78,0x01,0x88,0x2E,0x30,0x4A,0xC1,0x44,0xB9,0xFF,0xDF,0x3F,
++    0x00,0x01,0x80,0x14,0xC3,0x1C,0x18,0x02,0x00,0x08,0xC2,0x44,0xC6,0x40,0x08,0x09,
++    0x02,0x48,0xC4,0x00,0x81,0x2C,0x00,0x47,0xC6,0x3C,0xE8,0x03,0x40,0x31,0x88,0x36,
++    0x48,0xE2,0x40,0x43,0x10,0x81,0x18,0x82,0x00,0x43,0x38,0x31,0x07,0x07,0x39,0x80,
++    0x80,0x9E,0x08,0x09,0x00,0x0A,0x05,0x07,0xFF,0x85,0x59,0x43,0x10,0x42,0x88,0x1E,
++    0xC6,0x3C,0xE8,0x03,0x47,0x31,0x88,0xBE,0x50,0x15,0xA8,0x04,0x91,0x0C,0x30,0x12,
++    0x30,0xCA,0xD9,0x44,0xC7,0x2C,0xB8,0xFF,0xE8,0x17,0xC7,0x1C,0xCA,0x2C,0x00,0x00,
++    0xC0,0x00,0x82,0x2C,0x43,0xB0,0xE3,0x20,0x90,0x25,0xC7,0x24,0x16,0x22,0x9C,0x9E,
++    0x78,0x01,0x88,0x0E,0xC3,0x14,0x18,0x43,0xE7,0xF8,0x93,0xFD,0xC0,0x34,0xC0,0x03,
++    0xE5,0x00,0x12,0xC2,0xCB,0x5E,0x38,0xF7,0x58,0x80,0x04,0x01,0x20,0x20,0x07,0x00,
++    0xAA,0xAA,0xAA,0xAA,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0x39,0xFF,0x37,0x52,
++    0x00,0x01,0xC8,0x54,0xBC,0xF7,0xEF,0x27,0x87,0x5D,0xE8,0x85,0xAC,0xBD,0x87,0x2D,
++    0x33,0x62,0xD8,0x03,0x87,0x14,0xD0,0x0B,0x88,0x0C,0xC8,0x0C,0xC2,0x14,0x18,0x42,
++    0xCA,0x2C,0x00,0x10,0xC6,0x90,0x0A,0x09,0x02,0x48,0xC4,0xA8,0xA8,0x24,0xC8,0x2C,
++    0x8A,0xA1,0xC1,0x30,0xCF,0x2C,0x88,0xF9,0x8A,0x29,0xC1,0x38,0xB8,0x1C,0xC8,0x2C,
++    0xC0,0x14,0xC0,0x40,0x0A,0xE9,0x09,0x48,0xC0,0x00,0xEA,0x03,0x4E,0xFA,0x0F,0x43,
++    0xD0,0x3C,0x90,0x04,0x30,0x1A,0x09,0x01,0x00,0x09,0xD0,0x2C,0xBA,0xF7,0xF7,0x4F,
++    0x30,0x12,0x01,0x11,0xCF,0x3C,0xB8,0xF7,0xE8,0x9F,0x0A,0x01,0x00,0x09,0xD8,0x3C,
++    0xD7,0x14,0xB8,0xF7,0xE8,0x47,0xD7,0x3C,0x91,0x04,0x30,0x1A,0x00,0x11,0xD0,0x2C,
++    0xCF,0x14,0xB8,0xF7,0xF0,0xB7,0xD1,0x3C,0x92,0x04,0x00,0x29,0xE9,0x0A,0x30,0x1A,
++    0x11,0x01,0x30,0x42,0xBF,0xFF,0xF7,0x97,0x08,0x09,0x30,0x42,0xD8,0x3C,0xD0,0x14,
++    0xBE,0xF7,0xEF,0x8F,0xD0,0x3C,0x90,0x04,0x30,0x1A,0x01,0x19,0xD0,0x2C,0xC8,0x14,
++    0xB8,0xF7,0xF7,0xFF,0x30,0x12,0x01,0x01,0xCF,0x3C,0xB8,0xF7,0xE8,0x4F,0xD1,0x3C,
++    0x90,0x04,0x08,0x01,0x30,0x1A,0x31,0x42,0xD7,0x2C,0xB8,0xF7,0xF5,0x97,0xE0,0x03,
++    0x40,0x29,0xC0,0x96,0x00,0x01,0x08,0x01,0x05,0x67,0xD8,0x13,0x10,0x12,0xC4,0x06,
++    0x01,0x4C,0x41,0x54,0x81,0x93,0x41,0x54,0x83,0xD3,0xE1,0xF8,0xE5,0xB0,0xE3,0x68,
++    0xE6,0x00,0x92,0x05,0xD4,0x0C,0x10,0x82,0x98,0x7E,0xCF,0x1C,0xC0,0x24,0x10,0x01,
++    0x00,0x57,0x40,0x1C,0xC2,0x6B,0xC8,0xD8,0x92,0xDD,0x80,0xD8,0x00,0x1C,0x80,0x5B,
++    0xE4,0x48,0xE2,0x00,0xE6,0x90,0x92,0x95,0xDC,0x1B,0x15,0x9A,0xC0,0x8E,0x87,0x45,
++    0xEB,0x85,0xAF,0x85,0x35,0x42,0x80,0xC1,0x34,0x6A,0xA8,0x01,0x5F,0x53,0x51,0x73,
++    0x53,0x5B,0x55,0x63,0xE0,0x6B,0x69,0x01,0x81,0xD6,0x32,0x2A,0x19,0xEA,0x18,0xAA,
++    0x18,0xAA,0x80,0x0E,0x28,0x19,0x80,0x2B,0xC0,0x2B,0x68,0x01,0x83,0x0E,0xF0,0x68,
++    0x81,0x2B,0x30,0x2A,0x10,0xAA,0x80,0x26,0x30,0xEA,0x10,0xAA,0x88,0x0E,0x10,0x09,
++    0x01,0x97,0x30,0x2A,0x10,0xAA,0x81,0x26,0x30,0xEA,0x10,0xAA,0x88,0x0E,0x10,0x11,
++    0x00,0x57,0x60,0x01,0x80,0x1E,0x10,0x9A,0x88,0x0E,0x10,0x79,0x01,0x27,0x10,0x9A,
++    0x80,0x0E,0x10,0x21,0x00,0x07,0x10,0x01,0xC8,0x1B,0x24,0x01,0x10,0x9A,0x8C,0x0E,
++    0x50,0x01,0x88,0x0E,0x01,0x24,0x04,0x57,0x40,0x1C,0x2C,0xC9,0x0D,0x68,0x13,0x5A,
++    0x92,0x0E,0xE0,0xD8,0x00,0x1C,0x34,0x5A,0x2D,0x09,0x98,0x01,0x50,0x11,0x80,0x26,
++    0xE0,0x8E,0x50,0x01,0x80,0xDE,0x50,0x09,0x8C,0xCE,0x40,0x34,0x70,0xE1,0xC9,0xB6,
++    0xF0,0xDB,0x5A,0x51,0x90,0x9E,0x30,0x5A,0x98,0x01,0xE6,0xF3,0x18,0x72,0xA1,0xF3,
++    0xA4,0x6B,0x04,0x24,0x00,0x5F,0x50,0x21,0x80,0x4E,0x50,0x79,0x8C,0x3E,0x40,0x34,
++    0x70,0xE1,0xC9,0x26,0xF0,0xDB,0x5A,0x51,0x94,0x0E,0xA0,0x6B,0x04,0x24,0x8C,0x13,
++    0xEF,0x85,0xAB,0x9D,0x80,0x4D,0x34,0x32,0xC4,0x54,0xD0,0x03,0x80,0x3C,0xC0,0x54,
++    0xD0,0x03,0x86,0x34,0xC0,0x54,0xE8,0x03,0x43,0xF1,0x98,0x8E,0xC5,0x54,0x80,0x01,
++    0xF0,0x03,0x40,0x01,0x88,0x66,0xC3,0x54,0xCA,0x03,0x34,0x00,0x70,0x00,0x80,0x2C,
++    0x04,0x09,0x06,0x00,0xC1,0xB8,0x31,0xA2,0xA1,0xA1,0x01,0x81,0xF7,0x82,0x41,0x81,
++    0xDF,0x26,0xC0,0x81,0x30,0x84,0x01,0x09,0x80,0x24,0x00,0x0F,0x00,0x01,0x80,0x24,
++    0x01,0x91,0xF1,0x82,0x0E,0x79,0x1F,0x4A,0x10,0x42,0xE4,0x26,0x83,0x81,0x37,0x84,
++    0x00,0x09,0x80,0x1C,0x00,0x0F,0x00,0x01,0x83,0x1C,0x40,0xEA,0x82,0x14,0x10,0x02,
++    0x80,0x0C,0x00,0x01,0x81,0x44,0x00,0xBF,0x29,0x01,0x00,0x77,0x01,0x01,0xF0,0xC2,
++    0xCC,0x2C,0x10,0x42,0xD0,0xCE,0x40,0x01,0xE8,0x56,0xC8,0x14,0x10,0x42,0xEC,0x06,
++    0x80,0x14,0xC0,0x24,0x40,0x01,0x80,0xE6,0xC2,0x03,0xF1,0x00,0x80,0x03,0x01,0xC7,
++    0x40,0x01,0xD0,0xB6,0xCC,0x0C,0x10,0x42,0xD0,0x06,0x80,0x0C,0xC0,0x1C,0x40,0x01,
++    0x81,0x7E,0xC0,0x03,0xE1,0x00,0x82,0x03,0x00,0x5F,0xC0,0x54,0x08,0x21,0xEB,0x03,
++    0x83,0x07,0xD8,0x47,0x48,0x19,0x8B,0x26,0xC9,0x2C,0xC0,0x03,0x42,0x48,0xD2,0x00,
++    0x85,0x03,0xE1,0xF8,0xE3,0x20,0xE3,0x68,0x90,0x6D,0xC7,0x34,0x16,0x2A,0x9C,0x6E,
++    0xC2,0x44,0xE0,0x00,0x90,0x05,0x86,0x44,0xC8,0x3C,0xC0,0x44,0x16,0x42,0x9C,0x1E,
++    0x70,0x8C,0xC1,0x14,0xC1,0x40,0x30,0x84,0x70,0x8C,0xC3,0x0C,0xC3,0x40,0x30,0x84,
++    0x37,0x57,0xAC,0xBD,0x80,0x15,0x34,0x62,0x37,0xBA,0xE0,0x2B,0xDF,0x33,0xD3,0x03,
++    0x1A,0x42,0x03,0x08,0xC0,0x14,0xC0,0x40,0x0C,0x09,0x06,0x48,0xC0,0x00,0x82,0x0C,
++    0x36,0x02,0x81,0x01,0xE4,0x0B,0x10,0x01,0x18,0x8A,0xA0,0x0B,0x00,0xB1,0xED,0x02,
++    0x42,0x01,0x80,0x46,0x09,0x09,0x30,0xDA,0x30,0x52,0x31,0x42,0xBC,0xF7,0xE7,0x5F,
++    0x30,0x1A,0xB9,0x04,0x08,0x01,0x00,0x19,0xD7,0x14,0xB8,0xF7,0xE2,0xD7,0x06,0x29,
++    0xE9,0x0A,0x30,0x1A,0x30,0xD2,0xC1,0x0C,0xBE,0xFF,0xC7,0xEF,0x58,0x03,0x17,0x09,
++    0x35,0x8A,0x00,0x4A,0x1F,0x42,0x18,0x03,0xE7,0x68,0x93,0x6D,0x58,0x0B,0x03,0x0F,
++    0xE7,0x68,0x93,0x6D,0x35,0x82,0x00,0x42,0x10,0x0A,0x88,0x0E,0x17,0xAA,0x9D,0xBE,
++    0x11,0xAA,0x85,0x06,0xA1,0x2B,0x37,0xDA,0x30,0x52,0x09,0x01,0x07,0x09,0xB8,0xF7,
++    0xE1,0x17,0x33,0x1A,0xB9,0x04,0x30,0x4A,0x00,0x11,0xD0,0x14,0xBD,0xF7,0xE7,0x8F,
++    0xC1,0x14,0x08,0xE9,0xCA,0x00,0x0A,0x48,0xC1,0x00,0x52,0x62,0xEE,0x03,0x08,0x83,
++    0x42,0x62,0x41,0x0B,0x3F,0x48,0xAA,0xE6,0x04,0x41,0x00,0x83,0x47,0x83,0x08,0xF9,
++    0x88,0x19,0x18,0x42,0x00,0x83,0x80,0x2D,0xEF,0x85,0xAF,0x85,0x84,0xBD,0x34,0x22,
++    0x37,0x6A,0xD0,0x7B,0xD0,0x43,0x85,0x6C,0x31,0x1A,0x9B,0xA1,0x9C,0xB4,0x08,0x29,
++    0x34,0x02,0x03,0x48,0xC6,0x20,0x0A,0x09,0x03,0x48,0x24,0x0A,0x8B,0xAC,0xC8,0x43,
++    0x02,0x00,0x92,0x05,0x80,0x2C,0x00,0x01,0x80,0x24,0x00,0x09,0x81,0x14,0x30,0x42,
++    0x80,0x01,0x86,0xA4,0xE3,0x03,0x5A,0x73,0x32,0x32,0x3C,0x10,0x58,0x43,0x1D,0x32,
++    0x50,0x01,0xD0,0x46,0x40,0xA2,0x18,0x32,0xB3,0x1C,0x30,0x82,0x10,0xD9,0x07,0x82,
++    0xD2,0xA4,0xA0,0x83,0x00,0x47,0x40,0x82,0x18,0x02,0x1E,0x32,0xB3,0x1C,0x30,0x82,
++    0x10,0x21,0x18,0x82,0xD2,0xA4,0xA0,0x83,0x35,0x01,0x18,0x73,0xD8,0x43,0x45,0x01,
++    0x80,0x36,0xD0,0x6C,0xC2,0x14,0xF0,0x90,0x00,0x82,0xD4,0x1C,0x18,0x82,0x80,0x1C,
++    0x34,0x52,0x91,0x01,0x92,0x9C,0xF0,0x83,0x80,0x8C,0x00,0x3F,0x00,0x01,0x00,0x42,
++    0xC7,0x87,0xF9,0xFF,0x18,0x00,0x04,0x42,0xAA,0xAA,0xAA,0xAA,0xC0,0x9C,0x10,0xC1,
++    0xB0,0x12,0x94,0x84,0xD0,0x9C,0x00,0x01,0x18,0x83,0x80,0x7C,0xD6,0x9C,0x10,0x83,
++    0x80,0x74,0x10,0x01,0x97,0x64,0x50,0xFA,0x90,0x5C,0x10,0x01,0x91,0x54,0x30,0x72,
++    0xB5,0x01,0x99,0x83,0xCA,0x43,0x45,0x00,0x85,0x4C,0x10,0xA1,0xFA,0x82,0x82,0x00,
++    0x85,0x44,0xE0,0x43,0x40,0x29,0xC0,0xCE,0x03,0x01,0x30,0x12,0x32,0x84,0x30,0x84,
++    0x30,0x22,0x04,0x87,0x10,0x01,0x00,0x47,0x41,0x44,0x80,0x03,0x40,0x44,0x80,0xC3,
++    0xE4,0xD8,0xE2,0x48,0xE2,0x20,0xE3,0x90,0x95,0x95,0x12,0xD2,0xDB,0xA6,0x37,0x02,
++    0xE2,0x00,0x92,0x05,0x30,0x22,0xC4,0x6C,0x2F,0x22,0xDC,0x5E,0xC0,0xB4,0x80,0x3C,
++    0xE0,0xAC,0x00,0x01,0x85,0x94,0x00,0xBF,0x00,0x01,0x80,0x34,0x30,0x32,0xCC,0x94,
++    0xC4,0x14,0x00,0x42,0xC8,0x1C,0x10,0x42,0x80,0x86,0x03,0x01,0x32,0x22,0x04,0xEF,
++    0xC1,0x3C,0x40,0x0C,0xC2,0x03,0xD0,0x00,0x91,0x05,0x00,0x04,0xCA,0x9C,0xE0,0x4B,
++    0x48,0x11,0x98,0xA6,0xCC,0x84,0x10,0x42,0xD5,0x8E,0xD8,0x8B,0xE5,0x48,0x9A,0x8B,
++    0xC8,0x64,0xC0,0x48,0x88,0x64,0xD8,0x5C,0x34,0x12,0x10,0x1A,0xD8,0x06,0xD0,0x5C,
++    0x90,0x5C,0xD8,0x54,0x34,0x12,0x10,0x1A,0xE0,0x06,0xD0,0x54,0x90,0x54,0xC8,0x2C,
++    0x10,0x42,0xD4,0x3E,0x32,0x8A,0xE3,0x48,0x94,0x4D,0x36,0x72,0xC8,0x34,0xC0,0x48,
++    0x90,0x4D,0x88,0x34,0xCC,0x4C,0x10,0x42,0xEB,0xBE,0xC8,0x4B,0x10,0x0A,0xE4,0x2E,
++    0xDD,0x94,0x58,0x53,0x0C,0x09,0x00,0xCA,0x1D,0x52,0x18,0x53,0xE0,0x8B,0x4B,0x09,
++    0x8C,0x0E,0x08,0x09,0xA0,0x8B,0xCB,0x8C,0x10,0x42,0xEC,0xBE,0x30,0x02,0x0B,0x09,
++    0x00,0x0A,0xC4,0x7C,0x18,0x0A,0x88,0x7C,0x00,0x87,0xC8,0x44,0x10,0x42,0xD4,0x6E,
++    0xE0,0x8B,0x4B,0x09,0x8C,0x0E,0x08,0x09,0xA0,0x8B,0xCB,0x84,0x10,0x42,0xD4,0x2E,
++    0x30,0x02,0x0B,0x09,0x00,0x0A,0xC4,0x74,0x18,0x0A,0x88,0x74,0xE0,0x20,0xC5,0x3C,
++    0xE0,0x00,0x82,0x3C,0x32,0x02,0xE3,0x00,0x94,0x05,0x32,0x22,0x2C,0xE2,0xDD,0xFE,
++    0x30,0x82,0x43,0x11,0xCB,0x2E,0x30,0x8A,0xC0,0x34,0x80,0x07,0xC8,0x6F,0x97,0x05,
++    0x00,0x07,0x00,0x01,0x03,0xC8,0xD3,0x20,0x11,0x01,0x00,0x57,0x00,0x67,0x41,0x01,
++    0xE8,0x7E,0x08,0x01,0xF0,0x0A,0xDB,0x2C,0x10,0xCA,0xD4,0xB6,0xE4,0x18,0x12,0xCA,
++    0xE8,0x16,0xD0,0x48,0x00,0x0C,0x01,0x87,0x48,0x01,0xE8,0x76,0x09,0x09,0x00,0x0C,
++    0x00,0x5F,0x08,0x01,0xF4,0x0A,0x13,0x0A,0xD0,0x16,0xD0,0x48,0x00,0x0C,0x01,0x27,
++    0x48,0x01,0xD0,0x16,0x0E,0x01,0x18,0x4A,0x00,0x0C,0x09,0x01,0xF0,0x0A,0xDB,0x44,
++    0x10,0xCA,0xD4,0x1E,0xCA,0x24,0xE0,0x48,0x90,0x4D,0x8E,0x24,0xE2,0x20,0xE5,0x90,
++    0x95,0x95,0x12,0xD2,0xD8,0x9E,0x06,0x5F,0x00,0x01,0x08,0x01,0x01,0x37,0x00,0x0C,
++    0xE0,0x20,0xD5,0x3C,0xE0,0x90,0x92,0x3C,0xE2,0x00,0x92,0x05,0x17,0xC2,0xDD,0xB6,
++    0xC2,0x94,0xE0,0x00,0x90,0x05,0x82,0x94,0xC8,0x6C,0xC0,0x94,0x10,0x42,0xD4,0x06,
++    0x39,0x17,0xCA,0x43,0x40,0x71,0xC9,0x0E,0x01,0x71,0x89,0x43,0xC9,0x24,0xC8,0x43,
++    0x42,0x48,0xC4,0x00,0x91,0x05,0x8E,0x43,0x40,0x81,0xCA,0x0E,0x01,0x81,0x8A,0x43,
++    0xC2,0x9C,0xE0,0x03,0x42,0x11,0x98,0x56,0xD8,0x83,0x45,0x11,0xCC,0x3E,0xF2,0x00,
++    0x90,0x05,0x86,0x04,0xC8,0x54,0xC0,0x5C,0xC0,0x08,0xC2,0x64,0xD0,0x00,0xCA,0x04,
++    0x84,0x07,0xC8,0x17,0x90,0x05,0x80,0x0C,0x05,0x01,0x28,0x44,0x08,0xE9,0x0B,0x48,
++    0x10,0x01,0xE0,0xAC,0x31,0x22,0x04,0x0F,0x18,0x01,0x00,0xCF,0x01,0x01,0xF0,0x02,
++    0xF5,0x84,0x10,0x82,0xD0,0x8E,0xF0,0x0C,0xD8,0x00,0xAC,0x06,0x10,0x02,0x92,0x05,
++    0x34,0x32,0x10,0x0A,0xE0,0x06,0x30,0x72,0x30,0x8A,0x31,0x32,0x10,0x12,0xDC,0x06,
++    0x31,0xB2,0x30,0x92,0x69,0x74,0xC5,0x80,0x2D,0x44,0xE5,0x20,0xE2,0xD8,0x92,0xDD,
++    0x17,0xDA,0xDD,0x1E,0x32,0x02,0xE3,0x00,0x94,0x05,0x32,0x22,0xDC,0x6C,0x28,0xE2,
++    0xDD,0xD6,0x6E,0x44,0xC2,0x48,0xD4,0x00,0x90,0x05,0xCC,0x04,0x82,0x07,0xC8,0x17,
++    0x28,0x44,0xC5,0x0C,0x40,0x01,0xD0,0x06,0x13,0x02,0x2A,0x44,0x00,0x17,0x00,0x01,
++    0x2D,0x44,0x2B,0x44,0xC8,0x9C,0xC0,0x7C,0x18,0x43,0xC8,0x9C,0xC6,0x74,0x10,0x43,
++    0x87,0xBD,0xE8,0x85,0xAC,0xBD,0x87,0x15,0x32,0x62,0x70,0x9A,0x29,0x01,0x80,0xAB,
++    0x09,0x11,0x30,0x02,0x80,0x01,0x35,0x3A,0xA9,0x0B,0x34,0x0A,0xD0,0x24,0xC0,0x14,
++    0xBD,0xFF,0xDF,0x67,0xAD,0xEB,0xDD,0x03,0x40,0x01,0x80,0x76,0x6F,0x5A,0x42,0x43,
++    0x91,0x3D,0x4C,0x04,0x00,0x43,0x07,0x09,0x81,0x83,0x31,0x0A,0xD0,0x24,0xC0,0x14,
++    0xBA,0xFF,0xE7,0xA7,0x01,0x01,0x80,0x83,0x00,0x7B,0xD7,0x24,0x90,0x04,0x08,0x01,
++    0x30,0x1A,0x31,0x42,0xD7,0x14,0xB8,0xF7,0xD5,0xE7,0xE5,0x03,0x40,0x41,0x96,0x0E,
++    0xE5,0x00,0xA2,0x03,0x30,0xBF,0x10,0x01,0x00,0x37,0x08,0x01,0xE4,0x48,0x92,0x4D,
++    0x4F,0xA1,0xC8,0xDE,0xE4,0x90,0x92,0x95,0x17,0x12,0xCC,0xB6,0x38,0x82,0x3B,0x18,
++    0x78,0xD8,0x10,0x09,0x06,0xD2,0x94,0x95,0x18,0xF9,0x0F,0xD8,0x01,0xC2,0x58,0xA2,
++    0xC0,0x00,0x4E,0x09,0x88,0x66,0x40,0x0B,0x18,0x8A,0x04,0x0B,0x44,0x0B,0x1A,0x8A,
++    0x04,0x0B,0x42,0x0B,0x1C,0x8A,0x04,0x0B,0x44,0x0B,0x1E,0x8A,0x03,0x0B,0x3E,0x82,
++    0x48,0x01,0x88,0x66,0x44,0x0B,0x1A,0x8A,0x04,0x0B,0x42,0x0B,0x1C,0x8A,0x04,0x0B,
++    0x44,0x0B,0x1E,0x8A,0x00,0x0B,0x46,0x0B,0x18,0x8A,0x00,0x0B,0x38,0x82,0x4B,0x11,
++    0x88,0x66,0x40,0x0B,0x18,0x8A,0x04,0x0B,0x44,0x0B,0x1A,0x8A,0x04,0x0B,0x42,0x0B,
++    0x1C,0x8A,0x04,0x0B,0x40,0x0B,0x1E,0x8A,0x03,0x0B,0x3E,0x82,0x4F,0x19,0x88,0xE6,
++    0x44,0x0B,0x18,0x8A,0x04,0x0B,0x40,0x0B,0x1C,0x8A,0x04,0x0B,0x44,0x0B,0x1E,0x8A,
++    0x02,0x0B,0x46,0x0B,0x1A,0x8A,0x00,0x0B,0x3F,0x82,0xAB,0x8D,0x80,0x3D,0xC4,0x3C,
++    0xC8,0x3C,0x48,0x00,0x02,0x00,0xC4,0x00,0x38,0x00,0x48,0x92,0x72,0x00,0xC2,0x28,
++    0x40,0x72,0x40,0x0B,0x90,0x4D,0x8C,0x34,0x5C,0x0B,0x90,0x4D,0x8A,0x2C,0x58,0x0B,
++    0x90,0x4D,0x8C,0x24,0x5C,0x0B,0x94,0x4D,0x8E,0x1C,0x50,0x0B,0x90,0x75,0x4C,0x52,
++    0x44,0x53,0x92,0x95,0x90,0x14,0x40,0x53,0x92,0xBD,0x44,0x13,0x90,0x95,0x94,0x0C,
++    0x58,0x12,0x00,0x5F,0xE7,0xC7,0xF8,0xFF,0x00,0xB0,0x00,0x01,0x00,0x01,0x00,0x42,
++    0x80,0x00,0x00,0x42,0x08,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0x98,0x01,0x52,0xD3,
++    0x90,0x95,0x94,0x04,0x10,0x09,0x00,0x13,0xA8,0x10,0x1C,0x13,0x12,0x81,0x18,0x13,
++    0x18,0x13,0x14,0x79,0x11,0x13,0x16,0x01,0x00,0x53,0x12,0x89,0x02,0x53,0x40,0x0B,
++    0x10,0x81,0x19,0x8A,0x07,0x0B,0x02,0xF9,0x80,0x89,0x17,0xC3,0x07,0x09,0xB8,0xFF,
++    0xFF,0x17,0x03,0xF9,0x80,0x89,0x14,0xC3,0x07,0x09,0xB8,0xFF,0xF8,0xE7,0x02,0x19,
++    0x11,0x00,0x00,0x43,0x07,0x09,0xB8,0xFF,0xF8,0xB7,0x0A,0x11,0xC7,0x3C,0xB8,0xFF,
++    0xF8,0xF7,0x22,0xA1,0x01,0x01,0x40,0x4B,0x30,0x48,0xA8,0x16,0xE7,0x20,0x93,0x25,
++    0x03,0x0F,0xF0,0x20,0x92,0x25,0xE7,0x00,0x90,0x05,0x46,0x51,0x98,0x9E,0x0F,0x09,
++    0xC7,0x3C,0xB8,0xFF,0xF8,0x67,0x42,0x6A,0xC8,0x34,0x00,0x0B,0xC8,0x2C,0x18,0x0B,
++    0xCA,0x24,0x18,0x0B,0xCC,0x1C,0x18,0x0B,0x10,0x33,0x4E,0x4A,0xD2,0x14,0x00,0x53,
++    0x00,0x7B,0xC8,0x0C,0x00,0x0B,0x4A,0x2A,0xC2,0x04,0x88,0x01,0x10,0x43,0x60,0xA1,
++    0xC8,0x16,0x00,0x09,0x87,0x45,0xE8,0x85,0x07,0x01,0x38,0xDF,0x00,0x01,0x00,0x42,
++    0x18,0x00,0x04,0x42,0x00,0x0F,0x00,0x26,0xF8,0x48,0x48,0x21,0x94,0xDE,0x3F,0x58,
++    0xA8,0x0E,0x00,0x14,0xE6,0x00,0x3C,0x48,0x80,0x06,0x80,0x13,0x38,0x82,0x4B,0x01,
++    0x86,0x5E,0x38,0x18,0x80,0x16,0x80,0x13,0xE2,0x00,0xF2,0x48,0x48,0x11,0x98,0x26,
++    0x38,0x18,0xAC,0x16,0x04,0x14,0xE0,0x00,0xF7,0x48,0x3C,0x1F,0x17,0x01,0x38,0x77,
++    0x16,0x01,0x38,0xFF,0x10,0x01,0x48,0x18,0x11,0x5A,0x9C,0x66,0x54,0x18,0x10,0x5A,
++    0x98,0x8E,0x18,0x01,0x32,0xE2,0x04,0x77,0x30,0x1A,0x18,0x5A,0xA0,0xE6,0x11,0x01,
++    0x44,0x18,0x12,0x5A,0x98,0x8E,0x49,0x18,0x10,0x5A,0x9C,0xE6,0x54,0x18,0x10,0x5A,
++    0x9C,0x0E,0x30,0xA2,0x06,0xFF,0x49,0x18,0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD6,0x00,
++    0x0C,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD4,0x00,0x0A,0x92,0x4A,0x18,
++    0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD2,0x00,0x08,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,
++    0x0E,0x58,0xD0,0x00,0x0E,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD6,0x00,
++    0x0C,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD4,0x00,0x0A,0x92,0x42,0x18,
++    0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD2,0x00,0x0A,0x92,0xD2,0x08,0x90,0x06,0x30,0x0A,
++    0x08,0x92,0x32,0x82,0x3A,0x82,0x03,0xEF,0x78,0x50,0x86,0x06,0x10,0x4A,0x82,0x18,
++    0x9A,0x06,0x10,0x02,0x00,0x9A,0x12,0x01,0x30,0xE2,0x4C,0x18,0x11,0x5A,0x9C,0x6E,
++    0x54,0x18,0x10,0x5A,0x9F,0x96,0x10,0xE1,0x08,0x48,0xD4,0x95,0x54,0x18,0x10,0x5A,
++    0x9C,0x66,0x08,0x48,0x8C,0x90,0x14,0x5A,0x9C,0x46,0x08,0x48,0x8C,0x90,0x14,0x5A,
++    0x9C,0x26,0x08,0x48,0x84,0xD6,0x89,0x90,0x04,0x07,0x48,0x48,0x4C,0x18,0x16,0x5A,
++    0x9E,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,0x4C,0x18,0x14,0x5A,0x9C,0x0E,0x08,0x58,
++    0xD2,0x00,0x0E,0x92,0x4C,0x18,0x12,0x5A,0x9A,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,
++    0x4C,0x18,0x10,0x5A,0x98,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,0x44,0x18,0x16,0x5A,
++    0x9E,0x0E,0x00,0x58,0xD2,0x00,0x0E,0x92,0x44,0x18,0x14,0x5A,0x9C,0x0E,0x00,0x58,
++    0xD2,0x00,0x0E,0x92,0x92,0xCE,0x46,0x18,0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD2,0x00,
++    0x0A,0x92,0xD2,0x08,0x90,0x06,0x30,0x0A,0x32,0x1A,0x0B,0x92,0x80,0xD8,0x32,0x82,
++    0x9A,0x0E,0x10,0x02,0x58,0x01,0xA8,0x06,0x13,0x4A,0x3A,0x82,0x32,0x1A,0x83,0xD8,
++    0x9A,0x06,0x10,0x02,0xA8,0x0D,0x00,0x01,0x36,0x02,0x36,0x02,0xEB,0x15,0x30,0xAA,
++    0x81,0x07,0xC0,0x17,0x30,0x72,0x05,0x28,0x32,0x4A,0x33,0x9A,0x46,0x00,0x06,0x00,
++    0x30,0x2A,0x84,0xC5,0xAF,0x05,0xB9,0xDF,0xEB,0xBF,0xE6,0x05,0x3A,0x01,0x40,0x48,
++    0x30,0xB2,0x35,0x01,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,
++    0x2E,0x06,0x2E,0x06,0xEA,0x01,0x02,0x48,0x33,0x6A,0x3C,0x82,0x36,0x22,0x30,0x02,
++    0x31,0x02,0x36,0x02,0xB8,0xD7,0xDF,0xFF,0x43,0x02,0x38,0x82,0x58,0x60,0x05,0x01,
++    0x40,0x12,0x48,0x1A,0xF3,0x5D,0x3D,0x82,0x00,0x68,0x00,0x00,0x00,0xC0,0x00,0x00,
++    0x00,0x30,0x01,0x10,0x39,0x82,0xA3,0x85,0x33,0xA2,0xF3,0x20,0xC3,0x2B,0xE1,0x20,
++    0x10,0x5A,0x95,0x06,0x33,0xEA,0xE8,0x1A,0x07,0xD8,0xC2,0x18,0xE0,0x85,0x39,0xC2,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x20,0x01,0x42,
++    0x80,0x20,0x01,0x42,0x80,0x20,0x01,0x42,0x80,0x20,0x01,0x42,0x80,0x20,0x03,0x42,
++    0x80,0xA0,0x00,0x42,0x80,0x20,0x03,0x42,0x80,0xA0,0x00,0x42,0x80,0x20,0x03,0x42,
++    0x80,0xA0,0x00,0x42,0x80,0x20,0x03,0x42,0x80,0xA0,0x00,0x42,0x80,0xA0,0x03,0x42,
++    0x80,0x20,0x00,0x42,0x80,0xA0,0x03,0x42,0x80,0xA0,0x03,0x42,0x80,0x20,0x04,0x42,
++    0x80,0x20,0x04,0x42,0x80,0x20,0x04,0x42,0x80,0xA0,0x04,0x42,0x10,0x20,0x08,0x40,
++    0x40,0x08,0x20,0x10,0x10,0x20,0x08,0x40,0x20,0x08,0x40,0x20,0x20,0x10,0x08,0x40,
++    0x08,0x81,0x03,0x42,0x08,0xC1,0x03,0x42,0x08,0x41,0x00,0x42,0x08,0x81,0x00,0x42,
++    0x08,0xC1,0x00,0x42,0x08,0x01,0x01,0x42,0x08,0x81,0x02,0x42,0x08,0x41,0x02,0x42,
++    0x08,0xC1,0x02,0x42,0x08,0x01,0x02,0x42,0x08,0x01,0x02,0x42,0x08,0xC1,0x01,0x42,
++    0x08,0x41,0x02,0x42,0x08,0x81,0x01,0x42,0x08,0x81,0x02,0x42,0x08,0x41,0x01,0x42,
++    0x08,0xC1,0x02,0x42,0x08,0x01,0x01,0x42,0x08,0x01,0x03,0x42,0x08,0x81,0x00,0x42,
++    0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x00,0x00,
++    0x00,0x08,0xF8,0x0F,0xFF,0x07,0xF8,0xFF,0x07,0xF8,0x0F,0xF8,0x08,0x00,0x08,0x08,
++    0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x28,0xB5,0x39,0xC5,0x08,0x1D,
++    0x1B,0x2B,0x3A,0x28,0x53,0xB5,0x0A,0xC5,0x00,0x08,0x01,0x00,0x01,0x00,0x50,0x0D,
++    0x52,0x1D,0x52,0xB5,0x39,0x0D,0x04,0x08,0x51,0x3D,0x53,0x1D,0x51,0x3D,0x54,0x95,
++    0x51,0x3D,0x54,0x95,0x51,0x3D,0x54,0x95,0x0B,0x3D,0x34,0x88,0x51,0x3D,0x54,0x1D,
++    0x51,0x3D,0x54,0x95,0x04,0x00,0x50,0x3D,0x50,0x1D,0x01,0x00,0x00,0x00,0x00,0x00,
++    0x54,0x2D,0x53,0x3D,0x32,0x8D,0x32,0x38,0x01,0x28,0x0A,0x45,0x50,0xB5,0x53,0x95,
++    0x00,0x00,0x00,0x00,0x52,0xA5,0x51,0xB5,0x09,0xC5,0x03,0x08,0x03,0x00,0x50,0x3D,
++    0x55,0x1D,0x51,0x0D,0x51,0x3D,0x54,0x95,0x51,0x3D,0x53,0x1D,0x51,0x3D,0x54,0x95,
++    0x51,0x0D,0x55,0x0D,0x54,0xB5,0x3A,0x0D,0x00,0x08,0x01,0x00,0x53,0xA5,0x51,0x2D,
++    0x52,0x3D,0x34,0x8A,0x1D,0x38,0x52,0x45,0x52,0x0D,0x51,0x1D,0x54,0xB5,0x3A,0x0D,
++    0x53,0xA5,0x29,0xB5,0x39,0xC5,0x08,0x1D,0x19,0x2D,0x22,0x1D,0x44,0x0D,0x31,0x3D,
++    0x23,0x95,0x09,0xC1,0x29,0xB5,0x0B,0x1D,0x1B,0x2B,0x3A,0x28,0x00,0x00,0x00,0x08,
++    0xFF,0x07,0x00,0xF8,0x08,0x00,0x10,0x10,0x08,0x10,0x10,0x10,0x08,0x08,0x10,0x08,
++    0x10,0x08,0x10,0x08,0x10,0x10,0x08,0x08,0x10,0x10,0x08,0x08,0x08,0x08,0x10,0x10,
++    0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x08,0xF8,0x07,
++    0x08,0x00,0x08,0x08,0xE8,0xA2,0x01,0x00,0x00,0x00,0x00,0x01,0x00,0xC0,0x00,0x00,
++    0x00,0x00,0x05,0x00,0xE8,0x62,0x02,0x00,0x00,0xC0,0x00,0x01,0x58,0xA0,0x07,0x00,
++    0x00,0xE0,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0x00,0x70,0x00,0x30,0x09,0x40,0x1B,0x00,0x06,0x78,0x50,0x56,
++    0xFF,0xFF,0xFF,0xFF,0x3C,0x50,0x00,0x10,0x00,0x20,0x18,0x00,0x1E,0xAC,0xE4,0x09,
++    0x0F,0x00,0xCA,0xCA,0xFF,0xFF,0xFF,0xFF,0x0A,0x07,0x82,0x00,0x04,0x00,0x00,0x03,
++    0x95,0x83,0xC1,0x3C,0xC8,0xB2,0xB5,0x47
++};
++
++
++
++#define FW_INFO_SIZE	(0x18)
++#define FW_REAL_SIZE	(sizeof(fwbin))
++#define FW_BIN_SIZE		(24*1024+24)	    //24K byte
++
++#endif
++
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update2/cst3xx.c b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update2/cst3xx.c
+new file mode 100644
+index 000000000..3120bafe3
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update2/cst3xx.c
+@@ -0,0 +1,1437 @@
++/*
++ * cst3xx Touchscreen Controller Driver
++ */
++
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/i2c.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of_gpio.h>
++#include <linux/pm_qos.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include <linux/input/cst3xx.h>
++#include <linux/input/hyn_cst3xx_RS659_fw.h>
++#include "../../video/jz_fb_v13/jz_fb.h"
++
++struct st1615_ts_finger {
++	u16 x;
++	u16 y;
++	u8 t;
++	bool is_valid;
++};
++
++struct cst3xx_ts_data {
++	struct i2c_client *client;
++	struct input_dev *input_dev;
++	struct cst3xx_platform_data *pdata;
++	struct work_struct  work;
++       struct delayed_work dwork;
++	struct workqueue_struct *workqueue;
++	int irq;
++};
++
++static int cst3xx_into_program_mode(struct i2c_client * client);
++static int cst3xx_erase_program_area(struct i2c_client * client);
++static void cst3xx_reset_ic(struct cst3xx_ts_data *ts,unsigned int ms);
++static int cst3xx_write_program_data(struct i2c_client * client,const unsigned char *pdata);
++
++static int cst3xx_check_checksum(struct i2c_client * client);
++
++static int cst3xx_exit_program_mode(struct i2c_client * client);
++
++static int cst3xx_update_firmware(struct cst3xx_ts_data *ts, const unsigned char *pdata);
++
++static int cst3xx_firmware_info(struct i2c_client * client);
++
++static int cst3xx_update_judge( unsigned char *pdata, int strict);
++
++static int cst3xx_boot_update_fw(struct cst3xx_ts_data *ts,  unsigned char *pdata);
++
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_test(struct i2c_client *client);
++static void cst3xx_reset(struct cst3xx_ts_data *ts) ;
++extern  void close_vcc3v3Power(void);
++extern  void open_vcc3v3Power(void);
++
++static unsigned char *pcst3xx_update_firmware = (unsigned char *)cst3_fw ; //the updating firmware
++static unsigned int   g_cst3xx_ic_version  = 0;
++static unsigned int   g_cst3xx_ic_checksum = 0;
++static unsigned int   g_cst3xx_ic_checkcode =0;
++static unsigned int   g_cst3xx_ic_project_id  = 0;
++static unsigned int   g_cst3xx_ic_type  = 0;
++
++static unsigned char  report_flag = 0;
++static unsigned int x_temp_pos = 0;
++static unsigned int y_temp_pos = 0;
++
++#define HYN_DRAW_POINT
++
++#define USE_ANALOG_I2C     1 //i2c analog
++//#define USE_HIGHEST_I2CA  1// x1000 highest i2c
++//#define USE_LOWEST_I2CA   1 // x1000 lowest i2c
++#define HYN_UPDATE_FIRMWARE_POWERON_ENABLE
++#define HYN_UPDATE_FIRMWARE_ENABLE
++
++#pragma pack(1)
++typedef struct
++{
++    u16 pid;                 //product id   //
++    u16 vid;                 //version id   //
++} st_tpd_info;
++#pragma pack()
++
++st_tpd_info tpd_info;
++
++#define CST3XX_BIN_SIZE    (24*1024 + 24)
++#define CST3XX_MAX_X  480
++#define CST3XX_MAX_Y  800
++#define ERROR_TOUCH   1
++
++static void cst3xx_ts_power(struct cst3xx_ts_data *ts, bool poweron)
++{
++	if (gpio_is_valid(ts->pdata->reset_gpio))
++		gpio_direction_output(ts->pdata->reset_gpio, poweron);
++}
++
++static int cst3xx_into_program_mode(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[4];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x01;
++	buf[2] = 0xAA;	//set cmd to enter program mode
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0)  return -1;
++
++	mdelay(2);
++
++	buf[0] = 0xA0;
++	buf[1] = 0x02;	//check whether into program mode
++	ret = cst3xx_i2c_read_register(client, buf, 1);
++	if (ret < 0)  return -1;
++
++	if (buf[0] != 0x55) return -1;
++
++	return 0;
++}
++static int cst3xx_erase_program_area(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[3];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x02;
++	buf[2] = 0x00;		//set cmd to erase main area
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0) return -1;
++
++	mdelay(5);
++
++	buf[0] = 0xA0;
++	buf[1] = 0x03;
++	ret = cst3xx_i2c_read_register(client, buf, 1);
++	if (ret < 0)  return -1;
++
++	if (buf[0] != 0x55) return -1;
++
++	return 0;
++}
++
++
++static void cst3xx_reset_ic(struct cst3xx_ts_data *ts,unsigned int ms)
++{
++
++	unsigned char buf[4];
++	buf[0] = 0xD1;
++	buf[1] = 0x0E;
++	cst3xx_i2c_write(ts->client, buf, 2);
++/*
++	gpio_direction_output(ts->pdata->reset_gpio,0);
++	mdelay(2);
++	gpio_direction_output(ts->pdata->reset_gpio,1);
++*/
++	mdelay(ms);
++}
++
++
++static int cst3xx_write_program_data(struct i2c_client * client,
++		const unsigned char *pdata)
++{
++	int i, ret;
++	unsigned char *i2c_buf;
++	unsigned short eep_addr;
++	int total_kbyte;
++
++	unsigned char temp_buf[8];
++	unsigned short iic_addr;
++	int  j;
++
++
++	i2c_buf = kmalloc(sizeof(unsigned char)*(1024 + 2), GFP_KERNEL);
++	if (i2c_buf == NULL)
++		return -1;
++
++	//make sure fwbin len is N*1K
++	//total_kbyte = len / 1024;
++	total_kbyte = 24;
++	for (i=0; i<total_kbyte; i++) {
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x14;
++		eep_addr = i << 10;		//i * 1024
++		i2c_buf[2] = eep_addr;
++		i2c_buf[3] = eep_addr>>8;
++		ret = cst3xx_i2c_write(client, i2c_buf, 4);
++		if (ret < 0)
++			goto error_out;
++
++		memcpy(i2c_buf, pdata + eep_addr, 1024);
++		for(j=0; j<256; j++) {
++			iic_addr = (j<<2);
++    	temp_buf[0] = (iic_addr+0xA018)>>8;
++    	temp_buf[1] = (iic_addr+0xA018)&0xFF;
++		temp_buf[2] = i2c_buf[iic_addr+0];
++		temp_buf[3] = i2c_buf[iic_addr+1];
++		temp_buf[4] = i2c_buf[iic_addr+2];
++		temp_buf[5] = i2c_buf[iic_addr+3];
++    	      ret = cst3xx_i2c_write(client, temp_buf, 6);
++    		if (ret < 0)
++    			goto error_out;
++		}
++
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x04;
++		i2c_buf[2] = 0xEE;
++		ret = cst3xx_i2c_write(client, i2c_buf, 3);
++		if (ret < 0)
++			goto error_out;
++
++		mdelay(60);
++
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x05;
++		ret = cst3xx_i2c_read_register(client, i2c_buf, 1);
++		if (ret < 0)
++			goto error_out;
++
++		if (i2c_buf[0] != 0x55)
++			goto error_out;
++
++	}
++
++	i2c_buf[0] = 0xA0;
++	i2c_buf[1] = 0x03;
++	i2c_buf[2] = 0x00;
++	ret = cst3xx_i2c_write(client, i2c_buf, 3);
++	if (ret < 0)
++		goto error_out;
++
++	mdelay(8);
++
++	if (i2c_buf != NULL) {
++		kfree(i2c_buf);
++		i2c_buf = NULL;
++	}
++
++	return 0;
++
++error_out:
++	if (i2c_buf != NULL) {
++		kfree(i2c_buf);
++		i2c_buf = NULL;
++	}
++	return -1;
++}
++
++
++static int cst3xx_check_checksum(struct i2c_client * client)
++{
++	int ret;
++	int i;
++	unsigned int  checksum;
++	unsigned int  bin_checksum;
++	unsigned char buf[4];
++	const unsigned char *pData;
++
++	for(i=0; i<5; i++)
++	{
++		buf[0] = 0xA0;
++		buf[1] = 0x00;
++		ret = cst3xx_i2c_read_register(client, buf, 1);
++		if(ret < 0)
++		{
++			mdelay(2);
++			continue;
++		}
++
++		if(buf[0]!=0)
++			break;
++		else
++		mdelay(2);
++	}
++    mdelay(2);
++
++
++    if(buf[0]==0x01)
++	{
++		buf[0] = 0xA0;
++		buf[1] = 0x08;
++		ret = cst3xx_i2c_read_register(client, buf, 4);
++
++		if(ret < 0)	return -1;
++
++		// read chip checksum
++		checksum = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24);
++
++        pData=(unsigned char  *)pcst3xx_update_firmware +24*1024+16;   //7*1024 +512
++		bin_checksum = pData[0] + (pData[1]<<8) + (pData[2]<<16) + (pData[3]<<24);
++
++        printk("  hyn the updated ic checksum is :0x%x. the updating firmware checksum is:0x%x------\n", checksum, bin_checksum);
++
++        if(checksum!=bin_checksum)
++		{
++			printk(" cst3xx hyn check sum error.\n");
++			return -1;
++
++		}
++
++	}
++	else
++	{
++		printk(" cst3xx hyn No checksum.\n");
++		return -1;
++	}
++	return 0;
++}
++
++static int cst3xx_exit_program_mode(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[3];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x06;
++	buf[2] = 0xEE;
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0)
++		return -1;
++
++	mdelay(10);	//wait for restart
++
++
++	return 0;
++}
++
++
++static int cst3xx_update_firmware(struct cst3xx_ts_data *ts, const unsigned char *pdata)
++{
++	int ret;
++	int retry = 0;
++
++	printk(" cst3xx----------upgrade cst3xx begain------------\n");
++	disable_irq(ts->irq);
++	mdelay(20);
++START_FLOW:
++
++#ifdef HYN_UPDATE_FIRMWARE_POWERON_ENABLE
++	close_vcc3v3Power();
++	mdelay(20);
++	open_vcc3v3Power();
++	mdelay(5+retry);
++#else
++	cst3xx_reset_ic(ts,5+retry);
++#endif
++	ret = cst3xx_into_program_mode(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]into program mode failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_erase_program_area(ts->client);
++	if (ret) {
++		printk(" cst3xx[cst3xx]erase main area failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_write_program_data(ts->client, pdata);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]write program data into cstxxx failed.\n");
++		goto err_out;
++	}
++
++    ret =cst3xx_check_checksum(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx] after write program cst3xx_check_checksum failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_exit_program_mode(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]exit program mode failed.\n");
++		goto err_out;
++	}
++
++	cst3xx_reset_ic(ts,20);
++
++	printk(" cst3xx hyn----------cst3xx_update_firmware  end------------\n");
++
++	enable_irq(ts->irq);
++
++	return 0;
++
++err_out:
++	if (retry < 30) {
++		retry++;
++		mdelay(20);
++		goto START_FLOW;
++	}
++	else {
++		enable_irq(ts->irq);
++		return -1;
++	}
++}
++
++
++
++
++/*******************************************************
++Function:
++    get firmware version, ic type...
++Input:
++    client: i2c client
++Output:
++    success: 0
++    fail:	-1
++*******************************************************/
++static int cst3xx_firmware_info(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[28];
++//	unsigned short ic_type, project_id;
++
++
++	buf[0] = 0xD1;
++	buf[1] = 0x01;
++	ret = cst3xx_i2c_write(client, buf, 2);
++	if (ret < 0) return -1;
++
++	mdelay(40);
++
++	buf[0] = 0xD1;
++	buf[1] = 0xFC;
++	ret = cst3xx_i2c_read_register(client, buf, 4);
++	if (ret < 0) return -1;
++
++	//0xCACA0000
++	g_cst3xx_ic_checkcode = buf[3];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[2];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[1];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[0];
++
++	printk("linc cst3xx [cst3xx] the chip g_cst3xx_ic_checkcode:0x%x.\r\n",g_cst3xx_ic_checkcode);
++	
++	mdelay(2);
++	
++	buf[0] = 0xD2;
++	buf[1] = 0x04;
++	ret = cst3xx_i2c_read_register(client, buf, 4);
++	if (ret < 0) return -1;
++	g_cst3xx_ic_type = buf[3];
++	g_cst3xx_ic_type <<= 8;
++	g_cst3xx_ic_type |= buf[2];
++
++	
++	g_cst3xx_ic_project_id = buf[1];
++	g_cst3xx_ic_project_id <<= 8;
++	g_cst3xx_ic_project_id |= buf[0];
++
++	printk("linc cst3xx [cst3xx] the chip ic g_cst3xx_ic_type :0x%x, g_cst3xx_ic_project_id:0x%x\r\n",
++		g_cst3xx_ic_type, g_cst3xx_ic_project_id);
++
++	mdelay(2);
++	
++	buf[0] = 0xD2;
++	buf[1] = 0x08;
++	ret = cst3xx_i2c_read_register(client, buf, 8);
++	if (ret < 0) return -1;	
++
++	g_cst3xx_ic_version = buf[3];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[2];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[1];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[0];
++
++	g_cst3xx_ic_checksum = buf[7];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[6];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[5];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[4];	
++
++	tpd_info.vid = g_cst3xx_ic_version;
++    tpd_info.pid = 0x00;
++
++
++	printk(" cst3xx [cst3xx] the chip ic version:0x%x, checksum:0x%x\r\n",
++		g_cst3xx_ic_version, g_cst3xx_ic_checksum);
++
++	if(g_cst3xx_ic_version==0xA5A5A5A5)
++	{
++		printk(" cst3xx [cst3xx] the chip ic don't have firmware. \n");
++		return -1;
++	}
++	if((g_cst3xx_ic_checkcode&0xffff0000)!=0xCACA0000){
++		printk("linc cst3xx [cst3xx] cst3xx_firmware_info read error .\r\n");
++		return -1;
++	}
++
++    buf[0] = 0xD1;
++	buf[1] = 0x09;
++	ret = cst3xx_i2c_write(client, buf, 2);
++	if (ret < 0) return -1;
++    mdelay(5);
++
++
++	return 0;
++}
++
++static int cst3xx_update_judge( unsigned char *pdata, int strict)
++{
++	unsigned short ic_type, project_id;
++	unsigned int fw_checksum, fw_version;
++	const unsigned int *p;
++	int i;
++	unsigned char *pBuf;
++
++	fw_checksum = 0x55;
++	p = (const unsigned int *)pdata;
++	for (i=0; i<(CST3XX_BIN_SIZE-4); i+=4) {
++		fw_checksum += (*p);
++		p++;
++	}
++
++	if (fw_checksum != (*p)) {
++		printk(" cst3xx[cst3xx]calculated checksum error:0x%x not equal 0x%x.\n", fw_checksum, *p);
++		return -1;	//bad fw, so do not update
++	}
++
++	pBuf = &pdata[CST3XX_BIN_SIZE-16];
++
++	project_id = pBuf[1];
++	project_id <<= 8;
++	project_id |= pBuf[0];
++
++	ic_type = pBuf[3];
++	ic_type <<= 8;
++	ic_type |= pBuf[2];
++
++	fw_version = pBuf[7];
++	fw_version <<= 8;
++	fw_version |= pBuf[6];
++	fw_version <<= 8;
++	fw_version |= pBuf[5];
++	fw_version <<= 8;
++	fw_version |= pBuf[4];
++
++	fw_checksum = pBuf[11];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[10];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[9];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[8];
++
++	printk(" cst3xx[cst3xx]the updating firmware:project_id:0x%04x,ic type:0x%04x,version:0x%x,checksum:0x%x\n",
++			project_id, ic_type, fw_version, fw_checksum);
++
++	if (strict > 0) {
++
++		if (g_cst3xx_ic_checksum != fw_checksum){
++			if (g_cst3xx_ic_version >fw_version){
++				printk("[cst3xx]fw version(0x%x), ic version(0x%x).\n",fw_version, g_cst3xx_ic_version);
++			//	return -1;
++			}
++		}else{
++			printk("[cst3xx]fw checksum(0x%x), ic checksum(0x%x).\n",fw_checksum, g_cst3xx_ic_checksum);
++			return -1;
++		}
++	}
++
++	return 0;
++}
++static int cst3xx_boot_update_fw(struct cst3xx_ts_data *ts,  unsigned char *pdata)
++{
++	int ret;
++	int retry = 0;
++	int flag = 0;
++
++	while (retry++ < 3) {
++		ret = cst3xx_firmware_info(ts->client);
++		if (ret == 0) {
++			flag = 1;
++			break;
++		}
++	}
++
++	if (flag == 1) {
++		ret = cst3xx_update_judge(pdata, 1);
++		if (ret < 0) {
++			printk(" cst3xx[cst3xx] no need to update firmware.\n");
++			return 0;
++		}
++	}
++
++	ret = cst3xx_update_firmware(ts, pdata);
++	if (ret < 0){
++		printk(" cst3xx [cst3xx] update firmware failed.\n");
++		return -1;
++	}
++
++    mdelay(50);
++
++	ret = cst3xx_firmware_info(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx [cst3xx] after update read version and checksum fail.\n");
++		return -1;
++	}
++
++	return 0;
++}
++static int hyn_boot_update_fw(struct i2c_client * ts)
++{
++	unsigned char *ptr_fw;
++	int ret;
++	ptr_fw = pcst3xx_update_firmware;
++	ret = cst3xx_boot_update_fw(ts, ptr_fw);
++	return ret;
++	
++}
++
++
++/*******************************Chose which I2C interface ********************************************/
++
++#if USE_ANALOG_I2C
++
++#define I2CSDA  GPIO_PC(27)
++#define I2CSCL   GPIO_PC(26)
++
++#define I2CSDA_HIGH gpio_direction_output(GPIO_PC(27),1)
++#define I2CSDA_LOW  gpio_direction_output(GPIO_PC(27),0)
++
++#define I2CSCL_HIGH  gpio_direction_output(GPIO_PC(26),1)
++#define I2CSCL_LOW  gpio_direction_output(GPIO_PC(26),0)
++
++#define delay_data 2
++static void iicstart(void)
++{
++     I2CSDA_HIGH;
++      I2CSCL_HIGH;
++      __udelay(2);
++      I2CSDA_LOW;
++      __udelay(2);
++       I2CSCL_LOW;
++       __udelay(2);
++}
++static void iicstop(void)
++{
++     I2CSDA_LOW;
++     I2CSCL_HIGH;
++     __udelay(2);
++     I2CSDA_HIGH;
++     __udelay(2);
++
++}
++static unsigned char waitack(void)
++{
++   u8 ucErrTime=0;
++
++    gpio_direction_input(GPIO_PC(27));
++   //  __udelay(2);
++
++  //  I2CSDA_HIGH;
++  //  __udelay(2);
++     I2CSCL_HIGH;
++     __udelay(2);
++
++    while(__gpio_get_value(GPIO_PC(27)))
++    {
++        ucErrTime++;
++     //   printk("time out ++ \n");
++        if(ucErrTime>250)
++         {
++                iicstop();
++                return 1;
++        }
++    }
++    I2CSCL_LOW;
++     __udelay(2);
++    return 0;
++}
++static void sendack(void)
++{
++     I2CSCL_LOW;
++     __udelay(delay_data);
++     I2CSDA_LOW;
++     __udelay(delay_data);
++
++     I2CSCL_HIGH;
++     __udelay(delay_data);
++     I2CSCL_LOW;
++     __udelay(delay_data);
++
++}
++static void sendnotack(void)
++{
++     I2CSCL_LOW;
++     __udelay(delay_data);
++    I2CSDA_HIGH;
++    __udelay(delay_data);
++
++    I2CSCL_HIGH;
++    __udelay(delay_data);
++    I2CSCL_LOW;
++    __udelay(delay_data);
++}
++static void iicsendbyte(unsigned char ch)
++{
++     unsigned char i;
++     I2CSCL_LOW;
++     for(i = 0;i<8;i++)
++     {
++          if(ch&0x80)
++          {
++              I2CSDA_HIGH;
++          }
++          else
++          {
++              I2CSDA_LOW;
++          }
++           __udelay(delay_data);
++          ch<<=1;
++          I2CSCL_HIGH;
++          __udelay(delay_data);
++               I2CSCL_LOW;
++          __udelay(delay_data);
++     }
++}
++static unsigned char iicreceivebyte(unsigned char ack)
++{
++    unsigned char i=8;
++    unsigned char ddata=0;
++
++    gpio_direction_input(GPIO_PC(27));
++    __udelay(delay_data);
++
++     for(i = 0;i<8;i++)
++     {
++         I2CSCL_LOW;
++         __udelay(delay_data);
++         I2CSCL_HIGH;
++         __udelay(delay_data);
++
++         ddata<<=1;
++         if(gpio_get_value(GPIO_PC(27))) ddata++;
++    }
++
++    if(!ack)
++        sendnotack();
++     else
++        sendack();
++
++    return ddata;
++}
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++    int count = len;
++     iicstart();
++     __udelay(delay_data);
++
++/*
++	 iicsendbyte( (0x1a<<1) | 0);
++     __udelay(delay_data);
++
++     if(waitack())
++     {
++        iicstop();
++                printk(" cst3xx_i2c_read wait ack timeoue \n");
++        return 1;
++     }
++
++     iicsendbyte(buf[0]);
++     __udelay(delay_data);
++     waitack();
++     __udelay(delay_data);
++*/
++     iicstart();
++     __udelay(delay_data);
++
++     iicsendbyte((0x1a << 1 ) | 1);
++     __udelay(delay_data);
++     if(waitack())
++     {
++        iicstop();
++                printk(" cst3xx_i2c_read wait ack timeoue \n");
++        return 1;
++     }
++     __udelay(delay_data);
++
++    while(count)
++    {
++         if(count == 1) *buf = iicreceivebyte(0);
++         else *buf = iicreceivebyte(1);
++         count --;
++         buf++;
++    }
++     iicstop();
++     __udelay(delay_data);
++     return 0;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++     int count = len;
++      iicstart();
++   //   __udelay(delay_data);
++
++      iicsendbyte((0x1A << 1) | 0);
++//      __udelay(delay_data);
++
++     if(waitack())
++     {
++        iicstop();
++        printk(" cst3xx_i2c_write send address wait ack timeoue \n");
++        return 1;
++     }
++
++      while(count--)
++      {
++            iicsendbyte(*(buf++));
++            __udelay(delay_data);
++             if(waitack())
++             {
++                iicstop();
++               printk(" cst3xx_i2c_write wait ack timeoue \n");
++                return 1;
++             }
++            __udelay(delay_data);
++      }
++
++      iicstop();
++      __udelay(delay_data);
++
++	return 0;
++}
++
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	int ret = -1;
++
++    ret = cst3xx_i2c_write(client, buf, 2);
++    if(ret) printk("failed to write cst3xx\n");
++
++    ret = cst3xx_i2c_read(client, buf, len);
++    if(ret) printk("failed to write cst3xx\n");
++    return ret;
++}
++
++#elif  USE_LOWEST_I2CA
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++	int ret = -1;
++	int retries = 0;
++
++	while (retries < 2) {
++		ret = i2c_master_recv(client, buf, len);
++		if(ret<=0)
++		    retries++;
++        else
++            break;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++	int ret = -1;
++	int retries = 0;
++
++	while (retries < 2) {
++		ret = i2c_master_send(client, buf, len);
++		if(ret<=0)
++		    retries++;
++        else
++            break;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	int ret = -1;
++
++    ret = cst3xx_i2c_write(client, buf, 2);
++
++    ret = cst3xx_i2c_read(client, buf, len);
++
++    return ret;
++}
++
++#elif USE_HIGHEST_I2CA
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++	struct i2c_msg msg;
++	int ret = -1;
++	int retries = 0;
++
++	msg.flags |= I2C_M_RD;
++	msg.addr   = client->addr;
++	msg.len    = len;
++	msg.buf    = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == 1)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++/*******************************************************
++Function:
++    read data from register.
++Input:
++    buf: first two byte is register addr, then read data store into buf
++    len: length of data that to read
++Output:
++    success: number of messages
++    fail:	negative errno
++*******************************************************/
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	struct i2c_msg msgs[2];
++	int ret = -1;
++	int retries = 0;
++
++	msgs[0].flags = 0;
++	msgs[0].addr  = client->addr;
++	msgs[0].len   = 2;
++	msgs[0].buf   = buf;
++
++	msgs[1].flags |= I2C_M_RD;
++	msgs[1].addr   = client->addr;
++	msgs[1].len    = len;
++	msgs[1].buf    = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, msgs, 2);
++		if(ret == 2)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++	struct i2c_msg msg;
++	int ret = -1;
++	int retries = 0;
++
++	msg.flags = 0;
++	msg.addr  = client->addr;
++	msg.len   = len;
++	msg.buf   = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == 1)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++#else
++#endif
++/*********************************i2c end********************************/
++
++
++static int cst3xx_i2c_test(struct i2c_client *client)
++{
++	int retry = 0;
++	int ret;
++	unsigned char buf[4];
++
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	while (retry++ < 5) {
++		ret = cst3xx_i2c_write(client, buf, 2);
++		if (ret == 0)
++			return ret;
++
++		mdelay(2);
++	}
++
++    if(retry==5) printk(" cst3xx hyn I2C TEST error.ret:%d;\n", ret);
++
++	return ret;
++}
++
++
++static void cst3xx_reset(struct cst3xx_ts_data *ts) {
++	if(gpio_is_valid(ts->pdata->reset_gpio)) {
++		gpio_direction_output(ts->pdata->reset_gpio,0);
++		mdelay(100);
++		gpio_direction_output(ts->pdata->reset_gpio,1);
++		mdelay(100);
++	}
++}
++/****************************  basic communication end*******************************/
++
++
++static void cst3xx_touch_report(struct cst3xx_ts_data *ts)
++{
++	unsigned char buf[30];
++	unsigned char i2c_buf[8];
++	unsigned char key_status, key_id = 0, finger_id, sw;
++	unsigned int  input_x = 0;
++	unsigned int  input_y = 0;
++	unsigned int  input_w = 0;
++	unsigned int input_x_delta = 0;
++	unsigned int input_y_delta = 0;
++       unsigned char cnt_up, cnt_down;
++	int   i, ret, idx;
++	int cnt, i2c_len;
++
++	int  len_1, len_2;
++
++      key_status = 0;
++
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	ret = cst3xx_i2c_read_register(ts->client, buf, 7);
++	if(ret < 0) {
++		printk("  iic read touch point data failed.\n");
++		goto OUT_PROCESS;
++	}
++  //   printk(" read buf : buf[0]: %x ,buf[1]: %x ,buf[2]: %x, buf[3]: %x,buf[4]: %x ,buf[5]: %x ,buf[6]: %x, buf[7]: %x,\n",buf[0],buf[1],buf[2],buf[3],buf[4],buf[5],buf[6],buf[7]);
++
++	if(buf[6] != 0xAB) {
++		printk(KERN_INFO " data is not valid..\r\n");
++		goto OUT_PROCESS;
++	}
++
++    	cnt = buf[5] & 0x7F;
++	if(cnt > 1) goto OUT_PROCESS;
++	else if(cnt==0)     goto CLR_POINT;
++
++	if(cnt == 0x01) {
++		goto FINGER_PROCESS;
++	}
++
++FINGER_PROCESS:
++
++    /*
++     *  sw: buf[0] low 4 bit
++     *  x pos:  buf[1] low 4 bit | buf[3] high 4 bit
++     *  y pos:  buf[2] low 4 bit | buf[3] low  4 bit
++     *  z press : buf[4]
++     *  finger_id:buf[0] high 4 bit
++     */
++	i2c_buf[0] = 0xD0;
++	i2c_buf[1] = 0x00;
++	i2c_buf[2] = 0xAB;
++
++	ret = cst3xx_i2c_write(ts->client, i2c_buf, 3);
++	if(ret < 0) {
++		printk(" cst3xx hyn send read touch info ending failed.\r\n");
++		cst3xx_reset_ic(ts,20);
++              goto END;
++	}
++
++	idx = 0;
++       cnt_up = 0;
++       cnt_down = 0;
++	input_x = (unsigned int)((buf[idx + 1] << 4) | ((buf[idx + 3] >> 4) & 0x0F));
++	input_y = (unsigned int)((buf[idx + 2] << 4) | (buf[idx + 3] & 0x0F));
++	input_w = (unsigned int)(buf[idx + 4]);
++	sw = (buf[idx] & 0x0F) >> 1;
++	finger_id = (buf[idx] >> 4) & 0x0F;
++
++    printk(" no handle : cst3xxPoint x:%d, y:%d, w:%d, id:%d, sw:%d. \n", input_x, input_y, input_w,finger_id, sw);
++
++	input_x=input_x*CST3XX_MAX_X/268;
++//	input_y=input_y*CST3XX_MAX_Y/800;
++	
++//	if(input_x >= CST3XX_MAX_X) input_x = CST3XX_MAX_X;
++//	if(input_y >= CST3XX_MAX_Y) input_y = CST3XX_MAX_Y;
++
++//	input_x = CST3XX_MAX_X-input_x;
++//	input_y = CST3XX_MAX_Y-input_y;
++
++#ifdef 0//HYN_DRAW_POINT
++	if(input_x > 300){
++		input_x_delta = input_x - (CST3XX_MAX_X/2);
++		input_x = input_x + input_x_delta/((CST3XX_MAX_X/2)/20);
++		if(input_x > CST3XX_MAX_X) input_x = CST3XX_MAX_X;
++		}
++	if(input_x < 40){
++		input_x_delta = (CST3XX_MAX_X/2) - input_x;
++		input_x = input_x - input_x_delta/((CST3XX_MAX_X/2)/12);
++		if(input_x < 0) input_x = 0;
++		}
++	if(input_y > 760){
++		input_y_delta = input_y - (CST3XX_MAX_Y/2);
++		input_y = input_y + input_y_delta/((CST3XX_MAX_Y/2)/12);
++		if(input_y > CST3XX_MAX_Y) input_y = CST3XX_MAX_Y;
++		}
++	if(input_y < 40){
++		input_y_delta = (CST3XX_MAX_Y/2) - input_y;
++		input_y = input_y - input_y_delta/((CST3XX_MAX_Y/2)/25);
++		if(input_y < 0) input_y = 0;
++		}
++#endif
++
++    printk(" handle : cst3xxPoint x:%d, y:%d, w:%d, id:%d, sw:%d. \n\n", input_x, input_y, input_w,finger_id, sw);
++
++	if (sw == 0x03 ) {
++         	   if((input_x > x_temp_pos + ERROR_TOUCH) || (input_x < x_temp_pos -ERROR_TOUCH)  || (input_y > y_temp_pos + ERROR_TOUCH) || (input_y < y_temp_pos -ERROR_TOUCH))
++               {
++          //           printk(" REPORT TOUCH DOWM Handle \n");
++                     x_temp_pos = input_x;
++                     y_temp_pos = input_y;
++                     input_report_key(ts->input_dev, BTN_TOUCH, 1);
++    		        input_report_abs(ts->input_dev, ABS_X, input_x);
++    	               input_report_abs(ts->input_dev, ABS_Y, input_y);
++    		        input_report_abs(ts->input_dev, ABS_PRESSURE, 1);
++    		        input_sync(ts->input_dev);
++                 }
++                cnt_down++;
++       }
++      else if(sw == 0) {
++                cnt_up++;
++        }
++
++        if((cnt_up>0) && (cnt_down==0) ){
++      //      printk(" REPORT TOUCH UP Handle \n");
++            x_temp_pos = 0;
++            y_temp_pos = 0;
++            input_report_key(ts->input_dev, BTN_TOUCH, 0);
++            input_report_abs(ts->input_dev, ABS_PRESSURE, 0);
++            input_mt_sync(ts->input_dev);
++        }
++       input_sync(ts->input_dev);
++	goto END;
++CLR_POINT:
++
++	    input_report_key(ts->input_dev, BTN_TOUCH, 0);
++           input_mt_sync(ts->input_dev);
++           input_sync(ts->input_dev);
++
++OUT_PROCESS:
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	buf[2] = 0xAB;
++	ret = cst3xx_i2c_write(ts->client, buf, 3);
++	if (ret < 0) {
++		printk("  send read touch info ending failed.\n");
++		cst3xx_reset_ic(ts,20);
++	}
++END:
++	return;
++}
++
++
++/******************************* irq handle  begin************************************/
++static void cst3xx_work_handler(struct work_struct *work)
++{
++	struct cst3xx_ts_data *cst3xx_ts = container_of(work, struct cst3xx_ts_data, work);
++	int ret = 0;
++    /******************here handle touch *******************/
++    //    printk(KERN_INFO "-----------enter cst3xx_work_handler------------\n");
++         cst3xx_touch_report(cst3xx_ts);
++	  enable_irq(cst3xx_ts->irq);
++}
++
++static irqreturn_t cst3xx_ts_irq_handler(int irq, void *dev_id)
++{
++	struct cst3xx_ts_data *ts = dev_id;
++
++   //    printk( KERN_INFO "-----------enter cst3xx_ts_irq_handler------------\n");
++
++	disable_irq_nosync(ts->irq);//use in interrupt,disable_irq will make dead lock.
++
++	if (!work_pending(&ts->work)) {
++		queue_work(ts->workqueue, &ts->work);
++	//    queue_delayed_work(ts->workqueue,&ts->dwork,1);//10ms * x
++	} else {
++		enable_irq(ts->irq);
++	}
++
++	return IRQ_HANDLED;
++}
++/******************************* irq handle  end************************************/
++
++static int cst3xx_ts_probe(struct i2c_client *client,
++					const struct i2c_device_id *id)
++{
++       printk( KERN_INFO "Enter cst3xx_ts_probe -------------------\n");
++
++       int ret;
++	   int rc=-1;
++	struct cst3xx_ts_data *ts;
++
++	struct cst3xx_platform_data *pdata = (struct cst3xx_platform_data*)client->dev.platform_data;
++	struct input_dev *input_dev;
++	int error;
++
++#if USE_ANALOG_I2C
++        if (gpio_is_valid(I2CSDA))
++        {
++            gpio_free(I2CSDA);
++            ret = gpio_request(GPIO_PC(27),"I2C1-SDA");
++            if(ret < 0){
++                printk("I2C1-SDA gpio request failed\n");
++                return ret;
++            }
++        }
++         if (gpio_is_valid(I2CSCL))
++        {
++            gpio_free(I2CSCL);
++            ret = gpio_request(GPIO_PC(26),"I2C1-SCL");
++            if(ret < 0){
++                printk("I2C1-SCL gpio request failed\n");
++                return ret;
++            }
++         }
++#endif
++
++      ts = devm_kzalloc(&client->dev, sizeof(*ts), GFP_KERNEL);
++	if (!ts)
++		return -ENOMEM;
++      input_dev = input_allocate_device();
++      if(!input_dev)
++            return -ENOMEM;
++
++      ts->pdata = pdata;
++      ts->client = client;
++      ts->input_dev = input_dev;
++
++	if(client->addr != 0x1A) //check address
++	{
++		client->addr = 0x1A;
++		printk("Crystal_shen:i2c_client_HYN->addr=%d.\n",client->addr);
++
++	}
++
++	if (gpio_is_valid(ts->pdata->int_gpio)) {
++		//error = gpio_request(pdata->int_gpio,"cst3xx gpio irq");
++        	error = gpio_request_one(pdata->int_gpio, GPIOF_IN, "cst3xx gpio irq");
++		if (error < 0) {
++			dev_err(&client->dev, "Failed to request GPIO %d, error %d\n",
++				pdata->int_gpio, error);
++			return error;
++		}
++
++	/*	if (error < 0) {
++			dev_err(&client->dev, "%s:failed to set gpio irq.\n",__func__);
++			return error;
++		}*/
++		ts->irq = gpio_to_irq(pdata->int_gpio);
++             printk(" cst3xx ts -> irq = %d.\n",ts->irq);
++	}
++
++	if (gpio_is_valid(ts->pdata->reset_gpio)) {
++		error = devm_gpio_request(&client->dev, ts->pdata->reset_gpio, NULL);
++		if (error) {
++			dev_err(&client->dev,
++				"Unable to request GPIO pin %d.\n",
++				ts->pdata->reset_gpio);
++				return error;
++		}
++	}
++       cst3xx_reset(ts);
++       printk( KERN_INFO "cst3xx reset -------------------\n");
++       ret =  cst3xx_i2c_test(ts->client);
++       if(ret<0){
++
++          mdelay(100);
++
++          printk( KERN_INFO "cst3xx test OK -------------------\n");
++#ifdef HYN_UPDATE_FIRMWARE_ENABLE
++	        ret = cst3xx_boot_update_fw(ts,pcst3xx_update_firmware);//
++			if(ret < 0){
++			printk(" cst3xx hyn_boot_update_fw failed.\n");
++			return -1;
++			}
++#endif
++
++       }else{
++       	  
++          mdelay(20);
++		  rc = hyn_boot_update_fw(ts);
++		  if(rc < 0){
++			printk(" cst3xx hyn_boot_update_fw failed.\n");
++			//return -1;
++		}
++       }
++
++	input_dev->name = "cst3xxx -touchscreen";
++	input_dev->id.bustype = BUS_I2C;
++	input_dev->dev.parent = &client->dev;
++
++	set_bit(EV_KEY, input_dev->evbit);
++	set_bit(EV_ABS, input_dev->evbit);
++	set_bit(EV_SYN, input_dev->evbit);
++	set_bit(BTN_TOUCH, input_dev->keybit);
++
++    set_bit(ABS_X, input_dev->absbit);
++	set_bit(ABS_Y, input_dev->absbit);
++    set_bit(ABS_PRESSURE, input_dev->absbit);
++
++
++	input_set_abs_params(input_dev, ABS_X, ts->pdata->x_min, ts->pdata->x_max, 0, 0);
++	input_set_abs_params(input_dev, ABS_Y, ts->pdata->y_min, ts->pdata->y_max, 0, 0);
++    input_set_abs_params(input_dev, ABS_PRESSURE, 0, 1, 0 , 0);
++
++  /*     input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR, 0, MAX_AREA, 0, 0);
++       input_set_abs_params(input_dev, ABS_MT_WIDTH_MAJOR, 0, MAX_AREA, 0, 0);
++       input_set_abs_params(input_dev, ABS_MT_POSITION_X, ts->pdata->x_min, ts->pdata->x_max, 0, 0);
++	input_set_abs_params(input_dev, ABS_MT_POSITION_Y, ts->pdata->y_min, ts->pdata->y_max, 0, 0);
++*/
++       error = input_register_device(input_dev);
++	if (error) {
++		dev_err(&client->dev, "Unable to register %s input device\n",
++			input_dev->name);
++		return error;
++	}
++
++  //    INIT_DELAYED_WORK(&ts->dwork, cst3xx_work_handler);
++
++	INIT_WORK(&ts->work, cst3xx_work_handler);
++	ts->workqueue = create_singlethread_workqueue("cst3xx_wq");
++
++	error = devm_request_threaded_irq(&client->dev, client->irq,
++					  NULL,
++					  cst3xx_ts_irq_handler,
++					  IRQF_ONESHOT,
++					  client->name, ts);
++	if (error) {
++		dev_err(&client->dev, "Failed to register interrupt\n");
++		return error;
++	}
++  	error = request_irq(ts->irq,
++				cst3xx_ts_irq_handler,
++				ts->pdata->irqflags,
++				client->dev.driver->name,
++				ts);
++	if (error < 0) {
++		dev_err(&client->dev, "%s: request irq failed\n",__func__);
++		return error;
++	}
++     printk(KERN_INFO "-----------CST3XX probe end ------------\n");
++       return 0;
++}
++
++static int cst3xx_ts_remove(struct i2c_client *client)
++{
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++        free_irq(ts->irq,ts);
++        devm_free_irq(&ts->client->dev, ts->client->irq,ts);
++        destroy_workqueue(ts->workqueue);
++        input_unregister_device(ts->input_dev);
++        devm_gpio_free(&ts->client->dev, ts->pdata->reset_gpio);
++        gpio_free(ts->pdata->int_gpio);
++
++#if USE_ANALOG_I2C
++         gpio_free(I2CSDA);
++        gpio_free(I2CSCL);
++#endif
++
++	return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int cst3xx_ts_suspend(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++
++	if (device_may_wakeup(&client->dev)) {
++		enable_irq_wake(client->irq);
++	} else {
++		disable_irq(client->irq);
++		cst3xx_ts_power(ts, false);//reset
++	}
++
++	return 0;
++}
++
++static int cst3xx_ts_resume(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++
++	if (device_may_wakeup(&client->dev)) {
++		disable_irq_wake(client->irq);
++	} else {
++		cst3xx_ts_power(ts, true);
++		enable_irq(client->irq);
++	}
++	return 0;
++}
++
++#endif
++
++static SIMPLE_DEV_PM_OPS(cst3xx_ts_pm_ops,
++			 cst3xx_ts_suspend, cst3xx_ts_resume);
++
++static const struct i2c_device_id cst3xx_ts_id[] = {
++	{ CST3XX_NAME, 0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, cst3xx_ts_id);
++
++
++#ifdef CONFIG_OF
++static const struct of_device_id cst3xx_ts_dt_ids[] = {
++	{ .compatible = "xxxxx,cst3xx", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, cst3xx_ts_dt_ids);
++#endif
++
++
++static struct i2c_driver cst3xx_ts_driver = {
++	.probe		= cst3xx_ts_probe,
++	.remove		= cst3xx_ts_remove,
++	.id_table	= cst3xx_ts_id,
++	.driver = {
++		.name	= CST3XX_NAME,
++		.owner	= THIS_MODULE,
++		.of_match_table = of_match_ptr(cst3xx_ts_dt_ids),
++		.pm	= &cst3xx_ts_pm_ops,
++	},
++};
++
++module_i2c_driver(cst3xx_ts_driver);
++
++
++MODULE_AUTHOR("Tiben");
++MODULE_DESCRIPTION("SITRONIX CST3XX Touchscreen Controller Driver");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update2/cst3xx.h b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update2/cst3xx.h
+new file mode 100644
+index 000000000..68791e6af
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update2/cst3xx.h
+@@ -0,0 +1,29 @@
++#ifndef TOUCHSCREEN_CST3XX__H
++#define TOUCHSCREEN_CST3XX__H
++
++
++/* -- dirver configure -- */
++#define CFG_MAX_TOUCH_POINTS	1
++#define MAX_AREA	0xff
++
++#define CST3XX_NAME 	"cst3xx"
++
++/*register address*/
++#define CST3XX_ADDRESS 	0x1A
++
++
++/* The platform data for the Focaltech ft5x0x touchscreen driver */
++struct cst3xx_platform_data {
++	unsigned int x_min;
++	unsigned int y_min;
++	unsigned int x_max;
++	unsigned int y_max;
++	unsigned long irqflags;
++	unsigned int int_gpio;
++	unsigned int reset_gpio;
++};
++
++
++
++#endif
++
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update2/hyn_cst3xx_RS659_fw.h b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update2/hyn_cst3xx_RS659_fw.h
+new file mode 100644
+index 000000000..24cfbcfed
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/cst3xx_MCU_driver_0729_update2/hyn_cst3xx_RS659_fw.h
+@@ -0,0 +1,1552 @@
++
++#ifndef __CST3xx_FW_H__
++#define __CST3xx_FW_H__
++
++  unsigned char cst3_fw[] ={
++    0x98,0xE0,0x07,0x01,0xC8,0x28,0x02,0x00,0x00,0x00,0x00,0x00,0xC8,0xE8,0x01,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x90,0x08,0x07,0x00,0x98,0x08,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x98,0xA8,0x00,0x00,0x00,0x00,0x00,0x00,0x98,0x78,0x01,0x00,0x80,0x07,0xC0,0x17,
++    0x82,0x07,0xC0,0x07,0x01,0x65,0x40,0x86,0xC1,0x41,0xC0,0x20,0xC5,0x68,0x31,0x12,
++    0xF5,0x38,0x33,0x5A,0x32,0xA2,0x32,0xEA,0x10,0x62,0x8D,0x0E,0x81,0x07,0xC0,0x97,
++    0x30,0xF2,0xF3,0x79,0x65,0x7E,0x30,0xB2,0x31,0x09,0x10,0x9A,0x87,0x06,0xD0,0xD8,
++    0x35,0x12,0x35,0x5A,0x18,0x9A,0x39,0xC2,0x70,0x82,0x02,0x00,0x70,0x82,0x03,0x00,
++    0xD0,0x81,0x98,0x16,0x43,0xC6,0x0B,0xC6,0xC2,0xD6,0x3F,0x90,0x99,0x0E,0x40,0x86,
++    0x08,0x86,0xA9,0x0E,0x40,0x23,0x00,0x63,0x38,0x82,0x03,0x00,0x18,0x01,0x20,0x01,
++    0x28,0x01,0x30,0x01,0xD0,0x81,0x98,0x0E,0x0F,0xC6,0xC3,0xDE,0x38,0x90,0x9A,0x06,
++    0x08,0x86,0xA9,0x06,0x03,0x5B,0x38,0x82,0xAE,0xFD,0x30,0x02,0x30,0x02,0xEE,0xFD,
++    0xA8,0x85,0xE8,0x85,0x84,0x27,0xE8,0xBF,0x37,0x8A,0xB8,0xFF,0xF8,0xAF,0x87,0x0F,
++    0xD0,0xFF,0x80,0x27,0xEF,0x7F,0xBD,0xFF,0xF8,0x9F,0x87,0x27,0xE8,0xAF,0x05,0x00,
++    0xAF,0x85,0x6F,0xFA,0x39,0x01,0xC0,0x43,0x37,0x4A,0xC9,0x01,0x38,0x30,0x32,0x42,
++    0x86,0x01,0xC5,0x1B,0xCE,0x23,0xF0,0x53,0xC0,0x01,0x74,0x01,0xDD,0x16,0xC0,0x6B,
++    0x48,0x68,0x87,0x3E,0xAA,0x7B,0xAC,0x3B,0x10,0xD2,0x8C,0x16,0xB0,0x63,0x06,0x09,
++    0xB7,0x43,0xEC,0x85,0x34,0x6A,0xE8,0x4B,0xE6,0x48,0x92,0x4D,0xAF,0x4B,0x4D,0xF9,
++    0x8D,0x0E,0x10,0x12,0x82,0x16,0xE8,0x0B,0x48,0x09,0x88,0x1E,0xB5,0x5B,0xAF,0x7B,
++    0xAF,0x3B,0xEA,0x85,0x4F,0x09,0x8C,0xE6,0x0A,0x09,0xA8,0x0B,0xE8,0x85,0xAF,0x85,
++    0x67,0x3A,0xE7,0x01,0x00,0x0F,0x80,0x0F,0xF5,0x1F,0xF0,0x03,0x47,0x01,0x80,0xD6,
++    0xEF,0x85,0xA8,0xC5,0x00,0x21,0x80,0x0F,0xE8,0x6F,0x07,0x09,0x87,0x0F,0xE8,0x57,
++    0x79,0x02,0x47,0xC3,0x0C,0x01,0x19,0x42,0x00,0xC3,0x01,0x11,0x86,0x0F,0xE8,0xBF,
++    0x61,0xEA,0x56,0x03,0x29,0x41,0x18,0x42,0x17,0x03,0x49,0x03,0x1F,0x42,0x09,0x03,
++    0x15,0x2B,0x4B,0x03,0x1D,0x42,0x09,0x03,0x4D,0x03,0x1B,0x42,0x0B,0x03,0x4B,0x03,
++    0x35,0x21,0x18,0x82,0x0B,0x03,0x4B,0x03,0x42,0x00,0x02,0x00,0x09,0x03,0x4B,0x03,
++    0x19,0x42,0x09,0x03,0x49,0x03,0x19,0x82,0x09,0x03,0x49,0x03,0x08,0x09,0x18,0x42,
++    0x0F,0x03,0x41,0x03,0x1F,0x42,0x05,0x03,0x45,0x03,0x1F,0x82,0x07,0x03,0x47,0x03,
++    0x1F,0x42,0x04,0x03,0x45,0x03,0x1D,0x42,0x05,0x03,0x45,0x03,0x1D,0x82,0x05,0x03,
++    0x45,0x03,0x1B,0x42,0x03,0x03,0x43,0x03,0x1B,0x82,0x05,0x03,0x44,0x03,0x1D,0x42,
++    0x03,0x03,0x45,0x03,0x1B,0x42,0x04,0x03,0x0E,0x81,0x42,0x02,0x82,0x27,0xE0,0x97,
++    0x85,0x0F,0xE8,0x87,0x85,0x0F,0xE8,0x67,0x85,0x0F,0xE8,0x97,0x48,0xE2,0x05,0x01,
++    0x1D,0x43,0x4C,0x03,0x1D,0x42,0x0D,0x03,0x10,0x2B,0x03,0x11,0x84,0x0F,0xE8,0x97,
++    0x41,0xC3,0x09,0x01,0x19,0x42,0x00,0xC3,0x00,0x21,0x80,0x0F,0xE8,0x07,0x04,0x09,
++    0x83,0x0F,0xE8,0xEF,0x42,0x03,0x41,0x00,0x01,0x00,0x02,0x03,0x40,0x03,0x0F,0x09,
++    0x1F,0x42,0x00,0x03,0x4C,0x03,0x1B,0x42,0x09,0x03,0x4B,0x03,0x19,0x42,0x0C,0x03,
++    0x41,0x03,0x1D,0x42,0x05,0x03,0x45,0x03,0x1D,0x82,0x01,0x03,0x41,0x03,0x1B,0x42,
++    0x03,0x03,0x43,0x03,0x1B,0x82,0x01,0x03,0x48,0x0B,0x03,0x61,0x1B,0x0A,0x08,0x0B,
++    0x48,0x0B,0x19,0x0A,0x0F,0x0B,0x41,0x0B,0x1F,0x0A,0x00,0x0B,0x48,0xE2,0x04,0x09,
++    0xC8,0x01,0xAF,0x43,0x82,0x0F,0xD0,0xD7,0xEC,0xC5,0x47,0xCA,0xC6,0x01,0xF3,0x0B,
++    0x42,0xCA,0x84,0x01,0x48,0x01,0x80,0x3E,0x4A,0xD2,0x04,0x0B,0x0C,0xF9,0x57,0xB2,
++    0x8C,0x89,0x97,0x01,0x10,0x8B,0x00,0x17,0x48,0xB2,0xCC,0xE1,0x07,0x0B,0x12,0xF9,
++    0x96,0xA1,0x02,0x13,0x08,0x31,0x08,0x0B,0x0C,0x11,0x08,0x0B,0x0A,0x51,0x08,0x0B,
++    0x0C,0x49,0x18,0x0B,0x18,0x0B,0x0A,0x01,0x1C,0x0B,0x40,0x4A,0xC2,0x01,0x0F,0x14,
++    0x3F,0x82,0xAB,0x85,0x70,0x62,0x0C,0x01,0x2C,0x01,0x60,0x62,0x50,0x62,0x04,0x01,
++    0xA4,0x82,0x02,0x40,0x50,0x5A,0xC4,0x40,0xC4,0x00,0x54,0x5A,0xC0,0x10,0x1C,0x01,
++    0xC6,0x83,0x01,0x38,0xC1,0x83,0xD0,0xC0,0x94,0x05,0x14,0x2A,0x90,0x06,0x30,0x2A,
++    0x10,0x22,0xCC,0x06,0x32,0x22,0xE0,0x90,0xE6,0xD8,0x92,0xDD,0x5F,0x29,0x98,0x8E,
++    0x59,0xFA,0xDB,0x40,0xA3,0xC2,0xE2,0xB0,0xE6,0x48,0x92,0x4D,0x4E,0x71,0x98,0xDE,
++    0x48,0xD2,0x03,0x01,0xE4,0xD2,0x10,0x52,0x90,0x06,0x30,0x8A,0xE6,0x00,0x92,0x05,
++    0x47,0x71,0x98,0xBE,0x50,0xCA,0x03,0x01,0x00,0x84,0xE0,0xE2,0x43,0xAC,0xD0,0x20,
++    0xC8,0x20,0x03,0xA4,0xE6,0x00,0x92,0x05,0x47,0x71,0x98,0xB6,0x47,0x84,0x40,0xF9,
++    0xCF,0x0E,0x00,0xF9,0x03,0x84,0x48,0x92,0x40,0x84,0x80,0x43,0xE8,0x85,0xAF,0x85,
++    0x40,0x1A,0xC3,0x03,0x38,0x00,0x86,0xAE,0x00,0x01,0x85,0x0F,0xD3,0x7F,0x60,0x02,
++    0x01,0x01,0xE0,0x01,0x8F,0x03,0xB9,0xFF,0xF9,0x47,0x34,0x0A,0x56,0x4A,0xCB,0x01,
++    0x40,0x22,0x83,0x1F,0xD0,0x3F,0x04,0x11,0x88,0x03,0x01,0x01,0x86,0x0F,0xC8,0xB7,
++    0xBC,0xFF,0xFF,0xFF,0xE8,0x85,0xA8,0x85,0x41,0xAA,0xC2,0x01,0xC8,0x03,0x42,0x01,
++    0x8A,0x36,0x40,0x9A,0xC0,0x01,0xEF,0x03,0x40,0x29,0xC8,0x0E,0xBE,0xFF,0xF7,0x7F,
++    0x61,0x7A,0xC2,0x03,0x38,0x00,0xA8,0x0E,0xBE,0xFF,0xF7,0x9F,0xC3,0x03,0xC3,0x03,
++    0x08,0xE9,0x07,0x42,0x82,0x03,0x43,0xC2,0xC0,0x03,0x40,0x01,0x80,0x16,0x80,0x0F,
++    0xE7,0x3F,0x3E,0xE7,0xE8,0x85,0xA8,0x85,0x48,0x32,0x02,0x01,0x02,0x43,0x4C,0x22,
++    0xCC,0x01,0xB7,0x43,0xF0,0x43,0x86,0x0F,0xC8,0x8F,0xEE,0x85,0xA8,0x85,0x33,0x2A,
++    0x48,0x01,0x80,0x4E,0x68,0x01,0x80,0x1E,0x30,0x82,0xC0,0x51,0x20,0x01,0x00,0x5F,
++    0x30,0x82,0x80,0x51,0x20,0x01,0x00,0x3F,0x68,0x01,0x80,0x1E,0xF0,0x80,0x24,0x49,
++    0x18,0x22,0x07,0x0F,0xE0,0x80,0x24,0x51,0x0A,0x01,0xF0,0x0A,0x48,0x01,0xD0,0x06,
++    0x16,0x4A,0x0A,0x40,0x0A,0x01,0xF0,0x8A,0x82,0x27,0xD8,0x57,0x40,0xF9,0xEB,0x06,
++    0x00,0xF9,0x6B,0x01,0x87,0x16,0x08,0xF9,0x88,0x09,0xD0,0x40,0xCB,0x00,0xE8,0x85,
++    0xAC,0x85,0x87,0x3D,0x28,0x01,0x20,0x01,0x01,0x51,0x48,0x92,0x1A,0x42,0xC3,0x00,
++    0x80,0x34,0xC0,0x34,0x01,0x08,0x13,0x39,0xC4,0x00,0x0A,0x90,0xC0,0x10,0x04,0xE1,
++    0x90,0x2C,0xF0,0x82,0x80,0x24,0x30,0x01,0x38,0x01,0x10,0x01,0x90,0x1C,0x90,0x14,
++    0x60,0x01,0x80,0x46,0xF0,0x10,0xDB,0x34,0x04,0x90,0xC2,0xD0,0x1C,0x39,0x09,0xD8,
++    0xC0,0x90,0x36,0xE1,0xF8,0xB2,0x6C,0x01,0x83,0x56,0xF0,0x50,0x1A,0x51,0x18,0xD2,
++    0x5E,0x02,0xC1,0x90,0x1A,0x39,0xC1,0x90,0x0E,0xD8,0xC4,0x90,0x3E,0xE1,0xF8,0xBA,
++    0x60,0x21,0x80,0x4E,0xE0,0x18,0xD3,0x34,0x06,0xD8,0xC2,0x90,0x1C,0x39,0x09,0xD8,
++    0xC0,0x90,0x1E,0xE1,0xF0,0x9A,0x9E,0x1C,0x68,0x69,0x80,0x5E,0xE0,0x50,0x1B,0x51,
++    0x18,0xD2,0x5A,0xA2,0xC2,0x90,0xC6,0x88,0x14,0x39,0x09,0x90,0xC0,0x50,0x0C,0xE1,
++    0xF0,0x8A,0x8A,0x14,0x08,0x09,0x88,0x0C,0x70,0x41,0xD1,0x3E,0x78,0x41,0xD1,0x2E,
++    0xC9,0x1C,0x48,0x41,0xD0,0x16,0xC8,0x14,0x49,0x41,0xD9,0x06,0x08,0x01,0x00,0xEF,
++    0x00,0xE0,0x07,0x01,0x10,0x00,0x00,0x42,0xF8,0x00,0x06,0x42,0x80,0x30,0x02,0x01,
++    0x18,0x00,0x02,0x42,0x80,0x60,0x05,0x00,0x70,0x00,0x04,0x01,0xF8,0xFF,0x07,0x00,
++    0x80,0x50,0x06,0x01,0x08,0x40,0x00,0x01,0x60,0x20,0x02,0x00,0x00,0x60,0x00,0x01,
++    0x00,0x28,0x00,0x01,0x80,0xC0,0x04,0x01,0x00,0x20,0x00,0x01,0x88,0x0C,0x08,0x19,
++    0x86,0x27,0xD0,0x37,0x10,0x82,0xED,0x3E,0x10,0xC2,0xED,0x2E,0xCC,0x1C,0x10,0x42,
++    0xE8,0x16,0xC8,0x14,0x10,0x42,0xE4,0x0E,0x00,0x01,0x80,0x0C,0xC0,0x0C,0x40,0x01,
++    0x80,0x86,0xC8,0x24,0xD6,0x2C,0x78,0x40,0xC2,0x00,0x82,0x00,0xD0,0x48,0x90,0x4D,
++    0x1F,0x8C,0x54,0xFA,0x58,0xFA,0xC7,0x93,0xC0,0xDB,0x18,0xD2,0x80,0x16,0xD0,0x40,
++    0xCC,0x2C,0x18,0x44,0xE7,0x20,0x93,0x25,0x60,0x29,0x90,0x06,0x3B,0x4F,0xE3,0x68,
++    0x90,0x6D,0x6F,0x71,0x92,0x06,0x38,0xF7,0x87,0x3D,0xE8,0x85,0xA8,0xC5,0x2F,0x01,
++    0x40,0xAA,0xFF,0x03,0x81,0x04,0x00,0x5F,0x07,0x31,0x48,0xA2,0x1A,0x42,0xC3,0x00,
++    0x0C,0xC9,0x09,0x48,0xC0,0x30,0x3A,0x11,0xF8,0xBA,0x07,0x21,0xF0,0x82,0x41,0x51,
++    0xD0,0x0E,0x20,0x51,0x00,0x0F,0xC0,0x51,0x96,0x25,0x00,0x19,0x04,0x00,0x14,0x22,
++    0xE8,0x06,0x30,0x22,0x37,0x02,0xC1,0xF9,0xC0,0x89,0x0C,0xF1,0x1F,0x42,0x0A,0xF9,
++    0x88,0x89,0x84,0x27,0xD0,0xAF,0xCB,0x00,0x90,0x05,0x40,0x51,0xD0,0x06,0x00,0x51,
++    0x4C,0x1A,0x17,0x42,0xE8,0x06,0x30,0x42,0x05,0xBC,0x03,0x84,0xE7,0x68,0x93,0x6D,
++    0xC5,0x04,0x10,0x42,0xC7,0x86,0xEE,0xC5,0xAC,0x85,0x87,0x3D,0x00,0xF9,0x87,0x0C,
++    0x00,0x01,0x80,0x04,0x81,0x14,0x18,0x39,0x09,0xD8,0x24,0x39,0x57,0xBA,0x1E,0x22,
++    0x04,0x08,0xC2,0x48,0xC0,0x68,0x0E,0xE1,0xF2,0x4A,0xE3,0x00,0x92,0x05,0x40,0x31,
++    0xD8,0xB6,0x07,0x01,0x80,0x24,0x00,0x01,0x38,0x01,0x28,0x01,0x30,0xF9,0xCF,0x24,
++    0x12,0x51,0x18,0x8A,0x54,0x6A,0xC6,0x48,0x54,0x72,0xC6,0x50,0x90,0x34,0x08,0x01,
++    0x20,0x01,0xF8,0xA2,0x60,0xA1,0xE8,0x0E,0xE1,0xF8,0x93,0xFD,0xC0,0x00,0x91,0x05,
++    0x10,0x62,0xED,0x06,0x35,0x2A,0x11,0xA2,0xD1,0x06,0x30,0x32,0xE2,0x90,0xE4,0x48,
++    0x90,0x4D,0x4E,0x29,0x99,0x66,0x6F,0xE1,0xED,0x16,0x50,0xFA,0x0C,0x01,0xA8,0x8B,
++    0x08,0x29,0x80,0x27,0xD0,0x2F,0x91,0x0D,0xD0,0x40,0x83,0x71,0x40,0xE1,0xC0,0x6E,
++    0xD0,0x80,0x83,0x71,0x40,0xE1,0xC0,0x4E,0x68,0xE1,0xE9,0x3E,0x78,0x21,0xE8,0x2E,
++    0x50,0xA2,0x05,0x01,0x85,0x83,0x40,0x92,0x10,0xD1,0x87,0x13,0xC4,0x14,0x10,0x42,
++    0xD0,0x06,0x88,0x14,0xC5,0x0C,0x10,0x82,0xE8,0x06,0xB0,0x0C,0xC5,0x04,0x10,0x42,
++    0xD0,0x06,0xA8,0x04,0x6D,0x6A,0x75,0x7A,0xC0,0x34,0x18,0x01,0x48,0x01,0xE8,0xBE,
++    0x14,0x01,0xF0,0x12,0x10,0x52,0xDC,0x76,0x61,0x2A,0xC5,0x23,0x60,0x01,0x80,0x16,
++    0xD0,0x90,0x02,0x14,0x01,0xC7,0x50,0xE1,0xD6,0xB6,0x78,0x60,0xC3,0x20,0x83,0x20,
++    0xD8,0x90,0x00,0x14,0x00,0x87,0x50,0x01,0xE8,0x76,0x10,0x09,0x00,0x14,0x00,0x5F,
++    0x14,0x01,0xF0,0x12,0x10,0x52,0xE4,0x16,0xD0,0x90,0x02,0x14,0x00,0x27,0x50,0x01,
++    0xD0,0x16,0x10,0x01,0x18,0x92,0x06,0x14,0xE2,0x00,0xE4,0xD8,0x90,0xDD,0x5E,0x29,
++    0x98,0xA6,0xC6,0x24,0xE6,0x00,0x92,0x05,0x80,0x24,0xC0,0x24,0x44,0x71,0x98,0x16,
++    0x20,0x01,0x00,0x01,0x08,0x01,0x10,0x01,0x94,0x1C,0x50,0x82,0x04,0x18,0xC3,0xD0,
++    0x5E,0x82,0xC4,0xA8,0x30,0x72,0x19,0x01,0x15,0x01,0xF0,0x52,0xC0,0x80,0x90,0x05,
++    0xE0,0x48,0x92,0x4D,0xFD,0x1C,0x10,0xD2,0xE8,0x06,0x90,0x1C,0xAA,0x51,0xE0,0xD8,
++    0x90,0xDD,0x5E,0x71,0x98,0x86,0x87,0x27,0xC8,0x9F,0x95,0x2D,0xC5,0x14,0x10,0x42,
++    0xD0,0x06,0xA8,0x14,0x00,0x01,0x80,0x24,0x68,0x01,0xE8,0xDE,0x3F,0x01,0xF8,0xBA,
++    0x10,0x7A,0xDD,0x96,0x60,0x01,0x80,0x0E,0x60,0x21,0x88,0x16,0xD9,0xC0,0x03,0x84,
++    0x00,0xB7,0x08,0x19,0xC0,0x1C,0x80,0x27,0xCD,0xDF,0x14,0x42,0xD7,0x86,0x78,0x40,
++    0xCA,0x00,0x82,0x00,0xD1,0xC0,0x01,0x84,0x00,0x57,0x78,0x01,0xE8,0x46,0x00,0x09,
++    0x00,0x84,0x01,0x2F,0x01,0x01,0xF0,0x82,0x10,0x42,0xE5,0x0E,0xD9,0x00,0x02,0x84,
++    0xB0,0x51,0xC0,0x24,0xE6,0x00,0x92,0x05,0x80,0x24,0xC0,0x24,0x46,0x71,0x98,0x9E,
++    0xE7,0x20,0x93,0x25,0x65,0x29,0x98,0x66,0x43,0x2A,0x4B,0x32,0xC0,0x03,0xC0,0x4B,
++    0x33,0x22,0x58,0x4A,0x50,0x4A,0x1B,0x62,0x88,0xB6,0x01,0x01,0x4A,0x1A,0x03,0x20,
++    0xC3,0x08,0x63,0x22,0xCB,0x60,0x68,0x1A,0xAA,0x51,0xC8,0x68,0x31,0xF9,0x0C,0xB0,
++    0xC8,0x78,0x34,0x01,0xF8,0xF2,0x3D,0x01,0xFD,0x7A,0x17,0xF2,0xD0,0x3E,0x28,0x01,
++    0xF8,0x2A,0x6B,0xA1,0xE8,0x1E,0x78,0x79,0xEB,0x0E,0x00,0x68,0x02,0x2C,0x61,0xD2,
++    0xA0,0x51,0xC8,0x60,0xC4,0x70,0xC6,0x68,0x0B,0x01,0xF0,0x4A,0x2B,0x01,0xF8,0xAA,
++    0x10,0x4A,0xD5,0x66,0x0B,0x01,0xF0,0x0A,0x48,0xA1,0xE8,0x46,0x68,0x79,0xE8,0x36,
++    0x7B,0x70,0xC6,0xA8,0x83,0x68,0x03,0x70,0xCB,0x68,0xC5,0x48,0x02,0x0C,0xE1,0x00,
++    0x90,0x05,0x46,0x29,0x9C,0x56,0x36,0xFF,0x47,0x01,0x80,0xE6,0x22,0x01,0x40,0x3A,
++    0x00,0x08,0xC3,0x68,0x41,0x3A,0xC2,0x70,0x40,0x32,0x82,0x51,0xC4,0x40,0x09,0xF9,
++    0x0B,0x48,0xC0,0x78,0x10,0x01,0x08,0x01,0xF2,0xD2,0xF5,0x0A,0x10,0x52,0xD4,0x6E,
++    0x01,0x01,0xF0,0x82,0x81,0x2C,0x40,0x41,0xE8,0x46,0x48,0x79,0xEC,0x36,0x00,0x00,
++    0x08,0x29,0x80,0x27,0xC8,0xEF,0xC8,0x2C,0xC1,0x00,0x02,0x84,0x40,0xD2,0x81,0x51,
++    0xC1,0x40,0x49,0xD2,0xC0,0x48,0x1B,0x01,0x17,0x01,0xF0,0xDA,0xF4,0x52,0x14,0x9A,
++    0xD0,0x3E,0x08,0x01,0xF1,0x0A,0x4A,0x41,0xE8,0x1E,0x50,0x79,0xEA,0x0E,0x00,0x48,
++    0x03,0x0C,0xE0,0x20,0x90,0x25,0x67,0x29,0x9B,0x4E,0x36,0x2F,0xA9,0xC5,0x47,0x52,
++    0x17,0x09,0x80,0x01,0xC0,0x0B,0x18,0x8A,0x81,0x0B,0x68,0x3A,0x79,0x22,0x31,0x62,
++    0xA4,0x01,0x06,0x27,0xBB,0xFF,0xEF,0xFF,0x48,0x4A,0x41,0x43,0xE0,0x00,0x02,0x43,
++    0x40,0x42,0xC1,0x03,0x40,0x01,0x80,0x0E,0x05,0xC1,0xB0,0x43,0x40,0xF2,0x80,0x1F,
++    0xE9,0xE7,0x50,0x2A,0x48,0xEA,0x40,0xE2,0x86,0x1F,0xC8,0x3F,0xB9,0xFF,0xEF,0x7F,
++    0x01,0x11,0x88,0x03,0x50,0x02,0x49,0xC2,0x40,0xC2,0x80,0x1F,0xD8,0x37,0x55,0xF2,
++    0x48,0xAA,0x40,0xB2,0x85,0x1F,0xF8,0xE7,0xC8,0x03,0x43,0x01,0x83,0x16,0xC8,0x03,
++    0x40,0x11,0x88,0x26,0x48,0xCA,0x40,0x43,0x10,0x09,0x18,0x82,0x00,0x43,0x48,0x72,
++    0x40,0x72,0x80,0x1F,0xF0,0x47,0x73,0x5A,0xC1,0xCB,0xC1,0x83,0x18,0x42,0x80,0x0E,
++    0x05,0x01,0xA8,0x43,0xBA,0xFF,0xF7,0xC7,0x41,0x8A,0xC0,0x8B,0x09,0x0C,0xC6,0xCB,
++    0x11,0x0C,0xC8,0x4B,0x10,0x0C,0x72,0x22,0xB5,0x01,0xE2,0x8B,0x10,0x0C,0x04,0xCF,
++    0x00,0x48,0x00,0x01,0x00,0x40,0x00,0x01,0x00,0xE0,0x00,0x01,0x08,0x40,0x00,0x01,
++    0x18,0x10,0x00,0x00,0x48,0xE0,0x06,0x00,0x50,0xA0,0x02,0x00,0x50,0x50,0x02,0x00,
++    0x00,0xA0,0x00,0x01,0x00,0x20,0x00,0x01,0x80,0xC0,0x04,0x01,0xF8,0x00,0x06,0x42,
++    0x70,0x40,0x04,0x01,0x48,0xA2,0x40,0x4C,0x10,0x0C,0x4E,0xA2,0x40,0x4B,0x18,0x0C,
++    0xA2,0x48,0x18,0x0C,0xEC,0x4B,0x1D,0x0C,0xBA,0xFF,0xEF,0x57,0x05,0x11,0xA0,0x83,
++    0x32,0x8A,0xC9,0x01,0x40,0x72,0x80,0x1F,0xE9,0x9F,0x31,0x8A,0x12,0x09,0xC8,0x01,
++    0x40,0x5A,0x58,0x62,0x80,0x17,0xE8,0xD7,0xBC,0xFF,0xDF,0x97,0x32,0x8A,0xC9,0x01,
++    0x40,0x3A,0x80,0x0F,0xF0,0xDF,0x82,0x07,0xDF,0x0F,0xBA,0xFF,0xE3,0xE7,0xCE,0x03,
++    0x40,0x31,0x80,0x06,0x3F,0xB7,0xEB,0xC5,0x00,0x60,0x00,0x01,0x00,0xA0,0x00,0x01,
++    0x08,0x40,0x00,0x01,0x30,0x48,0x00,0x00,0xA8,0x85,0x33,0x22,0xF0,0x03,0x87,0x07,
++    0xF2,0x2F,0x46,0x7A,0x2C,0x01,0x00,0x2B,0xB6,0x2B,0x05,0x21,0xAF,0x2A,0xB8,0xFF,
++    0xE5,0xE7,0xA1,0x01,0xCA,0x03,0x33,0x08,0x42,0x52,0x72,0x48,0x1C,0x0B,0x5C,0x0B,
++    0x02,0x48,0x1A,0x0B,0x0B,0x2B,0xCE,0x0B,0x30,0x48,0xA8,0x16,0x0E,0x09,0x04,0x0B,
++    0x1B,0x2B,0xE8,0x85,0xAD,0x85,0x87,0xAD,0x42,0x12,0xC2,0x01,0x42,0x0B,0x40,0x48,
++    0x00,0x48,0x02,0x0B,0x52,0x02,0x4A,0x0A,0x40,0x0A,0x82,0x0F,0xCA,0xB7,0x40,0x0A,
++    0x71,0xFA,0xC1,0x80,0x81,0xA4,0x41,0xEA,0xB6,0xE1,0x81,0x01,0x83,0x9C,0x01,0x47,
++    0x47,0xD2,0xB9,0xFF,0xF9,0x4F,0x66,0xCA,0x52,0x03,0x83,0x01,0xE7,0x03,0x40,0x79,
++    0x81,0x06,0x31,0x12,0x48,0xB2,0x01,0x01,0x58,0x9A,0x81,0x07,0xF9,0x5F,0x36,0x12,
++    0x48,0x9A,0x01,0x09,0x58,0x82,0x81,0x07,0xFB,0x2F,0x56,0x03,0x80,0x01,0xE2,0x03,
++    0x40,0x59,0x8D,0x7E,0xC1,0xA4,0x31,0x8A,0x13,0x01,0xD8,0x1B,0xDB,0x2B,0x19,0x5A,
++    0x40,0x6C,0x40,0x3C,0xD8,0x68,0x07,0x2C,0xE4,0x00,0xE4,0x48,0xE4,0x90,0x92,0x95,
++    0x17,0xD2,0x9C,0xAE,0x52,0x03,0x83,0x01,0xE5,0x03,0x40,0x59,0x81,0x2E,0x50,0x12,
++    0x49,0x12,0x41,0x1A,0x58,0x0D,0x80,0x0F,0xC1,0x07,0xEC,0xA4,0x30,0xA2,0x39,0x01,
++    0x01,0x01,0xF0,0x42,0x0A,0x99,0x18,0x42,0x08,0x51,0x80,0x1F,0xF9,0x8F,0x07,0x44,
++    0x01,0x01,0xF0,0x02,0x0A,0x99,0x18,0x42,0x08,0x51,0x80,0x1F,0xF9,0x4F,0x07,0x04,
++    0xE5,0x68,0xE5,0x20,0xE7,0xF8,0x93,0xFD,0x7F,0x29,0x98,0x4E,0x68,0xB2,0x60,0xA2,
++    0xA0,0xF1,0x3D,0x01,0x01,0x01,0xF0,0x42,0x08,0x51,0x08,0x00,0x86,0x1F,0xF8,0xC7,
++    0x00,0x44,0x01,0x01,0xF0,0x02,0x09,0x51,0x08,0x00,0x80,0x1F,0xF9,0x8F,0x06,0x04,
++    0xE5,0x68,0xE5,0x20,0xE7,0xF8,0x93,0xFD,0x7F,0x29,0x98,0x5E,0x40,0x0D,0x80,0x07,
++    0xD9,0xDF,0xC1,0x9C,0xC8,0x03,0x42,0x31,0x81,0x96,0x84,0xAD,0xE8,0x85,0x07,0x00,
++    0x10,0x00,0x00,0x42,0x00,0x01,0x00,0x42,0x80,0xC0,0x04,0x01,0x00,0xE0,0x00,0x01,
++    0x08,0x40,0x00,0x01,0x48,0xE0,0x06,0x00,0x58,0x30,0x03,0x01,0x48,0xFA,0xFF,0x53,
++    0x84,0x13,0xF8,0x53,0x80,0x13,0x32,0x52,0x96,0x01,0xCE,0x93,0x80,0x13,0xCC,0x4B,
++    0x83,0x0B,0x3E,0x82,0xA8,0xC5,0xF7,0x34,0x37,0x22,0x40,0xC2,0xFD,0x03,0x16,0x02,
++    0xC9,0xFE,0x01,0x21,0x6B,0xB2,0x1F,0x02,0xCB,0x28,0x02,0x99,0x09,0x00,0xC2,0x40,
++    0x2A,0xA1,0xF8,0x2A,0x3E,0xB1,0xF8,0x3A,0x48,0x09,0x88,0x1E,0x0F,0xF9,0x8F,0x09,
++    0xD8,0x48,0x92,0x6D,0x50,0x09,0x88,0x1E,0x0A,0xC9,0x08,0x48,0xD8,0x48,0x96,0x7D,
++    0xCE,0x0B,0xCC,0x13,0x0A,0x48,0x00,0x90,0x18,0x8A,0x80,0xCB,0x8A,0x48,0x81,0xCB,
++    0x8C,0xC8,0x81,0xCB,0x39,0xD0,0x09,0x48,0x78,0x90,0x18,0x8A,0x86,0xCB,0xE6,0xD8,
++    0xE0,0xE8,0x5A,0x04,0x08,0xA1,0x80,0x1F,0xF8,0x4F,0x83,0x51,0x97,0x05,0x46,0xF9,
++    0x97,0x56,0x58,0x02,0xE8,0xCA,0x30,0x52,0x94,0x51,0x10,0x12,0x91,0x16,0x80,0x43,
++    0xA8,0xC2,0x00,0x1F,0x80,0x4B,0x01,0x0F,0x01,0xF9,0x87,0x43,0xC2,0x83,0xE9,0x00,
++    0x87,0x83,0xE9,0xC5,0xAC,0x85,0x87,0x2D,0x36,0x01,0x00,0xBD,0x40,0x03,0x80,0x14,
++    0x44,0x92,0xFE,0x1B,0x10,0x09,0x00,0x01,0x4E,0xA2,0x66,0xAA,0xC5,0x6B,0x68,0x59,
++    0x82,0x16,0xE0,0x00,0x17,0x02,0x9D,0xCE,0x00,0xF9,0x87,0x43,0x58,0x01,0x80,0xBE,
++    0x30,0x01,0x48,0x15,0x03,0x01,0x20,0x99,0x5B,0x4A,0x0E,0x20,0x01,0x77,0x28,0x21,
++    0x1F,0x2A,0xC2,0x68,0xC9,0x68,0xD1,0x6B,0x68,0x09,0x88,0x2E,0x83,0x43,0xE0,0xB0,
++    0x92,0xB5,0xE7,0x48,0x70,0x09,0x80,0x1E,0xE6,0x00,0x92,0x05,0x17,0x82,0x9C,0x76,
++    0x73,0x01,0x80,0x16,0x60,0x0A,0x6E,0x15,0x3D,0x01,0x40,0xE2,0x80,0x01,0x87,0x1C,
++    0x00,0x0F,0x79,0x01,0x88,0x9E,0x50,0x0D,0x90,0x04,0x10,0x01,0xC1,0x43,0x31,0x1A,
++    0x37,0x8A,0xB8,0xFF,0xFB,0xBF,0xE3,0x68,0xC4,0x1C,0xC0,0x03,0x4E,0x00,0x0E,0x00,
++    0x1B,0x82,0x89,0x03,0x05,0x59,0x8D,0x03,0xEB,0x20,0xE5,0x20,0x00,0x4F,0x50,0x0D,
++    0x90,0x04,0x10,0x01,0xC1,0x43,0x31,0x1A,0x37,0x8A,0xB8,0xFF,0xFB,0x1F,0xE3,0x68,
++    0xEB,0x20,0xE3,0xF8,0x95,0xFD,0x17,0xBA,0x98,0xDE,0xC6,0x1C,0x1C,0x01,0xC4,0x03,
++    0x48,0x08,0x4E,0x01,0x80,0x9E,0x70,0x01,0x81,0x3E,0x80,0x03,0xC0,0x1C,0xC8,0x03,
++    0x85,0x03,0x03,0x59,0x85,0x03,0xE5,0x20,0x01,0x3F,0x80,0x03,0xC0,0x1C,0xC8,0x03,
++    0x83,0x03,0x8B,0x1B,0x05,0x59,0x8D,0x03,0xEB,0x20,0xE5,0x20,0x00,0x27,0x70,0x09,
++    0xCD,0x16,0x00,0x59,0x83,0x03,0xE1,0x20,0x37,0x02,0xB9,0xFF,0xFC,0x7F,0x41,0xEA,
++    0x42,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,0x4A,0xDA,0x44,0x43,0x1A,0xC2,0x00,0x43,
++    0x61,0xD2,0x44,0x03,0x42,0x00,0x02,0x00,0x07,0x03,0x01,0xF9,0x80,0x89,0x84,0x1F,
++    0xE9,0x6F,0x46,0x03,0x08,0x09,0x18,0x42,0x00,0x03,0x81,0x2D,0xEF,0x85,0xAF,0xFD,
++    0x80,0x0D,0xFC,0x54,0x30,0x32,0x30,0x62,0x6F,0x42,0xAC,0x01,0x50,0x09,0x88,0x4E,
++    0x00,0x0F,0x80,0x0F,0xC1,0x6F,0xC0,0x43,0x37,0x00,0xAA,0xD6,0xC5,0x43,0x09,0xF9,
++    0x01,0x42,0x80,0x43,0x04,0x09,0x30,0x22,0x51,0x3A,0x04,0x8F,0x60,0x01,0xC1,0x2E,
++    0xF7,0x00,0x0B,0x01,0x1A,0x42,0x08,0x83,0x30,0x0A,0x01,0x17,0x02,0xF9,0x0F,0x83,
++    0x08,0x01,0x19,0x01,0x08,0x9B,0x04,0x01,0x00,0x4F,0x78,0x01,0x88,0x16,0x18,0x01,
++    0x00,0x9B,0x06,0x17,0xC6,0x9B,0x01,0x9B,0xCA,0xB0,0xE7,0x00,0x94,0x05,0x14,0x42,
++    0x9B,0x9E,0x37,0x02,0x40,0x01,0x80,0x26,0x04,0xA1,0x00,0x83,0x04,0x01,0x30,0x22,
++    0x00,0x0F,0x00,0x21,0x03,0x83,0xD4,0x00,0x92,0x25,0x44,0x83,0x08,0x01,0x1C,0x42,
++    0x01,0x83,0xC2,0x43,0x37,0x00,0xAA,0xE6,0xC5,0x43,0x09,0xF9,0x01,0x42,0x80,0x43,
++    0x66,0x01,0x88,0x5E,0xC0,0x24,0x40,0x09,0x88,0x7E,0x05,0x01,0x02,0x83,0x44,0x83,
++    0x08,0x01,0x1C,0x42,0x05,0x83,0x3A,0x47,0xAC,0x9D,0x87,0x1D,0x20,0x01,0x00,0x01,
++    0x80,0x0C,0x70,0x15,0x44,0xEA,0xF2,0x03,0xEE,0x00,0x92,0x3D,0x6F,0xDA,0xAA,0x01,
++    0x00,0xAF,0x81,0x07,0xF9,0xAF,0xC5,0x43,0x30,0x00,0xA2,0x1E,0x44,0xBA,0xF2,0x03,
++    0x17,0xC2,0x9D,0xB6,0x44,0xAA,0xF2,0x03,0x10,0xC2,0x9D,0x06,0x21,0x11,0xC0,0x43,
++    0x08,0xF9,0x05,0x42,0x82,0x43,0x41,0xC2,0x46,0x0B,0x14,0x79,0x00,0x8A,0x48,0x09,
++    0x88,0x9E,0x08,0x01,0x0E,0x0B,0x44,0x0B,0x83,0x8B,0xE1,0xB0,0xE7,0x20,0x93,0x25,
++    0x60,0x11,0x88,0x56,0x30,0x5A,0xD3,0xCB,0xD4,0x1C,0x10,0x8A,0x8A,0x2E,0xD0,0xCB,
++    0xD4,0x24,0x10,0x8A,0x88,0x0E,0x08,0x09,0x8F,0x0C,0x08,0x01,0x08,0x0B,0x0A,0x01,
++    0x08,0x0B,0x0C,0x81,0x02,0x0B,0x44,0x0B,0x10,0x01,0x1C,0x8A,0x00,0x0B,0x62,0x11,
++    0x88,0x4E,0xC6,0x0C,0x39,0x0F,0x4B,0xEA,0x60,0x54,0x80,0x13,0x12,0x01,0x80,0x13,
++    0xE4,0x4B,0x86,0x0B,0x4A,0x0A,0x8A,0x01,0x5E,0x53,0x84,0x13,0x58,0x53,0x8A,0x13,
++    0x12,0xA9,0x88,0x13,0x14,0x19,0x88,0x13,0x4E,0x53,0x8E,0x13,0x48,0x53,0x94,0x13,
++    0x4A,0x4B,0x92,0x0B,0x0C,0x31,0x90,0x0B,0x3F,0x82,0xAB,0x85,0x80,0x4D,0x34,0x22,
++    0x30,0x01,0x00,0x01,0x80,0x2C,0x38,0x01,0x48,0x62,0xD9,0x43,0xDA,0x4B,0x1A,0x42,
++    0x81,0x14,0x40,0x5A,0x80,0x71,0x80,0x24,0xC0,0x71,0x80,0x1C,0x60,0x09,0x80,0x0E,
++    0x60,0x29,0x88,0x7E,0x60,0x09,0x88,0x26,0x73,0x6A,0xE1,0x80,0x81,0x2C,0x78,0x6A,
++    0x01,0x27,0x70,0x6A,0xE0,0x80,0x83,0x2C,0x79,0x52,0xF9,0xC1,0x47,0x35,0xB8,0xFF,
++    0xF0,0xEF,0x01,0x3F,0x60,0x21,0x88,0x2E,0x70,0x42,0x41,0x35,0xBD,0xFF,0xFF,0xDF,
++    0x7B,0x22,0xB9,0x11,0x6F,0xCA,0xA8,0x01,0xC5,0x43,0x09,0xF9,0x01,0x42,0x80,0x43,
++    0xC1,0x43,0x09,0x01,0x19,0x42,0x80,0x43,0x42,0xD2,0x40,0x0B,0x10,0x01,0x1A,0x8A,
++    0x00,0x0B,0x42,0xCA,0x44,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,0x48,0xBA,0x40,0x43,
++    0x10,0x09,0x18,0x82,0x00,0x43,0x08,0x09,0x07,0x01,0xBC,0xFF,0xF8,0xAF,0x42,0x09,
++    0x88,0x5E,0x62,0x21,0x88,0x56,0x12,0x09,0x91,0x04,0x30,0x82,0x18,0x01,0xC8,0x14,
++    0xBF,0xFF,0xF7,0xAF,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x59,0x40,0x35,0x30,0x9A,
++    0xBF,0xFF,0xF7,0x6F,0x10,0x09,0x90,0x04,0x10,0x01,0x00,0xCF,0x00,0xE0,0x00,0x01,
++    0x08,0x40,0x00,0x01,0x80,0x00,0x06,0x01,0x00,0xF8,0x07,0x00,0x80,0x30,0x02,0x01,
++    0x30,0x04,0x05,0x08,0x00,0x00,0x06,0x42,0x80,0x01,0x06,0x42,0xF8,0x00,0x06,0x42,
++    0x18,0x60,0x05,0x01,0x70,0x70,0x06,0x01,0x50,0x20,0x07,0x01,0x68,0x60,0x02,0x01,
++    0x09,0x29,0x30,0xC2,0x37,0x9A,0xB8,0xFF,0xF0,0x57,0x16,0x09,0x90,0x04,0x10,0x01,
++    0x0E,0x71,0x40,0x0A,0x37,0x9A,0xB8,0xFF,0xF0,0x17,0x16,0x09,0x90,0x04,0x10,0x01,
++    0x08,0x29,0x30,0x9A,0xC7,0x24,0xB8,0xFF,0xF0,0xD7,0x15,0x09,0x90,0x04,0x10,0x01,
++    0x08,0x29,0x18,0x09,0xC7,0x1C,0xB8,0xFF,0xF1,0x97,0x05,0x9F,0x60,0x09,0x80,0x0E,
++    0x61,0x29,0x88,0x7E,0x10,0x11,0x90,0x04,0x11,0x09,0x30,0x82,0x18,0x01,0xC8,0x14,
++    0xBD,0xFF,0xF7,0x2F,0x10,0x11,0x90,0x04,0x10,0x01,0x30,0x9A,0xC8,0x14,0xC0,0x2C,
++    0xBC,0xFF,0xF7,0xEF,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x21,0x40,0x35,0x30,0x9A,
++    0xBC,0xFF,0xF7,0xAF,0x10,0x09,0x90,0x04,0x11,0x01,0x08,0x31,0x30,0xC2,0x31,0x9A,
++    0xBC,0xFF,0xF7,0x6F,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x29,0x30,0x9A,0xC0,0x24,
++    0xBC,0xFF,0xF7,0x2F,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x29,0x18,0x09,0xC0,0x1C,
++    0xBB,0xFF,0xF7,0xEF,0xC6,0x43,0x09,0xF9,0x01,0x42,0x80,0x43,0x40,0xDA,0x44,0x0B,
++    0x42,0x48,0x02,0x48,0x04,0x0B,0x40,0xD2,0x0A,0x01,0x0F,0x0B,0x0C,0x01,0x00,0x0B,
++    0x44,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,0x87,0x4D,0xE8,0x85,0xAC,0x85,0x63,0xAA,
++    0xC8,0x03,0x43,0x09,0x83,0x16,0xC8,0x03,0x40,0x29,0x88,0x86,0x46,0x8A,0xC4,0x01,
++    0x82,0x1F,0xC8,0xDF,0x69,0x82,0xC4,0x43,0x40,0x11,0x98,0x2E,0xCF,0x03,0xBB,0xFF,
++    0xF8,0x67,0x00,0x01,0x83,0x43,0xE9,0x85,0xE1,0x00,0x82,0x43,0xEB,0x85,0xCB,0x03,
++    0x40,0x21,0x88,0x26,0xB8,0xFF,0xFF,0x0F,0x03,0x19,0x88,0x03,0xEB,0x85,0xCB,0x03,
++    0x47,0x19,0x80,0xDE,0xC8,0x03,0x43,0x31,0x84,0xC6,0x47,0x12,0xC4,0x01,0xFE,0x03,
++    0x40,0x01,0x88,0x3E,0x41,0xFA,0x83,0x01,0xD0,0x0B,0x48,0x31,0x9C,0x76,0xC7,0x03,
++    0x37,0x00,0xA8,0x5E,0x44,0xDA,0xC3,0x01,0xE8,0x03,0x44,0x01,0x8F,0x36,0xBF,0xFF,
++    0xEB,0xCF,0xEC,0x85,0xA8,0xC5,0x27,0x01,0x30,0x1A,0x00,0x09,0x4B,0xAA,0x6B,0xBA,
++    0x30,0x01,0x59,0x51,0x80,0xE6,0xE1,0x4E,0x79,0xAA,0xC3,0xD3,0x85,0x1F,0xE8,0xFF,
++    0x61,0x52,0x20,0x09,0x39,0x61,0x62,0x52,0x71,0x61,0x62,0x92,0x40,0x6A,0x13,0x31,
++    0xC2,0x01,0x56,0x03,0x80,0x01,0x5A,0xC9,0x80,0xAE,0xE1,0x4E,0x59,0x59,0x80,0x56,
++    0x59,0x61,0x80,0x66,0x59,0x69,0x88,0xBE,0x02,0x29,0x88,0x43,0x21,0x09,0x00,0x9F,
++    0x59,0xD1,0x80,0x6E,0x59,0x01,0x89,0x7E,0x88,0x53,0x22,0x09,0x08,0x59,0xA5,0x0B,
++    0x00,0x57,0x01,0x39,0x89,0x43,0x02,0x3F,0x86,0x07,0xE8,0xA7,0x00,0x27,0x19,0x12,
++    0x81,0xD3,0x01,0x0F,0x00,0x41,0x18,0x12,0x80,0xD3,0x01,0xEF,0x02,0x11,0x88,0x43,
++    0x20,0x09,0x00,0xCF,0x02,0x01,0x88,0x43,0x41,0x43,0x19,0x82,0x00,0x43,0x01,0x9F,
++    0x88,0x43,0x22,0x09,0x00,0x87,0x00,0x19,0x88,0x43,0x22,0x09,0x00,0x67,0x00,0x21,
++    0x88,0x43,0x22,0x09,0x02,0x47,0x88,0x53,0x26,0x09,0x08,0x69,0xA0,0x0B,0x00,0x1F,
++    0x88,0x53,0x22,0x09,0x08,0x79,0xA7,0x0B,0x60,0x01,0x80,0x66,0x40,0x6A,0x42,0x0B,
++    0x30,0x48,0xA8,0x2E,0x08,0x81,0x06,0x0B,0x08,0x81,0x02,0x0B,0x08,0x81,0x00,0x0B,
++    0x45,0x43,0x19,0x82,0x07,0x43,0xE9,0xC5,0xAC,0x8D,0x87,0x15,0x40,0x32,0x82,0x0C,
++    0x46,0x02,0xC2,0x01,0xDA,0x2B,0xD8,0x33,0x0C,0x01,0xB0,0x0B,0x61,0x02,0xC2,0x0B,
++    0x10,0xF9,0x05,0x8A,0x81,0x0B,0xC1,0x0B,0x10,0x01,0x19,0x8A,0x81,0x0B,0x49,0xEA,
++    0x8A,0x01,0x46,0x53,0x18,0x01,0x1A,0xD2,0x01,0x53,0x52,0xAA,0x44,0x8B,0x1A,0x01,
++    0x1A,0xCA,0x00,0x8B,0x48,0x8A,0x41,0x53,0x18,0x09,0x18,0xD2,0x02,0x53,0x50,0x03,
++    0x80,0x01,0xE2,0x0B,0x49,0x79,0x87,0xAE,0xE6,0x03,0x40,0x69,0x88,0x16,0x09,0xA9,
++    0x07,0x91,0xB8,0xFF,0xE8,0x4F,0x47,0x09,0x89,0xDE,0x31,0x42,0x1A,0x82,0x03,0x38,
++    0x15,0x09,0x90,0xCD,0x90,0x04,0x18,0x01,0xC7,0x0C,0xB8,0xFF,0xE9,0x47,0x44,0x5A,
++    0x10,0x09,0x90,0x04,0x15,0x01,0x90,0xCD,0x37,0x9A,0xB8,0xFF,0xE8,0x07,0xC4,0x14,
++    0x15,0x09,0xC8,0x48,0xE8,0x48,0x90,0x04,0x00,0x48,0x12,0x01,0x1F,0x09,0xB8,0xFF,
++    0xE8,0xB7,0x03,0xF7,0x08,0xA1,0x00,0x91,0xBE,0xFF,0xEF,0x37,0x40,0x09,0x88,0xC6,
++    0x18,0xAA,0x13,0x09,0x20,0x40,0x63,0x08,0x90,0x04,0x30,0x9A,0xC7,0x0C,0xB8,0xFF,
++    0xE8,0x37,0x03,0x77,0x08,0xB1,0x00,0x91,0xBD,0xFF,0xEF,0xB7,0x40,0x09,0x88,0x46,
++    0xC0,0x14,0x10,0x09,0xC8,0x48,0xED,0x48,0x00,0x48,0x32,0x9A,0x97,0x04,0xB8,0xFF,
++    0xE9,0xB7,0xC2,0x03,0x08,0xF9,0x06,0x42,0x80,0x03,0x41,0x42,0x42,0x0B,0x40,0x48,
++    0x00,0x48,0x02,0x0B,0x47,0x32,0x08,0x01,0x08,0x0B,0x0A,0x01,0x02,0x0B,0x44,0x0B,
++    0x10,0x01,0x1C,0x8A,0x07,0x0B,0xEA,0xF5,0x70,0x00,0x04,0x01,0xF8,0x00,0x06,0x42,
++    0x80,0x01,0x06,0x42,0x00,0xE0,0x06,0x01,0x00,0x00,0x00,0x01,0x10,0x00,0x00,0x42,
++    0x00,0xE0,0x07,0x01,0x00,0x00,0x00,0x42,0x50,0x20,0x07,0x01,0x08,0x20,0x02,0x01,
++    0x52,0x2A,0x44,0x83,0x04,0x83,0x42,0x2A,0xF7,0x0B,0x4C,0xF9,0x94,0x16,0xF0,0x0B,
++    0xE4,0x48,0xB2,0x0B,0xF0,0x03,0x44,0xC1,0x90,0x0E,0x00,0x01,0x03,0x83,0x3C,0x82,
++    0x4C,0xFA,0x4B,0x53,0x5C,0xEA,0xE3,0xC3,0x1C,0x12,0x0C,0x53,0x10,0x43,0x02,0x09,
++    0xB3,0xC3,0x3C,0x82,0xAB,0x85,0x40,0xD2,0x84,0x01,0x42,0x0B,0x10,0x01,0x1C,0x8A,
++    0x03,0x0B,0x54,0xC2,0x4B,0xAA,0x43,0xC2,0x87,0x1F,0xC0,0x27,0xEF,0x85,0xA8,0xC5,
++    0x47,0x92,0x83,0x01,0xC3,0x0B,0x70,0xAA,0x30,0x48,0xAC,0x46,0xC2,0x0B,0x10,0x01,
++    0x18,0x8A,0x80,0x0B,0x44,0x83,0x0B,0x01,0x1B,0x42,0x04,0x83,0xE8,0xC5,0x0F,0x01,
++    0x0D,0x8B,0x45,0x9B,0x66,0x4A,0x03,0x79,0x01,0x1A,0x30,0x2A,0xAB,0x01,0x69,0x04,
++    0x50,0x13,0x5B,0x09,0x80,0x6E,0x59,0x29,0x80,0x46,0x58,0x41,0x8B,0xDE,0x93,0x4B,
++    0x46,0x9B,0x3F,0xD8,0x88,0x16,0x00,0x81,0x07,0x83,0xED,0xC5,0x0B,0x8B,0x4D,0x22,
++    0x10,0x42,0x8C,0x16,0x07,0x29,0x05,0x83,0x00,0x3F,0xE0,0x92,0x02,0x93,0xE7,0x00,
++    0x93,0x05,0x2C,0x04,0x40,0x89,0x9A,0x06,0x2A,0x0C,0x43,0xCA,0x40,0x13,0x08,0x41,
++    0x18,0x52,0x04,0x13,0x44,0x13,0x1C,0x52,0x00,0x13,0x14,0xA1,0x04,0x93,0x45,0x13,
++    0x1C,0x52,0x04,0x13,0x44,0x13,0x1C,0x52,0x04,0x13,0x44,0x13,0x1C,0x52,0x00,0x13,
++    0xEA,0xC5,0x5F,0xA2,0xD0,0x7B,0x43,0xDC,0x7B,0x11,0x90,0x56,0x78,0x01,0x88,0x36,
++    0x42,0x83,0x57,0x82,0x02,0x84,0x40,0x82,0x13,0x03,0x2B,0x0C,0x07,0x1F,0x44,0x83,
++    0x12,0xD0,0x48,0x62,0xC4,0x80,0x90,0x3D,0x06,0x7C,0x00,0x89,0x11,0x00,0xD0,0xC0,
++    0x40,0x01,0xC1,0x96,0x97,0xC5,0xBF,0xFF,0xF2,0xAF,0x43,0x42,0x13,0x3A,0x84,0x96,
++    0x40,0x32,0x82,0x41,0x13,0x3A,0x8C,0x76,0x00,0x09,0x80,0x07,0xC8,0x3F,0x06,0xC1,
++    0xB2,0x03,0x4D,0x1A,0x00,0x09,0x80,0x43,0x01,0x2F,0x43,0xC2,0x82,0x01,0xCE,0x03,
++    0x41,0x01,0x88,0x2E,0x46,0xEA,0xC1,0x31,0x10,0x3A,0x8C,0xAE,0x40,0xEA,0x41,0x0B,
++    0x40,0xCA,0x71,0x50,0x80,0x01,0x82,0x13,0x62,0x50,0x80,0x13,0x54,0x50,0x80,0x13,
++    0x80,0x0B,0xC6,0x0B,0xC4,0x13,0xC2,0x48,0xC6,0x13,0xC4,0x1B,0xC4,0x90,0xC6,0x48,
++    0x88,0x29,0x55,0x50,0x8A,0x13,0x88,0x0B,0x00,0x69,0x18,0x00,0xD2,0xC0,0x41,0x81,
++    0xC3,0x16,0x28,0x04,0x02,0xFF,0x01,0x27,0x06,0x01,0x18,0x02,0x29,0x04,0x03,0xD7,
++    0x41,0x6A,0xC1,0xC0,0x40,0x19,0xC1,0x1E,0x29,0x04,0x43,0x62,0x11,0x03,0x03,0x97,
++    0x41,0x4A,0xC1,0x81,0xC1,0xC0,0x41,0x01,0xC3,0x26,0x28,0x04,0x41,0x3A,0xC1,0x01,
++    0x11,0x03,0x03,0x47,0x00,0x69,0x18,0x00,0xD1,0xC0,0x41,0xB1,0xC3,0x1E,0x29,0x04,
++    0x00,0x0F,0x79,0xDA,0x10,0xC2,0x85,0xF6,0x40,0xBB,0xA7,0xBA,0x45,0xDA,0xC0,0xD1,
++    0x10,0x1A,0x8C,0x7E,0x6A,0x04,0x43,0x61,0x8B,0x66,0x50,0x1B,0xE0,0xFA,0x50,0x7A,
++    0x94,0x01,0x7A,0x01,0x88,0x16,0x00,0x09,0xA8,0x83,0x04,0x1F,0xE0,0xC2,0x40,0x01,
++    0x8C,0x06,0xA8,0x8B,0x6A,0x04,0xE3,0x00,0x93,0x05,0x2C,0x04,0x40,0x89,0x9A,0x16,
++    0x06,0x01,0x18,0x02,0x2B,0x04,0xD3,0x43,0xE3,0x00,0x92,0x43,0x05,0x81,0x00,0x83,
++    0xED,0xC5,0x07,0x8B,0xE8,0xC5,0x07,0x00,0x10,0x00,0x00,0x42,0x00,0xE0,0x00,0x01,
++    0xF8,0x00,0x06,0x42,0x80,0xC0,0x04,0x01,0x08,0x40,0x00,0x01,0x80,0x01,0x06,0x42,
++    0xF8,0xFF,0x07,0x00,0x00,0x10,0x00,0x01,0x80,0x30,0x02,0x01,0x88,0x36,0x00,0x00,
++    0x00,0x20,0x00,0x01,0x00,0xA0,0x00,0x01,0x77,0x81,0xF8,0xFF,0xF8,0x02,0x07,0x00,
++    0xA8,0x85,0x80,0x07,0xC8,0xBF,0x65,0x32,0xC8,0x03,0x43,0x01,0x80,0x26,0x40,0x31,
++    0x8F,0xD6,0xBF,0xFF,0xD7,0xFF,0x3B,0xBF,0xBE,0xFF,0xCF,0x07,0x38,0xA7,0x07,0x00,
++    0x00,0xE0,0x06,0x01,0xAF,0xC5,0x77,0x62,0x03,0x01,0x87,0x83,0x01,0x09,0x80,0x83,
++    0x0F,0x01,0x81,0x8B,0x05,0x19,0x80,0x83,0x03,0x41,0x89,0x83,0x07,0x69,0x89,0x83,
++    0x05,0x69,0x88,0x83,0x11,0x02,0x32,0xAA,0xA9,0x01,0x06,0x44,0x04,0xF9,0x87,0x89,
++    0x20,0x84,0x01,0x09,0x34,0x62,0xE1,0x01,0x93,0x03,0x91,0x03,0x05,0x41,0x90,0x03,
++    0x17,0x51,0x90,0x13,0x11,0xA1,0x98,0x13,0x98,0x0B,0x0D,0x81,0x99,0x0B,0xA7,0x03,
++    0x3B,0x01,0xA0,0xBB,0x09,0x71,0x98,0x8B,0x0B,0x29,0x98,0x8B,0x17,0x71,0x98,0x93,
++    0x99,0x8B,0xA5,0xBB,0xA1,0x83,0x05,0x81,0xA0,0x83,0x07,0x51,0x8F,0x03,0x01,0xB1,
++    0x8D,0x03,0x8B,0x3B,0x8B,0x3B,0x9F,0x0B,0x05,0x99,0x28,0x84,0x07,0xF9,0x87,0x09,
++    0x10,0x44,0x01,0xC9,0x0B,0x00,0x12,0x44,0x02,0x19,0x18,0x00,0x0E,0x43,0x43,0x5A,
++    0x0A,0x43,0x05,0x01,0xB9,0x43,0x31,0x02,0x0D,0x51,0x80,0x11,0x83,0x1F,0xD0,0x17,
++    0x01,0xB1,0x97,0x43,0x1B,0xF1,0x90,0x5B,0x89,0x7B,0x33,0x02,0x82,0x01,0xB2,0x3B,
++    0xB8,0x3B,0x08,0xC1,0xB8,0x0B,0x0A,0x51,0xBE,0x0B,0x14,0x41,0x31,0x0A,0x88,0x01,
++    0x0F,0x54,0x12,0xF9,0x94,0x99,0x0A,0x54,0x16,0xC1,0xBE,0x13,0x10,0x41,0x81,0x53,
++    0x12,0x11,0x87,0x53,0x80,0x5B,0x14,0x51,0x91,0x13,0x12,0x41,0x93,0x13,0x14,0x21,
++    0x92,0x13,0x16,0xA9,0x08,0x14,0x16,0x71,0x9A,0x13,0x10,0x69,0xA0,0x13,0x10,0x21,
++    0xA6,0x13,0x12,0x41,0x10,0x14,0x12,0x31,0xBF,0x93,0x37,0xBC,0xB0,0x3B,0x1C,0x21,
++    0x33,0x12,0x90,0x01,0x90,0x9B,0x1C,0x31,0x96,0x9B,0x12,0x99,0x08,0x94,0x11,0xA1,
++    0x80,0x53,0x16,0x51,0x8E,0x53,0xB0,0x3B,0x12,0x21,0x8C,0x53,0x53,0x42,0x05,0x54,
++    0x14,0x09,0x88,0x53,0x10,0x51,0x90,0x53,0x17,0x11,0xA0,0x13,0x08,0x21,0xA8,0x0B,
++    0x0A,0xC1,0xAB,0x0B,0xA8,0x0B,0x1C,0x01,0x33,0x0A,0xC8,0x01,0xA0,0x5B,0xAE,0x5B,
++    0x22,0xF1,0x88,0x01,0xBA,0x63,0xB8,0x63,0x24,0xE1,0xB9,0x63,0x26,0x41,0xB8,0x63,
++    0x80,0x13,0x08,0xB1,0x80,0x0B,0x0A,0x19,0x84,0x0B,0x4C,0xD2,0x00,0x0B,0x92,0x1B,
++    0x4C,0xCA,0xC4,0x01,0x38,0x0B,0x88,0x91,0x3E,0x0B,0x8A,0xE1,0x38,0x0B,0x0C,0xE1,
++    0x40,0xB2,0x84,0x1F,0xCC,0xBF,0x47,0xAA,0x09,0xE1,0xC0,0xC1,0x87,0x1F,0xC8,0x97,
++    0x4C,0x8A,0x44,0x9A,0xCE,0x11,0x03,0x0B,0xCC,0x71,0x00,0x0B,0x88,0xA1,0x08,0x0B,
++    0x8A,0xA1,0x08,0x0B,0xCA,0xE1,0x01,0x0B,0xC8,0xC1,0x01,0x0B,0x8C,0x61,0x0D,0x0B,
++    0xCA,0x81,0x15,0x0B,0xF8,0x48,0x10,0x0B,0xFE,0x48,0x08,0x0B,0xE9,0xC5,0xAF,0x85,
++    0x0C,0x01,0x60,0x0A,0x47,0x02,0xA4,0x61,0xF8,0x1B,0x06,0x77,0x02,0x21,0x19,0x42,
++    0xCB,0x28,0x00,0x99,0x12,0x79,0x08,0x00,0xC4,0x40,0x89,0x13,0x16,0x01,0x88,0x13,
++    0x94,0x13,0x10,0x14,0x12,0x14,0xE6,0x48,0x94,0x4D,0x16,0x5A,0xC0,0x76,0x07,0x01,
++    0x13,0xF9,0x2F,0x89,0x08,0x68,0x03,0x37,0x00,0x08,0xCA,0x48,0xCC,0x48,0xAA,0x53,
++    0xAA,0x53,0xE6,0x00,0x94,0x05,0x16,0x1A,0xC1,0xB6,0xEF,0x85,0xA3,0x85,0x51,0x72,
++    0x90,0x01,0x0E,0x01,0x26,0x8C,0xD0,0x01,0xBC,0x8B,0xB8,0x8B,0x36,0x9A,0x98,0x01,
++    0x8A,0xCB,0x0C,0xCC,0x9E,0xCB,0x88,0xCB,0x2C,0x09,0xB0,0xAB,0xA8,0x8B,0x34,0xA2,
++    0xA1,0x01,0xCD,0x1B,0xB0,0x9B,0x36,0x9A,0x9A,0x01,0xA9,0xCB,0x9A,0x01,0xA9,0xEB,
++    0xA8,0xCB,0xA8,0xAB,0x28,0x41,0x89,0xAB,0x8B,0x0B,0x57,0x32,0x88,0x8B,0x46,0x09,
++    0x8C,0x16,0xA8,0xCB,0xE5,0x85,0x39,0x97,0xE3,0x85,0x39,0x82,0x0B,0x08,0x42,0x12,
++    0x41,0x13,0x18,0x01,0x04,0xD2,0x90,0x41,0x04,0x13,0x10,0xD0,0x1A,0x8A,0x08,0x0B,
++    0x40,0x0B,0x42,0x0B,0x14,0x41,0x18,0x8A,0x00,0x0B,0x08,0x01,0x03,0x0B,0x3C,0x82,
++    0xAA,0x85,0x40,0xD2,0x40,0x0B,0x30,0x48,0xAE,0x2E,0x08,0x81,0x02,0x0B,0x08,0x81,
++    0x00,0x0B,0x08,0x81,0x02,0x0B,0x48,0xAA,0x8C,0x01,0x46,0x53,0x38,0x90,0x78,0x90,
++    0x04,0x53,0x44,0x53,0x18,0x81,0x19,0xD2,0x02,0x53,0x5C,0x8A,0x12,0x09,0x06,0xD3,
++    0x16,0x91,0x01,0x13,0x44,0x7A,0x42,0x23,0x10,0x61,0x18,0xA2,0x02,0x23,0x44,0x23,
++    0x1A,0xA2,0x00,0x23,0x4C,0x23,0x1A,0xA2,0x08,0x23,0x4A,0x23,0x18,0xA2,0x08,0x23,
++    0x40,0x23,0x1E,0xA2,0x02,0x23,0x46,0x43,0x10,0x01,0x1A,0x82,0x04,0x43,0x02,0xD1,
++    0x07,0xC3,0x00,0x01,0x08,0xC3,0xEA,0x85,0x40,0x12,0x42,0x13,0x08,0x09,0x18,0x52,
++    0x00,0x13,0x48,0x13,0x18,0x52,0x0C,0x13,0x4C,0x13,0x1A,0x52,0x0E,0x13,0x42,0x13,
++    0x1E,0x52,0x00,0x13,0x39,0x82,0x43,0xE2,0x58,0x0B,0x10,0x21,0x18,0x8A,0x18,0x0B,
++    0x5A,0x0B,0x10,0x01,0x18,0x8A,0x18,0x0B,0x5C,0x13,0x08,0x01,0x18,0x52,0x18,0x13,
++    0x40,0x92,0x11,0x01,0x80,0x01,0x06,0x13,0x40,0x13,0x1A,0x52,0x01,0x13,0x4A,0x72,
++    0x41,0x43,0x10,0x01,0x18,0x82,0x00,0x43,0x38,0x82,0xAB,0x85,0x08,0x09,0x00,0x31,
++    0x81,0x07,0xD0,0xF7,0x08,0x11,0x00,0x21,0x81,0x07,0xD0,0xD7,0x00,0x09,0x80,0x07,
++    0xD0,0xB7,0x02,0x31,0x82,0x07,0xD0,0x9F,0x00,0x21,0x80,0x07,0xD0,0x87,0x82,0x07,
++    0xD0,0x2F,0xEB,0x85,0xA8,0x85,0x43,0xF2,0x4A,0xBA,0xC0,0x91,0x11,0x43,0x0A,0x91,
++    0x80,0x1F,0xC8,0x07,0x40,0xD2,0x08,0x51,0x80,0x41,0x81,0x1F,0xC7,0xEF,0xBF,0xFF,
++    0xF0,0x4F,0x02,0x09,0xBA,0xFF,0xFF,0x17,0x07,0xA1,0xB8,0xFF,0xFF,0x3F,0xBB,0xFF,
++    0xFF,0xBF,0xBB,0xFF,0xFF,0xC7,0xBD,0xFF,0xFF,0x3F,0xBD,0xFF,0xF8,0x77,0x66,0x8A,
++    0x29,0x01,0x80,0x2B,0x08,0x2B,0x41,0x72,0x09,0x71,0x80,0x91,0x87,0x1F,0xC0,0x17,
++    0x0B,0x2C,0x81,0x2B,0x87,0x2B,0x85,0x2B,0x8B,0x2B,0x89,0x2B,0x05,0x51,0x88,0x03,
++    0x0F,0x2C,0x8B,0x2B,0x0B,0x2C,0xED,0x85,0x00,0xE0,0x00,0x01,0xC8,0x21,0x01,0x00,
++    0x70,0x02,0x01,0x00,0xF8,0xFF,0x07,0x04,0x68,0x02,0x03,0x00,0x70,0x70,0x06,0x01,
++    0x80,0xC0,0x04,0x01,0x00,0x20,0x00,0x01,0x10,0x00,0x00,0x42,0x00,0x00,0x00,0x42,
++    0x80,0x01,0x06,0x42,0xF8,0x00,0x06,0x42,0x18,0x00,0x02,0x42,0xA8,0x85,0x80,0x07,
++    0xC8,0xCF,0xEE,0x85,0xAF,0x85,0xB8,0xFF,0xE8,0x9F,0xEF,0x85,0xA8,0x7D,0x80,0x04,
++    0x88,0x0C,0xC0,0x0C,0x80,0x14,0xC0,0x04,0x83,0x1C,0x30,0x42,0x40,0x7E,0x80,0x25,
++    0xE8,0x05,0x00,0x00,0xAC,0xFD,0x87,0x1D,0x30,0x32,0x00,0x01,0x82,0x14,0x00,0x9F,
++    0x44,0xDA,0x0E,0x01,0x0C,0x0B,0x26,0x01,0xC2,0x14,0x00,0x28,0x7F,0xC2,0x4E,0xC3,
++    0x1F,0x02,0x09,0xC3,0xD0,0x6C,0x90,0x04,0x14,0x09,0x08,0x01,0x30,0x82,0xD9,0x64,
++    0x86,0x17,0xE0,0x1F,0xF8,0x82,0x33,0x0A,0xCF,0x99,0x49,0xC9,0x99,0x3E,0x40,0x91,
++    0xE7,0x16,0x48,0xC3,0x1F,0x02,0x0D,0xC3,0x40,0x20,0x63,0x01,0x88,0x36,0xD7,0x6C,
++    0x90,0x04,0x10,0x09,0x09,0x01,0x34,0x82,0xD8,0x64,0x80,0x17,0xE3,0x77,0xFD,0xA2,
++    0xD0,0x6C,0x90,0x04,0x14,0x09,0x08,0x01,0x30,0x82,0xD9,0x64,0x85,0x17,0xE0,0x2F,
++    0xF8,0xBA,0xD3,0x6C,0x90,0x04,0x10,0x09,0x09,0x01,0x34,0x82,0xD8,0x64,0x80,0x17,
++    0xE5,0xE7,0x14,0x3A,0xE9,0x16,0x30,0x02,0x30,0xE2,0x31,0x3A,0xFD,0x82,0x13,0xC2,
++    0xE3,0x0E,0x98,0xBA,0x05,0x17,0x10,0x02,0xDB,0x06,0x98,0xA2,0x46,0xC2,0x4D,0x03,
++    0xDE,0x8A,0x0B,0x00,0xC0,0x00,0xCA,0x24,0x00,0x44,0xC0,0x24,0xE0,0x00,0x84,0x24,
++    0xC2,0x14,0xE0,0x00,0x90,0x05,0x86,0x14,0xC8,0x2C,0xC0,0x14,0x15,0x42,0x9C,0x3E,
++    0x87,0x3D,0xE8,0x85,0xAC,0xFD,0x87,0x7D,0x30,0xA2,0x30,0xFA,0xD8,0x0B,0x8F,0x6C,
++    0xD8,0x0B,0x8B,0x64,0x40,0x01,0x80,0x6E,0x48,0x52,0x05,0x99,0x07,0x43,0x12,0xF9,
++    0x58,0x3A,0x95,0x81,0x10,0xD3,0x06,0x43,0x00,0xC1,0x83,0x17,0xF8,0xFF,0xF1,0x84,
++    0xB0,0xE1,0x01,0xCF,0x40,0x1A,0x0D,0x19,0x04,0x0B,0x0A,0x19,0x05,0x0B,0x48,0x12,
++    0xC2,0x84,0xC0,0x30,0x11,0x01,0x30,0xDA,0x30,0x8A,0x00,0x09,0x82,0x17,0xC0,0xC7,
++    0x29,0x01,0x30,0x1A,0x14,0x09,0x08,0x01,0x40,0x1D,0xB8,0x04,0x82,0x17,0xE0,0x6F,
++    0xE7,0x68,0x93,0x6D,0x6F,0x91,0x99,0xA6,0x48,0xB2,0x44,0x43,0x10,0x11,0x18,0x82,
++    0x01,0x43,0x30,0x02,0x80,0x01,0x35,0x2A,0xC8,0x03,0x32,0x00,0xAC,0xEE,0x49,0x9A,
++    0x00,0x01,0x80,0x43,0x31,0x12,0x31,0xCA,0x00,0x11,0x80,0x0F,0xF9,0xF7,0x34,0x1A,
++    0xB8,0x04,0x08,0x01,0x00,0x11,0xD0,0x84,0x84,0x17,0xC0,0x47,0x49,0x42,0xD4,0x43,
++    0x08,0x43,0x2A,0x01,0xC2,0x64,0x00,0x00,0x80,0x74,0x00,0xBF,0x31,0xDA,0x31,0x52,
++    0x08,0x01,0x00,0x09,0x81,0x17,0xC0,0x27,0xB8,0x0C,0xA0,0x04,0x30,0x8A,0x41,0x1D,
++    0xD8,0x84,0xD0,0x64,0xB9,0xFF,0xFF,0xF7,0xC4,0x74,0xC8,0x30,0x09,0x09,0x30,0xDA,
++    0x30,0x52,0x31,0x42,0x80,0x17,0xC0,0xA7,0xE7,0x68,0x93,0x6D,0xC4,0x6C,0x10,0x2A,
++    0x99,0x26,0x37,0x1A,0xB8,0x04,0x08,0x01,0x00,0x19,0xD0,0x84,0x82,0x17,0xC0,0xF7,
++    0x31,0x12,0x31,0xCA,0x00,0x01,0x80,0x0F,0xFB,0x47,0x4B,0x92,0x40,0x43,0x10,0x11,
++    0x18,0x82,0x04,0x43,0x87,0x9D,0xE8,0x85,0xAC,0xFD,0x87,0x1D,0x30,0x7A,0x50,0x01,
++    0x80,0x16,0x00,0x01,0x80,0x0C,0x00,0x0F,0x00,0x09,0x80,0x0C,0x2A,0x01,0x00,0x47,
++    0xCD,0x64,0x00,0x40,0xC1,0x30,0x32,0x52,0x08,0x19,0xD8,0x6C,0xC0,0x0C,0x80,0x0F,
++    0xF9,0x3F,0x07,0x41,0x85,0x17,0xF0,0xD7,0x20,0x09,0xC0,0x34,0x80,0x01,0x84,0x14,
++    0x60,0x81,0x99,0x36,0x0A,0xF9,0x47,0xF2,0x88,0x11,0x18,0x0B,0x42,0x08,0x1B,0x0B,
++    0x02,0x0F,0x40,0xDA,0x1F,0x23,0x02,0xF9,0x4F,0xCA,0x82,0x89,0x88,0x01,0x12,0x43,
++    0x00,0x11,0x80,0x17,0xF0,0x1F,0xC5,0x14,0xF0,0x03,0x46,0x01,0x80,0x3E,0x00,0x51,
++    0x84,0x17,0xF0,0xE7,0x40,0x83,0x41,0x03,0x30,0x00,0xA8,0x86,0x07,0x5F,0x00,0xF9,
++    0x4C,0x7A,0x82,0x89,0x88,0x01,0x12,0x43,0x00,0x09,0x80,0x17,0xF1,0x7F,0x44,0x83,
++    0x40,0x03,0x30,0x00,0xA3,0x1E,0xE0,0x20,0x93,0x25,0x67,0xF9,0xC9,0x86,0x06,0xE4,
++    0xE1,0xF8,0x35,0x52,0x08,0x09,0xD8,0x6C,0xC0,0x0C,0x80,0x0F,0xFB,0x4F,0xE5,0x68,
++    0x90,0x6D,0xC7,0x1C,0x15,0x2A,0x9C,0x9E,0x3F,0x17,0xA9,0x85,0x80,0x3D,0x34,0x7A,
++    0x34,0xA2,0x00,0xD9,0xEF,0x02,0x0E,0xF9,0x88,0x09,0x40,0x01,0x80,0x0E,0x30,0x72,
++    0x00,0x0F,0x30,0x19,0x13,0xB0,0xD9,0xC3,0x81,0x34,0xD8,0xC3,0x80,0x2C,0x98,0x1C,
++    0xC2,0x34,0x00,0x00,0xC0,0x00,0x86,0x24,0x45,0xAA,0x11,0x81,0x00,0x13,0x1A,0x0B,
++    0x28,0x01,0x00,0x67,0x4D,0x03,0x01,0x48,0xC0,0x00,0x42,0x03,0x01,0x33,0x30,0x1A,
++    0x30,0x52,0x09,0x09,0x00,0x01,0x80,0x0F,0xFB,0xDF,0xE3,0x68,0x90,0x6D,0xC7,0x34,
++    0x17,0x2A,0x9C,0x7E,0x28,0x01,0x00,0x67,0x4D,0x03,0x03,0x48,0xC0,0x00,0x42,0x03,
++    0x00,0x33,0x08,0x09,0x31,0x1A,0x31,0x52,0x30,0x42,0x80,0x0F,0xFB,0x4F,0xE3,0x68,
++    0x90,0x6D,0xC7,0x2C,0x17,0x2A,0x9C,0x7E,0x48,0x0B,0xA1,0x0C,0x89,0x04,0x30,0xDA,
++    0x10,0x09,0xC8,0x1C,0xC7,0x34,0xB8,0xFF,0xFB,0xFF,0x4A,0x0B,0x89,0x04,0x30,0xDA,
++    0x10,0x01,0xA0,0x0C,0xC8,0x24,0xC0,0x2C,0xBA,0xFF,0xFF,0xB7,0x48,0xC2,0x00,0x01,
++    0x88,0x01,0x12,0x43,0x48,0xB2,0x18,0x43,0x37,0x57,0xAE,0xC5,0x30,0x1A,0x30,0x42,
++    0x30,0xBA,0xD8,0x23,0xD8,0x2B,0x4A,0xB2,0xC0,0xC8,0x8A,0x04,0x30,0xD2,0x31,0xCA,
++    0x87,0x0F,0xF8,0xDF,0x30,0x01,0x00,0x3F,0x09,0x09,0x30,0xDA,0x30,0x92,0x31,0x42,
++    0x81,0x0F,0xF8,0xB7,0xE7,0xB0,0x93,0xB5,0x17,0x32,0x9D,0xAE,0xC8,0x04,0x10,0x01,
++    0x18,0x01,0x00,0x4F,0x00,0x01,0x00,0x1F,0x82,0x5B,0xE0,0x48,0xE6,0x00,0x92,0x05,
++    0x17,0x42,0x9D,0xCE,0xE6,0x90,0x92,0x95,0x17,0x12,0x9D,0x9E,0xE8,0xC5,0x07,0x00,
++    0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0x48,0xE0,0x06,0x00,0x00,0xD0,0x00,0x01,
++    0x60,0x20,0x02,0x00,0x49,0x32,0x41,0x2A,0x05,0x43,0x9E,0xFF,0x7F,0x04,0x3A,0xF7,
++    0x94,0x15,0x3A,0x00,0x77,0x18,0x06,0xF9,0x04,0xC2,0x3C,0x48,0x74,0x48,0x00,0xCA,
++    0x50,0x01,0xD0,0x5E,0x38,0x90,0x78,0x90,0xD4,0x41,0x40,0x98,0x54,0xE2,0x00,0xD8,
++    0xC6,0xD0,0x4C,0x9B,0x18,0x1A,0x1C,0x5A,0x0B,0x9B,0x3E,0x82,0x40,0x98,0x54,0xCA,
++    0x04,0xD8,0xC4,0xD0,0x44,0x9B,0x18,0x1A,0x18,0x5A,0x00,0x9B,0x3A,0x82,0x93,0x05,
++    0x36,0x10,0x76,0x90,0x0C,0x09,0x00,0x8A,0x48,0x00,0x52,0x9A,0x04,0x00,0xC4,0x00,
++    0x03,0x0B,0x38,0x82,0x96,0x05,0x32,0x10,0x70,0x90,0x0E,0x09,0x00,0x8A,0x54,0x72,
++    0x4C,0x00,0x02,0x00,0x94,0x01,0xC4,0x00,0x03,0x0B,0x38,0x82,0xB3,0x15,0x3B,0x82,
++    0xFB,0x85,0x39,0x82,0x40,0x32,0x48,0x0B,0x10,0x21,0x18,0x8A,0x0B,0x0B,0x38,0x82,
++    0x48,0x1A,0x48,0x43,0x14,0x21,0x18,0x82,0x0B,0x43,0x38,0x82,0x07,0x20,0x28,0xD0,
++    0x68,0x07,0x00,0x07,0x20,0x07,0x00,0x07,0x08,0x07,0x00,0x07,0xAC,0xFD,0x87,0x4D,
++    0xD0,0x94,0x30,0x22,0xF8,0x43,0x80,0x0C,0xF8,0x6B,0xC6,0x64,0x08,0x01,0x80,0x0B,
++    0x00,0x01,0x00,0x8F,0x0A,0x21,0x19,0x0A,0x18,0x99,0xCB,0x48,0x0E,0xD8,0xC2,0x48,
++    0xC8,0x4B,0x4C,0x79,0x80,0x36,0x80,0x83,0xE0,0x90,0xCA,0x64,0xD8,0x64,0xC0,0x4B,
++    0xE0,0x48,0x82,0xCB,0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0x5E,0xC0,0x64,0xC0,0x03,
++    0x80,0x44,0x40,0x01,0x88,0x0E,0x80,0x6D,0xE8,0x85,0xC7,0x44,0x40,0x09,0x88,0x1E,
++    0xC0,0x0C,0x40,0x09,0x8F,0x06,0x38,0xB7,0x00,0x01,0x80,0x34,0x80,0x2C,0xC8,0x44,
++    0xC4,0x0C,0x10,0x0A,0x88,0x96,0x02,0x01,0x30,0x01,0x08,0x01,0x88,0x1C,0x88,0x14,
++    0x1C,0xC9,0x09,0xD8,0x00,0x4F,0x10,0x31,0x18,0x52,0xCA,0x90,0xC2,0x90,0x46,0xBC,
++    0xC4,0xC0,0x41,0x94,0xCA,0xB0,0xE4,0x48,0x90,0x4D,0xD6,0x0C,0x17,0x8A,0x9C,0x96,
++    0xC8,0x0C,0x80,0x17,0xF0,0x6F,0x82,0x24,0x30,0x82,0xC9,0x0C,0x82,0x17,0xF0,0x47,
++    0x30,0x32,0x08,0x01,0x01,0x01,0x00,0x07,0x1A,0x99,0x0B,0xD8,0x02,0x0F,0xE0,0x48,
++    0x91,0x4D,0x16,0x21,0x18,0x52,0xCA,0x90,0xC4,0x90,0xCE,0x93,0x57,0x79,0x80,0xB6,
++    0x12,0x21,0x19,0x52,0xCE,0x90,0xC0,0x98,0x3E,0xF1,0xF8,0xFA,0xDF,0x1C,0xC0,0xD8,
++    0x98,0x1C,0x18,0xE9,0x0E,0xD8,0xC6,0x98,0x14,0x01,0xF0,0xD2,0xDE,0x14,0xC0,0x90,
++    0x92,0x14,0xE0,0x48,0x92,0x4D,0xE6,0x00,0x90,0x05,0xD6,0x44,0x16,0x12,0xC4,0xDE,
++    0xC8,0x44,0xC0,0x1C,0x80,0x17,0xF0,0xE7,0x30,0x3A,0xC8,0x44,0xC0,0x14,0x80,0x17,
++    0xF0,0xBF,0xC8,0x24,0xD8,0x48,0x8E,0x34,0xD0,0x80,0x81,0x2C,0x08,0x01,0x10,0x01,
++    0x00,0x77,0x00,0x01,0x33,0x5A,0x18,0x5A,0xF2,0x5C,0x00,0xD8,0xC8,0xD8,0x04,0x1F,
++    0x04,0x30,0x9A,0xD2,0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0xCE,0xE6,0x48,0x92,0x4D,
++    0x17,0x4A,0x9D,0x76,0x08,0x01,0x10,0x01,0x03,0xE7,0x19,0x99,0x08,0xD8,0x02,0x0F,
++    0xE6,0x48,0x92,0x4D,0x02,0x21,0x19,0x42,0xCC,0x00,0x30,0x22,0xC0,0x00,0x86,0x3C,
++    0xC8,0x03,0x44,0x79,0x80,0xA6,0x07,0x01,0x00,0x2F,0xD9,0x3C,0x34,0xF1,0xF8,0xF2,
++    0xD9,0x34,0x38,0xC9,0xC0,0xB0,0x1F,0x31,0x18,0x1A,0xCA,0xD8,0x0E,0xF8,0xCD,0xD8,
++    0x47,0xFC,0xDA,0xB0,0xAB,0x06,0x10,0xB2,0x95,0xB5,0x35,0xB2,0x37,0xE9,0x08,0xB0,
++    0x20,0x32,0x3B,0x01,0xF8,0xBA,0xF7,0x2C,0x45,0xDC,0xCC,0xF0,0xD0,0x98,0xAF,0x06,
++    0x10,0xDA,0x32,0xB2,0x18,0x72,0xFB,0x5C,0x07,0xB0,0xCB,0xB0,0x22,0x9A,0x03,0x38,
++    0x9A,0x9A,0xE7,0x00,0x90,0x05,0xDE,0x0C,0x16,0xC2,0x9C,0xB6,0xE6,0x48,0x92,0x4D,
++    0xE6,0x90,0x92,0x95,0xC0,0x64,0xC0,0x03,0x15,0x82,0xC4,0xF6,0xC0,0x64,0xC8,0x0C,
++    0xC4,0x03,0x10,0x42,0xC9,0x06,0x38,0xF7,0xC1,0x0C,0x38,0xE7,0xAC,0x85,0x87,0x3D,
++    0x34,0x22,0x00,0x91,0xD4,0x02,0x34,0x22,0x01,0xC1,0xF0,0x02,0x18,0x71,0x80,0x34,
++    0xF0,0x1A,0x9F,0x2C,0xD0,0x00,0x96,0x05,0x1F,0xD1,0xF0,0x1A,0x2B,0x81,0xF8,0x2A,
++    0x32,0xF2,0xDC,0xD8,0x90,0xDD,0xA8,0x24,0xC0,0x2B,0x6F,0x09,0x8D,0x16,0x10,0x04,
++    0x10,0x1C,0x07,0x6F,0x55,0x3C,0x05,0xE8,0xC7,0x68,0x51,0x04,0x07,0x30,0xC4,0x98,
++    0xD9,0x68,0x97,0x6D,0xD0,0xC0,0x90,0x1D,0x84,0x40,0x85,0xD8,0x17,0x04,0x15,0x1C,
++    0x4B,0x81,0x80,0xF6,0xE9,0x2C,0xC0,0x40,0x02,0x28,0xCA,0x00,0xEA,0x34,0xC8,0x00,
++    0x80,0x00,0x94,0x05,0xEF,0x24,0xC0,0x58,0x02,0xE8,0xCA,0xE8,0x37,0x9A,0xC3,0x58,
++    0x80,0xD8,0x94,0xED,0x90,0x01,0x46,0x01,0xD0,0x0E,0x00,0x01,0x00,0x27,0x50,0x9C,
++    0x10,0x1A,0xD4,0x0E,0x00,0x81,0xF0,0x82,0x68,0x01,0xD0,0x0E,0x28,0x01,0x00,0x27,
++    0x55,0x9C,0x12,0x5A,0xD0,0x0E,0x28,0x91,0xF8,0xAA,0xD2,0x2C,0xD0,0x90,0xF0,0xB0,
++    0xD2,0x06,0x10,0x92,0x06,0x98,0xC2,0xB8,0xD2,0x24,0xD8,0x90,0xF0,0x98,0xD0,0x06,
++    0x15,0x92,0xC2,0xF8,0x7E,0xD0,0xCF,0x90,0x18,0x90,0x66,0x90,0x58,0x01,0xD0,0x06,
++    0x12,0xDA,0x02,0xF8,0xC8,0xD8,0x76,0x01,0xD3,0x06,0x10,0xB2,0xCE,0xD8,0x7C,0xF0,
++    0xC6,0x98,0x1F,0xD8,0x60,0xF0,0x48,0x41,0x80,0x0E,0x48,0x49,0x88,0x2E,0x48,0x49,
++    0x8A,0x1E,0x20,0x88,0x63,0x50,0x20,0x88,0x63,0x70,0x30,0x0A,0x8B,0x0C,0x28,0x12,
++    0xCB,0x06,0x30,0x12,0xCC,0x0C,0x10,0x72,0xC8,0x06,0xF0,0x0C,0xDB,0x2C,0x30,0x0A,
++    0xD0,0x48,0x34,0x7A,0x1C,0xCA,0x02,0x58,0xC4,0x48,0x36,0x72,0x19,0x51,0x30,0xCA,
++    0xF3,0x1A,0x07,0xF8,0xCA,0x48,0x1E,0x5A,0x32,0x8A,0xC3,0xC8,0x1B,0x82,0x32,0x12,
++    0x46,0xB8,0xCA,0x00,0x02,0x00,0xC6,0x00,0x36,0x0A,0x03,0x48,0x88,0x1C,0x80,0x17,
++    0xE8,0xBF,0x80,0x14,0xD0,0x24,0xC0,0x0C,0xD8,0x00,0x34,0x0A,0x1C,0x82,0x02,0x10,
++    0xC0,0x00,0x14,0x61,0xF2,0x12,0x05,0x58,0xC2,0x48,0x1E,0x52,0xC3,0x80,0x18,0xAA,
++    0x00,0x07,0x00,0x67,0xCE,0x48,0x07,0x48,0xC0,0x40,0xC8,0x1C,0x80,0x17,0xE8,0x07,
++    0xCB,0x2C,0x08,0x0C,0xCD,0x24,0x08,0x0C,0xCF,0x14,0x08,0x0C,0x10,0x04,0x81,0x3D,
++    0xEF,0x85,0xAF,0xF5,0x30,0x3A,0xC0,0x44,0x60,0xD2,0xCF,0xE0,0x2F,0x31,0x70,0xCA,
++    0x1F,0xAA,0xC2,0x68,0xF5,0x21,0xC9,0x68,0x06,0x90,0xC2,0x90,0x59,0xAA,0xDF,0x81,
++    0xC6,0xB0,0xFE,0x13,0x31,0xB2,0x34,0xDA,0x32,0x3A,0xB8,0x01,0x30,0x12,0xB8,0x0C,
++    0x92,0x01,0xBE,0x01,0x59,0x09,0x88,0x4E,0x01,0x01,0x00,0x17,0xC0,0x0B,0x49,0x79,
++    0x89,0xE6,0x40,0x4C,0x0B,0x0C,0x47,0x5C,0x14,0x1C,0x31,0xE2,0xC1,0x9B,0x89,0x1B,
++    0xC3,0x9B,0x8B,0x1B,0x1B,0x0C,0x35,0x1A,0x19,0x1C,0x27,0x0C,0x23,0x1C,0x0B,0x0C,
++    0x09,0x1C,0x45,0x4C,0x1B,0x0C,0x41,0x4C,0x19,0x0C,0x83,0x03,0x0F,0x09,0x80,0x0B,
++    0x88,0x0B,0xFD,0x8B,0x90,0x0B,0x09,0x01,0x90,0x0B,0x03,0x27,0xA2,0x21,0xE1,0x00,
++    0x93,0x05,0x2E,0x82,0x9B,0xD6,0x2E,0x82,0x94,0xF6,0x03,0x2F,0x1A,0x21,0x19,0xCA,
++    0xC8,0x60,0x08,0x41,0x89,0x04,0x40,0x4C,0x18,0x0C,0x09,0x11,0xF3,0x4A,0x1B,0x0C,
++    0x35,0x62,0xCC,0x0B,0x48,0x09,0x88,0xAE,0x08,0xC1,0x18,0xE1,0xF7,0x0A,0xF3,0x1A,
++    0xD0,0x48,0xAE,0x06,0x14,0x4A,0x92,0x4D,0x30,0x72,0x1C,0xF1,0xF3,0x1A,0x37,0x0A,
++    0xD0,0x48,0xAE,0x06,0x14,0x4A,0x92,0x4D,0xE3,0xDB,0x21,0x8A,0x10,0xCA,0xCC,0x0E,
++    0x0D,0x01,0x88,0x0B,0x09,0xC1,0x18,0x01,0xF7,0x0A,0xF3,0x1A,0xD0,0x48,0xAE,0x06,
++    0x14,0x4A,0x92,0x4D,0x30,0x62,0x0C,0xD1,0x1B,0x11,0xF1,0x0A,0xF6,0x1A,0xD7,0x48,
++    0xAA,0x06,0x10,0x4A,0x24,0x0A,0x93,0x4D,0x30,0x62,0xDC,0x0C,0xC4,0x0B,0xE7,0xDB,
++    0xE4,0xD8,0x12,0xCA,0xC8,0x7E,0xF8,0x8B,0xEE,0xDB,0x01,0xCA,0x28,0x0A,0xCB,0x56,
++    0xD6,0x0B,0x4B,0x41,0x92,0x0E,0xE0,0x48,0x91,0x0B,0xD3,0x0B,0xFC,0x9B,0x10,0xCA,
++    0x92,0x0E,0xE0,0x48,0x91,0x0B,0xD1,0x0B,0x28,0x0A,0xCB,0xA6,0xDF,0x0C,0xC0,0x0B,
++    0xE2,0xDB,0xE4,0xD8,0x10,0xCA,0xCC,0x76,0xCA,0x0B,0x37,0x50,0xE2,0xCB,0x73,0x90,
++    0xF4,0x48,0x12,0x52,0x89,0x0E,0x08,0x01,0x80,0x0B,0x35,0x12,0x09,0x81,0x30,0x02,
++    0xBC,0xFF,0xF7,0xE7,0x00,0xDF,0xD8,0x0C,0xC4,0x0B,0xE7,0xDB,0xE4,0xD8,0x12,0xCA,
++    0xC8,0x1E,0xF8,0x8B,0xEE,0xD3,0x01,0x8A,0x91,0x0B,0x59,0x0C,0x23,0x0C,0x59,0x0C,
++    0x20,0x0C,0x33,0x12,0x30,0x02,0xC9,0x04,0xBC,0xFF,0xF7,0x47,0x03,0x01,0x90,0x03,
++    0xD0,0x03,0x41,0x01,0x80,0x1E,0x00,0x07,0x02,0x3F,0xF1,0x00,0x97,0x03,0xC1,0x03,
++    0x40,0xF9,0x93,0x0E,0xE7,0x00,0x82,0x03,0x43,0x44,0x15,0x04,0x03,0x19,0x80,0x03,
++    0xE4,0xC3,0x83,0x01,0x89,0x03,0xCF,0x03,0xC2,0x8B,0xD1,0x00,0xE0,0x00,0x42,0x11,
++    0xC3,0x2E,0xC8,0x03,0xC2,0x8B,0xD3,0x00,0xE0,0x00,0x42,0x11,0xCF,0x4E,0xC0,0x03,
++    0x40,0x11,0x98,0x36,0xCA,0x0C,0xE0,0x4B,0x10,0x42,0xC4,0x16,0x07,0x01,0x80,0x03,
++    0x89,0x03,0xC7,0x83,0x8B,0x03,0xC1,0x83,0x8F,0x03,0xEB,0xF5,0xAC,0x85,0x37,0xE2,
++    0x34,0x2A,0xAB,0x01,0x4A,0x5C,0x27,0xD8,0x67,0xE0,0x40,0xF9,0x88,0x0E,0x00,0x01,
++    0xE9,0x85,0x1F,0x21,0x1B,0xC2,0x5A,0xFA,0xC6,0x00,0xC4,0x00,0x1A,0x31,0x18,0xCA,
++    0xC3,0x48,0x54,0xE2,0xD4,0x21,0xC1,0x50,0x0A,0xA1,0xF0,0x0A,0x48,0x01,0xD0,0x06,
++    0x10,0x4A,0x1A,0xB1,0xF0,0x1A,0x5E,0x01,0xD2,0x06,0x10,0xDA,0xC3,0x48,0x5E,0xB2,
++    0x10,0xCA,0x9C,0x06,0x08,0x01,0x30,0x71,0x44,0x9C,0xF8,0x32,0xD8,0xD8,0xAC,0x06,
++    0x10,0xDA,0x32,0x81,0x44,0x94,0xFA,0x32,0xD8,0x90,0xAC,0x06,0x14,0x92,0xC2,0xD0,
++    0x11,0x12,0x9D,0x0E,0xC8,0x33,0x74,0x09,0x8B,0x26,0xE0,0x5B,0xCA,0x3B,0xF6,0xD8,
++    0x10,0xFA,0xDC,0xBE,0x70,0x09,0x88,0x3E,0xDC,0x5B,0x11,0x5A,0x9E,0x26,0xC0,0x03,
++    0x40,0xF1,0xC0,0x0E,0x40,0x51,0x90,0x6E,0x70,0x09,0x88,0x1E,0x30,0x02,0x5B,0x04,
++    0x40,0xC1,0x98,0x3E,0x70,0x09,0x88,0x16,0x04,0x00,0x13,0x82,0xCD,0x16,0x00,0x00,
++    0x10,0x82,0xC4,0x0E,0x07,0x01,0xE8,0x85,0x07,0x09,0xE8,0x85,0xAC,0xFD,0x87,0x5D,
++    0x30,0xB2,0x0C,0x01,0x28,0x01,0x00,0x01,0x80,0x14,0xC0,0xA4,0xF8,0x23,0x06,0x01,
++    0x30,0x22,0x84,0x34,0x00,0x27,0xD0,0x64,0x02,0xF9,0xA7,0x82,0xE6,0x48,0x92,0x4D,
++    0x17,0x0A,0x9D,0xC6,0xD3,0x74,0x28,0x92,0xC0,0x26,0xC0,0x74,0x83,0x24,0x30,0x82,
++    0x80,0x1C,0x00,0x1F,0x30,0x82,0x83,0x24,0xC0,0x74,0x80,0x1C,0x00,0x01,0x80,0x2C,
++    0x00,0xD7,0x1A,0x01,0x03,0xB7,0x32,0x02,0x06,0xC2,0x3E,0x00,0x8A,0x86,0x42,0x32,
++    0x80,0x3C,0x00,0x01,0xD0,0xA4,0xF0,0x5C,0xF8,0x93,0x90,0x54,0x33,0xD2,0x18,0x12,
++    0x05,0xB8,0xCA,0xD0,0x90,0x4C,0x00,0x6F,0xF6,0x34,0x00,0x32,0x38,0x90,0x8F,0x3E,
++    0xF2,0x4C,0x00,0x38,0xD8,0xB2,0xFF,0x3C,0x10,0xF2,0x95,0x0E,0xB0,0x3C,0x30,0x0A,
++    0xE6,0x00,0x92,0x05,0xD4,0x54,0x10,0x12,0xC1,0x76,0x77,0xBA,0x02,0x01,0x00,0x78,
++    0xB8,0x44,0x00,0x87,0x36,0x3A,0x03,0x3A,0x38,0xF8,0x8F,0x56,0x33,0x3A,0x18,0x3A,
++    0xD3,0x5C,0x00,0xF8,0xC0,0xF8,0xD5,0x44,0xD5,0xFA,0x15,0xBA,0xC1,0x0E,0x30,0xF2,
++    0x32,0x2A,0xE0,0x00,0x93,0x05,0x2E,0x82,0x9C,0x66,0x17,0xEA,0x88,0xA6,0xC0,0x14,
++    0xC8,0x00,0x84,0x14,0xC2,0x2C,0xE0,0x00,0x90,0x05,0x86,0x2C,0xC2,0x64,0xA0,0x2A,
++    0x31,0x09,0x30,0x82,0xD4,0x34,0x00,0x42,0x1C,0x82,0x90,0x05,0x85,0x34,0x00,0x72,
++    0x30,0x02,0x1B,0x32,0x94,0x85,0x35,0x22,0xD0,0x24,0xC0,0x2C,0x10,0x82,0x84,0x1E,
++    0xE6,0xD8,0x92,0xDD,0x2D,0x9A,0x9B,0x36,0xD0,0x24,0xC0,0x2C,0x15,0x82,0x9C,0x06,
++    0xC0,0x14,0x80,0x3C,0x10,0x01,0x00,0x01,0x0B,0x01,0x30,0x5A,0x80,0xCB,0x18,0x01,
++    0x0C,0x01,0x30,0x62,0x30,0x4A,0xE3,0x4A,0x02,0x0F,0xE0,0x48,0x90,0x4D,0x36,0xEA,
++    0x07,0x6A,0x3E,0x68,0x88,0xCE,0xEF,0x1C,0x10,0x4A,0x9D,0xFE,0x40,0x01,0x88,0x8E,
++    0x08,0xF9,0x07,0x5F,0xD0,0x64,0xE0,0x9A,0x28,0x9A,0x93,0x1E,0xD0,0xA4,0xF8,0x93,
++    0x10,0x12,0xC4,0x0E,0xD0,0x64,0xA0,0x8A,0xE6,0x00,0x92,0x05,0x17,0x02,0x9D,0x8E,
++    0x87,0x7D,0xE8,0x85,0xF6,0x00,0x92,0x05,0x30,0x4A,0xE3,0x4A,0x2D,0x09,0x30,0x62,
++    0x00,0x6F,0x01,0x00,0x70,0x30,0x03,0x00,0xF8,0xFF,0x07,0x00,0x33,0x6A,0x18,0x2A,
++    0xFB,0x5C,0x00,0x70,0xCA,0xB0,0x07,0x38,0xDD,0xAA,0xC7,0x50,0x2C,0x09,0x00,0x6A,
++    0x1D,0xEA,0x90,0x5D,0x31,0x72,0xA3,0x8A,0xED,0x3C,0x10,0x52,0x98,0x16,0x28,0x11,
++    0x30,0x62,0x05,0xA7,0xFA,0x74,0xE0,0x28,0x10,0xEA,0x9D,0x6E,0x90,0x3C,0x08,0x01,
++    0x00,0x27,0xF8,0x64,0xE3,0xAA,0xA3,0xEA,0xE6,0x48,0x92,0x4D,0x17,0x0A,0x9D,0xC6,
++    0xE0,0x8A,0x29,0x09,0x30,0x62,0x05,0x17,0x90,0x45,0x2F,0x01,0xA3,0xAA,0x31,0x2A,
++    0x6D,0x01,0x80,0x2E,0x33,0x6A,0x18,0x2A,0xFB,0x5C,0x00,0x70,0xCA,0xB0,0x07,0x38,
++    0xDA,0xAA,0xDF,0x90,0x2C,0x09,0x00,0x6A,0x1B,0x5A,0x35,0x6A,0xE2,0x4A,0xE1,0x48,
++    0xA4,0x4A,0x39,0xAF,0xAC,0xC5,0x37,0x22,0xFC,0x73,0x5E,0xAA,0x36,0x02,0xC3,0x00,
++    0x31,0x32,0x34,0xAA,0x38,0x21,0x31,0x62,0x1A,0xEA,0xA3,0x01,0x13,0x01,0x20,0x2A,
++    0xC0,0x68,0x07,0xF7,0xC0,0x1B,0x58,0x79,0x86,0xD6,0xC8,0x1B,0x30,0xD8,0xA0,0x3E,
++    0x18,0xF9,0x8F,0x1B,0x8E,0x1B,0xC2,0x1B,0xE5,0x3B,0x15,0xDA,0xC6,0x06,0x88,0x13,
++    0xCA,0x1B,0x36,0xD8,0x76,0xD8,0x8A,0x1B,0x58,0x01,0x80,0x0E,0xF6,0xD8,0x8A,0x1B,
++    0xC8,0x1B,0x5E,0x01,0x8A,0x26,0xC0,0x1B,0x44,0xD8,0x04,0xD8,0x84,0x1B,0x82,0x13,
++    0x84,0x21,0x11,0x2A,0xC0,0xF6,0x06,0x01,0x84,0x04,0xB8,0x53,0x30,0x82,0x03,0x8F,
++    0xC5,0x13,0x10,0x92,0x96,0x5E,0xC0,0x13,0xE2,0x3B,0x35,0x98,0x75,0xD8,0x12,0xDA,
++    0xCC,0x2E,0xC0,0x13,0x50,0x01,0x81,0x16,0x00,0x09,0x80,0x04,0x00,0x27,0x10,0x01,
++    0x81,0x13,0x84,0x21,0x17,0x2A,0xC4,0x5E,0xC0,0x04,0x40,0x01,0x83,0x76,0x31,0x92,
++    0x36,0x5A,0x98,0x01,0x00,0x47,0x01,0x01,0x80,0x83,0xC4,0x83,0x11,0x82,0x95,0x16,
++    0xC2,0x83,0x36,0x38,0xE3,0x03,0x75,0xF8,0x10,0x3A,0xCC,0xE6,0x04,0x09,0x80,0x83,
++    0xFA,0x43,0xE4,0x00,0xB8,0x43,0x3C,0x71,0xF8,0xBA,0x7E,0x01,0xD0,0x16,0x00,0x01,
++    0x08,0x84,0x06,0x27,0x54,0xC4,0x10,0x3A,0xE8,0x0E,0x50,0xC4,0x08,0x84,0x3E,0x81,
++    0xF8,0xBA,0x7E,0x01,0xD0,0x16,0x00,0x01,0x10,0x84,0x00,0x27,0x54,0xC4,0x12,0x3A,
++    0xEA,0x0E,0x50,0xC4,0x11,0x84,0x90,0x21,0x16,0xAA,0xC4,0xA6,0xF8,0x43,0x40,0x01,
++    0x88,0x36,0x58,0x44,0x16,0xE9,0x03,0x90,0x10,0x82,0x94,0x0E,0xE0,0x00,0x1A,0x44,
++    0xF8,0x43,0x44,0x01,0x80,0xCE,0x10,0x01,0x03,0x01,0x28,0x99,0x0E,0x68,0xFB,0x63,
++    0x01,0x6F,0x18,0x21,0x1B,0x1A,0x22,0x1A,0xC8,0xD8,0xD2,0xF3,0x70,0x09,0x88,0x26,
++    0xC8,0xDB,0x5E,0x19,0x8A,0x0E,0xE0,0x90,0x92,0x95,0xE6,0x00,0x94,0x05,0x16,0x22,
++    0xC0,0x7E,0x57,0x01,0x88,0x0E,0x00,0x01,0x1F,0x44,0xE8,0xC5,0xAC,0x85,0x87,0x3D,
++    0x30,0x2A,0x30,0x62,0x41,0x12,0xC2,0x40,0x08,0x29,0xEE,0x4A,0x4B,0x29,0x80,0xDE,
++    0x4B,0x02,0xC2,0x70,0xEB,0x48,0xC4,0x48,0x89,0x1C,0x48,0xF2,0x8B,0x61,0xC0,0x48,
++    0x88,0x14,0x08,0x01,0x10,0xF9,0x1F,0x79,0x03,0x3F,0xA0,0x92,0xC8,0x3B,0x7E,0x01,
++    0x88,0x06,0x80,0x1B,0xE6,0x48,0x92,0x4D,0x87,0x21,0xF9,0x3B,0x17,0x7A,0xC4,0xA6,
++    0x00,0x01,0x80,0x34,0xF8,0x03,0x41,0x01,0x80,0xCE,0xB2,0x04,0x31,0x0A,0x31,0x42,
++    0x58,0x2D,0xD0,0x14,0xBA,0xFF,0xDF,0x97,0x80,0x34,0xC0,0x34,0x40,0x01,0x88,0x76,
++    0x30,0x01,0x00,0x47,0x31,0x5A,0x31,0x92,0x08,0xF9,0x07,0x09,0xA7,0x04,0xB8,0xFF,
++    0xE3,0x47,0xE7,0xB0,0x91,0xB5,0xFF,0x03,0x17,0x82,0xC5,0x9E,0x00,0xFF,0xC1,0x34,
++    0x40,0x09,0x88,0x96,0xC1,0xB3,0x31,0x1A,0x30,0x52,0x09,0x01,0x37,0x82,0xB9,0xFF,
++    0xE8,0x2F,0x46,0x01,0x80,0x0E,0x00,0x01,0x00,0x07,0x00,0x09,0x30,0x5A,0x11,0x01,
++    0x30,0x8A,0xA1,0x04,0xBE,0xFF,0xE7,0x6F,0x00,0x4F,0xA1,0x04,0xFB,0x3B,0x31,0x5A,
++    0xE9,0xD3,0x30,0xDA,0xC8,0x1C,0xC0,0x14,0xB8,0xFF,0xF7,0x47,0x38,0x01,0x00,0xDF,
++    0xC6,0x1C,0xE8,0x02,0x40,0xF9,0x87,0x16,0xE0,0x82,0x81,0x24,0x07,0x0F,0x00,0xF9,
++    0x81,0x24,0x30,0x1A,0x31,0x52,0x31,0xCA,0xC7,0x24,0xB8,0xFF,0xE8,0xFF,0x44,0x01,
++    0x80,0x0E,0x00,0x01,0x00,0x07,0x00,0x09,0x31,0x5A,0x31,0xD2,0xA0,0x04,0xC8,0x24,
++    0xBD,0xFF,0xE7,0x3F,0xE7,0xF8,0x93,0xFD,0xFD,0x03,0x11,0xC2,0xC1,0x06,0x37,0x0A,
++    0x30,0x42,0xD1,0x34,0xBE,0xFF,0xF7,0xB7,0x20,0xCF,0x04,0x01,0x38,0x82,0x03,0x00,
++    0x70,0x30,0x03,0x00,0x48,0xE0,0x06,0x00,0xAE,0xFD,0x87,0x5D,0xC6,0xAC,0xDA,0x03,
++    0x82,0xCC,0xC1,0xAC,0xD9,0x03,0x84,0xC4,0x01,0x09,0x58,0x45,0x81,0xC3,0xC0,0xC4,
++    0xE2,0x00,0x82,0xC3,0xC4,0xC4,0x81,0xC3,0xC2,0xC4,0xF1,0x00,0x82,0xC3,0xC6,0xAC,
++    0x82,0x01,0x87,0x54,0xC0,0x0B,0x00,0x21,0x1A,0x0A,0xC0,0x54,0x82,0x0B,0xC0,0xAC,
++    0xCA,0x03,0x42,0x00,0x80,0xD4,0x09,0x01,0x40,0xB5,0x31,0x52,0x00,0x36,0x00,0x01,
++    0x82,0xF4,0xC0,0xAC,0xCC,0xB4,0x82,0x01,0x82,0x4C,0xC2,0x74,0x92,0x05,0x82,0x44,
++    0xC2,0x6C,0x92,0x05,0x82,0x3C,0xC2,0xAC,0x82,0x01,0x86,0x34,0x4B,0x11,0x80,0xBE,
++    0x10,0x01,0x00,0x01,0x4C,0x45,0xB1,0x4A,0x8F,0x2C,0x4A,0xF2,0xB2,0x4A,0x8C,0x24,
++    0x48,0xE2,0xEF,0x48,0xB2,0x4A,0x8C,0x1C,0x04,0x08,0xC4,0x48,0x91,0x4D,0x66,0x9D,
++    0xDB,0x74,0xA2,0x1A,0x62,0x85,0xD9,0x6C,0xA2,0x1A,0xDB,0x24,0x9A,0x34,0xD9,0x1C,
++    0x9A,0x2C,0xD9,0x2C,0x98,0x24,0x41,0x09,0x89,0x5E,0xD8,0x34,0x12,0xDA,0x92,0xDD,
++    0x99,0x34,0xD9,0x2C,0x12,0xDA,0x92,0xDD,0x99,0x2C,0xD9,0x24,0x12,0xDA,0x92,0xDD,
++    0x9A,0x24,0xD9,0x5C,0x32,0xE2,0xDC,0x64,0x9A,0x5C,0xD9,0x3C,0xE1,0x44,0xEA,0x2C,
++    0xCA,0xD8,0x92,0xDD,0xEB,0x34,0xC9,0x20,0x91,0x25,0xF3,0x24,0xED,0x5C,0xC9,0x68,
++    0xA8,0x5C,0x59,0x01,0xD9,0x86,0xEB,0xCC,0x13,0x5A,0xD5,0x6E,0x63,0x01,0xD8,0x5E,
++    0xED,0xC4,0x11,0x62,0xD1,0x46,0xEB,0x5C,0xC5,0x6B,0x49,0x68,0x8B,0x06,0x32,0x2A,
++    0x3F,0x01,0xF8,0x7A,0xEB,0x24,0x01,0x68,0x23,0x62,0x35,0x32,0x2B,0x01,0xF8,0xAA,
++    0xF5,0xD4,0x11,0xAA,0xEA,0xC6,0xF2,0xB4,0x71,0x09,0x88,0x16,0xD9,0xF0,0x93,0xB5,
++    0xB2,0x9C,0xF8,0x5C,0x35,0x01,0xF8,0xF2,0x10,0x72,0xDD,0x06,0x37,0xAA,0x81,0x68,
++    0x01,0x68,0x33,0x7A,0xF3,0x9C,0x10,0x6A,0x12,0xAA,0xE5,0x2E,0x6B,0x9D,0xA1,0x62,
++    0x6B,0x85,0xA1,0x5A,0x01,0xA8,0x72,0xB5,0xC9,0x68,0xE5,0x72,0xE1,0xB0,0xA3,0x72,
++    0xEB,0xF4,0xE0,0x68,0x90,0x6D,0xAF,0xF4,0xF5,0x9C,0x10,0xBA,0xD1,0xBE,0x05,0x9F,
++    0x09,0xEF,0x6A,0x9D,0xA1,0x62,0x6B,0x85,0xA2,0x5A,0x03,0xA8,0x75,0xB5,0xC9,0x68,
++    0xE3,0x72,0xE1,0xB0,0xA0,0x72,0xE9,0xF4,0xE7,0x68,0x93,0x6D,0xAD,0xF4,0x38,0x37,
++    0xE9,0x5C,0xC1,0x6B,0x48,0x68,0x6D,0x19,0x8A,0x6E,0x00,0xB0,0x7F,0xB5,0xC9,0xB0,
++    0xE0,0xB2,0x71,0x09,0xC2,0x3E,0xC0,0x64,0x08,0x01,0xC6,0x03,0x1A,0x42,0xC8,0x64,
++    0x82,0x43,0x80,0x7D,0xE8,0x85,0x6F,0x11,0x89,0x56,0x68,0x9D,0xA1,0x62,0x63,0x85,
++    0xA2,0x1A,0x03,0x98,0x4A,0xB5,0xC1,0xC8,0xE2,0x5A,0xE0,0xD8,0xA0,0x5A,0x00,0x1F,
++    0xCE,0x34,0xCA,0x4B,0x4F,0x51,0x90,0x66,0xE6,0x00,0x92,0x05,0x40,0x11,0x90,0x06,
++    0x3A,0xD7,0xE2,0x90,0x90,0x95,0x56,0x21,0x92,0x06,0x38,0x57,0x01,0x01,0x80,0x64,
++    0xC0,0xB4,0x42,0x09,0x88,0xF6,0x03,0x01,0x80,0x7C,0x01,0x01,0x81,0x74,0xC9,0x7C,
++    0x42,0xB5,0x01,0x48,0xC2,0x40,0x80,0x14,0xC1,0x74,0xC9,0x7C,0x02,0x00,0xC4,0x00,
++    0x91,0x05,0x86,0x4C,0xCA,0x74,0xC1,0x14,0xE0,0x2A,0x6A,0x09,0xC1,0x26,0xC0,0x64,
++    0xE6,0x00,0x92,0x05,0x87,0x64,0x01,0x8F,0xC0,0x74,0x41,0x09,0x89,0x16,0xC0,0x7C,
++    0x47,0x01,0x88,0xC6,0x08,0x81,0x41,0x45,0x83,0x17,0xC0,0x77,0xC0,0x6C,0x82,0x3C,
++    0xC0,0x74,0x82,0x34,0xC0,0x5C,0x82,0x0C,0xC0,0x64,0x82,0x04,0xC4,0x7C,0xE1,0x00,
++    0x3C,0x00,0x7C,0x00,0x50,0x5A,0xB4,0xA2,0xE8,0x98,0xB0,0xCA,0x31,0x62,0x74,0x45,
++    0xB1,0x8A,0xC1,0x7C,0xB0,0x82,0x80,0x24,0xC0,0x7C,0xB1,0xC2,0x81,0x1C,0xD0,0x7C,
++    0xB0,0x82,0x85,0x14,0xC0,0x74,0x41,0x09,0x88,0x5E,0xC0,0x24,0x12,0x02,0x92,0x05,
++    0x80,0x24,0xC0,0x1C,0x12,0x02,0x92,0x05,0x80,0x1C,0xC0,0x14,0x12,0x02,0x92,0x05,
++    0x80,0x14,0x00,0x01,0x83,0x2C,0xE0,0x68,0xAD,0xF4,0x01,0x9F,0x40,0x61,0x98,0x66,
++    0xC8,0x24,0xC0,0x34,0xD2,0x4C,0xD1,0x00,0x4C,0x9D,0xA1,0x42,0xC8,0x1C,0xC0,0x3C,
++    0xD2,0x4C,0xD1,0x00,0x4C,0x85,0xA1,0x42,0x00,0x47,0x15,0x01,0xDC,0x0C,0x00,0x28,
++    0xF0,0xD2,0x5C,0x45,0x88,0xD2,0x12,0x01,0x90,0x6C,0xD1,0x3C,0x92,0x95,0x92,0x0C,
++    0xD2,0x34,0x90,0x95,0x91,0x04,0xD2,0x6C,0x50,0x09,0x88,0x3E,0x12,0x12,0x93,0xA5,
++    0x32,0x12,0x13,0x92,0x94,0x95,0x32,0xA2,0x12,0x4A,0x92,0x4D,0xD2,0x0C,0xDA,0x04,
++    0xF0,0x0C,0x00,0x07,0x01,0xEF,0xB4,0x1C,0xF1,0x04,0xB0,0x5C,0x01,0x70,0xB2,0xFC,
++    0x22,0x12,0x93,0x95,0xCA,0xD8,0x90,0xDD,0xF9,0x1C,0xF1,0xFC,0xC9,0xB0,0xB7,0x1C,
++    0xF3,0x5C,0xC1,0xB0,0xB0,0x5C,0x51,0x01,0xD9,0xBE,0xF0,0xCC,0x10,0x92,0xD5,0xA6,
++    0x58,0x01,0xD8,0x96,0xF5,0xC4,0x11,0x9A,0xD1,0x7E,0xF8,0x1C,0x35,0x01,0xF8,0xF2,
++    0xF9,0x5C,0xC1,0xFB,0x48,0xF8,0x8D,0x46,0xFD,0xD4,0x11,0xF2,0xE8,0x2E,0x78,0x45,
++    0xCD,0xFA,0xCB,0xF0,0x7B,0x45,0x88,0xF2,0x39,0xD7,0xD6,0x6C,0xE6,0x90,0x92,0x95,
++    0x91,0x6C,0xD1,0x6C,0x55,0x11,0x98,0xF6,0x41,0x01,0x80,0xF6,0xF2,0x10,0xF2,0x4C,
++    0x00,0x90,0x5C,0x45,0xC7,0xD2,0xD4,0xB3,0xCC,0xDA,0xCA,0xB0,0x11,0xF2,0x94,0x86,
++    0xD0,0x2C,0x50,0x09,0x88,0x8E,0xD1,0x24,0xC1,0x34,0xD8,0x4C,0xD1,0x00,0x54,0x9D,
++    0xA0,0x82,0xDE,0x1C,0xD1,0x3C,0xE8,0x4C,0xD1,0x90,0x5E,0x85,0xA8,0xD2,0xEA,0x14,
++    0xDA,0x04,0xD8,0xE8,0x36,0x1A,0xD3,0x90,0x90,0x95,0xDA,0x00,0x93,0x1D,0xD2,0x40,
++    0x2C,0x01,0x38,0x01,0x50,0x01,0xD8,0x56,0xF5,0xCC,0x11,0x92,0xD0,0x3E,0x58,0x01,
++    0xD9,0x2E,0xF0,0xC4,0x10,0x9A,0xD5,0x16,0xC1,0x33,0x18,0xF2,0x83,0x33,0x20,0x12,
++    0x90,0x95,0xCA,0xD8,0x92,0xDD,0xC2,0x00,0xE7,0x68,0x93,0x6D,0x6F,0x11,0xC8,0x4E,
++    0x04,0xE7,0x10,0x9A,0x90,0x0E,0x10,0x09,0x90,0x2C,0xD8,0x24,0xD6,0x34,0xC0,0x90,
++    0x90,0x95,0x96,0x34,0xD8,0x1C,0xD0,0x3C,0xC6,0x90,0x96,0x95,0x90,0x3C,0xD0,0x14,
++    0xDA,0x0C,0x00,0x90,0xC0,0x90,0x96,0x0C,0xD8,0x14,0xD0,0x04,0xC0,0x90,0x96,0x04,
++    0xE6,0x00,0x92,0x05,0xD4,0xF4,0x11,0x82,0x92,0x06,0x38,0x3F,0xC2,0x74,0xE1,0x00,
++    0x91,0x05,0x86,0x74,0xC0,0x74,0x41,0x11,0x97,0x06,0x30,0xAF,0xC2,0x7C,0xE1,0x00,
++    0x91,0x05,0x86,0x7C,0xC0,0x7C,0x41,0x21,0x97,0x06,0x30,0x37,0x00,0x0F,0x00,0x41,
++    0x81,0x64,0xC1,0x64,0x41,0x41,0x88,0xD6,0x10,0x01,0x00,0x01,0x58,0x8A,0xE8,0xC8,
++    0xB4,0xF2,0xB4,0x7A,0x31,0x8A,0x31,0xDA,0x40,0x09,0x88,0x1E,0x12,0x4A,0x92,0x4D,
++    0x12,0xDA,0x92,0xDD,0xE7,0x6C,0xC2,0x18,0x92,0xDD,0xE2,0x74,0xC2,0x08,0x93,0x65,
++    0x04,0x08,0xC4,0x48,0x90,0x4D,0x5E,0x01,0xD9,0x76,0xE8,0xCC,0x10,0x5A,0xD5,0x5E,
++    0x60,0x01,0xD8,0x4E,0xED,0xC4,0x11,0x62,0xD1,0x36,0x68,0x9D,0xA1,0x62,0x63,0x85,
++    0xA0,0x1A,0x03,0x3F,0x70,0xF2,0x06,0x00,0x62,0x9D,0xD9,0x74,0xA1,0x1A,0x63,0x85,
++    0xDB,0x6C,0xA2,0x1A,0xE6,0x00,0x92,0x05,0x46,0x11,0x98,0x9E,0xE6,0x90,0x92,0x95,
++    0x56,0x21,0x98,0x56,0x58,0x85,0xD9,0xC3,0xA8,0xC3,0xC0,0xC3,0x90,0xC3,0x00,0x01,
++    0x81,0xFC,0x58,0x85,0xD8,0xC3,0xA8,0xC3,0xC0,0xC3,0x90,0xC3,0x00,0x01,0x80,0xE4,
++    0x30,0x3A,0x80,0xEC,0xC4,0xAC,0xCA,0x03,0x80,0xD4,0x01,0x01,0x0E,0x01,0x00,0x18,
++    0x54,0xA5,0xC0,0xD0,0x32,0xA2,0x04,0x20,0xC6,0x10,0x93,0x95,0x6D,0x9D,0xE1,0x72,
++    0x33,0x2A,0xA3,0x72,0x6D,0x85,0xE1,0x6A,0x32,0x12,0xC3,0x90,0x8A,0xAB,0xE0,0x48,
++    0x90,0x4D,0x4E,0x19,0x98,0x86,0x47,0x09,0x80,0x0E,0x40,0x19,0x88,0x66,0x60,0xA5,
++    0xE3,0x0A,0x37,0x12,0xCB,0x93,0x30,0x2A,0xC7,0x6B,0xA5,0x2A,0x34,0x1A,0xCB,0xE3,
++    0x8C,0xE3,0x80,0xCB,0x34,0x0A,0x8B,0x53,0x09,0x09,0x88,0x0C,0x09,0x01,0x88,0x74,
++    0xD3,0x74,0x31,0x0A,0xE1,0x4A,0xDC,0x74,0x36,0x12,0xC3,0x90,0xCA,0x9B,0xC0,0xAB,
++    0xC9,0x93,0x92,0x14,0xD0,0x74,0x51,0x01,0x88,0x16,0x41,0x01,0x80,0x0E,0x40,0x19,
++    0x8D,0x5E,0x10,0x4A,0x98,0x4E,0x10,0x09,0x90,0x04,0x41,0x01,0x8A,0x16,0xF0,0x10,
++    0x90,0x0C,0x01,0xF7,0x11,0x09,0x90,0x0C,0x00,0xDF,0x40,0x09,0x80,0x0E,0x40,0x11,
++    0x8D,0x5E,0x10,0x4A,0xC0,0x4E,0x10,0x09,0x90,0x04,0x41,0x09,0x8C,0x16,0xF0,0x10,
++    0x90,0x0C,0x01,0x77,0x11,0x09,0x90,0x0C,0x00,0x5F,0x10,0x01,0x90,0x04,0x01,0x47,
++    0x11,0x09,0x90,0x04,0x40,0x11,0x90,0x16,0xF1,0x90,0x94,0x0C,0x00,0x0F,0x10,0x09,
++    0x90,0x0C,0x41,0x01,0x80,0x0E,0x40,0x19,0x8D,0x0E,0x10,0x4A,0x90,0x2E,0x40,0x09,
++    0x80,0x0E,0x40,0x11,0x8D,0x26,0x10,0x4A,0xC0,0x16,0x10,0x09,0x94,0x54,0x01,0x8F,
++    0x11,0x01,0x90,0x54,0x01,0x77,0xF4,0xC4,0x33,0x12,0x19,0x92,0xF1,0xA4,0x92,0xE4,
++    0xC9,0x90,0xF4,0xEC,0xC9,0x90,0x94,0x5C,0xD0,0x5C,0xC1,0x93,0x92,0xDC,0x31,0x90,
++    0xA1,0xCE,0xD1,0xE4,0xF2,0xA4,0x02,0x90,0xC9,0x90,0xF4,0x3C,0x04,0xB0,0xCB,0x90,
++    0x35,0x39,0x09,0xB0,0xC8,0xB0,0x14,0xE1,0xF1,0x92,0xF5,0xD4,0x10,0x92,0xD5,0x26,
++    0xF0,0x64,0x71,0x41,0x88,0xB6,0x50,0x01,0xD9,0xA6,0xF0,0xDC,0x48,0xB0,0x87,0x06,
++    0x80,0x90,0xF2,0xE4,0xC0,0xB0,0xB5,0xE4,0xF2,0x3C,0x19,0xB2,0xC8,0xB8,0xF7,0xEC,
++    0x1C,0x12,0xCB,0x90,0x90,0xEC,0xD0,0xFC,0xE4,0x90,0x92,0x95,0x91,0xFC,0xD0,0xDC,
++    0x48,0x90,0x8E,0xEE,0xD0,0x4C,0xF2,0xF4,0xD5,0x93,0x12,0x92,0xC1,0x2E,0xD0,0xDC,
++    0x31,0x01,0x1E,0x92,0xF1,0x5C,0x81,0x93,0x01,0x47,0xD0,0xDC,0x31,0x01,0x1A,0x92,
++    0xF1,0x5C,0x81,0x93,0x01,0x17,0xD0,0x04,0x50,0x09,0x80,0x4E,0xD0,0x04,0x51,0x09,
++    0x8A,0x36,0xD0,0x6C,0x10,0xA2,0x84,0x1E,0xD5,0x0C,0xC1,0x10,0x95,0xA5,0x3A,0x57,
++    0x10,0x4A,0x8D,0xDE,0xD4,0x14,0x11,0x9A,0x89,0xC6,0xC8,0x74,0xE6,0x48,0x92,0x4D,
++    0x89,0x74,0xC9,0x74,0x48,0x11,0x90,0x06,0x3A,0x97,0xE2,0x00,0x90,0x05,0x46,0x21,
++    0x91,0x06,0x38,0x1F,0xC6,0x34,0xCA,0x03,0x42,0x01,0x88,0x5E,0xC9,0xAC,0x8A,0x01,
++    0xE0,0x43,0x36,0x10,0xAA,0x36,0x31,0x00,0x71,0x00,0x04,0x27,0xD0,0x54,0x51,0x01,
++    0x8D,0x5E,0x10,0x4A,0xCA,0x16,0xF0,0x48,0x90,0x4D,0x06,0x1F,0x10,0x4A,0x95,0x0E,
++    0xE6,0x48,0x92,0x4D,0x11,0x09,0x90,0x54,0x01,0x67,0xD0,0x14,0x10,0x9A,0xCC,0x16,
++    0xF6,0xD8,0x92,0xDD,0x01,0x27,0xD0,0x14,0x10,0x9A,0x94,0x0E,0xE6,0xD8,0x92,0xDD,
++    0x11,0x01,0x90,0x54,0x91,0x55,0x92,0x3C,0x97,0xE5,0x72,0xFA,0xD4,0x3C,0xC9,0x90,
++    0x93,0xEC,0x39,0x47,0x02,0x01,0xD0,0xAC,0x6C,0x94,0x16,0x12,0x9A,0xD6,0xC0,0xAC,
++    0xE8,0x4B,0x70,0x04,0x10,0x42,0x9C,0x26,0xC4,0x4C,0xD2,0x03,0xF6,0x00,0x94,0x05,
++    0x02,0x1F,0xC0,0x4C,0xD4,0x03,0xE4,0x00,0x90,0x05,0xCE,0xFC,0x10,0x0A,0x9C,0x4E,
++    0xC0,0xAC,0x0A,0x01,0xBA,0x0B,0xC0,0x54,0x08,0xD9,0xC7,0x03,0x02,0x42,0xC8,0x54,
++    0x82,0x43,0x28,0x37,0x27,0x01,0x28,0xF9,0xA8,0x09,0x60,0x01,0x8A,0x56,0xC0,0x44,
++    0xC8,0xC4,0xB9,0x9C,0xD2,0x34,0x4A,0x93,0x92,0x94,0xD0,0x74,0x5A,0x3A,0x07,0x90,
++    0xF0,0xF2,0x04,0x57,0xC1,0x3C,0xCA,0xCC,0xD0,0xEC,0x90,0x9C,0xD4,0x34,0x4A,0x93,
++    0x92,0x94,0xD0,0x6C,0x5A,0x12,0x07,0x90,0xF0,0xF2,0x44,0x01,0x82,0x16,0xF0,0x48,
++    0x10,0x42,0x8C,0x8E,0xD0,0x74,0x92,0x04,0x91,0x05,0x36,0x0A,0xDA,0x6C,0xD2,0x5C,
++    0xBB,0xEF,0xD7,0xA7,0x35,0x4A,0x11,0x42,0xE8,0x0E,0x30,0x42,0x00,0x17,0x40,0x01,
++    0xD0,0x06,0x00,0x01,0xC8,0x30,0x04,0x07,0xB0,0x01,0xC4,0x9C,0xC8,0xE4,0x10,0x00,
++    0x86,0x0F,0xE8,0x27,0xCC,0x94,0xC8,0x00,0x18,0x42,0x42,0x01,0xD0,0x06,0x00,0x01,
++    0xA0,0x00,0x60,0x01,0x8A,0x7E,0xC8,0x34,0x54,0x4C,0x10,0x0A,0xD0,0x06,0x30,0x42,
++    0xC8,0xAC,0x12,0x31,0xFA,0x4B,0x18,0x8A,0xD4,0xA4,0xC2,0x48,0x14,0xC9,0x09,0x90,
++    0xC2,0x48,0x04,0x44,0x02,0x77,0xC8,0x34,0x54,0x4C,0x12,0x0A,0xD0,0x06,0x30,0x42,
++    0xC8,0xAC,0x12,0x31,0xFA,0x4B,0x18,0x8A,0xD4,0xA4,0xC2,0x48,0x14,0xC9,0x09,0x90,
++    0xC4,0x48,0x04,0x44,0xE7,0x20,0x93,0x25,0x64,0x09,0xC8,0xF6,0xC0,0xAC,0x12,0x31,
++    0xE0,0x0B,0xC2,0xE4,0x02,0x42,0xCE,0xAC,0xFA,0x4B,0x18,0x8A,0xD4,0xA4,0xC2,0x48,
++    0x14,0xC9,0x09,0x90,0xC6,0x48,0x04,0x44,0xC2,0xAC,0xCA,0x74,0xFA,0x03,0x00,0x10,
++    0xC0,0xA4,0xC2,0x90,0x02,0x89,0x0B,0x00,0xC4,0x90,0xA8,0x8B,0xCA,0xAC,0xD2,0x6C,
++    0xFA,0x4B,0x00,0x58,0xCA,0xA4,0xC2,0xC8,0xC6,0x40,0xA8,0x13,0xC2,0xAC,0xCA,0xAC,
++    0xFA,0x03,0xE0,0x00,0xBD,0x43,0x20,0xE7,0xAC,0xFD,0x87,0xBD,0xEC,0x04,0x31,0xA2,
++    0xD8,0x43,0x87,0x84,0xD8,0x43,0x85,0x7C,0xC8,0x43,0x81,0x74,0x00,0x01,0x80,0x54,
++    0x42,0x22,0x45,0x0B,0x36,0x42,0x81,0x01,0x80,0xB4,0x48,0x01,0x80,0x1E,0xC0,0x74,
++    0x40,0x00,0x82,0x5C,0x00,0x67,0xC0,0xB4,0xC8,0x03,0x46,0x51,0x98,0x26,0xC8,0xB4,
++    0x00,0x49,0xB0,0x42,0x80,0x5C,0x00,0x1F,0xC0,0xB4,0x08,0x41,0xB0,0x0A,0x8A,0x5C,
++    0x40,0xCA,0xD4,0xD4,0xC8,0xBC,0xC0,0x80,0x80,0xAC,0x48,0x01,0x84,0xF6,0x49,0xBA,
++    0xC2,0xD4,0xC0,0x08,0x10,0x49,0xC5,0xD4,0x04,0x90,0xC4,0x18,0xE0,0xAC,0xC0,0x74,
++    0x42,0x00,0x12,0x02,0x90,0x05,0x82,0x54,0x30,0x01,0x00,0x7F,0x00,0x01,0x00,0x47,
++    0x40,0x7C,0x40,0xD4,0xD1,0xD0,0x05,0x14,0xE4,0x20,0xE5,0x48,0xE2,0xD8,0xE4,0x00,
++    0x90,0x05,0xD6,0x7C,0x17,0x82,0x9C,0x9E,0xE7,0xB0,0x93,0xB5,0xC4,0x84,0x10,0x32,
++    0x9B,0x66,0x37,0x02,0x40,0x01,0x80,0x06,0x3C,0x02,0x4C,0x2A,0xC2,0xD4,0xC0,0x18,
++    0x48,0x1A,0xC4,0xD4,0x8A,0xC1,0xC1,0x00,0x50,0x0A,0xCC,0xD4,0x94,0x81,0xC3,0x48,
++    0x10,0x01,0x00,0x47,0x40,0x24,0x40,0x74,0xD8,0x20,0x05,0xE4,0xE4,0xD8,0xE4,0x00,
++    0xE2,0x48,0xE4,0x90,0x90,0x95,0xE6,0x7C,0x17,0x12,0x9D,0x9E,0x48,0x92,0xC3,0xD4,
++    0xC0,0x00,0x82,0x4C,0xE0,0xAC,0x00,0x01,0x81,0x8C,0x30,0x42,0x80,0x01,0x81,0xA4,
++    0x80,0x01,0x86,0x9C,0x08,0x97,0x32,0x01,0x08,0x47,0xC2,0x4C,0xC4,0x03,0x48,0x00,
++    0x89,0xF6,0xF3,0x02,0xCC,0x74,0x10,0x42,0xD8,0xD6,0xC3,0x7C,0x32,0x5A,0x03,0x00,
++    0xD0,0x08,0x31,0x52,0xD6,0x01,0x59,0x94,0x10,0xD4,0x40,0x54,0x12,0xD4,0x42,0x4C,
++    0x11,0xCC,0x34,0x0A,0xCE,0x01,0x59,0x4C,0x11,0xCC,0x46,0x0C,0x1B,0xCC,0x40,0x0C,
++    0x18,0xCC,0xCA,0x08,0x31,0x52,0xD0,0x01,0x5C,0x94,0x1E,0xD4,0xD6,0x02,0x19,0xC4,
++    0x40,0x44,0x22,0xC4,0x40,0x25,0x70,0x01,0x88,0x26,0x08,0x01,0x16,0xCC,0x10,0xCC,
++    0x18,0xCC,0x04,0x47,0xCA,0x7C,0xF0,0x48,0x10,0x72,0x8C,0x26,0x0B,0x01,0x30,0x5A,
++    0x12,0xCC,0x1C,0xCC,0x20,0xCC,0xC8,0x8C,0x48,0x01,0x88,0x26,0x30,0x5A,0x13,0xCC,
++    0x14,0xCC,0x12,0xCC,0x00,0x4F,0xC8,0x84,0xD2,0x8C,0xF0,0x48,0x10,0x52,0x8C,0x26,
++    0x0B,0x01,0x30,0x5A,0x1E,0xCC,0x1C,0xCC,0x20,0xCC,0x10,0x01,0xF3,0x12,0x35,0x5A,
++    0x0A,0x81,0xF0,0xCA,0x11,0x8A,0xD4,0x9E,0x0A,0x91,0xF0,0xCA,0x17,0x8A,0xD4,0xD6,
++    0x0A,0xA1,0xF0,0xCA,0x17,0x8A,0xD4,0xB6,0x0A,0xB1,0xF0,0xCA,0x17,0x8A,0xD4,0x96,
++    0x0A,0xD1,0xF0,0xCA,0x11,0x8A,0xE4,0x1E,0x0A,0xE1,0xF0,0xCA,0x17,0x8A,0xE4,0xD6,
++    0x0A,0xF1,0xF0,0xCA,0x17,0x8A,0xE4,0xB6,0x0A,0x01,0xF1,0xCA,0x17,0x8A,0xE4,0x96,
++    0x0A,0xD1,0xEC,0x4A,0x4B,0x01,0x80,0xCE,0x08,0x01,0x88,0x6C,0x30,0x72,0x8C,0x1C,
++    0x88,0x64,0xD8,0xBC,0x5A,0x01,0x88,0x1E,0x32,0xE2,0xFC,0x78,0x1E,0x01,0xF0,0x1A,
++    0x10,0xDA,0xD5,0x46,0xC0,0xC8,0x92,0x4D,0xDA,0x1C,0xE0,0xD8,0x90,0xDD,0x06,0x07,
++    0x00,0xF7,0x9D,0x1C,0x00,0x2F,0x58,0x51,0xEB,0x1E,0x30,0x9A,0xE6,0xD8,0x92,0xDD,
++    0x34,0xF2,0xE4,0x00,0x32,0x1A,0xE3,0xD8,0x94,0xDD,0x36,0xE2,0x30,0x1A,0x5B,0x49,
++    0x9A,0x26,0xC7,0x80,0x90,0x05,0xD0,0xA4,0x70,0x4C,0xE9,0x93,0x10,0x8A,0x9C,0xB6,
++    0xCC,0x5C,0x10,0x42,0xD3,0x9E,0x30,0x8A,0x48,0x39,0x98,0x36,0xCA,0x5C,0x80,0x48,
++    0x10,0x0A,0xDC,0x66,0xC0,0x1C,0x40,0x01,0x88,0x4E,0xC0,0xB4,0xC8,0x03,0x46,0x11,
++    0x98,0x0E,0x00,0x09,0x80,0x6C,0x48,0xDA,0xC2,0x43,0xE2,0x00,0x80,0x43,0x4A,0xCA,
++    0xC0,0x43,0x40,0x81,0x90,0x26,0x52,0xC2,0xA2,0xB2,0xE0,0x00,0x81,0x43,0x00,0xFF,
++    0x34,0xB2,0x84,0x98,0xC0,0x98,0x96,0xDD,0x98,0x14,0x18,0x01,0x30,0xE2,0xDC,0x54,
++    0x80,0xD8,0x9A,0x94,0x1E,0x01,0xF0,0x1A,0xFD,0x94,0x10,0xDA,0xD3,0x56,0x30,0xBA,
++    0xC9,0xF8,0x96,0xFD,0x30,0xF2,0xFD,0x54,0x10,0xDA,0xD5,0x1E,0x86,0xB8,0xCA,0xB8,
++    0x90,0xFD,0xB9,0x14,0xC0,0xC8,0x02,0x97,0x60,0x20,0x02,0x00,0x70,0xD2,0x05,0x00,
++    0x70,0xD2,0x03,0x00,0x80,0x40,0x07,0x01,0x48,0xE0,0x06,0x00,0x28,0x60,0x00,0x00,
++    0x68,0x70,0x04,0x00,0x00,0xC0,0x00,0x01,0x80,0xC0,0x06,0x01,0x00,0xF7,0x90,0x4D,
++    0xE3,0x00,0x34,0x1A,0xE6,0xD8,0x92,0xDD,0x33,0xE2,0x34,0x1A,0x5E,0x49,0x98,0x8E,
++    0xC4,0x14,0x10,0x0A,0xD8,0x16,0xC8,0x5C,0x28,0x72,0xD4,0x0E,0x00,0x09,0x80,0x6C,
++    0xC6,0xB4,0xC8,0x03,0x40,0x51,0x98,0x16,0xC0,0xBC,0x40,0x01,0x80,0x46,0xC8,0x6C,
++    0x00,0x09,0x48,0x01,0x80,0x06,0x00,0x01,0x80,0x64,0x00,0x0F,0x00,0x09,0x80,0x64,
++    0xC0,0x64,0x40,0x01,0x80,0xA6,0x01,0x09,0xBC,0x43,0x43,0x3A,0x40,0x03,0x42,0x01,
++    0x88,0x5E,0xC0,0xB4,0xC8,0x03,0x46,0x51,0x90,0x3E,0xC0,0xA4,0x6E,0x4C,0xE7,0x03,
++    0x32,0x00,0x72,0x00,0x84,0x51,0x10,0x0A,0xC8,0x0E,0x10,0x01,0x00,0x07,0x10,0x09,
++    0xC0,0xC4,0x40,0x01,0x80,0x06,0x10,0x11,0xC0,0xD4,0x90,0x14,0x81,0x04,0x30,0x9A,
++    0xA9,0x0C,0x30,0x02,0xD0,0x8C,0xC8,0x4C,0xBA,0xFF,0xD7,0x37,0xC0,0x9C,0xC0,0x03,
++    0x38,0x00,0xAA,0x1E,0xFF,0x43,0xF9,0x4B,0x10,0x42,0x9C,0x4E,0xC0,0x9C,0xC0,0x03,
++    0x38,0x00,0xA2,0x1E,0x05,0x01,0xA8,0x43,0xCC,0x9C,0x80,0x43,0x87,0xDD,0xE8,0x85,
++    0xE0,0x20,0xC5,0x4C,0xE0,0x00,0x82,0x4C,0xE7,0xB0,0x93,0xB5,0xC4,0x7C,0x10,0x32,
++    0x95,0x06,0x30,0x97,0xC2,0x8C,0xE0,0x00,0x90,0x05,0x86,0x8C,0xC8,0x84,0xC0,0x8C,
++    0x10,0x42,0x94,0x06,0x37,0x3F,0x3D,0x4F,0xAC,0x9D,0x87,0x0D,0xD8,0x43,0x80,0x04,
++    0xDB,0x63,0x52,0x12,0xC4,0x0C,0xC0,0x28,0x50,0x02,0xC3,0x0C,0xD4,0xC1,0xC1,0x30,
++    0xE8,0x43,0x0C,0xF1,0x84,0x0F,0xD8,0x97,0x49,0xE9,0x88,0x0E,0x48,0xE2,0xC2,0x0C,
++    0xC5,0x10,0x0A,0x49,0xC4,0x0C,0x00,0x48,0xC0,0x08,0x1A,0x01,0x00,0x5F,0x00,0x01,
++    0x00,0x2F,0x40,0x7C,0x04,0xBC,0xE0,0x90,0xE2,0x48,0xE4,0x00,0x95,0x05,0x16,0x02,
++    0x9A,0xBE,0xE7,0xD8,0x90,0xDD,0xC6,0x04,0x17,0x1A,0x9C,0x86,0x00,0x01,0x00,0x2F,
++    0x41,0x8C,0x01,0x4C,0xE5,0x68,0xE5,0xB0,0xE6,0x00,0x92,0x05,0x17,0x02,0x9D,0xBE,
++    0x48,0x62,0xC2,0x0C,0xC0,0x00,0x12,0x01,0x00,0x67,0x08,0x01,0x00,0x37,0xC0,0x1B,
++    0x34,0xD8,0x74,0xD8,0x82,0x1B,0xE0,0x00,0xE6,0x48,0x92,0x4D,0x17,0x0A,0x9D,0xB6,
++    0xE6,0x90,0x92,0x95,0xCC,0x04,0x10,0x52,0x9F,0x7E,0xEF,0xF5,0xAC,0xFD,0x87,0x1D,
++    0x30,0x6A,0x30,0x01,0xBB,0x73,0xB9,0x73,0x37,0x42,0x81,0x01,0xC7,0x0B,0x10,0xE9,
++    0x02,0x52,0x38,0x48,0x7A,0x48,0x06,0x48,0x18,0x52,0x80,0x13,0xC7,0x0B,0x10,0xD9,
++    0x00,0x8A,0x80,0x0B,0x34,0x42,0x81,0x01,0x84,0x14,0xF0,0x03,0x78,0xB2,0x41,0x01,
++    0x80,0x4E,0x00,0x01,0x57,0xAA,0x09,0xF9,0xA2,0x8A,0xE0,0x00,0x90,0x05,0x46,0x81,
++    0x99,0xD6,0x87,0xF3,0x80,0xF3,0xAB,0x04,0x00,0x01,0xD8,0x1C,0xD0,0x34,0xC8,0x2C,
++    0xBD,0xFF,0xEF,0xD7,0x36,0x62,0xA1,0x01,0xC8,0x03,0x47,0x51,0x98,0x36,0xA8,0x04,
++    0x00,0x09,0xD8,0x1C,0xD0,0x34,0xC8,0x2C,0xBD,0xFF,0xEF,0x77,0xC4,0x14,0xF0,0x0B,
++    0x49,0x01,0x80,0xD6,0x00,0x01,0x48,0x09,0x8B,0x5E,0xC0,0xD3,0x50,0x01,0x80,0x46,
++    0x50,0x1A,0xC1,0x93,0x50,0x01,0x88,0x26,0x50,0x12,0xC1,0x93,0x50,0x01,0x88,0x06,
++    0x00,0x09,0x40,0x01,0x87,0x2E,0xC8,0x13,0x50,0x01,0x95,0x36,0xE7,0x90,0x8A,0x13,
++    0x07,0x1F,0xC8,0x13,0x50,0x51,0x90,0x06,0x8F,0x33,0xCF,0x13,0x50,0x51,0x98,0xE6,
++    0x40,0x01,0x88,0x6E,0x48,0x09,0x88,0x16,0xF7,0x90,0x8A,0x13,0x01,0x47,0x00,0x99,
++    0xEF,0x02,0x6A,0x4C,0x34,0x00,0x72,0x00,0x10,0x0A,0x94,0x0E,0xF7,0x90,0x8A,0x13,
++    0xC0,0xC3,0x43,0x11,0x9D,0x16,0x00,0x01,0x88,0x03,0x07,0x37,0x40,0x09,0x88,0x26,
++    0xCA,0x03,0x47,0x81,0x93,0x0E,0x00,0x21,0x89,0x03,0x37,0x4A,0xC7,0x1C,0xB8,0xFF,
++    0xF8,0xDF,0x81,0x3D,0xE8,0x85,0x07,0x00,0x80,0x40,0x07,0x01,0x68,0xF0,0x07,0x00,
++    0x28,0x60,0x00,0x00,0x60,0x20,0x02,0x00,0x00,0xC0,0x00,0x01,0x80,0xC0,0x06,0x01,
++    0x00,0x40,0x00,0x01,0x00,0x48,0x00,0x01,0xAC,0xFD,0x87,0x3D,0xE0,0x84,0x30,0xB2,
++    0x00,0x01,0x80,0x2C,0xD8,0x83,0x83,0x1C,0x60,0x8C,0x89,0x14,0xCA,0x44,0x18,0x0A,
++    0x50,0xFA,0xC7,0x3C,0xC0,0x00,0xC4,0x48,0x8F,0x34,0x40,0xF2,0xC0,0x03,0x40,0x09,
++    0x89,0x0E,0xE0,0x83,0x80,0x1C,0x00,0x01,0x10,0x01,0x00,0x1F,0x82,0x53,0xE0,0x48,
++    0xE6,0x00,0x92,0x05,0xDC,0x1C,0x10,0xC2,0x98,0xC6,0x0F,0x01,0x00,0x09,0xD8,0x54,
++    0xD0,0x44,0x80,0x07,0xD0,0xAF,0x2E,0x01,0x60,0x01,0x88,0x0E,0xE7,0x68,0x93,0x6D,
++    0xF8,0x34,0x08,0x01,0x01,0x5F,0xC0,0xC3,0x1E,0x02,0x91,0x05,0x80,0xC3,0xD1,0x8C,
++    0x10,0x82,0xCC,0x0E,0x19,0x02,0x85,0xC3,0xE2,0xF8,0xE3,0x48,0x90,0x4D,0xC6,0x1C,
++    0x17,0x0A,0x9C,0x86,0x48,0x42,0xC7,0x3C,0xC0,0x00,0x82,0x24,0xD0,0x54,0x90,0x04,
++    0x30,0x9A,0x01,0x11,0xD0,0x3C,0xC8,0x44,0x80,0x07,0xD8,0x47,0xD0,0x54,0x90,0x04,
++    0x04,0x41,0xEA,0x0A,0x00,0x01,0x1C,0x0A,0x30,0x9A,0x11,0x01,0xC0,0x24,0x80,0x07,
++    0xF6,0x27,0x05,0x29,0xE8,0x02,0x44,0x31,0x88,0x16,0x00,0x01,0x87,0x5D,0xE8,0x85,
++    0xC1,0x1C,0xD0,0xC0,0x09,0x01,0x00,0x3F,0xD0,0x24,0x18,0x01,0xF0,0x9A,0xD6,0x14,
++    0xD0,0xD0,0x94,0x95,0x68,0x01,0x88,0x2E,0x50,0xC1,0xE8,0xBE,0xC5,0x13,0x18,0x12,
++    0x80,0x13,0x00,0x9F,0x50,0x99,0xE8,0x2E,0xC0,0x13,0x50,0x01,0x82,0x16,0xF0,0x90,
++    0x80,0x13,0x00,0x5F,0x68,0x29,0x88,0x4E,0x58,0xE1,0xEE,0x3E,0xC0,0x13,0x50,0x01,
++    0x88,0x26,0xD0,0x2C,0x50,0x01,0x88,0x0E,0x10,0x09,0x90,0x2C,0xD4,0x24,0xE0,0x90,
++    0x92,0x24,0xE0,0x00,0xE6,0x48,0x92,0x4D,0xD4,0x1C,0x10,0x8A,0x9B,0xA6,0x46,0x20,
++    0x6C,0x21,0xC8,0xCE,0xD0,0x54,0x90,0x04,0x30,0x9A,0x09,0x01,0x00,0x19,0xD0,0x3C,
++    0x85,0x07,0xD0,0xE7,0x08,0x09,0x30,0x42,0xD8,0x54,0xD0,0x44,0x83,0x07,0xD0,0x07,
++    0xC5,0x2C,0x38,0xDF,0xAC,0xFD,0x87,0x1D,0xF0,0x64,0x30,0x7A,0x33,0xEA,0xD8,0xC3,
++    0x85,0x14,0x48,0xAA,0xC2,0x1C,0xC0,0x20,0x40,0x92,0xC5,0x03,0x40,0x09,0x88,0x0E,
++    0xE0,0xC3,0x81,0x14,0x08,0x01,0x00,0x09,0xD8,0x2C,0xD0,0x6C,0x82,0x07,0xD0,0x47,
++    0xD0,0x2C,0x90,0x04,0x30,0xDA,0x01,0x11,0xD0,0x1C,0xC8,0x6C,0x84,0x07,0xD0,0xB7,
++    0xD0,0x2C,0x90,0x04,0x06,0x41,0xEA,0x0A,0x00,0x01,0x1C,0x0A,0x30,0xDA,0x11,0x01,
++    0x30,0x02,0x81,0x07,0xF0,0x97,0xD1,0x2C,0x91,0x04,0x30,0xDA,0x08,0x01,0x00,0x19,
++    0xD0,0x1C,0x80,0x07,0xD0,0x1F,0x0C,0x09,0x30,0x42,0xD8,0x2C,0xD0,0x6C,0x80,0x07,
++    0xD4,0x3F,0x41,0xF2,0x00,0x44,0x01,0x01,0x00,0x84,0x09,0x01,0x00,0x77,0x00,0x01,
++    0xF0,0x02,0x11,0x01,0xF4,0x52,0x15,0x12,0xE9,0x06,0x00,0x44,0x15,0x01,0xF0,0x92,
++    0x10,0x12,0xD4,0x06,0x05,0x84,0xE1,0x20,0xE6,0x48,0x92,0x4D,0xC4,0x14,0x10,0x0A,
++    0x98,0x6E,0x87,0x3D,0xEF,0x85,0xAF,0xBD,0x80,0x55,0xC4,0x5C,0xD8,0x03,0x86,0x24,
++    0xCA,0x5C,0xD8,0x4B,0x8C,0x1C,0x50,0x52,0xCC,0x54,0xC0,0x48,0x8C,0x4C,0x48,0x4A,
++    0xC0,0x4B,0x48,0x09,0x88,0x46,0xC8,0x24,0xE6,0x48,0x92,0x4D,0x88,0x24,0x80,0x3C,
++    0xC0,0x5C,0xE0,0x03,0x80,0x1C,0x00,0x0F,0x00,0x01,0x80,0x3C,0xF8,0x3C,0xC0,0x5C,
++    0x80,0x01,0x86,0x44,0x04,0x7F,0x4B,0x12,0x04,0x01,0x00,0x43,0xC0,0x5C,0xC8,0x4C,
++    0xDB,0x03,0x1A,0xC2,0xC0,0x08,0x02,0x01,0x10,0xF9,0x01,0x1F,0x82,0x53,0xE0,0x48,
++    0xE6,0x00,0x92,0x05,0xDC,0x1C,0x10,0xC2,0x9C,0xC6,0x27,0x01,0x31,0x2A,0x31,0x32,
++    0x03,0xE7,0x40,0xC2,0x08,0x23,0x4E,0x2D,0xB8,0x0C,0x88,0x04,0x40,0x55,0x40,0x3E,
++    0x5F,0x35,0xB8,0xFF,0xF8,0x7F,0xC3,0x44,0xC8,0x03,0x42,0x31,0x83,0x7E,0x33,0x5A,
++    0x00,0xC1,0xF0,0xC2,0x40,0xE1,0xD1,0x1E,0x68,0x41,0x80,0x4E,0x18,0x62,0x05,0x1F,
++    0x70,0x01,0x8C,0x0E,0x30,0x72,0x01,0x1F,0x41,0x68,0x1B,0x62,0x6F,0x01,0x88,0x06,
++    0xC0,0x5C,0xC8,0x4C,0xDB,0x03,0x1A,0xC2,0xC0,0x08,0x02,0x01,0x10,0x01,0x00,0x1F,
++    0x82,0x53,0xE0,0x48,0xE6,0x00,0x92,0x05,0xDC,0x1C,0x10,0xC2,0x99,0xC6,0x37,0xAA,
++    0x20,0x01,0x00,0x0F,0x1B,0xA2,0x41,0xB0,0x77,0x01,0x88,0xDE,0xC0,0x5C,0x60,0x04,
++    0xC0,0x41,0x91,0x35,0x05,0xAF,0x18,0x62,0x46,0xD2,0x0A,0x23,0x48,0x2D,0xB8,0x0C,
++    0x88,0x04,0x40,0x55,0x40,0x3E,0x58,0x35,0xB9,0xFF,0xFF,0xA7,0xC2,0x44,0xC8,0x03,
++    0x42,0x31,0x80,0x6E,0x30,0x5A,0x03,0xA1,0xF5,0xC2,0x10,0x82,0xE9,0x06,0x18,0x62,
++    0x40,0x68,0x6B,0x01,0x88,0x3E,0xC7,0x54,0x0E,0x59,0xCB,0x00,0x0A,0x48,0xC2,0x00,
++    0xB3,0x23,0xE0,0xF8,0x90,0xFD,0xC7,0x24,0x14,0x3A,0x9C,0x66,0xF1,0x3C,0x00,0xA7,
++    0xC3,0x54,0x08,0x59,0xCA,0x00,0x0C,0x48,0xC1,0x38,0xF2,0xC3,0x40,0x01,0x88,0x0E,
++    0x01,0x09,0xB0,0xC3,0xF0,0xE3,0x29,0x01,0x01,0x01,0x00,0x0F,0xE7,0x68,0x93,0x6D,
++    0x40,0x09,0x88,0x1E,0x60,0xF9,0x97,0x0E,0xE5,0x20,0x93,0x25,0x48,0xE2,0x01,0x01,
++    0x00,0x43,0xAC,0x48,0x46,0xDA,0x09,0x23,0x20,0x00,0x67,0x10,0x00,0x0F,0x00,0xBF,
++    0x40,0x48,0x32,0x82,0x17,0x42,0x80,0xDE,0x48,0x01,0xC9,0x06,0x08,0x01,0x89,0x04,
++    0x90,0x0C,0x40,0x55,0x41,0x6E,0x30,0x8A,0xBA,0xFF,0xF7,0x77,0x40,0x01,0x80,0x0E,
++    0x6E,0x29,0x98,0xDE,0xB3,0xE3,0xE1,0xB0,0x90,0xB5,0xC7,0x24,0x16,0x32,0x9C,0x3E,
++    0x87,0x6D,0xE8,0x85,0xAC,0xBD,0x87,0x15,0x30,0x62,0x30,0xB2,0x48,0x2A,0x01,0x01,
++    0x81,0x43,0x40,0x4A,0x40,0x0B,0x10,0x11,0x18,0x8A,0x00,0x0B,0x28,0x01,0x00,0x3F,
++    0x09,0x09,0x30,0x9A,0x30,0x52,0x31,0x42,0x81,0x07,0xC8,0x57,0xE7,0x68,0x93,0x6D,
++    0xDD,0x03,0x11,0x42,0xC1,0xA6,0x37,0x12,0x30,0x8A,0x01,0x11,0x84,0x07,0xC0,0x2F,
++    0x31,0x92,0x31,0x0A,0xC7,0x14,0xB8,0xFF,0xF9,0x77,0x30,0x12,0x30,0x8A,0x01,0x01,
++    0x83,0x07,0xC0,0xDF,0xE0,0x03,0x41,0x01,0x80,0xBE,0x69,0xB2,0x44,0x43,0x97,0x3D,
++    0x4F,0x04,0x01,0x43,0x40,0x7A,0x08,0x09,0x81,0x0B,0x30,0x12,0x30,0x8A,0x01,0x11,
++    0x83,0x07,0xC0,0x5F,0x30,0x1A,0xB1,0x04,0x08,0x01,0x00,0x09,0xD0,0x14,0x80,0x07,
++    0xC8,0xAF,0xB2,0x04,0xD9,0x0B,0x37,0x1A,0x00,0x11,0xD0,0x14,0x82,0x07,0xC8,0x77,
++    0x31,0x92,0x31,0x0A,0xC7,0x14,0xB8,0xFF,0xF1,0x37,0x37,0x12,0x30,0x8A,0x01,0x6F,
++    0x60,0x20,0x02,0x00,0x00,0xD0,0x00,0x01,0x48,0xE0,0x06,0x00,0xF8,0xFB,0x07,0x00,
++    0x10,0x00,0x00,0x42,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0x00,0x01,0x80,0x07,
++    0xC0,0x27,0x42,0x5A,0x08,0x01,0x80,0x0B,0x01,0x7B,0x37,0x1A,0xB0,0x04,0x08,0x01,
++    0x00,0x11,0xD0,0x14,0x81,0x07,0xC8,0x57,0x31,0x12,0x31,0x8A,0x00,0x11,0x80,0x07,
++    0xC0,0xA7,0x51,0x22,0x40,0x83,0x08,0x11,0x18,0x42,0x04,0x83,0x87,0x2D,0xE8,0x85,
++    0x00,0xD0,0x00,0x01,0x18,0x00,0x04,0x42,0xA8,0x85,0x31,0x12,0x92,0x01,0x46,0x8C,
++    0x80,0x01,0xC7,0x1B,0x32,0xD8,0x72,0xD8,0x87,0x1B,0x58,0xE2,0x41,0xE3,0x30,0x20,
++    0xA2,0x16,0x40,0xE3,0x3F,0x20,0xAB,0xE6,0x58,0xCA,0x27,0x41,0x00,0xE3,0x44,0xE3,
++    0x28,0xF9,0xAF,0x19,0x18,0x62,0x01,0xE3,0xC7,0x23,0x48,0x20,0x8A,0x1E,0xF0,0x48,
++    0x20,0x48,0x60,0x48,0x88,0xC6,0x4F,0x01,0x88,0x36,0x40,0xC3,0x08,0x81,0x18,0x42,
++    0x07,0xC3,0x00,0xF9,0x82,0x89,0x04,0x84,0xEF,0x85,0xA9,0x85,0x46,0x63,0x42,0x5B,
++    0xDF,0xAB,0x72,0x62,0xC0,0xB3,0x71,0x09,0x8E,0x16,0x48,0x63,0x50,0x5B,0xE2,0xAB,
++    0x41,0x01,0x88,0x0E,0x10,0x01,0x00,0xE7,0x40,0x03,0x31,0x32,0xB5,0x41,0x30,0xA2,
++    0xE8,0x08,0x30,0x42,0xC4,0x01,0x5A,0x33,0xC1,0xFB,0x18,0xF2,0x1E,0x33,0x5C,0x33,
++    0xC5,0xFB,0x18,0xF2,0x1B,0x33,0x36,0x32,0x40,0x83,0xC1,0xF3,0x1B,0x82,0x35,0x32,
++    0x00,0x83,0x41,0x73,0xC4,0xC3,0x18,0x32,0x01,0x73,0xE8,0x20,0xE2,0xD8,0xE2,0x90,
++    0x95,0x95,0x16,0x52,0x9F,0x06,0xEF,0x85,0x41,0x09,0x88,0x0E,0x10,0x01,0x00,0xE7,
++    0x40,0x03,0x31,0x32,0xB5,0x41,0x30,0xA2,0xE8,0x08,0x30,0x42,0xC4,0x01,0x5A,0x33,
++    0xC5,0xFB,0x18,0xF2,0x1E,0x33,0x5C,0x33,0xC5,0xFB,0x18,0xF2,0x1B,0x33,0x36,0x32,
++    0x40,0x83,0xC1,0xF3,0x1B,0x82,0x35,0x32,0x00,0x83,0x41,0x73,0xC0,0xC3,0x18,0x32,
++    0x01,0x73,0xE8,0x20,0xE2,0xD8,0xE2,0x90,0x95,0x95,0x16,0x52,0x9F,0x06,0xEF,0x85,
++    0x41,0x11,0x88,0x0E,0x10,0x01,0x00,0xE7,0x40,0x03,0x31,0x32,0xB5,0x41,0x30,0xA2,
++    0xE8,0x08,0x30,0x42,0xC4,0x01,0x5A,0x33,0xC5,0xFB,0x18,0xF2,0x1E,0x33,0x5C,0x33,
++    0xC5,0xFB,0x18,0xF2,0x1B,0x33,0x36,0x32,0x40,0x83,0xC1,0xF3,0x1B,0x82,0x31,0x32,
++    0x00,0x83,0x41,0x73,0xC4,0xC3,0x18,0x32,0x01,0x73,0xE8,0x20,0xE2,0xD8,0xE2,0x90,
++    0x95,0x95,0x16,0x52,0x9F,0x06,0xEF,0x85,0x47,0x19,0x88,0xE6,0x10,0x01,0x00,0xE7,
++    0x40,0x03,0x31,0x32,0xB5,0x41,0x30,0xA2,0xE8,0x08,0x30,0x42,0xC4,0x01,0x5A,0x33,
++    0xC5,0xFB,0x18,0xF2,0x1E,0x33,0x5C,0x33,0xC5,0xFB,0x18,0xF2,0x1B,0x33,0x36,0x32,
++    0x40,0x83,0xC1,0xF3,0x1B,0x82,0x31,0x32,0x00,0x83,0x41,0x73,0xC0,0xC3,0x18,0x32,
++    0x01,0x73,0xE8,0x20,0xE2,0xD8,0xE2,0x90,0x95,0x95,0x16,0x52,0x9F,0x06,0xEF,0x85,
++    0xAA,0x85,0x47,0xE3,0x05,0xB0,0xCC,0x20,0x45,0xEB,0xC6,0x68,0x40,0x09,0x88,0x26,
++    0x45,0xE3,0xC8,0x20,0x44,0xDB,0xC4,0xE8,0x04,0x3F,0x78,0xD2,0xC0,0xFB,0x79,0x09,
++    0x8E,0x1E,0x48,0xE3,0xCA,0x20,0x55,0xDB,0xC1,0xE8,0x44,0x13,0xF9,0xA0,0xC0,0x5B,
++    0x40,0x09,0x88,0x76,0x48,0x01,0x88,0x66,0x44,0x83,0x1A,0xC2,0x04,0x83,0x42,0x83,
++    0x1C,0xC2,0x04,0x83,0x44,0x03,0x19,0xC2,0x00,0x03,0x41,0x83,0x18,0xC2,0x00,0x83,
++    0xE8,0x85,0x4F,0x09,0x8A,0x66,0x40,0x83,0x1A,0xC2,0x04,0x83,0x44,0x83,0x1C,0xC2,
++    0x00,0x83,0x44,0x83,0x18,0xC2,0x04,0x83,0x40,0x03,0x19,0xC2,0x07,0x03,0xE9,0x85,
++    0x48,0x11,0x88,0x66,0x44,0x03,0x19,0xC2,0x00,0x03,0x41,0x83,0x18,0xC2,0x04,0x83,
++    0x40,0x83,0x1A,0xC2,0x04,0x83,0x42,0x83,0x1C,0xC2,0x04,0x83,0xE8,0x85,0x4F,0x19,
++    0x89,0xE6,0x47,0x03,0x19,0xC2,0x04,0x03,0x44,0x83,0x18,0xC2,0x02,0x83,0x40,0x83,
++    0x1A,0xC2,0x04,0x83,0x40,0x83,0x1C,0xC2,0x07,0x83,0xEC,0x85,0xA8,0xFD,0xF7,0x4C,
++    0x30,0x62,0x2C,0x01,0x4D,0x93,0x49,0x8B,0x32,0x72,0xDC,0xE3,0x33,0x3A,0x49,0x8A,
++    0xC0,0x4B,0x48,0x09,0x89,0x0E,0x50,0x93,0xE0,0xE3,0x40,0x19,0x80,0x96,0x31,0x79,
++    0x49,0x5A,0x13,0xB0,0x40,0x11,0x88,0xB6,0x32,0x02,0x1B,0x3A,0x58,0x52,0xC3,0x14,
++    0xC1,0x00,0xC6,0xC0,0x33,0x9A,0x33,0x2A,0xEA,0xDA,0x0A,0x5B,0x08,0x01,0x00,0x3F,
++    0xC1,0x1B,0x18,0x9A,0x41,0xAB,0x00,0x5B,0xEA,0x90,0xE0,0x00,0xE6,0x48,0x92,0x4D,
++    0x17,0x0A,0x9D,0xAE,0xE8,0xFD,0x47,0x01,0x88,0x8E,0x18,0x01,0x12,0x5B,0x46,0xDA,
++    0x45,0x33,0x40,0xB0,0x00,0xB0,0x05,0x33,0x00,0x1B,0x02,0x5B,0x40,0x0B,0x18,0x81,
++    0x18,0xCA,0x04,0x0B,0x44,0x0B,0x18,0x01,0x18,0xCA,0x00,0x0B,0x00,0x17,0x40,0x09,
++    0x89,0x06,0x30,0xAA,0x00,0x01,0x00,0x27,0x40,0x8B,0x00,0x6B,0xEA,0x90,0xE0,0x00,
++    0x95,0x05,0x16,0x02,0x9F,0xC6,0xEF,0xFD,0x3B,0x82,0xAB,0x85,0x4A,0xA3,0xD8,0xEB,
++    0x33,0x70,0x72,0xB0,0x48,0x5A,0xC2,0x4B,0x48,0x09,0x88,0x0E,0x50,0xA3,0xE0,0xEB,
++    0x08,0x01,0x00,0x3F,0x42,0x13,0x41,0x93,0x00,0x92,0x07,0x14,0xEC,0x20,0xE1,0x00,
++    0xE6,0x48,0x92,0x4D,0x17,0x4A,0x9D,0xAE,0xEB,0x85,0xAB,0xC5,0x30,0x2A,0x30,0xB2,
++    0x61,0xF2,0x41,0x03,0x14,0x01,0x1C,0x82,0x01,0x03,0x41,0x03,0x10,0x81,0x18,0x82,
++    0x01,0x03,0x41,0x03,0x10,0x09,0x18,0x82,0x07,0x03,0xE1,0x53,0x00,0xF9,0x87,0x81,
++    0x19,0x12,0x40,0xBA,0x10,0x13,0x16,0x99,0x00,0x13,0x13,0x41,0x04,0x13,0x14,0xD9,
++    0xE8,0x92,0x52,0x01,0x80,0x16,0x10,0xC9,0x00,0x13,0x00,0x0F,0x10,0x89,0x00,0x13,
++    0x31,0x52,0x30,0x5A,0x08,0x01,0x00,0x09,0xB7,0x04,0xB8,0xFF,0xF9,0x7F,0x33,0x52,
++    0x30,0x8A,0x01,0x11,0xBB,0xFF,0xF7,0xCF,0x42,0x03,0x3B,0x00,0xAB,0xE6,0xEF,0xC5,
++    0xAC,0x9D,0x87,0x8D,0xCA,0x94,0xC8,0x4B,0x88,0x84,0xE0,0x94,0xA7,0x01,0xD2,0x1B,
++    0xD8,0x0B,0x89,0x04,0xCA,0x94,0xD8,0x6B,0x30,0x0A,0x88,0x71,0x30,0x62,0xCC,0x94,
++    0x30,0x01,0xE8,0x4B,0x48,0x09,0x88,0x56,0x08,0x01,0x00,0x27,0xC5,0x38,0x9A,0xF3,
++    0xA2,0x32,0xE2,0x48,0x90,0x4D,0xD2,0x94,0xDC,0x93,0x12,0x52,0xE0,0xB6,0x57,0xDA,
++    0x04,0xB3,0x02,0xB3,0x00,0xB3,0x0E,0x01,0x18,0x4A,0x06,0x8B,0xCA,0x94,0xD8,0x4B,
++    0xB0,0x8B,0x08,0x01,0x50,0xAA,0x30,0x01,0x05,0x78,0xC4,0xF8,0x0A,0xF3,0xC1,0x90,
++    0xB2,0xB3,0xE2,0x48,0x90,0x4D,0x4A,0x11,0xD8,0xA6,0xCF,0x94,0xE8,0x4B,0x48,0x29,
++    0xCD,0xF6,0x03,0x48,0xC3,0x48,0x00,0x50,0xC0,0x70,0x54,0x6A,0xC0,0xB0,0xB5,0x14,
++    0xC0,0x48,0x8C,0x0C,0x30,0x12,0x33,0x32,0xB0,0xE1,0x08,0x01,0x88,0x34,0x48,0x4A,
++    0x88,0x6C,0x88,0x64,0x30,0x32,0x04,0x01,0x32,0x22,0x04,0x97,0x18,0x00,0x04,0x42,
++    0x00,0x01,0x00,0x42,0x00,0xD0,0x00,0x01,0x60,0x20,0x02,0x00,0x80,0x40,0x07,0x01,
++    0x48,0xE0,0x06,0x00,0x78,0xF8,0x07,0x00,0xC8,0x14,0x00,0x01,0xF0,0x42,0xF8,0x0C,
++    0x0B,0x01,0xF0,0xCA,0x32,0x7A,0xD0,0x08,0x97,0x4D,0x48,0xF9,0xEF,0x06,0x08,0xF9,
++    0xCB,0x38,0x86,0xF8,0x78,0xF9,0xEF,0x06,0x3B,0xF9,0x37,0x82,0x82,0x3B,0xE0,0x00,
++    0x30,0x32,0xC4,0xBB,0x10,0xFA,0x9C,0x46,0x10,0xCA,0xDC,0x36,0x46,0x84,0xD9,0x48,
++    0xC0,0x00,0x92,0x05,0x04,0x84,0x81,0x08,0x04,0x37,0x10,0xCA,0xDC,0x16,0x00,0x78,
++    0x00,0xBC,0x01,0x0F,0x39,0x01,0x00,0xBC,0x10,0xCA,0xDC,0x0E,0x38,0x09,0xB8,0x34,
++    0x43,0x78,0x2B,0x3A,0xE8,0x26,0xF8,0x6C,0x10,0x7A,0xEC,0x2E,0x88,0x6C,0x00,0x1F,
++    0xFC,0x64,0x10,0x7A,0xE8,0x06,0x88,0x64,0x82,0x8B,0xE0,0x90,0xE0,0xB0,0xC5,0x14,
++    0xE0,0x00,0x84,0x14,0xC4,0x0C,0xE0,0x00,0x83,0x0C,0x30,0x02,0xE2,0x00,0x92,0x05,
++    0x35,0x22,0x2C,0x62,0xD8,0xC6,0xC5,0x34,0x40,0x01,0x80,0x8E,0x08,0x01,0x00,0x01,
++    0x80,0x5C,0xC0,0x04,0xC2,0x00,0x46,0x00,0x80,0x7C,0xC0,0x04,0x30,0x00,0x72,0x00,
++    0x80,0x74,0x00,0x01,0x30,0x22,0x84,0x2C,0x80,0x24,0x80,0x1C,0xF0,0x90,0x02,0x07,
++    0x03,0x1F,0xF5,0x40,0x94,0x05,0x32,0x32,0x03,0xFF,0x31,0x02,0x04,0x00,0x32,0x22,
++    0xC2,0x2C,0x00,0x00,0x80,0x2C,0xC0,0x24,0x00,0x00,0x82,0x24,0xC2,0x1C,0x00,0x00,
++    0x83,0x1C,0x40,0x40,0x28,0x82,0xEB,0x26,0xC0,0x83,0xF0,0x6C,0xD8,0x00,0x84,0x83,
++    0x00,0x1F,0xC0,0x83,0xF4,0x64,0xD8,0x00,0x80,0x83,0xC0,0x83,0x73,0x3D,0x30,0xBA,
++    0xA8,0x82,0xC7,0x83,0x10,0xC2,0xDC,0xDE,0xE2,0x48,0x92,0x4D,0xF1,0x5C,0xC0,0xB0,
++    0x90,0xB5,0xB1,0x5C,0x30,0x32,0x3B,0x09,0x1D,0xF2,0x31,0xA2,0xF5,0x7C,0x10,0x82,
++    0xD8,0x76,0xF0,0x2C,0x18,0xF2,0xB1,0x2C,0xF5,0x04,0x10,0x82,0xD8,0x46,0xF0,0x24,
++    0x18,0xF2,0xB1,0x24,0xF5,0x74,0x10,0x82,0xD8,0x16,0xC0,0x1C,0x18,0xC2,0x81,0x1C,
++    0xF3,0x90,0x32,0x82,0xF2,0x00,0x92,0x05,0x33,0x32,0x34,0x82,0x45,0x01,0xD0,0xE6,
++    0x42,0xE2,0xB7,0x0B,0xD0,0x50,0xB3,0x13,0x36,0x12,0x1B,0x92,0x03,0x13,0x30,0x12,
++    0x08,0x13,0xD0,0x2C,0x00,0x13,0xD2,0x24,0x00,0x13,0xD4,0x1C,0x00,0x13,0x36,0x01,
++    0x00,0xA7,0xC1,0x5C,0x86,0x07,0xE8,0xA7,0x90,0x05,0x80,0x5C,0x4D,0x8A,0x07,0x80,
++    0xC0,0x00,0x4A,0x13,0x40,0x3D,0x08,0x01,0x1C,0x01,0x30,0xF2,0x30,0xE2,0x04,0xCF,
++    0x38,0x98,0x86,0x7E,0xC0,0x1B,0xF8,0x5C,0xD8,0xD8,0x96,0xDD,0x58,0x01,0xE8,0x36,
++    0x83,0x1B,0x20,0x9A,0x94,0xDD,0x36,0xF2,0xE2,0x48,0x92,0x4D,0x00,0x27,0x18,0x01,
++    0x80,0x1B,0x00,0x0F,0x18,0x01,0x80,0x1B,0x42,0x90,0xE2,0x00,0x32,0x1A,0xE3,0xD8,
++    0x94,0xDD,0x32,0xE2,0x2F,0x62,0xDD,0x1E,0xE3,0xB0,0x93,0xB5,0x30,0x82,0x83,0x5C,
++    0x45,0xE2,0x06,0x98,0xC0,0xD8,0x08,0xD3,0xCA,0x00,0xB4,0x0B,0x48,0x21,0xD8,0x0E,
++    0x76,0x09,0xD8,0x36,0x06,0x01,0x50,0xBA,0x04,0x08,0xC4,0x58,0xE4,0x08,0x02,0x70,
++    0xC0,0xB0,0x4D,0xEB,0x4D,0xB3,0x19,0xAA,0x08,0xEB,0xC0,0x80,0xF4,0x1B,0xF2,0x2B,
++    0xDA,0xD8,0xB2,0x1B,0x90,0x45,0x42,0x09,0xD8,0x76,0x07,0x09,0xA6,0x03,0x43,0x6A,
++    0x0E,0x19,0x40,0x13,0x50,0x01,0x80,0x16,0x03,0x29,0xA0,0x0B,0x04,0xF7,0x40,0x13,
++    0x50,0x01,0x80,0x16,0x03,0x21,0xA0,0x0B,0x02,0xC7,0x40,0x0B,0x48,0x01,0x80,0x1E,
++    0x00,0x19,0x08,0x11,0xA0,0x0B,0x03,0x8F,0x48,0x03,0x40,0x01,0x88,0x26,0xC0,0x94,
++    0x86,0x01,0xCE,0x03,0x40,0x51,0x98,0x0E,0x00,0x11,0x00,0x3F,0xC1,0x94,0x80,0x01,
++    0xE0,0x03,0x44,0x01,0x80,0x0E,0x00,0x11,0x00,0x07,0x00,0x09,0xE4,0x0B,0xE3,0x50,
++    0xA3,0x13,0xDD,0x13,0x38,0x90,0xA2,0x0E,0xF3,0x48,0xA2,0x0B,0xE8,0x0B,0x13,0x29,
++    0x10,0x0A,0x94,0x0E,0xA8,0x13,0x01,0xEF,0x10,0x0A,0xCC,0x46,0x40,0x09,0x88,0x16,
++    0x09,0x81,0xAF,0x0B,0x00,0xB7,0xD0,0x48,0x01,0x52,0xAC,0x13,0x00,0x97,0x40,0x19,
++    0xC8,0x0E,0x08,0x19,0x02,0x07,0x90,0x0D,0xE8,0x13,0x51,0x01,0x82,0x16,0xF0,0x90,
++    0xA8,0x13,0x01,0x3F,0xD2,0x94,0xF0,0x48,0xCA,0x93,0x1C,0x52,0xCA,0x84,0xC0,0x88,
++    0xD0,0x94,0x88,0x8B,0xA8,0x03,0x83,0x9D,0xEF,0x85,0xAF,0xBD,0x80,0x6D,0x34,0x6A,
++    0xD9,0x63,0x33,0x42,0x80,0x01,0x82,0x64,0xD0,0x03,0x84,0x3C,0xC2,0x64,0xD8,0x03,
++    0x30,0x00,0xA8,0x1E,0x02,0xD9,0xEC,0x02,0x40,0x01,0x80,0xA6,0xC5,0x6C,0x00,0x08,
++    0xC3,0x40,0x00,0x08,0x52,0xC2,0xC4,0x08,0xC4,0x48,0xC4,0x10,0x00,0x01,0x18,0x01,
++    0x00,0x2F,0x00,0x5C,0x04,0x9C,0xE0,0x48,0xE2,0x90,0xE4,0x00,0x95,0x05,0x12,0x02,
++    0xD8,0xBE,0x87,0x85,0xEB,0x85,0x07,0x59,0xCA,0x6C,0x08,0x00,0xC4,0x40,0x70,0x7A,
++    0xF7,0x03,0x08,0x83,0xD0,0x7C,0x90,0x04,0x30,0x5A,0x09,0x01,0x00,0x11,0xD0,0x6C,
++    0xBB,0xFF,0xEF,0xE7,0x42,0x4A,0x84,0x01,0x43,0x0B,0x30,0x5A,0x09,0xCC,0x5C,0x8B,
++    0x0B,0xCC,0x5E,0x8B,0x15,0xCC,0x58,0x8B,0x17,0xCC,0x42,0x8B,0x14,0xCC,0x4C,0x22,
++    0x46,0x53,0x10,0xD4,0x48,0x93,0x1F,0xD4,0x17,0x89,0x00,0x93,0x13,0x19,0x18,0x93,
++    0x40,0x53,0x18,0x11,0x18,0xD2,0x04,0x53,0x40,0x0B,0x18,0xCA,0x01,0x0B,0x30,0x42,
++    0xE9,0x4B,0x81,0x01,0x80,0x5C,0x48,0x09,0x8D,0x5E,0x6A,0x44,0x81,0x14,0x30,0x8A,
++    0x5E,0x43,0x94,0x35,0xB0,0x0C,0x00,0x01,0x80,0x04,0xD0,0x6C,0x4F,0x92,0x03,0x00,
++    0xC2,0x00,0xC4,0x00,0x83,0x54,0x40,0x8A,0x18,0x33,0x0A,0x01,0x37,0x42,0xB9,0xFF,
++    0xE0,0x5F,0xF9,0x54,0xC1,0x64,0x30,0x5A,0xD1,0x0B,0x32,0xC2,0xD7,0x7C,0xB8,0xFF,
++    0xEB,0x67,0x4C,0x62,0x10,0x01,0x00,0x01,0x02,0x67,0x00,0x18,0x37,0xE2,0xF4,0xDA,
++    0x10,0x5A,0xD4,0x0E,0x33,0x0A,0xD3,0xCA,0x10,0x9A,0xEC,0x0E,0x35,0x12,0xD3,0xD2,
++    0xE2,0x00,0x92,0x05,0x17,0x02,0xDD,0x86,0xC4,0x14,0xE0,0x00,0x10,0x0A,0x9C,0x36,
++    0xC0,0x04,0x40,0x01,0x8B,0x9E,0x40,0x80,0x40,0x08,0xC2,0x70,0x00,0x3F,0xC0,0x14,
++    0xF4,0x00,0x14,0x12,0xE0,0x5E,0x00,0x09,0x83,0x04,0xE0,0xB0,0x90,0xB5,0x77,0x01,
++    0x80,0x16,0xC0,0x0C,0x16,0x32,0x9C,0x36,0x70,0x01,0x88,0x06,0x30,0x09,0xC0,0x5C,
++    0x90,0x33,0xC0,0x5C,0xD2,0x0B,0x40,0x8A,0x18,0x0B,0x32,0x01,0x36,0x42,0x81,0x01,
++    0x81,0x4C,0x80,0x01,0x83,0x44,0x00,0x37,0xC4,0x3C,0x10,0x32,0xD0,0x6E,0xC0,0x44,
++    0xC0,0x03,0xC8,0x44,0x32,0x00,0x72,0x00,0x82,0x43,0x40,0x42,0x0C,0x41,0x00,0x0B,
++    0x47,0x0B,0x10,0xF9,0x90,0x21,0x18,0x8A,0x00,0x0B,0xC8,0x6C,0x02,0x00,0xC5,0x08,
++    0x02,0x00,0x53,0x0A,0xC4,0x40,0xC0,0x00,0xC0,0x48,0x74,0x01,0x88,0x66,0x10,0x01,
++    0x78,0x02,0x02,0x37,0x18,0x01,0x00,0x1C,0x04,0x7C,0xE0,0x00,0xE2,0x48,0xE4,0x90,
++    0x95,0x95,0x12,0x12,0xD9,0xB6,0x07,0x07,0xDF,0x6C,0x00,0x10,0xC1,0x90,0x5E,0xB2,
++    0xC4,0x90,0x36,0xA2,0x18,0x01,0x00,0x9F,0x30,0x3A,0x13,0x01,0xF0,0xD2,0x3D,0x01,
++    0xFC,0x3A,0x16,0xBA,0xD0,0x06,0x00,0x14,0x3E,0x01,0xF8,0x7A,0x10,0xBA,0xEC,0x06,
++    0x04,0x54,0xE0,0x00,0xE3,0x48,0x34,0x12,0xE4,0x90,0x34,0xA2,0xE2,0xD8,0x92,0xDD,
++    0x17,0x1A,0xDD,0x4E,0xC4,0x3C,0x10,0x32,0x80,0x06,0xC1,0x44,0xC6,0x03,0x48,0x00,
++    0x88,0x1E,0xC0,0x4C,0xC8,0x03,0x42,0x31,0x88,0xBE,0xC7,0x4C,0xC8,0x03,0x42,0x31,
++    0x89,0x26,0x40,0x12,0x40,0x0B,0x10,0x81,0x18,0x8A,0x00,0x0B,0xCF,0x6C,0x00,0x00,
++    0xC0,0x00,0x4A,0xEA,0xC0,0x00,0xCA,0x64,0x32,0x5A,0xD1,0x4B,0xD7,0x7C,0xB8,0xFF,
++    0xE3,0x67,0xE7,0xB0,0x90,0xB5,0xC3,0x3C,0x14,0x32,0xEC,0xAE,0x43,0xBA,0x30,0x5A,
++    0x4A,0xCC,0x84,0x01,0x00,0x0B,0x40,0xAA,0x48,0xCC,0x1E,0x0B,0x52,0xCC,0x18,0x0B,
++    0x54,0xCC,0x1A,0x0B,0x56,0xCC,0x04,0x0B,0x4E,0x8A,0x50,0xD4,0x00,0x53,0x58,0xCC,
++    0x0F,0x0B,0x36,0xB7,0xAA,0x85,0xD8,0xE3,0x1A,0x0A,0x03,0x48,0xC5,0x50,0x0C,0x49,
++    0x02,0x48,0xC4,0x88,0xE8,0xD3,0x50,0x11,0xC0,0x4E,0x10,0x01,0x00,0x2F,0x40,0x1C,
++    0x04,0x5C,0xE0,0x48,0xE2,0x00,0xE4,0x90,0x95,0x95,0x12,0x12,0xD8,0xBE,0x17,0x01,
++    0x00,0x87,0x00,0x00,0x80,0x40,0x07,0x01,0x48,0xE0,0x06,0x00,0x00,0x01,0x00,0x42,
++    0x18,0x00,0x04,0x42,0xF8,0xFB,0x07,0x00,0x40,0x1C,0x00,0x5C,0xE4,0x00,0xE4,0x48,
++    0xE2,0x90,0x92,0x95,0x17,0x12,0xDD,0xBE,0xEF,0x85,0xA8,0x85,0x30,0x6A,0xF0,0x2C,
++    0x30,0x22,0x30,0x8A,0x31,0xFA,0x30,0xC2,0xB9,0xFF,0xDF,0xB7,0x31,0xDA,0x31,0x92,
++    0x31,0x4A,0x31,0x02,0xBC,0xFF,0xE7,0xCF,0xE8,0x85,0x37,0x0A,0x8D,0x01,0x86,0x01,
++    0x02,0x5F,0xC8,0x5B,0x58,0x31,0x88,0x46,0x40,0xFA,0x47,0x0B,0x10,0x81,0x18,0x8A,
++    0x00,0x0B,0x40,0x0B,0x18,0x8A,0x00,0x0B,0x3E,0x82,0xCB,0x1B,0x5F,0x01,0x88,0x86,
++    0x38,0x82,0xAB,0x85,0xDA,0x5B,0xD8,0x4B,0x1F,0x5A,0x4A,0xC2,0xC7,0x08,0x52,0xC2,
++    0xC0,0x00,0x14,0x01,0x00,0x27,0x40,0x24,0x04,0x64,0xE0,0x00,0xE2,0x48,0xE4,0x90,
++    0x17,0xD2,0x9C,0xC6,0xEF,0x85,0xA8,0xBD,0x80,0x15,0x34,0x62,0x37,0xBA,0xD8,0x33,
++    0xE8,0x03,0x09,0x01,0x18,0x4A,0x2E,0x01,0x40,0x29,0x90,0x16,0x1F,0x0B,0x1D,0x2B,
++    0x07,0x6F,0x00,0x09,0xEA,0x02,0x38,0x00,0xAF,0x26,0x50,0x52,0x58,0x03,0x1F,0x82,
++    0x18,0x03,0x05,0x27,0x57,0x3A,0x5F,0x03,0x18,0x92,0x1E,0x82,0x1D,0x03,0x1D,0x0B,
++    0x30,0x0A,0xC1,0x14,0xBC,0xFF,0xE7,0xE7,0x25,0x2B,0x59,0x03,0x28,0x01,0x00,0x17,
++    0x43,0x00,0xE2,0x68,0x96,0x6D,0x3F,0x08,0x8D,0x0E,0x10,0xAA,0x9B,0xC6,0xAF,0x2B,
++    0x73,0xCA,0x4E,0x04,0x00,0x83,0xC7,0x14,0x0A,0x59,0xCB,0x00,0x0A,0x48,0xC2,0x00,
++    0xF7,0x03,0x08,0x83,0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,0xBC,0xFF,0xDF,0x87,
++    0x30,0x1A,0xB9,0x04,0x30,0x4A,0x01,0x11,0xD7,0x14,0xB8,0xFF,0xD8,0xFF,0x06,0x09,
++    0xA7,0x01,0x8D,0x03,0x48,0x82,0x46,0x43,0x10,0x11,0x18,0x82,0x00,0x43,0x00,0x41,
++    0x01,0x83,0x45,0x83,0x08,0xF9,0x8F,0x19,0x19,0x42,0x00,0x83,0x87,0x2D,0xE8,0x85,
++    0x3F,0x82,0xAB,0xC5,0xD8,0x53,0x90,0x04,0xDC,0x53,0x32,0xB2,0xE9,0x53,0x54,0x91,
++    0x9E,0xBE,0x12,0x31,0xE0,0x92,0x52,0x01,0x8E,0x9E,0x52,0x02,0xC0,0x28,0x34,0x12,
++    0x91,0xE1,0x19,0xC1,0x8E,0x01,0xF4,0x1A,0xE8,0x63,0x3A,0x11,0x10,0x1A,0xDD,0x16,
++    0xD8,0xD8,0x38,0x1C,0xA9,0x7B,0x1E,0xD1,0xEE,0x63,0xF4,0x1A,0x15,0x32,0x13,0x9A,
++    0xE0,0x16,0xC8,0xD8,0x38,0x1C,0xB2,0x7B,0x30,0x01,0x38,0x01,0x1C,0x01,0x30,0xE2,
++    0x00,0x27,0x21,0x01,0x00,0xE7,0x18,0x01,0xF0,0x5A,0x5F,0x01,0xED,0x4E,0x10,0x9A,
++    0xE8,0x06,0x30,0xF2,0xE8,0x5B,0x5E,0x01,0x80,0x76,0x40,0x9C,0xF0,0xD8,0x02,0x9C,
++    0x00,0x57,0x58,0x01,0xD5,0x46,0x10,0xDA,0xD0,0x06,0x30,0xFA,0xF0,0x5B,0x58,0x01,
++    0x80,0x16,0x40,0x9C,0xE0,0xD8,0x02,0x9C,0xE4,0x68,0xE5,0x90,0xE7,0x20,0x93,0x25,
++    0x2F,0xA2,0x9B,0x06,0x32,0x1A,0xE3,0xD8,0x94,0xDD,0x36,0xE2,0xE5,0x04,0x28,0x22,
++    0x98,0xBE,0x7E,0x14,0xC8,0x90,0x3C,0x14,0x7E,0x14,0xCA,0x90,0x3E,0x14,0xEA,0x43,
++    0x40,0x01,0x80,0x0E,0xF6,0x00,0xAA,0x43,0xF0,0x43,0x40,0x01,0x82,0x0E,0xF0,0x00,
++    0xB7,0x43,0xE8,0xC5,0xAC,0xBD,0x87,0x15,0x30,0x62,0x30,0xBA,0xEF,0x2B,0xDB,0x33,
++    0xDB,0x03,0x1B,0x42,0x00,0x08,0xC2,0x14,0xC4,0x40,0x48,0x8A,0xC0,0x00,0x82,0x0C,
++    0x37,0x02,0x81,0x01,0xC4,0x0B,0x10,0x01,0x18,0x8A,0x80,0x0B,0x00,0x21,0xEE,0x02,
++    0x44,0x01,0x80,0x1E,0x09,0x09,0x30,0xDA,0x30,0x52,0x31,0x42,0xBF,0xFF,0xD7,0xC7,
++    0x30,0x1A,0xB9,0x04,0x08,0x01,0x00,0x19,0xD7,0x14,0xB8,0xFF,0xDA,0x3F,0x02,0x41,
++    0xE9,0x0A,0x30,0x1A,0x30,0xD2,0xC1,0x0C,0xBC,0xFF,0xDF,0x7F,0x31,0x1A,0x31,0x4A,
++    0xD0,0x14,0xC0,0x0C,0xBD,0xFF,0xF7,0xB7,0x50,0x02,0x1C,0x09,0xC0,0x83,0x40,0x01,
++    0x8B,0x5E,0xE0,0x68,0x95,0x6D,0x5F,0x0B,0x03,0x0F,0xE0,0x68,0x90,0x6D,0x37,0xC2,
++    0x00,0x42,0x15,0x0A,0x8D,0x0E,0x10,0xAA,0x99,0xBE,0x37,0x82,0x74,0x92,0x13,0x2A,
++    0x93,0xE6,0xA8,0x2B,0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,0xBE,0xFF,0xD7,0x47,
++    0x30,0x1A,0xB9,0x04,0x30,0x4A,0x01,0x11,0xD7,0x14,0xB8,0xFF,0xD8,0xBF,0xC0,0x14,
++    0x0A,0x59,0xCB,0x00,0x0A,0x48,0xC2,0x00,0xF7,0x03,0x08,0x83,0x05,0x41,0x00,0x83,
++    0x47,0x83,0x09,0xF9,0x88,0x19,0x18,0x42,0x01,0x83,0x39,0xBF,0xE1,0x0B,0x31,0x02,
++    0x80,0x01,0x4D,0x01,0x86,0x1E,0xC9,0x0B,0x49,0x09,0x88,0x06,0x0E,0x11,0x88,0x0B,
++    0xA8,0x2B,0x83,0x9B,0x4F,0x04,0x01,0x83,0x50,0x0A,0xCB,0x14,0xDC,0x03,0xC1,0x48,
++    0xE7,0x02,0x0A,0x83,0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,0xBC,0xFF,0xD7,0xC7,
++    0x30,0x1A,0xB9,0x04,0x30,0x4A,0x01,0x11,0xD7,0x14,0xB8,0xFF,0xD0,0x3F,0x07,0x41,
++    0x01,0x83,0x45,0x83,0x08,0xF9,0x8F,0x19,0x19,0x42,0x00,0x83,0x38,0x77,0x08,0x01,
++    0x88,0x0B,0x86,0x8B,0x3F,0x57,0xA8,0x85,0x84,0x9D,0x34,0x22,0x33,0x6A,0xD8,0x73,
++    0xD8,0x43,0x81,0x34,0x31,0x12,0x93,0xE1,0x92,0x94,0x48,0x72,0x32,0x02,0xC3,0x18,
++    0x4B,0x32,0x22,0x0A,0x8B,0x8C,0xC8,0x43,0x00,0x00,0x82,0x1C,0x00,0x01,0x80,0x14,
++    0x37,0x42,0x81,0x01,0x82,0x84,0xC0,0x03,0x5C,0x7B,0x35,0x32,0x3F,0x20,0x5A,0x43,
++    0x18,0x3A,0x60,0x01,0xD1,0x46,0x40,0xFA,0x18,0x3A,0xB8,0x0C,0x37,0x82,0x23,0xD9,
++    0x00,0x02,0xE1,0x84,0x80,0x03,0x03,0x47,0x46,0xD2,0x19,0x02,0x18,0x3A,0xB8,0x0C,
++    0x30,0x82,0x23,0x21,0x18,0x02,0xE1,0x84,0x80,0x03,0x3B,0x01,0x19,0x7B,0x37,0x42,
++    0x80,0x01,0x85,0x7C,0xC0,0x03,0x84,0x54,0xC0,0x7C,0x20,0x09,0xB8,0x22,0xA0,0x4C,
++    0x34,0x42,0x81,0x01,0x86,0x74,0x18,0x3B,0xB8,0x44,0xC0,0x74,0x18,0x3B,0xBC,0x3C,
++    0x31,0x42,0x81,0x01,0x84,0x6C,0xA0,0x3B,0xCA,0x43,0x45,0x00,0x86,0x2C,0x00,0x01,
++    0xFB,0x22,0x82,0x00,0x81,0x24,0xE8,0x43,0x40,0x29,0xC0,0xBE,0x03,0x01,0x30,0x22,
++    0x3B,0x04,0x39,0x04,0x20,0x01,0x00,0x77,0x00,0x01,0x00,0x47,0x40,0x7C,0x00,0xFC,
++    0x40,0x7C,0x00,0xBC,0xE4,0x90,0xE4,0x48,0xE2,0xD8,0xE4,0x00,0x95,0x05,0x12,0x82,
++    0xDB,0xA6,0xE7,0x20,0x90,0x25,0xC3,0x34,0x17,0x22,0xDC,0x6E,0xF8,0x94,0xE0,0x8C,
++    0x00,0x01,0x80,0x5C,0x00,0xAF,0x05,0x01,0x34,0x32,0x34,0x22,0xC8,0x5C,0x00,0x09,
++    0x00,0x42,0xCC,0x0C,0x80,0x64,0x10,0x42,0x81,0x7E,0xE3,0x53,0x50,0x01,0x80,0x2E,
++    0xC8,0x34,0xC0,0x5C,0xF4,0x48,0x12,0x42,0x88,0x06,0x30,0xB2,0x1A,0x01,0x00,0x87,
++    0x41,0xCC,0x41,0x14,0xD0,0x40,0x94,0x15,0x00,0x14,0xC9,0x1C,0x10,0x52,0xD4,0x3E,
++    0x32,0x02,0xE3,0x00,0x94,0x05,0x36,0x22,0x34,0x82,0xC3,0x00,0x94,0x05,0x30,0x32,
++    0xCC,0x2C,0x10,0x52,0xE8,0x3E,0x01,0x7F,0x00,0x01,0x00,0x42,0x48,0xE0,0x06,0x00,
++    0x38,0xA0,0x03,0x00,0xAA,0xAA,0xAA,0xAA,0x18,0x00,0x04,0x42,0x00,0xD0,0x00,0x01,
++    0x68,0xB8,0x03,0x00,0x28,0x60,0x00,0x00,0xCC,0x4B,0x13,0x8A,0xE7,0x1E,0x58,0x43,
++    0xC8,0x64,0x18,0x0A,0x18,0x4B,0xCF,0x6C,0xE8,0x4B,0x4A,0x09,0x88,0x16,0xC8,0x6C,
++    0x02,0x09,0xAC,0x43,0xCC,0x54,0x10,0x52,0xE8,0xBE,0x08,0x09,0xD4,0x44,0x00,0xCA,
++    0x18,0x8A,0x88,0x44,0x00,0x8F,0xC8,0x24,0x10,0x52,0xD4,0x76,0xCA,0x6C,0xE8,0x4B,
++    0x48,0x09,0x88,0x16,0xCC,0x6C,0x00,0x09,0xA8,0x43,0xCA,0x4C,0x10,0x52,0xD4,0x26,
++    0x08,0x09,0xD0,0x3C,0x00,0xCA,0x1C,0x8A,0x8D,0x3C,0xE0,0x20,0xE2,0xF8,0xE5,0xD8,
++    0x95,0xDD,0x12,0x9A,0xD8,0x66,0xC5,0x7C,0xC8,0x03,0x44,0x01,0x83,0x2E,0x32,0x02,
++    0x40,0x11,0xC8,0x2E,0x33,0x0A,0x33,0x82,0x83,0x07,0xC8,0xD7,0x90,0x05,0x00,0x07,
++    0x03,0x01,0x00,0x88,0xD0,0x20,0x13,0x01,0x01,0x57,0x01,0x67,0x40,0x01,0xE8,0x7E,
++    0x0B,0x01,0xF0,0x0A,0xDC,0x1C,0x10,0xCA,0xD2,0xB6,0xE0,0x18,0x10,0xCA,0xEC,0x16,
++    0xD1,0x48,0x00,0x0C,0x00,0x87,0x48,0x01,0xE8,0x76,0x08,0x09,0x00,0x0C,0x01,0x5F,
++    0x0B,0x01,0xF0,0x0A,0x10,0x0A,0xD4,0x16,0xD1,0x48,0x00,0x0C,0x00,0x27,0x48,0x01,
++    0xD0,0x16,0x08,0x01,0x19,0x4A,0x06,0x0C,0x0B,0x01,0xF0,0x0A,0xDC,0x24,0x10,0xCA,
++    0xD0,0x1E,0xC8,0x14,0xE6,0x48,0x92,0x4D,0x8D,0x14,0xE0,0x20,0xE2,0x90,0x92,0x95,
++    0x16,0x92,0xDD,0x9E,0x00,0x4F,0x00,0x01,0x08,0x01,0x00,0x27,0x05,0x0C,0xE1,0x20,
++    0xE2,0xF8,0xE5,0x00,0x95,0x05,0x12,0x82,0xD8,0xC6,0xC7,0x5C,0xE2,0x00,0x92,0x05,
++    0x80,0x5C,0xC8,0x34,0xC4,0x5C,0x10,0x42,0xD2,0x06,0x38,0x27,0xC9,0x43,0x41,0x71,
++    0xC9,0x0E,0x00,0x71,0x88,0x43,0xC1,0x14,0xCC,0x4B,0x41,0x00,0xC6,0x40,0x90,0x05,
++    0x8A,0x43,0x41,0x81,0xCA,0x0E,0x00,0x81,0x88,0x43,0x01,0x01,0x29,0x44,0x37,0x44,
++    0xC0,0x74,0xC8,0x44,0x18,0x0B,0xCE,0x74,0xC4,0x3C,0x18,0x43,0x87,0x9D,0xE8,0x85,
++    0xA8,0x85,0x33,0x2A,0x30,0x62,0x30,0xB2,0x31,0x0A,0x31,0x42,0xBA,0xFF,0xEF,0xCF,
++    0x48,0x6A,0x03,0x01,0x81,0x43,0x30,0x92,0x31,0x0A,0x31,0x42,0xBB,0xFF,0xEF,0x1F,
++    0xEE,0x03,0x41,0x41,0x92,0x0E,0xE0,0x00,0xAB,0x03,0xE9,0x85,0x10,0x01,0x00,0x37,
++    0x0A,0x01,0xE0,0x48,0x90,0x4D,0x4C,0xA1,0xCA,0xDE,0xE7,0x90,0x94,0x95,0x14,0x12,
++    0xCB,0xB6,0x3F,0x82,0x38,0x18,0x78,0xD8,0x14,0x09,0x00,0xD2,0x97,0x95,0x1E,0xF9,
++    0x08,0xD8,0x00,0xC2,0x5E,0xEA,0xC2,0x00,0x48,0x09,0x88,0x66,0x44,0x0B,0x18,0x8A,
++    0x02,0x0B,0x40,0x0B,0x1A,0x8A,0x04,0x0B,0x44,0x0B,0x1C,0x8A,0x06,0x0B,0x44,0x0B,
++    0x1E,0x8A,0x04,0x0B,0x38,0x82,0x4B,0x01,0x8A,0x66,0x40,0x0B,0x1A,0x8A,0x04,0x0B,
++    0x44,0x0B,0x1C,0x8A,0x06,0x0B,0x44,0x0B,0x1E,0x8A,0x04,0x0B,0x40,0x0B,0x18,0x8A,
++    0x03,0x0B,0x38,0x82,0x48,0x11,0x88,0x66,0x44,0x0B,0x18,0x8A,0x02,0x0B,0x40,0x0B,
++    0x1A,0x8A,0x04,0x0B,0x44,0x0B,0x1C,0x8A,0x06,0x0B,0x44,0x0B,0x1E,0x8A,0x00,0x0B,
++    0x38,0x82,0x4B,0x19,0x88,0xE6,0x47,0x0B,0x18,0x8A,0x04,0x0B,0x44,0x0B,0x1C,0x8A,
++    0x06,0x0B,0x44,0x0B,0x1E,0x8A,0x04,0x0B,0x40,0x0B,0x1A,0x8A,0x03,0x0B,0x3A,0x82,
++    0xAC,0x8D,0x87,0x3D,0xC0,0x3C,0xC8,0x3C,0x4C,0x00,0x00,0x00,0xC0,0x00,0x3A,0x00,
++    0x4A,0xDA,0x71,0x00,0xC1,0x28,0x42,0xDA,0x44,0x0B,0x90,0x4D,0x88,0x34,0x58,0x0B,
++    0x90,0x4D,0x8C,0x2C,0x5C,0x0B,0x92,0x4D,0x8C,0x24,0x58,0x0B,0x90,0x4D,0x8C,0x1C,
++    0x54,0x0B,0x96,0x75,0x4A,0xA2,0x41,0x53,0x90,0x95,0x94,0x14,0x44,0x53,0x90,0xBD,
++    0x44,0x13,0x92,0x95,0x91,0x0C,0x58,0x7A,0x98,0x01,0x52,0xD3,0x90,0x95,0x94,0x04,
++    0x10,0x09,0x00,0x13,0xA8,0x10,0x1C,0x13,0x12,0x81,0x18,0x13,0x18,0x13,0x14,0x79,
++    0x11,0x13,0x16,0x01,0x00,0x53,0x12,0x89,0x02,0x53,0x40,0x0B,0x10,0x81,0x19,0x8A,
++    0x07,0x0B,0x02,0xF9,0x80,0x89,0x17,0xC3,0x07,0x09,0xB8,0xFF,0xFF,0x7F,0x03,0xF9,
++    0x80,0x89,0x14,0xC3,0x07,0x09,0xB8,0xFF,0xF8,0x4F,0x03,0x19,0x11,0x00,0x00,0x43,
++    0x07,0x09,0xB8,0xFF,0xF8,0x1F,0x0B,0x11,0xC7,0x3C,0xB8,0xFF,0xF8,0x5F,0x23,0xA1,
++    0x01,0x01,0x40,0x4B,0x30,0x48,0xA8,0x16,0xE7,0x20,0x93,0x25,0x03,0x0F,0xF0,0x20,
++    0x92,0x25,0xE7,0x00,0x90,0x05,0x46,0x51,0x98,0x9E,0x0F,0x09,0xC7,0x3C,0xB8,0xFF,
++    0xF8,0xCF,0x42,0x82,0xC8,0x34,0x00,0x0B,0xC8,0x2C,0x18,0x0B,0xCA,0x24,0x18,0x0B,
++    0xCC,0x1C,0x18,0x0B,0x10,0x33,0x4E,0x62,0xD2,0x14,0x00,0x53,0x00,0x7B,0xC8,0x0C,
++    0x00,0x0B,0x4A,0x42,0xC2,0x04,0x88,0x01,0x10,0x43,0x60,0xA1,0xC8,0x16,0x00,0x09,
++    0x87,0x45,0xE8,0x85,0x07,0x01,0x38,0xDF,0x00,0xD0,0x00,0x01,0x80,0x00,0x00,0x42,
++    0x08,0x01,0x00,0x42,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0x00,0x0F,0x00,0x26,
++    0xF8,0x48,0x48,0x21,0x94,0xDE,0x3F,0x58,0xA8,0x0E,0x00,0x14,0xE6,0x00,0x3C,0x48,
++    0x80,0x06,0x80,0x13,0x38,0x82,0x4B,0x01,0x86,0x5E,0x38,0x18,0x80,0x16,0x80,0x13,
++    0xE2,0x00,0xF2,0x48,0x48,0x11,0x98,0x26,0x38,0x18,0xAC,0x16,0x04,0x14,0xE0,0x00,
++    0xF7,0x48,0x3C,0x1F,0x17,0x01,0x38,0x77,0x16,0x01,0x38,0xFF,0x10,0x01,0x48,0x18,
++    0x11,0x5A,0x9C,0x66,0x54,0x18,0x10,0x5A,0x98,0x8E,0x18,0x01,0x32,0xE2,0x04,0x77,
++    0x30,0x1A,0x18,0x5A,0xA0,0xE6,0x11,0x01,0x44,0x18,0x12,0x5A,0x98,0x8E,0x49,0x18,
++    0x10,0x5A,0x9C,0xE6,0x54,0x18,0x10,0x5A,0x9C,0x0E,0x30,0xA2,0x06,0xFF,0x49,0x18,
++    0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD6,0x00,0x0C,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,
++    0x0E,0x58,0xD4,0x00,0x0A,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD2,0x00,
++    0x08,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD0,0x00,0x0E,0x92,0x42,0x18,
++    0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD6,0x00,0x0C,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,
++    0x06,0x58,0xD4,0x00,0x0A,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD2,0x00,
++    0x0A,0x92,0xD2,0x08,0x90,0x06,0x30,0x0A,0x08,0x92,0x32,0x82,0x3A,0x82,0x03,0xEF,
++    0x78,0x50,0x86,0x06,0x10,0x4A,0x82,0x18,0x9A,0x06,0x10,0x02,0x00,0x9A,0x12,0x01,
++    0x30,0xE2,0x4C,0x18,0x11,0x5A,0x9C,0x6E,0x54,0x18,0x10,0x5A,0x9F,0x96,0x10,0xE1,
++    0x08,0x48,0xD4,0x95,0x54,0x18,0x10,0x5A,0x9C,0x66,0x08,0x48,0x8C,0x90,0x14,0x5A,
++    0x9C,0x46,0x08,0x48,0x8C,0x90,0x14,0x5A,0x9C,0x26,0x08,0x48,0x84,0xD6,0x89,0x90,
++    0x04,0x07,0x48,0x48,0x4C,0x18,0x16,0x5A,0x9E,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,
++    0x4C,0x18,0x14,0x5A,0x9C,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,0x4C,0x18,0x12,0x5A,
++    0x9A,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,0x4C,0x18,0x10,0x5A,0x98,0x0E,0x08,0x58,
++    0xD2,0x00,0x0E,0x92,0x44,0x18,0x16,0x5A,0x9E,0x0E,0x00,0x58,0xD2,0x00,0x0E,0x92,
++    0x44,0x18,0x14,0x5A,0x9C,0x0E,0x00,0x58,0xD2,0x00,0x0E,0x92,0x92,0xCE,0x46,0x18,
++    0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD2,0x00,0x0A,0x92,0xD2,0x08,0x90,0x06,0x30,0x0A,
++    0x32,0x1A,0x0B,0x92,0x80,0xD8,0x32,0x82,0x9A,0x0E,0x10,0x02,0x58,0x01,0xA8,0x06,
++    0x13,0x4A,0x3A,0x82,0x32,0x1A,0x83,0xD8,0x9A,0x06,0x10,0x02,0xA8,0x0D,0x00,0x01,
++    0x36,0x02,0x36,0x02,0xEB,0x15,0x30,0xAA,0x81,0x07,0xC0,0x17,0x30,0x72,0x05,0x28,
++    0x32,0x4A,0x33,0x9A,0x46,0x00,0x06,0x00,0x30,0x2A,0x84,0xC5,0xAF,0x05,0xB9,0xE7,
++    0xF3,0x6F,0xE4,0x05,0x3A,0x01,0x40,0x48,0x30,0xB2,0x35,0x01,0x2E,0x06,0x2E,0x06,
++    0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0xEA,0x01,0x02,0x48,
++    0x33,0x6A,0x3C,0x82,0x36,0x22,0x30,0x02,0x31,0x02,0x36,0x02,0xBA,0xDF,0xD7,0x5F,
++    0x43,0x02,0x38,0x82,0x88,0x20,0x00,0x01,0x40,0x12,0x48,0x1A,0xF3,0x5D,0x3D,0x82,
++    0x00,0x68,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x30,0x01,0x10,0x39,0x82,0xA3,0x85,
++    0x33,0xA2,0xF3,0x20,0xC3,0x2B,0xE1,0x20,0x10,0x5A,0x95,0x06,0x33,0xEA,0xE8,0x1A,
++    0x07,0xD8,0xC2,0x18,0xE0,0x85,0x39,0xC2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x80,0x20,0x03,0x42,0x80,0x20,0x03,0x42,0x80,0x20,0x04,0x42,
++    0x80,0x20,0x03,0x42,0x80,0xA0,0x04,0x42,0x80,0xA0,0x02,0x42,0x80,0xA0,0x04,0x42,
++    0x80,0xA0,0x02,0x42,0x80,0xA0,0x04,0x42,0x80,0xA0,0x02,0x42,0x80,0x20,0x05,0x42,
++    0x80,0xA0,0x02,0x42,0x80,0xA0,0x05,0x42,0x80,0x20,0x02,0x42,0x80,0x20,0x01,0x42,
++    0x80,0x20,0x01,0x42,0x80,0xA0,0x01,0x42,0x80,0xA0,0x01,0x42,0x80,0xA0,0x01,0x42,
++    0x10,0x20,0x08,0x40,0x40,0x08,0x20,0x10,0x10,0x20,0x08,0x40,0x40,0x08,0x20,0x40,
++    0x10,0x20,0x00,0x08,0x08,0xC1,0x02,0x42,0x08,0x81,0x02,0x42,0x08,0x81,0x03,0x42,
++    0x08,0x41,0x03,0x42,0x08,0x01,0x03,0x42,0x08,0x81,0x02,0x42,0x08,0x41,0x02,0x42,
++    0x08,0xC1,0x00,0x42,0x08,0x01,0x02,0x42,0x08,0x01,0x01,0x42,0x08,0xC1,0x01,0x42,
++    0x08,0x41,0x01,0x42,0x08,0x81,0x01,0x42,0x08,0x81,0x01,0x42,0x08,0x41,0x01,0x42,
++    0x08,0xC1,0x02,0x42,0x08,0x01,0x01,0x42,0x08,0x01,0x03,0x42,0x08,0xC1,0x00,0x42,
++    0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x00,0x00,
++    0x00,0x08,0xF8,0x0F,0xFF,0x07,0xF8,0xFF,0x07,0xF8,0x0F,0xF8,0x08,0x00,0x08,0x08,
++    0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x28,0xB5,0x39,0xC5,0x08,0x1D,
++    0x1B,0x2B,0x3A,0x28,0x53,0xB5,0x0A,0xC5,0x00,0x08,0x01,0x00,0x01,0x00,0x50,0x0D,
++    0x52,0x1D,0x52,0xB5,0x39,0x0D,0x04,0x08,0x51,0x3D,0x53,0x1D,0x51,0x3D,0x54,0x95,
++    0x51,0x3D,0x54,0x95,0x51,0x3D,0x54,0x95,0x0B,0x3D,0x34,0x88,0x51,0x3D,0x54,0x1D,
++    0x51,0x3D,0x54,0x95,0x04,0x00,0x50,0x3D,0x50,0x1D,0x01,0x00,0x00,0x00,0x00,0x00,
++    0x54,0x2D,0x53,0x3D,0x32,0x8D,0x32,0x38,0x01,0x28,0x0A,0x45,0x50,0xB5,0x53,0x95,
++    0x00,0x00,0x00,0x00,0x52,0xA5,0x51,0xB5,0x09,0xC5,0x03,0x08,0x03,0x00,0x50,0x3D,
++    0x55,0x1D,0x51,0x0D,0x51,0x3D,0x54,0x95,0x51,0x3D,0x53,0x1D,0x51,0x3D,0x54,0x95,
++    0x51,0x0D,0x55,0x0D,0x54,0xB5,0x3A,0x0D,0x00,0x08,0x01,0x00,0x53,0xA5,0x51,0x2D,
++    0x52,0x3D,0x34,0x8A,0x1D,0x38,0x52,0x45,0x52,0x0D,0x51,0x1D,0x54,0xB5,0x3A,0x0D,
++    0x53,0xA5,0x29,0xB5,0x39,0xC5,0x08,0x1D,0x19,0x2D,0x22,0x1D,0x44,0x0D,0x31,0x3D,
++    0x23,0x95,0x09,0xC1,0x29,0xB5,0x0B,0x1D,0x1B,0x2B,0x3A,0x28,0x00,0x00,0x00,0x08,
++    0xFF,0x07,0x00,0xF8,0x08,0x00,0x10,0x10,0x08,0x10,0x10,0x10,0x08,0x08,0x10,0x08,
++    0x10,0x08,0x10,0x08,0x10,0x10,0x08,0x08,0x10,0x10,0x08,0x08,0x08,0x08,0x10,0x10,
++    0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x08,
++    0xF8,0x07,0x08,0x00,0x08,0x08,0x00,0x00,0x78,0x42,0x00,0x00,0x00,0x00,0x00,0x01,
++    0x00,0xE0,0x00,0x00,0x00,0x00,0x05,0x00,0x78,0x22,0x01,0x00,0x00,0xE0,0x00,0x01,
++    0x88,0x40,0x02,0x00,0x00,0xE0,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xD1,0xDA,0xAA,0xA9,0x2E,0x2D,0x55,0x56,0xBB,0x43,0xAC,0x32,
++    0x99,0x21,0x8A,0x10,0x00,0x70,0x00,0x28,0x09,0x00,0x1F,0x00,0x06,0x78,0x50,0x56,
++    0xFF,0xFF,0xFF,0xFF,0xB2,0x30,0x08,0x40,0x00,0x40,0x20,0x00,0x03,0x13,0x2A,0xC7,
++    0x0F,0x00,0xCA,0xCA,0xFF,0xFF,0xFF,0xFF,0x06,0x16,0x48,0x01,0x08,0x00,0x00,0x04,
++    0x42,0x60,0x78,0xE5,0xD8,0xB9,0xCC,0x04
++};
++
++
++#define FW_INFO_SIZE	(0x18)
++#define FW_REAL_SIZE	(sizeof(fwbin))
++#define FW_BIN_SIZE		(24*1024+24)	    //24K byte
++
++#endif
++
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/hyn_cst3xx_RS659_fw_0730_268_800.h b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/hyn_cst3xx_RS659_fw_0730_268_800.h
+new file mode 100644
+index 000000000..3bd6f0b32
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Original_driver/hyn_cst3xx_RS659_fw_0730_268_800.h
+@@ -0,0 +1,1552 @@
++
++#ifndef __CST3xx_FW_H__
++#define __CST3xx_FW_H__
++
++  unsigned char cst3_fw[] ={
++    0x98,0xE0,0x07,0x01,0xC8,0x88,0x02,0x00,0x00,0x00,0x00,0x00,0xC8,0x48,0x02,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x98,0x88,0x00,0x00,0x98,0x88,0x01,0x00,0x00,0x00,0x00,0x00,
++    0x98,0x28,0x02,0x00,0x00,0x00,0x00,0x00,0x98,0xF8,0x02,0x00,0x80,0x07,0xC0,0x17,
++    0x82,0x07,0xC0,0x07,0x01,0x65,0x40,0x86,0xC1,0x41,0xC0,0x20,0xC5,0x68,0x31,0x12,
++    0xF5,0x38,0x33,0x5A,0x32,0xA2,0x32,0xEA,0x10,0x62,0x8D,0x0E,0x81,0x07,0xC0,0x97,
++    0x30,0xF2,0xF3,0x79,0x65,0x7E,0x30,0xB2,0x31,0x09,0x10,0x9A,0x87,0x06,0xD0,0xD8,
++    0x35,0x12,0x35,0x5A,0x18,0x9A,0x39,0xC2,0x70,0xE2,0x02,0x00,0x70,0xE2,0x03,0x00,
++    0xD0,0x81,0x98,0x16,0x43,0xC6,0x0B,0xC6,0xC2,0xD6,0x3F,0x90,0x99,0x0E,0x40,0x86,
++    0x08,0x86,0xA9,0x0E,0x40,0x23,0x00,0x63,0x38,0x82,0x03,0x00,0x18,0x01,0x20,0x01,
++    0x28,0x01,0x30,0x01,0xD0,0x81,0x98,0x0E,0x0F,0xC6,0xC3,0xDE,0x38,0x90,0x9A,0x06,
++    0x08,0x86,0xA9,0x06,0x03,0x5B,0x38,0x82,0xAE,0xFD,0x30,0x02,0x30,0x02,0xEE,0xFD,
++    0xA8,0x85,0xE8,0x85,0x84,0x27,0xE8,0xEF,0x37,0x8A,0xB8,0xFF,0xF8,0xAF,0x87,0x0F,
++    0xD0,0x2F,0x81,0x27,0xEF,0xAF,0xBD,0xFF,0xF8,0x9F,0x87,0x27,0xE8,0xDF,0x05,0x00,
++    0xAF,0x85,0x6F,0xFA,0x39,0x01,0xC0,0x43,0x37,0x4A,0xC9,0x01,0x38,0x30,0x32,0x42,
++    0x86,0x01,0xC5,0x1B,0xCE,0x23,0xF0,0x53,0xC0,0x01,0x74,0x01,0xDD,0x16,0xC0,0x6B,
++    0x48,0x68,0x87,0x3E,0xAA,0x7B,0xAC,0x3B,0x10,0xD2,0x8C,0x16,0xB0,0x63,0x06,0x09,
++    0xB7,0x43,0xEC,0x85,0x34,0x6A,0xE8,0x4B,0xE6,0x48,0x92,0x4D,0xAF,0x4B,0x4D,0xF9,
++    0x8D,0x0E,0x10,0x12,0x82,0x16,0xE8,0x0B,0x48,0x09,0x88,0x1E,0xB5,0x5B,0xAF,0x7B,
++    0xAF,0x3B,0xEA,0x85,0x4F,0x09,0x8C,0xE6,0x0A,0x09,0xA8,0x0B,0xE8,0x85,0xAF,0x85,
++    0x67,0x3A,0xE7,0x01,0x00,0x0F,0x80,0x0F,0xF5,0x4F,0xF0,0x03,0x47,0x01,0x80,0xD6,
++    0xEF,0x85,0xA8,0xC5,0x00,0x21,0x80,0x0F,0xE8,0x9F,0x07,0x09,0x87,0x0F,0xE8,0x87,
++    0x79,0x02,0x47,0xC3,0x0C,0x01,0x19,0x42,0x00,0xC3,0x01,0x11,0x86,0x0F,0xE8,0xEF,
++    0x61,0xEA,0x56,0x03,0x29,0x41,0x18,0x42,0x17,0x03,0x49,0x03,0x1F,0x42,0x09,0x03,
++    0x15,0x2B,0x4B,0x03,0x1D,0x42,0x09,0x03,0x4D,0x03,0x1B,0x42,0x0B,0x03,0x4B,0x03,
++    0x35,0x21,0x18,0x82,0x0B,0x03,0x4B,0x03,0x42,0x00,0x02,0x00,0x09,0x03,0x4B,0x03,
++    0x19,0x42,0x09,0x03,0x49,0x03,0x19,0x82,0x09,0x03,0x49,0x03,0x08,0x09,0x18,0x42,
++    0x0F,0x03,0x41,0x03,0x1F,0x42,0x05,0x03,0x45,0x03,0x1F,0x82,0x07,0x03,0x47,0x03,
++    0x1F,0x42,0x04,0x03,0x45,0x03,0x1D,0x42,0x05,0x03,0x45,0x03,0x1D,0x82,0x05,0x03,
++    0x45,0x03,0x1B,0x42,0x03,0x03,0x43,0x03,0x1B,0x82,0x05,0x03,0x44,0x03,0x1D,0x42,
++    0x03,0x03,0x45,0x03,0x1B,0x42,0x04,0x03,0x0E,0x81,0x42,0x02,0x82,0x27,0xE0,0xC7,
++    0x85,0x0F,0xE8,0xB7,0x85,0x0F,0xE8,0x97,0x85,0x0F,0xE8,0xC7,0x48,0xE2,0x05,0x01,
++    0x1D,0x43,0x4C,0x03,0x1D,0x42,0x0D,0x03,0x10,0x2B,0x03,0x11,0x84,0x0F,0xE8,0xC7,
++    0x41,0xC3,0x09,0x01,0x19,0x42,0x00,0xC3,0x00,0x21,0x80,0x0F,0xE8,0x37,0x04,0x09,
++    0x84,0x0F,0xE8,0x1F,0x42,0x03,0x41,0x00,0x01,0x00,0x02,0x03,0x40,0x03,0x0F,0x09,
++    0x1F,0x42,0x00,0x03,0x4C,0x03,0x1B,0x42,0x09,0x03,0x4B,0x03,0x19,0x42,0x0C,0x03,
++    0x41,0x03,0x1D,0x42,0x05,0x03,0x45,0x03,0x1D,0x82,0x01,0x03,0x41,0x03,0x1B,0x42,
++    0x03,0x03,0x43,0x03,0x1B,0x82,0x01,0x03,0x48,0x0B,0x03,0x61,0x1B,0x0A,0x08,0x0B,
++    0x48,0x0B,0x19,0x0A,0x0F,0x0B,0x41,0x0B,0x1F,0x0A,0x00,0x0B,0x48,0xE2,0x04,0x09,
++    0xC8,0x01,0xAF,0x43,0x83,0x0F,0xD0,0x07,0xEC,0xC5,0x47,0xCA,0xC6,0x01,0xF3,0x0B,
++    0x42,0xCA,0x84,0x01,0x48,0x01,0x80,0x3E,0x4A,0xD2,0x04,0x0B,0x0C,0xF9,0x57,0xB2,
++    0x8C,0x89,0x97,0x01,0x10,0x8B,0x00,0x17,0x48,0xB2,0xCC,0xE1,0x07,0x0B,0x12,0xF9,
++    0x96,0xA1,0x02,0x13,0x08,0x31,0x08,0x0B,0x0C,0x11,0x08,0x0B,0x0A,0x51,0x08,0x0B,
++    0x0C,0x49,0x18,0x0B,0x18,0x0B,0x0A,0x01,0x1C,0x0B,0x40,0x4A,0xC2,0x01,0x0F,0x14,
++    0x3F,0x82,0xAB,0x85,0x70,0x62,0x0C,0x01,0x2C,0x01,0x60,0x62,0x50,0x62,0x04,0x01,
++    0xA4,0x82,0x02,0x40,0x50,0x5A,0xC4,0x40,0xC4,0x00,0x54,0x5A,0xC0,0x10,0x1C,0x01,
++    0xC6,0x83,0x01,0x38,0xC1,0x83,0xD0,0xC0,0x94,0x05,0x14,0x2A,0x90,0x06,0x30,0x2A,
++    0x10,0x22,0xCC,0x06,0x32,0x22,0xE0,0x90,0xE6,0xD8,0x92,0xDD,0x5F,0x29,0x98,0x8E,
++    0x59,0xFA,0xDB,0x40,0xA3,0xC2,0xE2,0xB0,0xE6,0x48,0x92,0x4D,0x4E,0x71,0x98,0xDE,
++    0x48,0xD2,0x03,0x01,0xE4,0xD2,0x10,0x52,0x90,0x06,0x30,0x8A,0xE6,0x00,0x92,0x05,
++    0x47,0x71,0x98,0xBE,0x50,0xCA,0x03,0x01,0x00,0x84,0xE0,0xE2,0x43,0xAC,0xD0,0x20,
++    0xC8,0x20,0x03,0xA4,0xE6,0x00,0x92,0x05,0x47,0x71,0x98,0xB6,0x47,0x84,0x40,0xF9,
++    0xCF,0x0E,0x00,0xF9,0x03,0x84,0x48,0x92,0x40,0x84,0x80,0x43,0xE8,0x85,0xAF,0x85,
++    0x40,0x1A,0xC3,0x03,0x38,0x00,0x86,0xAE,0x00,0x01,0x85,0x0F,0xD3,0xAF,0x60,0x02,
++    0x01,0x01,0xE0,0x01,0x8F,0x03,0xB9,0xFF,0xF9,0x47,0x34,0x0A,0x56,0x4A,0xCB,0x01,
++    0x40,0x22,0x83,0x1F,0xD0,0x6F,0x04,0x11,0x88,0x03,0x01,0x01,0x86,0x0F,0xC8,0xE7,
++    0xBC,0xFF,0xFF,0xFF,0xE8,0x85,0xA8,0x85,0x41,0xAA,0xC2,0x01,0xC8,0x03,0x42,0x01,
++    0x8A,0x36,0x40,0x9A,0xC0,0x01,0xEF,0x03,0x40,0x29,0xC8,0x0E,0xBE,0xFF,0xF7,0x7F,
++    0x61,0x7A,0xC2,0x03,0x38,0x00,0xA8,0x0E,0xBE,0xFF,0xF7,0x9F,0xC3,0x03,0xC3,0x03,
++    0x08,0xE9,0x07,0x42,0x82,0x03,0x43,0xC2,0xC0,0x03,0x40,0x01,0x80,0x16,0x80,0x0F,
++    0xE7,0x6F,0x3E,0xE7,0xE8,0x85,0xA8,0x85,0x48,0x32,0x02,0x01,0x02,0x43,0x4C,0x22,
++    0xCC,0x01,0xB7,0x43,0xF0,0x43,0x86,0x0F,0xC8,0xBF,0xEE,0x85,0xA8,0x85,0x33,0x2A,
++    0x48,0x01,0x80,0x4E,0x68,0x01,0x80,0x1E,0x30,0x82,0xC0,0x51,0x20,0x01,0x00,0x5F,
++    0x30,0x82,0x80,0x51,0x20,0x01,0x00,0x3F,0x68,0x01,0x80,0x1E,0xF0,0x80,0x24,0x49,
++    0x18,0x22,0x07,0x0F,0xE0,0x80,0x24,0x51,0x0A,0x01,0xF0,0x0A,0x48,0x01,0xD0,0x06,
++    0x16,0x4A,0x0A,0x40,0x0A,0x01,0xF0,0x8A,0x82,0x27,0xD8,0x87,0x40,0xF9,0xEB,0x06,
++    0x00,0xF9,0x6B,0x01,0x87,0x16,0x08,0xF9,0x88,0x09,0xD0,0x40,0xCB,0x00,0xE8,0x85,
++    0xAC,0x85,0x87,0x3D,0x28,0x01,0x20,0x01,0x01,0x51,0x48,0x92,0x1A,0x42,0xC3,0x00,
++    0x80,0x34,0xC0,0x34,0x01,0x08,0x13,0x39,0xC4,0x00,0x0A,0x90,0xC0,0x10,0x04,0xE1,
++    0x90,0x2C,0xF0,0x82,0x80,0x24,0x30,0x01,0x38,0x01,0x10,0x01,0x90,0x1C,0x90,0x14,
++    0x60,0x01,0x80,0x46,0xF0,0x10,0xDB,0x34,0x04,0x90,0xC2,0xD0,0x1C,0x39,0x09,0xD8,
++    0xC0,0x90,0x36,0xE1,0xF8,0xB2,0x6C,0x01,0x83,0x56,0xF0,0x50,0x1A,0x51,0x18,0xD2,
++    0x5E,0x02,0xC1,0x90,0x1A,0x39,0xC1,0x90,0x0E,0xD8,0xC4,0x90,0x3E,0xE1,0xF8,0xBA,
++    0x60,0x21,0x80,0x4E,0xE0,0x18,0xD3,0x34,0x06,0xD8,0xC2,0x90,0x1C,0x39,0x09,0xD8,
++    0xC0,0x90,0x1E,0xE1,0xF0,0x9A,0x9E,0x1C,0x68,0x69,0x80,0x5E,0xE0,0x50,0x1B,0x51,
++    0x18,0xD2,0x5A,0xA2,0xC2,0x90,0xC6,0x88,0x14,0x39,0x09,0x90,0xC0,0x50,0x0C,0xE1,
++    0xF0,0x8A,0x8A,0x14,0x08,0x09,0x88,0x0C,0x70,0x41,0xD1,0x3E,0x78,0x41,0xD1,0x2E,
++    0xC9,0x1C,0x48,0x41,0xD0,0x16,0xC8,0x14,0x49,0x41,0xD9,0x06,0x08,0x01,0x00,0xEF,
++    0x00,0xE0,0x07,0x01,0x10,0x00,0x00,0x42,0xF8,0x00,0x06,0x42,0x80,0x30,0x02,0x01,
++    0x18,0x00,0x02,0x42,0x80,0x60,0x05,0x00,0x70,0x00,0x04,0x01,0xF8,0xFF,0x07,0x00,
++    0x80,0x50,0x06,0x01,0x08,0x40,0x00,0x01,0x60,0x20,0x02,0x00,0x00,0x60,0x00,0x01,
++    0x00,0x28,0x00,0x01,0x80,0xC0,0x04,0x01,0x00,0x20,0x00,0x01,0x88,0x0C,0x08,0x19,
++    0x86,0x27,0xD0,0x67,0x10,0x82,0xED,0x3E,0x10,0xC2,0xED,0x2E,0xCC,0x1C,0x10,0x42,
++    0xE8,0x16,0xC8,0x14,0x10,0x42,0xE4,0x0E,0x00,0x01,0x80,0x0C,0xC0,0x0C,0x40,0x01,
++    0x80,0x86,0xC8,0x24,0xD6,0x2C,0x78,0x40,0xC2,0x00,0x82,0x00,0xD0,0x48,0x90,0x4D,
++    0x1F,0x8C,0x54,0xFA,0x58,0xFA,0xC7,0x93,0xC0,0xDB,0x18,0xD2,0x80,0x16,0xD0,0x40,
++    0xCC,0x2C,0x18,0x44,0xE7,0x20,0x93,0x25,0x60,0x29,0x90,0x06,0x3B,0x4F,0xE3,0x68,
++    0x90,0x6D,0x6F,0x71,0x92,0x06,0x38,0xF7,0x87,0x3D,0xE8,0x85,0xA8,0xC5,0x2F,0x01,
++    0x40,0xAA,0xFF,0x03,0x81,0x04,0x00,0x5F,0x07,0x31,0x48,0xA2,0x1A,0x42,0xC3,0x00,
++    0x0C,0xC9,0x09,0x48,0xC0,0x30,0x3A,0x11,0xF8,0xBA,0x07,0x21,0xF0,0x82,0x41,0x51,
++    0xD0,0x0E,0x20,0x51,0x00,0x0F,0xC0,0x51,0x96,0x25,0x00,0x19,0x04,0x00,0x14,0x22,
++    0xE8,0x06,0x30,0x22,0x37,0x02,0xC1,0xF9,0xC0,0x89,0x0C,0xF1,0x1F,0x42,0x0A,0xF9,
++    0x88,0x89,0x84,0x27,0xD0,0xDF,0xCB,0x00,0x90,0x05,0x40,0x51,0xD0,0x06,0x00,0x51,
++    0x4C,0x1A,0x17,0x42,0xE8,0x06,0x30,0x42,0x05,0xBC,0x03,0x84,0xE7,0x68,0x93,0x6D,
++    0xC5,0x04,0x10,0x42,0xC7,0x86,0xEE,0xC5,0xAC,0x85,0x87,0x3D,0x00,0xF9,0x87,0x0C,
++    0x00,0x01,0x80,0x04,0x81,0x14,0x18,0x39,0x09,0xD8,0x24,0x39,0x57,0xBA,0x1E,0x22,
++    0x04,0x08,0xC2,0x48,0xC0,0x68,0x0E,0xE1,0xF2,0x4A,0xE3,0x00,0x92,0x05,0x40,0x31,
++    0xD8,0xB6,0x07,0x01,0x80,0x24,0x00,0x01,0x38,0x01,0x28,0x01,0x30,0xF9,0xCF,0x24,
++    0x12,0x51,0x18,0x8A,0x54,0x6A,0xC6,0x48,0x54,0x72,0xC6,0x50,0x90,0x34,0x08,0x01,
++    0x20,0x01,0xF8,0xA2,0x60,0xA1,0xE8,0x0E,0xE1,0xF8,0x93,0xFD,0xC0,0x00,0x91,0x05,
++    0x10,0x62,0xED,0x06,0x35,0x2A,0x11,0xA2,0xD1,0x06,0x30,0x32,0xE2,0x90,0xE4,0x48,
++    0x90,0x4D,0x4E,0x29,0x99,0x66,0x6F,0xE1,0xED,0x16,0x50,0xFA,0x0C,0x01,0xA8,0x8B,
++    0x08,0x29,0x80,0x27,0xD0,0x5F,0x91,0x0D,0xD0,0x40,0x83,0x71,0x40,0xE1,0xC0,0x6E,
++    0xD0,0x80,0x83,0x71,0x40,0xE1,0xC0,0x4E,0x68,0xE1,0xE9,0x3E,0x78,0x21,0xE8,0x2E,
++    0x50,0xA2,0x05,0x01,0x85,0x83,0x40,0x92,0x10,0xD1,0x87,0x13,0xC4,0x14,0x10,0x42,
++    0xD0,0x06,0x88,0x14,0xC5,0x0C,0x10,0x82,0xE8,0x06,0xB0,0x0C,0xC5,0x04,0x10,0x42,
++    0xD0,0x06,0xA8,0x04,0x6D,0x6A,0x75,0x7A,0xC0,0x34,0x18,0x01,0x48,0x01,0xE8,0xBE,
++    0x14,0x01,0xF0,0x12,0x10,0x52,0xDC,0x76,0x61,0x2A,0xC5,0x23,0x60,0x01,0x80,0x16,
++    0xD0,0x90,0x02,0x14,0x01,0xC7,0x50,0xE1,0xD6,0xB6,0x78,0x60,0xC3,0x20,0x83,0x20,
++    0xD8,0x90,0x00,0x14,0x00,0x87,0x50,0x01,0xE8,0x76,0x10,0x09,0x00,0x14,0x00,0x5F,
++    0x14,0x01,0xF0,0x12,0x10,0x52,0xE4,0x16,0xD0,0x90,0x02,0x14,0x00,0x27,0x50,0x01,
++    0xD0,0x16,0x10,0x01,0x18,0x92,0x06,0x14,0xE2,0x00,0xE4,0xD8,0x90,0xDD,0x5E,0x29,
++    0x98,0xA6,0xC6,0x24,0xE6,0x00,0x92,0x05,0x80,0x24,0xC0,0x24,0x44,0x71,0x98,0x16,
++    0x20,0x01,0x00,0x01,0x08,0x01,0x10,0x01,0x94,0x1C,0x50,0x82,0x04,0x18,0xC3,0xD0,
++    0x5E,0x82,0xC4,0xA8,0x30,0x72,0x19,0x01,0x15,0x01,0xF0,0x52,0xC0,0x80,0x90,0x05,
++    0xE0,0x48,0x92,0x4D,0xFD,0x1C,0x10,0xD2,0xE8,0x06,0x90,0x1C,0xAA,0x51,0xE0,0xD8,
++    0x90,0xDD,0x5E,0x71,0x98,0x86,0x87,0x27,0xC8,0xCF,0x95,0x2D,0xC5,0x14,0x10,0x42,
++    0xD0,0x06,0xA8,0x14,0x00,0x01,0x80,0x24,0x68,0x01,0xE8,0xDE,0x3F,0x01,0xF8,0xBA,
++    0x10,0x7A,0xDD,0x96,0x60,0x01,0x80,0x0E,0x60,0x21,0x88,0x16,0xD9,0xC0,0x03,0x84,
++    0x00,0xB7,0x08,0x19,0xC0,0x1C,0x80,0x27,0xCD,0x0F,0x15,0x42,0xD7,0x86,0x78,0x40,
++    0xCA,0x00,0x82,0x00,0xD1,0xC0,0x01,0x84,0x00,0x57,0x78,0x01,0xE8,0x46,0x00,0x09,
++    0x00,0x84,0x01,0x2F,0x01,0x01,0xF0,0x82,0x10,0x42,0xE5,0x0E,0xD9,0x00,0x02,0x84,
++    0xB0,0x51,0xC0,0x24,0xE6,0x00,0x92,0x05,0x80,0x24,0xC0,0x24,0x46,0x71,0x98,0x9E,
++    0xE7,0x20,0x93,0x25,0x65,0x29,0x98,0x66,0x43,0x2A,0x4B,0x32,0xC0,0x03,0xC0,0x4B,
++    0x33,0x22,0x58,0x4A,0x50,0x4A,0x1B,0x62,0x88,0xB6,0x01,0x01,0x4A,0x1A,0x03,0x20,
++    0xC3,0x08,0x63,0x22,0xCB,0x60,0x68,0x1A,0xAA,0x51,0xC8,0x68,0x31,0xF9,0x0C,0xB0,
++    0xC8,0x78,0x34,0x01,0xF8,0xF2,0x3D,0x01,0xFD,0x7A,0x17,0xF2,0xD0,0x3E,0x28,0x01,
++    0xF8,0x2A,0x6B,0xA1,0xE8,0x1E,0x78,0x79,0xEB,0x0E,0x00,0x68,0x02,0x2C,0x61,0xD2,
++    0xA0,0x51,0xC8,0x60,0xC4,0x70,0xC6,0x68,0x0B,0x01,0xF0,0x4A,0x2B,0x01,0xF8,0xAA,
++    0x10,0x4A,0xD5,0x66,0x0B,0x01,0xF0,0x0A,0x48,0xA1,0xE8,0x46,0x68,0x79,0xE8,0x36,
++    0x7B,0x70,0xC6,0xA8,0x83,0x68,0x03,0x70,0xCB,0x68,0xC5,0x48,0x02,0x0C,0xE1,0x00,
++    0x90,0x05,0x46,0x29,0x9C,0x56,0x36,0xFF,0x47,0x01,0x80,0xE6,0x22,0x01,0x40,0x3A,
++    0x00,0x08,0xC3,0x68,0x41,0x3A,0xC2,0x70,0x40,0x32,0x82,0x51,0xC4,0x40,0x09,0xF9,
++    0x0B,0x48,0xC0,0x78,0x10,0x01,0x08,0x01,0xF2,0xD2,0xF5,0x0A,0x10,0x52,0xD4,0x6E,
++    0x01,0x01,0xF0,0x82,0x81,0x2C,0x40,0x41,0xE8,0x46,0x48,0x79,0xEC,0x36,0x00,0x00,
++    0x08,0x29,0x80,0x27,0xC8,0x1F,0xC9,0x2C,0xC1,0x00,0x02,0x84,0x40,0xD2,0x81,0x51,
++    0xC1,0x40,0x49,0xD2,0xC0,0x48,0x1B,0x01,0x17,0x01,0xF0,0xDA,0xF4,0x52,0x14,0x9A,
++    0xD0,0x3E,0x08,0x01,0xF1,0x0A,0x4A,0x41,0xE8,0x1E,0x50,0x79,0xEA,0x0E,0x00,0x48,
++    0x03,0x0C,0xE0,0x20,0x90,0x25,0x67,0x29,0x9B,0x4E,0x36,0x2F,0xA9,0xC5,0x47,0x52,
++    0x17,0x09,0x80,0x01,0xC0,0x0B,0x18,0x8A,0x81,0x0B,0x68,0x3A,0x79,0x22,0x31,0x62,
++    0xA4,0x01,0x06,0x27,0xBB,0xFF,0xEF,0xFF,0x48,0x4A,0x41,0x43,0xE0,0x00,0x02,0x43,
++    0x40,0x42,0xC1,0x03,0x40,0x01,0x80,0x0E,0x05,0xC1,0xB0,0x43,0x40,0xF2,0x80,0x1F,
++    0xE9,0x17,0x51,0x2A,0x48,0xEA,0x40,0xE2,0x86,0x1F,0xC8,0x6F,0xB9,0xFF,0xEF,0x7F,
++    0x01,0x11,0x88,0x03,0x50,0x02,0x49,0xC2,0x40,0xC2,0x80,0x1F,0xD8,0x67,0x55,0xF2,
++    0x48,0xAA,0x40,0xB2,0x86,0x1F,0xF8,0x17,0xC8,0x03,0x43,0x01,0x83,0x16,0xC8,0x03,
++    0x40,0x11,0x88,0x26,0x48,0xCA,0x40,0x43,0x10,0x09,0x18,0x82,0x00,0x43,0x48,0x72,
++    0x40,0x72,0x80,0x1F,0xF0,0x77,0x73,0x5A,0xC1,0xCB,0xC1,0x83,0x18,0x42,0x80,0x0E,
++    0x05,0x01,0xA8,0x43,0xBA,0xFF,0xF7,0xC7,0x41,0x8A,0xC0,0x8B,0x09,0x0C,0xC6,0xCB,
++    0x11,0x0C,0xC8,0x4B,0x10,0x0C,0x72,0x22,0xB5,0x01,0xE2,0x8B,0x10,0x0C,0x04,0xCF,
++    0x00,0x48,0x00,0x01,0x00,0x40,0x00,0x01,0x00,0xE0,0x00,0x01,0x08,0x40,0x00,0x01,
++    0x18,0x10,0x00,0x00,0x48,0xE0,0x06,0x00,0x50,0xA0,0x02,0x00,0x50,0x50,0x02,0x00,
++    0x00,0xA0,0x00,0x01,0x00,0x20,0x00,0x01,0x80,0xC0,0x04,0x01,0xF8,0x00,0x06,0x42,
++    0x70,0x40,0x04,0x01,0x48,0xA2,0x40,0x4C,0x10,0x0C,0x4E,0xA2,0x40,0x4B,0x18,0x0C,
++    0xA2,0x48,0x18,0x0C,0xEC,0x4B,0x1D,0x0C,0xBA,0xFF,0xEF,0x57,0x05,0x11,0xA0,0x83,
++    0x32,0x8A,0xC9,0x01,0x40,0x72,0x80,0x1F,0xE9,0xCF,0x31,0x8A,0x12,0x09,0xC8,0x01,
++    0x40,0x5A,0x58,0x62,0x81,0x17,0xE8,0x07,0xBC,0xFF,0xDF,0x97,0x32,0x8A,0xC9,0x01,
++    0x40,0x3A,0x80,0x0F,0xF0,0x0F,0x83,0x07,0xDF,0xCF,0xBA,0xFF,0xE3,0xE7,0xCE,0x03,
++    0x40,0x31,0x80,0x06,0x3F,0xB7,0xEB,0xC5,0x00,0x60,0x00,0x01,0x00,0xA0,0x00,0x01,
++    0x08,0x40,0x00,0x01,0x30,0x48,0x00,0x00,0xA8,0x85,0x33,0x22,0xF0,0x03,0x87,0x07,
++    0xF2,0x5F,0x46,0x7A,0x2C,0x01,0x00,0x2B,0xB6,0x2B,0x05,0x21,0xAF,0x2A,0xB8,0xFF,
++    0xE5,0xE7,0xA1,0x01,0xCA,0x03,0x33,0x08,0x42,0x52,0x72,0x48,0x1C,0x0B,0x5C,0x0B,
++    0x02,0x48,0x1A,0x0B,0x0B,0x2B,0xCE,0x0B,0x30,0x48,0xA8,0x16,0x0E,0x09,0x04,0x0B,
++    0x1B,0x2B,0xE8,0x85,0xAD,0x85,0x87,0xAD,0x42,0x12,0xC2,0x01,0x42,0x0B,0x40,0x48,
++    0x00,0x48,0x02,0x0B,0x52,0x02,0x4A,0x0A,0x40,0x0A,0x82,0x0F,0xCA,0xE7,0x40,0x0A,
++    0x71,0xFA,0xC1,0x80,0x81,0xA4,0x41,0xEA,0xB6,0xE1,0x81,0x01,0x83,0x9C,0x01,0x47,
++    0x47,0xD2,0xB9,0xFF,0xF9,0x4F,0x66,0xCA,0x52,0x03,0x83,0x01,0xE7,0x03,0x40,0x79,
++    0x81,0x06,0x31,0x12,0x48,0xB2,0x01,0x01,0x58,0x9A,0x81,0x07,0xF9,0x8F,0x36,0x12,
++    0x48,0x9A,0x01,0x09,0x58,0x82,0x81,0x07,0xFB,0x5F,0x56,0x03,0x80,0x01,0xE2,0x03,
++    0x40,0x59,0x8D,0x7E,0xC1,0xA4,0x31,0x8A,0x13,0x01,0xD8,0x1B,0xDB,0x2B,0x19,0x5A,
++    0x40,0x6C,0x40,0x3C,0xD8,0x68,0x07,0x2C,0xE4,0x00,0xE4,0x48,0xE4,0x90,0x92,0x95,
++    0x17,0xD2,0x9C,0xAE,0x52,0x03,0x83,0x01,0xE5,0x03,0x40,0x59,0x81,0x2E,0x50,0x12,
++    0x49,0x12,0x41,0x1A,0x58,0x0D,0x80,0x0F,0xC1,0x37,0xEC,0xA4,0x30,0xA2,0x39,0x01,
++    0x01,0x01,0xF0,0x42,0x0A,0x99,0x18,0x42,0x08,0x51,0x80,0x1F,0xF9,0xBF,0x07,0x44,
++    0x01,0x01,0xF0,0x02,0x0A,0x99,0x18,0x42,0x08,0x51,0x80,0x1F,0xF9,0x7F,0x07,0x04,
++    0xE5,0x68,0xE5,0x20,0xE7,0xF8,0x93,0xFD,0x7F,0x29,0x98,0x4E,0x68,0xB2,0x60,0xA2,
++    0xA0,0xF1,0x3D,0x01,0x01,0x01,0xF0,0x42,0x08,0x51,0x08,0x00,0x86,0x1F,0xF8,0xF7,
++    0x00,0x44,0x01,0x01,0xF0,0x02,0x09,0x51,0x08,0x00,0x80,0x1F,0xF9,0xBF,0x06,0x04,
++    0xE5,0x68,0xE5,0x20,0xE7,0xF8,0x93,0xFD,0x7F,0x29,0x98,0x5E,0x40,0x0D,0x80,0x07,
++    0xD9,0x9F,0xC2,0x9C,0xC8,0x03,0x42,0x31,0x81,0x96,0x84,0xAD,0xE8,0x85,0x07,0x00,
++    0x10,0x00,0x00,0x42,0x00,0x01,0x00,0x42,0x80,0xC0,0x04,0x01,0x00,0xE0,0x00,0x01,
++    0x08,0x40,0x00,0x01,0x48,0xE0,0x06,0x00,0x58,0x30,0x03,0x01,0x48,0xFA,0xFF,0x53,
++    0x84,0x13,0xF8,0x53,0x80,0x13,0x32,0x52,0x96,0x01,0xCE,0x93,0x80,0x13,0xCC,0x4B,
++    0x83,0x0B,0x3E,0x82,0xA8,0xF5,0x37,0x2A,0x46,0xC2,0xFF,0x03,0x12,0x42,0xCD,0xBE,
++    0x07,0x21,0x61,0xBA,0x18,0x42,0xCB,0x20,0x02,0x99,0x0B,0x00,0xC0,0x20,0x39,0xA1,
++    0xF8,0x3A,0x37,0xB1,0xF8,0x32,0x9D,0x0C,0x48,0x09,0x88,0x1E,0x07,0xF9,0x87,0x09,
++    0xD8,0x00,0x96,0x3D,0x50,0x09,0x88,0x1E,0x02,0xC9,0x08,0x00,0xD8,0x00,0x94,0x35,
++    0xC8,0x03,0x85,0x04,0x06,0x81,0xDF,0x00,0x0A,0xE1,0x19,0x42,0x08,0x81,0x87,0x1F,
++    0xFE,0x2F,0xCC,0x00,0x93,0x05,0x40,0x71,0xD3,0x06,0x00,0x71,0x0B,0xF9,0x8F,0x99,
++    0x10,0x42,0xEC,0x06,0x30,0x42,0xC8,0x04,0xC8,0x13,0x0F,0x48,0x00,0x90,0x1A,0x8A,
++    0xD0,0x0C,0x80,0x8B,0xF8,0x0C,0x88,0x08,0x81,0xCB,0x8B,0x88,0x81,0xCB,0x3D,0x88,
++    0x08,0x00,0x78,0x48,0x1F,0x42,0x80,0xC3,0xE3,0xF8,0xE7,0xF8,0x58,0x04,0x09,0xA1,
++    0x82,0x1F,0xF8,0xD7,0x86,0x51,0x90,0x05,0x40,0xF9,0x97,0x56,0x5A,0xAA,0xEE,0xCA,
++    0x30,0x52,0x90,0x51,0x10,0x12,0x94,0x16,0x82,0xC3,0xA9,0xC2,0x01,0x1F,0x80,0xCB,
++    0x07,0x0F,0x00,0xF9,0x80,0xC3,0xC1,0x44,0xC8,0x44,0xC0,0x03,0xE8,0x00,0x82,0x43,
++    0xEF,0xF5,0xAF,0x85,0x80,0x2D,0x34,0x01,0x00,0x5D,0x46,0x03,0x86,0x14,0x40,0x3A,
++    0xF8,0x1B,0x14,0x09,0x06,0x01,0x48,0x4A,0x60,0x4A,0xC6,0x6B,0x68,0x59,0x85,0x16,
++    0xE5,0x00,0x12,0x02,0x9F,0xCE,0x07,0xF9,0x80,0x43,0x58,0x01,0x80,0xBE,0x30,0x01,
++    0x48,0x15,0x00,0x01,0x25,0x99,0x5B,0xF2,0x08,0x20,0x03,0x77,0x2A,0x21,0x19,0x2A,
++    0xC1,0x68,0xCF,0x68,0xD0,0x6B,0x69,0x09,0x88,0x2E,0x80,0x43,0xE7,0xB0,0x93,0xB5,
++    0xE0,0x48,0x72,0x09,0x82,0x1E,0xE0,0x00,0x94,0x05,0x16,0x82,0x98,0x76,0x77,0x01,
++    0x85,0x16,0x63,0xB2,0x68,0x15,0x38,0x01,0x47,0x82,0x85,0x01,0x81,0x1C,0x00,0x0F,
++    0x78,0x01,0x88,0x9E,0x50,0x0D,0x90,0x04,0x11,0x01,0xC0,0x43,0x30,0x1A,0x31,0x8A,
++    0xBB,0xFF,0xFF,0x07,0xE0,0x68,0xC3,0x1C,0xC6,0x03,0x4C,0x00,0x09,0x00,0x1E,0x82,
++    0x8D,0x03,0x03,0x59,0x8D,0x03,0xED,0x20,0xE0,0x20,0x03,0x4F,0x50,0x0D,0x90,0x04,
++    0x11,0x01,0xC0,0x43,0x30,0x1A,0x31,0x8A,0xBA,0xFF,0xFF,0x67,0xE3,0x68,0xEB,0x20,
++    0xE7,0xF8,0x93,0xFD,0x16,0xBA,0x9D,0xDE,0xC4,0x1C,0x18,0x01,0xC6,0x03,0x4C,0x08,
++    0x48,0x01,0x80,0x9E,0x70,0x01,0x80,0x3E,0x80,0x03,0xC1,0x1C,0xCB,0x03,0x80,0x03,
++    0x05,0x59,0x85,0x03,0xE0,0x20,0x05,0x3F,0x80,0x03,0xC1,0x1C,0xCB,0x03,0x80,0x03,
++    0x8D,0x1B,0x03,0x59,0x8D,0x03,0xED,0x20,0xE0,0x20,0x03,0x27,0x70,0x09,0xC8,0x16,
++    0x01,0x59,0x85,0x03,0xE1,0x20,0x33,0x02,0xB8,0xFF,0xFF,0xC7,0x42,0x8A,0x44,0x0B,
++    0x10,0x01,0x1A,0x8A,0x04,0x0B,0x4A,0x82,0x40,0x43,0x1A,0xC2,0x04,0x43,0x62,0x7A,
++    0x42,0x03,0x41,0x00,0x01,0x00,0x02,0x03,0x04,0xF9,0x87,0x89,0x85,0x1F,0xE8,0xE7,
++    0x40,0x03,0x09,0x09,0x19,0x42,0x00,0x03,0x87,0x2D,0xE8,0x85,0xAC,0xFD,0x87,0x0D,
++    0xF8,0x54,0x30,0x32,0x33,0x62,0x68,0xEA,0xA8,0x01,0x57,0x09,0x88,0x4E,0x00,0x0F,
++    0x87,0x07,0xF8,0xE7,0xC2,0x43,0x31,0x00,0xA9,0xD6,0xC7,0x43,0x08,0xF9,0x05,0x42,
++    0x80,0x43,0x01,0x09,0x33,0x22,0x54,0xE2,0x01,0x8F,0x61,0x01,0xC3,0x2E,0xF0,0x00,
++    0x08,0x01,0x1F,0x42,0x09,0x83,0x32,0x0A,0x07,0x17,0x00,0xF9,0x09,0x83,0x0A,0x01,
++    0x1C,0x01,0x08,0x9B,0x00,0x01,0x00,0x4F,0x78,0x01,0x88,0x16,0x1E,0x01,0x00,0x9B,
++    0x01,0x17,0xC0,0x9B,0x07,0x9B,0xCE,0xB0,0xE4,0x00,0x92,0x05,0x17,0x42,0x9C,0x9E,
++    0x30,0x02,0x43,0x01,0x80,0x26,0x00,0xA1,0x00,0x83,0x04,0x01,0x30,0x22,0x04,0x0F,
++    0x04,0x21,0x00,0x83,0xD4,0x00,0x93,0x25,0x44,0x83,0x0A,0x01,0x1A,0x42,0x00,0x83,
++    0xC2,0x43,0x31,0x00,0xA9,0xE6,0xC7,0x43,0x08,0xF9,0x05,0x42,0x80,0x43,0x61,0x01,
++    0x88,0x5E,0xC6,0x24,0x45,0x09,0x88,0x7E,0x04,0x01,0x00,0x83,0x44,0x83,0x0A,0x01,
++    0x1A,0x42,0x00,0x83,0x3F,0x47,0xAD,0x9D,0x80,0x1D,0x24,0x01,0x00,0x01,0x80,0x0C,
++    0x72,0x15,0x40,0x92,0xF2,0x03,0xEC,0x00,0x92,0x3D,0x6E,0x82,0xA9,0x01,0x07,0xAF,
++    0x85,0x07,0xF8,0x27,0xC2,0x43,0x31,0x00,0xA2,0x1E,0x40,0x62,0xF5,0x03,0x14,0xC2,
++    0x9A,0xB6,0x47,0x52,0xF5,0x03,0x14,0xC2,0x98,0x06,0x20,0x11,0xC5,0x43,0x09,0xF9,
++    0x01,0x42,0x80,0x43,0x44,0x62,0x42,0x0B,0x10,0x79,0x06,0x8A,0x48,0x09,0x88,0x9E,
++    0x0C,0x01,0x08,0x0B,0x41,0x0B,0x86,0x8B,0xE3,0xB0,0xE3,0x20,0x90,0x25,0x67,0x11,
++    0x8B,0x56,0x30,0x5A,0xD0,0xCB,0xD0,0x1C,0x10,0x8A,0x8C,0x2E,0xD0,0xCB,0xD2,0x24,
++    0x10,0x8A,0x8C,0x0E,0x08,0x09,0x88,0x0C,0x0A,0x01,0x0F,0x0B,0x0C,0x01,0x08,0x0B,
++    0x0C,0x81,0x00,0x0B,0x44,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,0x66,0x11,0x88,0x4E,
++    0xC3,0x0C,0x38,0x0F,0x48,0x8A,0x61,0x54,0x80,0x13,0x10,0x01,0x86,0x13,0xE2,0x4B,
++    0x81,0x0B,0x4C,0xB2,0x8C,0x01,0x5A,0x53,0x82,0x13,0x5E,0x53,0x88,0x13,0x10,0xA9,
++    0x88,0x13,0x12,0x19,0x8E,0x13,0x4C,0x53,0x8C,0x13,0x4E,0x53,0x92,0x13,0x48,0x4B,
++    0x90,0x0B,0x0A,0x31,0x93,0x0B,0x3C,0x82,0xAC,0x85,0x87,0x4D,0x30,0x22,0x30,0x01,
++    0x00,0x01,0x80,0x2C,0x39,0x01,0x48,0x0A,0xDA,0x43,0xD8,0x4B,0x18,0x42,0x82,0x14,
++    0x40,0xFA,0x80,0x71,0x80,0x24,0xC0,0x71,0x80,0x1C,0x60,0x09,0x80,0x0E,0x60,0x29,
++    0x88,0x7E,0x60,0x09,0x89,0x26,0x70,0x12,0xE0,0x80,0x83,0x2C,0x78,0x0A,0x01,0x27,
++    0x73,0x0A,0xE1,0x80,0x80,0x2C,0x78,0xFA,0xF8,0xC1,0x41,0x35,0xB9,0xFF,0xF7,0x37,
++    0x00,0x3F,0x60,0x21,0x88,0x2E,0x70,0xEA,0x47,0x35,0xB8,0xFF,0xF8,0xDF,0x7D,0xCA,
++    0xB8,0x11,0x6B,0x72,0xA9,0x01,0xC7,0x43,0x08,0xF9,0x05,0x42,0x81,0x43,0xC1,0x43,
++    0x08,0x01,0x19,0x42,0x80,0x43,0x41,0x7A,0x42,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,
++    0x42,0x6A,0x40,0x0B,0x10,0x01,0x1C,0x8A,0x00,0x0B,0x4A,0x62,0x40,0x43,0x10,0x09,
++    0x18,0x82,0x00,0x43,0x0C,0x09,0x00,0x01,0x00,0xD7,0x00,0x00,0x00,0xE0,0x00,0x01,
++    0x08,0x40,0x00,0x01,0x80,0x00,0x06,0x01,0x00,0xF8,0x07,0x00,0x80,0x30,0x02,0x01,
++    0x30,0x04,0x05,0x08,0x00,0x00,0x06,0x42,0x80,0x01,0x06,0x42,0xF8,0x00,0x06,0x42,
++    0x18,0x60,0x05,0x01,0x70,0x70,0x06,0x01,0x50,0x20,0x07,0x01,0x68,0x60,0x02,0x01,
++    0xB9,0xFF,0xFF,0xCF,0x43,0x09,0x88,0x2E,0x61,0x21,0x88,0x7E,0x10,0x09,0x90,0x04,
++    0x30,0x82,0x19,0x01,0xCF,0x14,0xB8,0xFF,0xF0,0xCF,0x16,0x09,0x90,0x04,0x10,0x01,
++    0x08,0x59,0x40,0x35,0x37,0x9A,0xB8,0xFF,0xF0,0x8F,0x16,0x09,0x90,0x04,0x10,0x01,
++    0x09,0x29,0x30,0xC2,0x37,0x9A,0xB8,0xFF,0xF0,0x4F,0x16,0x09,0x90,0x04,0x10,0x01,
++    0x0E,0x71,0x40,0x0A,0x37,0x9A,0xB8,0xFF,0xF0,0x0F,0x16,0x09,0x90,0x04,0x10,0x01,
++    0x08,0x29,0x30,0x9A,0xC7,0x24,0xB8,0xFF,0xF0,0xCF,0x15,0x09,0x90,0x04,0x10,0x01,
++    0x08,0x29,0x18,0x09,0xC7,0x1C,0xB8,0xFF,0xF1,0x8F,0x05,0x9F,0x60,0x09,0x80,0x0E,
++    0x61,0x29,0x88,0x7E,0x10,0x11,0x90,0x04,0x11,0x09,0x30,0x82,0x18,0x01,0xC8,0x14,
++    0xBD,0xFF,0xF7,0x27,0x10,0x11,0x90,0x04,0x10,0x01,0x30,0x9A,0xC8,0x14,0xC0,0x2C,
++    0xBC,0xFF,0xF7,0xE7,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x21,0x40,0x35,0x30,0x9A,
++    0xBC,0xFF,0xF7,0xA7,0x10,0x09,0x90,0x04,0x11,0x01,0x08,0x31,0x30,0xC2,0x31,0x9A,
++    0xBC,0xFF,0xF7,0x67,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x29,0x30,0x9A,0xC0,0x24,
++    0xBC,0xFF,0xF7,0x27,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x29,0x18,0x09,0xC0,0x1C,
++    0xBB,0xFF,0xF7,0xE7,0xC6,0x43,0x09,0xF9,0x01,0x42,0x80,0x43,0x40,0xDA,0x44,0x0B,
++    0x42,0x48,0x02,0x48,0x04,0x0B,0x40,0xD2,0x0A,0x01,0x0F,0x0B,0x0C,0x01,0x00,0x0B,
++    0x44,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,0x87,0x4D,0xE8,0x85,0xAC,0x85,0x63,0xAA,
++    0xC8,0x03,0x43,0x09,0x83,0x16,0xC8,0x03,0x40,0x29,0x88,0x86,0x46,0x8A,0xC4,0x01,
++    0x82,0x1F,0xC8,0x4F,0x69,0x82,0xC4,0x43,0x40,0x11,0x98,0x2E,0xCF,0x03,0xBB,0xFF,
++    0xF8,0x5F,0x00,0x01,0x83,0x43,0xE9,0x85,0xE1,0x00,0x82,0x43,0xEB,0x85,0xCB,0x03,
++    0x40,0x21,0x88,0x26,0xB8,0xFF,0xFF,0x07,0x03,0x19,0x88,0x03,0xEB,0x85,0xCB,0x03,
++    0x47,0x19,0x80,0xDE,0xC8,0x03,0x43,0x31,0x84,0xC6,0x47,0x12,0xC4,0x01,0xFE,0x03,
++    0x40,0x01,0x88,0x3E,0x41,0xFA,0x83,0x01,0xD0,0x0B,0x48,0x31,0x9C,0x76,0xC7,0x03,
++    0x37,0x00,0xA8,0x5E,0x44,0xDA,0xC3,0x01,0xE8,0x03,0x44,0x01,0x8F,0x36,0xBF,0xFF,
++    0xEB,0xC7,0xEC,0x85,0xA8,0xC5,0x27,0x01,0x30,0x1A,0x00,0x09,0x4B,0xAA,0x6B,0xBA,
++    0x30,0x01,0x59,0x51,0x80,0xE6,0xE1,0x4E,0x79,0xAA,0xC3,0xD3,0x85,0x1F,0xE8,0x6F,
++    0x61,0x52,0x20,0x09,0x39,0x61,0x62,0x52,0x71,0x61,0x62,0x92,0x40,0x6A,0x13,0x31,
++    0xC2,0x01,0x56,0x03,0x80,0x01,0x5A,0xC9,0x80,0xAE,0xE1,0x4E,0x59,0x59,0x80,0x56,
++    0x59,0x61,0x80,0x66,0x59,0x69,0x88,0xBE,0x02,0x29,0x88,0x43,0x21,0x09,0x00,0x9F,
++    0x59,0xD1,0x80,0x6E,0x59,0x01,0x89,0x7E,0x88,0x53,0x22,0x09,0x08,0x59,0xA5,0x0B,
++    0x00,0x57,0x01,0x39,0x89,0x43,0x02,0x3F,0x86,0x07,0xE8,0x17,0x00,0x27,0x19,0x12,
++    0x81,0xD3,0x01,0x0F,0x00,0x41,0x18,0x12,0x80,0xD3,0x01,0xEF,0x02,0x11,0x88,0x43,
++    0x20,0x09,0x00,0xCF,0x02,0x01,0x88,0x43,0x41,0x43,0x19,0x82,0x00,0x43,0x01,0x9F,
++    0x88,0x43,0x22,0x09,0x00,0x87,0x00,0x19,0x88,0x43,0x22,0x09,0x00,0x67,0x00,0x21,
++    0x88,0x43,0x22,0x09,0x02,0x47,0x88,0x53,0x26,0x09,0x08,0x69,0xA0,0x0B,0x00,0x1F,
++    0x88,0x53,0x22,0x09,0x08,0x79,0xA7,0x0B,0x60,0x01,0x80,0x66,0x40,0x6A,0x42,0x0B,
++    0x30,0x48,0xA8,0x2E,0x08,0x81,0x06,0x0B,0x08,0x81,0x02,0x0B,0x08,0x81,0x00,0x0B,
++    0x45,0x43,0x19,0x82,0x07,0x43,0xE9,0xC5,0xAC,0x8D,0x87,0x15,0x40,0x32,0x82,0x0C,
++    0x46,0x02,0xC2,0x01,0xDA,0x2B,0xD8,0x33,0x0C,0x01,0xB0,0x0B,0x61,0x02,0xC2,0x0B,
++    0x10,0xF9,0x05,0x8A,0x81,0x0B,0xC1,0x0B,0x10,0x01,0x19,0x8A,0x81,0x0B,0x49,0xEA,
++    0x8A,0x01,0x46,0x53,0x18,0x01,0x1A,0xD2,0x01,0x53,0x52,0xAA,0x44,0x8B,0x1A,0x01,
++    0x1A,0xCA,0x00,0x8B,0x48,0x8A,0x41,0x53,0x18,0x09,0x18,0xD2,0x02,0x53,0x50,0x03,
++    0x80,0x01,0xE2,0x0B,0x49,0x79,0x87,0xAE,0xE6,0x03,0x40,0x69,0x88,0x16,0x09,0xA9,
++    0x07,0x91,0xB8,0xFF,0xE8,0x47,0x47,0x09,0x89,0xDE,0x31,0x42,0x1A,0x82,0x03,0x38,
++    0x15,0x09,0x90,0xCD,0x90,0x04,0x18,0x01,0xC7,0x0C,0xB8,0xFF,0xE9,0x3F,0x44,0x5A,
++    0x10,0x09,0x90,0x04,0x15,0x01,0x90,0xCD,0x37,0x9A,0xB8,0xFF,0xE8,0xFF,0xC3,0x14,
++    0x15,0x09,0xC8,0x48,0xE8,0x48,0x90,0x04,0x00,0x48,0x12,0x01,0x1F,0x09,0xB8,0xFF,
++    0xE8,0xAF,0x03,0xF7,0x08,0xA1,0x00,0x91,0xBE,0xFF,0xEF,0x2F,0x40,0x09,0x88,0xC6,
++    0x18,0xAA,0x13,0x09,0x20,0x40,0x63,0x08,0x90,0x04,0x30,0x9A,0xC7,0x0C,0xB8,0xFF,
++    0xE8,0x2F,0x03,0x77,0x08,0xB1,0x00,0x91,0xBD,0xFF,0xEF,0xAF,0x40,0x09,0x88,0x46,
++    0xC0,0x14,0x10,0x09,0xC8,0x48,0xED,0x48,0x00,0x48,0x32,0x9A,0x97,0x04,0xB8,0xFF,
++    0xE9,0xAF,0xC2,0x03,0x08,0xF9,0x06,0x42,0x80,0x03,0x41,0x42,0x42,0x0B,0x40,0x48,
++    0x00,0x48,0x02,0x0B,0x47,0x32,0x08,0x01,0x08,0x0B,0x0A,0x01,0x02,0x0B,0x44,0x0B,
++    0x10,0x01,0x1C,0x8A,0x07,0x0B,0xEA,0xF5,0x70,0x00,0x04,0x01,0xF8,0x00,0x06,0x42,
++    0x80,0x01,0x06,0x42,0x00,0xE0,0x06,0x01,0x00,0x00,0x00,0x01,0x10,0x00,0x00,0x42,
++    0x00,0xE0,0x07,0x01,0x00,0x00,0x00,0x42,0x50,0x20,0x07,0x01,0x08,0x20,0x02,0x01,
++    0x52,0xE2,0x43,0x83,0x03,0x83,0x42,0xE2,0xF7,0x0B,0x4C,0xF9,0x94,0x16,0xF0,0x0B,
++    0xE4,0x48,0xB2,0x0B,0xF0,0x03,0x44,0xC1,0x90,0x0E,0x00,0x01,0x03,0x83,0x3C,0x82,
++    0x4C,0xB2,0x4B,0x53,0x5C,0xA2,0xE3,0xC3,0x1C,0x12,0x0C,0x53,0x10,0x43,0x02,0x09,
++    0xB3,0xC3,0x3C,0x82,0xAB,0x85,0x40,0x8A,0x84,0x01,0x42,0x0B,0x10,0x01,0x1C,0x8A,
++    0x03,0x0B,0x54,0x7A,0x4B,0x62,0x43,0x7A,0x86,0x1F,0xC0,0x97,0xEF,0x85,0xA8,0xC5,
++    0x47,0x4A,0x83,0x01,0xC3,0x0B,0x70,0x62,0x30,0x48,0xAC,0x46,0xC2,0x0B,0x10,0x01,
++    0x18,0x8A,0x80,0x0B,0x44,0x83,0x0B,0x01,0x1B,0x42,0x04,0x83,0xE8,0xC5,0x0F,0x01,
++    0x0D,0x8B,0x45,0x9B,0x66,0x02,0x03,0x79,0x01,0x1A,0x30,0x2A,0xAB,0x01,0x69,0x04,
++    0x50,0x13,0x5B,0x09,0x80,0xE6,0x58,0x29,0x80,0x46,0x58,0x41,0x8B,0xB6,0x93,0x4B,
++    0x46,0x9B,0x3F,0xD8,0x88,0x16,0x00,0x81,0x07,0x83,0xED,0xC5,0x0A,0x8B,0x4D,0xDA,
++    0x10,0x42,0x8C,0x16,0x07,0x29,0x05,0x83,0x00,0x3F,0xE0,0x92,0x02,0x93,0xE7,0x00,
++    0x93,0x05,0x2C,0x04,0x40,0x89,0x9A,0x06,0x28,0x0C,0x03,0xA1,0x07,0x83,0xED,0xC5,
++    0x5B,0x9A,0xD2,0x7B,0x40,0xDC,0x78,0x11,0x90,0x56,0x7B,0x01,0x8F,0x36,0x40,0x83,
++    0x50,0x7A,0x02,0x84,0x43,0x7A,0x12,0x03,0x2C,0x0C,0x03,0x1F,0x40,0x83,0x17,0xD0,
++    0x48,0x5A,0xC2,0x80,0x90,0x3D,0x04,0x7C,0x00,0x89,0x16,0x00,0xD1,0xC0,0x41,0x01,
++    0xC7,0x96,0x90,0xC5,0xBC,0xFF,0xF7,0x37,0x44,0x3A,0x12,0x3A,0x82,0x96,0x43,0x32,
++    0x84,0x41,0x10,0x3A,0x88,0x76,0x03,0x09,0x86,0x07,0xC8,0x37,0x05,0xC1,0xB0,0x03,
++    0x40,0x12,0x0A,0x09,0x83,0x0B,0x00,0x2F,0x46,0xBA,0x81,0x01,0xC8,0x03,0x42,0x01,
++    0x89,0x26,0x41,0xEA,0xC4,0x31,0x16,0x3A,0x89,0xAE,0x40,0xEA,0x41,0x0B,0x40,0xCA,
++    0x72,0x50,0x80,0x01,0x80,0x13,0x60,0x50,0x80,0x13,0x52,0x50,0x86,0x13,0x84,0x0B,
++    0xC2,0x0B,0xC0,0x13,0xC4,0x48,0xC4,0x13,0xC6,0x1B,0xC6,0x90,0xC5,0x48,0x8C,0x29,
++    0x50,0x50,0x88,0x13,0x88,0x0B,0x02,0x69,0x19,0x00,0xD0,0xC0,0x40,0x81,0xC2,0x0E,
++    0x29,0x04,0x03,0xFF,0x06,0x01,0x18,0x02,0x29,0x04,0x03,0xDF,0x41,0x6A,0xC1,0xC0,
++    0x40,0x19,0xC1,0x26,0x29,0x04,0x43,0x62,0x11,0x03,0x03,0x9F,0x01,0xC7,0x41,0x4A,
++    0xC1,0x81,0xC1,0xC0,0x40,0x01,0xC1,0x26,0x29,0x04,0x43,0x3A,0xC3,0x01,0x11,0x03,
++    0x00,0x47,0x01,0x69,0x19,0x00,0xD0,0xC0,0x41,0xB1,0xC1,0x1E,0x29,0x04,0x03,0x0F,
++    0x7D,0xD2,0x10,0xC2,0x87,0xF6,0x40,0xBB,0xA0,0xBA,0x40,0xDA,0xC4,0xD1,0x15,0x1A,
++    0x8B,0x7E,0x68,0x04,0x40,0x61,0x8A,0x66,0x50,0x1B,0xE3,0xFA,0x52,0x72,0x90,0x01,
++    0x78,0x01,0x8C,0x16,0x04,0x09,0xA8,0x83,0x00,0x1F,0xE0,0xC2,0x40,0x01,0x88,0x06,
++    0xAB,0x8B,0x6C,0x04,0xE4,0x00,0x92,0x05,0x2A,0x04,0x43,0x89,0x98,0x16,0x00,0x01,
++    0x1B,0x02,0x2E,0x04,0xD2,0x43,0xE3,0x00,0x90,0x43,0x03,0x81,0x07,0x83,0xED,0xC5,
++    0x07,0x8B,0xED,0xC5,0x10,0x00,0x00,0x42,0x00,0xE0,0x00,0x01,0xF8,0x00,0x06,0x42,
++    0x80,0xC0,0x04,0x01,0x08,0x40,0x00,0x01,0x80,0x01,0x06,0x42,0xF8,0xFF,0x07,0x00,
++    0x00,0x10,0x00,0x01,0x80,0x30,0x02,0x01,0x88,0x36,0x00,0x00,0x00,0x20,0x00,0x01,
++    0x00,0xA0,0x00,0x01,0x77,0x81,0xF8,0xFF,0xF8,0x02,0x07,0x00,0xA8,0x85,0x80,0x07,
++    0xC8,0xBF,0x65,0x32,0xC8,0x03,0x43,0x01,0x80,0x26,0x40,0x31,0x8F,0xD6,0xBF,0xFF,
++    0xD7,0xCF,0x3B,0xBF,0xBD,0xFF,0xCF,0xD7,0x38,0xA7,0x07,0x00,0x00,0xE0,0x06,0x01,
++    0xAF,0xC5,0x77,0x62,0x03,0x01,0x87,0x83,0x01,0x09,0x80,0x83,0x0F,0x01,0x81,0x8B,
++    0x05,0x19,0x80,0x83,0x03,0x41,0x89,0x83,0x07,0x69,0x89,0x83,0x05,0x69,0x88,0x83,
++    0x11,0x02,0x32,0xAA,0xA9,0x01,0x06,0x44,0x04,0xF9,0x87,0x89,0x20,0x84,0x01,0x09,
++    0x34,0x62,0xE1,0x01,0x93,0x03,0x91,0x03,0x05,0x41,0x90,0x03,0x17,0x51,0x90,0x13,
++    0x11,0xA1,0x98,0x13,0x98,0x0B,0x0D,0x81,0x99,0x0B,0xA7,0x03,0x3B,0x01,0xA0,0xBB,
++    0x09,0x71,0x98,0x8B,0x0B,0x29,0x98,0x8B,0x17,0x71,0x98,0x93,0x99,0x8B,0xA5,0xBB,
++    0xA1,0x83,0x05,0x81,0xA0,0x83,0x07,0x51,0x8F,0x03,0x01,0xB1,0x8D,0x03,0x8B,0x3B,
++    0x8B,0x3B,0x9F,0x0B,0x05,0x99,0x28,0x84,0x07,0xF9,0x87,0x09,0x10,0x44,0x01,0xC9,
++    0x0B,0x00,0x12,0x44,0x02,0x19,0x18,0x00,0x0E,0x43,0x43,0x5A,0x0A,0x43,0x05,0x01,
++    0xB9,0x43,0x31,0x02,0x0D,0x51,0x80,0x11,0x83,0x1F,0xD0,0x17,0x01,0xB1,0x97,0x43,
++    0x1B,0xF1,0x90,0x5B,0x89,0x7B,0x33,0x02,0x82,0x01,0xB2,0x3B,0xB8,0x3B,0x08,0xC1,
++    0xB8,0x0B,0x0A,0x51,0xBE,0x0B,0x14,0x41,0x31,0x0A,0x88,0x01,0x0F,0x54,0x12,0xF9,
++    0x94,0x99,0x0A,0x54,0x16,0xC1,0xBE,0x13,0x10,0x41,0x81,0x53,0x12,0x11,0x87,0x53,
++    0x80,0x5B,0x14,0x51,0x91,0x13,0x12,0x41,0x93,0x13,0x14,0x21,0x92,0x13,0x16,0xA9,
++    0x08,0x14,0x16,0x71,0x9A,0x13,0x10,0x69,0xA0,0x13,0x10,0x21,0xA6,0x13,0x12,0x41,
++    0x10,0x14,0x12,0x31,0xBF,0x93,0x37,0xBC,0xB0,0x3B,0x1C,0x21,0x33,0x12,0x90,0x01,
++    0x90,0x9B,0x1C,0x31,0x96,0x9B,0x12,0x99,0x08,0x94,0x11,0xA1,0x80,0x53,0x16,0x51,
++    0x8E,0x53,0xB0,0x3B,0x12,0x21,0x8C,0x53,0x53,0x42,0x05,0x54,0x14,0x09,0x88,0x53,
++    0x10,0x51,0x90,0x53,0x17,0x11,0xA0,0x13,0x08,0x21,0xA8,0x0B,0x0A,0xC1,0xAB,0x0B,
++    0xA8,0x0B,0x1C,0x01,0x33,0x0A,0xC8,0x01,0xA0,0x5B,0xAE,0x5B,0x22,0xF1,0x88,0x01,
++    0xBA,0x63,0xB8,0x63,0x24,0xE1,0xB9,0x63,0x26,0x41,0xB8,0x63,0x80,0x13,0x08,0xB1,
++    0x80,0x0B,0x0A,0x19,0x84,0x0B,0x4C,0xD2,0x00,0x0B,0x92,0x1B,0x4C,0xCA,0xC4,0x01,
++    0x38,0x0B,0x88,0x91,0x3E,0x0B,0x8A,0xE1,0x38,0x0B,0x0C,0xE1,0x40,0xB2,0x84,0x1F,
++    0xCC,0xBF,0x47,0xAA,0x09,0xE1,0xC0,0xC1,0x87,0x1F,0xC8,0x97,0x4C,0x8A,0x44,0x9A,
++    0xCE,0x11,0x03,0x0B,0xCC,0x71,0x00,0x0B,0x88,0xA1,0x08,0x0B,0x8A,0xA1,0x08,0x0B,
++    0xCA,0xE1,0x01,0x0B,0xC8,0xC1,0x01,0x0B,0x8C,0x61,0x0D,0x0B,0xCA,0x81,0x15,0x0B,
++    0xF8,0x48,0x10,0x0B,0xFE,0x48,0x08,0x0B,0xE9,0xC5,0xAF,0x85,0x0C,0x01,0x60,0x0A,
++    0x47,0x02,0xA4,0x61,0xF8,0x1B,0x06,0x77,0x02,0x21,0x19,0x42,0xCB,0x28,0x00,0x99,
++    0x12,0x79,0x08,0x00,0xC4,0x40,0x89,0x13,0x16,0x01,0x88,0x13,0x94,0x13,0x10,0x14,
++    0x12,0x14,0xE6,0x48,0x94,0x4D,0x16,0x5A,0xC0,0x76,0x07,0x01,0x13,0xF9,0x2F,0x89,
++    0x08,0x68,0x03,0x37,0x00,0x08,0xCA,0x48,0xCC,0x48,0xAA,0x53,0xAA,0x53,0xE6,0x00,
++    0x94,0x05,0x16,0x1A,0xC1,0xB6,0xEF,0x85,0xA3,0x85,0x51,0x72,0x90,0x01,0x0E,0x01,
++    0x26,0x8C,0xD0,0x01,0xBC,0x8B,0xB8,0x8B,0x36,0x9A,0x98,0x01,0x8A,0xCB,0x0C,0xCC,
++    0x9E,0xCB,0x88,0xCB,0x2C,0x09,0xB0,0xAB,0xA8,0x8B,0x34,0xA2,0xA1,0x01,0xCD,0x1B,
++    0xB0,0x9B,0x36,0x9A,0x9A,0x01,0xA9,0xCB,0x9A,0x01,0xA9,0xEB,0xA8,0xCB,0xA8,0xAB,
++    0x28,0x41,0x89,0xAB,0x8B,0x0B,0x57,0x32,0x88,0x8B,0x46,0x09,0x8C,0x16,0xA8,0xCB,
++    0xE5,0x85,0x39,0x97,0xE3,0x85,0x39,0x82,0x0B,0x08,0x42,0x12,0x41,0x13,0x18,0x01,
++    0x04,0xD2,0x90,0x41,0x04,0x13,0x10,0xD0,0x1A,0x8A,0x08,0x0B,0x40,0x0B,0x42,0x0B,
++    0x14,0x41,0x18,0x8A,0x00,0x0B,0x08,0x01,0x03,0x0B,0x3C,0x82,0xAA,0x85,0x40,0xD2,
++    0x40,0x0B,0x30,0x48,0xAE,0x2E,0x08,0x81,0x02,0x0B,0x08,0x81,0x00,0x0B,0x08,0x81,
++    0x02,0x0B,0x48,0xAA,0x8C,0x01,0x46,0x53,0x38,0x90,0x78,0x90,0x04,0x53,0x44,0x53,
++    0x18,0x81,0x19,0xD2,0x02,0x53,0x5C,0x8A,0x12,0x09,0x06,0xD3,0x16,0x91,0x01,0x13,
++    0x44,0x7A,0x42,0x23,0x10,0x61,0x18,0xA2,0x02,0x23,0x44,0x23,0x1A,0xA2,0x00,0x23,
++    0x48,0x23,0x1A,0xA2,0x08,0x23,0x4A,0x23,0x18,0xA2,0x08,0x23,0x40,0x23,0x1E,0xA2,
++    0x02,0x23,0x46,0x43,0x10,0x01,0x1A,0x82,0x04,0x43,0x02,0xD1,0x07,0xC3,0x00,0x01,
++    0x08,0xC3,0xEA,0x85,0x40,0x12,0x42,0x13,0x08,0x09,0x18,0x52,0x00,0x13,0x48,0x13,
++    0x18,0x52,0x0C,0x13,0x4C,0x13,0x1A,0x52,0x0E,0x13,0x42,0x13,0x1E,0x52,0x00,0x13,
++    0x39,0x82,0x43,0xE2,0x58,0x0B,0x10,0x21,0x18,0x8A,0x18,0x0B,0x5A,0x0B,0x10,0x01,
++    0x18,0x8A,0x18,0x0B,0x5C,0x13,0x08,0x01,0x18,0x52,0x18,0x13,0x40,0x92,0x11,0x01,
++    0x80,0x01,0x06,0x13,0x40,0x13,0x1A,0x52,0x01,0x13,0x4A,0x72,0x41,0x43,0x10,0x01,
++    0x18,0x82,0x00,0x43,0x38,0x82,0xAB,0x85,0x08,0x09,0x00,0x31,0x81,0x07,0xD0,0xF7,
++    0x08,0x11,0x00,0x21,0x81,0x07,0xD0,0xD7,0x00,0x09,0x80,0x07,0xD0,0xB7,0x02,0x31,
++    0x82,0x07,0xD0,0x9F,0x00,0x21,0x80,0x07,0xD0,0x87,0x82,0x07,0xD0,0x2F,0xEB,0x85,
++    0xA8,0x85,0x43,0xF2,0x4A,0xBA,0xC0,0x91,0x11,0x43,0x0A,0x91,0x80,0x1F,0xC8,0x07,
++    0x40,0xD2,0x08,0x51,0x80,0x41,0x81,0x1F,0xC7,0xEF,0xBF,0xFF,0xF0,0x4F,0x02,0x09,
++    0xBA,0xFF,0xFF,0x17,0x07,0xA1,0xB8,0xFF,0xFF,0x3F,0xBB,0xFF,0xFF,0xBF,0xBB,0xFF,
++    0xFF,0xC7,0xBD,0xFF,0xFF,0x3F,0xBD,0xFF,0xF8,0x77,0x66,0x8A,0x29,0x01,0x80,0x2B,
++    0x08,0x2B,0x41,0x72,0x09,0x71,0x80,0x91,0x87,0x1F,0xC0,0x17,0x0B,0x2C,0x81,0x2B,
++    0x87,0x2B,0x85,0x2B,0x8B,0x2B,0x89,0x2B,0x05,0x51,0x88,0x03,0x0F,0x2C,0x8B,0x2B,
++    0x0B,0x2C,0xED,0x85,0x00,0xE0,0x00,0x01,0xC8,0x21,0x01,0x00,0x70,0x02,0x01,0x00,
++    0xF8,0xFF,0x07,0x04,0x68,0x62,0x03,0x00,0x70,0x70,0x06,0x01,0x80,0xC0,0x04,0x01,
++    0x00,0x20,0x00,0x01,0x10,0x00,0x00,0x42,0x00,0x00,0x00,0x42,0x80,0x01,0x06,0x42,
++    0xF8,0x00,0x06,0x42,0x18,0x00,0x02,0x42,0xA8,0x85,0x80,0x07,0xC8,0xCF,0xEE,0x85,
++    0xAF,0x85,0xB8,0xFF,0xE8,0x9F,0xEF,0x85,0xA8,0x7D,0x80,0x04,0x88,0x0C,0xC0,0x0C,
++    0x80,0x14,0xC0,0x04,0x83,0x1C,0x30,0x42,0x40,0x7E,0x80,0x25,0xE8,0x05,0x00,0x00,
++    0xAC,0xFD,0x87,0x1D,0x30,0x32,0x00,0x01,0x82,0x14,0x00,0x9F,0x44,0xDA,0x0E,0x01,
++    0x0C,0x0B,0x26,0x01,0xC2,0x14,0x00,0x28,0x7F,0xC2,0x4E,0xC3,0x1F,0x02,0x09,0xC3,
++    0xD0,0x6C,0x90,0x04,0x14,0x09,0x08,0x01,0x30,0x82,0xD9,0x64,0x86,0x17,0xE0,0x1F,
++    0xF8,0x82,0x33,0x0A,0xCF,0x99,0x49,0xC9,0x99,0x3E,0x40,0x91,0xE7,0x16,0x48,0xC3,
++    0x1F,0x02,0x0D,0xC3,0x40,0x20,0x63,0x01,0x88,0x36,0xD7,0x6C,0x90,0x04,0x10,0x09,
++    0x09,0x01,0x34,0x82,0xD8,0x64,0x80,0x17,0xE3,0x77,0xFD,0xA2,0xD0,0x6C,0x90,0x04,
++    0x14,0x09,0x08,0x01,0x30,0x82,0xD9,0x64,0x85,0x17,0xE0,0x2F,0xF8,0xBA,0xD3,0x6C,
++    0x90,0x04,0x10,0x09,0x09,0x01,0x34,0x82,0xD8,0x64,0x80,0x17,0xE5,0xE7,0x14,0x3A,
++    0xE9,0x16,0x30,0x02,0x30,0xE2,0x31,0x3A,0xFD,0x82,0x13,0xC2,0xE3,0x0E,0x98,0xBA,
++    0x05,0x17,0x10,0x02,0xDB,0x06,0x98,0xA2,0x46,0xC2,0x4D,0x03,0xDE,0x8A,0x0B,0x00,
++    0xC0,0x00,0xCA,0x24,0x00,0x44,0xC0,0x24,0xE0,0x00,0x84,0x24,0xC2,0x14,0xE0,0x00,
++    0x90,0x05,0x86,0x14,0xC8,0x2C,0xC0,0x14,0x15,0x42,0x9C,0x3E,0x87,0x3D,0xE8,0x85,
++    0xAC,0xFD,0x87,0x7D,0x30,0xA2,0x30,0xFA,0xD8,0x0B,0x8F,0x6C,0xD8,0x0B,0x8B,0x64,
++    0x40,0x01,0x80,0x6E,0x48,0x52,0x05,0x99,0x07,0x43,0x12,0xF9,0x58,0x3A,0x95,0x81,
++    0x10,0xD3,0x06,0x43,0x00,0xC1,0x83,0x17,0xF8,0xFF,0xF1,0x84,0xB0,0xE1,0x01,0xCF,
++    0x40,0x1A,0x0D,0x19,0x04,0x0B,0x0A,0x19,0x05,0x0B,0x48,0x12,0xC2,0x84,0xC0,0x30,
++    0x11,0x01,0x30,0xDA,0x30,0x8A,0x00,0x09,0x82,0x17,0xC0,0xC7,0x29,0x01,0x30,0x1A,
++    0x14,0x09,0x08,0x01,0x40,0x1D,0xB8,0x04,0x82,0x17,0xE0,0x6F,0xE7,0x68,0x93,0x6D,
++    0x6F,0x91,0x99,0xA6,0x48,0xB2,0x44,0x43,0x10,0x11,0x18,0x82,0x01,0x43,0x30,0x02,
++    0x80,0x01,0x35,0x2A,0xC8,0x03,0x32,0x00,0xAC,0xEE,0x49,0x9A,0x00,0x01,0x80,0x43,
++    0x31,0x12,0x31,0xCA,0x00,0x11,0x80,0x0F,0xF9,0xF7,0x34,0x1A,0xB8,0x04,0x08,0x01,
++    0x00,0x11,0xD0,0x84,0x84,0x17,0xC0,0x47,0x49,0x42,0xD4,0x43,0x08,0x43,0x2A,0x01,
++    0xC2,0x64,0x00,0x00,0x80,0x74,0x00,0xBF,0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,
++    0x81,0x17,0xC0,0x27,0xB8,0x0C,0xA0,0x04,0x30,0x8A,0x41,0x1D,0xD8,0x84,0xD0,0x64,
++    0xB9,0xFF,0xFF,0xF7,0xC4,0x74,0xC8,0x30,0x09,0x09,0x30,0xDA,0x30,0x52,0x31,0x42,
++    0x80,0x17,0xC0,0xA7,0xE7,0x68,0x93,0x6D,0xC4,0x6C,0x10,0x2A,0x99,0x26,0x37,0x1A,
++    0xB8,0x04,0x08,0x01,0x00,0x19,0xD0,0x84,0x82,0x17,0xC0,0xF7,0x31,0x12,0x31,0xCA,
++    0x00,0x01,0x80,0x0F,0xFB,0x47,0x4B,0x92,0x40,0x43,0x10,0x11,0x18,0x82,0x04,0x43,
++    0x87,0x9D,0xE8,0x85,0xAC,0xFD,0x87,0x1D,0x30,0x7A,0x50,0x01,0x80,0x16,0x00,0x01,
++    0x80,0x0C,0x00,0x0F,0x00,0x09,0x80,0x0C,0x2A,0x01,0x00,0x47,0xCD,0x64,0x00,0x40,
++    0xC1,0x30,0x32,0x52,0x08,0x19,0xD8,0x6C,0xC0,0x0C,0x80,0x0F,0xF9,0x3F,0x07,0x41,
++    0x85,0x17,0xF0,0xD7,0x20,0x09,0xC0,0x34,0x80,0x01,0x84,0x14,0x60,0x81,0x99,0x36,
++    0x0A,0xF9,0x47,0xF2,0x88,0x11,0x18,0x0B,0x42,0x08,0x1B,0x0B,0x02,0x0F,0x40,0xDA,
++    0x1F,0x23,0x02,0xF9,0x4F,0xCA,0x82,0x89,0x88,0x01,0x12,0x43,0x00,0x11,0x80,0x17,
++    0xF0,0x1F,0xC5,0x14,0xF0,0x03,0x46,0x01,0x80,0x3E,0x00,0x51,0x84,0x17,0xF0,0xE7,
++    0x40,0x83,0x41,0x03,0x30,0x00,0xA8,0x86,0x07,0x5F,0x00,0xF9,0x4C,0x7A,0x82,0x89,
++    0x88,0x01,0x12,0x43,0x00,0x09,0x80,0x17,0xF1,0x7F,0x44,0x83,0x40,0x03,0x30,0x00,
++    0xA3,0x1E,0xE0,0x20,0x93,0x25,0x67,0xF9,0xC9,0x86,0x06,0xE4,0xE1,0xF8,0x35,0x52,
++    0x08,0x09,0xD8,0x6C,0xC0,0x0C,0x80,0x0F,0xFB,0x4F,0xE5,0x68,0x90,0x6D,0xC7,0x1C,
++    0x15,0x2A,0x9C,0x9E,0x3F,0x17,0xA9,0x85,0x80,0x3D,0x34,0x7A,0x34,0xA2,0x00,0xD9,
++    0xEF,0x02,0x0E,0xF9,0x88,0x09,0x40,0x01,0x80,0x0E,0x30,0x72,0x00,0x0F,0x30,0x19,
++    0x13,0xB0,0xD9,0xC3,0x81,0x34,0xD8,0xC3,0x80,0x2C,0x98,0x1C,0xC2,0x34,0x00,0x00,
++    0xC0,0x00,0x86,0x24,0x45,0xAA,0x11,0x81,0x00,0x13,0x1A,0x0B,0x28,0x01,0x00,0x67,
++    0x4D,0x03,0x01,0x48,0xC0,0x00,0x42,0x03,0x01,0x33,0x30,0x1A,0x30,0x52,0x09,0x09,
++    0x00,0x01,0x80,0x0F,0xFB,0xDF,0xE3,0x68,0x90,0x6D,0xC7,0x34,0x17,0x2A,0x9C,0x7E,
++    0x28,0x01,0x00,0x67,0x4D,0x03,0x03,0x48,0xC0,0x00,0x42,0x03,0x00,0x33,0x08,0x09,
++    0x31,0x1A,0x31,0x52,0x30,0x42,0x80,0x0F,0xFB,0x4F,0xE3,0x68,0x90,0x6D,0xC7,0x2C,
++    0x17,0x2A,0x9C,0x7E,0x48,0x0B,0xA1,0x0C,0x89,0x04,0x30,0xDA,0x10,0x09,0xC8,0x1C,
++    0xC7,0x34,0xB8,0xFF,0xFB,0xFF,0x4A,0x0B,0x89,0x04,0x30,0xDA,0x10,0x01,0xA0,0x0C,
++    0xC8,0x24,0xC0,0x2C,0xBA,0xFF,0xFF,0xB7,0x48,0xC2,0x00,0x01,0x88,0x01,0x12,0x43,
++    0x48,0xB2,0x18,0x43,0x37,0x57,0xAE,0xC5,0x30,0x1A,0x30,0x42,0x30,0xBA,0xD8,0x23,
++    0xD8,0x2B,0x4A,0xB2,0xC0,0xC8,0x8A,0x04,0x30,0xD2,0x31,0xCA,0x87,0x0F,0xF8,0xDF,
++    0x30,0x01,0x00,0x3F,0x09,0x09,0x30,0xDA,0x30,0x92,0x31,0x42,0x81,0x0F,0xF8,0xB7,
++    0xE7,0xB0,0x93,0xB5,0x17,0x32,0x9D,0xAE,0xC8,0x04,0x10,0x01,0x18,0x01,0x00,0x4F,
++    0x00,0x01,0x00,0x1F,0x82,0x5B,0xE0,0x48,0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0xCE,
++    0xE6,0x90,0x92,0x95,0x17,0x12,0x9D,0x9E,0xE8,0xC5,0x07,0x00,0x00,0x01,0x00,0x42,
++    0x18,0x00,0x04,0x42,0x48,0xE0,0x06,0x00,0x00,0xD0,0x00,0x01,0x60,0x20,0x02,0x00,
++    0x49,0x32,0x41,0x2A,0x05,0x43,0x9E,0xFF,0x7F,0x04,0x3A,0xF7,0x94,0x15,0x3A,0x00,
++    0x77,0x18,0x06,0xF9,0x04,0xC2,0x3C,0x48,0x74,0x48,0x00,0xCA,0x50,0x01,0xD0,0x5E,
++    0x38,0x90,0x78,0x90,0xD4,0x41,0x40,0x98,0x54,0xE2,0x00,0xD8,0xC6,0xD0,0x4C,0x9B,
++    0x18,0x1A,0x1C,0x5A,0x0B,0x9B,0x3E,0x82,0x40,0x98,0x54,0xCA,0x04,0xD8,0xC4,0xD0,
++    0x44,0x9B,0x18,0x1A,0x18,0x5A,0x00,0x9B,0x3A,0x82,0x93,0x05,0x36,0x10,0x76,0x90,
++    0x0C,0x09,0x00,0x8A,0x48,0x00,0x52,0x9A,0x04,0x00,0xC4,0x00,0x03,0x0B,0x38,0x82,
++    0x96,0x05,0x32,0x10,0x70,0x90,0x0E,0x09,0x00,0x8A,0x54,0x72,0x4C,0x00,0x02,0x00,
++    0x94,0x01,0xC4,0x00,0x03,0x0B,0x38,0x82,0xB3,0x15,0x3B,0x82,0xFB,0x85,0x39,0x82,
++    0x40,0x32,0x48,0x0B,0x10,0x21,0x18,0x8A,0x0B,0x0B,0x38,0x82,0x48,0x1A,0x48,0x43,
++    0x14,0x21,0x18,0x82,0x0B,0x43,0x38,0x82,0x07,0x20,0x28,0xD0,0x68,0x07,0x00,0x07,
++    0x20,0x07,0x00,0x07,0x08,0x07,0x00,0x07,0xAC,0xFD,0x87,0x4D,0xD0,0x94,0x30,0x22,
++    0xF8,0x43,0x80,0x0C,0xF8,0x6B,0xC6,0x64,0x08,0x01,0x80,0x0B,0x00,0x01,0x00,0x8F,
++    0x0A,0x21,0x19,0x0A,0x18,0x99,0xCB,0x48,0x0E,0xD8,0xC2,0x48,0xC8,0x4B,0x4C,0x79,
++    0x80,0x36,0x80,0x83,0xE0,0x90,0xCA,0x64,0xD8,0x64,0xC0,0x4B,0xE0,0x48,0x82,0xCB,
++    0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0x5E,0xC0,0x64,0xC0,0x03,0x80,0x44,0x40,0x01,
++    0x88,0x0E,0x80,0x6D,0xE8,0x85,0xC7,0x44,0x40,0x09,0x88,0x1E,0xC0,0x0C,0x40,0x09,
++    0x8F,0x06,0x38,0xB7,0x00,0x01,0x80,0x34,0x80,0x2C,0xC8,0x44,0xC4,0x0C,0x10,0x0A,
++    0x88,0x96,0x02,0x01,0x30,0x01,0x08,0x01,0x88,0x1C,0x88,0x14,0x1C,0xC9,0x09,0xD8,
++    0x00,0x4F,0x10,0x31,0x18,0x52,0xCA,0x90,0xC2,0x90,0x46,0xBC,0xC4,0xC0,0x41,0x94,
++    0xCA,0xB0,0xE4,0x48,0x90,0x4D,0xD6,0x0C,0x17,0x8A,0x9C,0x96,0xC8,0x0C,0x80,0x17,
++    0xF0,0x6F,0x82,0x24,0x30,0x82,0xC9,0x0C,0x82,0x17,0xF0,0x47,0x30,0x32,0x08,0x01,
++    0x01,0x01,0x00,0x07,0x1A,0x99,0x0B,0xD8,0x02,0x0F,0xE0,0x48,0x91,0x4D,0x16,0x21,
++    0x18,0x52,0xCA,0x90,0xC4,0x90,0xCE,0x93,0x57,0x79,0x80,0xB6,0x12,0x21,0x19,0x52,
++    0xCE,0x90,0xC0,0x98,0x3E,0xF1,0xF8,0xFA,0xDF,0x1C,0xC0,0xD8,0x98,0x1C,0x18,0xE9,
++    0x0E,0xD8,0xC6,0x98,0x14,0x01,0xF0,0xD2,0xDE,0x14,0xC0,0x90,0x92,0x14,0xE0,0x48,
++    0x92,0x4D,0xE6,0x00,0x90,0x05,0xD6,0x44,0x16,0x12,0xC4,0xDE,0xC8,0x44,0xC0,0x1C,
++    0x80,0x17,0xF0,0xE7,0x30,0x3A,0xC8,0x44,0xC0,0x14,0x80,0x17,0xF0,0xBF,0xC8,0x24,
++    0xD8,0x48,0x8E,0x34,0xD0,0x80,0x81,0x2C,0x08,0x01,0x10,0x01,0x00,0x77,0x00,0x01,
++    0x33,0x5A,0x18,0x5A,0xF2,0x5C,0x00,0xD8,0xC8,0xD8,0x04,0x1F,0x04,0x30,0x9A,0xD2,
++    0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0xCE,0xE6,0x48,0x92,0x4D,0x17,0x4A,0x9D,0x76,
++    0x08,0x01,0x10,0x01,0x03,0xE7,0x19,0x99,0x08,0xD8,0x02,0x0F,0xE6,0x48,0x92,0x4D,
++    0x02,0x21,0x19,0x42,0xCC,0x00,0x30,0x22,0xC0,0x00,0x86,0x3C,0xC8,0x03,0x44,0x79,
++    0x80,0xA6,0x07,0x01,0x00,0x2F,0xD9,0x3C,0x34,0xF1,0xF8,0xF2,0xD9,0x34,0x38,0xC9,
++    0xC0,0xB0,0x1F,0x31,0x18,0x1A,0xCA,0xD8,0x0E,0xF8,0xCD,0xD8,0x47,0xFC,0xDA,0xB0,
++    0xAB,0x06,0x10,0xB2,0x95,0xB5,0x35,0xB2,0x37,0xE9,0x08,0xB0,0x20,0x32,0x3B,0x01,
++    0xF8,0xBA,0xF7,0x2C,0x45,0xDC,0xCC,0xF0,0xD0,0x98,0xAF,0x06,0x10,0xDA,0x32,0xB2,
++    0x18,0x72,0xFB,0x5C,0x07,0xB0,0xCB,0xB0,0x22,0x9A,0x03,0x38,0x9A,0x9A,0xE7,0x00,
++    0x90,0x05,0xDE,0x0C,0x16,0xC2,0x9C,0xB6,0xE6,0x48,0x92,0x4D,0xE6,0x90,0x92,0x95,
++    0xC0,0x64,0xC0,0x03,0x15,0x82,0xC4,0xF6,0xC0,0x64,0xC8,0x0C,0xC4,0x03,0x10,0x42,
++    0xC9,0x06,0x38,0xF7,0xC1,0x0C,0x38,0xE7,0xAC,0x85,0x87,0x3D,0x34,0x22,0x00,0x91,
++    0xD4,0x02,0x34,0x22,0x01,0xC1,0xF0,0x02,0x18,0x71,0x80,0x34,0xF0,0x1A,0x9F,0x2C,
++    0xD0,0x00,0x96,0x05,0x1F,0xD1,0xF0,0x1A,0x2B,0x81,0xF8,0x2A,0x32,0xF2,0xDC,0xD8,
++    0x90,0xDD,0xA8,0x24,0xC0,0x2B,0x6F,0x09,0x8D,0x16,0x10,0x04,0x10,0x1C,0x07,0x6F,
++    0x55,0x3C,0x05,0xE8,0xC7,0x68,0x51,0x04,0x07,0x30,0xC4,0x98,0xD9,0x68,0x97,0x6D,
++    0xD0,0xC0,0x90,0x1D,0x84,0x40,0x85,0xD8,0x17,0x04,0x15,0x1C,0x4B,0x81,0x80,0xF6,
++    0xE9,0x2C,0xC0,0x40,0x02,0x28,0xCA,0x00,0xEA,0x34,0xC8,0x00,0x80,0x00,0x94,0x05,
++    0xEF,0x24,0xC0,0x58,0x02,0xE8,0xCA,0xE8,0x37,0x9A,0xC3,0x58,0x80,0xD8,0x94,0xED,
++    0x90,0x01,0x46,0x01,0xD0,0x0E,0x00,0x01,0x00,0x27,0x50,0x9C,0x10,0x1A,0xD4,0x0E,
++    0x00,0x81,0xF0,0x82,0x68,0x01,0xD0,0x0E,0x28,0x01,0x00,0x27,0x55,0x9C,0x12,0x5A,
++    0xD0,0x0E,0x28,0x91,0xF8,0xAA,0xD2,0x2C,0xD0,0x90,0xF0,0xB0,0xD2,0x06,0x10,0x92,
++    0x06,0x98,0xC2,0xB8,0xD2,0x24,0xD8,0x90,0xF0,0x98,0xD0,0x06,0x15,0x92,0xC2,0xF8,
++    0x7E,0xD0,0xCF,0x90,0x18,0x90,0x66,0x90,0x58,0x01,0xD0,0x06,0x12,0xDA,0x02,0xF8,
++    0xC8,0xD8,0x76,0x01,0xD3,0x06,0x10,0xB2,0xCE,0xD8,0x7C,0xF0,0xC6,0x98,0x1F,0xD8,
++    0x60,0xF0,0x48,0x41,0x80,0x0E,0x48,0x49,0x88,0x2E,0x48,0x49,0x8A,0x1E,0x20,0x88,
++    0x63,0x50,0x20,0x88,0x63,0x70,0x30,0x0A,0x8B,0x0C,0x28,0x12,0xCB,0x06,0x30,0x12,
++    0xCC,0x0C,0x10,0x72,0xC8,0x06,0xF0,0x0C,0xDB,0x2C,0x30,0x0A,0xD0,0x48,0x34,0x7A,
++    0x1C,0xCA,0x02,0x58,0xC4,0x48,0x36,0x72,0x19,0x51,0x30,0xCA,0xF3,0x1A,0x07,0xF8,
++    0xCA,0x48,0x1E,0x5A,0x32,0x8A,0xC3,0xC8,0x1B,0x82,0x32,0x12,0x46,0xB8,0xCA,0x00,
++    0x02,0x00,0xC6,0x00,0x36,0x0A,0x03,0x48,0x88,0x1C,0x80,0x17,0xE8,0xBF,0x80,0x14,
++    0xD0,0x24,0xC0,0x0C,0xD8,0x00,0x34,0x0A,0x1C,0x82,0x02,0x10,0xC0,0x00,0x14,0x61,
++    0xF2,0x12,0x05,0x58,0xC2,0x48,0x1E,0x52,0xC3,0x80,0x18,0xAA,0x00,0x07,0x00,0x67,
++    0xCE,0x48,0x07,0x48,0xC0,0x40,0xC8,0x1C,0x80,0x17,0xE8,0x07,0xCB,0x2C,0x08,0x0C,
++    0xCD,0x24,0x08,0x0C,0xCF,0x14,0x08,0x0C,0x10,0x04,0x81,0x3D,0xEF,0x85,0xAF,0xF5,
++    0x30,0x3A,0xC0,0x44,0x60,0xD2,0xCF,0xE0,0x2F,0x31,0x70,0xCA,0x1F,0xAA,0xC2,0x68,
++    0xF5,0x21,0xC9,0x68,0x06,0x90,0xC2,0x90,0x59,0xAA,0xDF,0x81,0xC6,0xB0,0xFE,0x13,
++    0x31,0xB2,0x34,0xDA,0x32,0x3A,0xB8,0x01,0x30,0x12,0xB8,0x0C,0x92,0x01,0xBE,0x01,
++    0x59,0x09,0x88,0x4E,0x01,0x01,0x00,0x17,0xC0,0x0B,0x49,0x79,0x89,0xE6,0x40,0x4C,
++    0x0B,0x0C,0x47,0x5C,0x14,0x1C,0x31,0xE2,0xC1,0x9B,0x89,0x1B,0xC3,0x9B,0x8B,0x1B,
++    0x1B,0x0C,0x35,0x1A,0x19,0x1C,0x27,0x0C,0x23,0x1C,0x0B,0x0C,0x09,0x1C,0x45,0x4C,
++    0x1B,0x0C,0x41,0x4C,0x19,0x0C,0x83,0x03,0x0F,0x09,0x80,0x0B,0x88,0x0B,0xFD,0x8B,
++    0x90,0x0B,0x09,0x01,0x90,0x0B,0x03,0x27,0xA2,0x21,0xE1,0x00,0x93,0x05,0x2E,0x82,
++    0x9B,0xD6,0x2E,0x82,0x94,0xF6,0x03,0x2F,0x1A,0x21,0x19,0xCA,0xC8,0x60,0x08,0x41,
++    0x89,0x04,0x40,0x4C,0x18,0x0C,0x09,0x11,0xF3,0x4A,0x1B,0x0C,0x35,0x62,0xCC,0x0B,
++    0x48,0x09,0x88,0xAE,0x08,0xC1,0x18,0xE1,0xF7,0x0A,0xF3,0x1A,0xD0,0x48,0xAE,0x06,
++    0x14,0x4A,0x92,0x4D,0x30,0x72,0x1C,0xF1,0xF3,0x1A,0x37,0x0A,0xD0,0x48,0xAE,0x06,
++    0x14,0x4A,0x92,0x4D,0xE3,0xDB,0x21,0x8A,0x10,0xCA,0xCC,0x0E,0x0D,0x01,0x88,0x0B,
++    0x09,0xC1,0x18,0x01,0xF7,0x0A,0xF3,0x1A,0xD0,0x48,0xAE,0x06,0x14,0x4A,0x92,0x4D,
++    0x30,0x62,0x0C,0xD1,0x1B,0x11,0xF1,0x0A,0xF6,0x1A,0xD7,0x48,0xAA,0x06,0x10,0x4A,
++    0x24,0x0A,0x93,0x4D,0x30,0x62,0xDC,0x0C,0xC4,0x0B,0xE7,0xDB,0xE4,0xD8,0x12,0xCA,
++    0xC8,0x7E,0xF8,0x8B,0xEE,0xDB,0x01,0xCA,0x28,0x0A,0xCB,0x56,0xD6,0x0B,0x4B,0x41,
++    0x92,0x0E,0xE0,0x48,0x91,0x0B,0xD3,0x0B,0xFC,0x9B,0x10,0xCA,0x92,0x0E,0xE0,0x48,
++    0x91,0x0B,0xD1,0x0B,0x28,0x0A,0xCB,0xA6,0xDF,0x0C,0xC0,0x0B,0xE2,0xDB,0xE4,0xD8,
++    0x10,0xCA,0xCC,0x76,0xCA,0x0B,0x37,0x50,0xE2,0xCB,0x73,0x90,0xF4,0x48,0x12,0x52,
++    0x89,0x0E,0x08,0x01,0x80,0x0B,0x35,0x12,0x09,0x81,0x30,0x02,0xBC,0xFF,0xF7,0xE7,
++    0x00,0xDF,0xD8,0x0C,0xC4,0x0B,0xE7,0xDB,0xE4,0xD8,0x12,0xCA,0xC8,0x1E,0xF8,0x8B,
++    0xEE,0xD3,0x01,0x8A,0x91,0x0B,0x59,0x0C,0x23,0x0C,0x59,0x0C,0x20,0x0C,0x33,0x12,
++    0x30,0x02,0xC9,0x04,0xBC,0xFF,0xF7,0x47,0x03,0x01,0x90,0x03,0xD0,0x03,0x41,0x01,
++    0x80,0x1E,0x00,0x07,0x02,0x3F,0xF1,0x00,0x97,0x03,0xC1,0x03,0x40,0xF9,0x93,0x0E,
++    0xE7,0x00,0x82,0x03,0x43,0x44,0x15,0x04,0x03,0x19,0x80,0x03,0xE4,0xC3,0x83,0x01,
++    0x89,0x03,0xCF,0x03,0xC2,0x8B,0xD1,0x00,0xE0,0x00,0x42,0x11,0xC3,0x2E,0xC8,0x03,
++    0xC2,0x8B,0xD3,0x00,0xE0,0x00,0x42,0x11,0xCF,0x4E,0xC0,0x03,0x40,0x11,0x98,0x36,
++    0xCA,0x0C,0xE0,0x4B,0x10,0x42,0xC4,0x16,0x07,0x01,0x80,0x03,0x89,0x03,0xC7,0x83,
++    0x8B,0x03,0xC1,0x83,0x8F,0x03,0xEB,0xF5,0xAC,0x85,0x37,0xE2,0x34,0x2A,0xAB,0x01,
++    0x4A,0x5C,0x27,0xD8,0x67,0xE0,0x40,0xF9,0x88,0x0E,0x00,0x01,0xE9,0x85,0x1F,0x21,
++    0x1B,0xC2,0x5A,0xFA,0xC6,0x00,0xC4,0x00,0x1A,0x31,0x18,0xCA,0xC3,0x48,0x54,0xE2,
++    0xD4,0x21,0xC1,0x50,0x0A,0xA1,0xF0,0x0A,0x48,0x01,0xD0,0x06,0x10,0x4A,0x1A,0xB1,
++    0xF0,0x1A,0x5E,0x01,0xD2,0x06,0x10,0xDA,0xC3,0x48,0x5E,0xB2,0x10,0xCA,0x9C,0x06,
++    0x08,0x01,0x30,0x71,0x44,0x9C,0xF8,0x32,0xD8,0xD8,0xAC,0x06,0x10,0xDA,0x32,0x81,
++    0x44,0x94,0xFA,0x32,0xD8,0x90,0xAC,0x06,0x14,0x92,0xC2,0xD0,0x11,0x12,0x9D,0x0E,
++    0xC8,0x33,0x74,0x09,0x8B,0x26,0xE0,0x5B,0xCA,0x3B,0xF6,0xD8,0x10,0xFA,0xDC,0xBE,
++    0x70,0x09,0x88,0x3E,0xDC,0x5B,0x11,0x5A,0x9E,0x26,0xC0,0x03,0x40,0xF1,0xC0,0x0E,
++    0x40,0x51,0x90,0x6E,0x70,0x09,0x88,0x1E,0x30,0x02,0x5B,0x04,0x40,0xC1,0x98,0x3E,
++    0x70,0x09,0x88,0x16,0x04,0x00,0x13,0x82,0xCD,0x16,0x00,0x00,0x10,0x82,0xC4,0x0E,
++    0x07,0x01,0xE8,0x85,0x07,0x09,0xE8,0x85,0xAC,0xFD,0x87,0x5D,0x30,0xB2,0x0C,0x01,
++    0x28,0x01,0x00,0x01,0x80,0x14,0xC0,0xA4,0xF8,0x23,0x06,0x01,0x30,0x22,0x84,0x34,
++    0x00,0x27,0xD0,0x64,0x02,0xF9,0xA7,0x82,0xE6,0x48,0x92,0x4D,0x17,0x0A,0x9D,0xC6,
++    0xD3,0x74,0x28,0x92,0xC0,0x26,0xC0,0x74,0x83,0x24,0x30,0x82,0x80,0x1C,0x00,0x1F,
++    0x30,0x82,0x83,0x24,0xC0,0x74,0x80,0x1C,0x00,0x01,0x80,0x2C,0x00,0xD7,0x1A,0x01,
++    0x03,0xB7,0x32,0x02,0x06,0xC2,0x3E,0x00,0x8A,0x86,0x42,0x32,0x80,0x3C,0x00,0x01,
++    0xD0,0xA4,0xF0,0x5C,0xF8,0x93,0x90,0x54,0x33,0xD2,0x18,0x12,0x05,0xB8,0xCA,0xD0,
++    0x90,0x4C,0x00,0x6F,0xF6,0x34,0x00,0x32,0x38,0x90,0x8F,0x3E,0xF2,0x4C,0x00,0x38,
++    0xD8,0xB2,0xFF,0x3C,0x10,0xF2,0x95,0x0E,0xB0,0x3C,0x30,0x0A,0xE6,0x00,0x92,0x05,
++    0xD4,0x54,0x10,0x12,0xC1,0x76,0x77,0xBA,0x02,0x01,0x00,0x78,0xB8,0x44,0x00,0x87,
++    0x36,0x3A,0x03,0x3A,0x38,0xF8,0x8F,0x56,0x33,0x3A,0x18,0x3A,0xD3,0x5C,0x00,0xF8,
++    0xC0,0xF8,0xD5,0x44,0xD5,0xFA,0x15,0xBA,0xC1,0x0E,0x30,0xF2,0x32,0x2A,0xE0,0x00,
++    0x93,0x05,0x2E,0x82,0x9C,0x66,0x17,0xEA,0x88,0xA6,0xC0,0x14,0xC8,0x00,0x84,0x14,
++    0xC2,0x2C,0xE0,0x00,0x90,0x05,0x86,0x2C,0xC2,0x64,0xA0,0x2A,0x31,0x09,0x30,0x82,
++    0xD4,0x34,0x00,0x42,0x1C,0x82,0x90,0x05,0x85,0x34,0x00,0x72,0x30,0x02,0x1B,0x32,
++    0x94,0x85,0x35,0x22,0xD0,0x24,0xC0,0x2C,0x10,0x82,0x84,0x1E,0xE6,0xD8,0x92,0xDD,
++    0x2D,0x9A,0x9B,0x36,0xD0,0x24,0xC0,0x2C,0x15,0x82,0x9C,0x06,0xC0,0x14,0x80,0x3C,
++    0x10,0x01,0x00,0x01,0x0B,0x01,0x30,0x5A,0x80,0xCB,0x18,0x01,0x0C,0x01,0x30,0x62,
++    0x30,0x4A,0xE3,0x4A,0x02,0x0F,0xE0,0x48,0x90,0x4D,0x36,0xEA,0x07,0x6A,0x3E,0x68,
++    0x88,0xCE,0xEF,0x1C,0x10,0x4A,0x9D,0xFE,0x40,0x01,0x88,0x8E,0x08,0xF9,0x07,0x5F,
++    0xD0,0x64,0xE0,0x9A,0x28,0x9A,0x93,0x1E,0xD0,0xA4,0xF8,0x93,0x10,0x12,0xC4,0x0E,
++    0xD0,0x64,0xA0,0x8A,0xE6,0x00,0x92,0x05,0x17,0x02,0x9D,0x8E,0x87,0x7D,0xE8,0x85,
++    0xF6,0x00,0x92,0x05,0x30,0x4A,0xE3,0x4A,0x2D,0x09,0x30,0x62,0x00,0x6F,0x01,0x00,
++    0x70,0x30,0x03,0x00,0xF8,0xFF,0x07,0x00,0x33,0x6A,0x18,0x2A,0xFB,0x5C,0x00,0x70,
++    0xCA,0xB0,0x07,0x38,0xDD,0xAA,0xC7,0x50,0x2C,0x09,0x00,0x6A,0x1D,0xEA,0x90,0x5D,
++    0x31,0x72,0xA3,0x8A,0xED,0x3C,0x10,0x52,0x98,0x16,0x28,0x11,0x30,0x62,0x05,0xA7,
++    0xFA,0x74,0xE0,0x28,0x10,0xEA,0x9D,0x6E,0x90,0x3C,0x08,0x01,0x00,0x27,0xF8,0x64,
++    0xE3,0xAA,0xA3,0xEA,0xE6,0x48,0x92,0x4D,0x17,0x0A,0x9D,0xC6,0xE0,0x8A,0x29,0x09,
++    0x30,0x62,0x05,0x17,0x90,0x45,0x2F,0x01,0xA3,0xAA,0x31,0x2A,0x6D,0x01,0x80,0x2E,
++    0x33,0x6A,0x18,0x2A,0xFB,0x5C,0x00,0x70,0xCA,0xB0,0x07,0x38,0xDA,0xAA,0xDF,0x90,
++    0x2C,0x09,0x00,0x6A,0x1B,0x5A,0x35,0x6A,0xE2,0x4A,0xE1,0x48,0xA4,0x4A,0x39,0xAF,
++    0xAC,0xC5,0x37,0x22,0xFC,0x73,0x5E,0xAA,0x36,0x02,0xC3,0x00,0x31,0x32,0x34,0xAA,
++    0x38,0x21,0x31,0x62,0x1A,0xEA,0xA3,0x01,0x13,0x01,0x20,0x2A,0xC0,0x68,0x07,0xF7,
++    0xC0,0x1B,0x58,0x79,0x86,0xD6,0xC8,0x1B,0x30,0xD8,0xA0,0x3E,0x18,0xF9,0x8F,0x1B,
++    0x8E,0x1B,0xC2,0x1B,0xE5,0x3B,0x15,0xDA,0xC6,0x06,0x88,0x13,0xCA,0x1B,0x36,0xD8,
++    0x76,0xD8,0x8A,0x1B,0x58,0x01,0x80,0x0E,0xF6,0xD8,0x8A,0x1B,0xC8,0x1B,0x5E,0x01,
++    0x8A,0x26,0xC0,0x1B,0x44,0xD8,0x04,0xD8,0x84,0x1B,0x82,0x13,0x84,0x21,0x11,0x2A,
++    0xC0,0xF6,0x06,0x01,0x84,0x04,0xB8,0x53,0x30,0x82,0x03,0x8F,0xC5,0x13,0x10,0x92,
++    0x96,0x5E,0xC0,0x13,0xE2,0x3B,0x35,0x98,0x75,0xD8,0x12,0xDA,0xCC,0x2E,0xC0,0x13,
++    0x50,0x01,0x81,0x16,0x00,0x09,0x80,0x04,0x00,0x27,0x10,0x01,0x81,0x13,0x84,0x21,
++    0x17,0x2A,0xC4,0x5E,0xC0,0x04,0x40,0x01,0x83,0x76,0x31,0x92,0x36,0x5A,0x98,0x01,
++    0x00,0x47,0x01,0x01,0x80,0x83,0xC4,0x83,0x11,0x82,0x95,0x16,0xC2,0x83,0x36,0x38,
++    0xE3,0x03,0x75,0xF8,0x10,0x3A,0xCC,0xE6,0x04,0x09,0x80,0x83,0xFA,0x43,0xE4,0x00,
++    0xB8,0x43,0x3C,0x71,0xF8,0xBA,0x7E,0x01,0xD0,0x16,0x00,0x01,0x08,0x84,0x06,0x27,
++    0x54,0xC4,0x10,0x3A,0xE8,0x0E,0x50,0xC4,0x08,0x84,0x3E,0x81,0xF8,0xBA,0x7E,0x01,
++    0xD0,0x16,0x00,0x01,0x10,0x84,0x00,0x27,0x54,0xC4,0x12,0x3A,0xEA,0x0E,0x50,0xC4,
++    0x11,0x84,0x90,0x21,0x16,0xAA,0xC4,0xA6,0xF8,0x43,0x40,0x01,0x88,0x36,0x58,0x44,
++    0x16,0xE9,0x03,0x90,0x10,0x82,0x94,0x0E,0xE0,0x00,0x1A,0x44,0xF8,0x43,0x44,0x01,
++    0x80,0xCE,0x10,0x01,0x03,0x01,0x28,0x99,0x0E,0x68,0xFB,0x63,0x01,0x6F,0x18,0x21,
++    0x1B,0x1A,0x22,0x1A,0xC8,0xD8,0xD2,0xF3,0x70,0x09,0x88,0x26,0xC8,0xDB,0x5E,0x19,
++    0x8A,0x0E,0xE0,0x90,0x92,0x95,0xE6,0x00,0x94,0x05,0x16,0x22,0xC0,0x7E,0x57,0x01,
++    0x88,0x0E,0x00,0x01,0x1F,0x44,0xE8,0xC5,0xAC,0x85,0x87,0x3D,0x30,0x2A,0x30,0x62,
++    0x41,0x12,0xC2,0x40,0x08,0x29,0xEE,0x4A,0x4B,0x29,0x80,0xDE,0x4B,0x02,0xC2,0x70,
++    0xEB,0x48,0xC4,0x48,0x89,0x1C,0x48,0xF2,0x8B,0x61,0xC0,0x48,0x88,0x14,0x08,0x01,
++    0x10,0xF9,0x1F,0x79,0x03,0x3F,0xA0,0x92,0xC8,0x3B,0x7E,0x01,0x88,0x06,0x80,0x1B,
++    0xE6,0x48,0x92,0x4D,0x87,0x21,0xF9,0x3B,0x17,0x7A,0xC4,0xA6,0x00,0x01,0x80,0x34,
++    0xF8,0x03,0x41,0x01,0x80,0xCE,0xB2,0x04,0x31,0x0A,0x31,0x42,0x58,0x2D,0xD0,0x14,
++    0xBA,0xFF,0xDF,0x97,0x80,0x34,0xC0,0x34,0x40,0x01,0x88,0x76,0x30,0x01,0x00,0x47,
++    0x31,0x5A,0x31,0x92,0x08,0xF9,0x07,0x09,0xA7,0x04,0xB8,0xFF,0xE3,0x47,0xE7,0xB0,
++    0x91,0xB5,0xFF,0x03,0x17,0x82,0xC5,0x9E,0x00,0xFF,0xC1,0x34,0x40,0x09,0x88,0x96,
++    0xC1,0xB3,0x31,0x1A,0x30,0x52,0x09,0x01,0x37,0x82,0xB9,0xFF,0xE8,0x2F,0x46,0x01,
++    0x80,0x0E,0x00,0x01,0x00,0x07,0x00,0x09,0x30,0x5A,0x11,0x01,0x30,0x8A,0xA1,0x04,
++    0xBE,0xFF,0xE7,0x6F,0x00,0x4F,0xA1,0x04,0xFB,0x3B,0x31,0x5A,0xE9,0xD3,0x30,0xDA,
++    0xC8,0x1C,0xC0,0x14,0xB8,0xFF,0xF7,0x47,0x38,0x01,0x00,0xDF,0xC6,0x1C,0xE8,0x02,
++    0x40,0xF9,0x87,0x16,0xE0,0x82,0x81,0x24,0x07,0x0F,0x00,0xF9,0x81,0x24,0x30,0x1A,
++    0x31,0x52,0x31,0xCA,0xC7,0x24,0xB8,0xFF,0xE8,0xFF,0x44,0x01,0x80,0x0E,0x00,0x01,
++    0x00,0x07,0x00,0x09,0x31,0x5A,0x31,0xD2,0xA0,0x04,0xC8,0x24,0xBD,0xFF,0xE7,0x3F,
++    0xE7,0xF8,0x93,0xFD,0xFD,0x03,0x11,0xC2,0xC1,0x06,0x37,0x0A,0x30,0x42,0xD1,0x34,
++    0xBE,0xFF,0xF7,0xB7,0x20,0xCF,0x04,0x01,0x38,0x82,0x03,0x00,0x70,0x30,0x03,0x00,
++    0x48,0xE0,0x06,0x00,0xAE,0xFD,0x87,0x5D,0xC6,0xAC,0xDA,0x03,0x82,0xCC,0xC1,0xAC,
++    0xD9,0x03,0x84,0xC4,0x01,0x09,0x58,0x45,0x81,0xC3,0xC0,0xC4,0xE2,0x00,0x82,0xC3,
++    0xC4,0xC4,0x81,0xC3,0xC2,0xC4,0xF1,0x00,0x82,0xC3,0xC6,0xAC,0x82,0x01,0x87,0x54,
++    0xC0,0x0B,0x00,0x21,0x1A,0x0A,0xC0,0x54,0x82,0x0B,0xC0,0xAC,0xCA,0x03,0x42,0x00,
++    0x80,0xD4,0x09,0x01,0x40,0xB5,0x31,0x52,0x00,0x36,0x00,0x01,0x82,0xF4,0xC0,0xAC,
++    0xCC,0xB4,0x82,0x01,0x82,0x4C,0xC2,0x74,0x92,0x05,0x82,0x44,0xC2,0x6C,0x92,0x05,
++    0x82,0x3C,0xC2,0xAC,0x82,0x01,0x86,0x34,0x4B,0x11,0x80,0xBE,0x10,0x01,0x00,0x01,
++    0x4C,0x45,0xB1,0x4A,0x8F,0x2C,0x4A,0xF2,0xB2,0x4A,0x8C,0x24,0x48,0xE2,0xEF,0x48,
++    0xB2,0x4A,0x8C,0x1C,0x04,0x08,0xC4,0x48,0x91,0x4D,0x66,0x9D,0xDB,0x74,0xA2,0x1A,
++    0x62,0x85,0xD9,0x6C,0xA2,0x1A,0xDB,0x24,0x9A,0x34,0xD9,0x1C,0x9A,0x2C,0xD9,0x2C,
++    0x98,0x24,0x41,0x09,0x89,0x5E,0xD8,0x34,0x12,0xDA,0x92,0xDD,0x99,0x34,0xD9,0x2C,
++    0x12,0xDA,0x92,0xDD,0x99,0x2C,0xD9,0x24,0x12,0xDA,0x92,0xDD,0x9A,0x24,0xD9,0x5C,
++    0x32,0xE2,0xDC,0x64,0x9A,0x5C,0xD9,0x3C,0xE1,0x44,0xEA,0x2C,0xCA,0xD8,0x92,0xDD,
++    0xEB,0x34,0xC9,0x20,0x91,0x25,0xF3,0x24,0xED,0x5C,0xC9,0x68,0xA8,0x5C,0x59,0x01,
++    0xD9,0x86,0xEB,0xCC,0x13,0x5A,0xD5,0x6E,0x63,0x01,0xD8,0x5E,0xED,0xC4,0x11,0x62,
++    0xD1,0x46,0xEB,0x5C,0xC5,0x6B,0x49,0x68,0x8B,0x06,0x32,0x2A,0x3F,0x01,0xF8,0x7A,
++    0xEB,0x24,0x01,0x68,0x23,0x62,0x35,0x32,0x2B,0x01,0xF8,0xAA,0xF5,0xD4,0x11,0xAA,
++    0xEA,0xC6,0xF2,0xB4,0x71,0x09,0x88,0x16,0xD9,0xF0,0x93,0xB5,0xB2,0x9C,0xF8,0x5C,
++    0x35,0x01,0xF8,0xF2,0x10,0x72,0xDD,0x06,0x37,0xAA,0x81,0x68,0x01,0x68,0x33,0x7A,
++    0xF3,0x9C,0x10,0x6A,0x12,0xAA,0xE5,0x2E,0x6B,0x9D,0xA1,0x62,0x6B,0x85,0xA1,0x5A,
++    0x01,0xA8,0x72,0xB5,0xC9,0x68,0xE5,0x72,0xE1,0xB0,0xA3,0x72,0xEB,0xF4,0xE0,0x68,
++    0x90,0x6D,0xAF,0xF4,0xF5,0x9C,0x10,0xBA,0xD1,0xBE,0x05,0x9F,0x09,0xEF,0x6A,0x9D,
++    0xA1,0x62,0x6B,0x85,0xA2,0x5A,0x03,0xA8,0x75,0xB5,0xC9,0x68,0xE3,0x72,0xE1,0xB0,
++    0xA0,0x72,0xE9,0xF4,0xE7,0x68,0x93,0x6D,0xAD,0xF4,0x38,0x37,0xE9,0x5C,0xC1,0x6B,
++    0x48,0x68,0x6D,0x19,0x8A,0x6E,0x00,0xB0,0x7F,0xB5,0xC9,0xB0,0xE0,0xB2,0x71,0x09,
++    0xC2,0x3E,0xC0,0x64,0x08,0x01,0xC6,0x03,0x1A,0x42,0xC8,0x64,0x82,0x43,0x80,0x7D,
++    0xE8,0x85,0x6F,0x11,0x89,0x56,0x68,0x9D,0xA1,0x62,0x63,0x85,0xA2,0x1A,0x03,0x98,
++    0x4A,0xB5,0xC1,0xC8,0xE2,0x5A,0xE0,0xD8,0xA0,0x5A,0x00,0x1F,0xCE,0x34,0xCA,0x4B,
++    0x4F,0x51,0x90,0x66,0xE6,0x00,0x92,0x05,0x40,0x11,0x90,0x06,0x3A,0xD7,0xE2,0x90,
++    0x90,0x95,0x56,0x21,0x92,0x06,0x38,0x57,0x01,0x01,0x80,0x64,0xC0,0xB4,0x42,0x09,
++    0x88,0xF6,0x03,0x01,0x80,0x7C,0x01,0x01,0x81,0x74,0xC9,0x7C,0x42,0xB5,0x01,0x48,
++    0xC2,0x40,0x80,0x14,0xC1,0x74,0xC9,0x7C,0x02,0x00,0xC4,0x00,0x91,0x05,0x86,0x4C,
++    0xCA,0x74,0xC1,0x14,0xE0,0x2A,0x6A,0x09,0xC1,0x26,0xC0,0x64,0xE6,0x00,0x92,0x05,
++    0x87,0x64,0x01,0x8F,0xC0,0x74,0x41,0x09,0x89,0x16,0xC0,0x7C,0x47,0x01,0x88,0xC6,
++    0x08,0x81,0x41,0x45,0x83,0x17,0xC0,0x77,0xC0,0x6C,0x82,0x3C,0xC0,0x74,0x82,0x34,
++    0xC0,0x5C,0x82,0x0C,0xC0,0x64,0x82,0x04,0xC4,0x7C,0xE1,0x00,0x3C,0x00,0x7C,0x00,
++    0x50,0x5A,0xB4,0xA2,0xE8,0x98,0xB0,0xCA,0x31,0x62,0x74,0x45,0xB1,0x8A,0xC1,0x7C,
++    0xB0,0x82,0x80,0x24,0xC0,0x7C,0xB1,0xC2,0x81,0x1C,0xD0,0x7C,0xB0,0x82,0x85,0x14,
++    0xC0,0x74,0x41,0x09,0x88,0x5E,0xC0,0x24,0x12,0x02,0x92,0x05,0x80,0x24,0xC0,0x1C,
++    0x12,0x02,0x92,0x05,0x80,0x1C,0xC0,0x14,0x12,0x02,0x92,0x05,0x80,0x14,0x00,0x01,
++    0x83,0x2C,0xE0,0x68,0xAD,0xF4,0x01,0x9F,0x40,0x61,0x98,0x66,0xC8,0x24,0xC0,0x34,
++    0xD2,0x4C,0xD1,0x00,0x4C,0x9D,0xA1,0x42,0xC8,0x1C,0xC0,0x3C,0xD2,0x4C,0xD1,0x00,
++    0x4C,0x85,0xA1,0x42,0x00,0x47,0x15,0x01,0xDC,0x0C,0x00,0x28,0xF0,0xD2,0x5C,0x45,
++    0x88,0xD2,0x12,0x01,0x90,0x6C,0xD1,0x3C,0x92,0x95,0x92,0x0C,0xD2,0x34,0x90,0x95,
++    0x91,0x04,0xD2,0x6C,0x50,0x09,0x88,0x3E,0x12,0x12,0x93,0xA5,0x32,0x12,0x13,0x92,
++    0x94,0x95,0x32,0xA2,0x12,0x4A,0x92,0x4D,0xD2,0x0C,0xDA,0x04,0xF0,0x0C,0x00,0x07,
++    0x01,0xEF,0xB4,0x1C,0xF1,0x04,0xB0,0x5C,0x01,0x70,0xB2,0xFC,0x22,0x12,0x93,0x95,
++    0xCA,0xD8,0x90,0xDD,0xF9,0x1C,0xF1,0xFC,0xC9,0xB0,0xB7,0x1C,0xF3,0x5C,0xC1,0xB0,
++    0xB0,0x5C,0x51,0x01,0xD9,0xBE,0xF0,0xCC,0x10,0x92,0xD5,0xA6,0x58,0x01,0xD8,0x96,
++    0xF5,0xC4,0x11,0x9A,0xD1,0x7E,0xF8,0x1C,0x35,0x01,0xF8,0xF2,0xF9,0x5C,0xC1,0xFB,
++    0x48,0xF8,0x8D,0x46,0xFD,0xD4,0x11,0xF2,0xE8,0x2E,0x78,0x45,0xCD,0xFA,0xCB,0xF0,
++    0x7B,0x45,0x88,0xF2,0x39,0xD7,0xD6,0x6C,0xE6,0x90,0x92,0x95,0x91,0x6C,0xD1,0x6C,
++    0x55,0x11,0x98,0xF6,0x41,0x01,0x80,0xF6,0xF2,0x10,0xF2,0x4C,0x00,0x90,0x5C,0x45,
++    0xC7,0xD2,0xD4,0xB3,0xCC,0xDA,0xCA,0xB0,0x11,0xF2,0x94,0x86,0xD0,0x2C,0x50,0x09,
++    0x88,0x8E,0xD1,0x24,0xC1,0x34,0xD8,0x4C,0xD1,0x00,0x54,0x9D,0xA0,0x82,0xDE,0x1C,
++    0xD1,0x3C,0xE8,0x4C,0xD1,0x90,0x5E,0x85,0xA8,0xD2,0xEA,0x14,0xDA,0x04,0xD8,0xE8,
++    0x36,0x1A,0xD3,0x90,0x90,0x95,0xDA,0x00,0x93,0x1D,0xD2,0x40,0x2C,0x01,0x38,0x01,
++    0x50,0x01,0xD8,0x56,0xF5,0xCC,0x11,0x92,0xD0,0x3E,0x58,0x01,0xD9,0x2E,0xF0,0xC4,
++    0x10,0x9A,0xD5,0x16,0xC1,0x33,0x18,0xF2,0x83,0x33,0x20,0x12,0x90,0x95,0xCA,0xD8,
++    0x92,0xDD,0xC2,0x00,0xE7,0x68,0x93,0x6D,0x6F,0x11,0xC8,0x4E,0x04,0xE7,0x10,0x9A,
++    0x90,0x0E,0x10,0x09,0x90,0x2C,0xD8,0x24,0xD6,0x34,0xC0,0x90,0x90,0x95,0x96,0x34,
++    0xD8,0x1C,0xD0,0x3C,0xC6,0x90,0x96,0x95,0x90,0x3C,0xD0,0x14,0xDA,0x0C,0x00,0x90,
++    0xC0,0x90,0x96,0x0C,0xD8,0x14,0xD0,0x04,0xC0,0x90,0x96,0x04,0xE6,0x00,0x92,0x05,
++    0xD4,0xF4,0x11,0x82,0x92,0x06,0x38,0x3F,0xC2,0x74,0xE1,0x00,0x91,0x05,0x86,0x74,
++    0xC0,0x74,0x41,0x11,0x97,0x06,0x30,0xAF,0xC2,0x7C,0xE1,0x00,0x91,0x05,0x86,0x7C,
++    0xC0,0x7C,0x41,0x21,0x97,0x06,0x30,0x37,0x00,0x0F,0x00,0x41,0x81,0x64,0xC1,0x64,
++    0x41,0x41,0x88,0xD6,0x10,0x01,0x00,0x01,0x58,0x8A,0xE8,0xC8,0xB4,0xF2,0xB4,0x7A,
++    0x31,0x8A,0x31,0xDA,0x40,0x09,0x88,0x1E,0x12,0x4A,0x92,0x4D,0x12,0xDA,0x92,0xDD,
++    0xE7,0x6C,0xC2,0x18,0x92,0xDD,0xE2,0x74,0xC2,0x08,0x93,0x65,0x04,0x08,0xC4,0x48,
++    0x90,0x4D,0x5E,0x01,0xD9,0x76,0xE8,0xCC,0x10,0x5A,0xD5,0x5E,0x60,0x01,0xD8,0x4E,
++    0xED,0xC4,0x11,0x62,0xD1,0x36,0x68,0x9D,0xA1,0x62,0x63,0x85,0xA0,0x1A,0x03,0x3F,
++    0x70,0x52,0x07,0x00,0x62,0x9D,0xD9,0x74,0xA1,0x1A,0x63,0x85,0xDB,0x6C,0xA2,0x1A,
++    0xE6,0x00,0x92,0x05,0x46,0x11,0x98,0x9E,0xE6,0x90,0x92,0x95,0x56,0x21,0x98,0x56,
++    0x58,0x85,0xD9,0xC3,0xA8,0xC3,0xC0,0xC3,0x90,0xC3,0x00,0x01,0x81,0xFC,0x58,0x85,
++    0xD8,0xC3,0xA8,0xC3,0xC0,0xC3,0x90,0xC3,0x00,0x01,0x80,0xE4,0x30,0x3A,0x80,0xEC,
++    0xC4,0xAC,0xCA,0x03,0x80,0xD4,0x01,0x01,0x0E,0x01,0x00,0x18,0x54,0xA5,0xC0,0xD0,
++    0x32,0xA2,0x04,0x20,0xC6,0x10,0x93,0x95,0x6D,0x9D,0xE1,0x72,0x33,0x2A,0xA3,0x72,
++    0x6D,0x85,0xE1,0x6A,0x32,0x12,0xC3,0x90,0x8A,0xAB,0xE0,0x48,0x90,0x4D,0x4E,0x19,
++    0x98,0x86,0x47,0x09,0x80,0x0E,0x40,0x19,0x88,0x66,0x60,0xA5,0xE3,0x0A,0x37,0x12,
++    0xCB,0x93,0x30,0x2A,0xC7,0x6B,0xA5,0x2A,0x34,0x1A,0xCB,0xE3,0x8C,0xE3,0x80,0xCB,
++    0x34,0x0A,0x8B,0x53,0x09,0x09,0x88,0x0C,0x09,0x01,0x88,0x74,0xD3,0x74,0x31,0x0A,
++    0xE1,0x4A,0xDC,0x74,0x36,0x12,0xC3,0x90,0xCA,0x9B,0xC0,0xAB,0xC9,0x93,0x92,0x14,
++    0xD0,0x74,0x51,0x01,0x88,0x16,0x41,0x01,0x80,0x0E,0x40,0x19,0x8D,0x5E,0x10,0x4A,
++    0x98,0x4E,0x10,0x09,0x90,0x04,0x41,0x01,0x8A,0x16,0xF0,0x10,0x90,0x0C,0x01,0xF7,
++    0x11,0x09,0x90,0x0C,0x00,0xDF,0x40,0x09,0x80,0x0E,0x40,0x11,0x8D,0x5E,0x10,0x4A,
++    0xC0,0x4E,0x10,0x09,0x90,0x04,0x41,0x09,0x8C,0x16,0xF0,0x10,0x90,0x0C,0x01,0x77,
++    0x11,0x09,0x90,0x0C,0x00,0x5F,0x10,0x01,0x90,0x04,0x01,0x47,0x11,0x09,0x90,0x04,
++    0x40,0x11,0x90,0x16,0xF1,0x90,0x94,0x0C,0x00,0x0F,0x10,0x09,0x90,0x0C,0x41,0x01,
++    0x80,0x0E,0x40,0x19,0x8D,0x0E,0x10,0x4A,0x90,0x2E,0x40,0x09,0x80,0x0E,0x40,0x11,
++    0x8D,0x26,0x10,0x4A,0xC0,0x16,0x10,0x09,0x94,0x54,0x01,0x8F,0x11,0x01,0x90,0x54,
++    0x01,0x77,0xF4,0xC4,0x33,0x12,0x19,0x92,0xF1,0xA4,0x92,0xE4,0xC9,0x90,0xF4,0xEC,
++    0xC9,0x90,0x94,0x5C,0xD0,0x5C,0xC1,0x93,0x92,0xDC,0x31,0x90,0xA1,0xCE,0xD1,0xE4,
++    0xF2,0xA4,0x02,0x90,0xC9,0x90,0xF4,0x3C,0x04,0xB0,0xCB,0x90,0x35,0x39,0x09,0xB0,
++    0xC8,0xB0,0x14,0xE1,0xF1,0x92,0xF5,0xD4,0x10,0x92,0xD5,0x26,0xF0,0x64,0x71,0x41,
++    0x88,0xB6,0x50,0x01,0xD9,0xA6,0xF0,0xDC,0x48,0xB0,0x87,0x06,0x80,0x90,0xF2,0xE4,
++    0xC0,0xB0,0xB5,0xE4,0xF2,0x3C,0x19,0xB2,0xC8,0xB8,0xF7,0xEC,0x1C,0x12,0xCB,0x90,
++    0x90,0xEC,0xD0,0xFC,0xE4,0x90,0x92,0x95,0x91,0xFC,0xD0,0xDC,0x48,0x90,0x8E,0xEE,
++    0xD0,0x4C,0xF2,0xF4,0xD5,0x93,0x12,0x92,0xC1,0x2E,0xD0,0xDC,0x31,0x01,0x1E,0x92,
++    0xF1,0x5C,0x81,0x93,0x01,0x47,0xD0,0xDC,0x31,0x01,0x1A,0x92,0xF1,0x5C,0x81,0x93,
++    0x01,0x17,0xD0,0x04,0x50,0x09,0x80,0x4E,0xD0,0x04,0x51,0x09,0x8A,0x36,0xD0,0x6C,
++    0x10,0xA2,0x84,0x1E,0xD5,0x0C,0xC1,0x10,0x95,0xA5,0x3A,0x57,0x10,0x4A,0x8D,0xDE,
++    0xD4,0x14,0x11,0x9A,0x89,0xC6,0xC8,0x74,0xE6,0x48,0x92,0x4D,0x89,0x74,0xC9,0x74,
++    0x48,0x11,0x90,0x06,0x3A,0x97,0xE2,0x00,0x90,0x05,0x46,0x21,0x91,0x06,0x38,0x1F,
++    0xC6,0x34,0xCA,0x03,0x42,0x01,0x88,0x5E,0xC9,0xAC,0x8A,0x01,0xE0,0x43,0x36,0x10,
++    0xAA,0x36,0x31,0x00,0x71,0x00,0x04,0x27,0xD0,0x54,0x51,0x01,0x8D,0x5E,0x10,0x4A,
++    0xCA,0x16,0xF0,0x48,0x90,0x4D,0x06,0x1F,0x10,0x4A,0x95,0x0E,0xE6,0x48,0x92,0x4D,
++    0x11,0x09,0x90,0x54,0x01,0x67,0xD0,0x14,0x10,0x9A,0xCC,0x16,0xF6,0xD8,0x92,0xDD,
++    0x01,0x27,0xD0,0x14,0x10,0x9A,0x94,0x0E,0xE6,0xD8,0x92,0xDD,0x11,0x01,0x90,0x54,
++    0x91,0x55,0x92,0x3C,0x97,0xE5,0x72,0xFA,0xD4,0x3C,0xC9,0x90,0x93,0xEC,0x39,0x47,
++    0x02,0x01,0xD0,0xAC,0x6C,0x94,0x16,0x12,0x9A,0xD6,0xC0,0xAC,0xE8,0x4B,0x70,0x04,
++    0x10,0x42,0x9C,0x26,0xC4,0x4C,0xD2,0x03,0xF6,0x00,0x94,0x05,0x02,0x1F,0xC0,0x4C,
++    0xD4,0x03,0xE4,0x00,0x90,0x05,0xCE,0xFC,0x10,0x0A,0x9C,0x4E,0xC0,0xAC,0x0A,0x01,
++    0xBA,0x0B,0xC0,0x54,0x08,0xD9,0xC7,0x03,0x02,0x42,0xC8,0x54,0x82,0x43,0x28,0x37,
++    0x27,0x01,0x28,0xF9,0xA8,0x09,0x60,0x01,0x8A,0x56,0xC0,0x44,0xC8,0xC4,0xB9,0x9C,
++    0xD2,0x34,0x4A,0x93,0x92,0x94,0xD0,0x74,0x5A,0x3A,0x07,0x90,0xF0,0xF2,0x04,0x57,
++    0xC1,0x3C,0xCA,0xCC,0xD0,0xEC,0x90,0x9C,0xD4,0x34,0x4A,0x93,0x92,0x94,0xD0,0x6C,
++    0x5A,0x12,0x07,0x90,0xF0,0xF2,0x44,0x01,0x82,0x16,0xF0,0x48,0x10,0x42,0x8C,0x8E,
++    0xD0,0x74,0x92,0x04,0x91,0x05,0x36,0x0A,0xDA,0x6C,0xD2,0x5C,0xBB,0xEF,0xD7,0x77,
++    0x35,0x4A,0x11,0x42,0xE8,0x0E,0x30,0x42,0x00,0x17,0x40,0x01,0xD0,0x06,0x00,0x01,
++    0xC8,0x30,0x04,0x07,0xB0,0x01,0xC4,0x9C,0xC8,0xE4,0x10,0x00,0x86,0x0F,0xE8,0x27,
++    0xCC,0x94,0xC8,0x00,0x18,0x42,0x42,0x01,0xD0,0x06,0x00,0x01,0xA0,0x00,0x60,0x01,
++    0x8A,0x7E,0xC8,0x34,0x54,0x4C,0x10,0x0A,0xD0,0x06,0x30,0x42,0xC8,0xAC,0x12,0x31,
++    0xFA,0x4B,0x18,0x8A,0xD4,0xA4,0xC2,0x48,0x14,0xC9,0x09,0x90,0xC2,0x48,0x04,0x44,
++    0x02,0x77,0xC8,0x34,0x54,0x4C,0x12,0x0A,0xD0,0x06,0x30,0x42,0xC8,0xAC,0x12,0x31,
++    0xFA,0x4B,0x18,0x8A,0xD4,0xA4,0xC2,0x48,0x14,0xC9,0x09,0x90,0xC4,0x48,0x04,0x44,
++    0xE7,0x20,0x93,0x25,0x64,0x09,0xC8,0xF6,0xC0,0xAC,0x12,0x31,0xE0,0x0B,0xC2,0xE4,
++    0x02,0x42,0xCE,0xAC,0xFA,0x4B,0x18,0x8A,0xD4,0xA4,0xC2,0x48,0x14,0xC9,0x09,0x90,
++    0xC6,0x48,0x04,0x44,0xC2,0xAC,0xCA,0x74,0xFA,0x03,0x00,0x10,0xC0,0xA4,0xC2,0x90,
++    0x02,0x89,0x0B,0x00,0xC4,0x90,0xA8,0x8B,0xCA,0xAC,0xD2,0x6C,0xFA,0x4B,0x00,0x58,
++    0xCA,0xA4,0xC2,0xC8,0xC6,0x40,0xA8,0x13,0xC2,0xAC,0xCA,0xAC,0xFA,0x03,0xE0,0x00,
++    0xBD,0x43,0x20,0xE7,0xAC,0xFD,0x87,0xBD,0xEC,0x04,0x31,0xA2,0xD8,0x43,0x87,0x84,
++    0xD8,0x43,0x85,0x7C,0xC8,0x43,0x81,0x74,0x00,0x01,0x80,0x54,0x42,0x22,0x45,0x0B,
++    0x36,0x42,0x81,0x01,0x80,0xB4,0x48,0x01,0x80,0x1E,0xC0,0x74,0x40,0x00,0x82,0x5C,
++    0x00,0x67,0xC0,0xB4,0xC8,0x03,0x46,0x51,0x98,0x26,0xC8,0xB4,0x00,0x49,0xB0,0x42,
++    0x80,0x5C,0x00,0x1F,0xC0,0xB4,0x08,0x41,0xB0,0x0A,0x8A,0x5C,0x40,0xCA,0xD4,0xD4,
++    0xC8,0xBC,0xC0,0x80,0x80,0xAC,0x48,0x01,0x84,0xF6,0x49,0xBA,0xC2,0xD4,0xC0,0x08,
++    0x10,0x49,0xC5,0xD4,0x04,0x90,0xC4,0x18,0xE0,0xAC,0xC0,0x74,0x42,0x00,0x12,0x02,
++    0x90,0x05,0x82,0x54,0x30,0x01,0x00,0x7F,0x00,0x01,0x00,0x47,0x40,0x7C,0x40,0xD4,
++    0xD1,0xD0,0x05,0x14,0xE4,0x20,0xE5,0x48,0xE2,0xD8,0xE4,0x00,0x90,0x05,0xD6,0x7C,
++    0x17,0x82,0x9C,0x9E,0xE7,0xB0,0x93,0xB5,0xC4,0x84,0x10,0x32,0x9B,0x66,0x37,0x02,
++    0x40,0x01,0x80,0x06,0x3C,0x02,0x4C,0x2A,0xC2,0xD4,0xC0,0x18,0x48,0x1A,0xC4,0xD4,
++    0x8A,0xC1,0xC1,0x00,0x50,0x0A,0xCC,0xD4,0x94,0x81,0xC3,0x48,0x10,0x01,0x00,0x47,
++    0x40,0x24,0x40,0x74,0xD8,0x20,0x05,0xE4,0xE4,0xD8,0xE4,0x00,0xE2,0x48,0xE4,0x90,
++    0x90,0x95,0xE6,0x7C,0x17,0x12,0x9D,0x9E,0x48,0x92,0xC3,0xD4,0xC0,0x00,0x82,0x4C,
++    0xE0,0xAC,0x00,0x01,0x81,0x8C,0x30,0x42,0x80,0x01,0x81,0xA4,0x80,0x01,0x86,0x9C,
++    0x08,0x97,0x32,0x01,0x08,0x47,0xC2,0x4C,0xC4,0x03,0x48,0x00,0x89,0xF6,0xF3,0x02,
++    0xCC,0x74,0x10,0x42,0xD8,0xD6,0xC3,0x7C,0x32,0x5A,0x03,0x00,0xD0,0x08,0x31,0x52,
++    0xD6,0x01,0x59,0x94,0x10,0xD4,0x40,0x54,0x12,0xD4,0x42,0x4C,0x11,0xCC,0x34,0x0A,
++    0xCE,0x01,0x59,0x4C,0x11,0xCC,0x46,0x0C,0x1B,0xCC,0x40,0x0C,0x18,0xCC,0xCA,0x08,
++    0x31,0x52,0xD0,0x01,0x5C,0x94,0x1E,0xD4,0xD6,0x02,0x19,0xC4,0x40,0x44,0x22,0xC4,
++    0x40,0x25,0x70,0x01,0x88,0x26,0x08,0x01,0x16,0xCC,0x10,0xCC,0x18,0xCC,0x04,0x47,
++    0xCA,0x7C,0xF0,0x48,0x10,0x72,0x8C,0x26,0x0B,0x01,0x30,0x5A,0x12,0xCC,0x1C,0xCC,
++    0x20,0xCC,0xC8,0x8C,0x48,0x01,0x88,0x26,0x30,0x5A,0x13,0xCC,0x14,0xCC,0x12,0xCC,
++    0x00,0x4F,0xC8,0x84,0xD2,0x8C,0xF0,0x48,0x10,0x52,0x8C,0x26,0x0B,0x01,0x30,0x5A,
++    0x1E,0xCC,0x1C,0xCC,0x20,0xCC,0x10,0x01,0xF3,0x12,0x35,0x5A,0x0A,0x81,0xF0,0xCA,
++    0x11,0x8A,0xD4,0x9E,0x0A,0x91,0xF0,0xCA,0x17,0x8A,0xD4,0xD6,0x0A,0xA1,0xF0,0xCA,
++    0x17,0x8A,0xD4,0xB6,0x0A,0xB1,0xF0,0xCA,0x17,0x8A,0xD4,0x96,0x0A,0xD1,0xF0,0xCA,
++    0x11,0x8A,0xE4,0x1E,0x0A,0xE1,0xF0,0xCA,0x17,0x8A,0xE4,0xD6,0x0A,0xF1,0xF0,0xCA,
++    0x17,0x8A,0xE4,0xB6,0x0A,0x01,0xF1,0xCA,0x17,0x8A,0xE4,0x96,0x0A,0xD1,0xEC,0x4A,
++    0x4B,0x01,0x80,0xCE,0x08,0x01,0x88,0x6C,0x30,0x72,0x8C,0x1C,0x88,0x64,0xD8,0xBC,
++    0x5A,0x01,0x88,0x1E,0x32,0xE2,0xFC,0x78,0x1E,0x01,0xF0,0x1A,0x10,0xDA,0xD5,0x46,
++    0xC0,0xC8,0x92,0x4D,0xDA,0x1C,0xE0,0xD8,0x90,0xDD,0x06,0x07,0x00,0xF7,0x9D,0x1C,
++    0x00,0x2F,0x58,0x51,0xEB,0x1E,0x30,0x9A,0xE6,0xD8,0x92,0xDD,0x34,0xF2,0xE4,0x00,
++    0x32,0x1A,0xE3,0xD8,0x94,0xDD,0x36,0xE2,0x30,0x1A,0x5B,0x49,0x9A,0x26,0xC7,0x80,
++    0x90,0x05,0xD0,0xA4,0x70,0x4C,0xE9,0x93,0x10,0x8A,0x9C,0xB6,0xCC,0x5C,0x10,0x42,
++    0xD3,0x9E,0x30,0x8A,0x48,0x39,0x98,0x36,0xCA,0x5C,0x80,0x48,0x10,0x0A,0xDC,0x66,
++    0xC0,0x1C,0x40,0x01,0x88,0x4E,0xC0,0xB4,0xC8,0x03,0x46,0x11,0x98,0x0E,0x00,0x09,
++    0x80,0x6C,0x48,0xDA,0xC2,0x43,0xE2,0x00,0x80,0x43,0x4A,0xCA,0xC0,0x43,0x40,0x81,
++    0x90,0x26,0x52,0xC2,0xA2,0xB2,0xE0,0x00,0x81,0x43,0x00,0xFF,0x34,0xB2,0x84,0x98,
++    0xC0,0x98,0x96,0xDD,0x98,0x14,0x18,0x01,0x30,0xE2,0xDC,0x54,0x80,0xD8,0x9A,0x94,
++    0x1E,0x01,0xF0,0x1A,0xFD,0x94,0x10,0xDA,0xD3,0x56,0x30,0xBA,0xC9,0xF8,0x96,0xFD,
++    0x30,0xF2,0xFD,0x54,0x10,0xDA,0xD5,0x1E,0x86,0xB8,0xCA,0xB8,0x90,0xFD,0xB9,0x14,
++    0xC0,0xC8,0x02,0x97,0x60,0x20,0x02,0x00,0x70,0x32,0x06,0x00,0x70,0x32,0x04,0x00,
++    0x80,0x40,0x07,0x01,0x48,0xE0,0x06,0x00,0x28,0x60,0x00,0x00,0x68,0x70,0x04,0x00,
++    0x00,0xC0,0x00,0x01,0x80,0xC0,0x06,0x01,0x00,0xF7,0x90,0x4D,0xE3,0x00,0x34,0x1A,
++    0xE6,0xD8,0x92,0xDD,0x33,0xE2,0x34,0x1A,0x5E,0x49,0x98,0x8E,0xC4,0x14,0x10,0x0A,
++    0xD8,0x16,0xC8,0x5C,0x28,0x72,0xD4,0x0E,0x00,0x09,0x80,0x6C,0xC6,0xB4,0xC8,0x03,
++    0x40,0x51,0x98,0x16,0xC0,0xBC,0x40,0x01,0x80,0x46,0xC8,0x6C,0x00,0x09,0x48,0x01,
++    0x80,0x06,0x00,0x01,0x80,0x64,0x00,0x0F,0x00,0x09,0x80,0x64,0xC0,0x64,0x40,0x01,
++    0x80,0xA6,0x01,0x09,0xBC,0x43,0x43,0x3A,0x40,0x03,0x42,0x01,0x88,0x5E,0xC0,0xB4,
++    0xC8,0x03,0x46,0x51,0x90,0x3E,0xC0,0xA4,0x6E,0x4C,0xE7,0x03,0x32,0x00,0x72,0x00,
++    0x84,0x51,0x10,0x0A,0xC8,0x0E,0x10,0x01,0x00,0x07,0x10,0x09,0xC0,0xC4,0x40,0x01,
++    0x80,0x06,0x10,0x11,0xC0,0xD4,0x90,0x14,0x81,0x04,0x30,0x9A,0xA9,0x0C,0x30,0x02,
++    0xD0,0x8C,0xC8,0x4C,0xBA,0xFF,0xD7,0x37,0xC0,0x9C,0xC0,0x03,0x38,0x00,0xAA,0x1E,
++    0xFF,0x43,0xF9,0x4B,0x10,0x42,0x9C,0x4E,0xC0,0x9C,0xC0,0x03,0x38,0x00,0xA2,0x1E,
++    0x05,0x01,0xA8,0x43,0xCC,0x9C,0x80,0x43,0x87,0xDD,0xE8,0x85,0xE0,0x20,0xC5,0x4C,
++    0xE0,0x00,0x82,0x4C,0xE7,0xB0,0x93,0xB5,0xC4,0x7C,0x10,0x32,0x95,0x06,0x30,0x97,
++    0xC2,0x8C,0xE0,0x00,0x90,0x05,0x86,0x8C,0xC8,0x84,0xC0,0x8C,0x10,0x42,0x94,0x06,
++    0x37,0x3F,0x3D,0x4F,0xAC,0x9D,0x87,0x0D,0xD8,0x43,0x80,0x04,0xDB,0x63,0x52,0x12,
++    0xC4,0x0C,0xC0,0x28,0x50,0x02,0xC3,0x0C,0xD4,0xC1,0xC1,0x30,0xE8,0x43,0x0C,0xF1,
++    0x84,0x0F,0xD8,0x97,0x49,0xE9,0x88,0x0E,0x48,0xE2,0xC2,0x0C,0xC5,0x10,0x0A,0x49,
++    0xC4,0x0C,0x00,0x48,0xC0,0x08,0x1A,0x01,0x00,0x5F,0x00,0x01,0x00,0x2F,0x40,0x7C,
++    0x04,0xBC,0xE0,0x90,0xE2,0x48,0xE4,0x00,0x95,0x05,0x16,0x02,0x9A,0xBE,0xE7,0xD8,
++    0x90,0xDD,0xC6,0x04,0x17,0x1A,0x9C,0x86,0x00,0x01,0x00,0x2F,0x41,0x8C,0x01,0x4C,
++    0xE5,0x68,0xE5,0xB0,0xE6,0x00,0x92,0x05,0x17,0x02,0x9D,0xBE,0x48,0x62,0xC2,0x0C,
++    0xC0,0x00,0x12,0x01,0x00,0x67,0x08,0x01,0x00,0x37,0xC0,0x1B,0x34,0xD8,0x74,0xD8,
++    0x82,0x1B,0xE0,0x00,0xE6,0x48,0x92,0x4D,0x17,0x0A,0x9D,0xB6,0xE6,0x90,0x92,0x95,
++    0xCC,0x04,0x10,0x52,0x9F,0x7E,0xEF,0xF5,0xAC,0xFD,0x87,0x1D,0x30,0x6A,0x30,0x01,
++    0xBB,0x73,0xB9,0x73,0x37,0x42,0x81,0x01,0xC7,0x0B,0x10,0xE9,0x02,0x52,0x38,0x48,
++    0x7A,0x48,0x06,0x48,0x18,0x52,0x80,0x13,0xC7,0x0B,0x10,0xD9,0x00,0x8A,0x80,0x0B,
++    0x34,0x42,0x81,0x01,0x84,0x14,0xF0,0x03,0x78,0xB2,0x41,0x01,0x80,0x4E,0x00,0x01,
++    0x57,0xAA,0x09,0xF9,0xA2,0x8A,0xE0,0x00,0x90,0x05,0x46,0x81,0x99,0xD6,0x87,0xF3,
++    0x80,0xF3,0xAB,0x04,0x00,0x01,0xD8,0x1C,0xD0,0x34,0xC8,0x2C,0xBD,0xFF,0xEF,0xD7,
++    0x36,0x62,0xA1,0x01,0xC8,0x03,0x47,0x51,0x98,0x36,0xA8,0x04,0x00,0x09,0xD8,0x1C,
++    0xD0,0x34,0xC8,0x2C,0xBD,0xFF,0xEF,0x77,0xC4,0x14,0xF0,0x0B,0x49,0x01,0x80,0xD6,
++    0x00,0x01,0x48,0x09,0x8B,0x5E,0xC0,0xD3,0x50,0x01,0x80,0x46,0x50,0x1A,0xC1,0x93,
++    0x50,0x01,0x88,0x26,0x50,0x12,0xC1,0x93,0x50,0x01,0x88,0x06,0x00,0x09,0x40,0x01,
++    0x87,0x2E,0xC8,0x13,0x50,0x01,0x95,0x36,0xE7,0x90,0x8A,0x13,0x07,0x1F,0xC8,0x13,
++    0x50,0x51,0x90,0x06,0x8F,0x33,0xCF,0x13,0x50,0x51,0x98,0xE6,0x40,0x01,0x88,0x6E,
++    0x48,0x09,0x88,0x16,0xF7,0x90,0x8A,0x13,0x01,0x47,0x00,0x99,0xEF,0x02,0x6A,0x4C,
++    0x34,0x00,0x72,0x00,0x10,0x0A,0x94,0x0E,0xF7,0x90,0x8A,0x13,0xC0,0xC3,0x43,0x11,
++    0x9D,0x16,0x00,0x01,0x88,0x03,0x07,0x37,0x40,0x09,0x88,0x26,0xCA,0x03,0x47,0x81,
++    0x93,0x0E,0x00,0x21,0x89,0x03,0x37,0x4A,0xC7,0x1C,0xB8,0xFF,0xF8,0xDF,0x81,0x3D,
++    0xE8,0x85,0x07,0x00,0x80,0x40,0x07,0x01,0x68,0xF0,0x07,0x00,0x28,0x60,0x00,0x00,
++    0x60,0x20,0x02,0x00,0x00,0xC0,0x00,0x01,0x80,0xC0,0x06,0x01,0x00,0x40,0x00,0x01,
++    0x00,0x48,0x00,0x01,0xAC,0xFD,0x87,0x3D,0xE0,0x84,0x30,0xB2,0x00,0x01,0x80,0x2C,
++    0xD8,0x83,0x83,0x1C,0x60,0x8C,0x89,0x14,0xCA,0x44,0x18,0x0A,0x50,0xFA,0xC7,0x3C,
++    0xC0,0x00,0xC4,0x48,0x8F,0x34,0x40,0xF2,0xC0,0x03,0x40,0x09,0x89,0x0E,0xE0,0x83,
++    0x80,0x1C,0x00,0x01,0x10,0x01,0x00,0x1F,0x82,0x53,0xE0,0x48,0xE6,0x00,0x92,0x05,
++    0xDC,0x1C,0x10,0xC2,0x98,0xC6,0x0F,0x01,0x00,0x09,0xD8,0x54,0xD0,0x44,0x80,0x07,
++    0xD0,0xAF,0x2E,0x01,0x60,0x01,0x88,0x0E,0xE7,0x68,0x93,0x6D,0xF8,0x34,0x08,0x01,
++    0x01,0x5F,0xC0,0xC3,0x1E,0x02,0x91,0x05,0x80,0xC3,0xD1,0x8C,0x10,0x82,0xCC,0x0E,
++    0x19,0x02,0x85,0xC3,0xE2,0xF8,0xE3,0x48,0x90,0x4D,0xC6,0x1C,0x17,0x0A,0x9C,0x86,
++    0x48,0x42,0xC7,0x3C,0xC0,0x00,0x82,0x24,0xD0,0x54,0x90,0x04,0x30,0x9A,0x01,0x11,
++    0xD0,0x3C,0xC8,0x44,0x80,0x07,0xD8,0x47,0xD0,0x54,0x90,0x04,0x04,0x41,0xEA,0x0A,
++    0x00,0x01,0x1C,0x0A,0x30,0x9A,0x11,0x01,0xC0,0x24,0x80,0x07,0xF6,0x27,0x05,0x29,
++    0xE8,0x02,0x44,0x31,0x88,0x16,0x00,0x01,0x87,0x5D,0xE8,0x85,0xC1,0x1C,0xD0,0xC0,
++    0x09,0x01,0x00,0x3F,0xD0,0x24,0x18,0x01,0xF0,0x9A,0xD6,0x14,0xD0,0xD0,0x94,0x95,
++    0x68,0x01,0x88,0x2E,0x50,0xC1,0xE8,0xBE,0xC5,0x13,0x18,0x12,0x80,0x13,0x00,0x9F,
++    0x50,0x99,0xE8,0x2E,0xC0,0x13,0x50,0x01,0x82,0x16,0xF0,0x90,0x80,0x13,0x00,0x5F,
++    0x68,0x29,0x88,0x4E,0x58,0xE1,0xEE,0x3E,0xC0,0x13,0x50,0x01,0x88,0x26,0xD0,0x2C,
++    0x50,0x01,0x88,0x0E,0x10,0x09,0x90,0x2C,0xD4,0x24,0xE0,0x90,0x92,0x24,0xE0,0x00,
++    0xE6,0x48,0x92,0x4D,0xD4,0x1C,0x10,0x8A,0x9B,0xA6,0x46,0x20,0x6C,0x21,0xC8,0xCE,
++    0xD0,0x54,0x90,0x04,0x30,0x9A,0x09,0x01,0x00,0x19,0xD0,0x3C,0x85,0x07,0xD0,0xE7,
++    0x08,0x09,0x30,0x42,0xD8,0x54,0xD0,0x44,0x83,0x07,0xD0,0x07,0xC5,0x2C,0x38,0xDF,
++    0xAC,0xFD,0x87,0x1D,0xF0,0x64,0x30,0x7A,0x33,0xEA,0xD8,0xC3,0x85,0x14,0x48,0xAA,
++    0xC2,0x1C,0xC0,0x20,0x40,0x92,0xC5,0x03,0x40,0x09,0x88,0x0E,0xE0,0xC3,0x81,0x14,
++    0x08,0x01,0x00,0x09,0xD8,0x2C,0xD0,0x6C,0x82,0x07,0xD0,0x47,0xD0,0x2C,0x90,0x04,
++    0x30,0xDA,0x01,0x11,0xD0,0x1C,0xC8,0x6C,0x84,0x07,0xD0,0xB7,0xD0,0x2C,0x90,0x04,
++    0x06,0x41,0xEA,0x0A,0x00,0x01,0x1C,0x0A,0x30,0xDA,0x11,0x01,0x30,0x02,0x81,0x07,
++    0xF0,0x97,0xD1,0x2C,0x91,0x04,0x30,0xDA,0x08,0x01,0x00,0x19,0xD0,0x1C,0x80,0x07,
++    0xD0,0x1F,0x0C,0x09,0x30,0x42,0xD8,0x2C,0xD0,0x6C,0x80,0x07,0xD4,0x3F,0x41,0xF2,
++    0x00,0x44,0x01,0x01,0x00,0x84,0x09,0x01,0x00,0x77,0x00,0x01,0xF0,0x02,0x11,0x01,
++    0xF4,0x52,0x15,0x12,0xE9,0x06,0x00,0x44,0x15,0x01,0xF0,0x92,0x10,0x12,0xD4,0x06,
++    0x05,0x84,0xE1,0x20,0xE6,0x48,0x92,0x4D,0xC4,0x14,0x10,0x0A,0x98,0x6E,0x87,0x3D,
++    0xEF,0x85,0xAF,0xBD,0x80,0x55,0xC4,0x5C,0xD8,0x03,0x86,0x24,0xCA,0x5C,0xD8,0x4B,
++    0x8C,0x1C,0x50,0x52,0xCC,0x54,0xC0,0x48,0x8C,0x4C,0x48,0x4A,0xC0,0x4B,0x48,0x09,
++    0x88,0x46,0xC8,0x24,0xE6,0x48,0x92,0x4D,0x88,0x24,0x80,0x3C,0xC0,0x5C,0xE0,0x03,
++    0x80,0x1C,0x00,0x0F,0x00,0x01,0x80,0x3C,0xF8,0x3C,0xC0,0x5C,0x80,0x01,0x86,0x44,
++    0x04,0x7F,0x4B,0x12,0x04,0x01,0x00,0x43,0xC0,0x5C,0xC8,0x4C,0xDB,0x03,0x1A,0xC2,
++    0xC0,0x08,0x02,0x01,0x10,0xF9,0x01,0x1F,0x82,0x53,0xE0,0x48,0xE6,0x00,0x92,0x05,
++    0xDC,0x1C,0x10,0xC2,0x9C,0xC6,0x27,0x01,0x31,0x2A,0x31,0x32,0x03,0xE7,0x40,0xC2,
++    0x08,0x23,0x4E,0x2D,0xB8,0x0C,0x88,0x04,0x40,0x55,0x40,0x3E,0x5F,0x35,0xB8,0xFF,
++    0xF8,0x7F,0xC3,0x44,0xC8,0x03,0x42,0x31,0x83,0x7E,0x33,0x5A,0x00,0xC1,0xF0,0xC2,
++    0x40,0xE1,0xD1,0x1E,0x68,0x41,0x80,0x4E,0x18,0x62,0x05,0x1F,0x70,0x01,0x8C,0x0E,
++    0x30,0x72,0x01,0x1F,0x41,0x68,0x1B,0x62,0x6F,0x01,0x88,0x06,0xC0,0x5C,0xC8,0x4C,
++    0xDB,0x03,0x1A,0xC2,0xC0,0x08,0x02,0x01,0x10,0x01,0x00,0x1F,0x82,0x53,0xE0,0x48,
++    0xE6,0x00,0x92,0x05,0xDC,0x1C,0x10,0xC2,0x99,0xC6,0x37,0xAA,0x20,0x01,0x00,0x0F,
++    0x1B,0xA2,0x41,0xB0,0x77,0x01,0x88,0xDE,0xC0,0x5C,0x60,0x04,0xC0,0x41,0x91,0x35,
++    0x05,0xAF,0x18,0x62,0x46,0xD2,0x0A,0x23,0x48,0x2D,0xB8,0x0C,0x88,0x04,0x40,0x55,
++    0x40,0x3E,0x58,0x35,0xB9,0xFF,0xFF,0xA7,0xC2,0x44,0xC8,0x03,0x42,0x31,0x80,0x6E,
++    0x30,0x5A,0x03,0xA1,0xF5,0xC2,0x10,0x82,0xE9,0x06,0x18,0x62,0x40,0x68,0x6B,0x01,
++    0x88,0x3E,0xC7,0x54,0x0E,0x59,0xCB,0x00,0x0A,0x48,0xC2,0x00,0xB3,0x23,0xE0,0xF8,
++    0x90,0xFD,0xC7,0x24,0x14,0x3A,0x9C,0x66,0xF1,0x3C,0x00,0xA7,0xC3,0x54,0x08,0x59,
++    0xCA,0x00,0x0C,0x48,0xC1,0x38,0xF2,0xC3,0x40,0x01,0x88,0x0E,0x01,0x09,0xB0,0xC3,
++    0xF0,0xE3,0x29,0x01,0x01,0x01,0x00,0x0F,0xE7,0x68,0x93,0x6D,0x40,0x09,0x88,0x1E,
++    0x60,0xF9,0x97,0x0E,0xE5,0x20,0x93,0x25,0x48,0xE2,0x01,0x01,0x00,0x43,0xAC,0x48,
++    0x46,0xDA,0x09,0x23,0x20,0x00,0x67,0x10,0x00,0x0F,0x00,0xBF,0x40,0x48,0x32,0x82,
++    0x17,0x42,0x80,0xDE,0x48,0x01,0xC9,0x06,0x08,0x01,0x89,0x04,0x90,0x0C,0x40,0x55,
++    0x41,0x6E,0x30,0x8A,0xBA,0xFF,0xF7,0x77,0x40,0x01,0x80,0x0E,0x6E,0x29,0x98,0xDE,
++    0xB3,0xE3,0xE1,0xB0,0x90,0xB5,0xC7,0x24,0x16,0x32,0x9C,0x3E,0x87,0x6D,0xE8,0x85,
++    0xAC,0xBD,0x87,0x15,0x30,0x62,0x30,0xB2,0x48,0x2A,0x01,0x01,0x81,0x43,0x40,0x4A,
++    0x40,0x0B,0x10,0x11,0x18,0x8A,0x00,0x0B,0x28,0x01,0x00,0x3F,0x09,0x09,0x30,0x9A,
++    0x30,0x52,0x31,0x42,0x81,0x07,0xC8,0x57,0xE7,0x68,0x93,0x6D,0xDD,0x03,0x11,0x42,
++    0xC1,0xA6,0x37,0x12,0x30,0x8A,0x01,0x11,0x84,0x07,0xC0,0x2F,0x31,0x92,0x31,0x0A,
++    0xC7,0x14,0xB8,0xFF,0xF9,0x77,0x30,0x12,0x30,0x8A,0x01,0x01,0x83,0x07,0xC0,0xDF,
++    0xE0,0x03,0x41,0x01,0x80,0xBE,0x69,0xB2,0x44,0x43,0x97,0x3D,0x4F,0x04,0x01,0x43,
++    0x40,0x7A,0x08,0x09,0x81,0x0B,0x30,0x12,0x30,0x8A,0x01,0x11,0x83,0x07,0xC0,0x5F,
++    0x30,0x1A,0xB1,0x04,0x08,0x01,0x00,0x09,0xD0,0x14,0x80,0x07,0xC8,0xAF,0xB2,0x04,
++    0xD9,0x0B,0x37,0x1A,0x00,0x11,0xD0,0x14,0x82,0x07,0xC8,0x77,0x31,0x92,0x31,0x0A,
++    0xC7,0x14,0xB8,0xFF,0xF1,0x37,0x37,0x12,0x30,0x8A,0x01,0x6F,0x60,0x20,0x02,0x00,
++    0x00,0xD0,0x00,0x01,0x48,0xE0,0x06,0x00,0xF8,0xFB,0x07,0x00,0x10,0x00,0x00,0x42,
++    0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0x00,0x01,0x80,0x07,0xC0,0x27,0x42,0x5A,
++    0x08,0x01,0x80,0x0B,0x01,0x7B,0x37,0x1A,0xB0,0x04,0x08,0x01,0x00,0x11,0xD0,0x14,
++    0x81,0x07,0xC8,0x57,0x31,0x12,0x31,0x8A,0x00,0x11,0x80,0x07,0xC0,0xA7,0x51,0x22,
++    0x40,0x83,0x08,0x11,0x18,0x42,0x04,0x83,0x87,0x2D,0xE8,0x85,0x00,0xD0,0x00,0x01,
++    0x18,0x00,0x04,0x42,0xA8,0x85,0x31,0x12,0x92,0x01,0x46,0x8C,0x80,0x01,0xC7,0x1B,
++    0x32,0xD8,0x72,0xD8,0x87,0x1B,0x58,0xE2,0x41,0xE3,0x30,0x20,0xA2,0x16,0x40,0xE3,
++    0x3F,0x20,0xAB,0xE6,0x58,0xCA,0x27,0x41,0x00,0xE3,0x44,0xE3,0x28,0xF9,0xAF,0x19,
++    0x18,0x62,0x01,0xE3,0xC7,0x23,0x48,0x20,0x8A,0x1E,0xF0,0x48,0x20,0x48,0x60,0x48,
++    0x88,0xC6,0x4F,0x01,0x88,0x36,0x40,0xC3,0x08,0x81,0x18,0x42,0x07,0xC3,0x00,0xF9,
++    0x82,0x89,0x04,0x84,0xEF,0x85,0xA9,0x85,0x46,0x63,0x42,0x5B,0xDF,0xAB,0x72,0x62,
++    0xC0,0xB3,0x71,0x09,0x8E,0x16,0x48,0x63,0x50,0x5B,0xE2,0xAB,0x41,0x01,0x88,0x0E,
++    0x10,0x01,0x00,0xE7,0x40,0x03,0x31,0x32,0xB5,0x41,0x30,0xA2,0xE8,0x08,0x30,0x42,
++    0xC4,0x01,0x5A,0x33,0xC1,0xFB,0x18,0xF2,0x1E,0x33,0x5C,0x33,0xC5,0xFB,0x18,0xF2,
++    0x1B,0x33,0x36,0x32,0x40,0x83,0xC1,0xF3,0x1B,0x82,0x35,0x32,0x00,0x83,0x41,0x73,
++    0xC4,0xC3,0x18,0x32,0x01,0x73,0xE8,0x20,0xE2,0xD8,0xE2,0x90,0x95,0x95,0x16,0x52,
++    0x9F,0x06,0xEF,0x85,0x41,0x09,0x88,0x0E,0x10,0x01,0x00,0xE7,0x40,0x03,0x31,0x32,
++    0xB5,0x41,0x30,0xA2,0xE8,0x08,0x30,0x42,0xC4,0x01,0x5A,0x33,0xC5,0xFB,0x18,0xF2,
++    0x1E,0x33,0x5C,0x33,0xC5,0xFB,0x18,0xF2,0x1B,0x33,0x36,0x32,0x40,0x83,0xC1,0xF3,
++    0x1B,0x82,0x35,0x32,0x00,0x83,0x41,0x73,0xC0,0xC3,0x18,0x32,0x01,0x73,0xE8,0x20,
++    0xE2,0xD8,0xE2,0x90,0x95,0x95,0x16,0x52,0x9F,0x06,0xEF,0x85,0x41,0x11,0x88,0x0E,
++    0x10,0x01,0x00,0xE7,0x40,0x03,0x31,0x32,0xB5,0x41,0x30,0xA2,0xE8,0x08,0x30,0x42,
++    0xC4,0x01,0x5A,0x33,0xC5,0xFB,0x18,0xF2,0x1E,0x33,0x5C,0x33,0xC5,0xFB,0x18,0xF2,
++    0x1B,0x33,0x36,0x32,0x40,0x83,0xC1,0xF3,0x1B,0x82,0x31,0x32,0x00,0x83,0x41,0x73,
++    0xC4,0xC3,0x18,0x32,0x01,0x73,0xE8,0x20,0xE2,0xD8,0xE2,0x90,0x95,0x95,0x16,0x52,
++    0x9F,0x06,0xEF,0x85,0x47,0x19,0x88,0xE6,0x10,0x01,0x00,0xE7,0x40,0x03,0x31,0x32,
++    0xB5,0x41,0x30,0xA2,0xE8,0x08,0x30,0x42,0xC4,0x01,0x5A,0x33,0xC5,0xFB,0x18,0xF2,
++    0x1E,0x33,0x5C,0x33,0xC5,0xFB,0x18,0xF2,0x1B,0x33,0x36,0x32,0x40,0x83,0xC1,0xF3,
++    0x1B,0x82,0x31,0x32,0x00,0x83,0x41,0x73,0xC0,0xC3,0x18,0x32,0x01,0x73,0xE8,0x20,
++    0xE2,0xD8,0xE2,0x90,0x95,0x95,0x16,0x52,0x9F,0x06,0xEF,0x85,0xAA,0x85,0x47,0xE3,
++    0x05,0xB0,0xCC,0x20,0x45,0xEB,0xC6,0x68,0x40,0x09,0x88,0x26,0x45,0xE3,0xC8,0x20,
++    0x44,0xDB,0xC4,0xE8,0x04,0x3F,0x78,0xD2,0xC0,0xFB,0x79,0x09,0x8E,0x1E,0x48,0xE3,
++    0xCA,0x20,0x55,0xDB,0xC1,0xE8,0x44,0x13,0xF9,0xA0,0xC0,0x5B,0x40,0x09,0x88,0x76,
++    0x48,0x01,0x88,0x66,0x44,0x83,0x1A,0xC2,0x04,0x83,0x42,0x83,0x1C,0xC2,0x04,0x83,
++    0x44,0x03,0x19,0xC2,0x00,0x03,0x41,0x83,0x18,0xC2,0x00,0x83,0xE8,0x85,0x4F,0x09,
++    0x8A,0x66,0x40,0x83,0x1A,0xC2,0x04,0x83,0x44,0x83,0x1C,0xC2,0x00,0x83,0x44,0x83,
++    0x18,0xC2,0x04,0x83,0x40,0x03,0x19,0xC2,0x07,0x03,0xE9,0x85,0x48,0x11,0x88,0x66,
++    0x44,0x03,0x19,0xC2,0x00,0x03,0x41,0x83,0x18,0xC2,0x04,0x83,0x40,0x83,0x1A,0xC2,
++    0x04,0x83,0x42,0x83,0x1C,0xC2,0x04,0x83,0xE8,0x85,0x4F,0x19,0x89,0xE6,0x47,0x03,
++    0x19,0xC2,0x04,0x03,0x44,0x83,0x18,0xC2,0x02,0x83,0x40,0x83,0x1A,0xC2,0x04,0x83,
++    0x40,0x83,0x1C,0xC2,0x07,0x83,0xEC,0x85,0xA8,0xFD,0xF7,0x4C,0x30,0x62,0x2C,0x01,
++    0x4D,0x93,0x49,0x8B,0x32,0x72,0xDC,0xE3,0x33,0x3A,0x49,0x8A,0xC0,0x4B,0x48,0x09,
++    0x89,0x0E,0x50,0x93,0xE0,0xE3,0x40,0x19,0x80,0x96,0x31,0x79,0x49,0x5A,0x13,0xB0,
++    0x40,0x11,0x88,0xB6,0x32,0x02,0x1B,0x3A,0x58,0x52,0xC3,0x14,0xC1,0x00,0xC6,0xC0,
++    0x33,0x9A,0x33,0x2A,0xEA,0xDA,0x0A,0x5B,0x08,0x01,0x00,0x3F,0xC1,0x1B,0x18,0x9A,
++    0x41,0xAB,0x00,0x5B,0xEA,0x90,0xE0,0x00,0xE6,0x48,0x92,0x4D,0x17,0x0A,0x9D,0xAE,
++    0xE8,0xFD,0x47,0x01,0x88,0x8E,0x18,0x01,0x12,0x5B,0x46,0xDA,0x45,0x33,0x40,0xB0,
++    0x00,0xB0,0x05,0x33,0x00,0x1B,0x02,0x5B,0x40,0x0B,0x18,0x81,0x18,0xCA,0x04,0x0B,
++    0x44,0x0B,0x18,0x01,0x18,0xCA,0x00,0x0B,0x00,0x17,0x40,0x09,0x89,0x06,0x30,0xAA,
++    0x00,0x01,0x00,0x27,0x40,0x8B,0x00,0x6B,0xEA,0x90,0xE0,0x00,0x95,0x05,0x16,0x02,
++    0x9F,0xC6,0xEF,0xFD,0x3B,0x82,0xAB,0x85,0x4A,0xA3,0xD8,0xEB,0x33,0x70,0x72,0xB0,
++    0x48,0x5A,0xC2,0x4B,0x48,0x09,0x88,0x0E,0x50,0xA3,0xE0,0xEB,0x08,0x01,0x00,0x3F,
++    0x42,0x13,0x41,0x93,0x00,0x92,0x07,0x14,0xEC,0x20,0xE1,0x00,0xE6,0x48,0x92,0x4D,
++    0x17,0x4A,0x9D,0xAE,0xEB,0x85,0xAB,0xC5,0x30,0x2A,0x30,0xB2,0x61,0xF2,0x41,0x03,
++    0x14,0x01,0x1C,0x82,0x01,0x03,0x41,0x03,0x10,0x81,0x18,0x82,0x01,0x03,0x41,0x03,
++    0x10,0x09,0x18,0x82,0x07,0x03,0xE1,0x53,0x00,0xF9,0x87,0x81,0x19,0x12,0x40,0xBA,
++    0x10,0x13,0x16,0x99,0x00,0x13,0x13,0x41,0x04,0x13,0x14,0xD9,0xE8,0x92,0x52,0x01,
++    0x80,0x16,0x10,0xC9,0x00,0x13,0x00,0x0F,0x10,0x89,0x00,0x13,0x31,0x52,0x30,0x5A,
++    0x08,0x01,0x00,0x09,0xB7,0x04,0xB8,0xFF,0xF9,0x7F,0x33,0x52,0x30,0x8A,0x01,0x11,
++    0xBB,0xFF,0xF7,0xCF,0x42,0x03,0x3B,0x00,0xAB,0xE6,0xEF,0xC5,0xAC,0x9D,0x87,0x8D,
++    0xCA,0x94,0xC8,0x4B,0x88,0x84,0xE0,0x94,0xA7,0x01,0xD2,0x1B,0xD8,0x0B,0x89,0x04,
++    0xCA,0x94,0xD8,0x6B,0x30,0x0A,0x88,0x71,0x30,0x62,0xCC,0x94,0x30,0x01,0xE8,0x4B,
++    0x48,0x09,0x88,0x56,0x08,0x01,0x00,0x27,0xC5,0x38,0x9A,0xF3,0xA2,0x32,0xE2,0x48,
++    0x90,0x4D,0xD2,0x94,0xDC,0x93,0x12,0x52,0xE0,0xB6,0x57,0xDA,0x04,0xB3,0x02,0xB3,
++    0x00,0xB3,0x0E,0x01,0x18,0x4A,0x06,0x8B,0xCA,0x94,0xD8,0x4B,0xB0,0x8B,0x08,0x01,
++    0x50,0xAA,0x30,0x01,0x05,0x78,0xC4,0xF8,0x0A,0xF3,0xC1,0x90,0xB2,0xB3,0xE2,0x48,
++    0x90,0x4D,0x4A,0x11,0xD8,0xA6,0xCF,0x94,0xE8,0x4B,0x48,0x29,0xCD,0xF6,0x03,0x48,
++    0xC3,0x48,0x00,0x50,0xC0,0x70,0x54,0x6A,0xC0,0xB0,0xB5,0x14,0xC0,0x48,0x8C,0x0C,
++    0x30,0x12,0x33,0x32,0xB0,0xE1,0x08,0x01,0x88,0x34,0x48,0x4A,0x88,0x6C,0x88,0x64,
++    0x30,0x32,0x04,0x01,0x32,0x22,0x04,0x97,0x18,0x00,0x04,0x42,0x00,0x01,0x00,0x42,
++    0x00,0xD0,0x00,0x01,0x60,0x20,0x02,0x00,0x80,0x40,0x07,0x01,0x48,0xE0,0x06,0x00,
++    0x78,0xF8,0x07,0x00,0xC8,0x14,0x00,0x01,0xF0,0x42,0xF8,0x0C,0x0B,0x01,0xF0,0xCA,
++    0x32,0x7A,0xD0,0x08,0x97,0x4D,0x48,0xF9,0xEF,0x06,0x08,0xF9,0xCB,0x38,0x86,0xF8,
++    0x78,0xF9,0xEF,0x06,0x3B,0xF9,0x37,0x82,0x82,0x3B,0xE0,0x00,0x30,0x32,0xC4,0xBB,
++    0x10,0xFA,0x9C,0x46,0x10,0xCA,0xDC,0x36,0x46,0x84,0xD9,0x48,0xC0,0x00,0x92,0x05,
++    0x04,0x84,0x81,0x08,0x04,0x37,0x10,0xCA,0xDC,0x16,0x00,0x78,0x00,0xBC,0x01,0x0F,
++    0x39,0x01,0x00,0xBC,0x10,0xCA,0xDC,0x0E,0x38,0x09,0xB8,0x34,0x43,0x78,0x2B,0x3A,
++    0xE8,0x26,0xF8,0x6C,0x10,0x7A,0xEC,0x2E,0x88,0x6C,0x00,0x1F,0xFC,0x64,0x10,0x7A,
++    0xE8,0x06,0x88,0x64,0x82,0x8B,0xE0,0x90,0xE0,0xB0,0xC5,0x14,0xE0,0x00,0x84,0x14,
++    0xC4,0x0C,0xE0,0x00,0x83,0x0C,0x30,0x02,0xE2,0x00,0x92,0x05,0x35,0x22,0x2C,0x62,
++    0xD8,0xC6,0xC5,0x34,0x40,0x01,0x80,0x8E,0x08,0x01,0x00,0x01,0x80,0x5C,0xC0,0x04,
++    0xC2,0x00,0x46,0x00,0x80,0x7C,0xC0,0x04,0x30,0x00,0x72,0x00,0x80,0x74,0x00,0x01,
++    0x30,0x22,0x84,0x2C,0x80,0x24,0x80,0x1C,0xF0,0x90,0x02,0x07,0x03,0x1F,0xF5,0x40,
++    0x94,0x05,0x32,0x32,0x03,0xFF,0x31,0x02,0x04,0x00,0x32,0x22,0xC2,0x2C,0x00,0x00,
++    0x80,0x2C,0xC0,0x24,0x00,0x00,0x82,0x24,0xC2,0x1C,0x00,0x00,0x83,0x1C,0x40,0x40,
++    0x28,0x82,0xEB,0x26,0xC0,0x83,0xF0,0x6C,0xD8,0x00,0x84,0x83,0x00,0x1F,0xC0,0x83,
++    0xF4,0x64,0xD8,0x00,0x80,0x83,0xC0,0x83,0x73,0x3D,0x30,0xBA,0xA8,0x82,0xC7,0x83,
++    0x10,0xC2,0xDC,0xDE,0xE2,0x48,0x92,0x4D,0xF1,0x5C,0xC0,0xB0,0x90,0xB5,0xB1,0x5C,
++    0x30,0x32,0x3B,0x09,0x1D,0xF2,0x31,0xA2,0xF5,0x7C,0x10,0x82,0xD8,0x76,0xF0,0x2C,
++    0x18,0xF2,0xB1,0x2C,0xF5,0x04,0x10,0x82,0xD8,0x46,0xF0,0x24,0x18,0xF2,0xB1,0x24,
++    0xF5,0x74,0x10,0x82,0xD8,0x16,0xC0,0x1C,0x18,0xC2,0x81,0x1C,0xF3,0x90,0x32,0x82,
++    0xF2,0x00,0x92,0x05,0x33,0x32,0x34,0x82,0x45,0x01,0xD0,0xE6,0x42,0xE2,0xB7,0x0B,
++    0xD0,0x50,0xB3,0x13,0x36,0x12,0x1B,0x92,0x03,0x13,0x30,0x12,0x08,0x13,0xD0,0x2C,
++    0x00,0x13,0xD2,0x24,0x00,0x13,0xD4,0x1C,0x00,0x13,0x36,0x01,0x00,0xA7,0xC1,0x5C,
++    0x86,0x07,0xE8,0xA7,0x90,0x05,0x80,0x5C,0x4D,0x8A,0x07,0x80,0xC0,0x00,0x4A,0x13,
++    0x40,0x3D,0x08,0x01,0x1C,0x01,0x30,0xF2,0x30,0xE2,0x04,0xCF,0x38,0x98,0x86,0x7E,
++    0xC0,0x1B,0xF8,0x5C,0xD8,0xD8,0x96,0xDD,0x58,0x01,0xE8,0x36,0x83,0x1B,0x20,0x9A,
++    0x94,0xDD,0x36,0xF2,0xE2,0x48,0x92,0x4D,0x00,0x27,0x18,0x01,0x80,0x1B,0x00,0x0F,
++    0x18,0x01,0x80,0x1B,0x42,0x90,0xE2,0x00,0x32,0x1A,0xE3,0xD8,0x94,0xDD,0x32,0xE2,
++    0x2F,0x62,0xDD,0x1E,0xE3,0xB0,0x93,0xB5,0x30,0x82,0x83,0x5C,0x45,0xE2,0x06,0x98,
++    0xC0,0xD8,0x08,0xD3,0xCA,0x00,0xB4,0x0B,0x48,0x21,0xD8,0x0E,0x76,0x09,0xD8,0x36,
++    0x06,0x01,0x50,0xBA,0x04,0x08,0xC4,0x58,0xE4,0x08,0x02,0x70,0xC0,0xB0,0x4D,0xEB,
++    0x4D,0xB3,0x19,0xAA,0x08,0xEB,0xC0,0x80,0xF4,0x1B,0xF2,0x2B,0xDA,0xD8,0xB2,0x1B,
++    0x90,0x45,0x42,0x09,0xD8,0x76,0x07,0x09,0xA6,0x03,0x43,0x6A,0x0E,0x19,0x40,0x13,
++    0x50,0x01,0x80,0x16,0x03,0x29,0xA0,0x0B,0x04,0xF7,0x40,0x13,0x50,0x01,0x80,0x16,
++    0x03,0x21,0xA0,0x0B,0x02,0xC7,0x40,0x0B,0x48,0x01,0x80,0x1E,0x00,0x19,0x08,0x11,
++    0xA0,0x0B,0x03,0x8F,0x48,0x03,0x40,0x01,0x88,0x26,0xC0,0x94,0x86,0x01,0xCE,0x03,
++    0x40,0x51,0x98,0x0E,0x00,0x11,0x00,0x3F,0xC1,0x94,0x80,0x01,0xE0,0x03,0x44,0x01,
++    0x80,0x0E,0x00,0x11,0x00,0x07,0x00,0x09,0xE4,0x0B,0xE3,0x50,0xA3,0x13,0xDD,0x13,
++    0x38,0x90,0xA2,0x0E,0xF3,0x48,0xA2,0x0B,0xE8,0x0B,0x13,0x29,0x10,0x0A,0x94,0x0E,
++    0xA8,0x13,0x01,0xEF,0x10,0x0A,0xCC,0x46,0x40,0x09,0x88,0x16,0x09,0x81,0xAF,0x0B,
++    0x00,0xB7,0xD0,0x48,0x01,0x52,0xAC,0x13,0x00,0x97,0x40,0x19,0xC8,0x0E,0x08,0x19,
++    0x02,0x07,0x90,0x0D,0xE8,0x13,0x51,0x01,0x82,0x16,0xF0,0x90,0xA8,0x13,0x01,0x3F,
++    0xD2,0x94,0xF0,0x48,0xCA,0x93,0x1C,0x52,0xCA,0x84,0xC0,0x88,0xD0,0x94,0x88,0x8B,
++    0xA8,0x03,0x83,0x9D,0xEF,0x85,0xAF,0xBD,0x80,0x6D,0x34,0x6A,0xD9,0x63,0x33,0x42,
++    0x80,0x01,0x82,0x64,0xD0,0x03,0x84,0x3C,0xC2,0x64,0xD8,0x03,0x30,0x00,0xA8,0x1E,
++    0x02,0xD9,0xEC,0x02,0x40,0x01,0x80,0xA6,0xC5,0x6C,0x00,0x08,0xC3,0x40,0x00,0x08,
++    0x52,0xC2,0xC4,0x08,0xC4,0x48,0xC4,0x10,0x00,0x01,0x18,0x01,0x00,0x2F,0x00,0x5C,
++    0x04,0x9C,0xE0,0x48,0xE2,0x90,0xE4,0x00,0x95,0x05,0x12,0x02,0xD8,0xBE,0x87,0x85,
++    0xEB,0x85,0x07,0x59,0xCA,0x6C,0x08,0x00,0xC4,0x40,0x70,0x7A,0xF7,0x03,0x08,0x83,
++    0xD0,0x7C,0x90,0x04,0x30,0x5A,0x09,0x01,0x00,0x11,0xD0,0x6C,0xBB,0xFF,0xEF,0xE7,
++    0x42,0x4A,0x84,0x01,0x43,0x0B,0x30,0x5A,0x09,0xCC,0x5C,0x8B,0x0B,0xCC,0x5E,0x8B,
++    0x15,0xCC,0x58,0x8B,0x17,0xCC,0x42,0x8B,0x14,0xCC,0x4C,0x22,0x46,0x53,0x10,0xD4,
++    0x48,0x93,0x1F,0xD4,0x17,0x89,0x00,0x93,0x13,0x19,0x18,0x93,0x40,0x53,0x18,0x11,
++    0x18,0xD2,0x04,0x53,0x40,0x0B,0x18,0xCA,0x01,0x0B,0x30,0x42,0xE9,0x4B,0x81,0x01,
++    0x80,0x5C,0x48,0x09,0x8D,0x5E,0x6A,0x44,0x81,0x14,0x30,0x8A,0x5E,0x43,0x94,0x35,
++    0xB0,0x0C,0x00,0x01,0x80,0x04,0xD0,0x6C,0x4F,0x92,0x03,0x00,0xC2,0x00,0xC4,0x00,
++    0x83,0x54,0x40,0x8A,0x18,0x33,0x0A,0x01,0x37,0x42,0xB9,0xFF,0xE0,0x5F,0xF9,0x54,
++    0xC1,0x64,0x30,0x5A,0xD1,0x0B,0x32,0xC2,0xD7,0x7C,0xB8,0xFF,0xEB,0x67,0x4C,0x62,
++    0x10,0x01,0x00,0x01,0x02,0x67,0x00,0x18,0x37,0xE2,0xF4,0xDA,0x10,0x5A,0xD4,0x0E,
++    0x33,0x0A,0xD3,0xCA,0x10,0x9A,0xEC,0x0E,0x35,0x12,0xD3,0xD2,0xE2,0x00,0x92,0x05,
++    0x17,0x02,0xDD,0x86,0xC4,0x14,0xE0,0x00,0x10,0x0A,0x9C,0x36,0xC0,0x04,0x40,0x01,
++    0x8B,0x9E,0x40,0x80,0x40,0x08,0xC2,0x70,0x00,0x3F,0xC0,0x14,0xF4,0x00,0x14,0x12,
++    0xE0,0x5E,0x00,0x09,0x83,0x04,0xE0,0xB0,0x90,0xB5,0x77,0x01,0x80,0x16,0xC0,0x0C,
++    0x16,0x32,0x9C,0x36,0x70,0x01,0x88,0x06,0x30,0x09,0xC0,0x5C,0x90,0x33,0xC0,0x5C,
++    0xD2,0x0B,0x40,0x8A,0x18,0x0B,0x32,0x01,0x36,0x42,0x81,0x01,0x81,0x4C,0x80,0x01,
++    0x83,0x44,0x00,0x37,0xC4,0x3C,0x10,0x32,0xD0,0x6E,0xC0,0x44,0xC0,0x03,0xC8,0x44,
++    0x32,0x00,0x72,0x00,0x82,0x43,0x40,0x42,0x0C,0x41,0x00,0x0B,0x47,0x0B,0x10,0xF9,
++    0x90,0x21,0x18,0x8A,0x00,0x0B,0xC8,0x6C,0x02,0x00,0xC5,0x08,0x02,0x00,0x53,0x0A,
++    0xC4,0x40,0xC0,0x00,0xC0,0x48,0x74,0x01,0x88,0x66,0x10,0x01,0x78,0x02,0x02,0x37,
++    0x18,0x01,0x00,0x1C,0x04,0x7C,0xE0,0x00,0xE2,0x48,0xE4,0x90,0x95,0x95,0x12,0x12,
++    0xD9,0xB6,0x07,0x07,0xDF,0x6C,0x00,0x10,0xC1,0x90,0x5E,0xB2,0xC4,0x90,0x36,0xA2,
++    0x18,0x01,0x00,0x9F,0x30,0x3A,0x13,0x01,0xF0,0xD2,0x3D,0x01,0xFC,0x3A,0x16,0xBA,
++    0xD0,0x06,0x00,0x14,0x3E,0x01,0xF8,0x7A,0x10,0xBA,0xEC,0x06,0x04,0x54,0xE0,0x00,
++    0xE3,0x48,0x34,0x12,0xE4,0x90,0x34,0xA2,0xE2,0xD8,0x92,0xDD,0x17,0x1A,0xDD,0x4E,
++    0xC4,0x3C,0x10,0x32,0x80,0x06,0xC1,0x44,0xC6,0x03,0x48,0x00,0x88,0x1E,0xC0,0x4C,
++    0xC8,0x03,0x42,0x31,0x88,0xBE,0xC7,0x4C,0xC8,0x03,0x42,0x31,0x89,0x26,0x40,0x12,
++    0x40,0x0B,0x10,0x81,0x18,0x8A,0x00,0x0B,0xCF,0x6C,0x00,0x00,0xC0,0x00,0x4A,0xEA,
++    0xC0,0x00,0xCA,0x64,0x32,0x5A,0xD1,0x4B,0xD7,0x7C,0xB8,0xFF,0xE3,0x67,0xE7,0xB0,
++    0x90,0xB5,0xC3,0x3C,0x14,0x32,0xEC,0xAE,0x43,0xBA,0x30,0x5A,0x4A,0xCC,0x84,0x01,
++    0x00,0x0B,0x40,0xAA,0x48,0xCC,0x1E,0x0B,0x52,0xCC,0x18,0x0B,0x54,0xCC,0x1A,0x0B,
++    0x56,0xCC,0x04,0x0B,0x4E,0x8A,0x50,0xD4,0x00,0x53,0x58,0xCC,0x0F,0x0B,0x36,0xB7,
++    0xAA,0x85,0xD8,0xE3,0x1A,0x0A,0x03,0x48,0xC5,0x50,0x0C,0x49,0x02,0x48,0xC4,0x88,
++    0xE8,0xD3,0x50,0x11,0xC0,0x4E,0x10,0x01,0x00,0x2F,0x40,0x1C,0x04,0x5C,0xE0,0x48,
++    0xE2,0x00,0xE4,0x90,0x95,0x95,0x12,0x12,0xD8,0xBE,0x17,0x01,0x00,0x87,0x00,0x00,
++    0x80,0x40,0x07,0x01,0x48,0xE0,0x06,0x00,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,
++    0xF8,0xFB,0x07,0x00,0x40,0x1C,0x00,0x5C,0xE4,0x00,0xE4,0x48,0xE2,0x90,0x92,0x95,
++    0x17,0x12,0xDD,0xBE,0xEF,0x85,0xA8,0x85,0x30,0x6A,0xF0,0x2C,0x30,0x22,0x30,0x8A,
++    0x31,0xFA,0x30,0xC2,0xB9,0xFF,0xDF,0xB7,0x31,0xDA,0x31,0x92,0x31,0x4A,0x31,0x02,
++    0xBC,0xFF,0xE7,0xCF,0xE8,0x85,0x37,0x0A,0x8D,0x01,0x86,0x01,0x02,0x5F,0xC8,0x5B,
++    0x58,0x31,0x88,0x46,0x40,0xFA,0x47,0x0B,0x10,0x81,0x18,0x8A,0x00,0x0B,0x40,0x0B,
++    0x18,0x8A,0x00,0x0B,0x3E,0x82,0xCB,0x1B,0x5F,0x01,0x88,0x86,0x38,0x82,0xAB,0x85,
++    0xDA,0x5B,0xD8,0x4B,0x1F,0x5A,0x4A,0xC2,0xC7,0x08,0x52,0xC2,0xC0,0x00,0x14,0x01,
++    0x00,0x27,0x40,0x24,0x04,0x64,0xE0,0x00,0xE2,0x48,0xE4,0x90,0x17,0xD2,0x9C,0xC6,
++    0xEF,0x85,0xA8,0xBD,0x80,0x15,0x34,0x62,0x37,0xBA,0xD8,0x33,0xE8,0x03,0x09,0x01,
++    0x18,0x4A,0x2E,0x01,0x40,0x29,0x90,0x16,0x1F,0x0B,0x1D,0x2B,0x07,0x6F,0x00,0x09,
++    0xEA,0x02,0x38,0x00,0xAF,0x26,0x50,0x52,0x58,0x03,0x1F,0x82,0x18,0x03,0x05,0x27,
++    0x57,0x3A,0x5F,0x03,0x18,0x92,0x1E,0x82,0x1D,0x03,0x1D,0x0B,0x30,0x0A,0xC1,0x14,
++    0xBC,0xFF,0xE7,0xE7,0x25,0x2B,0x59,0x03,0x28,0x01,0x00,0x17,0x43,0x00,0xE2,0x68,
++    0x96,0x6D,0x3F,0x08,0x8D,0x0E,0x10,0xAA,0x9B,0xC6,0xAF,0x2B,0x73,0xCA,0x4E,0x04,
++    0x00,0x83,0xC7,0x14,0x0A,0x59,0xCB,0x00,0x0A,0x48,0xC2,0x00,0xF7,0x03,0x08,0x83,
++    0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,0xBC,0xFF,0xDF,0x87,0x30,0x1A,0xB9,0x04,
++    0x30,0x4A,0x01,0x11,0xD7,0x14,0xB8,0xFF,0xD8,0xFF,0x06,0x09,0xA7,0x01,0x8D,0x03,
++    0x48,0x82,0x46,0x43,0x10,0x11,0x18,0x82,0x00,0x43,0x00,0x41,0x01,0x83,0x45,0x83,
++    0x08,0xF9,0x8F,0x19,0x19,0x42,0x00,0x83,0x87,0x2D,0xE8,0x85,0x3F,0x82,0xAB,0xC5,
++    0xD8,0x53,0x90,0x04,0xDC,0x53,0x32,0xB2,0xE9,0x53,0x54,0x91,0x9E,0xBE,0x12,0x31,
++    0xE0,0x92,0x52,0x01,0x8E,0x9E,0x52,0x02,0xC0,0x28,0x34,0x12,0x91,0xE1,0x19,0xC1,
++    0x8E,0x01,0xF4,0x1A,0xE8,0x63,0x3A,0x11,0x10,0x1A,0xDD,0x16,0xD8,0xD8,0x38,0x1C,
++    0xA9,0x7B,0x1E,0xD1,0xEE,0x63,0xF4,0x1A,0x15,0x32,0x13,0x9A,0xE0,0x16,0xC8,0xD8,
++    0x38,0x1C,0xB2,0x7B,0x30,0x01,0x38,0x01,0x1C,0x01,0x30,0xE2,0x00,0x27,0x21,0x01,
++    0x00,0xE7,0x18,0x01,0xF0,0x5A,0x5F,0x01,0xED,0x4E,0x10,0x9A,0xE8,0x06,0x30,0xF2,
++    0xE8,0x5B,0x5E,0x01,0x80,0x76,0x40,0x9C,0xF0,0xD8,0x02,0x9C,0x00,0x57,0x58,0x01,
++    0xD5,0x46,0x10,0xDA,0xD0,0x06,0x30,0xFA,0xF0,0x5B,0x58,0x01,0x80,0x16,0x40,0x9C,
++    0xE0,0xD8,0x02,0x9C,0xE4,0x68,0xE5,0x90,0xE7,0x20,0x93,0x25,0x2F,0xA2,0x9B,0x06,
++    0x32,0x1A,0xE3,0xD8,0x94,0xDD,0x36,0xE2,0xE5,0x04,0x28,0x22,0x98,0xBE,0x7E,0x14,
++    0xC8,0x90,0x3C,0x14,0x7E,0x14,0xCA,0x90,0x3E,0x14,0xEA,0x43,0x40,0x01,0x80,0x0E,
++    0xF6,0x00,0xAA,0x43,0xF0,0x43,0x40,0x01,0x82,0x0E,0xF0,0x00,0xB7,0x43,0xE8,0xC5,
++    0xAC,0xBD,0x87,0x15,0x30,0x62,0x30,0xBA,0xEF,0x2B,0xDB,0x33,0xDB,0x03,0x1B,0x42,
++    0x00,0x08,0xC2,0x14,0xC4,0x40,0x48,0x8A,0xC0,0x00,0x82,0x0C,0x37,0x02,0x81,0x01,
++    0xC4,0x0B,0x10,0x01,0x18,0x8A,0x80,0x0B,0x00,0x21,0xEE,0x02,0x44,0x01,0x80,0x1E,
++    0x09,0x09,0x30,0xDA,0x30,0x52,0x31,0x42,0xBF,0xFF,0xD7,0xC7,0x30,0x1A,0xB9,0x04,
++    0x08,0x01,0x00,0x19,0xD7,0x14,0xB8,0xFF,0xDA,0x3F,0x02,0x41,0xE9,0x0A,0x30,0x1A,
++    0x30,0xD2,0xC1,0x0C,0xBC,0xFF,0xDF,0x7F,0x31,0x1A,0x31,0x4A,0xD0,0x14,0xC0,0x0C,
++    0xBD,0xFF,0xF7,0xB7,0x50,0x02,0x1C,0x09,0xC0,0x83,0x40,0x01,0x8B,0x5E,0xE0,0x68,
++    0x95,0x6D,0x5F,0x0B,0x03,0x0F,0xE0,0x68,0x90,0x6D,0x37,0xC2,0x00,0x42,0x15,0x0A,
++    0x8D,0x0E,0x10,0xAA,0x99,0xBE,0x37,0x82,0x74,0x92,0x13,0x2A,0x93,0xE6,0xA8,0x2B,
++    0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,0xBE,0xFF,0xD7,0x47,0x30,0x1A,0xB9,0x04,
++    0x30,0x4A,0x01,0x11,0xD7,0x14,0xB8,0xFF,0xD8,0xBF,0xC0,0x14,0x0A,0x59,0xCB,0x00,
++    0x0A,0x48,0xC2,0x00,0xF7,0x03,0x08,0x83,0x05,0x41,0x00,0x83,0x47,0x83,0x09,0xF9,
++    0x88,0x19,0x18,0x42,0x01,0x83,0x39,0xBF,0xE1,0x0B,0x31,0x02,0x80,0x01,0x4D,0x01,
++    0x86,0x1E,0xC9,0x0B,0x49,0x09,0x88,0x06,0x0E,0x11,0x88,0x0B,0xA8,0x2B,0x83,0x9B,
++    0x4F,0x04,0x01,0x83,0x50,0x0A,0xCB,0x14,0xDC,0x03,0xC1,0x48,0xE7,0x02,0x0A,0x83,
++    0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,0xBC,0xFF,0xD7,0xC7,0x30,0x1A,0xB9,0x04,
++    0x30,0x4A,0x01,0x11,0xD7,0x14,0xB8,0xFF,0xD0,0x3F,0x07,0x41,0x01,0x83,0x45,0x83,
++    0x08,0xF9,0x8F,0x19,0x19,0x42,0x00,0x83,0x38,0x77,0x08,0x01,0x88,0x0B,0x86,0x8B,
++    0x3F,0x57,0xA8,0x85,0x84,0x9D,0x34,0x22,0x33,0x6A,0xD8,0x73,0xD8,0x43,0x81,0x34,
++    0x31,0x12,0x93,0xE1,0x92,0x94,0x48,0x72,0x32,0x02,0xC3,0x18,0x4B,0x32,0x22,0x0A,
++    0x8B,0x8C,0xC8,0x43,0x00,0x00,0x82,0x1C,0x00,0x01,0x80,0x14,0x37,0x42,0x81,0x01,
++    0x82,0x84,0xC0,0x03,0x5C,0x7B,0x35,0x32,0x3F,0x20,0x5A,0x43,0x18,0x3A,0x60,0x01,
++    0xD1,0x46,0x40,0xFA,0x18,0x3A,0xB8,0x0C,0x37,0x82,0x23,0xD9,0x00,0x02,0xE1,0x84,
++    0x80,0x03,0x03,0x47,0x46,0xD2,0x19,0x02,0x18,0x3A,0xB8,0x0C,0x30,0x82,0x23,0x21,
++    0x18,0x02,0xE1,0x84,0x80,0x03,0x3B,0x01,0x19,0x7B,0x37,0x42,0x80,0x01,0x85,0x7C,
++    0xC0,0x03,0x84,0x54,0xC0,0x7C,0x20,0x09,0xB8,0x22,0xA0,0x4C,0x34,0x42,0x81,0x01,
++    0x86,0x74,0x18,0x3B,0xB8,0x44,0xC0,0x74,0x18,0x3B,0xBC,0x3C,0x31,0x42,0x81,0x01,
++    0x84,0x6C,0xA0,0x3B,0xCA,0x43,0x45,0x00,0x86,0x2C,0x00,0x01,0xFB,0x22,0x82,0x00,
++    0x81,0x24,0xE8,0x43,0x40,0x29,0xC0,0xBE,0x03,0x01,0x30,0x22,0x3B,0x04,0x39,0x04,
++    0x20,0x01,0x00,0x77,0x00,0x01,0x00,0x47,0x40,0x7C,0x00,0xFC,0x40,0x7C,0x00,0xBC,
++    0xE4,0x90,0xE4,0x48,0xE2,0xD8,0xE4,0x00,0x95,0x05,0x12,0x82,0xDB,0xA6,0xE7,0x20,
++    0x90,0x25,0xC3,0x34,0x17,0x22,0xDC,0x6E,0xF8,0x94,0xE0,0x8C,0x00,0x01,0x80,0x5C,
++    0x00,0xAF,0x05,0x01,0x34,0x32,0x34,0x22,0xC8,0x5C,0x00,0x09,0x00,0x42,0xCC,0x0C,
++    0x80,0x64,0x10,0x42,0x81,0x7E,0xE3,0x53,0x50,0x01,0x80,0x2E,0xC8,0x34,0xC0,0x5C,
++    0xF4,0x48,0x12,0x42,0x88,0x06,0x30,0xB2,0x1A,0x01,0x00,0x87,0x41,0xCC,0x41,0x14,
++    0xD0,0x40,0x94,0x15,0x00,0x14,0xC9,0x1C,0x10,0x52,0xD4,0x3E,0x32,0x02,0xE3,0x00,
++    0x94,0x05,0x36,0x22,0x34,0x82,0xC3,0x00,0x94,0x05,0x30,0x32,0xCC,0x2C,0x10,0x52,
++    0xE8,0x3E,0x01,0x7F,0x00,0x01,0x00,0x42,0x48,0xE0,0x06,0x00,0x38,0xA0,0x03,0x00,
++    0xAA,0xAA,0xAA,0xAA,0x18,0x00,0x04,0x42,0x00,0xD0,0x00,0x01,0x68,0xB8,0x03,0x00,
++    0x28,0x60,0x00,0x00,0xCC,0x4B,0x13,0x8A,0xE7,0x1E,0x58,0x43,0xC8,0x64,0x18,0x0A,
++    0x18,0x4B,0xCF,0x6C,0xE8,0x4B,0x4A,0x09,0x88,0x16,0xC8,0x6C,0x02,0x09,0xAC,0x43,
++    0xCC,0x54,0x10,0x52,0xE8,0xBE,0x08,0x09,0xD4,0x44,0x00,0xCA,0x18,0x8A,0x88,0x44,
++    0x00,0x8F,0xC8,0x24,0x10,0x52,0xD4,0x76,0xCA,0x6C,0xE8,0x4B,0x48,0x09,0x88,0x16,
++    0xCC,0x6C,0x00,0x09,0xA8,0x43,0xCA,0x4C,0x10,0x52,0xD4,0x26,0x08,0x09,0xD0,0x3C,
++    0x00,0xCA,0x1C,0x8A,0x8D,0x3C,0xE0,0x20,0xE2,0xF8,0xE5,0xD8,0x95,0xDD,0x12,0x9A,
++    0xD8,0x66,0xC5,0x7C,0xC8,0x03,0x44,0x01,0x83,0x2E,0x32,0x02,0x40,0x11,0xC8,0x2E,
++    0x33,0x0A,0x33,0x82,0x83,0x07,0xC8,0xD7,0x90,0x05,0x00,0x07,0x03,0x01,0x00,0x88,
++    0xD0,0x20,0x13,0x01,0x01,0x57,0x01,0x67,0x40,0x01,0xE8,0x7E,0x0B,0x01,0xF0,0x0A,
++    0xDC,0x1C,0x10,0xCA,0xD2,0xB6,0xE0,0x18,0x10,0xCA,0xEC,0x16,0xD1,0x48,0x00,0x0C,
++    0x00,0x87,0x48,0x01,0xE8,0x76,0x08,0x09,0x00,0x0C,0x01,0x5F,0x0B,0x01,0xF0,0x0A,
++    0x10,0x0A,0xD4,0x16,0xD1,0x48,0x00,0x0C,0x00,0x27,0x48,0x01,0xD0,0x16,0x08,0x01,
++    0x19,0x4A,0x06,0x0C,0x0B,0x01,0xF0,0x0A,0xDC,0x24,0x10,0xCA,0xD0,0x1E,0xC8,0x14,
++    0xE6,0x48,0x92,0x4D,0x8D,0x14,0xE0,0x20,0xE2,0x90,0x92,0x95,0x16,0x92,0xDD,0x9E,
++    0x00,0x4F,0x00,0x01,0x08,0x01,0x00,0x27,0x05,0x0C,0xE1,0x20,0xE2,0xF8,0xE5,0x00,
++    0x95,0x05,0x12,0x82,0xD8,0xC6,0xC7,0x5C,0xE2,0x00,0x92,0x05,0x80,0x5C,0xC8,0x34,
++    0xC4,0x5C,0x10,0x42,0xD2,0x06,0x38,0x27,0xC9,0x43,0x41,0x71,0xC9,0x0E,0x00,0x71,
++    0x88,0x43,0xC1,0x14,0xCC,0x4B,0x41,0x00,0xC6,0x40,0x90,0x05,0x8A,0x43,0x41,0x81,
++    0xCA,0x0E,0x00,0x81,0x88,0x43,0x01,0x01,0x29,0x44,0x37,0x44,0xC0,0x74,0xC8,0x44,
++    0x18,0x0B,0xCE,0x74,0xC4,0x3C,0x18,0x43,0x87,0x9D,0xE8,0x85,0xA8,0x85,0x33,0x2A,
++    0x30,0x62,0x30,0xB2,0x31,0x0A,0x31,0x42,0xBA,0xFF,0xEF,0xCF,0x48,0x6A,0x03,0x01,
++    0x81,0x43,0x30,0x92,0x31,0x0A,0x31,0x42,0xBB,0xFF,0xEF,0x1F,0xEE,0x03,0x41,0x41,
++    0x92,0x0E,0xE0,0x00,0xAB,0x03,0xE9,0x85,0x10,0x01,0x00,0x37,0x0A,0x01,0xE0,0x48,
++    0x90,0x4D,0x4C,0xA1,0xCA,0xDE,0xE7,0x90,0x94,0x95,0x14,0x12,0xCB,0xB6,0x3F,0x82,
++    0x38,0x18,0x78,0xD8,0x14,0x09,0x00,0xD2,0x97,0x95,0x1E,0xF9,0x08,0xD8,0x00,0xC2,
++    0x5E,0xEA,0xC2,0x00,0x48,0x09,0x88,0x66,0x44,0x0B,0x18,0x8A,0x02,0x0B,0x40,0x0B,
++    0x1A,0x8A,0x04,0x0B,0x44,0x0B,0x1C,0x8A,0x06,0x0B,0x44,0x0B,0x1E,0x8A,0x04,0x0B,
++    0x38,0x82,0x4B,0x01,0x8A,0x66,0x40,0x0B,0x1A,0x8A,0x04,0x0B,0x44,0x0B,0x1C,0x8A,
++    0x06,0x0B,0x44,0x0B,0x1E,0x8A,0x04,0x0B,0x40,0x0B,0x18,0x8A,0x03,0x0B,0x38,0x82,
++    0x48,0x11,0x88,0x66,0x44,0x0B,0x18,0x8A,0x02,0x0B,0x40,0x0B,0x1A,0x8A,0x04,0x0B,
++    0x44,0x0B,0x1C,0x8A,0x06,0x0B,0x44,0x0B,0x1E,0x8A,0x00,0x0B,0x38,0x82,0x4B,0x19,
++    0x88,0xE6,0x47,0x0B,0x18,0x8A,0x04,0x0B,0x44,0x0B,0x1C,0x8A,0x06,0x0B,0x44,0x0B,
++    0x1E,0x8A,0x04,0x0B,0x40,0x0B,0x1A,0x8A,0x03,0x0B,0x3A,0x82,0xAC,0x8D,0x87,0x3D,
++    0xC0,0x3C,0xC8,0x3C,0x4C,0x00,0x00,0x00,0xC0,0x00,0x3A,0x00,0x4A,0xDA,0x71,0x00,
++    0xC1,0x28,0x42,0xDA,0x44,0x0B,0x90,0x4D,0x88,0x34,0x58,0x0B,0x90,0x4D,0x8C,0x2C,
++    0x5C,0x0B,0x92,0x4D,0x8C,0x24,0x58,0x0B,0x90,0x4D,0x8C,0x1C,0x54,0x0B,0x96,0x75,
++    0x4A,0xA2,0x41,0x53,0x90,0x95,0x94,0x14,0x44,0x53,0x90,0xBD,0x44,0x13,0x92,0x95,
++    0x91,0x0C,0x58,0x7A,0x98,0x01,0x52,0xD3,0x90,0x95,0x94,0x04,0x10,0x09,0x00,0x13,
++    0xA8,0x10,0x1C,0x13,0x12,0x81,0x18,0x13,0x18,0x13,0x14,0x79,0x11,0x13,0x16,0x01,
++    0x00,0x53,0x12,0x89,0x02,0x53,0x40,0x0B,0x10,0x81,0x19,0x8A,0x07,0x0B,0x02,0xF9,
++    0x80,0x89,0x17,0xC3,0x07,0x09,0xB8,0xFF,0xFF,0x7F,0x03,0xF9,0x80,0x89,0x14,0xC3,
++    0x07,0x09,0xB8,0xFF,0xF8,0x4F,0x03,0x19,0x11,0x00,0x00,0x43,0x07,0x09,0xB8,0xFF,
++    0xF8,0x1F,0x0B,0x11,0xC7,0x3C,0xB8,0xFF,0xF8,0x5F,0x23,0xA1,0x01,0x01,0x40,0x4B,
++    0x30,0x48,0xA8,0x16,0xE7,0x20,0x93,0x25,0x03,0x0F,0xF0,0x20,0x92,0x25,0xE7,0x00,
++    0x90,0x05,0x46,0x51,0x98,0x9E,0x0F,0x09,0xC7,0x3C,0xB8,0xFF,0xF8,0xCF,0x42,0x82,
++    0xC8,0x34,0x00,0x0B,0xC8,0x2C,0x18,0x0B,0xCA,0x24,0x18,0x0B,0xCC,0x1C,0x18,0x0B,
++    0x10,0x33,0x4E,0x62,0xD2,0x14,0x00,0x53,0x00,0x7B,0xC8,0x0C,0x00,0x0B,0x4A,0x42,
++    0xC2,0x04,0x88,0x01,0x10,0x43,0x60,0xA1,0xC8,0x16,0x00,0x09,0x87,0x45,0xE8,0x85,
++    0x07,0x01,0x38,0xDF,0x00,0xD0,0x00,0x01,0x80,0x00,0x00,0x42,0x08,0x01,0x00,0x42,
++    0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0x00,0x0F,0x00,0x26,0xF8,0x48,0x48,0x21,
++    0x94,0xDE,0x3F,0x58,0xA8,0x0E,0x00,0x14,0xE6,0x00,0x3C,0x48,0x80,0x06,0x80,0x13,
++    0x38,0x82,0x4B,0x01,0x86,0x5E,0x38,0x18,0x80,0x16,0x80,0x13,0xE2,0x00,0xF2,0x48,
++    0x48,0x11,0x98,0x26,0x38,0x18,0xAC,0x16,0x04,0x14,0xE0,0x00,0xF7,0x48,0x3C,0x1F,
++    0x17,0x01,0x38,0x77,0x16,0x01,0x38,0xFF,0x10,0x01,0x48,0x18,0x11,0x5A,0x9C,0x66,
++    0x54,0x18,0x10,0x5A,0x98,0x8E,0x18,0x01,0x32,0xE2,0x04,0x77,0x30,0x1A,0x18,0x5A,
++    0xA0,0xE6,0x11,0x01,0x44,0x18,0x12,0x5A,0x98,0x8E,0x49,0x18,0x10,0x5A,0x9C,0xE6,
++    0x54,0x18,0x10,0x5A,0x9C,0x0E,0x30,0xA2,0x06,0xFF,0x49,0x18,0x10,0x5A,0x9C,0x0E,
++    0x0E,0x58,0xD6,0x00,0x0C,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD4,0x00,
++    0x0A,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD2,0x00,0x08,0x92,0x4A,0x18,
++    0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD0,0x00,0x0E,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,
++    0x06,0x58,0xD6,0x00,0x0C,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD4,0x00,
++    0x0A,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD2,0x00,0x0A,0x92,0xD2,0x08,
++    0x90,0x06,0x30,0x0A,0x08,0x92,0x32,0x82,0x3A,0x82,0x03,0xEF,0x78,0x50,0x86,0x06,
++    0x10,0x4A,0x82,0x18,0x9A,0x06,0x10,0x02,0x00,0x9A,0x12,0x01,0x30,0xE2,0x4C,0x18,
++    0x11,0x5A,0x9C,0x6E,0x54,0x18,0x10,0x5A,0x9F,0x96,0x10,0xE1,0x08,0x48,0xD4,0x95,
++    0x54,0x18,0x10,0x5A,0x9C,0x66,0x08,0x48,0x8C,0x90,0x14,0x5A,0x9C,0x46,0x08,0x48,
++    0x8C,0x90,0x14,0x5A,0x9C,0x26,0x08,0x48,0x84,0xD6,0x89,0x90,0x04,0x07,0x48,0x48,
++    0x4C,0x18,0x16,0x5A,0x9E,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,0x4C,0x18,0x14,0x5A,
++    0x9C,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,0x4C,0x18,0x12,0x5A,0x9A,0x0E,0x08,0x58,
++    0xD2,0x00,0x0E,0x92,0x4C,0x18,0x10,0x5A,0x98,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,
++    0x44,0x18,0x16,0x5A,0x9E,0x0E,0x00,0x58,0xD2,0x00,0x0E,0x92,0x44,0x18,0x14,0x5A,
++    0x9C,0x0E,0x00,0x58,0xD2,0x00,0x0E,0x92,0x92,0xCE,0x46,0x18,0x10,0x5A,0x9C,0x0E,
++    0x06,0x58,0xD2,0x00,0x0A,0x92,0xD2,0x08,0x90,0x06,0x30,0x0A,0x32,0x1A,0x0B,0x92,
++    0x80,0xD8,0x32,0x82,0x9A,0x0E,0x10,0x02,0x58,0x01,0xA8,0x06,0x13,0x4A,0x3A,0x82,
++    0x32,0x1A,0x83,0xD8,0x9A,0x06,0x10,0x02,0xA8,0x0D,0x00,0x01,0x36,0x02,0x36,0x02,
++    0xEB,0x15,0x30,0xAA,0x81,0x07,0xC0,0x17,0x30,0x72,0x05,0x28,0x32,0x4A,0x33,0x9A,
++    0x46,0x00,0x06,0x00,0x30,0x2A,0x84,0xC5,0xAF,0x05,0xB9,0xE7,0xF3,0x6F,0xE4,0x05,
++    0x3A,0x01,0x40,0x48,0x30,0xB2,0x35,0x01,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,
++    0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0xEA,0x01,0x02,0x48,0x33,0x6A,0x3C,0x82,
++    0x36,0x22,0x30,0x02,0x31,0x02,0x36,0x02,0xBA,0xDF,0xD7,0x2F,0x43,0x02,0x38,0x82,
++    0x88,0x20,0x00,0x01,0x40,0x12,0x48,0x1A,0xF3,0x5D,0x3D,0x82,0x00,0x68,0x00,0x00,
++    0x00,0xC0,0x00,0x00,0x00,0x30,0x01,0x10,0x39,0x82,0xA3,0x85,0x33,0xA2,0xF3,0x20,
++    0xC3,0x2B,0xE1,0x20,0x10,0x5A,0x95,0x06,0x33,0xEA,0xE8,0x1A,0x07,0xD8,0xC2,0x18,
++    0xE0,0x85,0x39,0xC2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x80,0x20,0x03,0x42,0x80,0x20,0x03,0x42,0x80,0x20,0x04,0x42,0x80,0x20,0x03,0x42,
++    0x80,0xA0,0x04,0x42,0x80,0xA0,0x02,0x42,0x80,0xA0,0x04,0x42,0x80,0xA0,0x02,0x42,
++    0x80,0xA0,0x04,0x42,0x80,0xA0,0x02,0x42,0x80,0x20,0x05,0x42,0x80,0xA0,0x02,0x42,
++    0x80,0xA0,0x05,0x42,0x80,0x20,0x02,0x42,0x80,0x20,0x01,0x42,0x80,0x20,0x01,0x42,
++    0x80,0xA0,0x01,0x42,0x80,0xA0,0x01,0x42,0x80,0xA0,0x01,0x42,0x10,0x20,0x08,0x40,
++    0x40,0x08,0x20,0x10,0x10,0x20,0x08,0x40,0x40,0x08,0x20,0x40,0x10,0x20,0x00,0x08,
++    0x08,0xC1,0x02,0x42,0x08,0x81,0x02,0x42,0x08,0x81,0x03,0x42,0x08,0x41,0x03,0x42,
++    0x08,0x01,0x03,0x42,0x08,0x81,0x02,0x42,0x08,0x41,0x02,0x42,0x08,0xC1,0x00,0x42,
++    0x08,0x01,0x02,0x42,0x08,0x01,0x01,0x42,0x08,0xC1,0x01,0x42,0x08,0x41,0x01,0x42,
++    0x08,0x81,0x01,0x42,0x08,0x81,0x01,0x42,0x08,0x41,0x01,0x42,0x08,0xC1,0x02,0x42,
++    0x08,0x01,0x01,0x42,0x08,0x01,0x03,0x42,0x08,0xC1,0x00,0x42,0x50,0x50,0x50,0x50,
++    0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x00,0x00,0x00,0x08,0xF8,0x0F,
++    0xFF,0x07,0xF8,0xFF,0x07,0xF8,0x0F,0xF8,0x08,0x00,0x08,0x08,0x00,0x00,0x00,0x08,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x28,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x03,0x00,0x28,0xB5,0x39,0xC5,0x08,0x1D,0x1B,0x2B,0x3A,0x28,
++    0x53,0xB5,0x0A,0xC5,0x00,0x08,0x01,0x00,0x01,0x00,0x50,0x0D,0x52,0x1D,0x52,0xB5,
++    0x39,0x0D,0x04,0x08,0x51,0x3D,0x53,0x1D,0x51,0x3D,0x54,0x95,0x51,0x3D,0x54,0x95,
++    0x51,0x3D,0x54,0x95,0x0B,0x3D,0x34,0x88,0x51,0x3D,0x54,0x1D,0x51,0x3D,0x54,0x95,
++    0x04,0x00,0x50,0x3D,0x50,0x1D,0x01,0x00,0x00,0x00,0x00,0x00,0x54,0x2D,0x53,0x3D,
++    0x32,0x8D,0x32,0x38,0x01,0x28,0x0A,0x45,0x50,0xB5,0x53,0x95,0x00,0x00,0x00,0x00,
++    0x52,0xA5,0x51,0xB5,0x09,0xC5,0x03,0x08,0x03,0x00,0x50,0x3D,0x55,0x1D,0x51,0x0D,
++    0x51,0x3D,0x54,0x95,0x51,0x3D,0x53,0x1D,0x51,0x3D,0x54,0x95,0x51,0x0D,0x55,0x0D,
++    0x54,0xB5,0x3A,0x0D,0x00,0x08,0x01,0x00,0x53,0xA5,0x51,0x2D,0x52,0x3D,0x34,0x8A,
++    0x1D,0x38,0x52,0x45,0x52,0x0D,0x51,0x1D,0x54,0xB5,0x3A,0x0D,0x53,0xA5,0x29,0xB5,
++    0x39,0xC5,0x08,0x1D,0x19,0x2D,0x22,0x1D,0x44,0x0D,0x31,0x3D,0x23,0x95,0x09,0xC1,
++    0x29,0xB5,0x0B,0x1D,0x1B,0x2B,0x3A,0x28,0x00,0x00,0x00,0x08,0xFF,0x07,0x00,0xF8,
++    0x08,0x00,0x10,0x10,0x08,0x10,0x10,0x10,0x08,0x08,0x10,0x08,0x10,0x08,0x10,0x08,
++    0x10,0x10,0x08,0x08,0x10,0x10,0x08,0x08,0x08,0x08,0x10,0x10,0x10,0x10,0x10,0x10,
++    0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x08,0xF8,0x07,0x08,0x00,
++    0x08,0x08,0x00,0x00,0x78,0xA2,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0xE0,0x00,0x00,
++    0x00,0x00,0x05,0x00,0x78,0x82,0x01,0x00,0x00,0xE0,0x00,0x01,0x88,0x40,0x02,0x00,
++    0x00,0xE0,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xD1,0xDA,0xAA,0xA9,0x2E,0x2D,0x55,0x56,0xBB,0x43,0xAC,0x32,
++    0x99,0x21,0x8A,0x10,0x00,0x70,0x00,0x28,0x09,0x00,0x1F,0x00,0x06,0x78,0x50,0x56,
++    0xFF,0xFF,0xFF,0xFF,0xBA,0xB0,0x09,0x40,0x00,0x40,0x28,0x00,0x0B,0x1C,0x29,0xF0,
++    0x0F,0x00,0xCA,0xCA,0xFF,0xFF,0xFF,0xFF,0x36,0x17,0x48,0x01,0x08,0x00,0x00,0x05,
++    0x23,0x81,0x7E,0x05,0x5F,0x0D,0x69,0x30
++};
++
++
++#define FW_INFO_SIZE	(0x18)
++#define FW_REAL_SIZE	(sizeof(fwbin))
++#define FW_BIN_SIZE		(24*1024+24)	    //24K byte
++
++#endif
++
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/Readme b/module_drivers/drivers/input/touchscreen/hyn_touch/Readme
+new file mode 100644
+index 000000000..262f3cad4
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/Readme
+@@ -0,0 +1,6 @@
++1.Original_driver：
++	Provided by the original factory.
++2.Debug_driver:
++	Reference Original_driver to match out platform.
++
++3.Def driver------>Original_driver/cst3xx_MCU_driver-ori [Version 1]
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/hyn_cst3xx.c b/module_drivers/drivers/input/touchscreen/hyn_touch/hyn_cst3xx.c
+new file mode 100755
+index 000000000..b917cdd0d
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/hyn_cst3xx.c
+@@ -0,0 +1,1645 @@
++/*
++ * cst3xx Touchscreen Controller Driver
++ */
++
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/i2c.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of_gpio.h>
++#include <linux/pm_qos.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include "hyn_cst3xx.h"
++#include "hyn_cst3xx_RS659_fw.h"
++#include <soc/gpio.h>
++
++
++#define HYN_DEBUG_EN  1
++
++struct st1615_ts_finger {
++	u16 x;
++	u16 y;
++	u8 t;
++	bool is_valid;
++};
++
++
++static int cst3xx_into_program_mode(struct i2c_client * client);
++static int cst3xx_erase_program_area(struct i2c_client * client);
++static void cst3xx_reset_ic(struct cst3xx_ts_data *ts,unsigned int ms);
++static int cst3xx_write_program_data(struct i2c_client * client,const unsigned char *pdata);
++
++static int cst3xx_check_checksum(struct i2c_client * client);
++
++static int cst3xx_exit_program_mode(struct i2c_client * client);
++
++static int cst3xx_update_firmware(struct cst3xx_ts_data *ts, const unsigned char *pdata);
++
++static int cst3xx_firmware_info(struct i2c_client * client);
++
++static int cst3xx_update_judge( unsigned char *pdata, int strict);
++
++static int cst3xx_boot_update_fw(struct cst3xx_ts_data *ts,  unsigned char *pdata);
++
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len);
++static int cst3xx_i2c_test(struct i2c_client *client);
++static void cst3xx_reset(struct cst3xx_ts_data *ts) ;
++extern  void close_vcc3v3Power(void);
++extern  void open_vcc3v3Power(void);
++
++static unsigned char *pcst3xx_update_firmware = (unsigned char *)cst3_fw ; //the updating firmware
++static unsigned int   g_cst3xx_ic_version  = 0;
++static unsigned int   g_cst3xx_ic_checksum = 0;
++static unsigned int   g_cst3xx_ic_checkcode =0;
++static unsigned int   g_cst3xx_ic_project_id  = 0;
++static unsigned int   g_cst3xx_ic_type  = 0;
++
++static unsigned char  report_flag = 0;
++static unsigned int x_temp_pos = 0;
++static unsigned int y_temp_pos = 0;
++
++#define HYN_DRAW_POINT
++
++//#define USE_ANALOG_I2C     1 //i2c analog -->defconfig i2c.
++//#define USE_HIGHEST_I2CA  1// x1000 highest i2c
++#define USE_LOWEST_I2CA   1 // x1000 lowest i2c
++//#define HYN_UPDATE_FIRMWARE_POWERON_ENABLE
++#define HYN_UPDATE_FIRMWARE_ENABLE
++
++#pragma pack(1)
++typedef struct
++{
++    u16 pid;                 //product id   //
++    u16 vid;                 //version id   //
++} st_tpd_info;
++#pragma pack()
++
++st_tpd_info tpd_info;
++
++#define CST3XX_BIN_SIZE    (24*1024 + 24)
++//#define CST3XX_MAX_X  340
++#define CST3XX_MAX_X  480
++#define CST3XX_REL_X  268
++#define CST3XX_MAX_Y  800
++#define ERROR_TOUCH   1
++
++static void cst3xx_ts_power(struct cst3xx_ts_data *ts, bool poweron)
++{
++	if (gpio_is_valid(ts->pdata->reset_gpio))
++		gpio_direction_output(ts->pdata->reset_gpio, poweron);
++}
++
++static int cst3xx_into_program_mode(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[4];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x01;
++	buf[2] = 0xAA;	//set cmd to enter program mode
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0)  return -1;
++
++	mdelay(2);
++
++	buf[0] = 0xA0;
++	buf[1] = 0x02;	//check whether into program mode
++	ret = cst3xx_i2c_read_register(client, buf, 1);
++	if (ret < 0)  return -1;
++
++	if (buf[0] != 0x55) return -1;
++
++	return 0;
++}
++static int cst3xx_erase_program_area(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[3];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x02;
++	buf[2] = 0x00;		//set cmd to erase main area
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0) return -1;
++
++	mdelay(5);
++
++	buf[0] = 0xA0;
++	buf[1] = 0x03;
++	ret = cst3xx_i2c_read_register(client, buf, 1);
++	if (ret < 0)  return -1;
++
++	if (buf[0] != 0x55) return -1;
++
++	return 0;
++}
++
++
++static void cst3xx_reset_ic(struct cst3xx_ts_data *ts,unsigned int ms)
++{
++
++	unsigned char buf[4];
++	buf[0] = 0xD1;
++	buf[1] = 0x0E;
++	cst3xx_i2c_write(ts->client, buf, 2);
++/*
++	gpio_direction_output(ts->pdata->reset_gpio,0);
++	mdelay(2);
++	gpio_direction_output(ts->pdata->reset_gpio,1);
++*/
++	mdelay(ms);
++}
++
++
++static int cst3xx_write_program_data(struct i2c_client * client,
++		const unsigned char *pdata)
++{
++	int i, ret;
++	unsigned char *i2c_buf;
++	unsigned short eep_addr;
++	int total_kbyte;
++
++	unsigned char temp_buf[8];
++	unsigned short iic_addr;
++	int  j;
++
++
++	i2c_buf = kmalloc(sizeof(unsigned char)*(1024 + 2), GFP_KERNEL);
++	if (i2c_buf == NULL)
++		return -1;
++
++	//make sure fwbin len is N*1K
++	//total_kbyte = len / 1024;
++	total_kbyte = 24;
++	for (i=0; i<total_kbyte; i++) {
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x14;
++		eep_addr = i << 10;		//i * 1024
++		i2c_buf[2] = eep_addr;
++		i2c_buf[3] = eep_addr>>8;
++		ret = cst3xx_i2c_write(client, i2c_buf, 4);
++		if (ret < 0)
++			goto error_out;
++
++		memcpy(i2c_buf, pdata + eep_addr, 1024);
++		for(j=0; j<256; j++) {
++			iic_addr = (j<<2);
++    	temp_buf[0] = (iic_addr+0xA018)>>8;
++    	temp_buf[1] = (iic_addr+0xA018)&0xFF;
++		temp_buf[2] = i2c_buf[iic_addr+0];
++		temp_buf[3] = i2c_buf[iic_addr+1];
++		temp_buf[4] = i2c_buf[iic_addr+2];
++		temp_buf[5] = i2c_buf[iic_addr+3];
++    	      ret = cst3xx_i2c_write(client, temp_buf, 6);
++    		if (ret < 0)
++    			goto error_out;
++		}
++
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x04;
++		i2c_buf[2] = 0xEE;
++		ret = cst3xx_i2c_write(client, i2c_buf, 3);
++		if (ret < 0)
++			goto error_out;
++
++		mdelay(60);
++
++		i2c_buf[0] = 0xA0;
++		i2c_buf[1] = 0x05;
++		ret = cst3xx_i2c_read_register(client, i2c_buf, 1);
++		if (ret < 0)
++			goto error_out;
++
++		if (i2c_buf[0] != 0x55)
++			goto error_out;
++
++	}
++
++	i2c_buf[0] = 0xA0;
++	i2c_buf[1] = 0x03;
++	i2c_buf[2] = 0x00;
++	ret = cst3xx_i2c_write(client, i2c_buf, 3);
++	if (ret < 0)
++		goto error_out;
++
++	mdelay(8);
++
++	if (i2c_buf != NULL) {
++		kfree(i2c_buf);
++		i2c_buf = NULL;
++	}
++
++	return 0;
++
++error_out:
++	if (i2c_buf != NULL) {
++		kfree(i2c_buf);
++		i2c_buf = NULL;
++	}
++	return -1;
++}
++
++
++static int cst3xx_check_checksum(struct i2c_client * client)
++{
++	int ret;
++	int i;
++	unsigned int  checksum;
++	unsigned int  bin_checksum;
++	unsigned char buf[4];
++	const unsigned char *pData;
++
++	for(i=0; i<5; i++)
++	{
++		buf[0] = 0xA0;
++		buf[1] = 0x00;
++		ret = cst3xx_i2c_read_register(client, buf, 1);
++		if(ret < 0)
++		{
++			mdelay(2);
++			continue;
++		}
++
++		if(buf[0]!=0)
++			break;
++		else
++		mdelay(2);
++	}
++    mdelay(2);
++
++
++    if(buf[0]==0x01)
++	{
++		buf[0] = 0xA0;
++		buf[1] = 0x08;
++		ret = cst3xx_i2c_read_register(client, buf, 4);
++
++		if(ret < 0)	return -1;
++
++		// read chip checksum
++		checksum = buf[0] + (buf[1]<<8) + (buf[2]<<16) + (buf[3]<<24);
++
++        pData=(unsigned char  *)pcst3xx_update_firmware +24*1024+16;   //7*1024 +512
++		bin_checksum = pData[0] + (pData[1]<<8) + (pData[2]<<16) + (pData[3]<<24);
++
++        printk("  hyn the updated ic checksum is :0x%x. the updating firmware checksum is:0x%x------\n", checksum, bin_checksum);
++
++        if(checksum!=bin_checksum)
++		{
++			printk(" cst3xx hyn check sum error.\n");
++			return -1;
++
++		}
++
++	}
++	else
++	{
++		printk(" cst3xx hyn No checksum.\n");
++		return -1;
++	}
++	return 0;
++}
++
++static int cst3xx_exit_program_mode(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[3];
++
++	buf[0] = 0xA0;
++	buf[1] = 0x06;
++	buf[2] = 0xEE;
++	ret = cst3xx_i2c_write(client, buf, 3);
++	if (ret < 0)
++		return -1;
++
++	mdelay(10);	//wait for restart
++
++
++	return 0;
++}
++
++
++static int cst3xx_update_firmware(struct cst3xx_ts_data *ts, const unsigned char *pdata)
++{
++	int ret;
++	int retry = 0;
++
++	printk(" cst3xx----------upgrade cst3xx begain------------\n");
++	disable_irq(ts->irq);
++	mdelay(20);
++START_FLOW:
++
++#ifdef HYN_UPDATE_FIRMWARE_POWERON_ENABLE
++	close_vcc3v3Power();
++	mdelay(20);
++	open_vcc3v3Power();
++	mdelay(5+retry);
++#else
++	cst3xx_reset_ic(ts,5+retry);
++#endif
++	ret = cst3xx_into_program_mode(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]into program mode failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_erase_program_area(ts->client);
++	if (ret) {
++		printk(" cst3xx[cst3xx]erase main area failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_write_program_data(ts->client, pdata);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]write program data into cstxxx failed.\n");
++		goto err_out;
++	}
++
++    ret =cst3xx_check_checksum(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx] after write program cst3xx_check_checksum failed.\n");
++		goto err_out;
++	}
++
++	ret = cst3xx_exit_program_mode(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx[cst3xx]exit program mode failed.\n");
++		goto err_out;
++	}
++
++	cst3xx_reset_ic(ts,20);
++
++	printk(" cst3xx hyn----------cst3xx_update_firmware  end------------\n");
++
++	enable_irq(ts->irq);
++
++	return 0;
++
++err_out:
++	if (retry < 30) {
++		retry++;
++		mdelay(20);
++		goto START_FLOW;
++	}
++	else {
++		enable_irq(ts->irq);
++		return -1;
++	}
++}
++
++
++
++
++/*******************************************************
++Function:
++    get firmware version, ic type...
++Input:
++    client: i2c client
++Output:
++    success: 0
++    fail:	-1
++*******************************************************/
++static int cst3xx_firmware_info(struct i2c_client * client)
++{
++	int ret;
++	unsigned char buf[28];
++//	unsigned short ic_type, project_id;
++
++
++	buf[0] = 0xD1;
++	buf[1] = 0x01;
++	ret = cst3xx_i2c_write(client, buf, 2);
++	if (ret < 0) return -1;
++
++	mdelay(40);
++
++	buf[0] = 0xD1;
++	buf[1] = 0xFC;
++	ret = cst3xx_i2c_read_register(client, buf, 4);
++	if (ret < 0) return -1;
++
++	//0xCACA0000
++	g_cst3xx_ic_checkcode = buf[3];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[2];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[1];
++	g_cst3xx_ic_checkcode <<= 8;
++	g_cst3xx_ic_checkcode |= buf[0];
++
++	printk("linc cst3xx [cst3xx] the chip g_cst3xx_ic_checkcode:0x%x.\r\n",g_cst3xx_ic_checkcode);
++
++	mdelay(2);
++
++	buf[0] = 0xD2;
++	buf[1] = 0x04;
++	ret = cst3xx_i2c_read_register(client, buf, 4);
++	if (ret < 0) return -1;
++	g_cst3xx_ic_type = buf[3];
++	g_cst3xx_ic_type <<= 8;
++	g_cst3xx_ic_type |= buf[2];
++
++
++	g_cst3xx_ic_project_id = buf[1];
++	g_cst3xx_ic_project_id <<= 8;
++	g_cst3xx_ic_project_id |= buf[0];
++
++	printk("linc cst3xx [cst3xx] the chip ic g_cst3xx_ic_type :0x%x, g_cst3xx_ic_project_id:0x%x\r\n",
++		g_cst3xx_ic_type, g_cst3xx_ic_project_id);
++
++	mdelay(2);
++
++	buf[0] = 0xD2;
++	buf[1] = 0x08;
++	ret = cst3xx_i2c_read_register(client, buf, 8);
++	if (ret < 0) return -1;
++
++	g_cst3xx_ic_version = buf[3];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[2];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[1];
++	g_cst3xx_ic_version <<= 8;
++	g_cst3xx_ic_version |= buf[0];
++
++	g_cst3xx_ic_checksum = buf[7];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[6];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[5];
++	g_cst3xx_ic_checksum <<= 8;
++	g_cst3xx_ic_checksum |= buf[4];
++
++	tpd_info.vid = g_cst3xx_ic_version;
++    tpd_info.pid = 0x00;
++
++
++	printk(" cst3xx [cst3xx] the chip ic version:0x%x, checksum:0x%x\r\n",
++		g_cst3xx_ic_version, g_cst3xx_ic_checksum);
++
++	if(g_cst3xx_ic_version==0xA5A5A5A5)
++	{
++		printk(" cst3xx [cst3xx] the chip ic don't have firmware. \n");
++		return -1;
++	}
++	if((g_cst3xx_ic_checkcode&0xffff0000)!=0xCACA0000){
++		printk("linc cst3xx [cst3xx] cst3xx_firmware_info read error .\r\n");
++		return -1;
++	}
++
++    buf[0] = 0xD1;
++	buf[1] = 0x09;
++	ret = cst3xx_i2c_write(client, buf, 2);
++	if (ret < 0) return -1;
++    mdelay(5);
++
++
++	return 0;
++}
++
++static int cst3xx_update_judge( unsigned char *pdata, int strict)
++{
++	unsigned short ic_type, project_id;
++	unsigned int fw_checksum, fw_version;
++	const unsigned int *p;
++	int i;
++	unsigned char *pBuf;
++
++	fw_checksum = 0x55;
++	p = (const unsigned int *)pdata;
++	for (i=0; i<(CST3XX_BIN_SIZE-4); i+=4) {
++		fw_checksum += (*p);
++		p++;
++	}
++
++	if (fw_checksum != (*p)) {
++		printk(" cst3xx[cst3xx]calculated checksum error:0x%x not equal 0x%x.\n", fw_checksum, *p);
++		return -1;	//bad fw, so do not update
++	}
++
++	pBuf = &pdata[CST3XX_BIN_SIZE-16];
++
++	project_id = pBuf[1];
++	project_id <<= 8;
++	project_id |= pBuf[0];
++
++	ic_type = pBuf[3];
++	ic_type <<= 8;
++	ic_type |= pBuf[2];
++
++	fw_version = pBuf[7];
++	fw_version <<= 8;
++	fw_version |= pBuf[6];
++	fw_version <<= 8;
++	fw_version |= pBuf[5];
++	fw_version <<= 8;
++	fw_version |= pBuf[4];
++
++	fw_checksum = pBuf[11];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[10];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[9];
++	fw_checksum <<= 8;
++	fw_checksum |= pBuf[8];
++
++	printk(" cst3xx[cst3xx]the updating firmware:project_id:0x%04x,ic type:0x%04x,version:0x%x,checksum:0x%x\n",
++			project_id, ic_type, fw_version, fw_checksum);
++
++	if (strict > 0) {
++
++		if (g_cst3xx_ic_checksum != fw_checksum){
++			if (g_cst3xx_ic_version >fw_version){
++				printk("[cst3xx]fw version(0x%x), ic version(0x%x).\n",fw_version, g_cst3xx_ic_version);
++			//	return -1;
++			}
++		}else{
++			printk("[cst3xx]fw checksum(0x%x), ic checksum(0x%x).\n",fw_checksum, g_cst3xx_ic_checksum);
++			return -1;
++		}
++	}
++
++	return 0;
++}
++static int cst3xx_boot_update_fw(struct cst3xx_ts_data *ts,  unsigned char *pdata)
++{
++	int ret;
++	int retry = 0;
++	int flag = 0;
++
++	while (retry++ < 3) {
++		ret = cst3xx_firmware_info(ts->client);
++		if (ret == 0) {
++			flag = 1;
++			break;
++		}
++	}
++
++	if (flag == 1) {
++		ret = cst3xx_update_judge(pdata, 1);
++		if (ret < 0) {
++			printk(" cst3xx[cst3xx] no need to update firmware.\n");
++			return 0;
++		}
++	}
++
++	ret = cst3xx_update_firmware(ts, pdata);
++	if (ret < 0){
++		printk(" cst3xx [cst3xx] update firmware failed.\n");
++		return -1;
++	}
++
++    mdelay(50);
++
++	ret = cst3xx_firmware_info(ts->client);
++	if (ret < 0) {
++		printk(" cst3xx [cst3xx] after update read version and checksum fail.\n");
++		return -1;
++	}
++
++	return 0;
++}
++static int hyn_boot_update_fw(struct cst3xx_ts_data * ts)
++{
++	unsigned char *ptr_fw;
++	int ret;
++	ptr_fw = pcst3xx_update_firmware;
++	ret = cst3xx_boot_update_fw(ts, ptr_fw);
++	return ret;
++
++}
++
++
++/*******************************Chose which I2C interface ********************************************/
++
++#if USE_ANALOG_I2C
++
++#define I2CSDA  GPIO_PB(23)
++#define I2CSCL   GPIO_PB(22)
++
++#define I2CSDA_HIGH gpio_direction_output(I2CSDA,1)
++#define I2CSDA_LOW  gpio_direction_output(I2CSDA,0)
++
++#define I2CSCL_HIGH  gpio_direction_output(I2CSCL,1)
++#define I2CSCL_LOW  gpio_direction_output(I2CSCL,0)
++
++#define delay_data 2
++static void iicstart(void)
++{
++     I2CSDA_HIGH;
++      I2CSCL_HIGH;
++      __udelay(2);
++      I2CSDA_LOW;
++      __udelay(2);
++       I2CSCL_LOW;
++       __udelay(2);
++}
++static void iicstop(void)
++{
++     I2CSDA_LOW;
++     I2CSCL_HIGH;
++     __udelay(2);
++     I2CSDA_HIGH;
++     __udelay(2);
++
++}
++static unsigned char waitack(void)
++{
++   u8 ucErrTime=0;
++
++    gpio_direction_input(GPIO_PB(23));
++   //  __udelay(2);
++
++  //  I2CSDA_HIGH;
++  //  __udelay(2);
++     I2CSCL_HIGH;
++     __udelay(2);
++
++    while(__gpio_get_value(GPIO_PB(23)))
++    {
++        ucErrTime++;
++     //   printk("time out ++ \n");
++        if(ucErrTime>250)
++         {
++                iicstop();
++                return 1;
++        }
++    }
++    I2CSCL_LOW;
++     __udelay(2);
++    return 0;
++}
++static void sendack(void)
++{
++     I2CSCL_LOW;
++     __udelay(delay_data);
++     I2CSDA_LOW;
++     __udelay(delay_data);
++
++     I2CSCL_HIGH;
++     __udelay(delay_data);
++     I2CSCL_LOW;
++     __udelay(delay_data);
++
++}
++static void sendnotack(void)
++{
++     I2CSCL_LOW;
++     __udelay(delay_data);
++    I2CSDA_HIGH;
++    __udelay(delay_data);
++
++    I2CSCL_HIGH;
++    __udelay(delay_data);
++    I2CSCL_LOW;
++    __udelay(delay_data);
++}
++static void iicsendbyte(unsigned char ch)
++{
++     unsigned char i;
++     I2CSCL_LOW;
++     for(i = 0;i<8;i++)
++     {
++          if(ch&0x80)
++          {
++              I2CSDA_HIGH;
++          }
++          else
++          {
++              I2CSDA_LOW;
++          }
++           __udelay(delay_data);
++          ch<<=1;
++          I2CSCL_HIGH;
++          __udelay(delay_data);
++               I2CSCL_LOW;
++          __udelay(delay_data);
++     }
++}
++static unsigned char iicreceivebyte(unsigned char ack)
++{
++    unsigned char i=8;
++    unsigned char ddata=0;
++
++    gpio_direction_input(GPIO_PC(27));
++    __udelay(delay_data);
++
++     for(i = 0;i<8;i++)
++     {
++         I2CSCL_LOW;
++         __udelay(delay_data);
++         I2CSCL_HIGH;
++         __udelay(delay_data);
++
++         ddata<<=1;
++         if(gpio_get_value(GPIO_PC(27))) ddata++;
++    }
++
++    if(!ack)
++        sendnotack();
++     else
++        sendack();
++
++    return ddata;
++}
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++    int count = len;
++     iicstart();
++     __udelay(delay_data);
++
++/*
++	 iicsendbyte( (0x1a<<1) | 0);
++     __udelay(delay_data);
++
++     if(waitack())
++     {
++        iicstop();
++                printk(" cst3xx_i2c_read wait ack timeoue \n");
++        return 1;
++     }
++
++     iicsendbyte(buf[0]);
++     __udelay(delay_data);
++     waitack();
++     __udelay(delay_data);
++*/
++     iicstart();
++     __udelay(delay_data);
++
++     iicsendbyte((0x1a << 1 ) | 1);
++     __udelay(delay_data);
++     if(waitack())
++     {
++        iicstop();
++                printk(" cst3xx_i2c_read wait ack timeoue \n");
++        return 1;
++     }
++     __udelay(delay_data);
++
++    while(count)
++    {
++         if(count == 1) *buf = iicreceivebyte(0);
++         else *buf = iicreceivebyte(1);
++         count --;
++         buf++;
++    }
++     iicstop();
++     __udelay(delay_data);
++     return 0;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++     int count = len;
++      iicstart();
++   //   __udelay(delay_data);
++
++      iicsendbyte((0x1A << 1) | 0);
++//      __udelay(delay_data);
++
++     if(waitack())
++     {
++        iicstop();
++        printk(" cst3xx_i2c_write send address wait ack timeoue \n");
++        return 1;
++     }
++
++      while(count--)
++      {
++            iicsendbyte(*(buf++));
++            __udelay(delay_data);
++             if(waitack())
++             {
++                iicstop();
++               printk(" cst3xx_i2c_write wait ack timeoue \n");
++                return 1;
++             }
++            __udelay(delay_data);
++      }
++
++      iicstop();
++      __udelay(delay_data);
++
++	return 0;
++}
++
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	printk(">>>>>>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	int ret = -1;
++
++    ret = cst3xx_i2c_write(client, buf, 2);
++    if(ret) printk("failed to write cst3xx\n");
++
++    ret = cst3xx_i2c_read(client, buf, len);
++    if(ret) printk("failed to write cst3xx\n");
++    return ret;
++}
++
++#elif  USE_LOWEST_I2CA
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++//	printk(">>>>>>>low speed>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	int ret = -1;
++	int retries = 0;
++
++	while (retries < 2) {
++		ret = i2c_master_recv(client, buf, len);
++		if(ret<=0)
++		    retries++;
++        else
++            break;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++//	printk(">>>>>>low speed>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	int ret = -1;
++	int retries = 0;
++
++	while (retries < 2) {
++		ret = i2c_master_send(client, buf, len);
++		if(ret<=0)
++		    retries++;
++        else
++            break;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++//	printk(">>>>>low speed>>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	int ret = -1;
++
++    ret = cst3xx_i2c_write(client, buf, 2);
++
++    ret = cst3xx_i2c_read(client, buf, len);
++
++    return ret;
++}
++
++#elif USE_HIGHEST_I2CA
++static int cst3xx_i2c_read(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++	printk(">>>>>>high speed>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	struct i2c_msg msg;
++	int ret = -1;
++	int retries = 0;
++
++	msg.flags |= I2C_M_RD;
++	msg.addr   = client->addr;
++	msg.len    = len;
++	msg.buf    = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == 1)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++/*******************************************************
++Function:
++    read data from register.
++Input:
++    buf: first two byte is register addr, then read data store into buf
++    len: length of data that to read
++Output:
++    success: number of messages
++    fail:	negative errno
++*******************************************************/
++static int cst3xx_i2c_read_register(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++	printk(">>>>>>high speed>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	struct i2c_msg msgs[2];
++	int ret = -1;
++	int retries = 0;
++
++	msgs[0].flags = 0;
++	msgs[0].addr  = client->addr;
++	msgs[0].len   = 2;
++	msgs[0].buf   = buf;
++
++	msgs[1].flags |= I2C_M_RD;
++	msgs[1].addr   = client->addr;
++	msgs[1].len    = len;
++	msgs[1].buf    = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, msgs, 2);
++		if(ret == 2)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++
++static int cst3xx_i2c_write(struct i2c_client *client, unsigned char *buf, int len)
++{
++	HYN_FUNC_ENTER();
++	printk(">>>>>>high speed>>>>>>>>>>>func=%s,line=%d\n\n",__func__,__LINE__);
++	struct i2c_msg msg;
++	int ret = -1;
++	int retries = 0;
++
++	msg.flags = 0;
++	msg.addr  = client->addr;
++	msg.len   = len;
++	msg.buf   = buf;
++
++	while (retries < 2) {
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == 1)
++			break;
++		retries++;
++	}
++
++	return ret;
++}
++#else
++#endif
++/*********************************i2c end********************************/
++
++
++static int cst3xx_i2c_test(struct i2c_client *client)
++{
++	int retry = 0;
++	int ret;
++	unsigned char buf[4];
++
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	while (retry++ < 5) {
++		ret = cst3xx_i2c_write(client, buf, 2);
++		if (ret == 0)
++			return ret;
++
++		mdelay(2);
++	}
++
++    if(retry==5) printk(" cst3xx hyn I2C TEST error.ret:%d;\n", ret);
++
++	return ret;
++}
++
++
++static void cst3xx_reset(struct cst3xx_ts_data *ts) {
++	if(gpio_is_valid(ts->pdata->reset_gpio)) {
++		gpio_direction_output(ts->pdata->reset_gpio,0);
++		mdelay(100);
++		gpio_direction_output(ts->pdata->reset_gpio,1);
++		mdelay(100);
++	}
++}
++/****************************  basic communication end*******************************/
++
++
++static void cst3xx_touch_report(struct cst3xx_ts_data *ts)
++{
++	unsigned char buf[30];
++	unsigned char i2c_buf[8];
++	unsigned char key_status, key_id = 0, finger_id, sw;
++	unsigned int  input_x = 0,bx;
++	unsigned int  input_y = 0,by;
++	unsigned int  input_w = 0;
++	unsigned int input_x_delta = 0;
++	unsigned int input_y_delta = 0;
++       unsigned char cnt_up, cnt_down;
++	int   i, ret, idx;
++	int cnt, i2c_len;
++
++	int  len_1, len_2;
++
++      key_status = 0;
++
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	ret = cst3xx_i2c_read_register(ts->client, buf, 7);
++	if(ret < 0) {
++		printk("  iic read touch point data failed.\n");
++		goto OUT_PROCESS;
++	}
++  //   printk(" read buf : buf[0]: %x ,buf[1]: %x ,buf[2]: %x, buf[3]: %x,buf[4]: %x ,buf[5]: %x ,buf[6]: %x, buf[7]: %x,\n",buf[0],buf[1],buf[2],buf[3],buf[4],buf[5],buf[6],buf[7]);
++
++	if(buf[6] != 0xAB) {
++		printk(KERN_INFO " data is not valid..\r\n");
++		goto OUT_PROCESS;
++	}
++
++    	cnt = buf[5] & 0x7F;
++	if(cnt > 1) goto OUT_PROCESS;
++	else if(cnt==0)     goto CLR_POINT;
++
++	if(cnt == 0x01) {
++		goto FINGER_PROCESS;
++	}
++
++FINGER_PROCESS:
++
++    /*
++     *  sw: buf[0] low 4 bit
++     *  x pos:  buf[1] low 4 bit | buf[3] high 4 bit
++     *  y pos:  buf[2] low 4 bit | buf[3] low  4 bit
++     *  z press : buf[4]
++     *  finger_id:buf[0] high 4 bit
++     */
++	i2c_buf[0] = 0xD0;
++	i2c_buf[1] = 0x00;
++	i2c_buf[2] = 0xAB;
++
++	ret = cst3xx_i2c_write(ts->client, i2c_buf, 3);
++	if(ret < 0) {
++		printk(" cst3xx hyn send read touch info ending failed.\r\n");
++		cst3xx_reset_ic(ts,20);
++              goto END;
++	}
++
++	idx = 0;
++       cnt_up = 0;
++       cnt_down = 0;
++	input_x = (unsigned int)((buf[idx + 1] << 4) | ((buf[idx + 3] >> 4) & 0x0F));
++	input_y = (unsigned int)((buf[idx + 2] << 4) | (buf[idx + 3] & 0x0F));
++	input_w = (unsigned int)(buf[idx + 4]);
++	sw = (buf[idx] & 0x0F) >> 1;
++	finger_id = (buf[idx] >> 4) & 0x0F;
++
++    //printk(KERN_DEBUG " no handle : cst3xxPoint x:%d, y:%3d, w:%3d, id:%d, sw:%d. \n", input_x, input_y, input_w,finger_id, sw);
++	bx = input_x;
++	by = input_y;
++
++//	input_x=input_x*CST3XX_MAX_X/268;  //update 0729: no handle == handle
++//	input_x=input_x*CST3XX_MAX_X/360;  //
++//	input_y=input_y*CST3XX_MAX_Y/800;
++
++//	if(input_x >= CST3XX_MAX_X) input_x = CST3XX_MAX_X;
++//	if(input_y >= CST3XX_MAX_Y) input_y = CST3XX_MAX_Y;
++
++//	input_x = CST3XX_MAX_X-input_x;
++//	input_y = CST3XX_MAX_Y-input_y;
++#if 1 // clivia
++	#define TP_START_X	106
++	#define TP_WIDTH	268
++	#define TP_MAX_X	(TP_START_X+TP_WIDTH-1)
++	#define TP_START_Y	0
++	#define TP_HEIGHT	800
++	#define TP_MAX_Y	(TP_START_Y+TP_HEIGHT-1)
++	if(input_x < 106)
++		input_x = 106;
++	else if(input_x > TP_MAX_X)
++		input_x = TP_MAX_X;
++	else
++		input_x = input_x - 106;
++	if(input_y > TP_MAX_Y)
++		input_y = TP_MAX_Y;
++
++#else
++	if(input_x > CST3XX_MAX_X-1)
++		input_x = CST3XX_MAX_X-1;
++	if(input_y > CST3XX_MAX_Y-1)
++		input_y = CST3XX_MAX_Y-1;
++#ifdef HYN_DRAW_POINT
++	if(input_x > 300){
++		input_x_delta = input_x - (CST3XX_MAX_X/2);
++		input_x = input_x + input_x_delta/((CST3XX_MAX_X/2)/20);
++		if(input_x > CST3XX_MAX_X) input_x = CST3XX_MAX_X;
++		}
++	if(input_x < 40){
++		input_x_delta = (CST3XX_MAX_X/2) - input_x;
++		input_x = input_x - input_x_delta/((CST3XX_MAX_X/2)/12);
++		if(input_x < 0) input_x = 0;
++		}
++	if(input_y > 760){
++		input_y_delta = input_y - (CST3XX_MAX_Y/2);
++		input_y = input_y + input_y_delta/((CST3XX_MAX_Y/2)/12);
++		if(input_y > CST3XX_MAX_Y) input_y = CST3XX_MAX_Y;
++		}
++	if(input_y < 40){
++		input_y_delta = (CST3XX_MAX_Y/2) - input_y;
++		input_y = input_y - input_y_delta/((CST3XX_MAX_Y/2)/25);
++		if(input_y < 0) input_y = 0;
++		}
++	input_x -= (CST3XX_MAX_X - CST3XX_REL_X)/2;
++#endif
++#endif
++
++//    printk(KERN_DEBUG " handle : cst3xxPoint x:%d, y:%d, w:%d, id:%d, sw:%d. \n\n", input_x, input_y, input_w,finger_id, sw);
++      //clivia printk(KERN_DEBUG "cst3xxPoint bx:%3d, by=%3d, x:%3d, y:%3d, w:%3d, id:%d, sw:%d. \n", bx, by, input_x, input_y, input_w,finger_id, sw);
++	if (sw == 0x03 ) {
++         	   if((input_x > x_temp_pos + ERROR_TOUCH) || (input_x < x_temp_pos -ERROR_TOUCH)  || (input_y > y_temp_pos + ERROR_TOUCH) || (input_y < y_temp_pos -ERROR_TOUCH))
++               {
++          //           printk(" REPORT TOUCH DOWM Handle \n");
++					x_temp_pos = input_x;
++					y_temp_pos = input_y;
++					input_report_key(ts->input_dev, BTN_TOUCH, 1);
++    		        input_report_abs(ts->input_dev, ABS_X, input_x);
++					input_report_abs(ts->input_dev, ABS_Y, input_y);
++    		        input_report_abs(ts->input_dev, ABS_PRESSURE, 1);
++    		        input_sync(ts->input_dev);
++                 }
++                cnt_down++;
++       }
++      else if(sw == 0) {
++                cnt_up++;
++        }
++
++        if((cnt_up>0) && (cnt_down==0) ){
++      //      printk(" REPORT TOUCH UP Handle \n");
++            x_temp_pos = 0;
++            y_temp_pos = 0;
++            input_report_key(ts->input_dev, BTN_TOUCH, 0);
++            input_report_abs(ts->input_dev, ABS_PRESSURE, 0);
++            input_mt_sync(ts->input_dev);
++        }
++       input_sync(ts->input_dev);
++	goto END;
++CLR_POINT:
++
++	    input_report_key(ts->input_dev, BTN_TOUCH, 0);
++           input_mt_sync(ts->input_dev);
++           input_sync(ts->input_dev);
++
++OUT_PROCESS:
++	buf[0] = 0xD0;
++	buf[1] = 0x00;
++	buf[2] = 0xAB;
++	ret = cst3xx_i2c_write(ts->client, buf, 3);
++	if (ret < 0) {
++		printk("  send read touch info ending failed.\n");
++		cst3xx_reset_ic(ts,20);
++	}
++END:
++	return;
++}
++
++
++/******************************* irq handle  begin************************************/
++static void cst3xx_work_handler(struct work_struct *work)
++{
++	struct cst3xx_ts_data *cst3xx_ts = container_of(work, struct cst3xx_ts_data, work);
++	int ret = 0;
++    /******************here handle touch *******************/
++    //    printk(KERN_INFO "-----------enter cst3xx_work_handler------------\n");
++         cst3xx_touch_report(cst3xx_ts);
++	  enable_irq(cst3xx_ts->irq);
++}
++
++static irqreturn_t cst3xx_ts_irq_handler(int irq, void *dev_id)
++{
++	struct cst3xx_ts_data *ts = dev_id;
++
++   //    printk( KERN_INFO "-----------enter cst3xx_ts_irq_handler------------\n");
++
++	disable_irq_nosync(ts->irq);//use in interrupt,disable_irq will make dead lock.
++
++	if (!work_pending(&ts->work)) {
++		queue_work(ts->workqueue, &ts->work);
++	//    queue_delayed_work(ts->workqueue,&ts->dwork,1);//10ms * x
++	} else {
++		enable_irq(ts->irq);
++	}
++
++	return IRQ_HANDLED;
++}
++/******************************* irq handle  end************************************/
++static int cst3xx_parse_dt(struct device *dev, struct cst3xx_platform_data *pdata)
++{
++    int ret = 0;
++    struct device_node *np = dev->of_node;
++    u32 temp_val = 0;
++
++    HYN_FUNC_ENTER();
++
++    /* reset, irq gpio info */
++    pdata->reset_gpio = of_get_named_gpio_flags(np, "hyn,reset-gpio",
++                        0, &pdata->reset_gpio_flags);
++    if (pdata->reset_gpio < 0)
++        HYN_ERROR("Unable to get reset_gpio");
++
++    pdata->int_gpio = of_get_named_gpio_flags(np, "hyn,irq-gpio",
++                      0, pdata->irqflags);
++    if (pdata->int_gpio < 0)
++        HYN_ERROR("Unable to get irq_gpio");
++
++    HYN_INFO(" irq gpio:%d, reset gpio:%d",
++              pdata->int_gpio, pdata->reset_gpio);
++
++    HYN_FUNC_EXIT();
++    return 0;
++}
++static int cst3xx_gpio_configure(struct cst3xx_ts_data *data)
++{
++    int ret = 0;
++
++    HYN_FUNC_ENTER();
++    /* request irq gpio */
++    if (gpio_is_valid(data->pdata->int_gpio)) {
++        ret = gpio_request(data->pdata->int_gpio, "cst3xx_irq_gpio");
++        if (ret) {
++            HYN_ERROR("[GPIO]irq gpio request failed");
++            goto err_irq_gpio_req;
++        }
++
++        ret = gpio_direction_input(data->pdata->int_gpio);
++        if (ret) {
++            HYN_ERROR("[GPIO]set_direction for irq gpio failed");
++            goto err_irq_gpio_dir;
++        }
++    }
++
++    /* request reset gpio */
++    if (gpio_is_valid(data->pdata->reset_gpio)) {
++        ret = gpio_request(data->pdata->reset_gpio, "cst3xx_reset_gpio");
++        if (ret) {
++            HYN_ERROR("[GPIO]reset gpio request failed");
++            goto err_irq_gpio_dir;
++        }
++
++//        ret = gpio_direction_output(data->pdata->reset_gpio, 1);
++//        if (ret) {
++//            HYN_ERROR("[GPIO]set_direction for reset gpio failed");
++//            goto err_reset_gpio_dir;
++//        }
++    }
++
++    HYN_FUNC_EXIT();
++    return 0;
++
++err_reset_gpio_dir:
++    if (gpio_is_valid(data->pdata->reset_gpio))
++        gpio_free(data->pdata->reset_gpio);
++err_irq_gpio_dir:
++    if (gpio_is_valid(data->pdata->int_gpio))
++        gpio_free(data->pdata->int_gpio);
++err_irq_gpio_req:
++    HYN_FUNC_EXIT();
++    return ret;
++}
++
++static int cst3xx_input_init(struct cst3xx_ts_data *ts_data)
++{
++    int ret = 0;
++    int key_num = 0;
++    struct cst3xx_platform_data *pdata = ts_data->pdata;
++    struct input_dev *input_dev;
++
++    HYN_FUNC_ENTER();
++    input_dev = input_allocate_device();
++    if (!input_dev) {
++        HYN_ERROR("Failed to allocate memory for input device");
++        return -ENOMEM;
++    }
++
++    /* Init and register Input device */
++    input_dev->name = CST3XX_NAME;
++
++    input_dev->id.bustype = BUS_I2C;
++    input_dev->dev.parent = ts_data->dev;
++
++    input_set_drvdata(input_dev, ts_data);
++
++    __set_bit(EV_SYN, input_dev->evbit);
++    __set_bit(EV_ABS, input_dev->evbit);
++    __set_bit(EV_KEY, input_dev->evbit);
++    __set_bit(BTN_TOUCH, input_dev->keybit);
++//    __set_bit(INPUT_PROP_DIRECT, input_dev->propbit);
++    set_bit(ABS_X, input_dev->absbit); //add from hyn
++	set_bit(ABS_Y, input_dev->absbit);
++    set_bit(ABS_PRESSURE, input_dev->absbit);
++
++/*---add from hyn*/
++	input_set_abs_params(input_dev, ABS_X, ts_data->pdata->x_min, ts_data->pdata->x_max, 0, 0);
++	input_set_abs_params(input_dev, ABS_Y, ts_data->pdata->y_min, ts_data->pdata->y_max, 0, 0);
++    input_set_abs_params(input_dev, ABS_PRESSURE, 0, 1, 0 , 0);
++/*add from hyn---*/
++
++    ret = input_register_device(input_dev);
++    if (ret) {
++        HYN_ERROR("Input device registration failed");
++        input_set_drvdata(input_dev, NULL);
++        input_free_device(input_dev);
++        input_dev = NULL;
++        return ret;
++    }
++
++    ts_data->input_dev = input_dev;
++
++    HYN_FUNC_EXIT();
++    return 0;
++}
++
++static int cst3xx_irq_registration(struct cst3xx_ts_data *ts_data)
++{
++    int ret = 0;
++    struct cst3xx_platform_data *pdata = ts_data->pdata;
++
++    ts_data->irq = gpio_to_irq(pdata->int_gpio);
++    pdata->irqflags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
++    HYN_INFO("irq:%d, flag:%x", ts_data->irq, pdata->irqflags);
++    ret = request_threaded_irq(ts_data->irq, NULL, cst3xx_ts_irq_handler,
++                               pdata->irqflags,
++                               CST3XX_NAME, ts_data);
++
++    return ret;
++}
++
++static int cst3xx_ts_probe_entry(struct cst3xx_ts_data *ts_data)
++{
++    int ret = 0;
++    int rc=-1;
++    int pdata_size = sizeof(struct cst3xx_platform_data);
++
++    HYN_FUNC_ENTER();
++    ts_data->pdata = kzalloc(pdata_size, GFP_KERNEL);
++    if (!ts_data->pdata) {
++        HYN_ERROR("allocate memory for platform_data fail");
++        return -ENOMEM;
++    }
++
++    if (ts_data->dev->of_node) {
++        ret = cst3xx_parse_dt(ts_data->dev, ts_data->pdata);
++        if (ret)
++            HYN_ERROR("device-tree parse fail");
++    } else {
++        if (ts_data->dev->platform_data) {
++            memcpy(ts_data->pdata, ts_data->dev->platform_data, pdata_size);
++        } else {
++            HYN_ERROR("platform_data is null");
++            return -ENODEV;
++        }
++    }
++    //init work for cst3xx..
++
++	INIT_WORK(&ts_data->work, cst3xx_work_handler);
++
++    ts_data->workqueue = create_singlethread_workqueue("cst3xx_wq");
++    if (!ts_data->workqueue) {
++        HYN_ERROR("create cst3xx workqueue fail");
++    }
++
++//    spin_lock_init(&ts_data->irq_lock);
++//    mutex_init(&ts_data->report_mutex);
++//    mutex_init(&ts_data->bus_lock);
++
++    /* Init communication interface */
++    ret = cst3xx_bus_init(ts_data);
++    if (ret) {
++        HYN_ERROR("bus initialize fail");
++        goto err_bus_init;
++    }
++#if USE_ANALOG_I2C
++        if (gpio_is_valid(I2CSDA)
++        {
++            gpio_free(I2CSDA);
++            ret = gpio_request(GPIO_PB(23),"I2C2-SDA");
++            if(ret < 0){
++                printk("I2C2-SDA gpio request failed\n");
++                return ret;
++            }
++        }
++         if (gpio_is_valid(I2CSCL))
++        {
++            gpio_free(I2CSCL);
++            ret = gpio_request(GPIO_PB(22),"I2C2-SCL");
++            if(ret < 0){
++                printk("I2C2-SCL gpio request failed\n");
++                return ret;
++            }
++         }
++#endif
++       ret =  cst3xx_i2c_test(ts_data->client);
++      // if(ret>=0){
++	   if(ret<0){
++
++
++          mdelay(100);
++
++          printk( KERN_INFO "cst3xx test OK -------------------\n");
++#ifdef HYN_UPDATE_FIRMWARE_ENABLE
++	        ret = cst3xx_boot_update_fw(ts_data,pcst3xx_update_firmware);//
++			if(ret < 0){
++			printk(" cst3xx hyn_boot_update_fw failed.\n");
++			return -1;
++			}
++#endif
++
++       }else{
++         // printk( KERN_INFO "cst3xx hyn i2c communication failed.---------------\n");
++          mdelay(20);
++		  rc = hyn_boot_update_fw(ts_data);
++		  if(rc < 0){
++			printk(" cst3xx hyn_boot_update_fw failed.\n");
++			//return -1;
++		}
++       }
++
++    ret = cst3xx_input_init(ts_data);
++    if (ret) {
++        HYN_ERROR("input initialize fail");
++        goto err_input_init;
++    }
++
++    ret = cst3xx_gpio_configure(ts_data);
++    if (ret) {
++        HYN_ERROR("configure the gpios fail");
++        goto err_gpio_config;
++    }
++       printk( KERN_INFO "cst3xx reset ----before---------------\n");
++       cst3xx_reset(ts_data);
++       printk( KERN_INFO "cst3xx reset ----after--------------\n");
++
++    ret = cst3xx_irq_registration(ts_data);
++    if (ret) {
++        HYN_ERROR("request irq failed");
++        goto err_irq_req;
++    }
++
++    HYN_FUNC_EXIT();
++    return 0;
++
++err_irq_req:
++    if (gpio_is_valid(ts_data->pdata->reset_gpio))
++        gpio_free(ts_data->pdata->reset_gpio);
++    if (gpio_is_valid(ts_data->pdata->int_gpio))
++        gpio_free(ts_data->pdata->int_gpio);
++err_gpio_config:
++    kfree_safe(ts_data->point_buf);
++    kfree_safe(ts_data->events);
++err_input_init:
++    if (ts_data->workqueue)
++        destroy_workqueue(ts_data->workqueue);
++err_bus_init:
++    kfree_safe(ts_data->bus_tx_buf);
++    kfree_safe(ts_data->bus_rx_buf);
++    kfree_safe(ts_data->pdata);
++
++    HYN_FUNC_EXIT();
++    return ret;
++}
++static int cst3xx_ts_probe(struct i2c_client *client, const struct i2c_device_id *id)
++{
++    int ret = 0;
++    struct cst3xx_ts_data *ts_data = NULL;
++	struct input_dev *input_dev;
++
++	struct cst3xx_platform_data *pdata = (struct cst3xx_platform_data*)client->dev.platform_data;
++
++    HYN_INFO("Touch Screen(I2C BUS) driver prboe...");
++    if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
++        HYN_ERROR("I2C not supported");
++        return -ENODEV;
++    }
++
++    /* malloc memory for global struct variable */
++    ts_data = (struct cst3xx_ts_data *)kzalloc(sizeof(*ts_data), GFP_KERNEL);
++    if (!ts_data) {
++        HYN_ERROR("allocate memory for cst3xx_data fail");
++        return -ENOMEM;
++    }
++    ts_data->client = client;
++    ts_data->dev = &client->dev;
++    ts_data->pdata = pdata;
++    i2c_set_clientdata(client, ts_data);
++
++    ret = cst3xx_ts_probe_entry(ts_data);
++    if (ret) {
++        HYN_ERROR("Touch Screen(I2C BUS) driver probe fail");
++        kfree_safe(ts_data);
++        return ret;
++    }
++	if(client->addr != 0x1A) //check address
++	{
++		client->addr = 0x1A;
++		printk(">>>>>>>>>>>>>1>>>xtang:i2c_client_HYN->addr=%d.\n",client->addr);
++
++	}else
++		printk(">>>>>>>>>>>>2>>>>xtang:i2c_client_HYN->addr=%d.\n",client->addr);
++
++
++    HYN_INFO("Touch Screen(I2C BUS) driver prboe successfully");
++    return 0;
++}
++
++
++static int cst3xx_ts_remove(struct i2c_client *client)
++{
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++        free_irq(ts->irq,ts);
++        devm_free_irq(&ts->client->dev, ts->client->irq,ts);
++        destroy_workqueue(ts->workqueue);
++        input_unregister_device(ts->input_dev);
++        devm_gpio_free(&ts->client->dev, ts->pdata->reset_gpio);
++        gpio_free(ts->pdata->int_gpio);
++
++#if USE_ANALOG_I2C
++         gpio_free(I2CSDA);
++        gpio_free(I2CSCL);
++#endif
++//i2c bus init.
++	cst3xx_bus_exit(ts);
++
++	return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int cst3xx_ts_suspend(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++
++	if (device_may_wakeup(&client->dev)) {
++		enable_irq_wake(client->irq);
++	} else {
++		disable_irq(client->irq);
++		cst3xx_ts_power(ts, false);//reset
++	}
++
++	return 0;
++}
++
++static int cst3xx_ts_resume(struct device *dev)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	struct cst3xx_ts_data *ts = i2c_get_clientdata(client);
++
++	if (device_may_wakeup(&client->dev)) {
++		disable_irq_wake(client->irq);
++	} else {
++		cst3xx_ts_power(ts, true);
++		enable_irq(client->irq);
++	}
++	return 0;
++}
++
++#endif
++
++static SIMPLE_DEV_PM_OPS(cst3xx_ts_pm_ops,
++			 cst3xx_ts_suspend, cst3xx_ts_resume);
++
++static const struct i2c_device_id cst3xx_ts_id[] = {
++	{ CST3XX_NAME, 0 },
++	{ }
++};
++static const struct of_device_id cst3xx_dt_match[] = {
++    {.compatible = "hyn,cst3xx", },
++    {},
++};
++MODULE_DEVICE_TABLE(of, cst3xx_dt_match);
++
++static struct i2c_driver cst3xx_ts_driver = {
++    .probe = cst3xx_ts_probe,
++    .remove = cst3xx_ts_remove,
++    .driver = {
++        .name = CST3XX_NAME,
++        .owner = THIS_MODULE,
++        .of_match_table = of_match_ptr(cst3xx_dt_match),
++	.pm	= &cst3xx_ts_pm_ops,
++    },
++    .id_table = cst3xx_ts_id,
++};
++
++static int __init cst3xx_ts_init(void)
++{
++    int ret = 0;
++
++    HYN_FUNC_ENTER();
++    ret = i2c_add_driver(&cst3xx_ts_driver);
++    if ( ret != 0 ) {
++        HYN_ERROR("hyn touch screen driver init failed!");
++    }
++    HYN_FUNC_EXIT();
++    return ret;
++}
++
++static void __exit cst3xx_ts_exit(void)
++{
++    i2c_del_driver(&cst3xx_ts_driver);
++}
++//module_init(cst3xx_ts_init);
++late_initcall(cst3xx_ts_init);
++module_exit(cst3xx_ts_exit);
++
++MODULE_AUTHOR("HYN Driver Team");
++MODULE_DESCRIPTION("HYN Touchscreen Driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/hyn_cst3xx.h b/module_drivers/drivers/input/touchscreen/hyn_touch/hyn_cst3xx.h
+new file mode 100644
+index 000000000..16f9978d1
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/hyn_cst3xx.h
+@@ -0,0 +1,136 @@
++#ifndef TOUCHSCREEN_CST3XX__H
++#define TOUCHSCREEN_CST3XX__H
++
++/*****************************************************************************
++* Included header files
++*****************************************************************************/
++#include <linux/kernel.h>
++#include <linux/device.h>
++#include <linux/i2c.h>
++#include <linux/spi/spi.h>
++#include <linux/input.h>
++#include <linux/input/mt.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/vmalloc.h>
++#include <linux/gpio.h>
++#include <linux/regulator/consumer.h>
++#include <asm/uaccess.h>
++#include <linux/firmware.h>
++#include <linux/debugfs.h>
++#include <linux/mutex.h>
++#include <linux/workqueue.h>
++#include <linux/wait.h>
++#include <linux/time.h>
++#include <linux/jiffies.h>
++#include <linux/fs.h>
++#include <linux/proc_fs.h>
++#include <linux/version.h>
++#include <linux/types.h>
++#include <linux/sched.h>
++#include <linux/kthread.h>
++#include <linux/dma-mapping.h>
++
++
++/*****************************************************************************
++* Private constant and macro definitions using #define
++*****************************************************************************/
++
++/* -- dirver configure -- */
++#define CFG_MAX_TOUCH_POINTS	1
++#define MAX_AREA	0xff
++
++#define CST3XX_NAME 	"cst3xx"
++
++/*register address*/
++#define CST3XX_ADDRESS 	0x1A
++
++/*****************************************************************************
++* Private enumerations, structures and unions using typedef
++*****************************************************************************/
++struct cst3xx_ts_data {
++	struct i2c_client *client;
++	struct input_dev *input_dev;
++	struct device *dev;
++	struct cst3xx_platform_data *pdata;
++	struct work_struct  work;
++       struct delayed_work dwork;
++	struct workqueue_struct *workqueue;
++	int irq;
++
++	struct ts_event *events;
++	u8 *bus_tx_buf;
++	u8 *bus_rx_buf;
++	u8 *point_buf;
++
++};
++
++extern struct cst3xx_ts_data *cst3xx_data;
++/* The platform data for the Focaltech ft5x0x touchscreen driver */
++struct cst3xx_platform_data {
++	unsigned int x_min;
++	unsigned int y_min;
++	unsigned int x_max;
++	unsigned int y_max;
++	unsigned long irqflags;
++	unsigned int int_gpio;
++	unsigned int reset_gpio;
++    
++	unsigned int reset_gpio_flags;
++	spinlock_t irq_lock;
++	struct mutex report_mutex;
++	struct mutex bus_lock;
++	u8 *bus_tx_buf;
++	u8 *bus_rx_buf;
++};
++
++/*****************************************************************************
++* Global variable or extern global variabls/functions
++*****************************************************************************/
++
++int cst3xx_bus_init(struct cst3xx_ts_data *ts_data);  
++int cst3xx_bus_exit(struct cst3xx_ts_data *ts_data);  
++
++#define kfree_safe(pbuf) do {\
++    if (pbuf) {\
++        kfree(pbuf);\
++        pbuf = NULL;\
++    }\
++} while(0)
++
++/*****************************************************************************
++* Debug interface.
++*****************************************************************************/
++
++#if HYN_DEBUG_EN
++
++#define HYN_DEBUG(fmt, args...) do { \
++    printk("[HYN_TS]%s:"fmt"\n", __func__, ##args); \
++} while (0)
++
++#define HYN_FUNC_ENTER() do { \
++    printk("[HYN_TS]%s: Enter(%d)\n", __func__,__LINE__); \
++} while (0)
++
++#define HYN_FUNC_EXIT() do { \
++    printk("[HYN_TS]%s: Exit(%d)\n", __func__, __LINE__); \
++} while (0)
++#else /* #if HYN_DEBUG_EN*/
++#define HYN_DEBUG(fmt, args...)
++#define HYN_FUNC_ENTER()
++#define HYN_FUNC_EXIT()
++#endif
++
++#define HYN_INFO(fmt, args...) do { \
++    printk(KERN_INFO "[HYN_TS/I]%s:"fmt"\n", __func__, ##args); \
++} while (0)
++
++#define HYN_ERROR(fmt, args...) do { \
++    printk(KERN_ERR "[HYN_TS/E]%s:"fmt"\n", __func__, ##args); \
++} while (0)
++
++#endif /* TOUCHSCREEN_CST3XX__H  */
++
++
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/hyn_cst3xx_RS659_fw.h b/module_drivers/drivers/input/touchscreen/hyn_touch/hyn_cst3xx_RS659_fw.h
+new file mode 100644
+index 000000000..efb7139f2
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/hyn_cst3xx_RS659_fw.h
+@@ -0,0 +1,1550 @@
++
++#ifndef __CST3xx_FW_H__
++#define __CST3xx_FW_H__
++
++  unsigned char cst3_fw[] ={
++    0x98,0xE0,0x07,0x01,0xC8,0xC8,0x02,0x00,0x00,0x00,0x00,0x00,0xC8,0x88,0x02,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x98,0x68,0x00,0x00,0x98,0x68,0x01,0x00,0x00,0x00,0x00,0x00,
++    0x98,0x08,0x02,0x00,0x00,0x00,0x00,0x00,0x98,0xD8,0x02,0x00,0x80,0x07,0xC0,0x17,
++    0x82,0x07,0xC0,0x07,0x01,0x65,0x40,0x86,0xC1,0x41,0xC0,0x20,0xC5,0x68,0x31,0x12,
++    0xF5,0x38,0x33,0x5A,0x32,0xA2,0x32,0xEA,0x10,0x62,0x8D,0x0E,0x81,0x07,0xC0,0x97,
++    0x30,0xF2,0xF3,0x79,0x65,0x7E,0x30,0xB2,0x31,0x09,0x10,0x9A,0x87,0x06,0xD0,0xD8,
++    0x35,0x12,0x35,0x5A,0x18,0x9A,0x39,0xC2,0x70,0x22,0x03,0x00,0x70,0x22,0x04,0x00,
++    0xD0,0x81,0x98,0x16,0x43,0xC6,0x0B,0xC6,0xC2,0xD6,0x3F,0x90,0x99,0x0E,0x40,0x86,
++    0x08,0x86,0xA9,0x0E,0x40,0x23,0x00,0x63,0x38,0x82,0x03,0x00,0x18,0x01,0x20,0x01,
++    0x28,0x01,0x30,0x01,0xD0,0x81,0x98,0x0E,0x0F,0xC6,0xC3,0xDE,0x38,0x90,0x9A,0x06,
++    0x08,0x86,0xA9,0x06,0x03,0x5B,0x38,0x82,0xAE,0xFD,0x30,0x02,0x30,0x02,0xEE,0xFD,
++    0xA8,0x85,0xE8,0x85,0x85,0x27,0xE8,0x0F,0x37,0x8A,0xB8,0xFF,0xF8,0xAF,0x87,0x0F,
++    0xD0,0x1F,0x81,0x27,0xEF,0xCF,0xBD,0xFF,0xF8,0x9F,0x87,0x27,0xE8,0xFF,0x05,0x00,
++    0xAF,0x85,0x6F,0xFA,0x39,0x01,0xC0,0x43,0x37,0x4A,0xC9,0x01,0x38,0x30,0x32,0x42,
++    0x86,0x01,0xC5,0x1B,0xCE,0x23,0xF0,0x53,0xC0,0x01,0x74,0x01,0xDD,0x16,0xC0,0x6B,
++    0x48,0x68,0x87,0x3E,0xAA,0x7B,0xAC,0x3B,0x10,0xD2,0x8C,0x16,0xB0,0x63,0x06,0x09,
++    0xB7,0x43,0xEC,0x85,0x34,0x6A,0xE8,0x4B,0xE6,0x48,0x92,0x4D,0xAF,0x4B,0x4D,0xF9,
++    0x8D,0x0E,0x10,0x12,0x82,0x16,0xE8,0x0B,0x48,0x09,0x88,0x1E,0xB5,0x5B,0xAF,0x7B,
++    0xAF,0x3B,0xEA,0x85,0x4F,0x09,0x8C,0xE6,0x0A,0x09,0xA8,0x0B,0xE8,0x85,0xAF,0x85,
++    0x67,0x3A,0xE7,0x01,0x00,0x0F,0x80,0x0F,0xF5,0x6F,0xF0,0x03,0x47,0x01,0x80,0xD6,
++    0xEF,0x85,0xA8,0xC5,0x00,0x21,0x80,0x0F,0xE8,0xBF,0x07,0x09,0x87,0x0F,0xE8,0xA7,
++    0x79,0x02,0x47,0xC3,0x0C,0x01,0x19,0x42,0x00,0xC3,0x01,0x11,0x87,0x0F,0xE8,0x0F,
++    0x61,0xEA,0x56,0x03,0x29,0x41,0x18,0x42,0x17,0x03,0x49,0x03,0x1F,0x42,0x09,0x03,
++    0x15,0x2B,0x4B,0x03,0x1D,0x42,0x09,0x03,0x4D,0x03,0x1B,0x42,0x0B,0x03,0x4B,0x03,
++    0x35,0x21,0x18,0x82,0x0B,0x03,0x4B,0x03,0x42,0x00,0x02,0x00,0x09,0x03,0x4B,0x03,
++    0x19,0x42,0x09,0x03,0x49,0x03,0x19,0x82,0x09,0x03,0x49,0x03,0x08,0x09,0x18,0x42,
++    0x0F,0x03,0x41,0x03,0x1F,0x42,0x05,0x03,0x45,0x03,0x1F,0x82,0x07,0x03,0x47,0x03,
++    0x1F,0x42,0x04,0x03,0x45,0x03,0x1D,0x42,0x05,0x03,0x45,0x03,0x1D,0x82,0x05,0x03,
++    0x45,0x03,0x1B,0x42,0x03,0x03,0x43,0x03,0x1B,0x82,0x05,0x03,0x44,0x03,0x1D,0x42,
++    0x03,0x03,0x45,0x03,0x1B,0x42,0x04,0x03,0x0E,0x81,0x42,0x02,0x82,0x27,0xE0,0xE7,
++    0x85,0x0F,0xE8,0xD7,0x85,0x0F,0xE8,0xB7,0x85,0x0F,0xE8,0xE7,0x48,0xE2,0x05,0x01,
++    0x1D,0x43,0x4C,0x03,0x1D,0x42,0x0D,0x03,0x10,0x2B,0x03,0x11,0x84,0x0F,0xE8,0xE7,
++    0x41,0xC3,0x09,0x01,0x19,0x42,0x00,0xC3,0x00,0x21,0x80,0x0F,0xE8,0x57,0x04,0x09,
++    0x84,0x0F,0xE8,0x3F,0x42,0x03,0x41,0x00,0x01,0x00,0x02,0x03,0x40,0x03,0x0F,0x09,
++    0x1F,0x42,0x00,0x03,0x4C,0x03,0x1B,0x42,0x09,0x03,0x4B,0x03,0x19,0x42,0x0C,0x03,
++    0x41,0x03,0x1D,0x42,0x05,0x03,0x45,0x03,0x1D,0x82,0x01,0x03,0x41,0x03,0x1B,0x42,
++    0x03,0x03,0x43,0x03,0x1B,0x82,0x01,0x03,0x48,0x0B,0x03,0x61,0x1B,0x0A,0x08,0x0B,
++    0x48,0x0B,0x19,0x0A,0x0F,0x0B,0x41,0x0B,0x1F,0x0A,0x00,0x0B,0x48,0xE2,0x04,0x09,
++    0xC8,0x01,0xAF,0x43,0x83,0x0F,0xD0,0x07,0xEC,0xC5,0x47,0xCA,0xC6,0x01,0xF3,0x0B,
++    0x42,0xCA,0x84,0x01,0x48,0x01,0x80,0x3E,0x4A,0xD2,0x04,0x0B,0x0C,0xF9,0x57,0xB2,
++    0x8C,0x89,0x97,0x01,0x10,0x8B,0x00,0x17,0x48,0xB2,0xCC,0xE1,0x04,0x0B,0x52,0xB2,
++    0x00,0x13,0x0E,0x31,0x08,0x0B,0x08,0x11,0x08,0x0B,0x0C,0x51,0x0C,0x0B,0x1A,0x0B,
++    0x18,0x0B,0x0A,0x01,0x1C,0x0B,0x40,0x52,0xC2,0x01,0x0F,0x14,0x3F,0x82,0xAB,0x85,
++    0x70,0x72,0x0C,0x01,0x2C,0x01,0x60,0x72,0x50,0x72,0x04,0x01,0xA4,0x82,0x02,0x40,
++    0x50,0x6A,0xC4,0x40,0xC4,0x00,0x54,0x6A,0xC0,0x10,0x1C,0x01,0xC6,0x83,0x01,0x38,
++    0xC1,0x83,0xD0,0xC0,0x94,0x05,0x14,0x2A,0x90,0x06,0x30,0x2A,0x10,0x22,0xCC,0x06,
++    0x32,0x22,0xE0,0x90,0xE6,0xD8,0x92,0xDD,0x5F,0x29,0x98,0x8E,0x59,0x0A,0xDC,0x40,
++    0xA3,0xC2,0xE2,0xB0,0xE6,0x48,0x92,0x4D,0x4E,0x71,0x98,0xDE,0x48,0xE2,0x03,0x01,
++    0xE4,0xD2,0x10,0x52,0x90,0x06,0x30,0x8A,0xE6,0x00,0x92,0x05,0x47,0x71,0x98,0xBE,
++    0x50,0xDA,0x03,0x01,0x00,0x84,0xE0,0xE2,0x43,0xAC,0xD0,0x20,0xC8,0x20,0x03,0xA4,
++    0xE6,0x00,0x92,0x05,0x47,0x71,0x98,0xB6,0x47,0x84,0x40,0xF9,0xCF,0x0E,0x00,0xF9,
++    0x03,0x84,0x48,0xA2,0x40,0x84,0x80,0x43,0xE8,0x85,0xAF,0x85,0x40,0x22,0xC3,0x03,
++    0x38,0x00,0x86,0xAE,0x00,0x01,0x85,0x0F,0xD3,0xBF,0x60,0x0A,0x01,0x01,0xE0,0x01,
++    0x8F,0x03,0xB9,0xFF,0xF9,0x57,0x34,0x0A,0x56,0x5A,0xCB,0x01,0x40,0x32,0x83,0x1F,
++    0xD0,0x9F,0x04,0x11,0x88,0x03,0x01,0x01,0x86,0x0F,0xC8,0xF7,0xBC,0xFF,0xFF,0xFF,
++    0xE8,0x85,0xA8,0x85,0x41,0xB2,0xC2,0x01,0xC8,0x03,0x42,0x01,0x8A,0x36,0x40,0xA2,
++    0xC0,0x01,0xEF,0x03,0x40,0x29,0xC8,0x0E,0xBE,0xFF,0xF7,0x8F,0x61,0x82,0xC2,0x03,
++    0x38,0x00,0xA8,0x0E,0xBE,0xFF,0xF7,0xAF,0xC3,0x03,0xC3,0x03,0x08,0xE9,0x07,0x42,
++    0x82,0x03,0x43,0xD2,0xC0,0x03,0x40,0x01,0x80,0x16,0x80,0x0F,0xE7,0x9F,0x3E,0xE7,
++    0xE8,0x85,0xA8,0x85,0x48,0x3A,0x02,0x01,0x02,0x43,0x4C,0x2A,0xCC,0x01,0xB7,0x43,
++    0xF0,0x43,0x86,0x0F,0xC8,0xCF,0xEE,0x85,0xA8,0x85,0x33,0x2A,0x48,0x01,0x80,0x56,
++    0x68,0x01,0x80,0x1E,0x30,0x82,0xC0,0x51,0x20,0xF1,0x00,0x67,0x30,0x82,0x80,0x51,
++    0x27,0xE9,0x18,0x22,0x00,0x3F,0x68,0x01,0x84,0x1E,0xF0,0x80,0x27,0x89,0x18,0x22,
++    0x04,0x0F,0xE0,0x80,0x20,0x61,0x08,0x01,0xF0,0x0A,0x4A,0x01,0xD2,0x06,0x10,0x4A,
++    0x08,0x40,0x0E,0x01,0xF0,0x8A,0x82,0x27,0xDB,0xAF,0x42,0xF9,0xEB,0x06,0x00,0xF9,
++    0x68,0x01,0x80,0x16,0x08,0xF9,0x8F,0x09,0xD0,0x40,0xC8,0x00,0xEF,0x85,0xAB,0x85,
++    0x80,0x3D,0x2C,0x01,0x20,0x01,0x00,0x51,0x4B,0x9A,0x19,0x42,0xC0,0x00,0x82,0x34,
++    0xC3,0x34,0x00,0x08,0x12,0x39,0xC1,0x00,0x0C,0x90,0xC4,0x10,0x00,0xE1,0x90,0x2C,
++    0xF0,0x82,0x80,0x24,0x30,0x01,0x38,0x01,0x10,0x01,0x90,0x1C,0x90,0x14,0x60,0x01,
++    0x83,0x46,0xF0,0x10,0xDA,0x34,0x00,0x90,0xC1,0xD0,0x1C,0x39,0x0E,0xD8,0xC4,0x90,
++    0x34,0xE1,0xF8,0xB2,0x68,0x01,0x80,0x56,0xF0,0x50,0x1B,0x51,0x19,0xD2,0x5A,0x12,
++    0xC1,0x90,0x1E,0x39,0xC4,0x90,0x0A,0xD8,0xC0,0x90,0x3E,0xE1,0xF8,0xBA,0x66,0x21,
++    0x83,0x4E,0xE0,0x18,0xD2,0x34,0x00,0xD8,0xC1,0x90,0x1E,0x39,0x0E,0xD8,0xC4,0x90,
++    0x1E,0xE1,0xF0,0x9A,0x98,0x1C,0x68,0x69,0x83,0x5E,0xE0,0x50,0x1A,0x51,0x18,0xD2,
++    0x5E,0xAA,0xC0,0x90,0xC1,0x88,0x12,0x39,0x0C,0x90,0xC4,0x50,0x0A,0xE1,0xF0,0x8A,
++    0x88,0x14,0x08,0x09,0x89,0x0C,0x70,0x29,0xD1,0x3E,0x78,0x29,0xD0,0x2E,0xC8,0x1C,
++    0x48,0x29,0xD1,0x16,0xC9,0x14,0x48,0x29,0xD8,0x0E,0x08,0x01,0x88,0x0C,0x00,0xFF,
++    0x08,0x00,0x00,0x01,0x10,0x00,0x00,0x42,0xF8,0x00,0x06,0x42,0x80,0x50,0x02,0x01,
++    0x18,0x00,0x02,0x42,0x80,0x60,0x05,0x00,0x10,0x18,0x02,0x00,0x70,0x20,0x04,0x01,
++    0xF8,0xFF,0x07,0x00,0x80,0x70,0x06,0x01,0x08,0x60,0x00,0x01,0x60,0x20,0x02,0x00,
++    0x00,0x70,0x00,0x01,0x00,0x28,0x00,0x01,0x80,0xE0,0x04,0x01,0x00,0x20,0x00,0x01,
++    0x08,0x19,0x80,0x27,0xD5,0x7F,0x16,0x82,0xED,0x3E,0x10,0xC2,0xE8,0x2E,0xC8,0x1C,
++    0x10,0x42,0xEC,0x16,0xCC,0x14,0x10,0x42,0xE0,0x0E,0x00,0x01,0x80,0x0C,0xC0,0x0C,
++    0x40,0x01,0x80,0x86,0xC8,0x24,0xD0,0x2C,0x7A,0x40,0xC6,0x00,0x80,0x00,0xD2,0x48,
++    0x94,0x4D,0x18,0x8C,0x50,0xFA,0xC7,0x93,0x58,0xFA,0xC7,0xDB,0x18,0xD2,0x80,0x16,
++    0xD0,0x40,0xC8,0x2C,0x1B,0x44,0xE4,0x20,0x90,0x25,0x67,0x29,0x93,0x06,0x38,0x3F,
++    0xE7,0x68,0x93,0x6D,0x68,0x71,0x90,0x06,0x38,0xE7,0x82,0x3D,0xEF,0x85,0xAF,0xC5,
++    0x2F,0x01,0x40,0xB2,0xF8,0x03,0x80,0x04,0x00,0x5F,0x01,0x31,0x4B,0xA2,0x1F,0x42,
++    0xC1,0x00,0x0A,0xC9,0x0A,0x48,0xC4,0x30,0x3F,0x11,0xF8,0xBA,0x01,0x21,0xF0,0x82,
++    0x40,0x51,0xD0,0x0E,0x20,0x51,0x00,0x0F,0xC0,0x51,0x90,0x25,0x04,0x19,0x06,0x00,
++    0x10,0x22,0xEC,0x06,0x31,0x22,0x30,0x02,0xC4,0xF9,0xC7,0x89,0x0A,0xF1,0x18,0x42,
++    0x0C,0xF9,0x8F,0x89,0x83,0x27,0xD0,0xF7,0xC8,0x00,0x90,0x05,0x40,0x51,0xD0,0x06,
++    0x07,0x51,0x48,0x22,0x10,0x42,0xEC,0x06,0x33,0x42,0x00,0xBC,0x03,0x84,0xE5,0x68,
++    0x90,0x6D,0xC7,0x04,0x16,0x42,0xC5,0x86,0xEF,0xC5,0xAF,0x85,0x87,0x2D,0x04,0xF9,
++    0x80,0x0C,0x00,0x01,0x80,0x04,0x80,0x14,0x52,0xCA,0x06,0x08,0x1C,0x39,0xC1,0x48,
++    0x0E,0xD8,0xC4,0x68,0x0B,0xE1,0xF0,0x4A,0x27,0x39,0x19,0x22,0xE0,0x00,0x92,0x05,
++    0x47,0x31,0xDA,0x96,0x38,0x01,0x00,0x01,0x30,0x01,0x20,0x01,0x29,0xF9,0x37,0xCA,
++    0x12,0x51,0x18,0x8A,0x54,0x72,0xC6,0x48,0x54,0x7A,0xC6,0x58,0x98,0x24,0x10,0x01,
++    0x0A,0x01,0xF0,0xCA,0x48,0xA1,0xE8,0x0E,0xE1,0xB0,0x93,0xB5,0xC0,0x40,0x90,0x05,
++    0x10,0x0A,0xED,0x06,0x35,0x62,0x10,0x4A,0xD0,0x06,0x30,0x6A,0xE2,0xD8,0xE4,0x90,
++    0x90,0x95,0x56,0x29,0x99,0x66,0x67,0xE1,0xEE,0x16,0x50,0x02,0x0C,0x01,0xA8,0x8B,
++    0x08,0x29,0x80,0x27,0xD0,0x7F,0x91,0x0D,0xD0,0x00,0x83,0x71,0x40,0xE1,0xC0,0x6E,
++    0xD0,0x40,0x83,0x71,0x40,0xE1,0xC0,0x4E,0x60,0xE1,0xE9,0x3E,0x70,0x21,0xE8,0x2E,
++    0x50,0xAA,0x05,0x01,0x85,0x83,0x50,0x9A,0x00,0xD1,0x87,0x83,0xC4,0x14,0x10,0x42,
++    0xD0,0x06,0x88,0x14,0xC5,0x0C,0x10,0x42,0xE8,0x06,0xA8,0x0C,0xC5,0x04,0x10,0x02,
++    0xD0,0x06,0xA0,0x04,0x68,0x82,0xC5,0x24,0x18,0x01,0x48,0x01,0xE8,0xDE,0x10,0x01,
++    0xF4,0x12,0x14,0x52,0xDD,0x96,0x60,0x3A,0xC0,0x23,0x61,0x01,0x86,0x2E,0x78,0x60,
++    0xC3,0x20,0x83,0x20,0xD8,0x90,0x00,0x14,0x01,0xCF,0x50,0xE1,0xD6,0xBE,0xB8,0x60,
++    0x7B,0x20,0xC5,0x20,0x80,0x20,0xDD,0x90,0x00,0x14,0x00,0x87,0x50,0x01,0xE8,0x76,
++    0x10,0x09,0x00,0x14,0x00,0x5F,0x10,0x01,0xF4,0x12,0x14,0x52,0xE2,0x16,0xD0,0x90,
++    0x00,0x14,0x00,0x27,0x50,0x01,0xD0,0x16,0x16,0x01,0x18,0x92,0x04,0x14,0xE0,0x00,
++    0xE6,0xD8,0x92,0xDD,0x5E,0x29,0x98,0x86,0xE6,0xC0,0x93,0x3D,0x7C,0x71,0x98,0x16,
++    0x44,0x82,0x4C,0x8A,0xC0,0x03,0xC0,0x4B,0x34,0x22,0x78,0xA2,0x19,0x62,0x88,0xCE,
++    0x01,0x01,0x30,0xDA,0x7A,0x72,0x04,0x10,0xCC,0x88,0x56,0x7A,0xC4,0x50,0x64,0x72,
++    0xA0,0x51,0xC8,0x68,0x21,0xF9,0x0C,0x20,0xC8,0x60,0x30,0x01,0xF8,0x32,0x25,0x01,
++    0xFD,0x62,0x11,0x32,0xD0,0x3E,0x28,0x01,0xF8,0xAA,0x6A,0xA1,0xE8,0x1E,0x60,0x79,
++    0xEB,0x0E,0x00,0x60,0x04,0xA4,0x50,0x2A,0x94,0x51,0xC0,0x50,0xC4,0x68,0x66,0x1A,
++    0xE0,0x51,0xC8,0x48,0x30,0x01,0x20,0x01,0xF9,0x72,0xFC,0x62,0x10,0x32,0xD5,0x66,
++    0x0A,0x01,0xF0,0x8A,0x48,0xA1,0xE8,0x46,0x60,0x79,0xE8,0x36,0x7B,0x68,0xC6,0x60,
++    0x83,0x20,0x03,0x28,0xCB,0x20,0xC3,0x08,0x02,0x8C,0xE0,0x00,0x90,0x05,0x46,0x29,
++    0x99,0x4E,0x06,0xCF,0x41,0x01,0x80,0xBE,0x23,0x01,0x40,0x8A,0x00,0x08,0xC3,0x68,
++    0x41,0x8A,0xC3,0x70,0x40,0x82,0x83,0x51,0xC4,0x40,0x09,0xF9,0x0B,0x48,0xC0,0x78,
++    0x10,0x01,0x08,0x01,0xF2,0xD2,0xF5,0x0A,0x10,0x52,0xD4,0x6E,0x01,0x01,0xF0,0x82,
++    0x81,0x1C,0x40,0x41,0xE8,0x46,0x48,0x79,0xEC,0x36,0x00,0x00,0x08,0x29,0x80,0x27,
++    0xC8,0xCF,0xCB,0x1C,0xC1,0x00,0x02,0x84,0x40,0x22,0x83,0x51,0xC3,0x40,0x49,0x1A,
++    0xCB,0x51,0xC0,0x50,0x18,0x01,0x08,0x01,0xF2,0xDA,0xF7,0x8A,0x10,0x5A,0xD4,0x3E,
++    0x14,0x01,0xF0,0x12,0x50,0x41,0xE9,0x1E,0x48,0x79,0xE8,0x0E,0x00,0x88,0x02,0x0C,
++    0xE7,0x20,0x93,0x25,0x66,0x29,0x98,0x46,0x00,0x01,0x08,0x01,0x2A,0x99,0x60,0xA2,
++    0x1A,0x6A,0x5F,0xBA,0x02,0x70,0x03,0x50,0x38,0x39,0xC9,0x90,0x0E,0xF8,0xCD,0xB8,
++    0x15,0xE1,0xF0,0xD2,0x10,0x52,0xD5,0x2E,0xE4,0x00,0x92,0x05,0x10,0x92,0xD5,0x0E,
++    0xE4,0x00,0x96,0x05,0x50,0x81,0xEA,0x2E,0x08,0x01,0x80,0xCB,0x02,0x01,0x50,0x6A,
++    0x00,0x8C,0x00,0x1F,0xE0,0x48,0x92,0x4D,0x4F,0x31,0xDA,0x26,0x4F,0x1A,0x8A,0x01,
++    0x40,0x29,0xC8,0x6E,0xC0,0xC3,0x40,0xF1,0x92,0x1E,0xE0,0x00,0x80,0xC3,0x80,0x2D,
++    0xE8,0x85,0xC7,0x43,0x10,0x09,0x18,0x82,0x80,0x43,0x00,0x01,0x87,0xC3,0x38,0xB7,
++    0xC0,0xC3,0x40,0x01,0x82,0x0E,0xF0,0x00,0x81,0xC3,0x50,0xF2,0x40,0x84,0x40,0xF1,
++    0xC8,0x6E,0xC7,0x43,0x18,0x09,0x18,0xC2,0x80,0x43,0x00,0x01,0x07,0x84,0x38,0x37,
++    0xA9,0xC5,0x47,0x92,0x17,0x09,0x80,0x01,0xC0,0x0B,0x18,0x8A,0x81,0x0B,0x68,0x7A,
++    0x79,0x62,0x31,0x62,0xA4,0x01,0x06,0x3F,0xBC,0xFF,0xEF,0x5F,0x48,0x92,0x41,0x43,
++    0xE0,0x00,0x02,0x43,0x40,0x8A,0xC1,0x03,0x40,0x01,0x80,0x0E,0x05,0xC1,0xB0,0x43,
++    0x40,0x32,0x81,0x1F,0xE9,0xA7,0x51,0x72,0x49,0x2A,0x41,0x22,0x86,0x1F,0xC8,0xFF,
++    0xB9,0xFF,0xEF,0xDF,0x01,0x11,0x88,0x03,0x51,0x4A,0x49,0x02,0x40,0x02,0x81,0x1F,
++    0xD9,0xF7,0x55,0x3A,0x48,0xEA,0x40,0xF2,0x86,0x1F,0xF8,0xA7,0xC8,0x03,0x43,0x01,
++    0x83,0x16,0xC8,0x03,0x40,0x11,0x88,0x26,0x48,0x12,0x41,0x43,0x10,0x09,0x18,0x82,
++    0x00,0x43,0x48,0xB2,0x40,0xB2,0x80,0x1F,0xF0,0x07,0x74,0x9A,0xC1,0xCB,0xC1,0x83,
++    0x18,0x42,0x80,0x0E,0x05,0x01,0xA8,0x43,0xBB,0xFF,0xF7,0x3F,0x41,0xD2,0xC0,0x8B,
++    0x09,0x0C,0xC6,0xCB,0x11,0x0C,0xC8,0x4B,0x10,0x0C,0x72,0x62,0xB5,0x01,0xE2,0x8B,
++    0x10,0x0C,0x4C,0xB2,0x46,0x4C,0x10,0x0C,0x48,0x7A,0x40,0x4B,0x18,0x0C,0xA0,0x48,
++    0x1D,0x0C,0xEA,0x4B,0x1F,0x0C,0xBC,0xFF,0xE8,0x97,0x03,0x11,0xA0,0x83,0x4D,0x1A,
++    0x40,0x1A,0x00,0xEF,0x00,0x48,0x00,0x01,0x00,0x40,0x00,0x01,0x00,0x00,0x01,0x01,
++    0x08,0x60,0x00,0x01,0x18,0x10,0x00,0x00,0x48,0xE0,0x06,0x00,0x50,0xA0,0x02,0x00,
++    0x00,0x58,0x00,0x01,0x00,0x80,0x00,0x01,0x00,0xC0,0x00,0x01,0x00,0x20,0x00,0x01,
++    0x80,0xE0,0x04,0x01,0xF8,0x00,0x06,0x42,0x70,0x60,0x04,0x01,0x00,0x70,0x00,0x01,
++    0x82,0x1F,0xE8,0x47,0x30,0x8A,0x11,0x09,0xC8,0x01,0x42,0x52,0x58,0x52,0x80,0x17,
++    0xEF,0x7F,0xB9,0xFF,0xD9,0xEF,0x34,0x8A,0xC8,0x01,0x42,0x32,0x83,0x0F,0xF0,0x87,
++    0x82,0x07,0xD8,0xE7,0xBF,0xFF,0xE7,0x2F,0xC8,0x03,0x43,0x31,0x83,0x06,0x38,0x9F,
++    0xE8,0xC5,0x07,0x00,0x08,0x60,0x00,0x01,0x30,0x58,0x00,0x00,0xA8,0x85,0x33,0x22,
++    0xF0,0x03,0x87,0x07,0xF2,0xCF,0x46,0x7A,0x2C,0x01,0x00,0x2B,0xB6,0x2B,0x05,0x21,
++    0xAF,0x2A,0xB8,0xFF,0xE5,0x57,0xA2,0x01,0xCA,0x03,0x33,0x08,0x42,0x52,0x72,0x48,
++    0x1C,0x0B,0x5C,0x0B,0x02,0x48,0x1A,0x0B,0x0B,0x2B,0xCE,0x0B,0x30,0x48,0xA8,0x16,
++    0x0E,0x09,0x04,0x0B,0x1B,0x2B,0xE8,0x85,0xAD,0x85,0x87,0xAD,0x42,0x12,0xC2,0x01,
++    0x42,0x0B,0x40,0x48,0x00,0x48,0x02,0x0B,0x52,0x02,0x4A,0x0A,0x40,0x0A,0x82,0x0F,
++    0xCA,0x77,0x41,0x0A,0x71,0xFA,0xC1,0x80,0x81,0xA4,0x41,0xEA,0xB6,0xE1,0x81,0x01,
++    0x83,0x9C,0x01,0x47,0x47,0xD2,0xB9,0xFF,0xF9,0x4F,0x66,0xCA,0x52,0x03,0x83,0x01,
++    0xE7,0x03,0x40,0x79,0x81,0x06,0x31,0x12,0x48,0xB2,0x01,0x01,0x58,0x9A,0x81,0x07,
++    0xF9,0x1F,0x37,0x12,0x48,0x9A,0x01,0x09,0x58,0x82,0x81,0x07,0xFB,0xEF,0x56,0x03,
++    0x80,0x01,0xE2,0x03,0x40,0x59,0x8D,0x7E,0xC1,0xA4,0x31,0x8A,0x13,0x01,0xD8,0x1B,
++    0xDB,0x2B,0x19,0x5A,0x40,0x6C,0x40,0x3C,0xD8,0x68,0x07,0x2C,0xE4,0x00,0xE4,0x48,
++    0xE4,0x90,0x92,0x95,0x17,0xD2,0x9C,0xAE,0x52,0x03,0x83,0x01,0xE5,0x03,0x40,0x59,
++    0x81,0x2E,0x50,0x12,0x49,0x12,0x41,0x1A,0x58,0x0D,0x80,0x0F,0xC1,0xC7,0xEC,0xA4,
++    0x30,0xA2,0x39,0x01,0x01,0x01,0xF0,0x42,0x0A,0x99,0x18,0x42,0x08,0x51,0x80,0x27,
++    0xC1,0x4F,0x00,0x44,0x01,0x01,0xF0,0x02,0x0A,0x99,0x18,0x42,0x08,0x51,0x80,0x27,
++    0xC1,0x0F,0x00,0x04,0xE5,0x68,0xE5,0x20,0xE7,0xF8,0x93,0xFD,0x7F,0x29,0x98,0x4E,
++    0x68,0xB2,0x60,0xA2,0xA0,0xF1,0x3D,0x01,0x01,0x01,0xF0,0x42,0x08,0x51,0x08,0x00,
++    0x87,0x1F,0xF8,0x87,0x00,0x44,0x01,0x01,0xF0,0x02,0x09,0x51,0x08,0x00,0x80,0x1F,
++    0xF9,0x4F,0x07,0x04,0xE5,0x68,0xE5,0x20,0xE7,0xF8,0x93,0xFD,0x7F,0x29,0x98,0x5E,
++    0x40,0x0D,0x80,0x07,0xD9,0xE7,0xC2,0x9C,0xC8,0x03,0x42,0x31,0x81,0x96,0x84,0xAD,
++    0xE8,0x85,0x07,0x00,0x10,0x00,0x00,0x42,0x00,0x01,0x00,0x42,0x80,0xE0,0x04,0x01,
++    0x00,0x00,0x01,0x01,0x08,0x60,0x00,0x01,0x48,0xE0,0x06,0x00,0x58,0x50,0x03,0x01,
++    0x48,0xFA,0xFF,0x53,0x84,0x13,0xF8,0x53,0x80,0x13,0x32,0x52,0x96,0x01,0xCE,0x93,
++    0x80,0x13,0xCC,0x4B,0x83,0x0B,0x3E,0x82,0xA8,0xF5,0x37,0x2A,0x46,0xC2,0xFF,0x03,
++    0x12,0x42,0xCD,0xBE,0x07,0x21,0x61,0xBA,0x18,0x42,0xCB,0x20,0x02,0x99,0x0B,0x00,
++    0xC0,0x20,0x39,0xA1,0xF8,0x3A,0x37,0xB1,0xF8,0x32,0x9D,0x0C,0x48,0x09,0x88,0x1E,
++    0x07,0xF9,0x87,0x09,0xD8,0x00,0x96,0x3D,0x50,0x09,0x88,0x1E,0x02,0xC9,0x08,0x00,
++    0xD8,0x00,0x94,0x35,0xC8,0x03,0x85,0x04,0x06,0x81,0xDF,0x00,0x0A,0x51,0x1B,0x42,
++    0x08,0x81,0x87,0x1F,0xFE,0xBF,0xCC,0x00,0x93,0x05,0x40,0x51,0xD3,0x06,0x00,0x51,
++    0x0B,0xF9,0x8F,0xB9,0x10,0x42,0xEC,0x06,0x30,0x42,0xC8,0x04,0xC8,0x13,0x0F,0x48,
++    0x00,0x90,0x1A,0x8A,0xD0,0x0C,0x80,0x8B,0xF8,0x0C,0x88,0x08,0x81,0xCB,0x8B,0x88,
++    0x81,0xCB,0x3D,0x88,0x08,0x00,0x78,0x48,0x1F,0x42,0x80,0xC3,0xE3,0xF8,0xE7,0xF8,
++    0x58,0x04,0x09,0xA1,0x83,0x1F,0xF8,0x67,0x86,0x51,0x90,0x05,0x40,0xF9,0x97,0x56,
++    0x5A,0xAA,0xEE,0xCA,0x30,0x52,0x90,0x51,0x10,0x12,0x94,0x16,0x82,0xC3,0xA9,0xC2,
++    0x01,0x1F,0x80,0xCB,0x07,0x0F,0x00,0xF9,0x80,0xC3,0xC1,0x44,0xC8,0x44,0xC0,0x03,
++    0xE8,0x00,0x82,0x43,0xEF,0xF5,0xAF,0x85,0x80,0x2D,0x34,0x01,0x00,0x5D,0x46,0x03,
++    0x86,0x14,0x40,0x3A,0xF8,0x1B,0x14,0x09,0x06,0x01,0x48,0x4A,0x60,0x4A,0xC6,0x6B,
++    0x68,0x59,0x85,0x16,0xE5,0x00,0x12,0x02,0x9F,0xCE,0x07,0xF9,0x80,0x43,0x58,0x01,
++    0x80,0xBE,0x30,0x01,0x48,0x15,0x00,0x01,0x25,0x99,0x5B,0xF2,0x08,0x20,0x03,0x77,
++    0x2A,0x21,0x19,0x2A,0xC1,0x68,0xCF,0x68,0xD0,0x6B,0x69,0x09,0x88,0x2E,0x80,0x43,
++    0xE7,0xB0,0x93,0xB5,0xE0,0x48,0x72,0x09,0x82,0x1E,0xE0,0x00,0x94,0x05,0x16,0x82,
++    0x98,0x76,0x77,0x01,0x80,0x3E,0x73,0x09,0xCD,0x16,0x48,0xBA,0x00,0x09,0x80,0x43,
++    0x60,0x9A,0x6D,0x15,0x3D,0x01,0x40,0x72,0x80,0x01,0x87,0x1C,0x00,0x0F,0x79,0x01,
++    0x88,0x9E,0x50,0x0D,0x90,0x04,0x10,0x01,0xC1,0x43,0x31,0x1A,0x37,0x8A,0xB8,0xFF,
++    0xFB,0xDF,0xE2,0x68,0xC4,0x1C,0xC0,0x03,0x4E,0x00,0x0E,0x00,0x1B,0x82,0x89,0x03,
++    0x05,0x59,0x8D,0x03,0xEB,0x20,0xE5,0x20,0x00,0x4F,0x50,0x0D,0x90,0x04,0x10,0x01,
++    0xC1,0x43,0x31,0x1A,0x37,0x8A,0xB8,0xFF,0xFB,0x3F,0xE2,0x68,0xEB,0x20,0xE3,0xF8,
++    0x95,0xFD,0x17,0xBA,0x98,0xDE,0xC6,0x1C,0x1C,0x01,0xC4,0x03,0x48,0x08,0x4E,0x01,
++    0x80,0x9E,0x70,0x01,0x81,0x3E,0x80,0x03,0xC0,0x1C,0xC8,0x03,0x85,0x03,0x03,0x59,
++    0x85,0x03,0xE5,0x20,0x01,0x3F,0x80,0x03,0xC0,0x1C,0xC8,0x03,0x83,0x03,0x8B,0x1B,
++    0x05,0x59,0x8D,0x03,0xEB,0x20,0xE5,0x20,0x00,0x27,0x70,0x09,0xCD,0x16,0x00,0x59,
++    0x83,0x03,0xE1,0x20,0x37,0x02,0xB9,0xFF,0xFC,0x9F,0x40,0x82,0x42,0x0B,0x12,0x01,
++    0x1A,0x8A,0x00,0x0B,0x42,0x72,0x44,0x0B,0x1A,0xCA,0x00,0x0B,0x61,0x6A,0x44,0x03,
++    0x42,0x00,0x02,0x00,0x07,0x03,0x01,0xF9,0x80,0x89,0x84,0x1F,0xE9,0x4F,0x46,0x03,
++    0x08,0x09,0x18,0x42,0x00,0x03,0x81,0x2D,0xEF,0x85,0xAF,0xFD,0x80,0x0D,0xFC,0x54,
++    0x30,0x32,0x30,0x62,0x6F,0xD2,0xAB,0x01,0x50,0x09,0x88,0x4E,0x00,0x0F,0x80,0x0F,
++    0xC1,0x4F,0xC0,0x43,0x37,0x00,0xAA,0xD6,0xC5,0x43,0x09,0xF9,0x01,0x42,0x80,0x43,
++    0x04,0x09,0x30,0x22,0x51,0xD2,0x03,0x8F,0x60,0x01,0xC1,0x2E,0xF7,0x00,0x0B,0x01,
++    0x1A,0x42,0x08,0x83,0x30,0x0A,0x01,0x17,0x02,0xF9,0x0F,0x83,0x08,0x01,0x19,0x01,
++    0x08,0x9B,0x04,0x01,0x00,0x4F,0x78,0x01,0x88,0x16,0x18,0x01,0x00,0x9B,0x06,0x17,
++    0xC6,0x9B,0x01,0x9B,0xCA,0xB0,0xE7,0x00,0x94,0x05,0x14,0x42,0x9B,0x9E,0x37,0x02,
++    0x40,0x01,0x80,0x26,0x04,0xA1,0x00,0x83,0x04,0x01,0x30,0x22,0x00,0x0F,0x00,0x21,
++    0x03,0x83,0xD4,0x00,0x92,0x25,0x44,0x83,0x08,0x01,0x1C,0x42,0x01,0x83,0xC2,0x43,
++    0x37,0x00,0xAA,0xE6,0xC5,0x43,0x09,0xF9,0x01,0x42,0x80,0x43,0x66,0x01,0x88,0x5E,
++    0xC0,0x24,0x40,0x09,0x88,0x7E,0x05,0x01,0x02,0x83,0x44,0x83,0x08,0x01,0x1C,0x42,
++    0x05,0x83,0x3A,0x47,0xAC,0x9D,0x87,0x1D,0x20,0x01,0x00,0x01,0x80,0x0C,0x70,0x15,
++    0x44,0x7A,0xF2,0x03,0xEE,0x00,0x92,0x3D,0x6F,0x6A,0xAA,0x01,0x00,0xAF,0x81,0x07,
++    0xF9,0x8F,0xC5,0x43,0x30,0x00,0xA2,0x1E,0x44,0x4A,0xF2,0x03,0x17,0xC2,0x9D,0xB6,
++    0x44,0x3A,0xF2,0x03,0x10,0xC2,0x9D,0x06,0x21,0x11,0xC0,0x43,0x08,0xF9,0x05,0x42,
++    0x82,0x43,0x41,0x5A,0x46,0x0B,0x14,0x79,0x00,0x8A,0x48,0x09,0x88,0x9E,0x08,0x01,
++    0x0E,0x0B,0x44,0x0B,0x83,0x8B,0xE1,0xB0,0xE7,0x20,0x93,0x25,0x60,0x11,0x88,0x56,
++    0x30,0x5A,0xD3,0xCB,0xD4,0x1C,0x10,0x8A,0x8A,0x2E,0xD0,0xCB,0xD4,0x24,0x10,0x8A,
++    0x88,0x0E,0x08,0x09,0x8F,0x0C,0x08,0x01,0x08,0x0B,0x0A,0x01,0x08,0x0B,0x0C,0x81,
++    0x02,0x0B,0x44,0x0B,0x10,0x01,0x1C,0x8A,0x00,0x0B,0x62,0x11,0x88,0x4E,0xC6,0x0C,
++    0x39,0x0F,0x4B,0x7A,0x60,0x54,0x80,0x13,0x12,0x01,0x80,0x13,0xE4,0x4B,0x86,0x0B,
++    0x4A,0xA2,0x89,0x01,0x5E,0x53,0x84,0x13,0x58,0x53,0x8A,0x13,0x12,0x21,0x89,0x13,
++    0x14,0x19,0x88,0x13,0x4E,0x53,0x8E,0x13,0x48,0x53,0x94,0x13,0x4A,0x4B,0x92,0x0B,
++    0x0C,0x31,0x90,0x0B,0x3F,0x82,0xAB,0x85,0x80,0x4D,0x34,0x22,0x30,0x01,0x00,0x01,
++    0x80,0x2C,0x38,0x01,0x48,0xF2,0xD8,0x43,0xDA,0x4B,0x1A,0x42,0x80,0x14,0x40,0xEA,
++    0x80,0x71,0x80,0x24,0xC0,0x71,0x80,0x1C,0x60,0x09,0x80,0x0E,0x60,0x29,0x88,0x7E,
++    0x60,0x09,0x88,0x26,0x73,0x02,0xE1,0x80,0x81,0x2C,0x78,0x02,0x01,0x27,0x70,0x02,
++    0xE0,0x80,0x83,0x2C,0x79,0xEA,0xF8,0xC1,0x47,0x35,0xB8,0xFF,0xF0,0x0F,0x01,0x3F,
++    0x60,0x21,0x88,0x2E,0x70,0xDA,0x40,0x35,0xBD,0xFF,0xFF,0xDF,0x7B,0xBA,0xB8,0x11,
++    0x6F,0x5A,0xA8,0x01,0xC5,0x43,0x09,0xF9,0x01,0x42,0x80,0x43,0xC1,0x43,0x09,0x01,
++    0x19,0x42,0x80,0x43,0x42,0x6A,0x40,0x0B,0x10,0x01,0x1A,0x8A,0x00,0x0B,0x42,0x62,
++    0x44,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,0x48,0x52,0x40,0x43,0x10,0x09,0x00,0xDF,
++    0x00,0x00,0x01,0x01,0x08,0x60,0x00,0x01,0x80,0x20,0x06,0x01,0x00,0xF8,0x07,0x00,
++    0x80,0x50,0x02,0x01,0x30,0x04,0x05,0x08,0x00,0x60,0x00,0x01,0x00,0x00,0x06,0x42,
++    0x80,0x01,0x06,0x42,0xF8,0x00,0x06,0x42,0x18,0x80,0x05,0x01,0x70,0x90,0x06,0x01,
++    0x50,0x40,0x07,0x01,0x68,0x80,0x02,0x01,0x18,0x82,0x00,0x43,0x0C,0x09,0x00,0x01,
++    0xB9,0xFF,0xFF,0xC7,0x43,0x09,0x88,0x2E,0x61,0x21,0x88,0x7E,0x10,0x09,0x90,0x04,
++    0x30,0x82,0x19,0x01,0xCF,0x14,0xB8,0xFF,0xF0,0xC7,0x16,0x09,0x90,0x04,0x10,0x01,
++    0x08,0x59,0x40,0x35,0x37,0x9A,0xB8,0xFF,0xF0,0x87,0x16,0x09,0x90,0x04,0x10,0x01,
++    0x09,0x29,0x30,0xC2,0x37,0x9A,0xB8,0xFF,0xF0,0x47,0x16,0x09,0x90,0x04,0x10,0x01,
++    0x0E,0x71,0x40,0x1A,0x37,0x9A,0xB8,0xFF,0xF0,0x07,0x16,0x09,0x90,0x04,0x10,0x01,
++    0x08,0x29,0x30,0x9A,0xC7,0x24,0xB8,0xFF,0xF0,0xC7,0x15,0x09,0x90,0x04,0x10,0x01,
++    0x08,0x29,0x18,0x09,0xC7,0x1C,0xB8,0xFF,0xF1,0x87,0x05,0x9F,0x60,0x09,0x80,0x0E,
++    0x61,0x29,0x88,0x7E,0x10,0x11,0x90,0x04,0x11,0x09,0x30,0x82,0x18,0x01,0xC8,0x14,
++    0xBD,0xFF,0xF7,0x1F,0x10,0x11,0x90,0x04,0x10,0x01,0x30,0x9A,0xC8,0x14,0xC0,0x2C,
++    0xBC,0xFF,0xF7,0xDF,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x21,0x40,0x35,0x30,0x9A,
++    0xBC,0xFF,0xF7,0x9F,0x10,0x09,0x90,0x04,0x11,0x01,0x08,0x31,0x30,0xC2,0x31,0x9A,
++    0xBC,0xFF,0xF7,0x5F,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x29,0x30,0x9A,0xC0,0x24,
++    0xBC,0xFF,0xF7,0x1F,0x10,0x09,0x90,0x04,0x10,0x01,0x08,0x29,0x18,0x09,0xC0,0x1C,
++    0xBB,0xFF,0xF7,0xDF,0xC6,0x43,0x09,0xF9,0x01,0x42,0x80,0x43,0x40,0xEA,0x44,0x0B,
++    0x42,0x48,0x02,0x48,0x04,0x0B,0x40,0xE2,0x0A,0x01,0x0F,0x0B,0x0C,0x01,0x00,0x0B,
++    0x44,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,0x87,0x4D,0xE8,0x85,0xAC,0x85,0x63,0xBA,
++    0xC8,0x03,0x2B,0x01,0x40,0x09,0x80,0x16,0xC8,0x03,0x43,0x29,0x8C,0x7E,0x40,0x9A,
++    0xC0,0x01,0x86,0x1F,0xCC,0xA7,0x72,0x92,0xC0,0x83,0x41,0x11,0x9B,0x26,0xC8,0x03,
++    0xB8,0xFF,0xFF,0x4F,0x83,0xAB,0xE9,0x85,0xE1,0x00,0x82,0x83,0xEB,0x85,0xCB,0x03,
++    0x40,0x21,0x88,0x26,0xBF,0xFF,0xF7,0xFF,0x03,0x19,0x88,0x03,0xEB,0x85,0xCB,0x03,
++    0x47,0x19,0x80,0xDE,0xC8,0x03,0x43,0x31,0x84,0xC6,0x47,0x22,0xC4,0x01,0xFE,0x03,
++    0x40,0x01,0x88,0x3E,0x41,0x0A,0x84,0x01,0xD0,0x0B,0x48,0x31,0x9C,0x3E,0xC0,0x03,
++    0x30,0x00,0xA8,0x26,0x44,0xEA,0xC3,0x01,0xE8,0x03,0x44,0x01,0x83,0x16,0x40,0xEA,
++    0x83,0x2B,0xE8,0x85,0xBC,0xFF,0xEF,0x7F,0xEF,0x85,0xAB,0xC5,0x20,0x01,0x30,0x1A,
++    0x03,0x09,0x48,0xB2,0x69,0xC2,0x33,0x01,0x59,0x51,0x80,0xE6,0xE3,0x4E,0x78,0xBA,
++    0xC0,0xD3,0x81,0x1F,0xE8,0xB7,0x65,0x52,0x22,0x09,0x39,0x61,0x62,0x52,0x71,0x61,
++    0x63,0x92,0x41,0x72,0x16,0x31,0xC0,0x01,0x52,0x03,0x82,0x01,0x59,0xC9,0x80,0xAE,
++    0xE0,0x4E,0x58,0x59,0x80,0x56,0x59,0x61,0x80,0x66,0x59,0x69,0x88,0xBE,0x01,0x29,
++    0x88,0x43,0x22,0x09,0x00,0x9F,0x59,0xD1,0x81,0x6E,0x59,0x01,0x8A,0x7E,0x89,0x53,
++    0x25,0x09,0x08,0x59,0xA1,0x0B,0x00,0x57,0x02,0x39,0x88,0x43,0x00,0x3F,0x81,0x07,
++    0xE9,0x5F,0x06,0x27,0x19,0x12,0x80,0xD3,0x00,0x0F,0x01,0x41,0x19,0x12,0x80,0xD3,
++    0x00,0xEF,0x00,0x11,0x88,0x43,0x22,0x09,0x00,0xCF,0x00,0x01,0x89,0x43,0x42,0x43,
++    0x19,0x82,0x01,0x43,0x02,0x9F,0x88,0x43,0x20,0x09,0x00,0x87,0x02,0x19,0x88,0x43,
++    0x20,0x09,0x00,0x67,0x02,0x21,0x88,0x43,0x20,0x09,0x00,0x47,0x88,0x53,0x22,0x09,
++    0x08,0x69,0xA6,0x0B,0x02,0x1F,0x88,0x53,0x27,0x09,0x08,0x79,0xA0,0x0B,0x60,0x01,
++    0x82,0x66,0x40,0x7A,0x40,0x0B,0x30,0x48,0xAE,0x2E,0x08,0x81,0x02,0x0B,0x08,0x81,
++    0x00,0x0B,0x08,0x81,0x01,0x0B,0x40,0x43,0x19,0x82,0x05,0x43,0xEF,0xC5,0xAF,0x8D,
++    0x82,0x15,0x44,0x42,0x82,0x0C,0x40,0x0A,0xC0,0x01,0xDE,0x2B,0xD8,0x33,0x0A,0x01,
++    0xB2,0x0B,0x64,0x12,0xC5,0x0B,0x11,0xF9,0x01,0x8A,0x80,0x0B,0xC1,0x0B,0x11,0x01,
++    0x19,0x8A,0x80,0x0B,0x4E,0xF2,0x89,0x01,0x42,0x53,0x1A,0x01,0x1A,0xD2,0x00,0x53,
++    0x52,0xAA,0x41,0x8B,0x18,0x01,0x1C,0xCA,0x01,0x8B,0x4A,0x92,0x40,0x53,0x18,0x09,
++    0x18,0xD2,0x00,0x53,0x52,0x03,0x82,0x01,0xE7,0x0B,0x48,0x79,0x80,0xAE,0xE1,0x03,
++    0x41,0x69,0x8E,0x16,0x08,0xA9,0x00,0x91,0xBF,0xFF,0xEF,0x27,0x41,0x09,0x88,0xDE,
++    0x33,0x42,0x19,0x82,0x00,0x38,0x12,0x09,0x90,0xCD,0x95,0x04,0x18,0x01,0xC0,0x0C,
++    0xBC,0xFF,0xEF,0x1F,0x40,0x62,0x11,0x09,0x90,0x04,0x10,0x01,0x90,0xCD,0x35,0x9A,
++    0xBB,0xFF,0xEF,0xDF,0xC0,0x14,0x10,0x09,0xC8,0x48,0xED,0x48,0x92,0x04,0x00,0x48,
++    0x10,0x01,0x18,0x09,0xBB,0xFF,0xEF,0x8F,0x00,0xF7,0x08,0xA1,0x07,0x91,0xB8,0xFF,
++    0xE8,0x0F,0x46,0x09,0x8B,0xC6,0x18,0xAA,0x13,0x09,0x20,0x40,0x60,0x08,0x90,0x04,
++    0x30,0x9A,0xC0,0x0C,0xBB,0xFF,0xEF,0x0F,0x00,0x77,0x08,0xB1,0x07,0x91,0xB8,0xFF,
++    0xE8,0x8F,0x45,0x09,0x88,0x46,0xC0,0x14,0x15,0x09,0xC8,0x48,0xEA,0x48,0x00,0x48,
++    0x30,0x9A,0x90,0x04,0xBA,0xFF,0xEF,0x8F,0xC6,0x03,0x09,0xF9,0x01,0x42,0x80,0x03,
++    0x40,0x42,0x40,0x0B,0x42,0x48,0x02,0x48,0x00,0x0B,0x40,0x3A,0x0A,0x01,0x0F,0x0B,
++    0x0C,0x01,0x00,0x0B,0x44,0x0B,0x12,0x01,0x1A,0x8A,0x00,0x0B,0xE8,0xF5,0x07,0x00,
++    0x70,0x20,0x04,0x01,0xF8,0x00,0x06,0x42,0x80,0x01,0x06,0x42,0x00,0x00,0x07,0x01,
++    0x00,0x00,0x00,0x01,0x00,0x60,0x00,0x01,0x10,0x00,0x00,0x42,0x08,0x00,0x00,0x01,
++    0x00,0x00,0x00,0x42,0x50,0x40,0x07,0x01,0x08,0x40,0x02,0x01,0x52,0xE2,0x43,0x83,
++    0x03,0x83,0x42,0xE2,0xF7,0x0B,0x4C,0xF9,0x94,0x16,0xF0,0x0B,0xE4,0x48,0xB2,0x0B,
++    0xF0,0x03,0x44,0xC1,0x90,0x0E,0x00,0x01,0x03,0x83,0x3C,0x82,0x4C,0xB2,0x4B,0x53,
++    0x5C,0xA2,0xE3,0xC3,0x1C,0x12,0x0C,0x53,0x10,0x43,0x02,0x09,0xB3,0xC3,0x3C,0x82,
++    0xAB,0x85,0x40,0x8A,0x84,0x01,0x42,0x0B,0x10,0x01,0x1C,0x8A,0x03,0x0B,0x54,0x7A,
++    0x4B,0x62,0x43,0x7A,0x86,0x1F,0xC0,0xC7,0xEF,0x85,0xA8,0xC5,0x47,0x4A,0x83,0x01,
++    0xC3,0x0B,0x70,0x62,0x30,0x48,0xAC,0x46,0xC2,0x0B,0x10,0x01,0x18,0x8A,0x80,0x0B,
++    0x44,0x83,0x0B,0x01,0x1B,0x42,0x04,0x83,0xE8,0xC5,0x0F,0x01,0x0D,0x8B,0x45,0x9B,
++    0x66,0x02,0x03,0x79,0x01,0x1A,0x30,0x2A,0xAB,0x01,0x69,0x04,0x50,0x13,0x5B,0x09,
++    0x80,0xE6,0x58,0x29,0x80,0x46,0x58,0x41,0x8B,0xB6,0x93,0x4B,0x46,0x9B,0x3F,0xD8,
++    0x88,0x16,0x00,0x81,0x07,0x83,0xED,0xC5,0x0A,0x8B,0x4D,0xDA,0x10,0x42,0x8C,0x16,
++    0x07,0x29,0x05,0x83,0x00,0x3F,0xE0,0x92,0x02,0x93,0xE7,0x00,0x93,0x05,0x2C,0x04,
++    0x40,0x89,0x9A,0x06,0x28,0x0C,0x03,0xA1,0x07,0x83,0xED,0xC5,0x5B,0x9A,0xD2,0x7B,
++    0x40,0xDC,0x78,0x11,0x90,0x56,0x7B,0x01,0x8F,0x36,0x40,0x83,0x50,0x7A,0x02,0x84,
++    0x43,0x7A,0x12,0x03,0x2C,0x0C,0x03,0x1F,0x40,0x83,0x17,0xD0,0x48,0x5A,0xC2,0x80,
++    0x90,0x3D,0x04,0x7C,0x00,0x89,0x16,0x00,0xD1,0xC0,0x41,0x01,0xC7,0x96,0x90,0xC5,
++    0xBC,0xFF,0xF7,0x1F,0x44,0x3A,0x12,0x3A,0x82,0x96,0x43,0x32,0x84,0x41,0x10,0x3A,
++    0x88,0x76,0x03,0x09,0x86,0x07,0xC8,0x47,0x05,0xC1,0xB0,0x03,0x40,0x12,0x0A,0x09,
++    0x83,0x0B,0x00,0x2F,0x46,0xBA,0x81,0x01,0xC8,0x03,0x42,0x01,0x89,0x26,0x41,0xEA,
++    0xC4,0x31,0x16,0x3A,0x89,0xAE,0x40,0xEA,0x41,0x0B,0x40,0xCA,0x72,0x50,0x80,0x01,
++    0x80,0x13,0x60,0x50,0x80,0x13,0x52,0x50,0x86,0x13,0x84,0x0B,0xC2,0x0B,0xC0,0x13,
++    0xC4,0x48,0xC4,0x13,0xC6,0x1B,0xC6,0x90,0xC5,0x48,0x8C,0x29,0x50,0x50,0x88,0x13,
++    0x88,0x0B,0x02,0x69,0x19,0x00,0xD0,0xC0,0x40,0x81,0xC2,0x0E,0x29,0x04,0x03,0xFF,
++    0x06,0x01,0x18,0x02,0x29,0x04,0x03,0xDF,0x41,0x6A,0xC1,0xC0,0x40,0x19,0xC1,0x26,
++    0x29,0x04,0x43,0x62,0x11,0x03,0x03,0x9F,0x01,0xC7,0x41,0x4A,0xC1,0x81,0xC1,0xC0,
++    0x40,0x01,0xC1,0x26,0x29,0x04,0x43,0x3A,0xC3,0x01,0x11,0x03,0x00,0x47,0x01,0x69,
++    0x19,0x00,0xD0,0xC0,0x41,0xB1,0xC1,0x1E,0x29,0x04,0x03,0x0F,0x7D,0xD2,0x10,0xC2,
++    0x87,0xF6,0x40,0xBB,0xA0,0xBA,0x40,0xDA,0xC4,0xD1,0x15,0x1A,0x8B,0x7E,0x68,0x04,
++    0x40,0x61,0x8A,0x66,0x50,0x1B,0xE3,0xFA,0x52,0x72,0x90,0x01,0x78,0x01,0x8C,0x16,
++    0x04,0x09,0xA8,0x83,0x00,0x1F,0xE0,0xC2,0x40,0x01,0x88,0x06,0xAB,0x8B,0x6C,0x04,
++    0xE4,0x00,0x92,0x05,0x2A,0x04,0x43,0x89,0x98,0x16,0x00,0x01,0x1B,0x02,0x2E,0x04,
++    0xD2,0x43,0xE3,0x00,0x90,0x43,0x03,0x81,0x07,0x83,0xED,0xC5,0x07,0x8B,0xED,0xC5,
++    0x10,0x00,0x00,0x42,0x00,0x00,0x01,0x01,0xF8,0x00,0x06,0x42,0x80,0xE0,0x04,0x01,
++    0x08,0x60,0x00,0x01,0x80,0x01,0x06,0x42,0xF8,0xFF,0x07,0x00,0x00,0x10,0x00,0x01,
++    0x80,0x50,0x02,0x01,0x88,0x36,0x00,0x00,0x00,0x20,0x00,0x01,0x00,0xC0,0x00,0x01,
++    0x77,0x81,0xF8,0xFF,0xF8,0x02,0x07,0x00,0xA8,0x85,0x80,0x07,0xC8,0xCF,0x65,0x32,
++    0xC8,0x03,0x43,0x01,0x80,0x26,0x40,0x31,0x8F,0xD6,0xBF,0xFF,0xD7,0x6F,0x3B,0xBF,
++    0xBD,0xFF,0xCF,0x77,0x38,0xA7,0x07,0x00,0x00,0x00,0x07,0x01,0xAF,0xC5,0x77,0x7A,
++    0x03,0x01,0x87,0x83,0x01,0x09,0x80,0x83,0x07,0x01,0x81,0x83,0x05,0x19,0x80,0x83,
++    0x03,0x29,0x89,0x83,0x07,0x69,0x89,0x83,0x05,0x61,0x88,0x83,0x11,0x02,0x32,0xAA,
++    0xA9,0x01,0x06,0x44,0x04,0xF9,0x87,0x89,0x20,0x84,0x01,0x09,0x34,0x62,0xE1,0x01,
++    0x93,0x03,0x91,0x03,0x05,0x41,0x90,0x03,0x07,0x51,0x90,0x03,0x01,0xA1,0x98,0x03,
++    0x05,0xE9,0x98,0x03,0x07,0x71,0x98,0x03,0x01,0x39,0xA0,0x03,0x3B,0x01,0xA0,0xBB,
++    0x01,0x71,0x98,0x83,0x03,0x29,0x98,0x83,0x0F,0x71,0x98,0x8B,0x99,0x83,0xA5,0xBB,
++    0x0D,0x41,0xA0,0x8B,0x0F,0x81,0xA1,0x8B,0x09,0x61,0x88,0x0B,0x0B,0x71,0x8F,0x0B,
++    0x0D,0x11,0x8F,0x0B,0x0F,0xF1,0x88,0x0B,0x98,0x03,0x03,0x59,0x28,0x84,0x0D,0x40,
++    0x10,0x44,0x01,0xC9,0x0B,0x00,0x12,0x44,0x02,0x19,0x18,0x00,0x0E,0x43,0x43,0x62,
++    0x09,0x43,0xBD,0x7B,0x30,0x02,0x09,0x51,0x80,0x11,0x85,0x1F,0xD7,0x2F,0x03,0xB1,
++    0x90,0x43,0x01,0xF1,0x93,0x43,0x8B,0x7B,0x32,0x02,0x81,0x01,0xB0,0x3B,0xBA,0x3B,
++    0x0A,0xC1,0xB8,0x0B,0x0C,0x51,0xB8,0x0B,0x10,0x41,0x36,0x0A,0x8A,0x01,0x09,0x54,
++    0x12,0xF9,0x97,0x99,0x0E,0x54,0x14,0xC1,0xB9,0x13,0x1E,0x41,0x87,0x5B,0x10,0x11,
++    0x80,0x53,0x12,0xF1,0x80,0x53,0x14,0x51,0x94,0x13,0x92,0x1B,0x16,0x21,0x93,0x13,
++    0x16,0xA9,0x0A,0x14,0x10,0x71,0x98,0x13,0x10,0x69,0xA2,0x13,0x12,0x21,0xA0,0x13,
++    0x12,0x41,0x16,0x14,0x17,0x31,0xB8,0x93,0x34,0xBC,0xB7,0x3B,0x18,0x21,0x30,0x12,
++    0x94,0x01,0x93,0x9B,0x1A,0x31,0x90,0x9B,0x11,0x99,0x0E,0x94,0x16,0xA1,0x80,0x53,
++    0x10,0x51,0x88,0x53,0xB4,0x3B,0x16,0x21,0x8D,0x53,0x52,0x52,0x00,0x54,0x13,0x09,
++    0x88,0x53,0x14,0x51,0x90,0x53,0x10,0x11,0xA0,0x13,0x0F,0x21,0xAB,0x0B,0x08,0xC1,
++    0xAC,0x0B,0xAA,0x0B,0x33,0x0A,0xC8,0x01,0xA0,0x7B,0xAE,0x7B,0x1A,0xF1,0x88,0x01,
++    0xBA,0x5B,0xB8,0x5B,0x1C,0xE1,0xB9,0x5B,0x1E,0x41,0xB8,0x5B,0x80,0x13,0x08,0xB1,
++    0x80,0x0B,0x0A,0x19,0x84,0x0B,0x4C,0xE2,0x00,0x0B,0x92,0x3B,0x4C,0xDA,0xC4,0x01,
++    0x38,0x0B,0x88,0x91,0x3E,0x0B,0x8A,0xE1,0x38,0x0B,0x0C,0xE1,0x40,0xC2,0x84,0x1F,
++    0xCC,0xDF,0x47,0xBA,0x09,0xE1,0xC0,0xC1,0x87,0x1F,0xC8,0xB7,0x4C,0x9A,0x44,0xAA,
++    0xCE,0x11,0x03,0x0B,0xCC,0x71,0x00,0x0B,0x88,0xA1,0x08,0x0B,0x8A,0xA1,0x08,0x0B,
++    0xCA,0xE1,0x01,0x0B,0xC8,0xC1,0x01,0x0B,0x8C,0x61,0x0D,0x0B,0xCA,0x81,0x15,0x0B,
++    0xF8,0x48,0x10,0x0B,0xFE,0x48,0x08,0x0B,0xE9,0xC5,0xAF,0x85,0x0C,0x01,0x60,0x1A,
++    0x47,0x12,0xA4,0x61,0xF8,0x1B,0x06,0x77,0x02,0x21,0x19,0x42,0xCB,0x28,0x00,0x99,
++    0x12,0x79,0x08,0x00,0xC4,0x40,0x89,0x13,0x16,0x01,0x88,0x13,0x94,0x13,0x10,0x14,
++    0x12,0x14,0xE6,0x48,0x94,0x4D,0x16,0x5A,0xC0,0x76,0x07,0x01,0x13,0xF9,0x2F,0x89,
++    0x08,0x68,0x03,0x37,0x00,0x08,0xCA,0x48,0xCC,0x48,0xAA,0x53,0xAA,0x53,0xE6,0x00,
++    0x94,0x05,0x16,0x1A,0xC1,0xB6,0xEF,0x85,0xA3,0x85,0x51,0x82,0x90,0x01,0x0E,0x01,
++    0x26,0x8C,0xD0,0x01,0xBC,0x8B,0xB8,0x8B,0x36,0x9A,0x98,0x01,0x8A,0xCB,0x0C,0xCC,
++    0x9E,0xCB,0x88,0xCB,0x2C,0x09,0xB0,0xAB,0xA8,0x8B,0x34,0xA2,0xA1,0x01,0xCD,0x1B,
++    0xB0,0x9B,0x36,0x9A,0x9A,0x01,0xA9,0xCB,0x9A,0x01,0xA9,0xEB,0xA8,0xCB,0xA8,0xAB,
++    0x28,0x29,0x89,0xAB,0x8B,0x0B,0x57,0x42,0x88,0x8B,0x46,0x09,0x8C,0x16,0xA8,0xCB,
++    0xE5,0x85,0x39,0x97,0xE3,0x85,0x39,0x82,0x0B,0x08,0x42,0x22,0x41,0x13,0x18,0x01,
++    0x04,0xD2,0x90,0x41,0x04,0x13,0x10,0xD0,0x1A,0x8A,0x08,0x0B,0x40,0x0B,0x42,0x0B,
++    0x14,0x41,0x18,0x8A,0x00,0x0B,0x08,0x01,0x03,0x0B,0x3C,0x82,0xAA,0x85,0x40,0xE2,
++    0x40,0x0B,0x30,0x48,0xAE,0x2E,0x08,0x81,0x02,0x0B,0x08,0x81,0x00,0x0B,0x08,0x81,
++    0x02,0x0B,0x48,0xBA,0x8C,0x01,0x46,0x53,0x38,0x90,0x78,0x90,0x04,0x53,0x44,0x53,
++    0x18,0x81,0x19,0xD2,0x02,0x53,0x5C,0x9A,0x12,0x09,0x06,0xD3,0x16,0x91,0x01,0x13,
++    0x44,0x8A,0x42,0x23,0x10,0x61,0x18,0xA2,0x02,0x23,0x44,0x23,0x1A,0xA2,0x00,0x23,
++    0x4C,0x23,0x1A,0xA2,0x08,0x23,0x4A,0x23,0x18,0xA2,0x08,0x23,0x40,0x23,0x1E,0xA2,
++    0x02,0x23,0x46,0x43,0x10,0x01,0x1A,0x82,0x04,0x43,0x02,0xD1,0x07,0xC3,0x00,0x01,
++    0x08,0xC3,0xEA,0x85,0x40,0x22,0x42,0x13,0x08,0x09,0x18,0x52,0x00,0x13,0x48,0x13,
++    0x18,0x52,0x0C,0x13,0x4C,0x13,0x1A,0x52,0x0E,0x13,0x42,0x13,0x1E,0x52,0x00,0x13,
++    0x39,0x82,0x43,0xF2,0x58,0x0B,0x10,0x21,0x18,0x8A,0x18,0x0B,0x5A,0x0B,0x10,0x01,
++    0x18,0x8A,0x18,0x0B,0x5C,0x13,0x08,0x01,0x18,0x52,0x18,0x13,0x40,0xA2,0x11,0x01,
++    0x80,0x01,0x06,0x13,0x40,0x13,0x1A,0x52,0x01,0x13,0x4A,0x82,0x41,0x43,0x10,0x01,
++    0x18,0x82,0x00,0x43,0x38,0x82,0xAB,0x85,0x08,0x09,0x00,0x31,0x82,0x07,0xD0,0x17,
++    0x08,0x11,0x00,0x21,0x81,0x07,0xD0,0xF7,0x00,0x09,0x80,0x07,0xD0,0xD7,0x02,0x31,
++    0x82,0x07,0xD0,0xBF,0x00,0x21,0x80,0x07,0xD0,0xA7,0x82,0x07,0xD0,0x4F,0xEB,0x85,
++    0xA9,0x85,0x43,0x02,0x4A,0xCA,0xC0,0x91,0x11,0x43,0x0A,0x91,0x80,0x1F,0xC8,0x27,
++    0x40,0xE2,0x08,0x51,0x80,0x41,0x81,0x1F,0xC8,0x0F,0x60,0xDA,0x29,0x01,0x90,0x2B,
++    0xBA,0xFF,0xF7,0x27,0x07,0x09,0xB8,0xFF,0xF8,0xFF,0x01,0xA1,0xBB,0xFF,0xFF,0x27,
++    0xBB,0xFF,0xFF,0xA7,0xBD,0xFF,0xFF,0xAF,0xBD,0xFF,0xFF,0x27,0xBE,0xFF,0xFF,0x5F,
++    0x83,0x2B,0x09,0x2B,0x40,0x7A,0x08,0x71,0x80,0x91,0x81,0x1F,0xC3,0x2F,0x0F,0x2C,
++    0x85,0x2B,0x83,0x2B,0x81,0x2B,0x8F,0x2B,0x88,0x2B,0x03,0x51,0x8D,0x03,0x0D,0x2C,
++    0x8F,0x2B,0x0F,0x2C,0x13,0x2C,0x11,0x2C,0xE8,0x85,0x03,0x00,0x00,0x00,0x01,0x01,
++    0xC8,0x21,0x01,0x00,0x70,0x02,0x01,0x00,0xF8,0xFF,0x07,0x04,0x68,0xA2,0x03,0x00,
++    0x70,0x90,0x06,0x01,0x80,0xE0,0x04,0x01,0x00,0x20,0x00,0x01,0x10,0x00,0x00,0x42,
++    0x00,0x00,0x00,0x42,0x80,0x01,0x06,0x42,0xF8,0x00,0x06,0x42,0x18,0x00,0x02,0x42,
++    0xA8,0x85,0x80,0x07,0xC8,0xCF,0xEE,0x85,0xAF,0x85,0xB8,0xFF,0xE8,0x6F,0xEF,0x85,
++    0xA8,0x7D,0x80,0x04,0x88,0x0C,0xC0,0x0C,0x80,0x14,0xC0,0x04,0x83,0x1C,0x30,0x42,
++    0x40,0x7E,0x80,0x25,0xE8,0x05,0x00,0x00,0xAC,0xFD,0x87,0x1D,0x30,0x32,0x00,0x01,
++    0x82,0x14,0x00,0x9F,0x44,0xDA,0x0E,0x01,0x0C,0x0B,0x26,0x01,0xC2,0x14,0x00,0x28,
++    0x7F,0xC2,0x4E,0xC3,0x1F,0x02,0x09,0xC3,0xD0,0x6C,0x90,0x04,0x14,0x09,0x08,0x01,
++    0x30,0x82,0xD9,0x64,0x86,0x17,0xE0,0x1F,0xF8,0x82,0x33,0x0A,0xCF,0x99,0x49,0xC9,
++    0x99,0x3E,0x40,0x91,0xE7,0x16,0x48,0xC3,0x1F,0x02,0x0D,0xC3,0x40,0x20,0x63,0x01,
++    0x88,0x36,0xD7,0x6C,0x90,0x04,0x10,0x09,0x09,0x01,0x34,0x82,0xD8,0x64,0x80,0x17,
++    0xE3,0x77,0xFD,0xA2,0xD0,0x6C,0x90,0x04,0x14,0x09,0x08,0x01,0x30,0x82,0xD9,0x64,
++    0x85,0x17,0xE0,0x2F,0xF8,0xBA,0xD3,0x6C,0x90,0x04,0x10,0x09,0x09,0x01,0x34,0x82,
++    0xD8,0x64,0x80,0x17,0xE5,0xE7,0x14,0x3A,0xE9,0x16,0x30,0x02,0x30,0xE2,0x31,0x3A,
++    0xFD,0x82,0x13,0xC2,0xE3,0x0E,0x98,0xBA,0x05,0x17,0x10,0x02,0xDB,0x06,0x98,0xA2,
++    0x46,0xC2,0x4D,0x03,0xDE,0x8A,0x0B,0x00,0xC0,0x00,0xCA,0x24,0x00,0x44,0xC0,0x24,
++    0xE0,0x00,0x84,0x24,0xC2,0x14,0xE0,0x00,0x90,0x05,0x86,0x14,0xC8,0x2C,0xC0,0x14,
++    0x15,0x42,0x9C,0x3E,0x87,0x3D,0xE8,0x85,0xAC,0xFD,0x87,0x7D,0x30,0xA2,0x30,0xFA,
++    0xD8,0x0B,0x8F,0x6C,0xD8,0x0B,0x8B,0x64,0x40,0x01,0x80,0x6E,0x48,0x52,0x05,0x99,
++    0x07,0x43,0x12,0xF9,0x58,0x3A,0x95,0x81,0x10,0xD3,0x06,0x43,0x00,0xC1,0x83,0x17,
++    0xF8,0xFF,0xF1,0x84,0xB0,0xE1,0x01,0xCF,0x40,0x1A,0x0D,0x19,0x04,0x0B,0x0A,0x19,
++    0x05,0x0B,0x48,0x12,0xC2,0x84,0xC0,0x30,0x11,0x01,0x30,0xDA,0x30,0x8A,0x00,0x09,
++    0x82,0x17,0xC0,0xC7,0x29,0x01,0x30,0x1A,0x14,0x09,0x08,0x01,0x40,0x1D,0xB8,0x04,
++    0x82,0x17,0xE0,0x6F,0xE7,0x68,0x93,0x6D,0x6F,0x91,0x99,0xA6,0x48,0xB2,0x44,0x43,
++    0x10,0x11,0x18,0x82,0x01,0x43,0x30,0x02,0x80,0x01,0x35,0x2A,0xC8,0x03,0x32,0x00,
++    0xAC,0xEE,0x49,0x9A,0x00,0x01,0x80,0x43,0x31,0x12,0x31,0xCA,0x00,0x11,0x80,0x0F,
++    0xF9,0xF7,0x34,0x1A,0xB8,0x04,0x08,0x01,0x00,0x11,0xD0,0x84,0x84,0x17,0xC0,0x47,
++    0x49,0x42,0xD4,0x43,0x08,0x43,0x2A,0x01,0xC2,0x64,0x00,0x00,0x80,0x74,0x00,0xBF,
++    0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,0x81,0x17,0xC0,0x27,0xB8,0x0C,0xA0,0x04,
++    0x30,0x8A,0x41,0x1D,0xD8,0x84,0xD0,0x64,0xB9,0xFF,0xFF,0xF7,0xC4,0x74,0xC8,0x30,
++    0x09,0x09,0x30,0xDA,0x30,0x52,0x31,0x42,0x80,0x17,0xC0,0xA7,0xE7,0x68,0x93,0x6D,
++    0xC4,0x6C,0x10,0x2A,0x99,0x26,0x37,0x1A,0xB8,0x04,0x08,0x01,0x00,0x19,0xD0,0x84,
++    0x82,0x17,0xC0,0xF7,0x31,0x12,0x31,0xCA,0x00,0x01,0x80,0x0F,0xFB,0x47,0x4B,0x92,
++    0x40,0x43,0x10,0x11,0x18,0x82,0x04,0x43,0x87,0x9D,0xE8,0x85,0xAC,0xFD,0x87,0x1D,
++    0x30,0x7A,0x50,0x01,0x80,0x16,0x00,0x01,0x80,0x0C,0x00,0x0F,0x00,0x09,0x80,0x0C,
++    0x2A,0x01,0x00,0x47,0xCD,0x64,0x00,0x40,0xC1,0x30,0x32,0x52,0x08,0x19,0xD8,0x6C,
++    0xC0,0x0C,0x80,0x0F,0xF9,0x3F,0x07,0x41,0x85,0x17,0xF0,0xD7,0x20,0x09,0xC0,0x34,
++    0x80,0x01,0x84,0x14,0x60,0x81,0x99,0x36,0x0A,0xF9,0x47,0xF2,0x88,0x11,0x18,0x0B,
++    0x42,0x08,0x1B,0x0B,0x02,0x0F,0x40,0xDA,0x1F,0x23,0x02,0xF9,0x4F,0xCA,0x82,0x89,
++    0x88,0x01,0x12,0x43,0x00,0x11,0x80,0x17,0xF0,0x1F,0xC5,0x14,0xF0,0x03,0x46,0x01,
++    0x80,0x3E,0x00,0x51,0x84,0x17,0xF0,0xE7,0x40,0x83,0x41,0x03,0x30,0x00,0xA8,0x86,
++    0x07,0x5F,0x00,0xF9,0x4C,0x7A,0x82,0x89,0x88,0x01,0x12,0x43,0x00,0x09,0x80,0x17,
++    0xF1,0x7F,0x44,0x83,0x40,0x03,0x30,0x00,0xA3,0x1E,0xE0,0x20,0x93,0x25,0x67,0xF9,
++    0xC9,0x86,0x06,0xE4,0xE1,0xF8,0x35,0x52,0x08,0x09,0xD8,0x6C,0xC0,0x0C,0x80,0x0F,
++    0xFB,0x4F,0xE5,0x68,0x90,0x6D,0xC7,0x1C,0x15,0x2A,0x9C,0x9E,0x3F,0x17,0xA9,0x85,
++    0x80,0x3D,0x34,0x7A,0x34,0xA2,0x00,0xD9,0xEF,0x02,0x0E,0xF9,0x88,0x09,0x40,0x01,
++    0x80,0x0E,0x30,0x72,0x00,0x0F,0x30,0x19,0x13,0xB0,0xD9,0xC3,0x81,0x34,0xD8,0xC3,
++    0x80,0x2C,0x98,0x1C,0xC2,0x34,0x00,0x00,0xC0,0x00,0x86,0x24,0x45,0xAA,0x11,0x81,
++    0x00,0x13,0x1A,0x0B,0x28,0x01,0x00,0x67,0x4D,0x03,0x01,0x48,0xC0,0x00,0x42,0x03,
++    0x01,0x33,0x30,0x1A,0x30,0x52,0x09,0x09,0x00,0x01,0x80,0x0F,0xFB,0xDF,0xE3,0x68,
++    0x90,0x6D,0xC7,0x34,0x17,0x2A,0x9C,0x7E,0x28,0x01,0x00,0x67,0x4D,0x03,0x03,0x48,
++    0xC0,0x00,0x42,0x03,0x00,0x33,0x08,0x09,0x31,0x1A,0x31,0x52,0x30,0x42,0x80,0x0F,
++    0xFB,0x4F,0xE3,0x68,0x90,0x6D,0xC7,0x2C,0x17,0x2A,0x9C,0x7E,0x48,0x0B,0xA1,0x0C,
++    0x89,0x04,0x30,0xDA,0x10,0x09,0xC8,0x1C,0xC7,0x34,0xB8,0xFF,0xFB,0xFF,0x4A,0x0B,
++    0x89,0x04,0x30,0xDA,0x10,0x01,0xA0,0x0C,0xC8,0x24,0xC0,0x2C,0xBA,0xFF,0xFF,0xB7,
++    0x48,0xC2,0x00,0x01,0x88,0x01,0x12,0x43,0x48,0xB2,0x18,0x43,0x37,0x57,0xAE,0xC5,
++    0x30,0x1A,0x30,0x42,0x30,0xBA,0xD8,0x23,0xD8,0x2B,0x4A,0xB2,0xC0,0xC8,0x8A,0x04,
++    0x30,0xD2,0x31,0xCA,0x87,0x0F,0xF8,0xDF,0x30,0x01,0x00,0x3F,0x09,0x09,0x30,0xDA,
++    0x30,0x92,0x31,0x42,0x81,0x0F,0xF8,0xB7,0xE7,0xB0,0x93,0xB5,0x17,0x32,0x9D,0xAE,
++    0xC8,0x04,0x10,0x01,0x18,0x01,0x00,0x4F,0x00,0x01,0x00,0x1F,0x82,0x5B,0xE0,0x48,
++    0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0xCE,0xE6,0x90,0x92,0x95,0x17,0x12,0x9D,0x9E,
++    0xE8,0xC5,0x07,0x00,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0x48,0xE0,0x06,0x00,
++    0x00,0xF0,0x00,0x01,0x60,0x20,0x02,0x00,0x49,0x32,0x41,0x2A,0x05,0x43,0x9E,0xFF,
++    0x7F,0x04,0x3A,0xF7,0x94,0x15,0x3A,0x00,0x77,0x18,0x06,0xF9,0x04,0xC2,0x3C,0x48,
++    0x74,0x48,0x00,0xCA,0x50,0x01,0xD0,0x5E,0x38,0x90,0x78,0x90,0xD4,0x41,0x40,0x98,
++    0x54,0xE2,0x00,0xD8,0xC6,0xD0,0x4C,0x9B,0x18,0x1A,0x1C,0x5A,0x0B,0x9B,0x3E,0x82,
++    0x40,0x98,0x54,0xCA,0x04,0xD8,0xC4,0xD0,0x44,0x9B,0x18,0x1A,0x18,0x5A,0x00,0x9B,
++    0x3A,0x82,0x93,0x05,0x36,0x10,0x76,0x90,0x0C,0x09,0x00,0x8A,0x48,0x00,0x52,0x9A,
++    0x04,0x00,0xC4,0x00,0x03,0x0B,0x38,0x82,0x96,0x05,0x32,0x10,0x70,0x90,0x0E,0x09,
++    0x00,0x8A,0x54,0x72,0x4C,0x00,0x02,0x00,0x94,0x01,0xC4,0x00,0x03,0x0B,0x38,0x82,
++    0xB3,0x15,0x3B,0x82,0xFB,0x85,0x39,0x82,0x40,0x32,0x48,0x0B,0x10,0x21,0x18,0x8A,
++    0x0B,0x0B,0x38,0x82,0x48,0x1A,0x48,0x43,0x14,0x21,0x18,0x82,0x0B,0x43,0x38,0x82,
++    0x07,0x20,0x28,0xD0,0x68,0x07,0x00,0x07,0x20,0x07,0x00,0x07,0x08,0x07,0x00,0x07,
++    0xAC,0xFD,0x87,0x4D,0xD0,0x94,0x30,0x22,0xF8,0x43,0x80,0x0C,0xF8,0x6B,0xC6,0x64,
++    0x08,0x01,0x80,0x0B,0x00,0x01,0x00,0x8F,0x0A,0x21,0x19,0x0A,0x18,0x99,0xCB,0x48,
++    0x0E,0xD8,0xC2,0x48,0xC8,0x4B,0x4C,0x79,0x80,0x36,0x80,0x83,0xE0,0x90,0xCA,0x64,
++    0xD8,0x64,0xC0,0x4B,0xE0,0x48,0x82,0xCB,0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0x5E,
++    0xC0,0x64,0xC0,0x03,0x80,0x44,0x40,0x01,0x88,0x0E,0x80,0x6D,0xE8,0x85,0xC7,0x44,
++    0x40,0x09,0x88,0x1E,0xC0,0x0C,0x40,0x09,0x8F,0x06,0x38,0xB7,0x00,0x01,0x80,0x34,
++    0x80,0x2C,0xC8,0x44,0xC4,0x0C,0x10,0x0A,0x88,0x96,0x02,0x01,0x30,0x01,0x08,0x01,
++    0x88,0x1C,0x88,0x14,0x1C,0xC9,0x09,0xD8,0x00,0x4F,0x10,0x31,0x18,0x52,0xCA,0x90,
++    0xC2,0x90,0x46,0xBC,0xC4,0xC0,0x41,0x94,0xCA,0xB0,0xE4,0x48,0x90,0x4D,0xD6,0x0C,
++    0x17,0x8A,0x9C,0x96,0xC8,0x0C,0x80,0x17,0xF0,0x6F,0x82,0x24,0x30,0x82,0xC9,0x0C,
++    0x82,0x17,0xF0,0x47,0x30,0x32,0x08,0x01,0x01,0x01,0x00,0x07,0x1A,0x99,0x0B,0xD8,
++    0x02,0x0F,0xE0,0x48,0x91,0x4D,0x16,0x21,0x18,0x52,0xCA,0x90,0xC4,0x90,0xCE,0x93,
++    0x57,0x79,0x80,0xB6,0x12,0x21,0x19,0x52,0xCE,0x90,0xC0,0x98,0x3E,0xF1,0xF8,0xFA,
++    0xDF,0x1C,0xC0,0xD8,0x98,0x1C,0x18,0xE9,0x0E,0xD8,0xC6,0x98,0x14,0x01,0xF0,0xD2,
++    0xDE,0x14,0xC0,0x90,0x92,0x14,0xE0,0x48,0x92,0x4D,0xE6,0x00,0x90,0x05,0xD6,0x44,
++    0x16,0x12,0xC4,0xDE,0xC8,0x44,0xC0,0x1C,0x80,0x17,0xF0,0xE7,0x30,0x3A,0xC8,0x44,
++    0xC0,0x14,0x80,0x17,0xF0,0xBF,0xC8,0x24,0xD8,0x48,0x8E,0x34,0xD0,0x80,0x81,0x2C,
++    0x08,0x01,0x10,0x01,0x00,0x77,0x00,0x01,0x33,0x5A,0x18,0x5A,0xF2,0x5C,0x00,0xD8,
++    0xC8,0xD8,0x04,0x1F,0x04,0x30,0x9A,0xD2,0xE6,0x00,0x92,0x05,0x17,0x42,0x9D,0xCE,
++    0xE6,0x48,0x92,0x4D,0x17,0x4A,0x9D,0x76,0x08,0x01,0x10,0x01,0x03,0xE7,0x19,0x99,
++    0x08,0xD8,0x02,0x0F,0xE6,0x48,0x92,0x4D,0x02,0x21,0x19,0x42,0xCC,0x00,0x30,0x22,
++    0xC0,0x00,0x86,0x3C,0xC8,0x03,0x44,0x79,0x80,0xA6,0x07,0x01,0x00,0x2F,0xD9,0x3C,
++    0x34,0xF1,0xF8,0xF2,0xD9,0x34,0x38,0xC9,0xC0,0xB0,0x1F,0x31,0x18,0x1A,0xCA,0xD8,
++    0x0E,0xF8,0xCD,0xD8,0x47,0xFC,0xDA,0xB0,0xAB,0x06,0x10,0xB2,0x95,0xB5,0x35,0xB2,
++    0x37,0xE9,0x08,0xB0,0x20,0x32,0x3B,0x01,0xF8,0xBA,0xF7,0x2C,0x45,0xDC,0xCC,0xF0,
++    0xD0,0x98,0xAF,0x06,0x10,0xDA,0x32,0xB2,0x18,0x72,0xFB,0x5C,0x07,0xB0,0xCB,0xB0,
++    0x22,0x9A,0x03,0x38,0x9A,0x9A,0xE7,0x00,0x90,0x05,0xDE,0x0C,0x16,0xC2,0x9C,0xB6,
++    0xE6,0x48,0x92,0x4D,0xE6,0x90,0x92,0x95,0xC0,0x64,0xC0,0x03,0x15,0x82,0xC4,0xF6,
++    0xC0,0x64,0xC8,0x0C,0xC4,0x03,0x10,0x42,0xC9,0x06,0x38,0xF7,0xC1,0x0C,0x38,0xE7,
++    0xAC,0x85,0x87,0x3D,0x34,0x22,0x00,0x91,0xD4,0x02,0x34,0x22,0x01,0xC1,0xF0,0x02,
++    0x18,0x71,0x80,0x34,0xF0,0x1A,0x9F,0x2C,0xD0,0x00,0x96,0x05,0x1F,0xD1,0xF0,0x1A,
++    0x2B,0x81,0xF8,0x2A,0x32,0xF2,0xDC,0xD8,0x90,0xDD,0xA8,0x24,0xC0,0x2B,0x6F,0x09,
++    0x8D,0x16,0x10,0x04,0x10,0x1C,0x07,0x6F,0x55,0x3C,0x05,0xE8,0xC7,0x68,0x51,0x04,
++    0x07,0x30,0xC4,0x98,0xD9,0x68,0x97,0x6D,0xD0,0xC0,0x90,0x1D,0x84,0x40,0x85,0xD8,
++    0x17,0x04,0x15,0x1C,0x4B,0x81,0x80,0xF6,0xE9,0x2C,0xC0,0x40,0x02,0x28,0xCA,0x00,
++    0xEA,0x34,0xC8,0x00,0x80,0x00,0x94,0x05,0xEF,0x24,0xC0,0x58,0x02,0xE8,0xCA,0xE8,
++    0x37,0x9A,0xC3,0x58,0x80,0xD8,0x94,0xED,0x90,0x01,0x46,0x01,0xD0,0x0E,0x00,0x01,
++    0x00,0x27,0x50,0x9C,0x10,0x1A,0xD4,0x0E,0x00,0x81,0xF0,0x82,0x68,0x01,0xD0,0x0E,
++    0x28,0x01,0x00,0x27,0x55,0x9C,0x12,0x5A,0xD0,0x0E,0x28,0x91,0xF8,0xAA,0xD2,0x2C,
++    0xD0,0x90,0xF0,0xB0,0xD2,0x06,0x10,0x92,0x06,0x98,0xC2,0xB8,0xD2,0x24,0xD8,0x90,
++    0xF0,0x98,0xD0,0x06,0x15,0x92,0xC2,0xF8,0x7E,0xD0,0xCF,0x90,0x18,0x90,0x66,0x90,
++    0x58,0x01,0xD0,0x06,0x12,0xDA,0x02,0xF8,0xC8,0xD8,0x76,0x01,0xD3,0x06,0x10,0xB2,
++    0xCE,0xD8,0x7C,0xF0,0xC6,0x98,0x1F,0xD8,0x60,0xF0,0x48,0x41,0x80,0x0E,0x48,0x49,
++    0x88,0x2E,0x48,0x49,0x8A,0x1E,0x20,0x88,0x63,0x50,0x20,0x88,0x63,0x70,0x30,0x0A,
++    0x8B,0x0C,0x28,0x12,0xCB,0x06,0x30,0x12,0xCC,0x0C,0x10,0x72,0xC8,0x06,0xF0,0x0C,
++    0xDB,0x2C,0x30,0x0A,0xD0,0x48,0x34,0x7A,0x1C,0xCA,0x02,0x58,0xC4,0x48,0x36,0x72,
++    0x19,0x51,0x30,0xCA,0xF3,0x1A,0x07,0xF8,0xCA,0x48,0x1E,0x5A,0x32,0x8A,0xC3,0xC8,
++    0x1B,0x82,0x32,0x12,0x46,0xB8,0xCA,0x00,0x02,0x00,0xC6,0x00,0x36,0x0A,0x03,0x48,
++    0x88,0x1C,0x80,0x17,0xE8,0xBF,0x80,0x14,0xD0,0x24,0xC0,0x0C,0xD8,0x00,0x34,0x0A,
++    0x1C,0x82,0x02,0x10,0xC0,0x00,0x14,0x61,0xF2,0x12,0x05,0x58,0xC2,0x48,0x1E,0x52,
++    0xC3,0x80,0x18,0xAA,0x00,0x07,0x00,0x67,0xCE,0x48,0x07,0x48,0xC0,0x40,0xC8,0x1C,
++    0x80,0x17,0xE8,0x07,0xCB,0x2C,0x08,0x0C,0xCD,0x24,0x08,0x0C,0xCF,0x14,0x08,0x0C,
++    0x10,0x04,0x81,0x3D,0xEF,0x85,0xAF,0xF5,0x30,0x3A,0xC0,0x44,0x60,0xD2,0xCF,0xE0,
++    0x2F,0x31,0x70,0xCA,0x1F,0xAA,0xC2,0x68,0xF5,0x21,0xC9,0x68,0x06,0x90,0xC2,0x90,
++    0x59,0xAA,0xDF,0x81,0xC6,0xB0,0xFE,0x13,0x31,0xB2,0x34,0xDA,0x32,0x3A,0xB8,0x01,
++    0x30,0x12,0xB8,0x0C,0x92,0x01,0xBE,0x01,0x59,0x09,0x88,0x4E,0x01,0x01,0x00,0x17,
++    0xC0,0x0B,0x49,0x79,0x89,0xE6,0x40,0x4C,0x0B,0x0C,0x47,0x5C,0x14,0x1C,0x31,0xE2,
++    0xC1,0x9B,0x89,0x1B,0xC3,0x9B,0x8B,0x1B,0x1B,0x0C,0x35,0x1A,0x19,0x1C,0x27,0x0C,
++    0x23,0x1C,0x0B,0x0C,0x09,0x1C,0x45,0x4C,0x1B,0x0C,0x41,0x4C,0x19,0x0C,0x83,0x03,
++    0x0F,0x09,0x80,0x0B,0x88,0x0B,0xFD,0x8B,0x90,0x0B,0x09,0x01,0x90,0x0B,0x03,0x27,
++    0xA2,0x21,0xE1,0x00,0x93,0x05,0x2E,0x82,0x9B,0xD6,0x2E,0x82,0x94,0xF6,0x03,0x2F,
++    0x1A,0x21,0x19,0xCA,0xC8,0x60,0x08,0x41,0x89,0x04,0x40,0x4C,0x18,0x0C,0x09,0x11,
++    0xF3,0x4A,0x1B,0x0C,0x35,0x62,0xCC,0x0B,0x48,0x09,0x88,0xAE,0x08,0xC1,0x18,0xE1,
++    0xF7,0x0A,0xF3,0x1A,0xD0,0x48,0xAE,0x06,0x14,0x4A,0x92,0x4D,0x30,0x72,0x1C,0xF1,
++    0xF3,0x1A,0x37,0x0A,0xD0,0x48,0xAE,0x06,0x14,0x4A,0x92,0x4D,0xE3,0xDB,0x21,0x8A,
++    0x10,0xCA,0xCC,0x0E,0x0D,0x01,0x88,0x0B,0x09,0xC1,0x18,0x01,0xF7,0x0A,0xF3,0x1A,
++    0xD0,0x48,0xAE,0x06,0x14,0x4A,0x92,0x4D,0x30,0x62,0x0C,0xD1,0x1B,0x11,0xF1,0x0A,
++    0xF6,0x1A,0xD7,0x48,0xAA,0x06,0x10,0x4A,0x24,0x0A,0x93,0x4D,0x30,0x62,0xDC,0x0C,
++    0xC4,0x0B,0xE7,0xDB,0xE4,0xD8,0x12,0xCA,0xC8,0x7E,0xF8,0x8B,0xEE,0xDB,0x01,0xCA,
++    0x28,0x0A,0xCB,0x56,0xD6,0x0B,0x4B,0x41,0x92,0x0E,0xE0,0x48,0x91,0x0B,0xD3,0x0B,
++    0xFC,0x9B,0x10,0xCA,0x92,0x0E,0xE0,0x48,0x91,0x0B,0xD1,0x0B,0x28,0x0A,0xCB,0xA6,
++    0xDF,0x0C,0xC0,0x0B,0xE2,0xDB,0xE4,0xD8,0x10,0xCA,0xCC,0x76,0xCA,0x0B,0x37,0x50,
++    0xE2,0xCB,0x73,0x90,0xF4,0x48,0x12,0x52,0x89,0x0E,0x08,0x01,0x80,0x0B,0x35,0x12,
++    0x09,0x81,0x30,0x02,0xBC,0xFF,0xF7,0xE7,0x00,0xDF,0xD8,0x0C,0xC4,0x0B,0xE7,0xDB,
++    0xE4,0xD8,0x12,0xCA,0xC8,0x1E,0xF8,0x8B,0xEE,0xD3,0x01,0x8A,0x91,0x0B,0x59,0x0C,
++    0x23,0x0C,0x59,0x0C,0x20,0x0C,0x33,0x12,0x30,0x02,0xC9,0x04,0xBC,0xFF,0xF7,0x47,
++    0x03,0x01,0x90,0x03,0xD0,0x03,0x41,0x01,0x80,0x1E,0x00,0x07,0x02,0x3F,0xF1,0x00,
++    0x97,0x03,0xC1,0x03,0x40,0xF9,0x93,0x0E,0xE7,0x00,0x82,0x03,0x43,0x44,0x15,0x04,
++    0x03,0x19,0x80,0x03,0xE4,0xC3,0x83,0x01,0x89,0x03,0xCF,0x03,0xC2,0x8B,0xD1,0x00,
++    0xE0,0x00,0x42,0x11,0xC3,0x2E,0xC8,0x03,0xC2,0x8B,0xD3,0x00,0xE0,0x00,0x42,0x11,
++    0xCF,0x4E,0xC0,0x03,0x40,0x11,0x98,0x36,0xCA,0x0C,0xE0,0x4B,0x10,0x42,0xC4,0x16,
++    0x07,0x01,0x80,0x03,0x89,0x03,0xC7,0x83,0x8B,0x03,0xC1,0x83,0x8F,0x03,0xEB,0xF5,
++    0xAC,0x85,0x37,0xE2,0x34,0x2A,0xAB,0x01,0x4A,0x5C,0x27,0xD8,0x67,0xE0,0x40,0xF9,
++    0x88,0x0E,0x00,0x01,0xE9,0x85,0x1F,0x21,0x1B,0xC2,0x5A,0xFA,0xC6,0x00,0xC4,0x00,
++    0x1A,0x31,0x18,0xCA,0xC3,0x48,0x54,0xE2,0xD4,0x21,0xC1,0x50,0x0A,0xA1,0xF0,0x0A,
++    0x48,0x01,0xD0,0x06,0x10,0x4A,0x1A,0xB1,0xF0,0x1A,0x5E,0x01,0xD2,0x06,0x10,0xDA,
++    0xC3,0x48,0x5E,0xB2,0x10,0xCA,0x9C,0x06,0x08,0x01,0x30,0x71,0x44,0x9C,0xF8,0x32,
++    0xD8,0xD8,0xAC,0x06,0x10,0xDA,0x32,0x81,0x44,0x94,0xFA,0x32,0xD8,0x90,0xAC,0x06,
++    0x14,0x92,0xC2,0xD0,0x11,0x12,0x9D,0x0E,0xC8,0x33,0x74,0x09,0x8B,0x26,0xE0,0x5B,
++    0xCA,0x3B,0xF6,0xD8,0x10,0xFA,0xDC,0xBE,0x70,0x09,0x88,0x3E,0xDC,0x5B,0x11,0x5A,
++    0x9E,0x26,0xC0,0x03,0x40,0xF1,0xC0,0x0E,0x40,0x51,0x90,0x6E,0x70,0x09,0x88,0x1E,
++    0x30,0x02,0x5B,0x04,0x40,0xC1,0x98,0x3E,0x70,0x09,0x88,0x16,0x04,0x00,0x13,0x82,
++    0xCD,0x16,0x00,0x00,0x10,0x82,0xC4,0x0E,0x07,0x01,0xE8,0x85,0x07,0x09,0xE8,0x85,
++    0xAC,0xFD,0x87,0x5D,0x30,0xB2,0x0C,0x01,0x28,0x01,0x00,0x01,0x80,0x14,0xC0,0xA4,
++    0xF8,0x23,0x06,0x01,0x30,0x22,0x84,0x34,0x00,0x27,0xD0,0x64,0x02,0xF9,0xA7,0x82,
++    0xE6,0x48,0x92,0x4D,0x17,0x0A,0x9D,0xC6,0xD3,0x74,0x28,0x92,0xC0,0x26,0xC0,0x74,
++    0x83,0x24,0x30,0x82,0x80,0x1C,0x00,0x1F,0x30,0x82,0x83,0x24,0xC0,0x74,0x80,0x1C,
++    0x00,0x01,0x80,0x2C,0x00,0xD7,0x1A,0x01,0x03,0xB7,0x32,0x02,0x06,0xC2,0x3E,0x00,
++    0x8A,0x86,0x42,0x32,0x80,0x3C,0x00,0x01,0xD0,0xA4,0xF0,0x5C,0xF8,0x93,0x90,0x54,
++    0x33,0xD2,0x18,0x12,0x05,0xB8,0xCA,0xD0,0x90,0x4C,0x00,0x6F,0xF6,0x34,0x00,0x32,
++    0x38,0x90,0x8F,0x3E,0xF2,0x4C,0x00,0x38,0xD8,0xB2,0xFF,0x3C,0x10,0xF2,0x95,0x0E,
++    0xB0,0x3C,0x30,0x0A,0xE6,0x00,0x92,0x05,0xD4,0x54,0x10,0x12,0xC1,0x76,0x77,0xBA,
++    0x02,0x01,0x00,0x78,0xB8,0x44,0x00,0x87,0x36,0x3A,0x03,0x3A,0x38,0xF8,0x8F,0x56,
++    0x33,0x3A,0x18,0x3A,0xD3,0x5C,0x00,0xF8,0xC0,0xF8,0xD5,0x44,0xD5,0xFA,0x15,0xBA,
++    0xC1,0x0E,0x30,0xF2,0x32,0x2A,0xE0,0x00,0x93,0x05,0x2E,0x82,0x9C,0x66,0x17,0xEA,
++    0x88,0xA6,0xC0,0x14,0xC8,0x00,0x84,0x14,0xC2,0x2C,0xE0,0x00,0x90,0x05,0x86,0x2C,
++    0xC2,0x64,0xA0,0x2A,0x31,0x09,0x30,0x82,0xD4,0x34,0x00,0x42,0x1C,0x82,0x90,0x05,
++    0x85,0x34,0x00,0x72,0x30,0x02,0x1B,0x32,0x94,0x85,0x35,0x22,0xD0,0x24,0xC0,0x2C,
++    0x10,0x82,0x84,0x1E,0xE6,0xD8,0x92,0xDD,0x2D,0x9A,0x9B,0x36,0xD0,0x24,0xC0,0x2C,
++    0x15,0x82,0x9C,0x06,0xC0,0x14,0x80,0x3C,0x10,0x01,0x00,0x01,0x0B,0x01,0x30,0x5A,
++    0x80,0xCB,0x18,0x01,0x0C,0x01,0x30,0x62,0x30,0x4A,0xE3,0x4A,0x02,0x0F,0xE0,0x48,
++    0x90,0x4D,0x36,0xEA,0x07,0x6A,0x3E,0x68,0x88,0xCE,0xEF,0x1C,0x10,0x4A,0x9D,0xFE,
++    0x40,0x01,0x88,0x8E,0x08,0xF9,0x07,0x5F,0xD0,0x64,0xE0,0x9A,0x28,0x9A,0x93,0x1E,
++    0xD0,0xA4,0xF8,0x93,0x10,0x12,0xC4,0x0E,0xD0,0x64,0xA0,0x8A,0xE6,0x00,0x92,0x05,
++    0x17,0x02,0x9D,0x8E,0x87,0x7D,0xE8,0x85,0xF6,0x00,0x92,0x05,0x30,0x4A,0xE3,0x4A,
++    0x2D,0x09,0x30,0x62,0x00,0x6F,0x01,0x00,0x70,0x30,0x03,0x00,0xF8,0xFF,0x07,0x00,
++    0x33,0x6A,0x18,0x2A,0xFB,0x5C,0x00,0x70,0xCA,0xB0,0x07,0x38,0xDD,0xAA,0xC7,0x50,
++    0x2C,0x09,0x00,0x6A,0x1D,0xEA,0x90,0x5D,0x31,0x72,0xA3,0x8A,0xED,0x3C,0x10,0x52,
++    0x98,0x16,0x28,0x11,0x30,0x62,0x05,0xA7,0xFA,0x74,0xE0,0x28,0x10,0xEA,0x9D,0x6E,
++    0x90,0x3C,0x08,0x01,0x00,0x27,0xF8,0x64,0xE3,0xAA,0xA3,0xEA,0xE6,0x48,0x92,0x4D,
++    0x17,0x0A,0x9D,0xC6,0xE0,0x8A,0x29,0x09,0x30,0x62,0x05,0x17,0x90,0x45,0x2F,0x01,
++    0xA3,0xAA,0x31,0x2A,0x6D,0x01,0x80,0x2E,0x33,0x6A,0x18,0x2A,0xFB,0x5C,0x00,0x70,
++    0xCA,0xB0,0x07,0x38,0xDA,0xAA,0xDF,0x90,0x2C,0x09,0x00,0x6A,0x1B,0x5A,0x35,0x6A,
++    0xE2,0x4A,0xE1,0x48,0xA4,0x4A,0x39,0xAF,0xAC,0xC5,0x37,0x22,0xFC,0x73,0x5E,0xAA,
++    0x36,0x02,0xC3,0x00,0x31,0x32,0x34,0xAA,0x38,0x21,0x31,0x62,0x1A,0xEA,0xA3,0x01,
++    0x13,0x01,0x20,0x2A,0xC0,0x68,0x07,0xF7,0xC0,0x1B,0x58,0x79,0x86,0xD6,0xC8,0x1B,
++    0x30,0xD8,0xA0,0x3E,0x18,0xF9,0x8F,0x1B,0x8E,0x1B,0xC2,0x1B,0xE5,0x3B,0x15,0xDA,
++    0xC6,0x06,0x88,0x13,0xCA,0x1B,0x36,0xD8,0x76,0xD8,0x8A,0x1B,0x58,0x01,0x80,0x0E,
++    0xF6,0xD8,0x8A,0x1B,0xC8,0x1B,0x5E,0x01,0x8A,0x26,0xC0,0x1B,0x44,0xD8,0x04,0xD8,
++    0x84,0x1B,0x82,0x13,0x84,0x21,0x11,0x2A,0xC0,0xF6,0x06,0x01,0x84,0x04,0xB8,0x53,
++    0x30,0x82,0x03,0x8F,0xC5,0x13,0x10,0x92,0x96,0x5E,0xC0,0x13,0xE2,0x3B,0x35,0x98,
++    0x75,0xD8,0x12,0xDA,0xCC,0x2E,0xC0,0x13,0x50,0x01,0x81,0x16,0x00,0x09,0x80,0x04,
++    0x00,0x27,0x10,0x01,0x81,0x13,0x84,0x21,0x17,0x2A,0xC4,0x5E,0xC0,0x04,0x40,0x01,
++    0x83,0x76,0x31,0x92,0x36,0x5A,0x98,0x01,0x00,0x47,0x01,0x01,0x80,0x83,0xC4,0x83,
++    0x11,0x82,0x95,0x16,0xC2,0x83,0x36,0x38,0xE3,0x03,0x75,0xF8,0x10,0x3A,0xCC,0xE6,
++    0x04,0x09,0x80,0x83,0xFA,0x43,0xE4,0x00,0xB8,0x43,0x3C,0x71,0xF8,0xBA,0x7E,0x01,
++    0xD0,0x16,0x00,0x01,0x08,0x84,0x06,0x27,0x54,0xC4,0x10,0x3A,0xE8,0x0E,0x50,0xC4,
++    0x08,0x84,0x3E,0x81,0xF8,0xBA,0x7E,0x01,0xD0,0x16,0x00,0x01,0x10,0x84,0x00,0x27,
++    0x54,0xC4,0x12,0x3A,0xEA,0x0E,0x50,0xC4,0x11,0x84,0x90,0x21,0x16,0xAA,0xC4,0xA6,
++    0xF8,0x43,0x40,0x01,0x88,0x36,0x58,0x44,0x16,0xE9,0x03,0x90,0x10,0x82,0x94,0x0E,
++    0xE0,0x00,0x1A,0x44,0xF8,0x43,0x44,0x01,0x80,0xCE,0x10,0x01,0x03,0x01,0x28,0x99,
++    0x0E,0x68,0xFB,0x63,0x01,0x6F,0x18,0x21,0x1B,0x1A,0x22,0x1A,0xC8,0xD8,0xD2,0xF3,
++    0x70,0x09,0x88,0x26,0xC8,0xDB,0x5E,0x19,0x8A,0x0E,0xE0,0x90,0x92,0x95,0xE6,0x00,
++    0x94,0x05,0x16,0x22,0xC0,0x7E,0x57,0x01,0x88,0x0E,0x00,0x01,0x1F,0x44,0xE8,0xC5,
++    0xAC,0x85,0x87,0x3D,0x30,0x2A,0x30,0x62,0x41,0x12,0xC2,0x40,0x08,0x29,0xEE,0x4A,
++    0x4B,0x29,0x80,0xDE,0x4B,0x02,0xC2,0x70,0xEB,0x48,0xC4,0x48,0x89,0x1C,0x48,0xF2,
++    0x8B,0x61,0xC0,0x48,0x88,0x14,0x08,0x01,0x10,0xF9,0x1F,0x79,0x03,0x3F,0xA0,0x92,
++    0xC8,0x3B,0x7E,0x01,0x88,0x06,0x80,0x1B,0xE6,0x48,0x92,0x4D,0x87,0x21,0xF9,0x3B,
++    0x17,0x7A,0xC4,0xA6,0x00,0x01,0x80,0x34,0xF8,0x03,0x41,0x01,0x80,0xCE,0xB2,0x04,
++    0x31,0x0A,0x31,0x42,0x58,0x2D,0xD0,0x14,0xBA,0xFF,0xDF,0x97,0x80,0x34,0xC0,0x34,
++    0x40,0x01,0x88,0x76,0x30,0x01,0x00,0x47,0x31,0x5A,0x31,0x92,0x08,0xF9,0x07,0x09,
++    0xA7,0x04,0xB8,0xFF,0xE3,0x47,0xE7,0xB0,0x91,0xB5,0xFF,0x03,0x17,0x82,0xC5,0x9E,
++    0x00,0xFF,0xC1,0x34,0x40,0x09,0x88,0x96,0xC1,0xB3,0x31,0x1A,0x30,0x52,0x09,0x01,
++    0x37,0x82,0xB9,0xFF,0xE8,0x2F,0x46,0x01,0x80,0x0E,0x00,0x01,0x00,0x07,0x00,0x09,
++    0x30,0x5A,0x11,0x01,0x30,0x8A,0xA1,0x04,0xBE,0xFF,0xE7,0x6F,0x00,0x4F,0xA1,0x04,
++    0xFB,0x3B,0x31,0x5A,0xE9,0xD3,0x30,0xDA,0xC8,0x1C,0xC0,0x14,0xB8,0xFF,0xF7,0x47,
++    0x38,0x01,0x00,0xDF,0xC6,0x1C,0xE8,0x02,0x40,0xF9,0x87,0x16,0xE0,0x82,0x81,0x24,
++    0x07,0x0F,0x00,0xF9,0x81,0x24,0x30,0x1A,0x31,0x52,0x31,0xCA,0xC7,0x24,0xB8,0xFF,
++    0xE8,0xFF,0x44,0x01,0x80,0x0E,0x00,0x01,0x00,0x07,0x00,0x09,0x31,0x5A,0x31,0xD2,
++    0xA0,0x04,0xC8,0x24,0xBD,0xFF,0xE7,0x3F,0xE7,0xF8,0x93,0xFD,0xFD,0x03,0x11,0xC2,
++    0xC1,0x06,0x37,0x0A,0x30,0x42,0xD1,0x34,0xBE,0xFF,0xF7,0xB7,0x20,0xCF,0x04,0x01,
++    0x38,0x82,0x03,0x00,0x70,0x30,0x03,0x00,0x48,0xE0,0x06,0x00,0xAE,0xFD,0x87,0x5D,
++    0xC6,0xAC,0xDA,0x03,0x82,0xCC,0xC1,0xAC,0xD9,0x03,0x84,0xC4,0x01,0x09,0x58,0x45,
++    0x81,0xC3,0xC0,0xC4,0xE2,0x00,0x82,0xC3,0xC4,0xC4,0x81,0xC3,0xC2,0xC4,0xF1,0x00,
++    0x82,0xC3,0xC6,0xAC,0x82,0x01,0x87,0x54,0xC0,0x0B,0x00,0x21,0x1A,0x0A,0xC0,0x54,
++    0x82,0x0B,0xC0,0xAC,0xCA,0x03,0x42,0x00,0x80,0xD4,0x09,0x01,0x40,0xB5,0x31,0x52,
++    0x00,0x36,0x00,0x01,0x82,0xF4,0xC0,0xAC,0xCC,0xB4,0x82,0x01,0x82,0x4C,0xC2,0x74,
++    0x92,0x05,0x82,0x44,0xC2,0x6C,0x92,0x05,0x82,0x3C,0xC2,0xAC,0x82,0x01,0x86,0x34,
++    0x4B,0x11,0x80,0xBE,0x10,0x01,0x00,0x01,0x4C,0x45,0xB1,0x4A,0x8F,0x2C,0x4A,0xF2,
++    0xB2,0x4A,0x8C,0x24,0x48,0xE2,0xEF,0x48,0xB2,0x4A,0x8C,0x1C,0x04,0x08,0xC4,0x48,
++    0x91,0x4D,0x66,0x9D,0xDB,0x74,0xA2,0x1A,0x62,0x85,0xD9,0x6C,0xA2,0x1A,0xDB,0x24,
++    0x9A,0x34,0xD9,0x1C,0x9A,0x2C,0xD9,0x2C,0x98,0x24,0x41,0x09,0x89,0x5E,0xD8,0x34,
++    0x12,0xDA,0x92,0xDD,0x99,0x34,0xD9,0x2C,0x12,0xDA,0x92,0xDD,0x99,0x2C,0xD9,0x24,
++    0x12,0xDA,0x92,0xDD,0x9A,0x24,0xD9,0x5C,0x32,0xE2,0xDC,0x64,0x9A,0x5C,0xD9,0x3C,
++    0xE1,0x44,0xEA,0x2C,0xCA,0xD8,0x92,0xDD,0xEB,0x34,0xC9,0x20,0x91,0x25,0xF3,0x24,
++    0xED,0x5C,0xC9,0x68,0xA8,0x5C,0x59,0x01,0xD9,0x86,0xEB,0xCC,0x13,0x5A,0xD5,0x6E,
++    0x63,0x01,0xD8,0x5E,0xED,0xC4,0x11,0x62,0xD1,0x46,0xEB,0x5C,0xC5,0x6B,0x49,0x68,
++    0x8B,0x06,0x32,0x2A,0x3F,0x01,0xF8,0x7A,0xEB,0x24,0x01,0x68,0x23,0x62,0x35,0x32,
++    0x2B,0x01,0xF8,0xAA,0xF5,0xD4,0x11,0xAA,0xEA,0xC6,0xF2,0xB4,0x71,0x09,0x88,0x16,
++    0xD9,0xF0,0x93,0xB5,0xB2,0x9C,0xF8,0x5C,0x35,0x01,0xF8,0xF2,0x10,0x72,0xDD,0x06,
++    0x37,0xAA,0x81,0x68,0x01,0x68,0x33,0x7A,0xF3,0x9C,0x10,0x6A,0x12,0xAA,0xE5,0x2E,
++    0x6B,0x9D,0xA1,0x62,0x6B,0x85,0xA1,0x5A,0x01,0xA8,0x72,0xB5,0xC9,0x68,0xE5,0x72,
++    0xE1,0xB0,0xA3,0x72,0xEB,0xF4,0xE0,0x68,0x90,0x6D,0xAF,0xF4,0xF5,0x9C,0x10,0xBA,
++    0xD1,0xBE,0x05,0x9F,0x09,0xEF,0x6A,0x9D,0xA1,0x62,0x6B,0x85,0xA2,0x5A,0x03,0xA8,
++    0x75,0xB5,0xC9,0x68,0xE3,0x72,0xE1,0xB0,0xA0,0x72,0xE9,0xF4,0xE7,0x68,0x93,0x6D,
++    0xAD,0xF4,0x38,0x37,0xE9,0x5C,0xC1,0x6B,0x48,0x68,0x6D,0x19,0x8A,0x6E,0x00,0xB0,
++    0x7F,0xB5,0xC9,0xB0,0xE0,0xB2,0x71,0x09,0xC2,0x3E,0xC0,0x64,0x08,0x01,0xC6,0x03,
++    0x1A,0x42,0xC8,0x64,0x82,0x43,0x80,0x7D,0xE8,0x85,0x6F,0x11,0x89,0x56,0x68,0x9D,
++    0xA1,0x62,0x63,0x85,0xA2,0x1A,0x03,0x98,0x4A,0xB5,0xC1,0xC8,0xE2,0x5A,0xE0,0xD8,
++    0xA0,0x5A,0x00,0x1F,0xCE,0x34,0xCA,0x4B,0x4F,0x51,0x90,0x66,0xE6,0x00,0x92,0x05,
++    0x40,0x11,0x90,0x06,0x3A,0xD7,0xE2,0x90,0x90,0x95,0x56,0x21,0x92,0x06,0x38,0x57,
++    0x01,0x01,0x80,0x64,0xC0,0xB4,0x42,0x09,0x88,0xF6,0x03,0x01,0x80,0x7C,0x01,0x01,
++    0x81,0x74,0xC9,0x7C,0x42,0xB5,0x01,0x48,0xC2,0x40,0x80,0x14,0xC1,0x74,0xC9,0x7C,
++    0x02,0x00,0xC4,0x00,0x91,0x05,0x86,0x4C,0xCA,0x74,0xC1,0x14,0xE0,0x2A,0x6A,0x09,
++    0xC1,0x26,0xC0,0x64,0xE6,0x00,0x92,0x05,0x87,0x64,0x01,0x8F,0xC0,0x74,0x41,0x09,
++    0x89,0x16,0xC0,0x7C,0x47,0x01,0x88,0xC6,0x08,0x81,0x41,0x45,0x83,0x17,0xC0,0x77,
++    0xC0,0x6C,0x82,0x3C,0xC0,0x74,0x82,0x34,0xC0,0x5C,0x82,0x0C,0xC0,0x64,0x82,0x04,
++    0xC4,0x7C,0xE1,0x00,0x3C,0x00,0x7C,0x00,0x50,0x5A,0xB4,0xA2,0xE8,0x98,0xB0,0xCA,
++    0x31,0x62,0x74,0x45,0xB1,0x8A,0xC1,0x7C,0xB0,0x82,0x80,0x24,0xC0,0x7C,0xB1,0xC2,
++    0x81,0x1C,0xD0,0x7C,0xB0,0x82,0x85,0x14,0xC0,0x74,0x41,0x09,0x88,0x5E,0xC0,0x24,
++    0x12,0x02,0x92,0x05,0x80,0x24,0xC0,0x1C,0x12,0x02,0x92,0x05,0x80,0x1C,0xC0,0x14,
++    0x12,0x02,0x92,0x05,0x80,0x14,0x00,0x01,0x83,0x2C,0xE0,0x68,0xAD,0xF4,0x01,0x9F,
++    0x40,0x61,0x98,0x66,0xC8,0x24,0xC0,0x34,0xD2,0x4C,0xD1,0x00,0x4C,0x9D,0xA1,0x42,
++    0xC8,0x1C,0xC0,0x3C,0xD2,0x4C,0xD1,0x00,0x4C,0x85,0xA1,0x42,0x00,0x47,0x15,0x01,
++    0xDC,0x0C,0x00,0x28,0xF0,0xD2,0x5C,0x45,0x88,0xD2,0x12,0x01,0x90,0x6C,0xD1,0x3C,
++    0x92,0x95,0x92,0x0C,0xD2,0x34,0x90,0x95,0x91,0x04,0xD2,0x6C,0x50,0x09,0x88,0x3E,
++    0x12,0x12,0x93,0xA5,0x32,0x12,0x13,0x92,0x94,0x95,0x32,0xA2,0x12,0x4A,0x92,0x4D,
++    0xD2,0x0C,0xDA,0x04,0xF0,0x0C,0x00,0x07,0x01,0xEF,0xB4,0x1C,0xF1,0x04,0xB0,0x5C,
++    0x01,0x70,0xB2,0xFC,0x22,0x12,0x93,0x95,0xCA,0xD8,0x90,0xDD,0xF9,0x1C,0xF1,0xFC,
++    0xC9,0xB0,0xB7,0x1C,0xF3,0x5C,0xC1,0xB0,0xB0,0x5C,0x51,0x01,0xD9,0xBE,0xF0,0xCC,
++    0x10,0x92,0xD5,0xA6,0x58,0x01,0xD8,0x96,0xF5,0xC4,0x11,0x9A,0xD1,0x7E,0xF8,0x1C,
++    0x35,0x01,0xF8,0xF2,0xF9,0x5C,0xC1,0xFB,0x48,0xF8,0x8D,0x46,0xFD,0xD4,0x11,0xF2,
++    0xE8,0x2E,0x78,0x45,0xCD,0xFA,0xCB,0xF0,0x7B,0x45,0x88,0xF2,0x39,0xD7,0xD6,0x6C,
++    0xE6,0x90,0x92,0x95,0x91,0x6C,0xD1,0x6C,0x55,0x11,0x98,0xF6,0x41,0x01,0x80,0xF6,
++    0xF2,0x10,0xF2,0x4C,0x00,0x90,0x5C,0x45,0xC7,0xD2,0xD4,0xB3,0xCC,0xDA,0xCA,0xB0,
++    0x11,0xF2,0x94,0x86,0xD0,0x2C,0x50,0x09,0x88,0x8E,0xD1,0x24,0xC1,0x34,0xD8,0x4C,
++    0xD1,0x00,0x54,0x9D,0xA0,0x82,0xDE,0x1C,0xD1,0x3C,0xE8,0x4C,0xD1,0x90,0x5E,0x85,
++    0xA8,0xD2,0xEA,0x14,0xDA,0x04,0xD8,0xE8,0x36,0x1A,0xD3,0x90,0x90,0x95,0xDA,0x00,
++    0x93,0x1D,0xD2,0x40,0x2C,0x01,0x38,0x01,0x50,0x01,0xD8,0x56,0xF5,0xCC,0x11,0x92,
++    0xD0,0x3E,0x58,0x01,0xD9,0x2E,0xF0,0xC4,0x10,0x9A,0xD5,0x16,0xC1,0x33,0x18,0xF2,
++    0x83,0x33,0x20,0x12,0x90,0x95,0xCA,0xD8,0x92,0xDD,0xC2,0x00,0xE7,0x68,0x93,0x6D,
++    0x6F,0x11,0xC8,0x4E,0x04,0xE7,0x10,0x9A,0x90,0x0E,0x10,0x09,0x90,0x2C,0xD8,0x24,
++    0xD6,0x34,0xC0,0x90,0x90,0x95,0x96,0x34,0xD8,0x1C,0xD0,0x3C,0xC6,0x90,0x96,0x95,
++    0x90,0x3C,0xD0,0x14,0xDA,0x0C,0x00,0x90,0xC0,0x90,0x96,0x0C,0xD8,0x14,0xD0,0x04,
++    0xC0,0x90,0x96,0x04,0xE6,0x00,0x92,0x05,0xD4,0xF4,0x11,0x82,0x92,0x06,0x38,0x3F,
++    0xC2,0x74,0xE1,0x00,0x91,0x05,0x86,0x74,0xC0,0x74,0x41,0x11,0x97,0x06,0x30,0xAF,
++    0xC2,0x7C,0xE1,0x00,0x91,0x05,0x86,0x7C,0xC0,0x7C,0x41,0x21,0x97,0x06,0x30,0x37,
++    0x00,0x0F,0x00,0x41,0x81,0x64,0xC1,0x64,0x41,0x41,0x88,0xD6,0x10,0x01,0x00,0x01,
++    0x58,0x8A,0xE8,0xC8,0xB4,0xF2,0xB4,0x7A,0x31,0x8A,0x31,0xDA,0x40,0x09,0x88,0x1E,
++    0x12,0x4A,0x92,0x4D,0x12,0xDA,0x92,0xDD,0xE7,0x6C,0xC2,0x18,0x92,0xDD,0xE2,0x74,
++    0xC2,0x08,0x93,0x65,0x04,0x08,0xC4,0x48,0x90,0x4D,0x5E,0x01,0xD9,0x76,0xE8,0xCC,
++    0x10,0x5A,0xD5,0x5E,0x60,0x01,0xD8,0x4E,0xED,0xC4,0x11,0x62,0xD1,0x36,0x68,0x9D,
++    0xA1,0x62,0x63,0x85,0xA0,0x1A,0x03,0x3F,0x70,0x92,0x07,0x00,0x62,0x9D,0xD9,0x74,
++    0xA1,0x1A,0x63,0x85,0xDB,0x6C,0xA2,0x1A,0xE6,0x00,0x92,0x05,0x46,0x11,0x98,0x9E,
++    0xE6,0x90,0x92,0x95,0x56,0x21,0x98,0x56,0x58,0x85,0xD9,0xC3,0xA8,0xC3,0xC0,0xC3,
++    0x90,0xC3,0x00,0x01,0x81,0xFC,0x58,0x85,0xD8,0xC3,0xA8,0xC3,0xC0,0xC3,0x90,0xC3,
++    0x00,0x01,0x80,0xE4,0x30,0x3A,0x80,0xEC,0xC4,0xAC,0xCA,0x03,0x80,0xD4,0x01,0x01,
++    0x0E,0x01,0x00,0x18,0x54,0xA5,0xC0,0xD0,0x32,0xA2,0x04,0x20,0xC6,0x10,0x93,0x95,
++    0x6D,0x9D,0xE1,0x72,0x33,0x2A,0xA3,0x72,0x6D,0x85,0xE1,0x6A,0x32,0x12,0xC3,0x90,
++    0x8A,0xAB,0xE0,0x48,0x90,0x4D,0x4E,0x19,0x98,0x86,0x47,0x09,0x80,0x0E,0x40,0x19,
++    0x88,0x66,0x60,0xA5,0xE3,0x0A,0x37,0x12,0xCB,0x93,0x30,0x2A,0xC7,0x6B,0xA5,0x2A,
++    0x34,0x1A,0xCB,0xE3,0x8C,0xE3,0x80,0xCB,0x34,0x0A,0x8B,0x53,0x09,0x09,0x88,0x0C,
++    0x09,0x01,0x88,0x74,0xD3,0x74,0x31,0x0A,0xE1,0x4A,0xDC,0x74,0x36,0x12,0xC3,0x90,
++    0xCA,0x9B,0xC0,0xAB,0xC9,0x93,0x92,0x14,0xD0,0x74,0x51,0x01,0x88,0x16,0x41,0x01,
++    0x80,0x0E,0x40,0x19,0x8D,0x5E,0x10,0x4A,0x98,0x4E,0x10,0x09,0x90,0x04,0x41,0x01,
++    0x8A,0x16,0xF0,0x10,0x90,0x0C,0x01,0xF7,0x11,0x09,0x90,0x0C,0x00,0xDF,0x40,0x09,
++    0x80,0x0E,0x40,0x11,0x8D,0x5E,0x10,0x4A,0xC0,0x4E,0x10,0x09,0x90,0x04,0x41,0x09,
++    0x8C,0x16,0xF0,0x10,0x90,0x0C,0x01,0x77,0x11,0x09,0x90,0x0C,0x00,0x5F,0x10,0x01,
++    0x90,0x04,0x01,0x47,0x11,0x09,0x90,0x04,0x40,0x11,0x90,0x16,0xF1,0x90,0x94,0x0C,
++    0x00,0x0F,0x10,0x09,0x90,0x0C,0x41,0x01,0x80,0x0E,0x40,0x19,0x8D,0x0E,0x10,0x4A,
++    0x90,0x2E,0x40,0x09,0x80,0x0E,0x40,0x11,0x8D,0x26,0x10,0x4A,0xC0,0x16,0x10,0x09,
++    0x94,0x54,0x01,0x8F,0x11,0x01,0x90,0x54,0x01,0x77,0xF4,0xC4,0x33,0x12,0x19,0x92,
++    0xF1,0xA4,0x92,0xE4,0xC9,0x90,0xF4,0xEC,0xC9,0x90,0x94,0x5C,0xD0,0x5C,0xC1,0x93,
++    0x92,0xDC,0x31,0x90,0xA1,0xCE,0xD1,0xE4,0xF2,0xA4,0x02,0x90,0xC9,0x90,0xF4,0x3C,
++    0x04,0xB0,0xCB,0x90,0x35,0x39,0x09,0xB0,0xC8,0xB0,0x14,0xE1,0xF1,0x92,0xF5,0xD4,
++    0x10,0x92,0xD5,0x26,0xF0,0x64,0x71,0x41,0x88,0xB6,0x50,0x01,0xD9,0xA6,0xF0,0xDC,
++    0x48,0xB0,0x87,0x06,0x80,0x90,0xF2,0xE4,0xC0,0xB0,0xB5,0xE4,0xF2,0x3C,0x19,0xB2,
++    0xC8,0xB8,0xF7,0xEC,0x1C,0x12,0xCB,0x90,0x90,0xEC,0xD0,0xFC,0xE4,0x90,0x92,0x95,
++    0x91,0xFC,0xD0,0xDC,0x48,0x90,0x8E,0xEE,0xD0,0x4C,0xF2,0xF4,0xD5,0x93,0x12,0x92,
++    0xC1,0x2E,0xD0,0xDC,0x31,0x01,0x1E,0x92,0xF1,0x5C,0x81,0x93,0x01,0x47,0xD0,0xDC,
++    0x31,0x01,0x1A,0x92,0xF1,0x5C,0x81,0x93,0x01,0x17,0xD0,0x04,0x50,0x09,0x80,0x4E,
++    0xD0,0x04,0x51,0x09,0x8A,0x36,0xD0,0x6C,0x10,0xA2,0x84,0x1E,0xD5,0x0C,0xC1,0x10,
++    0x95,0xA5,0x3A,0x57,0x10,0x4A,0x8D,0xDE,0xD4,0x14,0x11,0x9A,0x89,0xC6,0xC8,0x74,
++    0xE6,0x48,0x92,0x4D,0x89,0x74,0xC9,0x74,0x48,0x11,0x90,0x06,0x3A,0x97,0xE2,0x00,
++    0x90,0x05,0x46,0x21,0x91,0x06,0x38,0x1F,0xC6,0x34,0xCA,0x03,0x42,0x01,0x88,0x5E,
++    0xC9,0xAC,0x8A,0x01,0xE0,0x43,0x36,0x10,0xAA,0x36,0x31,0x00,0x71,0x00,0x04,0x27,
++    0xD0,0x54,0x51,0x01,0x8D,0x5E,0x10,0x4A,0xCA,0x16,0xF0,0x48,0x90,0x4D,0x06,0x1F,
++    0x10,0x4A,0x95,0x0E,0xE6,0x48,0x92,0x4D,0x11,0x09,0x90,0x54,0x01,0x67,0xD0,0x14,
++    0x10,0x9A,0xCC,0x16,0xF6,0xD8,0x92,0xDD,0x01,0x27,0xD0,0x14,0x10,0x9A,0x94,0x0E,
++    0xE6,0xD8,0x92,0xDD,0x11,0x01,0x90,0x54,0x91,0x55,0x92,0x3C,0x97,0xE5,0x72,0xFA,
++    0xD4,0x3C,0xC9,0x90,0x93,0xEC,0x39,0x47,0x02,0x01,0xD0,0xAC,0x6C,0x94,0x16,0x12,
++    0x9A,0xD6,0xC0,0xAC,0xE8,0x4B,0x70,0x04,0x10,0x42,0x9C,0x26,0xC4,0x4C,0xD2,0x03,
++    0xF6,0x00,0x94,0x05,0x02,0x1F,0xC0,0x4C,0xD4,0x03,0xE4,0x00,0x90,0x05,0xCE,0xFC,
++    0x10,0x0A,0x9C,0x4E,0xC0,0xAC,0x0A,0x01,0xBA,0x0B,0xC0,0x54,0x08,0xD9,0xC7,0x03,
++    0x02,0x42,0xC8,0x54,0x82,0x43,0x28,0x37,0x27,0x01,0x28,0xF9,0xA8,0x09,0x60,0x01,
++    0x8A,0x56,0xC0,0x44,0xC8,0xC4,0xB9,0x9C,0xD2,0x34,0x4A,0x93,0x92,0x94,0xD0,0x74,
++    0x5A,0x3A,0x07,0x90,0xF0,0xF2,0x04,0x57,0xC1,0x3C,0xCA,0xCC,0xD0,0xEC,0x90,0x9C,
++    0xD4,0x34,0x4A,0x93,0x92,0x94,0xD0,0x6C,0x5A,0x12,0x07,0x90,0xF0,0xF2,0x44,0x01,
++    0x82,0x16,0xF0,0x48,0x10,0x42,0x8C,0x8E,0xD0,0x74,0x92,0x04,0x91,0x05,0x36,0x0A,
++    0xDA,0x6C,0xD2,0x5C,0xBB,0xEF,0xD7,0x47,0x35,0x4A,0x11,0x42,0xE8,0x0E,0x30,0x42,
++    0x00,0x17,0x40,0x01,0xD0,0x06,0x00,0x01,0xC8,0x30,0x04,0x07,0xB0,0x01,0xC4,0x9C,
++    0xC8,0xE4,0x10,0x00,0x86,0x0F,0xE8,0x27,0xCC,0x94,0xC8,0x00,0x18,0x42,0x42,0x01,
++    0xD0,0x06,0x00,0x01,0xA0,0x00,0x60,0x01,0x8A,0x7E,0xC8,0x34,0x54,0x4C,0x10,0x0A,
++    0xD0,0x06,0x30,0x42,0xC8,0xAC,0x12,0x31,0xFA,0x4B,0x18,0x8A,0xD4,0xA4,0xC2,0x48,
++    0x14,0xC9,0x09,0x90,0xC2,0x48,0x04,0x44,0x02,0x77,0xC8,0x34,0x54,0x4C,0x12,0x0A,
++    0xD0,0x06,0x30,0x42,0xC8,0xAC,0x12,0x31,0xFA,0x4B,0x18,0x8A,0xD4,0xA4,0xC2,0x48,
++    0x14,0xC9,0x09,0x90,0xC4,0x48,0x04,0x44,0xE7,0x20,0x93,0x25,0x64,0x09,0xC8,0xF6,
++    0xC0,0xAC,0x12,0x31,0xE0,0x0B,0xC2,0xE4,0x02,0x42,0xCE,0xAC,0xFA,0x4B,0x18,0x8A,
++    0xD4,0xA4,0xC2,0x48,0x14,0xC9,0x09,0x90,0xC6,0x48,0x04,0x44,0xC2,0xAC,0xCA,0x74,
++    0xFA,0x03,0x00,0x10,0xC0,0xA4,0xC2,0x90,0x02,0x89,0x0B,0x00,0xC4,0x90,0xA8,0x8B,
++    0xCA,0xAC,0xD2,0x6C,0xFA,0x4B,0x00,0x58,0xCA,0xA4,0xC2,0xC8,0xC6,0x40,0xA8,0x13,
++    0xC2,0xAC,0xCA,0xAC,0xFA,0x03,0xE0,0x00,0xBD,0x43,0x20,0xE7,0xAC,0xFD,0x87,0xBD,
++    0xEC,0x04,0x31,0xA2,0xD8,0x43,0x87,0x84,0xD8,0x43,0x85,0x7C,0xC8,0x43,0x81,0x74,
++    0x00,0x01,0x80,0x54,0x42,0x22,0x45,0x0B,0x36,0x42,0x81,0x01,0x80,0xB4,0x48,0x01,
++    0x80,0x1E,0xC0,0x74,0x40,0x00,0x82,0x5C,0x00,0x67,0xC0,0xB4,0xC8,0x03,0x46,0x51,
++    0x98,0x26,0xC8,0xB4,0x00,0x49,0xB0,0x42,0x80,0x5C,0x00,0x1F,0xC0,0xB4,0x08,0x41,
++    0xB0,0x0A,0x8A,0x5C,0x40,0xCA,0xD4,0xD4,0xC8,0xBC,0xC0,0x80,0x80,0xAC,0x48,0x01,
++    0x84,0xF6,0x49,0xBA,0xC2,0xD4,0xC0,0x08,0x10,0x49,0xC5,0xD4,0x04,0x90,0xC4,0x18,
++    0xE0,0xAC,0xC0,0x74,0x42,0x00,0x12,0x02,0x90,0x05,0x82,0x54,0x30,0x01,0x00,0x7F,
++    0x00,0x01,0x00,0x47,0x40,0x7C,0x40,0xD4,0xD1,0xD0,0x05,0x14,0xE4,0x20,0xE5,0x48,
++    0xE2,0xD8,0xE4,0x00,0x90,0x05,0xD6,0x7C,0x17,0x82,0x9C,0x9E,0xE7,0xB0,0x93,0xB5,
++    0xC4,0x84,0x10,0x32,0x9B,0x66,0x37,0x02,0x40,0x01,0x80,0x06,0x3C,0x02,0x4C,0x2A,
++    0xC2,0xD4,0xC0,0x18,0x48,0x1A,0xC4,0xD4,0x8A,0xC1,0xC1,0x00,0x50,0x0A,0xCC,0xD4,
++    0x94,0x81,0xC3,0x48,0x10,0x01,0x00,0x47,0x40,0x24,0x40,0x74,0xD8,0x20,0x05,0xE4,
++    0xE4,0xD8,0xE4,0x00,0xE2,0x48,0xE4,0x90,0x90,0x95,0xE6,0x7C,0x17,0x12,0x9D,0x9E,
++    0x48,0x92,0xC3,0xD4,0xC0,0x00,0x82,0x4C,0xE0,0xAC,0x00,0x01,0x81,0x8C,0x30,0x42,
++    0x80,0x01,0x81,0xA4,0x80,0x01,0x86,0x9C,0x08,0x97,0x32,0x01,0x08,0x47,0xC2,0x4C,
++    0xC4,0x03,0x48,0x00,0x89,0xF6,0xF3,0x02,0xCC,0x74,0x10,0x42,0xD8,0xD6,0xC3,0x7C,
++    0x32,0x5A,0x03,0x00,0xD0,0x08,0x31,0x52,0xD6,0x01,0x59,0x94,0x10,0xD4,0x40,0x54,
++    0x12,0xD4,0x42,0x4C,0x11,0xCC,0x34,0x0A,0xCE,0x01,0x59,0x4C,0x11,0xCC,0x46,0x0C,
++    0x1B,0xCC,0x40,0x0C,0x18,0xCC,0xCA,0x08,0x31,0x52,0xD0,0x01,0x5C,0x94,0x1E,0xD4,
++    0xD6,0x02,0x19,0xC4,0x40,0x44,0x22,0xC4,0x40,0x25,0x70,0x01,0x88,0x26,0x08,0x01,
++    0x16,0xCC,0x10,0xCC,0x18,0xCC,0x04,0x47,0xCA,0x7C,0xF0,0x48,0x10,0x72,0x8C,0x26,
++    0x0B,0x01,0x30,0x5A,0x12,0xCC,0x1C,0xCC,0x20,0xCC,0xC8,0x8C,0x48,0x01,0x88,0x26,
++    0x30,0x5A,0x13,0xCC,0x14,0xCC,0x12,0xCC,0x00,0x4F,0xC8,0x84,0xD2,0x8C,0xF0,0x48,
++    0x10,0x52,0x8C,0x26,0x0B,0x01,0x30,0x5A,0x1E,0xCC,0x1C,0xCC,0x20,0xCC,0x10,0x01,
++    0xF3,0x12,0x35,0x5A,0x0A,0x81,0xF0,0xCA,0x11,0x8A,0xD4,0x9E,0x0A,0x91,0xF0,0xCA,
++    0x17,0x8A,0xD4,0xD6,0x0A,0xA1,0xF0,0xCA,0x17,0x8A,0xD4,0xB6,0x0A,0xB1,0xF0,0xCA,
++    0x17,0x8A,0xD4,0x96,0x0A,0xD1,0xF0,0xCA,0x11,0x8A,0xE4,0x1E,0x0A,0xE1,0xF0,0xCA,
++    0x17,0x8A,0xE4,0xD6,0x0A,0xF1,0xF0,0xCA,0x17,0x8A,0xE4,0xB6,0x0A,0x01,0xF1,0xCA,
++    0x17,0x8A,0xE4,0x96,0x0A,0xD1,0xEC,0x4A,0x4B,0x01,0x80,0xCE,0x08,0x01,0x88,0x6C,
++    0x30,0x72,0x8C,0x1C,0x88,0x64,0xD8,0xBC,0x5A,0x01,0x88,0x1E,0x32,0xE2,0xFC,0x78,
++    0x1E,0x01,0xF0,0x1A,0x10,0xDA,0xD5,0x46,0xC0,0xC8,0x92,0x4D,0xDA,0x1C,0xE0,0xD8,
++    0x90,0xDD,0x06,0x07,0x00,0xF7,0x9D,0x1C,0x00,0x2F,0x58,0x51,0xEB,0x1E,0x30,0x9A,
++    0xE6,0xD8,0x92,0xDD,0x34,0xF2,0xE4,0x00,0x32,0x1A,0xE3,0xD8,0x94,0xDD,0x36,0xE2,
++    0x30,0x1A,0x5B,0x49,0x9A,0x26,0xC7,0x80,0x90,0x05,0xD0,0xA4,0x70,0x4C,0xE9,0x93,
++    0x10,0x8A,0x9C,0xB6,0xCC,0x5C,0x10,0x42,0xD3,0x9E,0x30,0x8A,0x48,0x39,0x98,0x36,
++    0xCA,0x5C,0x80,0x48,0x10,0x0A,0xDC,0x66,0xC0,0x1C,0x40,0x01,0x88,0x4E,0xC0,0xB4,
++    0xC8,0x03,0x46,0x11,0x98,0x0E,0x00,0x09,0x80,0x6C,0x48,0xDA,0xC2,0x43,0xE2,0x00,
++    0x80,0x43,0x4A,0xCA,0xC0,0x43,0x40,0x81,0x90,0x26,0x52,0xC2,0xA2,0xB2,0xE0,0x00,
++    0x81,0x43,0x00,0xFF,0x34,0xB2,0x84,0x98,0xC0,0x98,0x96,0xDD,0x98,0x14,0x18,0x01,
++    0x30,0xE2,0xDC,0x54,0x80,0xD8,0x9A,0x94,0x1E,0x01,0xF0,0x1A,0xFD,0x94,0x10,0xDA,
++    0xD3,0x56,0x30,0xBA,0xC9,0xF8,0x96,0xFD,0x30,0xF2,0xFD,0x54,0x10,0xDA,0xD5,0x1E,
++    0x86,0xB8,0xCA,0xB8,0x90,0xFD,0xB9,0x14,0xC0,0xC8,0x02,0x97,0x60,0x20,0x02,0x00,
++    0x70,0x72,0x06,0x00,0x70,0x72,0x04,0x00,0x80,0x60,0x07,0x01,0x48,0xE0,0x06,0x00,
++    0x28,0x60,0x00,0x00,0x68,0x70,0x04,0x00,0x00,0xE0,0x00,0x01,0x80,0xE0,0x06,0x01,
++    0x00,0xF7,0x90,0x4D,0xE3,0x00,0x34,0x1A,0xE6,0xD8,0x92,0xDD,0x33,0xE2,0x34,0x1A,
++    0x5E,0x49,0x98,0x8E,0xC4,0x14,0x10,0x0A,0xD8,0x16,0xC8,0x5C,0x28,0x72,0xD4,0x0E,
++    0x00,0x09,0x80,0x6C,0xC6,0xB4,0xC8,0x03,0x40,0x51,0x98,0x16,0xC0,0xBC,0x40,0x01,
++    0x80,0x46,0xC8,0x6C,0x00,0x09,0x48,0x01,0x80,0x06,0x00,0x01,0x80,0x64,0x00,0x0F,
++    0x00,0x09,0x80,0x64,0xC0,0x64,0x40,0x01,0x80,0xA6,0x01,0x09,0xBC,0x43,0x43,0x3A,
++    0x40,0x03,0x42,0x01,0x88,0x5E,0xC0,0xB4,0xC8,0x03,0x46,0x51,0x90,0x3E,0xC0,0xA4,
++    0x6E,0x4C,0xE7,0x03,0x32,0x00,0x72,0x00,0x84,0x51,0x10,0x0A,0xC8,0x0E,0x10,0x01,
++    0x00,0x07,0x10,0x09,0xC0,0xC4,0x40,0x01,0x80,0x06,0x10,0x11,0xC0,0xD4,0x90,0x14,
++    0x81,0x04,0x30,0x9A,0xA9,0x0C,0x30,0x02,0xD0,0x8C,0xC8,0x4C,0xBA,0xFF,0xD7,0x37,
++    0xC0,0x9C,0xC0,0x03,0x38,0x00,0xAA,0x1E,0xFF,0x43,0xF9,0x4B,0x10,0x42,0x9C,0x4E,
++    0xC0,0x9C,0xC0,0x03,0x38,0x00,0xA2,0x1E,0x05,0x01,0xA8,0x43,0xCC,0x9C,0x80,0x43,
++    0x87,0xDD,0xE8,0x85,0xE0,0x20,0xC5,0x4C,0xE0,0x00,0x82,0x4C,0xE7,0xB0,0x93,0xB5,
++    0xC4,0x7C,0x10,0x32,0x95,0x06,0x30,0x97,0xC2,0x8C,0xE0,0x00,0x90,0x05,0x86,0x8C,
++    0xC8,0x84,0xC0,0x8C,0x10,0x42,0x94,0x06,0x37,0x3F,0x3D,0x4F,0xAC,0x9D,0x87,0x0D,
++    0xD8,0x43,0x80,0x04,0xDB,0x63,0x52,0x12,0xC4,0x0C,0xC0,0x28,0x50,0x02,0xC3,0x0C,
++    0xD4,0xC1,0xC1,0x30,0xE8,0x43,0x0C,0xF1,0x84,0x0F,0xD8,0x97,0x49,0xE9,0x88,0x0E,
++    0x48,0xE2,0xC2,0x0C,0xC5,0x10,0x0A,0x49,0xC4,0x0C,0x00,0x48,0xC0,0x08,0x1A,0x01,
++    0x00,0x5F,0x00,0x01,0x00,0x2F,0x40,0x7C,0x04,0xBC,0xE0,0x90,0xE2,0x48,0xE4,0x00,
++    0x95,0x05,0x16,0x02,0x9A,0xBE,0xE7,0xD8,0x90,0xDD,0xC6,0x04,0x17,0x1A,0x9C,0x86,
++    0x00,0x01,0x00,0x2F,0x41,0x8C,0x01,0x4C,0xE5,0x68,0xE5,0xB0,0xE6,0x00,0x92,0x05,
++    0x17,0x02,0x9D,0xBE,0x48,0x62,0xC2,0x0C,0xC0,0x00,0x12,0x01,0x00,0x67,0x08,0x01,
++    0x00,0x37,0xC0,0x1B,0x34,0xD8,0x74,0xD8,0x82,0x1B,0xE0,0x00,0xE6,0x48,0x92,0x4D,
++    0x17,0x0A,0x9D,0xB6,0xE6,0x90,0x92,0x95,0xCC,0x04,0x10,0x52,0x9F,0x7E,0xEF,0xF5,
++    0xAC,0xFD,0x87,0x1D,0x30,0x6A,0x30,0x01,0xBB,0x73,0xB9,0x73,0x37,0x42,0x81,0x01,
++    0xC7,0x0B,0x10,0xE9,0x02,0x52,0x38,0x48,0x7A,0x48,0x06,0x48,0x18,0x52,0x80,0x13,
++    0xC7,0x0B,0x10,0xD9,0x00,0x8A,0x80,0x0B,0x34,0x42,0x81,0x01,0x84,0x14,0xF0,0x03,
++    0x78,0xB2,0x41,0x01,0x80,0x4E,0x00,0x01,0x57,0xAA,0x09,0xF9,0xA2,0x8A,0xE0,0x00,
++    0x90,0x05,0x46,0x81,0x99,0xD6,0x87,0xF3,0x80,0xF3,0xAB,0x04,0x00,0x01,0xD8,0x1C,
++    0xD0,0x34,0xC8,0x2C,0xBD,0xFF,0xEF,0xD7,0x36,0x62,0xA1,0x01,0xC8,0x03,0x47,0x51,
++    0x98,0x36,0xA8,0x04,0x00,0x09,0xD8,0x1C,0xD0,0x34,0xC8,0x2C,0xBD,0xFF,0xEF,0x77,
++    0xC4,0x14,0xF0,0x0B,0x49,0x01,0x80,0xD6,0x00,0x01,0x48,0x09,0x8B,0x5E,0xC0,0xD3,
++    0x50,0x01,0x80,0x46,0x50,0x1A,0xC1,0x93,0x50,0x01,0x88,0x26,0x50,0x12,0xC1,0x93,
++    0x50,0x01,0x88,0x06,0x00,0x09,0x40,0x01,0x87,0x2E,0xC8,0x13,0x50,0x01,0x95,0x36,
++    0xE7,0x90,0x8A,0x13,0x07,0x1F,0xC8,0x13,0x50,0x51,0x90,0x06,0x8F,0x33,0xCF,0x13,
++    0x50,0x51,0x98,0xE6,0x40,0x01,0x88,0x6E,0x48,0x09,0x88,0x16,0xF7,0x90,0x8A,0x13,
++    0x01,0x47,0x00,0x99,0xEF,0x02,0x6A,0x4C,0x34,0x00,0x72,0x00,0x10,0x0A,0x94,0x0E,
++    0xF7,0x90,0x8A,0x13,0xC0,0xC3,0x43,0x11,0x9D,0x16,0x00,0x01,0x88,0x03,0x07,0x37,
++    0x40,0x09,0x88,0x26,0xCA,0x03,0x47,0x81,0x93,0x0E,0x00,0x21,0x89,0x03,0x37,0x4A,
++    0xC7,0x1C,0xB8,0xFF,0xF8,0xDF,0x81,0x3D,0xE8,0x85,0x07,0x00,0x80,0x60,0x07,0x01,
++    0x68,0xF0,0x07,0x00,0x28,0x60,0x00,0x00,0x60,0x20,0x02,0x00,0x00,0xE0,0x00,0x01,
++    0x80,0xE0,0x06,0x01,0x00,0x40,0x00,0x01,0x00,0x48,0x00,0x01,0xAC,0xFD,0x87,0x3D,
++    0xE0,0x84,0x30,0xB2,0x00,0x01,0x80,0x2C,0xD8,0x83,0x83,0x1C,0x60,0x8C,0x89,0x14,
++    0xCA,0x44,0x18,0x0A,0x50,0xFA,0xC7,0x3C,0xC0,0x00,0xC4,0x48,0x8F,0x34,0x40,0xF2,
++    0xC0,0x03,0x40,0x09,0x89,0x0E,0xE0,0x83,0x80,0x1C,0x00,0x01,0x10,0x01,0x00,0x1F,
++    0x82,0x53,0xE0,0x48,0xE6,0x00,0x92,0x05,0xDC,0x1C,0x10,0xC2,0x98,0xC6,0x0F,0x01,
++    0x00,0x09,0xD8,0x54,0xD0,0x44,0x80,0x07,0xD0,0xAF,0x2E,0x01,0x60,0x01,0x88,0x0E,
++    0xE7,0x68,0x93,0x6D,0xF8,0x34,0x08,0x01,0x01,0x5F,0xC0,0xC3,0x1E,0x02,0x91,0x05,
++    0x80,0xC3,0xD1,0x8C,0x10,0x82,0xCC,0x0E,0x19,0x02,0x85,0xC3,0xE2,0xF8,0xE3,0x48,
++    0x90,0x4D,0xC6,0x1C,0x17,0x0A,0x9C,0x86,0x48,0x42,0xC7,0x3C,0xC0,0x00,0x82,0x24,
++    0xD0,0x54,0x90,0x04,0x30,0x9A,0x01,0x11,0xD0,0x3C,0xC8,0x44,0x80,0x07,0xD8,0x47,
++    0xD0,0x54,0x90,0x04,0x04,0x41,0xEA,0x0A,0x00,0x01,0x1C,0x0A,0x30,0x9A,0x11,0x01,
++    0xC0,0x24,0x80,0x07,0xF6,0x27,0x05,0x29,0xE8,0x02,0x44,0x31,0x88,0x16,0x00,0x01,
++    0x87,0x5D,0xE8,0x85,0xC1,0x1C,0xD0,0xC0,0x09,0x01,0x00,0x3F,0xD0,0x24,0x18,0x01,
++    0xF0,0x9A,0xD6,0x14,0xD0,0xD0,0x94,0x95,0x68,0x01,0x88,0x2E,0x50,0xC1,0xE8,0xBE,
++    0xC5,0x13,0x18,0x12,0x80,0x13,0x00,0x9F,0x50,0x99,0xE8,0x2E,0xC0,0x13,0x50,0x01,
++    0x82,0x16,0xF0,0x90,0x80,0x13,0x00,0x5F,0x68,0x29,0x88,0x4E,0x58,0xE1,0xEE,0x3E,
++    0xC0,0x13,0x50,0x01,0x88,0x26,0xD0,0x2C,0x50,0x01,0x88,0x0E,0x10,0x09,0x90,0x2C,
++    0xD4,0x24,0xE0,0x90,0x92,0x24,0xE0,0x00,0xE6,0x48,0x92,0x4D,0xD4,0x1C,0x10,0x8A,
++    0x9B,0xA6,0x46,0x20,0x6C,0x21,0xC8,0xCE,0xD0,0x54,0x90,0x04,0x30,0x9A,0x09,0x01,
++    0x00,0x19,0xD0,0x3C,0x85,0x07,0xD0,0xE7,0x08,0x09,0x30,0x42,0xD8,0x54,0xD0,0x44,
++    0x83,0x07,0xD0,0x07,0xC5,0x2C,0x38,0xDF,0xAC,0xFD,0x87,0x1D,0xF0,0x64,0x30,0x7A,
++    0x33,0xEA,0xD8,0xC3,0x85,0x14,0x48,0xAA,0xC2,0x1C,0xC0,0x20,0x40,0x92,0xC5,0x03,
++    0x40,0x09,0x88,0x0E,0xE0,0xC3,0x81,0x14,0x08,0x01,0x00,0x09,0xD8,0x2C,0xD0,0x6C,
++    0x82,0x07,0xD0,0x47,0xD0,0x2C,0x90,0x04,0x30,0xDA,0x01,0x11,0xD0,0x1C,0xC8,0x6C,
++    0x84,0x07,0xD0,0xB7,0xD0,0x2C,0x90,0x04,0x06,0x41,0xEA,0x0A,0x00,0x01,0x1C,0x0A,
++    0x30,0xDA,0x11,0x01,0x30,0x02,0x81,0x07,0xF0,0x97,0xD1,0x2C,0x91,0x04,0x30,0xDA,
++    0x08,0x01,0x00,0x19,0xD0,0x1C,0x80,0x07,0xD0,0x1F,0x0C,0x09,0x30,0x42,0xD8,0x2C,
++    0xD0,0x6C,0x80,0x07,0xD4,0x3F,0x41,0xF2,0x00,0x44,0x01,0x01,0x00,0x84,0x09,0x01,
++    0x00,0x77,0x00,0x01,0xF0,0x02,0x11,0x01,0xF4,0x52,0x15,0x12,0xE9,0x06,0x00,0x44,
++    0x15,0x01,0xF0,0x92,0x10,0x12,0xD4,0x06,0x05,0x84,0xE1,0x20,0xE6,0x48,0x92,0x4D,
++    0xC4,0x14,0x10,0x0A,0x98,0x6E,0x87,0x3D,0xEF,0x85,0xAF,0xBD,0x80,0x55,0xC4,0x5C,
++    0xD8,0x03,0x86,0x24,0xCA,0x5C,0xD8,0x4B,0x8C,0x1C,0x50,0x52,0xCC,0x54,0xC0,0x48,
++    0x8C,0x4C,0x48,0x4A,0xC0,0x4B,0x48,0x09,0x88,0x46,0xC8,0x24,0xE6,0x48,0x92,0x4D,
++    0x88,0x24,0x80,0x3C,0xC0,0x5C,0xE0,0x03,0x80,0x1C,0x00,0x0F,0x00,0x01,0x80,0x3C,
++    0xF8,0x3C,0xC0,0x5C,0x80,0x01,0x86,0x44,0x04,0x7F,0x4B,0x12,0x04,0x01,0x00,0x43,
++    0xC0,0x5C,0xC8,0x4C,0xDB,0x03,0x1A,0xC2,0xC0,0x08,0x02,0x01,0x10,0xF9,0x01,0x1F,
++    0x82,0x53,0xE0,0x48,0xE6,0x00,0x92,0x05,0xDC,0x1C,0x10,0xC2,0x9C,0xC6,0x27,0x01,
++    0x31,0x2A,0x31,0x32,0x03,0xE7,0x40,0xC2,0x08,0x23,0x4E,0x2D,0xB8,0x0C,0x88,0x04,
++    0x40,0x55,0x40,0x3E,0x5F,0x35,0xB8,0xFF,0xF8,0x7F,0xC3,0x44,0xC8,0x03,0x42,0x31,
++    0x83,0x7E,0x33,0x5A,0x00,0xC1,0xF0,0xC2,0x40,0xE1,0xD1,0x1E,0x68,0x41,0x80,0x4E,
++    0x18,0x62,0x05,0x1F,0x70,0x01,0x8C,0x0E,0x30,0x72,0x01,0x1F,0x41,0x68,0x1B,0x62,
++    0x6F,0x01,0x88,0x06,0xC0,0x5C,0xC8,0x4C,0xDB,0x03,0x1A,0xC2,0xC0,0x08,0x02,0x01,
++    0x10,0x01,0x00,0x1F,0x82,0x53,0xE0,0x48,0xE6,0x00,0x92,0x05,0xDC,0x1C,0x10,0xC2,
++    0x99,0xC6,0x37,0xAA,0x20,0x01,0x00,0x0F,0x1B,0xA2,0x41,0xB0,0x77,0x01,0x88,0xDE,
++    0xC0,0x5C,0x60,0x04,0xC0,0x41,0x91,0x35,0x05,0xAF,0x18,0x62,0x46,0xD2,0x0A,0x23,
++    0x48,0x2D,0xB8,0x0C,0x88,0x04,0x40,0x55,0x40,0x3E,0x58,0x35,0xB9,0xFF,0xFF,0xA7,
++    0xC2,0x44,0xC8,0x03,0x42,0x31,0x80,0x6E,0x30,0x5A,0x03,0xA1,0xF5,0xC2,0x10,0x82,
++    0xE9,0x06,0x18,0x62,0x40,0x68,0x6B,0x01,0x88,0x3E,0xC7,0x54,0x0E,0x59,0xCB,0x00,
++    0x0A,0x48,0xC2,0x00,0xB3,0x23,0xE0,0xF8,0x90,0xFD,0xC7,0x24,0x14,0x3A,0x9C,0x66,
++    0xF1,0x3C,0x00,0xA7,0xC3,0x54,0x08,0x59,0xCA,0x00,0x0C,0x48,0xC1,0x38,0xF2,0xC3,
++    0x40,0x01,0x88,0x0E,0x01,0x09,0xB0,0xC3,0xF0,0xE3,0x29,0x01,0x01,0x01,0x00,0x0F,
++    0xE7,0x68,0x93,0x6D,0x40,0x09,0x88,0x1E,0x60,0xF9,0x97,0x0E,0xE5,0x20,0x93,0x25,
++    0x48,0xE2,0x01,0x01,0x00,0x43,0xAC,0x48,0x46,0xDA,0x09,0x23,0x20,0x00,0x67,0x10,
++    0x00,0x0F,0x00,0xBF,0x40,0x48,0x32,0x82,0x17,0x42,0x80,0xDE,0x48,0x01,0xC9,0x06,
++    0x08,0x01,0x89,0x04,0x90,0x0C,0x40,0x55,0x41,0x6E,0x30,0x8A,0xBA,0xFF,0xF7,0x77,
++    0x40,0x01,0x80,0x0E,0x6E,0x29,0x98,0xDE,0xB3,0xE3,0xE1,0xB0,0x90,0xB5,0xC7,0x24,
++    0x16,0x32,0x9C,0x3E,0x87,0x6D,0xE8,0x85,0xAC,0xBD,0x87,0x15,0x30,0x62,0x30,0xB2,
++    0x48,0x2A,0x01,0x01,0x81,0x43,0x40,0x4A,0x40,0x0B,0x10,0x11,0x18,0x8A,0x00,0x0B,
++    0x28,0x01,0x00,0x3F,0x09,0x09,0x30,0x9A,0x30,0x52,0x31,0x42,0x81,0x07,0xC8,0x57,
++    0xE7,0x68,0x93,0x6D,0xDD,0x03,0x11,0x42,0xC1,0xA6,0x37,0x12,0x30,0x8A,0x01,0x11,
++    0x84,0x07,0xC0,0x2F,0x31,0x92,0x31,0x0A,0xC7,0x14,0xB8,0xFF,0xF9,0x77,0x30,0x12,
++    0x30,0x8A,0x01,0x01,0x83,0x07,0xC0,0xDF,0xE0,0x03,0x41,0x01,0x80,0xBE,0x69,0xB2,
++    0x44,0x43,0x97,0x3D,0x4F,0x04,0x01,0x43,0x40,0x7A,0x08,0x09,0x81,0x0B,0x30,0x12,
++    0x30,0x8A,0x01,0x11,0x83,0x07,0xC0,0x5F,0x30,0x1A,0xB1,0x04,0x08,0x01,0x00,0x09,
++    0xD0,0x14,0x80,0x07,0xC8,0xAF,0xB2,0x04,0xD9,0x0B,0x37,0x1A,0x00,0x11,0xD0,0x14,
++    0x82,0x07,0xC8,0x77,0x31,0x92,0x31,0x0A,0xC7,0x14,0xB8,0xFF,0xF1,0x37,0x37,0x12,
++    0x30,0x8A,0x01,0x6F,0x60,0x20,0x02,0x00,0x00,0xF0,0x00,0x01,0x48,0xE0,0x06,0x00,
++    0xF8,0xFB,0x07,0x00,0x10,0x00,0x00,0x42,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,
++    0x00,0x01,0x80,0x07,0xC0,0x27,0x42,0x5A,0x08,0x01,0x80,0x0B,0x01,0x7B,0x37,0x1A,
++    0xB0,0x04,0x08,0x01,0x00,0x11,0xD0,0x14,0x81,0x07,0xC8,0x57,0x31,0x12,0x31,0x8A,
++    0x00,0x11,0x80,0x07,0xC0,0xA7,0x51,0x22,0x40,0x83,0x08,0x11,0x18,0x42,0x04,0x83,
++    0x87,0x2D,0xE8,0x85,0x00,0xF0,0x00,0x01,0x18,0x00,0x04,0x42,0xA8,0x85,0x31,0x12,
++    0x92,0x01,0x46,0x8C,0x80,0x01,0xC7,0x1B,0x32,0xD8,0x72,0xD8,0x87,0x1B,0x58,0xE2,
++    0x41,0xE3,0x30,0x20,0xA2,0x16,0x40,0xE3,0x3F,0x20,0xAB,0xE6,0x58,0xCA,0x27,0x41,
++    0x00,0xE3,0x44,0xE3,0x28,0xF9,0xAF,0x19,0x18,0x62,0x01,0xE3,0xC7,0x23,0x48,0x20,
++    0x8A,0x1E,0xF0,0x48,0x20,0x48,0x60,0x48,0x88,0xC6,0x4F,0x01,0x88,0x36,0x40,0xC3,
++    0x08,0x81,0x18,0x42,0x07,0xC3,0x00,0xF9,0x82,0x89,0x04,0x84,0xEF,0x85,0xA9,0x85,
++    0x46,0x63,0x42,0x5B,0xDF,0xAB,0x72,0x62,0xC0,0xB3,0x71,0x09,0x8E,0x16,0x48,0x63,
++    0x50,0x5B,0xE2,0xAB,0x41,0x01,0x88,0x0E,0x10,0x01,0x00,0xE7,0x40,0x03,0x31,0x32,
++    0xB5,0x41,0x30,0xA2,0xE8,0x08,0x30,0x42,0xC4,0x01,0x5A,0x33,0xC1,0xFB,0x18,0xF2,
++    0x1E,0x33,0x5C,0x33,0xC5,0xFB,0x18,0xF2,0x1B,0x33,0x36,0x32,0x40,0x83,0xC1,0xF3,
++    0x1B,0x82,0x35,0x32,0x00,0x83,0x41,0x73,0xC4,0xC3,0x18,0x32,0x01,0x73,0xE8,0x20,
++    0xE2,0xD8,0xE2,0x90,0x95,0x95,0x16,0x52,0x9F,0x06,0xEF,0x85,0x41,0x09,0x88,0x0E,
++    0x10,0x01,0x00,0xE7,0x40,0x03,0x31,0x32,0xB5,0x41,0x30,0xA2,0xE8,0x08,0x30,0x42,
++    0xC4,0x01,0x5A,0x33,0xC5,0xFB,0x18,0xF2,0x1E,0x33,0x5C,0x33,0xC5,0xFB,0x18,0xF2,
++    0x1B,0x33,0x36,0x32,0x40,0x83,0xC1,0xF3,0x1B,0x82,0x35,0x32,0x00,0x83,0x41,0x73,
++    0xC0,0xC3,0x18,0x32,0x01,0x73,0xE8,0x20,0xE2,0xD8,0xE2,0x90,0x95,0x95,0x16,0x52,
++    0x9F,0x06,0xEF,0x85,0x41,0x11,0x88,0x0E,0x10,0x01,0x00,0xE7,0x40,0x03,0x31,0x32,
++    0xB5,0x41,0x30,0xA2,0xE8,0x08,0x30,0x42,0xC4,0x01,0x5A,0x33,0xC5,0xFB,0x18,0xF2,
++    0x1E,0x33,0x5C,0x33,0xC5,0xFB,0x18,0xF2,0x1B,0x33,0x36,0x32,0x40,0x83,0xC1,0xF3,
++    0x1B,0x82,0x31,0x32,0x00,0x83,0x41,0x73,0xC4,0xC3,0x18,0x32,0x01,0x73,0xE8,0x20,
++    0xE2,0xD8,0xE2,0x90,0x95,0x95,0x16,0x52,0x9F,0x06,0xEF,0x85,0x47,0x19,0x88,0xE6,
++    0x10,0x01,0x00,0xE7,0x40,0x03,0x31,0x32,0xB5,0x41,0x30,0xA2,0xE8,0x08,0x30,0x42,
++    0xC4,0x01,0x5A,0x33,0xC5,0xFB,0x18,0xF2,0x1E,0x33,0x5C,0x33,0xC5,0xFB,0x18,0xF2,
++    0x1B,0x33,0x36,0x32,0x40,0x83,0xC1,0xF3,0x1B,0x82,0x31,0x32,0x00,0x83,0x41,0x73,
++    0xC0,0xC3,0x18,0x32,0x01,0x73,0xE8,0x20,0xE2,0xD8,0xE2,0x90,0x95,0x95,0x16,0x52,
++    0x9F,0x06,0xEF,0x85,0xAA,0x85,0x47,0xE3,0x05,0xB0,0xCC,0x20,0x45,0xEB,0xC6,0x68,
++    0x40,0x09,0x88,0x26,0x45,0xE3,0xC8,0x20,0x44,0xDB,0xC4,0xE8,0x04,0x3F,0x78,0xD2,
++    0xC0,0xFB,0x79,0x09,0x8E,0x1E,0x48,0xE3,0xCA,0x20,0x55,0xDB,0xC1,0xE8,0x44,0x13,
++    0xF9,0xA0,0xC0,0x5B,0x40,0x09,0x88,0x76,0x48,0x01,0x88,0x66,0x44,0x83,0x1A,0xC2,
++    0x04,0x83,0x42,0x83,0x1C,0xC2,0x04,0x83,0x44,0x03,0x19,0xC2,0x00,0x03,0x41,0x83,
++    0x18,0xC2,0x00,0x83,0xE8,0x85,0x4F,0x09,0x8A,0x66,0x40,0x83,0x1A,0xC2,0x04,0x83,
++    0x44,0x83,0x1C,0xC2,0x00,0x83,0x44,0x83,0x18,0xC2,0x04,0x83,0x40,0x03,0x19,0xC2,
++    0x07,0x03,0xE9,0x85,0x48,0x11,0x88,0x66,0x44,0x03,0x19,0xC2,0x00,0x03,0x41,0x83,
++    0x18,0xC2,0x04,0x83,0x40,0x83,0x1A,0xC2,0x04,0x83,0x42,0x83,0x1C,0xC2,0x04,0x83,
++    0xE8,0x85,0x4F,0x19,0x89,0xE6,0x47,0x03,0x19,0xC2,0x04,0x03,0x44,0x83,0x18,0xC2,
++    0x02,0x83,0x40,0x83,0x1A,0xC2,0x04,0x83,0x40,0x83,0x1C,0xC2,0x07,0x83,0xEC,0x85,
++    0xA8,0xFD,0xF7,0x4C,0x30,0x62,0x2C,0x01,0x4D,0x93,0x49,0x8B,0x32,0x72,0xDC,0xE3,
++    0x33,0x3A,0x49,0x8A,0xC0,0x4B,0x48,0x09,0x89,0x0E,0x50,0x93,0xE0,0xE3,0x40,0x19,
++    0x80,0x96,0x31,0x79,0x49,0x5A,0x13,0xB0,0x40,0x11,0x88,0xB6,0x32,0x02,0x1B,0x3A,
++    0x58,0x52,0xC3,0x14,0xC1,0x00,0xC6,0xC0,0x33,0x9A,0x33,0x2A,0xEA,0xDA,0x0A,0x5B,
++    0x08,0x01,0x00,0x3F,0xC1,0x1B,0x18,0x9A,0x41,0xAB,0x00,0x5B,0xEA,0x90,0xE0,0x00,
++    0xE6,0x48,0x92,0x4D,0x17,0x0A,0x9D,0xAE,0xE8,0xFD,0x47,0x01,0x88,0x8E,0x18,0x01,
++    0x12,0x5B,0x46,0xDA,0x45,0x33,0x40,0xB0,0x00,0xB0,0x05,0x33,0x00,0x1B,0x02,0x5B,
++    0x40,0x0B,0x18,0x81,0x18,0xCA,0x04,0x0B,0x44,0x0B,0x18,0x01,0x18,0xCA,0x00,0x0B,
++    0x00,0x17,0x40,0x09,0x89,0x06,0x30,0xAA,0x00,0x01,0x00,0x27,0x40,0x8B,0x00,0x6B,
++    0xEA,0x90,0xE0,0x00,0x95,0x05,0x16,0x02,0x9F,0xC6,0xEF,0xFD,0x3B,0x82,0xAB,0x85,
++    0x4A,0xA3,0xD8,0xEB,0x33,0x70,0x72,0xB0,0x48,0x5A,0xC2,0x4B,0x48,0x09,0x88,0x0E,
++    0x50,0xA3,0xE0,0xEB,0x08,0x01,0x00,0x3F,0x42,0x13,0x41,0x93,0x00,0x92,0x07,0x14,
++    0xEC,0x20,0xE1,0x00,0xE6,0x48,0x92,0x4D,0x17,0x4A,0x9D,0xAE,0xEB,0x85,0xAB,0xC5,
++    0x30,0x2A,0x30,0xB2,0x61,0xF2,0x41,0x03,0x14,0x01,0x1C,0x82,0x01,0x03,0x41,0x03,
++    0x10,0x81,0x18,0x82,0x01,0x03,0x41,0x03,0x10,0x09,0x18,0x82,0x07,0x03,0xE1,0x53,
++    0x00,0xF9,0x87,0x81,0x19,0x12,0x40,0xBA,0x10,0x13,0x16,0x99,0x00,0x13,0x13,0x41,
++    0x04,0x13,0x14,0xD9,0xE8,0x92,0x52,0x01,0x80,0x16,0x10,0xC9,0x00,0x13,0x00,0x0F,
++    0x10,0x89,0x00,0x13,0x31,0x52,0x30,0x5A,0x08,0x01,0x00,0x09,0xB7,0x04,0xB8,0xFF,
++    0xF9,0x7F,0x33,0x52,0x30,0x8A,0x01,0x11,0xBB,0xFF,0xF7,0xCF,0x42,0x03,0x3B,0x00,
++    0xAB,0xE6,0xEF,0xC5,0xAC,0x9D,0x87,0x8D,0xCA,0x94,0xC8,0x4B,0x88,0x84,0xE0,0x94,
++    0xA7,0x01,0xD2,0x1B,0xD8,0x0B,0x89,0x04,0xCA,0x94,0xD8,0x6B,0x30,0x0A,0x88,0x71,
++    0x30,0x62,0xCC,0x94,0x30,0x01,0xE8,0x4B,0x48,0x09,0x88,0x56,0x08,0x01,0x00,0x27,
++    0xC5,0x38,0x9A,0xF3,0xA2,0x32,0xE2,0x48,0x90,0x4D,0xD2,0x94,0xDC,0x93,0x12,0x52,
++    0xE0,0xB6,0x57,0xDA,0x04,0xB3,0x02,0xB3,0x00,0xB3,0x0E,0x01,0x18,0x4A,0x06,0x8B,
++    0xCA,0x94,0xD8,0x4B,0xB0,0x8B,0x08,0x01,0x50,0xAA,0x30,0x01,0x05,0x78,0xC4,0xF8,
++    0x0A,0xF3,0xC1,0x90,0xB2,0xB3,0xE2,0x48,0x90,0x4D,0x4A,0x11,0xD8,0xA6,0xCF,0x94,
++    0xE8,0x4B,0x48,0x29,0xCD,0xF6,0x03,0x48,0xC3,0x48,0x00,0x50,0xC0,0x70,0x54,0x6A,
++    0xC0,0xB0,0xB5,0x14,0xC0,0x48,0x8C,0x0C,0x30,0x12,0x33,0x32,0xB0,0xE1,0x08,0x01,
++    0x88,0x34,0x48,0x4A,0x88,0x6C,0x88,0x64,0x30,0x32,0x04,0x01,0x32,0x22,0x04,0x97,
++    0x18,0x00,0x04,0x42,0x00,0x01,0x00,0x42,0x00,0xF0,0x00,0x01,0x60,0x20,0x02,0x00,
++    0x80,0x60,0x07,0x01,0x48,0xE0,0x06,0x00,0x78,0xF8,0x07,0x00,0xC8,0x14,0x00,0x01,
++    0xF0,0x42,0xF8,0x0C,0x0B,0x01,0xF0,0xCA,0x32,0x7A,0xD0,0x08,0x97,0x4D,0x48,0xF9,
++    0xEF,0x06,0x08,0xF9,0xCB,0x38,0x86,0xF8,0x78,0xF9,0xEF,0x06,0x3B,0xF9,0x37,0x82,
++    0x82,0x3B,0xE0,0x00,0x30,0x32,0xC4,0xBB,0x10,0xFA,0x9C,0x46,0x10,0xCA,0xDC,0x36,
++    0x46,0x84,0xD9,0x48,0xC0,0x00,0x92,0x05,0x04,0x84,0x81,0x08,0x04,0x37,0x10,0xCA,
++    0xDC,0x16,0x00,0x78,0x00,0xBC,0x01,0x0F,0x39,0x01,0x00,0xBC,0x10,0xCA,0xDC,0x0E,
++    0x38,0x09,0xB8,0x34,0x43,0x78,0x2B,0x3A,0xE8,0x26,0xF8,0x6C,0x10,0x7A,0xEC,0x2E,
++    0x88,0x6C,0x00,0x1F,0xFC,0x64,0x10,0x7A,0xE8,0x06,0x88,0x64,0x82,0x8B,0xE0,0x90,
++    0xE0,0xB0,0xC5,0x14,0xE0,0x00,0x84,0x14,0xC4,0x0C,0xE0,0x00,0x83,0x0C,0x30,0x02,
++    0xE2,0x00,0x92,0x05,0x35,0x22,0x2C,0x62,0xD8,0xC6,0xC5,0x34,0x40,0x01,0x80,0x8E,
++    0x08,0x01,0x00,0x01,0x80,0x5C,0xC0,0x04,0xC2,0x00,0x46,0x00,0x80,0x7C,0xC0,0x04,
++    0x30,0x00,0x72,0x00,0x80,0x74,0x00,0x01,0x30,0x22,0x84,0x2C,0x80,0x24,0x80,0x1C,
++    0xF0,0x90,0x02,0x07,0x03,0x1F,0xF5,0x40,0x94,0x05,0x32,0x32,0x03,0xFF,0x31,0x02,
++    0x04,0x00,0x32,0x22,0xC2,0x2C,0x00,0x00,0x80,0x2C,0xC0,0x24,0x00,0x00,0x82,0x24,
++    0xC2,0x1C,0x00,0x00,0x83,0x1C,0x40,0x40,0x28,0x82,0xEB,0x26,0xC0,0x83,0xF0,0x6C,
++    0xD8,0x00,0x84,0x83,0x00,0x1F,0xC0,0x83,0xF4,0x64,0xD8,0x00,0x80,0x83,0xC0,0x83,
++    0x73,0x3D,0x30,0xBA,0xA8,0x82,0xC7,0x83,0x10,0xC2,0xDC,0xDE,0xE2,0x48,0x92,0x4D,
++    0xF1,0x5C,0xC0,0xB0,0x90,0xB5,0xB1,0x5C,0x30,0x32,0x3B,0x09,0x1D,0xF2,0x31,0xA2,
++    0xF5,0x7C,0x10,0x82,0xD8,0x76,0xF0,0x2C,0x18,0xF2,0xB1,0x2C,0xF5,0x04,0x10,0x82,
++    0xD8,0x46,0xF0,0x24,0x18,0xF2,0xB1,0x24,0xF5,0x74,0x10,0x82,0xD8,0x16,0xC0,0x1C,
++    0x18,0xC2,0x81,0x1C,0xF3,0x90,0x32,0x82,0xF2,0x00,0x92,0x05,0x33,0x32,0x34,0x82,
++    0x45,0x01,0xD0,0xE6,0x42,0xE2,0xB7,0x0B,0xD0,0x50,0xB3,0x13,0x36,0x12,0x1B,0x92,
++    0x03,0x13,0x30,0x12,0x08,0x13,0xD0,0x2C,0x00,0x13,0xD2,0x24,0x00,0x13,0xD4,0x1C,
++    0x00,0x13,0x36,0x01,0x00,0xA7,0xC1,0x5C,0x86,0x07,0xE8,0xA7,0x90,0x05,0x80,0x5C,
++    0x4D,0x8A,0x07,0x80,0xC0,0x00,0x4A,0x13,0x40,0x3D,0x08,0x01,0x1C,0x01,0x30,0xF2,
++    0x30,0xE2,0x04,0xCF,0x38,0x98,0x86,0x7E,0xC0,0x1B,0xF8,0x5C,0xD8,0xD8,0x96,0xDD,
++    0x58,0x01,0xE8,0x36,0x83,0x1B,0x20,0x9A,0x94,0xDD,0x36,0xF2,0xE2,0x48,0x92,0x4D,
++    0x00,0x27,0x18,0x01,0x80,0x1B,0x00,0x0F,0x18,0x01,0x80,0x1B,0x42,0x90,0xE2,0x00,
++    0x32,0x1A,0xE3,0xD8,0x94,0xDD,0x32,0xE2,0x2F,0x62,0xDD,0x1E,0xE3,0xB0,0x93,0xB5,
++    0x30,0x82,0x83,0x5C,0x45,0xE2,0x06,0x98,0xC0,0xD8,0x08,0xD3,0xCA,0x00,0xB4,0x0B,
++    0x48,0x21,0xD8,0x0E,0x76,0x09,0xD8,0x36,0x06,0x01,0x50,0xBA,0x04,0x08,0xC4,0x58,
++    0xE4,0x08,0x02,0x70,0xC0,0xB0,0x4D,0xEB,0x4D,0xB3,0x19,0xAA,0x08,0xEB,0xC0,0x80,
++    0xF4,0x1B,0xF2,0x2B,0xDA,0xD8,0xB2,0x1B,0x90,0x45,0x42,0x09,0xD8,0x76,0x07,0x09,
++    0xA6,0x03,0x43,0x6A,0x0E,0x19,0x40,0x13,0x50,0x01,0x80,0x16,0x03,0x29,0xA0,0x0B,
++    0x04,0xF7,0x40,0x13,0x50,0x01,0x80,0x16,0x03,0x21,0xA0,0x0B,0x02,0xC7,0x40,0x0B,
++    0x48,0x01,0x80,0x1E,0x00,0x19,0x08,0x11,0xA0,0x0B,0x03,0x8F,0x48,0x03,0x40,0x01,
++    0x88,0x26,0xC0,0x94,0x86,0x01,0xCE,0x03,0x40,0x51,0x98,0x0E,0x00,0x11,0x00,0x3F,
++    0xC1,0x94,0x80,0x01,0xE0,0x03,0x44,0x01,0x80,0x0E,0x00,0x11,0x00,0x07,0x00,0x09,
++    0xE4,0x0B,0xE3,0x50,0xA3,0x13,0xDD,0x13,0x38,0x90,0xA2,0x0E,0xF3,0x48,0xA2,0x0B,
++    0xE8,0x0B,0x13,0x29,0x10,0x0A,0x94,0x0E,0xA8,0x13,0x01,0xEF,0x10,0x0A,0xCC,0x46,
++    0x40,0x09,0x88,0x16,0x09,0x81,0xAF,0x0B,0x00,0xB7,0xD0,0x48,0x01,0x52,0xAC,0x13,
++    0x00,0x97,0x40,0x19,0xC8,0x0E,0x08,0x19,0x02,0x07,0x90,0x0D,0xE8,0x13,0x51,0x01,
++    0x82,0x16,0xF0,0x90,0xA8,0x13,0x01,0x3F,0xD2,0x94,0xF0,0x48,0xCA,0x93,0x1C,0x52,
++    0xCA,0x84,0xC0,0x88,0xD0,0x94,0x88,0x8B,0xA8,0x03,0x83,0x9D,0xEF,0x85,0xAF,0xBD,
++    0x80,0x6D,0x34,0x6A,0xD9,0x63,0x33,0x42,0x80,0x01,0x82,0x64,0xD0,0x03,0x84,0x3C,
++    0xC2,0x64,0xD8,0x03,0x30,0x00,0xA8,0x1E,0x02,0xD9,0xEC,0x02,0x40,0x01,0x80,0xA6,
++    0xC5,0x6C,0x00,0x08,0xC3,0x40,0x00,0x08,0x52,0xC2,0xC4,0x08,0xC4,0x48,0xC4,0x10,
++    0x00,0x01,0x18,0x01,0x00,0x2F,0x00,0x5C,0x04,0x9C,0xE0,0x48,0xE2,0x90,0xE4,0x00,
++    0x95,0x05,0x12,0x02,0xD8,0xBE,0x87,0x85,0xEB,0x85,0x07,0x59,0xCA,0x6C,0x08,0x00,
++    0xC4,0x40,0x70,0x7A,0xF7,0x03,0x08,0x83,0xD0,0x7C,0x90,0x04,0x30,0x5A,0x09,0x01,
++    0x00,0x11,0xD0,0x6C,0xBB,0xFF,0xEF,0xE7,0x42,0x4A,0x84,0x01,0x43,0x0B,0x30,0x5A,
++    0x09,0xCC,0x5C,0x8B,0x0B,0xCC,0x5E,0x8B,0x15,0xCC,0x58,0x8B,0x17,0xCC,0x42,0x8B,
++    0x14,0xCC,0x4C,0x22,0x46,0x53,0x10,0xD4,0x48,0x93,0x1F,0xD4,0x17,0x89,0x00,0x93,
++    0x13,0x19,0x18,0x93,0x40,0x53,0x18,0x11,0x18,0xD2,0x04,0x53,0x40,0x0B,0x18,0xCA,
++    0x01,0x0B,0x30,0x42,0xE9,0x4B,0x81,0x01,0x80,0x5C,0x48,0x09,0x8D,0x5E,0x6A,0x44,
++    0x81,0x14,0x30,0x8A,0x5E,0x43,0x94,0x35,0xB0,0x0C,0x00,0x01,0x80,0x04,0xD0,0x6C,
++    0x4F,0x92,0x03,0x00,0xC2,0x00,0xC4,0x00,0x83,0x54,0x40,0x8A,0x18,0x33,0x0A,0x01,
++    0x37,0x42,0xB9,0xFF,0xE0,0x5F,0xF9,0x54,0xC1,0x64,0x30,0x5A,0xD1,0x0B,0x32,0xC2,
++    0xD7,0x7C,0xB8,0xFF,0xEB,0x67,0x4C,0x62,0x10,0x01,0x00,0x01,0x02,0x67,0x00,0x18,
++    0x37,0xE2,0xF4,0xDA,0x10,0x5A,0xD4,0x0E,0x33,0x0A,0xD3,0xCA,0x10,0x9A,0xEC,0x0E,
++    0x35,0x12,0xD3,0xD2,0xE2,0x00,0x92,0x05,0x17,0x02,0xDD,0x86,0xC4,0x14,0xE0,0x00,
++    0x10,0x0A,0x9C,0x36,0xC0,0x04,0x40,0x01,0x8B,0x9E,0x40,0x80,0x40,0x08,0xC2,0x70,
++    0x00,0x3F,0xC0,0x14,0xF4,0x00,0x14,0x12,0xE0,0x5E,0x00,0x09,0x83,0x04,0xE0,0xB0,
++    0x90,0xB5,0x77,0x01,0x80,0x16,0xC0,0x0C,0x16,0x32,0x9C,0x36,0x70,0x01,0x88,0x06,
++    0x30,0x09,0xC0,0x5C,0x90,0x33,0xC0,0x5C,0xD2,0x0B,0x40,0x8A,0x18,0x0B,0x32,0x01,
++    0x36,0x42,0x81,0x01,0x81,0x4C,0x80,0x01,0x83,0x44,0x00,0x37,0xC4,0x3C,0x10,0x32,
++    0xD0,0x6E,0xC0,0x44,0xC0,0x03,0xC8,0x44,0x32,0x00,0x72,0x00,0x82,0x43,0x40,0x42,
++    0x0C,0x41,0x00,0x0B,0x47,0x0B,0x10,0xF9,0x90,0x21,0x18,0x8A,0x00,0x0B,0xC8,0x6C,
++    0x02,0x00,0xC5,0x08,0x02,0x00,0x53,0x0A,0xC4,0x40,0xC0,0x00,0xC0,0x48,0x74,0x01,
++    0x88,0x66,0x10,0x01,0x78,0x02,0x02,0x37,0x18,0x01,0x00,0x1C,0x04,0x7C,0xE0,0x00,
++    0xE2,0x48,0xE4,0x90,0x95,0x95,0x12,0x12,0xD9,0xB6,0x07,0x07,0xDF,0x6C,0x00,0x10,
++    0xC1,0x90,0x5E,0xB2,0xC4,0x90,0x36,0xA2,0x18,0x01,0x00,0x9F,0x30,0x3A,0x13,0x01,
++    0xF0,0xD2,0x3D,0x01,0xFC,0x3A,0x16,0xBA,0xD0,0x06,0x00,0x14,0x3E,0x01,0xF8,0x7A,
++    0x10,0xBA,0xEC,0x06,0x04,0x54,0xE0,0x00,0xE3,0x48,0x34,0x12,0xE4,0x90,0x34,0xA2,
++    0xE2,0xD8,0x92,0xDD,0x17,0x1A,0xDD,0x4E,0xC4,0x3C,0x10,0x32,0x80,0x06,0xC1,0x44,
++    0xC6,0x03,0x48,0x00,0x88,0x1E,0xC0,0x4C,0xC8,0x03,0x42,0x31,0x88,0xBE,0xC7,0x4C,
++    0xC8,0x03,0x42,0x31,0x89,0x26,0x40,0x12,0x40,0x0B,0x10,0x81,0x18,0x8A,0x00,0x0B,
++    0xCF,0x6C,0x00,0x00,0xC0,0x00,0x4A,0xEA,0xC0,0x00,0xCA,0x64,0x32,0x5A,0xD1,0x4B,
++    0xD7,0x7C,0xB8,0xFF,0xE3,0x67,0xE7,0xB0,0x90,0xB5,0xC3,0x3C,0x14,0x32,0xEC,0xAE,
++    0x43,0xBA,0x30,0x5A,0x4A,0xCC,0x84,0x01,0x00,0x0B,0x40,0xAA,0x48,0xCC,0x1E,0x0B,
++    0x52,0xCC,0x18,0x0B,0x54,0xCC,0x1A,0x0B,0x56,0xCC,0x04,0x0B,0x4E,0x8A,0x50,0xD4,
++    0x00,0x53,0x58,0xCC,0x0F,0x0B,0x36,0xB7,0xAA,0x85,0xD8,0xE3,0x1A,0x0A,0x03,0x48,
++    0xC5,0x50,0x0C,0x49,0x02,0x48,0xC4,0x88,0xE8,0xD3,0x50,0x11,0xC0,0x4E,0x10,0x01,
++    0x00,0x2F,0x40,0x1C,0x04,0x5C,0xE0,0x48,0xE2,0x00,0xE4,0x90,0x95,0x95,0x12,0x12,
++    0xD8,0xBE,0x17,0x01,0x00,0x87,0x00,0x00,0x80,0x60,0x07,0x01,0x48,0xE0,0x06,0x00,
++    0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,0xF8,0xFB,0x07,0x00,0x40,0x1C,0x00,0x5C,
++    0xE4,0x00,0xE4,0x48,0xE2,0x90,0x92,0x95,0x17,0x12,0xDD,0xBE,0xEF,0x85,0xA8,0x85,
++    0x30,0x6A,0xF0,0x2C,0x30,0x22,0x30,0x8A,0x31,0xFA,0x30,0xC2,0xB9,0xFF,0xDF,0xB7,
++    0x31,0xDA,0x31,0x92,0x31,0x4A,0x31,0x02,0xBC,0xFF,0xE7,0xCF,0xE8,0x85,0x37,0x0A,
++    0x8D,0x01,0x86,0x01,0x02,0x5F,0xC8,0x5B,0x58,0x31,0x88,0x46,0x40,0xFA,0x47,0x0B,
++    0x10,0x81,0x18,0x8A,0x00,0x0B,0x40,0x0B,0x18,0x8A,0x00,0x0B,0x3E,0x82,0xCB,0x1B,
++    0x5F,0x01,0x88,0x86,0x38,0x82,0xAB,0x85,0xDA,0x5B,0xD8,0x4B,0x1F,0x5A,0x4A,0xC2,
++    0xC7,0x08,0x52,0xC2,0xC0,0x00,0x14,0x01,0x00,0x27,0x40,0x24,0x04,0x64,0xE0,0x00,
++    0xE2,0x48,0xE4,0x90,0x17,0xD2,0x9C,0xC6,0xEF,0x85,0xA8,0xBD,0x80,0x15,0x34,0x62,
++    0x37,0xBA,0xD8,0x33,0xE8,0x03,0x09,0x01,0x18,0x4A,0x2E,0x01,0x40,0x29,0x90,0x16,
++    0x1F,0x0B,0x1D,0x2B,0x07,0x6F,0x00,0x09,0xEA,0x02,0x38,0x00,0xAF,0x26,0x50,0x52,
++    0x58,0x03,0x1F,0x82,0x18,0x03,0x05,0x27,0x57,0x3A,0x5F,0x03,0x18,0x92,0x1E,0x82,
++    0x1D,0x03,0x1D,0x0B,0x30,0x0A,0xC1,0x14,0xBC,0xFF,0xE7,0xE7,0x25,0x2B,0x59,0x03,
++    0x28,0x01,0x00,0x17,0x43,0x00,0xE2,0x68,0x96,0x6D,0x3F,0x08,0x8D,0x0E,0x10,0xAA,
++    0x9B,0xC6,0xAF,0x2B,0x73,0xCA,0x4E,0x04,0x00,0x83,0xC7,0x14,0x0A,0x59,0xCB,0x00,
++    0x0A,0x48,0xC2,0x00,0xF7,0x03,0x08,0x83,0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,
++    0xBC,0xFF,0xDF,0x87,0x30,0x1A,0xB9,0x04,0x30,0x4A,0x01,0x11,0xD7,0x14,0xB8,0xFF,
++    0xD8,0xFF,0x06,0x09,0xA7,0x01,0x8D,0x03,0x48,0x82,0x46,0x43,0x10,0x11,0x18,0x82,
++    0x00,0x43,0x00,0x41,0x01,0x83,0x45,0x83,0x08,0xF9,0x8F,0x19,0x19,0x42,0x00,0x83,
++    0x87,0x2D,0xE8,0x85,0x3F,0x82,0xAB,0xC5,0xD8,0x53,0x90,0x04,0xDC,0x53,0x32,0xB2,
++    0xE9,0x53,0x54,0x91,0x9E,0xBE,0x12,0x31,0xE0,0x92,0x52,0x01,0x8E,0x9E,0x52,0x02,
++    0xC0,0x28,0x34,0x12,0x91,0xE1,0x19,0xC1,0x8E,0x01,0xF4,0x1A,0xE8,0x63,0x3A,0x11,
++    0x10,0x1A,0xDD,0x16,0xD8,0xD8,0x38,0x1C,0xA9,0x7B,0x1E,0xD1,0xEE,0x63,0xF4,0x1A,
++    0x15,0x32,0x13,0x9A,0xE0,0x16,0xC8,0xD8,0x38,0x1C,0xB2,0x7B,0x30,0x01,0x38,0x01,
++    0x1C,0x01,0x30,0xE2,0x00,0x27,0x21,0x01,0x00,0xE7,0x18,0x01,0xF0,0x5A,0x5F,0x01,
++    0xED,0x4E,0x10,0x9A,0xE8,0x06,0x30,0xF2,0xE8,0x5B,0x5E,0x01,0x80,0x76,0x40,0x9C,
++    0xF0,0xD8,0x02,0x9C,0x00,0x57,0x58,0x01,0xD5,0x46,0x10,0xDA,0xD0,0x06,0x30,0xFA,
++    0xF0,0x5B,0x58,0x01,0x80,0x16,0x40,0x9C,0xE0,0xD8,0x02,0x9C,0xE4,0x68,0xE5,0x90,
++    0xE7,0x20,0x93,0x25,0x2F,0xA2,0x9B,0x06,0x32,0x1A,0xE3,0xD8,0x94,0xDD,0x36,0xE2,
++    0xE5,0x04,0x28,0x22,0x98,0xBE,0x7E,0x14,0xC8,0x90,0x3C,0x14,0x7E,0x14,0xCA,0x90,
++    0x3E,0x14,0xEA,0x43,0x40,0x01,0x80,0x0E,0xF6,0x00,0xAA,0x43,0xF0,0x43,0x40,0x01,
++    0x82,0x0E,0xF0,0x00,0xB7,0x43,0xE8,0xC5,0xAC,0xBD,0x87,0x15,0x30,0x62,0x30,0xBA,
++    0xEF,0x2B,0xDB,0x33,0xDB,0x03,0x1B,0x42,0x00,0x08,0xC2,0x14,0xC4,0x40,0x48,0x8A,
++    0xC0,0x00,0x82,0x0C,0x37,0x02,0x81,0x01,0xC4,0x0B,0x10,0x01,0x18,0x8A,0x80,0x0B,
++    0x00,0x21,0xEE,0x02,0x44,0x01,0x80,0x1E,0x09,0x09,0x30,0xDA,0x30,0x52,0x31,0x42,
++    0xBF,0xFF,0xD7,0xC7,0x30,0x1A,0xB9,0x04,0x08,0x01,0x00,0x19,0xD7,0x14,0xB8,0xFF,
++    0xDA,0x3F,0x02,0x41,0xE9,0x0A,0x30,0x1A,0x30,0xD2,0xC1,0x0C,0xBC,0xFF,0xDF,0x7F,
++    0x31,0x1A,0x31,0x4A,0xD0,0x14,0xC0,0x0C,0xBD,0xFF,0xF7,0xB7,0x50,0x02,0x1C,0x09,
++    0xC0,0x83,0x40,0x01,0x8B,0x5E,0xE0,0x68,0x95,0x6D,0x5F,0x0B,0x03,0x0F,0xE0,0x68,
++    0x90,0x6D,0x37,0xC2,0x00,0x42,0x15,0x0A,0x8D,0x0E,0x10,0xAA,0x99,0xBE,0x37,0x82,
++    0x74,0x92,0x13,0x2A,0x93,0xE6,0xA8,0x2B,0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,
++    0xBE,0xFF,0xD7,0x47,0x30,0x1A,0xB9,0x04,0x30,0x4A,0x01,0x11,0xD7,0x14,0xB8,0xFF,
++    0xD8,0xBF,0xC0,0x14,0x0A,0x59,0xCB,0x00,0x0A,0x48,0xC2,0x00,0xF7,0x03,0x08,0x83,
++    0x05,0x41,0x00,0x83,0x47,0x83,0x09,0xF9,0x88,0x19,0x18,0x42,0x01,0x83,0x39,0xBF,
++    0xE1,0x0B,0x31,0x02,0x80,0x01,0x4D,0x01,0x86,0x1E,0xC9,0x0B,0x49,0x09,0x88,0x06,
++    0x0E,0x11,0x88,0x0B,0xA8,0x2B,0x83,0x9B,0x4F,0x04,0x01,0x83,0x50,0x0A,0xCB,0x14,
++    0xDC,0x03,0xC1,0x48,0xE7,0x02,0x0A,0x83,0x31,0xDA,0x31,0x52,0x08,0x01,0x00,0x09,
++    0xBC,0xFF,0xD7,0xC7,0x30,0x1A,0xB9,0x04,0x30,0x4A,0x01,0x11,0xD7,0x14,0xB8,0xFF,
++    0xD0,0x3F,0x07,0x41,0x01,0x83,0x45,0x83,0x08,0xF9,0x8F,0x19,0x19,0x42,0x00,0x83,
++    0x38,0x77,0x08,0x01,0x88,0x0B,0x86,0x8B,0x3F,0x57,0xA8,0x85,0x84,0x9D,0x34,0x22,
++    0x33,0x6A,0xD8,0x73,0xD8,0x43,0x81,0x34,0x31,0x12,0x93,0xE1,0x92,0x94,0x48,0x72,
++    0x32,0x02,0xC3,0x18,0x4B,0x32,0x22,0x0A,0x8B,0x8C,0xC8,0x43,0x00,0x00,0x82,0x1C,
++    0x00,0x01,0x80,0x14,0x37,0x42,0x81,0x01,0x82,0x84,0xC0,0x03,0x5C,0x7B,0x35,0x32,
++    0x3F,0x20,0x5A,0x43,0x18,0x3A,0x60,0x01,0xD1,0x46,0x40,0xFA,0x18,0x3A,0xB8,0x0C,
++    0x37,0x82,0x23,0xD9,0x00,0x02,0xE1,0x84,0x80,0x03,0x03,0x47,0x46,0xD2,0x19,0x02,
++    0x18,0x3A,0xB8,0x0C,0x30,0x82,0x23,0x21,0x18,0x02,0xE1,0x84,0x80,0x03,0x3B,0x01,
++    0x19,0x7B,0x37,0x42,0x80,0x01,0x85,0x7C,0xC0,0x03,0x84,0x54,0xC0,0x7C,0x20,0x09,
++    0xB8,0x22,0xA0,0x4C,0x34,0x42,0x81,0x01,0x86,0x74,0x18,0x3B,0xB8,0x44,0xC0,0x74,
++    0x18,0x3B,0xBC,0x3C,0x31,0x42,0x81,0x01,0x84,0x6C,0xA0,0x3B,0xCA,0x43,0x45,0x00,
++    0x86,0x2C,0x00,0x01,0xFB,0x22,0x82,0x00,0x81,0x24,0xE8,0x43,0x40,0x29,0xC0,0xBE,
++    0x03,0x01,0x30,0x22,0x3B,0x04,0x39,0x04,0x20,0x01,0x00,0x77,0x00,0x01,0x00,0x47,
++    0x40,0x7C,0x00,0xFC,0x40,0x7C,0x00,0xBC,0xE4,0x90,0xE4,0x48,0xE2,0xD8,0xE4,0x00,
++    0x95,0x05,0x12,0x82,0xDB,0xA6,0xE7,0x20,0x90,0x25,0xC3,0x34,0x17,0x22,0xDC,0x6E,
++    0xF8,0x94,0xE0,0x8C,0x00,0x01,0x80,0x5C,0x00,0xAF,0x05,0x01,0x34,0x32,0x34,0x22,
++    0xC8,0x5C,0x00,0x09,0x00,0x42,0xCC,0x0C,0x80,0x64,0x10,0x42,0x81,0x7E,0xE3,0x53,
++    0x50,0x01,0x80,0x2E,0xC8,0x34,0xC0,0x5C,0xF4,0x48,0x12,0x42,0x88,0x06,0x30,0xB2,
++    0x1A,0x01,0x00,0x87,0x41,0xCC,0x41,0x14,0xD0,0x40,0x94,0x15,0x00,0x14,0xC9,0x1C,
++    0x10,0x52,0xD4,0x3E,0x32,0x02,0xE3,0x00,0x94,0x05,0x36,0x22,0x34,0x82,0xC3,0x00,
++    0x94,0x05,0x30,0x32,0xCC,0x2C,0x10,0x52,0xE8,0x3E,0x01,0x7F,0x00,0x01,0x00,0x42,
++    0x48,0xE0,0x06,0x00,0x38,0xA0,0x03,0x00,0xAA,0xAA,0xAA,0xAA,0x18,0x00,0x04,0x42,
++    0x00,0xF0,0x00,0x01,0x68,0xB8,0x03,0x00,0x28,0x60,0x00,0x00,0xCC,0x4B,0x13,0x8A,
++    0xE7,0x1E,0x58,0x43,0xC8,0x64,0x18,0x0A,0x18,0x4B,0xCF,0x6C,0xE8,0x4B,0x4A,0x09,
++    0x88,0x16,0xC8,0x6C,0x02,0x09,0xAC,0x43,0xCC,0x54,0x10,0x52,0xE8,0xBE,0x08,0x09,
++    0xD4,0x44,0x00,0xCA,0x18,0x8A,0x88,0x44,0x00,0x8F,0xC8,0x24,0x10,0x52,0xD4,0x76,
++    0xCA,0x6C,0xE8,0x4B,0x48,0x09,0x88,0x16,0xCC,0x6C,0x00,0x09,0xA8,0x43,0xCA,0x4C,
++    0x10,0x52,0xD4,0x26,0x08,0x09,0xD0,0x3C,0x00,0xCA,0x1C,0x8A,0x8D,0x3C,0xE0,0x20,
++    0xE2,0xF8,0xE5,0xD8,0x95,0xDD,0x12,0x9A,0xD8,0x66,0xC5,0x7C,0xC8,0x03,0x44,0x01,
++    0x83,0x2E,0x32,0x02,0x40,0x11,0xC8,0x2E,0x33,0x0A,0x33,0x82,0x83,0x07,0xC8,0xD7,
++    0x90,0x05,0x00,0x07,0x03,0x01,0x00,0x88,0xD0,0x20,0x13,0x01,0x01,0x57,0x01,0x67,
++    0x40,0x01,0xE8,0x7E,0x0B,0x01,0xF0,0x0A,0xDC,0x1C,0x10,0xCA,0xD2,0xB6,0xE0,0x18,
++    0x10,0xCA,0xEC,0x16,0xD1,0x48,0x00,0x0C,0x00,0x87,0x48,0x01,0xE8,0x76,0x08,0x09,
++    0x00,0x0C,0x01,0x5F,0x0B,0x01,0xF0,0x0A,0x10,0x0A,0xD4,0x16,0xD1,0x48,0x00,0x0C,
++    0x00,0x27,0x48,0x01,0xD0,0x16,0x08,0x01,0x19,0x4A,0x06,0x0C,0x0B,0x01,0xF0,0x0A,
++    0xDC,0x24,0x10,0xCA,0xD0,0x1E,0xC8,0x14,0xE6,0x48,0x92,0x4D,0x8D,0x14,0xE0,0x20,
++    0xE2,0x90,0x92,0x95,0x16,0x92,0xDD,0x9E,0x00,0x4F,0x00,0x01,0x08,0x01,0x00,0x27,
++    0x05,0x0C,0xE1,0x20,0xE2,0xF8,0xE5,0x00,0x95,0x05,0x12,0x82,0xD8,0xC6,0xC7,0x5C,
++    0xE2,0x00,0x92,0x05,0x80,0x5C,0xC8,0x34,0xC4,0x5C,0x10,0x42,0xD2,0x06,0x38,0x27,
++    0xC9,0x43,0x41,0x71,0xC9,0x0E,0x00,0x71,0x88,0x43,0xC1,0x14,0xCC,0x4B,0x41,0x00,
++    0xC6,0x40,0x90,0x05,0x8A,0x43,0x41,0x81,0xCA,0x0E,0x00,0x81,0x88,0x43,0x01,0x01,
++    0x29,0x44,0x37,0x44,0xC0,0x74,0xC8,0x44,0x18,0x0B,0xCE,0x74,0xC4,0x3C,0x18,0x43,
++    0x87,0x9D,0xE8,0x85,0xA8,0x85,0x33,0x2A,0x30,0x62,0x30,0xB2,0x31,0x0A,0x31,0x42,
++    0xBA,0xFF,0xEF,0xCF,0x48,0x6A,0x03,0x01,0x81,0x43,0x30,0x92,0x31,0x0A,0x31,0x42,
++    0xBB,0xFF,0xEF,0x1F,0xEE,0x03,0x41,0x41,0x92,0x0E,0xE0,0x00,0xAB,0x03,0xE9,0x85,
++    0x10,0x01,0x00,0x37,0x0A,0x01,0xE0,0x48,0x90,0x4D,0x4C,0xA1,0xCA,0xDE,0xE7,0x90,
++    0x94,0x95,0x14,0x12,0xCB,0xB6,0x3F,0x82,0x38,0x18,0x78,0xD8,0x14,0x09,0x00,0xD2,
++    0x97,0x95,0x1E,0xF9,0x08,0xD8,0x00,0xC2,0x5E,0xEA,0xC2,0x00,0x48,0x09,0x88,0x66,
++    0x44,0x0B,0x18,0x8A,0x02,0x0B,0x40,0x0B,0x1A,0x8A,0x04,0x0B,0x44,0x0B,0x1C,0x8A,
++    0x06,0x0B,0x44,0x0B,0x1E,0x8A,0x04,0x0B,0x38,0x82,0x4B,0x01,0x8A,0x66,0x40,0x0B,
++    0x1A,0x8A,0x04,0x0B,0x44,0x0B,0x1C,0x8A,0x06,0x0B,0x44,0x0B,0x1E,0x8A,0x04,0x0B,
++    0x40,0x0B,0x18,0x8A,0x03,0x0B,0x38,0x82,0x48,0x11,0x88,0x66,0x44,0x0B,0x18,0x8A,
++    0x02,0x0B,0x40,0x0B,0x1A,0x8A,0x04,0x0B,0x44,0x0B,0x1C,0x8A,0x06,0x0B,0x44,0x0B,
++    0x1E,0x8A,0x00,0x0B,0x38,0x82,0x4B,0x19,0x88,0xE6,0x47,0x0B,0x18,0x8A,0x04,0x0B,
++    0x44,0x0B,0x1C,0x8A,0x06,0x0B,0x44,0x0B,0x1E,0x8A,0x04,0x0B,0x40,0x0B,0x1A,0x8A,
++    0x03,0x0B,0x3A,0x82,0xAC,0x8D,0x87,0x3D,0xC0,0x3C,0xC8,0x3C,0x4C,0x00,0x00,0x00,
++    0xC0,0x00,0x3A,0x00,0x4A,0xDA,0x71,0x00,0xC1,0x28,0x42,0xDA,0x44,0x0B,0x90,0x4D,
++    0x88,0x34,0x58,0x0B,0x90,0x4D,0x8C,0x2C,0x5C,0x0B,0x92,0x4D,0x8C,0x24,0x58,0x0B,
++    0x90,0x4D,0x8C,0x1C,0x54,0x0B,0x96,0x75,0x4A,0xA2,0x41,0x53,0x90,0x95,0x94,0x14,
++    0x44,0x53,0x90,0xBD,0x44,0x13,0x92,0x95,0x91,0x0C,0x58,0x7A,0x98,0x01,0x52,0xD3,
++    0x90,0x95,0x94,0x04,0x10,0x09,0x00,0x13,0xA8,0x10,0x1C,0x13,0x12,0x81,0x18,0x13,
++    0x18,0x13,0x14,0x79,0x11,0x13,0x16,0x01,0x00,0x53,0x12,0x89,0x02,0x53,0x40,0x0B,
++    0x10,0x81,0x19,0x8A,0x07,0x0B,0x02,0xF9,0x80,0x89,0x17,0xC3,0x07,0x09,0xB8,0xFF,
++    0xFF,0x7F,0x03,0xF9,0x80,0x89,0x14,0xC3,0x07,0x09,0xB8,0xFF,0xF8,0x4F,0x03,0x19,
++    0x11,0x00,0x00,0x43,0x07,0x09,0xB8,0xFF,0xF8,0x1F,0x0B,0x11,0xC7,0x3C,0xB8,0xFF,
++    0xF8,0x5F,0x23,0xA1,0x01,0x01,0x40,0x4B,0x30,0x48,0xA8,0x16,0xE7,0x20,0x93,0x25,
++    0x03,0x0F,0xF0,0x20,0x92,0x25,0xE7,0x00,0x90,0x05,0x46,0x51,0x98,0x9E,0x0F,0x09,
++    0xC7,0x3C,0xB8,0xFF,0xF8,0xCF,0x42,0x82,0xC8,0x34,0x00,0x0B,0xC8,0x2C,0x18,0x0B,
++    0xCA,0x24,0x18,0x0B,0xCC,0x1C,0x18,0x0B,0x10,0x33,0x4E,0x62,0xD2,0x14,0x00,0x53,
++    0x00,0x7B,0xC8,0x0C,0x00,0x0B,0x4A,0x42,0xC2,0x04,0x88,0x01,0x10,0x43,0x60,0xA1,
++    0xC8,0x16,0x00,0x09,0x87,0x45,0xE8,0x85,0x07,0x01,0x38,0xDF,0x00,0xF0,0x00,0x01,
++    0x80,0x00,0x00,0x42,0x08,0x01,0x00,0x42,0x00,0x01,0x00,0x42,0x18,0x00,0x04,0x42,
++    0x00,0x0F,0x00,0x26,0xF8,0x48,0x48,0x21,0x94,0xDE,0x3F,0x58,0xA8,0x0E,0x00,0x14,
++    0xE6,0x00,0x3C,0x48,0x80,0x06,0x80,0x13,0x38,0x82,0x4B,0x01,0x86,0x5E,0x38,0x18,
++    0x80,0x16,0x80,0x13,0xE2,0x00,0xF2,0x48,0x48,0x11,0x98,0x26,0x38,0x18,0xAC,0x16,
++    0x04,0x14,0xE0,0x00,0xF7,0x48,0x3C,0x1F,0x17,0x01,0x38,0x77,0x16,0x01,0x38,0xFF,
++    0x10,0x01,0x48,0x18,0x11,0x5A,0x9C,0x66,0x54,0x18,0x10,0x5A,0x98,0x8E,0x18,0x01,
++    0x32,0xE2,0x04,0x77,0x30,0x1A,0x18,0x5A,0xA0,0xE6,0x11,0x01,0x44,0x18,0x12,0x5A,
++    0x98,0x8E,0x49,0x18,0x10,0x5A,0x9C,0xE6,0x54,0x18,0x10,0x5A,0x9C,0x0E,0x30,0xA2,
++    0x06,0xFF,0x49,0x18,0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD6,0x00,0x0C,0x92,0x4A,0x18,
++    0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD4,0x00,0x0A,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,
++    0x0E,0x58,0xD2,0x00,0x08,0x92,0x4A,0x18,0x10,0x5A,0x9C,0x0E,0x0E,0x58,0xD0,0x00,
++    0x0E,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD6,0x00,0x0C,0x92,0x42,0x18,
++    0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD4,0x00,0x0A,0x92,0x42,0x18,0x10,0x5A,0x9C,0x0E,
++    0x06,0x58,0xD2,0x00,0x0A,0x92,0xD2,0x08,0x90,0x06,0x30,0x0A,0x08,0x92,0x32,0x82,
++    0x3A,0x82,0x03,0xEF,0x78,0x50,0x86,0x06,0x10,0x4A,0x82,0x18,0x9A,0x06,0x10,0x02,
++    0x00,0x9A,0x12,0x01,0x30,0xE2,0x4C,0x18,0x11,0x5A,0x9C,0x6E,0x54,0x18,0x10,0x5A,
++    0x9F,0x96,0x10,0xE1,0x08,0x48,0xD4,0x95,0x54,0x18,0x10,0x5A,0x9C,0x66,0x08,0x48,
++    0x8C,0x90,0x14,0x5A,0x9C,0x46,0x08,0x48,0x8C,0x90,0x14,0x5A,0x9C,0x26,0x08,0x48,
++    0x84,0xD6,0x89,0x90,0x04,0x07,0x48,0x48,0x4C,0x18,0x16,0x5A,0x9E,0x0E,0x08,0x58,
++    0xD2,0x00,0x0E,0x92,0x4C,0x18,0x14,0x5A,0x9C,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,
++    0x4C,0x18,0x12,0x5A,0x9A,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,0x4C,0x18,0x10,0x5A,
++    0x98,0x0E,0x08,0x58,0xD2,0x00,0x0E,0x92,0x44,0x18,0x16,0x5A,0x9E,0x0E,0x00,0x58,
++    0xD2,0x00,0x0E,0x92,0x44,0x18,0x14,0x5A,0x9C,0x0E,0x00,0x58,0xD2,0x00,0x0E,0x92,
++    0x92,0xCE,0x46,0x18,0x10,0x5A,0x9C,0x0E,0x06,0x58,0xD2,0x00,0x0A,0x92,0xD2,0x08,
++    0x90,0x06,0x30,0x0A,0x32,0x1A,0x0B,0x92,0x80,0xD8,0x32,0x82,0x9A,0x0E,0x10,0x02,
++    0x58,0x01,0xA8,0x06,0x13,0x4A,0x3A,0x82,0x32,0x1A,0x83,0xD8,0x9A,0x06,0x10,0x02,
++    0xA8,0x0D,0x00,0x01,0x36,0x02,0x36,0x02,0xEB,0x15,0x30,0xAA,0x81,0x07,0xC0,0x17,
++    0x30,0x72,0x05,0x28,0x32,0x4A,0x33,0x9A,0x46,0x00,0x06,0x00,0x30,0x2A,0x84,0xC5,
++    0xAF,0x05,0xB9,0xE7,0xF3,0x6F,0xE4,0x05,0x3A,0x01,0x40,0x48,0x30,0xB2,0x35,0x01,
++    0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,0x2E,0x06,
++    0xEA,0x01,0x02,0x48,0x33,0x6A,0x3C,0x82,0x36,0x22,0x30,0x02,0x31,0x02,0x36,0x02,
++    0xBA,0xDF,0xD7,0x0F,0x43,0x02,0x38,0x82,0x88,0x40,0x00,0x01,0x40,0x12,0x48,0x1A,
++    0xF3,0x5D,0x3D,0x82,0x00,0x68,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x30,0x01,0x10,
++    0x39,0x82,0xA3,0x85,0x33,0xA2,0xF3,0x20,0xC3,0x2B,0xE1,0x20,0x10,0x5A,0x95,0x06,
++    0x33,0xEA,0xE8,0x1A,0x07,0xD8,0xC2,0x18,0xE0,0x85,0x39,0xC2,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x20,0x03,0x42,0x80,0x20,0x03,0x42,
++    0x80,0x20,0x04,0x42,0x80,0x20,0x03,0x42,0x80,0xA0,0x04,0x42,0x80,0xA0,0x02,0x42,
++    0x80,0xA0,0x04,0x42,0x80,0xA0,0x02,0x42,0x80,0xA0,0x04,0x42,0x80,0xA0,0x02,0x42,
++    0x80,0x20,0x05,0x42,0x80,0xA0,0x02,0x42,0x80,0xA0,0x05,0x42,0x80,0x20,0x02,0x42,
++    0x80,0x20,0x01,0x42,0x80,0x20,0x01,0x42,0x80,0xA0,0x01,0x42,0x80,0xA0,0x01,0x42,
++    0x80,0xA0,0x01,0x42,0x10,0x20,0x08,0x40,0x40,0x08,0x20,0x10,0x10,0x20,0x08,0x40,
++    0x40,0x08,0x20,0x40,0x10,0x20,0x00,0x08,0x08,0xC1,0x02,0x42,0x08,0x81,0x02,0x42,
++    0x08,0x81,0x03,0x42,0x08,0x41,0x03,0x42,0x08,0x01,0x03,0x42,0x08,0x81,0x02,0x42,
++    0x08,0x41,0x02,0x42,0x08,0xC1,0x00,0x42,0x08,0x01,0x02,0x42,0x08,0x01,0x01,0x42,
++    0x08,0xC1,0x01,0x42,0x08,0x41,0x01,0x42,0x08,0x81,0x01,0x42,0x08,0x81,0x01,0x42,
++    0x08,0x41,0x01,0x42,0x08,0xC1,0x02,0x42,0x08,0x01,0x01,0x42,0x08,0x01,0x03,0x42,
++    0x08,0xC1,0x00,0x42,0x68,0x68,0x50,0x60,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,
++    0x50,0x50,0x00,0x00,0x00,0x08,0xF8,0x0F,0xFF,0x07,0xF8,0xFF,0x07,0xF8,0x0F,0xF8,
++    0x08,0x00,0x08,0x08,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x28,0xB5,
++    0x39,0xC5,0x08,0x1D,0x1B,0x2B,0x3A,0x28,0x53,0xB5,0x0A,0xC5,0x00,0x08,0x01,0x00,
++    0x01,0x00,0x50,0x0D,0x52,0x1D,0x52,0xB5,0x39,0x0D,0x04,0x08,0x51,0x3D,0x53,0x1D,
++    0x51,0x3D,0x54,0x95,0x51,0x3D,0x54,0x95,0x51,0x3D,0x54,0x95,0x0B,0x3D,0x34,0x88,
++    0x51,0x3D,0x54,0x1D,0x51,0x3D,0x54,0x95,0x04,0x00,0x50,0x3D,0x50,0x1D,0x01,0x00,
++    0x00,0x00,0x00,0x00,0x54,0x2D,0x53,0x3D,0x32,0x8D,0x32,0x38,0x01,0x28,0x0A,0x45,
++    0x50,0xB5,0x53,0x95,0x00,0x00,0x00,0x00,0x52,0xA5,0x51,0xB5,0x09,0xC5,0x03,0x08,
++    0x03,0x00,0x50,0x3D,0x55,0x1D,0x51,0x0D,0x51,0x3D,0x54,0x95,0x51,0x3D,0x53,0x1D,
++    0x51,0x3D,0x54,0x95,0x51,0x0D,0x55,0x0D,0x54,0xB5,0x3A,0x0D,0x00,0x08,0x01,0x00,
++    0x53,0xA5,0x51,0x2D,0x52,0x3D,0x34,0x8A,0x1D,0x38,0x52,0x45,0x52,0x0D,0x51,0x1D,
++    0x54,0xB5,0x3A,0x0D,0x53,0xA5,0x29,0xB5,0x39,0xC5,0x08,0x1D,0x19,0x2D,0x22,0x1D,
++    0x44,0x0D,0x31,0x3D,0x23,0x95,0x09,0xC1,0x29,0xB5,0x0B,0x1D,0x1B,0x2B,0x3A,0x28,
++    0x00,0x00,0x00,0x08,0xFF,0x07,0x00,0xF8,0x08,0x00,0x10,0x10,0x08,0x10,0x10,0x10,
++    0x08,0x08,0x10,0x08,0x10,0x08,0x10,0x08,0x10,0x10,0x08,0x08,0x10,0x10,0x08,0x08,
++    0x08,0x08,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x13,0x10,0xF8,0xA7,
++    0xFC,0x47,0xFC,0xE7,0xFE,0x27,0xFE,0xC7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x01,0x40,0x01,0xE0,0x03,0x20,0x03,0xC0,0x00,0x60,0x04,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x90,
++    0x00,0x78,0x00,0x00,0xFF,0x57,0xFF,0x17,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x08,0x08,0xF8,0x07,0x08,0x00,0x08,0x08,0x00,0x00,0x78,0xE2,0x00,0x00,
++    0x00,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x00,0x05,0x00,0x78,0xE2,0x01,0x00,
++    0x00,0x00,0x01,0x01,0x88,0x40,0x02,0x00,0x00,0xE0,0x05,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
++    0xFF,0xFF,0xFF,0xFF,0xD1,0xDA,0xAA,0xA9,0x2E,0x2D,0x55,0x56,0xBB,0x43,0xAC,0x32,
++    0x99,0x21,0x8A,0x10,0x00,0x70,0x00,0x28,0x09,0x00,0x1F,0x00,0x06,0x78,0x50,0x56,
++    0xFF,0xFF,0xFF,0xFF,0xBA,0xB0,0x09,0x40,0x00,0x10,0x28,0x10,0xF1,0x7A,0x16,0x5D,
++    0x0F,0x00,0xCA,0xCA,0xFF,0xFF,0xFF,0xFF,0x36,0x17,0x48,0x01,0x02,0x00,0x02,0x05,
++    0xCF,0x5E,0x2B,0xA2,0x79,0xC9,0x5A,0x26
++};
++#define FW_INFO_SIZE	(0x18)
++#define FW_REAL_SIZE	(sizeof(fwbin))
++#define FW_BIN_SIZE		(24*1024+24)	    //24K byte
++
++#endif
++
+diff --git a/module_drivers/drivers/input/touchscreen/hyn_touch/hyn_i2c.c b/module_drivers/drivers/input/touchscreen/hyn_touch/hyn_i2c.c
+new file mode 100644
+index 000000000..576aa89dd
+--- /dev/null
++++ b/module_drivers/drivers/input/touchscreen/hyn_touch/hyn_i2c.c
+@@ -0,0 +1,99 @@
++/*
++ *
++ * FocalTech TouchScreen driver.
++ *
++ * Copyright (c) 2012-2019, FocalTech Systems, Ltd., all rights reserved.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++/************************************************************************
++*
++* File Name: focaltech_i2c.c
++*
++* Author: Focaltech Driver Team
++*
++* Created: 2016-08-04
++*
++* Abstract: i2c communication with TP
++*
++* Version: v1.0
++*
++* Revision History:
++*
++************************************************************************/
++
++/*****************************************************************************
++* Included header files
++*****************************************************************************/
++//#include "hyn_core.h"
++#include "hyn_cst3xx.h"
++
++/*****************************************************************************
++* Private constant and macro definitions using #define
++*****************************************************************************/
++#define I2C_RETRY_NUMBER                    1
++#define I2C_BUF_LENGTH                      256
++
++/*****************************************************************************
++* Private enumerations, structures and unions using typedef
++*****************************************************************************/
++
++/*****************************************************************************
++* Static variables
++*****************************************************************************/
++
++/*****************************************************************************
++* Global variable or extern global variabls/functions
++*****************************************************************************/
++
++/*****************************************************************************
++* Static function prototypes
++*****************************************************************************/
++
++/*****************************************************************************
++* functions body
++*****************************************************************************/
++extern struct cst3xx_ts_data *ts_data;
++
++int cst3xx_bus_init(struct cst3xx_ts_data *ts_data)
++{
++    HYN_FUNC_ENTER();
++    ts_data->bus_tx_buf = kzalloc(I2C_BUF_LENGTH, GFP_KERNEL);
++    if (NULL == ts_data->bus_tx_buf) {
++        HYN_ERROR("failed to allocate memory for bus_tx_buf");
++        return -ENOMEM;
++    }
++
++    ts_data->bus_rx_buf = kzalloc(I2C_BUF_LENGTH, GFP_KERNEL);
++    if (NULL == ts_data->bus_rx_buf) {
++        HYN_ERROR("failed to allocate memory for bus_rx_buf");
++        return -ENOMEM;
++    }
++    HYN_FUNC_EXIT();
++    return 0;
++}
++
++int cst3xx_bus_exit(struct cst3xx_ts_data *ts_data)
++{
++    HYN_FUNC_ENTER();
++    if (ts_data && ts_data->bus_tx_buf) {
++        kfree(ts_data->bus_tx_buf);
++        ts_data->bus_tx_buf = NULL;
++    }
++
++    if (ts_data && ts_data->bus_rx_buf) {
++        kfree(ts_data->bus_rx_buf);
++        ts_data->bus_rx_buf = NULL;
++    }
++    HYN_FUNC_EXIT();
++    return 0;
++}
+diff --git a/module_drivers/drivers/irqchip/Kconfig b/module_drivers/drivers/irqchip/Kconfig
+new file mode 100644
+index 000000000..8843b4045
+--- /dev/null
++++ b/module_drivers/drivers/irqchip/Kconfig
+@@ -0,0 +1,20 @@
++config INGENIC_INTC
++        bool "intc v1 interrupt "
++	depends on SOC_X1600
++        select IRQ_DOMAIN
++
++config IRQ_INGENIC_CPU
++        bool "cpu interrupt driver"
++	depends on SOC_X2000 || SOC_X2000_V12 || SOC_X2100 || SOC_X2500 || SOC_M300
++        select IRQ_DOMAIN
++        help
++                Support for ingenic cpu core irq handler.
++
++config INGENIC_INTC_CHIP
++        bool "intc v2 interrupt driver"
++        depends on IRQ_INGENIC_CPU
++        select IRQ_DOMAIN
++        help
++                Support for ingenic XBURST2 based SOCs, which intc is
++                near cpu core,and each logic cpu has an intc.
++
+diff --git a/module_drivers/drivers/irqchip/Makefile b/module_drivers/drivers/irqchip/Makefile
+new file mode 100644
+index 000000000..035584462
+--- /dev/null
++++ b/module_drivers/drivers/irqchip/Makefile
+@@ -0,0 +1,3 @@
++obj-$(CONFIG_INGENIC_INTC)              += irq-ingenic.o
++obj-$(CONFIG_IRQ_INGENIC_CPU)           += irq-ingenic-cpu.o
++obj-$(CONFIG_INGENIC_INTC_CHIP)         += irq-ingenic-chip.o
+diff --git a/module_drivers/drivers/irqchip/irq-ingenic-chip.c b/module_drivers/drivers/irqchip/irq-ingenic-chip.c
+new file mode 100644
+index 000000000..b58f2654c
+--- /dev/null
++++ b/module_drivers/drivers/irqchip/irq-ingenic-chip.c
+@@ -0,0 +1,560 @@
++/*
++ * Copyright (C) 2017 Ingenic Semiconductor Co., Ltd.
++ *
++ *	Author: dongsheng.qiu, dongsheng.qiu@ingenic.com bo.liu@ingenic.com
++ *
++ * This program is free software; you can redistribute	it and/or modify it
++ * under  the terms of	the GNU General	 Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++
++
++#include <linux/init.h>
++#include <linux/irq.h>
++#include <linux/sched.h>
++#include <linux/interrupt.h>
++#include <linux/bitops.h>
++#include <linux/ioport.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <linux/of.h>
++#include <linux/timex.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/irqchip.h>
++#include <linux/clk.h>
++
++#include <dt-bindings/interrupt-controller/mips-irq.h>
++
++#include <asm/io.h>
++#include <asm/mipsregs.h>
++#include <asm/irq_cpu.h>
++#include <asm/irq.h>
++
++#define PART_OFF        0x20
++#define ISR_OFF         (0x00)
++#define IMR_OFF         (0x04)
++#define IMSR_OFF        (0x08)
++#define IMCR_OFF        (0x0c)
++#define IPR_OFF         (0x10)
++
++
++struct cpu_intc_map
++{
++	unsigned int cpu_num;
++	unsigned int dev_base;
++};
++static struct cpu_intc_map cpu_intc_map[NR_CPUS];
++
++struct core_irq_chip{
++	void __iomem *iobase;
++	unsigned int next_irq_resp;
++};
++struct irq_chip_data {
++	void __iomem *iobase[NR_CPUS];
++	raw_spinlock_t  lock;
++	struct cpumask irq_idle_mask;
++	unsigned int wake_up_flag[(INTC_NR_IRQS + 31) / 32];    /*  Interrupts which can generate wakeup signal when cpu asleep. */
++	unsigned char intc_num[INTC_NR_IRQS];                   /*  Which CPU/INTC does an interrupt current connect to, */
++	struct cpumask affinity[INTC_NR_IRQS];                  /*  Which CPU does an interrupt src affinity to. */
++};
++struct core_irq_chips {
++	struct core_irq_chip *__percpu *percpu_irq_chip;
++	struct irq_chip_data chip_data;
++	int irq;
++	void __iomem *iobase; /* external intc iobase*/
++	struct clk *intc_clk;
++};
++
++static struct core_irq_chip irq_chip_buf[NR_CPUS];
++static struct core_irq_chips g_irq_chips;
++
++
++static void percpu_irq_init(struct core_irq_chips *irq_chips, unsigned int cpu_num)
++{
++	unsigned int base = 0;
++	struct core_irq_chip *irq_chip;
++	int cpu = smp_processor_id();
++	void __iomem * iobase;
++	int i;
++
++	for(i = 0;i < NR_CPUS;i++)
++	{
++		if(cpu_intc_map[i].cpu_num == cpu_num) {
++			base = cpu_intc_map[i].dev_base;
++			irq_chip = &irq_chip_buf[i];
++			break;
++		}
++	}
++
++	if(base == 0){
++		pr_err("Error: CPU[%d] don't finded intc base address\n",cpu_num);
++		return;
++	}
++
++	iobase = (void *)base;
++
++	irq_chip = &irq_chip_buf[cpu];
++
++	irq_chip->iobase = iobase;
++	irq_chip->next_irq_resp = 0;
++	irq_chips->chip_data.iobase[cpu] = iobase;
++
++	*this_cpu_ptr(irq_chips->percpu_irq_chip) = irq_chip;
++	enable_percpu_irq(irq_chips->irq, IRQ_TYPE_NONE);
++
++	pr_info("percpu irq inited.\n");
++}
++int ingenic_percpu_irq_init(int cpu_num)
++{
++	percpu_irq_init(&g_irq_chips, cpu_num);
++	return 0;
++}
++EXPORT_SYMBOL_GPL(ingenic_percpu_irq_init);
++
++static void percpu_irq_deinit(struct core_irq_chips *irq_chips)
++{
++	disable_percpu_irq(irq_chips->irq);
++}
++
++void ingenic_percpu_irq_deinit(void)
++{
++	percpu_irq_deinit(&g_irq_chips);
++}
++EXPORT_SYMBOL_GPL(ingenic_percpu_irq_deinit);
++
++
++#ifdef CONFIG_SMP
++static inline void irq_lock(struct irq_chip_data *chip)
++{
++        raw_spin_lock(&chip->lock);
++}
++
++static inline void irq_unlock(struct irq_chip_data *chip)
++{
++        raw_spin_unlock(&chip->lock);
++}
++#else
++static inline void irq_lock(struct irq_chip_data *chip) { }
++static inline void irq_unlock(struct irq_chip_data *chip) { }
++#endif
++
++
++static void xburst2_irq_unmask(struct irq_data *data)
++{
++        struct irq_chip_data *chip = (struct irq_chip_data *)irq_data_get_irq_chip_data(data);
++        void __iomem * iobase;
++	int hwirq = data->hwirq;
++        unsigned int group;
++        unsigned int bit;
++        int intc_num;
++
++        group = hwirq / 32;
++        bit = 1 << ((hwirq) & 31);
++        irq_lock(chip);
++        intc_num = chip->intc_num[hwirq];
++        iobase = chip->iobase[intc_num];
++        writel(bit, iobase + group * PART_OFF + IMCR_OFF);
++        irq_unlock(chip);
++}
++
++
++static void xburst2_irq_mask(struct irq_data *data)
++{
++        struct irq_chip_data *chip = (struct irq_chip_data *)irq_data_get_irq_chip_data(data);
++        void __iomem * iobase;
++	int hwirq = data->hwirq;
++        unsigned int group;
++        unsigned int bit;
++        int intc_num;
++
++        group = hwirq / 32;
++        bit = 1 << ((hwirq) & 31);
++        irq_lock(chip);
++        intc_num = chip->intc_num[hwirq];
++        iobase = chip->iobase[intc_num];
++        writel(bit, iobase + group * PART_OFF + IMSR_OFF);
++
++#ifdef CONFIG_SMP
++        ingenic_irq_migration(0);
++#endif
++        irq_unlock(chip);
++}
++
++static int xburst2_irq_set_wake(struct irq_data *data, unsigned int on)
++{
++        struct irq_chip_data *chip = (struct irq_chip_data *)irq_data_get_irq_chip_data(data);
++        unsigned int group = (data->irq - IRQ_INTC_BASE) / 32;
++        unsigned int bit = 1 << ((data->irq - IRQ_INTC_BASE) & 31);
++
++        irq_lock(chip);
++        if(on) {
++                chip->wake_up_flag[group] |= bit;
++        }else {
++                chip->wake_up_flag[group] &= ~bit;
++        }
++        irq_unlock(chip);
++        return 0;
++}
++
++#ifdef CONFIG_SMP
++static int xburst2_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force)
++{
++        struct irq_chip_data *chip = (struct irq_chip_data *)irq_data_get_irq_chip_data(data);
++        int hwirq = data->hwirq;
++        unsigned int cpu = cpumask_any_and(dest,cpu_online_mask);
++        void __iomem * prev_iobase;
++        void __iomem * iobase;
++        int prev_intc_num;
++        int group;
++        unsigned int bit;
++
++//      printk("########%s, %d, dest->bits %lx, cpu_online_mask->bits: %lx\n", __func__, __LINE__, dest->bits[0], cpu_online_mask->bits[0]);
++
++        irq_lock(chip);
++
++        cpumask_and(&chip->affinity[hwirq],dest,cpu_online_mask);
++
++        prev_intc_num = chip->intc_num[hwirq];
++        prev_iobase = chip->iobase[prev_intc_num];
++        iobase = chip->iobase[cpu];
++        group = hwirq / 32;
++        bit = 1 << ((hwirq) & 31);
++
++        if(!(readl(prev_iobase + PART_OFF * group + IMR_OFF) & bit)){
++                writel(bit,prev_iobase + PART_OFF * group + IMSR_OFF);
++                writel(bit,iobase + PART_OFF * group + IMCR_OFF);
++        } else {
++                writel(bit,prev_iobase + PART_OFF * group + IMSR_OFF);
++        }
++        chip->intc_num[hwirq] = cpu;
++
++        irq_unlock(chip);
++
++        return IRQ_SET_MASK_OK;
++}
++#endif
++
++static struct irq_chip xburst2_irq_chip = {
++	.name           = "XBurst2-irqchip",
++	.irq_mask       = xburst2_irq_mask,
++	.irq_mask_ack   = xburst2_irq_mask,
++	.irq_unmask     = xburst2_irq_unmask,
++	.irq_ack        = xburst2_irq_mask,
++	.irq_eoi        = xburst2_irq_unmask,
++	.irq_set_wake   = xburst2_irq_set_wake,
++#ifdef CONFIG_SMP
++	.irq_set_affinity = xburst2_set_affinity,
++#endif
++};
++
++
++static irqreturn_t xburst2_irq_handler(int irq, void *data)
++{
++	struct core_irq_chip *irq_chip = *(struct core_irq_chip **)data;
++	void __iomem * iobase = irq_chip->iobase;
++	unsigned int irq_num = 0xffffffff;
++	int n = 0,i;
++	unsigned int next_irq_resp = irq_chip->next_irq_resp;
++	unsigned int ipr = readl(iobase + (next_irq_resp / 32) * PART_OFF + IPR_OFF);
++
++	do{
++		if(irq) {
++			for(i = next_irq_resp & 31;i < 32;i++)
++			{
++				if(ipr & (1 << i))
++				{
++					irq_num = (next_irq_resp & (~31)) + i;
++					break;
++				}
++			}
++		}
++		if(irq_num != 0xffffffff)
++			break;
++		next_irq_resp = (next_irq_resp & (~31)) + 32;
++		if(next_irq_resp >= INTC_NR_IRQS)
++			next_irq_resp = 0;
++		ipr = readl(iobase + (next_irq_resp / 32) * PART_OFF + IPR_OFF);
++		n++;
++	}while(n < ((INTC_NR_IRQS + 31) / 32 + 1));
++
++	if(irq_num != 0xffffffff)
++	{
++#ifdef CONFIG_SMP
++		irq_chip->next_irq_resp = irq_num;
++#else
++		irq_chip->next_irq_resp = irq_num + 1;
++		if(irq_chip->next_irq_resp >= INTC_NR_IRQS)
++			irq_chip->next_irq_resp = 0;
++#endif
++		do_IRQ(irq_num + IRQ_INTC_BASE);
++	}else{
++		//pr_err("Error: Not Find any irq,check me %s %d.\n",__FILE__,__LINE__);
++	}
++	return IRQ_HANDLED;
++}
++
++static void __init core_irq_setup(struct core_irq_chips *irq_chips)
++{
++	struct irq_chip_data *chip = &irq_chips->chip_data;
++	int ret;
++	int i;
++
++	irq_chips->percpu_irq_chip = alloc_percpu(struct core_irq_chip *);
++	if (!irq_chips->percpu_irq_chip) {
++		pr_err("ERROR:alloc cpu intc dev percpu fail!\n");
++		return;
++	}
++
++	ret = request_percpu_irq(irq_chips->irq, xburst2_irq_handler, "xburst2-intc", irq_chips->percpu_irq_chip);
++	if(ret) {
++		pr_err("ERROR:intc request error,ret: %d check %s %d\n", ret, __FILE__,__LINE__);
++		return;
++	}
++
++	cpumask_clear(&chip->irq_idle_mask);
++	raw_spin_lock_init(&chip->lock);
++
++
++	for(i = 0;i < ARRAY_SIZE(chip->wake_up_flag);i++)
++		chip->wake_up_flag[i] = 0;
++
++	for (i = 0; i < INTC_NR_IRQS; i++) {
++		cpumask_clear(&chip->affinity[i]);
++		chip->intc_num[i] = 0;
++	}
++
++	pr_info("core irq setup finished\n");
++}
++
++static int ingenic_irq_domain_map(struct irq_domain *d, unsigned int irq,
++				irq_hw_number_t hw)
++{
++
++	irq_set_chip_data(irq, (void *)d->host_data);
++	irq_set_chip_and_handler(irq, &xburst2_irq_chip, handle_level_irq);
++
++	return 0;
++}
++
++static const struct irq_domain_ops ingenic_irq_domain_ops = {
++	.map = ingenic_irq_domain_map,
++	.xlate = irq_domain_xlate_onetwocell,
++};
++
++static int __init ingenic_intc_of_init(struct device_node *node)
++{
++	struct core_irq_chips *irq_chips = &g_irq_chips;
++	void __iomem * iobase;
++	void __iomem * iobase_ex;
++	struct irq_domain *domain;
++	struct irq_chip_data *chip = &irq_chips->chip_data;
++	int irq;
++	struct property *prop;
++	const unsigned int *vp;
++	unsigned int pv;
++	int index = 0;
++
++	if(WARN_ON(!node))
++		return -ENODEV;
++
++	iobase = of_iomap(node, 0);
++	WARN(!iobase, "Unable to map core intc iobase registers!\n");
++
++	iobase_ex = of_iomap(node, 1);
++	WARN(!iobase_ex, "Unable to map external intc iobase registers!\n");
++	irq_chips->iobase = iobase_ex;
++
++	irq = irq_of_parse_and_map(node, 0);
++	WARN(irq < 0, "Failed to get intc irq from DT!\n");
++
++	irq_chips->irq = irq;
++
++
++	of_property_for_each_u32(node, "cpu-intc-map", prop, vp, pv) {
++		if(index % 2) {
++			cpu_intc_map[index/2].dev_base = (unsigned int)iobase + pv;
++		} else {
++			cpu_intc_map[index/2].cpu_num = pv;
++		}
++
++		index ++;
++		if(index > NR_CPUS * 2 - 1) {
++			printk("parse cpu-intc-iomap, intc define in dt is too large!\n");
++			break;
++		}
++        }
++
++	core_irq_setup(irq_chips);
++
++	irq_chips->intc_clk  = clk_get(NULL, "gate_intc");
++
++	domain = irq_domain_add_legacy(node, INTC_NR_IRQS, 8, 0, &ingenic_irq_domain_ops, chip);
++	WARN(!iobase, "Unable to register IRQ domain!\n");
++
++	percpu_irq_init(irq_chips, 0);
++
++	return 0;
++}
++
++
++
++static int __init ingenic_intc_init(struct device_node *node,
++		struct device_node *parent)
++{
++	return ingenic_intc_of_init(node);
++}
++IRQCHIP_DECLARE(ingenic_intc, "ingenic,core-intc", ingenic_intc_init);
++
++
++asmlinkage void plat_irq_dispatch(void)
++{
++	unsigned long status = read_c0_status();
++	unsigned long cause = read_c0_cause();
++	volatile unsigned long r = ((status & cause) >> 8) & 0xff;
++
++	if(r) {
++		if (r & 8) {  		/* IPI */
++			do_IRQ(MIPS_CPU_IRQ_BASE + 3);
++		} else if(r & 16) {	/* OST */
++			do_IRQ(MIPS_CPU_IRQ_BASE + 4);
++		} else if (r & 4) {	/* INTC */
++			do_IRQ(MIPS_CPU_IRQ_BASE + 2);
++		} else {		/* Others */
++			do_IRQ(MIPS_CPU_IRQ_BASE + __ffs(r));
++		}
++
++	} else {
++		printk("IRQ Error, cpu: %d Cause:0x%08lx, Status:0x%08lx\n", smp_processor_id(), cause, status);
++	}
++}
++
++void ingenic_irq_migration(int lock)
++{
++	struct core_irq_chips *irq_chips = &g_irq_chips;
++	struct irq_chip_data *chip = &irq_chips->chip_data;
++	unsigned int cpu = smp_processor_id();
++	void __iomem * iobase = NULL;
++	void __iomem * prev_iobase = NULL;
++	int i;
++	struct cpumask resp_mask;
++	unsigned int ipr = 0;
++
++	if(lock){
++		irq_lock(chip);
++	}
++
++	prev_iobase = chip->iobase[cpu];
++	for(i = 0;i < INTC_NR_IRQS;i++)
++	{
++		int group = i / 32;
++		int bitcount = i & 31;
++		unsigned int bit = 1 << bitcount;
++		int resp_cpu;
++
++		if(bitcount == 0) {
++			ipr = readl(prev_iobase + group * PART_OFF + IPR_OFF);
++		}
++
++		if(ipr == 0){
++			i = (i & (~31)) + 31;
++			continue;
++		}
++
++		if(ipr & bit){
++			cpumask_and(&resp_mask,&chip->affinity[i],&chip->irq_idle_mask);
++			for_each_cpu(resp_cpu,&resp_mask){
++				if(resp_cpu != cpu){
++					//printk("migrate irq from cpu[%d] to cpu[%d], i: %d\n", cpu, resp_cpu, i);
++					iobase = chip->iobase[resp_cpu];
++					if(!(readl(prev_iobase + PART_OFF * group + IMR_OFF) & bit)){
++						writel(bit,prev_iobase + PART_OFF * group + IMSR_OFF);
++						writel(bit,iobase + PART_OFF * group + IMCR_OFF);
++					}else{
++						writel(bit,iobase + PART_OFF * group + IMSR_OFF);
++					}
++					cpumask_clear_cpu(resp_cpu,&chip->irq_idle_mask);
++					chip->intc_num[i] = resp_cpu;
++					break;
++				}
++			}
++		}
++	}
++	if(lock){
++		irq_unlock(chip);
++	}
++}
++EXPORT_SYMBOL_GPL(ingenic_irq_migration);
++
++
++void ingenic_irq_cpumask_idle(int idle)
++{
++	struct core_irq_chips *irq_chips = &g_irq_chips;
++	struct irq_chip_data *chip = &irq_chips->chip_data;
++	int cpu = smp_processor_id();
++	irq_lock(chip);
++	if(idle){
++		cpumask_set_cpu(cpu,&chip->irq_idle_mask);
++	}else{
++		cpumask_clear_cpu(cpu,&chip->irq_idle_mask);
++	}
++	irq_unlock(chip);
++}
++EXPORT_SYMBOL_GPL(ingenic_irq_cpumask_idle);
++
++
++
++static unsigned long intc_saved[4];
++extern void __enable_irq(struct irq_desc *desc, unsigned int irq, bool resume);
++
++void arch_suspend_disable_irqs(void)
++{
++        struct irq_chip_data *chip_data = &g_irq_chips.chip_data;
++        struct core_irq_chip *irq_chip = *this_cpu_ptr(g_irq_chips.percpu_irq_chip);
++	struct core_irq_chips *irq_chips = &g_irq_chips;
++
++        unsigned int *intc_wakeup = chip_data->wake_up_flag;
++        void __iomem * intc_base = irq_chip->iobase;
++	struct clk *intc_clk;
++
++
++	local_irq_disable();
++
++        intc_saved[0] = readl(intc_base + IMR_OFF);
++        intc_saved[1] = readl(intc_base + PART_OFF + IMR_OFF);
++
++        /* Mask interrupts which are not wakeup src. */
++        writel(0xffffffff & ~intc_wakeup[0], intc_base + IMSR_OFF);
++        writel(0xffffffff & ~intc_wakeup[1], intc_base + PART_OFF + IMSR_OFF);
++	if(IS_ERR(irq_chips->intc_clk))
++		irq_chips->intc_clk  = clk_get(NULL, "gate_intc");
++	if (!IS_ERR(irq_chips->intc_clk))
++		clk_prepare_enable(irq_chips->intc_clk);
++
++	intc_saved[2] = readl(irq_chips->iobase + IMR_OFF);
++	intc_saved[3] = readl(irq_chips->iobase + PART_OFF + IMR_OFF);
++
++
++	writel(0xffffffff & ~intc_wakeup[0], irq_chips->iobase + IMR_OFF);
++	writel(0xffffffff & ~intc_wakeup[1], irq_chips->iobase + PART_OFF + IMR_OFF);
++
++}
++
++void arch_suspend_enable_irqs(void)
++{
++        struct core_irq_chip *irq_chip = *this_cpu_ptr(g_irq_chips.percpu_irq_chip);
++        void __iomem * intc_base = irq_chip->iobase;
++	struct core_irq_chips *irq_chips = &g_irq_chips;
++	struct clk *intc_clk = irq_chips->intc_clk;
++
++	writel(intc_saved[2],irq_chips->iobase + IMR_OFF);
++	writel(intc_saved[3],irq_chips->iobase + PART_OFF + IMR_OFF);
++	if (!IS_ERR(intc_clk))
++		clk_disable_unprepare(intc_clk);
++
++        writel(0xffffffff & ~intc_saved[0], intc_base + IMCR_OFF);
++        writel(0xffffffff & ~intc_saved[1], intc_base + PART_OFF + IMCR_OFF);
++
++        local_irq_enable();
++}
+diff --git a/module_drivers/drivers/irqchip/irq-ingenic-cpu.c b/module_drivers/drivers/irqchip/irq-ingenic-cpu.c
+new file mode 100644
+index 000000000..169bd7bd2
+--- /dev/null
++++ b/module_drivers/drivers/irqchip/irq-ingenic-cpu.c
+@@ -0,0 +1,128 @@
++/*
++ * Copyright (C) 2014 Ingenic Semiconductor Co., Ltd.
++ *
++ *	Author: dongsheng.qiu, dongsheng.qiu@ingenic.com bo.liu@ingenic.com
++ *
++ * This program is free software; you can redistribute	it and/or modify it
++ * under  the terms of	the GNU General	 Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/irq.h>
++#include <linux/irqchip.h>
++#include <linux/irqdomain.h>
++
++#include <dt-bindings/interrupt-controller/mips-irq.h>
++
++#include <asm/irq_cpu.h>
++#include <asm/mipsregs.h>
++#include <asm/mipsmtregs.h>
++#include <asm/setup.h>
++
++static inline void unmask_ingenic_irq(struct irq_data *d)
++{
++	set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
++#ifdef CONFIG_SMP
++	ingenic_irq_cpumask_idle(1);
++#endif
++}
++
++static inline void mask_ingenic_irq(struct irq_data *d)
++{
++	clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
++#ifdef CONFIG_SMP
++	ingenic_irq_cpumask_idle(0);
++	if(d->irq != CORE_INTC_IRQ){
++		ingenic_irq_migration(1);
++	}
++#endif
++}
++
++static struct irq_chip ingenic_cpu_irq_controller = {
++	.name		= "XBurst2",
++	.irq_ack	= mask_ingenic_irq,
++	.irq_mask	= mask_ingenic_irq,
++	.irq_mask_ack	= mask_ingenic_irq,
++	.irq_unmask	= unmask_ingenic_irq,
++	.irq_eoi	= unmask_ingenic_irq,
++	.irq_disable	= mask_ingenic_irq,
++	.irq_enable	= unmask_ingenic_irq,
++};
++
++asmlinkage void __weak plat_irq_dispatch(void)
++{
++	unsigned int status = read_c0_status();
++	unsigned int cause = read_c0_cause();
++
++	unsigned long pending = ((status & cause) >> 8) & 0xff;
++	int irq;
++
++	if (!pending) {
++		spurious_interrupt();
++		return;
++	}
++
++	if(pending) {
++		if (pending & 8) {  		/* IPI */
++			do_IRQ(MIPS_CPU_IRQ_BASE + 3);
++		} else if(pending & 16) {	/* OST */
++			do_IRQ(MIPS_CPU_IRQ_BASE + 4);
++		} else if (pending & 4) {	/* INTC */
++			do_IRQ(MIPS_CPU_IRQ_BASE + 2);
++		} else {		/* Others */
++			do_IRQ(MIPS_CPU_IRQ_BASE + __ffs(pending));
++		}
++
++	} else {
++		//printk("IRQ Error, cpu: %d Cause:0x%08lx, Status:0x%08lx\n", smp_processor_id(), cause, status);
++	}
++}
++
++static int ingenic_cpu_intc_map(struct irq_domain *d, unsigned int irq,
++							 irq_hw_number_t hw)
++{
++	static struct irq_chip *chip;
++
++	chip = &ingenic_cpu_irq_controller;
++
++	irq_set_percpu_devid(irq);
++	irq_set_chip_and_handler(irq, chip, handle_percpu_devid_irq);
++
++	return 0;
++}
++
++static const struct irq_domain_ops ingenic_cpu_intc_irq_domain_ops = {
++	.map = ingenic_cpu_intc_map,
++	.xlate = irq_domain_xlate_onecell,
++};
++
++static void __init __ingenic_cpu_irq_init(struct device_node *of_node)
++{
++	struct irq_domain *domain;
++
++	/* Mask interrupts. */
++	clear_c0_status(ST0_IM);
++	clear_c0_cause(CAUSEF_IP);
++
++	domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
++								   &ingenic_cpu_intc_irq_domain_ops, NULL);
++	if (!domain)
++		panic("Failed to add irqdomain for MIPS CPU");
++}
++
++void __init ingenic_cpu_irq_init(void)
++{
++	__ingenic_cpu_irq_init(NULL);
++}
++
++int __init ingenic_cpu_irq_of_init(struct device_node *of_node,
++								struct device_node *parent)
++{
++	__ingenic_cpu_irq_init(of_node);
++	return 0;
++}
++IRQCHIP_DECLARE(cpu_intc, "ingenic,cpu-interrupt-controller", ingenic_cpu_irq_of_init);
+diff --git a/module_drivers/drivers/irqchip/irq-ingenic.c b/module_drivers/drivers/irqchip/irq-ingenic.c
+new file mode 100644
+index 000000000..a9ea35037
+--- /dev/null
++++ b/module_drivers/drivers/irqchip/irq-ingenic.c
+@@ -0,0 +1,266 @@
++/*
++ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
++ *  ingenic platform IRQ support
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under  the terms of the GNU General	 Public License as published by the
++ *  Free Software Foundation;  either version 2 of the License, or (at your
++ *  option) any later version.
++ *
++ *  You should have received a copy of the GNU General Public License along
++ *  with this program; if not, write to the Free Software Foundation, Inc.,
++ *  675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/errno.h>
++#include <linux/init.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <linux/of.h>
++#include <linux/timex.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++
++#include <linux/debugfs.h>
++#include <linux/seq_file.h>
++#include <linux/irqchip.h>
++#include <asm/io.h>
++#include <asm/mipsregs.h>
++#include <asm/irq_cpu.h>
++#include <asm/irq.h>
++
++static void __iomem *intc_base;
++static unsigned ingenic_num_chips;
++
++#define TRACE_IRQ        1
++#define PART_OFF	0x20
++
++#define ISR_OFF		(0x00)
++#define IMR_OFF		(0x04)
++#define IMSR_OFF	(0x08)
++#define IMCR_OFF	(0x0c)
++#define IPR_OFF		(0x10)
++
++#define DSR0_OFF	(0x34)
++#define DMR0_OFF	(0x38)
++#define DPR0_OFF	(0x3c)
++#define DSR1_OFF	(0x40)
++#define DMR1_OFF	(0x44)
++#define DPR1_OFF	(0x48)
++
++static irqreturn_t ingenic_cascade(int irq, void *data)
++{
++	uint32_t irq_reg;
++	unsigned i;
++
++	for (i = 0; i < ingenic_num_chips; i++) {
++		irq_reg = readl(intc_base + (i * PART_OFF) + IPR_OFF);
++		if (!irq_reg)
++			continue;
++		generic_handle_irq(__fls(irq_reg) + (i * 32) + XBURST_SOC_IRQ_BASE);
++	}
++
++	return IRQ_HANDLED;
++}
++
++static void ingenic_irq_pm_set_mask(struct irq_chip_generic *gc, uint32_t unmask)
++{
++	struct irq_chip_regs *regs = &gc->chip_types->regs;
++
++	writel(unmask, gc->reg_base + regs->enable);
++	writel(~unmask, gc->reg_base + regs->disable);
++}
++
++void ingenic_irq_suspend(struct irq_data *data)
++{
++	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
++	ingenic_irq_pm_set_mask(gc, gc->wake_active);
++}
++
++void ingenic_irq_resume(struct irq_data *data)
++{
++	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
++	ingenic_irq_pm_set_mask(gc, gc->mask_cache);
++}
++
++static int __init ingenic_intc_of_init(struct device_node *node, unsigned num_chips)
++{
++	struct irq_chip_generic *gc;
++	struct irq_chip_type *ct;
++	struct irq_domain *domain;
++	struct resource res;
++	int ret, parent_irq;
++	unsigned i;
++
++	parent_irq = irq_of_parse_and_map(node, 0);
++	if (!parent_irq)
++		return -EINVAL;
++
++	ret = of_address_to_resource(node, 0, &res);
++	if (ret < 0)
++		return ret;
++
++	ingenic_num_chips = num_chips;
++	intc_base = ioremap(res.start,
++			       ((num_chips - 1) * PART_OFF) + 0x14);
++
++	domain = irq_domain_add_legacy(node, num_chips * 32, XBURST_SOC_IRQ_BASE, 0,
++				       &irq_domain_simple_ops, NULL);
++	if (!domain)
++		pr_warn("unable to register IRQ domain\n");
++
++	for (i = 0; i < num_chips; i++) {
++		/* Mask all irqs */
++		writel(0xffffffff, intc_base + (i * PART_OFF) + IMSR_OFF);
++
++		gc = irq_alloc_generic_chip("INTC", 1, XBURST_SOC_IRQ_BASE + (i * 32),
++					    intc_base + (i * PART_OFF),
++					    handle_level_irq);
++		gc->wake_enabled = IRQ_MSK(32);
++		ct = gc->chip_types;
++		ct->regs.enable = IMCR_OFF;
++		ct->regs.disable = IMSR_OFF;
++		ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
++		ct->chip.irq_mask = irq_gc_mask_disable_reg;
++		ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
++		ct->chip.irq_set_wake = irq_gc_set_wake;
++		ct->chip.irq_suspend = ingenic_irq_suspend;
++		ct->chip.irq_resume = ingenic_irq_resume;
++#ifdef CONFIG_SPARSE_IRQ
++		irq_alloc_descs(gc->irq_base, -1, gc->num_ct, of_node_to_nid(domain->of_node));
++#endif
++		irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, IRQ_NOPROBE | IRQ_LEVEL);
++	}
++
++	if (request_irq(parent_irq, ingenic_cascade, 0, "ingenic cascade interrupt", NULL))
++		pr_err("Failed to register ingenic cascade interrupt\n");
++
++	/* enable cpu interrupt mask */
++	set_c0_status(IE_IRQ0 | IE_IRQ1);
++	return 0;
++}
++
++static int __init ingenic_intc_init(struct device_node *node,
++		struct device_node *parent)
++{
++	return ingenic_intc_of_init(node, INTC_CHIP_NUM);
++}
++IRQCHIP_DECLARE(ingenic_intc, "ingenic,ingenic-intc", ingenic_intc_init);
++
++#if 0
++/*************************************************************************
++if nand was config:
++	After cpu was woke up,the mcu should be handler
++those interruptions of GPIO0,so that it was convenient to read/write nand,
++the process of GPIO's interruption as follows
++	|----------------------------------|
++	|               GPIO		   |
++	|                 |                |
++	|      |--****--INTC---------->|   |
++	|      |   MASK       UNMASK   |   |
++	|      CPU                    MCU  |
++	|                              |   |
++	|                         MAILEBOX |
++	|      | <---------------------|   |
++	|      |                           |
++	|    ingenicdma                         |
++	|      |                           |
++	|   soft intc                      |
++	|      |                           |
++	| handler func of intc             |
++	|__________________________________|
++
++	On the contraty, when cpu will go to sleep, the cpu should be handler
++GPIO0's interruptions, it was convenient to the next step, which is that cpu was
++woke up.
++				GPIO
++				  |
++		       |---------INTC-------->|
++		       | unmask          mask |
++		       CPU                   MCU
++		       |
++		       |
++		 handler func of intc
++************************************************************************/
++
++#define IRQ_IS_GGPIO(irq)  (irq >= IRQ_GPIO0 && irq <= IRQ_GPIO_END)
++extern void mcu_gpio_register(unsigned int ggpio, unsigned int reg);
++extern void mcu_gpio_unregister(unsigned int ggpio);
++
++void ingenic_change_irq_destination(int irq, bool cpu_to_mcu, unsigned gpio_pending_reg)
++{
++	int reg = 0;
++	if (WARN((irq < 0 || irq > 63),
++				"irq %d not support switch between cpu and mcu\n",
++				irq))
++		return;
++
++	if (cpu_to_mcu) {
++		if (irq < 32) {
++			writel((1 << irq), intc_base + IMSR_OFF);
++			if (IRQ_IS_GGPIO(irq))
++				mcu_gpio_register((irq-IRQ_GPIO0), gpio_pending_reg);
++			reg = readl(intc_base + DMR0_OFF);
++			writel((reg & (~(1 << irq))), intc_base + DMR0_OFF);
++		} else {
++			writel((1 << (irq - 32)), intc_base + PART_OFF + IMSR_OFF);
++			reg = readl(intc_base + DMR1_OFF);
++			writel((reg & (~(1 << (irq - 32)))), intc_base + DMR1_OFF);
++		}
++	} else {
++		if (irq < 32) {
++			reg = readl(intc_base + DMR0_OFF);
++			writel((reg | (1 << irq)), intc_base + DMR0_OFF);
++			if (IRQ_IS_GGPIO(irq))
++				mcu_gpio_unregister((irq-IRQ_GPIO0));
++			writel((1 << irq), intc_base + IMCR_OFF);
++		} else {
++			reg = readl(intc_base + DMR1_OFF);
++			writel((reg | (1 << (irq - 32))), intc_base + DMR1_OFF);
++			writel((1 << (irq - 32)), intc_base + PART_OFF + IMCR_OFF);
++		}
++	}
++	return;
++}
++EXPORT_SYMBOL_GPL(ingenic_change_irq_destination);
++#endif
++#ifdef CONFIG_DEBUG_FS
++static inline void intc_seq_reg(struct seq_file *s, const char *name,
++	unsigned int reg)
++{
++	seq_printf(s, "%s:\t\t%08x\n", name, readl(intc_base + reg));
++}
++
++static int intc_regs_show(struct seq_file *s, void *unused)
++{
++	intc_seq_reg(s, "Status", ISR_OFF);
++	intc_seq_reg(s, "Mask", IMR_OFF);
++	intc_seq_reg(s, "Pending", IPR_OFF);
++
++	return 0;
++}
++
++static int intc_regs_open(struct inode *inode, struct file *file)
++{
++	return single_open(file, intc_regs_show, NULL);
++}
++
++static const struct file_operations intc_regs_operations = {
++	.open		= intc_regs_open,
++	.read		= seq_read,
++	.llseek		= seq_lseek,
++	.release	= single_release,
++};
++
++static int __init intc_debugfs_init(void)
++{
++	(void) debugfs_create_file("intc_regs", S_IFREG | S_IRUGO,
++				NULL, NULL, &intc_regs_operations);
++	return 0;
++}
++subsys_initcall(intc_debugfs_init);
++#endif
+diff --git a/module_drivers/drivers/md_export/Makefile b/module_drivers/drivers/md_export/Makefile
+new file mode 100644
+index 000000000..70928c85b
+--- /dev/null
++++ b/module_drivers/drivers/md_export/Makefile
+@@ -0,0 +1 @@
++obj-y += md_export.o
+\ No newline at end of file
+diff --git a/module_drivers/drivers/md_export/md_export.c b/module_drivers/drivers/md_export/md_export.c
+new file mode 100644
+index 000000000..c0da81f2f
+--- /dev/null
++++ b/module_drivers/drivers/md_export/md_export.c
+@@ -0,0 +1,3 @@
++#include <linux/sched.h>
++
++EXPORT_SYMBOL_GPL(sched_setscheduler);
+\ No newline at end of file
+diff --git a/module_drivers/drivers/media/Makefile b/module_drivers/drivers/media/Makefile
+new file mode 100644
+index 000000000..8c25d878f
+--- /dev/null
++++ b/module_drivers/drivers/media/Makefile
+@@ -0,0 +1,3 @@
++obj-y += i2c/
++obj-y += platform/
++obj-y += v4l2-core/
+diff --git a/module_drivers/drivers/media/i2c/Kconfig b/module_drivers/drivers/media/i2c/Kconfig
+new file mode 100644
+index 000000000..80dc8562e
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/Kconfig
+@@ -0,0 +1,4 @@
++
++source "module_drivers/drivers/media/i2c/ingenic-isp/Kconfig"
++source "module_drivers/drivers/media/i2c/ingenic-isp-v2/Kconfig"
++source "module_drivers/drivers/media/i2c/ingenic-cim/Kconfig"
+diff --git a/module_drivers/drivers/media/i2c/Makefile b/module_drivers/drivers/media/i2c/Makefile
+new file mode 100644
+index 000000000..b162432c6
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/Makefile
+@@ -0,0 +1,3 @@
++obj-$(CONFIG_VIDEO_INGENIC_ISP) 	+= ingenic-isp/
++obj-$(CONFIG_VIDEO_INGENIC_ISP_V2)      += ingenic-isp-v2/
++obj-$(CONFIG_VIDEO_INGENIC_CIM)		+= ingenic-cim/
+diff --git a/module_drivers/drivers/media/i2c/ingenic-cim/Kconfig b/module_drivers/drivers/media/i2c/ingenic-cim/Kconfig
+new file mode 100644
+index 000000000..7acc00919
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-cim/Kconfig
+@@ -0,0 +1,56 @@
++comment "ingenic-cim camera sensor drivers"
++
++config INGENIC_CIM_CAMERA_OV2735B
++	tristate "ov2735 camera DVP interface support"
++	depends on VIDEO_INGENIC_CIM && I2C
++	help
++	  This is a ingenic-cim camera driver for the OmniVision OV2735 sensor DVP interface
++
++config INGENIC_CIM_CAMERA_AR0144
++	tristate "ar0144 camera mipi interface support"
++	depends on VIDEO_INGENIC_CIM && I2C
++	help
++	  This is a ingenic-cim camera driver for the OmniVision AR0144 sensor MIPI interface
++
++config INGENIC_CIM_CAMERA_OV5640
++	tristate "ov5640 camera DVP interface support"
++	depends on VIDEO_INGENIC_CIM && I2C
++	help
++	  This is a ingenic-cim camera driver for the OmniVision OV5640 sensor DVP interface
++
++config INGENIC_CIM_CAMERA_SC031GS
++	tristate "sc031gs camera DVP interface support"
++	depends on VIDEO_INGENIC_CIM && I2C
++	help
++	  This is a ingenic-cim camera driver for the OmniVision SC031GS sensor DVP interface
++
++config INGENIC_CIM_CAMERA_MIPI_SC031GS
++	tristate "sc031gs camera mipi interface support"
++	depends on VIDEO_INGENIC_CIM && I2C
++	help
++	  This is a ingenic-cim camera driver for the OmniVision SC031GS sensor MIPI interface
++
++config INGENIC_CIM_CAMERA_OV5645
++	tristate "ov5645 camera mipi interface support"
++	depends on VIDEO_INGENIC_CIM && I2C
++	help
++	  This is a ingenic-cim camera driver for the OmniVision OV5645 sensor MIPI interface
++
++config INGENIC_CIM_CAMERA_OV9281
++	tristate "ov9281 camera mipi interface support"
++	depends on VIDEO_INGENIC_CIM && I2C
++	help
++	  This is a ingenic-cim camera driver for the OmniVision OV9281 sensor MIPI interface
++
++config INGENIC_CIM_CAMERA_OV9281_DVP_SNAPSHOT
++	tristate "ov9281 camera support cim snapshot"
++	depends on VIDEO_INGENIC_CIM && I2C
++	help
++	  This is a ingenic-cim camera driver for the OmniVision OV9281 sensor DVP interface
++
++config INGENIC_CIM_CAMERA_OV4689
++	tristate "ov4689 camera mipi interface support"
++	depends on VIDEO_INGENIC_CIM && I2C
++	help
++	  This is a ingenic-cim camera driver for the OmniVision OV4689 sensor MIPI interface
++
+diff --git a/module_drivers/drivers/media/i2c/ingenic-cim/Makefile b/module_drivers/drivers/media/i2c/ingenic-cim/Makefile
+new file mode 100644
+index 000000000..a353d2a3c
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-cim/Makefile
+@@ -0,0 +1,12 @@
++obj-$(CONFIG_INGENIC_CIM_CAMERA_OV2735B)		+= ov2735b.o
++obj-$(CONFIG_INGENIC_CIM_CAMERA_AR0144)			+= ar0144.o
++obj-$(CONFIG_INGENIC_CIM_CAMERA_OV5640)			+= ov5640.o
++obj-$(CONFIG_INGENIC_CIM_CAMERA_SC031GS)		+= sc031gs.o
++obj-$(CONFIG_INGENIC_CIM_CAMERA_MIPI_SC031GS)		+= sc031gs-mipi.o
++obj-$(CONFIG_INGENIC_CIM_CAMERA_OV5645)			+= ov5645.o
++obj-$(CONFIG_INGENIC_CIM_CAMERA_OV9281)			+= ov9281.o
++obj-$(CONFIG_INGENIC_CIM_CAMERA_OV9281_DVP_SNAPSHOT)	+= ov9281-dvp-snapshot.o
++obj-$(CONFIG_INGENIC_CIM_CAMERA_OV4689)			+= ov4689.o
++
++ccflags-y += -I$(srctree)/module_drivers/drivers/media/platform/ingenic-cim/
++
+diff --git a/module_drivers/drivers/media/i2c/ingenic-cim/ar0144.c b/module_drivers/drivers/media/i2c/ingenic-cim/ar0144.c
+new file mode 100644
+index 000000000..49c1a7d03
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-cim/ar0144.c
+@@ -0,0 +1,935 @@
++/*
++ * ar0144 Camera Driver
++ *
++ * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com>
++ *
++ * Based on ov772x, ov9640 drivers and previous non merged implementations.
++ *
++ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright (C) 2006, OmniVision
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/i2c.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/gpio/consumer.h>
++#include <linux/of_gpio.h>
++#include <linux/v4l2-mediabus.h>
++#include <linux/videodev2.h>
++
++#include <media/v4l2-clk.h>
++#include <media/v4l2-subdev.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-image-sizes.h>
++#include <media/v4l2-device.h>
++
++
++#include <linux/clk.h>
++#include <linux/regulator/consumer.h>
++
++#define AR0144_REG_END         0xffff
++#define AR0144_REG_DELAY       0xfffe
++#define AR0144_REG_CHIP_ID		0x3000
++#define AR0144_CHIP_ID_HIGH		0x03
++#define AR0144_CHIP_ID_LOW		0x56
++
++#define  ar0144_DEFAULT_WIDTH    640
++#define  ar0144_DEFAULT_HEIGHT   480
++
++/* Private v4l2 controls */
++#define V4L2_CID_PRIVATE_BALANCE  (V4L2_CID_PRIVATE_BASE + 0)
++#define V4L2_CID_PRIVATE_EFFECT  (V4L2_CID_PRIVATE_BASE + 1)
++
++#define ar0144_FLIP_VAL			((unsigned char)0x04)
++#define ar0144_FLIP_MASK		((unsigned char)0x04)
++
++/* whether sensor support high resolution (> vga) preview or not */
++#define SUPPORT_HIGH_RESOLUTION_PRE		1
++
++/*
++ * Struct
++ */
++struct regval_list {
++	u16 reg_num;
++	u16 value;
++};
++
++struct mode_list {
++	u16 index;
++	const struct regval_list *mode_regs;
++};
++
++struct ar0144_win_size {
++	char *name;
++	int width;
++	int height;
++	const struct regval_list *regs;
++	unsigned int mbus_code;
++};
++
++
++struct ar0144_gpio {
++	int pin;
++	int active_level;
++};
++
++struct ar0144_priv {
++	struct v4l2_subdev		subdev;
++	struct v4l2_ctrl_handler	hdl;
++	u32	cfmt_code;
++	struct v4l2_clk			*clk;
++	const struct ar0144_win_size	*win;
++
++	int				model;
++	u16				balance_value;
++	u16				effect_value;
++	u16				flag_vflip:1;
++	u16				flag_hflip:1;
++
++//	struct soc_camera_subdev_desc	ssdd_dt;
++	struct v4l2_subdev_platform_data *sd_pdata;
++	struct gpio_desc *resetb_gpio;
++	struct gpio_desc *pwdn_gpio;
++	struct gpio_desc *vcc_en_gpio;
++	int (*power)(struct i2c_client *client, int on);
++	int (*reset)(struct i2c_client *client);
++
++	struct regulator *reg;
++	struct regulator *reg1;
++};
++
++unsigned short ar0144_read_reg(struct i2c_client *client, u16 reg, unsigned char *value)
++{
++	int ret;
++	unsigned short r = cpu_to_be16(reg);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 2,
++			.buf	= value,
++		}
++	};
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++int ar0144_write_reg(struct i2c_client *client, unsigned short reg, unsigned short value)
++{
++	int ret;
++	uint8_t buf[4] = {reg >> 8, reg & 0xff, value >> 8, value & 0xff};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 4,
++		.buf	= buf,
++	};
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static struct regval_list ar0144_720p_regs_mipi[] = {
++	//mipibps 444
++	//pclk 74.00
++	//hts:0x5D0  VTS 0x338
++	//again default 0x3060 = 0x0010
++	//expo 0x3012 = 0x01F3
++	//[ar0144_720P_60FPS]
++//	{ AR0144_REG_DELAY, 200},
++	{ 0x301A, 0x00D9 }, // RESET_REGISTER
++	{ AR0144_REG_DELAY, 200},
++	{ 0x301A, 0x3058 }, // RESET_REGISTER
++	{ AR0144_REG_DELAY, 100},
++	{ 0x3F4C, 0x003F }, // PIX_DEF_1D_DDC_LO_DEF
++	{ 0x3F4E, 0x0018 }, // PIX_DEF_1D_DDC_HI_DEF
++	{ 0x3F50, 0x17DF }, // PIX_DEF_1D_DDC_EDGE
++	{ 0x30B0, 0x0028 }, // DIGITAL_TEST
++	{ AR0144_REG_DELAY, 200},
++	{ 0x3ED6, 0x3CB5 }, // DAC_LD_10_11
++	{ 0x3ED8, 0x8765 }, // DAC_LD_12_13
++	{ 0x3EDA, 0x8888 }, // DAC_LD_14_15
++	{ 0x3EDC, 0x97FF }, // DAC_LD_16_17
++	{ 0x3EF8, 0x6522 }, // DAC_LD_44_45
++	{ 0x3EFA, 0x2222 }, // DAC_LD_46_47
++	{ 0x3EFC, 0x6666 }, // DAC_LD_48_49
++	{ 0x3F00, 0xAA05 }, // DAC_LD_52_53
++	{ 0x3EE2, 0x180E }, // DAC_LD_22_23
++	{ 0x3EE4, 0x0808 }, // DAC_LD_24_25
++	{ 0x3EEA, 0x2A09 }, // DAC_LD_30_31
++	{ 0x3060, 0x003C }, // ANALOG_GAIN
++	{ 0x30FE, 0x00A8 }, // NOISE_PEDESTAL
++	{ 0x3092, 0x00CF }, // ROW_NOISE_CONTROL
++	{ 0x3268, 0x0030 }, // SEQUENCER_CONTROL
++	{ 0x3786, 0x0006 }, // DIGITAL_CTRL_1
++	{ 0x3F4A, 0x0F70 }, // DELTA_DK_PIX_THRES
++	{ 0x306E, 0x4810 }, // DATAPATH_SELECT
++	{ 0x3064, 0x1802 }, // SMIA_TEST
++	{ 0x3EF6, 0x804D }, // DAC_LD_42_43
++	{ 0x3180, 0xC08F }, // DELTA_DK_CONTROL
++	{ 0x30BA, 0x7623 }, // DIGITAL_CTRL
++	{ 0x3176, 0x0480 }, // DELTA_DK_ADJUST_GREENR
++	{ 0x3178, 0x0480 }, // DELTA_DK_ADJUST_RED
++	{ 0x317A, 0x0480 }, // DELTA_DK_ADJUST_BLUE
++	{ 0x317C, 0x0480 }, // DELTA_DK_ADJUST_GREENB
++	{ 0x302A, 0x0006 }, // VT_PIX_CLK_DIV
++	{ 0x302C, 0x0001 }, // VT_SYS_CLK_DIV
++	{ 0x302E, 0x0004 }, // PRE_PLL_CLK_DIV
++	{ 0x3030, 0x004A }, // PLL_MULTIPLIER
++	{ 0x3036, 0x000C }, // OP_PIX_CLK_DIV
++	{ 0x3038, 0x0001 }, // OP_SYS_CLK_DIV
++	{ 0x30B0, 0x0028 }, // DIGITAL_TEST
++	{ AR0144_REG_DELAY, 100},
++	{ 0x31AE, 0x0202 }, // SERIAL_FORMAT
++	{ 0x31AC, 0x0C0C }, // DATA_FORMAT_BITS
++	{ 0x31B0, 0x0042 }, // FRAME_PREAMBLE
++	{ 0x31B2, 0x002E }, // LINE_PREAMBLE
++	{ 0x31B4, 0x2633 }, // MIPI_TIMING_0
++	{ 0x31B6, 0x210E }, // MIPI_TIMING_1
++	{ 0x31B8, 0x20C7 }, // MIPI_TIMING_2
++#if 0
++	{ 0x31BA, 0x0105 }, // MIPI_TIMING_3
++	{ 0x31BC, 0x0004 }, // MIPI_TIMING_4
++#else
++	{ 0x31BA, 0x01a5 }, // MIPI_TIMING_3
++	{ 0x31BC, 0x8004 }, // MIPI_TIMING_4
++#endif
++	{ 0x3002, 0x0028 }, // Y_ADDR_START
++	{ 0x3004, 0x0004 }, // X_ADDR_START
++	{ 0x3006, 0x02F7 }, // Y_ADDR_END
++	{ 0x3008, 0x0503 }, // X_ADDR_END
++	{ 0x300A, 0x0338 }, // FRAME_LENGTH_LINES
++	{ 0x300C, 0x05D0 }, // LINE_LENGTH_PCK
++//	{ 0x3012, 0x0064 }, // COARSE_INTEGRATION_TIME
++	{ 0x3012, 0x01F3 }, // COARSE_INTEGRATION_TIME
++	{ 0x30A2, 0x0001 }, // X_ODD_INC
++	{ 0x30A6, 0x0001 }, // Y_ODD_INC
++	{ 0x3040, 0x0000 }, // READ_MODE
++	{ 0x3064, 0x1882 }, // SMIA_TEST
++	{ 0x3064, 0x1802 }, // SMIA_TEST
++	{ 0x3028, 0x0010 }, // ROW_SPEED
++//	{ 0x301D, 0x0003 }, // FLIP
++#ifdef SNAPSHOT
++	{ 0x301A, 0x0958 }, // RESET_REGISTER stream_off
++	{ 0x30CE, 0x0120 },
++#else
++#endif
++	{AR0144_REG_END, 0x00},/* END MARKER */
++};
++
++
++#if 0
++
++static const struct regval_list ar0144_wb_auto_regs[] = {
++	{AR0144_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct regval_list ar0144_wb_incandescence_regs[] = {
++	{AR0144_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct regval_list ar0144_wb_daylight_regs[] = {
++	{AR0144_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct regval_list ar0144_wb_fluorescent_regs[] = {
++	{AR0144_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct regval_list ar0144_wb_cloud_regs[] = {
++	{AR0144_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct mode_list ar0144_balance[] = {
++	{0, ar0144_wb_auto_regs}, {1, ar0144_wb_incandescence_regs},
++	{2, ar0144_wb_daylight_regs}, {3, ar0144_wb_fluorescent_regs},
++	{4, ar0144_wb_cloud_regs},
++};
++
++
++static const struct regval_list ar0144_effect_normal_regs[] = {
++	{AR0144_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct regval_list ar0144_effect_grayscale_regs[] = {
++	{AR0144_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct regval_list ar0144_effect_sepia_regs[] = {
++	{AR0144_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct regval_list ar0144_effect_colorinv_regs[] = {
++	{AR0144_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct regval_list ar0144_effect_sepiabluel_regs[] = {
++	{AR0144_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct mode_list ar0144_effect[] = {
++	{0, ar0144_effect_normal_regs}, {1, ar0144_effect_grayscale_regs},
++	{2, ar0144_effect_sepia_regs}, {3, ar0144_effect_colorinv_regs},
++	{4, ar0144_effect_sepiabluel_regs},
++};
++
++#endif
++
++static struct ar0144_win_size ar0144_supported_win_sizes[] = {
++	{
++		.name = "720P",
++		.width = 1920 ,
++		.height = 720,
++		.regs = ar0144_720p_regs_mipi,
++		.mbus_code = MEDIA_BUS_FMT_Y8_1X8,
++	},
++};
++
++#define N_WIN_SIZES (ARRAY_SIZE(ar0144_supported_win_sizes))
++
++/*
++ * General functions
++ */
++
++static struct ar0144_priv *to_ov2735b(const struct i2c_client *client)
++{
++	return container_of(i2c_get_clientdata(client), struct ar0144_priv,
++			    subdev);
++}
++
++static int ar0144_write_array(struct i2c_client *client,
++			      const struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != AR0144_REG_END) {
++		if (vals->reg_num == AR0144_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ar0144_write_reg(client, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++#if 0
++static int ar0144_mask_set(struct i2c_client *client,
++			   u16  reg, u16  mask, u16  set)
++{
++	int ret = 0;
++	unsigned char value[2] = {0};
++	ret = ar0144_read_reg(client, reg, value);
++	if (ret < 0)
++		return ret;
++
++	val &= ~mask;
++	val |= set & mask;
++
++	dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val);
++
++	return ar0144_write_reg(client, reg, val);
++}
++#endif
++
++/*
++ * soc_camera_ops functions
++ */
++
++
++/*hw ops*/
++static int ar0144_hw_power(struct i2c_client *client, int on)
++{
++	struct ar0144_priv *priv = to_ov2735b(client);
++
++	dev_dbg(&client->dev, "%s: %s the camera\n",
++			__func__, on ? "ENABLE" : "DISABLE");
++
++	/* thses gpio should be set according to the active level in dt defines */
++	if(priv->vcc_en_gpio) {
++		gpiod_direction_output(priv->vcc_en_gpio, on);
++	}
++
++	if (priv->pwdn_gpio) {
++		gpiod_direction_output(priv->pwdn_gpio, on);
++	}
++
++	msleep(10);
++	return 0;
++}
++
++static int ar0144_reset(struct i2c_client *client)
++{
++	struct ar0144_priv *priv = to_ov2735b(client);
++
++	if(priv->resetb_gpio) {
++		gpiod_direction_output(priv->resetb_gpio, 1);
++		msleep(10);
++		gpiod_direction_output(priv->resetb_gpio, 0);
++		msleep(10);
++	}
++	return 0;
++}
++
++
++
++/*ctrl_ops*/
++static int ar0144_g_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd =
++		&container_of(ctrl->handler, struct ar0144_priv, hdl)->subdev;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ar0144_priv *priv = to_ov2735b(client);
++
++	switch (ctrl->id) {
++
++	case V4L2_CID_VFLIP:
++		ctrl->val = priv->flag_vflip;
++		break;
++	case V4L2_CID_HFLIP:
++		ctrl->val = priv->flag_hflip;
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++
++static int ar0144_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	int ret = 0;
++#if 0
++	struct v4l2_subdev *sd =
++		&container_of(ctrl->handler, struct ar0144_priv, hdl)->subdev;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ar0144_priv *priv = to_ov2735b(client);
++	int i = 0;
++	u16 value;
++
++	int balance_count = ARRAY_SIZE(ar0144_balance);
++	int effect_count = ARRAY_SIZE(ar0144_effect);
++
++	switch (ctrl->id) {
++	case V4L2_CID_VFLIP:
++		value = ctrl->val ? ar0144_FLIP_VAL : 0x00;
++		priv->flag_vflip = ctrl->val ? 1 : 0;
++//		ret = ar0144_mask_set(client, 0x301D, ar0144_FLIP_MASK, value);
++		break;
++
++	case V4L2_CID_HFLIP:
++		value = ctrl->val ? ar0144_FLIP_VAL : 0x00;
++		priv->flag_hflip = ctrl->val ? 1 : 0;
++//		ret = ar0144_mask_set(client, 0x301D, ar0144_FLIP_MASK, value);
++		break;
++
++	default:
++		dev_err(&client->dev, "no V4L2 CID: 0x%x ", ctrl->id);
++		return -EINVAL;
++	}
++
++#endif
++	return ret;
++}
++
++static const struct v4l2_ctrl_ops ar0144_ctrl_ops = {
++	.s_ctrl = ar0144_s_ctrl,
++	.g_volatile_ctrl = ar0144_g_ctrl,
++};
++
++/*core_ops*/
++static int ar0144_s_power(struct v4l2_subdev *sd, int on)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct ar0144_priv *priv = to_ov2735b(client);
++
++	if(priv->sd_pdata) {
++		if(on)
++			return regulator_bulk_enable(priv->sd_pdata->num_regulators,priv->sd_pdata->regulators);
++		else
++			return regulator_bulk_disable(priv->sd_pdata->num_regulators,priv->sd_pdata->regulators);
++	} else if(priv->power){
++		return priv->power(client, on);
++	} else {
++		dev_err(&client->dev, "ar0144_s_power failde");
++		return -EINVAL;
++	}
++}
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ar0144_g_register(struct v4l2_subdev *sd,
++			     struct v4l2_dbg_register *reg)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	int ret;
++
++	reg->size = 1;
++	if (reg->reg > 0xff)
++		return -EINVAL;
++
++	ret = ar0144_read_reg(client, reg->reg, reg->val);
++
++	return 0;
++}
++
++static int ar0144_s_register(struct v4l2_subdev *sd,
++			     const struct v4l2_dbg_register *reg)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++
++	if (reg->reg > 0xff ||
++	    reg->val > 0xff)
++		return -EINVAL;
++
++	return ar0144_write_reg(client, reg->reg, reg->val);
++}
++#endif
++
++static int ar0144_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++
++	if (!enable ) {
++		dev_info(&client->dev, "stream down\n");
++#ifdef SNAPSHOT
++		ar0144_write_reg(client, 0x301A, 0x0958);
++#else
++		ar0144_write_reg(client, 0x301A, 0x0058);
++#endif
++		return 0;
++	}
++
++	dev_info(&client->dev, "stream on\n");
++#ifdef SNAPSHOT
++	ar0144_write_reg(client, 0x301A, 0x095C);
++#else
++	ar0144_write_reg(client, 0x301A, 0x005C);
++#endif
++
++	return 0;
++}
++
++/* Select the nearest higher resolution for capture */
++static const struct ar0144_win_size *ar0144_select_win(u32 *code, u32 *width, u32 *height)
++{
++	int i, default_size = ARRAY_SIZE(ar0144_supported_win_sizes) - 1;
++
++	for (i = 0; i < ARRAY_SIZE(ar0144_supported_win_sizes); i++) {
++		if ((*width >= ar0144_supported_win_sizes[i].width) &&
++		    (*height >= ar0144_supported_win_sizes[i].height) &&
++		    (*code == ar0144_supported_win_sizes[i].mbus_code)) {
++			*width = ar0144_supported_win_sizes[i].width;
++			*height = ar0144_supported_win_sizes[i].height;
++			return &ar0144_supported_win_sizes[i];
++		}
++	}
++	return NULL;
++}
++
++static int ar0144_get_selection(struct v4l2_subdev *sd,
++			     struct v4l2_subdev_pad_config *cfg,
++			     struct v4l2_subdev_selection *sel)
++{
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ar0144_priv *priv = to_ov2735b(client);
++
++	if(!priv->win)
++		return -EINVAL;
++
++	sel->r.top = 0;
++	sel->r.left = 0;
++	sel->r.width = priv->win->width;
++	sel->r.height = priv->win->height;
++
++	return 0;
++}
++
++static int ar0144_get_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ar0144_priv *priv = to_ov2735b(client);
++
++	if (format->pad)
++		return -EINVAL;
++
++	if(priv->win){
++		mf->width = priv->win->width;
++		mf->height = priv->win->height;
++	} else {
++		mf->width = ar0144_DEFAULT_WIDTH;//priv->win->width;
++		mf->height = ar0144_DEFAULT_HEIGHT;//priv->win->height;
++	}
++	mf->code = priv->cfmt_code;
++
++	mf->colorspace = V4L2_COLORSPACE_JPEG;
++	mf->field	= V4L2_FIELD_NONE;
++
++	return 0;
++}
++
++static int ar0144_set_params(struct i2c_client *client, u32 *width, u32 *height, u32 code)
++{
++	struct ar0144_priv       *priv = to_ov2735b(client);
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	int ret;
++
++	int bala_index = priv->balance_value;
++	int effe_index = priv->effect_value;
++
++	/* reset hardware */
++	ar0144_reset(client);
++
++	/* initialize the sensor with default data */
++#if 0
++	dev_dbg(&client->dev, "%s: Init default", __func__);
++	ret = ar0144_write_array(client, ov2735b_init_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set balance */
++	ret = ar0144_write_array(client, ar0144_balance[bala_index].mode_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set effect */
++	ret = ar0144_write_array(client, ar0144_effect[effe_index].mode_regs);
++	if (ret < 0)
++		goto err;
++#endif
++	/* set size win */
++	dev_dbg(&client->dev, "priv->win.width = %d\n", priv->win->width);
++	dev_dbg(&client->dev, "priv->win.height = %d\n", priv->win->height);
++
++	ret = ar0144_write_array(client, priv->win->regs);
++	if (ret < 0)
++		goto err;
++
++	priv->cfmt_code = code;
++	*width = priv->win->width;
++	*height = priv->win->height;
++
++	return 0;
++
++err:
++	dev_err(&client->dev, "%s: Error %d", __func__, ret);
++	ar0144_reset(client);
++	priv->win = NULL;
++
++	return ret;
++}
++
++static int ar0144_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct ar0144_priv       *priv = to_ov2735b(client);
++
++	if (format->pad)
++		return -EINVAL;
++
++	priv->win = ar0144_select_win(&mf->code ,&mf->width, &mf->height);
++	if(!priv->win)
++		return -EINVAL;
++
++	mf->field	= V4L2_FIELD_NONE;
++	mf->colorspace = V4L2_COLORSPACE_JPEG;
++
++	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
++		ar0144_set_params(client, &mf->width,
++					 &mf->height, mf->code);
++	if(cfg)
++		cfg->try_fmt = *mf;
++	return 0;
++}
++
++static int ar0144_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad || code->index >= ARRAY_SIZE(ar0144_supported_win_sizes))
++		return -EINVAL;
++
++	code->code = ar0144_supported_win_sizes[code->index].mbus_code;
++	return 0;
++}
++
++static int ar0144_enum_frame_size(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_frame_size_enum *fse)
++{
++	int i, j;
++	int num_valid = -1;
++	__u32 index = fse->index;
++
++	if(index >= N_WIN_SIZES)
++		return -EINVAL;
++
++	fse->code = ar0144_supported_win_sizes[index].mbus_code;
++	fse->min_width = ar0144_supported_win_sizes[index].width;
++	fse->max_width = fse->min_width;
++	fse->min_height = ar0144_supported_win_sizes[index].height;
++	fse->max_height = fse->min_height;
++	return 0;
++
++}
++
++static int ar0144_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
++		struct v4l2_mbus_config *cfg)
++{
++	/*in dts*/
++	return 0;
++}
++
++static struct v4l2_subdev_core_ops ar0144_subdev_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register	= ar0144_g_register,
++	.s_register	= ar0144_s_register,
++#endif
++	.s_power	= ar0144_s_power,
++};
++
++static struct v4l2_subdev_video_ops ar0144_subdev_video_ops = {
++	.s_stream	= ar0144_s_stream,
++};
++
++static const struct v4l2_subdev_pad_ops ar0144_subdev_pad_ops = {
++	.enum_mbus_code = ar0144_enum_mbus_code,
++	.enum_frame_size = ar0144_enum_frame_size,
++	.get_fmt	= ar0144_get_fmt,
++	.set_fmt	= ar0144_set_fmt,
++	.get_mbus_config	= ar0144_g_mbus_config,
++	.get_selection	= ar0144_get_selection,
++};
++
++static struct v4l2_subdev_ops ar0144_subdev_ops = {
++	.core	= &ar0144_subdev_core_ops,
++	.video	= &ar0144_subdev_video_ops,
++	.pad	= &ar0144_subdev_pad_ops,
++};
++
++
++static int ar0144_detect(struct i2c_client *client, unsigned int *ident)
++{
++	unsigned char value[2] = {0};
++	int ret;
++
++	ret = ar0144_read_reg(client, AR0144_REG_CHIP_ID, value);
++
++	if (ret < 0)
++		return ret;
++
++	if (value[0] != AR0144_CHIP_ID_HIGH)
++		return -ENODEV;
++
++	if (value[1] != AR0144_CHIP_ID_LOW)
++		return -ENODEV;
++
++	return 0;
++}
++
++
++static int ar0144_probe_dt(struct i2c_client *client,
++		struct ar0144_priv *priv)
++{
++	struct v4l2_subdev_platform_data *sd_pdata = priv->sd_pdata;
++	struct device_node *np = client->dev.of_node;
++	int supplies = 0, index = 0;
++
++	supplies = of_property_count_strings(np, "supplies-name");
++	if(supplies > 0) {
++
++		sd_pdata = devm_kzalloc(&client->dev, sizeof(struct v4l2_subdev_platform_data), GFP_KERNEL);
++		sd_pdata->num_regulators = supplies;
++		sd_pdata->regulators = devm_kzalloc(&client->dev, supplies * sizeof(struct regulator_bulk_data), GFP_KERNEL);
++		if(!sd_pdata->regulators) {
++			dev_err(&client->dev, "Failed to allocate regulators.!\n");
++			devm_kfree(&client->dev,sd_pdata);
++			return -ENOMEM;
++		}
++
++		for(index = 0; index < sd_pdata->num_regulators; index ++) {
++			of_property_read_string_index(np, "supplies-name", index,
++					&(sd_pdata->regulators[index].supply));
++
++			dev_dbg(&client->dev, "sd_pdata->regulators[%d].supply: %s\n",
++					index, sd_pdata->regulators[index].supply);
++		}
++
++		devm_regulator_bulk_get(&client->dev, sd_pdata->num_regulators, sd_pdata->regulators);
++
++		//if(!client->dev.platform_data) /*TODO*/
++		//	client->dev.platform_data = &priv->sd_pdata;
++	} else {
++
++
++		/* Request the power down GPIO asserted */
++		priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn",
++				GPIOD_OUT_HIGH);
++		if (!priv->pwdn_gpio)
++			dev_dbg(&client->dev, "pwdn gpio is not assigned!\n");
++		else if (IS_ERR(priv->pwdn_gpio))
++			return PTR_ERR(priv->pwdn_gpio);
++
++		/* Request the power vcc-en GPIO asserted */
++		priv->vcc_en_gpio = devm_gpiod_get_optional(&client->dev, "vcc-en",
++				GPIOD_OUT_HIGH);
++		if (!priv->vcc_en_gpio)
++			dev_dbg(&client->dev, "vcc_en gpio is not assigned!\n");
++		else if (IS_ERR(priv->vcc_en_gpio))
++			return PTR_ERR(priv->vcc_en_gpio);
++
++		/* Request the power resetb GPIO asserted */
++		priv->resetb_gpio = devm_gpiod_get_optional(&client->dev, "resetb",
++				GPIOD_OUT_LOW);
++		if (!priv->resetb_gpio)
++			dev_dbg(&client->dev, "vcc_en gpio is not assigned!\n");
++		else if (IS_ERR(priv->resetb_gpio))
++			return PTR_ERR(priv->resetb_gpio);
++
++		/* Initialize the soc_camera_subdev_desc */
++		priv->power = ar0144_hw_power;
++	//	priv->reset = ar0144_hw_reset; /*TODO*/
++	}
++	return 0;
++}
++
++static int ar0144_probe(struct i2c_client *client,
++			const struct i2c_device_id *did)
++{
++	struct ar0144_priv	*priv;
++	struct i2c_adapter	*adapter = to_i2c_adapter(client->dev.parent);
++	int	ret;
++
++	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA)) {
++		dev_err(&adapter->dev,
++			"ar0144: I2C-Adapter doesn't support SMBUS\n");
++		return -EIO;
++	}
++
++	priv = devm_kzalloc(&client->dev, sizeof(struct ar0144_priv), GFP_KERNEL);
++	if (!priv) {
++		dev_err(&adapter->dev,
++			"Failed to allocate memory for private data!\n");
++		return -ENOMEM;
++	}
++
++	priv->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(priv->clk))
++		return -EPROBE_DEFER;
++
++	v4l2_clk_set_rate(priv->clk, 24000000);
++
++	/*mclk gate close*/
++//	*(volatile unsigned int *)0xb0000024 &= ~(1 << 5); 
++
++	ret = ar0144_probe_dt(client, priv);
++	if (ret)
++		goto err_probe_dt;
++
++	v4l2_i2c_subdev_init(&priv->subdev, client, &ar0144_subdev_ops);
++
++	/* add handler */
++	v4l2_ctrl_handler_init(&priv->hdl, 2);
++
++	v4l2_ctrl_new_std(&priv->hdl, &ar0144_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&priv->hdl, &ar0144_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++
++	priv->subdev.ctrl_handler = &priv->hdl;
++	if (priv->hdl.error) {
++		ret = priv->hdl.error;
++		goto err_hdl;
++	}
++
++#if 1
++	ret = ar0144_detect(client, NULL);
++	if(ret < 0){
++		v4l_err(client,"chip found @ 0x%x (%s) is not an ar0144 chip.\n",
++				client->addr << 1, client->adapter->name);
++		goto err_detect;
++	}
++#endif
++
++	ret = v4l2_ctrl_handler_setup(&priv->hdl);
++
++	ret = v4l2_async_register_subdev(&priv->subdev);
++	if (ret < 0)
++		goto err_async_register_subdev;
++
++	dev_info(&adapter->dev, "ar0144 Probed\n");
++
++	return 0;
++
++err_async_register_subdev:
++err_detect:
++	v4l2_ctrl_handler_free(&priv->hdl);
++err_hdl:
++	v4l2_device_unregister_subdev(&priv->subdev);
++err_probe_dt:
++	v4l2_clk_put(priv->clk);
++	devm_kfree(&client->dev, priv);
++	return ret;
++}
++
++static int ar0144_remove(struct i2c_client *client)
++{
++	struct ar0144_priv       *priv = to_ov2735b(client);
++
++	v4l2_async_unregister_subdev(&priv->subdev);
++	v4l2_ctrl_handler_free(&priv->hdl);
++	v4l2_device_unregister_subdev(&priv->subdev);
++	v4l2_clk_put(priv->clk);
++	devm_kfree(&client->dev, priv);
++	return 0;
++}
++
++static const struct i2c_device_id ar0144_id[] = {
++	{ "ar0144",  0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ar0144_id);
++static const struct of_device_id ar0144_of_match[] = {
++	{.compatible = "onsemi,ar0144", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ar0144_of_match);
++static struct i2c_driver ar0144_i2c_driver = {
++	.driver = {
++		.name = "ar0144",
++		.of_match_table = of_match_ptr(ar0144_of_match),
++	},
++	.probe    = ar0144_probe,
++	.remove   = ar0144_remove,
++	.id_table = ar0144_id,
++};
++module_i2c_driver(ar0144_i2c_driver);
++
++MODULE_DESCRIPTION("SoC Camera driver for onsemi ar0144 sensor");
++MODULE_LICENSE("GPL v2");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-cim/ov2735b.c b/module_drivers/drivers/media/i2c/ingenic-cim/ov2735b.c
+new file mode 100644
+index 000000000..790c69e17
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-cim/ov2735b.c
+@@ -0,0 +1,999 @@
++/*
++ * ov2735b Camera Driver
++ *
++ * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com>
++ *
++ * Based on ov772x, ov9640 drivers and previous non merged implementations.
++ *
++ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright (C) 2006, OmniVision
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/i2c.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/gpio/consumer.h>
++#include <linux/of_gpio.h>
++#include <linux/v4l2-mediabus.h>
++#include <linux/videodev2.h>
++
++#include <media/v4l2-clk.h>
++#include <media/v4l2-subdev.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-image-sizes.h>
++#include <media/v4l2-device.h>
++
++
++#include <linux/clk.h>
++#include <linux/regulator/consumer.h>
++
++#define OV2735B_CHIP_ID_H       (0x27)
++#define OV2735B_CHIP_ID_L       (0x35)
++#define OV2735B_REG_END         0xff
++#define OV2735B_REG_DELAY       0x00
++#define OV2735B_PAGE_REG            0xfd
++
++#define  ov2735b_DEFAULT_WIDTH    640
++#define  ov2735b_DEFAULT_HEIGHT   480
++
++/* Private v4l2 controls */
++#define V4L2_CID_PRIVATE_BALANCE  (V4L2_CID_PRIVATE_BASE + 0)
++#define V4L2_CID_PRIVATE_EFFECT  (V4L2_CID_PRIVATE_BASE + 1)
++
++#define ov2735b_FLIP_VAL			((unsigned char)0x04)
++#define ov2735b_FLIP_MASK		((unsigned char)0x04)
++
++/* whether sensor support high resolution (> vga) preview or not */
++#define SUPPORT_HIGH_RESOLUTION_PRE		1
++
++/*
++ * Struct
++ */
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++struct mode_list {
++	u16 index;
++	const struct regval_list *mode_regs;
++};
++
++struct ov2735b_win_size {
++	char *name;
++	int width;
++	int height;
++	const struct regval_list *regs;
++	unsigned int mbus_code;
++};
++
++
++struct ov2735b_gpio {
++	int pin;
++	int active_level;
++};
++
++struct ov2735b_priv {
++	struct v4l2_subdev		subdev;
++	struct v4l2_ctrl_handler	hdl;
++	u32	cfmt_code;
++	struct v4l2_clk			*clk;
++	const struct ov2735b_win_size	*win;
++
++	int				model;
++	u16				balance_value;
++	u16				effect_value;
++	u16				flag_vflip:1;
++	u16				flag_hflip:1;
++
++//	struct soc_camera_subdev_desc	ssdd_dt;
++	struct v4l2_subdev_platform_data *sd_pdata;
++	struct gpio_desc *resetb_gpio;
++	struct gpio_desc *pwdn_gpio;
++	struct gpio_desc *vcc_en_gpio;
++	int (*power)(struct i2c_client *client, int on);
++	int (*reset)(struct i2c_client *client);
++
++	struct regulator *reg;
++	struct regulator *reg1;
++};
++
++unsigned short ov2735b_read_reg(struct i2c_client *client, unsigned char reg, unsigned char *value)
++{
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr   = client->addr,
++			.flags  = 0,
++			.len    = 1,
++			.buf    = &reg,
++		},
++		[1] = {
++			.addr   = client->addr,
++			.flags  = I2C_M_RD,
++			.len    = 1,
++			.buf    = value,
++		}
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++int ov2735b_write_reg(struct i2c_client *client, unsigned char reg, unsigned short value)
++{
++	unsigned char buf[2] = {reg, value};
++	struct i2c_msg msg = {
++		.addr   = client->addr,
++		.flags  = 0,
++		.len    = 2,
++		.buf    = buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++
++}
++
++static struct regval_list ov2735b_1080p_regs[] = {
++	{0xfd, 0x00},
++	{OV2735B_REG_DELAY, 0x05},
++	{0xfd, 0x00},
++	{0x2f, 0x10},
++	{0x34, 0x00},
++	{0x30, 0x15},
++	{0x33, 0x01},
++	{0x35, 0x20},
++	{0x1d, 0xa5},
++	{0xfd, 0x01},
++	{0x0d, 0x00},
++	{0x30, 0x00},
++	{0x03, 0x01},
++	{0x04, 0x8f},
++	{0x01, 0x01},
++	{0x09, 0x00},
++	{0x0a, 0x20},
++	{0x06, 0x0a},
++	{0x24, 0x10},
++	{0x01, 0x01},
++	{0xfb, 0x73},
++	{0x01, 0x01},
++	{0xfd, 0x01},
++	{0x1a, 0x6b},
++	{0x1c, 0xea},
++	{0x16, 0x0c},
++	{0x21, 0x00},
++	{0x11, 0x63},
++	{0x19, 0xc3},
++	{0x26, 0xda},
++	{0x29, 0x01},
++	{0x33, 0x6f},
++	{0x2a, 0xd2},
++	{0x2c, 0x40},
++	{0xd0, 0x02},
++	{0xd1, 0x01},
++	{0xd2, 0x20},
++	{0xd3, 0x04},
++	{0xd4, 0x2a},
++	{0x50, 0x00},
++	{0x51, 0x2c},
++	{0x52, 0x29},
++	{0x53, 0x00},
++	{0x55, 0x44},
++	{0x58, 0x29},
++	{0x5a, 0x00},
++	{0x5b, 0x00},
++	{0x5d, 0x00},
++	{0x64, 0x2f},
++	{0x66, 0x62},
++	{0x68, 0x5b},
++	{0x75, 0x46},
++	{0x76, 0xf0},
++	{0x77, 0x4f},
++	{0x78, 0xef},
++	{0x72, 0xcf},
++	{0x73, 0x36},
++	{0x7d, 0x0d},
++	{0x7e, 0x0d},
++	{0x8a, 0x77},
++	{0x8b, 0x77},
++	{0xfd, 0x01},
++	{0xb1, 0x82},
++	{0xb3, 0x0b},
++	{0xb4, 0x14},
++	{0x9d, 0x40},
++	{0xa1, 0x05},
++	{0x94, 0x44},
++	{0x95, 0x33},
++	{0x96, 0x1f},
++	{0x98, 0x45},
++	{0x9c, 0x10},
++	{0xb5, 0x70},
++	{0xa0, 0x00},
++	{0x25, 0xe0},
++	{0x20, 0x7b},
++	{0x8f, 0x88},
++	{0x91, 0x40},
++	{0xfd, 0x01},
++	{0xfd, 0x02},
++	{0x5e, 0x03},
++	{0xfd, 0x02},
++	{0x60, 0xf0},
++	{0xa1, 0x04},
++	{0xa3, 0x40},
++	{0xa5, 0x02},
++	{0xa7, 0xc4},
++	{0xfd, 0x01},
++	{0x86, 0x77},
++	{0x89, 0x77},
++	{0x87, 0x74},
++	{0x88, 0x74},
++	{0xfc, 0xe0},
++	{0xfe, 0xe0},
++	{0xf0, 0x40},
++	{0xf1, 0x40},
++	{0xf2, 0x40},
++	{0xf3, 0x40},
++	{0xfd, 0x02},
++	{0x36, 0x08},
++	{0xa0, 0x00},
++	{0xa1, 0x08},
++	{0xa2, 0x04},
++	{0xa3, 0x38},
++	{0xa4, 0x00},
++	{0xa5, 0x04},
++	{0xa6, 0x03},
++	{0xa7, 0xc0},
++	{0xfd, 0x03},
++	{0xc0, 0x01},//OTP transf
++	{0xfd, 0x04},
++	{0x22, 0x14},
++	{0x23, 0x14},
++	{0xfd, 0x01},
++	{0x06, 0xe0},
++	{0x01, 0x01},
++	{0xfd, 0x00},
++	{0x1b, 0x00},
++	{0xfd, 0x01},
++	{0x0d, 0x10},
++	{0x0e, 0x05},
++	{0x0f, 0x2b},
++	{0x01, 0x01},
++
++	{OV2735B_REG_END, 0x00},        /* END MARKER */
++};
++
++#if 0
++
++static const struct regval_list ov2735b_wb_auto_regs[] = {
++	{OV2735B_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct regval_list ov2735b_wb_incandescence_regs[] = {
++	{OV2735B_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct regval_list ov2735b_wb_daylight_regs[] = {
++	{OV2735B_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct regval_list ov2735b_wb_fluorescent_regs[] = {
++	{OV2735B_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct regval_list ov2735b_wb_cloud_regs[] = {
++	{OV2735B_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct mode_list ov2735b_balance[] = {
++	{0, ov2735b_wb_auto_regs}, {1, ar0144_wb_incandescence_regs},
++	{2, ov2735b_wb_daylight_regs}, {3, ar0144_wb_fluorescent_regs},
++	{4, ov2735b_wb_cloud_regs},
++};
++
++
++static const struct regval_list ov2735b_effect_normal_regs[] = {
++	{OV2735B_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct regval_list ov2735b_effect_grayscale_regs[] = {
++	{OV2735B_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct regval_list ov2735b_effect_sepia_regs[] = {
++	{OV2735B_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct regval_list ov2735b_effect_colorinv_regs[] = {
++	{OV2735B_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct regval_list ov2735b_effect_sepiabluel_regs[] = {
++	{OV2735B_REG_END, 0x00},/* END MARKER */
++};
++
++static const struct mode_list ov2735b_effect[] = {
++	{0, ov2735b_effect_normal_regs}, {1, ar0144_effect_grayscale_regs},
++	{2, ov2735b_effect_sepia_regs}, {3, ar0144_effect_colorinv_regs},
++	{4, ov2735b_effect_sepiabluel_regs},
++};
++
++#endif
++
++static struct ov2735b_win_size ov2735b_supported_win_sizes[] = {
++	{
++		.name = "1080P",
++		.width = 1920,
++		.height = 1080,
++		.regs = ov2735b_1080p_regs,
++		//.mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
++		.mbus_code = MEDIA_BUS_FMT_Y8_1X8,
++	},
++};
++
++#define N_WIN_SIZES (ARRAY_SIZE(ov2735b_supported_win_sizes))
++
++/*
++ * General functions
++ */
++
++static struct ov2735b_priv *to_ov2735b(const struct i2c_client *client)
++{
++	return container_of(i2c_get_clientdata(client), struct ov2735b_priv,
++			    subdev);
++}
++
++static int ov2735b_write_array(struct i2c_client *client,
++			      const struct regval_list *vals)
++{
++	int ret;
++
++	while (vals->reg_num != OV2735B_REG_END) {
++		if (vals->reg_num == OV2735B_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ov2735b_write_reg(client, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++#if 0
++static int ov2735b_mask_set(struct i2c_client *client,
++			   u16  reg, u16  mask, u16  set)
++{
++	int ret = 0;
++	unsigned char value[2] = {0};
++	ret = ov2735b_read_reg(client, reg, value);
++	if (ret < 0)
++		return ret;
++
++	val &= ~mask;
++	val |= set & mask;
++
++	dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val);
++
++	return ov2735b_write_reg(client, reg, val);
++}
++#endif
++
++/*
++ * soc_camera_ops functions
++ */
++
++
++/*hw ops*/
++static int ov2735b_hw_power(struct i2c_client *client, int on)
++{
++	struct ov2735b_priv *priv = to_ov2735b(client);
++
++	dev_dbg(&client->dev, "%s: %s the camera\n",
++			__func__, on ? "ENABLE" : "DISABLE");
++
++	/* thses gpio should be set according to the active level in dt defines */
++	if(priv->vcc_en_gpio) {
++		gpiod_direction_output(priv->vcc_en_gpio, on);
++	}
++
++	if (priv->pwdn_gpio) {
++		gpiod_direction_output(priv->pwdn_gpio, on);
++	}
++
++	msleep(10);
++	return 0;
++}
++
++static int ov2735b_reset(struct i2c_client *client)
++{
++	struct ov2735b_priv *priv = to_ov2735b(client);
++
++	if(priv->resetb_gpio) {
++		gpiod_direction_output(priv->resetb_gpio, 1);
++		msleep(10);
++		gpiod_direction_output(priv->resetb_gpio, 0);
++		msleep(10);
++	}
++	return 0;
++}
++
++
++
++/*ctrl_ops*/
++static int ov2735b_g_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd =
++		&container_of(ctrl->handler, struct ov2735b_priv, hdl)->subdev;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov2735b_priv *priv = to_ov2735b(client);
++
++	switch (ctrl->id) {
++
++	case V4L2_CID_VFLIP:
++		ctrl->val = priv->flag_vflip;
++		break;
++	case V4L2_CID_HFLIP:
++		ctrl->val = priv->flag_hflip;
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++
++static int ov2735b_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	int ret = 0;
++#if 0
++	struct v4l2_subdev *sd =
++		&container_of(ctrl->handler, struct ov2735b_priv, hdl)->subdev;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov2735b_priv *priv = to_ov2735b(client);
++	int i = 0;
++	u16 value;
++
++	int balance_count = ARRAY_SIZE(ov2735b_balance);
++	int effect_count = ARRAY_SIZE(ov2735b_effect);
++
++	switch (ctrl->id) {
++	case V4L2_CID_VFLIP:
++		value = ctrl->val ? ov2735b_FLIP_VAL : 0x00;
++		priv->flag_vflip = ctrl->val ? 1 : 0;
++//		ret = ov2735b_mask_set(client, 0x301D, ar0144_FLIP_MASK, value);
++		break;
++
++	case V4L2_CID_HFLIP:
++		value = ctrl->val ? ov2735b_FLIP_VAL : 0x00;
++		priv->flag_hflip = ctrl->val ? 1 : 0;
++//		ret = ov2735b_mask_set(client, 0x301D, ar0144_FLIP_MASK, value);
++		break;
++
++	default:
++		dev_err(&client->dev, "no V4L2 CID: 0x%x ", ctrl->id);
++		return -EINVAL;
++	}
++
++#endif
++	return ret;
++}
++
++static const struct v4l2_ctrl_ops ov2735b_ctrl_ops = {
++	.s_ctrl = ov2735b_s_ctrl,
++	.g_volatile_ctrl = ov2735b_g_ctrl,
++};
++
++/*core_ops*/
++static int ov2735b_s_power(struct v4l2_subdev *sd, int on)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct ov2735b_priv *priv = to_ov2735b(client);
++
++	if(priv->sd_pdata) {
++		if(on)
++			return regulator_bulk_enable(priv->sd_pdata->num_regulators,priv->sd_pdata->regulators);
++		else
++			return regulator_bulk_disable(priv->sd_pdata->num_regulators,priv->sd_pdata->regulators);
++	} else if(priv->power){
++		return priv->power(client, on);
++	} else {
++		dev_err(&client->dev, "ov2735b_s_power failde");
++		return -EINVAL;
++	}
++}
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ov2735b_g_register(struct v4l2_subdev *sd,
++			     struct v4l2_dbg_register *reg)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	int ret;
++
++	reg->size = 1;
++	if (reg->reg > 0xff)
++		return -EINVAL;
++
++	ret = ov2735b_read_reg(client, reg->reg, reg->val);
++
++	return 0;
++}
++
++static int ov2735b_s_register(struct v4l2_subdev *sd,
++			     const struct v4l2_dbg_register *reg)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++
++	if (reg->reg > 0xff ||
++	    reg->val > 0xff)
++		return -EINVAL;
++
++	return ov2735b_write_reg(client, reg->reg, reg->val);
++}
++#endif
++
++static struct regval_list ov2735b_stream_on[] = {
++	{0xfd, 0x00},
++	{0x36, 0x00},
++	{0x37, 0x00},//fake stream on
++
++	{OV2735B_REG_END, 0x00},
++};
++
++static struct regval_list ov2735b_stream_off[] = {
++	{0xfd, 0x00},
++	{0x36, 0x01},
++	{0x37, 0x01},//fake stream off
++
++	{OV2735B_REG_END, 0x00},
++};
++
++static int ov2735b_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++
++	if (!enable ) {
++		dev_info(&client->dev, "stream down\n");
++		ov2735b_write_array(client, ov2735b_stream_off);
++		return 0;
++	}
++
++	dev_info(&client->dev, "stream on\n");
++	ov2735b_write_array(client, ov2735b_stream_on);
++
++	return 0;
++}
++
++/* Select the nearest higher resolution for capture */
++static const struct ov2735b_win_size *ov2735b_select_win(u32 *code, u32 *width, u32 *height)
++{
++	int i, default_size = ARRAY_SIZE(ov2735b_supported_win_sizes) - 1;
++
++	for (i = 0; i < ARRAY_SIZE(ov2735b_supported_win_sizes); i++) {
++		if ((*width >= ov2735b_supported_win_sizes[i].width) &&
++		    (*height >= ov2735b_supported_win_sizes[i].height) &&
++		    (*code == ov2735b_supported_win_sizes[i].mbus_code)) {
++			*width = ov2735b_supported_win_sizes[i].width;
++			*height = ov2735b_supported_win_sizes[i].height;
++			return &ov2735b_supported_win_sizes[i];
++		}
++	}
++
++	return NULL;
++}
++
++static int ov2735b_get_selection(struct v4l2_subdev *sd,
++			     struct v4l2_subdev_pad_config *cfg,
++			     struct v4l2_subdev_selection *sel)
++{
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov2735b_priv *priv = to_ov2735b(client);
++
++	if(!priv->win)
++		return -EINVAL;
++
++	sel->r.top = 0;
++	sel->r.left = 0;
++	sel->r.width = priv->win->width;
++	sel->r.height = priv->win->height;
++
++	return 0;
++}
++
++static int ov2735b_get_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov2735b_priv *priv = to_ov2735b(client);
++
++	if (format->pad)
++		return -EINVAL;
++
++	if(priv->win){
++		mf->width = priv->win->width;
++		mf->height = priv->win->height;
++	} else {
++		mf->width = ov2735b_DEFAULT_WIDTH;
++		mf->height = ov2735b_DEFAULT_HEIGHT;
++	}
++	mf->code = priv->cfmt_code;
++
++	mf->colorspace = V4L2_COLORSPACE_JPEG;
++	mf->field	= V4L2_FIELD_NONE;
++
++	return 0;
++}
++
++static int ov2735b_set_params(struct i2c_client *client, u32 *width, u32 *height, u32 code)
++{
++	struct ov2735b_priv       *priv = to_ov2735b(client);
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	int ret;
++
++	int bala_index = priv->balance_value;
++	int effe_index = priv->effect_value;
++
++	/* reset hardware */
++	ov2735b_reset(client);
++
++	/* initialize the sensor with default data */
++	dev_dbg(&client->dev, "%s: Init default", __func__);
++#if 0
++	ret = ov2735b_write_array(client, ov2735b_init_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set balance */
++	ret = ov2735b_write_array(client, ar0144_balance[bala_index].mode_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set effect */
++	ret = ov2735b_write_array(client, ar0144_effect[effe_index].mode_regs);
++	if (ret < 0)
++		goto err;
++#endif
++	/* set size win */
++	dev_dbg(&client->dev, "priv->win.width = %d\n", priv->win->width);
++	dev_dbg(&client->dev, "priv->win.height = %d\n", priv->win->height);
++
++	ret = ov2735b_write_array(client, priv->win->regs);
++	if (ret < 0)
++		goto err;
++
++	priv->cfmt_code = code;
++	*width = priv->win->width;
++	*height = priv->win->height;
++
++	return 0;
++
++err:
++	dev_err(&client->dev, "%s: Error %d", __func__, ret);
++	ov2735b_reset(client);
++	priv->win = NULL;
++
++	return ret;
++}
++
++static int ov2735b_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct ov2735b_priv       *priv = to_ov2735b(client);
++
++	if (format->pad)
++		return -EINVAL;
++
++	priv->win = ov2735b_select_win(&mf->code ,&mf->width, &mf->height);
++	if(!priv->win)
++		return -EINVAL;
++
++	mf->field	= V4L2_FIELD_NONE;
++	mf->colorspace = V4L2_COLORSPACE_JPEG;
++
++	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
++		ov2735b_set_params(client, &mf->width,
++					 &mf->height, mf->code);
++	if(cfg)
++		cfg->try_fmt = *mf;
++	return 0;
++}
++
++static int ov2735b_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad || code->index >= ARRAY_SIZE(ov2735b_supported_win_sizes))
++		return -EINVAL;
++
++	code->code = ov2735b_supported_win_sizes[code->index].mbus_code;
++	return 0;
++}
++
++static int ov2735b_enum_frame_size(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_frame_size_enum *fse)
++{
++	int i, j;
++	int num_valid = -1;
++	__u32 index = fse->index;
++
++	if(index >= N_WIN_SIZES)
++		return -EINVAL;
++
++	fse->code = ov2735b_supported_win_sizes[index].mbus_code;
++	fse->min_width = ov2735b_supported_win_sizes[index].width;
++	fse->max_width = fse->min_width;
++	fse->min_height = ov2735b_supported_win_sizes[index].height;
++	fse->max_height = fse->min_height;
++	return 0;
++
++}
++
++static int ov2735b_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
++		struct v4l2_mbus_config *cfg)
++{
++	/*int dts*/
++	return 0;
++}
++
++static struct v4l2_subdev_core_ops ov2735b_subdev_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register	= ov2735b_g_register,
++	.s_register	= ov2735b_s_register,
++#endif
++	.s_power	= ov2735b_s_power,
++};
++
++static struct v4l2_subdev_video_ops ov2735b_subdev_video_ops = {
++	.s_stream	= ov2735b_s_stream,
++};
++
++static const struct v4l2_subdev_pad_ops ov2735b_subdev_pad_ops = {
++	.enum_mbus_code = ov2735b_enum_mbus_code,
++	.enum_frame_size = ov2735b_enum_frame_size,
++	.get_fmt	= ov2735b_get_fmt,
++	.set_fmt	= ov2735b_set_fmt,
++	.get_mbus_config	= ov2735b_g_mbus_config,
++	.get_selection	= ov2735b_get_selection,
++};
++
++static struct v4l2_subdev_ops ov2735b_subdev_ops = {
++	.core	= &ov2735b_subdev_core_ops,
++	.video	= &ov2735b_subdev_video_ops,
++	.pad	= &ov2735b_subdev_pad_ops,
++};
++
++
++static int ov2735b_detect(struct i2c_client *client, unsigned int *ident)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	unsigned char v;
++	int ret;
++
++	ov2735b_s_power(sd, 1);
++	ret = ov2735b_read_reg(client, 0x02, &v);
++	printk("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != OV2735B_CHIP_ID_H)
++		return -ENODEV;
++
++	ret = ov2735b_read_reg(client, 0x03, &v);
++	printk("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != OV2735B_CHIP_ID_L)
++		return -ENODEV;
++
++	ret = ov2735b_read_reg(client, 0x04, &v);
++	printk("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != 0x05 && v != 0x06 && v != 0x07)
++		return -ENODEV;
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++//	ov2735b_s_power(sd, 0);
++	return 0;
++
++}
++
++
++static int ov2735b_probe_dt(struct i2c_client *client,
++		struct ov2735b_priv *priv)
++{
++	struct v4l2_subdev_platform_data *sd_pdata = priv->sd_pdata;
++	struct device_node *np = client->dev.of_node;
++	int supplies = 0, index = 0;
++
++	supplies = of_property_count_strings(np, "supplies-name");
++	if(supplies > 0) {
++
++		sd_pdata = devm_kzalloc(&client->dev, sizeof(struct v4l2_subdev_platform_data), GFP_KERNEL);
++		sd_pdata->num_regulators = supplies;
++		sd_pdata->regulators = devm_kzalloc(&client->dev, supplies * sizeof(struct regulator_bulk_data), GFP_KERNEL);
++		if(!sd_pdata->regulators) {
++			dev_err(&client->dev, "Failed to allocate regulators.!\n");
++			devm_kfree(&client->dev,sd_pdata);
++			return -ENOMEM;
++		}
++
++		for(index = 0; index < sd_pdata->num_regulators; index ++) {
++			of_property_read_string_index(np, "supplies-name", index,
++					&(sd_pdata->regulators[index].supply));
++
++			dev_dbg(&client->dev, "sd_pdata->regulators[%d].supply: %s\n",
++					index, sd_pdata->regulators[index].supply);
++		}
++
++		devm_regulator_bulk_get(&client->dev, sd_pdata->num_regulators, sd_pdata->regulators);
++
++		//if(!client->dev.platform_data) /*TODO*/
++		//	client->dev.platform_data = &priv->sd_pdata;
++	} else {
++
++
++		/* Request the power down GPIO asserted */
++		priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn",
++				GPIOD_OUT_HIGH);
++		if (!priv->pwdn_gpio)
++			dev_dbg(&client->dev, "pwdn gpio is not assigned!\n");
++		else if (IS_ERR(priv->pwdn_gpio))
++			return PTR_ERR(priv->pwdn_gpio);
++
++		/* Request the power vcc-en GPIO asserted */
++		priv->vcc_en_gpio = devm_gpiod_get_optional(&client->dev, "vcc-en",
++				GPIOD_OUT_HIGH);
++		if (!priv->vcc_en_gpio)
++			dev_dbg(&client->dev, "vcc_en gpio is not assigned!\n");
++		else if (IS_ERR(priv->vcc_en_gpio))
++			return PTR_ERR(priv->vcc_en_gpio);
++
++		/* Request the power resetb GPIO asserted */
++		priv->resetb_gpio = devm_gpiod_get_optional(&client->dev, "resetb",
++				GPIOD_OUT_LOW);
++		if (!priv->resetb_gpio)
++			dev_dbg(&client->dev, "vcc_en gpio is not assigned!\n");
++		else if (IS_ERR(priv->resetb_gpio))
++			return PTR_ERR(priv->resetb_gpio);
++
++		/* Initialize the soc_camera_subdev_desc */
++		priv->power = ov2735b_hw_power;
++	//	priv->reset = ov2735b_hw_reset; /*TODO*/
++	}
++	return 0;
++}
++
++static int ov2735b_probe(struct i2c_client *client,
++			const struct i2c_device_id *did)
++{
++	struct ov2735b_priv	*priv;
++	struct i2c_adapter	*adapter = to_i2c_adapter(client->dev.parent);
++	int	ret;
++
++	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA)) {
++		dev_err(&adapter->dev,
++			"ov2735b: I2C-Adapter doesn't support SMBUS\n");
++		return -EIO;
++	}
++
++	priv = devm_kzalloc(&client->dev, sizeof(struct ov2735b_priv), GFP_KERNEL);
++	if (!priv) {
++		dev_err(&adapter->dev,
++			"Failed to allocate memory for private data!\n");
++		return -ENOMEM;
++	}
++
++	priv->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(priv->clk))
++		return -EPROBE_DEFER;
++
++	v4l2_clk_set_rate(priv->clk, 24000000);
++
++	/*mclk gate close*/
++//	*(volatile unsigned int *)0xb0000024 &= ~(1 << 5); 
++
++	ret = ov2735b_probe_dt(client, priv);
++	if (ret)
++		goto err_probe_dt;
++
++	v4l2_i2c_subdev_init(&priv->subdev, client, &ov2735b_subdev_ops);
++
++	/* add handler */
++	v4l2_ctrl_handler_init(&priv->hdl, 2);
++
++	v4l2_ctrl_new_std(&priv->hdl, &ov2735b_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&priv->hdl, &ov2735b_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++
++	priv->subdev.ctrl_handler = &priv->hdl;
++	if (priv->hdl.error) {
++		ret = priv->hdl.error;
++		goto err_hdl;
++	}
++
++#if 0
++	ret = ov2735b_detect(client, NULL);
++	if(ret < 0){
++		v4l_err(client,"chip found @ 0x%x (%s) is not an ov2735b chip.\n",
++				client->addr << 1, client->adapter->name);
++		goto err_detect;
++	}
++#endif
++
++	ret = v4l2_ctrl_handler_setup(&priv->hdl);
++
++	ret = v4l2_async_register_subdev(&priv->subdev);
++	if (ret < 0)
++		goto err_async_register_subdev;
++
++	dev_info(&adapter->dev, "ov2735b Probed\n");
++
++	return 0;
++
++err_async_register_subdev:
++err_detect:
++	v4l2_ctrl_handler_free(&priv->hdl);
++err_hdl:
++	v4l2_device_unregister_subdev(&priv->subdev);
++err_probe_dt:
++	v4l2_clk_put(priv->clk);
++	devm_kfree(&client->dev, priv);
++	return ret;
++}
++
++static int ov2735b_remove(struct i2c_client *client)
++{
++	struct ov2735b_priv       *priv = to_ov2735b(client);
++
++	v4l2_async_unregister_subdev(&priv->subdev);
++	v4l2_ctrl_handler_free(&priv->hdl);
++	v4l2_device_unregister_subdev(&priv->subdev);
++	v4l2_clk_put(priv->clk);
++	devm_kfree(&client->dev, priv);
++	return 0;
++}
++
++static const struct i2c_device_id ov2735b_id[] = {
++	{ "ov2735b",  0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ov2735b_id);
++static const struct of_device_id ov2735b_of_match[] = {
++	{.compatible = "ovit,ov2735b", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov2735b_of_match);
++static struct i2c_driver ov2735b_i2c_driver = {
++	.driver = {
++		.name = "ov2735b",
++		.of_match_table = of_match_ptr(ov2735b_of_match),
++	},
++	.probe    = ov2735b_probe,
++	.remove   = ov2735b_remove,
++	.id_table = ov2735b_id,
++};
++module_i2c_driver(ov2735b_i2c_driver);
++
++MODULE_DESCRIPTION("SoC Camera driver for onsemi ov2735b sensor");
++MODULE_LICENSE("GPL v2");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-cim/ov4689.c b/module_drivers/drivers/media/i2c/ingenic-cim/ov4689.c
+new file mode 100644
+index 000000000..b59e4a176
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-cim/ov4689.c
+@@ -0,0 +1,3115 @@
++/*
++ * A V4L2 driver for OmniVision OV4689 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++
++#define OV4689_CHIP_ID_H	(0x46)
++#define OV4689_CHIP_ID_L	(0x88)
++#define OV4689_REG_END		0xffff
++#define OV4689_REG_DELAY	0xfffe
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct ov4689_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	/* struct sensor_info sensor_info; */
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct ov4689_gpio {
++	int pin;
++	int active_level;
++};
++
++struct ov4689_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct ov4689_win_size *win;
++
++	struct gpio_desc *reset;
++	struct gpio_desc *ircutp;
++	struct gpio_desc *ircutn;
++
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++struct again_lut ov4689_again_lut[] = {
++
++	{0x80, 0},
++	{0x88, 5731},
++	{0x90, 11136},
++	{0x98, 16248},
++	{0xa0, 21097},
++	{0xa8, 25710},
++	{0xb0, 30109},
++	{0xb8, 34312},
++	{0xc0, 38336},
++	{0xc8, 42195},
++	{0xd0, 45904},
++	{0xd8, 49472},
++	{0xe0, 52910},
++	{0xe8, 56228},
++	{0xf0, 59433},
++	{0xf8, 62534},
++	{0x178, 65536},
++	{0x17c, 68445},
++	{0x180, 71267},
++	{0x184, 74008},
++	{0x188, 76672},
++	{0x18c, 79262},
++	{0x190, 81784},
++	{0x194, 84240},
++	{0x198, 86633},
++	{0x19c, 88968},
++	{0x1a0, 91246},
++	{0x1a4, 93471},
++	{0x1a8, 95645},
++	{0x1ac, 97770},
++	{0x1b0, 99848},
++	{0x1b4, 101881},
++	{0x1b8, 103872},
++	{0x1bc, 105821},
++	{0x1c0, 107731},
++	{0x1c4, 109604},
++	{0x1c8, 111440},
++	{0x1cc, 113241},
++	{0x1d0, 115008},
++	{0x1d4, 116743},
++	{0x1d8, 118446},
++	{0x1dc, 120120},
++	{0x1e0, 121764},
++	{0x1e4, 123380},
++	{0x1e8, 124969},
++	{0x1ec, 126532},
++	{0x1f0, 128070},
++	{0x1f4, 129583},
++	{0x374, 131072},
++	{0x376, 132537},
++	{0x378, 133981},
++	{0x37a, 135403},
++	{0x37c, 136803},
++	{0x37e, 138184},
++	{0x380, 139544},
++	{0x382, 140885},
++	{0x384, 142208},
++	{0x386, 143512},
++	{0x388, 144798},
++	{0x38a, 146067},
++	{0x38c, 147320},
++	{0x38e, 148556},
++	{0x390, 149776},
++	{0x392, 150980},
++	{0x394, 152169},
++	{0x396, 153344},
++	{0x398, 154504},
++	{0x39a, 155650},
++	{0x39c, 156782},
++	{0x39e, 157901},
++	{0x3a0, 159007},
++	{0x3a2, 160100},
++	{0x3a4, 161181},
++	{0x3a6, 162249},
++	{0x3a8, 163306},
++	{0x3aa, 164350},
++	{0x3ac, 165384},
++	{0x3ae, 166406},
++	{0x3b0, 167417},
++	{0x3b2, 168418},
++	{0x3b4, 169408},
++	{0x3b6, 170387},
++	{0x3b8, 171357},
++	{0x3ba, 172317},
++	{0x3bc, 173267},
++	{0x3be, 174208},
++	{0x3c0, 175140},
++	{0x3c2, 176062},
++	{0x3c4, 176976},
++	{0x3c6, 177880},
++	{0x3c8, 178777},
++	{0x3ca, 179664},
++	{0x3cc, 180544},
++	{0x3ce, 181415},
++	{0x3d0, 182279},
++	{0x3d2, 183134},
++	{0x3d4, 183982},
++	{0x3d6, 184823},
++	{0x3d8, 185656},
++	{0x3da, 186482},
++	{0x3dc, 187300},
++	{0x3de, 188112},
++	{0x3e0, 188916},
++	{0x3e2, 189714},
++	{0x3e4, 190505},
++	{0x3e6, 191290},
++	{0x3e8, 192068},
++	{0x3ea, 192840},
++	{0x3ec, 193606},
++	{0x3ee, 194365},
++	{0x3f0, 195119},
++	{0x3f2, 195866},
++	{0x778, 196608},
++	{0x779, 197343},
++	{0x77a, 198073},
++	{0x77b, 198798},
++	{0x77c, 199517},
++	{0x77d, 200230},
++	{0x77e, 200939},
++	{0x77f, 201642},
++	{0x780, 202339},
++	{0x781, 203032},
++	{0x782, 203720},
++	{0x783, 204402},
++	{0x784, 205080},
++	{0x785, 205753},
++	{0x786, 206421},
++	{0x787, 207085},
++	{0x788, 207744},
++	{0x789, 208398},
++	{0x78a, 209048},
++	{0x78b, 209693},
++	{0x78c, 210334},
++	{0x78d, 210971},
++	{0x78e, 211603},
++	{0x78f, 212232},
++	{0x790, 212856},
++	{0x791, 213476},
++	{0x792, 214092},
++	{0x793, 214704},
++	{0x794, 215312},
++	{0x795, 215916},
++	{0x796, 216516},
++	{0x797, 217113},
++	{0x798, 217705},
++	{0x799, 218294},
++	{0x79a, 218880},
++	{0x79b, 219462},
++	{0x79c, 220040},
++	{0x79d, 220615},
++	{0x79e, 221186},
++	{0x79f, 221754},
++	{0x7a0, 222318},
++	{0x7a1, 222880},
++	{0x7a2, 223437},
++	{0x7a3, 223992},
++	{0x7a4, 224543},
++	{0x7a5, 225091},
++	{0x7a6, 225636},
++	{0x7a7, 226178},
++	{0x7a8, 226717},
++	{0x7a9, 227253},
++	{0x7aa, 227785},
++	{0x7ab, 228315},
++	{0x7ac, 228842},
++	{0x7ad, 229365},
++	{0x7ae, 229886},
++	{0x7af, 230404},
++	{0x7b0, 230920},
++	{0x7b1, 231432},
++	{0x7b2, 231942},
++	{0x7b3, 232449},
++	{0x7b4, 232953},
++	{0x7b5, 233455},
++	{0x7b6, 233954},
++	{0x7b7, 234450},
++	{0x7b8, 234944},
++	{0x7b9, 235435},
++	{0x7ba, 235923},
++	{0x7bb, 236410},
++	{0x7bc, 236893},
++	{0x7bd, 237374},
++	{0x7be, 237853},
++	{0x7bf, 238329},
++	{0x7c0, 238803},
++	{0x7c1, 239275},
++	{0x7c2, 239744},
++	{0x7c3, 240211},
++	{0x7c4, 240676},
++	{0x7c5, 241138},
++	{0x7c6, 241598},
++	{0x7c7, 242056},
++	{0x7c8, 242512},
++	{0x7c9, 242965},
++	{0x7ca, 243416},
++	{0x7cb, 243865},
++	{0x7cc, 244313},
++	{0x7cd, 244757},
++	{0x7ce, 245200},
++	{0x7cf, 245641},
++	{0x7d0, 246080},
++	{0x7d1, 246517},
++	{0x7d2, 246951},
++	{0x7d3, 247384},
++	{0x7d4, 247815},
++	{0x7d5, 248243},
++	{0x7d6, 248670},
++	{0x7d7, 249095},
++	{0x7d8, 249518},
++	{0x7d9, 249939},
++	{0x7da, 250359},
++	{0x7db, 250776},
++	{0x7dc, 251192},
++	{0x7dd, 251606},
++	{0x7de, 252018},
++	{0x7df, 252428},
++	{0x7e0, 252836},
++	{0x7e1, 253243},
++	{0x7e2, 253648},
++	{0x7e3, 254051},
++	{0x7e4, 254452},
++	{0x7e5, 254852},
++	{0x7e6, 255250},
++	{0x7e7, 255647},
++	{0x7e8, 256041},
++	{0x7e9, 256435},
++	{0x7ea, 256826},
++	{0x7eb, 257216},
++	{0x7ec, 257604},
++	{0x7ed, 257991},
++	{0x7ee, 258376},
++	{0x7ef, 258760},
++	{0x7f0, 259142},
++	{0x7f1, 259522},
++	{0x7f2, 259901},
++	{0x7f3, 260279},
++	{0x7f4, 260655},
++	{0x7f5, 261029},
++	{0x7f6, 261402},
++	{0x7f7, 261773},
++};
++
++static inline struct ov4689_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct ov4689_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct ov4689_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++static struct regval_list ov4689_init_regs_1920_1080_120fps_mipi[] = {
++	//	@@ 0 35 RES_1920x1080_120fps_1008Mbps
++	//		100 99 1920 1080
++	//102 3601 2ee0
++
++	{ 0x0103, 0x01 },
++	{ 0x3638, 0x00 },
++	{ 0x0300, 0x00 },
++	{ 0x0302, 0x2a },
++	{ 0x0303, 0x00 },
++	{ 0x0304, 0x03 },
++	{ 0x030b, 0x00 },
++	{ 0x030d, 0x1e },
++	{ 0x030e, 0x04 },
++	{ 0x030f, 0x01 },
++	{ 0x0312, 0x01 },
++	{ 0x031e, 0x00 },
++	{ 0x3000, 0x20 },
++	{ 0x3002, 0x00 },
++	{ 0x3018, 0x72 },
++	{ 0x3020, 0x93 },
++	{ 0x3021, 0x03 },
++	{ 0x3022, 0x01 },
++	{ 0x3031, 0x0a },
++	{ 0x303f, 0x0c },
++	{ 0x3305, 0xf1 },
++	{ 0x3307, 0x04 },
++	{ 0x3309, 0x29 },
++	{ 0x3500, 0x00 },
++	{ 0x3501, 0x4c },
++	{ 0x3502, 0x00 },
++	{ 0x3503, 0x04 },
++	{ 0x3504, 0x00 },
++	{ 0x3505, 0x00 },
++	{ 0x3506, 0x00 },
++	{ 0x3507, 0x00 },
++	{ 0x3508, 0x00 },
++	{ 0x3509, 0x80 },
++	{ 0x350a, 0x00 },
++	{ 0x350b, 0x00 },
++	{ 0x350c, 0x00 },
++	{ 0x350d, 0x00 },
++	{ 0x350e, 0x00 },
++	{ 0x350f, 0x80 },
++	{ 0x3510, 0x00 },
++	{ 0x3511, 0x00 },
++	{ 0x3512, 0x00 },
++	{ 0x3513, 0x00 },
++	{ 0x3514, 0x00 },
++	{ 0x3515, 0x80 },
++	{ 0x3516, 0x00 },
++	{ 0x3517, 0x00 },
++	{ 0x3518, 0x00 },
++	{ 0x3519, 0x00 },
++	{ 0x351a, 0x00 },
++	{ 0x351b, 0x80 },
++	{ 0x351c, 0x00 },
++	{ 0x351d, 0x00 },
++	{ 0x351e, 0x00 },
++	{ 0x351f, 0x00 },
++	{ 0x3520, 0x00 },
++	{ 0x3521, 0x80 },
++	{ 0x3522, 0x08 },
++	{ 0x3524, 0x08 },
++	{ 0x3526, 0x08 },
++	{ 0x3528, 0x08 },
++	{ 0x352a, 0x08 },
++	{ 0x3602, 0x00 },
++	{ 0x3603, 0x40 },
++	{ 0x3604, 0x02 },
++	{ 0x3605, 0x00 },
++	{ 0x3606, 0x00 },
++	{ 0x3607, 0x00 },
++	{ 0x3609, 0x12 },
++	{ 0x360a, 0x40 },
++	{ 0x360c, 0x08 },
++	{ 0x360f, 0xe5 },
++	{ 0x3608, 0x8f },
++	{ 0x3611, 0x00 },
++	{ 0x3613, 0xf7 },
++	{ 0x3616, 0x58 },
++	{ 0x3619, 0x99 },
++	{ 0x361b, 0x60 },
++	{ 0x361c, 0x7a },
++	{ 0x361e, 0x79 },
++	{ 0x361f, 0x02 },
++	{ 0x3632, 0x00 },
++	{ 0x3633, 0x10 },
++	{ 0x3634, 0x10 },
++	{ 0x3635, 0x10 },
++	{ 0x3636, 0x15 },
++	{ 0x3646, 0x86 },
++	{ 0x364a, 0x0b },
++	{ 0x3700, 0x17 },
++	{ 0x3701, 0x22 },
++	{ 0x3703, 0x10 },
++	{ 0x370a, 0x37 },
++	{ 0x3705, 0x00 },
++	{ 0x3706, 0x63 },
++	{ 0x3709, 0x3c },
++	{ 0x370b, 0x01 },
++	{ 0x370c, 0x30 },
++	{ 0x3710, 0x24 },
++	{ 0x3711, 0x0c },
++	{ 0x3716, 0x00 },
++	{ 0x3720, 0x28 },
++	{ 0x3729, 0x7b },
++	{ 0x372a, 0x84 },
++	{ 0x372b, 0xbd },
++	{ 0x372c, 0xbc },
++	{ 0x372e, 0x52 },
++	{ 0x373c, 0x0e },
++	{ 0x373e, 0x33 },
++	{ 0x3743, 0x10 },
++	{ 0x3744, 0x88 },
++	{ 0x3745, 0xc0 },
++	{ 0x374a, 0x43 },
++	{ 0x374c, 0x00 },
++	{ 0x374e, 0x23 },
++	{ 0x3751, 0x7b },
++	{ 0x3752, 0x84 },
++	{ 0x3753, 0xbd },
++	{ 0x3754, 0xbc },
++	{ 0x3756, 0x52 },
++	{ 0x375c, 0x00 },
++	{ 0x3760, 0x00 },
++	{ 0x3761, 0x00 },
++	{ 0x3762, 0x00 },
++	{ 0x3763, 0x00 },
++	{ 0x3764, 0x00 },
++	{ 0x3767, 0x04 },
++	{ 0x3768, 0x04 },
++	{ 0x3769, 0x08 },
++	{ 0x376a, 0x08 },
++	{ 0x376b, 0x20 },
++	{ 0x376c, 0x00 },
++	{ 0x376d, 0x00 },
++	{ 0x376e, 0x00 },
++	{ 0x3773, 0x00 },
++	{ 0x3774, 0x51 },
++	{ 0x3776, 0xbd },
++	{ 0x3777, 0xbd },
++	{ 0x3781, 0x18 },
++	{ 0x3783, 0x25 },
++	{ 0x3798, 0x1b },
++	{ 0x3800, 0x01 },
++	{ 0x3801, 0x88 },
++	{ 0x3802, 0x00 },
++	{ 0x3803, 0xe0 },
++	{ 0x3804, 0x09 },
++	{ 0x3805, 0x17 },
++	{ 0x3806, 0x05 },
++	{ 0x3807, 0x1f },
++	{ 0x3808, 0x07 },
++	{ 0x3809, 0x80 },
++	{ 0x380a, 0x04 },
++	{ 0x380b, 0x38 },
++	{ 0x380c, 0x03 },
++	{ 0x380d, 0x5c },
++	{ 0x380e, 0x04 },
++	{ 0x380f, 0x8A },
++	{ 0x3810, 0x00 },
++	{ 0x3811, 0x08 },
++	{ 0x3812, 0x00 },
++	{ 0x3813, 0x04 },
++	{ 0x3814, 0x01 },
++	{ 0x3815, 0x01 },
++	{ 0x3819, 0x01 },
++	{ 0x3820, 0x00 },
++	{ 0x3821, 0x06 },
++	{ 0x3829, 0x00 },
++	{ 0x382a, 0x01 },
++	{ 0x382b, 0x01 },
++	{ 0x382d, 0x7f },
++	{ 0x3830, 0x04 },
++	{ 0x3836, 0x01 },
++	{ 0x3837, 0x00 },
++	{ 0x3841, 0x02 },
++	{ 0x3846, 0x08 },
++	{ 0x3847, 0x07 },
++	{ 0x3d85, 0x36 },
++	{ 0x3d8c, 0x71 },
++	{ 0x3d8d, 0xcb },
++	{ 0x3f0a, 0x00 },
++	{ 0x4000, 0xf1 },
++	{ 0x4001, 0x40 },
++	{ 0x4002, 0x04 },
++	{ 0x4003, 0x14 },
++	{ 0x400e, 0x00 },
++	{ 0x4011, 0x00 },
++	{ 0x401a, 0x00 },
++	{ 0x401b, 0x00 },
++	{ 0x401c, 0x00 },
++	{ 0x401d, 0x00 },
++	{ 0x401f, 0x00 },
++	{ 0x4020, 0x00 },
++	{ 0x4021, 0x10 },
++	{ 0x4022, 0x06 },
++	{ 0x4023, 0x13 },
++	{ 0x4024, 0x07 },
++	{ 0x4025, 0x40 },
++	{ 0x4026, 0x07 },
++	{ 0x4027, 0x50 },
++	{ 0x4028, 0x00 },
++	{ 0x4029, 0x02 },
++	{ 0x402a, 0x06 },
++	{ 0x402b, 0x04 },
++	{ 0x402c, 0x02 },
++	{ 0x402d, 0x02 },
++	{ 0x402e, 0x0e },
++	{ 0x402f, 0x04 },
++	{ 0x4302, 0xff },
++	{ 0x4303, 0xff },
++	{ 0x4304, 0x00 },
++	{ 0x4305, 0x00 },
++	{ 0x4306, 0x00 },
++	{ 0x4308, 0x02 },
++	{ 0x4500, 0x6c },
++	{ 0x4501, 0xc4 },
++	{ 0x4502, 0x40 },
++	{ 0x4503, 0x01 },
++	{ 0x4601, 0x77 },
++	{ 0x4800, 0x04 },
++	{ 0x4813, 0x08 },
++	{ 0x481f, 0x40 },
++	{ 0x4829, 0x78 },
++	{ 0x4837, 0x10 },
++	{ 0x4b00, 0x2a },
++	{ 0x4b0d, 0x00 },
++	{ 0x4d00, 0x04 },
++	{ 0x4d01, 0x42 },
++	{ 0x4d02, 0xd1 },
++	{ 0x4d03, 0x93 },
++	{ 0x4d04, 0xf5 },
++	{ 0x4d05, 0xc1 },
++	{ 0x5000, 0xf3 },
++	{ 0x5001, 0x11 },
++	{ 0x5004, 0x00 },
++	{ 0x500a, 0x00 },
++	{ 0x500b, 0x00 },
++	{ 0x5032, 0x00 },
++	{ 0x5040, 0x00 },
++	{ 0x5050, 0x0c },
++	{ 0x5500, 0x00 },
++	{ 0x5501, 0x10 },
++	{ 0x5502, 0x01 },
++	{ 0x5503, 0x0f },
++	{ 0x8000, 0x00 },
++	{ 0x8001, 0x00 },
++	{ 0x8002, 0x00 },
++	{ 0x8003, 0x00 },
++	{ 0x8004, 0x00 },
++	{ 0x8005, 0x00 },
++	{ 0x8006, 0x00 },
++	{ 0x8007, 0x00 },
++	{ 0x8008, 0x00 },
++	{ 0x3638, 0x00 },
++	{ 0x0100, 0x00 },
++	{ 0x5040, 0x80 },
++	{OV4689_REG_END, 0x00},/* END MARKER */
++};
++
++static struct regval_list ov4689_init_regs_1920_1080_30fps_mipi[] = {
++#if 0 //1080p@30fps 1 lane ok
++	/* @@ 0 35 RES_1920x1080_30fps_816Mbps  1Lane */
++	/* ;SCLK = 80MHz MIPI CLK = 816Mbps/lane Mipi PCLK = 102MHz */
++	/* ;HTS = 2294 VTS = 1162 */
++	{0x0103, 0x01},
++	{0x3638, 0x00},
++	{0x0300, 0x00},
++	{0x0302, 0x22},
++	{0x0303, 0x00},
++	{0x0304, 0x03},
++	{0x030b, 0x00},
++	{0x030d, 0x1e},
++	{0x030e, 0x04},
++	{0x030f, 0x02},
++	{0x0312, 0x01},
++	{0x031e, 0x00},
++	{0x3000, 0x20},
++	{0x3002, 0x00},
++	{0x3018, 0x02},
++	{0x3020, 0x93},
++	{0x3021, 0x03},
++	{0x3022, 0x01},
++	{0x3031, 0x0a},
++	{0x303f, 0x0c},
++	{0x3305, 0xf1},
++	{0x3307, 0x04},
++	{0x3309, 0x29},
++	{0x3500, 0x00},
++	{0x3501, 0x4c},
++	{0x3502, 0x00},
++	{0x3503, 0x04},
++	{0x3504, 0x00},
++	{0x3505, 0x00},
++	{0x3506, 0x00},
++	{0x3507, 0x00},
++	{0x3508, 0x00},
++	{0x3509, 0x80},
++	{0x350a, 0x00},
++	{0x350b, 0x00},
++	{0x350c, 0x00},
++	{0x350d, 0x00},
++	{0x350e, 0x00},
++	{0x350f, 0x80},
++	{0x3510, 0x00},
++	{0x3511, 0x00},
++	{0x3512, 0x00},
++	{0x3513, 0x00},
++	{0x3514, 0x00},
++	{0x3515, 0x80},
++	{0x3516, 0x00},
++	{0x3517, 0x00},
++	{0x3518, 0x00},
++	{0x3519, 0x00},
++	{0x351a, 0x00},
++	{0x351b, 0x80},
++	{0x351c, 0x00},
++	{0x351d, 0x00},
++	{0x351e, 0x00},
++	{0x351f, 0x00},
++	{0x3520, 0x00},
++	{0x3521, 0x80},
++	{0x3522, 0x08},
++	{0x3524, 0x08},
++	{0x3526, 0x08},
++	{0x3528, 0x08},
++	{0x352a, 0x08},
++	{0x3602, 0x00},
++	{0x3603, 0x40},
++	{0x3604, 0x02},
++	{0x3605, 0x00},
++	{0x3606, 0x00},
++	{0x3607, 0x00},
++	{0x3609, 0x12},
++	{0x360a, 0x40},
++	{0x360c, 0x08},
++	{0x360f, 0xe5},
++	{0x3608, 0x8f},
++	{0x3611, 0x00},
++	{0x3613, 0xf7},
++	{0x3616, 0x58},
++	{0x3619, 0x99},
++	{0x361b, 0x60},
++	{0x361c, 0x7a},
++	{0x361e, 0x79},
++	{0x361f, 0x02},
++	{0x3632, 0x00},
++	{0x3633, 0x10},
++	{0x3634, 0x10},
++	{0x3635, 0x10},
++	{0x3636, 0x15},
++	{0x3646, 0x86},
++	{0x364a, 0x0b},
++	{0x3700, 0x17},
++	{0x3701, 0x22},
++	{0x3703, 0x10},
++	{0x370a, 0x37},
++	{0x3705, 0x00},
++	{0x3706, 0x63},
++	{0x3709, 0x3c},
++	{0x370b, 0x01},
++	{0x370c, 0x30},
++	{0x3710, 0x24},
++	{0x3711, 0x0c},
++	{0x3716, 0x00},
++	{0x3720, 0x28},
++	{0x3729, 0x7b},
++	{0x372a, 0x84},
++	{0x372b, 0xbd},
++	{0x372c, 0xbc},
++	{0x372e, 0x52},
++	{0x373c, 0x0e},
++	{0x373e, 0x33},
++	{0x3743, 0x10},
++	{0x3744, 0x88},
++	{0x3745, 0xc0},
++	{0x374a, 0x43},
++	{0x374c, 0x00},
++	{0x374e, 0x23},
++	{0x3751, 0x7b},
++	{0x3752, 0x84},
++	{0x3753, 0xbd},
++	{0x3754, 0xbc},
++	{0x3756, 0x52},
++	{0x375c, 0x00},
++	{0x3760, 0x00},
++	{0x3761, 0x00},
++	{0x3762, 0x00},
++	{0x3763, 0x00},
++	{0x3764, 0x00},
++	{0x3767, 0x04},
++	{0x3768, 0x04},
++	{0x3769, 0x08},
++	{0x376a, 0x08},
++	{0x376b, 0x20},
++	{0x376c, 0x00},
++	{0x376d, 0x00},
++	{0x376e, 0x00},
++	{0x3773, 0x00},
++	{0x3774, 0x51},
++	{0x3776, 0xbd},
++	{0x3777, 0xbd},
++	{0x3781, 0x18},
++	{0x3783, 0x25},
++	{0x3798, 0x1b},
++	{0x3800, 0x01},
++	{0x3801, 0x88},
++	{0x3802, 0x00},
++	{0x3803, 0xe0},
++	{0x3804, 0x09},
++	{0x3805, 0x17},
++	{0x3806, 0x05},
++	{0x3807, 0x1f},
++	{0x3808, 0x07},
++	{0x3809, 0x80},
++	{0x380a, 0x04},
++	{0x380b, 0x38},
++	{0x380c, 0x08},
++	{0x380d, 0xf6},
++	{0x380e, 0x04},
++	{0x380f, 0x8A},
++	{0x3810, 0x00},
++	{0x3811, 0x08},
++	{0x3812, 0x00},
++	{0x3813, 0x04},
++	{0x3814, 0x01},
++	{0x3815, 0x01},
++	{0x3819, 0x01},
++	{0x3820, 0x00},
++	{0x3821, 0x06},
++	{0x3829, 0x00},
++	{0x382a, 0x01},
++	{0x382b, 0x01},
++	{0x382d, 0x7f},
++	{0x3830, 0x04},
++	{0x3836, 0x01},
++	{0x3837, 0x00},
++	{0x3841, 0x02},
++	{0x3846, 0x08},
++	{0x3847, 0x07},
++	{0x3d85, 0x36},
++	{0x3d8c, 0x71},
++	{0x3d8d, 0xcb},
++	{0x3f0a, 0x00},
++	{0x4000, 0xf1},
++	{0x4001, 0x40},
++	{0x4002, 0x04},
++	{0x4003, 0x14},
++	{0x400e, 0x00},
++	{0x4011, 0x00},
++	{0x401a, 0x00},
++	{0x401b, 0x00},
++	{0x401c, 0x00},
++	{0x401d, 0x00},
++	{0x401f, 0x00},
++	{0x4020, 0x00},
++	{0x4021, 0x10},
++	{0x4022, 0x06},
++	{0x4023, 0x13},
++	{0x4024, 0x07},
++	{0x4025, 0x40},
++	{0x4026, 0x07},
++	{0x4027, 0x50},
++	{0x4028, 0x00},
++	{0x4029, 0x02},
++	{0x402a, 0x06},
++	{0x402b, 0x04},
++	{0x402c, 0x02},
++	{0x402d, 0x02},
++	{0x402e, 0x0e},
++	{0x402f, 0x04},
++	{0x4302, 0xff},
++	{0x4303, 0xff},
++	{0x4304, 0x00},
++	{0x4305, 0x00},
++	{0x4306, 0x00},
++	{0x4308, 0x02},
++	{0x4500, 0x6c},
++	{0x4501, 0xc4},
++	{0x4502, 0x40},
++	{0x4503, 0x01},
++	{0x4601, 0x77},
++	{0x4800, 0x04},
++	{0x4813, 0x08},
++	{0x481f, 0x40},
++	{0x4829, 0x78},
++	{0x4837, 0x2d},
++	{0x4b00, 0x2a},
++	{0x4b0d, 0x00},
++	{0x4d00, 0x04},
++	{0x4d01, 0x42},
++	{0x4d02, 0xd1},
++	{0x4d03, 0x93},
++	{0x4d04, 0xf5},
++	{0x4d05, 0xc1},
++	{0x5000, 0xf3},
++	{0x5001, 0x11},
++	{0x5004, 0x00},
++	{0x500a, 0x00},
++	{0x500b, 0x00},
++	{0x5032, 0x00},
++	{0x5040, 0x00},
++	{0x5050, 0x0c},
++	{0x5500, 0x00},
++	{0x5501, 0x10},
++	{0x5502, 0x01},
++	{0x5503, 0x0f},
++	{0x8000, 0x00},
++	{0x8001, 0x00},
++	{0x8002, 0x00},
++	{0x8003, 0x00},
++	{0x8004, 0x00},
++	{0x8005, 0x00},
++	{0x8006, 0x00},
++	{0x8007, 0x00},
++	{0x8008, 0x00},
++	{0x3638, 0x00},
++#endif
++#if 1
++	//1080p@30fps 2 or 4 lane
++	/* @@ 0 35 RES_1920x1080_30fps_816Mbps  2Lane */
++	/* ;SCLK = 80MHz MIPI CLK = 816Mbps/lane Mipi PCLK = 102MHz */
++	/* ;HTS = 2294 VTS = 1162 */
++	{0x0103, 0x01},
++	{0x3638, 0x00},
++	{0x0300, 0x00},
++	{0x0302, 0x23},
++	{0x0303, 0x01},
++	{0x0304, 0x03},
++	{0x030b, 0x00},
++	{0x030d, 0x1e},
++	{0x030e, 0x04},
++	{0x030f, 0x02},
++	{0x0312, 0x01},
++	{0x031e, 0x00},
++	{0x3000, 0x20},
++	{0x3002, 0x00},
++//	{0x3018, 0x72}, //4lan
++	{0x3018, 0x32}, //2lan
++	{0x3020, 0x93},
++	{0x3021, 0x03},
++	{0x3022, 0x01},
++	{0x3031, 0x0a},
++	{0x303f, 0x0c},
++	{0x3305, 0xf1},
++	{0x3307, 0x04},
++	{0x3309, 0x29},
++	{0x3500, 0x00},
++	{0x3501, 0x4c},
++	{0x3502, 0x00},
++	{0x3503, 0x04},
++	{0x3504, 0x00},
++	{0x3505, 0x00},
++	{0x3506, 0x00},
++	{0x3507, 0x00},
++	{0x3508, 0x00},
++	{0x3509, 0x80},
++	{0x350a, 0x00},
++	{0x350b, 0x00},
++	{0x350c, 0x00},
++	{0x350d, 0x00},
++	{0x350e, 0x00},
++	{0x350f, 0x80},
++	{0x3510, 0x00},
++	{0x3511, 0x00},
++	{0x3512, 0x00},
++	{0x3513, 0x00},
++	{0x3514, 0x00},
++	{0x3515, 0x80},
++	{0x3516, 0x00},
++	{0x3517, 0x00},
++	{0x3518, 0x00},
++	{0x3519, 0x00},
++	{0x351a, 0x00},
++	{0x351b, 0x80},
++	{0x351c, 0x00},
++	{0x351d, 0x00},
++	{0x351e, 0x00},
++	{0x351f, 0x00},
++	{0x3520, 0x00},
++	{0x3521, 0x80},
++	{0x3522, 0x08},
++	{0x3524, 0x08},
++	{0x3526, 0x08},
++	{0x3528, 0x08},
++	{0x352a, 0x08},
++	{0x3602, 0x00},
++	{0x3603, 0x40},
++	{0x3604, 0x02},
++	{0x3605, 0x00},
++	{0x3606, 0x00},
++	{0x3607, 0x00},
++	{0x3609, 0x12},
++	{0x360a, 0x40},
++	{0x360c, 0x08},
++	{0x360f, 0xe5},
++	{0x3608, 0x8f},
++	{0x3611, 0x00},
++	{0x3613, 0xf7},
++	{0x3616, 0x58},
++	{0x3619, 0x99},
++	{0x361b, 0x60},
++	{0x361c, 0x7a},
++	{0x361e, 0x79},
++	{0x361f, 0x02},
++	{0x3632, 0x00},
++	{0x3633, 0x10},
++	{0x3634, 0x10},
++	{0x3635, 0x10},
++	{0x3636, 0x15},
++	{0x3646, 0x86},
++	{0x364a, 0x0b},
++	{0x3700, 0x17},
++	{0x3701, 0x22},
++	{0x3703, 0x10},
++	{0x370a, 0x37},
++	{0x3705, 0x00},
++	{0x3706, 0x63},
++	{0x3709, 0x3c},
++	{0x370b, 0x01},
++	{0x370c, 0x30},
++	{0x3710, 0x24},
++	{0x3711, 0x0c},
++	{0x3716, 0x00},
++	{0x3720, 0x28},
++	{0x3729, 0x7b},
++	{0x372a, 0x84},
++	{0x372b, 0xbd},
++	{0x372c, 0xbc},
++	{0x372e, 0x52},
++	{0x373c, 0x0e},
++	{0x373e, 0x33},
++	{0x3743, 0x10},
++	{0x3744, 0x88},
++	{0x3745, 0xc0},
++	{0x374a, 0x43},
++	{0x374c, 0x00},
++	{0x374e, 0x23},
++	{0x3751, 0x7b},
++	{0x3752, 0x84},
++	{0x3753, 0xbd},
++	{0x3754, 0xbc},
++	{0x3756, 0x52},
++	{0x375c, 0x00},
++	{0x3760, 0x00},
++	{0x3761, 0x00},
++	{0x3762, 0x00},
++	{0x3763, 0x00},
++	{0x3764, 0x00},
++	{0x3767, 0x04},
++	{0x3768, 0x04},
++	{0x3769, 0x08},
++	{0x376a, 0x08},
++	{0x376b, 0x20},
++	{0x376c, 0x00},
++	{0x376d, 0x00},
++	{0x376e, 0x00},
++	{0x3773, 0x00},
++	{0x3774, 0x51},
++	{0x3776, 0xbd},
++	{0x3777, 0xbd},
++	{0x3781, 0x18},
++	{0x3783, 0x25},
++	{0x3798, 0x1b},
++	{0x3800, 0x01},
++	{0x3801, 0x88},
++	{0x3802, 0x00},
++	{0x3803, 0xe0},
++	{0x3804, 0x09},
++	{0x3805, 0x17},
++	{0x3806, 0x05},
++	{0x3807, 0x1f},
++	{0x3808, 0x07},
++	{0x3809, 0x80},
++	{0x380a, 0x04},
++	{0x380b, 0x38},
++	{0x380c, 0x08},
++	{0x380d, 0xf6},
++	{0x380e, 0x04},
++	{0x380f, 0x8A},
++	{0x3810, 0x00},
++	{0x3811, 0x08},
++	{0x3812, 0x00},
++	{0x3813, 0x04},
++	{0x3814, 0x01},
++	{0x3815, 0x01},
++	{0x3819, 0x01},
++	{0x3820, 0x00},
++	{0x3821, 0x06},
++	{0x3829, 0x00},
++	{0x382a, 0x01},
++	{0x382b, 0x01},
++	{0x382d, 0x7f},
++	{0x3830, 0x04},
++	{0x3836, 0x01},
++	{0x3837, 0x00},
++	{0x3841, 0x02},
++	{0x3846, 0x08},
++	{0x3847, 0x07},
++	{0x3d85, 0x36},
++	{0x3d8c, 0x71},
++	{0x3d8d, 0xcb},
++	{0x3f0a, 0x00},
++	{0x4000, 0xf1},
++	{0x4001, 0x40},
++	{0x4002, 0x04},
++	{0x4003, 0x14},
++	{0x400e, 0x00},
++	{0x4011, 0x00},
++	{0x401a, 0x00},
++	{0x401b, 0x00},
++	{0x401c, 0x00},
++	{0x401d, 0x00},
++	{0x401f, 0x00},
++	{0x4020, 0x00},
++	{0x4021, 0x10},
++	{0x4022, 0x06},
++	{0x4023, 0x13},
++	{0x4024, 0x07},
++	{0x4025, 0x40},
++	{0x4026, 0x07},
++	{0x4027, 0x50},
++	{0x4028, 0x00},
++	{0x4029, 0x02},
++	{0x402a, 0x06},
++	{0x402b, 0x04},
++	{0x402c, 0x02},
++	{0x402d, 0x02},
++	{0x402e, 0x0e},
++	{0x402f, 0x04},
++	{0x4302, 0xff},
++	{0x4303, 0xff},
++	{0x4304, 0x00},
++	{0x4305, 0x00},
++	{0x4306, 0x00},
++	{0x4308, 0x02},
++	{0x4500, 0x6c},
++	{0x4501, 0xc4},
++	{0x4502, 0x40},
++	{0x4503, 0x01},
++	{0x4601, 0x77},
++	{0x4800, 0x04},
++	{0x4813, 0x08},
++	{0x481f, 0x40},
++	{0x4829, 0x78},
++	{0x4837, 0x14}, //for zebra/panda
++	/* {0x4837, 0x80}, //for halley5 */
++	{0x4b00, 0x2a},
++	{0x4b0d, 0x00},
++	{0x4d00, 0x04},
++	{0x4d01, 0x42},
++	{0x4d02, 0xd1},
++	{0x4d03, 0x93},
++	{0x4d04, 0xf5},
++	{0x4d05, 0xc1},
++	{0x5000, 0xf3},
++	{0x5001, 0x11},
++	{0x5004, 0x00},
++	{0x500a, 0x00},
++	{0x500b, 0x00},
++	{0x5032, 0x00},
++	{0x5040, 0x00},
++	{0x5050, 0x0c},
++	{0x5500, 0x00},
++	{0x5501, 0x10},
++	{0x5502, 0x01},
++	{0x5503, 0x0f},
++	{0x8000, 0x00},
++	{0x8001, 0x00},
++	{0x8002, 0x00},
++	{0x8003, 0x00},
++	{0x8004, 0x00},
++	{0x8005, 0x00},
++	{0x8006, 0x00},
++	{0x8007, 0x00},
++	{0x8008, 0x00},
++	{0x3638, 0x00},
++#endif
++#if 0
++	/*support by ov , dosen't word in zebra & halley5*/
++//	@@ 0 35 RES_1920x1080_30fps_1008Mbps 4lane
++//100 99 1920 1080
++//102 3601 2ee0
++	{ 0x0103, 0x01 },
++	{ 0x3638, 0x00 },
++	{ 0x0300, 0x00 },
++	{ 0x0302, 0x2a },
++	{ 0x0303, 0x00 },
++	{ 0x0304, 0x03 },
++	{ 0x030b, 0x00 },
++	{ 0x030d, 0x1e },
++	{ 0x030e, 0x04 },
++	{ 0x030f, 0x01 },
++	{ 0x0312, 0x01 },
++	{ 0x031e, 0x00 },
++	{ 0x3000, 0x20 },
++	{ 0x3002, 0x00 },
++	{ 0x3018, 0x72 },
++//	{ 0x3018, 0x32 },
++	{ 0x3020, 0x93 },
++	{ 0x3021, 0x03 },
++	{ 0x3022, 0x01 },
++	{ 0x3031, 0x0a },
++	{ 0x303f, 0x0c },
++	{ 0x3305, 0xf1 },
++	{ 0x3307, 0x04 },
++	{ 0x3309, 0x29 },
++	{ 0x3500, 0x00 },
++	{ 0x3501, 0x4c },
++	{ 0x3502, 0x00 },
++	{ 0x3503, 0x04 },
++	{ 0x3504, 0x00 },
++	{ 0x3505, 0x00 },
++	{ 0x3506, 0x00 },
++	{ 0x3507, 0x00 },
++	{ 0x3508, 0x00 },
++	{ 0x3509, 0x80 },
++	{ 0x350a, 0x00 },
++	{ 0x350b, 0x00 },
++	{ 0x350c, 0x00 },
++	{ 0x350d, 0x00 },
++	{ 0x350e, 0x00 },
++	{ 0x350f, 0x80 },
++	{ 0x3510, 0x00 },
++	{ 0x3511, 0x00 },
++	{ 0x3512, 0x00 },
++	{ 0x3513, 0x00 },
++	{ 0x3514, 0x00 },
++	{ 0x3515, 0x80 },
++	{ 0x3516, 0x00 },
++	{ 0x3517, 0x00 },
++	{ 0x3518, 0x00 },
++	{ 0x3519, 0x00 },
++	{ 0x351a, 0x00 },
++	{ 0x351b, 0x80 },
++	{ 0x351c, 0x00 },
++	{ 0x351d, 0x00 },
++	{ 0x351e, 0x00 },
++	{ 0x351f, 0x00 },
++	{ 0x3520, 0x00 },
++	{ 0x3521, 0x80 },
++	{ 0x3522, 0x08 },
++	{ 0x3524, 0x08 },
++	{ 0x3526, 0x08 },
++	{ 0x3528, 0x08 },
++	{ 0x352a, 0x08 },
++	{ 0x3602, 0x00 },
++	{ 0x3603, 0x40 },
++	{ 0x3604, 0x02 },
++	{ 0x3605, 0x00 },
++	{ 0x3606, 0x00 },
++	{ 0x3607, 0x00 },
++	{ 0x3609, 0x12 },
++	{ 0x360a, 0x40 },
++	{ 0x360c, 0x08 },
++	{ 0x360f, 0xe5 },
++	{ 0x3608, 0x8f },
++	{ 0x3611, 0x00 },
++	{ 0x3613, 0xf7 },
++	{ 0x3616, 0x58 },
++	{ 0x3619, 0x99 },
++	{ 0x361b, 0x60 },
++	{ 0x361c, 0x7a },
++	{ 0x361e, 0x79 },
++	{ 0x361f, 0x02 },
++	{ 0x3632, 0x00 },
++	{ 0x3633, 0x10 },
++	{ 0x3634, 0x10 },
++	{ 0x3635, 0x10 },
++	{ 0x3636, 0x15 },
++	{ 0x3646, 0x86 },
++	{ 0x364a, 0x0b },
++	{ 0x3700, 0x17 },
++	{ 0x3701, 0x22 },
++	{ 0x3703, 0x10 },
++	{ 0x370a, 0x37 },
++	{ 0x3705, 0x00 },
++	{ 0x3706, 0x63 },
++	{ 0x3709, 0x3c },
++	{ 0x370b, 0x01 },
++	{ 0x370c, 0x30 },
++	{ 0x3710, 0x24 },
++	{ 0x3711, 0x0c },
++	{ 0x3716, 0x00 },
++	{ 0x3720, 0x28 },
++	{ 0x3729, 0x7b },
++	{ 0x372a, 0x84 },
++	{ 0x372b, 0xbd },
++	{ 0x372c, 0xbc },
++	{ 0x372e, 0x52 },
++	{ 0x373c, 0x0e },
++	{ 0x373e, 0x33 },
++	{ 0x3743, 0x10 },
++	{ 0x3744, 0x88 },
++	{ 0x3745, 0xc0 },
++	{ 0x374a, 0x43 },
++	{ 0x374c, 0x00 },
++	{ 0x374e, 0x23 },
++	{ 0x3751, 0x7b },
++	{ 0x3752, 0x84 },
++	{ 0x3753, 0xbd },
++	{ 0x3754, 0xbc },
++	{ 0x3756, 0x52 },
++	{ 0x375c, 0x00 },
++	{ 0x3760, 0x00 },
++	{ 0x3761, 0x00 },
++	{ 0x3762, 0x00 },
++	{ 0x3763, 0x00 },
++	{ 0x3764, 0x00 },
++	{ 0x3767, 0x04 },
++	{ 0x3768, 0x04 },
++	{ 0x3769, 0x08 },
++	{ 0x376a, 0x08 },
++	{ 0x376b, 0x20 },
++	{ 0x376c, 0x00 },
++	{ 0x376d, 0x00 },
++	{ 0x376e, 0x00 },
++	{ 0x3773, 0x00 },
++	{ 0x3774, 0x51 },
++	{ 0x3776, 0xbd },
++	{ 0x3777, 0xbd },
++	{ 0x3781, 0x18 },
++	{ 0x3783, 0x25 },
++	{ 0x3798, 0x1b },
++	{ 0x3800, 0x01 },
++	{ 0x3801, 0x88 },
++	{ 0x3802, 0x00 },
++	{ 0x3803, 0xe0 },
++	{ 0x3804, 0x09 },
++	{ 0x3805, 0x17 },
++	{ 0x3806, 0x05 },
++	{ 0x3807, 0x1f },
++	{ 0x3808, 0x07 },
++	{ 0x3809, 0x80 },
++	{ 0x380a, 0x04 },
++	{ 0x380b, 0x38 },
++	{ 0x380c, 0x06 },
++	{ 0x380d, 0xb8 },
++	{ 0x380e, 0x09 },
++	{ 0x380f, 0x14 },
++	{ 0x3810, 0x00 },
++	{ 0x3811, 0x08 },
++	{ 0x3812, 0x00 },
++	{ 0x3813, 0x04 },
++	{ 0x3814, 0x01 },
++	{ 0x3815, 0x01 },
++	{ 0x3819, 0x01 },
++	{ 0x3820, 0x00 },
++	{ 0x3821, 0x06 },
++	{ 0x3829, 0x00 },
++	{ 0x382a, 0x01 },
++	{ 0x382b, 0x01 },
++	{ 0x382d, 0x7f },
++	{ 0x3830, 0x04 },
++	{ 0x3836, 0x01 },
++	{ 0x3837, 0x00 },
++	{ 0x3841, 0x02 },
++	{ 0x3846, 0x08 },
++	{ 0x3847, 0x07 },
++	{ 0x3d85, 0x36 },
++	{ 0x3d8c, 0x71 },
++	{ 0x3d8d, 0xcb },
++	{ 0x3f0a, 0x00 },
++	{ 0x4000, 0xf1 },
++	{ 0x4001, 0x40 },
++	{ 0x4002, 0x04 },
++	{ 0x4003, 0x14 },
++	{ 0x400e, 0x00 },
++	{ 0x4011, 0x00 },
++	{ 0x401a, 0x00 },
++	{ 0x401b, 0x00 },
++	{ 0x401c, 0x00 },
++	{ 0x401d, 0x00 },
++	{ 0x401f, 0x00 },
++	{ 0x4020, 0x00 },
++	{ 0x4021, 0x10 },
++	{ 0x4022, 0x06 },
++	{ 0x4023, 0x13 },
++	{ 0x4024, 0x07 },
++	{ 0x4025, 0x40 },
++	{ 0x4026, 0x07 },
++	{ 0x4027, 0x50 },
++	{ 0x4028, 0x00 },
++	{ 0x4029, 0x02 },
++	{ 0x402a, 0x06 },
++	{ 0x402b, 0x04 },
++	{ 0x402c, 0x02 },
++	{ 0x402d, 0x02 },
++	{ 0x402e, 0x0e },
++	{ 0x402f, 0x04 },
++	{ 0x4302, 0xff },
++	{ 0x4303, 0xff },
++	{ 0x4304, 0x00 },
++	{ 0x4305, 0x00 },
++	{ 0x4306, 0x00 },
++	{ 0x4308, 0x02 },
++	{ 0x4500, 0x6c },
++	{ 0x4501, 0xc4 },
++	{ 0x4502, 0x40 },
++	{ 0x4503, 0x01 },
++	{ 0x4601, 0x77 },
++	{ 0x4800, 0x04 },
++	{ 0x4813, 0x08 },
++	{ 0x481f, 0x40 },
++	{ 0x4829, 0x78 },
++	{ 0x4837, 0x10 },
++	{ 0x4b00, 0x2a },
++	{ 0x4b0d, 0x00 },
++	{ 0x4d00, 0x04 },
++	{ 0x4d01, 0x42 },
++	{ 0x4d02, 0xd1 },
++	{ 0x4d03, 0x93 },
++	{ 0x4d04, 0xf5 },
++	{ 0x4d05, 0xc1 },
++	{ 0x5000, 0xf3 },
++	{ 0x5001, 0x11 },
++	{ 0x5004, 0x00 },
++	{ 0x500a, 0x00 },
++	{ 0x500b, 0x00 },
++	{ 0x5032, 0x00 },
++	{ 0x5040, 0x00 },
++	{ 0x5050, 0x0c },
++	{ 0x5500, 0x00 },
++	{ 0x5501, 0x10 },
++	{ 0x5502, 0x01 },
++	{ 0x5503, 0x0f },
++	{ 0x8000, 0x00 },
++	{ 0x8001, 0x00 },
++	{ 0x8002, 0x00 },
++	{ 0x8003, 0x00 },
++	{ 0x8004, 0x00 },
++	{ 0x8005, 0x00 },
++	{ 0x8006, 0x00 },
++	{ 0x8007, 0x00 },
++	{ 0x8008, 0x00 },
++	{ 0x3638, 0x00 },
++#endif
++	{0x0100, 0x00},
++//	{0x5040, 0x80},
++	{OV4689_REG_END, 0x00},/* END MARKER */
++};
++
++static struct regval_list ov4689_init_regs_2048_1520_30fps_mipi[] = {
++#if 0
++	/* @@ 0 35 RES_2048x1520_23.37fps_408Mbps  2Lane */
++	/* ;SCLK = 80MHz MIPI CLK = 408Mbps/lane Mipi PCLK = 51MHz */
++	/* ;HTS = 2200 VTS = 1556 */
++	{0x0103, 0x01},
++	{0x3638, 0x00},
++	{0x0300, 0x00},
++	{0x0302, 0x22},
++	{0x0303, 0x01},
++	{0x0304, 0x03},
++	{0x030b, 0x00},
++	{0x030d, 0x1e},
++	{0x030e, 0x04},
++	{0x030f, 0x02},
++	{0x0312, 0x01},
++	{0x031e, 0x00},
++	{0x3000, 0x20},
++	{0x3002, 0x00},
++	{0x3018, 0x32},
++	{0x3020, 0x93},
++	{0x3021, 0x03},
++	{0x3022, 0x01},
++	{0x3031, 0x0a},
++	{0x303f, 0x0c},
++	{0x3305, 0xf1},
++	{0x3307, 0x04},
++	{0x3309, 0x29},
++	{0x3500, 0x00},
++	{0x3501, 0x4c},
++	{0x3502, 0x00},
++	{0x3503, 0x04},
++	{0x3504, 0x00},
++	{0x3505, 0x00},
++	{0x3506, 0x00},
++	{0x3507, 0x00},
++	{0x3508, 0x00},
++	{0x3509, 0x80},
++	{0x350a, 0x00},
++	{0x350b, 0x00},
++	{0x350c, 0x00},
++	{0x350d, 0x00},
++	{0x350e, 0x00},
++	{0x350f, 0x80},
++	{0x3510, 0x00},
++	{0x3511, 0x00},
++	{0x3512, 0x00},
++	{0x3513, 0x00},
++	{0x3514, 0x00},
++	{0x3515, 0x80},
++	{0x3516, 0x00},
++	{0x3517, 0x00},
++	{0x3518, 0x00},
++	{0x3519, 0x00},
++	{0x351a, 0x00},
++	{0x351b, 0x80},
++	{0x351c, 0x00},
++	{0x351d, 0x00},
++	{0x351e, 0x00},
++	{0x351f, 0x00},
++	{0x3520, 0x00},
++	{0x3521, 0x80},
++	{0x3522, 0x08},
++	{0x3524, 0x08},
++	{0x3526, 0x08},
++	{0x3528, 0x08},
++	{0x352a, 0x08},
++	{0x3602, 0x00},
++	{0x3603, 0x40},
++	{0x3604, 0x02},
++	{0x3605, 0x00},
++	{0x3606, 0x00},
++	{0x3607, 0x00},
++	{0x3609, 0x12},
++	{0x360a, 0x40},
++	{0x360c, 0x08},
++	{0x360f, 0xe5},
++	{0x3608, 0x8f},
++	{0x3611, 0x00},
++	{0x3613, 0xf7},
++	{0x3616, 0x58},
++	{0x3619, 0x99},
++	{0x361b, 0x60},
++	{0x361c, 0x7a},
++	{0x361e, 0x79},
++	{0x361f, 0x02},
++	{0x3632, 0x00},
++	{0x3633, 0x10},
++	{0x3634, 0x10},
++	{0x3635, 0x10},
++	{0x3636, 0x15},
++	{0x3646, 0x86},
++	{0x364a, 0x0b},
++	{0x3700, 0x17},
++	{0x3701, 0x22},
++	{0x3703, 0x10},
++	{0x370a, 0x37},
++	{0x3705, 0x00},
++	{0x3706, 0x63},
++	{0x3709, 0x3c},
++	{0x370b, 0x01},
++	{0x370c, 0x30},
++	{0x3710, 0x24},
++	{0x3711, 0x0c},
++	{0x3716, 0x00},
++	{0x3720, 0x28},
++	{0x3729, 0x7b},
++	{0x372a, 0x84},
++	{0x372b, 0xbd},
++	{0x372c, 0xbc},
++	{0x372e, 0x52},
++	{0x373c, 0x0e},
++	{0x373e, 0x33},
++	{0x3743, 0x10},
++	{0x3744, 0x88},
++	{0x3745, 0xc0},
++	{0x374a, 0x43},
++	{0x374c, 0x00},
++	{0x374e, 0x23},
++	{0x3751, 0x7b},
++	{0x3752, 0x84},
++	{0x3753, 0xbd},
++	{0x3754, 0xbc},
++	{0x3756, 0x52},
++	{0x375c, 0x00},
++	{0x3760, 0x00},
++	{0x3761, 0x00},
++	{0x3762, 0x00},
++	{0x3763, 0x00},
++	{0x3764, 0x00},
++	{0x3767, 0x04},
++	{0x3768, 0x04},
++	{0x3769, 0x08},
++	{0x376a, 0x08},
++	{0x376b, 0x20},
++	{0x376c, 0x00},
++	{0x376d, 0x00},
++	{0x376e, 0x00},
++	{0x3773, 0x00},
++	{0x3774, 0x51},
++	{0x3776, 0xbd},
++	{0x3777, 0xbd},
++	{0x3781, 0x18},
++	{0x3783, 0x25},
++	{0x3798, 0x1b},
++	{0x3800, 0x01},
++	{0x3801, 0x48},
++	{0x3802, 0x00},
++	{0x3803, 0x04},
++	{0x3804, 0x09},
++	{0x3805, 0x57},
++	{0x3806, 0x05},
++	{0x3807, 0xFB},
++	{0x3808, 0x08},
++	{0x3809, 0x00},
++	{0x380A, 0x05},
++	{0x380B, 0xF0},
++	{0x380C, 0x08},
++	{0x380D, 0x98},
++	{0x380E, 0x06},
++	{0x380F, 0x14},
++	{0x3810, 0x00},
++	{0x3811, 0x08},
++	{0x3812, 0x00},
++	{0x3813, 0x04},
++	{0x3814, 0x01},
++	{0x3815, 0x01},
++	{0x3819, 0x01},
++	{0x3820, 0x00},
++	{0x3821, 0x06},
++	{0x3829, 0x00},
++	{0x382a, 0x01},
++	{0x382b, 0x01},
++	{0x382d, 0x7f},
++	{0x3830, 0x04},
++	{0x3836, 0x01},
++	{0x3837, 0x00},
++	{0x3841, 0x02},
++	{0x3846, 0x08},
++	{0x3847, 0x07},
++	{0x3d85, 0x36},
++	{0x3d8c, 0x71},
++	{0x3d8d, 0xcb},
++	{0x3f0a, 0x00},
++	{0x4000, 0xf1},
++	{0x4001, 0x40},
++	{0x4002, 0x04},
++	{0x4003, 0x14},
++	{0x400e, 0x00},
++	{0x4011, 0x00},
++	{0x401a, 0x00},
++	{0x401b, 0x00},
++	{0x401c, 0x00},
++	{0x401d, 0x00},
++	{0x401f, 0x00},
++	{0x4020, 0x00},
++	{0x4021, 0x10},
++	{0x4022, 0x06},
++	{0x4023, 0x93},
++	{0x4024, 0x07},
++	{0x4025, 0xC0},
++	{0x4026, 0x07},
++	{0x4027, 0xD0},
++	{0x4028, 0x00},
++	{0x4029, 0x02},
++	{0x402a, 0x06},
++	{0x402b, 0x04},
++	{0x402c, 0x02},
++	{0x402d, 0x02},
++	{0x402e, 0x0e},
++	{0x402f, 0x04},
++	{0x4302, 0xff},
++	{0x4303, 0xff},
++	{0x4304, 0x00},
++	{0x4305, 0x00},
++	{0x4306, 0x00},
++	{0x4308, 0x02},
++	{0x4500, 0x6c},
++	{0x4501, 0xc4},
++	{0x4502, 0x40},
++	{0x4503, 0x01},
++	{0x4601, 0x7f},
++	{0x4800, 0x04},
++	{0x4813, 0x08},
++	{0x481f, 0x40},
++	{0x4829, 0x78},
++	{0x4837, 0x14},
++	{0x4b00, 0x2a},
++	{0x4b0d, 0x00},
++	{0x4d00, 0x04},
++	{0x4d01, 0x42},
++	{0x4d02, 0xd1},
++	{0x4d03, 0x93},
++	{0x4d04, 0xf5},
++	{0x4d05, 0xc1},
++	{0x5000, 0xf3},
++	{0x5001, 0x11},
++	{0x5004, 0x00},
++	{0x500a, 0x00},
++	{0x500b, 0x00},
++	{0x5032, 0x00},
++	{0x5040, 0x00},
++	{0x5050, 0x0c},
++	{0x5500, 0x00},
++	{0x5501, 0x10},
++	{0x5502, 0x01},
++	{0x5503, 0x0f},
++	{0x8000, 0x00},
++	{0x8001, 0x00},
++	{0x8002, 0x00},
++	{0x8003, 0x00},
++	{0x8004, 0x00},
++	{0x8005, 0x00},
++	{0x8006, 0x00},
++	{0x8007, 0x00},
++	{0x8008, 0x00},
++	{0x3638, 0x00},
++	{0x0100, 0x00},
++#endif
++
++#if 1
++	/* @@ 0 35 RES_2048x1520_30fps_600Mbps  2Lane                   */
++	/* ;SCLK = 120 MHz MIPI CLK = 600Mbps/lane Mipi PCLK = 75MHz         */
++	/* ;HTS = 2570 VTS = 1556      */
++	{0x0103, 0x01},
++	{0x3638, 0x00},
++	{0x0300, 0x00},
++	{0x0302, 0x19},
++	{0x0303, 0x00},
++	{0x0304, 0x03},
++	{0x030b, 0x00},
++	{0x030d, 0x1e},
++	{0x030e, 0x04},
++	{0x030f, 0x01},
++	{0x0312, 0x01},
++	{0x031e, 0x00},
++	{0x3000, 0x20},
++	{0x3002, 0x00},
++	{0x3018, 0x32},
++	{0x3020, 0x93},
++	{0x3021, 0x03},
++	{0x3022, 0x01},
++	{0x3031, 0x0a},
++	{0x303f, 0x0c},
++	{0x3305, 0xf1},
++	{0x3307, 0x04},
++	{0x3309, 0x29},
++	{0x3500, 0x00},
++	{0x3501, 0x4c},
++	{0x3502, 0x00},
++	{0x3503, 0x04},
++	{0x3504, 0x00},
++	{0x3505, 0x00},
++	{0x3506, 0x00},
++	{0x3507, 0x00},
++	{0x3508, 0x00},
++	{0x3509, 0x80},
++	{0x350a, 0x00},
++	{0x350b, 0x00},
++	{0x350c, 0x00},
++	{0x350d, 0x00},
++	{0x350e, 0x00},
++	{0x350f, 0x80},
++	{0x3510, 0x00},
++	{0x3511, 0x00},
++	{0x3512, 0x00},
++	{0x3513, 0x00},
++	{0x3514, 0x00},
++	{0x3515, 0x80},
++	{0x3516, 0x00},
++	{0x3517, 0x00},
++	{0x3518, 0x00},
++	{0x3519, 0x00},
++	{0x351a, 0x00},
++	{0x351b, 0x80},
++	{0x351c, 0x00},
++	{0x351d, 0x00},
++	{0x351e, 0x00},
++	{0x351f, 0x00},
++	{0x3520, 0x00},
++	{0x3521, 0x80},
++	{0x3522, 0x08},
++	{0x3524, 0x08},
++	{0x3526, 0x08},
++	{0x3528, 0x08},
++	{0x352a, 0x08},
++	{0x3602, 0x00},
++	{0x3603, 0x40},
++	{0x3604, 0x02},
++	{0x3605, 0x00},
++	{0x3606, 0x00},
++	{0x3607, 0x00},
++	{0x3609, 0x12},
++	{0x360a, 0x40},
++	{0x360c, 0x08},
++	{0x360f, 0xe5},
++	{0x3608, 0x8f},
++	{0x3611, 0x00},
++	{0x3613, 0xf7},
++	{0x3616, 0x58},
++	{0x3619, 0x99},
++	{0x361b, 0x60},
++	{0x361c, 0x7a},
++	{0x361e, 0x79},
++	{0x361f, 0x02},
++	{0x3632, 0x00},
++	{0x3633, 0x10},
++	{0x3634, 0x10},
++	{0x3635, 0x10},
++	{0x3636, 0x15},
++	{0x3646, 0x86},
++	{0x364a, 0x0b},
++	{0x3700, 0x17},
++	{0x3701, 0x22},
++	{0x3703, 0x10},
++	{0x370a, 0x37},
++	{0x3705, 0x00},
++	{0x3706, 0x63},
++	{0x3709, 0x3c},
++	{0x370b, 0x01},
++	{0x370c, 0x30},
++	{0x3710, 0x24},
++	{0x3711, 0x0c},
++	{0x3716, 0x00},
++	{0x3720, 0x28},
++	{0x3729, 0x7b},
++	{0x372a, 0x84},
++	{0x372b, 0xbd},
++	{0x372c, 0xbc},
++	{0x372e, 0x52},
++	{0x373c, 0x0e},
++	{0x373e, 0x33},
++	{0x3743, 0x10},
++	{0x3744, 0x88},
++	{0x3745, 0xc0},
++	{0x374a, 0x43},
++	{0x374c, 0x00},
++	{0x374e, 0x23},
++	{0x3751, 0x7b},
++	{0x3752, 0x84},
++	{0x3753, 0xbd},
++	{0x3754, 0xbc},
++	{0x3756, 0x52},
++	{0x375c, 0x00},
++	{0x3760, 0x00},
++	{0x3761, 0x00},
++	{0x3762, 0x00},
++	{0x3763, 0x00},
++	{0x3764, 0x00},
++	{0x3767, 0x04},
++	{0x3768, 0x04},
++	{0x3769, 0x08},
++	{0x376a, 0x08},
++	{0x376b, 0x20},
++	{0x376c, 0x00},
++	{0x376d, 0x00},
++	{0x376e, 0x00},
++	{0x3773, 0x00},
++	{0x3774, 0x51},
++	{0x3776, 0xbd},
++	{0x3777, 0xbd},
++	{0x3781, 0x18},
++	{0x3783, 0x25},
++	{0x3798, 0x1b},
++	{0x3800, 0x01},
++	{0x3801, 0x48},
++	{0x3802, 0x00},
++	{0x3803, 0x04},
++	{0x3804, 0x09},
++	{0x3805, 0x57},
++	{0x3806, 0x05},
++	{0x3807, 0xFB},
++	{0x3808, 0x08},
++	{0x3809, 0x00},
++	{0x380A, 0x05},
++	{0x380B, 0xF0},
++	{0x380C, 0x0a},
++	{0x380D, 0x0a},
++	{0x380E, 0x06},
++	{0x380F, 0x14},
++	{0x3810, 0x00},
++	{0x3811, 0x08},
++	{0x3812, 0x00},
++	{0x3813, 0x04},
++	{0x3814, 0x01},
++	{0x3815, 0x01},
++	{0x3819, 0x01},
++	{0x3820, 0x00},
++	{0x3821, 0x06},
++	{0x3829, 0x00},
++	{0x382a, 0x01},
++	{0x382b, 0x01},
++	{0x382d, 0x7f},
++	{0x3830, 0x04},
++	{0x3836, 0x01},
++	{0x3837, 0x00},
++	{0x3841, 0x02},
++	{0x3846, 0x08},
++	{0x3847, 0x07},
++	{0x3d85, 0x36},
++	{0x3d8c, 0x71},
++	{0x3d8d, 0xcb},
++	{0x3f0a, 0x00},
++	{0x4000, 0xf1},
++	{0x4001, 0x40},
++	{0x4002, 0x04},
++	{0x4003, 0x14},
++	{0x400e, 0x00},
++	{0x4011, 0x00},
++	{0x401a, 0x00},
++	{0x401b, 0x00},
++	{0x401c, 0x00},
++	{0x401d, 0x00},
++	{0x401f, 0x00},
++	{0x4020, 0x00},
++	{0x4021, 0x10},
++	{0x4022, 0x06},
++	{0x4023, 0x93},
++	{0x4024, 0x07},
++	{0x4025, 0xC0},
++	{0x4026, 0x07},
++	{0x4027, 0xD0},
++	{0x4028, 0x00},
++	{0x4029, 0x02},
++	{0x402a, 0x06},
++	{0x402b, 0x04},
++	{0x402c, 0x02},
++	{0x402d, 0x02},
++	{0x402e, 0x0e},
++	{0x402f, 0x04},
++	{0x4302, 0xff},
++	{0x4303, 0xff},
++	{0x4304, 0x00},
++	{0x4305, 0x00},
++	{0x4306, 0x00},
++	{0x4308, 0x02},
++	{0x4500, 0x6c},
++	{0x4501, 0xc4},
++	{0x4502, 0x40},
++	{0x4503, 0x01},
++	{0x4601, 0x7f},
++	{0x4800, 0x04},
++	{0x4813, 0x08},
++	{0x481f, 0x40},
++	{0x4829, 0x78},
++	{0x4837, 0x2d},
++	{0x4b00, 0x2a},
++	{0x4b0d, 0x00},
++	{0x4d00, 0x04},
++	{0x4d01, 0x42},
++	{0x4d02, 0xd1},
++	{0x4d03, 0x93},
++	{0x4d04, 0xf5},
++	{0x4d05, 0xc1},
++	{0x5000, 0xf3},
++	{0x5001, 0x11},
++	{0x5004, 0x00},
++	{0x500a, 0x00},
++	{0x500b, 0x00},
++	{0x5032, 0x00},
++	{0x5040, 0x00},
++	{0x5050, 0x0c},
++	{0x5500, 0x00},
++	{0x5501, 0x10},
++	{0x5502, 0x01},
++	{0x5503, 0x0f},
++	{0x8000, 0x00},
++	{0x8001, 0x00},
++	{0x8002, 0x00},
++	{0x8003, 0x00},
++	{0x8004, 0x00},
++	{0x8005, 0x00},
++	{0x8006, 0x00},
++	{0x8007, 0x00},
++	{0x8008, 0x00},
++	{0x3638, 0x00},
++	{0x0100, 0x00},
++#endif
++
++#if 0
++	/* @@ 0 35 RES_2048x1520_25fps_420Mbps  2Lane */
++	/* ;SCLK = 82.7MHz MIPI CLK = 420Mbps/lane Mipi PCLK = 52.5MHz */
++	/* ;HTS = 2125 VTS = 1556 */
++	{0x0103, 0x01},
++	{0x3638, 0x00},
++	{0x0300, 0x00},
++	{0x0302, 0x23},
++	{0x0303, 0x01},
++	{0x0304, 0x03},
++	{0x030b, 0x00},
++	{0x030d, 0x1f},
++	{0x030e, 0x04},
++	{0x030f, 0x02},
++	{0x0312, 0x01},
++	{0x031e, 0x00},
++	{0x3000, 0x20},
++	{0x3002, 0x00},
++#ifdef DRIVE_CAPABILITY_1
++	{0x3011,0x00},
++#elif defined(DRIVE_CAPABILITY_2)
++	{0x3011,0x20},
++#elif defined(DRIVE_CAPABILITY_3)
++	{0x3011,0x40},
++#elif defined(DRIVE_CAPABILITY_4)
++	{0x3011,0x60},
++#endif
++	{0x3018, 0x32},
++	{0x3020, 0x93},
++	{0x3021, 0x03},
++	{0x3022, 0x01},
++	{0x3031, 0x0a},
++	{0x303f, 0x0c},
++	{0x3037, 0x01},
++//	{0x303f, 0x0d},
++//	{0x3012, 0x22},
++	{0x3305, 0xf1},
++	{0x3307, 0x04},
++	{0x3309, 0x29},
++	{0x3500, 0x00},
++	{0x3501, 0x4c},
++	{0x3502, 0x00},
++	{0x3503, 0x04},
++	{0x3504, 0x00},
++	{0x3505, 0x00},
++	{0x3506, 0x00},
++	{0x3507, 0x00},
++	{0x3508, 0x00},
++	{0x3509, 0x80},
++	{0x350a, 0x00},
++	{0x350b, 0x00},
++	{0x350c, 0x00},
++	{0x350d, 0x00},
++	{0x350e, 0x00},
++	{0x350f, 0x80},
++	{0x3510, 0x00},
++	{0x3511, 0x00},
++	{0x3512, 0x00},
++	{0x3513, 0x00},
++	{0x3514, 0x00},
++	{0x3515, 0x80},
++	{0x3516, 0x00},
++	{0x3517, 0x00},
++	{0x3518, 0x00},
++	{0x3519, 0x00},
++	{0x351a, 0x00},
++	{0x351b, 0x80},
++	{0x351c, 0x00},
++	{0x351d, 0x00},
++	{0x351e, 0x00},
++	{0x351f, 0x00},
++	{0x3520, 0x00},
++	{0x3521, 0x80},
++	{0x3522, 0x08},
++	{0x3524, 0x08},
++	{0x3526, 0x08},
++	{0x3528, 0x08},
++	{0x352a, 0x08},
++	{0x3602, 0x00},
++	{0x3603, 0x40},
++	{0x3604, 0x02},
++	{0x3605, 0x00},
++	{0x3606, 0x00},
++	{0x3607, 0x00},
++	{0x3609, 0x12},
++	{0x360a, 0x40},
++	{0x360c, 0x08},
++	{0x360f, 0xe5},
++	{0x3608, 0x8f},
++	{0x3611, 0x00},
++	{0x3613, 0xf7},
++	{0x3616, 0x58},
++	{0x3619, 0x99},
++	{0x361b, 0x60},
++	{0x361c, 0x7a},
++	{0x361e, 0x79},
++	{0x361f, 0x02},
++	{0x3632, 0x00},
++	{0x3633, 0x10},
++	{0x3634, 0x10},
++	{0x3635, 0x10},
++	{0x3636, 0x15},
++	{0x3646, 0x86},
++	{0x364a, 0x0b},
++	{0x3700, 0x17},
++	{0x3701, 0x22},
++	{0x3703, 0x10},
++	{0x370a, 0x37},
++	{0x3705, 0x00},
++	{0x3706, 0x63},
++	{0x3709, 0x3c},
++	{0x370b, 0x01},
++	{0x370c, 0x30},
++	{0x3710, 0x24},
++	{0x3711, 0x0c},
++	{0x3716, 0x00},
++	{0x3720, 0x28},
++	{0x3729, 0x7b},
++	{0x372a, 0x84},
++	{0x372b, 0xbd},
++	{0x372c, 0xbc},
++	{0x372e, 0x52},
++	{0x373c, 0x0e},
++	{0x373e, 0x33},
++	{0x3743, 0x10},
++	{0x3744, 0x88},
++	{0x3745, 0xc0},
++	{0x374a, 0x43},
++	{0x374c, 0x00},
++	{0x374e, 0x23},
++	{0x3751, 0x7b},
++	{0x3752, 0x84},
++	{0x3753, 0xbd},
++	{0x3754, 0xbc},
++	{0x3756, 0x52},
++	{0x375c, 0x00},
++	{0x3760, 0x00},
++	{0x3761, 0x00},
++	{0x3762, 0x00},
++	{0x3763, 0x00},
++	{0x3764, 0x00},
++	{0x3767, 0x04},
++	{0x3768, 0x04},
++	{0x3769, 0x08},
++	{0x376a, 0x08},
++	{0x376b, 0x20},
++	{0x376c, 0x00},
++	{0x376d, 0x00},
++	{0x376e, 0x00},
++	{0x3773, 0x00},
++	{0x3774, 0x51},
++	{0x3776, 0xbd},
++	{0x3777, 0xbd},
++	{0x3781, 0x18},
++	{0x3783, 0x25},
++	{0x3798, 0x1b},
++	{0x3800, 0x01},
++	{0x3801, 0x48},
++	{0x3802, 0x00},
++	{0x3803, 0x04},
++	{0x3804, 0x09},
++	{0x3805, 0x57},
++	{0x3806, 0x05},
++	{0x3807, 0xFB},
++	{0x3808, 0x08},
++	{0x3809, 0x00},
++	{0x380A, 0x05},
++	{0x380B, 0xF0},
++	{0x380C, 0x08},
++	{0x380D, 0x4d},
++	{0x380E, 0x06},
++	{0x380F, 0x14},
++	{0x3810, 0x00},
++	{0x3811, 0x08},
++	{0x3812, 0x00},
++	{0x3813, 0x04},
++	{0x3814, 0x01},
++	{0x3815, 0x01},
++	{0x3819, 0x01},
++	{0x3820, 0x00},
++	{0x3821, 0x06},
++	{0x3829, 0x00},
++	{0x382a, 0x01},
++	{0x382b, 0x01},
++	{0x382d, 0x7f},
++	{0x3830, 0x04},
++	{0x3836, 0x01},
++	{0x3837, 0x00},
++	{0x3841, 0x02},
++	{0x3846, 0x08},
++	{0x3847, 0x07},
++	{0x3d85, 0x36},
++	{0x3d8c, 0x71},
++	{0x3d8d, 0xcb},
++	{0x3f0a, 0x00},
++	{0x4000, 0xf1},
++	{0x4001, 0x40},
++	{0x4002, 0x04},
++	{0x4003, 0x14},
++	{0x400e, 0x00},
++	{0x4011, 0x00},
++	{0x401a, 0x00},
++	{0x401b, 0x00},
++	{0x401c, 0x00},
++	{0x401d, 0x00},
++	{0x401f, 0x00},
++	{0x4020, 0x00},
++	{0x4021, 0x10},
++	{0x4022, 0x06},
++	{0x4023, 0x93},
++	{0x4024, 0x07},
++	{0x4025, 0xC0},
++	{0x4026, 0x07},
++	{0x4027, 0xD0},
++	{0x4028, 0x00},
++	{0x4029, 0x02},
++	{0x402a, 0x06},
++	{0x402b, 0x04},
++	{0x402c, 0x02},
++	{0x402d, 0x02},
++	{0x402e, 0x0e},
++	{0x402f, 0x04},
++	{0x4302, 0xff},
++	{0x4303, 0xff},
++	{0x4304, 0x00},
++	{0x4305, 0x00},
++	{0x4306, 0x00},
++	{0x4308, 0x02},
++	{0x4500, 0x6c},
++	{0x4501, 0xc4},
++	{0x4502, 0x40},
++	{0x4503, 0x01},
++	{0x4601, 0x7f},
++	{0x4800, 0x04},
++	{0x4813, 0x08},
++	{0x481f, 0x40},
++	{0x4829, 0x78},
++	{0x4837, 0x14},
++	{0x4b00, 0x2a},
++	{0x4b0d, 0x00},
++	{0x4d00, 0x04},
++	{0x4d01, 0x42},
++	{0x4d02, 0xd1},
++	{0x4d03, 0x93},
++	{0x4d04, 0xf5},
++	{0x4d05, 0xc1},
++	{0x5000, 0xf3},
++	{0x5001, 0x11},
++	{0x5004, 0x00},
++	{0x500a, 0x00},
++	{0x500b, 0x00},
++	{0x5032, 0x00},
++	{0x5040, 0x00},
++	{0x5050, 0x0c},
++	{0x5500, 0x00},
++	{0x5501, 0x10},
++	{0x5502, 0x01},
++	{0x5503, 0x0f},
++	{0x8000, 0x00},
++	{0x8001, 0x00},
++	{0x8002, 0x00},
++	{0x8003, 0x00},
++	{0x8004, 0x00},
++	{0x8005, 0x00},
++	{0x8006, 0x00},
++	{0x8007, 0x00},
++	{0x8008, 0x00},
++	{0x3638, 0x00},
++	//{0x5040, 0x80},//color bar
++	{0x0100, 0x00},
++#endif
++	{OV4689_REG_END, 0x00},/* END MARKER */
++};
++
++static struct regval_list ov4689_init_regs_2592_1520_30fps_mipi[] = {
++	{0x0103, 0x01},
++	{0x3638, 0x00},
++	{0x0300, 0x00},
++	{0x0302, 0x19}, //0x19
++	{0x0303, 0x00},
++	{0x0304, 0x03}, //0x03
++	{0x030b, 0x00},
++	{0x030d, 0x1e},
++	{0x030e, 0x04},
++	{0x030f, 0x01},
++	{0x0311, 0x00},
++	{0x0312, 0x01},
++	{0x031e, 0x00},
++	{0x3000, 0x20},
++	{0x3002, 0x00},
++	{0x3018, 0x32},
++	{0x3019, 0x0c},
++	{0x3020, 0x93},
++	{0x3021, 0x03},
++	{0x3022, 0x01},
++	{0x3031, 0x0a},
++	{0x303f, 0x0c},
++	{0x3305, 0xf1},
++	{0x3307, 0x04},
++	{0x3309, 0x29},
++	{0x3500, 0x00},
++	{0x3501, 0x60},
++	{0x3502, 0x00},
++	{0x3503, 0x04},
++	{0x3504, 0x00},
++	{0x3505, 0x00},
++	{0x3506, 0x00},
++	{0x3507, 0x00},
++	{0x3508, 0x00},
++	{0x3509, 0x80},
++	{0x350a, 0x00},
++	{0x350b, 0x00},
++	{0x350c, 0x00},
++	{0x350d, 0x00},
++	{0x350e, 0x00},
++	{0x350f, 0x80},
++	{0x3510, 0x00},
++	{0x3511, 0x00},
++	{0x3512, 0x00},
++	{0x3513, 0x00},
++	{0x3514, 0x00},
++	{0x3515, 0x80},
++	{0x3516, 0x00},
++	{0x3517, 0x00},
++	{0x3518, 0x00},
++	{0x3519, 0x00},
++	{0x351a, 0x00},
++	{0x351b, 0x80},
++	{0x351c, 0x00},
++	{0x351d, 0x00},
++	{0x351e, 0x00},
++	{0x351f, 0x00},
++	{0x3520, 0x00},
++	{0x3521, 0x80},
++	{0x3522, 0x08},
++	{0x3524, 0x08},
++	{0x3526, 0x08},
++	{0x3528, 0x08},
++	{0x352a, 0x08},
++	{0x3602, 0x00},
++	{0x3603, 0x40},
++	{0x3604, 0x02},
++	{0x3605, 0x00},
++	{0x3606, 0x00},
++	{0x3607, 0x00},
++	{0x3609, 0x12},
++	{0x360a, 0x40},
++	{0x360c, 0x08},
++	{0x360f, 0xe5},
++	{0x3608, 0x8f},
++	{0x3611, 0x00},
++	{0x3613, 0xf7},
++	{0x3616, 0x58},
++	{0x3619, 0x99},
++	{0x361b, 0x60},
++	{0x361c, 0x7a},
++	{0x361e, 0x79},
++	{0x361f, 0x02},
++	{0x3632, 0x00},
++	{0x3633, 0x10},
++	{0x3634, 0x10},
++	{0x3635, 0x10},
++	{0x3636, 0x15},
++	{0x3646, 0x86},
++	{0x364a, 0x0b},
++	{0x3700, 0x17},
++	{0x3701, 0x22},
++	{0x3703, 0x10},
++	{0x370a, 0x37},
++	{0x3705, 0x00},
++	{0x3706, 0x63},
++	{0x3709, 0x3c},
++	{0x370b, 0x01},
++	{0x370c, 0x30},
++	{0x3710, 0x24},
++	{0x3711, 0x0c},
++	{0x3716, 0x00},
++	{0x3720, 0x28},
++	{0x3729, 0x7b},
++	{0x372a, 0x84},
++	{0x372b, 0xbd},
++	{0x372c, 0xbc},
++	{0x372e, 0x52},
++	{0x373c, 0x0e},
++	{0x373e, 0x33},
++	{0x3743, 0x10},
++	{0x3744, 0x88},
++	{0x3745, 0xc0},
++	{0x374a, 0x43},
++	{0x374c, 0x00},
++	{0x374e, 0x23},
++	{0x3751, 0x7b},
++	{0x3752, 0x84},
++	{0x3753, 0xbd},
++	{0x3754, 0xbc},
++	{0x3756, 0x52},
++	{0x375c, 0x00},
++	{0x3760, 0x00},
++	{0x3761, 0x00},
++	{0x3762, 0x00},
++	{0x3763, 0x00},
++	{0x3764, 0x00},
++	{0x3767, 0x04},
++	{0x3768, 0x04},
++	{0x3769, 0x08},
++	{0x376a, 0x08},
++	{0x376b, 0x20},
++	{0x376c, 0x00},
++	{0x376d, 0x00},
++	{0x376e, 0x00},
++	{0x3773, 0x00},
++	{0x3774, 0x51},
++	{0x3776, 0xbd},
++	{0x3777, 0xbd},
++	{0x3781, 0x18},
++	{0x3783, 0x25},
++	{0x3798, 0x1b},
++	{0x3800, 0x00},
++	{0x3801, 0x38},
++	{0x3802, 0x00},
++	{0x3803, 0x04},
++	{0x3804, 0x0a},
++	{0x3805, 0x67},
++	{0x3806, 0x05},
++	{0x3807, 0xfb},
++	{0x3808, 0x0a},
++	{0x3809, 0x20},
++	{0x380a, 0x05},
++	{0x380b, 0xf0},
++	{0x380c, 0x0A},
++	{0x380d, 0x82},//0x18
++	{0x380e, 0x06},
++	{0x380f, 0xfb},
++	{0x3810, 0x00},
++	{0x3811, 0x08},
++	{0x3812, 0x00},
++	{0x3813, 0x04},
++	{0x3814, 0x01},
++	{0x3815, 0x01},
++	{0x3819, 0x01},
++	{0x3820, 0x00},
++	{0x3821, 0x06},
++	{0x3829, 0x00},
++	{0x382a, 0x01},
++	{0x382b, 0x01},
++	{0x382d, 0x7f},
++	{0x3830, 0x04},
++	{0x3836, 0x01},
++	{0x3837, 0x00},
++	{0x3841, 0x02},
++	{0x3846, 0x08},
++	{0x3847, 0x07},
++	{0x3d85, 0x36},
++	{0x3d8c, 0x71},
++	{0x3d8d, 0xcb},
++	{0x3f0a, 0x00},
++	{0x4000, 0xf1},
++	{0x4001, 0x40},
++	{0x4002, 0x04},
++	{0x4003, 0x14},
++	{0x400e, 0x00},
++	{0x4011, 0x00},
++	{0x401a, 0x00},
++	{0x401b, 0x00},
++	{0x401c, 0x00},
++	{0x401d, 0x00},
++	{0x401f, 0x00},
++	{0x4020, 0x00},
++	{0x4021, 0x10},
++	{0x4022, 0x08},
++	{0x4023, 0xb3},
++	{0x4024, 0x09},
++	{0x4025, 0xe0},
++	{0x4026, 0x09},
++	{0x4027, 0xf0},//
++	{0x4028, 0x00},
++	{0x4029, 0x02},
++	{0x402a, 0x06},
++	{0x402b, 0x04},
++	{0x402c, 0x02},
++	{0x402d, 0x02},
++	{0x402e, 0x0e},
++	{0x402f, 0x04},
++	{0x4302, 0xff},
++	{0x4303, 0xff},
++	{0x4304, 0x00},
++	{0x4305, 0x00},
++	{0x4306, 0x00},
++	{0x4308, 0x02},
++	{0x4500, 0x6c},
++	{0x4501, 0xc4},
++	{0x4502, 0x40},
++	{0x4503, 0x01},
++	{0x4601, 0xA1},//
++	{0x4800, 0x04},
++	{0x4813, 0x08},
++	{0x481f, 0x40},
++	{0x4829, 0x78},
++	{0x4837, 0x10},
++	{0x4b00, 0x2a},
++	{0x4b0d, 0x00},
++	{0x4d00, 0x04},
++	{0x4d01, 0x42},
++	{0x4d02, 0xd1},
++	{0x4d03, 0x93},
++	{0x4d04, 0xf5},
++	{0x4d05, 0xc1},
++	{0x5000, 0xf3},
++	{0x5001, 0x11},
++	{0x5004, 0x00},
++	{0x500a, 0x00},
++	{0x500b, 0x00},
++	{0x5032, 0x00},
++	{0x5040, 0x00},
++	{0x5050, 0x0c},
++	{0x5500, 0x00},
++	{0x5501, 0x10},
++	{0x5502, 0x01},
++	{0x5503, 0x0f},
++	{0x8000, 0x00},
++	{0x8001, 0x00},
++	{0x8002, 0x00},
++	{0x8003, 0x00},
++	{0x8004, 0x00},
++	{0x8005, 0x00},
++	{0x8006, 0x00},
++	{0x8007, 0x00},
++	{0x8008, 0x00},
++	{0x3638, 0x00},
++	{0x0100, 0x00},
++	{OV4689_REG_END, 0x00},/* END MARKER */
++};
++
++/*
++ * the part of driver was fixed.
++ */
++
++static struct regval_list ov4689_stream_on_mipi[] = {
++	{0x0100, 0x01},
++	{OV4689_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list ov4689_stream_off_mipi[] = {
++	{0x0100, 0x00},
++	{OV4689_REG_END, 0x00},	/* END MARKER */
++};
++
++static int ov4689_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret = 0;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ov4689_write(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3] = {(reg>>8)&0xff, reg&0xff, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 3,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ov4689_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != OV4689_REG_END) {
++		if (vals->reg_num == OV4689_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ov4689_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++/*
++ * Write a list of register settings; ff/ff stops the process.
++ */
++static int ov4689_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != OV4689_REG_END) {
++		if (vals->reg_num == OV4689_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ov4689_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int ov4689_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov4689_info *info = to_state(sd);
++
++	if(val) {
++		gpiod_direction_output(info->reset, 1);
++		msleep(10);
++		gpiod_direction_output(info->reset, 0);
++		msleep(10);
++	}
++	return 0;
++}
++
++static int ov4689_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov4689_info *info = to_state(sd);
++
++	if(val) {
++		gpiod_direction_output(info->ircutp, 1);
++		gpiod_direction_output(info->ircutn, 1);
++		msleep(10);
++		gpiod_direction_output(info->ircutp, 0);
++	} else {
++		gpiod_direction_output(info->ircutp, 0);
++		gpiod_direction_output(info->ircutn, 0);
++		msleep(10);
++		gpiod_direction_output(info->ircutp, 1);
++	}
++	return 0;
++}
++
++static int ov4689_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov4689_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = ov4689_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++
++static int ov4689_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++	ret = ov4689_read(sd, 0x300a, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != OV4689_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = ov4689_read(sd, 0x300b, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != OV4689_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	return 0;
++}
++
++
++static struct ov4689_win_size ov4689_win_sizes[] = {
++	{
++		.width		= 1920,
++		.height		= 1080,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++#ifdef CONFIG_OV4689_1080P_120FPS
++		.regs 		= ov4689_init_regs_1920_1080_120fps_mipi,
++#else
++		.regs 		= ov4689_init_regs_1920_1080_30fps_mipi,
++#endif
++	},
++	{
++		.width		= 2048,
++		.height		= 1520,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov4689_init_regs_2048_1520_30fps_mipi,
++	},
++	{
++		.width		= 2592,
++		.height		= 1520,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov4689_init_regs_2592_1520_30fps_mipi,
++	}
++};
++
++#define N_OV4689_FMTS  ARRAY_SIZE(ov4689_win_sizes)
++
++static int ov4689_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad || code->index >= N_OV4689_FMTS)
++		return -EINVAL;
++
++	code->code = ov4689_win_sizes[code->index].mbus_code;
++
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int ov4689_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int ov4689_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct ov4689_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	/* *(unsigned int *)fmt->reserved = &info->win->sensor_info; */
++
++//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int ov4689_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov4689_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov4689_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov4689_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int ov4689_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int ov4689_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov4689_again_lut); i++) {
++		lut = &ov4689_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov4689_again_lut); i++) {
++		lut = &ov4689_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return 0;
++}
++
++static int ov4689_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	char v = 0;
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++	ret += ov4689_read(sd, 0x3509, &v);
++
++	reg_val |= v;
++	ret += ov4689_read(sd, 0x3508, &v);
++	reg_val |= v << 8;
++
++	*value = regval_to_again(reg_val);
++
++	return ret;
++}
++/*set analog gain db value, map value to sensor register.*/
++static int ov4689_s_again(struct v4l2_subdev *sd, int value)
++{
++	struct ov4689_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int ret = 0;
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(value);
++	}
++
++	ret += ov4689_write(sd, 0x3509, (unsigned char)(reg_value & 0xff));
++	ret += ov4689_write(sd, 0x3508, (unsigned char)((reg_value>>8) & 0xff));
++	if (ret < 0)
++		return ret;
++
++	return ret;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int ov4689_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov4689_s_exp(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	ret += ov4689_write(sd, 0x3502, ((unsigned char)(value & 0xf)) << 4);
++	ret += ov4689_write(sd, 0x3501, (unsigned char)((value >> 4) & 0xff));
++	ret += ov4689_write(sd, 0x3500, (unsigned char)((value >> 12) & 0xf));
++
++	return ret;
++}
++
++static int ov4689_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov4689_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return ov4689_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov4689_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int ov4689_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov4689_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return ov4689_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return ov4689_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return ov4689_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return ov4689_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* ov4689_s_gain turns off auto gain */
++			return ov4689_s_gain(sd, info->gain->val);
++		}
++		return ov4689_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return ov4689_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov4689_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return ov4689_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops ov4689_ctrl_ops = {
++	.s_ctrl = ov4689_s_ctrl,
++	.g_volatile_ctrl = ov4689_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ov4689_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = ov4689_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int ov4689_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	ov4689_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int ov4689_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	int ret = 0;
++
++	if (enable) {
++		ret = ov4689_write_array(sd, ov4689_stream_on_mipi);
++		pr_debug("ov4689 stream on\n");
++
++	}
++	else {
++		ret = ov4689_write_array(sd, ov4689_stream_off_mipi);
++		pr_debug("ov4689 stream off\n");
++	}
++	return ret;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops ov4689_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = ov4689_g_register,
++	.s_register = ov4689_s_register,
++#endif
++//	.g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
++//	.try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
++//	.s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
++//	.g_ctrl = v4l2_subdev_g_ctrl,
++//	.s_ctrl = v4l2_subdev_s_ctrl,
++//	.queryctrl = v4l2_subdev_queryctrl,
++//	.querymenu = v4l2_subdev_querymenu,
++};
++
++static int ov4689_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
++		struct v4l2_mbus_config *cfg)
++{
++	/*int dts*/
++	return 0;
++}
++
++static const struct v4l2_subdev_video_ops ov4689_video_ops = {
++	.s_stream = ov4689_s_stream,
++};
++
++static const struct v4l2_subdev_pad_ops ov4689_pad_ops = {
++	//.enum_frame_interval = ov4689_enum_frame_interval,
++	//.num_frame_size = ov4689_enum_frame_size,
++	.enum_mbus_code = ov4689_enum_mbus_code,
++	.set_fmt = ov4689_set_fmt,
++	.get_fmt = ov4689_get_fmt,
++	.get_mbus_config = ov4689_g_mbus_config,
++};
++
++static const struct v4l2_subdev_ops ov4689_ops = {
++	.core = &ov4689_core_ops,
++	.video = &ov4689_video_ops,
++	.pad = &ov4689_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int ov4689_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_subdev *sd;
++	struct ov4689_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	/* Request the reset GPIO deasserted */
++	info->reset = devm_gpiod_get_optional(&client->dev, "reset",
++			GPIOD_OUT_LOW);
++	if (!info->reset)
++		dev_dbg(&client->dev, "reset gpio is not assigned!\n");
++	else if (IS_ERR(info->reset))
++		return PTR_ERR(info->reset);
++
++	info->ircutp = devm_gpiod_get_optional(&client->dev, "ircutp",
++			GPIOD_OUT_LOW);
++	if (!info->ircutp)
++		dev_dbg(&client->dev, "ircutp gpio is not assigned!\n");
++	else if (IS_ERR(info->ircutp))
++		return PTR_ERR(info->ircutp);
++
++	info->ircutn = devm_gpiod_get_optional(&client->dev, "ircutn",
++			GPIOD_OUT_LOW);
++	if (!info->ircutn)
++		dev_dbg(&client->dev, "ircutn gpio is not assigned!\n");
++	else if (IS_ERR(info->ircutn))
++		return PTR_ERR(info->ircutn);
++
++	v4l2_i2c_subdev_init(sd, client, &ov4689_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++	info->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++
++	ov4689_reset(sd, 1);
++#if 1
++	/* Make sure it's an ov4689 */
++	ret = ov4689_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an ov4689 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++
++	/*IRCUT ctl 0:off 1:on*/
++	ov4689_ircut(sd, 0);
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 261773, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1520 - 4, 1, 1000);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++#ifdef CONFIG_OV4689_2048X1520_30FPS
++	info->win = &ov4689_win_sizes[1];
++#else
++	info->win = &ov4689_win_sizes[0];
++#endif
++
++	ov4689_init(sd, 1);
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "ov4689 Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int ov4689_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov4689_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	devm_kfree(&client->dev, info);
++	return 0;
++}
++
++static const struct i2c_device_id ov4689_id[] = {
++	{ "ov4689", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ov4689_id);
++
++static const struct of_device_id ov4689_of_match[] = {
++	{.compatible = "ovti,ov4689", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov2640_of_match);
++
++
++static struct i2c_driver ov4689_driver = {
++	.driver = {
++		.name	= "ov4689",
++		.of_match_table = of_match_ptr(ov4689_of_match),
++	},
++	.probe		= ov4689_probe,
++	.remove		= ov4689_remove,
++	.id_table	= ov4689_id,
++};
++
++module_i2c_driver(ov4689_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for OmniVision ov4689 sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-cim/ov5640.c b/module_drivers/drivers/media/i2c/ingenic-cim/ov5640.c
+new file mode 100644
+index 000000000..856edd0d3
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-cim/ov5640.c
+@@ -0,0 +1,1925 @@
++/*
++ * ov5640 Camera Driver
++ *
++ * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com>
++ *
++ * Based on ov772x, ov9640 drivers and previous non merged implementations.
++ *
++ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright (C) 2006, OmniVision
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/i2c.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/gpio/consumer.h>
++#include <linux/of_gpio.h>
++#include <linux/v4l2-mediabus.h>
++#include <linux/videodev2.h>
++
++#include <media/v4l2-clk.h>
++#include <media/v4l2-subdev.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-image-sizes.h>
++#include <media/v4l2-device.h>
++#include <ingenic_camera.h>
++
++#include <linux/clk.h>
++#include <linux/regulator/consumer.h>
++
++#define REG_CHIP_ID_HIGH		0x300a
++#define REG_CHIP_ID_LOW			0x300b
++#define REG_CHIP_REVISION		0x302a
++#define CHIP_ID_HIGH			0x56
++#define CHIP_ID_LOW			0x40
++
++/* Private v4l2 controls */
++#define V4L2_CID_PRIVATE_BALANCE  (V4L2_CID_PRIVATE_BASE + 0)
++#define V4L2_CID_PRIVATE_EFFECT  (V4L2_CID_PRIVATE_BASE + 1)
++
++/* In flip, the OV5640 does not need additional settings because the ISP block
++ * will auto-detect whether the pixel is in the red line or blue line and make
++ * the necessary adjustments.
++ */
++#define REG_TC_VFLIP			0x3820
++#define REG_TC_MIRROR			0x3821
++#define OV5640_HFLIP			0x1
++#define OV5640_VFLIP			0x2
++#define OV5640_FLIP_VAL			((unsigned char)0x06)
++#define OV5640_FLIP_MASK		((unsigned char)0x06)
++
++ /* whether sensor support high resolution (> vga) preview or not */
++#define SUPPORT_HIGH_RESOLUTION_PRE		1
++
++/*
++ * Struct
++ */
++struct regval_list {
++	u16 reg_num;
++	u16 value;
++};
++
++struct mode_list {
++	u16 index;
++	const struct regval_list *mode_regs;
++};
++
++/* Supported resolutions */
++enum ov5640_width {
++	W_QVGA	= 320,
++	W_VGA	= 640,
++	W_720P	= 1280,
++	W_1080P	= 1920,
++};
++
++enum ov5640_height {
++	H_QVGA	= 240,
++	H_VGA	= 480,
++	H_720P	= 720,
++	H_1080P	= 1080,
++};
++
++struct ov5640_format {
++	u32 code;
++	const struct regval_list *regs;
++};
++
++struct ov5640_win_size {
++	char *name;
++	enum ov5640_width width;
++	enum ov5640_height height;
++	const struct regval_list *regs;
++	unsigned int mbus_code;
++};
++
++struct ov5640_priv {
++	struct v4l2_subdev		subdev;
++	struct v4l2_ctrl_handler	hdl;
++	u32	cfmt_code;
++	struct v4l2_clk			*clk;
++	const struct ov5640_win_size	*win;
++
++	int				model;
++	u16				balance_value;
++	u16				effect_value;
++	u16				flag_vflip:1;
++	u16				flag_hflip:1;
++
++	struct v4l2_subdev_platform_data *sd_pdata;
++	struct gpio_desc *resetb_gpio;
++	struct gpio_desc *pwdn_gpio;
++	struct gpio_desc *vcc_en_gpio;
++
++	int (*power)(struct i2c_client *client, int on);
++	int (*reset)(struct i2c_client *client);
++
++	struct regulator *reg;
++	struct regulator *reg1;
++};
++
++int cam_t_j = 0, cam_t_i = 0;
++unsigned long long cam_t0_buf[10];
++unsigned long long cam_t1_buf[10];
++
++static inline int sensor_i2c_master_send(struct i2c_client *client,
++		const char *buf ,int count)
++{
++	int ret;
++	struct i2c_adapter *adap=client->adapter;
++	struct i2c_msg msg;
++
++	msg.addr = client->addr;
++	msg.flags = client->flags & I2C_M_TEN;
++	msg.len = count;
++	msg.buf = (char *)buf;
++#if 0
++	{
++		if (cam_t_i < 10)
++			cam_t0_buf[cam_t_i] = cpu_clock(smp_processor_id());
++	}
++#endif
++
++	ret = i2c_transfer(adap, &msg, 1);
++
++#if 0
++	{
++		if (cam_t_i < 10) {
++			cam_t1_buf[cam_t_i] = cpu_clock(smp_processor_id());
++			cam_t_i++;
++		}
++		if (cam_t_i == 10) {
++			cam_t_j = cam_t_i;
++			cam_t_i = 11;
++			while(--cam_t_j)
++				printk("cam%d : i2c1_time 0  = %lld, i2c1_time 1"
++						"= %lld, time = %lld\n",
++						cam_t_j,
++						cam_t0_buf[cam_t_j],
++						cam_t1_buf[cam_t_j],
++						cam_t1_buf[cam_t_j]
++						- cam_t0_buf[cam_t_j]);
++		}
++	}
++#endif
++
++	/* If everything went ok (i.e. 1 msg transmitted), return #bytes
++	   transmitted, else error code. */
++	return (ret == 1) ? count : ret;
++}
++
++static inline int sensor_i2c_master_recv(struct i2c_client *client,
++		char *buf ,int count)
++{
++	struct i2c_adapter *adap=client->adapter;
++	struct i2c_msg msg;
++	int ret;
++
++	msg.addr = client->addr;
++	msg.flags = client->flags & I2C_M_TEN;
++	msg.flags |= I2C_M_RD;
++	msg.len = count;
++	msg.buf = buf;
++	ret = i2c_transfer(adap, &msg, 1);
++
++	/* If everything went ok (i.e. 1 msg transmitted), return #bytes
++	   transmitted, else error code. */
++	return (ret == 1) ? count : ret;
++}
++
++static s32 ov5640_read_reg(struct i2c_client *client, u16 reg)
++{
++	int ret;
++	u8 retval;
++	u16 r = cpu_to_be16(reg);
++
++	ret = sensor_i2c_master_send(client,(u8 *)&r,2);
++
++	if (ret < 0)
++		return ret;
++	if (ret != 2)
++		return -EIO;
++
++	ret = sensor_i2c_master_recv(client, &retval, 1);
++	if (ret < 0)
++		return ret;
++	if (ret != 1)
++		return -EIO;
++	return retval;
++
++}
++
++static s32 ov5640_write_reg(struct i2c_client *client, u16 reg, u8 val)
++{
++	unsigned char msg[3];
++	int ret;
++
++
++	reg = cpu_to_be16(reg);
++
++	memcpy(&msg[0], &reg, 2);
++	memcpy(&msg[2], &val, 1);
++
++	ret = sensor_i2c_master_send(client, msg, 3);
++
++	if (ret < 0)
++	{
++		printk("RET<0\n");
++		return ret;
++	}
++	if (ret < 3)
++	{
++		printk("RET<3\n");
++		return -EIO;
++	}
++
++	return 0;
++}
++
++/*
++ * Registers settings
++ */
++
++#define ENDMARKER { 0xff, 0xff }
++
++static const struct regval_list ov5640_init_regs[] = {
++	{0x3103, 0x11},
++	{0x3008, 0x82},	// sw reset
++	{0x3008, 0x42},	// sw powerdown
++	{0x3103, 0x03},
++	{0x3017, 0xff},
++	{0x3018, 0xff},	// i/o control
++	{0x3034, 0x18},
++	{0x3035, 0x11},
++	{0x3036, 0x46},
++	{0x3037, 0x13},
++	{0x3108, 0x01},
++	{0x3630, 0x36},	//??
++	{0x3631, 0x0e},
++	{0x3632, 0xe2},
++	{0x3633, 0x12},
++	{0x3621, 0xe0},
++	{0x3704, 0xa0},	//??
++	{0x3703, 0x5a},
++	{0x3715, 0x78},
++	{0x3717, 0x01},
++	{0x370b, 0x60},
++	{0x3705, 0x1a},
++	{0x3905, 0x02},
++	{0x3906, 0x10},
++	{0x3901, 0x0a},
++	{0x3731, 0x12},
++	{0x3600, 0x08},
++	{0x3601, 0x33},
++	{0x302d, 0x60},
++	{0x3620, 0x52},
++	{0x371b, 0x20},
++	{0x471c, 0x50},
++	{0x3a13, 0x43},
++	{0x3a18, 0x00},
++	{0x3a19, 0xf8},
++	{0x3635, 0x13},
++	{0x3636, 0x03},
++	{0x3634, 0x40},
++	{0x3622, 0x01},
++	{0x3c01, 0x34},
++	{0x3c04, 0x28},
++	{0x3c05, 0x98},
++	{0x3c06, 0x00},
++	{0x3c07, 0x08},
++	{0x3c08, 0x00},
++	{0x3c09, 0x1c},
++	{0x3c0a, 0x9c},
++	{0x3c0b, 0x40},
++	{0x3820, 0x41},
++	{0x3821, 0x07},
++	{0x3814, 0x31},
++	{0x3815, 0x31},
++	{0x3800, 0x00},
++	{0x3801, 0x00},
++	{0x3802, 0x00},
++	{0x3803, 0x04},
++	{0x3804, 0x0a},
++	{0x3805, 0x3f},
++	{0x3806, 0x07},
++	{0x3807, 0x9b},
++	{0x3808, 0x02},
++	{0x3809, 0x80},
++	{0x380a, 0x01},
++	{0x380b, 0xe0},
++	{0x380c, 0x07},
++	{0x380d, 0x68},
++	{0x380e, 0x03},
++	{0x380f, 0xd8},
++	{0x3810, 0x00},
++	{0x3811, 0x10},
++	{0x3812, 0x00},
++	{0x3813, 0x06},
++	{0x3618, 0x00},
++	{0x3612, 0x29},
++	{0x3708, 0x62},
++	{0x3709, 0x52},
++	{0x370c, 0x03},
++	{0x3a02, 0x03},
++	{0x3a03, 0xd8},
++	{0x3a08, 0x01},
++	{0x3a09, 0x27},
++	{0x3a0a, 0x00},
++	{0x3a0b, 0xf6},
++	{0x3a0e, 0x03},
++	{0x3a0d, 0x04},
++	{0x3a14, 0x03},
++	{0x3a15, 0xd8},
++	{0x4000, 0x81},
++	{0x4001, 0x02},
++	{0x4004, 0x02},
++	{0x3000, 0x00},
++	{0x3002, 0x1c},
++	{0x3004, 0xff},
++	{0x3006, 0xc3},
++	{0x300e, 0x58},	//set output interface is DVP
++	{0x302e, 0x00},
++	{0x4300, 0x30},	//YUV422, sequence YUYV
++	{0x4740, 0x00},	//pclk polarity HSYNC, VSYNC, PCLK, 0: active low, 1: active high.
++	{0x501f, 0x00},
++	{0x4713, 0x03},
++	{0x4407, 0x04},
++	{0x440e, 0x00},
++	{0x460b, 0x35},
++	{0x460c, 0x22},
++	{0x3824, 0x02},
++	{0x5000, 0xa7},
++	{0x5001, 0xa3},
++	{0x5180, 0xff},
++	{0x5181, 0xf2},
++	{0x5182, 0x00},
++	{0x5183, 0x14},
++	{0x5184, 0x25},
++	{0x5185, 0x24},
++	{0x5186, 0x09},
++	{0x5187, 0x09},
++	{0x5188, 0x09},
++	{0x5189, 0x75},
++	{0x518a, 0x54},
++	{0x518b, 0xe0},
++	{0x518c, 0xb2},
++	{0x518d, 0x42},
++	{0x518e, 0x3d},
++	{0x518f, 0x56},
++	{0x5190, 0x46},
++	{0x5191, 0xf8},
++	{0x5192, 0x04},
++	{0x5193, 0x70},
++	{0x5194, 0xf0},
++	{0x5195, 0xf0},
++	{0x5196, 0x03},
++	{0x5197, 0x01},
++	{0x5198, 0x04},
++	{0x5199, 0x12},
++	{0x519a, 0x04},
++	{0x519b, 0x00},
++	{0x519c, 0x06},
++	{0x519d, 0x82},
++	{0x519e, 0x38},
++	{0x5381, 0x1e},
++	{0x5382, 0x5b},
++	{0x5383, 0x08},
++	{0x5384, 0x0a},
++	{0x5385, 0x7e},
++	{0x5386, 0x88},
++	{0x5387, 0x7c},
++	{0x5388, 0x6c},
++	{0x5389, 0x10},
++	{0x538a, 0x01},
++	{0x538b, 0x98},
++	{0x5300, 0x08},
++	{0x5301, 0x30},
++	{0x5302, 0x10},
++	{0x5303, 0x00},
++	{0x5304, 0x08},
++	{0x5305, 0x30},
++	{0x5306, 0x08},
++	{0x5307, 0x16},
++	{0x5309, 0x08},
++	{0x530a, 0x30},
++	{0x530b, 0x04},
++	{0x530c, 0x06},
++	{0x5480, 0x01},
++	{0x5481, 0x08},
++	{0x5482, 0x14},
++	{0x5483, 0x28},
++	{0x5484, 0x51},
++	{0x5485, 0x65},
++	{0x5486, 0x71},
++	{0x5487, 0x7d},
++	{0x5488, 0x87},
++	{0x5489, 0x91},
++	{0x548a, 0x9a},
++	{0x548b, 0xaa},
++	{0x548c, 0xb8},
++	{0x548d, 0xcd},
++	{0x548e, 0xdd},
++	{0x548f, 0xea},
++	{0x5490, 0x1d},
++	{0x5580, 0x06},
++	{0x5583, 0x40},
++	{0x5584, 0x10},
++	{0x5589, 0x10},
++	{0x558a, 0x00},
++	{0x558b, 0xf8},
++	{0x5800, 0x23},
++	{0x5801, 0x14},
++	{0x5802, 0x0f},
++	{0x5803, 0x0f},
++	{0x5804, 0x12},
++	{0x5805, 0x26},
++	{0x5806, 0x0c},
++	{0x5807, 0x08},
++	{0x5808, 0x05},
++	{0x5809, 0x05},
++	{0x580a, 0x08},
++	{0x580b, 0x0d},
++	{0x580c, 0x08},
++	{0x580d, 0x03},
++	{0x580e, 0x00},
++	{0x580f, 0x00},
++	{0x5810, 0x03},
++	{0x5811, 0x09},
++	{0x5812, 0x07},
++	{0x5813, 0x03},
++	{0x5814, 0x00},
++	{0x5815, 0x01},
++	{0x5816, 0x03},
++	{0x5817, 0x08},
++	{0x5818, 0x0d},
++	{0x5819, 0x08},
++	{0x581a, 0x05},
++	{0x581b, 0x06},
++	{0x581c, 0x08},
++	{0x581d, 0x0e},
++	{0x581e, 0x29},
++	{0x581f, 0x17},
++	{0x5820, 0x11},
++	{0x5821, 0x11},
++	{0x5822, 0x15},
++	{0x5823, 0x28},
++	{0x5824, 0x46},
++	{0x5825, 0x26},
++	{0x5826, 0x08},
++	{0x5827, 0x26},
++	{0x5828, 0x64},
++	{0x5829, 0x26},
++	{0x582a, 0x24},
++	{0x582b, 0x22},
++	{0x582c, 0x24},
++	{0x582d, 0x24},
++	{0x582e, 0x06},
++	{0x582f, 0x22},
++	{0x5830, 0x40},
++	{0x5831, 0x42},
++	{0x5832, 0x24},
++	{0x5833, 0x26},
++	{0x5834, 0x24},
++	{0x5835, 0x22},
++	{0x5836, 0x22},
++	{0x5837, 0x26},
++	{0x5838, 0x44},
++	{0x5839, 0x24},
++	{0x583a, 0x26},
++	{0x583b, 0x28},
++	{0x583c, 0x42},
++	{0x583d, 0xce},
++	{0x5025, 0x00},
++	{0x3a0f, 0x30},
++	{0x3a10, 0x28},
++	{0x3a1b, 0x30},
++	{0x3a1e, 0x26},
++	{0x3a11, 0x60},
++	{0x3a1f, 0x14},
++	{0x3008, 0x02},
++	{0x3035, 0x21},
++	/* {0x503d, 0x80}, // color bar */
++	{0x4202, 0X0F},
++	ENDMARKER,
++};
++
++static const struct regval_list ov5640_qvga_regs[] = {
++	{0x4202, 0x0f},
++
++	{0x3c07, 0x08},
++	{0x5189, 0x72},
++
++	{0x3503, 0x00},
++	{0x3a00, 0x3c},
++	{0x3a02, 0x09},
++	{0x3a03, 0x3a},
++	{0x3a14, 0x09},
++	{0x3a15, 0x3a},
++
++	{0x5302, 0x3f},
++	{0x5303, 0x10},
++	{0x5306, 0x04},
++	{0x5307, 0x14},
++
++	{0x3820, 0x41},
++	{0x3821, 0x07},
++
++	{0x3800, 0x00},
++	{0x3801, 0x00},
++	{0x3802, 0x00},
++	{0x3803, 0x04},
++	{0x3804, 0x0a},
++	{0x3805, 0x3f},
++	{0x3806, 0x07},
++	{0x3807, 0x9b},
++	{0x3808, 0x01},
++	{0x3809, 0x40},
++	{0x380a, 0x00},
++	{0x380b, 0xf0},
++	{0x3810, 0x00},
++	{0x3811, 0x10},
++	{0x3812, 0x00},
++	{0x3813, 0x06},
++	{0x3814, 0x31},
++	{0x3815, 0x31},
++
++	{0x3034, 0x1a},
++	//{0x3035, 0x11},
++	{0x3035, 0x21},
++
++	{0x3036, 0x46},
++	{0x3037, 0x13},
++
++	{0x380c, 0x07},
++	{0x380d, 0x68},
++	{0x380e, 0x03},
++	{0x380f, 0xd8},
++
++	{0x3a08, 0x01},
++	{0x3a09, 0x27},
++	{0x3a0e, 0x03},
++	{0x3a0a, 0x00},
++	{0x3a0b, 0xf6},
++	{0x3a0d, 0x04},
++
++	{0x3618, 0x00},
++	{0x3612, 0x29},
++	{0x3709, 0x52},
++	{0x370c, 0x03},
++
++	{0x4004, 0x02},
++	{0x3002, 0x1c},
++	{0x3006, 0xc3},
++	{0x3824, 0x02},
++	{0x5001, 0xa3},
++
++	{0x4713, 0x03},
++	{0x4407, 0x04},
++	{0x460b, 0x35},
++	{0x460c, 0x22},
++	{0x4837, 0x22},
++
++	{0x5586, 0x24},
++	{0x5585, 0x10},
++	{0x5587, 0x20},
++	{0x5588, 0x01},
++
++	//{0x4202, 0x00},
++
++	{0x3023, 0x01},
++	{0x3022, 0x04},
++
++	ENDMARKER,
++};
++
++static const struct regval_list ov5640_vga_regs[] = {
++	{0x4202, 0x0f},
++
++	{0x3c07, 0x08},
++	{0x5189, 0x72},
++
++	{0x3503, 0x00},
++	{0x3a00, 0x3c},
++	{0x3a02, 0x09},
++	{0x3a03, 0x3a},
++	{0x3a14, 0x09},
++	{0x3a15, 0x3a},
++
++	{0x5302, 0x3f},
++	{0x5303, 0x10},
++	{0x5306, 0x04},
++	{0x5307, 0x14},
++
++	{0x3820, 0x41},
++	{0x3821, 0x07},
++
++	{0x3800, 0x00},
++	{0x3801, 0x00},
++	{0x3802, 0x00},
++	{0x3803, 0x04},
++	{0x3804, 0x0a},
++	{0x3805, 0x3f},
++	{0x3806, 0x07},
++	{0x3807, 0x9b},
++	{0x3808, 0x02},
++	{0x3809, 0x80},
++	{0x380a, 0x01},
++	{0x380b, 0xe0},
++	{0x3810, 0x00},
++	{0x3811, 0x10},
++	{0x3812, 0x00},
++	{0x3813, 0x06},
++	{0x3814, 0x31},
++	{0x3815, 0x31},
++
++	{0x3034, 0x1a},
++	{0x3035, 0x11},
++	{0x3036, 0x46},
++	{0x3037, 0x13},
++
++	{0x380c, 0x07},
++	{0x380d, 0x68},
++	{0x380e, 0x03},
++	{0x380f, 0xd8},
++
++	{0x3a08, 0x01},
++	{0x3a09, 0x27},
++	{0x3a0e, 0x03},
++	{0x3a0a, 0x00},
++	{0x3a0b, 0xf6},
++	{0x3a0d, 0x04},
++
++	{0x3618, 0x00},
++	{0x3612, 0x29},
++	{0x3709, 0x52},
++	{0x370c, 0x03},
++
++	{0x4004, 0x02},
++	{0x3002, 0x1c},
++	{0x3006, 0xc3},
++	{0x3824, 0x02},
++	{0x5001, 0xa3},
++
++	{0x4713, 0x03},
++	{0x4407, 0x04},
++	{0x460b, 0x35},
++	{0x460c, 0x22},
++	{0x4837, 0x22},
++
++	{0x5586, 0x24},
++	{0x5585, 0x10},
++	{0x5587, 0x20},
++	{0x5588, 0x01},
++
++	//{0x4202, 0x00},
++
++	{0x3023, 0x01},
++	{0x3022, 0x04},
++	ENDMARKER,
++};
++
++static const struct regval_list ov5640_720p_regs[] = {
++	{0x4202, 0x0f},
++
++	{0x3c07, 0x07},
++	{0x5189, 0x72},
++
++	{0x3503, 0x00},
++
++	{0x5302, 0x3f},
++	{0x5303, 0x10},
++	{0x5306, 0x04},
++	{0x5307, 0x14},
++
++	{0x3820, 0x41},
++	{0x3821, 0x07},
++
++	{0x3800, 0x00},
++	{0x3801, 0x00},
++	{0x3802, 0x00},
++	{0x3803, 0xfa},
++	{0x3804, 0x0a},
++	{0x3805, 0x3f},
++	{0x3806, 0x06},
++	{0x3807, 0xa9},
++	{0x3808, 0x05},
++	{0x3809, 0x00},
++	{0x380a, 0x02},
++	{0x380b, 0xd0},
++	{0x3813, 0x04},
++	{0x3814, 0x31},
++	{0x3815, 0x31},
++
++	{0x3034, 0x1a},
++	{0x3035, 0x41}, //30fps
++	{0x3036, 0x69},
++	{0x3037, 0x13},
++
++	{0x380c, 0x07},
++	{0x380d, 0x64},
++	{0x380e, 0x02},
++	{0x380f, 0xe4},
++
++	{0x3a08, 0x00},
++	{0x3a09, 0xde},
++	{0x3a0e, 0x03},
++	{0x3a0a, 0x00},
++	{0x3a0b, 0xb9},
++	{0x3a0d, 0x04},
++
++	{0x3a00, 0x38},
++	{0x3a02, 0x02},
++	{0x3a03, 0xe4},
++	{0x3a14, 0x02},
++	{0x3a15, 0xe4},
++
++	{0x3618, 0x00},
++	{0x3612, 0x29},
++	{0x3709, 0x52},
++	{0x370c, 0x03},
++
++	{0x4004, 0x02},
++	{0x3002, 0x1c},
++	{0x3006, 0xc3},
++	{0x3824, 0x04},
++	{0x5001, 0x83},
++
++	{0x4713, 0x03},
++	{0x4407, 0x04},
++	{0x460b, 0x37},
++	{0x460c, 0x20},
++	{0x4837, 0x16},
++
++	{0x5586, 0x24},
++	{0x5585, 0x10},
++	{0x5587, 0x20},
++	{0x5588, 0x01},
++
++//	{0x4202, 0x00},
++
++	{0x3023, 0x01},
++	{0x3022, 0x04},
++
++	ENDMARKER,
++};
++
++static const struct regval_list ov5640_1080p_regs[] = {
++	{0x4202, 0x0f},
++
++	{0x3c07, 0x07},
++	{0x5189, 0x72},
++
++	{0x3503, 0x00},
++
++	{0x5302, 0x3f},
++	{0x5303, 0x10},
++	{0x5306, 0x04},
++	{0x5307, 0x14},
++
++	{0x3820, 0x40},
++	{0x3821, 0x00},
++
++	{0x3800, 0x01},
++	{0x3801, 0x50},
++	{0x3802, 0x01},
++	{0x3803, 0xb2},
++	{0x3804, 0x08},
++	{0x3805, 0xef},
++	{0x3806, 0x05},
++	{0x3807, 0xf1},
++	{0x3808, 0x07},
++	{0x3809, 0x80},
++	{0x380a, 0x04},
++	{0x380b, 0x38},
++	{0x3813, 0x04},
++	{0x3814, 0x11},
++	{0x3815, 0x11},
++
++	{0x3034, 0x1a},
++	{0x3035, 0x41}, //3.75fps
++	{0x3036, 0x69},
++	{0x3037, 0x13},
++
++	{0x380c, 0x09},
++	{0x380d, 0xc4},
++	{0x380e, 0x04},
++	{0x380f, 0x60},
++
++	{0x3a08, 0x01},
++	{0x3a09, 0x50},
++	{0x3a0e, 0x03},
++	{0x3a0a, 0x01},
++	{0x3a0b, 0x18},
++	{0x3a0d, 0x04},
++
++	{0x3a00, 0x38},
++	{0x3a02, 0x04},
++	{0x3a03, 0x60},
++	{0x3a14, 0x04},
++	{0x3a15, 0x60},
++
++	{0x3618, 0x04},
++	{0x3612, 0x2b},
++	{0x3709, 0x12},
++	{0x370c, 0x00},
++
++	{0x4004, 0x06},
++	{0x3002, 0x1c},
++	{0x3006, 0xc3},
++	{0x3824, 0x04},
++	{0x5001, 0x83},
++
++	{0x4713, 0x02},
++	{0x4407, 0x04},
++	{0x460b, 0x37},
++	{0x460c, 0x20},
++	{0x4837, 0x0a},
++
++	{0x5586, 0x24},
++	{0x5585, 0x10},
++	{0x5587, 0x20},
++	{0x5588, 0x01},
++
++	//{0x4202, 0x00},
++
++	{0x3023, 0x01},
++	{0x3022, 0x04},
++	ENDMARKER,
++};
++
++static const struct regval_list ov5640_wb_auto_regs[] = {
++	{0x3406, 0x00},
++	ENDMARKER,
++};
++
++static const struct regval_list ov5640_wb_incandescence_regs[] = {
++	{0x3212, 0x03},
++
++	{0x3406, 0x01},
++	{0x3400, 0x05},
++	{0x3401, 0x48},
++	{0x3402, 0x04},
++	{0x3403, 0x00},
++	{0x3404, 0x07},
++	{0x3405, 0xcf},
++
++	{0x3212, 0x13},
++	{0x3212, 0xa3},
++	ENDMARKER,
++};
++
++static const struct regval_list ov5640_wb_daylight_regs[] = {
++	{0x3212, 0x03},
++
++	{0x3406, 0x01},
++	{0x3400, 0x06},
++	{0x3401, 0x1c},
++	{0x3402, 0x04},
++	{0x3403, 0x00},
++	{0x3404, 0x04},
++	{0x3405, 0xf3},
++
++	{0x3212, 0x13},
++	{0x3212, 0xa3},
++	ENDMARKER,
++};
++
++static const struct regval_list ov5640_wb_fluorescent_regs[] = {
++	{0x3212, 0x03},
++
++	{0x3406, 0x01},
++	{0x3400, 0x05},
++	{0x3401, 0x8c},
++	{0x3402, 0x04},
++	{0x3403, 0x00},
++	{0x3404, 0x06},
++	{0x3405, 0xe8},
++
++	{0x3212, 0x13},
++	{0x3212, 0xa3},
++	ENDMARKER,
++};
++
++static const struct regval_list ov5640_wb_cloud_regs[] = {
++	{0x3212, 0x03},
++
++	{0x3406, 0x01},
++	{0x3400, 0x06},
++	{0x3401, 0x48},
++	{0x3402, 0x04},
++	{0x3403, 0x00},
++	{0x3404, 0x04},
++	{0x3405, 0xd3},
++
++	{0x3212, 0x13},
++	{0x3212, 0xa3},
++	ENDMARKER,
++};
++
++static const struct mode_list ov5640_balance[] = {
++	{0, ov5640_wb_auto_regs}, {1, ov5640_wb_incandescence_regs},
++	{2, ov5640_wb_daylight_regs}, {3, ov5640_wb_fluorescent_regs},
++	{4, ov5640_wb_cloud_regs},
++};
++
++static const struct regval_list ov5640_effect_normal_regs[] = {
++	{0x3212, 0x03},
++
++	{0x5580, 0x06},
++	{0x5583, 0x40},
++	{0x5584, 0x10},
++
++	{0x3212, 0x13},
++	{0x3212, 0xa3},
++
++	ENDMARKER,
++};
++
++static const struct regval_list ov5640_effect_grayscale_regs[] = {
++	{0x3212, 0x03},
++
++	{0x5580, 0x1e},
++	{0x5583, 0x80},
++	{0x5584, 0x80},
++
++	{0x3212, 0x13},
++	{0x3212, 0xa3},
++
++	ENDMARKER,
++};
++
++static const struct regval_list ov5640_effect_sepia_regs[] = {
++	{0x3212, 0x03},
++
++	{0x5580, 0x1e},
++	{0x5583, 0x40},
++	{0x5584, 0xa0},
++
++	{0x3212, 0x13},
++	{0x3212, 0xa3},
++
++	ENDMARKER,
++};
++
++static const struct regval_list ov5640_effect_colorinv_regs[] = {
++	{0x3212, 0x03},
++
++	{0x5580, 0x46},
++	{0x5583, 0x40},
++	{0x5584, 0x10},
++
++	{0x3212, 0x13},
++	{0x3212, 0xa3},
++
++	ENDMARKER,
++};
++
++static const struct regval_list ov5640_effect_sepiabluel_regs[] = {
++	{0x3212, 0x03},
++
++	{0x5580, 0x1e},
++	{0x5583, 0xa0},
++	{0x5584, 0x40},
++
++	{0x3212, 0x13},
++	{0x3212, 0xa3},
++
++	ENDMARKER,
++};
++
++struct regval_list ov5640_BGR565_Setting[] = {
++	{0x4300, 0x60},//BGR565
++	{0x501f, 0x01},//ISP RGB
++	ENDMARKER,
++};
++
++struct regval_list ov5640_RGB565_Setting[] = {
++	{0x4300, 0x61},//RGB565
++	{0x501f, 0x01},//ISP RGB */
++	ENDMARKER,
++};
++
++struct regval_list ov5640_GRB565_Setting[] = {
++	{0x4300, 0x62},//GRB565
++	{0x501f, 0x01},//ISP RGB
++	ENDMARKER,
++};
++
++struct regval_list ov5640_BRG565_Setting[] = {
++	{0x4300, 0x63},//BRG565
++	{0x501f, 0x01},//ISP RGB
++	ENDMARKER,
++};
++
++struct regval_list ov5640_GBR565_Setting[] = {
++	{0x4300, 0x64},//GBR565
++	{0x501f, 0x01},//ISP RGB
++	ENDMARKER,
++};
++
++struct regval_list ov5640_RBG565_Setting[] = {
++	{0x4300, 0x65},//RBG565
++	{0x501f, 0x01},//ISP RGB
++	ENDMARKER,
++};
++
++
++struct regval_list ov5640_YUV422_YUYV_Setting[] = {
++	{0x4300, 0x30},//YUYV
++	{0x501f, 0x00},//ISP YUV
++	ENDMARKER,
++};
++
++struct regval_list ov5640_YUV422_YVYU_Setting[] = {
++	{0x4300, 0x31},//YVYU
++	{0x501f, 0x00},//ISP YUV
++	ENDMARKER,
++};
++
++struct regval_list ov5640_YUV422_UYVY_Setting[] = {
++	{0x4300, 0x32},//UYVY
++	{0x501f, 0x00},//ISP YUV
++	ENDMARKER,
++};
++
++struct regval_list ov5640_YUV422_VYUY_Setting[] = {
++	{0x4300, 0x33},//VYUY
++	{0x501f, 0x00},//ISP YUV
++	ENDMARKER,
++};
++
++struct regval_list ov5640_SBGGR8_Setting[] = {
++	{0x4300, 0xf8},//raw
++	{0x501f, 0x03},
++	{0x3811, 0x10},
++	{0x3813, 0x04},
++	ENDMARKER,
++};
++struct regval_list ov5640_SGBRG8_Setting[] = {
++	{0x4300, 0xf8},//raw
++	{0x501f, 0x03},
++	{0x3811, 0x11},
++	{0x3813, 0x04},
++	ENDMARKER,
++};
++struct regval_list ov5640_SGRBG8_Setting[] = {
++	{0x4300, 0xf8},//raw
++	{0x501f, 0x03},
++	{0x3811, 0x10},
++	{0x3813, 0x05},
++	ENDMARKER,
++};
++
++struct regval_list ov5640_SRGGB8_Setting[] = {
++	{0x4300, 0xf8},//raw
++	{0x501f, 0x03},
++	{0x3811, 0x11},
++	{0x3813, 0x05},
++	ENDMARKER,
++};
++
++struct regval_list ov5640_Y8_Setting[] = {
++	{0x4300, 0x10},//Y
++	ENDMARKER,
++};
++
++static struct ov5640_format ov5640_fmt[] = {
++	{MEDIA_BUS_FMT_RGB565_2X8_LE, ov5640_RGB565_Setting},
++	{INGENIC_MEDIA_BUS_FMT_RBG565_2X8_LE, ov5640_RBG565_Setting},
++	{MEDIA_BUS_FMT_BGR565_2X8_LE, ov5640_BGR565_Setting},
++	{INGENIC_MEDIA_BUS_FMT_BRG565_2X8_LE, ov5640_BRG565_Setting},
++	{INGENIC_MEDIA_BUS_FMT_GRB565_2X8_LE, ov5640_GRB565_Setting},
++	{INGENIC_MEDIA_BUS_FMT_GBR565_2X8_LE, ov5640_GBR565_Setting},
++	{MEDIA_BUS_FMT_YUYV8_2X8, ov5640_YUV422_YUYV_Setting},
++	{MEDIA_BUS_FMT_YVYU8_2X8, ov5640_YUV422_YVYU_Setting},
++	{MEDIA_BUS_FMT_UYVY8_2X8, ov5640_YUV422_UYVY_Setting},
++	{MEDIA_BUS_FMT_VYUY8_2X8, ov5640_YUV422_VYUY_Setting},
++
++	{MEDIA_BUS_FMT_SBGGR8_1X8, ov5640_SBGGR8_Setting}, /*raw 8*/
++	{MEDIA_BUS_FMT_SGBRG8_1X8, ov5640_SGBRG8_Setting}, /*raw 8*/
++	{MEDIA_BUS_FMT_SGRBG8_1X8, ov5640_SGRBG8_Setting}, /*raw 8*/
++	{MEDIA_BUS_FMT_SRGGB8_1X8, ov5640_SRGGB8_Setting}, /*raw 8*/
++	{MEDIA_BUS_FMT_Y8_1X8, ov5640_Y8_Setting}, /*raw 8*/
++};
++
++#define N_FMT_SIZES (ARRAY_SIZE(ov5640_fmt))
++
++static const struct mode_list ov5640_effect[] = {
++	{0, ov5640_effect_normal_regs}, {1, ov5640_effect_grayscale_regs},
++	{2, ov5640_effect_sepia_regs}, {3, ov5640_effect_colorinv_regs},
++	{4, ov5640_effect_sepiabluel_regs},
++};
++
++#define OV5640_SIZE(n, w, h, r) \
++	{.name = n, .width = w , .height = h, .regs = r}
++
++static struct ov5640_win_size ov5640_supported_win_sizes[] = {
++	OV5640_SIZE("1080P", W_1080P, H_1080P, ov5640_1080p_regs),
++	OV5640_SIZE("720P", W_720P, H_720P, ov5640_720p_regs),
++	OV5640_SIZE("VGA", W_VGA, H_VGA, ov5640_vga_regs),
++	OV5640_SIZE("QVGA", W_QVGA, H_QVGA, ov5640_qvga_regs),
++};
++
++#define N_WIN_SIZES (ARRAY_SIZE(ov5640_supported_win_sizes))
++
++static const struct regval_list ov5640_yuv422_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov5640_rgb565_regs[] = {
++	ENDMARKER,
++};
++
++/*
++ * Supported balance menus
++ */
++static const struct v4l2_querymenu ov5640_balance_menus[] = {
++	{
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 0,
++		.name		= "auto",
++	}, {
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 1,
++		.name		= "incandescent",
++	}, {
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 2,
++		.name		= "fluorescent",
++	},  {
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 3,
++		.name		= "daylight",
++	},  {
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 4,
++		.name		= "cloudy-daylight",
++	},
++
++};
++
++/*
++ * Supported effect menus
++ */
++static const struct v4l2_querymenu ov5640_effect_menus[] = {
++	{
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 0,
++		.name		= "none",
++	}, {
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 1,
++		.name		= "mono",
++	}, {
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 2,
++		.name		= "sepia",
++	},  {
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 3,
++		.name		= "negative",
++	}, {
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 4,
++		.name		= "aqua",
++	},
++};
++/*
++ * General functions
++ */
++static struct ov5640_priv *to_ov5640(const struct i2c_client *client)
++{
++	return container_of(i2c_get_clientdata(client), struct ov5640_priv,
++			    subdev);
++}
++
++static int ov5640_write_array(struct i2c_client *client,
++			      const struct regval_list *vals)
++{
++	int ret;
++
++	while ((vals->reg_num != 0xff) || (vals->value != 0xff)) {
++		ret = ov5640_write_reg(client, vals->reg_num, vals->value);
++		dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x",
++			 vals->reg_num, vals->value);
++
++		if (ret < 0)
++			return ret;
++		vals++;
++	}
++
++	return 0;
++}
++
++static int ov5640_mask_set(struct i2c_client *client,
++			   u16  reg, u16  mask, u16  set)
++{
++	s32 val = ov5640_read_reg(client, reg);
++	if (val < 0)
++		return val;
++
++	val &= ~mask;
++	val |= set & mask;
++
++	dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val);
++
++	return ov5640_write_reg(client, reg, val);
++}
++
++/*
++ * soc_camera_ops functions
++ */
++
++/* OF probe functions */
++static int ov5640_hw_power(struct i2c_client *client, int on)
++{
++	struct ov5640_priv *priv = to_ov5640(client);
++
++	dev_dbg(&client->dev, "%s: %s the camera\n",
++			__func__, on ? "ENABLE" : "DISABLE");
++
++	/* thses gpio should be set according to the active level in dt defines */
++	if(priv->vcc_en_gpio) {
++		gpiod_direction_output(priv->vcc_en_gpio, on);
++	}
++
++	if (priv->pwdn_gpio) {
++		gpiod_direction_output(priv->pwdn_gpio, !on);
++	}
++
++	msleep(10);
++	return 0;
++}
++
++static int ov5640_reset(struct i2c_client *client)
++{
++	struct ov5640_priv *priv = to_ov5640(client);
++
++	if(priv->resetb_gpio) {
++		gpiod_direction_output(priv->resetb_gpio, 1);
++		msleep(10);
++		gpiod_direction_output(priv->resetb_gpio, 0);
++		msleep(10);
++	}
++
++	return 0;
++}
++
++static int ov5640_g_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd =
++		&container_of(ctrl->handler, struct ov5640_priv, hdl)->subdev;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov5640_priv *priv = to_ov5640(client);
++
++	switch (ctrl->id) {
++	case V4L2_CID_VFLIP:
++		ctrl->val = priv->flag_vflip;
++		break;
++	case V4L2_CID_HFLIP:
++		ctrl->val = priv->flag_hflip;
++		break;
++	case V4L2_CID_PRIVATE_BALANCE:
++		ctrl->val = priv->balance_value;
++		break;
++	case V4L2_CID_PRIVATE_EFFECT:
++		ctrl->val = priv->effect_value;
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++static int ov5640_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd =
++		&container_of(ctrl->handler, struct ov5640_priv, hdl)->subdev;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov5640_priv *priv = to_ov5640(client);
++	int ret = 0;
++	int i = 0;
++	u16 value;
++
++	int balance_count = ARRAY_SIZE(ov5640_balance);
++	int effect_count = ARRAY_SIZE(ov5640_effect);
++
++	switch (ctrl->id) {
++	case V4L2_CID_PRIVATE_BALANCE:
++		if(ctrl->val > balance_count)
++			return -EINVAL;
++
++		for(i = 0; i < balance_count; i++) {
++			if(ctrl->val == ov5640_balance[i].index) {
++				ret = ov5640_write_array(client,
++						ov5640_balance[ctrl->val].mode_regs);
++				priv->balance_value = ctrl->val;
++				break;
++			}
++		}
++		break;
++
++	case V4L2_CID_PRIVATE_EFFECT:
++		if(ctrl->val > effect_count)
++			return -EINVAL;
++
++		for(i = 0; i < effect_count; i++) {
++			if(ctrl->val == ov5640_effect[i].index) {
++				ret = ov5640_write_array(client,
++						ov5640_effect[ctrl->val].mode_regs);
++				priv->effect_value = ctrl->val;
++				break;
++			}
++		}
++		break;
++
++	case V4L2_CID_VFLIP:
++		value = ctrl->val ? OV5640_FLIP_VAL : 0x00;
++		priv->flag_vflip = ctrl->val ? 1 : 0;
++		ret = ov5640_mask_set(client, REG_TC_VFLIP, OV5640_FLIP_MASK, value);
++		break;
++
++	case V4L2_CID_HFLIP:
++		value = ctrl->val ? OV5640_FLIP_VAL : 0x00;
++		priv->flag_hflip = ctrl->val ? 1 : 0;
++		ret = ov5640_mask_set(client, REG_TC_MIRROR, OV5640_FLIP_MASK, value);
++		break;
++
++	default:
++		dev_err(&client->dev, "no V4L2 CID: 0x%x ", ctrl->id);
++		return -EINVAL;
++	}
++	return ret;
++}
++
++static const struct v4l2_ctrl_ops ov5640_ctrl_ops = {
++	.s_ctrl = ov5640_s_ctrl,
++	.g_volatile_ctrl = ov5640_g_ctrl,
++};
++
++static int ov5640_s_power(struct v4l2_subdev *sd, int on)
++
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct ov5640_priv *priv = to_ov5640(client);
++
++	if(priv->sd_pdata) {
++		if(on)
++			return regulator_bulk_enable(priv->sd_pdata->num_regulators,priv->sd_pdata->regulators);
++		else
++			return regulator_bulk_disable(priv->sd_pdata->num_regulators,priv->sd_pdata->regulators);
++	} else if(priv->power){
++		return priv->power(client, on);
++	} else {
++		dev_err(&client->dev, "ov5640_s_power failde");
++		return -EINVAL;
++	}
++}
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ov5640_g_register(struct v4l2_subdev *sd,
++			     struct v4l2_dbg_register *reg)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	int ret;
++
++	reg->size = 1;
++	if (reg->reg == 0xff)
++		return -EINVAL;
++
++	ret = ov5640_read_reg(client, reg->reg);
++	if (ret < 0)
++		return ret;
++
++	reg->val = ret;
++
++	return 0;
++}
++
++static int ov5640_s_register(struct v4l2_subdev *sd,
++			     const struct v4l2_dbg_register *reg)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++
++	if (reg->reg == 0xff ||
++	    reg->val == 0xff)
++		return -EINVAL;
++
++	return ov5640_write_reg(client, reg->reg, reg->val);
++}
++#endif
++
++static int ov5640_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++
++	if (!enable ) {
++		dev_dbg(&client->dev, "stream down\n");
++		ov5640_write_reg(client, 0x4202, 0x0f);
++		return 0;
++	}
++
++	dev_dbg(&client->dev, "stream on\n");
++	ov5640_write_reg(client, 0x4202, 0x00);
++
++	return 0;
++}
++
++/* Select the nearest higher resolution for capture */
++static const struct ov5640_win_size *ov5640_select_win(u32 *width, u32 *height)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(ov5640_supported_win_sizes); i++) {
++		if ((*width >= ov5640_supported_win_sizes[i].width) &&
++		    (*height >= ov5640_supported_win_sizes[i].height)) {
++			*width = ov5640_supported_win_sizes[i].width;
++			*height = ov5640_supported_win_sizes[i].height;
++			return &ov5640_supported_win_sizes[i];
++		}
++	}
++
++	return NULL;
++}
++
++static int ov5640_set_params(struct i2c_client *client, u32 *width, u32 *height,
++			     u32 code)
++{
++	struct ov5640_priv       *priv = to_ov5640(client);
++	int ret;
++	int i;
++
++	int bala_index = priv->balance_value;
++	int effe_index = priv->effect_value;
++
++	/* select win */
++	priv->win = ov5640_select_win(width, height);
++
++	/* select format */
++	priv->cfmt_code = 0;
++
++	/* reset hardware */
++	ov5640_reset(client);
++
++	/* initialize the sensor with default data */
++	dev_dbg(&client->dev, "%s: Init default", __func__);
++	ret = ov5640_write_array(client, ov5640_init_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set balance */
++	ret = ov5640_write_array(client, ov5640_balance[bala_index].mode_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set effect */
++	ret = ov5640_write_array(client, ov5640_effect[effe_index].mode_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set size win */
++	ret = ov5640_write_array(client, priv->win->regs);
++	if (ret < 0)
++		goto err;
++
++	for (i = 0; i < N_FMT_SIZES; i++) {
++		if (ov5640_fmt[i].code == code) {
++			ret = ov5640_write_array(client, ov5640_fmt[i].regs);
++			if (ret < 0)
++				goto err;
++		}
++	}
++
++	priv->cfmt_code = code;
++	*width = priv->win->width;
++	*height = priv->win->height;
++
++	return 0;
++
++err:
++	dev_err(&client->dev, "%s: Error %d", __func__, ret);
++	ov5640_reset(client);
++	priv->win = NULL;
++
++	return ret;
++}
++
++static int ov5640_get_selection(struct v4l2_subdev *sd,
++					     struct v4l2_subdev_pad_config *cfg,
++					     struct v4l2_subdev_selection *sel)
++{
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov5640_priv *priv = to_ov5640(client);
++
++	if(!priv->win)
++		return -EINVAL;
++
++	sel->r.top = 0;
++	sel->r.left = 0;
++	sel->r.width = priv->win->width;
++	sel->r.height = priv->win->height;
++
++	return 0;
++}
++
++static int ov5640_get_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov5640_priv *priv = to_ov5640(client);
++
++	if (format->pad)
++		return -EINVAL;
++
++	if (!priv->win) {
++		mf->width = W_VGA,
++		mf->height = H_VGA;
++		priv->win = ov5640_select_win(&mf->width, &mf->height);
++		priv->cfmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
++	}
++
++	mf->width	= priv->win->width;
++	mf->height	= priv->win->height;
++	mf->code	= priv->cfmt_code;
++
++	switch (mf->code) {
++	case MEDIA_BUS_FMT_RGB565_2X8_BE:
++	case MEDIA_BUS_FMT_RGB565_2X8_LE:
++	case INGENIC_MEDIA_BUS_FMT_RBG565_2X8_LE:
++	case MEDIA_BUS_FMT_BGR565_2X8_LE:
++	case INGENIC_MEDIA_BUS_FMT_BRG565_2X8_LE:
++	case INGENIC_MEDIA_BUS_FMT_GBR565_2X8_LE:
++	case INGENIC_MEDIA_BUS_FMT_GRB565_2X8_LE:
++		mf->colorspace = V4L2_COLORSPACE_SRGB;
++		break;
++	case MEDIA_BUS_FMT_YUYV8_2X8:
++	case MEDIA_BUS_FMT_YVYU8_2X8:
++	case MEDIA_BUS_FMT_UYVY8_2X8:
++	case MEDIA_BUS_FMT_VYUY8_2X8:
++	default:
++		mf->colorspace = V4L2_COLORSPACE_JPEG;
++		break;
++	}
++	mf->field	= V4L2_FIELD_NONE;
++
++	return 0;
++}
++
++static int ov5640_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct ov5640_priv *priv = to_ov5640(client);
++
++	if (format->pad)
++		return -EINVAL;
++	/*
++	 * select suitable win, but don't store it
++	 */
++	priv->win = ov5640_select_win(&mf->width, &mf->height);
++	if(!priv->win)
++		return -EINVAL;
++
++	mf->field	= V4L2_FIELD_NONE;
++
++	switch (mf->code) {
++	case MEDIA_BUS_FMT_RGB565_2X8_BE:
++	case MEDIA_BUS_FMT_RGB565_2X8_LE:
++	case INGENIC_MEDIA_BUS_FMT_RBG565_2X8_LE:
++	case MEDIA_BUS_FMT_BGR565_2X8_LE:
++	case INGENIC_MEDIA_BUS_FMT_BRG565_2X8_LE:
++	case INGENIC_MEDIA_BUS_FMT_GBR565_2X8_LE:
++	case INGENIC_MEDIA_BUS_FMT_GRB565_2X8_LE:
++		mf->colorspace = V4L2_COLORSPACE_SRGB;
++		break;
++	case MEDIA_BUS_FMT_YUYV8_2X8:
++	case MEDIA_BUS_FMT_YVYU8_2X8:
++	case MEDIA_BUS_FMT_UYVY8_2X8:
++	case MEDIA_BUS_FMT_VYUY8_2X8:
++		mf->colorspace = V4L2_COLORSPACE_JPEG;
++		break;
++	default:
++		mf->colorspace = V4L2_COLORSPACE_JPEG;
++		break;
++	}
++
++	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
++		ov5640_set_params(client, &mf->width, &mf->height, mf->code);
++	if(cfg)
++		cfg->try_fmt = *mf;
++	return 0;
++}
++
++static int ov5640_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad || code->index >= N_FMT_SIZES)
++		return -EINVAL;
++
++	code->code = ov5640_fmt[code->index].code;
++
++	return 0;
++}
++
++static int ov5640_enum_frame_size(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_frame_size_enum *fse)
++{
++	int i, j;
++	int num_valid = -1;
++	__u32 index = fse->index;
++
++	if(index >= N_WIN_SIZES)
++		return -EINVAL;
++
++	j = N_FMT_SIZES;
++	while(--j)
++		if(fse->code == ov5640_fmt[j].code)
++			break;
++	for (i = 0; i < N_WIN_SIZES; i++) {
++		if (index == ++num_valid) {
++			fse->code = ov5640_fmt[j].code;
++			fse->min_width = ov5640_supported_win_sizes[index].width;
++			fse->max_width = fse->min_width;
++			fse->min_height = ov5640_supported_win_sizes[index].height;
++			fse->max_height = fse->min_height;
++			return 0;
++		}
++	}
++	return -EINVAL;
++}
++
++static int ov5640_hw_reset(struct i2c_client *client)
++{
++	struct ov5640_priv *priv = to_ov5640(client);
++
++	if (priv->resetb_gpio) {
++		/* Active the resetb pin to perform a reset pulse */
++		gpiod_direction_output(priv->resetb_gpio, 1);
++		usleep_range(3000, 5000);
++		gpiod_direction_output(priv->resetb_gpio, 0);
++	}
++
++	return 0;
++}
++
++static int ov5640_video_probe(struct i2c_client *client)
++{
++	unsigned char retval = 0, retval_high = 0, retval_low = 0;
++	struct ov5640_priv *priv = to_ov5640(client);
++	int ret;
++
++	ret = ov5640_s_power(&priv->subdev, 1);
++	if (ret < 0)
++		return ret;
++	/*
++	 * check and show product ID and manufacturer ID
++	 */
++
++	retval = ov5640_write_reg(client, 0x3008, 0x80);
++	if(retval) {
++		dev_err(&client->dev, "i2c write failed!\n");
++		ret = -EINVAL;
++		goto done;
++	}
++
++	retval_high = ov5640_read_reg(client, REG_CHIP_ID_HIGH);
++	if (retval_high != CHIP_ID_HIGH) {
++		dev_err(&client->dev, "read sensor %s chip_id high %x is error\n",
++				client->name, retval_high);
++		ret = -EINVAL;
++		goto done;
++	}
++
++
++	retval_low = ov5640_read_reg(client, REG_CHIP_ID_LOW);
++	if (retval_low != CHIP_ID_LOW) {
++		dev_err(&client->dev, "read sensor %s chip_id low %x is error\n",
++				client->name, retval_low);
++		ret = -EINVAL;
++		goto done;
++	}
++
++	dev_info(&client->dev, "read sensor %s id high:0x%x,low:%x successed!\n",
++			client->name, retval_high, retval_low);
++done:
++	return ret;
++}
++
++static int ov5640_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
++				struct v4l2_mbus_config *cfg)
++{
++	/*int dts*/
++	return 0;
++}
++
++static struct v4l2_subdev_core_ops ov5640_subdev_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register	= ov5640_g_register,
++	.s_register	= ov5640_s_register,
++#endif
++	.s_power	= ov5640_s_power,
++};
++
++static struct v4l2_subdev_video_ops ov5640_subdev_video_ops = {
++	.s_stream	= ov5640_s_stream,
++};
++
++static const struct v4l2_subdev_pad_ops ov5640_subdev_pad_ops = {
++	.enum_mbus_code = ov5640_enum_mbus_code,
++	.enum_frame_size = ov5640_enum_frame_size,
++	.get_fmt	= ov5640_get_fmt,
++	.set_fmt	= ov5640_set_fmt,
++	.get_mbus_config = ov5640_g_mbus_config,
++	.get_selection	= ov5640_get_selection,
++};
++
++static struct v4l2_subdev_ops ov5640_subdev_ops = {
++	.core	= &ov5640_subdev_core_ops,
++	.video	= &ov5640_subdev_video_ops,
++	.pad	= &ov5640_subdev_pad_ops,
++};
++
++static int ov5640_probe_dt(struct i2c_client *client,
++		struct ov5640_priv *priv)
++{
++
++	struct v4l2_subdev_platform_data *sd_pdata = priv->sd_pdata;
++	struct device_node *np = client->dev.of_node;
++	int supplies = 0, index = 0;
++
++	supplies = of_property_count_strings(np, "supplies-name");
++	if(supplies > 0) {
++		sd_pdata = devm_kzalloc(&client->dev, sizeof(struct v4l2_subdev_platform_data), GFP_KERNEL);
++		sd_pdata->num_regulators = supplies;
++		sd_pdata->regulators = devm_kzalloc(&client->dev, supplies * sizeof(struct regulator_bulk_data), GFP_KERNEL);
++		if(!sd_pdata->regulators) {
++			dev_err(&client->dev, "Failed to allocate regulators.!\n");
++			devm_kfree(&client->dev,sd_pdata);
++			return -ENOMEM;
++		}
++
++		for(index = 0; index < sd_pdata->num_regulators; index ++) {
++			of_property_read_string_index(np, "supplies-name", index,
++					&(sd_pdata->regulators[index].supply));
++
++			dev_dbg(&client->dev, "sd_pdata->regulators[%d].supply: %s\n",
++					index, sd_pdata->regulators[index].supply);
++		}
++
++		devm_regulator_bulk_get(&client->dev, sd_pdata->num_regulators, sd_pdata->regulators);
++	} else {
++		/* Request the reset GPIO deasserted */
++		priv->resetb_gpio = devm_gpiod_get_optional(&client->dev, "resetb",
++				GPIOD_OUT_LOW);
++		if (!priv->resetb_gpio)
++			dev_dbg(&client->dev, "resetb gpio is not assigned!\n");
++		else if (IS_ERR(priv->resetb_gpio))
++			return PTR_ERR(priv->resetb_gpio);
++
++		/* Request the power down GPIO asserted */
++		priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn",
++				GPIOD_OUT_HIGH);
++		if (!priv->pwdn_gpio)
++			dev_dbg(&client->dev, "pwdn gpio is not assigned!\n");
++		else if (IS_ERR(priv->pwdn_gpio))
++			return PTR_ERR(priv->pwdn_gpio);
++
++		/* Request the power down GPIO asserted */
++		priv->vcc_en_gpio = devm_gpiod_get_optional(&client->dev, "vcc-en",
++				GPIOD_OUT_HIGH);
++		if (!priv->vcc_en_gpio)
++			dev_dbg(&client->dev, "vcc_en gpio is not assigned!\n");
++		else if (IS_ERR(priv->vcc_en_gpio))
++			return PTR_ERR(priv->vcc_en_gpio);
++
++		/* Initialize the soc_camera_subdev_desc */
++		priv->power = ov5640_hw_power;
++		priv->reset = ov5640_hw_reset; /* TODO */
++	}
++	return 0;
++}
++
++#include <linux/regulator/consumer.h>
++/*
++ * i2c_driver functions
++ */
++static int ov5640_probe(struct i2c_client *client,
++			const struct i2c_device_id *did)
++{
++	struct ov5640_priv	*priv;
++	struct i2c_adapter	*adapter = to_i2c_adapter(client->dev.parent);
++	int ret;
++
++	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA)) {
++		dev_err(&adapter->dev,
++			"OV5640: I2C-Adapter doesn't support SMBUS\n");
++		return -EIO;
++	}
++
++	priv = devm_kzalloc(&client->dev, sizeof(struct ov5640_priv), GFP_KERNEL);
++	if (!priv) {
++		dev_err(&adapter->dev,
++			"Failed to allocate memory for private data!\n");
++		return -ENOMEM;
++	}
++
++	priv->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(priv->clk))
++		return -EPROBE_DEFER;
++
++	v4l2_clk_set_rate(priv->clk, 25000000);
++
++	ret = ov5640_probe_dt(client, priv);
++	if (ret)
++		goto err_probe_dt;
++
++	v4l2_i2c_subdev_init(&priv->subdev, client, &ov5640_subdev_ops);
++
++	/* add handler */
++	v4l2_ctrl_handler_init(&priv->hdl, 2);
++	v4l2_ctrl_new_std(&priv->hdl, &ov5640_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&priv->hdl, &ov5640_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	priv->subdev.ctrl_handler = &priv->hdl;
++	if (priv->hdl.error) {
++		ret = priv->hdl.error;
++		goto err_hdl;
++	}
++
++	ret = ov5640_video_probe(client);
++	if (ret < 0)
++		goto err_detect;
++
++	ret = v4l2_ctrl_handler_setup(&priv->hdl);
++
++	ret = v4l2_async_register_subdev(&priv->subdev);
++	if (ret < 0)
++		goto err_async_register_subdev;
++
++	dev_info(&adapter->dev, "OV5640 Probed\n");
++
++	return 0;
++
++err_async_register_subdev:
++err_detect:
++	v4l2_ctrl_handler_free(&priv->hdl);
++err_hdl:
++	v4l2_device_unregister_subdev(&priv->subdev);
++err_probe_dt:
++	v4l2_clk_put(priv->clk);
++	devm_kfree(&client->dev, priv);
++	return ret;
++}
++
++static int ov5640_remove(struct i2c_client *client)
++{
++	struct ov5640_priv       *priv = to_ov5640(client);
++
++	v4l2_async_unregister_subdev(&priv->subdev);
++	v4l2_clk_put(priv->clk);
++	v4l2_device_unregister_subdev(&priv->subdev);
++	v4l2_ctrl_handler_free(&priv->hdl);
++	devm_kfree(&client->dev, priv);
++	return 0;
++}
++
++static const struct i2c_device_id ov5640_id[] = {
++	{ "ov5640", 0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ov5640_id);
++
++static const struct of_device_id ov5640_of_match[] = {
++	{.compatible = "ovti,ov5640", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov5640_of_match);
++
++static struct i2c_driver ov5640_i2c_driver = {
++	.driver = {
++		.name = "ov5640",
++		.of_match_table = of_match_ptr(ov5640_of_match),
++	},
++	.probe    = ov5640_probe,
++	.remove   = ov5640_remove,
++	.id_table = ov5640_id,
++};
++
++module_i2c_driver(ov5640_i2c_driver);
++
++MODULE_DESCRIPTION("SoC Camera driver for Omni Vision 5640 sensor");
++MODULE_AUTHOR("Alberto Panizzo");
++MODULE_LICENSE("GPL v2");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-cim/ov5645.c b/module_drivers/drivers/media/i2c/ingenic-cim/ov5645.c
+new file mode 100644
+index 000000000..84c43f3db
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-cim/ov5645.c
+@@ -0,0 +1,1629 @@
++/*
++ * ov5645 Camera Driver
++ *
++ * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com>
++ *
++ * Based on ov772x, ov9640 drivers and previous non merged implementations.
++ *
++ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright (C) 2006, OmniVision
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/i2c.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/gpio/consumer.h>
++#include <linux/of_gpio.h>
++#include <linux/v4l2-mediabus.h>
++#include <linux/videodev2.h>
++
++#include <media/v4l2-clk.h>
++#include <media/v4l2-subdev.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-image-sizes.h>
++#include <media/v4l2-device.h>
++#include <ingenic_camera.h>
++
++#include <linux/clk.h>
++#include <linux/regulator/consumer.h>
++
++#define REG_CHIP_ID_HIGH	0x300a
++#define REG_CHIP_ID_LOW		0x300b
++#define CHIP_ID_HIGH		0x56
++#define CHIP_ID_LOW		0x45
++
++#define  OV5645_DEFAULT_WIDTH    640
++#define  OV5645_DEFAULT_HEIGHT   480
++
++/* Private v4l2 controls */
++#define V4L2_CID_PRIVATE_BALANCE  (V4L2_CID_PRIVATE_BASE + 0)
++#define V4L2_CID_PRIVATE_EFFECT  (V4L2_CID_PRIVATE_BASE + 1)
++
++#define REG_TC_VFLIP			0x3820
++#define REG_TC_MIRROR			0x3821
++#define OV5645_FLIP_VAL			((unsigned char)0x04)
++#define OV5645_FLIP_MASK		((unsigned char)0x04)
++
++/* whether sensor support high resolution (> vga) preview or not */
++#define SUPPORT_HIGH_RESOLUTION_PRE		1
++
++/*
++ * Struct
++ */
++struct regval_list {
++	u16 reg_num;
++	u16 value;
++};
++
++struct mode_list {
++	u16 index;
++	const struct regval_list *mode_regs;
++};
++
++/* Supported resolutions */
++enum ov5645_width {
++	W_VGA	= OV5645_DEFAULT_WIDTH,
++	W_720P	= 1280,
++	W_1080P	= 1920,
++};
++
++enum ov5645_height {
++	H_VGA	= OV5645_DEFAULT_HEIGHT,
++	H_720P	= 720,
++	H_1080P	= 1080,
++};
++
++struct ov5645_format {
++	u32 code;
++	const struct regval_list *regs;
++};
++
++struct ov5645_win_size {
++	char *name;
++	enum ov5645_width width;
++	enum ov5645_height height;
++	const struct regval_list *regs;
++};
++
++struct ov5645_gpio {
++	int pin;
++	int active_level;
++};
++
++struct ov5645_priv {
++	struct v4l2_subdev		subdev;
++	struct v4l2_ctrl_handler	hdl;
++	u32	cfmt_code;
++	struct v4l2_clk			*clk;
++	const struct ov5645_win_size	*win;
++
++	int				model;
++	u16				balance_value;
++	u16				effect_value;
++	u16				flag_vflip:1;
++	u16				flag_hflip:1;
++
++	struct v4l2_subdev_platform_data *sd_pdata;
++	struct gpio_desc *resetb_gpio;
++	struct gpio_desc *pwdn_gpio;
++	struct gpio_desc *vcc_en_gpio;
++
++	int (*power)(struct i2c_client *client, int on);
++	int (*reset)(struct i2c_client *client);
++
++	struct regulator *reg;
++	struct regulator *reg1;
++};
++
++static inline int sensor_i2c_master_send(struct i2c_client *client,
++		const char *buf ,int count)
++{
++	int ret;
++	struct i2c_adapter *adap=client->adapter;
++	struct i2c_msg msg;
++
++	msg.addr = client->addr;
++	msg.flags = client->flags & I2C_M_TEN;
++	msg.len = count;
++	msg.buf = (char *)buf;
++
++	ret = i2c_transfer(adap, &msg, 1);
++
++	return (ret == 1) ? count : ret;
++}
++
++static inline int sensor_i2c_master_recv(struct i2c_client *client,
++		char *buf ,int count)
++{
++	struct i2c_adapter *adap=client->adapter;
++	struct i2c_msg msg;
++	int ret;
++
++	msg.addr = client->addr;
++	msg.flags = client->flags & I2C_M_TEN;
++	msg.flags |= I2C_M_RD;
++	msg.len = count;
++	msg.buf = buf;
++	ret = i2c_transfer(adap, &msg, 1);
++
++	return (ret == 1) ? count : ret;
++}
++
++
++unsigned char ov5645_read_reg(struct i2c_client *client, u16 reg)
++{
++	int ret;
++	unsigned char retval;
++	unsigned short r = cpu_to_be16(reg);
++
++	ret = sensor_i2c_master_send(client,(u8 *)&r,2);
++
++	if (ret < 0)
++		return ret;
++	if (ret != 2)
++		return -EIO;
++
++	ret = sensor_i2c_master_recv(client, &retval, 1);
++	if (ret < 0)
++		return ret;
++	if (ret != 1)
++		return -EIO;
++	return retval;
++}
++
++int ov5645_write_reg(struct i2c_client *client, u16 reg, u8 val)
++{
++	unsigned char msg[3];
++	int ret;
++
++	reg = cpu_to_be16(reg);
++
++	memcpy(&msg[0], &reg, 2);
++	memcpy(&msg[2], &val, 1);
++
++	ret = sensor_i2c_master_send(client, msg, 3);
++
++	if (ret < 0)
++	{
++		printk("RET<0\n");
++		return ret;
++	}
++	if (ret < 3)
++	{
++		printk("RET<3\n");
++		return -EIO;
++	}
++
++	return 0;
++}
++
++/*
++ * Registers settings
++ */
++
++#define ENDMARKER { 0xffff, 0x00 }
++#define OV5645_REG_DELAY	0xfffe
++
++static const struct regval_list ov5645_init_regs[] = {
++	{0x3103, 0x11}, // software standby
++	{0x3008, 0x82}, // software reset
++	//delay(5ms)
++	{OV5645_REG_DELAY, 3},
++	{0x4202, 0x0f}, // analog control
++	{0x4202, 0x0f}, // analog control
++
++	{0x3008, 0x42},
++	{0x3103, 0x03},
++	{0x3503, 0x07},
++	{0x3002, 0x1c},
++	{0x3006, 0xc3},
++	{0x300e, 0x45},
++	{0x3017, 0x40},
++	{0x3018, 0x00},
++	{0x302e, 0x0b},
++	{0x3037, 0x13},
++	{0x3108, 0x01},
++	{0x3611, 0x06},
++	{0x3612, 0xab},
++	{0x3614, 0x50},
++	{0x3618, 0x00},
++	{0x3034, 0x18},
++	{0x3035, 0x21},
++	{0x3036, 0x70},
++	{0x3500, 0x00},
++	{0x3501, 0x01},
++	{0x3502, 0x00},
++	{0x350a, 0x00},
++	{0x350b, 0x3f},
++	{0x3600, 0x09},
++	{0x3601, 0x43},
++	{0x3620, 0x33},
++	{0x3621, 0xe0},
++	{0x3622, 0x01},
++	{0x3630, 0x2d},
++	{0x3631, 0x00},
++	{0x3632, 0x32},
++	{0x3633, 0x52},
++	{0x3634, 0x70},
++	{0x3635, 0x13},
++	{0x3636, 0x03},
++	{0x3702, 0x6e},
++	{0x3703, 0x52},
++	{0x3704, 0xa0},
++	{0x3705, 0x33},
++	{0x3708, 0x66},
++	{0x3709, 0x12},
++	{0x370b, 0x61},
++	{0x370c, 0xc3},
++	{0x370f, 0x10},
++	{0x3715, 0x08},
++	{0x3717, 0x01},
++	{0x371b, 0x20},
++	{0x3731, 0x22},
++	{0x3739, 0x70},
++	{0x3901, 0x0a},
++	{0x3905, 0x02},
++	{0x3906, 0x10},
++	{0x3719, 0x86},
++	{0x3800, 0x00},
++	{0x3801, 0x00},
++	{0x3802, 0x00},
++	{0x3803, 0x06},
++	{0x3804, 0x0a},
++	{0x3805, 0x3f},
++	{0x3806, 0x07},
++	{0x3807, 0x9d},
++	{0x3808, 0x05},
++	{0x3809, 0x00},
++	{0x380a, 0x03},
++	{0x380b, 0xc0},
++	{0x380c, 0x07},
++	{0x380d, 0x68},
++	{0x380e, 0x03},
++	{0x380f, 0xd8},
++	{0x3810, 0x00},
++	{0x3811, 0x10},
++	{0x3812, 0x00},
++	{0x3813, 0x06},
++	{0x3814, 0x31},
++	{0x3815, 0x31},
++	{0x3820, 0x47},
++	{0x3821, 0x07},
++	{0x3824, 0x01},
++	{0x3826, 0x03},
++	{0x3828, 0x08},
++	{0x3a02, 0x03},
++	{0x3a03, 0xd8},
++	{0x3a08, 0x01},
++	{0x3a09, 0xf8},
++	{0x3a0a, 0x01},
++	{0x3a0b, 0xa4},
++	{0x3a0e, 0x02},
++	{0x3a0d, 0x02},
++	{0x3a14, 0x03}, // 50Hz max exposure = 984
++	{0x3a15, 0xd8}, // 50Hz max exposure
++	{0x3a18, 0x01}, // gain ceiling = 31.5x
++	{0x3a19, 0xf8}, // gain ceiling
++	// 50/0xauto, 0xde,tect
++	{0x3c01, 0x34},
++	{0x3c04, 0x28},
++	{0x3c05, 0x98},
++	{0x3c07, 0x07},
++	{0x3c09, 0xc2},
++	{0x3c0a, 0x9c},
++	{0x3c0b, 0x40},
++	{0x3c01, 0x34},
++	{0x4001, 0x02},
++	{0x4004, 0x02},
++	{0x4005, 0x18},
++	{0x4300, 0x32}, /* YUYV */
++	{0x4514, 0x00},
++	{0x4520, 0xb0},
++	{0x460b, 0x37},
++	{0x460c, 0x20},
++	// MIPI timing
++	{0x4818, 0x01},
++	{0x481d, 0xf0},
++	{0x481f, 0x50},
++	{0x4823, 0x70},
++	{0x4831, 0x14},
++	{0x4837, 0x10},
++	// BLC start line
++	// B0xline, 0xnu,mber
++	// BLC update by gain change
++	// YUV 422, YUYV
++	// global timing
++	{0x5000, 0xa7}, // Lenc on, raw gamma on, BPC on, WPC on, color interpolation on
++	{0x5001, 0x83}, // SDE on, scale off, UV adjust off, color matrix on, AWB on
++	{0x501d, 0x00},
++	{0x501f, 0x00}, // select ISP YUV 422
++	{0x503d, 0x00},
++	{0x505c, 0x30},
++	// AWB control
++	{0x5181, 0x59},
++	{0x5183, 0x00},
++	{0x5191, 0xf0},
++	{0x5192, 0x03},
++	// AVG control
++	{0x5684, 0x10},
++	{0x5685, 0xa0},
++	{0x5686, 0x0c},
++	{0x5687, 0x78},
++	{0x5a00, 0x08},
++	{0x5a21, 0x00},
++	{0x5a24, 0x00},
++	{0x3008, 0x02}, // wake 0xfrom, 0xso,ftware standby
++	{0x3503, 0x00}, // AGC auto, AEC auto
++	// AWB control
++	{0x5180, 0xff},
++	{0x5181, 0xf2},
++	{0x5182, 0x00},
++	{0x5183, 0x14},
++	{0x5184, 0x25},
++	{0x5185, 0x24},
++	{0x5186, 0x09},
++	{0x5187, 0x09},
++	{0x5188, 0x0a},
++	{0x5189, 0x75},
++	{0x518a, 0x52},
++	{0x518b, 0xea},
++	{0x518c, 0xa8},
++	{0x518d, 0x42},
++	{0x518e, 0x38},
++	{0x518f, 0x56},
++	{0x5190, 0x42},
++	{0x5191, 0xf8},
++	{0x5192, 0x04},
++	{0x5193, 0x70},
++	{0x5194, 0xf0},
++	{0x5195, 0xf0},
++	{0x5196, 0x03},
++	{0x5197, 0x01},
++	{0x5198, 0x04},
++	{0x5199, 0x12},
++	{0x519a, 0x04},
++	{0x519b, 0x00},
++	{0x519c, 0x06},
++	{0x519d, 0x82},
++	{0x519e, 0x38},
++	// matrix
++	{0x5381, 0x1e},
++	{0x5382, 0x5b},
++	{0x5383, 0x08},
++	{0x5384, 0x0b},
++	{0x5385, 0x84},
++	{0x5386, 0x8f},
++	{0x5387, 0x82},
++	{0x5388, 0x71},
++	{0x5389, 0x11},
++	{0x538a, 0x01},
++	{0x538b, 0x98},
++	// CIP
++	{0x5300, 0x08},
++	{0x5301, 0x30},
++	{0x5302, 0x10},
++	{0x5303, 0x00},
++	{0x5304, 0x08},
++	{0x5305, 0x30},
++	{0x5306, 0x08},
++	{0x5307, 0x16},
++	{0x5309, 0x08},
++	{0x530a, 0x30},
++	{0x530b, 0x04},
++	{0x530c, 0x06},
++	// Gamma
++	{0x5480, 0x01},
++	{0x5481, 0x0e},
++	{0x5482, 0x18},
++	{0x5483, 0x2b},
++	{0x5484, 0x52},
++	{0x5485, 0x65},
++	{0x5486, 0x71},
++	{0x5487, 0x7d},
++	{0x5488, 0x87},
++	{0x5489, 0x91},
++	{0x548a, 0x9a},
++	{0x548b, 0xaa},
++	{0x548c, 0xb8},
++	{0x548d, 0xcd},
++	{0x548e, 0xdd},
++	{0x548f, 0xea},
++	{0x5490, 0x1d},
++	{0x5580, 0x06},
++	{0x5583, 0x40},
++	{0x5584, 0x30},
++	{0x5589, 0x10},
++	{0x558a, 0x00},
++	{0x558b, 0xf8},
++	// LENC
++	{0x5800, 0x3f},
++	{0x5801, 0x16},
++	{0x5802, 0x0e},
++	{0x5803, 0x0d},
++	{0x5804, 0x17},
++	{0x5805, 0x3f},
++	{0x5806, 0x0b},
++	{0x5807, 0x06},
++	{0x5808, 0x04},
++	{0x5809, 0x04},
++	{0x580a, 0x06},
++	{0x580b, 0x0b},
++	{0x580c, 0x09},
++	{0x580d, 0x03},
++	{0x580e, 0x00},
++	{0x580f, 0x00},
++	{0x5810, 0x03},
++	{0x5811, 0x08},
++	{0x5812, 0x0a},
++	{0x5813, 0x03},
++	{0x5814, 0x00},
++	{0x5815, 0x00},
++	{0x5816, 0x04},
++	{0x5817, 0x09},
++	{0x5818, 0x0f},
++	{0x5819, 0x08},
++	{0x581a, 0x06},
++	{0x581b, 0x06},
++	{0x581c, 0x08},
++	{0x581d, 0x0c},
++	{0x581e, 0x3f},
++	{0x581f, 0x1e},
++	{0x5820, 0x12},
++	{0x5821, 0x13},
++	{0x5822, 0x21},
++	{0x5823, 0x3f},
++	{0x5824, 0x68},
++	{0x5825, 0x28},
++	{0x5826, 0x2c},
++	{0x5827, 0x28},
++	{0x5828, 0x08},
++	{0x5829, 0x48},
++	{0x582a, 0x64},
++	{0x582b, 0x62},
++	{0x582c, 0x64},
++	{0x582d, 0x28},
++	{0x582e, 0x46},
++	{0x582f, 0x62},
++	{0x5830, 0x60},
++	{0x5831, 0x62},
++	{0x5832, 0x26},
++	{0x5833, 0x48},
++	{0x5834, 0x66},
++	{0x5835, 0x44},
++	{0x5836, 0x64},
++	{0x5837, 0x28},
++	{0x5838, 0x66},
++	{0x5839, 0x48},
++	{0x583a, 0x2c},
++	{0x583b, 0x28},
++	{0x583c, 0x26},
++	{0x583d, 0xae},
++	{0x5025, 0x00}, // AEC in H
++	{0x3a0f, 0x38}, // AEC in L
++	{0x3a10, 0x30}, // AEC out H
++	{0x3a1b, 0x38}, // AEC out L
++	{0x3a1e, 0x30}, // control zone H
++	{0x3a11, 0x70}, // control zone L
++	{0x3a1f, 0x18}, // wake up from standby
++	{0x3008, 0x02},
++	// DPC Setting //
++	{0x5780, 0xfc}, // default value
++	{0x5781, 0x13}, // default value
++	{0x5782, 0x03}, // default 8
++	{0x5786, 0x20}, // default 10 -- add
++	{0x5787, 0x40}, // default 10
++	{0x5788, 0x08},
++	// white pixel threshold
++	{0x5789, 0x08}, // 1x
++	{0x578a, 0x02}, // 8x – set in 5783
++	{0x578b, 0x01}, // 12x – set in 5784
++	{0x578c, 0x01}, // 128x
++	// black pixel threshold
++	{0x578d, 0x0c}, // 1x
++	{0x578e, 0x02}, // 8x – set in 5783
++	{0x578f, 0x01}, // 12x – set in 5784
++	ENDMARKER,
++};
++
++static const struct regval_list ov5645_wb_auto_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov5645_wb_incandescence_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov5645_wb_daylight_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov5645_wb_fluorescent_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov5645_wb_cloud_regs[] = {
++	ENDMARKER,
++};
++
++static const struct mode_list ov5645_balance[] = {
++	{0, ov5645_wb_auto_regs}, {1, ov5645_wb_incandescence_regs},
++	{2, ov5645_wb_daylight_regs}, {3, ov5645_wb_fluorescent_regs},
++	{4, ov5645_wb_cloud_regs},
++};
++
++
++static const struct regval_list ov5645_effect_normal_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov5645_effect_grayscale_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov5645_effect_sepia_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov5645_effect_colorinv_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov5645_effect_sepiabluel_regs[] = {
++	ENDMARKER,
++};
++
++static const struct mode_list ov5645_effect[] = {
++	{0, ov5645_effect_normal_regs}, {1, ov5645_effect_grayscale_regs},
++	{2, ov5645_effect_sepia_regs}, {3, ov5645_effect_colorinv_regs},
++	{4, ov5645_effect_sepiabluel_regs},
++};
++
++static const struct regval_list ov5645_vga_regs[] = {
++	//Sysclk = 42Mhz, MIPI 2 lane 168MBps
++	//0x3612, 0xa9,
++	{0x3618, 0x00},
++	{0x3035, 0x21},
++	{0x3036, 0x54},
++	{0x3600, 0x09},
++	{0x3601, 0x43},
++	{0x3708, 0x66},
++	{0x370c, 0xc3},
++	{0x3803, 0xfa},// VS L
++	{0x3806, 0x06},// VH = 1705
++	{0x3807, 0xa9},// VH
++	{0x3808, 0x02},// DVPHO = 640
++	{0x3809, 0x80},// DVPHO
++	{0x380a, 0x01},// DVPVO = 480
++	{0x380b, 0xe0},// DVPVO
++	{0x380c, 0x07},// HTS = 1892
++	{0x380d, 0x64},// HTS
++	{0x380e, 0x02},// VTS = 740
++	{0x380f, 0xe4},// VTS
++	{0x3814, 0x31},// X INC
++	{0x3815, 0x31},// X INC
++	{0x3820, 0x41},// flip off, V bin on
++	{0x3821, 0x07},// mirror on, H bin on
++	{0x4514, 0x00},
++
++	{0x3a02, 0x02},// night mode ceiling = 740
++	{0x3a03, 0xe4},// night mode ceiling
++	{0x3a08, 0x00},// B50 = 222
++	{0x3a09, 0xde},// B50
++	{0x3a0a, 0x00},// B60 = 185
++	{0x3a0b, 0xb9},// B60
++	{0x3a0e, 0x03},// max 50
++	{0x3a0d, 0x04},// max 60
++	{0x3a14, 0x02},//max 50hz exposure = 3/100
++	{0x3a15, 0x9a},// max 50hz exposure
++	{0x3a18, 0x01},// max gain = 31.5x
++	{0x3a19, 0xf8},// max gain
++	{0x4004, 0x02},// BLC line number
++	{0x4005, 0x18},// BLC update by gain change
++	{0x4837, 0x16},// MIPI global timing
++	{0x3503, 0x00},// AGC/AEC on
++
++	{0x4300, 0x30},//YUYV
++	{0x501f, 0x00},//ISP YUV
++//	{0x503d ,0x80},
++
++	ENDMARKER,
++};
++
++static const struct regval_list ov5645_720p_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov5645_1080p_regs[] = {
++	{0x3618 ,0x04},
++	{0x3035 ,0x61},
++	{0x3036 ,0x30},
++	{0x3600 ,0x08},
++	{0x3601 ,0x33},
++	{0x3708 ,0x63},
++	{0x370c ,0xc0},
++	{0x3800 ,0x01},
++	{0x3801 ,0x50},
++	{0x3802 ,0x01},
++	{0x3803 ,0xb2},
++	{0x3804 ,0x08},
++	{0x3805 ,0xef},
++	{0x3806 ,0x05},
++	{0x3807 ,0xf1},
++	{0x3808 ,0x07},//width[11:8]1920
++	{0x3809 ,0x80},//width[7:0]
++	{0x380a ,0x04},//height[11:8]1080
++	{0x380b ,0x38},//height[7:0]
++	{0x380c ,0x09},
++	{0x380d ,0xc4},
++	{0x380e ,0x04},
++	{0x380f ,0x60},
++	{0x3813 ,0x04},
++	{0x3814 ,0x11},
++	{0x3815 ,0x11},
++	{0x3820 ,0x40},
++	{0x3821 ,0x06},
++	{0x3a02 ,0x04},
++	{0x3a03 ,0x60},
++	{0x3a09 ,0x50},
++	{0x3a0b ,0x18},
++	{0x3a0e ,0x03},
++	{0x3a0d ,0x04},
++	{0x3a14 ,0x04},
++	{0x3a15 ,0x60},
++	{0x3a18 ,0x00},
++	{0x4004 ,0x06},
++	{0x4050 ,0x6e},
++	{0x4051 ,0x8f},
++	{0x4300 ,0x30},
++	{0x4837 ,0x0b},
++	{0x5301 ,0x1e},
++	{0x5305 ,0x1e},
++	{0x530a ,0x1e},
++	{0x5580 ,0x02},
++	{0x5780 ,0xfc},
++	{0x5781 ,0x13},
++	{0x5782 ,0x03},
++	{0x5786 ,0x20},
++	{0x5787 ,0x40},
++	{0x5788 ,0x08},
++	{0x5789 ,0x08},
++	{0x578a ,0x02},
++	{0x578b ,0x01},
++	{0x578c ,0x01},
++	{0x578d ,0x0c},
++	{0x578e ,0x02},
++	{0x578f ,0x01},
++	{0x5790 ,0x01},
++	{0x3a11 ,0x70},
++	{0x3a1b ,0x38},
++	{0x3a1e ,0x30},
++	{0x3a1f ,0x18},
++	{0x4300 ,0x00},
++	{0x501f ,0x03},
++	{0x3008 ,0x02},
++//	{0x503d ,0x80},
++
++	ENDMARKER,
++};
++
++
++#define OV5645_SIZE(n, w, h, r) \
++	{.name = n, .width = w , .height = h, .regs = r }
++
++static struct ov5645_win_size ov5645_supported_win_sizes[] = {
++	OV5645_SIZE("VGA", W_VGA, H_VGA, ov5645_vga_regs),
++	OV5645_SIZE("720P", W_720P, H_720P, ov5645_720p_regs),
++	OV5645_SIZE("1080P", W_1080P, H_1080P, ov5645_1080p_regs),
++};
++
++#define N_WIN_SIZES (ARRAY_SIZE(ov5645_supported_win_sizes))
++
++struct regval_list ov5645_BGR565_Setting[] = {
++	{0x4300, 0x60},//BGR565
++	{0x501f, 0x01},//ISP RGB
++	ENDMARKER,
++};
++
++struct regval_list ov5645_RGB565_Setting[] = {
++	/* {0x4300, 0x61},//RGB565 */
++	{0x4300, 0x6F},//RGB565
++	{0x501f, 0x01},//ISP RGB */
++	ENDMARKER,
++};
++
++struct regval_list ov5645_GRB565_Setting[] = {
++	{0x4300, 0x62},//GRB565
++	{0x501f, 0x01},//ISP RGB
++	ENDMARKER,
++};
++
++struct regval_list ov5645_BRG565_Setting[] = {
++	{0x4300, 0x63},//BRG565
++	{0x501f, 0x01},//ISP RGB
++	ENDMARKER,
++};
++
++struct regval_list ov5645_GBR565_Setting[] = {
++	{0x4300, 0x64},//GBR565
++	{0x501f, 0x01},//ISP RGB
++	ENDMARKER,
++};
++
++struct regval_list ov5645_RBG565_Setting[] = {
++	{0x4300, 0x65},//GBR565
++	{0x501f, 0x01},//ISP RGB
++	ENDMARKER,
++};
++
++struct regval_list ov5645_YUV422_YUYV_Setting[] = {
++	{0x4300, 0x30},//YUYV
++	{0x501f, 0x00},//ISP YUV
++	ENDMARKER,
++};
++
++struct regval_list ov5645_YUV422_YVYU_Setting[] = {
++	{0x4300, 0x31},//YVYU
++	{0x501f, 0x00},//ISP YUV
++	ENDMARKER,
++};
++
++struct regval_list ov5645_YUV422_UYVY_Setting[] = {
++	{0x4300, 0x32},//UYVY
++	{0x501f, 0x00},//ISP YUV
++	ENDMARKER,
++};
++
++struct regval_list ov5645_YUV422_VYUY_Setting[] = {
++	{0x4300, 0x33},//VYUY
++	{0x501f, 0x00},//ISP YUV
++	ENDMARKER,
++};
++
++struct regval_list ov5645_SBGGR8_Setting[] = {
++	{0x4300, 0xf8},//raw
++	{0x501f, 0x03},
++	{0x3811, 0x10},
++	{0x3813, 0x04},
++	ENDMARKER,
++};
++
++struct regval_list ov5645_SGBRG8_Setting[] = {
++	{0x4300, 0xf8},//raw
++	{0x501f, 0x03},
++	{0x3811, 0x11},
++	{0x3813, 0x04},
++	ENDMARKER,
++};
++
++struct regval_list ov5645_SGRBG8_Setting[] = {
++	{0x4300, 0xf8},//raw
++	{0x501f, 0x03},
++	{0x3811, 0x10},
++	{0x3813, 0x05},
++	ENDMARKER,
++};
++
++struct regval_list ov5645_SRGGB8_Setting[] = {
++	{0x4300, 0xf8},//raw
++	{0x501f, 0x03},
++	{0x3811, 0x11},
++	{0x3813, 0x05},
++	ENDMARKER,
++};
++
++
++struct regval_list ov5645_SBGGR10_Setting[] = {
++	{0x3034, 0x1a},
++	{0x4300, 0xf8},//raw
++	{0x501f, 0x03},
++	{0x3811, 0x10},
++	{0x3813, 0x04},
++	ENDMARKER,
++};
++
++struct regval_list ov5645_SGBRG10_Setting[] = {
++	{0x3034, 0x1a},
++	{0x4300, 0xf8},//raw
++	{0x501f, 0x03},
++	{0x3811, 0x11},
++	{0x3813, 0x04},
++	ENDMARKER,
++};
++
++struct regval_list ov5645_SGRBG10_Setting[] = {
++	{0x3034, 0x1a},
++	{0x4300, 0xf8},//raw
++	{0x501f, 0x03},
++	{0x3811, 0x10},
++	{0x3813, 0x05},
++	ENDMARKER,
++};
++
++struct regval_list ov5645_SRGGB10_Setting[] = {
++	{0x3034, 0x1a},
++	{0x4300, 0xf8},//raw
++	{0x501f, 0x03},
++	{0x3811, 0x11},
++	{0x3813, 0x05},
++	ENDMARKER,
++};
++
++
++struct ov5645_format ov5645_fmt[] = {
++	{MEDIA_BUS_FMT_RGB565_2X8_LE, ov5645_RGB565_Setting},
++	{INGENIC_MEDIA_BUS_FMT_RBG565_2X8_LE, ov5645_RBG565_Setting},
++	{MEDIA_BUS_FMT_BGR565_2X8_LE, ov5645_BGR565_Setting},
++	{INGENIC_MEDIA_BUS_FMT_BRG565_2X8_LE, ov5645_BRG565_Setting},
++	{INGENIC_MEDIA_BUS_FMT_GRB565_2X8_LE, ov5645_GRB565_Setting},
++	{INGENIC_MEDIA_BUS_FMT_GBR565_2X8_LE, ov5645_GBR565_Setting},
++	{MEDIA_BUS_FMT_YUYV8_2X8, ov5645_YUV422_YUYV_Setting},
++	{MEDIA_BUS_FMT_YVYU8_2X8, ov5645_YUV422_YVYU_Setting},
++	{MEDIA_BUS_FMT_UYVY8_2X8, ov5645_YUV422_UYVY_Setting},
++	{MEDIA_BUS_FMT_VYUY8_2X8, ov5645_YUV422_VYUY_Setting},
++	{MEDIA_BUS_FMT_SBGGR8_1X8, ov5645_SBGGR8_Setting},
++	{MEDIA_BUS_FMT_SGBRG8_1X8, ov5645_SGBRG8_Setting},
++	{MEDIA_BUS_FMT_SGRBG8_1X8, ov5645_SGRBG8_Setting},
++	{MEDIA_BUS_FMT_SRGGB8_1X8, ov5645_SRGGB8_Setting},
++	{MEDIA_BUS_FMT_SBGGR10_1X10, ov5645_SBGGR10_Setting},
++	{MEDIA_BUS_FMT_SGBRG10_1X10, ov5645_SGBRG10_Setting},
++	{MEDIA_BUS_FMT_SGRBG10_1X10, ov5645_SGRBG10_Setting},
++	{MEDIA_BUS_FMT_SRGGB10_1X10, ov5645_SRGGB10_Setting},
++};
++
++#define N_FMT_SIZES (ARRAY_SIZE(ov5645_fmt))
++
++/*
++ * Supported balance menus
++ */
++static const struct v4l2_querymenu ov5645_balance_menus[] = {
++	{
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 0,
++		.name		= "auto",
++	}, {
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 1,
++		.name		= "incandescent",
++	}, {
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 2,
++		.name		= "fluorescent",
++	},  {
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 3,
++		.name		= "daylight",
++	},  {
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 4,
++		.name		= "cloudy-daylight",
++	},
++
++};
++
++/*
++ * Supported effect menus
++ */
++static const struct v4l2_querymenu ov5645_effect_menus[] = {
++	{
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 0,
++		.name		= "none",
++	}, {
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 1,
++		.name		= "mono",
++	}, {
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 2,
++		.name		= "sepia",
++	},  {
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 3,
++		.name		= "negative",
++	}, {
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 4,
++		.name		= "aqua",
++	},
++};
++
++
++/*
++ * General functions
++ */
++static struct ov5645_priv *to_ov5645(const struct i2c_client *client)
++{
++	return container_of(i2c_get_clientdata(client), struct ov5645_priv,
++			    subdev);
++}
++
++static int ov5645_write_array(struct i2c_client *client,
++			      const struct regval_list *vals)
++{
++	int ret;
++
++	while (vals->reg_num != 0xffff) {
++		ret = ov5645_write_reg(client, vals->reg_num, vals->value);
++		dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x",
++			 vals->reg_num, vals->value);
++
++		if (ret < 0)
++			return ret;
++		vals++;
++	}
++	return 0;
++}
++
++static int ov5645_mask_set(struct i2c_client *client,
++			   u16  reg, u16  mask, u16  set)
++{
++	s32 val = ov5645_read_reg(client, reg);
++	if (val < 0)
++		return val;
++
++	val &= ~mask;
++	val |= set & mask;
++
++	dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val);
++
++	return ov5645_write_reg(client, reg, val);
++}
++
++
++/* OF probe functions */
++static int ov5645_hw_power(struct i2c_client *client, int on)
++{
++	struct ov5645_priv *priv = to_ov5645(client);
++
++	dev_dbg(&client->dev, "%s: %s the camera\n",
++			__func__, on ? "ENABLE" : "DISABLE");
++
++	/* thses gpio should be set according to the active level in dt defines */
++	if(priv->vcc_en_gpio) {
++		gpiod_direction_output(priv->vcc_en_gpio, on);
++	}
++
++	if (priv->pwdn_gpio) {
++		gpiod_direction_output(priv->pwdn_gpio, !on);
++	}
++
++	msleep(10);
++	return 0;
++}
++
++static int ov5645_reset(struct i2c_client *client)
++{
++	struct ov5645_priv *priv = to_ov5645(client);
++
++	if(priv->resetb_gpio) {
++		gpiod_direction_output(priv->resetb_gpio, 1);
++		msleep(10);
++		gpiod_direction_output(priv->resetb_gpio, 0);
++		msleep(10);
++	}
++
++	return 0;
++}
++
++static int ov5645_g_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd =
++		&container_of(ctrl->handler, struct ov5645_priv, hdl)->subdev;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov5645_priv *priv = to_ov5645(client);
++
++	switch (ctrl->id) {
++	case V4L2_CID_VFLIP:
++		ctrl->val = priv->flag_vflip;
++		break;
++	case V4L2_CID_HFLIP:
++		ctrl->val = priv->flag_hflip;
++		break;
++	case V4L2_CID_PRIVATE_BALANCE:
++		ctrl->val = priv->balance_value;
++		break;
++	case V4L2_CID_PRIVATE_EFFECT:
++		ctrl->val = priv->effect_value;
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++static int ov5645_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd =
++		&container_of(ctrl->handler, struct ov5645_priv, hdl)->subdev;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov5645_priv *priv = to_ov5645(client);
++	int ret = 0;
++	int i = 0;
++	u16 value;
++
++	int balance_count = ARRAY_SIZE(ov5645_balance);
++	int effect_count = ARRAY_SIZE(ov5645_effect);
++
++	switch (ctrl->id) {
++	case V4L2_CID_PRIVATE_BALANCE:
++		if(ctrl->val > balance_count)
++			return -EINVAL;
++
++		for(i = 0; i < balance_count; i++) {
++			if(ctrl->val == ov5645_balance[i].index) {
++				ret = ov5645_write_array(client,
++						ov5645_balance[ctrl->val].mode_regs);
++				priv->balance_value = ctrl->val;
++				break;
++			}
++		}
++		break;
++
++	case V4L2_CID_PRIVATE_EFFECT:
++		if(ctrl->val > effect_count)
++			return -EINVAL;
++
++		for(i = 0; i < effect_count; i++) {
++			if(ctrl->val == ov5645_effect[i].index) {
++				ret = ov5645_write_array(client,
++						ov5645_effect[ctrl->val].mode_regs);
++				priv->effect_value = ctrl->val;
++				break;
++			}
++		}
++		break;
++
++	case V4L2_CID_VFLIP:
++		value = ctrl->val ? OV5645_FLIP_VAL : 0x00;
++		priv->flag_vflip = ctrl->val ? 1 : 0;
++		ret = ov5645_mask_set(client, REG_TC_VFLIP, OV5645_FLIP_MASK, value);
++		break;
++
++	case V4L2_CID_HFLIP:
++		value = ctrl->val ? OV5645_FLIP_VAL : 0x00;
++		priv->flag_hflip = ctrl->val ? 1 : 0;
++		ret = ov5645_mask_set(client, REG_TC_MIRROR, OV5645_FLIP_MASK, value);
++		break;
++
++	default:
++		dev_err(&client->dev, "no V4L2 CID: 0x%x ", ctrl->id);
++		return -EINVAL;
++	}
++	return ret;
++}
++
++static const struct v4l2_ctrl_ops ov5645_ctrl_ops = {
++	.s_ctrl = ov5645_s_ctrl,
++	.g_volatile_ctrl = ov5645_g_ctrl,
++};
++
++static int ov5645_s_power(struct v4l2_subdev *sd, int on)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct ov5645_priv *priv = to_ov5645(client);
++
++	if(priv->sd_pdata) {
++		if(on)
++			return regulator_bulk_enable(priv->sd_pdata->num_regulators,priv->sd_pdata->regulators);
++		else
++			return regulator_bulk_disable(priv->sd_pdata->num_regulators,priv->sd_pdata->regulators);
++	} else if(priv->power){
++		return priv->power(client, on);
++	} else {
++		dev_err(&client->dev, "ov5640_s_power failde");
++		return -EINVAL;
++	}
++}
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ov5645_g_register(struct v4l2_subdev *sd,
++			     struct v4l2_dbg_register *reg)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	int ret;
++
++	reg->size = 1;
++	if (reg->reg > 0xff)
++		return -EINVAL;
++
++	ret = ov5645_read_reg(client, reg->reg);
++	if (ret < 0)
++		return ret;
++
++	reg->val = ret;
++
++	return 0;
++}
++
++static int ov5645_s_register(struct v4l2_subdev *sd,
++			     const struct v4l2_dbg_register *reg)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++
++	if (reg->reg > 0xff ||
++	    reg->val > 0xff)
++		return -EINVAL;
++
++	return ov5645_write_reg(client, reg->reg, reg->val);
++}
++#endif
++
++/*
++ * soc_camera_ops functions
++ */
++static int ov5645_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++
++	if (!enable ) {
++		dev_info(&client->dev, "stream down\n");
++		ov5645_write_reg(client, 0x4202, 0x0f);
++		return 0;
++	}
++
++	dev_info(&client->dev, "stream on\n");
++	ov5645_write_reg(client, 0x4202, 0x00);
++
++	return 0;
++}
++
++/* Select the nearest higher resolution for capture */
++static const struct ov5645_win_size *ov5645_select_win(u32 *width, u32 *height)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(ov5645_supported_win_sizes); i++) {
++		if ((*width <= ov5645_supported_win_sizes[i].width) &&
++		    (*height <= ov5645_supported_win_sizes[i].height)) {
++			*width = ov5645_supported_win_sizes[i].width;
++			*height = ov5645_supported_win_sizes[i].height;
++			return &ov5645_supported_win_sizes[i];
++		}
++	}
++	return NULL;
++}
++
++static int ov5645_get_selection(struct v4l2_subdev *sd,
++					     struct v4l2_subdev_pad_config *cfg,
++					     struct v4l2_subdev_selection *sel)
++{
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov5645_priv *priv = to_ov5645(client);
++
++	if(!priv->win)
++		return -EINVAL;
++
++	sel->r.top = 0;
++	sel->r.left = 0;
++	sel->r.width = priv->win->width;
++	sel->r.height = priv->win->height;
++
++	return 0;
++}
++
++static int ov5645_get_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov5645_priv *priv = to_ov5645(client);
++
++	if (format->pad)
++		return -EINVAL;
++
++	if(priv->win) {
++		mf->width = priv->win->width;
++		mf->height = priv->win->height;
++	} else {
++		mf->width = OV5645_DEFAULT_WIDTH;
++		mf->height = OV5645_DEFAULT_HEIGHT;
++	}
++
++	mf->code = priv->cfmt_code;
++
++	mf->colorspace = V4L2_COLORSPACE_JPEG;
++	mf->field	= V4L2_FIELD_NONE;
++
++	return 0;
++}
++
++static int ov5645_set_params(struct i2c_client *client, u32 *width, u32 *height, u32 code)
++{
++	struct ov5645_priv       *priv = to_ov5645(client);
++	int ret;
++
++	int bala_index = priv->balance_value;
++	int effe_index = priv->effect_value;
++	int i;
++
++	/* select win */
++	priv->win = ov5645_select_win(width, height);
++
++	/* select format */
++	priv->cfmt_code = 0;
++
++	/* reset hardware */
++	ov5645_reset(client);
++
++	/* initialize the sensor with default data */
++	dev_dbg(&client->dev, "%s: Init default", __func__);
++	ret = ov5645_write_array(client, ov5645_init_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set balance */
++	ret = ov5645_write_array(client, ov5645_balance[bala_index].mode_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set effect */
++	ret = ov5645_write_array(client, ov5645_effect[effe_index].mode_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set size win */
++	ret = ov5645_write_array(client, priv->win->regs);
++	if (ret < 0)
++		goto err;
++
++	for (i = 0; i < N_FMT_SIZES; i++) {
++		if (ov5645_fmt[i].code == code) {
++			ret = ov5645_write_array(client, ov5645_fmt[i].regs);
++			if (ret < 0)
++				goto err;
++		}
++	}
++
++	priv->cfmt_code = code;
++	*width = priv->win->width;
++	*height = priv->win->height;
++
++	return 0;
++
++err:
++	dev_err(&client->dev, "%s: Error %d", __func__, ret);
++	ov5645_reset(client);
++	priv->win = NULL;
++
++	return ret;
++}
++
++static int ov5645_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct ov5645_priv       *priv = to_ov5645(client);
++
++	if (format->pad)
++		return -EINVAL;
++
++	/*
++	 * select suitable win, but don't store it
++	 */
++	priv->win = ov5645_select_win(&mf->width, &mf->height);
++	if(!priv->win)
++		return -EINVAL;
++
++	mf->field	= V4L2_FIELD_NONE;
++	mf->colorspace = V4L2_COLORSPACE_JPEG;
++
++	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
++		ov5645_set_params(client, &mf->width,
++					 &mf->height, mf->code);
++	if(cfg)
++		cfg->try_fmt = *mf;
++	return 0;
++}
++
++static int ov5645_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad || code->index >= N_FMT_SIZES)
++		return -EINVAL;
++
++	code->code = ov5645_fmt[code->index].code;
++	return 0;
++}
++
++static int ov5645_enum_frame_size(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_frame_size_enum *fse)
++{
++	int i, j;
++	int num_valid = -1;
++	__u32 index = fse->index;
++
++	if(index >= N_WIN_SIZES)
++		return -EINVAL;
++
++	j = N_FMT_SIZES;
++	while(--j)
++		if(fse->code == ov5645_fmt[j].code)
++			break;
++
++	for (i = 0; i < N_WIN_SIZES; i++) {
++		if (index == ++num_valid) {
++			fse->code = ov5645_fmt[j].code;
++			fse->min_width = ov5645_supported_win_sizes[index].width;
++			fse->max_width = fse->min_width;
++			fse->min_height = ov5645_supported_win_sizes[index].height;
++			fse->max_height = fse->min_height;
++			return 0;
++		}
++	}
++
++	return -EINVAL;
++}
++
++static int ov5645_hw_reset(struct i2c_client *client)
++{
++	struct ov5645_priv *priv = to_ov5645(client);
++
++	if(priv->resetb_gpio) {
++		gpiod_direction_output(priv->resetb_gpio, 1);
++		usleep_range(3000, 5000);
++		gpiod_direction_output(priv->resetb_gpio, 0);
++	}
++	return 0;
++}
++
++static int ov5645_video_probe(struct i2c_client *client)
++{
++	unsigned char retval = 0, retval_high = 0, retval_low = 0;
++	struct ov5645_priv *priv = to_ov5645(client);
++	int ret;
++
++	ret = ov5645_s_power(&priv->subdev, 1);
++	if (ret < 0)
++		return ret;
++	/*
++	 * check and show product ID and manufacturer ID
++	 */
++
++	retval = ov5645_write_reg(client, 0x3008, 0x82);
++	if(retval) {
++		dev_err(&client->dev, "i2c write failed!\n");
++		ret = -EINVAL;
++		goto done;
++	}
++
++	retval_high = ov5645_read_reg(client, REG_CHIP_ID_HIGH);
++	if (retval_high != CHIP_ID_HIGH) {
++		dev_err(&client->dev, "read sensor %s chip_id high %x is error\n",
++				client->name, retval_high);
++		ret = -EINVAL;
++		goto done;
++	}
++
++
++	retval_low = ov5645_read_reg(client, REG_CHIP_ID_LOW);
++	if (retval_low != CHIP_ID_LOW) {
++		dev_err(&client->dev, "read sensor %s chip_id low %x is error\n",
++				client->name, retval_low);
++		ret = -EINVAL;
++		goto done;
++	}
++
++	dev_info(&client->dev, "read sensor %s id high:0x%x,low:%x successed!\n",
++			client->name, retval_high, retval_low);
++
++done:
++	return ret;
++}
++
++static int ov5645_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
++		struct v4l2_mbus_config *cfg)
++{
++	/*int dts*/
++	return 0;
++}
++
++static struct v4l2_subdev_core_ops ov5645_subdev_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register	= ov5645_g_register,
++	.s_register	= ov5645_s_register,
++#endif
++	.s_power	= ov5645_s_power,
++};
++
++static struct v4l2_subdev_video_ops ov5645_subdev_video_ops = {
++	.s_stream	= ov5645_s_stream,
++};
++
++static const struct v4l2_subdev_pad_ops ov5645_subdev_pad_ops = {
++	.enum_mbus_code = ov5645_enum_mbus_code,
++	.enum_frame_size = ov5645_enum_frame_size,
++	.get_fmt	= ov5645_get_fmt,
++	.set_fmt	= ov5645_set_fmt,
++	.get_mbus_config = ov5645_g_mbus_config,
++	.get_selection	= ov5645_get_selection,
++};
++
++static struct v4l2_subdev_ops ov5645_subdev_ops = {
++	.core	= &ov5645_subdev_core_ops,
++	.video	= &ov5645_subdev_video_ops,
++	.pad	= &ov5645_subdev_pad_ops,
++};
++
++static int ov5645_probe_dt(struct i2c_client *client,
++		struct ov5645_priv *priv)
++{
++	struct v4l2_subdev_platform_data *sd_pdata = priv->sd_pdata;
++	struct device_node *np = client->dev.of_node;
++	int supplies = 0, index = 0;
++
++	supplies = of_property_count_strings(np, "supplies-name");
++	if(supplies > 0) {
++		sd_pdata = devm_kzalloc(&client->dev, sizeof(struct v4l2_subdev_platform_data), GFP_KERNEL);
++		sd_pdata->num_regulators = supplies;
++		sd_pdata->regulators = devm_kzalloc(&client->dev, supplies * sizeof(struct regulator_bulk_data), GFP_KERNEL);
++		if(!sd_pdata->regulators) {
++			dev_err(&client->dev, "Failed to allocate regulators.!\n");
++			devm_kfree(&client->dev,sd_pdata);
++			return -ENOMEM;
++		}
++
++		for(index = 0; index < sd_pdata->num_regulators; index ++) {
++			of_property_read_string_index(np, "supplies-name", index,
++					&(sd_pdata->regulators[index].supply));
++
++			dev_dbg(&client->dev, "sd_pdata->regulators[%d].supply: %s\n",
++					index, sd_pdata->regulators[index].supply);
++		}
++
++		devm_regulator_bulk_get(&client->dev, sd_pdata->num_regulators, sd_pdata->regulators);
++	} else {
++		/* Request the reset GPIO deasserted */
++		priv->resetb_gpio = devm_gpiod_get_optional(&client->dev, "resetb",
++				GPIOD_OUT_LOW);
++		if (!priv->resetb_gpio)
++			dev_dbg(&client->dev, "resetb gpio is not assigned!\n");
++		else if (IS_ERR(priv->resetb_gpio))
++			return PTR_ERR(priv->resetb_gpio);
++
++		/* Request the power down GPIO asserted */
++		priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn",
++				GPIOD_OUT_HIGH);
++		if (!priv->pwdn_gpio)
++			dev_dbg(&client->dev, "pwdn gpio is not assigned!\n");
++		else if (IS_ERR(priv->pwdn_gpio))
++			return PTR_ERR(priv->pwdn_gpio);
++
++		/* Request the power down GPIO asserted */
++		priv->vcc_en_gpio = devm_gpiod_get_optional(&client->dev, "vcc-en",
++				GPIOD_OUT_HIGH);
++		if (!priv->vcc_en_gpio)
++			dev_dbg(&client->dev, "vcc_en gpio is not assigned!\n");
++		else if (IS_ERR(priv->vcc_en_gpio))
++			return PTR_ERR(priv->vcc_en_gpio);
++
++		/* Initialize the soc_camera_subdev_desc */
++		priv->power = ov5645_hw_power;
++		priv->reset = ov5645_hw_reset;
++	}
++	return 0;
++}
++
++#include <linux/regulator/consumer.h>
++/*
++ * i2c_driver functions
++ */
++static int ov5645_probe(struct i2c_client *client,
++			const struct i2c_device_id *did)
++{
++	struct ov5645_priv	*priv;
++	struct i2c_adapter	*adapter = to_i2c_adapter(client->dev.parent);
++	int	ret;
++
++	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA)) {
++		dev_err(&adapter->dev,
++			"ov5645: I2C-Adapter doesn't support SMBUS\n");
++		return -EIO;
++	}
++
++	priv = devm_kzalloc(&client->dev, sizeof(struct ov5645_priv), GFP_KERNEL);
++	if (!priv) {
++		dev_err(&adapter->dev,
++			"Failed to allocate memory for private data!\n");
++		return -ENOMEM;
++	}
++
++	priv->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(priv->clk))
++		return -EPROBE_DEFER;
++
++	v4l2_clk_set_rate(priv->clk, 24000000);
++
++	/*mclk gate close*/
++//	*(volatile unsigned int *)0xb0000024 &= ~(1 << 5);
++
++	ret = ov5645_probe_dt(client, priv);
++	if (ret)
++		goto err_probe_dt;
++
++	v4l2_i2c_subdev_init(&priv->subdev, client, &ov5645_subdev_ops);
++
++	/* add handler */
++	v4l2_ctrl_handler_init(&priv->hdl, 2);
++	v4l2_ctrl_new_std(&priv->hdl, &ov5645_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&priv->hdl, &ov5645_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	priv->subdev.ctrl_handler = &priv->hdl;
++	if (priv->hdl.error) {
++		ret = priv->hdl.error;
++		goto err_hdl;
++	}
++
++	ret = ov5645_video_probe(client);
++	if (ret < 0)
++		goto err_detect;
++
++	ret = v4l2_ctrl_handler_setup(&priv->hdl);
++
++	ret = v4l2_async_register_subdev(&priv->subdev);
++	if (ret < 0)
++		goto err_async_register_subdev;
++
++	dev_info(&adapter->dev, "ov5645 Probed\n");
++
++	return 0;
++
++err_async_register_subdev:
++err_detect:
++	v4l2_ctrl_handler_free(&priv->hdl);
++err_hdl:
++	v4l2_device_unregister_subdev(&priv->subdev);
++err_probe_dt:
++	v4l2_clk_put(priv->clk);
++	devm_kfree(&client->dev, priv);
++	return ret;
++}
++
++static int ov5645_remove(struct i2c_client *client)
++{
++	struct ov5645_priv       *priv = to_ov5645(client);
++
++	v4l2_async_unregister_subdev(&priv->subdev);
++	v4l2_clk_put(priv->clk);
++	v4l2_device_unregister_subdev(&priv->subdev);
++	v4l2_ctrl_handler_free(&priv->hdl);
++	devm_kfree(&client->dev, priv);
++	return 0;
++}
++
++static const struct i2c_device_id ov5645_id[] = {
++	{ "ov5645",  0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ov5645_id);
++static const struct of_device_id ov5645_of_match[] = {
++	{.compatible = "ovti,ov5645", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov5645_of_match);
++static struct i2c_driver ov5645_i2c_driver = {
++	.driver = {
++		.name = "ov5645",
++		.of_match_table = of_match_ptr(ov5645_of_match),
++	},
++	.probe    = ov5645_probe,
++	.remove   = ov5645_remove,
++	.id_table = ov5645_id,
++};
++module_i2c_driver(ov5645_i2c_driver);
++
++MODULE_DESCRIPTION("SoC Camera driver for Omni Vision ov5645 sensor");
++MODULE_AUTHOR("Alberto Panizzo");
++MODULE_LICENSE("GPL v2");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-cim/ov9281-dvp-snapshot.c b/module_drivers/drivers/media/i2c/ingenic-cim/ov9281-dvp-snapshot.c
+new file mode 100644
+index 000000000..63335df05
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-cim/ov9281-dvp-snapshot.c
+@@ -0,0 +1,1223 @@
++/*
++ * ov9281 Camera Driver
++ *
++ * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com>
++ *
++ * Based on ov772x, ov9640 drivers and previous non merged implementations.
++ *
++ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright (C) 2006, OmniVision
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/i2c.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/gpio/consumer.h>
++#include <linux/of_gpio.h>
++#include <linux/v4l2-mediabus.h>
++#include <linux/videodev2.h>
++
++#include <media/v4l2-clk.h>
++#include <media/v4l2-subdev.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-image-sizes.h>
++#include <media/v4l2-device.h>
++#include <ingenic_camera.h>
++
++#include <linux/clk.h>
++#include <linux/regulator/consumer.h>
++
++#define REG_CHIP_ID_HIGH	0x300a
++#define REG_CHIP_ID_LOW		0x300b
++#define CHIP_ID_HIGH		0x92
++#define CHIP_ID_LOW		0x81
++
++#define  OV9281_DEFAULT_WIDTH    1280
++#define  OV9281_DEFAULT_HEIGHT   720
++/* #define  OV9281_DEFAULT_WIDTH    640 */
++/* #define  OV9281_DEFAULT_HEIGHT   480 */
++
++/* Private v4l2 controls */
++#define V4L2_CID_PRIVATE_BALANCE  (V4L2_CID_PRIVATE_BASE + 0)
++#define V4L2_CID_PRIVATE_EFFECT  (V4L2_CID_PRIVATE_BASE + 1)
++
++#define REG_TC_VFLIP			0x3820
++#define REG_TC_MIRROR			0x3821
++#define OV9281_FLIP_VAL			((unsigned char)0x04)
++#define OV9281_FLIP_MASK		((unsigned char)0x04)
++
++/* whether sensor support high resolution (> vga) preview or not */
++#define SUPPORT_HIGH_RESOLUTION_PRE		1
++
++/*
++ * Struct
++ */
++struct regval_list {
++	u16 reg_num;
++	u16 value;
++};
++
++struct mode_list {
++	u16 index;
++	const struct regval_list *mode_regs;
++};
++
++/* Supported resolutions */
++enum ov9281_width {
++	W_720P	= OV9281_DEFAULT_WIDTH,
++	/* W_640 = OV9281_DEFAULT_WIDTH, */
++};
++
++enum ov9281_height {
++	H_720P	= OV9281_DEFAULT_HEIGHT,
++	/* H_480 = OV9281_DEFAULT_HEIGHT, */
++};
++
++struct ov9281_win_size {
++	char *name;
++	enum ov9281_width width;
++	enum ov9281_height height;
++	const struct regval_list *regs;
++	unsigned int mbus_code;
++};
++
++struct ov9281_priv {
++	struct v4l2_subdev		subdev;
++	struct v4l2_ctrl_handler	hdl;
++	u32	cfmt_code;
++	struct v4l2_clk			*clk;
++	const struct ov9281_win_size	*win;
++
++	int				model;
++	u16				balance_value;
++	u16				effect_value;
++	u16				flag_vflip:1;
++	u16				flag_hflip:1;
++
++	struct v4l2_subdev_platform_data *sd_pdata;
++	struct gpio_desc *resetb_gpio;
++	struct gpio_desc *pwdn_gpio;
++	struct gpio_desc *vcc_en_gpio;
++
++	int (*power)(struct i2c_client *client, int on);
++	int (*reset)(struct i2c_client *client);
++
++	struct regulator *reg;
++	struct regulator *reg1;
++};
++
++static inline int sensor_i2c_master_send(struct i2c_client *client,
++		const char *buf ,int count)
++{
++	int ret;
++	struct i2c_adapter *adap=client->adapter;
++	struct i2c_msg msg;
++
++	msg.addr = client->addr;
++	msg.flags = client->flags & I2C_M_TEN;
++	msg.len = count;
++	msg.buf = (char *)buf;
++
++	ret = i2c_transfer(adap, &msg, 1);
++
++	return (ret == 1) ? count : ret;
++}
++
++static inline int sensor_i2c_master_recv(struct i2c_client *client,
++		char *buf ,int count)
++{
++	struct i2c_adapter *adap=client->adapter;
++	struct i2c_msg msg;
++	int ret;
++
++	msg.addr = client->addr;
++	msg.flags = client->flags & I2C_M_TEN;
++	msg.flags |= I2C_M_RD;
++	msg.len = count;
++	msg.buf = buf;
++	ret = i2c_transfer(adap, &msg, 1);
++
++	return (ret == 1) ? count : ret;
++}
++
++
++unsigned char ov9281_read_reg(struct i2c_client *client, u16 reg)
++{
++	int ret;
++	unsigned char retval;
++	unsigned short r = cpu_to_be16(reg);
++
++	ret = sensor_i2c_master_send(client,(u8 *)&r,2);
++
++	if (ret < 0)
++		return ret;
++	if (ret != 2)
++		return -EIO;
++
++	ret = sensor_i2c_master_recv(client, &retval, 1);
++	if (ret < 0)
++		return ret;
++	if (ret != 1)
++		return -EIO;
++	return retval;
++}
++
++int ov9281_write_reg(struct i2c_client *client, u16 reg, u8 val)
++{
++	unsigned char msg[3];
++	int ret;
++
++	reg = cpu_to_be16(reg);
++
++	memcpy(&msg[0], &reg, 2);
++	memcpy(&msg[2], &val, 1);
++
++	ret = sensor_i2c_master_send(client, msg, 3);
++
++	if (ret < 0)
++	{
++		printk("RET<0\n");
++		return ret;
++	}
++	if (ret < 3)
++	{
++		printk("RET<3\n");
++		return -EIO;
++	}
++
++	return 0;
++}
++
++/*
++ * Registers settings
++ */
++
++#define ENDMARKER { 0xffff, 0xff }
++
++static const struct regval_list ov9281_init_regs[] = {
++	{ 0x0103, 0x01 },
++	{ 0x0302, 0x30 },
++	{ 0x030d, 0x60 },
++	{ 0x030e, 0x06 },
++	{ 0x3001, 0x62 },
++	{ 0x3004, 0x01 },
++	{ 0x3005, 0xff },
++
++	{ 0x3667, 0xda }, //choose PWM pin for DVP vsync output
++	{ 0x3006, 0xe6 }, //[2]1:enable output for PWM pin ; [1]0:enable input for FSIN pin
++	{ 0x0100, 0x01 },
++
++
++	{ 0x3011, 0x0a },
++	{ 0x3013, 0x18 },
++	{ 0x3022, 0x07 },
++	{ 0x3030, 0x10 },
++	{ 0x3039, 0x2e },
++	{ 0x303a, 0xf0 },
++	{ 0x3500, 0x00 },
++	{ 0x3501, 0x2a },
++	{ 0x3502, 0x90 },
++	{ 0x3503, 0x08 },
++	{ 0x3505, 0x8c },
++	{ 0x3507, 0x03 },
++	{ 0x3508, 0x00 },
++//	{ 0x3509, 0x40 },
++	{ 0x3509, 0x30 },
++	{ 0x3610, 0x80 },
++	{ 0x3611, 0xa0 },
++	{ 0x3620, 0x6f },
++	{ 0x3632, 0x56 },
++	{ 0x3633, 0x78 },
++	{ 0x3662, 0x03 },
++	{ 0x3666, 0x5a },
++	{ 0x366f, 0x7e },
++	{ 0x3680, 0x84 },
++	{ 0x3712, 0x80 },
++	{ 0x372d, 0x22 },
++	{ 0x3731, 0x80 },
++	{ 0x3732, 0x30 },
++	{ 0x3778, 0x00 },
++	{ 0x377d, 0x22 },
++	{ 0x3788, 0x02 },
++	{ 0x3789, 0xa4 },
++	{ 0x378a, 0x00 },
++	{ 0x378b, 0x4a },
++	{ 0x3799, 0x20 },
++	{ 0x3800, 0x00 },
++	{ 0x3801, 0x00 },
++	{ 0x3802, 0x00 },
++	{ 0x3803, 0x00 },
++	{ 0x3804, 0x05 },
++	{ 0x3805, 0x0f },
++	{ 0x3806, 0x03 },
++	{ 0x3807, 0x2f },
++	{ 0x3808, 0x05 },
++	{ 0x3809, 0x00 },
++	{ 0x380a, 0x02 },
++	{ 0x380b, 0xd0 },
++	{ 0x380c, 0x02 },
++	{ 0x380d, 0xd8 },
++	{ 0x380e, 0x03 },
++	{ 0x380f, 0x54 },
++	{ 0x3810, 0x00 },
++	{ 0x3811, 0x08 },
++	{ 0x3812, 0x00 },
++	{ 0x3813, 0x08 },
++	{ 0x3814, 0x11 },
++	{ 0x3815, 0x11 },
++	{ 0x3820, 0x40 },
++	{ 0x3821, 0x00 },
++	{ 0x3881, 0x42 },
++	{ 0x38b1, 0x00 },
++	{ 0x3920, 0xff },
++	{ 0x4003, 0x40 },
++	{ 0x4008, 0x04 },
++	{ 0x4009, 0x0b },
++	{ 0x400c, 0x00 },
++	{ 0x400d, 0x07 },
++	{ 0x4010, 0x40 },
++	{ 0x4043, 0x40 },
++	{ 0x4307, 0x30 },
++	{ 0x4317, 0x01 },
++	{ 0x4501, 0x00 },
++	{ 0x4507, 0x00 },
++	{ 0x4509, 0x00 },
++	{ 0x450a, 0x08 },
++	{ 0x4601, 0x04 },
++	{ 0x470f, 0xe0 },
++	{ 0x4f07, 0x00 },
++	{ 0x4800, 0x00 },
++	{ 0x5000, 0x9f },
++	{ 0x5001, 0x00 },
++	{ 0x5e00, 0x00 },
++	{ 0x5d00, 0x0b },
++	{ 0x5d01, 0x02 },
++
++	{ 0x4f00, 0x01},
++	{ 0x0100, 0x00},
++
++	{ 0x320c, 0x8f},
++	{ 0x302c, 0x00},
++	{ 0x302d, 0x00},
++	{ 0x302e, 0x00},
++	{ 0x302f, 0x02},
++	{ 0x303f, 0x01},
++	{ 0x3023, 0x07},
++	{ 0x4242, 0x00},
++
++//	{ 0x3030, 0x80},
++//	{ 0x3030, 0x10},
++//	{ 0x3030, 0x90},
++	{ 0x3030, 0x80},
++	{ 0x3030, 0x84},
++
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_wb_auto_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_wb_incandescence_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_wb_daylight_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_wb_fluorescent_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_wb_cloud_regs[] = {
++	ENDMARKER,
++};
++
++static const struct mode_list ov9281_balance[] = {
++	{0, ov9281_wb_auto_regs}, {1, ov9281_wb_incandescence_regs},
++	{2, ov9281_wb_daylight_regs}, {3, ov9281_wb_fluorescent_regs},
++	{4, ov9281_wb_cloud_regs},
++};
++
++
++static const struct regval_list ov9281_effect_normal_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_effect_grayscale_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_effect_sepia_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_effect_colorinv_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_effect_sepiabluel_regs[] = {
++	ENDMARKER,
++};
++
++static const struct mode_list ov9281_effect[] = {
++	{0, ov9281_effect_normal_regs}, {1, ov9281_effect_grayscale_regs},
++	{2, ov9281_effect_sepia_regs}, {3, ov9281_effect_colorinv_regs},
++	{4, ov9281_effect_sepiabluel_regs},
++};
++
++static const struct regval_list ov9281_720p_regs[] = {
++    {0x4708, 0x0},
++    {0x3808,0x05},
++    {0x3809,0x00},      /* ISP Horizontal Output Width: 1280 */
++    {0x380a,0x02},
++    {0x380b,0xd0},      /* ISP Vertical Output Width : 720*/
++    {0x380c,0x02},
++    {0x380d,0xd8},      /* HTS: Horizontal Timing Size: 728 */
++    {0x380e,0x03},
++    {0x380f,0x8e},      /* VTS: Vertical Timing Size: 910 */
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_vga_regs[] = {
++	{ 0x3808, 0x02 },
++	{ 0x3809, 0x80 },
++	{ 0x380a, 0x01 },
++	{ 0x380b, 0xe0 },
++	{ 0x380c, 0x02 },
++	{ 0x380d, 0xd8 },
++	{ 0x380e, 0x03 },
++	{ 0x380f, 0x54 },
++	ENDMARKER,
++};
++
++#define OV9281_SIZE(n, w, h, r, c) \
++	{.name = n, .width = w , .height = h, .regs = r, .mbus_code = c }
++
++static struct ov9281_win_size ov9281_supported_win_sizes[] = {
++	OV9281_SIZE("720P", W_720P, H_720P, ov9281_720p_regs, MEDIA_BUS_FMT_Y8_1X8),
++	/* OV9281_SIZE("vga", W_640,H_480,ov9281_vga_regs), */
++};
++
++#define N_WIN_SIZES (ARRAY_SIZE(ov9281_supported_win_sizes))
++/*
++static u32 ov9281_codes[] = {
++	MEDIA_BUS_FMT_Y8_1X8,
++};
++*/
++/*
++ * Supported balance menus
++ */
++static const struct v4l2_querymenu ov9281_balance_menus[] = {
++	{
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 0,
++		.name		= "auto",
++	}, {
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 1,
++		.name		= "incandescent",
++	}, {
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 2,
++		.name		= "fluorescent",
++	},  {
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 3,
++		.name		= "daylight",
++	},  {
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 4,
++		.name		= "cloudy-daylight",
++	},
++
++};
++
++/*
++ * Supported effect menus
++ */
++static const struct v4l2_querymenu ov9281_effect_menus[] = {
++	{
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 0,
++		.name		= "none",
++	}, {
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 1,
++		.name		= "mono",
++	}, {
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 2,
++		.name		= "sepia",
++	},  {
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 3,
++		.name		= "negative",
++	}, {
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 4,
++		.name		= "aqua",
++	},
++};
++
++
++/*
++ * General functions
++ */
++static struct ov9281_priv *to_ov9281(const struct i2c_client *client)
++{
++	return container_of(i2c_get_clientdata(client), struct ov9281_priv,
++			    subdev);
++}
++
++static int ov9281_write_array(struct i2c_client *client,
++			      const struct regval_list *vals)
++{
++	int ret;
++
++	while ((vals->reg_num != 0xffff) || (vals->value != 0xff)) {
++		ret = ov9281_write_reg(client, vals->reg_num, vals->value);
++		dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x",
++			 vals->reg_num, vals->value);
++
++		if (ret < 0)
++			return ret;
++		vals++;
++	}
++	return 0;
++}
++#if 1
++static int ov9281_mask_set(struct i2c_client *client,
++			   u16  reg, u16  mask, u16  set)
++{
++	s32 val = ov9281_read_reg(client, reg);
++	if (val < 0)
++		return val;
++
++	val &= ~mask;
++	val |= set & mask;
++
++	dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val);
++
++	return ov9281_write_reg(client, reg, val);
++}
++#endif
++
++/* OF probe functions */
++static int ov9281_hw_power(struct i2c_client *client, int on)
++{
++	struct ov9281_priv *priv = to_ov9281(client);
++
++	dev_dbg(&client->dev, "%s: %s the camera\n",
++			__func__, on ? "ENABLE" : "DISABLE");
++
++	/* thses gpio should be set according to the active level in dt defines */
++	if(priv->vcc_en_gpio) {
++		gpiod_direction_output(priv->vcc_en_gpio, on);
++	}
++
++	if (priv->pwdn_gpio) {
++		gpiod_direction_output(priv->pwdn_gpio, on);
++	}
++
++	msleep(10);
++	return 0;
++}
++
++static int ov9281_reset(struct i2c_client *client)
++{
++	struct ov9281_priv *priv = to_ov9281(client);
++
++	if(priv->resetb_gpio) {
++		gpiod_direction_output(priv->resetb_gpio, 1);
++		msleep(10);
++		gpiod_direction_output(priv->resetb_gpio, 0);
++		msleep(10);
++	}
++
++	return 0;
++}
++
++static int ov9281_g_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd =
++		&container_of(ctrl->handler, struct ov9281_priv, hdl)->subdev;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov9281_priv *priv = to_ov9281(client);
++
++	switch (ctrl->id) {
++	case V4L2_CID_VFLIP:
++		ctrl->val = priv->flag_vflip;
++		break;
++	case V4L2_CID_HFLIP:
++		ctrl->val = priv->flag_hflip;
++		break;
++	case V4L2_CID_PRIVATE_BALANCE:
++		ctrl->val = priv->balance_value;
++		break;
++	case V4L2_CID_PRIVATE_EFFECT:
++		ctrl->val = priv->effect_value;
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++static int ov9281_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd =
++		&container_of(ctrl->handler, struct ov9281_priv, hdl)->subdev;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov9281_priv *priv = to_ov9281(client);
++	int ret = 0;
++	int i = 0;
++	u16 value;
++
++	int balance_count = ARRAY_SIZE(ov9281_balance);
++	int effect_count = ARRAY_SIZE(ov9281_effect);
++
++	switch (ctrl->id) {
++	case V4L2_CID_PRIVATE_BALANCE:
++		if(ctrl->val > balance_count)
++			return -EINVAL;
++
++		for(i = 0; i < balance_count; i++) {
++			if(ctrl->val == ov9281_balance[i].index) {
++				ret = ov9281_write_array(client,
++						ov9281_balance[ctrl->val].mode_regs);
++				priv->balance_value = ctrl->val;
++				break;
++			}
++		}
++		break;
++
++	case V4L2_CID_PRIVATE_EFFECT:
++		if(ctrl->val > effect_count)
++			return -EINVAL;
++
++		for(i = 0; i < effect_count; i++) {
++			if(ctrl->val == ov9281_effect[i].index) {
++				ret = ov9281_write_array(client,
++						ov9281_effect[ctrl->val].mode_regs);
++				priv->effect_value = ctrl->val;
++				break;
++			}
++		}
++		break;
++
++	case V4L2_CID_VFLIP:
++		value = ctrl->val ? OV9281_FLIP_VAL : 0x00;
++		priv->flag_vflip = ctrl->val ? 1 : 0;
++		ret = ov9281_mask_set(client, REG_TC_VFLIP, OV9281_FLIP_MASK, value);
++		break;
++
++	case V4L2_CID_HFLIP:
++		value = ctrl->val ? OV9281_FLIP_VAL : 0x00;
++		priv->flag_hflip = ctrl->val ? 1 : 0;
++		ret = ov9281_mask_set(client, REG_TC_MIRROR, OV9281_FLIP_MASK, value);
++		break;
++
++	default:
++		dev_err(&client->dev, "no V4L2 CID: 0x%x ", ctrl->id);
++		return -EINVAL;
++	}
++
++	return ret;
++}
++
++static const struct v4l2_ctrl_ops ov9281_ctrl_ops = {
++	.s_ctrl = ov9281_s_ctrl,
++	.g_volatile_ctrl = ov9281_g_ctrl,
++};
++#if 0
++static int ov9281_querymenu(struct v4l2_subdev *sd,
++					struct v4l2_querymenu *qm)
++{
++	switch (qm->id) {
++	case V4L2_CID_PRIVATE_BALANCE:
++		memcpy(qm->name, ov9281_balance_menus[qm->index].name,
++				sizeof(qm->name));
++		break;
++
++	case V4L2_CID_PRIVATE_EFFECT:
++		memcpy(qm->name, ov9281_effect_menus[qm->index].name,
++				sizeof(qm->name));
++		break;
++	}
++
++	return 0;
++}
++#endif
++
++static int ov9281_s_power(struct v4l2_subdev *sd, int on)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct ov9281_priv *priv = to_ov9281(client);
++
++	if(priv->sd_pdata) {
++		if(on)
++			return regulator_bulk_enable(priv->sd_pdata->num_regulators,priv->sd_pdata->regulators);
++		else
++			return regulator_bulk_disable(priv->sd_pdata->num_regulators,priv->sd_pdata->regulators);
++	} else if(priv->power) {
++		return priv->power(client, on);
++	} else {
++		dev_err(&client->dev, "ov9281_s_power failde");
++		return -EINVAL;
++	}
++
++//	return soc_camera_set_power(&client->dev, ssdd, priv->clk, on);
++}
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ov9281_g_register(struct v4l2_subdev *sd,
++			     struct v4l2_dbg_register *reg)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	int ret;
++
++	reg->size = 1;
++	if (reg->reg > 0xff)
++		return -EINVAL;
++
++	ret = ov9281_read_reg(client, reg->reg);
++	if (ret < 0)
++		return ret;
++
++	reg->val = ret;
++
++	return 0;
++}
++
++static int ov9281_s_register(struct v4l2_subdev *sd,
++			     const struct v4l2_dbg_register *reg)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++
++	if (reg->reg > 0xff ||
++	    reg->val > 0xff)
++		return -EINVAL;
++
++	return ov9281_write_reg(client, reg->reg, reg->val);
++}
++#endif
++
++/*
++ * soc_camera_ops functions
++ */
++static int ov9281_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++
++	if (!enable ) {
++		dev_info(&client->dev, "stream down\n");
++		ov9281_write_reg(client, 0x0100, 0x00);
++		return 0;
++	}
++
++	dev_info(&client->dev, "stream on\n");
++	ov9281_write_reg(client, 0x0100, 0x01);
++
++	return 0;
++}
++
++/* Select the nearest higher resolution for capture */
++static const struct ov9281_win_size *ov9281_select_win(u32 *code, u32 *width, u32 *height)
++{
++	int i, default_size = ARRAY_SIZE(ov9281_supported_win_sizes) - 1;
++
++	for (i = 0; i < ARRAY_SIZE(ov9281_supported_win_sizes); i++) {
++		if ((*width >= ov9281_supported_win_sizes[i].width) &&
++		    (*height >= ov9281_supported_win_sizes[i].height) &&
++		    (*code == ov9281_supported_win_sizes[i].mbus_code)) {
++			*width = ov9281_supported_win_sizes[i].width;
++			*height = ov9281_supported_win_sizes[i].height;
++			return &ov9281_supported_win_sizes[i];
++		}
++	}
++	return NULL;
++}
++
++static int ov9281_get_selection(struct v4l2_subdev *sd,
++			     struct v4l2_subdev_pad_config *cfg,
++			     struct v4l2_subdev_selection *sel)
++{
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov9281_priv *priv = to_ov9281(client);
++
++	if(!priv->win)
++		return -EINVAL;
++
++	sel->r.top = 0;
++	sel->r.left = 0;
++	sel->r.width = priv->win->width;
++	sel->r.height = priv->win->height;
++
++	return 0;
++}
++
++static int ov9281_get_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov9281_priv *priv = to_ov9281(client);
++
++	if (format->pad)
++		return -EINVAL;
++
++	if(priv->win) {
++		mf->width = priv->win->width;
++		mf->height = priv->win->height;
++	} else {
++		mf->width = OV9281_DEFAULT_WIDTH;
++		mf->height = OV9281_DEFAULT_HEIGHT;
++	}
++	mf->code = priv->cfmt_code;
++
++	mf->colorspace = V4L2_COLORSPACE_JPEG;
++	mf->field	= V4L2_FIELD_NONE;
++
++	return 0;
++}
++
++static int ov9281_set_params(struct i2c_client *client, u32 *width, u32 *height, u32 code)
++{
++	struct ov9281_priv       *priv = to_ov9281(client);
++	int ret;
++
++	int bala_index = priv->balance_value;
++	int effe_index = priv->effect_value;
++
++	/* select win */
++	priv->win = ov9281_select_win(&code, width, height);
++
++	/* select format */
++	priv->cfmt_code = 0;
++
++	/* reset hardware */
++	ov9281_reset(client);
++
++	/* initialize the sensor with default data */
++	dev_dbg(&client->dev, "%s: Init default", __func__);
++	ret = ov9281_write_array(client, ov9281_init_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set balance */
++	ret = ov9281_write_array(client, ov9281_balance[bala_index].mode_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set effect */
++	ret = ov9281_write_array(client, ov9281_effect[effe_index].mode_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set size win */
++	ret = ov9281_write_array(client, priv->win->regs);
++	if (ret < 0)
++		goto err;
++
++	priv->cfmt_code = code;
++	*width = priv->win->width;
++	*height = priv->win->height;
++
++	return 0;
++
++err:
++	dev_err(&client->dev, "%s: Error %d", __func__, ret);
++	ov9281_reset(client);
++	priv->win = NULL;
++
++	return ret;
++}
++
++static int ov9281_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct ov9281_priv *priv = to_ov9281(client);
++
++	if (format->pad)
++		return -EINVAL;
++
++	/*
++	 * select suitable win, but don't store it
++	 */
++	priv->win = ov9281_select_win(&mf->code, &mf->width, &mf->height);
++	if(!priv->win)
++		return -EINVAL;
++
++	mf->field	= V4L2_FIELD_NONE;
++	mf->colorspace = V4L2_COLORSPACE_JPEG;
++
++	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
++		ov9281_set_params(client, &mf->width,
++					 &mf->height, mf->code);
++	if(cfg)
++		cfg->try_fmt = *mf;
++	return 0;
++}
++
++static int ov9281_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad || code->index >= ARRAY_SIZE(ov9281_supported_win_sizes))
++		return -EINVAL;
++
++	code->code = ov9281_supported_win_sizes[code->index].mbus_code;
++	return 0;
++}
++
++static int ov9281_enum_frame_size(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_frame_size_enum *fse)
++{
++	int i, j;
++	int num_valid = -1;
++	__u32 index = fse->index;
++
++	if(index >= N_WIN_SIZES)
++		return -EINVAL;
++
++#if 0
++	j = ARRAY_SIZE(ov9281_codes);
++	while(--j)
++		if(fse->code == ov9281_codes[j])
++			break;
++	for (i = 0; i < N_WIN_SIZES; i++) {
++		if (index == ++num_valid) {
++			fse->code = ov9281_codes[j];
++			fse->min_width = ov9281_supported_win_sizes[index].width;
++			fse->max_width = fse->min_width;
++			fse->min_height = ov9281_supported_win_sizes[index].height;
++			fse->max_height = fse->min_height;
++			return 0;
++		}
++	}
++
++	return -EINVAL;
++#endif
++	fse->code = ov9281_supported_win_sizes[index].mbus_code;
++	fse->min_width = ov9281_supported_win_sizes[index].width;
++	fse->max_width = fse->min_width;
++	fse->min_height = ov9281_supported_win_sizes[index].height;
++	fse->max_height = fse->min_height;
++	return 0;
++}
++#if 0
++static int ov9281_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
++{
++	a->c.left	= 0;
++	a->c.top	= 0;
++	a->c.width	= OV9281_DEFAULT_WIDTH;
++	a->c.height	= OV9281_DEFAULT_HEIGHT;
++	a->type		= V4L2_BUF_TYPE_VIDEO_CAPTURE;
++
++	return 0;
++}
++
++static int ov9281_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
++{
++	a->bounds.left			= 0;
++	a->bounds.top			= 0;
++	a->bounds.width			= OV9281_DEFAULT_WIDTH;
++	a->bounds.height		= OV9281_DEFAULT_HEIGHT;
++	a->defrect			= a->bounds;
++	a->type				= V4L2_BUF_TYPE_VIDEO_CAPTURE;
++	a->pixelaspect.numerator	= 1;
++	a->pixelaspect.denominator	= 1;
++
++	return 0;
++}
++#endif
++static int ov9281_video_probe(struct i2c_client *client)
++{
++	unsigned char retval_high = 0, retval_low = 0;
++	struct ov9281_priv *priv = to_ov9281(client);
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	int ret;
++
++	ret = ov9281_s_power(&priv->subdev, 1);
++	if (ret < 0)
++		return ret;
++	/*
++	 * check and show product ID and manufacturer ID
++	 */
++
++	retval_high = ov9281_read_reg(client, REG_CHIP_ID_HIGH);
++	if (retval_high != CHIP_ID_HIGH) {
++		dev_err(&client->dev, "read sensor %s chip_id high %x is error\n",
++				client->name, retval_high);
++		ret = -EINVAL;
++		goto done;
++	}
++
++
++	retval_low = ov9281_read_reg(client, REG_CHIP_ID_LOW);
++	if (retval_low != CHIP_ID_LOW) {
++		dev_err(&client->dev, "read sensor %s chip_id low %x is error\n",
++				client->name, retval_low);
++		ret = -EINVAL;
++		goto done;
++	}
++
++	dev_info(&client->dev, "read sensor %s id high:0x%x,low:%x successed!\n",
++			client->name, retval_high, retval_low);
++
++	ret = v4l2_ctrl_handler_setup(&priv->hdl);
++
++done:
++//	ov9281_s_power(&priv->subdev, 0);
++	return ret;
++}
++
++static int ov9281_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
++		struct v4l2_mbus_config *cfg)
++{
++/*
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
++
++	cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
++		V4L2_MBUS_VSYNC_ACTIVE_LOW | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
++		V4L2_MBUS_DATA_ACTIVE_HIGH;
++	cfg->type = V4L2_MBUS_PARALLEL;
++
++	cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
++*/
++	/*int dts*/
++	return 0;
++}
++
++static struct v4l2_subdev_core_ops ov9281_subdev_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register	= ov9281_g_register,
++	.s_register	= ov9281_s_register,
++#endif
++	.s_power	= ov9281_s_power,
++	//.querymenu	= ov9281_querymenu,
++};
++
++static struct v4l2_subdev_video_ops ov9281_subdev_video_ops = {
++	.s_stream	= ov9281_s_stream,
++//	.cropcap	= ov9281_cropcap,
++//	.g_crop		= ov9281_g_crop,
++//	.g_mbus_config	= ov9281_g_mbus_config,
++};
++
++static const struct v4l2_subdev_pad_ops ov9281_subdev_pad_ops = {
++	.enum_mbus_code = ov9281_enum_mbus_code,
++	.enum_frame_size = ov9281_enum_frame_size,
++	.get_fmt	= ov9281_get_fmt,
++	.set_fmt	= ov9281_set_fmt,
++	.get_mbus_config = ov9281_g_mbus_config,
++	.get_selection	= ov9281_get_selection,
++};
++
++static struct v4l2_subdev_ops ov9281_subdev_ops = {
++	.core	= &ov9281_subdev_core_ops,
++	.video	= &ov9281_subdev_video_ops,
++	.pad	= &ov9281_subdev_pad_ops,
++};
++
++static int ov9281_hw_reset(struct i2c_client *client)
++{
++	struct ov9281_priv *priv = to_ov9281(client);
++
++	if (priv->resetb_gpio) {
++		/* Active the resetb pin to perform a reset pulse */
++		gpiod_direction_output(priv->resetb_gpio, 1);
++		usleep_range(3000, 5000);
++		gpiod_direction_output(priv->resetb_gpio, 0);
++	}
++
++	return 0;
++}
++
++
++static int ov9281_probe_dt(struct i2c_client *client,
++		struct ov9281_priv *priv)
++{
++	struct v4l2_subdev_platform_data *sd_pdata = priv->sd_pdata;
++	struct device_node *np = client->dev.of_node;
++	int supplies = 0, index = 0;
++
++	supplies = of_property_count_strings(np, "supplies-name");
++	if(supplies > 0) {
++		sd_pdata = devm_kzalloc(&client->dev, sizeof(struct v4l2_subdev_platform_data), GFP_KERNEL);
++		sd_pdata->num_regulators = supplies;
++		sd_pdata->regulators = devm_kzalloc(&client->dev, supplies * sizeof(struct regulator_bulk_data), GFP_KERNEL);
++		if(!sd_pdata->regulators) {
++			dev_err(&client->dev, "Failed to allocate regulators.!\n");
++			devm_kfree(&client->dev,sd_pdata);
++			return -ENOMEM;
++		}
++
++		for(index = 0; index < sd_pdata->num_regulators; index ++) {
++			of_property_read_string_index(np, "supplies-name", index,
++					&(sd_pdata->regulators[index].supply));
++
++			dev_dbg(&client->dev, "sd_pdata->regulators[%d].supply: %s\n",
++					index, sd_pdata->regulators[index].supply);
++		}
++
++		devm_regulator_bulk_get(&client->dev, sd_pdata->num_regulators, sd_pdata->regulators);
++//	soc_camera_power_init(&client->dev, ssdd_dt);
++	} else {
++		/* Request the power down GPIO asserted */
++		priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn",
++				GPIOD_OUT_HIGH);
++		if (!priv->pwdn_gpio)
++			dev_dbg(&client->dev, "pwdn gpio is not assigned!\n");
++		else if	(IS_ERR(priv->pwdn_gpio))
++			return PTR_ERR(priv->pwdn_gpio);
++
++		/* Request the power down GPIO asserted */
++		priv->vcc_en_gpio = devm_gpiod_get_optional(&client->dev, "vcc-en",
++				GPIOD_OUT_HIGH);
++		if (!priv->vcc_en_gpio)
++			dev_dbg(&client->dev, "vcc_en gpio is not assigned!\n");
++		else if (IS_ERR(priv->vcc_en_gpio))
++			return PTR_ERR(priv->vcc_en_gpio);
++
++		/* Initialize the soc_camera_subdev_desc */
++		priv->power = ov9281_hw_power;
++		priv->reset = ov9281_hw_reset;
++	}
++	return 0;
++}
++
++#include <linux/regulator/consumer.h>
++/*
++ * i2c_driver functions
++ */
++static int ov9281_probe(struct i2c_client *client,
++			const struct i2c_device_id *did)
++{
++	struct ov9281_priv	*priv;
++	struct i2c_adapter	*adapter = to_i2c_adapter(client->dev.parent);
++	int	ret;
++
++	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA)) {
++		dev_err(&adapter->dev,
++			"ov9281: I2C-Adapter doesn't support SMBUS\n");
++		return -EIO;
++	}
++
++	priv = devm_kzalloc(&client->dev, sizeof(struct ov9281_priv), GFP_KERNEL);
++	if (!priv) {
++		dev_err(&adapter->dev,
++			"Failed to allocate memory for private data!\n");
++		return -ENOMEM;
++	}
++
++	priv->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(priv->clk))
++		return -EPROBE_DEFER;
++
++	v4l2_clk_set_rate(priv->clk, 24000000);
++/**
++	if (!ssdd && !client->dev.of_node) {
++		dev_err(&client->dev, "Missing platform_data for driver\n");
++		ret = -EINVAL;
++		goto err_videoprobe;
++	}
++
++	if (!ssdd) {
++		ret = ov9281_probe_dt(client, priv);
++		if (ret)
++			goto err_clk;
++	}
++*/
++	ret = ov9281_probe_dt(client, priv);
++	if (ret)
++		goto err_probe_dt;
++
++	v4l2_i2c_subdev_init(&priv->subdev, client, &ov9281_subdev_ops);
++
++	/* add handler */
++	v4l2_ctrl_handler_init(&priv->hdl, 2);
++	v4l2_ctrl_new_std(&priv->hdl, &ov9281_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&priv->hdl, &ov9281_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	priv->subdev.ctrl_handler = &priv->hdl;
++	if (priv->hdl.error) {
++		ret = priv->hdl.error;
++		goto err_hdl;
++	}
++
++	ret = ov9281_video_probe(client);
++	if (ret < 0)
++		goto err_detect;
++
++	ret = v4l2_async_register_subdev(&priv->subdev);
++	if (ret < 0)
++		goto err_async_register_subdev;
++
++	dev_info(&adapter->dev, "ov9281 DVP snapshot Probed\n");
++
++	return 0;
++
++err_async_register_subdev:
++err_detect:
++	v4l2_ctrl_handler_free(&priv->hdl);
++err_hdl:
++	v4l2_device_unregister_subdev(&priv->subdev);
++err_probe_dt:
++	v4l2_clk_put(priv->clk);
++	devm_kfree(&client->dev, priv);
++	return ret;
++}
++
++static int ov9281_remove(struct i2c_client *client)
++{
++	struct ov9281_priv       *priv = to_ov9281(client);
++
++	v4l2_async_unregister_subdev(&priv->subdev);
++	v4l2_clk_put(priv->clk);
++	v4l2_device_unregister_subdev(&priv->subdev);
++	v4l2_ctrl_handler_free(&priv->hdl);
++	devm_kfree(&client->dev, priv);
++	return 0;
++}
++
++static const struct i2c_device_id ov9281_id[] = {
++	{ "ov9281",  0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ov9281_id);
++static const struct of_device_id ov9281_of_match[] = {
++	{.compatible = "ovti,ov9281", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov9281_of_match);
++static struct i2c_driver ov9281_i2c_driver = {
++	.driver = {
++		.name = "ov9281",
++		.of_match_table = of_match_ptr(ov9281_of_match),
++	},
++	.probe    = ov9281_probe,
++	.remove   = ov9281_remove,
++	.id_table = ov9281_id,
++};
++module_i2c_driver(ov9281_i2c_driver);
++
++MODULE_DESCRIPTION("SoC Camera driver for Omni Vision ov9281 sensor");
++MODULE_AUTHOR("Alberto Panizzo");
++MODULE_LICENSE("GPL v2");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-cim/ov9281.c b/module_drivers/drivers/media/i2c/ingenic-cim/ov9281.c
+new file mode 100644
+index 000000000..cf69ea8fa
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-cim/ov9281.c
+@@ -0,0 +1,1068 @@
++/*
++ * ov9281 Camera Driver
++ *
++ * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com>
++ *
++ * Based on ov772x, ov9640 drivers and previous non merged implementations.
++ *
++ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright (C) 2006, OmniVision
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/i2c.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/gpio/consumer.h>
++#include <linux/of_gpio.h>
++#include <linux/v4l2-mediabus.h>
++#include <linux/videodev2.h>
++
++#include <media/v4l2-clk.h>
++#include <media/v4l2-subdev.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-image-sizes.h>
++#include <media/v4l2-device.h>
++
++#include <linux/clk.h>
++#include <linux/regulator/consumer.h>
++
++#define REG_CHIP_ID_HIGH	0x300a
++#define REG_CHIP_ID_LOW		0x300b
++#define CHIP_ID_HIGH		0x92
++#define CHIP_ID_LOW		0x81
++
++#define  OV9281_DEFAULT_WIDTH    1280
++#define  OV9281_DEFAULT_HEIGHT   720
++
++/* Private v4l2 controls */
++#define V4L2_CID_PRIVATE_BALANCE  (V4L2_CID_PRIVATE_BASE + 0)
++#define V4L2_CID_PRIVATE_EFFECT  (V4L2_CID_PRIVATE_BASE + 1)
++
++#define REG_TC_VFLIP			0x3820
++#define REG_TC_MIRROR			0x3821
++#define OV9281_FLIP_VAL			((unsigned char)0x04)
++#define OV9281_FLIP_MASK		((unsigned char)0x04)
++
++/* whether sensor support high resolution (> vga) preview or not */
++#define SUPPORT_HIGH_RESOLUTION_PRE		1
++
++/*
++ * Struct
++ */
++struct regval_list {
++	u16 reg_num;
++	u16 value;
++};
++
++struct mode_list {
++	u16 index;
++	const struct regval_list *mode_regs;
++};
++
++/* Supported resolutions */
++enum ov9281_width {
++	W_720P	= OV9281_DEFAULT_WIDTH,
++};
++
++enum ov9281_height {
++	H_720P	= OV9281_DEFAULT_HEIGHT,
++};
++
++struct ov9281_win_size {
++	char *name;
++	enum ov9281_width width;
++	enum ov9281_height height;
++	const struct regval_list *regs;
++	unsigned int mbus_code;
++};
++
++struct ov9281_priv {
++	struct v4l2_subdev		subdev;
++	struct v4l2_ctrl_handler	hdl;
++	u32	cfmt_code;
++	struct v4l2_clk			*clk;
++	const struct ov9281_win_size	*win;
++
++	int				model;
++	u16				balance_value;
++	u16				effect_value;
++	u16				flag_vflip:1;
++	u16				flag_hflip:1;
++
++	struct v4l2_subdev_platform_data *sd_pdata;
++	struct gpio_desc *resetb_gpio;
++	struct gpio_desc *pwdn_gpio;
++	struct gpio_desc *vcc_en_gpio;
++
++	int (*power)(struct i2c_client *client, int on);
++	int (*reset)(struct i2c_client *client);
++
++	struct regulator *reg;
++	struct regulator *reg1;
++};
++
++static inline int sensor_i2c_master_send(struct i2c_client *client,
++		const char *buf ,int count)
++{
++	int ret;
++	struct i2c_adapter *adap=client->adapter;
++	struct i2c_msg msg;
++
++	msg.addr = client->addr;
++	msg.flags = client->flags & I2C_M_TEN;
++	msg.len = count;
++	msg.buf = (char *)buf;
++
++	ret = i2c_transfer(adap, &msg, 1);
++
++	return (ret == 1) ? count : ret;
++}
++
++static inline int sensor_i2c_master_recv(struct i2c_client *client,
++		char *buf ,int count)
++{
++	struct i2c_adapter *adap=client->adapter;
++	struct i2c_msg msg;
++	int ret;
++
++	msg.addr = client->addr;
++	msg.flags = client->flags & I2C_M_TEN;
++	msg.flags |= I2C_M_RD;
++	msg.len = count;
++	msg.buf = buf;
++	ret = i2c_transfer(adap, &msg, 1);
++
++	return (ret == 1) ? count : ret;
++}
++
++
++unsigned char ov9281_read_reg(struct i2c_client *client, u16 reg)
++{
++	int ret;
++	unsigned char retval;
++	unsigned short r = cpu_to_be16(reg);
++
++	ret = sensor_i2c_master_send(client,(u8 *)&r,2);
++
++	if (ret < 0)
++		return ret;
++	if (ret != 2)
++		return -EIO;
++
++	ret = sensor_i2c_master_recv(client, &retval, 1);
++	if (ret < 0)
++		return ret;
++	if (ret != 1)
++		return -EIO;
++	return retval;
++}
++
++int ov9281_write_reg(struct i2c_client *client, u16 reg, u8 val)
++{
++	unsigned char msg[3];
++	int ret;
++
++	reg = cpu_to_be16(reg);
++
++	memcpy(&msg[0], &reg, 2);
++	memcpy(&msg[2], &val, 1);
++
++	ret = sensor_i2c_master_send(client, msg, 3);
++
++	if (ret < 0)
++	{
++		printk("RET<0\n");
++		return ret;
++	}
++	if (ret < 3)
++	{
++		printk("RET<3\n");
++		return -EIO;
++	}
++
++	return 0;
++}
++
++/*
++ * Registers settings
++ */
++
++#define ENDMARKER { 0xffff, 0xff }
++
++static const struct regval_list ov9281_init_regs[] = {
++	{ 0x0103, 0x01},
++	{ 0x0302, 0x32},
++	{ 0x030d, 0x50},
++	{ 0x030e, 0x02},
++	{ 0x3001, 0x00},
++	{ 0x3004, 0x00},
++	{ 0x3005, 0x00},
++	{ 0x3006, 0x04},
++	{ 0x3011, 0x0a},
++	{ 0x3013, 0x18},
++	{ 0x3022, 0x01},
++	{ 0x3030, 0x10},
++	{ 0x3039, 0x32},
++	{ 0x303a, 0x00},
++	{ 0x3500, 0x00},
++	{ 0x3501, 0x2a},
++	{ 0x3502, 0x90},
++	{ 0x3503, 0x08},
++	{ 0x3505, 0x8c},
++	{ 0x3507, 0x03},
++	{ 0x3508, 0x00},
++	{ 0x3509, 0x10},
++	{ 0x3610, 0x80},
++	{ 0x3611, 0xa0},
++	{ 0x3620, 0x6f},
++	{ 0x3632, 0x56},
++	{ 0x3633, 0x78},
++	{ 0x3662, 0x03}, /* 1 lane raw8 */
++	{ 0x3666, 0x00},
++	{ 0x366f, 0x5a},
++	{ 0x3680, 0x84},
++	{ 0x3712, 0x80},
++	{ 0x372d, 0x22},
++	{ 0x3731, 0x80},
++	{ 0x3732, 0x30},
++	{ 0x3778, 0x00},
++	{ 0x377d, 0x22},
++	{ 0x3788, 0x02},
++	{ 0x3789, 0xa4},
++	{ 0x378a, 0x00},
++	{ 0x378b, 0x4a},
++	{ 0x3799, 0x20},
++	{ 0x3800, 0x00},
++	{ 0x3801, 0x00},
++	{ 0x3802, 0x00},
++	{ 0x3803, 0x00},
++	{ 0x3804, 0x05},
++	{ 0x3805, 0x0f},
++	{ 0x3806, 0x03},
++	{ 0x3807, 0x2f},
++	{ 0x3808, 0x05},
++	{ 0x3809, 0x00},
++	{ 0x380a, 0x02},
++	{ 0x380b, 0xd0},
++#if 0 /* 30 fps */
++	{ 0x380c, 0x05}, /* hsync */
++	{ 0x380d, 0xd8},
++	{ 0x380e, 0x06}, /* vsync */
++	{ 0x380f, 0x8e},
++#endif
++#if 1 /* 45 fps */
++	{ 0x380c, 0x05}, /* hsync */
++	{ 0x380d, 0xd8},
++	{ 0x380e, 0x04}, /* vsync */
++	{ 0x380f, 0x8e},
++#endif
++#if 0 /* 60 fps */
++	{ 0x380c, 0x04}, /* hsync */
++	{ 0x380d, 0xd8},
++	{ 0x380e, 0x03}, /* vsync */
++	{ 0x380f, 0x8e},
++#endif
++	{ 0x3810, 0x00},
++	{ 0x3811, 0x08},
++	{ 0x3812, 0x00},
++	{ 0x3813, 0x08},
++	{ 0x3814, 0x11},
++	{ 0x3815, 0x11},
++	{ 0x3820, 0x40},
++	{ 0x3821, 0x00},
++	{ 0x3881, 0x42},
++	{ 0x38b1, 0x00},
++	{ 0x3920, 0xff},
++	{ 0x4003, 0x40},
++	{ 0x4008, 0x04},
++	{ 0x4009, 0x0b},
++	{ 0x400c, 0x00},
++	{ 0x400d, 0x07},
++	{ 0x4010, 0x40},
++	{ 0x4043, 0x40},
++	{ 0x4307, 0x30},
++	{ 0x4317, 0x00},
++	{ 0x4501, 0x00},
++	{ 0x4507, 0x00},
++	{ 0x4509, 0x00},
++	{ 0x450a, 0x08},
++	{ 0x4601, 0x04},
++	{ 0x470f, 0x00},
++	{ 0x4f07, 0x00},
++	{ 0x4800, 0x00},
++	{ 0x5000, 0x9f},
++	{ 0x5001, 0x00},
++	{ 0x5e00, 0x00},
++	{ 0x5d00, 0x07},
++	{ 0x5d01, 0x00},
++//	{ 0x0100, 0x00},
++
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_wb_auto_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_wb_incandescence_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_wb_daylight_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_wb_fluorescent_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_wb_cloud_regs[] = {
++	ENDMARKER,
++};
++
++static const struct mode_list ov9281_balance[] = {
++	{0, ov9281_wb_auto_regs}, {1, ov9281_wb_incandescence_regs},
++	{2, ov9281_wb_daylight_regs}, {3, ov9281_wb_fluorescent_regs},
++	{4, ov9281_wb_cloud_regs},
++};
++
++
++static const struct regval_list ov9281_effect_normal_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_effect_grayscale_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_effect_sepia_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_effect_colorinv_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list ov9281_effect_sepiabluel_regs[] = {
++	ENDMARKER,
++};
++
++static const struct mode_list ov9281_effect[] = {
++	{0, ov9281_effect_normal_regs}, {1, ov9281_effect_grayscale_regs},
++	{2, ov9281_effect_sepia_regs}, {3, ov9281_effect_colorinv_regs},
++	{4, ov9281_effect_sepiabluel_regs},
++};
++
++static const struct regval_list ov9281_720p_regs[] = {
++	ENDMARKER,
++};
++
++#define OV9281_SIZE(n, w, h, r, c) \
++	{.name = n, .width = w , .height = h, .regs = r, .mbus_code = c }
++
++static struct ov9281_win_size ov9281_supported_win_sizes[] = {
++	OV9281_SIZE("720P", W_720P, H_720P, ov9281_720p_regs, MEDIA_BUS_FMT_Y8_1X8),
++};
++
++#define N_WIN_SIZES (ARRAY_SIZE(ov9281_supported_win_sizes))
++
++/*
++ * Supported balance menus
++ */
++static const struct v4l2_querymenu ov9281_balance_menus[] = {
++	{
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 0,
++		.name		= "auto",
++	}, {
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 1,
++		.name		= "incandescent",
++	}, {
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 2,
++		.name		= "fluorescent",
++	},  {
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 3,
++		.name		= "daylight",
++	},  {
++		.id		= V4L2_CID_PRIVATE_BALANCE,
++		.index		= 4,
++		.name		= "cloudy-daylight",
++	},
++
++};
++
++/*
++ * Supported effect menus
++ */
++static const struct v4l2_querymenu ov9281_effect_menus[] = {
++	{
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 0,
++		.name		= "none",
++	}, {
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 1,
++		.name		= "mono",
++	}, {
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 2,
++		.name		= "sepia",
++	},  {
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 3,
++		.name		= "negative",
++	}, {
++		.id		= V4L2_CID_PRIVATE_EFFECT,
++		.index		= 4,
++		.name		= "aqua",
++	},
++};
++
++
++/*
++ * General functions
++ */
++static struct ov9281_priv *to_ov9281(const struct i2c_client *client)
++{
++	return container_of(i2c_get_clientdata(client), struct ov9281_priv,
++			    subdev);
++}
++
++static int ov9281_write_array(struct i2c_client *client,
++			      const struct regval_list *vals)
++{
++	int ret;
++
++	while ((vals->reg_num != 0xffff) || (vals->value != 0xff)) {
++		ret = ov9281_write_reg(client, vals->reg_num, vals->value);
++		dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x",
++			 vals->reg_num, vals->value);
++
++		if (ret < 0)
++			return ret;
++		vals++;
++	}
++	return 0;
++}
++
++static int ov9281_mask_set(struct i2c_client *client,
++			   u16  reg, u16  mask, u16  set)
++{
++	s32 val = ov9281_read_reg(client, reg);
++	if (val < 0)
++		return val;
++
++	val &= ~mask;
++	val |= set & mask;
++
++	dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val);
++
++	return ov9281_write_reg(client, reg, val);
++}
++
++/* OF probe functions */
++static int ov9281_hw_power(struct i2c_client *client, int on)
++{
++	struct ov9281_priv *priv = to_ov9281(client);
++
++	dev_dbg(&client->dev, "%s: %s the camera\n",
++			__func__, on ? "ENABLE" : "DISABLE");
++
++	/* thses gpio should be set according to the active level in dt defines */
++
++	if(priv->vcc_en_gpio) {
++		gpiod_direction_output(priv->vcc_en_gpio, on);
++	}
++
++	if (priv->pwdn_gpio) {
++		gpiod_direction_output(priv->pwdn_gpio, on);
++	}
++
++	msleep(10);
++	return 0;
++}
++
++static int ov9281_reset(struct i2c_client *client)
++{
++	struct ov9281_priv *priv = to_ov9281(client);
++
++	if(priv->resetb_gpio) {
++		gpiod_direction_output(priv->resetb_gpio, 1);
++		msleep(10);
++		gpiod_direction_output(priv->resetb_gpio, 0);
++		msleep(10);
++	}
++
++	return 0;
++}
++
++static int ov9281_g_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd =
++		&container_of(ctrl->handler, struct ov9281_priv, hdl)->subdev;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov9281_priv *priv = to_ov9281(client);
++
++	switch (ctrl->id) {
++	case V4L2_CID_VFLIP:
++		ctrl->val = priv->flag_vflip;
++		break;
++	case V4L2_CID_HFLIP:
++		ctrl->val = priv->flag_hflip;
++		break;
++	case V4L2_CID_PRIVATE_BALANCE:
++		ctrl->val = priv->balance_value;
++		break;
++	case V4L2_CID_PRIVATE_EFFECT:
++		ctrl->val = priv->effect_value;
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++static int ov9281_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd =
++		&container_of(ctrl->handler, struct ov9281_priv, hdl)->subdev;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov9281_priv *priv = to_ov9281(client);
++	int ret = 0;
++	int i = 0;
++	u16 value;
++
++	int balance_count = ARRAY_SIZE(ov9281_balance);
++	int effect_count = ARRAY_SIZE(ov9281_effect);
++
++	switch (ctrl->id) {
++	case V4L2_CID_PRIVATE_BALANCE:
++		if(ctrl->val > balance_count)
++			return -EINVAL;
++
++		for(i = 0; i < balance_count; i++) {
++			if(ctrl->val == ov9281_balance[i].index) {
++				ret = ov9281_write_array(client,
++						ov9281_balance[ctrl->val].mode_regs);
++				priv->balance_value = ctrl->val;
++				break;
++			}
++		}
++		break;
++
++	case V4L2_CID_PRIVATE_EFFECT:
++		if(ctrl->val > effect_count)
++			return -EINVAL;
++
++		for(i = 0; i < effect_count; i++) {
++			if(ctrl->val == ov9281_effect[i].index) {
++				ret = ov9281_write_array(client,
++						ov9281_effect[ctrl->val].mode_regs);
++				priv->effect_value = ctrl->val;
++				break;
++			}
++		}
++		break;
++
++	case V4L2_CID_VFLIP:
++		value = ctrl->val ? OV9281_FLIP_VAL : 0x00;
++		priv->flag_vflip = ctrl->val ? 1 : 0;
++		ret = ov9281_mask_set(client, REG_TC_VFLIP, OV9281_FLIP_MASK, value);
++		break;
++
++	case V4L2_CID_HFLIP:
++		value = ctrl->val ? OV9281_FLIP_VAL : 0x00;
++		priv->flag_hflip = ctrl->val ? 1 : 0;
++		ret = ov9281_mask_set(client, REG_TC_MIRROR, OV9281_FLIP_MASK, value);
++		break;
++
++	default:
++		dev_err(&client->dev, "no V4L2 CID: 0x%x ", ctrl->id);
++		return -EINVAL;
++	}
++	return ret;
++}
++
++static const struct v4l2_ctrl_ops ov9281_ctrl_ops = {
++	.s_ctrl = ov9281_s_ctrl,
++	.g_volatile_ctrl = ov9281_g_ctrl,
++};
++
++static int ov9281_s_power(struct v4l2_subdev *sd, int on)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct ov9281_priv *priv = to_ov9281(client);
++
++	if(priv->sd_pdata) {
++		if(on)
++			return regulator_bulk_enable(priv->sd_pdata->num_regulators,priv->sd_pdata->regulators);
++		else
++			return regulator_bulk_disable(priv->sd_pdata->num_regulators,priv->sd_pdata->regulators);
++	} else if(priv->power){
++		return priv->power(client, on);
++	} else {
++		dev_err(&client->dev, "ov9281_s_power failde");
++		return -EINVAL;
++	}
++}
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ov9281_g_register(struct v4l2_subdev *sd,
++			     struct v4l2_dbg_register *reg)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	int ret;
++
++	reg->size = 1;
++	if (reg->reg > 0xff)
++		return -EINVAL;
++
++	ret = ov9281_read_reg(client, reg->reg);
++	if (ret < 0)
++		return ret;
++
++	reg->val = ret;
++
++	return 0;
++}
++
++static int ov9281_s_register(struct v4l2_subdev *sd,
++			     const struct v4l2_dbg_register *reg)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++
++	if (reg->reg > 0xff ||
++	    reg->val > 0xff)
++		return -EINVAL;
++
++	return ov9281_write_reg(client, reg->reg, reg->val);
++}
++#endif
++
++/*
++ * soc_camera_ops functions
++ */
++static int ov9281_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++
++	if (!enable ) {
++		dev_info(&client->dev, "stream down\n");
++		ov9281_write_reg(client, 0x0100, 0x00);
++		return 0;
++	}
++
++	dev_info(&client->dev, "stream on\n");
++	ov9281_write_reg(client, 0x0100, 0x01);
++
++	return 0;
++}
++
++/* Select the nearest higher resolution for capture */
++static const struct ov9281_win_size *ov9281_select_win(u32 *code, u32 *width, u32 *height)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(ov9281_supported_win_sizes); i++) {
++		if ((*width >= ov9281_supported_win_sizes[i].width) &&
++		    (*height >= ov9281_supported_win_sizes[i].height) &&
++		    (*code == ov9281_supported_win_sizes[i].mbus_code)) {
++			*width = ov9281_supported_win_sizes[i].width;
++			*height = ov9281_supported_win_sizes[i].height;
++			return &ov9281_supported_win_sizes[i];
++		}
++	}
++
++	return NULL;
++}
++
++static int ov9281_get_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct ov9281_priv *priv = to_ov9281(client);
++
++	if (format->pad)
++		return -EINVAL;
++	if(priv->win) {
++		mf->width = priv->win->width;
++		mf->height = priv->win->height;
++	} else {
++		mf->width = OV9281_DEFAULT_WIDTH;
++		mf->height = OV9281_DEFAULT_HEIGHT;
++	}
++	mf->code = priv->cfmt_code;
++
++	mf->colorspace = V4L2_COLORSPACE_JPEG;
++	mf->field	= V4L2_FIELD_NONE;
++
++	return 0;
++}
++
++static int ov9281_set_params(struct i2c_client *client, u32 *width, u32 *height, u32 code)
++{
++	struct ov9281_priv       *priv = to_ov9281(client);
++	int ret;
++
++	int bala_index = priv->balance_value;
++	int effe_index = priv->effect_value;
++
++	/* select win */
++	priv->win = ov9281_select_win(&code, width, height);
++
++	/* select format */
++	priv->cfmt_code = 0;
++
++	/* reset hardware */
++	ov9281_reset(client);
++
++	/* initialize the sensor with default data */
++	dev_dbg(&client->dev, "%s: Init default", __func__);
++	ret = ov9281_write_array(client, ov9281_init_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set balance */
++	ret = ov9281_write_array(client, ov9281_balance[bala_index].mode_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set effect */
++	ret = ov9281_write_array(client, ov9281_effect[effe_index].mode_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set size win */
++	ret = ov9281_write_array(client, priv->win->regs);
++	if (ret < 0)
++		goto err;
++
++	priv->cfmt_code = code;
++	*width = priv->win->width;
++	*height = priv->win->height;
++
++	return 0;
++
++err:
++	dev_err(&client->dev, "%s: Error %d", __func__, ret);
++	ov9281_reset(client);
++	priv->win = NULL;
++
++	return ret;
++}
++
++static int ov9281_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct ov9281_priv *priv = to_ov9281(client);
++
++	if (format->pad)
++		return -EINVAL;
++
++	/*
++	 * select suitable win, but don't store it
++	 */
++	priv->win = ov9281_select_win(&mf->code, &mf->width, &mf->height);
++	if(!priv->win)
++		return -EINVAL;
++
++	mf->field	= V4L2_FIELD_NONE;
++	mf->colorspace = V4L2_COLORSPACE_JPEG;
++
++	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
++		ov9281_set_params(client, &mf->width,
++					 &mf->height, mf->code);
++	if(cfg)
++		cfg->try_fmt = *mf;
++	return 0;
++}
++
++static int ov9281_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad || code->index >= ARRAY_SIZE(ov9281_supported_win_sizes))
++		return -EINVAL;
++
++	code->code = ov9281_supported_win_sizes[code->index].mbus_code;
++	return 0;
++}
++
++static int ov9281_enum_frame_size(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_frame_size_enum *fse)
++{
++	__u32 index = fse->index;
++
++	if(index >= N_WIN_SIZES)
++		return -EINVAL;
++
++	fse->code = ov9281_supported_win_sizes[index].mbus_code;
++	fse->min_width = ov9281_supported_win_sizes[index].width;
++	fse->max_width = fse->min_width;
++	fse->min_height = ov9281_supported_win_sizes[index].height;
++	fse->max_height = fse->min_height;
++	return 0;
++
++}
++
++static int ov9281_video_probe(struct i2c_client *client)
++{
++	unsigned char retval_high = 0, retval_low = 0;
++	struct ov9281_priv *priv = to_ov9281(client);
++	int ret;
++
++	ret = ov9281_s_power(&priv->subdev, 1);
++	if (ret < 0)
++		return ret;
++	/*
++	 * check and show product ID and manufacturer ID
++	 */
++	retval_high = ov9281_read_reg(client, REG_CHIP_ID_HIGH);
++	if (retval_high != CHIP_ID_HIGH) {
++		dev_err(&client->dev, "read sensor %s chip_id high %x is error\n",
++				client->name, retval_high);
++		ret = -EINVAL;
++		goto done;
++	}
++
++
++	retval_low = ov9281_read_reg(client, REG_CHIP_ID_LOW);
++	if (retval_low != CHIP_ID_LOW) {
++		dev_err(&client->dev, "read sensor %s chip_id low %x is error\n",
++				client->name, retval_low);
++		ret = -EINVAL;
++		goto done;
++	}
++
++	dev_info(&client->dev, "read sensor %s id high:0x%x,low:%x successed!\n",
++			client->name, retval_high, retval_low);
++
++done:
++	return ret;
++}
++
++static int ov9281_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
++		struct v4l2_mbus_config *cfg)
++{
++	/*int dts*/
++	return 0;
++}
++
++static struct v4l2_subdev_core_ops ov9281_subdev_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register	= ov9281_g_register,
++	.s_register	= ov9281_s_register,
++#endif
++	.s_power	= ov9281_s_power,
++};
++
++static struct v4l2_subdev_video_ops ov9281_subdev_video_ops = {
++	.s_stream	= ov9281_s_stream,
++};
++
++static const struct v4l2_subdev_pad_ops ov9281_subdev_pad_ops = {
++	.enum_mbus_code = ov9281_enum_mbus_code,
++	.enum_frame_size = ov9281_enum_frame_size,
++	.get_fmt	= ov9281_get_fmt,
++	.set_fmt	= ov9281_set_fmt,
++	.get_mbus_config = ov9281_g_mbus_config,
++};
++
++static struct v4l2_subdev_ops ov9281_subdev_ops = {
++	.core	= &ov9281_subdev_core_ops,
++	.video	= &ov9281_subdev_video_ops,
++	.pad	= &ov9281_subdev_pad_ops,
++};
++
++static int ov9281_hw_reset(struct i2c_client *client)
++{
++	struct ov9281_priv *priv = to_ov9281(client);
++
++	if (priv->resetb_gpio) {
++		/* Active the resetb pin to perform a reset pulse */
++		gpiod_direction_output(priv->resetb_gpio, 1);
++		usleep_range(3000, 5000);
++		gpiod_direction_output(priv->resetb_gpio, 0);
++	}
++
++	return 0;
++}
++
++static int ov9281_probe_dt(struct i2c_client *client,
++		struct ov9281_priv *priv)
++{
++
++	struct v4l2_subdev_platform_data *sd_pdata = priv->sd_pdata;
++	struct device_node *np = client->dev.of_node;
++	int supplies = 0, index = 0;
++
++	supplies = of_property_count_strings(np, "supplies-name");
++	if(supplies > 0) {
++		sd_pdata = devm_kzalloc(&client->dev, sizeof(struct v4l2_subdev_platform_data), GFP_KERNEL);
++		sd_pdata->num_regulators = supplies;
++		sd_pdata->regulators = devm_kzalloc(&client->dev, supplies * sizeof(struct regulator_bulk_data), GFP_KERNEL);
++		if(!sd_pdata->regulators) {
++			dev_err(&client->dev, "Failed to allocate regulators.!\n");
++			devm_kfree(&client->dev,sd_pdata);
++			return -ENOMEM;
++		}
++
++		for(index = 0; index < sd_pdata->num_regulators; index ++) {
++			of_property_read_string_index(np, "supplies-name", index,
++					&(sd_pdata->regulators[index].supply));
++
++			dev_dbg(&client->dev, "sd_pdata->regulators[%d].supply: %s\n",
++					index, sd_pdata->regulators[index].supply);
++		}
++
++		devm_regulator_bulk_get(&client->dev, sd_pdata->num_regulators, sd_pdata->regulators);
++
++	} else {
++		/* Request the power down GPIO asserted */
++		priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn",
++				GPIOD_OUT_HIGH);
++		if (!priv->pwdn_gpio)
++			dev_dbg(&client->dev, "pwdn gpio is not assigned!\n");
++		else if (IS_ERR(priv->pwdn_gpio))
++			return PTR_ERR(priv->pwdn_gpio);
++
++		/* Request the power down GPIO asserted */
++		priv->vcc_en_gpio = devm_gpiod_get_optional(&client->dev, "vcc-en",
++				GPIOD_OUT_HIGH);
++		if (!priv->vcc_en_gpio)
++			dev_dbg(&client->dev, "vcc_en gpio is not assigned!\n");
++		else if (IS_ERR(priv->vcc_en_gpio))
++			return PTR_ERR(priv->vcc_en_gpio);
++
++		/* Initialize the soc_camera_subdev_desc */
++		priv->power = ov9281_hw_power;
++		priv->reset = ov9281_hw_reset;
++	}
++	return 0;
++}
++
++#include <linux/regulator/consumer.h>
++/*
++ * i2c_driver functions
++ */
++static int ov9281_probe(struct i2c_client *client,
++			const struct i2c_device_id *did)
++{
++	struct ov9281_priv	*priv;
++	struct i2c_adapter	*adapter = to_i2c_adapter(client->dev.parent);
++	int	ret;
++
++	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA)) {
++		dev_err(&adapter->dev,
++			"ov9281: I2C-Adapter doesn't support SMBUS\n");
++		return -EIO;
++	}
++
++	priv = devm_kzalloc(&client->dev, sizeof(struct ov9281_priv), GFP_KERNEL);
++	if (!priv) {
++		dev_err(&adapter->dev,
++			"Failed to allocate memory for private data!\n");
++		return -ENOMEM;
++	}
++
++	priv->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(priv->clk))
++		return -EPROBE_DEFER;
++
++	v4l2_clk_set_rate(priv->clk, 24000000);
++
++	ret = ov9281_probe_dt(client, priv);
++	if (ret)
++		goto err_probe_dt;
++
++	v4l2_i2c_subdev_init(&priv->subdev, client, &ov9281_subdev_ops);
++
++	/* add handler */
++	v4l2_ctrl_handler_init(&priv->hdl, 2);
++	v4l2_ctrl_new_std(&priv->hdl, &ov9281_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&priv->hdl, &ov9281_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	priv->subdev.ctrl_handler = &priv->hdl;
++	if (priv->hdl.error) {
++		ret = priv->hdl.error;
++		goto err_hdl;
++	}
++
++	ret = ov9281_video_probe(client);
++	if (ret < 0)
++		goto err_detect;
++
++	ret = v4l2_ctrl_handler_setup(&priv->hdl);
++
++	ret = v4l2_async_register_subdev(&priv->subdev);
++	if (ret < 0)
++		goto err_async_register_subdev;
++
++	dev_info(&adapter->dev, "ov9281 Probed\n");
++
++	return 0;
++
++err_async_register_subdev:
++err_detect:
++	v4l2_ctrl_handler_free(&priv->hdl);
++err_hdl:
++	v4l2_device_unregister_subdev(&priv->subdev);
++err_probe_dt:
++	v4l2_clk_put(priv->clk);
++	devm_kfree(&client->dev, priv);
++	return ret;
++}
++
++static int ov9281_remove(struct i2c_client *client)
++{
++	struct ov9281_priv       *priv = to_ov9281(client);
++
++	v4l2_async_unregister_subdev(&priv->subdev);
++	v4l2_clk_put(priv->clk);
++	v4l2_device_unregister_subdev(&priv->subdev);
++	v4l2_ctrl_handler_free(&priv->hdl);
++	devm_kfree(&client->dev, priv);
++	return 0;
++}
++
++static const struct i2c_device_id ov9281_id[] = {
++	{ "ov9281",  0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ov9281_id);
++static const struct of_device_id ov9281_of_match[] = {
++	{.compatible = "ovti,ov9281", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov9281_of_match);
++static struct i2c_driver ov9281_i2c_driver = {
++	.driver = {
++		.name = "ov9281",
++		.of_match_table = of_match_ptr(ov9281_of_match),
++	},
++	.probe    = ov9281_probe,
++	.remove   = ov9281_remove,
++	.id_table = ov9281_id,
++};
++module_i2c_driver(ov9281_i2c_driver);
++
++MODULE_DESCRIPTION("SoC Camera driver for Omni Vision ov9281 sensor");
++MODULE_AUTHOR("Alberto Panizzo");
++MODULE_LICENSE("GPL v2");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-cim/sc031gs-mipi.c b/module_drivers/drivers/media/i2c/ingenic-cim/sc031gs-mipi.c
+new file mode 100644
+index 000000000..35cabb31f
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-cim/sc031gs-mipi.c
+@@ -0,0 +1,919 @@
++/*
++ * sc031gs Camera Driver
++ *
++ * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com>
++ *
++ * Based on ov772x, ov9640 drivers and previous non merged implementations.
++ *
++ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright (C) 2006, OmniVision
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/i2c.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/gpio/consumer.h>
++#include <linux/of_gpio.h>
++#include <linux/v4l2-mediabus.h>
++#include <linux/videodev2.h>
++
++#include <media/v4l2-clk.h>
++#include <media/v4l2-subdev.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-image-sizes.h>
++#include <media/v4l2-device.h>
++#include <ingenic_camera.h>
++
++#include <linux/clk.h>
++#include <linux/regulator/consumer.h>
++
++#define REG_CHIP_ID_HIGH	0x3107
++#define REG_CHIP_ID_LOW		0x3108
++#define CHIP_ID_HIGH		0x00
++#define CHIP_ID_LOW		0x31
++#define SC031_REG_DELAY		0xfe
++
++#define  SC031GS_DEFAULT_WIDTH    640
++#define  SC031GS_DEFAULT_HEIGHT   480
++
++/*
++ * Struct
++ */
++struct regval_list {
++	u16 reg_num;
++	u16 value;
++};
++
++struct mode_list {
++	u16 index;
++	const struct regval_list *mode_regs;
++};
++
++/* Supported resolutions */
++enum sc031gs_width {
++	W_VGA	= SC031GS_DEFAULT_WIDTH,
++};
++
++enum sc031gs_height {
++	H_VGA	= SC031GS_DEFAULT_HEIGHT,
++};
++
++struct sc031gs_win_size {
++	char *name;
++	enum sc031gs_width width;
++	enum sc031gs_height height;
++	const struct regval_list *regs;
++	unsigned int mbus_code;
++};
++
++struct sc031gs_priv {
++	struct v4l2_subdev		subdev;
++	struct v4l2_ctrl_handler	hdl;
++	u32	cfmt_code;
++	struct v4l2_clk			*clk;
++	const struct sc031gs_win_size	*win;
++
++	int				model;
++	u16				balance_value;
++	u16				effect_value;
++	u16				flag_vflip:1;
++	u16				flag_hflip:1;
++
++	struct v4l2_subdev_platform_data *sd_pdata;
++	struct gpio_desc *resetb_gpio;
++	struct gpio_desc *pwdn_gpio;
++	struct gpio_desc *vcc_en_gpio;
++
++	int (*power)(struct i2c_client *client, int on);
++	int (*reset)(struct i2c_client *client);
++
++	struct regulator *reg;
++	struct regulator *reg1;
++};
++
++static inline int sensor_i2c_master_send(struct i2c_client *client,
++		const char *buf ,int count)
++{
++	int ret;
++	struct i2c_adapter *adap=client->adapter;
++	struct i2c_msg msg;
++
++	msg.addr = client->addr;
++	msg.flags = client->flags & I2C_M_TEN;
++	msg.len = count;
++	msg.buf = (char *)buf;
++
++	ret = i2c_transfer(adap, &msg, 1);
++
++	return (ret == 1) ? count : ret;
++}
++
++static inline int sensor_i2c_master_recv(struct i2c_client *client,
++		char *buf ,int count)
++{
++	struct i2c_adapter *adap=client->adapter;
++	struct i2c_msg msg;
++	int ret;
++
++	msg.addr = client->addr;
++	msg.flags = client->flags & I2C_M_TEN;
++	msg.flags |= I2C_M_RD;
++	msg.len = count;
++	msg.buf = buf;
++	ret = i2c_transfer(adap, &msg, 1);
++
++	return (ret == 1) ? count : ret;
++}
++
++
++unsigned char sc031gs_read_reg(struct i2c_client *client, u16 reg)
++{
++	int ret;
++	unsigned char retval;
++	unsigned short r = cpu_to_be16(reg);
++
++	ret = sensor_i2c_master_send(client,(u8 *)&r,2);
++
++	if (ret < 0)
++		return ret;
++	if (ret != 2)
++		return -EIO;
++
++	ret = sensor_i2c_master_recv(client, &retval, 1);
++	if (ret < 0)
++		return ret;
++	if (ret != 1)
++		return -EIO;
++	return retval;
++}
++
++int sc031gs_write_reg(struct i2c_client *client, u16 reg, u8 val)
++{
++	unsigned char msg[3];
++	int ret;
++
++	reg = cpu_to_be16(reg);
++
++	memcpy(&msg[0], &reg, 2);
++	memcpy(&msg[2], &val, 1);
++
++	ret = sensor_i2c_master_send(client, msg, 3);
++
++	if (ret < 0)
++	{
++		printk("RET<0\n");
++		return ret;
++	}
++	if (ret < 3)
++	{
++		printk("RET<3\n");
++		return -EIO;
++	}
++
++	return 0;
++}
++
++/*
++ * Registers settings
++ */
++
++#define ENDMARKER { 0xffff, 0xff }
++
++static const struct regval_list sc031gs_init_regs[] = {
++
++	{0x0103, 0x01},
++	{0x0100, 0x00},
++	{0x36e9, 0x80},
++	{0x36f9, 0x80},
++	{0x3001, 0x00},
++	{0x3000, 0x00},
++	{0x300f, 0x0f},
++	{0x3018, 0x33},
++	{0x3019, 0xfc},
++	{0x301c, 0x78},
++	{0x301f, 0x0e},
++	{0x3031, 0x0a},
++	{0x3037, 0x20},
++	{0x303f, 0x01},
++	{0x320c, 0x04},
++	{0x320d, 0xb0},
++	{0x320e, 0x07},
++	{0x320f, 0xd0},
++	{0x3220, 0x10},
++	{0x3250, 0xc0},
++	{0x3251, 0x02},
++	{0x3252, 0x02},
++	{0x3253, 0xa6},
++	{0x3254, 0x02},
++	{0x3255, 0x07},
++	{0x3304, 0x48},
++	{0x3306, 0x38},
++	{0x3309, 0x68},
++	{0x330b, 0xe0},
++	{0x330c, 0x18},
++	{0x330f, 0x20},
++	{0x3310, 0x10},
++	{0x3314, 0x1e},
++	{0x3315, 0x38},
++	{0x3316, 0x40},
++	{0x3317, 0x10},
++	{0x3329, 0x34},
++	{0x332d, 0x34},
++	{0x332f, 0x38},
++	{0x3335, 0x3c},
++	{0x3344, 0x3c},
++	{0x335b, 0x80},
++	{0x335f, 0x80},
++	{0x3366, 0x06},
++	{0x3385, 0x31},
++	{0x3387, 0x51},
++	{0x3389, 0x01},
++	{0x33b1, 0x03},
++	{0x33b2, 0x06},
++	{0x3621, 0xa4},
++	{0x3622, 0x05},
++	{0x3624, 0x47},
++	{0x3630, 0x46},
++	{0x3631, 0x48},
++	{0x3633, 0x52},
++	{0x3635, 0x18},
++	{0x3636, 0x25},
++	{0x3637, 0x89},
++	{0x3638, 0x0f},
++	{0x3639, 0x08},
++	{0x363a, 0x00},
++	{0x363b, 0x48},
++	{0x363c, 0x06},
++	{0x363d, 0x00},
++	{0x363e, 0xf8},
++	{0x3640, 0x00},
++	{0x3641, 0x01},
++	{0x36ea, 0x3b},
++	{0x36eb, 0x0e},
++	{0x36ec, 0x1e},
++	{0x36ed, 0x33},
++	{0x36fa, 0x3a},
++	{0x36fc, 0x01},
++	{0x3908, 0x91},
++	{0x3d08, 0x01},
++	{0x3e01, 0x70},
++	{0x3e02, 0x00}, // 1800
++	{0x3e06, 0x0c},
++	{0x3e08, 0x01},
++	{0x3e09, 0x1f}, //4x again
++	{0x4500, 0x59},
++	{0x4501, 0xc4},
++	{0x4603, 0x00},
++	{0x4809, 0x01},
++	{0x4837, 0x38},
++	{0x5011, 0x00},
++	{0x36e9, 0x00},
++	{0x36f9, 0x00},
++	//{0x0100, 0x01}, //stream on
++
++	//Delay  10ms}
++	{0x4418, 0x08},
++	{0x4419, 0x8e},
++
++	//[gain<2]
++	{0x3314, 0x1e},//0222
++	{0x3317, 0x10},
++	//[4>gain>=2]
++	{0x3314, 0x4f}, //0222
++	{0x3317, 0x0f}, //0625
++	//[gain>=4]
++	{0x3314, 0x4f}, //0222
++	{0x3317, 0x0f}, //0625
++	{SC031_REG_DELAY,10},
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_qvga_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_vga_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_720p_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_1080p_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_wb_auto_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_wb_incandescence_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_wb_daylight_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_wb_fluorescent_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_wb_cloud_regs[] = {
++	ENDMARKER,
++};
++
++static const struct mode_list sc031gs_balance[] = {
++	{0, sc031gs_wb_auto_regs}, {1, sc031gs_wb_incandescence_regs},
++	{2, sc031gs_wb_daylight_regs}, {3, sc031gs_wb_fluorescent_regs},
++	{4, sc031gs_wb_cloud_regs},
++};
++
++
++static const struct regval_list sc031gs_effect_normal_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_effect_grayscale_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_effect_sepia_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_effect_colorinv_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_effect_sepiabluel_regs[] = {
++	ENDMARKER,
++};
++
++static const struct mode_list sc031gs_effect[] = {
++	{0, sc031gs_effect_normal_regs}, {1, sc031gs_effect_grayscale_regs},
++	{2, sc031gs_effect_sepia_regs}, {3, sc031gs_effect_colorinv_regs},
++	{4, sc031gs_effect_sepiabluel_regs},
++};
++
++#define SC031GS_SIZE(n, w, h, r, c) \
++	{.name = n, .width = w , .height = h, .regs = r, .mbus_code = c }
++
++static struct sc031gs_win_size sc031gs_supported_win_sizes[] = {
++	SC031GS_SIZE("VGA", W_VGA, H_VGA, sc031gs_vga_regs, MEDIA_BUS_FMT_SBGGR10_1X10),
++};
++
++#define N_WIN_SIZES (ARRAY_SIZE(sc031gs_supported_win_sizes))
++/*
++ * General functions
++ */
++static struct sc031gs_priv *to_sc031gs(const struct i2c_client *client)
++{
++	return container_of(i2c_get_clientdata(client), struct sc031gs_priv,
++			    subdev);
++}
++
++static int sc031gs_write_array(struct i2c_client *client,
++			      const struct regval_list *vals)
++{
++	int ret;
++
++	while ((vals->reg_num != 0xffff) || (vals->value != 0xff)) {
++		ret = sc031gs_write_reg(client, vals->reg_num, vals->value);
++		dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x",
++			 vals->reg_num, vals->value);
++
++		if (ret < 0)
++			return ret;
++		vals++;
++	}
++	return 0;
++}
++
++/* OF probe functions */
++static int sc031gs_hw_power(struct i2c_client *client, int on)
++{
++	struct sc031gs_priv *priv = to_sc031gs(client);
++
++	dev_dbg(&client->dev, "%s: %s the camera\n",
++			__func__, on ? "ENABLE" : "DISABLE");
++
++	/* thses gpio should be set according to the active level in dt defines */
++	if(priv->vcc_en_gpio) {
++		gpiod_direction_output(priv->vcc_en_gpio, on);
++	}
++
++	msleep(3);
++
++	if (priv->pwdn_gpio) {
++		gpiod_direction_output(priv->pwdn_gpio, on);
++	}
++
++	msleep(10);
++	return 0;
++}
++
++static int sc031gs_reset(struct i2c_client *client)
++{
++	struct sc031gs_priv *priv = to_sc031gs(client);
++
++	if(priv->resetb_gpio) {
++		gpiod_direction_output(priv->resetb_gpio, 1);
++		msleep(10);
++		gpiod_direction_output(priv->resetb_gpio, 0);
++		msleep(10);
++	}
++
++	return 0;
++}
++
++static int sc031gs_s_power(struct v4l2_subdev *sd, int on)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct sc031gs_priv *priv = to_sc031gs(client);
++
++	if(priv->sd_pdata) {
++		if(on){
++			return regulator_bulk_enable(priv->sd_pdata->num_regulators,priv->sd_pdata->regulators);
++		}else{
++			return regulator_bulk_disable(priv->sd_pdata->num_regulators,priv->sd_pdata->regulators);
++		}
++	} else if(priv->power) {
++		return priv->power(client, on);
++	} else {
++		dev_err(&client->dev, "sc031gs_s_power failde");
++		return -EINVAL;
++	}
++
++}
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int sc031gs_g_register(struct v4l2_subdev *sd,
++			     struct v4l2_dbg_register *reg)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	int ret;
++
++	reg->size = 1;
++	if (reg->reg > 0xff)
++		return -EINVAL;
++
++	ret = sc031gs_read_reg(client, reg->reg);
++	if (ret < 0)
++		return ret;
++
++	reg->val = ret;
++
++	return 0;
++}
++
++static int sc031gs_s_register(struct v4l2_subdev *sd,
++			     const struct v4l2_dbg_register *reg)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++
++	if (reg->reg > 0xff ||
++	    reg->val > 0xff)
++		return -EINVAL;
++
++	return sc031gs_write_reg(client, reg->reg, reg->val);
++}
++#endif
++
++/*
++ * soc_camera_ops functions
++ */
++static int sc031gs_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++
++	if (!enable ) {
++		dev_info(&client->dev, "stream down\n");
++		sc031gs_write_reg(client, 0x0100, 0x00);
++		return 0;
++	}
++
++	dev_info(&client->dev, "stream on\n");
++	sc031gs_write_reg(client, 0x0100, 0x01);
++
++	return 0;
++}
++
++/* Select the nearest higher resolution for capture */
++static const struct sc031gs_win_size *sc031gs_select_win(u32 *code, u32 *width, u32 *height)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(sc031gs_supported_win_sizes); i++) {
++		if ((*width >= sc031gs_supported_win_sizes[i].width) &&
++		    (*height >= sc031gs_supported_win_sizes[i].height) &&
++		    (*code == sc031gs_supported_win_sizes[i].mbus_code)) {
++			*width = sc031gs_supported_win_sizes[i].width;
++			*height = sc031gs_supported_win_sizes[i].height;
++			return &sc031gs_supported_win_sizes[i];
++		}
++	}
++
++	return NULL;
++}
++
++static int sc031gs_get_selection(struct v4l2_subdev *sd,
++				struct v4l2_subdev_pad_config *cfg,
++				struct v4l2_subdev_selection *sel)
++{
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct sc031gs_priv *priv = to_sc031gs(client);
++
++	if(!priv->win)
++		return -EINVAL;
++
++	sel->r.top = 0;
++	sel->r.left = 0;
++	sel->r.width = priv->win->width;
++	sel->r.height = priv->win->height;
++
++	return 0;
++}
++
++static int sc031gs_get_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct sc031gs_priv *priv = to_sc031gs(client);
++
++	if (format->pad)
++		return -EINVAL;
++	if(priv->win) {
++		mf->width = priv->win->width;
++		mf->height = priv->win->height;
++	} else {
++		mf->width = SC031GS_DEFAULT_WIDTH;
++		mf->height = SC031GS_DEFAULT_HEIGHT;
++	}
++	mf->code = priv->cfmt_code;
++
++	mf->colorspace = V4L2_COLORSPACE_JPEG;
++	mf->field	= V4L2_FIELD_NONE;
++
++	return 0;
++}
++
++static int sc031gs_set_params(struct i2c_client *client, u32 *width, u32 *height, u32 code)
++{
++	struct sc031gs_priv       *priv = to_sc031gs(client);
++	int ret;
++
++	int bala_index = priv->balance_value;
++	int effe_index = priv->effect_value;
++
++	/* select win */
++	priv->win = sc031gs_select_win(&code, width, height);
++
++	/* select format */
++	priv->cfmt_code = 0;
++
++	/* reset hardware */
++	sc031gs_reset(client);
++
++	/* initialize the sensor with default data */
++	dev_dbg(&client->dev, "%s: Init default", __func__);
++
++	ret = sc031gs_write_array(client, sc031gs_init_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set balance */
++	ret = sc031gs_write_array(client, sc031gs_balance[bala_index].mode_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set effect */
++	ret = sc031gs_write_array(client, sc031gs_effect[effe_index].mode_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set size win */
++	ret = sc031gs_write_array(client, priv->win->regs);
++	if (ret < 0)
++		goto err;
++
++	priv->cfmt_code = code;
++	*width = priv->win->width;
++	*height = priv->win->height;
++
++	return 0;
++
++err:
++	dev_err(&client->dev, "%s: Error %d", __func__, ret);
++	sc031gs_reset(client);
++	priv->win = NULL;
++
++	return ret;
++}
++
++static int sc031gs_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct sc031gs_priv *priv = to_sc031gs(client);
++
++	if (format->pad)
++		return -EINVAL;
++
++	/*
++	 * select suitable win, but don't store it
++	 */
++	priv->win = sc031gs_select_win(&mf->code, &mf->width, &mf->height);
++	if(!priv->win)
++		return -EINVAL;
++
++	mf->field	= V4L2_FIELD_NONE;
++	mf->colorspace = V4L2_COLORSPACE_JPEG;
++
++	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
++		sc031gs_set_params(client, &mf->width, &mf->height, mf->code);
++	if(cfg)
++		cfg->try_fmt = *mf;
++	return 0;
++}
++
++static int sc031gs_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad || code->index >= ARRAY_SIZE(sc031gs_supported_win_sizes))
++		return -EINVAL;
++
++	code->code = sc031gs_supported_win_sizes[code->index].mbus_code;
++	return 0;
++}
++
++static int sc031gs_enum_frame_size(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_frame_size_enum *fse)
++{
++	__u32 index = fse->index;
++
++	if(index >= N_WIN_SIZES)
++		return -EINVAL;
++
++	fse->code = sc031gs_supported_win_sizes[index].mbus_code;
++	fse->min_width = sc031gs_supported_win_sizes[index].width;
++	fse->max_width = fse->min_width;
++	fse->min_height = sc031gs_supported_win_sizes[index].height;
++	fse->max_height = fse->min_height;
++	return 0;
++}
++
++static int sc031gs_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
++		struct v4l2_mbus_config *cfg)
++{
++	/*int dts*/
++	return 0;
++}
++
++static struct v4l2_subdev_core_ops sc031gs_subdev_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register	= sc031gs_g_register,
++	.s_register	= sc031gs_s_register,
++#endif
++	.s_power	= sc031gs_s_power,
++};
++
++static struct v4l2_subdev_video_ops sc031gs_subdev_video_ops = {
++	.s_stream	= sc031gs_s_stream,
++};
++
++static const struct v4l2_subdev_pad_ops sc031gs_subdev_pad_ops = {
++	.enum_mbus_code = sc031gs_enum_mbus_code,
++	.enum_frame_size = sc031gs_enum_frame_size,
++	.get_fmt	= sc031gs_get_fmt,
++	.set_fmt	= sc031gs_set_fmt,
++	.get_mbus_config = sc031gs_g_mbus_config,
++	.get_selection	= sc031gs_get_selection,
++};
++
++static struct v4l2_subdev_ops sc031gs_subdev_ops = {
++	.core	= &sc031gs_subdev_core_ops,
++	.video	= &sc031gs_subdev_video_ops,
++	.pad	= &sc031gs_subdev_pad_ops,
++};
++
++static int sc031gs_hw_reset(struct i2c_client *client)
++{
++	struct sc031gs_priv *priv = to_sc031gs(client);
++
++	if (priv->resetb_gpio) {
++		/* Active the resetb pin to perform a reset pulse */
++		gpiod_direction_output(priv->resetb_gpio, 1);
++		usleep_range(3000, 5000);
++		gpiod_direction_output(priv->resetb_gpio, 0);
++	}
++
++	return 0;
++}
++
++static int sc031gs_video_probe(struct i2c_client *client)
++{
++	unsigned char retval_high = 0, retval_low = 0;
++	struct sc031gs_priv *priv = to_sc031gs(client);
++	int ret;
++
++	ret = sc031gs_s_power(&priv->subdev, 1);
++	if (ret < 0)
++		return ret;
++	/*
++	 * check and show product ID and manufacturer ID
++	 */
++
++	retval_high = sc031gs_read_reg(client, REG_CHIP_ID_HIGH);
++	if (retval_high != CHIP_ID_HIGH) {
++		dev_err(&client->dev, "read sensor %s chip_id high %x is error\n",
++				client->name, retval_high);
++		ret = -EINVAL;
++		goto done;
++	}
++
++
++	retval_low = sc031gs_read_reg(client, REG_CHIP_ID_LOW);
++	if (retval_low != CHIP_ID_LOW) {
++		dev_err(&client->dev, "read sensor %s chip_id low %x is error\n",
++				client->name, retval_low);
++		ret = -EINVAL;
++		goto done;
++	}
++	dev_info(&client->dev, "read sensor %s id high:0x%x,low:%x successed!\n",
++			client->name, retval_high, retval_low);
++
++done:
++//	sc031gs_s_power(&priv->subdev, 0);
++	return ret;
++}
++
++static int sc031gs_probe_dt(struct i2c_client *client,
++		struct sc031gs_priv *priv)
++{
++
++	struct v4l2_subdev_platform_data *sd_pdata = priv->sd_pdata;
++	struct device_node *np = client->dev.of_node;
++	int supplies = 0, index = 0;
++
++	supplies = of_property_count_strings(np, "supplies-name");
++	if(supplies > 0) {
++		sd_pdata = devm_kzalloc(&client->dev, sizeof(struct v4l2_subdev_platform_data), GFP_KERNEL);
++		sd_pdata->num_regulators = supplies;
++		sd_pdata->regulators = devm_kzalloc(&client->dev, supplies * sizeof(struct regulator_bulk_data), GFP_KERNEL);
++		if(!sd_pdata->regulators) {
++			dev_err(&client->dev, "Failed to allocate regulators.!\n");
++			devm_kfree(&client->dev,sd_pdata);
++			return -ENOMEM;
++		}
++
++		for(index = 0; index < sd_pdata->num_regulators; index ++) {
++			of_property_read_string_index(np, "supplies-name", index,
++					&(sd_pdata->regulators[index].supply));
++
++			dev_dbg(&client->dev, "sd_pdata->regulators[%d].supply: %s\n",
++					index, sd_pdata->regulators[index].supply);
++		}
++
++		devm_regulator_bulk_get(&client->dev, sd_pdata->num_regulators, sd_pdata->regulators);
++	} else {
++		/* Request the reset GPIO deasserted */
++		priv->resetb_gpio = devm_gpiod_get_optional(&client->dev, "resetb",
++				GPIOD_OUT_LOW);
++		if (!priv->resetb_gpio)
++			dev_dbg(&client->dev, "resetb gpio is not assigned!\n");
++		else if (IS_ERR(priv->resetb_gpio))
++			return PTR_ERR(priv->resetb_gpio);
++
++		/* Request the power down GPIO asserted */
++		priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn",
++				GPIOD_OUT_LOW);
++		if (!priv->pwdn_gpio)
++			dev_dbg(&client->dev, "pwdn gpio is not assigned!\n");
++		else if (IS_ERR(priv->pwdn_gpio))
++			return PTR_ERR(priv->pwdn_gpio);
++
++		/* Request the power down GPIO asserted */
++		priv->vcc_en_gpio = devm_gpiod_get_optional(&client->dev, "vcc-en",
++				GPIOD_OUT_LOW);
++		if (!priv->vcc_en_gpio)
++			dev_dbg(&client->dev, "vcc_en gpio is not assigned!\n");
++		else if (IS_ERR(priv->vcc_en_gpio))
++			return PTR_ERR(priv->vcc_en_gpio);
++
++		/* Initialize the soc_camera_subdev_desc */
++		priv->power = sc031gs_hw_power;
++		priv->reset = sc031gs_hw_reset;
++	}
++	return 0;
++}
++
++#include <linux/regulator/consumer.h>
++/*
++ * i2c_driver functions
++ */
++static int sc031gs_probe(struct i2c_client *client,
++			const struct i2c_device_id *did)
++{
++	struct sc031gs_priv	*priv;
++	struct i2c_adapter	*adapter = to_i2c_adapter(client->dev.parent);
++	int	ret;
++
++	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA)) {
++		dev_err(&adapter->dev,
++			"sc031gs: I2C-Adapter doesn't support SMBUS\n");
++		return -EIO;
++	}
++
++	priv = devm_kzalloc(&client->dev, sizeof(struct sc031gs_priv), GFP_KERNEL);
++	if (!priv) {
++		dev_err(&adapter->dev,
++			"Failed to allocate memory for private data!\n");
++		return -ENOMEM;
++	}
++
++	priv->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(priv->clk))
++		return -EPROBE_DEFER;
++
++	v4l2_clk_set_rate(priv->clk, 24000000);
++
++	ret = sc031gs_probe_dt(client, priv);
++	if (ret)
++		goto err_probe_dt;
++
++	v4l2_i2c_subdev_init(&priv->subdev, client, &sc031gs_subdev_ops);
++
++	ret = sc031gs_video_probe(client);
++	if (ret < 0)
++		goto err_detect;
++
++	ret = v4l2_async_register_subdev(&priv->subdev);
++	if (ret < 0)
++		goto err_async_register_subdev;
++
++	dev_info(&adapter->dev, "sc031gs mipi Probed\n");
++
++	return 0;
++
++err_async_register_subdev:
++err_detect:
++	v4l2_ctrl_handler_free(&priv->hdl);
++err_hdl:
++	v4l2_device_unregister_subdev(&priv->subdev);
++err_probe_dt:
++	v4l2_clk_put(priv->clk);
++	devm_kfree(&client->dev, priv);
++	return ret;
++}
++
++static int sc031gs_remove(struct i2c_client *client)
++{
++	struct sc031gs_priv       *priv = to_sc031gs(client);
++
++	v4l2_async_unregister_subdev(&priv->subdev);
++	v4l2_clk_put(priv->clk);
++	v4l2_device_unregister_subdev(&priv->subdev);
++	v4l2_ctrl_handler_free(&priv->hdl);
++	devm_kfree(&client->dev, priv);
++	return 0;
++}
++
++static const struct i2c_device_id sc031gs_id[] = {
++	{ "sc031gs",  0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, sc031gs_id);
++static const struct of_device_id sc031gs_of_match[] = {
++	{.compatible = "sc031gs", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, sc031gs_of_match);
++static struct i2c_driver sc031gs_i2c_driver = {
++	.driver = {
++		.name = "sc031gs",
++		.of_match_table = of_match_ptr(sc031gs_of_match),
++	},
++	.probe    = sc031gs_probe,
++	.remove   = sc031gs_remove,
++	.id_table = sc031gs_id,
++};
++
++module_i2c_driver(sc031gs_i2c_driver);
++
++MODULE_DESCRIPTION("SoC Camera driver for smartsens SC031GS sensor");
++MODULE_LICENSE("GPL v2");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-cim/sc031gs.c b/module_drivers/drivers/media/i2c/ingenic-cim/sc031gs.c
+new file mode 100644
+index 000000000..535b1301d
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-cim/sc031gs.c
+@@ -0,0 +1,985 @@
++/*
++ * sc031gs Camera Driver
++ *
++ * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com>
++ *
++ * Based on ov772x, ov9640 drivers and previous non merged implementations.
++ *
++ * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright (C) 2006, OmniVision
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/i2c.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/gpio/consumer.h>
++#include <linux/of_gpio.h>
++#include <linux/v4l2-mediabus.h>
++#include <linux/videodev2.h>
++
++#include <media/v4l2-clk.h>
++#include <media/v4l2-subdev.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-image-sizes.h>
++#include <media/v4l2-device.h>
++#include <ingenic_camera.h>
++
++#include <linux/clk.h>
++#include <linux/regulator/consumer.h>
++
++#define REG_CHIP_ID_HIGH	0x3107
++#define REG_CHIP_ID_LOW		0x3108
++#define CHIP_ID_HIGH		0x00
++#define CHIP_ID_LOW		0x31
++
++#define  SC031GS_DEFAULT_WIDTH    640
++#define  SC031GS_DEFAULT_HEIGHT   480
++
++/* Private v4l2 controls */
++#define V4L2_CID_PRIVATE_BALANCE  (V4L2_CID_PRIVATE_BASE + 0)
++#define V4L2_CID_PRIVATE_EFFECT  (V4L2_CID_PRIVATE_BASE + 1)
++
++/*
++ * Struct
++ */
++struct regval_list {
++	u16 reg_num;
++	u16 value;
++};
++
++struct mode_list {
++	u16 index;
++	const struct regval_list *mode_regs;
++};
++
++/* Supported resolutions */
++enum sc031gs_width {
++	W_VGA	= SC031GS_DEFAULT_WIDTH,
++};
++
++enum sc031gs_height {
++	H_VGA	= SC031GS_DEFAULT_HEIGHT,
++};
++
++struct sc031gs_win_size {
++	char *name;
++	enum sc031gs_width width;
++	enum sc031gs_height height;
++	const struct regval_list *regs;
++	unsigned int mbus_code;
++};
++
++struct sc031gs_priv {
++	struct v4l2_subdev		subdev;
++	struct v4l2_ctrl_handler	hdl;
++	u32	cfmt_code;
++	struct v4l2_clk			*clk;
++	const struct sc031gs_win_size	*win;
++
++	int				model;
++	u16				balance_value;
++	u16				effect_value;
++	u16				flag_vflip:1;
++	u16				flag_hflip:1;
++
++	struct v4l2_subdev_platform_data *sd_pdata;
++	struct gpio_desc *resetb_gpio;
++	struct gpio_desc *pwdn_gpio;
++	struct gpio_desc *vcc_en_gpio;
++
++	int (*power)(struct i2c_client *client, int on);
++	int (*reset)(struct i2c_client *client);
++
++	struct regulator *reg;
++	struct regulator *reg1;
++};
++
++static inline int sensor_i2c_master_send(struct i2c_client *client,
++		const char *buf ,int count)
++{
++	int ret;
++	struct i2c_adapter *adap=client->adapter;
++	struct i2c_msg msg;
++
++	msg.addr = client->addr;
++	msg.flags = client->flags & I2C_M_TEN;
++	msg.len = count;
++	msg.buf = (char *)buf;
++
++	ret = i2c_transfer(adap, &msg, 1);
++
++	return (ret == 1) ? count : ret;
++}
++
++static inline int sensor_i2c_master_recv(struct i2c_client *client,
++		char *buf ,int count)
++{
++	struct i2c_adapter *adap=client->adapter;
++	struct i2c_msg msg;
++	int ret;
++
++	msg.addr = client->addr;
++	msg.flags = client->flags & I2C_M_TEN;
++	msg.flags |= I2C_M_RD;
++	msg.len = count;
++	msg.buf = buf;
++	ret = i2c_transfer(adap, &msg, 1);
++
++	return (ret == 1) ? count : ret;
++}
++
++
++unsigned char sc031gs_read_reg(struct i2c_client *client, u16 reg)
++{
++	int ret;
++	unsigned char retval;
++	unsigned short r = cpu_to_be16(reg);
++
++	ret = sensor_i2c_master_send(client,(u8 *)&r,2);
++
++	if (ret < 0)
++		return ret;
++	if (ret != 2)
++		return -EIO;
++
++	ret = sensor_i2c_master_recv(client, &retval, 1);
++	if (ret < 0)
++		return ret;
++	if (ret != 1)
++		return -EIO;
++	return retval;
++}
++
++int sc031gs_write_reg(struct i2c_client *client, u16 reg, u8 val)
++{
++	unsigned char msg[3];
++	int ret;
++
++	reg = cpu_to_be16(reg);
++
++	memcpy(&msg[0], &reg, 2);
++	memcpy(&msg[2], &val, 1);
++
++	ret = sensor_i2c_master_send(client, msg, 3);
++
++	if (ret < 0)
++	{
++		printk("RET<0\n");
++		return ret;
++	}
++	if (ret < 3)
++	{
++		printk("RET<3\n");
++		return -EIO;
++	}
++
++	return 0;
++}
++
++/*
++ * Registers settings
++ */
++
++#define ENDMARKER { 0xffff, 0xff }
++
++static const struct regval_list sc031gs_init_regs[] = {
++	{0x0103,0x01},
++	{0x0100,0x00},
++	{0x3018,0x1f},
++	{0x3019,0xff},
++	{0x301c,0xb4},
++	{0x363c,0x08},
++	{0x3630,0x82},
++	{0x3638,0x0f},
++	{0x3639,0x08},
++	{0x335b,0x80},
++	{0x3636,0x25},
++	{0x3640,0x02},
++	{0x3306,0x38},
++	{0x3304,0x48},
++	{0x3389,0x01},
++	{0x3385,0x31},
++	{0x330c,0x18},
++	{0x3315,0x38},
++	{0x3306,0x28},
++	{0x3309,0x68},
++	{0x3387,0x51},
++	{0x3306,0x48},
++	{0x3366,0x04},
++	{0x335f,0x80},
++	{0x363a,0x00},
++	{0x3622,0x01},
++	{0x3633,0x62},
++	{0x36f9,0x20},
++	{0x3637,0x80},
++	{0x363d,0x04},
++	{0x3e06,0x00},
++	{0x363c,0x48},
++	{0x320c,0x03},
++	{0x320e,0x0e},
++	{0x320f,0xa8},
++	{0x3306,0x38},
++	{0x330b,0xb6},
++	{0x36f9,0x24},
++	{0x363b,0x4a},
++	{0x3366,0x02},
++	{0x3316,0x78},
++	{0x3344,0x74},
++	{0x3335,0x74},
++	{0x332f,0x70},
++	{0x332d,0x6c},
++	{0x3329,0x6c},
++	{0x363c,0x08},
++	{0x3630,0x81},
++	{0x3366,0x06},
++	{0x3314,0x3a},
++	{0x3317,0x28},
++	{0x3622,0x05},
++	{0x363d,0x00},
++	{0x3637,0x86},
++	{0x3e01,0x62},
++	{0x3633,0x52},
++	{0x3630,0x86},
++	{0x3306,0x4c},
++	{0x330b,0xa0},
++	{0x3631,0x48},
++	{0x33b1,0x03},
++	{0x33b2,0x06},
++	{0x320c,0x02},
++	{0x320e,0x02},
++	{0x320f,0x0d},
++	{0x3e01,0x20},
++	{0x3e02,0x20},
++	{0x3316,0x68},
++	{0x3344,0x64},
++	{0x3335,0x64},
++	{0x332f,0x60},
++	{0x332d,0x5c},
++	{0x3329,0x5c},
++	{0x3310,0x10},
++	{0x3637,0x87},
++	{0x363e,0xf8},
++	{0x3254,0x02},
++	{0x3255,0x07},
++	{0x3252,0x02},
++	{0x3253,0xa6},
++	{0x3250,0xf0},
++	{0x3251,0x02},
++	{0x330f,0x50},
++	{0x3630,0x46},
++	{0x3621,0xa2},
++	{0x3621,0xa0},
++	{0x4500,0x59},
++	{0x3637,0x88},
++	{0x3908,0x81},
++	{0x3640,0x00},
++	{0x3641,0x02},
++	{0x363c,0x05},
++	{0x363b,0x4c},
++	{0x36e9,0x40},
++	{0x36ea,0x36},
++	{0x36ed,0x13},
++	{0x36f9,0x04},
++	{0x36fa,0x38},
++	{0x330b,0x80},
++	{0x3640,0x00},
++	{0x3641,0x01},
++	{0x3d08,0x00},
++	{0x3306,0x48},
++	{0x3621,0xa4},
++	{0x300f,0x0f},
++	{0x4837,0x1b},
++	{0x4809,0x01},
++	{0x363b,0x48},
++	{0x363c,0x06},
++	{0x36e9,0x00},
++	{0x36ea,0x3b},
++	{0x36eb,0x1A},
++	{0x36ec,0x0A},
++	{0x36ed,0x33},
++	{0x36f9,0x00},
++	{0x36fa,0x3a},
++	{0x36fc,0x01},
++	{0x320c,0x03},
++	{0x320d,0x6e},
++	{0x320e,0x02},
++	{0x320f,0xab},
++	{0x330b,0x80},
++	{0x330f,0x50},
++	{0x3637,0x89},
++	{0x3641,0x01},
++	{0x4501,0xc4},
++	{0x5011,0x01},
++	{0x3908,0x21},
++	{0x3e01,0x40},
++	{0x3e02,0x80},
++	{0x3306,0x38},
++	{0x330b,0xe0},
++	{0x330f,0x20},
++	{0x3d08,0x01},
++	{0x3314,0x65},
++	{0x5011,0x00},
++	{0x3e06,0x0c},
++	{0x3908,0x91},
++	{0x3624,0x47},
++	{0x3220,0x10},
++	{0x3635,0x18},
++	{0x3223,0x50},
++	{0x301f,0x01},
++	{0x3028,0x82},
++	{0x0100,0x01},
++
++	//Delay 10ms
++	{0x4418,0x08},
++	{0x4419,0x80},
++	{0x363d,0x10},
++	{0x3630,0x48},
++	//[gain<2]
++	{0x3314,0x65},
++	{0x3317,0x10},
++	//[4>gain>=2]
++	{0x3314,0x65},
++	{0x3317,0x10},
++	//[gain>=4]
++	{0x3314,0x60},
++	{0x3317,0x0e},
++
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_qvga_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_vga_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_720p_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_1080p_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_wb_auto_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_wb_incandescence_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_wb_daylight_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_wb_fluorescent_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_wb_cloud_regs[] = {
++	ENDMARKER,
++};
++
++static const struct mode_list sc031gs_balance[] = {
++	{0, sc031gs_wb_auto_regs}, {1, sc031gs_wb_incandescence_regs},
++	{2, sc031gs_wb_daylight_regs}, {3, sc031gs_wb_fluorescent_regs},
++	{4, sc031gs_wb_cloud_regs},
++};
++
++
++static const struct regval_list sc031gs_effect_normal_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_effect_grayscale_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_effect_sepia_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_effect_colorinv_regs[] = {
++	ENDMARKER,
++};
++
++static const struct regval_list sc031gs_effect_sepiabluel_regs[] = {
++	ENDMARKER,
++};
++
++static const struct mode_list sc031gs_effect[] = {
++	{0, sc031gs_effect_normal_regs}, {1, sc031gs_effect_grayscale_regs},
++	{2, sc031gs_effect_sepia_regs}, {3, sc031gs_effect_colorinv_regs},
++	{4, sc031gs_effect_sepiabluel_regs},
++};
++
++#define SC031GS_SIZE(n, w, h, r, c) \
++	{.name = n, .width = w , .height = h, .regs = r, .mbus_code = c }
++
++static struct sc031gs_win_size sc031gs_supported_win_sizes[] = {
++	SC031GS_SIZE("VGA", W_VGA, H_VGA, sc031gs_vga_regs, MEDIA_BUS_FMT_Y8_1X8),
++};
++
++#define N_WIN_SIZES (ARRAY_SIZE(sc031gs_supported_win_sizes))
++
++/*
++ * General functions
++ */
++static struct sc031gs_priv *to_sc031gs(const struct i2c_client *client)
++{
++	return container_of(i2c_get_clientdata(client), struct sc031gs_priv,
++			    subdev);
++}
++
++static int sc031gs_write_array(struct i2c_client *client,
++			      const struct regval_list *vals)
++{
++	int ret;
++
++	while ((vals->reg_num != 0xffff) || (vals->value != 0xff)) {
++		ret = sc031gs_write_reg(client, vals->reg_num, vals->value);
++		dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x",
++			 vals->reg_num, vals->value);
++
++		if (ret < 0)
++			return ret;
++		vals++;
++	}
++	return 0;
++}
++
++/* OF probe functions */
++static int sc031gs_hw_power(struct i2c_client *client, int on)
++{
++	struct sc031gs_priv *priv = to_sc031gs(client);
++
++	dev_dbg(&client->dev, "%s: %s the camera\n",
++			__func__, on ? "ENABLE" : "DISABLE");
++
++	/* thses gpio should be set according to the active level in dt defines */
++	if(priv->vcc_en_gpio) {
++		gpiod_direction_output(priv->vcc_en_gpio, !on);
++	}
++
++	msleep(3);
++
++	if (priv->pwdn_gpio) {
++		gpiod_direction_output(priv->pwdn_gpio, on);
++	}
++
++	msleep(10);
++	return 0;
++}
++
++static int sc031gs_reset(struct i2c_client *client)
++{
++	struct sc031gs_priv *priv = to_sc031gs(client);
++
++	if(priv->resetb_gpio) {
++		gpiod_direction_output(priv->resetb_gpio, 1);
++		msleep(10);
++		gpiod_direction_output(priv->resetb_gpio, 0);
++		msleep(10);
++	}
++
++	return 0;
++}
++
++static int sc031gs_s_power(struct v4l2_subdev *sd, int on)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct sc031gs_priv *priv = to_sc031gs(client);
++
++	if(priv->sd_pdata) {
++		if(on)
++			return regulator_bulk_enable(priv->sd_pdata->num_regulators,priv->sd_pdata->regulators);
++		else
++			return regulator_bulk_disable(priv->sd_pdata->num_regulators,priv->sd_pdata->regulators);
++	} else if(priv->power) {
++		return priv->power(client, on);
++	} else {
++		dev_err(&client->dev, "sc031gs_s_power failde");
++		return -EINVAL;
++	}
++
++}
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int sc031gs_g_register(struct v4l2_subdev *sd,
++			     struct v4l2_dbg_register *reg)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	int ret;
++
++	reg->size = 1;
++	if (reg->reg > 0xff)
++		return -EINVAL;
++
++	ret = sc031gs_read_reg(client, reg->reg);
++	if (ret < 0)
++		return ret;
++
++	reg->val = ret;
++
++	return 0;
++}
++
++static int sc031gs_s_register(struct v4l2_subdev *sd,
++			     const struct v4l2_dbg_register *reg)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++
++	if (reg->reg > 0xff ||
++	    reg->val > 0xff)
++		return -EINVAL;
++
++	return sc031gs_write_reg(client, reg->reg, reg->val);
++}
++#endif
++
++/*
++ * soc_camera_ops functions
++ */
++static int sc031gs_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++
++	if (!enable ) {
++		dev_info(&client->dev, "stream down\n");
++		sc031gs_write_reg(client, 0x0100, 0x00);
++		return 0;
++	}
++
++	dev_info(&client->dev, "stream on\n");
++	sc031gs_write_reg(client, 0x0100, 0x01);
++
++	return 0;
++}
++
++/* Select the nearest higher resolution for capture */
++static const struct sc031gs_win_size *sc031gs_select_win(u32 code, u32 *width, u32 *height)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(sc031gs_supported_win_sizes); i++) {
++		if ((*width >= sc031gs_supported_win_sizes[i].width) &&
++		    (*height >= sc031gs_supported_win_sizes[i].height) &&
++		    (code == sc031gs_supported_win_sizes[i].mbus_code)) {
++			*width = sc031gs_supported_win_sizes[i].width;
++			*height = sc031gs_supported_win_sizes[i].height;
++			return &sc031gs_supported_win_sizes[i];
++		}
++	}
++	return NULL;
++}
++
++static int sc031gs_get_selection(struct v4l2_subdev *sd,
++				struct v4l2_subdev_pad_config *cfg,
++				struct v4l2_subdev_selection *sel)
++{
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct sc031gs_priv *priv = to_sc031gs(client);
++
++	if(!priv->win)
++		return -EINVAL;
++
++	sel->r.top = 0;
++	sel->r.left = 0;
++	sel->r.width = priv->win->width;
++	sel->r.height = priv->win->height;
++
++	return 0;
++}
++
++static int sc031gs_get_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	struct sc031gs_priv *priv = to_sc031gs(client);
++
++	if (format->pad)
++		return -EINVAL;
++	if(priv->win) {
++		mf->width = priv->win->width;
++		mf->height = priv->win->height;
++	} else {
++		mf->width = SC031GS_DEFAULT_WIDTH;
++		mf->height = SC031GS_DEFAULT_HEIGHT;
++	}
++	mf->code = priv->cfmt_code;
++
++	mf->colorspace = V4L2_COLORSPACE_JPEG;
++	mf->field	= V4L2_FIELD_NONE;
++
++	return 0;
++}
++
++static int sc031gs_set_params(struct i2c_client *client, u32 *width, u32 *height, u32 code)
++{
++	struct sc031gs_priv       *priv = to_sc031gs(client);
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	int ret;
++
++	int bala_index = priv->balance_value;
++	int effe_index = priv->effect_value;
++
++	/* select win */
++	priv->win = sc031gs_select_win(code, width, height);
++
++	/* select format */
++	priv->cfmt_code = 0;
++
++	/* reset hardware */
++	sc031gs_reset(client);
++
++	/* initialize the sensor with default data */
++	dev_dbg(&client->dev, "%s: Init default", __func__);
++
++	ret = sc031gs_write_array(client, sc031gs_init_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set balance */
++	ret = sc031gs_write_array(client, sc031gs_balance[bala_index].mode_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set effect */
++	ret = sc031gs_write_array(client, sc031gs_effect[effe_index].mode_regs);
++	if (ret < 0)
++		goto err;
++
++	/* set size win */
++	ret = sc031gs_write_array(client, priv->win->regs);
++	if (ret < 0)
++		goto err;
++
++	priv->cfmt_code = code;
++	*width = priv->win->width;
++	*height = priv->win->height;
++
++	return 0;
++
++err:
++	dev_err(&client->dev, "%s: Error %d", __func__, ret);
++	sc031gs_reset(client);
++	priv->win = NULL;
++
++	return ret;
++}
++
++static int sc031gs_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct sc031gs_priv *priv = to_sc031gs(client);
++
++	if (format->pad)
++		return -EINVAL;
++
++	/*
++	 * select suitable win, but don't store it
++	 */
++	priv->win = sc031gs_select_win(mf->code, &mf->width, &mf->height);
++	if(!priv->win)
++		return -EINVAL;
++
++	mf->field	= V4L2_FIELD_NONE;
++	mf->colorspace = V4L2_COLORSPACE_JPEG;
++
++	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
++		sc031gs_set_params(client, &mf->width, &mf->height, mf->code);
++	if(cfg)
++		cfg->try_fmt = *mf;
++	return 0;
++}
++
++static int sc031gs_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad || code->index >= ARRAY_SIZE(sc031gs_supported_win_sizes))
++		return -EINVAL;
++
++	code->code = sc031gs_supported_win_sizes[code->index].mbus_code;
++	return 0;
++}
++
++static int sc031gs_enum_frame_size(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_frame_size_enum *fse)
++{
++	__u32 index = fse->index;
++
++	if(index >= N_WIN_SIZES)
++		return -EINVAL;
++
++	fse->code = sc031gs_supported_win_sizes[index].mbus_code;
++	fse->min_width = sc031gs_supported_win_sizes[index].width;
++	fse->max_width = fse->min_width;
++	fse->min_height = sc031gs_supported_win_sizes[index].height;
++	fse->max_height = fse->min_height;
++	return 0;
++}
++
++static int sc031gs_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
++		struct v4l2_mbus_config *cfg)
++{
++	/* int dts*/
++	return 0;
++}
++
++static struct v4l2_subdev_core_ops sc031gs_subdev_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register	= sc031gs_g_register,
++	.s_register	= sc031gs_s_register,
++#endif
++	.s_power	= sc031gs_s_power,
++};
++
++static struct v4l2_subdev_video_ops sc031gs_subdev_video_ops = {
++	.s_stream	= sc031gs_s_stream,
++};
++
++static const struct v4l2_subdev_pad_ops sc031gs_subdev_pad_ops = {
++	.enum_mbus_code = sc031gs_enum_mbus_code,
++	.enum_frame_size = sc031gs_enum_frame_size,
++	.get_fmt	= sc031gs_get_fmt,
++	.set_fmt	= sc031gs_set_fmt,
++	.get_mbus_config = sc031gs_g_mbus_config,
++	.get_selection	= sc031gs_get_selection,
++};
++
++static struct v4l2_subdev_ops sc031gs_subdev_ops = {
++	.core	= &sc031gs_subdev_core_ops,
++	.video	= &sc031gs_subdev_video_ops,
++	.pad	= &sc031gs_subdev_pad_ops,
++};
++
++static int sc031gs_hw_reset(struct i2c_client *client)
++{
++	struct sc031gs_priv *priv = to_sc031gs(client);
++
++	if (priv->resetb_gpio) {
++		/* Active the resetb pin to perform a reset pulse */
++		gpiod_direction_output(priv->resetb_gpio, 1);
++		usleep_range(3000, 5000);
++		gpiod_direction_output(priv->resetb_gpio, 0);
++	}
++
++	return 0;
++}
++
++static int sc031gs_video_probe(struct i2c_client *client)
++{
++	unsigned char retval = 0, retval_high = 0, retval_low = 0;
++	struct sc031gs_priv *priv = to_sc031gs(client);
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	int ret;
++
++	ret = sc031gs_s_power(&priv->subdev, 1);
++	if (ret < 0)
++		return ret;
++	/*
++	 * check and show product ID and manufacturer ID
++	 */
++
++	retval = sc031gs_write_reg(client, 0x0103, 0x01);
++	if(retval) {
++		dev_err(&client->dev, "i2c write failed!\n");
++		ret = -EINVAL;
++		goto done;
++	}
++
++	retval_high = sc031gs_read_reg(client, REG_CHIP_ID_HIGH);
++	if (retval_high != CHIP_ID_HIGH) {
++		dev_err(&client->dev, "read sensor %s chip_id high %x is error\n",
++				client->name, retval_high);
++		ret = -EINVAL;
++		goto done;
++	}
++
++
++	retval_low = sc031gs_read_reg(client, REG_CHIP_ID_LOW);
++	if (retval_low != CHIP_ID_LOW) {
++		dev_err(&client->dev, "read sensor %s chip_id low %x is error\n",
++				client->name, retval_low);
++		ret = -EINVAL;
++		goto done;
++	}
++
++	dev_info(&client->dev, "read sensor %s id high:0x%x,low:%x successed!\n",
++			client->name, retval_high, retval_low);
++
++done:
++	return ret;
++}
++
++static int sc031gs_probe_dt(struct i2c_client *client,
++		struct sc031gs_priv *priv)
++{
++	struct v4l2_subdev_platform_data *sd_pdata = priv->sd_pdata;
++	struct device_node *np = client->dev.of_node;
++	int supplies = 0, index = 0;
++
++	supplies = of_property_count_strings(np, "supplies-name");
++	if(supplies > 0) {
++		sd_pdata = devm_kzalloc(&client->dev, sizeof(struct v4l2_subdev_platform_data), GFP_KERNEL);
++		sd_pdata->num_regulators = supplies;
++		sd_pdata->regulators = devm_kzalloc(&client->dev, supplies * sizeof(struct regulator_bulk_data), GFP_KERNEL);
++		if(!sd_pdata->regulators) {
++			dev_err(&client->dev, "Failed to allocate regulators.!\n");
++			devm_kfree(&client->dev,sd_pdata);
++			return -ENOMEM;
++		}
++
++		for(index = 0; index < sd_pdata->num_regulators; index ++) {
++			of_property_read_string_index(np, "supplies-name", index,
++					&(sd_pdata->regulators[index].supply));
++
++			dev_dbg(&client->dev, "sd_pdata->regulators[%d].supply: %s\n",
++					index, sd_pdata->regulators[index].supply);
++		}
++
++		devm_regulator_bulk_get(&client->dev, sd_pdata->num_regulators, sd_pdata->regulators);
++	} else {
++		/* Request the reset GPIO deasserted */
++		priv->resetb_gpio = devm_gpiod_get_optional(&client->dev, "resetb",
++				GPIOD_OUT_LOW);
++		if (!priv->resetb_gpio)
++			dev_dbg(&client->dev, "resetb gpio is not assigned!\n");
++		else if (IS_ERR(priv->resetb_gpio))
++			return PTR_ERR(priv->resetb_gpio);
++
++		/* Request the power down GPIO asserted */
++		priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn",
++				GPIOD_OUT_LOW);
++		if (!priv->pwdn_gpio)
++			dev_dbg(&client->dev, "pwdn gpio is not assigned!\n");
++		else if (IS_ERR(priv->pwdn_gpio))
++			return PTR_ERR(priv->pwdn_gpio);
++
++		/* Request the power down GPIO asserted */
++		priv->vcc_en_gpio = devm_gpiod_get_optional(&client->dev, "vcc-en",
++				GPIOD_OUT_HIGH);
++		if (!priv->vcc_en_gpio)
++			dev_dbg(&client->dev, "vcc_en gpio is not assigned!\n");
++		else if (IS_ERR(priv->vcc_en_gpio))
++			return PTR_ERR(priv->vcc_en_gpio);
++
++		/* Initialize the soc_camera_subdev_desc */
++		priv->power = sc031gs_hw_power;
++		priv->reset = sc031gs_hw_reset;
++	}
++	return 0;
++}
++
++#include <linux/regulator/consumer.h>
++/*
++ * i2c_driver functions
++ */
++static int sc031gs_probe(struct i2c_client *client,
++			const struct i2c_device_id *did)
++{
++	struct sc031gs_priv	*priv;
++	struct i2c_adapter	*adapter = to_i2c_adapter(client->dev.parent);
++	int	ret;
++
++	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA)) {
++		dev_err(&adapter->dev,
++			"sc031gs: I2C-Adapter doesn't support SMBUS\n");
++		return -EIO;
++	}
++
++	priv = devm_kzalloc(&client->dev, sizeof(struct sc031gs_priv), GFP_KERNEL);
++	if (!priv) {
++		dev_err(&adapter->dev,
++			"Failed to allocate memory for private data!\n");
++		return -ENOMEM;
++	}
++
++	priv->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(priv->clk))
++		return -EPROBE_DEFER;
++
++	v4l2_clk_set_rate(priv->clk, 24000000);
++
++	ret = sc031gs_probe_dt(client, priv);
++	if (ret)
++		goto err_probe_dt;
++
++	v4l2_i2c_subdev_init(&priv->subdev, client, &sc031gs_subdev_ops);
++
++	ret = sc031gs_video_probe(client);
++	if (ret < 0)
++		goto err_detect;
++
++	ret = v4l2_async_register_subdev(&priv->subdev);
++	if (ret < 0)
++		goto err_async_register_subdev;
++
++	dev_info(&adapter->dev, "sc031gs Probed\n");
++
++	return 0;
++
++err_async_register_subdev:
++err_detect:
++	v4l2_ctrl_handler_free(&priv->hdl);
++err_hdl:
++	v4l2_device_unregister_subdev(&priv->subdev);
++err_probe_dt:
++	v4l2_clk_put(priv->clk);
++	devm_kfree(&client->dev, priv);
++	return ret;
++}
++
++static int sc031gs_remove(struct i2c_client *client)
++{
++	struct sc031gs_priv       *priv = to_sc031gs(client);
++
++	v4l2_async_unregister_subdev(&priv->subdev);
++	v4l2_clk_put(priv->clk);
++	v4l2_device_unregister_subdev(&priv->subdev);
++	v4l2_ctrl_handler_free(&priv->hdl);
++	devm_kfree(&client->dev, priv);
++	return 0;
++}
++
++static const struct i2c_device_id sc031gs_id[] = {
++	{ "sc031gs",  0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, sc031gs_id);
++static const struct of_device_id sc031gs_of_match[] = {
++	{.compatible = "sc031gs", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, sc031gs_of_match);
++static struct i2c_driver sc031gs_i2c_driver = {
++	.driver = {
++		.name = "sc031gs",
++		.of_match_table = of_match_ptr(sc031gs_of_match),
++	},
++	.probe    = sc031gs_probe,
++	.remove   = sc031gs_remove,
++	.id_table = sc031gs_id,
++};
++
++module_i2c_driver(sc031gs_i2c_driver);
++
++MODULE_DESCRIPTION("SoC Camera driver for smartsens SC031GS sensor");
++MODULE_LICENSE("GPL v2");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp-v2/Kconfig b/module_drivers/drivers/media/i2c/ingenic-isp-v2/Kconfig
+new file mode 100644
+index 000000000..372adde35
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp-v2/Kconfig
+@@ -0,0 +1,49 @@
++comment "ingenic-isp-v2 camera sensor drivers"
++
++config INGENIC_ISP_V2_CAMERA_IMX327
++	tristate "imx327 sensor support"
++	depends on VIDEO_INGENIC_ISP_V2 && I2C
++	help
++	  This is a ingenic-isp camera driver for IMX327
++
++config INGENIC_ISP_V2_CAMERA_GC2093
++	tristate "gc2093 sensor support"
++	depends on VIDEO_INGENIC_ISP_V2 && I2C
++	help
++	  This is a ingenic-isp camera driver for GC2093
++
++config INGENIC_ISP_V2_CAMERA_OV2735A
++	tristate "ov2735a sensor support"
++	depends on VIDEO_INGENIC_ISP_V2 && I2C
++	help
++	  This is a ingenic-isp camera driver for ov2735a
++
++config INGENIC_ISP_V2_CAMERA_SC2310
++	tristate "sc2310 sensor support"
++	depends on VIDEO_INGENIC_ISP_V2 && I2C
++	help
++	  This is a ingenic-isp camera driver for sc2310
++
++config INGENIC_ISP_V2_CAMERA_SC230AI
++	tristate "sc230ai sensor support"
++	depends on VIDEO_INGENIC_ISP_V2 && I2C
++	help
++	  This is a ingenic-isp camera driver for sc230ai
++
++config INGENIC_ISP_V2_CAMERA_GC2155
++	tristate "gc2155 sensor support"
++	depends on VIDEO_INGENIC_ISP_V2 && I2C
++	help
++	  This is a ingenic-isp camera driver for gc2155
++
++config INGENIC_ISP_V2_CAMERA_OV4689
++	tristate "ov4689 sensor support"
++	depends on VIDEO_INGENIC_ISP_V2 && I2C
++	help
++	  This is a ingenic-isp camera driver for ov4689
++
++config INGENIC_ISP_V2_CAMERA_OV7251
++	tristate "ov7251 sensor support"
++	depends on VIDEO_INGENIC_ISP_V2 && I2C
++	help
++	  This is a ingenic-isp camera driver for ov7251
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp-v2/Makefile b/module_drivers/drivers/media/i2c/ingenic-isp-v2/Makefile
+new file mode 100644
+index 000000000..8779e03bf
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp-v2/Makefile
+@@ -0,0 +1,10 @@
++obj-$(CONFIG_INGENIC_ISP_V2_CAMERA_IMX327) +=	imx327.o
++obj-$(CONFIG_INGENIC_ISP_V2_CAMERA_GC2093) +=	gc2093.o
++obj-$(CONFIG_INGENIC_ISP_V2_CAMERA_OV2735A) +=  ov2735a.o
++obj-$(CONFIG_INGENIC_ISP_V2_CAMERA_SC2310) +=  sc2310.o
++obj-$(CONFIG_INGENIC_ISP_V2_CAMERA_SC230AI) +=  sc230ai.o
++obj-$(CONFIG_INGENIC_ISP_V2_CAMERA_GC2155) +=  gc2155.o
++obj-$(CONFIG_INGENIC_ISP_V2_CAMERA_OV4689) +=  ov4689.o
++obj-$(CONFIG_INGENIC_ISP_V2_CAMERA_OV7251) +=  ov7251.o
++
++ccflags-y += -I$(srctree)/module_drivers/drivers/media/platform/ingenic-isp-v2/
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp-v2/gc2053.c b/module_drivers/drivers/media/i2c/ingenic-isp-v2/gc2053.c
+new file mode 100755
+index 000000000..763cdbc69
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp-v2/gc2053.c
+@@ -0,0 +1,1001 @@
++/*
++ * A V4L2 driver for OmniVision gc2053 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++#include <linux/clk.h>
++
++#include <isp-sensor.h>
++
++#define GC2053_CHIP_ID_H	(0x20)
++#define GC2053_CHIP_ID_L	(0x53)
++#define GC2053_REG_END		0xff
++#define GC2053_REG_DELAY	0x00
++
++#define AGAIN_MAX_DB 0x64
++#define DGAIN_MAX_DB 0x64
++#define LOG2_GAIN_SHIFT 16
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++
++struct gc2053_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++};
++
++struct gc2053_gpio {
++	int pin;
++	int active_level;
++};
++
++struct gc2053_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++	/* struct clk *sclka; */
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct gc2053_win_size *win;
++
++	struct gc2053_gpio reset;
++	struct gc2053_gpio pwdn;
++	struct gc2053_gpio pwen;
++};
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	int index;
++	unsigned int regb4;
++	unsigned int regb3;
++	unsigned int regb2;
++	unsigned int dpc;
++	unsigned int blc;
++	unsigned int gain;
++};
++
++struct again_lut gc2053_again_lut[] = {
++	{0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0},
++	{0x01, 0x00, 0x00, 0x14, 0x01, 0x00, 5776},
++	{0x02, 0x00, 0x00, 0x20, 0x01, 0x00, 11553},
++	{0x03, 0x00, 0x10, 0x00, 0x01, 0x0c, 17330},
++	{0x04, 0x00, 0x10, 0x10, 0x01, 0x0c, 23450},
++	{0x05, 0x00, 0x20, 0x00, 0x01, 0x1b, 29570},
++	{0x06, 0x00, 0x20, 0x14, 0x01, 0x1b, 36240},
++	{0x07, 0x00, 0x20, 0x28, 0x01, 0x1b, 42910},
++	{0x08, 0x00, 0x30, 0x00, 0x01, 0x2c, 49580},
++	{0x09, 0x00, 0x30, 0x14, 0x01, 0x2c, 57187},
++	{0x0A, 0x00, 0x40, 0x00, 0x01, 0x3f, 64793},
++	{0x0B, 0x00, 0x40, 0x14, 0x01, 0x3f, 72266},
++	{0x0C, 0x00, 0x50, 0x00, 0x02, 0x16, 79739},
++	{0x0D, 0x00, 0x50, 0x18, 0x02, 0x16, 88754},
++	{0x0E, 0x00, 0x60, 0x00, 0x02, 0x35, 97768},
++	{0x0F, 0x00, 0x60, 0x18, 0x02, 0x35, 106442},
++	{0x10, 0x00, 0x70, 0x00, 0x03, 0x16, 115115},
++	{0x11, 0x00, 0x70, 0x14, 0x03, 0x16, 122907},
++	{0x12, 0x00, 0x80, 0x00, 0x04, 0x02, 130699},
++	{0x13, 0x00, 0x80, 0x14, 0x04, 0x02, 138382},
++	{0x14, 0x00, 0x90, 0x00, 0x04, 0x31, 146065},
++	{0x15, 0x00, 0x90, 0x18, 0x04, 0x31, 154815},
++	{0x16, 0x00, 0xa0, 0x00, 0x05, 0x32, 163565},
++	{0x17, 0x00, 0xa0, 0x14, 0x05, 0x32, 171002},
++	{0x18, 0x00, 0xb0, 0x00, 0x06, 0x35, 178439},
++	{0x19, 0x00, 0xb0, 0x18, 0x06, 0x35, 186777},
++	{0x1A, 0x00, 0xc0, 0x00, 0x08, 0x04, 195116},
++	{0x1B, 0x00, 0xc0, 0x14, 0x08, 0x04, 202863},
++	{0x1C, 0x00, 0x5a, 0x00, 0x09, 0x19, 210610},
++	{0x1D, 0x00, 0x5a, 0x14, 0x09, 0x19, 216774},
++	{0x1E, 0x00, 0x5a, 0x20, 0x09, 0x19, 222937},
++	{0x1F, 0x00, 0x83, 0x00, 0x0b, 0x0f, 229100},
++	{0x20, 0x00, 0x83, 0x14, 0x0b, 0x0f, 236816},
++	{0x21, 0x00, 0x93, 0x00, 0x0d, 0x12, 244531},
++	{0x22, 0x00, 0x93, 0x18, 0x0d, 0x12, 252603},
++	{0x23, 0x00, 0x84, 0x00, 0x10, 0x00, 260674},
++	{0x24, 0x00, 0x84, 0x14, 0x10, 0x00, 268190},
++	{0x25, 0x00, 0x94, 0x00, 0x12, 0x3a, 275706},
++	{0x26, 0x00, 0x94, 0x18, 0x12, 0x3a, 283977},
++	{0x27, 0x01, 0x2c, 0x00, 0x1a, 0x02, 292248},
++	{0x28, 0x01, 0x2c, 0x18, 0x1a, 0x02, 300872},
++	{0x29, 0x01, 0x3c, 0x00, 0x1b, 0x20, 309495},
++	{0x2A, 0x01, 0x3c, 0x18, 0x1b, 0x20, 317963},
++	{0x2B, 0x00, 0x8c, 0x00, 0x20, 0x0f, 326431},
++	{0x2C, 0x00, 0x8c, 0x18, 0x20, 0x0f, 334373},
++	{0x2D, 0x00, 0x9c, 0x00, 0x26, 0x07, 342315},
++	{0x2E, 0x00, 0x9c, 0x18, 0x26, 0x07, 350616},
++	{0x2F, 0x02, 0x64, 0x00, 0x36, 0x21, 358918},
++	{0x30, 0x02, 0x64, 0x18, 0x36, 0x21, 366834},
++	{0x31, 0x02, 0x74, 0x00, 0x37, 0x3a, 374750},
++	{0x32, 0x02, 0x74, 0x18, 0x37, 0x3a, 382687},
++	{0x33, 0x00, 0xc6, 0x00, 0x3d, 0x02, 390624},
++	{0x34, 0x00, 0xc6, 0x18, 0x3d, 0x02, 399464},
++	{0x35, 0x00, 0xdc, 0x00, 0x3f, 0x3f, 408304},
++	{0x36, 0x00, 0xdc, 0x18, 0x3f, 0x3f, 416945},
++	{0x37, 0x02, 0x85, 0x00, 0x3f, 0x3f, 421145},
++	{0x38, 0x02, 0x95, 0x00, 0x3f, 0x3f, 440355},
++	{0x39, 0x00, 0xce, 0x00, 0x3f, 0x3f, 444858}
++};
++
++
++static inline struct gc2053_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct gc2053_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct gc2053_info, hdl)->sd;
++}
++struct regval_list {
++	uint8_t reg_num;
++	unsigned char value;
++};
++
++static struct regval_list gc2053_init_regs_1920_1080_25fps_mipi[] = {
++	/*system*/
++	{0xfe, 0x80},
++	{0xfe, 0x80},
++	{0xfe, 0x80},
++	{0xfe, 0x00},
++	{0xf2, 0x00},
++	{0xf3, 0x00},
++	{0xf4, 0x36},
++	{0xf5, 0xc0},
++	{0xf6, 0x44},
++	{0xf7, 0x01},
++	{0xf8, 0x63},
++	{0xf9, 0x40},
++	{0xfc, 0x8e},
++	/*CISCTL & ANALOG*/
++	{0xfe, 0x00},
++	{0x87, 0x18},
++	{0xee, 0x30},
++	{0xd0, 0xb7},
++	{0x03, 0x04},
++	{0x04, 0x60},
++	{0x05, 0x04},
++	{0x06, 0x4c},
++	{0x07, 0x00},
++	{0x08, 0x11},
++	{0x09, 0x00},
++	{0x0a, 0x02},
++	{0x0b, 0x00},
++	{0x0c, 0x02},
++	{0x0d, 0x04},
++	{0x0e, 0x40},
++	{0x12, 0xe2},
++	{0x13, 0x16},
++	{0x19, 0x0a},
++	{0x21, 0x1c},
++	{0x28, 0x0a},
++	{0x29, 0x24},
++	{0x2b, 0x04},
++	{0x32, 0xf8},
++	{0x37, 0x03},
++	{0x39, 0x15},
++	{0x43, 0x07},
++	{0x44, 0x40},
++	{0x46, 0x0b},
++	{0x4b, 0x20},
++	{0x4e, 0x08},
++	{0x55, 0x20},
++	{0x66, 0x05},
++	{0x67, 0x05},
++	{0x77, 0x01},
++	{0x78, 0x00},
++	{0x7c, 0x93},
++	{0x8c, 0x12},
++	{0x8d, 0x92},
++	{0x90, 0x00},/*use frame length to change fps*/
++	{0x41, 0x05},
++	{0x42, 0x46},/*vts for 25fps mipi*/
++	{0x9d, 0x10},
++	{0xce, 0x7c},
++	{0xd2, 0x41},
++	{0xd3, 0xdc},
++	{0xe6, 0x50},
++	/*gain*/
++	{0xb6, 0xc0},
++	{0xb0, 0x70},
++	{0xb1, 0x01},
++	{0xb2, 0x00},
++	{0xb3, 0x00},
++	{0xb4, 0x00},
++	{0xb8, 0x01},
++	{0xb9, 0x00},
++	/*blk*/
++	{0x26, 0x30},
++	{0xfe, 0x01},
++	{0x40, 0x23},
++	{0x55, 0x07},
++	{0x60, 0x40},
++	{0xfe, 0x04},
++	{0x14, 0x78},
++	{0x15, 0x78},
++	{0x16, 0x78},
++	{0x17, 0x78},
++	/*window*/
++	{0xfe, 0x01},
++	{0x92, 0x00},
++	{0x94, 0x03},
++	{0x95, 0x04},
++	{0x96, 0x38},
++	{0x97, 0x07},
++	{0x98, 0x80},
++	/*ISP*/
++	{0xfe, 0x01},
++	{0x01, 0x05},
++	{0x02, 0x89},
++	{0x04, 0x01},
++	{0x07, 0xa6},
++	{0x08, 0xa9},
++	{0x09, 0xa8},
++	{0x0a, 0xa7},
++	{0x0b, 0xff},
++	{0x0c, 0xff},
++	{0x0f, 0x00},
++	{0x50, 0x1c},
++	{0x89, 0x03},
++	{0xfe, 0x04},
++	{0x28, 0x86},
++	{0x29, 0x86},
++	{0x2a, 0x86},
++	{0x2b, 0x68},
++	{0x2c, 0x68},
++	{0x2d, 0x68},
++	{0x2e, 0x68},
++	{0x2f, 0x68},
++	{0x30, 0x4f},
++	{0x31, 0x68},
++	{0x32, 0x67},
++	{0x33, 0x66},
++	{0x34, 0x66},
++	{0x35, 0x66},
++	{0x36, 0x66},
++	{0x37, 0x66},
++	{0x38, 0x62},
++	{0x39, 0x62},
++	{0x3a, 0x62},
++	{0x3b, 0x62},
++	{0x3c, 0x62},
++	{0x3d, 0x62},
++	{0x3e, 0x62},
++	{0x3f, 0x62},
++	/****DVP & MIPI****/
++	{0xfe, 0x01},
++	{0x9a, 0x06},
++	{0xfe, 0x00},
++	{0x7b, 0x2a},
++	{0x23, 0x2d},
++	{0xfe, 0x03},
++	{0x01, 0x27},
++	{0x02, 0x56},
++	{0x03, 0x8e},/*0xb6*/
++	{0x12, 0x80},
++	{0x13, 0x07},
++	{0x15, 0x12},
++	{0xfe, 0x00},
++	{0x3e, 0x91},
++
++	{GC2053_REG_END, 0x00},	/* END MARKER */
++};
++
++/*
++ * the part of driver was fixed.
++ */
++
++static struct regval_list gc2053_stream_on_mipi[] = {
++	{GC2053_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list gc2053_stream_off_mipi[] = {
++	{GC2053_REG_END, 0x00},	/* END MARKER */
++};
++
++static int gc2053_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct gc2053_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 1,
++			.buf	= &reg,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret = 0;
++
++	printk("i2c device addr : 0x%x~~~~~~~~~~~~~\n",client->addr);
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int gc2053_write(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char value)
++{
++	struct gc2053_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {reg, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 2,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int gc2053_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != GC2053_REG_END) {
++		if (vals->reg_num == GC2053_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = gc2053_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++/*
++ * Write a list of register settings; ff/ff stops the process.
++ */
++static int gc2053_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != GC2053_REG_END) {
++		if (vals->reg_num == GC2053_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = gc2053_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int gc2053_reset(struct v4l2_subdev *sd, u32 val)
++{
++	return 0;
++}
++
++static int gc2053_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	return 0;
++}
++
++static int gc2053_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct gc2053_info *info = to_state(sd);
++	int ret = 0;
++	printk("%s:~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n",__func__);
++	ret = gc2053_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++
++static int gc2053_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++	ret = gc2053_read(sd, 0xf0, &v);
++	printk("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != GC2053_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = gc2053_read(sd, 0xf1, &v);
++	printk("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != GC2053_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	return 0;
++}
++
++static struct gc2053_win_size gc2053_win_sizes[] = {
++	{
++		.mipi_cfg.clk			= 600,	//data rate = 600Mbps/lane, clk is about 600Mbps.
++		.mipi_cfg.twidth		= 1920,
++		.mipi_cfg.theight		= 1080,
++		.mipi_cfg.mipi_mode		= SENSOR_MIPI_OTHER_MODE,
++		.mipi_cfg.mipi_vcomp_en		= 0,
++		.mipi_cfg.mipi_hcomp_en		= 0,
++		.mipi_cfg.mipi_crop_start0x	= 0,
++		.mipi_cfg.mipi_crop_start0y	= 0,
++		.mipi_cfg.mipi_crop_start1x	= 0,
++		.mipi_cfg.mipi_crop_start1y	= 0,
++		.mipi_cfg.mipi_crop_start2x	= 0,
++		.mipi_cfg.mipi_crop_start2y	= 0,
++		.mipi_cfg.mipi_crop_start3x	= 0,
++		.mipi_cfg.mipi_crop_start3y	= 0,
++		.mipi_cfg.hcrop_diff_en		= 0,
++		.mipi_cfg.line_sync_mode	= 0,
++		.mipi_cfg.work_start_flag	= 0,
++		.mipi_cfg.data_type_en		= 0,
++		.mipi_cfg.data_type_value	= 0,
++		.mipi_cfg.del_start		= 0,
++		.mipi_cfg.sensor_frame_mode	= TX_SENSOR_DEFAULT_FRAME_MODE,
++		.mipi_cfg.sensor_fid_mode	= 0,
++		.mipi_cfg.sensor_mode		= TX_SENSOR_DEFAULT_MODE,
++		.mipi_cfg.sensor_csi_fmt	= TX_SENSOR_RAW10,
++
++		.width				= 1920,
++		.height				= 1080,
++		.fps				= 25 << 16 | 1,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= gc2053_init_regs_1920_1080_25fps_mipi,
++
++	},
++};
++
++static int gc2053_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_gc2053_FMTS)
++		return -EINVAL;
++
++	code->code = gc2053_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int gc2053_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct gc2053_format_struct *ovfmt;
++	struct gc2053_win_size *wsize;
++	struct gc2053_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int gc2053_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct gc2053_info *info = to_state(sd);
++	struct gc2053_win_size *wsize = info->win;
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = wsize->width;
++	fmt->height = wsize->height;
++	fmt->code = wsize->mbus_code;
++	fmt->colorspace = wsize->colorspace;
++	*(unsigned int *)fmt->reserved = &wsize->sensor_info;
++
++	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int gc2053_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2053_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2053_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2053_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int gc2053_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int gc2053_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(gc2093_again_lut); i++) {
++		lut = &gc2093_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->index;
++		}
++	}
++
++	/*last value.*/
++	return lut->index;
++}
++static int gc2053_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	struct gc2053_info *info = to_state(sd);
++	unsigned char v = 0;
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++	return ret;
++}
++/*set analog gain db value, map value to sensor register.*/
++static int gc2053_s_again(struct v4l2_subdev *sd, int again)
++{
++	struct gc2053_info *info = to_state(sd);
++	struct again_lut *val_lut = gc2053_again_lut;
++	unsigned int reg_value = 0;
++	int ret = 0;
++	if(again < info->again->minimum || again > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(again);
++	}
++
++	ret = gc2053_write(sd, 0xfe, 0x00);
++	ret += gc2053_write(sd, 0xb4, val_lut[again].regb4);
++	ret += gc2053_write(sd, 0xb3, val_lut[again].regb3);
++	ret += gc2053_write(sd, 0xb2, val_lut[again].regb2);
++	ret += gc2053_write(sd, 0xb8, val_lut[again].dpc);
++	ret += gc2053_write(sd, 0xb9, val_lut[again].blc);
++	if(ret < 0){
++		printk("%s : gc2053_write error %d~~~~\n",__func__,__LINE__);
++		return ret;
++	}
++
++	return 0;
++
++}
++
++/*
++ * Tweak autogain.
++ */
++static int gc2053_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2053_s_exp(struct v4l2_subdev *sd, int value)
++{
++	struct gc2053_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = gc2053_write(sd, 0x04, value&0xff);
++	ret += gc2053_write(sd, 0x03, (value&0x3f00)>>8);
++
++	return ret;
++}
++
++static int gc2053_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct gc2053_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return gc2053_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return gc2053_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int gc2053_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct gc2053_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return gc2053_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return gc2053_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return gc2053_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return gc2053_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* gc2053_s_gain turns off auto gain */
++			return gc2053_s_gain(sd, info->gain->val);
++		}
++		return gc2053_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return gc2053_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return gc2053_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return gc2053_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops gc2053_ctrl_ops = {
++	.s_ctrl = gc2053_s_ctrl,
++	.g_volatile_ctrl = gc2053_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int gc2053_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = gc2053_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int gc2053_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	gc2053_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int gc2053_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct gc2053_info *info = to_state(sd);
++	int ret = 0;
++	printk("%s:~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n",__func__);
++	if (enable) {
++		ret = gc2053_write_array(sd, gc2053_stream_on_mipi);
++		printk("gc2053 stream on\n");
++
++	}
++	else {
++		ret = gc2053_write_array(sd, gc2053_stream_off_mipi);
++		printk("gc2053 stream off\n");
++	}
++	return ret;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops gc2053_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = gc2053_g_register,
++	.s_register = gc2053_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops gc2053_video_ops = {
++	.s_stream = gc2053_s_stream,
++};
++
++static const struct v4l2_subdev_pad_ops gc2053_pad_ops = {
++	//.enum_frame_interval = gc2053_enum_frame_interval,
++	//.num_frame_size = gc2053_enum_frame_size,
++	//.enum_mbus_code = gc2053_enum_mbus_code,
++	.set_fmt = gc2053_set_fmt,
++	.get_fmt = gc2053_get_fmt,
++};
++
++static const struct v4l2_subdev_ops gc2053_ops = {
++	.core = &gc2053_core_ops,
++	.video = &gc2053_video_ops,
++	.pad = &gc2053_pad_ops,
++};
++
++void gc2053_power_init_seq(struct gc2053_info *info)
++{
++	*(volatile unsigned int*)0xb0010100 = 0x1;
++	//gpio_direction_output(4,0);
++	udelay(50);
++	gpio_direction_output(info->pwen.pin,info->pwen.active_level);
++	udelay(50);
++
++	gpio_direction_output(info->reset.pin,!info->reset.active_level);
++	msleep(10);
++	gpio_direction_output(info->reset.pin,info->reset.active_level);
++	msleep(20);
++	gpio_direction_output(info->reset.pin,!info->reset.active_level);
++	msleep(50);
++
++	gpio_direction_output(info->pwdn.pin,info->pwdn.active_level);
++	msleep(10);
++	gpio_direction_output(info->pwdn.pin,!info->pwdn.active_level);
++	msleep(10);
++	gpio_direction_output(info->pwdn.pin,info->pwdn.active_level);
++	msleep(10);
++}
++/* ----------------------------------------------------------------------- */
++
++static int gc2053_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	printk("~~~%s:%d~~~=====================================\n", __func__, __LINE__);
++	struct v4l2_fract tpf;
++	struct v4l2_subdev *sd;
++	struct gc2053_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++	unsigned long rate;
++	unsigned char value;
++	int mclk_index = -1;
++	printk("~~~%s:%d~~~\n", __func__, __LINE__);
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,pwen-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->pwen.pin = gpio;
++		info->pwen.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,pwdn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->pwdn.pin = gpio;
++		info->pwdn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	printk("gpio set ok ~~~%s:%d~~~\n", __func__, __LINE__);
++
++	gc2053_power_init_seq(info);
++	v4l2_i2c_subdev_init(sd, client, &gc2053_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++#if 1
++
++#if 1
++	char id_div[9];
++	char id_mux[9];
++	printk("%s:%d\n", __func__, __LINE__);
++	of_property_read_u32(client->dev.of_node, "ingenic,mclk", &mclk_index);
++	if(mclk_index == 0) {
++		memcpy(id_div, "div_cim0", sizeof(id_div));
++		memcpy(id_mux, "mux_cim0", sizeof(id_mux));
++	} else if(mclk_index == 1) {
++		memcpy(id_div, "div_cim1", sizeof(id_div));
++		memcpy(id_mux, "mux_cim1", sizeof(id_mux));
++	} else if(mclk_index == 2) {
++		memcpy(id_div, "div_cim2", sizeof(id_div));
++		memcpy(id_mux, "mux_cim2", sizeof(id_mux));
++	} else
++		printk("Unkonwn mclk index\n");
++
++
++	info->clk = v4l2_clk_get(&client->dev, id_div);
++#endif
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++
++	ret = v4l2_clk_set_rate(info->clk, 27000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++#endif
++
++#if 1
++	/* Make sure it's an gc2053 */
++	ret = gc2053_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an gc2053 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++#if 1
++	/*IRCUT ctl 0:off 1:on*/
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &gc2053_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &gc2053_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &gc2053_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &gc2053_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &gc2053_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &gc2053_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 444858, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &gc2053_ctrl_ops,
++			V4L2_CID_EXPOSURE, 1, 1350 - 4, 1, 1000);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->win = &gc2053_win_sizes[0];
++
++	gc2053_init(sd, 1);
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	/* test image   */
++//	gc2053_write(sd,0x018c,0x01);
++	dev_info(&client->dev, "gc2053 Probed\n");
++	return 0;
++#endif
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int gc2053_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct gc2053_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id gc2053_id[] = {
++	{ "gc2053", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, gc2053_id);
++
++static const struct of_device_id gc2053_of_match[] = {
++	{.compatible = "gc2053", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, gc2053_of_match);
++
++
++static struct i2c_driver gc2053_driver = {
++	.driver = {
++		.name	= "gc2053",
++		.of_match_table = of_match_ptr(gc2053_of_match),
++	},
++	.probe		= gc2053_probe,
++	.remove		= gc2053_remove,
++	.id_table	= gc2053_id,
++};
++
++module_i2c_driver(gc2053_driver);
++MODULE_DESCRIPTION("A low-level driver for gc2053 sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp-v2/gc2093.c b/module_drivers/drivers/media/i2c/ingenic-isp-v2/gc2093.c
+new file mode 100644
+index 000000000..6fee0e215
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp-v2/gc2093.c
+@@ -0,0 +1,1255 @@
++/*
++ * A V4L2 driver for OmniVision gc2093 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++#include <linux/clk.h>
++
++#include <isp-sensor.h>
++
++#define GC2093_CHIP_ID_H	(0x20)
++#define GC2093_CHIP_ID_L	(0x93)
++#define GC2093_REG_CHIP_ID_HIGH         0x03f0
++#define GC2093_REG_CHIP_ID_LOW          0x03f1
++
++
++#define GC2093_REG_END		0xffff
++#define GC2093_REG_DELAY	0x00
++#define GC2093_PAGE_REG	    0xfd
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++
++struct gc2093_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++};
++
++struct gc2093_gpio {
++	int pin;
++	int active_level;
++};
++
++struct gc2093_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++	struct v4l2_ctrl *again_short;
++
++	struct v4l2_clk *clk;
++	/* struct clk *sclka; */
++
++	struct v4l2_ctrl *exposure;
++	struct v4l2_ctrl *exposure_short;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct gc2093_win_size *win;
++
++	struct gc2093_gpio reset;
++	struct gc2093_gpio pwdn;
++	struct gc2093_gpio pwen;
++};
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int index;
++	unsigned char regb0;
++	unsigned char regb1;
++	unsigned int  regb2;
++	unsigned char regb3;
++	unsigned char regb4;
++	unsigned char regb5;
++	unsigned char regb6;
++	unsigned char regb7;
++
++	unsigned int gain;
++};
++
++struct again_lut gc2093_again_lut[] = {
++	{0x0,0x00,0x00,0x01,0x00,0x68,0x07,0x00,0xf8,0},
++	{0x1,0x00,0x10,0x01,0x0c,0x68,0x07,0x00,0xf8,14997},
++	{0x2,0x00,0x20,0x01,0x1b,0x6c,0x07,0x00,0xf8,32233},
++	{0x3,0x00,0x30,0xf01,0x2c,0x6c,0x07,0x00,0xf8,46808},
++	{0x4,0x00,0x40,0x01,0x3f,0x7c,0x07,0x00,0xf8,60995},
++	{0x5,0x00,0x50,0x02,0x16,0x7c,0x07,0x00,0xf8,75348},
++	{0x6,0x00,0x60,0x02,0x35,0x7c,0x08,0x00,0xf9,90681},
++	{0x7,0x00,0x70,0x03,0x16,0x7c,0x0b,0x00,0xfc,104361},
++	{0x8,0x00,0x80,0x04,0x02,0x7c,0x0d,0x00,0xfe,118021},
++	{0x9,0x00,0x90,0x04,0x31,0x7c,0x0f,0x08,0x00,131438},
++	{0xA,0x00,0xa0,0x05,0x32,0x7c,0x11,0x08,0x02,145749},
++	{0xB,0x00,0xb0,0x06,0x35,0x7c,0x14,0x08,0x05,159553},
++	{0xC,0x00,0xc0,0x08,0x04,0x7c,0x16,0x08,0x07,172553},
++	{0xD,0x00,0x5a,0x09,0x19,0x7c,0x18,0x08,0x09,183132},
++	{0xE,0x00,0x83,0x0b,0x0f,0x7c,0x1b,0x08,0x0c,198614},
++	{0xF,0x00,0x93,0x0d,0x12,0x7c,0x1e,0x08,0x0f,212697},
++	{0x10,0x00,0x84,0x10,0x00,0x7c,0x22,0x08,0x13,226175},
++	{0x11,0x00,0x94,0x12,0x3a,0x7c,0x26,0x08,0x17,240788},
++	{0x12,0x00,0x5d,0x1a,0x02,0x7c,0x30,0x08,0x21,271536},
++	{0x13,0x00,0x9b,0x1b,0x20,0x7c,0x30,0x08,0x21,272451},
++	{0x14,0x00,0x8c,0x20,0x0f,0x7c,0x35,0x08,0x26,287144},
++	{0x15,0x00,0x9c,0x26,0x07,0x7c,0x3b,0x08,0x2c,302425},
++	{0x16,0x00,0xB6,0x36,0x21,0x7c,0x43,0x08,0x34,334228},
++	{0x17,0x00,0xad,0x37,0x3a,0x7c,0x43,0x08,0x34,351574},
++	{0x18,0x00,0xbd,0x3d,0x02,0x7c,0x43,0x08,0x34,367506},
++};
++
++
++static inline struct gc2093_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct gc2093_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct gc2093_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++static struct regval_list gc2093_init_regs_1920_1080_60fps_mipi[] = {
++       /****system****/
++       {0x03fe, 0xf0},
++       {0x03fe, 0xf0},
++       {0x03fe, 0xf0},
++       {0x03fe, 0x00},
++       {0x03f2, 0x00},
++       {0x03f3, 0x00},
++       {0x03f4, 0x36},
++       {0x03f5, 0xc0},
++       {0x03f6, 0x0B},
++       {0x03f7, 0x01},
++      // {0x03f8, 0x58}, //24Mhz
++       {0x03f8, 0x58},  //27Mhz
++       {0x03f9, 0x40},
++       {0x03fc, 0x8e},
++       /****CISCTL & NALOG****/
++       {0x0087, 0x18},
++       {0x00ee, 0x30},
++       {0x00d0, 0xbf},
++       {0x01a0, 0x00},
++       {0x01a4, 0x40},
++       {0x01a5, 0x40},
++       {0x01a6, 0x40},
++       {0x01af, 0x09},
++       {0x0001, 0x00},
++       {0x0002, 0x02},
++       {0x0003, 0x04},
++       {0x0004, 0x02},
++       {0x0005, 0x02},
++       {0x0006, 0x94},
++       {0x0007, 0x00},
++       {0x0008, 0x11},
++       {0x0009, 0x00},
++       {0x000a, 0x02},
++       {0x000b, 0x00},
++       {0x000c, 0x04},
++       {0x000d, 0x04},
++       {0x000e, 0x40},
++       {0x000f, 0x07},
++       {0x0010, 0x8c},
++       {0x0013, 0x15},
++       {0x0019, 0x0c},
++       {0x0041, 0x04},
++	{0x0042, 0xE2},   //frame length 0x04e2=1250
++
++      // {0x0041, 0x05},    //or dorp
++      // {0x0042, 0xE6},    //frame length 0x05E6=1350
++
++       {0x0053, 0x60},
++       {0x008d, 0x92},
++       {0x0090, 0x00},
++       {0x00c7, 0xe1},
++       {0x001b, 0x73},
++       {0x0028, 0x0d},
++       {0x0029, 0x24},
++       {0x002b, 0x04},
++       {0x002e, 0x23},
++       {0x0037, 0x03},
++       {0x0043, 0x04},
++       {0x0044, 0x28},
++       {0x004a, 0x01},
++       {0x004b, 0x20},
++       {0x0055, 0x28},
++       {0x0066, 0x3f},
++       {0x0068, 0x3f},
++       {0x006b, 0x44},
++       {0x0077, 0x00},
++       {0x0078, 0x20},
++       {0x007c, 0xa1},
++       {0x00ce, 0x7c},
++       {0x00d3, 0xd4},
++       {0x00e6, 0x50},
++       /****gain****/
++       {0x00b6, 0xc0},
++       {0x00b0, 0x68},    //0x60
++
++       {0x00b3,0x00},
++       {0x00b8,0x01},
++       {0x00b9,0x00},
++       {0x00b1,0x01},
++       {0x00b2,0x00},
++
++       /*****isp****/
++       //{0x0101, 0x0c},
++       {0x0102, 0x89},
++       {0x0104, 0x01},
++       {0x010f, 0x00},
++       {0x0158, 0x00},
++       {/*dark sun*/},
++       {0x0123, 0x08},
++       {0x0123, 0x00},
++       {0x0120, 0x01},
++       {0x0121, 0x04},
++       {0x0122, 0xd8},
++       {0x0124, 0x03},
++       {0x0125, 0xff},
++       {0x001a, 0x8c},
++       {0x00c6, 0xe0},
++       /****blk****/
++       {0x0026, 0x30},
++       {0x0142, 0x00},
++       {0x0149, 0x1e},
++       {0x014a, 0x0f},
++       {0x014b, 0x00},
++       {0x0155, 0x07},
++       {0x0414, 0x78},
++       {0x0415, 0x78},
++       {0x0416, 0x78},
++       {0x0417, 0x78},
++       {0x0454, 0x78},
++       {0x0455, 0x78},
++       {0x0456, 0x78},
++       {0x0457, 0x78},
++       {0x04e0, 0x18},
++       /****window****/
++       {0x0192, 0x02},
++       {0x0194, 0x03},
++       {0x0195, 0x04},
++       {0x0196, 0x38},
++       {0x0197, 0x07},
++       {0x0198, 0x80},
++       /****DVP & MIP*****/
++       {0x019a, 0x06},
++       {0x007b, 0x2a},
++       {0x0023, 0x2d},
++       {0x0201, 0x27},
++       {0x0202, 0x56},
++       //{0x0203, 0xb6},     //try 0xce or 0x8e  or drop
++       {0x0203, 0x8e},     //try 0xce or 0x8e  or drop
++       {0x0212, 0x80},
++       {0x0213, 0x07},
++       {0x0215, 0x10},
++       {0x003e, 0x91},
++       {GC2093_REG_END, 0x00},	/* END MARKER */
++};
++
++#if 1
++static struct regval_list gc2093_init_regs_1920_1080_30fps_mipi_lin[] = {
++	{0x03fe, 0xf0},
++	{0x03fe, 0xf0},
++	{0x03fe, 0xf0},
++	{0x03fe, 0x00},
++	{0x03f2, 0x00},
++	{0x03f3, 0x00},
++	{0x03f4, 0x36},
++	{0x03f5, 0xc0},
++	{0x03f6, 0x0A},
++	{0x03f7, 0x01},
++	{0x03f8, 0x24},
++	{0x03f9, 0x10},
++	{0x03fc, 0x8e},
++	/****CISCTL & ANALOG****/
++	{0x0087, 0x18},
++	{0x00ee, 0x30},
++	{0x00d0, 0xbf},
++	{0x01a0, 0x00},
++	{0x01a4, 0x40},
++	{0x01a5, 0x40},
++	{0x01a6, 0x40},
++	{0x01af, 0x09},
++	{0x0001, 0x00},
++	{0x0002, 0x02},
++	{0x0003, 0x04},
++	{0x0004, 0x00},
++	{0x0005, 0x02},
++	{0x0006, 0xd5},
++	{0x0007, 0x00},
++	{0x0008, 0x8e},//vb=142
++	{0x0009, 0x00},
++	{0x000a, 0x02},
++	{0x000b, 0x00},
++	{0x000c, 0x04},
++	{0x000d, 0x04},
++	{0x000e, 0x40},
++	{0x000f, 0x07},
++	{0x0010, 0x8c},
++	{0x0013, 0x15},
++	{0x0019, 0x0c},
++//	{0x0041, 0x04},//1250
++//	{0x0042, 0xe2},//1250
++	{0x0041, 0x05},//1350 jz
++	{0x0042, 0x46},//1350 jz
++	{0x0053, 0x60},
++	{0x008d, 0x92},
++	{0x0090, 0x00},
++	{0x00c7, 0xe1},
++	{0x001b, 0x73},
++	{0x0028, 0x0d},
++	{0x0029, 0x24},
++	{0x002b, 0x04},
++	{0x002e, 0x23},
++	{0x0037, 0x03},
++	{0x0043, 0x04},
++	{0x0044, 0x38},
++	{0x004a, 0x01},
++	{0x004b, 0x28},
++	{0x0055, 0x38},
++	{0x006b, 0x44},
++	{0x0077, 0x00},
++	{0x0078, 0x20},
++	{0x007c, 0xa1},
++	{0x00ce, 0x7c},
++	{0x00d3, 0xd4},
++	{0x00e6, 0x50},
++	/*gain*/
++	{0x00b6, 0xc0},
++	{0x00b0, 0x60},
++	{0x00b3, 0x00},
++	{0x00b8, 0x01},
++	{0x00b9, 0x00},
++	{0x00b1, 0x01},
++	{0x00b2, 0x00},
++	/*isp*/
++	{0x0102, 0x89},
++	{0x0104, 0x01},
++	{0x010e, 0x00},//jz wdr -> lin
++	{0x010f, 0x00},
++	{0x0158, 0x00},
++	/*dark sun*/
++	{0x0123, 0x08},
++	{0x0123, 0x00},
++	{0x0120, 0x00},
++	{0x0121, 0x00},
++	{0x0122, 0x0f},
++	{0x0124, 0x03},
++	{0x0125, 0xff},
++	{0x0126, 0x3c},
++	{0x001a, 0x8c},
++	{0x00c6, 0xe0},
++	/*blk*/
++	{0x0026, 0x30},
++	{0x0142, 0x00},
++	{0x0149, 0x1e},
++	{0x014a, 0x07},
++	{0x014b, 0x80},
++	{0x0155, 0x00},
++	{0x0414, 0x78},
++	{0x0415, 0x78},
++	{0x0416, 0x78},
++	{0x0417, 0x78},
++	{0x04e0, 0x18},
++	/*window*/
++	{0x0192, 0x02},
++	{0x0194, 0x03},
++	{0x0195, 0x04},
++	{0x0196, 0x38},
++	{0x0197, 0x07},
++	{0x0198, 0x80},
++	{0x01b0, 0x01},
++	{0x01b1, 0x00},
++	{0x01b2, 0x20},
++	{0x01b3, 0x00},
++	{0x01b4, 0xf0},
++	{0x01b5, 0x80},
++	{0x01b6, 0x05},
++	{0x01b8, 0x01},
++	{0x01b9, 0xe0},
++	{0x01ba, 0x01},
++	{0x01bb, 0x80},
++	/****DVP & MIPI****/
++	{0x019a, 0x06},
++	{0x007b, 0x2a},
++	{0x0023, 0x2d},
++	{0x0201, 0x27},
++	{0x0202, 0x56},
++//	{0x0203, 0xb6},
++	{0x0203, 0x8e},
++	{0x0212, 0x80},
++	{0x0213, 0x07},
++	{0x0215, 0x12},
++	/****HDR EN****/
++	{0x0027, 0x70},//jz
++	{0x0215, 0x12},//jz
++	{0x024d, 0x00},//jz
++	{0x003e, 0x91},
++	{GC2093_REG_END, 0x00}, /* END MARKER */
++};
++#endif
++
++static struct regval_list gc2093_init_regs_1920_1080_15fps_mipi_wdr[] = {
++	{0x03fe, 0xf0},
++	{0x03fe, 0xf0},
++	{0x03fe, 0xf0},
++	{0x03fe, 0x00},
++	{0x03f2, 0x00},
++	{0x03f3, 0x00},
++	{0x03f4, 0x36},
++	{0x03f5, 0xc0},
++	{0x03f6, 0x0A},
++	{0x03f7, 0x01},
++	{0x03f8, 0x24},
++	{0x03f9, 0x10},
++	{0x03fc, 0x8e},
++	/****CISCTL & ANALOG****/
++	{0x0087, 0x18},
++	{0x00ee, 0x30},
++	{0x00d0, 0xbf},
++	{0x01a0, 0x00},
++	{0x01a4, 0x40},
++	{0x01a5, 0x40},
++	{0x01a6, 0x40},
++	{0x01af, 0x09},
++	{0x0001, 0x00},
++	{0x0002, 0x02},
++	{0x0003, 0x04},
++	{0x0004, 0x00},
++	{0x0005, 0x02},
++	{0x0006, 0xd5},
++	{0x0007, 0x00},
++	{0x0008, 0x8e},//vb=142
++	{0x0009, 0x00},
++	{0x000a, 0x02},
++	{0x000b, 0x00},
++	{0x000c, 0x04},
++	{0x000d, 0x04},
++	{0x000e, 0x40},
++	{0x000f, 0x07},
++	{0x0010, 0x8c},
++	{0x0013, 0x15},
++	{0x0019, 0x0c},
++//	{0x0041, 0x04},//1250
++//	{0x0042, 0xe2},//1250
++	{0x0041, 0x05},//1350 jz
++	{0x0042, 0x46},//1350 jz
++	{0x0053, 0x60},
++	{0x008d, 0x92},
++	{0x0090, 0x00},
++	{0x00c7, 0xe1},
++	{0x001b, 0x73},
++	{0x0028, 0x0d},
++	{0x0029, 0x24},
++	{0x002b, 0x04},
++	{0x002e, 0x23},
++	{0x0037, 0x03},
++	{0x0043, 0x04},
++	{0x0044, 0x38},
++	{0x004a, 0x01},
++	{0x004b, 0x28},
++	{0x0055, 0x38},
++	{0x006b, 0x44},
++	{0x0077, 0x00},
++	{0x0078, 0x20},
++	{0x007c, 0xa1},
++	{0x00ce, 0x7c},
++	{0x00d3, 0xd4},
++	{0x00e6, 0x50},
++	/*gain*/
++	{0x00b6, 0xc0},
++	{0x00b0, 0x60},
++	{0x00b3, 0x00},
++	{0x00b8, 0x01},
++	{0x00b9, 0x00},
++	{0x00b1, 0x01},
++	{0x00b2, 0x00},
++	/*isp*/
++	{0x0102, 0x89},
++	{0x0104, 0x01},
++	{0x010e, 0x01},
++	{0x010f, 0x00},
++	{0x0158, 0x00},
++	/*dark sun*/
++	{0x0123, 0x08},
++	{0x0123, 0x00},
++	{0x0120, 0x00},
++	{0x0121, 0x00},
++	{0x0122, 0x0f},
++	{0x0124, 0x03},
++	{0x0125, 0xff},
++	{0x0126, 0x3c},
++	{0x001a, 0x8c},
++	{0x00c6, 0xe0},
++	/*blk*/
++	{0x0026, 0x30},
++	{0x0142, 0x00},
++	{0x0149, 0x1e},
++	{0x014a, 0x07},
++	{0x014b, 0x80},
++	{0x0155, 0x00},
++	{0x0414, 0x78},
++	{0x0415, 0x78},
++	{0x0416, 0x78},
++	{0x0417, 0x78},
++	{0x04e0, 0x18},
++	/*window*/
++	{0x0192, 0x02},
++	{0x0194, 0x03},
++	{0x0195, 0x04},
++	{0x0196, 0x38},
++	{0x0197, 0x07},
++	{0x0198, 0x80},
++	{0x01b0, 0x01},
++	{0x01b1, 0x00},
++	{0x01b2, 0x20},
++	{0x01b3, 0x00},
++	{0x01b4, 0xf0},
++	{0x01b5, 0x80},
++	{0x01b6, 0x05},
++	{0x01b8, 0x01},
++	{0x01b9, 0xe0},
++	{0x01ba, 0x01},
++	{0x01bb, 0x80},
++	/****DVP & MIPI****/
++	{0x019a, 0x06},
++	{0x007b, 0x2a},
++	{0x0023, 0x2d},
++	{0x0201, 0x27},
++	{0x0202, 0x56},
++//	{0x0203, 0xb6},
++	{0x0203, 0x8e},
++	{0x0212, 0x80},
++	{0x0213, 0x07},
++	{0x0215, 0x12},
++	/****HDR EN****/
++	{0x0027, 0x71},
++	{0x0215, 0x92},
++	{0x024d, 0x01},
++	{0x003e, 0x91},
++	{GC2093_REG_END, 0x00}, /* END MARKER */
++};
++
++/*
++ * the part of driver was fixed.
++ */
++
++static struct regval_list gc2093_stream_on_mipi[] = {
++	{GC2093_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list gc2093_stream_off_mipi[] = {
++	{GC2093_REG_END, 0x00},	/* END MARKER */
++};
++
++static int gc2093_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct gc2093_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret = 0;
++
++	printk("i2c device addr : 0x%x~~~~~~~~~~~~~\n",client->addr);
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int gc2093_write(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char value)
++{
++	struct gc2093_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3] = {(reg>>8)&0xff, reg&0xff, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 3,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int gc2093_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != GC2093_REG_END) {
++		if (vals->reg_num == GC2093_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = gc2093_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++/*
++ * Write a list of register settings; ff/ff stops the process.
++ */
++static int gc2093_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != GC2093_REG_END) {
++		if (vals->reg_num == GC2093_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = gc2093_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int gc2093_reset(struct v4l2_subdev *sd, u32 val)
++{
++	return 0;
++}
++
++static int gc2093_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	return 0;
++}
++
++static int gc2093_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct gc2093_info *info = to_state(sd);
++	int ret = 0;
++	printk("%s:~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n",__func__);
++	ret = gc2093_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++
++static int gc2093_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++	ret = gc2093_read(sd, 0x03f0, &v);
++	printk("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != GC2093_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = gc2093_read(sd, 0x03f1, &v);
++	printk("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != GC2093_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	return 0;
++}
++
++static struct gc2093_win_size gc2093_win_sizes[] = {
++	{
++		.sensor_info.mipi_cfg.clk			= 650,	//data rate = 650Mbps/lane, clk is about 650Mbps.
++		.sensor_info.mipi_cfg.twidth		= 1920,
++		.sensor_info.mipi_cfg.theight		= 1080,
++		.sensor_info.mipi_cfg.mipi_mode		= SENSOR_MIPI_OTHER_MODE,
++		.sensor_info.mipi_cfg.mipi_vcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_hcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3y	= 0,
++		.sensor_info.mipi_cfg.hcrop_diff_en		= 0,
++		.sensor_info.mipi_cfg.line_sync_mode	= 0,
++		.sensor_info.mipi_cfg.work_start_flag	= 0,
++		.sensor_info.mipi_cfg.data_type_en		= 0,
++		.sensor_info.mipi_cfg.data_type_value	= 0,
++		.sensor_info.mipi_cfg.del_start		= 0,
++		.sensor_info.mipi_cfg.sensor_frame_mode	= TX_SENSOR_DEFAULT_FRAME_MODE,
++		.sensor_info.mipi_cfg.sensor_fid_mode	= 0,
++		.sensor_info.mipi_cfg.sensor_mode		= TX_SENSOR_DEFAULT_MODE,
++		.sensor_info.mipi_cfg.sensor_csi_fmt	= TX_SENSOR_RAW10,
++		.sensor_info.fps				= 25 << 16 | 1,
++		.sensor_info.wdr_en				= 0,
++
++		.width				= 1920,
++		.height				= 1080,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		//.regs 		= gc2093_init_regs_1920_1080_30fps_mipi_lin,
++
++		.regs 		= gc2093_init_regs_1920_1080_60fps_mipi,
++	},
++#if 0
++	{
++		.sensor_info.mipi_cfg.twidth		= 1920,
++		.sensor_info.mipi_cfg.theight		= 1080,
++		.sensor_info.mipi_cfg.mipi_mode		= SENSOR_MIPI_OTHER_MODE,
++		.sensor_info.mipi_cfg.mipi_vcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_hcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3y	= 0,
++		.sensor_info.mipi_cfg.hcrop_diff_en		= 0,
++		.sensor_info.mipi_cfg.line_sync_mode	= 0,
++		.sensor_info.mipi_cfg.work_start_flag	= 0,
++		.sensor_info.mipi_cfg.data_type_en		= 0,
++		.sensor_info.mipi_cfg.data_type_value	= 0,
++		.sensor_info.mipi_cfg.del_start		= 0,
++		.sensor_info.mipi_cfg.sensor_frame_mode	= TX_SENSOR_WDR_2_FRAME_MODE,
++		.sensor_info.mipi_cfg.sensor_fid_mode	= 0,
++		.sensor_info.mipi_cfg.sensor_mode		= TX_SENSOR_VC_MODE,
++		.sensor_info.mipi_cfg.sensor_csi_fmt	= TX_SENSOR_RAW10,
++                .sensor_info
++		.width				= 1920,
++		.height				= 1080,
++		.fps				= 15 << 16 | 1,
++		.mbus_code	= MEDIA_BUS_FMT_SRGGB10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= gc2093_init_regs_1920_1080_15fps_mipi_wdr,
++	},
++#endif
++};
++
++static int gc2093_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_gc2093_FMTS)
++		return -EINVAL;
++
++	code->code = gc2093_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int gc2093_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct gc2093_format_struct *ovfmt;
++	struct gc2093_win_size *wsize;
++	struct gc2093_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int gc2093_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct gc2093_info *info = to_state(sd);
++	struct gc2093_win_size *wsize = info->win;
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = wsize->width;
++	fmt->height = wsize->height;
++	fmt->code = wsize->mbus_code;
++	fmt->colorspace = wsize->colorspace;
++	*(unsigned int *)fmt->reserved = &wsize->sensor_info;
++
++	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int gc2093_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2093_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2093_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2093_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int gc2093_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int gc2093_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(gc2093_again_lut); i++) {
++		lut = &gc2093_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->index;
++		}
++	}
++
++	/*last value.*/
++	return lut->index;
++}
++
++static int gc2093_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++    return 0;
++}
++
++/*set analog gain db value, map value to sensor register.*/
++static int gc2093_s_again(struct v4l2_subdev *sd, int again)
++{
++	struct gc2093_info *info = to_state(sd);
++	struct again_lut *val_lut = gc2093_again_lut;
++	unsigned int reg_value = 0;
++	int ret = 0;
++	if(again < info->again->minimum || again > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(again);
++	}
++
++	ret += gc2093_write(sd,0xb4,val_lut[reg_value].regb0);
++	ret += gc2093_write(sd,0xb3,val_lut[reg_value].regb1);
++	ret += gc2093_write(sd,0xb8,val_lut[reg_value].regb2);
++	ret += gc2093_write(sd,0xb9,val_lut[reg_value].regb3);
++	ret += gc2093_write(sd,0xce,val_lut[reg_value].regb4);
++	ret += gc2093_write(sd,0xc2,val_lut[reg_value].regb5);
++	ret += gc2093_write(sd,0xcf,val_lut[reg_value].regb6);
++	ret += gc2093_write(sd,0xd9,val_lut[reg_value].regb7);
++	return ret;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int gc2093_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2093_s_exp(struct v4l2_subdev *sd, int value)
++{
++	struct gc2093_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = gc2093_write(sd, 0x04, value & 0xff);
++	ret += gc2093_write(sd, 0x03, (value>>8)&0x3f);
++
++	return ret;
++}
++
++static int gc2093_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct gc2093_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return gc2093_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return gc2093_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int gc2093_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct gc2093_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return gc2093_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return gc2093_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return gc2093_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return gc2093_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* gc2093_s_gain turns off auto gain */
++			return gc2093_s_gain(sd, info->gain->val);
++		}
++		return gc2093_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return gc2093_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return gc2093_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return gc2093_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops gc2093_ctrl_ops = {
++	.s_ctrl = gc2093_s_ctrl,
++	.g_volatile_ctrl = gc2093_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int gc2093_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = gc2093_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int gc2093_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	gc2093_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int gc2093_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct gc2093_info *info = to_state(sd);
++	int ret = 0;
++	printk("%s:~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n",__func__);
++	if (enable) {
++		ret = gc2093_write_array(sd, gc2093_stream_on_mipi);
++		printk("gc2093 stream on\n");
++
++	}
++	else {
++		ret = gc2093_write_array(sd, gc2093_stream_off_mipi);
++		printk("gc2093 stream off\n");
++	}
++	return ret;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops gc2093_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = gc2093_g_register,
++	.s_register = gc2093_s_register,
++#endif
++};
++
++static const struct v4l2_subdev_video_ops gc2093_video_ops = {
++	.s_stream = gc2093_s_stream,
++};
++
++static const struct v4l2_subdev_pad_ops gc2093_pad_ops = {
++	//.enum_frame_interval = gc2093_enum_frame_interval,
++	//.num_frame_size = gc2093_enum_frame_size,
++	//.enum_mbus_code = gc2093_enum_mbus_code,
++	.set_fmt = gc2093_set_fmt,
++	.get_fmt = gc2093_get_fmt,
++};
++
++static const struct v4l2_subdev_ops gc2093_ops = {
++	.core = &gc2093_core_ops,
++	.video = &gc2093_video_ops,
++	.pad = &gc2093_pad_ops,
++};
++
++void gc2093_power_init_seq(struct gc2093_info *info)
++{
++	*(volatile unsigned int*)0xb0010100 = 0x1;
++	gpio_direction_output(4,0);
++	udelay(50);
++	gpio_direction_output(info->pwen.pin,info->pwen.active_level);
++	udelay(50);
++
++	gpio_direction_output(info->reset.pin,!info->reset.active_level);
++	msleep(10);
++	gpio_direction_output(info->reset.pin,info->reset.active_level);
++	msleep(20);
++	gpio_direction_output(info->reset.pin,!info->reset.active_level);
++	msleep(50);
++
++	gpio_direction_output(info->pwdn.pin,info->pwdn.active_level);
++	msleep(10);
++	gpio_direction_output(info->pwdn.pin,!info->pwdn.active_level);
++	msleep(10);
++	gpio_direction_output(info->pwdn.pin,info->pwdn.active_level);
++	msleep(10);
++}
++/* ----------------------------------------------------------------------- */
++
++static int gc2093_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	printk("~~~%s:%d~~~=====================================\n", __func__, __LINE__);
++	struct v4l2_fract tpf;
++	struct v4l2_subdev *sd;
++	struct gc2093_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++	unsigned long rate;
++	unsigned char value;
++	printk("~~~%s:%d~~~\n", __func__, __LINE__);
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,pwen-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->pwen.pin = gpio;
++		info->pwen.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,pwdn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->pwdn.pin = gpio;
++		info->pwdn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	printk("gpio set ok ~~~%s:%d~~~\n", __func__, __LINE__);
++
++	gc2093_power_init_seq(info);
++	v4l2_i2c_subdev_init(sd, client, &gc2093_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++#if 1
++	info->clk = v4l2_clk_get(&client->dev, "div_cim0");
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++
++	ret = v4l2_clk_set_rate(info->clk, 27000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++#endif
++
++#if 1
++	/* Make sure it's an gc2093 */
++	ret = gc2093_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an gc2093 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++#if 1
++	/*IRCUT ctl 0:off 1:on*/
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 367506, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1350 - 4, 1, 1000);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->win = &gc2093_win_sizes[0];
++
++	gc2093_init(sd, 1);
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	/* test image   */
++//	gc2093_write(sd,0x018c,0x01);
++	dev_info(&client->dev, "gc2093 Probed\n");
++	return 0;
++#endif
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int gc2093_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct gc2093_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id gc2093_id[] = {
++	{ "gc2093b", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, gc2093_id);
++
++static const struct of_device_id gc2093_of_match[] = {
++	{.compatible = "gc2093b", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, gc2093_of_match);
++
++
++static struct i2c_driver gc2093_driver = {
++	.driver = {
++		.name	= "gc2093b",
++		.of_match_table = of_match_ptr(gc2093_of_match),
++	},
++	.probe		= gc2093_probe,
++	.remove		= gc2093_remove,
++	.id_table	= gc2093_id,
++};
++
++module_i2c_driver(gc2093_driver);
++MODULE_DESCRIPTION("A low-level driver for gc2093 sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp-v2/gc2155.c b/module_drivers/drivers/media/i2c/ingenic-isp-v2/gc2155.c
+new file mode 100644
+index 000000000..ef7f2c8ad
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp-v2/gc2155.c
+@@ -0,0 +1,1516 @@
++/*
++ * A V4L2 driver for OmniVision GC2155 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++#include <linux/clk.h>
++
++#include <isp-sensor.h>
++
++#define GC2155_CHIP_ID_H	(0x21)
++#define GC2155_CHIP_ID_L	(0x55)
++#define GC2155_REG_END		0xff
++#define GC2155_REG_DELAY	0x00
++
++#define AGAIN_MAX_DB 0x64
++#define DGAIN_MAX_DB 0x64
++#define LOG2_GAIN_SHIFT 16
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++
++struct gc2155_win_size {
++	unsigned int width;
++	unsigned int height;
++	struct sensor_info sensor_info;
++	unsigned int mbus_code;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++};
++
++struct gc2155_gpio {
++	int pin;
++	int active_level;
++};
++
++struct gc2155_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++	struct v4l2_ctrl *again_short;
++
++	struct v4l2_clk *clk;
++	struct clk *sclka;
++
++	struct v4l2_ctrl *exposure;
++	struct v4l2_ctrl *exposure_short;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct gc2155_win_size *win;
++
++	struct gc2155_gpio pwdn;
++	struct gc2155_gpio reset;
++};
++
++
++static inline struct gc2155_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct gc2155_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct gc2155_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++
++static struct regval_list gc2155_init_regs[] = {
++	{0xfe,0xf0},
++	{0xfe,0xf0},
++	{0xfe,0xf0},
++	{0xfc,0x06},
++	{0xf6,0x00},
++	{0xf7,0x1d},
++	{0xf8,0x84},
++	{0xfa,0x00},
++	{0xf9,0xfe},
++	{0xf2,0x00},
++	{0xfe,0x00},
++	{0x03,0x04},
++	{0x04,0xe2},
++	{0x09,0x00},
++	{0x0a,0x00},
++	{0x0b,0x00},
++	{0x0c,0x00},
++	{0x0d,0x04},
++	{0x0e,0xc0},
++	{0x0f,0x06},
++	{0x10,0x50},
++	{0x12,0x2e},
++	{0x17,0x14}, // mirror
++	{0x18,0x02},
++	{0x19,0x0e},
++	{0x1a,0x01},
++	{0x1b,0x4b},
++	{0x1c,0x07},
++	{0x1d,0x10},
++	{0x1e,0x98},
++	{0x1f,0x78},
++	{0x20,0x05},
++	{0x21,0x40},
++	{0x22,0xf0},
++	{0x24,0x16},
++	{0x25,0x01},
++	{0x26,0x10},
++	{0x2d,0x40},
++	{0x30,0x01},
++	{0x31,0x90},
++	{0x33,0x04},
++	{0x34,0x01},
++	{0xfe,0x00},
++	{0x80,0xff},
++	{0x81,0x2c},
++	{0x82,0xfa},
++	{0x83,0x00},
++	{0x84,0x02}, //y u yv
++	{0x85,0x08},
++	{0x86,0x02},
++	{0x89,0x03},
++	{0x8a,0x00},
++	{0x8b,0x00},
++	{0xb0,0x55},
++	{0xc3,0x11}, //00
++	{0xc4,0x20},
++	{0xc5,0x30},
++	{0xc6,0x38},
++	{0xc7,0x40},
++	{0xec,0x02},
++	{0xed,0x04},
++	{0xee,0x60},
++	{0xef,0x90},
++	{0xb6,0x01},
++	{0x90,0x01},
++	{0x91,0x00},
++	{0x92,0x00},
++	{0x93,0x00},
++	{0x94,0x00},
++	{0x95,0x04},
++	{0x96,0xb0},
++	{0x97,0x06},
++	{0x98,0x40},
++	{0xfe,0x00},
++	{0x18,0x02},
++	{0x40,0x42},
++	{0x41,0x00},
++	{0x43,0x5b},//0X54
++	{0x5e,0x00},
++	{0x5f,0x00},
++	{0x60,0x00},
++	{0x61,0x00},
++	{0x62,0x00},
++	{0x63,0x00},
++	{0x64,0x00},
++	{0x65,0x00},
++	{0x66,0x20},
++	{0x67,0x20},
++	{0x68,0x20},
++	{0x69,0x20},
++	{0x6a,0x08},
++	{0x6b,0x08},
++	{0x6c,0x08},
++	{0x6d,0x08},
++	{0x6e,0x08},
++	{0x6f,0x08},
++	{0x70,0x08},
++	{0x71,0x08},
++	{0x72,0xf0},
++	{0x7e,0x3c},
++	{0x7f,0x00},
++	{0xfe,0x00},
++	{0xfe,0x01},
++	{0x01,0x08},
++	{0x02,0xc0},
++	{0x03,0x04},
++	{0x04,0x90},
++	{0x05,0x30},
++	{0x06,0x98},
++	{0x07,0x28},
++	{0x08,0x6c},
++	{0x09,0x00},
++	{0x0a,0xc2},
++	{0x0b,0x11},
++	{0x0c,0x10},
++	{0x13,0x2d},
++	{0x17,0x00},
++	{0x1c,0x11},
++	{0x1e,0x61},
++	{0x1f,0x30},
++	{0x20,0x40},
++	{0x22,0x80},
++	{0x23,0x20},
++	{0x12,0x35},
++	{0x15,0x50},
++	{0x10,0x31},
++	{0x3e,0x28},
++	{0x3f,0xe0},
++	{0x40,0xe0},
++	{0x41,0x08},
++	{0xfe,0x02},
++	{0x0f,0x05},
++	{0xfe,0x02},
++	{0x90,0x6c},
++	{0x91,0x03},
++	{0x92,0xc4},
++	{0x97,0x64},
++	{0x98,0x88},
++	{0x9d,0x08},
++	{0xa2,0x11},
++	{0xfe,0x00},
++	{0xfe,0x02},
++	{0x80,0xc1},
++	{0x81,0x08},
++	{0x82,0x05},
++	{0x83,0x04},
++	{0x86,0x80},
++	{0x87,0x30},
++	{0x88,0x15},
++	{0x89,0x80},
++	{0x8a,0x60},
++	{0x8b,0x30},
++	{0xfe,0x01},
++	{0x21,0x14},
++	{0xfe,0x02},
++	{0x3c,0x06},
++	{0x3d,0x40},
++	{0x48,0x30},
++	{0x49,0x06},
++	{0x4b,0x08},
++	{0x4c,0x20},
++	{0xa3,0x50},
++	{0xa4,0x30},
++	{0xa5,0x40},
++	{0xa6,0x80},
++	{0xab,0x40},
++	{0xae,0x0c},
++	{0xb3,0x42},
++	{0xb4,0x24},
++	{0xb6,0x50},
++	{0xb7,0x01},
++	{0xb9,0x28},
++	{0xfe,0x00},
++	{0xfe,0x02},
++	{0x10,0x0d},
++	{0x11,0x12},
++	{0x12,0x17},
++	{0x13,0x1c},
++	{0x14,0x27},
++	{0x15,0x34},
++	{0x16,0x44},
++	{0x17,0x55},
++	{0x18,0x6e},
++	{0x19,0x81},
++	{0x1a,0x91},
++	{0x1b,0x9c},
++	{0x1c,0xaa},
++	{0x1d,0xbb},
++	{0x1e,0xca},
++	{0x1f,0xd5},
++	{0x20,0xe0},
++	{0x21,0xe7},
++	{0x22,0xed},
++	{0x23,0xf6},
++	{0x24,0xfb},
++	{0x25,0xff},
++	{0xfe,0x02},
++	{0x26,0x0d},
++	{0x27,0x12},
++	{0x28,0x17},
++	{0x29,0x1c},
++	{0x2a,0x27},
++	{0x2b,0x34},
++	{0x2c,0x44},
++	{0x2d,0x55},
++	{0x2e,0x6e},
++	{0x2f,0x81},
++	{0x30,0x91},
++	{0x31,0x9c},
++	{0x32,0xaa},
++	{0x33,0xbb},
++	{0x34,0xca},
++	{0x35,0xd5},
++	{0x36,0xe0},
++	{0x37,0xe7},
++	{0x38,0xed},
++	{0x39,0xf6},
++	{0x3a,0xfb},
++	{0x3b,0xff},
++	{0xfe,0x02},
++	{0xd1,0x28},
++	{0xd2,0x28},
++	{0xdd,0x14},
++	{0xde,0x88},
++	{0xed,0x80},
++	{0xfe,0x01},
++	{0xc2,0x1f},
++	{0xc3,0x13},
++	{0xc4,0x0e},
++	{0xc8,0x16},
++	{0xc9,0x0f},
++	{0xca,0x0c},
++	{0xbc,0x52},
++	{0xbd,0x2c},
++	{0xbe,0x27},
++	{0xb6,0x47},
++	{0xb7,0x32},
++	{0xb8,0x30},
++	{0xc5,0x00},
++	{0xc6,0x00},
++	{0xc7,0x00},
++	{0xcb,0x00},
++	{0xcc,0x00},
++	{0xcd,0x00},
++	{0xbf,0x0e},
++	{0xc0,0x00},
++	{0xc1,0x00},
++	{0xb9,0x08},
++	{0xba,0x00},
++	{0xbb,0x00},
++	{0xaa,0x0a},
++	{0xab,0x0c},
++	{0xac,0x0d},
++	{0xad,0x02},
++	{0xae,0x06},
++	{0xaf,0x05},
++	{0xb0,0x00},
++	{0xb1,0x05},
++	{0xb2,0x02},
++	{0xb3,0x04},
++	{0xb4,0x04},
++	{0xb5,0x05},
++	{0xd0,0x00},
++	{0xd1,0x00},
++	{0xd2,0x00},
++	{0xd6,0x02},
++	{0xd7,0x00},
++	{0xd8,0x00},
++	{0xd9,0x00},
++	{0xda,0x00},
++	{0xdb,0x00},
++	{0xd3,0x00},
++	{0xd4,0x00},
++	{0xd5,0x00},
++	{0xa4,0x04},
++	{0xa5,0x00},
++	{0xa6,0x77},
++	{0xa7,0x77},
++	{0xa8,0x77},
++	{0xa9,0x77},
++	{0xa1,0x80},
++	{0xa2,0x80},
++	{0xfe,0x01},
++	{0xdc,0x35},
++	{0xdd,0x28},
++	{0xdf,0x0d},
++	{0xe0,0x70},
++	{0xe1,0x78},
++	{0xe2,0x70},
++	{0xe3,0x78},
++	{0xe6,0x90},
++	{0xe7,0x70},
++	{0xe8,0x90},
++	{0xe9,0x70},
++	{0xfe,0x00},
++	{0xfe,0x01},
++	{0x4f,0x00},
++	{0x4f,0x00},
++	{0x4b,0x01},
++	{0x4f,0x00},
++	{0x4c,0x01},
++	{0x4d,0x71},
++	{0x4e,0x02},
++	{0x4c,0x01},
++	{0x4d,0x91},
++	{0x4e,0x02},
++	{0x4c,0x01},
++	{0x4d,0x50},
++	{0x4e,0x02},
++	{0x4c,0x01},
++	{0x4d,0x70},
++	{0x4e,0x02},
++	{0x4c,0x01},
++	{0x4d,0x90},
++	{0x4e,0x02},
++	{0x4c,0x01},
++	{0x4d,0xb0},
++	{0x4e,0x02},
++	{0x4c,0x01},
++	{0x4d,0xd0},
++	{0x4e,0x02},
++	{0x4c,0x01},
++	{0x4d,0x4f},
++	{0x4e,0x02},
++	{0x4c,0x01},
++	{0x4d,0x6f},
++	{0x4e,0x02},
++	{0x4c,0x01},
++	{0x4d,0x8f},
++	{0x4e,0x02},
++	{0x4c,0x01},
++	{0x4d,0xaf},
++	{0x4e,0x02},
++	{0x4c,0x01},
++	{0x4d,0xcf},
++	{0x4e,0x02},
++	{0x4c,0x01},
++	{0x4d,0x6e},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0x8e},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0xae},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0xce},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0x4d},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0x6d},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0x8d},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0xad},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0xcd},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0x4c},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0x6c},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0x8c},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0xac},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0xcc},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0xec},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0x4b},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0x6b},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0x8b},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0xab},
++	{0x4e,0x03},
++	{0x4c,0x01},
++	{0x4d,0x8a},
++	{0x4e,0x04},
++	{0x4c,0x01},
++	{0x4d,0xaa},
++	{0x4e,0x04},
++	{0x4c,0x01},
++	{0x4d,0xca},
++	{0x4e,0x04},
++	{0x4c,0x01},
++	{0x4d,0xa9},
++	{0x4e,0x04},
++	{0x4c,0x01},
++	{0x4d,0xc9},
++	{0x4e,0x04},
++	{0x4c,0x01},
++	{0x4d,0xcb},
++	{0x4e,0x05},
++	{0x4c,0x01},
++	{0x4d,0xeb},
++	{0x4e,0x05},
++	{0x4c,0x02},
++	{0x4d,0x0b},
++	{0x4e,0x05},
++	{0x4c,0x02},
++	{0x4d,0x2b},
++	{0x4e,0x05},
++	{0x4c,0x02},
++	{0x4d,0x4b},
++	{0x4e,0x05},
++	{0x4c,0x01},
++	{0x4d,0xea},
++	{0x4e,0x05},
++	{0x4c,0x02},
++	{0x4d,0x0a},
++	{0x4e,0x05},
++	{0x4c,0x02},
++	{0x4d,0x2a},
++	{0x4e,0x05},
++	{0x4c,0x02},
++	{0x4d,0x6a},
++	{0x4e,0x06},
++	{0x4c,0x02},
++	{0x4d,0x29},
++	{0x4e,0x06},
++	{0x4c,0x02},
++	{0x4d,0x49},
++	{0x4e,0x06},
++	{0x4c,0x02},
++	{0x4d,0x69},
++	{0x4e,0x06},
++	{0x4c,0x02},
++	{0x4d,0x89},
++	{0x4e,0x06},
++	{0x4c,0x02},
++	{0x4d,0xa9},
++	{0x4e,0x06},
++	{0x4c,0x02},
++	{0x4d,0xc9},
++	{0x4e,0x06},
++	{0x4c,0x02},
++	{0x4d,0x48},
++	{0x4e,0x06},
++	{0x4c,0x02},
++	{0x4d,0x68},
++	{0x4e,0x06},
++	{0x4c,0x03},
++	{0x4d,0x09},
++	{0x4e,0x07},
++	{0x4c,0x02},
++	{0x4d,0xa8},
++	{0x4e,0x07},
++	{0x4c,0x02},
++	{0x4d,0xc8},
++	{0x4e,0x07},
++	{0x4c,0x02},
++	{0x4d,0xe8},
++	{0x4e,0x07},
++	{0x4c,0x03},
++	{0x4d,0x08},
++	{0x4e,0x07},
++	{0x4c,0x03},
++	{0x4d,0x28},
++	{0x4e,0x07},
++	{0x4c,0x02},
++	{0x4d,0x87},
++	{0x4e,0x07},
++	{0x4c,0x02},
++	{0x4d,0xa7},
++	{0x4e,0x07},
++	{0x4c,0x02},
++	{0x4d,0xc7},
++	{0x4e,0x07},
++	{0x4c,0x02},
++	{0x4d,0xe7},
++	{0x4e,0x07},
++	{0x4c,0x03},
++	{0x4d,0x07},
++	{0x4e,0x07},
++	{0x4f,0x01},
++	{0xfe,0x01},
++	{0x50,0x80},
++	{0x51,0xa8},
++	{0x52,0x57},
++	{0x53,0x38},
++	{0x54,0xc7},
++	{0x56,0x0e},
++	{0x58,0x08},
++	{0x5b,0x00},
++	{0x5c,0x74},
++	{0x5d,0x8b},
++	{0x61,0xd3},
++	{0x62,0x90},
++	{0x63,0xaa},
++	{0x65,0x04},
++	{0x67,0xb2},
++	{0x68,0xac},
++	{0x69,0x00},
++	{0x6a,0xb2},
++	{0x6b,0xac},
++	{0x6c,0xdc},
++	{0x6d,0xb0},
++	{0x6e,0x30},
++	{0x6f,0x40},
++	{0x70,0x05},
++	{0x71,0x80},
++	{0x72,0x80},
++	{0x73,0x30},
++	{0x74,0x01},
++	{0x75,0x01},
++	{0x7f,0x08},
++	{0x76,0x70},
++	{0x77,0x48},
++	{0x78,0xa0},
++	{0xfe,0x00},
++	{0xfe,0x02},
++	{0xc0,0x01},
++	{0xc1,0x4a},
++	{0xc2,0xf3},
++	{0xc3,0xfc},
++	{0xc4,0xe4},
++	{0xc5,0x48},
++	{0xc6,0xec},
++	{0xc7,0x45},
++	{0xc8,0xf8},
++	{0xc9,0x02},
++	{0xca,0xfe},
++	{0xcb,0x42},
++	{0xcc,0x00},
++	{0xcd,0x45},
++	{0xce,0xf0},
++	{0xcf,0x00},
++	{0xe3,0xf0},
++	{0xe4,0x45},
++	{0xe5,0xe8},
++	{0xfe,0x01},
++	{0x9f,0x42},
++	{0xfe,0x00},
++	{0xfe,0x00},
++	{0xf2,0x0f},
++	{0xfe,0x00},
++	{0x05,0x01},
++	{0x06,0x56},
++	{0x07,0x00},
++	{0x08,0x32},
++	{0xfe,0x01},
++	{0x25,0x00},
++	{0x26,0xfa},
++	{0x27,0x04},
++	{0x28,0xe2}, //20fps
++	{0x29,0x06},
++	{0x2a,0xd6}, //16fps
++	{0x2b,0x07},
++	{0x2c,0xd0}, //12fps
++	{0x2d,0x0b},
++	{0x2e,0xb8}, //8fps
++	{0xfe,0x00},
++	{0xfe,0x00},
++	{0xfa,0x00},
++	{0xfd,0x01},
++	{0xfe,0x00},
++	{0x90,0x01},
++	{0x91,0x00},
++	{0x92,0x00},
++	{0x93,0x00},
++	{0x95,0x04},// win_size 320 * 240
++	{0x96,0xb0},
++	{0x97,0x06},
++	{0x98,0x40},
++
++
++	{0x99,0x11},
++	{0x9a,0x06},
++	{0xfe,0x01},
++	{0xec,0x01},
++	{0xed,0x02},
++	{0xee,0x30},
++	{0xef,0x48},
++	{0xfe,0x01},
++	{0x74,0x00},
++	{0xfe,0x01},
++	{0x01,0x04},
++	{0x02,0x60},
++	{0x03,0x02},
++	{0x04,0x48},
++	{0x05,0x18},
++	{0x06,0x4c},
++	{0x07,0x14},
++	{0x08,0x36},
++	{0x0a,0xc0},
++	{0x21,0x14},
++	{0xfe,0x00},
++	{0xfe,0x00},
++	{0xc3,0x11},
++	{0xc4,0x20},
++	{0xc5,0x30},
++	{0xfa,0x11},//pclk rate
++	{0x86,0x02},//pclk polar
++	{0xfe,0x00},
++
++#if 1
++	// 720P init
++	 {0xfe,0x00},
++	 {0xb6,0x01},
++	 {0xfd,0x00},
++
++  //subsample
++	 {0xfe,0x00},
++	 {0x99,0x55},
++	 {0x9a,0x06},
++	 {0x9b,0x00},
++	 {0x9c,0x00},
++	 {0x9d,0x01},
++	 {0x9e,0x23},
++	 {0x9f,0x00},
++	 {0xa0,0x00},
++	 {0xa1,0x01},
++	 {0xa2,0x23},
++	 //crop window
++	 {0x90,0x01},
++	 {0x91,0x00},
++	 {0x92,0x78},
++	 {0x93,0x00},
++	 {0x94,0x00},
++	 {0x95,0x02},
++	 {0x96,0xd0},
++	 {0x97,0x05},
++	 {0x98,0x00},
++	 // AWB
++	 {0xfe,0x00},
++	 {0xec,0x02},
++	 {0xed,0x04},
++	 {0xee,0x60},
++	 {0xef,0x90},
++	 {0xfe,0x01},
++	 {0x74,0x01},
++	 // AEC
++	 {0xfe,0x01},
++	 {0x01,0x08},
++	 {0x02,0xc0},
++	 {0x03,0x04},
++	 {0x04,0x90},
++	 {0x05,0x30},
++	 {0x06,0x98},
++	 {0x07,0x28},
++	 {0x08,0x6c},
++	 {0x0a,0xc2},
++	 {0x21,0x15},
++	 {0xfe,0x00},
++#if 0
++	 //banding setting 20fps fixed///
++	 {0xfe,0x00},
++	 {0x03,0x03},
++	 {0x04,0xe8},
++	 {0x05,0x01},
++	 {0x06,0x56},
++	 {0x07,0x00},
++	 {0x08,0x32},
++	 {0xfe,0x01},
++	 {0x25,0x00},
++	 {0x26,0xfa},
++	 {0x27,0x04},
++	 {0x28,0xe2}, //20fps
++	 {0x29,0x04},
++	 {0x2a,0xe2}, //16fps   5dc
++	 {0x2b,0x04},
++	 {0x2c,0xe2}, //16fps  6d6  5dc
++	 {0x2d,0x04},
++	 {0x2e,0xe2}, //8fps	bb8
++	 {0x3c,0x00}, //8fps
++	 {0xfe,0x00},
++#endif
++#endif
++#if 0
++	 /*qvga*/
++	 {0xfe,0x00},
++	 {0xfd,0x01},
++	 // crop window
++	 {0xfe,0x00},
++	 {0x90,0x01},
++	 {0x91,0x00},
++	 {0x92,0xb4},
++	 {0x93,0x00},
++	 {0x94,0xf0},
++	 {0x95,0x00},
++	 {0x96,0xf0},
++	 {0x97,0x01},
++	 {0x98,0x40},
++	 // AWB
++	 {0xfe,0x00},
++	 {0xec,0x01},
++	 {0xed,0x02},
++	 {0xee,0x30},
++	 {0xef,0x48},
++	 {0xfe,0x01},
++	 {0x74,0x00},
++	 //// AEC
++	 {0xfe,0x01},
++	 {0x01,0x04},
++	 {0x02,0x60},
++	 {0x03,0x02},
++	 {0x04,0x48},
++	 {0x05,0x18},
++	 {0x06,0x4c},
++	 {0x07,0x14},
++	 {0x08,0x36},
++	 {0x0a,0xc0},
++	 {0x21,0x14},
++#if 0
++	 {0x25,0x01},
++	 {0x26,0x90},
++	 {0x27,0x03},
++	 {0x28,0x20}, //50fps
++	 {0x29,0x03},
++	 {0x2a,0x20},
++	 {0x2b,0x03},
++	 {0x2c,0x20},
++	 {0x2d,0x03},
++	 {0x2e,0x20},
++#endif
++	 {0xfe,0x00},
++	 //// gamma
++	 {0xfe,0x00},
++	 {0xc3,0x11},
++	 {0xc4,0x20},
++	 {0xc5,0x30},
++	 {0xfe,0x00},
++#endif
++
++
++	{0xfe, 0x00},
++	{0x8d, 0x08},
++
++
++	 {GC2155_REG_END, 0x00},	/* END MARKER */
++
++};
++
++
++
++/*
++ * the part of driver was fixed.
++ */
++
++static struct regval_list gc2155_stream_on_mipi[] = {
++	/*
++	{0x3000, 0x00},
++	*/
++	{GC2155_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list gc2155_stream_off_mipi[] = {
++	/*
++	{0x3000, 0x01},
++	*/
++	{GC2155_REG_END, 0x00},	/* END MARKER */
++};
++
++static int gc2155_read(struct v4l2_subdev *sd, unsigned char reg,
++		unsigned char *value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 1,
++			.buf	= &reg,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret = 0;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int gc2155_write(struct v4l2_subdev *sd, unsigned char reg,
++		unsigned char value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	unsigned char buf[2] = {reg, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 2,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int gc2155_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != GC2155_REG_END) {
++		if (vals->reg_num == GC2155_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = gc2155_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++/*
++ * Write a list of register settings; ff/ff stops the process.
++ */
++static int gc2155_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != GC2155_REG_END) {
++		if (vals->reg_num == GC2155_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = gc2155_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++static int gc2155_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++	ret = gc2155_read(sd, 0xf0, &v);
++//	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != GC2155_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = gc2155_read(sd, 0xf1, &v);
++//	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != GC2155_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	return 0;
++}
++
++static struct gc2155_win_size gc2155_win_sizes[] = {
++	{
++		.width				= 1280,
++		.height				= 720,
++		.sensor_info.fps				= 25 << 16 | 1,
++		.sensor_info.total_width			= 1280,
++		.sensor_info.total_height			= 720,
++		.sensor_info.wdr_en				= 0,
++		.mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= gc2155_init_regs,
++	},
++};
++
++#if 0
++static int gc2155_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad || code->index >= N_GC2155_FMTS)
++		return -EINVAL;
++
++	code->code = gc2155_formats[code->index].mbus_code;
++	return 0;
++}
++#endif
++
++/*
++ * Set a format.
++ */
++static int gc2155_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int gc2155_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct gc2155_info *info = to_state(sd);
++	struct gc2155_win_size *wsize = info->win;
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = wsize->width;
++	fmt->height = wsize->height;
++	fmt->code = wsize->mbus_code;
++	fmt->colorspace = wsize->colorspace;
++	*(unsigned int *)fmt->reserved = (unsigned int)&wsize->sensor_info;
++
++//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int gc2155_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2155_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2155_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2155_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int gc2155_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int gc2155_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	unsigned int again=(gain*20)>>LOG2_GAIN_SHIFT;
++	// Limit Max gain
++	if(again>AGAIN_MAX_DB+DGAIN_MAX_DB) again=AGAIN_MAX_DB+DGAIN_MAX_DB;
++	return again;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	return (((int32_t)regval)<<LOG2_GAIN_SHIFT)/20;
++}
++
++static int gc2155_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++#if 0
++	struct gc2155_info *info = to_state(sd);
++	unsigned char v = 0;
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++
++	ret += gc2155_read(sd, 0x3014, &v);
++	reg_val = v;
++
++	*value = regval_to_again(reg_val);
++	return ret;
++#endif
++	return 0;
++}
++
++/*set analog gain db value, map value to sensor register.*/
++static int gc2155_s_again(struct v4l2_subdev *sd, int again)
++{
++#if 0
++	struct gc2155_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int ret = 0;
++
++//	printk("again = %d\n", again);
++	reg_value = again_to_regval(again);
++	ret += gc2155_write(sd, 0x3014, (unsigned char)(reg_value & 0xff));
++	return ret;
++#endif
++	return 0;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int gc2155_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2155_s_exp(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++#if 0
++	struct gc2155_info *info = to_state(sd);
++	int shs = 0;
++	unsigned char val = 0;
++	int total_height = 0;
++
++//	printk("exp = %d\n", value);
++	ret = gc2155_read(sd, 0x3019, &val);
++	total_height |= val << 8;
++	ret = gc2155_read(sd, 0x3018, &val);
++	total_height |= val;
++
++	if(info->win->sensor_info.wdr_en) {
++		total_height *= 2;
++		shs = total_height - value - 1;
++		ret = gc2155_write(sd, 0x3024, (unsigned char)(shs & 0xff));
++		ret += gc2155_write(sd, 0x3025, (unsigned char)((shs >> 8) & 0xff));
++		ret += gc2155_write(sd, 0x3026, (unsigned char)((shs >> 16) & 0x3));
++	} else {
++		shs = total_height - value - 1;
++		ret = gc2155_write(sd, 0x3020, (unsigned char)(shs & 0xff));
++		ret += gc2155_write(sd, 0x3021, (unsigned char)((shs >> 8) & 0xff));
++		ret += gc2155_write(sd, 0x3022, (unsigned char)((shs >> 16) & 0x3));
++	}
++#endif
++	return ret;
++}
++
++static int gc2155_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct gc2155_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return gc2155_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return gc2155_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int gc2155_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct gc2155_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++		case V4L2_CID_BRIGHTNESS:
++			return gc2155_s_brightness(sd, ctrl->val);
++		case V4L2_CID_CONTRAST:
++			return gc2155_s_contrast(sd, ctrl->val);
++		case V4L2_CID_VFLIP:
++			return gc2155_s_vflip(sd, ctrl->val);
++		case V4L2_CID_HFLIP:
++			return gc2155_s_hflip(sd, ctrl->val);
++		case V4L2_CID_AUTOGAIN:
++			/* Only set manual gain if auto gain is not explicitly
++			   turned on. */
++			if (!ctrl->val) {
++				/* gc2155_s_gain turns off auto gain */
++				return gc2155_s_gain(sd, info->gain->val);
++			}
++			return gc2155_s_autogain(sd, ctrl->val);
++		case V4L2_CID_GAIN:
++			return gc2155_s_gain(sd, ctrl->val);
++		case V4L2_CID_ANALOGUE_GAIN:
++			return gc2155_s_again(sd, ctrl->val);
++		case V4L2_CID_EXPOSURE:
++			return gc2155_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops gc2155_ctrl_ops = {
++	.s_ctrl = gc2155_s_ctrl,
++	.g_volatile_ctrl = gc2155_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int gc2155_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = gc2155_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int gc2155_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	gc2155_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++static int gc2155_core_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct gc2155_info *info = to_state(sd);
++	int ret = 0;
++	ret = gc2155_write_array(sd, info->win->regs);
++	return ret;
++}
++
++static int gc2155_power(struct v4l2_subdev *sd, u32 val)
++{
++	struct gc2155_info *info = to_state(sd);
++	if(val) {
++		gpio_direction_output(info->pwdn.pin, info->reset.active_level);
++		msleep(10);
++	}
++	else{
++		gpio_direction_output(info->pwdn.pin, !info->reset.active_level);
++		msleep(10);
++	}
++	return 0;
++}
++
++static int gc2155_core_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct gc2155_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(10);
++	}
++	return 0;
++}
++
++
++int gc2155_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	int ret = 0;
++
++	if (enable) {
++		gc2155_core_reset(sd, 1);
++		gc2155_core_init(sd, 1);
++		ret = gc2155_write_array(sd, gc2155_stream_on_mipi);
++		pr_debug("gc2155 stream on\n");
++
++	}
++	else {
++		ret = gc2155_write_array(sd, gc2155_stream_off_mipi);
++		pr_debug("gc2155 stream off\n");
++	}
++	return ret;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops gc2155_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = gc2155_g_register,
++	.s_register = gc2155_s_register,
++#endif
++	.init = gc2155_core_init,
++	.reset = gc2155_core_reset,
++
++};
++
++static const struct v4l2_subdev_video_ops gc2155_video_ops = {
++	.s_stream = gc2155_s_stream,
++};
++
++static const struct v4l2_subdev_pad_ops gc2155_pad_ops = {
++	//.enum_frame_interval = gc2155_enum_frame_interval,
++	//.num_frame_size = gc2155_enum_frame_size,
++	//.enum_mbus_code = gc2155_enum_mbus_code,
++	.set_fmt = gc2155_set_fmt,
++	.get_fmt = gc2155_get_fmt,
++};
++
++static const struct v4l2_subdev_ops gc2155_ops = {
++	.core = &gc2155_core_ops,
++	.video = &gc2155_video_ops,
++	.pad = &gc2155_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int gc2155_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_subdev *sd;
++	struct gc2155_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++	unsigned long rate;
++	int mclk_index = -1;
++	char id_div[9];
++	char id_mux[9];
++
++	*(volatile unsigned int *)(0xb0010100) = 1;
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,pwdn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->pwdn.pin = gpio;
++		info->pwdn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	v4l2_i2c_subdev_init(sd, client, &gc2155_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++#if 1
++
++	of_property_read_u32(client->dev.of_node, "ingenic,mclk", &mclk_index);
++	if(mclk_index == 0) {
++		memcpy(id_div, "div_cim0", sizeof(id_div));
++		memcpy(id_mux, "mux_cim0", sizeof(id_mux));
++	} else if(mclk_index == 1) {
++		memcpy(id_div, "div_cim1", sizeof(id_div));
++		memcpy(id_mux, "mux_cim1", sizeof(id_mux));
++	} else if(mclk_index == 2) {
++		memcpy(id_div, "div_cim2", sizeof(id_div));
++		memcpy(id_mux, "mux_cim2", sizeof(id_mux));
++	} else
++		printk("Unkonwn mclk index\n");
++
++
++	info->clk = v4l2_clk_get(&client->dev, id_div);
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++	info->sclka = devm_clk_get(&client->dev, id_mux);
++
++	rate = v4l2_clk_get_rate(info->clk);
++	if (((rate / 1000) % 24000) != 0) {
++		ret = clk_set_parent(info->sclka, clk_get(NULL, "epll"));
++		info->sclka = devm_clk_get(&client->dev, "epll");
++		if (IS_ERR(info->sclka)) {
++			pr_err("get sclka failed\n");
++		} else {
++			rate = clk_get_rate(info->sclka);
++			if (((rate / 1000) % 24000) != 0) {
++				clk_set_rate(info->sclka, 120000000);
++			}
++		}
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++#endif
++
++
++	gc2155_power(sd, 1);
++	gc2155_core_reset(sd, 1);
++#if 1
++	/* Make sure it's an gc2155 */
++	ret = gc2155_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an gc2155 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++
++	info->win = &gc2155_win_sizes[0];
++
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 10);
++	v4l2_ctrl_new_std(&info->hdl, &gc2155_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &gc2155_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &gc2155_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &gc2155_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &gc2155_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &gc2155_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 589824, 1, 10000);
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &gc2155_ctrl_ops,
++			V4L2_CID_EXPOSURE, 1, 1176, 1, 1000);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "gc2155 Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int gc2155_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct gc2155_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id gc2155_id[] = {
++	{ "gc2155", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, gc2155_id);
++
++static const struct of_device_id gc2155_of_match[] = {
++	{.compatible = "GalaxyCore,gc2155", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, gc2155_of_match);
++
++
++static struct i2c_driver gc2155_driver = {
++	.driver = {
++		.name	= "gc2155",
++		.of_match_table = of_match_ptr(gc2155_of_match),
++	},
++	.probe		= gc2155_probe,
++	.remove		= gc2155_remove,
++	.id_table	= gc2155_id,
++};
++
++module_i2c_driver(gc2155_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for OmniVision gc2155 sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp-v2/imx327.c b/module_drivers/drivers/media/i2c/ingenic-isp-v2/imx327.c
+new file mode 100644
+index 000000000..5772832ba
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp-v2/imx327.c
+@@ -0,0 +1,1109 @@
++/*
++ * A V4L2 driver for OmniVision IMX327 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++#include <linux/clk.h>
++
++#include <isp-sensor.h>
++
++#define IMX327_CHIP_ID_H	(0xb2)
++#define IMX327_CHIP_ID_L	(0x01)
++#define IMX327_REG_END		0xffff
++#define IMX327_REG_DELAY	0xfffe
++
++#define AGAIN_MAX_DB 0x64
++#define DGAIN_MAX_DB 0x64
++#define LOG2_GAIN_SHIFT 16
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++
++struct imx327_win_size {
++	unsigned int width;
++	unsigned int height;
++	struct sensor_info sensor_info;
++	unsigned int mbus_code;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++};
++
++struct imx327_gpio {
++	int pin;
++	int active_level;
++};
++
++struct imx327_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++	struct v4l2_ctrl *again_short;
++
++	struct v4l2_clk *clk;
++	struct clk *sclka;
++
++	struct v4l2_ctrl *exposure;
++	struct v4l2_ctrl *exposure_short;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct imx327_win_size *win;
++
++	struct imx327_gpio reset;
++	struct imx327_gpio ircutp;
++	struct imx327_gpio ircutn;
++};
++
++
++static inline struct imx327_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct imx327_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct imx327_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++
++static struct regval_list imx327_init_regs_1920_1080_30fps_mipi[] = {
++	{0x3000, 0x01},//standy
++	{0x3001, 0x01},
++	{0x3002, 0x01},//Master stop
++//	{IMX327_REG_DELAY, 0x18},
++	{0x3005, 0x01},
++	{0x3007, 0x00},
++	{0x3009, 0x02},
++	{0x300A, 0xF0},
++	{0x300B, 0x00},
++	{0x3011, 0x0A},
++	{0x3012, 0x64},
++	{0x3014, 0x00},
++	{0x3018, 0x65},// 1125
++	{0x3019, 0x04},
++	{0x301A, 0x00},
++	{0x301C, 0xa0},//0x1130:30fps 0x14a0:25fps
++	{0x301D, 0x14},
++	{0x3022, 0x00},
++	{0x3046, 0x01},
++	{0x3048, 0x00},
++	{0x3049, 0x08},
++	{0x304B, 0x0A},
++	{0x305C, 0x18},
++	{0x305D, 0x03},
++	{0x305E, 0x20},
++	{0x305F, 0x01},
++	{0x309E, 0x4A},
++	{0x309F, 0x4A},
++	{0x30D2, 0x19},
++	{0x30D7, 0x03},
++	{0x3129, 0x00},
++	{0x313B, 0x61},
++	{0x315E, 0x1A},
++	{0x3164, 0x1A},
++	{0x317C, 0x00},
++	{0x31EC, 0x0E},
++	{0x3405, 0x10},
++	{0x3407, 0x01},
++	{0x3414, 0x0A},
++	{0x3418, 0x49},
++	{0x3419, 0x04},
++	{0x3441, 0x0C},
++	{0x3442, 0x0C},
++	{0x3443, 0x01},
++	{0x3444, 0x20},
++	{0x3445, 0x25},
++	{0x3446, 0x57},
++	{0x3447, 0x00},
++	{0x3448, 0x37},
++	{0x3449, 0x00},
++	{0x344A, 0x2F},//1f
++	{0x344B, 0x00},
++	{0x344C, 0x1F},
++	{0x344D, 0x00},
++	{0x344E, 0x1F},
++	{0x344F, 0x00},
++	{0x3450, 0x77},
++	{0x3451, 0x00},
++	{0x3452, 0x1F},
++	{0x3453, 0x00},
++	{0x3454, 0x17},
++	{0x3455, 0x00},
++	{0x346a, 0x9c},//EBD
++	{0x346b, 0x07},
++	{0x3472, 0x9C},
++	{0x3473, 0x07},
++	{0x3480, 0x49},
++//	{IMX327_REG_DELAY, 0x18},
++	{0x3001, 0x00},//standy cancel
++	{0x3002, 0x00},//Master start
++	{0x3000, 0x01},//standy cancel
++	{IMX327_REG_END, 0x00},/* END MARKER */
++};
++
++
++static struct regval_list imx327_init_regs_1920_1080_30fps_mipi_2dol_lcg[] = {
++//add
++	{0x3000, 0x01},//standy
++	{0x3001, 0x01},
++	{0x3002, 0x01},//Master stop
++//	{IMX327_REG_DELAY, 0x18},
++//	{0x3002, 0x00},
++	{0x3005, 0x01},//ADBIT 01:12bit
++	{0x3007, 0x40},//WINMODE[6:4]
++	{0x3009, 0x01},//FRSEL[1:0]
++	{0x300a, 0xf0},
++	{0x300c, 0x11},//WDMODE[0] WDSEL[5:4]
++	{0x3010, 0x61},//FPGC gain for each gain
++	{0x30f0, 0x64},//FPGC1 gain for each gain
++	{0x3011, 0x02},
++	{0x3018, 0x6E},//Vmax FSC=vmax*2
++	{0x3019, 0x05},//0x486
++	{0x301c, 0x58},//Hmax
++	{0x301d, 0x08},
++#if 0
++	{0x3018, 0x86},//Vmax FSC=vmax*2
++	{0x3019, 0x04},//0x486  1158  60.04fps
++	{0x301c, 0x05},//Hmax   2136 0x858
++	{0x301d, 0x0a},
++#endif
++#if 1
++	{0x3020, 0x02},//SHS1 S
++	{0x3021, 0x00},
++#else
++//	{0x3014, 0x70},
++	{0x3020, 0x02},//SHS1 S
++	{0x3021, 0x00},
++	{0x3022, 0x00},
++#endif
++	{0x3024, 0x73},//SHS2 L
++	{0x3025, 0x04},
++	{0x3028, 0x00},//SHS3
++	{0x3029, 0x00},
++	{0x302a, 0x00},
++	{0x3030, 0x65},//RHS1
++	{0x3031, 0x00},
++	{0x3032, 0x00},
++	{0x3034, 0x00},//RHS2
++	{0x3035, 0x00},
++	{0x3036, 0x00},
++	{0x303c, 0x04},//WINPV[7:0]
++	{0x303d, 0x00},//WINPV[2:0]
++	{0x303e, 0x41},//WINWV[7:0]
++	{0x303f, 0x04},//WINWV[2:0]
++	{0x3045, 0x05},
++	{0x3046, 0x01},//ODBIT[1:0]
++	{0x304b, 0x0a},
++	{0x305c, 0x18},
++	{0x305d, 0x03},
++	{0x305e, 0x20},
++	{0x305f, 0x01},
++	{0x309e, 0x4a},
++	{0x309f, 0x4a},
++	{0x30d2, 0x19},
++	{0x30d7, 0x03},
++	{0x3106, 0x11},
++	{0x3129, 0x00},
++	{0x313b, 0x61},
++	{0x315e, 0x1a},
++	{0x3164, 0x1a},
++#if 0
++	{0x31a0, 0xbc},
++	{0x31a1, 0x00},
++
++#endif
++	{0x317c, 0x00},
++	{0x31ec, 0x0e},
++	{0x3204, 0x4a},
++	{0x3209, 0xf0},
++	{0x320a, 0x22},
++	{0x3344, 0x38},
++	{0x3405, 0x00},
++	{0x3407, 0x01},
++	{0x3414, 0x00},//OPB_SIZE_V[5:0]
++	{0x3415, 0x00},//NULL0_SIZE_V[5:0]
++	{0x3418, 0x7a},//Y_OUT_SIZE[7:0]
++	{0x3419, 0x09},//Y_OUT_SIZE[4:0]
++	{0x3441, 0x0c},
++	{0x3442, 0x0c},
++	{0x3443, 0x01},
++	{0x3444, 0x20},
++	{0x3445, 0x25},
++	{0x3446, 0x77},
++	{0x3447, 0x00},
++	{0x3448, 0x67},
++	{0x3449, 0x00},
++	{0x344a, 0x47},
++	{0x344b, 0x00},
++	{0x344c, 0x37},
++	{0x344d, 0x00},
++	{0x344e, 0x3f},
++	{0x344f, 0x00},
++	{0x3450, 0xff},
++	{0x3451, 0x00},
++	{0x3452, 0x3f},
++	{0x3453, 0x00},
++	{0x3454, 0x37},
++	{0x3455, 0x00},
++	{0x346a, 0x9c},//EBD
++	{0x346b, 0x07},
++	{0x3472, 0xa0},
++	{0x3473, 0x07},
++	{0x347b, 0x23},
++	{0x3480, 0x49},
++//	{IMX327_REG_DELAY, 0x18},
++	{0x3001, 0x00},//standy cancel
++	{0x3002, 0x00},//Master start
++	{0x3000, 0x01},//standy cancel
++	{IMX327_REG_END, 0x00},/* END MARKER */
++
++};
++
++
++
++/*
++ * the part of driver was fixed.
++ */
++
++static struct regval_list imx327_stream_on_mipi[] = {
++	{0x3000, 0x00},
++	{IMX327_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list imx327_stream_off_mipi[] = {
++	{0x3000, 0x01},
++	{IMX327_REG_END, 0x00},	/* END MARKER */
++};
++
++static int imx327_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct imx327_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret = 0;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int imx327_write(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char value)
++{
++	struct imx327_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3] = {(reg>>8)&0xff, reg&0xff, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 3,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int imx327_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != IMX327_REG_END) {
++		if (vals->reg_num == IMX327_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = imx327_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++/*
++ * Write a list of register settings; ff/ff stops the process.
++ */
++static int imx327_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != IMX327_REG_END) {
++		if (vals->reg_num == IMX327_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = imx327_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++static int imx327_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	struct imx327_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++	} else {
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, !info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++	}
++	return 0;
++}
++
++static int imx327_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++	ret = imx327_read(sd, 0x301e, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != IMX327_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = imx327_read(sd, 0x301f, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != IMX327_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	return 0;
++}
++
++static struct imx327_win_size imx327_win_sizes[] = {
++	{
++		.width				= 1920,
++		.height				= 1080,
++		.sensor_info.fps				= 25 << 16 | 1,
++		.sensor_info.total_width			= 2136,
++		.sensor_info.total_height			= 2781,
++		.sensor_info.wdr_en				= 1,
++		.sensor_info.mipi_cfg.clk			= 891,
++		.sensor_info.mipi_cfg.twidth		= 1952,
++		.sensor_info.mipi_cfg.theight		= 1109,
++		.sensor_info.mipi_cfg.mipi_mode		= SENSOR_MIPI_SONY_MODE,
++		.sensor_info.mipi_cfg.mipi_vcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_hcomp_en		= 1,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 16,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 12,
++		.sensor_info.mipi_cfg.mipi_crop_start1x	= 16,
++		.sensor_info.mipi_cfg.mipi_crop_start1y	= 62,
++		.sensor_info.mipi_cfg.mipi_crop_start2x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3y	= 0,
++		.sensor_info.mipi_cfg.hcrop_diff_en		= 0,
++		.sensor_info.mipi_cfg.line_sync_mode	= 0,
++		.sensor_info.mipi_cfg.work_start_flag	= 0,
++		.sensor_info.mipi_cfg.data_type_en		= 0,
++		.sensor_info.mipi_cfg.data_type_value	= RAW12,
++		.sensor_info.mipi_cfg.del_start		= 1,
++		.sensor_info.mipi_cfg.sensor_frame_mode	= TX_SENSOR_WDR_2_FRAME_MODE,
++		.sensor_info.mipi_cfg.sensor_fid_mode	= 0,
++		.sensor_info.mipi_cfg.sensor_mode		= TX_SENSOR_NOT_VC_MODE,
++		.sensor_info.mipi_cfg.sensor_csi_fmt		= TX_SENSOR_RAW12,
++		.mbus_code	= MEDIA_BUS_FMT_SRGGB12_1X12,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= imx327_init_regs_1920_1080_30fps_mipi_2dol_lcg,
++	},
++	{
++		.width				= 1920,
++		.height				= 1080,
++		.sensor_info.fps				= 25 << 16 | 1,
++		.sensor_info.total_width			= 5280,
++		.sensor_info.total_height			= 1125,
++		.sensor_info.wdr_en				= 0,
++		.sensor_info.mipi_cfg.clk			= 445,
++		.sensor_info.mipi_cfg.twidth		= 1948,
++		.sensor_info.mipi_cfg.theight		= 1109,
++		.sensor_info.mipi_cfg.mipi_mode		= SENSOR_MIPI_SONY_MODE,
++		.sensor_info.mipi_cfg.mipi_vcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_hcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 12,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 20,
++		.sensor_info.mipi_cfg.mipi_crop_start1x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3y	= 0,
++		.sensor_info.mipi_cfg.hcrop_diff_en		= 0,
++		.sensor_info.mipi_cfg.line_sync_mode	= 0,
++		.sensor_info.mipi_cfg.work_start_flag	= 0,
++		.sensor_info.mipi_cfg.data_type_en		= 0,
++		.sensor_info.mipi_cfg.data_type_value	= RAW12,
++		.sensor_info.mipi_cfg.del_start		= 0,
++		.sensor_info.mipi_cfg.sensor_frame_mode	= TX_SENSOR_DEFAULT_FRAME_MODE,
++		.sensor_info.mipi_cfg.sensor_fid_mode	= 0,
++		.sensor_info.mipi_cfg.sensor_mode		= TX_SENSOR_DEFAULT_MODE,
++		.sensor_info.mipi_cfg.sensor_csi_fmt		= TX_SENSOR_RAW12,
++		.mbus_code	= MEDIA_BUS_FMT_SRGGB12_1X12,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= imx327_init_regs_1920_1080_30fps_mipi,
++	},
++};
++
++static int imx327_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_IMX327_FMTS)
++		return -EINVAL;
++
++	code->code = imx327_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int imx327_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct imx327_format_struct *ovfmt;
++	struct imx327_win_size *wsize;
++	struct imx327_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int imx327_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct imx327_info *info = to_state(sd);
++	struct imx327_win_size *wsize = info->win;
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = wsize->width;
++	fmt->height = wsize->height;
++	fmt->code = wsize->mbus_code;
++	fmt->colorspace = wsize->colorspace;
++	*(unsigned int *)fmt->reserved = &wsize->sensor_info;
++
++//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int imx327_s_wdr(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++	struct imx327_info *info = to_state(sd);
++	printk("%s:%d\n", __func__, value);
++	if(value)
++		info->win = &imx327_win_sizes[0];
++	else
++		info->win = &imx327_win_sizes[1];
++
++	return ret;
++}
++
++static int imx327_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int imx327_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int imx327_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int imx327_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int imx327_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int imx327_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	unsigned int again=(gain*20)>>LOG2_GAIN_SHIFT;
++	// Limit Max gain
++	if(again>AGAIN_MAX_DB+DGAIN_MAX_DB) again=AGAIN_MAX_DB+DGAIN_MAX_DB;
++	return again;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	return (((int32_t)regval)<<LOG2_GAIN_SHIFT)/20;
++}
++
++static int imx327_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	struct imx327_info *info = to_state(sd);
++	unsigned char v = 0;
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++
++	ret += imx327_read(sd, 0x3014, &v);
++	reg_val = v;
++
++	*value = regval_to_again(reg_val);
++
++	return ret;
++}
++
++static int imx327_g_again_short(struct v4l2_subdev *sd, __s32 *value)
++{
++	struct imx327_info *info = to_state(sd);
++	unsigned char v = 0;
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++	ret += imx327_read(sd, 0x30f2, &v);
++	reg_val = v;
++
++	*value = regval_to_again(reg_val);
++
++	return ret;
++}
++/*set analog gain db value, map value to sensor register.*/
++static int imx327_s_again(struct v4l2_subdev *sd, int again)
++{
++	struct imx327_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int ret = 0;
++
++//	printk("again = %d\n", again);
++	reg_value = again_to_regval(again);
++	ret += imx327_write(sd, 0x3014, (unsigned char)(reg_value & 0xff));
++
++	return ret;
++}
++
++static int imx327_s_again_short(struct v4l2_subdev *sd, int again)
++{
++	struct imx327_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int ret = 0;
++
++	reg_value = again_to_regval(again);
++	ret += imx327_write(sd, 0x30f2, (unsigned char)(reg_value & 0xff));
++
++
++	return ret;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int imx327_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int imx327_s_exp(struct v4l2_subdev *sd, int value)
++{
++	struct imx327_info *info = to_state(sd);
++	int ret = 0;
++	int shs = 0;
++	unsigned char val = 0;
++	int total_height = 0;
++
++//	printk("exp = %d\n", value);
++	ret = imx327_read(sd, 0x3019, &val);
++	total_height |= val << 8;
++	ret = imx327_read(sd, 0x3018, &val);
++	total_height |= val;
++
++	if(info->win->sensor_info.wdr_en) {
++		total_height *= 2;
++		shs = total_height - value - 1;
++		ret = imx327_write(sd, 0x3024, (unsigned char)(shs & 0xff));
++		ret += imx327_write(sd, 0x3025, (unsigned char)((shs >> 8) & 0xff));
++		ret += imx327_write(sd, 0x3026, (unsigned char)((shs >> 16) & 0x3));
++	} else {
++		shs = total_height - value - 1;
++		ret = imx327_write(sd, 0x3020, (unsigned char)(shs & 0xff));
++		ret += imx327_write(sd, 0x3021, (unsigned char)((shs >> 8) & 0xff));
++		ret += imx327_write(sd, 0x3022, (unsigned char)((shs >> 16) & 0x3));
++	}
++
++	return ret;
++}
++
++static int imx327_s_exp_short(struct v4l2_subdev *sd, int value)
++{
++	struct imx327_info *info = to_state(sd);
++	int ret = 0;
++
++	int shs = 101 - value - 1;
++	ret = imx327_write(sd, 0x3020, (unsigned char)(shs & 0xff));
++	ret += imx327_write(sd, 0x3021, (unsigned char)((shs >> 8) & 0xff));
++	ret += imx327_write(sd, 0x3022, (unsigned char)((shs >> 16) & 0x3));
++
++
++	return ret;
++}
++
++static int imx327_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct imx327_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return imx327_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return imx327_g_again(sd, &info->again->val);
++	case V4L2_CID_USER_ANALOG_GAIN_SHORT:
++		return imx327_g_again_short(sd, &info->again_short->val);
++	}
++	return -EINVAL;
++}
++
++static int imx327_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct imx327_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++		case V4L2_CID_BRIGHTNESS:
++			return imx327_s_brightness(sd, ctrl->val);
++		case V4L2_CID_CONTRAST:
++			return imx327_s_contrast(sd, ctrl->val);
++		case V4L2_CID_VFLIP:
++			return imx327_s_vflip(sd, ctrl->val);
++		case V4L2_CID_HFLIP:
++			return imx327_s_hflip(sd, ctrl->val);
++		case V4L2_CID_AUTOGAIN:
++			/* Only set manual gain if auto gain is not explicitly
++			   turned on. */
++			if (!ctrl->val) {
++				/* imx327_s_gain turns off auto gain */
++				return imx327_s_gain(sd, info->gain->val);
++			}
++			return imx327_s_autogain(sd, ctrl->val);
++		case V4L2_CID_GAIN:
++			return imx327_s_gain(sd, ctrl->val);
++		case V4L2_CID_ANALOGUE_GAIN:
++			return imx327_s_again(sd, ctrl->val);
++		case V4L2_CID_USER_ANALOG_GAIN_SHORT:
++			return imx327_s_again_short(sd, ctrl->val);
++		case V4L2_CID_EXPOSURE:
++			return imx327_s_exp(sd, ctrl->val);
++		case V4L2_CID_USER_EXPOSURE_SHORT:
++			return imx327_s_exp_short(sd, ctrl->val);
++		case V4L2_CID_WIDE_DYNAMIC_RANGE:
++			return imx327_s_wdr(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops imx327_ctrl_ops = {
++	.s_ctrl = imx327_s_ctrl,
++	.g_volatile_ctrl = imx327_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int imx327_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = imx327_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int imx327_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	imx327_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++static int imx327_core_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct imx327_info *info = to_state(sd);
++	int ret = 0;
++	ret = imx327_write_array(sd, info->win->regs);
++	return ret;
++}
++
++static int imx327_core_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct imx327_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(10);
++	}
++	return 0;
++}
++
++
++int imx327_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct imx327_info *info = to_state(sd);
++	int ret = 0;
++
++	if (enable) {
++		ret = imx327_write_array(sd, imx327_stream_on_mipi);
++		pr_debug("imx327 stream on\n");
++
++	}
++	else {
++		ret = imx327_write_array(sd, imx327_stream_off_mipi);
++		pr_debug("imx327 stream off\n");
++	}
++	return ret;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops imx327_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = imx327_g_register,
++	.s_register = imx327_s_register,
++#endif
++	.init = imx327_core_init,
++	.reset = imx327_core_reset,
++
++};
++
++static const struct v4l2_subdev_video_ops imx327_video_ops = {
++	.s_stream = imx327_s_stream,
++};
++
++static const struct v4l2_subdev_pad_ops imx327_pad_ops = {
++	//.enum_frame_interval = imx327_enum_frame_interval,
++	//.num_frame_size = imx327_enum_frame_size,
++	//.enum_mbus_code = imx327_enum_mbus_code,
++	.set_fmt = imx327_set_fmt,
++	.get_fmt = imx327_get_fmt,
++};
++
++static const struct v4l2_subdev_ops imx327_ops = {
++	.core = &imx327_core_ops,
++	.video = &imx327_video_ops,
++	.pad = &imx327_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int imx327_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_fract tpf;
++	struct v4l2_subdev *sd;
++	struct imx327_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++	unsigned long rate;
++	struct v4l2_ctrl_config cfg = {0};
++	int mclk_index = -1;
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutp-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutp.pin = gpio;
++		info->ircutp.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutn.pin = gpio;
++		info->ircutn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	v4l2_i2c_subdev_init(sd, client, &imx327_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++#if 1
++
++	char id_div[9];
++	char id_mux[9];
++	printk("%s:%d\n", __func__, __LINE__);
++	of_property_read_u32(client->dev.of_node, "ingenic,mclk", &mclk_index);
++	if(mclk_index == 0) {
++		memcpy(id_div, "div_cim0", sizeof(id_div));
++		memcpy(id_mux, "mux_cim0", sizeof(id_mux));
++	} else if(mclk_index == 1) {
++		memcpy(id_div, "div_cim1", sizeof(id_div));
++		memcpy(id_mux, "mux_cim1", sizeof(id_mux));
++	} else if(mclk_index == 2) {
++		memcpy(id_div, "div_cim2", sizeof(id_div));
++		memcpy(id_mux, "mux_cim2", sizeof(id_mux));
++	} else
++		printk("Unkonwn mclk index\n");
++
++
++	info->clk = v4l2_clk_get(&client->dev, id_div);
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++	info->sclka = devm_clk_get(&client->dev, id_mux);
++
++	printk("sclka is %s\n", info->sclka?"NOT NULL":"NULL");
++	rate = v4l2_clk_get_rate(info->clk);
++	if (((rate / 1000) % 37125) != 0) {
++		ret = clk_set_parent(info->sclka, clk_get(NULL, "epll"));
++		info->sclka = devm_clk_get(&client->dev, "epll");
++		if (IS_ERR(info->sclka)) {
++			pr_err("get sclka failed\n");
++		} else {
++			rate = clk_get_rate(info->sclka);
++			if (((rate / 1000) % 37125) != 0) {
++				clk_set_rate(info->sclka, 891000000);
++			}
++		}
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 37125000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++#endif
++
++
++	imx327_core_reset(sd, 1);
++#if 1
++	/* Make sure it's an imx327 */
++	ret = imx327_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an imx327 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++
++	/*IRCUT ctl 0:off 1:on*/
++	imx327_ircut(sd, 0);
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 10);
++	v4l2_ctrl_new_std(&info->hdl, &imx327_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &imx327_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &imx327_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &imx327_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &imx327_ctrl_ops,
++			V4L2_CID_WIDE_DYNAMIC_RANGE, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &imx327_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &imx327_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 589824, 1, 10000);
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &imx327_ctrl_ops,
++			V4L2_CID_EXPOSURE, 1, 1176, 1, 1000);
++
++	cfg.ops = &imx327_ctrl_ops;
++	cfg.id = V4L2_CID_USER_EXPOSURE_SHORT;
++	cfg.name = "expo short";
++	cfg.type = V4L2_CTRL_TYPE_INTEGER;
++	cfg.min = 1;
++	cfg.max = 98;
++	cfg.step = 1;
++	cfg.def = 50;
++	info->exposure_short = v4l2_ctrl_new_custom(&info->hdl, &cfg, NULL);
++
++	memset(&cfg, 0, sizeof(cfg));
++	cfg.ops = &imx327_ctrl_ops;
++	cfg.id = V4L2_CID_USER_ANALOG_GAIN_SHORT;
++	cfg.name = "analog gain short";
++	cfg.type = V4L2_CTRL_TYPE_INTEGER;
++	cfg.min = 0;
++	cfg.max = 589824;
++	cfg.step = 1;
++	cfg.def = 10000;
++	info->again_short = v4l2_ctrl_new_custom(&info->hdl, &cfg, NULL);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "imx327 Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int imx327_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct imx327_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id imx327_id[] = {
++	{ "imx327", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, imx327_id);
++
++static const struct of_device_id imx327_of_match[] = {
++	{.compatible = "ovti,imx327", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, imx327_of_match);
++
++
++static struct i2c_driver imx327_driver = {
++	.driver = {
++		.name	= "imx327",
++		.of_match_table = of_match_ptr(imx327_of_match),
++	},
++	.probe		= imx327_probe,
++	.remove		= imx327_remove,
++	.id_table	= imx327_id,
++};
++
++module_i2c_driver(imx327_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for OmniVision imx327 sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp-v2/ov2735a.c b/module_drivers/drivers/media/i2c/ingenic-isp-v2/ov2735a.c
+new file mode 100644
+index 000000000..15e4d8e1c
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp-v2/ov2735a.c
+@@ -0,0 +1,1132 @@
++/*
++ * A V4L2 driver for OmniVision OV2735a cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++#include <linux/clk.h>
++#include <isp-sensor.h>
++
++
++#define OV2735A_CHIP_ID_H	(0x27)
++#define OV2735A_CHIP_ID_L	(0x35)
++#define OV2735A_REG_END		0xff
++#define OV2735A_REG_DELAY	0x00
++#define OV2735A_PAGE_REG	    0xfd
++
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct ov2735a_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct ov2735a_gpio {
++	int pin;
++	int active_level;
++};
++
++struct ov2735a_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++	struct clk *sclka;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct ov2735a_win_size *win;
++
++	struct ov2735a_gpio reset;
++	struct ov2735a_gpio ircutp;
++	struct ov2735a_gpio ircutn;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++
++struct again_lut ov2735a_again_lut[] = {
++	{0x10,	0},
++	{0x11,	5731},
++	{0x12,	11136},
++	{0x13,	16248},
++	{0x14,	21097},
++	{0x15,	25710},
++	{0x16,	30109},
++	{0x17,	34312},
++	{0x18,	38336},
++	{0x19,	42195},
++	{0x1a,	45904},
++	{0x1b,	49472},
++	{0x1c,	52910},
++	{0x1d,	56228},
++	{0x1e,	59433},
++	{0x1f,	62534},
++	{0x20,	65536},
++	{0x22,	71267},
++	{0x24,	76672},
++	{0x26,	81784},
++	{0x28,	86633},
++	{0x2a,	91246},
++	{0x2c,	95645},
++	{0x2e,	99848},
++	{0x30,	103872},
++	{0x32,	107731},
++	{0x34,	111440},
++	{0x36,	115008},
++	{0x38,	118446},
++	{0x3a,	121764},
++	{0x3c,	124969},
++	{0x3e,	128070},
++	{0x40,	131072},
++	{0x44,	136803},
++	{0x48,	142208},
++	{0x4c,	147320},
++	{0x50,	152169},
++	{0x54,	156782},
++	{0x58,	161181},
++	{0x5c,	165384},
++	{0x60,	169408},
++	{0x64,	173267},
++	{0x68,	176976},
++	{0x6c,	180544},
++	{0x70,	183982},
++	{0x74,	187300},
++	{0x78,	190505},
++	{0x7c,	193606},
++	{0x80,	196608},
++	{0x88,	202339},
++	{0x90,	207744},
++	{0x98,	212856},
++	{0xa0,	217705},
++	{0xa8,	222318},
++	{0xb0,	226717},
++	{0xb8,	230920},
++	{0xc0,	234944},
++	{0xc8,	238803},
++	{0xd0,	242512},
++	{0xd8,	246080},
++	{0xe0,	249518},
++	{0xe8,	252836},
++	{0xf0,	256041},
++	{0xf8,	259142},
++};
++
++static inline struct ov2735a_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct ov2735a_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct ov2735a_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++static struct regval_list ov2735a_init_regs_1920_1080_30fps_MIPI[] = {
++	{0xfd, 0x00},
++	{OV2735A_REG_DELAY, 0x05},
++	{0xfd, 0x00},
++	{0x2f, 0x10},
++	{0x34, 0x00},
++	{0x30, 0x15},
++	{0x33, 0x01},
++	{0x35, 0x20},
++	{0xfd, 0x01},
++	{0x0d, 0x00},
++	{0x30, 0x00},
++	{0x03, 0x01},
++	{0x04, 0x8f},
++	{0x01, 0x01},
++	{0x09, 0x00},
++	{0x0a, 0x20},
++	{0x06, 0x0a},
++	{0x24, 0x10},
++	{0x01, 0x01},
++	{0xfb, 0x73},
++	{0x01, 0x01},
++	{0xfd, 0x01},
++	{0x1a, 0x6b},
++	{0x1c, 0xea},
++	{0x16, 0x0c},
++	{0x21, 0x00},
++	{0x11, 0xe8},//;63	;fr
++	{0x19, 0xc3},
++	{0x26, 0xda},
++	{0x29, 0x01},
++	{0x33, 0x6f},
++	{0x2a, 0xd2},
++	{0x2c, 0x40},
++	{0xd0, 0x02},
++	{0xd1, 0x01},
++	{0xd2, 0x20},
++	{0xd3, 0x03},//;04	;
++	{0xd4, 0xa4},//;2a	;
++	{0x50, 0x00},
++	{0x51, 0x2c},
++	{0x52, 0x29},
++	{0x53, 0x00},
++	{0x55, 0x44},
++	{0x58, 0x29},
++	{0x5a, 0x00},
++	{0x5b, 0x00},
++	{0x5d, 0x00},
++	{0x64, 0x2f},
++	{0x66, 0x62},
++	{0x68, 0x5b},
++	{0x75, 0x46},
++	{0x76, 0xf0},
++	{0x77, 0x4f},
++	{0x78, 0xef},
++	{0x72, 0xcf},
++	{0x73, 0x36},
++	{0x7d, 0x0d},
++	{0x7e, 0x0d},
++	{0x8a, 0x77},
++	{0x8b, 0x77},
++	{0xfd, 0x01},
++	{0xb1, 0x83},//;DPHY enable 8b
++
++//	{0xb2, 0x40},//hs mode
++
++	{0xb3, 0x0b},//;0b;09;1d
++	{0xb4, 0x14},//;MIPI PLL enable;14;35;36
++	{0x9d, 0x40},//;mipi hs dc level 40/03/55
++	{0xa1, 0x05},//;speed/03
++	{0x94, 0x44},//;dphy time
++	{0x95, 0x33},//;dphy time
++	{0x96, 0x1f},//;dphy time
++	{0x98, 0x45},//;dphy time
++	{0x9c, 0x10},//;dphy time
++	{0xb5, 0x70},//;30
++	{0xa0, 0x01},//;mipi enable
++	{0x25, 0xe0},
++	{0x20, 0x7b},
++	{0x8f, 0x88},
++	{0x91, 0x40},
++
++	{0xfd, 0x02},
++	{0x5e, 0x03},
++	{0xa1, 0x04},
++	{0xa3, 0x40},
++	{0xa5, 0x02},
++	{0xa7, 0xc4},
++	{0xfd, 0x01},
++	{0x86, 0x77},
++	{0x89, 0x77},
++	{0x87, 0x74},
++	{0x88, 0x74},
++	{0xfc, 0xe0},
++	{0xfe, 0xe0},
++	{0xf0, 0x40},
++	{0xf1, 0x40},
++	{0xf2, 0x40},
++	{0xf3, 0x40},
++
++#if 1
++	{0xfd, 0x02},//;;crop to 1920x1080
++	{0xa0, 0x00},//;Image vertical start MSB3bits
++	{0xa1, 0x08},//;Image vertical start LSB8bits
++	{0xa2, 0x04},//;image vertical size  MSB8bits
++	{0xa3, 0x38},//;image vertical size  LSB8bits
++	{0xa4, 0x00},
++	{0xa5, 0x04},//;H start 8Lsb, keep center
++	{0xa6, 0x03},
++	{0xa7, 0xc0},//;Half H size Lsb8bits
++	{0xfd, 0x01},
++	{0x8e, 0x07},
++	{0x8f, 0x80},//;MIPI column number
++	{0x90, 0x04},//;MIPI row number
++	{0x91, 0x38},
++
++	{0xfd, 0x03},
++	{0xc0, 0x01},//;enable transfer OTP BP information
++	{0xfd, 0x04},
++	{0x21, 0x14},
++	{0x22, 0x14},
++	{0x23, 0x14},//;enhance normal and dummy BPC
++
++	{0xfd, 0x01},
++	{0x06, 0xe0},//;insert dummy line , the frame rate is 30.01.
++//	{0x01, 0x01},//;
++//	{0xa0, 0x01},//;MIPI enable, stream on
++#else
++	{0xfd, 0x02},//;;crop to 1920x1080
++	{0xa0, 0x00},//;Image vertical start MSB3bits
++	{0xa1, 0x08},//;Image vertical start LSB8bits
++	{0xa2, 0x01},//;image vertical size  MSB8bits
++	{0xa3, 0xe0},//;image vertical size  LSB8bits
++	{0xa4, 0x00},
++	{0xa5, 0x04},//;H start 8Lsb, keep center
++	{0xa6, 0x01},
++	{0xa7, 0x40},//;Half H size Lsb8bits
++	{0xfd, 0x01},
++	{0x8e, 0x02},
++	{0x8f, 0x80},//;MIPI column number
++	{0x90, 0x01},//;MIPI row number
++	{0x91, 0xe0},
++
++	{0xfd, 0x03},
++	{0xc0, 0x01},//;enable transfer OTP BP information
++	{0xfd, 0x04},
++	{0x21, 0x14},
++	{0x22, 0x14},
++	{0x23, 0x14},//;enhance normal and dummy BPC
++
++	{0xfd, 0x01},
++	{0x06, 0xe0},//;insert dummy line , the frame rate is 30.01.
++	{0x01, 0x01},//;
++	{0xa0, 0x01},//;MIPI enable, stream on
++#endif
++
++#if 0
++	{0xfd, 0x01},//@@ 1 11 Mirror_On_Flip_Off
++
++	{0x3f, 0x01},//03
++	{0xf8, 0x00},//02
++	{0x01, 0x01},
++	{0xfd, 0x02},
++	{0x62, 0x01},//;full size mode flip off row start for OTP BPC
++	{0x63, 0x00},
++	{0xfd, 0x01},
++
++#endif
++#if 0
++	{0xfd, 0x01},//@@ 1 12 Mirror_On_Flip_On
++
++	{0x3f, 0x03},// 03
++
++	{0xf8, 0x02},//02
++
++	{0x01, 0x01},
++	{0xfd, 0x02},
++	{0x62, 0x48},
++	{0x63, 0x04},//;full size flip, row start:1096(0x448)
++	{0xfd, 0x01},
++#endif
++
++#if 0
++	{0xfd, 0x01},//@@ 1 13 Mirror_Off_Flip_Off
++
++	{0x3f, 0x00},//03
++	{0xf8, 0x00},// 02
++
++	{0x01, 0x01},
++	{0xfd, 0x02},
++	{0x62, 0x01},//;full size mode flip off row start for OTP BPC
++	{0x63, 0x00},
++	{0xfd, 0x01},
++#endif
++
++#if 1
++	{0xfd, 0x01},//@@ 1 14 Mirror_Off_Flip_On
++
++	{0x3f, 0x02},//03
++	{0xf8, 0x02},//02
++	{0x01, 0x01},
++
++	{0xfd, 0x02},
++	{0x62, 0x48},
++	{0x63, 0x04},//;full size flip, row start:1096(0x448)
++	{0xfd, 0x01},
++#endif
++
++	{0x01, 0x01},//;
++	{0xa0, 0x01},//;MIPI enable, stream on
++	{OV2735A_REG_END, 0x00},	/* END MARKER */
++};
++
++
++static struct regval_list ov2735a_stream_on[] = {
++	{0xfd, 0x00},
++	{0x36, 0x00},
++	{0x37, 0x00},//fake stream on
++	{OV2735A_REG_END, 0x00},
++};
++
++static struct regval_list ov2735a_stream_off[] = {
++	{0xfd, 0x00},
++	{0x36, 0x01},
++	{0x37, 0x01},//fake stream off
++	{OV2735A_REG_END, 0x00},
++};
++
++
++int ov2735a_read(struct v4l2_subdev *sd, unsigned char reg,
++		unsigned char *value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 1,
++			.buf	= &reg,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ov2735a_write(struct v4l2_subdev *sd, unsigned char reg,
++			unsigned char value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	unsigned char buf[2] = {reg, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 2,
++		.buf	= buf,
++	};
++	int ret;
++	unsigned int timeout  = 100;
++	while(timeout--){
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == -EAGAIN){
++			msleep(100);
++			continue;
++		}
++		else
++			break;
++	}
++	if(ret > 0)
++		ret = 0;
++	return ret;
++}
++
++static int ov2735a_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != OV2735A_REG_END) {
++		if (vals->reg_num == OV2735A_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = ov2735a_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++			if (vals->reg_num == OV2735A_PAGE_REG){
++				val &= 0xf8;
++				val |= (vals->value & 0x07);
++				ret = ov2735a_write(sd, vals->reg_num, val);
++				ret = ov2735a_read(sd, vals->reg_num, &val);
++			}
++		}
++		vals++;
++	}
++	return 0;
++}
++static int ov2735a_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != OV2735A_REG_END) {
++		if (vals->reg_num == OV2735A_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = ov2735a_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int ov2735a_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov2735a_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(10);
++	}
++	return 0;
++}
++
++static int ov2735a_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov2735a_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++	} else {
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, !info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++	}
++	return 0;
++}
++
++static int ov2735a_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov2735a_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = ov2735a_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++
++static int ov2735a_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++
++	ret = ov2735a_read(sd, 0x02, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != OV2735A_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = ov2735a_read(sd, 0x03, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != OV2735A_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	ret = ov2735a_read(sd, 0x04, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != 0x05 && v != 0x06 && v != 0x07)
++		return -ENODEV;
++
++
++	return 0;
++
++}
++
++static struct ov2735a_win_size ov2735a_win_sizes[] = {
++	{
++		.width				= 1920,
++		.height				= 1080,
++		.sensor_info.fps				= 30 << 16 | 1,
++		.sensor_info.total_width			= 1936,
++		.sensor_info.total_height			= 1096,
++		.sensor_info.wdr_en				= 0,
++		.sensor_info.mipi_cfg.clk			= 600,
++		.sensor_info.mipi_cfg.twidth		= 1920,
++		.sensor_info.mipi_cfg.theight		= 1080,
++		.sensor_info.mipi_cfg.mipi_mode		= SENSOR_MIPI_OTHER_MODE,
++		.sensor_info.mipi_cfg.mipi_vcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_hcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3y	= 0,
++		.sensor_info.mipi_cfg.hcrop_diff_en		= 0,
++		.sensor_info.mipi_cfg.line_sync_mode	= 0,
++		.sensor_info.mipi_cfg.work_start_flag	= 0,
++		.sensor_info.mipi_cfg.data_type_en		= 0,
++		.sensor_info.mipi_cfg.data_type_value	= RAW10,
++		.sensor_info.mipi_cfg.del_start		= 0,
++		.sensor_info.mipi_cfg.sensor_frame_mode	= TX_SENSOR_DEFAULT_FRAME_MODE,
++		.sensor_info.mipi_cfg.sensor_fid_mode	= 0,
++		.sensor_info.mipi_cfg.sensor_mode		= TX_SENSOR_DEFAULT_MODE,
++		.sensor_info.mipi_cfg.sensor_csi_fmt		= TX_SENSOR_RAW10,
++		.mbus_code	= MEDIA_BUS_FMT_SGRBG10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov2735a_init_regs_1920_1080_30fps_MIPI,
++	},
++};
++
++static int ov2735a_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_OV2735a_FMTS)
++		return -EINVAL;
++
++	code->code = ov2735a_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int ov2735a_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct ov2735a_format_struct *ovfmt;
++	struct ov2735a_win_size *wsize;
++	struct ov2735a_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int ov2735a_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct ov2735a_info *info = to_state(sd);
++	struct ov2735a_win_size *wsize = info->win;
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = wsize->width;
++	fmt->height = wsize->height;
++	fmt->code = wsize->mbus_code;
++	fmt->colorspace = wsize->colorspace;
++	*(unsigned int *)fmt->reserved = &wsize->sensor_info; /*reserved[0] reserved[1]*/
++
++//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int ov2735a_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov2735a_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov2735a_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov2735a_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int ov2735a_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int ov2735a_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++//	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov2735a_again_lut); i++) {
++		lut = &ov2735a_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov2735a_again_lut); i++) {
++		lut = &ov2735a_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return -EINVAL;
++}
++
++static int ov2735a_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	char v = 0;
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++
++	ret = ov2735a_read(sd, 0x23, &v);
++	reg_val |= v ;
++
++	*value = regval_to_again(reg_val);
++
++	return ret;
++
++}
++/*set analog gain db value, map value to sensor register.*/
++static int ov2735a_s_again(struct v4l2_subdev *sd, int value)
++{
++	struct ov2735a_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int ret = 0;
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(value);
++	}
++
++	ret = ov2735a_write(sd, 0xfd, 0x01);
++	ret += ov2735a_write(sd, 0x24, (unsigned char)reg_value);
++	ret += ov2735a_write(sd, 0x01, 0x01);
++	if (ret < 0){
++		printk("ov2735a_write error  %d\n" ,__LINE__ );
++		return ret;
++	}
++	return 0;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int ov2735a_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov2735a_s_exp(struct v4l2_subdev *sd, int value)
++{
++	struct ov2735a_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = ov2735a_write(sd, 0xfd, 0x01);
++	ret += ov2735a_write(sd, 0x4, (unsigned char)(value & 0xff));
++	ret += ov2735a_write(sd, 0x3, (unsigned char)((value & 0xff00) >> 8));
++	ret += ov2735a_write(sd, 0x01, 0x01);
++
++	if (ret < 0) {
++		printk("ov2735a_write error  %d\n" ,__LINE__);
++		return ret;
++	}
++	return ret;
++}
++
++static int ov2735a_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov2735a_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return ov2735a_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov2735a_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int ov2735a_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov2735a_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return ov2735a_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return ov2735a_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return ov2735a_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return ov2735a_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* ov2735a_s_gain turns off auto gain */
++			return ov2735a_s_gain(sd, info->gain->val);
++		}
++		return ov2735a_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return ov2735a_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov2735a_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return ov2735a_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops ov2735a_ctrl_ops = {
++	.s_ctrl = ov2735a_s_ctrl,
++	.g_volatile_ctrl = ov2735a_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ov2735a_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = ov2735a_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int ov2735a_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	ov2735a_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int ov2735a_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct ov2735a_info *info = to_state(sd);
++	int ret = 0;
++
++	if (enable) {
++		ov2735a_reset(sd, 1);
++		ov2735a_write_array(sd, info->win->regs);
++		ret = ov2735a_write_array(sd, ov2735a_stream_on);
++		printk("ov2735a stream on\n");
++
++	}
++	else {
++		ret = ov2735a_write_array(sd, ov2735a_stream_off);
++		printk("ov2735a stream off\n");
++	}
++	return ret;
++}
++
++
++int ov2735a_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct ov2735a_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops ov2735a_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = ov2735a_g_register,
++	.s_register = ov2735a_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops ov2735a_video_ops = {
++	.s_stream = ov2735a_s_stream,
++	.g_frame_interval	= ov2735a_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops ov2735a_pad_ops = {
++	//.enum_frame_interval = ov2735a_enum_frame_interval,
++	//.num_frame_size = ov2735a_enum_frame_size,
++	//.enum_mbus_code = ov2735a_enum_mbus_code,
++	.set_fmt = ov2735a_set_fmt,
++	.get_fmt = ov2735a_get_fmt,
++};
++
++static const struct v4l2_subdev_ops ov2735a_ops = {
++	.core = &ov2735a_core_ops,
++	.video = &ov2735a_video_ops,
++	.pad = &ov2735a_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int ov2735a_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_fract tpf;
++	struct v4l2_subdev *sd;
++	struct ov2735a_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++	unsigned long rate;
++	struct v4l2_ctrl_config cfg = {0};
++	int mclk_index = -1;
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutp-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutp.pin = gpio;
++		info->ircutp.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutn.pin = gpio;
++		info->ircutn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	v4l2_i2c_subdev_init(sd, client, &ov2735a_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++#if 1
++
++	char id_div[9];
++	char id_mux[9];
++	printk("%s:%d\n", __func__, __LINE__);
++	of_property_read_u32(client->dev.of_node, "ingenic,mclk", &mclk_index);
++	if(mclk_index == 0) {
++		memcpy(id_div, "div_cim0", sizeof(id_div));
++		memcpy(id_mux, "mux_cim0", sizeof(id_mux));
++	} else if(mclk_index == 1) {
++		memcpy(id_div, "div_cim1", sizeof(id_div));
++		memcpy(id_mux, "mux_cim1", sizeof(id_mux));
++	} else if(mclk_index == 2) {
++		memcpy(id_div, "div_cim2", sizeof(id_div));
++		memcpy(id_mux, "mux_cim2", sizeof(id_mux));
++	} else
++		printk("Unkonwn mclk index\n");
++
++
++	info->clk = v4l2_clk_get(&client->dev, id_div);
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++	info->sclka = devm_clk_get(&client->dev, id_mux);
++
++	printk("sclka is %s\n", info->sclka?"NOT NULL":"NULL");
++	rate = v4l2_clk_get_rate(info->clk);
++	if (((rate / 1000) % 24000) != 0) {
++		ret = clk_set_parent(info->sclka, clk_get(NULL, "epll"));
++		info->sclka = devm_clk_get(&client->dev, "epll");
++		if (IS_ERR(info->sclka)) {
++			pr_err("get sclka failed\n");
++		} else {
++			rate = clk_get_rate(info->sclka);
++			if (((rate / 1000) % 24000) != 0) {
++				clk_set_rate(info->sclka, 120000000);
++			}
++		}
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++#endif
++
++	info->win = &ov2735a_win_sizes[0];
++	ov2735a_reset(sd, 1);
++#if 1
++	/* Make sure it's an ov2735a */
++	ret = ov2735a_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an ov2735a chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++	/*IRCUT ctl 0:off 1:on*/
++	ov2735a_ircut(sd, 0);
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &ov2735a_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &ov2735a_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &ov2735a_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &ov2735a_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &ov2735a_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &ov2735a_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 259142, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov2735a_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1899 - 4, 1, 1500);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "ov2735a Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int ov2735a_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov2735a_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id ov2735a_id[] = {
++	{ "ov2735a", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ov2735a_id);
++
++static const struct of_device_id ov2735a_of_match[] = {
++	{.compatible = "ovti,ov2735a", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov2735a_of_match);
++
++
++static struct i2c_driver ov2735a_driver = {
++	.driver = {
++		.name	= "ov2735a",
++		.of_match_table = of_match_ptr(ov2735a_of_match),
++	},
++	.probe		= ov2735a_probe,
++	.remove		= ov2735a_remove,
++	.id_table	= ov2735a_id,
++};
++
++module_i2c_driver(ov2735a_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for OmniVision ov2735a sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp-v2/ov4689.c b/module_drivers/drivers/media/i2c/ingenic-isp-v2/ov4689.c
+new file mode 100644
+index 000000000..db5617af7
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp-v2/ov4689.c
+@@ -0,0 +1,1629 @@
++/*
++ * A V4L2 driver for OmniVision OV4689 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++#include <linux/clk.h>
++#include <isp-sensor.h>
++
++#define OV4689_CHIP_ID_H	(0x46)
++#define OV4689_CHIP_ID_L	(0x88)
++#define OV4689_REG_END		0xffff
++#define OV4689_REG_DELAY	0xfffe
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct ov4689_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct ov4689_gpio {
++	int pin;
++	int active_level;
++};
++
++struct ov4689_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++	struct clk *sclka;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct ov4689_win_size *win;
++
++	struct ov4689_gpio reset;
++	struct ov4689_gpio ircutp;
++	struct ov4689_gpio ircutn;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++struct again_lut ov4689_again_lut[] = {
++
++	{0x80, 0},
++	{0x88, 5731},
++	{0x90, 11136},
++	{0x98, 16248},
++	{0xa0, 21097},
++	{0xa8, 25710},
++	{0xb0, 30109},
++	{0xb8, 34312},
++	{0xc0, 38336},
++	{0xc8, 42195},
++	{0xd0, 45904},
++	{0xd8, 49472},
++	{0xe0, 52910},
++	{0xe8, 56228},
++	{0xf0, 59433},
++	{0xf8, 62534},
++	{0x178, 65536},
++	{0x17c, 68445},
++	{0x180, 71267},
++	{0x184, 74008},
++	{0x188, 76672},
++	{0x18c, 79262},
++	{0x190, 81784},
++	{0x194, 84240},
++	{0x198, 86633},
++	{0x19c, 88968},
++	{0x1a0, 91246},
++	{0x1a4, 93471},
++	{0x1a8, 95645},
++	{0x1ac, 97770},
++	{0x1b0, 99848},
++	{0x1b4, 101881},
++	{0x1b8, 103872},
++	{0x1bc, 105821},
++	{0x1c0, 107731},
++	{0x1c4, 109604},
++	{0x1c8, 111440},
++	{0x1cc, 113241},
++	{0x1d0, 115008},
++	{0x1d4, 116743},
++	{0x1d8, 118446},
++	{0x1dc, 120120},
++	{0x1e0, 121764},
++	{0x1e4, 123380},
++	{0x1e8, 124969},
++	{0x1ec, 126532},
++	{0x1f0, 128070},
++	{0x1f4, 129583},
++	{0x374, 131072},
++	{0x376, 132537},
++	{0x378, 133981},
++	{0x37a, 135403},
++	{0x37c, 136803},
++	{0x37e, 138184},
++	{0x380, 139544},
++	{0x382, 140885},
++	{0x384, 142208},
++	{0x386, 143512},
++	{0x388, 144798},
++	{0x38a, 146067},
++	{0x38c, 147320},
++	{0x38e, 148556},
++	{0x390, 149776},
++	{0x392, 150980},
++	{0x394, 152169},
++	{0x396, 153344},
++	{0x398, 154504},
++	{0x39a, 155650},
++	{0x39c, 156782},
++	{0x39e, 157901},
++	{0x3a0, 159007},
++	{0x3a2, 160100},
++	{0x3a4, 161181},
++	{0x3a6, 162249},
++	{0x3a8, 163306},
++	{0x3aa, 164350},
++	{0x3ac, 165384},
++	{0x3ae, 166406},
++	{0x3b0, 167417},
++	{0x3b2, 168418},
++	{0x3b4, 169408},
++	{0x3b6, 170387},
++	{0x3b8, 171357},
++	{0x3ba, 172317},
++	{0x3bc, 173267},
++	{0x3be, 174208},
++	{0x3c0, 175140},
++	{0x3c2, 176062},
++	{0x3c4, 176976},
++	{0x3c6, 177880},
++	{0x3c8, 178777},
++	{0x3ca, 179664},
++	{0x3cc, 180544},
++	{0x3ce, 181415},
++	{0x3d0, 182279},
++	{0x3d2, 183134},
++	{0x3d4, 183982},
++	{0x3d6, 184823},
++	{0x3d8, 185656},
++	{0x3da, 186482},
++	{0x3dc, 187300},
++	{0x3de, 188112},
++	{0x3e0, 188916},
++	{0x3e2, 189714},
++	{0x3e4, 190505},
++	{0x3e6, 191290},
++	{0x3e8, 192068},
++	{0x3ea, 192840},
++	{0x3ec, 193606},
++	{0x3ee, 194365},
++	{0x3f0, 195119},
++	{0x3f2, 195866},
++	{0x778, 196608},
++	{0x779, 197343},
++	{0x77a, 198073},
++	{0x77b, 198798},
++	{0x77c, 199517},
++	{0x77d, 200230},
++	{0x77e, 200939},
++	{0x77f, 201642},
++	{0x780, 202339},
++	{0x781, 203032},
++	{0x782, 203720},
++	{0x783, 204402},
++	{0x784, 205080},
++	{0x785, 205753},
++	{0x786, 206421},
++	{0x787, 207085},
++	{0x788, 207744},
++	{0x789, 208398},
++	{0x78a, 209048},
++	{0x78b, 209693},
++	{0x78c, 210334},
++	{0x78d, 210971},
++	{0x78e, 211603},
++	{0x78f, 212232},
++	{0x790, 212856},
++	{0x791, 213476},
++	{0x792, 214092},
++	{0x793, 214704},
++	{0x794, 215312},
++	{0x795, 215916},
++	{0x796, 216516},
++	{0x797, 217113},
++	{0x798, 217705},
++	{0x799, 218294},
++	{0x79a, 218880},
++	{0x79b, 219462},
++	{0x79c, 220040},
++	{0x79d, 220615},
++	{0x79e, 221186},
++	{0x79f, 221754},
++	{0x7a0, 222318},
++	{0x7a1, 222880},
++	{0x7a2, 223437},
++	{0x7a3, 223992},
++	{0x7a4, 224543},
++	{0x7a5, 225091},
++	{0x7a6, 225636},
++	{0x7a7, 226178},
++	{0x7a8, 226717},
++	{0x7a9, 227253},
++	{0x7aa, 227785},
++	{0x7ab, 228315},
++	{0x7ac, 228842},
++	{0x7ad, 229365},
++	{0x7ae, 229886},
++	{0x7af, 230404},
++	{0x7b0, 230920},
++	{0x7b1, 231432},
++	{0x7b2, 231942},
++	{0x7b3, 232449},
++	{0x7b4, 232953},
++	{0x7b5, 233455},
++	{0x7b6, 233954},
++	{0x7b7, 234450},
++	{0x7b8, 234944},
++	{0x7b9, 235435},
++	{0x7ba, 235923},
++	{0x7bb, 236410},
++	{0x7bc, 236893},
++	{0x7bd, 237374},
++	{0x7be, 237853},
++	{0x7bf, 238329},
++	{0x7c0, 238803},
++	{0x7c1, 239275},
++	{0x7c2, 239744},
++	{0x7c3, 240211},
++	{0x7c4, 240676},
++	{0x7c5, 241138},
++	{0x7c6, 241598},
++	{0x7c7, 242056},
++	{0x7c8, 242512},
++	{0x7c9, 242965},
++	{0x7ca, 243416},
++	{0x7cb, 243865},
++	{0x7cc, 244313},
++	{0x7cd, 244757},
++	{0x7ce, 245200},
++	{0x7cf, 245641},
++	{0x7d0, 246080},
++	{0x7d1, 246517},
++	{0x7d2, 246951},
++	{0x7d3, 247384},
++	{0x7d4, 247815},
++	{0x7d5, 248243},
++	{0x7d6, 248670},
++	{0x7d7, 249095},
++	{0x7d8, 249518},
++	{0x7d9, 249939},
++	{0x7da, 250359},
++	{0x7db, 250776},
++	{0x7dc, 251192},
++	{0x7dd, 251606},
++	{0x7de, 252018},
++	{0x7df, 252428},
++	{0x7e0, 252836},
++	{0x7e1, 253243},
++	{0x7e2, 253648},
++	{0x7e3, 254051},
++	{0x7e4, 254452},
++	{0x7e5, 254852},
++	{0x7e6, 255250},
++	{0x7e7, 255647},
++	{0x7e8, 256041},
++	{0x7e9, 256435},
++	{0x7ea, 256826},
++	{0x7eb, 257216},
++	{0x7ec, 257604},
++	{0x7ed, 257991},
++	{0x7ee, 258376},
++	{0x7ef, 258760},
++	{0x7f0, 259142},
++	{0x7f1, 259522},
++	{0x7f2, 259901},
++	{0x7f3, 260279},
++	{0x7f4, 260655},
++	{0x7f5, 261029},
++	{0x7f6, 261402},
++	{0x7f7, 261773},
++};
++
++static inline struct ov4689_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct ov4689_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct ov4689_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++static struct regval_list ov4689_init_regs_1920_1080_30fps_mipi[] = {
++	//1080p@30fps 2 or 4 lane
++	/* @@ 0 35 RES_1920x1080_30fps_816Mbps  2Lane */
++	/* ;SCLK = 80MHz MIPI CLK = 816Mbps/lane Mipi PCLK = 102MHz */
++	/* ;HTS = 2294 VTS = 1162 */
++	{0x0103, 0x01},
++	{0x3638, 0x00},
++	{0x0300, 0x00},
++	{0x0302, 0x23},
++	{0x0303, 0x01},
++	{0x0304, 0x03},
++	{0x030b, 0x00},
++	{0x030d, 0x1e},
++	{0x030e, 0x04},
++	{0x030f, 0x02},
++	{0x0312, 0x01},
++	{0x031e, 0x00},
++	{0x3000, 0x20},
++	{0x3002, 0x00},
++//	{0x3018, 0x72}, //4lan
++	{0x3018, 0x32}, //2lan
++	{0x3020, 0x93},
++	{0x3021, 0x03},
++	{0x3022, 0x01},
++	{0x3031, 0x0a},
++	{0x303f, 0x0c},
++	{0x3305, 0xf1},
++	{0x3307, 0x04},
++	{0x3309, 0x29},
++	{0x3500, 0x00},
++	{0x3501, 0x4c},
++	{0x3502, 0x00},
++	{0x3503, 0x04},
++	{0x3504, 0x00},
++	{0x3505, 0x00},
++	{0x3506, 0x00},
++	{0x3507, 0x00},
++	{0x3508, 0x00},
++	{0x3509, 0x80},
++	{0x350a, 0x00},
++	{0x350b, 0x00},
++	{0x350c, 0x00},
++	{0x350d, 0x00},
++	{0x350e, 0x00},
++	{0x350f, 0x80},
++	{0x3510, 0x00},
++	{0x3511, 0x00},
++	{0x3512, 0x00},
++	{0x3513, 0x00},
++	{0x3514, 0x00},
++	{0x3515, 0x80},
++	{0x3516, 0x00},
++	{0x3517, 0x00},
++	{0x3518, 0x00},
++	{0x3519, 0x00},
++	{0x351a, 0x00},
++	{0x351b, 0x80},
++	{0x351c, 0x00},
++	{0x351d, 0x00},
++	{0x351e, 0x00},
++	{0x351f, 0x00},
++	{0x3520, 0x00},
++	{0x3521, 0x80},
++	{0x3522, 0x08},
++	{0x3524, 0x08},
++	{0x3526, 0x08},
++	{0x3528, 0x08},
++	{0x352a, 0x08},
++	{0x3602, 0x00},
++	{0x3603, 0x40},
++	{0x3604, 0x02},
++	{0x3605, 0x00},
++	{0x3606, 0x00},
++	{0x3607, 0x00},
++	{0x3609, 0x12},
++	{0x360a, 0x40},
++	{0x360c, 0x08},
++	{0x360f, 0xe5},
++	{0x3608, 0x8f},
++	{0x3611, 0x00},
++	{0x3613, 0xf7},
++	{0x3616, 0x58},
++	{0x3619, 0x99},
++	{0x361b, 0x60},
++	{0x361c, 0x7a},
++	{0x361e, 0x79},
++	{0x361f, 0x02},
++	{0x3632, 0x00},
++	{0x3633, 0x10},
++	{0x3634, 0x10},
++	{0x3635, 0x10},
++	{0x3636, 0x15},
++	{0x3646, 0x86},
++	{0x364a, 0x0b},
++	{0x3700, 0x17},
++	{0x3701, 0x22},
++	{0x3703, 0x10},
++	{0x370a, 0x37},
++	{0x3705, 0x00},
++	{0x3706, 0x63},
++	{0x3709, 0x3c},
++	{0x370b, 0x01},
++	{0x370c, 0x30},
++	{0x3710, 0x24},
++	{0x3711, 0x0c},
++	{0x3716, 0x00},
++	{0x3720, 0x28},
++	{0x3729, 0x7b},
++	{0x372a, 0x84},
++	{0x372b, 0xbd},
++	{0x372c, 0xbc},
++	{0x372e, 0x52},
++	{0x373c, 0x0e},
++	{0x373e, 0x33},
++	{0x3743, 0x10},
++	{0x3744, 0x88},
++	{0x3745, 0xc0},
++	{0x374a, 0x43},
++	{0x374c, 0x00},
++	{0x374e, 0x23},
++	{0x3751, 0x7b},
++	{0x3752, 0x84},
++	{0x3753, 0xbd},
++	{0x3754, 0xbc},
++	{0x3756, 0x52},
++	{0x375c, 0x00},
++	{0x3760, 0x00},
++	{0x3761, 0x00},
++	{0x3762, 0x00},
++	{0x3763, 0x00},
++	{0x3764, 0x00},
++	{0x3767, 0x04},
++	{0x3768, 0x04},
++	{0x3769, 0x08},
++	{0x376a, 0x08},
++	{0x376b, 0x20},
++	{0x376c, 0x00},
++	{0x376d, 0x00},
++	{0x376e, 0x00},
++	{0x3773, 0x00},
++	{0x3774, 0x51},
++	{0x3776, 0xbd},
++	{0x3777, 0xbd},
++	{0x3781, 0x18},
++	{0x3783, 0x25},
++	{0x3798, 0x1b},
++	{0x3800, 0x01},
++	{0x3801, 0x88},
++	{0x3802, 0x00},
++	{0x3803, 0xe0},
++	{0x3804, 0x09},
++	{0x3805, 0x17},
++	{0x3806, 0x05},
++	{0x3807, 0x1f},
++	{0x3808, 0x07},
++	{0x3809, 0x80},
++	{0x380a, 0x04},
++	{0x380b, 0x38},
++	{0x380c, 0x08},
++	{0x380d, 0xf6},
++	{0x380e, 0x04},
++	{0x380f, 0x8A},
++	{0x3810, 0x00},
++	{0x3811, 0x08},
++	{0x3812, 0x00},
++	{0x3813, 0x04},
++	{0x3814, 0x01},
++	{0x3815, 0x01},
++	{0x3819, 0x01},
++	{0x3820, 0x00},
++	{0x3821, 0x06},
++	{0x3829, 0x00},
++	{0x382a, 0x01},
++	{0x382b, 0x01},
++	{0x382d, 0x7f},
++	{0x3830, 0x04},
++	{0x3836, 0x01},
++	{0x3837, 0x00},
++	{0x3841, 0x02},
++	{0x3846, 0x08},
++	{0x3847, 0x07},
++	{0x3d85, 0x36},
++	{0x3d8c, 0x71},
++	{0x3d8d, 0xcb},
++	{0x3f0a, 0x00},
++	{0x4000, 0xf1},
++	{0x4001, 0x40},
++	{0x4002, 0x04},
++	{0x4003, 0x14},
++	{0x400e, 0x00},
++	{0x4011, 0x00},
++	{0x401a, 0x00},
++	{0x401b, 0x00},
++	{0x401c, 0x00},
++	{0x401d, 0x00},
++	{0x401f, 0x00},
++	{0x4020, 0x00},
++	{0x4021, 0x10},
++	{0x4022, 0x06},
++	{0x4023, 0x13},
++	{0x4024, 0x07},
++	{0x4025, 0x40},
++	{0x4026, 0x07},
++	{0x4027, 0x50},
++	{0x4028, 0x00},
++	{0x4029, 0x02},
++	{0x402a, 0x06},
++	{0x402b, 0x04},
++	{0x402c, 0x02},
++	{0x402d, 0x02},
++	{0x402e, 0x0e},
++	{0x402f, 0x04},
++	{0x4302, 0xff},
++	{0x4303, 0xff},
++	{0x4304, 0x00},
++	{0x4305, 0x00},
++	{0x4306, 0x00},
++	{0x4308, 0x02},
++	{0x4500, 0x6c},
++	{0x4501, 0xc4},
++	{0x4502, 0x40},
++	{0x4503, 0x01},
++	{0x4601, 0x77},
++	{0x4800, 0x04},
++	{0x4813, 0x08},
++	{0x481f, 0x40},
++	{0x4829, 0x78},
++//	{0x4837, 0x14}, //for zebra
++	{0x4837, 0x80}, //for halley5
++	{0x4b00, 0x2a},
++	{0x4b0d, 0x00},
++	{0x4d00, 0x04},
++	{0x4d01, 0x42},
++	{0x4d02, 0xd1},
++	{0x4d03, 0x93},
++	{0x4d04, 0xf5},
++	{0x4d05, 0xc1},
++	{0x5000, 0xf3},
++	{0x5001, 0x11},
++	{0x5004, 0x00},
++	{0x500a, 0x00},
++	{0x500b, 0x00},
++	{0x5032, 0x00},
++	{0x5040, 0x00},
++	{0x5050, 0x0c},
++	{0x5500, 0x00},
++	{0x5501, 0x10},
++	{0x5502, 0x01},
++	{0x5503, 0x0f},
++	{0x8000, 0x00},
++	{0x8001, 0x00},
++	{0x8002, 0x00},
++	{0x8003, 0x00},
++	{0x8004, 0x00},
++	{0x8005, 0x00},
++	{0x8006, 0x00},
++	{0x8007, 0x00},
++	{0x8008, 0x00},
++	{0x3638, 0x00},
++	{0x0100, 0x00},
++	{OV4689_REG_END, 0x00},/* END MARKER */
++};
++
++static struct regval_list ov4689_init_regs_2592_1520_30fps_mipi[] = {
++	{0x0103, 0x01},
++	{0x3638, 0x00},
++	{0x0300, 0x00},
++	{0x0302, 0x19}, //0x19
++	{0x0303, 0x00},
++	{0x0304, 0x03}, //0x03
++	{0x030b, 0x00},
++	{0x030d, 0x1e},
++	{0x030e, 0x04},
++	{0x030f, 0x01},
++	{0x0311, 0x00},
++	{0x0312, 0x01},
++	{0x031e, 0x00},
++	{0x3000, 0x20},
++	{0x3002, 0x00},
++	{0x3018, 0x32},
++	{0x3019, 0x0c},
++	{0x3020, 0x93},
++	{0x3021, 0x03},
++	{0x3022, 0x01},
++	{0x3031, 0x0a},
++	{0x303f, 0x0c},
++	{0x3305, 0xf1},
++	{0x3307, 0x04},
++	{0x3309, 0x29},
++	{0x3500, 0x00},
++	{0x3501, 0x60},
++	{0x3502, 0x00},
++	{0x3503, 0x04},
++	{0x3504, 0x00},
++	{0x3505, 0x00},
++	{0x3506, 0x00},
++	{0x3507, 0x00},
++	{0x3508, 0x00},
++	{0x3509, 0x80},
++	{0x350a, 0x00},
++	{0x350b, 0x00},
++	{0x350c, 0x00},
++	{0x350d, 0x00},
++	{0x350e, 0x00},
++	{0x350f, 0x80},
++	{0x3510, 0x00},
++	{0x3511, 0x00},
++	{0x3512, 0x00},
++	{0x3513, 0x00},
++	{0x3514, 0x00},
++	{0x3515, 0x80},
++	{0x3516, 0x00},
++	{0x3517, 0x00},
++	{0x3518, 0x00},
++	{0x3519, 0x00},
++	{0x351a, 0x00},
++	{0x351b, 0x80},
++	{0x351c, 0x00},
++	{0x351d, 0x00},
++	{0x351e, 0x00},
++	{0x351f, 0x00},
++	{0x3520, 0x00},
++	{0x3521, 0x80},
++	{0x3522, 0x08},
++	{0x3524, 0x08},
++	{0x3526, 0x08},
++	{0x3528, 0x08},
++	{0x352a, 0x08},
++	{0x3602, 0x00},
++	{0x3603, 0x40},
++	{0x3604, 0x02},
++	{0x3605, 0x00},
++	{0x3606, 0x00},
++	{0x3607, 0x00},
++	{0x3609, 0x12},
++	{0x360a, 0x40},
++	{0x360c, 0x08},
++	{0x360f, 0xe5},
++	{0x3608, 0x8f},
++	{0x3611, 0x00},
++	{0x3613, 0xf7},
++	{0x3616, 0x58},
++	{0x3619, 0x99},
++	{0x361b, 0x60},
++	{0x361c, 0x7a},
++	{0x361e, 0x79},
++	{0x361f, 0x02},
++	{0x3632, 0x00},
++	{0x3633, 0x10},
++	{0x3634, 0x10},
++	{0x3635, 0x10},
++	{0x3636, 0x15},
++	{0x3646, 0x86},
++	{0x364a, 0x0b},
++	{0x3700, 0x17},
++	{0x3701, 0x22},
++	{0x3703, 0x10},
++	{0x370a, 0x37},
++	{0x3705, 0x00},
++	{0x3706, 0x63},
++	{0x3709, 0x3c},
++	{0x370b, 0x01},
++	{0x370c, 0x30},
++	{0x3710, 0x24},
++	{0x3711, 0x0c},
++	{0x3716, 0x00},
++	{0x3720, 0x28},
++	{0x3729, 0x7b},
++	{0x372a, 0x84},
++	{0x372b, 0xbd},
++	{0x372c, 0xbc},
++	{0x372e, 0x52},
++	{0x373c, 0x0e},
++	{0x373e, 0x33},
++	{0x3743, 0x10},
++	{0x3744, 0x88},
++	{0x3745, 0xc0},
++	{0x374a, 0x43},
++	{0x374c, 0x00},
++	{0x374e, 0x23},
++	{0x3751, 0x7b},
++	{0x3752, 0x84},
++	{0x3753, 0xbd},
++	{0x3754, 0xbc},
++	{0x3756, 0x52},
++	{0x375c, 0x00},
++	{0x3760, 0x00},
++	{0x3761, 0x00},
++	{0x3762, 0x00},
++	{0x3763, 0x00},
++	{0x3764, 0x00},
++	{0x3767, 0x04},
++	{0x3768, 0x04},
++	{0x3769, 0x08},
++	{0x376a, 0x08},
++	{0x376b, 0x20},
++	{0x376c, 0x00},
++	{0x376d, 0x00},
++	{0x376e, 0x00},
++	{0x3773, 0x00},
++	{0x3774, 0x51},
++	{0x3776, 0xbd},
++	{0x3777, 0xbd},
++	{0x3781, 0x18},
++	{0x3783, 0x25},
++	{0x3798, 0x1b},
++	{0x3800, 0x00},
++	{0x3801, 0x38},
++	{0x3802, 0x00},
++	{0x3803, 0x04},
++	{0x3804, 0x0a},
++	{0x3805, 0x67},
++	{0x3806, 0x05},
++	{0x3807, 0xfb},
++	{0x3808, 0x0a},
++	{0x3809, 0x20},
++	{0x380a, 0x05},
++	{0x380b, 0xf0},
++	{0x380c, 0x0A},
++	{0x380d, 0x82},//0x18
++	{0x380e, 0x06},
++	{0x380f, 0xfb},
++	{0x3810, 0x00},
++	{0x3811, 0x08},
++	{0x3812, 0x00},
++	{0x3813, 0x04},
++	{0x3814, 0x01},
++	{0x3815, 0x01},
++	{0x3819, 0x01},
++	{0x3820, 0x00},
++	{0x3821, 0x06},
++	{0x3829, 0x00},
++	{0x382a, 0x01},
++	{0x382b, 0x01},
++	{0x382d, 0x7f},
++	{0x3830, 0x04},
++	{0x3836, 0x01},
++	{0x3837, 0x00},
++	{0x3841, 0x02},
++	{0x3846, 0x08},
++	{0x3847, 0x07},
++	{0x3d85, 0x36},
++	{0x3d8c, 0x71},
++	{0x3d8d, 0xcb},
++	{0x3f0a, 0x00},
++	{0x4000, 0xf1},
++	{0x4001, 0x40},
++	{0x4002, 0x04},
++	{0x4003, 0x14},
++	{0x400e, 0x00},
++	{0x4011, 0x00},
++	{0x401a, 0x00},
++	{0x401b, 0x00},
++	{0x401c, 0x00},
++	{0x401d, 0x00},
++	{0x401f, 0x00},
++	{0x4020, 0x00},
++	{0x4021, 0x10},
++	{0x4022, 0x08},
++	{0x4023, 0xb3},
++	{0x4024, 0x09},
++	{0x4025, 0xe0},
++	{0x4026, 0x09},
++	{0x4027, 0xf0},//
++	{0x4028, 0x00},
++	{0x4029, 0x02},
++	{0x402a, 0x06},
++	{0x402b, 0x04},
++	{0x402c, 0x02},
++	{0x402d, 0x02},
++	{0x402e, 0x0e},
++	{0x402f, 0x04},
++	{0x4302, 0xff},
++	{0x4303, 0xff},
++	{0x4304, 0x00},
++	{0x4305, 0x00},
++	{0x4306, 0x00},
++	{0x4308, 0x02},
++	{0x4500, 0x6c},
++	{0x4501, 0xc4},
++	{0x4502, 0x40},
++	{0x4503, 0x01},
++	{0x4601, 0xA1},//
++	{0x4800, 0x04},
++	{0x4813, 0x08},
++	{0x481f, 0x40},
++	{0x4829, 0x78},
++	{0x4837, 0x10},
++	{0x4b00, 0x2a},
++	{0x4b0d, 0x00},
++	{0x4d00, 0x04},
++	{0x4d01, 0x42},
++	{0x4d02, 0xd1},
++	{0x4d03, 0x93},
++	{0x4d04, 0xf5},
++	{0x4d05, 0xc1},
++	{0x5000, 0xf3},
++	{0x5001, 0x11},
++	{0x5004, 0x00},
++	{0x500a, 0x00},
++	{0x500b, 0x00},
++	{0x5032, 0x00},
++	{0x5040, 0x00},
++	{0x5050, 0x0c},
++	{0x5500, 0x00},
++	{0x5501, 0x10},
++	{0x5502, 0x01},
++	{0x5503, 0x0f},
++	{0x8000, 0x00},
++	{0x8001, 0x00},
++	{0x8002, 0x00},
++	{0x8003, 0x00},
++	{0x8004, 0x00},
++	{0x8005, 0x00},
++	{0x8006, 0x00},
++	{0x8007, 0x00},
++	{0x8008, 0x00},
++	{0x3638, 0x00},
++	{0x0100, 0x00},
++	{OV4689_REG_END, 0x00},/* END MARKER */
++};
++
++
++
++
++static struct regval_list ov4689_stream_on[] = {
++	{0x0100,0x01},
++	{OV4689_REG_END, 0x00},
++};
++
++static struct regval_list ov4689_stream_off[] = {
++	{0x0100,0x00},
++	{OV4689_REG_END, 0x00},
++};
++
++
++int ov4689_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ov4689_write(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3] = {(reg>>8)&0xff, reg&0xff, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 3,
++		.buf	= buf,
++	};
++	int ret;
++	unsigned int timeout  = 100;
++	while(timeout--){
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == -EAGAIN){
++			msleep(100);
++			continue;
++		}
++		else
++			break;
++	}
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ov4689_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != OV4689_REG_END) {
++		if (vals->reg_num == OV4689_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ov4689_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++/*
++ * Write a list of register settings; ff/ff stops the process.
++ */
++static int ov4689_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != OV4689_REG_END) {
++		if (vals->reg_num == OV4689_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ov4689_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int ov4689_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov4689_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(10);
++	}
++	return 0;
++}
++
++static int ov4689_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov4689_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++	} else {
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, !info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++	}
++	return 0;
++}
++
++
++static int ov4689_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++	ret = ov4689_read(sd, 0x300a, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != OV4689_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = ov4689_read(sd, 0x300b, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != OV4689_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++	return 0;
++
++}
++
++static struct ov4689_win_size ov4689_win_sizes[] = {
++	{
++		.width				= 1920,
++		.height				= 1080,
++		.sensor_info.fps				= 30 << 16 | 1,
++		.sensor_info.total_width			= 2294,
++		.sensor_info.total_height			= 1162,
++		.sensor_info.wdr_en				= 0,
++		.sensor_info.mipi_cfg.clk			= 80,
++		.sensor_info.mipi_cfg.twidth		= 1920,
++		.sensor_info.mipi_cfg.theight		= 1080,
++		.sensor_info.mipi_cfg.mipi_mode		= SENSOR_MIPI_OTHER_MODE,
++		.sensor_info.mipi_cfg.mipi_vcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_hcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3y	= 0,
++		.sensor_info.mipi_cfg.hcrop_diff_en		= 0,
++		.sensor_info.mipi_cfg.line_sync_mode	= 0,
++		.sensor_info.mipi_cfg.work_start_flag	= 0,
++		.sensor_info.mipi_cfg.data_type_en		= 0,
++		.sensor_info.mipi_cfg.data_type_value	= RAW10,
++		.sensor_info.mipi_cfg.del_start		= 0,
++		.sensor_info.mipi_cfg.sensor_frame_mode	= TX_SENSOR_DEFAULT_FRAME_MODE,
++		.sensor_info.mipi_cfg.sensor_fid_mode	= 0,
++		.sensor_info.mipi_cfg.sensor_mode		= TX_SENSOR_DEFAULT_MODE,
++		.sensor_info.mipi_cfg.sensor_csi_fmt		= TX_SENSOR_RAW10,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov4689_init_regs_1920_1080_30fps_mipi,
++	},
++	{
++		.width				= 2592,
++		.height				= 1520,
++		.sensor_info.fps				= 25 << 16 | 1,
++		.sensor_info.total_width			= 2690,
++		.sensor_info.total_height			= 1787,
++		.sensor_info.wdr_en				= 0,
++		.sensor_info.mipi_cfg.clk			= 80,
++		.sensor_info.mipi_cfg.twidth		= 2592,
++		.sensor_info.mipi_cfg.theight		= 1520,
++		.sensor_info.mipi_cfg.mipi_mode		= SENSOR_MIPI_OTHER_MODE,
++		.sensor_info.mipi_cfg.mipi_vcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_hcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3y	= 0,
++		.sensor_info.mipi_cfg.hcrop_diff_en		= 0,
++		.sensor_info.mipi_cfg.line_sync_mode	= 0,
++		.sensor_info.mipi_cfg.work_start_flag	= 0,
++		.sensor_info.mipi_cfg.data_type_en		= 0,
++		.sensor_info.mipi_cfg.data_type_value	= RAW10,
++		.sensor_info.mipi_cfg.del_start		= 0,
++		.sensor_info.mipi_cfg.sensor_frame_mode	= TX_SENSOR_DEFAULT_FRAME_MODE,
++		.sensor_info.mipi_cfg.sensor_fid_mode	= 0,
++		.sensor_info.mipi_cfg.sensor_mode		= TX_SENSOR_DEFAULT_MODE,
++		.sensor_info.mipi_cfg.sensor_csi_fmt		= TX_SENSOR_RAW10,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov4689_init_regs_2592_1520_30fps_mipi,
++	},
++};
++
++
++static int ov4689_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_OV4689_FMTS)
++		return -EINVAL;
++
++	code->code = ov4689_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int ov4689_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct ov4689_format_struct *ovfmt;
++	struct ov4689_win_size *wsize;
++	struct ov4689_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int ov4689_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct ov4689_info *info = to_state(sd);
++	struct ov4689_win_size *wsize = info->win;
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = wsize->width;
++	fmt->height = wsize->height;
++	fmt->code = wsize->mbus_code;
++	fmt->colorspace = wsize->colorspace;
++	*(unsigned int *)fmt->reserved = &wsize->sensor_info; /*reserved[0] reserved[1]*/
++
++//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int ov4689_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov4689_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov4689_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov4689_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int ov4689_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int ov4689_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++//	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov4689_again_lut); i++) {
++		lut = &ov4689_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov4689_again_lut); i++) {
++		lut = &ov4689_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return 0;
++}
++
++static int ov4689_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	struct ov4689_info *info = to_state(sd);
++	char v = 0;
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++
++	ret += ov4689_read(sd, 0x3509, &v);
++
++	reg_val |= v;
++	ret += ov4689_read(sd, 0x3508, &v);
++	reg_val |= v << 8;
++
++
++	*value = regval_to_again(reg_val);
++
++	return ret;
++}
++/*set analog gain db value, map value to sensor register.*/
++static int ov4689_s_again(struct v4l2_subdev *sd, int value)
++{
++	struct ov4689_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int ret = 0;
++	int i;
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(value);
++	}
++
++	ret += ov4689_write(sd, 0x3509, (unsigned char)(reg_value & 0xff));
++	ret += ov4689_write(sd, 0x3508, (unsigned char)((reg_value>>8) & 0xff));
++	if (ret < 0)
++		return ret;
++
++	return ret;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int ov4689_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov4689_s_exp(struct v4l2_subdev *sd, int value)
++{
++	struct ov4689_info *info = to_state(sd);
++	int ret = 0;
++
++	ret += ov4689_write(sd, 0x3502, ((unsigned char)(value & 0xf)) << 4);
++	ret += ov4689_write(sd, 0x3501, (unsigned char)((value >> 4) & 0xff));
++	ret += ov4689_write(sd, 0x3500, (unsigned char)((value >> 12) & 0xf));
++
++	return ret;
++}
++
++static int ov4689_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov4689_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return ov4689_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov4689_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int ov4689_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov4689_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return ov4689_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return ov4689_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return ov4689_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return ov4689_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* ov4689_s_gain turns off auto gain */
++			return ov4689_s_gain(sd, info->gain->val);
++		}
++		return ov4689_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return ov4689_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov4689_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return ov4689_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops ov4689_ctrl_ops = {
++	.s_ctrl = ov4689_s_ctrl,
++	.g_volatile_ctrl = ov4689_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ov4689_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = ov4689_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int ov4689_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	ov4689_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++static int ov4689_core_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov4689_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = ov4689_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++int ov4689_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct ov4689_info *info = to_state(sd);
++	int ret = 0;
++
++	if (enable) {
++		ret = ov4689_write_array(sd, ov4689_stream_on);
++		printk("ov4689 stream on\n");
++
++	}
++	else {
++		ret = ov4689_write_array(sd, ov4689_stream_off);
++		printk("ov4689 stream off\n");
++	}
++	return ret;
++}
++
++
++int ov4689_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct ov4689_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops ov4689_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = ov4689_g_register,
++	.s_register = ov4689_s_register,
++#endif
++	.init = ov4689_core_init,
++};
++
++static const struct v4l2_subdev_video_ops ov4689_video_ops = {
++	.s_stream = ov4689_s_stream,
++	.g_frame_interval	= ov4689_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops ov4689_pad_ops = {
++	//.enum_frame_interval = ov4689_enum_frame_interval,
++	//.num_frame_size = ov4689_enum_frame_size,
++	//.enum_mbus_code = ov4689_enum_mbus_code,
++	.set_fmt = ov4689_set_fmt,
++	.get_fmt = ov4689_get_fmt,
++};
++
++static const struct v4l2_subdev_ops ov4689_ops = {
++	.core = &ov4689_core_ops,
++	.video = &ov4689_video_ops,
++	.pad = &ov4689_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int ov4689_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_fract tpf;
++	struct v4l2_subdev *sd;
++	struct ov4689_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++	unsigned long rate;
++	int mclk_index = -1;
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutp-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutp.pin = gpio;
++		info->ircutp.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutn.pin = gpio;
++		info->ircutn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	v4l2_i2c_subdev_init(sd, client, &ov4689_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++	char id_div[9];
++	char id_mux[9];
++	of_property_read_u32(client->dev.of_node, "ingenic,mclk", &mclk_index);
++	if(mclk_index == 0) {
++		memcpy(id_div, "div_cim0", sizeof(id_div));
++		memcpy(id_mux, "mux_cim0", sizeof(id_mux));
++	} else if(mclk_index == 1) {
++		memcpy(id_div, "div_cim1", sizeof(id_div));
++		memcpy(id_mux, "mux_cim1", sizeof(id_mux));
++	} else if(mclk_index == 2) {
++		memcpy(id_div, "div_cim2", sizeof(id_div));
++		memcpy(id_mux, "mux_cim2", sizeof(id_mux));
++	} else
++		printk("Unkonwn mclk index\n");
++
++
++	info->clk = v4l2_clk_get(&client->dev, id_div);
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++	info->sclka = devm_clk_get(&client->dev, id_mux);
++
++	rate = v4l2_clk_get_rate(info->clk);
++	if (((rate / 1000) % 24000) != 0) {
++		ret = clk_set_parent(info->sclka, clk_get(NULL, "epll"));
++		info->sclka = devm_clk_get(&client->dev, "epll");
++		if (IS_ERR(info->sclka)) {
++			pr_err("get sclka failed\n");
++		} else {
++			rate = clk_get_rate(info->sclka);
++			if (((rate / 1000) % 27000) != 0) {
++				clk_set_rate(info->sclka, 891000000);
++			}
++		}
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++
++	ov4689_reset(sd, 1);
++#if 1
++	/* Make sure it's an ov4689 */
++	ret = ov4689_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an ov4689 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++
++	/*IRCUT ctl 0:off 1:on*/
++	ov4689_ircut(sd, 0);
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 261773, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_EXPOSURE, 0, 1520 - 4, 1, 1000);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->win = &ov4689_win_sizes[1];
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "ov4689 Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int ov4689_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov4689_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id ov4689_id[] = {
++	{ "ov4689", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ov4689_id);
++
++static const struct of_device_id ov4689_of_match[] = {
++	{.compatible = "ovit,ov4689", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov4689_of_match);
++
++
++static struct i2c_driver ov4689_driver = {
++	.driver = {
++		.name	= "ov4689",
++		.of_match_table = of_match_ptr(ov4689_of_match),
++	},
++	.probe		= ov4689_probe,
++	.remove		= ov4689_remove,
++	.id_table	= ov4689_id,
++};
++
++module_i2c_driver(ov4689_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for OmniVision ov4689 sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp-v2/ov7251.c b/module_drivers/drivers/media/i2c/ingenic-isp-v2/ov7251.c
+new file mode 100644
+index 000000000..ee083617b
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp-v2/ov7251.c
+@@ -0,0 +1,1534 @@
++/*
++ * A V4L2 driver for OmniVision OV7251 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++#include <linux/clk.h>
++#include <isp-sensor.h>
++
++#define OV7251_CHIP_ID_H	(0x77)
++#define OV7251_CHIP_ID_L	(0x50)
++#define OV7251_REG_END		0xffff
++#define OV7251_REG_DELAY	0xfffe
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct ov7251_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct ov7251_gpio {
++	int pin;
++	int active_level;
++};
++
++struct ov7251_supply {
++	struct regulator *vdd2v8;	/* Digital Core supply */
++	struct regulator *vdd1v8;		/* Digital I/O supply */
++};
++
++struct ov7251_info {
++	struct ov7251_supply supply;
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++	struct clk *sclka;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct ov7251_win_size *win;
++
++	struct ov7251_gpio reset;
++	struct ov7251_gpio ircutp;
++	struct ov7251_gpio ircutn;
++	struct ov7251_gpio pwr;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++struct again_lut ov7251_again_lut[] = {
++
++	{0x80, 0},
++	{0x88, 5731},
++	{0x90, 11136},
++	{0x98, 16248},
++	{0xa0, 21097},
++	{0xa8, 25710},
++	{0xb0, 30109},
++	{0xb8, 34312},
++	{0xc0, 38336},
++	{0xc8, 42195},
++	{0xd0, 45904},
++	{0xd8, 49472},
++	{0xe0, 52910},
++	{0xe8, 56228},
++	{0xf0, 59433},
++	{0xf8, 62534},
++	{0x178, 65536},
++	{0x17c, 68445},
++	{0x180, 71267},
++	{0x184, 74008},
++	{0x188, 76672},
++	{0x18c, 79262},
++	{0x190, 81784},
++	{0x194, 84240},
++	{0x198, 86633},
++	{0x19c, 88968},
++	{0x1a0, 91246},
++	{0x1a4, 93471},
++	{0x1a8, 95645},
++	{0x1ac, 97770},
++	{0x1b0, 99848},
++	{0x1b4, 101881},
++	{0x1b8, 103872},
++	{0x1bc, 105821},
++	{0x1c0, 107731},
++	{0x1c4, 109604},
++	{0x1c8, 111440},
++	{0x1cc, 113241},
++	{0x1d0, 115008},
++	{0x1d4, 116743},
++	{0x1d8, 118446},
++	{0x1dc, 120120},
++	{0x1e0, 121764},
++	{0x1e4, 123380},
++	{0x1e8, 124969},
++	{0x1ec, 126532},
++	{0x1f0, 128070},
++	{0x1f4, 129583},
++	{0x374, 131072},
++	{0x376, 132537},
++	{0x378, 133981},
++	{0x37a, 135403},
++	{0x37c, 136803},
++	{0x37e, 138184},
++	{0x380, 139544},
++	{0x382, 140885},
++	{0x384, 142208},
++	{0x386, 143512},
++	{0x388, 144798},
++	{0x38a, 146067},
++	{0x38c, 147320},
++	{0x38e, 148556},
++	{0x390, 149776},
++	{0x392, 150980},
++	{0x394, 152169},
++	{0x396, 153344},
++	{0x398, 154504},
++	{0x39a, 155650},
++	{0x39c, 156782},
++	{0x39e, 157901},
++	{0x3a0, 159007},
++	{0x3a2, 160100},
++	{0x3a4, 161181},
++	{0x3a6, 162249},
++	{0x3a8, 163306},
++	{0x3aa, 164350},
++	{0x3ac, 165384},
++	{0x3ae, 166406},
++	{0x3b0, 167417},
++	{0x3b2, 168418},
++	{0x3b4, 169408},
++	{0x3b6, 170387},
++	{0x3b8, 171357},
++	{0x3ba, 172317},
++	{0x3bc, 173267},
++	{0x3be, 174208},
++	{0x3c0, 175140},
++	{0x3c2, 176062},
++	{0x3c4, 176976},
++	{0x3c6, 177880},
++	{0x3c8, 178777},
++	{0x3ca, 179664},
++	{0x3cc, 180544},
++	{0x3ce, 181415},
++	{0x3d0, 182279},
++	{0x3d2, 183134},
++	{0x3d4, 183982},
++	{0x3d6, 184823},
++	{0x3d8, 185656},
++	{0x3da, 186482},
++	{0x3dc, 187300},
++	{0x3de, 188112},
++	{0x3e0, 188916},
++	{0x3e2, 189714},
++	{0x3e4, 190505},
++	{0x3e6, 191290},
++	{0x3e8, 192068},
++	{0x3ea, 192840},
++	{0x3ec, 193606},
++	{0x3ee, 194365},
++	{0x3f0, 195119},
++	{0x3f2, 195866},
++	{0x778, 196608},
++	{0x779, 197343},
++	{0x77a, 198073},
++	{0x77b, 198798},
++	{0x77c, 199517},
++	{0x77d, 200230},
++	{0x77e, 200939},
++	{0x77f, 201642},
++	{0x780, 202339},
++	{0x781, 203032},
++	{0x782, 203720},
++	{0x783, 204402},
++	{0x784, 205080},
++	{0x785, 205753},
++	{0x786, 206421},
++	{0x787, 207085},
++	{0x788, 207744},
++	{0x789, 208398},
++	{0x78a, 209048},
++	{0x78b, 209693},
++	{0x78c, 210334},
++	{0x78d, 210971},
++	{0x78e, 211603},
++	{0x78f, 212232},
++	{0x790, 212856},
++	{0x791, 213476},
++	{0x792, 214092},
++	{0x793, 214704},
++	{0x794, 215312},
++	{0x795, 215916},
++	{0x796, 216516},
++	{0x797, 217113},
++	{0x798, 217705},
++	{0x799, 218294},
++	{0x79a, 218880},
++	{0x79b, 219462},
++	{0x79c, 220040},
++	{0x79d, 220615},
++	{0x79e, 221186},
++	{0x79f, 221754},
++	{0x7a0, 222318},
++	{0x7a1, 222880},
++	{0x7a2, 223437},
++	{0x7a3, 223992},
++	{0x7a4, 224543},
++	{0x7a5, 225091},
++	{0x7a6, 225636},
++	{0x7a7, 226178},
++	{0x7a8, 226717},
++	{0x7a9, 227253},
++	{0x7aa, 227785},
++	{0x7ab, 228315},
++	{0x7ac, 228842},
++	{0x7ad, 229365},
++	{0x7ae, 229886},
++	{0x7af, 230404},
++	{0x7b0, 230920},
++	{0x7b1, 231432},
++	{0x7b2, 231942},
++	{0x7b3, 232449},
++	{0x7b4, 232953},
++	{0x7b5, 233455},
++	{0x7b6, 233954},
++	{0x7b7, 234450},
++	{0x7b8, 234944},
++	{0x7b9, 235435},
++	{0x7ba, 235923},
++	{0x7bb, 236410},
++	{0x7bc, 236893},
++	{0x7bd, 237374},
++	{0x7be, 237853},
++	{0x7bf, 238329},
++	{0x7c0, 238803},
++	{0x7c1, 239275},
++	{0x7c2, 239744},
++	{0x7c3, 240211},
++	{0x7c4, 240676},
++	{0x7c5, 241138},
++	{0x7c6, 241598},
++	{0x7c7, 242056},
++	{0x7c8, 242512},
++	{0x7c9, 242965},
++	{0x7ca, 243416},
++	{0x7cb, 243865},
++	{0x7cc, 244313},
++	{0x7cd, 244757},
++	{0x7ce, 245200},
++	{0x7cf, 245641},
++	{0x7d0, 246080},
++	{0x7d1, 246517},
++	{0x7d2, 246951},
++	{0x7d3, 247384},
++	{0x7d4, 247815},
++	{0x7d5, 248243},
++	{0x7d6, 248670},
++	{0x7d7, 249095},
++	{0x7d8, 249518},
++	{0x7d9, 249939},
++	{0x7da, 250359},
++	{0x7db, 250776},
++	{0x7dc, 251192},
++	{0x7dd, 251606},
++	{0x7de, 252018},
++	{0x7df, 252428},
++	{0x7e0, 252836},
++	{0x7e1, 253243},
++	{0x7e2, 253648},
++	{0x7e3, 254051},
++	{0x7e4, 254452},
++	{0x7e5, 254852},
++	{0x7e6, 255250},
++	{0x7e7, 255647},
++	{0x7e8, 256041},
++	{0x7e9, 256435},
++	{0x7ea, 256826},
++	{0x7eb, 257216},
++	{0x7ec, 257604},
++	{0x7ed, 257991},
++	{0x7ee, 258376},
++	{0x7ef, 258760},
++	{0x7f0, 259142},
++	{0x7f1, 259522},
++	{0x7f2, 259901},
++	{0x7f3, 260279},
++	{0x7f4, 260655},
++	{0x7f5, 261029},
++	{0x7f6, 261402},
++	{0x7f7, 261773},
++};
++
++static inline struct ov7251_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct ov7251_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct ov7251_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++
++
++static struct regval_list ov7251_init_regs_640_480_mipi[] = {
++	{0x3501, 0x00},
++	{0x3502, 0x80},
++	{0x3674, 0xef}, 
++	{0x373c, 0x8e},
++	{0x37a8, 0x01},
++	{0x37a9, 0xc0},
++	{0x3803, 0x04},
++	{0x3807, 0xeb},
++	{0x3808, 0x02},
++	{0x3809, 0x80},
++	{0x380a, 0x01},
++	{0x380b, 0xe0},
++	{0x380c, 0x05},
++	{0x380d, 0x70},
++	{0x380e, 0x02},
++	{0x380f, 0x40},
++	{0x3813, 0x05}, 
++	{0x3814, 0x11},
++	{0x3815, 0x11},
++	{0x3820, 0x40},
++	{0x3821, 0x00},
++	{0x3c0c, 0x01},
++	{0x3c0d, 0xd0},
++	{0x3c0e, 0x02},
++	{0x3c0f, 0x0a},
++	{0x4001, 0x42},
++	{0x4004, 0x04},
++	{0x0100, 0x01},
++	{OV7251_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list ov7251_init_regs_320_240_mipi[] = {
++	{0x3501, 0x00},
++	{0x3502, 0x90},
++	{0x3674, 0xef},
++	{0x373c, 0xe8},
++	{0x37a8, 0x02},
++	{0x37a9, 0x14},
++	{0x3803, 0x00},
++	{0x3807, 0xef},
++	{0x3808, 0x01},
++	{0x3809, 0x40},
++	{0x380a, 0x00},
++	{0x380b, 0xf0},
++	{0x380c, 0x05},
++	{0x380d, 0x70},
++	{0x380e, 0x02},
++	{0x380f, 0x40},
++	{0x3813, 0x05},
++	{0x3814, 0x31},
++	{0x3815, 0x31},
++	{0x3820, 0x42},
++	{0x3821, 0x01},
++	{0x3c0e, 0x01},
++	{0x3c0f, 0x30},
++	{0x4001, 0x40},
++	{0x4004, 0x02},
++	{0x0100, 0x01},
++	{OV7251_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list ov7251_init_regs_160_120_mipi[] = {
++	{0x3501, 0x02}, //
++	{0x3502, 0x80}, //expo
++//	{0x3509, 0x18},
++//	{0x3504, 0x03},
++//	{0x3505, 0x00}, //mannual again
++	{0x3674, 0xff}, //
++	{0x373c, 0xe8}, //
++	{0x37a8, 0x02}, //
++	{0x37a9, 0x14}, //
++	{0x3803, 0x00}, //
++	{0x3807, 0xef}, //
++	{0x3808, 0x00}, //01
++	{0x3809, 0xa0}, //40
++	{0x380a, 0x00}, //
++	{0x380b, 0x78}, //f0
++	{0x380c, 0x03}, //
++	{0x380d, 0xa0}, //HTS
++	{0x380e, 0x02}, //
++	{0x380f, 0x0a}, //VTS
++	{0x3811, 0x02},
++	{0x3813, 0x03}, //05
++	{0x3814, 0x44}, //31
++	{0x3815, 0x44}, //31
++	{0x3820, 0x42}, //
++	{0x3821, 0x01}, //
++	{0x3c0c, 0x01}, //
++	{0x3c0d, 0x82}, //
++	{0x3c0e, 0x01}, //
++	{0x3c0f, 0x30}, //
++	{0x4001, 0x40}, //
++	{0x4004, 0x02}, //
++	{0x0100, 0x01}, //
++	{OV7251_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list ov7251_common_init_regs_mipi[] = {
++	{0x0103, 0x01},
++	{0x0100, 0x00},
++	{0x3005, 0x00},
++	{0x3012, 0xc0},
++	{0x3013, 0xd2},
++	{0x3014, 0x04},
++	{0x3016, 0x10},
++	{0x3017, 0x00},
++	{0x3018, 0x00},
++	{0x301a, 0x00},
++	{0x301b, 0x00},
++	{0x301c, 0x00},
++	{0x3023, 0x05},
++	{0x3037, 0xf0},
++	{0x3098, 0x04},
++	{0x3099, 0x28},
++	{0x309a, 0x05},
++	{0x309b, 0x04},
++	{0x30b0, 0x0a},
++	{0x30b1, 0x01},
++	{0x30b3, 0x64},
++	{0x30b4, 0x03},
++	{0x30b5, 0x05},
++	{0x3106, 0xda},
++	{0x3500, 0x00},
++	{0x3503, 0x07},
++	{0x3509, 0x10},
++	{0x350b, 0x10},
++	{0x3600, 0x1c},
++	{0x3602, 0x62},
++	{0x3620, 0xb7},
++	{0x3622, 0x04},
++	{0x3626, 0x21},
++	{0x3627, 0x30},
++	{0x3630, 0x44},
++	{0x3631, 0x35},
++	{0x3634, 0x60},
++	{0x3636, 0x00},
++	{0x3662, 0x01},
++	{0x3663, 0x70},
++	{0x3664, 0xf0},
++	{0x3666, 0x0a},
++	{0x3669, 0x1a},
++	{0x366a, 0x00},
++	{0x366b, 0x50},
++	{0x3673, 0x01},
++	{0x3675, 0x03},
++	{0x3705, 0x41},
++	{0x3709, 0x40},
++	{0x3742, 0x00},
++	{0x3757, 0xb3},
++	{0x3788, 0x00},
++	{0x3800, 0x00},
++	{0x3801, 0x04},
++	{0x3802, 0x00},
++	{0x3804, 0x02},
++	{0x3805, 0x8b},
++	{0x3806, 0x01},
++	{0x3810, 0x00},
++	{0x3811, 0x04},
++	{0x3812, 0x00},
++	{0x382f, 0x0e},
++	{0x3832, 0x00},
++	{0x3833, 0x05},
++	{0x3834, 0x00},
++	{0x3835, 0x0c},
++	{0x3837, 0x00},
++	{0x3b80, 0x00},
++	{0x3b81, 0xa5},
++	{0x3b82, 0x10},
++	{0x3b83, 0x00},
++	{0x3b84, 0x08},
++	{0x3b85, 0x00},
++	{0x3b86, 0x01},
++	{0x3b87, 0x00},
++	{0x3b88, 0x00},
++	{0x3b89, 0x00},
++	{0x3b8a, 0x00},
++	{0x3b8b, 0x05},
++	{0x3b8c, 0x00},
++	{0x3b8d, 0x00},
++	{0x3b8e, 0x00},
++	{0x3b8f, 0x1a},
++	{0x3b94, 0x05},
++	{0x3b95, 0xf2},
++	{0x3b96, 0x40},
++	{0x3c00, 0x89},
++	{0x3c01, 0x63},
++	{0x3c02, 0x01},
++	{0x3c03, 0x00},
++	{0x3c04, 0x00},
++	{0x3c05, 0x03},
++	{0x3c06, 0x00},
++	{0x3c07, 0x06},
++	{0x4005, 0x00},
++	{0x404e, 0x01},
++	{0x4300, 0xff},
++	{0x4301, 0x00},
++	{0x4501, 0x48},
++	{0x4600, 0x00},
++	{0x4601, 0x4e},
++	{0x4801, 0x0f},
++	{0x4806, 0x0f},
++	{0x4819, 0xaa},
++	{0x4823, 0x3e},
++	{0x4837, 0x19},
++	{0x4a0d, 0x00},
++	{0x4a47, 0x7f},
++	{0x4a49, 0xf0},
++	{0x4a4b, 0x30},
++	{0x5000, 0x85},
++	{0x5001, 0x80},
++	{OV7251_REG_END, 0x00},	/* END MARKER */
++};
++
++/*
++ * the part of driver was fixed.
++ */
++
++static struct regval_list ov7251_stream_on_mipi[] = {
++	{0x0100, 0x01},
++	{OV7251_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list ov7251_stream_off_mipi[] = {
++	{0x0100, 0x00},
++	{OV7251_REG_END, 0x00},	/* END MARKER */
++};
++
++static int ov7251_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct ov7251_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret = 0;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ov7251_write(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char value)
++{
++	struct ov7251_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3] = {(reg>>8)&0xff, reg&0xff, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 3,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ov7251_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != OV7251_REG_END) {
++		if (vals->reg_num == OV7251_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ov7251_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++/*
++ * Write a list of register settings; ff/ff stops the process.
++ */
++static int ov7251_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != OV7251_REG_END) {
++		if (vals->reg_num == OV7251_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ov7251_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int ov7251_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov7251_info *info = to_state(sd);
++	printk("%s >>>>>>>>>>> %s >>>>\n",__func__,__func__);
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(20);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(20);
++	}
++	return 0;
++}
++
++static int ov7251_pwr_set(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov7251_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->pwr.pin, info->pwr.active_level);
++	} else {
++		gpio_direction_output(info->pwr.pin, !info->pwr.active_level);
++	}
++	return 0;
++}
++
++static int ov7251_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov7251_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++	} else {
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, !info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++	}
++	return 0;
++}
++
++static int ov7251_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov7251_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = ov7251_write_array(sd, ov7251_common_init_regs_mipi);
++
++	return ret;
++}
++
++
++
++static int ov7251_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v = 0;
++	int ret;
++//while(1)
++	{
++	ret = ov7251_read(sd, 0x300a, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	}
++	if (ret < 0)
++		return ret;
++	if (v != OV7251_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = ov7251_read(sd, 0x300b, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++
++	if (ret < 0)
++		return ret;
++	if (v != OV7251_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	return 0;
++}
++
++
++static struct ov7251_win_size ov7251_win_sizes[] = {
++	/* { */
++	/* 	.sensor_info.mipi_cfg.twidth		= 640, */
++	/* 	.sensor_info.mipi_cfg.theight		= 480, */
++	/* 	.sensor_info.mipi_cfg.mipi_crop_start0x	= 0, */
++	/* 	.sensor_info.mipi_cfg.mipi_crop_start0y	= 0, */
++	/* 	.sensor_info.fps			= 60 << 16 | 1, */
++
++	/* 	.width		= 640, */
++	/* 	.height		= 480, */
++	/* 	.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10, */
++	/* 	.colorspace	= V4L2_COLORSPACE_SRGB, */
++	/* 	.regs 		= ov7251_init_regs_640_480_mipi, */
++	/* }, */
++	/* { */
++	/* 	.sensor_info.mipi_cfg.twidth		= 320, */
++	/* 	.sensor_info.mipi_cfg.theight		= 240, */
++	/* 	.sensor_info.mipi_cfg.mipi_crop_start0x	= 0, */
++	/* 	.sensor_info.mipi_cfg.mipi_crop_start0y	= 0, */
++	/* 	.sensor_info.fps			= 60 << 16 | 1, */
++
++	/* 	.width		= 320, */
++	/* 	.height		= 240, */
++	/* 	.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10, */
++	/* 	.colorspace	= V4L2_COLORSPACE_SRGB, */
++	/* 	.regs 		= ov7251_init_regs_320_240_mipi, */
++	/* }, */
++	/* { */
++	/* 	.sensor_info.mipi_cfg.twidth		= 160, */
++	/* 	.sensor_info.mipi_cfg.theight		= 120, */
++	/* 	.sensor_info.mipi_cfg.mipi_crop_start0x	= 0, */
++	/* 	.sensor_info.mipi_cfg.mipi_crop_start0y	= 0, */
++	/* 	.sensor_info.fps			= 75 << 16 | 1, */
++
++	/* 	.width		= 160, */
++	/* 	.height		= 120, */
++	/* 	.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10, */
++	/* 	.colorspace	= V4L2_COLORSPACE_SRGB, */
++	/* 	.regs 		= ov7251_init_regs_160_120_mipi, */
++	/* }, */
++	{
++		.width				= 640,
++		.height				= 480,
++		.sensor_info.fps				= 60 << 16 | 1,
++//		.sensor_info.total_width			= 656,
++//		.sensor_info.total_height			= 496,
++		.sensor_info.wdr_en				= 0,
++		.sensor_info.mipi_cfg.clk			= 600,
++		.sensor_info.mipi_cfg.twidth		= 640,
++		.sensor_info.mipi_cfg.theight		= 480,
++		.sensor_info.mipi_cfg.mipi_mode		= SENSOR_MIPI_OTHER_MODE,
++		.sensor_info.mipi_cfg.mipi_vcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_hcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3y	= 0,
++		.sensor_info.mipi_cfg.hcrop_diff_en		= 0,
++		.sensor_info.mipi_cfg.line_sync_mode	= 0,
++		.sensor_info.mipi_cfg.work_start_flag	= 0,
++		.sensor_info.mipi_cfg.data_type_en		= 0,
++		.sensor_info.mipi_cfg.data_type_value	= RAW10,
++		.sensor_info.mipi_cfg.del_start		= 0,
++		.sensor_info.mipi_cfg.sensor_frame_mode	= TX_SENSOR_DEFAULT_FRAME_MODE,
++		.sensor_info.mipi_cfg.sensor_fid_mode	= 0,
++		.sensor_info.mipi_cfg.sensor_mode		= TX_SENSOR_DEFAULT_MODE,
++		.sensor_info.mipi_cfg.sensor_csi_fmt		= TX_SENSOR_RAW10,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov7251_init_regs_640_480_mipi,
++	},
++	{
++		.width				= 320,
++		.height				= 240,
++		.sensor_info.fps				= 60 << 16 | 1,
++//		.sensor_info.total_width			= 656,
++//		.sensor_info.total_height			= 496,
++		.sensor_info.wdr_en				= 0,
++		.sensor_info.mipi_cfg.clk			= 600,
++		.sensor_info.mipi_cfg.twidth		= 320,
++		.sensor_info.mipi_cfg.theight		= 240,
++		.sensor_info.mipi_cfg.mipi_mode		= SENSOR_MIPI_OTHER_MODE,
++		.sensor_info.mipi_cfg.mipi_vcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_hcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3y	= 0,
++		.sensor_info.mipi_cfg.hcrop_diff_en		= 0,
++		.sensor_info.mipi_cfg.line_sync_mode	= 0,
++		.sensor_info.mipi_cfg.work_start_flag	= 0,
++		.sensor_info.mipi_cfg.data_type_en		= 0,
++		.sensor_info.mipi_cfg.data_type_value	= RAW10,
++		.sensor_info.mipi_cfg.del_start		= 0,
++		.sensor_info.mipi_cfg.sensor_frame_mode	= TX_SENSOR_DEFAULT_FRAME_MODE,
++		.sensor_info.mipi_cfg.sensor_fid_mode	= 0,
++		.sensor_info.mipi_cfg.sensor_mode		= TX_SENSOR_DEFAULT_MODE,
++		.sensor_info.mipi_cfg.sensor_csi_fmt		= TX_SENSOR_RAW10,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov7251_init_regs_320_240_mipi,
++	},
++	{
++		.width				= 160,
++		.height				= 120,
++		.sensor_info.fps				= 100 << 16 | 1,
++	//	.sensor_info.total_width			= 656,
++	//	.sensor_info.total_height			= 496,
++		.sensor_info.wdr_en				= 0,
++		.sensor_info.mipi_cfg.clk			= 600,
++		.sensor_info.mipi_cfg.twidth		= 160,
++		.sensor_info.mipi_cfg.theight		= 120,
++		.sensor_info.mipi_cfg.mipi_mode		= SENSOR_MIPI_OTHER_MODE,
++		.sensor_info.mipi_cfg.mipi_vcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_hcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3y	= 0,
++		.sensor_info.mipi_cfg.hcrop_diff_en		= 0,
++		.sensor_info.mipi_cfg.line_sync_mode	= 0,
++		.sensor_info.mipi_cfg.work_start_flag	= 0,
++		.sensor_info.mipi_cfg.data_type_en		= 0,
++		.sensor_info.mipi_cfg.data_type_value	= RAW10,
++		.sensor_info.mipi_cfg.del_start		= 0,
++		.sensor_info.mipi_cfg.sensor_frame_mode	= TX_SENSOR_DEFAULT_FRAME_MODE,
++		.sensor_info.mipi_cfg.sensor_fid_mode	= 0,
++		.sensor_info.mipi_cfg.sensor_mode		= TX_SENSOR_DEFAULT_MODE,
++		.sensor_info.mipi_cfg.sensor_csi_fmt		= TX_SENSOR_RAW10,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov7251_init_regs_160_120_mipi,
++	},
++};
++
++static const struct ov7251_win_size *ov7251_select_win(u32 *width, u32 *height)
++{
++	int i, default_size = ARRAY_SIZE(ov7251_win_sizes) - 1;
++
++	for (i = 0; i < ARRAY_SIZE(ov7251_win_sizes); i++) {
++		if ((*width >= ov7251_win_sizes[i].width) &&
++				(*height >= ov7251_win_sizes[i].height)) {
++			*width = ov7251_win_sizes[i].width;
++			*height = ov7251_win_sizes[i].height;
++			return &ov7251_win_sizes[i];
++		}
++	}
++
++	*width = ov7251_win_sizes[default_size].width;
++	*height = ov7251_win_sizes[default_size].height;
++	return &ov7251_win_sizes[default_size];
++}
++
++
++static int ov7251_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_OV7251_FMTS)
++		return -EINVAL;
++
++	code->code = ov7251_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int ov7251_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct ov7251_format_struct *ovfmt;
++	struct ov7251_win_size *wsize;
++	struct ov7251_info *info = to_state(sd);
++	int ret;
++
++	info->win = ov7251_select_win(&format->format.width, &format->format.height);
++
++	return 0;
++}
++
++static int ov7251_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct ov7251_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	*(unsigned int *)fmt->reserved = &info->win->sensor_info;
++
++
++//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int ov7251_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov7251_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov7251_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov7251_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int ov7251_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int ov7251_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++//	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov7251_again_lut); i++) {
++		lut = &ov7251_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov7251_again_lut); i++) {
++		lut = &ov7251_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++}
++
++static int ov7251_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	/*
++	struct ov7251_info *info = to_state(sd);
++	char v = 0;
++	unsigned int reg_val = 0;
++
++
++	ret += ov7251_read(sd, 0x3509, &v);
++
++	reg_val |= v;
++	ret += ov7251_read(sd, 0x3508, &v);
++	reg_val |= v << 8;
++
++
++	*value = regval_to_again(reg_val);
++	*/
++
++	return ret;
++}
++/*set analog gain db value, map value to sensor register.*/
++static int ov7251_s_again(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++#if 0
++	struct ov7251_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int i;
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(value);
++	}
++
++	ret += ov7251_write(sd, 0x3509, (unsigned char)(reg_value & 0xff));
++	ret += ov7251_write(sd, 0x3508, (unsigned char)((reg_value>>8) & 0xff));
++	if (ret < 0)
++		return ret;
++
++#endif
++	return ret;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int ov7251_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov7251_s_exp(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++	/*
++	struct ov7251_info *info = to_state(sd);
++
++	ret += ov7251_write(sd, 0x3502, ((unsigned char)(value & 0xf)) << 4);
++	ret += ov7251_write(sd, 0x3501, (unsigned char)((value >> 4) & 0xff));
++	ret += ov7251_write(sd, 0x3500, (unsigned char)((value >> 12) & 0xf));
++
++	*/
++	return ret;
++}
++
++static int ov7251_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov7251_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return ov7251_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov7251_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int ov7251_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov7251_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return ov7251_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return ov7251_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return ov7251_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return ov7251_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* ov7251_s_gain turns off auto gain */
++			return ov7251_s_gain(sd, info->gain->val);
++		}
++		return ov7251_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return ov7251_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov7251_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return ov7251_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops ov7251_ctrl_ops = {
++	.s_ctrl = ov7251_s_ctrl,
++	.g_volatile_ctrl = ov7251_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ov7251_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = ov7251_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int ov7251_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	ov7251_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int ov7251_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct ov7251_info *info = to_state(sd);
++	int ret = 0;
++
++	if (enable) {
++		ov7251_write_array(sd, info->win->regs);
++		ov7251_s_again(sd, 100000);
++		ret = ov7251_write_array(sd, ov7251_stream_on_mipi);
++		printk("ov7251 stream on\n");
++
++	}
++	else {
++		ret = ov7251_write_array(sd, ov7251_stream_off_mipi);
++		printk("ov7251 stream off\n");
++	}
++	return ret;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops ov7251_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = ov7251_g_register,
++	.s_register = ov7251_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops ov7251_video_ops = {
++	.s_stream = ov7251_s_stream,
++};
++
++static const struct v4l2_subdev_pad_ops ov7251_pad_ops = {
++	//.enum_frame_interval = ov7251_enum_frame_interval,
++	//.num_frame_size = ov7251_enum_frame_size,
++	//.enum_mbus_code = ov7251_enum_mbus_code,
++	.set_fmt = ov7251_set_fmt,
++	.get_fmt = ov7251_get_fmt,
++};
++
++static const struct v4l2_subdev_ops ov7251_ops = {
++	.core = &ov7251_core_ops,
++	.video = &ov7251_video_ops,
++	.pad = &ov7251_pad_ops,
++};
++
++#if 0
++int ov7251_regulator_get_supply(struct device *dev)
++{
++	int ret;
++	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov7251_info *info = to_state(sd);
++
++	info->supply.vdd2v8 = devm_regulator_get_optional(dev, "vdd2v8");
++	info->supply.vdd1v8 = devm_regulator_get_optional(dev, "vdd1v8");
++
++	if (IS_ERR(info->supply.vdd2v8)) {
++		if (PTR_ERR(info->supply.vdd2v8) == -EPROBE_DEFER)
++			return -EPROBE_DEFER;
++		printk("No vdd2v8 regulator found\n");
++	}
++
++	if (IS_ERR(info->supply.vdd1v8)) {
++		if (PTR_ERR(info->supply.vdd1v8) == -EPROBE_DEFER)
++			return -EPROBE_DEFER;
++		printk("No vdd1v8 regulator found\n");
++	}
++	if (!IS_ERR(info->supply.vdd2v8)) {
++		ret = regulator_enable(info->supply.vdd2v8);
++		if (ret)
++			dev_err(&client->dev, "ov7251 vdd2v8 supply enable failed\n");
++	}
++	if (!IS_ERR(info->supply.vdd1v8)) {
++		ret = regulator_enable(info->supply.vdd1v8);
++		if (ret)
++			dev_err(&client->dev, "ov7251 vdd1v8 supply enable failed\n");
++	}
++
++	return 0;
++}
++#endif
++/* ----------------------------------------------------------------------- */
++
++static int ov7251_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_fract tpf;
++	struct v4l2_subdev *sd;
++	struct ov7251_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++	int tmp;
++	int mclk_index;
++	unsigned long rate;
++	dev_info(&client->dev, "ov7251 probing\n");
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutp-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutp.pin = gpio;
++		info->ircutp.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutn.pin = gpio;
++		info->ircutn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,pwr-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->pwr.pin = gpio;
++		info->pwr.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	v4l2_i2c_subdev_init(sd, client, &ov7251_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/* ret = ov7251_regulator_get_supply(&client->dev); */
++	/* if (ret) */
++	/* 	dev_err(&client->dev, "get supply failed!\n"); */
++
++	*(volatile unsigned int *)(0xb0010100) = 1;	// set gpio a work at 1.8v
++	ov7251_pwr_set(sd,1);
++	/*clk*/
++	char id_div[9];
++	char id_mux[9];
++	printk("%s:%d\n", __func__, __LINE__);
++	of_property_read_u32(client->dev.of_node, "ingenic,mclk", &mclk_index);
++	if(mclk_index == 0) {
++		memcpy(id_div, "div_cim0", sizeof(id_div));
++		memcpy(id_mux, "mux_cim0", sizeof(id_mux));
++	} else if(mclk_index == 1) {
++		memcpy(id_div, "div_cim1", sizeof(id_div));
++		memcpy(id_mux, "mux_cim1", sizeof(id_mux));
++	} else if(mclk_index == 2) {
++		memcpy(id_div, "div_cim2", sizeof(id_div));
++		memcpy(id_mux, "mux_cim2", sizeof(id_mux));
++	} else
++		printk("Unkonwn mclk index\n");
++
++
++	info->clk = v4l2_clk_get(&client->dev, id_div);
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++	info->sclka = devm_clk_get(&client->dev, id_mux);
++
++	printk("sclka is %s\n", info->sclka?"NOT NULL":"NULL");
++	rate = v4l2_clk_get_rate(info->clk);
++	if (((rate / 1000) % 24000) != 0) {
++		ret = clk_set_parent(info->sclka, clk_get(NULL, "epll"));
++		info->sclka = devm_clk_get(&client->dev, "epll");
++		if (IS_ERR(info->sclka)) {
++			pr_err("get sclka failed\n");
++		} else {
++			rate = clk_get_rate(info->sclka);
++			if (((rate / 1000) % 24000) != 0) {
++				clk_set_rate(info->sclka, 120000000);
++			}
++		}
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++	ov7251_reset(sd, 1);
++#if 1
++	/* Make sure it's an ov7251 */
++	ret = ov7251_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an ov7251 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &ov7251_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &ov7251_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &ov7251_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &ov7251_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7251_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &ov7251_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 261773, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7251_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1520 - 4, 1, 1000);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	ov7251_init(sd, 1);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "ov7251 Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int ov7251_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov7251_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id ov7251_id[] = {
++	{ "ov7251", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ov7251_id);
++
++static const struct of_device_id ov7251_of_match[] = {
++	{.compatible = "ovti,ov7251", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov2640_of_match);
++
++int ov7251_suspend(struct device *dev)
++{
++	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov7251_info *info = to_state(sd);
++	int ret;
++
++	/* if (!IS_ERR(info->supply.vdd2v8)) { */
++	/* 	ret = regulator_disable(info->supply.vdd2v8); */
++	/* 	if (ret) { */
++	/* 		dev_err(dev, "ov7251 vdd2v8 supply disable failed\n"); */
++	/* 		return ret; */
++	/* 	} */
++	/* } */
++	/* if (!IS_ERR(info->supply.vdd1v8)) { */
++	/* 	ret = regulator_disable(info->supply.vdd1v8); */
++	/* 	if (ret) { */
++	/* 		dev_err(dev, "ov7251 vdd1v8 supply disable failed\n"); */
++	/* 		return ret; */
++	/* 	} */
++	/* } */
++
++	v4l2_clk_disable(info->clk);
++	return 0;
++}
++
++int ov7251_resume(struct device *dev)
++{
++	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov7251_info *info = to_state(sd);
++	int ret;
++
++	/* if (!IS_ERR(info->supply.vdd2v8)) { */
++	/* 	ret = regulator_enable(info->supply.vdd2v8); */
++	/* 	if (ret) { */
++	/* 		dev_err(dev, "ov7251 vdd2v8 supply enable failed\n"); */
++	/* 	} */
++	/* } */
++	/* if (!IS_ERR(info->supply.vdd1v8)) { */
++	/* 	ret = regulator_enable(info->supply.vdd1v8); */
++	/* 	if (ret) { */
++	/* 		dev_err(dev, "ov7251 vdd1v8 supply enable failed\n"); */
++	/* 	} */
++	/* } */
++
++	v4l2_clk_enable(info->clk);
++	ov7251_reset(sd, 1);
++	ov7251_init(sd, 1);
++	return 0;
++}
++
++const struct dev_pm_ops ov7251_pm =
++{
++	.suspend = ov7251_suspend,
++	.resume = ov7251_resume,
++};
++
++
++
++static struct i2c_driver ov7251_driver = {
++	.driver = {
++		.name	= "ov7251",
++		.of_match_table = of_match_ptr(ov7251_of_match),
++		.pm	= &ov7251_pm,
++	},
++	.probe		= ov7251_probe,
++	.remove		= ov7251_remove,
++	.id_table	= ov7251_id,
++};
++
++module_i2c_driver(ov7251_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for OmniVision ov7251 sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp-v2/sc230ai.c b/module_drivers/drivers/media/i2c/ingenic-isp-v2/sc230ai.c
+new file mode 100644
+index 000000000..a63de3007
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp-v2/sc230ai.c
+@@ -0,0 +1,1972 @@
++/*
++ * A V4L2 driver for OmniVision OV2735a cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++#include <linux/clk.h>
++#include <isp-sensor.h>
++
++
++#define SC230AI_CHIP_ID_H	(0xcb)
++#define SC230AI_CHIP_ID_L	(0x34)
++#define SC230AI_REG_END		0xff
++#define SC230AI_REG_DELAY	0x00
++#define SC230AI_PAGE_REG	    0xfd
++
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct sc230ai_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct sc230ai_gpio {
++	int pin;
++	int active_level;
++};
++
++struct sc230ai_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++	struct v4l2_ctrl *again_short;
++
++	struct v4l2_clk *clk;
++	struct clk *sclka;
++
++	struct v4l2_ctrl *exposure;
++	struct v4l2_ctrl *exposure_short;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct sc230ai_win_size *win;
++
++	struct sc230ai_gpio xshutdn;
++	struct sc230ai_gpio pwdn;
++	struct sc230ai_gpio efsync;
++	struct sc230ai_gpio led;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int fine_value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++
++struct again_lut sc230ai_again_lut[] = {
++	/*
++	{0x00,	0},
++	{0x01,	65536},
++	{0x40,	115455},
++	{0x48,	180991},
++	{0x49,	246527},
++	{0x4b,	312063},
++	{0x4f,	377599},
++	{0x5f,	443135},
++	*/
++
++	{0x00,0x80,0},
++	{0x00,0x82,1501},
++	{0x00,0x84,2886},
++	{0x00,0x86,4343},
++	{0x00,0x88,5776},
++	{0x00,0x8a,7101},
++	{0x00,0x8c,8494},
++	{0x00,0x8e,9782},
++	{0x00,0x90,11136},
++	{0x00,0x92,12471},
++	{0x00,0x94,13706},
++	{0x00,0x96,15006},
++	{0x00,0x98,16288},
++	{0x00,0x9a,17474},
++	{0x00,0x9c,18724},
++	{0x00,0x9e,19880},
++	{0x00,0xa0,21098},
++	{0x00,0xa2,22300},
++	{0x00,0xa4,23414},
++	{0x00,0xa6,24588},
++	{0x00,0xa8,25747},
++	{0x00,0xaa,26821},
++	{0x00,0xac,27953},
++	{0x00,0xae,29003},
++	{0x00,0xb0,30109},
++	{0x00,0xb2,31203},
++	{0x00,0xb4,32217},
++	{0x00,0xb6,33287},
++	{0x00,0xb8,34345},
++	{0x00,0xba,35326},
++	{0x00,0xbc,36362},
++	{0x00,0xbe,37322},
++	{0x00,0xc0,38336},
++	{0x00,0xc2,39339},
++	{0x00,0xc4,40270},
++	{0x00,0xc6,41253},
++	{0x00,0xc8,42226},
++	{0x00,0xca,43129},
++	{0x00,0xcc,44083},
++	{0x00,0xce,44968},
++	{0x00,0xd0,45904},
++	{0x00,0xd2,46830},
++	{0x00,0xd4,47691},
++	{0x00,0xd6,48600},
++	{0x00,0xd8,49500},
++	{0x00,0xda,50337},
++	{0x00,0xdc,51221},
++	{0x00,0xdf,52042},
++	{0x00,0xe0,52911},
++	{0x00,0xe2,53771},
++	{0x00,0xe4,54571},
++	{0x00,0xe6,55417},
++	{0x00,0xe8,56255},
++	{0x00,0xea,57034},
++	{0x00,0xec,57858},
++	{0x00,0xee,58624},
++	{0x00,0xf0,59434},
++	{0x00,0xf2,60237},
++	{0x00,0xf4,60984},
++	{0x00,0xf6,61775},
++	{0x00,0xf8,62559},
++	{0x00,0xfa,63288},
++	{0x00,0xfc,64059},
++	{0x00,0xfe,64777},
++	{0x01,0x80,65536},
++	{0x01,0x82,66990},
++	{0x01,0x84,68468},
++	{0x01,0x86,69879},
++	{0x01,0x88,71268},
++	{0x01,0x8a,72637},
++	{0x01,0x8c,74030},
++	{0x01,0x8e,75360},
++	{0x01,0x90,76672},
++	{0x01,0x92,77966},
++	{0x01,0x94,79283},
++	{0x01,0x96,80542},
++	{0x01,0x98,81784},
++	{0x01,0x9a,83010},
++	{0x01,0x9c,84260},
++	{0x01,0x9e,85454},
++	{0x01,0xa0,86634},
++	{0x01,0xa2,87799},
++	{0x01,0xa4,88987},
++	{0x01,0xa6,90124},
++	{0x01,0xa8,91247},
++	{0x01,0xaa,92357},
++	{0x01,0xac,93489},
++	{0x01,0xae,94573},
++	{0x01,0xb0,95645},
++	{0x01,0xb2,96705},
++	{0x01,0xb4,97787},
++	{0x01,0xb6,98823},
++	{0x01,0xb8,99848},
++	{0x01,0xba,100862},
++	{0x01,0xbc,101898},
++	{0x01,0xbe,102890},
++	{0x01,0xc0,103872},
++	{0x01,0xc2,104844},
++	{0x01,0xc4,105837},
++	{0x01,0xc6,106789},
++	{0x01,0xc8,107732},
++	{0x01,0xca,108665},
++	{0x01,0xcc,109619},
++	{0x01,0xce,110534},
++	{0x01,0xd0,111440},
++	{0x01,0xd2,112338},
++	{0x01,0xd4,113255},
++	{0x01,0xd6,114136},
++	{0x01,0xd8,115008},
++	{0x40,0x80,115455},
++	{0x40,0x82,116323},
++	{0x40,0x84,117182},
++	{0x40,0x86,118034},
++	{0x40,0x88,118878},
++	{0x40,0x8a,119715},
++	{0x40,0x8c,120544},
++	{0x40,0x8e,121366},
++	{0x40,0x90,122181},
++	{0x40,0x92,122989},
++	{0x40,0x94,123790},
++	{0x40,0x96,124585},
++	{0x40,0x98,125373},
++	{0x40,0x9a,126154},
++	{0x40,0x9c,126929},
++	{0x40,0x9e,127697},
++	{0x40,0xa0,128460},
++	{0x40,0xa2,129216},
++	{0x40,0xa4,129966},
++	{0x40,0xa6,130711},
++	{0x40,0xa8,131449},
++	{0x40,0xaa,132910},
++	{0x40,0xac,134347},
++	{0x40,0xae,135764},
++	{0x40,0xb0,137159},
++	{0x40,0xb2,138534},
++	{0x40,0xb4,139890},
++	{0x40,0xb6,141226},
++	{0x40,0xb8,142544},
++	{0x40,0xba,143843},
++	{0x40,0xbc,145125},
++	{0x40,0xbe,146390},
++	{0x40,0xc0,147638},
++	{0x40,0xc2,148870},
++	{0x40,0xc4,150086},
++	{0x40,0xc6,151286},
++	{0x40,0xc8,152472},
++	{0x40,0xca,153643},
++	{0x40,0xcc,154799},
++	{0x40,0xce,155942},
++	{0x40,0xd0,157071},
++	{0x40,0xd2,158186},
++	{0x40,0xd4,159289},
++	{0x40,0xd6,160379},
++	{0x40,0xd8,161456},
++	{0x40,0xda,162521},
++	{0x40,0xdc,163575},
++	{0x40,0xdf,164616},
++	{0x40,0xe0,165647},
++	{0x40,0xe2,166666},
++	{0x40,0xe4,167675},
++	{0x40,0xe6,168672},
++	{0x40,0xe8,169660},
++	{0x40,0xea,170637},
++	{0x40,0xec,171604},
++	{0x40,0xee,172562},
++	{0x40,0xf0,173509},
++	{0x40,0xf2,174448},
++	{0x40,0xf4,175377},
++	{0x40,0xf6,176297},
++	{0x40,0xf8,177208},
++	{0x40,0xfa,178111},
++	{0x40,0xfc,179005},
++	{0x40,0xfe,179891},
++	{0x48,0x80,180991},
++	{0x48,0x82,181859},
++	{0x48,0x84,182718},
++	{0x48,0x86,183570},
++	{0x48,0x88,184414},
++	{0x48,0x8a,185251},
++	{0x48,0x8c,186080},
++	{0x48,0x8e,186902},
++	{0x48,0x90,187717},
++	{0x48,0x92,188525},
++	{0x48,0x94,189326},
++	{0x48,0x96,190121},
++	{0x48,0x98,190909},
++	{0x48,0x9a,191690},
++	{0x48,0x9c,192465},
++	{0x48,0x9e,193233},
++	{0x48,0xa0,193996},
++	{0x48,0xa2,194752},
++	{0x48,0xa4,195502},
++	{0x48,0xa6,196247},
++	{0x48,0xa8,197718},
++	{0x48,0xaa,199167},
++	{0x48,0xac,200594},
++	{0x48,0xae,202000},
++	{0x48,0xb0,203385},
++	{0x48,0xb2,204751},
++	{0x48,0xb4,206096},
++	{0x48,0xb6,207423},
++	{0x48,0xb8,208732},
++	{0x48,0xba,210022},
++	{0x48,0xbc,211296},
++	{0x48,0xbe,212552},
++	{0x48,0xc0,213792},
++	{0x48,0xc2,215016},
++	{0x48,0xc4,216224},
++	{0x48,0xc6,217417},
++	{0x48,0xc8,218595},
++	{0x48,0xca,219759},
++	{0x48,0xcc,220908},
++	{0x48,0xce,222044},
++	{0x48,0xd0,223166},
++	{0x48,0xd2,224275},
++	{0x48,0xd4,225371},
++	{0x48,0xd6,226455},
++	{0x48,0xd8,227526},
++	{0x48,0xda,228585},
++	{0x48,0xdc,229633},
++	{0x48,0xdf,230669},
++	{0x48,0xe0,231694},
++	{0x48,0xe2,232708},
++	{0x48,0xe4,233711},
++	{0x48,0xe6,234703},
++	{0x48,0xe8,235686},
++	{0x48,0xea,236658},
++	{0x48,0xec,237620},
++	{0x48,0xee,238573},
++	{0x48,0xf0,239516},
++	{0x48,0xf2,240450},
++	{0x48,0xf4,241374},
++	{0x48,0xf6,242290},
++	{0x48,0xf8,243197},
++	{0x48,0xfa,244095},
++	{0x48,0xfc,244985},
++	{0x48,0xfe,245866},
++	{0x49,0x80,246527},
++	{0x49,0x82,247395},
++	{0x49,0x84,248254},
++	{0x49,0x86,249106},
++	{0x49,0x88,249950},
++	{0x49,0x8a,250787},
++	{0x49,0x8c,251616},
++	{0x49,0x8e,252438},
++	{0x49,0x90,253253},
++	{0x49,0x92,254061},
++	{0x49,0x94,254862},
++	{0x49,0x96,255657},
++	{0x49,0x98,256445},
++	{0x49,0x9a,257226},
++	{0x49,0x9c,258001},
++	{0x49,0x9e,258769},
++	{0x49,0xa0,259532},
++	{0x49,0xa2,260288},
++	{0x49,0xa4,261038},
++	{0x49,0xa6,261783},
++	{0x49,0xa8,263254},
++	{0x49,0xaa,264703},
++	{0x49,0xac,266130},
++	{0x49,0xae,267536},
++	{0x49,0xb0,268921},
++	{0x49,0xb2,270287},
++	{0x49,0xb4,271632},
++	{0x49,0xb6,272959},
++	{0x49,0xb8,274268},
++	{0x49,0xba,275558},
++	{0x49,0xbc,276832},
++	{0x49,0xbe,278088},
++	{0x49,0xc0,279328},
++	{0x49,0xc2,280552},
++	{0x49,0xc4,281760},
++	{0x49,0xc6,282953},
++	{0x49,0xc8,284131},
++	{0x49,0xca,285295},
++	{0x49,0xcc,286444},
++	{0x49,0xce,287580},
++	{0x49,0xd0,288702},
++	{0x49,0xd2,289811},
++	{0x49,0xd4,290907},
++	{0x49,0xd6,291991},
++	{0x49,0xd8,293062},
++	{0x49,0xda,294121},
++	{0x49,0xdc,295169},
++	{0x49,0xdf,296205},
++	{0x49,0xe0,297230},
++	{0x49,0xe2,298244},
++	{0x49,0xe4,299247},
++	{0x49,0xe6,300239},
++	{0x49,0xe8,301222},
++	{0x49,0xea,302194},
++	{0x49,0xec,303156},
++	{0x49,0xee,304109},
++	{0x49,0xf0,305052},
++	{0x49,0xf2,305986},
++	{0x49,0xf4,306910},
++	{0x49,0xf6,307826},
++	{0x49,0xf8,308733},
++	{0x49,0xfa,309631},
++	{0x49,0xfc,310521},
++	{0x49,0xfe,311402},
++	{0x4b,0x80,312063},
++	{0x4b,0x82,312931},
++	{0x4b,0x84,313790},
++	{0x4b,0x86,314642},
++	{0x4b,0x88,315486},
++	{0x4b,0x8a,316323},
++	{0x4b,0x8c,317152},
++	{0x4b,0x8e,317974},
++	{0x4b,0x90,318789},
++	{0x4b,0x92,319597},
++	{0x4b,0x94,320398},
++	{0x4b,0x96,321193},
++	{0x4b,0x98,321981},
++	{0x4b,0x9a,322762},
++	{0x4b,0x9c,323537},
++	{0x4b,0x9e,324305},
++	{0x4b,0xa0,325068},
++	{0x4b,0xa2,325824},
++	{0x4b,0xa4,326574},
++	{0x4b,0xa6,327319},
++	{0x4b,0xa8,328057},
++	{0x4b,0xaa,329518},
++	{0x4b,0xac,330955},
++	{0x4b,0xae,332372},
++	{0x4b,0xb0,333767},
++	{0x4b,0xb2,335142},
++	{0x4b,0xb4,336498},
++	{0x4b,0xb6,337834},
++	{0x4b,0xb8,339152},
++	{0x4b,0xba,340451},
++	{0x4b,0xbc,341733},
++	{0x4b,0xbe,342998},
++	{0x4b,0xc0,344246},
++	{0x4b,0xc2,345478},
++	{0x4b,0xc4,346694},
++	{0x4b,0xc6,347894},
++	{0x4b,0xc8,349080},
++	{0x4b,0xca,350251},
++	{0x4b,0xcc,351407},
++	{0x4b,0xce,352550},
++	{0x4b,0xd0,353679},
++	{0x4b,0xd2,354794},
++	{0x4b,0xd4,355897},
++	{0x4b,0xd6,356987},
++	{0x4b,0xd8,358064},
++	{0x4b,0xda,359129},
++	{0x4b,0xdc,360183},
++	{0x4b,0xdf,361224},
++	{0x4b,0xe0,362255},
++	{0x4b,0xe2,363274},
++	{0x4b,0xe4,364283},
++	{0x4b,0xe6,365280},
++	{0x4b,0xe8,366268},
++	{0x4b,0xea,367245},
++	{0x4b,0xec,368212},
++	{0x4b,0xee,369170},
++	{0x4b,0xf0,370117},
++	{0x4b,0xf2,371056},
++	{0x4b,0xf4,371985},
++	{0x4b,0xf6,372905},
++	{0x4b,0xf8,373816},
++	{0x4b,0xfa,374719},
++	{0x4b,0xfc,375613},
++	{0x4b,0xfe,376499},
++	{0x4f,0x80,377599},
++	{0x4f,0x82,378467},
++	{0x4f,0x84,379326},
++	{0x4f,0x86,380178},
++	{0x4f,0x88,381022},
++	{0x4f,0x8a,381859},
++	{0x4f,0x8c,382688},
++	{0x4f,0x8e,383510},
++	{0x4f,0x90,384325},
++	{0x4f,0x92,385133},
++	{0x4f,0x94,385934},
++	{0x4f,0x96,386729},
++	{0x4f,0x98,387517},
++	{0x4f,0x9a,388298},
++	{0x4f,0x9c,389073},
++	{0x4f,0x9e,389841},
++	{0x4f,0xa0,390604},
++	{0x4f,0xa2,391360},
++	{0x4f,0xa4,392110},
++	{0x4f,0xa6,392855},
++	{0x4f,0xa8,393593},
++	{0x4f,0xaa,395054},
++	{0x4f,0xac,396491},
++	{0x4f,0xae,397908},
++	{0x4f,0xb0,399303},
++	{0x4f,0xb2,400678},
++	{0x4f,0xb4,402034},
++	{0x4f,0xb6,403370},
++	{0x4f,0xb8,404688},
++	{0x4f,0xba,405987},
++	{0x4f,0xbc,407269},
++	{0x4f,0xbe,408534},
++	{0x4f,0xc0,409782},
++	{0x4f,0xc2,411014},
++	{0x4f,0xc4,412230},
++	{0x4f,0xc6,413430},
++	{0x4f,0xc8,414616},
++	{0x4f,0xca,415787},
++	{0x4f,0xcc,416943},
++	{0x4f,0xce,418086},
++	{0x4f,0xd0,419215},
++	{0x4f,0xd2,420330},
++	{0x4f,0xd4,421433},
++	{0x4f,0xd6,422523},
++	{0x4f,0xd8,423600},
++	{0x4f,0xda,424665},
++	{0x4f,0xdc,425719},
++	{0x4f,0xdf,426760},
++	{0x4f,0xe0,427791},
++	{0x4f,0xe2,428810},
++	{0x4f,0xe4,429819},
++	{0x4f,0xe6,430816},
++	{0x4f,0xe8,431804},
++	{0x4f,0xea,432781},
++	{0x4f,0xec,433748},
++	{0x4f,0xee,434706},
++	{0x4f,0xf0,435653},
++	{0x4f,0xf2,436592},
++	{0x4f,0xf4,437521},
++	{0x4f,0xf6,438441},
++	{0x4f,0xf8,439352},
++	{0x4f,0xfa,440255},
++	{0x4f,0xfc,441149},
++	{0x4f,0xfe,442035},
++	{0x5f,0x80,443135},
++};
++
++static inline struct sc230ai_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct sc230ai_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct sc230ai_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++static struct regval_list sc230ai_init_regs_1920_1080_30fps_MIPI[] = {
++	{0x0103,0x01},
++	{0x0100,0x00},
++	{0x36e9,0x80},
++	{0x37f9,0x80},
++	{0x301f,0x01},
++	{0x3221,0x06},
++	{0x3301,0x07},
++	{0x3304,0x50},
++	{0x3306,0x70},
++	{0x3308,0x18},
++	{0x3309,0x68},
++	{0x330a,0x01},
++	{0x330b,0x20},
++	{0x331e,0x41},
++	{0x331f,0x59},
++	{0x3333,0x10},
++	{0x3334,0x40},
++	{0x335d,0x60},
++	{0x335e,0x06},
++	{0x335f,0x08},
++	{0x3364,0x5e},
++	{0x337c,0x02},
++	{0x337d,0x0a},
++	{0x3390,0x01},
++	{0x3391,0x0b},
++	{0x3392,0x0f},
++	{0x3393,0x09},
++	{0x3394,0x0d},
++	{0x3395,0x60},
++	{0x3396,0x48},
++	{0x3397,0x49},
++	{0x3398,0x4b},
++	{0x3399,0x06},
++	{0x339a,0x0a},
++	{0x339b,0x0d},
++	{0x339c,0x60},
++	{0x33a2,0x04},
++	{0x33af,0x40},
++	{0x33b1,0x80},
++	{0x33b3,0x40},
++	{0x33b9,0x0a},
++	{0x33f9,0xa0},
++	{0x33fb,0xbf},
++	{0x33fc,0x5f},
++	{0x33fd,0x7f},
++	{0x349f,0x03},
++	{0x34a6,0x4b},
++	{0x34a7,0x5f},
++	{0x34a8,0x30},
++	{0x34a9,0x20},
++	{0x34aa,0x01},
++	{0x34ab,0x28},
++	{0x34ac,0x01},
++	{0x34ad,0x58},
++	{0x34f8,0x7f},
++	{0x34f9,0x10},
++	{0x3630,0xc0},
++	{0x3633,0x44},
++	{0x363b,0x20},
++	{0x3670,0x09},
++	{0x3674,0xb0},
++	{0x3675,0x80},
++	{0x3676,0x88},
++	{0x367c,0x40},
++	{0x367d,0x49},
++	{0x3690,0x44},
++	{0x3691,0x33},
++	{0x3692,0x43},
++	{0x369c,0x49},
++	{0x369d,0x4f},
++	{0x36ae,0x4b},
++	{0x36af,0x4f},
++	{0x36b0,0x87},
++	{0x36b1,0x94},
++	{0x36b2,0xbc},
++	{0x36d0,0x01},
++	{0x3722,0x97},
++	{0x3728,0x90},
++	{0x3901,0x02},
++	{0x3902,0xc5},
++	{0x3904,0x04},
++	{0x3907,0x00},
++	{0x3908,0x41},
++	{0x3909,0x00},
++	{0x390a,0x00},
++	{0x3933,0x84},
++	{0x3934,0x10},
++	{0x3940,0x78},
++	{0x3942,0x04},
++	{0x3943,0x11},
++	{0x3e00,0x00},
++	{0x3e01,0x8c},
++	{0x3e02,0x20},
++	{0x440e,0x02},
++	{0x5010,0x01},
++	{0x5787,0x08},
++	{0x5788,0x03},
++	{0x5789,0x00},
++	{0x578a,0x10},
++	{0x578b,0x08},
++	{0x578c,0x00},
++	{0x5790,0x08},
++	{0x5791,0x04},
++	{0x5792,0x00},
++	{0x5793,0x10},
++	{0x5794,0x08},
++	{0x5795,0x00},
++	{0x5799,0x06},
++	{0x57ad,0x00},
++	{0x5ae0,0xfe},
++	{0x5ae1,0x40},
++	{0x5ae2,0x3f},
++	{0x5ae3,0x38},
++	{0x5ae4,0x28},
++	{0x5ae5,0x3f},
++	{0x5ae6,0x38},
++	{0x5ae7,0x28},
++	{0x5ae8,0x3f},
++	{0x5ae9,0x3c},
++	{0x5aea,0x2c},
++	{0x5aeb,0x3f},
++	{0x5aec,0x3c},
++	{0x5aed,0x2c},
++	{0x5af4,0x3f},
++	{0x5af5,0x38},
++	{0x5af6,0x28},
++	{0x5af7,0x3f},
++	{0x5af8,0x38},
++	{0x5af9,0x28},
++	{0x5afa,0x3f},
++	{0x5afb,0x3c},
++	{0x5afc,0x2c},
++	{0x5afd,0x3f},
++	{0x5afe,0x3c},
++	{0x5aff,0x2c},
++	{0x36e9,0x20},
++	{0x37f9,0x27},
++	{SC230AI_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list sc230ai_init_regs_1920_1080_30fps_wdr_MIPI[] = {
++	{0x0103,0x01},
++	{0x0100,0x00},
++	{0x36e9,0x80},
++	{0x37f9,0x80},
++	{0x301f,0x06},
++	{0x320e,0x08},
++	{0x320f,0xca},
++	{0x3221,0x06},
++	{0x3250,0xff},
++	{0x3281,0x01},
++	{0x3301,0x09},
++	{0x3304,0x50},
++	{0x3306,0x48},
++	{0x3308,0x18},
++	{0x3309,0x68},
++	{0x330a,0x00},
++	{0x330b,0xc0},
++	{0x331e,0x41},
++	{0x331f,0x59},
++	{0x3333,0x10},
++	{0x3334,0x40},
++	{0x335d,0x60},
++	{0x335e,0x06},
++	{0x335f,0x08},
++	{0x3364,0x5e},
++	{0x337c,0x02},
++	{0x337d,0x0a},
++	{0x3390,0x01},
++	{0x3391,0x0b},
++	{0x3392,0x0f},
++	{0x3393,0x0c},
++	{0x3394,0x0d},
++	{0x3395,0x60},
++	{0x3396,0x48},
++	{0x3397,0x49},
++	{0x3398,0x4f},
++	{0x3399,0x0a},
++	{0x339a,0x0f},
++	{0x339b,0x14},
++	{0x339c,0x60},
++	{0x33a2,0x04},
++	{0x33af,0x40},
++	{0x33b1,0x80},
++	{0x33b3,0x40},
++	{0x33b9,0x0a},
++	{0x33f9,0x70},
++	{0x33fb,0x90},
++	{0x33fc,0x4b},
++	{0x33fd,0x5f},
++	{0x349f,0x03},
++	{0x34a6,0x4b},
++	{0x34a7,0x4f},
++	{0x34a8,0x30},
++	{0x34a9,0x20},
++	{0x34aa,0x00},
++	{0x34ab,0xe0},
++	{0x34ac,0x01},
++	{0x34ad,0x00},
++	{0x34f8,0x5f},
++	{0x34f9,0x10},
++	{0x3630,0xc0},
++	{0x3633,0x44},
++	{0x3637,0x29},
++	{0x363b,0x20},
++	{0x3670,0x09},
++	{0x3674,0xb0},
++	{0x3675,0x80},
++	{0x3676,0x88},
++	{0x367c,0x40},
++	{0x367d,0x49},
++	{0x3690,0x44},
++	{0x3691,0x44},
++	{0x3692,0x54},
++	{0x369c,0x49},
++	{0x369d,0x4f},
++	{0x36ae,0x4b},
++	{0x36af,0x4f},
++	{0x36b0,0x87},
++	{0x36b1,0x94},
++	{0x36b2,0xbc},
++	{0x36d0,0x01},
++	{0x36ea,0x0b},
++	{0x36eb,0x04},
++	{0x36ec,0x0c},
++	{0x36ed,0x24},
++	{0x370f,0x01},
++	{0x3722,0x17},
++	{0x3728,0x90},
++	{0x37b0,0x17},
++	{0x37b1,0x17},
++	{0x37b2,0x97},
++	{0x37b3,0x4b},
++	{0x37b4,0x4f},
++	{0x37fa,0x0b},
++	{0x37fb,0x24},
++	{0x37fc,0x10},
++	{0x37fd,0x22},
++	{0x3901,0x02},
++	{0x3902,0xc5},
++	{0x3904,0x04},
++	{0x3907,0x00},
++	{0x3908,0x41},
++	{0x3909,0x00},
++	{0x390a,0x00},
++	{0x391f,0x04},
++	{0x3933,0x84},
++	{0x3934,0x10},
++	{0x3940,0x78},
++	{0x3942,0x04},
++	{0x3943,0x11},
++	{0x3e00,0x01},
++	{0x3e01,0x06},
++	{0x3e02,0x00},
++//	{0x3e22,0x00}, //short exp
++	{0x3e04,0x10}, //short exp
++	{0x3e05,0x60}, //short exp
++	{0x3e06,0x00},
++	{0x3e07,0x80},
++	{0x3e08,0x03},
++	{0x3e09,0x40},
++	{0x3e10,0x00},
++	{0x3e11,0x80},
++	{0x3e12,0x03},
++	{0x3e13,0x40},
++	{0x3e23,0x00},
++	{0x3e24,0x88},
++	{0x440e,0x02},
++	{0x4816,0x71}, //vc
++	{0x5010,0x00},
++	{0x5787,0x08},
++	{0x5788,0x03},
++	{0x5789,0x00},
++	{0x578a,0x10},
++	{0x578b,0x08},
++	{0x578c,0x00},
++	{0x5790,0x08},
++	{0x5791,0x04},
++	{0x5792,0x00},
++	{0x5793,0x10},
++	{0x5794,0x08},
++	{0x5795,0x00},
++	{0x5799,0x06},
++	{0x57ad,0x00},
++	{0x5ae0,0xfe},
++	{0x5ae1,0x40},
++	{0x5ae2,0x3f},
++	{0x5ae3,0x38},
++	{0x5ae4,0x28},
++	{0x5ae5,0x3f},
++	{0x5ae6,0x38},
++	{0x5ae7,0x28},
++	{0x5ae8,0x3f},
++	{0x5ae9,0x3c},
++	{0x5aea,0x2c},
++	{0x5aeb,0x3f},
++	{0x5aec,0x3c},
++	{0x5aed,0x2c},
++	{0x5af4,0x3f},
++	{0x5af5,0x38},
++	{0x5af6,0x28},
++	{0x5af7,0x3f},
++	{0x5af8,0x38},
++	{0x5af9,0x28},
++	{0x5afa,0x3f},
++	{0x5afb,0x3c},
++	{0x5afc,0x2c},
++	{0x5afd,0x3f},
++	{0x5afe,0x3c},
++	{0x5aff,0x2c},
++	{0x36e9,0x20},
++	{0x37f9,0x24},
++	{SC230AI_REG_END, 0x00},
++};
++
++
++static struct regval_list sc230ai_init_regs_1920_1080_60fps_MIPI[] = {
++	{0x0103,0x01},
++	{0x0100,0x00},
++	{0x36e9,0x80},
++	{0x37f9,0x80},
++	{0x301f,0x02},
++	{0x3221,0x06},
++	{0x3301,0x09},
++	{0x3304,0x50},
++	{0x3306,0x48},
++	{0x3308,0x18},
++	{0x3309,0x68},
++	{0x330a,0x00},
++	{0x330b,0xc0},
++	{0x331e,0x41},
++	{0x331f,0x59},
++	{0x3333,0x10},
++	{0x3334,0x40},
++	{0x335d,0x60},
++	{0x335e,0x06},
++	{0x335f,0x08},
++	{0x3364,0x5e},
++	{0x337c,0x02},
++	{0x337d,0x0a},
++	{0x3390,0x01},
++	{0x3391,0x0b},
++	{0x3392,0x0f},
++	{0x3393,0x0c},
++	{0x3394,0x0d},
++	{0x3395,0x60},
++	{0x3396,0x48},
++	{0x3397,0x49},
++	{0x3398,0x4f},
++	{0x3399,0x0a},
++	{0x339a,0x0f},
++	{0x339b,0x14},
++	{0x339c,0x60},
++	{0x33a2,0x04},
++	{0x33af,0x40},
++	{0x33b1,0x80},
++	{0x33b3,0x40},
++	{0x33b9,0x0a},
++	{0x33f9,0x70},
++	{0x33fb,0x90},
++	{0x33fc,0x4b},
++	{0x33fd,0x5f},
++	{0x349f,0x03},
++	{0x34a6,0x4b},
++	{0x34a7,0x4f},
++	{0x34a8,0x30},
++	{0x34a9,0x20},
++	{0x34aa,0x00},
++	{0x34ab,0xe0},
++	{0x34ac,0x01},
++	{0x34ad,0x00},
++	{0x34f8,0x5f},
++	{0x34f9,0x10},
++	{0x3630,0xc0},
++	{0x3633,0x44},
++	{0x3637,0x29},
++	{0x363b,0x20},
++	{0x3670,0x09},
++	{0x3674,0xb0},
++	{0x3675,0x80},
++	{0x3676,0x88},
++	{0x367c,0x40},
++	{0x367d,0x49},
++	{0x3690,0x44},
++	{0x3691,0x44},
++	{0x3692,0x54},
++	{0x369c,0x49},
++	{0x369d,0x4f},
++	{0x36ae,0x4b},
++	{0x36af,0x4f},
++	{0x36b0,0x87},
++	{0x36b1,0x94},
++	{0x36b2,0xbc},
++	{0x36d0,0x01},
++	{0x36ea,0x0b},
++	{0x36eb,0x04},
++	{0x36ec,0x0c},
++	{0x36ed,0x24},
++	{0x370f,0x01},
++	{0x3722,0x17},
++	{0x3728,0x90},
++	{0x37b0,0x17},
++	{0x37b1,0x17},
++	{0x37b2,0x97},
++	{0x37b3,0x4b},
++	{0x37b4,0x4f},
++	{0x37fa,0x0b},
++	{0x37fb,0x24},
++	{0x37fc,0x10},
++	{0x37fd,0x22},
++	{0x3901,0x02},
++	{0x3902,0xc5},
++	{0x3904,0x04},
++	{0x3907,0x00},
++	{0x3908,0x41},
++	{0x3909,0x00},
++	{0x390a,0x00},
++	{0x391f,0x04},
++	{0x3933,0x84},
++	{0x3934,0x10},
++	{0x3940,0x78},
++	{0x3942,0x04},
++	{0x3943,0x11},
++	{0x3e00,0x00},
++	{0x3e01,0x8c},
++	{0x3e02,0x20},
++	{0x440e,0x02},
++	{0x5010,0x01},
++	{0x5787,0x08},
++	{0x5788,0x03},
++	{0x5789,0x00},
++	{0x578a,0x10},
++	{0x578b,0x08},
++	{0x578c,0x00},
++	{0x5790,0x08},
++	{0x5791,0x04},
++	{0x5792,0x00},
++	{0x5793,0x10},
++	{0x5794,0x08},
++	{0x5795,0x00},
++	{0x5799,0x06},
++	{0x57ad,0x00},
++	{0x5ae0,0xfe},
++	{0x5ae1,0x40},
++	{0x5ae2,0x3f},
++	{0x5ae3,0x38},
++	{0x5ae4,0x28},
++	{0x5ae5,0x3f},
++	{0x5ae6,0x38},
++	{0x5ae7,0x28},
++	{0x5ae8,0x3f},
++	{0x5ae9,0x3c},
++	{0x5aea,0x2c},
++	{0x5aeb,0x3f},
++	{0x5aec,0x3c},
++	{0x5aed,0x2c},
++	{0x5af4,0x3f},
++	{0x5af5,0x38},
++	{0x5af6,0x28},
++	{0x5af7,0x3f},
++	{0x5af8,0x38},
++	{0x5af9,0x28},
++	{0x5afa,0x3f},
++	{0x5afb,0x3c},
++	{0x5afc,0x2c},
++	{0x5afd,0x3f},
++	{0x5afe,0x3c},
++	{0x5aff,0x2c},
++	{0x36e9,0x20},
++	{0x37f9,0x24},
++	{SC230AI_REG_END, 0x00},
++};
++
++
++static struct regval_list sc230ai_stream_on[] = {
++	{0x0100,0x01},
++	{SC230AI_REG_END, 0x00},
++};
++
++static struct regval_list sc230ai_stream_off[] = {
++	{0x0100,0x00},
++	{SC230AI_REG_END, 0x00},
++};
++
++
++int sc230ai_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int sc230ai_write(struct v4l2_subdev *sd, unsigned short reg,
++			unsigned char value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3] = {(reg>>8)&0xff, reg&0xff, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 3,
++		.buf	= buf,
++	};
++	int ret;
++	unsigned int timeout  = 100;
++	while(timeout--){
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == -EAGAIN){
++			msleep(100);
++			continue;
++		}
++		else
++			break;
++	}
++	if (ret > 0)
++		ret = 0;
++	return ret;
++}
++
++static int sc230ai_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != SC230AI_REG_END) {
++		if (vals->reg_num == SC230AI_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = sc230ai_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++			if (vals->reg_num == SC230AI_PAGE_REG){
++				val &= 0xf8;
++				val |= (vals->value & 0x07);
++				ret = sc230ai_write(sd, vals->reg_num, val);
++				ret = sc230ai_read(sd, vals->reg_num, &val);
++			}
++		}
++		vals++;
++	}
++	return 0;
++}
++static int sc230ai_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != SC230AI_REG_END) {
++		if (vals->reg_num == SC230AI_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = sc230ai_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int sc230ai_lightup(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc230ai_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->led.pin, info->led.active_level);
++	} else {
++		gpio_direction_output(info->led.pin, !info->led.active_level);
++	}
++	return 0;
++}
++
++static int sc230ai_xshutdn(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc230ai_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->xshutdn.pin, info->xshutdn.active_level);
++	} else {
++		gpio_direction_output(info->xshutdn.pin, !info->xshutdn.active_level);
++	}
++	return 0;
++}
++
++static int sc230ai_pwdn(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc230ai_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->pwdn.pin, info->pwdn.active_level);
++		msleep(10);
++	} else {
++		gpio_direction_output(info->pwdn.pin, !info->pwdn.active_level);
++	}
++	return 0;
++}
++
++static int sc230ai_hw_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc230ai_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->xshutdn.pin, !info->xshutdn.active_level);
++		gpio_direction_output(info->xshutdn.pin, info->xshutdn.active_level);
++	}
++	return 0;
++}
++
++static int sc230ai_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++
++	ret = sc230ai_read(sd, 0x3107, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != SC230AI_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = sc230ai_read(sd, 0x3108, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != SC230AI_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++	return 0;
++
++}
++
++static struct sc230ai_win_size sc230ai_win_sizes[] = {
++	{
++		.width				= 1920,
++		.height				= 1080,
++		.sensor_info.fps				= 30 << 16 | 1,
++		.sensor_info.total_width			= 1928,
++		.sensor_info.total_height			= 1152,
++		.sensor_info.wdr_en				= 0,
++		.sensor_info.mipi_cfg.clk			= 600,
++		.sensor_info.mipi_cfg.twidth		= 1920,
++		.sensor_info.mipi_cfg.theight		= 1080,
++		.sensor_info.mipi_cfg.mipi_mode		= SENSOR_MIPI_OTHER_MODE,
++		.sensor_info.mipi_cfg.mipi_vcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_hcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3y	= 0,
++		.sensor_info.mipi_cfg.hcrop_diff_en		= 0,
++		.sensor_info.mipi_cfg.line_sync_mode	= 0,
++		.sensor_info.mipi_cfg.work_start_flag	= 0,
++		.sensor_info.mipi_cfg.data_type_en		= 0,
++		.sensor_info.mipi_cfg.data_type_value	= RAW10,
++		.sensor_info.mipi_cfg.del_start		= 0,
++		.sensor_info.mipi_cfg.sensor_frame_mode	= TX_SENSOR_DEFAULT_FRAME_MODE,
++		.sensor_info.mipi_cfg.sensor_fid_mode	= 0,
++		.sensor_info.mipi_cfg.sensor_mode		= TX_SENSOR_DEFAULT_MODE,
++		.sensor_info.mipi_cfg.sensor_csi_fmt		= TX_SENSOR_RAW10,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= sc230ai_init_regs_1920_1080_30fps_MIPI,
++	},
++	{
++		.width				= 1920,
++		.height				= 1080,
++		.sensor_info.fps				= 60 << 16 | 1,
++		.sensor_info.total_width			= 1928,
++		.sensor_info.total_height			= 1152,
++		.sensor_info.wdr_en				= 0,
++		.sensor_info.mipi_cfg.clk			= 600,
++		.sensor_info.mipi_cfg.twidth		= 1920,
++		.sensor_info.mipi_cfg.theight		= 1080,
++		.sensor_info.mipi_cfg.mipi_mode		= SENSOR_MIPI_OTHER_MODE,
++		.sensor_info.mipi_cfg.mipi_vcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_hcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3y	= 0,
++		.sensor_info.mipi_cfg.hcrop_diff_en		= 0,
++		.sensor_info.mipi_cfg.line_sync_mode	= 0,
++		.sensor_info.mipi_cfg.work_start_flag	= 0,
++		.sensor_info.mipi_cfg.data_type_en		= 0,
++		.sensor_info.mipi_cfg.data_type_value	= RAW10,
++		.sensor_info.mipi_cfg.del_start		= 0,
++		.sensor_info.mipi_cfg.sensor_frame_mode	= TX_SENSOR_DEFAULT_FRAME_MODE,
++		.sensor_info.mipi_cfg.sensor_fid_mode	= 0,
++		.sensor_info.mipi_cfg.sensor_mode		= TX_SENSOR_DEFAULT_MODE,
++		.sensor_info.mipi_cfg.sensor_csi_fmt		= TX_SENSOR_RAW10,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= sc230ai_init_regs_1920_1080_60fps_MIPI,
++	},
++	{
++		.width				= 1920,
++		.height				= 1080,
++		.sensor_info.fps				= 30 << 16 | 1,
++		.sensor_info.total_width			= 1928,
++		.sensor_info.total_height			= 2250,
++		.sensor_info.wdr_en				= 1,
++		.sensor_info.mipi_cfg.clk			= 600,
++		.sensor_info.mipi_cfg.twidth		= 1920,
++		.sensor_info.mipi_cfg.theight		= 1080,
++		.sensor_info.mipi_cfg.mipi_mode		= SENSOR_MIPI_OTHER_MODE,
++		.sensor_info.mipi_cfg.mipi_vcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_hcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3y	= 0,
++		.sensor_info.mipi_cfg.hcrop_diff_en		= 0,
++		.sensor_info.mipi_cfg.line_sync_mode	= 0,
++		.sensor_info.mipi_cfg.work_start_flag	= 0,
++		.sensor_info.mipi_cfg.data_type_en		= 0,
++		.sensor_info.mipi_cfg.data_type_value	= RAW10,
++		.sensor_info.mipi_cfg.del_start		= 0,
++		.sensor_info.mipi_cfg.sensor_frame_mode	= TX_SENSOR_WDR_2_FRAME_MODE,
++		.sensor_info.mipi_cfg.sensor_fid_mode	= 0,
++		.sensor_info.mipi_cfg.sensor_mode		= TX_SENSOR_VC_MODE,
++		.sensor_info.mipi_cfg.sensor_csi_fmt		= TX_SENSOR_RAW10,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= sc230ai_init_regs_1920_1080_30fps_wdr_MIPI,
++	},
++};
++
++#if 0
++static int sc230ai_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad || code->index >= N_OV2735a_FMTS)
++		return -EINVAL;
++
++	code->code = sc230ai_formats[code->index].mbus_code;
++	return 0;
++}
++#endif
++
++/*
++ * Set a format.
++ */
++static int sc230ai_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++
++	if (format->pad)
++	{
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int sc230ai_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct sc230ai_info *info = to_state(sd);
++	struct sc230ai_win_size *wsize = info->win;
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = wsize->width;
++	fmt->height = wsize->height;
++	fmt->code = wsize->mbus_code;
++	fmt->colorspace = wsize->colorspace;
++	*(unsigned int *)fmt->reserved = (unsigned int)&wsize->sensor_info; /*reserved[0] reserved[1]*/
++
++//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int sc230ai_s_wdr(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++	struct sc230ai_info *info = to_state(sd);
++//	printk("%s:%d\n", __func__, value);
++	if(value)
++		info->win = &sc230ai_win_sizes[2];
++	else
++		info->win = &sc230ai_win_sizes[0];
++	return ret;
++}
++
++static int sc230ai_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc230ai_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc230ai_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc230ai_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int sc230ai_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int sc230ai_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++//	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain, unsigned int *value, unsigned int *fine_value)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(sc230ai_again_lut); i++) {
++		lut = &sc230ai_again_lut[i];
++
++		if(gain <= lut->gain) {
++			*value = lut->value;
++			*fine_value = lut->fine_value;
++			return lut->value;
++		}
++	}
++	/*last value.*/
++	*value = lut->value;
++	*fine_value = lut->fine_value;
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval, unsigned int fine_reg_val)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(sc230ai_again_lut); i++) {
++		lut = &sc230ai_again_lut[i];
++
++		if(regval == lut->value && fine_reg_val == lut->fine_value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return -EINVAL;
++}
++
++static int sc230ai_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	char v = 0;
++	unsigned int reg_val = 0;
++	unsigned int fine_reg_val = 0;
++	int ret = 0;
++
++
++	ret = sc230ai_read(sd, 0x3e09, &v);
++	reg_val = v ;
++	ret = sc230ai_read(sd, 0x3e07, &v);
++	fine_reg_val = v ;
++
++	*value = regval_to_again(reg_val, fine_reg_val);
++
++	return ret;
++
++}
++
++static int sc230ai_g_again_short(struct v4l2_subdev *sd, __s32 *value)
++{
++	char v = 0;
++	unsigned int reg_val = 0;
++	unsigned int fine_reg_val = 0;
++	int ret = 0;
++
++
++	ret = sc230ai_read(sd, 0x3e13, &v);
++	reg_val = v ;
++	ret = sc230ai_read(sd, 0x3e11, &v);
++	fine_reg_val = v ;
++
++	*value = regval_to_again(reg_val, fine_reg_val);
++
++	return ret;
++
++}
++
++/*set analog gain db value, map value to sensor register.*/
++static int sc230ai_s_again(struct v4l2_subdev *sd, int value)
++{
++	struct sc230ai_info *info = to_state(sd);
++	unsigned int reg_value;
++	unsigned int reg_fine_value;
++	int ret = 0;
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		again_to_regval(info->again->default_value, &reg_value, &reg_fine_value);
++	} else {
++		again_to_regval(value, &reg_value, &reg_fine_value);
++	}
++
++	ret += sc230ai_write(sd, 0x3e09, (unsigned char)(reg_value));
++	ret += sc230ai_write(sd, 0x3e07, (unsigned char)(reg_fine_value));
++	if (ret < 0){
++		printk("sc230ai_write error  %d\n" ,__LINE__ );
++		return ret;
++	}
++	return 0;
++}
++
++static int sc230ai_s_again_short(struct v4l2_subdev *sd, int value)
++{
++	struct sc230ai_info *info = to_state(sd);
++	unsigned int reg_value;
++	unsigned int reg_fine_value;
++	int ret = 0;
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		again_to_regval(info->again->default_value, &reg_value, &reg_fine_value);
++	} else {
++		again_to_regval(value, &reg_value, &reg_fine_value);
++	}
++
++	ret += sc230ai_write(sd, 0x3e13, (unsigned char)(reg_value));
++	ret += sc230ai_write(sd, 0x3e11, (unsigned char)(reg_fine_value));
++	if (ret < 0){
++		printk("sc230ai_write error  %d\n" ,__LINE__ );
++		return ret;
++	}
++	return 0;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int sc230ai_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc230ai_s_exp(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	value *= 2; /*unit in half line*/
++	ret += sc230ai_write(sd, 0x3e00, (unsigned char)((value >> 12) & 0xf));
++	ret += sc230ai_write(sd, 0x3e01, (unsigned char)((value >> 4) & 0xff));
++	ret += sc230ai_write(sd, 0x3e02, (unsigned char)(value & 0xf) << 4);
++
++	if (ret < 0) {
++		printk("sc230ai_write error  %d\n" ,__LINE__);
++		return ret;
++	}
++
++	return 0;
++}
++
++static int sc230ai_s_exp_short(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	value *= 2; /*unit in half line*/
++	ret += sc230ai_write(sd, 0x3e22, (unsigned char)((value >> 12) & 0xf));
++	ret += sc230ai_write(sd, 0x3e04, (unsigned char)((value >> 4) & 0xff));
++	ret += sc230ai_write(sd, 0x3e05, (unsigned char)(value & 0xf) << 4);
++
++	if (ret < 0) {
++		printk("sc230ai_write error  %d\n" ,__LINE__);
++		return ret;
++	}
++
++	return 0;
++}
++
++
++static int sc230ai_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct sc230ai_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return sc230ai_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return sc230ai_g_again(sd, &info->again->val);
++	case V4L2_CID_USER_ANALOG_GAIN_SHORT:
++		return sc230ai_g_again_short(sd, &info->again_short->val);
++	}
++	return -EINVAL;
++}
++
++static int sc230ai_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct sc230ai_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return sc230ai_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return sc230ai_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return sc230ai_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return sc230ai_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* sc230ai_s_gain turns off auto gain */
++			return sc230ai_s_gain(sd, info->gain->val);
++		}
++		return sc230ai_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return sc230ai_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return sc230ai_s_again(sd, ctrl->val);
++	case V4L2_CID_USER_ANALOG_GAIN_SHORT:
++		return sc230ai_s_again_short(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return sc230ai_s_exp(sd, ctrl->val);
++	case V4L2_CID_USER_EXPOSURE_SHORT:
++		return sc230ai_s_exp_short(sd, ctrl->val);
++	case V4L2_CID_WIDE_DYNAMIC_RANGE:
++		return sc230ai_s_wdr(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops sc230ai_ctrl_ops = {
++	.s_ctrl = sc230ai_s_ctrl,
++	.g_volatile_ctrl = sc230ai_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int sc230ai_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = sc230ai_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int sc230ai_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	sc230ai_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++static int sc230ai_core_reset(struct v4l2_subdev *sd, u32 val)
++{
++	unsigned char v;
++	int ret;
++
++	/*software reset*/
++	ret = sc230ai_read(sd, 0x0103, &v);
++
++	if(val) {
++		v |= 1;
++		ret += sc230ai_write(sd, 0x0103, v);
++	}
++	return 0;
++}
++
++static int sc230ai_core_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc230ai_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = sc230ai_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++
++
++int sc230ai_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	int ret = 0;
++
++	if (enable) {
++		ret = sc230ai_write_array(sd, sc230ai_stream_on);
++		printk("sc230ai stream on\n");
++
++	}
++	else {
++		ret = sc230ai_write_array(sd, sc230ai_stream_off);
++		printk("sc230ai stream off\n");
++	}
++	return ret;
++}
++
++
++int sc230ai_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct sc230ai_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops sc230ai_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = sc230ai_g_register,
++	.s_register = sc230ai_s_register,
++#endif
++	.init = sc230ai_core_init,
++	.reset = sc230ai_core_reset,
++
++};
++
++static const struct v4l2_subdev_video_ops sc230ai_video_ops = {
++	.s_stream = sc230ai_s_stream,
++	.g_frame_interval	= sc230ai_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops sc230ai_pad_ops = {
++	//.enum_frame_interval = sc230ai_enum_frame_interval,
++	//.num_frame_size = sc230ai_enum_frame_size,
++	//.enum_mbus_code = sc230ai_enum_mbus_code,
++	.set_fmt = sc230ai_set_fmt,
++	.get_fmt = sc230ai_get_fmt,
++};
++
++static const struct v4l2_subdev_ops sc230ai_ops = {
++	.core = &sc230ai_core_ops,
++	.video = &sc230ai_video_ops,
++	.pad = &sc230ai_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int sc230ai_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_subdev *sd;
++	struct sc230ai_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++	unsigned long rate;
++	struct v4l2_ctrl_config cfg = {0};
++	int mclk_index = -1;
++	char id_div[9];
++	char id_mux[9];
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,xshutdn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->xshutdn.pin = gpio;
++		info->xshutdn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,pwdn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->pwdn.pin = gpio;
++		info->pwdn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,efsync-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->efsync.pin = gpio;
++		info->efsync.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,led-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->led.pin = gpio;
++		info->led.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++
++	v4l2_i2c_subdev_init(sd, client, &sc230ai_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++	of_property_read_u32(client->dev.of_node, "ingenic,mclk", &mclk_index);
++	if(mclk_index == 0) {
++		memcpy(id_div, "div_cim0", sizeof(id_div));
++		memcpy(id_mux, "mux_cim0", sizeof(id_mux));
++	} else if(mclk_index == 1) {
++		memcpy(id_div, "div_cim1", sizeof(id_div));
++		memcpy(id_mux, "mux_cim1", sizeof(id_mux));
++	} else if(mclk_index == 2) {
++		memcpy(id_div, "div_cim2", sizeof(id_div));
++		memcpy(id_mux, "mux_cim2", sizeof(id_mux));
++	} else
++		printk("Unkonwn mclk index\n");
++
++
++	info->clk = v4l2_clk_get(&client->dev, id_div);
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++	info->sclka = devm_clk_get(&client->dev, id_mux);
++
++	rate = v4l2_clk_get_rate(info->clk);
++	if (((rate / 1000) % 27000) != 0) {
++		ret = clk_set_parent(info->sclka, clk_get(NULL, "epll"));
++		info->sclka = devm_clk_get(&client->dev, "epll");
++		if (IS_ERR(info->sclka)) {
++			pr_err("get sclka failed\n");
++		} else {
++			rate = clk_get_rate(info->sclka);
++			if (((rate / 1000) % 27000) != 0) {
++				clk_set_rate(info->sclka, 891000000);
++			}
++		}
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 27000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++	*(volatile unsigned int *)(0xb0010100) = 1; // set gpio a work at 1.8v
++	sc230ai_xshutdn(sd, 1);
++	sc230ai_pwdn(sd, 1);
++	sc230ai_lightup(sd, 1);
++#if 1
++	/* Make sure it's an sc230ai */
++	ret = sc230ai_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an sc230ai chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &sc230ai_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &sc230ai_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &sc230ai_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &sc230ai_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &sc230ai_ctrl_ops,
++			V4L2_CID_WIDE_DYNAMIC_RANGE, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &sc230ai_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &sc230ai_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 443135, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &sc230ai_ctrl_ops,
++			V4L2_CID_EXPOSURE, 1,  1152 - 4 , 4, 600);
++
++	cfg.ops = &sc230ai_ctrl_ops;
++	cfg.id = V4L2_CID_USER_EXPOSURE_SHORT;
++	cfg.name = "expo short";
++	cfg.type = V4L2_CTRL_TYPE_INTEGER;
++	cfg.min = 1;
++	cfg.max = 131;
++	cfg.step = 4;
++	cfg.def = 50;
++	info->exposure_short = v4l2_ctrl_new_custom(&info->hdl, &cfg, NULL);
++
++	memset(&cfg, 0, sizeof(cfg));
++	cfg.ops = &sc230ai_ctrl_ops;
++	cfg.id = V4L2_CID_USER_ANALOG_GAIN_SHORT;
++	cfg.name = "analog gain short";
++	cfg.type = V4L2_CTRL_TYPE_INTEGER;
++	cfg.min = 0;
++	cfg.max = 589824;
++	cfg.step = 1;
++	cfg.def = 10000;
++	info->again_short = v4l2_ctrl_new_custom(&info->hdl, &cfg, NULL);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "sc230ai Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int sc230ai_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct sc230ai_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id sc230ai_id[] = {
++	{ "sc230ai", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, sc230ai_id);
++
++static const struct of_device_id sc230ai_of_match[] = {
++	{.compatible = "smartsens,sc230ai", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, sc230ai_of_match);
++
++
++static struct i2c_driver sc230ai_driver = {
++	.driver = {
++		.name	= "sc230ai",
++		.of_match_table = of_match_ptr(sc230ai_of_match),
++	},
++	.probe		= sc230ai_probe,
++	.remove		= sc230ai_remove,
++	.id_table	= sc230ai_id,
++};
++
++module_i2c_driver(sc230ai_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for SmartSens sc230ai sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp-v2/sc2310.c b/module_drivers/drivers/media/i2c/ingenic-isp-v2/sc2310.c
+new file mode 100644
+index 000000000..03760e8bb
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp-v2/sc2310.c
+@@ -0,0 +1,2461 @@
++/*
++ * A V4L2 driver for SmartSens sc2310 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++#include <linux/clk.h>
++
++#include <isp-sensor.h>
++
++#define SC2310_CHIP_ID_H	(0x23)
++#define SC2310_CHIP_ID_L	(0x11)
++#define SC2310_REG_END		0xffff
++#define SC2310_REG_DELAY	0xfffe
++
++#define AGAIN_MAX_DB 0x64
++#define DGAIN_MAX_DB 0x64
++#define LOG2_GAIN_SHIFT 16
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++//#define SC2310_WDR_EN
++
++struct sc2310_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++};
++
++struct sc2310_gpio {
++	int pin;
++	int active_level;
++};
++
++struct sc2310_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++	struct v4l2_ctrl *again_short;
++
++	struct v4l2_clk *clk;
++	struct clk *sclka;
++
++	struct v4l2_ctrl *exposure;
++	struct v4l2_ctrl *exposure_short;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct sc2310_win_size *win;
++
++	struct sc2310_gpio reset;
++	struct sc2310_gpio ircutp;
++	struct sc2310_gpio ircutn;
++	struct sc2310_gpio pwen;
++	struct sc2310_gpio pwdn;
++};
++
++void sc2310_power_init_seq(struct sc2310_info *info);
++static inline struct sc2310_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct sc2310_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct sc2310_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;
++	unsigned int gain;
++};
++
++struct again_lut sc2310_again_lut[] = {
++	{0x340, 0},
++	{0x342, 2886},
++	{0x344, 5776},
++	{0x346, 8494},
++	{0x348, 11136},
++	{0x34a, 13706},
++	{0x34c, 16287},
++	{0x34e, 18723},
++	{0x350, 21097},
++	{0x352, 23414},
++	{0x354, 25746},
++	{0x356, 27953},
++	{0x358, 30109},
++	{0x35a, 32217},
++	{0x35c, 34345},
++	{0x35e, 36361},
++	{0x360, 38336},
++	{0x362, 40270},
++	{0x364, 42226},
++	{0x366, 44082},
++	{0x368, 45904},
++	{0x36a, 47690},
++	{0x36c, 49500},
++	{0x36e, 51220},
++	{0x370, 52910},
++	{0x372, 54571},
++	{0x374, 56254},
++	{0x376, 57857},
++	{0x378, 59433},
++	{0x37a, 60984},
++	{0x37c, 62558},
++	{0x37e, 64059},
++	{0x740, 65536},
++	{0x742, 68468},
++	{0x744, 71267},
++	{0x746, 74030},
++	{0x748, 76672},
++	{0x74a, 79283},
++	{0x74c, 81784},
++	{0x74e, 84259},
++	{0x750, 86633},
++	{0x752, 88986},
++	{0x754, 91246},
++	{0x756, 93489},
++	{0x2341, 96091},
++	{0x2343, 98956},
++	{0x2345, 101736},
++	{0x2347, 104437},
++	{0x2349, 107063},
++	{0x234b, 109618},
++	{0x234d, 112106},
++	{0x234f, 114530},
++	{0x2351, 116894},
++	{0x2353, 119200},
++	{0x2355, 121451},
++	{0x2357, 123649},
++	{0x2359, 125798},
++	{0x235b, 127899},
++	{0x235d, 129954},
++	{0x235f, 131965},
++	{0x2361, 133935},
++	{0x2363, 135864},
++	{0x2365, 137755},
++	{0x2367, 139609},
++	{0x2369, 141427},
++	{0x236b, 143211},
++	{0x236d, 144962},
++	{0x236f, 146681},
++	{0x2371, 148369},
++	{0x2373, 150027},
++	{0x2375, 151657},
++	{0x2377, 153260},
++	{0x2379, 154836},
++	{0x237b, 156385},
++	{0x237d, 157910},
++	{0x237f, 159411},
++	{0x2741, 161610},
++	{0x2743, 164475},
++	{0x2745, 167256},
++	{0x2747, 169958},
++	{0x2749, 172584},
++	{0x274b, 175140},
++	{0x274d, 177628},
++	{0x274f, 180052},
++	{0x2751, 182416},
++	{0x2753, 184722},
++	{0x2755, 186974},
++	{0x2757, 189172},
++	{0x2759, 191321},
++	{0x275b, 193423},
++	{0x275d, 195478},
++	{0x275f, 197490},
++	{0x2761, 199460},
++	{0x2763, 201389},
++	{0x2765, 203280},
++	{0x2767, 205134},
++	{0x2769, 206953},
++	{0x276b, 208736},
++	{0x276d, 210487},
++	{0x276f, 212207},
++	{0x2771, 213895},
++	{0x2773, 215554},
++	{0x2775, 217184},
++	{0x2777, 218786},
++	{0x2779, 220362},
++	{0x277b, 221912},
++	{0x277d, 223437},
++	{0x277f, 224938},
++	{0x2f41, 227146},
++	{0x2f43, 230011},
++	{0x2f45, 232792},
++	{0x2f47, 235494},
++	{0x2f49, 238120},
++	{0x2f4b, 240676},
++	{0x2f4d, 243164},
++	{0x2f4f, 245588},
++	{0x2f51, 247952},
++	{0x2f53, 250258},
++	{0x2f55, 252510},
++	{0x2f57, 254708},
++	{0x2f59, 256857},
++	{0x2f5b, 258959},
++	{0x2f5d, 261014},
++	{0x2f5f, 263026},
++	{0x2f61, 264996},
++	{0x2f63, 266925},
++	{0x2f65, 268816},
++	{0x2f67, 270670},
++	{0x2f69, 272489},
++	{0x2f6b, 274273},
++	{0x2f6d, 276023},
++	{0x2f6f, 277743},
++	{0x2f71, 279431},
++	{0x2f73, 281090},
++	{0x2f75, 282720},
++	{0x2f77, 284322},
++	{0x2f79, 285898},
++	{0x2f7b, 287448},
++	{0x2f7d, 288973},
++	{0x2f7f, 290474},
++	{0x3f41, 292682},
++	{0x3f43, 295547},
++	{0x3f45, 298328},
++	{0x3f47, 301030},
++	{0x3f49, 303656},
++	{0x3f4b, 306212},
++	{0x3f4d, 308700},
++	{0x3f4f, 311124},
++	{0x3f51, 313488},
++	{0x3f53, 315794},
++	{0x3f55, 318046},
++	{0x3f57, 320244},
++	{0x3f59, 322393},
++	{0x3f5b, 324495},
++	{0x3f5d, 326550},
++	{0x3f5f, 328562},
++	{0x3f61, 330532},
++	{0x3f63, 332461},
++	{0x3f65, 334352},
++	{0x3f67, 336206},
++	{0x3f69, 338025},
++	{0x3f6b, 339809},
++	{0x3f6d, 341559},
++	{0x3f6f, 343279},
++	{0x3f71, 344967},
++	{0x3f73, 346626},
++	{0x3f75, 348256},
++	{0x3f77, 349858},
++	{0x3f79, 351434},
++	{0x3f7b, 352984},
++	{0x3f7d, 354509},
++	{0x3f7f, 356010},
++};
++
++static struct regval_list sc2310_init_regs_1920_1080_25fps_mipi_dol[] = {
++	{0x0103, 0x01},
++	{0x0100, 0x00},
++	{0x36e9, 0xa6},
++	{0x36f9, 0x85},
++	{0x3001, 0xfe},
++	{0x3018, 0x33},
++	{0x301c, 0x78},
++	{0x3031, 0x0a},
++	{0x3037, 0x24},
++	{0x3038, 0x44},
++	{0x303f, 0x01},
++	{0x3200, 0x00},
++	{0x3201, 0x04},
++	{0x3202, 0x00},
++	{0x3203, 0x00},
++	{0x3204, 0x07},
++	{0x3205, 0x8b},
++	{0x3206, 0x04},
++	{0x3207, 0x3f},
++	{0x3208, 0x07},
++	{0x3209, 0x80},
++	{0x320a, 0x04},
++	{0x320b, 0x38},
++	{0x320c, 0x04},
++	{0x320d, 0x4c},
++	{0x320e, 0x08},//0x08
++	{0x320f, 0xca},
++	{0x3211, 0x04},
++	{0x3213, 0x04},
++	{0x3220, 0x51},
++	{0x3222, 0x29},
++	{0x3301, 0x10},
++	{0x3302, 0x10},
++	{0x3303, 0x30},
++	{0x3306, 0x54},
++	{0x3308, 0x10},
++	{0x3309, 0x48},
++	{0x330a, 0x00},
++	{0x330b, 0xb4},
++	{0x330e, 0x30},
++	{0x3314, 0x04},
++	{0x331b, 0x83},
++	{0x331e, 0x21},
++	{0x331f, 0x39},
++	{0x3320, 0x01},
++	{0x3324, 0x02},
++	{0x3325, 0x02},
++	{0x3326, 0x00},
++	{0x3333, 0x30},
++	{0x3334, 0x40},
++	{0x333d, 0x08},
++	{0x3341, 0x07},
++	{0x3343, 0x03},
++	{0x3364, 0x1d},
++	{0x3366, 0xc0},
++	{0x3367, 0x08},
++	{0x3368, 0x04},
++	{0x3369, 0x00},
++	{0x336a, 0x00},
++	{0x336b, 0x00},
++	{0x336c, 0x42},
++	{0x337f, 0x03},
++	{0x3380, 0x1b},
++	{0x33aa, 0x00},
++	{0x33b6, 0x07},
++	{0x33b7, 0x07},
++	{0x33b8, 0x10},
++	{0x33b9, 0x10},
++	{0x33ba, 0x10},
++	{0x33bb, 0x07},
++	{0x33bc, 0x07},
++	{0x33bd, 0x18},
++	{0x33be, 0x18},
++	{0x33bf, 0x18},
++	{0x33c0, 0x05},
++	{0x360f, 0x05},
++	{0x3621, 0xac},
++	{0x3622, 0xf6},
++	{0x3623, 0x18},
++	{0x3624, 0x47},
++	{0x3625, 0x09},
++	{0x3630, 0xc8},
++	{0x3631, 0x88},
++	{0x3632, 0x18},
++	{0x3633, 0x22},
++	{0x3634, 0x44},
++	{0x3635, 0x20},
++	{0x3636, 0x62},
++	{0x3637, 0x0c},
++	{0x3638, 0x24},
++	{0x363a, 0x83},
++	{0x363b, 0x08},
++	{0x363c, 0x05},
++	{0x363d, 0x05},
++	{0x3640, 0x00},
++	{0x366e, 0x04},
++	{0x3670, 0x6a},
++	{0x3671, 0xf6},
++	{0x3672, 0x16},
++	{0x3673, 0x16},
++	{0x3674, 0xc8},
++	{0x3675, 0x54},
++	{0x3676, 0x18},
++	{0x3677, 0x22},
++	{0x3678, 0x53},
++	{0x3679, 0x55},
++	{0x367a, 0x40},
++	{0x367b, 0x40},
++	{0x367c, 0x40},
++	{0x367d, 0x58},
++	{0x367e, 0x40},
++	{0x367f, 0x58},
++	{0x3693, 0x20},
++	{0x3694, 0x40},
++	{0x3695, 0x40},
++	{0x3696, 0x9f},
++	{0x3697, 0x9f},
++	{0x3698, 0x9f},
++	{0x369e, 0x40},
++	{0x369f, 0x40},
++	{0x36a0, 0x58},
++	{0x36a1, 0x78},
++	{0x36ea, 0x35},
++	{0x36eb, 0x0a},
++	{0x36ec, 0x0e},
++	{0x36fa, 0xa8},
++	{0x3802, 0x00},
++	{0x3901, 0x02},
++	{0x3902, 0xc5},
++	{0x3905, 0xd8},
++	{0x3907, 0x01},
++	{0x3908, 0x01},
++	{0x391d, 0x21},
++	{0x391e, 0x00},
++	{0x391f, 0xc0},
++	{0x3933, 0x28},
++	{0x3934, 0x0a},
++	{0x3940, 0x1b},
++	{0x3941, 0x40},
++	{0x3942, 0x08},
++	{0x3943, 0x0e},
++	{0x3e00, 0x01},
++	{0x3e01, 0x07},
++	{0x3e02, 0xa0},
++	{0x3e03, 0x0b},
++	{0x3e04, 0x10},
++	{0x3e05, 0x80},
++	{0x3e06, 0x00},
++	{0x3e07, 0x80},
++	{0x3e08, 0x03},
++	{0x3e09, 0x40},
++	{0x3e0e, 0x66},
++	{0x3e14, 0xb0},
++	{0x3e1e, 0x35},
++	{0x3e23, 0x00},
++	{0x3e24, 0x26},
++	{0x3e25, 0x03},
++	{0x3e26, 0x40},
++	{0x3f00, 0x0d},
++	{0x3f04, 0x02},
++	{0x3f05, 0x1e},
++	{0x3f08, 0x04},
++	{0x4500, 0x59},
++	{0x4501, 0xa4},
++	{0x4509, 0x10},
++	{0x4602, 0x0f},
++	{0x4603, 0x00},
++	{0x4809, 0x01},
++	{0x4816, 0x51},
++	{0x4837, 0x1a},
++	{0x5000, 0x06},
++	{0x5780, 0x7f},
++	{0x5781, 0x06},
++	{0x5782, 0x04},
++	{0x5783, 0x02},
++	{0x5784, 0x01},
++	{0x5785, 0x16},
++	{0x5786, 0x12},
++	{0x5787, 0x08},
++	{0x5788, 0x02},
++	{0x57a0, 0x00},
++	{0x57a1, 0x74},
++	{0x57a2, 0x01},
++	{0x57a3, 0xf4},
++	{0x57a4, 0xf0},
++	{0x6000, 0x06},
++	{0x6002, 0x06},
++	{0x36e9, 0x26},
++	{0x36f9, 0x05},
++	{0x0100, 0x01},
++
++	{SC2310_REG_DELAY, 10},
++	{SC2310_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list sc2310_init_regs_1920_1080_15fps_mipi[] = {
++	/* {0x0103, 0x01}, */
++	/* {0x0100, 0x00}, */
++	/* {SC2310_REG_DELAY, 10}, */
++	{0x36e9, 0xa3},//bypass pll1	20180830
++	{0x36f9, 0x85},//bypass pll2	20180830
++	{0x4509, 0x10},
++	{0x4500, 0x39},
++	{0x3907, 0x00},
++	{0x3908, 0x44},
++	{0x3633, 0x87},
++	{0x3306, 0x7e},
++	{0x330b, 0x00},
++	{0x3635, 0x4c},
++	{0x330e, 0x7a},
++	{0x3302, 0x1f}, //3302 need be odd why????  3366	 3302	 3621
++	{0x3e01, 0x8c},
++	{0x3e02, 0x80},
++	{0x3e09, 0x1f},
++	{0x3e08, 0x3f},
++	{0x3e06, 0x03},
++	{0x337f, 0x03}, //new auto precharge  330e in 3372   [7:6] 11: close div_rst 00:open div_rst
++	{0x3368, 0x04},
++	{0x3369, 0x00},
++	{0x336a, 0x00},
++	{0x336b, 0x00},
++	{0x3367, 0x08},
++	{0x330e, 0x30},
++	{0x3320, 0x06}, // New ramp offset timing
++	{0x3326, 0x00},
++	{0x331e, 0x11},
++	{0x331f, 0x21},
++	{0x3303, 0x20},
++	{0x3309, 0x30},
++	{0x4501, 0xc4},
++	{0x3e06, 0x00},
++	{0x3e08, 0x03},
++	{0x3e09, 0x10},
++	{0x3366, 0x7c}, // div_rst gap
++	{0x3622, 0x02},
++	{0x3633, 0x63},
++	{0x3038, 0x88},
++	{0x3635, 0x45},
++	{0x363b, 0x04},
++	{0x363c, 0x06},
++	{0x363d, 0x05},
++	{0x3633, 0x23},
++	{0x3301, 0x10},
++	{0x3306, 0x58},
++	{0x3622, 0x06},//blksun
++	{0x3631, 0x88},
++	{0x3630, 0x38},
++	{0x3633, 0x22},
++	{0x3018, 0x33},//[7:5] lane_num-1
++	{0x3031, 0x0c},//[3:0] bitmode
++	{0x3037, 0x40},//[6:5] bitsel  40:12bit
++	{0x3001, 0xFE},//[0] c_y
++	{0x4603, 0x00},//[0] data_fifo mipi mode
++	{0x4837, 0x35},//[7:0] pclk period * 2
++	{0x36e9, 0x83},
++	{0x36eb, 0x0f},
++	{0x36ec, 0x1f},
++	{0x303f, 0x01},
++	{0x330b, 0x20},
++	{0x3640, 0x00},
++	{0x3308, 0x10},
++	{0x3637, 0x0a},
++	{0x3e09, 0x20}, //3f for 2x fine gain
++	{0x363b, 0x08},
++	{0x3637, 0x09}, // ADC range: 14.8k fullwell  blc target : 0.9k	  output fullwell: 13.9k (5fps 27C  linear fullwell is 14.5K)
++	{0x3638, 0x14},
++	{0x3636, 0x65},
++	{0x3907, 0x01},
++	{0x3908, 0x01},
++	{0x3320, 0x01}, //ramp
++	{0x331e, 0x15},
++	{0x331f, 0x25},
++	{0x3366, 0x80},
++	{0x3634, 0x34},
++	{0x57a4, 0xf0}, //default c0,
++	{0x3635, 0x41}, //fpn
++	{0x3e02, 0x30}, //minimum exp 3? debug
++	{0x3333, 0x30}, //col fpn  G >br	 ?
++	{0x331b, 0x83},
++	{0x3334, 0x40},
++	{0x3306, 0x6c},
++	{0x3638, 0x17},
++	{0x330a, 0x01},
++	{0x330b, 0x14},
++	{0x3302, 0x10},
++	{0x3308, 0x08},
++	{0x3303, 0x18},
++	{0x3309, 0x18},
++	{0x331e, 0x11},
++	{0x331f, 0x11},
++	{0x3f00, 0x0d}, //[2]	hts/2-4
++	{0x3f04, 0x02},
++	{0x3f05, 0x22},
++	{0x3622, 0xe6},
++	{0x3633, 0x22},
++	{0x3630, 0xc8},
++	{0x3301, 0x10},
++	{0x36e9, 0xa3},
++	{0x36eb, 0x0b},
++	{0x36ec, 0x0f},
++	{0x3638, 0x27},
++	{0x33aa, 0x00}, //power save mode
++	{0x3624, 0x02},
++	{0x3621, 0xac},
++	{0x4509, 0x40},
++	{0x391e, 0x00},
++	{0x391f, 0xc0},
++	{0x3635, 0x45},
++	{0x336c, 0x40},
++	{0x3621, 0xae},
++	{0x3623, 0x08},
++	{0x36fa, 0xad}, //charge pump
++	{0x3634, 0x44},
++	{0x3621, 0xac}, //fifo delay
++	{0x4500, 0x59},
++	{0x3623, 0x18}, //for more grp rdout setup margin
++	{0x3f08, 0x04},
++	{0x3f00, 0x0d}, //[2]	hts/2-4-{3f08}
++	{0x3f04, 0x02}, //0321
++	{0x3f05, 0x1e}, //0321
++	{0x336c, 0x42}, //recover read timing
++	{0x5000, 0x06},//dpc enable
++	{0x5780, 0x7f},//auto blc setting
++	{0x57a0, 0x00},	//gain0 = 2x	0x0710Ö�0x071f
++	{0x57a1, 0x71},
++	{0x57a2, 0x01},	//gain1 = 8x	0x1f10Ö�0x1f1f
++	{0x57a3, 0xf1},
++	{0x5781, 0x06},	//white	1x
++	{0x5782, 0x04},	//2x
++	{0x5783, 0x02},	//8x
++	{0x5784, 0x01},	//128x
++	{0x5785, 0x16},	//black	1x
++	{0x5786, 0x12},	//2x
++	{0x5787, 0x08},	//8x
++	{0x5788, 0x02},	//128x
++	{0x3933, 0x28},
++	{0x3934, 0x0a},
++	{0x3940, 0x1b},
++	{0x3941, 0x40},
++	{0x3942, 0x08},
++	{0x3943, 0x0e},
++	{0x3208, 0x07},
++	{0x3209, 0x80},
++	{0x320a, 0x04},
++	{0x320b, 0x38},
++	{0x3211, 0x08},
++	{0x3213, 0x08},
++	{0x36e9, 0xa3},
++	{0x36ea, 0x77},
++	{0x36eb, 0x0b},
++	{0x36ec, 0x0f},
++	{0x36ed, 0x03},
++	{0x36f9, 0x85},
++	{0x36fa, 0x2d},
++	{0x36fb, 0x10},
++	{0x320c, 0x04},//hts=1125*2=2250
++	{0x320d, 0x65},
++	{0x320e, 0x12},//vts=2400
++	{0x320f, 0x60},
++	{0x3235, 0x12},//vts*2-0x02
++	{0x3236, 0xbe},
++	{0x3f04, 0x02},//{0x320c,0x320d}/2-0x3f08-0x04
++	{0x3f05, 0x2a},
++	{0x3802, 0x00},
++	{0x3624, 0x47},
++	{0x3621, 0xac},
++	{0x36fa, 0x2f},
++	{0x3637, 0x08},
++	{0x3638, 0x25},
++	{0x3635, 0x40},
++	{0x363b, 0x08},
++	{0x363c, 0x05},
++	{0x363d, 0x05},
++	{0x3303, 0x1c},
++	{0x3309, 0x1c},
++	{0x3324, 0x02}, //falling edge: ramp_offset_en cover ramp_integ_en
++	{0x3325, 0x02},
++	{0x333d, 0x08}, //count_div_rst_width
++	{0x3314, 0x04},
++	{0x36fa, 0x28},
++	{0x3205, 0x93},
++	{0x3e14, 0xb0}, //[7]:1 ana fine gain double 20~3f
++	{0x3e1e, 0x35}, //[7]:1 open DCG function in 0x3e03=0x03 [6]:0 DCG >2	[2] 1: dig_fine_gain_en [1:0] max fine gain  01: 3f
++	{0x3e0e, 0x66}, //[7:3] fine gain to compsensate 2.4x DCGgain  5 : 2.3125x  6:2.375x  [2]:1 DCG gain between sa1gain 2~4	 [1]:1 dcg gain in 0x3e08[5]
++	{0x3364, 0x1d},//[4] fine gain op 1~20--3f 0~10--1f [4] ana dithring en
++	{0x33b6, 0x07},//gain0 when dcg off
++	{0x33b7, 0x07},//gain1 when dcg off
++	{0x33b8, 0x10},//sel0 when dcg off
++	{0x33b9, 0x10},//sel1 when dcg off
++	{0x33ba, 0x10},//sel2 when dcg off
++	{0x33bb, 0x07},//gain0 when dcg on
++	{0x33bc, 0x07},//gain1 when dcg on
++	{0x33bd, 0x14},//sel0 when dcg on
++	{0x33be, 0x14},//sel1 when dcg on
++	{0x33bf, 0x14},//sel2 when dcg on
++	{0x360f, 0x05},//[0] 3622 auto en
++	{0x367a, 0x40},//gain0
++	{0x367b, 0x40},//gain1
++	{0x3671, 0xf6},//sel0
++	{0x3672, 0x16},//sel1
++	{0x3673, 0x16},//sel2
++	{0x366e, 0x04},//[2] fine gain op 1~20--3f 0~10--1f
++	{0x3670, 0x4a},//[1] 3630 auto en, [3] 3633 auto en, [6] 363a auto en
++	{0x367c, 0x40},//gain0	3e08[5:2] 1000
++	{0x367d, 0x58},//gain1 3e08[5:2] 1011
++	{0x3674, 0xc8},//sel0
++	{0x3675, 0x54},//sel1
++	{0x3676, 0x18},//sel2
++	{0x367e, 0x40},//gain0	3e08[5:2] 1000
++	{0x367f, 0x58},//gain1	3e08[5:2] 1011
++	{0x3677, 0x22},//sel0
++	{0x3678, 0x53},//sel1
++	{0x3679, 0x55},//sel2
++	{0x36a0, 0x58},//gain0	3e08[5:2] 1011
++	{0x36a1, 0x78},//gain1	3e08[5:2] 1111
++	{0x3696, 0x83},//sel0
++	{0x3697, 0x87},//sel1
++	{0x3698, 0x9f},//sel2
++	{0x4837, 0x31},
++	{0x6000, 0x00},
++	{0x6002, 0x00},
++	{0x301c, 0x78},//close dvp
++	{0x3037, 0x44},//[3:0] pump div	range [10M,20M],sclk=81/2=40.5M,div=4-->sclk/4=10.125M,duty cycle-->even number
++	{0x3038, 0x44},//[7:4]ppump & [3:0]npump
++	{0x3632, 0x18},//[5:4]idac driver
++	{0x5785, 0x40},//black	point 1x
++	{0x4809, 0x01},//mipi first frame, lp status
++	{0x3637, 0x10},
++	{0x5000, 0x06},//dpc enable
++	{0x5780, 0x7f},//auto blc setting
++	{0x57a0, 0x00},	//gain0 = 2x	0x0740Ö�0x077f
++	{0x57a1, 0x74},
++	{0x57a2, 0x01},	//gain1 = 8x	0x1f40Ö�0x1f7f
++	{0x57a3, 0xf4},
++	{0x5781, 0x06},	//white	1x
++	{0x5782, 0x04},	//2x
++	{0x5783, 0x02},	//8x
++	{0x5784, 0x01},	//128x
++	{0x5785, 0x16},	//black	1x
++	{0x5786, 0x12},	//2x
++	{0x5787, 0x08},	//8x
++	{0x5788, 0x02},	//128x
++	{0x4501, 0xb4},//reduce bit
++	{0x3637, 0x20},
++	{0x4509, 0x20},//blc quantification	//20181206
++	{0x3364, 0x1d},//[4] fine gain op 1~20--3f 0~10--1f [4] ana dithring en
++	{0x33b6, 0x07},//gain0 when dcg off	gain<dcg
++	{0x33b7, 0x07},//gain1 when dcg off
++	{0x33b8, 0x10},//sel0 when dcg off
++	{0x33b9, 0x10},//sel1 when dcg off
++	{0x33ba, 0x10},//sel2 when dcg off
++	{0x33bb, 0x07},//gain0 when dcg on		gain>=dcg
++	{0x33bc, 0x07},//gain1 when dcg on
++	{0x33bd, 0x20},//sel0 when dcg on
++	{0x33be, 0x20},//sel1 when dcg on
++	{0x33bf, 0x20},//sel2 when dcg on
++	{0x360f, 0x05},//[0] 3622 auto en
++	{0x367a, 0x40},//gain0
++	{0x367b, 0x40},//gain1
++	{0x3671, 0xf6},//sel0
++	{0x3672, 0x16},//sel1
++	{0x3673, 0x16},//sel2
++	{0x366e, 0x04},//[2] fine gain op 1~20--3f 0~10--1f
++	{0x3670, 0x4a},//[1] 3630 auto en, [3] 3633 auto en, [6] 363a auto en
++	{0x367c, 0x40},//gain0	3e08[5:2] 1000
++	{0x367d, 0x58},//gain1 3e08[5:2] 1011
++	{0x3674, 0xc8},//sel0
++	{0x3675, 0x54},//sel1
++	{0x3676, 0x18},//sel2
++	{0x367e, 0x40},//gain0	3e08[5:2] 1000
++	{0x367f, 0x58},//gain1	3e08[5:2] 1011
++	{0x3677, 0x22},//sel0
++	{0x3678, 0x33},//sel1
++	{0x3679, 0x44},//sel2
++	{0x36a0, 0x58},//gain0	3e08[5:2] 1011
++	{0x36a1, 0x78},//gain1	3e08[5:2] 1111
++	{0x3696, 0x83},//sel0
++	{0x3697, 0x87},//sel1
++	{0x3698, 0x9f},//sel2
++	{0x3637, 0x17},//fullwell 8.6k
++	{0x331e, 0x11},
++	{0x331f, 0x21},//1d
++	{0x3303, 0x1c},	//[hl,to][1,1a,2e]
++	{0x3309, 0x3c},	//[hl,to][1,32,46]
++	{0x330a, 0x00},
++	{0x330b, 0xc8},	//[bs,to][1,a8,ec]
++	{0x3306, 0x68},	//[hl,bs][1,46,88]
++	{0x3200, 0x00},
++	{0x3201, 0x04},
++	{0x3202, 0x00},
++	{0x3203, 0x04},
++	{0x3204, 0x07},
++	{0x3205, 0x8b},
++	{0x3206, 0x04},
++	{0x3207, 0x43},
++	{0x3208, 0x07},
++	{0x3209, 0x80},
++	{0x320a, 0x04},
++	{0x320b, 0x38},
++	{0x3211, 0x04},
++	{0x3213, 0x04},
++	{0x3380, 0x1b},
++	{0x3341, 0x07},//3318[3:0] + 2
++	{0x3343, 0x03},//3318[3:0] -2
++	{0x3e25, 0x03},//blc dithering(analog fine gain)
++	{0x3e26, 0x40},
++	{0x3366, 0x70},//[60,78]
++	{0x3e00, 0x00},//max_exposure = vts*2-6;	min_exposure = 3;	20180712
++	{0x3e01, 0x95},
++	{0x3e02, 0xa0},
++	{0x3e03, 0x0b},//gain map 0x0b mode	gain=1x
++	{0x3e06, 0x00},
++	{0x3e07, 0x80},
++	{0x3e08, 0x03},
++	{0x3e09, 0x40},
++	{0x3905, 0xd8},
++	{0x36e9, 0x23},//enable pll1	20180830
++	{0x36f9, 0x05},//enable pll2	20180830
++	{0x0100, 0x01},
++
++	{SC2310_REG_DELAY, 10},
++	{SC2310_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list sc2310_init_regs_1920_1080_15fps_mipi_dol[] = {
++	{0x0103, 0x01},
++	{0x0100, 0x00},
++	{0x36e9, 0xa3},//bypass pll1	20180830
++	{0x36f9, 0x85},//bypass pll2	20180830
++	{0x4509, 0x10},
++	{0x4500, 0x39},
++	{0x3907, 0x00},
++	{0x3908, 0x44},
++	{0x3633, 0x87},
++	{0x3306, 0x7e},
++	{0x330b, 0x00},
++	{0x3635, 0x4c},
++	{0x330e, 0x7a},
++	{0x3302, 0x1f}, //3302 need be odd why????  3366  3302   3621
++	{0x3e01, 0x8c},
++	{0x3e02, 0x80},
++	{0x3e09, 0x1f},
++	{0x3e08, 0x3f},
++	{0x3e06, 0x03},
++	{0x337f, 0x03}, //new auto precharge  330e in 3372   [7:6] 11: close div_rst 00:open div_rst
++	{0x3368, 0x04},
++	{0x3369, 0x00},
++	{0x336a, 0x00},
++	{0x336b, 0x00},
++	{0x3367, 0x08},
++	{0x330e, 0x30},
++	{0x3320, 0x06}, // New ramp offset timing
++	{0x3326, 0x00},
++	{0x331e, 0x11},
++	{0x331f, 0x21},
++	{0x3303, 0x20},
++	{0x3309, 0x30},
++	{0x4501, 0xc4},
++	{0x3e06, 0x00},
++	{0x3e08, 0x03},
++	{0x3e09, 0x10},
++	{0x3366, 0x7c}, // div_rst gap
++	{0x3622, 0x02},
++	{0x3633, 0x63},
++	{0x3038, 0x88},
++	{0x3635, 0x45},
++	{0x363b, 0x04},
++	{0x363c, 0x06},
++	{0x363d, 0x05},
++	{0x3633, 0x23},
++	{0x3301, 0x10},
++	{0x3306, 0x58},
++	{0x3622, 0x06},//blksun
++	{0x3631, 0x88},
++	{0x3630, 0x38},
++	{0x3633, 0x22},
++	{0x3018, 0x33},//[7:5] lane_num-1
++	{0x3031, 0x0c},//[3:0] bitmode
++	{0x3037, 0x40},//[6:5] bitsel  40:12bit
++	{0x3001, 0xFE},//[0] c_y
++	{0x4603, 0x00},//[0] data_fifo mipi mode
++	{0x4837, 0x35},//[7:0] pclk period * 2
++	{0x36e9, 0x83},
++	{0x36eb, 0x0f},
++	{0x36ec, 0x1f},
++	{0x303f, 0x01},
++	{0x330b, 0x20},
++	{0x3640, 0x00},
++	{0x3308, 0x10},
++	{0x3637, 0x0a},
++	{0x3e09, 0x20}, //3f for 2x fine gain
++	{0x363b, 0x08},
++	{0x3637, 0x09}, // ADC range: 14.8k fullwell  blc target : 0.9k   output fullwell: 13.9k (5fps 27C  linear fullwell is 14.5K)
++	{0x3638, 0x14},
++	{0x3636, 0x65},
++	{0x3907, 0x01},
++	{0x3908, 0x01},
++	{0x3320, 0x01}, //ramp
++	{0x331e, 0x15},
++	{0x331f, 0x25},
++	{0x3366, 0x80},
++	{0x3634, 0x34},
++	{0x57a4, 0xf0}, //default c0,
++	{0x3635, 0x41}, //fpn
++	{0x3e02, 0x30}, //minimum exp 3? debug
++	{0x3333, 0x30}, //col fpn  G >br  ?
++	{0x331b, 0x83},
++	{0x3334, 0x40},
++	{0x3306, 0x6c},
++	{0x3638, 0x17},
++	{0x330a, 0x01},
++	{0x330b, 0x14},
++	{0x3302, 0x10},
++	{0x3308, 0x08},
++	{0x3303, 0x18},
++	{0x3309, 0x18},
++	{0x331e, 0x11},
++	{0x331f, 0x11},
++	{0x3f00, 0x0d}, //[2]   hts/2-4
++	{0x3f04, 0x02},
++	{0x3f05, 0x22},
++	{0x3622, 0xe6},
++	{0x3633, 0x22},
++	{0x3630, 0xc8},
++	{0x3301, 0x10},
++	{0x36e9, 0xa3},
++	{0x36eb, 0x0b},
++	{0x36ec, 0x0f},
++	{0x3638, 0x27},
++	{0x33aa, 0x00}, //power save mode
++	{0x3624, 0x02},
++	{0x3621, 0xac},
++	{0x4509, 0x40},
++	{0x391e, 0x00},
++	{0x391f, 0xc0},
++	{0x3635, 0x45},
++	{0x336c, 0x40},
++	{0x3621, 0xae},
++	{0x3623, 0x08},
++	{0x36fa, 0xad}, //charge pump
++	{0x3634, 0x44},
++	{0x3621, 0xac}, //fifo delay
++	{0x4500, 0x59},
++	{0x3623, 0x18}, //for more grp rdout setup margin
++	{0x3f08, 0x04},
++	{0x3f00, 0x0d}, //[2]   hts/2-4-{3f08}
++	{0x3f04, 0x02}, //0321
++	{0x3f05, 0x1e}, //0321
++	{0x336c, 0x42}, //recover read timing
++	{0x5000, 0x06},//dpc enable
++	{0x5780, 0x7f},//auto blc setting
++	{0x57a0, 0x00},	//gain0 = 2x	0x0710Ö�0x071f
++	{0x57a1, 0x71},
++	{0x57a2, 0x01},	//gain1 = 8x	0x1f10Ö�0x1f1f
++	{0x57a3, 0xf1},
++	{0x5781, 0x06},	//white	1x
++	{0x5782, 0x04},	//2x
++	{0x5783, 0x02},	//8x
++	{0x5784, 0x01},	//128x
++	{0x5785, 0x16},	//black	1x
++	{0x5786, 0x12},	//2x
++	{0x5787, 0x08},	//8x
++	{0x5788, 0x02},	//128x
++	{0x3933, 0x28},
++	{0x3934, 0x0a},
++	{0x3940, 0x1b},
++	{0x3941, 0x40},
++	{0x3942, 0x08},
++	{0x3943, 0x0e},
++	{0x3208, 0x07},
++	{0x3209, 0x80},
++	{0x320a, 0x04},
++	{0x320b, 0x38},
++	{0x3211, 0x08},
++	{0x3213, 0x08},
++	{0x36e9, 0xa3},
++	{0x36ea, 0x77},
++	{0x36eb, 0x0b},
++	{0x36ec, 0x0f},
++	{0x36ed, 0x03},
++	{0x36f9, 0x85},
++	{0x36fa, 0x2d},
++	{0x36fb, 0x10},
++	{0x320c, 0x04},//hts=1125*2=2250
++	{0x320d, 0x65},
++	{0x320e, 0x04},//vts=1200
++	{0x320f, 0xb0},
++	{0x3235, 0x12},//vts*2-0x02
++	{0x3236, 0xbe},
++	{0x3f04, 0x02},//{0x320c,0x320d}/2-0x3f08-0x04
++	{0x3f05, 0x2a},
++	{0x3802, 0x00},
++	{0x3624, 0x47},
++	{0x3621, 0xac},
++	{0x36fa, 0x2f},
++	{0x3637, 0x08},
++	{0x3638, 0x25},
++	{0x3635, 0x40},
++	{0x363b, 0x08},
++	{0x363c, 0x05},
++	{0x363d, 0x05},
++	{0x3303, 0x1c},
++	{0x3309, 0x1c},
++	{0x3324, 0x02}, //falling edge: ramp_offset_en cover ramp_integ_en
++	{0x3325, 0x02},
++	{0x333d, 0x08}, //count_div_rst_width
++	{0x3314, 0x04},
++	{0x36fa, 0x28},
++	{0x3205, 0x93},
++	{0x3e14, 0xb0}, //[7]:1 ana fine gain double 20~3f
++	{0x3e1e, 0x35}, //[7]:1 open DCG function in 0x3e03=0x03 [6]:0 DCG >2   [2] 1: dig_fine_gain_en [1:0] max fine gain  01: 3f
++	{0x3e0e, 0x66}, //[7:3] fine gain to compsensate 2.4x DCGgain  5 : 2.3125x  6:2.375x  [2]:1 DCG gain between sa1gain 2~4  [1]:1 dcg gain in 0x3e08[5]
++	{0x3364, 0x1d},//[4] fine gain op 1~20--3f 0~10--1f [4] ana dithring en
++	{0x33b6, 0x07},//gain0 when dcg off
++	{0x33b7, 0x07},//gain1 when dcg off
++	{0x33b8, 0x10},//sel0 when dcg off
++	{0x33b9, 0x10},//sel1 when dcg off
++	{0x33ba, 0x10},//sel2 when dcg off
++	{0x33bb, 0x07},//gain0 when dcg on
++	{0x33bc, 0x07},//gain1 when dcg on
++	{0x33bd, 0x14},//sel0 when dcg on
++	{0x33be, 0x14},//sel1 when dcg on
++	{0x33bf, 0x14},//sel2 when dcg on
++	{0x360f, 0x05},//[0] 3622 auto en
++	{0x367a, 0x40},//gain0
++	{0x367b, 0x40},//gain1
++	{0x3671, 0xf6},//sel0
++	{0x3672, 0x16},//sel1
++	{0x3673, 0x16},//sel2
++	{0x366e, 0x04},//[2] fine gain op 1~20--3f 0~10--1f
++	{0x3670, 0x4a},//[1] 3630 auto en, [3] 3633 auto en, [6] 363a auto en
++	{0x367c, 0x40},//gain0  3e08[5:2] 1000
++	{0x367d, 0x58},//gain1 3e08[5:2] 1011
++	{0x3674, 0xc8},//sel0
++	{0x3675, 0x54},//sel1
++	{0x3676, 0x18},//sel2
++	{0x367e, 0x40},//gain0  3e08[5:2] 1000
++	{0x367f, 0x58},//gain1  3e08[5:2] 1011
++	{0x3677, 0x22},//sel0
++	{0x3678, 0x53},//sel1
++	{0x3679, 0x55},//sel2
++	{0x36a0, 0x58},//gain0  3e08[5:2] 1011
++	{0x36a1, 0x78},//gain1  3e08[5:2] 1111
++	{0x3696, 0x83},//sel0
++	{0x3697, 0x87},//sel1
++	{0x3698, 0x9f},//sel2
++	{0x4837, 0x31},
++	{0x6000, 0x00},
++	{0x6002, 0x00},
++	{0x301c, 0x78},//close dvp
++	{0x3037, 0x44},//[3:0] pump div	range [10M,20M],sclk=81/2=40.5M,div=4-->sclk/4=10.125M,duty cycle-->even number
++	{0x3038, 0x44},//[7:4]ppump & [3:0]npump
++	{0x3632, 0x18},//[5:4]idac driver
++	{0x5785, 0x40},//black	point 1x
++	{0x4809, 0x01},//mipi first frame, lp status
++	{0x3637, 0x10},
++	{0x5000, 0x06},//dpc enable
++	{0x5780, 0x7f},//auto blc setting
++	{0x57a0, 0x00},	//gain0 = 2x	0x0740Ö�0x077f
++	{0x57a1, 0x74},
++	{0x57a2, 0x01},	//gain1 = 8x	0x1f40Ö�0x1f7f
++	{0x57a3, 0xf4},
++	{0x5781, 0x06},	//white	1x
++	{0x5782, 0x04},	//2x
++	{0x5783, 0x02},	//8x
++	{0x5784, 0x01},	//128x
++	{0x5785, 0x16},	//black	1x
++	{0x5786, 0x12},	//2x
++	{0x5787, 0x08},	//8x
++	{0x5788, 0x02},	//128x
++	{0x4501, 0xb4},//reduce bit
++	{0x3637, 0x20},
++	{0x4509, 0x20},//blc quantification	//20181206
++	{0x3364, 0x1d},//[4] fine gain op 1~20--3f 0~10--1f [4] ana dithring en
++	{0x33b6, 0x07},//gain0 when dcg off	gain<dcg
++	{0x33b7, 0x07},//gain1 when dcg off
++	{0x33b8, 0x10},//sel0 when dcg off
++	{0x33b9, 0x10},//sel1 when dcg off
++	{0x33ba, 0x10},//sel2 when dcg off
++	{0x33bb, 0x07},//gain0 when dcg on		gain>=dcg
++	{0x33bc, 0x07},//gain1 when dcg on
++	{0x33bd, 0x20},//sel0 when dcg on
++	{0x33be, 0x20},//sel1 when dcg on
++	{0x33bf, 0x20},//sel2 when dcg on
++	{0x360f, 0x05},//[0] 3622 auto en
++	{0x367a, 0x40},//gain0
++	{0x367b, 0x40},//gain1
++	{0x3671, 0xf6},//sel0
++	{0x3672, 0x16},//sel1
++	{0x3673, 0x16},//sel2
++	{0x366e, 0x04},//[2] fine gain op 1~20--3f 0~10--1f
++	{0x3670, 0x4a},//[1] 3630 auto en, [3] 3633 auto en, [6] 363a auto en
++	{0x367c, 0x40},//gain0  3e08[5:2] 1000
++	{0x367d, 0x58},//gain1 3e08[5:2] 1011
++	{0x3674, 0xc8},//sel0
++	{0x3675, 0x54},//sel1
++	{0x3676, 0x18},//sel2
++	{0x367e, 0x40},//gain0  3e08[5:2] 1000
++	{0x367f, 0x58},//gain1  3e08[5:2] 1011
++	{0x3677, 0x22},//sel0
++	{0x3678, 0x33},//sel1
++	{0x3679, 0x44},//sel2
++	{0x36a0, 0x58},//gain0  3e08[5:2] 1011
++	{0x36a1, 0x78},//gain1  3e08[5:2] 1111
++	{0x3696, 0x9f},//sel0
++	{0x3697, 0x9f},//sel1
++	{0x3698, 0x9f},//sel2
++	{0x3637, 0x17},//fullwell 8.6k
++	{0x331e, 0x11},
++	{0x331f, 0x21},//1d
++	{0x3303, 0x1c},	//[hl,to][1,1a,2e]
++	{0x3309, 0x3c},	//[hl,to][1,32,46]
++	{0x330a, 0x00},
++	{0x330b, 0xc8},	//[bs,to][1,a8,ec]
++	{0x3306, 0x68},	//[hl,bs][1,46,88]
++	{0x3200, 0x00},
++	{0x3201, 0x04},
++	{0x3202, 0x00},
++	{0x3203, 0x04},
++	{0x3204, 0x07},
++	{0x3205, 0x8b},
++	{0x3206, 0x04},
++	{0x3207, 0x43},
++	{0x3208, 0x07},
++	{0x3209, 0x80},
++	{0x320a, 0x04},
++	{0x320b, 0x38},
++	{0x3211, 0x04},
++	{0x3213, 0x04},
++	{0x3380, 0x1b},
++	{0x3341, 0x07},//3318[3:0] + 2
++	{0x3343, 0x03},//3318[3:0] -2
++	{0x3e25, 0x03},//blc dithering(analog fine gain)
++	{0x3e26, 0x40},
++	{0x3366, 0x70},//[60,78]
++	{0x4816, 0x51},//bit[4]
++	{0x3220, 0x51},//bit[6]
++	{0x4602, 0x0f},//bit[3:0]
++	{0x33c0, 0x05},//bit[2]
++	{0x6000, 0x06},
++	{0x6002, 0x06},
++	/* {0x320e, 0x1a},//double vts */
++	/* {0x320f, 0x60}, */
++	{0x320e, 0x12},//double vts
++	{0x320f, 0x60},
++	{0x3202, 0x00},//x_start must be 0x00
++	{0x3203, 0x00},
++	{0x3206, 0x04},//1088	activeBoard=4
++	{0x3207, 0x3f},
++	{0x3e00, 0x01},//max long exposure = 0x103e
++	{0x3e01, 0x19},
++	{0x3e02, 0xe0},
++	{0x3e04, 0x11},//max short exposure = 0x104
++	{0x3e05, 0x80},
++	{0x3e23, 0x01},//max long exp : max short exp <= 16:1
++	{0x3e24, 0x1a},
++	{0x3e03, 0x0b},//gain map 0x0b mode	gain=1x
++	{0x3e06, 0x00},
++	{0x3e07, 0x80},
++	{0x3e08, 0x03},
++	{0x3e09, 0x40},
++	{0x3905, 0xd8},
++	{0x36e9, 0x23},//enable pll1	20180830
++	{0x36f9, 0x05},//enable pll2	20180830
++	{0x0100, 0x01},
++	{SC2310_REG_DELAY, 10},
++	{SC2310_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list sc2310_init_regs_1920_1080_25fps_mipi[] = {
++	{0x0103, 0x01},
++	{0x0100, 0x00},
++	{0x36e9, 0xa3},//bypass pll1
++	{0x36f9, 0x85},//bypass pll2
++	{0x337f, 0x03},
++	{0x3368, 0x04},
++	{0x3369, 0x00},
++	{0x336a, 0x00},
++	{0x336b, 0x00},
++	{0x3367, 0x08},
++	{0x330e, 0x30},
++	{0x3326, 0x00},
++	{0x3631, 0x88},
++	{0x3018, 0x33},
++	{0x3031, 0x0c},
++	{0x3001, 0xfe},
++	{0x4603, 0x00},
++	{0x303f, 0x01},
++	{0x3640, 0x00},
++	{0x3636, 0x65},
++	{0x3907, 0x01},
++	{0x3908, 0x01},
++	{0x3320, 0x01},
++	{0x3366, 0x70},
++	{0x57a4, 0xf0},
++	{0x3333, 0x30},
++	{0x331b, 0x83},
++	{0x3334, 0x40},
++	{0x3302, 0x10},
++	{0x3308, 0x08},
++	{0x3622, 0xe6},
++	{0x3633, 0x22},
++	{0x3630, 0xc8},
++	{0x3301, 0x10},
++	{0x33aa, 0x00},
++	{0x391e, 0x00},
++	{0x391f, 0xc0},
++	{0x3634, 0x44},
++	{0x4500, 0x59},
++	{0x3623, 0x18},
++	{0x3f08, 0x04},
++	{0x3f00, 0x0d},
++	{0x336c, 0x42},
++	{0x3933, 0x28},
++	{0x3934, 0x0a},
++	{0x3940, 0x1b},
++	{0x3941, 0x40},
++	{0x3942, 0x08},
++	{0x3943, 0x0e},
++	{0x36ea, 0x77},
++	{0x36eb, 0x0b},
++	{0x36ec, 0x0f},
++	{0x36ed, 0x03},
++	{0x36fb, 0x10},
++	{0x320c, 0x04},//1125
++	{0x320d, 0x65},
++	{0x320e, 0x05},//1440
++	{0x320f, 0xa0},
++	{0x3235, 0x09},
++	{0x3236, 0x5e},
++	{0x3f04, 0x02},
++	{0x3f05, 0x2a},
++	{0x3802, 0x00},
++	{0x3624, 0x47},
++	{0x3621, 0xac},
++	{0x3638, 0x25},
++	{0x3635, 0x40},
++	{0x363b, 0x08},
++	{0x363c, 0x05},
++	{0x363d, 0x05},
++	{0x3324, 0x02},
++	{0x3325, 0x02},
++	{0x333d, 0x08},
++	{0x3314, 0x04},
++	{0x36fa, 0x28},
++	{0x3e14, 0xb0},
++	{0x3e1e, 0x35},
++	{0x3e0e, 0x66},
++	{0x4837, 0x31},
++	{0x6000, 0x00},
++	{0x6002, 0x00},
++	{0x301c, 0x78},
++	{0x3037, 0x44},
++	{0x3038, 0x44},
++	{0x3632, 0x18},
++	{0x4809, 0x01},
++	{0x5000, 0x06},
++	{0x5780, 0x7f},
++	{0x57a0, 0x00},
++	{0x57a1, 0x74},
++	{0x57a2, 0x01},
++	{0x57a3, 0xf4},
++	{0x5781, 0x06},
++	{0x5782, 0x04},
++	{0x5783, 0x02},
++	{0x5784, 0x01},
++	{0x5785, 0x16},
++	{0x5786, 0x12},
++	{0x5787, 0x08},
++	{0x5788, 0x02},
++	{0x4501, 0xb4},
++	{0x4509, 0x20},
++	{0x3364, 0x1d},
++	{0x33b6, 0x07},
++	{0x33b7, 0x07},
++	{0x33b8, 0x10},
++	{0x33b9, 0x10},
++	{0x33ba, 0x10},
++	{0x33bb, 0x07},
++	{0x33bc, 0x07},
++	{0x33bd, 0x20},
++	{0x33be, 0x20},
++	{0x33bf, 0x20},
++	{0x360f, 0x05},
++	{0x367a, 0x40},
++	{0x367b, 0x40},
++	{0x3671, 0xf6},
++	{0x3672, 0x16},
++	{0x3673, 0x16},
++	{0x366e, 0x04},
++	{0x3670, 0x4a},
++	{0x367c, 0x40},
++	{0x367d, 0x58},
++	{0x3674, 0xc8},
++	{0x3675, 0x54},
++	{0x3676, 0x18},
++	{0x367e, 0x40},
++	{0x367f, 0x58},
++	{0x3677, 0x22},
++	{0x3678, 0x33},
++	{0x3679, 0x44},
++	{0x36a0, 0x58},
++	{0x36a1, 0x78},
++	{0x3696, 0x83},
++	{0x3697, 0x87},
++	{0x3698, 0x9f},
++	{0x3637, 0x17},
++	{0x331e, 0x11},
++	{0x331f, 0x21},
++	{0x3303, 0x1c},
++	{0x3309, 0x3c},
++	{0x330a, 0x00},
++	{0x330b, 0xc8},
++	{0x3306, 0x68},
++	{0x3200, 0x00},
++	{0x3201, 0x04},
++	{0x3202, 0x00},
++	{0x3203, 0x04},
++	{0x3204, 0x07},
++	{0x3205, 0x8b},
++	{0x3206, 0x04},
++	{0x3207, 0x43},
++	{0x3208, 0x07},
++	{0x3209, 0x80},
++	{0x320a, 0x04},
++	{0x320b, 0x38},
++	{0x3211, 0x04},
++	{0x3213, 0x04},
++	{0x3380, 0x1b},
++	{0x3341, 0x07},
++	{0x3343, 0x03},
++	{0x3e25, 0x03},
++	{0x3e26, 0x40},
++	{0x3e00, 0x00},
++	{0x3e01, 0x95},
++	{0x3e02, 0xa0},
++	{0x3e03, 0x0b},
++	{0x3e06, 0x00},
++	{0x3e07, 0x80},
++	{0x3e08, 0x03},
++	{0x3e09, 0x40},
++	{0x3905, 0xd8},
++	{0x36e9, 0x23},
++	{0x36f9, 0x05},
++	{0x0100, 0x01},
++	{SC2310_REG_DELAY, 10},
++	{SC2310_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list sc2310_init_regs_1920_1080_25fps_dvp[] = {
++	{0x0103, 0x01},
++	{0x0100, 0x00},
++	{0x36e9, 0xa3},//bypass pll1
++	{0x36f9, 0x85},//bypass pll2
++	{0x337f, 0x03},
++	{0x3368, 0x04},
++	{0x3369, 0x00},
++	{0x336a, 0x00},
++	{0x336b, 0x00},
++	{0x3367, 0x08},
++	{0x330e, 0x30},
++	{0x3326, 0x00},
++	{0x3631, 0x88},
++	{0x3640, 0x00},
++	{0x3636, 0x65},
++	{0x3907, 0x01},
++	{0x3908, 0x01},
++	{0x3320, 0x01},
++	{0x3366, 0x70},
++	{0x57a4, 0xf0},
++	{0x3333, 0x30},
++	{0x331b, 0x83},
++	{0x3334, 0x40},
++	{0x3302, 0x10},
++	{0x3308, 0x08},
++	{0x3622, 0xe6},
++	{0x3633, 0x22},
++	{0x3630, 0xc8},
++	{0x3301, 0x10},
++	{0x33aa, 0x00},
++	{0x391e, 0x00},
++	{0x391f, 0xc0},
++	{0x3634, 0x44},
++	{0x4500, 0x59},
++	{0x3623, 0x18},
++	{0x3f08, 0x04},
++	{0x3f00, 0x0d},
++	{0x336c, 0x42},
++	{0x3933, 0x28},
++	{0x3934, 0x0a},
++	{0x3940, 0x1b},
++	{0x3941, 0x40},
++	{0x3942, 0x08},
++	{0x3943, 0x0e},
++	{0x36ea, 0x77},
++	{0x36eb, 0x0b},
++	{0x36ec, 0x0f},
++	{0x36ed, 0x03},
++	{0x36fb, 0x10},
++	{0x320c, 0x04},
++	{0x320d, 0x65},
++	{0x320e, 0x05},
++	{0x320f, 0xa0},
++	{0x3235, 0x09},
++	{0x3236, 0x5e},
++	{0x3f04, 0x02},
++	{0x3f05, 0x2a},
++	{0x3802, 0x00},
++	{0x3624, 0x47},
++	{0x3621, 0xac},
++	{0x3019, 0xff},
++	{0x301c, 0xb4},
++	{0x3018, 0x1f},
++	{0x3031, 0x0a},
++	{0x3001, 0xff},
++	{0x4603, 0x01},
++	{0x4837, 0x36},
++	{0x303f, 0x81},
++	{0x3d08, 0x01},
++	{0x3638, 0x25},
++	{0x3635, 0x40},
++	{0x363b, 0x08},
++	{0x363c, 0x05},
++	{0x363d, 0x05},
++	{0x3641, 0x01},
++	{0x3324, 0x02},
++	{0x3325, 0x02},
++	{0x333d, 0x08},
++	{0x3314, 0x04},
++	{0x36fa, 0x28},
++	{0x3e14, 0xb0},
++	{0x3e1e, 0x35},
++	{0x3e0e, 0x66},
++	{0x6000, 0x00},
++	{0x6002, 0x00},
++	{0x3037, 0x24},
++	{0x3038, 0x44},
++	{0x3632, 0x18},
++	{0x4809, 0x01},
++	{0x5000, 0x06},
++	{0x5780, 0x7f},
++	{0x57a0, 0x00},
++	{0x57a1, 0x74},
++	{0x57a2, 0x01},
++	{0x57a3, 0xf4},
++	{0x5781, 0x06},
++	{0x5782, 0x04},
++	{0x5783, 0x02},
++	{0x5784, 0x01},
++	{0x5785, 0x16},
++	{0x5786, 0x12},
++	{0x5787, 0x08},
++	{0x5788, 0x02},
++	{0x4501, 0xb4},
++	{0x4509, 0x20},
++	{0x3364, 0x1d},
++	{0x33b6, 0x07},
++	{0x33b7, 0x07},
++	{0x33b8, 0x10},
++	{0x33b9, 0x10},
++	{0x33ba, 0x10},
++	{0x33bb, 0x07},
++	{0x33bc, 0x07},
++	{0x33bd, 0x20},
++	{0x33be, 0x20},
++	{0x33bf, 0x20},
++	{0x360f, 0x05},
++	{0x367a, 0x40},
++	{0x367b, 0x40},
++	{0x3671, 0xf6},
++	{0x3672, 0x16},
++	{0x3673, 0x16},
++	{0x366e, 0x04},
++	{0x3670, 0x4a},
++	{0x367c, 0x40},
++	{0x367d, 0x58},
++	{0x3674, 0xc8},
++	{0x3675, 0x54},
++	{0x3676, 0x18},
++	{0x367e, 0x40},
++	{0x367f, 0x58},
++	{0x3677, 0x22},
++	{0x3678, 0x33},
++	{0x3679, 0x44},
++	{0x36a0, 0x58},
++	{0x36a1, 0x78},
++	{0x3696, 0x83},
++	{0x3697, 0x87},
++	{0x3698, 0x9f},
++	{0x3637, 0x17},
++	{0x331e, 0x11},
++	{0x331f, 0x21},
++	{0x3303, 0x1c},
++	{0x3309, 0x3c},
++	{0x330a, 0x00},
++	{0x330b, 0xc8},
++	{0x3306, 0x68},
++	{0x3200, 0x00},
++	{0x3201, 0x04},
++	{0x3202, 0x00},
++	{0x3203, 0x04},
++	{0x3204, 0x07},
++	{0x3205, 0x8b},
++	{0x3206, 0x04},
++	{0x3207, 0x43},
++	{0x3208, 0x07},
++	{0x3209, 0x80},
++	{0x320a, 0x04},
++	{0x320b, 0x38},
++	{0x3211, 0x04},
++	{0x3213, 0x04},
++	{0x3380, 0x1b},
++	{0x3341, 0x07},
++	{0x3343, 0x03},
++	{0x3e25, 0x03},
++	{0x3e26, 0x40},
++	{0x3e00, 0x00},
++	{0x3e01, 0x95},
++	{0x3e02, 0xa0},
++	{0x3e03, 0x0b},
++	{0x3e06, 0x00},
++	{0x3e07, 0x80},
++	{0x3e08, 0x03},
++	{0x3e09, 0x40},
++	{0x3905, 0xd8},
++	{0x36e9, 0x23},
++	{0x36f9, 0x05},
++	{0x0100, 0x01},
++	{SC2310_REG_DELAY, 10},
++	{SC2310_REG_END, 0x00},	/* END MARKER */
++};
++
++
++
++
++/*
++ * the part of driver was fixed.
++ */
++
++static struct regval_list sc2310_stream_on_dvp[] = {
++	{0x0100, 0x01},
++	{SC2310_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list sc2310_stream_off_dvp[] = {
++	{0x0100, 0x00},
++	{SC2310_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list sc2310_stream_on_mipi[] = {
++	{0x0100,0x01},
++	{SC2310_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list sc2310_stream_off_mipi[] = {
++	{0x0100, 0x00},
++	{SC2310_REG_END, 0x00},	/* END MARKER */
++};
++
++static int sc2310_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct sc2310_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++
++	int ret = 0;
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int sc2310_write(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char value)
++{
++	struct sc2310_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3] = {(reg>>8)&0xff, reg&0xff, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 3,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++#if 0
++static int sc2310_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != SC2310_REG_END) {
++		if (vals->reg_num == SC2310_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = sc2310_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++#endif
++
++/*
++ * Write a list of register settings; ff/ff stops the process.
++ */
++static int sc2310_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != SC2310_REG_END) {
++		if (vals->reg_num == SC2310_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = sc2310_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int sc2310_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc2310_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(10);
++	}
++	return 0;
++}
++
++static int sc2310_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc2310_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++	} else {
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, !info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++	}
++	return 0;
++}
++
++static int sc2310_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc2310_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = sc2310_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++
++static int sc2310_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++	ret = sc2310_read(sd, 0x3107, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != SC2310_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = sc2310_read(sd, 0x3108, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != SC2310_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	return 0;
++}
++
++static struct sc2310_win_size sc2310_win_sizes[] = {
++	{
++		.width				= 1920,
++		.height				= 1080,
++		.sensor_info.fps				= 15 << 16 | 1,
++		.sensor_info.wdr_en				= 0,
++		.sensor_info.mipi_cfg.clk			= 400,
++		.sensor_info.mipi_cfg.twidth		= 1920,
++		.sensor_info.mipi_cfg.theight		= 1080,
++		.sensor_info.mipi_cfg.mipi_mode		= SENSOR_MIPI_OTHER_MODE,
++		.sensor_info.mipi_cfg.mipi_vcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_hcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3y	= 0,
++		.sensor_info.mipi_cfg.hcrop_diff_en		= 0,
++		.sensor_info.mipi_cfg.line_sync_mode	= 0,
++		.sensor_info.mipi_cfg.work_start_flag	= 0,
++		.sensor_info.mipi_cfg.data_type_en		= 0,
++		.sensor_info.mipi_cfg.data_type_value	= RAW12,
++		.sensor_info.mipi_cfg.del_start		= 1,
++		.sensor_info.mipi_cfg.sensor_frame_mode	= TX_SENSOR_WDR_2_FRAME_MODE,
++		.sensor_info.mipi_cfg.sensor_fid_mode	= 0,
++		.sensor_info.mipi_cfg.sensor_mode		= TX_SENSOR_DEFAULT_MODE,
++		.sensor_info.mipi_cfg.sensor_csi_fmt		= TX_SENSOR_RAW12,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR12_1X12,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= sc2310_init_regs_1920_1080_15fps_mipi,
++	},//[0]
++	{
++		.width				= 1920,
++		.height				= 1080,
++		.sensor_info.fps				= 25 << 16 | 1,
++		.sensor_info.wdr_en				= 0,
++		.sensor_info.mipi_cfg.clk			= 400,
++		.sensor_info.mipi_cfg.twidth		= 1920,
++		.sensor_info.mipi_cfg.theight		= 1080,
++		.sensor_info.mipi_cfg.mipi_mode		= SENSOR_MIPI_OTHER_MODE,
++		.sensor_info.mipi_cfg.mipi_vcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_hcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3y	= 0,
++		.sensor_info.mipi_cfg.hcrop_diff_en		= 0,
++		.sensor_info.mipi_cfg.line_sync_mode	= 0,
++		.sensor_info.mipi_cfg.work_start_flag	= 0,
++		.sensor_info.mipi_cfg.data_type_en		= 0,
++		.sensor_info.mipi_cfg.data_type_value	= RAW12,
++		.sensor_info.mipi_cfg.del_start		= 0,
++		.sensor_info.mipi_cfg.sensor_frame_mode	= TX_SENSOR_DEFAULT_FRAME_MODE,
++		.sensor_info.mipi_cfg.sensor_fid_mode	= 0,
++		.sensor_info.mipi_cfg.sensor_mode		= TX_SENSOR_DEFAULT_MODE,
++		.sensor_info.mipi_cfg.sensor_csi_fmt		= TX_SENSOR_RAW12,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR12_1X12,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= sc2310_init_regs_1920_1080_25fps_mipi,
++	},//[1]
++	{
++		.width				= 1920,
++		.height				= 1080,
++		.sensor_info.fps				= 25 << 16 | 1,
++		.sensor_info.wdr_en				= 0,
++		.sensor_info.mipi_cfg.clk			= 400,
++		.sensor_info.mipi_cfg.twidth		= 1920,
++		.sensor_info.mipi_cfg.theight		= 1080,
++		.sensor_info.mipi_cfg.mipi_mode		= SENSOR_MIPI_OTHER_MODE,
++		.sensor_info.mipi_cfg.mipi_vcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_hcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3y	= 0,
++		.sensor_info.mipi_cfg.hcrop_diff_en		= 0,
++		.sensor_info.mipi_cfg.line_sync_mode	= 0,
++		.sensor_info.mipi_cfg.work_start_flag	= 0,
++		.sensor_info.mipi_cfg.data_type_en		= 0,
++		.sensor_info.mipi_cfg.data_type_value	= RAW12,
++		.sensor_info.mipi_cfg.del_start		= 0,
++		.sensor_info.mipi_cfg.sensor_frame_mode	= TX_SENSOR_DEFAULT_FRAME_MODE,
++		.sensor_info.mipi_cfg.sensor_fid_mode	= 0,
++		.sensor_info.mipi_cfg.sensor_mode		= TX_SENSOR_DEFAULT_MODE,
++		.sensor_info.mipi_cfg.sensor_csi_fmt		= TX_SENSOR_RAW12,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR12_1X12,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= sc2310_init_regs_1920_1080_15fps_mipi_dol,
++	},//[2]
++	{
++		.width				= 1920,
++		.height				= 1080,
++		.sensor_info.fps				= 25 << 16 | 1,
++		.sensor_info.wdr_en				= 0,
++		.sensor_info.mipi_cfg.clk			= 400,
++		.sensor_info.mipi_cfg.twidth		= 1920,
++		.sensor_info.mipi_cfg.theight		= 1080,
++		.sensor_info.mipi_cfg.mipi_mode		= SENSOR_MIPI_OTHER_MODE,
++		.sensor_info.mipi_cfg.mipi_vcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_hcomp_en		= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start1y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start2y	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start3y	= 0,
++		.sensor_info.mipi_cfg.hcrop_diff_en		= 0,
++		.sensor_info.mipi_cfg.line_sync_mode	= 0,
++		.sensor_info.mipi_cfg.work_start_flag	= 0,
++		.sensor_info.mipi_cfg.data_type_en		= 0,
++		.sensor_info.mipi_cfg.data_type_value	= RAW12,
++		.sensor_info.mipi_cfg.del_start		= 0,
++		.sensor_info.mipi_cfg.sensor_frame_mode	= TX_SENSOR_DEFAULT_FRAME_MODE,
++		.sensor_info.mipi_cfg.sensor_fid_mode	= 0,
++		.sensor_info.mipi_cfg.sensor_mode		= TX_SENSOR_DEFAULT_MODE,
++		.sensor_info.mipi_cfg.sensor_csi_fmt		= TX_SENSOR_RAW12,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR12_1X12,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= sc2310_init_regs_1920_1080_25fps_mipi_dol,
++	},//[3]
++	{
++		.width				= 1920,
++		.height				= 1080,
++		.sensor_info.fps		= 25 << 16 | 1,
++		.sensor_info.wdr_en		= 1,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR12_1X12,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= sc2310_init_regs_1920_1080_25fps_dvp,
++	},//[4]
++};
++
++static int sc2310_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int sc2310_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct sc2310_format_struct *ovfmt;
++	struct sc2310_win_size *wsize;
++	struct sc2310_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int sc2310_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct sc2310_info *info = to_state(sd);
++	struct sc2310_win_size *wsize = info->win;
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = wsize->width;
++	fmt->height = wsize->height;
++	fmt->code = wsize->mbus_code;
++	fmt->colorspace = wsize->colorspace;
++	*(unsigned int *)fmt->reserved = &wsize->sensor_info;
++
++	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int sc2310_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc2310_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc2310_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc2310_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int sc2310_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int sc2310_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(sc2310_again_lut); i++) {
++		lut = &sc2310_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(sc2310_again_lut); i++) {
++		lut = &sc2310_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return -EINVAL;
++}
++
++static int sc2310_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	struct sc2310_info *info = to_state(sd);
++	unsigned char v = 0;
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++
++	return ret;
++}
++
++static int sc2310_g_again_short(struct v4l2_subdev *sd, __s32 *value)
++{
++	struct sc2310_info *info = to_state(sd);
++	unsigned char v = 0;
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++	return ret;
++}
++/*set analog gain db value, map value to sensor register.*/
++static int sc2310_s_again(struct v4l2_subdev *sd, int again)
++{
++	struct sc2310_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int ret = 0;
++	if(again < info->again->minimum || again > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(again);
++	} 
++
++	ret = sc2310_write(sd, 0x3e09, (unsigned char)(reg_value & 0xff));
++	ret += sc2310_write(sd, 0x3e08, (unsigned char)(reg_value >> 8 & 0x3f));
++
++	return ret;
++}
++
++static int sc2310_s_again_short(struct v4l2_subdev *sd, int again)
++{
++	struct sc2310_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int ret = 0;
++	if(again < info->again->minimum || again > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(again);
++	} 
++
++	ret = sc2310_write(sd, 0x3e13, (unsigned char)(reg_value & 0xff));
++	ret += sc2310_write(sd, 0x3e12, (unsigned char)(reg_value >> 8 & 0x3f));
++
++	return ret;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int sc2310_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc2310_s_exp(struct v4l2_subdev *sd, int value)
++{
++	struct sc2310_info *info = to_state(sd);
++	int ret = 0;
++	unsigned int expo = 0;
++#ifdef SC2310_WDR_EN
++	expo = value*4;
++	ret += sc2310_write(sd, 0x3e00, (unsigned char)((expo >> 12) & 0x0f));
++	ret += sc2310_write(sd, 0x3e01, (unsigned char)((expo >> 4) & 0xff));
++	ret += sc2310_write(sd, 0x3e02, (unsigned char)((expo & 0x0f) << 4));
++	if (value < 0x50) {
++		ret += sc2310_write(sd, 0x3812, 0x00);
++		ret += sc2310_write(sd, 0x3314, 0x14);
++		ret += sc2310_write(sd, 0x3812, 0x30);
++	} else if(value > 0xa0){
++		ret += sc2310_write(sd, 0x3812, 0x00);
++		ret += sc2310_write(sd, 0x3314, 0x04);
++		ret += sc2310_write(sd, 0x3812, 0x30);
++	}
++#else
++	expo = value*2;
++	ret += sc2310_write(sd, 0x3e00, (unsigned char)((expo >> 12) & 0x0f));
++	ret += sc2310_write(sd, 0x3e01, (unsigned char)((expo >> 4) & 0xff));
++	ret += sc2310_write(sd, 0x3e02, (unsigned char)((expo & 0x0f) << 4));
++	if (value < 0x50) {
++		ret += sc2310_write(sd, 0x3812, 0x00);
++		ret += sc2310_write(sd, 0x3314, 0x14);
++		ret += sc2310_write(sd, 0x3812, 0x30);
++	} else if(value > 0xa0){
++		ret += sc2310_write(sd, 0x3812, 0x00);
++		ret += sc2310_write(sd, 0x3314, 0x04);
++		ret += sc2310_write(sd, 0x3812, 0x30);
++	}
++#endif
++
++	return ret;
++}
++
++static int sc2310_s_exp_short(struct v4l2_subdev *sd, int value)
++{
++	struct sc2310_info *info = to_state(sd);
++	int ret = 0;
++	unsigned int expo = 0;
++	ret += sc2310_write(sd, 0x3e04, (unsigned char)((expo >> 4) & 0xff));
++	ret += sc2310_write(sd, 0x3e05, (unsigned char)((expo & 0x0f) << 4));
++	if (value < 0x50) {
++		ret += sc2310_write(sd, 0x3812, 0x00);
++		ret += sc2310_write(sd, 0x3314, 0x14);
++		ret += sc2310_write(sd, 0x3812, 0x30);
++	}
++	else if(value > 0xa0){
++		ret += sc2310_write(sd, 0x3812, 0x00);
++		ret += sc2310_write(sd, 0x3314, 0x04);
++		ret += sc2310_write(sd, 0x3812, 0x30);
++	}
++
++	return ret;
++}
++
++static int sc2310_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct sc2310_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return sc2310_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return sc2310_g_again(sd, &info->again->val);
++	case V4L2_CID_USER_ANALOG_GAIN_SHORT:
++		return sc2310_g_again_short(sd, &info->again_short->val);
++	}
++	return -EINVAL;
++}
++
++static int sc2310_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct sc2310_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return sc2310_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return sc2310_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return sc2310_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return sc2310_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* sc2310_s_gain turns off auto gain */
++			return sc2310_s_gain(sd, info->gain->val);
++		}
++		return sc2310_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return sc2310_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return sc2310_s_again(sd, ctrl->val);
++	case V4L2_CID_USER_ANALOG_GAIN_SHORT:
++		return sc2310_s_again_short(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return sc2310_s_exp(sd, ctrl->val);
++	case V4L2_CID_USER_EXPOSURE_SHORT:
++		return sc2310_s_exp_short(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops sc2310_ctrl_ops = {
++	.s_ctrl = sc2310_s_ctrl,
++	.g_volatile_ctrl = sc2310_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int sc2310_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = sc2310_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 2;
++	return ret;
++}
++
++static int sc2310_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	sc2310_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int sc2310_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct sc2310_info *info = to_state(sd);
++	int ret = 0;
++
++	if (enable) {
++		sc2310_power_init_seq(info);
++		sc2310_init(sd, 1);
++		ret = sc2310_write_array(sd, sc2310_stream_on_mipi);
++		printk("--------------------->>>>>sc2310 stream on\n");
++
++	}
++	else {
++		ret = sc2310_write_array(sd, sc2310_stream_off_mipi);
++		printk("--------------------->>>>>>>>sc2310 stream off\n");
++	}
++	return ret;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops sc2310_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = sc2310_g_register,
++	.s_register = sc2310_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops sc2310_video_ops = {
++	.s_stream = sc2310_s_stream,
++};
++
++static const struct v4l2_subdev_pad_ops sc2310_pad_ops = {
++	//.enum_frame_interval = sc2310_enum_frame_interval,
++	//.num_frame_size = sc2310_enum_frame_size,
++	//.enum_mbus_code = sc2310_enum_mbus_code,
++	.set_fmt = sc2310_set_fmt,
++	.get_fmt = sc2310_get_fmt,
++};
++
++static const struct v4l2_subdev_ops sc2310_ops = {
++	.core = &sc2310_core_ops,
++	.video = &sc2310_video_ops,
++	.pad = &sc2310_pad_ops,
++};
++
++void sc2310_power_init_seq(struct sc2310_info *info)
++{
++	*(volatile unsigned int*)0xb0010100 = 0x1;  //set gpio power domain 1.8v
++	gpio_direction_output(4,0);
++	udelay(50);
++	if(info->pwen.pin == 3){
++		gpio_direction_output(info->pwen.pin,info->pwen.active_level);
++		udelay(50);
++	}
++	gpio_direction_output(info->pwen.pin,info->pwen.active_level);
++	udelay(50);
++
++	gpio_direction_output(info->reset.pin,!info->reset.active_level);
++	msleep(40);
++	gpio_direction_output(info->reset.pin,info->reset.active_level);
++	msleep(40);
++	gpio_direction_output(info->reset.pin,!info->reset.active_level);
++	msleep(40);
++
++	gpio_direction_output(info->pwdn.pin,info->pwdn.active_level);
++	msleep(10);
++	gpio_direction_output(info->pwdn.pin,!info->pwdn.active_level);
++	msleep(10);
++	gpio_direction_output(info->pwdn.pin,info->pwdn.active_level);
++	msleep(10);
++}
++/* ----------------------------------------------------------------------- */
++
++static int sc2310_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_fract tpf;
++	struct v4l2_subdev *sd;
++	struct sc2310_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++	unsigned long rate;
++	struct v4l2_ctrl_config cfg = {0};
++	int mclk_index = -1;
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutp-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutp.pin = gpio;
++		info->ircutp.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutn.pin = gpio;
++		info->ircutn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,pwen-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->pwen.pin = gpio;
++		info->pwen.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,pwdn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->pwdn.pin = gpio;
++		info->pwdn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	sc2310_power_init_seq(info);
++	v4l2_i2c_subdev_init(sd, client, &sc2310_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++#if 1
++
++	char id_div[9];
++	char id_mux[9];
++	printk("%s:%d\n", __func__, __LINE__);
++	of_property_read_u32(client->dev.of_node, "ingenic,mclk", &mclk_index);
++	if(mclk_index == 0) {
++		memcpy(id_div, "div_cim0", sizeof(id_div));
++		memcpy(id_mux, "mux_cim0", sizeof(id_mux));
++	} else if(mclk_index == 1) {
++		memcpy(id_div, "div_cim1", sizeof(id_div));
++		memcpy(id_mux, "mux_cim1", sizeof(id_mux));
++	} else if(mclk_index == 2) {
++		memcpy(id_div, "div_cim2", sizeof(id_div));
++		memcpy(id_mux, "mux_cim2", sizeof(id_mux));
++	} else
++		printk("Unkonwn mclk index\n");
++
++
++	info->clk = v4l2_clk_get(&client->dev, id_div);
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++#endif
++
++
++	//sc2310_reset(sd, 1);
++#if 1
++	/* Make sure it's an sc2310 */
++	ret = sc2310_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an sc2310 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++
++	/*IRCUT ctl 0:off 1:on*/
++	//sc2310_ircut(sd, 0);
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &sc2310_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &sc2310_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &sc2310_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &sc2310_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &sc2310_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &sc2310_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 356010, 1, 10000);
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &sc2310_ctrl_ops,
++			V4L2_CID_EXPOSURE, 2, 0x5a0 - 3, 1, 1000);
++
++#if 1
++	cfg.ops = &sc2310_ctrl_ops;
++	cfg.id = V4L2_CID_USER_EXPOSURE_SHORT;
++	cfg.name = "expo short";
++	cfg.type = V4L2_CTRL_TYPE_INTEGER;
++	cfg.min = 5;
++	cfg.max = 0x5a0 - 3;
++	cfg.step = 1;
++	cfg.def = 1000;
++	info->exposure_short = v4l2_ctrl_new_custom(&info->hdl, &cfg, NULL);
++
++	memset(&cfg, 0, sizeof(cfg));
++	cfg.ops = &sc2310_ctrl_ops;
++	cfg.id = V4L2_CID_USER_ANALOG_GAIN_SHORT;
++	cfg.name = "analog gain short";
++	cfg.type = V4L2_CTRL_TYPE_INTEGER;
++	cfg.min = 0;
++	cfg.max = 356010;
++	cfg.step = 1;
++	cfg.def = 10000;
++	info->again_short = v4l2_ctrl_new_custom(&info->hdl, &cfg, NULL);
++#endif
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->win = &sc2310_win_sizes[1];
++
++	sc2310_init(sd, 1);
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "sc2310 Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int sc2310_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct sc2310_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id sc2310_id[] = {
++	{ "sc2310", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, sc2310_id);
++
++static const struct of_device_id sc2310_of_match[] = {
++	{.compatible = "smartsens,sc2310", },
++	{},
++};
++MODULE_DEVICE_TABLE(of,	sc2310_of_match);
++
++
++static struct i2c_driver sc2310_driver = {
++	.driver = {
++		.name	= "sc2310",
++		.of_match_table = of_match_ptr(sc2310_of_match),
++	},
++	.probe		= sc2310_probe,
++	.remove		= sc2310_remove,
++	.id_table	= sc2310_id,
++};
++
++module_i2c_driver(sc2310_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for SmartSens sc2310 sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/Kconfig b/module_drivers/drivers/media/i2c/ingenic-isp/Kconfig
+new file mode 100644
+index 000000000..50509b160
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/Kconfig
+@@ -0,0 +1,92 @@
++comment "ingenic-isp camera sensor drivers"
++
++
++config INGENIC_ISP_CAMERA_OV4689
++	tristate "ov4689 camera support"
++	depends on VIDEO_INGENIC_ISP && I2C
++	help
++	  This is a ingenic-isp camera driver for the OmniVision OV4689 sensor
++
++config INGENIC_ISP_CAMERA_SC2232H
++	tristate "sc2232h camera support"
++	depends on VIDEO_INGENIC_ISP && I2C
++	help
++	  This is a ingenic-isp camera driver for the OmniVision sc2232h sensor
++
++config INGENIC_ISP_CAMERA_OV2735B
++	tristate "ov2735 camera DVP interface support"
++	depends on VIDEO_INGENIC_ISP && I2C
++	help
++	  This is a ingenic-isp camera driver for the OmniVision OV2735 sensor DVP interface
++
++config INGENIC_ISP_CAMERA_OV2735A
++	tristate "ov2735 camera MIPI interface support"
++	depends on VIDEO_INGENIC_ISP && I2C
++	help
++	  This is a ingenic-isp camera driver for the OmniVision OV2735 sensor MIPI interface
++
++config INGENIC_ISP_CAMERA_GC1054
++	tristate "gc1054 camera MIPI interface support"
++	depends on VIDEO_INGENIC_ISP && I2C
++	help
++	  This is a ingenic-isp camera driver for the Galaxyc gc1054 sensor MIPI interface
++
++config INGENIC_ISP_CAMERA_AR0144
++	tristate "ar0144 camera support"
++	depends on VIDEO_INGENIC_ISP && I2C
++	help
++	  This is a ingenic-isp camera driver for the Onsemi ar0144 sensor
++
++config INGENIC_ISP_CAMERA_AR0234
++	tristate "ar0234 camera support"
++	depends on VIDEO_INGENIC_ISP && I2C
++	help
++	  This is a ingenic-isp camera driver for the Onsemi ar0234 sensor
++
++config INGENIC_ISP_CAMERA_OV7251
++	tristate "ov7251 camera MIPI interface support"
++	depends on VIDEO_INGENIC_ISP && I2C
++	help
++	  This is a ingenic-isp camera driver for the OmniVision OV7251 sensor MIPI interface
++
++config INGENIC_ISP_CAMERA_SC031GS
++	tristate "sc031gs camera MIPI interface support"
++	depends on VIDEO_INGENIC_ISP && I2C
++	help
++	  This is a ingenic-isp camera driver for the SmartSens sc031gs sensor MIPI interface
++
++config INGENIC_ISP_CAMERA_OV6710
++	tristate "ov6710 camera MIPI interface support"
++	depends on VIDEO_INGENIC_ISP && I2C
++	help
++	  This is a ingenic-isp camera driver for the OmniVision OV6710 sensor MIPI interface
++
++config INGENIC_ISP_CAMERA_CISADC
++	tristate "CIS ADC Simulator"
++	depends on VIDEO_INGENIC_ISP && I2C
++	help
++	  This is a ingenic-isp camera driver for CIS ADC
++
++config INGENIC_ISP_CAMERA_GC2093
++	tristate "gc2093 camera MIPI interface support"
++	depends on VIDEO_INGENIC_ISP && I2C
++	help
++	  This is a ingenic-isp camera driver for the OmniVision GC2093 sensor MIPI interface
++
++config INGENIC_ISP_CAMERA_GM8914_GM8913_GC2093
++	tristate "GM8914 GM8913 gc2093 camera support"
++	depends on VIDEO_INGENIC_ISP && I2C
++	help
++	  This is a ingenic-isp camera driver for the zhenxin gm8914/gm8913 gc2093 sensor
++
++config INGENIC_ISP_CAMERA_IMX335
++	tristate "IMX335 camera MIPI interface support"
++	depends on VIDEO_INGENIC_ISP && I2C
++	help
++	  This is a ingenic-isp camera driver for IMX335 sensor MIPI interface
++
++config INGENIC_ISP_CAMERA_SC230AI
++	tristate "SC230AI camera MIPI interface support"
++	depends on VIDEO_INGENIC_ISP && I2C
++	help
++	  This is a ingenic-isp camera driver for SC230AI sensor MIPI interface
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/Makefile b/module_drivers/drivers/media/i2c/ingenic-isp/Makefile
+new file mode 100644
+index 000000000..edf286b57
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/Makefile
+@@ -0,0 +1,17 @@
++obj-$(CONFIG_INGENIC_ISP_CAMERA_OV4689) +=	ov4689.o
++obj-$(CONFIG_INGENIC_ISP_CAMERA_SC2232H) += sc2232h.o
++obj-$(CONFIG_INGENIC_ISP_CAMERA_OV2735B) +=	ov2735b.o
++obj-$(CONFIG_INGENIC_ISP_CAMERA_OV2735A) +=	ov2735a.o
++obj-$(CONFIG_INGENIC_ISP_CAMERA_GC1054) +=	gc1054.o
++obj-$(CONFIG_INGENIC_ISP_CAMERA_AR0144) +=	ar0144.o
++obj-$(CONFIG_INGENIC_ISP_CAMERA_AR0234) +=	ar0234.o
++obj-$(CONFIG_INGENIC_ISP_CAMERA_OV7251) +=	ov7251.o
++obj-$(CONFIG_INGENIC_ISP_CAMERA_SC031GS) +=	sc031gs.o
++obj-$(CONFIG_INGENIC_ISP_CAMERA_OV6710) +=	ov6710.o
++obj-$(CONFIG_INGENIC_ISP_CAMERA_CISADC) +=	cisadc.o
++obj-$(CONFIG_INGENIC_ISP_CAMERA_GC2093) +=  	gc2093.o
++obj-$(CONFIG_INGENIC_ISP_CAMERA_GM8914_GM8913_GC2093) +=	gm8914_gm8913_gc2093.o
++obj-$(CONFIG_INGENIC_ISP_CAMERA_IMX335) +=  	imx335.o
++obj-$(CONFIG_INGENIC_ISP_CAMERA_SC230AI) +=  	sc230ai.o
++
++ccflags-y += -I$(srctree)/module_drivers/drivers/media/platform/ingenic-isp/
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/ar0144.c b/module_drivers/drivers/media/i2c/ingenic-isp/ar0144.c
+new file mode 100644
+index 000000000..4294895bc
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/ar0144.c
+@@ -0,0 +1,998 @@
++/*
++ * A V4L2 driver for OmniVision AR0144 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++
++#include <isp-sensor.h>
++
++#define AR0144_CHIP_ID_H	(0x03)
++#define AR0144_CHIP_ID_L	(0x56)
++#define AR0144_CHIP_ID          (0x0356)
++#define AR0144_CHIP_ID_REG      (0x3000)
++
++#define AR0144_REG_END		0xffff
++#define AR0144_REG_DELAY	0xfffe
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct ar0144_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct ar0144_gpio {
++	int pin;
++	int active_level;
++};
++
++
++struct ar0144_supply{
++	struct regulator *pwen;
++	struct regulator *avdd;
++	struct regulator *dvdd;
++	struct regulator *dovdd;
++};
++
++struct ar0144_info {
++	struct ar0144_supply supply;
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct ar0144_win_size *win;
++
++	struct ar0144_gpio reset;
++	struct ar0144_gpio expo;
++	struct ar0144_gpio oe;
++	struct ar0144_gpio pwen;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++struct again_lut ar0144_again_lut[] = {
++    { 0x0, 0 },
++    { 0x1, 2794 },
++    { 0x2, 6397 },
++    { 0x3, 9011 },
++    { 0x4, 12388 },
++    { 0x5, 16447 },
++    { 0x6, 19572 },
++    { 0x7, 23340 },
++    { 0x8, 26963 },
++    { 0x9, 31135 },
++    { 0xa, 35780 },
++    { 0xb, 39588 },
++    { 0xc, 44438 },
++    { 0xd, 49051 },
++    { 0xe, 54517 },
++    { 0xf, 59685 },
++    { 0x10, 65536 },
++    { 0x12, 71490 },
++    { 0x14, 78338 },
++    { 0x16, 85108 },
++    { 0x18, 92854 },
++    { 0x1a, 100992 },
++    { 0x1c, 109974 },
++    { 0x1e, 120053 },
++    { 0x20, 131072 },
++    { 0x22, 137247 },
++    { 0x24, 143667 },
++    { 0x26, 150644 },
++    { 0x28, 158212 },
++    { 0x2a, 166528 },
++    { 0x2c, 175510 },
++    { 0x2e, 185457 },
++    { 0x30, 196608 },
++    { 0x32, 202783 },
++    { 0x34, 209203 },
++    { 0x36, 216276 },
++    { 0x38, 223748 },
++    { 0x3a, 232064 },
++    { 0x3c, 241046 },
++    { 0x3e, 250993 },
++    { 0x40, 262144 },
++};
++
++static inline struct ar0144_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct ar0144_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct ar0144_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned short value;
++};
++
++static struct regval_list ar0144_init_regs_720p_60fps_mipi[] = {
++	//mipibps 444
++	//pclk 74.00
++	//hts:0x5D0  VTS 0x338
++	//again default 0x3060 = 0x0010
++	//expo 0x3012 = 0x01F3
++	//[ar0144_720P_60FPS]
++//	{ AR0144_REG_DELAY, 200},
++	{ 0x301A, 0x00D9 }, // RESET_REGISTER
++	{ AR0144_REG_DELAY, 200},
++	{ 0x301A, 0x3058 }, // RESET_REGISTER
++	{ AR0144_REG_DELAY, 100},
++	{ 0x3F4C, 0x003F }, // PIX_DEF_1D_DDC_LO_DEF
++	{ 0x3F4E, 0x0018 }, // PIX_DEF_1D_DDC_HI_DEF
++	{ 0x3F50, 0x17DF }, // PIX_DEF_1D_DDC_EDGE
++	{ 0x30B0, 0x0028 }, // DIGITAL_TEST
++	{ AR0144_REG_DELAY, 200},
++	{ 0x3ED6, 0x3CB5 }, // DAC_LD_10_11
++	{ 0x3ED8, 0x8765 }, // DAC_LD_12_13
++	{ 0x3EDA, 0x8888 }, // DAC_LD_14_15
++	{ 0x3EDC, 0x97FF }, // DAC_LD_16_17
++	{ 0x3EF8, 0x6522 }, // DAC_LD_44_45
++	{ 0x3EFA, 0x2222 }, // DAC_LD_46_47
++	{ 0x3EFC, 0x6666 }, // DAC_LD_48_49
++	{ 0x3F00, 0xAA05 }, // DAC_LD_52_53
++	{ 0x3EE2, 0x180E }, // DAC_LD_22_23
++	{ 0x3EE4, 0x0808 }, // DAC_LD_24_25
++	{ 0x3EEA, 0x2A09 }, // DAC_LD_30_31
++	{ 0x3060, 0x0010 }, // ANALOG_GAIN
++	{ 0x30FE, 0x00A8 }, // NOISE_PEDESTAL
++	{ 0x3092, 0x00CF }, // ROW_NOISE_CONTROL
++	{ 0x3268, 0x0030 }, // SEQUENCER_CONTROL
++	{ 0x3786, 0x0006 }, // DIGITAL_CTRL_1
++	{ 0x3F4A, 0x0F70 }, // DELTA_DK_PIX_THRES
++	{ 0x306E, 0x4810 }, // DATAPATH_SELECT
++	{ 0x3064, 0x1802 }, // SMIA_TEST
++	{ 0x3EF6, 0x804D }, // DAC_LD_42_43
++	{ 0x3180, 0xC08F }, // DELTA_DK_CONTROL
++	{ 0x30BA, 0x7623 }, // DIGITAL_CTRL
++	{ 0x3176, 0x0480 }, // DELTA_DK_ADJUST_GREENR
++	{ 0x3178, 0x0480 }, // DELTA_DK_ADJUST_RED
++	{ 0x317A, 0x0480 }, // DELTA_DK_ADJUST_BLUE
++	{ 0x317C, 0x0480 }, // DELTA_DK_ADJUST_GREENB
++	{ 0x302A, 0x0006 }, // VT_PIX_CLK_DIV
++	{ 0x302C, 0x0001 }, // VT_SYS_CLK_DIV
++	{ 0x302E, 0x0004 }, // PRE_PLL_CLK_DIV
++	{ 0x3030, 0x004A }, // PLL_MULTIPLIER
++	{ 0x3036, 0x000C }, // OP_PIX_CLK_DIV
++	{ 0x3038, 0x0001 }, // OP_SYS_CLK_DIV
++	{ 0x30B0, 0x0028 }, // DIGITAL_TEST
++	{ AR0144_REG_DELAY, 100},
++	{ 0x31AE, 0x0202 }, // SERIAL_FORMAT
++	{ 0x31AC, 0x0C0C }, // DATA_FORMAT_BITS
++	{ 0x31B0, 0x0042 }, // FRAME_PREAMBLE
++	{ 0x31B2, 0x002E }, // LINE_PREAMBLE
++	{ 0x31B4, 0x2633 }, // MIPI_TIMING_0
++	{ 0x31B6, 0x210E }, // MIPI_TIMING_1
++	{ 0x31B8, 0x20C7 }, // MIPI_TIMING_2
++#if 0
++	{ 0x31BA, 0x0105 }, // MIPI_TIMING_3
++	{ 0x31BC, 0x0004 }, // MIPI_TIMING_4
++#else
++	{ 0x31BA, 0x01a5 }, // MIPI_TIMING_3
++	{ 0x31BC, 0x8004 }, // MIPI_TIMING_4
++#endif
++	{ 0x3002, 0x0028 }, // Y_ADDR_START
++	{ 0x3004, 0x0004 }, // X_ADDR_START
++	{ 0x3006, 0x02F8 }, // Y_ADDR_END
++	{ 0x3008, 0x0503 }, // X_ADDR_END
++	{ 0x300A, 0x0338 }, // FRAME_LENGTH_LINES
++	{ 0x300C, 0x05D0 }, // LINE_LENGTH_PCK
++//	{ 0x3012, 0x0064 }, // COARSE_INTEGRATION_TIME
++	{ 0x3012, 0x01F3 }, // COARSE_INTEGRATION_TIME
++	{ 0x30A2, 0x0001 }, // X_ODD_INC
++	{ 0x30A6, 0x0001 }, // Y_ODD_INC
++	{ 0x3040, 0x0000 }, // READ_MODE
++	{ 0x3064, 0x1882 }, // SMIA_TEST
++	{ 0x3064, 0x1802 }, // SMIA_TEST
++	{ 0x3028, 0x0010 }, // ROW_SPEED
++//	{ 0x301A, 0x005C }, // RESET_REGISTER stream_on
++	{AR0144_REG_END, 0x00},/* END MARKER */
++};
++
++/*
++ * the part of driver was fixed.
++ */
++
++static struct regval_list ar0144_stream_on[] = {
++//	{0x301A, 0x19CC},
++	{0x301A, 0x005C},
++	{AR0144_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list ar0144_stream_off[] = {
++//	{0x301A, 0x19C8},
++	{0x301A, 0x0058},
++	{AR0144_REG_END, 0x00},	/* END MARKER */
++};
++
++static int ar0144_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct ar0144_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 2,
++			.buf	= value,
++		}
++	};
++	int ret = 0;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ar0144_write(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned short value)
++{
++	struct ar0144_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[4] = {reg >> 8, reg & 0xff, value >> 8, value & 0xff};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 4,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ar0144_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val[2];
++	uint16_t value;
++	while (vals->reg_num != AR0144_REG_END) {
++		if (vals->reg_num == AR0144_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ar0144_read(sd, vals->reg_num, val);
++			if (ret < 0)
++				return ret;
++		}
++		vals->value=(val[0]<<8)|val[1];
++		vals++;
++	}
++	return 0;
++}
++
++/*
++ * Write a list of register settings; ff/ff stops the process.
++ */
++static int ar0144_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != AR0144_REG_END) {
++		if (vals->reg_num == AR0144_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ar0144_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int ar0144_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct ar0144_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(20);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(20);
++	}
++	return 0;
++}
++
++static int ar0144_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct ar0144_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = ar0144_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++
++static int ar0144_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v[2] = {0};
++	int ret;
++	ret = ar0144_read(sd, 0x3000, v);
++
++	if (ret < 0)
++		return ret;
++
++	if (v[0] != AR0144_CHIP_ID_H)
++		return -ENODEV;
++
++	if (v[1] != AR0144_CHIP_ID_L)
++		return -ENODEV;
++
++	return 0;
++}
++
++
++static struct ar0144_win_size ar0144_win_sizes[] = {
++	{
++		.sensor_info.mipi_cfg.twidth		= 1280,
++		.sensor_info.mipi_cfg.theight		= 720,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.fps			= 60 << 16 | 1,
++
++		.width		= 1280,
++		.height		= 720,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR12_1X12,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ar0144_init_regs_720p_60fps_mipi,
++	},
++};
++
++static int ar0144_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_AR0144_FMTS)
++		return -EINVAL;
++
++	code->code = ar0144_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int ar0144_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct ar0144_format_struct *ovfmt;
++	struct ar0144_win_size *wsize;
++	struct ar0144_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int ar0144_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct ar0144_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	*(unsigned int *)fmt->reserved = &info->win->sensor_info;
++
++
++//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int ar0144_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ar0144_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ar0144_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ar0144_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int ar0144_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int ar0144_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ar0144_again_lut); i++) {
++		lut = &ar0144_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ar0144_again_lut); i++) {
++		lut = &ar0144_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return 0;
++}
++
++static int ar0144_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	struct ar0144_info *info = to_state(sd);
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++
++	ret = ar0144_read(sd, 0x3509, &reg_val);
++
++	*value = regval_to_again(reg_val);
++
++	return ret;
++}
++/*set analog gain db value, map value to sensor register.*/
++static int ar0144_s_again(struct v4l2_subdev *sd, int value)
++{
++	struct ar0144_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int ret = 0;
++	int i;
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(value);
++	}
++
++	ret += ar0144_write(sd, 0x3060, reg_value);
++	if (ret < 0)
++		return ret;
++
++	return ret;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int ar0144_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ar0144_s_exp(struct v4l2_subdev *sd, int value)
++{
++	struct ar0144_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = ar0144_write(sd, 0x3012, value);
++
++	return ret;
++}
++
++static int ar0144_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ar0144_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return ar0144_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ar0144_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int ar0144_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ar0144_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return ar0144_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return ar0144_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return ar0144_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return ar0144_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* ar0144_s_gain turns off auto gain */
++			return ar0144_s_gain(sd, info->gain->val);
++		}
++		return ar0144_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return ar0144_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ar0144_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return ar0144_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops ar0144_ctrl_ops = {
++	.s_ctrl = ar0144_s_ctrl,
++	.g_volatile_ctrl = ar0144_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ar0144_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = ar0144_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int ar0144_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	ar0144_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int ar0144_power_t(struct v4l2_subdev *sd, int on)
++{
++	struct ar0144_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	int ret;
++
++	info->supply.pwen  = devm_regulator_get_optional(&client->dev, "pwen");
++	if (IS_ERR(info->supply.pwen)){
++			if ((PTR_ERR(info->supply.pwen) == -EPROBE_DEFER))
++				return -EPROBE_DEFER;
++			printk("No ar0144 vdd regulator found\n");
++	}
++
++	if (!IS_ERR(info->supply.pwen)){
++		if(on){
++			ret = regulator_enable(info->supply.pwen);
++			if (ret)
++				dev_err(&client->dev, "ar0144 pwen supply disable failed\n");
++		}else{
++			ret = regulator_disable(info->supply.pwen);
++			if (ret)
++				dev_err(&client->dev, "ar0144 pwen supply disable failed\n");
++		}
++	}else{
++		dev_err(&client->dev, "ar0144 vdd supply IS_ERR failed\n");
++	}
++
++	return ret;
++}
++
++int ar0144_power(struct v4l2_subdev *sd, int on)
++{
++	struct ar0144_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	int ret;
++
++	/*double sensor,eg halley5_camera v1.0*/
++	ar0144_power_t(sd,on);
++
++	info->supply.avdd  = devm_regulator_get_optional(&client->dev, "avdd");
++	info->supply.dvdd  = devm_regulator_get_optional(&client->dev, "dvdd");
++	info->supply.dovdd = devm_regulator_get_optional(&client->dev, "dovdd");
++
++	if (IS_ERR(info->supply.avdd)||IS_ERR(info->supply.dvdd)
++		||IS_ERR(info->supply.dovdd)) {
++			if ((PTR_ERR(info->supply.avdd) == -EPROBE_DEFER)
++				||(PTR_ERR(info->supply.avdd) == -EPROBE_DEFER)
++					||(PTR_ERR(info->supply.avdd) == -EPROBE_DEFER))
++				return -EPROBE_DEFER;
++			printk("No ar0144 vdd regulator found\n");
++	}
++
++	if ((!IS_ERR(info->supply.avdd))&&(!IS_ERR(info->supply.avdd))
++			&&(!IS_ERR(info->supply.avdd)))  {
++		if(on){
++			ret = regulator_enable(info->supply.avdd);
++			ret = regulator_enable(info->supply.dvdd);
++			ret = regulator_enable(info->supply.dovdd);
++			if (ret)
++			   dev_err(&client->dev, "ar0144 vdd supply disable failed\n");
++		}
++		else{
++			ret = regulator_disable(info->supply.avdd);
++			ret = regulator_disable(info->supply.dvdd);
++			ret = regulator_disable(info->supply.dovdd);
++			if (ret)
++			    dev_err(&client->dev, "ar0144 vdd supply disable failed\n");
++		}
++	}else{
++		dev_err(&client->dev, "ar0144 vdd supply IS_ERR failed\n");
++	}
++
++	return ret;
++}
++
++int ar0144_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct ar0144_info *info = to_state(sd);
++	int ret = 0;
++	struct regval_list *vals;
++
++	if (enable) {
++		ret = ar0144_write_array(sd, ar0144_stream_on);
++		pr_debug("ar0144 stream on\n");
++	}
++	else {
++		ret = ar0144_write_array(sd, ar0144_stream_off);
++		pr_debug("ar0144 stream off\n");
++	}
++	return ret;
++}
++
++
++int ar0144_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct ar0144_info *info = to_state(sd);
++	if(info->win->fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops ar0144_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = ar0144_g_register,
++	.s_register = ar0144_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops ar0144_video_ops = {
++	.s_stream = ar0144_s_stream,
++	.g_frame_interval = ar0144_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops ar0144_pad_ops = {
++	//.enum_frame_interval = ar0144_enum_frame_interval,
++	//.num_frame_size = ar0144_enum_frame_size,
++	//.enum_mbus_code = ar0144_enum_mbus_code,
++	.set_fmt = ar0144_set_fmt,
++	.get_fmt = ar0144_get_fmt,
++};
++
++static const struct v4l2_subdev_ops ar0144_ops = {
++	.core = &ar0144_core_ops,
++	.video = &ar0144_video_ops,
++	.pad = &ar0144_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int ar0144_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_fract tpf;
++	struct v4l2_subdev *sd;
++	struct ar0144_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,expo-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->expo.pin = gpio;
++		info->expo.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,oe-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->oe.pin = gpio;
++		info->oe.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,pwen-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->pwen.pin = gpio;
++		info->pwen.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++
++	v4l2_i2c_subdev_init(sd, client, &ar0144_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	ar0144_power(sd, 1);
++	msleep(30);
++
++	/*clk*/
++	info->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++
++	ar0144_reset(sd, 1);
++#if 1
++	/* Make sure it's an ar0144 */
++	ret = ar0144_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an ar0144 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++
++	/*IRCUT ctl 0:off 1:on*/
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &ar0144_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &ar0144_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &ar0144_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &ar0144_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &ar0144_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &ar0144_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 1, 262144, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &ar0144_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1520 - 4, 1, 1000);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->win = &ar0144_win_sizes[0];
++
++	ar0144_init(sd, 1);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "ar0144 Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int ar0144_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ar0144_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id ar0144_id[] = {
++	{ "ar0144", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ar0144_id);
++
++static const struct of_device_id ar0144_of_match[] = {
++	{.compatible = "onsemi,ar0144", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov2640_of_match);
++
++int ar0144_suspend(struct device *dev)
++{
++        struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++        struct v4l2_subdev *sd = i2c_get_clientdata(client);
++        struct ar0144_info *info = to_state(sd);
++	int ret=0;
++
++	ar0144_power(sd, 0);
++	v4l2_clk_disable(info->clk);
++        return 0;
++}
++
++int ar0144_resume(struct device *dev)
++{
++	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ar0144_info *info = to_state(sd);
++	int ret=0;
++
++	ar0144_power(sd, 1);
++	v4l2_clk_enable(info->clk);
++	ar0144_reset(sd, 1);
++	ar0144_init(sd, 1);
++	return 0;
++}
++
++const struct dev_pm_ops ar0144_pm =
++{
++        .suspend = ar0144_suspend,
++        .resume = ar0144_resume,
++};
++
++
++static struct i2c_driver ar0144_driver = {
++	.driver = {
++		.name	= "ar0144",
++		.of_match_table = of_match_ptr(ar0144_of_match),
++		.pm     = &ar0144_pm,
++	},
++	.probe		= ar0144_probe,
++	.remove		= ar0144_remove,
++	.id_table	= ar0144_id,
++};
++
++module_i2c_driver(ar0144_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for onsemi ar0144 sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/ar0234.c b/module_drivers/drivers/media/i2c/ingenic-isp/ar0234.c
+new file mode 100644
+index 000000000..d061d266e
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/ar0234.c
+@@ -0,0 +1,1183 @@
++/*
++ * A V4L2 driver for OmniVision AR0234 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++
++#include <isp-sensor.h>
++
++#define AR0234_CHIP_ID_H	(0x0a)
++#define AR0234_CHIP_ID_L	(0x56)
++#define AR0234_CHIP_ID          (0x0356)
++#define AR0234_CHIP_ID_REG      (0x3000)
++
++#define AR0234_REG_END		0xffff
++#define AR0234_REG_DELAY	0xfffe
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct ar0234_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct ar0234_gpio {
++	int pin;
++	int active_level;
++};
++
++struct ar0234_supply{
++	struct regulator *pwen;
++	struct regulator *shutdown;
++};
++
++struct ar0234_info {
++	struct ar0234_supply supply;
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct ar0234_win_size *win;
++
++	struct ar0234_gpio reset;
++	struct ar0234_gpio expo;
++	struct ar0234_gpio oe;
++	struct ar0234_gpio pwen;
++	struct ar0234_gpio shutdown;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++struct again_lut ar0234_again_lut[] = {
++    { 0x0, 0 },
++    { 0x1, 2794 },
++    { 0x2, 6397 },
++    { 0x3, 9011 },
++    { 0x4, 12388 },
++    { 0x5, 16447 },
++    { 0x6, 19572 },
++    { 0x7, 23340 },
++    { 0x8, 26963 },
++    { 0x9, 31135 },
++    { 0xa, 35780 },
++    { 0xb, 39588 },
++    { 0xc, 44438 },
++    { 0xd, 49051 },
++    { 0xe, 54517 },
++    { 0xf, 59685 },
++    { 0x10, 65536 },
++    { 0x12, 71490 },
++    { 0x14, 78338 },
++    { 0x16, 85108 },
++    { 0x18, 92854 },
++    { 0x1a, 100992 },
++    { 0x1c, 109974 },
++    { 0x1e, 120053 },
++    { 0x20, 131072 },
++    { 0x22, 137247 },
++    { 0x24, 143667 },
++    { 0x26, 150644 },
++    { 0x28, 158212 },
++    { 0x2a, 166528 },
++    { 0x2c, 175510 },
++    { 0x2e, 185457 },
++    { 0x30, 196608 },
++    { 0x32, 202783 },
++    { 0x34, 209203 },
++    { 0x36, 216276 },
++    { 0x38, 223748 },
++    { 0x3a, 232064 },
++    { 0x3c, 241046 },
++    { 0x3e, 250993 },
++    { 0x40, 262144 },
++};
++
++static inline struct ar0234_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct ar0234_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct ar0234_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned short value;
++};
++
++static struct regval_list ar0234_init_regs_1080p_60fps_mipi[] = {
++	/*
++	   [AR0234_MIPI_2Lane_1920x1080_10bits_24MCLK_891Mbps_60fps]
++	   ;load = seq
++	   load = PLL_settings
++	   load = Timing_settings
++	   [seq]
++	   */
++	{ AR0234_REG_DELAY, 200},
++	{ 0x301A, 0x00D9}, // RESET_REGISTER
++	{ AR0234_REG_DELAY, 200},
++	{ 0x3F4C, 0x121F}, // PIX_DEF_1D_DDC_LO_DEF
++	{ 0x3F4E, 0x121F}, // PIX_DEF_1D_DDC_HI_DEF
++	{ 0x3F50, 0x0B81}, // PIX_DEF_1D_DDC_EDGE
++	{ 0x31E0, 0x0003}, // PIX_DEF_ID
++	{ 0x31E0, 0x0003}, // PIX_DEF_ID
++	{ 0x30B0, 0x0028}, // DIGITAL_TEST
++	{ AR0234_REG_DELAY, 200},
++	{ 0x3088, 0x8000}, // SEQ_CTRL_PORT
++	{ 0x3086, 0xC1AE}, // SEQ_DATA_PORT
++	{ 0x3086, 0x327F}, // SEQ_DATA_PORT
++	{ 0x3086, 0x5780}, // SEQ_DATA_PORT
++	{ 0x3086, 0x272F}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7416}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7E13}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8000}, // SEQ_DATA_PORT
++	{ 0x3086, 0x307E}, // SEQ_DATA_PORT
++	{ 0x3086, 0xFF80}, // SEQ_DATA_PORT
++	{ 0x3086, 0x20C3}, // SEQ_DATA_PORT
++	{ 0x3086, 0xB00E}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8190}, // SEQ_DATA_PORT
++	{ 0x3086, 0x1643}, // SEQ_DATA_PORT
++	{ 0x3086, 0x1651}, // SEQ_DATA_PORT
++	{ 0x3086, 0x9D3E}, // SEQ_DATA_PORT
++	{ 0x3086, 0x9545}, // SEQ_DATA_PORT
++	{ 0x3086, 0x2209}, // SEQ_DATA_PORT
++	{ 0x3086, 0x3781}, // SEQ_DATA_PORT
++	{ 0x3086, 0x9016}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4316}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7F90}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8000}, // SEQ_DATA_PORT
++	{ 0x3086, 0x387F}, // SEQ_DATA_PORT
++	{ 0x3086, 0x1380}, // SEQ_DATA_PORT
++	{ 0x3086, 0x233B}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7F93}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4502}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8000}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7FB0}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8D66}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7F90}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8192}, // SEQ_DATA_PORT
++	{ 0x3086, 0x3C16}, // SEQ_DATA_PORT
++	{ 0x3086, 0x357F}, // SEQ_DATA_PORT
++	{ 0x3086, 0x9345}, // SEQ_DATA_PORT
++	{ 0x3086, 0x0280}, // SEQ_DATA_PORT
++	{ 0x3086, 0x007F}, // SEQ_DATA_PORT
++	{ 0x3086, 0xB08D}, // SEQ_DATA_PORT
++	{ 0x3086, 0x667F}, // SEQ_DATA_PORT
++	{ 0x3086, 0x9081}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8237}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4502}, // SEQ_DATA_PORT
++	{ 0x3086, 0x3681}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8044}, // SEQ_DATA_PORT
++	{ 0x3086, 0x1631}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4374}, // SEQ_DATA_PORT
++	{ 0x3086, 0x1678}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7B7D}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4502}, // SEQ_DATA_PORT
++	{ 0x3086, 0x450A}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7E12}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8180}, // SEQ_DATA_PORT
++	{ 0x3086, 0x377F}, // SEQ_DATA_PORT
++	{ 0x3086, 0x1045}, // SEQ_DATA_PORT
++	{ 0x3086, 0x0A0E}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7FD4}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8024}, // SEQ_DATA_PORT
++	{ 0x3086, 0x0E82}, // SEQ_DATA_PORT
++	{ 0x3086, 0x9CC2}, // SEQ_DATA_PORT
++	{ 0x3086, 0xAFA8}, // SEQ_DATA_PORT
++	{ 0x3086, 0xAA03}, // SEQ_DATA_PORT
++	{ 0x3086, 0x430D}, // SEQ_DATA_PORT
++	{ 0x3086, 0x2D46}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4316}, // SEQ_DATA_PORT
++	{ 0x3086, 0x5F16}, // SEQ_DATA_PORT
++	{ 0x3086, 0x530D}, // SEQ_DATA_PORT
++	{ 0x3086, 0x1660}, // SEQ_DATA_PORT
++	{ 0x3086, 0x401E}, // SEQ_DATA_PORT
++	{ 0x3086, 0x2904}, // SEQ_DATA_PORT
++	{ 0x3086, 0x2984}, // SEQ_DATA_PORT
++	{ 0x3086, 0x81E7}, // SEQ_DATA_PORT
++	{ 0x3086, 0x816F}, // SEQ_DATA_PORT
++	{ 0x3086, 0x1706}, // SEQ_DATA_PORT
++	{ 0x3086, 0x81E7}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7F81}, // SEQ_DATA_PORT
++	{ 0x3086, 0x5C0D}, // SEQ_DATA_PORT
++	{ 0x3086, 0x5754}, // SEQ_DATA_PORT
++	{ 0x3086, 0x495F}, // SEQ_DATA_PORT
++	{ 0x3086, 0x5305}, // SEQ_DATA_PORT
++	{ 0x3086, 0x5307}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4D2B}, // SEQ_DATA_PORT
++	{ 0x3086, 0xF810}, // SEQ_DATA_PORT
++	{ 0x3086, 0x164C}, // SEQ_DATA_PORT
++	{ 0x3086, 0x0755}, // SEQ_DATA_PORT
++	{ 0x3086, 0x562B}, // SEQ_DATA_PORT
++	{ 0x3086, 0xB82B}, // SEQ_DATA_PORT
++	{ 0x3086, 0x984E}, // SEQ_DATA_PORT
++	{ 0x3086, 0x1129}, // SEQ_DATA_PORT
++	{ 0x3086, 0x9460}, // SEQ_DATA_PORT
++	{ 0x3086, 0x5C09}, // SEQ_DATA_PORT
++	{ 0x3086, 0x5C1B}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4002}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4500}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4580}, // SEQ_DATA_PORT
++	{ 0x3086, 0x29B6}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7F80}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4004}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7F88}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4109}, // SEQ_DATA_PORT
++	{ 0x3086, 0x5C0B}, // SEQ_DATA_PORT
++	{ 0x3086, 0x29B2}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4115}, // SEQ_DATA_PORT
++	{ 0x3086, 0x5C03}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4105}, // SEQ_DATA_PORT
++	{ 0x3086, 0x5F2B}, // SEQ_DATA_PORT
++	{ 0x3086, 0x902B}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8081}, // SEQ_DATA_PORT
++	{ 0x3086, 0x6F40}, // SEQ_DATA_PORT
++	{ 0x3086, 0x1041}, // SEQ_DATA_PORT
++	{ 0x3086, 0x0160}, // SEQ_DATA_PORT
++	{ 0x3086, 0x29A2}, // SEQ_DATA_PORT
++	{ 0x3086, 0x29A3}, // SEQ_DATA_PORT
++	{ 0x3086, 0x5F4D}, // SEQ_DATA_PORT
++	{ 0x3086, 0x1C17}, // SEQ_DATA_PORT
++	{ 0x3086, 0x0281}, // SEQ_DATA_PORT
++	{ 0x3086, 0xE729}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8345}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8840}, // SEQ_DATA_PORT
++	{ 0x3086, 0x0F7F}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8A40}, // SEQ_DATA_PORT
++	{ 0x3086, 0x2345}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8024}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4008}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7F88}, // SEQ_DATA_PORT
++	{ 0x3086, 0x5D29}, // SEQ_DATA_PORT
++	{ 0x3086, 0x9288}, // SEQ_DATA_PORT
++	{ 0x3086, 0x102B}, // SEQ_DATA_PORT
++	{ 0x3086, 0x0489}, // SEQ_DATA_PORT
++	{ 0x3086, 0x165C}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4386}, // SEQ_DATA_PORT
++	{ 0x3086, 0x170B}, // SEQ_DATA_PORT
++	{ 0x3086, 0x5C03}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8A48}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4D4E}, // SEQ_DATA_PORT
++	{ 0x3086, 0x2B80}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4C09}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4119}, // SEQ_DATA_PORT
++	{ 0x3086, 0x816F}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4110}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4001}, // SEQ_DATA_PORT
++	{ 0x3086, 0x6029}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8229}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8329}, // SEQ_DATA_PORT
++	{ 0x3086, 0x435C}, // SEQ_DATA_PORT
++	{ 0x3086, 0x055F}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4D1C}, // SEQ_DATA_PORT
++	{ 0x3086, 0x81E7}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4502}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8180}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7F80}, // SEQ_DATA_PORT
++	{ 0x3086, 0x410A}, // SEQ_DATA_PORT
++	{ 0x3086, 0x9144}, // SEQ_DATA_PORT
++	{ 0x3086, 0x1609}, // SEQ_DATA_PORT
++	{ 0x3086, 0x2FC3}, // SEQ_DATA_PORT
++	{ 0x3086, 0xB130}, // SEQ_DATA_PORT
++	{ 0x3086, 0xC3B1}, // SEQ_DATA_PORT
++	{ 0x3086, 0x0343}, // SEQ_DATA_PORT
++	{ 0x3086, 0x164A}, // SEQ_DATA_PORT
++	{ 0x3086, 0x0A43}, // SEQ_DATA_PORT
++	{ 0x3086, 0x160B}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4316}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8F43}, // SEQ_DATA_PORT
++	{ 0x3086, 0x1690}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4316}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7F81}, // SEQ_DATA_PORT
++	{ 0x3086, 0x450A}, // SEQ_DATA_PORT
++	{ 0x3086, 0x410F}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7F83}, // SEQ_DATA_PORT
++	{ 0x3086, 0x5D29}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4488}, // SEQ_DATA_PORT
++	{ 0x3086, 0x102B}, // SEQ_DATA_PORT
++	{ 0x3086, 0x0453}, // SEQ_DATA_PORT
++	{ 0x3086, 0x0D40}, // SEQ_DATA_PORT
++	{ 0x3086, 0x2345}, // SEQ_DATA_PORT
++	{ 0x3086, 0x0240}, // SEQ_DATA_PORT
++	{ 0x3086, 0x087F}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8053}, // SEQ_DATA_PORT
++	{ 0x3086, 0x0D89}, // SEQ_DATA_PORT
++	{ 0x3086, 0x165C}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4586}, // SEQ_DATA_PORT
++	{ 0x3086, 0x170B}, // SEQ_DATA_PORT
++	{ 0x3086, 0x5C05}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8A60}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4B91}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4416}, // SEQ_DATA_PORT
++	{ 0x3086, 0x09C1}, // SEQ_DATA_PORT
++	{ 0x3086, 0x2CA9}, // SEQ_DATA_PORT
++	{ 0x3086, 0xAB30}, // SEQ_DATA_PORT
++	{ 0x3086, 0x51B3}, // SEQ_DATA_PORT
++	{ 0x3086, 0x3D5A}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7E3D}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7E19}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8000}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8B1F}, // SEQ_DATA_PORT
++	{ 0x3086, 0x2A1F}, // SEQ_DATA_PORT
++	{ 0x3086, 0x83A2}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7516}, // SEQ_DATA_PORT
++	{ 0x3086, 0xAD33}, // SEQ_DATA_PORT
++	{ 0x3086, 0x450A}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7F53}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8023}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8C66}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7F13}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8184}, // SEQ_DATA_PORT
++	{ 0x3086, 0x1481}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8031}, // SEQ_DATA_PORT
++	{ 0x3086, 0x3D64}, // SEQ_DATA_PORT
++	{ 0x3086, 0x452A}, // SEQ_DATA_PORT
++	{ 0x3086, 0x9451}, // SEQ_DATA_PORT
++	{ 0x3086, 0x9E96}, // SEQ_DATA_PORT
++	{ 0x3086, 0x3D2B}, // SEQ_DATA_PORT
++	{ 0x3086, 0x3D1B}, // SEQ_DATA_PORT
++	{ 0x3086, 0x529F}, // SEQ_DATA_PORT
++	{ 0x3086, 0x0E3D}, // SEQ_DATA_PORT
++	{ 0x3086, 0x083D}, // SEQ_DATA_PORT
++	{ 0x3086, 0x167E}, // SEQ_DATA_PORT
++	{ 0x3086, 0x307E}, // SEQ_DATA_PORT
++	{ 0x3086, 0x1175}, // SEQ_DATA_PORT
++	{ 0x3086, 0x163E}, // SEQ_DATA_PORT
++	{ 0x3086, 0x970E}, // SEQ_DATA_PORT
++	{ 0x3086, 0x82B2}, // SEQ_DATA_PORT
++	{ 0x3086, 0x3D7F}, // SEQ_DATA_PORT
++	{ 0x3086, 0xAC3E}, // SEQ_DATA_PORT
++	{ 0x3086, 0x4502}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7E11}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7FD0}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8000}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8C66}, // SEQ_DATA_PORT
++	{ 0x3086, 0x7F90}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8194}, // SEQ_DATA_PORT
++	{ 0x3086, 0x3F44}, // SEQ_DATA_PORT
++	{ 0x3086, 0x1681}, // SEQ_DATA_PORT
++	{ 0x3086, 0x8416}, // SEQ_DATA_PORT
++	{ 0x3086, 0x2C2C}, // SEQ_DATA_PORT
++	{ 0x3086, 0x2C2C}, // SEQ_DATA_PORT
++	//	[PLL_settings]
++	{ 0x302A, 0x0005}, 	//VT_PIX_CLK_DIV = 5
++	{ 0x302C, 0x0001}, 	//VT_SYS_CLK_DIV = 1
++	{ 0x302E, 0x0007}, 	//PRE_PLL_CLK_DIV = 7
++	{ 0x3030, 0x0082}, 	//PLL_MULTIPLIER = 130
++	{ 0x3036, 0x000A}, 	//OP_PIX_CLK_DIV = 10
++	{ 0x3038, 0x0001}, 	//OP_SYS_CLK_DIV = 1
++	//	BITFIELD = 0x30B0, 0x4000, 0x0000	//DIGITAL_TEST, bits 0x4000 = 0
++	{ 0x31B0, 0x0082}, 	//FRAME_PREAMBLE = 130
++	{ 0x31B2, 0x005C}, 	//LINE_PREAMBLE = 92
++	{ 0x31B4, 0x4248}, 	//MIPI_TIMING_0 = 16968
++	{ 0x31B6, 0x3258}, 	//MIPI_TIMING_1 = 12888
++	{ 0x31B8, 0x804B}, 	//MIPI_TIMING_2 = 32843
++	{ 0x31BA, 0x030B}, 	//MIPI_TIMING_3 = 779
++	{ 0x31BC, 0x8E09}, 	//MIPI_TIMING_4 = 36361
++	{ 0x3354, 0x002B}, 	//MIPI_CNTRL = 43
++
++
++	//	[Timing_settings]
++	{ 0x301A, 0x2058}, 	//RESET_REGISTER = 8280
++	{ 0x31AE, 0x0202}, 	//SERIAL_FORMAT = 514
++	{ 0x3002, 0x0044}, 	//Y_ADDR_START = 68
++	{ 0x3004, 0x0008}, 	//X_ADDR_START = 8
++	{ 0x3006, 0x047B}, 	//Y_ADDR_END = 1147
++	{ 0x3008, 0x0787}, 	//X_ADDR_END = 1927
++	{ 0x300A, 0x04B8}, 	//FRAME_LENGTH_LINES = 1208
++	{ 0x300C, 0x0264}, 	//LINE_LENGTH_PCK = 612
++	{ 0x3012, 0x048D}, 	//COARSE_INTEGRATION_TIME = 1165
++	{ 0x31AC, 0x0A0A}, 	//DATA_FORMAT_BITS = 2570
++	{ 0x3354, 0x002B},        //MIPI DATATYPE 10BITS
++	{ 0x306E, 0x9010}, 	//DATAPATH_SELECT = 36880
++	{ 0x30A2, 0x0001}, 	//X_ODD_INC = 1
++	{ 0x30A6, 0x0001}, 	//Y_ODD_INC = 1
++	{ 0x3082, 0x0003}, 	//OPERATION_MODE_CTRL = 3
++	{ 0x3040, 0x0000}, 	//READ_MODE = 0
++	{ 0x31D0, 0x0000}, 	//COMPANDING = 0
++//	{ 0x301A, 0x205C}, 	//RESET_REGISTER = 8284
++	{AR0234_REG_END, 0x00},/* END MARKER */
++};
++
++/*
++ * the part of driver was fixed.
++ */
++
++static struct regval_list ar0234_stream_on[] = {
++//	{0x301A, 0x19CC},
++	{0x301A, 0x205C},
++	{AR0234_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list ar0234_stream_off[] = {
++//	{0x301A, 0x19C8},
++	{0x301A, 0x2058},
++	{AR0234_REG_END, 0x00},	/* END MARKER */
++};
++
++static int ar0234_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct ar0234_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 2,
++			.buf	= value,
++		}
++	};
++	int ret = 0;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ar0234_write(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned short value)
++{
++	struct ar0234_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[4] = {reg >> 8, reg & 0xff, value >> 8, value & 0xff};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 4,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ar0234_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val[2];
++	uint16_t value;
++	while (vals->reg_num != AR0234_REG_END) {
++		if (vals->reg_num == AR0234_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ar0234_read(sd, vals->reg_num, val);
++			if (ret < 0)
++				return ret;
++		}
++		vals->value=(val[0]<<8)|val[1];
++		vals++;
++	}
++	return 0;
++}
++
++/*
++ * Write a list of register settings; ff/ff stops the process.
++ */
++static int ar0234_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != AR0234_REG_END) {
++		if (vals->reg_num == AR0234_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ar0234_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int ar0234_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct ar0234_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(10);
++	}
++	return 0;
++}
++
++static int ar0234_shutdown(struct v4l2_subdev *sd, u32 on)
++{
++	struct ar0234_info *info = to_state(sd);
++	int ret = 0;
++
++	if(on)
++		ret = gpio_direction_output(info->shutdown.pin, info->shutdown.active_level);
++	else
++		ret = gpio_direction_output(info->shutdown.pin, !info->shutdown.active_level);
++	return ret;
++}
++
++static int ar0234_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct ar0234_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = ar0234_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++
++static int ar0234_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v[2] = {0};
++	int ret;
++	ret = ar0234_read(sd, 0x3000, v);
++
++	if (ret < 0)
++		return ret;
++
++	printk("%x %x \n", v[0], v[1]);
++	if (v[0] != AR0234_CHIP_ID_H)
++		return -ENODEV;
++
++	if (v[1] != AR0234_CHIP_ID_L)
++		return -ENODEV;
++
++	return 0;
++}
++
++
++static struct ar0234_win_size ar0234_win_sizes[] = {
++	{
++		.sensor_info.mipi_cfg.twidth		= 1920,
++		.sensor_info.mipi_cfg.theight		= 1080,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.fps			= 60 << 16 | 1,
++
++		.width		= 1920,
++		.height		= 1080,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ar0234_init_regs_1080p_60fps_mipi,
++	},
++};
++
++static int ar0234_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_AR0234_FMTS)
++		return -EINVAL;
++
++	code->code = ar0234_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int ar0234_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct ar0234_format_struct *ovfmt;
++	struct ar0234_win_size *wsize;
++	struct ar0234_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int ar0234_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct ar0234_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	*(unsigned int *)fmt->reserved = &info->win->sensor_info;
++
++
++//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int ar0234_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ar0234_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ar0234_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ar0234_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int ar0234_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int ar0234_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ar0234_again_lut); i++) {
++		lut = &ar0234_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ar0234_again_lut); i++) {
++		lut = &ar0234_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return 0;
++}
++
++static int ar0234_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	struct ar0234_info *info = to_state(sd);
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++
++	ret = ar0234_read(sd, 0x3509, &reg_val);
++
++	*value = regval_to_again(reg_val);
++
++	return ret;
++}
++/*set analog gain db value, map value to sensor register.*/
++static int ar0234_s_again(struct v4l2_subdev *sd, int value)
++{
++	struct ar0234_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int ret = 0;
++	int i;
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(value);
++	}
++
++	ret += ar0234_write(sd, 0x3060, reg_value);
++	if (ret < 0)
++		return ret;
++
++	return ret;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int ar0234_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ar0234_s_exp(struct v4l2_subdev *sd, int value)
++{
++	struct ar0234_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = ar0234_write(sd, 0x3012, value);
++
++	return ret;
++}
++
++static int ar0234_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ar0234_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return ar0234_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ar0234_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int ar0234_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ar0234_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return ar0234_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return ar0234_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return ar0234_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return ar0234_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* ar0234_s_gain turns off auto gain */
++			return ar0234_s_gain(sd, info->gain->val);
++		}
++		return ar0234_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return ar0234_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ar0234_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return ar0234_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops ar0234_ctrl_ops = {
++	.s_ctrl = ar0234_s_ctrl,
++	.g_volatile_ctrl = ar0234_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ar0234_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = ar0234_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int ar0234_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	ar0234_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++
++int ar0234_s_power(struct v4l2_subdev *sd, int on)
++{
++	struct ar0234_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	int ret;
++
++	info->supply.pwen  = devm_regulator_get_optional(&client->dev, "pwen");
++	info->supply.shutdown  = devm_regulator_get_optional(&client->dev, "shutdown");
++
++	if (IS_ERR(info->supply.pwen)||IS_ERR(info->supply.shutdown)) {
++		if ((PTR_ERR(info->supply.pwen) == -EPROBE_DEFER)||(PTR_ERR(info->supply.shutdown) == -EPROBE_DEFER))
++			return -EPROBE_DEFER;
++		printk("No ar0234 vdd regulator found\n");
++	}
++
++	if ((!IS_ERR(info->supply.pwen))&&(!IS_ERR(info->supply.shutdown))){
++		if(on){
++			ret = regulator_enable(info->supply.pwen);
++			ret = regulator_enable(info->supply.shutdown);
++			if (ret)
++			   dev_err(&client->dev, "ar0234 vdd supply disable failed\n");
++		}else{
++			ret = regulator_disable(info->supply.pwen);
++			ret = regulator_disable(info->supply.shutdown);
++			if (ret)
++			    dev_err(&client->dev, "ar0234 vdd supply disable failed\n");
++		}
++	}else{
++		dev_err(&client->dev, "ar0234 vdd supply IS_ERR failed\n");
++	}
++	return ret;
++}
++
++int ar0234_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct ar0234_info *info = to_state(sd);
++	int ret = 0;
++	struct regval_list *vals;
++
++	if (enable) {
++		ret = ar0234_write_array(sd, ar0234_stream_on);
++		pr_debug("ar0234 stream on\n");
++	}
++	else {
++		ret = ar0234_write_array(sd, ar0234_stream_off);
++		pr_debug("ar0234 stream off\n");
++	}
++	return ret;
++}
++
++
++int ar0234_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct ar0234_info *info = to_state(sd);
++	if(info->win->fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops ar0234_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = ar0234_g_register,
++	.s_register = ar0234_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops ar0234_video_ops = {
++	.s_stream = ar0234_s_stream,
++	.g_frame_interval = ar0234_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops ar0234_pad_ops = {
++	//.enum_frame_interval = ar0234_enum_frame_interval,
++	//.num_frame_size = ar0234_enum_frame_size,
++	//.enum_mbus_code = ar0234_enum_mbus_code,
++	.set_fmt = ar0234_set_fmt,
++	.get_fmt = ar0234_get_fmt,
++};
++
++static const struct v4l2_subdev_ops ar0234_ops = {
++	.core = &ar0234_core_ops,
++	.video = &ar0234_video_ops,
++	.pad = &ar0234_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int ar0234_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_fract tpf;
++	struct v4l2_subdev *sd;
++	struct ar0234_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,expo-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->expo.pin = gpio;
++		info->expo.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,oe-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->oe.pin = gpio;
++		info->oe.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,pwen-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->pwen.pin = gpio;
++		info->pwen.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,shutdown-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->shutdown.pin = gpio;
++		info->shutdown.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++
++	v4l2_i2c_subdev_init(sd, client, &ar0234_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++	info->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++
++//	ar0234_shutdown(sd, 0);
++	ar0234_s_power(sd, 1);
++	ar0234_reset(sd, 1);
++#if 1
++	/* Make sure it's an ar0234 */
++	ret = ar0234_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an ar0234 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++
++	/*IRCUT ctl 0:off 1:on*/
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &ar0234_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &ar0234_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &ar0234_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &ar0234_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &ar0234_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &ar0234_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 1, 262144, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &ar0234_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1520 - 4, 1, 1000);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->win = &ar0234_win_sizes[0];
++	ar0234_init(sd, 1);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "ar0234 Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int ar0234_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ar0234_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	ar0234_s_power(sd, 0);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id ar0234_id[] = {
++	{ "ar0234", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ar0234_id);
++
++static const struct of_device_id ar0234_of_match[] = {
++	{.compatible = "onsemi,ar0234", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov2640_of_match);
++
++static int ar0234_suspend(struct device *dev)
++{
++        struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++        struct v4l2_subdev *sd = i2c_get_clientdata(client);
++        struct ar0234_info *info = to_state(sd);
++	int ret=0;
++
++	ar0234_s_power(sd,0);
++	v4l2_clk_disable(info->clk);
++        return 0;
++}
++
++static int ar0234_resume(struct device *dev)
++{
++	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ar0234_info *info = to_state(sd);
++	int ret=0;
++
++	ar0234_s_power(sd,1);
++	v4l2_clk_enable(info->clk);
++	ar0234_reset(sd, 1);
++	ar0234_init(sd, 1);
++	return 0;
++}
++
++const struct dev_pm_ops ar0234_pm =
++{
++        .suspend = ar0234_suspend,
++        .resume  = ar0234_resume,
++};
++
++
++static struct i2c_driver ar0234_driver = {
++	.driver = {
++		.name	= "ar0234",
++		.of_match_table = of_match_ptr(ar0234_of_match),
++		.pm	=  &ar0234_pm,
++	},
++	.probe		= ar0234_probe,
++	.remove		= ar0234_remove,
++	.id_table	= ar0234_id,
++};
++
++module_i2c_driver(ar0234_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for onsemi ar0234 sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/cisadc.c b/module_drivers/drivers/media/i2c/ingenic-isp/cisadc.c
+new file mode 100644
+index 000000000..2591db0cb
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/cisadc.c
+@@ -0,0 +1,602 @@
++
++#define DEBUG
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++
++#include <isp-sensor.h>
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct cisadc_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct cisadc_gpio {
++	int pin;
++	int active_level;
++};
++
++struct cisadc_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct cisadc_win_size *win;
++
++	struct cisadc_gpio reset;
++	struct cisadc_gpio ircutp;
++	struct cisadc_gpio ircutn;
++};
++
++
++/* scanner cis 300dpi/600dpi/1200dpi */
++static struct cisadc_win_size cisadc_win_sizes[] = {
++	/* 300dpi */
++	{
++		.width		= 5376, // 300dpi, dma 32bytes aligned
++		.height		= 1,
++		.sensor_info.fps		= 30 << 16 | 1,
++		/* .mbus_code	= MEDIA_BUS_FMT_SBGGR8_1X8, */
++		/* .colorspace	= V4L2_COLORSPACE_SRGB, */
++		/* .mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8, */
++		/* .colorspace	= V4L2_COLORSPACE_DEFAULT, */
++		.mbus_code	= MEDIA_BUS_FMT_Y8_1X8,
++		.colorspace	= V4L2_COLORSPACE_RAW,
++	},
++	/* 600dpi */
++	{
++		.width		= 10556, // 600dpi, dma 32bytes aligned
++		.height		= 1,
++		.sensor_info.fps		= 30 << 16 | 1,
++		.mbus_code	= MEDIA_BUS_FMT_Y8_1X8,
++		.colorspace	= V4L2_COLORSPACE_RAW,
++	},
++	/* 1200dpi */
++	{
++		.width		= 20920, // 1200dpi, dma 32bytes aligned
++		.height		= 1,
++		.sensor_info.fps		= 30 << 16 | 1,
++		.mbus_code	= MEDIA_BUS_FMT_Y8_1X8,
++		.colorspace	= V4L2_COLORSPACE_RAW,
++	},
++	/* user set xdpi, width/height */
++	{
++		.width		= 0, // 1200dpi, dma 32bytes aligned
++		.height		= 0,
++		.sensor_info.fps		= 30 << 16 | 1,
++		/* .mbus_code	= MEDIA_BUS_FMT_SBGGR8_1X8, */
++		/* .colorspace	= V4L2_COLORSPACE_SRGB, */
++		/* .mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8, */
++		/* .colorspace	= V4L2_COLORSPACE_DEFAULT, */
++		.mbus_code	= MEDIA_BUS_FMT_Y8_1X8,
++		.colorspace	= V4L2_COLORSPACE_RAW,
++	},
++};
++
++static inline struct cisadc_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct cisadc_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct cisadc_info, hdl)->sd;
++}
++
++#if 0
++/*
++ * Stuff that knows about the sensor.
++ */
++static int cisadc_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct cisadc_info *info = to_state(sd);
++#if 0
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(10);
++	}
++#endif
++	return 0;
++}
++
++static int cisadc_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	struct cisadc_info *info = to_state(sd);
++#if 0
++	if(val) {
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++	} else {
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, !info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++	}
++#endif
++	return 0;
++}
++
++static int cisadc_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct cisadc_info *info = to_state(sd);
++	int ret = 0;
++
++	//ret = cisadc_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++
++static int cisadc_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x return 0;\n", __func__, __LINE__, ret,v);
++
++	return 0;
++}
++#endif
++
++static int cisadc_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_CISADC_FMTS)
++		return -EINVAL;
++
++	code->code = cisadc_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++static const struct cisadc_win_size *cisadc_select_win(u32 *width, u32 *height)
++{
++	int i, default_size, win_size;
++	default_size = 0;
++	win_size = ARRAY_SIZE(cisadc_win_sizes);
++	//win_size -= 1;
++	for (i = 0; i < win_size; i++) {
++		if ((*width <= cisadc_win_sizes[i].width) &&
++				(*height <= cisadc_win_sizes[i].height)) {
++			*width = cisadc_win_sizes[i].width;
++			*height = cisadc_win_sizes[i].height;
++			return &cisadc_win_sizes[i];
++		}
++	}
++
++	*width = cisadc_win_sizes[default_size].width;
++	*height = cisadc_win_sizes[default_size].height;
++	return &cisadc_win_sizes[default_size];
++}
++
++/*
++ * Set a format.
++ */
++static int cisadc_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct cisadc_format_struct *ovfmt;
++	struct cisadc_win_size *wsize;
++	struct cisadc_info *info = to_state(sd);
++	int ret;
++	int win_size;
++
++	win_size = ARRAY_SIZE(cisadc_win_sizes);
++	dev_info(sd->dev, "format width=%d, height=%d, code=0x%x, format->pad=%p, win_size=%d\n", format->format.width, format->format.height, format->format.code, format->pad, win_size);
++
++	win_size--;
++	format->format.width = cisadc_win_sizes[win_size].width = format->format.width;
++	format->format.height = cisadc_win_sizes[win_size].height = format->format.height;
++
++	info->win = &cisadc_win_sizes[win_size];
++	//info->win = cisadc_select_win(&format->format.width, &format->format.height);
++
++	return 0;
++}
++
++static int cisadc_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct cisadc_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	*(unsigned int *)fmt->reserved = &info->win->sensor_info;
++
++
++	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++#if 0
++static int cisadc_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int cisadc_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int cisadc_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int cisadc_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int cisadc_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	char v = 0;
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++	return ret;
++
++}
++/*set analog gain db value, map value to sensor register.*/
++static int cisadc_s_again(struct v4l2_subdev *sd, int value)
++{
++	struct cisadc_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int ret = 0;
++
++	return 0;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int cisadc_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int cisadc_s_exp(struct v4l2_subdev *sd, int value)
++{
++	struct cisadc_info *info = to_state(sd);
++	int ret = 0;
++	if(info->exposure->val != value) {
++		ret = cisadc_write(sd, 0xfd, 0x01);
++		ret += cisadc_write(sd, 0x4, (unsigned char)(value & 0xff));
++		ret += cisadc_write(sd, 0x3, (unsigned char)((value & 0xff00) >> 8));
++		ret += cisadc_write(sd, 0x01, 0x01);
++	}
++	if (ret < 0) {
++		printk("cisadc_write error  %d\n" ,__LINE__);
++		return ret;
++	}
++	return ret;
++}
++#endif
++
++#if 0
++static int cisadc_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++#if 0
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct cisadc_info *info = to_state(sd);
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return cisadc_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return cisadc_g_again(sd, &info->again->val);
++	}
++#endif
++	return -EINVAL;
++}
++
++static int cisadc_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++#if 0
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct cisadc_info *info = to_state(sd);
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return cisadc_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return cisadc_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return cisadc_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return cisadc_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* cisadc_s_gain turns off auto gain */
++			return cisadc_s_gain(sd, info->gain->val);
++		}
++		return cisadc_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return cisadc_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return cisadc_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return cisadc_s_exp(sd, ctrl->val);
++	}
++#endif
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops cisadc_ctrl_ops = {
++	.s_ctrl = cisadc_s_ctrl,
++	.g_volatile_ctrl = cisadc_g_volatile_ctrl,
++};
++#endif
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int cisadc_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	//ret = cisadc_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int cisadc_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	//cisadc_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int cisadc_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct cisadc_info *info = to_state(sd);
++	int ret = 0;
++
++	return ret;
++}
++
++int cisadc_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct cisadc_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops cisadc_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = cisadc_g_register,
++	.s_register = cisadc_s_register,
++#endif
++};
++
++static const struct v4l2_subdev_video_ops cisadc_video_ops = {
++	.s_stream = cisadc_s_stream,
++	.g_frame_interval = cisadc_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops cisadc_pad_ops = {
++	//.enum_frame_interval = cisadc_enum_frame_interval,
++	//.num_frame_size = cisadc_enum_frame_size,
++	//.enum_mbus_code = cisadc_enum_mbus_code,
++	.set_fmt = cisadc_set_fmt,
++	.get_fmt = cisadc_get_fmt,
++};
++
++static const struct v4l2_subdev_ops cisadc_ops = {
++	.core = &cisadc_core_ops,
++	.video = &cisadc_video_ops,
++	.pad = &cisadc_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++extern int isp_clk;
++
++static int cisadc_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_subdev *sd;
++	struct cisadc_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++	unsigned int ispcdr;
++
++	/*
++	 * after system boot up, #devmem 0x10000030 32 0x8000000f
++	 * to set vic clock on.
++	 */
++	isp_clk = 4710000;	/* isp clk = cis-clk/2 = 9.3MHz/2 = 4.7MHz */
++	ispcdr = *(unsigned int*)0xB0000030;
++	v4l_info(client, "%s() isp_clk=%d, ispcdr=0x%08x\n",
++		 __func__, isp_clk, ispcdr);
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	v4l2_i2c_subdev_init(sd, client, &cisadc_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++#if 0
++	/*clk*/
++	info->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++
++	cisadc_reset(sd, 1);
++
++	/* Make sure it's an cisadc */
++	ret = cisadc_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an cisadc chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++
++	/*IRCUT ctl 0:off 1:on*/
++	cisadc_ircut(sd, 0);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &cisadc_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &cisadc_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &cisadc_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &cisadc_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &cisadc_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &cisadc_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 259142, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &cisadc_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1899 - 4, 1, 1500);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++#endif
++	info->win = &cisadc_win_sizes[0];
++	//cisadc_init(sd, 1);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "cisadc Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int cisadc_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct cisadc_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id cisadc_id[] = {
++	{ "cisadc", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, cisadc_id);
++
++static const struct of_device_id cisadc_of_match[] = {
++	{.compatible = "ingenic,cisadc", },
++	{},
++};
++
++static struct i2c_driver cisadc_driver = {
++	.driver = {
++		.name	= "cisadc",
++		.of_match_table = of_match_ptr(cisadc_of_match),
++	},
++	.probe		= cisadc_probe,
++	.remove		= cisadc_remove,
++	.id_table	= cisadc_id,
++};
++
++module_i2c_driver(cisadc_driver);
++MODULE_AUTHOR("Justin <linggang.wang@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for CIS ADC");
++MODULE_LICENSE("GPLv2");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/gc1054.c b/module_drivers/drivers/media/i2c/ingenic-isp/gc1054.c
+new file mode 100644
+index 000000000..f4fb0bb58
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/gc1054.c
+@@ -0,0 +1,1606 @@
++/*
++ * A V4L2 driver for OmniVision gc1054 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#define DEBUG
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++
++#include <isp-sensor.h>
++
++#define GC1054_CHIP_ID_H	(0x10)
++#define GC1054_CHIP_ID_L	(0x54)
++#define GC1054_REG_CHIP_ID_HIGH         0xF0
++#define GC1054_REG_CHIP_ID_LOW          0xF1
++
++
++#define GC1054_REG_END		0xff
++#define GC1054_REG_DELAY	0x00
++#define GC1054_PAGE_REG	    0xfd
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct gc1054_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct gc1054_gpio {
++	int pin;
++	int active_level;
++};
++
++struct gc1054_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct gc1054_win_size *win;
++
++	struct gc1054_gpio pwr;
++
++	struct gc1054_gpio reset;
++	struct gc1054_gpio cimen;
++	struct gc1054_gpio ircutp;
++	struct gc1054_gpio ircutn;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++
++struct again_lut gc1054_again_lut[] = {
++//gc1054_mipi.c add//
++    {0x00, 0},
++    {0x01, 33220},
++    {0x02, 64776},
++    {0x03, 98789},
++    {0x04, 131801},
++    {0x05, 165630},
++    {0x06, 197337},
++    {0x07, 231174},
++    {0x08, 262879},
++    {0x09, 297665},
++    { 0x0a, 329326},
++
++};
++
++static inline struct gc1054_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct gc1054_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct gc1054_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++static struct regval_list gc1054_init_regs_1280_720_30fps_dvp[] = {
++//Mclk=24Mhz£¬PCLK=39Mhz
++//HD=1726,VD=750,row_time=HD/PCLK=44.25us
++//Actual_window_size=1280*720
++	/////////////////////////////////////////////////////
++	//////////////////////   SYS   //////////////////////
++	/////////////////////////////////////////////////////
++	{0xf2,0x00},
++	{0xf6,0x00},
++	{0xfc,0x04},
++	{0xf7,0x01},
++	{0xf8,0x0c},
++	{0xf9,0x00}, // 06
++	{0xfa,0x80},
++	{0xfc,0x0e},
++	/////////////////////////////////////////////////////
++	////////////////   ANALOG & CISCTL   ////////////////
++	/////////////////////////////////////////////////////
++	{0xfe,0x00},
++	{0x03,0x02},
++	{0x04,0xa6},
++	{0x05,0x02}, //HB
++	{0x06,0x07},
++	{0x07,0x00}, //VB
++	{0x08,0x0a},
++	{0x09,0x00},
++
++	{0x0a,0x04}, //row start
++	{0x0b,0x00},
++	{0x0c,0x00}, //col start
++
++ 	 {0x0d,0x02},
++	 {0x0e,0xd4}, //height 724
++
++	{0x0f,0x05},
++	{0x10,0x08}, //width 1288
++
++
++	{0x17,0xc0},
++	{0x18,0x02},
++	{0x19,0x08},
++	{0x1a,0x18},
++	{0x1d,0x12},
++	{0x1e,0x50},
++	{0x1f,0x80},
++	{0x21,0x30},
++	{0x23,0xf8},
++	{0x25,0x10},
++	{0x28,0x20},
++	{0x34,0x08}, //data low
++	{0x3c,0x10},
++	{0x3d,0x0e},
++	{0xcc,0x8e},
++	{0xcd,0x9a},
++	{0xcf,0x70},
++	{0xd0,0xa9},
++	{0xd1,0xc5},
++	{0xd2,0xed}, //data high
++	{0xd8,0x3c}, //dacin offset
++	{0xd9,0x7a},
++	{0xda,0x12},
++	{0xdb,0x50},
++	{0xde,0x0c},
++	{0xe3,0x60},
++	{0xe4,0x78},
++	{0xfe,0x01},
++	{0xe3,0x01},
++	{0xe6,0x10}, //ramps offset
++	/////////////////////////////////////////////////////
++	//////////////////////   ISP   //////////////////////
++	/////////////////////////////////////////////////////
++	{0xfe,0x01},
++	{0x80,0x50},
++	{0x88,0x23},
++	{0x89,0x03},
++//	{0x8c,0x01},//bit0:test color bar.
++	{0x90,0x01},
++	{0x92,0x02}, //crop win 2<=y<=4
++	{0x94,0x03}, //crop win 2<=x<=5
++	{0x95,0x02}, //crop win height
++	{0x96,0xd0},
++	{0x97,0x05}, //crop win width
++	{0x98,0x00},
++	/////////////////////////////////////////////////////
++	//////////////////////   BLK   //////////////////////
++	/////////////////////////////////////////////////////
++	{0xfe,0x01},
++	{0x40,0x22},
++	{0x43,0x03},
++	{0x4e,0x3c},
++	{0x4f,0x00},
++	{0x60,0x00},
++	{0x61,0x80},
++	/////////////////////////////////////////////////////
++	//////////////////////   GAIN   /////////////////////
++	/////////////////////////////////////////////////////
++	{0xfe,0x01},
++	{0xb0,0x48},
++	{0xb1,0x01},
++	{0xb2,0x00},
++	{0xb6,0x00},
++	{0xfe,0x02},
++	{0x01,0x00},
++	{0x02,0x01},
++	{0x03,0x02},
++	{0x04,0x03},
++	{0x05,0x04},
++	{0x06,0x05},
++	{0x07,0x06},
++	{0x08,0x0e},
++	{0x09,0x16},
++	{0x0a,0x1e},
++	{0x0b,0x36},
++	{0x0c,0x3e},
++	{0x0d,0x56},
++	{0xfe,0x02},
++	{0xb0,0x00}, //col_gain[11:8]
++	{0xb1,0x00},
++	{0xb2,0x00},
++	{0xb3,0x11},
++	{0xb4,0x22},
++	{0xb5,0x54},
++	{0xb6,0xb8},
++	{0xb7,0x60},
++	{0xb9,0x00}, //col_gain[12]
++	{0xba,0xc0},
++	{0xc0,0x20}, //col_gain[7:0]
++	{0xc1,0x2d},
++	{0xc2,0x40},
++	{0xc3,0x5b},
++	{0xc4,0x80},
++	{0xc5,0xb5},
++	{0xc6,0x00},
++	{0xc7,0x6a},
++	{0xc8,0x00},
++	{0xc9,0xd4},
++	{0xca,0x00},
++	{0xcb,0xa8},
++	{0xcc,0x00},
++	{0xcd,0x50},
++	{0xce,0x00},
++	{0xcf,0xa1},
++	/////////////////////////////////////////////////////
++	////////////////////   DARKSUN   ////////////////////
++	/////////////////////////////////////////////////////
++	{0xfe,0x02},
++	{0x54,0xf7},
++	{0x55,0xf0},
++	{0x56,0x00},
++	{0x57,0x00},
++	{0x58,0x00},
++	{0x5a,0x04},
++	/////////////////////////////////////////////////////
++	///////////////////////   DD   //////////////////////
++	/////////////////////////////////////////////////////
++	{0xfe,0x04},
++	{0x81,0x8a},
++	/////////////////////////////////////////////////////
++	//////////////////////	 DVI	/////////////////////
++	/////////////////////////////////////////////////////
++	{0xfe,0x03},
++	{0x01,0x00},
++	{0x02,0x00},
++	{0x03,0x00},
++	{0x10,0x11},
++
++	{0x15,0x00},
++	{0x40,0x01},
++	{0x41,0x00},
++////////////////////////////////////////////
++/////////////   pad enable   ///////////////
++////////////////////////////////////////////
++	{0xfe,0x00},
++	{0xf2,0x0f},
++
++	{GC1054_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list gc1054_init_regs_1080_360_60fps_dvp[] = {
++//Mclk=24Mhz，PCLK=39Mhz
++//HD=1626,VD=399,row_time=HD/PCLK=41.69us
++//Actual_window_size=1280*720
++/////////////////////////////////////////////////////
++//////////////////////   SYS   //////////////////////
++/////////////////////////////////////////////////////
++	{0xf2,0x00},
++	{0xf6,0x00},
++	{0xfc,0x04},
++	{0xf7,0x01},
++//	{0xf8,0x0c},//pclk 39Mhz.
++	{0xf8,0x11},//pclk 54Mhz.
++	{0xf9,0x00},
++	{0xfa,0x80},
++	{0xfc,0x0e},
++////////////////////////////////////////////
++///////   ANALOG & CISCTL   ////////////////
++////////////////////////////////////////////
++	{0xfe,0x00},
++//	{0x03,0x02},////// exposure 12bit~8bit
++//	{0x04,0xa6},/////  exposure 7bit~0bit 720p default:678 ,1080*360<399
++	///////////
++	{0x03,0x01},
++	{0x04,0x08}, //xtang debug :384
++	/////////////
++	{0x05,0x02}, //HB
++	{0x06,0x07},
++	{0x07,0x00}, //VB
++	{0x08,0x13},//====ori
++//	{0x08,0x0a},//====720p def
++	/////////////
++	{0x09,0x00},
++//	{0x0a,0x04}, //row start
++	{0x0a,0xb4}, //row start 180
++	{0x0b,0x00},
++//	{0x0c,0x00}, //col start
++	{0x0c,0xc8}, //64 col start 100
++	////////////
++	{0x0d,0x01},
++	{0x0e,0x78}, //height 376
++	{0x0f,0x04},
++	{0x10,0x48}, //width 1096
++	/////////
++//	{0x0d,0x02},
++//	{0x0e,0xd4},//724
++//	{0x0f,0x05},
++//	{0x10,0x08}, //1288
++	/////////
++	{0x17,0xc0},
++	{0x18,0x02},
++	{0x19,0x08},
++	{0x1a,0x18},
++	{0x1d,0x12},
++	{0x1e,0x50},
++	{0x1f,0x80},
++	{0x21,0x30},
++	{0x23,0xf8},
++	{0x25,0x10},
++	{0x28,0x20},
++	{0x34,0x08}, //data low
++	{0x3c,0x10},
++	{0x3d,0x0e},
++	{0xcc,0x8e},
++	{0xcd,0x9a},
++	{0xcf,0x70},
++	{0xd0,0xa9},
++	{0xd1,0xc5},
++	{0xd2,0xed}, //data high
++	{0xd8,0x3c}, //dacin offset
++	{0xd9,0x7a},
++	{0xda,0x12},
++	{0xdb,0x50},
++	{0xde,0x0c},
++	{0xe3,0x60},
++	{0xe4,0x78},
++	{0xfe,0x01},
++	{0xe3,0x01},
++	{0xe6,0x10}, //ramps offset
++///////////////////,/////////////////////////
++/////////////   ISP   //////////////////////
++////////////////////////////////////////////
++	{0xfe,0x01}, 
++	{0x80,0x50},
++	{0x88,0x23},
++	{0x89,0x03},
++//	{0x8c,0x01},//test color bar
++	{0x90,0x01},
++	{0x92,0x02}, //crop win 2<=y<=4
++	{0x94,0x03}, //crop win 2<=x<=5
++	{0x95,0x01}, //crop win height
++	{0x96,0x68},
++	{0x97,0x04}, //crop win width
++	{0x98,0x38},
++////////////////////////////////////////////
++/////////////   BLK   //////////////////////
++////////////////////////////////////////////
++	{0xfe,0x01}, 
++	{0x40,0x22},
++	{0x43,0x03},
++	{0x4e,0x3c},
++	{0x4f,0x00},
++	{0x60,0x00},
++	{0x61,0x80},
++////////////////////////////////////////////
++/////////////   GAIN   /////////////////////
++////////////////////////////////////////////
++	{0xfe,0x01}, 
++	{0xb0,0x48},
++	{0xb1,0x01},
++	{0xb2,0x00},
++	{0xb6,0x00},
++	{0xfe,0x02},
++	{0x01,0x00},
++	{0x02,0x01},
++	{0x03,0x02},
++	{0x04,0x03},
++	{0x05,0x04},
++	{0x06,0x05},
++	{0x07,0x06},
++	{0x08,0x0e},
++	{0x09,0x16},
++	{0x0a,0x1e},
++	{0x0b,0x36},
++	{0x0c,0x3e},
++	{0x0d,0x56},
++	{0xfe,0x02},
++	{0xb0,0x00}, //col_gain[11:8]
++	{0xb1,0x00},
++	{0xb2,0x00},
++	{0xb3,0x11},
++	{0xb4,0x22},
++	{0xb5,0x54},
++	{0xb6,0xb8},
++	{0xb7,0x60},
++	{0xb9,0x00}, //col_gain[12]
++	{0xba,0xc0},
++	{0xc0,0x20}, //col_gain[7:0]
++	{0xc1,0x2d},
++	{0xc2,0x40},
++	{0xc3,0x5b},
++	{0xc4,0x80},
++	{0xc5,0xb5},
++	{0xc6,0x00},
++	{0xc7,0x6a},
++	{0xc8,0x00},
++	{0xc9,0xd4},
++	{0xca,0x00},
++	{0xcb,0xa8},
++	{0xcc,0x00},
++	{0xcd,0x50},
++	{0xce,0x00},
++	{0xcf,0xa1},
++////////////////////////////////////////////
++///////////   DARKSUN   ////////////////////
++////////////////////////////////////////////
++	{0xfe,0x02}, 
++	{0x54,0xf7},
++	{0x55,0xf0},
++	{0x56,0x00},
++	{0x57,0x00},
++	{0x58,0x00},
++	{0x5a,0x04},
++////////////////////////////////////////////
++//////////////   DD   //////////////////////
++////////////////////////////////////////////
++	{0xfe,0x04}, 
++	{0x81,0x8a},
++////////////////////////////////////////////
++/////////////	 MIPI	/////////////////////
++////////////////////////////////////////////
++	{0xfe,0x03}, 
++	{0x01,0x00},
++	{0x02,0x00},
++	{0x03,0x00},
++	{0x10,0x11},
++	{0x15,0x00},
++	{0x40,0x01},
++	{0x41,0x00},
++	///////////
++	{0x42,0x38},
++	{0x43,0x04},// width 1080 (must set!)
++////////////////////////////////////////////
++/////////////   pad enable   ///////////////
++////////////////////////////////////////////
++	{0xfe,0x00},
++	{0xf2,0x0f},
++	{GC1054_REG_END, 0x00},	/* END MARKER */
++
++};
++static struct regval_list gc1054_init_regs_540_360_100fps_dvp[] = {
++//Mclk=24Mhz，PCLK=39Mhz
++//HD=1626,VD=398,row_time=HD/PCLK=25.1us
++//Actual_window_size=540*360
++/////////////////////////////////////////////////////
++//////////////////////   SYS   //////////////////////
++/////////////////////////////////////////////////////
++	{0xf2,0x00},
++	{0xf6,0x00},
++	{0xfc,0x04},
++	{0xf7,0x01},
++//	{0xf8,0x11},// stage:3M,54MHZ.
++	{0xf8,0x0c},// stage:3M,39MHZ.
++	{0xf9,0x00},
++	{0xfa,0x80},
++	{0xfc,0x0e},
++////////////////////////////////////////////
++///////   ANALOG & CISCTL   ////////////////
++////////////////////////////////////////////
++	{0xfe,0x00},
++//	{0x03,0x02},
++//	{0x04,0xa6},
++	////////
++	{0x03,0x01},
++//	{0x04,0x08}, //xtang debug:384
++	{0x04,0x00}, //gc debug:256
++	////////
++	{0x05,0x02}, //HB
++//	{0x06,0x07},
++//	//////
++	{0x06,0x06},// xtang debug  hb
++	/////
++	{0x07,0x00}, //VB
++	{0x08,0x12},
++	{0x09,0x00},
++	{0x0a,0x04}, //row start
++	{0x0b,0x00},
++	{0x0c,0x00}, //col start
++	{0x0d,0x01},
++	{0x0e,0x78}, //height 724
++//	{0x0f,0x04},
++//	{0x10,0x48}, //width 1288
++//	////
++	{0x0f,0x02},
++	{0x10,0x2c}, //debug width 556
++//	////
++	{0x17,0xc0},
++	{0x18,0x02},
++	{0x19,0x08},
++	{0x1a,0x18},
++	{0x1d,0x12},
++	{0x1e,0x50},
++	{0x1f,0x80},
++	{0x21,0x30},
++	{0x23,0xf8},
++	{0x25,0x10},
++	{0x28,0x20},
++	{0x34,0x08}, //data low
++	{0x3c,0x10},
++	{0x3d,0x0e},
++	{0xcc,0x8e},
++	{0xcd,0x9a},
++	{0xcf,0x70},
++	{0xd0,0xa9},
++	{0xd1,0xc5},
++	{0xd2,0xed}, //data high
++	{0xd8,0x3c}, //dacin offset
++	{0xd9,0x7a},
++	{0xda,0x12},
++	{0xdb,0x50},
++	{0xde,0x0c},
++	{0xe3,0x60},
++	{0xe4,0x78},
++	{0xfe,0x01},
++	{0xe3,0x01},
++	{0xe6,0x10}, //ramps offset
++////////////////////////////////////////////
++/////////////   ISP   //////////////////////
++////////////////////////////////////////////
++	{0xfe,0x01},
++	{0x80,0x50},
++	{0x88,0x23},
++	{0x89,0x03},
++	{0x90,0x01},
++	{0x92,0x02}, //crop win 2<=y<=4
++	{0x94,0x03}, //crop win 2<=x<=5
++	{0x95,0x01}, //crop win height
++	{0x96,0x68},
++	{0x97,0x02}, //crop win width
++	{0x98,0x1c},
++////////////////////////////////////////////
++/////////////   BLK   //////////////////////
++////////////////////////////////////////////
++	{0xfe,0x01},
++	{0x40,0x22},
++	{0x43,0x03},
++	{0x4e,0x3c},
++	{0x4f,0x00},
++	{0x60,0x00},
++	{0x61,0x80},
++////////////////////////////////////////////
++/////////////   GAIN   /////////////////////
++////////////////////////////////////////////
++	{0xfe,0x01},
++	{0xb0,0x48},
++	{0xb1,0x01},
++	{0xb2,0x00},
++	{0xb6,0x00},
++	{0xfe,0x02},
++	{0x01,0x00},
++	{0x02,0x01},
++	{0x03,0x02},
++	{0x04,0x03},
++	{0x05,0x04},
++	{0x06,0x05},
++	{0x07,0x06},
++	{0x08,0x0e},
++	{0x09,0x16},
++	{0x0a,0x1e},
++	{0x0b,0x36},
++	{0x0c,0x3e},
++	{0x0d,0x56},
++	{0xfe,0x02},
++	{0xb0,0x00}, //col_gain[11:8]
++	{0xb1,0x00},
++	{0xb2,0x00},
++	{0xb3,0x11},
++	{0xb4,0x22},
++	{0xb5,0x54},
++	{0xb6,0xb8},
++	{0xb7,0x60},
++	{0xb9,0x00}, //col_gain[12]
++	{0xba,0xc0},
++	{0xc0,0x20}, //col_gain[7:0]
++	{0xc1,0x2d},
++	{0xc2,0x40},
++	{0xc3,0x5b},
++	{0xc4,0x80},
++	{0xc5,0xb5},
++	{0xc6,0x00},
++	{0xc7,0x6a},
++	{0xc8,0x00},
++	{0xc9,0xd4},
++	{0xca,0x00},
++	{0xcb,0xa8},
++	{0xcc,0x00},
++	{0xcd,0x50},
++	{0xce,0x00},
++	{0xcf,0xa1},
++////////////////////////////////////////////
++///////////   DARKSUN   ////////////////////
++////////////////////////////////////////////
++	{0xfe,0x02},
++	{0x54,0xf7},
++	{0x55,0xf0},
++	{0x56,0x00},
++	{0x57,0x00},
++	{0x58,0x00},
++	{0x5a,0x04},
++////////////////////////////////////////////
++//////////////   DD   //////////////////////
++////////////////////////////////////////////
++	{0xfe,0x04},
++	{0x81,0x8a},
++////////////////////////////////////////////
++/////////////	 MIPI	/////////////////////
++////////////////////////////////////////////
++	{0xfe,0x03},
++	{0x01,0x00},
++	{0x02,0x00},
++	{0x03,0x00},
++	{0x10,0x11},
++	{0x15,0x00},
++	{0x40,0x01},
++	{0x41,0x00},
++	{0x42,0x1c},
++	{0x43,0x02},
++////////////////////////////////////////////
++/////////////   pad enable   ///////////////
++////////////////////////////////////////////
++	{0xfe,0x00},
++	{0xf2,0x0f},
++	{GC1054_REG_END, 0x00},
++};
++static struct regval_list gc1054_init_regs_720_360_100fps_dvp[] = {
++//Mclk=24Mhz，PCLK=39Mhz
++//HD=1626,VD=398,row_time=HD/PCLK=25.1us
++//Actual_window_size=720*360
++/////////////////////////////////////////////////////
++//////////////////////   SYS   //////////////////////
++/////////////////////////////////////////////////////
++	{0xf2,0x00}, 
++	{0xf6,0x00},
++	{0xfc,0x04},
++	{0xf7,0x01},
++	{0xf8,0x11},
++	{0xf9,0x00},
++	{0xfa,0x80},
++	{0xfc,0x0e},
++////////////////////////////////////////////
++///////   ANALOG & CISCTL   ////////////////
++////////////////////////////////////////////
++	{0xfe,0x00}, 
++	{0x03,0x01}, 
++	{0x04,0x00}, 
++	{0x05,0x02}, //HB
++	{0x06,0x07},
++	{0x07,0x00}, //VB
++	{0x08,0x12}, 
++	{0x09,0x00},
++	{0x0a,0x04}, //row start
++	{0x0b,0x00},
++	{0x0c,0x02}, //col start
++	{0x0d,0x01}, 
++	{0x0e,0x90}, //height 724
++	{0x0f,0x02},
++	{0x10,0xe0},//width 1288
++	{0x17,0xc0},
++	{0x18,0x02},
++	{0x19,0x08},
++	{0x1a,0x18},
++	{0x1d,0x12},
++	{0x1e,0x50},
++	{0x1f,0x80},
++	{0x21,0x30},
++	{0x23,0xf8},
++	{0x25,0x10},
++	{0x28,0x20},
++	{0x34,0x08}, //data low
++	{0x3c,0x10},
++	{0x3d,0x0e},
++	{0xcc,0x8e},
++	{0xcd,0x9a},
++	{0xcf,0x70},
++	{0xd0,0xa9},
++	{0xd1,0xc5},
++	{0xd2,0xed}, //data high
++	{0xd8,0x3c}, //dacin offset
++	{0xd9,0x7a},
++	{0xda,0x12},
++	{0xdb,0x50},
++	{0xde,0x0c},
++	{0xe3,0x60},
++	{0xe4,0x78},
++	{0xfe,0x01},
++	{0xe3,0x01},
++	{0xe6,0x10}, //ramps offset
++////////////////////////////////////////////
++/////////////   ISP   //////////////////////
++////////////////////////////////////////////
++	{0xfe,0x01}, 
++	{0x80,0x50},
++	{0x88,0x23},
++	{0x89,0x03},
++	{0x90,0x01}, 
++	{0x92,0x01}, //crop win 2<=y<=4
++	{0x94,0x02}, //crop win 2<=x<=5
++	{0x95,0x01}, //crop win height
++	{0x96,0x68},
++	{0x97,0x02}, //crop win width
++	{0x98,0xd0},
++////////////////////////////////////////////
++/////////////   BLK   //////////////////////
++////////////////////////////////////////////
++	{0xfe,0x01}, 
++	{0x40,0x22},
++	{0x43,0x03},
++	{0x4e,0x3c},
++	{0x4f,0x00},
++	{0x60,0x00},
++	{0x61,0x80},
++////////////////////////////////////////////
++/////////////   GAIN   /////////////////////
++////////////////////////////////////////////
++	{0xfe,0x01}, 
++	{0xb0,0x48},
++	{0xb1,0x01}, 
++	{0xb2,0x00}, 
++	{0xb6,0x00}, 
++	{0xfe,0x02},
++	{0x01,0x00},
++	{0x02,0x01},
++	{0x03,0x02},
++	{0x04,0x03},
++	{0x05,0x04},
++	{0x06,0x05},
++	{0x07,0x06},
++	{0x08,0x0e},
++	{0x09,0x16},
++	{0x0a,0x1e},
++	{0x0b,0x36},
++	{0x0c,0x3e},
++	{0x0d,0x56},
++	{0xfe,0x02},
++	{0xb0,0x00}, //col_gain[11:8]
++	{0xb1,0x00},
++	{0xb2,0x00},
++	{0xb3,0x11},
++	{0xb4,0x22},
++	{0xb5,0x54},
++	{0xb6,0xb8},
++	{0xb7,0x60},
++	{0xb9,0x00}, //col_gain[12]
++	{0xba,0xc0},
++	{0xc0,0x20}, //col_gain[7:0]
++	{0xc1,0x2d},
++	{0xc2,0x40},
++	{0xc3,0x5b},
++	{0xc4,0x80},
++	{0xc5,0xb5},
++	{0xc6,0x00},
++	{0xc7,0x6a},
++	{0xc8,0x00},
++	{0xc9,0xd4},
++	{0xca,0x00},
++	{0xcb,0xa8},
++	{0xcc,0x00},
++	{0xcd,0x50},
++	{0xce,0x00},
++	{0xcf,0xa1},
++////////////////////////////////////////////
++///////////   DARKSUN   ////////////////////
++////////////////////////////////////////////
++	{0xfe,0x02}, 
++	{0x54,0xf7},
++	{0x55,0xf0},
++	{0x56,0x00},
++	{0x57,0x00},
++	{0x58,0x00},
++	{0x5a,0x04},
++////////////////////////////////////////////
++//////////////   DD   //////////////////////
++////////////////////////////////////////////
++	{0xfe,0x04}, 
++	{0x81,0x8a},
++////////////////////////////////////////////
++/////////////	 MIPI	/////////////////////
++////////////////////////////////////////////
++	{0xfe,0x03}, 
++	{0x01,0x00},
++	{0x02,0x00},
++	{0x03,0x00},
++	{0x10,0x11},
++	{0x15,0x00},
++	{0x40,0x01},
++	{0x41,0x00},
++	{0x42,0xd0},
++	{0x43,0x02},
++////////////////////////////////////////////
++/////////////   pad enable   ///////////////
++////////////////////////////////////////////
++	{0xfe,0x00}, 
++	{0xf2,0x0f}, 
++	{GC1054_REG_END, 0x00},
++
++};
++
++// reg: 0xf2
++//「陌上桑: DVP用这个控制stream on�
++//—————————
++//「陌上桑: 0x0f写0x00就是关闭输出了�
++//—————————
++//
++static struct regval_list gc1054_stream_on[] = {
++	{0xfe, 0x03},
++//	{0x10, 0x90},//mipi stream on
++	{0x10, 0x11},//dvp fake stream on
++
++	{GC1054_REG_END, 0x00},
++};
++
++static struct regval_list gc1054_stream_off[] = {
++	{0xfe, 0x03},
++	{0x10, 0x00},//fake stream off
++
++	{GC1054_REG_END, 0x00},
++};
++
++
++int gc1054_read(struct v4l2_subdev *sd, unsigned char reg,
++		unsigned char *value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 1,
++			.buf	= &reg,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int gc1054_write(struct v4l2_subdev *sd, unsigned char reg,
++			unsigned char value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	unsigned char buf[2] = {reg, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 2,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int gc1054_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != GC1054_REG_END) {
++		if (vals->reg_num == GC1054_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = gc1054_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++//			dev_vdbg(&sd->dev, "array: 0x%02x, 0x%02x",
++			pr_debug("array: 0x%02x, 0x%02x\n",
++					         vals->reg_num, val);
++		}
++		vals++;
++	}
++	return 0;
++}
++static int gc1054_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != GC1054_REG_END) {
++		if (vals->reg_num == GC1054_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = gc1054_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int gc1054_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct gc1054_info *info = to_state(sd);
++return 0;
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(20);
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(20);
++	}
++	return 0;
++}
++
++static int gc1054_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	struct gc1054_info *info = to_state(sd);
++return 0;
++	if(val) {
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++	} else {
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, !info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++	}
++	return 0;
++}
++
++static int gc1054_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct gc1054_info *info = to_state(sd);
++	int ret = 0;
++//	struct regval_list*reg = info->win->regs;
++//	ret = gc1054_write_array(sd, info->win->regs);
++//#if 0
++//	while(reg->reg_num != GC1054_REG_END)
++//	{
++//			printk("--->reg:0x%02x,value:[0x%02x]\n",reg->reg_num,reg->value);
++//			reg ++;
++//
++//	}
++//#else
++//	ret = gc1054_read_array(sd, info->win->regs);
++//	if (ret<0)
++//#endif
++
++	return ret;
++}
++
++
++
++static int gc1054_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++
++
++	ret = gc1054_read(sd, GC1054_REG_CHIP_ID_HIGH, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != GC1054_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = gc1054_read(sd, GC1054_REG_CHIP_ID_LOW, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != GC1054_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	printk(" gc1054 id %x\n", *ident);
++	return 0;
++}
++
++
++static struct gc1054_win_size gc1054_win_sizes[] = {
++	/* 1280*720 */
++
++	{
++		.width		= 1280,
++		.height		= 720,
++		.sensor_info.fps		= 30 << 16 | 1,
++		.mbus_code	= MEDIA_BUS_FMT_SRGGB8_1X8,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= gc1054_init_regs_1280_720_30fps_dvp,
++	},
++	/* 1080*360 */
++
++	{
++		.width		= 1080,
++		.height		= 360,
++		.sensor_info.fps		= 60 << 16 | 1,
++		.mbus_code	= MEDIA_BUS_FMT_SRGGB8_1X8,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= gc1054_init_regs_1080_360_60fps_dvp,
++	},
++	
++	/* 720*360 */
++
++	{
++		.width		= 720,
++		.height		= 360,
++		.sensor_info.fps		= 100 << 16 | 1,
++		.mbus_code	= MEDIA_BUS_FMT_SRGGB8_1X8,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= gc1054_init_regs_720_360_100fps_dvp,
++	},
++
++};
++static const struct gc1054_win_size *gc1054_select_win(u32 *width, u32 *height)
++{
++	int i, default_size = ARRAY_SIZE(gc1054_win_sizes) - 1;
++
++	for (i = 0; i < ARRAY_SIZE(gc1054_win_sizes); i++) {
++		if ((*width >= gc1054_win_sizes[i].width) &&
++				(*height >= gc1054_win_sizes[i].height)) {
++			*width = gc1054_win_sizes[i].width;
++			*height = gc1054_win_sizes[i].height;
++			return &gc1054_win_sizes[i];
++		}
++	}
++
++	*width = gc1054_win_sizes[default_size].width;
++	*height = gc1054_win_sizes[default_size].height;
++//	printk("------w=%d,h=%d--default_size=%d---->line=%d,func=%s\n",*width,*height,default_size,__LINE__,__func__);
++	return &gc1054_win_sizes[default_size];
++}
++
++static int gc1054_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_GC1054_FMTS)
++		return -EINVAL;
++
++	code->code = gc1054_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int gc1054_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct gc1054_format_struct *ovfmt;
++	struct gc1054_win_size *wsize;
++	struct gc1054_info *info = to_state(sd);
++	int ret;
++
++//	if (format->pad)
++//		return -EINVAL;
++
++	info->win = gc1054_select_win(&format->format.width, &format->format.height);
++
++
++	return 0;
++}
++
++static int gc1054_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct gc1054_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	*(unsigned int *)fmt->reserved = &info->win->sensor_info;
++
++
++	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int gc1054_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc1054_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc1054_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc1054_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int gc1054_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int gc1054_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(gc1054_again_lut); i++) {
++		lut = &gc1054_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(gc1054_again_lut); i++) {
++		lut = &gc1054_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return -EINVAL;
++}
++
++static int gc1054_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	char v = 0;
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++
++	ret = gc1054_read(sd, 0x23, &v);
++	reg_val |= v ;
++
++	*value = regval_to_again(reg_val);
++
++	return ret;
++
++}
++/*set analog gain db value, map value to sensor register.*/
++static int gc1054_s_again(struct v4l2_subdev *sd, int value)
++{
++	struct gc1054_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int ret = 0;
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(value);
++	}
++
++//gc1054_mipi.c//
++	ret = gc1054_write(sd, 0xfe, 0x01);
++	ret += gc1054_write(sd, 0xb6, (unsigned char)reg_value);
++	ret = gc1054_write(sd, 0xfe, 0x00);
++//	printk("gc1054_write ok ,set analog gain from gc1054_again_lut array. %d\n" ,__LINE__ );
++//gc1054_mipi.c//
++
++	if (ret < 0){
++		printk("gc1054_write error  %d\n" ,__LINE__ );
++		return ret;
++	}
++	return 0;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int gc1054_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc1054_s_exp(struct v4l2_subdev *sd, int value)
++{
++	struct gc1054_info *info = to_state(sd);
++	int ret = 0;
++
++//	ret = gc1054_write(sd, 0xfd, 0x01);
++//	ret += gc1054_write(sd, 0x4, (unsigned char)(value & 0xff));
++//	ret += gc1054_write(sd, 0x3, (unsigned char)((value & 0xff00) >> 8));
++//	ret += gc1054_write(sd, 0x01, 0x01);
++//
++//	if (ret < 0) {
++//		printk("gc1054_write error  %d\n" ,__LINE__);
++//		return ret;
++//	}
++	return ret;
++}
++
++static int gc1054_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct gc1054_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return gc1054_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return gc1054_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int gc1054_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct gc1054_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return gc1054_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return gc1054_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return gc1054_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return gc1054_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* gc1054_s_gain turns off auto gain */
++			return gc1054_s_gain(sd, info->gain->val);
++		}
++		return gc1054_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return gc1054_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return gc1054_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return gc1054_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops gc1054_ctrl_ops = {
++	.s_ctrl = gc1054_s_ctrl,
++	.g_volatile_ctrl = gc1054_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int gc1054_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = gc1054_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int gc1054_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	gc1054_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int gc1054_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct gc1054_info *info = to_state(sd);
++	int ret = 0;
++	if (enable) {
++		ret = gc1054_write_array(sd, info->win->regs);
++		if(ret<0)
++			return ret;
++		ret = gc1054_write_array(sd, gc1054_stream_on);
++		pr_debug("gc1054 stream on\n");
++
++	}
++	else {
++		ret = gc1054_write_array(sd, gc1054_stream_off);
++		pr_debug("gc1054 stream off\n");
++	}
++	return ret;
++}
++
++int gc1054_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct gc1054_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops gc1054_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = gc1054_g_register,
++	.s_register = gc1054_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops gc1054_video_ops = {
++	.s_stream = gc1054_s_stream,
++	.g_frame_interval = gc1054_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops gc1054_pad_ops = {
++	//.enum_frame_interval = gc1054_enum_frame_interval,
++	//.num_frame_size = gc1054_enum_frame_size,
++	//.enum_mbus_code = gc1054_enum_mbus_code,
++	.set_fmt = gc1054_set_fmt,
++	.get_fmt = gc1054_get_fmt,
++};
++
++static const struct v4l2_subdev_ops gc1054_ops = {
++	.core = &gc1054_core_ops,
++	.video = &gc1054_video_ops,
++	.pad = &gc1054_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int gc1054_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_subdev *sd;
++	struct gc1054_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++
++printk(" gc1054 probe \n\n");
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++//	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,cim-rst-gpio", 0, &flags);
++//	if(gpio_is_valid(gpio)) {
++//		info->reset.pin = gpio;
++//		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++//		printk("~~~~~~~line=%d,reset gpio=%d,value=%d\n",__LINE__,info->reset.pin,info->reset.active_level);
++//		ret = gpio_request_one(info->reset.pin, GPIOF_DIR_OUT, "rst");
++//		if(ret < 0) {
++//				dev_err(&client->dev, "Failed to request reset pin!\n");
++//				return ret;
++//		}
++//	}
++
++
++
++//init cim-en-gpio:3v3
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,cim-en-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->cimen.pin = gpio;
++		info->cimen.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(info->cimen.pin, GPIOF_DIR_OUT, "cim-en");
++		if(ret < 0) {
++			dev_err(&client->dev, "Failed to request cimen pin!\n");
++			return ret;
++		}
++		ret = gpio_direction_output(info->cimen.pin,info->cimen.active_level); //0
++		if(ret < 0) {
++			dev_err(&client->dev, "Failed to output cimen pin 0!\n");
++			return ret;
++		}
++
++	}
++
++
++	v4l2_i2c_subdev_init(sd, client, &gc1054_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++	info->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++
++//	gc1054_reset(sd, 1);
++
++#if 1
++	/* Make sure it's an gc1054 */
++		ret = gc1054_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an gc1054 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++	/*IRCUT ctl 0:off 1:on*/
++//	gc1054_ircut(sd, 0);
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &gc1054_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &gc1054_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &gc1054_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &gc1054_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &gc1054_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &gc1054_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 259142, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &gc1054_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1899 - 4, 1, 1500);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++//	info->win = &gc1054_win_sizes[0];//720p
++//	info->win = &gc1054_win_sizes[1];//1080*360
++//	info->win = &gc1054_win_sizes[2];//720*360
++	gc1054_init(sd, 1);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "gc1054 Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int gc1054_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct gc1054_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id gc1054_id[] = {
++	{ "gc1054", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, gc1054_id);
++
++static const struct of_device_id gc1054_of_match[] = {
++	{.compatible = "galaxyc,gc1054", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov2640_of_match);
++
++
++static struct i2c_driver gc1054_driver = {
++	.driver = {
++		.name	= "gc1054",
++		.of_match_table = of_match_ptr(gc1054_of_match),
++	},
++	.probe		= gc1054_probe,
++	.remove		= gc1054_remove,
++	.id_table	= gc1054_id,
++};
++
++module_i2c_driver(gc1054_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for OmniVision gc1054 sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/gc2093.c b/module_drivers/drivers/media/i2c/ingenic-isp/gc2093.c
+new file mode 100644
+index 000000000..ad64d5e09
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/gc2093.c
+@@ -0,0 +1,1043 @@
++/*
++ * A V4L2 driver for OmniVision gc2093 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#define DEBUG
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++
++#include <isp-sensor.h>
++
++#define GC2093_CHIP_ID_H	(0x20)
++#define GC2093_CHIP_ID_L	(0x93)
++#define GC2093_REG_CHIP_ID_HIGH         0x03f0
++#define GC2093_REG_CHIP_ID_LOW          0x03f1
++
++
++#define GC2093_REG_END		0xffff
++#define GC2093_REG_DELAY	0x00
++#define GC2093_PAGE_REG	    0xfd
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct gc2093_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++};
++
++struct gc2093_gpio {
++	int pin;
++	int active_level;
++};
++
++struct gc2093_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct gc2093_win_size *win;
++
++	struct gc2093_gpio pwr;
++
++	struct gc2093_gpio reset;
++	struct gc2093_gpio cimen;
++	struct gc2093_gpio ircutp;
++	struct gc2093_gpio ircutn;
++};
++
++
++
++static unsigned int  regValTable_t30[25][8] = {
++       // {0xb3,0xb8,0xb9,0x155,0xc2,0xcf,0xd9},
++	{0x00,0x01,0x00,0x08,0x10,0x08,0x0a,0},
++	{0x10,0x01,0x0c,0x08,0x10,0x08,0x0a,14997},
++	{0x20,0x01,0x1b,0x08,0x11,0x08,0x0c,32233},
++	{0x30,0x01,0x2c,0x08,0x12,0x08,0x0e,46808},
++	{0x40,0x01,0x3f,0x08,0x14,0x08,0x12,60995},
++	{0x50,0x02,0x16,0x08,0x15,0x08,0x14,75348},
++	{0x60,0x02,0x35,0x08,0x17,0x08,0x18,90681},
++	{0x70,0x03,0x16,0x08,0x18,0x08,0x1a,104361},
++	{0x80,0x04,0x02,0x08,0x1a,0x08,0x1e,118021},
++	{0x90,0x04,0x31,0x08,0x1b,0x08,0x20,131438},
++	{0xa0,0x05,0x32,0x08,0x1d,0x08,0x24,145749},
++	{0xb0,0x06,0x35,0x08,0x1e,0x08,0x26,159553},
++	{0xc0,0x08,0x04,0x08,0x20,0x08,0x2a,172553},
++	{0x5a,0x09,0x19,0x08,0x1e,0x08,0x2a,183132},
++	{0x83,0x0b,0x0f,0x08,0x1f,0x08,0x2a,198614},
++	{0x93,0x0d,0x12,0x08,0x21,0x08,0x2e,212697},
++	{0x84,0x10,0x00,0x0b,0x22,0x08,0x30,226175},
++	{0x94,0x12,0x3a,0x0b,0x24,0x08,0x34,240788},
++	{0x5d,0x1a,0x02,0x0b,0x26,0x08,0x34,271536},
++	{0x9b,0x1b,0x20,0x0b,0x26,0x08,0x34,272451},
++	{0x8c,0x20,0x0f,0x0b,0x26,0x08,0x34,287144},
++	{0x9c,0x26,0x07,0x12,0x26,0x08,0x34,302425},
++	{0xB6,0x36,0x21,0x12,0x26,0x08,0x34,334228},
++	{0xad,0x37,0x3a,0x12,0x26,0x08,0x34,351574},
++	{0xbd,0x3d,0x02,0x12,0x26,0x08,0x34,367506},
++};
++unsigned int  gainLevelTable[26] = {
++	64,
++	76,
++	91,
++	107,
++	125,
++	147,
++	177,
++	211,
++	248,
++	297,
++	356,
++	425,
++	504,
++	599,
++	709,
++	836,
++	978,
++	1153,
++	1647,
++	1651,
++	1935,
++	2292,
++	3239,
++	3959,
++	4686,
++	0xffffffff,
++};
++
++/***********************************/
++
++
++struct again_lut {
++	unsigned int index;
++	unsigned char regb0;
++	unsigned char regb1;
++	unsigned int  regb2;
++	unsigned char regb3;
++	unsigned char regb4;
++	unsigned char regb5;
++	unsigned char regb6;
++	unsigned char regb7;
++
++	unsigned int gain;
++};
++
++
++static inline struct gc2093_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct gc2093_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct gc2093_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++static struct regval_list gc2093_init_regs_1920_1080_60fps_mipi[] = {
++       /****system****/
++       {0x03fe, 0xf0},
++       {0x03fe, 0xf0},
++       {0x03fe, 0xf0},
++       {0x03fe, 0x00},
++       {0x03f2, 0x00},
++       {0x03f3, 0x00},
++       {0x03f4, 0x36},
++       {0x03f5, 0xc0},
++       {0x03f6, 0x0B},
++       {0x03f7, 0x01},
++      // {0x03f8, 0x58}, //24Mhz
++       {0x03f8, 0x58},  //27Mhz
++       {0x03f9, 0x40},
++       {0x03fc, 0x8e},
++       /****CISCTL & NALOG****/
++       {0x0087, 0x18},
++       {0x00ee, 0x30},
++       {0x00d0, 0xbf},
++       {0x01a0, 0x00},
++       {0x01a4, 0x40},
++       {0x01a5, 0x40},
++       {0x01a6, 0x40},
++       {0x01af, 0x09},
++       {0x0001, 0x00},
++       {0x0002, 0x02},
++       {0x0003, 0x04},
++       {0x0004, 0x02},
++       {0x0005, 0x02},
++       {0x0006, 0x94},
++       {0x0007, 0x00},
++       {0x0008, 0x11},
++       {0x0009, 0x00},
++       {0x000a, 0x02},
++       {0x000b, 0x00},
++       {0x000c, 0x04},
++       {0x000d, 0x04},
++       {0x000e, 0x40},
++       {0x000f, 0x07},
++       {0x0010, 0x8c},
++       {0x0013, 0x15},
++       {0x0019, 0x0c},
++       {0x0041, 0x04},
++	{0x0042, 0xE2},   //frame length 0x04e2=1250
++
++      // {0x0041, 0x05},    //or dorp
++      // {0x0042, 0xE6},    //frame length 0x05E6=1350
++
++       {0x0053, 0x60},
++       {0x008d, 0x92},
++       {0x0090, 0x00},
++       {0x00c7, 0xe1},
++       {0x001b, 0x73},
++       {0x0028, 0x0d},
++       {0x0029, 0x24},
++       {0x002b, 0x04},
++       {0x002e, 0x23},
++       {0x0037, 0x03},
++       {0x0043, 0x04},
++       {0x0044, 0x28},
++       {0x004a, 0x01},
++       {0x004b, 0x20},
++       {0x0055, 0x28},
++       {0x0066, 0x3f},
++       {0x0068, 0x3f},
++       {0x006b, 0x44},
++       {0x0077, 0x00},
++       {0x0078, 0x20},
++       {0x007c, 0xa1},
++       {0x00ce, 0x7c},
++       {0x00d3, 0xd4},
++       {0x00e6, 0x50},
++       /****gain****/
++       {0x00b6, 0xc0},
++       {0x00b0, 0x68},    //0x60
++
++       {0x00b3,0x00},
++       {0x00b8,0x01},
++       {0x00b9,0x00},
++       {0x00b1,0x01},
++       {0x00b2,0x00},
++
++       /*****isp****/
++       //{0x0101, 0x0c},
++       {0x0102, 0x89},
++       {0x0104, 0x01},
++       {0x010f, 0x00},
++       {0x0158, 0x00},
++       {/*dark sun*/},
++       {0x0123, 0x08},
++       {0x0123, 0x00},
++       {0x0120, 0x01},
++       {0x0121, 0x04},
++       {0x0122, 0xd8},
++       {0x0124, 0x03},
++       {0x0125, 0xff},
++       {0x001a, 0x8c},
++       {0x00c6, 0xe0},
++       /****blk****/
++       {0x0026, 0x30},
++       {0x0142, 0x00},
++       {0x0149, 0x1e},
++       {0x014a, 0x0f},
++       {0x014b, 0x00},
++       {0x0155, 0x07},
++       {0x0414, 0x78},
++       {0x0415, 0x78},
++       {0x0416, 0x78},
++       {0x0417, 0x78},
++       {0x0454, 0x78},
++       {0x0455, 0x78},
++       {0x0456, 0x78},
++       {0x0457, 0x78},
++       {0x04e0, 0x18},
++       /****window****/
++       {0x0192, 0x02},
++       {0x0194, 0x03},
++       {0x0195, 0x04},
++       {0x0196, 0x38},
++       {0x0197, 0x07},
++       {0x0198, 0x80},
++       /****DVP & MIP*****/
++       {0x019a, 0x06},
++       {0x007b, 0x2a},
++       {0x0023, 0x2d},
++       {0x0201, 0x27},
++       {0x0202, 0x56},
++       //{0x0203, 0xb6},     //try 0xce or 0x8e  or drop
++       {0x0203, 0x8e},     //try 0xce or 0x8e  or drop
++       {0x0212, 0x80},
++       {0x0213, 0x07},
++       {0x0215, 0x10},
++       {0x003e, 0x91},
++       {GC2093_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list gc2093_stream_on[] = {
++	{GC2093_REG_END, 0x00},
++};
++
++static struct regval_list gc2093_stream_off[] = {
++	{GC2093_REG_END, 0x00},
++};
++
++
++int gc2093_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2]={(reg>>8)&0xff,reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int gc2093_write(struct v4l2_subdev *sd, unsigned short reg,
++			unsigned char value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3]={(reg>>8)&0xff,reg&0xff,value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 3,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int gc2093_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != GC2093_REG_END) {
++		if (vals->reg_num == GC2093_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = gc2093_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++			{
++				printk("array: 0x%02x, 0x%02x\n",vals->reg_num, val);
++				return ret;
++			}
++		}
++		vals++;
++	}
++	return 0;
++}
++static int gc2093_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != GC2093_REG_END) {
++		if (vals->reg_num == GC2093_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = gc2093_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int gc2093_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct gc2093_info *info = to_state(sd);
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(20);
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(20);
++	}
++	return 0;
++}
++
++static int gc2093_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	struct gc2093_info *info = to_state(sd);
++return 0;
++	if(val) {
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++	} else {
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, !info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++	}
++	return 0;
++}
++
++static int gc2093_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct gc2093_info *info = to_state(sd);
++	int ret = 0;
++	struct regval_list*reg = info->win->regs;
++	ret = gc2093_write_array(sd, info->win->regs);
++//#if 0
++//	while(reg->reg_num != gc2093_REG_END)
++//	{
++//			printk("--->reg:0x%02x,value:[0x%02x]\n",reg->reg_num,reg->value);
++//			reg ++;
++//
++//	}
++//#else
++//	ret = gc2093_read_array(sd, info->win->regs);
++//	if (ret<0)
++//#endif
++
++	return ret;
++}
++
++
++
++
++static int gc2093_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++
++
++	ret = gc2093_read(sd, GC2093_REG_CHIP_ID_HIGH, &v);
++	printk("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != GC2093_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = gc2093_read(sd, GC2093_REG_CHIP_ID_LOW, &v);
++	printk("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != GC2093_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	printk(" gc2093 id %x\n", *ident);
++	return 0;
++}
++
++
++static struct gc2093_win_size gc2093_win_sizes[] = {
++	{
++		.sensor_info.mipi_cfg.twidth		= 1920,
++		.sensor_info.mipi_cfg.theight		= 1080,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.fps				= 55 << 16 | 1,
++
++		.width				= 1920,
++		.height				= 1080,
++		.mbus_code	= MEDIA_BUS_FMT_SRGGB10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= gc2093_init_regs_1920_1080_60fps_mipi,
++	},
++
++};
++static const struct gc2093_win_size *gc2093_select_win(u32 *width, u32 *height)
++{
++	int i, default_size = ARRAY_SIZE(gc2093_win_sizes) - 1;
++
++	for (i = 0; i < ARRAY_SIZE(gc2093_win_sizes); i++) {
++		if ((*width >= gc2093_win_sizes[i].width) &&
++				(*height >= gc2093_win_sizes[i].height)) {
++			*width = gc2093_win_sizes[i].width;
++			*height = gc2093_win_sizes[i].height;
++			return &gc2093_win_sizes[i];
++		}
++	}
++
++	*width = gc2093_win_sizes[default_size].width;
++	*height = gc2093_win_sizes[default_size].height;
++	printk("------w=%d,h=%d--default_size=%d---->line=%d,func=%s\n",*width,*height,default_size,__LINE__,__func__);
++	return &gc2093_win_sizes[default_size];
++}
++
++static int gc2093_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_gc2093_FMTS)
++		return -EINVAL;
++
++	code->code = gc2093_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int gc2093_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct gc2093_format_struct *ovfmt;
++	struct gc2093_win_size *wsize;
++	struct gc2093_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++//	info->win = gc2093_select_win(&format->format.width, &format->format.height);
++
++
++	return 0;
++}
++
++static int gc2093_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct gc2093_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	*(unsigned int *)fmt->reserved = &info->win->sensor_info;
++
++	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int gc2093_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2093_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2093_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2093_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int gc2093_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int gc2093_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++#if  0
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(gc2093_again_lut); i++) {
++		lut = &gc2093_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(gc2093_again_lut); i++) {
++		lut = &gc2093_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return -EINVAL;
++}
++#endif
++
++static int gc2093_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++//	printk("~~~g_again=%d\n",*value);
++#if 1
++    return 0;
++#else
++    char v=0;
++    unsigned int reg_val=0;
++    int ret=0;
++    int i=0;
++    int total;
++    total = sizeof(gainLevelTable) / sizeof(unsigned int);
++
++    ret=gc2093_read(sd,0x00b1,&v);
++    reg_val|=(v<<6);
++    ret+=gc2093_read(sd,0x00b2,&v);
++    reg_val|=((v>>2)|0x3f);
++
++    for (i = 0; i < total; i++)
++    {
++        if ((gainLevelTable[i] <= reg_val)&&(reg_val < gainLevelTable[i+1]))
++	{
++		*value=reg_val;
++		break;
++	}
++    }
++    return ret;
++#endif
++}
++/*set analog gain db value, map value to sensor register.*/
++static int gc2093_s_again(struct v4l2_subdev *sd, int value)
++{
++//	printk("~~~s_again=%d\n",value);
++	int index;
++	//return 0;
++
++#if 1
++    int i,ret=0;
++    int total;
++    unsigned int tol_dig_gain = 0;
++
++    total = sizeof(gainLevelTable) / sizeof(unsigned int);
++
++    for (i = 0; i < total; i++)
++    {
++        //if ((regValTable[i][8] <= value)&&(value < regValTable[i+1][8]))
++        if (value <= regValTable_t30[i][7])
++            break;
++    }
++//    printk("~~i=%d,~~~gainLevelTable[i]=%d\n",i,gainLevelTable[i]);
++//    printk("~~~regValTable[i][7]=%d\n",regValTable[i][7]);
++    tol_dig_gain = value*64/regValTable_t30[i][7];
++
++    ret += gc2093_write(sd,0x00b3,regValTable_t30[i][0]);
++    ret += gc2093_write(sd,0x00b8,regValTable_t30[i][1]);
++    ret += gc2093_write(sd,0x00b9,regValTable_t30[i][2]);
++    ret += gc2093_write(sd,0x0155,regValTable_t30[i][3]);
++    gc2093_write(sd,0x031d,0x2d);
++   // ret += gc2093_write(sd,0x00c2,regValTable_t30[i][4]);
++   // ret += gc2093_write(sd,0x00cf,regValTable_t30[i][5]);
++   // ret += gc2093_write(sd,0x00d9,regValTable_t30[i][6]);
++    gc2093_write(sd,0x031d,0x28);
++
++   ret +=gc2093_write(sd,0x00b1,(tol_dig_gain>>6));
++   ret +=gc2093_write(sd,0x00b2,((tol_dig_gain&0x3f)<<2));
++    if (ret < 0) {
++	    printk("gc2093_write error  %d" ,__LINE__ );
++	    return ret;
++    }
++#endif
++    return 0;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int gc2093_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2093_s_exp(struct v4l2_subdev *sd, int intt)
++{
++	int line_frame_total=1200;
++	int frame_length;
++	if(intt>line_frame_total)
++		frame_length=intt+1;
++	else
++		frame_length=line_frame_total;
++	gc2093_write(sd,0x0003,(intt>>8)&0x3f);
++	gc2093_write(sd,0x0004,intt & 0xff);
++	return 0;
++}
++
++static int gc2093_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct gc2093_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return gc2093_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return gc2093_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int gc2093_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct gc2093_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return gc2093_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return gc2093_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return gc2093_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return gc2093_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* gc2093_s_gain turns off auto gain */
++			return gc2093_s_gain(sd, info->gain->val);
++		}
++		return gc2093_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return gc2093_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return gc2093_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return gc2093_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops gc2093_ctrl_ops = {
++	.s_ctrl = gc2093_s_ctrl,
++	.g_volatile_ctrl = gc2093_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int gc2093_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = gc2093_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int gc2093_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	gc2093_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int gc2093_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct gc2093_info *info = to_state(sd);
++	int ret = 0;
++	int val=0;
++	printk("------------>line=%d,func=%s\n",__LINE__,__func__);
++	if (enable) {
++	//	ret = gc2093_write_array(sd, info->win->regs);
++	//	if(ret<0)
++	//		return ret;
++		ret = gc2093_write_array(sd, gc2093_stream_on);
++
++	//	ret = gc2093_read(sd, 0x0199, &val);
++
++		pr_debug("gc2093 stream on\n");
++	printk("----on-------->line=%d,func=%s\n",__LINE__,__func__);
++
++	}
++	else {
++		ret = gc2093_write_array(sd, gc2093_stream_off);
++		pr_debug("gc2093 stream off\n");
++	printk("----off-------->line=%d,func=%s\n",__LINE__,__func__);
++	}
++	return ret;
++}
++
++int gc2093_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct gc2093_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops gc2093_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = gc2093_g_register,
++	.s_register = gc2093_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops gc2093_video_ops = {
++	.s_stream = gc2093_s_stream,
++	.g_frame_interval = gc2093_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops gc2093_pad_ops = {
++	//.enum_frame_interval = gc2093_enum_frame_interval,
++	//.num_frame_size = gc2093_enum_frame_size,
++	//.enum_mbus_code = gc2093_enum_mbus_code,
++	.set_fmt = gc2093_set_fmt,
++	.get_fmt = gc2093_get_fmt,
++};
++
++static const struct v4l2_subdev_ops gc2093_ops = {
++	.core = &gc2093_core_ops,
++	.video = &gc2093_video_ops,
++	.pad = &gc2093_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int gc2093_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_subdev *sd;
++	struct gc2093_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++
++	printk(" gc2093 probe \n\n");
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	v4l2_i2c_subdev_init(sd, client, &gc2093_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++	info->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 27000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++
++	gc2093_reset(sd, 1);
++
++	/* Make sure it's an gc2093 */
++	ret = gc2093_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an gc2093 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++//	gc2093_ircut(sd, 0);
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++		//	V4L2_CID_ANALOGUE_GAIN, 0, 259142, 1, 10000);
++			V4L2_CID_ANALOGUE_GAIN, 0, 405939, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1899 - 4, 1, 1500);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->win = &gc2093_win_sizes[0];//720p
++
++	gc2093_init(sd, 1);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "gc2093 Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int gc2093_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct gc2093_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id gc2093_id[] = {
++	{ "gc2093", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, gc2093_id);
++
++static const struct of_device_id gc2093_of_match[] = {
++	{.compatible = "galaxyc,gc2093", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov2640_of_match);
++
++
++static struct i2c_driver gc2093_driver = {
++	.driver = {
++		.name	= "gc2093",
++		.of_match_table = of_match_ptr(gc2093_of_match),
++	},
++	.probe		= gc2093_probe,
++	.remove		= gc2093_remove,
++	.id_table	= gc2093_id,
++};
++
++module_i2c_driver(gc2093_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for OmniVision gc2093 sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/gm8914_gm8913_gc2093.c b/module_drivers/drivers/media/i2c/ingenic-isp/gm8914_gm8913_gc2093.c
+new file mode 100644
+index 000000000..084b9cf37
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/gm8914_gm8913_gc2093.c
+@@ -0,0 +1,1508 @@
++/*
++ * A V4L2 driver for OmniVision gc2093 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#define DEBUG
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++
++
++#define GC2093_CHIP_ID_H	(0x20)
++#define GC2093_CHIP_ID_L	(0x93)
++#define GC2093_REG_CHIP_ID_HIGH         0x03f0
++#define GC2093_REG_CHIP_ID_LOW          0x03f1
++
++
++#define LHAN 0
++
++
++#define GC2093_REG_END		0xffff
++#define GC2093_REG_DELAY	0x00
++#define GC2093_PAGE_REG	    0xfd
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct gc2093_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int fps;
++	unsigned int mbus_code;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct gc2093_gpio {
++	int pin;
++	int active_level;
++};
++
++struct gc2093_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct gc2093_win_size *win;
++
++	struct gc2093_gpio pwr;
++
++	struct gc2093_gpio reset;
++	struct gc2093_gpio cimen;
++	struct gc2093_gpio ircutp;
++	struct gc2093_gpio ircutn;
++};
++
++
++
++static unsigned int  regValTable_t30[25][8] = {
++       // {0xb3,0xb8,0xb9,0x155,0xc2,0xcf,0xd9},
++	{0x00,0x01,0x00,0x08,0x10,0x08,0x0a,0},
++	{0x10,0x01,0x0c,0x08,0x10,0x08,0x0a,14997},
++	{0x20,0x01,0x1b,0x08,0x11,0x08,0x0c,32233},
++	{0x30,0x01,0x2c,0x08,0x12,0x08,0x0e,46808},
++	{0x40,0x01,0x3f,0x08,0x14,0x08,0x12,60995},
++	{0x50,0x02,0x16,0x08,0x15,0x08,0x14,75348},
++	{0x60,0x02,0x35,0x08,0x17,0x08,0x18,90681},
++	{0x70,0x03,0x16,0x08,0x18,0x08,0x1a,104361},
++	{0x80,0x04,0x02,0x08,0x1a,0x08,0x1e,118021},
++	{0x90,0x04,0x31,0x08,0x1b,0x08,0x20,131438},
++	{0xa0,0x05,0x32,0x08,0x1d,0x08,0x24,145749},
++	{0xb0,0x06,0x35,0x08,0x1e,0x08,0x26,159553},
++	{0xc0,0x08,0x04,0x08,0x20,0x08,0x2a,172553},
++	{0x5a,0x09,0x19,0x08,0x1e,0x08,0x2a,183132},
++	{0x83,0x0b,0x0f,0x08,0x1f,0x08,0x2a,198614},
++	{0x93,0x0d,0x12,0x08,0x21,0x08,0x2e,212697},
++	{0x84,0x10,0x00,0x0b,0x22,0x08,0x30,226175},
++	{0x94,0x12,0x3a,0x0b,0x24,0x08,0x34,240788},
++	{0x5d,0x1a,0x02,0x0b,0x26,0x08,0x34,271536},
++	{0x9b,0x1b,0x20,0x0b,0x26,0x08,0x34,272451},
++	{0x8c,0x20,0x0f,0x0b,0x26,0x08,0x34,287144},
++	{0x9c,0x26,0x07,0x12,0x26,0x08,0x34,302425},
++	{0xB6,0x36,0x21,0x12,0x26,0x08,0x34,334228},
++	{0xad,0x37,0x3a,0x12,0x26,0x08,0x34,351574},
++	{0xbd,0x3d,0x02,0x12,0x26,0x08,0x34,367506},
++};
++unsigned int  gainLevelTable[26] = {
++	64,
++	76,
++	91,
++	107,
++	125,
++	147,
++	177,
++	211,
++	248,
++	297,
++	356,
++	425,
++	504,
++	599,
++	709,
++	836,
++	978,
++	1153,
++	1647,
++	1651,
++	1935,
++	2292,
++	3239,
++	3959,
++	4686,
++	0xffffffff,
++};
++
++/***********************************/
++
++
++struct again_lut {
++	unsigned int index;
++	unsigned char regb0;
++	unsigned char regb1;
++	unsigned int  regb2;
++	unsigned char regb3;
++	unsigned char regb4;
++	unsigned char regb5;
++	unsigned char regb6;
++	unsigned char regb7;
++
++	unsigned int gain;
++};
++
++
++static inline struct gc2093_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct gc2093_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct gc2093_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++static struct regval_list gc2093_init_regs_1920_1080_30fps_mipi[] = {
++/*
++mclk=27mhz
++pclk:74.25Mhz
++Linelength:2200
++row time:29.629us
++frame rate:30fps
++window height:1125 
++size:1920*1080
++*/
++
++/****system****/
++{0x03fe,0x80},
++{0x03fe,0x80},
++{0x03fe,0x80},
++{0x03fe,0x00},
++{0x03f2,0x00}, 
++{0x03f3,0x0f}, 
++{0x03f4,0x36}, 
++{0x03f5,0xc0}, 
++{0x03f6,0x0A}, 
++{0x03f7,0x01}, 
++{0x03f8,0x2C}, 
++{0x03f9,0x10}, 
++{0x03fc,0x8e},
++/****CISCTL & ANALOG****/
++{0x0087,0x18},
++{0x00ee,0x30},
++{0x00d0,0xb7},
++{0x01a0,0x00},
++{0x01a4,0x40},
++{0x01a5,0x40},
++{0x01a6,0x40},
++{0x01af,0x09},
++{0x0001,0x00},
++{0x0002,0x02},
++{0x0003,0x00},
++{0x0004,0x02},
++{0x0005,0x04},
++{0x0006,0x4c},
++{0x0007,0x00},
++{0x0008,0x11},
++{0x0009,0x00},
++{0x000a,0x02},
++{0x000b,0x00},
++{0x000c,0x04},
++{0x000d,0x04},
++{0x000e,0x40},
++{0x000f,0x07},
++{0x0010,0x8c},
++{0x0013,0x15},
++{0x0019,0x0c},
++{0x0041,0x04},
++{0x0042,0x65},
++{0x0053,0x60},
++{0x008d,0x92},
++{0x0090,0x00},
++{0x0053,0x60},
++{0x00c7,0xe1},
++{0x001b,0x73},
++{0x0028,0x0d},
++{0x0029,0x24},
++{0x002b,0x04},
++{0x002e,0x23},
++{0x0037,0x03},
++{0x0043,0x04},
++{0x0044,0x20},
++{0x0046,0x0b},
++{0x004a,0x01},
++{0x004b,0x20},
++{0x0055,0x20},
++{0x0068,0x20},
++{0x0069,0x20},
++{0x0077,0x00},
++{0x0078,0x04},
++{0x007c,0x91},
++{0x00ce,0x7c},
++{0x00d3,0xdc},
++{0x00e6,0x50},
++/*gain*/
++{0x00b6,0xc0},
++{0x00b0,0x60},
++/*isp*/
++{0x0102,0x89},
++{0x0104,0x01},
++/*blk*/
++{0x0026,0x20},
++{0x0142,0x00},
++{0x0149,0x1e},
++{0x014a,0x07},
++{0x014b,0x80},
++{0x0155,0x07},
++{0x0414,0x7e},
++{0x0415,0x7e},
++{0x0416,0x7e},
++{0x0417,0x7e},
++/*window*/
++{0x0192,0x02},
++{0x0194,0x03},
++{0x0195,0x04},
++{0x0196,0x38},
++{0x0197,0x07},
++{0x0198,0x80},
++/****DVP & MIPI****/
++{0x019a,0x06},
++//{0x007b,0x2a},
++{0x0023,0x2d},
++{0x0201,0x20},
++{0x0202,0x56},
++{0x0203,0xb2},
++{0x0212,0x80},
++{0x0213,0x07},
++{0x003e,0x40},
++	
++	{GC2093_REG_END, 0x00},
++};
++
++static struct regval_list gc2093_init_regs_1920_1080_60fps_mipi[] = {
++//mclk=27mhz
++//pclk:148.5Mhz
++//Linelength:2200
++//row time:14.814us
++//frame rate:60fps
++//window height:1125
++//size:1920*1080
++/****system****/
++	{0x03fe, 0x80},
++	{0x03fe, 0x80},
++	{0x03fe, 0x80},
++	{0x03fe, 0x00},
++	{0x03f2, 0x00},
++	{0x03f3, 0x0f},
++	{0x03f4, 0x36},
++	{0x03f5, 0xc0},
++	{0x03f6, 0x42},
++	{0x03f7, 0x01},
++	{0x03f8, 0x2c},
++	{0x03f9, 0x82}, // I2C transfer error, ABORT interrupt
++	{0x03fc, 0x8e},
++	/****CISCTL & ANALOG****/
++	{0x0087, 0x18},
++	{0x00ee, 0x30},
++	{0x00d0, 0xb7},
++	{0x01a0, 0x00},
++	{0x01a4, 0x40},
++	{0x01a5, 0x40},
++	{0x01a6, 0x40},
++	{0x01af, 0x09},
++	{0x0001, 0x00},
++	{0x0002, 0x02},
++	{0x0003, 0x00},
++	{0x0004, 0x02},
++	{0x0005, 0x02},
++	{0x0006, 0x26},
++	{0x0007, 0x00},
++	{0x0008, 0x11},
++	{0x0009, 0x00},
++	{0x000a, 0x02},
++	{0x000b, 0x00},
++	{0x000c, 0x04},
++	{0x000d, 0x04},
++	{0x000e, 0x40},
++	{0x000f, 0x07},
++	{0x0010, 0x8c},
++	{0x0013, 0x15},
++	{0x0019, 0x0c},
++	{0x0041, 0x04},
++	{0x0042, 0x65},
++	{0x0053, 0x60},
++	{0x008d, 0x92},
++	{0x0090, 0x00},
++	{0x0053, 0x60},
++	{0x00c7, 0xe1},
++	{0x001b, 0x73},
++	{0x0028, 0x0d},
++	{0x0029, 0x24},
++	{0x002b, 0x04},
++	{0x002e, 0x23},
++	{0x0037, 0x03},
++	{0x0043, 0x04},
++	{0x0044, 0x20},
++	{0x0046, 0x0b},
++	{0x004a, 0x01},
++	{0x004b, 0x20},
++	{0x0055, 0x20},
++	{0x0068, 0x20},
++	{0x0069, 0x20},
++	{0x0077, 0x00},
++	{0x0078, 0x04},
++	{0x007c, 0x91},
++	{0x00ce, 0x7c},
++	{0x00d3, 0xdc},
++	{0x00e6, 0x50},
++	/*gain*/
++	{0x00b6, 0xc0},
++	{0x00b0, 0x60},
++	/*isp*/
++	{0x0102, 0x89},
++	{0x0104, 0x01},
++	/*blk*/
++	{0x0026, 0x20},
++	{0x0142, 0x00},
++	{0x0149, 0x1e},
++	{0x014a, 0x07},
++	{0x014b, 0x80},
++	{0x0155, 0x07},
++	{0x0414, 0x7e},
++	{0x0415, 0x7e},
++	{0x0416, 0x7e},
++	{0x0417, 0x7e},
++	/*window*/
++	{0x0192, 0x02},
++	{0x0194, 0x03},
++	{0x0195, 0x04},
++	{0x0196, 0x38},
++	{0x0197, 0x07},
++	{0x0198, 0x80},
++	/****DVP & MIPI****/
++	{0x019a, 0x06}, 
++	//{0x007b, 0x2a}, // I2C transfer error, ABORT interrupt
++	{0x0023, 0x2d},
++	{0x0201, 0x20},
++	{0x0202, 0x56},
++	{0x0203, 0xb2},
++	{0x0212, 0x80},
++	{0x0213, 0x07},
++	{0x003e, 0x40},
++	{GC2093_REG_END, 0x00},
++};
++
++static struct regval_list gc2093_stream_on[] = {
++	{GC2093_REG_END, 0x00},
++};
++
++static struct regval_list gc2093_stream_off[] = {
++	{GC2093_REG_END, 0x00},
++};
++
++
++int gc2093_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2]={(reg>>8)&0xff,reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int gc2093_write(struct v4l2_subdev *sd, unsigned short reg,
++			unsigned char value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3]={(reg>>8)&0xff,reg&0xff,value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 3,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int gc2093_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != GC2093_REG_END) {
++		if (vals->reg_num == GC2093_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = gc2093_read(sd, vals->reg_num, &val);
++			printk("%s() 0x%02x, 0x%02x\n", __func__, vals->reg_num, val);
++			if (ret < 0)
++			{
++				return ret;
++			}
++		}
++		vals++;
++	}
++	return 0;
++}
++static int gc2093_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != GC2093_REG_END) {
++		if (vals->reg_num == GC2093_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = gc2093_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int gc2093_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct gc2093_info *info = to_state(sd);
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(20);
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(20);
++	}
++	return 0;
++}
++
++static int gc2093_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	struct gc2093_info *info = to_state(sd);
++return 0;
++	if(val) {
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++	} else {
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, !info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++	}
++	return 0;
++}
++
++
++static int gc2093_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++
++
++	ret = gc2093_read(sd, GC2093_REG_CHIP_ID_HIGH, &v);
++	printk("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != GC2093_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = gc2093_read(sd, GC2093_REG_CHIP_ID_LOW, &v);
++	printk("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != GC2093_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	printk(" gc2093 id %x\n", *ident);
++	return 0;
++}
++
++static int gm8914_i2c_read(unsigned int reg, unsigned int *data);
++static int gm8914_i2c_write(unsigned int reg, unsigned int data);
++static int gm8913_i2c_read(unsigned int reg, unsigned int *data);
++static int gm8913_i2c_write(unsigned int reg, unsigned int data);
++
++
++static int I2C_write(int addr, int reg, int data)
++{
++	switch(addr) {
++	case 0xC0:
++		gm8914_i2c_write(reg, data);
++		break;
++	case 0x32:
++		gm8913_i2c_write(reg, data);
++		break;
++		/*
++	case 0x52:
++		gc2093_i2c_write(reg, data);
++		break;*/
++	default:
++		printk("%s() error slave i2c addr: 0x%x\n", __func__, addr);
++	}
++
++	return;
++}
++
++static int gm8914_gm8913_init(void)
++{
++	I2C_write(0xC0, 0x50, 0x32);
++	I2C_write(0xC0, 0x54, 0x02);
++	I2C_write(0xC0, 0x04, 0x07);
++	mdelay(10);
++
++	I2C_write(0xC0, 0x07, 0x32);
++	mdelay(10);
++	I2C_write(0x32, 0x11, 0x31); // i2c 100kHz
++	I2C_write(0x32, 0x12, 0x31); // i2c 100kHz
++	I2C_write(0x32, 0x53, 0x3f);
++	//I2C_write(0x32, 0x53, 0x0f);
++	mdelay(10);
++	I2C_write(0xC0, 0x08, 0x6e); // sensor id: 0x6e/6f,
++	I2C_write(0xC0, 0x10, 0x52);
++	mdelay(10);
++}
++
++
++static int gc2093_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct gc2093_info *info = to_state(sd);
++	struct i2c_client  *client = v4l2_get_subdevdata(sd);
++	int ret = 0;
++
++	ret = gc2093_write_array(sd, info->win->regs);
++	if (ret < 0) {
++		dev_err(&client->dev, "%s: Error\n", __func__);
++		return ret;
++	}
++#if 1
++	ret = gc2093_read_array(sd, info->win->regs);
++	if (ret < 0) {
++		dev_err(&client->dev, "%s: Error\n", __func__);
++		return ret;
++	}
++#endif
++	return ret;
++}
++
++
++static struct gc2093_win_size gc2093_win_sizes[] = {
++	{
++		.width		= 1920,
++		.height		= 1080,
++		.fps		= 30 << 16 | 1,
++		.mbus_code	= MEDIA_BUS_FMT_SRGGB10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= gc2093_init_regs_1920_1080_30fps_mipi,
++		//.regs 		= gc2093_init_regs_1920_1080_60fps_mipi,
++	},
++
++};
++static const struct gc2093_win_size *gc2093_select_win(u32 *width, u32 *height)
++{
++	int i, default_size = ARRAY_SIZE(gc2093_win_sizes) - 1;
++
++	for (i = 0; i < ARRAY_SIZE(gc2093_win_sizes); i++) {
++		if ((*width >= gc2093_win_sizes[i].width) &&
++				(*height >= gc2093_win_sizes[i].height)) {
++			*width = gc2093_win_sizes[i].width;
++			*height = gc2093_win_sizes[i].height;
++			return &gc2093_win_sizes[i];
++		}
++	}
++
++	*width = gc2093_win_sizes[default_size].width;
++	*height = gc2093_win_sizes[default_size].height;
++	printk("------w=%d,h=%d--default_size=%d---->line=%d,func=%s\n",*width,*height,default_size,__LINE__,__func__);
++	return &gc2093_win_sizes[default_size];
++}
++
++static int gc2093_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_gc2093_FMTS)
++		return -EINVAL;
++
++	code->code = gc2093_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int gc2093_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct gc2093_format_struct *ovfmt;
++	struct gc2093_win_size *wsize;
++	struct gc2093_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++//	info->win = gc2093_select_win(&format->format.width, &format->format.height);
++
++
++	return 0;
++}
++
++static int gc2093_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct gc2093_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++
++
++	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int gc2093_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2093_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2093_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2093_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int gc2093_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int gc2093_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++#if  0
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(gc2093_again_lut); i++) {
++		lut = &gc2093_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(gc2093_again_lut); i++) {
++		lut = &gc2093_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return -EINVAL;
++}
++#endif
++
++static int gc2093_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++//	printk("~~~g_again=%d\n",*value);
++#if 1
++    return 0;
++#else
++    char v=0;
++    unsigned int reg_val=0;
++    int ret=0;
++    int i=0;
++    int total;
++    total = sizeof(gainLevelTable) / sizeof(unsigned int);
++
++    ret=gc2093_read(sd,0x00b1,&v);
++    reg_val|=(v<<6);
++    ret+=gc2093_read(sd,0x00b2,&v);
++    reg_val|=((v>>2)|0x3f);
++
++    for (i = 0; i < total; i++)
++    {
++        if ((gainLevelTable[i] <= reg_val)&&(reg_val < gainLevelTable[i+1]))
++	{
++		*value=reg_val;
++		break;
++	}
++    }
++    return ret;
++#endif
++}
++/*set analog gain db value, map value to sensor register.*/
++static int gc2093_s_again(struct v4l2_subdev *sd, int value)
++{
++//	printk("~~~s_again=%d\n",value);
++	int index;
++	//return 0;
++
++#if 1
++    int i,ret=0;
++    int total;
++    unsigned int tol_dig_gain = 0;
++
++    total = sizeof(gainLevelTable) / sizeof(unsigned int);
++
++    for (i = 0; i < total; i++)
++    {
++        //if ((regValTable[i][8] <= value)&&(value < regValTable[i+1][8]))
++        if (value <= regValTable_t30[i][7])
++            break;
++    }
++//    printk("~~i=%d,~~~gainLevelTable[i]=%d\n",i,gainLevelTable[i]);
++//    printk("~~~regValTable[i][7]=%d\n",regValTable[i][7]);
++    tol_dig_gain = value*64/regValTable_t30[i][7];
++
++    ret += gc2093_write(sd,0x00b3,regValTable_t30[i][0]);
++    ret += gc2093_write(sd,0x00b8,regValTable_t30[i][1]);
++    ret += gc2093_write(sd,0x00b9,regValTable_t30[i][2]);
++    ret += gc2093_write(sd,0x0155,regValTable_t30[i][3]);
++    gc2093_write(sd,0x031d,0x2d);
++   // ret += gc2093_write(sd,0x00c2,regValTable_t30[i][4]);
++   // ret += gc2093_write(sd,0x00cf,regValTable_t30[i][5]);
++   // ret += gc2093_write(sd,0x00d9,regValTable_t30[i][6]);
++    gc2093_write(sd,0x031d,0x28);
++
++   ret +=gc2093_write(sd,0x00b1,(tol_dig_gain>>6));
++   ret +=gc2093_write(sd,0x00b2,((tol_dig_gain&0x3f)<<2));
++    if (ret < 0) {
++	    printk("gc2093_write error  %d" ,__LINE__ );
++	    return ret;
++    }
++#endif
++    return 0;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int gc2093_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int gc2093_s_exp(struct v4l2_subdev *sd, int intt)
++{
++	int line_frame_total=1200;
++	int frame_length;
++	if(intt>line_frame_total)
++		frame_length=intt+1;
++	else
++		frame_length=line_frame_total;
++	gc2093_write(sd,0x0003,(intt>>8)&0x3f);
++	gc2093_write(sd,0x0004,intt & 0xff);
++	return 0;
++}
++
++static int gc2093_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct gc2093_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return gc2093_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return gc2093_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int gc2093_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct gc2093_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return gc2093_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return gc2093_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return gc2093_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return gc2093_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* gc2093_s_gain turns off auto gain */
++			return gc2093_s_gain(sd, info->gain->val);
++		}
++		return gc2093_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return gc2093_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return gc2093_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return gc2093_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops gc2093_ctrl_ops = {
++	.s_ctrl = gc2093_s_ctrl,
++	.g_volatile_ctrl = gc2093_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int gc2093_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = gc2093_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int gc2093_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	gc2093_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int gc2093_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct gc2093_info *info = to_state(sd);
++	int ret = 0;
++	int val=0;
++	printk("------------>line=%d,func=%s\n",__LINE__,__func__);
++	if (enable) {
++	//	ret = gc2093_write_array(sd, info->win->regs);
++	//	if(ret<0)
++	//		return ret;
++		ret = gc2093_write_array(sd, gc2093_stream_on);
++
++	//	ret = gc2093_read(sd, 0x0199, &val);
++
++		pr_debug("gc2093 stream on\n");
++	printk("----on-------->line=%d,func=%s\n",__LINE__,__func__);
++
++	}
++	else {
++		ret = gc2093_write_array(sd, gc2093_stream_off);
++		pr_debug("gc2093 stream off\n");
++	printk("----off-------->line=%d,func=%s\n",__LINE__,__func__);
++	}
++	return ret;
++}
++
++int gc2093_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct gc2093_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops gc2093_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = gc2093_g_register,
++	.s_register = gc2093_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops gc2093_video_ops = {
++	.s_stream = gc2093_s_stream,
++	.g_frame_interval = gc2093_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops gc2093_pad_ops = {
++	//.enum_frame_interval = gc2093_enum_frame_interval,
++	//.num_frame_size = gc2093_enum_frame_size,
++	//.enum_mbus_code = gc2093_enum_mbus_code,
++	.set_fmt = gc2093_set_fmt,
++	.get_fmt = gc2093_get_fmt,
++};
++
++static const struct v4l2_subdev_ops gc2093_ops = {
++	.core = &gc2093_core_ops,
++	.video = &gc2093_video_ops,
++	.pad = &gc2093_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int gc2093_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_subdev *sd;
++	struct gc2093_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++
++	printk(" gc2093 probe \n\n");
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	v4l2_i2c_subdev_init(sd, client, &gc2093_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++	info->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 27000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++
++	gc2093_reset(sd, 1);
++
++	gm8914_gm8913_init();
++
++	/* Make sure it's an gc2093 */
++	ret = gc2093_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an gc2093 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++//	gc2093_ircut(sd, 0);
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++		//	V4L2_CID_ANALOGUE_GAIN, 0, 259142, 1, 10000);
++			V4L2_CID_ANALOGUE_GAIN, 0, 405939, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &gc2093_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1899 - 4, 1, 1500);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->win = &gc2093_win_sizes[0];//720p
++//	info->win = &gc2093_win_sizes[1];//1080*360
++//	info->win = &gc2093_win_sizes[2];//720*360
++
++	gc2093_init(sd, 1);
++
++	gc2093_init(sd, 1);	/* try 2 time init. */
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	}
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "gc2093 Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int gc2093_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct gc2093_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id gc2093_id[] = {
++	{ "gc2093", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, gc2093_id);
++
++static const struct of_device_id gc2093_of_match[] = {
++	{.compatible = "galaxyc,gc2093", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, gc2093_of_match);
++
++
++static struct i2c_driver gc2093_driver = {
++	.driver = {
++		.name	= "gc2093",
++		.of_match_table = of_match_ptr(gc2093_of_match),
++	},
++	.probe		= gc2093_probe,
++	.remove		= gc2093_remove,
++	.id_table	= gc2093_id,
++};
++
++module_i2c_driver(gc2093_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for galaxyc gc2093 sensors");
++MODULE_LICENSE("GPL");
++
++
++/* ================================= GM8913 ===================================== */
++
++struct gm8913_info {
++	struct i2c_client *i2c;
++	struct i2c_device_id *id;
++};
++
++static struct gm8913_info *gm8913info;
++
++static int gm8913_read(struct i2c_client *i2c, unsigned char reg,
++		unsigned char *value)
++{
++	struct i2c_client *client = i2c;
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 1,
++			.buf	= &reg,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int gm8913_write(struct i2c_client *i2c, unsigned char reg,
++			unsigned char value)
++{
++	struct i2c_client *client = i2c;
++	unsigned char buf[2] = {reg, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 2,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int gm8913_i2c_read(unsigned int reg, unsigned int *data)
++{
++	int ret;
++	if (gm8913info==NULL)
++		return -1;
++
++	ret = gm8913_read(gm8913info->i2c, reg, (unsigned char *)data);
++	printk("%s() gm8913info=%p, reg=%02x, data=%02x\n", __func__, gm8913info, reg, *data);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int gm8913_i2c_write(unsigned int reg, unsigned int data)
++{
++	int ret;
++	printk("%s() gm8913info=%p, reg=%02x, data=%02x\n", __func__, gm8913info, reg, data);
++	if (gm8913info==NULL)
++		return -1;
++
++	ret = gm8913_write(gm8913info->i2c, reg, data);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int gm8913_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct gm8913_info *info;
++
++	printk("===========func=%s,line=%d\n\n",__func__,__LINE__);
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	gm8913info = info;
++	info->i2c = client;
++
++	return 0;
++}
++
++static int gm8913_remove(struct i2c_client *client)
++{
++	return 0;
++}
++
++static const struct i2c_device_id gm8913_id[] = {
++	{ "gm8913", 0},
++	{ }
++};
++
++MODULE_DEVICE_TABLE(i2c, gm8913_id);
++
++static const struct of_device_id gm8913_of_match[] = {
++	{.compatible = "zhenxin,gm8913", },
++	{},
++};
++
++MODULE_DEVICE_TABLE(of, gm8913_of_match);
++
++
++static struct i2c_driver gm8913_driver = {
++	.driver = {
++		.name	= "gm8913",
++		.of_match_table = of_match_ptr(gm8913_of_match),
++	},
++	.probe		= gm8913_probe,
++	.remove		= gm8913_remove,
++	.id_table	= gm8913_id,
++};
++
++module_i2c_driver(gm8913_driver);
++
++/* ================================= GM8913 ===================================== */
++
++/* ================================= GM8914 ===================================== */
++
++struct gm8914_info {
++	struct i2c_client *i2c;
++	struct i2c_device_id *id;
++};
++
++static struct gm8914_info *gm8914info;
++
++static int gm8914_read(struct i2c_client *i2c, unsigned char reg,
++		unsigned char *value)
++{
++	struct i2c_client *client = i2c;
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 1,
++			.buf	= &reg,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int gm8914_write(struct i2c_client *i2c, unsigned char reg,
++			unsigned char value)
++{
++	struct i2c_client *client = i2c;
++	unsigned char buf[2] = {reg, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 2,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int gm8914_i2c_read(unsigned int reg, unsigned int *data)
++{
++	int ret;
++	if (gm8914info==NULL)
++		return -1;
++
++	ret = gm8914_read(gm8914info->i2c, reg, (unsigned char *)data);
++	printk("%s() gm8914info=%p, reg=%02x, data=%02x\n", __func__, gm8914info, reg, *data);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int gm8914_i2c_write(unsigned int reg, unsigned int data)
++{
++	int ret;
++	printk("%s() gm8914info=%p, reg=%02x, data=%02x\n", __func__, gm8914info, reg, data);
++	if (gm8914info==NULL)
++		return -1;
++
++	ret = gm8914_write(gm8914info->i2c, reg, data);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int gm8914_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct gm8914_info *info;
++
++	printk("===========func=%s,line=%d\n\n",__func__,__LINE__);
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	gm8914info = info;
++	info->i2c = client;
++
++	return 0;
++}
++
++static int gm8914_remove(struct i2c_client *client)
++{
++	return 0;
++}
++
++static const struct i2c_device_id gm8914_id[] = {
++	{ "gm8914", 0},
++	{ }
++};
++
++MODULE_DEVICE_TABLE(i2c, gm8914_id);
++
++static const struct of_device_id gm8914_of_match[] = {
++	{.compatible = "zhenxin,gm8914", },
++	{},
++};
++
++MODULE_DEVICE_TABLE(of, gm8914_of_match);
++
++
++static struct i2c_driver gm8914_driver = {
++	.driver = {
++		.name	= "gm8914",
++		.of_match_table = of_match_ptr(gm8914_of_match),
++	},
++	.probe		= gm8914_probe,
++	.remove		= gm8914_remove,
++	.id_table	= gm8914_id,
++};
++
++module_i2c_driver(gm8914_driver);
++
++/* ================================= GM8914 ===================================== */
++
++/* ================================= board dts ===================================== */
++#if 0
++&i2c3 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa>;
++
++	gm8914:gm8914@0x60 {
++		status = "ok";
++		compatible = "zhenxin,gm8914";
++		reg = <0x60>;
++	};
++	gm8913:gm8913@0x19 {
++		status = "ok";
++		compatible = "zhenxin,gm8913";
++		reg = <0x19>;
++	};
++
++/* gc8914 sensor slave id :0x37*/
++
++	gc2093:gc2093@0x29 {
++		status = "ok";
++		compatible = "galaxyc,gc2093";
++		reg = <0x29>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vic_pa_low_10bit>;
++
++		port {
++			gc2093_ep0:endpoint {
++				remote-endpoint = <&isp0_ep>;
++				bus-width = <10>;	/* Used data lines */
++				data-shift = <0>;	/* Lines 9:0 are used */
++
++				/* If hsync-active/vsync-active are missing,
++				   embedded BT.656 sync is used */
++				hsync-active = <1>;	/* Active high */
++				vsync-active = <1>;	/* Active high */
++				data-active = <1>;	/* Active high */
++				pclk-sample = <1>;	/* Rising */
++			};
++		};
++
++	};
++
++};
++
++&isp0_ep {
++	remote-endpoint = <&gc2093_ep0>;
++	bus-width = <10>;	/* Used data lines */
++	data-shift = <0>;	/* Lines 9:0 are used */
++
++	/* If hsync-active/vsync-active are missing,
++	   embedded BT.656 sync is used */
++	hsync-active = <1>;	/* Active high */
++	vsync-active = <1>;	/* Active high */
++
++	data-active = <1>;	/* Active high */
++	pclk-sample = <1>;	/* Rising */
++};
++#endif
++/* ================================= board dts ===================================== */
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/hm2140.c b/module_drivers/drivers/media/i2c/ingenic-isp/hm2140.c
+new file mode 100644
+index 000000000..b16d9310d
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/hm2140.c
+@@ -0,0 +1,1091 @@
++/*
++ * A V4L2 driver for Himax HM2140 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++
++#include <isp-sensor.h>
++
++#define HM2140_CHIP_ID_H	(0x21)
++#define HM2140_CHIP_ID_L	(0x40)
++#define HM2140_REG_END		0xff
++#define HM2140_REG_DELAY	0x00
++#define HM2140_PAGE_REG	    0xfd
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct hm2140_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct hm2140_gpio {
++	int pin;
++	int active_level;
++};
++
++struct hm2140_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct hm2140_win_size *win;
++
++	struct hm2140_gpio pwdn;
++	struct hm2140_gpio sync;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++
++struct again_lut hm2140_again_lut[] ={
++	{0x00, 0},
++	{0x01, 4096},
++	{0x02, 8192},
++	{0x03, 12288},
++	{0x04, 16384},
++	{0x05, 20480},
++	{0x06, 24576},
++	{0x07, 28672},
++	{0x08, 32768},
++	{0x09, 36864},
++	{0x0A, 40960},
++	{0x0B, 45056},
++	{0x0C, 49152},
++	{0x0D, 53248},
++	{0x0E, 57344},
++	{0x0F, 61440},
++	{0x10, 65536},
++	{0x12, 69632},
++	{0x14, 73728},
++	{0x16, 77824},
++	{0x18, 81920},
++	{0x1A, 86016},
++	{0x1C, 90112},
++	{0x1E, 94208},
++	{0x20, 98304},
++	{0x22, 102400},
++	{0x24, 106496},
++	{0x26, 110592},
++	{0x28, 114688},
++	{0x2A, 118784},
++	{0x2C, 122880},
++	{0x2E, 126976},
++	{0x30, 131072},
++	{0x34, 135168},
++	{0x38, 139264},
++	{0x3C, 143360},
++	{0x40, 147456},
++	{0x44, 151552},
++	{0x48, 155648},
++	{0x4C, 159744},
++	{0x50, 163840},
++	{0x54, 167936},
++	{0x58, 172032},
++	{0x5C, 176128},
++	{0x60, 180224},
++	{0x64, 184320},
++	{0x68, 188416},
++	{0x6C, 192512},
++	{0x70, 196608},
++};
++
++static inline struct hm2140_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct hm2140_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct hm2140_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++static struct regval_list hm2140_init_regs_1920_1080_30fps_MIPI[] = {
++    {0x0103, 0x00},
++    {HM2140_REG_DELAY, 5},
++    {0x5227, 0x74},
++    {0x030B, 0x11},
++    {HM2140_REG_DELAY, 100},
++    {0x0307, 0x00},
++    {0x0309, 0x00},
++    {0x030A, 0x0A},
++    {0x030D, 0x03},
++    {0x030F, 0x2B},
++    {0x5235, 0xA4},
++    {0x5236, 0x92},
++    {0x5237, 0x23},
++    {0x5238, 0xDC},
++    {0x5239, 0x01},
++    {0x0100, 0x02},
++    {0x4001, 0x00},
++    {0x4002, 0x2B},
++    {0x0101, 0x00},
++    {0x4026, 0x3B},
++    {0x0202, 0x04},
++    {0x0203, 0x92},
++    {0x0340, 0x04},
++    {0x0341, 0x94},
++    {0x0342, 0x08},
++    {0x0343, 0x98},
++    {0x034c, 0x07},
++    {0x034d, 0x80},
++    {0x034e, 0x04},
++    {0x034f, 0x38},
++    {0x0350, 0x73},
++    {0x5015, 0x33},
++    {0x50DD, 0x01},
++    {0x50CB, 0xA3},
++    {0x5004, 0x40},
++    {0x5005, 0x28},
++    {0x504D, 0x7F},
++    {0x504E, 0x00},
++    {0x5040, 0x07},
++    {0x5011, 0x00},
++    {0x501D, 0x4C},
++    {0x5011, 0x0B},
++    {0x5012, 0x01},
++    {0x5013, 0x03},
++    {0x4131, 0x01},
++    {0x5282, 0xFF},
++    {0x5283, 0x07},
++    {0x5010, 0x20},
++    {0x4132, 0x20},
++    {0x50D5, 0xE0},
++    {0x50D7, 0x12},
++    {0x50BB, 0x14},
++    {0x50B7, 0x00},
++    {0x50B8, 0x35},
++    {0x50B9, 0x11},
++    {0x50BA, 0x30},
++    {0x50B3, 0x24},
++    {0x50B4, 0x00},
++    {0x50FA, 0x02},
++    {0x509B, 0x01},
++    {0x50AA, 0xFF},
++    {0x50AB, 0x45},
++    {0x509C, 0x00},
++    {0x50AD, 0x0C},
++    {0x5096, 0x00},
++    {0x50A1, 0x12},
++    {0x50AF, 0x21},
++    {0x50A0, 0x11},
++    {0x50A2, 0x21},
++    {0x509D, 0x20},
++    {0x50AC, 0x55},
++    {0x50AE, 0x26},
++    {0x509E, 0x03},
++    {0x509F, 0x01},
++    {0x5097, 0x12},
++    {0x5099, 0x00},
++    {0x50B5, 0x00},
++    {0x50B6, 0x10},
++    {0x5094, 0x08},
++    {0x5200, 0x43},
++    {0x5201, 0xC0},
++    {0x5202, 0x00},
++    {0x5203, 0x00},
++    {0x5204, 0x00},
++    {0x5205, 0x05},
++    {0x5206, 0xA1},
++    {0x5207, 0x01},
++    {0x5208, 0x0A},
++    {0x5209, 0x0C},
++    {0x520A, 0x00},
++    {0x520B, 0x45},
++    {0x520C, 0x15},
++    {0x520D, 0x40},
++    {0x520E, 0x50},
++    {0x520F, 0x10},
++    {0x5214, 0x40},
++    {0x5215, 0x14},
++    {0x5216, 0x00},
++    {0x5217, 0x02},
++    {0x5218, 0x07},
++    {0x521C, 0x00},
++    {0x521E, 0x00},
++    {0x522A, 0x3F},
++    {0x522C, 0x00},
++    {0x5230, 0x00},
++    {0x5232, 0x05},
++    {0x523A, 0x20},
++    {0x523B, 0x34},
++    {0x523C, 0x03},
++    {0x523D, 0x00},
++    {0x523E, 0x00},
++    {0x523F, 0x70},
++    {0x50E8, 0x16},
++    {0x50E9, 0x00},
++    {0x50EB, 0x0F},
++    {0x4B11, 0x0F},
++    {0x4B12, 0x0F},
++    {0x4B31, 0x04},
++    {0x4B3B, 0x02},
++    {0x4B44, 0x80},
++    {0x4B45, 0x00},
++    {0x4B47, 0x00},
++    {0x4B4E, 0x30},
++    {0x4020, 0x20},
++    {0x5100, 0x13},
++    {0x5101, 0x2B},
++    {0x5102, 0x3B},
++    {0x5103, 0x4B},
++    {0x5104, 0x5F},
++    {0x5105, 0x6F},
++    {0x5106, 0x7F},
++    {0x5108, 0x00},
++    {0x5109, 0x00},
++    {0x510A, 0x00},
++    {0x510B, 0x00},
++    {0x510C, 0x00},
++    {0x510D, 0x00},
++    {0x510E, 0x00},
++    {0x5110, 0x0E},
++    {0x5111, 0x0E},
++    {0x5112, 0x0E},
++    {0x5113, 0x0E},
++    {0x5114, 0x0E},
++    {0x5115, 0x0E},
++    {0x5116, 0x0E},
++    {0x5118, 0x09},
++    {0x5119, 0x09},
++    {0x511A, 0x09},
++    {0x511B, 0x09},
++    {0x511C, 0x09},
++    {0x511D, 0x09},
++    {0x511E, 0x09},
++    {0x5120, 0xEA},
++    {0x5121, 0x6A},
++    {0x5122, 0x6A},
++    {0x5123, 0x6A},
++    {0x5124, 0x6A},
++    {0x5125, 0x6A},
++    {0x5126, 0x6A},
++    {0x5140, 0x0B},
++    {0x5141, 0x1B},
++    {0x5142, 0x2B},
++    {0x5143, 0x3B},
++    {0x5144, 0x4B},
++    {0x5145, 0x5B},
++    {0x5146, 0x6B},
++    {0x5148, 0x02},
++    {0x5149, 0x02},
++    {0x514A, 0x02},
++    {0x514B, 0x02},
++    {0x514C, 0x02},
++    {0x514D, 0x02},
++    {0x514E, 0x02},
++    {0x5150, 0x08},
++    {0x5151, 0x08},
++    {0x5152, 0x08},
++    {0x5153, 0x08},
++    {0x5154, 0x08},
++    {0x5155, 0x08},
++    {0x5156, 0x08},
++    {0x5158, 0x02},
++    {0x5159, 0x02},
++    {0x515A, 0x02},
++    {0x515B, 0x02},
++    {0x515C, 0x02},
++    {0x515D, 0x02},
++    {0x515E, 0x02},
++    {0x5160, 0x66},
++    {0x5161, 0x66},
++    {0x5162, 0x66},
++    {0x5163, 0x66},
++    {0x5164, 0x66},
++    {0x5165, 0x66},
++    {0x5166, 0x66},
++    {0x5180, 0x00},
++    {0x5189, 0x00},
++    {0x5192, 0x00},
++    {0x519B, 0x00},
++    {0x51A4, 0x00},
++    {0x51AD, 0x00},
++    {0x51B6, 0x00},
++    {0x51C0, 0x00},
++    {0x5181, 0x00},
++    {0x518A, 0x00},
++    {0x5193, 0x00},
++    {0x519C, 0x00},
++    {0x51A5, 0x00},
++    {0x51AE, 0x00},
++    {0x51B7, 0x00},
++    {0x51C1, 0x00},
++    {0x5182, 0x85},
++    {0x518B, 0x85},
++    {0x5194, 0x85},
++    {0x519D, 0x85},
++    {0x51A6, 0x85},
++    {0x51AF, 0x85},
++    {0x51B8, 0x85},
++    {0x51C2, 0x85},
++    {0x5183, 0x52},
++    {0x518C, 0x52},
++    {0x5195, 0x52},
++    {0x519E, 0x52},
++    {0x51A7, 0x52},
++    {0x51B0, 0x52},
++    {0x51B9, 0x52},
++    {0x51C3, 0x52},
++    {0x5184, 0x00},
++    {0x518D, 0x00},
++    {0x5196, 0x08},
++    {0x519F, 0x08},
++    {0x51A8, 0x08},
++    {0x51B1, 0x08},
++    {0x51BA, 0x08},
++    {0x51C4, 0x08},
++    {0x5185, 0x73},
++    {0x518E, 0x73},
++    {0x5197, 0x73},
++    {0x51A0, 0x73},
++    {0x51A9, 0x73},
++    {0x51B2, 0x73},
++    {0x51BB, 0x73},
++    {0x51C5, 0x73},
++    {0x5186, 0x34},
++    {0x518F, 0xA4},
++    {0x5198, 0x34},
++    {0x51A1, 0x34},
++    {0x51AA, 0x34},
++    {0x51B3, 0x3F},
++    {0x51BC, 0x3F},
++    {0x51C6, 0x3F},
++    {0x5187, 0x40},
++    {0x5190, 0x38},
++    {0x5199, 0x20},
++    {0x51A2, 0x08},
++    {0x51AB, 0x04},
++    {0x51B4, 0x04},
++    {0x51BD, 0x02},
++    {0x51C7, 0x01},
++    {0x5188, 0x20},
++    {0x5191, 0x40},
++    {0x519A, 0x40},
++    {0x51A3, 0x40},
++    {0x51AC, 0x40},
++    {0x51B5, 0x78},
++    {0x51BE, 0x78},
++    {0x51C8, 0x78},
++    {0x51E1, 0x07},
++    {0x51E3, 0x07},
++    {0x51E5, 0x07},
++    {0x51ED, 0x00},
++    {0x51EE, 0x00},
++    {0x4002, 0x2B},
++    {0x3132, 0x00},
++    {0x4024, 0x40},
++    {0x5229, 0xFC},
++    {0x4002, 0x2B},
++    {0x3110, 0x03},
++    {0x373D, 0x12},
++    {0xBAA2, 0xC0},
++    {0xBAA2, 0x40},
++    {0xBA90, 0x01},
++    {0xBA93, 0x02},
++    {0x350D, 0x01},
++    {0x3514, 0x00},
++    {0x350C, 0x01},
++    {0x3519, 0x00},
++    {0x351A, 0x01},
++    {0x351B, 0x1E},
++    {0x351C, 0x90},
++    {0x351E, 0x05},
++    {0x351D, 0x05},
++    {0x4B20, 0x8E},
++    {0x4B18, 0x00},
++    {0x4B3E, 0x00},
++    {0x4B0E, 0x21},
++#if 0 // test pattern
++    {0x4026, 0x3a},
++    {0x0601, 0x02},
++    {0x3110, 0x01},
++    {0x3735, 0x00},
++    {0x5013, 0x00},
++    {0x501d, 0x04},
++    {0x4131, 0x00},
++#endif
++    {0x0104, 0x01},
++    {0x0104, 0x00},
++    {0x0100, 0x00},
++    {HM2140_REG_END, 0x00}, /* END MARKER */
++};
++
++
++static struct regval_list hm2140_stream_on[] = {
++	{0x0100, 0x01},
++	{HM2140_REG_END, 0x00},
++};
++
++static struct regval_list hm2140_stream_off[] = {
++	{0x0100, 0x00},
++	{HM2140_REG_END, 0x00},
++};
++
++/* read a register */
++static int hm2140_read(struct v4l2_subdev *sd, uint16_t reg, uint8_t *val)
++{
++	int ret;
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(uint8_t)((reg & 0xFF00) >> 8), (uint8_t)((reg & 0x00FF))};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr   = client->addr,
++			.flags  = 0,
++			.len    = 2,
++			.buf    = buf,
++		},
++		[1] = {
++			.addr   = client->addr,
++			.flags  = I2C_M_RD,
++			.len    = 1,
++			.buf    = val,
++		},
++	};
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret < 0) {
++		dev_err(&client->dev, "Failed reading register 0x%04x!\n", reg);
++		return ret;
++	}
++
++	return 0;
++}
++
++/* write a register */
++static int hm2140_write(struct v4l2_subdev *sd, uint16_t reg, uint8_t val)
++{
++	int ret;
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3];
++	struct i2c_msg msg;
++
++	buf[0] = (uint8_t)((reg & 0xFF00) >> 8);
++	buf[1] = (uint8_t)((reg & 0x00FF));
++	buf[2] = val;
++
++	msg.addr        = client->addr;
++	msg.flags       = 0;
++	msg.len         = 3;
++	msg.buf         = buf;
++
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret < 0) {
++		dev_err(&client->dev, "Failed writing register 0x%04x!\n", reg);
++		return ret;
++	}
++
++	return 0;
++} 
++
++static int hm2140_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != HM2140_REG_END) {
++		if (vals->reg_num == HM2140_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = hm2140_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++			if (vals->reg_num == HM2140_PAGE_REG){
++				val &= 0xf8;
++				val |= (vals->value & 0x07);
++				ret = hm2140_write(sd, vals->reg_num, val);
++				ret = hm2140_read(sd, vals->reg_num, &val);
++			}
++		}
++		vals++;
++	}
++	return 0;
++}
++static int hm2140_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != HM2140_REG_END) {
++		if (vals->reg_num == HM2140_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = hm2140_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int hm2140_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct hm2140_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->pwdn.pin, info->pwdn.active_level);
++		msleep(10);
++		gpio_direction_output(info->pwdn.pin, !info->pwdn.active_level);
++		msleep(10);
++	}
++	return 0;
++}
++
++
++static int hm2140_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++
++	ret = hm2140_read(sd, 0x0000, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != HM2140_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = hm2140_read(sd, 0x0001, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != HM2140_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	return 0;
++}
++
++
++static struct hm2140_win_size hm2140_win_sizes[] = {
++	/* 1920*1080 */
++	{
++		.width		= 1920,
++		.height		= 1080,
++		.sensor_info.fps		= 30 << 16 | 1,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= hm2140_init_regs_1920_1080_30fps_MIPI,
++	}
++};
++
++static int hm2140_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_HM2140_FMTS)
++		return -EINVAL;
++
++	code->code = hm2140_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int hm2140_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct hm2140_format_struct *ovfmt;
++	struct hm2140_win_size *wsize;
++	struct hm2140_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int hm2140_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct hm2140_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	*(unsigned int *)fmt->reserved = &info->win->sensor_info;
++
++
++//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int hm2140_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int hm2140_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int hm2140_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int hm2140_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int hm2140_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int hm2140_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(hm2140_again_lut); i++) {
++		lut = &hm2140_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(hm2140_again_lut); i++) {
++		lut = &hm2140_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return -EINVAL;
++}
++
++static int hm2140_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	struct hm2140_info *info = to_state(sd);
++	char v = 0;
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++
++	ret += hm2140_read(sd, 0x0205, &v);
++	reg_val |= v;
++
++	*value = regval_to_again(reg_val);
++	return ret;
++}
++
++static int hm2140_s_again(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++	struct hm2140_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int i;
++
++	printk("[%s %d ]````\n", __func__, __LINE__);
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(value);
++	}
++
++	ret += hm2140_write(sd, 0x0205, (unsigned char)(reg_value & 0xff));
++	ret += hm2140_write(sd, 0x0104, 0x01);
++	if (ret < 0)
++		return ret;
++
++	return ret;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int hm2140_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int hm2140_s_exp(struct v4l2_subdev *sd, int value)
++{
++	struct hm2140_info *info = to_state(sd);
++	int ret = 0;
++	ret += hm2140_write(sd, 0x0203, ((unsigned char)(value & 0xff)));
++	ret += hm2140_write(sd, 0x0202, ((unsigned char)(value >> 8)) & 0xff);
++	ret += hm2140_write(sd, 0x0104, 0x01);
++	return 0;
++}
++
++static int hm2140_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct hm2140_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return -EINVAL; //hm2140_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return hm2140_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int hm2140_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct hm2140_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return hm2140_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return hm2140_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return hm2140_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return hm2140_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* hm2140_s_gain turns off auto gain */
++			return hm2140_s_gain(sd, info->gain->val);
++		}
++		return hm2140_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return hm2140_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return hm2140_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return hm2140_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops hm2140_ctrl_ops = {
++	.s_ctrl = hm2140_s_ctrl,
++	.g_volatile_ctrl = hm2140_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int hm2140_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = hm2140_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int hm2140_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	hm2140_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int hm2140_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	int ret = 0;
++
++	if (enable) {
++		ret = hm2140_write_array(sd, hm2140_stream_on);
++		printk("hm2140 stream on\n");
++	}
++	else {
++		ret = hm2140_write_array(sd, hm2140_stream_off);
++		printk("hm2140 stream off\n");
++	}
++	return ret;
++}
++
++
++int hm2140_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct hm2140_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops hm2140_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = hm2140_g_register,
++	.s_register = hm2140_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops hm2140_video_ops = {
++	.s_stream = hm2140_s_stream,
++	.g_frame_interval = hm2140_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops hm2140_pad_ops = {
++	//.enum_frame_interval = hm2140_enum_frame_interval,
++	//.num_frame_size = hm2140_enum_frame_size,
++	//.enum_mbus_code = hm2140_enum_mbus_code,
++	.set_fmt = hm2140_set_fmt,
++	.get_fmt = hm2140_get_fmt,
++};
++
++static const struct v4l2_subdev_ops hm2140_ops = {
++	.core = &hm2140_core_ops,
++	.video = &hm2140_video_ops,
++	.pad = &hm2140_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int hm2140_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_subdev *sd;
++	struct hm2140_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++
++	printk("------------%s, %d\n", __func__, __LINE__);
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,pwdn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->pwdn.pin = gpio;
++		info->pwdn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,sync-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->sync.pin = gpio;
++		info->sync.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	v4l2_i2c_subdev_init(sd, client, &hm2140_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++	info->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++
++	info->win = &hm2140_win_sizes[0];
++
++	hm2140_reset(sd, 1);
++	/* Make sure it's an hm2140 */
++	ret = hm2140_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an hm2140 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++	ret = hm2140_write_array(sd, info->win->regs);
++	if (ret) {
++		v4l_err(client,
++			"hm2140 init failed!\n");
++		return ret;
++	}
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &hm2140_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &hm2140_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &hm2140_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &hm2140_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &hm2140_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &hm2140_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 262144, 1, 1);
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &hm2140_ctrl_ops,
++			V4L2_CID_EXPOSURE, 1, 1080, 1, 0x0108);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "hm2140 Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int hm2140_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct hm2140_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id hm2140_id[] = {
++	{ "hm2140", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, hm2140_id);
++
++static const struct of_device_id hm2140_of_match[] = {
++	{.compatible = "himax,hm2140", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, hm2140_of_match);
++
++
++static struct i2c_driver hm2140_driver = {
++	.driver = {
++		.name	= "hm2140",
++		.of_match_table = of_match_ptr(hm2140_of_match),
++	},
++	.probe		= hm2140_probe,
++	.remove		= hm2140_remove,
++	.id_table	= hm2140_id,
++};
++
++module_i2c_driver(hm2140_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for Himax hm2140 sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/imx335.c b/module_drivers/drivers/media/i2c/ingenic-isp/imx335.c
+new file mode 100644
+index 000000000..4a68885db
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/imx335.c
+@@ -0,0 +1,1429 @@
++/*
++ * A V4L2 driver for Sony imx335 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ *
++ * imx335 datasheet description:
++ * Input frequency: 6 to 27 MHz / 37.125 MHz / 74.25 MHz
++ * â—† Built-in timing adjustment circuit, H/V driver and serial communication circuit
++ * ◆ Number of recommended recording pixels: 2592 (H) × 1944 (V) approx. 5.04M pixel
++ * uboot epll clock config:#define CONFIG_SYS_EPLL_FREQ           297000000
++ */
++#define DEBUG
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++#include <linux/clk.h>
++
++#include <isp-sensor.h>
++
++#define IMX335_CHIP_ID_H	(0x08)
++#define IMX335_CHIP_ID_L	(0x00)
++#define IMX335_REG_CHIP_ID_HIGH         0x3112
++#define IMX335_REG_CHIP_ID_LOW          0x3113
++#define IMX335_REG_END		0xffff
++#define IMX335_REG_DELAY	0x00
++#define IMX335_PAGE_REG	    0xfd
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct imx335_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct imx335_gpio {
++	int pin;
++	int active_level;
++};
++
++struct imx335_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++	struct clk *sclka;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct imx335_win_size *win;
++
++	struct imx335_gpio pwr;
++
++	struct imx335_gpio reset;
++	struct imx335_gpio pwdn;
++	struct imx335_gpio ircutp;
++	struct imx335_gpio ircutn;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;
++	unsigned int gain;
++};
++
++static inline struct imx335_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct imx335_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct imx335_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++
++struct again_lut imx335_again_lut[] = {
++	/* analog gain */
++	{0x0, 0},
++	{0x1, 3265},
++	{0x2, 6531},
++	{0x3, 9796},
++	{0x4, 13062},
++	{0x5, 16327},
++	{0x6, 19593},
++	{0x7, 22859},
++	{0x8, 26124},
++	{0x9, 29390},
++	{0xa, 32655},
++	{0xb, 35921},
++	{0xc, 39187},
++	{0xd, 42452},
++	{0xe, 45718},
++	{0xf, 48983},
++	{0x10, 52249},
++	{0x11, 55514},
++	{0x12, 58780},
++	{0x13, 62046},
++	{0x14, 65311},
++	{0x15, 68577},
++	{0x16, 71842},
++	{0x17, 75108},
++	{0x18, 78374},
++	{0x19, 81639},
++	{0x1a, 84905},
++	{0x1b, 88170},
++	{0x1c, 91436},
++	{0x1d, 94702},
++	{0x1e, 97967},
++	{0x1f, 101233},
++	{0x20, 104498},
++	{0x21, 107764},
++	{0x22, 111029},
++	{0x23, 114295},
++	{0x24, 117561},
++	{0x25, 120826},
++	{0x26, 124092},
++	{0x27, 127357},
++	{0x28, 130623},
++	{0x29, 133889},
++	{0x2a, 137154},
++	{0x2b, 140420},
++	{0x2c, 143685},
++	{0x2d, 146951},
++	{0x2e, 150217},
++	{0x2f, 153482},
++	{0x30, 156748},
++	{0x31, 160013},
++	{0x32, 163279},
++	{0x33, 166544},
++	{0x34, 169810},
++	{0x35, 173076},
++	{0x36, 176341},
++	{0x37, 179607},
++	{0x38, 182872},
++	{0x39, 186138},
++	{0x3a, 189404},
++	{0x3b, 192669},
++	{0x3c, 195935},
++	{0x3d, 199200},
++	{0x3e, 202466},
++	{0x3f, 205732},
++	{0x40, 208997},
++	{0x41, 212263},
++	{0x42, 215528},
++	{0x43, 218794},
++	{0x44, 222059},
++	{0x45, 225325},
++	{0x46, 228591},
++	{0x47, 231856},
++	{0x48, 235122},
++	{0x49, 238387},
++	{0x4a, 241653},
++	{0x4b, 244919},
++	{0x4c, 248184},
++	{0x4d, 251450},
++	{0x4e, 254715},
++	{0x4f, 257981},
++	{0x50, 261247},
++	{0x51, 264512},
++	{0x52, 267778},
++	{0x53, 271043},
++	{0x54, 274309},
++	{0x55, 277574},
++	{0x56, 280840},
++	{0x57, 284106},
++	{0x58, 287371},
++	{0x59, 290637},
++	{0x5a, 293902},
++	{0x5b, 297168},
++	{0x5c, 300434},
++	{0x5d, 303699},
++	{0x5e, 306965},
++	{0x5f, 310230},
++	{0x60, 313496},
++	{0x61, 316762},
++	{0x62, 320027},
++	{0x63, 323293},
++	{0x64, 326558},
++	/* analog+digital */
++	{0x65, 329824},
++	{0x66, 333089},
++	{0x67, 336355},
++	{0x68, 339621},
++	{0x69, 342886},
++	{0x6a, 346152},
++	{0x6b, 349417},
++	{0x6c, 352683},
++	{0x6d, 355949},
++	{0x6e, 359214},
++	{0x6f, 362480},
++	{0x70, 365745},
++	{0x71, 369011},
++	{0x72, 372277},
++	{0x73, 375542},
++	{0x74, 378808},
++	{0x75, 382073},
++	{0x76, 385339},
++	{0x77, 388604},
++	{0x78, 391870},
++	{0x79, 395136},
++	{0x7a, 398401},
++	{0x7b, 401667},
++	{0x7c, 404932},
++	{0x7d, 408198},
++	{0x7e, 411464},
++	{0x7f, 414729},
++	{0x80, 417995},
++	{0x81, 421260},
++	{0x82, 424526},
++	{0x83, 427792},
++	{0x84, 431057},
++	{0x85, 434323},
++	{0x86, 437588},
++	{0x87, 440854},
++	{0x88, 444119},
++	{0x89, 447385},
++	{0x8a, 450651},
++	{0x8b, 453916},
++	{0x8c, 457182},
++	{0x8d, 460447},
++	{0x8e, 463713},
++	{0x8f, 466979},
++	{0x90, 470244},
++	{0x91, 473510},
++	{0x92, 476775},
++	{0x93, 480041},
++	{0x94, 483307},
++	{0x95, 486572},
++	{0x96, 489838},
++	{0x97, 493103},
++	{0x98, 496369},
++	{0x99, 499634},
++	{0x9a, 502900},/*204x*/
++	{0x9b, 506166},
++	{0x9c, 509431},
++	{0x9d, 512697},
++	{0x9e, 515962},
++	{0x9f, 519228},
++	{0xa0, 522494},
++	{0xa1, 525759},
++	{0xa2, 529025},
++	{0xa3, 532290},
++	{0xa4, 535556},
++	{0xa5, 538822},
++	{0xa6, 542087},
++	{0xa7, 545353},
++	{0xa8, 548618},
++	{0xa9, 551884},
++	{0xaa, 555149},
++	{0xab, 558415},
++	{0xac, 561681},
++	{0xad, 564946},
++	{0xae, 568212},
++	{0xaf, 571477},
++	{0xb0, 574743},
++	{0xb1, 578009},
++	{0xb2, 581274},
++	{0xb3, 584540},
++	{0xb4, 587805},
++	{0xb5, 591071},
++	{0xb6, 594337},
++	{0xb7, 597602},
++	{0xb8, 600868},
++	{0xb9, 604133},
++	{0xba, 607399},
++	{0xbb, 610664},
++	{0xbc, 613930},
++	{0xbd, 617196},
++	{0xbe, 620461},
++	{0xbf, 623727},
++	{0xc0, 626992},
++	{0xc1, 630258},
++	{0xc2, 633524},
++	{0xc3, 636789},
++	{0xc4, 640055},
++	{0xc5, 643320},
++	{0xc6, 646586},
++	{0xc7, 649852},
++	{0xc8, 653117},
++	{0xc9, 656383},
++	{0xca, 659648},
++	{0xcb, 662914},
++	{0xcc, 666179},
++	{0xcd, 669445},
++	{0xce, 672711},
++	{0xcf, 675976},
++	{0xd0, 679242},
++	{0xd1, 682507},
++	{0xd2, 685773},
++	{0xd3, 689039},
++	{0xd4, 692304},
++	{0xd5, 695570},
++	{0xd6, 698835},
++	{0xd7, 702101},
++	{0xd8, 705367},
++	{0xd9, 708632},
++	{0xda, 711898},
++	{0xdb, 715163},
++	{0xdc, 718429},
++	{0xdd, 721694},
++	{0xde, 724960},
++	{0xdf, 728226},
++	{0xe0, 731491},
++	{0xe1, 734757},
++	{0xe2, 738022},
++	{0xe3, 741288},
++	{0xe4, 744554},
++	{0xe5, 747819},
++	{0xe6, 751085},
++	{0xe7, 754350},
++	{0xe8, 757616},
++	{0xe9, 760882},
++	{0xea, 764147},
++	{0xeb, 767413},
++	{0xec, 770678},
++	{0xed, 773944},
++	{0xee, 777209},
++	{0xef, 780475},
++	{0xf0, 783741},
++};
++
++/***********************************/
++
++static struct regval_list imx335_init_regs_2592_1944_15fps_mipi[] = {
++	{0x3000, 0x01},
++	{0x3001, 0x00},
++	{0x3002, 0x01},
++	{0x3004, 0x00},
++	{0x300C, 0x5B},
++	{0x300D, 0x40},
++	{0x3018, 0x00},
++	{0x302C, 0x30},
++	{0x302D, 0x00},
++	{0x302E, 0x38},
++	{0x302F, 0x0A},
++	{0x3030, 0x1d},
++	{0x3031, 0x10},
++	{0x3032, 0x00},
++	{0x3034, 0xb0},
++	{0x3035, 0x04},/* 20fps 0x384 */
++	{0x3048, 0x00},
++	{0x3049, 0x00},
++	{0x304A, 0x03},
++	{0x304B, 0x01},
++	{0x304C, 0x14},
++	{0x304E, 0x00},
++	{0x304F, 0x00},/* vflip */
++	{0x3050, 0x00},
++	{0x3056, 0xAC},
++	{0x3057, 0x07},
++	{0x3058, 0x09},
++	{0x3059, 0x00},
++	{0x305A, 0x00},
++	{0x305C, 0x12},
++	{0x305D, 0x00},
++	{0x305E, 0x00},
++	{0x3060, 0xE8},
++	{0x3061, 0x00},
++	{0x3062, 0x00},
++	{0x3064, 0x09},
++	{0x3065, 0x00},
++	{0x3066, 0x00},
++	{0x3068, 0xCE},
++	{0x3069, 0x00},
++	{0x306A, 0x00},
++	{0x306C, 0x68},
++	{0x306D, 0x06},
++	{0x306E, 0x00},
++	{0x3072, 0x28},
++	{0x3073, 0x00},
++	{0x3074, 0xB0},
++	{0x3075, 0x00},
++	{0x3076, 0x58},
++	{0x3077, 0x0F},
++	{0x3078, 0x01},
++	{0x3079, 0x02},
++	{0x307A, 0xFF},
++	{0x307B, 0x02},
++	{0x307C, 0x00},
++	{0x307D, 0x00},
++	{0x307E, 0x00},
++	{0x307F, 0x00},
++	{0x3080, 0x01},
++	{0x3081, 0x02},
++	{0x3082, 0xFF},
++	{0x3083, 0x02},
++	{0x3084, 0x00},
++	{0x3085, 0x00},
++	{0x3086, 0x00},
++	{0x3087, 0x00},
++	{0x30A4, 0x33},
++	{0x30A8, 0x10},
++	{0x30A9, 0x04},
++	{0x30AC, 0x00},
++	{0x30AD, 0x00},
++	{0x30B0, 0x10},
++	{0x30B1, 0x08},
++	{0x30B4, 0x00},
++	{0x30B5, 0x00},
++	{0x30B6, 0x00},
++	{0x30B7, 0x00},
++	{0x30C6, 0x00},
++	{0x30C7, 0x00},
++	{0x30CE, 0x00},
++	{0x30CF, 0x00},
++	{0x30D8, 0x4C},
++	{0x30D9, 0x10},
++	{0x30E8, 0x00},
++	{0x30E9, 0x00},
++	{0x30EA, 0x00},
++	{0x30EB, 0x00},
++	{0x30EC, 0x00},
++	{0x30ED, 0x00},
++	{0x30EE, 0x00},
++	{0x30EF, 0x00},
++	{0x3112, 0x08},
++	{0x3113, 0x00},
++	{0x3116, 0x08},
++	{0x3117, 0x00},
++	{0x314C, 0x80},
++	{0x314D, 0x00},
++	{0x315A, 0x06},
++	{0x3167, 0x01},
++	{0x3168, 0x68},
++	{0x316A, 0x7E},
++	{0x3199, 0x00},
++	{0x319D, 0x00},
++	{0x319E, 0x03},
++	{0x31A0, 0x2A},
++	{0x31A1, 0x00},
++	{0x31D4, 0x00},
++	{0x31D5, 0x00},
++	{0x3288, 0x21},
++	{0x328A, 0x02},
++	{0x3300, 0x00},
++	{0x3302, 0x32},
++	{0x3303, 0x00},
++	{0x3414, 0x05},
++	{0x3416, 0x18},
++	{0x341C, 0xff},//0xFF},
++	{0x341D, 0x01},
++	{0x3648, 0x01},
++	{0x364A, 0x04},
++	{0x364C, 0x04},
++	{0x3678, 0x01},
++	{0x367C, 0x31},
++	{0x367E, 0x31},
++	{0x3706, 0x10},
++	{0x3708, 0x03},
++	{0x3714, 0x02},
++	{0x3715, 0x02},
++	{0x3716, 0x01},
++	{0x3717, 0x03},
++	{0x371C, 0x3D},
++	{0x371D, 0x3F},
++	{0x372C, 0x00},
++	{0x372D, 0x00},
++	{0x372E, 0x46},
++	{0x372F, 0x00},
++	{0x3730, 0x89},
++	{0x3731, 0x00},
++	{0x3732, 0x08},
++	{0x3733, 0x01},
++	{0x3734, 0xFE},
++	{0x3735, 0x05},
++	{0x3740, 0x02},
++	{0x375D, 0x00},
++	{0x375E, 0x00},
++	{0x375F, 0x11},
++	{0x3760, 0x01},
++	{0x3768, 0x1B},
++	{0x3769, 0x1B},
++	{0x376A, 0x1B},
++	{0x376B, 0x1B},
++	{0x376C, 0x1A},
++	{0x376D, 0x17},
++	{0x376E, 0x0F},
++	{0x3776, 0x00},
++	{0x3777, 0x00},
++	{0x3778, 0x46},
++	{0x3779, 0x00},
++	{0x377A, 0x89},
++	{0x377B, 0x00},
++	{0x377C, 0x08},
++	{0x377D, 0x01},
++	{0x377E, 0x23},
++	{0x377F, 0x02},
++	{0x3780, 0xD9},
++	{0x3781, 0x03},
++	{0x3782, 0xF5},
++	{0x3783, 0x06},
++	{0x3784, 0xA5},
++	{0x3788, 0x0F},
++	{0x378A, 0xD9},
++	{0x378B, 0x03},
++	{0x378C, 0xEB},
++	{0x378D, 0x05},
++	{0x378E, 0x87},
++	{0x378F, 0x06},
++	{0x3790, 0xF5},
++	{0x3792, 0x43},
++	{0x3794, 0x7A},
++	{0x3796, 0xA1},
++	{0x37B0, 0x36},
++	{0x3A01, 0x01},
++	{0x3A04, 0x48},
++	{0x3A05, 0x09},
++	{0x3A18, 0x67},
++	{0x3A19, 0x00},
++	{0x3A1A, 0x27},
++	{0x3A1B, 0x00},
++	{0x3A1C, 0x27},
++	{0x3A1D, 0x00},
++	{0x3A1E, 0xB7},
++	{0x3A1F, 0x00},
++	{0x3A20, 0x2F},
++	{0x3A21, 0x00},
++	{0x3A22, 0x4F},
++	{0x3A23, 0x00},
++	{0x3A24, 0x2F},
++	{0x3A25, 0x00},
++	{0x3A26, 0x47},
++	{0x3A27, 0x00},
++	{0x3A28, 0x27},
++	{0x3A29, 0x00},
++
++	/*pattern generator*/
++#ifdef IMX335_TESTPATTERN
++	{0x3148, 0x10},
++	{0x3280, 0x00},
++	{0x329c, 0x01},
++	{0x329e, 0x0b},
++	{0x32a0, 0x11},/*tpg colorwidth*/
++#endif
++	{0x3002, 0x00},
++	{0x3000, 0x00},
++
++	{IMX335_REG_END, 0x00},/* END MARKER */
++};
++
++static struct regval_list imx335_init_regs_2592_1944_25fps_mipi[] = {
++	{0x3000, 0x01},
++	{0x3001, 0x00},
++	{0x3002, 0x01},
++	{0x3004, 0x00},
++	{0x300c, 0x5b},
++	{0x300d, 0x40},
++	{0x3018, 0x00},
++	{0x302c, 0x30},
++	{0x302d, 0x00},
++	{0x302e, 0x38},
++	{0x302f, 0x0a},
++	{0x3030, 0x18},
++	{0x3031, 0x15},//1518
++	{0x3032, 0x00},
++	{0x3034, 0x26},
++	{0x3035, 0x02},
++	{0x3050, 0x00},
++	{0x315a, 0x02},
++	{0x316a, 0x7e},
++	{0x319d, 0x00},
++	{0x31a1, 0x00},
++	{0x3288, 0x21},
++	{0x328a, 0x02},
++	{0x3414, 0x05},
++	{0x3416, 0x18},
++	{0x341c, 0xff},
++	{0x341d, 0x01},
++	{0x3648, 0x01},
++	{0x364a, 0x04},
++	{0x364c, 0x04},
++	{0x3678, 0x01},
++	{0x367c, 0x31},
++	{0x367e, 0x31},
++	{0x3706, 0x10},
++	{0x3708, 0x03},
++	{0x3714, 0x02},
++	{0x3715, 0x02},
++	{0x3716, 0x01},
++	{0x3717, 0x03},
++	{0x371c, 0x3d},
++	{0x371d, 0x3f},
++	{0x372c, 0x00},
++	{0x372d, 0x00},
++	{0x372e, 0x46},
++	{0x372f, 0x00},
++	{0x3730, 0x89},
++	{0x3731, 0x00},
++	{0x3732, 0x08},
++	{0x3733, 0x01},
++	{0x3734, 0xfe},
++	{0x3735, 0x05},
++	{0x3740, 0x02},
++	{0x375d, 0x00},
++	{0x375e, 0x00},
++	{0x375f, 0x11},
++	{0x3760, 0x01},
++	{0x3768, 0x1b},
++	{0x3769, 0x1b},
++	{0x376a, 0x1b},
++	{0x376b, 0x1b},
++	{0x376c, 0x1a},
++	{0x376d, 0x17},
++	{0x376e, 0x0f},
++	{0x3776, 0x00},
++	{0x3777, 0x00},
++	{0x3778, 0x46},
++	{0x3779, 0x00},
++	{0x377a, 0x89},
++	{0x377b, 0x00},
++	{0x377c, 0x08},
++	{0x377d, 0x01},
++	{0x377e, 0x23},
++	{0x377f, 0x02},
++	{0x3780, 0xd9},
++	{0x3781, 0x03},
++	{0x3782, 0xf5},
++	{0x3783, 0x06},
++	{0x3784, 0xa5},
++	{0x3788, 0x0f},
++	{0x378a, 0xd9},
++	{0x378b, 0x03},
++	{0x378c, 0xeb},
++	{0x378d, 0x05},
++	{0x378e, 0x87},
++	{0x378f, 0x06},
++	{0x3790, 0xf5},
++	{0x3792, 0x43},
++	{0x3794, 0x7a},
++	{0x3796, 0xa1},
++	{0x3a01, 0x01},
++	/*pattern generator*/
++#ifdef IMX335_TESTPATTERN
++	{0x3148, 0x10},
++	{0x3280, 0x00},
++	{0x329c, 0x01},
++	{0x329e, 0x0b},
++	{0x32a0, 0x11},/*tpg colorwidth*/
++#endif
++	{0x3002, 0x00},
++	{0x3000, 0x00},
++	{IMX335_REG_END, 0x00},/* END MARKER */
++};
++
++/*
++ * the part of driver was fixed.
++ */
++static struct regval_list imx335_stream_on_mipi[] = {
++	{0x3000, 0x00},
++	{IMX335_REG_END, 0x00},
++};
++
++static struct regval_list imx335_stream_off_mipi[] = {
++	{0x3000, 0x01},
++	{IMX335_REG_END, 0x00},
++};
++
++int imx335_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret = 0;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int imx335_write(struct v4l2_subdev *sd, unsigned short reg,
++			unsigned char value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3] = {(reg>>8)&0xff, reg&0xff, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 3,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int imx335_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != IMX335_REG_END) {
++		if (vals->reg_num == IMX335_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = imx335_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++			{
++				printk("array: 0x%02x, 0x%02x\n",vals->reg_num, val);
++				return ret;
++			}
++		}
++		vals++;
++	}
++	return 0;
++}
++
++/*
++ * Write a list of register settings; ff/ff stops the process.
++ */
++static int imx335_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != IMX335_REG_END) {
++		if (vals->reg_num == IMX335_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = imx335_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int imx335_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct imx335_info *info = to_state(sd);
++		gpio_direction_output(info->pwdn.pin, info->pwdn.active_level);
++//		printk("==========file=%s,func=%s,line=%d,pwdn=%d,level=%d,\n\n",__FILE__,__func__,__LINE__,info->pwdn.pin,info->pwdn.active_level);
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(10);
++	}
++	return 0;
++}
++
++static int imx335_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	struct imx335_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++	} else {
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, !info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++	}
++	return 0;
++}
++
++static int imx335_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct imx335_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = imx335_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++
++
++static int imx335_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++
++	ret = imx335_read(sd, IMX335_REG_CHIP_ID_HIGH, &v);
++	printk("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != IMX335_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = imx335_read(sd, IMX335_REG_CHIP_ID_LOW, &v);
++	printk("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != IMX335_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	printk(" imx335 id %x\n", *ident);
++	return 0;
++}
++
++
++static struct imx335_win_size imx335_win_sizes[] = {
++#if 1
++	{
++		.sensor_info.mipi_cfg.twidth		= 2616,
++		.sensor_info.mipi_cfg.theight		= 1944,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 648, //hcrop(2592-1944)
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 34,  //Margin for color processing
++		.sensor_info.fps			= 15 << 16 | 1,
++
++		.width		= 1944,
++		.height		= 1944,
++		.mbus_code	= MEDIA_BUS_FMT_SGBRG10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= imx335_init_regs_2592_1944_15fps_mipi,
++	},
++#endif
++	{
++		.sensor_info.mipi_cfg.twidth		= 2616,
++		.sensor_info.mipi_cfg.theight		= 1944,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 648,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 34,
++		.sensor_info.fps			= 25 << 16 | 1,
++
++		.width		= 1944,
++		.height		= 1944,
++		.mbus_code	= MEDIA_BUS_FMT_SGBRG10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= imx335_init_regs_2592_1944_25fps_mipi,
++	},
++
++};
++static const struct imx335_win_size *imx335_select_win(u32 *width, u32 *height)
++{
++	int i, default_size = ARRAY_SIZE(imx335_win_sizes) - 1;
++
++	for (i = 0; i < ARRAY_SIZE(imx335_win_sizes); i++) {
++		if ((*width >= imx335_win_sizes[i].width) &&
++				(*height >= imx335_win_sizes[i].height)) {
++			*width = imx335_win_sizes[i].width;
++			*height = imx335_win_sizes[i].height;
++			return &imx335_win_sizes[i];
++		}
++	}
++
++	*width = imx335_win_sizes[default_size].width;
++	*height = imx335_win_sizes[default_size].height;
++	printk("------w=%d,h=%d--default_size=%d---->line=%d,func=%s\n",*width,*height,default_size,__LINE__,__func__);
++	return &imx335_win_sizes[default_size];
++}
++
++static int imx335_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_imx335_FMTS)
++		return -EINVAL;
++
++	code->code = imx335_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int imx335_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct imx335_format_struct *ovfmt;
++	struct imx335_win_size *wsize;
++	struct imx335_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++//	info->win = imx335_select_win(&format->format.width, &format->format.height);
++
++
++	return 0;
++}
++
++static int imx335_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct imx335_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	*(unsigned int *)fmt->reserved = &info->win->sensor_info;
++
++	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int imx335_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int imx335_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int imx335_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int imx335_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int imx335_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int imx335_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++#if  0
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(imx335_again_lut); i++) {
++		lut = &imx335_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(imx335_again_lut); i++) {
++		lut = &imx335_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return -EINVAL;
++}
++#endif
++
++static int imx335_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++//	printk("~~~g_again=%d\n",*value);
++#if 1
++    return 0;
++#else
++    char v=0;
++    unsigned int reg_val=0;
++    int ret=0;
++    int i=0;
++    int total;
++    total = sizeof(gainLevelTable) / sizeof(unsigned int);
++
++    ret=imx335_read(sd,0x00b1,&v);
++    reg_val|=(v<<6);
++    ret+=imx335_read(sd,0x00b2,&v);
++    reg_val|=((v>>2)|0x3f);
++
++    for (i = 0; i < total; i++)
++    {
++        if ((gainLevelTable[i] <= reg_val)&&(reg_val < gainLevelTable[i+1]))
++	{
++		*value=reg_val;
++		break;
++	}
++    }
++    return ret;
++#endif
++}
++/*set analog gain db value, map value to sensor register.*/
++static int imx335_s_again(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++#if 0
++	ret = imx335_write(sd, 0x30e8, (unsigned char)(value & 0xff));
++	ret += imx335_write(sd, 0x30e9, (unsigned char)((value >> 8) & 0x07));
++	if (ret < 0)
++		return ret;
++#endif
++    return 0;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int imx335_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int imx335_s_exp(struct v4l2_subdev *sd, int value)
++{
++#if 1
++	int ret = 0;
++
++	unsigned short shr0 = 0;
++	unsigned short vmax = 0;
++
++	vmax = imx335_win_sizes[0].sensor_info.mipi_cfg.theight;
++	printk("====================>>>>>>>>>>>>>>>vmax=%d\n",vmax);
++	shr0 = vmax - value;
++	printk("====================>>>>>>>>>>>>>>>shr0=%d\n",shr0);
++	ret = imx335_write(sd, 0x3058, (unsigned char)(shr0 & 0xff));
++	ret += imx335_write(sd, 0x3059, (unsigned char)((shr0 >> 8) & 0xff));
++	ret += imx335_write(sd, 0x305a, (unsigned char)((shr0 >> 16) & 0x0f));
++	if (0 != ret) {
++		IS_ERR("err: imx335_write err\n");
++		return ret;
++	}
++#endif
++	return 0;
++}
++
++static int imx335_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct imx335_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return imx335_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return imx335_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int imx335_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct imx335_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return imx335_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return imx335_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return imx335_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return imx335_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* imx335_s_gain turns off auto gain */
++			return imx335_s_gain(sd, info->gain->val);
++		}
++		return imx335_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return imx335_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return imx335_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return imx335_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops imx335_ctrl_ops = {
++	.s_ctrl = imx335_s_ctrl,
++	.g_volatile_ctrl = imx335_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int imx335_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = imx335_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 2;
++	return ret;
++}
++
++static int imx335_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	imx335_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int imx335_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct imx335_info *info = to_state(sd);
++	int ret = 0;
++	int val=0;
++	printk("------------>line=%d,func=%s\n",__LINE__,__func__);
++	if (enable) {
++		imx335_reset(sd,1);
++		imx335_init(sd,1);
++		ret = imx335_write_array(sd, imx335_stream_on_mipi);
++		pr_debug("imx335 stream on\n");
++	printk("----on-------->line=%d,func=%s\n",__LINE__,__func__);
++
++	}
++	else {
++		ret = imx335_write_array(sd, imx335_stream_off_mipi);
++		pr_debug("imx335 stream off\n");
++	printk("----off-------->line=%d,func=%s\n",__LINE__,__func__);
++	}
++	return ret;
++}
++
++int imx335_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct imx335_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops imx335_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = imx335_g_register,
++	.s_register = imx335_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops imx335_video_ops = {
++	.s_stream = imx335_s_stream,
++	.g_frame_interval = imx335_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops imx335_pad_ops = {
++	//.enum_frame_interval = imx335_enum_frame_interval,
++	//.num_frame_size = imx335_enum_frame_size,
++	//.enum_mbus_code = imx335_enum_mbus_code,
++	.set_fmt = imx335_set_fmt,
++	.get_fmt = imx335_get_fmt,
++};
++
++static const struct v4l2_subdev_ops imx335_ops = {
++	.core = &imx335_core_ops,
++	.video = &imx335_video_ops,
++	.pad = &imx335_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int imx335_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_subdev *sd;
++	struct imx335_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++	unsigned long rate;
++
++	printk(" imx335 probe \n\n");
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,pwdn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->pwdn.pin = gpio;
++		info->pwdn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	v4l2_i2c_subdev_init(sd, client, &imx335_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++#if 1
++
++	info->clk = v4l2_clk_get(&client->dev, "div_cim");
++#if 1
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++	info->sclka = devm_clk_get(&client->dev, "mux_cim");
++
++	printk("sclka is %s\n", info->sclka?"NOT NULL":"NULL");
++	rate = v4l2_clk_get_rate(info->clk);
++	if (((rate / 1000) % 37125) != 0) {
++		ret = clk_set_parent(info->sclka, clk_get(NULL, "epll"));
++		info->sclka = devm_clk_get(&client->dev, "epll");
++		if (IS_ERR(info->sclka)) {
++			pr_err("get sclka failed\n");
++		} else {
++			rate = clk_get_rate(info->sclka);
++			if (((rate / 1000) % 37125) != 0) {
++				clk_set_rate(info->sclka, 891000000);
++			}
++		}
++	}
++#endif
++
++	ret = v4l2_clk_set_rate(info->clk, 37125000);
++
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++#endif
++
++	imx335_reset(sd, 1);
++
++	/* Make sure it's an imx335 */
++	ret = imx335_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an imx335 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++//	imx335_ircut(sd, 0);
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &imx335_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &imx335_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &imx335_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &imx335_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &imx335_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &imx335_ctrl_ops,
++		//	V4L2_CID_ANALOGUE_GAIN, 0, 259142, 1, 10000);
++			V4L2_CID_ANALOGUE_GAIN, 0, 405939, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &imx335_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1899 - 4, 1, 1500);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->win = &imx335_win_sizes[0];//720p
++//	info->win = &imx335_win_sizes[1];//1080*360
++//	info->win = &imx335_win_sizes[2];//720*360
++	imx335_init(sd, 1);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "imx335 Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int imx335_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct imx335_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id imx335_id[] = {
++	{ "imx335", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, imx335_id);
++
++static const struct of_device_id imx335_of_match[] = {
++	{.compatible = "sony,imx335", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, imx335_of_match);
++
++
++static struct i2c_driver imx335_driver = {
++	.driver = {
++		.name	= "imx335",
++		.of_match_table = of_match_ptr(imx335_of_match),
++	},
++	.probe		= imx335_probe,
++	.remove		= imx335_remove,
++	.id_table	= imx335_id,
++};
++
++module_i2c_driver(imx335_driver);
++MODULE_DESCRIPTION("A low-level driver for Sony imx335 sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/ov2735a.c b/module_drivers/drivers/media/i2c/ingenic-isp/ov2735a.c
+new file mode 100644
+index 000000000..62ffa338a
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/ov2735a.c
+@@ -0,0 +1,1157 @@
++/*
++ * A V4L2 driver for OmniVision OV2735A cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++
++#include <isp-sensor.h>
++
++#define OV2735A_CHIP_ID_H	(0x27)
++#define OV2735A_CHIP_ID_L	(0x35)
++#define OV2735A_REG_END		0xff
++#define OV2735A_REG_DELAY	0x00
++#define OV2735A_PAGE_REG	    0xfd
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct ov2735a_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct ov2735a_gpio {
++	int pin;
++	int active_level;
++};
++
++struct ov2735a_supply{
++	struct regulator *avdd;
++	struct regulator *dvdd;
++	struct regulator *dovdd;
++};
++
++struct ov2735a_info {
++	struct ov2735a_supply supply;
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct ov2735a_win_size *win;
++
++	struct ov2735a_gpio reset;
++	struct ov2735a_gpio ircutp;
++	struct ov2735a_gpio ircutn;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++
++struct again_lut ov2735a_again_lut[] = {
++	{0x10,	0},
++	{0x11,	5731},
++	{0x12,	11136},
++	{0x13,	16248},
++	{0x14,	21097},
++	{0x15,	25710},
++	{0x16,	30109},
++	{0x17,	34312},
++	{0x18,	38336},
++	{0x19,	42195},
++	{0x1a,	45904},
++	{0x1b,	49472},
++	{0x1c,	52910},
++	{0x1d,	56228},
++	{0x1e,	59433},
++	{0x1f,	62534},
++	{0x20,	65536},
++	{0x22,	71267},
++	{0x24,	76672},
++	{0x26,	81784},
++	{0x28,	86633},
++	{0x2a,	91246},
++	{0x2c,	95645},
++	{0x2e,	99848},
++	{0x30,	103872},
++	{0x32,	107731},
++	{0x34,	111440},
++	{0x36,	115008},
++	{0x38,	118446},
++	{0x3a,	121764},
++	{0x3c,	124969},
++	{0x3e,	128070},
++	{0x40,	131072},
++	{0x44,	136803},
++	{0x48,	142208},
++	{0x4c,	147320},
++	{0x50,	152169},
++	{0x54,	156782},
++	{0x58,	161181},
++	{0x5c,	165384},
++	{0x60,	169408},
++	{0x64,	173267},
++	{0x68,	176976},
++	{0x6c,	180544},
++	{0x70,	183982},
++	{0x74,	187300},
++	{0x78,	190505},
++	{0x7c,	193606},
++	{0x80,	196608},
++	{0x88,	202339},
++	{0x90,	207744},
++	{0x98,	212856},
++	{0xa0,	217705},
++	{0xa8,	222318},
++	{0xb0,	226717},
++	{0xb8,	230920},
++	{0xc0,	234944},
++	{0xc8,	238803},
++	{0xd0,	242512},
++	{0xd8,	246080},
++	{0xe0,	249518},
++	{0xe8,	252836},
++	{0xf0,	256041},
++	{0xf8,	259142},
++};
++
++static inline struct ov2735a_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct ov2735a_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct ov2735a_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++static struct regval_list ov2735a_init_regs_1920_1080_30fps_MIPI[] = {
++	{0xfd, 0x00},
++	{OV2735A_REG_DELAY, 0x05},
++	{0xfd, 0x00},
++	{0x2f, 0x10},
++	{0x34, 0x00},
++	{0x30, 0x15},
++	{0x33, 0x01},
++	{0x35, 0x20},
++	{0xfd, 0x01},
++	{0x0d, 0x00},
++	{0x30, 0x00},
++	{0x03, 0x01},
++	{0x04, 0x8f},
++	{0x01, 0x01},
++	{0x09, 0x00},
++	{0x0a, 0x20},
++	{0x06, 0x0a},
++	{0x24, 0x10},
++	{0x01, 0x01},
++	{0xfb, 0x73},
++	{0x01, 0x01},
++	{0xfd, 0x01},
++	{0x1a, 0x6b},
++	{0x1c, 0xea},
++	{0x16, 0x0c},
++	{0x21, 0x00},
++	{0x11, 0xe8},//;63	;fr
++	{0x19, 0xc3},
++	{0x26, 0xda},
++	{0x29, 0x01},
++	{0x33, 0x6f},
++	{0x2a, 0xd2},
++	{0x2c, 0x40},
++	{0xd0, 0x02},
++	{0xd1, 0x01},
++	{0xd2, 0x20},
++	{0xd3, 0x03},//;04	;
++	{0xd4, 0xa4},//;2a	;
++	{0x50, 0x00},
++	{0x51, 0x2c},
++	{0x52, 0x29},
++	{0x53, 0x00},
++	{0x55, 0x44},
++	{0x58, 0x29},
++	{0x5a, 0x00},
++	{0x5b, 0x00},
++	{0x5d, 0x00},
++	{0x64, 0x2f},
++	{0x66, 0x62},
++	{0x68, 0x5b},
++	{0x75, 0x46},
++	{0x76, 0xf0},
++	{0x77, 0x4f},
++	{0x78, 0xef},
++	{0x72, 0xcf},
++	{0x73, 0x36},
++	{0x7d, 0x0d},
++	{0x7e, 0x0d},
++	{0x8a, 0x77},
++	{0x8b, 0x77},
++	{0xfd, 0x01},
++	{0xb1, 0x83},//;DPHY enable 8b
++
++//	{0xb2, 0x40},//hs mode
++
++	{0xb3, 0x0b},//;0b;09;1d
++	{0xb4, 0x14},//;MIPI PLL enable;14;35;36
++	{0x9d, 0x40},//;mipi hs dc level 40/03/55
++	{0xa1, 0x05},//;speed/03
++	{0x94, 0x44},//;dphy time
++	{0x95, 0x33},//;dphy time
++	{0x96, 0x1f},//;dphy time
++	{0x98, 0x45},//;dphy time
++	{0x9c, 0x10},//;dphy time
++	{0xb5, 0x70},//;30
++	{0xa0, 0x01},//;mipi enable
++	{0x25, 0xe0},
++	{0x20, 0x7b},
++	{0x8f, 0x88},
++	{0x91, 0x40},
++
++	{0xfd, 0x02},
++	{0x5e, 0x03},
++	{0xa1, 0x04},
++	{0xa3, 0x40},
++	{0xa5, 0x02},
++	{0xa7, 0xc4},
++	{0xfd, 0x01},
++	{0x86, 0x77},
++	{0x89, 0x77},
++	{0x87, 0x74},
++	{0x88, 0x74},
++	{0xfc, 0xe0},
++	{0xfe, 0xe0},
++	{0xf0, 0x40},
++	{0xf1, 0x40},
++	{0xf2, 0x40},
++	{0xf3, 0x40},
++
++#if 1
++	{0xfd, 0x02},//;;crop to 1920x1080
++	{0xa0, 0x00},//;Image vertical start MSB3bits
++	{0xa1, 0x08},//;Image vertical start LSB8bits
++	{0xa2, 0x04},//;image vertical size  MSB8bits
++	{0xa3, 0x38},//;image vertical size  LSB8bits
++	{0xa4, 0x00},
++	{0xa5, 0x04},//;H start 8Lsb, keep center
++	{0xa6, 0x03},
++	{0xa7, 0xc0},//;Half H size Lsb8bits
++	{0xfd, 0x01},
++	{0x8e, 0x07},
++	{0x8f, 0x80},//;MIPI column number
++	{0x90, 0x04},//;MIPI row number
++	{0x91, 0x38},
++
++	{0xfd, 0x03},
++	{0xc0, 0x01},//;enable transfer OTP BP information
++	{0xfd, 0x04},
++	{0x21, 0x14},
++	{0x22, 0x14},
++	{0x23, 0x14},//;enhance normal and dummy BPC
++
++	{0xfd, 0x01},
++	{0x06, 0xe0},//;insert dummy line , the frame rate is 30.01.
++//	{0x01, 0x01},//;
++//	{0xa0, 0x01},//;MIPI enable, stream on
++#else
++	{0xfd, 0x02},//;;crop to 1920x1080
++	{0xa0, 0x00},//;Image vertical start MSB3bits
++	{0xa1, 0x08},//;Image vertical start LSB8bits
++	{0xa2, 0x01},//;image vertical size  MSB8bits
++	{0xa3, 0xe0},//;image vertical size  LSB8bits
++	{0xa4, 0x00},
++	{0xa5, 0x04},//;H start 8Lsb, keep center
++	{0xa6, 0x01},
++	{0xa7, 0x40},//;Half H size Lsb8bits
++	{0xfd, 0x01},
++	{0x8e, 0x02},
++	{0x8f, 0x80},//;MIPI column number
++	{0x90, 0x01},//;MIPI row number
++	{0x91, 0xe0},
++
++	{0xfd, 0x03},
++	{0xc0, 0x01},//;enable transfer OTP BP information
++	{0xfd, 0x04},
++	{0x21, 0x14},
++	{0x22, 0x14},
++	{0x23, 0x14},//;enhance normal and dummy BPC
++
++	{0xfd, 0x01},
++	{0x06, 0xe0},//;insert dummy line , the frame rate is 30.01.
++	{0x01, 0x01},//;
++	{0xa0, 0x01},//;MIPI enable, stream on
++#endif
++
++#if 0
++	{0xfd, 0x01},//@@ 1 11 Mirror_On_Flip_Off
++
++	{0x3f, 0x01},//03
++	{0xf8, 0x00},//02
++	{0x01, 0x01},
++	{0xfd, 0x02},
++	{0x62, 0x01},//;full size mode flip off row start for OTP BPC
++	{0x63, 0x00},
++	{0xfd, 0x01},
++
++#endif
++#if 0
++	{0xfd, 0x01},//@@ 1 12 Mirror_On_Flip_On
++
++	{0x3f, 0x03},// 03
++
++	{0xf8, 0x02},//02
++
++	{0x01, 0x01},
++	{0xfd, 0x02},
++	{0x62, 0x48},
++	{0x63, 0x04},//;full size flip, row start:1096(0x448)
++	{0xfd, 0x01},
++#endif
++
++#if 0
++	{0xfd, 0x01},//@@ 1 13 Mirror_Off_Flip_Off
++
++	{0x3f, 0x00},//03
++	{0xf8, 0x00},// 02
++
++	{0x01, 0x01},
++	{0xfd, 0x02},
++	{0x62, 0x01},//;full size mode flip off row start for OTP BPC
++	{0x63, 0x00},
++	{0xfd, 0x01},
++#endif
++
++#if 1
++	{0xfd, 0x01},//@@ 1 14 Mirror_Off_Flip_On
++
++	{0x3f, 0x02},//03
++	{0xf8, 0x02},//02
++	{0x01, 0x01},
++
++	{0xfd, 0x02},
++	{0x62, 0x48},
++	{0x63, 0x04},//;full size flip, row start:1096(0x448)
++	{0xfd, 0x01},
++#endif
++
++	{0x01, 0x01},//;
++	{0xa0, 0x01},//;MIPI enable, stream on
++	{0xfd, 0x00},
++	{0x36, 0x01},
++	{0x37, 0x01},//fake stream off
++
++	{OV2735A_REG_END, 0x00},	/* END MARKER */
++};
++
++
++static struct regval_list ov2735a_stream_on[] = {
++	{0xfd, 0x00},
++	{0x36, 0x00},
++	{0x37, 0x00},//fake stream on
++	{OV2735A_REG_END, 0x00},
++};
++
++static struct regval_list ov2735a_stream_off[] = {
++	{0xfd, 0x00},
++	{0x36, 0x01},
++	{0x37, 0x01},//fake stream off
++	{OV2735A_REG_END, 0x00},
++};
++
++
++int ov2735a_read(struct v4l2_subdev *sd, unsigned char reg,
++		unsigned char *value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 1,
++			.buf	= &reg,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ov2735a_write(struct v4l2_subdev *sd, unsigned char reg,
++			unsigned char value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	unsigned char buf[2] = {reg, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 2,
++		.buf	= buf,
++	};
++	int ret;
++	unsigned int timeout  = 100;
++	while(timeout--){
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == -EAGAIN){
++			msleep(100);
++			continue;
++		}
++		else
++			break;
++	}
++
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ov2735a_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != OV2735A_REG_END) {
++		if (vals->reg_num == OV2735A_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = ov2735a_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++			if (vals->reg_num == OV2735A_PAGE_REG){
++				val &= 0xf8;
++				val |= (vals->value & 0x07);
++				ret = ov2735a_write(sd, vals->reg_num, val);
++				ret = ov2735a_read(sd, vals->reg_num, &val);
++			}
++		}
++		vals++;
++	}
++	return 0;
++}
++static int ov2735a_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != OV2735A_REG_END) {
++		if (vals->reg_num == OV2735A_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = ov2735a_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int ov2735a_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov2735a_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(10);
++	}
++	return 0;
++}
++
++static int ov2735a_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov2735a_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++	} else {
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, !info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++	}
++	return 0;
++}
++
++static int ov2735a_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov2735a_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = ov2735a_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++
++static int ov2735a_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++
++	ret = ov2735a_read(sd, 0x02, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != OV2735A_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = ov2735a_read(sd, 0x03, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != OV2735A_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	ret = ov2735a_read(sd, 0x04, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != 0x05 && v != 0x06 && v != 0x07)
++		return -ENODEV;
++
++
++	return 0;
++}
++
++
++static struct ov2735a_win_size ov2735a_win_sizes[] = {
++	/* 1920*1080 */
++	{
++		.sensor_info.mipi_cfg.twidth		= 1920,
++		.sensor_info.mipi_cfg.theight		= 1080,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.fps			= 30 << 16 | 1,
++		.sensor_info.total_width			= 1936,
++		.sensor_info.total_height			= 1304,
++
++		.width		= 1920,
++		.height		= 1080,
++		.mbus_code	= MEDIA_BUS_FMT_SGRBG10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov2735a_init_regs_1920_1080_30fps_MIPI,
++	}
++};
++
++#if 0
++static int ov2735a_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad || code->index >= N_OV2735A_FMTS)
++		return -EINVAL;
++
++	code->code = ov2735a_formats[code->index].mbus_code;
++	return 0;
++}
++#endif
++
++/*
++ * Set a format.
++ */
++static int ov2735a_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++	return ret;
++}
++
++static int ov2735a_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct ov2735a_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	*(unsigned int *)fmt->reserved = (unsigned int)&info->win->sensor_info;
++
++
++//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int ov2735a_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov2735a_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov2735a_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov2735a_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int ov2735a_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int ov2735a_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov2735a_again_lut); i++) {
++		lut = &ov2735a_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov2735a_again_lut); i++) {
++		lut = &ov2735a_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return -EINVAL;
++}
++
++static int ov2735a_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	char v = 0;
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++
++	ret = ov2735a_read(sd, 0x23, &v);
++	reg_val |= v ;
++
++	*value = regval_to_again(reg_val);
++
++	return ret;
++
++}
++/*set analog gain db value, map value to sensor register.*/
++static int ov2735a_s_again(struct v4l2_subdev *sd, int value)
++{
++	struct ov2735a_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int ret = 0;
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(value);
++	}
++
++	ret = ov2735a_write(sd, 0xfd, 0x01);
++	ret += ov2735a_write(sd, 0x24, (unsigned char)reg_value);
++	ret += ov2735a_write(sd, 0x01, 0x01);
++	if (ret < 0){
++		printk("ov2735a_write error  %d\n" ,__LINE__ );
++		return ret;
++	}
++	return 0;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int ov2735a_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov2735a_s_exp(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	ret = ov2735a_write(sd, 0xfd, 0x01);
++	ret += ov2735a_write(sd, 0x4, (unsigned char)(value & 0xff));
++	ret += ov2735a_write(sd, 0x3, (unsigned char)((value & 0xff00) >> 8));
++	ret += ov2735a_write(sd, 0x01, 0x01);
++
++	if (ret < 0) {
++		printk("ov2735a_write error  %d\n" ,__LINE__);
++		return ret;
++	}
++	return ret;
++}
++
++static int ov2735a_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov2735a_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return ov2735a_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov2735a_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int ov2735a_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov2735a_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return ov2735a_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return ov2735a_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return ov2735a_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return ov2735a_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* ov2735a_s_gain turns off auto gain */
++			return ov2735a_s_gain(sd, info->gain->val);
++		}
++		return ov2735a_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return ov2735a_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov2735a_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return ov2735a_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops ov2735a_ctrl_ops = {
++	.s_ctrl = ov2735a_s_ctrl,
++	.g_volatile_ctrl = ov2735a_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ov2735a_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = ov2735a_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int ov2735a_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	ov2735a_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++static int ov2735a_power(struct v4l2_subdev *sd, int on)
++{
++	struct ov2735a_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	int ret;
++
++	info->supply.avdd  = devm_regulator_get_optional(&client->dev, "avdd");
++	info->supply.dvdd  = devm_regulator_get_optional(&client->dev, "dvdd");
++	info->supply.dovdd = devm_regulator_get_optional(&client->dev, "dovdd");
++
++	if (IS_ERR(info->supply.avdd)||IS_ERR(info->supply.dvdd)
++		||IS_ERR(info->supply.dovdd)) {
++			if ((PTR_ERR(info->supply.avdd) == -EPROBE_DEFER)
++				||(PTR_ERR(info->supply.dvdd) == -EPROBE_DEFER)
++					||(PTR_ERR(info->supply.dovdd) == -EPROBE_DEFER))
++				return -EPROBE_DEFER;
++			printk("No ov2735a vdd regulator found\n");
++	}
++
++	if ((!IS_ERR(info->supply.avdd))&&(!IS_ERR(info->supply.avdd))
++			&&(!IS_ERR(info->supply.avdd)))  {
++		if(on){
++			ret = regulator_enable(info->supply.avdd);
++			ret = regulator_enable(info->supply.dvdd);
++			ret = regulator_enable(info->supply.dovdd);
++			if (ret)
++			   dev_err(&client->dev, "ov2735a vdd supply disable failed\n");
++		}
++		else{
++			ret = regulator_disable(info->supply.avdd);
++			ret = regulator_disable(info->supply.dvdd);
++			ret = regulator_disable(info->supply.dovdd);
++			if (ret)
++			    dev_err(&client->dev, "ov2735a vdd supply disable failed\n");
++		}
++	}else{
++		dev_err(&client->dev, "ov2735a vdd supply IS_ERR failed\n");
++	}
++	return ret;
++}
++
++int ov2735a_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct ov2735a_info *info = to_state(sd);
++	int ret = 0;
++
++	if (enable) {
++		ov2735a_reset(sd, 1);
++		ov2735a_write_array(sd, info->win->regs);
++		ret = ov2735a_write_array(sd, ov2735a_stream_on);
++		printk("ov2735a stream on\n");
++
++	}
++	else {
++		ret = ov2735a_write_array(sd, ov2735a_stream_off);
++		printk("ov2735a stream off\n");
++	}
++	return ret;
++}
++
++
++int ov2735a_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct ov2735a_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops ov2735a_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = ov2735a_g_register,
++	.s_register = ov2735a_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops ov2735a_video_ops = {
++	.s_stream = ov2735a_s_stream,
++	.g_frame_interval = ov2735a_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops ov2735a_pad_ops = {
++	//.enum_frame_interval = ov2735a_enum_frame_interval,
++	//.num_frame_size = ov2735a_enum_frame_size,
++	//.enum_mbus_code = ov2735a_enum_mbus_code,
++	.set_fmt = ov2735a_set_fmt,
++	.get_fmt = ov2735a_get_fmt,
++};
++
++static const struct v4l2_subdev_ops ov2735a_ops = {
++	.core = &ov2735a_core_ops,
++	.video = &ov2735a_video_ops,
++	.pad = &ov2735a_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int ov2735a_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_subdev *sd;
++	struct ov2735a_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutp-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutp.pin = gpio;
++		info->ircutp.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutn.pin = gpio;
++		info->ircutn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	v4l2_i2c_subdev_init(sd, client, &ov2735a_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	ov2735a_power(sd,1);
++
++	/*clk*/
++	info->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++
++	info->win = &ov2735a_win_sizes[0];
++	ov2735a_reset(sd, 1);
++#if 1
++	/* Make sure it's an ov2735a */
++	ret = ov2735a_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an ov2735a chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++	/*IRCUT ctl 0:off 1:on*/
++	ov2735a_ircut(sd, 0);
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &ov2735a_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &ov2735a_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &ov2735a_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &ov2735a_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &ov2735a_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &ov2735a_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 259142, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov2735a_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1899 - 4, 1, 1500);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "ov2735a Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int ov2735a_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov2735a_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id ov2735a_id[] = {
++	{ "ov2735a", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ov2735a_id);
++
++static const struct of_device_id ov2735a_of_match[] = {
++	{.compatible = "ovti,ov2735a", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov2735a_of_match);
++
++
++static int ov2735a_suspend(struct device *dev)
++{
++        struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++        struct v4l2_subdev *sd = i2c_get_clientdata(client);
++        struct ov2735a_info *info = to_state(sd);
++	int ret=0;
++
++	ov2735a_power(sd,0);
++	v4l2_clk_disable(info->clk);
++        return ret;
++}
++
++static int ov2735a_resume(struct device *dev)
++{
++	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov2735a_info *info = to_state(sd);
++	int ret=0;
++
++	ov2735a_power(sd,1);
++	v4l2_clk_enable(info->clk);
++	ov2735a_reset(sd, 1);
++	ov2735a_init(sd, 1);
++	return ret;
++}
++
++const struct dev_pm_ops ov2735a_pm =
++{
++        .suspend = ov2735a_suspend,
++        .resume  = ov2735a_resume,
++};
++
++
++static struct i2c_driver ov2735a_driver = {
++	.driver = {
++		.name	= "ov2735a",
++		.of_match_table = of_match_ptr(ov2735a_of_match),
++		.pm	=  &ov2735a_pm,
++	},
++	.probe		= ov2735a_probe,
++	.remove		= ov2735a_remove,
++	.id_table	= ov2735a_id,
++};
++
++module_i2c_driver(ov2735a_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for OmniVision ov2735a sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/ov2735b.c b/module_drivers/drivers/media/i2c/ingenic-isp/ov2735b.c
+new file mode 100644
+index 000000000..e47728a18
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/ov2735b.c
+@@ -0,0 +1,1202 @@
++/*
++ * A V4L2 driver for OmniVision OV2735B cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++
++#include <isp-sensor.h>
++
++#define OV2735B_CHIP_ID_H	(0x27)
++#define OV2735B_CHIP_ID_L	(0x35)
++#define OV2735B_REG_END		0xff
++#define OV2735B_REG_DELAY	0x00
++#define OV2735B_PAGE_REG	    0xfd
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct ov2735b_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct ov2735b_gpio {
++	int pin;
++	int active_level;
++};
++
++struct ov2735b_supply{
++	struct regulator *avdd;
++	struct regulator *dvdd;
++	struct regulator *dovdd;
++};
++
++struct ov2735b_info {
++	struct ov2735b_supply supply;
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct ov2735b_win_size *win;
++
++	struct ov2735b_gpio reset;
++	struct ov2735b_gpio ircutp;
++	struct ov2735b_gpio ircutn;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++
++struct again_lut ov2735b_again_lut[] = {
++	{0x10,	0},
++	{0x11,	5731},
++	{0x12,	11136},
++	{0x13,	16248},
++	{0x14,	21097},
++	{0x15,	25710},
++	{0x16,	30109},
++	{0x17,	34312},
++	{0x18,	38336},
++	{0x19,	42195},
++	{0x1a,	45904},
++	{0x1b,	49472},
++	{0x1c,	52910},
++	{0x1d,	56228},
++	{0x1e,	59433},
++	{0x1f,	62534},
++	{0x20,	65536},
++	{0x22,	71267},
++	{0x24,	76672},
++	{0x26,	81784},
++	{0x28,	86633},
++	{0x2a,	91246},
++	{0x2c,	95645},
++	{0x2e,	99848},
++	{0x30,	103872},
++	{0x32,	107731},
++	{0x34,	111440},
++	{0x36,	115008},
++	{0x38,	118446},
++	{0x3a,	121764},
++	{0x3c,	124969},
++	{0x3e,	128070},
++	{0x40,	131072},
++	{0x44,	136803},
++	{0x48,	142208},
++	{0x4c,	147320},
++	{0x50,	152169},
++	{0x54,	156782},
++	{0x58,	161181},
++	{0x5c,	165384},
++	{0x60,	169408},
++	{0x64,	173267},
++	{0x68,	176976},
++	{0x6c,	180544},
++	{0x70,	183982},
++	{0x74,	187300},
++	{0x78,	190505},
++	{0x7c,	193606},
++	{0x80,	196608},
++	{0x88,	202339},
++	{0x90,	207744},
++	{0x98,	212856},
++	{0xa0,	217705},
++	{0xa8,	222318},
++	{0xb0,	226717},
++	{0xb8,	230920},
++	{0xc0,	234944},
++	{0xc8,	238803},
++	{0xd0,	242512},
++	{0xd8,	246080},
++	{0xe0,	249518},
++	{0xe8,	252836},
++	{0xf0,	256041},
++	{0xf8,	259142},
++};
++
++static inline struct ov2735b_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct ov2735b_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct ov2735b_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++static struct regval_list ov2735b_init_regs_1920_1080_30fps_dvp[] = {
++	{0xfd, 0x00},
++	{OV2735B_REG_DELAY, 0x05},
++	{0xfd, 0x00},
++	{0x2f, 0x10},
++	{0x34, 0x00},
++	{0x30, 0x15},
++	{0x33, 0x01},
++	{0x35, 0x20},
++	{0x1d, 0xa5},
++	{0xfd, 0x01},
++	{0x0d, 0x00},
++	{0x30, 0x00},
++	{0x03, 0x01},
++	{0x04, 0x8f},
++	{0x01, 0x01},
++	{0x09, 0x00},
++	{0x0a, 0x20},
++	{0x06, 0x0a},
++	{0x24, 0x10},
++	{0x01, 0x01},
++	{0xfb, 0x73},
++	{0x01, 0x01},
++	{0xfd, 0x01},
++	{0x1a, 0x6b},
++	{0x1c, 0xea},
++	{0x16, 0x0c},
++	{0x21, 0x00},
++	{0x11, 0x63},
++	{0x19, 0xc3},
++	{0x26, 0xda},
++	{0x29, 0x01},
++	{0x33, 0x6f},
++	{0x2a, 0xd2},
++	{0x2c, 0x40},
++	{0xd0, 0x02},
++	{0xd1, 0x01},
++	{0xd2, 0x20},
++	{0xd3, 0x04},
++	{0xd4, 0x2a},
++	{0x50, 0x00},
++	{0x51, 0x2c},
++	{0x52, 0x29},
++	{0x53, 0x00},
++	{0x55, 0x44},
++	{0x58, 0x29},
++	{0x5a, 0x00},
++	{0x5b, 0x00},
++	{0x5d, 0x00},
++	{0x64, 0x2f},
++	{0x66, 0x62},
++	{0x68, 0x5b},
++	{0x75, 0x46},
++	{0x76, 0xf0},
++	{0x77, 0x4f},
++	{0x78, 0xef},
++	{0x72, 0xcf},
++	{0x73, 0x36},
++	{0x7d, 0x0d},
++	{0x7e, 0x0d},
++	{0x8a, 0x77},
++	{0x8b, 0x77},
++	{0xfd, 0x01},
++	{0xb1, 0x82},
++	{0xb3, 0x0b},
++	{0xb4, 0x14},
++	{0x9d, 0x40},
++	{0xa1, 0x05},
++	{0x94, 0x44},
++	{0x95, 0x33},
++	{0x96, 0x1f},
++	{0x98, 0x45},
++	{0x9c, 0x10},
++	{0xb5, 0x70},
++	{0xa0, 0x00},
++	{0x25, 0xe0},
++	{0x20, 0x7b},
++	{0x8f, 0x88},
++	{0x91, 0x40},
++	{0xfd, 0x01},
++	{0xfd, 0x02},
++	{0x5e, 0x03},
++	{0xfd, 0x02},
++	{0x60, 0xf0},
++	{0xa1, 0x04},
++	{0xa3, 0x40},
++	{0xa5, 0x02},
++	{0xa7, 0xc4},
++	{0xfd, 0x01},
++	{0x86, 0x77},
++	{0x89, 0x77},
++	{0x87, 0x74},
++	{0x88, 0x74},
++	{0xfc, 0xe0},
++	{0xfe, 0xe0},
++	{0xf0, 0x40},
++	{0xf1, 0x40},
++	{0xf2, 0x40},
++	{0xf3, 0x40},
++	{0xfd, 0x02},
++	{0x36, 0x08},
++	{0xa0, 0x00},
++	{0xa1, 0x08},
++	{0xa2, 0x04},
++	{0xa3, 0x38},
++	{0xa4, 0x00},
++	{0xa5, 0x04},
++	{0xa6, 0x03},
++	{0xa7, 0xc0},
++	{0xfd, 0x03},
++	{0xc0, 0x01},//OTP transf
++	{0xfd, 0x04},
++	{0x22, 0x14},
++	{0x23, 0x14},
++	{0xfd, 0x01},
++	{0x06, 0xe0},
++	{0x01, 0x01},
++	{0xfd, 0x00},
++	{0x1b, 0x00},
++	{0xfd, 0x01},
++	{0x0d, 0x10},
++	{0x0e, 0x05},
++	{0x0f, 0x2b},
++	{0x01, 0x01},
++	{0xfd, 0x00},
++	{0x36, 0x01},
++	{0x37, 0x01},//fake stream off
++
++	{OV2735B_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list ov2735b_init_regs_1920_1080_15fps_dvp[] = {
++	{0xfd, 0x00},
++	{OV2735B_REG_DELAY, 0x05},
++	{0xfd, 0x00},
++	{0x2f, 0x08},
++	{0x34, 0x00},
++	{0x30, 0x15},
++	{0x33, 0x01},
++	{0x35, 0x20},
++	{0x1d, 0xa5},
++	{0xfd, 0x01},
++	{0x0d, 0x00},
++	{0x30, 0x00},
++	{0x03, 0x01},
++	{0x04, 0x8f},
++	{0x01, 0x01},
++	{0x09, 0x00},
++	{0x0a, 0x20},
++	{0x06, 0x0a},
++	{0x24, 0x10},
++	{0x01, 0x01},
++	{0xfb, 0x73},
++	{0x01, 0x01},
++	{0xfd, 0x01},
++	{0x1a, 0x6b},
++	{0x1c, 0xea},
++	{0x16, 0x0c},
++	{0x21, 0x00},
++	{0x11, 0x63},
++	{0x19, 0xc3},
++	{0x26, 0xda},
++	{0x29, 0x01},
++	{0x33, 0x6f},
++	{0x2a, 0xd2},
++	{0x2c, 0x40},
++	{0xd0, 0x02},
++	{0xd1, 0x01},
++	{0xd2, 0x20},
++	{0xd3, 0x04},
++	{0xd4, 0x2a},
++	{0x50, 0x00},
++	{0x51, 0x2c},
++	{0x52, 0x29},
++	{0x53, 0x00},
++	{0x55, 0x44},
++	{0x58, 0x29},
++	{0x5a, 0x00},
++	{0x5b, 0x00},
++	{0x5d, 0x00},
++	{0x64, 0x2f},
++	{0x66, 0x62},
++	{0x68, 0x5b},
++	{0x75, 0x46},
++	{0x76, 0xf0},
++	{0x77, 0x4f},
++	{0x78, 0xef},
++	{0x72, 0xcf},
++	{0x73, 0x36},
++	{0x7d, 0x0d},
++	{0x7e, 0x0d},
++	{0x8a, 0x77},
++	{0x8b, 0x77},
++	{0xfd, 0x01},
++	{0xb1, 0x82},
++	{0xb3, 0x0b},
++	{0xb4, 0x14},
++	{0x9d, 0x40},
++	{0xa1, 0x05},
++	{0x94, 0x44},
++	{0x95, 0x33},
++	{0x96, 0x1f},
++	{0x98, 0x45},
++	{0x9c, 0x10},
++	{0xb5, 0x70},
++	{0xa0, 0x00},
++	{0x25, 0xe0},
++	{0x20, 0x7b},
++	{0x8f, 0x88},
++	{0x91, 0x40},
++	{0xfd, 0x01},
++	{0xfd, 0x02},
++	{0x5e, 0x03},
++	{0xfd, 0x02},
++	{0x60, 0xf0},
++	{0xa1, 0x04},
++	{0xa3, 0x40},
++	{0xa5, 0x02},
++	{0xa7, 0xc4},
++	{0xfd, 0x01},
++	{0x86, 0x77},
++	{0x89, 0x77},
++	{0x87, 0x74},
++	{0x88, 0x74},
++	{0xfc, 0xe0},
++	{0xfe, 0xe0},
++	{0xf0, 0x40},
++	{0xf1, 0x40},
++	{0xf2, 0x40},
++	{0xf3, 0x40},
++	{0xfd, 0x02},
++	{0x36, 0x08},
++	{0xa0, 0x00},
++	{0xa1, 0x08},
++	{0xa2, 0x04},
++	{0xa3, 0x38},
++	{0xa4, 0x00},
++	{0xa5, 0x04},
++	{0xa6, 0x03},
++	{0xa7, 0xc0},
++	{0xfd, 0x03},
++	{0xc0, 0x01},//OTP transf
++	{0xfd, 0x04},
++	{0x22, 0x14},
++	{0x23, 0x14},
++	{0xfd, 0x01},
++	{0x06, 0xe0},
++	{0x01, 0x01},
++	{0xfd, 0x00},
++	{0x1b, 0x00},
++	{0xfd, 0x01},
++	{0x0d, 0x10},
++	{0x0e, 0x07},
++	{0x0f, 0x6b},
++	{0x01, 0x01},
++	{0xfd, 0x00},
++	{0x36, 0x01},
++	{0x37, 0x01},//fake stream off
++
++	{OV2735B_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list ov2735b_stream_on[] = {
++	{0xfd, 0x00},
++	{0x36, 0x00},
++	{0x37, 0x00},//fake stream on
++
++	{OV2735B_REG_END, 0x00},
++};
++
++static struct regval_list ov2735b_stream_off[] = {
++	{0xfd, 0x00},
++	{0x36, 0x01},
++	{0x37, 0x01},//fake stream off
++
++	{OV2735B_REG_END, 0x00},
++};
++
++
++int ov2735b_read(struct v4l2_subdev *sd, unsigned char reg,
++		unsigned char *value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 1,
++			.buf	= &reg,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ov2735b_write(struct v4l2_subdev *sd, unsigned char reg,
++			unsigned char value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	unsigned char buf[2] = {reg, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 2,
++		.buf	= buf,
++	};
++	int ret;
++	unsigned int timeout  = 100;
++	while(timeout--){
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == -EAGAIN){
++			msleep(100);
++			continue;
++		}
++		else
++			break;
++	}
++
++	if (ret > 0)
++		ret = 0;
++	return ret;
++}
++
++static int ov2735b_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != OV2735B_REG_END) {
++		if (vals->reg_num == OV2735B_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = ov2735b_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++			if (vals->reg_num == OV2735B_PAGE_REG){
++				val &= 0xf8;
++				val |= (vals->value & 0x07);
++				ret = ov2735b_write(sd, vals->reg_num, val);
++				ret = ov2735b_read(sd, vals->reg_num, &val);
++			}
++		}
++		vals++;
++	}
++	return 0;
++}
++static int ov2735b_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != OV2735B_REG_END) {
++		if (vals->reg_num == OV2735B_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = ov2735b_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int ov2735b_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov2735b_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(10);
++	}
++	return 0;
++}
++
++static int ov2735b_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov2735b_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++	} else {
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, !info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++	}
++	return 0;
++}
++
++static int ov2735b_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov2735b_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = ov2735b_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++
++static int ov2735b_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++
++	ret = ov2735b_read(sd, 0x02, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != OV2735B_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = ov2735b_read(sd, 0x03, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != OV2735B_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	ret = ov2735b_read(sd, 0x04, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != 0x05 && v != 0x06 && v != 0x07)
++		return -ENODEV;
++
++
++	return 0;
++}
++
++
++static struct ov2735b_win_size ov2735b_win_sizes[] = {
++	/* 1920*1080 */
++	{
++
++		.sensor_info.fps			= 30 << 16 | 1,
++
++		.width		= 1920,
++		.height		= 1080,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov2735b_init_regs_1920_1080_30fps_dvp,
++	}
++};
++
++static int ov2735b_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_OV2735B_FMTS)
++		return -EINVAL;
++
++	code->code = ov2735b_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int ov2735b_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct ov2735b_format_struct *ovfmt;
++	struct ov2735b_win_size *wsize;
++	struct ov2735b_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int ov2735b_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct ov2735b_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	*(unsigned int *)fmt->reserved = &info->win->sensor_info;
++
++
++//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int ov2735b_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov2735b_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov2735b_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov2735b_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int ov2735b_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int ov2735b_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov2735b_again_lut); i++) {
++		lut = &ov2735b_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov2735b_again_lut); i++) {
++		lut = &ov2735b_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return -EINVAL;
++}
++
++static int ov2735b_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	char v = 0;
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++
++	ret = ov2735b_read(sd, 0x23, &v);
++	reg_val |= v ;
++
++	*value = regval_to_again(reg_val);
++
++	return ret;
++
++}
++/*set analog gain db value, map value to sensor register.*/
++static int ov2735b_s_again(struct v4l2_subdev *sd, int value)
++{
++	struct ov2735b_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int ret = 0;
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(value);
++	}
++
++	ret = ov2735b_write(sd, 0xfd, 0x01);
++	ret += ov2735b_write(sd, 0x24, (unsigned char)reg_value);
++	ret += ov2735b_write(sd, 0x01, 0x01);
++	if (ret < 0){
++		printk("ov2735b_write error  %d\n" ,__LINE__ );
++		return ret;
++	}
++	return 0;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int ov2735b_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov2735b_s_exp(struct v4l2_subdev *sd, int value)
++{
++	struct ov2735b_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = ov2735b_write(sd, 0xfd, 0x01);
++	ret += ov2735b_write(sd, 0x4, (unsigned char)(value & 0xff));
++	ret += ov2735b_write(sd, 0x3, (unsigned char)((value & 0xff00) >> 8));
++	ret += ov2735b_write(sd, 0x01, 0x01);
++
++	if (ret < 0) {
++		printk("ov2735b_write error  %d\n" ,__LINE__);
++		return ret;
++	}
++	return ret;
++}
++
++static int ov2735b_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov2735b_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return ov2735b_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov2735b_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int ov2735b_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov2735b_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return ov2735b_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return ov2735b_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return ov2735b_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return ov2735b_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* ov2735b_s_gain turns off auto gain */
++			return ov2735b_s_gain(sd, info->gain->val);
++		}
++		return ov2735b_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return ov2735b_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov2735b_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return ov2735b_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops ov2735b_ctrl_ops = {
++	.s_ctrl = ov2735b_s_ctrl,
++	.g_volatile_ctrl = ov2735b_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ov2735b_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = ov2735b_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int ov2735b_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	ov2735b_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++static int ov2735b_power(struct v4l2_subdev *sd, int on)
++{
++	struct ov2735b_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	int ret;
++
++	info->supply.avdd  = devm_regulator_get_optional(&client->dev, "avdd");
++	info->supply.dvdd  = devm_regulator_get_optional(&client->dev, "dvdd");
++	info->supply.dovdd = devm_regulator_get_optional(&client->dev, "dovdd");
++
++	if (IS_ERR(info->supply.avdd)||IS_ERR(info->supply.dvdd)
++		||IS_ERR(info->supply.dovdd)) {
++			if ((PTR_ERR(info->supply.avdd) == -EPROBE_DEFER)
++				||(PTR_ERR(info->supply.avdd) == -EPROBE_DEFER)
++					||(PTR_ERR(info->supply.avdd) == -EPROBE_DEFER))
++				return -EPROBE_DEFER;
++			printk("No ov2735b vdd regulator found\n");
++	}
++
++	if ((!IS_ERR(info->supply.avdd))&&(!IS_ERR(info->supply.avdd))
++			&&(!IS_ERR(info->supply.avdd)))  {
++		if(on){
++			ret = regulator_enable(info->supply.avdd);
++			ret = regulator_enable(info->supply.dvdd);
++			ret = regulator_enable(info->supply.dovdd);
++			if (ret)
++			   dev_err(&client->dev, "ov2735b vdd supply disable failed\n");
++		}
++		else{
++			ret = regulator_disable(info->supply.avdd);
++			ret = regulator_disable(info->supply.dvdd);
++			ret = regulator_disable(info->supply.dovdd);
++			if (ret)
++			    dev_err(&client->dev, "ov2735b vdd supply disable failed\n");
++		}
++	}else{
++		dev_err(&client->dev, "ov2735b vdd supply IS_ERR failed\n");
++	}
++	return ret;
++}
++
++
++
++
++int ov2735b_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct ov2735b_info *info = to_state(sd);
++	int ret = 0;
++
++	if (enable) {
++		ret = ov2735b_write_array(sd, ov2735b_stream_on);
++		pr_debug("ov2735b stream on\n");
++
++	}
++	else {
++		ret = ov2735b_write_array(sd, ov2735b_stream_off);
++		pr_debug("ov2735b stream off\n");
++	}
++	return ret;
++}
++
++int ov2735b_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct ov2735b_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops ov2735b_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = ov2735b_g_register,
++	.s_register = ov2735b_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops ov2735b_video_ops = {
++	.s_stream = ov2735b_s_stream,
++	.g_frame_interval = ov2735b_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops ov2735b_pad_ops = {
++	//.enum_frame_interval = ov2735b_enum_frame_interval,
++	//.num_frame_size = ov2735b_enum_frame_size,
++	//.enum_mbus_code = ov2735b_enum_mbus_code,
++	.set_fmt = ov2735b_set_fmt,
++	.get_fmt = ov2735b_get_fmt,
++};
++
++static const struct v4l2_subdev_ops ov2735b_ops = {
++	.core = &ov2735b_core_ops,
++	.video = &ov2735b_video_ops,
++	.pad = &ov2735b_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int ov2735b_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_subdev *sd;
++	struct ov2735b_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutp-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutp.pin = gpio;
++		info->ircutp.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutn.pin = gpio;
++		info->ircutn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	v4l2_i2c_subdev_init(sd, client, &ov2735b_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	ov2735b_power(sd,1);
++
++	/*clk*/
++	info->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++
++	ov2735b_reset(sd, 1);
++#if 1
++	/* Make sure it's an ov2735b */
++	ret = ov2735b_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an ov2735b chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++	/*IRCUT ctl 0:off 1:on*/
++	ov2735b_ircut(sd, 0);
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &ov2735b_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &ov2735b_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &ov2735b_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &ov2735b_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &ov2735b_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &ov2735b_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 259142, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov2735b_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1899 - 4, 1, 1500);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->win = &ov2735b_win_sizes[0];
++	ov2735b_init(sd, 1);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "ov2735b Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int ov2735b_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov2735b_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id ov2735b_id[] = {
++	{ "ov2735b", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ov2735b_id);
++
++static const struct of_device_id ov2735b_of_match[] = {
++	{.compatible = "ovti,ov2735b", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov2735b_of_match);
++
++
++static int ov2735b_suspend(struct device *dev)
++{
++        struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++        struct v4l2_subdev *sd = i2c_get_clientdata(client);
++        struct ov2735b_info *info = to_state(sd);
++	int ret=0;
++
++	ov2735b_power(sd,0);
++	v4l2_clk_disable(info->clk);
++        return 0;
++}
++
++static int ov2735b_resume(struct device *dev)
++{
++	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov2735b_info *info = to_state(sd);
++	int ret=0;
++
++	ov2735b_power(sd,1);
++	v4l2_clk_enable(info->clk);
++	ov2735b_reset(sd, 1);
++	ov2735b_init(sd, 1);
++	return 0;
++}
++
++const struct dev_pm_ops ov2735b_pm =
++{
++        .suspend = ov2735b_suspend,
++        .resume  = ov2735b_resume,
++};
++
++static struct i2c_driver ov2735b_driver = {
++	.driver = {
++		.name	= "ov2735b",
++		.of_match_table = of_match_ptr(ov2735b_of_match),
++		.pm	=  &ov2735b_pm,
++	},
++	.probe		= ov2735b_probe,
++	.remove		= ov2735b_remove,
++	.id_table	= ov2735b_id,
++};
++
++module_i2c_driver(ov2735b_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for OmniVision ov2735b sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/ov4689.c b/module_drivers/drivers/media/i2c/ingenic-isp/ov4689.c
+new file mode 100644
+index 000000000..462ecff03
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/ov4689.c
+@@ -0,0 +1,3224 @@
++/*
++ * A V4L2 driver for OmniVision OV4689 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++
++#include <isp-sensor.h>
++
++#define OV4689_CHIP_ID_H	(0x46)
++#define OV4689_CHIP_ID_L	(0x88)
++#define OV4689_REG_END		0xffff
++#define OV4689_REG_DELAY	0xfffe
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct ov4689_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct ov4689_gpio {
++	int pin;
++	int active_level;
++};
++
++struct ov4689_supply{
++	struct regulator *avdd;
++	struct regulator *dvdd;
++	struct regulator *dovdd;
++};
++
++struct ov4689_info {
++	struct ov4689_supply supply;
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct ov4689_win_size *win;
++
++	struct ov4689_gpio reset;
++	struct ov4689_gpio ircutp;
++	struct ov4689_gpio ircutn;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++struct again_lut ov4689_again_lut[] = {
++
++	{0x80, 0},
++	{0x88, 5731},
++	{0x90, 11136},
++	{0x98, 16248},
++	{0xa0, 21097},
++	{0xa8, 25710},
++	{0xb0, 30109},
++	{0xb8, 34312},
++	{0xc0, 38336},
++	{0xc8, 42195},
++	{0xd0, 45904},
++	{0xd8, 49472},
++	{0xe0, 52910},
++	{0xe8, 56228},
++	{0xf0, 59433},
++	{0xf8, 62534},
++	{0x178, 65536},
++	{0x17c, 68445},
++	{0x180, 71267},
++	{0x184, 74008},
++	{0x188, 76672},
++	{0x18c, 79262},
++	{0x190, 81784},
++	{0x194, 84240},
++	{0x198, 86633},
++	{0x19c, 88968},
++	{0x1a0, 91246},
++	{0x1a4, 93471},
++	{0x1a8, 95645},
++	{0x1ac, 97770},
++	{0x1b0, 99848},
++	{0x1b4, 101881},
++	{0x1b8, 103872},
++	{0x1bc, 105821},
++	{0x1c0, 107731},
++	{0x1c4, 109604},
++	{0x1c8, 111440},
++	{0x1cc, 113241},
++	{0x1d0, 115008},
++	{0x1d4, 116743},
++	{0x1d8, 118446},
++	{0x1dc, 120120},
++	{0x1e0, 121764},
++	{0x1e4, 123380},
++	{0x1e8, 124969},
++	{0x1ec, 126532},
++	{0x1f0, 128070},
++	{0x1f4, 129583},
++	{0x374, 131072},
++	{0x376, 132537},
++	{0x378, 133981},
++	{0x37a, 135403},
++	{0x37c, 136803},
++	{0x37e, 138184},
++	{0x380, 139544},
++	{0x382, 140885},
++	{0x384, 142208},
++	{0x386, 143512},
++	{0x388, 144798},
++	{0x38a, 146067},
++	{0x38c, 147320},
++	{0x38e, 148556},
++	{0x390, 149776},
++	{0x392, 150980},
++	{0x394, 152169},
++	{0x396, 153344},
++	{0x398, 154504},
++	{0x39a, 155650},
++	{0x39c, 156782},
++	{0x39e, 157901},
++	{0x3a0, 159007},
++	{0x3a2, 160100},
++	{0x3a4, 161181},
++	{0x3a6, 162249},
++	{0x3a8, 163306},
++	{0x3aa, 164350},
++	{0x3ac, 165384},
++	{0x3ae, 166406},
++	{0x3b0, 167417},
++	{0x3b2, 168418},
++	{0x3b4, 169408},
++	{0x3b6, 170387},
++	{0x3b8, 171357},
++	{0x3ba, 172317},
++	{0x3bc, 173267},
++	{0x3be, 174208},
++	{0x3c0, 175140},
++	{0x3c2, 176062},
++	{0x3c4, 176976},
++	{0x3c6, 177880},
++	{0x3c8, 178777},
++	{0x3ca, 179664},
++	{0x3cc, 180544},
++	{0x3ce, 181415},
++	{0x3d0, 182279},
++	{0x3d2, 183134},
++	{0x3d4, 183982},
++	{0x3d6, 184823},
++	{0x3d8, 185656},
++	{0x3da, 186482},
++	{0x3dc, 187300},
++	{0x3de, 188112},
++	{0x3e0, 188916},
++	{0x3e2, 189714},
++	{0x3e4, 190505},
++	{0x3e6, 191290},
++	{0x3e8, 192068},
++	{0x3ea, 192840},
++	{0x3ec, 193606},
++	{0x3ee, 194365},
++	{0x3f0, 195119},
++	{0x3f2, 195866},
++	{0x778, 196608},
++	{0x779, 197343},
++	{0x77a, 198073},
++	{0x77b, 198798},
++	{0x77c, 199517},
++	{0x77d, 200230},
++	{0x77e, 200939},
++	{0x77f, 201642},
++	{0x780, 202339},
++	{0x781, 203032},
++	{0x782, 203720},
++	{0x783, 204402},
++	{0x784, 205080},
++	{0x785, 205753},
++	{0x786, 206421},
++	{0x787, 207085},
++	{0x788, 207744},
++	{0x789, 208398},
++	{0x78a, 209048},
++	{0x78b, 209693},
++	{0x78c, 210334},
++	{0x78d, 210971},
++	{0x78e, 211603},
++	{0x78f, 212232},
++	{0x790, 212856},
++	{0x791, 213476},
++	{0x792, 214092},
++	{0x793, 214704},
++	{0x794, 215312},
++	{0x795, 215916},
++	{0x796, 216516},
++	{0x797, 217113},
++	{0x798, 217705},
++	{0x799, 218294},
++	{0x79a, 218880},
++	{0x79b, 219462},
++	{0x79c, 220040},
++	{0x79d, 220615},
++	{0x79e, 221186},
++	{0x79f, 221754},
++	{0x7a0, 222318},
++	{0x7a1, 222880},
++	{0x7a2, 223437},
++	{0x7a3, 223992},
++	{0x7a4, 224543},
++	{0x7a5, 225091},
++	{0x7a6, 225636},
++	{0x7a7, 226178},
++	{0x7a8, 226717},
++	{0x7a9, 227253},
++	{0x7aa, 227785},
++	{0x7ab, 228315},
++	{0x7ac, 228842},
++	{0x7ad, 229365},
++	{0x7ae, 229886},
++	{0x7af, 230404},
++	{0x7b0, 230920},
++	{0x7b1, 231432},
++	{0x7b2, 231942},
++	{0x7b3, 232449},
++	{0x7b4, 232953},
++	{0x7b5, 233455},
++	{0x7b6, 233954},
++	{0x7b7, 234450},
++	{0x7b8, 234944},
++	{0x7b9, 235435},
++	{0x7ba, 235923},
++	{0x7bb, 236410},
++	{0x7bc, 236893},
++	{0x7bd, 237374},
++	{0x7be, 237853},
++	{0x7bf, 238329},
++	{0x7c0, 238803},
++	{0x7c1, 239275},
++	{0x7c2, 239744},
++	{0x7c3, 240211},
++	{0x7c4, 240676},
++	{0x7c5, 241138},
++	{0x7c6, 241598},
++	{0x7c7, 242056},
++	{0x7c8, 242512},
++	{0x7c9, 242965},
++	{0x7ca, 243416},
++	{0x7cb, 243865},
++	{0x7cc, 244313},
++	{0x7cd, 244757},
++	{0x7ce, 245200},
++	{0x7cf, 245641},
++	{0x7d0, 246080},
++	{0x7d1, 246517},
++	{0x7d2, 246951},
++	{0x7d3, 247384},
++	{0x7d4, 247815},
++	{0x7d5, 248243},
++	{0x7d6, 248670},
++	{0x7d7, 249095},
++	{0x7d8, 249518},
++	{0x7d9, 249939},
++	{0x7da, 250359},
++	{0x7db, 250776},
++	{0x7dc, 251192},
++	{0x7dd, 251606},
++	{0x7de, 252018},
++	{0x7df, 252428},
++	{0x7e0, 252836},
++	{0x7e1, 253243},
++	{0x7e2, 253648},
++	{0x7e3, 254051},
++	{0x7e4, 254452},
++	{0x7e5, 254852},
++	{0x7e6, 255250},
++	{0x7e7, 255647},
++	{0x7e8, 256041},
++	{0x7e9, 256435},
++	{0x7ea, 256826},
++	{0x7eb, 257216},
++	{0x7ec, 257604},
++	{0x7ed, 257991},
++	{0x7ee, 258376},
++	{0x7ef, 258760},
++	{0x7f0, 259142},
++	{0x7f1, 259522},
++	{0x7f2, 259901},
++	{0x7f3, 260279},
++	{0x7f4, 260655},
++	{0x7f5, 261029},
++	{0x7f6, 261402},
++	{0x7f7, 261773},
++};
++
++static inline struct ov4689_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct ov4689_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct ov4689_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++
++static struct regval_list ov4689_init_regs_1920_1080_120fps_mipi[] = {
++	//	@@ 0 35 RES_1920x1080_120fps_1008Mbps
++	//		100 99 1920 1080
++	//102 3601 2ee0
++
++	{ 0x0103, 0x01 }, 
++	{ 0x3638, 0x00 }, 
++	{ 0x0300, 0x00 }, 
++	{ 0x0302, 0x2a }, 
++	{ 0x0303, 0x00 }, 
++	{ 0x0304, 0x03 }, 
++	{ 0x030b, 0x00 }, 
++	{ 0x030d, 0x1e }, 
++	{ 0x030e, 0x04 }, 
++	{ 0x030f, 0x01 }, 
++	{ 0x0312, 0x01 }, 
++	{ 0x031e, 0x00 }, 
++	{ 0x3000, 0x20 }, 
++	{ 0x3002, 0x00 }, 
++	{ 0x3018, 0x72 }, 
++	{ 0x3020, 0x93 }, 
++	{ 0x3021, 0x03 }, 
++	{ 0x3022, 0x01 }, 
++	{ 0x3031, 0x0a }, 
++	{ 0x303f, 0x0c },
++	{ 0x3305, 0xf1 }, 
++	{ 0x3307, 0x04 }, 
++	{ 0x3309, 0x29 }, 
++	{ 0x3500, 0x00 }, 
++	{ 0x3501, 0x4c }, 
++	{ 0x3502, 0x00 }, 
++	{ 0x3503, 0x04 }, 
++	{ 0x3504, 0x00 }, 
++	{ 0x3505, 0x00 }, 
++	{ 0x3506, 0x00 }, 
++	{ 0x3507, 0x00 }, 
++	{ 0x3508, 0x00 }, 
++	{ 0x3509, 0x80 }, 
++	{ 0x350a, 0x00 }, 
++	{ 0x350b, 0x00 }, 
++	{ 0x350c, 0x00 }, 
++	{ 0x350d, 0x00 }, 
++	{ 0x350e, 0x00 }, 
++	{ 0x350f, 0x80 }, 
++	{ 0x3510, 0x00 }, 
++	{ 0x3511, 0x00 }, 
++	{ 0x3512, 0x00 }, 
++	{ 0x3513, 0x00 }, 
++	{ 0x3514, 0x00 }, 
++	{ 0x3515, 0x80 }, 
++	{ 0x3516, 0x00 }, 
++	{ 0x3517, 0x00 }, 
++	{ 0x3518, 0x00 }, 
++	{ 0x3519, 0x00 }, 
++	{ 0x351a, 0x00 }, 
++	{ 0x351b, 0x80 }, 
++	{ 0x351c, 0x00 }, 
++	{ 0x351d, 0x00 }, 
++	{ 0x351e, 0x00 }, 
++	{ 0x351f, 0x00 }, 
++	{ 0x3520, 0x00 }, 
++	{ 0x3521, 0x80 }, 
++	{ 0x3522, 0x08 }, 
++	{ 0x3524, 0x08 }, 
++	{ 0x3526, 0x08 }, 
++	{ 0x3528, 0x08 }, 
++	{ 0x352a, 0x08 }, 
++	{ 0x3602, 0x00 }, 
++	{ 0x3603, 0x40 }, 
++	{ 0x3604, 0x02 }, 
++	{ 0x3605, 0x00 }, 
++	{ 0x3606, 0x00 }, 
++	{ 0x3607, 0x00 }, 
++	{ 0x3609, 0x12 }, 
++	{ 0x360a, 0x40 }, 
++	{ 0x360c, 0x08 }, 
++	{ 0x360f, 0xe5 }, 
++	{ 0x3608, 0x8f }, 
++	{ 0x3611, 0x00 }, 
++	{ 0x3613, 0xf7 }, 
++	{ 0x3616, 0x58 }, 
++	{ 0x3619, 0x99 }, 
++	{ 0x361b, 0x60 }, 
++	{ 0x361c, 0x7a }, 
++	{ 0x361e, 0x79 }, 
++	{ 0x361f, 0x02 }, 
++	{ 0x3632, 0x00 }, 
++	{ 0x3633, 0x10 }, 
++	{ 0x3634, 0x10 }, 
++	{ 0x3635, 0x10 }, 
++	{ 0x3636, 0x15 }, 
++	{ 0x3646, 0x86 }, 
++	{ 0x364a, 0x0b }, 
++	{ 0x3700, 0x17 }, 
++	{ 0x3701, 0x22 }, 
++	{ 0x3703, 0x10 }, 
++	{ 0x370a, 0x37 }, 
++	{ 0x3705, 0x00 }, 
++	{ 0x3706, 0x63 }, 
++	{ 0x3709, 0x3c }, 
++	{ 0x370b, 0x01 }, 
++	{ 0x370c, 0x30 }, 
++	{ 0x3710, 0x24 }, 
++	{ 0x3711, 0x0c }, 
++	{ 0x3716, 0x00 }, 
++	{ 0x3720, 0x28 }, 
++	{ 0x3729, 0x7b }, 
++	{ 0x372a, 0x84 }, 
++	{ 0x372b, 0xbd }, 
++	{ 0x372c, 0xbc }, 
++	{ 0x372e, 0x52 }, 
++	{ 0x373c, 0x0e }, 
++	{ 0x373e, 0x33 }, 
++	{ 0x3743, 0x10 }, 
++	{ 0x3744, 0x88 }, 
++	{ 0x3745, 0xc0 }, 
++	{ 0x374a, 0x43 }, 
++	{ 0x374c, 0x00 }, 
++	{ 0x374e, 0x23 }, 
++	{ 0x3751, 0x7b }, 
++	{ 0x3752, 0x84 }, 
++	{ 0x3753, 0xbd }, 
++	{ 0x3754, 0xbc }, 
++	{ 0x3756, 0x52 }, 
++	{ 0x375c, 0x00 }, 
++	{ 0x3760, 0x00 }, 
++	{ 0x3761, 0x00 }, 
++	{ 0x3762, 0x00 }, 
++	{ 0x3763, 0x00 }, 
++	{ 0x3764, 0x00 }, 
++	{ 0x3767, 0x04 }, 
++	{ 0x3768, 0x04 }, 
++	{ 0x3769, 0x08 }, 
++	{ 0x376a, 0x08 }, 
++	{ 0x376b, 0x20 }, 
++	{ 0x376c, 0x00 }, 
++	{ 0x376d, 0x00 }, 
++	{ 0x376e, 0x00 }, 
++	{ 0x3773, 0x00 }, 
++	{ 0x3774, 0x51 }, 
++	{ 0x3776, 0xbd }, 
++	{ 0x3777, 0xbd }, 
++	{ 0x3781, 0x18 }, 
++	{ 0x3783, 0x25 }, 
++	{ 0x3798, 0x1b }, 
++	{ 0x3800, 0x01 }, 
++	{ 0x3801, 0x88 }, 
++	{ 0x3802, 0x00 }, 
++	{ 0x3803, 0xe0 }, 
++	{ 0x3804, 0x09 }, 
++	{ 0x3805, 0x17 }, 
++	{ 0x3806, 0x05 }, 
++	{ 0x3807, 0x1f }, 
++	{ 0x3808, 0x07 }, 
++	{ 0x3809, 0x80 }, 
++	{ 0x380a, 0x04 }, 
++	{ 0x380b, 0x38 }, 
++	{ 0x380c, 0x03 }, 
++	{ 0x380d, 0x5c }, 
++	{ 0x380e, 0x04 }, 
++	{ 0x380f, 0x8A }, 
++	{ 0x3810, 0x00 }, 
++	{ 0x3811, 0x08 }, 
++	{ 0x3812, 0x00 }, 
++	{ 0x3813, 0x04 }, 
++	{ 0x3814, 0x01 }, 
++	{ 0x3815, 0x01 }, 
++	{ 0x3819, 0x01 }, 
++	{ 0x3820, 0x00 }, 
++	{ 0x3821, 0x06 }, 
++	{ 0x3829, 0x00 }, 
++	{ 0x382a, 0x01 }, 
++	{ 0x382b, 0x01 }, 
++	{ 0x382d, 0x7f }, 
++	{ 0x3830, 0x04 }, 
++	{ 0x3836, 0x01 }, 
++	{ 0x3837, 0x00 }, 
++	{ 0x3841, 0x02 }, 
++	{ 0x3846, 0x08 }, 
++	{ 0x3847, 0x07 }, 
++	{ 0x3d85, 0x36 }, 
++	{ 0x3d8c, 0x71 }, 
++	{ 0x3d8d, 0xcb }, 
++	{ 0x3f0a, 0x00 }, 
++	{ 0x4000, 0xf1 }, 
++	{ 0x4001, 0x40 }, 
++	{ 0x4002, 0x04 }, 
++	{ 0x4003, 0x14 }, 
++	{ 0x400e, 0x00 }, 
++	{ 0x4011, 0x00 }, 
++	{ 0x401a, 0x00 }, 
++	{ 0x401b, 0x00 }, 
++	{ 0x401c, 0x00 }, 
++	{ 0x401d, 0x00 }, 
++	{ 0x401f, 0x00 }, 
++	{ 0x4020, 0x00 }, 
++	{ 0x4021, 0x10 }, 
++	{ 0x4022, 0x06 }, 
++	{ 0x4023, 0x13 }, 
++	{ 0x4024, 0x07 }, 
++	{ 0x4025, 0x40 }, 
++	{ 0x4026, 0x07 }, 
++	{ 0x4027, 0x50 }, 
++	{ 0x4028, 0x00 }, 
++	{ 0x4029, 0x02 }, 
++	{ 0x402a, 0x06 }, 
++	{ 0x402b, 0x04 }, 
++	{ 0x402c, 0x02 }, 
++	{ 0x402d, 0x02 }, 
++	{ 0x402e, 0x0e }, 
++	{ 0x402f, 0x04 }, 
++	{ 0x4302, 0xff }, 
++	{ 0x4303, 0xff }, 
++	{ 0x4304, 0x00 }, 
++	{ 0x4305, 0x00 }, 
++	{ 0x4306, 0x00 }, 
++	{ 0x4308, 0x02 }, 
++	{ 0x4500, 0x6c }, 
++	{ 0x4501, 0xc4 }, 
++	{ 0x4502, 0x40 }, 
++	{ 0x4503, 0x01 }, 
++	{ 0x4601, 0x77 }, 
++	{ 0x4800, 0x04 }, 
++	{ 0x4813, 0x08 }, 
++	{ 0x481f, 0x40 }, 
++	{ 0x4829, 0x78 }, 
++	{ 0x4837, 0x10 },  // 
++	{ 0x4b00, 0x2a }, 
++	{ 0x4b0d, 0x00 }, 
++	{ 0x4d00, 0x04 }, 
++	{ 0x4d01, 0x42 },
++	{ 0x4d02, 0xd1 }, 
++	{ 0x4d03, 0x93 }, 
++	{ 0x4d04, 0xf5 }, 
++	{ 0x4d05, 0xc1 }, 
++	{ 0x5000, 0xf3 }, 
++	{ 0x5001, 0x11 }, 
++	{ 0x5004, 0x00 }, 
++	{ 0x500a, 0x00 }, 
++	{ 0x500b, 0x00 }, 
++	{ 0x5032, 0x00 }, 
++	{ 0x5040, 0x00 }, 
++	{ 0x5050, 0x0c }, 
++	{ 0x5500, 0x00 }, 
++	{ 0x5501, 0x10 }, 
++	{ 0x5502, 0x01 }, 
++	{ 0x5503, 0x0f }, 
++	{ 0x8000, 0x00 }, 
++	{ 0x8001, 0x00 }, 
++	{ 0x8002, 0x00 }, 
++	{ 0x8003, 0x00 }, 
++	{ 0x8004, 0x00 }, 
++	{ 0x8005, 0x00 }, 
++	{ 0x8006, 0x00 }, 
++	{ 0x8007, 0x00 }, 
++	{ 0x8008, 0x00 }, 
++	{ 0x3638, 0x00 }, 
++	{ 0x0100, 0x00 }, 
++//	{ 0x5040, 0x80 }, /* color bar */
++	{OV4689_REG_END, 0x00},/* END MARKER */
++};
++
++static struct regval_list ov4689_init_regs_1920_1080_30fps_mipi[] = {
++#if 0 //1080p@30fps 1 lane ok
++	/* @@ 0 35 RES_1920x1080_30fps_816Mbps  1Lane */
++	/* ;SCLK = 80MHz MIPI CLK = 816Mbps/lane Mipi PCLK = 102MHz */
++	/* ;HTS = 2294 VTS = 1162 */
++	{0x0103, 0x01},
++	{0x3638, 0x00},
++	{0x0300, 0x00},
++	{0x0302, 0x22},
++	{0x0303, 0x00},
++	{0x0304, 0x03},
++	{0x030b, 0x00},
++	{0x030d, 0x1e},
++	{0x030e, 0x04},
++	{0x030f, 0x02},
++	{0x0312, 0x01},
++	{0x031e, 0x00},
++	{0x3000, 0x20},
++	{0x3002, 0x00},
++	{0x3018, 0x02},
++	{0x3020, 0x93},
++	{0x3021, 0x03},
++	{0x3022, 0x01},
++	{0x3031, 0x0a},
++	{0x303f, 0x0c},
++	{0x3305, 0xf1},
++	{0x3307, 0x04},
++	{0x3309, 0x29},
++	{0x3500, 0x00},
++	{0x3501, 0x4c},
++	{0x3502, 0x00},
++	{0x3503, 0x04},
++	{0x3504, 0x00},
++	{0x3505, 0x00},
++	{0x3506, 0x00},
++	{0x3507, 0x00},
++	{0x3508, 0x00},
++	{0x3509, 0x80},
++	{0x350a, 0x00},
++	{0x350b, 0x00},
++	{0x350c, 0x00},
++	{0x350d, 0x00},
++	{0x350e, 0x00},
++	{0x350f, 0x80},
++	{0x3510, 0x00},
++	{0x3511, 0x00},
++	{0x3512, 0x00},
++	{0x3513, 0x00},
++	{0x3514, 0x00},
++	{0x3515, 0x80},
++	{0x3516, 0x00},
++	{0x3517, 0x00},
++	{0x3518, 0x00},
++	{0x3519, 0x00},
++	{0x351a, 0x00},
++	{0x351b, 0x80},
++	{0x351c, 0x00},
++	{0x351d, 0x00},
++	{0x351e, 0x00},
++	{0x351f, 0x00},
++	{0x3520, 0x00},
++	{0x3521, 0x80},
++	{0x3522, 0x08},
++	{0x3524, 0x08},
++	{0x3526, 0x08},
++	{0x3528, 0x08},
++	{0x352a, 0x08},
++	{0x3602, 0x00},
++	{0x3603, 0x40},
++	{0x3604, 0x02},
++	{0x3605, 0x00},
++	{0x3606, 0x00},
++	{0x3607, 0x00},
++	{0x3609, 0x12},
++	{0x360a, 0x40},
++	{0x360c, 0x08},
++	{0x360f, 0xe5},
++	{0x3608, 0x8f},
++	{0x3611, 0x00},
++	{0x3613, 0xf7},
++	{0x3616, 0x58},
++	{0x3619, 0x99},
++	{0x361b, 0x60},
++	{0x361c, 0x7a},
++	{0x361e, 0x79},
++	{0x361f, 0x02},
++	{0x3632, 0x00},
++	{0x3633, 0x10},
++	{0x3634, 0x10},
++	{0x3635, 0x10},
++	{0x3636, 0x15},
++	{0x3646, 0x86},
++	{0x364a, 0x0b},
++	{0x3700, 0x17},
++	{0x3701, 0x22},
++	{0x3703, 0x10},
++	{0x370a, 0x37},
++	{0x3705, 0x00},
++	{0x3706, 0x63},
++	{0x3709, 0x3c},
++	{0x370b, 0x01},
++	{0x370c, 0x30},
++	{0x3710, 0x24},
++	{0x3711, 0x0c},
++	{0x3716, 0x00},
++	{0x3720, 0x28},
++	{0x3729, 0x7b},
++	{0x372a, 0x84},
++	{0x372b, 0xbd},
++	{0x372c, 0xbc},
++	{0x372e, 0x52},
++	{0x373c, 0x0e},
++	{0x373e, 0x33},
++	{0x3743, 0x10},
++	{0x3744, 0x88},
++	{0x3745, 0xc0},
++	{0x374a, 0x43},
++	{0x374c, 0x00},
++	{0x374e, 0x23},
++	{0x3751, 0x7b},
++	{0x3752, 0x84},
++	{0x3753, 0xbd},
++	{0x3754, 0xbc},
++	{0x3756, 0x52},
++	{0x375c, 0x00},
++	{0x3760, 0x00},
++	{0x3761, 0x00},
++	{0x3762, 0x00},
++	{0x3763, 0x00},
++	{0x3764, 0x00},
++	{0x3767, 0x04},
++	{0x3768, 0x04},
++	{0x3769, 0x08},
++	{0x376a, 0x08},
++	{0x376b, 0x20},
++	{0x376c, 0x00},
++	{0x376d, 0x00},
++	{0x376e, 0x00},
++	{0x3773, 0x00},
++	{0x3774, 0x51},
++	{0x3776, 0xbd},
++	{0x3777, 0xbd},
++	{0x3781, 0x18},
++	{0x3783, 0x25},
++	{0x3798, 0x1b},
++	{0x3800, 0x01},
++	{0x3801, 0x88},
++	{0x3802, 0x00},
++	{0x3803, 0xe0},
++	{0x3804, 0x09},
++	{0x3805, 0x17},
++	{0x3806, 0x05},
++	{0x3807, 0x1f},
++	{0x3808, 0x07},
++	{0x3809, 0x80},
++	{0x380a, 0x04},
++	{0x380b, 0x38},
++	{0x380c, 0x08},
++	{0x380d, 0xf6},
++	{0x380e, 0x04},
++	{0x380f, 0x8A},
++	{0x3810, 0x00},
++	{0x3811, 0x08},
++	{0x3812, 0x00},
++	{0x3813, 0x04},
++	{0x3814, 0x01},
++	{0x3815, 0x01},
++	{0x3819, 0x01},
++	{0x3820, 0x00},
++	{0x3821, 0x06},
++	{0x3829, 0x00},
++	{0x382a, 0x01},
++	{0x382b, 0x01},
++	{0x382d, 0x7f},
++	{0x3830, 0x04},
++	{0x3836, 0x01},
++	{0x3837, 0x00},
++	{0x3841, 0x02},
++	{0x3846, 0x08},
++	{0x3847, 0x07},
++	{0x3d85, 0x36},
++	{0x3d8c, 0x71},
++	{0x3d8d, 0xcb},
++	{0x3f0a, 0x00},
++	{0x4000, 0xf1},
++	{0x4001, 0x40},
++	{0x4002, 0x04},
++	{0x4003, 0x14},
++	{0x400e, 0x00},
++	{0x4011, 0x00},
++	{0x401a, 0x00},
++	{0x401b, 0x00},
++	{0x401c, 0x00},
++	{0x401d, 0x00},
++	{0x401f, 0x00},
++	{0x4020, 0x00},
++	{0x4021, 0x10},
++	{0x4022, 0x06},
++	{0x4023, 0x13},
++	{0x4024, 0x07},
++	{0x4025, 0x40},
++	{0x4026, 0x07},
++	{0x4027, 0x50},
++	{0x4028, 0x00},
++	{0x4029, 0x02},
++	{0x402a, 0x06},
++	{0x402b, 0x04},
++	{0x402c, 0x02},
++	{0x402d, 0x02},
++	{0x402e, 0x0e},
++	{0x402f, 0x04},
++	{0x4302, 0xff},
++	{0x4303, 0xff},
++	{0x4304, 0x00},
++	{0x4305, 0x00},
++	{0x4306, 0x00},
++	{0x4308, 0x02},
++	{0x4500, 0x6c},
++	{0x4501, 0xc4},
++	{0x4502, 0x40},
++	{0x4503, 0x01},
++	{0x4601, 0x77},
++	{0x4800, 0x04},
++	{0x4813, 0x08},
++	{0x481f, 0x40},
++	{0x4829, 0x78},
++	{0x4837, 0x2d},
++	{0x4b00, 0x2a},
++	{0x4b0d, 0x00},
++	{0x4d00, 0x04},
++	{0x4d01, 0x42},
++	{0x4d02, 0xd1},
++	{0x4d03, 0x93},
++	{0x4d04, 0xf5},
++	{0x4d05, 0xc1},
++	{0x5000, 0xf3},
++	{0x5001, 0x11},
++	{0x5004, 0x00},
++	{0x500a, 0x00},
++	{0x500b, 0x00},
++	{0x5032, 0x00},
++	{0x5040, 0x00},
++	{0x5050, 0x0c},
++	{0x5500, 0x00},
++	{0x5501, 0x10},
++	{0x5502, 0x01},
++	{0x5503, 0x0f},
++	{0x8000, 0x00},
++	{0x8001, 0x00},
++	{0x8002, 0x00},
++	{0x8003, 0x00},
++	{0x8004, 0x00},
++	{0x8005, 0x00},
++	{0x8006, 0x00},
++	{0x8007, 0x00},
++	{0x8008, 0x00},
++	{0x3638, 0x00},
++#endif
++#if 1
++	//1080p@30fps 2 or 4 lane
++	/* @@ 0 35 RES_1920x1080_30fps_816Mbps  2Lane */
++	/* ;SCLK = 80MHz MIPI CLK = 816Mbps/lane Mipi PCLK = 102MHz */
++	/* ;HTS = 2294 VTS = 1162 */
++	{0x0103, 0x01},
++	{0x3638, 0x00},
++	{0x0300, 0x00},
++	{0x0302, 0x23},
++	{0x0303, 0x01},
++	{0x0304, 0x03},
++	{0x030b, 0x00},
++	{0x030d, 0x1e},
++	{0x030e, 0x04},
++	{0x030f, 0x02},
++	{0x0312, 0x01},
++	{0x031e, 0x00},
++	{0x3000, 0x20},
++	{0x3002, 0x00},
++//	{0x3018, 0x72}, //4lan
++	{0x3018, 0x32}, //2lan
++	{0x3020, 0x93},
++	{0x3021, 0x03},
++	{0x3022, 0x01},
++	{0x3031, 0x0a},
++	{0x303f, 0x0c},
++	{0x3305, 0xf1},
++	{0x3307, 0x04},
++	{0x3309, 0x29},
++	{0x3500, 0x00},
++	{0x3501, 0x4c},
++	{0x3502, 0x00},
++	{0x3503, 0x04},
++	{0x3504, 0x00},
++	{0x3505, 0x00},
++	{0x3506, 0x00},
++	{0x3507, 0x00},
++	{0x3508, 0x00},
++	{0x3509, 0x80},
++	{0x350a, 0x00},
++	{0x350b, 0x00},
++	{0x350c, 0x00},
++	{0x350d, 0x00},
++	{0x350e, 0x00},
++	{0x350f, 0x80},
++	{0x3510, 0x00},
++	{0x3511, 0x00},
++	{0x3512, 0x00},
++	{0x3513, 0x00},
++	{0x3514, 0x00},
++	{0x3515, 0x80},
++	{0x3516, 0x00},
++	{0x3517, 0x00},
++	{0x3518, 0x00},
++	{0x3519, 0x00},
++	{0x351a, 0x00},
++	{0x351b, 0x80},
++	{0x351c, 0x00},
++	{0x351d, 0x00},
++	{0x351e, 0x00},
++	{0x351f, 0x00},
++	{0x3520, 0x00},
++	{0x3521, 0x80},
++	{0x3522, 0x08},
++	{0x3524, 0x08},
++	{0x3526, 0x08},
++	{0x3528, 0x08},
++	{0x352a, 0x08},
++	{0x3602, 0x00},
++	{0x3603, 0x40},
++	{0x3604, 0x02},
++	{0x3605, 0x00},
++	{0x3606, 0x00},
++	{0x3607, 0x00},
++	{0x3609, 0x12},
++	{0x360a, 0x40},
++	{0x360c, 0x08},
++	{0x360f, 0xe5},
++	{0x3608, 0x8f},
++	{0x3611, 0x00},
++	{0x3613, 0xf7},
++	{0x3616, 0x58},
++	{0x3619, 0x99},
++	{0x361b, 0x60},
++	{0x361c, 0x7a},
++	{0x361e, 0x79},
++	{0x361f, 0x02},
++	{0x3632, 0x00},
++	{0x3633, 0x10},
++	{0x3634, 0x10},
++	{0x3635, 0x10},
++	{0x3636, 0x15},
++	{0x3646, 0x86},
++	{0x364a, 0x0b},
++	{0x3700, 0x17},
++	{0x3701, 0x22},
++	{0x3703, 0x10},
++	{0x370a, 0x37},
++	{0x3705, 0x00},
++	{0x3706, 0x63},
++	{0x3709, 0x3c},
++	{0x370b, 0x01},
++	{0x370c, 0x30},
++	{0x3710, 0x24},
++	{0x3711, 0x0c},
++	{0x3716, 0x00},
++	{0x3720, 0x28},
++	{0x3729, 0x7b},
++	{0x372a, 0x84},
++	{0x372b, 0xbd},
++	{0x372c, 0xbc},
++	{0x372e, 0x52},
++	{0x373c, 0x0e},
++	{0x373e, 0x33},
++	{0x3743, 0x10},
++	{0x3744, 0x88},
++	{0x3745, 0xc0},
++	{0x374a, 0x43},
++	{0x374c, 0x00},
++	{0x374e, 0x23},
++	{0x3751, 0x7b},
++	{0x3752, 0x84},
++	{0x3753, 0xbd},
++	{0x3754, 0xbc},
++	{0x3756, 0x52},
++	{0x375c, 0x00},
++	{0x3760, 0x00},
++	{0x3761, 0x00},
++	{0x3762, 0x00},
++	{0x3763, 0x00},
++	{0x3764, 0x00},
++	{0x3767, 0x04},
++	{0x3768, 0x04},
++	{0x3769, 0x08},
++	{0x376a, 0x08},
++	{0x376b, 0x20},
++	{0x376c, 0x00},
++	{0x376d, 0x00},
++	{0x376e, 0x00},
++	{0x3773, 0x00},
++	{0x3774, 0x51},
++	{0x3776, 0xbd},
++	{0x3777, 0xbd},
++	{0x3781, 0x18},
++	{0x3783, 0x25},
++	{0x3798, 0x1b},
++	{0x3800, 0x01},
++	{0x3801, 0x88},
++	{0x3802, 0x00},
++	{0x3803, 0xe0},
++	{0x3804, 0x09},
++	{0x3805, 0x17},
++	{0x3806, 0x05},
++	{0x3807, 0x1f},
++	{0x3808, 0x07},
++	{0x3809, 0x80},
++	{0x380a, 0x04},
++	{0x380b, 0x38},
++	{0x380c, 0x08},
++	{0x380d, 0xf6},
++	{0x380e, 0x04},
++	{0x380f, 0x8A},
++	{0x3810, 0x00},
++	{0x3811, 0x08},
++	{0x3812, 0x00},
++	{0x3813, 0x04},
++	{0x3814, 0x01},
++	{0x3815, 0x01},
++	{0x3819, 0x01},
++	{0x3820, 0x00},
++	{0x3821, 0x06},
++	{0x3829, 0x00},
++	{0x382a, 0x01},
++	{0x382b, 0x01},
++	{0x382d, 0x7f},
++	{0x3830, 0x04},
++	{0x3836, 0x01},
++	{0x3837, 0x00},
++	{0x3841, 0x02},
++	{0x3846, 0x08},
++	{0x3847, 0x07},
++	{0x3d85, 0x36},
++	{0x3d8c, 0x71},
++	{0x3d8d, 0xcb},
++	{0x3f0a, 0x00},
++	{0x4000, 0xf1},
++	{0x4001, 0x40},
++	{0x4002, 0x04},
++	{0x4003, 0x14},
++	{0x400e, 0x00},
++	{0x4011, 0x00},
++	{0x401a, 0x00},
++	{0x401b, 0x00},
++	{0x401c, 0x00},
++	{0x401d, 0x00},
++	{0x401f, 0x00},
++	{0x4020, 0x00},
++	{0x4021, 0x10},
++	{0x4022, 0x06},
++	{0x4023, 0x13},
++	{0x4024, 0x07},
++	{0x4025, 0x40},
++	{0x4026, 0x07},
++	{0x4027, 0x50},
++	{0x4028, 0x00},
++	{0x4029, 0x02},
++	{0x402a, 0x06},
++	{0x402b, 0x04},
++	{0x402c, 0x02},
++	{0x402d, 0x02},
++	{0x402e, 0x0e},
++	{0x402f, 0x04},
++	{0x4302, 0xff},
++	{0x4303, 0xff},
++	{0x4304, 0x00},
++	{0x4305, 0x00},
++	{0x4306, 0x00},
++	{0x4308, 0x02},
++	{0x4500, 0x6c},
++	{0x4501, 0xc4},
++	{0x4502, 0x40},
++	{0x4503, 0x01},
++	{0x4601, 0x77},
++	{0x4800, 0x04},
++	{0x4813, 0x08},
++	{0x481f, 0x40},
++	{0x4829, 0x78},
++//	{0x4837, 0x14}, //for zebra
++	{0x4837, 0x80}, //for halley5
++	{0x4b00, 0x2a},
++	{0x4b0d, 0x00},
++	{0x4d00, 0x04},
++	{0x4d01, 0x42},
++	{0x4d02, 0xd1},
++	{0x4d03, 0x93},
++	{0x4d04, 0xf5},
++	{0x4d05, 0xc1},
++	{0x5000, 0xf3},
++	{0x5001, 0x11},
++	{0x5004, 0x00},
++	{0x500a, 0x00},
++	{0x500b, 0x00},
++	{0x5032, 0x00},
++	{0x5040, 0x00},
++	{0x5050, 0x0c},
++	{0x5500, 0x00},
++	{0x5501, 0x10},
++	{0x5502, 0x01},
++	{0x5503, 0x0f},
++	{0x8000, 0x00},
++	{0x8001, 0x00},
++	{0x8002, 0x00},
++	{0x8003, 0x00},
++	{0x8004, 0x00},
++	{0x8005, 0x00},
++	{0x8006, 0x00},
++	{0x8007, 0x00},
++	{0x8008, 0x00},
++	{0x3638, 0x00},
++#endif
++#if 0
++	/*support by ov , dosen't word in zebra & halley5*/
++//	@@ 0 35 RES_1920x1080_30fps_1008Mbps 4lane
++//100 99 1920 1080
++//102 3601 2ee0
++	{ 0x0103, 0x01 }, 
++	{ 0x3638, 0x00 }, 
++	{ 0x0300, 0x00 }, 
++	{ 0x0302, 0x2a }, 
++	{ 0x0303, 0x00 },
++	{ 0x0304, 0x03 }, 
++	{ 0x030b, 0x00 }, 
++	{ 0x030d, 0x1e }, 
++	{ 0x030e, 0x04 }, 
++	{ 0x030f, 0x01 }, 
++	{ 0x0312, 0x01 }, 
++	{ 0x031e, 0x00 }, 
++	{ 0x3000, 0x20 }, 
++	{ 0x3002, 0x00 }, 
++	{ 0x3018, 0x72 }, 
++//	{ 0x3018, 0x32 }, 
++	{ 0x3020, 0x93 }, 
++	{ 0x3021, 0x03 }, 
++	{ 0x3022, 0x01 }, 
++	{ 0x3031, 0x0a }, 
++	{ 0x303f, 0x0c },
++	{ 0x3305, 0xf1 }, 
++	{ 0x3307, 0x04 }, 
++	{ 0x3309, 0x29 }, 
++	{ 0x3500, 0x00 }, 
++	{ 0x3501, 0x4c }, 
++	{ 0x3502, 0x00 }, 
++	{ 0x3503, 0x04 }, 
++	{ 0x3504, 0x00 }, 
++	{ 0x3505, 0x00 }, 
++	{ 0x3506, 0x00 }, 
++	{ 0x3507, 0x00 }, 
++	{ 0x3508, 0x00 }, 
++	{ 0x3509, 0x80 }, 
++	{ 0x350a, 0x00 }, 
++	{ 0x350b, 0x00 }, 
++	{ 0x350c, 0x00 }, 
++	{ 0x350d, 0x00 }, 
++	{ 0x350e, 0x00 }, 
++	{ 0x350f, 0x80 }, 
++	{ 0x3510, 0x00 }, 
++	{ 0x3511, 0x00 }, 
++	{ 0x3512, 0x00 }, 
++	{ 0x3513, 0x00 }, 
++	{ 0x3514, 0x00 }, 
++	{ 0x3515, 0x80 }, 
++	{ 0x3516, 0x00 }, 
++	{ 0x3517, 0x00 }, 
++	{ 0x3518, 0x00 }, 
++	{ 0x3519, 0x00 }, 
++	{ 0x351a, 0x00 }, 
++	{ 0x351b, 0x80 }, 
++	{ 0x351c, 0x00 }, 
++	{ 0x351d, 0x00 }, 
++	{ 0x351e, 0x00 }, 
++	{ 0x351f, 0x00 }, 
++	{ 0x3520, 0x00 }, 
++	{ 0x3521, 0x80 }, 
++	{ 0x3522, 0x08 }, 
++	{ 0x3524, 0x08 }, 
++	{ 0x3526, 0x08 }, 
++	{ 0x3528, 0x08 }, 
++	{ 0x352a, 0x08 }, 
++	{ 0x3602, 0x00 }, 
++	{ 0x3603, 0x40 }, 
++	{ 0x3604, 0x02 }, 
++	{ 0x3605, 0x00 }, 
++	{ 0x3606, 0x00 }, 
++	{ 0x3607, 0x00 }, 
++	{ 0x3609, 0x12 }, 
++	{ 0x360a, 0x40 }, 
++	{ 0x360c, 0x08 }, 
++	{ 0x360f, 0xe5 }, 
++	{ 0x3608, 0x8f }, 
++	{ 0x3611, 0x00 }, 
++	{ 0x3613, 0xf7 }, 
++	{ 0x3616, 0x58 }, 
++	{ 0x3619, 0x99 }, 
++	{ 0x361b, 0x60 }, 
++	{ 0x361c, 0x7a }, 
++	{ 0x361e, 0x79 }, 
++	{ 0x361f, 0x02 }, 
++	{ 0x3632, 0x00 }, 
++	{ 0x3633, 0x10 }, 
++	{ 0x3634, 0x10 }, 
++	{ 0x3635, 0x10 }, 
++	{ 0x3636, 0x15 }, 
++	{ 0x3646, 0x86 }, 
++	{ 0x364a, 0x0b }, 
++	{ 0x3700, 0x17 }, 
++	{ 0x3701, 0x22 }, 
++	{ 0x3703, 0x10 }, 
++	{ 0x370a, 0x37 }, 
++	{ 0x3705, 0x00 }, 
++	{ 0x3706, 0x63 }, 
++	{ 0x3709, 0x3c }, 
++	{ 0x370b, 0x01 }, 
++	{ 0x370c, 0x30 }, 
++	{ 0x3710, 0x24 }, 
++	{ 0x3711, 0x0c }, 
++	{ 0x3716, 0x00 }, 
++	{ 0x3720, 0x28 }, 
++	{ 0x3729, 0x7b }, 
++	{ 0x372a, 0x84 }, 
++	{ 0x372b, 0xbd }, 
++	{ 0x372c, 0xbc }, 
++	{ 0x372e, 0x52 }, 
++	{ 0x373c, 0x0e }, 
++	{ 0x373e, 0x33 }, 
++	{ 0x3743, 0x10 }, 
++	{ 0x3744, 0x88 }, 
++	{ 0x3745, 0xc0 }, 
++	{ 0x374a, 0x43 }, 
++	{ 0x374c, 0x00 }, 
++	{ 0x374e, 0x23 }, 
++	{ 0x3751, 0x7b }, 
++	{ 0x3752, 0x84 }, 
++	{ 0x3753, 0xbd }, 
++	{ 0x3754, 0xbc }, 
++	{ 0x3756, 0x52 }, 
++	{ 0x375c, 0x00 }, 
++	{ 0x3760, 0x00 }, 
++	{ 0x3761, 0x00 }, 
++	{ 0x3762, 0x00 }, 
++	{ 0x3763, 0x00 }, 
++	{ 0x3764, 0x00 }, 
++	{ 0x3767, 0x04 }, 
++	{ 0x3768, 0x04 }, 
++	{ 0x3769, 0x08 }, 
++	{ 0x376a, 0x08 }, 
++	{ 0x376b, 0x20 }, 
++	{ 0x376c, 0x00 }, 
++	{ 0x376d, 0x00 }, 
++	{ 0x376e, 0x00 }, 
++	{ 0x3773, 0x00 }, 
++	{ 0x3774, 0x51 }, 
++	{ 0x3776, 0xbd }, 
++	{ 0x3777, 0xbd }, 
++	{ 0x3781, 0x18 }, 
++	{ 0x3783, 0x25 }, 
++	{ 0x3798, 0x1b }, 
++	{ 0x3800, 0x01 }, 
++	{ 0x3801, 0x88 }, 
++	{ 0x3802, 0x00 }, 
++	{ 0x3803, 0xe0 }, 
++	{ 0x3804, 0x09 }, 
++	{ 0x3805, 0x17 }, 
++	{ 0x3806, 0x05 }, 
++	{ 0x3807, 0x1f }, 
++	{ 0x3808, 0x07 }, 
++	{ 0x3809, 0x80 }, 
++	{ 0x380a, 0x04 }, 
++	{ 0x380b, 0x38 }, 
++	{ 0x380c, 0x06 }, 
++	{ 0x380d, 0xb8 }, 
++	{ 0x380e, 0x09 }, 
++	{ 0x380f, 0x14 }, 
++	{ 0x3810, 0x00 }, 
++	{ 0x3811, 0x08 }, 
++	{ 0x3812, 0x00 }, 
++	{ 0x3813, 0x04 }, 
++	{ 0x3814, 0x01 }, 
++	{ 0x3815, 0x01 }, 
++	{ 0x3819, 0x01 }, 
++	{ 0x3820, 0x00 }, 
++	{ 0x3821, 0x06 }, 
++	{ 0x3829, 0x00 }, 
++	{ 0x382a, 0x01 }, 
++	{ 0x382b, 0x01 }, 
++	{ 0x382d, 0x7f }, 
++	{ 0x3830, 0x04 }, 
++	{ 0x3836, 0x01 }, 
++	{ 0x3837, 0x00 }, 
++	{ 0x3841, 0x02 }, 
++	{ 0x3846, 0x08 }, 
++	{ 0x3847, 0x07 }, 
++	{ 0x3d85, 0x36 }, 
++	{ 0x3d8c, 0x71 }, 
++	{ 0x3d8d, 0xcb }, 
++	{ 0x3f0a, 0x00 }, 
++	{ 0x4000, 0xf1 }, 
++	{ 0x4001, 0x40 }, 
++	{ 0x4002, 0x04 }, 
++	{ 0x4003, 0x14 }, 
++	{ 0x400e, 0x00 }, 
++	{ 0x4011, 0x00 }, 
++	{ 0x401a, 0x00 }, 
++	{ 0x401b, 0x00 }, 
++	{ 0x401c, 0x00 }, 
++	{ 0x401d, 0x00 }, 
++	{ 0x401f, 0x00 }, 
++	{ 0x4020, 0x00 }, 
++	{ 0x4021, 0x10 }, 
++	{ 0x4022, 0x06 }, 
++	{ 0x4023, 0x13 }, 
++	{ 0x4024, 0x07 }, 
++	{ 0x4025, 0x40 }, 
++	{ 0x4026, 0x07 }, 
++	{ 0x4027, 0x50 }, 
++	{ 0x4028, 0x00 }, 
++	{ 0x4029, 0x02 }, 
++	{ 0x402a, 0x06 }, 
++	{ 0x402b, 0x04 }, 
++	{ 0x402c, 0x02 }, 
++	{ 0x402d, 0x02 }, 
++	{ 0x402e, 0x0e }, 
++	{ 0x402f, 0x04 }, 
++	{ 0x4302, 0xff }, 
++	{ 0x4303, 0xff }, 
++	{ 0x4304, 0x00 }, 
++	{ 0x4305, 0x00 }, 
++	{ 0x4306, 0x00 }, 
++	{ 0x4308, 0x02 }, 
++	{ 0x4500, 0x6c }, 
++	{ 0x4501, 0xc4 }, 
++	{ 0x4502, 0x40 }, 
++	{ 0x4503, 0x01 }, 
++	{ 0x4601, 0x77 }, 
++	{ 0x4800, 0x04 }, 
++	{ 0x4813, 0x08 }, 
++	{ 0x481f, 0x40 }, 
++	{ 0x4829, 0x78 }, 
++	{ 0x4837, 0x10 }, 
++	{ 0x4b00, 0x2a }, 
++	{ 0x4b0d, 0x00 }, 
++	{ 0x4d00, 0x04 }, 
++	{ 0x4d01, 0x42 },
++	{ 0x4d02, 0xd1 }, 
++	{ 0x4d03, 0x93 }, 
++	{ 0x4d04, 0xf5 }, 
++	{ 0x4d05, 0xc1 }, 
++	{ 0x5000, 0xf3 }, 
++	{ 0x5001, 0x11 }, 
++	{ 0x5004, 0x00 }, 
++	{ 0x500a, 0x00 }, 
++	{ 0x500b, 0x00 }, 
++	{ 0x5032, 0x00 }, 
++	{ 0x5040, 0x00 }, 
++	{ 0x5050, 0x0c }, 
++	{ 0x5500, 0x00 }, 
++	{ 0x5501, 0x10 }, 
++	{ 0x5502, 0x01 }, 
++	{ 0x5503, 0x0f }, 
++	{ 0x8000, 0x00 }, 
++	{ 0x8001, 0x00 }, 
++	{ 0x8002, 0x00 }, 
++	{ 0x8003, 0x00 }, 
++	{ 0x8004, 0x00 }, 
++	{ 0x8005, 0x00 }, 
++	{ 0x8006, 0x00 }, 
++	{ 0x8007, 0x00 }, 
++	{ 0x8008, 0x00 }, 
++	{ 0x3638, 0x00 }, 
++#endif
++	{0x0100, 0x00},
++//	{0x5040, 0x80},
++	{OV4689_REG_END, 0x00},/* END MARKER */
++};
++
++static struct regval_list ov4689_init_regs_2048_1520_30fps_mipi[] = {
++#if 0
++	/* @@ 0 35 RES_2048x1520_23.37fps_408Mbps  2Lane */
++	/* ;SCLK = 80MHz MIPI CLK = 408Mbps/lane Mipi PCLK = 51MHz */
++	/* ;HTS = 2200 VTS = 1556 */
++	{0x0103, 0x01},
++	{0x3638, 0x00},
++	{0x0300, 0x00},
++	{0x0302, 0x22},
++	{0x0303, 0x01},
++	{0x0304, 0x03},
++	{0x030b, 0x00},
++	{0x030d, 0x1e},
++	{0x030e, 0x04},
++	{0x030f, 0x02},
++	{0x0312, 0x01},
++	{0x031e, 0x00},
++	{0x3000, 0x20},
++	{0x3002, 0x00},
++	{0x3018, 0x32},
++	{0x3020, 0x93},
++	{0x3021, 0x03},
++	{0x3022, 0x01},
++	{0x3031, 0x0a},
++	{0x303f, 0x0c},
++	{0x3305, 0xf1},
++	{0x3307, 0x04},
++	{0x3309, 0x29},
++	{0x3500, 0x00},
++	{0x3501, 0x4c},
++	{0x3502, 0x00},
++	{0x3503, 0x04},
++	{0x3504, 0x00},
++	{0x3505, 0x00},
++	{0x3506, 0x00},
++	{0x3507, 0x00},
++	{0x3508, 0x00},
++	{0x3509, 0x80},
++	{0x350a, 0x00},
++	{0x350b, 0x00},
++	{0x350c, 0x00},
++	{0x350d, 0x00},
++	{0x350e, 0x00},
++	{0x350f, 0x80},
++	{0x3510, 0x00},
++	{0x3511, 0x00},
++	{0x3512, 0x00},
++	{0x3513, 0x00},
++	{0x3514, 0x00},
++	{0x3515, 0x80},
++	{0x3516, 0x00},
++	{0x3517, 0x00},
++	{0x3518, 0x00},
++	{0x3519, 0x00},
++	{0x351a, 0x00},
++	{0x351b, 0x80},
++	{0x351c, 0x00},
++	{0x351d, 0x00},
++	{0x351e, 0x00},
++	{0x351f, 0x00},
++	{0x3520, 0x00},
++	{0x3521, 0x80},
++	{0x3522, 0x08},
++	{0x3524, 0x08},
++	{0x3526, 0x08},
++	{0x3528, 0x08},
++	{0x352a, 0x08},
++	{0x3602, 0x00},
++	{0x3603, 0x40},
++	{0x3604, 0x02},
++	{0x3605, 0x00},
++	{0x3606, 0x00},
++	{0x3607, 0x00},
++	{0x3609, 0x12},
++	{0x360a, 0x40},
++	{0x360c, 0x08},
++	{0x360f, 0xe5},
++	{0x3608, 0x8f},
++	{0x3611, 0x00},
++	{0x3613, 0xf7},
++	{0x3616, 0x58},
++	{0x3619, 0x99},
++	{0x361b, 0x60},
++	{0x361c, 0x7a},
++	{0x361e, 0x79},
++	{0x361f, 0x02},
++	{0x3632, 0x00},
++	{0x3633, 0x10},
++	{0x3634, 0x10},
++	{0x3635, 0x10},
++	{0x3636, 0x15},
++	{0x3646, 0x86},
++	{0x364a, 0x0b},
++	{0x3700, 0x17},
++	{0x3701, 0x22},
++	{0x3703, 0x10},
++	{0x370a, 0x37},
++	{0x3705, 0x00},
++	{0x3706, 0x63},
++	{0x3709, 0x3c},
++	{0x370b, 0x01},
++	{0x370c, 0x30},
++	{0x3710, 0x24},
++	{0x3711, 0x0c},
++	{0x3716, 0x00},
++	{0x3720, 0x28},
++	{0x3729, 0x7b},
++	{0x372a, 0x84},
++	{0x372b, 0xbd},
++	{0x372c, 0xbc},
++	{0x372e, 0x52},
++	{0x373c, 0x0e},
++	{0x373e, 0x33},
++	{0x3743, 0x10},
++	{0x3744, 0x88},
++	{0x3745, 0xc0},
++	{0x374a, 0x43},
++	{0x374c, 0x00},
++	{0x374e, 0x23},
++	{0x3751, 0x7b},
++	{0x3752, 0x84},
++	{0x3753, 0xbd},
++	{0x3754, 0xbc},
++	{0x3756, 0x52},
++	{0x375c, 0x00},
++	{0x3760, 0x00},
++	{0x3761, 0x00},
++	{0x3762, 0x00},
++	{0x3763, 0x00},
++	{0x3764, 0x00},
++	{0x3767, 0x04},
++	{0x3768, 0x04},
++	{0x3769, 0x08},
++	{0x376a, 0x08},
++	{0x376b, 0x20},
++	{0x376c, 0x00},
++	{0x376d, 0x00},
++	{0x376e, 0x00},
++	{0x3773, 0x00},
++	{0x3774, 0x51},
++	{0x3776, 0xbd},
++	{0x3777, 0xbd},
++	{0x3781, 0x18},
++	{0x3783, 0x25},
++	{0x3798, 0x1b},
++	{0x3800, 0x01},
++	{0x3801, 0x48},
++	{0x3802, 0x00},
++	{0x3803, 0x04},
++	{0x3804, 0x09},
++	{0x3805, 0x57},
++	{0x3806, 0x05},
++	{0x3807, 0xFB},
++	{0x3808, 0x08},
++	{0x3809, 0x00},
++	{0x380A, 0x05},
++	{0x380B, 0xF0},
++	{0x380C, 0x08},
++	{0x380D, 0x98},
++	{0x380E, 0x06},
++	{0x380F, 0x14},
++	{0x3810, 0x00},
++	{0x3811, 0x08},
++	{0x3812, 0x00},
++	{0x3813, 0x04},
++	{0x3814, 0x01},
++	{0x3815, 0x01},
++	{0x3819, 0x01},
++	{0x3820, 0x00},
++	{0x3821, 0x06},
++	{0x3829, 0x00},
++	{0x382a, 0x01},
++	{0x382b, 0x01},
++	{0x382d, 0x7f},
++	{0x3830, 0x04},
++	{0x3836, 0x01},
++	{0x3837, 0x00},
++	{0x3841, 0x02},
++	{0x3846, 0x08},
++	{0x3847, 0x07},
++	{0x3d85, 0x36},
++	{0x3d8c, 0x71},
++	{0x3d8d, 0xcb},
++	{0x3f0a, 0x00},
++	{0x4000, 0xf1},
++	{0x4001, 0x40},
++	{0x4002, 0x04},
++	{0x4003, 0x14},
++	{0x400e, 0x00},
++	{0x4011, 0x00},
++	{0x401a, 0x00},
++	{0x401b, 0x00},
++	{0x401c, 0x00},
++	{0x401d, 0x00},
++	{0x401f, 0x00},
++	{0x4020, 0x00},
++	{0x4021, 0x10},
++	{0x4022, 0x06},
++	{0x4023, 0x93},
++	{0x4024, 0x07},
++	{0x4025, 0xC0},
++	{0x4026, 0x07},
++	{0x4027, 0xD0},
++	{0x4028, 0x00},
++	{0x4029, 0x02},
++	{0x402a, 0x06},
++	{0x402b, 0x04},
++	{0x402c, 0x02},
++	{0x402d, 0x02},
++	{0x402e, 0x0e},
++	{0x402f, 0x04},
++	{0x4302, 0xff},
++	{0x4303, 0xff},
++	{0x4304, 0x00},
++	{0x4305, 0x00},
++	{0x4306, 0x00},
++	{0x4308, 0x02},
++	{0x4500, 0x6c},
++	{0x4501, 0xc4},
++	{0x4502, 0x40},
++	{0x4503, 0x01},
++	{0x4601, 0x7f},
++	{0x4800, 0x04},
++	{0x4813, 0x08},
++	{0x481f, 0x40},
++	{0x4829, 0x78},
++	{0x4837, 0x14},
++	{0x4b00, 0x2a},
++	{0x4b0d, 0x00},
++	{0x4d00, 0x04},
++	{0x4d01, 0x42},
++	{0x4d02, 0xd1},
++	{0x4d03, 0x93},
++	{0x4d04, 0xf5},
++	{0x4d05, 0xc1},
++	{0x5000, 0xf3},
++	{0x5001, 0x11},
++	{0x5004, 0x00},
++	{0x500a, 0x00},
++	{0x500b, 0x00},
++	{0x5032, 0x00},
++	{0x5040, 0x00},
++	{0x5050, 0x0c},
++	{0x5500, 0x00},
++	{0x5501, 0x10},
++	{0x5502, 0x01},
++	{0x5503, 0x0f},
++	{0x8000, 0x00},
++	{0x8001, 0x00},
++	{0x8002, 0x00},
++	{0x8003, 0x00},
++	{0x8004, 0x00},
++	{0x8005, 0x00},
++	{0x8006, 0x00},
++	{0x8007, 0x00},
++	{0x8008, 0x00},
++	{0x3638, 0x00},
++	{0x0100, 0x00},
++#endif
++
++#if 1
++	/* @@ 0 35 RES_2048x1520_30fps_600Mbps  2Lane                   */
++	/* ;SCLK = 120 MHz MIPI CLK = 600Mbps/lane Mipi PCLK = 75MHz         */
++	/* ;HTS = 2570 VTS = 1556      */
++	{0x0103, 0x01},
++	{0x3638, 0x00},
++	{0x0300, 0x00},
++	{0x0302, 0x19},
++	{0x0303, 0x00},
++	{0x0304, 0x03},
++	{0x030b, 0x00},
++	{0x030d, 0x1e},
++	{0x030e, 0x04},
++	{0x030f, 0x01},
++	{0x0312, 0x01},
++	{0x031e, 0x00},
++	{0x3000, 0x20},
++	{0x3002, 0x00},
++	{0x3018, 0x32},
++	{0x3020, 0x93},
++	{0x3021, 0x03},
++	{0x3022, 0x01},
++	{0x3031, 0x0a},
++	{0x303f, 0x0c},
++	{0x3305, 0xf1},
++	{0x3307, 0x04},
++	{0x3309, 0x29},
++	{0x3500, 0x00},
++	{0x3501, 0x4c},
++	{0x3502, 0x00},
++	{0x3503, 0x04},
++	{0x3504, 0x00},
++	{0x3505, 0x00},
++	{0x3506, 0x00},
++	{0x3507, 0x00},
++	{0x3508, 0x00},
++	{0x3509, 0x80},
++	{0x350a, 0x00},
++	{0x350b, 0x00},
++	{0x350c, 0x00},
++	{0x350d, 0x00},
++	{0x350e, 0x00},
++	{0x350f, 0x80},
++	{0x3510, 0x00},
++	{0x3511, 0x00},
++	{0x3512, 0x00},
++	{0x3513, 0x00},
++	{0x3514, 0x00},
++	{0x3515, 0x80},
++	{0x3516, 0x00},
++	{0x3517, 0x00},
++	{0x3518, 0x00},
++	{0x3519, 0x00},
++	{0x351a, 0x00},
++	{0x351b, 0x80},
++	{0x351c, 0x00},
++	{0x351d, 0x00},
++	{0x351e, 0x00},
++	{0x351f, 0x00},
++	{0x3520, 0x00},
++	{0x3521, 0x80},
++	{0x3522, 0x08},
++	{0x3524, 0x08},
++	{0x3526, 0x08},
++	{0x3528, 0x08},
++	{0x352a, 0x08},
++	{0x3602, 0x00},
++	{0x3603, 0x40},
++	{0x3604, 0x02},
++	{0x3605, 0x00},
++	{0x3606, 0x00},
++	{0x3607, 0x00},
++	{0x3609, 0x12},
++	{0x360a, 0x40},
++	{0x360c, 0x08},
++	{0x360f, 0xe5},
++	{0x3608, 0x8f},
++	{0x3611, 0x00},
++	{0x3613, 0xf7},
++	{0x3616, 0x58},
++	{0x3619, 0x99},
++	{0x361b, 0x60},
++	{0x361c, 0x7a},
++	{0x361e, 0x79},
++	{0x361f, 0x02},
++	{0x3632, 0x00},
++	{0x3633, 0x10},
++	{0x3634, 0x10},
++	{0x3635, 0x10},
++	{0x3636, 0x15},
++	{0x3646, 0x86},
++	{0x364a, 0x0b},
++	{0x3700, 0x17},
++	{0x3701, 0x22},
++	{0x3703, 0x10},
++	{0x370a, 0x37},
++	{0x3705, 0x00},
++	{0x3706, 0x63},
++	{0x3709, 0x3c},
++	{0x370b, 0x01},
++	{0x370c, 0x30},
++	{0x3710, 0x24},
++	{0x3711, 0x0c},
++	{0x3716, 0x00},
++	{0x3720, 0x28},
++	{0x3729, 0x7b},
++	{0x372a, 0x84},
++	{0x372b, 0xbd},
++	{0x372c, 0xbc},
++	{0x372e, 0x52},
++	{0x373c, 0x0e},
++	{0x373e, 0x33},
++	{0x3743, 0x10},
++	{0x3744, 0x88},
++	{0x3745, 0xc0},
++	{0x374a, 0x43},
++	{0x374c, 0x00},
++	{0x374e, 0x23},
++	{0x3751, 0x7b},
++	{0x3752, 0x84},
++	{0x3753, 0xbd},
++	{0x3754, 0xbc},
++	{0x3756, 0x52},
++	{0x375c, 0x00},
++	{0x3760, 0x00},
++	{0x3761, 0x00},
++	{0x3762, 0x00},
++	{0x3763, 0x00},
++	{0x3764, 0x00},
++	{0x3767, 0x04},
++	{0x3768, 0x04},
++	{0x3769, 0x08},
++	{0x376a, 0x08},
++	{0x376b, 0x20},
++	{0x376c, 0x00},
++	{0x376d, 0x00},
++	{0x376e, 0x00},
++	{0x3773, 0x00},
++	{0x3774, 0x51},
++	{0x3776, 0xbd},
++	{0x3777, 0xbd},
++	{0x3781, 0x18},
++	{0x3783, 0x25},
++	{0x3798, 0x1b},
++	{0x3800, 0x01},
++	{0x3801, 0x48},
++	{0x3802, 0x00},
++	{0x3803, 0x04},
++	{0x3804, 0x09},
++	{0x3805, 0x57},
++	{0x3806, 0x05},
++	{0x3807, 0xFB},
++	{0x3808, 0x08},
++	{0x3809, 0x00},
++	{0x380A, 0x05},
++	{0x380B, 0xF0},
++	{0x380C, 0x0a},
++	{0x380D, 0x0a},
++	{0x380E, 0x06},
++	{0x380F, 0x14},
++	{0x3810, 0x00},
++	{0x3811, 0x08},
++	{0x3812, 0x00},
++	{0x3813, 0x04},
++	{0x3814, 0x01},
++	{0x3815, 0x01},
++	{0x3819, 0x01},
++	{0x3820, 0x00},
++	{0x3821, 0x06},
++	{0x3829, 0x00},
++	{0x382a, 0x01},
++	{0x382b, 0x01},
++	{0x382d, 0x7f},
++	{0x3830, 0x04},
++	{0x3836, 0x01},
++	{0x3837, 0x00},
++	{0x3841, 0x02},
++	{0x3846, 0x08},
++	{0x3847, 0x07},
++	{0x3d85, 0x36},
++	{0x3d8c, 0x71},
++	{0x3d8d, 0xcb},
++	{0x3f0a, 0x00},
++	{0x4000, 0xf1},
++	{0x4001, 0x40},
++	{0x4002, 0x04},
++	{0x4003, 0x14},
++	{0x400e, 0x00},
++	{0x4011, 0x00},
++	{0x401a, 0x00},
++	{0x401b, 0x00},
++	{0x401c, 0x00},
++	{0x401d, 0x00},
++	{0x401f, 0x00},
++	{0x4020, 0x00},
++	{0x4021, 0x10},
++	{0x4022, 0x06},
++	{0x4023, 0x93},
++	{0x4024, 0x07},
++	{0x4025, 0xC0},
++	{0x4026, 0x07},
++	{0x4027, 0xD0},
++	{0x4028, 0x00},
++	{0x4029, 0x02},
++	{0x402a, 0x06},
++	{0x402b, 0x04},
++	{0x402c, 0x02},
++	{0x402d, 0x02},
++	{0x402e, 0x0e},
++	{0x402f, 0x04},
++	{0x4302, 0xff},
++	{0x4303, 0xff},
++	{0x4304, 0x00},
++	{0x4305, 0x00},
++	{0x4306, 0x00},
++	{0x4308, 0x02},
++	{0x4500, 0x6c},
++	{0x4501, 0xc4},
++	{0x4502, 0x40},
++	{0x4503, 0x01},
++	{0x4601, 0x7f},
++	{0x4800, 0x04},
++	{0x4813, 0x08},
++	{0x481f, 0x40},
++	{0x4829, 0x78},
++	{0x4837, 0x2d},
++	{0x4b00, 0x2a},
++	{0x4b0d, 0x00},
++	{0x4d00, 0x04},
++	{0x4d01, 0x42},
++	{0x4d02, 0xd1},
++	{0x4d03, 0x93},
++	{0x4d04, 0xf5},
++	{0x4d05, 0xc1},
++	{0x5000, 0xf3},
++	{0x5001, 0x11},
++	{0x5004, 0x00},
++	{0x500a, 0x00},
++	{0x500b, 0x00},
++	{0x5032, 0x00},
++	{0x5040, 0x00},
++	{0x5050, 0x0c},
++	{0x5500, 0x00},
++	{0x5501, 0x10},
++	{0x5502, 0x01},
++	{0x5503, 0x0f},
++	{0x8000, 0x00},
++	{0x8001, 0x00},
++	{0x8002, 0x00},
++	{0x8003, 0x00},
++	{0x8004, 0x00},
++	{0x8005, 0x00},
++	{0x8006, 0x00},
++	{0x8007, 0x00},
++	{0x8008, 0x00},
++	{0x3638, 0x00},
++	{0x0100, 0x00},
++#endif
++
++#if 0
++	/* @@ 0 35 RES_2048x1520_25fps_420Mbps  2Lane */
++	/* ;SCLK = 82.7MHz MIPI CLK = 420Mbps/lane Mipi PCLK = 52.5MHz */
++	/* ;HTS = 2125 VTS = 1556 */
++	{0x0103, 0x01},
++	{0x3638, 0x00},
++	{0x0300, 0x00},
++	{0x0302, 0x23},
++	{0x0303, 0x01},
++	{0x0304, 0x03},
++	{0x030b, 0x00},
++	{0x030d, 0x1f},
++	{0x030e, 0x04},
++	{0x030f, 0x02},
++	{0x0312, 0x01},
++	{0x031e, 0x00},
++	{0x3000, 0x20},
++	{0x3002, 0x00},
++#ifdef DRIVE_CAPABILITY_1
++	{0x3011,0x00},
++#elif defined(DRIVE_CAPABILITY_2)
++	{0x3011,0x20},
++#elif defined(DRIVE_CAPABILITY_3)
++	{0x3011,0x40},
++#elif defined(DRIVE_CAPABILITY_4)
++	{0x3011,0x60},
++#endif
++	{0x3018, 0x32},
++	{0x3020, 0x93},
++	{0x3021, 0x03},
++	{0x3022, 0x01},
++	{0x3031, 0x0a},
++	{0x303f, 0x0c},
++	{0x3037, 0x01},
++//	{0x303f, 0x0d},
++//	{0x3012, 0x22},
++	{0x3305, 0xf1},
++	{0x3307, 0x04},
++	{0x3309, 0x29},
++	{0x3500, 0x00},
++	{0x3501, 0x4c},
++	{0x3502, 0x00},
++	{0x3503, 0x04},
++	{0x3504, 0x00},
++	{0x3505, 0x00},
++	{0x3506, 0x00},
++	{0x3507, 0x00},
++	{0x3508, 0x00},
++	{0x3509, 0x80},
++	{0x350a, 0x00},
++	{0x350b, 0x00},
++	{0x350c, 0x00},
++	{0x350d, 0x00},
++	{0x350e, 0x00},
++	{0x350f, 0x80},
++	{0x3510, 0x00},
++	{0x3511, 0x00},
++	{0x3512, 0x00},
++	{0x3513, 0x00},
++	{0x3514, 0x00},
++	{0x3515, 0x80},
++	{0x3516, 0x00},
++	{0x3517, 0x00},
++	{0x3518, 0x00},
++	{0x3519, 0x00},
++	{0x351a, 0x00},
++	{0x351b, 0x80},
++	{0x351c, 0x00},
++	{0x351d, 0x00},
++	{0x351e, 0x00},
++	{0x351f, 0x00},
++	{0x3520, 0x00},
++	{0x3521, 0x80},
++	{0x3522, 0x08},
++	{0x3524, 0x08},
++	{0x3526, 0x08},
++	{0x3528, 0x08},
++	{0x352a, 0x08},
++	{0x3602, 0x00},
++	{0x3603, 0x40},
++	{0x3604, 0x02},
++	{0x3605, 0x00},
++	{0x3606, 0x00},
++	{0x3607, 0x00},
++	{0x3609, 0x12},
++	{0x360a, 0x40},
++	{0x360c, 0x08},
++	{0x360f, 0xe5},
++	{0x3608, 0x8f},
++	{0x3611, 0x00},
++	{0x3613, 0xf7},
++	{0x3616, 0x58},
++	{0x3619, 0x99},
++	{0x361b, 0x60},
++	{0x361c, 0x7a},
++	{0x361e, 0x79},
++	{0x361f, 0x02},
++	{0x3632, 0x00},
++	{0x3633, 0x10},
++	{0x3634, 0x10},
++	{0x3635, 0x10},
++	{0x3636, 0x15},
++	{0x3646, 0x86},
++	{0x364a, 0x0b},
++	{0x3700, 0x17},
++	{0x3701, 0x22},
++	{0x3703, 0x10},
++	{0x370a, 0x37},
++	{0x3705, 0x00},
++	{0x3706, 0x63},
++	{0x3709, 0x3c},
++	{0x370b, 0x01},
++	{0x370c, 0x30},
++	{0x3710, 0x24},
++	{0x3711, 0x0c},
++	{0x3716, 0x00},
++	{0x3720, 0x28},
++	{0x3729, 0x7b},
++	{0x372a, 0x84},
++	{0x372b, 0xbd},
++	{0x372c, 0xbc},
++	{0x372e, 0x52},
++	{0x373c, 0x0e},
++	{0x373e, 0x33},
++	{0x3743, 0x10},
++	{0x3744, 0x88},
++	{0x3745, 0xc0},
++	{0x374a, 0x43},
++	{0x374c, 0x00},
++	{0x374e, 0x23},
++	{0x3751, 0x7b},
++	{0x3752, 0x84},
++	{0x3753, 0xbd},
++	{0x3754, 0xbc},
++	{0x3756, 0x52},
++	{0x375c, 0x00},
++	{0x3760, 0x00},
++	{0x3761, 0x00},
++	{0x3762, 0x00},
++	{0x3763, 0x00},
++	{0x3764, 0x00},
++	{0x3767, 0x04},
++	{0x3768, 0x04},
++	{0x3769, 0x08},
++	{0x376a, 0x08},
++	{0x376b, 0x20},
++	{0x376c, 0x00},
++	{0x376d, 0x00},
++	{0x376e, 0x00},
++	{0x3773, 0x00},
++	{0x3774, 0x51},
++	{0x3776, 0xbd},
++	{0x3777, 0xbd},
++	{0x3781, 0x18},
++	{0x3783, 0x25},
++	{0x3798, 0x1b},
++	{0x3800, 0x01},
++	{0x3801, 0x48},
++	{0x3802, 0x00},
++	{0x3803, 0x04},
++	{0x3804, 0x09},
++	{0x3805, 0x57},
++	{0x3806, 0x05},
++	{0x3807, 0xFB},
++	{0x3808, 0x08},
++	{0x3809, 0x00},
++	{0x380A, 0x05},
++	{0x380B, 0xF0},
++	{0x380C, 0x08},
++	{0x380D, 0x4d},
++	{0x380E, 0x06},
++	{0x380F, 0x14},
++	{0x3810, 0x00},
++	{0x3811, 0x08},
++	{0x3812, 0x00},
++	{0x3813, 0x04},
++	{0x3814, 0x01},
++	{0x3815, 0x01},
++	{0x3819, 0x01},
++	{0x3820, 0x00},
++	{0x3821, 0x06},
++	{0x3829, 0x00},
++	{0x382a, 0x01},
++	{0x382b, 0x01},
++	{0x382d, 0x7f},
++	{0x3830, 0x04},
++	{0x3836, 0x01},
++	{0x3837, 0x00},
++	{0x3841, 0x02},
++	{0x3846, 0x08},
++	{0x3847, 0x07},
++	{0x3d85, 0x36},
++	{0x3d8c, 0x71},
++	{0x3d8d, 0xcb},
++	{0x3f0a, 0x00},
++	{0x4000, 0xf1},
++	{0x4001, 0x40},
++	{0x4002, 0x04},
++	{0x4003, 0x14},
++	{0x400e, 0x00},
++	{0x4011, 0x00},
++	{0x401a, 0x00},
++	{0x401b, 0x00},
++	{0x401c, 0x00},
++	{0x401d, 0x00},
++	{0x401f, 0x00},
++	{0x4020, 0x00},
++	{0x4021, 0x10},
++	{0x4022, 0x06},
++	{0x4023, 0x93},
++	{0x4024, 0x07},
++	{0x4025, 0xC0},
++	{0x4026, 0x07},
++	{0x4027, 0xD0},
++	{0x4028, 0x00},
++	{0x4029, 0x02},
++	{0x402a, 0x06},
++	{0x402b, 0x04},
++	{0x402c, 0x02},
++	{0x402d, 0x02},
++	{0x402e, 0x0e},
++	{0x402f, 0x04},
++	{0x4302, 0xff},
++	{0x4303, 0xff},
++	{0x4304, 0x00},
++	{0x4305, 0x00},
++	{0x4306, 0x00},
++	{0x4308, 0x02},
++	{0x4500, 0x6c},
++	{0x4501, 0xc4},
++	{0x4502, 0x40},
++	{0x4503, 0x01},
++	{0x4601, 0x7f},
++	{0x4800, 0x04},
++	{0x4813, 0x08},
++	{0x481f, 0x40},
++	{0x4829, 0x78},
++	{0x4837, 0x14},
++	{0x4b00, 0x2a},
++	{0x4b0d, 0x00},
++	{0x4d00, 0x04},
++	{0x4d01, 0x42},
++	{0x4d02, 0xd1},
++	{0x4d03, 0x93},
++	{0x4d04, 0xf5},
++	{0x4d05, 0xc1},
++	{0x5000, 0xf3},
++	{0x5001, 0x11},
++	{0x5004, 0x00},
++	{0x500a, 0x00},
++	{0x500b, 0x00},
++	{0x5032, 0x00},
++	{0x5040, 0x00},
++	{0x5050, 0x0c},
++	{0x5500, 0x00},
++	{0x5501, 0x10},
++	{0x5502, 0x01},
++	{0x5503, 0x0f},
++	{0x8000, 0x00},
++	{0x8001, 0x00},
++	{0x8002, 0x00},
++	{0x8003, 0x00},
++	{0x8004, 0x00},
++	{0x8005, 0x00},
++	{0x8006, 0x00},
++	{0x8007, 0x00},
++	{0x8008, 0x00},
++	{0x3638, 0x00},
++	//{0x5040, 0x80},//color bar
++	{0x0100, 0x00},
++#endif
++	{OV4689_REG_END, 0x00},/* END MARKER */
++};
++
++static struct regval_list ov4689_init_regs_2592_1520_30fps_mipi[] = {
++	{0x0103, 0x01},
++	{0x3638, 0x00},
++	{0x0300, 0x00},
++	{0x0302, 0x19}, //0x19
++	{0x0303, 0x00},
++	{0x0304, 0x03}, //0x03
++	{0x030b, 0x00},
++	{0x030d, 0x1e},
++	{0x030e, 0x04},
++	{0x030f, 0x01},
++	{0x0311, 0x00},
++	{0x0312, 0x01},
++	{0x031e, 0x00},
++	{0x3000, 0x20},
++	{0x3002, 0x00},
++	{0x3018, 0x32},
++	{0x3019, 0x0c},
++	{0x3020, 0x93},
++	{0x3021, 0x03},
++	{0x3022, 0x01},
++	{0x3031, 0x0a},
++	{0x303f, 0x0c},
++	{0x3305, 0xf1},
++	{0x3307, 0x04},
++	{0x3309, 0x29},
++	{0x3500, 0x00},
++	{0x3501, 0x60},
++	{0x3502, 0x00},
++	{0x3503, 0x04},
++	{0x3504, 0x00},
++	{0x3505, 0x00},
++	{0x3506, 0x00},
++	{0x3507, 0x00},
++	{0x3508, 0x00},
++	{0x3509, 0x80},
++	{0x350a, 0x00},
++	{0x350b, 0x00},
++	{0x350c, 0x00},
++	{0x350d, 0x00},
++	{0x350e, 0x00},
++	{0x350f, 0x80},
++	{0x3510, 0x00},
++	{0x3511, 0x00},
++	{0x3512, 0x00},
++	{0x3513, 0x00},
++	{0x3514, 0x00},
++	{0x3515, 0x80},
++	{0x3516, 0x00},
++	{0x3517, 0x00},
++	{0x3518, 0x00},
++	{0x3519, 0x00},
++	{0x351a, 0x00},
++	{0x351b, 0x80},
++	{0x351c, 0x00},
++	{0x351d, 0x00},
++	{0x351e, 0x00},
++	{0x351f, 0x00},
++	{0x3520, 0x00},
++	{0x3521, 0x80},
++	{0x3522, 0x08},
++	{0x3524, 0x08},
++	{0x3526, 0x08},
++	{0x3528, 0x08},
++	{0x352a, 0x08},
++	{0x3602, 0x00},
++	{0x3603, 0x40},
++	{0x3604, 0x02},
++	{0x3605, 0x00},
++	{0x3606, 0x00},
++	{0x3607, 0x00},
++	{0x3609, 0x12},
++	{0x360a, 0x40},
++	{0x360c, 0x08},
++	{0x360f, 0xe5},
++	{0x3608, 0x8f},
++	{0x3611, 0x00},
++	{0x3613, 0xf7},
++	{0x3616, 0x58},
++	{0x3619, 0x99},
++	{0x361b, 0x60},
++	{0x361c, 0x7a},
++	{0x361e, 0x79},
++	{0x361f, 0x02},
++	{0x3632, 0x00},
++	{0x3633, 0x10},
++	{0x3634, 0x10},
++	{0x3635, 0x10},
++	{0x3636, 0x15},
++	{0x3646, 0x86},
++	{0x364a, 0x0b},
++	{0x3700, 0x17},
++	{0x3701, 0x22},
++	{0x3703, 0x10},
++	{0x370a, 0x37},
++	{0x3705, 0x00},
++	{0x3706, 0x63},
++	{0x3709, 0x3c},
++	{0x370b, 0x01},
++	{0x370c, 0x30},
++	{0x3710, 0x24},
++	{0x3711, 0x0c},
++	{0x3716, 0x00},
++	{0x3720, 0x28},
++	{0x3729, 0x7b},
++	{0x372a, 0x84},
++	{0x372b, 0xbd},
++	{0x372c, 0xbc},
++	{0x372e, 0x52},
++	{0x373c, 0x0e},
++	{0x373e, 0x33},
++	{0x3743, 0x10},
++	{0x3744, 0x88},
++	{0x3745, 0xc0},
++	{0x374a, 0x43},
++	{0x374c, 0x00},
++	{0x374e, 0x23},
++	{0x3751, 0x7b},
++	{0x3752, 0x84},
++	{0x3753, 0xbd},
++	{0x3754, 0xbc},
++	{0x3756, 0x52},
++	{0x375c, 0x00},
++	{0x3760, 0x00},
++	{0x3761, 0x00},
++	{0x3762, 0x00},
++	{0x3763, 0x00},
++	{0x3764, 0x00},
++	{0x3767, 0x04},
++	{0x3768, 0x04},
++	{0x3769, 0x08},
++	{0x376a, 0x08},
++	{0x376b, 0x20},
++	{0x376c, 0x00},
++	{0x376d, 0x00},
++	{0x376e, 0x00},
++	{0x3773, 0x00},
++	{0x3774, 0x51},
++	{0x3776, 0xbd},
++	{0x3777, 0xbd},
++	{0x3781, 0x18},
++	{0x3783, 0x25},
++	{0x3798, 0x1b},
++	{0x3800, 0x00},
++	{0x3801, 0x38},
++	{0x3802, 0x00},
++	{0x3803, 0x04},
++	{0x3804, 0x0a},
++	{0x3805, 0x67},
++	{0x3806, 0x05},
++	{0x3807, 0xfb},
++	{0x3808, 0x0a},
++	{0x3809, 0x20},
++	{0x380a, 0x05},
++	{0x380b, 0xf0},
++	{0x380c, 0x0A},
++	{0x380d, 0x82},//0x18
++	{0x380e, 0x06},
++	{0x380f, 0xfb},
++	{0x3810, 0x00},
++	{0x3811, 0x08},
++	{0x3812, 0x00},
++	{0x3813, 0x04},
++	{0x3814, 0x01},
++	{0x3815, 0x01},
++	{0x3819, 0x01},
++	{0x3820, 0x00},
++	{0x3821, 0x06},
++	{0x3829, 0x00},
++	{0x382a, 0x01},
++	{0x382b, 0x01},
++	{0x382d, 0x7f},
++	{0x3830, 0x04},
++	{0x3836, 0x01},
++	{0x3837, 0x00},
++	{0x3841, 0x02},
++	{0x3846, 0x08},
++	{0x3847, 0x07},
++	{0x3d85, 0x36},
++	{0x3d8c, 0x71},
++	{0x3d8d, 0xcb},
++	{0x3f0a, 0x00},
++	{0x4000, 0xf1},
++	{0x4001, 0x40},
++	{0x4002, 0x04},
++	{0x4003, 0x14},
++	{0x400e, 0x00},
++	{0x4011, 0x00},
++	{0x401a, 0x00},
++	{0x401b, 0x00},
++	{0x401c, 0x00},
++	{0x401d, 0x00},
++	{0x401f, 0x00},
++	{0x4020, 0x00},
++	{0x4021, 0x10},
++	{0x4022, 0x08},
++	{0x4023, 0xb3},
++	{0x4024, 0x09},
++	{0x4025, 0xe0},
++	{0x4026, 0x09},
++	{0x4027, 0xf0},//
++	{0x4028, 0x00},
++	{0x4029, 0x02},
++	{0x402a, 0x06},
++	{0x402b, 0x04},
++	{0x402c, 0x02},
++	{0x402d, 0x02},
++	{0x402e, 0x0e},
++	{0x402f, 0x04},
++	{0x4302, 0xff},
++	{0x4303, 0xff},
++	{0x4304, 0x00},
++	{0x4305, 0x00},
++	{0x4306, 0x00},
++	{0x4308, 0x02},
++	{0x4500, 0x6c},
++	{0x4501, 0xc4},
++	{0x4502, 0x40},
++	{0x4503, 0x01},
++	{0x4601, 0xA1},//
++	{0x4800, 0x04},
++	{0x4813, 0x08},
++	{0x481f, 0x40},
++	{0x4829, 0x78},
++	{0x4837, 0x10},
++	{0x4b00, 0x2a},
++	{0x4b0d, 0x00},
++	{0x4d00, 0x04},
++	{0x4d01, 0x42},
++	{0x4d02, 0xd1},
++	{0x4d03, 0x93},
++	{0x4d04, 0xf5},
++	{0x4d05, 0xc1},
++	{0x5000, 0xf3},
++	{0x5001, 0x11},
++	{0x5004, 0x00},
++	{0x500a, 0x00},
++	{0x500b, 0x00},
++	{0x5032, 0x00},
++	{0x5040, 0x00},
++	{0x5050, 0x0c},
++	{0x5500, 0x00},
++	{0x5501, 0x10},
++	{0x5502, 0x01},
++	{0x5503, 0x0f},
++	{0x8000, 0x00},
++	{0x8001, 0x00},
++	{0x8002, 0x00},
++	{0x8003, 0x00},
++	{0x8004, 0x00},
++	{0x8005, 0x00},
++	{0x8006, 0x00},
++	{0x8007, 0x00},
++	{0x8008, 0x00},
++	{0x3638, 0x00},
++	{0x0100, 0x00},
++	{OV4689_REG_END, 0x00},/* END MARKER */
++};
++
++/*
++ * the part of driver was fixed.
++ */
++
++static struct regval_list ov4689_stream_on_mipi[] = {
++	{0x0100, 0x01},
++	{OV4689_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list ov4689_stream_off_mipi[] = {
++	{0x0100, 0x00},
++	{OV4689_REG_END, 0x00},	/* END MARKER */
++};
++
++static int ov4689_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct ov4689_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret = 0;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ov4689_write(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char value)
++{
++	struct ov4689_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3] = {(reg>>8)&0xff, reg&0xff, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 3,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ov4689_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != OV4689_REG_END) {
++		if (vals->reg_num == OV4689_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ov4689_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++/*
++ * Write a list of register settings; ff/ff stops the process.
++ */
++static int ov4689_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != OV4689_REG_END) {
++		if (vals->reg_num == OV4689_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ov4689_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int ov4689_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov4689_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(10);
++	}
++	return 0;
++}
++
++static int ov4689_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov4689_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++	} else {
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, !info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++	}
++	return 0;
++}
++
++static int ov4689_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov4689_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = ov4689_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++
++static int ov4689_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++	ret = ov4689_read(sd, 0x300a, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != OV4689_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = ov4689_read(sd, 0x300b, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != OV4689_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	return 0;
++}
++
++
++static struct ov4689_win_size ov4689_win_sizes[] = {
++	{
++		.sensor_info.mipi_cfg.twidth		= 1920,
++		.sensor_info.mipi_cfg.theight		= 1080,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.fps			= 30 << 16 | 1,
++
++		.width		= 1920,
++		.height		= 1080,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++#ifdef CONFIG_OV4689_1080P_120FPS
++		.regs 		= ov4689_init_regs_1920_1080_120fps_mipi,
++#else
++		.regs 		= ov4689_init_regs_1920_1080_30fps_mipi,
++#endif
++	},
++	{
++		.sensor_info.mipi_cfg.twidth		= 2048,
++		.sensor_info.mipi_cfg.theight		= 1520,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.fps			= 25 << 16 | 1,
++
++		.width		= 2048,
++		.height		= 1520,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov4689_init_regs_2048_1520_30fps_mipi,
++	},
++	{
++		.sensor_info.mipi_cfg.twidth		= 2592,
++		.sensor_info.mipi_cfg.theight		= 1520,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.fps			= 25 << 16 | 1,
++
++		.width		= 2592,
++		.height		= 1520,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov4689_init_regs_2592_1520_30fps_mipi,
++	}
++};
++
++static int ov4689_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_OV4689_FMTS)
++		return -EINVAL;
++
++	code->code = ov4689_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int ov4689_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct ov4689_format_struct *ovfmt;
++	struct ov4689_win_size *wsize;
++	struct ov4689_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int ov4689_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct ov4689_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	*(unsigned int *)fmt->reserved = &info->win->sensor_info;
++
++
++//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int ov4689_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov4689_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov4689_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov4689_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int ov4689_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int ov4689_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov4689_again_lut); i++) {
++		lut = &ov4689_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov4689_again_lut); i++) {
++		lut = &ov4689_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return 0;
++}
++
++static int ov4689_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	struct ov4689_info *info = to_state(sd);
++	char v = 0;
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++
++	ret += ov4689_read(sd, 0x3509, &v);
++
++	reg_val |= v;
++	ret += ov4689_read(sd, 0x3508, &v);
++	reg_val |= v << 8;
++
++
++	*value = regval_to_again(reg_val);
++
++	return ret;
++}
++/*set analog gain db value, map value to sensor register.*/
++static int ov4689_s_again(struct v4l2_subdev *sd, int value)
++{
++	struct ov4689_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int ret = 0;
++	int i;
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(value);
++	}
++
++	ret += ov4689_write(sd, 0x3509, (unsigned char)(reg_value & 0xff));
++	ret += ov4689_write(sd, 0x3508, (unsigned char)((reg_value>>8) & 0xff));
++	if (ret < 0)
++		return ret;
++
++	return ret;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int ov4689_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov4689_s_exp(struct v4l2_subdev *sd, int value)
++{
++	struct ov4689_info *info = to_state(sd);
++	int ret = 0;
++
++	ret += ov4689_write(sd, 0x3502, ((unsigned char)(value & 0xf)) << 4);
++	ret += ov4689_write(sd, 0x3501, (unsigned char)((value >> 4) & 0xff));
++	ret += ov4689_write(sd, 0x3500, (unsigned char)((value >> 12) & 0xf));
++
++	return ret;
++}
++
++static int ov4689_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov4689_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return ov4689_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov4689_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int ov4689_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov4689_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return ov4689_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return ov4689_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return ov4689_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return ov4689_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* ov4689_s_gain turns off auto gain */
++			return ov4689_s_gain(sd, info->gain->val);
++		}
++		return ov4689_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return ov4689_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov4689_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return ov4689_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops ov4689_ctrl_ops = {
++	.s_ctrl = ov4689_s_ctrl,
++	.g_volatile_ctrl = ov4689_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ov4689_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = ov4689_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int ov4689_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	ov4689_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++static int ov4689_power(struct v4l2_subdev *sd, int on)
++{
++	struct ov4689_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	int ret;
++
++	info->supply.avdd  = devm_regulator_get_optional(&client->dev, "avdd");
++	info->supply.dvdd  = devm_regulator_get_optional(&client->dev, "dvdd");
++	info->supply.dovdd = devm_regulator_get_optional(&client->dev, "dovdd");
++
++	if (IS_ERR(info->supply.avdd)||IS_ERR(info->supply.dvdd)
++		||IS_ERR(info->supply.dovdd)) {
++			if ((PTR_ERR(info->supply.avdd) == -EPROBE_DEFER)
++				||(PTR_ERR(info->supply.avdd) == -EPROBE_DEFER)
++					||(PTR_ERR(info->supply.avdd) == -EPROBE_DEFER))
++				return -EPROBE_DEFER;
++			printk("No ov4689 vdd regulator found\n");
++	}
++
++	if ((!IS_ERR(info->supply.avdd))&&(!IS_ERR(info->supply.avdd))
++			&&(!IS_ERR(info->supply.avdd)))  {
++		if(on){
++			ret = regulator_enable(info->supply.avdd);
++			ret = regulator_enable(info->supply.dvdd);
++			ret = regulator_enable(info->supply.dovdd);
++			if (ret)
++			   dev_err(&client->dev, "ov4689 vdd supply disable failed\n");
++		}
++		else{
++			ret = regulator_disable(info->supply.avdd);
++			ret = regulator_disable(info->supply.dvdd);
++			ret = regulator_disable(info->supply.dovdd);
++			if (ret)
++			    dev_err(&client->dev, "ov4689 vdd supply disable failed\n");
++		}
++	}else{
++		dev_err(&client->dev, "ov4689 vdd supply IS_ERR failed\n");
++	}
++	return ret;
++}
++
++
++int ov4689_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct ov4689_info *info = to_state(sd);
++	int ret = 0;
++
++	if (enable) {
++		ret = ov4689_write_array(sd, ov4689_stream_on_mipi);
++		pr_debug("ov4689 stream on\n");
++
++	}
++	else {
++		ret = ov4689_write_array(sd, ov4689_stream_off_mipi);
++		pr_debug("ov4689 stream off\n");
++	}
++	return ret;
++}
++int ov4689_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct ov4689_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops ov4689_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = ov4689_g_register,
++	.s_register = ov4689_s_register,
++#endif
++};
++
++static const struct v4l2_subdev_video_ops ov4689_video_ops = {
++	.s_stream = ov4689_s_stream,
++	.g_frame_interval = ov4689_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops ov4689_pad_ops = {
++	//.enum_frame_interval = ov4689_enum_frame_interval,
++	//.num_frame_size = ov4689_enum_frame_size,
++	//.enum_mbus_code = ov4689_enum_mbus_code,
++	.set_fmt = ov4689_set_fmt,
++	.get_fmt = ov4689_get_fmt,
++};
++
++static const struct v4l2_subdev_ops ov4689_ops = {
++	.core = &ov4689_core_ops,
++	.video = &ov4689_video_ops,
++	.pad = &ov4689_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int ov4689_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_fract tpf;
++	struct v4l2_subdev *sd;
++	struct ov4689_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutp-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutp.pin = gpio;
++		info->ircutp.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutn.pin = gpio;
++		info->ircutn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	v4l2_i2c_subdev_init(sd, client, &ov4689_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++	info->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++	ov4689_power(sd,1);
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++
++	ov4689_reset(sd, 1);
++#if 1
++	/* Make sure it's an ov4689 */
++	ret = ov4689_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an ov4689 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++
++	/*IRCUT ctl 0:off 1:on*/
++	ov4689_ircut(sd, 0);
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 261773, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov4689_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1520 - 4, 1, 1000);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++#ifdef CONFIG_OV4689_2048X1520_30FPS
++	info->win = &ov4689_win_sizes[1];
++#else 
++	info->win = &ov4689_win_sizes[0];
++#endif
++
++	ov4689_init(sd, 1);
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "ov4689 Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int ov4689_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov4689_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id ov4689_id[] = {
++	{ "ov4689", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ov4689_id);
++
++static const struct of_device_id ov4689_of_match[] = {
++	{.compatible = "ovti,ov4689", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov2640_of_match);
++
++static int ov4689_suspend(struct device *dev)
++{
++        struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++        struct v4l2_subdev *sd = i2c_get_clientdata(client);
++        struct ov4689_info *info = to_state(sd);
++	int ret=0;
++
++	ov4689_power(sd,0);
++	v4l2_clk_disable(info->clk);
++        return 0;
++}
++
++static int ov4689_resume(struct device *dev)
++{
++	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov4689_info *info = to_state(sd);
++	int ret=0;
++
++	ov4689_power(sd,1);
++	v4l2_clk_enable(info->clk);
++	ov4689_reset(sd, 1);
++	ov4689_init(sd, 1);
++	return 0;
++}
++
++const struct dev_pm_ops ov4689_pm =
++{
++        .suspend = ov4689_suspend,
++        .resume  = ov4689_resume,
++};
++
++
++static struct i2c_driver ov4689_driver = {
++	.driver = {
++		.name	= "ov4689",
++		.of_match_table = of_match_ptr(ov4689_of_match),
++		.pm	=  &ov4689_pm,
++	},
++	.probe		= ov4689_probe,
++	.remove		= ov4689_remove,
++	.id_table	= ov4689_id,
++};
++
++module_i2c_driver(ov4689_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for OmniVision ov4689 sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/ov6710.c b/module_drivers/drivers/media/i2c/ingenic-isp/ov6710.c
+new file mode 100644
+index 000000000..ced0659fa
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/ov6710.c
+@@ -0,0 +1,1549 @@
++/*
++ * A V4L2 driver for OmniVision OV6710 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++
++#include <isp-sensor.h>
++
++#define OV6710_CHIP_ID_H	(0x67)
++#define OV6710_CHIP_ID_L	(0x10)
++#define OV6710_REG_END		0xffff
++#define OV6710_REG_DELAY	0xfffe
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct ov6710_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct ov6710_gpio {
++	int pin;
++	int active_level;
++};
++
++struct ov6710_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct ov6710_win_size *win;
++
++	struct ov6710_gpio reset;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++struct again_lut ov6710_again_lut[] = {
++
++	{0x0,0},
++	{0x2,2909},
++	{0x5,5731},
++	{0x7,8472},
++	{0x10,11136},
++	{0x12,13726},
++	{0x15,16248},
++	{0x17,18704},
++	{0x20,21097},
++	{0x22,23432},
++	{0x25,25710},
++	{0x27,27935},
++	{0x30,30109},
++	{0x32,32234},
++	{0x35,34312},
++	{0x37,36345},
++	{0x40,38336},
++	{0x42,40285},
++	{0x45,42195},
++	{0x47,44068},
++	{0x50,45904},
++	{0x52,47704},
++	{0x55,49472},
++	{0x57,51207},
++	{0x60,52910},
++	{0x62,54584},
++	{0x65,56228},
++	{0x67,57844},
++	{0x70,59433},
++	{0x72,60996},
++	{0x75,62534},
++	{0x77,64047},
++	{0x80,65536},
++	{0x82,67001},
++	{0x85,68445},
++	{0x87,69867},
++	{0x90,71267},
++	{0x92,72648},
++	{0x95,74008},
++	{0x97,75349},
++	{0xa0,76672},
++	{0xa2,77976},
++	{0xa5,79262},
++	{0xa7,80531},
++	{0xb0,81784},
++	{0xb2,83020},
++	{0xb5,84240},
++	{0xb7,85444},
++	{0xc0,86633},
++	{0xc2,87808},
++	{0xc5,88968},
++	{0xc7,90114},
++	{0xd0,91246},
++	{0xd2,92365},
++	{0xd5,93471},
++	{0xd7,94564},
++	{0xe0,95645},
++	{0xe2,96713},
++	{0xe5,97770},
++	{0xe7,98814},
++	{0xf0,99848},
++	{0xf2,100870},
++	{0xf5,101881},
++	{0xf7,102882},
++	{0x100,103872},
++	{0x102,104851},
++	{0x105,105821},
++	{0x107,106781},
++	{0x110,107731},
++	{0x112,108672},
++	{0x115,109604},
++	{0x117,110526},
++	{0x120,111440},
++	{0x122,112344},
++	{0x125,113240},
++	{0x127,114128},
++	{0x130,115008},
++	{0x132,115879},
++	{0x135,116743},
++	{0x137,117598},
++	{0x140,118446},
++	{0x142,119287},
++	{0x145,120120},
++	{0x147,120946},
++	{0x150,121764},
++	{0x152,122576},
++	{0x155,123380},
++	{0x157,124178},
++	{0x160,124969},
++	{0x162,125754},
++	{0x165,126532},
++	{0x167,127304},
++	{0x170,128070},
++	{0x172,128829},
++	{0x175,129583},
++	{0x177,130330},
++	{0x180,131072},
++	{0x182,131807},
++	{0x185,132537},
++	{0x187,133262},
++	{0x190,133981},
++	{0x192,134694},
++	{0x195,135403},
++	{0x197,136106},
++	{0x1a0,136803},
++	{0x1a2,137496},
++	{0x1a5,138184},
++	{0x1a7,138866},
++	{0x1b0,139544},
++	{0x1b2,140217},
++	{0x1b5,140885},
++	{0x1b7,141549},
++	{0x1c0,142208},
++	{0x1c2,142862},
++	{0x1c5,143512},
++	{0x1c7,144157},
++	{0x1d0,144798},
++	{0x1d2,145435},
++	{0x1d5,146067},
++	{0x1d7,146696},
++	{0x1e0,147320},
++	{0x1e2,147940},
++	{0x1e5,148556},
++	{0x1e7,149168},
++	{0x1f0,149776},
++	{0x1f2,150380},
++	{0x1f5,150980},
++	{0x1f7,151577},
++	{0x200,152169},
++	{0x202,152758},
++	{0x205,153344},
++	{0x207,153926},
++	{0x210,154504},
++	{0x212,155079},
++	{0x215,155650},
++	{0x217,156218},
++	{0x220,156782},
++	{0x222,157344},
++	{0x225,157901},
++	{0x227,158456},
++	{0x230,159007},
++	{0x232,159555},
++	{0x235,160100},
++	{0x237,160642},
++	{0x240,161181},
++	{0x242,161716},
++	{0x245,162249},
++	{0x247,162779},
++	{0x250,163306},
++	{0x252,163829},
++	{0x255,164350},
++	{0x257,164868},
++	{0x260,165384},
++	{0x262,165896},
++	{0x265,166406},
++	{0x267,166913},
++	{0x270,167417},
++	{0x272,167919},
++	{0x275,168418},
++	{0x277,168914},
++	{0x280,169408},
++	{0x282,169899},
++	{0x285,170387},
++	{0x287,170873},
++	{0x290,171357},
++	{0x292,171838},
++	{0x295,172317},
++	{0x297,172793},
++	{0x2a0,173267},
++	{0x2a2,173739},
++	{0x2a5,174208},
++	{0x2a7,174675},
++	{0x2b0,175140},
++	{0x2b2,175602},
++	{0x2b5,176062},
++	{0x2b7,176520},
++	{0x2c0,176976},
++	{0x2c2,177429},
++	{0x2c5,177880},
++	{0x2c7,178329},
++	{0x2d0,178776},
++	{0x2d2,179221},
++	{0x2d5,179664},
++	{0x2d7,180105},
++	{0x2e0,180544},
++	{0x2e2,180981},
++	{0x2e5,181415},
++	{0x2e7,181848},
++	{0x2f0,182279},
++	{0x2f2,182707},
++	{0x2f5,183134},
++	{0x2f7,183559},
++	{0x300,183982},
++	{0x302,184403},
++	{0x305,184823},
++	{0x307,185240},
++	{0x310,185656},
++	{0x312,186070},
++	{0x315,186482},
++	{0x317,186892},
++	{0x320,187300},
++	{0x322,187707},
++	{0x325,188112},
++	{0x327,188515},
++	{0x330,188916},
++	{0x332,189316},
++	{0x335,189714},
++	{0x337,190111},
++	{0x340,190505},
++	{0x342,190899},
++	{0x345,191290},
++	{0x347,191680},
++	{0x350,192068},
++	{0x352,192455},
++	{0x355,192840},
++	{0x357,193224},
++	{0x360,193606},
++	{0x362,193986},
++	{0x365,194365},
++	{0x367,194743},
++	{0x370,195119},
++	{0x372,195493},
++	{0x375,195866},
++	{0x377,196237},
++	{0x380,196608},
++	{0x382,196976},
++	{0x385,197343},
++	{0x387,197709},
++	{0x390,198073},
++	{0x392,198436},
++	{0x395,198798},
++	{0x397,199158},
++	{0x3a0,199517},
++	{0x3a2,199874},
++	{0x3a5,200230},
++	{0x3a7,200585},
++	{0x3b0,200939},
++	{0x3b2,201291},
++	{0x3b5,201642},
++	{0x3b7,201991},
++	{0x3c0,202339},
++	{0x3c2,202686},
++	{0x3c5,203032},
++	{0x3c7,203377},
++	{0x3d0,203720},
++	{0x3d2,204062},
++	{0x3d5,204402},
++	{0x3d7,204742},
++	{0x3e0,205080},
++	{0x3e2,205417},
++	{0x3e5,205753},
++	{0x3e7,206088},
++	{0x3f0,206421},
++	{0x3f2,206754},
++	{0x3f5,207085},
++	{0x3f7,207415},
++};
++
++static inline struct ov6710_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct ov6710_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct ov6710_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++static struct regval_list ov6710_init_regs_400_400_120fps_mipi[] = {
++	{0x0103, 0x01},
++	{0x0100, 0x00},
++	{0x3005, 0x00},
++	{0x3013, 0x12},
++	{0x3014, 0x04},
++	{0x3016, 0x10},
++	{0x3017, 0x00},
++	{0x3018, 0x00},
++	{0x301a, 0x00},
++	{0x301b, 0x00},
++	{0x301c, 0x00},
++	{0x3037, 0xf0},
++	{0x3080, 0x01},
++	{0x3081, 0x00},
++	{0x3082, 0x01},
++	{0x3098, 0x04},
++	{0x3099, 0x28},
++	{0x309a, 0x06},
++	{0x309b, 0x04},
++	{0x309c, 0x00},
++	{0x309d, 0x00},
++	{0x309e, 0x01},
++	{0x309f, 0x00},
++	{0x30b0, 0x0a},
++	{0x30b1, 0x02},
++	{0x30b2, 0x00},
++	{0x30b3, 0x32},
++	{0x30b4, 0x02},
++	{0x30b5, 0x05},
++	{0x3106, 0xd9},
++	{0x3500, 0x00},
++	{0x3501, 0x73},
++	{0x3502, 0x20},
++	{0x3503, 0x07},
++	{0x3509, 0x10},
++	{0x350a, 0x00},
++	{0x350b, 0x10},
++	{0x3600, 0xfc},
++	{0x3620, 0xb7},
++	{0x3621, 0x05},
++	{0x3626, 0x31},
++	{0x3627, 0x40},
++	{0x3632, 0xa3},
++	{0x3633, 0x34},
++	{0x3634, 0x40},
++	{0x3636, 0x00},
++	{0x3660, 0x80},
++	{0x3662, 0x01},
++	{0x3664, 0xf0},
++	{0x366a, 0x10},
++	{0x366b, 0x06},
++	{0x3680, 0xf4},
++	{0x3681, 0x50},
++	{0x3682, 0x00},
++	{0x3708, 0x20},
++	{0x3709, 0x40},
++	{0x370d, 0x03},
++	{0x373b, 0x02},
++	{0x373c, 0x08},
++	{0x3742, 0x00},
++	{0x3744, 0x16},
++	{0x3745, 0x08},
++	{0x3781, 0xfc},
++	{0x3788, 0x00},
++	{0x3800, 0x00},
++	{0x3801, 0x04},
++	{0x3802, 0x00},
++	{0x3803, 0x04},
++	{0x3804, 0x01},
++	{0x3805, 0x9b},
++	{0x3806, 0x01},
++	{0x3807, 0x9b},
++	{0x3808, 0x01},
++	{0x3809, 0x90},
++	{0x380a, 0x01},
++	{0x380b, 0x90},
++	{0x380c, 0x05},
++	{0x380d, 0xf2},
++	{0x380e, 0x08},
++	{0x380f, 0x36},
++	{0x3810, 0x00},
++	{0x3811, 0x04},
++	{0x3812, 0x00},
++	{0x3813, 0x04},
++	{0x3814, 0x11},
++	{0x3815, 0x11},
++	{0x3820, 0x00},
++	{0x3821, 0x00},
++	{0x382b, 0xfa},
++	{0x382f, 0x04},
++	{0x3832, 0x00},
++	{0x3833, 0x05},
++	{0x3834, 0x00},
++	{0x3835, 0x05},
++	{0x3882, 0x04},
++	{0x3883, 0x00},
++	{0x38a4, 0x10},
++	{0x38a5, 0x00},
++	{0x38b1, 0x03},
++	{0x3b80, 0x00},
++	{0x3b81, 0xa5},
++	{0x3b82, 0x10},
++	{0x3b83, 0x00},
++	{0x3b84, 0x08},
++	{0x3b85, 0x00},
++	{0x3b86, 0x01},
++	{0x3b87, 0x00},
++	{0x3b88, 0x00},
++	{0x3b89, 0x00},
++	{0x3b8a, 0x00},
++	{0x3b8b, 0x05},
++	{0x3b8c, 0x00},
++	{0x3b8d, 0x00},
++	{0x3b8e, 0x00},
++	{0x3b8f, 0x1a},
++	{0x3b94, 0x05},
++	{0x3b95, 0xf2},
++	{0x3b96, 0xf0},
++	{0x4004, 0x04},
++	{0x404e, 0x01},
++	{0x4801, 0x0f},
++	{0x4806, 0x0f},
++	{0x4837, 0x43},
++	{0x5a01, 0x00},
++	{0x5a03, 0x00},
++	{0x5a04, 0x10},
++	{0x5a05, 0xa0},
++	{0x5a06, 0x0c},
++	{0x5a07, 0x78},
++	{0x5a08, 0x00},
++//	{0x0100, 0x01},
++	{OV6710_REG_END, 0x00},/* END MARKER */
++};
++
++static struct regval_list ov6710_init_regs_200_200_120fps_mipi_bin[] = {
++	{0x0103, 0x01},
++	{0x0100, 0x00},
++	{0x3005, 0x00},
++	{0x3013, 0x12},
++	{0x3014, 0x04},
++	{0x3016, 0x10},
++	{0x3017, 0x00},
++	{0x3018, 0x00},
++	{0x301a, 0x00},
++	{0x301b, 0x00},
++	{0x301c, 0x00},
++	{0x3037, 0xf0},
++	{0x3080, 0x01},
++	{0x3081, 0x00},
++	{0x3082, 0x01},
++	{0x3098, 0x04},
++	{0x3099, 0x14},
++	{0x309a, 0x06},
++	{0x309b, 0x02},
++	{0x309c, 0x00},
++	{0x309d, 0x00},
++	{0x309e, 0x01},
++	{0x309f, 0x00},
++	{0x30b0, 0x0a},
++	{0x30b1, 0x04},
++	{0x30b2, 0x00},
++	{0x30b3, 0x32},
++	{0x30b4, 0x02},
++	{0x30b5, 0x05},
++	{0x3106, 0xd9},
++	{0x3500, 0x00},
++	{0x3501, 0x0e},
++	{0x3502, 0x80},
++	{0x3503, 0x07},
++	{0x3509, 0x10},
++	{0x350b, 0x10},
++	{0x3620, 0xb7},
++	{0x3621, 0x05},
++	{0x3626, 0x31},
++	{0x3627, 0x40},
++	{0x3632, 0xa3},
++	{0x3633, 0x34},
++	{0x3634, 0x40},
++	{0x3636, 0x00},
++	{0x3660, 0x80},
++	{0x3662, 0x01},
++	{0x3664, 0xf0},
++	{0x366a, 0x00},
++	{0x366b, 0x50},
++	{0x3680, 0xf4},
++	{0x3681, 0x50},
++	{0x3682, 0x00},
++	{0x3708, 0x20},
++	{0x3709, 0x40},
++	{0x370d, 0x03},
++	{0x373b, 0x02},
++	{0x373c, 0xe8},
++	{0x3742, 0x00},
++	{0x3744, 0x16},
++	{0x3745, 0x08},
++	{0x3781, 0xfc},
++	{0x3788, 0x00},
++	{0x3800, 0x00},
++	{0x3801, 0x00},
++	{0x3802, 0x00},
++	{0x3803, 0x00},
++	{0x3804, 0x01},
++	{0x3805, 0x9f},
++	{0x3806, 0x01},
++	{0x3807, 0x9f},
++	{0x3808, 0x00},
++	{0x3809, 0xc8},
++	{0x380a, 0x00},
++	{0x380b, 0xc8},
++	{0x380c, 0x05},
++	{0x380d, 0x78},
++	{0x380e, 0x00},
++	{0x380f, 0xee},
++	{0x3810, 0x00},
++	{0x3811, 0x04},
++	{0x3812, 0x00},
++	{0x3813, 0x04},
++	{0x3814, 0x31},
++	{0x3815, 0x31},
++	{0x3820, 0x02},
++	{0x3821, 0x01},
++	{0x382b, 0xfa},
++	{0x382f, 0x04},
++	{0x3832, 0x00},
++	{0x3833, 0x05},
++	{0x3834, 0x00},
++	{0x3835, 0x05},
++	{0x3882, 0x04},
++	{0x3883, 0x00},
++	{0x38a4, 0x10},
++	{0x38a5, 0x00},
++	{0x38b1, 0x03},
++	{0x3b80, 0x00},
++	{0x3b81, 0xa5},
++	{0x3b82, 0x10},
++	{0x3b83, 0x00},
++	{0x3b84, 0x08},
++	{0x3b85, 0x00},
++	{0x3b86, 0x01},
++	{0x3b87, 0x00},
++	{0x3b88, 0x00},
++	{0x3b89, 0x00},
++	{0x3b8a, 0x00},
++	{0x3b8b, 0x05},
++	{0x3b8c, 0x00},
++	{0x3b8d, 0x00},
++	{0x3b8e, 0x00},
++	{0x3b8f, 0x1a},
++	{0x3b94, 0x05},
++	{0x3b95, 0xf2},
++	{0x3b96, 0xf0},
++	{0x4004, 0x02},
++	{0x404e, 0x01},
++	{0x4801, 0x0f},
++	{0x4806, 0x0f},
++	{0x4837, 0x85},
++	{0x0100, 0x01},
++	{OV6710_REG_END, 0x00},/* END MARKER */
++};
++
++static struct regval_list ov6710_init_regs_200_200_120fps_mipi_skip[] = {
++	{0x0103, 0x01},
++	{0x0100, 0x00},
++	{0x3005, 0x00},
++	{0x3013, 0x12},
++	{0x3014, 0x04},
++	{0x3016, 0x10},
++	{0x3017, 0x00},
++	{0x3018, 0x00},
++	{0x301a, 0x00},
++	{0x301b, 0x00},
++	{0x301c, 0x00},
++	{0x3037, 0xf0},
++	{0x3080, 0x01},
++	{0x3081, 0x00},
++	{0x3082, 0x01},
++	{0x3098, 0x04},
++	{0x3099, 0x14},
++	{0x309a, 0x06},
++	{0x309b, 0x02},
++	{0x309c, 0x00},
++	{0x309d, 0x00},
++	{0x309e, 0x01},
++	{0x309f, 0x00},
++	{0x30b0, 0x0a},
++	{0x30b1, 0x04},
++	{0x30b2, 0x00},
++	{0x30b3, 0x32},
++	{0x30b4, 0x02},
++	{0x30b5, 0x05},
++	{0x3106, 0xd9},
++	{0x3500, 0x00},
++	{0x3501, 0x0e},
++	{0x3502, 0x80},
++	{0x3503, 0x07},
++	{0x3509, 0x10},
++	{0x350b, 0x10},
++	{0x3620, 0xb7},
++	{0x3621, 0x05},
++	{0x3626, 0x31},
++	{0x3627, 0x40},
++	{0x3632, 0xa3},
++	{0x3633, 0x34},
++	{0x3634, 0x40},
++	{0x3636, 0x00},
++	{0x3660, 0x80},
++	{0x3662, 0x01},
++	{0x3664, 0xf0},
++	{0x366a, 0x00},
++	{0x366b, 0x50},
++	{0x3680, 0xf4},
++	{0x3681, 0x50},
++	{0x3682, 0x00},
++	{0x3708, 0x20},
++	{0x3709, 0x40},
++	{0x370d, 0x03},
++	{0x373b, 0x02},
++	{0x373c, 0x08},
++	{0x3742, 0xe0},
++	{0x3744, 0x16},
++	{0x3745, 0x08},
++	{0x3781, 0xfc},
++	{0x3788, 0x21},
++	{0x3800, 0x00},
++	{0x3801, 0x00},
++	{0x3802, 0x00},
++	{0x3803, 0x00},
++	{0x3804, 0x01},
++	{0x3805, 0x9f},
++	{0x3806, 0x01},
++	{0x3807, 0x9f},
++	{0x3808, 0x00},
++	{0x3809, 0xc8},
++	{0x380a, 0x00},
++	{0x380b, 0xc8},
++	{0x380c, 0x05},
++	{0x380d, 0x78},
++	{0x380e, 0x00},
++	{0x380f, 0xee},
++	{0x3810, 0x00},
++	{0x3811, 0x04},
++	{0x3812, 0x00},
++	{0x3813, 0x04},
++	{0x3814, 0x31},
++	{0x3815, 0x22},
++	{0x3820, 0x00},
++	{0x3821, 0x00},
++	{0x382b, 0xfa},
++	{0x382f, 0x04},
++	{0x3832, 0x00},
++	{0x3833, 0x05},
++	{0x3834, 0x00},
++	{0x3835, 0x05},
++	{0x3882, 0x04},
++	{0x3883, 0x00},
++	{0x38a4, 0x10},
++	{0x38a5, 0x00},
++	{0x38b1, 0x03},
++	{0x3b80, 0x00},
++	{0x3b81, 0xa5},
++	{0x3b82, 0x10},
++	{0x3b83, 0x00},
++	{0x3b84, 0x08},
++	{0x3b85, 0x00},
++	{0x3b86, 0x01},
++	{0x3b87, 0x00},
++	{0x3b88, 0x00},
++	{0x3b89, 0x00},
++	{0x3b8a, 0x00},
++	{0x3b8b, 0x05},
++	{0x3b8c, 0x00},
++	{0x3b8d, 0x00},
++	{0x3b8e, 0x00},
++	{0x3b8f, 0x1a},
++	{0x3b94, 0x05},
++	{0x3b95, 0xf2},
++	{0x3b96, 0xf0},
++	{0x4004, 0x02},
++	{0x404e, 0x01},
++	{0x4801, 0x0f},
++	{0x4806, 0x0f},
++	{0x4837, 0x53},
++	{0x0100, 0x01},
++	{OV6710_REG_END, 0x00},/* END MARKER */
++};
++
++static struct regval_list ov6710_init_regs_100_100_120fps_mipi[] = {
++	{0x0103, 0x01},
++	{0x0100, 0x00},
++	{0x3005, 0x00},
++	{0x3013, 0x12},
++	{0x3014, 0x04},
++	{0x3016, 0x10},
++	{0x3017, 0x00},
++	{0x3018, 0x00},
++	{0x301a, 0x00},
++	{0x301b, 0x00},
++	{0x301c, 0x00},
++	{0x3037, 0xf0},
++	{0x3080, 0x01},
++	{0x3081, 0x00},
++	{0x3082, 0x01},
++	{0x3098, 0x04},
++	{0x3099, 0x14},
++	{0x309a, 0x08},
++	{0x309b, 0x02},
++	{0x309c, 0x00},
++	{0x309d, 0x00},
++	{0x309e, 0x01},
++	{0x309f, 0x00},
++	{0x30b0, 0x0a},
++	{0x30b1, 0x06},
++	{0x30b2, 0x00},
++	{0x30b3, 0x32},
++	{0x30b4, 0x02},
++	{0x30b5, 0x05},
++	{0x3106, 0xd9},
++	{0x3500, 0x00},
++	{0x3501, 0x07},
++	{0x3502, 0x80},
++	{0x3503, 0x07},
++	{0x3509, 0x10},
++	{0x350b, 0x10},
++	{0x3620, 0xb7},
++	{0x3621, 0x05},
++	{0x3626, 0x31},
++	{0x3627, 0x40},
++	{0x3632, 0xa3},
++	{0x3633, 0x34},
++	{0x3634, 0x40},
++	{0x3636, 0x00},
++	{0x3660, 0x80},
++	{0x3662, 0x01},
++	{0x3664, 0xf0},
++	{0x366a, 0x00},
++	{0x366b, 0x50},
++	{0x3680, 0xf4},
++	{0x3681, 0x50},
++	{0x3682, 0x00},
++	{0x3708, 0x20},
++	{0x3709, 0x40},
++	{0x370d, 0x03},
++	{0x373b, 0x02},
++	{0x373c, 0x08},
++	{0x3742, 0xe0},
++	{0x3744, 0x16},
++	{0x3745, 0x08},
++	{0x3781, 0xfc},
++	{0x3788, 0x61},
++	{0x3800, 0x00},
++	{0x3801, 0x00},
++	{0x3802, 0x00},
++	{0x3803, 0x00},
++	{0x3804, 0x01},
++	{0x3805, 0x9f},
++	{0x3806, 0x01},
++	{0x3807, 0x9f},
++	{0x3808, 0x00},
++	{0x3809, 0x64},
++	{0x380a, 0x00},
++	{0x380b, 0x64},
++	{0x380c, 0x05},
++	{0x380d, 0x00},
++	{0x380e, 0x00},
++	{0x380f, 0xc4},
++	{0x3810, 0x00},
++	{0x3811, 0x02},
++	{0x3812, 0x00},
++	{0x3813, 0x02},
++	{0x3814, 0x71},
++	{0x3815, 0x44},
++	{0x3820, 0x00},
++	{0x3821, 0x01},
++	{0x382b, 0xfa},
++	{0x382f, 0x04},
++	{0x3832, 0x00},
++	{0x3833, 0x05},
++	{0x3834, 0x00},
++	{0x3835, 0x05},
++	{0x3882, 0x04},
++	{0x3883, 0x00},
++	{0x38a4, 0x10},
++	{0x38a5, 0x00},
++	{0x38b1, 0x03},
++	{0x3b80, 0x00},
++	{0x3b81, 0xa5},
++	{0x3b82, 0x10},
++	{0x3b83, 0x00},
++	{0x3b84, 0x08},
++	{0x3b85, 0x00},
++	{0x3b86, 0x01},
++	{0x3b87, 0x00},
++	{0x3b88, 0x00},
++	{0x3b89, 0x00},
++	{0x3b8a, 0x00},
++	{0x3b8b, 0x05},
++	{0x3b8c, 0x00},
++	{0x3b8d, 0x00},
++	{0x3b8e, 0x00},
++	{0x3b8f, 0x1a},
++	{0x3b94, 0x05},
++	{0x3b95, 0xf2},
++	{0x3b96, 0xf0},
++	{0x4004, 0x02},
++	{0x404e, 0x01},
++	{0x4801, 0x0f},
++	{0x4806, 0x0f},
++	{0x4837, 0xc8},
++	{0x0100, 0x01},
++	{OV6710_REG_END, 0x00},/* END MARKER */
++};
++
++static struct regval_list ov6710_stream_on_mipi[] = {
++	{0x0100, 0x01},
++	{OV6710_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list ov6710_stream_off_mipi[] = {
++	{0x0100, 0x00},
++	{OV6710_REG_END, 0x00},	/* END MARKER */
++};
++
++static int ov6710_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct ov6710_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret = 0;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ov6710_write(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char value)
++{
++	struct ov6710_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3] = {(reg>>8)&0xff, reg&0xff, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 3,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ov6710_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != OV6710_REG_END) {
++		if (vals->reg_num == OV6710_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ov6710_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++/*
++ * Write a list of register settings; ff/ff stops the process.
++ */
++static int ov6710_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != OV6710_REG_END) {
++		if (vals->reg_num == OV6710_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ov6710_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int ov6710_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov6710_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(10);
++	}
++	return 0;
++}
++
++
++static int ov6710_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov6710_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = ov6710_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++
++static int ov6710_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++	ret = ov6710_read(sd, 0x300a, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != OV6710_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = ov6710_read(sd, 0x300b, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != OV6710_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	return 0;
++}
++
++
++static struct ov6710_win_size ov6710_win_sizes[] = {
++	{
++
++		.sensor_info.mipi_cfg.twidth		= 400,
++		.sensor_info.mipi_cfg.theight		= 400,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.fps			= 120 << 16 | 1,
++
++
++		.width		= 400,
++		.height		= 400,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov6710_init_regs_400_400_120fps_mipi,
++	},
++	{
++		.sensor_info.mipi_cfg.twidth		= 200,
++		.sensor_info.mipi_cfg.theight		= 200,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.fps			= 120 << 16 | 1,
++
++		.width		= 200,
++		.height		= 200,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov6710_init_regs_200_200_120fps_mipi_skip,
++	},
++	{
++		.sensor_info.mipi_cfg.twidth		= 100,
++		.sensor_info.mipi_cfg.theight		= 100,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.fps			= 120 << 16 | 1,
++
++		.width		= 100,
++		.height		= 100,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov6710_init_regs_100_100_120fps_mipi,
++	},
++};
++
++static int ov6710_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_OV6710_FMTS)
++		return -EINVAL;
++
++	code->code = ov6710_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int ov6710_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct ov6710_format_struct *ovfmt;
++	struct ov6710_win_size *wsize;
++	struct ov6710_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int ov6710_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct ov6710_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	*(unsigned int *)fmt->reserved = &info->win->sensor_info;
++
++
++//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int ov6710_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov6710_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov6710_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov6710_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int ov6710_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int ov6710_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov6710_again_lut); i++) {
++		lut = &ov6710_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov6710_again_lut); i++) {
++		lut = &ov6710_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return 0;
++}
++
++static int ov6710_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	struct ov6710_info *info = to_state(sd);
++	char v = 0;
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++
++	ret += ov6710_read(sd, 0x350a, &v);
++
++	reg_val |= v;
++	ret += ov6710_read(sd, 0x350b, &v);
++	reg_val |= v << 8;
++
++
++	*value = regval_to_again(reg_val);
++
++	return ret;
++}
++/*set analog gain db value, map value to sensor register.*/
++static int ov6710_s_again(struct v4l2_subdev *sd, int value)
++{
++	struct ov6710_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int ret = 0;
++	int i;
++
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(value);
++	}
++
++	ret += ov6710_write(sd, 0x350a, (unsigned char)((reg_value>>8) & 0x3));
++	ret += ov6710_write(sd, 0x350b, (unsigned char)(reg_value & 0xff));
++
++	return ret;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int ov6710_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov6710_s_exp(struct v4l2_subdev *sd, int value)
++{
++	struct ov6710_info *info = to_state(sd);
++	int ret = 0;
++	unsigned char v;
++	int frame_length = 0;
++
++	ret = ov6710_read(sd, 0x380e, &v);
++	frame_length = v << 8;
++
++	ret += ov6710_read(sd, 0x380f, &v);
++	frame_length |= v;
++
++	if(value < frame_length){
++		ret += ov6710_write(sd, 0x3502, ((unsigned char)(value & 0xf)) << 4);
++		ret += ov6710_write(sd, 0x3501, (unsigned char)((value >> 4) & 0xff));
++		ret += ov6710_write(sd, 0x3500, (unsigned char)((value >> 12) & 0xf));
++	}
++	return ret;
++}
++
++static int ov6710_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov6710_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return ov6710_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov6710_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int ov6710_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov6710_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return ov6710_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return ov6710_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return ov6710_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return ov6710_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* ov6710_s_gain turns off auto gain */
++			return ov6710_s_gain(sd, info->gain->val);
++		}
++		return ov6710_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return ov6710_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov6710_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return ov6710_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops ov6710_ctrl_ops = {
++	.s_ctrl = ov6710_s_ctrl,
++	.g_volatile_ctrl = ov6710_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ov6710_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = ov6710_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int ov6710_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	ov6710_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int ov6710_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct ov6710_info *info = to_state(sd);
++	int ret = 0;
++
++	if (enable) {
++		ov6710_write_array(sd, info->win->regs);
++		ov6710_s_again(sd, 100000);
++		ret = ov6710_write_array(sd, ov6710_stream_on_mipi);
++		pr_debug("ov6710 stream on\n");
++
++	}
++	else {
++		ret = ov6710_write_array(sd, ov6710_stream_off_mipi);
++		pr_debug("ov6710 stream off\n");
++	}
++	return ret;
++}
++
++int ov6710_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct ov6710_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops ov6710_core_ops = {
++	//.reset = ov6710_reset,
++	.init = ov6710_init,
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = ov6710_g_register,
++	.s_register = ov6710_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops ov6710_video_ops = {
++	.s_stream = ov6710_s_stream,
++	.g_frame_interval = ov6710_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops ov6710_pad_ops = {
++	//.enum_frame_interval = ov6710_enum_frame_interval,
++	//.num_frame_size = ov6710_enum_frame_size,
++	//.enum_mbus_code = ov6710_enum_mbus_code,
++	.set_fmt = ov6710_set_fmt,
++	.get_fmt = ov6710_get_fmt,
++};
++
++static const struct v4l2_subdev_ops ov6710_ops = {
++	.core = &ov6710_core_ops,
++	.video = &ov6710_video_ops,
++	.pad = &ov6710_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int ov6710_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_fract tpf;
++	struct v4l2_subdev *sd;
++	struct ov6710_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++    unsigned int iovcc_1v8;
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	iovcc_1v8 = of_property_read_bool(client->dev.of_node, "ingenic,iovcc_1v8");
++	if(iovcc_1v8) {
++		/*X2000 spec*/
++		*(volatile unsigned int *)0xb00000e0 |= (1<<30);
++	}
++	v4l2_i2c_subdev_init(sd, client, &ov6710_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++	info->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++
++	ov6710_reset(sd, 1);
++#if 1
++	/* Make sure it's an ov6710 */
++	ret = ov6710_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an ov6710 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &ov6710_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &ov6710_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &ov6710_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &ov6710_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &ov6710_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &ov6710_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 261773, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov6710_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1520 - 4, 1, 1000);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->win = &ov6710_win_sizes[0];
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "ov6710 Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int ov6710_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov6710_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id ov6710_id[] = {
++	{ "ov6710", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ov6710_id);
++
++static const struct of_device_id ov6710_of_match[] = {
++	{.compatible = "ovti,ov6710", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov2640_of_match);
++
++
++static struct i2c_driver ov6710_driver = {
++	.driver = {
++		.name	= "ov6710",
++		.of_match_table = of_match_ptr(ov6710_of_match),
++	},
++	.probe		= ov6710_probe,
++	.remove		= ov6710_remove,
++	.id_table	= ov6710_id,
++};
++
++module_i2c_driver(ov6710_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for OmniVision ov6710 sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/ov7251.c b/module_drivers/drivers/media/i2c/ingenic-isp/ov7251.c
+new file mode 100644
+index 000000000..4318853c5
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/ov7251.c
+@@ -0,0 +1,1396 @@
++/*
++ * A V4L2 driver for OmniVision OV7251 cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++
++#include <isp-sensor.h>
++
++#define OV7251_CHIP_ID_H	(0x77)
++#define OV7251_CHIP_ID_L	(0x50)
++#define OV7251_REG_END		0xffff
++#define OV7251_REG_DELAY	0xfffe
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct ov7251_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct ov7251_gpio {
++	int pin;
++	int active_level;
++};
++
++struct ov7251_supply {
++	struct regulator *vdd2v8;	/* Digital Core supply */
++	struct regulator *vdd1v8;		/* Digital I/O supply */
++};
++
++struct ov7251_info {
++	struct ov7251_supply supply;
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct ov7251_win_size *win;
++
++	struct ov7251_gpio reset;
++	struct ov7251_gpio ircutp;
++	struct ov7251_gpio ircutn;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++struct again_lut ov7251_again_lut[] = {
++
++	{0x80, 0},
++	{0x88, 5731},
++	{0x90, 11136},
++	{0x98, 16248},
++	{0xa0, 21097},
++	{0xa8, 25710},
++	{0xb0, 30109},
++	{0xb8, 34312},
++	{0xc0, 38336},
++	{0xc8, 42195},
++	{0xd0, 45904},
++	{0xd8, 49472},
++	{0xe0, 52910},
++	{0xe8, 56228},
++	{0xf0, 59433},
++	{0xf8, 62534},
++	{0x178, 65536},
++	{0x17c, 68445},
++	{0x180, 71267},
++	{0x184, 74008},
++	{0x188, 76672},
++	{0x18c, 79262},
++	{0x190, 81784},
++	{0x194, 84240},
++	{0x198, 86633},
++	{0x19c, 88968},
++	{0x1a0, 91246},
++	{0x1a4, 93471},
++	{0x1a8, 95645},
++	{0x1ac, 97770},
++	{0x1b0, 99848},
++	{0x1b4, 101881},
++	{0x1b8, 103872},
++	{0x1bc, 105821},
++	{0x1c0, 107731},
++	{0x1c4, 109604},
++	{0x1c8, 111440},
++	{0x1cc, 113241},
++	{0x1d0, 115008},
++	{0x1d4, 116743},
++	{0x1d8, 118446},
++	{0x1dc, 120120},
++	{0x1e0, 121764},
++	{0x1e4, 123380},
++	{0x1e8, 124969},
++	{0x1ec, 126532},
++	{0x1f0, 128070},
++	{0x1f4, 129583},
++	{0x374, 131072},
++	{0x376, 132537},
++	{0x378, 133981},
++	{0x37a, 135403},
++	{0x37c, 136803},
++	{0x37e, 138184},
++	{0x380, 139544},
++	{0x382, 140885},
++	{0x384, 142208},
++	{0x386, 143512},
++	{0x388, 144798},
++	{0x38a, 146067},
++	{0x38c, 147320},
++	{0x38e, 148556},
++	{0x390, 149776},
++	{0x392, 150980},
++	{0x394, 152169},
++	{0x396, 153344},
++	{0x398, 154504},
++	{0x39a, 155650},
++	{0x39c, 156782},
++	{0x39e, 157901},
++	{0x3a0, 159007},
++	{0x3a2, 160100},
++	{0x3a4, 161181},
++	{0x3a6, 162249},
++	{0x3a8, 163306},
++	{0x3aa, 164350},
++	{0x3ac, 165384},
++	{0x3ae, 166406},
++	{0x3b0, 167417},
++	{0x3b2, 168418},
++	{0x3b4, 169408},
++	{0x3b6, 170387},
++	{0x3b8, 171357},
++	{0x3ba, 172317},
++	{0x3bc, 173267},
++	{0x3be, 174208},
++	{0x3c0, 175140},
++	{0x3c2, 176062},
++	{0x3c4, 176976},
++	{0x3c6, 177880},
++	{0x3c8, 178777},
++	{0x3ca, 179664},
++	{0x3cc, 180544},
++	{0x3ce, 181415},
++	{0x3d0, 182279},
++	{0x3d2, 183134},
++	{0x3d4, 183982},
++	{0x3d6, 184823},
++	{0x3d8, 185656},
++	{0x3da, 186482},
++	{0x3dc, 187300},
++	{0x3de, 188112},
++	{0x3e0, 188916},
++	{0x3e2, 189714},
++	{0x3e4, 190505},
++	{0x3e6, 191290},
++	{0x3e8, 192068},
++	{0x3ea, 192840},
++	{0x3ec, 193606},
++	{0x3ee, 194365},
++	{0x3f0, 195119},
++	{0x3f2, 195866},
++	{0x778, 196608},
++	{0x779, 197343},
++	{0x77a, 198073},
++	{0x77b, 198798},
++	{0x77c, 199517},
++	{0x77d, 200230},
++	{0x77e, 200939},
++	{0x77f, 201642},
++	{0x780, 202339},
++	{0x781, 203032},
++	{0x782, 203720},
++	{0x783, 204402},
++	{0x784, 205080},
++	{0x785, 205753},
++	{0x786, 206421},
++	{0x787, 207085},
++	{0x788, 207744},
++	{0x789, 208398},
++	{0x78a, 209048},
++	{0x78b, 209693},
++	{0x78c, 210334},
++	{0x78d, 210971},
++	{0x78e, 211603},
++	{0x78f, 212232},
++	{0x790, 212856},
++	{0x791, 213476},
++	{0x792, 214092},
++	{0x793, 214704},
++	{0x794, 215312},
++	{0x795, 215916},
++	{0x796, 216516},
++	{0x797, 217113},
++	{0x798, 217705},
++	{0x799, 218294},
++	{0x79a, 218880},
++	{0x79b, 219462},
++	{0x79c, 220040},
++	{0x79d, 220615},
++	{0x79e, 221186},
++	{0x79f, 221754},
++	{0x7a0, 222318},
++	{0x7a1, 222880},
++	{0x7a2, 223437},
++	{0x7a3, 223992},
++	{0x7a4, 224543},
++	{0x7a5, 225091},
++	{0x7a6, 225636},
++	{0x7a7, 226178},
++	{0x7a8, 226717},
++	{0x7a9, 227253},
++	{0x7aa, 227785},
++	{0x7ab, 228315},
++	{0x7ac, 228842},
++	{0x7ad, 229365},
++	{0x7ae, 229886},
++	{0x7af, 230404},
++	{0x7b0, 230920},
++	{0x7b1, 231432},
++	{0x7b2, 231942},
++	{0x7b3, 232449},
++	{0x7b4, 232953},
++	{0x7b5, 233455},
++	{0x7b6, 233954},
++	{0x7b7, 234450},
++	{0x7b8, 234944},
++	{0x7b9, 235435},
++	{0x7ba, 235923},
++	{0x7bb, 236410},
++	{0x7bc, 236893},
++	{0x7bd, 237374},
++	{0x7be, 237853},
++	{0x7bf, 238329},
++	{0x7c0, 238803},
++	{0x7c1, 239275},
++	{0x7c2, 239744},
++	{0x7c3, 240211},
++	{0x7c4, 240676},
++	{0x7c5, 241138},
++	{0x7c6, 241598},
++	{0x7c7, 242056},
++	{0x7c8, 242512},
++	{0x7c9, 242965},
++	{0x7ca, 243416},
++	{0x7cb, 243865},
++	{0x7cc, 244313},
++	{0x7cd, 244757},
++	{0x7ce, 245200},
++	{0x7cf, 245641},
++	{0x7d0, 246080},
++	{0x7d1, 246517},
++	{0x7d2, 246951},
++	{0x7d3, 247384},
++	{0x7d4, 247815},
++	{0x7d5, 248243},
++	{0x7d6, 248670},
++	{0x7d7, 249095},
++	{0x7d8, 249518},
++	{0x7d9, 249939},
++	{0x7da, 250359},
++	{0x7db, 250776},
++	{0x7dc, 251192},
++	{0x7dd, 251606},
++	{0x7de, 252018},
++	{0x7df, 252428},
++	{0x7e0, 252836},
++	{0x7e1, 253243},
++	{0x7e2, 253648},
++	{0x7e3, 254051},
++	{0x7e4, 254452},
++	{0x7e5, 254852},
++	{0x7e6, 255250},
++	{0x7e7, 255647},
++	{0x7e8, 256041},
++	{0x7e9, 256435},
++	{0x7ea, 256826},
++	{0x7eb, 257216},
++	{0x7ec, 257604},
++	{0x7ed, 257991},
++	{0x7ee, 258376},
++	{0x7ef, 258760},
++	{0x7f0, 259142},
++	{0x7f1, 259522},
++	{0x7f2, 259901},
++	{0x7f3, 260279},
++	{0x7f4, 260655},
++	{0x7f5, 261029},
++	{0x7f6, 261402},
++	{0x7f7, 261773},
++};
++
++static inline struct ov7251_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct ov7251_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct ov7251_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++
++
++static struct regval_list ov7251_init_regs_640_480_mipi[] = {
++	{0x3501, 0x00},
++	{0x3502, 0x80},
++	{0x3674, 0xef}, 
++	{0x373c, 0x8e},
++	{0x37a8, 0x01},
++	{0x37a9, 0xc0},
++	{0x3803, 0x04},
++	{0x3807, 0xeb},
++	{0x3808, 0x02},
++	{0x3809, 0x80},
++	{0x380a, 0x01},
++	{0x380b, 0xe0},
++	{0x380c, 0x05},
++	{0x380d, 0x70},
++	{0x380e, 0x02},
++	{0x380f, 0x40},
++	{0x3813, 0x05}, 
++	{0x3814, 0x11},
++	{0x3815, 0x11},
++	{0x3820, 0x40},
++	{0x3821, 0x00},
++	{0x3c0c, 0x01},
++	{0x3c0d, 0xd0},
++	{0x3c0e, 0x02},
++	{0x3c0f, 0x0a},
++	{0x4001, 0x42},
++	{0x4004, 0x04},
++	{0x0100, 0x01},
++	{OV7251_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list ov7251_init_regs_320_240_mipi[] = {
++	{0x3501, 0x00},
++	{0x3502, 0x90},
++	{0x3674, 0xef},
++	{0x373c, 0xe8},
++	{0x37a8, 0x02},
++	{0x37a9, 0x14},
++	{0x3803, 0x00},
++	{0x3807, 0xef},
++	{0x3808, 0x01},
++	{0x3809, 0x40},
++	{0x380a, 0x00},
++	{0x380b, 0xf0},
++	{0x380c, 0x05},
++	{0x380d, 0x70},
++	{0x380e, 0x02},
++	{0x380f, 0x40},
++	{0x3813, 0x05},
++	{0x3814, 0x31},
++	{0x3815, 0x31},
++	{0x3820, 0x42},
++	{0x3821, 0x01},
++	{0x3c0e, 0x01},
++	{0x3c0f, 0x30},
++	{0x4001, 0x40},
++	{0x4004, 0x02},
++	{0x0100, 0x01},
++	{OV7251_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list ov7251_init_regs_160_120_mipi[] = {
++	{0x3501, 0x02}, //
++	{0x3502, 0x80}, //expo
++//	{0x3509, 0x18},
++//	{0x3504, 0x03},
++//	{0x3505, 0x00}, //mannual again
++	{0x3674, 0xff}, //
++	{0x373c, 0xe8}, //
++	{0x37a8, 0x02}, //
++	{0x37a9, 0x14}, //
++	{0x3803, 0x00}, //
++	{0x3807, 0xef}, //
++	{0x3808, 0x00}, //01
++	{0x3809, 0xa0}, //40
++	{0x380a, 0x00}, //
++	{0x380b, 0x78}, //f0
++	{0x380c, 0x03}, //
++	{0x380d, 0xa0}, //HTS
++	{0x380e, 0x02}, //
++	{0x380f, 0x0a}, //VTS
++	{0x3811, 0x02},
++	{0x3813, 0x03}, //05
++	{0x3814, 0x44}, //31
++	{0x3815, 0x44}, //31
++	{0x3820, 0x42}, //
++	{0x3821, 0x01}, //
++	{0x3c0c, 0x01}, //
++	{0x3c0d, 0x82}, //
++	{0x3c0e, 0x01}, //
++	{0x3c0f, 0x30}, //
++	{0x4001, 0x40}, //
++	{0x4004, 0x02}, //
++	{0x0100, 0x01}, //
++	{OV7251_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list ov7251_common_init_regs_mipi[] = {
++	{0x0103, 0x01},
++	{0x0100, 0x00},
++	{0x3005, 0x00},
++	{0x3012, 0xc0},
++	{0x3013, 0xd2},
++	{0x3014, 0x04},
++	{0x3016, 0x10},
++	{0x3017, 0x00},
++	{0x3018, 0x00},
++	{0x301a, 0x00},
++	{0x301b, 0x00},
++	{0x301c, 0x00},
++	{0x3023, 0x05},
++	{0x3037, 0xf0},
++	{0x3098, 0x04},
++	{0x3099, 0x28},
++	{0x309a, 0x05},
++	{0x309b, 0x04},
++	{0x30b0, 0x0a},
++	{0x30b1, 0x01},
++	{0x30b3, 0x64},
++	{0x30b4, 0x03},
++	{0x30b5, 0x05},
++	{0x3106, 0xda},
++	{0x3500, 0x00},
++	{0x3503, 0x07},
++	{0x3509, 0x10},
++	{0x350b, 0x10},
++	{0x3600, 0x1c},
++	{0x3602, 0x62},
++	{0x3620, 0xb7},
++	{0x3622, 0x04},
++	{0x3626, 0x21},
++	{0x3627, 0x30},
++	{0x3630, 0x44},
++	{0x3631, 0x35},
++	{0x3634, 0x60},
++	{0x3636, 0x00},
++	{0x3662, 0x01},
++	{0x3663, 0x70},
++	{0x3664, 0xf0},
++	{0x3666, 0x0a},
++	{0x3669, 0x1a},
++	{0x366a, 0x00},
++	{0x366b, 0x50},
++	{0x3673, 0x01},
++	{0x3675, 0x03},
++	{0x3705, 0x41},
++	{0x3709, 0x40},
++	{0x3742, 0x00},
++	{0x3757, 0xb3},
++	{0x3788, 0x00},
++	{0x3800, 0x00},
++	{0x3801, 0x04},
++	{0x3802, 0x00},
++	{0x3804, 0x02},
++	{0x3805, 0x8b},
++	{0x3806, 0x01},
++	{0x3810, 0x00},
++	{0x3811, 0x04},
++	{0x3812, 0x00},
++	{0x382f, 0x0e},
++	{0x3832, 0x00},
++	{0x3833, 0x05},
++	{0x3834, 0x00},
++	{0x3835, 0x0c},
++	{0x3837, 0x00},
++	{0x3b80, 0x00},
++	{0x3b81, 0xa5},
++	{0x3b82, 0x10},
++	{0x3b83, 0x00},
++	{0x3b84, 0x08},
++	{0x3b85, 0x00},
++	{0x3b86, 0x01},
++	{0x3b87, 0x00},
++	{0x3b88, 0x00},
++	{0x3b89, 0x00},
++	{0x3b8a, 0x00},
++	{0x3b8b, 0x05},
++	{0x3b8c, 0x00},
++	{0x3b8d, 0x00},
++	{0x3b8e, 0x00},
++	{0x3b8f, 0x1a},
++	{0x3b94, 0x05},
++	{0x3b95, 0xf2},
++	{0x3b96, 0x40},
++	{0x3c00, 0x89},
++	{0x3c01, 0x63},
++	{0x3c02, 0x01},
++	{0x3c03, 0x00},
++	{0x3c04, 0x00},
++	{0x3c05, 0x03},
++	{0x3c06, 0x00},
++	{0x3c07, 0x06},
++	{0x4005, 0x00},
++	{0x404e, 0x01},
++	{0x4300, 0xff},
++	{0x4301, 0x00},
++	{0x4501, 0x48},
++	{0x4600, 0x00},
++	{0x4601, 0x4e},
++	{0x4801, 0x0f},
++	{0x4806, 0x0f},
++	{0x4819, 0xaa},
++	{0x4823, 0x3e},
++	{0x4837, 0x19},
++	{0x4a0d, 0x00},
++	{0x4a47, 0x7f},
++	{0x4a49, 0xf0},
++	{0x4a4b, 0x30},
++	{0x5000, 0x85},
++	{0x5001, 0x80},
++	{OV7251_REG_END, 0x00},	/* END MARKER */
++};
++
++/*
++ * the part of driver was fixed.
++ */
++
++static struct regval_list ov7251_stream_on_mipi[] = {
++	{0x0100, 0x01},
++	{OV7251_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list ov7251_stream_off_mipi[] = {
++	{0x0100, 0x00},
++	{OV7251_REG_END, 0x00},	/* END MARKER */
++};
++
++static int ov7251_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct ov7251_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret = 0;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ov7251_write(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char value)
++{
++	struct ov7251_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3] = {(reg>>8)&0xff, reg&0xff, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 3,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int ov7251_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != OV7251_REG_END) {
++		if (vals->reg_num == OV7251_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ov7251_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++/*
++ * Write a list of register settings; ff/ff stops the process.
++ */
++static int ov7251_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != OV7251_REG_END) {
++		if (vals->reg_num == OV7251_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = ov7251_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int ov7251_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov7251_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(10);
++	}
++	return 0;
++}
++
++static int ov7251_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov7251_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++	} else {
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, !info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++	}
++	return 0;
++}
++
++static int ov7251_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct ov7251_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = ov7251_write_array(sd, ov7251_common_init_regs_mipi);
++
++	return ret;
++}
++
++
++
++static int ov7251_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v = 0;
++	int ret;
++//while(1)
++	{
++	ret = ov7251_read(sd, 0x300a, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	}
++	if (ret < 0)
++		return ret;
++	if (v != OV7251_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = ov7251_read(sd, 0x300b, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++
++	if (ret < 0)
++		return ret;
++	if (v != OV7251_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	return 0;
++}
++
++
++static struct ov7251_win_size ov7251_win_sizes[] = {
++	{
++		.sensor_info.mipi_cfg.twidth		= 640,
++		.sensor_info.mipi_cfg.theight		= 480,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.fps			= 60 << 16 | 1,
++
++		.width		= 640,
++		.height		= 480,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov7251_init_regs_640_480_mipi,
++	},
++	{
++		.sensor_info.mipi_cfg.twidth		= 320,
++		.sensor_info.mipi_cfg.theight		= 240,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.fps			= 60 << 16 | 1,
++
++		.width		= 320,
++		.height		= 240,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov7251_init_regs_320_240_mipi,
++	},
++	{
++		.sensor_info.mipi_cfg.twidth		= 160,
++		.sensor_info.mipi_cfg.theight		= 120,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.fps			= 75 << 16 | 1,
++
++		.width		= 160,
++		.height		= 120,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= ov7251_init_regs_160_120_mipi,
++	},
++};
++
++static const struct ov7251_win_size *ov7251_select_win(u32 *width, u32 *height)
++{
++	int i, default_size = ARRAY_SIZE(ov7251_win_sizes) - 1;
++
++	for (i = 0; i < ARRAY_SIZE(ov7251_win_sizes); i++) {
++		if ((*width >= ov7251_win_sizes[i].width) &&
++				(*height >= ov7251_win_sizes[i].height)) {
++			*width = ov7251_win_sizes[i].width;
++			*height = ov7251_win_sizes[i].height;
++			return &ov7251_win_sizes[i];
++		}
++	}
++
++	*width = ov7251_win_sizes[default_size].width;
++	*height = ov7251_win_sizes[default_size].height;
++	return &ov7251_win_sizes[default_size];
++}
++
++
++static int ov7251_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_OV7251_FMTS)
++		return -EINVAL;
++
++	code->code = ov7251_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int ov7251_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct ov7251_format_struct *ovfmt;
++	struct ov7251_win_size *wsize;
++	struct ov7251_info *info = to_state(sd);
++	int ret;
++
++	info->win = ov7251_select_win(&format->format.width, &format->format.height);
++
++	return 0;
++}
++
++static int ov7251_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct ov7251_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	*(unsigned int *)fmt->reserved = &info->win->sensor_info;
++
++
++//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int ov7251_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov7251_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov7251_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov7251_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int ov7251_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int ov7251_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov7251_again_lut); i++) {
++		lut = &ov7251_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(ov7251_again_lut); i++) {
++		lut = &ov7251_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++}
++
++static int ov7251_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	/*
++	struct ov7251_info *info = to_state(sd);
++	char v = 0;
++	unsigned int reg_val = 0;
++
++
++	ret += ov7251_read(sd, 0x3509, &v);
++
++	reg_val |= v;
++	ret += ov7251_read(sd, 0x3508, &v);
++	reg_val |= v << 8;
++
++
++	*value = regval_to_again(reg_val);
++	*/
++
++	return ret;
++}
++/*set analog gain db value, map value to sensor register.*/
++static int ov7251_s_again(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++#if 0
++	struct ov7251_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int i;
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(value);
++	}
++
++	ret += ov7251_write(sd, 0x3509, (unsigned char)(reg_value & 0xff));
++	ret += ov7251_write(sd, 0x3508, (unsigned char)((reg_value>>8) & 0xff));
++	if (ret < 0)
++		return ret;
++
++#endif
++	return ret;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int ov7251_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int ov7251_s_exp(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++	/*
++	struct ov7251_info *info = to_state(sd);
++
++	ret += ov7251_write(sd, 0x3502, ((unsigned char)(value & 0xf)) << 4);
++	ret += ov7251_write(sd, 0x3501, (unsigned char)((value >> 4) & 0xff));
++	ret += ov7251_write(sd, 0x3500, (unsigned char)((value >> 12) & 0xf));
++
++	*/
++	return ret;
++}
++
++static int ov7251_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov7251_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return ov7251_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov7251_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int ov7251_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct ov7251_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return ov7251_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return ov7251_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return ov7251_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return ov7251_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* ov7251_s_gain turns off auto gain */
++			return ov7251_s_gain(sd, info->gain->val);
++		}
++		return ov7251_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return ov7251_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return ov7251_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return ov7251_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops ov7251_ctrl_ops = {
++	.s_ctrl = ov7251_s_ctrl,
++	.g_volatile_ctrl = ov7251_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ov7251_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = ov7251_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int ov7251_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	ov7251_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int ov7251_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct ov7251_info *info = to_state(sd);
++	int ret = 0;
++
++	if (enable) {
++		ov7251_write_array(sd, info->win->regs);
++		ov7251_s_again(sd, 100000);
++		ret = ov7251_write_array(sd, ov7251_stream_on_mipi);
++		pr_debug("ov7251 stream on\n");
++
++	}
++	else {
++		ret = ov7251_write_array(sd, ov7251_stream_off_mipi);
++		pr_debug("ov7251 stream off\n");
++	}
++	return ret;
++}
++
++int ov7251_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct ov7251_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops ov7251_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = ov7251_g_register,
++	.s_register = ov7251_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops ov7251_video_ops = {
++	.s_stream = ov7251_s_stream,
++	.g_frame_interval = ov7251_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops ov7251_pad_ops = {
++	//.enum_frame_interval = ov7251_enum_frame_interval,
++	//.num_frame_size = ov7251_enum_frame_size,
++	//.enum_mbus_code = ov7251_enum_mbus_code,
++	.set_fmt = ov7251_set_fmt,
++	.get_fmt = ov7251_get_fmt,
++};
++
++static const struct v4l2_subdev_ops ov7251_ops = {
++	.core = &ov7251_core_ops,
++	.video = &ov7251_video_ops,
++	.pad = &ov7251_pad_ops,
++};
++
++int ov7251_regulator_get_supply(struct device *dev)
++{
++	int ret;
++	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov7251_info *info = to_state(sd);
++
++	info->supply.vdd2v8 = devm_regulator_get_optional(dev, "vdd2v8");
++	info->supply.vdd1v8 = devm_regulator_get_optional(dev, "vdd1v8");
++
++	if (IS_ERR(info->supply.vdd2v8)) {
++		if (PTR_ERR(info->supply.vdd2v8) == -EPROBE_DEFER) {
++			printk("No vdd2v8 regulator found\n");
++			return -EPROBE_DEFER;
++    	}
++	}
++
++	if (IS_ERR(info->supply.vdd1v8)) {
++		if (PTR_ERR(info->supply.vdd1v8) == -EPROBE_DEFER) {
++			printk("No vdd1v8 regulator found\n");
++			return -EPROBE_DEFER;
++    	}
++	}
++	if (!IS_ERR(info->supply.vdd2v8)) {
++		ret = regulator_enable(info->supply.vdd2v8);
++		if (ret) {
++			dev_err(&client->dev, "ov7251 vdd2v8 supply enable failed\n");
++			return ret;
++		}
++	}
++	if (!IS_ERR(info->supply.vdd1v8)) {
++		ret = regulator_enable(info->supply.vdd1v8);
++		if (ret) {
++			dev_err(&client->dev, "ov7251 vdd1v8 supply enable failed\n");
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++/* ----------------------------------------------------------------------- */
++
++static int ov7251_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_fract tpf;
++	struct v4l2_subdev *sd;
++	struct ov7251_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++	int tmp;
++
++	dev_info(&client->dev, "ov7251 probing\n");
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutp-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutp.pin = gpio;
++		info->ircutp.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->ircutn.pin = gpio;
++		info->ircutn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	v4l2_i2c_subdev_init(sd, client, &ov7251_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	ret = ov7251_regulator_get_supply(&client->dev);
++	if (ret)
++		dev_err(&client->dev, "get supply failed!\n");
++
++	/*clk*/
++	info->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++
++	info->win = &ov7251_win_sizes[0];
++	ov7251_reset(sd, 1);
++#if 1
++	/* Make sure it's an ov7251 */
++	ret = ov7251_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an ov7251 chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &ov7251_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &ov7251_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &ov7251_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &ov7251_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7251_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &ov7251_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 261773, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7251_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1520 - 4, 1, 1000);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	ov7251_init(sd, 1);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "ov7251 Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int ov7251_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov7251_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id ov7251_id[] = {
++	{ "ov7251", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ov7251_id);
++
++static const struct of_device_id ov7251_of_match[] = {
++	{.compatible = "ovti,ov7251", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov2640_of_match);
++
++int ov7251_suspend(struct device *dev)
++{
++	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov7251_info *info = to_state(sd);
++	int ret;
++
++	if (!IS_ERR(info->supply.vdd2v8)) {
++		ret = regulator_disable(info->supply.vdd2v8);
++		if (ret) {
++			dev_err(dev, "ov7251 vdd2v8 supply disable failed\n");
++			return ret;
++		}
++	}
++	if (!IS_ERR(info->supply.vdd1v8)) {
++		ret = regulator_disable(info->supply.vdd1v8);
++		if (ret) {
++			dev_err(dev, "ov7251 vdd1v8 supply disable failed\n");
++			return ret;
++		}
++	}
++
++	v4l2_clk_disable(info->clk);
++	return 0;
++}
++
++int ov7251_resume(struct device *dev)
++{
++	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct ov7251_info *info = to_state(sd);
++	int ret;
++
++	if (!IS_ERR(info->supply.vdd2v8)) {
++		ret = regulator_enable(info->supply.vdd2v8);
++		if (ret) {
++			dev_err(dev, "ov7251 vdd2v8 supply enable failed\n");
++			return ret;
++		}
++	}
++	if (!IS_ERR(info->supply.vdd1v8)) {
++		ret = regulator_enable(info->supply.vdd1v8);
++		if (ret) {
++			dev_err(dev, "ov7251 vdd1v8 supply enable failed\n");
++			return ret;
++		}
++	}
++
++	v4l2_clk_enable(info->clk);
++	ov7251_reset(sd, 1);
++	ov7251_init(sd, 1);
++	return 0;
++}
++
++const struct dev_pm_ops ov7251_pm =
++{
++	.suspend = ov7251_suspend,
++	.resume = ov7251_resume,
++};
++
++
++
++static struct i2c_driver ov7251_driver = {
++	.driver = {
++		.name	= "ov7251",
++		.of_match_table = of_match_ptr(ov7251_of_match),
++		.pm	= &ov7251_pm,
++	},
++	.probe		= ov7251_probe,
++	.remove		= ov7251_remove,
++	.id_table	= ov7251_id,
++};
++
++module_i2c_driver(ov7251_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for OmniVision ov7251 sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/sc0132gs.c b/module_drivers/drivers/media/i2c/ingenic-isp/sc0132gs.c
+new file mode 100644
+index 000000000..323b21b2d
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/sc0132gs.c
+@@ -0,0 +1,1630 @@
++/*
++ * A V4L2 driver for OmniVision SC0132GS cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++#include <isp-sensor.h>
++
++#define SC0132GS_CHIP_ID_H       (0x01)
++#define SC0132GS_CHIP_ID_L       (0x32)
++#define SC0132GS_REG_END		0xffff
++#define SC0132GS_REG_DELAY	0xfffe
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct sc0132gs_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct sc0132gs_gpio {
++	int pin;
++	int active_level;
++};
++
++struct sc0132gs_supply{
++	struct regulator *avdd;
++	struct regulator *dvdd;
++	struct regulator *dovdd;
++};
++
++struct sc0132gs_info {
++	struct sc0132gs_supply supply;
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++	struct clk *sclka;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct sc0132gs_win_size *win;
++
++	struct sc0132gs_gpio reset;
++	struct sc0132gs_gpio vcc_en;
++	struct sc0132gs_gpio ircutp;
++	struct sc0132gs_gpio ircutn;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++struct again_lut sc0132gs_again_lut[] = {
++
++	{0x80, 0},
++	{0x88, 5731},
++	{0x90, 11136},
++	{0x98, 16248},
++	{0xa0, 21097},
++	{0xa8, 25710},
++	{0xb0, 30109},
++	{0xb8, 34312},
++	{0xc0, 38336},
++	{0xc8, 42195},
++	{0xd0, 45904},
++	{0xd8, 49472},
++	{0xe0, 52910},
++	{0xe8, 56228},
++	{0xf0, 59433},
++	{0xf8, 62534},
++	{0x178, 65536},
++	{0x17c, 68445},
++	{0x180, 71267},
++	{0x184, 74008},
++	{0x188, 76672},
++	{0x18c, 79262},
++	{0x190, 81784},
++	{0x194, 84240},
++	{0x198, 86633},
++	{0x19c, 88968},
++	{0x1a0, 91246},
++	{0x1a4, 93471},
++	{0x1a8, 95645},
++	{0x1ac, 97770},
++	{0x1b0, 99848},
++	{0x1b4, 101881},
++	{0x1b8, 103872},
++	{0x1bc, 105821},
++	{0x1c0, 107731},
++	{0x1c4, 109604},
++	{0x1c8, 111440},
++	{0x1cc, 113241},
++	{0x1d0, 115008},
++	{0x1d4, 116743},
++	{0x1d8, 118446},
++	{0x1dc, 120120},
++	{0x1e0, 121764},
++	{0x1e4, 123380},
++	{0x1e8, 124969},
++	{0x1ec, 126532},
++	{0x1f0, 128070},
++	{0x1f4, 129583},
++	{0x374, 131072},
++	{0x376, 132537},
++	{0x378, 133981},
++	{0x37a, 135403},
++	{0x37c, 136803},
++	{0x37e, 138184},
++	{0x380, 139544},
++	{0x382, 140885},
++	{0x384, 142208},
++	{0x386, 143512},
++	{0x388, 144798},
++	{0x38a, 146067},
++	{0x38c, 147320},
++	{0x38e, 148556},
++	{0x390, 149776},
++	{0x392, 150980},
++	{0x394, 152169},
++	{0x396, 153344},
++	{0x398, 154504},
++	{0x39a, 155650},
++	{0x39c, 156782},
++	{0x39e, 157901},
++	{0x3a0, 159007},
++	{0x3a2, 160100},
++	{0x3a4, 161181},
++	{0x3a6, 162249},
++	{0x3a8, 163306},
++	{0x3aa, 164350},
++	{0x3ac, 165384},
++	{0x3ae, 166406},
++	{0x3b0, 167417},
++	{0x3b2, 168418},
++	{0x3b4, 169408},
++	{0x3b6, 170387},
++	{0x3b8, 171357},
++	{0x3ba, 172317},
++	{0x3bc, 173267},
++	{0x3be, 174208},
++	{0x3c0, 175140},
++	{0x3c2, 176062},
++	{0x3c4, 176976},
++	{0x3c6, 177880},
++	{0x3c8, 178777},
++	{0x3ca, 179664},
++	{0x3cc, 180544},
++	{0x3ce, 181415},
++	{0x3d0, 182279},
++	{0x3d2, 183134},
++	{0x3d4, 183982},
++	{0x3d6, 184823},
++	{0x3d8, 185656},
++	{0x3da, 186482},
++	{0x3dc, 187300},
++	{0x3de, 188112},
++	{0x3e0, 188916},
++	{0x3e2, 189714},
++	{0x3e4, 190505},
++	{0x3e6, 191290},
++	{0x3e8, 192068},
++	{0x3ea, 192840},
++	{0x3ec, 193606},
++	{0x3ee, 194365},
++	{0x3f0, 195119},
++	{0x3f2, 195866},
++	{0x778, 196608},
++	{0x779, 197343},
++	{0x77a, 198073},
++	{0x77b, 198798},
++	{0x77c, 199517},
++	{0x77d, 200230},
++	{0x77e, 200939},
++	{0x77f, 201642},
++	{0x780, 202339},
++	{0x781, 203032},
++	{0x782, 203720},
++	{0x783, 204402},
++	{0x784, 205080},
++	{0x785, 205753},
++	{0x786, 206421},
++	{0x787, 207085},
++	{0x788, 207744},
++	{0x789, 208398},
++	{0x78a, 209048},
++	{0x78b, 209693},
++	{0x78c, 210334},
++	{0x78d, 210971},
++	{0x78e, 211603},
++	{0x78f, 212232},
++	{0x790, 212856},
++	{0x791, 213476},
++	{0x792, 214092},
++	{0x793, 214704},
++	{0x794, 215312},
++	{0x795, 215916},
++	{0x796, 216516},
++	{0x797, 217113},
++	{0x798, 217705},
++	{0x799, 218294},
++	{0x79a, 218880},
++	{0x79b, 219462},
++	{0x79c, 220040},
++	{0x79d, 220615},
++	{0x79e, 221186},
++	{0x79f, 221754},
++	{0x7a0, 222318},
++	{0x7a1, 222880},
++	{0x7a2, 223437},
++	{0x7a3, 223992},
++	{0x7a4, 224543},
++	{0x7a5, 225091},
++	{0x7a6, 225636},
++	{0x7a7, 226178},
++	{0x7a8, 226717},
++	{0x7a9, 227253},
++	{0x7aa, 227785},
++	{0x7ab, 228315},
++	{0x7ac, 228842},
++	{0x7ad, 229365},
++	{0x7ae, 229886},
++	{0x7af, 230404},
++	{0x7b0, 230920},
++	{0x7b1, 231432},
++	{0x7b2, 231942},
++	{0x7b3, 232449},
++	{0x7b4, 232953},
++	{0x7b5, 233455},
++	{0x7b6, 233954},
++	{0x7b7, 234450},
++	{0x7b8, 234944},
++	{0x7b9, 235435},
++	{0x7ba, 235923},
++	{0x7bb, 236410},
++	{0x7bc, 236893},
++	{0x7bd, 237374},
++	{0x7be, 237853},
++	{0x7bf, 238329},
++	{0x7c0, 238803},
++	{0x7c1, 239275},
++	{0x7c2, 239744},
++	{0x7c3, 240211},
++	{0x7c4, 240676},
++	{0x7c5, 241138},
++	{0x7c6, 241598},
++	{0x7c7, 242056},
++	{0x7c8, 242512},
++	{0x7c9, 242965},
++	{0x7ca, 243416},
++	{0x7cb, 243865},
++	{0x7cc, 244313},
++	{0x7cd, 244757},
++	{0x7ce, 245200},
++	{0x7cf, 245641},
++	{0x7d0, 246080},
++	{0x7d1, 246517},
++	{0x7d2, 246951},
++	{0x7d3, 247384},
++	{0x7d4, 247815},
++	{0x7d5, 248243},
++	{0x7d6, 248670},
++	{0x7d7, 249095},
++	{0x7d8, 249518},
++	{0x7d9, 249939},
++	{0x7da, 250359},
++	{0x7db, 250776},
++	{0x7dc, 251192},
++	{0x7dd, 251606},
++	{0x7de, 252018},
++	{0x7df, 252428},
++	{0x7e0, 252836},
++	{0x7e1, 253243},
++	{0x7e2, 253648},
++	{0x7e3, 254051},
++	{0x7e4, 254452},
++	{0x7e5, 254852},
++	{0x7e6, 255250},
++	{0x7e7, 255647},
++	{0x7e8, 256041},
++	{0x7e9, 256435},
++	{0x7ea, 256826},
++	{0x7eb, 257216},
++	{0x7ec, 257604},
++	{0x7ed, 257991},
++	{0x7ee, 258376},
++	{0x7ef, 258760},
++	{0x7f0, 259142},
++	{0x7f1, 259522},
++	{0x7f2, 259901},
++	{0x7f3, 260279},
++	{0x7f4, 260655},
++	{0x7f5, 261029},
++	{0x7f6, 261402},
++	{0x7f7, 261773},
++};
++
++static struct i2c_client *led_ic_client;
++static struct i2c_board_info aw9110b_info = {	
++	I2C_BOARD_INFO("aw9110b", 0x5b),
++};
++
++static inline struct sc0132gs_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct sc0132gs_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct sc0132gs_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++static struct regval_list sc0132gs_init_regs_1080_1280_60fps_mipi[] = {
++	//[ParaList]
++#if 1
++	//sc132gs_setting_1080x1280
++	{0x0103,0x01},
++	{0x0100,0x00},
++	//PLL bypass
++	{0x36e9,0x80},
++	{0x36f9,0x80},
++	{0x0100,0x00},
++	{0x3018,0x32},
++	{0x3019,0x0c},
++	{0x301a,0xb4},
++	{0x3031,0x08}, // raw8
++	//{0x3031,0x0a}, // raw10
++	{0x3032,0x60},
++	{0x3038,0x44},
++	{0x3207,0x17},
++	{0x320c,0x05},
++	{0x320d,0x35},
++	{0x320e,0x05},
++	{0x320f,0x46},
++	{0x3250,0xcc},
++	{0x3251,0x02},
++	{0x3252,0x05},
++	{0x3253,0x41},
++	{0x3254,0x05},
++	{0x3255,0x3b},
++	{0x3306,0x78},
++	{0x330a,0x00},
++	{0x330b,0xc8},
++	{0x330f,0x24},
++	{0x3314,0x80},
++	{0x3315,0x40},
++	{0x3317,0xf0},
++	{0x331f,0x12},
++	{0x3364,0x00},
++	{0x3385,0x41},
++	{0x3387,0x41},
++	{0x3389,0x09},
++	{0x33ab,0x00},
++	{0x33ac,0x00},
++	{0x33b1,0x03},
++	{0x33b2,0x12},
++	{0x33f8,0x02},
++	{0x33fa,0x01},
++	{0x3409,0x08},
++	{0x34f0,0xc0},
++	{0x34f1,0x20},
++	{0x34f2,0x03},
++	{0x3622,0xf5},
++	{0x3630,0x5c},
++	{0x3631,0x80},
++	{0x3632,0xc8},
++	{0x3633,0x32},
++	{0x3638,0x2a},
++	{0x3639,0x07},
++	{0x363b,0x48},
++	{0x363c,0x83},
++	{0x363d,0x10},
++	{0x36ea,0x38},
++	{0x36fa,0x25},
++	{0x36fb,0x05},
++	{0x36fd,0x04},
++	{0x3900,0x11},
++	{0x3901,0x05},
++	{0x3902,0xc5},
++	{0x3904,0x04},
++	{0x3908,0x91},
++	{0x391e,0x00},
++	{0x3e01,0x53},
++	{0x3e02,0xe0},
++	{0x3e06,0x07},//Bit[3:0]: digital gain
++	{0x3e08,0x05},//10 gain
++	{0x3e09,0x12},//
++	{0x3e0e,0xd2},
++	{0x3e14,0xb0},
++	{0x3e1e,0x7c},
++	{0x3e26,0x20},
++	{0x4418,0x38},
++	//{0x4501,0x08}, // test Bit[3]: incremental pattern
++	{0x4503,0x10},
++	{0x4837,0x21},
++	{0x5000,0x0e},
++	{0x540c,0x51},
++	{0x550f,0x38},
++	{0x5780,0x67},
++	{0x5784,0x10},
++	{0x5785,0x06},
++	{0x5787,0x02},
++	{0x5788,0x00},
++	{0x5789,0x00},
++	{0x578a,0x02},
++	{0x578b,0x00},
++	{0x578c,0x00},
++	{0x5790,0x00},
++	{0x5791,0x00},
++	{0x5792,0x00},
++	{0x5793,0x00},
++	{0x5794,0x00},
++	{0x5795,0x00},
++	{0x5799,0x04},
++	//PLL set
++	{0x36e9,0x20},
++	{0x36f9,0x24},
++	{0x0100,0x01},
++	{0x33fa,0x02},
++	{0x3317,0x0a},
++	{0x0100,0x01},
++	{0x3221,0x66}, // flip,mirror on
++	//{0x3221,0x00}, // flip,mirror off
++#endif
++	{SC0132GS_REG_END, 0x00},	/* END MARKER */
++};
++
++
++/*
++ * the part of driver was fixed.
++ */
++
++static struct regval_list sc0132gs_stream_on_mipi[] = {
++	{0x0100, 0x01},
++	{SC0132GS_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list sc0132gs_stream_off_mipi[] = {
++	{0x0100, 0x00},
++	{SC0132GS_REG_END, 0x00},	/* END MARKER */
++};
++
++static int sc0132gs_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct sc0132gs_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret = 0;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int sc0132gs_write(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char value)
++{
++	struct sc0132gs_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3] = {(reg>>8)&0xff, reg&0xff, value};
++	//printk("sc0132gs write i2c with %d %d\n", buf[0], buf[1]);
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 3,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int sc0132gs_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != SC0132GS_REG_END) {
++		if (vals->reg_num == SC0132GS_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = sc0132gs_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++/*
++ * Write a list of register settings; ff/ff stops the process.
++ */
++static int sc0132gs_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != SC0132GS_REG_END) {
++		if (vals->reg_num == SC0132GS_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = sc0132gs_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int sc0132gs_power(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc0132gs_info *info = to_state(sd);
++	/*struct i2c_client *client = v4l2_get_subdevdata(sd);
++	int ret;*/
++
++	if(val){
++		gpio_direction_output(info->vcc_en.pin, info->vcc_en.active_level);
++	}else{
++		gpio_direction_output(info->vcc_en.pin, !info->vcc_en.active_level);
++	}
++	/*info->supply.avdd  = devm_regulator_get_optional(&client->dev, "avdd");
++	info->supply.dvdd  = devm_regulator_get_optional(&client->dev, "dvdd");
++	info->supply.dovdd = devm_regulator_get_optional(&client->dev, "dovdd");
++
++	if (IS_ERR(info->supply.avdd)||IS_ERR(info->supply.dvdd)
++		||IS_ERR(info->supply.dovdd)) {
++			if ((PTR_ERR(info->supply.avdd) == -EPROBE_DEFER)
++				||(PTR_ERR(info->supply.avdd) == -EPROBE_DEFER)
++					||(PTR_ERR(info->supply.avdd) == -EPROBE_DEFER))
++				return -EPROBE_DEFER;
++			printk("No sc230ai vdd regulator found\n");
++	}
++
++	if ((!IS_ERR(info->supply.avdd))&&(!IS_ERR(info->supply.avdd))
++			&&(!IS_ERR(info->supply.avdd)))  {
++		if(val){
++			ret = regulator_enable(info->supply.avdd);
++			ret = regulator_enable(info->supply.dvdd);
++			ret = regulator_enable(info->supply.dovdd);
++			if (ret)
++			   dev_err(&client->dev, "sc230ai vdd supply disable failed\n");
++		}
++		else{
++			ret = regulator_disable(info->supply.avdd);
++			ret = regulator_disable(info->supply.dvdd);
++			ret = regulator_disable(info->supply.dovdd);
++			if (ret)
++			    dev_err(&client->dev, "sc230ai vdd supply disable failed\n");
++		}
++	}else{
++		dev_err(&client->dev, "sc230ai vdd supply IS_ERR failed\n");
++	}*/
++	return 0;
++}
++
++static int sc0132gs_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc0132gs_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(10);
++	}
++	return 0;
++}
++
++static int sc0132gs_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc0132gs_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++	} else {
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, !info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++	}
++	return 0;
++}
++
++/*
++static int sc0132gs_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc0132gs_info *info = to_state(sd);
++	int ret = 0;
++	//printk("sc0132gs init called ....\n");
++	ret = sc0132gs_write_array(sd, info->win->regs);
++
++	return ret;
++}
++*/
++
++
++static int sc0132gs_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v = 0;
++	int ret;
++
++	ret = sc0132gs_read(sd, 0x3107, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != SC0132GS_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = sc0132gs_read(sd, 0x3108, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != SC0132GS_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	return 0;
++}
++
++#if 0
++/* grey y8 */
++static struct sc0132gs_win_size sc0132gs_win_sizes[] = {
++	{
++		.width		= 1080,
++		.height		= 1280,
++		//.fps		= 60 << 16 | 1,
++		.sensor_info.fps				= 60 << 16 | 1,
++		.sensor_info.mipi_cfg.twidth		= 1080,
++		.sensor_info.mipi_cfg.theight		= 1280,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		//.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.mbus_code	= MEDIA_BUS_FMT_Y8_1X8,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= sc0132gs_init_regs_1080_1280_60fps_mipi,
++	},
++};
++#else
++/* YUV422 */
++static struct sc0132gs_win_size sc0132gs_win_sizes[] = {
++	{
++		.width		= 1080/2,
++		.height		= 1280,
++		//.fps		= 60 << 16 | 1,
++		.sensor_info.fps				= 60 << 16 | 1,
++		.sensor_info.mipi_cfg.twidth		= 1080/2,
++		.sensor_info.mipi_cfg.theight		= 1280,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		//.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		//.mbus_code	= MEDIA_BUS_FMT_Y8_1X8,
++		//.mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8,
++		//.mbus_code	= MEDIA_BUS_FMT_YVYU8_2X8,
++		//.mbus_code	= MEDIA_BUS_FMT_VYUY8_2X8,
++		.mbus_code	= MEDIA_BUS_FMT_UYVY8_2X8, /* sc0132gs UYVY8_2X8 order ok. */
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= sc0132gs_init_regs_1080_1280_60fps_mipi,
++	},
++};
++#endif
++
++static int sc0132gs_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_SC0132GS_FMTS)
++		return -EINVAL;
++
++	code->code = sc0132gs_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int sc0132gs_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct sc0132gs_format_struct *ovfmt;
++	struct sc0132gs_win_size *wsize;
++	struct sc0132gs_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int sc0132gs_get_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct sc0132gs_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	*(unsigned int *)fmt->reserved = &info->win->sensor_info;
++
++
++	//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++	//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int sc0132gs_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc0132gs_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc0132gs_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc0132gs_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int sc0132gs_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int sc0132gs_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(sc0132gs_again_lut); i++) {
++		lut = &sc0132gs_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(sc0132gs_again_lut); i++) {
++		lut = &sc0132gs_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++}
++
++static int sc0132gs_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	/*
++	   struct sc0132gs_info *info = to_state(sd);
++	   char v = 0;
++	   unsigned int reg_val = 0;
++
++
++	   ret += sc0132gs_read(sd, 0x3509, &v);
++
++	   reg_val |= v;
++	   ret += sc0132gs_read(sd, 0x3508, &v);
++	   reg_val |= v << 8;
++
++
++	 *value = regval_to_again(reg_val);
++	 */
++
++	return ret;
++}
++/*set analog gain db value, map value to sensor register.*/
++static int sc0132gs_s_again(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++#if 0
++	struct sc0132gs_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int i;
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(value);
++	}
++
++	ret += sc0132gs_write(sd, 0x3509, (unsigned char)(reg_value & 0xff));
++	ret += sc0132gs_write(sd, 0x3508, (unsigned char)((reg_value>>8) & 0xff));
++	if (ret < 0)
++		return ret;
++
++#endif
++	return ret;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int sc0132gs_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc0132gs_s_exp(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++	/*
++	   struct sc0132gs_info *info = to_state(sd);
++
++	   if(info->exposure->val != value) {
++	   ret += sc0132gs_write(sd, 0x3502, ((unsigned char)(value & 0xf)) << 4);
++	   ret += sc0132gs_write(sd, 0x3501, (unsigned char)((value >> 4) & 0xff));
++	   ret += sc0132gs_write(sd, 0x3500, (unsigned char)((value >> 12) & 0xf));
++	   }
++
++*/
++	return ret;
++}
++
++static int sc0132gs_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct sc0132gs_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++		case V4L2_CID_AUTOGAIN:
++			return sc0132gs_g_gain(sd, &info->gain->val);
++		case V4L2_CID_ANALOGUE_GAIN:
++			return sc0132gs_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int sc0132gs_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct sc0132gs_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++		case V4L2_CID_BRIGHTNESS:
++			return sc0132gs_s_brightness(sd, ctrl->val);
++		case V4L2_CID_CONTRAST:
++			return sc0132gs_s_contrast(sd, ctrl->val);
++		case V4L2_CID_VFLIP:
++			return sc0132gs_s_vflip(sd, ctrl->val);
++		case V4L2_CID_HFLIP:
++			return sc0132gs_s_hflip(sd, ctrl->val);
++		case V4L2_CID_AUTOGAIN:
++			/* Only set manual gain if auto gain is not explicitly
++			   turned on. */
++			if (!ctrl->val) {
++				/* sc0132gs_s_gain turns off auto gain */
++				return sc0132gs_s_gain(sd, info->gain->val);
++			}
++			return sc0132gs_s_autogain(sd, ctrl->val);
++		case V4L2_CID_GAIN:
++			return sc0132gs_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return sc0132gs_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return sc0132gs_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops sc0132gs_ctrl_ops = {
++	.s_ctrl = sc0132gs_s_ctrl,
++	.g_volatile_ctrl = sc0132gs_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int sc0132gs_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = sc0132gs_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int sc0132gs_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	sc0132gs_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int sc0132gs_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct sc0132gs_info *info = to_state(sd);
++	int ret = 0;
++
++	if (enable) {
++		ret = sc0132gs_write_array(sd, sc0132gs_stream_on_mipi);
++		pr_debug("sc0132gs stream on\n");
++	}
++	else {
++		ret = sc0132gs_write_array(sd, sc0132gs_stream_off_mipi);
++		pr_debug("sc0132gs stream off\n");
++	}
++	return ret;
++}
++typedef struct I2C_regs{
++    struct regval_list regs[8];
++    u16 count;
++}TOMATO_I2C_regs;
++
++#define TOMATO_VIDIOC_IIC_WRITE          _IOWR('V', BASE_VIDIOC_PRIVATE + 1, TOMATO_I2C_regs)
++#define TOMATO_VIDIOC_IIC_READ           _IOWR('V', BASE_VIDIOC_PRIVATE + 2, TOMATO_I2C_regs)
++
++#define VIDIOC_S_SENSORPWRSTATE          _IOW('v',60,int)
++#define VIDIOC_G_SENSORPWRSTATE          _IOR('v',61,int)
++#define VIDIOC_S_ILLUMCTRL               _IOW('v',62,int)
++#define ILLUM_WORKAROUND
++
++#ifdef ILLUM_WORKAROUND
++#define ILLUM_PIN                       32*1 + 24//PB_24
++#define ILLUM_RED_PIN                   32*1 + 29//PB_29
++#define ILLUM_BLUE_PIN                  32*1 + 30//PB_30
++#define ILLUM_CHIP_PIN                  32*1 + 31//PB_31
++#define ILLUM_SET_LEVEL_LOW_PIN			32*1 + 14//GPIO_PB(14)
++#define ILLUM_SET_LEVEL_MID_PIN			32*1 + 13//GPIO_PB(13)
++#define ILLUM_SET_LEVEL_HIGH_PIN		32*1 + 12//GPIO_PB(12)
++#define AIMER_PIN						32*1 + 28//PB_28
++
++typedef struct {
++	int illum_low_level_is_set;
++	int illum_mid_level_is_set;
++	int illum_high_level_is_set;
++} Illum_level;
++
++Illum_level         Illum_level_status = {0,0,0};
++
++static int RequestIlluminationRelatedGpioPins(struct i2c_client *client)
++{
++    int error = 0;
++
++    #ifdef ILLUM_WORKAROUND
++        //illum_enable_ctrl_pin
++        if (!gpio_is_valid(ILLUM_PIN))
++        {
++            //dev_info(&client->dev,"invalid ILLM_PIN gpio number\n");
++            //PRINTDBG("invalid ILLM_PIN gpio number\n");
++            return (-1);
++        }
++        error = gpio_request_one(ILLUM_PIN, GPIOF_OUT_INIT_LOW, "sc0132gs");
++        if (error < 0)
++        {
++            //dev_info(&client->dev,"Failed to request GPIO %d, error %d\n", ILLUM_PIN, error);
++            //PRINTDBG("Failed to request GPIO %d, error %d\n", ILLUM_PIN, error);
++            return error;
++        }
++        //illum_enable_ctrl_pin
++        if (!gpio_is_valid(ILLUM_RED_PIN))
++        {
++            //dev_info(&client->dev,"invalid ILLM_PIN gpio number\n");
++            //PRINTDBG("invalid ILLM_PIN gpio number\n");
++            return (-1);
++        }
++        error = gpio_request_one(ILLUM_RED_PIN, GPIOF_OUT_INIT_LOW, "sc0132gs");
++        if (error < 0)
++        {
++            //dev_info(&client->dev,"Failed to request GPIO %d, error %d\n", ILLUM_PIN, error);
++            //PRINTDBG("Failed to request GPIO %d, error %d\n", ILLUM_PIN, error);
++            return error;
++        }
++        //illum_enable_ctrl_pin
++        if (!gpio_is_valid(ILLUM_BLUE_PIN))
++        {
++            //dev_info(&client->dev,"invalid ILLM_PIN gpio number\n");
++            //PRINTDBG("invalid ILLM_PIN gpio number\n");
++            return (-1);
++        }
++        error = gpio_request_one(ILLUM_BLUE_PIN, GPIOF_OUT_INIT_LOW, "sc0132gs");
++        if (error < 0)
++        {
++            //dev_info(&client->dev,"Failed to request GPIO %d, error %d\n", ILLUM_PIN, error);
++            //PRINTDBG("Failed to request GPIO %d, error %d\n", ILLUM_PIN, error);
++            return error;
++        }
++        //illum_enable_ctrl_pin
++        if (!gpio_is_valid(ILLUM_CHIP_PIN))
++        {
++            //dev_info(&client->dev,"invalid ILLM_PIN gpio number\n");
++            //PRINTDBG("invalid ILLM_PIN gpio number\n");
++            return (-1);
++        }
++        error = gpio_request_one(ILLUM_CHIP_PIN, GPIOF_OUT_INIT_HIGH, "sc0132gs");
++        if (error < 0)
++        {
++            //dev_info(&client->dev,"Failed to request GPIO %d, error %d\n", ILLUM_PIN, error);
++            //PRINTDBG("Failed to request GPIO %d, error %d\n", ILLUM_PIN, error);
++            return error;
++        }        
++		//illum_low_level_pin
++		if (!gpio_is_valid(ILLUM_SET_LEVEL_LOW_PIN))
++		{
++			dev_info(&client->dev,"invalid gpio number:%d!\n",ILLUM_SET_LEVEL_LOW_PIN);
++			return (-1);
++		}
++		error = gpio_request_one(ILLUM_SET_LEVEL_LOW_PIN, GPIOF_OUT_INIT_LOW, "sc0132gs");
++		if (error < 0)
++		{
++			dev_info(&client->dev,"Failed to request GPIO %d, error %d\n", ILLUM_SET_LEVEL_LOW_PIN, error);
++			return error;
++		}
++		//illum_mid_level_pin
++		if (!gpio_is_valid(ILLUM_SET_LEVEL_MID_PIN))
++		{
++			dev_info(&client->dev,"invalid gpio number:%d!\n",ILLUM_SET_LEVEL_MID_PIN);
++			return (-1);
++		}
++		error = gpio_request_one(ILLUM_SET_LEVEL_MID_PIN, GPIOF_OUT_INIT_LOW, "sc0132gs");
++		if (error < 0)
++		{
++			dev_info(&client->dev,"Failed to request GPIO %d, error %d\n", ILLUM_SET_LEVEL_MID_PIN, error);
++			return error;
++		}
++		//illum_high_level_pin
++		if (!gpio_is_valid(ILLUM_SET_LEVEL_HIGH_PIN))
++		{
++			dev_info(&client->dev,"invalid gpio number:%d!\n",ILLUM_SET_LEVEL_HIGH_PIN);
++			return (-1);
++		}
++		error = gpio_request_one(ILLUM_SET_LEVEL_HIGH_PIN, GPIOF_OUT_INIT_LOW, "sc0132gs");
++		if (error < 0)
++		{
++			dev_info(&client->dev,"Failed to request GPIO %d, error %d\n", ILLUM_SET_LEVEL_HIGH_PIN, error);
++			return error;
++		}
++		if (!gpio_is_valid(AIMER_PIN))
++		{
++			dev_info(&client->dev,"invalid AIMER_PIN gpio number\n");
++			return (-1);
++		}
++		error = gpio_request_one(AIMER_PIN, GPIOF_OUT_INIT_LOW, "sc0132gs");
++		if (error < 0)
++		{
++			dev_info(&client->dev,"Failed to request GPIO %d, error %d\n", AIMER_PIN, error);
++			return error;
++		}
++		i2c_smbus_write_byte_data(led_ic_client, 0x02, 0x00);
++		i2c_smbus_write_byte_data(led_ic_client, 0x11, 0x00);
++		i2c_smbus_write_byte_data(led_ic_client, 0x12, 0x00);
++		i2c_smbus_write_byte_data(led_ic_client, 0x13, 0x00);
++		i2c_smbus_write_byte_data(led_ic_client, 0x20, 0x80);
++		i2c_smbus_write_byte_data(led_ic_client, 0x21, 0x80);
++		i2c_smbus_write_byte_data(led_ic_client, 0x22, 0x80);
++		i2c_smbus_write_byte_data(led_ic_client, 0x23, 0x80);
++		i2c_smbus_write_byte_data(led_ic_client, 0x24, 0x80);
++		i2c_smbus_write_byte_data(led_ic_client, 0x25, 0x80);
++		i2c_smbus_write_byte_data(led_ic_client, 0x26, 0x80);
++		i2c_smbus_write_byte_data(led_ic_client, 0x27, 0x80);
++		i2c_smbus_write_byte_data(led_ic_client, 0x28, 0x80);
++		i2c_smbus_write_byte_data(led_ic_client, 0x29, 0x80);
++    #endif
++
++    return error;
++}
++
++static int IlluminationSetLevel(unsigned int illum_level_pin)
++{
++	int error = 0;
++#ifdef ILLUM_WORKAROUND
++
++	//PRINTDBG("Illum_level_status %d %d %d \r\n",Illum_level_status.illum_low_level_is_set,Illum_level_status.illum_mid_level_is_set,Illum_level_status.illum_high_level_is_set);
++	error = gpio_direction_output(illum_level_pin,1);
++	if (error<0)
++	{
++		//dev_info(&client->dev,"Failed to set out direction GPIO %d, error %d\n", illum_level_pin, error);
++		return - 1;
++	}
++
++	if(ILLUM_SET_LEVEL_LOW_PIN == illum_level_pin) 
++	{
++		Illum_level_status.illum_low_level_is_set = 1;
++	}
++	if(ILLUM_SET_LEVEL_MID_PIN == illum_level_pin) 
++	{
++		Illum_level_status.illum_mid_level_is_set = 1;
++	}
++	if(ILLUM_SET_LEVEL_HIGH_PIN == illum_level_pin) 
++	{
++		Illum_level_status.illum_high_level_is_set = 1;
++	}
++	
++	/******************set other illum pins direction input as hardward required***********************/
++	if(ILLUM_SET_LEVEL_LOW_PIN != illum_level_pin)
++	{
++		error = gpio_direction_input(ILLUM_SET_LEVEL_LOW_PIN);
++		if (error<0)
++		{
++			//dev_info(&client->dev,"Failed to set input direction GPIO %d, error %d\n", ILLUM_SET_LEVEL_LOW_PIN, error);
++			return - 1;
++		}
++		else
++		{
++			Illum_level_status.illum_low_level_is_set = 0;
++		}
++	}
++
++	if(ILLUM_SET_LEVEL_MID_PIN != illum_level_pin)
++	{
++		error = gpio_direction_input(ILLUM_SET_LEVEL_MID_PIN);
++		if (error<0)
++		{
++			//dev_info(&client->dev,"Failed to set input direction GPIO %d, error %d\n", ILLUM_SET_LEVEL_MID_PIN, error);
++			return - 1;
++		}
++		else
++		{
++			Illum_level_status.illum_mid_level_is_set = 0;
++		}
++	}
++
++	if(ILLUM_SET_LEVEL_HIGH_PIN != illum_level_pin)
++	{
++		error = gpio_direction_input(ILLUM_SET_LEVEL_HIGH_PIN);
++		if (error<0)
++		{
++			//dev_info(&client->dev,"Failed to set input direction GPIO %d, error %d\n", ILLUM_SET_LEVEL_HIGH_PIN, error);
++			return - 1;
++		}
++		else
++		{
++			Illum_level_status.illum_high_level_is_set = 0;
++		}
++	}
++	/***********************************************************************************************/
++#endif
++	return 0;
++}
++
++static int IlluminationSetControl(long *illum_ctrl)
++{
++    int error = 0;
++
++#ifdef ILLUM_WORKAROUND
++	if (((*illum_ctrl)>>5)&0x1)		// Aimer on
++	{
++		gpio_set_value(AIMER_PIN, 1);
++	}
++	else							// Aimer off
++	{
++		gpio_set_value(AIMER_PIN, 0);
++	}
++
++    if (((*illum_ctrl)>>4)&0x1)     //Illum on
++    {
++		if (((*illum_ctrl)>>6)&0x1)
++		{
++			gpio_set_value(ILLUM_PIN, 0);
++			gpio_set_value(ILLUM_RED_PIN, 1);
++			gpio_set_value(ILLUM_BLUE_PIN, 0);
++		}
++		else if (((*illum_ctrl)>>7)&0x1)
++		{
++			gpio_set_value(ILLUM_PIN, 0);
++			gpio_set_value(ILLUM_RED_PIN, 0);
++			gpio_set_value(ILLUM_BLUE_PIN, 1);
++		}
++		else
++		{
++			gpio_set_value(ILLUM_PIN, 1);
++			gpio_set_value(ILLUM_RED_PIN, 0);
++			gpio_set_value(ILLUM_BLUE_PIN, 0);
++		}
++
++		switch((*illum_ctrl)&0x03)
++		{
++		case 1:			// illum low level
++			IlluminationSetLevel(ILLUM_SET_LEVEL_LOW_PIN);		
++			break;
++		case 2:			// illum mid level
++			IlluminationSetLevel(ILLUM_SET_LEVEL_MID_PIN);
++			break;
++		case 3:			// illum high level
++			IlluminationSetLevel(ILLUM_SET_LEVEL_HIGH_PIN);
++			break;
++		default:
++			IlluminationSetLevel(ILLUM_SET_LEVEL_LOW_PIN);
++			break;
++		}
++    }
++    else                            //Illum off
++    {
++		gpio_set_value(ILLUM_PIN, 0);
++		gpio_set_value(ILLUM_RED_PIN, 0);
++		gpio_set_value(ILLUM_BLUE_PIN, 0);
++    }
++#endif
++    return error;
++}
++#endif
++
++static int sc0132gs_read_I2cRegs(struct v4l2_subdev *sd, TOMATO_I2C_regs *vals)
++{
++    int ret = -1;
++    int i;
++    struct regval_list *pregs = &(vals->regs);
++    for(i = 0; i < vals->count; i++)
++    {
++        unsigned char val;
++        ret = sc0132gs_read(sd, pregs->reg_num & 0xffff, &val);
++        if (ret < 0)
++            return ret;
++        pregs->value = val;
++        pregs++;
++    }
++    return 0;
++}
++
++static int sc0132gs_write_I2cRegs(struct v4l2_subdev *sd,const TOMATO_I2C_regs *vals)
++{
++    int ret;
++    int i;
++    struct regval_list *pregs = &(vals->regs);
++    for(i = 0; i < vals->count; i++)
++    {
++        ret = sc0132gs_write(sd, pregs->reg_num & 0xffff, (unsigned char)pregs->value);
++        //printk("[%s-%d]: 0x%02x, 0x%02x-----%p\n",__func__,__LINE__ ,pregs->reg_num, pregs->value,pregs);//dev_vdbg
++        if (ret < 0)
++            return ret;
++        pregs++;
++    }
++    return 0;
++}
++
++/**
++ * sc0132gs_ioctl - IOCTL handler
++ * @sd: device object
++ * @cmd: Command
++ * @arg: arguments
++ */
++static long sc0132gs_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
++{
++    struct i2c_client  *client = v4l2_get_subdevdata(sd);
++    //struct sc031gs_priv *priv = to_sc031gs(client);
++    int ret = 0;
++    long powerstate = 0;
++    long illum_ctrl = 0;
++    TOMATO_I2C_regs *vals = (TOMATO_I2C_regs *)arg;
++    /*struct regval_list sc031gs_powerstatus_regs = {0x0100,0};*/
++
++    unsigned char val[2];
++    uint16_t regVal;
++    switch (cmd)
++    {
++        case TOMATO_VIDIOC_IIC_WRITE:
++            ret = sc0132gs_write_I2cRegs(sd,vals);
++            break;
++        case TOMATO_VIDIOC_IIC_READ:
++            ret = sc0132gs_read_I2cRegs(sd,vals);
++            break;
++        case VIDIOC_S_SENSORPWRSTATE:
++            memcpy(&powerstate,arg,sizeof(long));//copy_from_usr
++            ret = sc0132gs_power(sd, powerstate?0:1);
++            break;
++        case VIDIOC_G_SENSORPWRSTATE:
++            //ret = ar0144_read(sd,AR0144_RESET_REG, val);
++            //regVal=(val[0]<<8)|val[1];
++            //if(regVal&0x0004) 
++            //    powerstate = 0;
++            //else 
++            powerstate = 0;
++            memcpy(arg,&powerstate,sizeof(long));//copy_to_usr
++            ret = 0;
++            break;
++#if defined(ILLUM_WORKAROUND)||defined(AIMER_WORKAROUND)
++        case VIDIOC_S_ILLUMCTRL:
++            memcpy(&illum_ctrl,arg,sizeof(long));//copy_from_usr
++            //Illum_value = illum_ctrl;
++            IlluminationSetControl(&illum_ctrl); 
++            ret = 0;
++            break;
++#endif
++        default:
++            //dev_info(&client->dev, "no V4L2 CID: 0x%x \n", cmd);
++            ret = -EINVAL;
++            break;
++    }
++    return ret;
++}
++
++int sc0132gs_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct sc0132gs_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops sc0132gs_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = sc0132gs_g_register,
++	.s_register = sc0132gs_s_register,
++#endif
++	.ioctl = sc0132gs_ioctl,
++};
++
++static const struct v4l2_subdev_video_ops sc0132gs_video_ops = {
++	.s_stream = sc0132gs_s_stream,
++	.g_frame_interval = sc0132gs_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops sc0132gs_pad_ops = {
++	//.enum_frame_interval = sc0132gs_enum_frame_interval,
++	//.num_frame_size = sc0132gs_enum_frame_size,
++	//.enum_mbus_code = sc0132gs_enum_mbus_code,
++	.set_fmt = sc0132gs_set_fmt,
++	.get_fmt = sc0132gs_get_fmt,
++};
++
++static const struct v4l2_subdev_ops sc0132gs_ops = {
++	.core = &sc0132gs_core_ops,
++	.video = &sc0132gs_video_ops,
++	.pad = &sc0132gs_pad_ops,
++};
++
++
++/* ----------------------------------------------------------------------- */
++
++static int sc0132gs_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_fract tpf;
++	struct v4l2_subdev *sd;
++	struct sc0132gs_info *info;
++	struct i2c_adapter *i2c_adap;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++	int tmp;
++
++	dev_info(&client->dev, "sc0132gs probing\n");
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	printk("[%d] gpio=%d\n", __LINE__, gpio);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,vcc-en-gpio", 0, &flags);
++	printk("[%d] gpio=%d\n", __LINE__, gpio);
++	if(gpio_is_valid(gpio)) {
++		info->vcc_en.pin = gpio;
++		info->vcc_en.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutp-gpio", 0, &flags);
++	printk("[%d] gpio=%d\n", __LINE__, gpio);
++	if(gpio_is_valid(gpio)) {
++		info->ircutp.pin = gpio;
++		info->ircutp.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutn-gpio", 0, &flags);
++	printk("[%d] gpio=%d\n", __LINE__, gpio);
++	if(gpio_is_valid(gpio)) {
++		info->ircutn.pin = gpio;
++		info->ircutn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	v4l2_i2c_subdev_init(sd, client, &sc0132gs_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++	info->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++
++	sc0132gs_power(sd, 1);
++	msleep(10);
++	sc0132gs_reset(sd, 1);
++#if 1
++	/* Make sure it's an sc0132gs */
++	ret = sc0132gs_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an sc0132gs chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &sc0132gs_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &sc0132gs_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &sc0132gs_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &sc0132gs_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &sc0132gs_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &sc0132gs_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 261773, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &sc0132gs_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1520 - 4, 1, 1000);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->win = &sc0132gs_win_sizes[0];
++	sc0132gs_write_array(sd, info->win->regs);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++    #if defined(ILLUM_WORKAROUND)||defined(AIMER_WORKAROUND)
++        i2c_adap = i2c_get_adapter(2);
++        if (i2c_adap)
++        {
++			led_ic_client = i2c_new_device(i2c_adap, &aw9110b_info);
++			if (NULL == led_ic_client) {
++				printk(KERN_ERR "%s i2c_new_device is Err!\n", __func__);
++				return 0;
++			}
++			i2c_put_adapter(i2c_adap);
++		}
++		RequestIlluminationRelatedGpioPins(client);
++    #endif
++	
++	dev_info(&client->dev, "sc0132gs Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int sc0132gs_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct sc0132gs_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id sc0132gs_id[] = {
++	{ "sc0132gs", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, sc0132gs_id);
++
++static const struct of_device_id sc0132gs_of_match[] = {
++	{.compatible = "ovti,sc0132gs", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov2640_of_match);
++
++
++static struct i2c_driver sc0132gs_driver = {
++	.driver = {
++		.name	= "sc0132gs",
++		.of_match_table = of_match_ptr(sc0132gs_of_match),
++	},
++	.probe		= sc0132gs_probe,
++	.remove		= sc0132gs_remove,
++	.id_table	= sc0132gs_id,
++};
++
++module_i2c_driver(sc0132gs_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for OmniVision sc0132gs sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/sc031gs.c b/module_drivers/drivers/media/i2c/ingenic-isp/sc031gs.c
+new file mode 100644
+index 000000000..035252766
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/sc031gs.c
+@@ -0,0 +1,2226 @@
++/*
++ * A V4L2 driver for OmniVision SC031GS cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++
++#include <isp-sensor.h>
++
++#define SC031GS_CHIP_ID_H       (0x00)
++#define SC031GS_CHIP_ID_M       (0x31)
++#define SC031GS_CHIP_ID_L       (0x01)
++#define SC031GS_REG_END		0xffff
++#define SC031GS_REG_DELAY	0xfffe
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct sc031gs_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct sc031gs_gpio {
++	int pin;
++	int active_level;
++};
++
++struct sc031gs_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct sc031gs_win_size *win;
++
++	struct sc031gs_gpio reset;
++	struct sc031gs_gpio vcc_en;
++	struct sc031gs_gpio ircutp;
++	struct sc031gs_gpio ircutn;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++struct again_lut sc031gs_again_lut[] = {
++
++	{0x80, 0},
++	{0x88, 5731},
++	{0x90, 11136},
++	{0x98, 16248},
++	{0xa0, 21097},
++	{0xa8, 25710},
++	{0xb0, 30109},
++	{0xb8, 34312},
++	{0xc0, 38336},
++	{0xc8, 42195},
++	{0xd0, 45904},
++	{0xd8, 49472},
++	{0xe0, 52910},
++	{0xe8, 56228},
++	{0xf0, 59433},
++	{0xf8, 62534},
++	{0x178, 65536},
++	{0x17c, 68445},
++	{0x180, 71267},
++	{0x184, 74008},
++	{0x188, 76672},
++	{0x18c, 79262},
++	{0x190, 81784},
++	{0x194, 84240},
++	{0x198, 86633},
++	{0x19c, 88968},
++	{0x1a0, 91246},
++	{0x1a4, 93471},
++	{0x1a8, 95645},
++	{0x1ac, 97770},
++	{0x1b0, 99848},
++	{0x1b4, 101881},
++	{0x1b8, 103872},
++	{0x1bc, 105821},
++	{0x1c0, 107731},
++	{0x1c4, 109604},
++	{0x1c8, 111440},
++	{0x1cc, 113241},
++	{0x1d0, 115008},
++	{0x1d4, 116743},
++	{0x1d8, 118446},
++	{0x1dc, 120120},
++	{0x1e0, 121764},
++	{0x1e4, 123380},
++	{0x1e8, 124969},
++	{0x1ec, 126532},
++	{0x1f0, 128070},
++	{0x1f4, 129583},
++	{0x374, 131072},
++	{0x376, 132537},
++	{0x378, 133981},
++	{0x37a, 135403},
++	{0x37c, 136803},
++	{0x37e, 138184},
++	{0x380, 139544},
++	{0x382, 140885},
++	{0x384, 142208},
++	{0x386, 143512},
++	{0x388, 144798},
++	{0x38a, 146067},
++	{0x38c, 147320},
++	{0x38e, 148556},
++	{0x390, 149776},
++	{0x392, 150980},
++	{0x394, 152169},
++	{0x396, 153344},
++	{0x398, 154504},
++	{0x39a, 155650},
++	{0x39c, 156782},
++	{0x39e, 157901},
++	{0x3a0, 159007},
++	{0x3a2, 160100},
++	{0x3a4, 161181},
++	{0x3a6, 162249},
++	{0x3a8, 163306},
++	{0x3aa, 164350},
++	{0x3ac, 165384},
++	{0x3ae, 166406},
++	{0x3b0, 167417},
++	{0x3b2, 168418},
++	{0x3b4, 169408},
++	{0x3b6, 170387},
++	{0x3b8, 171357},
++	{0x3ba, 172317},
++	{0x3bc, 173267},
++	{0x3be, 174208},
++	{0x3c0, 175140},
++	{0x3c2, 176062},
++	{0x3c4, 176976},
++	{0x3c6, 177880},
++	{0x3c8, 178777},
++	{0x3ca, 179664},
++	{0x3cc, 180544},
++	{0x3ce, 181415},
++	{0x3d0, 182279},
++	{0x3d2, 183134},
++	{0x3d4, 183982},
++	{0x3d6, 184823},
++	{0x3d8, 185656},
++	{0x3da, 186482},
++	{0x3dc, 187300},
++	{0x3de, 188112},
++	{0x3e0, 188916},
++	{0x3e2, 189714},
++	{0x3e4, 190505},
++	{0x3e6, 191290},
++	{0x3e8, 192068},
++	{0x3ea, 192840},
++	{0x3ec, 193606},
++	{0x3ee, 194365},
++	{0x3f0, 195119},
++	{0x3f2, 195866},
++	{0x778, 196608},
++	{0x779, 197343},
++	{0x77a, 198073},
++	{0x77b, 198798},
++	{0x77c, 199517},
++	{0x77d, 200230},
++	{0x77e, 200939},
++	{0x77f, 201642},
++	{0x780, 202339},
++	{0x781, 203032},
++	{0x782, 203720},
++	{0x783, 204402},
++	{0x784, 205080},
++	{0x785, 205753},
++	{0x786, 206421},
++	{0x787, 207085},
++	{0x788, 207744},
++	{0x789, 208398},
++	{0x78a, 209048},
++	{0x78b, 209693},
++	{0x78c, 210334},
++	{0x78d, 210971},
++	{0x78e, 211603},
++	{0x78f, 212232},
++	{0x790, 212856},
++	{0x791, 213476},
++	{0x792, 214092},
++	{0x793, 214704},
++	{0x794, 215312},
++	{0x795, 215916},
++	{0x796, 216516},
++	{0x797, 217113},
++	{0x798, 217705},
++	{0x799, 218294},
++	{0x79a, 218880},
++	{0x79b, 219462},
++	{0x79c, 220040},
++	{0x79d, 220615},
++	{0x79e, 221186},
++	{0x79f, 221754},
++	{0x7a0, 222318},
++	{0x7a1, 222880},
++	{0x7a2, 223437},
++	{0x7a3, 223992},
++	{0x7a4, 224543},
++	{0x7a5, 225091},
++	{0x7a6, 225636},
++	{0x7a7, 226178},
++	{0x7a8, 226717},
++	{0x7a9, 227253},
++	{0x7aa, 227785},
++	{0x7ab, 228315},
++	{0x7ac, 228842},
++	{0x7ad, 229365},
++	{0x7ae, 229886},
++	{0x7af, 230404},
++	{0x7b0, 230920},
++	{0x7b1, 231432},
++	{0x7b2, 231942},
++	{0x7b3, 232449},
++	{0x7b4, 232953},
++	{0x7b5, 233455},
++	{0x7b6, 233954},
++	{0x7b7, 234450},
++	{0x7b8, 234944},
++	{0x7b9, 235435},
++	{0x7ba, 235923},
++	{0x7bb, 236410},
++	{0x7bc, 236893},
++	{0x7bd, 237374},
++	{0x7be, 237853},
++	{0x7bf, 238329},
++	{0x7c0, 238803},
++	{0x7c1, 239275},
++	{0x7c2, 239744},
++	{0x7c3, 240211},
++	{0x7c4, 240676},
++	{0x7c5, 241138},
++	{0x7c6, 241598},
++	{0x7c7, 242056},
++	{0x7c8, 242512},
++	{0x7c9, 242965},
++	{0x7ca, 243416},
++	{0x7cb, 243865},
++	{0x7cc, 244313},
++	{0x7cd, 244757},
++	{0x7ce, 245200},
++	{0x7cf, 245641},
++	{0x7d0, 246080},
++	{0x7d1, 246517},
++	{0x7d2, 246951},
++	{0x7d3, 247384},
++	{0x7d4, 247815},
++	{0x7d5, 248243},
++	{0x7d6, 248670},
++	{0x7d7, 249095},
++	{0x7d8, 249518},
++	{0x7d9, 249939},
++	{0x7da, 250359},
++	{0x7db, 250776},
++	{0x7dc, 251192},
++	{0x7dd, 251606},
++	{0x7de, 252018},
++	{0x7df, 252428},
++	{0x7e0, 252836},
++	{0x7e1, 253243},
++	{0x7e2, 253648},
++	{0x7e3, 254051},
++	{0x7e4, 254452},
++	{0x7e5, 254852},
++	{0x7e6, 255250},
++	{0x7e7, 255647},
++	{0x7e8, 256041},
++	{0x7e9, 256435},
++	{0x7ea, 256826},
++	{0x7eb, 257216},
++	{0x7ec, 257604},
++	{0x7ed, 257991},
++	{0x7ee, 258376},
++	{0x7ef, 258760},
++	{0x7f0, 259142},
++	{0x7f1, 259522},
++	{0x7f2, 259901},
++	{0x7f3, 260279},
++	{0x7f4, 260655},
++	{0x7f5, 261029},
++	{0x7f6, 261402},
++	{0x7f7, 261773},
++};
++
++static inline struct sc031gs_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct sc031gs_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct sc031gs_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++static struct regval_list sc031gs_init_regs_640_480_60fps_mipi[] = {
++	//[ParaList]
++	{0x0103,0x01},
++	{0x0100,0x00},
++
++
++	//close mipi
++	//{0x3018,0x1f}, 
++	//{0x3019,0xff},
++	//{0x301c,0xb4},
++
++
++
++	//for mipi
++	{0x4603,0x00},//[0] fifo dvp read en
++	{0x3000,0x00},//
++	{0x3001,0x00},//pad dvp en
++	{0x303f,0x01},//[7] pll pclk dis
++
++	{0x3018,0x13},//[7:5] lane num = [7:5] + 1 , [3:2] pd_mipi
++
++	{0x3031,0x0a},//[3:0] mipi bit num
++	{0x3037,0x20},//[6:5] phy bit num 00~8bit 01~10bit 10~12bit
++	{0x301c,0x78},//[7] pclk_dvp_en [6] pclk_mipi_en [3] rst_dvp [2] rst_mipi
++	{0x3019,0xfe},//[3:0] lane_disable
++
++
++	{0x363c,0x08},
++	{0x3630,0x82},
++
++
++	{0x3638,0x0f}, //ramp offset
++	{0x3639,0x08}, //ramp_vref
++	{0x335b,0x80}, //pix_samp all high
++	//{0x3323,0x80}, //[7] srs all1  col fpn /with vln all 1 pix fpn
++
++	{0x3636,0x25},
++	{0x3640,0x02},
++	{0x3306,0x38},
++
++	{0x3304,0x48},
++	{0x3389,0x01}, //offset en
++	{0x3385,0x31}, //integ en
++	{0x330c,0x18}, //0109
++	{0x3315,0x38},
++	{0x3306,0x28},
++	{0x3309,0x68},
++	{0x3387,0x51}, //integ_en
++	{0x3306,0x48},
++
++
++	//0101
++	{0x3366,0x04}, //sb over count up
++
++	{0x335f,0x80}, //avdd samp all high
++	{0x363a,0x00}, // psr
++
++	{0x3622,0x01},
++	{0x3633,0x62},
++
++	//bsi
++	{0x36f9,0x20},
++
++	//{0x3250,0xf0},
++	{0x3637,0x80},
++	{0x363d,0x04},
++	{0x3e06,0x00},
++	{0x363c,0x48},
++
++
++	{0x320c,0x03},
++	{0x320e,0x0e},
++	{0x320f,0xa8},
++	{0x3306,0x38},
++	{0x330b,0xb6},
++
++
++	//{0x3621,0x90},
++	{0x36f9,0x24},
++
++
++	//0104
++	{0x363b,0x4a},
++	{0x3366,0x02},
++
++	//precharge
++	{0x3316,0x78},
++	{0x3344,0x74},
++	{0x3335,0x74},
++	{0x332f,0x70},
++	{0x332d,0x6c},
++	{0x3329,0x6c},
++
++	//0105
++	//{0x3250,0xff},
++
++	//1.24
++	{0x363c,0x08},
++	{0x3630,0x81},
++
++	//{0x3314,0x28}, //for offset cancel
++	//{0x3317,0x23},
++	//{0x3366,0x04},
++
++	{0x3366,0x06},
++
++	{0x3314,0x3a},
++	{0x3317,0x28},
++
++	//0130
++	{0x3622,0x05}, //blksun
++	{0x363d,0x00},
++	{0x3637,0x86},
++
++	{0x3e01,0x62},
++	{0x3633,0x52},
++	{0x3630,0x86},
++	{0x3306,0x4c},
++	{0x330b,0xa0},
++
++	//0131
++	{0x3631,0x48},
++
++	//0201
++	{0x33b1,0x03}, // chis position
++	{0x33b2,0x06}, //[3:2]=chis_length [1:0] +1=trans_length
++	{0x320c,0x02},
++	{0x320e,0x02},
++	{0x320f,0x0d},
++	{0x3e01,0x20},
++	{0x3e02,0x20},
++
++	//precharge
++	{0x3316,0x48},
++	{0x3344,0x44},
++	{0x3335,0x44},
++	{0x332f,0x40},
++	{0x332d,0x3c},
++	{0x3329,0x3c},
++
++	{0x3310,0x10}, //tx width
++
++	{0x3637,0x87},
++	{0x363e,0xf8},
++
++
++	//power save mode  0201B
++
++	{0x3254,0x02},
++	{0x3255,0x07},  //{3204,3205}={3260,3261}+1
++
++	{0x3252,0x02},
++	{0x3253,0xa6},  // {3252,3253}={320e,320f}-5
++
++	{0x3250,0xc0},  //[5:4]sa1 [3:2] opbuf  [1:0] ramp 0724
++	{0x3251,0x02},  //[1] opbuf  [0] ramp
++
++	//0322
++	{0x330f,0x50},
++	{0x3630,0x46},
++
++	//0324
++	{0x3621,0xa2}, //aa?
++
++	//0329
++	{0x3621,0xa0},
++	{0x4500,0x59}, //fifo delay
++
++	//0404
++	{0x3637,0x88}, //blksun margin
++	{0x3908,0x81}, //for digital gain
++
++	{0x3640,0x00},
++	{0x3641,0x02},
++
++	{0x363c,0x05}, //only for vt++ com1 dvp sample
++	{0x363b,0x4c},
++
++	//72MPCLK 183fps
++
++	{0x36e9,0x40},
++	{0x36ea,0x36},
++	{0x36ed,0x13},
++
++	{0x36f9,0x04},
++	{0x36fa,0x38},
++	{0x330b,0x80},
++
++
++	//{0x3304,0x40},
++	//{0x3389,0x01}, //offset en
++	//{0x3385,0x31}, //integ en
++	//{0x330c,0x10}, //0109
++	//{0x3315,0x30},
++	//{0x3309,0x60},
++	//{0x3387,0x51}, //integ_en
++	//{0x3306,0x50},
++
++	{0x3640,0x00},
++	{0x3641,0x01},
++
++	//0502
++	{0x3d08,0x00},
++	{0x3306,0x48},
++	{0x3621,0xa4},
++	{0x300f,0x0f},
++
++
++	//0612
++	{0x4837, 0x1b},  //0x4837=2000/PCLK
++	{0x4809, 0x01}, //clock lane lp initialized to 11
++
++	//0622  24M input 72MPCLK 120fps
++	{0x363b,0x48},
++	{0x363c,0x06},
++	{0x36e9,0x00},
++	{0x36ea,0x3b},
++	{0x36eb,0x0e},
++	{0x36ec,0x0e},
++	{0x36ed,0x33},
++	{0x36f9,0x00},
++	{0x36fa,0x3a},
++	{0x36fc,0x01},
++#if 0
++	{0x320c,0x03}, //for high temp more margin
++	{0x320d,0x6e},
++	{0x320e,0x02},
++	{0x320f,0xab}, //120fps
++#else
++	{0x320c,0x04}, //for high temp more margin
++	{0x320d,0x8e},
++	{0x320e,0x03},
++	{0x320f,0xeb}, //60fps
++#endif
++
++
++#if 0
++	{0x3208,0x00},
++	{0x3209,0x80},
++	{0x320a,0x00},
++	{0x320b,0x60}, //128*96
++#endif
++
++	{0x330b,0x80},
++	{0x330f,0x50},
++
++	{0x3637,0x89}, //blksun margin
++
++	{0x3641,0x01}, //0x01 for 2.8V dovdd 0x02 for 1.8V DOVDD
++
++	//0625 for 70C 4ms 16X gain
++	{0x4501,0xc4},
++	{0x5011,0x01},
++	{0x3908,0x21},
++	{0x3e01,0x01},
++	{0x3e02,0xa0},
++	{0x3306,0x38},
++	{0x330b,0xe0}, //high temp [a0,f0]
++	{0x330f,0x20},
++
++	//0626
++	{0x3d08,0x01},
++
++	//0724
++	{0x5011,0x00},
++	{0x3e06,0x0c},
++	{0x3908,0x91},
++
++	//{0x3314,0x3a}, 
++	//{0x3317,0x20},
++	{0x3314,0x1e},
++	{0x3317,0x10}, //gain
++
++	//st light
++	{0x3635,0x18},
++
++	//  reduce minimum precharge
++	{0x3316,0x40},
++	{0x3344,0x3c},
++	{0x3335,0x3c},
++	{0x332f,0x38},
++	{0x332d,0x34},
++	{0x3329,0x34},
++	//20180829
++	{0x3624,0x47},
++
++	//20181101
++	{0x3220,0x10},//[1:0] vflip blc����
++
++	//20181106
++	{0x3635,0x18},
++
++	{0x0100,0x01}, //72M sysclk 576M cntclk
++
++
++
++	{0x4418,0x08},
++	{0x4419,0x8e}, //20190222 cover avdd 2.6V-3.0V
++
++//	{0x0100,0x01}, //72M sysclk 576M cntclk
++
++
++	/*
++	//[gain<2]
++	{0x3314,0x1e},//0222
++	{0x3317,0x10},
++	//[4>gain>=2]
++	{0x3314,0x4f}, //0222
++	{0x3317,0x0f}, //0625
++	//[gain>=4]
++	{0x3314,0x4f}, //0222
++	{0x3317,0x0f}, //0625
++
++	//[half count_clk test]
++	{0x36f9,0x20},
++	{0x3304,0x40},
++	{0x3389,0x01}, //offset en
++	{0x3385,0x31}, //integ en
++	{0x330c,0x18}, //0109
++	{0x3315,0x38},
++	{0x3306,0x28},
++	{0x3309,0x60},
++	{0x3387,0x51}, //integ_en
++	{0x3306,0x48},
++
++	//[noise_test]
++	{0x3324,0x10},
++	{0x3907,0x04},
++	{0x3e06,0x03},
++
++	//[dark current test]
++	{0x3e01,0xea},
++	{0x3e02,0x10},
++	{0x3e06,0x03},
++	{0x3902,0x05},
++	{0x3909,0x0c},
++	{0x3e08,0x1f},
++	{0x3622,0x01},
++
++	//[pos offset]
++	{0x3314,0x34},
++	{0x3317,0x29},
++
++	//[precharge test]
++	{0x3e09,0x1f},
++	{0x3e08,0x1f},
++	{0x3e06,0x03},
++	{0x3902,0x05},
++	{0x3909,0x0d},
++	{0x390a,0x80},
++
++
++	//[pls test] //AF=2.6
++	{0x4419,0x8e},
++	{0x3630,0x66},
++	{0x3902,0x05},
++	{0x3909,0x0f},
++	{0x390a,0x80},
++	{0x3314,0x4a},
++	{0x3317,0x0e},
++	{0x320e,0x10},
++	//{0x3907,0x04},
++	{0x3e01,0x00},
++	{0x3e02,0x20},
++	{0x320c,0x12},
++	{0x320d,0xee},
++	*/
++//	{0x4501,0xac},
++//	{0x3902,0x05},
++//	{0x3e06,0x03},
++	{SC031GS_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list sc031gs_init_regs_320_240_60fps_mipi[] = {
++	//[ParaList]
++	{0x0103,0x01},
++	{0x0100,0x00},
++
++
++	//close mipi
++	//{0x3018,0x1f}, 
++	//{0x3019,0xff},
++	//{0x301c,0xb4},
++
++
++
++	//for mipi
++	{0x4603,0x00},//[0] fifo dvp read en
++	{0x3000,0x00},//
++	{0x3001,0x00},//pad dvp en
++	{0x303f,0x01},//[7] pll pclk dis
++
++	{0x3018,0x13},//[7:5] lane num = [7:5] + 1 , [3:2] pd_mipi
++
++	{0x3031,0x0a},//[3:0] mipi bit num
++	{0x3037,0x20},//[6:5] phy bit num 00~8bit 01~10bit 10~12bit
++	{0x301c,0x78},//[7] pclk_dvp_en [6] pclk_mipi_en [3] rst_dvp [2] rst_mipi
++	{0x3019,0xfe},//[3:0] lane_disable
++
++
++	{0x363c,0x08},
++	{0x3630,0x82},
++
++
++	{0x3638,0x0f}, //ramp offset
++	{0x3639,0x08}, //ramp_vref
++	{0x335b,0x80}, //pix_samp all high
++	//{0x3323,0x80}, //[7] srs all1  col fpn /with vln all 1 pix fpn
++
++	{0x3636,0x25},
++	{0x3640,0x02},
++	{0x3306,0x38},
++
++	{0x3304,0x48},
++	{0x3389,0x01}, //offset en
++	{0x3385,0x31}, //integ en
++	{0x330c,0x18}, //0109
++	{0x3315,0x38},
++	{0x3306,0x28},
++	{0x3309,0x68},
++	{0x3387,0x51}, //integ_en
++	{0x3306,0x48},
++
++
++	//0101
++	{0x3366,0x04}, //sb over count up
++
++	{0x335f,0x80}, //avdd samp all high
++	{0x363a,0x00}, // psr
++
++	{0x3622,0x01},
++	{0x3633,0x62},
++
++	//bsi
++	{0x36f9,0x20},
++
++	//{0x3250,0xf0},
++	{0x3637,0x80},
++	{0x363d,0x04},
++	{0x3e06,0x00},
++	{0x363c,0x48},
++
++
++	{0x320c,0x03},
++	{0x320e,0x0e},
++	{0x320f,0xa8},
++	{0x3306,0x38},
++	{0x330b,0xb6},
++
++
++	//{0x3621,0x90},
++	{0x36f9,0x24},
++
++
++	//0104
++	{0x363b,0x4a},
++	{0x3366,0x02},
++
++	//precharge
++	{0x3316,0x78},
++	{0x3344,0x74},
++	{0x3335,0x74},
++	{0x332f,0x70},
++	{0x332d,0x6c},
++	{0x3329,0x6c},
++
++	//0105
++	//{0x3250,0xff},
++
++	//1.24
++	{0x363c,0x08},
++	{0x3630,0x81},
++
++	//{0x3314,0x28}, //for offset cancel
++	//{0x3317,0x23},
++	//{0x3366,0x04},
++
++	{0x3366,0x06},
++
++	{0x3314,0x3a},
++	{0x3317,0x28},
++
++	//0130
++	{0x3622,0x05}, //blksun
++	{0x363d,0x00},
++	{0x3637,0x86},
++
++	{0x3e01,0x62},
++	{0x3633,0x52},
++	{0x3630,0x86},
++	{0x3306,0x4c},
++	{0x330b,0xa0},
++
++	//0131
++	{0x3631,0x48},
++
++	//0201
++	{0x33b1,0x03}, // chis position
++	{0x33b2,0x06}, //[3:2]=chis_length [1:0] +1=trans_length
++	{0x320c,0x02},
++	{0x320e,0x02},
++	{0x320f,0x0d},
++	{0x3e01,0x20},
++	{0x3e02,0x20},
++
++	//precharge
++	{0x3316,0x48},
++	{0x3344,0x44},
++	{0x3335,0x44},
++	{0x332f,0x40},
++	{0x332d,0x3c},
++	{0x3329,0x3c},
++
++	{0x3310,0x10}, //tx width
++
++	{0x3637,0x87},
++	{0x363e,0xf8},
++
++
++	//power save mode  0201B
++
++	{0x3254,0x02},
++	{0x3255,0x07},  //{3204,3205}={3260,3261}+1
++
++	{0x3252,0x02},
++	{0x3253,0xa6},  // {3252,3253}={320e,320f}-5
++
++	{0x3250,0xc0},  //[5:4]sa1 [3:2] opbuf  [1:0] ramp 0724
++	{0x3251,0x02},  //[1] opbuf  [0] ramp
++
++	//0322
++	{0x330f,0x50},
++	{0x3630,0x46},
++
++	//0324
++	{0x3621,0xa2}, //aa?
++
++	//0329
++	{0x3621,0xa0},
++	{0x4500,0x59}, //fifo delay
++
++	//0404
++	{0x3637,0x88}, //blksun margin
++	{0x3908,0x81}, //for digital gain
++
++	{0x3640,0x00},
++	{0x3641,0x02},
++
++	{0x363c,0x05}, //only for vt++ com1 dvp sample
++	{0x363b,0x4c},
++
++	//72MPCLK 183fps
++
++	{0x36e9,0x40},
++	{0x36ea,0x36},
++	{0x36ed,0x13},
++
++	{0x36f9,0x04},
++	{0x36fa,0x38},
++	{0x330b,0x80},
++
++
++	//{0x3304,0x40},
++	//{0x3389,0x01}, //offset en
++	//{0x3385,0x31}, //integ en
++	//{0x330c,0x10}, //0109
++	//{0x3315,0x30},
++	//{0x3309,0x60},
++	//{0x3387,0x51}, //integ_en
++	//{0x3306,0x50},
++
++	{0x3640,0x00},
++	{0x3641,0x01},
++
++	//0502
++	{0x3d08,0x00},
++	{0x3306,0x48},
++	{0x3621,0xa4},
++	{0x300f,0x0f},
++
++
++	//0612
++	{0x4837, 0x1b},  //0x4837=2000/PCLK
++	{0x4809, 0x01}, //clock lane lp initialized to 11
++
++	//0622  24M input 72MPCLK 120fps
++	{0x363b,0x48},
++	{0x363c,0x06},
++	{0x36e9,0x00},
++	{0x36ea,0x3b},
++	{0x36eb,0x0e},
++	{0x36ec,0x0e},
++	{0x36ed,0x33},
++	{0x36f9,0x00},
++	{0x36fa,0x3a},
++	{0x36fc,0x01},
++#if 0
++	{0x320c,0x03}, //for high temp more margin
++	{0x320d,0x6e},
++	{0x320e,0x02},
++	{0x320f,0xab}, //120fps
++#else
++	{0x320c,0x04}, //for high temp more margin
++	{0x320d,0x8e},
++	{0x320e,0x03},
++	{0x320f,0xeb}, //60fps
++#endif
++
++
++#if 1
++	{0x3208,0x01},
++	{0x3209,0x40},
++	{0x320a,0x00},
++	{0x320b,0xf0}, //320*240
++
++	{0x3210, 0x00},
++	{0x3211, 0xA0},
++	{0x3212, 0x00},
++	{0x3213, 0x78},
++#endif
++
++	{0x330b,0x80},
++	{0x330f,0x50},
++
++	{0x3637,0x89}, //blksun margin
++
++	{0x3641,0x01}, //0x01 for 2.8V dovdd 0x02 for 1.8V DOVDD
++
++	//0625 for 70C 4ms 16X gain
++	{0x4501,0xc4},
++	{0x5011,0x01},
++	{0x3908,0x21},
++	{0x3e01,0x0a},
++	{0x3e02,0x80}, //expo time
++	{0x3306,0x38},
++	{0x330b,0xe0}, //high temp [a0,f0]
++	{0x330f,0x20},
++
++	//0626
++	{0x3d08,0x01},
++
++	//0724
++	{0x5011,0x00},
++	{0x3e06,0x0c},
++	{0x3908,0x91},
++
++	//{0x3314,0x3a}, 
++	//{0x3317,0x20},
++	{0x3314,0x1e},
++	{0x3317,0x10}, //gain
++
++	//st light
++	{0x3635,0x18},
++
++	//  reduce minimum precharge
++	{0x3316,0x40},
++	{0x3344,0x3c},
++	{0x3335,0x3c},
++	{0x332f,0x38},
++	{0x332d,0x34},
++	{0x3329,0x34},
++	//20180829
++	{0x3624,0x47},
++
++	//20181101
++	{0x3220,0x10},//[1:0] vflip blc����
++
++	//20181106
++	{0x3635,0x18},
++
++	{0x0100,0x01}, //72M sysclk 576M cntclk
++
++
++
++	{0x4418,0x08},
++	{0x4419,0x8e}, //20190222 cover avdd 2.6V-3.0V
++
++//	{0x0100,0x01}, //72M sysclk 576M cntclk
++
++
++	/*
++	//[gain<2]
++	{0x3314,0x1e},//0222
++	{0x3317,0x10},
++	//[4>gain>=2]
++	{0x3314,0x4f}, //0222
++	{0x3317,0x0f}, //0625
++	//[gain>=4]
++	{0x3314,0x4f}, //0222
++	{0x3317,0x0f}, //0625
++
++	//[half count_clk test]
++	{0x36f9,0x20},
++	{0x3304,0x40},
++	{0x3389,0x01}, //offset en
++	{0x3385,0x31}, //integ en
++	{0x330c,0x18}, //0109
++	{0x3315,0x38},
++	{0x3306,0x28},
++	{0x3309,0x60},
++	{0x3387,0x51}, //integ_en
++	{0x3306,0x48},
++
++	//[noise_test]
++	{0x3324,0x10},
++	{0x3907,0x04},
++	{0x3e06,0x03},
++
++	//[dark current test]
++	{0x3e01,0xea},
++	{0x3e02,0x10},
++	{0x3e06,0x03},
++	{0x3902,0x05},
++	{0x3909,0x0c},
++	{0x3e08,0x1f},
++	{0x3622,0x01},
++
++	//[pos offset]
++	{0x3314,0x34},
++	{0x3317,0x29},
++
++	//[precharge test]
++	{0x3e09,0x1f},
++	{0x3e08,0x1f},
++	{0x3e06,0x03},
++	{0x3902,0x05},
++	{0x3909,0x0d},
++	{0x390a,0x80},
++
++
++	//[pls test] //AF=2.6
++	{0x4419,0x8e},
++	{0x3630,0x66},
++	{0x3902,0x05},
++	{0x3909,0x0f},
++	{0x390a,0x80},
++	{0x3314,0x4a},
++	{0x3317,0x0e},
++	{0x320e,0x10},
++	//{0x3907,0x04},
++	{0x3e01,0x00},
++	{0x3e02,0x20},
++	{0x320c,0x12},
++	{0x320d,0xee},
++	*/
++//	{0x4501,0xac},
++//	{0x3902,0x05},
++//	{0x3e06,0x03},
++	{SC031GS_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list sc031gs_init_regs_128_96_60fps_mipi[] = {
++	//[ParaList]
++	{0x0103,0x01},
++	{0x0100,0x00},
++
++
++	//close mipi
++	//{0x3018,0x1f},
++	//{0x3019,0xff},
++	//{0x301c,0xb4},
++
++
++
++	//for mipi
++	{0x4603,0x00},//[0] fifo dvp read en
++	{0x3000,0x00},//
++	{0x3001,0x00},//pad dvp en
++	{0x303f,0x01},//[7] pll pclk dis
++
++	{0x3018,0x13},//[7:5] lane num = [7:5] + 1 , [3:2] pd_mipi
++
++	{0x3031,0x0a},//[3:0] mipi bit num
++	{0x3037,0x20},//[6:5] phy bit num 00~8bit 01~10bit 10~12bit
++	{0x301c,0x78},//[7] pclk_dvp_en [6] pclk_mipi_en [3] rst_dvp [2] rst_mipi
++	{0x3019,0xfe},//[3:0] lane_disable
++
++
++	{0x363c,0x08},
++	{0x3630,0x82},
++
++
++	{0x3638,0x0f}, //ramp offset
++	{0x3639,0x08}, //ramp_vref
++	{0x335b,0x80}, //pix_samp all high
++	//{0x3323,0x80}, //[7] srs all1  col fpn /with vln all 1 pix fpn
++
++	{0x3636,0x25},
++	{0x3640,0x02},
++	{0x3306,0x38},
++
++	{0x3304,0x48},
++	{0x3389,0x01}, //offset en
++	{0x3385,0x31}, //integ en
++	{0x330c,0x18}, //0109
++	{0x3315,0x38},
++	{0x3306,0x28},
++	{0x3309,0x68},
++	{0x3387,0x51}, //integ_en
++	{0x3306,0x48},
++
++
++	//0101
++	{0x3366,0x04}, //sb over count up
++
++	{0x335f,0x80}, //avdd samp all high
++	{0x363a,0x00}, // psr
++
++	{0x3622,0x01},
++	{0x3633,0x62},
++
++	//bsi
++	{0x36f9,0x20},
++
++	//{0x3250,0xf0},
++	{0x3637,0x80},
++	{0x363d,0x04},
++	{0x3e06,0x00},
++	{0x363c,0x48},
++
++
++	{0x320c,0x03},
++	{0x320e,0x0e},
++	{0x320f,0xa8},
++	{0x3306,0x38},
++	{0x330b,0xb6},
++
++
++	//{0x3621,0x90},
++	{0x36f9,0x24},
++
++
++	//0104
++	{0x363b,0x4a},
++	{0x3366,0x02},
++
++	//precharge
++	{0x3316,0x78},
++	{0x3344,0x74},
++	{0x3335,0x74},
++	{0x332f,0x70},
++	{0x332d,0x6c},
++	{0x3329,0x6c},
++
++	//0105
++	//{0x3250,0xff},
++
++	//1.24
++	{0x363c,0x08},
++	{0x3630,0x81},
++
++	//{0x3314,0x28}, //for offset cancel
++	//{0x3317,0x23},
++	//{0x3366,0x04},
++
++	{0x3366,0x06},
++
++	{0x3314,0x3a},
++	{0x3317,0x28},
++
++	//0130
++	{0x3622,0x05}, //blksun
++	{0x363d,0x00},
++	{0x3637,0x86},
++
++	{0x3e01,0x62},
++	{0x3633,0x52},
++	{0x3630,0x86},
++	{0x3306,0x4c},
++	{0x330b,0xa0},
++
++	//0131
++	{0x3631,0x48},
++
++	//0201
++	{0x33b1,0x03}, // chis position
++	{0x33b2,0x06}, //[3:2]=chis_length [1:0] +1=trans_length
++	{0x320c,0x02},
++	{0x320e,0x02},
++	{0x320f,0x0d},
++	{0x3e01,0x20},
++	{0x3e02,0x20},
++
++	//precharge
++	{0x3316,0x48},
++	{0x3344,0x44},
++	{0x3335,0x44},
++	{0x332f,0x40},
++	{0x332d,0x3c},
++	{0x3329,0x3c},
++
++	{0x3310,0x10}, //tx width
++
++	{0x3637,0x87},
++	{0x363e,0xf8},
++
++
++	//power save mode  0201B
++
++	{0x3254,0x02},
++	{0x3255,0x07},  //{3204,3205}={3260,3261}+1
++
++	{0x3252,0x02},
++	{0x3253,0xa6},  // {3252,3253}={320e,320f}-5
++
++	{0x3250,0xc0},  //[5:4]sa1 [3:2] opbuf  [1:0] ramp 0724
++	{0x3251,0x02},  //[1] opbuf  [0] ramp
++
++	//0322
++	{0x330f,0x50},
++	{0x3630,0x46},
++
++	//0324
++	{0x3621,0xa2}, //aa?
++
++	//0329
++	{0x3621,0xa0},
++	{0x4500,0x59}, //fifo delay
++
++	//0404
++	{0x3637,0x88}, //blksun margin
++	{0x3908,0x81}, //for digital gain
++
++	{0x3640,0x00},
++	{0x3641,0x02},
++
++	{0x363c,0x05}, //only for vt++ com1 dvp sample
++	{0x363b,0x4c},
++
++	//72MPCLK 183fps
++
++	{0x36e9,0x40},
++	{0x36ea,0x36},
++	{0x36ed,0x13},
++
++	{0x36f9,0x04},
++	{0x36fa,0x38},
++	{0x330b,0x80},
++
++
++	//{0x3304,0x40},
++	//{0x3389,0x01}, //offset en
++	//{0x3385,0x31}, //integ en
++	//{0x330c,0x10}, //0109
++	//{0x3315,0x30},
++	//{0x3309,0x60},
++	//{0x3387,0x51}, //integ_en
++	//{0x3306,0x50},
++
++	{0x3640,0x00},
++	{0x3641,0x01},
++
++	//0502
++	{0x3d08,0x00},
++	{0x3306,0x48},
++	{0x3621,0xa4},
++	{0x300f,0x0f},
++
++
++	//0612
++	{0x4837, 0x1b},  //0x4837=2000/PCLK
++	{0x4809, 0x01}, //clock lane lp initialized to 11
++
++	//0622  24M input 72MPCLK 120fps
++	{0x363b,0x48},
++	{0x363c,0x06},
++	{0x36e9,0x00},
++	{0x36ea,0x3b},
++	{0x36eb,0x0e},
++	{0x36ec,0x0e},
++	{0x36ed,0x33},
++	{0x36f9,0x00},
++	{0x36fa,0x3a},
++	{0x36fc,0x01},
++#if 0
++	{0x320c,0x03}, //for high temp more margin
++	{0x320d,0x6e},
++	{0x320e,0x02},
++	{0x320f,0xab}, //120fps
++#else
++	{0x320c,0x04}, //for high temp more margin
++	{0x320d,0x8e},
++	{0x320e,0x03},
++	{0x320f,0xeb}, //60fps
++#endif
++
++
++#if 1
++	{0x3208,0x00},
++	{0x3209,0x80},
++	{0x320a,0x00},
++	{0x320b,0x60}, //128*96
++#endif
++
++	{0x330b,0x80},
++	{0x330f,0x50},
++
++	{0x3637,0x89}, //blksun margin
++
++	{0x3641,0x01}, //0x01 for 2.8V dovdd 0x02 for 1.8V DOVDD
++
++	//0625 for 70C 4ms 16X gain
++	{0x4501,0xc4},
++	{0x5011,0x01},
++	{0x3908,0x21},
++	{0x3e01,0x0a},
++	{0x3e02,0x80},
++	{0x3306,0x38},
++	{0x330b,0xe0}, //high temp [a0,f0]
++	{0x330f,0x20},
++
++	//0626
++	{0x3d08,0x01},
++
++	//0724
++	{0x5011,0x00},
++	{0x3e06,0x0c},
++	{0x3908,0x91},
++
++	//{0x3314,0x3a}, 
++	//{0x3317,0x20},
++	{0x3314,0x1e},
++	{0x3317,0x10}, //gain
++
++	//st light
++	{0x3635,0x18},
++
++	//  reduce minimum precharge
++	{0x3316,0x40},
++	{0x3344,0x3c},
++	{0x3335,0x3c},
++	{0x332f,0x38},
++	{0x332d,0x34},
++	{0x3329,0x34},
++	//20180829
++	{0x3624,0x47},
++
++	//20181101
++	{0x3220,0x10},//[1:0] vflip blc����
++
++	//20181106
++	{0x3635,0x18},
++
++	{0x0100,0x01}, //72M sysclk 576M cntclk
++
++
++
++	{0x4418,0x08},
++	{0x4419,0x8e}, //20190222 cover avdd 2.6V-3.0V
++
++//	{0x0100,0x01}, //72M sysclk 576M cntclk
++
++
++	/*
++	//[gain<2]
++	{0x3314,0x1e},//0222
++	{0x3317,0x10},
++	//[4>gain>=2]
++	{0x3314,0x4f}, //0222
++	{0x3317,0x0f}, //0625
++	//[gain>=4]
++	{0x3314,0x4f}, //0222
++	{0x3317,0x0f}, //0625
++
++	//[half count_clk test]
++	{0x36f9,0x20},
++	{0x3304,0x40},
++	{0x3389,0x01}, //offset en
++	{0x3385,0x31}, //integ en
++	{0x330c,0x18}, //0109
++	{0x3315,0x38},
++	{0x3306,0x28},
++	{0x3309,0x60},
++	{0x3387,0x51}, //integ_en
++	{0x3306,0x48},
++
++	//[noise_test]
++	{0x3324,0x10},
++	{0x3907,0x04},
++	{0x3e06,0x03},
++
++	//[dark current test]
++	{0x3e01,0xea},
++	{0x3e02,0x10},
++	{0x3e06,0x03},
++	{0x3902,0x05},
++	{0x3909,0x0c},
++	{0x3e08,0x1f},
++	{0x3622,0x01},
++
++	//[pos offset]
++	{0x3314,0x34},
++	{0x3317,0x29},
++
++	//[precharge test]
++	{0x3e09,0x1f},
++	{0x3e08,0x1f},
++	{0x3e06,0x03},
++	{0x3902,0x05},
++	{0x3909,0x0d},
++	{0x390a,0x80},
++
++
++	//[pls test] //AF=2.6
++	{0x4419,0x8e},
++	{0x3630,0x66},
++	{0x3902,0x05},
++	{0x3909,0x0f},
++	{0x390a,0x80},
++	{0x3314,0x4a},
++	{0x3317,0x0e},
++	{0x320e,0x10},
++	//{0x3907,0x04},
++	{0x3e01,0x00},
++	{0x3e02,0x20},
++	{0x320c,0x12},
++	{0x320d,0xee},
++	*/
++//	{0x4501,0xac},
++//	{0x3902,0x05},
++//	{0x3e06,0x03},
++	{SC031GS_REG_END, 0x00},	/* END MARKER */
++};
++
++
++/*
++ * the part of driver was fixed.
++ */
++
++static struct regval_list sc031gs_stream_on_mipi[] = {
++	{0x0100, 0x01},
++	{SC031GS_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list sc031gs_stream_off_mipi[] = {
++	//close mipi
++//	{0x3018,0x1f}, 
++//	{0x3019,0xff},
++//	{0x301c,0xb4},
++	{SC031GS_REG_END, 0x00},	/* END MARKER */
++};
++
++static int sc031gs_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct sc031gs_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret = 0;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int sc031gs_write(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char value)
++{
++	struct sc031gs_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3] = {(reg>>8)&0xff, reg&0xff, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 3,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int sc031gs_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != SC031GS_REG_END) {
++		if (vals->reg_num == SC031GS_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = sc031gs_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++/*
++ * Write a list of register settings; ff/ff stops the process.
++ */
++static int sc031gs_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != SC031GS_REG_END) {
++		if (vals->reg_num == SC031GS_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = sc031gs_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int sc031gs_power(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc031gs_info *info = to_state(sd);
++
++	if(val){
++		*(volatile unsigned int *)0xb0010230 &= ~(1 << 28);
++		*(volatile unsigned int *)0xb0010240 |= (1 << 28);
++//		gpio_direction_output(info->reset.pin, info->reset.active_level);
++	}else{
++		*(volatile unsigned int *)0xb0010230 |= (1 << 28);
++		*(volatile unsigned int *)0xb0010240 &= ~(1 << 28);
++//		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++	}
++	return 0;
++}
++
++static int sc031gs_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc031gs_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(10);
++	}
++	return 0;
++}
++
++static int sc031gs_ircut(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc031gs_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++	} else {
++		gpio_direction_output(info->ircutp.pin, !info->ircutp.active_level);
++		gpio_direction_output(info->ircutn.pin, !info->ircutn.active_level);
++		msleep(10);
++		gpio_direction_output(info->ircutp.pin, info->ircutp.active_level);
++	}
++	return 0;
++}
++
++static int sc031gs_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc031gs_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = sc031gs_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++
++static int sc031gs_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v = 0;
++	int ret;
++
++	ret = sc031gs_read(sd, 0x3107, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != SC031GS_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = sc031gs_read(sd, 0x3108, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != SC031GS_CHIP_ID_M)
++		return -ENODEV;
++	*ident = v;
++
++	ret = sc031gs_read(sd, 0x3109, &v);
++	pr_info("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != SC031GS_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	return 0;
++}
++
++
++static struct sc031gs_win_size sc031gs_win_sizes[] = {
++	{
++		.sensor_info.mipi_cfg.twidth		= 640,
++		.sensor_info.mipi_cfg.theight		= 480,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.fps			= 60 << 16 | 1,
++
++		.width		= 640,
++		.height		= 480,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= sc031gs_init_regs_640_480_60fps_mipi,
++	},
++	{
++		.sensor_info.mipi_cfg.twidth		= 320,
++		.sensor_info.mipi_cfg.theight		= 240,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.fps			= 60 << 16 | 1,
++
++		.width		= 320,
++		.height		= 240,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= sc031gs_init_regs_320_240_60fps_mipi,
++	},
++	{
++		.sensor_info.mipi_cfg.twidth		= 128,
++		.sensor_info.mipi_cfg.theight		= 96,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.sensor_info.fps			= 60 << 16 | 1,
++
++		.width		= 128,
++		.height		= 96,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= sc031gs_init_regs_128_96_60fps_mipi,
++	},
++};
++
++static int sc031gs_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_SC031GS_FMTS)
++		return -EINVAL;
++
++	code->code = sc031gs_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int sc031gs_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct sc031gs_format_struct *ovfmt;
++	struct sc031gs_win_size *wsize;
++	struct sc031gs_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int sc031gs_get_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct sc031gs_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	*(unsigned int *)fmt->reserved = &info->win->sensor_info;
++
++
++	//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++	//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int sc031gs_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc031gs_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc031gs_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc031gs_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int sc031gs_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int sc031gs_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(sc031gs_again_lut); i++) {
++		lut = &sc031gs_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(sc031gs_again_lut); i++) {
++		lut = &sc031gs_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++}
++
++static int sc031gs_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	/*
++	   struct sc031gs_info *info = to_state(sd);
++	   char v = 0;
++	   unsigned int reg_val = 0;
++
++
++	   ret += sc031gs_read(sd, 0x3509, &v);
++
++	   reg_val |= v;
++	   ret += sc031gs_read(sd, 0x3508, &v);
++	   reg_val |= v << 8;
++
++
++	 *value = regval_to_again(reg_val);
++	 */
++
++	return ret;
++}
++/*set analog gain db value, map value to sensor register.*/
++static int sc031gs_s_again(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++#if 0
++	struct sc031gs_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int i;
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(value);
++	}
++
++	ret += sc031gs_write(sd, 0x3509, (unsigned char)(reg_value & 0xff));
++	ret += sc031gs_write(sd, 0x3508, (unsigned char)((reg_value>>8) & 0xff));
++	if (ret < 0)
++		return ret;
++
++#endif
++	return ret;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int sc031gs_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc031gs_s_exp(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++	/*
++	   struct sc031gs_info *info = to_state(sd);
++
++	   ret += sc031gs_write(sd, 0x3502, ((unsigned char)(value & 0xf)) << 4);
++	   ret += sc031gs_write(sd, 0x3501, (unsigned char)((value >> 4) & 0xff));
++	   ret += sc031gs_write(sd, 0x3500, (unsigned char)((value >> 12) & 0xf));
++
++*/
++	return ret;
++}
++
++static int sc031gs_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct sc031gs_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++		case V4L2_CID_AUTOGAIN:
++			return sc031gs_g_gain(sd, &info->gain->val);
++		case V4L2_CID_ANALOGUE_GAIN:
++			return sc031gs_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int sc031gs_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct sc031gs_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++		case V4L2_CID_BRIGHTNESS:
++			return sc031gs_s_brightness(sd, ctrl->val);
++		case V4L2_CID_CONTRAST:
++			return sc031gs_s_contrast(sd, ctrl->val);
++		case V4L2_CID_VFLIP:
++			return sc031gs_s_vflip(sd, ctrl->val);
++		case V4L2_CID_HFLIP:
++			return sc031gs_s_hflip(sd, ctrl->val);
++		case V4L2_CID_AUTOGAIN:
++			/* Only set manual gain if auto gain is not explicitly
++			   turned on. */
++			if (!ctrl->val) {
++				/* sc031gs_s_gain turns off auto gain */
++				return sc031gs_s_gain(sd, info->gain->val);
++			}
++			return sc031gs_s_autogain(sd, ctrl->val);
++		case V4L2_CID_GAIN:
++			return sc031gs_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return sc031gs_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return sc031gs_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops sc031gs_ctrl_ops = {
++	.s_ctrl = sc031gs_s_ctrl,
++	.g_volatile_ctrl = sc031gs_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int sc031gs_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = sc031gs_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int sc031gs_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	sc031gs_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int sc031gs_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct sc031gs_info *info = to_state(sd);
++	int ret = 0;
++
++	if (enable) {
++
++		sc031gs_write_array(sd, info->win->regs);
++		sc031gs_s_again(sd, 100000);
++		ret = sc031gs_write_array(sd, sc031gs_stream_on_mipi);
++		pr_debug("sc031gs stream on\n");
++
++	}
++	else {
++		ret = sc031gs_write_array(sd, sc031gs_stream_off_mipi);
++		pr_debug("sc031gs stream off\n");
++	}
++	return ret;
++}
++
++int sc031gs_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct sc031gs_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops sc031gs_core_ops = {
++	.reset = sc031gs_reset,
++	.init = sc031gs_init,
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = sc031gs_g_register,
++	.s_register = sc031gs_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops sc031gs_video_ops = {
++	.s_stream = sc031gs_s_stream,
++	.g_frame_interval = sc031gs_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops sc031gs_pad_ops = {
++	//.enum_frame_interval = sc031gs_enum_frame_interval,
++	//.num_frame_size = sc031gs_enum_frame_size,
++	//.enum_mbus_code = sc031gs_enum_mbus_code,
++	.set_fmt = sc031gs_set_fmt,
++	.get_fmt = sc031gs_get_fmt,
++};
++
++static const struct v4l2_subdev_ops sc031gs_ops = {
++	.core = &sc031gs_core_ops,
++	.video = &sc031gs_video_ops,
++	.pad = &sc031gs_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int sc031gs_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_fract tpf;
++	struct v4l2_subdev *sd;
++	struct sc031gs_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++	int tmp;
++
++	dev_info(&client->dev, "sc031gs probing\n");
++
++	/*
++	*(volatile unsigned int *)0xb0010340 &= ~(3 << 30);
++
++	*(volatile unsigned int *)0xb0010010 &= ~(3 << 16);
++	*(volatile unsigned int *)0xb0010020 &= ~(3 << 16);
++	*(volatile unsigned int *)0xb0010030 &= ~(3 << 16);
++	*(volatile unsigned int *)0xb0010040 &= ~(3 << 16);
++
++//	*(volatile unsigned int *)0xb00100a0 |= (3 << 16);
++//	*(volatile unsigned int *)0xb00100b0 |= (3 << 16);
++//	*(volatile unsigned int *)0xb00100c0 |= (3 << 16);
++	*/
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	printk("[%d] gpio=%d\n", __LINE__, gpio);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,vcc-en-gpio", 0, &flags);
++	printk("[%d] gpio=%d\n", __LINE__, gpio);
++	if(gpio_is_valid(gpio)) {
++		info->vcc_en.pin = gpio;
++		info->vcc_en.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutp-gpio", 0, &flags);
++	printk("[%d] gpio=%d\n", __LINE__, gpio);
++	if(gpio_is_valid(gpio)) {
++		info->ircutp.pin = gpio;
++		info->ircutp.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,ircutn-gpio", 0, &flags);
++	printk("[%d] gpio=%d\n", __LINE__, gpio);
++	if(gpio_is_valid(gpio)) {
++		info->ircutn.pin = gpio;
++		info->ircutn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	v4l2_i2c_subdev_init(sd, client, &sc031gs_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	/*clk*/
++	info->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++
++	sc031gs_power(sd, 1);
++	msleep(10);
++	sc031gs_reset(sd, 1);
++#if 1
++	/* Make sure it's an sc031gs */
++	ret = sc031gs_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an sc031gs chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &sc031gs_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &sc031gs_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &sc031gs_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &sc031gs_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &sc031gs_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &sc031gs_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 261773, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &sc031gs_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1520 - 4, 1, 1000);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->win = &sc031gs_win_sizes[0];
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "sc031gs Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int sc031gs_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct sc031gs_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id sc031gs_id[] = {
++	{ "sc031gs", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, sc031gs_id);
++
++static const struct of_device_id sc031gs_of_match[] = {
++	{.compatible = "ovti,sc031gs", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov2640_of_match);
++
++
++static struct i2c_driver sc031gs_driver = {
++	.driver = {
++		.name	= "sc031gs",
++		.of_match_table = of_match_ptr(sc031gs_of_match),
++	},
++	.probe		= sc031gs_probe,
++	.remove		= sc031gs_remove,
++	.id_table	= sc031gs_id,
++};
++
++module_i2c_driver(sc031gs_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for OmniVision sc031gs sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/sc2232h.c b/module_drivers/drivers/media/i2c/ingenic-isp/sc2232h.c
+new file mode 100644
+index 000000000..0e9bdee60
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/sc2232h.c
+@@ -0,0 +1,1173 @@
++/*
++ * A V4L2 driver for OmniVision sc2232h cameras.
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++
++#include <isp-sensor.h>
++
++#define SC2232H_CHIP_ID_H       (0xcb)
++#define SC2232H_CHIP_ID_M       (0x07)
++#define SC2232H_CHIP_ID_L       (0x01)
++#define SC2232H_REG_END		0xffff
++#define SC2232H_REG_DELAY	0xfffe
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct sc2232h_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct sc2232h_gpio {
++	int pin;
++	int active_level;
++};
++
++struct sc2232h_info {
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct sc2232h_win_size *win;
++	struct sc2232h_gpio reset;
++
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++struct again_lut sc2232h_again_lut[] = {
++
++	{0x10, 0},
++	{0x11, 5731},
++	{0x12, 11136},
++	{0x13, 16248},
++	{0x14, 21097},
++	{0x15, 25710},
++	{0x16, 30109},
++	{0x17, 34312},
++	{0x18, 38336},
++	{0x19, 42195},
++	{0x1a, 45904},
++	{0x1b, 49472},
++	{0x1c, 52910},
++	{0x1d, 56228},
++	{0x1e, 59433},
++	{0x1f, 62534},
++	{0x110,	65536},
++	{0x111,	71267},
++	{0x112,	76672},
++	{0x113,	81784},
++	{0x114,	86633},
++	{0x115,	91246},
++	{0x116,	95645},
++	{0x117,	99848},
++	{0x118, 103872},
++	{0x119,	107731},
++	{0x11a,	111440},
++	{0x11b,	115008},
++	{0x11c,	118446},
++	{0x11d,	121764},
++	{0x11e,	124969},
++	{0x11f,	128070},
++	{0x310, 131072},
++	{0x311,	136803},
++	{0x312,	142208},
++	{0x313,	147320},
++	{0x314,	152169},
++	{0x315,	156782},
++	{0x316,	161181},
++	{0x317,	165384},
++	{0x318,	169408},
++	{0x319,	173267},
++	{0x31a,	176976},
++	{0x31b,	180544},
++	{0x31c,	183982},
++	{0x31d,	187300},
++	{0x31e,	190505},
++	{0x31f,	193606},
++	{0x710, 196608},
++	{0x711,	202339},
++	{0x712,	207744},
++	{0x713,	212856},
++	{0x714,	217705},
++	{0x715,	222318},
++	{0x716,	226717},
++	{0x717,	230920},
++	{0x718,	234944},
++	{0x719,	238803},
++	{0x71a,	242512},
++	{0x71b,	246080},
++	{0x71c,	249518},
++	{0x71d,	252836},
++	{0x71e,	256041},
++	/* {0x71f, 259142}, */
++};
++
++static inline struct sc2232h_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct sc2232h_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct sc2232h_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++static struct regval_list sc2232h_init_regs_1920_1080_25fps_mipi[] = {
++	{0x0103, 0x01},
++	{0x0100, 0x00},
++	{0x3034, 0x81},
++	{0x3039, 0xd4},
++	{0x3624, 0x08},
++	{0x337f, 0x03},
++	{0x3368, 0x04},
++	{0x3369, 0x00},
++	{0x336a, 0x00},
++	{0x336b, 0x00},
++	{0x3367, 0x08},
++	{0x330e, 0x30},
++	{0x3366, 0x7c},
++	{0x3302, 0x1f},
++	{0x3907, 0x00},
++	{0x3908, 0x11},
++	{0x335e, 0x01},
++	{0x335f, 0x03},
++	{0x337c, 0x04},
++	{0x337d, 0x06},
++	{0x33a0, 0x05},
++	{0x3633, 0x4f},
++	{0x3622, 0x06},
++	{0x3631, 0x84},
++	{0x366e, 0x08},
++	{0x3326, 0x00},
++	{0x3303, 0x20},
++	{0x3638, 0x1f},
++	{0x3636, 0x25},
++	{0x3625, 0x02},
++	{0x331b, 0x83},
++	{0x3333, 0x30},
++	{0x3635, 0xa0},
++	{0x363c, 0x05},
++	{0x3038, 0xff},
++	{0x3639, 0x09},
++	{0x3621, 0x28},
++	{0x3211, 0x0c},
++	{0x3320, 0x01},
++	{0x331e, 0x19},
++	{0x3620, 0x28},
++	{0x3309, 0x60},
++	{0x331f, 0x59},
++	{0x3308, 0x10},
++	{0x3f00, 0x07},
++	{0x33aa, 0x10},
++	{0x3677, 0x86},
++	{0x3678, 0x88},
++	{0x3679, 0x88},
++	{0x367e, 0x08},
++	{0x367f, 0x28},
++	{0x3670, 0x0c},
++	{0x3690, 0x33},
++	{0x3691, 0x11},
++	{0x3692, 0x43},
++	{0x369c, 0x08},
++	{0x369d, 0x28},
++	{0x360f, 0x01},
++	{0x3671, 0xc6},
++	{0x3672, 0x06},
++	{0x3673, 0x16},
++	{0x367a, 0x28},
++	{0x367b, 0x3f},
++	{0x3221, 0x80},
++	{0x3222, 0x29},
++	{0x3901, 0x02},
++	{0x3905, 0x98},
++	{0x3e1e, 0x34},
++	{0x3900, 0x19},
++	{0x391d, 0x04},
++	{0x391e, 0x00},
++	{0x3641, 0x01},
++	{0x3213, 0x04},
++	{0x3614, 0x80},
++	{0x363a, 0x9f},
++	{0x3630, 0x9c},
++	{0x3306, 0x48},
++	{0x330b, 0xcd},
++	{0x3018, 0x33},
++	{0x3031, 0x0a},
++	{0x3037, 0x20},
++	{0x3001, 0xfe},
++	{0x4603, 0x00},
++	{0x4827, 0x48},
++	{0x301c, 0x78},
++	{0x4809, 0x01},
++	{0x3314, 0x04},
++	{0x3933, 0x0a},
++	{0x3934, 0x18},
++	{0x3940, 0x60},
++	{0x3942, 0x02},
++	{0x3943, 0x1f},
++	{0x3960, 0xba},
++	{0x3961, 0xae},
++	{0x3966, 0xba},
++	{0x3980, 0xa0},
++	{0x3981, 0x40},
++	{0x3982, 0x18},
++	{0x3903, 0x08},
++	{0x3984, 0x08},
++	{0x3985, 0x20},
++	{0x3986, 0x50},
++	{0x3987, 0xb0},
++	{0x3988, 0x08},
++	{0x3989, 0x10},
++	{0x398a, 0x20},
++	{0x398b, 0x30},
++	{0x398c, 0x60},
++	{0x398d, 0x20},
++	{0x398e, 0x10},
++	{0x398f, 0x08},
++	{0x3990, 0x60},
++	{0x3991, 0x24},
++	{0x3992, 0x15},
++	{0x3993, 0x08},
++	{0x3994, 0x0a},
++	{0x3995, 0x20},
++	{0x3996, 0x38},
++	{0x3997, 0xa0},
++	{0x3998, 0x08},
++	{0x3999, 0x10},
++	{0x399a, 0x18},
++	{0x399b, 0x30},
++	{0x399c, 0x30},
++	{0x399d, 0x18},
++	{0x399e, 0x10},
++	{0x399f, 0x08},
++	{0x3637, 0x55},
++	{0x366f, 0x2c},
++	{0x5000, 0x06},
++	{0x5780, 0x7f},
++	{0x5781, 0x04},
++	{0x5782, 0x03},
++	{0x5783, 0x02},
++	{0x5784, 0x01},
++	{0x5785, 0x18},
++	{0x5786, 0x10},
++	{0x5787, 0x08},
++	{0x5788, 0x02},
++	{0x57a0, 0x00},
++	{0x57a1, 0x71},
++	{0x57a2, 0x01},
++	{0x57a3, 0xf1},
++	{0x395e, 0xc0},
++	{0x3962, 0x88},
++	{0x303a, 0xb3},
++	{0x303c, 0x0e},
++	{0x3035, 0x9b},
++	{0x320c, 0x08},
++	{0x320d, 0x20},
++	{0x320e, 0x05},
++	{0x320f, 0xdc},/*25fps*/
++	{0x3f04, 0x03},
++	{0x3f05, 0xec},
++	{0x3235, 0x09},
++	{0x3236, 0xc2},
++	{0x4837, 0x33},
++	{0x3802, 0x00},
++	{0x3963, 0x80},
++	{0x303b, 0x16},
++	{0x301f, 0x05},
++	{0x363b, 0x26},
++	{0x3902, 0xc5},
++	{0x3e00, 0x00},
++	{0x3e01, 0x9c},
++	{0x3e02, 0x00},
++	{0x3e03, 0x0b},
++	{0x3e06, 0x00},
++	{0x3e07, 0x80},
++	{0x3e08, 0x03},
++	{0x3e09, 0x10},
++	{0x3301, 0x12},
++	{0x3632, 0x08},
++	{0x3034, 0x01},
++	{0x3039, 0x24},
++
++	{SC2232H_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list sc2232h_init_regs_1920_1080_25fps_dvp[] = {
++	{0x0103, 0x01},
++	{0x0100, 0x00},
++	{0x3034, 0x81},
++	{0x3039, 0xd4},
++	{0x3018, 0x1f},
++	{0x3019, 0xff},
++	{0x301c, 0xb4},
++	{0x3624, 0x08},
++	{0x337f, 0x03},
++	{0x3368, 0x04},
++	{0x3369, 0x00},
++	{0x336a, 0x00},
++	{0x336b, 0x00},
++	{0x3367, 0x08},
++	{0x330e, 0x30},
++	{0x3366, 0x7c},
++	{0x3302, 0x1f},
++	{0x303f, 0x81},
++	{0x3907, 0x00},
++	{0x3908, 0x11},
++	{0x335e, 0x01},
++	{0x335f, 0x03},
++	{0x337c, 0x04},
++	{0x337d, 0x06},
++	{0x33a0, 0x05},
++	{0x3633, 0x4f},
++	{0x3622, 0x06},
++	{0x3631, 0x84},
++	{0x366e, 0x08},
++	{0x3326, 0x00},
++	{0x3303, 0x20},
++	{0x3638, 0x1f},
++	{0x3636, 0x25},
++	{0x3625, 0x02},
++	{0x331b, 0x83},
++	{0x3333, 0x30},
++	{0x3635, 0xa0},
++	{0x363c, 0x05},
++	{0x3038, 0xff},
++	{0x3639, 0x09},
++	{0x3621, 0x28},
++	{0x3211, 0x0c},
++	{0x3320, 0x01},
++	{0x331e, 0x19},
++	{0x3620, 0x28},
++	{0x3309, 0x60},
++	{0x331f, 0x59},
++	{0x3308, 0x10},
++	{0x3f00, 0x07},
++	{0x33aa, 0x10},
++	{0x3677, 0x86},
++	{0x3678, 0x88},
++	{0x3679, 0x88},
++	{0x367e, 0x08},
++	{0x367f, 0x28},
++	{0x3670, 0x0c},
++	{0x3690, 0x33},
++	{0x3691, 0x11},
++	{0x3692, 0x43},
++	{0x369c, 0x08},
++	{0x369d, 0x28},
++	{0x360f, 0x01},
++	{0x3671, 0xc6},
++	{0x3672, 0x06},
++	{0x3673, 0x16},
++	{0x367a, 0x28},
++	{0x367b, 0x3f},
++	{0x3221, 0x80},
++	{0x3222, 0x29},
++	{0x3901, 0x02},
++	{0x3905, 0x98},
++	{0x3e1e, 0x34},
++	{0x3900, 0x19},
++	{0x391d, 0x04},
++	{0x391e, 0x00},
++	{0x3641, 0x01},
++	{0x3213, 0x04},
++	{0x3614, 0x80},
++	{0x363a, 0x9f},
++	{0x3630, 0x9c},
++	{0x3306, 0x48},
++	{0x330b, 0xcd},
++	{0x3314, 0x04},
++	{0x3933, 0x0a},
++	{0x3934, 0x18},
++	{0x3940, 0x60},
++	{0x3942, 0x02},
++	{0x3943, 0x1f},
++	{0x3960, 0xba},
++	{0x3961, 0xae},
++	{0x3966, 0xba},
++	{0x3980, 0xa0},
++	{0x3981, 0x40},
++	{0x3982, 0x18},
++	{0x3903, 0x08},
++	{0x3984, 0x08},
++	{0x3985, 0x20},
++	{0x3986, 0x50},
++	{0x3987, 0xb0},
++	{0x3988, 0x08},
++	{0x3989, 0x10},
++	{0x398a, 0x20},
++	{0x398b, 0x30},
++	{0x398c, 0x60},
++	{0x398d, 0x20},
++	{0x398e, 0x10},
++	{0x398f, 0x08},
++	{0x3990, 0x60},
++	{0x3991, 0x24},
++	{0x3992, 0x15},
++	{0x3993, 0x08},
++	{0x3994, 0x0a},
++	{0x3995, 0x20},
++	{0x3996, 0x38},
++	{0x3997, 0xa0},
++	{0x3998, 0x08},
++	{0x3999, 0x10},
++	{0x399a, 0x18},
++	{0x399b, 0x30},
++	{0x399c, 0x30},
++	{0x399d, 0x18},
++	{0x399e, 0x10},
++	{0x399f, 0x08},
++	{0x3637, 0x55},
++	{0x366f, 0x2c},
++	{0x5000, 0x06},
++	{0x5780, 0x7f},
++	{0x5781, 0x04},
++	{0x5782, 0x03},
++	{0x5783, 0x02},
++	{0x5784, 0x01},
++	{0x5785, 0x18},
++	{0x5786, 0x10},
++	{0x5787, 0x08},
++	{0x5788, 0x02},
++	{0x57a0, 0x00},
++	{0x57a1, 0x71},
++	{0x57a2, 0x01},
++	{0x57a3, 0xf1},
++	{0x395e, 0xc0},
++	{0x3962, 0x88},
++	{0x303a, 0xb3},
++	{0x303c, 0x0e},
++	{0x3035, 0x9b},
++	{0x320c, 0x08},
++	{0x320d, 0x20},
++	{0x320e, 0x05},
++	{0x320f, 0xd0},/*vts for 25fps*/
++	{0x3f04, 0x03},
++	{0x3f05, 0xec},
++	{0x3235, 0x09},
++	{0x3236, 0xc2},
++	{0x3802, 0x00},
++	{0x3963, 0x80},
++	{0x303b, 0x16},
++	{0x301f, 0x03},
++	{0x363b, 0x26},
++	{0x3902, 0xc5},
++	{0x3e00, 0x00},
++//	{0x3e01, 0x9c},
++	{0x3e01, 0xbc},
++	{0x3e02, 0x00},
++	{0x3e03, 0x0b},
++	{0x3e06, 0x00},
++	{0x3e07, 0x80},
++	{0x3e08, 0x03},
++	{0x3e09, 0x10},
++	{0x3d08, 0x00},//PCLK polarity
++	{0x3301, 0x12},
++	{0x3632, 0x08},
++	{0x3034, 0x01},
++	{0x3039, 0x24},
++
++	{SC2232H_REG_END, 0x00},	/* END MARKER */
++};
++/*
++ * the part of driver was fixed.
++ */
++
++static struct regval_list sc2232h_stream_on[] = {
++	{0x0100, 0x01},
++	{SC2232H_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list sc2232h_stream_off[] = {
++	{0x0100, 0x00},
++	{SC2232H_REG_END, 0x00},	/* END MARKER */
++};
++
++static int sc2232h_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct sc2232h_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret = 0;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int sc2232h_write(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char value)
++{
++	struct sc2232h_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3] = {(reg>>8)&0xff, reg&0xff, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 3,
++		.buf	= buf,
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int sc2232h_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != SC2232H_REG_END) {
++		if (vals->reg_num == SC2232H_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = sc2232h_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++/*
++ * Write a list of register settings; ff/ff stops the process.
++ */
++static int sc2232h_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != SC2232H_REG_END) {
++		if (vals->reg_num == SC2232H_REG_DELAY) {
++			msleep(vals->value);
++		} else {
++			ret = sc2232h_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int sc2232h_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc2232h_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->reset.pin, info->reset.active_level);
++		msleep(10);
++		gpio_direction_output(info->reset.pin, !info->reset.active_level);
++		msleep(10);
++	}
++	return 0;
++}
++
++
++static int sc2232h_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc2232h_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = sc2232h_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++
++static int sc2232h_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++	ret = sc2232h_read(sd, 0x3107, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != SC2232H_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = sc2232h_read(sd, 0x3108, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != SC2232H_CHIP_ID_M)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++
++	ret = sc2232h_read(sd, 0x3109, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != SC2232H_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++	return 0;
++}
++
++
++static struct sc2232h_win_size sc2232h_win_sizes[] = {
++	{
++		.width		= 1920,
++		.height		= 1080,
++		.sensor_info.fps		= 25 << 16 | 1,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= sc2232h_init_regs_1920_1080_25fps_dvp,
++	},
++};
++
++static int sc2232h_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_SC2232H_FMTS)
++		return -EINVAL;
++
++	code->code = sc2232h_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int sc2232h_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct sc2232h_format_struct *ovfmt;
++	struct sc2232h_win_size *wsize;
++	struct sc2232h_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int sc2232h_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct sc2232h_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	*(unsigned int *)fmt->reserved = &info->win->sensor_info;
++
++
++//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int sc2232h_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc2232h_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc2232h_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc2232h_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int sc2232h_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int sc2232h_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(sc2232h_again_lut); i++) {
++		lut = &sc2232h_again_lut[i];
++
++		if(gain <= lut->gain) {
++			return lut->value;
++		}
++	}
++
++	/*last value.*/
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(sc2232h_again_lut); i++) {
++		lut = &sc2232h_again_lut[i];
++
++		if(regval == lut->value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return 0;
++}
++
++static int sc2232h_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	struct sc2232h_info *info = to_state(sd);
++	char v = 0;
++	unsigned int reg_val = 0;
++	int ret = 0;
++
++
++	ret += sc2232h_read(sd, 0x3509, &v);
++
++	reg_val |= v;
++	ret += sc2232h_read(sd, 0x3508, &v);
++	reg_val |= v << 8;
++
++
++	*value = regval_to_again(reg_val);
++
++	return ret;
++}
++/*set analog gain db value, map value to sensor register.*/
++static int sc2232h_s_again(struct v4l2_subdev *sd, int value)
++{
++	struct sc2232h_info *info = to_state(sd);
++	unsigned int reg_value = 0;
++	int ret = 0;
++	int i;
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		reg_value = again_to_regval(info->again->default_value);
++	} else {
++		reg_value = again_to_regval(value);
++	}
++	/* denoise logic */
++	if (reg_value < 0x110) {
++		sc2232h_write(sd, 0x3812, 0x00);
++		sc2232h_write(sd, 0x3301, 0x12);
++		sc2232h_write(sd, 0x3632, 0x08);
++		sc2232h_write(sd, 0x3812, 0x30);
++	} else if (reg_value >= 0x110 && reg_value < 0x310) {
++		sc2232h_write(sd, 0x3812, 0x00);
++		sc2232h_write(sd, 0x3301, 0x20);
++		sc2232h_write(sd, 0x3632, 0x08);
++		sc2232h_write(sd, 0x3812, 0x30);
++	} else if(reg_value >= 0x310&&reg_value < 0x710) {
++		sc2232h_write(sd, 0x3812, 0x00);
++		sc2232h_write(sd, 0x3301, 0x28);
++		sc2232h_write(sd, 0x3632, 0x08);
++		sc2232h_write(sd, 0x3812, 0x30);
++	} else if(reg_value >= 0x710&&reg_value <= 0x71e) {
++		sc2232h_write(sd, 0x3812, 0x00);
++		sc2232h_write(sd, 0x3301, 0x64);
++		sc2232h_write(sd, 0x3632, 0x08);
++		sc2232h_write(sd, 0x3812, 0x30);
++	} else { //may be flick
++		sc2232h_write(sd, 0x3812, 0x00);
++		sc2232h_write(sd, 0x3301, 0x64);
++		sc2232h_write(sd, 0x3632, 0x48);
++		sc2232h_write(sd, 0x3812, 0x30);
++	}
++	ret = sc2232h_write(sd, 0x3e09, (unsigned char)(reg_value & 0xff));
++	ret += sc2232h_write(sd, 0x3e08, (unsigned char)((reg_value >> 8 << 2) | 0x03));
++	if (ret < 0)
++		return ret;
++
++	return ret;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int sc2232h_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc2232h_s_exp(struct v4l2_subdev *sd, int value)
++{
++	struct sc2232h_info *info = to_state(sd);
++	int ret = 0;
++
++	value *= 2;
++	ret = sc2232h_write(sd, 0x3e00, (unsigned char)((value >> 12) & 0x0f));
++	ret += sc2232h_write(sd, 0x3e01, (unsigned char)((value >> 4) & 0xff));
++	ret += sc2232h_write(sd, 0x3e02, (unsigned char)((value & 0x0f) << 4));
++
++	if (value < 250) {
++		ret += sc2232h_write(sd, 0x3314, 0x14);
++	}
++	else if(value > 450){
++		ret += sc2232h_write(sd, 0x3314, 0x04);
++	}
++
++	if (ret < 0)
++		return ret;
++
++	return ret;
++}
++
++static int sc2232h_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct sc2232h_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return sc2232h_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return sc2232h_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int sc2232h_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct sc2232h_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return sc2232h_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return sc2232h_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return sc2232h_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return sc2232h_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* sc2232h_s_gain turns off auto gain */
++			return sc2232h_s_gain(sd, info->gain->val);
++		}
++		return sc2232h_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return sc2232h_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return sc2232h_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return sc2232h_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops sc2232h_ctrl_ops = {
++	.s_ctrl = sc2232h_s_ctrl,
++	.g_volatile_ctrl = sc2232h_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int sc2232h_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = sc2232h_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int sc2232h_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	sc2232h_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++int sc2232h_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct sc2232h_info *info = to_state(sd);
++	int ret = 0;
++
++	if (enable) {
++		ret = sc2232h_write_array(sd, sc2232h_stream_on);
++		pr_debug("sc2232h stream on\n");
++
++	}
++	else {
++		ret = sc2232h_write_array(sd, sc2232h_stream_off);
++		pr_debug("sc2232h stream off\n");
++	}
++	return ret;
++}
++
++int sc2232h_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct sc2232h_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops sc2232h_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = sc2232h_g_register,
++	.s_register = sc2232h_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops sc2232h_video_ops = {
++	.s_stream = sc2232h_s_stream,
++	.g_frame_interval = sc2232h_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops sc2232h_pad_ops = {
++	//.enum_frame_interval = sc2232h_enum_frame_interval,
++	//.num_frame_size = sc2232h_enum_frame_size,
++	//.enum_mbus_code = sc2232h_enum_mbus_code,
++	.set_fmt = sc2232h_set_fmt,
++	.get_fmt = sc2232h_get_fmt,
++};
++
++static const struct v4l2_subdev_ops sc2232h_ops = {
++	.core = &sc2232h_core_ops,
++	.video = &sc2232h_video_ops,
++	.pad = &sc2232h_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int sc2232h_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_fract tpf;
++	struct v4l2_subdev *sd;
++	struct sc2232h_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->reset.pin = gpio;
++		info->reset.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++	v4l2_i2c_subdev_init(sd, client, &sc2232h_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	sc2232h_reset(sd, 1);
++
++#if 1
++	/* Make sure it's an sc2232h */
++	ret = sc2232h_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an sc2232h chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &sc2232h_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &sc2232h_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &sc2232h_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &sc2232h_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &sc2232h_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &sc2232h_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 261773, 1, 10000);
++
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &sc2232h_ctrl_ops,
++			V4L2_CID_EXPOSURE, 4, 1520 - 4, 1, 1000);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->win = &sc2232h_win_sizes[0];
++	sc2232h_init(sd, 1);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "sc2232h Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	return ret;
++}
++
++
++static int sc2232h_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct sc2232h_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	return 0;
++}
++
++static const struct i2c_device_id sc2232h_id[] = {
++	{ "sc2232h", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, sc2232h_id);
++
++static const struct of_device_id sc2232h_of_match[] = {
++	{.compatible = "ingenic,sc2232h", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ov2640_of_match);
++
++
++static struct i2c_driver sc2232h_driver = {
++	.driver = {
++		.name	= "sc2232h",
++		.of_match_table = of_match_ptr(sc2232h_of_match),
++	},
++	.probe		= sc2232h_probe,
++	.remove		= sc2232h_remove,
++	.id_table	= sc2232h_id,
++};
++
++module_i2c_driver(sc2232h_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for OmniVision sc2232h sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/i2c/ingenic-isp/sc230ai.c b/module_drivers/drivers/media/i2c/ingenic-isp/sc230ai.c
+new file mode 100644
+index 000000000..9156c61dc
+--- /dev/null
++++ b/module_drivers/drivers/media/i2c/ingenic-isp/sc230ai.c
+@@ -0,0 +1,1653 @@
++/*
++ * A V4L2 driver for OmniVision SC230AI cameras.
++ *
++ * Copyright 2006 One Laptop Per Child Association, Inc.  Written
++ * by Jonathan Corbet with substantial inspiration from Mark
++ * McClelland's ovcamchip code.
++ *
++ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
++ *
++ * This file may be distributed under the terms of the GNU General
++ * Public License, version 2.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-clk.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++#include <linux/of_gpio.h>
++#include <isp-sensor.h>
++
++
++#define SC230AI_CHIP_ID_H	(0xcb)
++#define SC230AI_CHIP_ID_L	(0x34)
++#define SC230AI_REG_END		0xff
++#define SC230AI_REG_DELAY	0x00
++#define SC230AI_PAGE_REG	    0xfd
++
++static bool debug;
++module_param(debug, bool, 0644);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++
++struct sc230ai_win_size {
++	unsigned int width;
++	unsigned int height;
++	unsigned int mbus_code;
++	struct sensor_info sensor_info;
++	enum v4l2_colorspace colorspace;
++	void *regs;
++
++};
++
++struct sc230ai_gpio {
++	int pin;
++	int active_level;
++};
++
++struct sc230ai_supply{
++	struct regulator *avdd;
++	struct regulator *dvdd;
++	struct regulator *dovdd;
++};
++
++struct sc230ai_info {
++	struct sc230ai_supply supply;
++	struct v4l2_subdev sd;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_ctrl *gain;
++	struct v4l2_ctrl *again;
++
++	struct v4l2_clk *clk;
++	struct clk *sclka;
++
++	struct v4l2_ctrl *exposure;
++
++	struct media_pad pad;
++
++	struct v4l2_subdev_format *format;	/*current fmt.*/
++	struct sc230ai_win_size *win;
++
++	struct sc230ai_gpio xshutdn;
++	struct sc230ai_gpio pwdn;
++	struct sc230ai_gpio efsync;
++	struct sc230ai_gpio led;
++};
++
++
++/*
++ * the part of driver maybe modify about different sensor and different board.
++ */
++struct again_lut {
++	unsigned int value;	/*sensor regs value*/
++	unsigned int fine_value;	/*sensor regs value*/
++	unsigned int gain;	/*isp gain*/
++};
++
++struct again_lut sc230ai_again_lut[] = {
++	/*
++	{0x00,	0},
++	{0x01,	65536},
++	{0x40,	115455},
++	{0x48,	180991},
++	{0x49,	246527},
++	{0x4b,	312063},
++	{0x4f,	377599},
++	{0x5f,	443135},
++	*/
++
++	{0x00,0x80,0},
++	{0x00,0x82,1501},
++	{0x00,0x84,2886},
++	{0x00,0x86,4343},
++	{0x00,0x88,5776},
++	{0x00,0x8a,7101},
++	{0x00,0x8c,8494},
++	{0x00,0x8e,9782},
++	{0x00,0x90,11136},
++	{0x00,0x92,12471},
++	{0x00,0x94,13706},
++	{0x00,0x96,15006},
++	{0x00,0x98,16288},
++	{0x00,0x9a,17474},
++	{0x00,0x9c,18724},
++	{0x00,0x9e,19880},
++	{0x00,0xa0,21098},
++	{0x00,0xa2,22300},
++	{0x00,0xa4,23414},
++	{0x00,0xa6,24588},
++	{0x00,0xa8,25747},
++	{0x00,0xaa,26821},
++	{0x00,0xac,27953},
++	{0x00,0xae,29003},
++	{0x00,0xb0,30109},
++	{0x00,0xb2,31203},
++	{0x00,0xb4,32217},
++	{0x00,0xb6,33287},
++	{0x00,0xb8,34345},
++	{0x00,0xba,35326},
++	{0x00,0xbc,36362},
++	{0x00,0xbe,37322},
++	{0x00,0xc0,38336},
++	{0x00,0xc2,39339},
++	{0x00,0xc4,40270},
++	{0x00,0xc6,41253},
++	{0x00,0xc8,42226},
++	{0x00,0xca,43129},
++	{0x00,0xcc,44083},
++	{0x00,0xce,44968},
++	{0x00,0xd0,45904},
++	{0x00,0xd2,46830},
++	{0x00,0xd4,47691},
++	{0x00,0xd6,48600},
++	{0x00,0xd8,49500},
++	{0x00,0xda,50337},
++	{0x00,0xdc,51221},
++	{0x00,0xdf,52042},
++	{0x00,0xe0,52911},
++	{0x00,0xe2,53771},
++	{0x00,0xe4,54571},
++	{0x00,0xe6,55417},
++	{0x00,0xe8,56255},
++	{0x00,0xea,57034},
++	{0x00,0xec,57858},
++	{0x00,0xee,58624},
++	{0x00,0xf0,59434},
++	{0x00,0xf2,60237},
++	{0x00,0xf4,60984},
++	{0x00,0xf6,61775},
++	{0x00,0xf8,62559},
++	{0x00,0xfa,63288},
++	{0x00,0xfc,64059},
++	{0x00,0xfe,64777},
++	{0x01,0x80,65536},
++	{0x01,0x82,66990},
++	{0x01,0x84,68468},
++	{0x01,0x86,69879},
++	{0x01,0x88,71268},
++	{0x01,0x8a,72637},
++	{0x01,0x8c,74030},
++	{0x01,0x8e,75360},
++	{0x01,0x90,76672},
++	{0x01,0x92,77966},
++	{0x01,0x94,79283},
++	{0x01,0x96,80542},
++	{0x01,0x98,81784},
++	{0x01,0x9a,83010},
++	{0x01,0x9c,84260},
++	{0x01,0x9e,85454},
++	{0x01,0xa0,86634},
++	{0x01,0xa2,87799},
++	{0x01,0xa4,88987},
++	{0x01,0xa6,90124},
++	{0x01,0xa8,91247},
++	{0x01,0xaa,92357},
++	{0x01,0xac,93489},
++	{0x01,0xae,94573},
++	{0x01,0xb0,95645},
++	{0x01,0xb2,96705},
++	{0x01,0xb4,97787},
++	{0x01,0xb6,98823},
++	{0x01,0xb8,99848},
++	{0x01,0xba,100862},
++	{0x01,0xbc,101898},
++	{0x01,0xbe,102890},
++	{0x01,0xc0,103872},
++	{0x01,0xc2,104844},
++	{0x01,0xc4,105837},
++	{0x01,0xc6,106789},
++	{0x01,0xc8,107732},
++	{0x01,0xca,108665},
++	{0x01,0xcc,109619},
++	{0x01,0xce,110534},
++	{0x01,0xd0,111440},
++	{0x01,0xd2,112338},
++	{0x01,0xd4,113255},
++	{0x01,0xd6,114136},
++	{0x01,0xd8,115008},
++	{0x40,0x80,115455},
++	{0x40,0x82,116323},
++	{0x40,0x84,117182},
++	{0x40,0x86,118034},
++	{0x40,0x88,118878},
++	{0x40,0x8a,119715},
++	{0x40,0x8c,120544},
++	{0x40,0x8e,121366},
++	{0x40,0x90,122181},
++	{0x40,0x92,122989},
++	{0x40,0x94,123790},
++	{0x40,0x96,124585},
++	{0x40,0x98,125373},
++	{0x40,0x9a,126154},
++	{0x40,0x9c,126929},
++	{0x40,0x9e,127697},
++	{0x40,0xa0,128460},
++	{0x40,0xa2,129216},
++	{0x40,0xa4,129966},
++	{0x40,0xa6,130711},
++	{0x40,0xa8,131449},
++	{0x40,0xaa,132910},
++	{0x40,0xac,134347},
++	{0x40,0xae,135764},
++	{0x40,0xb0,137159},
++	{0x40,0xb2,138534},
++	{0x40,0xb4,139890},
++	{0x40,0xb6,141226},
++	{0x40,0xb8,142544},
++	{0x40,0xba,143843},
++	{0x40,0xbc,145125},
++	{0x40,0xbe,146390},
++	{0x40,0xc0,147638},
++	{0x40,0xc2,148870},
++	{0x40,0xc4,150086},
++	{0x40,0xc6,151286},
++	{0x40,0xc8,152472},
++	{0x40,0xca,153643},
++	{0x40,0xcc,154799},
++	{0x40,0xce,155942},
++	{0x40,0xd0,157071},
++	{0x40,0xd2,158186},
++	{0x40,0xd4,159289},
++	{0x40,0xd6,160379},
++	{0x40,0xd8,161456},
++	{0x40,0xda,162521},
++	{0x40,0xdc,163575},
++	{0x40,0xdf,164616},
++	{0x40,0xe0,165647},
++	{0x40,0xe2,166666},
++	{0x40,0xe4,167675},
++	{0x40,0xe6,168672},
++	{0x40,0xe8,169660},
++	{0x40,0xea,170637},
++	{0x40,0xec,171604},
++	{0x40,0xee,172562},
++	{0x40,0xf0,173509},
++	{0x40,0xf2,174448},
++	{0x40,0xf4,175377},
++	{0x40,0xf6,176297},
++	{0x40,0xf8,177208},
++	{0x40,0xfa,178111},
++	{0x40,0xfc,179005},
++	{0x40,0xfe,179891},
++	{0x48,0x80,180991},
++	{0x48,0x82,181859},
++	{0x48,0x84,182718},
++	{0x48,0x86,183570},
++	{0x48,0x88,184414},
++	{0x48,0x8a,185251},
++	{0x48,0x8c,186080},
++	{0x48,0x8e,186902},
++	{0x48,0x90,187717},
++	{0x48,0x92,188525},
++	{0x48,0x94,189326},
++	{0x48,0x96,190121},
++	{0x48,0x98,190909},
++	{0x48,0x9a,191690},
++	{0x48,0x9c,192465},
++	{0x48,0x9e,193233},
++	{0x48,0xa0,193996},
++	{0x48,0xa2,194752},
++	{0x48,0xa4,195502},
++	{0x48,0xa6,196247},
++	{0x48,0xa8,197718},
++	{0x48,0xaa,199167},
++	{0x48,0xac,200594},
++	{0x48,0xae,202000},
++	{0x48,0xb0,203385},
++	{0x48,0xb2,204751},
++	{0x48,0xb4,206096},
++	{0x48,0xb6,207423},
++	{0x48,0xb8,208732},
++	{0x48,0xba,210022},
++	{0x48,0xbc,211296},
++	{0x48,0xbe,212552},
++	{0x48,0xc0,213792},
++	{0x48,0xc2,215016},
++	{0x48,0xc4,216224},
++	{0x48,0xc6,217417},
++	{0x48,0xc8,218595},
++	{0x48,0xca,219759},
++	{0x48,0xcc,220908},
++	{0x48,0xce,222044},
++	{0x48,0xd0,223166},
++	{0x48,0xd2,224275},
++	{0x48,0xd4,225371},
++	{0x48,0xd6,226455},
++	{0x48,0xd8,227526},
++	{0x48,0xda,228585},
++	{0x48,0xdc,229633},
++	{0x48,0xdf,230669},
++	{0x48,0xe0,231694},
++	{0x48,0xe2,232708},
++	{0x48,0xe4,233711},
++	{0x48,0xe6,234703},
++	{0x48,0xe8,235686},
++	{0x48,0xea,236658},
++	{0x48,0xec,237620},
++	{0x48,0xee,238573},
++	{0x48,0xf0,239516},
++	{0x48,0xf2,240450},
++	{0x48,0xf4,241374},
++	{0x48,0xf6,242290},
++	{0x48,0xf8,243197},
++	{0x48,0xfa,244095},
++	{0x48,0xfc,244985},
++	{0x48,0xfe,245866},
++	{0x49,0x80,246527},
++	{0x49,0x82,247395},
++	{0x49,0x84,248254},
++	{0x49,0x86,249106},
++	{0x49,0x88,249950},
++	{0x49,0x8a,250787},
++	{0x49,0x8c,251616},
++	{0x49,0x8e,252438},
++	{0x49,0x90,253253},
++	{0x49,0x92,254061},
++	{0x49,0x94,254862},
++	{0x49,0x96,255657},
++	{0x49,0x98,256445},
++	{0x49,0x9a,257226},
++	{0x49,0x9c,258001},
++	{0x49,0x9e,258769},
++	{0x49,0xa0,259532},
++	{0x49,0xa2,260288},
++	{0x49,0xa4,261038},
++	{0x49,0xa6,261783},
++	{0x49,0xa8,263254},
++	{0x49,0xaa,264703},
++	{0x49,0xac,266130},
++	{0x49,0xae,267536},
++	{0x49,0xb0,268921},
++	{0x49,0xb2,270287},
++	{0x49,0xb4,271632},
++	{0x49,0xb6,272959},
++	{0x49,0xb8,274268},
++	{0x49,0xba,275558},
++	{0x49,0xbc,276832},
++	{0x49,0xbe,278088},
++	{0x49,0xc0,279328},
++	{0x49,0xc2,280552},
++	{0x49,0xc4,281760},
++	{0x49,0xc6,282953},
++	{0x49,0xc8,284131},
++	{0x49,0xca,285295},
++	{0x49,0xcc,286444},
++	{0x49,0xce,287580},
++	{0x49,0xd0,288702},
++	{0x49,0xd2,289811},
++	{0x49,0xd4,290907},
++	{0x49,0xd6,291991},
++	{0x49,0xd8,293062},
++	{0x49,0xda,294121},
++	{0x49,0xdc,295169},
++	{0x49,0xdf,296205},
++	{0x49,0xe0,297230},
++	{0x49,0xe2,298244},
++	{0x49,0xe4,299247},
++	{0x49,0xe6,300239},
++	{0x49,0xe8,301222},
++	{0x49,0xea,302194},
++	{0x49,0xec,303156},
++	{0x49,0xee,304109},
++	{0x49,0xf0,305052},
++	{0x49,0xf2,305986},
++	{0x49,0xf4,306910},
++	{0x49,0xf6,307826},
++	{0x49,0xf8,308733},
++	{0x49,0xfa,309631},
++	{0x49,0xfc,310521},
++	{0x49,0xfe,311402},
++	{0x4b,0x80,312063},
++	{0x4b,0x82,312931},
++	{0x4b,0x84,313790},
++	{0x4b,0x86,314642},
++	{0x4b,0x88,315486},
++	{0x4b,0x8a,316323},
++	{0x4b,0x8c,317152},
++	{0x4b,0x8e,317974},
++	{0x4b,0x90,318789},
++	{0x4b,0x92,319597},
++	{0x4b,0x94,320398},
++	{0x4b,0x96,321193},
++	{0x4b,0x98,321981},
++	{0x4b,0x9a,322762},
++	{0x4b,0x9c,323537},
++	{0x4b,0x9e,324305},
++	{0x4b,0xa0,325068},
++	{0x4b,0xa2,325824},
++	{0x4b,0xa4,326574},
++	{0x4b,0xa6,327319},
++	{0x4b,0xa8,328057},
++	{0x4b,0xaa,329518},
++	{0x4b,0xac,330955},
++	{0x4b,0xae,332372},
++	{0x4b,0xb0,333767},
++	{0x4b,0xb2,335142},
++	{0x4b,0xb4,336498},
++	{0x4b,0xb6,337834},
++	{0x4b,0xb8,339152},
++	{0x4b,0xba,340451},
++	{0x4b,0xbc,341733},
++	{0x4b,0xbe,342998},
++	{0x4b,0xc0,344246},
++	{0x4b,0xc2,345478},
++	{0x4b,0xc4,346694},
++	{0x4b,0xc6,347894},
++	{0x4b,0xc8,349080},
++	{0x4b,0xca,350251},
++	{0x4b,0xcc,351407},
++	{0x4b,0xce,352550},
++	{0x4b,0xd0,353679},
++	{0x4b,0xd2,354794},
++	{0x4b,0xd4,355897},
++	{0x4b,0xd6,356987},
++	{0x4b,0xd8,358064},
++	{0x4b,0xda,359129},
++	{0x4b,0xdc,360183},
++	{0x4b,0xdf,361224},
++	{0x4b,0xe0,362255},
++	{0x4b,0xe2,363274},
++	{0x4b,0xe4,364283},
++	{0x4b,0xe6,365280},
++	{0x4b,0xe8,366268},
++	{0x4b,0xea,367245},
++	{0x4b,0xec,368212},
++	{0x4b,0xee,369170},
++	{0x4b,0xf0,370117},
++	{0x4b,0xf2,371056},
++	{0x4b,0xf4,371985},
++	{0x4b,0xf6,372905},
++	{0x4b,0xf8,373816},
++	{0x4b,0xfa,374719},
++	{0x4b,0xfc,375613},
++	{0x4b,0xfe,376499},
++	{0x4f,0x80,377599},
++	{0x4f,0x82,378467},
++	{0x4f,0x84,379326},
++	{0x4f,0x86,380178},
++	{0x4f,0x88,381022},
++	{0x4f,0x8a,381859},
++	{0x4f,0x8c,382688},
++	{0x4f,0x8e,383510},
++	{0x4f,0x90,384325},
++	{0x4f,0x92,385133},
++	{0x4f,0x94,385934},
++	{0x4f,0x96,386729},
++	{0x4f,0x98,387517},
++	{0x4f,0x9a,388298},
++	{0x4f,0x9c,389073},
++	{0x4f,0x9e,389841},
++	{0x4f,0xa0,390604},
++	{0x4f,0xa2,391360},
++	{0x4f,0xa4,392110},
++	{0x4f,0xa6,392855},
++	{0x4f,0xa8,393593},
++	{0x4f,0xaa,395054},
++	{0x4f,0xac,396491},
++	{0x4f,0xae,397908},
++	{0x4f,0xb0,399303},
++	{0x4f,0xb2,400678},
++	{0x4f,0xb4,402034},
++	{0x4f,0xb6,403370},
++	{0x4f,0xb8,404688},
++	{0x4f,0xba,405987},
++	{0x4f,0xbc,407269},
++	{0x4f,0xbe,408534},
++	{0x4f,0xc0,409782},
++	{0x4f,0xc2,411014},
++	{0x4f,0xc4,412230},
++	{0x4f,0xc6,413430},
++	{0x4f,0xc8,414616},
++	{0x4f,0xca,415787},
++	{0x4f,0xcc,416943},
++	{0x4f,0xce,418086},
++	{0x4f,0xd0,419215},
++	{0x4f,0xd2,420330},
++	{0x4f,0xd4,421433},
++	{0x4f,0xd6,422523},
++	{0x4f,0xd8,423600},
++	{0x4f,0xda,424665},
++	{0x4f,0xdc,425719},
++	{0x4f,0xdf,426760},
++	{0x4f,0xe0,427791},
++	{0x4f,0xe2,428810},
++	{0x4f,0xe4,429819},
++	{0x4f,0xe6,430816},
++	{0x4f,0xe8,431804},
++	{0x4f,0xea,432781},
++	{0x4f,0xec,433748},
++	{0x4f,0xee,434706},
++	{0x4f,0xf0,435653},
++	{0x4f,0xf2,436592},
++	{0x4f,0xf4,437521},
++	{0x4f,0xf6,438441},
++	{0x4f,0xf8,439352},
++	{0x4f,0xfa,440255},
++	{0x4f,0xfc,441149},
++	{0x4f,0xfe,442035},
++	{0x5f,0x80,443135},
++};
++
++static inline struct sc230ai_info *to_state(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct sc230ai_info, sd);
++}
++
++static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct sc230ai_info, hdl)->sd;
++}
++struct regval_list {
++	uint16_t reg_num;
++	unsigned char value;
++};
++
++static struct regval_list sc230ai_init_regs_1920_1080_30fps_MIPI[] = {
++	{0x0103,0x01},
++	{0x0100,0x00},
++	{0x36e9,0x80},
++	{0x37f9,0x80},
++	{0x301f,0x01},
++	{0x3221,0x06},
++	{0x3301,0x07},
++	{0x3304,0x50},
++	{0x3306,0x70},
++	{0x3308,0x18},
++	{0x3309,0x68},
++	{0x330a,0x01},
++	{0x330b,0x20},
++	{0x331e,0x41},
++	{0x331f,0x59},
++	{0x3333,0x10},
++	{0x3334,0x40},
++	{0x335d,0x60},
++	{0x335e,0x06},
++	{0x335f,0x08},
++	{0x3364,0x5e},
++	{0x337c,0x02},
++	{0x337d,0x0a},
++	{0x3390,0x01},
++	{0x3391,0x0b},
++	{0x3392,0x0f},
++	{0x3393,0x09},
++	{0x3394,0x0d},
++	{0x3395,0x60},
++	{0x3396,0x48},
++	{0x3397,0x49},
++	{0x3398,0x4b},
++	{0x3399,0x06},
++	{0x339a,0x0a},
++	{0x339b,0x0d},
++	{0x339c,0x60},
++	{0x33a2,0x04},
++	{0x33af,0x40},
++	{0x33b1,0x80},
++	{0x33b3,0x40},
++	{0x33b9,0x0a},
++	{0x33f9,0xa0},
++	{0x33fb,0xbf},
++	{0x33fc,0x5f},
++	{0x33fd,0x7f},
++	{0x349f,0x03},
++	{0x34a6,0x4b},
++	{0x34a7,0x5f},
++	{0x34a8,0x30},
++	{0x34a9,0x20},
++	{0x34aa,0x01},
++	{0x34ab,0x28},
++	{0x34ac,0x01},
++	{0x34ad,0x58},
++	{0x34f8,0x7f},
++	{0x34f9,0x10},
++	{0x3630,0xc0},
++	{0x3633,0x44},
++	{0x363b,0x20},
++	{0x3670,0x09},
++	{0x3674,0xb0},
++	{0x3675,0x80},
++	{0x3676,0x88},
++	{0x367c,0x40},
++	{0x367d,0x49},
++	{0x3690,0x44},
++	{0x3691,0x33},
++	{0x3692,0x43},
++	{0x369c,0x49},
++	{0x369d,0x4f},
++	{0x36ae,0x4b},
++	{0x36af,0x4f},
++	{0x36b0,0x87},
++	{0x36b1,0x94},
++	{0x36b2,0xbc},
++	{0x36d0,0x01},
++	{0x3722,0x97},
++	{0x3728,0x90},
++	{0x3901,0x02},
++	{0x3902,0xc5},
++	{0x3904,0x04},
++	{0x3907,0x00},
++	{0x3908,0x41},
++	{0x3909,0x00},
++	{0x390a,0x00},
++	{0x3933,0x84},
++	{0x3934,0x10},
++	{0x3940,0x78},
++	{0x3942,0x04},
++	{0x3943,0x11},
++	{0x3e00,0x00},
++	{0x3e01,0x8c},
++	{0x3e02,0x20},
++	{0x440e,0x02},
++	{0x5010,0x01},
++	{0x5787,0x08},
++	{0x5788,0x03},
++	{0x5789,0x00},
++	{0x578a,0x10},
++	{0x578b,0x08},
++	{0x578c,0x00},
++	{0x5790,0x08},
++	{0x5791,0x04},
++	{0x5792,0x00},
++	{0x5793,0x10},
++	{0x5794,0x08},
++	{0x5795,0x00},
++	{0x5799,0x06},
++	{0x57ad,0x00},
++	{0x5ae0,0xfe},
++	{0x5ae1,0x40},
++	{0x5ae2,0x3f},
++	{0x5ae3,0x38},
++	{0x5ae4,0x28},
++	{0x5ae5,0x3f},
++	{0x5ae6,0x38},
++	{0x5ae7,0x28},
++	{0x5ae8,0x3f},
++	{0x5ae9,0x3c},
++	{0x5aea,0x2c},
++	{0x5aeb,0x3f},
++	{0x5aec,0x3c},
++	{0x5aed,0x2c},
++	{0x5af4,0x3f},
++	{0x5af5,0x38},
++	{0x5af6,0x28},
++	{0x5af7,0x3f},
++	{0x5af8,0x38},
++	{0x5af9,0x28},
++	{0x5afa,0x3f},
++	{0x5afb,0x3c},
++	{0x5afc,0x2c},
++	{0x5afd,0x3f},
++	{0x5afe,0x3c},
++	{0x5aff,0x2c},
++	{0x36e9,0x20},
++	{0x37f9,0x27},
++	{SC230AI_REG_END, 0x00},	/* END MARKER */
++};
++
++static struct regval_list sc230ai_init_regs_1920_1080_60fps_MIPI[] = {
++	{0x0103,0x01},
++	{0x0100,0x00},
++	{0x36e9,0x80},
++	{0x37f9,0x80},
++	{0x301f,0x02},
++	{0x3221,0x06},
++	{0x3301,0x09},
++	{0x3304,0x50},
++	{0x3306,0x48},
++	{0x3308,0x18},
++	{0x3309,0x68},
++	{0x330a,0x00},
++	{0x330b,0xc0},
++	{0x331e,0x41},
++	{0x331f,0x59},
++	{0x3333,0x10},
++	{0x3334,0x40},
++	{0x335d,0x60},
++	{0x335e,0x06},
++	{0x335f,0x08},
++	{0x3364,0x5e},
++	{0x337c,0x02},
++	{0x337d,0x0a},
++	{0x3390,0x01},
++	{0x3391,0x0b},
++	{0x3392,0x0f},
++	{0x3393,0x0c},
++	{0x3394,0x0d},
++	{0x3395,0x60},
++	{0x3396,0x48},
++	{0x3397,0x49},
++	{0x3398,0x4f},
++	{0x3399,0x0a},
++	{0x339a,0x0f},
++	{0x339b,0x14},
++	{0x339c,0x60},
++	{0x33a2,0x04},
++	{0x33af,0x40},
++	{0x33b1,0x80},
++	{0x33b3,0x40},
++	{0x33b9,0x0a},
++	{0x33f9,0x70},
++	{0x33fb,0x90},
++	{0x33fc,0x4b},
++	{0x33fd,0x5f},
++	{0x349f,0x03},
++	{0x34a6,0x4b},
++	{0x34a7,0x4f},
++	{0x34a8,0x30},
++	{0x34a9,0x20},
++	{0x34aa,0x00},
++	{0x34ab,0xe0},
++	{0x34ac,0x01},
++	{0x34ad,0x00},
++	{0x34f8,0x5f},
++	{0x34f9,0x10},
++	{0x3630,0xc0},
++	{0x3633,0x44},
++	{0x3637,0x29},
++	{0x363b,0x20},
++	{0x3670,0x09},
++	{0x3674,0xb0},
++	{0x3675,0x80},
++	{0x3676,0x88},
++	{0x367c,0x40},
++	{0x367d,0x49},
++	{0x3690,0x44},
++	{0x3691,0x44},
++	{0x3692,0x54},
++	{0x369c,0x49},
++	{0x369d,0x4f},
++	{0x36ae,0x4b},
++	{0x36af,0x4f},
++	{0x36b0,0x87},
++	{0x36b1,0x94},
++	{0x36b2,0xbc},
++	{0x36d0,0x01},
++	{0x36ea,0x0b},
++	{0x36eb,0x04},
++	{0x36ec,0x0c},
++	{0x36ed,0x24},
++	{0x370f,0x01},
++	{0x3722,0x17},
++	{0x3728,0x90},
++	{0x37b0,0x17},
++	{0x37b1,0x17},
++	{0x37b2,0x97},
++	{0x37b3,0x4b},
++	{0x37b4,0x4f},
++	{0x37fa,0x0b},
++	{0x37fb,0x24},
++	{0x37fc,0x10},
++	{0x37fd,0x22},
++	{0x3901,0x02},
++	{0x3902,0xc5},
++	{0x3904,0x04},
++	{0x3907,0x00},
++	{0x3908,0x41},
++	{0x3909,0x00},
++	{0x390a,0x00},
++	{0x391f,0x04},
++	{0x3933,0x84},
++	{0x3934,0x10},
++	{0x3940,0x78},
++	{0x3942,0x04},
++	{0x3943,0x11},
++	{0x3e00,0x00},
++	{0x3e01,0x8c},
++	{0x3e02,0x20},
++	{0x440e,0x02},
++	{0x5010,0x01},
++	{0x5787,0x08},
++	{0x5788,0x03},
++	{0x5789,0x00},
++	{0x578a,0x10},
++	{0x578b,0x08},
++	{0x578c,0x00},
++	{0x5790,0x08},
++	{0x5791,0x04},
++	{0x5792,0x00},
++	{0x5793,0x10},
++	{0x5794,0x08},
++	{0x5795,0x00},
++	{0x5799,0x06},
++	{0x57ad,0x00},
++	{0x5ae0,0xfe},
++	{0x5ae1,0x40},
++	{0x5ae2,0x3f},
++	{0x5ae3,0x38},
++	{0x5ae4,0x28},
++	{0x5ae5,0x3f},
++	{0x5ae6,0x38},
++	{0x5ae7,0x28},
++	{0x5ae8,0x3f},
++	{0x5ae9,0x3c},
++	{0x5aea,0x2c},
++	{0x5aeb,0x3f},
++	{0x5aec,0x3c},
++	{0x5aed,0x2c},
++	{0x5af4,0x3f},
++	{0x5af5,0x38},
++	{0x5af6,0x28},
++	{0x5af7,0x3f},
++	{0x5af8,0x38},
++	{0x5af9,0x28},
++	{0x5afa,0x3f},
++	{0x5afb,0x3c},
++	{0x5afc,0x2c},
++	{0x5afd,0x3f},
++	{0x5afe,0x3c},
++	{0x5aff,0x2c},
++	{0x36e9,0x20},
++	{0x37f9,0x24},
++	{SC230AI_REG_END, 0x00},
++};
++
++
++static struct regval_list sc230ai_stream_on[] = {
++	{0x0100,0x01},
++	{SC230AI_REG_END, 0x00},
++};
++
++static struct regval_list sc230ai_stream_off[] = {
++	{0x0100,0x00},
++	{SC230AI_REG_END, 0x00},
++};
++
++
++int sc230ai_read(struct v4l2_subdev *sd, unsigned short reg,
++		unsigned char *value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[2] = {(reg>>8)&0xff, reg&0xff};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 2,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 1,
++			.buf	= value,
++		}
++	};
++	int ret;
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int sc230ai_write(struct v4l2_subdev *sd, unsigned short reg,
++			unsigned char value)
++{
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	uint8_t buf[3] = {(reg>>8)&0xff, reg&0xff, value};
++	struct i2c_msg msg = {
++		.addr	= client->addr,
++		.flags	= 0,
++		.len	= 3,
++		.buf	= buf,
++	};
++	int ret;
++	unsigned int timeout  = 100;
++	while(timeout--){
++		ret = i2c_transfer(client->adapter, &msg, 1);
++		if(ret == -EAGAIN){
++			msleep(100);
++			continue;
++		}
++		else
++			break;
++	}
++	if (ret > 0)
++		ret = 0;
++	return ret;
++}
++
++static int sc230ai_read_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	unsigned char val;
++	while (vals->reg_num != SC230AI_REG_END) {
++		if (vals->reg_num == SC230AI_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = sc230ai_read(sd, vals->reg_num, &val);
++			if (ret < 0)
++				return ret;
++			if (vals->reg_num == SC230AI_PAGE_REG){
++				val &= 0xf8;
++				val |= (vals->value & 0x07);
++				ret = sc230ai_write(sd, vals->reg_num, val);
++				ret = sc230ai_read(sd, vals->reg_num, &val);
++			}
++		}
++		vals++;
++	}
++	return 0;
++}
++static int sc230ai_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
++{
++	int ret;
++	while (vals->reg_num != SC230AI_REG_END) {
++		if (vals->reg_num == SC230AI_REG_DELAY) {
++				msleep(vals->value);
++		} else {
++			ret = sc230ai_write(sd, vals->reg_num, vals->value);
++			if (ret < 0)
++				return ret;
++		}
++		vals++;
++	}
++	return 0;
++}
++
++
++/*
++ * Stuff that knows about the sensor.
++ */
++static int sc230ai_lightup(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc230ai_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->led.pin, info->led.active_level);
++	} else {
++		gpio_direction_output(info->led.pin, !info->led.active_level);
++	}
++	return 0;
++}
++
++static int sc230ai_xshutdn(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc230ai_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->xshutdn.pin, info->xshutdn.active_level);
++	} else {
++		gpio_direction_output(info->xshutdn.pin, !info->xshutdn.active_level);
++	}
++	return 0;
++}
++
++static int sc230ai_pwdn(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc230ai_info *info = to_state(sd);
++
++	if(val) {
++		gpio_direction_output(info->pwdn.pin, info->pwdn.active_level);
++		msleep(10);
++	} else {
++		gpio_direction_output(info->pwdn.pin, !info->pwdn.active_level);
++	}
++	return 0;
++}
++
++static int sc230ai_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc230ai_info *info = to_state(sd);
++	unsigned char v;
++	int ret;
++
++	/*software reset*/
++	ret = sc230ai_read(sd, 0x0103, &v);
++
++	if(val) {
++		v |= 1;
++		ret += sc230ai_write(sd, 0x0103, v);
++	}
++	return 0;
++}
++
++
++static int sc230ai_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct sc230ai_info *info = to_state(sd);
++	int ret = 0;
++
++	ret = sc230ai_write_array(sd, info->win->regs);
++
++	return ret;
++}
++
++
++static int sc230ai_detect(struct v4l2_subdev *sd, unsigned int *ident)
++{
++	unsigned char v;
++	int ret;
++
++	ret = sc230ai_read(sd, 0x3107, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != SC230AI_CHIP_ID_H)
++		return -ENODEV;
++	*ident = v;
++
++	ret = sc230ai_read(sd, 0x3108, &v);
++	pr_debug("-----%s: %d ret = %d, v = 0x%02x\n", __func__, __LINE__, ret,v);
++	if (ret < 0)
++		return ret;
++	if (v != SC230AI_CHIP_ID_L)
++		return -ENODEV;
++	*ident = (*ident << 8) | v;
++	return 0;
++
++}
++
++static struct sc230ai_win_size sc230ai_win_sizes[] = {
++	{
++		.width				= 1920,
++		.height				= 1080,
++		.sensor_info.fps				= 30 << 16 | 1,
++		.sensor_info.mipi_cfg.twidth		= 1920,
++		.sensor_info.mipi_cfg.theight		= 1080,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= sc230ai_init_regs_1920_1080_30fps_MIPI,
++	},
++	{
++		.width				= 1920,
++		.height				= 1080,
++		.sensor_info.fps				= 60 << 16 | 1,
++		.sensor_info.mipi_cfg.twidth		= 1920,
++		.sensor_info.mipi_cfg.theight		= 1080,
++		.sensor_info.mipi_cfg.mipi_crop_start0x	= 0,
++		.sensor_info.mipi_cfg.mipi_crop_start0y	= 0,
++		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace	= V4L2_COLORSPACE_SRGB,
++		.regs 		= sc230ai_init_regs_1920_1080_60fps_MIPI,
++	},
++};
++
++static int sc230ai_enum_mbus_code(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_mbus_code_enum *code)
++{
++#if 0
++	if (code->pad || code->index >= N_SC230AI_FMTS)
++		return -EINVAL;
++
++	code->code = sc230ai_formats[code->index].mbus_code;
++#endif
++	return 0;
++}
++
++/*
++ * Set a format.
++ */
++static int sc230ai_set_fmt(struct v4l2_subdev *sd,
++		struct v4l2_subdev_pad_config *cfg,
++		struct v4l2_subdev_format *format)
++{
++	struct sc230ai_format_struct *ovfmt;
++	struct sc230ai_win_size *wsize;
++	struct sc230ai_info *info = to_state(sd);
++	int ret;
++
++	if (format->pad)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int sc230ai_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct sc230ai_info *info = to_state(sd);
++	struct v4l2_mbus_framefmt *fmt = &format->format;
++	int ret = 0;
++
++	if(!info->win) {
++		dev_err(sd->dev, "sensor win_size not set!\n");
++		return -EINVAL;
++	}
++
++	fmt->width = info->win->width;
++	fmt->height = info->win->height;
++	fmt->code = info->win->mbus_code;
++	fmt->colorspace = info->win->colorspace;
++	*(unsigned int *)fmt->reserved = &info->win->sensor_info;
++
++
++//	printk("----%s, %d, width: %d, height: %d, code: %x\n",
++//			__func__, __LINE__, fmt->width, fmt->height, fmt->code);
++
++	return ret;
++}
++
++static int sc230ai_s_brightness(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc230ai_s_contrast(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc230ai_s_hflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc230ai_s_vflip(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++/*
++ * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
++ * the data sheet, the VREF parts should be the most significant, but
++ * experience shows otherwise.  There seems to be little value in
++ * messing with the VREF bits, so we leave them alone.
++ */
++static int sc230ai_g_gain(struct v4l2_subdev *sd, __s32 *value)
++{
++	int ret = 0;
++	unsigned char gain = 0;
++
++	*value = gain;
++	return ret;
++}
++
++static int sc230ai_s_gain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++//	printk("---%s, %d, s_gain: value: %d\n", __func__, __LINE__, value);
++
++	return ret;
++}
++
++static unsigned int again_to_regval(int gain, unsigned int *value, unsigned int *fine_value)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(sc230ai_again_lut); i++) {
++		lut = &sc230ai_again_lut[i];
++
++		if(gain <= lut->gain) {
++			*value = lut->value;
++			*fine_value = lut->fine_value;
++			return lut->value;
++		}
++	}
++	/*last value.*/
++	*value = lut->value;
++	*fine_value = lut->fine_value;
++	return lut->value;
++}
++
++static int regval_to_again(unsigned int regval, unsigned int fine_reg_val)
++{
++	struct again_lut *lut = NULL;
++	int i = 0;
++	for(i = 0; i < ARRAY_SIZE(sc230ai_again_lut); i++) {
++		lut = &sc230ai_again_lut[i];
++
++		if(regval == lut->value && fine_reg_val == lut->fine_value) {
++			return lut->gain;
++		}
++	}
++	printk("%s, %d regval not mapped to isp gain\n", __func__, __LINE__);
++	return -EINVAL;
++}
++
++static int sc230ai_g_again(struct v4l2_subdev *sd, __s32 *value)
++{
++	char v = 0;
++	unsigned int reg_val = 0;
++	unsigned int fine_reg_val = 0;
++	int ret = 0;
++
++
++	ret = sc230ai_read(sd, 0x3e09, &v);
++	reg_val = v ;
++	ret = sc230ai_read(sd, 0x3e07, &v);
++	fine_reg_val = v ;
++
++	*value = regval_to_again(reg_val, fine_reg_val);
++
++	return ret;
++
++}
++/*set analog gain db value, map value to sensor register.*/
++static int sc230ai_s_again(struct v4l2_subdev *sd, int value)
++{
++	struct sc230ai_info *info = to_state(sd);
++	unsigned int reg_value;
++	unsigned int reg_fine_value;
++	int ret = 0;
++
++	if(value < info->again->minimum || value > info->again->maximum) {
++		/* use default value. */
++		again_to_regval(info->again->default_value, &reg_value, &reg_fine_value);
++	} else {
++		again_to_regval(value, &reg_value, &reg_fine_value);
++	}
++
++	ret += sc230ai_write(sd, 0x3e09, (unsigned char)(reg_value));
++	ret += sc230ai_write(sd, 0x3e07, (unsigned char)(reg_fine_value));
++	if (ret < 0){
++		printk("sc230ai_write error  %d\n" ,__LINE__ );
++		return ret;
++	}
++	return 0;
++}
++
++/*
++ * Tweak autogain.
++ */
++static int sc230ai_s_autogain(struct v4l2_subdev *sd, int value)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static int sc230ai_s_exp(struct v4l2_subdev *sd, int value)
++{
++	struct sc230ai_info *info = to_state(sd);
++	int ret = 0;
++
++	value *= 2; /*unit in half line*/
++	ret += sc230ai_write(sd, 0x3e00, (unsigned char)((value >> 12) & 0xf));
++	ret += sc230ai_write(sd, 0x3e01, (unsigned char)((value >> 4) & 0xff));
++	ret += sc230ai_write(sd, 0x3e02, (unsigned char)(value & 0xf) << 4);
++
++	if (ret < 0) {
++		printk("sc230ai_write error  %d\n" ,__LINE__);
++		return ret;
++	}
++
++	return 0;
++}
++
++static int sc230ai_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct sc230ai_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_AUTOGAIN:
++		return sc230ai_g_gain(sd, &info->gain->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return sc230ai_g_again(sd, &info->again->val);
++	}
++	return -EINVAL;
++}
++
++static int sc230ai_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = to_sd(ctrl);
++	struct sc230ai_info *info = to_state(sd);
++
++	switch (ctrl->id) {
++	case V4L2_CID_BRIGHTNESS:
++		return sc230ai_s_brightness(sd, ctrl->val);
++	case V4L2_CID_CONTRAST:
++		return sc230ai_s_contrast(sd, ctrl->val);
++	case V4L2_CID_VFLIP:
++		return sc230ai_s_vflip(sd, ctrl->val);
++	case V4L2_CID_HFLIP:
++		return sc230ai_s_hflip(sd, ctrl->val);
++	case V4L2_CID_AUTOGAIN:
++		/* Only set manual gain if auto gain is not explicitly
++		   turned on. */
++		if (!ctrl->val) {
++			/* sc230ai_s_gain turns off auto gain */
++			return sc230ai_s_gain(sd, info->gain->val);
++		}
++		return sc230ai_s_autogain(sd, ctrl->val);
++	case V4L2_CID_GAIN:
++		return sc230ai_s_gain(sd, ctrl->val);
++	case V4L2_CID_ANALOGUE_GAIN:
++		return sc230ai_s_again(sd, ctrl->val);
++	case V4L2_CID_EXPOSURE:
++		return sc230ai_s_exp(sd, ctrl->val);
++	}
++	return -EINVAL;
++}
++
++static const struct v4l2_ctrl_ops sc230ai_ctrl_ops = {
++	.s_ctrl = sc230ai_s_ctrl,
++	.g_volatile_ctrl = sc230ai_g_volatile_ctrl,
++};
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int sc230ai_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
++{
++	unsigned char val = 0;
++	int ret;
++
++	ret = sc230ai_read(sd, reg->reg & 0xffff, &val);
++	reg->val = val;
++	reg->size = 1;
++	return ret;
++}
++
++static int sc230ai_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
++{
++	sc230ai_write(sd, reg->reg & 0xffff, reg->val & 0xff);
++	return 0;
++}
++#endif
++
++static int sc230ai_power(struct v4l2_subdev *sd, int on)
++{
++	struct sc230ai_info *info = to_state(sd);
++	struct i2c_client *client = v4l2_get_subdevdata(sd);
++	int ret;
++
++	info->supply.avdd  = devm_regulator_get_optional(&client->dev, "avdd");
++	info->supply.dvdd  = devm_regulator_get_optional(&client->dev, "dvdd");
++	info->supply.dovdd = devm_regulator_get_optional(&client->dev, "dovdd");
++
++	if (IS_ERR(info->supply.avdd)||IS_ERR(info->supply.dvdd)
++		||IS_ERR(info->supply.dovdd)) {
++			if ((PTR_ERR(info->supply.avdd) == -EPROBE_DEFER)
++				||(PTR_ERR(info->supply.avdd) == -EPROBE_DEFER)
++					||(PTR_ERR(info->supply.avdd) == -EPROBE_DEFER))
++				return -EPROBE_DEFER;
++			printk("No sc230ai vdd regulator found\n");
++	}
++
++	if ((!IS_ERR(info->supply.avdd))&&(!IS_ERR(info->supply.avdd))
++			&&(!IS_ERR(info->supply.avdd)))  {
++		if(on){
++			ret = regulator_enable(info->supply.avdd);
++			ret = regulator_enable(info->supply.dvdd);
++			ret = regulator_enable(info->supply.dovdd);
++			if (ret)
++			   dev_err(&client->dev, "sc230ai vdd supply disable failed\n");
++		}
++		else{
++			ret = regulator_disable(info->supply.avdd);
++			ret = regulator_disable(info->supply.dvdd);
++			ret = regulator_disable(info->supply.dovdd);
++			if (ret)
++			    dev_err(&client->dev, "sc230ai vdd supply disable failed\n");
++		}
++	}else{
++		dev_err(&client->dev, "sc230ai vdd supply IS_ERR failed\n");
++	}
++	return ret;
++}
++
++
++
++int sc230ai_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct sc230ai_info *info = to_state(sd);
++	int ret = 0;
++
++	if (enable) {
++		ret = sc230ai_write_array(sd, sc230ai_stream_on);
++		printk("sc230ai stream on\n");
++
++	}
++	else {
++		ret = sc230ai_write_array(sd, sc230ai_stream_off);
++		printk("sc230ai stream off\n");
++	}
++	return ret;
++}
++
++
++int sc230ai_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *interval)
++{
++	struct sc230ai_info *info = to_state(sd);
++	if(info->win->sensor_info.fps){
++		interval->interval.numerator = info->win->sensor_info.fps & 0xffff;
++		interval->interval.denominator = info->win->sensor_info.fps >> 16;
++		return 0;
++	}
++	return -EINVAL;
++}
++/* ----------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops sc230ai_core_ops = {
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = sc230ai_g_register,
++	.s_register = sc230ai_s_register,
++#endif
++
++};
++
++static const struct v4l2_subdev_video_ops sc230ai_video_ops = {
++	.s_stream = sc230ai_s_stream,
++	.g_frame_interval = sc230ai_g_frame_interval,
++};
++
++static const struct v4l2_subdev_pad_ops sc230ai_pad_ops = {
++	//.enum_frame_interval = sc230ai_enum_frame_interval,
++	//.num_frame_size = sc230ai_enum_frame_size,
++	//.enum_mbus_code = sc230ai_enum_mbus_code,
++	.set_fmt = sc230ai_set_fmt,
++	.get_fmt = sc230ai_get_fmt,
++};
++
++static const struct v4l2_subdev_ops sc230ai_ops = {
++	.core = &sc230ai_core_ops,
++	.video = &sc230ai_video_ops,
++	.pad = &sc230ai_pad_ops,
++};
++
++/* ----------------------------------------------------------------------- */
++
++static int sc230ai_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct v4l2_subdev *sd;
++	struct sc230ai_info *info;
++	int ret;
++	unsigned int ident = 0;
++	int gpio = -EINVAL;
++	unsigned int flags;
++
++	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
++	if (info == NULL)
++		return -ENOMEM;
++	sd = &info->sd;
++
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,xshutdn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->xshutdn.pin = gpio;
++		info->xshutdn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,pwdn-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->pwdn.pin = gpio;
++		info->pwdn.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,efsync-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->efsync.pin = gpio;
++		info->efsync.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++	gpio = of_get_named_gpio_flags(client->dev.of_node, "ingenic,led-gpio", 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		info->led.pin = gpio;
++		info->led.active_level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	}
++
++
++	v4l2_i2c_subdev_init(sd, client, &sc230ai_ops);
++	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++
++	sc230ai_power(sd,1);
++
++	/*clk*/
++	info->clk = v4l2_clk_get(&client->dev, "div_cim");
++	if (IS_ERR(info->clk)) {
++		ret = PTR_ERR(info->clk);
++		goto err_clkget;
++	}
++
++	ret = v4l2_clk_set_rate(info->clk, 24000000);
++	if(ret)
++		dev_err(sd->dev, "clk_set_rate err!\n");
++
++	ret = v4l2_clk_enable(info->clk);
++	if(ret)
++		dev_err(sd->dev, "clk_enable err!\n");
++
++	sc230ai_xshutdn(sd, 1);
++	sc230ai_pwdn(sd, 1);
++	sc230ai_lightup(sd, 0);
++	sc230ai_reset(sd, 1);
++#if 1
++	/* Make sure it's an sc230ai */
++	ret = sc230ai_detect(sd, &ident);
++	if (ret) {
++		v4l_err(client,
++			"chip found @ 0x%x (%s) is not an sc230ai chip.\n",
++			client->addr << 1, client->adapter->name);
++		return ret;
++	}
++#endif
++
++	v4l_info(client, "chip found @ 0x%02x (%s)\n",
++			client->addr << 1, client->adapter->name);
++
++	v4l2_ctrl_handler_init(&info->hdl, 8);
++	v4l2_ctrl_new_std(&info->hdl, &sc230ai_ctrl_ops,
++			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
++	v4l2_ctrl_new_std(&info->hdl, &sc230ai_ctrl_ops,
++			V4L2_CID_CONTRAST, 0, 127, 1, 64);
++	v4l2_ctrl_new_std(&info->hdl, &sc230ai_ctrl_ops,
++			V4L2_CID_VFLIP, 0, 1, 1, 0);
++	v4l2_ctrl_new_std(&info->hdl, &sc230ai_ctrl_ops,
++			V4L2_CID_HFLIP, 0, 1, 1, 0);
++	info->gain = v4l2_ctrl_new_std(&info->hdl, &sc230ai_ctrl_ops,
++			V4L2_CID_GAIN, 0, 255, 1, 128);
++	info->again = v4l2_ctrl_new_std(&info->hdl, &sc230ai_ctrl_ops,
++			V4L2_CID_ANALOGUE_GAIN, 0, 443135, 1, 10000);
++	/*unit exposure lines: */
++	info->exposure = v4l2_ctrl_new_std(&info->hdl, &sc230ai_ctrl_ops,
++			V4L2_CID_EXPOSURE, 1,  1152 - 4 , 4, 600);
++
++	sd->ctrl_handler = &info->hdl;
++	if (info->hdl.error) {
++		int err = info->hdl.error;
++
++		v4l2_ctrl_handler_free(&info->hdl);
++		return err;
++	}
++	v4l2_ctrl_handler_setup(&info->hdl);
++
++	info->win = &sc230ai_win_sizes[0];
++	sc230ai_init(sd, 1);
++
++	info->pad.flags = MEDIA_PAD_FL_SOURCE;
++	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
++	if(ret < 0) {
++		goto err_entity_init;
++	}
++	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = v4l2_async_register_subdev(&info->sd);
++	if (ret < 0)
++		goto err_videoprobe;
++
++	dev_info(&client->dev, "sc230ai Probed\n");
++	return 0;
++err_videoprobe:
++err_entity_init:
++	v4l2_clk_put(info->clk);
++err_clkget:
++	return ret;
++}
++
++
++static int sc230ai_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct sc230ai_info *info = to_state(sd);
++
++	v4l2_device_unregister_subdev(sd);
++	v4l2_ctrl_handler_free(&info->hdl);
++	v4l2_clk_put(info->clk);
++	return 0;
++}
++
++static const struct i2c_device_id sc230ai_id[] = {
++	{ "sc230ai", 0},
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, sc230ai_id);
++
++static const struct of_device_id sc230ai_of_match[] = {
++	{.compatible = "smartsens,sc230ai", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, sc230ai_of_match);
++
++
++static int sc230ai_suspend(struct device *dev)
++{
++        struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++        struct v4l2_subdev *sd = i2c_get_clientdata(client);
++        struct sc230ai_info *info = to_state(sd);
++	int ret=0;
++
++	sc230ai_power(sd,0);
++	v4l2_clk_disable(info->clk);
++        return 0;
++}
++
++static int sc230ai_resume(struct device *dev)
++{
++	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct sc230ai_info *info = to_state(sd);
++	int ret=0;
++
++	sc230ai_power(sd,1);
++	v4l2_clk_enable(info->clk);
++	sc230ai_reset(sd, 1);
++	sc230ai_init(sd, 1);
++	return 0;
++}
++
++const struct dev_pm_ops sc230ai_pm =
++{
++        .suspend = sc230ai_suspend,
++        .resume  = sc230ai_resume,
++};
++
++
++static struct i2c_driver sc230ai_driver = {
++	.driver = {
++		.name	= "sc230ai",
++		.of_match_table = of_match_ptr(sc230ai_of_match),
++		.pm	=  &sc230ai_pm,
++	},
++	.probe		= sc230ai_probe,
++	.remove		= sc230ai_remove,
++	.id_table	= sc230ai_id,
++};
++
++module_i2c_driver(sc230ai_driver);
++MODULE_AUTHOR("qpz <aric.pzqi@ingenic.com>");
++MODULE_DESCRIPTION("A low-level driver for SmartSens sc230ai sensors");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/platform/Kconfig b/module_drivers/drivers/media/platform/Kconfig
+new file mode 100644
+index 000000000..1296b5b56
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/Kconfig
+@@ -0,0 +1,41 @@
++menu "[ISP] Drivers"
++
++
++config VIDEO_INGENIC_ISP
++        tristate "V4L2 Driver for ingenic isp"
++        depends on VIDEO_DEV && VIDEO_V4L2
++	depends on SOC_X2000_V12 || SOC_X2000 || SOC_M300 || SOC_X2100
++        select VIDEOBUF2_DMA_CONTIG
++        select VIDEOBUF2_DMA_CONTIG_INGENIC
++source "module_drivers/drivers/media/platform/ingenic-isp/Kconfig"
++
++
++config VIDEO_INGENIC_ISP_V2
++        tristate "V4L2 Driver for ingenic isp version 2"
++        depends on VIDEO_DEV && VIDEO_V4L2
++	depends on SOC_X2500
++        select VIDEOBUF2_DMA_CONTIG
++        select VIDEOBUF2_DMA_CONTIG_INGENIC
++source "module_drivers/drivers/media/platform/ingenic-isp-v2/Kconfig"
++endmenu
++
++menu "[CIM] Drivers"
++	depends on SOC_X2000_V12 || SOC_X2000 || SOC_M300 || SOC_X1600 || SOC_X2100
++source "module_drivers/drivers/media/platform/ingenic-cim/Kconfig"
++endmenu
++
++
++menu "[Rotator] Drivers"
++	depends on SOC_X2000_V12 || SOC_X2000 || SOC_M300 || SOC_X2100
++source "module_drivers/drivers/media/platform/ingenic-rotate/Kconfig"
++endmenu
++
++menu "[I2D] Drivers"
++	depends on SOC_X2500
++source "module_drivers/drivers/media/platform/ingenic-i2d/Kconfig"
++endmenu
++
++menu "[VPU] Drivers"
++	depends on SOC_X2000_V12 || SOC_X2000 || SOC_M300 || SOC_X2100
++source "module_drivers/drivers/media/platform/ingenic-vcodec/Kconfig"
++endmenu
+diff --git a/module_drivers/drivers/media/platform/Makefile b/module_drivers/drivers/media/platform/Makefile
+new file mode 100644
+index 000000000..9defda6d7
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/Makefile
+@@ -0,0 +1,6 @@
++obj-$(CONFIG_VIDEO_INGENIC_ISP) += ingenic-isp/
++obj-$(CONFIG_VIDEO_INGENIC_ISP_V2) += ingenic-isp-v2/
++obj-$(CONFIG_VIDEO_INGENIC_ROTATE) 		+= ingenic-rotate/
++obj-$(CONFIG_VIDEO_INGENIC_VCODEC)	+= ingenic-vcodec/
++obj-$(CONFIG_INGENIC_I2D) 		+= ingenic-i2d/
++obj-$(CONFIG_VIDEO_INGENIC_CIM)		+= ingenic-cim/
+diff --git a/module_drivers/drivers/media/platform/ingenic-cim/Kconfig b/module_drivers/drivers/media/platform/ingenic-cim/Kconfig
+new file mode 100644
+index 000000000..c230a6a98
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-cim/Kconfig
+@@ -0,0 +1,82 @@
++config VIDEO_INGENIC_CIM
++	tristate "Ingenic Soc Camera Driver for X2000 && M300 && X1600"
++	select VIDEOBUF2_DMA_CONTIG_INGENIC
++	select V4L2_FWNODE
++	help
++		CIM Driver for X2000 && M300 && X1600
++
++config CAMERA_USE_SNAPSHOT
++	bool "Sensor support snapshot function"
++	depends on VIDEO_INGENIC_CIM
++	help
++		Sensor support snapshot function
++
++config SNAPSHOT_PULSE_WIDTH
++        int "Snapshot pulse width"
++        depends on CAMERA_USE_SNAPSHOT
++        default 8
++        help
++          Snapshot pulse width
++
++config SNAPSHOT_FRAME_DELAY
++        int "One frame end delay"
++        depends on CAMERA_USE_SNAPSHOT
++        default 100
++        help
++          One frame end delay
++
++menuconfig PANDA_CAMERA_BOARD
++	bool "panda_camera_board"
++	depends on VIDEO_INGENIC_CIM
++	depends on SOC_X1600
++	default n
++	help
++	  Say Y here to enable support for panda_camera_boards.
++
++config RD_X1600_PANDA_MIPI_CAMERA_1V0
++	bool "panda camera driver for RD_X1600_PANDA_MIPI_CAMERA_1V0"
++	depends on PANDA_CAMERA_BOARD
++	select INGENIC_CIM_CAMERA_OV5645
++
++config RD_X1600_PANDA_MIPI_CAMERA_2V0
++	bool "panda camera driver for RD_X1600_PANDA_MIPI_CAMERA_2V0"
++	depends on PANDA_CAMERA_BOARD
++	select INGENIC_CIM_CAMERA_OV9281
++
++config RD_X1600_PANDA_MIPI_CAMERA_3V2
++	bool "panda camera driver for RD_X1600_PANDA_MIPI_CAMERA_3V2"
++	depends on PANDA_CAMERA_BOARD
++	select INGENIC_CIM_CAMERA_OV4689
++
++config RD_X1600_PANDA_DVP_CAMERA_1V0
++	bool "panda camera driver for RD_X1600_PANDA_DVP_CAMERA_V1.0"
++	depends on PANDA_CAMERA_BOARD
++	select INGENIC_CIM_CAMERA_SC031GS
++
++config RD_X1600_PANDA_DVP_CAMERA_AND_LCD_1V0
++	bool "panda camera driver for RD_X1600_PANDA_DVP_CAMERA_AND_LCD_V1.0"
++	depends on PANDA_CAMERA_BOARD
++	select INGENIC_CIM_CAMERA_OV5640
++
++config RD_X1600_PANDA_DVP_CAMERA_2V0
++	bool "panda camera driver for RD_X1600_PANDA_DVP_CAMERA_V2.0"
++	depends on PANDA_CAMERA_BOARD
++	select INGENIC_CIM_CAMERA_OV9281_DVP_SNAPSHOT
++
++menuconfig HALLEY6_CAMERA_BOARD
++	bool "halley6_camera_board"
++	depends on VIDEO_INGENIC_CIM
++	depends on SOC_X1600
++	default n
++	help
++	  Say Y here to enable support for panda_camera_boards.
++
++config RD_X1600_HALLEY6_MIPI_CAMERA
++	bool "halley6 camera driver for RD_X1600_HALLEY6_MIPI_CAMERA"
++	depends on HALLEY6_CAMERA_BOARD
++	select INGENIC_CIM_CAMERA_MIPI_SC031GS
++
++config RD_X1600_HALLEY6_DVP_CAMERA
++	bool "halley6 camera driver for RD_X1600_HALLEY6_DVP_CAMERA"
++	depends on HALLEY6_CAMERA_BOARD
++	select INGENIC_CIM_CAMERA_SC031GS
+diff --git a/module_drivers/drivers/media/platform/ingenic-cim/Makefile b/module_drivers/drivers/media/platform/ingenic-cim/Makefile
+new file mode 100644
+index 000000000..520cd2c08
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-cim/Makefile
+@@ -0,0 +1,2 @@
++obj-y	+= ingenic_camera.o mipi_csi.o
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-cim/ingenic_camera.c b/module_drivers/drivers/media/platform/ingenic-cim/ingenic_camera.c
+new file mode 100644
+index 000000000..6b016518b
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-cim/ingenic_camera.c
+@@ -0,0 +1,2566 @@
++/*
++ * Copyright (c) 2012 Ingenic Semiconductor Co., Ltd.
++ *              http://www.ingenic.com/
++ *
++ * Core file for Ingenic Display Controller driver
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/types.h>
++#include <linux/dma-mapping.h>
++#include <linux/mutex.h>
++#include <linux/version.h>
++#include <linux/platform_device.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/device.h>
++#include <linux/gpio.h>
++#include <linux/interrupt.h>
++#include <linux/slab.h>
++#include <linux/time.h>
++#include <asm/dma.h>
++#include <asm/page.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-common.h>
++#include <media/v4l2-dev.h>
++#include <media/videobuf2-v4l2.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++#include <media/ingenic_video_nr.h>
++#include "ingenic_camera.h"
++#include "mipi_csi.h"
++#include <linux/of_reserved_mem.h>
++#include <linux/of.h>
++#include <linux/of_graph.h>
++#include <asm/mach-generic/spaces.h>
++
++
++
++int max_buffer_num = 3;
++module_param(max_buffer_num, int, 0644);
++MODULE_PARM_DESC(max_buffer_num, "cim max buffer number");
++
++static int frame_size_check_flag = 0;
++static int showFPS = 0;
++
++struct cim_video_format cim_formats[] = {
++	/*MONO */
++	{
++		.name     = "Y8, GREY",
++		.fourcc   = V4L2_PIX_FMT_GREY,
++		.depth    = {8},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_Y8_1X8,
++		.colorspace = V4L2_COLORSPACE_RAW,
++	},
++	{
++		.name     = "Y10, Y10 ",
++		.fourcc   = V4L2_PIX_FMT_Y10,
++		.depth    = {10},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_Y10_1X10,
++		.colorspace = V4L2_COLORSPACE_RAW,
++	},
++	{
++		.name     = "Y12, Y12 ",
++		.fourcc   = V4L2_PIX_FMT_Y12,
++		.depth    = {12},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_Y12_1X12,
++		.colorspace = V4L2_COLORSPACE_RAW,
++	},
++	/*yuv422 */
++	{
++		.name     = "YUV422, YUYV",
++		.fourcc   = V4L2_PIX_FMT_YUYV,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	{
++		.name     = "YUV422, YVYU",
++		.fourcc   = V4L2_PIX_FMT_YVYU,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	{
++		.name     = "YUV422, UYVY",
++		.fourcc   = V4L2_PIX_FMT_UYVY,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	{
++		.name     = "YUV422, VYUY",
++		.fourcc   = V4L2_PIX_FMT_VYUY,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	/*RGB*/
++	{
++		.name     = "RGB565, RGBP",
++		.fourcc   = V4L2_PIX_FMT_RGB565,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	{
++		.name     = "RBG565, RBGP",
++		.fourcc   = INGENIC_V4L2_PIX_FMT_RBG565,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = INGENIC_MEDIA_BUS_FMT_RBG565_2X8_LE,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	{
++		.name     = "BGR565, BGRP",
++		.fourcc   = INGENIC_V4L2_PIX_FMT_BGR565,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_BGR565_2X8_LE,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	{
++		.name     = "BRG565, BRGP",
++		.fourcc   = INGENIC_V4L2_PIX_FMT_BRG565,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = INGENIC_MEDIA_BUS_FMT_BRG565_2X8_LE,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	{
++		.name     = "GRB565, GRBP",
++		.fourcc   = INGENIC_V4L2_PIX_FMT_GRB565,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = INGENIC_MEDIA_BUS_FMT_GRB565_2X8_LE,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	{
++		.name     = "GBR565, GBRP",
++		.fourcc   = INGENIC_V4L2_PIX_FMT_GBR565,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = INGENIC_MEDIA_BUS_FMT_GBR565_2X8_LE,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	{
++		.name     = "GBR888, GBR3",
++		.fourcc   = V4L2_PIX_FMT_RGB24,
++		.depth    = {24},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_RGB888_1X24,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	/* RAW8 */
++	{
++		.name     = "RAW8, 8  BGBG.. GRGR..",
++		.fourcc   = V4L2_PIX_FMT_SBGGR8,
++		.depth    = {8},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW8, 8  GBGB.. RGRG..",
++		.fourcc   = V4L2_PIX_FMT_SGBRG8,
++		.depth    = {8},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW8, 8  GRGR.. BGBG..",
++		.fourcc   = V4L2_PIX_FMT_SGRBG8,
++		.depth    = {8},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW8, 8  RGRG.. GBGB..",
++		.fourcc   = V4L2_PIX_FMT_SRGGB8,
++		.depth    = {8},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	/* RAW10 */
++	{
++		.name     = "RAW10, 10  BGBG.. GRGR..",
++		.fourcc   = V4L2_PIX_FMT_SBGGR10,
++		.depth    = {10},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW10, 10  GBGB.. RGRG..",
++		.fourcc   = V4L2_PIX_FMT_SGBRG10,
++		.depth    = {10},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW10, 10  GRGR.. BGBG..",
++		.fourcc   = V4L2_PIX_FMT_SGRBG10,
++		.depth    = {10},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW10, 10  RGRG.. GBGB..",
++		.fourcc   = V4L2_PIX_FMT_SRGGB10,
++		.depth    = {10},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	/* RAW12 */
++	{
++		.name     = "RAW12, 12  BGBG.. GRGR..",
++		.fourcc   = V4L2_PIX_FMT_SBGGR12,
++		.depth    = {12},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW12, 12  GBGB.. RGRG..",
++		.fourcc   = V4L2_PIX_FMT_SGBRG12,
++		.depth    = {12},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW12, 12  GRGR.. BGBG..",
++		.fourcc   = V4L2_PIX_FMT_SGRBG12,
++		.depth    = {12},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW12, 12  RGRG.. GBGB..",
++		.fourcc   = V4L2_PIX_FMT_SRGGB12,
++		.depth    = {12},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++};
++
++
++static struct ingenic_camera_dev *v4l2_dev_to_pcdev(struct v4l2_device *v4l2_dev)
++{
++	return container_of(v4l2_dev, struct ingenic_camera_dev, v4l2_dev);
++}
++
++static struct cim_video_ctx *ctrl_to_ctx(struct v4l2_ctrl *ctrl)
++{
++	return container_of(ctrl->handler, struct cim_video_ctx, hdl);
++}
++
++static int get_asd_index(struct v4l2_async_subdev *asd)
++{
++	struct cim_async_subdev *casd = container_of(asd, struct cim_async_subdev, asd);
++	return casd->index;
++}
++
++static int is_cim_disabled(struct ingenic_camera_dev *pcdev)
++{
++	return !(cim_readl(pcdev, CIM_ST) & CIM_ST_WORKING);
++}
++
++static int ingenic_cim_get_video_nr(int index)
++{
++	if(index == 0)
++		return INGENIC_CIM_VIDEO_NR_0;
++	else if(index == 1)
++		return INGENIC_CIM_VIDEO_NR_1;
++	else
++		return 0;
++}
++
++void cim_dump_reg(struct ingenic_camera_dev *pcdev)
++{
++	if(!pcdev) {
++		printk("===>>%s,%d pcdev is NULL!\n",__func__,__LINE__);
++		return;
++	}
++	printk("\n***************************************\n");
++	printk("GLB_CFG			0x%08x\n", cim_readl(pcdev, GLB_CFG));
++	printk("FRM_SIZE		0x%08x\n", cim_readl(pcdev, FRM_SIZE));
++	printk("CROP_SITE		0x%08x\n", cim_readl(pcdev, CROP_SITE));
++	printk("RESIZE_CFG		0x%08x\n", cim_readl(pcdev, RESIZE_CFG));
++	printk("RESIZE_COEF_X		0x%08x\n", cim_readl(pcdev, RESIZE_COEF_X));
++	printk("RESIZE_COEF_Y		0x%08x\n", cim_readl(pcdev, RESIZE_COEF_Y));
++	printk("SCAN_CFG		0x%08x\n", cim_readl(pcdev, SCAN_CFG));
++	printk("QOS_CTRL		0x%08x\n", cim_readl(pcdev, QOS_CTRL));
++	printk("QOS_CFG			0x%08x\n", cim_readl(pcdev, QOS_CFG));
++	printk("DLY_CFG			0x%08x\n", cim_readl(pcdev, DLY_CFG));
++	printk("DES_ADDR		0x%08x\n", cim_readl(pcdev, DES_ADDR));
++	printk("CIM_ST			0x%08x\n", cim_readl(pcdev, CIM_ST));
++	printk("CIM_CLR_ST		0x%08x\n", cim_readl(pcdev, CIM_CLR_ST));
++	printk("CIM_INTC		0x%08x\n", cim_readl(pcdev, CIM_INTC));
++	printk("INT_FLAG		0x%08x\n", cim_readl(pcdev, INT_FLAG));
++	printk("FRAME_ID		0x%08x\n", cim_readl(pcdev, FRAME_ID));
++	printk("ACT_SIZE		0x%08x\n", cim_readl(pcdev, ACT_SIZE));
++	printk("DBG_CGC			0x%08x\n", cim_readl(pcdev, DBG_CGC));
++	printk("***************************************\n\n");
++}
++
++void cim_dump_reg_des(struct ingenic_camera_dev *pcdev)
++{
++	int version = pcdev->cim_priv->version_num;
++	printk("\n***************************************\n");
++	printk("DBG_DES next		0x%08x\n", cim_readl(pcdev, DBG_DES));
++	printk("DBG_DES WRBK_ADDR:	0x%08x\n", cim_readl(pcdev, DBG_DES));
++	printk("DBG_DES WRBK_STRD:	0x%08x\n", cim_readl(pcdev, DBG_DES));
++	printk("DBG_DES DES_INTC_t:	0x%08x\n", cim_readl(pcdev, DBG_DES));
++	printk("DBG_DES DES_CFG_t:	0x%08x\n", cim_readl(pcdev, DBG_DES));
++	if (version == 2) {
++		printk("DES_HIST_CFG_t:		0x%08x\n", cim_readl(pcdev, DBG_DES));
++		printk("HIST_WRBK_ADDR:		0x%08x\n", cim_readl(pcdev, DBG_DES));
++	} else {
++		printk("DES_HIST_CFG_t:		0x%08x\n", cim_readl(pcdev, DBG_DES));
++		printk("HIST_WRBK_ADDR:		0x%08x\n", cim_readl(pcdev, DBG_DES));
++	}
++	printk("SF_WRBK_ADDR:		0x%08x\n", cim_readl(pcdev, DBG_DES));
++	printk("DBG_DMA:		0x%08x\n", cim_readl(pcdev, DBG_DMA));
++	printk("***************************************\n\n");
++}
++
++void cim_dump_des(struct ingenic_camera_dev *pcdev)
++{
++	struct ingenic_camera_desc_v1 *desc_v1 = NULL;
++	struct ingenic_camera_desc_v2 *desc_v2 = NULL;
++	int i;
++	int version = pcdev->cim_priv->version_num;
++	if (version == 1) {
++		desc_v1 = (struct ingenic_camera_desc_v1 *)pcdev->desc_vaddr;
++		printk("\n***************************************\n");
++		for(i = 0; i < pcdev->buf_cnt; i++) {
++			printk("print des %d\n",i);
++			printk("next:			0x%08x\n", desc_v1[i].next);
++			printk("WRBK_ADDR:		0x%08x\n", desc_v1[i].WRBK_ADDR);
++			printk("WRBK_STRD:		0x%08x\n", desc_v1[i].WRBK_STRD);
++			printk("DES_INTC_t:		0x%08x\n", desc_v1[i].DES_INTC_t.d32);
++			printk("DES_CFG_t:		0x%08x\n", desc_v1[i].DES_CFG_t.d32);
++			printk("DES_HIST_CFG_t:		0x%08x\n", desc_v1[i].DES_HIST_CFG_t.d32);
++			printk("HIST_WRBK_ADDR:		0x%08x\n", desc_v1[i].HIST_WRBK_ADDR);
++			printk("SF_WRBK_ADDR:		0x%08x\n", desc_v1[i].SF_WRBK_ADDR);
++		}
++		printk("***************************************\n\n");
++	} else {
++		desc_v2 = (struct ingenic_camera_desc_v2 *)pcdev->desc_vaddr;
++		printk("\n***************************************\n");
++		for(i = 0; i < pcdev->buf_cnt; i++) {
++			printk("print des %d\n",i);
++			printk("next:			0x%08x\n", desc_v2[i].next);
++			printk("WRBK_ADDR:		0x%08x\n", desc_v2[i].WRBK_ADDR);
++			printk("WRBK_STRD:		0x%08x\n", desc_v2[i].WRBK_STRD);
++			printk("DES_INTC_t:		0x%08x\n", desc_v2[i].DES_INTC_t.d32);
++			printk("DES_CFG_t:		0x%08x\n", desc_v2[i].DES_CFG_t.d32);
++			printk("DES_LUMI_CFG_t:		0x%08x\n", desc_v2[i].DES_LUMI_CFG_t.d32);
++			printk("LUMI_WRBK_ADDR:		0x%08x\n", desc_v2[i].LUMI_WRBK_ADDR);
++			printk("SF_WRBK_ADDR:		0x%08x\n", desc_v2[i].SF_WRBK_ADDR);
++		}
++		printk("***************************************\n\n");
++	}
++}
++
++static void calculate_frame_rate(void)
++{
++	static ktime_t time_now, time_last;
++	unsigned int interval_in_us;
++	static unsigned int fpsCount = 0;
++
++	switch(showFPS){
++	case 1:
++		fpsCount++;
++		time_now = ktime_get();
++		interval_in_us =time_now - time_last;
++		if ( interval_in_us > (NSEC_PER_SEC) ) { /* 1 second = 1000000 us. */
++			printk(" CIM FPS: %d\n",fpsCount);
++			fpsCount = 0;
++			time_last = time_now;
++		}
++		break;
++	case 2:
++		time_now = ktime_get();
++		interval_in_us =time_now - time_last;
++		printk(" CIM tow frame interval in ns: %d\n",interval_in_us);
++		time_last = time_now;
++		break;
++	default:
++		if (showFPS > 2) {
++			int d, f;
++			fpsCount++;
++			time_now = ktime_get();
++			interval_in_us =time_now - time_last;
++			if (interval_in_us > NSEC_PER_SEC * showFPS ) { /* 1 second = 1000000 us. */
++				d = fpsCount / showFPS;
++				f = (fpsCount * 10) / showFPS - d * 10;
++				printk(" CIM FPS: %d.%01d\n", d, f);
++				fpsCount = 0;
++				time_last = time_now;
++			}
++		}
++		break;
++	}
++}
++
++
++
++static unsigned int fourcc_to_mbus_code(unsigned int fourcc){
++	const struct cim_video_format *fmt = NULL;
++	int i;
++	for(i=0; i<ARRAY_SIZE(cim_formats); i++)
++	{
++		fmt = &cim_formats[i];
++		if(fourcc ==fmt->fourcc)
++			return fmt->mbus_code;
++	}
++	return 0;
++}
++
++static unsigned int fourcc_to_mbus_depth(unsigned int fourcc){
++	const struct cim_video_format *fmt = NULL;
++	int i;
++	for(i=0; i<ARRAY_SIZE(cim_formats); i++)
++	{
++		fmt = &cim_formats[i];
++		if(fourcc ==fmt->fourcc)
++			return fmt->depth[0];
++	}
++	return 0;
++}
++
++
++static int ingenic_camera_alloc_desc(struct ingenic_camera_dev *pcdev, unsigned int count)
++{
++
++	int desc_size = 0;
++	pcdev->buf_cnt = count;
++	if (pcdev->cim_priv->version_num == 2) {
++		desc_size = sizeof(struct ingenic_camera_desc_v2);
++		pcdev->desc_vaddr = dma_alloc_coherent(pcdev->v4l2_dev.dev,
++				desc_size * pcdev->buf_cnt,
++				(dma_addr_t *)&pcdev->desc_v2_paddr, GFP_KERNEL);
++		if (!pcdev->desc_v2_paddr)
++			return -ENOMEM;
++	} else {
++		desc_size = sizeof(struct ingenic_camera_desc_v1);
++		pcdev->desc_vaddr = dma_alloc_coherent(pcdev->v4l2_dev.dev,
++				desc_size * pcdev->buf_cnt,
++				(dma_addr_t *)&pcdev->desc_v1_paddr, GFP_KERNEL);
++		if (!pcdev->desc_v1_paddr)
++			return -ENOMEM;
++	}
++
++	return 0;
++}
++
++static void ingenic_camera_free_desc(struct ingenic_camera_dev *pcdev)
++{
++	int desc_size = 0;
++	if (pcdev->cim_priv->version_num == 2) {
++		desc_size = sizeof(struct ingenic_camera_desc_v2);
++
++		if(pcdev && pcdev->desc_vaddr) {
++			dma_free_coherent(pcdev->v4l2_dev.dev,
++					desc_size * pcdev->buf_cnt,
++					pcdev->desc_vaddr, (dma_addr_t )pcdev->desc_v2_paddr);
++
++			pcdev->desc_vaddr = NULL;
++		}
++	} else {
++		desc_size = sizeof(struct ingenic_camera_desc_v1);
++		if (pcdev && pcdev->desc_vaddr) {
++			dma_free_coherent(pcdev->v4l2_dev.dev,
++					desc_size * pcdev->buf_cnt,
++					pcdev->desc_vaddr, (dma_addr_t )pcdev->desc_v1_paddr);
++
++			pcdev->desc_vaddr = NULL;
++		}
++	}
++}
++
++static int ingenic_init_desc(struct vb2_buffer *vb2) {
++	struct cim_video_ctx *ctx = vb2_get_drv_priv(vb2->vb2_queue);
++	struct v4l2_pix_format *user_fmt = &ctx->format.fmt.pix;
++	struct ingenic_camera_dev *pcdev = ctx->cimvideo.pcdev;
++	struct ingenic_camera_desc_v1 *desc_v1;
++	struct ingenic_camera_desc_v2 *desc_v2;
++	dma_addr_t dma_address;
++	u32 index = vb2->index;
++	u32 pixfmt = user_fmt->pixelformat;
++	u32 sizeimage = user_fmt->sizeimage;
++	u32 user_width = user_fmt->width;
++
++	dma_address = *(dma_addr_t *)vb2_plane_cookie(vb2, 0);
++	if(!dma_address) {
++		dev_err(ctx->cimvideo.dev, "Failed to setup DMA address\n");
++		return -ENOMEM;
++	}
++
++	if (pcdev->cim_priv->version_num == 2) {
++		desc_v2 = (struct ingenic_camera_desc_v2 *) pcdev->desc_vaddr;
++		desc_v2[index].DES_CFG_t.data.ID = index;
++		desc_v2[index].WRBK_ADDR = dma_address;
++	} else {
++		desc_v1 = (struct ingenic_camera_desc_v1 *) pcdev->desc_vaddr;
++		desc_v1[index].DES_CFG_t.data.ID = index;
++		desc_v1[index].WRBK_ADDR = dma_address;
++	}
++
++	switch (pixfmt){
++		case V4L2_PIX_FMT_RGB565:
++		case INGENIC_V4L2_PIX_FMT_RBG565:
++		case INGENIC_V4L2_PIX_FMT_BGR565:
++		case INGENIC_V4L2_PIX_FMT_BRG565:
++		case INGENIC_V4L2_PIX_FMT_GRB565:
++		case INGENIC_V4L2_PIX_FMT_GBR565:
++			if (pcdev->cim_priv->version_num == 2) {
++				desc_v2[index].DES_CFG_t.data.WRBK_FMT = WRBK_FMT_RGB565;
++			} else {
++				desc_v1[index].DES_CFG_t.data.WRBK_FMT = WRBK_FMT_RGB565;
++			}
++			break;
++		case V4L2_PIX_FMT_RGB32:
++			if (pcdev->cim_priv->version_num == 2) {
++				desc_v2[index].DES_CFG_t.data.WRBK_FMT = WRBK_FMT_RGB888;
++			} else {
++				desc_v1[index].DES_CFG_t.data.WRBK_FMT = WRBK_FMT_RGB888;
++			}
++			break;
++		case V4L2_PIX_FMT_YUYV:
++		case V4L2_PIX_FMT_YVYU:
++		case V4L2_PIX_FMT_UYVY:
++		case V4L2_PIX_FMT_VYUY:
++			if (pcdev->cim_priv->version_num == 2) {
++				desc_v2[index].DES_CFG_t.data.WRBK_FMT = WRBK_FMT_YUV422;
++			} else {
++				desc_v1[index].DES_CFG_t.data.WRBK_FMT = WRBK_FMT_YUV422;
++			}
++			break;
++		case V4L2_PIX_FMT_GREY:
++		case V4L2_PIX_FMT_SBGGR8:
++		case V4L2_PIX_FMT_SGBRG8:
++		case V4L2_PIX_FMT_SGRBG8:
++		case V4L2_PIX_FMT_SRGGB8:
++		case V4L2_PIX_FMT_SBGGR10:
++		case V4L2_PIX_FMT_SGBRG10:
++		case V4L2_PIX_FMT_SGRBG10:
++		case V4L2_PIX_FMT_SRGGB10:
++			if (pcdev->cim_priv->version_num == 2) {
++				desc_v2[index].DES_CFG_t.data.WRBK_FMT = WRBK_FMT_MONO;
++			} else {
++				desc_v1[index].DES_CFG_t.data.WRBK_FMT = WRBK_FMT_MONO;
++			}
++			break;
++		default:
++			dev_err(ctx->cimvideo.dev, "No support format!\n");
++			return -EINVAL;
++	}
++
++	if(pcdev->cim_priv->version_num == 2 && ctx->output_y == 1)
++		desc_v2[index].DES_CFG_t.data.WRBK_FMT = WRBK_FMT_Y;
++
++
++	if(pcdev->cim_priv->version_num == 1 && !pcdev->desc_v1_head &&
++			!pcdev->desc_v1_tail) {
++		pcdev->desc_v1_head = &desc_v1[index];
++		pcdev->desc_v1_tail = &desc_v1[index];
++		desc_v1[index].DES_INTC_t.data.EOF_MSK = 0;
++		desc_v1[index].DES_CFG_t.data.DES_END = 1;
++		desc_v1[index].next = 0;
++	} else if(pcdev->cim_priv->version_num == 1 && pcdev->desc_v1_head != NULL &&
++			pcdev->desc_v1_tail != NULL) {
++		pcdev->desc_v1_tail->next = (dma_addr_t)(&pcdev->desc_v1_paddr[index]);
++		v4l2_async_notifier_init(&pcdev->notifier);
++		pcdev->desc_v1_tail->DES_INTC_t.data.EOF_MSK = 1;
++		pcdev->desc_v1_tail->DES_CFG_t.data.DES_END = 0;
++		pcdev->desc_v1_tail = &desc_v1[index];
++
++		desc_v1[index].DES_INTC_t.data.EOF_MSK = 0;
++		desc_v1[index].DES_CFG_t.data.DES_END = 1;
++		desc_v1[index].next = 0;
++	} else if (pcdev->cim_priv->version_num == 2 && !pcdev->desc_v2_head &&
++			!pcdev->desc_v2_tail) {
++		pcdev->desc_v2_head = &desc_v2[index];
++		pcdev->desc_v2_tail = &desc_v2[index];
++		desc_v2[index].DES_INTC_t.data.EOF_MSK = 0;
++		desc_v2[index].DES_CFG_t.data.DES_END = 1;
++		desc_v2[index].next = 0;
++	} else if(pcdev->cim_priv->version_num == 2 && pcdev->desc_v2_head != NULL &&
++			pcdev->desc_v2_tail != NULL) {
++		pcdev->desc_v2_tail->next = (dma_addr_t)(&pcdev->desc_v2_paddr[index]);
++		pcdev->desc_v2_tail->DES_INTC_t.data.EOF_MSK = 1;
++		pcdev->desc_v2_tail->DES_CFG_t.data.DES_END = 0;
++		pcdev->desc_v2_tail = &desc_v2[index];
++
++		desc_v2[index].DES_INTC_t.data.EOF_MSK = 0;
++		desc_v2[index].DES_CFG_t.data.DES_END = 1;
++		desc_v2[index].next = 0;
++	}
++
++	if(pcdev->cim_priv->version_num == 2) {
++		if(!ctx->lumi_en) {
++			desc_v2[index].DES_LUMI_CFG_t.d32 = 0;
++			desc_v2[index].LUMI_WRBK_ADDR = 0;
++		} else {
++			desc_v2[index].DES_LUMI_CFG_t.LUMI_EN = 1;
++			desc_v2[index].LUMI_WRBK_ADDR
++				= desc_v2[index].WRBK_ADDR + sizeimage;
++		}
++
++		if(!ctx->interlace) {
++			desc_v2[index].WRBK_STRD = user_width;
++			desc_v2[index].SF_WRBK_ADDR = 0;
++		} else {
++			desc_v2[index].WRBK_STRD = user_width * 2;
++			desc_v2[index].SF_WRBK_ADDR =
++				desc_v2[index].WRBK_ADDR + user_width * 2;
++		}
++	} else {
++		if(!ctx->hist_en) {
++			desc_v1[index].DES_HIST_CFG_t.d32 = 0;
++			desc_v1[index].HIST_WRBK_ADDR = 0;
++		} else {
++			if(pixfmt != V4L2_PIX_FMT_YUYV &&
++					pixfmt != V4L2_PIX_FMT_GREY) {
++				dev_err(ctx->cimvideo.dev,"fmt not support hist!\n");
++				return -EINVAL;
++			}
++			desc_v1[index].DES_HIST_CFG_t.HIST_EN = 1;
++			desc_v1[index].DES_HIST_CFG_t.GAIN_MUL = ctx->hist_gain_mul;
++			desc_v1[index].DES_HIST_CFG_t.GAIN_ADD = ctx->hist_gain_add;
++			desc_v1[index].HIST_WRBK_ADDR
++				= desc_v1[index].WRBK_ADDR + sizeimage;
++		}
++
++		if(!ctx->interlace) {
++			desc_v1[index].WRBK_STRD = user_width;
++			desc_v1[index].SF_WRBK_ADDR = 0;
++		} else {
++			desc_v1[index].WRBK_STRD = user_width * 2;
++			desc_v1[index].SF_WRBK_ADDR =
++				desc_v1[index].WRBK_ADDR + user_width * 2;
++		}
++	}
++
++	return 0;
++}
++
++static int ingenic_camera_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct cim_video_ctx *ctx = ctrl_to_ctx(ctrl);
++	struct ingenic_camera_dev *pcdev = ctx->cimvideo.pcdev;
++	struct ingenic_camera_desc_v1 *desc_v1;
++	unsigned int tmp;
++	int i;
++	int expo_width = 0x08;
++	int dly_num = 0x80;
++
++	switch (ctrl->id) {
++		case INGENIC_CID_CROP_WAY:
++		//	img_sz->crop_way = ctrl->val;
++			break;
++		case INGENIC_CID_LUMI_EN:
++			ctx->lumi_en = 1;
++			break;
++		case INGENIC_CID_OUTPUT_Y:
++			ctx->output_y = 1;
++			break;
++		case INGENIC_CID_POINT1_X:
++			tmp = cim_readl(pcdev, LUMI_POINT1);
++			tmp &= ~0x7ff;
++			tmp |= ctrl->val;
++			cim_writel(pcdev, tmp, LUMI_POINT1);
++			break;
++		case INGENIC_CID_POINT1_Y:
++			tmp = cim_readl(pcdev, LUMI_POINT1);
++			tmp &= ~(0x7ff << 16);
++			tmp |= ctrl->val << 16;
++			cim_writel(pcdev, tmp, LUMI_POINT1);
++			break;
++		case INGENIC_CID_POINT2_X:
++			tmp = cim_readl(pcdev, LUMI_POINT2);
++			tmp &= ~0x7ff;
++			tmp |= ctrl->val;
++			cim_writel(pcdev, tmp, LUMI_POINT2);
++			break;
++		case INGENIC_CID_POINT2_Y:
++			tmp = cim_readl(pcdev, LUMI_POINT2);
++			tmp &= ~(0x7ff << 16);
++			tmp |= ctrl->val << 16;
++			cim_writel(pcdev, tmp, LUMI_POINT2);
++			break;
++		case INGENIC_CID_SNAPSHOT_EN:
++			if(!is_cim_disabled(pcdev)){
++				printk("too late to set snapshot mode\n");
++				return 0;
++			}
++			ctx->snapshot = 1;
++			tmp = cim_readl(pcdev, GLB_CFG);
++			tmp |= GLB_CFG_DAT_MODE;
++			tmp &= ~GLB_CFG_EXPO_WIDTH_MASK_V2;
++			tmp |= (expo_width << GLB_CFG_EXPO_WIDTH_LBIT);
++			cim_writel(pcdev, tmp, GLB_CFG);
++			tmp = dly_num;
++			tmp |= CIM_DLY_EN;
++			tmp |= CIM_DLY_MD;
++			cim_writel(pcdev, tmp, DLY_CFG);
++			break;
++		case INGENIC_CID_EXP_PULSE_W:
++			if(!is_cim_disabled(pcdev)){
++				printk("too late to set exposure width!\n");
++				return 0;
++			}
++			if(!ctx->snapshot)
++				return 0;
++			tmp = cim_readl(pcdev, GLB_CFG);
++			tmp &= ~GLB_CFG_EXPO_WIDTH_MASK_V2;
++			tmp |= ((ctrl->val & 0x1f) << GLB_CFG_EXPO_WIDTH_LBIT);
++			cim_writel(pcdev, tmp, GLB_CFG);
++			expo_width = ctrl->val;
++			break;
++		case INGENIC_CID_SNAPSHOT_DELAY_T:
++			if(!is_cim_disabled(pcdev)){
++				printk("too late to set delay number!\n");
++				return 0;
++			}
++			if(!ctx->snapshot)
++				return 0;
++			tmp = ctrl->val;
++			tmp |= CIM_DLY_EN;
++			tmp |= CIM_DLY_MD;
++			cim_writel(pcdev, tmp, DLY_CFG);
++			dly_num = ctrl->val;
++			break;
++		case INGENIC_CID_SCALE_SHARP:
++			tmp = cim_readl(pcdev,RESIZE_CFG);
++			tmp &= ~CIM_SHARPL_MASK;
++			tmp |= ctrl->val << CIM_SHARPL_LBIT;
++			cim_writel(pcdev, tmp, RESIZE_CFG);
++			break;
++		case INGENIC_CID_HIST_EN:
++			ctx->hist_en = 1;
++			break;
++		case INGENIC_CID_HIST_GAIN_ADD:
++			ctx->hist_gain_add = ctrl->val;
++			desc_v1 = (struct ingenic_camera_desc_v1 *) pcdev->desc_vaddr;
++			if(!ctx->hist_en || !desc_v1) {
++				dev_dbg(pcdev->dev, "setting hist_add are not satisfied!\n");
++				return 0;
++			}
++			for(i = 0; i < pcdev->buf_cnt; i++)
++				desc_v1[i].DES_HIST_CFG_t.GAIN_ADD = ctx->hist_gain_add;
++			break;
++		case INGENIC_CID_HIST_GAIN_MUL:
++			ctx->hist_gain_mul = ctrl->val;
++			desc_v1 = (struct ingenic_camera_desc_v1 *) pcdev->desc_vaddr;
++			if(!ctx->hist_en || !desc_v1) {
++				dev_dbg(pcdev->dev, "setting hist_mul are not satisfied!\n");
++				return 0;
++			}
++			for(i = 0; i < pcdev->buf_cnt; i++)
++				desc_v1[i].DES_HIST_CFG_t.GAIN_MUL = ctx->hist_gain_mul;
++			break;
++		default:
++			dev_err(pcdev->dev, "ctrl id not supported!\n");
++			break;
++	}
++	return 0;
++}
++
++static const struct v4l2_ctrl_ops ingenic_camera_ctrl_ops = {
++	.s_ctrl = ingenic_camera_s_ctrl,
++};
++
++static const struct v4l2_ctrl_config img_crop_way = {
++	.ops	= &ingenic_camera_ctrl_ops,
++	.id	= INGENIC_CID_CROP_WAY,
++	.name	= "crop way",
++	.type	= V4L2_CTRL_TYPE_INTEGER,
++	.def	= CROP_SPECIFY_ZONE,
++	.max	= CROP_BASE_MAX_PIC,
++	.min	= CROP_SPECIFY_ZONE,
++	.max	= CROP_BASE_MAX_PIC,
++	.step	= 1,
++};
++
++static const struct v4l2_ctrl_config lumi_en = {
++	.ops	= &ingenic_camera_ctrl_ops,
++	.id	= INGENIC_CID_LUMI_EN,
++	.type	= V4L2_CTRL_TYPE_BUTTON,
++	.name	= "lumi enable",
++};
++
++static const struct v4l2_ctrl_config output_y = {
++	.ops	= &ingenic_camera_ctrl_ops,
++	.id	= INGENIC_CID_OUTPUT_Y,
++	.type	= V4L2_CTRL_TYPE_BUTTON,
++	.name	= "output Y enable",
++};
++
++static const struct v4l2_ctrl_config point1_x = {
++	.ops	= &ingenic_camera_ctrl_ops,
++	.id	= INGENIC_CID_POINT1_X,
++	.type	= V4L2_CTRL_TYPE_INTEGER,
++	.name	= "point1 x-offset",
++	.def	= 0x78,
++	.min	= 0,
++	.max	= 0x7ff,
++	.step	= 1,
++};
++
++static const struct v4l2_ctrl_config point1_y = {
++	.ops	= &ingenic_camera_ctrl_ops,
++	.id	= INGENIC_CID_POINT1_Y,
++	.type	= V4L2_CTRL_TYPE_INTEGER,
++	.name	= "point1 y-offset",
++	.def	= 0x78,
++	.min	= 0,
++	.max	= 0x7ff,
++	.step	= 1,
++};
++
++static const struct v4l2_ctrl_config point2_x = {
++	.ops	= &ingenic_camera_ctrl_ops,
++	.id	= INGENIC_CID_POINT2_X,
++	.type	= V4L2_CTRL_TYPE_INTEGER,
++	.name	= "point2 x-offset",
++	.def	= 0xf0,
++	.min	= 0,
++	.max	= 0x7ff,
++	.step	= 1,
++};
++
++static const struct v4l2_ctrl_config point2_y = {
++	.ops	= &ingenic_camera_ctrl_ops,
++	.id	= INGENIC_CID_POINT2_Y,
++	.type	= V4L2_CTRL_TYPE_INTEGER,
++	.name	= "point2 y-offset",
++	.def	= 0xf0,
++	.min	= 0,
++	.max	= 0x7ff,
++	.step	= 1,
++};
++static const struct v4l2_ctrl_config snapshot_en = {
++	.ops	= &ingenic_camera_ctrl_ops,
++	.id	= INGENIC_CID_SNAPSHOT_EN,
++	.type	= V4L2_CTRL_TYPE_BUTTON,
++	.name	= "snapshot enable",
++};
++
++static const struct v4l2_ctrl_config exp_pulse_w= {
++	.ops	= &ingenic_camera_ctrl_ops,
++	.id	= INGENIC_CID_EXP_PULSE_W,
++	.name	= "pulse width",
++	.type	= V4L2_CTRL_TYPE_INTEGER,
++	.def	= 0xf,
++	.min	= 0x01,
++	.max	= 0x1f,
++	.step	= 1,
++};
++
++static const struct v4l2_ctrl_config delay_t= {
++	.ops	= &ingenic_camera_ctrl_ops,
++	.id	= INGENIC_CID_SNAPSHOT_DELAY_T,
++	.name	= "delay number",
++	.type	= V4L2_CTRL_TYPE_INTEGER,
++	.def	= 0x00,
++	.min	= 0x00,
++	.max	= 0x800000,
++	.step	= 1,
++};
++
++static const struct v4l2_ctrl_config img_scale_sharp = {
++	.ops	= &ingenic_camera_ctrl_ops,
++	.id	= INGENIC_CID_SCALE_SHARP,
++	.name	= "scale sharp",
++	.type	= V4L2_CTRL_TYPE_INTEGER,
++	.def	= 2,
++	.min	= 0,
++	.max	= 3,
++	.step	= 1,
++};
++
++static const struct v4l2_ctrl_config hist_en = {
++	.ops	= &ingenic_camera_ctrl_ops,
++	.id	= INGENIC_CID_HIST_EN,
++	.type	= V4L2_CTRL_TYPE_BUTTON,
++	.name	= "histgram enable",
++};
++
++static const struct v4l2_ctrl_config hist_gain_add = {
++	.ops	= &ingenic_camera_ctrl_ops,
++	.id	= INGENIC_CID_HIST_GAIN_ADD,
++	.name	= "hist gain add",
++	.type	= V4L2_CTRL_TYPE_INTEGER,
++	.def	= 0,
++	.min	= 0,
++	.max	= 0xff,
++	.step	= 1,
++};
++
++static const struct v4l2_ctrl_config hist_gain_mul = {
++	.ops	= &ingenic_camera_ctrl_ops,
++	.id	= INGENIC_CID_HIST_GAIN_MUL,
++	.name	= "hist gain mul",
++	.type	= V4L2_CTRL_TYPE_INTEGER,
++	.def	= 0x20,
++	.min	= 0,
++	.max	= 0xff,
++	.step	= 1,
++};
++
++
++static int ingenic_camera_wakeup(struct ingenic_camera_dev *pcdev) {
++	struct ingenic_buffer *buf = pcdev->active;
++	struct vb2_v4l2_buffer *vbuf = &pcdev->active->vb;
++	int id = cim_readl(pcdev, FRAME_ID);
++
++	if(!buf || vbuf->vb2_buf.index != id) {
++		dev_err(pcdev->dev, "cim buf synchronous problems!\n");
++		return -EINVAL;
++	}
++
++	list_del_init(&buf->list);
++	vbuf->vb2_buf.timestamp = ktime_get_ns();
++	vbuf->sequence = pcdev->sequence++;
++	vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_DONE);
++
++	return 0;
++}
++
++static irqreturn_t ingenic_camera_irq_handler(int irq, void *data) {
++	struct ingenic_camera_dev *pcdev = (struct ingenic_camera_dev *)data;
++	struct ingenic_camera_desc_v1 *desc_v1_p;
++	struct ingenic_camera_desc_v2 *desc_v2_p;
++	unsigned long status = 0;
++	unsigned long flags = 0;
++	unsigned long regval = 0;
++
++	spin_lock_irqsave(&pcdev->lock, flags);
++
++	/* read interrupt flag register */
++	status = cim_readl(pcdev,INT_FLAG);
++	if (!status) {
++		dev_err(pcdev->dev, "cim irq_flag is NULL! \n");
++		goto out;
++	}
++
++	if(status & CIM_INT_FLAG_EOW) {
++		cim_writel(pcdev, CIM_INT_FLAG_EOW, CIM_CLR_ST);
++
++		if(status & CIM_INT_FLAG_EOF) {
++			cim_writel(pcdev, CIM_INT_FLAG_EOF, CIM_CLR_ST);
++		}
++
++		if(ingenic_camera_wakeup(pcdev))
++			goto out;
++
++		if (list_empty(&pcdev->video_buffer_list)) {
++			pcdev->active = NULL;
++			goto out;
++		}
++
++		/* start next dma frame. */
++		if (pcdev->cim_priv->version_num == 2) {
++			desc_v2_p = pcdev->desc_v2_paddr;
++			regval = (unsigned long)(pcdev->desc_v2_head->next);
++			pcdev->desc_v2_head =
++				(struct ingenic_camera_desc_v2 *)((regval)|0xa0000000);
++		} else {
++			desc_v1_p = pcdev->desc_v1_paddr;
++			regval = (unsigned long)(pcdev->desc_v1_head->next);
++			pcdev->desc_v1_head =
++				(struct ingenic_camera_desc_v1 *)(regval|0xa0000000);
++		}
++
++		cim_writel(pcdev, regval, DES_ADDR);
++		cim_writel(pcdev, CIM_CTRL_START, CIM_CTRL);
++
++		pcdev->active =
++			list_entry(pcdev->video_buffer_list.next, struct ingenic_buffer, list);
++		goto out;
++	}
++
++	if(status & CIM_INT_FLAG_EOF) {
++		cim_writel(pcdev, CIM_INT_FLAG_EOF, CIM_CLR_ST);
++
++		if(ingenic_camera_wakeup(pcdev))
++			goto out;
++
++		pcdev->active =
++			list_entry(pcdev->video_buffer_list.next, struct ingenic_buffer, list);
++		if (pcdev->cim_priv->version_num == 2) {
++			pcdev->desc_v2_head =
++				(struct ingenic_camera_desc_v2 *)((pcdev->desc_v2_head->next)|0xa0000000);
++		} else
++			pcdev->desc_v1_head =
++				(struct ingenic_camera_desc_v1 *)((pcdev->desc_v1_head->next)|0xa0000000);
++
++		goto out;
++	}
++
++	if (status & CIM_INT_FLAG_SZ_ERR) {
++		unsigned int val;
++		val = cim_readl(pcdev, ACT_SIZE);
++		cim_writel(pcdev, CIM_CLR_SZ_ERR, CIM_CLR_ST);
++		dev_err(pcdev->dev, "cim size err! w = %d h = %d\n", val&0x3ff, val>>16&0x3ff);
++		goto out;
++	}
++
++	if (status & CIM_INT_FLAG_OVER) {
++		cim_writel(pcdev, CIM_INT_FLAG_OVER, CIM_CLR_ST);
++		dev_err(pcdev->dev, "cim overflow! \n");
++		goto out;
++	}
++
++	if(status & CIM_INT_FLAG_GSA) {
++		cim_writel(pcdev, CIM_INT_FLAG_GSA, CIM_CLR_ST);
++		printk("cim general stop! \n");
++		goto out;
++	}
++
++	if(status & CIM_INT_FLAG_SOF) {
++		cim_writel(pcdev, CIM_INT_FLAG_SOF, CIM_CLR_ST);
++		goto out;
++	}
++
++out:
++	spin_unlock_irqrestore(&pcdev->lock, flags);
++	return IRQ_HANDLED;
++}
++
++/*ioctl_ops*/
++static int ingenic_camera_querycap(struct file *file, void *fh,
++			       struct v4l2_capability *cap)
++{
++	struct cim_video_ctx *ctx = video_drvdata(file);
++
++	strlcpy(cap->driver, "ingenic-camera", sizeof(cap->driver));
++	cap->version = VERSION_CODE;
++	cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
++	cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
++
++	return 0;
++}
++
++static int ingenic_camera_enum_fmt_vid_cap(struct file *file, void *fh,
++		struct v4l2_fmtdesc *f)
++{
++	struct cim_video_ctx *ctx = video_drvdata(file);
++	struct cim_video_device *cimvideo = &ctx->cimvideo;
++	const struct cim_video_format *fmt = NULL;
++	struct v4l2_subdev_mbus_code_enum code = {
++		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
++	};
++	int i, ret = 0;
++
++	code.index = f->index;
++	ret = v4l2_subdev_call(cimvideo->subdev, pad, enum_mbus_code, NULL, &code);
++	if (ret < 0)
++		return -EINVAL;
++
++	for(i=0; i < ARRAY_SIZE(cim_formats); i++) {
++		fmt = &cim_formats[i];
++		if(fmt->mbus_code == code.code)
++		{
++			strlcpy(f->description, fmt->name, sizeof(f->description));
++			f->pixelformat = fmt->fourcc;
++			return 0;
++		}
++	}
++	return -EINVAL;
++}
++
++static int ingenic_camera_set_bus_param(struct cim_video_ctx *ctx) {
++	struct cim_video_device *cimvideo = &ctx->cimvideo;
++	struct v4l2_pix_format *user_fmt = &ctx->format.fmt.pix;
++	struct ingenic_camera_dev *pcdev = cimvideo->pcdev;
++	struct cim_async_subdev *casd = &pcdev->casd[cimvideo->index];
++	struct ingenic_image_sz *img_sz = &ctx->img_sz;
++	int version = pcdev->cim_priv->version_num;
++	unsigned long common_flags;
++	unsigned long glb_cfg = 0;
++	unsigned long tmp;
++	unsigned long intc = 0;
++
++	glb_cfg = cim_readl(pcdev,GLB_CFG);
++	if(casd->bus_type == V4L2_MBUS_CSI2_DPHY) {
++		/***Csi2 interface requirements***/
++		common_flags = V4L2_MBUS_MASTER |
++			V4L2_MBUS_HSYNC_ACTIVE_HIGH |
++			V4L2_MBUS_VSYNC_ACTIVE_HIGH |
++			V4L2_MBUS_PCLK_SAMPLE_RISING;
++		glb_cfg |= GLB_CFG_DAT_IF_SEL;
++
++	} else if(casd->bus_type == V4L2_MBUS_PARALLEL) {
++		common_flags = casd->parallel.flags;
++		glb_cfg &= ~GLB_CFG_DAT_IF_SEL;
++	} else if(casd->bus_type == V4L2_MBUS_BT656) {
++		common_flags = casd->parallel.flags;
++		if(common_flags & V4L2_MBUS_SLAVE) {
++			dev_err(cimvideo->dev, "bt656_mbus slave mode not supported!\n");
++			return -EINVAL;
++		}
++		glb_cfg &= ~GLB_CFG_DAT_IF_SEL;
++	} else {
++		dev_err(cimvideo->dev, "cim interface not supported!\n");
++		return -EINVAL;
++	}
++
++	/*PCLK Polarity Set*/
++	glb_cfg = (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) ?
++		(glb_cfg | GLB_CFG_DE_PCLK) : (glb_cfg & (~GLB_CFG_DE_PCLK));
++
++	/*VSYNC Polarity Set*/
++	glb_cfg = (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) ?
++		(glb_cfg | GLB_CFG_DL_VSYNC) : (glb_cfg & (~GLB_CFG_DL_VSYNC));
++
++	/*HSYNC Polarity Set*/
++	glb_cfg = (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) ?
++		(glb_cfg | GLB_CFG_DL_HSYNC) : (glb_cfg & (~GLB_CFG_DL_HSYNC));
++
++	glb_cfg &= (version == 1) ? (~GLB_CFG_C_ORDER_MASK_V1) : (~GLB_CFG_C_ORDER_MASK_V2);
++	glb_cfg &= (~GLB_CFG_C_ORDER_MASK_V1);
++
++	if(casd->bus_type != V4L2_MBUS_BT656) {
++		switch(fourcc_to_mbus_code(user_fmt->pixelformat)) {
++			case MEDIA_BUS_FMT_RGB565_2X8_LE:
++				glb_cfg |= (GLB_CFG_ORG_FMT_RGB565 | GLB_CFG_C_ORDER_RGB);
++				break;
++			case INGENIC_MEDIA_BUS_FMT_RBG565_2X8_LE:
++				glb_cfg |= (GLB_CFG_ORG_FMT_RGB565 | GLB_CFG_C_ORDER_RBG);
++				break;
++			case MEDIA_BUS_FMT_BGR565_2X8_LE:
++				glb_cfg |= (GLB_CFG_ORG_FMT_RGB565 | GLB_CFG_C_ORDER_BGR);
++				break;
++			case INGENIC_MEDIA_BUS_FMT_BRG565_2X8_LE:
++				glb_cfg |= (GLB_CFG_ORG_FMT_RGB565 | GLB_CFG_C_ORDER_BRG);
++				break;
++			case INGENIC_MEDIA_BUS_FMT_GRB565_2X8_LE:
++				glb_cfg |= (GLB_CFG_ORG_FMT_RGB565 | GLB_CFG_C_ORDER_GRB);
++				break;
++			case INGENIC_MEDIA_BUS_FMT_GBR565_2X8_LE:
++				glb_cfg |= (GLB_CFG_ORG_FMT_RGB565 | GLB_CFG_C_ORDER_GBR);
++				break;
++			case MEDIA_BUS_FMT_UYVY8_2X8:
++				glb_cfg |= (GLB_CFG_ORG_FMT_YUYV422 | GLB_CFG_C_ORDER_UYVY);
++				break;
++			case MEDIA_BUS_FMT_VYUY8_2X8:
++				glb_cfg |= (GLB_CFG_ORG_FMT_YUYV422 | GLB_CFG_C_ORDER_VYUY);
++				break;
++			case MEDIA_BUS_FMT_YUYV8_2X8:
++				glb_cfg |= (GLB_CFG_ORG_FMT_YUYV422 | GLB_CFG_C_ORDER_YUYV);
++				break;
++			case MEDIA_BUS_FMT_YVYU8_2X8:
++				glb_cfg |= (GLB_CFG_ORG_FMT_YUYV422 | GLB_CFG_C_ORDER_YVYU);
++				break;
++			case MEDIA_BUS_FMT_RGB888_1X24:
++				glb_cfg |= (GLB_CFG_ORG_FMT_RGB888 | GLB_CFG_C_ORDER_RGB);
++				break;
++			case MEDIA_BUS_FMT_Y8_1X8:
++				glb_cfg |= GLB_CFG_ORG_FMT_MONO;
++				break;
++			case MEDIA_BUS_FMT_Y10_1X10:
++				glb_cfg |= GLB_CFG_ORG_FMT_10BIT_MONO;
++				break;
++			case MEDIA_BUS_FMT_Y12_1X12:
++				glb_cfg |= GLB_CFG_ORG_FMT_12BIT_MONO;
++				break;
++			case MEDIA_BUS_FMT_SBGGR8_1X8:
++				glb_cfg |= (GLB_CFG_C_ORDER_BGGR | GLB_CFG_ORG_FMT_8BIT_RAW);
++				break;
++			case MEDIA_BUS_FMT_SGBRG8_1X8:
++				glb_cfg |= (GLB_CFG_C_ORDER_GBRG | GLB_CFG_ORG_FMT_8BIT_RAW);
++				break;
++			case MEDIA_BUS_FMT_SGRBG8_1X8:
++				glb_cfg |= (GLB_CFG_C_ORDER_GRBG | GLB_CFG_ORG_FMT_8BIT_RAW);
++				break;
++			case MEDIA_BUS_FMT_SRGGB8_1X8:
++				glb_cfg |= (GLB_CFG_C_ORDER_RGGB | GLB_CFG_ORG_FMT_8BIT_RAW);
++				break;
++			case MEDIA_BUS_FMT_SBGGR10_1X10:
++				glb_cfg |= (GLB_CFG_C_ORDER_BGGR | GLB_CFG_ORG_FMT_10BIT_RAW);
++				break;
++			case MEDIA_BUS_FMT_SGBRG10_1X10:
++				glb_cfg |= (GLB_CFG_C_ORDER_GBRG | GLB_CFG_ORG_FMT_10BIT_RAW);
++				break;
++			case MEDIA_BUS_FMT_SGRBG10_1X10:
++				glb_cfg |= (GLB_CFG_C_ORDER_GRBG | GLB_CFG_ORG_FMT_10BIT_RAW);
++				break;
++			case MEDIA_BUS_FMT_SRGGB10_1X10:
++				glb_cfg |= (GLB_CFG_C_ORDER_RGGB | GLB_CFG_ORG_FMT_10BIT_RAW);
++				break;
++			case MEDIA_BUS_FMT_SBGGR12_1X12:
++				glb_cfg |= (GLB_CFG_C_ORDER_BGGR | GLB_CFG_ORG_FMT_12BIT_RAW);
++				break;
++			case MEDIA_BUS_FMT_SGBRG12_1X12:
++				glb_cfg |= (GLB_CFG_C_ORDER_GBRG | GLB_CFG_ORG_FMT_12BIT_RAW);
++				break;
++			case MEDIA_BUS_FMT_SGRBG12_1X12:
++				glb_cfg |= (GLB_CFG_C_ORDER_GRBG | GLB_CFG_ORG_FMT_12BIT_RAW);
++				break;
++			case MEDIA_BUS_FMT_SRGGB12_1X12:
++				glb_cfg |= (GLB_CFG_C_ORDER_RGGB | GLB_CFG_ORG_FMT_12BIT_RAW);
++				break;
++			default:
++				dev_err(cimvideo->dev, "Providing code %x not support\n", fourcc_to_mbus_code(user_fmt->pixelformat));
++				return -EINVAL;
++		}
++	} else {
++		unsigned int sf_cfg = 0;
++		switch(fourcc_to_mbus_code(user_fmt->pixelformat)) {
++			case MEDIA_BUS_FMT_YUYV8_2X8:
++				glb_cfg |= (GLB_CFG_ORG_FMT_ITU656 | GLB_CFG_C_ORDER_YUYV);
++				break;
++			case MEDIA_BUS_FMT_YVYU8_2X8:
++				glb_cfg |= (GLB_CFG_ORG_FMT_ITU656 | GLB_CFG_C_ORDER_YVYU);
++				break;
++			case MEDIA_BUS_FMT_UYVY8_2X8:
++				glb_cfg |= (GLB_CFG_ORG_FMT_ITU656 | GLB_CFG_C_ORDER_UYVY);
++				break;
++			case MEDIA_BUS_FMT_VYUY8_2X8:
++				glb_cfg |= (GLB_CFG_ORG_FMT_ITU656 | GLB_CFG_C_ORDER_VYUY);
++				break;
++			default:
++				dev_err(cimvideo->dev, "Providing code %d not support\n",
++					fourcc_to_mbus_code(user_fmt->pixelformat));
++				break;
++		}
++
++		if(user_fmt->field == V4L2_FIELD_NONE) {
++			ctx->interlace = 0;
++		} else {
++			switch(user_fmt->field) {
++			case V4L2_FIELD_INTERLACED_TB:
++			case V4L2_FIELD_INTERLACED:
++				sf_cfg &= ~CIM_F_ORDER;
++				break;
++			case V4L2_FIELD_INTERLACED_BT:
++				sf_cfg |= CIM_F_ORDER;
++				break;
++			default:
++				dev_err(cimvideo->dev,
++					"itu656 unsupported field");
++				break;
++			}
++			sf_cfg |= CIM_SCAN_MD;
++			sf_cfg &= ~CIM_SF_HEIGHT_MASK;
++			sf_cfg |= ((img_sz->src_h / 2) & 0xfff);
++			ctx->interlace = 1;
++		}
++		cim_writel(pcdev, sf_cfg, SCAN_CFG);
++	}
++
++	glb_cfg |= GLB_CFG_BURST_LEN_32;
++	glb_cfg |= GLB_CFG_AUTO_RECOVERY;
++	if(frame_size_check_flag == 1)
++		glb_cfg |= GLB_CFG_SIZE_CHK;
++	else
++		glb_cfg &= ~GLB_CFG_SIZE_CHK;
++
++#ifdef CONFIG_CAMERA_USE_SNAPSHOT
++	tmp = CONFIG_SNAPSHOT_PULSE_WIDTH;
++	if(!tmp) {
++		tmp = 0x08;
++	}
++	glb_cfg |= GLB_CFG_DAT_MODE;
++	if (version == 1) {
++		glb_cfg &= ~GLB_CFG_EXPO_WIDTH_MASK_V1;
++		glb_cfg |= (((tmp-1) & 0x7) << GLB_CFG_EXPO_WIDTH_LBIT);
++	} else {
++		glb_cfg &= ~GLB_CFG_EXPO_WIDTH_MASK_V2;
++		glb_cfg |= ((tmp & 0x1f) << GLB_CFG_EXPO_WIDTH_LBIT);
++	}
++	tmp = CONFIG_SNAPSHOT_FRAME_DELAY & 0xffffff;
++	tmp |= CIM_DLY_EN;
++	tmp |= CIM_DLY_MD;
++	if (version == 2)
++		tmp |= CIM_EXPO_WIDTH_EN;
++	cim_writel(pcdev, tmp, DLY_CFG);
++#else
++	cim_writel(pcdev, 0, DLY_CFG);
++#endif
++
++	if(ctx->interlace) {
++		img_sz->src_h = img_sz->src_h / 2;
++	}
++	tmp = (img_sz->src_w << CIM_CROP_WIDTH_LBIT) |
++		(img_sz->src_h << CIM_CROP_HEIGHT_LBIT);
++	cim_writel(pcdev, tmp, FRM_SIZE);
++	tmp = cim_readl(pcdev, FRM_SIZE);
++	cim_writel(pcdev, 0, CROP_SITE);
++
++	/* enable stop of frame interrupt. */
++	intc |= CIM_INTC_MSK_EOW;
++
++	/* enable end of frame interrupt,
++	 * Work together with DES_INTC.EOF_MSK,
++	 * only when both are 1 will generate interrupt. */
++	intc |= CIM_INTC_MSK_EOF;
++
++	/* enable general stop of frame interrupt. */
++	intc |= CIM_INTC_MSK_GSA;
++
++	/* enable rxfifo overflow interrupt */
++	intc |= CIM_INTC_MSK_OVER;
++
++	/* enable size check err */
++	if(frame_size_check_flag == 1)
++		intc |= CIM_INTC_MSK_SZ_ERR;
++	else
++		intc &= ~CIM_INTC_MSK_SZ_ERR;
++
++	cim_writel(pcdev, 0, DBG_CGC);
++	cim_writel(pcdev, glb_cfg, GLB_CFG);
++	cim_writel(pcdev, intc, CIM_INTC);
++	cim_writel(pcdev, 0, QOS_CTRL);
++
++	return 0;
++}
++
++static int __ingenic_camera_try_fmt(struct cim_video_ctx *ctx, struct v4l2_format *f)
++{
++	struct cim_video_device *cimvideo = &ctx->cimvideo;
++	struct v4l2_subdev *sd = cimvideo->subdev;
++	struct v4l2_subdev_format format = {
++		.which = V4L2_SUBDEV_FORMAT_TRY,
++	};
++	struct v4l2_subdev_pad_config cfg;
++	struct v4l2_mbus_framefmt *mf = &format.format;
++	struct v4l2_pix_format *pix = &f->fmt.pix;
++	struct ingenic_image_sz *img_sz = &ctx->img_sz;
++	int depth = 0;
++	int ret = 0;
++
++	v4l_bound_align_image(&pix->width, 100, 2046,
++			(pix->pixelformat == V4L2_PIX_FMT_YUYV ? 1 : 0),
++			&pix->height, 100, 2046, 0, 0);
++
++	mf->width	= pix->width;
++	mf->height	= pix->height;
++	mf->field	= pix->field;
++	mf->colorspace	= pix->colorspace;
++	mf->code	= fourcc_to_mbus_code(pix->pixelformat);
++
++	ret = v4l2_subdev_call(sd, pad, set_fmt, &cfg, &format);
++	if (ret < 0){
++		return ret;
++	}
++
++	pix->width = mf->width;
++	pix->height = mf->height;
++	pix->field = mf->field;
++	pix->colorspace = mf->colorspace;
++	depth = fourcc_to_mbus_depth(pix->pixelformat);
++	pix->bytesperline = pix->width * depth / 8;
++	pix->sizeimage = pix->bytesperline * pix->height;
++
++	return 0;
++}
++
++static int ingenic_camera_try_fmt_vid_cap(struct file *file, void *fh,
++				    struct v4l2_format *f)
++{
++	struct cim_video_ctx *ctx = video_drvdata(file);
++	return __ingenic_camera_try_fmt(ctx, f);
++}
++
++static int ingenic_camera_s_fmt_vid_cap(struct file *file, void *fh,
++				    struct v4l2_format *f)
++{
++	struct cim_video_ctx *ctx = video_drvdata(file);
++	struct v4l2_pix_format *user_fmt = &ctx->format.fmt.pix;
++	struct cim_video_device *cimvideo = &ctx->cimvideo;
++	struct v4l2_subdev *sd = cimvideo->subdev;
++	struct ingenic_image_sz *img_sz = &ctx->img_sz;
++	struct v4l2_subdev_format format = {
++		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
++	};
++	struct v4l2_mbus_framefmt *mf = &format.format;
++	struct v4l2_pix_format *pix = &f->fmt.pix;
++	unsigned int pad = 0;
++	int ret = 0;
++
++	printk("%s:%d\n",__func__, __LINE__);
++	ret = __ingenic_camera_try_fmt(ctx, f);
++	if(ret)
++		return ret;
++
++	mf->width	= pix->width;
++	mf->height	= pix->height;
++	mf->field	= pix->field;
++	mf->colorspace	= pix->colorspace;
++	mf->code	= fourcc_to_mbus_code(pix->pixelformat);
++
++	ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &format);
++	if (ret < 0){
++		return ret;
++	}
++
++	img_sz->src_w = mf->width;
++	img_sz->src_h = mf->height;
++
++	if(unlikely(img_sz->rsz_flag == true)) {
++		dev_err(cimvideo->dev, "Set_crop should be behind set_fmt!\n");
++		return -EINVAL;
++	}
++
++	user_fmt->width = pix->width;
++	user_fmt->height = pix->height;
++	user_fmt->bytesperline = pix->bytesperline;
++	user_fmt->sizeimage = pix->sizeimage;
++	user_fmt->pixelformat = pix->pixelformat;
++	user_fmt->colorspace = pix->colorspace;
++	user_fmt->field = pix->field;
++
++	return ingenic_camera_set_bus_param(ctx);
++}
++
++static int ingenic_camera_g_fmt_vid_cap(struct file *file, void *fh,
++				    struct v4l2_format *f)
++{
++	struct cim_video_ctx *ctx = video_drvdata(file);
++	struct v4l2_pix_format *user_fmt = &ctx->format.fmt.pix;
++
++	printk("%s:%d\n",__func__, __LINE__);
++	memcpy(&f->fmt.pix, user_fmt, sizeof(struct v4l2_pix_format));
++
++	return 0;
++}
++
++static int ingenic_camera_g_selection(struct file *file, void *fh,
++				  struct v4l2_selection *s)
++{
++	struct cim_video_ctx *ctx = video_drvdata(file);
++	struct cim_video_device *cimvideo = &ctx->cimvideo;
++	struct v4l2_subdev *sd = cimvideo->subdev;
++	struct ingenic_image_sz *img_sz = &ctx->img_sz;
++	struct v4l2_subdev_selection sel;
++	struct v4l2_subdev_pad_config cfg;
++	int ret = 0;
++
++	switch (s->target) {
++		case V4L2_SEL_TGT_CROP:
++			printk("%s:%d\n",__func__, __LINE__);
++		case V4L2_SEL_TGT_CROP_DEFAULT:
++			printk("%s:%d\n",__func__, __LINE__);
++			s->r.left= img_sz->c_left;
++			s->r.top= img_sz->c_top;
++			s->r.width= img_sz->c_w;
++			s->r.height= img_sz->c_h;
++			return 0;
++		case V4L2_SEL_TGT_CROP_BOUNDS:
++			printk("%s:%d\n",__func__, __LINE__);
++			ret = v4l2_subdev_call(sd, pad, get_selection, &cfg, &sel);
++			if(!ret)
++				s->r =sel.r;
++			else
++				memset(&s->r, sizeof(struct v4l2_rect), 0);
++			return 0;
++	}
++	printk("%s:%d\n",__func__, __LINE__);
++	return -EINVAL;
++}
++
++static int ingenic_camera_check_crop(struct cim_video_ctx *ctx, struct v4l2_rect *r)
++{
++	struct v4l2_rect rect_w = *r;
++	struct v4l2_pix_format *user_fmt = &ctx->format.fmt.pix;
++	u32 pixfmt = user_fmt->pixelformat;
++	unsigned int walign;
++	unsigned int halign;
++
++	if(user_fmt->field != V4L2_FIELD_NONE) {
++		dev_err(ctx->cimvideo.dev, "field not supported by crop!\n");
++		return -EINVAL;
++	}
++
++	if((rect_w.width + rect_w.left > 2046) ||
++		(rect_w.height + rect_w.top > 2046)) {
++		dev_err(ctx->cimvideo.dev, "crop bounds check failed!\n");
++		return -EINVAL;
++	}
++
++	switch(pixfmt){
++	case V4L2_PIX_FMT_YUYV:
++	case V4L2_PIX_FMT_YVYU:
++	case V4L2_PIX_FMT_VYUY:
++	case V4L2_PIX_FMT_UYVY:
++		walign = 1;
++		halign = 0;
++		break;
++	case V4L2_PIX_FMT_SBGGR8:
++	case V4L2_PIX_FMT_SGBRG8:
++	case V4L2_PIX_FMT_SGRBG8:
++	case V4L2_PIX_FMT_SRGGB8:
++	case V4L2_PIX_FMT_SBGGR10:
++	case V4L2_PIX_FMT_SGBRG10:
++	case V4L2_PIX_FMT_SGRBG10:
++	case V4L2_PIX_FMT_SRGGB10:
++	case V4L2_PIX_FMT_SBGGR12:
++	case V4L2_PIX_FMT_SGBRG12:
++	case V4L2_PIX_FMT_SGRBG12:
++	case V4L2_PIX_FMT_SRGGB12:
++		walign = 1;
++		halign = 1;
++		break;
++	default:
++		walign = 0;
++		halign = 0;
++		break;
++	}
++
++	v4l_bound_align_image(&rect_w.width, 100, 2046, walign,
++			&rect_w.height, 100, 2046, halign, 0);
++
++	if((rect_w.width != r->width) ||
++		(rect_w.height != r->height)) {
++		dev_err(ctx->cimvideo.dev, "crop sizes check failed!\n");
++		return -EINVAL;
++	}
++
++	if((pixfmt == V4L2_PIX_FMT_YUYV)
++		&& (rect_w.left % 2)) {
++		dev_err(ctx->cimvideo.dev, "crop align check failed!\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int ingenic_camera_s_selection(struct file *file, void *fh,
++				  struct v4l2_selection *s)
++{
++	struct cim_video_ctx *ctx = video_drvdata(file);
++	struct v4l2_pix_format *user_fmt = &ctx->format.fmt.pix;
++	struct cim_video_device *cimvideo = &ctx->cimvideo;
++	struct v4l2_subdev *sd = cimvideo->subdev;
++	struct ingenic_camera_dev *pcdev = cimvideo->pcdev;
++	struct v4l2_rect rect_w = s->r;
++	struct v4l2_subdev_selection sel = {
++		.r = rect_w,
++	};
++	struct ingenic_image_sz *img_sz = &ctx->img_sz;
++	unsigned int framesize = 0;
++	unsigned int cropsite = 0;
++	int depth = 0;
++	int width, height;
++	int ret;
++
++	ret = v4l2_subdev_call(sd, pad, set_selection, NULL ,&sel);
++	if(!ret){
++		/*crop by sensor*/
++		dev_dbg(cimvideo->dev, "Sensor cropped %dx%d\n",
++				rect_w.width, rect_w.height);
++
++		img_sz->src_w		= rect_w.width;
++		img_sz->src_h		= rect_w.height;
++
++		img_sz->c_left		= sel.r.left;
++		img_sz->c_top		= sel.r.top;
++		img_sz->c_w		= sel.r.width;
++		img_sz->c_h		= sel.r.height;
++
++		framesize = (img_sz->src_w << CIM_CROP_WIDTH_LBIT) |
++			(img_sz->src_h << CIM_CROP_HEIGHT_LBIT);
++		cropsite = 0;
++	} else {
++		/*crop by cim*/
++		ret = ingenic_camera_check_crop(ctx, &rect_w);
++		if (ret)
++			return ret;
++
++		width = img_sz->src_w;
++		height = img_sz->src_h;
++
++		if(((rect_w.left + rect_w.width) > width) ||
++				((rect_w.top + rect_w.height) > height)) {
++			dev_err(cimvideo->dev, "please enum appropriate framesizes!\n");
++			return -EINVAL;
++		}
++
++		img_sz->c_left		= rect_w.left;
++		img_sz->c_top		= rect_w.top;
++		img_sz->c_w		= rect_w.width;
++		img_sz->c_h		= rect_w.height;
++
++
++		framesize = (img_sz->c_w << CIM_CROP_WIDTH_LBIT) |
++			(img_sz->c_h << CIM_CROP_HEIGHT_LBIT);
++		cropsite = (img_sz->c_left << CIM_CROP_X_LBIT) |
++			(img_sz->c_top << CIM_CROP_Y_LBIT);
++
++	}
++	user_fmt->width = rect_w.width;
++	user_fmt->height = rect_w.height;
++	depth = fourcc_to_mbus_depth(user_fmt->pixelformat);
++	user_fmt->bytesperline = user_fmt->width * depth / 8;
++	user_fmt->sizeimage = user_fmt->bytesperline * user_fmt->height;
++
++	img_sz->rsz_flag		= true;
++
++	cim_writel(pcdev, framesize, FRM_SIZE);
++	cim_writel(pcdev, cropsite, CROP_SITE);
++
++	printk("%s:%d\n",__func__, __LINE__);
++	return 0;
++}
++
++static int ingenic_camera_enum_framesizes(struct file *file, void *fh,
++				      struct v4l2_frmsizeenum *fsize)
++{
++	struct cim_video_ctx *ctx = video_drvdata(file);
++	struct cim_video_device *cimvideo = &ctx->cimvideo;
++	struct v4l2_subdev *sd = cimvideo->subdev;
++	struct v4l2_subdev_frame_size_enum fse = {
++		.index = fsize->index,
++		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
++	};
++	int ret;
++
++	ret = v4l2_subdev_call(sd, pad, enum_frame_size, NULL, &fse);
++	if (ret < 0)
++		return ret;
++
++	if (fse.min_width == fse.max_width &&
++	    fse.min_height == fse.max_height) {
++		fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
++		fsize->discrete.width = fse.min_width;
++		fsize->discrete.height = fse.min_height;
++		return 0;
++	}
++	fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
++	fsize->stepwise.min_width = fse.min_width;
++	fsize->stepwise.max_width = fse.max_width;
++	fsize->stepwise.min_height = fse.min_height;
++	fsize->stepwise.max_height = fse.max_height;
++	fsize->stepwise.step_width = 1;
++	fsize->stepwise.step_height = 1;
++
++	return 0;
++}
++
++static int ingenic_camera_s_input(struct file *file, void *fh, unsigned int i)
++{
++	return 0;
++}
++
++static const struct v4l2_ioctl_ops cim_video_ioctl_ops = {
++	.vidioc_querycap                = ingenic_camera_querycap,
++	.vidioc_enum_fmt_vid_cap        = ingenic_camera_enum_fmt_vid_cap,
++	.vidioc_g_fmt_vid_cap           = ingenic_camera_g_fmt_vid_cap,
++	.vidioc_s_fmt_vid_cap           = ingenic_camera_s_fmt_vid_cap,
++	.vidioc_g_selection		= ingenic_camera_g_selection,
++	.vidioc_s_selection		= ingenic_camera_s_selection,
++	.vidioc_try_fmt_vid_cap         = ingenic_camera_try_fmt_vid_cap,
++	.vidioc_reqbufs                 = vb2_ioctl_reqbufs,
++	.vidioc_querybuf                = vb2_ioctl_querybuf,
++	.vidioc_qbuf                    = vb2_ioctl_qbuf,
++	.vidioc_dqbuf                   = vb2_ioctl_dqbuf,
++	.vidioc_streamon                = vb2_ioctl_streamon,
++	.vidioc_streamoff               = vb2_ioctl_streamoff,
++	.vidioc_enum_framesizes         = ingenic_camera_enum_framesizes,
++	.vidioc_s_input			= ingenic_camera_s_input,
++//	.vidioc_g_parm                  = isp_video_g_parm,
++//	.vidioc_s_ctrl                  = isp_video_s_ctrl,
++//	.vidioc_g_ctrl                  = isp_video_g_ctrl,
++};
++
++
++/*video_queue_ops*/
++static int ingenic_videobuf_init(struct vb2_buffer *vb2)
++{
++	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb2);
++	struct ingenic_buffer *buf = container_of(vbuf, struct ingenic_buffer, vb);
++
++	INIT_LIST_HEAD(&buf->list);
++
++	return 0;
++}
++
++
++static int ingenic_videobuf_setup(struct vb2_queue *q,
++			   unsigned int *num_buffers, unsigned int *num_planes,
++			   unsigned int sizes[], struct device *alloc_devs[])
++{
++	struct cim_video_ctx *ctx = vb2_get_drv_priv(q);
++	struct v4l2_pix_format *user_fmt = &ctx->format.fmt.pix;
++	struct cim_video_device *cimvideo = &ctx->cimvideo;
++	struct ingenic_camera_dev *pcdev = cimvideo->pcdev;
++	int max_video_mem = pcdev->cim_priv->max_video_mem;
++	int size;
++
++	*num_planes = 1;
++	size = user_fmt->sizeimage;
++	if(ctx->hist_en)
++		size += CIM_HIST_SIZE;
++	else if(ctx->lumi_en){
++		size += CIM_LUMI_SIZE;
++	}
++
++	if (!*num_buffers || *num_buffers > max_buffer_num)
++		*num_buffers = max_buffer_num;
++
++	if (size * *num_buffers > max_video_mem)
++		*num_buffers = max_video_mem / size;
++
++	sizes[0] = size;
++	alloc_devs[0] = cimvideo->pcdev->dev;
++
++	pcdev->start_streaming_called = 0;
++	pcdev->sequence = 0;
++	pcdev->active = NULL;
++
++	if(ingenic_camera_alloc_desc(pcdev, *num_buffers))
++		return -ENOMEM;
++	dev_info(cimvideo->dev, "%s, count=%d, size=%d\n", __func__,
++		*num_buffers, size);
++
++	return 0;
++}
++
++static	int ingenic_buffer_prepare(struct vb2_buffer *vb)
++{
++	struct cim_video_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
++	struct v4l2_pix_format *user_fmt = &ctx->format.fmt.pix;
++	int ret = 0;
++
++	dev_vdbg(ctx->cimvideo.dev, "%s (vb=0x%p) 0x%p %lu\n", __func__,
++		vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
++
++	vb2_set_plane_payload(vb, 0, user_fmt->sizeimage);
++	if (vb2_plane_vaddr(vb, 0) &&
++	    vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
++		ret = -EINVAL;
++		return ret;
++	}
++
++	return 0;
++
++}
++
++
++static void ingenic_buffer_queue(struct vb2_buffer *vb)
++{
++	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
++	struct cim_video_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
++	struct ingenic_camera_dev *pcdev = ctx->cimvideo.pcdev;
++	struct ingenic_buffer *buf = container_of(vbuf, struct ingenic_buffer, vb);
++	struct ingenic_camera_desc_v1 *desc_v1_v;
++	struct ingenic_camera_desc_v1 *desc_v1_p;
++	struct ingenic_camera_desc_v2 *desc_v2_v;
++	struct ingenic_camera_desc_v2 *desc_v2_p;
++	unsigned long flags;
++	unsigned int regval;
++	int index = vb->index;
++
++	spin_lock_irqsave(&pcdev->lock, flags);
++
++	list_add_tail(&buf->list, &pcdev->video_buffer_list);
++	if (!pcdev->active) {
++		pcdev->active = buf;
++	}
++
++	if(!pcdev->start_streaming_called) {
++		goto out;
++	}
++
++	if((index > pcdev->buf_cnt) || (index < 0)) {
++		dev_err(ctx->cimvideo.dev,"Warning: index %d out of range!\n", index);
++		goto out;
++	}
++
++	if(pcdev->cim_priv->version_num == 2) {
++		desc_v2_v = (struct ingenic_camera_desc_v2 *) pcdev->desc_vaddr;
++		desc_v2_p = pcdev->desc_v2_paddr;
++
++		if(is_cim_disabled(pcdev) && list_is_singular(&pcdev->video_buffer_list)) {
++			desc_v2_v[index].DES_CFG_t.data.DES_END = 1;
++			desc_v2_v[index].DES_INTC_t.data.EOF_MSK = 0;
++
++			pcdev->desc_v2_head = &desc_v2_v[index];
++			pcdev->desc_v2_tail = &desc_v2_v[index];
++
++			regval = (dma_addr_t)(&desc_v2_p[index]);
++			cim_writel(pcdev, regval, DES_ADDR);
++			cim_writel(pcdev, CIM_CTRL_START, CIM_CTRL);
++		} else {
++			pcdev->desc_v2_tail->next = (dma_addr_t)(&desc_v2_p[index]);
++			pcdev->desc_v2_tail->DES_INTC_t.data.EOF_MSK = 1;
++			pcdev->desc_v2_tail->DES_CFG_t.data.DES_END = 0;
++			pcdev->desc_v2_tail = &desc_v2_v[index];
++
++			desc_v2_v[index].DES_CFG_t.data.DES_END = 1;
++			desc_v2_v[index].DES_INTC_t.data.EOF_MSK = 0;
++		}
++	} else {
++		desc_v1_v = (struct ingenic_camera_desc_v1 *) pcdev->desc_vaddr;
++		desc_v1_p = pcdev->desc_v1_paddr;
++
++		if(is_cim_disabled(pcdev) && list_is_singular(&pcdev->video_buffer_list)) {
++			desc_v1_v[index].DES_CFG_t.data.DES_END = 1;
++			desc_v1_v[index].DES_INTC_t.data.EOF_MSK = 0;
++
++			pcdev->desc_v1_head = &desc_v1_v[index];
++			pcdev->desc_v1_tail = &desc_v1_v[index];
++
++			regval = (dma_addr_t)(&desc_v1_p[index]);
++			cim_writel(pcdev, regval, DES_ADDR);
++			cim_writel(pcdev, CIM_CTRL_START, CIM_CTRL);
++		} else {
++			pcdev->desc_v1_tail->next = (dma_addr_t)(&desc_v1_p[index]);
++			pcdev->desc_v1_tail->DES_INTC_t.data.EOF_MSK = 1;
++			pcdev->desc_v1_tail->DES_CFG_t.data.DES_END = 0;
++			pcdev->desc_v1_tail = &desc_v1_v[index];
++
++			desc_v1_v[index].DES_CFG_t.data.DES_END = 1;
++		}
++	}
++
++out:
++	spin_unlock_irqrestore(&pcdev->lock, flags);
++
++	if(showFPS){
++		calculate_frame_rate();
++	}
++
++	return;
++}
++
++static void ingenic_cim_start(struct ingenic_camera_dev *pcdev)
++{
++	struct vb2_buffer *vb2 = &pcdev->active->vb.vb2_buf;
++	unsigned regval = 0;
++	int index;
++
++	BUG_ON(!pcdev->active);
++
++	/* clear status register */
++	cim_writel(pcdev, CIM_CLR_ALL, CIM_CLR_ST);
++
++	/* configure dma desc addr*/
++	index = vb2->index;
++	if (pcdev->cim_priv->version_num == 2)
++		regval = (dma_addr_t)(&(pcdev->desc_v2_paddr[index]));
++	else
++		regval = (dma_addr_t)(&(pcdev->desc_v1_paddr[index]));
++
++	cim_writel(pcdev, regval, DES_ADDR);
++
++	cim_writel(pcdev, CIM_CTRL_START, CIM_CTRL);
++}
++
++static void ingenic_cim_stop(struct ingenic_camera_dev *pcdev)
++{
++	cim_writel(pcdev, CIM_CTRL_QCK_STOP, CIM_CTRL);
++	cim_writel(pcdev, CIM_CLR_ALL, CIM_CLR_ST);
++}
++
++static int ingenic_cim_soft_reset(struct cim_video_ctx *ctx)
++{
++	struct cim_video_device *cimvideo = &ctx->cimvideo;
++	struct ingenic_camera_dev *pcdev = cimvideo->pcdev;
++	struct v4l2_subdev *sd = cimvideo->subdev;
++	int count = 4000;
++
++	v4l2_subdev_call(sd, video, s_stream, 1);
++
++	cim_writel(pcdev, CIM_CTRL_SOFT_RST, CIM_CTRL);
++	while((!(cim_readl(pcdev,CIM_ST) & CIM_ST_SRST)) && count--) {
++		udelay(1000);
++	}
++
++	if (count < 0) {
++		v4l2_subdev_call(sd, video, s_stream, 0);
++		dev_err(pcdev->dev, "cim soft reset failed!\n");
++		return -ENODEV;
++	}
++	cim_writel(pcdev,CIM_CLR_SRST,CIM_CLR_ST);
++
++	v4l2_subdev_call(sd, video, s_stream, 0);
++
++	return 0;
++}
++
++static int ingenic_start_streaming(struct vb2_queue *q, unsigned int count)
++{
++	struct cim_video_ctx *ctx = vb2_get_drv_priv(q);
++	struct ingenic_camera_dev *pcdev = ctx->cimvideo.pcdev;
++	struct v4l2_subdev *sd = ctx->cimvideo.subdev;
++	struct ingenic_buffer *buf, *node;
++	int version = pcdev->cim_priv->version_num;
++	int index = ctx->cimvideo.index;
++	struct cim_async_subdev *casd = &pcdev->casd[index];
++	unsigned long flags;
++	int ret = 0;
++	unsigned int tmp = 0;
++
++	list_for_each_entry_safe(buf, node, &pcdev->video_buffer_list, list) {
++		ret = ingenic_init_desc(&buf->vb.vb2_buf);
++		if(ret) {
++			dev_err(ctx->cimvideo.dev, "%s:Desc initialization failed\n",
++					__func__);
++			return ret;
++		}
++	}
++
++	if(casd->bus_type == V4L2_MBUS_CSI2_DPHY) {
++		ret = csi_phy_start(version, casd->mipi_csi2.num_data_lanes);
++		if(ret < 0) {
++			dev_err(ctx->cimvideo.dev, "csi starting failed!\n");
++			return ret;
++		}
++	}
++
++	ret = ingenic_cim_soft_reset(ctx);
++	if(ret)
++		goto err;
++
++	v4l2_subdev_call(sd, video, s_stream, 1);
++
++	if(ret)
++		goto err;
++
++	spin_lock_irqsave(&pcdev->lock, flags);
++	ingenic_cim_start(pcdev);
++	pcdev->start_streaming_called = 1;
++	spin_unlock_irqrestore(&pcdev->lock, flags);
++
++	return 0;
++err:
++	if(casd->bus_type == V4L2_MBUS_CSI2_DPHY)
++		csi_phy_stop(version);
++
++	if(ctx->snapshot){
++		tmp = cim_readl(pcdev, GLB_CFG);
++		tmp &= ~GLB_CFG_DAT_MODE;
++		tmp &= ~GLB_CFG_EXPO_WIDTH_MASK_V2;
++		cim_writel(pcdev, tmp, GLB_CFG);
++		cim_writel(pcdev, 0, DLY_CFG);
++	}
++
++	list_for_each_entry_safe(buf, node, &pcdev->video_buffer_list, list) {
++		list_del_init(&buf->list);
++		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
++	}
++
++	pcdev->desc_v1_head = NULL;
++	pcdev->desc_v1_tail = NULL;
++	pcdev->desc_v2_head = NULL;
++	pcdev->desc_v2_tail = NULL;
++
++	return ret;
++}
++
++static void ingenic_stop_streaming(struct vb2_queue *q)
++{
++	struct cim_video_ctx *ctx = vb2_get_drv_priv(q);
++	struct v4l2_subdev *sd = ctx->cimvideo.subdev;
++	struct ingenic_camera_dev *pcdev = ctx->cimvideo.pcdev;
++	struct ingenic_buffer *buf, *node;
++	int version = pcdev->cim_priv->version_num;
++	int index = ctx->cimvideo.index;
++	struct cim_async_subdev *casd = &pcdev->casd[index];
++	unsigned long flags;
++	unsigned int tmp = 0;
++
++	spin_lock_irqsave(&pcdev->lock, flags);
++	ingenic_cim_stop(pcdev);
++//	printk("[%d]~~~~~~~~%x\n", __LINE__, *(volatile unsigned int *)0xb3062004);
++
++	/* Release all active buffers */
++	list_for_each_entry_safe(buf, node, &pcdev->video_buffer_list, list) {
++		list_del_init(&buf->list);
++		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
++	}
++
++	pcdev->start_streaming_called = 0;
++	pcdev->desc_v1_head = NULL;
++	pcdev->desc_v1_tail = NULL;
++	pcdev->desc_v2_head = NULL;
++	pcdev->desc_v2_tail = NULL;
++	pcdev->active = NULL;
++
++	if(ctx->snapshot){
++		tmp = cim_readl(pcdev, GLB_CFG);
++		tmp &= ~GLB_CFG_DAT_MODE;
++		tmp &= ~GLB_CFG_EXPO_WIDTH_MASK_V2;
++		cim_writel(pcdev, tmp, GLB_CFG);
++		cim_writel(pcdev, 0, DLY_CFG);
++	}
++
++	spin_unlock_irqrestore(&pcdev->lock, flags);
++
++	if(casd->bus_type == V4L2_MBUS_CSI2_DPHY)
++		csi_phy_stop(version);
++	v4l2_subdev_call(sd, video, s_stream, 0);
++}
++
++
++static struct vb2_ops cim_video_queue_ops = {
++	.buf_init		= ingenic_videobuf_init,
++	.queue_setup		= ingenic_videobuf_setup,
++	.buf_prepare		= ingenic_buffer_prepare,
++	.buf_queue		= ingenic_buffer_queue,
++	.start_streaming	= ingenic_start_streaming,
++	.stop_streaming		= ingenic_stop_streaming,
++};
++
++static void ingenic_camera_activate(struct ingenic_camera_dev *pcdev) {
++	int ret = -1;
++
++	if(pcdev->clk) {
++		ret = clk_prepare_enable(pcdev->clk);
++	}
++	if(pcdev->mipi_clk) {
++		ret = clk_prepare_enable(pcdev->mipi_clk);
++	}
++}
++
++static void ingenic_camera_deactivate(struct ingenic_camera_dev *pcdev) {
++	if( pcdev->mipi_clk) {
++		clk_disable_unprepare(pcdev->mipi_clk);
++	}
++	if(pcdev->clk) {
++		clk_disable_unprepare(pcdev->clk);
++	}
++}
++
++
++static int cim_video_open(struct file *file)
++{
++	struct cim_video_ctx *ctx = video_drvdata(file);
++	struct cim_video_device *cimvideo = &ctx->cimvideo;
++	struct ingenic_camera_dev *pcdev = cimvideo->pcdev;
++	struct video_device *video = &cimvideo->video;
++	struct vb2_queue *queue = NULL;
++	int ret = 0;
++
++	mutex_lock(&pcdev->mutex);
++
++	if(pcdev->active_ctx){
++		if(cimvideo->index != pcdev->active_ctx->cimvideo.index)
++			dev_info(cimvideo->dev, "Only one cim video device node can be operated at the same time");
++		ret = -EBUSY;
++		goto err_busy;
++	}
++
++	v4l2_fh_init(&ctx->fh, &cimvideo->video);
++	v4l2_fh_add(&ctx->fh);
++
++	queue = &ctx->queue;
++	queue->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++	queue->io_modes = VB2_MMAP |VB2_USERPTR;
++	queue->drv_priv = ctx;
++	queue->ops = &cim_video_queue_ops;
++	queue->mem_ops = &ingenic_vb2_dma_contig_memops;
++	queue->buf_struct_size = sizeof(struct ingenic_buffer);
++	queue->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
++	queue->lock = &cimvideo->queue_lock;
++
++	ret = vb2_queue_init(queue);
++	if(ret < 0) {
++		goto err_vb2_queue_init;
++	}
++
++	video->queue = queue;
++
++	file->private_data = &ctx->fh;
++	pcdev->active_ctx = ctx;
++	ingenic_camera_activate(pcdev);
++
++	mutex_unlock(&pcdev->mutex);
++
++	return 0;
++
++err_vb2_queue_init:
++	v4l2_fh_del(&ctx->fh);
++err_busy:
++	mutex_unlock(&pcdev->mutex);
++	return ret;
++}
++
++static int cim_video_release(struct file *file)
++{
++	struct cim_video_ctx *ctx = video_drvdata(file);
++	struct cim_video_device *cimvideo = &ctx->cimvideo;
++	struct ingenic_camera_dev *pcdev = cimvideo->pcdev;
++	struct video_device *video = &cimvideo->video;
++
++	/*lock*/
++	mutex_lock(&pcdev->mutex);
++
++	vb2_queue_release(video->queue);
++
++	ingenic_camera_deactivate(pcdev);
++	ingenic_camera_free_desc(pcdev);
++
++	pcdev->active_ctx = NULL;
++	file->private_data = NULL;
++	video->queue = NULL;
++
++	memset(&ctx->img_sz, 0, sizeof(struct ingenic_image_sz));
++	memset(&ctx->format, 0, sizeof(struct v4l2_format));
++	ctx->interlace = 0;
++	ctx->uv_offset = 0;
++	ctx->payload_size = 0;
++
++	ctx->hist_en = 0;
++	ctx->hist_gain_add = 0;
++	ctx->hist_gain_mul = 0;
++	ctx->lumi_en = 0;
++	ctx->snapshot = 0;
++	ctx->output_y = 0;
++	v4l2_fh_del(&ctx->fh);
++	v4l2_fh_exit(&ctx->fh);
++
++	/*unlock*/
++	mutex_unlock(&pcdev->mutex);
++
++	return 0;
++
++}
++
++
++static struct v4l2_file_operations cim_video_fops = {
++	.owner = THIS_MODULE,
++	.unlocked_ioctl = video_ioctl2,
++	.open = cim_video_open,
++	.release = cim_video_release,
++	.poll = vb2_fop_poll,
++	.mmap = vb2_fop_mmap,
++};
++
++int ingenic_cim_asd_notifier_bound(struct v4l2_async_notifier *notifier,
++		struct v4l2_subdev *subdev,
++		struct v4l2_async_subdev *asd)
++{
++	struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
++	struct ingenic_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
++	struct cim_video_device *cimvideo = NULL;
++	struct video_device *video = NULL;
++	int index = get_asd_index(asd);
++	struct cim_video_ctx *ctx = pcdev->ctx[index];
++	int ret = 0;
++
++	ctx = kzalloc(sizeof(struct cim_video_ctx), GFP_KERNEL);
++	if(IS_ERR_OR_NULL(ctx)) {
++		dev_err(cimvideo->dev, "Failed to alloc ctx for cim_video_ctx\n");
++		ret = -ENOMEM;
++		goto err_ctx_alloc;
++	}
++
++	cimvideo = &ctx->cimvideo;
++	video = &cimvideo->video;
++
++	cimvideo->pcdev = pcdev;
++	cimvideo->index = index;
++	cimvideo->alloc_ctx = ingenic_vb2_dma_contig_init_ctx(cimvideo->dev);
++	if(IS_ERR_OR_NULL(cimvideo->alloc_ctx)) {
++		ret = -ENOMEM;
++		goto err_dma_alloc_ctx;
++	}
++
++	mutex_init(&cimvideo->queue_lock);
++	mutex_init(&cimvideo->stream_lock);
++
++	/*ctrl_handler*/
++	v4l2_ctrl_handler_init(&ctx->hdl, 10);
++	v4l2_ctrl_new_custom(&ctx->hdl, &img_crop_way, NULL);
++	if (pcdev->cim_priv->version_num == 2) {
++		v4l2_ctrl_new_custom(&ctx->hdl, &lumi_en, NULL);
++		v4l2_ctrl_new_custom(&ctx->hdl, &output_y, NULL);
++		v4l2_ctrl_new_custom(&ctx->hdl, &point1_x, NULL);
++		v4l2_ctrl_new_custom(&ctx->hdl, &point1_y, NULL);
++		v4l2_ctrl_new_custom(&ctx->hdl, &point2_x, NULL);
++		v4l2_ctrl_new_custom(&ctx->hdl, &point2_y, NULL);
++	} else {
++		v4l2_ctrl_new_custom(&ctx->hdl, &img_scale_sharp, NULL);
++		v4l2_ctrl_new_custom(&ctx->hdl, &hist_en, NULL);
++		v4l2_ctrl_new_custom(&ctx->hdl, &hist_gain_add, NULL);
++		v4l2_ctrl_new_custom(&ctx->hdl, &hist_gain_mul, NULL);
++	}
++	v4l2_ctrl_new_custom(&ctx->hdl, &snapshot_en, NULL);
++	v4l2_ctrl_new_custom(&ctx->hdl, &exp_pulse_w, NULL);
++	v4l2_ctrl_new_custom(&ctx->hdl, &delay_t, NULL);
++
++	v4l2_ctrl_handler_setup(&ctx->hdl);
++
++	/*video register device*/
++	snprintf(video->name, sizeof(video->name), "%s-%d", v4l2_dev->name, index);
++	video->fops = &cim_video_fops;
++	video->ioctl_ops = &cim_video_ioctl_ops;
++	video->release = video_device_release_empty;
++	video->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
++	video->v4l2_dev = v4l2_dev;
++	video->ctrl_handler = &ctx->hdl;
++	video_set_drvdata(video, ctx);
++
++	cimvideo->dev = pcdev->dev;
++	cimvideo->subdev = subdev;
++
++	ret = video_register_device(video, VFL_TYPE_VIDEO, ingenic_cim_get_video_nr(index));
++	if(ret < 0) {
++		goto err_video_register_device;
++	}
++
++	dev_info(pcdev->dev, "register video device %s @ /dev/video%d ok\n", video->name, video->num);
++
++	return 0;
++
++err_video_register_device:
++	ingenic_vb2_dma_contig_cleanup_ctx(cimvideo->alloc_ctx);
++err_dma_alloc_ctx:
++	kfree(ctx);
++err_ctx_alloc:
++	return ret;
++}
++
++int ingenic_cim_asd_notifier_complete(struct v4l2_async_notifier *notifier){
++
++	return 0;
++}
++
++void ingenic_cim_asd_notifier_unbind(struct v4l2_async_notifier *notifier,
++		struct v4l2_subdev *subdev,
++		struct v4l2_async_subdev *asd)
++{
++	struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
++	struct ingenic_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
++	int index = get_asd_index(asd);
++	struct cim_video_ctx *ctx = pcdev->ctx[index];
++	struct cim_video_device *cimvideo = &ctx->cimvideo;
++
++	v4l2_ctrl_handler_free(&ctx->hdl);
++	video_unregister_device(&cimvideo->video);
++	ingenic_vb2_dma_contig_cleanup_ctx(cimvideo->alloc_ctx);
++	kfree(ctx);
++}
++
++struct v4l2_async_notifier_operations ingenic_cim_async_ops = {
++	.bound = ingenic_cim_asd_notifier_bound,
++	.complete = ingenic_cim_asd_notifier_complete,
++	.unbind = ingenic_cim_asd_notifier_unbind,
++};
++
++
++static int ingenic_cim_phrase_remote_endpoint(struct ingenic_camera_dev *pcdev)
++{
++	struct device_node *node = NULL;
++	struct v4l2_async_subdev *asd = NULL;
++	int ret = 0;
++
++	v4l2_async_notifier_init(&pcdev->notifier);
++	while((node = of_graph_get_next_endpoint(pcdev->dev->of_node, node)) && pcdev->asd_num < MAX_ASYNC_SUBDEVS)
++	{
++		pcdev->casd[pcdev->asd_num].index = pcdev->asd_num;
++		ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(node), &pcdev->vep[pcdev->asd_num]);
++		if(ret) {
++			of_node_put(node);
++			return ret;
++		}
++		pcdev->casd[pcdev->asd_num].bus_type = pcdev->vep[pcdev->asd_num].bus_type;
++		pcdev->casd[pcdev->asd_num].parallel = pcdev->vep[pcdev->asd_num].bus.parallel;
++		pcdev->casd[pcdev->asd_num].mipi_csi2 = pcdev->vep[pcdev->asd_num].bus.mipi_csi2;
++		pcdev->casd[pcdev->asd_num].index = pcdev->asd_num;
++
++		asd = &pcdev->casd[pcdev->asd_num].asd;
++		asd->match.fwnode = fwnode_graph_get_remote_port_parent(of_fwnode_handle(node));
++		asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
++
++		of_node_put(node);
++
++		ret = v4l2_async_notifier_add_subdev(&pcdev->notifier, asd);
++		if (ret) {
++			fwnode_handle_put(asd->match.fwnode);
++			return ret;
++		}
++
++		fwnode_handle_put(asd->match.fwnode);
++
++		pcdev->asd_num++;
++	}
++	return ret;
++}
++
++/**********************cim_debug***************************/
++static ssize_t frame_size_check_r(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	snprintf(buf, 100, " 0: disable frame size check.\n 1: enable frame size check.\n");
++	return 100;
++}
++
++static ssize_t frame_size_check_w(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++        if (count != 2)
++                return -EINVAL;
++
++        if (*buf == '0') {
++                frame_size_check_flag = 0;
++        } else if (*buf == '1') {
++                frame_size_check_flag = 1;
++        } else {
++                return -EINVAL;
++        }
++
++        return count;
++}
++
++static ssize_t fps_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	printk("\n-----you can choice print way:\n");
++	printk("Example: echo NUM > show_fps\n");
++	printk("NUM = 0: close fps statistics\n");
++	printk("NUM = 1: print recently fps\n");
++	printk("NUM = 2: print interval between last and this queue buffers\n");
++	printk("NUM > 2: print fps after NUM second\n");
++	return 0;
++}
++
++static ssize_t fps_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	int num = 0;
++	num = simple_strtoul(buf, NULL, 0);
++	if(num < 0){
++		printk("\n--please 'cat show_fps' to view using the method\n\n");
++		return n;
++	}
++	showFPS = num;
++	return n;
++}
++
++static DEVICE_ATTR(frame_size_check, S_IRUGO|S_IWUSR, frame_size_check_r, frame_size_check_w);
++static DEVICE_ATTR(show_fps, S_IRUGO|S_IWUSR, fps_show, fps_store);
++
++static struct attribute *cim_debug_attrs[] = {
++	&dev_attr_frame_size_check.attr,
++	&dev_attr_show_fps.attr,
++	NULL,
++};
++const char cim_group_name[] = "debug";
++static struct attribute_group cim_debug_attr_group = {
++	.name	= cim_group_name,
++	.attrs	= cim_debug_attrs,
++};
++
++/***************************prob*******************************/
++static struct cim_private version1_pri = {
++	.max_video_mem = VIDEO_MEM + CIM_HIST_SIZE,
++	.version_num = 1,
++
++};
++
++static struct cim_private version2_pri = {
++	.max_video_mem = VIDEO_MEM + CIM_LUMI_SIZE,
++	.version_num = 2,
++};
++
++static const struct of_device_id ingenic_camera_of_match[] = {
++	{ .compatible = "ingenic,m300-cim", .data = (struct cim_private *)&version1_pri },
++	{ .compatible = "ingenic,x2000-cim", .data = (struct cim_private *)&version1_pri },
++	{ .compatible = "ingenic,x1600-cim", .data = (struct cim_private *)&version2_pri },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, ingenic_camera_of_match);
++
++static int ingenic_camera_probe(struct platform_device *pdev) {
++	int ret = 0;
++	unsigned int irq;
++	struct resource *res;
++	void __iomem *base;
++	struct ingenic_camera_dev *pcdev;
++
++	/* malloc */
++	pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
++	if (!pcdev) {
++		dev_err(&pdev->dev, "Could not allocate pcdev\n");
++		ret = -ENOMEM;
++		goto err_kzalloc;
++	}
++
++	/* resource */
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if(!res) {
++		dev_err(&pdev->dev, "Could not get resource!\n");
++		ret = -ENODEV;
++		goto err_get_resource;
++	}
++
++	/* irq */
++	irq = platform_get_irq(pdev, 0);
++	if (irq <= 0) {
++		dev_err(&pdev->dev, "Could not get irq!\n");
++		ret = -ENODEV;
++		goto err_get_irq;
++	}
++
++	pcdev->priv = of_match_node(ingenic_camera_of_match, pdev->dev.of_node);
++	pcdev->cim_priv = (struct cim_private *)pcdev->priv->data;
++
++	printk("cim current version: %d\n", pcdev->cim_priv->version_num);
++
++	/*get cim clk*/
++	pcdev->clk = of_clk_get(pdev->dev.of_node, 1);
++	if (pcdev->clk == NULL) {
++		ret = PTR_ERR(pcdev->clk);
++		dev_err(&pdev->dev, "%s:can't get clk %s\n", __func__, "cim");
++		goto err_clk_get_cim;
++	}
++
++	/*get mipi clk*/
++	pcdev->mipi_clk = of_clk_get(pdev->dev.of_node, 2);
++	if (pcdev->mipi_clk == NULL) {
++		ret = PTR_ERR(pcdev->clk);
++		dev_err(&pdev->dev, "%s:can't get clk %s\n", __func__, "cim");
++		goto err_clk_get_mipi;
++	}
++
++	/* Request the regions. */
++	if (!request_mem_region(res->start, resource_size(res), DRIVER_NAME)) {
++		ret = -EBUSY;
++		goto err_request_mem_region;
++	}
++	base = ioremap(res->start, resource_size(res));
++	if (!base) {
++		ret = -ENOMEM;
++		goto err_ioremap;
++	}
++
++	spin_lock_init(&pcdev->lock);
++	INIT_LIST_HEAD(&pcdev->video_buffer_list);
++	mutex_init(&pcdev->mutex);
++
++	pcdev->dev = &pdev->dev;
++	pcdev->res = res;
++	pcdev->irq = irq;
++	pcdev->base = base;
++	pcdev->active = NULL;
++	pcdev->desc_v1_head = NULL;
++	pcdev->desc_v1_tail = NULL;
++	pcdev->desc_v2_head = NULL;
++	pcdev->desc_v2_tail = NULL;
++
++	/* request irq */
++	ret = devm_request_irq(&pdev->dev, pcdev->irq, ingenic_camera_irq_handler, 0,
++			dev_name(&pdev->dev), pcdev);
++	if(ret) {
++		dev_err(&pdev->dev, "request irq failed!\n");
++		goto err_request_irq;
++	}
++
++	ret = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
++	if (ret)
++		goto err_v4l2_dev_register;
++
++	ret = sysfs_create_group(&pcdev->dev->kobj, &cim_debug_attr_group);
++	if (ret) {
++		dev_err(&pdev->dev, "device create sysfs group failed\n");
++
++		ret = -EINVAL;
++		goto err_free_file;
++	}
++
++	/*asd*/
++	ret = ingenic_cim_phrase_remote_endpoint(pcdev);
++	if(ret)
++		goto err_phrase_remote_endpoint;
++
++	pcdev->notifier.ops = &ingenic_cim_async_ops;
++	ret = v4l2_async_notifier_register(&pcdev->v4l2_dev, &pcdev->notifier);
++	if(ret){
++		printk( "v4l2_async_notifier_register failed %d\n", ret);
++		goto err_regist_notifier;
++	}
++
++	ret = of_reserved_mem_device_init(pcdev->dev);
++	if(ret)
++		dev_warn(pcdev->dev, "failed to init reserved mem\n");
++
++	dev_dbg(&pdev->dev, "ingenic Camera driver loaded!\n");
++
++	platform_set_drvdata(pdev, pcdev);
++	return 0;
++
++err_regist_notifier:
++err_phrase_remote_endpoint:
++	sysfs_remove_group(&pcdev->dev->kobj, &cim_debug_attr_group);
++err_free_file:
++	v4l2_device_unregister(&pcdev->v4l2_dev);
++err_v4l2_dev_register:
++	free_irq(pcdev->irq, pcdev);
++err_request_irq:
++	iounmap(pcdev->base);
++err_ioremap:
++	release_mem_region(res->start, resource_size(res));
++err_request_mem_region:
++	devm_clk_put(&pdev->dev, pcdev->mipi_clk);
++err_clk_get_mipi:
++	devm_clk_put(&pdev->dev, pcdev->clk);
++err_clk_get_cim:
++err_get_irq:
++err_get_resource:
++	kfree(pcdev);
++//	cimvideo->ops = video_ops;
++err_kzalloc:
++	return ret;
++
++}
++
++static int ingenic_camera_remove(struct platform_device *pdev)
++{
++	struct ingenic_camera_dev *pcdev = platform_get_drvdata(pdev);
++
++	v4l2_async_notifier_unregister(&pcdev->notifier);
++	sysfs_remove_group(&pcdev->dev->kobj, &cim_debug_attr_group);
++	v4l2_device_unregister(&pcdev->v4l2_dev);
++	free_irq(pcdev->irq, pcdev);
++	iounmap(pcdev->base);
++	release_mem_region(pcdev->res->start, resource_size(pcdev->res));
++	devm_clk_put(&pdev->dev, pcdev->mipi_clk);
++	devm_clk_put(&pdev->dev, pcdev->clk);
++	kfree(pcdev);
++	dev_dbg(&pdev->dev, "ingenic Camera driver unloaded\n");
++	return 0;
++}
++
++static struct platform_driver ingenic_camera_driver = {
++	.probe		= ingenic_camera_probe,
++	.remove		= ingenic_camera_remove,
++	.driver		= {
++		.name	= DRIVER_NAME,
++		.owner	= THIS_MODULE,
++		.of_match_table = ingenic_camera_of_match,
++	},
++};
++
++module_platform_driver(ingenic_camera_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("anan <an.an@ingenic.cn>");
++MODULE_DESCRIPTION("ingenic Soc Camera Host Driver");
++MODULE_ALIAS("a ingenic-cim platform");
+diff --git a/module_drivers/drivers/media/platform/ingenic-cim/ingenic_camera.h b/module_drivers/drivers/media/platform/ingenic-cim/ingenic_camera.h
+new file mode 100644
+index 000000000..444929776
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-cim/ingenic_camera.h
+@@ -0,0 +1,581 @@
++/*
++ * Copyright (c) 2012 Ingenic Semiconductor Co., Ltd.
++ *              http://www.ingenic.com/
++ *
++ * Core file for Ingenic Display Controller driver
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __INGENIC_CAMERA_H__
++#define __INGENIC_CAMERA_H__
++
++#include <linux/videodev2.h>
++#include <uapi/linux/videodev2.h>
++//#include <media/soc_camera.h>
++#include <linux/clk.h>
++#include <linux/proc_fs.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-fwnode.h>
++#include <media/v4l2-ioctl.h>
++#include <media/v4l2-ctrls.h>
++#include <media/videobuf2-v4l2.h>
++//#include <media/v4l2-clk.h>
++//#include <media/v4l2-common.h>
++//#include <media/v4l2-event.h>
++
++
++#define VERSION_CODE		 KERNEL_VERSION(0, 0, 1)
++#define DRIVER_NAME		 "ingenic-cim"
++#define CAMERA_GSENSOR_VCC	"vcc_gsensor"
++#define CIM_BUS_FLAGS	\
++	(SOCAM_MASTER | SOCAM_VSYNC_ACTIVE_HIGH | \
++	 SOCAM_VSYNC_ACTIVE_LOW | SOCAM_HSYNC_ACTIVE_HIGH | \
++	 SOCAM_HSYNC_ACTIVE_LOW | SOCAM_PCLK_SAMPLE_RISING | \
++	 SOCAM_PCLK_SAMPLE_FALLING | SOCAM_DATAWIDTH_8)
++
++#define CIM_LUMI_SIZE		 (9 * 4)
++#define CIM_HIST_SIZE		 (256 * 4)
++#define VIDEO_MEM		 (16 * 2046 * 2046)
++#define INGENIC_CAMERA_CSI2_2_LANE	 1
++#define INGENIC_CAMERA_HSYNC_HIGH     2
++#define INGENIC_CAMERA_PCLK_RISING    4
++#define INGENIC_CAMERA_VSYNC_HIGH     6
++
++/* ingenic cim ctrl id */
++#define INGENIC_CID_CUSTOM_BASE		(V4L2_CID_USER_BASE | 0xf000)
++#define INGENIC_CID_SCALE_SHARP		(INGENIC_CID_CUSTOM_BASE + 1)
++#define INGENIC_CID_HIST_EN		(INGENIC_CID_CUSTOM_BASE + 2)
++#define INGENIC_CID_HIST_GAIN_ADD	(INGENIC_CID_CUSTOM_BASE + 3)
++#define INGENIC_CID_HIST_GAIN_MUL	(INGENIC_CID_CUSTOM_BASE + 4)
++#define INGENIC_CID_CROP_WAY		(INGENIC_CID_CUSTOM_BASE + 5)
++#define INGENIC_CID_SNAPSHOT_EN		(INGENIC_CID_CUSTOM_BASE + 6)
++#define INGENIC_CID_EXP_PULSE_W		(INGENIC_CID_CUSTOM_BASE + 7)
++#define INGENIC_CID_SNAPSHOT_DELAY_T	(INGENIC_CID_CUSTOM_BASE + 8)
++#define INGENIC_CID_POINT2_X		(INGENIC_CID_CUSTOM_BASE + 9)
++#define INGENIC_CID_POINT2_Y		(INGENIC_CID_CUSTOM_BASE + 10)
++#define INGENIC_CID_OUTPUT_Y		(INGENIC_CID_CUSTOM_BASE + 11)
++#define INGENIC_CID_LUMI_EN		(INGENIC_CID_CUSTOM_BASE + 12)
++#define INGENIC_CID_POINT1_X		(INGENIC_CID_CUSTOM_BASE + 13)
++#define INGENIC_CID_POINT1_Y		(INGENIC_CID_CUSTOM_BASE + 14)
++
++#define INGENIC_MEDIA_BUS_FMT_RBG565_2X8_LE             0x1118
++#define INGENIC_MEDIA_BUS_FMT_BRG565_2X8_LE             0x1119
++#define INGENIC_MEDIA_BUS_FMT_GRB565_2X8_LE             0x111a
++#define INGENIC_MEDIA_BUS_FMT_GBR565_2X8_LE             0x111b
++
++
++#define INGENIC_V4L2_PIX_FMT_RBG565  v4l2_fourcc('R', 'B', 'G', 'P') /* 16  RBG-5-6-5     */
++#define INGENIC_V4L2_PIX_FMT_BGR565  v4l2_fourcc('B', 'G', 'R', 'P') /* 16  BGR-5-6-5     */
++#define INGENIC_V4L2_PIX_FMT_BRG565  v4l2_fourcc('B', 'R', 'G', 'P') /* 16  BRG-5-6-5     */
++#define INGENIC_V4L2_PIX_FMT_GRB565  v4l2_fourcc('G', 'R', 'B', 'P') /* 16  GRB-5-6-5     */
++#define INGENIC_V4L2_PIX_FMT_GBR565  v4l2_fourcc('G', 'B', 'R', 'P') /* 16  GBR-5-6-5     */
++
++struct cim_video_format {
++	const char *name;
++	unsigned int fourcc;
++	unsigned int depth[3];  /*max 3 plane*/
++	unsigned int mbus_code;
++	unsigned int num_planes;
++	enum v4l2_colorspace colorspace;
++};
++
++typedef union DES_INTC{
++	unsigned int d32;
++	struct{
++		unsigned reserved0:1;
++		unsigned EOF_MSK:1;
++		unsigned SOF_MSK:1;
++		unsigned reserved3_31:29;
++	}data;
++
++}DES_INTC_t;
++
++typedef union DES_CFG{
++	unsigned int d32;
++	struct{
++		unsigned DES_END:1;
++		unsigned reserved1_15:15;
++		unsigned WRBK_FMT:3;
++		unsigned reserved19_25:7;
++		unsigned ID:6;
++	}data;
++
++}DES_CFG_t;
++
++typedef union DES_HIST_CFG {
++	unsigned int d32;
++	struct{
++		unsigned int GAIN_MUL:8;
++		unsigned int GAIN_ADD:8;
++		unsigned int reserved16_30:15;
++		unsigned int HIST_EN:1;
++	};
++}DES_HIST_CFG_t;
++
++typedef union DES_LUMI_CFG {
++	unsigned int d32;
++	struct{
++		unsigned int reserved0_29:30;
++		unsigned int LUMI_EN:1;
++		unsigned int reserved31:1;
++	};
++}DES_LUMI_CFG_t;
++
++struct ingenic_camera_desc_v1{
++	dma_addr_t    next;
++	unsigned int  WRBK_ADDR;
++	unsigned int  WRBK_STRD;
++	DES_INTC_t    DES_INTC_t;
++	DES_CFG_t     DES_CFG_t;
++	DES_HIST_CFG_t DES_HIST_CFG_t;
++	unsigned int HIST_WRBK_ADDR;
++	unsigned int SF_WRBK_ADDR;
++}__attribute__ ((aligned (8)));
++
++struct ingenic_camera_desc_v2{
++	dma_addr_t    next;
++	unsigned int  WRBK_ADDR;
++	unsigned int  WRBK_STRD;
++	DES_INTC_t    DES_INTC_t;
++	DES_CFG_t     DES_CFG_t;
++	DES_LUMI_CFG_t DES_LUMI_CFG_t;
++	unsigned int LUMI_WRBK_ADDR;
++	unsigned int SF_WRBK_ADDR;
++}__attribute__ ((aligned (8)));
++
++struct cim_private {
++	int max_video_mem;
++	int version_num;
++};
++
++struct sensor_pdata {
++	unsigned int gpio_rst;
++	unsigned int gpio_power;
++	unsigned int gpio_en;
++//	enum v4l2_mbus_type dat_if;
++	/* senser support snapshot function */
++	unsigned short snapshot;
++	/* snapshot exposure pulse time, unit pixclk cycle */
++	unsigned short exp_pulse_w;
++	/* the time it takes to end a frame
++	 * to the next frame start*/
++	unsigned int delay_t;
++};
++
++struct ingenic_camera_pdata {
++	unsigned long mclk_10khz;
++	unsigned long flags;
++	struct sensor_pdata sensor_pdata;
++};
++
++/* buffer for one video frame */
++struct ingenic_buffer {
++	/* common v4l buffer stuff -- must be first */
++	struct vb2_v4l2_buffer vb;
++	struct list_head list;
++};
++
++enum {
++	IMG_NO_RESIZE,
++	IMG_RESIZE_CROP,
++};
++
++enum {
++	CROP_SPECIFY_ZONE,
++	CROP_BASE_MAX_PIC,
++};
++
++struct ingenic_image_sz{
++	bool rsz_flag;
++	unsigned int src_w;	//camera input size
++	unsigned int src_h;
++
++	unsigned int c_left;	//crop size
++	unsigned int c_top;
++	unsigned int c_w;
++	unsigned int c_h;
++};
++
++struct cim_async_subdev {
++//	struct v4l2_subdev *sd;
++	struct v4l2_async_subdev asd;
++	int index;
++
++	enum v4l2_mbus_type bus_type;
++	struct v4l2_fwnode_bus_parallel parallel;
++	struct v4l2_fwnode_bus_mipi_csi2 mipi_csi2;
++
++//	int enabled;
++
++//	unsigned int    source_pad;
++};
++
++
++struct cim_video_device {
++	struct ingenic_camera_dev *pcdev;
++	struct device *dev;
++	struct v4l2_subdev *subdev;
++	char *name;
++	int index;
++	struct video_device video;
++
++	void *alloc_ctx;
++//	struct vb2_queue *queue;
++	struct mutex queue_lock;
++	struct mutex stream_lock;
++
++	unsigned int max_buffer_num;    /*max vb2 num*/
++};
++
++struct cim_video_ctx {
++	struct cim_video_device cimvideo;
++	struct vb2_queue queue;
++	struct v4l2_ctrl_handler hdl;
++	struct v4l2_fh  fh;     /*handle*/
++	struct ingenic_image_sz img_sz;
++	struct v4l2_format format;
++	unsigned int interlace;
++	unsigned int uv_offset;
++	unsigned int payload_size;
++
++	unsigned int hist_en;
++	unsigned int hist_gain_add;
++	unsigned int hist_gain_mul;
++	unsigned int lumi_en;
++	unsigned int snapshot;
++	unsigned int output_y;
++};
++
++
++#define MAX_ASYNC_SUBDEVS 2
++
++struct ingenic_camera_dev {
++	struct v4l2_device v4l2_dev;
++	struct v4l2_async_notifier notifier;
++	struct cim_async_subdev casd[MAX_ASYNC_SUBDEVS];
++	struct v4l2_fwnode_endpoint     vep[MAX_ASYNC_SUBDEVS];
++	struct cim_video_ctx *ctx[MAX_ASYNC_SUBDEVS];
++	struct cim_video_ctx *active_ctx;
++	unsigned int asd_num;
++	struct mutex mutex;
++
++	struct ingenic_buffer *active;
++	struct list_head video_buffer_list;
++
++	int	sequence;
++	int	start_streaming_called;
++	unsigned int buf_cnt;
++
++
++        struct device *dev;
++	struct resource *res;
++	struct clk *clk;
++	struct clk *mclk;
++	struct clk *mipi_clk;
++	void __iomem *base;
++	unsigned int irq;
++	unsigned long mclk_freq;
++	spinlock_t lock;
++
++	void *desc_vaddr;
++	struct ingenic_camera_desc_v1 *desc_v1_paddr;
++	struct ingenic_camera_desc_v1 *desc_v1_head;
++	struct ingenic_camera_desc_v1 *desc_v1_tail;
++
++	struct ingenic_camera_desc_v2 *desc_v2_paddr;
++	struct ingenic_camera_desc_v2 *desc_v2_head;
++	struct ingenic_camera_desc_v2 *desc_v2_tail;
++
++	struct ingenic_camera_pdata *pdata;
++	const struct of_device_id *priv;
++	struct cim_private *cim_priv;
++};
++
++#define GENMASK(h, l) \
++	(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
++
++#define	GLB_CFG					(0x0000)
++#define FRM_SIZE				(0x0004)
++#define CROP_SITE				(0x0008)
++#define RESIZE_CFG				(0x000c)
++#define RESIZE_COEF_X				(0x0010)
++#define RESIZE_COEF_Y				(0x0014)
++#define SCAN_CFG				(0x0018)
++#define DLY_CFG					(0x001C)
++#define QOS_CTRL				(0x0020)
++#define QOS_CFG					(0x0024)
++#define LUMI_POINT1				(0x0028)
++#define LUMI_POINT2				(0x002c)
++#define DES_ADDR				(0x1000)
++#define CIM_CTRL				(0x2000)
++#define CIM_ST					(0x2004)
++#define CIM_CLR_ST				(0x2008)
++#define CIM_INTC				(0x200c)
++#define INT_FLAG				(0x2010)
++#define FRAME_ID				(0x2014)
++#define ACT_SIZE				(0x2018)
++#define DBG_DES					(0x3000)
++#define DBG_DMA					(0x3004)
++#define DBG_CGC					(0x3008)
++
++/** GLOBAL register*/
++#define GLB_CFG_C_ORDER_HBIT_V1			23
++#define GLB_CFG_C_ORDER_HBIT_V2			24
++#define GLB_CFG_C_ORDER_LBIT			20
++#define GLB_CFG_C_ORDER_MASK_V1	\
++	GENMASK(GLB_CFG_C_ORDER_HBIT_V1, GLB_CFG_C_ORDER_LBIT)
++#define GLB_CFG_C_ORDER_MASK_V2	\
++	GENMASK(GLB_CFG_C_ORDER_HBIT_V2, GLB_CFG_C_ORDER_LBIT)
++#define GLB_CFG_C_ORDER_RGB			(0x0 << GLB_CFG_C_ORDER_LBIT)
++#define GLB_CFG_C_ORDER_RBG			(0x1 << GLB_CFG_C_ORDER_LBIT)
++#define GLB_CFG_C_ORDER_GRB			(0x2 << GLB_CFG_C_ORDER_LBIT)
++#define GLB_CFG_C_ORDER_GBR			(0x3 << GLB_CFG_C_ORDER_LBIT)
++#define GLB_CFG_C_ORDER_BRG			(0x4 << GLB_CFG_C_ORDER_LBIT)
++#define GLB_CFG_C_ORDER_BGR			(0x5 << GLB_CFG_C_ORDER_LBIT)
++#define GLB_CFG_C_ORDER_YUYV			(0x8 << GLB_CFG_C_ORDER_LBIT)
++#define GLB_CFG_C_ORDER_YVYU			(0x9 << GLB_CFG_C_ORDER_LBIT)
++#define GLB_CFG_C_ORDER_UYVY			(0xa << GLB_CFG_C_ORDER_LBIT)
++#define GLB_CFG_C_ORDER_VYUY			(0xb << GLB_CFG_C_ORDER_LBIT)
++#define GLB_CFG_C_ORDER_RGGB			(0x10 << GLB_CFG_C_ORDER_LBIT)
++#define GLB_CFG_C_ORDER_BGGR			(0x11 << GLB_CFG_C_ORDER_LBIT)
++#define GLB_CFG_C_ORDER_GRBG			(0x12 << GLB_CFG_C_ORDER_LBIT)
++#define GLB_CFG_C_ORDER_GBRG			(0x13 << GLB_CFG_C_ORDER_LBIT)
++
++#define GLB_CFG_ORG_FMT_HBIT_V1			18
++#define GLB_CFG_ORG_FMT_HBIT_V2			19
++#define GLB_CFG_ORG_FMT_LBIT			16
++#define GLB_CFG_ORG_FMT_MASK_V1	\
++	GENMASK(GLB_CFG_ORG_FMT_HBIT_V1, GLB_CFG_ORG_FMT_LBIT)
++#define GLB_CFG_ORG_FMT_MASK_V2	\
++	GENMASK(GLB_CFG_ORG_FMT_HBIT_V2, GLB_CFG_ORG_FMT_LBIT)
++#define GLB_CFG_ORG_FMT_RGB565			(0x0 << GLB_CFG_ORG_FMT_LBIT)
++#define GLB_CFG_ORG_FMT_RGB888			(0x1 << GLB_CFG_ORG_FMT_LBIT)
++#define GLB_CFG_ORG_FMT_YUYV422			(0x2 << GLB_CFG_ORG_FMT_LBIT)
++#define GLB_CFG_ORG_FMT_ITU656			(0x3 << GLB_CFG_ORG_FMT_LBIT)
++#define GLB_CFG_ORG_FMT_MONO			(0x4 << GLB_CFG_ORG_FMT_LBIT)
++#define GLB_CFG_ORG_FMT_10BIT_MONO		(0x5 << GLB_CFG_ORG_FMT_LBIT)
++#define GLB_CFG_ORG_FMT_12BIT_MONO		(0x6 << GLB_CFG_ORG_FMT_LBIT)
++#define GLB_CFG_ORG_FMT_8BIT_RAW		(0x7 << GLB_CFG_ORG_FMT_LBIT)
++#define GLB_CFG_ORG_FMT_10BIT_RAW		(0x8 << GLB_CFG_ORG_FMT_LBIT)
++#define GLB_CFG_ORG_FMT_12BIT_RAW		(0x9 << GLB_CFG_ORG_FMT_LBIT)
++
++#define GLB_CFG_DE_PCLK				BIT(15)
++#define GLB_CFG_DL_VSYNC			BIT(14)
++#define GLB_CFG_DL_HSYNC			BIT(13)
++
++#define GLB_CFG_EXPO_WIDTH_HBIT_V1		10
++#define GLB_CFG_EXPO_WIDTH_HBIT_V2		12
++#define GLB_CFG_EXPO_WIDTH_LBIT			8
++#define	GLB_CFG_EXPO_WIDTH_MASK_V1	\
++	GENMASK(GLB_CFG_EXPO_WIDTH_HBIT_V1, GLB_CFG_EXPO_WIDTH_LBIT)
++#define	GLB_CFG_EXPO_WIDTH_MASK_V2		\
++	GENMASK(GLB_CFG_EXPO_WIDTH_HBIT_V2, GLB_CFG_EXPO_WIDTH_LBIT)
++#define GLB_CFG_SIZE_CHK			BIT(5)
++#define GLB_CFG_DAT_IF_SEL			BIT(4)
++#define GLB_CFG_DAT_MODE			BIT(3)
++
++#define GLB_CFG_BURST_LEN_HBIT			2
++#define GLB_CFG_BURST_LEN_LBIT			1
++#define	GLB_CFG_BURST_LEN_MASK		\
++	GENMASK(GLB_CFG_BURST_LEN_HBIT, GLB_CFG_BURST_LEN_LBIT)
++#define	GLB_CFG_BURST_LEN_4			(0x0 << GLB_CFG_BURST_LEN_LBIT)
++#define	GLB_CFG_BURST_LEN_8			(0x1 << GLB_CFG_BURST_LEN_LBIT)
++#define	GLB_CFG_BURST_LEN_16			(0x2 << GLB_CFG_BURST_LEN_LBIT)
++#define	GLB_CFG_BURST_LEN_32			(0x3 << GLB_CFG_BURST_LEN_LBIT)
++
++#define GLB_CFG_AUTO_RECOVERY			BIT(0)
++
++
++/**Frame size register*/
++#define CIM_CROP_WIDTH_HBIT			10
++#define CIM_CROP_WIDTH_LBIT			0
++#define	CIM_CROP_WIDTH_MASK	\
++	GENMASK(CIM_CROP_WIDTH_HBIT, CIM_CROP_WIDTH_LBIT)
++
++#define CIM_CROP_HEIGHT_HBIT			26
++#define CIM_CROP_HEIGHT_LBIT			16
++#define	CIM_CROP_HEIGHT_MASK	\
++	GENMASK(CIM_CROP_HEIGHT_HBIT, CIM_CROP_HEIGHT_LBIT)
++
++/**Crop site register*/
++
++#define CIM_CROP_X_HBIT				10
++#define CIM_CROP_X_LBIT				0
++#define CIM_CROP_X_MASK		\
++	GENMASK(CIM_CROP_X_HBIT, CIM_CROP_X_LBIT)
++
++#define CIM_CROP_Y_HBIT				26
++#define CIM_CROP_Y_LBIT				16
++#define CIM_CROP_Y_MASK		\
++	GENMASK(CIM_CROP_Y_HBIT, CIM_CROP_Y_LBIT)
++
++/** Scale size register*/
++#define CIM_TAR_WIDTH_HBIT			10
++#define CIM_TAR_WIDTH_LBIT			0
++#define CIM_TAR_WIDTH_MASK	\
++	GENMASK(CIM_TAR_WIDTH_HBIT, CIM_TAR_WIDTH_LBIT)
++
++#define CIM_TAR_HEIGHT_HBIT			26
++#define CIM_TAR_HEIGHT_LBIT			16
++#define CIM_TAR_HEIGHT_MASK	\
++	GENMASK(CIM_TAR_HEIGHT_HBIT, CIM_TAR_HEIGHT_LBIT)
++
++#define CIM_SHARPL_HBIT				15
++#define CIM_SHARPL_LBIT				14
++#define CIM_SHARPL_MASK		\
++	GENMASK(CIM_SHARPL_HBIT, CIM_SHARPL_LBIT)
++#define CIM_LOWST_SHARPL			(0x0 << CIM_SHARPL_LBIT)
++#define CIM_HIGST_SHARPL			(0x3 << CIM_SHARPL_LBIT)
++
++#define CIM_SCALE_EN				BIT(31)
++
++/**Resize Coef X register*/
++#define CIM_RESIZE_COEF_X_HBIT			19
++#define CIM_RESIZE_COEF_X_LBIT			0
++#define CIM_RESIZE_COEF_X_MASK		\
++	GENMASK(CIM_RESIZE_COEF_X_HBIT, CIM_RESIZE_COEF_X_LBIT)
++
++/**Resize Coef Y register*/
++
++#define CIM_RESIZE_COEF_Y_HBIT			19
++#define CIM_RESIZE_COEF_Y_LBIT			0
++#define CIM_RESIZE_COEF_Y_MASK		\
++	GENMASK(CIM_RESIZE_COEF_Y_HBIT, CIM_RESIZE_COEF_Y_LBIT)
++
++/**Second Field Height register*/
++#define CIM_SF_HEIGHT_HBIT			11
++#define CIM_SF_HEIGHT_LBIT			0
++#define CIM_SF_HEIGHT_MASK	\
++	GENMASK(CIM_SF_HEIGHT_HBIT, CIM_SF_HEIGHT_LBIT)
++
++#define CIM_F_ORDER				BIT(30)
++#define CIM_SCAN_MD				BIT(31)
++
++/**Delay counter register*/
++#define CIM_DLY_NUM_HBIT			23
++#define CIM_DLY_NUM_LBIT			0
++#define CIM_DLY_NUM_MASK	\
++	GENMASK(CIM_DLY_NUM_HBIT, CIM_DLY_NUM_LBIT)
++
++#define CIM_EXPO_WIDTH_EN			BIT(0)
++#define CIM_DLY_MD				BIT(30)
++#define CIM_DLY_EN				BIT(31)
++
++#define CIM_QOS_CTRL				BIT(0)
++#define CIM_QOS_VAL_HBIT			2
++#define CIM_QOS_VAL_LBIT			1
++#define CIM_QOS_VAL_MASK	\
++	GENMASK(CIM_QOS_VAL_HBIT, CIM_QOS_VAL_LBIT)
++
++#define CIM_QOS_CFG_TH2_LBIT			(26)
++#define CIM_QOS_CFG_TH2_HBIT			(18)
++#define CIM_QOS_CFG_TH2_MASK	\
++	GENMASK(CIM_QOS_CFG_TH2_HBIT, CIM_QOS_CFG_TH2_LBIT)
++#define CIM_QOS_CFG_TH1_LBIT			(17)
++#define CIM_QOS_CFG_TH1_HBIT			(9)
++#define CIM_QOS_CFG_TH1_MASK	\
++	GENMASK(CIM_QOS_CFG_TH1_HBIT, CIM_QOS_CFG_TH1_LBIT)
++#define CIM_QOS_CFG_TH0_LBIT			(0)
++#define CIM_QOS_CFG_TH0_HBIT			(8)
++#define CIM_QOS_CFG_TH0_MASK	\
++	GENMASK(CIM_QOS_CFG_TH0_HBIT, CIM_QOS_CFG_TH0_LBIT)
++
++/**Descriptor address register*/
++#define CIM_DES_ADDR_HBIT			31
++#define CIM_DES_ADDR_LBIT			0
++#define CIM_DES_ADDR_MASK	\
++	GENMASK(CIM_DES_ADDR_HBIT, CIM_DES_ADDR_LBIT)
++
++/**Control register*/
++#define CIM_CTRL_START				BIT(0)
++#define CIM_CTRL_QCK_STOP			BIT(1)
++#define CIM_CTRL_GEN_STOP			BIT(2)
++#define CIM_CTRL_SOFT_RST			BIT(3)
++#define CIM_CTRL_DBG_DES_RST			BIT(4)
++
++/**status register*/
++#define CIM_ST_WORKING				BIT(0)
++#define CIM_ST_EOF				BIT(1)
++#define CIM_ST_SOF				BIT(2)
++#define CIM_ST_GSA				BIT(3)
++#define CIM_ST_OVER				BIT(4)
++#define CIM_ST_EOW				BIT(5)
++#define CIM_ST_SZ_ERR				BIT(6)
++#define CIM_ST_SRST				BIT(7)
++
++/**Clear status register*/
++#define CIM_CLR_FRM_END				BIT(1)
++#define CIM_CLR_FRM_START			BIT(2)
++#define CIM_CLR_GSA				BIT(3)
++#define CIM_CLR_OVER				BIT(4)
++#define CIM_CLR_EOW				BIT(5)
++#define CIM_CLR_SZ_ERR				BIT(6)
++#define CIM_CLR_SRST				BIT(7)
++#define CIM_CLR_ALL	\
++	(CIM_CLR_FRM_END | CIM_CLR_FRM_START | \
++	 CIM_CLR_GSA | CIM_CLR_OVER | \
++	 CIM_CLR_EOW | CIM_CLR_SZ_ERR)
++
++/**CIM INTC register*/
++#define CIM_INTC_MSK_EOF			BIT(1)
++#define CIM_INTC_MSK_SOF			BIT(2)
++#define CIM_INTC_MSK_GSA			BIT(3)
++#define CIM_INTC_MSK_OVER			BIT(4)
++#define CIM_INTC_MSK_EOW			BIT(5)
++#define CIM_INTC_MSK_SZ_ERR			BIT(6)
++
++/**CIM_INT_FLAG*/
++#define CIM_INT_FLAG_EOF			BIT(1)
++#define CIM_INT_FLAG_SOF			BIT(2)
++#define CIM_INT_FLAG_GSA			BIT(3)
++#define CIM_INT_FLAG_OVER			BIT(4)
++#define CIM_INT_FLAG_EOW			BIT(5)
++#define CIM_INT_FLAG_SZ_ERR			BIT(6)
++
++#define CIM_CGC_FLOW				BIT(0)
++#define CIM_CGC_DVP				BIT(1)
++#define CIM_CGC_SCALE				BIT(2)
++#define CIM_CGC_DES				BIT(3)
++#define CIM_CGC_WRBK				BIT(4)
++#define CIM_CGC_REG				BIT(5)
++
++/**dma Write back format*/
++#define DES_CFG_WRBK_FMT_HBIT			18
++#define DES_CFG_WRBK_FMT_LBIT			16
++#define DES_CFG_WRBK_FMT_MASK	\
++	GENMASK(DES_CFG_WRBK_FMT_HBIT, DES_CFG_WRBK_FMT_LBIT)
++
++#define WRBK_FMT_RGB888				(6)
++#define WRBK_FMT_Y				(5)
++#define WRBK_FMT_MONO				(4)
++#define WRBK_FMT_YUV422				(3)
++#define WRBK_FMT_RGB565				(1)
++
++
++#define CIM_HSIT_EN				BIT(31)
++#define CIM_GAIN_ADD_HBIT			15
++#define CIM_GAIN_ADD_LBIT			8
++#define CIM_GAIN_ADD_MASK	\
++	GENMASK(CIM_GAIN_ADD_HBIT, CIM_GAIN_ADD_LBIT)
++#define CIM_GAIN_MUL_HBIT			7
++#define CIM_GAIN_MUL_LBIT			0
++#define CIM_GAIN_MUL_MASK	\
++	GENMASK(CIM_GAIN_MUL_HBIT, CIM_GAIN_MUL_LBIT)
++
++static inline void cim_writel(struct ingenic_camera_dev *pcdev,
++			unsigned int val, unsigned int off)
++{
++	writel(val, pcdev->base + off);
++}
++
++static inline unsigned int cim_readl(struct ingenic_camera_dev *pcdev,
++			unsigned int off)
++{
++	return readl(pcdev->base + off);
++}
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-cim/mipi_csi.c b/module_drivers/drivers/media/platform/ingenic-cim/mipi_csi.c
+new file mode 100644
+index 000000000..cf143f883
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-cim/mipi_csi.c
+@@ -0,0 +1,222 @@
++/*
++ * Copyright (c) 2012 Ingenic Semiconductor Co., Ltd.
++ *              http://www.ingenic.com/
++ *
++ * Core file for Ingenic Display Controller driver
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++#include <linux/delay.h>
++#include "mipi_csi.h"
++
++void dump_csi_reg(void)
++{
++	printk("****>>>>> dump csi reg <<<<<******\n");
++	printk("**********VERSION =%08x\n", csi_core_read(VERSION));
++	printk("**********N_LANES =%08x\n", csi_core_read(N_LANES));
++	printk("**********PHY_SHUTDOWNZ = %08x\n", csi_core_read(PHY_SHUTDOWNZ));
++	printk("**********DPHY_RSTZ = %08x\n", csi_core_read(DPHY_RSTZ));
++	printk("**********CSI2_RESETN =%08x\n", csi_core_read(CSI2_RESETN));
++	printk("**********PHY_STATE = %08x\n", csi_core_read(PHY_STATE));
++	printk("**********DATA_IDS_1 = %08x\n", csi_core_read(DATA_IDS_1));
++	printk("**********DATA_IDS_2 = %08x\n", csi_core_read(DATA_IDS_2));
++	printk("**********ERR1 = %08x\n", csi_core_read(ERR1));
++	printk("**********ERR2 = %08x\n", csi_core_read(ERR2));
++	printk("**********MASK1 =%08x\n", csi_core_read(MASK1));
++	printk("**********MASK2 =%08x\n", csi_core_read(MASK2));
++	printk("**********PHY_TST_CTRL0 = %08x\n", csi_core_read(PHY_TST_CTRL0));
++	printk("**********PHY_TST_CTRL1 = %08x\n", csi_core_read(PHY_TST_CTRL1));
++}
++
++void check_csi_error(void) {
++
++	unsigned int temp1, temp2;
++	while(1){
++		dump_csi_reg();
++		temp1 = csi_core_read(ERR1);
++		temp2 = csi_core_read(ERR2);
++		if(temp1 != 0)
++			printk("error-------- 1:0x%08x\n", temp1);
++		if(temp2 != 0)
++			printk("error-------- 2:0x%08x\n", temp2);
++	}
++}
++
++static unsigned char csi_core_write_part(unsigned int address, unsigned int data, unsigned char shift, unsigned char width)
++{
++        unsigned int mask = (1 << width) - 1;
++        unsigned int temp = csi_core_read(address);
++        temp &= ~(mask << shift);
++        temp |= (data & mask) << shift;
++        csi_core_write(address, temp);
++
++	return 0;
++}
++
++static unsigned char  csi_event_disable(unsigned int  mask, unsigned char err_reg_no)
++{
++	switch (err_reg_no)
++	{
++		case 1:
++			csi_core_write(MASK1, mask | csi_core_read(MASK1));
++			break;
++		case 2:
++			csi_core_write(MASK2, mask | csi_core_read(MASK2));
++			break;
++		default:
++			return ERR_OUT_OF_BOUND;
++	}
++
++	return 0;
++}
++
++unsigned char csi_set_on_lanes(unsigned char lanes)
++{
++	csi_core_write_part(N_LANES, (lanes - 1), 0, 2);
++	return 0;
++}
++
++static int csi_phy_ready(void)
++{
++	int ready;
++
++	// TODO: phy0: lane0 is ready. need to be update for other lane
++	ready = csi_core_read(PHY_STATE);
++
++	if ((ready & (1 << 10 )) && (ready & (1<<4)))
++		return 1;
++
++	return 0;
++}
++
++
++/* Reduce power consumption */
++int csi_phy_set_bandgap(void)
++{
++	unsigned int reg;
++
++	/*reset phy*/
++	csi_core_write_part(PHY_SHUTDOWNZ, 0, 0, 1);
++	csi_core_write_part(CSI2_RESETN, 0, 0, 1);
++	csi_core_write_part(DPHY_RSTZ, 0, 0, 1);
++
++	csi_core_write_part(CSI2_RESETN, 1, 0, 1);
++	csi_core_write_part(DPHY_RSTZ, 1, 0, 1);
++	csi_core_write_part(PHY_SHUTDOWNZ, 1, 0, 1);
++
++	/* set bandgap (reg0b[7])*/
++	reg = csi_phy_read(RXPHY_REG_0_0b);
++	reg |= (0x1 << 7);
++	csi_phy_write(RXPHY_REG_0_0b, reg);
++	/* printk("debug ---- > reg0b[7]:0x%08x, %d\n", csi_phy_read(RXPHY_REG_0_0b), __LINE__); */
++	return 0;
++}
++
++int csi_phy_start(int version, unsigned int lans)
++{
++	int retries = 30;
++	int i;
++	unsigned int reg;
++
++	if (version == 1) {
++		printk("*******%s***** lans = %d\n", __func__, lans);
++		csi_set_on_lanes(lans);
++
++		/* both csi0 csi1 */
++		*(volatile unsigned int *) 0xb0074008 = 1;
++		*(volatile unsigned int *) 0xb007400c = 1;
++		*(volatile unsigned int *) 0xb0073008 = 1;
++		*(volatile unsigned int *) 0xb007300c = 1;
++
++		csi_core_write_part(CSI2_RESETN, 0, 0, 1);
++		csi_core_write_part(CSI2_RESETN, 1, 0, 1);
++	} else {
++		/*reset phy*/
++		csi_core_write_part(PHY_SHUTDOWNZ, 0, 0, 1);
++		csi_core_write_part(CSI2_RESETN, 0, 0, 1);
++		csi_core_write_part(DPHY_RSTZ, 0, 0, 1);
++
++		printk("lans: %d\n", lans);
++		csi_set_on_lanes(lans);
++
++		csi_core_write_part(CSI2_RESETN, 1, 0, 1);
++		csi_core_write_part(DPHY_RSTZ, 1, 0, 1);
++		csi_core_write_part(PHY_SHUTDOWNZ, 1, 0, 1);
++
++		udelay(1000);
++
++		/*r/w phy register*/
++		switch(lans) {
++			case 1:
++				csi_phy_write(RXPHY_REG_0_00, 0x75);
++				break;
++			case 2:
++				csi_phy_write(RXPHY_REG_0_00, 0x7d);
++				break;
++			default:
++				printk("Config lans error\n");
++				break;
++		}
++		csi_phy_write(RXPHY_REG_2_0a, 0x3f);
++
++		/* clear bandgap (reg0b[7])*/
++		reg = csi_phy_read(RXPHY_REG_0_0b);
++		reg &= ~(0x1 << 7);
++		csi_phy_write(RXPHY_REG_0_0b, reg);
++		/* printk("debug ---- > reg0b[7]:0x%08x\n", csi_phy_read(RXPHY_REG_0_0b)); */
++
++	}
++
++	/* MASK all interrupts */
++	csi_event_disable(0xffffffff, 1);
++	csi_event_disable(0xffffffff, 2);
++
++	if (version == 2) {
++		/* wait for phy ready */
++		for (i = 0; i < retries; i++) {
++			if (csi_phy_ready())
++				break;
++			udelay(300);
++		}
++
++		if (i >= retries) {
++			printk("CSI PHY is not ready\n");
++			return -1;
++
++
++		}
++	}
++
++	return 0;
++}
++
++int csi_phy_stop(int version)
++{
++
++	printk("csi_phy_stop being called \n");
++	/*reset phy*/
++	/* both csi0 csi1 */
++	if (version == 1) {
++		*(volatile unsigned int *) 0xb0074008 = 0;
++		*(volatile unsigned int *) 0xb007400c = 0;
++	} else {
++		csi_phy_set_bandgap();
++	}
++	*(volatile unsigned int *) 0xb0073008 = 0;
++	*(volatile unsigned int *) 0xb007300c = 0;
++//	csi_core_write_part(PHY_SHUTDOWNZ, 0, 0, 1);
++//	csi_core_write_part(DPHY_RSTZ, 0, 0, 1);
++	csi_core_write_part(CSI2_RESETN, 0, 0, 1);
++
++	return 0;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-cim/mipi_csi.h b/module_drivers/drivers/media/platform/ingenic-cim/mipi_csi.h
+new file mode 100644
+index 000000000..fbb11cc5e
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-cim/mipi_csi.h
+@@ -0,0 +1,98 @@
++/*
++ * Copyright (c) 2012 Ingenic Semiconductor Co., Ltd.
++ *              http://www.ingenic.com/
++ *
++ * Core file for Ingenic Display Controller driver
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __MIPI_CSI_H__
++#define __MIPI_CSI_H__
++
++/* csi host regs, base addr should be defined in board cfg */
++#ifdef CONFIG_SOC_X1600
++#define DWC_CSI_CTRL_BASE		0xB0073000
++#else
++#define DWC_CSI_CTRL_BASE		0xB0074000
++#endif
++#define INNO_CSI_PHY_BASE		0xB0076000
++
++/* csi controller */
++#define VERSION				0x00
++#define N_LANES				0x04
++#define PHY_SHUTDOWNZ			0x08
++#define DPHY_RSTZ			0x0C
++#define CSI2_RESETN			0x10
++#define PHY_STATE			0x14
++#define DATA_IDS_1			0x18
++#define DATA_IDS_2			0x1C
++#define ERR1				0x20
++#define ERR2				0x24
++#define MASK1				0x28
++#define MASK2				0x2C
++#define PHY_TST_CTRL0			0x30
++#define PHY_TST_CTRL1			0x34
++#define DEBUG				0x40
++
++/* csi d-phy */
++#define LANE_EN				0x000
++#define CLK_CNT_TIME			0x100
++#define L0_CNT_TIME			0x180
++#define L1_CNT_TIME			0x200
++#define L2_CNT_TIME			0x280
++#define L3_CNT_TIME			0x300
++#define CLK_CON_MODE			0x128
++#define SWITCH_LVDS_BANK		0x080
++#define MODEL_EN			0x2cc
++#define LVDS_LOGICAL_EN			0x300
++
++/* inno d-phy*/
++#define RXPHY_REG_0_00			0x00
++#define RXPHY_REG_0_0b			0x2c
++#define RXPHY_REG_0_0d			0x34
++#define RXPHY_REG_0_0e			0x38
++#define RXPHY_REG_0_0f			0x3c
++#define RXPHY_REG_0_12			0x48
++#define RXPHY_REG_1_00			0x80
++#define RXPHY_REG_2_0a			0x128
++#define RXPHY_REG_2_10			0x140
++#define RXPHY_REG_2_11			0x144
++#define RXPHY_REG_2_12			0x148
++
++typedef enum
++{
++	ERR_NOT_INIT = 0xFE,
++	ERR_ALREADY_INIT = 0xFD,
++	ERR_NOT_COMPATIBLE = 0xFC,
++	ERR_UNDEFINED = 0xFB,
++	ERR_OUT_OF_BOUND = 0xFA,
++	SUCCESS = 0
++} csi_error_t;
++
++
++#define dwc_csi_readl(reg)              \
++	readl((unsigned int *)(DWC_CSI_CTRL_BASE + reg))
++#define dwc_csi_writel(reg, value)          \
++	writel((value), (unsigned int *)(DWC_CSI_CTRL_BASE + reg))
++
++#define csi_core_write(addr, value) dwc_csi_writel(addr, value)
++#define csi_core_read(addr) dwc_csi_readl(addr)
++
++#define csi_phy_read(reg)              \
++	readl((unsigned int *)(INNO_CSI_PHY_BASE + reg))
++#define csi_phy_write(reg, value)          \
++	writel((value), (unsigned int *)(INNO_CSI_PHY_BASE + reg))
++
++/* function */
++extern int csi_phy_init(void);
++extern int csi_phy_start(int version, unsigned int lans);
++extern int csi_phy_stop(int version);
++
++extern void dump_csi_reg(void);
++extern void check_csi_error(void);
++extern unsigned char csi_set_on_lanes(unsigned char lanes);
++
++#endif/*__MIPI_CSI_H__*/
+diff --git a/module_drivers/drivers/media/platform/ingenic-i2d/Kconfig b/module_drivers/drivers/media/platform/ingenic-i2d/Kconfig
+new file mode 100644
+index 000000000..cfbf78953
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-i2d/Kconfig
+@@ -0,0 +1,16 @@
++menuconfig JZ_I2D
++    bool "JZ I2D Driver"
++    default n
++    depends on SOC_X2500 && VIDEO_DEV && VIDEO_V4L2
++    select VIDEOBUF2_DMA_CONTIG_INGENIC
++    select V4L2_MEM2MEM_DEV
++    help
++        Support for Ingenic i2d Driver
++
++config INGENIC_I2D
++	tristate "Ingenic I2D Driver"
++	depends on JZ_I2D
++	default n
++	help
++	  Support for Ingenic i2d operations (image rotater).
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-i2d/Makefile b/module_drivers/drivers/media/platform/ingenic-i2d/Makefile
+new file mode 100644
+index 000000000..3a4ab3a39
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-i2d/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_INGENIC_I2D)        += i2d_video.o ingenic_i2d.o
+diff --git a/module_drivers/drivers/media/platform/ingenic-i2d/i2d_video.c b/module_drivers/drivers/media/platform/ingenic-i2d/i2d_video.c
+new file mode 100644
+index 000000000..8e703661f
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-i2d/i2d_video.c
+@@ -0,0 +1,751 @@
++#include <linux/module.h>
++#include <linux/fs.h>
++#include <linux/version.h>
++#include <linux/timer.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/of.h>
++
++#include <linux/platform_device.h>
++#include <media/v4l2-mem2mem.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ioctl.h>
++#include <media/videobuf2-core.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++#include <media/ingenic_video_nr.h>
++
++#include "i2d_video.h"
++#include "ingenic_i2d.h"
++
++#define JZ_I2D_NAME		"jz-i2d"
++
++
++static struct i2d_fmt formats[] = {
++	{
++		.name	= "YUV 420",
++		.fourcc	= V4L2_PIX_FMT_NV12,
++		.depth	= 12,
++		.types	= MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
++	},
++	{
++		.name	= "RAW8",
++		.fourcc	= V4L2_PIX_FMT_SBGGR8,
++		.depth	= 16,
++		.types	= MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
++	},
++	{
++		.name	= "RGB_565",
++		.fourcc	= V4L2_PIX_FMT_RGB565,
++		.depth	= 16,
++		.types	= MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
++	},
++	{
++		.name	= "ARGB_8888",
++		.fourcc	= V4L2_PIX_FMT_ARGB32,
++		.depth	= 32,
++		.types	= MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
++	},
++};
++
++#define NUM_FORMATS ARRAY_SIZE(formats)
++
++static struct i2d_fmt *find_fmt(struct v4l2_format *f)
++{
++	unsigned int i;
++	for (i = 0; i < NUM_FORMATS; i++) {
++		if (formats[i].fourcc == f->fmt.pix.pixelformat)
++			return &formats[i];
++	}
++	return NULL;
++}
++
++static int vidioc_querycap(struct file *file, void *priv,
++				struct v4l2_capability *cap)
++{
++	strncpy(cap->driver, JZ_I2D_NAME, sizeof(cap->driver) - 1);
++	strncpy(cap->card, JZ_I2D_NAME, sizeof(cap->card) - 1);
++	cap->bus_info[0] = 0;
++	cap->version = KERNEL_VERSION(4, 4, 19);
++	/*
++	 * This is only a mem-to-mem video device. The capture and output
++	 * device capability flags are left only for backward compatibility
++	 * and are scheduled for removal.
++	 */
++	cap->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M;
++	cap->capabilities =  cap->device_caps |
++		V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
++		V4L2_CAP_DEVICE_CAPS;
++
++	return 0;
++}
++
++static inline struct ingenic_i2d_ctx *fh_to_ctx(struct v4l2_fh *fh)
++{
++	return container_of(fh, struct ingenic_i2d_ctx, fh);
++}
++
++static int enum_fmt(struct v4l2_fmtdesc *f, u32 type)
++{
++	int i, num;
++	struct i2d_fmt *fmt;
++
++	num = 0;
++	for (i = 0; i < NUM_FORMATS; ++i) {
++		if (formats[i].types & type) {
++			/* index-th format of type type found ? */
++			if (num == f->index)
++				break;
++			/* Correct type but haven't reached our index yet,
++			 * just increment per-type index */
++			++num;
++		}
++	}
++
++	if (i < NUM_FORMATS) {
++		/* Format found */
++		fmt = &formats[i];
++		strncpy(f->description, fmt->name, sizeof(f->description) - 1);
++		f->pixelformat = fmt->fourcc;
++		return 0;
++	}
++
++	/* Format not found */
++	return -EINVAL;
++}
++
++static int vidioc_try_fmt(struct file *file, void *prv, struct v4l2_format *f)
++{
++	struct i2d_fmt *fmt;
++	enum v4l2_field *field;
++
++	fmt = find_fmt(f);
++	if (!fmt)
++		return -EINVAL;
++
++	field = &f->fmt.pix.field;
++	if (*field == V4L2_FIELD_ANY)
++		*field = V4L2_FIELD_NONE;
++	else if (*field != V4L2_FIELD_NONE)
++		return -EINVAL;
++
++	if (f->fmt.pix.width > MAX_WIDTH
++		|| f->fmt.pix.height > MAX_HEIGHT
++		|| f->fmt.pix.width < MIN_WIDTH
++		|| f->fmt.pix.height < MIN_HEIGHT) {
++		return -EINVAL;
++	}
++
++	f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3;
++	f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
++	return 0;
++}
++static struct i2d_frame_info *get_frame(struct ingenic_i2d_ctx *ctx,
++		enum v4l2_buf_type type)
++{
++	switch (type) {
++	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++		return &ctx->out_info;
++	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++		return &ctx->cap_info;
++	default:
++		return ERR_PTR(-EINVAL);
++	}
++}
++static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
++				   struct v4l2_fmtdesc *f)
++{
++	return enum_fmt(f, MEM2MEM_CAPTURE);
++}
++
++static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
++				   struct v4l2_fmtdesc *f)
++{
++	return enum_fmt(f, MEM2MEM_OUTPUT);
++}
++
++static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f)
++{
++	struct ingenic_i2d_ctx *ctx = fh_to_ctx(prv);
++	struct vb2_queue *vq;
++	struct i2d_frame_info *frame;
++
++	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
++	if (!vq)
++		return -EINVAL;
++	frame = get_frame(ctx, f->type);
++	if (IS_ERR(frame))
++		return PTR_ERR(frame);
++
++	f->fmt.pix.width		= frame->width;
++	f->fmt.pix.height		= frame->height;
++	f->fmt.pix.field		= V4L2_FIELD_NONE;
++	f->fmt.pix.pixelformat		= frame->fmt->fourcc;
++	f->fmt.pix.bytesperline		= (frame->width * frame->fmt->depth) >> 3;
++	f->fmt.pix.sizeimage		= frame->size;
++	return 0;
++}
++
++static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f)
++{
++	struct ingenic_i2d_ctx *ctx = fh_to_ctx(prv);
++	struct ingenic_i2d_dev *dev = ctx->i2d_dev;
++	struct vb2_queue *vq;
++	struct i2d_frame_info *frame;
++	struct i2d_fmt *fmt;
++	int ret = 0;
++
++	/* Adjust all values accordingly to the hardware capabilities
++	 * and chosen format. */
++	ret = vidioc_try_fmt(file, prv, f);
++	if (ret)
++		return ret;
++	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
++	if (vb2_is_busy(vq)) {
++		v4l2_err(&dev->v4l2_dev, "queue (%d) bust\n", f->type);
++		return -EBUSY;
++	}
++	frame = get_frame(ctx, f->type);
++	if (IS_ERR(frame))
++		return PTR_ERR(frame);
++	fmt = find_fmt(f);
++	if (!fmt)
++		return -EINVAL;
++	frame->width	= f->fmt.pix.width;
++	frame->height	= f->fmt.pix.height;
++	frame->size		= f->fmt.pix.sizeimage;
++	frame->fmt		= fmt;
++	frame->bytesperline	= f->fmt.pix.bytesperline;
++	return 0;
++}
++
++static int vidioc_streamon(struct file *file, void *priv,
++					enum v4l2_buf_type type)
++{
++	struct ingenic_i2d_ctx *ctx = priv;
++
++	return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
++}
++
++static int vidioc_streamoff(struct file *file, void *priv,
++					enum v4l2_buf_type type)
++{
++	struct ingenic_i2d_ctx *ctx = priv;
++
++	return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
++}
++
++static int _i2d_vidioc_expbuf(struct file *file, void* prv,
++		  struct v4l2_exportbuffer *eb)
++{
++	struct vb2_queue *vq;
++	struct ingenic_i2d_ctx *ctx = fh_to_ctx(prv);
++	if(ctx->m2m_ctx){
++		return v4l2_m2m_expbuf(file,ctx->m2m_ctx,eb);
++	}
++	return -EINVAL;
++}
++
++static int i2d_queue_setup(struct vb2_queue *vq,
++			   unsigned int *num_buffers, unsigned int *num_planes,
++			   unsigned int sizes[], struct device *alloc_devs[])
++{
++	struct ingenic_i2d_ctx *ctx = vb2_get_drv_priv(vq);
++	struct i2d_frame_info *frame = get_frame(ctx, vq->type);
++
++	if (IS_ERR(frame))
++		return PTR_ERR(frame);
++
++	*num_planes = 1;
++	sizes[0] = frame->size;
++	alloc_devs[0] = ctx->i2d_dev->dev;
++
++	if (*num_buffers == 0)
++		*num_buffers = 1;
++
++	return 0;
++}
++
++static int i2d_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct ingenic_i2d_ctx *ctx = container_of(ctrl->handler, struct ingenic_i2d_ctx,ctrl_handler);
++	unsigned long flags;
++
++	spin_lock_irqsave(&ctx->i2d_dev->ctrl_lock, flags);
++	switch (ctrl->id) {
++	case V4L2_CID_HFLIP:
++		ctx->hflip = ctx->ctrl_hflip->val;
++		break;
++	case V4L2_CID_VFLIP:
++		ctx->vflip = ctx->ctrl_vflip->val;
++		break;
++	case V4L2_CID_ROTATE:
++		ctx->angle = ctx->ctrl_rot->val;
++		break;
++	}
++	spin_unlock_irqrestore(&ctx->i2d_dev->ctrl_lock, flags);
++	return 0;
++}
++
++static const struct v4l2_ctrl_ops i2d_ctrl_ops = {
++	.s_ctrl		= i2d_s_ctrl,
++};
++
++static int i2d_setup_ctrls(struct ingenic_i2d_ctx *ctx)
++{
++	struct ingenic_i2d_dev *dev = ctx->i2d_dev;
++
++	v4l2_ctrl_handler_init(&ctx->ctrl_handler, 3);
++
++	ctx->ctrl_hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &i2d_ctrl_ops,
++						V4L2_CID_HFLIP, 0, 1, 1, 0);
++
++	ctx->ctrl_vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &i2d_ctrl_ops,
++						V4L2_CID_VFLIP, 0, 1, 1, 0);
++	ctx->ctrl_rot = v4l2_ctrl_new_std(&ctx->ctrl_handler, &i2d_ctrl_ops,
++						V4L2_CID_ROTATE, 0, 270, 90, 0);
++
++	if (ctx->ctrl_handler.error) {
++		int err = ctx->ctrl_handler.error;
++		v4l2_err(&dev->v4l2_dev, "rot_setup_ctrls failed\n");
++		v4l2_ctrl_handler_free(&ctx->ctrl_handler);
++		return err;
++	}
++
++	return 0;
++}
++
++static int i2d_buf_prepare(struct vb2_buffer *vb)
++{
++	struct ingenic_i2d_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
++	struct i2d_frame_info *frame = get_frame(ctx, vb->vb2_queue->type);
++
++	if (IS_ERR(frame))
++		return PTR_ERR(frame);
++	vb2_set_plane_payload(vb, 0, frame->size);
++	return 0;
++}
++
++static void i2d_buf_queue(struct vb2_buffer *vb)
++{
++	struct ingenic_i2d_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
++	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
++
++	if (ctx->m2m_ctx)
++		v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
++}
++
++static struct vb2_ops i2d_qops = {
++	.queue_setup	= i2d_queue_setup,
++	.buf_prepare	= i2d_buf_prepare,
++	.buf_queue	= i2d_buf_queue,
++};
++
++static int queue_init(void *priv, struct vb2_queue *src_vq,
++						struct vb2_queue *dst_vq)
++{
++	struct ingenic_i2d_ctx *ctx = priv;
++	int ret;
++
++	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
++	src_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
++	src_vq->drv_priv = ctx;
++	src_vq->ops = &i2d_qops;
++	src_vq->mem_ops = &ingenic_vb2_dma_contig_memops;
++	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
++	src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
++	src_vq->lock = &ctx->i2d_dev->dev_mutex;
++
++	ret = vb2_queue_init(src_vq);
++	if (ret)
++		return ret;
++
++	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++	dst_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
++	dst_vq->drv_priv = ctx;
++	dst_vq->ops = &i2d_qops;
++	dst_vq->mem_ops = &ingenic_vb2_dma_contig_memops;
++	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
++	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
++	dst_vq->lock = &ctx->i2d_dev->dev_mutex;
++
++	return vb2_queue_init(dst_vq);
++}
++
++static void set_default_fmt(struct ingenic_i2d_ctx *ctx)
++{
++	struct i2d_frame_info *cap, *out;
++
++	cap = &ctx->cap_info;
++	out = &ctx->out_info;
++
++	cap->width = DEFAULT_WIDTH;
++	cap->height = DEFAULT_HEIGHT;
++	cap->fmt = &formats[0];
++	cap->bytesperline = DEFAULT_WIDTH * cap->fmt->depth >> 3;
++	cap->size = cap->bytesperline * cap->height;
++
++	out->width = DEFAULT_WIDTH;
++	out->height = DEFAULT_HEIGHT;
++	out->fmt = &formats[0];
++	out->bytesperline = DEFAULT_WIDTH * out->fmt->depth >> 3;
++	out->size = out->bytesperline * out->height;
++}
++
++
++static int i2d_open(struct file *file)
++{
++	struct ingenic_i2d_dev *dev = video_drvdata(file);
++	struct ingenic_i2d_ctx *ctx = NULL;
++	int ret = 0;
++
++	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
++	if (!ctx)
++		return -ENOMEM;
++
++	if (mutex_lock_interruptible(&dev->dev_mutex)) {
++		kfree(ctx);
++		return -ERESTARTSYS;
++	}
++	ctx->i2d_dev = dev;
++
++	/* Set default formats */
++	set_default_fmt(ctx);
++
++	v4l2_fh_init(&ctx->fh, video_devdata(file));
++	ctx->fh.ctrl_handler = &ctx->ctrl_handler;
++	file->private_data = &ctx->fh;
++	v4l2_fh_add(&ctx->fh);
++
++	ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
++	if (IS_ERR(ctx->m2m_ctx)) {
++		ret = PTR_ERR(ctx->m2m_ctx);
++		goto err;
++	}
++	ctx->fh.m2m_ctx = ctx->m2m_ctx;
++
++	ret = i2d_setup_ctrls(ctx);
++	if(ret)
++		goto err;
++
++	/* Write the default values to the ctx struct */
++	v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
++
++	clk_prepare_enable(dev->clk);
++
++	mutex_unlock(&dev->dev_mutex);
++
++	return 0;
++err:
++	v4l2_fh_del(&ctx->fh);
++	v4l2_fh_exit(&ctx->fh);
++	mutex_unlock(&dev->dev_mutex);
++	kfree(ctx);
++	return ret;
++}
++
++static int i2d_release(struct file *file)
++{
++	struct ingenic_i2d_dev *dev = video_drvdata(file);
++	struct ingenic_i2d_ctx *ctx = fh_to_ctx(file->private_data);
++
++	clk_disable_unprepare(dev->clk);
++
++	mutex_lock(&dev->dev_mutex);
++	v4l2_m2m_ctx_release(ctx->m2m_ctx);
++	mutex_unlock(&dev->dev_mutex);
++	v4l2_ctrl_handler_free(&ctx->ctrl_handler);
++	v4l2_fh_del(&ctx->fh);
++	v4l2_fh_exit(&ctx->fh);
++	kfree(ctx);
++	return 0;
++}
++
++static irqreturn_t i2d_irq_handler(int irq, void *prv)
++{
++	struct ingenic_i2d_dev *dev = prv;
++	struct ingenic_i2d_ctx *ctx = dev->cur_ctx;
++	struct vb2_v4l2_buffer *src, *dst;
++
++	unsigned int status = i2d_irq_clear(dev);
++
++	if(unlikely(ctx == NULL)) {
++		printk("I2D:ctx == NULL\n");
++		return IRQ_HANDLED;
++	}
++
++	src = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
++	if(unlikely(src == NULL)) {
++		printk("I2D:src == NULL\n");
++		return IRQ_HANDLED;
++	}
++	dst = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
++	if(unlikely(dst == NULL)) {
++		printk("I2D:dst == NULL\n");
++		return IRQ_HANDLED;
++	}
++
++	/* dst->timecode = src->timecode; */
++	/* dst->timestamp = src->timestamp; */
++
++	v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE);
++	v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
++	v4l2_m2m_job_finish(dev->m2m_dev, ctx->m2m_ctx);
++
++	dev->cur_ctx = NULL;
++	if(status & 0x1)
++		wake_up(&dev->irq_queue);
++	return IRQ_HANDLED;
++}
++
++static void device_run(void *prv)
++{
++	struct ingenic_i2d_ctx *ctx = prv;
++	struct ingenic_i2d_dev *dev = ctx->i2d_dev;
++	struct vb2_v4l2_buffer *src, *dst;
++	unsigned long flags;
++	unsigned int srcaddr,dstaddr;
++	dev->cur_ctx = ctx;
++
++	src = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
++	dst = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
++
++	spin_lock_irqsave(&dev->ctrl_lock, flags);
++
++	/* clk_prepare_enable(dev->clk); */
++	i2d_safe_reset(dev);
++	srcaddr = ingenic_vb2_dma_contig_plane_dma_addr(&src->vb2_buf,0);
++	dstaddr = ingenic_vb2_dma_contig_plane_dma_addr(&dst->vb2_buf,0);
++	i2d_set_init_info(dev, &ctx->out_info,srcaddr,dstaddr);
++	/* do_gettimeofday(&time_now); */
++	i2d_start(dev);
++	spin_unlock_irqrestore(&dev->ctrl_lock, flags);
++}
++
++
++
++#define I2D_TIMEOUT 2000
++static void job_abort(void *prv)
++{
++	struct ingenic_i2d_ctx *ctx = prv;
++	struct ingenic_i2d_dev *dev = ctx->i2d_dev;
++	int ret;
++
++	if (dev->cur_ctx == NULL) /* No job currently running */
++		return;
++
++	ret = wait_event_timeout(dev->irq_queue,dev->cur_ctx == NULL,msecs_to_jiffies(I2D_TIMEOUT));
++	if(!ret) {
++		struct vb2_v4l2_buffer *src_vb, *dst_vb;
++
++		i2d_safe_reset(dev);
++
++		src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
++		dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
++		dst_vb->vb2_buf.timestamp = src_vb->vb2_buf.timestamp;
++		dst_vb->timecode = src_vb->timecode;
++		dst_vb->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
++		dst_vb->flags |=
++			src_vb->flags
++			& V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
++
++		v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_ERROR);
++		v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_ERROR);
++
++		v4l2_m2m_job_finish(dev->m2m_dev,
++				    ctx->m2m_ctx);
++		dev->cur_ctx = NULL;
++		/* clk_disable_unprepare(dev->clk); */
++	} else {
++		printk("I2D : wait_event_timeout %s []%d] >>>>>>>\n",__func__,__LINE__);
++	}
++}
++
++static const struct v4l2_file_operations i2d_fops = {
++	.owner		= THIS_MODULE,
++	.open		= i2d_open,
++	.release	= i2d_release,
++	.poll		= v4l2_m2m_fop_poll,
++	.unlocked_ioctl	= video_ioctl2,
++	.mmap		= v4l2_m2m_fop_mmap,
++};
++
++static const struct v4l2_ioctl_ops i2d_ioctl_ops = {
++	.vidioc_querycap		= vidioc_querycap,
++
++	.vidioc_enum_fmt_vid_cap	= vidioc_enum_fmt_vid_cap,
++	.vidioc_g_fmt_vid_cap		= vidioc_g_fmt,
++	.vidioc_try_fmt_vid_cap		= vidioc_try_fmt,
++	.vidioc_s_fmt_vid_cap		= vidioc_s_fmt,
++
++	.vidioc_enum_fmt_vid_out	= vidioc_enum_fmt_vid_out,
++	.vidioc_g_fmt_vid_out		= vidioc_g_fmt,
++	.vidioc_try_fmt_vid_out		= vidioc_try_fmt,
++	.vidioc_s_fmt_vid_out		= vidioc_s_fmt,
++
++	.vidioc_reqbufs			= v4l2_m2m_ioctl_reqbufs,
++	.vidioc_querybuf		= v4l2_m2m_ioctl_querybuf,
++	.vidioc_qbuf			= v4l2_m2m_ioctl_qbuf,
++	.vidioc_dqbuf			= v4l2_m2m_ioctl_dqbuf,
++	.vidioc_expbuf          = _i2d_vidioc_expbuf,
++
++	.vidioc_streamon		= vidioc_streamon,
++	.vidioc_streamoff		= vidioc_streamoff,
++};
++
++
++static struct video_device i2d_videodev = {
++	.name		= "ingenic-i2d",
++	.fops		= &i2d_fops,
++	.ioctl_ops	= &i2d_ioctl_ops,
++	.minor		= -1,
++	.release	= video_device_release,
++	.vfl_dir	= VFL_DIR_M2M,
++};
++
++static struct v4l2_m2m_ops i2d_m2m_ops = {
++	.device_run	= device_run,
++	.job_abort	= job_abort,
++};
++
++static int ingenic_i2d_probe(struct platform_device *pdev)
++{
++	struct ingenic_i2d_dev *i2d_dev;
++	struct video_device *vfd;
++	struct resource *res;
++	int ret = 0;
++	i2d_dev = devm_kzalloc(&pdev->dev, sizeof(*i2d_dev), GFP_KERNEL);
++	if (!i2d_dev)
++		return -ENOMEM;
++	i2d_dev->dev = &pdev->dev;
++	spin_lock_init(&i2d_dev->irqlock);
++	spin_lock_init(&i2d_dev->ctrl_lock);
++	mutex_init(&i2d_dev->dev_mutex);
++	atomic_set(&i2d_dev->num_inst,0);
++	init_waitqueue_head(&i2d_dev->irq_queue);
++	init_completion(&i2d_dev->done_i2d);
++
++	res = platform_get_resource(pdev,IORESOURCE_MEM,0);
++
++	i2d_dev->base = devm_ioremap_resource(&pdev->dev,res);
++	if(IS_ERR(i2d_dev->base))
++		return PTR_ERR(i2d_dev->base);
++
++	i2d_dev->irq = platform_get_irq(pdev,0);
++	if(i2d_dev->irq < 0){
++		dev_err(&pdev->dev,"get i2d irq num error\n");
++		return i2d_dev->irq;
++	}
++
++	i2d_dev->name = pdev->name;
++
++	ret = devm_request_irq(i2d_dev->dev, i2d_dev->irq, i2d_irq_handler,
++						IRQF_SHARED, i2d_dev->name, i2d_dev);
++	if(ret < 0){
++		dev_err(i2d_dev->dev,"i2d request irq error\n");
++		return ret;
++	}
++	/* i2d_dev->irq_is_request = 0; */
++
++	/* clocks */
++	i2d_dev->clk = clk_get(&pdev->dev, "gate_i2d");
++	if (IS_ERR(i2d_dev->clk)) {
++		dev_err(&pdev->dev, "cannot get clock\n");
++		return PTR_ERR(i2d_dev->clk);
++	}
++	dev_dbg(&pdev->dev, "i2d clock source %p\n", i2d_dev->clk);
++
++
++	i2d_dev->alloc_ctx = ingenic_vb2_dma_contig_init_ctx(&pdev->dev);
++	if (IS_ERR(i2d_dev->alloc_ctx)) {
++		ret = PTR_ERR(i2d_dev->alloc_ctx);
++		goto clk_get_cleanup;
++	}
++	ret = v4l2_device_register(&pdev->dev, &i2d_dev->v4l2_dev);
++	if (ret)
++		goto alloc_ctx_cleanup;
++
++	vfd = &i2d_videodev;
++	vfd->lock = &i2d_dev->dev_mutex;
++	vfd->v4l2_dev = &i2d_dev->v4l2_dev;
++	vfd->device_caps = V4L2_CAP_STREAMING |
++		  V4L2_CAP_VIDEO_M2M;
++
++	ret = video_register_device(vfd, VFL_TYPE_VIDEO, INGENIC_ROTATE_VIDEO_NR);
++	if (ret) {
++		v4l2_err(&i2d_dev->v4l2_dev, "Failed to register video device\n");
++		goto free_video_device;
++	}
++
++	video_set_drvdata(vfd, i2d_dev);
++	snprintf(vfd->name, sizeof(vfd->name), "%s", i2d_videodev.name);
++	i2d_dev->vfd = vfd;
++	v4l2_info(&i2d_dev->v4l2_dev, "device registered as /dev/video%d\n",vfd->num);
++
++	platform_set_drvdata(pdev, i2d_dev);
++	i2d_dev->m2m_dev = v4l2_m2m_init(&i2d_m2m_ops);
++
++	if (IS_ERR(i2d_dev->m2m_dev)) {
++		v4l2_err(&i2d_dev->v4l2_dev, "Failed to init mem2mem device\n");
++		ret = PTR_ERR(i2d_dev->m2m_dev);
++		goto unreg_video_dev;
++	}
++	printk("%s ok >>>>>>>>>>>>>>>>>>>>>>\n",__func__);
++	return 0;
++
++unreg_video_dev:
++	video_unregister_device(vfd);
++free_video_device:
++unreg_v4l2_dev:
++	v4l2_device_unregister(&i2d_dev->v4l2_dev);
++alloc_ctx_cleanup:
++	ingenic_vb2_dma_contig_cleanup_ctx(i2d_dev->alloc_ctx);
++clk_get_cleanup:
++	clk_put(i2d_dev->clk);
++
++	return 0;
++}
++
++static int ingenic_i2d_remove(struct platform_device *pdev)
++{
++	struct ingenic_i2d_dev *dev = (struct ingenic_i2d_dev *)platform_get_drvdata(pdev);
++
++	v4l2_info(&dev->v4l2_dev, "Removing " JZ_I2D_NAME);
++	v4l2_m2m_release(dev->m2m_dev);
++	video_unregister_device(dev->vfd);
++	v4l2_device_unregister(&dev->v4l2_dev);
++	ingenic_vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
++	clk_put(dev->clk);
++	return 0;
++}
++
++
++static const struct of_device_id ingenic_i2d_match[] = {
++	{
++		.compatible = "ingenic,x2500-i2d",
++		.data = NULL,
++	},
++	{ },
++};
++
++MODULE_DEVICE_TABLE(of, ingenic_i2d_match);
++
++
++static struct platform_driver i2d_pdrv = {
++	.probe		= ingenic_i2d_probe,
++	.remove		= ingenic_i2d_remove,
++	.driver		= {
++		.owner = THIS_MODULE,
++		.of_match_table	= of_match_ptr(ingenic_i2d_match),
++		.name = JZ_I2D_NAME,
++		.owner = THIS_MODULE,
++	},
++};
++
++module_platform_driver(i2d_pdrv);
++
++MODULE_DESCRIPTION("X2500 i2d driver");
++MODULE_LICENSE("GPL");
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-i2d/i2d_video.h b/module_drivers/drivers/media/platform/ingenic-i2d/i2d_video.h
+new file mode 100644
+index 000000000..912219abb
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-i2d/i2d_video.h
+@@ -0,0 +1,75 @@
++#ifndef __I2D_VIDEO_H__
++#define __I2D_VIDEO_H__
++
++#include <linux/platform_device.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++
++#define MAX_WIDTH	3840
++#define MAX_HEIGHT	2160
++#define MIN_WIDTH	0
++#define	MIN_HEIGHT	0
++
++#define DEFAULT_WIDTH 640
++#define DEFAULT_HEIGHT 480
++
++
++#define MEM2MEM_CAPTURE	(1 << 0)
++#define MEM2MEM_OUTPUT	(1 << 1)
++
++struct i2d_fmt {
++	char	*name;
++	u32	fourcc;
++	int	depth;
++	u32	types;
++};
++
++struct i2d_frame_info{
++	uint16_t width;
++	uint16_t height;
++	struct i2d_fmt *fmt;
++	uint32_t	size;
++	uint32_t	bytesperline;
++};
++
++struct ingenic_i2d_dev {
++	char* name;
++	struct device *dev;
++	struct v4l2_device	v4l2_dev;
++	struct v4l2_m2m_dev	*m2m_dev;
++	struct video_device	*vfd;
++	atomic_t			num_inst;
++	struct mutex		dev_mutex;
++	spinlock_t			irqlock;
++	spinlock_t			ctrl_lock;
++	void __iomem		*base;
++	struct clk			*clk;
++	int irq;
++	int irq_is_request;
++	wait_queue_head_t	irq_queue;
++	void*	*alloc_ctx;
++	struct ingenic_i2d_ctx	*cur_ctx;
++	struct completion done_i2d;
++};
++
++struct ingenic_i2d_ctx {
++	struct v4l2_fh		fh;
++	struct ingenic_i2d_dev	*i2d_dev;
++	struct v4l2_m2m_ctx	*m2m_ctx;
++	struct v4l2_ctrl_handler ctrl_handler;
++	struct v4l2_ctrl	*ctrl_hflip;
++	struct v4l2_ctrl	*ctrl_vflip;
++	struct v4l2_ctrl	*ctrl_rot;
++	struct i2d_frame_info	cap_info;
++	struct i2d_frame_info	out_info;
++	uint32_t			vflip;
++	uint32_t			hflip;
++	uint32_t			angle;
++	dma_addr_t			paddr;
++};
++
++
++
++#endif		// __I2D_VIDEO_H__
++
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-i2d/ingenic_i2d.c b/module_drivers/drivers/media/platform/ingenic-i2d/ingenic_i2d.c
+new file mode 100644
+index 000000000..9571f4799
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-i2d/ingenic_i2d.c
+@@ -0,0 +1,252 @@
++#include <linux/io.h>
++#include <linux/delay.h>
++
++#include "i2d_video.h"
++#include "ingenic_i2d.h"
++
++
++
++static void reg_bit_set(struct ingenic_i2d_dev* dev,int offset,int bit)
++{
++	unsigned int val = 0;
++	val = reg_read(dev,offset);
++	val |= bit;
++	reg_write(dev,offset,val);
++}
++
++static void reg_bit_clr(struct ingenic_i2d_dev *dev,int offset, int bit)
++{
++	unsigned int val = 0;
++	val = reg_read(dev,offset);
++	val &= ~ (bit);
++	reg_write(dev,offset,val);
++}
++
++void i2d_safe_reset(struct ingenic_i2d_dev *dev)
++{
++	reg_bit_set(dev,I2D_CTRL,I2D_SAFE_RESET);
++}
++
++void i2d_reset(struct ingenic_i2d_dev *dev)
++{
++	reg_bit_set(dev,I2D_CTRL,I2D_RESET);
++}
++
++static int i2d_reg_set(struct ingenic_i2d_dev *i2d, struct i2d_param *i2d_param)
++{
++    unsigned int fmt = 0;
++    unsigned int srcw = 0;
++    unsigned int srch = 0;
++    unsigned int flip_enable = 0, mirr_enable = 0, rotate_angle = 0, rotate_enable = 0;
++    unsigned int flip_mode = 0;
++    unsigned int value = 0;
++
++	unsigned int src_y_pbuf = 0;
++	unsigned int src_uv_pbuf = 0;
++    unsigned int dst_y_pbuf = 0;
++    unsigned int dst_uv_pbuf = 0;
++
++    unsigned int src_y_strid = 0;
++	unsigned int src_uv_strid = 0;
++    unsigned int dst_y_strid = 0;
++    unsigned int dst_uv_strid = 0;
++
++    struct i2d_param *ip = i2d_param;
++    if (i2d == NULL) {
++		dev_err(i2d->dev, "i2d: i2d is NULL or i2d_param is NULL\n");
++		return -1;
++	}
++
++    fmt = ip->data_type;
++    srcw = ip->src_w;
++    srch = ip->src_h;
++    flip_enable = ip->flip_enable;
++    mirr_enable = ip->mirr_enable;
++    rotate_enable = ip->rotate_enable;
++    rotate_angle = ip->rotate_angle;
++
++    switch(fmt) {
++        case V4L2_PIX_FMT_NV12:
++            src_y_strid  = srcw;
++            src_uv_strid = srcw;
++            if ((rotate_angle == 0) || (rotate_angle == 180) || (flip_enable == 1) || (mirr_enable == 1)) {
++                dst_y_strid = srcw;
++                dst_uv_strid = srcw;
++            } else if ((rotate_angle == 90) || (rotate_angle == 270)) {
++                dst_y_strid = srch;
++                dst_uv_strid = srch;
++            }
++            reg_write(i2d, I2D_IMG_MODE, I2D_DATA_TYPE_NV12);
++            break;
++        case V4L2_PIX_FMT_SBGGR8:
++            src_y_strid = srcw;
++            src_uv_strid = srcw;
++            if ((rotate_angle == 0) || (rotate_angle == 180) || (flip_enable == 1) || (mirr_enable == 1)) {
++                dst_y_strid = srcw;
++                dst_uv_strid = srcw;
++            } else if ((rotate_angle == 90) || (rotate_angle == 270)) {
++                dst_y_strid = srch;
++                dst_uv_strid = srch;
++            }
++            reg_write(i2d, I2D_IMG_MODE, I2D_DATA_TYPE_RAW8);
++            break;
++        case V4L2_PIX_FMT_RGB565:
++            src_y_strid = srcw << 1;
++            src_uv_strid = srcw;
++            if ((rotate_angle == 0) || (rotate_angle == 180) || (flip_enable == 1) || (mirr_enable == 1)) {
++                dst_y_strid = srcw << 1;
++                dst_uv_strid = srcw;
++            } else if ((rotate_angle == 90) || (rotate_angle == 270)) {
++                dst_y_strid = srch << 1;
++                dst_uv_strid = srch;
++            }
++            reg_write(i2d, I2D_IMG_MODE, I2D_DATA_TYPE_RGB565);
++            break;
++        case V4L2_PIX_FMT_ARGB32:
++            src_y_strid = srcw << 2;
++            src_uv_strid = srcw;
++            if ((rotate_angle == 0) || (rotate_angle == 180) || (flip_enable == 1) || (mirr_enable == 1)) {
++                dst_y_strid = srcw << 2;
++                dst_uv_strid = srcw;
++            } else if ((rotate_angle == 90) || (rotate_angle == 270)) {
++                dst_y_strid = srch << 2;
++                dst_uv_strid = srch;
++            }
++            reg_write(i2d, I2D_IMG_MODE, I2D_DATA_TYPE_ARGB8888);
++            break;
++        default:
++            src_y_strid  = srcw;
++            src_uv_strid = srcw;
++            if ((rotate_angle == 0) || (rotate_angle == 180) || (flip_enable == 1) || (mirr_enable == 1)) {
++                dst_y_strid = srcw;
++                dst_uv_strid = srcw;
++            } else if ((rotate_angle == 90) || (rotate_angle == 270)) {
++                dst_y_strid = srch;
++                dst_uv_strid = srch;
++            }
++			printk("not support fmt ,set default nv12");
++            reg_write(i2d, I2D_IMG_MODE, I2D_DATA_TYPE_NV12);
++            break;
++    }
++
++
++#ifdef TIMEOUT_TEST
++    reg_write(i2d, I2D_TIMEOUT_MODE, (0 << 0)); //timeout mode 0:not restart  1:auto restart
++    reg_write(i2d, I2D_TIMEOUT_VALUE, (0x64 << 0)); //timeout value
++#endif
++    reg_write(i2d, I2D_IMG_SIZE, (srcw << I2D_WIDTH | srch << I2D_HEIGHT));
++   // reg_write(i2d, I2D_IMG_MODE, I2D_DATA_TYPE_NV12);
++    reg_write(i2d, I2D_IMG_SIZE, (srcw << I2D_WIDTH | srch << I2D_HEIGHT));
++    //reg_write(i2d, I2D_IMG_MODE, I2D_FLIP_MODE_90);
++
++    if(rotate_enable == 1) {
++        unsigned int value = 0, tmp1 = 0;
++		if(rotate_angle == 0){
++			tmp1 = 0;
++			dst_uv_pbuf = ip->dst_addr_y + dst_y_strid*srch;
++		} else if(rotate_angle == 90){
++			tmp1 = 1;
++			dst_uv_pbuf = ip->dst_addr_y + dst_y_strid*srcw;
++		} else if(rotate_angle == 180){
++			tmp1 = 2;
++			dst_uv_pbuf = ip->dst_addr_y + dst_y_strid*srch;
++		} else if(rotate_angle == 270){
++			tmp1 = 3;
++			dst_uv_pbuf = ip->dst_addr_y + dst_y_strid*srcw;
++		} else {
++			tmp1 = 0;
++            dst_uv_pbuf = ip->dst_addr_y + dst_y_strid*srch;
++		}
++		/* set rotate angle  */
++		value = reg_read(i2d,I2D_IMG_MODE);
++		value &= ~(3 << 2);
++		value |= (tmp1 << 2);
++		reg_write(i2d,I2D_IMG_MODE,value);
++	}
++
++     if(mirr_enable == 1) {
++        dst_uv_pbuf = ip->dst_addr_y + dst_y_strid*srch;
++        value = reg_read(i2d, I2D_IMG_MODE);
++        reg_write(i2d, I2D_IMG_MODE, (value | I2D_MIRR));
++    }
++
++    if(flip_enable == 1) {
++        dst_uv_pbuf = ip->dst_addr_y + dst_y_strid*srch;
++        value = reg_read(i2d, I2D_IMG_MODE);
++        reg_write(i2d, I2D_IMG_MODE, (value | I2D_FLIP));
++    }
++
++
++
++    src_y_pbuf = ip->src_addr_y;
++    src_uv_pbuf = ip->src_addr_y + src_y_strid*srch;
++    dst_y_pbuf = ip->dst_addr_y;
++
++    reg_write(i2d, I2D_SRC_ADDR_Y, src_y_pbuf);
++    reg_write(i2d, I2D_SRC_ADDR_UV, src_uv_pbuf);
++    reg_write(i2d, I2D_DST_ADDR_Y, dst_y_pbuf);
++    reg_write(i2d, I2D_DST_ADDR_UV, dst_uv_pbuf);
++
++
++    reg_write(i2d, I2D_SRC_Y_STRID, src_y_strid);
++    reg_write(i2d, I2D_SRC_UV_STRID, src_uv_strid);
++    reg_write(i2d, I2D_DST_Y_STRID, dst_y_strid);
++    reg_write(i2d, I2D_DST_UV_STRID, dst_uv_strid);
++
++
++    return 0;
++}
++
++int i2d_set_init_info(struct ingenic_i2d_dev *dev,struct i2d_frame_info *info,dma_addr_t src_addr,dma_addr_t dst_addr)
++{
++	struct ingenic_i2d_ctx *ctx;
++	struct i2d_param param;
++	ctx = dev->cur_ctx;
++	param.src_w = info->width;
++	param.src_h = info->height;
++	param.data_type = info->fmt->fourcc;
++	param.rotate_enable = 1;
++	param.rotate_angle = ctx->angle;
++	param.flip_enable = ctx->vflip;
++	param.mirr_enable = ctx->hflip;
++	param.src_addr_y = src_addr;
++	param.dst_addr_y = dst_addr;
++	return i2d_reg_set(dev,&param);
++}
++
++#if 0
++int i2d_set_angle(ingenic_i2d_dev* dev, uint32_t angle)
++{
++
++}
++
++int i2d_set_vflip(ingenic_i2d_dev* dev, uint32_t vflip)
++{
++
++}
++
++int i2d_set_hflip(ingenic_i2d_dev* dev, uint32_t hflip)
++{
++
++}
++#endif
++
++int i2d_start(struct ingenic_i2d_dev *dev)
++{
++	reg_bit_set(dev, I2D_IRQ_MASK, (I2D_IRQ_TIMEOUT_MASK | I2D_IRQ_FRAME_DONE_MASK));	// mask 0
++	reg_write(dev,I2D_SHD_CTRL,0xffffffff);
++	reg_bit_set(dev, I2D_CTRL, I2D_START);
++	return 0;
++}
++
++
++int i2d_irq_clear(struct ingenic_i2d_dev *dev)
++{
++	unsigned int status;
++	status = reg_read(dev,I2D_IRQ_STATE);
++	reg_bit_set(dev,I2D_IRQ_CLEAR,status);
++	/* if (status & 0x1){ */
++	/*     complete(&dev->done_i2d); */
++	/* } */
++	return status;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-i2d/ingenic_i2d.h b/module_drivers/drivers/media/platform/ingenic-i2d/ingenic_i2d.h
+new file mode 100644
+index 000000000..3dad61722
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-i2d/ingenic_i2d.h
+@@ -0,0 +1,157 @@
++#ifndef __I2D_H__
++#define __I2D_H__
++
++#define I2D_BASE	0xB30B0000
++
++#define I2D_RTL_VERSION	        0x00
++#define I2D_SHD_CTRL        0x08
++#define I2D_CTRL	        0x10
++#define I2D_IMG_SIZE	    0x14
++#define I2D_IMG_MODE	    0x18
++#define I2D_SRC_ADDR_Y	    0x20
++#define I2D_SRC_ADDR_UV	    0x24
++#define I2D_SRC_Y_STRID	    0x28
++#define I2D_SRC_UV_STRID	0x2C
++#define I2D_DST_ADDR_Y	    0x30
++#define I2D_DST_ADDR_UV	    0x34
++#define I2D_DST_Y_STRID	    0x38
++#define I2D_DST_UV_STRID	0x3C
++#define I2D_IRQ_STATE	    0x80
++#define I2D_IRQ_CLEAR	    0x84
++#define I2D_IRQ_MASK	    0x88
++#define I2D_TIMEOUT_VALUE	0x90
++#define I2D_TIMEOUT_MODE	0x94
++#define I2D_CLK_GATE	    0x98
++#define I2D_DBG_0	        0xA0
++
++#define u32 unsigned int
++
++/* VERSION*/
++#define I2D_VERSION (1 << 0)
++
++/* SHD_CTRL */
++#define I2D_MODE_SHADOW (1 << 1)
++
++/* SHD_CTRL */
++#define I2D_MODE_SHADOW (1 << 1)
++#define I2D_ADDR_SHADOW (1 << 0)
++
++/* CTRL */
++#define I2D_RESET       (1 << 16)
++#define I2D_SAFE_RESET  (1 << 4)
++#define I2D_START       (1 << 0)
++
++/* IMG_SIZE */
++#define I2D_WIDTH       (16)
++#define I2D_HEIGHT      (0)
++
++/* I2D_MODE */
++#define I2D_DATA_TYPE            (4)
++#define I2D_DATA_TYPE_NV12       (0 << I2D_DATA_TYPE)
++#define I2D_DATA_TYPE_RAW8       (1 << I2D_DATA_TYPE)
++#define I2D_DATA_TYPE_RGB565     (2 << I2D_DATA_TYPE)
++#define I2D_DATA_TYPE_ARGB8888   (3 << I2D_DATA_TYPE)
++
++#define I2D_FLIP_MODE            (2)
++#define I2D_FLIP_MODE_0          (0 << I2D_FLIP_MODE)
++#define I2D_FLIP_MODE_90         (1 << I2D_FLIP_MODE)
++#define I2D_FLIP_MODE_180        (2 << I2D_FLIP_MODE)
++#define I2D_FLIP_MODE_270        (3 << I2D_FLIP_MODE)
++
++#define I2D_MIRR        (1 << 1)
++#define I2D_FLIP        (1 << 0)
++
++/* SRC_ADDR_Y */
++#define I2D_SRC_Y       (0)
++
++/* SRC_ADDR_UV */
++#define I2D_SRC_UV      (0)
++
++/* SRC_Y_STRID */
++#define I2D_SRC_STRID_Y       (0)
++
++/* SRC_UV_STRID */
++#define I2D_SRC_STRID_UV      (0)
++
++/* DST_ADDR_Y */
++#define I2D_DST_Y       (0)
++
++/* DST_ADDR_UV */
++#define I2D_DST_UV      (0)
++
++/* DST_Y_STRID */
++#define I2D_DST_STRID_Y       (0)
++
++/* DST_UV_STRID */
++#define I2D_DST_STRID_UV      (0)
++
++/* IRQ_STATE */
++#define I2D_IRQ_TIMEOUT       (1)
++#define I2D_IRQ_FRAME_DONE    (0)
++
++/* IRQ_CLEAR */
++#define I2D_IRQ_TIMEOUT_CLR       (1 << 1)
++#define I2D_IRQ_FRAME_DONE_CLR    (1 << 0)
++
++/* IRQ_MASK */
++#define I2D_IRQ_TIMEOUT_MASK       (0 << 1)
++#define I2D_IRQ_FRAME_DONE_MASK    (0 << 0)
++
++/* TIMEOUT_MODE */
++#define I2D_TIMEOUT_RST       (0)
++
++enum                          
++{
++    FLIP_MODE_0_DEGREE   = 1,
++    FLIP_MODE_90_DEGREE  = 2,
++    FLIP_MODE_180_DEGREE = 3,
++    FLIP_MODE_270_DEGREE = 4,
++    FLIP_MODE_MIRR       = 5,
++    FLIP_MODE_FLIP       = 6,
++};
++
++
++struct i2d_param
++{
++    unsigned int        src_w;
++    unsigned int        src_h;
++    unsigned int        data_type;
++    unsigned int        rotate_enable;
++    unsigned int        rotate_angle;
++    unsigned int        flip_enable;
++    unsigned int        mirr_enable;
++
++    unsigned int        src_addr_y;
++    unsigned int        src_addr_uv;
++    unsigned int        dst_addr_y;
++    unsigned int        dst_addr_uv;
++
++    unsigned int        src_y_strid;
++    unsigned int        src_uv_strid;
++    unsigned int        dst_y_strid;
++    unsigned int        dst_uv_strid;
++};
++
++static inline unsigned int reg_read(struct ingenic_i2d_dev *dev,int offset)
++{
++	return readl(dev->base + offset);
++}
++
++static inline void reg_write(struct ingenic_i2d_dev *dev,int offset, unsigned int val)
++{
++	writel(val, dev->base + offset);
++}
++
++void i2d_safe_reset(struct ingenic_i2d_dev *dev);
++
++void i2d_reset(struct ingenic_i2d_dev *dev);
++
++int i2d_set_init_info(struct ingenic_i2d_dev *dev,struct i2d_frame_info *info,dma_addr_t src_addr,dma_addr_t dst_addr);
++
++int i2d_start(struct ingenic_i2d_dev *dev);
++
++int i2d_irq_clear(struct ingenic_i2d_dev *dev);
++#endif		// __I2D_H__
++
++
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/Kconfig b/module_drivers/drivers/media/platform/ingenic-isp-v2/Kconfig
+new file mode 100644
+index 000000000..bc235d500
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/Kconfig
+@@ -0,0 +1,56 @@
++choice
++	prompt "isp total sensor num select"
++	depends on VIDEO_INGENIC_ISP_V2
++	default INGENIC_ISP_V2_SENSOR_NUM_TWO
++	help
++	Select isp total sensor number.
++config INGENIC_ISP_V2_SENSOR_NUM_ONE
++	bool "isp total sensor num one"
++config INGENIC_ISP_V2_SENSOR_NUM_TWO
++	bool "isp total sensor num two"
++config INGENIC_ISP_V2_SENSOR_NUM_THREE
++	bool "isp total sensor num three"
++endchoice
++
++
++menuconfig HIPPO_CAMERA_BOARD
++	bool "hippo_camera_board"
++	depends on VIDEO_INGENIC_ISP_V2
++	default n
++	help
++		Say Y here to enable support for hippo_camera_boards.
++
++
++config RD_X2500_HIPPO_CAMERA_1V0
++	bool "X2500 isp camera driver for RD_X2500_HIPPO_CAMERA_1V0"
++	depends on HIPPO_CAMERA_BOARD
++	select INGENIC_ISP_V2_CAMERA_SC230AI
++	select INGENIC_ISP_V2_CAMERA_GC2155
++
++config RD_X2500_HIPPO_CAMERA_1V1
++	bool "X2500 isp camera driver for RD_X2500_HIPPO_CAMERA_1V1"
++	depends on HIPPO_CAMERA_BOARD
++	select INGENIC_ISP_V2_CAMERA_SC230AI
++
++config RD_X2000_HALLEY5_CAMERA_3V2
++	bool "X2500 isp camera driver for RD_X2000_HALLEY5_CAMERA_3V2"
++	depends on HIPPO_CAMERA_BOARD
++	select INGENIC_ISP_V2_CAMERA_OV4689
++
++config RD_X2000_HALLEY5_CAMERA_4V3
++	bool "X2500 isp camera driver for RD_X2000_HALLEY5_CAMERA_4V3"
++	depends on HIPPO_CAMERA_BOARD
++	select INGENIC_ISP_V2_CAMERA_OV2735A
++
++
++config VIC_DMA_ROUTE
++	bool "vic dma out route enable"
++	default n
++	depends on VIDEO_INGENIC_ISP_V2
++
++config MSCA_BDEV
++	bool "mscaler bdev support"
++	default n
++	depends on VIDEO_INGENIC_ISP_V2
++
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/Makefile b/module_drivers/drivers/media/platform/ingenic-isp-v2/Makefile
+new file mode 100644
+index 000000000..0f8f900b4
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/Makefile
+@@ -0,0 +1,20 @@
++obj-y	+= isp-drv.o
++obj-y	+= csi.o
++obj-y	+= mscaler.o
++obj-y	+= vic.o
++obj-y	+= isp.o
++obj-y	+= sensor.o
++obj-y	+= isp-video.o
++obj-y	+= isp-core-tuning.o
++obj-$(CONFIG_MSCA_BDEV)	+= mscaler-bdev.o
++
++ccflags-y += -I$(srctree)/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/inc
++ccflags-$(CONFIG_MSCA_BDEV) += -I$(srctree)/module_drivers/drivers/media/platform/ingenic-vcodec/helix
++obj-y	+= isp-core/
++
++FILE=$(srctree)/module_drivers/drivers/media/platform/ingenic-isp/isp-core/isp-core.a_shipped
++ifeq ($(FILE), $(wildcard $(FILE)))
++$(error "please remove overlay isp-core.a_shipped")
++endif
++
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/csi-regs.h b/module_drivers/drivers/media/platform/ingenic-isp-v2/csi-regs.h
+new file mode 100644
+index 000000000..c0348374c
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/csi-regs.h
+@@ -0,0 +1,69 @@
++#ifndef __INGENIC_ISP_CSI_H__
++#define __INGENIC_ISP_CSI_H__
++
++#define VERSION				0x00
++#define N_LANES				0x04
++#define PHY_SHUTDOWNZ			0x08
++#define DPHY_RSTZ			0x0C
++#define CSI2_RESETN			0x10
++#define PHY_STATE			0x14
++#define DATA_IDS_1			0x18
++#define DATA_IDS_2			0x1C
++#define ERR1				0x20
++#define ERR2				0x24
++#define MASK1				0x28
++#define MASK2				0x2C
++#define PHY_TST_CTRL0       		0x30
++#define PHY_TST_CTRL1       		0x34
++#define CTRL_DUAL_ENABLE                        0x080
++#define RXVALID_MASK                            0x100
++
++
++#define VC0_FRAME_NUM			0x40	/*[31:16] FS End, [15:0] FS Start*/
++#define VC1_FRAME_NUM			0x44
++#define VC2_FRAME_NUM			0x48
++#define VC3_FRAME_NUM			0x4c
++#define VC0_LINE_NUM			0x50	/*[31:16] Line End, [15:0] Line Start*/
++#define VC1_LINE_NUM			0x54
++#define VC2_LINE_NUM			0x58
++#define VC3_LINE_NUM			0x60
++
++
++
++#define csi_readl(port, reg)						\
++	__raw_readl((unsigned int *)((port)->base + reg))
++#define csi_writel(port, reg, value)					\
++	__raw_writel((value), (unsigned int *)((port)->base + reg))
++
++#define csi_core_writel(csi, addr, value)				\
++	writel(value, (unsigned int *)((csi)->iobase + addr))
++#define csi_core_readl(csi, addr)					\
++	readl((unsigned int *)((csi)->iobase + addr))
++
++
++#define CSI_PHY_IOBASE	0x10022000
++
++#define PHY_ENB				0x000
++#define PHY_DUAL_CLK_ENB		0x080
++#define PHY_CK0_CONTI			0x128
++#define PHY_CK0_SETTLE			0x160
++#define PHY_DATA0_CONTI			0x1A8
++#define PHY_DATA0_SETTLE		0x1E0
++#define PHY_DATA1_CONTI			0x228
++#define PHY_DATA1_SETTLE		0x260
++#define PHY_DATA2_CONTI			0x2A8
++#define PHY_DATA2_SETTLE		0x2E0
++#define PHY_DATA3_CONTI			0x328
++#define PHY_DATA3_SETTLE		0x360
++#define PHY_CK1_CONTI			0x3A8
++#define PHY_CK1_SETTLE			0x3E0
++
++
++#define csi_phy_writel(csi, addr, value)					\
++	writel(value, (unsigned int *)((csi)->phy_base + addr))
++
++#define csi_phy_readl(csi, addr)						\
++       	readl((unsigned int *)((csi)->phy_base + addr))
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/csi.c b/module_drivers/drivers/media/platform/ingenic-isp-v2/csi.c
+new file mode 100644
+index 000000000..b11ec63bd
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/csi.c
+@@ -0,0 +1,554 @@
++#include <linux/clk.h>
++#include <linux/media-bus-format.h>
++#include <linux/media.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_graph.h>
++#include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
++#include <linux/pm_domain.h>
++#include <linux/slab.h>
++#include <linux/videodev2.h>
++#include <linux/component.h>
++
++#include <media/media-device.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-event.h>
++
++
++#include "isp-drv.h"
++#include "csi-regs.h"
++
++static const struct v4l2_subdev_core_ops csi_subdev_core_ops = {
++        .log_status = v4l2_ctrl_subdev_log_status,
++        .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
++        .unsubscribe_event = v4l2_event_subdev_unsubscribe,
++};
++
++int rx_settle_time = 0;
++module_param(rx_settle_time, int, 0664);
++MODULE_PARM_DESC(rx_settle_time, "csi rx-settle counter");
++
++static int csi_subdev_set_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct csi_device *csi = v4l2_get_subdevdata(sd);
++	struct media_pad *remote = NULL;
++	struct v4l2_subdev *remote_sd = NULL;
++	int ret = 0;
++
++	remote = media_entity_remote_pad(&csi->pads[CSI_PAD_SINK]);
++	remote_sd = media_entity_to_v4l2_subdev(remote->entity);
++
++	ret = v4l2_subdev_call(remote_sd, pad, set_fmt, NULL, format);
++	if(ret < 0) {
++		dev_dbg(csi->dev, "Failed to set_fmt from remote pad\n");
++	}
++
++	return 0;
++}
++static int csi_subdev_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct csi_device *csi = v4l2_get_subdevdata(sd);
++	struct media_pad *remote = NULL;
++	struct v4l2_subdev *remote_sd = NULL;
++	struct v4l2_subdev_format remote_subdev_fmt;
++	int ret = 0;
++
++	remote = media_entity_remote_pad(&csi->pads[CSI_PAD_SINK]);
++	remote_sd = media_entity_to_v4l2_subdev(remote->entity);
++
++	/*获��当�格�，�制到输出格�.*/
++	remote_subdev_fmt.pad = remote->index;
++	remote_subdev_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	ret = v4l2_subdev_call(remote_sd, pad, get_fmt, NULL, &remote_subdev_fmt);
++	if(ret < 0) {
++		dev_err(csi->dev, "Failed to get_fmt from remote pad\n");
++		return -EINVAL;
++	}
++
++	memcpy(&format->format, &remote_subdev_fmt.format, sizeof(format->format));
++
++	csi->formats[CSI_PAD_SINK] = csi->formats[CSI_PAD_SOURCE] = *format;
++	csi->sensor_info = (struct sensor_info *)*(unsigned int *)format->format.reserved;
++	//printk("----%s, %d, format->pad: %d\n", __func__, __LINE__, format->pad);
++	return 0;
++}
++
++
++static const struct v4l2_subdev_pad_ops csi_subdev_pad_ops = {
++        .set_fmt                = csi_subdev_set_fmt,
++        .get_fmt                = csi_subdev_get_fmt,
++	/*
++        .init_cfg               = csi_subdev_init_cfg,
++        .enum_mbus_code         = csi_subdev_enum_mbus_code,
++        .enum_frame_size        = csi_subdev_enum_frame_size,
++        .get_fmt                = csi_subdev_get_fmt,
++	*/
++};
++
++struct phy_reseter {
++	struct csi_device *csi[2];
++	unsigned int phy_started[2];
++};
++
++struct phy_reseter global_phy_reseter = {
++	.csi = {NULL, NULL},
++	.phy_started = {0, 0}
++};
++
++DEFINE_SPINLOCK(reset_lock);
++
++static unsigned char csi_core_write_part(struct csi_device *csi,unsigned int address,
++                                                unsigned int data, unsigned char shift, unsigned char width)
++{
++        unsigned int mask = (1 << width) - 1;
++        unsigned int temp = csi_core_readl(csi, address);
++
++        temp &= ~(mask << shift);
++        temp |= (data & mask) << shift;
++        csi_core_writel(csi, address, temp);
++
++        return 0;
++}
++
++static inline int csi_core_write_io(unsigned int iobase, unsigned int address, unsigned int data, unsigned char shift, unsigned char width)
++{
++        unsigned int mask = (1 << width) - 1;
++        unsigned int temp = readl((unsigned int *)(iobase + address));
++
++        temp &= ~(mask << shift);
++        temp |= (data & mask) << shift;
++        writel(temp, (unsigned int *)(iobase + address));
++	return 0;
++}
++
++
++#define CSI0_IOBASE	0xb0054000
++#define CSI1_IOBASE	0xb0023000
++static int csi_phy_start(struct csi_device *csi, struct phy_reseter *reseter)
++{
++	unsigned long flags;
++	/*already reseted.*/
++	spin_lock_irqsave(&reset_lock, flags);
++	if(reseter->phy_started[0] || reseter->phy_started[1]) {
++		reseter->phy_started[csi->reset_index] = 1;
++		spin_unlock_irqrestore(&reset_lock, flags);
++		return 0;
++	}
++
++	/* CSI0 and CSI1 reset both at CSI0. */
++	csi_core_write_io(CSI0_IOBASE, DPHY_RSTZ, 0, 0, 1);
++	csi_core_write_io(CSI0_IOBASE, DPHY_RSTZ, 1, 0, 1);
++
++	reseter->phy_started[csi->reset_index] = 1;
++	spin_unlock_irqrestore(&reset_lock, flags);
++
++
++	return 0;
++}
++
++static void csi_phy_stop(struct csi_device *csi, struct phy_reseter *reseter)
++{
++
++	unsigned long flags;
++
++	/* CSI2_RESET */
++	spin_lock_irqsave(&reset_lock, flags);
++	csi_core_write_part(csi, CSI2_RESETN, 0, 0, 1);
++
++	reseter->phy_started[csi->reset_index] = 0;
++
++	if((reseter->phy_started[0] == 0) && (reseter->phy_started[1] == 0)) {
++		/* shutdown phy. */
++		csi_core_write_io(CSI0_IOBASE, DPHY_RSTZ, 0, 0, 1);
++	}
++
++	spin_unlock_irqrestore(&reset_lock, flags);
++}
++
++
++static unsigned int settle_time_cal(unsigned int clk)
++{
++	unsigned int settle_time = 0;
++
++	if(clk >= 80 && clk < 110)
++		settle_time = 0x2;
++	else if(clk >= 110 && clk < 150)
++		settle_time = 0x3;
++	else if(clk >= 150 && clk < 300)
++		settle_time = 0x6;
++	else if(clk >= 300 && clk < 400)
++		settle_time = 0x8;
++	else if(clk >= 400 && clk < 500)
++		settle_time = 0xb;
++	else if(clk >= 500 && clk < 600)
++		settle_time = 0xe;
++	else if(clk >= 600 && clk < 700)
++		settle_time = 0x10;
++	else if(clk >= 700 && clk < 800)
++		settle_time = 0x12;
++	else if(clk >= 800 && clk < 1000)
++		settle_time = 0x16;
++	else if(clk >= 1000 && clk < 1200)
++		settle_time = 0x1e;
++	else if(clk >= 1200 && clk < 1400)
++		settle_time = 0x23;
++	else if(clk >= 1400 && clk < 1600)
++		settle_time = 0x2d;
++	else if(clk >= 1600 && clk < 1800)
++		settle_time = 0x32;
++	else if(clk >= 1800 && clk < 2000)
++		settle_time = 0x37;
++	else if(clk >= 2000 && clk < 2400)
++		settle_time = 0x3c;
++	else
++		settle_time = 0x3c;
++
++	return settle_time;
++}
++
++
++static int csi_subdev_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct csi_device *csi = v4l2_get_subdevdata(sd);
++	struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2 = ispcam_get_bus_mipi_csi2(csi->ispcam);
++	struct mipi_cfg *mipi_cfg = &csi->sensor_info->mipi_cfg;
++	unsigned short nlanes = mipi_csi2->num_data_lanes;
++	int conti = 0;
++
++	if(enable) {
++		if(csi->enabled++ > 0) {
++			return 0;
++		}
++
++		csi_phy_start(csi, &global_phy_reseter);
++
++		if(nlanes > 2){
++			csi_core_writel(csi,CTRL_DUAL_ENABLE, 0x0);	/*1c mode*/
++			csi_phy_writel(csi, PHY_DUAL_CLK_ENB, 0x1f);
++		} else {
++			csi_core_writel(csi,CTRL_DUAL_ENABLE, 0x1);	/*2c mode*/
++			csi_phy_writel(csi, PHY_DUAL_CLK_ENB, 0x5f);
++		}
++		csi_core_writel(csi, N_LANES, nlanes - 1);
++
++		if(csi->iobase == (unsigned int *)0xb0054000)
++			conti = 0x3f;
++		else
++			conti = 0x0f;
++		csi_phy_writel(csi, PHY_CK0_CONTI, conti);
++		csi_phy_writel(csi, PHY_DATA0_CONTI, conti);
++		csi_phy_writel(csi, PHY_DATA1_CONTI, conti);
++		csi_phy_writel(csi, PHY_DATA2_CONTI, conti);
++		csi_phy_writel(csi, PHY_DATA3_CONTI, conti);
++		csi_phy_writel(csi, PHY_CK1_CONTI, conti);
++
++		csi->settle_time = settle_time_cal(mipi_cfg->clk);
++
++		if(rx_settle_time) {
++			printk("debug rx_settle_time: %d\n", rx_settle_time);
++			csi->settle_time = rx_settle_time;
++		}
++
++		if((!csi->settle_time) && (!mipi_cfg->clk)) {
++			printk("[Error], mipi_cfg->clk is invalid, using incorrect mipi rx_settle_time, **** check ****\n");
++		}
++
++		csi_phy_writel(csi, PHY_CK0_SETTLE, csi->settle_time);
++		csi_phy_writel(csi, PHY_DATA0_SETTLE, csi->settle_time);
++		csi_phy_writel(csi, PHY_DATA1_SETTLE, csi->settle_time);
++		csi_phy_writel(csi, PHY_DATA2_SETTLE, csi->settle_time);
++		csi_phy_writel(csi, PHY_DATA3_SETTLE, csi->settle_time);
++		csi_phy_writel(csi, PHY_CK1_SETTLE, csi->settle_time);
++		/* CSI2_RESET */
++		csi_core_writel(csi, CSI2_RESETN, 0x0);
++		csi_core_writel(csi, CSI2_RESETN, 0x1);
++
++		if(nlanes > 2){
++			csi_core_writel(csi, RXVALID_MASK, 0xf);
++		} else {
++			csi_core_writel(csi, RXVALID_MASK, 0x3);
++		}
++
++		csi_core_writel(csi, PHY_SHUTDOWNZ, 0x0);
++		csi_core_writel(csi, MASK1, 0xffffffff);
++		csi_core_writel(csi, MASK2, 0xffffffff);
++		csi_phy_writel(csi, PHY_ENB, 0x7d);
++	} else {
++
++		if(--csi->enabled > 0) {
++			return 0;
++		}
++		csi_phy_stop(csi, &global_phy_reseter);
++	}
++
++	return 0;
++}
++
++
++static const struct v4l2_subdev_video_ops csi_subdev_video_ops = {
++        .s_stream = csi_subdev_s_stream,
++};
++
++
++static const struct v4l2_subdev_ops csi_subdev_ops = {
++        .core = &csi_subdev_core_ops,
++        .pad = &csi_subdev_pad_ops,
++        .video = &csi_subdev_video_ops,
++};
++
++static ssize_t
++dump_csi(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct csi_device *csi = dev_get_drvdata(dev);
++	char *p = buf;
++
++	p += sprintf(p, "VERSION	:0x%08x\n",	csi_core_readl(csi, VERSION));
++	p += sprintf(p, "N_LANES	:0x%08x\n",	csi_core_readl(csi, N_LANES));
++	p += sprintf(p, "PHY_SHUTDOWNZ	:0x%08x\n",	csi_core_readl(csi, PHY_SHUTDOWNZ));
++	p += sprintf(p, "DPHY_RSTZ	:0x%08x\n",	csi_core_readl(csi, DPHY_RSTZ));
++	p += sprintf(p, "CSI2_RESETN	:0x%08x\n",	csi_core_readl(csi, CSI2_RESETN));
++	p += sprintf(p, "PHY_STATE	:0x%08x\n",	csi_core_readl(csi, PHY_STATE));
++	p += sprintf(p, "DATA_IDS_1	:0x%08x\n",	csi_core_readl(csi, DATA_IDS_1));
++	p += sprintf(p, "DATA_IDS_2	:0x%08x\n",	csi_core_readl(csi, DATA_IDS_2));
++	p += sprintf(p, "ERR1		:0x%08x\n",	csi_core_readl(csi, ERR1));
++	p += sprintf(p, "ERR2		:0x%08x\n",	csi_core_readl(csi, ERR2));
++	p += sprintf(p, "MASK1		:0x%08x\n",	csi_core_readl(csi, MASK1));
++	p += sprintf(p, "MASK2		:0x%08x\n",	csi_core_readl(csi, MASK2));
++	p += sprintf(p, "PHY_TST_CTRL0  :0x%08x\n",	csi_core_readl(csi, PHY_TST_CTRL0));
++	p += sprintf(p, "PHY_TST_CTRL1  :0x%08x\n",	csi_core_readl(csi, PHY_TST_CTRL1));
++	p += sprintf(p, "VC0_FRAME_NUM	:0x%08x\n",	csi_core_readl(csi, VC0_FRAME_NUM));
++	p += sprintf(p, "VC1_FRAME_NUM	:0x%08x\n",	csi_core_readl(csi, VC1_FRAME_NUM));
++	p += sprintf(p, "VC2_FRAME_NUM	:0x%08x\n",	csi_core_readl(csi, VC2_FRAME_NUM));
++	p += sprintf(p, "VC3_FRAME_NUM	:0x%08x\n",	csi_core_readl(csi, VC3_FRAME_NUM));
++	p += sprintf(p, "VC0_LINE_NUM	:0x%08x\n",	csi_core_readl(csi, VC0_LINE_NUM));
++	p += sprintf(p, "VC1_LINE_NUM	:0x%08x\n",	csi_core_readl(csi, VC1_LINE_NUM));
++	p += sprintf(p, "VC2_LINE_NUM	:0x%08x\n",	csi_core_readl(csi, VC2_LINE_NUM));
++	p += sprintf(p, "VC3_LINE_NUM	:0x%08x\n",	csi_core_readl(csi, VC3_LINE_NUM));
++
++	return p - buf;
++}
++
++
++static DEVICE_ATTR(dump_csi, S_IRUGO|S_IWUSR, dump_csi, NULL);
++
++static struct attribute *csi_debug_attrs[] = {
++        &dev_attr_dump_csi.attr,
++	NULL,
++};
++
++static struct attribute_group csi_debug_attr_group = {
++        .name   = "debug",
++        .attrs  = csi_debug_attrs,
++};
++
++
++static int csi_comp_bind(struct device *comp, struct device *master,
++                              void *master_data)
++{
++	struct csi_device *csi = dev_get_drvdata(comp);
++	struct ispcam_device *ispcam = (struct ispcam_device *)master_data;
++	struct v4l2_device *v4l2_dev = &ispcam->v4l2_dev;
++	struct v4l2_subdev *sd = &csi->sd;
++	int ret = 0;
++
++	//dev_info(comp, "----dev_name(comp): %s----%s, %d \n", dev_name(comp), __func__, __LINE__);
++
++	/* link subdev to master.*/
++	csi->ispcam = (void *)ispcam;
++	ispcam->csi = csi;
++
++	/*1. register supported subdev ctrls.*/
++
++
++	/*2. init v4l2_subdev*/
++
++	v4l2_subdev_init(sd, &csi_subdev_ops);
++
++	sd->owner = THIS_MODULE;
++	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++	strscpy(sd->name, dev_name(comp), sizeof(sd->name));
++	v4l2_set_subdevdata(sd, csi);
++
++
++	/* init csi pads. */
++	csi->pads = kzalloc(sizeof(struct media_pad) * CSI_NUM_PADS, GFP_KERNEL);
++	if(!csi->pads) {
++		ret = -ENOMEM;
++		goto err_alloc_pads;
++	}
++	csi->pads[0].index = CSI_PAD_SINK;
++	csi->pads[0].flags = MEDIA_PAD_FL_SINK;
++	csi->pads[1].index = CSI_PAD_SOURCE;
++	csi->pads[1].flags = MEDIA_PAD_FL_SOURCE;
++
++	ret = media_entity_pads_init(&sd->entity, CSI_NUM_PADS, csi->pads);
++
++	/*3. register v4l2_subdev*/
++	sd->entity.function = MEDIA_ENT_F_IO_V4L;
++	ret = v4l2_device_register_subdev(v4l2_dev, sd);
++	if(ret < 0) {
++		dev_err(comp, "Failed to register v4l2_subdev for csi\n");
++		goto err_subdev_register;
++	}
++
++
++	return 0;
++err_subdev_register:
++err_alloc_pads:
++	return ret;
++}
++
++
++static void csi_comp_unbind(struct device *comp, struct device *master,
++                                 void *master_data)
++{
++        struct csi_device *csi = dev_get_drvdata(comp);
++
++	dev_info(comp, "----TODO-implement unbind: %p---%s, %d \n",csi, __func__, __LINE__);
++}
++
++
++
++static const struct component_ops csi_comp_ops = {
++        .bind = csi_comp_bind,
++        .unbind = csi_comp_unbind,
++};
++
++
++static int ingenic_csi_probe(struct platform_device *pdev)
++{
++
++	struct csi_device *csi = NULL;
++	struct resource *regs = NULL;
++
++	int ret = 0;
++	int i = 0;
++
++	csi = kzalloc(sizeof(struct csi_device), GFP_KERNEL);
++	if(!csi) {
++		pr_err("Failed to alloc csi dev [%s]\n", pdev->name);
++		return -ENOMEM;
++	}
++
++	csi->dev = &pdev->dev;
++	platform_set_drvdata(pdev, csi);
++	dev_set_drvdata(csi->dev, csi);
++
++	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if(!regs) {
++		dev_err(&pdev->dev, "No iomem resource!\n");
++		goto err_get_resource;
++	}
++
++	csi->iobase = devm_ioremap_resource(&pdev->dev, regs);
++	if(!csi->iobase) {
++		goto err_ioremap;
++	}
++
++	csi->phy_base = CSI_PHY_IOBASE | 0xa0000000;
++
++	/*TODO: clk*/
++	csi->gate_clk = of_clk_get(csi->dev->of_node, 0);
++	if(!csi->gate_clk) {
++		dev_err(csi->dev, "failed to get gate clk\n");
++		goto err_gate_clk;
++	}
++	clk_prepare_enable(csi->gate_clk);
++
++	ret = sysfs_create_group(&csi->dev->kobj, &csi_debug_attr_group);
++	if (ret) {
++		dev_err(csi->dev, "device create sysfs group failed\n");
++
++		ret = -EINVAL;
++		goto err_sys_group;
++	}
++
++	for(i = 0; i < 2; i++) {
++		if(global_phy_reseter.csi[i] == NULL) {
++			global_phy_reseter.csi[i] = csi;
++			csi->reset_index = i;
++			break;
++		}
++	}
++
++	ret = component_add(csi->dev, &csi_comp_ops);
++	if(ret < 0) {
++		dev_err(csi->dev, "Failed to add component csi!\n");
++	}
++
++	return 0;
++err_sys_group:
++err_gate_clk:
++err_ioremap:
++err_get_resource:
++
++	return ret;
++}
++
++
++
++static int ingenic_csi_remove(struct platform_device *pdev)
++{
++	struct csi_device *csi = dev_get_drvdata(&pdev->dev);
++
++	clk_disable_unprepare(csi->gate_clk);
++	return 0;
++}
++
++
++
++static const struct of_device_id ingenic_csi_dt_match[] = {
++        { .compatible = "ingenic,x2500-csi" },
++        { }
++};
++
++MODULE_DEVICE_TABLE(of, ingenic_csi_dt_match);
++
++static int __maybe_unused ingenic_csi_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	struct csi_device *csi = dev_get_drvdata(&pdev->dev);
++
++	if(csi->enabled){
++		dev_err(csi->dev, "faild to suspend, csi is streaming on\n");
++		return -EBUSY;
++	}
++
++	clk_disable_unprepare(csi->gate_clk);
++        return 0;
++}
++
++static int __maybe_unused ingenic_csi_resume(struct platform_device *pdev)
++{
++	struct csi_device *csi = dev_get_drvdata(&pdev->dev);
++
++	clk_prepare_enable(csi->gate_clk);
++        return 0;
++}
++
++
++static struct platform_driver ingenic_csi_driver = {
++        .probe = ingenic_csi_probe,
++        .remove = ingenic_csi_remove,
++	.suspend = ingenic_csi_suspend,
++	.resume = ingenic_csi_resume,
++        .driver = {
++                .name = "ingenic-csi",
++                .of_match_table = ingenic_csi_dt_match,
++        },
++};
++
++module_platform_driver(ingenic_csi_driver);
++
++MODULE_ALIAS("platform:ingenic-csi");
++MODULE_DESCRIPTION("ingenic csi subsystem");
++MODULE_AUTHOR("qipengzhen <aric.pzqi@ingenic.com>");
++MODULE_LICENSE("GPL v2");
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core-tuning.c b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core-tuning.c
+new file mode 100644
+index 000000000..954afe3ae
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core-tuning.c
+@@ -0,0 +1,704 @@
++#include <linux/videodev2.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <media/v4l2-ctrls.h>
++#include "isp-drv.h"
++
++static inline int tx_isp_isp_hflip_s_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	int hvflip;
++	int value = control->value;
++	isp->ctrls.hflip = value;
++
++	hvflip = (isp->ctrls.hflip << 0)|(isp->ctrls.vflip << 1);
++	tisp_hv_flip_enable(isp->sensor_id, hvflip);
++
++	return 0;
++}
++
++static inline int tx_isp_isp_hflip_g_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	int ret = 0;
++	control->value = isp->ctrls.hflip;
++	return ret;
++}
++
++static inline int tx_isp_isp_vflip_s_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	int hvflip;
++	int value = control->value;
++	isp->ctrls.vflip = value;
++
++	hvflip = (isp->ctrls.hflip << 0)|(isp->ctrls.vflip << 1);
++	tisp_hv_flip_enable(isp->sensor_id, hvflip);
++
++	return 0;
++}
++
++static inline int tx_isp_isp_vflip_g_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	int ret = 0;
++	control->value = isp->ctrls.vflip;
++	return ret;
++}
++
++static inline int tx_isp_isp_sat_s_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	int value = control->value;
++	tisp_set_saturation(isp->sensor_id, value);
++	isp->ctrls.saturation = value;
++	return 0;
++}
++
++static inline int tx_isp_isp_sat_g_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	control->value = isp->ctrls.saturation;
++	return 0;
++}
++
++static inline int tx_isp_isp_bright_s_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	int value = control->value;
++	tisp_set_brightness(isp->sensor_id, value);
++	isp->ctrls.brightness = value;
++
++	return 0;
++}
++
++static inline int tx_isp_isp_bright_g_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	control->value = isp->ctrls.brightness;
++
++	return 0;
++}
++
++static inline int tx_isp_isp_contrast_s_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	int value = control->value;
++	tisp_set_contrast(isp->sensor_id, value);
++	isp->ctrls.contrast = value;
++
++	return 0;
++}
++
++static inline int tx_isp_isp_contrast_g_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	control->value = isp->ctrls.contrast;
++
++	return 0;
++}
++
++static inline int tx_isp_isp_sharp_s_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	int value = control->value;
++	tisp_set_sharpness(isp->sensor_id, value);
++	isp->ctrls.sharpness = value;
++
++	return 0;
++}
++
++static inline int tx_isp_isp_sharp_g_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	control->value = isp->ctrls.sharpness;
++
++	return 0;
++}
++
++
++extern int tisp_ae_main_manual_set(tisp_ae_ctrls_t ae_manual);
++extern int tisp_ae_main_manual_get(tisp_ae_ctrls_t *ae_manual);
++extern int tisp_ae_sec_manual_set(tisp_ae_ctrls_t ae_manual);
++extern int tisp_ae_sec_manual_get(tisp_ae_ctrls_t *ae_manual);
++
++static int ispcore_exp_auto_s_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	tisp_ae_ctrls_t ae_manual;
++	int ret = 0;
++	/*
++	 * control->value.
++	 *	0: 自动�光.
++	 *	1: 手动�光.
++	 *	2. 快门优先.
++	 *	3. 光圈优先.
++	 * */
++
++	if(isp->sensor_id == 0)
++		ret = tisp_ae_main_manual_get(&ae_manual);
++	else if(isp->sensor_id == 1)
++		ret = tisp_ae_sec_manual_get(&ae_manual);
++	else
++		ret = -EINVAL;
++	if(ret)
++		return ret;
++
++	if(control->value == V4L2_EXPOSURE_AUTO) {
++		ae_manual.tisp_ae_it_manual = 0;
++	} else if(control->value == V4L2_EXPOSURE_MANUAL) {
++		ae_manual.tisp_ae_it_manual = 1;
++	}
++
++	if(isp->sensor_id == 0)
++		ret = tisp_ae_main_manual_set(ae_manual);
++	else if(isp->sensor_id == 1)
++		ret = tisp_ae_sec_manual_set(ae_manual);
++	else
++		ret = -EINVAL;
++
++	return ret;
++}
++
++/* 获�当��光方�.*/
++static int ispcore_exp_auto_g_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	tisp_ae_ctrls_t ae_manual;
++	int ret = 0;
++
++	if(isp->sensor_id == 0)
++		ret = tisp_ae_main_manual_get(&ae_manual);
++	else if(isp->sensor_id == 1)
++		ret = tisp_ae_sec_manual_get(&ae_manual);
++	else
++		ret = -EINVAL;
++
++	control->value = ae_manual.tisp_ae_it_manual == 0 ? V4L2_EXPOSURE_AUTO : V4L2_EXPOSURE_MANUAL;
++
++	return ret;
++}
++
++/* 设置�光等级. eg: [-4, 4]
++ *
++ *  相对�光时间. 从 [-4, 4] -> [inte_min, inte_max]
++ * */
++static int ispcore_exp_s_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	return 0;
++}
++
++static int ispcore_exp_g_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	return 0;
++}
++
++/* 设置�光时间. */
++static int ispcore_exp_abs_s_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	tisp_ae_ctrls_t ae_manual;
++	int ret = 0;
++
++	if(isp->sensor_id == 0)
++		ret = tisp_ae_main_manual_get(&ae_manual);
++	else if(isp->sensor_id == 1)
++		ret = tisp_ae_sec_manual_get(&ae_manual);
++	else
++		ret = -EINVAL;
++	if(ret)
++		return ret;
++
++	if(ae_manual.tisp_ae_it_manual) {
++		ae_manual.tisp_ae_sensor_integration_time = control->value;
++		if(isp->sensor_id == 0)
++			ret = tisp_ae_main_manual_set(ae_manual);
++		else if(isp->sensor_id == 1)
++			ret = tisp_ae_sec_manual_set(ae_manual);
++		else
++			ret = -EINVAL;
++	} else {
++		dev_warn(isp->dev, "set exp_abs while in exposure [auto] mode.\n");
++	}
++
++	return ret;
++
++}
++
++static int ispcore_exp_abs_g_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	tisp_ae_ctrls_t ae_manual;
++	int ret = 0;
++
++	if(isp->sensor_id == 0)
++		ret = tisp_ae_main_manual_get(&ae_manual);
++	else if(isp->sensor_id == 1)
++		ret = tisp_ae_sec_manual_get(&ae_manual);
++	else
++		ret = -EINVAL;
++
++	control->value = ae_manual.tisp_ae_sensor_integration_time;
++
++	return ret;
++}
++
++/*设置自动增益控制方�
++ * 0: 自动增益控制
++ * 1: 手动增益控制.
++ * */
++static inline int ispcore_auto_gain_s_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	tisp_ae_ctrls_t ae_manual;
++	int ret = 0;
++
++
++	if(isp->sensor_id == 0)
++		ret = tisp_ae_main_manual_get(&ae_manual);
++	else if(isp->sensor_id == 1)
++		ret = tisp_ae_sec_manual_get(&ae_manual);
++	else
++		ret = -EINVAL;
++	if(ret)
++		return ret;
++
++	ae_manual.tisp_ae_ag_manual = control->value;
++
++	if(isp->sensor_id == 0)
++		ret = tisp_ae_main_manual_set(ae_manual);
++	else if(isp->sensor_id == 1)
++		ret = tisp_ae_sec_manual_set(ae_manual);
++	else
++		ret = -EINVAL;
++
++	return ret;
++}
++
++/*获�自动增益控制方�.*/
++static inline int ispcore_auto_gain_g_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	tisp_ae_ctrls_t ae_manual;
++	int ret = 0;
++
++	if(isp->sensor_id == 0)
++		ret = tisp_ae_main_manual_get(&ae_manual);
++	else if(isp->sensor_id == 1)
++		ret = tisp_ae_sec_manual_get(&ae_manual);
++	else
++		ret = -EINVAL;
++
++	control->value = ae_manual.tisp_ae_ag_manual;
++
++	return ret;
++}
++
++/*手动增益控制模�下，设置当�增益.*/
++static inline int ispcore_gain_s_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	tisp_ae_ctrls_t ae_manual;
++	int ret = 0;
++
++	if(isp->sensor_id == 0)
++		ret = tisp_ae_main_manual_get(&ae_manual);
++	else if(isp->sensor_id == 1)
++		ret = tisp_ae_sec_manual_get(&ae_manual);
++	else
++		ret = -EINVAL;
++	if(ret)
++		return ret;
++
++	if(ae_manual.tisp_ae_ag_manual) {
++		ae_manual.tisp_ae_sensor_again = control->value;
++		if(isp->sensor_id == 0)
++			ret = tisp_ae_main_manual_set(ae_manual);
++		else if(isp->sensor_id == 1)
++			ret = tisp_ae_sec_manual_set(ae_manual);
++		else
++			ret = -EINVAL;
++	} else {
++		dev_warn(isp->dev, "set exp_abs while in exposure [auto] mode.\n");
++	}
++
++	return ret;
++}
++static inline int ispcore_gain_g_control(struct isp_device *isp, struct v4l2_control *control)
++{
++	tisp_ae_ctrls_t ae_manual;
++	int ret = 0;
++
++	if(isp->sensor_id == 0)
++		ret = tisp_ae_main_manual_get(&ae_manual);
++	else if(isp->sensor_id == 1)
++		ret = tisp_ae_sec_manual_get(&ae_manual);
++	else
++		ret = -EINVAL;
++
++	control->value = ae_manual.tisp_ae_sensor_again;
++
++	return ret;
++}
++
++static inline int tx_isp_isp_flicker_s_attr(struct isp_device *isp, struct v4l2_control *control)
++{
++	tisp_anfiflicker_attr_t attr;
++	int ret = 0;
++
++	ret = copy_from_user(&attr, (const void __user*)control->value, sizeof(tisp_anfiflicker_attr_t));
++	if(ret != 0){
++		ISP_ERROR("[ %s:%d ] copy error!!!\n", __func__, __LINE__);
++	} else {
++		ret = tisp_s_antiflick(isp->sensor_id, &attr);
++		if(ret != 0)
++			ISP_WARNING("[ %s:%d ] set control failed!!!\n", __func__, __LINE__);
++	}
++
++	return ret;
++}
++
++static inline int tx_isp_isp_flicker_g_attr(struct isp_device *isp, struct v4l2_control *control)
++{
++	tisp_anfiflicker_attr_t attr;
++	int ret = 0;
++
++	ret = tisp_g_antiflick(isp->sensor_id, &attr);
++	if(ret != 0){
++		ISP_ERROR("[ %s:%d ] get control failed!!!\n", __func__, __LINE__);
++		goto err_get_flicker;
++	}
++
++	ret = copy_to_user((void __user*)control->value, (const void *)&attr, sizeof(tisp_anfiflicker_attr_t));
++	if(ret != 0)
++		ISP_ERROR("[ %s:%d ] copy error!!!\n", __func__, __LINE__);
++
++err_get_flicker:
++	return ret;
++}
++
++static int tx_isp_isp_module_s_attr(struct isp_device *isp, struct v4l2_control *control)
++{
++	tisp_module_control_t module;
++	int ret = 0;
++
++	module.key = control->value;
++	tisp_s_module_control(isp->sensor_id, module);
++
++	return ret;
++}
++
++static int tx_isp_isp_module_g_attr(struct isp_device *isp, struct v4l2_control *control)
++{
++	tisp_module_control_t module;
++	int ret = 0;
++
++	tisp_g_module_control(isp->sensor_id, &module);
++	control->value = module.key;
++
++	return ret;
++}
++
++static inline int tx_isp_isp_day_or_night_g_ctrl(struct isp_device *isp, struct v4l2_control *control)
++{
++	control->value = isp->ctrls.daynight;
++	return 0;
++}
++
++static inline int tx_isp_isp_day_or_night_s_ctrl(struct isp_device *isp, struct v4l2_control *control)
++{
++	int ret = 0;
++	TISP_MODE_DN_E dn = control->value;
++
++	if(dn != isp->ctrls.daynight){
++		tisp_day_or_night_s_ctrl(isp->sensor_id, dn);
++		isp->ctrls.daynight = dn;
++	}
++
++	return ret;
++}
++
++static int tx_isp_isp_ae_luma_g_ctrl(struct isp_device *isp, struct v4l2_control *control)
++{
++#if 0
++	unsigned char luma;
++	struct v4l2_subdev_format *input_fmt = &isp->formats[ISP_PAD_SINK];
++	int width = input_fmt->format.width;
++	int height = input_fmt->format.height;
++
++	tisp_g_ae_luma(&core->core_tuning, &luma, width, height);
++	control->value = luma;
++#endif
++	return 0;
++}
++
++static int tx_isp_bcsh_hue_s_ctrl(struct isp_device *isp, struct v4l2_control *control)
++{
++	unsigned char value = control->value;
++	int ret = 0;
++
++	tisp_set_bcsh_hue(isp->sensor_id, value);
++	isp->ctrls.hue = value;
++
++	return ret;
++}
++
++static int tx_isp_bcsh_hue_g_ctrl(struct isp_device *isp, struct v4l2_control *control)
++{
++	int ret = 0;
++
++	control->value = isp->ctrls.hue;
++
++	return ret;
++}
++
++static int tx_isp_switch_bin(struct isp_device *isp, struct v4l2_control *control)
++{
++	tisp_bin_t attr;
++	int ret = 0;
++
++	ret = private_copy_from_user(&attr, (const void __user*)control->value, sizeof(attr));
++	if(ret != 0){
++		ISP_ERROR("[ %s:%d ] copy error!!!\n", __func__, __LINE__);
++	} else {
++		//printk("\n------------------>> Test:%d-%d-%s <<------------------\n", attr.enable, attr.mode, attr.bname);
++		ret = tisp_switch_bin(isp->sensor_id, &attr);
++		if(ret != 0)
++			ISP_WARNING("[ %s:%d ] switch bin failed!!!\n", __func__, __LINE__);
++	}
++	return ret;
++}
++
++static int tx_isp_faceae_s_attr(struct isp_video_device *ispvideo, struct v4l2_control *control)
++{
++
++	struct ispcam_device *ispcam = ispvideo->ispcam;
++	struct mscaler_device *mscaler = ispcam->mscaler;
++	struct isp_device *isp = ispcam->isp;
++        struct media_pad *remote = media_entity_remote_pad(&ispvideo->pad);
++	struct v4l2_subdev_format *input_fmt = &mscaler->formats[MSCALER_PAD_SINK];
++	struct v4l2_subdev_format *output_fmt = &mscaler->formats[remote->index];
++
++	int in_width = input_fmt->format.width;
++	int in_height = input_fmt->format.height;
++	int out_width = output_fmt->format.width;
++	int out_height = output_fmt->format.height;
++
++	tisp_face_t attr;
++	int ret = 0;
++
++	ret = copy_from_user(&attr, (const void __user*)control->value, sizeof(attr));
++	if(ret != 0){
++		ISP_ERROR("[ %s:%d ] copy error!!!\n", __func__, __LINE__);
++	} else {
++		attr.top = (attr.top * in_height)/out_height;
++		attr.bottom = (attr.bottom * in_height)/out_height;
++		attr.left = (attr.left * in_width)/out_width;
++		attr.right = (attr.right * in_width)/out_width;
++		ret = tisp_ae_face_set(isp->sensor_id, &attr);
++		if(ret != 0)
++			ISP_WARNING("[ %s:%d ] set ae face failed!!!\n", __func__, __LINE__);
++
++	}
++	return ret;
++}
++
++static int tx_isp_faceae_g_attr(struct isp_device *isp, struct v4l2_control *control)
++{
++	tisp_face_t attr;
++	int ret = 0;
++
++	ret = tisp_ae_face_get(isp->sensor_id, &attr);
++	if(ret != 0){
++		ISP_WARNING("[ %s:%d ] get ae smart failed!!!\n", __func__, __LINE__);
++		goto err_get_aesmart;
++	}
++
++	ret = copy_to_user((void __user*)control->value, (const void *)&attr, sizeof(attr));
++	if(ret != 0)
++		ISP_ERROR("[ %s:%d ] copy error!!!\n", __func__, __LINE__);
++
++err_get_aesmart:
++	return ret;
++}
++
++static int tx_isp_faceawb_s_attr(struct isp_device *isp, struct v4l2_control *control)
++{
++	tisp_face_t attr;
++	int ret = 0;
++
++	ret = copy_from_user(&attr, (const void __user*)control->value, sizeof(attr));
++	if(ret != 0){
++		ISP_ERROR("[ %s:%d ] copy error!!!\n", __func__, __LINE__);
++	} else {
++		ret = tisp_awb_face_set(isp->sensor_id, &attr);
++		if(ret != 0)
++			ISP_WARNING("[ %s:%d ] set awb face failed!!!\n", __func__, __LINE__);
++
++	}
++	return ret;
++}
++
++static int tx_isp_faceawb_g_attr(struct isp_device *isp, struct v4l2_control *control)
++{
++	tisp_face_t attr;
++	int ret = 0;
++
++	ret = tisp_awb_face_get(isp->sensor_id, &attr);
++	if(ret != 0){
++		ISP_WARNING("[ %s:%d ] get awb face attr failed!!!\n", __func__, __LINE__);
++		goto err_get_aesmart;
++	}
++
++	ret = copy_to_user((void __user*)control->value, (const void *)&attr, sizeof(attr));
++	if(ret != 0)
++		ISP_ERROR("[ %s:%d ] copy error!!!\n", __func__, __LINE__);
++
++err_get_aesmart:
++	return ret;
++}
++
++static int wdr_enable(struct isp_device *isp, struct v4l2_control *control)
++{
++	struct isp_async_device	*isd = &isp->ispcam->isd[0];
++	//int enable = control->value;
++	int ret = 0;
++
++	ret = v4l2_s_ctrl(NULL, isd->sd->ctrl_handler, control);
++	return ret;
++}
++
++static int tx_isp_set_default_bin_path(struct isp_device *isp, struct v4l2_control *control)
++{
++	int ret = 0;
++	ret = copy_from_user(&isp->bpath, (const void __user*)control->value, sizeof(isp->bpath));
++	return ret;
++}
++
++int isp_video_g_ctrl(struct file *file, void *fh, struct v4l2_control *a)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct isp_device 	*isp	= ispcam->isp;
++	int ret = 0;
++
++	switch(a->id){
++		case V4L2_CID_HFLIP:
++			ret = tx_isp_isp_hflip_g_control(isp, a);
++			break;
++		case V4L2_CID_VFLIP:
++			ret = tx_isp_isp_vflip_g_control(isp, a);
++			break;
++		case V4L2_CID_SATURATION:
++			ret = tx_isp_isp_sat_g_control(isp, a);
++			break;
++		case V4L2_CID_BRIGHTNESS:
++			ret = tx_isp_isp_bright_g_control(isp, a);
++			break;
++		case V4L2_CID_CONTRAST:
++			ret = tx_isp_isp_contrast_g_control(isp, a);
++			break;
++		case V4L2_CID_SHARPNESS:
++			ret = tx_isp_isp_sharp_g_control(isp, a);
++			break;
++		case V4L2_CID_EXPOSURE_AUTO:
++			ret = ispcore_exp_auto_g_control(isp, a);
++			break;
++		case V4L2_CID_EXPOSURE_ABSOLUTE:
++			ret = ispcore_exp_abs_g_control(isp, a);
++			break;
++		case V4L2_CID_EXPOSURE:
++			ret = ispcore_exp_g_control(isp, a);
++			break;
++		case V4L2_CID_AUTOGAIN:
++			ret = ispcore_auto_gain_g_control(isp, a);
++			break;
++		case V4L2_CID_GAIN:
++			ret = ispcore_gain_g_control(isp, a);
++			break;
++		case V4L2_CID_HUE:
++			ret = tx_isp_bcsh_hue_g_ctrl(isp, a);
++			break;
++		case V4L2_CID_POWER_LINE_FREQUENCY:
++			ret = tx_isp_isp_flicker_g_attr(isp, a);
++			break;
++		case IMAGE_TUNING_CID_MODULE_CONTROL:
++			ret = tx_isp_isp_module_g_attr(isp, a);
++			break;
++		case IMAGE_TUNING_CID_DAY_OR_NIGHT:
++			ret = tx_isp_isp_day_or_night_g_ctrl(isp, a);
++			break;
++		case IMAGE_TUNING_CID_AE_LUMA:
++			ret = tx_isp_isp_ae_luma_g_ctrl(isp, a);
++			break;
++		case IMAGE_TUNING_CID_FACE_AE_CONTROL:
++			ret = tx_isp_faceae_g_attr(isp, a);
++			break;
++		case IMAGE_TUNING_CID_FACE_AWB_CONTROL:
++			ret = tx_isp_faceawb_g_attr(isp, a);
++			break;
++		default:
++			ret = -EPERM;
++			break;
++	}
++
++	return ret;
++}
++
++
++int isp_video_s_ctrl(struct file *file, void *fh, struct v4l2_control *a)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct isp_device 	*isp	= ispcam->isp;
++	int ret = 0;
++
++	switch (a->id) {
++		case V4L2_CID_HFLIP:
++			ret = tx_isp_isp_hflip_s_control(isp, a);
++			break;
++		case V4L2_CID_VFLIP:
++			ret = tx_isp_isp_vflip_s_control(isp, a);
++			break;
++		case V4L2_CID_SATURATION:
++			ret = tx_isp_isp_sat_s_control(isp, a);
++			break;
++		case V4L2_CID_BRIGHTNESS:
++			ret = tx_isp_isp_bright_s_control(isp, a);
++			break;
++		case V4L2_CID_CONTRAST:
++			ret = tx_isp_isp_contrast_s_control(isp, a);
++			break;
++		case V4L2_CID_SHARPNESS:
++			ret = tx_isp_isp_sharp_s_control(isp, a);
++			break;
++		case V4L2_CID_EXPOSURE_AUTO:
++			ret = ispcore_exp_auto_s_control(isp, a);
++			break;
++		case V4L2_CID_EXPOSURE_ABSOLUTE:
++			ret = ispcore_exp_abs_s_control(isp, a);
++			break;
++		case V4L2_CID_EXPOSURE:
++			ret = ispcore_exp_s_control(isp, a);
++			break;
++		case V4L2_CID_AUTOGAIN:
++			ret = ispcore_auto_gain_s_control(isp, a);
++			break;
++		case V4L2_CID_GAIN:
++			ret = ispcore_gain_s_control(isp, a);
++			break;
++		case V4L2_CID_HUE:
++			ret = tx_isp_bcsh_hue_s_ctrl(isp, a);
++			break;
++		case IMAGE_TUNING_CID_SWITCH_BIN:
++			ret = tx_isp_switch_bin(isp, a);
++			break;
++		case V4L2_CID_POWER_LINE_FREQUENCY:
++			ret = tx_isp_isp_flicker_s_attr(isp, a);
++			break;
++		case IMAGE_TUNING_CID_MODULE_CONTROL:
++			ret = tx_isp_isp_module_s_attr(isp, a);
++			break;
++		case IMAGE_TUNING_CID_DAY_OR_NIGHT:
++			ret = tx_isp_isp_day_or_night_s_ctrl(isp, a);
++			break;
++		case IMAGE_TUNING_CID_FACE_AE_CONTROL:
++			ret = tx_isp_faceae_s_attr(ispvideo, a);
++			break;
++		case IMAGE_TUNING_CID_FACE_AWB_CONTROL:
++			ret = tx_isp_faceawb_s_attr(isp, a);
++			break;
++		case V4L2_CID_WIDE_DYNAMIC_RANGE:
++			ret = wdr_enable(isp, a);
++			break;
++		case IMAGE_TUNING_CID_SET_DEFAULT_BIN_PATH:
++			ret = tx_isp_set_default_bin_path(isp, a);
++			break;
++		default:
++			ret = -EPERM;
++			break;
++	}
++	return ret;
++}
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/Makefile b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/Makefile
+new file mode 100755
+index 000000000..a0e01ba43
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/Makefile
+@@ -0,0 +1 @@
++obj-y  +=isp-core.a
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/inc/system_sensor_drv.h b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/inc/system_sensor_drv.h
+new file mode 100644
+index 000000000..e6546a59d
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/inc/system_sensor_drv.h
+@@ -0,0 +1,96 @@
++#ifndef __SENSOR_DRV_H__
++#define __SENSOR_DRV_H__
++
++#include "linux/types.h"
++
++#define LOG2_GAIN_SHIFT 16
++
++typedef struct _sensor_context_t
++{
++	int sensor_id;
++	uint16_t again;
++	uint16_t dgain;
++	uint8_t n_context;
++	uint8_t wdr_mode;
++	uint16_t again_x2;
++	uint16_t dgain_coarse;
++	uint16_t dgain_fine;
++	uint8_t column_buffer_gain_index;
++	uint16_t again_short;
++	uint16_t it;
++	uint16_t it_short;
++	uint16_t dgain_short;
++} sensor_context_t;
++
++typedef struct _image_resolution_t
++{
++	uint16_t width;
++	uint16_t height;
++} image_resolution_t;
++
++typedef struct _sensor_param_t
++{
++	uint8_t mode;
++	image_resolution_t total;
++	image_resolution_t active;
++	sensor_context_t sensor_ctx;
++	int32_t again_log2_max;
++	int32_t dgain_log2_max;
++	uint32_t integration_time_min;
++	uint32_t integration_time_max;
++	uint32_t integration_time_long_max;
++	uint32_t integration_time_limit;
++	uint16_t day_light_integration_time_max;
++	uint8_t integration_time_apply_delay;
++	uint8_t analog_gain_apply_delay;
++	uint8_t digital_gain_apply_delay;
++	int32_t xoffset;
++	int32_t yoffset;
++	int32_t anti_flicker_pos;
++	uint32_t lines_per_second;
++	uint32_t integration_time_min_short;
++	uint32_t integration_time_max_short;
++	uint32_t again_log2_max_short;
++	uint32_t dgain_log2_max_short;
++	uint8_t analog_gain_short_apply_delay;
++	uint8_t digital_gain_short_apply_delay;
++	uint8_t integration_time_short_apply_delay;
++} sensor_param_t;
++
++typedef struct _sensor_control_t
++{
++	sensor_param_t param[3];
++	void (*hw_reset_disable)(void);
++	void (*hw_reset_enable)(void);
++	int32_t (*alloc_analog_gain)(int32_t gain, sensor_context_t *p_ctx);
++	int32_t (*alloc_analog_gain_short)(int32_t gain, sensor_context_t *p_ctx);
++	int32_t (*alloc_digital_gain)(int32_t gain, sensor_context_t *p_ctx);
++	int32_t (*alloc_digital_gain_short)(int32_t gain, sensor_context_t *p_ctx);
++	uint32_t (*alloc_integration_time)(uint32_t int_time, sensor_context_t *p_ctx);
++	uint32_t (*alloc_integration_time_short)(uint32_t int_time, sensor_context_t *p_ctx);
++	void (*set_integration_time)(uint16_t int_time, sensor_param_t *param);
++	void (*set_integration_time_short)(uint16_t int_time, sensor_param_t *param);
++	void (*start_changes)(sensor_context_t *p_ctx);
++	void (*end_changes)(sensor_context_t *p_ctx);
++	void (*set_analog_gain)(uint32_t again_reg_val, sensor_context_t *p_ctx);
++	void (*get_analog_gain)(uint32_t *again_reg_val, sensor_context_t *p_ctx);
++	void (*set_analog_gain_short)(uint32_t again_reg_val, sensor_context_t *p_ctx);
++	void (*get_analog_gain_short)(uint32_t *again_reg_val, sensor_context_t *p_ctx);
++	void (*set_digital_gain)(uint32_t dgain_reg_val, sensor_context_t *p_ctx);
++	void (*set_digital_gain_short)(uint32_t dgain_reg_val, sensor_context_t *p_ctx);
++	uint16_t (*get_normal_fps)(sensor_param_t *param);
++	uint16_t (*read_black_pedestal)(int i, uint32_t gain);
++	void (*set_mode)( uint8_t mode, sensor_param_t *param);
++	void (*set_wdr_mode)(uint8_t wdr, sensor_param_t *param);
++	uint32_t (*fps_control)(uint8_t fps, sensor_param_t *param);
++	uint16_t (*get_id)(sensor_context_t *p_ctx);
++	void (*disable_isp)(sensor_context_t *p_ctx);
++	uint32_t (*get_lines_per_second)(sensor_param_t *param);
++} sensor_control_t;
++
++typedef sensor_control_t *sensor_control_ptr_t;
++
++void sensor_init(sensor_control_t *ctrl, int vinum);
++int sensor_early_init(void *ispcore);
++
++#endif /* __SENSOR_DRV_H__ */
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/inc/tiziano-core-ctrl.h b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/inc/tiziano-core-ctrl.h
+new file mode 100644
+index 000000000..2bbacd171
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/inc/tiziano-core-ctrl.h
+@@ -0,0 +1,868 @@
++#ifndef __TIZIANO_TIZIANO_CORE_TUNING_H__
++#define __TIZIANO_TIZIANO_CORE_TUNING_H__
++#include "tiziano-isp.h"
++extern int day_night[2];
++
++typedef enum tisp_mode_day_and_night {
++	TISP_RUNING_MODE_DAY_MODE,
++	TISP_RUNING_MODE_NIGHT_MODE,
++	TISP_RUNING_MODE_CUSTOM_MODE,
++	TISP_RUNING_MODE_BUTT,
++} TISP_MODE_DN_E;
++
++struct isp_core_sensor_attr{
++	unsigned int hts;/* sensor hts */
++	unsigned int vts;/* sensor vts */
++	unsigned int fps;/* sensor fps: */
++	unsigned int width;/* sensor width*/
++	unsigned int height;/* sensor height*/
++};
++
++typedef enum {
++	ISP_CORE_FLIP_NORMAL_MODE = 0,
++	ISP_CORE_FLIP_H_MODE = 1,
++	ISP_CORE_FLIP_V_MODE = 2,
++	ISP_CORE_FLIP_HV_MODE = 3,
++	ISP_CORE_FLIP_MODE_BUTT,
++} ISP_CORE_HVFLIP;
++
++typedef struct tisp_ncu_info {
++	uint32_t width;
++	uint32_t height;
++	uint32_t sta_y_block_size;
++	uint32_t sta_y_stride;
++	uint32_t sta_y_buf_size;
++} tisp_ncu_info_t;
++
++typedef enum {
++	IMP_ISP_GAMMA_CURVE_DEFAULT,
++	IMP_ISP_GAMMA_CURVE_SRGB,
++	IMP_ISP_GAMMA_CURVE_HDR,
++	IMP_ISP_GAMMA_CURVE_USER,
++	IMP_ISP_GAMMA_CURVE_BUTT,
++} tisp_gamma_type_t;
++typedef struct tisp_gamma_lut{
++	tisp_gamma_type_t type;
++	unsigned short gamma[129];
++} tisp_gamma_t;
++
++typedef struct {
++	unsigned char weight[225];
++} tisp_3a_weight_t;
++
++typedef struct tisp_zone_info{
++	unsigned int zone[15][15];
++}  __attribute__((packed, aligned(1))) tisp_zone_info_t;
++
++typedef struct {
++	tisp_zone_info_t wb_r;
++	tisp_zone_info_t wb_g;
++	tisp_zone_info_t wb_b;
++} tisp_wb_statis_info_t;
++
++typedef enum tisp_wb_algo_t{
++	IMPISP_AWB_ALGO_NORMAL,
++	IMPISP_AWB_ALGO_GRAYWORLD,
++	IMPISP_AWB_ALGO_REWEIGHT,
++} TISP_AWB_ALGO;
++
++typedef struct tisp_ae_ex_min {
++	unsigned int min_it;
++	unsigned int min_again;
++	unsigned int min_it_short;
++	unsigned int min_again_short;
++} tisp_ae_ex_min_t;
++
++typedef union tisp_module_control {
++	unsigned int key;
++	struct {
++		unsigned int bitBypassBLC : 1; /* [0]  */
++		unsigned int bitBypassLSC : 1; /* [1]  */
++		unsigned int bitBypassAWB0 : 1; /* [2]  */
++		unsigned int bitBypassWDR : 1; /* [3]  */
++		unsigned int bitBypassDPC : 1; /* [4]  */
++		unsigned int bitBypassGIB : 1; /* [5]	*/
++		unsigned int bitBypassAWB1 : 1; /* [6]  */
++		unsigned int bitBypassADR : 1; /* [7]	 */
++		unsigned int bitBypassDMSC : 1; /* [8]	 */
++		unsigned int bitBypassCCM : 1; /* [9]  */
++		unsigned int bitBypassGAMMA : 1; /* [10]  */
++		unsigned int bitBypassDEFOG : 1; /* [11] */
++		unsigned int bitBypassCSC : 1; /* [12]	 */
++		unsigned int bitBypassMDNS : 1; /* [13]	 */
++		unsigned int bitBypassYDNS : 1; /* [14]  */
++		unsigned int bitBypassBCSH : 1; /* [15]	 */
++		unsigned int bitBypassCLM : 1; /* [16]	 */
++		unsigned int bitBypassYSP : 1; /* [17]	 */
++		unsigned int bitBypassSDNS : 1; /* [18]	 */
++		unsigned int bitBypassCDNS : 1; /* [19]	 */
++		unsigned int bitBypassHLDC : 1; /* [20]	 */
++		unsigned int bitBypassLCE : 1; /* [21]	 */
++		unsigned int bitRsv : 10; /* [22 ~ 30]	*/
++	};
++} tisp_module_control_t;
++
++typedef struct tisp_autozoom_control {
++	int32_t zoom_chx_en[3];
++	int32_t zoom_left[3];
++	int32_t zoom_top[3];
++	int32_t zoom_width[3];
++	int32_t zoom_height[3];
++} tisp_autozoom_attr_t;
++
++typedef enum {
++	ISP_CSC_CG_BT601_FULL,
++	ISP_CSC_CG_BT601_LIMITED,
++	ISP_CSC_CG_BT709_FULL,
++	ISP_CSC_CG_BT709_LIMITED,
++	ISP_CSC_CG_USER,
++	ISP_CSC_CG_BUTT,
++} tisp_csc_cg_t;
++
++typedef struct {
++	int CscCoef[9];
++	unsigned char CscOffset[2];
++	unsigned char CscClip[4];
++} tisp_csc_matrix_t;
++
++typedef struct {
++	tisp_csc_cg_t ColorGamut;
++	tisp_csc_matrix_t Matrix;
++	tisp_csc_matrix_t Matrixin;
++} tisp_csc_attr_t;
++
++typedef struct tisp_ccm_attr{
++	char ccm_manual;
++	char sat_en;
++	int32_t ccm[9];
++} tisp_ccm_t;
++
++typedef enum {
++	ISP_ANTIFLICKER_DISABLE_MODE,
++	ISP_ANTIFLICKER_NORMAL_MODE,
++	ISP_ANTIFLICKER_AUTO_MODE,// can reach min it
++	ISP_ANTIFLICKER_BUTT,
++} tisp_antiflicker_mode_t;
++typedef struct {
++	tisp_antiflicker_mode_t mode;
++	uint8_t freq;
++} tisp_anfiflicker_attr_t;
++
++typedef enum {
++	IMPISP_MASK_TYPE_RGB = 0,
++	IMPISP_MASK_TYPE_YUV = 1,
++} mask_value_type_t;
++
++typedef union {
++	struct {
++		unsigned char r_value;
++		unsigned char g_value;
++		unsigned char b_value;
++	} mask_argb;
++	struct {
++		unsigned char y_value;
++		unsigned char u_value;
++		unsigned char v_value;
++	} mask_ayuv;
++} mask_value_t;
++
++struct isp_mask_block_par {
++	unsigned char mask_en;
++	unsigned short mask_pos_top;
++	unsigned short mask_pos_left;
++	unsigned short mask_width;
++	unsigned short mask_height;
++	mask_value_t mask_value;
++};
++
++typedef struct {
++	struct isp_mask_block_par mask_chx[3][4];
++	mask_value_type_t mask_type;
++} tisp_mask_attr_t;
++
++/**
++ * OSD picture atribution
++ */
++typedef struct {
++	uint8_t  osd_enable;    /**< osd enable */
++	uint16_t osd_left;      /**< osd area x value */
++	uint16_t osd_top;       /**< osd area y value */
++	uint16_t osd_width;     /**< osd area width */
++	uint16_t osd_height;    /**< osd area height */
++	char osd_image_path[128];
++	uint16_t osd_stride;    /**< osd stride */
++} tisp_osd_pic_attr_t;
++
++/**
++ * OSD picture type
++ */
++typedef enum {
++	IMP_ISP_PIC_ARGB_1555,      /**< ARGB1555 */
++	IMP_ISP_PIC_ARGB_8888,      /**< ARGB888 */
++} tisp_pic_type_t;
++
++/**
++ * OSD type
++ */
++typedef enum {
++	IMP_ISP_ARGB_TYPE_ARGB = 0,
++	IMP_ISP_ARGB_TYPE_ARBG,
++	IMP_ISP_ARGB_TYPE_AGRB,
++	IMP_ISP_ARGB_TYPE_AGBR,
++	IMP_ISP_ARGB_TYPE_ABRG,
++	IMP_ISP_ARGB_TYPE_ABGR,
++	IMP_ISP_ARGB_TYPE_RGBA = 8,
++	IMP_ISP_ARGB_TYPE_RBGA,
++	IMP_ISP_ARGB_TYPE_GRBA,
++	IMP_ISP_ARGB_TYPE_GBRA,
++	IMP_ISP_ARGB_TYPE_BRGA,
++	IMP_ISP_ARGB_TYPE_BGRA,
++} tisp_argb_type_t;
++
++/**
++ * OSD channel attribution
++ */
++typedef struct {
++	tisp_pic_type_t osd_type;                         /**< OSD picture type */
++	tisp_argb_type_t osd_argb_type;                   /**< OSD argb type */
++	TISP_OPS_MODE osd_pixel_alpha_disable;    /**< OSD pixel alpha disable function enable */
++	tisp_osd_pic_attr_t pic[8];                        /**< OSD picture attribution */
++} tisp_osd_chx_attr_t;
++
++typedef struct {
++	tisp_osd_chx_attr_t osd_chx[2];
++} tisp_osd_attr_t;
++
++/**
++ * Draw window attribution
++ */
++typedef struct {
++	uint8_t  wind_enable;           /**< draw window enable */
++	uint16_t wind_x;                /**< window start pixel in horizental */
++	uint16_t wind_y;                /**< window start pixel in vertical */
++	uint16_t wind_w;                /**< window width */
++	uint16_t wind_h;                /**< window height */
++	mask_value_t wind_color;  /**< window color */
++	uint8_t  wind_line_w;           /**< window line width */
++	uint8_t  wind_alpha;            /**< window alpha */
++} tisp_draw_wind_attr_t;
++
++/**
++ * Draw range attribution
++ */
++typedef struct {
++	uint8_t  rang_enable;              /**< draw range enable */
++	uint16_t rang_x;                   /**< range start pixel in horizental */
++	uint16_t rang_y;                   /**< range start pixel in vertical */
++	uint16_t rang_w;                   /**< range width */
++	uint16_t rang_h;                   /**< range height */
++	mask_value_t rang_color;     /**< range color */
++	uint8_t  rang_line_w;              /**< range line width */
++	uint8_t  rang_alpha;               /**< range alpha(3bit) */
++	uint16_t rang_extend;              /**< range extend */
++} tisp_draw_range_attr_t;
++
++/**
++ * Draw line attribution
++ */
++typedef struct {
++	uint8_t  line_enable;           /**< draw line enable */
++	uint16_t line_startx;           /**< line start pixel in horizental */
++	uint16_t line_starty;           /**< line start pixel in vertical */
++	uint16_t line_endx;             /**< line width */
++	uint16_t line_endy;             /**< line height */
++	mask_value_t line_color;  /**< line color */
++	uint8_t  line_width;            /**< line line width */
++	uint8_t  line_alpha;            /**< line alpha */
++} tisp_draw_line_attr_t;
++
++/**
++ * Draw type
++ */
++typedef enum {
++	TISP_DRAW_LINE,	     /**< Draw line */
++	TISP_DRAW_RANGE,     /**< Draw range */
++	TISP_DRAW_WIND,	     /**< Draw window */
++} tisp_draw_type_t;
++
++/**
++ * Draw unit Attribution
++ */
++typedef struct {
++	tisp_draw_type_t type;               /**< draw type */
++	union {
++		tisp_draw_wind_attr_t wind;   /**< draw window attr */
++		tisp_draw_range_attr_t rang;   /**< draw range attr */
++		tisp_draw_line_attr_t line;   /**< draw line attr */
++	} draw_cfg;                        /**< draw attr */
++} tisp_draw_attr_t;
++
++/**
++ * Draw Attribution for each channel
++ */
++typedef struct {
++	tisp_draw_attr_t draw_chx[2][16];   /**< draw attr for channel0, the max draw num is 16 */
++} tisp_draw_chx_attr_t;
++
++
++/**
++ * awb mode
++ */
++typedef enum {
++	ISP_CORE_WB_MODE_AUTO = 0,			/**< auto mode */
++	ISP_CORE_WB_MODE_MANUAL,			/**< manual mode */
++	ISP_CORE_WB_MODE_DAY_LIGHT,			/**< day light mode */
++	ISP_CORE_WB_MODE_CLOUDY,			/**< cloudy mode */
++	ISP_CORE_WB_MODE_INCANDESCENT,                  /**< incandescent mode */
++	ISP_CORE_WB_MODE_FLOURESCENT,                   /**< flourescent mode */
++	ISP_CORE_WB_MODE_TWILIGHT,			/**< twilight mode */
++	ISP_CORE_WB_MODE_SHADE,				/**< shade mode */
++	ISP_CORE_WB_MODE_WARM_FLOURESCENT,              /**< warm flourescent mode */
++	ISP_CORE_WB_MODE_COLORTEND,			/**< Color Trend Mode */
++} TISPAWBMode;
++
++/**
++ * awb gain
++ */
++typedef struct {
++	uint32_t rgain;     /**< awb r-gain */
++	uint32_t bgain;     /**< awb b-gain */
++} tisp_awb_gain_t;
++
++/**
++ * awb custom mode attribution
++ */
++typedef struct {
++	TISP_OPS_MODE customEn;  /**< awb custom enable */
++	tisp_awb_gain_t gainH;           /**< awb gain on high ct */
++	tisp_awb_gain_t gainM;           /**< awb gain on medium ct */
++	tisp_awb_gain_t gainL;           /**< awb gain on low ct */
++	uint32_t ct_node[4];           /**< awb custom mode nodes */
++} tisp_awb_custom_attr_t;
++
++/**
++ * awb attribution
++ */
++typedef struct isp_core_wb_attr{
++	TISPAWBMode mode;                     /**< awb mode */
++	tisp_awb_gain_t gain_val;			/**< awb gain on manual mode */
++	TISP_OPS_MODE frz;
++	unsigned int ct;                        /**< awb current ct value */
++	tisp_awb_custom_attr_t custom;         /**< awb custom attribution */
++	TISP_OPS_MODE awb_start_en;       /**< awb algo start function enable */
++	tisp_awb_gain_t awb_start;                /**< awb algo start point */
++} tisp_awb_attr_t;
++
++
++typedef struct isp_core_awb_global_statis {
++	tisp_awb_gain_t statis_weight_gain;              /**< awb statistics */
++	tisp_awb_gain_t statis_gol_gain;          /**< awb global statistics */
++} tisp_awb_global_statics_t;
++
++/**
++ * AE scence mode
++ */
++typedef enum {
++	TISP_AE_SCENCE_AUTO,	     /**< auto mode */
++	TISP_AE_SCENCE_DISABLE,	     /**< diable mode */
++	TISP_AE_SCENCE_ROI_ENABLE,	     /**< enable mode */
++	TISP_AE_SCENCE_GLOBAL_ENABLE,	     /**< enable mode */
++	TISP_AE_SCENCE_BUTT,	     /**< effect paramater, parameters have to be less than this value */
++} TISPAEScenceMode;
++
++/**
++ * AE scence mode attr
++ */
++typedef struct {
++	TISPAEScenceMode AeHLCEn;         /**< AE high light depress enable */
++	unsigned char AeHLCStrength;        /**< AE high light depress strength (0 ~ 10) */
++	TISPAEScenceMode AeBLCEn;         /**< AE back light compensation */
++	unsigned char AeBLCStrength;        /**< AE back light compensation strength (0 ~ 10) */
++	TISPAEScenceMode AeTargetCompEn;  /**< AE luma target compensation enable */
++	uint32_t AeTargetComp;              /**< AE luma target compensation strength（0 ~ 255）*/
++	TISPAEScenceMode AeStartEn;       /**< AE start point enable */
++	uint32_t AeStartEv;                 /**< AE start ev value */
++
++	uint32_t luma;                                          /**< AE luma value */
++	uint32_t luma_scence;                                          /**< AE luma value */
++} tisp_ae_scence_attr_t;
++
++typedef enum {
++	ISP_CORE_EXPR_UNIT_LINE,			/**< The unit is integration line */
++	ISP_CORE_EXPR_UNIT_US,				/**< The unit is millisecond */
++} TISPAEIntegrationTimeUnit;
++
++/**
++ * AE exposure info
++ */
++typedef struct {
++	TISPAEIntegrationTimeUnit AeIntegrationTimeUnit;     /**< AE integration time unit */
++	TISP_OPS_TYPE AeMode;				 /**< AE freezen enable */
++	TISP_OPS_TYPE AeIntegrationTimeMode;		 /**< AE integration time manual */
++	TISP_OPS_TYPE AeAGainManualMode;		 /**< AE sensor analog gain manual */
++	TISP_OPS_TYPE AeDGainManualMode;		 /**< AE sensor digital gain manual */
++	TISP_OPS_TYPE AeIspDGainManualMode;		 /**< AE ISP digital gain manual */
++	uint32_t AeIntegrationTime;                            /**< AE integration time value */
++	uint32_t AeAGain;                                      /**< AE sensor analog gain value */
++	uint32_t AeDGain;                                      /**< AE sensor digital gain value */
++	uint32_t AeIspDGain;                                   /**< AE ISP digital gain value */
++
++	TISP_OPS_TYPE AeMinIntegrationTimeMode;		 /**< Reserve */
++	TISP_OPS_TYPE AeMinAGainMode;			 /**< AE min analog gain enable */
++	TISP_OPS_TYPE AeMinDgainMode;			 /**< Reserve */
++	TISP_OPS_TYPE AeMinIspDGainMode;		 /**< Reserve */
++	TISP_OPS_TYPE AeMaxIntegrationTimeMode;		 /**< AE max integration time enable */
++	TISP_OPS_TYPE AeMaxAGainMode;			 /**< AE max sensor analog gain enable */
++	TISP_OPS_TYPE AeMaxDgainMode;			 /**< AE max sensor digital gain enable */
++	TISP_OPS_TYPE AeMaxIspDGainMode;		 /**< AE max isp digital gain enable */
++	uint32_t AeMinIntegrationTime;                         /**< AE min integration time */
++	uint32_t AeMinAGain;                                   /**< AE min sensor analog gain */
++	uint32_t AeMinDgain;                                   /**< AE min sensor digital gain */
++	uint32_t AeMinIspDGain;                                /**< AE min isp digital gain */
++	uint32_t AeMaxIntegrationTime;                         /**< AE max integration time */
++	uint32_t AeMaxAGain;                                   /**< AE max sensor analog gain */
++	uint32_t AeMaxDgain;                                   /**< AE max sensor digital gain */
++	uint32_t AeMaxIspDGain;                                /**< AE max isp digital gain */
++
++	/* WDR模�下短帧的AE 手动模�属性*/
++	TISP_OPS_TYPE AeShortMode;			  /**< AE freezen enable */
++	TISP_OPS_TYPE AeShortIntegrationTimeMode;	  /**< AE integration time manual */
++	TISP_OPS_TYPE AeShortAGainManualMode;		  /**< AE sensor analog gain manual */
++	TISP_OPS_TYPE AeShortDGainManualMode;		  /**< AE sensor digital gain manual */
++	TISP_OPS_TYPE AeShortIspDGainManualMode;	  /**< AE ISP digital gain manual */
++	uint32_t AeShortIntegrationTime;                        /**< AE integration time value */
++	uint32_t AeShortAGain;                                  /**< AE sensor analog gain value */
++	uint32_t AeShortDGain;                                  /**< AE sensor digital gain value */
++	uint32_t AeShortIspDGain;                               /**< AE ISP digital gain value */
++
++	TISP_OPS_TYPE AeShortMinIntegrationTimeMode;	  /**< Reserve */
++	TISP_OPS_TYPE AeShortMinAGainMode;		  /**< AE min analog gain enable */
++	TISP_OPS_TYPE AeShortMinDgainMode;		  /**< Reserve */
++	TISP_OPS_TYPE AeShortMinIspDGainMode;		  /**< Reserve */
++	TISP_OPS_TYPE AeShortMaxIntegrationTimeMode;	  /**< AE max integration time enable */
++	TISP_OPS_TYPE AeShortMaxAGainMode;		  /**< AE max sensor analog gain enable */
++	TISP_OPS_TYPE AeShortMaxDgainMode;		  /**< AE max sensor digital gain enable */
++	TISP_OPS_TYPE AeShortMaxIspDGainMode;		  /**< AE max isp digital gain enable */
++	uint32_t AeShortMinIntegrationTime;                     /**< AE min integration time */
++	uint32_t AeShortMinAGain;                               /**< AE min sensor analog gain */
++	uint32_t AeShortMinDgain;                               /**< AE min sensor digital gain */
++	uint32_t AeShortMinIspDGain;                            /**< AE min isp digital gain */
++	uint32_t AeShortMaxIntegrationTime;                     /**< AE max integration time */
++	uint32_t AeShortMaxAGain;                               /**< AE max sensor analog gain */
++	uint32_t AeShortMaxDgain;                               /**< AE max sensor digital gain */
++	uint32_t AeShortMaxIspDGain;                            /**< AE max isp digital gain */
++
++	uint32_t TotalGainDb;                                   /**< AE total gain, unit is dB */
++	uint32_t TotalGainDbShort;                                   /**< AE total gain, unit is dB */
++	uint32_t ExposureValue;                                 /**< AE exposure value(integration time x again x dgain) */
++	uint32_t EVLog2;                                        /**< AE exposure value cal by log */
++} tisp_ae_exprinfo_t;
++
++/**
++ * AE statistics info
++ */
++typedef struct {
++	unsigned short ae_hist_5bin[5];     /**< AE hist bin value [0 ~ 65535] */
++	uint32_t ae_hist_256bin[256];       /**< AE hist bin value, is the true value of pixels num each bin */
++	tisp_zone_info_t ae_statis;         /**< AE statistics info */
++}  __attribute__((packed, aligned(1))) tisp_ae_statis_info_t;
++
++/**
++ * AF statistics info
++ */
++typedef struct {
++	tisp_zone_info_t Af_Fir0;
++	tisp_zone_info_t Af_Fir1;
++	tisp_zone_info_t Af_Iir0;
++	tisp_zone_info_t Af_Iir1;
++	tisp_zone_info_t Af_YSum;
++	tisp_zone_info_t Af_HighLumaCnt;
++} tisp_af_statis_info_t;
++
++/**
++ * AE weight attribute
++ */
++typedef struct {
++	TISP_OPS_MODE roi_enable;     /**< roi weight set enable */
++	TISP_OPS_MODE weight_enable;  /**< global weight set enable */
++	tisp_3a_weight_t ae_roi;                /**< roi weight value (0 ~ 8) */
++	tisp_3a_weight_t ae_weight;             /**< global weight value (0 ~ 8)*/
++} tisp_ae_weight_t;
++
++/**
++ * statistics color domain
++ */
++typedef enum {
++	IMP_ISP_HIST_ON_RAW,   /**< Raw Domain */
++	IMP_ISP_HIST_ON_YUV,   /**< YUV Domain */
++} TISPHistDomain;
++
++/**
++ * statistics hist area struct
++ */
++typedef struct {
++	unsigned int start_h;   /**< start pixel in the horizontal */
++	unsigned int start_v;   /**< start pixel in the vertical */
++	unsigned char node_h;   /**< the statistics node num in the horizontal */
++	unsigned char node_v;   /**< the statistics node num in the vertical */
++} tisp_statis_location_t;
++
++/**
++ * AE statistics attribution
++ */
++typedef struct {
++	TISP_OPS_MODE ae_statis_en;
++	tisp_statis_location_t local;   /**< AE statistics location */
++	TISPHistDomain hist_domain;   /**< AE Hist statistics color domain */
++	unsigned char histThresh[4];    /**< AE Hist Thresh */
++} tisp_ae_statis_attr_t;
++
++/**
++ * AWB statistics value attribution
++ */
++typedef enum {
++	IMP_ISP_AWB_ORIGIN,    /**< Original value */
++	IMP_ISP_AWB_LIMITED,   /**< Limited statistics value */
++} TISPAWBStatisMode;
++
++/**
++ * AWB statistics attribution
++ */
++typedef struct {
++	TISP_OPS_MODE awb_statis_en;
++	tisp_statis_location_t local;  /**< AWB Statistic area */
++	TISPAWBStatisMode mode;      /**< AWB Statistic mode */
++} tisp_awb_statis_attr_t;
++
++/**
++ * AF statistics attribution
++ */
++typedef struct {
++	TISP_OPS_MODE af_statis_en;
++	tisp_statis_location_t local;           /**< AF statistics area */
++	unsigned char af_metrics_shift;         /**< Metrics scaling factor 0x0 is default*/
++	unsigned short af_delta;                /**< AF statistics low pass fliter weight [0 ~ 64]*/
++	unsigned short af_theta;                /**< AF statistics high pass fliter weight [0 ~ 64]*/
++	unsigned short af_hilight_th;           /**< AF high light threshold [0 ~ 255]*/
++	unsigned short af_alpha_alt;            /**< AF statistics H and V direction weight [0 ~ 64]*/
++	unsigned short af_belta_alt;            /**< AF statistics H and V direction weight [0 ~ 64]*/
++} tisp_af_statis_attr_t;
++
++/**
++ * Statistics info attribution
++ */
++typedef struct {
++	tisp_ae_statis_attr_t ae;      /**< AE statistics info attr */
++	tisp_awb_statis_attr_t awb;    /**< AWB statistics info attr */
++	tisp_af_statis_attr_t af;      /**< AF statistics info attr */
++} tisp_statis_config_t;
++
++typedef enum {
++	IMP_ISP_MODULE_SINTER = 0, /**< 2D�噪下标 */
++	IMP_ISP_MODULE_TEMPER,     /**< 3D�噪下标 */
++	IMP_ISP_MODULE_DRC,        /**< 数字宽动�下标 */
++	IMP_ISP_MODULE_DPC,        /**< 动�去�点下标 */
++	IMP_ISP_MODULE_BUTT,       /**< 用于判断�数有效性的值，必须大于此值 */
++} IMPISPModuleRatioArrayList;
++
++typedef struct {
++	TISP_OPS_MODE en;   /**< module ratio enable */
++	uint8_t ratio;            /**< module ratio value. The default value is 128, more than 128 (increase strength), and less than 128 (decrease strength) */
++} tisp_ratio_unit_t;
++
++/**
++ * ISP module ratio Attrbution
++ */
++typedef struct {
++	tisp_ratio_unit_t ratio_attr[16]; /**< module ratio attr */
++} tisp_module_ratio_t;
++
++typedef struct {
++	uint32_t af_metrics;        /**< AF Main metrics */
++	uint32_t af_metrics_alt;    /**< AF second metrics */
++	uint8_t af_frame_num;		/**< AF frame num */
++} tisp_af_metric_info_t;
++
++typedef struct {
++	TISP_OPS_MODE enable;
++	unsigned int left;
++	unsigned int top;
++	unsigned int right;
++	unsigned int bottom;
++	unsigned int target;
++} tisp_face_t;
++
++typedef enum {
++	TISP_WDR_OUTPUT_MODE_FUS_FRAME,
++	TISP_WDR_OUTPUT_MODE_LONG_FRAME,
++	TISP_WDR_OUTPUT_MODE_SHORT_FRAME,
++	TISP_WDR_OUTPUT_MODE_BUTT,
++} tisp_wdr_output_mode_t;
++
++typedef struct {
++	TISPAEIntegrationTimeUnit AeIntegrationTimeUnit;  /**< AE�光时间�� */
++	uint32_t AeIntegrationTime;                         /**< AE手动模�下的�光值 */
++	uint32_t AeAGain;                                   /**< AE Sensor 模拟增益值，��是�数 x 1024 */
++	uint32_t AeDGain;                                   /**< AE Sensor数字增益值，��是�数 x 1024 */
++	uint32_t AeIspDGain;                                /**< AE ISP 数字增益值，���数 x 1024*/
++
++	uint32_t AeMinIntegrationTime;                      /**< AE最��光时间 */
++	uint32_t AeMinAGain;                                /**< AE最�sensor模拟增益 */
++	uint32_t AeMinDgain;                                /**< AE最�sensor数字增益 */
++	uint32_t AeMinIspDGain;                             /**< AE最�ISP数字增益 */
++	uint32_t AeMaxIntegrationTime;                      /**< AE最大�光时间 */
++	uint32_t AeMaxAGain;                                /**< AE最大sensor模拟增益 */
++	uint32_t AeMaxDgain;                                /**< AE最大sensor数字增益 */
++	uint32_t AeMaxIspDGain;                             /**< AE最大ISP数字增益 */
++
++	/* WDR模�下短帧的AE 手动模�属性*/
++	uint32_t AeShortIntegrationTime;                    /**< AE手动模�下的�光值 */
++	uint32_t AeShortAGain;                              /**< AE Sensor 模拟增益值，��是�数 x 1024 */
++	uint32_t AeShortDGain;                              /**< AE Sensor数字增益值，��是�数 x 1024 */
++	uint32_t AeShortIspDGain;                           /**< AE ISP 数字增益值，���数 x 1024*/
++
++	uint32_t AeShortMinIntegrationTime;                 /**< AE最��光时间 */
++	uint32_t AeShortMinAGain;                           /**< AE最�sensor模拟增益 */
++	uint32_t AeShortMinDgain;                           /**< AE最�sensor数字增益 */
++	uint32_t AeShortMinIspDGain;                        /**< AE最�ISP数字增益 */
++	uint32_t AeShortMaxIntegrationTime;                 /**< AE最大�光时间 */
++	uint32_t AeShortMaxAGain;                           /**< AE最大sensor模拟增益 */
++	uint32_t AeShortMaxDgain;                           /**< AE最大sensor数字增益 */
++	uint32_t AeShortMaxIspDGain;                        /**< AE最大ISP数字增益 */
++	uint32_t fps;       /**< sensor 帧率 */
++	tisp_ae_statis_attr_t AeStatis;
++} tisp_ae_algo_init_t;
++
++typedef struct {
++	tisp_ae_statis_info_t ae_info;
++	TISPAEIntegrationTimeUnit AeIntegrationTimeUnit;  /**< AE�光时间�� */
++	uint32_t AeIntegrationTime;                         /**< AE手动模�下的�光值 */
++	uint32_t AeAGain;                                   /**< AE Sensor 模拟增益值，��是�数 x 1024 */
++	uint32_t AeDGain;                                   /**< AE Sensor数字增益值，��是�数 x 1024 */
++	uint32_t AeIspDGain;                                /**< AE ISP 数字增益值，���数 x 1024*/
++	uint32_t AeShortIntegrationTime;                    /**< AE手动模�下的�光值 */
++	uint32_t AeShortAGain;                              /**< AE Sensor 模拟增益值，��是�数 x 1024 */
++	uint32_t AeShortDGain;                              /**< AE Sensor数字增益值，��是�数 x 1024 */
++	uint32_t AeShortIspDGain;                           /**< AE ISP 数字增益值，���数 x 1024*/
++
++	uint32_t Wdr_mode;
++	struct isp_core_sensor_attr sensor_attr;
++}  __attribute__((packed, aligned(1))) tisp_ae_algo_info_t;
++
++typedef struct {
++	uint32_t change;
++	TISPAEIntegrationTimeUnit AeIntegrationTimeUnit;  /**< AE�光时间�� */
++	uint32_t AeIntegrationTime;                         /**< AE手动模�下的�光值 */
++	uint32_t AeAGain;                                   /**< AE Sensor 模拟增益值，��是�数 x 1024 */
++	uint32_t AeDGain;                                   /**< AE Sensor数字增益值，��是�数 x 1024 */
++
++	uint32_t AeIspDGain;                                /**< AE ISP 数字增益值，���数 x 1024*/
++	uint32_t AeShortIntegrationTime;                    /**< AE手动模�下的�光值 */
++	uint32_t AeShortAGain;                              /**< AE Sensor 模拟增益值，��是�数 x 1024 */
++	uint32_t AeShortDGain;                              /**< AE Sensor数字增益值，��是�数 x 1024 */
++	uint32_t AeShortIspDGain;                           /**< AE ISP 数字增益值，���数 x 1024*/
++
++	uint32_t luma;                         /**< AE Luma值 */
++	uint32_t luma_scence;                  /**< AE 场景Luma值 */
++} tisp_ae_algo_attr_t;
++
++typedef struct {
++	uint32_t version;
++	int vinum;
++	tisp_ae_algo_init_t AeInitAttr;
++} tisp_ae_algo_init_self_t;
++
++typedef struct {
++	uint32_t version;
++	int vinum;
++	tisp_ae_algo_info_t Aeinfo;
++} __attribute__((packed, aligned(1))) tisp_ae_algo_info_self_t;
++
++typedef struct {
++	uint32_t version;
++	int vinum;
++	tisp_ae_algo_attr_t AeAttr;
++} tisp_ae_algo_attr_self_t;
++
++typedef enum {
++	IMPISP_AE_NOTIFY_FPS_CHANGE,
++} tisp_ae_algo_notify_t;
++
++typedef struct {
++	void *priv_data;
++	int (*open)(void *priv_data, tisp_ae_algo_init_t AeInitAttr);
++	void (*close)(void *priv_data);
++	void (*handle)(void *priv_data, const tisp_ae_algo_info_t *AeInfo, tisp_ae_algo_attr_t *AeAttr);
++	int (*notify)(void *priv_data, tisp_ae_algo_notify_t notify, void* data);
++} tisp_ae_algo_func_t;
++
++typedef struct {
++	tisp_awb_statis_attr_t AwbStatis;
++} tisp_awb_algo_init_t;
++
++typedef struct {
++	uint32_t cur_r_gain;
++	uint32_t cur_b_gain;
++	uint32_t r_gain_statis;
++	uint32_t b_gain_statis;
++	uint32_t r_gain_wei_statis;
++	uint32_t b_gain_wei_statis;
++	tisp_wb_statis_info_t awb_statis;
++}__attribute__((packed, aligned(1))) tisp_awb_algo_info_t;
++
++typedef struct {
++	uint32_t change;
++	uint32_t r_gain;
++	uint32_t b_gain;
++	uint32_t ct;
++} tisp_awb_algo_attr_t;
++
++typedef enum {
++	IMPISP_AWB_NOTIFY_MODE_CHANGE,
++} tisp_awb_algo_notify_t;
++
++typedef struct {
++	uint32_t version;
++	int vinum;
++	tisp_awb_algo_init_t AwbInitAttr;
++} tisp_awb_algo_init_self_t;
++
++typedef struct {
++	uint32_t version;
++	int vinum;
++	tisp_awb_algo_info_t Awbinfo;
++} __attribute__((packed, aligned(1))) tisp_awb_algo_info_self_t;
++
++typedef struct {
++	uint32_t version;
++	int vinum;
++	tisp_awb_algo_attr_t AwbAttr;
++} tisp_awb_algo_attr_self_t;
++
++typedef struct {
++	void *priv_data;
++	int (*open)(void *priv_data, tisp_awb_algo_init_self_t *AwbInitAttr);
++	void (*close)(void *priv_data);
++	void (*handle)(void *priv_data, const tisp_awb_algo_info_self_t *AwbInfo, tisp_awb_algo_attr_self_t *AwbAttr);
++	int (*notify)(void *priv_data, tisp_awb_algo_notify_t notify, void *data);
++} tisp_awb_algo_func_t;
++
++typedef struct {
++	char version[8];
++	char rbpath[64];
++	uint32_t dstatus;
++	uint32_t nstatus;
++} tisp_show_bin;
++
++typedef struct {
++	unsigned char saturation[3];
++	unsigned char contrast[3];
++	unsigned char sharpness[3];
++	unsigned char brightness[3];
++	unsigned char hue[3];
++	tisp_ae_exprinfo_t ae_info[3];
++	tisp_ae_scence_attr_t ae_scence[3];
++	tisp_module_ratio_t module_ratio[3];
++	tisp_statis_config_t stattis_config[2];
++	tisp_awb_attr_t awb_attr[3];
++	tisp_ae_weight_t ae_weight[3];
++	tisp_awb_custom_attr_t awb_custom[3];
++	tisp_anfiflicker_attr_t flicker_attr[3];
++	tisp_show_bin swbin[2];
++} tisp_core_tuning_attr;
++
++typedef struct {
++	TISP_OPS_MODE enable;
++	unsigned char bname[64];
++} tisp_bin_t;
++
++typedef struct {
++	TISP_OPS_MODE enable;
++	uint8_t lsize;
++	uint32_t fmark;
++} tisp_frame_drop_t;
++
++typedef struct {
++	uint8_t vinum;
++	tisp_frame_drop_t fdrop[3];
++} tisp_frame_drop_attr_t;
++
++int tisp_enable_tuning(void);
++void tisp_disable_tuning(void);
++tisp_core_tuning_attr* tisp_get_tuning(void);
++
++int32_t tisp_day_or_night_s_ctrl(int vinum, TISP_MODE_DN_E dn);
++TISP_MODE_DN_E tisp_day_or_night_g_ctrl(int vinum);
++int tisp_set_fps(int vinum, int fps);
++
++int tisp_ae_face_get(int vinum, tisp_face_t *attr);
++int tisp_ae_face_set(int vinum, tisp_face_t *attr);
++int tisp_awb_face_get(int vinum, tisp_face_t *attr);
++int tisp_awb_face_set(int vinum, tisp_face_t *attr);
++void tisp_set_brightness(int vinum, unsigned char brightness);
++void tisp_set_sharpness(int vinum, unsigned char sharpness);
++void tisp_set_saturation(int vinum, unsigned char saturation);
++void tisp_set_contrast(int vinum, unsigned char contrast);
++int tisp_set_csc_attr(int vinum, tisp_csc_attr_t *attr);
++void tisp_get_csc_attr(int vinum, tisp_csc_attr_t *attr);
++int tisp_s_ccm_attr(int vinum, tisp_ccm_t *ccm_attr);
++int tisp_g_ccm_attr(int vinum, tisp_ccm_t *ccm_attr);
++int tisp_s_Gamma(int vinum, tisp_gamma_t *gammas);
++int tisp_g_Gamma(int vinum, tisp_gamma_t *gammag);
++void tisp_s_module_control(int vinum, tisp_module_control_t top);
++void tisp_g_module_control(int vinum, tisp_module_control_t *top);
++void tisp_set_bcsh_hue(int vinum, unsigned char hue);
++int tisp_s_antiflick(int vinum, tisp_anfiflicker_attr_t *attr);
++int tisp_g_antiflick(int vinum, tisp_anfiflicker_attr_t *attr);
++void tisp_hv_flip_enable(int vinum, unsigned char en);
++void tisp_hv_flip_get(unsigned char *en);
++int tisp_s_autozoom_control(int vinum, tisp_autozoom_attr_t *autozoom_attr);
++int tisp_g_autozoom_control(int vinum, tisp_autozoom_attr_t *autozoom_attr);
++int tisp_s_mscaler_mask_attr(int vinum, tisp_mask_attr_t *attr);
++int tisp_g_mscaler_mask_attr(int vinum, tisp_mask_attr_t *attr);
++int tisp_s_osd_attr(int vinum, tisp_osd_attr_t *attr);
++int tisp_g_osd_attr(int vinum, tisp_osd_attr_t *attr);
++int tisp_s_draw_attr(int vinum, tisp_draw_chx_attr_t *attr);
++int tisp_g_draw_attr(int vinum, tisp_draw_chx_attr_t *attr);
++int tisp_s_ae_scence_attr(int vinum, tisp_ae_scence_attr_t *attr);
++int tisp_g_ae_scence_attr(int vinum, tisp_ae_scence_attr_t *attr);
++int tisp_g_af_metric_attr(int vinum, tisp_af_metric_info_t *metrics);
++int tisp_g_ae_exprinfo_attr(int vinum, tisp_ae_exprinfo_t *attr);
++
++int tisp_s_wdr_en(int vinum, int enable);
++int tisp_g_wdr_en(int *enable);
++void wdr_init_mine(void);
++int tisp_s_af_weight_attr(int vinum, tisp_3a_weight_t *attr);
++int tisp_g_af_weight_attr(int vinum, tisp_3a_weight_t *attr);
++int tisp_s_awb_weight_attr(int vinum, tisp_3a_weight_t *attr);
++int tisp_g_awb_weight_attr(int vinum, tisp_3a_weight_t *attr);
++int tisp_g_awb_attr(int vinum, tisp_awb_attr_t *attr);
++int tisp_s_awb_attr(int vinum, tisp_awb_attr_t *attr);
++int tisp_g_awb_statis_attr(int vinum, tisp_wb_statis_info_t *attr);
++int tisp_g_awb_global_statis_attr(int vinum, tisp_awb_global_statics_t *attr);
++int tisp_s_ae_exprinfo_attr(int vinum, tisp_ae_exprinfo_t *attr);
++int tisp_g_ae_statis_attr(int vinum, tisp_ae_statis_info_t *attr);
++int tisp_g_af_statis_attr(int vinum, tisp_af_statis_info_t *attr);
++int tisp_s_ae_weight_attr(int vinum, tisp_ae_weight_t *attr);
++int tisp_g_ae_weight_attr(int vinum, tisp_ae_weight_t *attr);
++int tisp_s_statis_config_attr(int vinum, tisp_statis_config_t *attr);
++int tisp_g_statis_config_attr(int vinum, tisp_statis_config_t *attr);
++int tisp_s_module_ratio_attr(int vinum, tisp_module_ratio_t *attr);
++int tisp_g_module_ratio_attr(int vinum, tisp_module_ratio_t *attr);
++int tisp_switch_bin(int vinum, tisp_bin_t *attr);
++int tisp_core_switch_bin(int num, tisp_bin_t *attr);
++void tisp_msca_Shd_ctrl(int vinum, int omd_index);
++uint32_t tisp_msca_state(void);
++void tisp_ae_algo_handle(int vinum, tisp_ae_algo_attr_self_t *ae_attr);
++void tisp_ae_algo_init(int vinum, int enable, tisp_ae_algo_init_self_t *ae_init);
++void tisp_awb_algo_handle(int vinum, tisp_awb_algo_attr_self_t *awb_attr);
++void tisp_awb_algo_init(int vinum, int enable, tisp_awb_algo_init_self_t *awb_init);
++int tisp_get_antiflicker_step(int vinum, uint16_t *gdeflick_lut, uint16_t *gnodes);
++void tisp_get_ae_tgain(int vinum, unsigned int *tgain);
++void tisp_ae_algo_deinit(int vinum);
++void tisp_awb_algo_deinit(int vinum);
++int32_t tisp_set_wdr_output_mode(int vinum, tisp_wdr_output_mode_t *mode);
++int32_t tisp_get_wdr_output_mode(int vinum, tisp_wdr_output_mode_t *mode);
++int32_t tisp_set_frame_drop(int vinum, int chx, tisp_frame_drop_t *tfd);
++int32_t tisp_get_frame_drop(int vinum, int chx, tisp_frame_drop_t *tfd);
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/inc/tiziano-isp.h b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/inc/tiziano-isp.h
+new file mode 100644
+index 000000000..79ebf4315
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/inc/tiziano-isp.h
+@@ -0,0 +1,257 @@
++#ifndef __TIZIANO_ISP_H__
++#define __TIZIANO_ISP_H__
++
++#include <txx-funcs.h>
++
++typedef enum {
++	TISP_OPS_MODE_DISABLE,			/**< DISABLE mode of the current module */
++	TISP_OPS_MODE_ENABLE,			/**< ENABLE mode of the current module */
++	TISP_OPS_MODE_BUTT,			/**< effect paramater, parameters have to be less than this value*/
++} TISP_OPS_MODE;
++
++/**
++ * ISP Function Mode
++ */
++typedef enum {
++	TISP_OPS_TYPE_AUTO,			/**< AUTO mode of the current module*/
++	TISP_OPS_TYPE_MANUAL,			/**< MANUAL mode of the current module*/
++	TISP_OPS_TYPE_BUTT,			/**< effect paramater, parameters have to be less than this value*/
++} TISP_OPS_TYPE;
++
++typedef struct {
++	unsigned int max_again;	//the format is .16
++	unsigned int max_dgain;	//the format is .16
++	unsigned int again;
++	unsigned int dgain;
++	unsigned int fps;
++	unsigned short min_integration_time;
++	unsigned short min_integration_time_native;
++	unsigned short max_integration_time_native;
++	unsigned short integration_time_limit;
++	unsigned int integration_time;
++	unsigned short total_width;
++	unsigned short total_height;
++	unsigned short max_integration_time;
++	unsigned short integration_time_apply_delay;
++	unsigned short again_apply_delay;
++	unsigned short dgain_apply_delay;
++	unsigned short one_line_expr_in_us;
++	unsigned short min_integration_time_short;
++	unsigned short max_integration_time_short;
++	unsigned int integration_time_short;
++	unsigned int max_again_short;	//the format is .16
++	unsigned int again_short;
++	unsigned int max_dgain_short;	//the format is .16
++	unsigned int dgain_short;
++	unsigned short again_short_apply_delay;
++	unsigned short dgain_short_apply_delay;
++	unsigned short integration_time_short_apply_delay;
++} sensor_info_t;
++
++typedef enum {
++	IMPISP_DUALSENSOR_SIGLE_BYPASS_MODE = 0,
++	IMPISP_DUALSENSOR_DUAL_DIRECT_MODE,
++	IMPISP_DUALSENSOR_DUAL_SELECT_MODE,
++	IMPISP_DUALSENSOR_DUAL_SINGLECACHED_MODE,
++	IMPISP_DUALSENSOR_DUAL_ALLCACHED_MODE,
++	IMPISP_DUALSENSOR_MODE_BUTT,
++} dual_sensor_mode_t;
++
++typedef struct {
++	TISP_OPS_MODE en;
++	uint32_t switch_con;
++ 	uint32_t switch_con_num;
++} tisp_dual_sensor_switch_t;
++
++typedef enum {
++	IMPISP_TOTAL_ONE = 1,
++	IMPISP_TOTAL_TWO,
++	IMPISP_TOTAL_THR,
++	IMPISP_TOTAL_BUTT,
++} sensor_num_t;
++
++
++typedef enum{
++	IMPISP_NOT_JOINT = 0,
++	IMPISP_MAIN_ON_THE_LEFT,
++	IMPISP_MAIN_ON_THE_RIGHT,
++	IMPISP_MAIN_ON_THE_ABOVE,
++	IMPISP_MAIN_ON_THE_UNDER,
++	IMPISP_MIAN_JOINT_BUTT,
++} dual_sensor_split_joint;
++
++typedef struct {
++	sensor_num_t sensor_num;
++	dual_sensor_mode_t dual_mode;
++	tisp_dual_sensor_switch_t dual_mode_switch;
++	dual_sensor_split_joint joint_mode;
++} multisensor_mode_t;
++
++typedef struct {
++	int width;
++	int height;
++	int bayer;
++	char sensor[16];
++	sensor_info_t sensor_info;
++	int WdrEn;
++	int DNMode;
++	int sensorId;  //the sensor id:mark the struct for sensor 0/1
++	multisensor_mode_t multi_mode;
++} tisp_init_param_t;
++
++typedef struct {
++	tisp_init_param_t sensor[3];
++	multisensor_mode_t multi_mode;
++} tisp_init_par_t;
++
++typedef struct {
++	int scaler_en;
++	int scaler_width;
++	int scaler_height;
++	int crop_en;
++	int crop_x;
++	int crop_y;
++	int crop_width;
++	int crop_height;
++	int fcrop_en;
++	int fcrop_x;
++	int fcrop_y;
++	int fcrop_width;
++	int fcrop_height;
++} tisp_channel_attr_t;
++
++//ae
++typedef struct {
++	uint32_t tisp_ae_manual;
++	uint32_t tisp_ae_sensor_again;
++	uint32_t tisp_ae_sensor_dgain;
++	uint32_t tisp_ae_sensor_integration_time;
++	uint32_t tisp_ae_isp_dgian;
++	uint32_t tisp_ae_max_sensor_again;
++	uint32_t tisp_ae_max_sensor_dgain;
++	uint32_t tisp_ae_max_sensor_integration_time;
++	uint32_t tisp_ae_max_isp_dgain;
++	uint32_t tisp_ae_ev;
++	uint32_t tisp_ae_tgain_db;
++	uint32_t tisp_ae_again_db;
++	uint32_t tisp_ae_ir;
++	uint32_t tisp_ae_it_manual;
++	uint32_t tisp_ae_ag_manual;
++	uint32_t tisp_ae_dg_manual;
++	uint32_t tisp_ae_it_short_manual;
++	uint32_t tisp_ae_ag_short_manual;
++	uint32_t tisp_ae_sensor_again_short;
++	uint32_t tisp_ae_sensor_integration_time_short;
++	uint32_t tisp_ae_max_sensor_again_short;
++	uint32_t tisp_ae_max_sensor_integration_time_short;
++	uint32_t tisp_ae_max_sensor_dgain_short;
++	uint32_t tisp_ae_max_isp_dgain_short;
++	uint32_t tisp_ae_manual_short;
++	uint32_t tisp_ae_sensor_dgain_short;
++	uint32_t tisp_ae_dg_manual_short;
++	uint32_t tisp_ae_isp_dgian_short;
++	uint32_t tisp_ae_min_sensor_again;
++	uint32_t tisp_ae_min_sensor_dgain;
++	uint32_t tisp_ae_min_sensor_integration_time;
++	uint32_t tisp_ae_min_isp_dgain;
++	uint32_t tisp_ae_min_sensor_again_short;
++	uint32_t tisp_ae_min_sensor_integration_time_short;
++	uint32_t tisp_ae_min_sensor_dgain_short;
++	uint32_t tisp_ae_min_isp_dgain_short;
++	uint32_t tisp_ae_sensor_dg_manual;
++	uint32_t tisp_ae_sensor_dg_short_manual;
++	uint32_t tisp_ae_ev_short;
++	uint32_t tisp_ae_tgain_db_short;
++	uint32_t tisp_ae_again_db_short;
++} tisp_ae_ctrls_t;
++
++typedef struct {
++	uint32_t tisp_wb_manual;
++	uint32_t tisp_wb_rg;
++	uint32_t tisp_wb_bg;
++	uint32_t tisp_wb_rg_sta_global;
++	uint32_t tisp_wb_bg_sta_global;
++	uint32_t tisp_wb_rg_sta_weight;
++	uint32_t tisp_wb_bg_sta_weight;
++} tisp_wb_attr_t;
++
++typedef struct {
++	uint32_t ae_hist[256];
++	uint32_t ae_hist_5bin[5];
++	uint32_t ae_hist_nodes[4];
++	uint8_t ae_hist_hv[2];
++} tisp_ae_sta_t;
++
++typedef struct {
++	unsigned int af_metrics;
++	unsigned int af_metrics_alt;
++	unsigned char af_enable;
++	unsigned char af_metrics_shift;
++	unsigned short af_delta;
++	unsigned short af_theta;
++	unsigned short af_hilight_th;
++	unsigned short af_alpha_alt;
++	unsigned char  af_hstart;
++	unsigned char  af_vstart;
++	unsigned char  af_stat_nodeh;
++	unsigned char  af_stat_nodev;
++	unsigned short  af_belta_alt;
++} tisp_af_attr;
++
++typedef struct {
++	int vinum;
++	char path[64];
++} tx_isp_bin_path;
++
++extern struct completion ae_algo_comp[2];
++extern struct completion ae_algo_close_comp[2];
++extern struct completion awb_algo_comp[2];
++extern struct completion awb_algo_close_comp[2];
++extern tisp_ae_ctrls_t tisp_ae_main_ctrls;
++extern tisp_ae_ctrls_t tisp_ae_sec_ctrls;
++extern tisp_init_par_t tisp_par_info;
++extern int main_day_night_switch;
++extern int event_busy;
++
++int tisp_main_init(tisp_init_param_t *p, char *bpath);
++int tisp_sec_init(tisp_init_param_t *p, char *bpath);
++void tisp_ipc_triger(void);
++int tisp_deinit(int vinum);
++void tisp_stream_on(tisp_init_param_t *p);
++void tisp_process_init(void);
++void tisp_process_deinit(int vinum);
++void tisp_slake_all(void);
++void tisp_activate_all(void);
++
++int tisp_channel_main_start(int chx);
++int tisp_channel_sec_start(int chx);
++int tisp_channel_main_stop(int chx);
++int tisp_channel_sec_stop(int chx);
++int tisp_channel_main_fifo_clear(int chx);
++int tisp_channel_sec_fifo_clear(int chx);
++int tisp_channel_main_attr_set(int chx ,tisp_channel_attr_t * cattr);
++int tisp_channel_sec_attr_set(int chx ,tisp_channel_attr_t * cattr);
++
++int tisp_fw_process(int vinum);
++int tiziano_sync_sensor_attr(tisp_init_param_t *sensor_attr);
++
++void Tzn_Msca_addr_fifo_write(uint8_t sensor_num/*{{{*/
++			      ,uint8_t channel
++			      ,uint32_t phy_y_addr
++			      ,uint32_t phy_c_addr
++	);/*}}}*/
++
++void Tzn_Msca_addr_fifo_read(uint8_t sensor_num/*{{{*/
++			     ,uint8_t channel
++			     ,uint32_t * phy_y_addr
++			     ,uint32_t * phy_c_addr
++	);/*}}}*/
++
++uint8_t Tzn_Msca_addr_fifo_have_read(uint8_t sensor_num/*{{{*/
++				     ,uint8_t channel
++	);/*}}}*/
++
++void tisp_hardware_reg_refresh(int vinum);
++void tisp_lce_get_debug(unsigned int *deinfo);
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/inc/tiziano_sys.h b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/inc/tiziano_sys.h
+new file mode 100644
+index 000000000..fddd7e027
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/inc/tiziano_sys.h
+@@ -0,0 +1,11 @@
++#ifndef __TIZIANO_SYS_H__
++#define __TIZIANO_SYS_H__
++
++extern int system_reg_write(unsigned int reg, unsigned int value);
++extern unsigned int  system_reg_read(unsigned int reg);
++extern int system_lock(void);
++extern int system_unlock(void);
++extern int system_irq_func_main_set(int irq, void *func);
++extern int system_irq_func_sec_set(int irq, void *func);
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/inc/txx-funcs.h b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/inc/txx-funcs.h
+new file mode 100644
+index 000000000..0cc04ccbe
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-core/inc/txx-funcs.h
+@@ -0,0 +1,222 @@
++#ifndef __TXX_DRV_FUNCS_H__
++#define __TXX_DRV_FUNCS_H__
++#include <linux/mm.h>
++#include <linux/fs.h>
++#include <linux/clk.h>
++#include <linux/pwm.h>
++#include <linux/file.h>
++#include <linux/list.h>
++#include <linux/gpio.h>
++#include <linux/time.h>
++#include <linux/sched.h>
++/*#include <linux/delay.h>*/
++#include <linux/module.h>
++#include <linux/debugfs.h>
++#include <linux/kthread.h>
++#include <linux/mfd/core.h>
++#include <linux/mempolicy.h>
++#include <linux/interrupt.h>
++#include <linux/device.h>
++#include <linux/miscdevice.h>
++#include <linux/platform_device.h>
++#include <linux/errno.h>
++#include <linux/i2c.h>
++#include <linux/mutex.h>
++#include <linux/netlink.h>
++#include <linux/completion.h>
++#include <net/netlink.h>
++#include <linux/spi/spi.h>
++#include <linux/proc_fs.h>
++#include <linux/time.h>
++
++// #include <soc/irq.h>
++#include <dt-bindings/interrupt-controller/x2500-irq.h>
++
++#include <soc/base.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/uaccess.h>
++#include <asm/cacheflush.h>
++#include <soc/gpio.h>
++// #include <mach/platform.h>
++/*#include <linux/seq_file.h>*/
++#include <ingenic_proc.h>
++
++#ifndef U16_MAX
++#define U16_MAX 					0xFFFF
++#endif
++
++#define ISP_INFO_LEVEL		0x0
++#define ISP_WARNING_LEVEL	0x1
++#define ISP_ERROR_LEVEL		0x2
++#define ISP_PRINT(level, format, ...)			\
++	isp_printf(level, format, ##__VA_ARGS__)
++#define ISP_INFO(...) ISP_PRINT(ISP_INFO_LEVEL, __VA_ARGS__)
++#define ISP_WARNING(...) ISP_PRINT(ISP_WARNING_LEVEL, __VA_ARGS__)
++#define ISP_ERROR(...) ISP_PRINT(ISP_ERROR_LEVEL, __VA_ARGS__)
++
++//extern unsigned int isp_print_level;
++/*int isp_debug_init(void);*/
++/*int isp_debug_deinit(void);*/
++int isp_printf(unsigned int level, unsigned char *fmt, ...);
++int get_isp_clk(void);
++void *private_vmalloc(unsigned long size);
++void private_vfree(const void *addr);
++
++#define paddr2vaddr(phyaddr) ((void *)((phyaddr) + PAGE_OFFSET - PHYS_OFFSET))
++
++uint8_t private_leading_one_position(const uint32_t in);
++uint32_t private_log2_int_to_fixed(const uint32_t val, const uint8_t out_precision, const uint8_t shift_out);
++uint32_t private_log2_fixed_to_fixed(const uint32_t val, const int in_fix_point, const uint8_t out_fix_point);
++int32_t private_log2_fixed_to_fixed_64(uint64_t val, int32_t in_fix_point, uint8_t out_fix_point);
++uint32_t private_math_exp2(uint32_t val, const unsigned char shift_in, const unsigned char shift_out);
++
++/* platform interfaces */
++int private_platform_driver_register(struct platform_driver *drv);
++void private_platform_driver_unregister(struct platform_driver *drv);
++void private_platform_set_drvdata(struct platform_device *pdev, void *data);
++void *private_platform_get_drvdata(struct platform_device *pdev);
++int private_platform_device_register(struct platform_device *pdev);
++void private_platform_device_unregister(struct platform_device *pdev);
++struct resource *private_platform_get_resource(struct platform_device *dev,
++					       unsigned int type, unsigned int num);
++void private_dev_set_drvdata(struct device *dev, void *data);
++void* private_dev_get_drvdata(const struct device *dev);
++int private_platform_get_irq(struct platform_device *dev, unsigned int num);
++struct resource * private_request_mem_region(resource_size_t start, resource_size_t n,
++					     const char *name);
++void private_release_mem_region(resource_size_t start, resource_size_t n);
++
++void __iomem * private_ioremap(phys_addr_t offset, unsigned long size);
++void private_iounmap(const volatile void __iomem *addr);
++/* interrupt interfaces */
++int private_request_threaded_irq(unsigned int irq, irq_handler_t handler,
++				 irq_handler_t thread_fn, unsigned long irqflags,
++				 const char *devname, void *dev_id);
++void private_enable_irq(unsigned int irq);
++void private_disable_irq(unsigned int irq);
++void private_free_irq(unsigned int irq, void *dev_id);
++
++/* lock and mutex interfaces */
++void __private_spin_lock_irqsave(spinlock_t *lock, unsigned long *flags);
++#define private_spin_lock_irqsave(lock, flags) \
++			__private_spin_lock_irqsave(lock, (&flags));
++void private_spin_unlock_irqrestore(spinlock_t *lock, unsigned long flags);
++void private_spin_lock_init(spinlock_t *lock);
++void private_mutex_lock(struct mutex *lock);
++void private_mutex_unlock(struct mutex *lock);
++void private_raw_mutex_init(struct mutex *lock, const char *name, struct lock_class_key *key);
++
++#define private_mutex_init(mutex) \
++	do {								\
++	static struct lock_class_key __key;		\
++							\
++	private_raw_mutex_init((mutex), #mutex, &__key);		\
++} while (0)
++
++/* clock interfaces */
++struct clk * private_clk_get(struct device *dev, const char *id);
++int private_clk_enable(struct clk *clk);
++void private_clk_disable(struct clk *clk);
++unsigned long private_clk_get_rate(struct clk *clk);
++void private_clk_put(struct clk *clk);
++int private_clk_set_rate(struct clk *clk, unsigned long rate);
++
++struct clk *private_devm_clk_get(struct device *dev, const char *id);
++int private_clk_prepare_enable(struct clk *clk);
++void private_clk_disable_unprepare(struct clk *clk);
++void private_devm_clk_put(struct device *dev, struct clk *clk);
++
++/* i2c interfaces */
++struct i2c_adapter* private_i2c_get_adapter(int nr);
++void private_i2c_put_adapter(struct i2c_adapter *adap);
++int private_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num);
++int private_i2c_register_driver(struct module *, struct i2c_driver *);
++void private_i2c_del_driver(struct i2c_driver *drv);
++struct i2c_client *private_i2c_new_device(struct i2c_adapter *adap, struct i2c_board_info const *info);
++void private_i2c_set_clientdata(struct i2c_client *dev, void *data);
++void *private_i2c_get_clientdata(const struct i2c_client *dev);
++int private_i2c_add_driver(struct i2c_driver *drv);
++void private_i2c_unregister_device(struct i2c_client *client);
++
++/* gpio interfaces */
++int private_gpio_request(unsigned gpio, const char *label);
++void private_gpio_free(unsigned gpio);
++int private_gpio_direction_output(unsigned gpio, int value);
++int private_gpio_direction_input(unsigned gpio);
++int private_gpio_set_debounce(unsigned gpio, unsigned debounce);
++int private_jzgpio_set_func(enum gpio_port port, enum gpio_function func,unsigned long pins);
++// int private_jzgpio_ctrl_pull(enum gpio_port port, int enable_pull,unsigned long pins);
++
++/* system interfaces */
++void private_msleep(unsigned int msecs);
++bool private_capable(int cap);
++unsigned long long private_sched_clock(void);
++bool private_try_module_get(struct module *module);
++int private_request_module(bool wait, const char *fmt, ...);
++void private_module_put(struct module *module);
++
++/* wait interfaces */
++void private_init_completion(struct completion *x);
++void private_complete(struct completion *x);
++int private_wait_for_completion_interruptible(struct completion *x);
++unsigned long private_wait_for_completion_timeout(struct completion *x, unsigned long timeover);
++int private_wait_event_interruptible(wait_queue_head_t *q, int (*state)(void *), void *data);
++void private_wake_up_all(wait_queue_head_t *q);
++void private_wake_up(wait_queue_head_t *q);
++void private_init_waitqueue_head(wait_queue_head_t *q);
++
++/* misc driver interfaces */
++int private_misc_register(struct miscdevice *mdev);
++void private_misc_deregister(struct miscdevice *mdev);
++
++struct proc_dir_entry *private_proc_create_data(const char *name, umode_t mode, struct proc_dir_entry *parent,const struct proc_ops *proc_ops, void *data);
++/* proc file interfaces */
++ssize_t private_seq_read(struct file *file, char __user *buf, size_t size, loff_t *ppos);
++loff_t private_seq_lseek(struct file *file, loff_t offset, int whence);
++int private_single_release(struct inode *inode, struct file *file);
++int private_single_open_size(struct file *file, int (*show)(struct seq_file *, void *),
++			     void *data, size_t size);
++struct proc_dir_entry* private_jz_proc_mkdir(char *s);
++void private_proc_remove(struct proc_dir_entry *de);
++void private_seq_printf(struct seq_file *m, const char *f, ...);
++unsigned long long private_simple_strtoull(const char *cp, char **endp, unsigned int base);
++
++/* kthread interfaces */
++bool private_kthread_should_stop(void);
++struct task_struct* private_kthread_run(int (*threadfn)(void *data), void *data, const char namefmt[]);
++int private_kthread_stop(struct task_struct *k);
++
++void* private_kmalloc(size_t s, gfp_t gfp);
++void private_kfree(void *p);
++long private_copy_from_user(void *to, const void __user *from, long size);
++long private_copy_to_user(void __user *to, const void *from, long size);
++
++/* netlink */
++struct sk_buff* private_nlmsg_new(size_t payload, gfp_t flags);
++struct nlmsghdr *private_nlmsg_put(struct sk_buff *skb, u32 portid, u32 seq,
++					 int type, int payload, int flags);
++int private_netlink_unicast(struct sock *ssk, struct sk_buff *skb,
++		    u32 portid, int nonblock);
++struct sock *private_netlink_kernel_create(struct net *net, int unit, struct netlink_kernel_cfg *cfg);
++void private_sock_release(struct socket *sock);
++
++/* file ops */
++struct file *private_filp_open(const char *filename, int flags, umode_t mode);
++int private_filp_close(struct file *filp, fl_owner_t id);
++ssize_t private_vfs_read(struct file *file, char __user *buf, size_t count, loff_t *pos);
++ssize_t private_vfs_write(struct file *file, const char __user *buf, size_t count, loff_t *pos);
++loff_t private_vfs_llseek(struct file *file, loff_t offset, int whence);
++mm_segment_t private_get_fs(void);
++void private_set_fs(mm_segment_t val);
++void private_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
++			 enum dma_data_direction direction);
++void private_getrawmonotonic(struct timespec64 *ts);
++struct net *private_get_init_net(void);
++
++/* isp driver interface */
++void private_get_isp_priv_mem(unsigned int *phyaddr, unsigned int *size);
++
++/* int private_driver_get_interface(void); */
++
++#endif /*__TXX_DRV_FUNCS_H__*/
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-drv.c b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-drv.c
+new file mode 100644
+index 000000000..59e97dcb0
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-drv.c
+@@ -0,0 +1,451 @@
++#include <linux/clk.h>
++#include <linux/media-bus-format.h>
++#include <linux/media.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_graph.h>
++#include <linux/of_platform.h>
++#include <linux/of_reserved_mem.h>
++#include <linux/pm_runtime.h>
++#include <linux/pm_domain.h>
++#include <linux/slab.h>
++#include <linux/videodev2.h>
++#include <linux/component.h>
++
++#include <media/media-device.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-device.h>
++
++#include "isp-drv.h"
++
++
++static const struct of_device_id ingenic_isp_dt_match[];
++
++static int ingenic_isp_parse_dt(struct ispcam_device * ispcam)
++{
++	struct device *dev = ispcam->dev;
++	struct device_node *node = NULL;
++	struct v4l2_async_notifier *notifier = &ispcam->notifier;
++	struct platform_device *pdev = NULL;
++	struct v4l2_async_subdev *asd = NULL;
++	const char *compatible = NULL;
++	unsigned int cplen = 0;
++	int ret = 0;
++
++
++	for_each_child_of_node(dev->of_node, node) {
++		compatible = of_get_property(node, "compatible", &cplen);
++
++		if(!compatible && (cplen == 0)) {
++			continue;
++		}
++		if(!of_device_is_available(node)) {
++			continue;
++		}
++		pdev = of_platform_device_create(node, NULL,dev);
++		if(!pdev) {
++			printk("failed to populate_platform_device, node->full_name");
++		}
++
++		ispcam->subdevs[ispcam->subdev_num++] = pdev;
++		if(ispcam->subdev_num > MAX_SUB_DEVS) {
++			printk("too many sub platform devices!\n");
++			return -EINVAL;
++		}
++	}
++
++
++	printk("start parse remote-endpoint!\n");
++	asd = devm_kzalloc(dev, MAX_ASYNC_SUBDEVS * sizeof(*notifier->sd->asd), GFP_KERNEL);
++
++	/* 解�endpoint, 远程端点，建立关系, 在下�注册回调，等注册完�通知.创建video_device.*/
++
++	while(
++		(node = of_graph_get_next_endpoint(dev->of_node, node))) {
++		ispcam->isd[ispcam->asd_num].asd = *asd;
++		ispcam->isd[ispcam->asd_num].index = ispcam->asd_num;
++
++		/*TODO: 构建与vep对应的数�结构，存储从dts中传入的数�.*/
++		ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(node), &ispcam->vep[ispcam->asd_num]);
++		if(ret < 0) {
++			of_node_put(node);
++			return -EINVAL;
++		}
++		ispcam->isd[ispcam->asd_num].bus_type = ispcam->vep[ispcam->asd_num].bus_type;
++		ispcam->isd[ispcam->asd_num].parallel = ispcam->vep[ispcam->asd_num].bus.parallel;
++		ispcam->isd[ispcam->asd_num].mipi_csi2 = ispcam->vep[ispcam->asd_num].bus.mipi_csi2;
++
++
++		asd->match.fwnode = fwnode_graph_get_remote_port_parent(of_fwnode_handle(node));
++		asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
++
++		of_node_put(node);
++
++		v4l2_async_notifier_init(&ispcam->notifier);
++
++		ret = v4l2_async_notifier_add_subdev(&ispcam->notifier, asd);
++		if (ret) {
++			fwnode_handle_put(asd->match.fwnode);
++			return ret;
++		}
++
++		fwnode_handle_put(asd->match.fwnode);
++		ispcam->asd_num ++;
++	}
++
++#if 0
++
++	printk("dump subdevs ------------ pdevs:\n");
++	for(i = 0; i < ispcam->subdev_num; i++) {
++		printk("---sudev: %d, name: %s\n", i, ispcam->subdevs[i]->name);
++	}
++
++	printk("dump async subdevs!\n");
++	/*dump of parse subdevs.*/
++	for(i = 0; i < ispcam->asd_num; i++) {
++		asd = &ispcam->isd[i].asd;
++		printk("asd: %d, asd->match.of.node->full_name: %s\n", i, asd->match.fwnode->dev->of_node->full_name);
++	}
++
++#endif
++	return ret;
++}
++
++static int ispcam_asd_notifier_bound(struct v4l2_async_notifier *async,
++                                     struct v4l2_subdev *subdev,
++                                     struct v4l2_async_subdev *asd)
++{
++        struct ispcam_device *ispcam = container_of(async, struct ispcam_device,
++                                              notifier);
++	struct isp_async_device *isd = &ispcam->isd[0];
++
++	struct media_entity *entity = &subdev->entity; /*SOURCE_PAD*/
++	int i = 0;
++	int ret = 0;
++
++	if(entity->num_pads == 0) {
++		dev_err(ispcam->dev, "%s, %d No pad found in async entity(%s)\n", __func__, __LINE__, subdev->name);
++		return -EINVAL;
++	}
++
++	for(i = 0; i < entity->num_pads; i++) {
++		if(entity->pads[i].flags & MEDIA_PAD_FL_SOURCE)
++			break;
++	}
++
++
++	if(i == entity->num_pads) {
++		dev_err(ispcam->dev, "%s, %d, no source pad in async entity (%s)\n", __func__, __LINE__, subdev->name);
++		return -EINVAL;
++	}
++
++	isd->source_pad = i;
++
++	isd->sd = subdev;
++	/*TODO: pass common args from isp host to sensor driver.*/
++	isd->sd->host_priv = NULL;
++
++
++	ret = sensor_device_probe(&ispcam->sensor, ispcam);
++	if(ret < 0) {
++		/*TODO*/
++	}
++
++	dev_info(ispcam->dev, "%s, %d\n", __func__, __LINE__);
++
++	return 0;
++}
++
++static int ispcam_asd_notifier_complete(struct v4l2_async_notifier *async)
++{
++        struct ispcam_device *ispcam = container_of(async, struct ispcam_device,
++                                              notifier);
++
++	int ret = 0;
++	struct media_entity *input = NULL;		/*SINK PAD*/
++	unsigned int flags = 0;
++	unsigned int pad = 0;
++	struct isp_async_device *isd = &ispcam->isd[0];
++
++	dev_info(ispcam->dev, "%s, %d\n", __func__, __LINE__);
++	/*1. 绑定所有的�component,确�所有的�的硬件设备在线, �设备会在里�进行subdev的�始化和注册等�作.*/
++	ret = component_bind_all(ispcam->dev, ispcam);
++	if(ret < 0) {
++		goto err_component_bind_all;
++	}
++
++	/*CSI	<->	VIC*/
++
++	/*VIC	<->	ISP*/
++	//printk("creating link vic to isp\n");
++	if(ispcam->vic && ispcam->isp)
++		ret = media_create_pad_link(
++				&ispcam->vic->sd.entity, VIC_PAD_SOURCE,
++				&ispcam->isp->sd.entity, ISP_PAD_SINK, MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
++
++#ifdef CONFIG_VIC_DMA_ROUTE
++	/*VIC <-> Memory*/
++	if(ispcam->vic)
++		ret = media_create_pad_link(
++				&ispcam->vic->sd.entity, VIC_PAD_SOURCE,
++				&ispcam->vic->ispvideo.video.entity, ISP_VIDEO_PAD_SINK, MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
++#endif
++
++	/*ISP	<->	MSCALER*/
++	//printk("creating link isp to mscaler\n");
++	if(ispcam->isp && ispcam->mscaler)
++		ret = media_create_pad_link(
++				&ispcam->isp->sd.entity, ISP_PAD_SOURCE,
++				&ispcam->mscaler->sd.entity, MSCALER_PAD_SINK, MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
++
++	/*Sensor -> 0]CSI[1 -> 0]VIC[1 -> 0]ISP[1 -> 0]Mscaler[1 -> ]Memory*/
++	//printk("creating link from mscaler to isp-video\n");
++	if(ispcam->mscaler) {
++		ret = media_create_pad_link(
++				&ispcam->mscaler->sd.entity, MSCALER_PAD_SOURCE_CH0,
++				&ispcam->mscaler->ispvideo[0].video.entity, ISP_VIDEO_PAD_SINK, MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
++
++		/*CH1*/
++		if(MSCALER_MAX_CH > 1) {
++			ret = media_create_pad_link(
++					&ispcam->mscaler->sd.entity, MSCALER_PAD_SOURCE_CH1,
++					&ispcam->mscaler->ispvideo[1].video.entity, ISP_VIDEO_PAD_SINK, MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
++		}
++		/*CH2*/
++		if(MSCALER_MAX_CH > 2) {
++			ret = media_create_pad_link(
++					&ispcam->mscaler->sd.entity, MSCALER_PAD_SOURCE_CH2,
++					&ispcam->mscaler->ispvideo[2].video.entity, ISP_VIDEO_PAD_SINK, MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
++		}
++	}
++	if(isd->bus_type == V4L2_MBUS_CSI2_DPHY) {
++		dev_info(ispcam->dev, "creating link csi to vic\n");
++		if(!ispcam->csi) {
++			dev_err(ispcam->dev, "*** Error: MIPI Sensor Found while CSI not enabled in dts ***\n");
++			return -EINVAL;
++		}
++		/*1. connect csi to vic.*/
++		if(ispcam->csi && ispcam->vic)
++			ret = media_create_pad_link(
++					&ispcam->csi->sd.entity, CSI_PAD_SOURCE,
++					&ispcam->vic->sd.entity, VIC_PAD_SINK, MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
++		/*connect to csi pad*/
++		input = &ispcam->csi->sd.entity;
++		flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
++		pad = CSI_PAD_SINK;
++	} else if(isd->bus_type == V4L2_MBUS_PARALLEL) {
++		dev_info(ispcam->dev, "creating link dvp to vic.\n");
++		/*connect to vic dvp port.*/
++		input = &ispcam->vic->sd.entity;
++		pad =	VIC_PAD_SINK;
++		flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
++
++	} else {
++		dev_err(ispcam->dev, "Unsupported v4l2 mbus type.\n");
++		return -EINVAL;
++	}
++	/* connect sensor to csi or vic. */
++	ret = media_create_pad_link(&isd->sd->entity, isd->source_pad,
++			input, pad, MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
++	if(ret < 0) {
++		dev_err(ispcam->dev, "%s, %d, failed to create link from [%s] to [%s]\n",
++				__func__, __LINE__, isd->sd->entity.name, input->name);
++		return -EINVAL;
++	}
++
++	/* Expose all subdev's nodes*/
++	ret = v4l2_device_register_subdev_nodes(&ispcam->v4l2_dev);
++	if (ret) {
++		dev_err(ispcam->mdev.dev,
++				"vimc subdev nodes registration failed (err=%d)\n",
++				ret);
++		goto err_register_subdev_nodes;
++	}
++
++	return 0;
++err_register_subdev_nodes:
++err_component_bind_all:
++	return ret;
++}
++
++
++
++static int ispcam_comp_bind(struct device *master)
++{
++        struct ispcam_device *ispcam = platform_get_drvdata(to_platform_device(master));
++	int ret = 0;
++	struct v4l2_async_notifier_operations ops = {
++		.bound = ispcam_asd_notifier_bound,
++		.complete = ispcam_asd_notifier_complete,
++	};
++	dev_info(master, "master component bind.!\n");
++	media_device_init(&ispcam->mdev);
++
++	/* Register the v4l2 struct */
++	ret = v4l2_device_register(ispcam->mdev.dev, &ispcam->v4l2_dev);
++	if (ret) {
++		dev_err(ispcam->mdev.dev,
++				"v4l2 device register failed (err=%d)\n", ret);
++		return ret;
++	}
++
++	ret = media_device_register(&ispcam->mdev);
++	if(ret < 0) {
++		dev_err(ispcam->mdev.dev, "media device register failed\n");
++		goto err_media_device_register;
++	}
++
++
++
++
++	/*3. 注册异步设备完�通知,确�所有的sensor在线.在完�通知里�进行media_device和link的创建.*/
++	ispcam->notifier.ops = &ops;
++	ret = v4l2_async_notifier_register(&ispcam->v4l2_dev, &ispcam->notifier);
++	if(ret < 0) {
++		goto err_v4l2_async_notifier_register;
++	}
++
++
++	return 0;
++err_v4l2_async_notifier_register:
++err_media_device_register:
++	return ret;
++}
++
++static void ispcam_comp_unbind(struct device *master)
++{
++        struct ispcam_device *ispcam = platform_get_drvdata(to_platform_device(master));
++
++        dev_info(master, "TODO: %p master component unbind!\n", ispcam);
++
++}
++
++
++static const struct component_master_ops ispcam_comp_ops = {
++        .bind = ispcam_comp_bind,
++        .unbind = ispcam_comp_unbind,
++};
++
++
++static int comp_compare(struct device *comp, void *data)
++{
++	return comp == data;
++}
++
++static int ingenic_isp_probe(struct platform_device *pdev)
++{
++
++	struct ispcam_device *ispcam = NULL;
++	struct component_match *match = NULL;
++	const struct of_device_id *of_match;
++	struct ispcam_data *data = NULL;
++	int ret;
++	int i;
++	char *dev_nr = NULL;
++
++	ispcam = kzalloc(sizeof(struct ispcam_device), GFP_KERNEL);
++	if(!ispcam) {
++		pr_err("Failed to alloc ispcam dev [%s]\n", pdev->name);
++		return -ENOMEM;
++	}
++
++	ispcam->dev = &pdev->dev;
++	platform_set_drvdata(pdev, ispcam);
++
++	of_match = of_match_node(ingenic_isp_dt_match, pdev->dev.of_node);
++	if (!of_match){
++		return -ENODEV;
++	}
++
++	data = (struct ispcam_data *)of_match->data;
++	if(data->chip_name)
++		memcpy(ispcam->chip_name, data->chip_name, sizeof(ispcam->chip_name));
++	else
++		return -ENODEV;
++
++	ingenic_isp_parse_dt(ispcam);
++
++	for(i = 0; i < ispcam->subdev_num; i++) {
++		component_match_add(ispcam->dev, &match, comp_compare, &ispcam->subdevs[i]->dev);
++	}
++
++
++	mutex_init(&ispcam->mutex);
++	ispcam->v4l2_dev.mdev = &ispcam->mdev;
++
++	ispcam->mdev.dev = ispcam->dev;
++	strlcpy(ispcam->mdev.model, "ingenic-isp", sizeof(ispcam->mdev.model));
++
++	dev_nr = strchr(pdev->name, '@');
++	if(!dev_nr){
++		dev_err(ispcam->dev, "failed to get dev_nr\n");
++		return -ENODEV;
++	}
++	ispcam->dev_nr = dev_nr[1]-'0';
++
++	/* add self to component */
++	ret = component_master_add_with_match(ispcam->dev, &ispcam_comp_ops, match);
++	if(ret < 0) {
++		dev_err(ispcam->dev, "failed to add component master\n");
++		/*TODO*/
++	}
++
++	ret = of_reserved_mem_device_init(ispcam->dev);
++	if(ret)
++		dev_warn(ispcam->dev, "failed to init reserved mem\n");
++
++	return 0;
++
++
++	return ret;
++}
++
++
++
++static int ingenic_isp_remove(struct platform_device *pdev)
++{
++
++	return 0;
++}
++
++struct ispcam_data ingenic_x2500_camera_data = {
++	.chip_name = "x2500",
++};
++
++
++static const struct of_device_id ingenic_isp_dt_match[] = {
++        { .compatible = "ingenic,x2500-isp-camera", .data = (void *)&ingenic_x2500_camera_data},
++        { }
++};
++
++MODULE_DEVICE_TABLE(of, ingenic_isp_dt_match);
++
++static int __maybe_unused ingenic_isp_drv_suspend(struct platform_device *pdev, pm_message_t state)
++{
++        return 0;
++}
++
++static int __maybe_unused ingenic_isp_drv_resume(struct platform_device *pdev)
++{
++        return 0;
++}
++
++static struct platform_driver ingenic_isp_driver = {
++        .probe = ingenic_isp_probe,
++        .remove = ingenic_isp_remove,
++	.suspend = ingenic_isp_drv_suspend,
++	.resume = ingenic_isp_drv_resume,
++        .driver = {
++                .name = "ingenic-ispdrv",
++                .of_match_table = ingenic_isp_dt_match,
++        },
++};
++
++module_platform_driver(ingenic_isp_driver);
++
++MODULE_ALIAS("platform:ingenic-ispdrv");
++MODULE_DESCRIPTION("ingenic isp subsystem");
++MODULE_AUTHOR("qipengzhen <aric.pzqi@ingenic.com>");
++MODULE_LICENSE("GPL v2");
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-drv.h b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-drv.h
+new file mode 100644
+index 000000000..4f6df6755
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-drv.h
+@@ -0,0 +1,398 @@
++#ifndef __INGENIC_ISP_DRV_H__
++#define __INGENIC_ISP_DRV_H__
++
++#include <linux/clk.h>
++
++#include <media/media-device.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-fwnode.h>
++#include <media/videobuf2-core.h>
++#include <media/videobuf2-v4l2.h>
++
++#include <system_sensor_drv.h>
++#include <tiziano-isp.h>
++#include <tiziano-core-ctrl.h>
++#include "isp-sensor.h"
++
++
++#define 	MAX_SUB_DEVS		5
++#define 	MAX_ASYNC_SUBDEVS	1	/*�个ISP�时最大支�1个sensor.*/
++
++extern unsigned int MAIN_ISP_INDEX;
++extern unsigned int SEC_ISP_INDEX;
++
++struct isp_video_format {
++	const char *name;
++	unsigned int fourcc;
++	unsigned int depth[3];	/*max 3 plane*/
++	unsigned int mbus_code;
++	unsigned int num_planes;
++	enum v4l2_colorspace colorspace;
++};
++
++struct isp_pipeline {
++	struct media_pipeline pipeline;
++};
++
++
++#define to_isp_buffer(buf)      container_of(buf, struct isp_video_buffer, vb2)
++struct isp_video_buffer {
++	struct vb2_v4l2_buffer vb2;
++	struct list_head list_entry;
++	unsigned int uv_offset;	/* 当使用single plane的buffer时,表明uv的�移大�.*/
++};
++
++/*�个mscaler_video_device代表一个数�节点示例, mscaler有三个channel，所有三个video_device.*/
++/*通用video_device， mscaler 的三个channel�以注册, vic也�以注册，所以通称为isp_video_device.*/
++#define ISP_VIDEO_PAD_SINK	0
++#define ISP_VIDEO_NUM_PADS	1
++struct isp_video_device {
++	char *name;
++
++	struct video_device video;
++	struct device *dev;
++	struct isp_video_ctx *ctx;
++
++	struct media_pad pad;
++
++	struct ispcam_device *ispcam;
++
++	void *alloc_ctx;
++	struct vb2_queue *queue;
++	struct mutex queue_lock;
++
++	struct mutex mutex;
++
++	struct mutex stream_lock;
++	struct isp_pipeline pipe;
++
++
++	struct v4l2_format format;
++	struct isp_video_format *(*find_format)(const u32 *pixelformat, const u32 *mbus_code, int index);
++	struct isp_video_format *current_format;
++	const struct isp_video_ops *ops;
++
++	int bypass;	/*bypass isp.*/
++	unsigned int max_buffer_num;	/*max vb2 num*/
++};
++
++struct isp_video_ops {
++	/**/
++	struct isp_video_format *(*find_format)(const u32 *pixelformat, const u32 *mbus_code, int index);
++
++	/*qbuf*/
++	/*called by VIDIOC_QBUF in isp-video.c*/
++	int (*qbuf)(struct isp_video_device *ispvideo, struct isp_video_buffer *isp_buffer);
++};
++
++/* isp-core-tuning*/
++struct isp_core_tuning_ctrl {
++	unsigned int vflip;
++	unsigned int hflip;
++	TISP_MODE_DN_E daynight;
++	int saturation;
++	int brightness;
++	int contrast;
++	int sharpness;
++	char hue;
++};
++
++enum isp_image_tuning_private_cmd_id {
++	IMAGE_TUNING_CID_MODULE_CONTROL = V4L2_CID_PRIVATE_BASE,
++	IMAGE_TUNING_CID_DAY_OR_NIGHT,
++	IMAGE_TUNING_CID_AE_LUMA,
++	IMAGE_TUNING_CID_FACE_AE_CONTROL,
++	IMAGE_TUNING_CID_FACE_AWB_CONTROL,
++	IMAGE_TUNING_CID_SWITCH_BIN,
++	IMAGE_TUNING_CID_SET_DEFAULT_BIN_PATH,
++};
++
++#define CSI_PAD_SINK	0
++#define CSI_PAD_SOURCE	1
++#define CSI_NUM_PADS	2
++struct csi_device {
++	struct device *dev;
++	int irq;
++	void __iomem *iobase;
++	unsigned int phy_base;
++	struct ispcam_device *ispcam;	/*struct ispcam_device*/
++
++	struct v4l2_subdev sd;
++
++	struct media_pad *pads;
++	struct v4l2_subdev_format formats[CSI_NUM_PADS];
++
++	struct clk *gate_clk;
++
++	int reset_index;
++	int enabled;
++
++	int settle_time;
++	struct sensor_info *sensor_info;
++};
++
++
++#define	VIC_PAD_SINK		0
++#define VIC_PAD_SOURCE		1
++#define	VIC_NUM_PADS		2
++struct vic_device {
++	struct device *dev;
++
++	int irq;
++	void __iomem *iobase;
++	struct ispcam_device *ispcam;	/*struct ispcam_device*/
++
++	struct v4l2_subdev sd;
++
++	struct media_pad *pads;
++	struct isp_video_device ispvideo;	/*VIC support video out*/
++	struct v4l2_subdev_format formats[VIC_NUM_PADS];
++
++	unsigned int active_sink_pad;
++
++	struct list_head dma_queued_list;
++	spinlock_t lock;
++	int enabled;
++
++	unsigned int buffer_index;
++	int buffer_count;
++	int stop_flag;
++	int global_reset;
++	int frame_capture_counter;
++
++	unsigned int framenum;
++
++	unsigned int snap_paddr;
++	void* snap_vaddr;
++	struct completion snap_comp;
++
++	unsigned int dma_complete;
++	struct sensor_info *sensor_info;
++};
++
++#define ISP_PAD_SINK	0
++#define ISP_PAD_SOURCE	1
++#define ISP_NUM_PADS	2
++
++#define MDNS_BUF 0
++struct buf_info {
++	dma_addr_t paddr;
++	void *vaddr;
++	unsigned int size;
++};
++
++
++struct isp_device {
++	struct device *dev;
++	int irq;
++	void __iomem *iobase;
++	struct ispcam_device *ispcam;
++	spinlock_t lock;
++
++	void __iomem *cpm_reset;
++	unsigned int bit_sr;
++	unsigned int bit_stp;
++	unsigned int bit_ack;
++
++	struct v4l2_subdev sd;
++
++	struct media_pad *pads;
++	struct v4l2_subdev_format formats[ISP_NUM_PADS];
++
++	struct clk *div_clk;
++	struct clk *gate_clk;
++	struct clk *power_clk;
++
++	multisensor_mode_t multi_mode;
++
++	struct task_struct *process_thread;
++//	tisp_core_t core;
++	int enabled;
++	unsigned int index;
++	unsigned int sensor_id;
++
++	/* IRQ callbacks.*/
++	int (*irq_func_cb[32])(void);
++	void *irq_func_data[32];
++
++	struct buf_info buf_info[3];
++	struct isp_core_tuning_ctrl ctrls;
++	struct sensor_info *sensor_info;
++
++	tx_isp_bin_path bpath;
++};
++
++
++#ifdef CONFIG_MSCA_BDEV
++struct mscaler_backend_device {
++	struct device *dev;
++	struct list_head processing_list;
++	spinlock_t lock;
++	wait_queue_head_t wq;
++
++	struct task_struct *process_thread;
++
++	/* mscaler output fmt. */
++	unsigned int width;
++	unsigned int height;
++	unsigned int fmt;
++	unsigned int ch;	/*which channel this backend device belongs to.*/
++
++	int activated;	/* is bdev activated??*/
++
++	struct ingenic_venc_ctx *ctx;
++};
++#endif
++
++/*MSCALER最大支�3个ch输出，�个ch支���的缩放等级. 这里�使用1个channel.*/
++#define MSCALER_MAX_CH			3
++#define MSCALER_PAD_SINK		0
++#define MSCALER_PAD_SOURCE_CH0		1
++#define MSCALER_PAD_SOURCE_CH1		2
++#define MSCALER_PAD_SOURCE_CH2		3
++#define MSCALER_NUM_PADS		4
++struct mscaler_device {
++	struct device *dev;
++	int irq;
++	void __iomem *iobase;
++	struct ispcam_device *ispcam;
++
++	struct v4l2_subdev sd;
++	struct media_pad *pads;
++
++	struct list_head dma_queued_list[MSCALER_MAX_CH];
++	struct list_head dma_pending_list[MSCALER_MAX_CH];
++
++	struct isp_video_device ispvideo[MSCALER_MAX_CH];
++	/*包�了输入pad和输出pad的format*/
++	struct v4l2_subdev_format formats[MSCALER_NUM_PADS];
++	tisp_channel_attr_t attr[MSCALER_MAX_CH];
++
++	spinlock_t lock;
++
++	unsigned int state[MSCALER_MAX_CH];	/*0: stopped, 1: streaming*/
++	unsigned int framenum[MSCALER_MAX_CH];
++
++	struct kobject *mask_kobj;
++	struct kobject *mask_ch_kobj[MSCALER_MAX_CH];
++
++	unsigned int sensor_id;
++#ifdef CONFIG_MSCA_BDEV
++	struct mscaler_backend_device bdev[MSCALER_MAX_CH];
++#endif
++};
++
++
++/* �个 isp_async_device 代表一个异步注册的 sensor设备. */
++struct isp_async_device {
++	struct v4l2_subdev *sd;
++	struct v4l2_async_subdev asd;
++	int index;
++
++	enum v4l2_mbus_type bus_type;
++	struct v4l2_fwnode_bus_parallel parallel;
++	struct v4l2_fwnode_bus_mipi_csi2 mipi_csi2;
++
++	int enabled;
++
++	unsigned int	source_pad;
++};
++
++struct sensor_device {
++	struct isp_async_device *isd;
++
++	struct ispcam_device *ispcam;
++	struct isp_device *isp;
++
++};
++
++
++
++
++#define to_isp_video_ctx(fh)  container_of(fh, struct isp_video_ctx, fh)
++
++/*every open create one ctx, should only one ctx is running at a time*/
++struct isp_video_ctx {
++	struct isp_video_device *ispvideo;
++
++	struct v4l2_fh	fh;	/*handle*/
++	struct vb2_queue queue;
++	struct v4l2_format format;
++	unsigned int uv_offset;
++	unsigned int payload_size;
++};
++
++#define SUBDEV_PAD_SINK		0
++#define SUBDEV_PAD_SOURCE	1
++#define SUBDEV_NUM_PADS		2
++
++
++struct ispcam_data {
++	char chip_name[32];
++};
++
++struct ispcam_device {
++	struct device *dev;
++	struct platform_device *subdevs[MAX_SUB_DEVS];
++	unsigned int subdev_num;
++	char chip_name[32];
++	int dev_nr;
++	unsigned int sensor_id;
++
++	struct media_device mdev;
++	struct v4l2_device v4l2_dev;
++	struct v4l2_async_notifier notifier;	/*异步通知，用�接收sensor注册完�信�.*/
++
++	/*TODO: 应该�会支�一个sensor, MAX_ASYNC_SUBDEVS 应该为1*/
++	struct isp_async_device	isd[MAX_ASYNC_SUBDEVS];
++	//struct v4l2_async_subdev asd[MAX_ASYNC_SUBDEVS];
++	unsigned int asd_num;		/*实际的async device个数，从endpoint中解�出�的.*/
++	struct v4l2_fwnode_endpoint	vep[MAX_ASYNC_SUBDEVS];	/*�个异步设备对应到一个端点上.*/
++
++	int enabled;
++
++	struct mutex	mutex;
++	struct isp_device 	*isp;
++	struct csi_device 	*csi;
++	struct vic_device 	*vic;
++	struct mscaler_device 	*mscaler;
++	struct sensor_device 	sensor;
++
++};
++
++
++/* isp-video*/
++extern int isp_video_init(struct isp_video_device *ispvideo, char *name, const struct isp_video_ops *ops);
++
++extern int isp_video_cleanup(struct isp_video_device *ispvideo);
++
++extern int isp_video_register(struct isp_video_device *ispvideo, struct v4l2_device *v4l2_dev, int nr);
++
++extern int isp_video_unregister(struct isp_video_device *ispvideo);
++
++static inline struct v4l2_fwnode_bus_parallel *ispcam_get_bus_parallel(struct ispcam_device *ispcam)
++{
++	return &ispcam->isd[0].parallel;
++}
++
++static inline struct v4l2_fwnode_bus_mipi_csi2 *ispcam_get_bus_mipi_csi2(struct ispcam_device *ispcam)
++{
++	return &ispcam->isd[0].mipi_csi2;
++}
++
++/* sensor */
++
++int sensor_device_probe(struct sensor_device *sensor, struct ispcam_device *ispcam);
++
++#ifdef CONFIG_MSCA_BDEV
++/* mscaler backend */
++int ms_bdev_init(struct mscaler_backend_device *ms_bdev);
++
++int ms_bdev_deinit(struct mscaler_backend_device *ms_bdev);
++
++int ms_bdev_qbuf(struct mscaler_backend_device *ms_bdev, struct isp_video_buffer *isp_buffer);
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-regs-x2000.h b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-regs-x2000.h
+new file mode 100755
+index 000000000..410bedd3a
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-regs-x2000.h
+@@ -0,0 +1,1453 @@
++#ifndef TIZIANO_MAP__H
++#define TIZIANO_MAP__H
++#ifndef TIZIANO_BASE
++#define TIZIANO_BASE  0x0
++#endif
++#ifndef TIZIANO_MAN
++#define TIZIANO_MAN 3
++#endif
++
++//============================================================
++// BASE ADDRESS
++//============================================================
++#define    VIC_BASE              (TIZIANO_BASE + 0x10000)
++#define    TOP_BASE              (TIZIANO_BASE + 0x00000)
++#define    IP_BASE               (TIZIANO_BASE + 0x00100)
++#define    DPC_BASE              (TIZIANO_BASE + 0x00200)
++#define    GIB_BASE              (TIZIANO_BASE + 0x00400)
++#define    LSC_BASE              (TIZIANO_BASE + 0x00500)
++#define    AG_BASE               (TIZIANO_BASE + 0x00600)
++#define    AE_BASE               (TIZIANO_BASE + 0x00700)
++#define    AWB_BASE              (TIZIANO_BASE + 0x00800)
++#define    AF_BASE               (TIZIANO_BASE + 0x00900)
++#define    ADR_BASE              (TIZIANO_BASE + 0x00A00)
++#define    IRINT_BASE            (TIZIANO_BASE + 0x00F00)
++#define    DMSC_BASE             (TIZIANO_BASE + 0x01000)
++#define    CCM_BASE              (TIZIANO_BASE + 0x01200)
++#define    DEFOG_BASE            (TIZIANO_BASE + 0x01300)
++#define    CSC_BASE              (TIZIANO_BASE + 0x01700)
++#define    CLM_BASE              (TIZIANO_BASE + 0x01800)
++#define    SP_BASE               (TIZIANO_BASE + 0x01900)
++#define    MDNS_BASE             (TIZIANO_BASE + 0x01B00)
++#define    SDNS_BASE             (TIZIANO_BASE + 0x02000)
++#define    HLDC_BASE             (TIZIANO_BASE + 0x02200)
++#define    MSCA_BASE             (TIZIANO_BASE + 0x02300)
++
++#define    DPC_MEM_BASE          (TIZIANO_BASE + 0x04000)
++#define    LSC_MEM_BASE          (TIZIANO_BASE + 0x06000)
++#define    GIB_MEM_BASE          (TIZIANO_BASE + 0x08000)
++#define    AE_HIST_MEM_BASE      (TIZIANO_BASE + 0x08200)
++#define    R_GAMMA_MEM_BASE      (TIZIANO_BASE + 0x08A00)
++#define    G_GAMMA_MEM_BASE      (TIZIANO_BASE + 0x08C00)
++#define    B_GAMMA_MEM_BASE      (TIZIANO_BASE + 0x08E00)
++#define    DEFOG_MEM_BASE        (TIZIANO_BASE + 0x09000)
++#define    CLM_H_0_MEM_BASE      (TIZIANO_BASE + 0x0A000)
++#define    CLM_H_1_MEM_BASE      (TIZIANO_BASE + 0x0A800)
++#define    CLM_S_0_MEM_BASE      (TIZIANO_BASE + 0x0B000)
++#define    CLM_S_1_MEM_BASE      (TIZIANO_BASE + 0x0B800)
++
++#if 0
++//============================================================
++// VIC
++//============================================================
++#define    VIC_ADDR_CONTROL                       (VIC_BASE + 0x00)
++#define    VIC_ADDR_RESOLUTION                    (VIC_BASE + 0x04)
++#define    VIC_ADDR_FRAME_ECC                     (VIC_BASE + 0x08)
++#define    VIC_ADDR_INTF_TYPE                     (VIC_BASE + 0x0C)
++#define    VIC_ADDR_BT_CFG                        (VIC_BASE + 0x10)
++#define    VIC_ADDR_PCLK_GATE                     (VIC_BASE + 0x1C)
++#define    VIC_ADDR_HOR_PARA0                     (VIC_BASE + 0x20)
++#define    VIC_ADDR_HOR_PARA1                     (VIC_BASE + 0x24)
++#define    VIC_ADDR_VER_PARA0                     (VIC_BASE + 0x30)
++#define    VIC_ADDR_VER_PARA1                     (VIC_BASE + 0x34)
++#define    VIC_ADDR_VER_PARA2                     (VIC_BASE + 0x38)
++#define    VIC_ADDR_VER_PARA3                     (VIC_BASE + 0x3C)
++#define    VIC_ADDR_GLB_CFG                       (VIC_BASE + 0x50)
++#define    VIC_ADDR_AB_VLA                        (VIC_BASE + 0x54)
++#define    VIC_ADDR_HBLK_R                        (VIC_BASE + 0x58)
++#define    VIC_ADDR_VBLK_R                        (VIC_BASE + 0x5C)
++#define    VIC_ADDR_SAV_VALUE0                    (VIC_BASE + 0x60)
++#define    VIC_ADDR_EAV_VALUE0                    (VIC_BASE + 0x64)
++#define    VIC_ADDR_SAV_VALUE1                    (VIC_BASE + 0x68)
++#define    VIC_ADDR_EAV_VALUE1                    (VIC_BASE + 0x6C)
++#define    VIC_ADDR_SAV_VALUE2                    (VIC_BASE + 0x70)
++#define    VIC_ADDR_EAV_VALUE2                    (VIC_BASE + 0x74)
++#define    VIC_ADDR_WORK_STATE                    (VIC_BASE + 0x0090)
++#define    VIC_ADDR_PIX_REG                       (VIC_BASE + 0x0094)
++#define    VIC_ADDR_LINE_REG                      (VIC_BASE + 0x0098)
++#define    VIC_ADDR_OFIFO_CNT                     (VIC_BASE + 0x009C)
++#define    VIC_ADDR_BF_BAR_CTRL                   (VIC_BASE + 0x00A0)
++#define    VIC_ADDR_BF_BAR_BLANK                  (VIC_BASE + 0x00A4)
++#define    VIC_ADDR_AF_BAR_CTRL                   (VIC_BASE + 0x00B0)
++#define    VIC_ADDR_AF_BAR_BLANK                  (VIC_BASE + 0x00B4)
++#define    VIC_ADDR_WHITE_BAR                     (VIC_BASE + 0x00C0)
++#define    VIC_ADDR_BLACK_BAR                     (VIC_BASE + 0x00C4)
++#define    VIC_ADDR_BLUE_BAR                      (VIC_BASE + 0x00C8)
++#define    VIC_ADDR_GREEN_BAR                     (VIC_BASE + 0x00CC)
++#define    VIC_ADDR_RED_BAR                       (VIC_BASE + 0x00D0)
++#define    VIC_ADDR_CYAN_BAR                      (VIC_BASE + 0x00D4)
++#define    VIC_ADDR_YELLOW_BAR                    (VIC_BASE + 0x00D8)
++#define    VIC_ADDR_MAGENTA_BAR                   (VIC_BASE + 0x00DC)
++#define    VIC_ADDR_WHITE_BAR2                    (VIC_BASE + 0x00E0)
++#define    VIC_ADDR_BLACK_BAR2                    (VIC_BASE + 0x00E4)
++#define    VIC_ADDR_BLUE_BAR2                     (VIC_BASE + 0x00E8)
++#define    VIC_ADDR_GREEN_BAR2                    (VIC_BASE + 0x00EC)
++#define    VIC_ADDR_RED_BAR2                      (VIC_BASE + 0x00F0)
++#define    VIC_ADDR_CYAN_BAR2                     (VIC_BASE + 0x00F4)
++#define    VIC_ADDR_YELLOW_BAR2                   (VIC_BASE + 0x00F8)
++#define    VIC_ADDR_MAGENTA_BAR2                  (VIC_BASE + 0x00FC)
++#define    VIC_ADDR_INT_STA                       (VIC_BASE + 0x0100)
++#define    VIC_ADDR_INT_MASK                      (VIC_BASE + 0x0104)
++#define    VIC_ADDR_INT_CLR                       (VIC_BASE + 0x0108)
++#define    VIC_ADDR_DMA_CONFIGURE                 (VIC_BASE + 0x0200)
++#define    VIC_ADDR_DMA_RES_R                     (VIC_BASE + 0x0204)
++#define    VIC_ADDR_DMA_RESET                     (VIC_BASE + 0x0208)
++#define    VIC_ADDR_DMA_Y_CH_BANK_CONTROL         (VIC_BASE + 0x0210)
++#define    VIC_ADDR_DMA_Y_CH_LINE_STRIDE          (VIC_BASE + 0x0214)
++#define    VIC_ADDR_DMA_Y_CH_BANK0_ADDR           (VIC_BASE + 0x0218)
++#define    VIC_ADDR_DMA_Y_CH_BANK1_ADDR           (VIC_BASE + 0x021c)
++#define    VIC_ADDR_DMA_Y_CH_BANK2_ADDR           (VIC_BASE + 0x0220)
++#define    VIC_ADDR_DMA_Y_CH_BANK3_ADDR           (VIC_BASE + 0x0224)
++#define    VIC_ADDR_DMA_Y_CH_BANK4_ADDR           (VIC_BASE + 0x0228)
++#define    VIC_ADDR_DMA_UV_CH_BANK_CONTROL        (VIC_BASE + 0x0230)
++#define    VIC_ADDR_DMA_UV_CH_LINE_STRIDE         (VIC_BASE + 0x0234)
++#define    VIC_ADDR_DMA_UV_CH_BANK0_ADDR          (VIC_BASE + 0x0238)
++#define    VIC_ADDR_DMA_UV_CH_BANK1_ADDR          (VIC_BASE + 0x023c)
++#define    VIC_ADDR_DMA_UV_CH_BANK2_ADDR          (VIC_BASE + 0x0240)
++#define    VIC_ADDR_DMA_UV_CH_BANK3_ADDR          (VIC_BASE + 0x0244)
++#define    VIC_ADDR_DMA_UV_CH_BANK4_ADDR          (VIC_BASE + 0x0248)
++#define    VIC_ADDR_SYFIFO_USED                   (VIC_BASE + 0x0300)
++#define    VIC_ADDR_FR_DONE_CNT                   (VIC_BASE + 0x0304)
++#define    VIC_ADDR_DVP_SIZE                      (VIC_BASE + 0x0308)
++#define    VIC_ADDR_DVP_WORK_STA                  (VIC_BASE + 0x030C)
++
++#endif
++
++//============================================================
++// TOP
++//============================================================
++#define    DPC			(0 << 0)
++#define    GIB			(0 << 1)
++#define    LSC			(0 << 2)
++#define    AWB			(0 << 3)
++#define    ADR			(1 << 4)
++#define    DMS			(0 << 5)
++#define    CCM			(0 << 6)
++#define    GAMMA		(0 << 7)
++#define	   DEFOG		(1 << 8)
++#define    CLM			(0 << 9)
++#define    Y_SHARPEN		(0 << 10)
++#define    MDNS			(0 << 11)
++#define    SDNS			(0 << 12)
++#define    HLDC			(1 << 13)
++#define    TP			(1 << 14)
++#define    FONT			(1 << 15)
++#define    SEL			(0 << 31)
++#define    TIZIANO_BYPASS_INIT (DPC|GIB|LSC|AWB|ADR|DMS|CCM|GAMMA|DEFOG|CLM|Y_SHARPEN|MDNS|SDNS|HLDC|TP|FONT|SEL)
++
++#define    TIZIANO_FM_SIZE				(TOP_BASE + 0X0004)
++#define    TIZIANO_BATER_TYPE				(TOP_BASE + 0X0008)
++#define    TIZAINO_BYPASS_CON				(TOP_BASE + 0X000C)
++#define    TIZIANO_TOP_CON				(TOP_BASE + 0X0010)
++#define    TIZIANO_REG_CON				(TOP_BASE + 0X001C)
++#define    TIZAINO_INT_EN				(TOP_BASE + 0X0080)
++
++#define    TOP_CTRL_ADDR_VERSION                        (TOP_BASE + 0x0000)
++#define    TOP_CTRL_ADDR_FM_SIZE                        (TOP_BASE + 0x0004)
++#define    TOP_CTRL_ADDR_BAYER_TYPE                     (TOP_BASE + 0x0008)
++#define    TOP_CTRL_ADDR_BYPASS_CON                     (TOP_BASE + 0x000C)
++#define    TOP_CTRL_ADDR_TOP_CON                        (TOP_BASE + 0x0010)
++#define    TOP_CTRL_ADDR_TOP_STATE                      (TOP_BASE + 0x0014)
++#define    TOP_CTRL_ADDR_LINE_SPACE                     (TOP_BASE + 0x0018)
++#define    TOP_CTRL_ADDR_REG_CON                        (TOP_BASE + 0x001C)
++#define    TOP_CTRL_ADDR_DMA_RC_TRIG                    (TOP_BASE + 0x0030)
++#define    TOP_CTRL_ADDR_DMA_RC_CON                     (TOP_BASE + 0x0034)
++#define    TOP_CTRL_ADDR_DMA_RC_ADDR                    (TOP_BASE + 0x0038)
++#define    TOP_CTRL_ADDR_DMA_RC_STATE                   (TOP_BASE + 0x003C)
++#define    TOP_CTRL_ADDR_DMA_RC_APB_WR_DATA             (TOP_BASE + 0x0040)
++#define    TOP_CTRL_ADDR_DMA_RC_APB_WR_ADDR             (TOP_BASE + 0x0044)
++#define    TOP_CTRL_ADDR_DMA_RD_CON                     (TOP_BASE + 0x0050)
++#define    TOP_CTRL_ADDR_DMA_WR_CON                     (TOP_BASE + 0x0054)
++#define    TOP_CTRL_ADDR_DMA_FR_WR_CON                  (TOP_BASE + 0x0058)
++#define    TOP_CTRL_ADDR_DMA_STA_WR_CON                 (TOP_BASE + 0x005C)
++#define    TOP_CTRL_ADDR_DMA_RD_DEBUG                   (TOP_BASE + 0x0060)
++#define    TOP_CTRL_ADDR_DMA_WR_DEBUG                   (TOP_BASE + 0x0064)
++#define    TOP_CTRL_ADDR_DMA_FR_WR_DEBUG                (TOP_BASE + 0x0068)
++#define    TOP_CTRL_ADDR_DMA_STA_WR_DEBUG               (TOP_BASE + 0x006C)
++#define    TOP_CTRL_ADDR_INT_EN                         (TOP_BASE + 0x0080)
++#define    TOP_CTRL_ADDR_INT_REG                        (TOP_BASE + 0x0084)
++#define    TOP_CTRL_ADDR_INT_CLR                        (TOP_BASE + 0x0088)
++#define    TOP_CTRL_ADDR_TP_FREERUN                     (TOP_BASE + 0x00A0)
++#define    TOP_CTRL_ADDR_TP_CON                         (TOP_BASE + 0x00A4)
++#define    TOP_CTRL_ADDR_TP_SIZE                        (TOP_BASE + 0x00A8)
++#define    TOP_CTRL_ADDR_TP_FONT                        (TOP_BASE + 0x00AC)
++#define    TOP_CTRL_ADDR_TP_FLICK                       (TOP_BASE + 0x00B0)
++#define    TOP_CTRL_ADDR_TP_CS_TYPE                     (TOP_BASE + 0x00B4)
++#define    TOP_CTRL_ADDR_TP_CS_FCLO                     (TOP_BASE + 0x00B8)
++#define    TOP_CTRL_ADDR_TP_CS_BCLO                     (TOP_BASE + 0x00BC)
++
++//============================================================
++// Input Interface
++//============================================================
++#define    INPUT_CTRL_ADDR_IP_TRIG                      (IP_BASE + 0x0000)
++#define    INPUT_CTRL_ADDR_CONTROL                      (IP_BASE + 0x0004)
++#define    INPUT_CTRL_ADDR_CHK_TRIG                     (IP_BASE + 0x0008)
++#define    INPUT_CTRL_ADDR_CHK_TIME                     (IP_BASE + 0x000C)
++#define    INPUT_CTRL_ADDR_CHK_CNT                      (IP_BASE + 0x0010)
++#define    INPUT_CTRL_ADDR_CHK_FR_CNT                   (IP_BASE + 0x0014)
++#define    INPUT_CTRL_ADDR_IP_STATE                     (IP_BASE + 0x0018)
++#define    INPUT_CTRL_ADDR_IN_CNT                       (IP_BASE + 0x001C)
++#define    INPUT_CTRL_ADDR_OUT_CNT                      (IP_BASE + 0x0020)
++
++//============================================================
++// DPC
++//============================================================
++#if 0
++#define    DPC_ADDR_SYNC                          (DPC_BASE + 0x0000)
++#define    DPC_ADDR_S_EN                          (DPC_BASE + 0x0004)
++#define    DPC_ADDR_S_OC_BLEND_ALPHA              (DPC_BASE + 0x0008)
++#define    DPC_ADDR_OC_BLEND_ALPHA                (DPC_BASE + 0x000C)
++#define    DPC_ADDR_SD_LV1_SLOPE                  (DPC_BASE + 0x0010)
++#define    DPC_ADDR_SD_LV2_SLOPE                  (DPC_BASE + 0x0014)
++#define    DPC_ADDR_LS_BLEND_ALPHA_RB             (DPC_BASE + 0x0018)
++#define    DPC_ADDR_LV1_DIFF_THRES_RB             (DPC_BASE + 0x001C)
++#define    DPC_ADDR_SD_LV2_DIFF_THRES_RB          (DPC_BASE + 0x0020)
++#define    DPC_ADDR_SD_LV2_P0_THRES_RB            (DPC_BASE + 0x0024)
++#define    DPC_ADDR_SD_LV2_P2_THRES_RB            (DPC_BASE + 0x0028)
++#define    DPC_ADDR_SD_LV2_P0_DIST_THRES_RB       (DPC_BASE + 0x002C)
++#define    DPC_ADDR_SD_LV2_P2_DIST_THRES_RB       (DPC_BASE + 0x0030)
++#define    DPC_ADDR_LD_LV2_THRES_RB               (DPC_BASE + 0x0034)
++#define    DPC_ADDR_LS_BLEND_ALPHA_G              (DPC_BASE + 0x0038)
++#define    DPC_ADDR_LV1_DIFF_THRES_G              (DPC_BASE + 0x003C)
++#define    DPC_ADDR_SD_LV2_DIFF_THRES_G           (DPC_BASE + 0x0040)
++#define    DPC_ADDR_SD_LV2_P0_THRES_G             (DPC_BASE + 0x0044)
++#define    DPC_ADDR_SD_LV2_P2_THRES_G             (DPC_BASE + 0x0048)
++#define    DPC_ADDR_SD_LV2_P0_DIST_THRES_G        (DPC_BASE + 0x004C)
++#define    DPC_ADDR_SD_LV2_P2_DIST_THRES_G        (DPC_BASE + 0x0050)
++#define    DPC_ADDR_LD_LV2_THRES_G                (DPC_BASE + 0x0054)
++#define    DPC_ADDR_CTR_FUNC_EN                   (DPC_BASE + 0x0058)
++#define    DPC_ADDR_CTR_MD_SEG_OPT                (DPC_BASE + 0x005C)
++#define    DPC_ADDR_CTR_BASE_THRES                (DPC_BASE + 0x0060)
++#define    DPC_ADDR_RDNS_FUNC_EN                  (DPC_BASE + 0x0064)
++#define    DPC_ADDR_RDNS_FLAT_THRES               (DPC_BASE + 0x0068)
++#define    DPC_ADDR_RDNS_TEXT_THRES               (DPC_BASE + 0x006C)
++#define    DPC_ADDR_RDNS_SIGMA_X1                 (DPC_BASE + 0x0070)
++#define    DPC_ADDR_RDNS_STD                      (DPC_BASE + 0x0074)
++#define    DPC_ADDR_RDNS_RB_GAUS_SIGMA            (DPC_BASE + 0x0078)
++#define    DPC_ADDR_RDNS_G_SIGMA_X                (DPC_BASE + 0x007C)
++#define    DPC_ADDR_RDNS_G_SIGMA_S                (DPC_BASE + 0x0080)
++#define    DPC_ADDR_RDNS_RB_SIGMA_X               (DPC_BASE + 0x0084)
++#define    DPC_ADDR_RDNS_RB_SIGMA_S               (DPC_BASE + 0x0088)
++#define    DPC_ADDR_CTR_MD_NP_ARRAY_RG0           (DPC_BASE + 0x008C)
++#define    DPC_ADDR_CTR_MD_NP_ARRAY_RG1           (DPC_BASE + 0x0090)
++#define    DPC_ADDR_CTR_MD_NP_ARRAY_RG2           (DPC_BASE + 0x0094)
++#define    DPC_ADDR_CTR_MD_NP_ARRAY_RG3           (DPC_BASE + 0x0098)
++#define    DPC_ADDR_RDNS_STD_NP_ARRAY_RG0         (DPC_BASE + 0x009C)
++#define    DPC_ADDR_RDNS_STD_NP_ARRAY_RG1         (DPC_BASE + 0x00A0)
++#define    DPC_ADDR_RDNS_STD_NP_ARRAY_RG2         (DPC_BASE + 0x00A4)
++#define    DPC_ADDR_RDNS_STD_NP_ARRAY_RG3         (DPC_BASE + 0x00A8)
++#define    DPC_ADDR_RDNS_STD_NP_ARRAY_RG4         (DPC_BASE + 0x00AC)
++#define    DPC_ADDR_RDNS_STD_NP_ARRAY_RG5         (DPC_BASE + 0x00B0)
++#define    DPC_ADDR_RDNS_STD_NP_ARRAY_RG6         (DPC_BASE + 0x00B4)
++#define    DPC_ADDR_RDNS_STD_NP_ARRAY_RG7         (DPC_BASE + 0x00B8)
++#define    DPC_ADDR_RDNS_G_LUM_NP_ARRAY_RG0       (DPC_BASE + 0x00BC)
++#define    DPC_ADDR_RDNS_G_LUM_NP_ARRAY_RG1       (DPC_BASE + 0x00C0)
++#define    DPC_ADDR_RDNS_G_LUM_NP_ARRAY_RG2       (DPC_BASE + 0x00C4)
++#define    DPC_ADDR_RDNS_G_LUM_NP_ARRAY_RG3       (DPC_BASE + 0x00C8)
++#define    DPC_ADDR_RDNS_G_LUM_NP_ARRAY_RG4       (DPC_BASE + 0x00CC)
++#define    DPC_ADDR_RDNS_G_LUM_NP_ARRAY_RG5       (DPC_BASE + 0x00D0)
++#define    DPC_ADDR_RDNS_G_LUM_NP_ARRAY_RG6       (DPC_BASE + 0x00D4)
++#define    DPC_ADDR_RDNS_G_LUM_NP_ARRAY_RG7       (DPC_BASE + 0x00D8)
++#define    DPC_ADDR_RDNS_G_STD_NP_ARRAY_RG0       (DPC_BASE + 0x00DC)
++#define    DPC_ADDR_RDNS_G_STD_NP_ARRAY_RG1       (DPC_BASE + 0x00E0)
++#define    DPC_ADDR_RDNS_G_STD_NP_ARRAY_RG2       (DPC_BASE + 0x00E4)
++#define    DPC_ADDR_RDNS_G_STD_NP_ARRAY_RG3       (DPC_BASE + 0x00E8)
++#define    DPC_ADDR_RDNS_G_STD_NP_ARRAY_RG4       (DPC_BASE + 0x00EC)
++#define    DPC_ADDR_RDNS_G_STD_NP_ARRAY_RG5       (DPC_BASE + 0x00F0)
++#define    DPC_ADDR_RDNS_G_STD_NP_ARRAY_RG6       (DPC_BASE + 0x00F4)
++#define    DPC_ADDR_RDNS_G_STD_NP_ARRAY_RG7       (DPC_BASE + 0x00F8)
++#define    DPC_ADDR_RDNS_RB_LUM_NP_ARRAY_RG0      (DPC_BASE + 0x00FC)
++#define    DPC_ADDR_RDNS_RB_LUM_NP_ARRAY_RG1      (DPC_BASE + 0x0100)
++#define    DPC_ADDR_RDNS_RB_LUM_NP_ARRAY_RG2      (DPC_BASE + 0x0104)
++#define    DPC_ADDR_RDNS_RB_LUM_NP_ARRAY_RG3      (DPC_BASE + 0x0108)
++#define    DPC_ADDR_RDNS_RB_LUM_NP_ARRAY_RG4      (DPC_BASE + 0x010C)
++#define    DPC_ADDR_RDNS_RB_LUM_NP_ARRAY_RG5      (DPC_BASE + 0x0110)
++#define    DPC_ADDR_RDNS_RB_LUM_NP_ARRAY_RG6      (DPC_BASE + 0x0114)
++#define    DPC_ADDR_RDNS_RB_LUM_NP_ARRAY_RG7      (DPC_BASE + 0x0118)
++#define    DPC_ADDR_RDNS_RB_STD_NP_ARRAY_RG0      (DPC_BASE + 0x011C)
++#define    DPC_ADDR_RDNS_RB_STD_NP_ARRAY_RG1      (DPC_BASE + 0x0120)
++#define    DPC_ADDR_RDNS_RB_STD_NP_ARRAY_RG2      (DPC_BASE + 0x0124)
++#define    DPC_ADDR_RDNS_RB_STD_NP_ARRAY_RG3      (DPC_BASE + 0x0128)
++#define    DPC_ADDR_RDNS_RB_STD_NP_ARRAY_RG4      (DPC_BASE + 0x012C)
++#define    DPC_ADDR_RDNS_RB_STD_NP_ARRAY_RG5      (DPC_BASE + 0x0130)
++#define    DPC_ADDR_RDNS_RB_STD_NP_ARRAY_RG6      (DPC_BASE + 0x0134)
++#define    DPC_ADDR_RDNS_RB_STD_NP_ARRAY_RG7      (DPC_BASE + 0x0138)
++#define    DPC_ADDR_SDP_NUM                       (DPC_BASE + 0x013C)
++#define    DPC_ADDR_SP_DEBUG_REG_0                (DPC_BASE + 0x0140)
++#define    DPC_ADDR_SP_DEBUG_REG_1                (DPC_BASE + 0x0144)
++
++//============================================================
++// GIB
++//============================================================
++#define    GIB_ADDR_REG_CTRL                      (GIB_BASE + 0x0000)
++#define    GIB_ADDR_CONFIG                        (GIB_BASE + 0x0004)
++#define    GIB_ADDR_R_G                           (GIB_BASE + 0x0008)
++#define    GIB_ADDR_B_IR                          (GIB_BASE + 0x000c)
++#define    GIB_ADDR_DEIRM_R12                     (GIB_BASE + 0x0010)
++#define    GIB_ADDR_DEIRM_R34                     (GIB_BASE + 0x0014)
++#define    GIB_ADDR_DEIRM_C1                      (GIB_BASE + 0x0018)
++#define    GIB_ADDR_DEIRM_G12                     (GIB_BASE + 0x001c)
++#define    GIB_ADDR_DEIRM_G34                     (GIB_BASE + 0x0020)
++#define    GIB_ADDR_DEIRM_C2                      (GIB_BASE + 0x0024)
++#define    GIB_ADDR_DEIRM_B12                     (GIB_BASE + 0x0028)
++#define    GIB_ADDR_DEIRM_B34                     (GIB_BASE + 0x002c)
++#define    GIB_ADDR_DEIRM_C3                      (GIB_BASE + 0x0030)
++#define    GIB_ADDR_DEIRM_BLC12                   (GIB_BASE + 0x0034)
++#define    GIB_ADDR_DEIRM_BLC34                   (GIB_BASE + 0x0038)
++#define    GIB_ADDR_DEIRM_BLC5                    (GIB_BASE + 0x003c)
++#define    GIB_ADDR_DEBUG0                        (GIB_BASE + 0x0040)
++#define    GIB_DEIR_R_BASE                        (GIB_MEM_BASE + 0x0000)
++#define    GIB_DEIR_G_BASE                        (GIB_MEM_BASE + 0x0080)
++#define    GIB_DEIR_B_BASE                        (GIB_MEM_BASE + 0x0100)
++
++//============================================================
++// LSC
++//============================================================
++#define    LSC_ADDR_T_VERSION                     (LSC_BASE + 0x0000)
++#define    LSC_ADDR_T_DBG_SEL                     (LSC_BASE + 0x0004)
++#define    LSC_ADDR_T_DBG_VALUE                   (LSC_BASE + 0x0008)
++#define    LSC_ADDR_MESH_SIZE                     (LSC_BASE + 0x0010)
++#define    LSC_ADDR_MESH_SCALE                    (LSC_BASE + 0x0014)
++#define    LSC_ADDR_LUT_STRIDE                    (LSC_BASE + 0x0018)
++
++//============================================================
++// AG
++//============================================================
++#define    AWB_GAIN_ADDR_REG_CTRL                 (AG_BASE + 0x0000)
++#define    AWB_GAIN_ADDR_R_G                      (AG_BASE + 0x0004)
++#define    AWB_GAIN_ADDR_B_IR                     (AG_BASE + 0x0008)
++#define    AWB_GAIN_ADDR_DEBUG0                   (AG_BASE + 0x000c)
++
++//============================================================
++// AE
++//============================================================
++#define    AE_STAT_ADDR_REG_CTRL                  (AE_BASE + 0x0000)
++#define    AE_STAT_ADDR_ZONE_NUM_START            (AE_BASE + 0x0004)
++#define    AE_STAT_ADDR_HOR_ZONE_SIZE_14          (AE_BASE + 0x0008)
++#define    AE_STAT_ADDR_HOR_ZONE_SIZE_58          (AE_BASE + 0x000c)
++#define    AE_STAT_ADDR_HOR_ZONE_SIZE_912         (AE_BASE + 0x0010)
++#define    AE_STAT_ADDR_HOR_ZONE_SIZE_1315        (AE_BASE + 0x0014)
++#define    AE_STAT_ADDR_VER_ZONE_SIZE_14          (AE_BASE + 0x0018)
++#define    AE_STAT_ADDR_VER_ZONE_SIZE_58          (AE_BASE + 0x001c)
++#define    AE_STAT_ADDR_VER_ZONE_SIZE_912         (AE_BASE + 0x0020)
++#define    AE_STAT_ADDR_VER_ZONE_SIZE_1315        (AE_BASE + 0x0024)
++#define    AE_STAT_ADDR_LUM_TH_FREQ               (AE_BASE + 0x0028)
++#define    AE_STAT_ADDR_AE_DMA_BASE_1             (AE_BASE + 0x002c)
++#define    AE_STAT_ADDR_AE_DMA_BASE_2             (AE_BASE + 0x0030)
++#define    AE_STAT_ADDR_AE_DMA_BASE_3             (AE_BASE + 0x0034)
++#define    AE_STAT_ADDR_AE_DMA_BASE_4             (AE_BASE + 0x0038)
++#define    AE_STAT_ADDR_HIST_DMA_BASE_1           (AE_BASE + 0x003c)
++#define    AE_STAT_ADDR_HIST_DMA_BASE_2           (AE_BASE + 0x0040)
++#define    AE_STAT_ADDR_HIST_DMA_BASE_3           (AE_BASE + 0x0044)
++#define    AE_STAT_ADDR_HIST_DMA_BASE_4           (AE_BASE + 0x0048)
++#define    AE_STAT_ADDR_DMA_BASE_NUM              (AE_BASE + 0x004c)
++#define    AE_STAT_ADDR_DMA_INFO                  (AE_BASE + 0x0050)
++#define    AE_STAT_ADDR_DEBUG0                    (AE_BASE + 0x0054)
++#define    AE_STAT_ADDR_DEBUG1                    (AE_BASE + 0x0058)
++
++//============================================================
++// AWB
++//============================================================
++#define    AWB_STAT_ADDR_REG_CTRL                 (AWB_BASE + 0x0000)
++#define    AWB_STAT_ADDR_ZONE_NUM_START           (AWB_BASE + 0x0004)
++#define    AWB_STAT_ADDR_HOR_ZONE_SIZE_14         (AWB_BASE + 0x0008)
++#define    AWB_STAT_ADDR_HOR_ZONE_SIZE_58         (AWB_BASE + 0x000c)
++#define    AWB_STAT_ADDR_HOR_ZONE_SIZE_912        (AWB_BASE + 0x0010)
++#define    AWB_STAT_ADDR_HOR_ZONE_SIZE_1315       (AWB_BASE + 0x0014)
++#define    AWB_STAT_ADDR_VER_ZONE_SIZE_14         (AWB_BASE + 0x0018)
++#define    AWB_STAT_ADDR_VER_ZONE_SIZE_58         (AWB_BASE + 0x001c)
++#define    AWB_STAT_ADDR_VER_ZONE_SIZE_912        (AWB_BASE + 0x0020)
++#define    AWB_STAT_ADDR_VER_ZONE_SIZE_1315       (AWB_BASE + 0x0024)
++#define    AWB_STAT_ADDR_RG_TH                    (AWB_BASE + 0x0028)
++#define    AWB_STAT_ADDR_BG_TH                    (AWB_BASE + 0x002c)
++#define    AWB_STAT_ADDR_K1_A1                    (AWB_BASE + 0x0030)
++#define    AWB_STAT_ADDR_K2_A2                    (AWB_BASE + 0x0034)
++#define    AWB_STAT_ADDR_LUM_TH_FREQ              (AWB_BASE + 0x0038)
++#define    AWB_STAT_ADDR_AWB_DMA_BASE_1           (AWB_BASE + 0x003c)
++#define    AWB_STAT_ADDR_AWB_DMA_BASE_2           (AWB_BASE + 0x0040)
++#define    AWB_STAT_ADDR_AWB_DMA_BASE_3           (AWB_BASE + 0x0044)
++#define    AWB_STAT_ADDR_AWB_DMA_BASE_4           (AWB_BASE + 0x0048)
++#define    AWB_STAT_ADDR_DMA_BASE_NUM             (AWB_BASE + 0x004c)
++#define    AWB_STAT_ADDR_DMA_INFO                 (AWB_BASE + 0x0050)
++#define    AWB_STAT_ADDR_DEBUG0                   (AWB_BASE + 0x0054)
++#define    AWB_STAT_ADDR_DEBUG1                   (AWB_BASE + 0x0058)
++
++//============================================================
++// AF
++//============================================================
++#define    AF_STAT_ADDR_REG_CTRL                  (AF_BASE + 0x0000)
++#define    AF_STAT_ADDR_ZONE_NUM_START            (AF_BASE + 0x0004)
++#define    AF_STAT_ADDR_HOR_ZONE_SIZE_14          (AF_BASE + 0x0008)
++#define    AF_STAT_ADDR_HOR_ZONE_SIZE_58          (AF_BASE + 0x000c)
++#define    AF_STAT_ADDR_HOR_ZONE_SIZE_912         (AF_BASE + 0x0010)
++#define    AF_STAT_ADDR_HOR_ZONE_SIZE_1315        (AF_BASE + 0x0014)
++#define    AF_STAT_ADDR_VER_ZONE_SIZE_14          (AF_BASE + 0x0018)
++#define    AF_STAT_ADDR_VER_ZONE_SIZE_58          (AF_BASE + 0x001c)
++#define    AF_STAT_ADDR_VER_ZONE_SIZE_912         (AF_BASE + 0x0020)
++#define    AF_STAT_ADDR_VER_ZONE_SIZE_1315        (AF_BASE + 0x0024)
++#define    AF_STAT_ADDR_FREQ_IIR_EN_LUM_TH        (AF_BASE + 0x0028)
++#define    AF_STAT_ADDR_LDG_COR_EN                (AF_BASE + 0x002c)
++#define    AF_STAT_ADDR_FIR0_G1_G2                (AF_BASE + 0x0030)
++#define    AF_STAT_ADDR_FIR0_G3_G4                (AF_BASE + 0x0034)
++#define    AF_STAT_ADDR_FIR0_G5                   (AF_BASE + 0x0038)
++#define    AF_STAT_ADDR_FIR1_G1_G2                (AF_BASE + 0x003c)
++#define    AF_STAT_ADDR_FIR1_G3_G4                (AF_BASE + 0x0040)
++#define    AF_STAT_ADDR_FIR1_G5                   (AF_BASE + 0x0044)
++#define    AF_STAT_ADDR_IIR0_G1_G3                (AF_BASE + 0x0048)
++#define    AF_STAT_ADDR_IIR0_G4_G5                (AF_BASE + 0x004c)
++#define    AF_STAT_ADDR_IIR0_G6_G8                (AF_BASE + 0x0050)
++#define    AF_STAT_ADDR_IIR0_G9_G10               (AF_BASE + 0x0054)
++#define    AF_STAT_ADDR_IIR1_G1_G3                (AF_BASE + 0x0058)
++#define    AF_STAT_ADDR_IIR1_G4_G5                (AF_BASE + 0x005c)
++#define    AF_STAT_ADDR_IIR1_G6_G8                (AF_BASE + 0x0060)
++#define    AF_STAT_ADDR_IIR1_G9_G10               (AF_BASE + 0x0064)
++#define    AF_STAT_ADDR_LDG_FIR0_LOW              (AF_BASE + 0x0068)
++#define    AF_STAT_ADDR_LDG_FIR0_HIGH             (AF_BASE + 0x006c)
++#define    AF_STAT_ADDR_LDG_FIR1_LOW              (AF_BASE + 0x0070)
++#define    AF_STAT_ADDR_LDG_FIR1_HIGH             (AF_BASE + 0x0074)
++#define    AF_STAT_ADDR_LDG_IIR0_LOW              (AF_BASE + 0x0078)
++#define    AF_STAT_ADDR_LDG_IIR0_HIGH             (AF_BASE + 0x007c)
++#define    AF_STAT_ADDR_LDG_IIR1_LOW              (AF_BASE + 0x0080)
++#define    AF_STAT_ADDR_LDG_IIR1_HIGH             (AF_BASE + 0x0084)
++#define    AF_STAT_ADDR_COR_F0_TH_LH              (AF_BASE + 0x0088)
++#define    AF_STAT_ADDR_COR_F0_SLP_LIM            (AF_BASE + 0x008c)
++#define    AF_STAT_ADDR_COR_F1_TH_LH              (AF_BASE + 0x0090)
++#define    AF_STAT_ADDR_COR_F1_SLP_LIM            (AF_BASE + 0x0094)
++#define    AF_STAT_ADDR_COR_I0_TH_LH              (AF_BASE + 0x0098)
++#define    AF_STAT_ADDR_COR_I0_SLP_LIM            (AF_BASE + 0x009c)
++#define    AF_STAT_ADDR_COR_I1_TH_LH              (AF_BASE + 0x00a0)
++#define    AF_STAT_ADDR_COR_I1_SLP_LIM            (AF_BASE + 0x00a4)
++#define    AF_STAT_ADDR_AF_DMA_BASE_1             (AF_BASE + 0x00a8)
++#define    AF_STAT_ADDR_AF_DMA_BASE_2             (AF_BASE + 0x00ac)
++#define    AF_STAT_ADDR_AF_DMA_BASE_3             (AF_BASE + 0x00b0)
++#define    AF_STAT_ADDR_AF_DMA_BASE_4             (AF_BASE + 0x00b4)
++#define    AF_STAT_ADDR_DMA_BASE_NUM              (AF_BASE + 0x00b8)
++#define    AF_STAT_ADDR_DMA_INFO                  (AF_BASE + 0x00bc)
++#define    AF_STAT_ADDR_DEBUG0                    (AF_BASE + 0x00c0)
++
++//============================================================
++// ADR
++//============================================================
++#define    ADR_ADDR_T_VERSION                     (ADR_BASE + 0x0000)
++#define    ADR_ADDR_T_DBG_SEL                     (ADR_BASE + 0x0004)
++#define    ADR_ADDR_T_DEG_VALUE                   (ADR_BASE + 0x0008)
++#define    ADR_ADDR_STEP_PAR                      (ADR_BASE + 0x000C)
++#define    ADR_ADDR_BLK_COORD_M_P_0               (ADR_BASE + 0x0010)
++#define    ADR_ADDR_BLK_COORD_M_P_1               (ADR_BASE + 0x0014)
++#define    ADR_ADDR_BLK_COORD_M_P_2               (ADR_BASE + 0x0018)
++#define    ADR_ADDR_BLK_COORD_N_P_0               (ADR_BASE + 0x001C)
++#define    ADR_ADDR_BLK_COORD_N_P_1               (ADR_BASE + 0x0020)
++#define    ADR_ADDR_BLK_COORD_N_P_2               (ADR_BASE + 0x0024)
++#define    ADR_ADDR_CEN_DIS_P_0                   (ADR_BASE + 0x0028)
++#define    ADR_ADDR_CEN_DIS_P_1                   (ADR_BASE + 0x002C)
++#define    ADR_ADDR_CEN_DIS_P_2                   (ADR_BASE + 0x0030)
++#define    ADR_ADDR_CEN_DIS_P_3                   (ADR_BASE + 0x0034)
++#define    ADR_ADDR_CEN_DIS_P_4                   (ADR_BASE + 0x0038)
++#define    ADR_ADDR_CEN_DIS_P_5                   (ADR_BASE + 0x003C)
++#define    ADR_ADDR_CEN_DIS_P_6                   (ADR_BASE + 0x0040)
++#define    ADR_ADDR_CEN_DIS_P_7                   (ADR_BASE + 0x0044)
++#define    ADR_ADDR_CEN_DIS_P_8                   (ADR_BASE + 0x0048)
++#define    ADR_ADDR_CEN_DIS_P_9                   (ADR_BASE + 0x004C)
++#define    ADR_ADDR_CEN_DIS_P_A                   (ADR_BASE + 0x0050)
++#define    ADR_ADDR_CEN_DIS_P_B                   (ADR_BASE + 0x0054)
++#define    ADR_ADDR_CEN_DIS_P_C                   (ADR_BASE + 0x0058)
++#define    ADR_ADDR_CEN_DIS_P_D                   (ADR_BASE + 0x005C)
++#define    ADR_ADDR_CEN_DIS_P_E                   (ADR_BASE + 0x0060)
++#define    ADR_ADDR_CEN_DIS_P_F                   (ADR_BASE + 0x0064)
++#define    ADR_ADDR_MAP_KPOINT_X_P0               (ADR_BASE + 0x0068)
++#define    ADR_ADDR_MAP_KPOINT_X_P1               (ADR_BASE + 0x006C)
++#define    ADR_ADDR_MAP_KPOINT_X_P2               (ADR_BASE + 0x0070)
++#define    ADR_ADDR_MAP_KPOINT_X_P3               (ADR_BASE + 0x0074)
++#define    ADR_ADDR_MAP_KPOINT_X_P4               (ADR_BASE + 0x0078)
++#define    ADR_ADDR_MAP_KPOINT_X_P5               (ADR_BASE + 0x007C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P00_0            (ADR_BASE + 0x0080)
++#define    ADR_ADDR_MAP_KPOINT_Y_P00_1            (ADR_BASE + 0x0084)
++#define    ADR_ADDR_MAP_KPOINT_Y_P00_2            (ADR_BASE + 0x0088)
++#define    ADR_ADDR_MAP_KPOINT_Y_P00_3            (ADR_BASE + 0x008C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P00_4            (ADR_BASE + 0x0090)
++#define    ADR_ADDR_MAP_KPOINT_Y_P00_5            (ADR_BASE + 0x0094)
++#define    ADR_ADDR_MAP_KPOINT_Y_P01_0            (ADR_BASE + 0x0098)
++#define    ADR_ADDR_MAP_KPOINT_Y_P01_1            (ADR_BASE + 0x009C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P01_2            (ADR_BASE + 0x00A0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P01_3            (ADR_BASE + 0x00A4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P01_4            (ADR_BASE + 0x00A8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P01_5            (ADR_BASE + 0x00AC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P02_0            (ADR_BASE + 0x00B0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P02_1            (ADR_BASE + 0x00B4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P02_2            (ADR_BASE + 0x00B8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P02_3            (ADR_BASE + 0x00BC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P02_4            (ADR_BASE + 0x00C0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P02_5            (ADR_BASE + 0x00C4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P03_0            (ADR_BASE + 0x00C8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P03_1            (ADR_BASE + 0x00CC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P03_2            (ADR_BASE + 0x00D0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P03_3            (ADR_BASE + 0x00D4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P03_4            (ADR_BASE + 0x00D8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P03_5            (ADR_BASE + 0x00DC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P04_0            (ADR_BASE + 0x00E0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P04_1            (ADR_BASE + 0x00E4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P04_2            (ADR_BASE + 0x00E8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P04_3            (ADR_BASE + 0x00EC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P04_4            (ADR_BASE + 0x00F0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P04_5            (ADR_BASE + 0x00F4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P05_0            (ADR_BASE + 0x00F8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P05_1            (ADR_BASE + 0x00FC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P05_2            (ADR_BASE + 0x0100)
++#define    ADR_ADDR_MAP_KPOINT_Y_P05_3            (ADR_BASE + 0x0104)
++#define    ADR_ADDR_MAP_KPOINT_Y_P05_4            (ADR_BASE + 0x0108)
++#define    ADR_ADDR_MAP_KPOINT_Y_P05_5            (ADR_BASE + 0x010C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P06_0            (ADR_BASE + 0x0110)
++#define    ADR_ADDR_MAP_KPOINT_Y_P06_1            (ADR_BASE + 0x0114)
++#define    ADR_ADDR_MAP_KPOINT_Y_P06_2            (ADR_BASE + 0x0118)
++#define    ADR_ADDR_MAP_KPOINT_Y_P06_3            (ADR_BASE + 0x011C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P06_4            (ADR_BASE + 0x0120)
++#define    ADR_ADDR_MAP_KPOINT_Y_P06_5            (ADR_BASE + 0x0124)
++#define    ADR_ADDR_MAP_KPOINT_Y_P07_0            (ADR_BASE + 0x0128)
++#define    ADR_ADDR_MAP_KPOINT_Y_P07_1            (ADR_BASE + 0x012C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P07_2            (ADR_BASE + 0x0130)
++#define    ADR_ADDR_MAP_KPOINT_Y_P07_3            (ADR_BASE + 0x0134)
++#define    ADR_ADDR_MAP_KPOINT_Y_P07_4            (ADR_BASE + 0x0138)
++#define    ADR_ADDR_MAP_KPOINT_Y_P07_5            (ADR_BASE + 0x013C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P08_0            (ADR_BASE + 0x0140)
++#define    ADR_ADDR_MAP_KPOINT_Y_P08_1            (ADR_BASE + 0x0144)
++#define    ADR_ADDR_MAP_KPOINT_Y_P08_2            (ADR_BASE + 0x0148)
++#define    ADR_ADDR_MAP_KPOINT_Y_P08_3            (ADR_BASE + 0x014C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P08_4            (ADR_BASE + 0x0150)
++#define    ADR_ADDR_MAP_KPOINT_Y_P08_5            (ADR_BASE + 0x0154)
++#define    ADR_ADDR_MAP_KPOINT_Y_P09_0            (ADR_BASE + 0x0158)
++#define    ADR_ADDR_MAP_KPOINT_Y_P09_1            (ADR_BASE + 0x015C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P09_2            (ADR_BASE + 0x0160)
++#define    ADR_ADDR_MAP_KPOINT_Y_P09_3            (ADR_BASE + 0x0164)
++#define    ADR_ADDR_MAP_KPOINT_Y_P09_4            (ADR_BASE + 0x0168)
++#define    ADR_ADDR_MAP_KPOINT_Y_P09_5            (ADR_BASE + 0x016C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P10_0            (ADR_BASE + 0x0170)
++#define    ADR_ADDR_MAP_KPOINT_Y_P10_1            (ADR_BASE + 0x0174)
++#define    ADR_ADDR_MAP_KPOINT_Y_P10_2            (ADR_BASE + 0x0178)
++#define    ADR_ADDR_MAP_KPOINT_Y_P10_3            (ADR_BASE + 0x017C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P10_4            (ADR_BASE + 0x0180)
++#define    ADR_ADDR_MAP_KPOINT_Y_P10_5            (ADR_BASE + 0x0184)
++#define    ADR_ADDR_MAP_KPOINT_Y_P11_0            (ADR_BASE + 0x0188)
++#define    ADR_ADDR_MAP_KPOINT_Y_P11_1            (ADR_BASE + 0x018C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P11_2            (ADR_BASE + 0x0190)
++#define    ADR_ADDR_MAP_KPOINT_Y_P11_3            (ADR_BASE + 0x0194)
++#define    ADR_ADDR_MAP_KPOINT_Y_P11_4            (ADR_BASE + 0x0198)
++#define    ADR_ADDR_MAP_KPOINT_Y_P11_5            (ADR_BASE + 0x019C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P12_0            (ADR_BASE + 0x01A0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P12_1            (ADR_BASE + 0x01A4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P12_2            (ADR_BASE + 0x01A8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P12_3            (ADR_BASE + 0x01AC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P12_4            (ADR_BASE + 0x01B0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P12_5            (ADR_BASE + 0x01B4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P13_0            (ADR_BASE + 0x01B8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P13_1            (ADR_BASE + 0x01BC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P13_2            (ADR_BASE + 0x01C0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P13_3            (ADR_BASE + 0x01C4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P13_4            (ADR_BASE + 0x01C8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P13_5            (ADR_BASE + 0x01CC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P14_0            (ADR_BASE + 0x01D0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P14_1            (ADR_BASE + 0x01D4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P14_2            (ADR_BASE + 0x01D8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P14_3            (ADR_BASE + 0x01DC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P14_4            (ADR_BASE + 0x01E0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P14_5            (ADR_BASE + 0x01E4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P15_0            (ADR_BASE + 0x01E8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P15_1            (ADR_BASE + 0x01EC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P15_2            (ADR_BASE + 0x01F0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P15_3            (ADR_BASE + 0x01F4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P15_4            (ADR_BASE + 0x01F8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P15_5            (ADR_BASE + 0x01FC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P16_0            (ADR_BASE + 0x0200)
++#define    ADR_ADDR_MAP_KPOINT_Y_P16_1            (ADR_BASE + 0x0204)
++#define    ADR_ADDR_MAP_KPOINT_Y_P16_2            (ADR_BASE + 0x0208)
++#define    ADR_ADDR_MAP_KPOINT_Y_P16_3            (ADR_BASE + 0x020C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P16_4            (ADR_BASE + 0x0210)
++#define    ADR_ADDR_MAP_KPOINT_Y_P16_5            (ADR_BASE + 0x0214)
++#define    ADR_ADDR_MAP_KPOINT_Y_P17_0            (ADR_BASE + 0x0218)
++#define    ADR_ADDR_MAP_KPOINT_Y_P17_1            (ADR_BASE + 0x021C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P17_2            (ADR_BASE + 0x0220)
++#define    ADR_ADDR_MAP_KPOINT_Y_P17_3            (ADR_BASE + 0x0224)
++#define    ADR_ADDR_MAP_KPOINT_Y_P17_4            (ADR_BASE + 0x0228)
++#define    ADR_ADDR_MAP_KPOINT_Y_P17_5            (ADR_BASE + 0x022C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P18_0            (ADR_BASE + 0x0230)
++#define    ADR_ADDR_MAP_KPOINT_Y_P18_1            (ADR_BASE + 0x0234)
++#define    ADR_ADDR_MAP_KPOINT_Y_P18_2            (ADR_BASE + 0x0238)
++#define    ADR_ADDR_MAP_KPOINT_Y_P18_3            (ADR_BASE + 0x023C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P18_4            (ADR_BASE + 0x0240)
++#define    ADR_ADDR_MAP_KPOINT_Y_P18_5            (ADR_BASE + 0x0244)
++#define    ADR_ADDR_MAP_KPOINT_Y_P19_0            (ADR_BASE + 0x0248)
++#define    ADR_ADDR_MAP_KPOINT_Y_P19_1            (ADR_BASE + 0x024C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P19_2            (ADR_BASE + 0x0250)
++#define    ADR_ADDR_MAP_KPOINT_Y_P19_3            (ADR_BASE + 0x0254)
++#define    ADR_ADDR_MAP_KPOINT_Y_P19_4            (ADR_BASE + 0x0258)
++#define    ADR_ADDR_MAP_KPOINT_Y_P19_5            (ADR_BASE + 0x025C)
++#define    ADR_ADDR_WEILUT20_P0                   (ADR_BASE + 0x0260)
++#define    ADR_ADDR_WEILUT20_P1                   (ADR_BASE + 0x0264)
++#define    ADR_ADDR_WEILUT20_P2                   (ADR_BASE + 0x0268)
++#define    ADR_ADDR_WEILUT20_P3                   (ADR_BASE + 0x026C)
++#define    ADR_ADDR_WEILUT20_P4                   (ADR_BASE + 0x0270)
++#define    ADR_ADDR_WEILUT20_P5                   (ADR_BASE + 0x0274)
++#define    ADR_ADDR_WEILUT20_P6                   (ADR_BASE + 0x0278)
++#define    ADR_ADDR_WEILUT20_P7                   (ADR_BASE + 0x027C)
++#define    ADR_ADDR_WEILUT02_P0                   (ADR_BASE + 0x0280)
++#define    ADR_ADDR_WEILUT02_P1                   (ADR_BASE + 0x0284)
++#define    ADR_ADDR_WEILUT02_P2                   (ADR_BASE + 0x0288)
++#define    ADR_ADDR_WEILUT02_P3                   (ADR_BASE + 0x028C)
++#define    ADR_ADDR_WEILUT02_P4                   (ADR_BASE + 0x0290)
++#define    ADR_ADDR_WEILUT02_P5                   (ADR_BASE + 0x0294)
++#define    ADR_ADDR_WEILUT02_P6                   (ADR_BASE + 0x0298)
++#define    ADR_ADDR_WEILUT02_P7                   (ADR_BASE + 0x029C)
++#define    ADR_ADDR_WEILUT12_P0                   (ADR_BASE + 0x02A0)
++#define    ADR_ADDR_WEILUT12_P1                   (ADR_BASE + 0x02A4)
++#define    ADR_ADDR_WEILUT12_P2                   (ADR_BASE + 0x02A8)
++#define    ADR_ADDR_WEILUT12_P3                   (ADR_BASE + 0x02AC)
++#define    ADR_ADDR_WEILUT12_P4                   (ADR_BASE + 0x02B0)
++#define    ADR_ADDR_WEILUT12_P5                   (ADR_BASE + 0x02B4)
++#define    ADR_ADDR_WEILUT12_P6                   (ADR_BASE + 0x02B8)
++#define    ADR_ADDR_WEILUT12_P7                   (ADR_BASE + 0x02BC)
++#define    ADR_ADDR_WEILUT22_P0                   (ADR_BASE + 0x02C0)
++#define    ADR_ADDR_WEILUT22_P1                   (ADR_BASE + 0x02C4)
++#define    ADR_ADDR_WEILUT22_P2                   (ADR_BASE + 0x02C8)
++#define    ADR_ADDR_WEILUT22_P3                   (ADR_BASE + 0x02CC)
++#define    ADR_ADDR_WEILUT22_P4                   (ADR_BASE + 0x02D0)
++#define    ADR_ADDR_WEILUT22_P5                   (ADR_BASE + 0x02D4)
++#define    ADR_ADDR_WEILUT22_P6                   (ADR_BASE + 0x02D8)
++#define    ADR_ADDR_WEILUT22_P7                   (ADR_BASE + 0x02DC)
++#define    ADR_ADDR_WEILUT21_P0                   (ADR_BASE + 0x02E0)
++#define    ADR_ADDR_WEILUT21_P1                   (ADR_BASE + 0x02E4)
++#define    ADR_ADDR_WEILUT21_P2                   (ADR_BASE + 0x02E8)
++#define    ADR_ADDR_WEILUT21_P3                   (ADR_BASE + 0x02EC)
++#define    ADR_ADDR_WEILUT21_P4                   (ADR_BASE + 0x02F0)
++#define    ADR_ADDR_WEILUT21_P5                   (ADR_BASE + 0x02F4)
++#define    ADR_ADDR_WEILUT21_P6                   (ADR_BASE + 0x02F8)
++#define    ADR_ADDR_WEILUT21_P7                   (ADR_BASE + 0x02FC)
++#define    ADR_ADDR_MAP_KPOINT_POW_P0             (ADR_BASE + 0x0300)
++#define    ADR_ADDR_MAP_KPOINT_POW_P1             (ADR_BASE + 0x0304)
++#define    ADR_ADDR_MAP_KPOINT_POW_P2             (ADR_BASE + 0x0308)
++#define    ADR_ADDR_CTC_KPOINT_X_P0               (ADR_BASE + 0x0310)
++#define    ADR_ADDR_CTC_KPOINT_X_P1               (ADR_BASE + 0x0314)
++#define    ADR_ADDR_CON_W_DIS_P00                 (ADR_BASE + 0x0320)
++#define    ADR_ADDR_CON_W_DIS_P01                 (ADR_BASE + 0x0324)
++#define    ADR_ADDR_CON_W_DIS_P02                 (ADR_BASE + 0x0328)
++#define    ADR_ADDR_CON_W_DIS_P03                 (ADR_BASE + 0x032C)
++#define    ADR_ADDR_CON_W_DIS_P04                 (ADR_BASE + 0x0330)
++#define    ADR_ADDR_CON_W_DIS_P05                 (ADR_BASE + 0x0334)
++#define    ADR_ADDR_CON_W_DIS_P06                 (ADR_BASE + 0x0338)
++#define    ADR_ADDR_CON_W_DIS_P07                 (ADR_BASE + 0x033C)
++#define    ADR_ADDR_CON_W_DIS_P08                 (ADR_BASE + 0x0340)
++#define    ADR_ADDR_CON_W_DIS_P09                 (ADR_BASE + 0x0344)
++#define    ADR_ADDR_CON_W_DIS_P10                 (ADR_BASE + 0x0348)
++#define    ADR_ADDR_CON_W_DIS_P11                 (ADR_BASE + 0x034C)
++#define    ADR_ADDR_CON_W_DIS_P12                 (ADR_BASE + 0x0350)
++#define    ADR_ADDR_CON_W_DIS_P13                 (ADR_BASE + 0x0354)
++#define    ADR_ADDR_CON_W_DIS_P14                 (ADR_BASE + 0x0358)
++#define    ADR_ADDR_CON_W_DIS_P15                 (ADR_BASE + 0x035C)
++#define    ADR_ADDR_CON_W_DIS_P16                 (ADR_BASE + 0x0360)
++#define    ADR_ADDR_CON_W_DIS_P17                 (ADR_BASE + 0x0364)
++#define    ADR_ADDR_CON_W_DIS_P18                 (ADR_BASE + 0x0368)
++#define    ADR_ADDR_CON_W_DIS_P19                 (ADR_BASE + 0x036C)
++#define    ADR_ADDR_CON_W_DIS_P20                 (ADR_BASE + 0x0370)
++#define    ADR_ADDR_CON_W_DIS_P21                 (ADR_BASE + 0x0374)
++#define    ADR_ADDR_CON_W_DIS_P22                 (ADR_BASE + 0x0378)
++#define    ADR_ADDR_CON_W_DIS_P23                 (ADR_BASE + 0x037C)
++#define    ADR_ADDR_CON_W_DIS_P24                 (ADR_BASE + 0x0380)
++#define    ADR_ADDR_CON_W_DIS_P25                 (ADR_BASE + 0x0384)
++#define    ADR_ADDR_CON_W_DIS_P26                 (ADR_BASE + 0x0388)
++#define    ADR_ADDR_CON_W_DIS_P27                 (ADR_BASE + 0x038C)
++#define    ADR_ADDR_CON_W_DIS_P28                 (ADR_BASE + 0x0390)
++#define    ADR_ADDR_CON_W_DIS_P29                 (ADR_BASE + 0x0394)
++#define    ADR_ADDR_CON_W_DIS_P30                 (ADR_BASE + 0x0398)
++#define    ADR_ADDR_CON_W_DIS_P31                 (ADR_BASE + 0x039C)
++#define    ADR_ADDR_CTC_KPOINT_MUX_P0             (ADR_BASE + 0x03A0)
++#define    ADR_ADDR_CTC_KPOINT_MUX_P1             (ADR_BASE + 0x03A4)
++#define    ADR_ADDR_CTC_RATIO                     (ADR_BASE + 0x03A8)
++#define    ADR_ADDR_MIN_KPOINT_X_P0               (ADR_BASE + 0x03B0)
++#define    ADR_ADDR_MIN_KPOINT_X_P1               (ADR_BASE + 0x03B4)
++#define    ADR_ADDR_MIN_KPOINT_X_P2               (ADR_BASE + 0x03B8)
++#define    ADR_ADDR_MIN_KPOINT_X_P3               (ADR_BASE + 0x03BC)
++#define    ADR_ADDR_MIN_KPOINT_X_P4               (ADR_BASE + 0x03C0)
++#define    ADR_ADDR_MIN_KPOINT_X_P5               (ADR_BASE + 0x03C4)
++#define    ADR_ADDR_MIN_KPOINT_Y_P0               (ADR_BASE + 0x03C8)
++#define    ADR_ADDR_MIN_KPOINT_Y_P1               (ADR_BASE + 0x03CC)
++#define    ADR_ADDR_MIN_KPOINT_Y_P2               (ADR_BASE + 0x03D0)
++#define    ADR_ADDR_MIN_KPOINT_Y_P3               (ADR_BASE + 0x03D4)
++#define    ADR_ADDR_MIN_KPOINT_Y_P4               (ADR_BASE + 0x03D8)
++#define    ADR_ADDR_MIN_KPOINT_Y_P5               (ADR_BASE + 0x03DC)
++#define    ADR_ADDR_MIN_KPOINT_POW_P0             (ADR_BASE + 0x03E0)
++#define    ADR_ADDR_MIN_KPOINT_POW_P1             (ADR_BASE + 0x03E4)
++#define    ADR_ADDR_MIN_KPOINT_POW_P2             (ADR_BASE + 0x03E8)
++#define    ADR_ADDR_COC_KPOINT_X_P0               (ADR_BASE + 0x03F0)
++#define    ADR_ADDR_COC_KPOINT_X_P1               (ADR_BASE + 0x03F4)
++#define    ADR_ADDR_COC_KPOINT_X_P2               (ADR_BASE + 0x03F8)
++#define    ADR_ADDR_COC_KPOINT_X_P3               (ADR_BASE + 0x03FC)
++#define    ADR_ADDR_COC_KPOINT_X_P4               (ADR_BASE + 0x0400)
++#define    ADR_ADDR_COC_KPOINT_X_P5               (ADR_BASE + 0x0404)
++#define    ADR_ADDR_COC_THRES                     (ADR_BASE + 0x0408)
++#define    ADR_ADDR_COC_STREN                     (ADR_BASE + 0x040C)
++#define    ADR_ADDR_COC_MODE                      (ADR_BASE + 0x0410)
++#define    ADR_ADDR_COC_KPOINT_POW_P0             (ADR_BASE + 0x0414)
++#define    ADR_ADDR_COC_KPOINT_POW_P1             (ADR_BASE + 0x0418)
++#define    ADR_ADDR_COC_KPOINT_POW_P2             (ADR_BASE + 0x041C)
++#define    ADR_ADDR_STAT_BLOCK_DIFF_P_0           (ADR_BASE + 0x0420)
++#define    ADR_ADDR_STAT_BLOCK_DIFF_P_1           (ADR_BASE + 0x0424)
++#define    ADR_ADDR_BANK_ADDR_P0                  (ADR_BASE + 0x0428)
++#define    ADR_ADDR_BANK_ADDR_P1                  (ADR_BASE + 0x042C)
++#define    ADR_ADDR_BANK_ADDR_P2                  (ADR_BASE + 0x0430)
++#define    ADR_ADDR_BANK_ADDR_P3                  (ADR_BASE + 0x0434)
++#define    ADR_ADDR_BANK_NUMBER                   (ADR_BASE + 0x0438)
++#define    ADR_ADDR_FRAME_ADDR                    (ADR_BASE + 0x043C)
++#define    ADR_ADDR_FRAME_ID                      (ADR_BASE + 0x0440)
++#define    ADR_ADDR_FRAME_RATE                    (ADR_BASE + 0x0444)
++#define    ADR_ADDR_SHADOW_CTRL                   (ADR_BASE + 0x0448)
++#define    ADR_ADDR_DEBUG_SIGNAL_0                (ADR_BASE + 0x0450)
++#define    ADR_ADDR_DEBUG_SIGNAL_1                (ADR_BASE + 0x0454)
++#define    ADR_ADDR_DEBUG_SIGNAL_2                (ADR_BASE + 0x0458)
++#define    ADR_ADDR_DEBUG_SIGNAL_3                (ADR_BASE + 0x045C)
++#define    ADR_ADDR_DEBUG_SIGNAL_4                (ADR_BASE + 0x0460)
++#define    ADR_ADDR_DEBUG_SIGNAL_5                (ADR_BASE + 0x0464)
++
++//============================================================
++// IRINT
++//============================================================
++#define    IRINT_ADDR_T_VERSION                   (IRINT_BASE + 0x0000)
++#define    IRINT_ADDR_T_DBG_SEL                   (IRINT_BASE + 0x0004)
++#define    IRINT_ADDR_T_DBG_VALUE                 (IRINT_BASE + 0x0008)
++#define    IRINT_ADDR_DIFF_PAR                    (IRINT_BASE + 0x0010)
++#define    IRINT_ADDR_MIN_PAR                     (IRINT_BASE + 0x0014)
++
++//============================================================
++// DMSC
++//============================================================
++#define    DMSC_ADDR_SYNC                         (DMSC_BASE + 0x0000)
++#define    DMSC_ADDR_G_STD_STREN                  (DMSC_BASE + 0x0004)
++#define    DMSC_ADDR_UU_THRES                     (DMSC_BASE + 0x0008)
++#define    DMSC_ADDR_ALIAS_DIR_DIFF               (DMSC_BASE + 0x000C)
++#define    DMSC_ADDR_WIN5_HV_EDGE_THRES           (DMSC_BASE + 0x0010)
++#define    DMSC_ADDR_HV_EDGE_THRES                (DMSC_BASE + 0x0014)
++#define    DMSC_ADDR_HV_EDGE                      (DMSC_BASE + 0x0020)
++#define    DMSC_ADDR_AA_EDGE_THRES                (DMSC_BASE + 0x0024)
++#define    DMSC_ADDR_AA_EDGE                      (DMSC_BASE + 0x0028)
++#define    DMSC_ADDR_HVAA_EDGE_THRES              (DMSC_BASE + 0x002C)
++#define    DMSC_ADDR_HVAA_EDGE                    (DMSC_BASE + 0x0030)
++#define    DMSC_ADDR_ALIAS_STREN                  (DMSC_BASE + 0x0034)
++#define    DMSC_ADDR_ALIAS_THRES                  (DMSC_BASE + 0x0038)
++#define    DMSC_ADDR_NOR_ALIAS_BLUR               (DMSC_BASE + 0x003C)
++#define    DMSC_ADDR_NOR_UU_WEI_STREN             (DMSC_BASE + 0x0040)
++#define    DMSC_ADDR_SP_D_V2_SIGMA                (DMSC_BASE + 0x0044)
++#define    DMSC_ADDR_SP_D_W_SP_STREN              (DMSC_BASE + 0x0048)
++#define    DMSC_ADDR_SP_D_LL_STREN                (DMSC_BASE + 0x004C)
++#define    DMSC_ADDR_SP_D_LL_THRES                (DMSC_BASE + 0x0050)
++#define    DMSC_ADDR_SP_D_W_LIMIT                 (DMSC_BASE + 0x0054)
++#define    DMSC_ADDR_SP_D_B_LIMIT                 (DMSC_BASE + 0x0058)
++#define    DMSC_ADDR_SP_UD_V2_SIGMA               (DMSC_BASE + 0x005C)
++#define    DMSC_ADDR_SP_UD_W_SP_STREN             (DMSC_BASE + 0x0060)
++#define    DMSC_ADDR_SP_UD_LL_STREN               (DMSC_BASE + 0x0064)
++#define    DMSC_ADDR_SP_UD_LL_THRES               (DMSC_BASE + 0x0068)
++#define    DMSC_ADDR_SP_UD_W_LIMIT                (DMSC_BASE + 0x006C)
++#define    DMSC_ADDR_SP_UD_B_LIMIT                (DMSC_BASE + 0x0070)
++#define    DMSC_ADDR_SP_NOR_ALIAS_THRES           (DMSC_BASE + 0x0074)
++#define    DMSC_ADDR_ALIAS_FUSION_THRES           (DMSC_BASE + 0x0078)
++#define    DMSC_ADDR_ALIAS_DIR_INTP_SP_STREN      (DMSC_BASE + 0x007C)
++#define    DMSC_ADDR_FC_ALIAS_STREN               (DMSC_BASE + 0x0080)
++#define    DMSC_ADDR_FC_ALIAS_THRES               (DMSC_BASE + 0x0084)
++#define    DMSC_ADDR_FC_NOR_SAT_THRES             (DMSC_BASE + 0x0088)
++#define    DMSC_ADDR_FC_TEXT_THRES                (DMSC_BASE + 0x008C)
++#define    DMSC_ADDR_FC_NOR_EDGE_SLOPE            (DMSC_BASE + 0x0090)
++#define    DMSC_ADDR_UU_NP_ARRAY_RG0              (DMSC_BASE + 0x0094)
++#define    DMSC_ADDR_UU_NP_ARRAY_RG1              (DMSC_BASE + 0x0098)
++#define    DMSC_ADDR_UU_NP_ARRAY_RG2              (DMSC_BASE + 0x009C)
++#define    DMSC_ADDR_UU_NP_ARRAY_RG3              (DMSC_BASE + 0x00A0)
++#define    DMSC_ADDR_UU_NP_ARRAY_RG4              (DMSC_BASE + 0x00A4)
++#define    DMSC_ADDR_UU_NP_ARRAY_RG5              (DMSC_BASE + 0x00A8)
++#define    DMSC_ADDR_UU_NP_ARRAY_RG6              (DMSC_BASE + 0x00AC)
++#define    DMSC_ADDR_UU_NP_ARRAY_RG7              (DMSC_BASE + 0x00B0)
++#define    DMSC_ADDR_SP_D_SIGMA_3_NP_ARRAY_RG0    (DMSC_BASE + 0x00B4)
++#define    DMSC_ADDR_SP_D_SIGMA_3_NP_ARRAY_RG1    (DMSC_BASE + 0x00B8)
++#define    DMSC_ADDR_SP_D_SIGMA_3_NP_ARRAY_RG2    (DMSC_BASE + 0x00BC)
++#define    DMSC_ADDR_SP_D_W_WEI_NP_ARRAY_RG0      (DMSC_BASE + 0x00C0)
++#define    DMSC_ADDR_SP_D_W_WEI_NP_ARRAY_RG1      (DMSC_BASE + 0x00C4)
++#define    DMSC_ADDR_SP_D_W_WEI_NP_ARRAY_RG2      (DMSC_BASE + 0x00C8)
++#define    DMSC_ADDR_SP_D_W_WEI_NP_ARRAY_RG3      (DMSC_BASE + 0x00CC)
++#define    DMSC_ADDR_SP_D_B_WEI_NP_ARRAY_RG0      (DMSC_BASE + 0x00D0)
++#define    DMSC_ADDR_SP_D_B_WEI_NP_ARRAY_RG1      (DMSC_BASE + 0x00D4)
++#define    DMSC_ADDR_SP_D_B_WEI_NP_ARRAY_RG2      (DMSC_BASE + 0x00D8)
++#define    DMSC_ADDR_SP_D_B_WEI_NP_ARRAY_RG3      (DMSC_BASE + 0x00DC)
++#define    DMSC_ADDR_SP_UD_W_WEI_NP_ARRAY_RG0     (DMSC_BASE + 0x00E0)
++#define    DMSC_ADDR_SP_UD_W_WEI_NP_ARRAY_RG1     (DMSC_BASE + 0x00E4)
++#define    DMSC_ADDR_SP_UD_W_WEI_NP_ARRAY_RG2     (DMSC_BASE + 0x00E8)
++#define    DMSC_ADDR_SP_UD_W_WEI_NP_ARRAY_RG3     (DMSC_BASE + 0x00EC)
++#define    DMSC_ADDR_SP_UD_B_WEI_NP_ARRAY_RG0     (DMSC_BASE + 0x00F0)
++#define    DMSC_ADDR_SP_UD_B_WEI_NP_ARRAY_RG1     (DMSC_BASE + 0x00F4)
++#define    DMSC_ADDR_SP_UD_B_WEI_NP_ARRAY_RG2     (DMSC_BASE + 0x00F8)
++#define    DMSC_ADDR_SP_UD_B_WEI_NP_ARRAY_RG3     (DMSC_BASE + 0x00FC)
++#define    DMSC_ADDR_OUT_OPT                      (DMSC_BASE + 0x0100)
++#define    DMSC_ADDR_SP_DEBUG_REG_0               (DMSC_BASE + 0x0104)
++#define    DMSC_ADDR_SP_DEBUG_REG_1               (DMSC_BASE + 0x0108)
++#define    DMSC_ADDR_FC_TEXT_2_STREN              (DMSC_BASE + 0x010C)
++#define    DMSC_ADDR_FC_TEXT_2_THRES              (DMSC_BASE + 0x0110)
++#define    DMSC_ADDR_FC_THRES_H_1                 (DMSC_BASE + 0x0114)
++#define    DMSC_ADDR_FC_THRES_H_2                 (DMSC_BASE + 0x0118)
++
++//============================================================
++// CCM
++//============================================================
++#define    CCM_ADDR_REG_CTRL                      (CCM_BASE + 0x0000)
++#define    CCM_ADDR_CCM_RRRG                      (CCM_BASE + 0x0004)
++#define    CCM_ADDR_CCM_RBGR                      (CCM_BASE + 0x0008)
++#define    CCM_ADDR_CCM_GGGB                      (CCM_BASE + 0x000c)
++#define    CCM_ADDR_CCM_BRBG                      (CCM_BASE + 0x0010)
++#define    CCM_ADDR_CCM_BB                        (CCM_BASE + 0x0014)
++#define    CCM_ADDR_DP_CFG                        (CCM_BASE + 0x0018)
++#define    CCM_ADDR_DP_SLOP                       (CCM_BASE + 0x001c)
++#define    CCM_ADDR_SAT_THRES                     (CCM_BASE + 0x0020)
++
++//===============================================
++// DEFOG
++//===============================================
++#define    DEFOG_ADDR_BLOCK_COORD_M_01_00         (DEFOG_BASE + 0x0000)
++#define    DEFOG_ADDR_BLOCK_COORD_M_03_02         (DEFOG_BASE + 0x0004)
++#define    DEFOG_ADDR_BLOCK_COORD_M_05_04         (DEFOG_BASE + 0x0008)
++#define    DEFOG_ADDR_BLOCK_COORD_M_07_06         (DEFOG_BASE + 0x000C)
++#define    DEFOG_ADDR_BLOCK_COORD_M_09_08         (DEFOG_BASE + 0x0010)
++#define    DEFOG_ADDR_BLOCK_COORD_M____10         (DEFOG_BASE + 0x0014)
++#define    DEFOG_ADDR_BLOCK_COORD_N_01_00         (DEFOG_BASE + 0x0020)
++#define    DEFOG_ADDR_BLOCK_COORD_N_03_02         (DEFOG_BASE + 0x0024)
++#define    DEFOG_ADDR_BLOCK_COORD_N_05_04         (DEFOG_BASE + 0x0028)
++#define    DEFOG_ADDR_BLOCK_COORD_N_07_06         (DEFOG_BASE + 0x002C)
++#define    DEFOG_ADDR_BLOCK_COORD_N_09_08         (DEFOG_BASE + 0x0030)
++#define    DEFOG_ADDR_BLOCK_COORD_N_11_10         (DEFOG_BASE + 0x0034)
++#define    DEFOG_ADDR_BLOCK_COORD_N_13_12         (DEFOG_BASE + 0x0038)
++#define    DEFOG_ADDR_BLOCK_COORD_N_15_14         (DEFOG_BASE + 0x003C)
++#define    DEFOG_ADDR_BLOCK_COORD_N_17_16         (DEFOG_BASE + 0x0040)
++#define    DEFOG_ADDR_BLOCK_COORD_N_19_18         (DEFOG_BASE + 0x0044)
++#define    DEFOG_ADDR_BLOCK_COORD_N____20         (DEFOG_BASE + 0x0048)
++#define    DEFOG_ADDR_CT3X3_DIS_01_00             (DEFOG_BASE + 0x0050)
++#define    DEFOG_ADDR_CT3X3_DIS_03_02             (DEFOG_BASE + 0x0054)
++#define    DEFOG_ADDR_CT3X3_DIS_05_04             (DEFOG_BASE + 0x0058)
++#define    DEFOG_ADDR_CT3X3_DIS_07_06             (DEFOG_BASE + 0x005C)
++#define    DEFOG_ADDR_CT3X3_DIS_09_08             (DEFOG_BASE + 0x0060)
++#define    DEFOG_ADDR_CT3X3_DIS_11_10             (DEFOG_BASE + 0x0064)
++#define    DEFOG_ADDR_CT3X3_DIS_13_12             (DEFOG_BASE + 0x0068)
++#define    DEFOG_ADDR_CT3X3_DIS_15_14             (DEFOG_BASE + 0x006C)
++#define    DEFOG_ADDR_CT3X3_DIS_17_16             (DEFOG_BASE + 0x0070)
++#define    DEFOG_ADDR_CT3X3_DIS_19_18             (DEFOG_BASE + 0x0074)
++#define    DEFOG_ADDR_CT3X3_DIS_21_20             (DEFOG_BASE + 0x0078)
++#define    DEFOG_ADDR_CT3X3_DIS_23_22             (DEFOG_BASE + 0x007C)
++#define    DEFOG_ADDR_CT5X5_DIS_01_00             (DEFOG_BASE + 0x0080)
++#define    DEFOG_ADDR_CT5X5_DIS_03_02             (DEFOG_BASE + 0x0084)
++#define    DEFOG_ADDR_CT5X5_DIS_05_04             (DEFOG_BASE + 0x0088)
++#define    DEFOG_ADDR_CT5X5_DIS_07_06             (DEFOG_BASE + 0x008C)
++#define    DEFOG_ADDR_CT5X5_DIS_09_08             (DEFOG_BASE + 0x0090)
++#define    DEFOG_ADDR_CT5X5_DIS_11_10             (DEFOG_BASE + 0x0094)
++#define    DEFOG_ADDR_CT5X5_DIS_13_12             (DEFOG_BASE + 0x0098)
++#define    DEFOG_ADDR_CT5X5_DIS_15_14             (DEFOG_BASE + 0x009C)
++#define    DEFOG_ADDR_CT5X5_DIS_17_16             (DEFOG_BASE + 0x00A0)
++#define    DEFOG_ADDR_CT5X5_DIS_19_18             (DEFOG_BASE + 0x00A4)
++#define    DEFOG_ADDR_CT5X5_DIS_21_20             (DEFOG_BASE + 0x00A8)
++#define    DEFOG_ADDR_CT5X5_DIS_23_22             (DEFOG_BASE + 0x00AC)
++#define    DEFOG_ADDR_CT5X5_DIS_25_24             (DEFOG_BASE + 0x00B0)
++#define    DEFOG_ADDR_CT5X5_DIS_27_26             (DEFOG_BASE + 0x00B4)
++#define    DEFOG_ADDR_CT5X5_DIS_29_28             (DEFOG_BASE + 0x00B8)
++#define    DEFOG_ADDR_CT5X5_DIS_31_30             (DEFOG_BASE + 0x00BC)
++#define    DEFOG_ADDR_WEIGHTLUT02_05_00           (DEFOG_BASE + 0x00C0)
++#define    DEFOG_ADDR_WEIGHTLUT02_11_06           (DEFOG_BASE + 0x00C4)
++#define    DEFOG_ADDR_WEIGHTLUT02_17_12           (DEFOG_BASE + 0x00C8)
++#define    DEFOG_ADDR_WEIGHTLUT02_23_18           (DEFOG_BASE + 0x00CC)
++#define    DEFOG_ADDR_WEIGHTLUT02_29_24           (DEFOG_BASE + 0x00D0)
++#define    DEFOG_ADDR_WEIGHTLUT02_31_30           (DEFOG_BASE + 0x00D4)
++#define    DEFOG_ADDR_WEIGHTLUT20_05_00           (DEFOG_BASE + 0x00E0)
++#define    DEFOG_ADDR_WEIGHTLUT20_11_06           (DEFOG_BASE + 0x00E4)
++#define    DEFOG_ADDR_WEIGHTLUT20_17_12           (DEFOG_BASE + 0x00E8)
++#define    DEFOG_ADDR_WEIGHTLUT20_23_18           (DEFOG_BASE + 0x00EC)
++#define    DEFOG_ADDR_WEIGHTLUT20_29_24           (DEFOG_BASE + 0x00F0)
++#define    DEFOG_ADDR_WEIGHTLUT20_31_30           (DEFOG_BASE + 0x00F4)
++#define    DEFOG_ADDR_WEIGHTLUT21_05_00           (DEFOG_BASE + 0x0100)
++#define    DEFOG_ADDR_WEIGHTLUT21_11_06           (DEFOG_BASE + 0x0104)
++#define    DEFOG_ADDR_WEIGHTLUT21_17_12           (DEFOG_BASE + 0x0108)
++#define    DEFOG_ADDR_WEIGHTLUT21_23_18           (DEFOG_BASE + 0x010C)
++#define    DEFOG_ADDR_WEIGHTLUT21_29_24           (DEFOG_BASE + 0x0110)
++#define    DEFOG_ADDR_WEIGHTLUT21_31_30           (DEFOG_BASE + 0x0114)
++#define    DEFOG_ADDR_WEIGHTLUT12_05_00           (DEFOG_BASE + 0x0120)
++#define    DEFOG_ADDR_WEIGHTLUT12_11_06           (DEFOG_BASE + 0x0124)
++#define    DEFOG_ADDR_WEIGHTLUT12_17_12           (DEFOG_BASE + 0x0128)
++#define    DEFOG_ADDR_WEIGHTLUT12_23_18           (DEFOG_BASE + 0x012C)
++#define    DEFOG_ADDR_WEIGHTLUT12_29_24           (DEFOG_BASE + 0x0130)
++#define    DEFOG_ADDR_WEIGHTLUT12_31_30           (DEFOG_BASE + 0x0134)
++#define    DEFOG_ADDR_WEIGHTLUT22_05_00           (DEFOG_BASE + 0x0140)
++#define    DEFOG_ADDR_WEIGHTLUT22_11_06           (DEFOG_BASE + 0x0144)
++#define    DEFOG_ADDR_WEIGHTLUT22_17_12           (DEFOG_BASE + 0x0148)
++#define    DEFOG_ADDR_WEIGHTLUT22_23_18           (DEFOG_BASE + 0x014C)
++#define    DEFOG_ADDR_WEIGHTLUT22_29_24           (DEFOG_BASE + 0x0150)
++#define    DEFOG_ADDR_WEIGHTLUT22_31_30           (DEFOG_BASE + 0x0154)
++#define    DEFOG_ADDR_BANK_BUFF_NUM               (DEFOG_BASE + 0x0160)
++#define    DEFOG_ADDR_BANK_ADDR_0                 (DEFOG_BASE + 0x0164)
++#define    DEFOG_ADDR_BANK_ADDR_1                 (DEFOG_BASE + 0x0168)
++#define    DEFOG_ADDR_BANK_ADDR_2                 (DEFOG_BASE + 0x016C)
++#define    DEFOG_ADDR_BANK_ADDR_3                 (DEFOG_BASE + 0x0170)
++#define    DEFOG_ADDR_PARA                        (DEFOG_BASE + 0x0180)
++#define    DEFOG_ADDR_CLOR_CTRL_X3210             (DEFOG_BASE + 0x0190)
++#define    DEFOG_ADDR_CLOR_CTRL_Y3210             (DEFOG_BASE + 0x0194)
++#define    DEFOG_ADDR_CLOR_CTRL_XY44              (DEFOG_BASE + 0x0198)
++#define    DEFOG_ADDR_CLOR_CTRL_POW3210           (DEFOG_BASE + 0x019C)
++#define    DEFOG_ADDR_TRANS_DARK_CTRL_X3210       (DEFOG_BASE + 0x01A0)
++#define    DEFOG_ADDR_TRANS_DARK_CTRL_Y3210       (DEFOG_BASE + 0x01A4)
++#define    DEFOG_ADDR_TRANS_DARK_CTRL_XY44        (DEFOG_BASE + 0x01A8)
++#define    DEFOG_ADDR_TRANS_DARK_CTRL_POW3210     (DEFOG_BASE + 0x01AC)
++#define    DEFOG_ADDR_OVEREXPO_WGT_X3210          (DEFOG_BASE + 0x01B0)
++#define    DEFOG_ADDR_OVEREXPO_WGT_Y3210          (DEFOG_BASE + 0x01B4)
++#define    DEFOG_ADDR_OVEREXPO_WGT_POW210         (DEFOG_BASE + 0x01B8)
++#define    DEFOG_ADDR_DARKSPC_WGT_X3210           (DEFOG_BASE + 0x01C0)
++#define    DEFOG_ADDR_DARKSPC_WGT_Y3210           (DEFOG_BASE + 0x01C4)
++#define    DEFOG_ADDR_DARKSPC_WGT_POW210          (DEFOG_BASE + 0x01C8)
++#define    DEFOG_ADDR_FRAME_RATE                  (DEFOG_BASE + 0x01D0)
++#define    DEFOG_ADDR_CTRL                        (DEFOG_BASE + 0x01E0)
++#define    DEFOG_ADDR_FRAME_ADDR                  (DEFOG_BASE + 0x0200)
++#define    DEFOG_ADDR_FRAME_ID                    (DEFOG_BASE + 0x0204)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_0              (DEFOG_BASE + 0x0208)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_1              (DEFOG_BASE + 0x020C)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_2              (DEFOG_BASE + 0x0210)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_3              (DEFOG_BASE + 0x0214)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_4              (DEFOG_BASE + 0x0218)
++#define    DEFOG_ADDR_BLOCK_CFG_SEL		  (DEFOG_BASE + 0x0220)
++#define	   DEFOG_ADDR_BLOCK_CFG_BASE		  (DEFOG_BASE + 0x0224)
++
++//============================================================
++// CSC
++//============================================================
++#define    CSC_ADDR_CTRL                          (CSC_BASE + 0x0000)
++#define    CSC_ADDR_SUB                           (CSC_BASE + 0x0004)
++#define    CSC_ADDR_PAR_0                         (CSC_BASE + 0x0010)
++#define    CSC_ADDR_PAR_1                         (CSC_BASE + 0x0014)
++#define    CSC_ADDR_PAR_2                         (CSC_BASE + 0x0018)
++#define    CSC_ADDR_OFF_SET                       (CSC_BASE + 0x0020)
++#define    CSC_ADDR_CLIP                          (CSC_BASE + 0x0030)
++
++//============================================================
++// CLM
++//============================================================
++#define    CLM_ADDR_REG_CTRL                      (CLM_BASE + 0x0000)
++#define    CLM_ADDR_LUT_SHIFT                     (CLM_BASE + 0x0004)
++#define    CLM_ADDR_CSC_RB                        (CLM_BASE + 0x0008)
++#define    CLM_ADDR_CSC_G                         (CLM_BASE + 0x000c)
++#define    CLM_ADDR_CSC_U                         (CLM_BASE + 0x0010)
++#define    CLM_ADDR_CSC_V                         (CLM_BASE + 0x0014)
++#define    CLM_ADDR_CSC_Y                         (CLM_BASE + 0x0018)
++#define    CLM_ADDR_CA_S_THRES                    (CLM_BASE + 0x001c)
++#define    CLM_ADDR_CA_S_SLOP                     (CLM_BASE + 0x0020)
++#define    CLM_ADDR_CA_V_THRES                    (CLM_BASE + 0x0024)
++#define    CLM_ADDR_CA_V_SLOP                     (CLM_BASE + 0x0028)
++#define    CLM_ADDR_DEBUG0                        (CLM_BASE + 0x002c)
++
++//============================================================
++// Sharpen
++//============================================================
++#define    SHARPEN_ADDR_SYNC                  (SP_BASE + 0x0000)
++#define    SHARPEN_ADDR_STD_DIV_OPT           (SP_BASE + 0x0004)
++#define    SHARPEN_ADDR_V2_SIGMA              (SP_BASE + 0x0008)
++#define    SHARPEN_ADDR_W_WEI_SEG_OPT         (SP_BASE + 0x000C)
++#define    SHARPEN_ADDR_STREN                 (SP_BASE + 0x0010)
++#define    SHARPEN_ADDR_THRES                 (SP_BASE + 0x0014)
++#define    SHARPEN_ADDR_UU_SLOPE              (SP_BASE + 0x0018)
++#define    SHARPEN_ADDR_UU_NP_ARRAY_RG0       (SP_BASE + 0x001C)
++#define    SHARPEN_ADDR_UU_NP_ARRAY_RG1       (SP_BASE + 0x0020)
++#define    SHARPEN_ADDR_UU_NP_ARRAY_RG2       (SP_BASE + 0x0024)
++#define    SHARPEN_ADDR_UU_NP_ARRAY_RG3       (SP_BASE + 0x0028)
++#define    SHARPEN_ADDR_V1_SIGMA_NP_ARRAY_RG0 (SP_BASE + 0x002C)
++#define    SHARPEN_ADDR_V1_SIGMA_NP_ARRAY_RG1 (SP_BASE + 0x0030)
++#define    SHARPEN_ADDR_V1_SIGMA_NP_ARRAY_RG2 (SP_BASE + 0x0034)
++#define    SHARPEN_ADDR_W_WEI_NP_ARRAY_RG0    (SP_BASE + 0x0038)
++#define    SHARPEN_ADDR_W_WEI_NP_ARRAY_RG1    (SP_BASE + 0x003C)
++#define    SHARPEN_ADDR_W_WEI_NP_ARRAY_RG2    (SP_BASE + 0x0040)
++#define    SHARPEN_ADDR_W_WEI_NP_ARRAY_RG3    (SP_BASE + 0x0044)
++#define    SHARPEN_ADDR_B_WEI_NP_ARRAY_RG0    (SP_BASE + 0x0048)
++#define    SHARPEN_ADDR_B_WEI_NP_ARRAY_RG1    (SP_BASE + 0x004C)
++#define    SHARPEN_ADDR_B_WEI_NP_ARRAY_RG2    (SP_BASE + 0x0050)
++#define    SHARPEN_ADDR_B_WEI_NP_ARRAY_RG3    (SP_BASE + 0x0054)
++
++//============================================================
++// MDNS
++//============================================================
++#define    MDNS_ADDR_T_VERSION                    (MDNS_BASE + 0x0000)
++#define    MDNS_ADDR_REG_CTRL                     (MDNS_BASE + 0x0004)
++#define    MDNS_ADDR_DBG_SEL                      (MDNS_BASE + 0x0008)
++#define    MDNS_ADDR_DBG_VALUE                    (MDNS_BASE + 0x000C)
++#define    MDNS_ADDR_Y_REF_BASE_ADDR              (MDNS_BASE + 0x0010)
++#define    MDNS_ADDR_Y_REF_STRIDE                 (MDNS_BASE + 0x0014)
++#define    MDNS_ADDR_Y_REF_FRM_SIZE               (MDNS_BASE + 0x0018)
++#define    MDNS_ADDR_Y_REF_FRM_NUM                (MDNS_BASE + 0x001C)
++#define    MDNS_ADDR_UV_REF_BASE_ADDR             (MDNS_BASE + 0x0020)
++#define    MDNS_ADDR_UV_REF_STRIDE                (MDNS_BASE + 0x0024)
++#define    MDNS_ADDR_UV_REF_FRM_SIZE              (MDNS_BASE + 0x0028)
++#define    MDNS_ADDR_UV_REF_FRM_NUM               (MDNS_BASE + 0x002C)
++#define    MDNS_ADDR_STA_BASE_ADDR                (MDNS_BASE + 0x0030)
++#define    MDNS_ADDR_STA_STRIDE                   (MDNS_BASE + 0x0034)
++#define    MDNS_ADDR_STA_FRM_SIZE                 (MDNS_BASE + 0x0038)
++#define    MDNS_ADDR_STA_FRM_NUM                  (MDNS_BASE + 0x003C)
++#define    MDNS_ADDR_PBT_BASE_ADDR                (MDNS_BASE + 0x0040)
++#define    MDNS_ADDR_PBT_STRIDE                   (MDNS_BASE + 0x0044)
++#define    MDNS_ADDR_PBT_FRM_SIZE                 (MDNS_BASE + 0x0048)
++#define    MDNS_ADDR_PBT_FRM_NUM                  (MDNS_BASE + 0x004C)
++#define    MDNS_ADDR_T_FRM_NUM                    (MDNS_BASE + 0x0050)
++#define    MDNS_ADDR_T_TOP_FUN                    (MDNS_BASE + 0x0060)
++#define    MDNS_ADDR_STA_OVER_CFG                 (MDNS_BASE + 0x0070)
++#define    MDNS_ADDR_STA_WIN_CFG                  (MDNS_BASE + 0x0074)
++#define    MDNS_ADDR_STA_BLK_SIZE                 (MDNS_BASE + 0x0078)
++#define    MDNS_ADDR_STA_BLK_NUM                  (MDNS_BASE + 0x007C)
++#define    MDNS_ADDR_STA_MAX_NUM                  (MDNS_BASE + 0x0080)
++#define    MDNS_ADDR_STA_DIFF_THRES               (MDNS_BASE + 0x0084)
++#define    MDNS_ADDR_STA_MV_NUM_THRES00           (MDNS_BASE + 0x0090)
++#define    MDNS_ADDR_STA_MV_NUM_THRES01           (MDNS_BASE + 0x0094)
++#define    MDNS_ADDR_STA_MV_NUM_THRES10           (MDNS_BASE + 0x0098)
++#define    MDNS_ADDR_STA_MV_NUM_THRES11           (MDNS_BASE + 0x009C)
++#define    MDNS_ADDR_PBT_START_POINT              (MDNS_BASE + 0x00A0)
++#define    MDNS_ADDR_PBT_WIN_SIZE                 (MDNS_BASE + 0x00A4)
++#define    MDNS_ADDR_PBT_OVER_CFG                 (MDNS_BASE + 0x00B0)
++#define    MDNS_ADDR_PBT_WIN_CFG                  (MDNS_BASE + 0x00B4)
++#define    MDNS_ADDR_PBT_BLK_SIZE                 (MDNS_BASE + 0x00B8)
++#define    MDNS_ADDR_PBT_BLK_NUM                  (MDNS_BASE + 0x00BC)
++#define    MDNS_ADDR_PBT_MAX_NUM                  (MDNS_BASE + 0x00C0)
++#define    MDNS_ADDR_PBT_DIFF_THRES               (MDNS_BASE + 0x00C4)
++#define    MDNS_ADDR_PBT_MV_NUM_THRES00           (MDNS_BASE + 0x00D0)
++#define    MDNS_ADDR_PBT_MV_NUM_THRES01           (MDNS_BASE + 0x00D4)
++#define    MDNS_ADDR_PBT_MV_NUM_THRES10           (MDNS_BASE + 0x00D8)
++#define    MDNS_ADDR_PBT_MV_NUM_THRES11           (MDNS_BASE + 0x00DC)
++#define    MDNS_ADDR_Y_CUT_VALUE                  (MDNS_BASE + 0x00E0)
++#define    MDNS_ADDR_Y_EDGE_PAR                   (MDNS_BASE + 0x00E4)
++#define    MDNS_ADDR_Y_BI_PAR0                    (MDNS_BASE + 0x00E8)
++#define    MDNS_ADDR_Y_BI_PAR1                    (MDNS_BASE + 0x00EC)
++#define    MDNS_ADDR_Y_TCA_PAR                    (MDNS_BASE + 0x00F0)
++#define    MDNS_ADDR_Y_TEA_T_PAR0                 (MDNS_BASE + 0x00F4)
++#define    MDNS_ADDR_Y_TEA_T_PAR1                 (MDNS_BASE + 0x00F8)
++#define    MDNS_ADDR_Y_TEA_V_PAR0                 (MDNS_BASE + 0x00FC)
++#define    MDNS_ADDR_Y_TEA_V_PAR1                 (MDNS_BASE + 0x0100)
++#define    MDNS_ADDR_Y_TEA_W_PAR0                 (MDNS_BASE + 0x0104)
++#define    MDNS_ADDR_Y_TEA_W_PAR1                 (MDNS_BASE + 0x0108)
++#define    MDNS_ADDR_Y_TLA_WIN_OPT                (MDNS_BASE + 0x010C)
++#define    MDNS_ADDR_Y_TLA_T_PAR0                 (MDNS_BASE + 0x0110)
++#define    MDNS_ADDR_Y_TLA_T_PAR1                 (MDNS_BASE + 0x0114)
++#define    MDNS_ADDR_Y_TLA_T_PAR2                 (MDNS_BASE + 0x0118)
++#define    MDNS_ADDR_Y_TLA_T_PAR3                 (MDNS_BASE + 0x011C)
++#define    MDNS_ADDR_Y_TLA_V_PAR0                 (MDNS_BASE + 0x0120)
++#define    MDNS_ADDR_Y_TLA_V_PAR1                 (MDNS_BASE + 0x0124)
++#define    MDNS_ADDR_Y_TLA_V_PAR2                 (MDNS_BASE + 0x0128)
++#define    MDNS_ADDR_Y_TLA_V_PAR3                 (MDNS_BASE + 0x012C)
++#define    MDNS_ADDR_Y_TLA_W_PAR0                 (MDNS_BASE + 0x0130)
++#define    MDNS_ADDR_Y_TLA_W_PAR1                 (MDNS_BASE + 0x0134)
++#define    MDNS_ADDR_Y_TLA_W_PAR2                 (MDNS_BASE + 0x0138)
++#define    MDNS_ADDR_Y_TLA_W_PAR3                 (MDNS_BASE + 0x013C)
++#define    MDNS_ADDR_Y_SAD_CFG                    (MDNS_BASE + 0x0140)
++#define    MDNS_ADDR_Y_STA_WEI_PAR0               (MDNS_BASE + 0x0150)
++#define    MDNS_ADDR_Y_STA_WEI_PAR1               (MDNS_BASE + 0x0154)
++#define    MDNS_ADDR_Y_STA_WEI_PAR2               (MDNS_BASE + 0x0158)
++#define    MDNS_ADDR_Y_STA_WEI_PAR3               (MDNS_BASE + 0x015C)
++#define    MDNS_ADDR_Y_STA_WEI_PAR4               (MDNS_BASE + 0x0160)
++#define    MDNS_ADDR_Y_STA_WEI_PAR5               (MDNS_BASE + 0x0164)
++#define    MDNS_ADDR_Y_STA_WEI_PAR6               (MDNS_BASE + 0x0168)
++#define    MDNS_ADDR_Y_STA_WEI_PAR7               (MDNS_BASE + 0x016C)
++#define    MDNS_ADDR_Y_STA_WEI_PAR8               (MDNS_BASE + 0x0170)
++#define    MDNS_ADDR_Y_STA_WEI_PAR9               (MDNS_BASE + 0x0174)
++#define    MDNS_ADDR_Y_STA_WEI_PARa               (MDNS_BASE + 0x0178)
++#define    MDNS_ADDR_Y_STA_WEI_PARb               (MDNS_BASE + 0x017C)
++#define    MDNS_ADDR_Y_STA_WEI_PARc               (MDNS_BASE + 0x0180)
++#define    MDNS_ADDR_Y_STA_WEI_PARd               (MDNS_BASE + 0x0184)
++#define    MDNS_ADDR_Y_STA_WEI_PARe               (MDNS_BASE + 0x0188)
++#define    MDNS_ADDR_Y_STA_WEI_PARf               (MDNS_BASE + 0x018C)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR0               (MDNS_BASE + 0x0190)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR1               (MDNS_BASE + 0x0194)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR2               (MDNS_BASE + 0x0198)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR3               (MDNS_BASE + 0x019C)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR4               (MDNS_BASE + 0x01A0)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR5               (MDNS_BASE + 0x01A4)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR6               (MDNS_BASE + 0x01A8)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR7               (MDNS_BASE + 0x01AC)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR8               (MDNS_BASE + 0x01B0)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR9               (MDNS_BASE + 0x01B4)
++#define    MDNS_ADDR_Y_PBT_WEI_PARa               (MDNS_BASE + 0x01B8)
++#define    MDNS_ADDR_Y_PBT_WEI_PARb               (MDNS_BASE + 0x01BC)
++#define    MDNS_ADDR_Y_PBT_WEI_PARc               (MDNS_BASE + 0x01C0)
++#define    MDNS_ADDR_Y_PBT_WEI_PARd               (MDNS_BASE + 0x01C4)
++#define    MDNS_ADDR_Y_PBT_WEI_PARe               (MDNS_BASE + 0x01C8)
++#define    MDNS_ADDR_Y_PBT_WEI_PARf               (MDNS_BASE + 0x01CC)
++#define    MDNS_ADDR_Y_WSA_S_PAR                  (MDNS_BASE + 0x01D0)
++#define    MDNS_ADDR_Y_WSA_M_PAR                  (MDNS_BASE + 0x01D4)
++#define    MDNS_ADDR_Y_WFA_PAR                    (MDNS_BASE + 0x01D8)
++#define    MDNS_ADDR_Y_REF_WEI_LMT                (MDNS_BASE + 0x01DC)
++#define    MDNS_ADDR_Y_REF_WEI_SGM_X_PAR0         (MDNS_BASE + 0x01E0)
++#define    MDNS_ADDR_Y_REF_WEI_SGM_X_PAR1         (MDNS_BASE + 0x01E4)
++#define    MDNS_ADDR_Y_REF_WEI_SGM_X_PAR2         (MDNS_BASE + 0x01E8)
++#define    MDNS_ADDR_Y_REF_WEI_SGM_Y_PAR0         (MDNS_BASE + 0x01EC)
++#define    MDNS_ADDR_Y_REF_WEI_SGM_Y_PAR1         (MDNS_BASE + 0x01F0)
++#define    MDNS_ADDR_Y_REF_WEI_SGM_S_PAR0         (MDNS_BASE + 0x01F4)
++#define    MDNS_ADDR_Y_REF_WEI_SGM_S_PAR1         (MDNS_BASE + 0x01F8)
++#define    MDNS_ADDR_Y_FS_MV_JUDGE_THRES          (MDNS_BASE + 0x01FC)
++#define    MDNS_ADDR_Y_FS_S_CUR_SHP_WIN_OPT       (MDNS_BASE + 0x0200)
++#define    MDNS_ADDR_Y_FS_S_CUR_SHP_STREN_P0      (MDNS_BASE + 0x0204)
++#define    MDNS_ADDR_Y_FS_S_CUR_SHP_STREN_P1      (MDNS_BASE + 0x0208)
++#define    MDNS_ADDR_Y_FS_S_CUR_SHP_STREN_P2      (MDNS_BASE + 0x020C)
++#define    MDNS_ADDR_Y_FS_S_CUR_SHP_STREN_P3      (MDNS_BASE + 0x0210)
++#define    MDNS_ADDR_Y_FS_S_REF_SHP_WIN_OPT       (MDNS_BASE + 0x0214)
++#define    MDNS_ADDR_Y_FS_S_REF_SHP_STREN_P0      (MDNS_BASE + 0x0218)
++#define    MDNS_ADDR_Y_FS_S_REF_SHP_STREN_P1      (MDNS_BASE + 0x021C)
++#define    MDNS_ADDR_Y_FS_S_REF_SHP_STREN_P2      (MDNS_BASE + 0x0220)
++#define    MDNS_ADDR_Y_FS_S_REF_SHP_STREN_P3      (MDNS_BASE + 0x0224)
++#define    MDNS_ADDR_Y_FS_S_SHP_WEI               (MDNS_BASE + 0x0228)
++#define    MDNS_ADDR_Y_FS_M_CUR_SHP_WIN_OPT       (MDNS_BASE + 0x022C)
++#define    MDNS_ADDR_Y_FS_M_CUR_SHP_STREN_P0      (MDNS_BASE + 0x0230)
++#define    MDNS_ADDR_Y_FS_M_CUR_SHP_STREN_P1      (MDNS_BASE + 0x0234)
++#define    MDNS_ADDR_Y_FS_M_CUR_SHP_STREN_P2      (MDNS_BASE + 0x0238)
++#define    MDNS_ADDR_Y_FS_M_CUR_SHP_STREN_P3      (MDNS_BASE + 0x023C)
++#define    MDNS_ADDR_Y_FS_M_REF_SHP_WIN_OPT       (MDNS_BASE + 0x0240)
++#define    MDNS_ADDR_Y_FS_M_REF_SHP_STREN_P0      (MDNS_BASE + 0x0244)
++#define    MDNS_ADDR_Y_FS_M_REF_SHP_STREN_P1      (MDNS_BASE + 0x0248)
++#define    MDNS_ADDR_Y_FS_M_REF_SHP_STREN_P2      (MDNS_BASE + 0x024C)
++#define    MDNS_ADDR_Y_FS_M_REF_SHP_STREN_P3      (MDNS_BASE + 0x0250)
++#define    MDNS_ADDR_Y_FS_M_SHP_WEI               (MDNS_BASE + 0x0254)
++#define    MDNS_ADDR_Y_FS_SHP_CUR_STA_WEI_P0      (MDNS_BASE + 0x0258)
++#define    MDNS_ADDR_Y_FS_SHP_CUR_STA_WEI_P1      (MDNS_BASE + 0x025C)
++#define    MDNS_ADDR_Y_FS_SHP_REF_STA_WEI_P0      (MDNS_BASE + 0x0260)
++#define    MDNS_ADDR_Y_FS_SHP_REF_STA_WEI_P1      (MDNS_BASE + 0x0264)
++#define    MDNS_ADDR_Y_FS_SHP_CUR_FLUCT_PAR       (MDNS_BASE + 0x0268)
++#define    MDNS_ADDR_Y_FS_SHP_REF_FLUCT_PAR       (MDNS_BASE + 0x026C)
++#define    MDNS_ADDR_UV_CUT_VALUE                 (MDNS_BASE + 0x0280)
++#define    MDNS_ADDR_UV_SAD_CFG                   (MDNS_BASE + 0x0284)
++#define    MDNS_ADDR_UV_TCA_PAR                   (MDNS_BASE + 0x0290)
++#define    MDNS_ADDR_UV_TMA_T_PAR0                (MDNS_BASE + 0x0294)
++#define    MDNS_ADDR_UV_TMA_T_PAR1                (MDNS_BASE + 0x0298)
++#define    MDNS_ADDR_UV_TMA_V_PAR0                (MDNS_BASE + 0x029C)
++#define    MDNS_ADDR_UV_TMA_V_PAR1                (MDNS_BASE + 0x02a0)
++#define    MDNS_ADDR_UV_TMA_W_PAR0                (MDNS_BASE + 0x02a4)
++#define    MDNS_ADDR_UV_TMA_W_PAR1                (MDNS_BASE + 0x02a8)
++#define    MDNS_ADDR_UV_STA_WEI_PAR0              (MDNS_BASE + 0x02b0)
++#define    MDNS_ADDR_UV_STA_WEI_PAR1              (MDNS_BASE + 0x02b4)
++#define    MDNS_ADDR_UV_STA_WEI_PAR2              (MDNS_BASE + 0x02b8)
++#define    MDNS_ADDR_UV_STA_WEI_PAR3              (MDNS_BASE + 0x02bC)
++#define    MDNS_ADDR_UV_STA_WEI_PAR4              (MDNS_BASE + 0x02c0)
++#define    MDNS_ADDR_UV_STA_WEI_PAR5              (MDNS_BASE + 0x02c4)
++#define    MDNS_ADDR_UV_STA_WEI_PAR6              (MDNS_BASE + 0x02c8)
++#define    MDNS_ADDR_UV_STA_WEI_PAR7              (MDNS_BASE + 0x02cC)
++#define    MDNS_ADDR_UV_STA_WEI_PAR8              (MDNS_BASE + 0x02d0)
++#define    MDNS_ADDR_UV_STA_WEI_PAR9              (MDNS_BASE + 0x02d4)
++#define    MDNS_ADDR_UV_STA_WEI_PARa              (MDNS_BASE + 0x02d8)
++#define    MDNS_ADDR_UV_STA_WEI_PARb              (MDNS_BASE + 0x02dC)
++#define    MDNS_ADDR_UV_STA_WEI_PARc              (MDNS_BASE + 0x02e0)
++#define    MDNS_ADDR_UV_STA_WEI_PARd              (MDNS_BASE + 0x02e4)
++#define    MDNS_ADDR_UV_STA_WEI_PARe              (MDNS_BASE + 0x02e8)
++#define    MDNS_ADDR_UV_STA_WEI_PARf              (MDNS_BASE + 0x02eC)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR0              (MDNS_BASE + 0x02f0)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR1              (MDNS_BASE + 0x02f4)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR2              (MDNS_BASE + 0x02f8)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR3              (MDNS_BASE + 0x02fC)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR4              (MDNS_BASE + 0x0300)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR5              (MDNS_BASE + 0x0304)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR6              (MDNS_BASE + 0x0308)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR7              (MDNS_BASE + 0x030C)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR8              (MDNS_BASE + 0x0310)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR9              (MDNS_BASE + 0x0314)
++#define    MDNS_ADDR_UV_PBT_WEI_PARa              (MDNS_BASE + 0x0318)
++#define    MDNS_ADDR_UV_PBT_WEI_PARb              (MDNS_BASE + 0x031C)
++#define    MDNS_ADDR_UV_PBT_WEI_PARc              (MDNS_BASE + 0x0320)
++#define    MDNS_ADDR_UV_PBT_WEI_PARd              (MDNS_BASE + 0x0324)
++#define    MDNS_ADDR_UV_PBT_WEI_PARe              (MDNS_BASE + 0x0328)
++#define    MDNS_ADDR_UV_PBT_WEI_PARf              (MDNS_BASE + 0x032C)
++#define    MDNS_ADDR_UV_WSA_S_PAR                 (MDNS_BASE + 0x0330)
++#define    MDNS_ADDR_UV_WSA_M_PAR                 (MDNS_BASE + 0x0334)
++#define    MDNS_ADDR_UV_REF_WEI_LMT               (MDNS_BASE + 0x0338)
++#define    MDNS_ADDR_UV_REF_WEI_SGM_X_PAR0        (MDNS_BASE + 0x0340)
++#define    MDNS_ADDR_UV_REF_WEI_SGM_X_PAR1        (MDNS_BASE + 0x0344)
++#define    MDNS_ADDR_UV_REF_WEI_SGM_X_PAR2        (MDNS_BASE + 0x0348)
++#define    MDNS_ADDR_UV_REF_WEI_SGM_Y_PAR0        (MDNS_BASE + 0x034C)
++#define    MDNS_ADDR_UV_REF_WEI_SGM_Y_PAR1        (MDNS_BASE + 0x0350)
++#define    MDNS_ADDR_UV_REF_WEI_SGM_S_PAR0        (MDNS_BASE + 0x0354)
++#define    MDNS_ADDR_UV_REF_WEI_SGM_S_PAR1        (MDNS_BASE + 0x0358)
++#define    MDNS_ADDR_UV_FS_MV_JUDGE_THRES         (MDNS_BASE + 0x035C)
++#define    MDNS_ADDR_UV_FC_TYPE                   (MDNS_BASE + 0x0360)
++#define    MDNS_ADDR_UV_FC_S_PAR0                 (MDNS_BASE + 0x0370)
++#define    MDNS_ADDR_UV_FC_S_PAR1                 (MDNS_BASE + 0x0374)
++#define    MDNS_ADDR_UV_FC_M_PAR0                 (MDNS_BASE + 0x0378)
++#define    MDNS_ADDR_UV_FC_M_PAR1                 (MDNS_BASE + 0x037C)
++#define    MDNS_ADDR_UV_BLUR_WEI                  (MDNS_BASE + 0x0380)
++
++//============================================================
++// SDNS
++//============================================================
++#define    SDNS_ADDR_T_VERSION                    (SDNS_BASE + 0x0000)
++#define    SDNS_ADDR_REG_CTRL                     (SDNS_BASE + 0x0004)
++#define    SDNS_ADDR_DBG_SEL                      (SDNS_BASE + 0x0008)
++#define    SDNS_ADDR_DBG_VALUE                    (SDNS_BASE + 0x000C)
++#define    SDNS_ADDR_Y_FUN_EN                     (SDNS_BASE + 0x0010)
++#define    SDNS_ADDR_Y_COM_PAR0                   (SDNS_BASE + 0x0014)
++#define    SDNS_ADDR_Y_COM_PAR1                   (SDNS_BASE + 0x0018)
++#define    SDNS_ADDR_Y_FUSION_PAR0                (SDNS_BASE + 0x001C)
++#define    SDNS_ADDR_Y_FUSION_PAR1                (SDNS_BASE + 0x0020)
++#define    SDNS_ADDR_Y_FUSION_PAR2                (SDNS_BASE + 0x0024)
++#define    SDNS_ADDR_Y_FUSION_PAR3                (SDNS_BASE + 0x0028)
++#define    SDNS_ADDR_Y_DETAIL_PAR0                (SDNS_BASE + 0x002C)
++#define    SDNS_ADDR_Y_DETAIL_PAR1                (SDNS_BASE + 0x0030)
++#define    SDNS_ADDR_Y_DETAIL_PAR2                (SDNS_BASE + 0x0034)
++#define    SDNS_ADDR_Y_DETAIL_PAR3                (SDNS_BASE + 0x0038)
++#define    SDNS_ADDR_Y_LUMA_PAR0                  (SDNS_BASE + 0x003C)
++#define    SDNS_ADDR_Y_LUMA_PAR1                  (SDNS_BASE + 0x0040)
++#define    SDNS_ADDR_Y_LUMA_PAR2                  (SDNS_BASE + 0x0044)
++#define    SDNS_ADDR_Y_LUMA_PAR3                  (SDNS_BASE + 0x0048)
++#define    SDNS_ADDR_Y_BSHP_PAR0                  (SDNS_BASE + 0x004C)
++#define    SDNS_ADDR_Y_BSHP_PAR1                  (SDNS_BASE + 0x0050)
++#define    SDNS_ADDR_Y_BSHP_PAR2                  (SDNS_BASE + 0x0054)
++#define    SDNS_ADDR_Y_BSHP_PAR3                  (SDNS_BASE + 0x0058)
++#define    SDNS_ADDR_Y_DSHP_PAR0                  (SDNS_BASE + 0x005C)
++#define    SDNS_ADDR_Y_DSHP_PAR1                  (SDNS_BASE + 0x0060)
++#define    SDNS_ADDR_Y_DSHP_PAR2                  (SDNS_BASE + 0x0064)
++#define    SDNS_ADDR_Y_DSHP_PAR3                  (SDNS_BASE + 0x0068)
++#define    SDNS_ADDR_Y_BI_PAR0                    (SDNS_BASE + 0x006C)
++#define    SDNS_ADDR_Y_BI_PAR1                    (SDNS_BASE + 0x0070)
++#define    SDNS_ADDR_Y_BI_PAR2                    (SDNS_BASE + 0x0074)
++#define    SDNS_ADDR_Y_BI_PAR3                    (SDNS_BASE + 0x0078)
++#define    SDNS_ADDR_UV_FUN_EN                    (SDNS_BASE + 0x0080)
++#define    SDNS_ADDR_UV_COM_PAR                   (SDNS_BASE + 0x0084)
++#define    SDNS_ADDR_UV_FUSION_PAR0               (SDNS_BASE + 0x0088)
++#define    SDNS_ADDR_UV_FUSION_PAR1               (SDNS_BASE + 0x008C)
++#define    SDNS_ADDR_UV_FUSION_PAR2               (SDNS_BASE + 0x0090)
++#define    SDNS_ADDR_UV_FUSION_PAR3               (SDNS_BASE + 0x0094)
++
++//============================================================
++// HLDC
++//============================================================
++#define    HLDC_ADDR_REG_CTRL                     (HLDC_BASE + 0x0000)
++#define    HLDC_ADDR_DIS_Y_COEFF_X                (HLDC_BASE + 0x0004)
++#define    HLDC_ADDR_DIS_UV_COEFF_X               (HLDC_BASE + 0x0008)
++#define    HLDC_ADDR_P1_Y_VAL                     (HLDC_BASE + 0x000C)
++#define    HLDC_ADDR_P1_UV_VAL                    (HLDC_BASE + 0x0010)
++#define    HLDC_ADDR_R2_Y_REP                     (HLDC_BASE + 0x0014)
++#define    HLDC_ADDR_R2_UV_REP                    (HLDC_BASE + 0x0018)
++#define    HLDC_ADDR_Y_OFFSET                     (HLDC_BASE + 0x001C)
++#define    HLDC_ADDR_UV_OFFSET                    (HLDC_BASE + 0x0020)
++#define    HLDC_ADDR_LINE_BLK_Y                   (HLDC_BASE + 0x0024)
++#define    HLDC_ADDR_LINE_BLK_UV                  (HLDC_BASE + 0x0028)
++
++//============================================================
++// Mscaler
++//============================================================
++#define    MSCA_CTRL                         (MSCA_BASE+0x000)
++#define    MSCA_CH_EN                        (MSCA_BASE+0x004)
++#define    MSCA_CH_STA                       (MSCA_BASE+0x008)
++#define    MSCA_INT_STA                      (MSCA_BASE+0x00C)
++#define    MSCA_INT_MSK                      (MSCA_BASE+0x010)
++#define    MSCA_INT_CLR                      (MSCA_BASE+0x014)
++#define    MSCA_DMAOUT_ARB                   (MSCA_BASE+0x018)
++#define    MSCA_CLK_GATE_EN                  (MSCA_BASE+0x01C)
++#define    MSCA_CLK_DIS                      (MSCA_BASE+0x020)
++#define    MSCA_SRC_IN                       (MSCA_BASE+0x030)
++#define    MSCA_SRC_SIZE                     (MSCA_BASE+0x034)
++#define    MSCA_GLO_RSZ_COEF_WR              (MSCA_BASE+0x040)
++#define    MSCA_SYS_PRO_CLK_EN               (MSCA_BASE+0x050)
++#define    MSCA_DS0_CLK_NUM                  (MSCA_BASE+0x054)
++#define    MSCA_DS1_CLK_NUM                  (MSCA_BASE+0x058)
++#define    MSCA_DS2_CLK_NUM                  (MSCA_BASE+0x05C)
++
++//ds0
++#define    MSCA_ADDR_DS0_RSZ_SIZE                 (MSCA_BASE+0x100)
++#define    MSCA_ADDR_DS0_RSZ_STEP                 (MSCA_BASE+0x104)
++#define    MSCA_ADDR_DS0_CROP_POS                 (MSCA_BASE+0x128)
++#define    MSCA_ADDR_DS0_CROP_SIZE                (MSCA_BASE+0x12C)
++#define    MSCA_ADDR_DS0_FRA_RATE_LOOP            (MSCA_BASE+0x130)
++#define    MSCA_ADDR_DS0_FRA_RATE_MASK            (MSCA_BASE+0x134)
++#define    MSCA_ADDR_DS0_MASK0_POS                (MSCA_BASE+0x138)
++#define    MSCA_ADDR_DS0_MASK0_SIZE               (MSCA_BASE+0x13C)
++#define    MSCA_ADDR_DS0_MASK0_ARGB               (MSCA_BASE+0x140)
++#define    MSCA_ADDR_DS0_MASK1_POS                (MSCA_BASE+0x144)
++#define    MSCA_ADDR_DS0_MASK1_SIZE               (MSCA_BASE+0x148)
++#define    MSCA_ADDR_DS0_MASK1_ARGB               (MSCA_BASE+0x14C)
++#define    MSCA_ADDR_DS0_MASK2_POS                (MSCA_BASE+0x150)
++#define    MSCA_ADDR_DS0_MASK2_SIZE               (MSCA_BASE+0x154)
++#define    MSCA_ADDR_DS0_MASK2_ARGB               (MSCA_BASE+0x158)
++#define    MSCA_ADDR_DS0_MASK3_POS                (MSCA_BASE+0x15C)
++#define    MSCA_ADDR_DS0_MASK3_SIZE               (MSCA_BASE+0x160)
++#define    MSCA_ADDR_DS0_MASK3_ARGB               (MSCA_BASE+0x164)
++#define    MSCA_ADDR_DS0_DMAOUT_FMT               (MSCA_BASE+0x168)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_ADDR            (MSCA_BASE+0x16C)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_FIFO_STA        (MSCA_BASE+0x170)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_LAST_ADDR       (MSCA_BASE+0x174)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_LAST_STATS_NUM  (MSCA_BASE+0x178)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_LAST_FIFO_STA   (MSCA_BASE+0x17C)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_STR             (MSCA_BASE+0x180)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_ADDR           (MSCA_BASE+0x184)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_FIFO_STA       (MSCA_BASE+0x188)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_LAST_ADDR      (MSCA_BASE+0x18C)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_LAST_STATS_NUM (MSCA_BASE+0x190)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_LAST_FIFO_STA  (MSCA_BASE+0x194)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_STR            (MSCA_BASE+0x198)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_FIFO_CLR        (MSCA_BASE+0x19C)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_FIFO_CLR       (MSCA_BASE+0x1A0)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_LAST_FIFO_CLR   (MSCA_BASE+0x1A4)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_LAST_FIFO_CLR  (MSCA_BASE+0x1A8)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_ADDR_SEL        (MSCA_BASE+0x1AC)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_ADDR_SEL       (MSCA_BASE+0x1B0)
++
++//-- ds1
++#define    MSCA_ADDR_DS1_RSZ_SIZE                 (MSCA_BASE+0x200)
++#define    MSCA_ADDR_DS1_RSZ_STEP                 (MSCA_BASE+0x204)
++#define    MSCA_ADDR_DS1_CROP_POS                 (MSCA_BASE+0x228)
++#define    MSCA_ADDR_DS1_CROP_SIZE                (MSCA_BASE+0x22C)
++#define    MSCA_ADDR_DS1_FRA_RATE_LOOP            (MSCA_BASE+0x230)
++#define    MSCA_ADDR_DS1_FRA_RATE_MASK            (MSCA_BASE+0x234)
++#define    MSCA_ADDR_DS1_MASK0_POS                (MSCA_BASE+0x238)
++#define    MSCA_ADDR_DS1_MASK0_SIZE               (MSCA_BASE+0x23C)
++#define    MSCA_ADDR_DS1_MASK0_ARGB               (MSCA_BASE+0x240)
++#define    MSCA_ADDR_DS1_MASK1_POS                (MSCA_BASE+0x244)
++#define    MSCA_ADDR_DS1_MASK1_SIZE               (MSCA_BASE+0x248)
++#define    MSCA_ADDR_DS1_MASK1_ARGB               (MSCA_BASE+0x24C)
++#define    MSCA_ADDR_DS1_MASK2_POS                (MSCA_BASE+0x250)
++#define    MSCA_ADDR_DS1_MASK2_SIZE               (MSCA_BASE+0x254)
++#define    MSCA_ADDR_DS1_MASK2_ARGB               (MSCA_BASE+0x258)
++#define    MSCA_ADDR_DS1_MASK3_POS                (MSCA_BASE+0x25C)
++#define    MSCA_ADDR_DS1_MASK3_SIZE               (MSCA_BASE+0x260)
++#define    MSCA_ADDR_DS1_MASK3_ARGB               (MSCA_BASE+0x264)
++#define    MSCA_ADDR_DS1_DMAOUT_FMT               (MSCA_BASE+0x268)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_ADDR            (MSCA_BASE+0x26C)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_FIFO_STA        (MSCA_BASE+0x270)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_LAST_ADDR       (MSCA_BASE+0x274)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_LAST_STATS_NUM  (MSCA_BASE+0x278)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_LAST_FIFO_STA   (MSCA_BASE+0x27C)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_STR             (MSCA_BASE+0x280)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_ADDR           (MSCA_BASE+0x284)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_FIFO_STA       (MSCA_BASE+0x288)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_LAST_ADDR      (MSCA_BASE+0x28C)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_LAST_STATS_NUM (MSCA_BASE+0x290)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_LAST_FIFO_STA  (MSCA_BASE+0x294)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_STR            (MSCA_BASE+0x298)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_FIFO_CLR        (MSCA_BASE+0x29C)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_FIFO_CLR       (MSCA_BASE+0x2A0)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_LAST_FIFO_CLR   (MSCA_BASE+0x2A4)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_LAST_FIFO_CLR  (MSCA_BASE+0x2A8)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_ADDR_SEL        (MSCA_BASE+0x2AC)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_ADDR_SEL       (MSCA_BASE+0x2B0)
++
++
++//-- ds2
++#define    MSCA_ADDR_DS2_RSZ_SIZE                 (MSCA_BASE+0x300)
++#define    MSCA_ADDR_DS2_RSZ_STEP                 (MSCA_BASE+0x304)
++#define    MSCA_ADDR_DS2_CROP_POS                 (MSCA_BASE+0x328)
++#define    MSCA_ADDR_DS2_CROP_SIZE                (MSCA_BASE+0x32C)
++#define    MSCA_ADDR_DS2_FRA_RATE_LOOP            (MSCA_BASE+0x330)
++#define    MSCA_ADDR_DS2_FRA_RATE_MASK            (MSCA_BASE+0x334)
++#define    MSCA_ADDR_DS2_MASK0_POS                (MSCA_BASE+0x338)
++#define    MSCA_ADDR_DS2_MASK0_SIZE               (MSCA_BASE+0x33C)
++#define    MSCA_ADDR_DS2_MASK0_ARGB               (MSCA_BASE+0x340)
++#define    MSCA_ADDR_DS2_MASK1_POS                (MSCA_BASE+0x344)
++#define    MSCA_ADDR_DS2_MASK1_SIZE               (MSCA_BASE+0x348)
++#define    MSCA_ADDR_DS2_MASK1_ARGB               (MSCA_BASE+0x34C)
++#define    MSCA_ADDR_DS2_MASK2_POS                (MSCA_BASE+0x350)
++#define    MSCA_ADDR_DS2_MASK2_SIZE               (MSCA_BASE+0x354)
++#define    MSCA_ADDR_DS2_MASK2_ARGB               (MSCA_BASE+0x358)
++#define    MSCA_ADDR_DS2_MASK3_POS                (MSCA_BASE+0x35C)
++#define    MSCA_ADDR_DS2_MASK3_SIZE               (MSCA_BASE+0x360)
++#define    MSCA_ADDR_DS2_MASK3_ARGB               (MSCA_BASE+0x364)
++#define    MSCA_ADDR_DS2_DMAOUT_FMT               (MSCA_BASE+0x368)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_ADDR            (MSCA_BASE+0x36C)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_FIFO_STA        (MSCA_BASE+0x370)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_LAST_ADDR       (MSCA_BASE+0x374)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_LAST_STATS_NUM  (MSCA_BASE+0x378)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_LAST_FIFO_STA   (MSCA_BASE+0x37C)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_STR             (MSCA_BASE+0x380)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_ADDR           (MSCA_BASE+0x384)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_FIFO_STA       (MSCA_BASE+0x388)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_LAST_ADDR      (MSCA_BASE+0x38C)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_LAST_STATS_NUM (MSCA_BASE+0x390)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_LAST_FIFO_STA  (MSCA_BASE+0x394)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_STR            (MSCA_BASE+0x398)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_FIFO_CLR        (MSCA_BASE+0x39C)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_FIFO_CLR       (MSCA_BASE+0x3A0)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_LAST_FIFO_CLR   (MSCA_BASE+0x3A4)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_LAST_FIFO_CLR  (MSCA_BASE+0x3A8)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_ADDR_SEL        (MSCA_BASE+0x3AC)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_ADDR_SEL       (MSCA_BASE+0x3B0)
++
++//--DEBUG
++#define    MSCA_ADDR_VRSZ_Y_DBG_SEL               (MSCA_BASE+0x080)
++#define    MSCA_ADDR_VRSZ_UV_DBG_SEL              (MSCA_BASE+0x084)
++#define    MSCA_ADDR_DS0_DMA_OUT_DBG0_SEL         (MSCA_BASE+0x088)
++#define    MSCA_ADDR_DS0_DMA_OUT_DBG1_SEL         (MSCA_BASE+0x08C)
++#define    MSCA_ADDR_DS0_DMA_OUT_DBG2_SEL         (MSCA_BASE+0x090)
++#define    MSCA_ADDR_DS1_DMA_OUT_DBG0_SEL         (MSCA_BASE+0x094)
++#define    MSCA_ADDR_DS1_DMA_OUT_DBG1_SEL         (MSCA_BASE+0x098)
++#define    MSCA_ADDR_DS1_DMA_OUT_DBG2_SEL         (MSCA_BASE+0x09C)
++#define    MSCA_ADDR_DS2_DMA_OUT_DBG0_SEL         (MSCA_BASE+0x0A0)
++#define    MSCA_ADDR_DS2_DMA_OUT_DBG1_SEL         (MSCA_BASE+0x0A4)
++#define    MSCA_ADDR_DS2_DMA_OUT_DBG2_SEL         (MSCA_BASE+0x0A8)
++#define    MSCA_ADDR_DS0_HRSZ_Y_DBG_SEL           (MSCA_BASE+0x0AC)
++#define    MSCA_ADDR_DS0_HRSZ_UV_DBG_SEL          (MSCA_BASE+0x0B0)
++#define    MSCA_ADDR_DS1_HRSZ_Y_DBG_SEL           (MSCA_BASE+0x0B4)
++#define    MSCA_ADDR_DS1_HRSZ_UV_DBG_SEL          (MSCA_BASE+0x0B8)
++#define    MSCA_ADDR_DS2_HRSZ_Y_DBG_SEL           (MSCA_BASE+0x0BC)
++#define    MSCA_ADDR_DS2_HRSZ_UV_DBG_SEL          (MSCA_BASE+0x0C0)
++#define    MSCA_ADDR_BP_BUS0_DBG_SEL              (MSCA_BASE+0x0C4)
++#define    MSCA_ADDR_BP_BUS1_DBG_SEL              (MSCA_BASE+0x0C8)
++#define    MSCA_ADDR_BP_BUS2_DBG_SEL              (MSCA_BASE+0x0CC)
++#define    MSCA_ADDR_STP_DBG_SEL                  (MSCA_BASE+0x0D0)
++
++#define    MSCA_ADDR_DS0_CRC_Y_SEL                (MSCA_BASE+0x0E0)
++#define    MSCA_ADDR_DS0_CRC_UV_SEL               (MSCA_BASE+0x0E4)
++#define    MSCA_ADDR_DS1_CRC_Y_SEL                (MSCA_BASE+0x0E8)
++#define    MSCA_ADDR_DS1_CRC_UV_SEL               (MSCA_BASE+0x0EC)
++#define    MSCA_ADDR_DS2_CRC_Y_SEL                (MSCA_BASE+0x0F0)
++#define    MSCA_ADDR_DS2_CRC_UV_SEL               (MSCA_BASE+0x0F4)
++
++#define CHx_RSZ_OSIZE(n)				(MSCA_BASE+(0x0100*(n))+0x100)
++#define CHx_RSZ_STEP(n)					(MSCA_BASE+(0x0100*(n))+0x104)
++
++#define CHx_CROP_OPOS(n)				(MSCA_BASE+(0x0100*(n))+0x128)
++#define CHx_CROP_OSIZE(n)				(MSCA_BASE+(0x0100*(n))+0x12c)
++#define CHx_FRA_CTRL_LOOP(n)				(MSCA_BASE+(0x0100*(n))+0x130)
++#define CHx_FRA_CTRL_MASK(n)				(MSCA_BASE+(0x0100*(n))+0x134)
++#define CHx_MS0_POS(n)					(MSCA_BASE+(0x0100*(n))+0x138)
++#define CHx_MS0_SIZE(n)					(MSCA_BASE+(0x0100*(n))+0x13c)
++#define CHx_MS0_VALUE(n)				(MSCA_BASE+(0x0100*(n))+0x140)
++#define CHx_MS1_POS(n)					(MSCA_BASE+(0x0100*(n))+0x144)
++#define CHx_MS1_SIZE(n)					(MSCA_BASE+(0x0100*(n))+0x148)
++#define CHx_MS1_VALUE(n)				(MSCA_BASE+(0x0100*(n))+0x14c)
++#define CHx_MS2_POS(n)					(MSCA_BASE+(0x0100*(n))+0x150)
++#define CHx_MS2_SIZE(n)					(MSCA_BASE+(0x0100*(n))+0x154)
++#define CHx_MS2_VALUE(n)				(MSCA_BASE+(0x0100*(n))+0x158)
++#define CHx_MS3_POS(n)					(MSCA_BASE+(0x0100*(n))+0x15c)
++#define CHx_MS3_SIZE(n)					(MSCA_BASE+(0x0100*(n))+0x160)
++#define CHx_MS3_VALUE(n)				(MSCA_BASE+(0x0100*(n))+0x164)
++#define CHx_OUT_FMT(n)					(MSCA_BASE+(0x0100*(n))+0x168)
++#define CHx_DMAOUT_Y_ADDR(n)				(MSCA_BASE+(0x0100*(n))+0x16c)
++#define CHx_Y_ADDR_FIFO_STA(n)				(MSCA_BASE+(0x0100*(n))+0x170)
++#define CHx_DMAOUT_Y_LAST_ADDR(n)			(MSCA_BASE+(0x0100*(n))+0x174)
++#define CHx_DMAOUT_Y_LAST_STATS_NUM(n)			(MSCA_BASE+(0x0100*(n))+0x178)
++#define CHx_Y_LAST_ADDR_FIFO_STA(n)			(MSCA_BASE+(0x0100*(n))+0x17c)
++#define CHx_DMAOUT_Y_STRI(n)				(MSCA_BASE+(0x0100*(n))+0x180)
++#define CHx_DMAOUT_UV_ADDR(n)				(MSCA_BASE+(0x0100*(n))+0x184)
++#define CHx_UV_ADDR_FIFO_STA(n)				(MSCA_BASE+(0x0100*(n))+0x188)
++#define CHx_DMAOUT_UV_LAST_ADDR(n)			(MSCA_BASE+(0x0100*(n))+0x18c)
++#define CHx_DMAOUT_UV_LAST_STATS_NUM(n)			(MSCA_BASE+(0x0100*(n))+0x190)
++#define CHx_UV_LAST_ADDR_FIFO_STA(n)			(MSCA_BASE+(0x0100*(n))+0x194)
++#define CHx_DMAOUT_UV_STRI(n)				(MSCA_BASE+(0x0100*(n))+0x198)
++#define CHx_DMAOUT_Y_ADDR_CLR(n)			(MSCA_BASE+(0x0100*(n))+0x19c)
++#define CHx_DMAOUT_UV_ADDR_CLR(n)			(MSCA_BASE+(0x0100*(n))+0x1a0)
++#define CHx_DMAOUT_Y_LAST_ADDR_CLR(n)			(MSCA_BASE+(0x0100*(n))+0x1a4)
++#define CHx_DMAOUT_UV_LAST_ADDR_CLR(n)			(MSCA_BASE+(0x0100*(n))+0x1a8)
++#define CHx_DMAOUT_Y_ADDR_SEL(n)			(MSCA_BASE+(0x0100*(n))+0x1ac)
++#define CHx_DMAOUT_UV_ADDR_SEL(n)			(MSCA_BASE+(0x0100*(n))+0x1b0)
++
++#define TIZIANO_ISP_IRQ_ISP_FRD                        (0)
++#define TIZIANO_ISP_IRQ_STOP                           (4)
++#define TIZIANO_ISP_IRQ_CTM_STATIC                     (8)
++#define TIZIANO_ISP_IRQ_AE_STATIC                      (16)
++#define TIZIANO_ISP_IRQ_AE_HIST                        (17)
++#define TIZIANO_ISP_IRQ_AWB_STATIC                     (18)
++#define TIZIANO_ISP_IRQ_AF_STATIC                      (19)
++#define TIZIANO_ISP_IRQ_ADR_STATIC                     (20)
++#define TIZIANO_ISP_IRQ_DEFOG_STATIC                   (21)
++#define TIZIANO_ISP_IRQ_DMAOUT_FRD                     (23)
++#endif
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-regs.h b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-regs.h
+new file mode 100755
+index 000000000..cd3d04bd7
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-regs.h
+@@ -0,0 +1,4289 @@
++#ifndef TIZIANO_MAP_H
++#define TIZIANO_MAP_H
++
++#ifndef TIZIANO_BASE
++#define TIZIANO_BASE 0x0
++#endif
++
++//============================================================
++// BASE ADDRESS
++//============================================================
++#define    TOP_BASE                  (TIZIANO_BASE + 0x00000)
++#define    IPC_BASE                  (TIZIANO_BASE + 0x01000)
++#define    FBIST_BASE                (TIZIANO_BASE + 0x70000)
++#define    RESP_BASE                 (TIZIANO_BASE + 0x40000)
++#define    MCFG_BASE                 (TIZIANO_BASE + 0x50000)
++
++#define    BLC0_BASE                 (TIZIANO_BASE + 0x02000)
++#define    LSC0_BASE                 (TIZIANO_BASE + 0x03000)
++#define    AWBG00_BASE               (TIZIANO_BASE + 0x04000)
++#define    AWBG10_BASE               (TIZIANO_BASE + 0x05000)
++#define    WDR0_BASE                 (TIZIANO_BASE + 0x06000)
++#define    WDR_BASE(n)                 (TIZIANO_BASE + 0x06000 + n * 0x0800)
++#define    DPC_BASE(n)                 (TIZIANO_BASE + 0x07000 + n * 0x0100)
++#define    GIB_BASE(n)                 (TIZIANO_BASE + 0x08000 + n * 0x0080)
++#define    ADR0_BASE                 (TIZIANO_BASE + 0x09000)
++#define    ADR_BASE(n)               (TIZIANO_BASE + 0x09000 + n * 0x0800)
++#define    DEMOSAIC_BASE(n)            (TIZIANO_BASE + 0x0A000 + n * 0x0400)
++#define    CCM0_BASE                 (TIZIANO_BASE + 0x0B000)
++#define    DEFOG_BASE(n)               (TIZIANO_BASE + 0x0C000 + n * 0x0400)
++#define    CSC_BASE(n)                 (TIZIANO_BASE + 0x0D000 + n * 0x0080)
++#define    LCE0_BASE                 (TIZIANO_BASE + 0x0E000)
++#define    MDNS_BASE(n)             (TIZIANO_BASE + 0x0F000 + 0x0800 * n)
++#define    YDNS_BASE(n)                (TIZIANO_BASE + 0x10000 + n * 0x100)
++#define    BCSH0_BASE                (TIZIANO_BASE + 0x11000)
++#define    CLM0_BASE                 (TIZIANO_BASE + 0x12000)
++#define    Y_SHARPEN_BASE(n)           (TIZIANO_BASE + 0x13000 + n * 0x0200)
++#define    SDNS_BASE(n)                (TIZIANO_BASE + 0x14000 + n * 0x0400)
++#define    HLDC_BASE(n)              (TIZIANO_BASE + 0x15000 + n * 0x0080)
++#define    MSCALER0_BASE             (TIZIANO_BASE + 0x16000)
++#define    AWB0_BASE                 (TIZIANO_BASE + 0x18000)
++#define    AE0_BASE                  (TIZIANO_BASE + 0x19000)
++#define    AF_BASE                   (TIZIANO_BASE + 0x1A000)
++#define    GSM0_BASE                 (TIZIANO_BASE + 0x1B000)
++#define    CDNS_BASE(n)                (TIZIANO_BASE + 0x1C000 + n * 0x80)
++#define    TSTP_BASE(n)                (TIZIANO_BASE + 0x60000 + n * 0x0100)
++
++#define    BLC1_BASE                 (TIZIANO_BASE + 0x02000 + 0x0080)
++#define    LSC1_BASE                 (TIZIANO_BASE + 0x03000 + 0x0080)
++#define    AWBG01_BASE               (TIZIANO_BASE + 0x04000 + 0x0020)
++#define    AWBG11_BASE               (TIZIANO_BASE + 0x05000 + 0x0020)
++#define    WDR1_BASE                 (TIZIANO_BASE + 0x06000 + 0x0800)
++#define    ADR1_BASE                 (TIZIANO_BASE + 0x09000 + 0x0800)
++#define    CCM1_BASE                 (TIZIANO_BASE + 0x0B000 + 0x0040)
++#define    LCE1_BASE                 (TIZIANO_BASE + 0x0E000 + 0x0100)
++#define    BCSH1_BASE                (TIZIANO_BASE + 0x11000 + 0x0100)
++#define    CLM1_BASE                 (TIZIANO_BASE + 0x12000 + 0x0080)
++#define    MSCALER1_BASE             (TIZIANO_BASE + 0x16000 + 0x1000)
++#define    AWB1_BASE                 (TIZIANO_BASE + 0x18000 + 0x0200)
++#define    AE1_BASE                  (TIZIANO_BASE + 0x19000 + 0x0200)
++#define    GSM1_BASE                 (TIZIANO_BASE + 0x1B000 + 0x0040)
++
++//============================================================
++// TOP ADDRESS
++//============================================================
++#define    TOP_ADDR_VERSION                                  (TOP_BASE + 0x0000)
++#define    TOP_ADDR_TOP_CON                                  (TOP_BASE + 0x0020)
++
++#define    FUN_RST						(1 << 2)
++#define    REG_RST						(1 << 1)
++#define    ALL_RST						(1 << 0)
++#define    TOP_ADDR_TOP_RST                                  (TOP_BASE + 0x0024)
++#define    TOP_ADDR_TOP_INFO                                 (TOP_BASE + 0x0028)
++
++#define    BLC_BYPASS                                        (1 << 0)
++#define    LSC_BYPASS                                        (1 << 1)
++#define    AWB0_BYPASS                                       (1 << 2)
++#define    WDR_BYPASS                                        (1 << 3)
++#define    DPC_BYPASS                                        (1 << 4)
++#define    GIB_BYPASS                                        (1 << 5)
++#define    AWB1_BYPASS                                       (1 << 6)
++#define    ADR_BYPASS                                        (1 << 7)
++#define    DMSC_BYPASS                                       (1 << 8)
++#define    CCM_BYPASS                                        (1 << 9)
++#define    GAMMA_BYPASS                                      (1 << 10)
++#define    DEFOG_BYPASS                                      (1 << 11)
++#define    CSC_BYPASS                                        (1 << 12)
++#define    MDNS_BYPASS                                       (1 << 13)
++#define    YDNS_BYPASS                                       (1 << 14)
++#define    BCSH_BYPASS                                       (1 << 15)
++#define    CLM_BYPASS                                        (1 << 16)
++#define    YSP_BYPASS                                        (1 << 17)
++#define    SDNS_BYPASS                                       (1 << 18)
++#define    CDNS_BYPASS                                       (1 << 19)
++#define    HLDC_BYPASS                                       (1 << 20)
++#define    LCE_BYPASS                                        (1 << 21)
++#define    TPRAW_PAT_BYPASS                                  (1 << 22)
++#define    TPRGB_PAT_BYPASS                                  (1 << 23)
++#define    TPYUV_PAT_BYPASS                                  (1 << 24)
++#define    TPRAW_FONT_BYPASS                                 (1 << 25)
++#define    TPRGB_FONT_BYPASS                                 (1 << 26)
++#define    TPYUV_FONT_BYPASS                                 (1 << 27)
++#define    TPRAW_FREE_BYPASS                                 (1 << 28)
++#define    TPRGB_FREE_BYPASS                                 (1 << 29)
++#define    TPYUV_FREE_BYPASS                                 (1 << 30)
++
++#define    TIZIANO_BYPASS_INIT    (BLC_BYPASS|LSC_BYPASS|AWB0_BYPASS|WDR_BYPASS|DPC_BYPASS|GIB_BYPASS|AWB1_BYPASS|ADR_BYPASS|DMSC_BYPASS|CCM_BYPASS|GAMMA_BYPASS|DEFOG_BYPASS|CSC_BYPASS|MDNS_BYPASS|YDNS_BYPASS|BCSH_BYPASS|CLM_BYPASS|YSP_BYPASS|SDNS_BYPASS|CDNS_BYPASS|HLDC_BYPASS|LCE_BYPASS|TPRAW_PAT_BYPASS |TPRGB_PAT_BYPASS|TPYUV_PAT_BYPASS|TPRAW_FONT_BYPASS|TPRGB_FONT_BYPASS|TPYUV_FONT_BYPASS|TPRAW_FREE_BYPASS|TPRGB_FREE_BYPASS|TPYUV_FREE_BYPASS)
++
++#define    TOP_ADDR_BYPASS(num)                              (TOP_BASE + 0x0040 + num * 4)
++#define    TOP_ADDR_REG_CON                                  (TOP_BASE + 0x0048)
++#define    TOP_ADDR_STATIC_EN1                               (TOP_BASE + 0x0050)
++#define    TOP_ADDR_STATIC_POS1                              (TOP_BASE + 0x005C)
++
++
++#define    AE_STATIC_EN                                      ( 1 << 0)
++#define    AE_HIST_EN                                        ( 1 << 1)
++#define    AE_IR_HIST_EN                                     ( 1 << 2)
++#define    AWB_STATIC_EN                                     ( 1 << 3)
++#define    AF_STATIC_EN                                      ( 1 << 4)
++#define    GSM_STATIC_EN                                     ( 1 << 5)
++#define    WDR_STATIC_EN                                     ( 1 << 6)
++#define    ADR_STATIC_EN                                     ( 1 << 7)
++#define    DEFOG_STATIC_EN                                   ( 1 << 8)
++#define    LCE_STATIC_EN                                     ( 1 << 9)
++#define    TOP_ADDR_STATIC_EN                                (TOP_BASE + 0x0060)
++#define    TOP_ADDR_STATIC_STOP                              (TOP_BASE + 0x0064)
++#define    TOP_ADDR_STATIC_RST                               (TOP_BASE + 0x0068)
++#define    TOP_ADDR_STATIC_POS                               (TOP_BASE + 0x006C)
++#define    TOP_ADDR_S0_FRM_SIZE                              (TOP_BASE + 0x0080)
++#define    TOP_ADDR_S1_FRM_SIZE                              (TOP_BASE + 0x0084)
++#define    TOP_ADDR_S0_BAYER_TYPE                            (TOP_BASE + 0x0088)
++#define    TOP_ADDR_S1_BAYER_TYPE                            (TOP_BASE + 0x008C)
++#define    TOP_ADDR_S0_LINE_SPACE_0                          (TOP_BASE + 0x0090)
++#define    TOP_ADDR_S0_LINE_SPACE_1                          (TOP_BASE + 0x0094)
++#define    TOP_ADDR_S1_LINE_SPACE_0                          (TOP_BASE + 0x0098)
++#define    TOP_ADDR_S1_LINE_SPACE_1                          (TOP_BASE + 0x009C)
++#define    TOP_ADDR_STOP_CON                                 (TOP_BASE + 0x0200)
++#define    TOP_ADDR_STOP_STATE                               (TOP_BASE + 0x0204)
++#define    TOP_ADDR_DMA_RD_CON                               (TOP_BASE + 0x0220)
++#define    TOP_ADDR_DMA_RD_INFO                              (TOP_BASE + 0x0224)
++#define    TOP_ADDR_DMA_WR_CON_0                             (TOP_BASE + 0x0240)
++#define    TOP_ADDR_DMA_WR_CON_1                             (TOP_BASE + 0x0244)
++#define    TOP_ADDR_DMA_WR_CON_2                             (TOP_BASE + 0x0248)
++#define    TOP_ADDR_DMA_WR_CON_3                             (TOP_BASE + 0x024C)
++#define    TOP_ADDR_DMA_WR_CON_4                             (TOP_BASE + 0x0250)
++#define    TOP_ADDR_DMA_WR_CON_5                             (TOP_BASE + 0x0254)
++#define    TOP_ADDR_DMA_WR_INFO_0                            (TOP_BASE + 0x0280)
++#define    TOP_ADDR_DMA_WR_INFO_1                            (TOP_BASE + 0x0284)
++#define    TOP_ADDR_DMA_WR_INFO_2                            (TOP_BASE + 0x0288)
++#define    TOP_ADDR_DMA_WR_INFO_3                            (TOP_BASE + 0x028C)
++#define    TOP_ADDR_DMA_WR_INFO_4                            (TOP_BASE + 0x0290)
++#define    TOP_ADDR_DMA_WR_INFO_5                            (TOP_BASE + 0x0294)
++#define    TOP_ADDR_DMA_WR_INFO_6                            (TOP_BASE + 0x0298)
++#define    TOP_ADDR_DMA_WR_INFO_7                            (TOP_BASE + 0x029C)
++#define    TOP_ADDR_DMA_WR_INFO_8                            (TOP_BASE + 0x02A0)
++#define    TOP_ADDR_DMA_WR_INFO_9                            (TOP_BASE + 0x02A4)
++
++//============================================================
++// BLC ADDRESS
++//============================================================
++#define    MAIN_BLC_ADDR_SHD_CTRL                            (BLC0_BASE + 0x0000)
++#define    MAIN_BLC_ADDR_BL_L_0                              (BLC0_BASE + 0x0004)
++#define    MAIN_BLC_ADDR_BL_L_1                              (BLC0_BASE + 0x0008)
++#define    MAIN_BLC_ADDR_BL_L_2                              (BLC0_BASE + 0x000c)
++#define    MAIN_BLC_ADDR_BL_MIN_L                            (BLC0_BASE + 0x0010)
++#define    MAIN_BLC_ADDR_BL_S_0                              (BLC0_BASE + 0x0014)
++#define    MAIN_BLC_ADDR_BL_S_1                              (BLC0_BASE + 0x0018)
++#define    MAIN_BLC_ADDR_BL_S_2                              (BLC0_BASE + 0x001c)
++#define    MAIN_BLC_ADDR_BL_MIN_S                            (BLC0_BASE + 0x0020)
++#define    MAIN_BLC_ADDR_R_G_GAIN_L                          (BLC0_BASE + 0x0024)
++#define    MAIN_BLC_ADDR_B_IR_GAIN_L                         (BLC0_BASE + 0x0028)
++#define    MAIN_BLC_ADDR_GAIN_SFT_OPT_L                      (BLC0_BASE + 0x002c)
++#define    MAIN_BLC_ADDR_R_G_GAIN_S                          (BLC0_BASE + 0x0030)
++#define    MAIN_BLC_ADDR_B_IR_GAIN_S                         (BLC0_BASE + 0x0034)
++#define    MAIN_BLC_ADDR_GAIN_SFT_OPT_S                      (BLC0_BASE + 0x0038)
++#define    MAIN_BLC_ADDR_DEBUG0                              (BLC0_BASE + 0x003c)
++#define    MAIN_BLC_ADDR_DEBUG1                              (BLC0_BASE + 0x0040)
++#define    MAIN_BLC_ADDR_DEBUG2                              (BLC0_BASE + 0x0044)
++
++#define    SEC_BLC_ADDR_SHD_CTRL                             (BLC1_BASE + 0x0000)
++#define    SEC_BLC_ADDR_BL_L_0                               (BLC1_BASE + 0x0004)
++#define    SEC_BLC_ADDR_BL_L_1                               (BLC1_BASE + 0x0008)
++#define    SEC_BLC_ADDR_BL_L_2                               (BLC1_BASE + 0x000c)
++#define    SEC_BLC_ADDR_BL_MIN_L                             (BLC1_BASE + 0x0010)
++#define    SEC_BLC_ADDR_BL_S_0                               (BLC1_BASE + 0x0014)
++#define    SEC_BLC_ADDR_BL_S_1                               (BLC1_BASE + 0x0018)
++#define    SEC_BLC_ADDR_BL_S_2                               (BLC1_BASE + 0x001c)
++#define    SEC_BLC_ADDR_BL_MIN_S                             (BLC1_BASE + 0x0020)
++#define    SEC_BLC_ADDR_R_G_GAIN_L                           (BLC1_BASE + 0x0024)
++#define    SEC_BLC_ADDR_B_IR_GAIN_L                          (BLC1_BASE + 0x0028)
++#define    SEC_BLC_ADDR_GAIN_SFT_OPT_L                       (BLC1_BASE + 0x002c)
++#define    SEC_BLC_ADDR_R_G_GAIN_S                           (BLC1_BASE + 0x0030)
++#define    SEC_BLC_ADDR_B_IR_GAIN_S                          (BLC1_BASE + 0x0034)
++#define    SEC_BLC_ADDR_GAIN_SFT_OPT_S                       (BLC1_BASE + 0x0038)
++#define    SEC_BLC_ADDR_DEBUG0                               (BLC1_BASE + 0x003c)
++#define    SEC_BLC_ADDR_DEBUG1                               (BLC1_BASE + 0x0040)
++#define    SEC_BLC_ADDR_DEBUG2                               (BLC1_BASE + 0x0044)
++
++//===========================================================
++// LSC ADDRESS
++//============================================================
++#define    MAIN_LSC_ADDR_MESH_SIZE                            (LSC0_BASE + 0x0000)
++#define    MAIN_LSC_ADDR_SCALE_MEAN_OFST                      (LSC0_BASE + 0x0004)
++#define    MAIN_LSC_ADDR_DARK_ZONE_IMPRV_L                    (LSC0_BASE + 0x0008)
++#define    MAIN_LSC_ADDR_DARK_ZONE_IMPRV_S                    (LSC0_BASE + 0x000c)
++#define    MAIN_LSC_ADDR_FRAME_STREN                          (LSC0_BASE + 0x0010)
++#define    MAIN_LSC_ADDR_DEBUG_0                              (LSC0_BASE + 0x0014)
++#define    MAIN_LSC_ADDR_DEBUG_1                              (LSC0_BASE + 0x0018)
++#define    MAIN_LSC_ADDR_DEBUG_2                              (LSC0_BASE + 0x001c)
++#define    MAIN_LSC_ADDR_DEBUG_3                              (LSC0_BASE + 0x0020)
++#define    MAIN_LSC_ADDR_DEBUG_4                              (LSC0_BASE + 0x0024)
++#define    MAIN_LSC_ADDR_DEBUG_5                              (LSC0_BASE + 0x0028)
++#define    MAIN_LSC_ADDR_DEBUG_6                              (LSC0_BASE + 0x002c)
++#define    MAIN_LSC_ADDR_DEBUG_7                              (LSC0_BASE + 0x0030)
++#define    MAIN_LSC_ADDR_DEBUG_8                              (LSC0_BASE + 0x0034)
++#define    MAIN_LSC_ADDR_DEBUG_9                              (LSC0_BASE + 0x0038)
++#define    MAIN_LSC_ADDR_DEBUG_10                             (LSC0_BASE + 0x003c)
++#define    MAIN_LSC_ADDR_DEBUG_11                             (LSC0_BASE + 0x0040)
++#define    MAIN_LSC_ADDR_DEBUG_12                             (LSC0_BASE + 0x0044)
++#define    MAIN_LSC_ADDR_DEBUG_13                             (LSC0_BASE + 0x0048)
++#define    MAIN_LSC_ADDR_DEBUG_14                             (LSC0_BASE + 0x004c)
++#define    MAIN_LSC_ADDR_DEBUG_15                             (LSC0_BASE + 0x0050)
++#define    MAIN_LSC_ADDR_DEBUG_16                             (LSC0_BASE + 0x0054)
++#define    MAIN_LSC_ADDR_DEBUG_17                             (LSC0_BASE + 0x0058)
++#define    MAIN_LSC_ADDR_DEBUG_18                             (LSC0_BASE + 0x005c)
++#define    MAIN_LSC_ADDR_DEBUG_19                             (LSC0_BASE + 0x0060)
++#define    MAIN_LSC_ADDR_DEBUG_20                             (LSC0_BASE + 0x0064)
++#define    MAIN_LSC_ADDR_DEBUG_21                             (LSC0_BASE + 0x0068)
++#define    MAIN_LSC_ADDR_DEBUG_22                             (LSC0_BASE + 0x006c)
++
++#define    SEC_LSC_ADDR_MESH_SIZE                             (LSC1_BASE + 0x0000)
++#define    SEC_LSC_ADDR_SCALE_MEAN_OFST                       (LSC1_BASE + 0x0004)
++#define    SEC_LSC_ADDR_DARK_ZONE_IMPRV_L                     (LSC1_BASE + 0x0008)
++#define    SEC_LSC_ADDR_DARK_ZONE_IMPRV_S                     (LSC1_BASE + 0x000c)
++#define    SEC_LSC_ADDR_FRAME_STREN                           (LSC1_BASE + 0x0010)
++#define    SEC_LSC_ADDR_DEBUG_0                               (LSC1_BASE + 0x0014)
++#define    SEC_LSC_ADDR_DEBUG_1                               (LSC1_BASE + 0x0018)
++#define    SEC_LSC_ADDR_DEBUG_2                               (LSC1_BASE + 0x001c)
++#define    SEC_LSC_ADDR_DEBUG_3                               (LSC1_BASE + 0x0020)
++#define    SEC_LSC_ADDR_DEBUG_4                               (LSC1_BASE + 0x0024)
++#define    SEC_LSC_ADDR_DEBUG_5                               (LSC1_BASE + 0x0028)
++#define    SEC_LSC_ADDR_DEBUG_6                               (LSC1_BASE + 0x002c)
++#define    SEC_LSC_ADDR_DEBUG_7                               (LSC1_BASE + 0x0030)
++#define    SEC_LSC_ADDR_DEBUG_8                               (LSC1_BASE + 0x0034)
++#define    SEC_LSC_ADDR_DEBUG_9                               (LSC1_BASE + 0x0038)
++#define    SEC_LSC_ADDR_DEBUG_10                              (LSC1_BASE + 0x003c)
++#define    SEC_LSC_ADDR_DEBUG_11                              (LSC1_BASE + 0x0040)
++#define    SEC_LSC_ADDR_DEBUG_12                              (LSC1_BASE + 0x0044)
++#define    SEC_LSC_ADDR_DEBUG_13                              (LSC1_BASE + 0x0048)
++#define    SEC_LSC_ADDR_DEBUG_14                              (LSC1_BASE + 0x004c)
++#define    SEC_LSC_ADDR_DEBUG_15                              (LSC1_BASE + 0x0050)
++#define    SEC_LSC_ADDR_DEBUG_16                              (LSC1_BASE + 0x0054)
++#define    SEC_LSC_ADDR_DEBUG_17                              (LSC1_BASE + 0x0058)
++#define    SEC_LSC_ADDR_DEBUG_18                              (LSC1_BASE + 0x005c)
++#define    SEC_LSC_ADDR_DEBUG_19                              (LSC1_BASE + 0x0060)
++#define    SEC_LSC_ADDR_DEBUG_20                              (LSC1_BASE + 0x0064)
++#define    SEC_LSC_ADDR_DEBUG_21                              (LSC1_BASE + 0x0068)
++#define    SEC_LSC_ADDR_DEBUG_22                              (LSC1_BASE + 0x006c)
++
++//============================================================
++// AWBG0 ADDRESS
++//============================================================
++#define    MAIN_AWBG0_ADDR_SHD_CTRL                           (AWBG00_BASE + 0x0000)
++#define    MAIN_AWBG0_ADDR_R_G_GAIN_L                         (AWBG00_BASE + 0x0004)
++#define    MAIN_AWBG0_ADDR_B_IR_GAIN_L                        (AWBG00_BASE + 0x0008)
++#define    MAIN_AWBG0_ADDR_R_G_GAIN_S                         (AWBG00_BASE + 0x000c)
++#define    MAIN_AWBG0_ADDR_B_IR_GAIN_S                        (AWBG00_BASE + 0x0010)
++#define    MAIN_AWBG0_ADDR_DEBUG1                             (AWBG00_BASE + 0x0014)
++#define    MAIN_AWBG0_ADDR_DEBUG2                             (AWBG00_BASE + 0x0018)
++
++#define    SEC_AWBG0_ADDR_SHD_CTRL                            (AWBG01_BASE + 0x0000)
++#define    SEC_AWBG0_ADDR_R_G_GAIN_L                          (AWBG01_BASE + 0x0004)
++#define    SEC_AWBG0_ADDR_B_IR_GAIN_L                         (AWBG01_BASE + 0x0008)
++#define    SEC_AWBG0_ADDR_R_G_GAIN_S                          (AWBG01_BASE + 0x000c)
++#define    SEC_AWBG0_ADDR_B_IR_GAIN_S                         (AWBG01_BASE + 0x0010)
++#define    SEC_AWBG0_ADDR_DEBUG1                              (AWBG01_BASE + 0x0014)
++#define    SEC_AWBG0_ADDR_DEBUG2                              (AWBG01_BASE + 0x0018)
++
++//============================================================
++// WDR ADDRESS
++//============================================================
++#define    WDR_ADDR_T_VERSION(n)                                (WDR_BASE(n) + 0x0000)
++#define    WDR_ADDR_STA_ST_ADDR_000_00(n)                       (WDR_BASE(n) + 0x0010)
++#define    WDR_ADDR_STA_ST_ADDR_001_01(n)                       (WDR_BASE(n) + 0x0014)
++#define    WDR_ADDR_STA_ST_ADDR_002_02(n)                       (WDR_BASE(n) + 0x0018)
++#define    WDR_ADDR_STA_ST_ADDR_003_03(n)                       (WDR_BASE(n) + 0x001c)
++#define    WDR_ADDR_STA_BUF_NUM(n)                              (WDR_BASE(n) + 0x0030)
++#define    WDR_ADDR_STA_EXT_PRIO(n)                             (WDR_BASE(n) + 0x0034)
++#define    WDR_ADDR_DEBUG(n)                                    (WDR_BASE(n) + 0x0040)
++#define    WDR_ADDR_STA_THR(n)                                  (WDR_BASE(n) + 0x0048)
++#define    WDR_ADDR_DEGOSTPARA_0(n)                             (WDR_BASE(n) + 0x004c)
++#define    WDR_ADDR_DEGOSTPARA_1(n)                             (WDR_BASE(n) + 0x0050)
++#define    WDR_ADDR_DEGOSTPARA_2(n)                             (WDR_BASE(n) + 0x0054)
++#define    WDR_ADDR_DEGOSTPARA_3(n)                             (WDR_BASE(n) + 0x0058)
++#define    WDR_ADDR_DEGOSTPARA_4(n)                             (WDR_BASE(n) + 0x005c)
++#define    WDR_ADDR_MAPR_01_00(n)                               (WDR_BASE(n) + 0x0060)
++#define    WDR_ADDR_MAPR_03_02(n)                               (WDR_BASE(n) + 0x0064)
++#define    WDR_ADDR_MAPR_05_04(n)                               (WDR_BASE(n) + 0x0068)
++#define    WDR_ADDR_MAPR_07_06(n)                               (WDR_BASE(n) + 0x006c)
++#define    WDR_ADDR_MAPR_09_08(n)                               (WDR_BASE(n) + 0x0070)
++#define    WDR_ADDR_MAPR_11_10(n)                               (WDR_BASE(n) + 0x0074)
++#define    WDR_ADDR_MAPR_13_12(n)                               (WDR_BASE(n) + 0x0078)
++#define    WDR_ADDR_MAPR_15_14(n)                               (WDR_BASE(n) + 0x007c)
++#define    WDR_ADDR_MAPR_17_16(n)                               (WDR_BASE(n) + 0x0080)
++#define    WDR_ADDR_MAPR_19_18(n)                               (WDR_BASE(n) + 0x0084)
++#define    WDR_ADDR_MAPR_21_20(n)                               (WDR_BASE(n) + 0x0088)
++#define    WDR_ADDR_MAPR_23_22(n)                               (WDR_BASE(n) + 0x008c)
++#define    WDR_ADDR_MAPR_25_24(n)                               (WDR_BASE(n) + 0x0090)
++#define    WDR_ADDR_MAPR_27_26(n)                               (WDR_BASE(n) + 0x0094)
++#define    WDR_ADDR_MAPR_29_28(n)                               (WDR_BASE(n) + 0x0098)
++#define    WDR_ADDR_MAPR_31_30(n)                               (WDR_BASE(n) + 0x009c)
++#define    WDR_ADDR_MAPR_33_32(n)                               (WDR_BASE(n) + 0x00a0)
++#define    WDR_ADDR_MAPR_35_34(n)                               (WDR_BASE(n) + 0x00a4)
++#define    WDR_ADDR_MAPR_37_36(n)                               (WDR_BASE(n) + 0x00a8)
++#define    WDR_ADDR_MAPR_39_38(n)                               (WDR_BASE(n) + 0x00ac)
++#define    WDR_ADDR_MAPR_41_40(n)                               (WDR_BASE(n) + 0x00b0)
++#define    WDR_ADDR_MAPR_43_42(n)                               (WDR_BASE(n) + 0x00b4)
++#define    WDR_ADDR_MAPR_45_44(n)                               (WDR_BASE(n) + 0x00b8)
++#define    WDR_ADDR_MAPR_47_46(n)                               (WDR_BASE(n) + 0x00bc)
++#define    WDR_ADDR_MAPR_49_48(n)                               (WDR_BASE(n) + 0x00c0)
++#define    WDR_ADDR_MAPR_51_50(n)                               (WDR_BASE(n) + 0x00c4)
++#define    WDR_ADDR_MAPR_53_52(n)                               (WDR_BASE(n) + 0x00c8)
++#define    WDR_ADDR_MAPR_55_54(n)                               (WDR_BASE(n) + 0x00cc)
++#define    WDR_ADDR_MAPR_57_56(n)                               (WDR_BASE(n) + 0x00d0)
++#define    WDR_ADDR_MAPR_59_58(n)                               (WDR_BASE(n) + 0x00d4)
++#define    WDR_ADDR_MAPR_61_60(n)                               (WDR_BASE(n) + 0x00d8)
++#define    WDR_ADDR_MAPR_63_62(n)                               (WDR_BASE(n) + 0x00dc)
++#define    WDR_ADDR_MAPR_65_64(n)                               (WDR_BASE(n) + 0x00e0)
++#define    WDR_ADDR_MAPR_67_66(n)                               (WDR_BASE(n) + 0x00e4)
++#define    WDR_ADDR_MAPR_69_68(n)                               (WDR_BASE(n) + 0x00e8)
++#define    WDR_ADDR_MAPR_71_70(n)                               (WDR_BASE(n) + 0x00ec)
++#define    WDR_ADDR_MAPR_73_72(n)                               (WDR_BASE(n) + 0x00f0)
++#define    WDR_ADDR_MAPR_75_74(n)                               (WDR_BASE(n) + 0x00f4)
++#define    WDR_ADDR_MAPR_77_76(n)                               (WDR_BASE(n) + 0x00f8)
++#define    WDR_ADDR_MAPR_79_78(n)                               (WDR_BASE(n) + 0x00fc)
++#define    WDR_ADDR_MAPR_80_80(n)                               (WDR_BASE(n) + 0x0100)
++#define    WDR_ADDR_MAPG_01_00(n)                               (WDR_BASE(n) + 0x0104)
++#define    WDR_ADDR_MAPG_03_02(n)                               (WDR_BASE(n) + 0x0108)
++#define    WDR_ADDR_MAPG_05_04(n)                               (WDR_BASE(n) + 0x010c)
++#define    WDR_ADDR_MAPG_07_06(n)                               (WDR_BASE(n) + 0x0110)
++#define    WDR_ADDR_MAPG_09_08(n)                               (WDR_BASE(n) + 0x0114)
++#define    WDR_ADDR_MAPG_11_10(n)                               (WDR_BASE(n) + 0x0118)
++#define    WDR_ADDR_MAPG_13_12(n)                               (WDR_BASE(n) + 0x011c)
++#define    WDR_ADDR_MAPG_15_14(n)                               (WDR_BASE(n) + 0x0120)
++#define    WDR_ADDR_MAPG_17_16(n)                               (WDR_BASE(n) + 0x0124)
++#define    WDR_ADDR_MAPG_19_18(n)                               (WDR_BASE(n) + 0x0128)
++#define    WDR_ADDR_MAPG_21_20(n)                               (WDR_BASE(n) + 0x012c)
++#define    WDR_ADDR_MAPG_23_22(n)                               (WDR_BASE(n) + 0x0130)
++#define    WDR_ADDR_MAPG_25_24(n)                               (WDR_BASE(n) + 0x0134)
++#define    WDR_ADDR_MAPG_27_26(n)                               (WDR_BASE(n) + 0x0138)
++#define    WDR_ADDR_MAPG_29_28(n)                               (WDR_BASE(n) + 0x013c)
++#define    WDR_ADDR_MAPG_31_30(n)                               (WDR_BASE(n) + 0x0140)
++#define    WDR_ADDR_MAPG_33_32(n)                               (WDR_BASE(n) + 0x0144)
++#define    WDR_ADDR_MAPG_35_34(n)                               (WDR_BASE(n) + 0x0148)
++#define    WDR_ADDR_MAPG_37_36(n)                               (WDR_BASE(n) + 0x014c)
++#define    WDR_ADDR_MAPG_39_38(n)                               (WDR_BASE(n) + 0x0150)
++#define    WDR_ADDR_MAPG_41_40(n)                               (WDR_BASE(n) + 0x0154)
++#define    WDR_ADDR_MAPG_43_42(n)                               (WDR_BASE(n) + 0x0158)
++#define    WDR_ADDR_MAPG_45_44(n)                               (WDR_BASE(n) + 0x015c)
++#define    WDR_ADDR_MAPG_47_46(n)                               (WDR_BASE(n) + 0x0160)
++#define    WDR_ADDR_MAPG_49_48(n)                               (WDR_BASE(n) + 0x0164)
++#define    WDR_ADDR_MAPG_51_50(n)                               (WDR_BASE(n) + 0x0168)
++#define    WDR_ADDR_MAPG_53_52(n)                               (WDR_BASE(n) + 0x016c)
++#define    WDR_ADDR_MAPG_55_54(n)                               (WDR_BASE(n) + 0x0170)
++#define    WDR_ADDR_MAPG_57_56(n)                               (WDR_BASE(n) + 0x0174)
++#define    WDR_ADDR_MAPG_59_58(n)                               (WDR_BASE(n) + 0x0178)
++#define    WDR_ADDR_MAPG_61_60(n)                               (WDR_BASE(n) + 0x017c)
++#define    WDR_ADDR_MAPG_63_62(n)                               (WDR_BASE(n) + 0x0180)
++#define    WDR_ADDR_MAPG_65_64(n)                               (WDR_BASE(n) + 0x0184)
++#define    WDR_ADDR_MAPG_67_66(n)                               (WDR_BASE(n) + 0x0188)
++#define    WDR_ADDR_MAPG_69_68(n)                               (WDR_BASE(n) + 0x018c)
++#define    WDR_ADDR_MAPG_71_70(n)                               (WDR_BASE(n) + 0x0190)
++#define    WDR_ADDR_MAPG_73_72(n)                               (WDR_BASE(n) + 0x0194)
++#define    WDR_ADDR_MAPG_75_74(n)                               (WDR_BASE(n) + 0x0198)
++#define    WDR_ADDR_MAPG_77_76(n)                               (WDR_BASE(n) + 0x019c)
++#define    WDR_ADDR_MAPG_79_78(n)                               (WDR_BASE(n) + 0x01a0)
++#define    WDR_ADDR_MAPG_80_80(n)                               (WDR_BASE(n) + 0x01a4)
++#define    WDR_ADDR_MAPB_01_00(n)                               (WDR_BASE(n) + 0x01a8)
++#define    WDR_ADDR_MAPB_03_02(n)                               (WDR_BASE(n) + 0x01ac)
++#define    WDR_ADDR_MAPB_05_04(n)                               (WDR_BASE(n) + 0x01b0)
++#define    WDR_ADDR_MAPB_07_06(n)                               (WDR_BASE(n) + 0x01b4)
++#define    WDR_ADDR_MAPB_09_08(n)                               (WDR_BASE(n) + 0x01b8)
++#define    WDR_ADDR_MAPB_11_10(n)                               (WDR_BASE(n) + 0x01bc)
++#define    WDR_ADDR_MAPB_13_12(n)                               (WDR_BASE(n) + 0x01c0)
++#define    WDR_ADDR_MAPB_15_14(n)                               (WDR_BASE(n) + 0x01c4)
++#define    WDR_ADDR_MAPB_17_16(n)                               (WDR_BASE(n) + 0x01c8)
++#define    WDR_ADDR_MAPB_19_18(n)                               (WDR_BASE(n) + 0x01cc)
++#define    WDR_ADDR_MAPB_21_20(n)                               (WDR_BASE(n) + 0x01d0)
++#define    WDR_ADDR_MAPB_23_22(n)                               (WDR_BASE(n) + 0x01d4)
++#define    WDR_ADDR_MAPB_25_24(n)                               (WDR_BASE(n) + 0x01d8)
++#define    WDR_ADDR_MAPB_27_26(n)                               (WDR_BASE(n) + 0x01dc)
++#define    WDR_ADDR_MAPB_29_28(n)                               (WDR_BASE(n) + 0x01e0)
++#define    WDR_ADDR_MAPB_31_30(n)                               (WDR_BASE(n) + 0x01e4)
++#define    WDR_ADDR_MAPB_33_32(n)                               (WDR_BASE(n) + 0x01e8)
++#define    WDR_ADDR_MAPB_35_34(n)                               (WDR_BASE(n) + 0x01ec)
++#define    WDR_ADDR_MAPB_37_36(n)                               (WDR_BASE(n) + 0x01f0)
++#define    WDR_ADDR_MAPB_39_38(n)                               (WDR_BASE(n) + 0x01f4)
++#define    WDR_ADDR_MAPB_41_40(n)                               (WDR_BASE(n) + 0x01f8)
++#define    WDR_ADDR_MAPB_43_42(n)                               (WDR_BASE(n) + 0x01fc)
++#define    WDR_ADDR_MAPB_45_44(n)                               (WDR_BASE(n) + 0x0200)
++#define    WDR_ADDR_MAPB_47_46(n)                               (WDR_BASE(n) + 0x0204)
++#define    WDR_ADDR_MAPB_49_48(n)                               (WDR_BASE(n) + 0x0208)
++#define    WDR_ADDR_MAPB_51_50(n)                               (WDR_BASE(n) + 0x020c)
++#define    WDR_ADDR_MAPB_53_52(n)                               (WDR_BASE(n) + 0x0210)
++#define    WDR_ADDR_MAPB_55_54(n)                               (WDR_BASE(n) + 0x0214)
++#define    WDR_ADDR_MAPB_57_56(n)                               (WDR_BASE(n) + 0x0218)
++#define    WDR_ADDR_MAPB_59_58(n)                               (WDR_BASE(n) + 0x021c)
++#define    WDR_ADDR_MAPB_61_60(n)                               (WDR_BASE(n) + 0x0220)
++#define    WDR_ADDR_MAPB_63_62(n)                               (WDR_BASE(n) + 0x0224)
++#define    WDR_ADDR_MAPB_65_64(n)                               (WDR_BASE(n) + 0x0228)
++#define    WDR_ADDR_MAPB_67_66(n)                               (WDR_BASE(n) + 0x022c)
++#define    WDR_ADDR_MAPB_69_68(n)                               (WDR_BASE(n) + 0x0230)
++#define    WDR_ADDR_MAPB_71_70(n)                               (WDR_BASE(n) + 0x0234)
++#define    WDR_ADDR_MAPB_73_72(n)                               (WDR_BASE(n) + 0x0238)
++#define    WDR_ADDR_MAPB_75_74(n)                               (WDR_BASE(n) + 0x023c)
++#define    WDR_ADDR_MAPB_77_76(n)                               (WDR_BASE(n) + 0x0240)
++#define    WDR_ADDR_MAPB_79_78(n)                               (WDR_BASE(n) + 0x0244)
++#define    WDR_ADDR_MAPB_80_80(n)                               (WDR_BASE(n) + 0x0248)
++#define    WDR_ADDR_THRLABLE_01_00(n)                           (WDR_BASE(n) + 0x024c)
++#define    WDR_ADDR_THRLABLE_03_02(n)                           (WDR_BASE(n) + 0x0250)
++#define    WDR_ADDR_THRLABLE_05_04(n)                           (WDR_BASE(n) + 0x0254)
++#define    WDR_ADDR_THRLABLE_07_06(n)                           (WDR_BASE(n) + 0x0258)
++#define    WDR_ADDR_THRLABLE_09_08(n)                           (WDR_BASE(n) + 0x025c)
++#define    WDR_ADDR_THRLABLE_11_10(n)                           (WDR_BASE(n) + 0x0260)
++#define    WDR_ADDR_THRLABLE_13_12(n)                           (WDR_BASE(n) + 0x0264)
++#define    WDR_ADDR_THRLABLE_15_14(n)                           (WDR_BASE(n) + 0x0268)
++#define    WDR_ADDR_THRLABLE_17_16(n)                           (WDR_BASE(n) + 0x026c)
++#define    WDR_ADDR_THRLABLE_19_18(n)                           (WDR_BASE(n) + 0x0270)
++#define    WDR_ADDR_THRLABLE_21_20(n)                           (WDR_BASE(n) + 0x0274)
++#define    WDR_ADDR_THRLABLE_23_22(n)                           (WDR_BASE(n) + 0x0278)
++#define    WDR_ADDR_THRLABLE_25_24(n)                           (WDR_BASE(n) + 0x027c)
++#define    WDR_ADDR_THRLABLE_26_26(n)                           (WDR_BASE(n) + 0x0280)
++#define    WDR_ADDR_THRLABLEN_01_00(n)                          (WDR_BASE(n) + 0x0284)
++#define    WDR_ADDR_THRLABLEN_03_02(n)                          (WDR_BASE(n) + 0x0288)
++#define    WDR_ADDR_THRLABLEN_05_04(n)                          (WDR_BASE(n) + 0x028c)
++#define    WDR_ADDR_THRLABLEN_07_06(n)                          (WDR_BASE(n) + 0x0290)
++#define    WDR_ADDR_THRLABLEN_09_08(n)                          (WDR_BASE(n) + 0x0294)
++#define    WDR_ADDR_THRLABLEN_11_10(n)                          (WDR_BASE(n) + 0x0298)
++#define    WDR_ADDR_THRLABLEN_13_12(n)                          (WDR_BASE(n) + 0x029c)
++#define    WDR_ADDR_THRLABLEN_15_14(n)                          (WDR_BASE(n) + 0x02a0)
++#define    WDR_ADDR_THRLABLEN_17_16(n)                          (WDR_BASE(n) + 0x02a4)
++#define    WDR_ADDR_THRLABLEN_19_18(n)                          (WDR_BASE(n) + 0x02a8)
++#define    WDR_ADDR_THRLABLEN_21_20(n)                          (WDR_BASE(n) + 0x02ac)
++#define    WDR_ADDR_THRLABLEN_23_22(n)                          (WDR_BASE(n) + 0x02b0)
++#define    WDR_ADDR_THRLABLEN_25_24(n)                          (WDR_BASE(n) + 0x02b4)
++#define    WDR_ADDR_THRALL_01_00(n)                             (WDR_BASE(n) + 0x02b8)
++#define    WDR_ADDR_THRALL_03_02(n)                             (WDR_BASE(n) + 0x02bc)
++#define    WDR_ADDR_THRALL_05_04(n)                             (WDR_BASE(n) + 0x02c0)
++#define    WDR_ADDR_THRALL_07_06(n)                             (WDR_BASE(n) + 0x02c4)
++#define    WDR_ADDR_THRALL_09_08(n)                             (WDR_BASE(n) + 0x02c8)
++#define    WDR_ADDR_THRALL_11_10(n)                             (WDR_BASE(n) + 0x02cc)
++#define    WDR_ADDR_THRALL_13_12(n)                             (WDR_BASE(n) + 0x02d0)
++#define    WDR_ADDR_THRALL_15_14(n)                             (WDR_BASE(n) + 0x02d4)
++#define    WDR_ADDR_THRALL_17_16(n)                             (WDR_BASE(n) + 0x02d8)
++#define    WDR_ADDR_THRALL_19_18(n)                             (WDR_BASE(n) + 0x02dc)
++#define    WDR_ADDR_THRALL_21_20(n)                             (WDR_BASE(n) + 0x02e0)
++#define    WDR_ADDR_THRALL_23_22(n)                             (WDR_BASE(n) + 0x02e4)
++#define    WDR_ADDR_THRALL_25_24(n)                             (WDR_BASE(n) + 0x02e8)
++#define    WDR_ADDR_THRALL_26_26(n)                             (WDR_BASE(n) + 0x02ec)
++#define    WDR_ADDR_THRRANGEK_00_00(n)                          (WDR_BASE(n) + 0x02f0)
++#define    WDR_ADDR_THRRANGEK_01_01(n)                          (WDR_BASE(n) + 0x02f4)
++#define    WDR_ADDR_THRRANGEK_02_02(n)                          (WDR_BASE(n) + 0x02f8)
++#define    WDR_ADDR_THRRANGEK_03_03(n)                          (WDR_BASE(n) + 0x02fc)
++#define    WDR_ADDR_THRRANGEK_04_04(n)                          (WDR_BASE(n) + 0x0300)
++#define    WDR_ADDR_THRRANGEK_05_05(n)                          (WDR_BASE(n) + 0x0304)
++#define    WDR_ADDR_THRRANGEK_06_06(n)                          (WDR_BASE(n) + 0x0308)
++#define    WDR_ADDR_THRRANGEK_07_07(n)                          (WDR_BASE(n) + 0x030c)
++#define    WDR_ADDR_THRRANGEK_08_08(n)                          (WDR_BASE(n) + 0x0310)
++#define    WDR_ADDR_THRRANGEK_09_09(n)                          (WDR_BASE(n) + 0x0314)
++#define    WDR_ADDR_THRRANGEK_10_10(n)                          (WDR_BASE(n) + 0x0318)
++#define    WDR_ADDR_THRRANGEK_11_11(n)                          (WDR_BASE(n) + 0x031c)
++#define    WDR_ADDR_THRRANGEK_12_12(n)                          (WDR_BASE(n) + 0x0320)
++#define    WDR_ADDR_THRRANGEK_13_13(n)                          (WDR_BASE(n) + 0x0324)
++#define    WDR_ADDR_THRRANGEK_14_14(n)                          (WDR_BASE(n) + 0x0328)
++#define    WDR_ADDR_THRRANGEK_15_15(n)                          (WDR_BASE(n) + 0x032c)
++#define    WDR_ADDR_THRRANGEK_16_16(n)                          (WDR_BASE(n) + 0x0330)
++#define    WDR_ADDR_THRRANGEK_17_17(n)                          (WDR_BASE(n) + 0x0334)
++#define    WDR_ADDR_THRRANGEK_18_18(n)                          (WDR_BASE(n) + 0x0338)
++#define    WDR_ADDR_THRRANGEK_19_19(n)                          (WDR_BASE(n) + 0x033c)
++#define    WDR_ADDR_THRRANGEK_20_20(n)                          (WDR_BASE(n) + 0x0340)
++#define    WDR_ADDR_THRRANGEK_21_21(n)                          (WDR_BASE(n) + 0x0344)
++#define    WDR_ADDR_THRRANGEK_22_22(n)                          (WDR_BASE(n) + 0x0348)
++#define    WDR_ADDR_THRRANGEK_23_23(n)                          (WDR_BASE(n) + 0x034c)
++#define    WDR_ADDR_THRRANGEK_24_24(n)                          (WDR_BASE(n) + 0x0350)
++#define    WDR_ADDR_THRRANGEK_25_25(n)                          (WDR_BASE(n) + 0x0354)
++#define    WDR_ADDR_THRRANGEK_26_26(n)                          (WDR_BASE(n) + 0x0358)
++#define    WDR_ADDR_DARKLABLE_01_00(n)                          (WDR_BASE(n) + 0x035c)
++#define    WDR_ADDR_DARKLABLE_03_02(n)                          (WDR_BASE(n) + 0x0360)
++#define    WDR_ADDR_DARKLABLE_04_04(n)                          (WDR_BASE(n) + 0x0364)
++#define    WDR_ADDR_DARKLABLEN_01_00(n)                         (WDR_BASE(n) + 0x0368)
++#define    WDR_ADDR_DARKLABLEN_03_02(n)                         (WDR_BASE(n) + 0x036c)
++#define    WDR_ADDR_DARKWEIGHT_01_00(n)                         (WDR_BASE(n) + 0x0370)
++#define    WDR_ADDR_DARKWEIGHT_03_02(n)                         (WDR_BASE(n) + 0x0374)
++#define    WDR_ADDR_DARKWEIGHT_04_04(n)                         (WDR_BASE(n) + 0x0378)
++#define    WDR_ADDR_NOISEREDUCELABLE_00_00(n)                   (WDR_BASE(n) + 0x037c)
++#define    WDR_ADDR_LABLE_ENRATE(n)                             (WDR_BASE(n) + 0x0380)
++#define    WDR_ADDR_VALUE_ENRATE(n)                             (WDR_BASE(n) + 0x0384)
++#define    WDR_ADDR_K_ENRATE1(n)                                (WDR_BASE(n) + 0x0388)
++#define    WDR_ADDR_K_ENRATE2(n)                                (WDR_BASE(n) + 0x038c)
++#define    WDR_ADDR_ENMAXMIN_V1(n)                              (WDR_BASE(n) + 0x0390)
++#define    WDR_ADDR_RATIO_MINMAX_X(n)                           (WDR_BASE(n) + 0x0394)
++#define    WDR_ADDR_K_RATIO_MINMAX_Y(n)                         (WDR_BASE(n) + 0x039c)
++#define    WDR_ADDR_K_K_RATIO(n)                                (WDR_BASE(n) + 0x03a0)
++#define    WDR_ADDR_FUSIONTHRMINMAX_X(n)                        (WDR_BASE(n) + 0x03a4)
++#define    WDR_ADDR_K_WEIGHT(n)                                 (WDR_BASE(n) + 0x03a8)
++#define    WDR_ADDR_MAXVALUE(n)                                 (WDR_BASE(n) + 0x03ac)
++#define    WDR_ADDR_TMP_MAXVALUE(n)                             (WDR_BASE(n) + 0x03b0)
++#define    WDR_ADDR_THR_MAXVALUE_12BIT(n)                       (WDR_BASE(n) + 0x03b4)
++#define    WDR_ADDR_TMP_FUSION_MAX(n)                           (WDR_BASE(n) + 0x03b8)
++#define    WDR_ADDR_W_FUSION_X(n)                               (WDR_BASE(n) + 0x03bc)
++#define    WDR_ADDR_K_W_FUSION0(n)                              (WDR_BASE(n) + 0x03c0)
++#define    WDR_ADDR_LAMDA_01(n)                                 (WDR_BASE(n) + 0x03c4)
++#define    WDR_ADDR_LAMDA_23(n)                                 (WDR_BASE(n) + 0x03c8)
++#define    WDR_ADDR_LAMDA_4(n)                                  (WDR_BASE(n) + 0x03cc)
++#define    WDR_ADDR_W_FUSION_X1(n)                              (WDR_BASE(n) + 0x03d0)
++#define    WDR_ADDR_W_FUSION_X_N(n)                             (WDR_BASE(n) + 0x03d4)
++#define    WDR_ADDR_CONSTRACT_MAXVALUE_LOG(n)                   (WDR_BASE(n) + 0x03d8)
++#define    WDR_ADDR_TMP_MAXVALUE_LOG(n)                         (WDR_BASE(n) + 0x03dc)
++#define    WDR_ADDR_LABLE_EN_01(n)                              (WDR_BASE(n) + 0x03e0)
++#define    WDR_ADDR_LABLE_EN_2(n)                               (WDR_BASE(n) + 0x03e4)
++#define    WDR_ADDR_VALUE_EN1(n)                                (WDR_BASE(n) + 0x03e8)
++#define    WDR_ADDR_LABLE_EN_Y_01(n)                            (WDR_BASE(n) + 0x03ec)
++#define    WDR_ADDR_LABLE_EN_Y_2(n)                             (WDR_BASE(n) + 0x03f0)
++#define    WDR_ADDR_K_EN1(n)                                    (WDR_BASE(n) + 0x03f4)
++#define    WDR_ADDR_K_EN2(n)                                    (WDR_BASE(n) + 0x03f8)
++#define    WDR_ADDR_TMP_EN1(n)                                  (WDR_BASE(n) + 0x03fc)
++#define    WDR_ADDR_TMP_EN2(n)                                  (WDR_BASE(n) + 0x0400)
++#define    WDR_ADDR_D_RATIO(n)                                  (WDR_BASE(n) + 0x0404)
++#define    WDR_ADDR_LABLE_Y_SHORT(n)                            (WDR_BASE(n) + 0x0408)
++#define    WDR_ADDR_LABLE_W(n)                                  (WDR_BASE(n) + 0x040c)
++#define    WDR_ADDR_THR_DENOISE(n)                              (WDR_BASE(n) + 0x0410)
++#define    WDR_ADDR_VALUE_GAMMA_01_00(n)                        (WDR_BASE(n) + 0x0420)
++#define    WDR_ADDR_VALUE_GAMMA_03_02(n)                        (WDR_BASE(n) + 0x0424)
++#define    WDR_ADDR_VALUE_GAMMA_05_04(n)                        (WDR_BASE(n) + 0x0428)
++#define    WDR_ADDR_VALUE_GAMMA_07_06(n)                        (WDR_BASE(n) + 0x042c)
++#define    WDR_ADDR_VALUE_GAMMA_09_08(n)                        (WDR_BASE(n) + 0x0430)
++#define    WDR_ADDR_VALUE_GAMMA_11_10(n)                        (WDR_BASE(n) + 0x0434)
++#define    WDR_ADDR_VALUE_GAMMA_13_12(n)                        (WDR_BASE(n) + 0x0438)
++#define    WDR_ADDR_VALUE_GAMMA_15_14(n)                        (WDR_BASE(n) + 0x043c)
++#define    WDR_ADDR_VALUE_GAMMA_17_16(n)                        (WDR_BASE(n) + 0x0440)
++#define    WDR_ADDR_VALUE_GAMMA_19_18(n)                        (WDR_BASE(n) + 0x0444)
++#define    WDR_ADDR_VALUE_GAMMA_21_20(n)                        (WDR_BASE(n) + 0x0448)
++#define    WDR_ADDR_VALUE_GAMMA_23_22(n)                        (WDR_BASE(n) + 0x044c)
++#define    WDR_ADDR_VALUE_GAMMA_25_24(n)                        (WDR_BASE(n) + 0x0450)
++#define    WDR_ADDR_VALUE_GAMMA_27_26(n)                        (WDR_BASE(n) + 0x0454)
++#define    WDR_ADDR_VALUE_GAMMA_29_28(n)                        (WDR_BASE(n) + 0x0458)
++#define    WDR_ADDR_VALUE_GAMMA_31_30(n)                        (WDR_BASE(n) + 0x045c)
++#define    WDR_ADDR_VALUE_GAMMA_33_32(n)                        (WDR_BASE(n) + 0x0460)
++#define    WDR_ADDR_VALUE_GAMMA_35_34(n)                        (WDR_BASE(n) + 0x0464)
++#define    WDR_ADDR_VALUE_GAMMA_37_36(n)                        (WDR_BASE(n) + 0x0468)
++#define    WDR_ADDR_VALUE_GAMMA_39_38(n)                        (WDR_BASE(n) + 0x046c)
++#define    WDR_ADDR_VALUE_GAMMA_41_40(n)                        (WDR_BASE(n) + 0x0470)
++#define    WDR_ADDR_VALUE_GAMMA_43_42(n)                        (WDR_BASE(n) + 0x0474)
++#define    WDR_ADDR_VALUE_GAMMA_45_44(n)                        (WDR_BASE(n) + 0x0478)
++#define    WDR_ADDR_VALUE_GAMMA_47_46(n)                        (WDR_BASE(n) + 0x047c)
++#define    WDR_ADDR_VALUE_GAMMA_49_48(n)                        (WDR_BASE(n) + 0x0480)
++#define    WDR_ADDR_VALUE_GAMMA_51_50(n)                        (WDR_BASE(n) + 0x0484)
++#define    WDR_ADDR_VALUE_GAMMA_53_52(n)                        (WDR_BASE(n) + 0x0488)
++#define    WDR_ADDR_VALUE_GAMMA_55_54(n)                        (WDR_BASE(n) + 0x048c)
++#define    WDR_ADDR_VALUE_GAMMA_57_56(n)                        (WDR_BASE(n) + 0x0490)
++#define    WDR_ADDR_VALUE_GAMMA_59_58(n)                        (WDR_BASE(n) + 0x0494)
++#define    WDR_ADDR_VALUE_GAMMA_61_60(n)                        (WDR_BASE(n) + 0x0498)
++#define    WDR_ADDR_VALUE_GAMMA_63_62(n)                        (WDR_BASE(n) + 0x049c)
++#define    WDR_ADDR_VALUE_GAMMA_65_64(n)                        (WDR_BASE(n) + 0x04a0)
++#define    WDR_ADDR_VALUE_GAMMA_67_66(n)                        (WDR_BASE(n) + 0x04a4)
++#define    WDR_ADDR_VALUE_GAMMA_69_68(n)                        (WDR_BASE(n) + 0x04a8)
++#define    WDR_ADDR_VALUE_GAMMA_71_70(n)                        (WDR_BASE(n) + 0x04ac)
++#define    WDR_ADDR_VALUE_GAMMA_73_72(n)                        (WDR_BASE(n) + 0x04b0)
++#define    WDR_ADDR_VALUE_GAMMA_75_74(n)                        (WDR_BASE(n) + 0x04b4)
++#define    WDR_ADDR_VALUE_GAMMA_77_76(n)                        (WDR_BASE(n) + 0x04b8)
++#define    WDR_ADDR_VALUE_GAMMA_79_78(n)                        (WDR_BASE(n) + 0x04bc)
++#define    WDR_ADDR_VALUE_GAMMA_81_80(n)                        (WDR_BASE(n) + 0x04c0)
++#define    WDR_ADDR_VALUE_GAMMA_83_82(n)                        (WDR_BASE(n) + 0x04c4)
++#define    WDR_ADDR_VALUE_GAMMA_85_84(n)                        (WDR_BASE(n) + 0x04c8)
++#define    WDR_ADDR_VALUE_GAMMA_87_86(n)                        (WDR_BASE(n) + 0x04cc)
++#define    WDR_ADDR_VALUE_GAMMA_89_88(n)                        (WDR_BASE(n) + 0x04d0)
++#define    WDR_ADDR_VALUE_GAMMA_91_90(n)                        (WDR_BASE(n) + 0x04d4)
++#define    WDR_ADDR_VALUE_GAMMA_93_92(n)                        (WDR_BASE(n) + 0x04d8)
++#define    WDR_ADDR_VALUE_GAMMA_95_94(n)                        (WDR_BASE(n) + 0x04dc)
++#define    WDR_ADDR_VALUE_GAMMA_96_96(n)                        (WDR_BASE(n) + 0x04e0)
++#define    WDR_ADDR_VALUE_ZIP_01_00(n)                          (WDR_BASE(n) + 0x04e4)
++#define    WDR_ADDR_VALUE_ZIP_03_02(n)                          (WDR_BASE(n) + 0x04e8)
++#define    WDR_ADDR_VALUE_ZIP_05_04(n)                          (WDR_BASE(n) + 0x04ec)
++#define    WDR_ADDR_VALUE_ZIP_07_06(n)                          (WDR_BASE(n) + 0x04f0)
++#define    WDR_ADDR_VALUE_ZIP_09_08(n)                          (WDR_BASE(n) + 0x04f4)
++#define    WDR_ADDR_VALUE_ZIP_11_10(n)                          (WDR_BASE(n) + 0x04f8)
++#define    WDR_ADDR_VALUE_ZIP_13_12(n)                          (WDR_BASE(n) + 0x04fc)
++#define    WDR_ADDR_VALUE_ZIP_15_14(n)                          (WDR_BASE(n) + 0x0500)
++#define    WDR_ADDR_VALUE_ZIP_17_16(n)                          (WDR_BASE(n) + 0x0504)
++#define    WDR_ADDR_VALUE_ZIP_19_18(n)                          (WDR_BASE(n) + 0x0508)
++#define    WDR_ADDR_VALUE_ZIP_21_20(n)                          (WDR_BASE(n) + 0x050c)
++#define    WDR_ADDR_VALUE_ZIP_23_22(n)                          (WDR_BASE(n) + 0x0510)
++#define    WDR_ADDR_VALUE_ZIP_25_24(n)                          (WDR_BASE(n) + 0x0514)
++#define    WDR_ADDR_VALUE_ZIP_27_26(n)                          (WDR_BASE(n) + 0x0518)
++#define    WDR_ADDR_VALUE_ZIP_29_28(n)                          (WDR_BASE(n) + 0x051c)
++#define    WDR_ADDR_VALUE_ZIP_31_30(n)                          (WDR_BASE(n) + 0x0520)
++#define    WDR_ADDR_VALUE_ZIP_33_32(n)                          (WDR_BASE(n) + 0x0524)
++#define    WDR_ADDR_VALUE_ZIP_35_34(n)                          (WDR_BASE(n) + 0x0528)
++#define    WDR_ADDR_VALUE_ZIP_37_36(n)                          (WDR_BASE(n) + 0x052c)
++#define    WDR_ADDR_VALUE_ZIP_39_38(n)                          (WDR_BASE(n) + 0x0530)
++#define    WDR_ADDR_VALUE_ZIP_41_40(n)                          (WDR_BASE(n) + 0x0534)
++#define    WDR_ADDR_VALUE_ZIP_43_42(n)                          (WDR_BASE(n) + 0x0538)
++#define    WDR_ADDR_VALUE_ZIP_45_44(n)                          (WDR_BASE(n) + 0x053c)
++#define    WDR_ADDR_VALUE_ZIP_47_46(n)                          (WDR_BASE(n) + 0x0540)
++#define    WDR_ADDR_VALUE_ZIP_49_48(n)                          (WDR_BASE(n) + 0x0544)
++#define    WDR_ADDR_VALUE_ZIP_51_50(n)                          (WDR_BASE(n) + 0x0548)
++#define    WDR_ADDR_VALUE_ZIP_53_52(n)                          (WDR_BASE(n) + 0x054c)
++#define    WDR_ADDR_VALUE_ZIP_55_54(n)                          (WDR_BASE(n) + 0x0550)
++#define    WDR_ADDR_VALUE_ZIP_57_56(n)                          (WDR_BASE(n) + 0x0554)
++#define    WDR_ADDR_VALUE_ZIP_59_58(n)                          (WDR_BASE(n) + 0x0558)
++#define    WDR_ADDR_VALUE_ZIP_61_60(n)                          (WDR_BASE(n) + 0x055c)
++#define    WDR_ADDR_VALUE_ZIP_63_62(n)                          (WDR_BASE(n) + 0x0560)
++#define    WDR_ADDR_VALUE_ZIP_65_64(n)                          (WDR_BASE(n) + 0x0564)
++#define    WDR_ADDR_VALUE_ZIP_67_66(n)                          (WDR_BASE(n) + 0x0568)
++#define    WDR_ADDR_VALUE_ZIP_69_68(n)                          (WDR_BASE(n) + 0x056c)
++#define    WDR_ADDR_VALUE_ZIP_71_70(n)                          (WDR_BASE(n) + 0x0570)
++#define    WDR_ADDR_VALUE_ZIP_73_72(n)                          (WDR_BASE(n) + 0x0574)
++#define    WDR_ADDR_VALUE_ZIP_75_74(n)                          (WDR_BASE(n) + 0x0578)
++#define    WDR_ADDR_VALUE_ZIP_77_76(n)                          (WDR_BASE(n) + 0x057c)
++#define    WDR_ADDR_VALUE_ZIP_79_78(n)                          (WDR_BASE(n) + 0x0580)
++#define    WDR_ADDR_VALUE_ZIP_81_80(n)                          (WDR_BASE(n) + 0x0584)
++#define    WDR_ADDR_VALUE_ZIP_83_82(n)                          (WDR_BASE(n) + 0x0588)
++#define    WDR_ADDR_VALUE_ZIP_85_84(n)                          (WDR_BASE(n) + 0x058c)
++#define    WDR_ADDR_VALUE_ZIP_87_86(n)                          (WDR_BASE(n) + 0x0590)
++#define    WDR_ADDR_VALUE_ZIP_89_88(n)                          (WDR_BASE(n) + 0x0594)
++#define    WDR_ADDR_VALUE_ZIP_91_90(n)                          (WDR_BASE(n) + 0x0598)
++#define    WDR_ADDR_VALUE_ZIP_93_92(n)                          (WDR_BASE(n) + 0x059c)
++#define    WDR_ADDR_VALUE_ZIP_95_94(n)                          (WDR_BASE(n) + 0x05a0)
++#define    WDR_ADDR_VALUE_ZIP_97_96(n)                          (WDR_BASE(n) + 0x05a4)
++#define    WDR_ADDR_VALUE_ZIP_98_98(n)                          (WDR_BASE(n) + 0x05a8)
++#define    WDR_ADDR_VALUE_FUSION_01_00(n)                       (WDR_BASE(n) + 0x05ac)
++#define    WDR_ADDR_VALUE_FUSION_03_02(n)                       (WDR_BASE(n) + 0x05b0)
++#define    WDR_ADDR_VALUE_FUSION_05_04(n)                       (WDR_BASE(n) + 0x05b4)
++#define    WDR_ADDR_VALUE_FUSION_07_06(n)                       (WDR_BASE(n) + 0x05b8)
++#define    WDR_ADDR_VALUE_FUSION_09_08(n)                       (WDR_BASE(n) + 0x05bc)
++#define    WDR_ADDR_VALUE_FUSION_11_10(n)                       (WDR_BASE(n) + 0x05c0)
++#define    WDR_ADDR_VALUE_FUSION_13_12(n)                       (WDR_BASE(n) + 0x05c4)
++#define    WDR_ADDR_VALUE_FUSION_15_14(n)                       (WDR_BASE(n) + 0x05c8)
++#define    WDR_ADDR_VALUE_FUSION_17_16(n)                       (WDR_BASE(n) + 0x05cc)
++#define    WDR_ADDR_VALUE_FUSION_19_18(n)                       (WDR_BASE(n) + 0x05d0)
++#define    WDR_ADDR_VALUE_FUSION_21_20(n)                       (WDR_BASE(n) + 0x05d4)
++#define    WDR_ADDR_VALUE_FUSION_23_22(n)                       (WDR_BASE(n) + 0x05d8)
++#define    WDR_ADDR_VALUE_FUSION_25_24(n)                       (WDR_BASE(n) + 0x05dc)
++#define    WDR_ADDR_VALUE_FUSION_27_26(n)                       (WDR_BASE(n) + 0x05e0)
++#define    WDR_ADDR_VALUE_FUSION_29_28(n)                       (WDR_BASE(n) + 0x05e4)
++#define    WDR_ADDR_VALUE_FUSION_31_30(n)                       (WDR_BASE(n) + 0x05e8)
++#define    WDR_ADDR_VALUE_FUSION_32_32(n)                       (WDR_BASE(n) + 0x05ec)
++#define    WDR_ADDR_VALUE_W_LINE_01_00(n)                       (WDR_BASE(n) + 0x05f0)
++#define    WDR_ADDR_VALUE_W_LINE_03_02(n)                       (WDR_BASE(n) + 0x05f4)
++#define    WDR_ADDR_VALUE_W_LINE_04_04(n)                       (WDR_BASE(n) + 0x05f8)
++#define    WDR_ADDR_FUSIONTHRMAX_Y(n)                           (WDR_BASE(n) + 0x05fc)
++#define    WDR_ADDR_D_WH(n)                                     (WDR_BASE(n) + 0x0600)
++#define    WDR_ADDR_STAT_EN(n)                                  (WDR_BASE(n) + 0x0604)
++#define    WDR_ADDR_STA_INFO_ADDR0(n)                           (WDR_BASE(n) + 0x0610)
++#define    WDR_ADDR_STA_INFO_CNT0(n)                            (WDR_BASE(n) + 0x0614)
++#define    WDR_ADDR_STA_INFO_ADDR1(n)                           (WDR_BASE(n) + 0x0618)
++#define    WDR_ADDR_STA_INFO_CNT1(n)                            (WDR_BASE(n) + 0x061c)
++#define    WDR_ADDR_DBG_00_00(n)                                (WDR_BASE(n) + 0x0680)
++#define    WDR_ADDR_DBG_01_01(n)                                (WDR_BASE(n) + 0x0684)
++#define    WDR_ADDR_DBG_02_02(n)                                (WDR_BASE(n) + 0x0688)
++#define    WDR_ADDR_DBG_03_03(n)                                (WDR_BASE(n) + 0x068c)
++#define    WDR_ADDR_DBG_04_04(n)                                (WDR_BASE(n) + 0x0690)
++#define    WDR_ADDR_DBG_05_05(n)                                (WDR_BASE(n) + 0x0694)
++#define    WDR_ADDR_DBG_06_06(n)                                (WDR_BASE(n) + 0x0698)
++#define    WDR_ADDR_DBG_07_07(n)                                (WDR_BASE(n) + 0x069c)
++
++#define    MAIN_WDR_ADDR_T_VERSION                                (WDR0_BASE + 0x0000)
++#define    MAIN_WDR_ADDR_STA_ST_ADDR_000_00                       (WDR0_BASE + 0x0010)
++#define    MAIN_WDR_ADDR_STA_ST_ADDR_001_01                       (WDR0_BASE + 0x0014)
++#define    MAIN_WDR_ADDR_STA_ST_ADDR_002_02                       (WDR0_BASE + 0x0018)
++#define    MAIN_WDR_ADDR_STA_ST_ADDR_003_03                       (WDR0_BASE + 0x001c)
++#define    MAIN_WDR_ADDR_STA_BUF_NUM                              (WDR0_BASE + 0x0030)
++#define    MAIN_WDR_ADDR_STA_EXT_PRIO                             (WDR0_BASE + 0x0034)
++#define    MAIN_WDR_ADDR_DEBUG                                    (WDR0_BASE + 0x0040)
++#define    MAIN_WDR_ADDR_STA_THR                                  (WDR0_BASE + 0x0048)
++#define    MAIN_WDR_ADDR_STA_INFO_ADDR0                           (WDR0_BASE + 0x0610)
++#define    MAIN_WDR_ADDR_STA_INFO_CNT0                            (WDR0_BASE + 0x0614)
++#define    MAIN_WDR_ADDR_STA_INFO_ADDR1                           (WDR0_BASE + 0x0618)
++#define    MAIN_WDR_ADDR_STA_INFO_CNT1                            (WDR0_BASE + 0x061c)
++#define    MAIN_WDR_ADDR_DBG_00_00                                (WDR0_BASE + 0x0680)
++#define    MAIN_WDR_ADDR_DBG_01_01                                (WDR0_BASE + 0x0684)
++#define    MAIN_WDR_ADDR_DBG_02_02                                (WDR0_BASE + 0x0688)
++#define    MAIN_WDR_ADDR_DBG_03_03                                (WDR0_BASE + 0x068c)
++#define    MAIN_WDR_ADDR_DBG_04_04                                (WDR0_BASE + 0x0690)
++#define    MAIN_WDR_ADDR_DBG_05_05                                (WDR0_BASE + 0x0694)
++#define    MAIN_WDR_ADDR_DBG_06_06                                (WDR0_BASE + 0x0698)
++#define    MAIN_WDR_ADDR_DBG_07_07                                (WDR0_BASE + 0x069c)
++
++#define    SEC_WDR_ADDR_T_VERSION                                 (WDR1_BASE + 0x0000)
++#define    SEC_WDR_ADDR_STA_ST_ADDR_000_00                        (WDR1_BASE + 0x0010)
++#define    SEC_WDR_ADDR_STA_ST_ADDR_001_01                        (WDR1_BASE + 0x0014)
++#define    SEC_WDR_ADDR_STA_ST_ADDR_002_02                        (WDR1_BASE + 0x0018)
++#define    SEC_WDR_ADDR_STA_ST_ADDR_003_03                        (WDR1_BASE + 0x001c)
++#define    SEC_WDR_ADDR_STA_BUF_NUM                               (WDR1_BASE + 0x0030)
++#define    SEC_WDR_ADDR_STA_EXT_PRIO                              (WDR1_BASE + 0x0034)
++#define    SEC_WDR_ADDR_DEBUG                                     (WDR1_BASE + 0x0040)
++#define    SEC_WDR_ADDR_STA_THR                                   (WDR1_BASE + 0x0048)
++#define    SEC_WDR_ADDR_DEGOSTPARA_0                              (WDR1_BASE + 0x004c)
++#define    SEC_WDR_ADDR_DEGOSTPARA_1                              (WDR1_BASE + 0x0050)
++#define    SEC_WDR_ADDR_DEGOSTPARA_2                              (WDR1_BASE + 0x0054)
++#define    SEC_WDR_ADDR_DEGOSTPARA_3                              (WDR1_BASE + 0x0058)
++#define    SEC_WDR_ADDR_DEGOSTPARA_4                              (WDR1_BASE + 0x005c)
++#define    SEC_WDR_ADDR_MAPR_01_00                                (WDR1_BASE + 0x0060)
++#define    SEC_WDR_ADDR_MAPR_03_02                                (WDR1_BASE + 0x0064)
++#define    SEC_WDR_ADDR_MAPR_05_04                                (WDR1_BASE + 0x0068)
++#define    SEC_WDR_ADDR_MAPR_07_06                                (WDR1_BASE + 0x006c)
++#define    SEC_WDR_ADDR_MAPR_09_08                                (WDR1_BASE + 0x0070)
++#define    SEC_WDR_ADDR_MAPR_11_10                                (WDR1_BASE + 0x0074)
++#define    SEC_WDR_ADDR_MAPR_13_12                                (WDR1_BASE + 0x0078)
++#define    SEC_WDR_ADDR_MAPR_15_14                                (WDR1_BASE + 0x007c)
++#define    SEC_WDR_ADDR_MAPR_17_16                                (WDR1_BASE + 0x0080)
++#define    SEC_WDR_ADDR_MAPR_19_18                                (WDR1_BASE + 0x0084)
++#define    SEC_WDR_ADDR_MAPR_21_20                                (WDR1_BASE + 0x0088)
++#define    SEC_WDR_ADDR_MAPR_23_22                                (WDR1_BASE + 0x008c)
++#define    SEC_WDR_ADDR_MAPR_25_24                                (WDR1_BASE + 0x0090)
++#define    SEC_WDR_ADDR_MAPR_27_26                                (WDR1_BASE + 0x0094)
++#define    SEC_WDR_ADDR_MAPR_29_28                                (WDR1_BASE + 0x0098)
++#define    SEC_WDR_ADDR_MAPR_31_30                                (WDR1_BASE + 0x009c)
++#define    SEC_WDR_ADDR_MAPR_33_32                                (WDR1_BASE + 0x00a0)
++#define    SEC_WDR_ADDR_MAPR_35_34                                (WDR1_BASE + 0x00a4)
++#define    SEC_WDR_ADDR_MAPR_37_36                                (WDR1_BASE + 0x00a8)
++#define    SEC_WDR_ADDR_MAPR_39_38                                (WDR1_BASE + 0x00ac)
++#define    SEC_WDR_ADDR_MAPR_41_40                                (WDR1_BASE + 0x00b0)
++#define    SEC_WDR_ADDR_MAPR_43_42                                (WDR1_BASE + 0x00b4)
++#define    SEC_WDR_ADDR_MAPR_45_44                                (WDR1_BASE + 0x00b8)
++#define    SEC_WDR_ADDR_MAPR_47_46                                (WDR1_BASE + 0x00bc)
++#define    SEC_WDR_ADDR_MAPR_49_48                                (WDR1_BASE + 0x00c0)
++#define    SEC_WDR_ADDR_MAPR_51_50                                (WDR1_BASE + 0x00c4)
++#define    SEC_WDR_ADDR_MAPR_53_52                                (WDR1_BASE + 0x00c8)
++#define    SEC_WDR_ADDR_MAPR_55_54                                (WDR1_BASE + 0x00cc)
++#define    SEC_WDR_ADDR_MAPR_57_56                                (WDR1_BASE + 0x00d0)
++#define    SEC_WDR_ADDR_MAPR_59_58                                (WDR1_BASE + 0x00d4)
++#define    SEC_WDR_ADDR_MAPR_61_60                                (WDR1_BASE + 0x00d8)
++#define    SEC_WDR_ADDR_MAPR_63_62                                (WDR1_BASE + 0x00dc)
++#define    SEC_WDR_ADDR_MAPR_65_64                                (WDR1_BASE + 0x00e0)
++#define    SEC_WDR_ADDR_MAPR_67_66                                (WDR1_BASE + 0x00e4)
++#define    SEC_WDR_ADDR_MAPR_69_68                                (WDR1_BASE + 0x00e8)
++#define    SEC_WDR_ADDR_MAPR_71_70                                (WDR1_BASE + 0x00ec)
++#define    SEC_WDR_ADDR_MAPR_73_72                                (WDR1_BASE + 0x00f0)
++#define    SEC_WDR_ADDR_MAPR_75_74                                (WDR1_BASE + 0x00f4)
++#define    SEC_WDR_ADDR_MAPR_77_76                                (WDR1_BASE + 0x00f8)
++#define    SEC_WDR_ADDR_MAPR_79_78                                (WDR1_BASE + 0x00fc)
++#define    SEC_WDR_ADDR_MAPR_80_80                                (WDR1_BASE + 0x0100)
++#define    SEC_WDR_ADDR_MAPG_01_00                                (WDR1_BASE + 0x0104)
++#define    SEC_WDR_ADDR_MAPG_03_02                                (WDR1_BASE + 0x0108)
++#define    SEC_WDR_ADDR_MAPG_05_04                                (WDR1_BASE + 0x010c)
++#define    SEC_WDR_ADDR_MAPG_07_06                                (WDR1_BASE + 0x0110)
++#define    SEC_WDR_ADDR_MAPG_09_08                                (WDR1_BASE + 0x0114)
++#define    SEC_WDR_ADDR_MAPG_11_10                                (WDR1_BASE + 0x0118)
++#define    SEC_WDR_ADDR_MAPG_13_12                                (WDR1_BASE + 0x011c)
++#define    SEC_WDR_ADDR_MAPG_15_14                                (WDR1_BASE + 0x0120)
++#define    SEC_WDR_ADDR_MAPG_17_16                                (WDR1_BASE + 0x0124)
++#define    SEC_WDR_ADDR_MAPG_19_18                                (WDR1_BASE + 0x0128)
++#define    SEC_WDR_ADDR_MAPG_21_20                                (WDR1_BASE + 0x012c)
++#define    SEC_WDR_ADDR_MAPG_23_22                                (WDR1_BASE + 0x0130)
++#define    SEC_WDR_ADDR_MAPG_25_24                                (WDR1_BASE + 0x0134)
++#define    SEC_WDR_ADDR_MAPG_27_26                                (WDR1_BASE + 0x0138)
++#define    SEC_WDR_ADDR_MAPG_29_28                                (WDR1_BASE + 0x013c)
++#define    SEC_WDR_ADDR_MAPG_31_30                                (WDR1_BASE + 0x0140)
++#define    SEC_WDR_ADDR_MAPG_33_32                                (WDR1_BASE + 0x0144)
++#define    SEC_WDR_ADDR_MAPG_35_34                                (WDR1_BASE + 0x0148)
++#define    SEC_WDR_ADDR_MAPG_37_36                                (WDR1_BASE + 0x014c)
++#define    SEC_WDR_ADDR_MAPG_39_38                                (WDR1_BASE + 0x0150)
++#define    SEC_WDR_ADDR_MAPG_41_40                                (WDR1_BASE + 0x0154)
++#define    SEC_WDR_ADDR_MAPG_43_42                                (WDR1_BASE + 0x0158)
++#define    SEC_WDR_ADDR_MAPG_45_44                                (WDR1_BASE + 0x015c)
++#define    SEC_WDR_ADDR_MAPG_47_46                                (WDR1_BASE + 0x0160)
++#define    SEC_WDR_ADDR_MAPG_49_48                                (WDR1_BASE + 0x0164)
++#define    SEC_WDR_ADDR_MAPG_51_50                                (WDR1_BASE + 0x0168)
++#define    SEC_WDR_ADDR_MAPG_53_52                                (WDR1_BASE + 0x016c)
++#define    SEC_WDR_ADDR_MAPG_55_54                                (WDR1_BASE + 0x0170)
++#define    SEC_WDR_ADDR_MAPG_57_56                                (WDR1_BASE + 0x0174)
++#define    SEC_WDR_ADDR_MAPG_59_58                                (WDR1_BASE + 0x0178)
++#define    SEC_WDR_ADDR_MAPG_61_60                                (WDR1_BASE + 0x017c)
++#define    SEC_WDR_ADDR_MAPG_63_62                                (WDR1_BASE + 0x0180)
++#define    SEC_WDR_ADDR_MAPG_65_64                                (WDR1_BASE + 0x0184)
++#define    SEC_WDR_ADDR_MAPG_67_66                                (WDR1_BASE + 0x0188)
++#define    SEC_WDR_ADDR_MAPG_69_68                                (WDR1_BASE + 0x018c)
++#define    SEC_WDR_ADDR_MAPG_71_70                                (WDR1_BASE + 0x0190)
++#define    SEC_WDR_ADDR_MAPG_73_72                                (WDR1_BASE + 0x0194)
++#define    SEC_WDR_ADDR_MAPG_75_74                                (WDR1_BASE + 0x0198)
++#define    SEC_WDR_ADDR_MAPG_77_76                                (WDR1_BASE + 0x019c)
++#define    SEC_WDR_ADDR_MAPG_79_78                                (WDR1_BASE + 0x01a0)
++#define    SEC_WDR_ADDR_MAPG_80_80                                (WDR1_BASE + 0x01a4)
++#define    SEC_WDR_ADDR_MAPB_01_00                                (WDR1_BASE + 0x01a8)
++#define    SEC_WDR_ADDR_MAPB_03_02                                (WDR1_BASE + 0x01ac)
++#define    SEC_WDR_ADDR_MAPB_05_04                                (WDR1_BASE + 0x01b0)
++#define    SEC_WDR_ADDR_MAPB_07_06                                (WDR1_BASE + 0x01b4)
++#define    SEC_WDR_ADDR_MAPB_09_08                                (WDR1_BASE + 0x01b8)
++#define    SEC_WDR_ADDR_MAPB_11_10                                (WDR1_BASE + 0x01bc)
++#define    SEC_WDR_ADDR_MAPB_13_12                                (WDR1_BASE + 0x01c0)
++#define    SEC_WDR_ADDR_MAPB_15_14                                (WDR1_BASE + 0x01c4)
++#define    SEC_WDR_ADDR_MAPB_17_16                                (WDR1_BASE + 0x01c8)
++#define    SEC_WDR_ADDR_MAPB_19_18                                (WDR1_BASE + 0x01cc)
++#define    SEC_WDR_ADDR_MAPB_21_20                                (WDR1_BASE + 0x01d0)
++#define    SEC_WDR_ADDR_MAPB_23_22                                (WDR1_BASE + 0x01d4)
++#define    SEC_WDR_ADDR_MAPB_25_24                                (WDR1_BASE + 0x01d8)
++#define    SEC_WDR_ADDR_MAPB_27_26                                (WDR1_BASE + 0x01dc)
++#define    SEC_WDR_ADDR_MAPB_29_28                                (WDR1_BASE + 0x01e0)
++#define    SEC_WDR_ADDR_MAPB_31_30                                (WDR1_BASE + 0x01e4)
++#define    SEC_WDR_ADDR_MAPB_33_32                                (WDR1_BASE + 0x01e8)
++#define    SEC_WDR_ADDR_MAPB_35_34                                (WDR1_BASE + 0x01ec)
++#define    SEC_WDR_ADDR_MAPB_37_36                                (WDR1_BASE + 0x01f0)
++#define    SEC_WDR_ADDR_MAPB_39_38                                (WDR1_BASE + 0x01f4)
++#define    SEC_WDR_ADDR_MAPB_41_40                                (WDR1_BASE + 0x01f8)
++#define    SEC_WDR_ADDR_MAPB_43_42                                (WDR1_BASE + 0x01fc)
++#define    SEC_WDR_ADDR_MAPB_45_44                                (WDR1_BASE + 0x0200)
++#define    SEC_WDR_ADDR_MAPB_47_46                                (WDR1_BASE + 0x0204)
++#define    SEC_WDR_ADDR_MAPB_49_48                                (WDR1_BASE + 0x0208)
++#define    SEC_WDR_ADDR_MAPB_51_50                                (WDR1_BASE + 0x020c)
++#define    SEC_WDR_ADDR_MAPB_53_52                                (WDR1_BASE + 0x0210)
++#define    SEC_WDR_ADDR_MAPB_55_54                                (WDR1_BASE + 0x0214)
++#define    SEC_WDR_ADDR_MAPB_57_56                                (WDR1_BASE + 0x0218)
++#define    SEC_WDR_ADDR_MAPB_59_58                                (WDR1_BASE + 0x021c)
++#define    SEC_WDR_ADDR_MAPB_61_60                                (WDR1_BASE + 0x0220)
++#define    SEC_WDR_ADDR_MAPB_63_62                                (WDR1_BASE + 0x0224)
++#define    SEC_WDR_ADDR_MAPB_65_64                                (WDR1_BASE + 0x0228)
++#define    SEC_WDR_ADDR_MAPB_67_66                                (WDR1_BASE + 0x022c)
++#define    SEC_WDR_ADDR_MAPB_69_68                                (WDR1_BASE + 0x0230)
++#define    SEC_WDR_ADDR_MAPB_71_70                                (WDR1_BASE + 0x0234)
++#define    SEC_WDR_ADDR_MAPB_73_72                                (WDR1_BASE + 0x0238)
++#define    SEC_WDR_ADDR_MAPB_75_74                                (WDR1_BASE + 0x023c)
++#define    SEC_WDR_ADDR_MAPB_77_76                                (WDR1_BASE + 0x0240)
++#define    SEC_WDR_ADDR_MAPB_79_78                                (WDR1_BASE + 0x0244)
++#define    SEC_WDR_ADDR_MAPB_80_80                                (WDR1_BASE + 0x0248)
++#define    SEC_WDR_ADDR_THRLABLE_01_00                            (WDR1_BASE + 0x024c)
++#define    SEC_WDR_ADDR_THRLABLE_03_02                            (WDR1_BASE + 0x0250)
++#define    SEC_WDR_ADDR_THRLABLE_05_04                            (WDR1_BASE + 0x0254)
++#define    SEC_WDR_ADDR_THRLABLE_07_06                            (WDR1_BASE + 0x0258)
++#define    SEC_WDR_ADDR_THRLABLE_09_08                            (WDR1_BASE + 0x025c)
++#define    SEC_WDR_ADDR_THRLABLE_11_10                            (WDR1_BASE + 0x0260)
++#define    SEC_WDR_ADDR_THRLABLE_13_12                            (WDR1_BASE + 0x0264)
++#define    SEC_WDR_ADDR_THRLABLE_15_14                            (WDR1_BASE + 0x0268)
++#define    SEC_WDR_ADDR_THRLABLE_17_16                            (WDR1_BASE + 0x026c)
++#define    SEC_WDR_ADDR_THRLABLE_19_18                            (WDR1_BASE + 0x0270)
++#define    SEC_WDR_ADDR_THRLABLE_21_20                            (WDR1_BASE + 0x0274)
++#define    SEC_WDR_ADDR_THRLABLE_23_22                            (WDR1_BASE + 0x0278)
++#define    SEC_WDR_ADDR_THRLABLE_25_24                            (WDR1_BASE + 0x027c)
++#define    SEC_WDR_ADDR_THRLABLE_26_26                            (WDR1_BASE + 0x0280)
++#define    SEC_WDR_ADDR_THRLABLEN_01_00                           (WDR1_BASE + 0x0284)
++#define    SEC_WDR_ADDR_THRLABLEN_03_02                           (WDR1_BASE + 0x0288)
++#define    SEC_WDR_ADDR_THRLABLEN_05_04                           (WDR1_BASE + 0x028c)
++#define    SEC_WDR_ADDR_THRLABLEN_07_06                           (WDR1_BASE + 0x0290)
++#define    SEC_WDR_ADDR_THRLABLEN_09_08                           (WDR1_BASE + 0x0294)
++#define    SEC_WDR_ADDR_THRLABLEN_11_10                           (WDR1_BASE + 0x0298)
++#define    SEC_WDR_ADDR_THRLABLEN_13_12                           (WDR1_BASE + 0x029c)
++#define    SEC_WDR_ADDR_THRLABLEN_15_14                           (WDR1_BASE + 0x02a0)
++#define    SEC_WDR_ADDR_THRLABLEN_17_16                           (WDR1_BASE + 0x02a4)
++#define    SEC_WDR_ADDR_THRLABLEN_19_18                           (WDR1_BASE + 0x02a8)
++#define    SEC_WDR_ADDR_THRLABLEN_21_20                           (WDR1_BASE + 0x02ac)
++#define    SEC_WDR_ADDR_THRLABLEN_23_22                           (WDR1_BASE + 0x02b0)
++#define    SEC_WDR_ADDR_THRLABLEN_25_24                           (WDR1_BASE + 0x02b4)
++#define    SEC_WDR_ADDR_THRALL_01_00                              (WDR1_BASE + 0x02b8)
++#define    SEC_WDR_ADDR_THRALL_03_02                              (WDR1_BASE + 0x02bc)
++#define    SEC_WDR_ADDR_THRALL_05_04                              (WDR1_BASE + 0x02c0)
++#define    SEC_WDR_ADDR_THRALL_07_06                              (WDR1_BASE + 0x02c4)
++#define    SEC_WDR_ADDR_THRALL_09_08                              (WDR1_BASE + 0x02c8)
++#define    SEC_WDR_ADDR_THRALL_11_10                              (WDR1_BASE + 0x02cc)
++#define    SEC_WDR_ADDR_THRALL_13_12                              (WDR1_BASE + 0x02d0)
++#define    SEC_WDR_ADDR_THRALL_15_14                              (WDR1_BASE + 0x02d4)
++#define    SEC_WDR_ADDR_THRALL_17_16                              (WDR1_BASE + 0x02d8)
++#define    SEC_WDR_ADDR_THRALL_19_18                              (WDR1_BASE + 0x02dc)
++#define    SEC_WDR_ADDR_THRALL_21_20                              (WDR1_BASE + 0x02e0)
++#define    SEC_WDR_ADDR_THRALL_23_22                              (WDR1_BASE + 0x02e4)
++#define    SEC_WDR_ADDR_THRALL_25_24                              (WDR1_BASE + 0x02e8)
++#define    SEC_WDR_ADDR_THRALL_26_26                              (WDR1_BASE + 0x02ec)
++#define    SEC_WDR_ADDR_THRRANGEK_00_00                           (WDR1_BASE + 0x02f0)
++#define    SEC_WDR_ADDR_THRRANGEK_01_01                           (WDR1_BASE + 0x02f4)
++#define    SEC_WDR_ADDR_THRRANGEK_02_02                           (WDR1_BASE + 0x02f8)
++#define    SEC_WDR_ADDR_THRRANGEK_03_03                           (WDR1_BASE + 0x02fc)
++#define    SEC_WDR_ADDR_THRRANGEK_04_04                           (WDR1_BASE + 0x0300)
++#define    SEC_WDR_ADDR_THRRANGEK_05_05                           (WDR1_BASE + 0x0304)
++#define    SEC_WDR_ADDR_THRRANGEK_06_06                           (WDR1_BASE + 0x0308)
++#define    SEC_WDR_ADDR_THRRANGEK_07_07                           (WDR1_BASE + 0x030c)
++#define    SEC_WDR_ADDR_THRRANGEK_08_08                           (WDR1_BASE + 0x0310)
++#define    SEC_WDR_ADDR_THRRANGEK_09_09                           (WDR1_BASE + 0x0314)
++#define    SEC_WDR_ADDR_THRRANGEK_10_10                           (WDR1_BASE + 0x0318)
++#define    SEC_WDR_ADDR_THRRANGEK_11_11                           (WDR1_BASE + 0x031c)
++#define    SEC_WDR_ADDR_THRRANGEK_12_12                           (WDR1_BASE + 0x0320)
++#define    SEC_WDR_ADDR_THRRANGEK_13_13                           (WDR1_BASE + 0x0324)
++#define    SEC_WDR_ADDR_THRRANGEK_14_14                           (WDR1_BASE + 0x0328)
++#define    SEC_WDR_ADDR_THRRANGEK_15_15                           (WDR1_BASE + 0x032c)
++#define    SEC_WDR_ADDR_THRRANGEK_16_16                           (WDR1_BASE + 0x0330)
++#define    SEC_WDR_ADDR_THRRANGEK_17_17                           (WDR1_BASE + 0x0334)
++#define    SEC_WDR_ADDR_THRRANGEK_18_18                           (WDR1_BASE + 0x0338)
++#define    SEC_WDR_ADDR_THRRANGEK_19_19                           (WDR1_BASE + 0x033c)
++#define    SEC_WDR_ADDR_THRRANGEK_20_20                           (WDR1_BASE + 0x0340)
++#define    SEC_WDR_ADDR_THRRANGEK_21_21                           (WDR1_BASE + 0x0344)
++#define    SEC_WDR_ADDR_THRRANGEK_22_22                           (WDR1_BASE + 0x0348)
++#define    SEC_WDR_ADDR_THRRANGEK_23_23                           (WDR1_BASE + 0x034c)
++#define    SEC_WDR_ADDR_THRRANGEK_24_24                           (WDR1_BASE + 0x0350)
++#define    SEC_WDR_ADDR_THRRANGEK_25_25                           (WDR1_BASE + 0x0354)
++#define    SEC_WDR_ADDR_THRRANGEK_26_26                           (WDR1_BASE + 0x0358)
++#define    SEC_WDR_ADDR_DARKLABLE_01_00                           (WDR1_BASE + 0x035c)
++#define    SEC_WDR_ADDR_DARKLABLE_03_02                           (WDR1_BASE + 0x0360)
++#define    SEC_WDR_ADDR_DARKLABLE_04_04                           (WDR1_BASE + 0x0364)
++#define    SEC_WDR_ADDR_DARKLABLEN_01_00                          (WDR1_BASE + 0x0368)
++#define    SEC_WDR_ADDR_DARKLABLEN_03_02                          (WDR1_BASE + 0x036c)
++#define    SEC_WDR_ADDR_DARKWEIGHT_01_00                          (WDR1_BASE + 0x0370)
++#define    SEC_WDR_ADDR_DARKWEIGHT_03_02                          (WDR1_BASE + 0x0374)
++#define    SEC_WDR_ADDR_DARKWEIGHT_04_04                          (WDR1_BASE + 0x0378)
++#define    SEC_WDR_ADDR_NOISEREDUCELABLE_00_00                    (WDR1_BASE + 0x037c)
++#define    SEC_WDR_ADDR_LABLE_ENRATE                              (WDR1_BASE + 0x0380)
++#define    SEC_WDR_ADDR_VALUE_ENRATE                              (WDR1_BASE + 0x0384)
++#define    SEC_WDR_ADDR_K_ENRATE1                                 (WDR1_BASE + 0x0388)
++#define    SEC_WDR_ADDR_K_ENRATE2                                 (WDR1_BASE + 0x038c)
++#define    SEC_WDR_ADDR_ENMAXMIN_V1                               (WDR1_BASE + 0x0390)
++#define    SEC_WDR_ADDR_RATIO_MINMAX_X                            (WDR1_BASE + 0x0394)
++#define    SEC_WDR_ADDR_K_RATIO_MINMAX_Y                          (WDR1_BASE + 0x039c)
++#define    SEC_WDR_ADDR_K_K_RATIO                                 (WDR1_BASE + 0x03a0)
++#define    SEC_WDR_ADDR_FUSIONTHRMINMAX_X                         (WDR1_BASE + 0x03a4)
++#define    SEC_WDR_ADDR_K_WEIGHT                                  (WDR1_BASE + 0x03a8)
++#define    SEC_WDR_ADDR_MAXVALUE                                  (WDR1_BASE + 0x03ac)
++#define    SEC_WDR_ADDR_TMP_MAXVALUE                              (WDR1_BASE + 0x03b0)
++#define    SEC_WDR_ADDR_THR_MAXVALUE_12BIT                        (WDR1_BASE + 0x03b4)
++#define    SEC_WDR_ADDR_TMP_FUSION_MAX                            (WDR1_BASE + 0x03b8)
++#define    SEC_WDR_ADDR_W_FUSION_X                                (WDR1_BASE + 0x03bc)
++#define    SEC_WDR_ADDR_K_W_FUSION0                               (WDR1_BASE + 0x03c0)
++#define    SEC_WDR_ADDR_LAMDA_01                                  (WDR1_BASE + 0x03c4)
++#define    SEC_WDR_ADDR_LAMDA_23                                  (WDR1_BASE + 0x03c8)
++#define    SEC_WDR_ADDR_LAMDA_4                                   (WDR1_BASE + 0x03cc)
++#define    SEC_WDR_ADDR_W_FUSION_X1                               (WDR1_BASE + 0x03d0)
++#define    SEC_WDR_ADDR_W_FUSION_X_N                              (WDR1_BASE + 0x03d4)
++#define    SEC_WDR_ADDR_CONSTRACT_MAXVALUE_LOG                    (WDR1_BASE + 0x03d8)
++#define    SEC_WDR_ADDR_TMP_MAXVALUE_LOG                          (WDR1_BASE + 0x03dc)
++#define    SEC_WDR_ADDR_LABLE_EN_01                               (WDR1_BASE + 0x03e0)
++#define    SEC_WDR_ADDR_LABLE_EN_2                                (WDR1_BASE + 0x03e4)
++#define    SEC_WDR_ADDR_VALUE_EN1                                 (WDR1_BASE + 0x03e8)
++#define    SEC_WDR_ADDR_LABLE_EN_Y_01                             (WDR1_BASE + 0x03ec)
++#define    SEC_WDR_ADDR_LABLE_EN_Y_2                              (WDR1_BASE + 0x03f0)
++#define    SEC_WDR_ADDR_K_EN1                                     (WDR1_BASE + 0x03f4)
++#define    SEC_WDR_ADDR_K_EN2                                     (WDR1_BASE + 0x03f8)
++#define    SEC_WDR_ADDR_TMP_EN1                                   (WDR1_BASE + 0x03fc)
++#define    SEC_WDR_ADDR_TMP_EN2                                   (WDR1_BASE + 0x0400)
++#define    SEC_WDR_ADDR_D_RATIO                                   (WDR1_BASE + 0x0404)
++#define    SEC_WDR_ADDR_LABLE_Y_SHORT                             (WDR1_BASE + 0x0408)
++#define    SEC_WDR_ADDR_LABLE_W                                   (WDR1_BASE + 0x040c)
++#define    SEC_WDR_ADDR_THR_DENOISE                               (WDR1_BASE + 0x0410)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_01_00                         (WDR1_BASE + 0x0420)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_03_02                         (WDR1_BASE + 0x0424)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_05_04                         (WDR1_BASE + 0x0428)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_07_06                         (WDR1_BASE + 0x042c)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_09_08                         (WDR1_BASE + 0x0430)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_11_10                         (WDR1_BASE + 0x0434)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_13_12                         (WDR1_BASE + 0x0438)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_15_14                         (WDR1_BASE + 0x043c)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_17_16                         (WDR1_BASE + 0x0440)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_19_18                         (WDR1_BASE + 0x0444)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_21_20                         (WDR1_BASE + 0x0448)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_23_22                         (WDR1_BASE + 0x044c)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_25_24                         (WDR1_BASE + 0x0450)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_27_26                         (WDR1_BASE + 0x0454)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_29_28                         (WDR1_BASE + 0x0458)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_31_30                         (WDR1_BASE + 0x045c)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_33_32                         (WDR1_BASE + 0x0460)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_35_34                         (WDR1_BASE + 0x0464)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_37_36                         (WDR1_BASE + 0x0468)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_39_38                         (WDR1_BASE + 0x046c)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_41_40                         (WDR1_BASE + 0x0470)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_43_42                         (WDR1_BASE + 0x0474)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_45_44                         (WDR1_BASE + 0x0478)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_47_46                         (WDR1_BASE + 0x047c)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_49_48                         (WDR1_BASE + 0x0480)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_51_50                         (WDR1_BASE + 0x0484)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_53_52                         (WDR1_BASE + 0x0488)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_55_54                         (WDR1_BASE + 0x048c)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_57_56                         (WDR1_BASE + 0x0490)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_59_58                         (WDR1_BASE + 0x0494)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_61_60                         (WDR1_BASE + 0x0498)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_63_62                         (WDR1_BASE + 0x049c)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_65_64                         (WDR1_BASE + 0x04a0)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_67_66                         (WDR1_BASE + 0x04a4)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_69_68                         (WDR1_BASE + 0x04a8)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_71_70                         (WDR1_BASE + 0x04ac)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_73_72                         (WDR1_BASE + 0x04b0)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_75_74                         (WDR1_BASE + 0x04b4)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_77_76                         (WDR1_BASE + 0x04b8)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_79_78                         (WDR1_BASE + 0x04bc)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_81_80                         (WDR1_BASE + 0x04c0)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_83_82                         (WDR1_BASE + 0x04c4)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_85_84                         (WDR1_BASE + 0x04c8)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_87_86                         (WDR1_BASE + 0x04cc)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_89_88                         (WDR1_BASE + 0x04d0)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_91_90                         (WDR1_BASE + 0x04d4)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_93_92                         (WDR1_BASE + 0x04d8)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_95_94                         (WDR1_BASE + 0x04dc)
++#define    SEC_WDR_ADDR_VALUE_GAMMA_96_96                         (WDR1_BASE + 0x04e0)
++#define    SEC_WDR_ADDR_VALUE_ZIP_01_00                           (WDR1_BASE + 0x04e4)
++#define    SEC_WDR_ADDR_VALUE_ZIP_03_02                           (WDR1_BASE + 0x04e8)
++#define    SEC_WDR_ADDR_VALUE_ZIP_05_04                           (WDR1_BASE + 0x04ec)
++#define    SEC_WDR_ADDR_VALUE_ZIP_07_06                           (WDR1_BASE + 0x04f0)
++#define    SEC_WDR_ADDR_VALUE_ZIP_09_08                           (WDR1_BASE + 0x04f4)
++#define    SEC_WDR_ADDR_VALUE_ZIP_11_10                           (WDR1_BASE + 0x04f8)
++#define    SEC_WDR_ADDR_VALUE_ZIP_13_12                           (WDR1_BASE + 0x04fc)
++#define    SEC_WDR_ADDR_VALUE_ZIP_15_14                           (WDR1_BASE + 0x0500)
++#define    SEC_WDR_ADDR_VALUE_ZIP_17_16                           (WDR1_BASE + 0x0504)
++#define    SEC_WDR_ADDR_VALUE_ZIP_19_18                           (WDR1_BASE + 0x0508)
++#define    SEC_WDR_ADDR_VALUE_ZIP_21_20                           (WDR1_BASE + 0x050c)
++#define    SEC_WDR_ADDR_VALUE_ZIP_23_22                           (WDR1_BASE + 0x0510)
++#define    SEC_WDR_ADDR_VALUE_ZIP_25_24                           (WDR1_BASE + 0x0514)
++#define    SEC_WDR_ADDR_VALUE_ZIP_27_26                           (WDR1_BASE + 0x0518)
++#define    SEC_WDR_ADDR_VALUE_ZIP_29_28                           (WDR1_BASE + 0x051c)
++#define    SEC_WDR_ADDR_VALUE_ZIP_31_30                           (WDR1_BASE + 0x0520)
++#define    SEC_WDR_ADDR_VALUE_ZIP_33_32                           (WDR1_BASE + 0x0524)
++#define    SEC_WDR_ADDR_VALUE_ZIP_35_34                           (WDR1_BASE + 0x0528)
++#define    SEC_WDR_ADDR_VALUE_ZIP_37_36                           (WDR1_BASE + 0x052c)
++#define    SEC_WDR_ADDR_VALUE_ZIP_39_38                           (WDR1_BASE + 0x0530)
++#define    SEC_WDR_ADDR_VALUE_ZIP_41_40                           (WDR1_BASE + 0x0534)
++#define    SEC_WDR_ADDR_VALUE_ZIP_43_42                           (WDR1_BASE + 0x0538)
++#define    SEC_WDR_ADDR_VALUE_ZIP_45_44                           (WDR1_BASE + 0x053c)
++#define    SEC_WDR_ADDR_VALUE_ZIP_47_46                           (WDR1_BASE + 0x0540)
++#define    SEC_WDR_ADDR_VALUE_ZIP_49_48                           (WDR1_BASE + 0x0544)
++#define    SEC_WDR_ADDR_VALUE_ZIP_51_50                           (WDR1_BASE + 0x0548)
++#define    SEC_WDR_ADDR_VALUE_ZIP_53_52                           (WDR1_BASE + 0x054c)
++#define    SEC_WDR_ADDR_VALUE_ZIP_55_54                           (WDR1_BASE + 0x0550)
++#define    SEC_WDR_ADDR_VALUE_ZIP_57_56                           (WDR1_BASE + 0x0554)
++#define    SEC_WDR_ADDR_VALUE_ZIP_59_58                           (WDR1_BASE + 0x0558)
++#define    SEC_WDR_ADDR_VALUE_ZIP_61_60                           (WDR1_BASE + 0x055c)
++#define    SEC_WDR_ADDR_VALUE_ZIP_63_62                           (WDR1_BASE + 0x0560)
++#define    SEC_WDR_ADDR_VALUE_ZIP_65_64                           (WDR1_BASE + 0x0564)
++#define    SEC_WDR_ADDR_VALUE_ZIP_67_66                           (WDR1_BASE + 0x0568)
++#define    SEC_WDR_ADDR_VALUE_ZIP_69_68                           (WDR1_BASE + 0x056c)
++#define    SEC_WDR_ADDR_VALUE_ZIP_71_70                           (WDR1_BASE + 0x0570)
++#define    SEC_WDR_ADDR_VALUE_ZIP_73_72                           (WDR1_BASE + 0x0574)
++#define    SEC_WDR_ADDR_VALUE_ZIP_75_74                           (WDR1_BASE + 0x0578)
++#define    SEC_WDR_ADDR_VALUE_ZIP_77_76                           (WDR1_BASE + 0x057c)
++#define    SEC_WDR_ADDR_VALUE_ZIP_79_78                           (WDR1_BASE + 0x0580)
++#define    SEC_WDR_ADDR_VALUE_ZIP_81_80                           (WDR1_BASE + 0x0584)
++#define    SEC_WDR_ADDR_VALUE_ZIP_83_82                           (WDR1_BASE + 0x0588)
++#define    SEC_WDR_ADDR_VALUE_ZIP_85_84                           (WDR1_BASE + 0x058c)
++#define    SEC_WDR_ADDR_VALUE_ZIP_87_86                           (WDR1_BASE + 0x0590)
++#define    SEC_WDR_ADDR_VALUE_ZIP_89_88                           (WDR1_BASE + 0x0594)
++#define    SEC_WDR_ADDR_VALUE_ZIP_91_90                           (WDR1_BASE + 0x0598)
++#define    SEC_WDR_ADDR_VALUE_ZIP_93_92                           (WDR1_BASE + 0x059c)
++#define    SEC_WDR_ADDR_VALUE_ZIP_95_94                           (WDR1_BASE + 0x05a0)
++#define    SEC_WDR_ADDR_VALUE_ZIP_97_96                           (WDR1_BASE + 0x05a4)
++#define    SEC_WDR_ADDR_VALUE_ZIP_98_98                           (WDR1_BASE + 0x05a8)
++#define    SEC_WDR_ADDR_VALUE_FUSION_01_00                        (WDR1_BASE + 0x05ac)
++#define    SEC_WDR_ADDR_VALUE_FUSION_03_02                        (WDR1_BASE + 0x05b0)
++#define    SEC_WDR_ADDR_VALUE_FUSION_05_04                        (WDR1_BASE + 0x05b4)
++#define    SEC_WDR_ADDR_VALUE_FUSION_07_06                        (WDR1_BASE + 0x05b8)
++#define    SEC_WDR_ADDR_VALUE_FUSION_09_08                        (WDR1_BASE + 0x05bc)
++#define    SEC_WDR_ADDR_VALUE_FUSION_11_10                        (WDR1_BASE + 0x05c0)
++#define    SEC_WDR_ADDR_VALUE_FUSION_13_12                        (WDR1_BASE + 0x05c4)
++#define    SEC_WDR_ADDR_VALUE_FUSION_15_14                        (WDR1_BASE + 0x05c8)
++#define    SEC_WDR_ADDR_VALUE_FUSION_17_16                        (WDR1_BASE + 0x05cc)
++#define    SEC_WDR_ADDR_VALUE_FUSION_19_18                        (WDR1_BASE + 0x05d0)
++#define    SEC_WDR_ADDR_VALUE_FUSION_21_20                        (WDR1_BASE + 0x05d4)
++#define    SEC_WDR_ADDR_VALUE_FUSION_23_22                        (WDR1_BASE + 0x05d8)
++#define    SEC_WDR_ADDR_VALUE_FUSION_25_24                        (WDR1_BASE + 0x05dc)
++#define    SEC_WDR_ADDR_VALUE_FUSION_27_26                        (WDR1_BASE + 0x05e0)
++#define    SEC_WDR_ADDR_VALUE_FUSION_29_28                        (WDR1_BASE + 0x05e4)
++#define    SEC_WDR_ADDR_VALUE_FUSION_31_30                        (WDR1_BASE + 0x05e8)
++#define    SEC_WDR_ADDR_VALUE_FUSION_32_32                        (WDR1_BASE + 0x05ec)
++#define    SEC_WDR_ADDR_VALUE_W_LINE_01_00                        (WDR1_BASE + 0x05f0)
++#define    SEC_WDR_ADDR_VALUE_W_LINE_03_02                        (WDR1_BASE + 0x05f4)
++#define    SEC_WDR_ADDR_VALUE_W_LINE_04_04                        (WDR1_BASE + 0x05f8)
++#define    SEC_WDR_ADDR_FUSIONTHRMAX_Y                            (WDR1_BASE + 0x05fc)
++#define    SEC_WDR_ADDR_D_WH                                      (WDR1_BASE + 0x0600)
++#define    SEC_WDR_ADDR_STAT_EN                                   (WDR1_BASE + 0x0604)
++#define    SEC_WDR_ADDR_STA_INFO_ADDR0                            (WDR1_BASE + 0x0610)
++#define    SEC_WDR_ADDR_STA_INFO_CNT0                             (WDR1_BASE + 0x0614)
++#define    SEC_WDR_ADDR_STA_INFO_ADDR1                            (WDR1_BASE + 0x0618)
++#define    SEC_WDR_ADDR_STA_INFO_CNT1                             (WDR1_BASE + 0x061c)
++#define    SEC_WDR_ADDR_DBG_00_00                                 (WDR1_BASE + 0x0680)
++#define    SEC_WDR_ADDR_DBG_01_01                                 (WDR1_BASE + 0x0684)
++#define    SEC_WDR_ADDR_DBG_02_02                                 (WDR1_BASE + 0x0688)
++#define    SEC_WDR_ADDR_DBG_03_03                                 (WDR1_BASE + 0x068c)
++#define    SEC_WDR_ADDR_DBG_04_04                                 (WDR1_BASE + 0x0690)
++#define    SEC_WDR_ADDR_DBG_05_05                                 (WDR1_BASE + 0x0694)
++#define    SEC_WDR_ADDR_DBG_06_06                                 (WDR1_BASE + 0x0698)
++#define    SEC_WDR_ADDR_DBG_07_07                                 (WDR1_BASE + 0x069c)
++
++//============================================================
++// DPC ADDRESS
++//============================================================
++#define DPC_ADDR_S_CON(n)           (DPC_BASE(n) + 0x0000)
++#define DPC_ADDR_ALPHA(n)           (DPC_BASE(n) + 0x0004)
++#define DPC_ADDR_LV_EN(n)           (DPC_BASE(n) + 0x0008)
++#define DPC_ADDR_LV2_POS_EN(n)           (DPC_BASE(n) + 0x000c)
++#define DPC_ADDR_SC_WEI(n)           (DPC_BASE(n) + 0x0010)
++#define DPC_ADDR_SLOPE_1(n)           (DPC_BASE(n) + 0x0014)
++#define DPC_ADDR_SLOPE_2(n)           (DPC_BASE(n) + 0x0018)
++#define DPC_ADDR_LV1_THRES_RB(n)           (DPC_BASE(n) + 0x001c)
++#define DPC_ADDR_LV2_DIFF_THRES_RB(n)           (DPC_BASE(n) + 0x0020)
++#define DPC_ADDR_LV2_POS_THRES_RB_1(n)           (DPC_BASE(n) + 0x0024)
++#define DPC_ADDR_LV2_POS_THRES_RB_2(n)           (DPC_BASE(n) + 0x0028)
++#define DPC_ADDR_LV2_POS_DIST_THRES_RB_1(n)           (DPC_BASE(n) + 0x002c)
++#define DPC_ADDR_LV2_POS_DIST_THRES_RB_2(n)           (DPC_BASE(n) + 0x0030)
++#define DPC_ADDR_LV3_THRES_RB(n)           (DPC_BASE(n) + 0x0034)
++#define DPC_ADDR_LV1_THRES_G(n)           (DPC_BASE(n) + 0x0038)
++#define DPC_ADDR_LV2_DIFF_THRES_G(n)           (DPC_BASE(n) + 0x003c)
++#define DPC_ADDR_LV2_POS_THRES_G_1(n)           (DPC_BASE(n) + 0x0040)
++#define DPC_ADDR_LV2_POS_THRES_G_2(n)           (DPC_BASE(n) + 0x0044)
++#define DPC_ADDR_LV2_POS_DIST_THRES_G_1(n)           (DPC_BASE(n) + 0x0048)
++#define DPC_ADDR_LV2_POS_DIST_THRES_G_2(n)           (DPC_BASE(n) + 0x004c)
++#define DPC_ADDR_LV3_THRES_G(n)           (DPC_BASE(n) + 0x0050)
++#define DPC_ADDR_CTR_CON(n)           (DPC_BASE(n) + 0x0054)
++#define DPC_ADDR_CTR_MD_CON(n)           (DPC_BASE(n) + 0x0058)
++#define DPC_ADDR_CTR_STD_CON(n)           (DPC_BASE(n) + 0x005c)
++#define DPC_ADDR_CTR_BASE_THRES(n)           (DPC_BASE(n) + 0x0060)
++#define DPC_ADDR_CTR_MD_NP_1(n)           (DPC_BASE(n) + 0x0064)
++#define DPC_ADDR_CTR_MD_NP_2(n)           (DPC_BASE(n) + 0x0068)
++#define DPC_ADDR_CTR_MD_NP_3(n)           (DPC_BASE(n) + 0x006c)
++#define DPC_ADDR_CTR_MD_NP_4(n)           (DPC_BASE(n) + 0x0070)
++#define DPC_ADDR_CTR_STD_NP_1(n)           (DPC_BASE(n) + 0x0074)
++#define DPC_ADDR_CTR_STD_NP_2(n)           (DPC_BASE(n) + 0x0078)
++#define DPC_ADDR_CTR_STD_NP_3(n)           (DPC_BASE(n) + 0x007c)
++#define DPC_ADDR_CTR_STD_NP_4(n)           (DPC_BASE(n) + 0x0080)
++#define DPC_ADDR_STILL_STD_THRES(n)           (DPC_BASE(n) + 0x0084)
++#define DPC_ADDR_DBG_0(n)           (DPC_BASE(n) + 0x0088)
++#define DPC_ADDR_DBG_1(n)           (DPC_BASE(n) + 0x008c)
++#define DPC_ADDR_DBG_2(n)           (DPC_BASE(n) + 0x0090)
++#define DPC_ADDR_DBG_3(n)           (DPC_BASE(n) + 0x0094)
++#define DPC_ADDR_DBG_4(n)           (DPC_BASE(n) + 0x0098)
++#define DPC_ADDR_SHD_CTRL(n)           (DPC_BASE(n) + 0x009c)
++#define DPC_ADDR_DNS_STD_THRES(n)           (DPC_BASE(n) + 0x00a0)
++
++//============================================================
++// GIB ADDRESS
++//============================================================
++#define GIB_ADDR_GIB_GAIN_0(n)            (GIB_BASE(n) + 0x0000)
++#define GIB_ADDR_GIB_GAIN_1(n)            (GIB_BASE(n) + 0x0004)
++#define GIB_ADDR_GIB_OVEXP_THRES(n)            (GIB_BASE(n) + 0x0008)
++#define GIB_ADDR_GIB_EN(n)            (GIB_BASE(n) + 0x000c)
++#define GIB_ADDR_GIB_DEIRM_R_0(n)            (GIB_BASE(n) + 0x0010)
++#define GIB_ADDR_GIB_DEIRM_R_1(n)            (GIB_BASE(n) + 0x0014)
++#define GIB_ADDR_GIB_DEIRM_G_0(n)            (GIB_BASE(n) + 0x0018)
++#define GIB_ADDR_GIB_DEIRM_G_1(n)            (GIB_BASE(n) + 0x001c)
++#define GIB_ADDR_GIB_DEIRM_B_0(n)            (GIB_BASE(n) + 0x0020)
++#define GIB_ADDR_GIB_DEIRM_B_1(n)            (GIB_BASE(n) + 0x0024)
++#define GIB_ADDR_GIB_DEIRM_C_0(n)            (GIB_BASE(n) + 0x0028)
++#define GIB_ADDR_GIB_DEIRM_C_1(n)            (GIB_BASE(n) + 0x002c)
++#define GIB_ADDR_GIB_BLC_CH(n)            (GIB_BASE(n) + 0x0030)
++#define GIB_ADDR_GIB_BLC_CH_0(n)            (GIB_BASE(n) + 0x0034)
++#define GIB_ADDR_GIB_BLC_CH_1(n)            (GIB_BASE(n) + 0x0038)
++#define GIB_ADDR_GIB_BLC_CH_2(n)            (GIB_BASE(n) + 0x003c)
++#define GIB_ADDR_SHD_CTRL(n)            (GIB_BASE(n) + 0x0040)
++#define GIB_ADDR_DEBUG0(n)            (GIB_BASE(n) + 0x0044)
++#define GIB_ADDR_DEBUG1(n)            (GIB_BASE(n) + 0x0048)
++#define GIB_ADDR_DEBUG2(n)            (GIB_BASE(n) + 0x004c)
++#define GIB_ADDR_DEBUG3(n)            (GIB_BASE(n) + 0x0050)
++#define GIB_ADDR_DEBUG4(n)            (GIB_BASE(n) + 0x0054)
++#define GIB_ADDR_DEBUG5(n)            (GIB_BASE(n) + 0x0058)
++
++//============================================================
++// AWBG1 ADDRESS
++//============================================================
++#define    MAIN_AWBG1_ADDR_SHD_CTRL                                  (AWBG10_BASE + 0x0000)
++#define    MAIN_AWBG1_ADDR_R_G_GAIN_L                                (AWBG10_BASE + 0x0004)
++#define    MAIN_AWBG1_ADDR_B_IR_GAIN_L                               (AWBG10_BASE + 0x0008)
++#define    MAIN_AWBG1_ADDR_R_G_GAIN_S                                (AWBG10_BASE + 0x000c)
++#define    MAIN_AWBG1_ADDR_B_IR_GAIN_S                               (AWBG10_BASE + 0x0010)
++#define    MAIN_AWBG1_ADDR_DEBUG1                                    (AWBG10_BASE + 0x0014)
++#define    MAIN_AWBG1_ADDR_DEBUG2                                    (AWBG10_BASE + 0x0018)
++
++#define    SEC_AWBG1_ADDR_SHD_CTRL                                   (AWBG11_BASE + 0x0000)
++#define    SEC_AWBG1_ADDR_R_G_GAIN_L                                 (AWBG11_BASE + 0x0004)
++#define    SEC_AWBG1_ADDR_B_IR_GAIN_L                                (AWBG11_BASE + 0x0008)
++#define    SEC_AWBG1_ADDR_R_G_GAIN_S                                 (AWBG11_BASE + 0x000c)
++#define    SEC_AWBG1_ADDR_B_IR_GAIN_S                                (AWBG11_BASE + 0x0010)
++#define    SEC_AWBG1_ADDR_DEBUG1                                     (AWBG11_BASE + 0x0014)
++#define    SEC_AWBG1_ADDR_DEBUG2                                     (AWBG11_BASE + 0x0018)
++
++//============================================================
++// ADR ADDRESS
++//============================================================
++#define    MAIN_ADR_ADDR_MODE                                        (ADR0_BASE + 0x0000)
++#define    MAIN_ADR_ADDR_EXT_PRIO                                    (ADR0_BASE + 0x0004)
++
++#define    ADR_ADDR_MODULES_EN(n)                                  (ADR_BASE(n) + 0x0008)
++#define    ADR_ADDR_ADR_COC_IN_TH(n)                               (ADR_BASE(n) + 0x0010)
++#define    ADR_ADDR_ADR_COC_GAM_DIV(n)                             (ADR_BASE(n) + 0x0014)
++#define    ADR_ADDR_COC_W_DEFAULT(n)                               (ADR_BASE(n) + 0x0018)
++#define    ADR_ADDR_IR_LIMIT(n)                                    (ADR_BASE(n) + 0x001c)
++#define    ADR_ADDR_LEAST_BWC_MODE_EN(n)                           (ADR_BASE(n) + 0x0020)
++#define    ADR_ADDR_BWC_TH(n)                                      (ADR_BASE(n) + 0x0024)
++#define    ADR_ADDR_ADR_COC_W_EN(n)                                (ADR_BASE(n) + 0x0028)
++#define    ADR_ADDR_ADR_BLOCK_COORD_M_01_00(n)                     (ADR_BASE(n) + 0x0030)
++#define    ADR_ADDR_ADR_BLOCK_COORD_M_03_02(n)                     (ADR_BASE(n) + 0x0034)
++#define    ADR_ADDR_ADR_BLOCK_COORD_M_04_04(n)                     (ADR_BASE(n) + 0x0038)
++#define    ADR_ADDR_ADR_BLOCK_COORD_N_01_00(n)                     (ADR_BASE(n) + 0x003c)
++#define    ADR_ADDR_ADR_BLOCK_COORD_N_03_02(n)                     (ADR_BASE(n) + 0x0040)
++#define    ADR_ADDR_ADR_BLOCK_COORD_N_05_04(n)                     (ADR_BASE(n) + 0x0044)
++#define    ADR_ADDR_ADR_BLOCK_COORD_N_06_06(n)                     (ADR_BASE(n) + 0x0048)
++#define    ADR_ADDR_ADR_WEIGHTLUT20__03_00(n)                      (ADR_BASE(n) + 0x004c)
++#define    ADR_ADDR_ADR_WEIGHTLUT20__07_04(n)                      (ADR_BASE(n) + 0x0050)
++#define    ADR_ADDR_ADR_WEIGHTLUT20__11_08(n)                      (ADR_BASE(n) + 0x0054)
++#define    ADR_ADDR_ADR_WEIGHTLUT20__15_12(n)                      (ADR_BASE(n) + 0x0058)
++#define    ADR_ADDR_ADR_WEIGHTLUT20__19_16(n)                      (ADR_BASE(n) + 0x005c)
++#define    ADR_ADDR_ADR_WEIGHTLUT20__23_20(n)                      (ADR_BASE(n) + 0x0060)
++#define    ADR_ADDR_ADR_WEIGHTLUT20__27_24(n)                      (ADR_BASE(n) + 0x0064)
++#define    ADR_ADDR_ADR_WEIGHTLUT20__31_28(n)                      (ADR_BASE(n) + 0x0068)
++#define    ADR_ADDR_ADR_WEIGHTLUT02__03_00(n)                      (ADR_BASE(n) + 0x006c)
++#define    ADR_ADDR_ADR_WEIGHTLUT02__07_04(n)                      (ADR_BASE(n) + 0x0070)
++#define    ADR_ADDR_ADR_WEIGHTLUT02__11_08(n)                      (ADR_BASE(n) + 0x0074)
++#define    ADR_ADDR_ADR_WEIGHTLUT02__15_12(n)                      (ADR_BASE(n) + 0x0078)
++#define    ADR_ADDR_ADR_WEIGHTLUT02__19_16(n)                      (ADR_BASE(n) + 0x007c)
++#define    ADR_ADDR_ADR_WEIGHTLUT02__23_20(n)                      (ADR_BASE(n) + 0x0080)
++#define    ADR_ADDR_ADR_WEIGHTLUT02__27_24(n)                      (ADR_BASE(n) + 0x0084)
++#define    ADR_ADDR_ADR_WEIGHTLUT02__31_28(n)                      (ADR_BASE(n) + 0x0088)
++#define    ADR_ADDR_ADR_WEIGHTLUT12__03_00(n)                      (ADR_BASE(n) + 0x008c)
++#define    ADR_ADDR_ADR_WEIGHTLUT12__07_04(n)                      (ADR_BASE(n) + 0x0090)
++#define    ADR_ADDR_ADR_WEIGHTLUT12__11_08(n)                      (ADR_BASE(n) + 0x0094)
++#define    ADR_ADDR_ADR_WEIGHTLUT12__15_12(n)                      (ADR_BASE(n) + 0x0098)
++#define    ADR_ADDR_ADR_WEIGHTLUT12__19_16(n)                      (ADR_BASE(n) + 0x009c)
++#define    ADR_ADDR_ADR_WEIGHTLUT12__23_20(n)                      (ADR_BASE(n) + 0x00a0)
++#define    ADR_ADDR_ADR_WEIGHTLUT12__27_24(n)                      (ADR_BASE(n) + 0x00a4)
++#define    ADR_ADDR_ADR_WEIGHTLUT12__31_28(n)                      (ADR_BASE(n) + 0x00a8)
++#define    ADR_ADDR_ADR_WEIGHTLUT22__03_00(n)                      (ADR_BASE(n) + 0x00ac)
++#define    ADR_ADDR_ADR_WEIGHTLUT22__07_04(n)                      (ADR_BASE(n) + 0x00b0)
++#define    ADR_ADDR_ADR_WEIGHTLUT22__11_08(n)                      (ADR_BASE(n) + 0x00b4)
++#define    ADR_ADDR_ADR_WEIGHTLUT22__15_12(n)                      (ADR_BASE(n) + 0x00b8)
++#define    ADR_ADDR_ADR_WEIGHTLUT22__19_16(n)                      (ADR_BASE(n) + 0x00bc)
++#define    ADR_ADDR_ADR_WEIGHTLUT22__23_20(n)                      (ADR_BASE(n) + 0x00c0)
++#define    ADR_ADDR_ADR_WEIGHTLUT22__27_24(n)                      (ADR_BASE(n) + 0x00c4)
++#define    ADR_ADDR_ADR_WEIGHTLUT22__31_28(n)                      (ADR_BASE(n) + 0x00c8)
++#define    ADR_ADDR_ADR_WEIGHTLUT21__03_00(n)                      (ADR_BASE(n) + 0x00cc)
++#define    ADR_ADDR_ADR_WEIGHTLUT21__07_04(n)                      (ADR_BASE(n) + 0x00d0)
++#define    ADR_ADDR_ADR_WEIGHTLUT21__11_08(n)                      (ADR_BASE(n) + 0x00d4)
++#define    ADR_ADDR_ADR_WEIGHTLUT21__15_12(n)                      (ADR_BASE(n) + 0x00d8)
++#define    ADR_ADDR_ADR_WEIGHTLUT21__19_16(n)                      (ADR_BASE(n) + 0x00dc)
++#define    ADR_ADDR_ADR_WEIGHTLUT21__23_20(n)                      (ADR_BASE(n) + 0x00e0)
++#define    ADR_ADDR_ADR_WEIGHTLUT21__27_24(n)                      (ADR_BASE(n) + 0x00e4)
++#define    ADR_ADDR_ADR_WEIGHTLUT21__31_28(n)                      (ADR_BASE(n) + 0x00e8)
++#define    ADR_ADDR_CTC_KNEEPOINT_Y__01_00(n)                      (ADR_BASE(n) + 0x00ec)
++#define    ADR_ADDR_CTC_KNEEPOINT_Y__03_02(n)                      (ADR_BASE(n) + 0x00f0)
++#define    ADR_ADDR_CTC_KNEEPOINT_Y__05_04(n)                      (ADR_BASE(n) + 0x00f4)
++#define    ADR_ADDR_CTC_KNEEPOINT_Y__07_06(n)                      (ADR_BASE(n) + 0x00f8)
++#define    ADR_ADDR_CTC_KNEEPOINT_Y__09_08(n)                      (ADR_BASE(n) + 0x00fc)
++#define    ADR_ADDR_CTC_KNEEPOINT_Y__11_10(n)                      (ADR_BASE(n) + 0x0100)
++#define    ADR_ADDR_CTC_KNEEPOINT_Y__13_12(n)                      (ADR_BASE(n) + 0x0104)
++#define    ADR_ADDR_CTC_KNEEPOINT_Y__15_14(n)                      (ADR_BASE(n) + 0x0108)
++#define    ADR_ADDR_ADR_CTC1_Y__01_00(n)                           (ADR_BASE(n) + 0x010c)
++#define    ADR_ADDR_ADR_CTC1_Y__03_02(n)                           (ADR_BASE(n) + 0x0110)
++#define    ADR_ADDR_ADR_CTC1_Y__05_04(n)                           (ADR_BASE(n) + 0x0114)
++#define    ADR_ADDR_ADR_CTC1_Y__07_06(n)                           (ADR_BASE(n) + 0x0118)
++#define    ADR_ADDR_ADR_CTC1_Y__09_08(n)                           (ADR_BASE(n) + 0x011c)
++#define    ADR_ADDR_ADR_CTC1_Y__11_10(n)                           (ADR_BASE(n) + 0x0120)
++#define    ADR_ADDR_ADR_CTC1_Y__13_12(n)                           (ADR_BASE(n) + 0x0124)
++#define    ADR_ADDR_ADR_CTC1_Y__15_14(n)                           (ADR_BASE(n) + 0x0128)
++#define    ADR_ADDR_ADR_CTC1_Y__17_16(n)                           (ADR_BASE(n) + 0x012c)
++#define    ADR_ADDR_ADR_CTC1_Y__19_18(n)                           (ADR_BASE(n) + 0x0130)
++#define    ADR_ADDR_ADR_CTC1_Y__20_20(n)                           (ADR_BASE(n) + 0x0134)
++#define    ADR_ADDR_MIN_KNEEPOINT_Y__01_00(n)                      (ADR_BASE(n) + 0x0138)
++#define    ADR_ADDR_MIN_KNEEPOINT_Y__03_02(n)                      (ADR_BASE(n) + 0x013c)
++#define    ADR_ADDR_MIN_KNEEPOINT_Y__05_04(n)                      (ADR_BASE(n) + 0x0140)
++#define    ADR_ADDR_MIN_KNEEPOINT_Y__07_06(n)                      (ADR_BASE(n) + 0x0144)
++#define    ADR_ADDR_MIN_KNEEPOINT_Y__09_08(n)                      (ADR_BASE(n) + 0x0148)
++#define    ADR_ADDR_MIN_KNEEPOINT_Y__11_10(n)                      (ADR_BASE(n) + 0x014c)
++#define    ADR_ADDR_MIN_KNEEPOINT_Y__13_12(n)                      (ADR_BASE(n) + 0x0150)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_00__01_00(n)                   (ADR_BASE(n) + 0x0154)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_00__03_02(n)                   (ADR_BASE(n) + 0x0158)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_00__05_04(n)                   (ADR_BASE(n) + 0x015c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_00__07_06(n)                   (ADR_BASE(n) + 0x0160)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_00__09_08(n)                   (ADR_BASE(n) + 0x0164)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_00__11_10(n)                   (ADR_BASE(n) + 0x0168)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_00__13_12(n)                   (ADR_BASE(n) + 0x016c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_01__01_00(n)                   (ADR_BASE(n) + 0x0170)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_01__03_02(n)                   (ADR_BASE(n) + 0x0174)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_01__05_04(n)                   (ADR_BASE(n) + 0x0178)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_01__07_06(n)                   (ADR_BASE(n) + 0x017c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_01__09_08(n)                   (ADR_BASE(n) + 0x0180)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_01__11_10(n)                   (ADR_BASE(n) + 0x0184)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_01__13_12(n)                   (ADR_BASE(n) + 0x0188)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_02__01_00(n)                   (ADR_BASE(n) + 0x018c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_02__03_02(n)                   (ADR_BASE(n) + 0x0190)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_02__05_04(n)                   (ADR_BASE(n) + 0x0194)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_02__07_06(n)                   (ADR_BASE(n) + 0x0198)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_02__09_08(n)                   (ADR_BASE(n) + 0x019c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_02__11_10(n)                   (ADR_BASE(n) + 0x01a0)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_02__13_12(n)                   (ADR_BASE(n) + 0x01a4)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_03__01_00(n)                   (ADR_BASE(n) + 0x01a8)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_03__03_02(n)                   (ADR_BASE(n) + 0x01ac)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_03__05_04(n)                   (ADR_BASE(n) + 0x01b0)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_03__07_06(n)                   (ADR_BASE(n) + 0x01b4)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_03__09_08(n)                   (ADR_BASE(n) + 0x01b8)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_03__11_10(n)                   (ADR_BASE(n) + 0x01bc)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_03__13_12(n)                   (ADR_BASE(n) + 0x01c0)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_04__01_00(n)                   (ADR_BASE(n) + 0x01c4)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_04__03_02(n)                   (ADR_BASE(n) + 0x01c8)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_04__05_04(n)                   (ADR_BASE(n) + 0x01cc)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_04__07_06(n)                   (ADR_BASE(n) + 0x01d0)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_04__09_08(n)                   (ADR_BASE(n) + 0x01d4)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_04__11_10(n)                   (ADR_BASE(n) + 0x01d8)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_04__13_12(n)                   (ADR_BASE(n) + 0x01dc)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_05__01_00(n)                   (ADR_BASE(n) + 0x01e0)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_05__03_02(n)                   (ADR_BASE(n) + 0x01e4)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_05__05_04(n)                   (ADR_BASE(n) + 0x01e8)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_05__07_06(n)                   (ADR_BASE(n) + 0x01ec)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_05__09_08(n)                   (ADR_BASE(n) + 0x01f0)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_05__11_10(n)                   (ADR_BASE(n) + 0x01f4)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_05__13_12(n)                   (ADR_BASE(n) + 0x01f8)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_06__01_00(n)                   (ADR_BASE(n) + 0x01fc)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_06__03_02(n)                   (ADR_BASE(n) + 0x0200)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_06__05_04(n)                   (ADR_BASE(n) + 0x0204)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_06__07_06(n)                   (ADR_BASE(n) + 0x0208)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_06__09_08(n)                   (ADR_BASE(n) + 0x020c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_06__11_10(n)                   (ADR_BASE(n) + 0x0210)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_06__13_12(n)                   (ADR_BASE(n) + 0x0214)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_07__01_00(n)                   (ADR_BASE(n) + 0x0218)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_07__03_02(n)                   (ADR_BASE(n) + 0x021c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_07__05_04(n)                   (ADR_BASE(n) + 0x0220)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_07__07_06(n)                   (ADR_BASE(n) + 0x0224)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_07__09_08(n)                   (ADR_BASE(n) + 0x0228)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_07__11_10(n)                   (ADR_BASE(n) + 0x022c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_07__13_12(n)                   (ADR_BASE(n) + 0x0230)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_08__01_00(n)                   (ADR_BASE(n) + 0x0234)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_08__03_02(n)                   (ADR_BASE(n) + 0x0238)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_08__05_04(n)                   (ADR_BASE(n) + 0x023c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_08__07_06(n)                   (ADR_BASE(n) + 0x0240)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_08__09_08(n)                   (ADR_BASE(n) + 0x0244)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_08__11_10(n)                   (ADR_BASE(n) + 0x0248)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_08__13_12(n)                   (ADR_BASE(n) + 0x024c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_09__01_00(n)                   (ADR_BASE(n) + 0x0250)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_09__03_02(n)                   (ADR_BASE(n) + 0x0254)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_09__05_04(n)                   (ADR_BASE(n) + 0x0258)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_09__07_06(n)                   (ADR_BASE(n) + 0x025c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_09__09_08(n)                   (ADR_BASE(n) + 0x0260)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_09__11_10(n)                   (ADR_BASE(n) + 0x0264)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_09__13_12(n)                   (ADR_BASE(n) + 0x0268)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_10__01_00(n)                   (ADR_BASE(n) + 0x026c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_10__03_02(n)                   (ADR_BASE(n) + 0x0270)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_10__05_04(n)                   (ADR_BASE(n) + 0x0274)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_10__07_06(n)                   (ADR_BASE(n) + 0x0278)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_10__09_08(n)                   (ADR_BASE(n) + 0x027c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_10__11_10(n)                   (ADR_BASE(n) + 0x0280)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_10__13_12(n)                   (ADR_BASE(n) + 0x0284)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_11__01_00(n)                   (ADR_BASE(n) + 0x0288)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_11__03_02(n)                   (ADR_BASE(n) + 0x028c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_11__05_04(n)                   (ADR_BASE(n) + 0x0290)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_11__07_06(n)                   (ADR_BASE(n) + 0x0294)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_11__09_08(n)                   (ADR_BASE(n) + 0x0298)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_11__11_10(n)                   (ADR_BASE(n) + 0x029c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_11__13_12(n)                   (ADR_BASE(n) + 0x02a0)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_12__01_00(n)                   (ADR_BASE(n) + 0x02a4)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_12__03_02(n)                   (ADR_BASE(n) + 0x02a8)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_12__05_04(n)                   (ADR_BASE(n) + 0x02ac)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_12__07_06(n)                   (ADR_BASE(n) + 0x02b0)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_12__09_08(n)                   (ADR_BASE(n) + 0x02b4)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_12__11_10(n)                   (ADR_BASE(n) + 0x02b8)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_12__13_12(n)                   (ADR_BASE(n) + 0x02bc)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_13__01_00(n)                   (ADR_BASE(n) + 0x02c0)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_13__03_02(n)                   (ADR_BASE(n) + 0x02c4)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_13__05_04(n)                   (ADR_BASE(n) + 0x02c8)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_13__07_06(n)                   (ADR_BASE(n) + 0x02cc)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_13__09_08(n)                   (ADR_BASE(n) + 0x02d0)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_13__11_10(n)                   (ADR_BASE(n) + 0x02d4)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_13__13_12(n)                   (ADR_BASE(n) + 0x02d8)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_14__01_00(n)                   (ADR_BASE(n) + 0x02dc)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_14__03_02(n)                   (ADR_BASE(n) + 0x02e0)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_14__05_04(n)                   (ADR_BASE(n) + 0x02e4)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_14__07_06(n)                   (ADR_BASE(n) + 0x02e8)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_14__09_08(n)                   (ADR_BASE(n) + 0x02ec)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_14__11_10(n)                   (ADR_BASE(n) + 0x02f0)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_14__13_12(n)                   (ADR_BASE(n) + 0x02f4)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_15__01_00(n)                   (ADR_BASE(n) + 0x02f8)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_15__03_02(n)                   (ADR_BASE(n) + 0x02fc)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_15__05_04(n)                   (ADR_BASE(n) + 0x0300)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_15__07_06(n)                   (ADR_BASE(n) + 0x0304)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_15__09_08(n)                   (ADR_BASE(n) + 0x0308)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_15__11_10(n)                   (ADR_BASE(n) + 0x030c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_15__13_12(n)                   (ADR_BASE(n) + 0x0310)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_16__01_00(n)                   (ADR_BASE(n) + 0x0314)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_16__03_02(n)                   (ADR_BASE(n) + 0x0318)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_16__05_04(n)                   (ADR_BASE(n) + 0x031c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_16__07_06(n)                   (ADR_BASE(n) + 0x0320)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_16__09_08(n)                   (ADR_BASE(n) + 0x0324)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_16__11_10(n)                   (ADR_BASE(n) + 0x0328)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_16__13_12(n)                   (ADR_BASE(n) + 0x032c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_17__01_00(n)                   (ADR_BASE(n) + 0x0330)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_17__03_02(n)                   (ADR_BASE(n) + 0x0334)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_17__05_04(n)                   (ADR_BASE(n) + 0x0338)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_17__07_06(n)                   (ADR_BASE(n) + 0x033c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_17__09_08(n)                   (ADR_BASE(n) + 0x0340)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_17__11_10(n)                   (ADR_BASE(n) + 0x0344)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_17__13_12(n)                   (ADR_BASE(n) + 0x0348)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_18__01_00(n)                   (ADR_BASE(n) + 0x034c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_18__03_02(n)                   (ADR_BASE(n) + 0x0350)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_18__05_04(n)                   (ADR_BASE(n) + 0x0354)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_18__07_06(n)                   (ADR_BASE(n) + 0x0358)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_18__09_08(n)                   (ADR_BASE(n) + 0x035c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_18__11_10(n)                   (ADR_BASE(n) + 0x0360)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_18__13_12(n)                   (ADR_BASE(n) + 0x0364)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_19__01_00(n)                   (ADR_BASE(n) + 0x0368)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_19__03_02(n)                   (ADR_BASE(n) + 0x036c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_19__05_04(n)                   (ADR_BASE(n) + 0x0370)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_19__07_06(n)                   (ADR_BASE(n) + 0x0374)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_19__09_08(n)                   (ADR_BASE(n) + 0x0378)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_19__11_10(n)                   (ADR_BASE(n) + 0x037c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_19__13_12(n)                   (ADR_BASE(n) + 0x0380)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_20__01_00(n)                   (ADR_BASE(n) + 0x0384)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_20__03_02(n)                   (ADR_BASE(n) + 0x0388)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_20__05_04(n)                   (ADR_BASE(n) + 0x038c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_20__07_06(n)                   (ADR_BASE(n) + 0x0390)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_20__09_08(n)                   (ADR_BASE(n) + 0x0394)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_20__11_10(n)                   (ADR_BASE(n) + 0x0398)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_20__13_12(n)                   (ADR_BASE(n) + 0x039c)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_21__01_00(n)                   (ADR_BASE(n) + 0x03a0)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_21__03_02(n)                   (ADR_BASE(n) + 0x03a4)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_21__05_04(n)                   (ADR_BASE(n) + 0x03a8)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_21__07_06(n)                   (ADR_BASE(n) + 0x03ac)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_21__09_08(n)                   (ADR_BASE(n) + 0x03b0)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_21__11_10(n)                   (ADR_BASE(n) + 0x03b4)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_21__13_12(n)                   (ADR_BASE(n) + 0x03b8)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_22__01_00(n)                   (ADR_BASE(n) + 0x03bc)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_22__03_02(n)                   (ADR_BASE(n) + 0x03c0)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_22__05_04(n)                   (ADR_BASE(n) + 0x03c4)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_22__07_06(n)                   (ADR_BASE(n) + 0x03c8)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_22__09_08(n)                   (ADR_BASE(n) + 0x03cc)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_22__11_10(n)                   (ADR_BASE(n) + 0x03d0)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_22__13_12(n)                   (ADR_BASE(n) + 0x03d4)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_23__01_00(n)                   (ADR_BASE(n) + 0x03d8)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_23__03_02(n)                   (ADR_BASE(n) + 0x03dc)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_23__05_04(n)                   (ADR_BASE(n) + 0x03e0)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_23__07_06(n)                   (ADR_BASE(n) + 0x03e4)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_23__09_08(n)                   (ADR_BASE(n) + 0x03e8)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_23__11_10(n)                   (ADR_BASE(n) + 0x03ec)
++#define    ADR_ADDR_MAP_KNEEPOINT_Y_23__13_12(n)                   (ADR_BASE(n) + 0x03f0)
++#define    ADR_ADDR_COC_KNEEPOINT_Y1__01_00(n)                     (ADR_BASE(n) + 0x03f4)
++#define    ADR_ADDR_COC_KNEEPOINT_Y1__03_02(n)                     (ADR_BASE(n) + 0x03f8)
++#define    ADR_ADDR_COC_KNEEPOINT_Y1__05_04(n)                     (ADR_BASE(n) + 0x03fc)
++#define    ADR_ADDR_COC_KNEEPOINT_Y1__07_06(n)                     (ADR_BASE(n) + 0x0400)
++#define    ADR_ADDR_COC_KNEEPOINT_Y1__09_08(n)                     (ADR_BASE(n) + 0x0404)
++#define    ADR_ADDR_COC_KNEEPOINT_Y1__11_10(n)                     (ADR_BASE(n) + 0x0408)
++#define    ADR_ADDR_COC_KNEEPOINT_Y2__01_00(n)                     (ADR_BASE(n) + 0x040c)
++#define    ADR_ADDR_COC_KNEEPOINT_Y2__03_02(n)                     (ADR_BASE(n) + 0x0410)
++#define    ADR_ADDR_COC_KNEEPOINT_Y2__05_04(n)                     (ADR_BASE(n) + 0x0414)
++#define    ADR_ADDR_COC_KNEEPOINT_Y2__07_06(n)                     (ADR_BASE(n) + 0x0418)
++#define    ADR_ADDR_COC_KNEEPOINT_Y2__09_08(n)                     (ADR_BASE(n) + 0x041c)
++#define    ADR_ADDR_COC_KNEEPOINT_Y2__11_10(n)                     (ADR_BASE(n) + 0x0420)
++#define    ADR_ADDR_COC_KNEEPOINT_Y3__01_00(n)                     (ADR_BASE(n) + 0x0424)
++#define    ADR_ADDR_COC_KNEEPOINT_Y3__03_02(n)                     (ADR_BASE(n) + 0x0428)
++#define    ADR_ADDR_COC_KNEEPOINT_Y3__05_04(n)                     (ADR_BASE(n) + 0x042c)
++#define    ADR_ADDR_COC_KNEEPOINT_Y3__07_06(n)                     (ADR_BASE(n) + 0x0430)
++#define    ADR_ADDR_COC_KNEEPOINT_Y3__09_08(n)                     (ADR_BASE(n) + 0x0434)
++#define    ADR_ADDR_COC_KNEEPOINT_Y3__11_10(n)                     (ADR_BASE(n) + 0x0438)
++#define    ADR_ADDR_COC_KNEEPOINT_Y4__01_00(n)                     (ADR_BASE(n) + 0x043c)
++#define    ADR_ADDR_COC_KNEEPOINT_Y4__03_02(n)                     (ADR_BASE(n) + 0x0440)
++#define    ADR_ADDR_COC_KNEEPOINT_Y4__05_04(n)                     (ADR_BASE(n) + 0x0444)
++#define    ADR_ADDR_COC_KNEEPOINT_Y4__07_06(n)                     (ADR_BASE(n) + 0x0448)
++#define    ADR_ADDR_COC_KNEEPOINT_Y4__09_08(n)                     (ADR_BASE(n) + 0x044c)
++#define    ADR_ADDR_COC_KNEEPOINT_Y4__11_10(n)                     (ADR_BASE(n) + 0x0450)
++#define    ADR_ADDR_COC_KNEEPOINT_Y5__01_00(n)                     (ADR_BASE(n) + 0x0454)
++#define    ADR_ADDR_COC_KNEEPOINT_Y5__03_02(n)                     (ADR_BASE(n) + 0x0458)
++#define    ADR_ADDR_COC_KNEEPOINT_Y5__05_04(n)                     (ADR_BASE(n) + 0x045c)
++#define    ADR_ADDR_COC_KNEEPOINT_Y5__07_06(n)                     (ADR_BASE(n) + 0x0460)
++#define    ADR_ADDR_COC_KNEEPOINT_Y5__09_08(n)                     (ADR_BASE(n) + 0x0464)
++#define    ADR_ADDR_COC_KNEEPOINT_Y5__11_10(n)                     (ADR_BASE(n) + 0x0468)
++#define    ADR_ADDR_ADR_COC_GAM1_Y__01_00(n)                       (ADR_BASE(n) + 0x046c)
++#define    ADR_ADDR_ADR_COC_GAM1_Y__03_02(n)                       (ADR_BASE(n) + 0x0470)
++#define    ADR_ADDR_ADR_COC_GAM1_Y__04_04(n)                       (ADR_BASE(n) + 0x0474)
++#define    ADR_ADDR_ADR_COC_GAM2_Y__01_00(n)                       (ADR_BASE(n) + 0x0478)
++#define    ADR_ADDR_ADR_COC_GAM2_Y__03_02(n)                       (ADR_BASE(n) + 0x047c)
++#define    ADR_ADDR_ADR_COC_GAM2_Y__05_04(n)                       (ADR_BASE(n) + 0x0480)
++#define    ADR_ADDR_ADR_COC_GAM2_Y__07_06(n)                       (ADR_BASE(n) + 0x0484)
++#define    ADR_ADDR_ADR_COC_GAM2_Y__09_08(n)                       (ADR_BASE(n) + 0x0488)
++#define    ADR_ADDR_ADR_COC_GAM2_Y__11_10(n)                       (ADR_BASE(n) + 0x048c)
++#define    ADR_ADDR_ADR_COC_GAM2_Y__13_12(n)                       (ADR_BASE(n) + 0x0490)
++#define    ADR_ADDR_ADR_COC_GAM2_Y__15_14(n)                       (ADR_BASE(n) + 0x0494)
++#define    ADR_ADDR_ADR_COC_GAM2_Y__17_16(n)                       (ADR_BASE(n) + 0x0498)
++#define    ADR_ADDR_CENTRE_W_DISTANCE__01_00(n)                    (ADR_BASE(n) + 0x049c)
++#define    ADR_ADDR_CENTRE_W_DISTANCE__03_02(n)                    (ADR_BASE(n) + 0x04a0)
++#define    ADR_ADDR_CENTRE_W_DISTANCE__05_04(n)                    (ADR_BASE(n) + 0x04a4)
++#define    ADR_ADDR_CENTRE_W_DISTANCE__07_06(n)                    (ADR_BASE(n) + 0x04a8)
++#define    ADR_ADDR_CENTRE_W_DISTANCE__09_08(n)                    (ADR_BASE(n) + 0x04ac)
++#define    ADR_ADDR_CENTRE_W_DISTANCE__11_10(n)                    (ADR_BASE(n) + 0x04b0)
++#define    ADR_ADDR_CENTRE_W_DISTANCE__13_12(n)                    (ADR_BASE(n) + 0x04b4)
++#define    ADR_ADDR_CENTRE_W_DISTANCE__15_14(n)                    (ADR_BASE(n) + 0x04b8)
++#define    ADR_ADDR_CENTRE_W_DISTANCE__17_16(n)                    (ADR_BASE(n) + 0x04bc)
++#define    ADR_ADDR_CENTRE_W_DISTANCE__19_18(n)                    (ADR_BASE(n) + 0x04c0)
++#define    ADR_ADDR_CENTRE_W_DISTANCE__21_20(n)                    (ADR_BASE(n) + 0x04c4)
++#define    ADR_ADDR_CENTRE_W_DISTANCE__23_22(n)                    (ADR_BASE(n) + 0x04c8)
++#define    ADR_ADDR_CENTRE_W_DISTANCE__25_24(n)                    (ADR_BASE(n) + 0x04cc)
++#define    ADR_ADDR_CENTRE_W_DISTANCE__27_26(n)                    (ADR_BASE(n) + 0x04d0)
++#define    ADR_ADDR_CENTRE_W_DISTANCE__29_28(n)                    (ADR_BASE(n) + 0x04d4)
++#define    ADR_ADDR_CENTRE_W_DISTANCE__30_30(n)                    (ADR_BASE(n) + 0x04d8)
++#define    ADR_ADDR_ADR_COC_GAM_01_00(n)                           (ADR_BASE(n) + 0x04dc)
++#define    ADR_ADDR_ADR_COC_GAM_03_02(n)                           (ADR_BASE(n) + 0x04e0)
++#define    ADR_ADDR_ADR_COC_GAM_04_04(n)                           (ADR_BASE(n) + 0x04e4)
++#define    ADR_ADDR_ADR_COC_W_X_01_00(n)                           (ADR_BASE(n) + 0x04e8)
++#define    ADR_ADDR_ADR_COC_W_X_03_02(n)                           (ADR_BASE(n) + 0x04ec)
++#define    ADR_ADDR_ADR_COC_W_Y_01_00(n)                           (ADR_BASE(n) + 0x04f0)
++#define    ADR_ADDR_ADR_COC_W_Y_03_02(n)                           (ADR_BASE(n) + 0x04f4)
++#define    ADR_ADDR_ADR_COC_W_POW_01_00(n)                         (ADR_BASE(n) + 0x04f8)
++#define    ADR_ADDR_ADR_COC_W_POW_02_02(n)                         (ADR_BASE(n) + 0x04fc)
++
++#define    MAIN_ADR_ADDR_STAT_FRAME_RATE                             (ADR0_BASE + 0x0500)
++#define    MAIN_ADR_ADDR_BANK_BUFFER_NUMBER                          (ADR0_BASE + 0x0510)
++#define    MAIN_ADR_ADDR_BANK00_ADDR                                 (ADR0_BASE + 0x0514)
++#define    MAIN_ADR_ADDR_BANK01_ADDR                                 (ADR0_BASE + 0x0518)
++#define    MAIN_ADR_ADDR_BANK02_ADDR                                 (ADR0_BASE + 0x051c)
++#define    MAIN_ADR_ADDR_BANK03_ADDR                                 (ADR0_BASE + 0x0520)
++#define    MAIN_ADR_ADDR_FRAME_ADDR0                                 (ADR0_BASE + 0x0540)
++#define    MAIN_ADR_ADDR_FRAME_ID0                                   (ADR0_BASE + 0x0544)
++#define    MAIN_ADR_ADDR_FRAME_ADDR1                                 (ADR0_BASE + 0x0548)
++#define    MAIN_ADR_ADDR_FRAME_ID1                                   (ADR0_BASE + 0x054c)
++#define    MAIN_ADR_ADDR_DBG_0                                       (ADR0_BASE + 0x0580)
++#define    MAIN_ADR_ADDR_DBG_1                                       (ADR0_BASE + 0x0584)
++#define    MAIN_ADR_ADDR_DBG_2                                       (ADR0_BASE + 0x0588)
++#define    MAIN_ADR_ADDR_DBG_3                                       (ADR0_BASE + 0x058c)
++#define    MAIN_ADR_ADDR_DBG_4                                       (ADR0_BASE + 0x0590)
++#define    MAIN_ADR_ADDR_DBG_5                                       (ADR0_BASE + 0x0594)
++#define    MAIN_ADR_ADDR_DBG_6                                       (ADR0_BASE + 0x0598)
++#define    MAIN_ADR_ADDR_DBG_7                                       (ADR0_BASE + 0x059c)
++#define    MAIN_ADR_ADDR_DBG_8                                       (ADR0_BASE + 0x05a0)
++
++#define    SEC_ADR_ADDR_MODE                                         (ADR1_BASE + 0x0000)
++#define    SEC_ADR_ADDR_EXT_PRIO                                     (ADR1_BASE + 0x0004)
++
++#define    SEC_ADR_ADDR_STAT_FRAME_RATE                              (ADR1_BASE + 0x0500)
++#define    SEC_ADR_ADDR_BANK_BUFFER_NUMBER                           (ADR1_BASE + 0x0510)
++#define    SEC_ADR_ADDR_BANK00_ADDR                                  (ADR1_BASE + 0x0514)
++#define    SEC_ADR_ADDR_BANK01_ADDR                                  (ADR1_BASE + 0x0518)
++#define    SEC_ADR_ADDR_BANK02_ADDR                                  (ADR1_BASE + 0x051c)
++#define    SEC_ADR_ADDR_BANK03_ADDR                                  (ADR1_BASE + 0x0520)
++#define    SEC_ADR_ADDR_FRAME_ADDR0                                  (ADR1_BASE + 0x0540)
++#define    SEC_ADR_ADDR_FRAME_ID0                                    (ADR1_BASE + 0x0544)
++#define    SEC_ADR_ADDR_FRAME_ADDR1                                  (ADR1_BASE + 0x0548)
++#define    SEC_ADR_ADDR_FRAME_ID1                                    (ADR1_BASE + 0x054c)
++#define    SEC_ADR_ADDR_DBG_0                                        (ADR1_BASE + 0x0580)
++#define    SEC_ADR_ADDR_DBG_1                                        (ADR1_BASE + 0x0584)
++#define    SEC_ADR_ADDR_DBG_2                                        (ADR1_BASE + 0x0588)
++#define    SEC_ADR_ADDR_DBG_3                                        (ADR1_BASE + 0x058c)
++#define    SEC_ADR_ADDR_DBG_4                                        (ADR1_BASE + 0x0590)
++#define    SEC_ADR_ADDR_DBG_5                                        (ADR1_BASE + 0x0594)
++#define    SEC_ADR_ADDR_DBG_6                                        (ADR1_BASE + 0x0598)
++#define    SEC_ADR_ADDR_DBG_7                                        (ADR1_BASE + 0x059c)
++#define    SEC_ADR_ADDR_DBG_8                                        (ADR1_BASE + 0x05a0)
++
++//============================================================
++// DMSC ADDRESS
++//============================================================
++#define    DEMOSAIC_ADDR_OUT_OPT(n)             (DEMOSAIC_BASE(n) + 0x0000)
++#define    DEMOSAIC_ADDR_G_STD_STREN(n)             (DEMOSAIC_BASE(n) + 0x0004)
++#define    DEMOSAIC_ADDR_UU_THRES(n)             (DEMOSAIC_BASE(n) + 0x0008)
++#define    DEMOSAIC_ADDR_ALIAS_DIR_DIFF(n)             (DEMOSAIC_BASE(n) + 0x000c)
++#define    DEMOSAIC_ADDR_WIN5_HV_EDGE_THRES(n)             (DEMOSAIC_BASE(n) + 0x0010)
++#define    DEMOSAIC_ADDR_HV_EDGE_THRES(n)             (DEMOSAIC_BASE(n) + 0x0014)
++#define    DEMOSAIC_ADDR_HV_EDGE(n)             (DEMOSAIC_BASE(n) + 0x0020)
++#define    DEMOSAIC_ADDR_AA_EDGE_THRES(n)             (DEMOSAIC_BASE(n) + 0x0024)
++#define    DEMOSAIC_ADDR_AA_EDGE(n)             (DEMOSAIC_BASE(n) + 0x0028)
++#define    DEMOSAIC_ADDR_HVAA_EDGE_THRES(n)             (DEMOSAIC_BASE(n) + 0x002c)
++#define    DEMOSAIC_ADDR_HVAA_EDGE(n)             (DEMOSAIC_BASE(n) + 0x0030)
++#define    DEMOSAIC_ADDR_ALIAS_STREN(n)             (DEMOSAIC_BASE(n) + 0x0034)
++#define    DEMOSAIC_ADDR_ALIAS_THRES(n)             (DEMOSAIC_BASE(n) + 0x0038)
++#define    DEMOSAIC_ADDR_NOR_ALIAS_BLUR(n)             (DEMOSAIC_BASE(n) + 0x003c)
++#define    DEMOSAIC_ADDR_NOR_UU_WEI_STREN(n)             (DEMOSAIC_BASE(n) + 0x0040)
++#define    DEMOSAIC_ADDR_SP_D_V2_SIGMA(n)             (DEMOSAIC_BASE(n) + 0x0044)
++#define    DEMOSAIC_ADDR_SP_D_W_SP_STREN(n)             (DEMOSAIC_BASE(n) + 0x0048)
++#define    DEMOSAIC_ADDR_SP_D_LL_STREN(n)             (DEMOSAIC_BASE(n) + 0x004c)
++#define    DEMOSAIC_ADDR_SP_D_THRES(n)             (DEMOSAIC_BASE(n) + 0x0050)
++#define    DEMOSAIC_ADDR_SP_D_W_LIMIT(n)             (DEMOSAIC_BASE(n) + 0x0054)
++#define    DEMOSAIC_ADDR_SP_D_B_LIMIT(n)             (DEMOSAIC_BASE(n) + 0x0058)
++#define    DEMOSAIC_ADDR_SP_UD_V2_SIGMA(n)             (DEMOSAIC_BASE(n) + 0x005c)
++#define    DEMOSAIC_ADDR_SP_UD_W_SP_STREN(n)             (DEMOSAIC_BASE(n) + 0x0060)
++#define    DEMOSAIC_ADDR_SP_UD_LL_STREN(n)             (DEMOSAIC_BASE(n) + 0x0064)
++#define    DEMOSAIC_ADDR_SP_UD_LL_THRES(n)             (DEMOSAIC_BASE(n) + 0x0068)
++#define    DEMOSAIC_ADDR_SP_UD_W_LIMIT(n)             (DEMOSAIC_BASE(n) + 0x006c)
++#define    DEMOSAIC_ADDR_SP_UD_B_LIMIT(n)             (DEMOSAIC_BASE(n) + 0x0070)
++#define    DEMOSAIC_ADDR_SP_NOR_ALIAS_THRES(n)             (DEMOSAIC_BASE(n) + 0x0074)
++#define    DEMOSAIC_ADDR_ALIAS_FUSION_THRES(n)             (DEMOSAIC_BASE(n) + 0x0078)
++#define    DEMOSAIC_ADDR_ALIAS_DIR_INTP_SP_STREN(n)             (DEMOSAIC_BASE(n) + 0x007c)
++#define    DEMOSAIC_ADDR_FC_ALIAS_STREN(n)             (DEMOSAIC_BASE(n) + 0x0080)
++#define    DEMOSAIC_ADDR_FC_ALIAS_THRES(n)             (DEMOSAIC_BASE(n) + 0x0084)
++#define    DEMOSAIC_ADDR_FC_NOR_SAT_THRES(n)             (DEMOSAIC_BASE(n) + 0x0088)
++#define    DEMOSAIC_ADDR_FC_TEXT_THRES(n)             (DEMOSAIC_BASE(n) + 0x008c)
++#define    DEMOSAIC_ADDR_FC_NOR_EDGE_SLOPE(n)             (DEMOSAIC_BASE(n) + 0x0090)
++#define    DEMOSAIC_ADDR_FC_THRES_H_1(n)             (DEMOSAIC_BASE(n) + 0x009c)
++#define    DEMOSAIC_ADDR_SP_D_V2_WIN5_THRES(n)             (DEMOSAIC_BASE(n) + 0x00a4)
++#define    DEMOSAIC_ADDR_SP_D_OE_EN(n)             (DEMOSAIC_BASE(n) + 0x00ac)
++#define    DEMOSAIC_ADDR_SP_UD_V1_SEL_OPT(n)             (DEMOSAIC_BASE(n) + 0x00b0)
++#define    DEMOSAIC_ADDR_SP_UD_V2_SEL_OPT(n)             (DEMOSAIC_BASE(n) + 0x00b4)
++#define    DEMOSAIC_ADDR_SP_UD_STD_THRES(n)             (DEMOSAIC_BASE(n) + 0x00b8)
++#define    DEMOSAIC_ADDR_SP_UD_OE_EN(n)             (DEMOSAIC_BASE(n) + 0x00c4)
++#define    DEMOSAIC_ADDR_UU_NP_REG0(n)             (DEMOSAIC_BASE(n) + 0x00c8)
++#define    DEMOSAIC_ADDR_UU_NP_REG1(n)             (DEMOSAIC_BASE(n) + 0x00cc)
++#define    DEMOSAIC_ADDR_UU_NP_REG2(n)             (DEMOSAIC_BASE(n) + 0x00d0)
++#define    DEMOSAIC_ADDR_UU_NP_REG3(n)             (DEMOSAIC_BASE(n) + 0x00d4)
++#define    DEMOSAIC_ADDR_UU_NP_REG4(n)             (DEMOSAIC_BASE(n) + 0x00d8)
++#define    DEMOSAIC_ADDR_UU_NP_REG5(n)             (DEMOSAIC_BASE(n) + 0x00dc)
++#define    DEMOSAIC_ADDR_UU_NP_REG6(n)             (DEMOSAIC_BASE(n) + 0x00e0)
++#define    DEMOSAIC_ADDR_UU_NP_REG7(n)             (DEMOSAIC_BASE(n) + 0x00e4)
++#define    DEMOSAIC_ADDR_SP_D_W_WEI_NP_REG0(n)             (DEMOSAIC_BASE(n) + 0x00f4)
++#define    DEMOSAIC_ADDR_SP_D_W_WEI_NP_REG1(n)             (DEMOSAIC_BASE(n) + 0x00f8)
++#define    DEMOSAIC_ADDR_SP_D_W_WEI_NP_REG2(n)             (DEMOSAIC_BASE(n) + 0x00fc)
++#define    DEMOSAIC_ADDR_SP_D_W_WEI_NP_REG3(n)             (DEMOSAIC_BASE(n) + 0x0100)
++#define    DEMOSAIC_ADDR_SP_D_W_WEI_NP_REG4(n)             (DEMOSAIC_BASE(n) + 0x0104)
++#define    DEMOSAIC_ADDR_SP_D_W_WEI_NP_REG5(n)             (DEMOSAIC_BASE(n) + 0x0108)
++#define    DEMOSAIC_ADDR_SP_D_W_WEI_NP_REG6(n)             (DEMOSAIC_BASE(n) + 0x010c)
++#define    DEMOSAIC_ADDR_SP_UD_W_WEI_NP_REG0(n)             (DEMOSAIC_BASE(n) + 0x011c)
++#define    DEMOSAIC_ADDR_SP_UD_W_WEI_NP_REG1(n)             (DEMOSAIC_BASE(n) + 0x0120)
++#define    DEMOSAIC_ADDR_SP_UD_W_WEI_NP_REG2(n)             (DEMOSAIC_BASE(n) + 0x0124)
++#define    DEMOSAIC_ADDR_SP_UD_W_WEI_NP_REG3(n)             (DEMOSAIC_BASE(n) + 0x0128)
++#define    DEMOSAIC_ADDR_SP_UD_W_WEI_NP_REG4(n)             (DEMOSAIC_BASE(n) + 0x012c)
++#define    DEMOSAIC_ADDR_SP_UD_W_WEI_NP_REG5(n)             (DEMOSAIC_BASE(n) + 0x0130)
++#define    DEMOSAIC_ADDR_SP_UD_W_WEI_NP_REG6(n)             (DEMOSAIC_BASE(n) + 0x0134)
++#define    DEMOSAIC_ADDR_DEIR_EN(n)             (DEMOSAIC_BASE(n) + 0x0144)
++#define    DEMOSAIC_ADDR_DEIR_RGB_OE(n)             (DEMOSAIC_BASE(n) + 0x0148)
++#define    DEMOSAIC_ADDR_DEIR_IR_OE(n)             (DEMOSAIC_BASE(n) + 0x014c)
++#define    DEMOSAIC_ADDR_R_DEIR_NP_REG0(n)             (DEMOSAIC_BASE(n) + 0x0150)
++#define    DEMOSAIC_ADDR_R_DEIR_NP_REG1(n)             (DEMOSAIC_BASE(n) + 0x0154)
++#define    DEMOSAIC_ADDR_R_DEIR_NP_REG2(n)             (DEMOSAIC_BASE(n) + 0x0158)
++#define    DEMOSAIC_ADDR_R_DEIR_NP_REG3(n)             (DEMOSAIC_BASE(n) + 0x015c)
++#define    DEMOSAIC_ADDR_G_DEIR_NP_REG0(n)             (DEMOSAIC_BASE(n) + 0x0160)
++#define    DEMOSAIC_ADDR_G_DEIR_NP_REG1(n)             (DEMOSAIC_BASE(n) + 0x0164)
++#define    DEMOSAIC_ADDR_G_DEIR_NP_REG2(n)             (DEMOSAIC_BASE(n) + 0x0168)
++#define    DEMOSAIC_ADDR_G_DEIR_NP_REG3(n)             (DEMOSAIC_BASE(n) + 0x016c)
++#define    DEMOSAIC_ADDR_B_DEIR_NP_REG0(n)             (DEMOSAIC_BASE(n) + 0x0170)
++#define    DEMOSAIC_ADDR_B_DEIR_NP_REG1(n)             (DEMOSAIC_BASE(n) + 0x0174)
++#define    DEMOSAIC_ADDR_B_DEIR_NP_REG2(n)             (DEMOSAIC_BASE(n) + 0x0178)
++#define    DEMOSAIC_ADDR_B_DEIR_NP_REG3(n)             (DEMOSAIC_BASE(n) + 0x017c)
++#define    DEMOSAIC_ADDR_FC_LUM_THRES(n)             (DEMOSAIC_BASE(n) + 0x0180)
++#define    DEMOSAIC_ADDR_AWB_GAIN(n)             (DEMOSAIC_BASE(n) + 0x0184)
++#define    DEMOSAIC_ADDR_DEIR_FUSION_THRES(n)             (DEMOSAIC_BASE(n) + 0x0188)
++#define    DEMOSAIC_ADDR_DEBUG_0(n)             (DEMOSAIC_BASE(n) + 0x018c)
++#define    DEMOSAIC_ADDR_DEBUG_1(n)             (DEMOSAIC_BASE(n) + 0x0190)
++#define    DEMOSAIC_ADDR_DEBUG_2(n)             (DEMOSAIC_BASE(n) + 0x0194)
++#define    DEMOSAIC_ADDR_DEBUG_3(n)             (DEMOSAIC_BASE(n) + 0x0198)
++#define    DEMOSAIC_ADDR_SHD_CTRL(n)             (DEMOSAIC_BASE(n) + 0x019c)
++#define    DEMOSAIC_ADDR_FC_H_SAT_THRES(n)             (DEMOSAIC_BASE(n) + 0x01a8)
++#define    DEMOSAIC_ADDR_SP_FLAT_THRES(n)             (DEMOSAIC_BASE(n) + 0x01ac)
++#define    DEMOSAIC_ADDR_SP_FLAT_SLOPE(n)             (DEMOSAIC_BASE(n) + 0x01b0)
++#define    DEMOSAIC_ADDR_SP_FLAT_STREN(n)             (DEMOSAIC_BASE(n) + 0x01b4)
++#define    DEMOSAIC_ADDR_SP_D_DIR_THRES(n)             (DEMOSAIC_BASE(n) + 0x01b8)
++#define    DEMOSAIC_ADDR_H_SP_P1_VALUE(n)             (DEMOSAIC_BASE(n) + 0x01bc)
++#define    DEMOSAIC_ADDR_H_SP_P1_THRES(n)             (DEMOSAIC_BASE(n) + 0x01c0)
++#define    DEMOSAIC_ADDR_H_SP_P1_S_LOW_HIGH(n)             (DEMOSAIC_BASE(n) + 0x01c4)
++#define    DEMOSAIC_ADDR_H_SP_P2_VALUE(n)             (DEMOSAIC_BASE(n) + 0x01c8)
++#define    DEMOSAIC_ADDR_H_SP_P2_THRES(n)             (DEMOSAIC_BASE(n) + 0x01cc)
++#define    DEMOSAIC_ADDR_H_SP_P2_S_LOW_HIGH(n)             (DEMOSAIC_BASE(n) + 0x01d0)
++#define    DEMOSAIC_ADDR_H_SP_P3_VALUE(n)             (DEMOSAIC_BASE(n) + 0x01d4)
++#define    DEMOSAIC_ADDR_H_SP_P3_THRES(n)             (DEMOSAIC_BASE(n) + 0x01d8)
++#define    DEMOSAIC_ADDR_H_SP_P3_S_LOW_HIGH(n)             (DEMOSAIC_BASE(n) + 0x01dc)
++#define    DEMOSAIC_ADDR_H_SP_SLOPE(n)             (DEMOSAIC_BASE(n) + 0x01e0)
++#define    DEMOSAIC_ADDR_S_S0_SEL(n)             (DEMOSAIC_BASE(n) + 0x01e4)
++#define    DEMOSAIC_ADDR_S_UU_THRES(n)             (DEMOSAIC_BASE(n) + 0x01e8)
++#define    DEMOSAIC_ADDR_S_UU_SLOPE(n)             (DEMOSAIC_BASE(n) + 0x01ec)
++#define    DEMOSAIC_ADDR_S_V2_COEF1234(n)             (DEMOSAIC_BASE(n) + 0x01f0)
++#define    DEMOSAIC_ADDR_S_V2_COEF5(n)             (DEMOSAIC_BASE(n) + 0x01f4)
++#define    DEMOSAIC_ADDR_S_V1_COEF012(n)             (DEMOSAIC_BASE(n) + 0x01f8)
++#define    DEMOSAIC_ADDR_S_WEI_SEG_OPT(n)             (DEMOSAIC_BASE(n) + 0x01fc)
++#define    DEMOSAIC_ADDR_S_WEI_SEG_OPT_1(n)             (DEMOSAIC_BASE(n) + 0x0200)
++#define    DEMOSAIC_ADDR_S_B_SP_STREN(n)             (DEMOSAIC_BASE(n) + 0x0204)
++#define    DEMOSAIC_ADDR_S_G_STD(n)             (DEMOSAIC_BASE(n) + 0x0208)
++#define    DEMOSAIC_ADDR_S_LL_THRES(n)             (DEMOSAIC_BASE(n) + 0x020c)
++#define    DEMOSAIC_ADDR_S_HL_THRES(n)             (DEMOSAIC_BASE(n) + 0x0210)
++#define    DEMOSAIC_ADDR_S_FLAT_THRES(n)             (DEMOSAIC_BASE(n) + 0x0214)
++#define    DEMOSAIC_ADDR_S_OE_EN(n)             (DEMOSAIC_BASE(n) + 0x0218)
++#define    DEMOSAIC_ADDR_S_SHRINK_EN(n)             (DEMOSAIC_BASE(n) + 0x021c)
++#define    DEMOSAIC_ADDR_FC_NOR_SAT(n)             (DEMOSAIC_BASE(n) + 0x0220)
++#define    DEMOSAIC_ADDR_FC_NOR_SAT_1(n)             (DEMOSAIC_BASE(n) + 0x0224)
++#define    DEMOSAIC_ADDR_FC_NOR_H_THRES(n)             (DEMOSAIC_BASE(n) + 0x0228)
++#define    DEMOSAIC_ADDR_FC_TEXT_SAT_THRES(n)             (DEMOSAIC_BASE(n) + 0x022c)
++#define    DEMOSAIC_ADDR_FC_TEXT_LUM_THRES(n)             (DEMOSAIC_BASE(n) + 0x0230)
++#define    DEMOSAIC_ADDR_FC_TEXT_S_STD_THRES(n)             (DEMOSAIC_BASE(n) + 0x0234)
++#define    DEMOSAIC_ADDR_FC_TEXT_H_THRES(n)             (DEMOSAIC_BASE(n) + 0x0238)
++#define    DEMOSAIC_ADDR_FC_NOR_H_SLOPE(n)             (DEMOSAIC_BASE(n) + 0x023c)
++#define    DEMOSAIC_ADDR_S_FLAT_SLOPE(n)             (DEMOSAIC_BASE(n) + 0x0240)
++#define    DEMOSAIC_ADDR_FC_OE_SAT_THRES(n)             (DEMOSAIC_BASE(n) + 0x0244)
++#define    DEMOSAIC_ADDR_FC_OE_H_THRES(n)             (DEMOSAIC_BASE(n) + 0x0248)
++#define    DEMOSAIC_ADDR_SP_S_WEI_NP_ARRAY(n)             (DEMOSAIC_BASE(n) + 0x024c)
++#define    DEMOSAIC_ADDR_SP_S_WEI_NP_ARRAY_1(n)             (DEMOSAIC_BASE(n) + 0x0250)
++#define    DEMOSAIC_ADDR_SP_S_WEI_NP_ARRAY_2(n)             (DEMOSAIC_BASE(n) + 0x0254)
++#define    DEMOSAIC_ADDR_SP_S_WEI_NP_ARRAY_3(n)             (DEMOSAIC_BASE(n) + 0x0258)
++#define    DEMOSAIC_ADDR_SP_S_WEI_NP_ARRAY_4(n)             (DEMOSAIC_BASE(n) + 0x025c)
++#define    DEMOSAIC_ADDR_SP_S_WEI_NP_ARRAY_5(n)             (DEMOSAIC_BASE(n) + 0x0260)
++#define    DEMOSAIC_ADDR_SP_S_WEI_NP_ARRAY_6(n)             (DEMOSAIC_BASE(n) + 0x0264)
++#define    DEMOSAIC_ADDR_SP_S_WEI_NP_ARRAY_7(n)             (DEMOSAIC_BASE(n) + 0x0268)
++#define    DEMOSAIC_ADDR_S_LAP_3_MUL_FACTOR(n)             (DEMOSAIC_BASE(n) + 0x026c)
++#define    DEMOSAIC_ADDR_S_LAP_3_STD_SLOPE(n)             (DEMOSAIC_BASE(n) + 0x0270)
++#define    DEMOSAIC_ADDR_G_LAP_3_MUL_FACTOR(n)             (DEMOSAIC_BASE(n) + 0x0274)
++#define    DEMOSAIC_ADDR_G_LAP_3_STD_SLOPE(n)             (DEMOSAIC_BASE(n) + 0x0278)
++
++//============================================================
++// CCM ADDRESS
++//============================================================
++#define MAIN_CCM_ADDR_SHD_CTRL                                 (CCM0_BASE + 0x0000)
++#define MAIN_CCM_ADDR_CCM_RRRG                                 (CCM0_BASE + 0x0004)
++#define MAIN_CCM_ADDR_CCM_RBGR                                 (CCM0_BASE + 0x0008)
++#define MAIN_CCM_ADDR_CCM_GGGB                                 (CCM0_BASE + 0x000c)
++#define MAIN_CCM_ADDR_CCM_BRBG                                 (CCM0_BASE + 0x0010)
++#define MAIN_CCM_ADDR_CCM_BB                                   (CCM0_BASE + 0x0014)
++#define MAIN_CCM_ADDR_CCM_DP_CFG                               (CCM0_BASE + 0x0018)
++#define MAIN_CCM_ADDR_CCM_DP_SLOPE                             (CCM0_BASE + 0x001c)
++#define MAIN_CCM_ADDR_CCM_SAT_THRES                            (CCM0_BASE + 0x0020)
++#define MAIN_CCM_ADDR_DEBUG0                                   (CCM0_BASE + 0x0024)
++#define MAIN_CCM_ADDR_DEBUG1                                   (CCM0_BASE + 0x0028)
++
++#define SEC_CCM_ADDR_SHD_CTRL                                 (CCM1_BASE + 0x0000)
++#define SEC_CCM_ADDR_CCM_RRRG                                 (CCM1_BASE + 0x0004)
++#define SEC_CCM_ADDR_CCM_RBGR                                 (CCM1_BASE + 0x0008)
++#define SEC_CCM_ADDR_CCM_GGGB                                 (CCM1_BASE + 0x000c)
++#define SEC_CCM_ADDR_CCM_BRBG                                 (CCM1_BASE + 0x0010)
++#define SEC_CCM_ADDR_CCM_BB                                   (CCM1_BASE + 0x0014)
++#define SEC_CCM_ADDR_CCM_DP_CFG                               (CCM1_BASE + 0x0018)
++#define SEC_CCM_ADDR_CCM_DP_SLOPE                             (CCM1_BASE + 0x001c)
++#define SEC_CCM_ADDR_CCM_SAT_THRES                            (CCM1_BASE + 0x0020)
++#define SEC_CCM_ADDR_DEBUG0                                   (CCM1_BASE + 0x0024)
++#define SEC_CCM_ADDR_DEBUG1
++
++//============================================================
++// DEFOG ADDRESS
++//============================================================
++#define    DEFOG_ADDR_VERSION(n)                  (DEFOG_BASE(n) + 0x0000)
++#define    DEFOG_ADDR_CTRL(n)                  (DEFOG_BASE(n) + 0x0004)
++#define    DEFOG_ADDR_BLOCKSIZE_BS(n)                  (DEFOG_BASE(n) + 0x0008)
++#define    DEFOG_ADDR_BLOCKSIZE_SY(n)                  (DEFOG_BASE(n) + 0x000c)
++#define    DEFOG_ADDR_PARA(n)                  (DEFOG_BASE(n) + 0x0010)
++#define    DEFOG_ADDR_EXT_PRIO(n)                  (DEFOG_BASE(n) + 0x0014)
++#define    DEFOG_ADDR_W_3X3_TABLE__01_00(n)                  (DEFOG_BASE(n) + 0x0020)
++#define    DEFOG_ADDR_W_3X3_TABLE__03_02(n)                  (DEFOG_BASE(n) + 0x0024)
++#define    DEFOG_ADDR_W_3X3_TABLE__05_04(n)                  (DEFOG_BASE(n) + 0x0028)
++#define    DEFOG_ADDR_W_3X3_TABLE__07_06(n)                  (DEFOG_BASE(n) + 0x002c)
++#define    DEFOG_ADDR_W_3X3_TABLE__09_08(n)                  (DEFOG_BASE(n) + 0x0030)
++#define    DEFOG_ADDR_W_3X3_TABLE__11_10(n)                  (DEFOG_BASE(n) + 0x0034)
++#define    DEFOG_ADDR_W_3X3_TABLE__13_12(n)                  (DEFOG_BASE(n) + 0x0038)
++#define    DEFOG_ADDR_W_3X3_TABLE__15_14(n)                  (DEFOG_BASE(n) + 0x003c)
++#define    DEFOG_ADDR_W_3X3_TABLE__17_16(n)                  (DEFOG_BASE(n) + 0x0040)
++#define    DEFOG_ADDR_W_3X3_TABLE__19_18(n)                  (DEFOG_BASE(n) + 0x0044)
++#define    DEFOG_ADDR_W_3X3_TABLE__21_20(n)                  (DEFOG_BASE(n) + 0x0048)
++#define    DEFOG_ADDR_W_3X3_TABLE__23_22(n)                  (DEFOG_BASE(n) + 0x004c)
++#define    DEFOG_ADDR_W_5X5_TABLE__01_00(n)                  (DEFOG_BASE(n) + 0x0050)
++#define    DEFOG_ADDR_W_5X5_TABLE__03_02(n)                  (DEFOG_BASE(n) + 0x0054)
++#define    DEFOG_ADDR_W_5X5_TABLE__05_04(n)                  (DEFOG_BASE(n) + 0x0058)
++#define    DEFOG_ADDR_W_5X5_TABLE__07_06(n)                  (DEFOG_BASE(n) + 0x005c)
++#define    DEFOG_ADDR_W_5X5_TABLE__09_08(n)                  (DEFOG_BASE(n) + 0x0060)
++#define    DEFOG_ADDR_W_5X5_TABLE__11_10(n)                  (DEFOG_BASE(n) + 0x0064)
++#define    DEFOG_ADDR_W_5X5_TABLE__13_12(n)                  (DEFOG_BASE(n) + 0x0068)
++#define    DEFOG_ADDR_W_5X5_TABLE__15_14(n)                  (DEFOG_BASE(n) + 0x006c)
++#define    DEFOG_ADDR_W_5X5_TABLE__17_16(n)                  (DEFOG_BASE(n) + 0x0070)
++#define    DEFOG_ADDR_W_5X5_TABLE__19_18(n)                  (DEFOG_BASE(n) + 0x0074)
++#define    DEFOG_ADDR_W_5X5_TABLE__21_20(n)                  (DEFOG_BASE(n) + 0x0078)
++#define    DEFOG_ADDR_W_5X5_TABLE__23_22(n)                  (DEFOG_BASE(n) + 0x007c)
++#define    DEFOG_ADDR_W_5X5_TABLE__25_24(n)                  (DEFOG_BASE(n) + 0x0080)
++#define    DEFOG_ADDR_W_5X5_TABLE__27_26(n)                  (DEFOG_BASE(n) + 0x0084)
++#define    DEFOG_ADDR_W_5X5_TABLE__29_28(n)                  (DEFOG_BASE(n) + 0x0088)
++#define    DEFOG_ADDR_W_5X5_TABLE__30_30(n)                  (DEFOG_BASE(n) + 0x008c)
++#define    DEFOG_ADDR_WEIGHT_A__03_00(n)                  (DEFOG_BASE(n) + 0x0090)
++#define    DEFOG_ADDR_WEIGHT_A__07_04(n)                  (DEFOG_BASE(n) + 0x0094)
++#define    DEFOG_ADDR_WEIGHT_A__11_08(n)                  (DEFOG_BASE(n) + 0x0098)
++#define    DEFOG_ADDR_WEIGHT_A__15_12(n)                  (DEFOG_BASE(n) + 0x009c)
++#define    DEFOG_ADDR_WEIGHT_A__19_16(n)                  (DEFOG_BASE(n) + 0x00a0)
++#define    DEFOG_ADDR_WEIGHT_A__23_20(n)                  (DEFOG_BASE(n) + 0x00a4)
++#define    DEFOG_ADDR_WEIGHT_A__27_24(n)                  (DEFOG_BASE(n) + 0x00a8)
++#define    DEFOG_ADDR_WEIGHT_A__31_28(n)                  (DEFOG_BASE(n) + 0x00ac)
++#define    DEFOG_ADDR_WEIGHT_B1__03_00(n)                  (DEFOG_BASE(n) + 0x00b0)
++#define    DEFOG_ADDR_WEIGHT_B1__07_04(n)                  (DEFOG_BASE(n) + 0x00b4)
++#define    DEFOG_ADDR_WEIGHT_B1__11_08(n)                  (DEFOG_BASE(n) + 0x00b8)
++#define    DEFOG_ADDR_WEIGHT_B1__15_12(n)                  (DEFOG_BASE(n) + 0x00bc)
++#define    DEFOG_ADDR_WEIGHT_B1__19_16(n)                  (DEFOG_BASE(n) + 0x00c0)
++#define    DEFOG_ADDR_WEIGHT_B1__23_20(n)                  (DEFOG_BASE(n) + 0x00c4)
++#define    DEFOG_ADDR_WEIGHT_B1__27_24(n)                  (DEFOG_BASE(n) + 0x00c8)
++#define    DEFOG_ADDR_WEIGHT_B1__31_28(n)                  (DEFOG_BASE(n) + 0x00cc)
++#define    DEFOG_ADDR_WEIGHT_B2__03_00(n)                  (DEFOG_BASE(n) + 0x00d0)
++#define    DEFOG_ADDR_WEIGHT_B2__07_04(n)                  (DEFOG_BASE(n) + 0x00d4)
++#define    DEFOG_ADDR_WEIGHT_B2__11_08(n)                  (DEFOG_BASE(n) + 0x00d8)
++#define    DEFOG_ADDR_WEIGHT_B2__15_12(n)                  (DEFOG_BASE(n) + 0x00dc)
++#define    DEFOG_ADDR_WEIGHT_B2__19_16(n)                  (DEFOG_BASE(n) + 0x00e0)
++#define    DEFOG_ADDR_WEIGHT_B2__23_20(n)                  (DEFOG_BASE(n) + 0x00e4)
++#define    DEFOG_ADDR_WEIGHT_B2__27_24(n)                  (DEFOG_BASE(n) + 0x00e8)
++#define    DEFOG_ADDR_WEIGHT_B2__31_28(n)                  (DEFOG_BASE(n) + 0x00ec)
++#define    DEFOG_ADDR_WEIGHT_C1__03_00(n)                  (DEFOG_BASE(n) + 0x00f0)
++#define    DEFOG_ADDR_WEIGHT_C1__07_04(n)                  (DEFOG_BASE(n) + 0x00f4)
++#define    DEFOG_ADDR_WEIGHT_C1__11_08(n)                  (DEFOG_BASE(n) + 0x00f8)
++#define    DEFOG_ADDR_WEIGHT_C1__15_12(n)                  (DEFOG_BASE(n) + 0x00fc)
++#define    DEFOG_ADDR_WEIGHT_C1__19_16(n)                  (DEFOG_BASE(n) + 0x0100)
++#define    DEFOG_ADDR_WEIGHT_C1__23_20(n)                  (DEFOG_BASE(n) + 0x0104)
++#define    DEFOG_ADDR_WEIGHT_C1__27_24(n)                  (DEFOG_BASE(n) + 0x0108)
++#define    DEFOG_ADDR_WEIGHT_C1__31_28(n)                  (DEFOG_BASE(n) + 0x010c)
++#define    DEFOG_ADDR_WEIGHT_C2__03_00(n)                  (DEFOG_BASE(n) + 0x0110)
++#define    DEFOG_ADDR_WEIGHT_C2__07_04(n)                  (DEFOG_BASE(n) + 0x0114)
++#define    DEFOG_ADDR_WEIGHT_C2__11_08(n)                  (DEFOG_BASE(n) + 0x0118)
++#define    DEFOG_ADDR_WEIGHT_C2__15_12(n)                  (DEFOG_BASE(n) + 0x011c)
++#define    DEFOG_ADDR_WEIGHT_C2__19_16(n)                  (DEFOG_BASE(n) + 0x0120)
++#define    DEFOG_ADDR_WEIGHT_C2__23_20(n)                  (DEFOG_BASE(n) + 0x0124)
++#define    DEFOG_ADDR_WEIGHT_C2__27_24(n)                  (DEFOG_BASE(n) + 0x0128)
++#define    DEFOG_ADDR_WEIGHT_C2__31_28(n)                  (DEFOG_BASE(n) + 0x012c)
++#define    DEFOG_ADDR_LC_SAT__03_00(n)                  (DEFOG_BASE(n) + 0x0130)
++#define    DEFOG_ADDR_LC_SAT__07_04(n)                  (DEFOG_BASE(n) + 0x0134)
++#define    DEFOG_ADDR_LC_SAT__11_08(n)                  (DEFOG_BASE(n) + 0x0138)
++#define    DEFOG_ADDR_LC_SAT__15_12(n)                  (DEFOG_BASE(n) + 0x013c)
++#define    DEFOG_ADDR_LC_SAT__19_16(n)                  (DEFOG_BASE(n) + 0x0140)
++#define    DEFOG_ADDR_LC_SAT__23_20(n)                  (DEFOG_BASE(n) + 0x0144)
++#define    DEFOG_ADDR_LC_SAT__27_24(n)                  (DEFOG_BASE(n) + 0x0148)
++#define    DEFOG_ADDR_LC_SAT__31_28(n)                  (DEFOG_BASE(n) + 0x014c)
++#define    DEFOG_ADDR_LC_VAL__03_00(n)                  (DEFOG_BASE(n) + 0x0150)
++#define    DEFOG_ADDR_LC_VAL__07_04(n)                  (DEFOG_BASE(n) + 0x0154)
++#define    DEFOG_ADDR_LC_VAL__11_08(n)                  (DEFOG_BASE(n) + 0x0158)
++#define    DEFOG_ADDR_LC_VAL__15_12(n)                  (DEFOG_BASE(n) + 0x015c)
++#define    DEFOG_ADDR_LC_VAL__19_16(n)                  (DEFOG_BASE(n) + 0x0160)
++#define    DEFOG_ADDR_LC_VAL__23_20(n)                  (DEFOG_BASE(n) + 0x0164)
++#define    DEFOG_ADDR_LC_VAL__27_24(n)                  (DEFOG_BASE(n) + 0x0168)
++#define    DEFOG_ADDR_LC_VAL__31_28(n)                  (DEFOG_BASE(n) + 0x016c)
++#define    DEFOG_ADDR_K_ADJUST__01_00(n)                  (DEFOG_BASE(n) + 0x0170)
++#define    DEFOG_ADDR_K_ADJUST__03_02(n)                  (DEFOG_BASE(n) + 0x0174)
++#define    DEFOG_ADDR_K_ADJUST__05_04(n)                  (DEFOG_BASE(n) + 0x0178)
++#define    DEFOG_ADDR_K_ADJUST__07_06(n)                  (DEFOG_BASE(n) + 0x017c)
++#define    DEFOG_ADDR_K_ADJUST__09_08(n)                  (DEFOG_BASE(n) + 0x0180)
++#define    DEFOG_ADDR_K_ADJUST__11_10(n)                  (DEFOG_BASE(n) + 0x0184)
++#define    DEFOG_ADDR_K_ADJUST__13_12(n)                  (DEFOG_BASE(n) + 0x0188)
++#define    DEFOG_ADDR_K_ADJUST__15_14(n)                  (DEFOG_BASE(n) + 0x018c)
++#define    DEFOG_ADDR_K_ADJUST__16_16(n)                  (DEFOG_BASE(n) + 0x0190)
++#define    DEFOG_ADDR_SSJ_DIFF_THR__03_00(n)                  (DEFOG_BASE(n) + 0x0194)
++#define    DEFOG_ADDR_SSJ_DIFF_THR__07_04(n)                  (DEFOG_BASE(n) + 0x0198)
++#define    DEFOG_ADDR_SSJ_DIFF_THR__11_08(n)                  (DEFOG_BASE(n) + 0x019c)
++#define    DEFOG_ADDR_SSJ_DIFF_THR__15_12(n)                  (DEFOG_BASE(n) + 0x01a0)
++#define    DEFOG_ADDR_SSJ_DIFF_THR__19_16(n)                  (DEFOG_BASE(n) + 0x01a4)
++#define    DEFOG_ADDR_SSJ_DIFF_THR__23_20(n)                  (DEFOG_BASE(n) + 0x01a8)
++#define    DEFOG_ADDR_SSJ_DIFF_THR__27_24(n)                  (DEFOG_BASE(n) + 0x01ac)
++#define    DEFOG_ADDR_SSJ_DIFF_THR__31_28(n)                  (DEFOG_BASE(n) + 0x01b0)
++#define    DEFOG_ADDR_ADJUST_RED__03_00(n)                  (DEFOG_BASE(n) + 0x01b4)
++#define    DEFOG_ADDR_ADJUST_RED__07_04(n)                  (DEFOG_BASE(n) + 0x01b8)
++#define    DEFOG_ADDR_ADJUST_RED__11_08(n)                  (DEFOG_BASE(n) + 0x01bc)
++#define    DEFOG_ADDR_ADJUST_RED__15_12(n)                  (DEFOG_BASE(n) + 0x01c0)
++#define    DEFOG_ADDR_ADJUST_RED__16_16(n)                  (DEFOG_BASE(n) + 0x01c4)
++#define    DEFOG_ADDR_ADJUST_GREEN__03_00(n)                  (DEFOG_BASE(n) + 0x01c8)
++#define    DEFOG_ADDR_ADJUST_GREEN__07_04(n)                  (DEFOG_BASE(n) + 0x01cc)
++#define    DEFOG_ADDR_ADJUST_GREEN__11_08(n)                  (DEFOG_BASE(n) + 0x01d0)
++#define    DEFOG_ADDR_ADJUST_GREEN__15_12(n)                  (DEFOG_BASE(n) + 0x01d4)
++#define    DEFOG_ADDR_ADJUST_GREEN__16_16(n)                  (DEFOG_BASE(n) + 0x01d8)
++#define    DEFOG_ADDR_ADJUST_BLUE__03_00(n)                  (DEFOG_BASE(n) + 0x01dc)
++#define    DEFOG_ADDR_ADJUST_BLUE__07_04(n)                  (DEFOG_BASE(n) + 0x01e0)
++#define    DEFOG_ADDR_ADJUST_BLUE__11_08(n)                  (DEFOG_BASE(n) + 0x01e4)
++#define    DEFOG_ADDR_ADJUST_BLUE__15_12(n)                  (DEFOG_BASE(n) + 0x01e8)
++#define    DEFOG_ADDR_ADJUST_BLUE__16_16(n)                  (DEFOG_BASE(n) + 0x01ec)
++#define    DEFOG_ADDR_ADJUST_YELLOW__03_00(n)                  (DEFOG_BASE(n) + 0x01f0)
++#define    DEFOG_ADDR_ADJUST_YELLOW__07_04(n)                  (DEFOG_BASE(n) + 0x01f4)
++#define    DEFOG_ADDR_ADJUST_YELLOW__11_08(n)                  (DEFOG_BASE(n) + 0x01f8)
++#define    DEFOG_ADDR_ADJUST_YELLOW__15_12(n)                  (DEFOG_BASE(n) + 0x01fc)
++#define    DEFOG_ADDR_ADJUST_YELLOW__16_16(n)                  (DEFOG_BASE(n) + 0x0200)
++#define    DEFOG_ADDR_ADJUST_PURPLE__03_00(n)                  (DEFOG_BASE(n) + 0x0204)
++#define    DEFOG_ADDR_ADJUST_PURPLE__07_04(n)                  (DEFOG_BASE(n) + 0x0208)
++#define    DEFOG_ADDR_ADJUST_PURPLE__11_08(n)                  (DEFOG_BASE(n) + 0x020c)
++#define    DEFOG_ADDR_ADJUST_PURPLE__15_12(n)                  (DEFOG_BASE(n) + 0x0210)
++#define    DEFOG_ADDR_ADJUST_PURPLE__16_16(n)                  (DEFOG_BASE(n) + 0x0214)
++#define    DEFOG_ADDR_ADJUST_CYAN__03_00(n)                  (DEFOG_BASE(n) + 0x0218)
++#define    DEFOG_ADDR_ADJUST_CYAN__07_04(n)                  (DEFOG_BASE(n) + 0x021c)
++#define    DEFOG_ADDR_ADJUST_CYAN__11_08(n)                  (DEFOG_BASE(n) + 0x0220)
++#define    DEFOG_ADDR_ADJUST_CYAN__15_12(n)                  (DEFOG_BASE(n) + 0x0224)
++#define    DEFOG_ADDR_ADJUST_CYAN__16_16(n)                  (DEFOG_BASE(n) + 0x0228)
++#define    DEFOG_ADDR_DEFOG_DB__03_00(n)                  (DEFOG_BASE(n) + 0x022c)
++#define    DEFOG_ADDR_DEFOG_DB__07_04(n)                  (DEFOG_BASE(n) + 0x0230)
++#define    DEFOG_ADDR_DEFOG_DB__11_08(n)                  (DEFOG_BASE(n) + 0x0234)
++#define    DEFOG_ADDR_DEFOG_DB__15_12(n)                  (DEFOG_BASE(n) + 0x0238)
++#define    DEFOG_ADDR_DEFOG_DB__19_16(n)                  (DEFOG_BASE(n) + 0x023c)
++#define    DEFOG_ADDR_DEFOG_DB__23_20(n)                  (DEFOG_BASE(n) + 0x0240)
++#define    DEFOG_ADDR_DEFOG_DB__27_24(n)                  (DEFOG_BASE(n) + 0x0244)
++#define    DEFOG_ADDR_DEFOG_DB__31_28(n)                  (DEFOG_BASE(n) + 0x0248)
++#define    DEFOG_ADDR_FRAME_RATE(n)                  (DEFOG_BASE(n) + 0x0280)
++#define    DEFOG_ADDR_STAT(n)                  (DEFOG_BASE(n) + 0x0284)
++#define    DEFOG_ADDR_BANK_BUFF_NUM(n)                  (DEFOG_BASE(n) + 0x028c)
++#define    DEFOG_ADDR_BANK_ADDR0_00_00(n)                  (DEFOG_BASE(n) + 0x0290)
++#define    DEFOG_ADDR_BANK_ADDR0_01_01(n)                  (DEFOG_BASE(n) + 0x0294)
++#define    DEFOG_ADDR_BANK_ADDR0_02_02(n)                  (DEFOG_BASE(n) + 0x0298)
++#define    DEFOG_ADDR_BANK_ADDR0_03_03(n)                  (DEFOG_BASE(n) + 0x029c)
++#define    DEFOG_ADDR_DEBUG_REG_FLAG(n)                  (DEFOG_BASE(n) + 0x02a0)
++#define    DEFOG_ADDR_LUT_RD_SEL(n)                  (DEFOG_BASE(n) + 0x02a8)
++#define    DEFOG_ADDR_LUT_SHD_EN(n)                  (DEFOG_BASE(n) + 0x02ac)
++#define    DEFOG_ADDR_FRAME_ID0(n)                  (DEFOG_BASE(n) + 0x02b0)
++#define    DEFOG_ADDR_FRAME_ADDR(n)                   (DEFOG_BASE(0) + 0x02b4 + 8 * n)
++#define    DEFOG_ADDR_FRAME_ID1(n)                  (DEFOG_BASE(n) + 0x02b8)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_0(n)                  (DEFOG_BASE(n) + 0x0300)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_1(n)                  (DEFOG_BASE(n) + 0x0304)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_2(n)                  (DEFOG_BASE(n) + 0x0308)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_3(n)                  (DEFOG_BASE(n) + 0x030c)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_4(n)                  (DEFOG_BASE(n) + 0x0310)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_5(n)                  (DEFOG_BASE(n) + 0x0314)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_6(n)                  (DEFOG_BASE(n) + 0x0318)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_7(n)                  (DEFOG_BASE(n) + 0x031c)
++
++//============================================================
++// CSC ADDRESS
++//============================================================
++#define    CSC_ADDR_CTRL(n)       (CSC_BASE(n) + 0x0000)
++#define    CSC_ADDR_SUB(n)       (CSC_BASE(n) + 0x0004)
++#define    CSC_ADDR_PAR_0(n)       (CSC_BASE(n) + 0x0010)
++#define    CSC_ADDR_PAR_1(n)       (CSC_BASE(n) + 0x0014)
++#define    CSC_ADDR_PAR_2(n)       (CSC_BASE(n) + 0x0018)
++#define    CSC_ADDR_OFF_SET(n)       (CSC_BASE(n) + 0x0020)
++#define    CSC_ADDR_CLIP(n)       (CSC_BASE(n) + 0x0030)
++#define    CSC_ADDR_MODE(n)       (CSC_BASE(n) + 0x0034)
++#define    CSC_ADDR_DBG_0(n)       (CSC_BASE(n) + 0x0040)
++#define    CSC_ADDR_DBG_1(n)       (CSC_BASE(n) + 0x0044)
++#define    CSC_ADDR_DBG_2(n)       (CSC_BASE(n) + 0x0048)
++#define    CSC_ADDR_DBG_3(n)       (CSC_BASE(n) + 0x004c)
++
++//============================================================
++// LCE ADDRESS
++//============================================================
++#define    MAIN_LCE_ADDR_ZONE_INFO1                                  (LCE0_BASE + 0x0000)
++#define    MAIN_LCE_ADDR_ZONE_INFO2                                  (LCE0_BASE + 0x0004)
++#define    MAIN_LCE_ADDR_AREA_SIZE1                                  (LCE0_BASE + 0x0008)
++#define    MAIN_LCE_ADDR_AREA_SIZE2                                  (LCE0_BASE + 0x000c)
++#define    MAIN_LCE_ADDR_RAM_INFO1                                   (LCE0_BASE + 0x0010)
++#define    MAIN_LCE_ADDR_RAM_INFO2                                   (LCE0_BASE + 0x0014)
++#define    MAIN_LCE_ADDR_DEBUG_0                                     (LCE0_BASE + 0x0018)
++#define    MAIN_LCE_ADDR_DEBUG_1                                     (LCE0_BASE + 0x001c)
++#define    MAIN_LCE_ADDR_DEBUG_2                                     (LCE0_BASE + 0x0020)
++#define    MAIN_LCE_ADDR_DEBUG_3                                     (LCE0_BASE + 0x0024)
++#define    MAIN_LCE_ADDR_DEBUG_4                                     (LCE0_BASE + 0x0028)
++#define    MAIN_LCE_ADDR_DEBUG_5                                     (LCE0_BASE + 0x002c)
++#define    MAIN_LCE_ADDR_DEBUG_6                                     (LCE0_BASE + 0x0030)
++#define    MAIN_LCE_ADDR_DEBUG_7                                     (LCE0_BASE + 0x0034)
++#define    MAIN_LCE_ADDR_DEBUG_8                                     (LCE0_BASE + 0x0038)
++#define    MAIN_LCE_ADDR_DEBUG_9                                     (LCE0_BASE + 0x003c)
++#define    MAIN_LCE_ADDR_DEBUG_10                                    (LCE0_BASE + 0x0040)
++#define    MAIN_LCE_ADDR_DEBUG_11                                    (LCE0_BASE + 0x0044)
++#define    MAIN_LCE_ADDR_DEBUG_12                                    (LCE0_BASE + 0x0048)
++#define    MAIN_LCE_ADDR_DEBUG_13                                    (LCE0_BASE + 0x004c)
++#define    MAIN_LCE_ADDR_PARSTORE_CLR                                (LCE0_BASE + 0x0080)
++#define    MAIN_LCE_ADDR_PARSTORE_DONE                               (LCE0_BASE + 0x0084)
++#define    MAIN_LCE_ADDR_PARSTORE_RBSEL                              (LCE0_BASE + 0x0088)
++
++#define    SEC_LCE_ADDR_ZONE_INFO1                                   (LCE1_BASE + 0x0000)
++#define    SEC_LCE_ADDR_ZONE_INFO2                                   (LCE1_BASE + 0x0004)
++#define    SEC_LCE_ADDR_AREA_SIZE1                                   (LCE1_BASE + 0x0008)
++#define    SEC_LCE_ADDR_AREA_SIZE2                                   (LCE1_BASE + 0x000c)
++#define    SEC_LCE_ADDR_RAM_INFO1                                    (LCE1_BASE + 0x0010)
++#define    SEC_LCE_ADDR_RAM_INFO2                                    (LCE1_BASE + 0x0014)
++#define    SEC_LCE_ADDR_DEBUG_0                                      (LCE1_BASE + 0x0018)
++#define    SEC_LCE_ADDR_DEBUG_1                                      (LCE1_BASE + 0x001c)
++#define    SEC_LCE_ADDR_DEBUG_2                                      (LCE1_BASE + 0x0020)
++#define    SEC_LCE_ADDR_DEBUG_3                                      (LCE1_BASE + 0x0024)
++#define    SEC_LCE_ADDR_DEBUG_4                                      (LCE1_BASE + 0x0028)
++#define    SEC_LCE_ADDR_DEBUG_5                                      (LCE1_BASE + 0x002c)
++#define    SEC_LCE_ADDR_DEBUG_6                                      (LCE1_BASE + 0x0030)
++#define    SEC_LCE_ADDR_DEBUG_7                                      (LCE1_BASE + 0x0034)
++#define    SEC_LCE_ADDR_DEBUG_8                                      (LCE1_BASE + 0x0038)
++#define    SEC_LCE_ADDR_DEBUG_9                                      (LCE1_BASE + 0x003c)
++#define    SEC_LCE_ADDR_DEBUG_10                                     (LCE1_BASE + 0x0040)
++#define    SEC_LCE_ADDR_DEBUG_11                                     (LCE1_BASE + 0x0044)
++#define    SEC_LCE_ADDR_DEBUG_12                                     (LCE1_BASE + 0x0048)
++#define    SEC_LCE_ADDR_DEBUG_13                                     (LCE1_BASE + 0x004c)
++#define    SEC_LCE_ADDR_PARSTORE_CLR                                 (LCE1_BASE + 0x0080)
++#define    SEC_LCE_ADDR_PARSTORE_DONE                                (LCE1_BASE + 0x0084)
++#define    SEC_LCE_ADDR_PARSTORE_RBSEL                               (LCE1_BASE + 0x0088)
++
++//============================================================
++// MDNS ADDRESS
++//============================================================
++#define    MDNS_ADDR_VERSION(n)                                     (MDNS_BASE(n) + 0x0000)
++#define    MDNS_ADDR_SHD_CTRL(n)                                    (MDNS_BASE(n) + 0x0004)
++#define    MDNS_ADDR_START(n)                                       (MDNS_BASE(n) + 0x0008)
++#define    MDNS_ADDR_OUTSEL(n)                                      (MDNS_BASE(n) + 0x000c)
++#define    MDNS_ADDR_MD_EN(n)                                       (MDNS_BASE(n) + 0x0020)
++#define    MDNS_ADDR_FUNC_EN(n)                                     (MDNS_BASE(n) + 0x0024)
++#define    MDNS_ADDR_YREF_ADDR(n)                                   (MDNS_BASE(n) + 0x0040)
++#define    MDNS_ADDR_YREF_STRIDE(n)                                 (MDNS_BASE(n) + 0x0044)
++#define    MDNS_ADDR_CREF_ADDR(n)                                   (MDNS_BASE(n) + 0x0048)
++#define    MDNS_ADDR_CREF_STRIDE(n)                                 (MDNS_BASE(n) + 0x004c)
++#define    MDNS_ADDR_BSN_ADDR(n)                                    (MDNS_BASE(n) + 0x0050)
++#define    MDNS_ADDR_BSN_STRIDE(n)                                  (MDNS_BASE(n) + 0x0054)
++#define    MDNS_ADDR_ASS_ADDR(n)                                    (MDNS_BASE(n) + 0x0058)
++#define    MDNS_ADDR_ASS_STRIDE(n)                                  (MDNS_BASE(n) + 0x005c)
++#define    MDNS_ADDR_LYN_ADDR(n)                                    (MDNS_BASE(n) + 0x0060)
++#define    MDNS_ADDR_LYN_STRIDE(n)                                  (MDNS_BASE(n) + 0x0064)
++#define    MDNS_ADDR_YTTPHASE(n)                                    (MDNS_BASE(n) + 0x0068)
++#define    MDNS_ADDR_CTTPHASE(n)                                    (MDNS_BASE(n) + 0x006c)
++#define    MDNS_ADDR_YRESENDPOINT(n)                                (MDNS_BASE(n) + 0x0070)
++#define    MDNS_ADDR_CRESENDPOINT(n)                                (MDNS_BASE(n) + 0x0074)
++#define    MDNS_ADDR_BSNBLKSIZE(n)                (MDNS_BASE(n) + 0x0100)
++#define    MDNS_ADDR_BSNPOS(n)                (MDNS_BASE(n) + 0x0104)
++#define    MDNS_ADDR_BSNIMGSIZE(n)                (MDNS_BASE(n) + 0x0108)
++#define    MDNS_ADDR_BSNNUM(n)                (MDNS_BASE(n) + 0x010c)
++#define    MDNS_ADDR_BSNLINPAR(n)                (MDNS_BASE(n) + 0x0110)
++#define    MDNS_ADDR_BSNTHRES(n)                (MDNS_BASE(n) + 0x0114)
++#define    MDNS_ADDR_PBV0THRES(n)                (MDNS_BASE(n) + 0x0118)
++#define    MDNS_ADDR_PBV1THRES(n)                (MDNS_BASE(n) + 0x011c)
++#define    MDNS_ADDR_CNRADJPAR0(n)                (MDNS_BASE(n) + 0x0120)
++#define    MDNS_ADDR_LUMAADJPAR0(n)                (MDNS_BASE(n) + 0x0124)
++#define    MDNS_ADDR_LUMAADJPAR1(n)                (MDNS_BASE(n) + 0x0128)
++#define    MDNS_ADDR_LUMAADJPAR2(n)                (MDNS_BASE(n) + 0x012c)
++#define    MDNS_ADDR_EDGEADJPAR0(n)                (MDNS_BASE(n) + 0x0130)
++#define    MDNS_ADDR_EDGEADJPAR1(n)                (MDNS_BASE(n) + 0x0134)
++#define    MDNS_ADDR_EDGEADJPAR2(n)                (MDNS_BASE(n) + 0x0138)
++#define    MDNS_ADDR_SADTHRES(n)                (MDNS_BASE(n) + 0x013c)
++#define    MDNS_ADDR_LIMREFWEI(n)                (MDNS_BASE(n) + 0x0150)
++#define    MDNS_ADDR_BSNREFWEIPAR0(n)                (MDNS_BASE(n) + 0x0154)
++#define    MDNS_ADDR_BSNREFWEIPAR1(n)                (MDNS_BASE(n) + 0x0158)
++#define    MDNS_ADDR_PBV0REFWEIPAR0(n)                (MDNS_BASE(n) + 0x015c)
++#define    MDNS_ADDR_PBV0REFWEIPAR1(n)                (MDNS_BASE(n) + 0x0160)
++#define    MDNS_ADDR_PBV1REFWEIPAR0(n)                (MDNS_BASE(n) + 0x0164)
++#define    MDNS_ADDR_PBV1REFWEIPAR1(n)                (MDNS_BASE(n) + 0x0168)
++#define    MDNS_ADDR_PSNREFWEI(n)                (MDNS_BASE(n) + 0x016c)
++#define    MDNS_ADDR_PBVFUSWEIPAR0(n)                (MDNS_BASE(n) + 0x0170)
++#define    MDNS_ADDR_PBVFUSWEIPAR1(n)                (MDNS_BASE(n) + 0x0174)
++#define    MDNS_ADDR_PBVFUSWEIPAR2(n)                (MDNS_BASE(n) + 0x0178)
++#define    MDNS_ADDR_BSNFUSWEIPAR0(n)                (MDNS_BASE(n) + 0x017c)
++#define    MDNS_ADDR_BSNFUSWEIPAR1(n)                (MDNS_BASE(n) + 0x0180)
++#define    MDNS_ADDR_BSNFUSWEIPAR2(n)                (MDNS_BASE(n) + 0x0184)
++#define    MDNS_ADDR_LUMAFUSWEIPAR0(n)                (MDNS_BASE(n) + 0x0188)
++#define    MDNS_ADDR_LUMAFUSWEIPAR1(n)                (MDNS_BASE(n) + 0x018c)
++#define    MDNS_ADDR_LUMAFUSWEIPAR2(n)                (MDNS_BASE(n) + 0x0190)
++#define    MDNS_ADDR_PSNFUSWEI(n)                (MDNS_BASE(n) + 0x0194)
++#define    MDNS_ADDR_CNRFUSWEI(n)                (MDNS_BASE(n) + 0x0198)
++#define    MDNS_ADDR_BGMWEIMINPAR0(n)                (MDNS_BASE(n) + 0x01b0)
++#define    MDNS_ADDR_BGMWEIMINPAR1(n)                (MDNS_BASE(n) + 0x01b4)
++#define    MDNS_ADDR_BGMWEIMINPAR2(n)                (MDNS_BASE(n) + 0x01b8)
++#define    MDNS_ADDR_STILLSTAGEPAR0(n)                (MDNS_BASE(n) + 0x01bc)
++#define    MDNS_ADDR_STILLSTAGEPAR1(n)                (MDNS_BASE(n) + 0x01c0)
++#define    MDNS_ADDR_EDGEVALPAR0(n)                (MDNS_BASE(n) + 0x01c4)
++#define    MDNS_ADDR_EDGEVALPAR1(n)                (MDNS_BASE(n) + 0x01c8)
++#define    MDNS_ADDR_EDGEVALPAR2(n)                (MDNS_BASE(n) + 0x01cc)
++#define    MDNS_ADDR_EDGEVALPAR3(n)                (MDNS_BASE(n) + 0x01d0)
++#define    MDNS_ADDR_EDGEVALPAR4(n)                (MDNS_BASE(n) + 0x01d4)
++#define    MDNS_ADDR_CBMFUSWEIPAR0(n)                (MDNS_BASE(n) + 0x01d8)
++#define    MDNS_ADDR_CBMFUSWEIPAR1(n)                (MDNS_BASE(n) + 0x01dc)
++#define    MDNS_ADDR_CBMFUSWEIPAR2(n)                (MDNS_BASE(n) + 0x01e0)
++#define    MDNS_ADDR_RBMFUSWEIPAR0(n)                (MDNS_BASE(n) + 0x01e4)
++#define    MDNS_ADDR_RBMFUSWEIPAR1(n)                (MDNS_BASE(n) + 0x01e8)
++#define    MDNS_ADDR_RBMFUSWEIPAR2(n)                (MDNS_BASE(n) + 0x01ec)
++#define    MDNS_ADDR_SPATHRES(n)                (MDNS_BASE(n) + 0x01f0)
++#define    MDNS_ADDR_BGMFUSWEIPAR0(n)                (MDNS_BASE(n) + 0x01f4)
++#define    MDNS_ADDR_BGMFUSWEIPAR1(n)                (MDNS_BASE(n) + 0x01f8)
++#define    MDNS_ADDR_CURSPAFUSWEIPAR0(n)                (MDNS_BASE(n) + 0x01fc)
++#define    MDNS_ADDR_CURSPAFUSWEIPAR1(n)                (MDNS_BASE(n) + 0x0200)
++#define    MDNS_ADDR_REFSPAFUSWEIPAR0(n)                (MDNS_BASE(n) + 0x0204)
++#define    MDNS_ADDR_REFSPAFUSWEIPAR1(n)                (MDNS_BASE(n) + 0x0208)
++#define    MDNS_ADDR_REFRECALWEI(n)                (MDNS_BASE(n) + 0x020c)
++#define    MDNS_ADDR_IIRPAR0(n)                (MDNS_BASE(n) + 0x0210)
++#define    MDNS_ADDR_IIRPAR1(n)                (MDNS_BASE(n) + 0x0214)
++#define    MDNS_ADDR_IIRPAR2(n)                (MDNS_BASE(n) + 0x0218)
++#define    MDNS_ADDR_CSADTHRES(n)                (MDNS_BASE(n) + 0x0230)
++#define    MDNS_ADDR_CLIMREFWEI(n)                (MDNS_BASE(n) + 0x0234)
++#define    MDNS_ADDR_LYNWEIMINPAR0(n)                (MDNS_BASE(n) + 0x0238)
++#define    MDNS_ADDR_LYNWEIMINPAR1(n)                (MDNS_BASE(n) + 0x023c)
++#define    MDNS_ADDR_LYNWEIMINPAR2(n)                (MDNS_BASE(n) + 0x0240)
++#define    MDNS_ADDR_LYNFUSWEIPAR0(n)                (MDNS_BASE(n) + 0x0244)
++#define    MDNS_ADDR_LYNFUSWEIPAR1(n)                (MDNS_BASE(n) + 0x0248)
++#define    MDNS_ADDR_CCBMFUSWEIPAR0(n)                (MDNS_BASE(n) + 0x024c)
++#define    MDNS_ADDR_CCBMFUSWEIPAR1(n)                (MDNS_BASE(n) + 0x0250)
++#define    MDNS_ADDR_CCBMFUSWEIPAR2(n)                (MDNS_BASE(n) + 0x0254)
++#define    MDNS_ADDR_CRBMFUSWEIPAR0(n)                (MDNS_BASE(n) + 0x0258)
++#define    MDNS_ADDR_CRBMFUSWEIPAR1(n)                (MDNS_BASE(n) + 0x025c)
++#define    MDNS_ADDR_CRBMFUSWEIPAR2(n)                (MDNS_BASE(n) + 0x0260)
++#define    MDNS_ADDR_CCURSPAFUSWEIPAR0(n)                (MDNS_BASE(n) + 0x0264)
++#define    MDNS_ADDR_CCURSPAFUSWEIPAR1(n)                (MDNS_BASE(n) + 0x0268)
++#define    MDNS_ADDR_CREFSPAFUSWEIPAR0(n)                (MDNS_BASE(n) + 0x026c)
++#define    MDNS_ADDR_CREFSPAFUSWEIPAR1(n)                (MDNS_BASE(n) + 0x0270)
++#define    MDNS_ADDR_CREFRECALWEI(n)                (MDNS_BASE(n) + 0x0274)
++#define    MDNS_ADDR_CIIRPAR0(n)                (MDNS_BASE(n) + 0x0278)
++#define    MDNS_ADDR_CIIRPAR1(n)                (MDNS_BASE(n) + 0x027c)
++#define    MDNS_ADDR_CIIRPAR2(n)                (MDNS_BASE(n) + 0x0280)
++#define    MDNS_ADDR_DEPURPLEPAR0(n)                (MDNS_BASE(n) + 0x02a0)
++#define    MDNS_ADDR_DEPURPLEPAR1(n)                (MDNS_BASE(n) + 0x02a4)
++#define    MDNS_ADDR_DEPURPLEPAR2(n)                (MDNS_BASE(n) + 0x02a8)
++#define    MDNS_ADDR_DEPURPLEPAR3(n)                (MDNS_BASE(n) + 0x02ac)
++#define    MDNS_ADDR_DBGSIG0(n)                (MDNS_BASE(n) + 0x0300)
++#define    MDNS_ADDR_DBGSIG1(n)                (MDNS_BASE(n) + 0x0304)
++#define    MDNS_ADDR_DBGSIG2(n)                (MDNS_BASE(n) + 0x0308)
++#define    MDNS_ADDR_DBGSIG3(n)                (MDNS_BASE(n) + 0x030c)
++#define    MDNS_ADDR_DBGSIG4(n)                (MDNS_BASE(n) + 0x0310)
++#define    MDNS_ADDR_DBGSIG5(n)                (MDNS_BASE(n) + 0x0314)
++#define    MDNS_ADDR_DBGSIG6(n)                (MDNS_BASE(n) + 0x0318)
++#define    MDNS_ADDR_DBGSIG7(n)                (MDNS_BASE(n) + 0x031c)
++#define    MDNS_ADDR_DBGSIG8(n)                (MDNS_BASE(n) + 0x0320)
++#define    MDNS_ADDR_DBGSIG9(n)                (MDNS_BASE(n) + 0x0324)
++#define    MDNS_ADDR_DBGSIG10(n)                (MDNS_BASE(n) + 0x0328)
++#define    MDNS_ADDR_DBGSIG11(n)                (MDNS_BASE(n) + 0x032c)
++#define    MDNS_ADDR_DBGSIG12(n)                (MDNS_BASE(n) + 0x0330)
++#define    MDNS_ADDR_DBGSIG13(n)                (MDNS_BASE(n) + 0x0334)
++#define    MDNS_ADDR_DBGSIG14(n)                (MDNS_BASE(n) + 0x0338)
++#define    MDNS_ADDR_DBGSIG15(n)                (MDNS_BASE(n) + 0x033c)
++#define    MDNS_ADDR_DBGSIG16(n)                (MDNS_BASE(n) + 0x0340)
++#define    MDNS_ADDR_DBGSIG17(n)                (MDNS_BASE(n) + 0x0344)
++#define    MDNS_ADDR_DBGSIG18(n)                (MDNS_BASE(n) + 0x0348)
++#define    MDNS_ADDR_DBGSIG19(n)                (MDNS_BASE(n) + 0x034c)
++#define    MDNS_ADDR_DBGSIG20(n)                (MDNS_BASE(n) + 0x0350)
++#define    MDNS_ADDR_DBGSIG21(n)                (MDNS_BASE(n) + 0x0354)
++#define    MDNS_ADDR_DBGSIG22(n)                (MDNS_BASE(n) + 0x0358)
++#define    MDNS_ADDR_DBGSIG23(n)                (MDNS_BASE(n) + 0x035c)
++#define    MDNS_ADDR_DBGSIG24(n)                (MDNS_BASE(n) + 0x0360)
++#define    MDNS_ADDR_DBGSIG25(n)                (MDNS_BASE(n) + 0x0364)
++#define    MDNS_ADDR_DBGSIG26(n)                (MDNS_BASE(n) + 0x0368)
++#define    MDNS_ADDR_DBGSIG27(n)                (MDNS_BASE(n) + 0x036c)
++#define    MDNS_ADDR_DBGSIG28(n)                (MDNS_BASE(n) + 0x0370)
++#define    MDNS_ADDR_DBGSIG29(n)                (MDNS_BASE(n) + 0x0374)
++#define    MDNS_ADDR_DBGSIG30(n)                (MDNS_BASE(n) + 0x0378)
++#define    MDNS_ADDR_DBGSIG31(n)                (MDNS_BASE(n) + 0x037c)
++#define    MDNS_ADDR_DBGSIG32(n)                (MDNS_BASE(n) + 0x0380)
++#define    MDNS_ADDR_DBGSIG33(n)                (MDNS_BASE(n) + 0x0384)
++#define    MDNS_ADDR_DBGSIG34(n)                (MDNS_BASE(n) + 0x0388)
++#define    MDNS_ADDR_DBGSIG35(n)                (MDNS_BASE(n) + 0x038c)
++#define    MDNS_ADDR_DBGSIG36(n)                (MDNS_BASE(n) + 0x0390)
++#define    MDNS_ADDR_DBGSIG37(n)                (MDNS_BASE(n) + 0x0394)
++#define    MDNS_ADDR_DBGSIG38(n)                (MDNS_BASE(n) + 0x0398)
++#define    MDNS_ADDR_DBGSIG39(n)                (MDNS_BASE(n) + 0x039c)
++#define    MDNS_ADDR_DBGSIG40(n)                (MDNS_BASE(n) + 0x03a0)
++#define    MDNS_ADDR_DBGSIG41(n)                (MDNS_BASE(n) + 0x03a4)
++#define    MDNS_ADDR_DBGSIG42(n)                (MDNS_BASE(n) + 0x03a8)
++#define    MDNS_ADDR_DBGSIG43(n)                (MDNS_BASE(n) + 0x03ac)
++#define    MDNS_ADDR_DBGSIG44(n)                (MDNS_BASE(n) + 0x03b0)
++#define    MDNS_ADDR_DBGSIG45(n)                (MDNS_BASE(n) + 0x03b4)
++#define    MDNS_ADDR_DBGSIG46(n)                (MDNS_BASE(n) + 0x03b8)
++#define    MDNS_ADDR_DBGSIG47(n)                (MDNS_BASE(n) + 0x03bc)
++#define    MDNS_ADDR_DBGSIG48(n)                (MDNS_BASE(n) + 0x03c0)
++#define    MDNS_ADDR_DBGSIG49(n)                (MDNS_BASE(n) + 0x03c4)
++#define    MDNS_ADDR_DBGSIG50(n)                (MDNS_BASE(n) + 0x03c8)
++#define    MDNS_ADDR_DBGSIG51(n)                (MDNS_BASE(n) + 0x03cc)
++#define    MDNS_ADDR_DBGSIG52(n)                (MDNS_BASE(n) + 0x03d0)
++#define    MDNS_ADDR_DBGSIG53(n)                (MDNS_BASE(n) + 0x03d4)
++#define    MDNS_ADDR_DBGSIG54(n)                (MDNS_BASE(n) + 0x03d8)
++#define    MDNS_ADDR_DBGSIG55(n)                (MDNS_BASE(n) + 0x03dc)
++#define    MDNS_ADDR_DBGSIG56(n)                (MDNS_BASE(n) + 0x03e0)
++#define    MDNS_ADDR_DBGSIG57(n)                (MDNS_BASE(n) + 0x03e4)
++#define    MDNS_ADDR_DBGSIG58(n)                (MDNS_BASE(n) + 0x03e8)
++#define    MDNS_ADDR_DBGSIG59(n)                (MDNS_BASE(n) + 0x03ec)
++#define    MDNS_ADDR_DBGSIG60(n)                (MDNS_BASE(n) + 0x03f0)
++#define    MDNS_ADDR_DBGSIG61(n)                (MDNS_BASE(n) + 0x03f4)
++#define    MDNS_ADDR_DBGSIG62(n)                (MDNS_BASE(n) + 0x03f8)
++#define    MDNS_ADDR_DBGSIG63(n)                (MDNS_BASE(n) + 0x03fc)
++#define    MDNS_ADDR_DBGSIG64(n)                (MDNS_BASE(n) + 0x0400)
++#define    MDNS_ADDR_DBGSIG65(n)                (MDNS_BASE(n) + 0x0404)
++#define    MDNS_ADDR_DBGSIG66(n)                (MDNS_BASE(n) + 0x0408)
++#define    MDNS_ADDR_DBGSIG67(n)                (MDNS_BASE(n) + 0x040c)
++
++//============================================================
++// YDNS ADDRESS
++//============================================================
++#define    YDNS_ADDR_VERSION(n)                            (YDNS_BASE(n) + 0x0000)
++#define    YDNS_ADDR_SHD_CTRL(n)                            (YDNS_BASE(n) + 0x0004)
++#define    YDNS_ADDR_OUTSEL(n)                            (YDNS_BASE(n) + 0x0008)
++#define    YDNS_ADDR_MD_EN(n)                            (YDNS_BASE(n) + 0x0010)
++#define    YDNS_ADDR_YEDGEPAR(n)                            (YDNS_BASE(n) + 0x0020)
++#define    YDNS_ADDR_YFUSWEIPAR0(n)                            (YDNS_BASE(n) + 0x0024)
++#define    YDNS_ADDR_YFUSWEIPAR1(n)                            (YDNS_BASE(n) + 0x0028)
++#define    YDNS_ADDR_CIIRPAR(n)                            (YDNS_BASE(n) + 0x0040)
++#define    YDNS_ADDR_CFUSWEIPAR0(n)                            (YDNS_BASE(n) + 0x0044)
++#define    YDNS_ADDR_CFUSWEIPAR1(n)                            (YDNS_BASE(n) + 0x0048)
++#define    YDNS_ADDR_DBGSIG0(n)                            (YDNS_BASE(n) + 0x0060)
++#define    YDNS_ADDR_DBGSIG1(n)                            (YDNS_BASE(n) + 0x0064)
++#define    YDNS_ADDR_DBGSIG2(n)                            (YDNS_BASE(n) + 0x0068)
++#define    YDNS_ADDR_DBGSIG3(n)                            (YDNS_BASE(n) + 0x006c)
++#define    YDNS_ADDR_DBGSIG4(n)                            (YDNS_BASE(n) + 0x0070)
++#define    YDNS_ADDR_DBGSIG5(n)                            (YDNS_BASE(n) + 0x0074)
++#define    YDNS_ADDR_DBGSIG6(n)                            (YDNS_BASE(n) + 0x0078)
++#define    YDNS_ADDR_DBGSIG7(n)                            (YDNS_BASE(n) + 0x007c)
++#define    YDNS_ADDR_DBGSIG8(n)                            (YDNS_BASE(n) + 0x0080)
++
++//============================================================
++// CDNS ADDRESS
++//============================================================
++#define    CDNS_ADDR_VERSION(n)                            (CDNS_BASE(n) + 0x0000)
++#define    CDNS_ADDR_SHD_CTRL(n)                            (CDNS_BASE(n) + 0x0004)
++#define    CDNS_ADDR_OUTSEL(n)                            (CDNS_BASE(n) + 0x0008)
++#define    CDNS_ADDR_STDDIVOPT(n)                            (CDNS_BASE(n) + 0x0010)
++#define    CDNS_ADDR_SPEC0PAR(n)                            (CDNS_BASE(n) + 0x0020)
++#define    CDNS_ADDR_SPEC1PAR(n)                            (CDNS_BASE(n) + 0x0024)
++#define    CDNS_ADDR_SPEC2PAR(n)                            (CDNS_BASE(n) + 0x0028)
++#define    CDNS_ADDR_SPEC3PAR(n)                            (CDNS_BASE(n) + 0x002c)
++#define    CDNS_ADDR_SPEC4PAR(n)                            (CDNS_BASE(n) + 0x0030)
++#define    CDNS_ADDR_SPEC5PAR(n)                            (CDNS_BASE(n) + 0x0034)
++#define    CDNS_ADDR_SPEC6PAR(n)                            (CDNS_BASE(n) + 0x0038)
++#define    CDNS_ADDR_SPEC7PAR(n)                            (CDNS_BASE(n) + 0x003c)
++#define    CDNS_ADDR_IIRWEIGHT(n)                            (CDNS_BASE(n) + 0x0040)
++#define    CDNS_ADDR_FUSWEIGHT(n)                            (CDNS_BASE(n) + 0x0050)
++#define    CDNS_ADDR_DBGSIG0(n)                            (CDNS_BASE(n) + 0x0060)
++#define    CDNS_ADDR_DBGSIG1(n)                            (CDNS_BASE(n) + 0x0064)
++#define    CDNS_ADDR_DBGSIG2(n)                            (CDNS_BASE(n) + 0x0068)
++#define    CDNS_ADDR_DBGSIG3(n)                            (CDNS_BASE(n) + 0x006c)
++#define    CDNS_ADDR_DBGSIG4(n)                            (CDNS_BASE(n) + 0x0070)
++#define    CDNS_ADDR_DBGSIG5(n)                            (CDNS_BASE(n) + 0x0074)
++#define    CDNS_ADDR_DBGSIG6(n)                            (CDNS_BASE(n) + 0x0078)
++
++//============================================================
++// BCSH ADDRESS
++//============================================================
++#define MAIN_BCSH_ADDR_CLIP_Y0_LIMIT                           (BCSH0_BASE + 0x0000)
++#define MAIN_BCSH_ADDR_CLIP_Y1_LIMIT                           (BCSH0_BASE + 0x0004)
++#define MAIN_BCSH_ADDR_CLIP_Y2_LIMIT                           (BCSH0_BASE + 0x0008)
++#define MAIN_BCSH_ADDR_CLIP_C0_LIMIT                           (BCSH0_BASE + 0x000c)
++#define MAIN_BCSH_ADDR_CLIP_C1_LIMIT                           (BCSH0_BASE + 0x0010)
++#define MAIN_BCSH_ADDR_CLIP_C2_LIMIT                           (BCSH0_BASE + 0x0014)
++#define MAIN_BCSH_ADDR_OFFSET_Y                                (BCSH0_BASE + 0x0018)
++#define MAIN_BCSH_ADDR_OFFSET_U                                (BCSH0_BASE + 0x001c)
++#define MAIN_BCSH_ADDR_OFFSET_V                                (BCSH0_BASE + 0x0020)
++#define MAIN_BCSH_ADDR_MATRIX_COEF00                           (BCSH0_BASE + 0x0024)
++#define MAIN_BCSH_ADDR_MATRIX_COEF02                           (BCSH0_BASE + 0x0028)
++#define MAIN_BCSH_ADDR_MATRIX_COEF10                           (BCSH0_BASE + 0x002c)
++#define MAIN_BCSH_ADDR_MATRIX_COEF12                           (BCSH0_BASE + 0x0030)
++#define MAIN_BCSH_ADDR_MATRIX_COEF20                           (BCSH0_BASE + 0x0034)
++#define MAIN_BCSH_ADDR_MATRIX_COEF22                           (BCSH0_BASE + 0x0038)
++#define MAIN_BCSH_ADDR_PRO_DK                                  (BCSH0_BASE + 0x003c)
++#define MAIN_BCSH_ADDR_PRO_DK_TH                               (BCSH0_BASE + 0x0040)
++#define MAIN_BCSH_ADDR_PRO_BR                                  (BCSH0_BASE + 0x0044)
++#define MAIN_BCSH_ADDR_PRO_BR_TH                               (BCSH0_BASE + 0x0048)
++#define MAIN_BCSH_ADDR_PRO_SAT                                 (BCSH0_BASE + 0x004c)
++#define MAIN_BCSH_ADDR_PRO_SAT_TH                              (BCSH0_BASE + 0x0050)
++#define MAIN_BCSH_ADDR_CON_ENABLE                              (BCSH0_BASE + 0x0054)
++#define MAIN_BCSH_ADDR_CON_S1                                  (BCSH0_BASE + 0x0058)
++#define MAIN_BCSH_ADDR_CON_X                                   (BCSH0_BASE + 0x005c)
++#define MAIN_BCSH_ADDR_CON_Y                                   (BCSH0_BASE + 0x0060)
++#define MAIN_BCSH_ADDR_SAT_ENABLE                              (BCSH0_BASE + 0x0064)
++#define MAIN_BCSH_ADDR_SAT_TH                                  (BCSH0_BASE + 0x0068)
++#define MAIN_BCSH_ADDR_SAT_STREN_S                             (BCSH0_BASE + 0x006c)
++#define MAIN_BCSH_ADDR_SAT_STREN_M                             (BCSH0_BASE + 0x0070)
++#define MAIN_BCSH_ADDR_DEBUG_0                                 (BCSH0_BASE + 0x0074)
++#define MAIN_BCSH_ADDR_DEBUG_1                                 (BCSH0_BASE + 0x0078)
++#define MAIN_BCSH_ADDR_DEBUG_2                                 (BCSH0_BASE + 0x007c)
++#define MAIN_BCSH_ADDR_DEBUG_3                                 (BCSH0_BASE + 0x0080)
++#define MAIN_BCSH_ADDR_DEBUG_4                                 (BCSH0_BASE + 0x0084)
++#define MAIN_BCSH_ADDR_DEBUG_5                                 (BCSH0_BASE + 0x0088)
++#define MAIN_BCSH_ADDR_DEBUG_6                                 (BCSH0_BASE + 0x008c)
++#define MAIN_BCSH_ADDR_DEBUG_7                                 (BCSH0_BASE + 0x0090)
++#define MAIN_BCSH_ADDR_DEBUG_8                                 (BCSH0_BASE + 0x0094)
++
++#define SEC_BCSH_ADDR_CLIP_Y0_LIMIT                           (BCSH1_BASE + 0x0000)
++#define SEC_BCSH_ADDR_CLIP_Y1_LIMIT                           (BCSH1_BASE + 0x0004)
++#define SEC_BCSH_ADDR_CLIP_Y2_LIMIT                           (BCSH1_BASE + 0x0008)
++#define SEC_BCSH_ADDR_CLIP_C0_LIMIT                           (BCSH1_BASE + 0x000c)
++#define SEC_BCSH_ADDR_CLIP_C1_LIMIT                           (BCSH1_BASE + 0x0010)
++#define SEC_BCSH_ADDR_CLIP_C2_LIMIT                           (BCSH1_BASE + 0x0014)
++#define SEC_BCSH_ADDR_OFFSET_Y                                (BCSH1_BASE + 0x0018)
++#define SEC_BCSH_ADDR_OFFSET_U                                (BCSH1_BASE + 0x001c)
++#define SEC_BCSH_ADDR_OFFSET_V                                (BCSH1_BASE + 0x0020)
++#define SEC_BCSH_ADDR_MATRIX_COEF00                           (BCSH1_BASE + 0x0024)
++#define SEC_BCSH_ADDR_MATRIX_COEF02                           (BCSH1_BASE + 0x0028)
++#define SEC_BCSH_ADDR_MATRIX_COEF10                           (BCSH1_BASE + 0x002c)
++#define SEC_BCSH_ADDR_MATRIX_COEF12                           (BCSH1_BASE + 0x0030)
++#define SEC_BCSH_ADDR_MATRIX_COEF20                           (BCSH1_BASE + 0x0034)
++#define SEC_BCSH_ADDR_MATRIX_COEF22                           (BCSH1_BASE + 0x0038)
++#define SEC_BCSH_ADDR_PRO_DK                                  (BCSH1_BASE + 0x003c)
++#define SEC_BCSH_ADDR_PRO_DK_TH                               (BCSH1_BASE + 0x0040)
++#define SEC_BCSH_ADDR_PRO_BR                                  (BCSH1_BASE + 0x0044)
++#define SEC_BCSH_ADDR_PRO_BR_TH                               (BCSH1_BASE + 0x0048)
++#define SEC_BCSH_ADDR_PRO_SAT                                 (BCSH1_BASE + 0x004c)
++#define SEC_BCSH_ADDR_PRO_SAT_TH                              (BCSH1_BASE + 0x0050)
++#define SEC_BCSH_ADDR_CON_ENABLE                              (BCSH1_BASE + 0x0054)
++#define SEC_BCSH_ADDR_CON_S1                                  (BCSH1_BASE + 0x0058)
++#define SEC_BCSH_ADDR_CON_X                                   (BCSH1_BASE + 0x005c)
++#define SEC_BCSH_ADDR_CON_Y                                   (BCSH1_BASE + 0x0060)
++#define SEC_BCSH_ADDR_SAT_ENABLE                              (BCSH1_BASE + 0x0064)
++#define SEC_BCSH_ADDR_SAT_TH                                  (BCSH1_BASE + 0x0068)
++#define SEC_BCSH_ADDR_SAT_STREN_S                             (BCSH1_BASE + 0x006c)
++#define SEC_BCSH_ADDR_SAT_STREN_M                             (BCSH1_BASE + 0x0070)
++#define SEC_BCSH_ADDR_DEBUG_0                                 (BCSH1_BASE + 0x0074)
++#define SEC_BCSH_ADDR_DEBUG_1                                 (BCSH1_BASE + 0x0078)
++#define SEC_BCSH_ADDR_DEBUG_2                                 (BCSH1_BASE + 0x007c)
++#define SEC_BCSH_ADDR_DEBUG_3                                 (BCSH1_BASE + 0x0080)
++#define SEC_BCSH_ADDR_DEBUG_4                                 (BCSH1_BASE + 0x0084)
++#define SEC_BCSH_ADDR_DEBUG_5                                 (BCSH1_BASE + 0x0088)
++#define SEC_BCSH_ADDR_DEBUG_6                                 (BCSH1_BASE + 0x008c)
++#define SEC_BCSH_ADDR_DEBUG_7                                 (BCSH1_BASE + 0x0090)
++#define SEC_BCSH_ADDR_DEBUG_8                                 (BCSH1_BASE + 0x0094)
++
++
++//============================================================
++// CLM ADDRESS
++//============================================================
++#define MAIN_CLM_ADDR_SHD_CTRL                                 (CLM0_BASE + 0x0000)
++#define MAIN_CLM_ADDR_LUT_SHIFT                                (CLM0_BASE + 0x0004)
++#define MAIN_CLM_ADDR_CSC_RB                                   (CLM0_BASE + 0x0008)
++#define MAIN_CLM_ADDR_CSC_G                                    (CLM0_BASE + 0x000c)
++#define MAIN_CLM_ADDR_CSC_U                                    (CLM0_BASE + 0x0010)
++#define MAIN_CLM_ADDR_CSC_V                                    (CLM0_BASE + 0x0014)
++#define MAIN_CLM_ADDR_CSC_Y                                    (CLM0_BASE + 0x0018)
++#define MAIN_CLM_ADDR_CA_S_THRES                               (CLM0_BASE + 0x001c)
++#define MAIN_CLM_ADDR_CA_S_SLOPE                               (CLM0_BASE + 0x0020)
++#define MAIN_CLM_ADDR_CA_V_THRES                               (CLM0_BASE + 0x0024)
++#define MAIN_CLM_ADDR_CA_V_SLOPE                               (CLM0_BASE + 0x0028)
++#define MAIN_CLM_ADDR_DEBUG0                                   (CLM0_BASE + 0x002c)
++#define MAIN_CLM_ADDR_DEBUG1                                   (CLM0_BASE + 0x0030)
++#define MAIN_CLM_ADDR_DEBUG2                                   (CLM0_BASE + 0x0034)
++#define MAIN_CLM_ADDR_DEBUG3                                   (CLM0_BASE + 0x0038)
++#define MAIN_CLM_ADDR_DEBUG4                                   (CLM0_BASE + 0x003c)
++#define MAIN_CLM_ADDR_DEBUG5                                   (CLM0_BASE + 0x0040)
++#define MAIN_CLM_ADDR_DEBUG6                                   (CLM0_BASE + 0x0044)
++#define MAIN_CLM_ADDR_DEBUG7                                   (CLM0_BASE + 0x0048)
++
++#define SEC_CLM_ADDR_SHD_CTRL                                 (CLM1_BASE + 0x0000)
++#define SEC_CLM_ADDR_LUT_SHIFT                                (CLM1_BASE + 0x0004)
++#define SEC_CLM_ADDR_CSC_RB                                   (CLM1_BASE + 0x0008)
++#define SEC_CLM_ADDR_CSC_G                                    (CLM1_BASE + 0x000c)
++#define SEC_CLM_ADDR_CSC_U                                    (CLM1_BASE + 0x0010)
++#define SEC_CLM_ADDR_CSC_V                                    (CLM1_BASE + 0x0014)
++#define SEC_CLM_ADDR_CSC_Y                                    (CLM1_BASE + 0x0018)
++#define SEC_CLM_ADDR_CA_S_THRES                               (CLM1_BASE + 0x001c)
++#define SEC_CLM_ADDR_CA_S_SLOPE                               (CLM1_BASE + 0x0020)
++#define SEC_CLM_ADDR_CA_V_THRES                               (CLM1_BASE + 0x0024)
++#define SEC_CLM_ADDR_CA_V_SLOPE                               (CLM1_BASE + 0x0028)
++#define SEC_CLM_ADDR_DEBUG0                                   (CLM1_BASE + 0x002c)
++#define SEC_CLM_ADDR_DEBUG1                                   (CLM1_BASE + 0x0030)
++#define SEC_CLM_ADDR_DEBUG2                                   (CLM1_BASE + 0x0034)
++#define SEC_CLM_ADDR_DEBUG3                                   (CLM1_BASE + 0x0038)
++#define SEC_CLM_ADDR_DEBUG4                                   (CLM1_BASE + 0x003c)
++#define SEC_CLM_ADDR_DEBUG5                                   (CLM1_BASE + 0x0040)
++#define SEC_CLM_ADDR_DEBUG6                                   (CLM1_BASE + 0x0044)
++#define SEC_CLM_ADDR_DEBUG7                                   (CLM1_BASE + 0x0048)
++
++
++//============================================================
++// YSP0 ADDRESS
++//============================================================
++#define    Y_SHARPEN_ADDR_SL_EXP(n)       (Y_SHARPEN_BASE(n) + 0x0000)
++#define    Y_SHARPEN_ADDR_SL_SEL_OPT(n)       (Y_SHARPEN_BASE(n) + 0x0004)
++#define    Y_SHARPEN_ADDR_EDGE_THRES(n)       (Y_SHARPEN_BASE(n) + 0x0008)
++#define    Y_SHARPEN_ADDR_OS_MAX_THRES(n)       (Y_SHARPEN_BASE(n) + 0x000c)
++#define    Y_SHARPEN_ADDR_OS_SUP(n)       (Y_SHARPEN_BASE(n) + 0x0010)
++#define    Y_SHARPEN_ADDR_HV_THRES(n)       (Y_SHARPEN_BASE(n) + 0x0014)
++#define    Y_SHARPEN_ADDR_HV_STREN_T(n)       (Y_SHARPEN_BASE(n) + 0x0018)
++#define    Y_SHARPEN_ADDR_AA_THRES(n)       (Y_SHARPEN_BASE(n) + 0x001c)
++#define    Y_SHARPEN_ADDR_AA_STREN_T(n)       (Y_SHARPEN_BASE(n) + 0x0020)
++#define    Y_SHARPEN_ADDR_HVAA_THRES(n)       (Y_SHARPEN_BASE(n) + 0x0024)
++#define    Y_SHARPEN_ADDR_HVAA_STREN_T(n)       (Y_SHARPEN_BASE(n) + 0x0028)
++#define    Y_SHARPEN_ADDR_THRES(n)       (Y_SHARPEN_BASE(n) + 0x002c)
++#define    Y_SHARPEN_ADDR_V1(n)       (Y_SHARPEN_BASE(n) + 0x0030)
++#define    Y_SHARPEN_ADDR_V2(n)       (Y_SHARPEN_BASE(n) + 0x0034)
++#define    Y_SHARPEN_ADDR_DNS_OPT(n)       (Y_SHARPEN_BASE(n) + 0x0038)
++#define    Y_SHARPEN_ADDR_D_0(n)       (Y_SHARPEN_BASE(n) + 0x003c)
++#define    Y_SHARPEN_ADDR_D_1(n)       (Y_SHARPEN_BASE(n) + 0x0040)
++#define    Y_SHARPEN_ADDR_D_2(n)       (Y_SHARPEN_BASE(n) + 0x0044)
++#define    Y_SHARPEN_ADDR_D_3(n)       (Y_SHARPEN_BASE(n) + 0x0048)
++#define    Y_SHARPEN_ADDR_UD_1(n)       (Y_SHARPEN_BASE(n) + 0x004c)
++#define    Y_SHARPEN_ADDR_UD_2(n)       (Y_SHARPEN_BASE(n) + 0x0050)
++#define    Y_SHARPEN_ADDR_UD_3(n)       (Y_SHARPEN_BASE(n) + 0x0054)
++#define    Y_SHARPEN_ADDR_DEBUG0(n)       (Y_SHARPEN_BASE(n) + 0x0058)
++#define    Y_SHARPEN_ADDR_DEBUG1(n)       (Y_SHARPEN_BASE(n) + 0x005c)
++#define    Y_SHARPEN_ADDR_DEBUG2(n)       (Y_SHARPEN_BASE(n) + 0x0060)
++#define    Y_SHARPEN_ADDR_DEBUG3(n)       (Y_SHARPEN_BASE(n) + 0x0064)
++#define    Y_SHARPEN_ADDR_DEBUG4(n)       (Y_SHARPEN_BASE(n) + 0x0068)
++#define    Y_SHARPEN_ADDR_DEBUG5(n)       (Y_SHARPEN_BASE(n) + 0x006c)
++#define    Y_SHARPEN_ADDR_DEBUG6(n)       (Y_SHARPEN_BASE(n) + 0x0070)
++#define    Y_SHARPEN_ADDR_DEBUG7(n)       (Y_SHARPEN_BASE(n) + 0x0074)
++#define    Y_SHARPEN_ADDR_SHD_CTRL(n)       (Y_SHARPEN_BASE(n) + 0x0078)
++#define    Y_SHARPEN_ADDR_UV_EDGE(n)       (Y_SHARPEN_BASE(n) + 0x007c)
++#define    Y_SHARPEN_ADDR_DNS_THRES_0_SL__03_00(n)       (Y_SHARPEN_BASE(n) + 0x0080)
++#define    Y_SHARPEN_ADDR_DNS_THRES_0_SL__07_04(n)       (Y_SHARPEN_BASE(n) + 0x0084)
++#define    Y_SHARPEN_ADDR_DNS_STREN_0_SL__03_00(n)       (Y_SHARPEN_BASE(n) + 0x0088)
++#define    Y_SHARPEN_ADDR_DNS_STREN_0_SL__07_04(n)       (Y_SHARPEN_BASE(n) + 0x008c)
++#define    Y_SHARPEN_ADDR_DNS_THRES_1_SL__03_00(n)       (Y_SHARPEN_BASE(n) + 0x0090)
++#define    Y_SHARPEN_ADDR_DNS_THRES_1_SL__07_04(n)       (Y_SHARPEN_BASE(n) + 0x0094)
++#define    Y_SHARPEN_ADDR_DNS_STREN_1_SL__03_00(n)       (Y_SHARPEN_BASE(n) + 0x0098)
++#define    Y_SHARPEN_ADDR_DNS_STREN_1_SL__07_04(n)       (Y_SHARPEN_BASE(n) + 0x009c)
++#define    Y_SHARPEN_ADDR_DNS_STREN_2_SL__03_00(n)       (Y_SHARPEN_BASE(n) + 0x00a0)
++#define    Y_SHARPEN_ADDR_DNS_STREN_2_SL__07_04(n)       (Y_SHARPEN_BASE(n) + 0x00a4)
++#define    Y_SHARPEN_ADDR_UU_NP__03_00(n)       (Y_SHARPEN_BASE(n) + 0x00a8)
++#define    Y_SHARPEN_ADDR_UU_NP__07_04(n)       (Y_SHARPEN_BASE(n) + 0x00ac)
++#define    Y_SHARPEN_ADDR_UU_NP__11_08(n)       (Y_SHARPEN_BASE(n) + 0x00b0)
++#define    Y_SHARPEN_ADDR_UU_NP__15_12(n)       (Y_SHARPEN_BASE(n) + 0x00b4)
++#define    Y_SHARPEN_ADDR_D_UU_THRES_SL__01_00(n)       (Y_SHARPEN_BASE(n) + 0x00b8)
++#define    Y_SHARPEN_ADDR_D_UU_THRES_SL__03_02(n)       (Y_SHARPEN_BASE(n) + 0x00bc)
++#define    Y_SHARPEN_ADDR_D_UU_THRES_SL__05_04(n)       (Y_SHARPEN_BASE(n) + 0x00c0)
++#define    Y_SHARPEN_ADDR_D_UU_THRES_SL__07_06(n)       (Y_SHARPEN_BASE(n) + 0x00c4)
++#define    Y_SHARPEN_ADDR_D_WEI_NP__03_00(n)       (Y_SHARPEN_BASE(n) + 0x00c8)
++#define    Y_SHARPEN_ADDR_D_WEI_NP__07_04(n)       (Y_SHARPEN_BASE(n) + 0x00cc)
++#define    Y_SHARPEN_ADDR_D_WEI_NP__11_08(n)       (Y_SHARPEN_BASE(n) + 0x00d0)
++#define    Y_SHARPEN_ADDR_D_WEI_NP__15_12(n)       (Y_SHARPEN_BASE(n) + 0x00d4)
++#define    Y_SHARPEN_ADDR_D_WEI_NP__19_16(n)       (Y_SHARPEN_BASE(n) + 0x00d8)
++#define    Y_SHARPEN_ADDR_D_WEI_NP__23_20(n)       (Y_SHARPEN_BASE(n) + 0x00dc)
++#define    Y_SHARPEN_ADDR_D_WEI_NP__27_24(n)       (Y_SHARPEN_BASE(n) + 0x00e0)
++#define    Y_SHARPEN_ADDR_D_WEI_NP__31_28(n)       (Y_SHARPEN_BASE(n) + 0x00e4)
++#define    Y_SHARPEN_ADDR_D_LL_THRES_SL__03_00(n)       (Y_SHARPEN_BASE(n) + 0x00e8)
++#define    Y_SHARPEN_ADDR_D_LL_THRES_SL__07_04(n)       (Y_SHARPEN_BASE(n) + 0x00ec)
++#define    Y_SHARPEN_ADDR_D_LL_STREN_SL__01_00(n)       (Y_SHARPEN_BASE(n) + 0x00f0)
++#define    Y_SHARPEN_ADDR_D_LL_STREN_SL__03_02(n)       (Y_SHARPEN_BASE(n) + 0x00f4)
++#define    Y_SHARPEN_ADDR_D_LL_STREN_SL__05_04(n)       (Y_SHARPEN_BASE(n) + 0x00f8)
++#define    Y_SHARPEN_ADDR_D_LL_STREN_SL__07_06(n)       (Y_SHARPEN_BASE(n) + 0x00fc)
++#define    Y_SHARPEN_ADDR_D_HL_THRES_SL__03_00(n)       (Y_SHARPEN_BASE(n) + 0x0100)
++#define    Y_SHARPEN_ADDR_D_HL_THRES_SL__07_04(n)       (Y_SHARPEN_BASE(n) + 0x0104)
++#define    Y_SHARPEN_ADDR_D_HL_STREN_SL__01_00(n)       (Y_SHARPEN_BASE(n) + 0x0108)
++#define    Y_SHARPEN_ADDR_D_HL_STREN_SL__03_02(n)       (Y_SHARPEN_BASE(n) + 0x010c)
++#define    Y_SHARPEN_ADDR_D_HL_STREN_SL__05_04(n)       (Y_SHARPEN_BASE(n) + 0x0110)
++#define    Y_SHARPEN_ADDR_D_HL_STREN_SL__07_06(n)       (Y_SHARPEN_BASE(n) + 0x0114)
++#define    Y_SHARPEN_ADDR_UD_UU_THRES_SL__01_00(n)       (Y_SHARPEN_BASE(n) + 0x0118)
++#define    Y_SHARPEN_ADDR_UD_UU_THRES_SL__03_02(n)       (Y_SHARPEN_BASE(n) + 0x011c)
++#define    Y_SHARPEN_ADDR_UD_UU_THRES_SL__05_04(n)       (Y_SHARPEN_BASE(n) + 0x0120)
++#define    Y_SHARPEN_ADDR_UD_UU_THRES_SL__07_06(n)       (Y_SHARPEN_BASE(n) + 0x0124)
++#define    Y_SHARPEN_ADDR_UD_WEI_NP__03_00(n)       (Y_SHARPEN_BASE(n) + 0x0128)
++#define    Y_SHARPEN_ADDR_UD_WEI_NP__07_04(n)       (Y_SHARPEN_BASE(n) + 0x012c)
++#define    Y_SHARPEN_ADDR_UD_WEI_NP__11_08(n)       (Y_SHARPEN_BASE(n) + 0x0130)
++#define    Y_SHARPEN_ADDR_UD_WEI_NP__15_12(n)       (Y_SHARPEN_BASE(n) + 0x0134)
++#define    Y_SHARPEN_ADDR_UD_WEI_NP__19_16(n)       (Y_SHARPEN_BASE(n) + 0x0138)
++#define    Y_SHARPEN_ADDR_UD_WEI_NP__23_20(n)       (Y_SHARPEN_BASE(n) + 0x013c)
++#define    Y_SHARPEN_ADDR_UD_WEI_NP__27_24(n)       (Y_SHARPEN_BASE(n) + 0x0140)
++#define    Y_SHARPEN_ADDR_UD_WEI_NP__31_28(n)       (Y_SHARPEN_BASE(n) + 0x0144)
++#define    Y_SHARPEN_ADDR_UD_LL_THRES_SL__03_00(n)       (Y_SHARPEN_BASE(n) + 0x0148)
++#define    Y_SHARPEN_ADDR_UD_LL_THRES_SL__07_04(n)       (Y_SHARPEN_BASE(n) + 0x014c)
++#define    Y_SHARPEN_ADDR_UD_LL_STREN_SL__01_00(n)       (Y_SHARPEN_BASE(n) + 0x0150)
++#define    Y_SHARPEN_ADDR_UD_LL_STREN_SL__03_02(n)       (Y_SHARPEN_BASE(n) + 0x0154)
++#define    Y_SHARPEN_ADDR_UD_LL_STREN_SL__05_04(n)       (Y_SHARPEN_BASE(n) + 0x0158)
++#define    Y_SHARPEN_ADDR_UD_LL_STREN_SL__07_06(n)       (Y_SHARPEN_BASE(n) + 0x015c)
++#define    Y_SHARPEN_ADDR_UD_HL_THRES_SL__03_00(n)       (Y_SHARPEN_BASE(n) + 0x0160)
++#define    Y_SHARPEN_ADDR_UD_HL_THRES_SL__07_04(n)       (Y_SHARPEN_BASE(n) + 0x0164)
++#define    Y_SHARPEN_ADDR_UD_HL_STREN_SL__01_00(n)       (Y_SHARPEN_BASE(n) + 0x0168)
++#define    Y_SHARPEN_ADDR_UD_HL_STREN_SL__03_02(n)       (Y_SHARPEN_BASE(n) + 0x016c)
++#define    Y_SHARPEN_ADDR_UD_HL_STREN_SL__05_04(n)       (Y_SHARPEN_BASE(n) + 0x0170)
++#define    Y_SHARPEN_ADDR_UD_HL_STREN_SL__07_06(n)       (Y_SHARPEN_BASE(n) + 0x0174)
++#define    Y_SHARPEN_ADDR_D_UU_STREN_SL__01_00(n)       (Y_SHARPEN_BASE(n) + 0x0178)
++#define    Y_SHARPEN_ADDR_D_UU_STREN_SL__03_02(n)       (Y_SHARPEN_BASE(n) + 0x017c)
++#define    Y_SHARPEN_ADDR_D_UU_STREN_SL__05_04(n)       (Y_SHARPEN_BASE(n) + 0x0180)
++#define    Y_SHARPEN_ADDR_D_UU_STREN_SL__07_06(n)       (Y_SHARPEN_BASE(n) + 0x0184)
++#define    Y_SHARPEN_ADDR_D_W_SP_STREN_SL__01_00(n)       (Y_SHARPEN_BASE(n) + 0x0188)
++#define    Y_SHARPEN_ADDR_D_W_SP_STREN_SL__03_02(n)       (Y_SHARPEN_BASE(n) + 0x018c)
++#define    Y_SHARPEN_ADDR_D_W_SP_STREN_SL__05_04(n)       (Y_SHARPEN_BASE(n) + 0x0190)
++#define    Y_SHARPEN_ADDR_D_W_SP_STREN_SL__07_06(n)       (Y_SHARPEN_BASE(n) + 0x0194)
++#define    Y_SHARPEN_ADDR_D_B_SP_STREN_SL__01_00(n)       (Y_SHARPEN_BASE(n) + 0x0198)
++#define    Y_SHARPEN_ADDR_D_B_SP_STREN_SL__03_02(n)       (Y_SHARPEN_BASE(n) + 0x019c)
++#define    Y_SHARPEN_ADDR_D_B_SP_STREN_SL__05_04(n)       (Y_SHARPEN_BASE(n) + 0x01a0)
++#define    Y_SHARPEN_ADDR_D_B_SP_STREN_SL__07_06(n)       (Y_SHARPEN_BASE(n) + 0x01a4)
++#define    Y_SHARPEN_ADDR_UD_UU_STREN_SL__01_00(n)       (Y_SHARPEN_BASE(n) + 0x01a8)
++#define    Y_SHARPEN_ADDR_UD_UU_STREN_SL__03_02(n)       (Y_SHARPEN_BASE(n) + 0x01ac)
++#define    Y_SHARPEN_ADDR_UD_UU_STREN_SL__05_04(n)       (Y_SHARPEN_BASE(n) + 0x01b0)
++#define    Y_SHARPEN_ADDR_UD_UU_STREN_SL__07_06(n)       (Y_SHARPEN_BASE(n) + 0x01b4)
++#define    Y_SHARPEN_ADDR_UD_W_SP_STREN_SL__01_00(n)       (Y_SHARPEN_BASE(n) + 0x01b8)
++#define    Y_SHARPEN_ADDR_UD_W_SP_STREN_SL__03_02(n)       (Y_SHARPEN_BASE(n) + 0x01bc)
++#define    Y_SHARPEN_ADDR_UD_W_SP_STREN_SL__05_04(n)       (Y_SHARPEN_BASE(n) + 0x01c0)
++#define    Y_SHARPEN_ADDR_UD_W_SP_STREN_SL__07_06(n)       (Y_SHARPEN_BASE(n) + 0x01c4)
++#define    Y_SHARPEN_ADDR_UD_B_SP_STREN_SL__01_00(n)       (Y_SHARPEN_BASE(n) + 0x01c8)
++#define    Y_SHARPEN_ADDR_UD_B_SP_STREN_SL__03_02(n)       (Y_SHARPEN_BASE(n) + 0x01cc)
++#define    Y_SHARPEN_ADDR_UD_B_SP_STREN_SL__05_04(n)       (Y_SHARPEN_BASE(n) + 0x01d0)
++#define    Y_SHARPEN_ADDR_UD_B_SP_STREN_SL__07_06(n)       (Y_SHARPEN_BASE(n) + 0x01d4)
++#define    Y_SHARPEN_ADDR_FLAT_SLOPE(n)       (Y_SHARPEN_BASE(n) + 0x01d8)
++#define    Y_SHARPEN_ADDR_LAP_3_0(n)       (Y_SHARPEN_BASE(n) + 0x01dc)
++#define    Y_SHARPEN_ADDR_LAP_3_1(n)       (Y_SHARPEN_BASE(n) + 0x01e0)
++#define    Y_SHARPEN_ADDR_LAP_3_2(n)       (Y_SHARPEN_BASE(n) + 0x01e4)
++
++//============================================================
++// SDNS ADDRESS main
++//============================================================
++#define    SDNS_ADDR_ABCD_SEG_OPT(n)        (SDNS_BASE(n) + 0x0000)
++#define    SDNS_ADDR_STD_THR(n)        (SDNS_BASE(n) + 0x0004)
++#define    SDNS_ADDR_GRAD_ZXY_THRES(n)        (SDNS_BASE(n) + 0x000c)
++#define    SDNS_ADDR_MMEM_YB_THRES(n)        (SDNS_BASE(n) + 0x0010)
++#define    SDNS_ADDR_DIFF_R_STD_OUT_VAL_THRES(n)        (SDNS_BASE(n) + 0x0014)
++#define    SDNS_ADDR_H_VAL_MAX(n)        (SDNS_BASE(n) + 0x0018)
++#define    SDNS_ADDR_MV_INFOR_THRES(n)        (SDNS_BASE(n) + 0x001c)
++#define    SDNS_ADDR_HLS_EN(n)        (SDNS_BASE(n) + 0x0020)
++#define    SDNS_ADDR_AVE_SEG_OPT_EN(n)        (SDNS_BASE(n) + 0x0024)
++#define    SDNS_ADDR_AVE_SEG_OPT_THRES(n)        (SDNS_BASE(n) + 0x0028)
++#define    SDNS_ADDR_AVE_SEG_OPT(n)        (SDNS_BASE(n) + 0x002c)
++#define    SDNS_ADDR_AVE_SLOPE(n)        (SDNS_BASE(n) + 0x0030)
++#define    SDNS_ADDR_ROW_COPY_OPT(n)        (SDNS_BASE(n) + 0x0034)
++#define    SDNS_ADDR_ROW_STDAVE_THRES(n)        (SDNS_BASE(n) + 0x0038)
++#define    SDNS_ADDR_STA_STD_EN(n)        (SDNS_BASE(n) + 0x003c)
++#define    SDNS_ADDR_STA_COUNT_THRES(n)        (SDNS_BASE(n) + 0x0040)
++#define    SDNS_ADDR_DEBUG_0(n)        (SDNS_BASE(n) + 0x0044)
++#define    SDNS_ADDR_DEBUG_1(n)        (SDNS_BASE(n) + 0x0048)
++#define    SDNS_ADDR_DEBUG_2(n)        (SDNS_BASE(n) + 0x004c)
++#define    SDNS_ADDR_DEBUG_3(n)        (SDNS_BASE(n) + 0x0050)
++#define    SDNS_ADDR_SHD_CTRL(n)        (SDNS_BASE(n) + 0x0054)
++#define    SDNS_ADDR_DMAO_CFG(n)        (SDNS_BASE(n) + 0x0058)
++#define    SDNS_ADDR_DMAO_ADDR_0(n)        (SDNS_BASE(n) + 0x005c)
++#define    SDNS_ADDR_DMAO_ADDR_1(n)        (SDNS_BASE(n) + 0x0060)
++#define    SDNS_ADDR_DMAO_ADDR_2(n)        (SDNS_BASE(n) + 0x0064)
++#define    SDNS_ADDR_DMAO_ADDR_3(n)        (SDNS_BASE(n) + 0x0068)
++#define    SDNS_ADDR_DMAO_CUR_ADDR(n)        (SDNS_BASE(n) + 0x006c)
++#define    SDNS_ADDR_DMAI_CFG(n)        (SDNS_BASE(n) + 0x0070)
++#define    SDNS_ADDR_DMAI_ADDR_0(n)        (SDNS_BASE(n) + 0x0074)
++#define    SDNS_ADDR_DMAI_ADDR_1(n)        (SDNS_BASE(n) + 0x0078)
++#define    SDNS_ADDR_DMAI_ADDR_2(n)        (SDNS_BASE(n) + 0x007c)
++#define    SDNS_ADDR_DMAI_ADDR_3(n)        (SDNS_BASE(n) + 0x0080)
++#define    SDNS_ADDR_FRST_FRM_FLAG(n)        (SDNS_BASE(n) + 0x0084)
++#define    SDNS_ADDR_STA_STD_OPT(n)        (SDNS_BASE(n) + 0x0088)
++#define    SDNS_ADDR_G_DET_VAL(n)        (SDNS_BASE(n) + 0x008c)
++#define    SDNS_ADDR_HOR_VER_T01_THRES(n)        (SDNS_BASE(n) + 0x0090)
++#define    SDNS_ADDR_H_VAL_MAX_LIGHT(n)        (SDNS_BASE(n) + 0x0094)
++#define    SDNS_ADDR_SP_LIMIT(n)        (SDNS_BASE(n) + 0x0098)
++#define    SDNS_ADDR_SP_LL_THRES(n)        (SDNS_BASE(n) + 0x009c)
++#define    SDNS_ADDR_R_S_01_00(n)        (SDNS_BASE(n) + 0x0100)
++#define    SDNS_ADDR_R_S_03_02(n)        (SDNS_BASE(n) + 0x0104)
++#define    SDNS_ADDR_R_S_05_04(n)        (SDNS_BASE(n) + 0x0108)
++#define    SDNS_ADDR_R_S_07_06(n)        (SDNS_BASE(n) + 0x010c)
++#define    SDNS_ADDR_R_S_09_08(n)        (SDNS_BASE(n) + 0x0110)
++#define    SDNS_ADDR_R_S_11_10(n)        (SDNS_BASE(n) + 0x0114)
++#define    SDNS_ADDR_R_S_13_12(n)        (SDNS_BASE(n) + 0x0118)
++#define    SDNS_ADDR_R_S_14_14(n)        (SDNS_BASE(n) + 0x011c)
++#define    SDNS_ADDR_R_MV_01_00(n)        (SDNS_BASE(n) + 0x0120)
++#define    SDNS_ADDR_R_MV_03_02(n)        (SDNS_BASE(n) + 0x0124)
++#define    SDNS_ADDR_R_MV_05_04(n)        (SDNS_BASE(n) + 0x0128)
++#define    SDNS_ADDR_R_MV_07_06(n)        (SDNS_BASE(n) + 0x012c)
++#define    SDNS_ADDR_R_MV_09_08(n)        (SDNS_BASE(n) + 0x0130)
++#define    SDNS_ADDR_R_MV_11_10(n)        (SDNS_BASE(n) + 0x0134)
++#define    SDNS_ADDR_R_MV_13_12(n)        (SDNS_BASE(n) + 0x0138)
++#define    SDNS_ADDR_R_MV_14_14(n)        (SDNS_BASE(n) + 0x013c)
++#define    SDNS_ADDR_H_S_03_00(n)        (SDNS_BASE(n) + 0x0140)
++#define    SDNS_ADDR_H_S_07_04(n)        (SDNS_BASE(n) + 0x0144)
++#define    SDNS_ADDR_H_S_11_08(n)        (SDNS_BASE(n) + 0x0148)
++#define    SDNS_ADDR_H_S_15_12(n)        (SDNS_BASE(n) + 0x014c)
++#define    SDNS_ADDR_H_MV_03_00(n)        (SDNS_BASE(n) + 0x0150)
++#define    SDNS_ADDR_H_MV_07_04(n)        (SDNS_BASE(n) + 0x0154)
++#define    SDNS_ADDR_H_MV_11_08(n)        (SDNS_BASE(n) + 0x0158)
++#define    SDNS_ADDR_H_MV_15_12(n)        (SDNS_BASE(n) + 0x015c)
++#define    SDNS_ADDR_BLOCK_R_S_03_00(n)        (SDNS_BASE(n) + 0x0160)
++#define    SDNS_ADDR_BLOCK_R_S_07_04(n)        (SDNS_BASE(n) + 0x0164)
++#define    SDNS_ADDR_BLOCK_R_S_10_08(n)        (SDNS_BASE(n) + 0x0168)
++#define    SDNS_ADDR_BLOCK_H_S_03_00(n)        (SDNS_BASE(n) + 0x016c)
++#define    SDNS_ADDR_BLOCK_H_S_07_04(n)        (SDNS_BASE(n) + 0x0170)
++#define    SDNS_ADDR_BLOCK_H_S_11_08(n)        (SDNS_BASE(n) + 0x0174)
++#define    SDNS_ADDR_TT_OPT_THRES_01_00(n)        (SDNS_BASE(n) + 0x0178)
++#define    SDNS_ADDR_TT_OPT_THRES_03_02(n)        (SDNS_BASE(n) + 0x017c)
++#define    SDNS_ADDR_TT_OPT_THRES_05_04(n)        (SDNS_BASE(n) + 0x0180)
++#define    SDNS_ADDR_D_S1_THR_01_00(n)        (SDNS_BASE(n) + 0x0184)
++#define    SDNS_ADDR_D_S1_THR_03_02(n)        (SDNS_BASE(n) + 0x0188)
++#define    SDNS_ADDR_D_S1_THR_05_04(n)        (SDNS_BASE(n) + 0x018c)
++#define    SDNS_ADDR_D_S1_THR_06_06(n)        (SDNS_BASE(n) + 0x0190)
++#define    SDNS_ADDR_W_THR_03_00(n)        (SDNS_BASE(n) + 0x0194)
++#define    SDNS_ADDR_W_THR_07_04(n)        (SDNS_BASE(n) + 0x0198)
++#define    SDNS_ADDR_H_MV_WEI_03_00(n)        (SDNS_BASE(n) + 0x019c)
++#define    SDNS_ADDR_H_MV_WEI_07_04(n)        (SDNS_BASE(n) + 0x01a0)
++#define    SDNS_ADDR_DARK_THRES_03_00(n)        (SDNS_BASE(n) + 0x01a4)
++#define    SDNS_ADDR_DARK_THRES_07_04(n)        (SDNS_BASE(n) + 0x01a8)
++#define    SDNS_ADDR_LIGHT_THRES_03_00(n)        (SDNS_BASE(n) + 0x01ac)
++#define    SDNS_ADDR_LIGHT_THRES_07_04(n)        (SDNS_BASE(n) + 0x01b0)
++#define    SDNS_ADDR_SP_UU_THRES_01_00(n)        (SDNS_BASE(n) + 0x01b4)
++#define    SDNS_ADDR_SP_UU_THRES_03_02(n)        (SDNS_BASE(n) + 0x01b8)
++#define    SDNS_ADDR_SP_UU_THRES_05_04(n)        (SDNS_BASE(n) + 0x01bc)
++#define    SDNS_ADDR_SP_UU_THRES_07_06(n)        (SDNS_BASE(n) + 0x01c0)
++#define    SDNS_ADDR_SP_UU_STREN_01_00(n)        (SDNS_BASE(n) + 0x01c4)
++#define    SDNS_ADDR_SP_UU_STREN_03_02(n)        (SDNS_BASE(n) + 0x01c8)
++#define    SDNS_ADDR_SP_UU_STREN_05_04(n)        (SDNS_BASE(n) + 0x01cc)
++#define    SDNS_ADDR_SP_UU_STREN_07_06(n)        (SDNS_BASE(n) + 0x01d0)
++#define    SDNS_ADDR_SP_WEI_NP_ARRAY_03_00(n)        (SDNS_BASE(n) + 0x01d4)
++#define    SDNS_ADDR_SP_WEI_NP_ARRAY_07_04(n)        (SDNS_BASE(n) + 0x01d8)
++#define    SDNS_ADDR_SP_WEI_NP_ARRAY_11_08(n)        (SDNS_BASE(n) + 0x01dc)
++#define    SDNS_ADDR_SP_WEI_NP_ARRAY_15_12(n)        (SDNS_BASE(n) + 0x01e0)
++#define    SDNS_ADDR_SP_WEI_NP_ARRAY_19_16(n)        (SDNS_BASE(n) + 0x01e4)
++#define    SDNS_ADDR_SP_WEI_NP_ARRAY_23_20(n)        (SDNS_BASE(n) + 0x01e8)
++#define    SDNS_ADDR_SP_WEI_NP_ARRAY_27_24(n)        (SDNS_BASE(n) + 0x01ec)
++#define    SDNS_ADDR_SP_WEI_NP_ARRAY_31_28(n)        (SDNS_BASE(n) + 0x01f0)
++#define    SDNS_ADDR_SP_W_STREN_03_00(n)        (SDNS_BASE(n) + 0x01f4)
++#define    SDNS_ADDR_SP_W_STREN_07_04(n)        (SDNS_BASE(n) + 0x01f8)
++#define    SDNS_ADDR_SP_B_STREN_03_00(n)        (SDNS_BASE(n) + 0x01fc)
++#define    SDNS_ADDR_SP_B_STREN_07_04(n)        (SDNS_BASE(n) + 0x0200)
++
++//============================================================
++// YSP1 ADDRESS
++//============================================================
++#define    YSP1_BASE1                                               YSP1_BASE + 0x0200
++#define    MAIN_YSP1_ADDR_SL_EXP                                   (YSP1_BASE + 0x0000)
++#define    MAIN_YSP1_ADDR_SL_SEL_OPT                               (YSP1_BASE + 0x0004)
++#define    MAIN_YSP1_ADDR_EDGE_THRES                               (YSP1_BASE + 0x0008)
++#define    MAIN_YSP1_ADDR_EDGE_MAX_THRES                           (YSP1_BASE + 0x000c)
++#define    MAIN_YSP1_ADDR_EDGE_SCALE_OPT                           (YSP1_BASE + 0x0010)
++#define    MAIN_YSP1_ADDR_OS_0                                     (YSP1_BASE + 0x0014)
++#define    MAIN_YSP1_ADDR_OS_1                                     (YSP1_BASE + 0x0018)
++#define    MAIN_YSP1_ADDR_OS_2                                     (YSP1_BASE + 0x001c)
++#define    MAIN_YSP1_ADDR_OS_3                                     (YSP1_BASE + 0x0020)
++#define    MAIN_YSP1_ADDR_V1                                       (YSP1_BASE + 0x0024)
++#define    MAIN_YSP1_ADDR_V2                                       (YSP1_BASE + 0x0028)
++#define    MAIN_YSP1_ADDR_DNS_0                                    (YSP1_BASE + 0x002c)
++#define    MAIN_YSP1_ADDR_DNS_1                                    (YSP1_BASE + 0x0030)
++#define    MAIN_YSP1_ADDR_DNS_2                                    (YSP1_BASE + 0x0034)
++#define    MAIN_YSP1_ADDR_DNS_3                                    (YSP1_BASE + 0x0038)
++#define    MAIN_YSP1_ADDR_DNS_4                                    (YSP1_BASE + 0x003c)
++#define    MAIN_YSP1_ADDR_DNS_5                                    (YSP1_BASE + 0x0040)
++#define    MAIN_YSP1_ADDR_DIR_0                                    (YSP1_BASE + 0x0044)
++#define    MAIN_YSP1_ADDR_DIR_1                                    (YSP1_BASE + 0x0048)
++#define    MAIN_YSP1_ADDR_UU_0                                     (YSP1_BASE + 0x004c)
++#define    MAIN_YSP1_ADDR_UU_1                                     (YSP1_BASE + 0x0050)
++#define    MAIN_YSP1_ADDR_LL                                       (YSP1_BASE + 0x0054)
++#define    MAIN_YSP1_ADDR_HL                                       (YSP1_BASE + 0x0058)
++#define    MAIN_YSP1_ADDR_W_WEI                                    (YSP1_BASE + 0x005c)
++#define    MAIN_YSP1_ADDR_DIR_0_0                                  (YSP1_BASE + 0x0060)
++#define    MAIN_YSP1_ADDR_DIR_1_1                                  (YSP1_BASE + 0x0064)
++#define    MAIN_YSP1_ADDR_DIR_2                                    (YSP1_BASE + 0x0068)
++#define    MAIN_YSP1_ADDR_UDIR_0                                   (YSP1_BASE + 0x006c)
++#define    MAIN_YSP1_ADDR_UDIR_1                                   (YSP1_BASE + 0x0070)
++#define    MAIN_YSP1_ADDR_DETAIL_0                                 (YSP1_BASE + 0x0074)
++#define    MAIN_YSP1_ADDR_DETAIL_1                                 (YSP1_BASE + 0x0078)
++#define    MAIN_YSP1_ADDR_DETAIL_2                                 (YSP1_BASE + 0x007c)
++#define    MAIN_YSP1_ADDR_DEBUG0                                   (YSP0_BASE + 0x0080)
++#define    MAIN_YSP1_ADDR_DEBUG1                                   (YSP0_BASE + 0x0084)
++#define    MAIN_YSP1_ADDR_SHD_CTRL                                 (YSP1_BASE + 0x0088)
++#define    MAIN_YSP1_ADDR_UU_NP_ARRAY_03_00                        (YSP1_BASE + 0x008c)
++#define    MAIN_YSP1_ADDR_UU_NP_ARRAY_07_04                        (YSP1_BASE + 0x0090)
++#define    MAIN_YSP1_ADDR_UU_NP_ARRAY_11_08                        (YSP1_BASE + 0x0094)
++#define    MAIN_YSP1_ADDR_UU_NP_ARRAY_15_12                        (YSP1_BASE + 0x0098)
++#define    MAIN_YSP1_ADDR_W_WEI_NP_ARRAY_03_00                     (YSP1_BASE + 0x009c)
++#define    MAIN_YSP1_ADDR_W_WEI_NP_ARRAY_07_04                     (YSP1_BASE + 0x00a0)
++#define    MAIN_YSP1_ADDR_W_WEI_NP_ARRAY_11_08                     (YSP1_BASE + 0x00a4)
++#define    MAIN_YSP1_ADDR_W_WEI_NP_ARRAY_15_12                     (YSP1_BASE + 0x00a8)
++#define    MAIN_YSP1_ADDR_B_WEI_NP_ARRAY_03_00                     (YSP1_BASE + 0x00ac)
++#define    MAIN_YSP1_ADDR_B_WEI_NP_ARRAY_07_04                     (YSP1_BASE + 0x00b0)
++#define    MAIN_YSP1_ADDR_B_WEI_NP_ARRAY_11_08                     (YSP1_BASE + 0x00b4)
++#define    MAIN_YSP1_ADDR_B_WEI_NP_ARRAY_15_12                     (YSP1_BASE + 0x00b8)
++#define    MAIN_YSP1_ADDR_DNS_THRES_0_SL_ARRAY_03_00               (YSP1_BASE + 0x00bc)
++#define    MAIN_YSP1_ADDR_DNS_THRES_0_SL_ARRAY_07_04               (YSP1_BASE + 0x00c0)
++#define    MAIN_YSP1_ADDR_DNS_STREN_0_SL_ARRAY_03_00               (YSP1_BASE + 0x00c4)
++#define    MAIN_YSP1_ADDR_DNS_STREN_0_SL_ARRAY_07_04               (YSP1_BASE + 0x00c8)
++#define    MAIN_YSP1_ADDR_DNS_THRES_1_SL_ARRAY_03_00               (YSP1_BASE + 0x00cc)
++#define    MAIN_YSP1_ADDR_DNS_THRES_1_SL_ARRAY_07_04               (YSP1_BASE + 0x00d0)
++#define    MAIN_YSP1_ADDR_DNS_STREN_1_SL_ARRAY_03_00               (YSP1_BASE + 0x00d4)
++#define    MAIN_YSP1_ADDR_DNS_STREN_1_SL_ARRAY_07_04               (YSP1_BASE + 0x00d8)
++#define    MAIN_YSP1_ADDR_DNS_STREN_2_SL_ARRAY_03_00               (YSP1_BASE + 0x00dc)
++#define    MAIN_YSP1_ADDR_DNS_STREN_2_SL_ARRAY_07_04               (YSP1_BASE + 0x00e0)
++#define    MAIN_YSP1_ADDR_DIR_WEI_THRES_SL_ARRAY_03_00             (YSP1_BASE + 0x00e4)
++#define    MAIN_YSP1_ADDR_DIR_WEI_THRES_SL_ARRAY_07_04             (YSP1_BASE + 0x00e8)
++#define    MAIN_YSP1_ADDR_UU_THRES_SL_ARRAY_03_00                  (YSP1_BASE + 0x00ec)
++#define    MAIN_YSP1_ADDR_UU_THRES_SL_ARRAY_07_04                  (YSP1_BASE + 0x00f0)
++#define    MAIN_YSP1_ADDR_DIR_SP_SL_ARRAY_03_00                    (YSP1_BASE + 0x00f4)
++#define    MAIN_YSP1_ADDR_DIR_SP_SL_ARRAY_07_04                    (YSP1_BASE + 0x00f8)
++#define    MAIN_YSP1_ADDR_UDIR_SP_SL_ARRAY_03_00                   (YSP1_BASE + 0x00fc)
++#define    MAIN_YSP1_ADDR_UDIR_SP_SL_ARRAY_07_04                   (YSP1_BASE + 0x0100)
++#define    MAIN_YSP1_ADDR_DETAIL_SP_SL_ARRAY_03_00                 (YSP1_BASE + 0x0104)
++#define    MAIN_YSP1_ADDR_DETAIL_SP_SL_ARRAY_07_04                 (YSP1_BASE + 0x0108)
++
++#define    SEC_YSP1_ADDR_SL_EXP                                   (YSP1_BASE1 + 0x0000)
++#define    SEC_YSP1_ADDR_SL_SEL_OPT                               (YSP1_BASE1 + 0x0004)
++#define    SEC_YSP1_ADDR_EDGE_THRES                               (YSP1_BASE1 + 0x0008)
++#define    SEC_YSP1_ADDR_EDGE_MAX_THRES                           (YSP1_BASE1 + 0x000c)
++#define    SEC_YSP1_ADDR_EDGE_SCALE_OPT                           (YSP1_BASE1 + 0x0010)
++#define    SEC_YSP1_ADDR_OS_0                                     (YSP1_BASE1 + 0x0014)
++#define    SEC_YSP1_ADDR_OS_1                                     (YSP1_BASE1 + 0x0018)
++#define    SEC_YSP1_ADDR_OS_2                                     (YSP1_BASE1 + 0x001c)
++#define    SEC_YSP1_ADDR_OS_3                                     (YSP1_BASE1 + 0x0020)
++#define    SEC_YSP1_ADDR_V1                                       (YSP1_BASE1 + 0x0024)
++#define    SEC_YSP1_ADDR_V2                                       (YSP1_BASE1 + 0x0028)
++#define    SEC_YSP1_ADDR_DNS_0                                    (YSP1_BASE1 + 0x002c)
++#define    SEC_YSP1_ADDR_DNS_1                                    (YSP1_BASE1 + 0x0030)
++#define    SEC_YSP1_ADDR_DNS_2                                    (YSP1_BASE1 + 0x0034)
++#define    SEC_YSP1_ADDR_DNS_3                                    (YSP1_BASE1 + 0x0038)
++#define    SEC_YSP1_ADDR_DNS_4                                    (YSP1_BASE1 + 0x003c)
++#define    SEC_YSP1_ADDR_DNS_5                                    (YSP1_BASE1 + 0x0040)
++#define    SEC_YSP1_ADDR_DIR_0                                    (YSP1_BASE1 + 0x0044)
++#define    SEC_YSP1_ADDR_DIR_1                                    (YSP1_BASE1 + 0x0048)
++#define    SEC_YSP1_ADDR_UU_0                                     (YSP1_BASE1 + 0x004c)
++#define    SEC_YSP1_ADDR_UU_1                                     (YSP1_BASE1 + 0x0050)
++#define    SEC_YSP1_ADDR_LL                                       (YSP1_BASE1 + 0x0054)
++#define    SEC_YSP1_ADDR_HL                                       (YSP1_BASE1 + 0x0058)
++#define    SEC_YSP1_ADDR_W_WEI                                    (YSP1_BASE1 + 0x005c)
++#define    SEC_YSP1_ADDR_DIR_0_0                                  (YSP1_BASE1 + 0x0060)
++#define    SEC_YSP1_ADDR_DIR_1_1                                  (YSP1_BASE1 + 0x0064)
++#define    SEC_YSP1_ADDR_DIR_2                                    (YSP1_BASE1 + 0x0068)
++#define    SEC_YSP1_ADDR_UDIR_0                                   (YSP1_BASE1 + 0x006c)
++#define    SEC_YSP1_ADDR_UDIR_1                                   (YSP1_BASE1 + 0x0070)
++#define    SEC_YSP1_ADDR_DETAIL_0                                 (YSP1_BASE1 + 0x0074)
++#define    SEC_YSP1_ADDR_DETAIL_1                                 (YSP1_BASE1 + 0x0078)
++#define    SEC_YSP1_ADDR_DETAIL_2                                 (YSP1_BASE1 + 0x007c)
++#define    SEC_YSP1_ADDR_DEBUG0                                   (YSP0_BASE1 + 0x0080)
++#define    SEC_YSP1_ADDR_DEBUG1                                   (YSP0_BASE1 + 0x0084)
++#define    SEC_YSP1_ADDR_SHD_CTRL                                 (YSP1_BASE1 + 0x0088)
++#define    SEC_YSP1_ADDR_UU_NP_ARRAY_03_00                        (YSP1_BASE1 + 0x008c)
++#define    SEC_YSP1_ADDR_UU_NP_ARRAY_07_04                        (YSP1_BASE1 + 0x0090)
++#define    SEC_YSP1_ADDR_UU_NP_ARRAY_11_08                        (YSP1_BASE1 + 0x0094)
++#define    SEC_YSP1_ADDR_UU_NP_ARRAY_15_12                        (YSP1_BASE1 + 0x0098)
++#define    SEC_YSP1_ADDR_W_WEI_NP_ARRAY_03_00                     (YSP1_BASE1 + 0x009c)
++#define    SEC_YSP1_ADDR_W_WEI_NP_ARRAY_07_04                     (YSP1_BASE1 + 0x00a0)
++#define    SEC_YSP1_ADDR_W_WEI_NP_ARRAY_11_08                     (YSP1_BASE1 + 0x00a4)
++#define    SEC_YSP1_ADDR_W_WEI_NP_ARRAY_15_12                     (YSP1_BASE1 + 0x00a8)
++#define    SEC_YSP1_ADDR_B_WEI_NP_ARRAY_03_00                     (YSP1_BASE1 + 0x00ac)
++#define    SEC_YSP1_ADDR_B_WEI_NP_ARRAY_07_04                     (YSP1_BASE1 + 0x00b0)
++#define    SEC_YSP1_ADDR_B_WEI_NP_ARRAY_11_08                     (YSP1_BASE1 + 0x00b4)
++#define    SEC_YSP1_ADDR_B_WEI_NP_ARRAY_15_12                     (YSP1_BASE1 + 0x00b8)
++#define    SEC_YSP1_ADDR_DNS_THRES_0_SL_ARRAY_03_00               (YSP1_BASE1 + 0x00bc)
++#define    SEC_YSP1_ADDR_DNS_THRES_0_SL_ARRAY_07_04               (YSP1_BASE1 + 0x00c0)
++#define    SEC_YSP1_ADDR_DNS_STREN_0_SL_ARRAY_03_00               (YSP1_BASE1 + 0x00c4)
++#define    SEC_YSP1_ADDR_DNS_STREN_0_SL_ARRAY_07_04               (YSP1_BASE1 + 0x00c8)
++#define    SEC_YSP1_ADDR_DNS_THRES_1_SL_ARRAY_03_00               (YSP1_BASE1 + 0x00cc)
++#define    SEC_YSP1_ADDR_DNS_THRES_1_SL_ARRAY_07_04               (YSP1_BASE1 + 0x00d0)
++#define    SEC_YSP1_ADDR_DNS_STREN_1_SL_ARRAY_03_00               (YSP1_BASE1 + 0x00d4)
++#define    SEC_YSP1_ADDR_DNS_STREN_1_SL_ARRAY_07_04               (YSP1_BASE1 + 0x00d8)
++#define    SEC_YSP1_ADDR_DNS_STREN_2_SL_ARRAY_03_00               (YSP1_BASE1 + 0x00dc)
++#define    SEC_YSP1_ADDR_DNS_STREN_2_SL_ARRAY_07_04               (YSP1_BASE1 + 0x00e0)
++#define    SEC_YSP1_ADDR_DIR_WEI_THRES_SL_ARRAY_03_00             (YSP1_BASE1 + 0x00e4)
++#define    SEC_YSP1_ADDR_DIR_WEI_THRES_SL_ARRAY_07_04             (YSP1_BASE1 + 0x00e8)
++#define    SEC_YSP1_ADDR_UU_THRES_SL_ARRAY_03_00                  (YSP1_BASE1 + 0x00ec)
++#define    SEC_YSP1_ADDR_UU_THRES_SL_ARRAY_07_04                  (YSP1_BASE1 + 0x00f0)
++#define    SEC_YSP1_ADDR_DIR_SP_SL_ARRAY_03_00                    (YSP1_BASE1 + 0x00f4)
++#define    SEC_YSP1_ADDR_DIR_SP_SL_ARRAY_07_04                    (YSP1_BASE1 + 0x00f8)
++#define    SEC_YSP1_ADDR_UDIR_SP_SL_ARRAY_03_00                   (YSP1_BASE1 + 0x00fc)
++#define    SEC_YSP1_ADDR_UDIR_SP_SL_ARRAY_07_04                   (YSP1_BASE1 + 0x0100)
++#define    SEC_YSP1_ADDR_DETAIL_SP_SL_ARRAY_03_00                 (YSP1_BASE1 + 0x0104)
++#define    SEC_YSP1_ADDR_DETAIL_SP_SL_ARRAY_07_04                 (YSP1_BASE1 + 0x0108)
++
++//============================================================
++// HLDC ADDRESS
++//============================================================
++#define   HLDC_ADDR_FRAME_BP_EN(n)                           (HLDC_BASE(n) + 0x0000)
++#define   HLDC_ADDR_DIS_Y_COEFF_X(n)                         (HLDC_BASE(n) + 0x0004)
++#define   HLDC_ADDR_DIS_UV_COEFF_X(n)                        (HLDC_BASE(n) + 0x0008)
++#define   HLDC_ADDR_P1_Y_VAL(n)                              (HLDC_BASE(n) + 0x000c)
++#define   HLDC_ADDR_P1_UV_VAL(n)                         (HLDC_BASE(n) + 0x0010)
++#define   HLDC_ADDR_R2_Y_REP(n)                         (HLDC_BASE(n) + 0x0014)
++#define   HLDC_ADDR_R2_UV_REP(n)                         (HLDC_BASE(n) + 0x0018)
++#define   HLDC_ADDR_Y_OFFSET(n)                         (HLDC_BASE(n) + 0x001c)
++#define   HLDC_ADDR_UV_OFFSET(n)                         (HLDC_BASE(n) + 0x0020)
++#define   HLDC_ADDR_LINE_BLK_Y(n)                         (HLDC_BASE(n) + 0x0024)
++#define   HLDC_ADDR_LINE_BLK_UV(n)                         (HLDC_BASE(n) + 0x0028)
++#define   HLDC_ADDR_DBG_Y_0(n)                         (HLDC_BASE(n) + 0x002c)
++#define   HLDC_ADDR_DBG_Y_1(n)                         (HLDC_BASE(n) + 0x0030)
++#define   HLDC_ADDR_DBG_Y_2(n)                         (HLDC_BASE(n) + 0x0034)
++#define   HLDC_ADDR_DBG_UV_0(n)                         (HLDC_BASE(n) + 0x0038)
++#define   HLDC_ADDR_DBG_UV_1(n)                         (HLDC_BASE(n) + 0x003c)
++#define   HLDC_ADDR_DBG_UV_2(n)                         (HLDC_BASE(n) + 0x0040)
++#define   HLDC_ADDR_SHD_CTRL(n)                         (HLDC_BASE(n) + 0x0044)
++
++//============================================================
++// AE ADDRESS
++//============================================================
++#define    MAIN_AE_ADDR_SHD_CTRL                                  (AE0_BASE + 0x0000)
++#define    MAIN_AE_ADDR_ZONE_NUM_START                            (AE0_BASE + 0x0004)
++#define    MAIN_AE_ADDR_HOR_ZONE_SIZE_14                          (AE0_BASE + 0x0008)
++#define    MAIN_AE_ADDR_HOR_ZONE_SIZE_58                          (AE0_BASE + 0x000c)
++#define    MAIN_AE_ADDR_HOR_ZONE_SIZE_912                         (AE0_BASE + 0x0010)
++#define    MAIN_AE_ADDR_HOR_ZONE_SIZE_1315                        (AE0_BASE + 0x0014)
++#define    MAIN_AE_ADDR_VER_ZONE_SIZE_14                          (AE0_BASE + 0x0018)
++#define    MAIN_AE_ADDR_VER_ZONE_SIZE_58                          (AE0_BASE + 0x001c)
++#define    MAIN_AE_ADDR_VER_ZONE_SIZE_912                         (AE0_BASE + 0x0020)
++#define    MAIN_AE_ADDR_VER_ZONE_SIZE_1315                        (AE0_BASE + 0x0024)
++#define    MAIN_AE_ADDR_LUM_TH_FREQ                               (AE0_BASE + 0x0028)
++#define    MAIN_AE_ADDR_AE_DMA_BASE_1                             (AE0_BASE + 0x002c)
++#define    MAIN_AE_ADDR_AE_DMA_BASE_2                             (AE0_BASE + 0x0030)
++#define    MAIN_AE_ADDR_AE_DMA_BASE_3                             (AE0_BASE + 0x0034)
++#define    MAIN_AE_ADDR_AE_DMA_BASE_4                             (AE0_BASE + 0x0038)
++#define    MAIN_AE_ADDR_HIST_DMA_BASE_1                           (AE0_BASE + 0x003c)
++#define    MAIN_AE_ADDR_HIST_DMA_BASE_2                           (AE0_BASE + 0x0040)
++#define    MAIN_AE_ADDR_HIST_DMA_BASE_3                           (AE0_BASE + 0x0044)
++#define    MAIN_AE_ADDR_HIST_DMA_BASE_4                           (AE0_BASE + 0x0048)
++#define    MAIN_AE_ADDR_DMA_BASE_NUM                              (AE0_BASE + 0x004c)
++#define    MAIN_AE_ADDR_DMA_INFO                                  (AE0_BASE + 0x0050)
++#define    MAIN_AE_ADDR_SPEC_ZONE_HSIZE                           (AE0_BASE + 0x0054)
++#define    MAIN_AE_ADDR_SPEC_ZONE_VSIZE                           (AE0_BASE + 0x0058)
++#define    MAIN_AE_ADDR_SPEC_SUM_DARK                             (AE0_BASE + 0x005c)
++#define    MAIN_AE_ADDR_SPEC_SUM_MID                              (AE0_BASE + 0x0060)
++#define    MAIN_AE_ADDR_SPEC_SUM_SAT                              (AE0_BASE + 0x0064)
++#define    MAIN_AE_ADDR_SPEC_CNT_DARK                             (AE0_BASE + 0x0068)
++#define    MAIN_AE_ADDR_SPEC_CNT_SAT                              (AE0_BASE + 0x006c)
++#define    MAIN_AE_ADDR_SPEC_SUM_IR                               (AE0_BASE + 0x0070)
++#define    MAIN_AE_ADDR_DEBUG_0                                   (AE0_BASE + 0x0074)
++#define    MAIN_AE_ADDR_DEBUG_1                                   (AE0_BASE + 0x0078)
++#define    MAIN_AE_ADDR_DEBUG_2                                   (AE0_BASE + 0x007c)
++#define    MAIN_AE_ADDR_DEBUG_3                                   (AE0_BASE + 0x0080)
++#define    MAIN_AE_ADDR_DEBUG_4                                   (AE0_BASE + 0x0084)
++#define    MAIN_AE_ADDR_DEBUG_5                                   (AE0_BASE + 0x0088)
++#define    MAIN_AE_ADDR_DEBUG_6                                   (AE0_BASE + 0x008c)
++#define    MAIN_AE_ADDR_DEBUG_7                                   (AE0_BASE + 0x0090)
++#define    MAIN_AE_ADDR_DEBUG_8                                   (AE0_BASE + 0x0094)
++#define    MAIN_AE_ADDR_DEBUG_9                                   (AE0_BASE + 0x0098)
++#define    MAIN_AE_ADDR_DEBUG_10                                  (AE0_BASE + 0x009c)
++#define    MAIN_AE_ADDR_DEBUG_11                                  (AE0_BASE + 0x00a0)
++#define    MAIN_AE_ADDR_DEBUG_12                                  (AE0_BASE + 0x00a4)
++#define    MAIN_AE_ADDR_DEBUG_13                                  (AE0_BASE + 0x00a8)
++
++#define    SEC_AE_ADDR_SHD_CTRL                                   (AE1_BASE + 0x0000)
++#define    SEC_AE_ADDR_ZONE_NUM_START                             (AE1_BASE + 0x0004)
++#define    SEC_AE_ADDR_HOR_ZONE_SIZE_14                           (AE1_BASE + 0x0008)
++#define    SEC_AE_ADDR_HOR_ZONE_SIZE_58                           (AE1_BASE + 0x000c)
++#define    SEC_AE_ADDR_HOR_ZONE_SIZE_912                          (AE1_BASE + 0x0010)
++#define    SEC_AE_ADDR_HOR_ZONE_SIZE_1315                         (AE1_BASE + 0x0014)
++#define    SEC_AE_ADDR_VER_ZONE_SIZE_14                           (AE1_BASE + 0x0018)
++#define    SEC_AE_ADDR_VER_ZONE_SIZE_58                           (AE1_BASE + 0x001c)
++#define    SEC_AE_ADDR_VER_ZONE_SIZE_912                          (AE1_BASE + 0x0020)
++#define    SEC_AE_ADDR_VER_ZONE_SIZE_1315                         (AE1_BASE + 0x0024)
++#define    SEC_AE_ADDR_LUM_TH_FREQ                                (AE1_BASE + 0x0028)
++#define    SEC_AE_ADDR_AE_DMA_BASE_1                              (AE1_BASE + 0x002c)
++#define    SEC_AE_ADDR_AE_DMA_BASE_2                              (AE1_BASE + 0x0030)
++#define    SEC_AE_ADDR_AE_DMA_BASE_3                              (AE1_BASE + 0x0034)
++#define    SEC_AE_ADDR_AE_DMA_BASE_4                              (AE1_BASE + 0x0038)
++#define    SEC_AE_ADDR_HIST_DMA_BASE_1                            (AE1_BASE + 0x003c)
++#define    SEC_AE_ADDR_HIST_DMA_BASE_2                            (AE1_BASE + 0x0040)
++#define    SEC_AE_ADDR_HIST_DMA_BASE_3                            (AE1_BASE + 0x0044)
++#define    SEC_AE_ADDR_HIST_DMA_BASE_4                            (AE1_BASE + 0x0048)
++#define    SEC_AE_ADDR_DMA_BASE_NUM                               (AE1_BASE + 0x004c)
++#define    SEC_AE_ADDR_DMA_INFO                                   (AE1_BASE + 0x0050)
++#define    SEC_AE_ADDR_SPEC_ZONE_HSIZE                            (AE1_BASE + 0x0054)
++#define    SEC_AE_ADDR_SPEC_ZONE_VSIZE                            (AE1_BASE + 0x0058)
++#define    SEC_AE_ADDR_SPEC_SUM_DARK                              (AE1_BASE + 0x005c)
++#define    SEC_AE_ADDR_SPEC_SUM_MID                               (AE1_BASE + 0x0060)
++#define    SEC_AE_ADDR_SPEC_SUM_SAT                               (AE1_BASE + 0x0064)
++#define    SEC_AE_ADDR_SPEC_CNT_DARK                              (AE1_BASE + 0x0068)
++#define    SEC_AE_ADDR_SPEC_CNT_SAT                               (AE1_BASE + 0x006c)
++#define    SEC_AE_ADDR_SPEC_SUM_IR                                (AE1_BASE + 0x0070)
++#define    SEC_AE_ADDR_DEBUG_0                                    (AE1_BASE + 0x0074)
++#define    SEC_AE_ADDR_DEBUG_1                                    (AE1_BASE + 0x0078)
++#define    SEC_AE_ADDR_DEBUG_2                                    (AE1_BASE + 0x007c)
++#define    SEC_AE_ADDR_DEBUG_3                                    (AE1_BASE + 0x0080)
++#define    SEC_AE_ADDR_DEBUG_4                                    (AE1_BASE + 0x0084)
++#define    SEC_AE_ADDR_DEBUG_5                                    (AE1_BASE + 0x0088)
++#define    SEC_AE_ADDR_DEBUG_6                                    (AE1_BASE + 0x008c)
++#define    SEC_AE_ADDR_DEBUG_7                                    (AE1_BASE + 0x0090)
++#define    SEC_AE_ADDR_DEBUG_8                                    (AE1_BASE + 0x0094)
++#define    SEC_AE_ADDR_DEBUG_9                                    (AE1_BASE + 0x0098)
++#define    SEC_AE_ADDR_DEBUG_10                                   (AE1_BASE + 0x009c)
++#define    SEC_AE_ADDR_DEBUG_11                                   (AE1_BASE + 0x00a0)
++#define    SEC_AE_ADDR_DEBUG_12                                   (AE1_BASE + 0x00a4)
++#define    SEC_AE_ADDR_DEBUG_13                                   (AE1_BASE + 0x00a8)
++
++//============================================================
++// AWB ADDRESS
++//============================================================
++#define    MAIN_AWB_ADDR_SHD_CTRL                                 (AWB0_BASE + 0x0000)
++#define    MAIN_AWB_ADDR_ZONE_NUM_START                           (AWB0_BASE + 0x0004)
++#define    MAIN_AWB_ADDR_HOR_ZONE_SIZE_14                         (AWB0_BASE + 0x0008)
++#define    MAIN_AWB_ADDR_HOR_ZONE_SIZE_58                         (AWB0_BASE + 0x000c)
++#define    MAIN_AWB_ADDR_HOR_ZONE_SIZE_912                        (AWB0_BASE + 0x0010)
++#define    MAIN_AWB_ADDR_HOR_ZONE_SIZE_1315                       (AWB0_BASE + 0x0014)
++#define    MAIN_AWB_ADDR_VER_ZONE_SIZE_14                         (AWB0_BASE + 0x0018)
++#define    MAIN_AWB_ADDR_VER_ZONE_SIZE_58                         (AWB0_BASE + 0x001c)
++#define    MAIN_AWB_ADDR_VER_ZONE_SIZE_912                        (AWB0_BASE + 0x0020)
++#define    MAIN_AWB_ADDR_VER_ZONE_SIZE_1315                       (AWB0_BASE + 0x0024)
++#define    MAIN_AWB_ADDR_RG_TH                                    (AWB0_BASE + 0x0028)
++#define    MAIN_AWB_ADDR_BG_TH                                    (AWB0_BASE + 0x002c)
++#define    MAIN_AWB_ADDR_K1_A1                                    (AWB0_BASE + 0x0030)
++#define    MAIN_AWB_ADDR_K2_A2                                    (AWB0_BASE + 0x0034)
++#define    MAIN_AWB_ADDR_LUM_TH_FREQ                              (AWB0_BASE + 0x0038)
++#define    MAIN_AWB_ADDR_AWB_DMA_BASE_1                           (AWB0_BASE + 0x003c)
++#define    MAIN_AWB_ADDR_AWB_DMA_BASE_2                           (AWB0_BASE + 0x0040)
++#define    MAIN_AWB_ADDR_AWB_DMA_BASE_3                           (AWB0_BASE + 0x0044)
++#define    MAIN_AWB_ADDR_AWB_DMA_BASE_4                           (AWB0_BASE + 0x0048)
++#define    MAIN_AWB_ADDR_DMA_BASE_NUM                             (AWB0_BASE + 0x004c)
++#define    MAIN_AWB_ADDR_DMA_INFO                                 (AWB0_BASE + 0x0050)
++#define    MAIN_AWB_ADDR_REMV_RG_INFO_0                           (AWB0_BASE + 0x0054)
++#define    MAIN_AWB_ADDR_REMV_RG_INFO_1                           (AWB0_BASE + 0x0058)
++#define    MAIN_AWB_ADDR_REMV_RG_INFO_2                           (AWB0_BASE + 0x005c)
++#define    MAIN_AWB_ADDR_REMV_RG_INFO_3                           (AWB0_BASE + 0x0060)
++#define    MAIN_AWB_ADDR_REMV_RG_INFO_4                           (AWB0_BASE + 0x0064)
++#define    MAIN_AWB_ADDR_REMV_BG_INFO_0                           (AWB0_BASE + 0x0068)
++#define    MAIN_AWB_ADDR_REMV_BG_INFO_1                           (AWB0_BASE + 0x006c)
++#define    MAIN_AWB_ADDR_REMV_BG_INFO_2                           (AWB0_BASE + 0x0070)
++#define    MAIN_AWB_ADDR_REMV_BG_INFO_3                           (AWB0_BASE + 0x0074)
++#define    MAIN_AWB_ADDR_REMV_BG_INFO_4                           (AWB0_BASE + 0x0078)
++#define    MAIN_AWB_ADDR_REMV_RADIUS_INFO_0                       (AWB0_BASE + 0x007c)
++#define    MAIN_AWB_ADDR_REMV_RADIUS_INFO_1                       (AWB0_BASE + 0x0080)
++#define    MAIN_AWB_ADDR_REMV_RADIUS_INFO_2                       (AWB0_BASE + 0x0084)
++#define    MAIN_AWB_ADDR_REMV_RADIUS_INFO_3                       (AWB0_BASE + 0x0088)
++#define    MAIN_AWB_ADDR_REMV_RADIUS_INFO_4                       (AWB0_BASE + 0x008c)
++#define    MAIN_AWB_ADDR_REMV_RADIUS_INFO_5                       (AWB0_BASE + 0x0090)
++#define    MAIN_AWB_ADDR_REMV_RADIUS_INFO_6                       (AWB0_BASE + 0x0094)
++#define    MAIN_AWB_ADDR_REMV_RADIUS_INFO_7                       (AWB0_BASE + 0x0098)
++#define    MAIN_AWB_ADDR_REMV_RADIUS_INFO_8                       (AWB0_BASE + 0x009c)
++#define    MAIN_AWB_ADDR_REMV_RADIUS_INFO_9                       (AWB0_BASE + 0x00a0)
++#define    MAIN_AWB_ADDR_SPEC_ZONE_INFO_0                         (AWB0_BASE + 0x00a4)
++#define    MAIN_AWB_ADDR_SPEC_ZONE_INFO_1                         (AWB0_BASE + 0x00a8)
++#define    MAIN_AWB_ADDR_R_SUM_SPEC                               (AWB0_BASE + 0x00ac)
++#define    MAIN_AWB_ADDR_G_SUM_SPEC                               (AWB0_BASE + 0x00b0)
++#define    MAIN_AWB_ADDR_B_SUM_SPEC                               (AWB0_BASE + 0x00b4)
++#define    MAIN_AWB_ADDR_IR_SUM_SPEC                              (AWB0_BASE + 0x00b8)
++#define    MAIN_AWB_ADDR_PIX_SUM_SPEC                             (AWB0_BASE + 0x00bc)
++#define    MAIN_AWB_ADDR_DEBUG_0                                  (AWB0_BASE + 0x00c0)
++#define    MAIN_AWB_ADDR_DEBUG_1                                  (AWB0_BASE + 0x00c4)
++#define    MAIN_AWB_ADDR_DEBUG_2                                  (AWB0_BASE + 0x00c8)
++#define    MAIN_AWB_ADDR_DEBUG_3                                  (AWB0_BASE + 0x00cc)
++#define    MAIN_AWB_ADDR_DEBUG_4                                  (AWB0_BASE + 0x00d0)
++#define    MAIN_AWB_ADDR_DEBUG_5                                  (AWB0_BASE + 0x00d4)
++#define    MAIN_AWB_ADDR_DEBUG_6                                  (AWB0_BASE + 0x00d8)
++#define    MAIN_AWB_ADDR_DEBUG_7                                  (AWB0_BASE + 0x00dc)
++#define    MAIN_AWB_ADDR_DEBUG_8                                  (AWB0_BASE + 0x00e0)
++#define    MAIN_AWB_ADDR_DEBUG_9                                  (AWB0_BASE + 0x00e4)
++#define    MAIN_AWB_ADDR_DEBUG_10                                 (AWB0_BASE + 0x00e8)
++#define    MAIN_AWB_ADDR_DEBUG_11                                 (AWB0_BASE + 0x00ec)
++#define    MAIN_AWB_ADDR_DEBUG_12                                 (AWB0_BASE + 0x00f0)
++#define    MAIN_AWB_ADDR_DEBUG_13                                 (AWB0_BASE + 0x00f4)
++#define    MAIN_AWB_ADDR_DEBUG_14                                 (AWB0_BASE + 0x00f8)
++
++#define    SEC_AWB_ADDR_SHD_CTRL                                  (AWB1_BASE + 0x0000)
++#define    SEC_AWB_ADDR_ZONE_NUM_START                            (AWB1_BASE + 0x0004)
++#define    SEC_AWB_ADDR_HOR_ZONE_SIZE_14                          (AWB1_BASE + 0x0008)
++#define    SEC_AWB_ADDR_HOR_ZONE_SIZE_58                          (AWB1_BASE + 0x000c)
++#define    SEC_AWB_ADDR_HOR_ZONE_SIZE_912                         (AWB1_BASE + 0x0010)
++#define    SEC_AWB_ADDR_HOR_ZONE_SIZE_1315                        (AWB1_BASE + 0x0014)
++#define    SEC_AWB_ADDR_VER_ZONE_SIZE_14                          (AWB1_BASE + 0x0018)
++#define    SEC_AWB_ADDR_VER_ZONE_SIZE_58                          (AWB1_BASE + 0x001c)
++#define    SEC_AWB_ADDR_VER_ZONE_SIZE_912                         (AWB1_BASE + 0x0020)
++#define    SEC_AWB_ADDR_VER_ZONE_SIZE_1315                        (AWB1_BASE + 0x0024)
++#define    SEC_AWB_ADDR_RG_TH                                     (AWB1_BASE + 0x0028)
++#define    SEC_AWB_ADDR_BG_TH                                     (AWB1_BASE + 0x002c)
++#define    SEC_AWB_ADDR_K1_A1                                     (AWB1_BASE + 0x0030)
++#define    SEC_AWB_ADDR_K2_A2                                     (AWB1_BASE + 0x0034)
++#define    SEC_AWB_ADDR_LUM_TH_FREQ                               (AWB1_BASE + 0x0038)
++#define    SEC_AWB_ADDR_AWB_DMA_BASE_1                            (AWB1_BASE + 0x003c)
++#define    SEC_AWB_ADDR_AWB_DMA_BASE_2                            (AWB1_BASE + 0x0040)
++#define    SEC_AWB_ADDR_AWB_DMA_BASE_3                            (AWB1_BASE + 0x0044)
++#define    SEC_AWB_ADDR_AWB_DMA_BASE_4                            (AWB1_BASE + 0x0048)
++#define    SEC_AWB_ADDR_DMA_BASE_NUM                              (AWB1_BASE + 0x004c)
++#define    SEC_AWB_ADDR_DMA_INFO                                  (AWB1_BASE + 0x0050)
++#define    SEC_AWB_ADDR_REMV_RG_INFO_0                            (AWB1_BASE + 0x0054)
++#define    SEC_AWB_ADDR_REMV_RG_INFO_1                            (AWB1_BASE + 0x0058)
++#define    SEC_AWB_ADDR_REMV_RG_INFO_2                            (AWB1_BASE + 0x005c)
++#define    SEC_AWB_ADDR_REMV_RG_INFO_3                            (AWB1_BASE + 0x0060)
++#define    SEC_AWB_ADDR_REMV_RG_INFO_4                            (AWB1_BASE + 0x0064)
++#define    SEC_AWB_ADDR_REMV_BG_INFO_0                            (AWB1_BASE + 0x0068)
++#define    SEC_AWB_ADDR_REMV_BG_INFO_1                            (AWB1_BASE + 0x006c)
++#define    SEC_AWB_ADDR_REMV_BG_INFO_2                            (AWB1_BASE + 0x0070)
++#define    SEC_AWB_ADDR_REMV_BG_INFO_3                            (AWB1_BASE + 0x0074)
++#define    SEC_AWB_ADDR_REMV_BG_INFO_4                            (AWB1_BASE + 0x0078)
++#define    SEC_AWB_ADDR_REMV_RADIUS_INFO_0                        (AWB1_BASE + 0x007c)
++#define    SEC_AWB_ADDR_REMV_RADIUS_INFO_1                        (AWB1_BASE + 0x0080)
++#define    SEC_AWB_ADDR_REMV_RADIUS_INFO_2                        (AWB1_BASE + 0x0084)
++#define    SEC_AWB_ADDR_REMV_RADIUS_INFO_3                        (AWB1_BASE + 0x0088)
++#define    SEC_AWB_ADDR_REMV_RADIUS_INFO_4                        (AWB1_BASE + 0x008c)
++#define    SEC_AWB_ADDR_REMV_RADIUS_INFO_5                        (AWB1_BASE + 0x0090)
++#define    SEC_AWB_ADDR_REMV_RADIUS_INFO_6                        (AWB1_BASE + 0x0094)
++#define    SEC_AWB_ADDR_REMV_RADIUS_INFO_7                        (AWB1_BASE + 0x0098)
++#define    SEC_AWB_ADDR_REMV_RADIUS_INFO_8                        (AWB1_BASE + 0x009c)
++#define    SEC_AWB_ADDR_REMV_RADIUS_INFO_9                        (AWB1_BASE + 0x00a0)
++#define    SEC_AWB_ADDR_SPEC_ZONE_INFO_0                          (AWB1_BASE + 0x00a4)
++#define    SEC_AWB_ADDR_SPEC_ZONE_INFO_1                          (AWB1_BASE + 0x00a8)
++#define    SEC_AWB_ADDR_R_SUM_SPEC                                (AWB1_BASE + 0x00ac)
++#define    SEC_AWB_ADDR_G_SUM_SPEC                                (AWB1_BASE + 0x00b0)
++#define    SEC_AWB_ADDR_B_SUM_SPEC                                (AWB1_BASE + 0x00b4)
++#define    SEC_AWB_ADDR_IR_SUM_SPEC                               (AWB1_BASE + 0x00b8)
++#define    SEC_AWB_ADDR_PIX_SUM_SPEC                              (AWB1_BASE + 0x00bc)
++#define    SEC_AWB_ADDR_DEBUG_0                                   (AWB1_BASE + 0x00c0)
++#define    SEC_AWB_ADDR_DEBUG_1                                   (AWB1_BASE + 0x00c4)
++#define    SEC_AWB_ADDR_DEBUG_2                                   (AWB1_BASE + 0x00c8)
++#define    SEC_AWB_ADDR_DEBUG_3                                   (AWB1_BASE + 0x00cc)
++#define    SEC_AWB_ADDR_DEBUG_4                                   (AWB1_BASE + 0x00d0)
++#define    SEC_AWB_ADDR_DEBUG_5                                   (AWB1_BASE + 0x00d4)
++#define    SEC_AWB_ADDR_DEBUG_6                                   (AWB1_BASE + 0x00d8)
++#define    SEC_AWB_ADDR_DEBUG_7                                   (AWB1_BASE + 0x00dc)
++#define    SEC_AWB_ADDR_DEBUG_8                                   (AWB1_BASE + 0x00e0)
++#define    SEC_AWB_ADDR_DEBUG_9                                   (AWB1_BASE + 0x00e4)
++#define    SEC_AWB_ADDR_DEBUG_10                                  (AWB1_BASE + 0x00e8)
++#define    SEC_AWB_ADDR_DEBUG_11                                  (AWB1_BASE + 0x00ec)
++#define    SEC_AWB_ADDR_DEBUG_12                                  (AWB1_BASE + 0x00f0)
++#define    SEC_AWB_ADDR_DEBUG_13                                  (AWB1_BASE + 0x00f4)
++#define    SEC_AWB_ADDR_DEBUG_14                                  (AWB1_BASE + 0x00f8)
++
++//============================================================
++// AF ADDRESS
++//============================================================
++#define    AF_BASE1                                                (AF_BASE + 0x200)
++#define    MAIN_AF_ADDR_SHD_CTRL                                   (AF_BASE + 0x0000)
++#define    MAIN_AF_ADDR_ZONE_NUM_START                             (AF_BASE + 0x0004)
++#define    MAIN_AF_ADDR_HOR_ZONE_SIZE_1                            (AF_BASE + 0x0008)
++#define    MAIN_AF_ADDR_HOR_ZONE_SIZE_3                            (AF_BASE + 0x000c)
++#define    MAIN_AF_ADDR_HOR_ZONE_SIZE_5                            (AF_BASE + 0x0010)
++#define    MAIN_AF_ADDR_HOR_ZONE_SIZE_7                            (AF_BASE + 0x0014)
++#define    MAIN_AF_ADDR_HOR_ZONE_SIZE_9                            (AF_BASE + 0x0018)
++#define    MAIN_AF_ADDR_HOR_ZONE_SIZE_11                           (AF_BASE + 0x001c)
++#define    MAIN_AF_ADDR_HOR_ZONE_SIZE_13                           (AF_BASE + 0x0020)
++#define    MAIN_AF_ADDR_HOR_ZONE_SIZE_15                           (AF_BASE + 0x0024)
++#define    MAIN_AF_ADDR_VER_ZONE_SIZE_1                            (AF_BASE + 0x0028)
++#define    MAIN_AF_ADDR_VER_ZONE_SIZE_5                            (AF_BASE + 0x002c)
++#define    MAIN_AF_ADDR_VER_ZONE_SIZE_9                            (AF_BASE + 0x0030)
++#define    MAIN_AF_ADDR_VER_ZONE_SIZE_13                           (AF_BASE + 0x0034)
++#define    MAIN_AF_ADDR_FREQ_IIR_EN_LUM_TH                         (AF_BASE + 0x0038)
++#define    MAIN_AF_ADDR_LDG_COR_EN                                 (AF_BASE + 0x003c)
++#define    MAIN_AF_ADDR_FIR0_G1_G2                                 (AF_BASE + 0x0040)
++#define    MAIN_AF_ADDR_FIR0_G3_G4                                 (AF_BASE + 0x0044)
++#define    MAIN_AF_ADDR_FIR0_G5                                    (AF_BASE + 0x0048)
++#define    MAIN_AF_ADDR_FIR1_G1_G2                                 (AF_BASE + 0x004c)
++#define    MAIN_AF_ADDR_FIR1_G3_G4                                 (AF_BASE + 0x0050)
++#define    MAIN_AF_ADDR_FIR1_G5                                    (AF_BASE + 0x0054)
++#define    MAIN_AF_ADDR_IIR0_G1_G3                                 (AF_BASE + 0x0058)
++#define    MAIN_AF_ADDR_IIR0_G4_G5                                 (AF_BASE + 0x005c)
++#define    MAIN_AF_ADDR_IIR0_G6_G8                                 (AF_BASE + 0x0060)
++#define    MAIN_AF_ADDR_IIR0_G9_G10                                (AF_BASE + 0x0064)
++#define    MAIN_AF_ADDR_IIR1_G1_G3                                 (AF_BASE + 0x0068)
++#define    MAIN_AF_ADDR_IIR1_G4_G5                                 (AF_BASE + 0x006c)
++#define    MAIN_AF_ADDR_IIR1_G6_G8                                 (AF_BASE + 0x0070)
++#define    MAIN_AF_ADDR_IIR1_G9_G10                                (AF_BASE + 0x0074)
++#define    MAIN_AF_ADDR_LDG_FIR0_LOW                               (AF_BASE + 0x0078)
++#define    MAIN_AF_ADDR_LDG_FIR0_HIGH                              (AF_BASE + 0x007c)
++#define    MAIN_AF_ADDR_LDG_FIR1_LOW                               (AF_BASE + 0x0080)
++#define    MAIN_AF_ADDR_LDG_FIR1_HIGH                              (AF_BASE + 0x0084)
++#define    MAIN_AF_ADDR_LDG_IIR0_LOW                               (AF_BASE + 0x0088)
++#define    MAIN_AF_ADDR_LDG_IIR0_HIGH                              (AF_BASE + 0x008c)
++#define    MAIN_AF_ADDR_LDG_IIR1_LOW                               (AF_BASE + 0x0090)
++#define    MAIN_AF_ADDR_LDG_IIR1_HIGH                              (AF_BASE + 0x0094)
++#define    MAIN_AF_ADDR_LDG_FIR_GAIN                               (AF_BASE + 0x0098)
++#define    MAIN_AF_ADDR_LDG_IIR_GAIN                               (AF_BASE + 0x009c)
++#define    MAIN_AF_ADDR_COR_F0_TH_LH                               (AF_BASE + 0x00a0)
++#define    MAIN_AF_ADDR_COR_F1_TH_LH                               (AF_BASE + 0x00a4)
++#define    MAIN_AF_ADDR_COR_I0_TH_LH                               (AF_BASE + 0x00a8)
++#define    MAIN_AF_ADDR_COR_I1_TH_LH                               (AF_BASE + 0x00ac)
++#define    MAIN_AF_ADDR_STAT_MODE_EN                               (AF_BASE + 0x00b0)
++#define    MAIN_AF_ADDR_STAT_TH_F                                  (AF_BASE + 0x00b4)
++#define    MAIN_AF_ADDR_STAT_TH_I                                  (AF_BASE + 0x00b8)
++#define    MAIN_AF_ADDR_STAT_SLP_LIM_F0                            (AF_BASE + 0x00bc)
++#define    MAIN_AF_ADDR_STAT_SLP_LIM_F1                            (AF_BASE + 0x00c0)
++#define    MAIN_AF_ADDR_STAT_SLP_LIM_I0                            (AF_BASE + 0x00c4)
++#define    MAIN_AF_ADDR_STAT_SLP_LIM_I1                            (AF_BASE + 0x00c8)
++#define    MAIN_AF_ADDR_AF_DMA_BASE_1                              (AF_BASE + 0x00cc)
++#define    MAIN_AF_ADDR_AF_DMA_BASE_2                              (AF_BASE + 0x00d0)
++#define    MAIN_AF_ADDR_AF_DMA_BASE_3                              (AF_BASE + 0x00d4)
++#define    MAIN_AF_ADDR_AF_DMA_BASE_4                              (AF_BASE + 0x00d8)
++#define    MAIN_AF_ADDR_DMA_BASE_NUM                               (AF_BASE + 0x00dc)
++#define    MAIN_AF_ADDR_DMA_INFO                                   (AF_BASE + 0x00e0)
++#define    MAIN_AF_ADDR_DEBUG_0                                    (AF_BASE + 0x00e4)
++#define    MAIN_AF_ADDR_DEBUG_1                                    (AF_BASE + 0x00e8)
++#define    MAIN_AF_ADDR_DEBUG_2                                    (AF_BASE + 0x00ec)
++#define    MAIN_AF_ADDR_DEBUG_3                                    (AF_BASE + 0x00f0)
++
++#define    SEC_AF_ADDR_SHD_CTRL                                   (AF_BASE1 + 0x0000)
++#define    SEC_AF_ADDR_ZONE_NUM_START                             (AF_BASE1 + 0x0004)
++#define    SEC_AF_ADDR_HOR_ZONE_SIZE_1                            (AF_BASE1 + 0x0008)
++#define    SEC_AF_ADDR_HOR_ZONE_SIZE_3                            (AF_BASE1 + 0x000c)
++#define    SEC_AF_ADDR_HOR_ZONE_SIZE_5                            (AF_BASE1 + 0x0010)
++#define    SEC_AF_ADDR_HOR_ZONE_SIZE_7                            (AF_BASE1 + 0x0014)
++#define    SEC_AF_ADDR_HOR_ZONE_SIZE_9                            (AF_BASE1 + 0x0018)
++#define    SEC_AF_ADDR_HOR_ZONE_SIZE_11                           (AF_BASE1 + 0x001c)
++#define    SEC_AF_ADDR_HOR_ZONE_SIZE_13                           (AF_BASE1 + 0x0020)
++#define    SEC_AF_ADDR_HOR_ZONE_SIZE_15                           (AF_BASE1 + 0x0024)
++#define    SEC_AF_ADDR_VER_ZONE_SIZE_1                            (AF_BASE1 + 0x0028)
++#define    SEC_AF_ADDR_VER_ZONE_SIZE_5                            (AF_BASE1 + 0x002c)
++#define    SEC_AF_ADDR_VER_ZONE_SIZE_9                            (AF_BASE1 + 0x0030)
++#define    SEC_AF_ADDR_VER_ZONE_SIZE_13                           (AF_BASE1 + 0x0034)
++#define    SEC_AF_ADDR_FREQ_IIR_EN_LUM_TH                         (AF_BASE1 + 0x0038)
++#define    SEC_AF_ADDR_LDG_COR_EN                                 (AF_BASE1 + 0x003c)
++#define    SEC_AF_ADDR_FIR0_G1_G2                                 (AF_BASE1 + 0x0040)
++#define    SEC_AF_ADDR_FIR0_G3_G4                                 (AF_BASE1 + 0x0044)
++#define    SEC_AF_ADDR_FIR0_G5                                    (AF_BASE1 + 0x0048)
++#define    SEC_AF_ADDR_FIR1_G1_G2                                 (AF_BASE1 + 0x004c)
++#define    SEC_AF_ADDR_FIR1_G3_G4                                 (AF_BASE1 + 0x0050)
++#define    SEC_AF_ADDR_FIR1_G5                                    (AF_BASE1 + 0x0054)
++#define    SEC_AF_ADDR_IIR0_G1_G3                                 (AF_BASE1 + 0x0058)
++#define    SEC_AF_ADDR_IIR0_G4_G5                                 (AF_BASE1 + 0x005c)
++#define    SEC_AF_ADDR_IIR0_G6_G8                                 (AF_BASE1 + 0x0060)
++#define    SEC_AF_ADDR_IIR0_G9_G10                                (AF_BASE1 + 0x0064)
++#define    SEC_AF_ADDR_IIR1_G1_G3                                 (AF_BASE1 + 0x0068)
++#define    SEC_AF_ADDR_IIR1_G4_G5                                 (AF_BASE1 + 0x006c)
++#define    SEC_AF_ADDR_IIR1_G6_G8                                 (AF_BASE1 + 0x0070)
++#define    SEC_AF_ADDR_IIR1_G9_G10                                (AF_BASE1 + 0x0074)
++#define    SEC_AF_ADDR_LDG_FIR0_LOW                               (AF_BASE1 + 0x0078)
++#define    SEC_AF_ADDR_LDG_FIR0_HIGH                              (AF_BASE1 + 0x007c)
++#define    SEC_AF_ADDR_LDG_FIR1_LOW                               (AF_BASE1 + 0x0080)
++#define    SEC_AF_ADDR_LDG_FIR1_HIGH                              (AF_BASE1 + 0x0084)
++#define    SEC_AF_ADDR_LDG_IIR0_LOW                               (AF_BASE1 + 0x0088)
++#define    SEC_AF_ADDR_LDG_IIR0_HIGH                              (AF_BASE1 + 0x008c)
++#define    SEC_AF_ADDR_LDG_IIR1_LOW                               (AF_BASE1 + 0x0090)
++#define    SEC_AF_ADDR_LDG_IIR1_HIGH                              (AF_BASE1 + 0x0094)
++#define    SEC_AF_ADDR_LDG_FIR_GAIN                               (AF_BASE1 + 0x0098)
++#define    SEC_AF_ADDR_LDG_IIR_GAIN                               (AF_BASE1 + 0x009c)
++#define    SEC_AF_ADDR_COR_F0_TH_LH                               (AF_BASE1 + 0x00a0)
++#define    SEC_AF_ADDR_COR_F1_TH_LH                               (AF_BASE1 + 0x00a4)
++#define    SEC_AF_ADDR_COR_I0_TH_LH                               (AF_BASE1 + 0x00a8)
++#define    SEC_AF_ADDR_COR_I1_TH_LH                               (AF_BASE1 + 0x00ac)
++#define    SEC_AF_ADDR_STAT_MODE_EN                               (AF_BASE1 + 0x00b0)
++#define    SEC_AF_ADDR_STAT_TH_F                                  (AF_BASE1 + 0x00b4)
++#define    SEC_AF_ADDR_STAT_TH_I                                  (AF_BASE1 + 0x00b8)
++#define    SEC_AF_ADDR_STAT_SLP_LIM_F0                            (AF_BASE1 + 0x00bc)
++#define    SEC_AF_ADDR_STAT_SLP_LIM_F1                            (AF_BASE1 + 0x00c0)
++#define    SEC_AF_ADDR_STAT_SLP_LIM_I0                            (AF_BASE1 + 0x00c4)
++#define    SEC_AF_ADDR_STAT_SLP_LIM_I1                            (AF_BASE1 + 0x00c8)
++#define    SEC_AF_ADDR_AF_DMA_BASE_1                              (AF_BASE1 + 0x00cc)
++#define    SEC_AF_ADDR_AF_DMA_BASE_2                              (AF_BASE1 + 0x00d0)
++#define    SEC_AF_ADDR_AF_DMA_BASE_3                              (AF_BASE1 + 0x00d4)
++#define    SEC_AF_ADDR_AF_DMA_BASE_4                              (AF_BASE1 + 0x00d8)
++#define    SEC_AF_ADDR_DMA_BASE_NUM                               (AF_BASE1 + 0x00dc)
++#define    SEC_AF_ADDR_DMA_INFO                                   (AF_BASE1 + 0x00e0)
++#define    SEC_AF_ADDR_DEBUG_0                                    (AF_BASE1 + 0x00e4)
++#define    SEC_AF_ADDR_DEBUG_1                                    (AF_BASE1 + 0x00e8)
++#define    SEC_AF_ADDR_DEBUG_2                                    (AF_BASE1 + 0x00ec)
++#define    SEC_AF_ADDR_DEBUG_3                                    (AF_BASE1 + 0x00f0)
++
++//============================================================
++// GSM ADDRESS
++//============================================================
++#define    GSM0_ADDR_BUF_CLR                                  (GSM0_BASE + 0x0000)
++#define    GSM0_ADDR_BUF_STATE                                (GSM0_BASE + 0x0004)
++#define    GSM0_ADDR_FRM_RATE                                 (GSM0_BASE + 0x0010)
++#define    GSM0_ADDR_ADJUST                                   (GSM0_BASE + 0x0020)
++#define    GSM0_ADDR_DBGSIG0                                  (GSM0_BASE + 0x0030)
++
++#define    GSM1_ADDR_BUF_CLR                                   (GSM1_BASE + 0x0000)
++#define    GSM1_ADDR_BUF_STATE                                 (GSM1_BASE + 0x0004)
++#define    GSM1_ADDR_FRM_RATE                                  (GSM1_BASE + 0x0010)
++#define    GSM1_ADDR_ADJUST                                    (GSM1_BASE + 0x0020)
++#define    GSM1_ADDR_DBGSIG0                                   (GSM1_BASE + 0x0030)
++
++//============================================================
++// IPC ADDRESS
++//============================================================
++#define IPC_ADDR_IP_TRIG                                   (IPC_BASE + 0x0000)
++#define IPC_ADDR_SHD_CTRL                                  (IPC_BASE + 0x0004)
++#define IPC_ADDR_CONTROL                                   (IPC_BASE + 0x0008)
++#define IPC_ADDR_CHK_TRIG                                  (IPC_BASE + 0x000c)
++#define IPC_ADDR_DUAL_CHN_SWITCH_CON                       (IPC_BASE + 0x0010)
++#define IPC_ADDR_DUAL_CHN_SWITCH_CON_NUM                   (IPC_BASE + 0x0014)
++#define IPC_ADDR_DUAL_CHN_SEL                              (IPC_BASE + 0x0018)
++#define IPC_ADDR_V0_NEAR_FULL                              (IPC_BASE + 0x001c)
++#define IPC_ADDR_V0_NEAR_FULL_THRES                        (IPC_BASE + 0x0020)
++#define IPC_ADDR_V1_NEAR_FULL                              (IPC_BASE + 0x0024)
++#define IPC_ADDR_V1_NEAR_FULL_THRES                        (IPC_BASE + 0x0028)
++#define IPC_ADDR_DF_CHN_COMP_EN                            (IPC_BASE + 0x002c)
++#define IPC_ADDR_DF_CH0_ADDR                               (IPC_BASE + 0x0030)
++#define IPC_ADDR_DF_CH1_ADDR                               (IPC_BASE + 0x0034)
++#define IPC_ADDR_DF_CH2_ADDR                               (IPC_BASE + 0x0038)
++#define IPC_ADDR_DF_CH3_ADDR                               (IPC_BASE + 0x003c)
++#define IPC_ADDR_DF_CH0_SIZE                               (IPC_BASE + 0x0040)
++#define IPC_ADDR_DF_CH1_SIZE                               (IPC_BASE + 0x0044)
++#define IPC_ADDR_DF_CH2_SIZE                               (IPC_BASE + 0x0048)
++#define IPC_ADDR_DF_CH3_SIZE                               (IPC_BASE + 0x004c)
++#define IPC_ADDR_YUV_OFFSET                                (IPC_BASE + 0x0050)
++#define IPC_ADDR_WDMA_THRES_0                              (IPC_BASE + 0x0054)
++#define IPC_ADDR_WDMA_THRES_1                              (IPC_BASE + 0x0058)
++#define IPC_ADDR_RDMA_THRES                                (IPC_BASE + 0x005c)
++#define IPC_ADDR_DUAL_M3_ORI_MODE                          (IPC_BASE + 0x0060)
++#define IPC_ADDR_M3_V0_URGENT_THRES                        (IPC_BASE + 0x0064)
++#define IPC_ADDR_M3_V1_URGENT_THRES                        (IPC_BASE + 0x0068)
++#define IPC_ADDR_M3_V0_V0_THRES                            (IPC_BASE + 0x006c)
++#define IPC_ADDR_M3_V0_V1_THRES                            (IPC_BASE + 0x0070)
++#define IPC_ADDR_M3_V1_V0_THRES                            (IPC_BASE + 0x0074)
++#define IPC_ADDR_M3_V1_V1_THRES                            (IPC_BASE + 0x0078)
++#define IPC_ADDR_V0_CH0_IN_CNT                             (IPC_BASE + 0x0100)
++#define IPC_ADDR_V0_CH1_IN_CNT                             (IPC_BASE + 0x0104)
++#define IPC_ADDR_V1_CH0_IN_CNT                             (IPC_BASE + 0x0108)
++#define IPC_ADDR_V1_CH1_IN_CNT                             (IPC_BASE + 0x010c)
++#define IPC_ADDR_V0_CH0_ERR_CNT                            (IPC_BASE + 0x0110)
++#define IPC_ADDR_V0_CH1_ERR_CNT                            (IPC_BASE + 0x0114)
++#define IPC_ADDR_V1_CH0_ERR_CNT                            (IPC_BASE + 0x0118)
++#define IPC_ADDR_V1_CH1_ERR_CNT                            (IPC_BASE + 0x011c)
++#define IPC_ADDR_ERR_CHN_INDEX                             (IPC_BASE + 0x0120)
++#define IPC_ADDR_V0_CH0_CHK_FR_CNT                         (IPC_BASE + 0x0124)
++#define IPC_ADDR_V0_CH1_CHK_FR_CNT                         (IPC_BASE + 0x0128)
++#define IPC_ADDR_V1_CH0_CHK_FR_CNT                         (IPC_BASE + 0x012c)
++#define IPC_ADDR_V1_CH1_CHK_FR_CNT                         (IPC_BASE + 0x0130)
++#define IPC_ADDR_CHN_OUT_CNT                               (IPC_BASE + 0x0134)
++#define IPC_ADDR_IN_OUT_STATE                              (IPC_BASE + 0x0138)
++#define IPC_ADDR_IN_CH01_FIFO_CNT                          (IPC_BASE + 0x013c)
++#define IPC_ADDR_IN_CH2_FIFO_CNT                           (IPC_BASE + 0x0140)
++#define IPC_ADDR_COMP_CH0_DMA_CNT                          (IPC_BASE + 0x0144)
++#define IPC_ADDR_COMP_CH1_DMA_CNT                          (IPC_BASE + 0x0148)
++#define IPC_ADDR_COMP_CH2_DMA_CNT                          (IPC_BASE + 0x014c)
++#define IPC_ADDR_COMP_CH3_DMA_CNT                          (IPC_BASE + 0x0150)
++#define IPC_ADDR_FR_PRO_NUM                                (IPC_BASE + 0x0154)
++#define IPC_ADDR_CH0_FR_INTERVAL                           (IPC_BASE + 0x0158)
++#define IPC_ADDR_CH1_FR_INTERVAL                           (IPC_BASE + 0x015c)
++
++//============================================================
++// MCFG ADDRESS
++//============================================================
++#define    MCFG_ADDR_S0_DPC_CNTL                             (MCFG_BASE + 0x0000)
++#define    MCFG_ADDR_S0_DPC_WCHNL                            (MCFG_BASE + 0x0004)
++#define    MCFG_ADDR_S0_DPC_RCHNL                            (MCFG_BASE + 0x0008)
++#define    MCFG_ADDR_S0_DPC_RESP                             (MCFG_BASE + 0x000c)
++#define    MCFG_ADDR_S1_DPC_CNTL                             (MCFG_BASE + 0x0010)
++#define    MCFG_ADDR_S1_DPC_WCHNL                            (MCFG_BASE + 0x0014)
++#define    MCFG_ADDR_S1_DPC_RCHNL                            (MCFG_BASE + 0x0018)
++#define    MCFG_ADDR_S1_DPC_RESP                             (MCFG_BASE + 0x001c)
++#define    MCFG_ADDR_S0_LSC_CNTL                             (MCFG_BASE + 0x0020)
++#define    MCFG_ADDR_S0_LSC_WCHNL                            (MCFG_BASE + 0x0024)
++#define    MCFG_ADDR_S0_LSC_RCHNL                            (MCFG_BASE + 0x0028)
++#define    MCFG_ADDR_S0_LSC_RESP                             (MCFG_BASE + 0x002c)
++#define    MCFG_ADDR_S1_LSC_CNTL                             (MCFG_BASE + 0x0030)
++#define    MCFG_ADDR_S1_LSC_WCHNL                            (MCFG_BASE + 0x0034)
++#define    MCFG_ADDR_S1_LSC_RCHNL                            (MCFG_BASE + 0x0038)
++#define    MCFG_ADDR_S1_LSC_RESP                             (MCFG_BASE + 0x003c)
++#define    MCFG_ADDR_S0_RGAMMA_CNTL                          (MCFG_BASE + 0x0040)
++#define    MCFG_ADDR_S0_RGAMMA_WCHNL                         (MCFG_BASE + 0x0044)
++#define    MCFG_ADDR_S0_RGAMMA_RCHNL                         (MCFG_BASE + 0x0048)
++#define    MCFG_ADDR_S0_RGAMMA_RESP                          (MCFG_BASE + 0x004c)
++#define    MCFG_ADDR_S1_RGAMMA_CNTL                          (MCFG_BASE + 0x0050)
++#define    MCFG_ADDR_S1_RGAMMA_WCHNL                         (MCFG_BASE + 0x0054)
++#define    MCFG_ADDR_S1_RGAMMA_RCHNL                         (MCFG_BASE + 0x0058)
++#define    MCFG_ADDR_S1_RGAMMA_RESP                          (MCFG_BASE + 0x005c)
++#define    MCFG_ADDR_S0_BGAMMA_CNTL                          (MCFG_BASE + 0x0060)
++#define    MCFG_ADDR_S0_BGAMMA_WCHNL                         (MCFG_BASE + 0x0064)
++#define    MCFG_ADDR_S0_BGAMMA_RCHNL                         (MCFG_BASE + 0x0068)
++#define    MCFG_ADDR_S0_BGAMMA_RESP                          (MCFG_BASE + 0x006c)
++#define    MCFG_ADDR_S1_BGAMMA_CNTL                          (MCFG_BASE + 0x0070)
++#define    MCFG_ADDR_S1_BGAMMA_WCHNL                         (MCFG_BASE + 0x0074)
++#define    MCFG_ADDR_S1_BGAMMA_RCHNL                         (MCFG_BASE + 0x0078)
++#define    MCFG_ADDR_S1_BGAMMA_RESP                          (MCFG_BASE + 0x007c)
++#define    MCFG_ADDR_S0_GGAMMA_CNTL                          (MCFG_BASE + 0x0080)
++#define    MCFG_ADDR_S0_GGAMMA_WCHNL                         (MCFG_BASE + 0x0084)
++#define    MCFG_ADDR_S0_GGAMMA_RCHNL                         (MCFG_BASE + 0x0088)
++#define    MCFG_ADDR_S0_GGAMMA_RESP                          (MCFG_BASE + 0x008c)
++#define    MCFG_ADDR_S1_GGAMMA_CNTL                          (MCFG_BASE + 0x0090)
++#define    MCFG_ADDR_S1_GGAMMA_WCHNL                         (MCFG_BASE + 0x0094)
++#define    MCFG_ADDR_S1_GGAMMA_RCHNL                         (MCFG_BASE + 0x0098)
++#define    MCFG_ADDR_S1_GGAMMA_RESP                          (MCFG_BASE + 0x009c)
++#define    MCFG_ADDR_S0_DEFOG_CNTL                           (MCFG_BASE + 0x00a0)
++#define    MCFG_ADDR_S0_DEFOG_WCHNL                          (MCFG_BASE + 0x00a4)
++#define    MCFG_ADDR_S0_DEFOG_RCHNL                          (MCFG_BASE + 0x00a8)
++#define    MCFG_ADDR_S0_DEFOG_RESP                           (MCFG_BASE + 0x00ac)
++#define    MCFG_ADDR_S1_DEFOG_CNTL                           (MCFG_BASE + 0x00b0)
++#define    MCFG_ADDR_S1_DEFOG_WCHNL                          (MCFG_BASE + 0x00b4)
++#define    MCFG_ADDR_S1_DEFOG_RCHNL                          (MCFG_BASE + 0x00b8)
++#define    MCFG_ADDR_S1_DEFOG_RESP                           (MCFG_BASE + 0x00bc)
++#define    MCFG_ADDR_S0_CLMH0_CNTL                           (MCFG_BASE + 0x00c0)
++#define    MCFG_ADDR_S0_CLMH0_WCHNL                          (MCFG_BASE + 0x00c4)
++#define    MCFG_ADDR_S0_CLMH0_RCHNL                          (MCFG_BASE + 0x00c8)
++#define    MCFG_ADDR_S0_CLMH0_RESP                           (MCFG_BASE + 0x00cc)
++#define    MCFG_ADDR_S1_CLMH0_CNTL                           (MCFG_BASE + 0x00d0)
++#define    MCFG_ADDR_S1_CLMH0_WCHNL                          (MCFG_BASE + 0x00d4)
++#define    MCFG_ADDR_S1_CLMH0_RCHNL                          (MCFG_BASE + 0x00d8)
++#define    MCFG_ADDR_S1_CLMH0_RESP                           (MCFG_BASE + 0x00dc)
++#define    MCFG_ADDR_S0_CLMH1_CNTL                           (MCFG_BASE + 0x00e0)
++#define    MCFG_ADDR_S0_CLMH1_WCHNL                          (MCFG_BASE + 0x00e4)
++#define    MCFG_ADDR_S0_CLMH1_RCHNL                          (MCFG_BASE + 0x00e8)
++#define    MCFG_ADDR_S0_CLMH1_RESP                           (MCFG_BASE + 0x00ec)
++#define    MCFG_ADDR_S1_CLMH1_CNTL                           (MCFG_BASE + 0x00f0)
++#define    MCFG_ADDR_S1_CLMH1_WCHNL                          (MCFG_BASE + 0x00f4)
++#define    MCFG_ADDR_S1_CLMH1_RCHNL                          (MCFG_BASE + 0x00f8)
++#define    MCFG_ADDR_S1_CLMH1_RESP                           (MCFG_BASE + 0x00fc)
++#define    MCFG_ADDR_S0_CLMS0_CNTL                           (MCFG_BASE + 0x0100)
++#define    MCFG_ADDR_S0_CLMS0_WCHNL                          (MCFG_BASE + 0x0104)
++#define    MCFG_ADDR_S0_CLMS0_RCHNL                          (MCFG_BASE + 0x0108)
++#define    MCFG_ADDR_S0_CLMS0_RESP                           (MCFG_BASE + 0x010c)
++#define    MCFG_ADDR_S1_CLMS0_CNTL                           (MCFG_BASE + 0x0110)
++#define    MCFG_ADDR_S1_CLMS0_WCHNL                          (MCFG_BASE + 0x0114)
++#define    MCFG_ADDR_S1_CLMS0_RCHNL                          (MCFG_BASE + 0x0118)
++#define    MCFG_ADDR_S1_CLMS0_RESP                           (MCFG_BASE + 0x011c)
++#define    MCFG_ADDR_S0_CLMS1_CNTL                           (MCFG_BASE + 0x0120)
++#define    MCFG_ADDR_S0_CLMS1_WCHNL                          (MCFG_BASE + 0x0124)
++#define    MCFG_ADDR_S0_CLMS1_RCHNL                          (MCFG_BASE + 0x0128)
++#define    MCFG_ADDR_S0_CLMS1_RESP                           (MCFG_BASE + 0x012c)
++#define    MCFG_ADDR_S1_CLMS1_CNTL                           (MCFG_BASE + 0x0130)
++#define    MCFG_ADDR_S1_CLMS1_WCHNL                          (MCFG_BASE + 0x0134)
++#define    MCFG_ADDR_S1_CLMS1_RCHNL                          (MCFG_BASE + 0x0138)
++#define    MCFG_ADDR_S1_CLMS1_RESP                           (MCFG_BASE + 0x013c)
++#define    MCFG_ADDR_S0_GIBR_CNTL                            (MCFG_BASE + 0x0140)
++#define    MCFG_ADDR_S0_GIBR_WCHNL                           (MCFG_BASE + 0x0144)
++#define    MCFG_ADDR_S0_GIBR_RCHNL                           (MCFG_BASE + 0x0148)
++#define    MCFG_ADDR_S0_GIBR_RESP                            (MCFG_BASE + 0x014c)
++#define    MCFG_ADDR_S0_GIBG_CNTL                            (MCFG_BASE + 0x0150)
++#define    MCFG_ADDR_S0_GIBG_WCHNL                           (MCFG_BASE + 0x0154)
++#define    MCFG_ADDR_S0_GIBG_RCHNL                           (MCFG_BASE + 0x0158)
++#define    MCFG_ADDR_S0_GIBG_RESP                            (MCFG_BASE + 0x015c)
++#define    MCFG_ADDR_S0_GIBB_CNTL                            (MCFG_BASE + 0x0160)
++#define    MCFG_ADDR_S0_GIBB_WCHNL                           (MCFG_BASE + 0x0164)
++#define    MCFG_ADDR_S0_GIBB_RCHNL                           (MCFG_BASE + 0x0168)
++#define    MCFG_ADDR_S0_GIBB_RESP                            (MCFG_BASE + 0x016c)
++#define    MCFG_ADDR_S1_GIBR_CNTL                            (MCFG_BASE + 0x0170)
++#define    MCFG_ADDR_S1_GIBR_WCHNL                           (MCFG_BASE + 0x0174)
++#define    MCFG_ADDR_S1_GIBR_RCHNL                           (MCFG_BASE + 0x0178)
++#define    MCFG_ADDR_S1_GIBR_RESP                            (MCFG_BASE + 0x017c)
++#define    MCFG_ADDR_S1_GIBG_CNTL                            (MCFG_BASE + 0x0180)
++#define    MCFG_ADDR_S1_GIBG_WCHNL                           (MCFG_BASE + 0x0184)
++#define    MCFG_ADDR_S1_GIBG_RCHNL                           (MCFG_BASE + 0x0188)
++#define    MCFG_ADDR_S1_GIBG_RESP                            (MCFG_BASE + 0x018c)
++#define    MCFG_ADDR_S1_GIBB_CNTL                            (MCFG_BASE + 0x0190)
++#define    MCFG_ADDR_S1_GIBB_WCHNL                           (MCFG_BASE + 0x0194)
++#define    MCFG_ADDR_S1_GIBB_RCHNL                           (MCFG_BASE + 0x0198)
++#define    MCFG_ADDR_S1_GIBB_RESP                            (MCFG_BASE + 0x019c)
++#define    MCFG_ADDR_S0_GSM_CNTL                             (MCFG_BASE + 0x01a0)
++#define    MCFG_ADDR_S0_GSM_WCHNL                            (MCFG_BASE + 0x01a4)
++#define    MCFG_ADDR_S0_GSM_RCHNL                            (MCFG_BASE + 0x01a8)
++#define    MCFG_ADDR_S0_GSM_RESP                             (MCFG_BASE + 0x01ac)
++#define    MCFG_ADDR_S1_GSM_CNTL                             (MCFG_BASE + 0x01b0)
++#define    MCFG_ADDR_S1_GSM_WCHNL                            (MCFG_BASE + 0x01b4)
++#define    MCFG_ADDR_S1_GSM_RCHNL                            (MCFG_BASE + 0x01b8)
++#define    MCFG_ADDR_S1_GSM_RESP                             (MCFG_BASE + 0x01bc)
++#define    MCFG_ADDR_S0_LCE_CNTL                             (MCFG_BASE + 0x01c0)
++#define    MCFG_ADDR_S0_LCE_WCHNL                            (MCFG_BASE + 0x01c4)
++#define    MCFG_ADDR_S0_LCE_RCHNL                            (MCFG_BASE + 0x01c8)
++#define    MCFG_ADDR_S0_LCE_RESP                             (MCFG_BASE + 0x01cc)
++#define    MCFG_ADDR_S1_LCE_CNTL                             (MCFG_BASE + 0x01d0)
++#define    MCFG_ADDR_S1_LCE_WCHNL                            (MCFG_BASE + 0x01d4)
++#define    MCFG_ADDR_S1_LCE_RCHNL                            (MCFG_BASE + 0x01d8)
++#define    MCFG_ADDR_S1_LCE_RESP                             (MCFG_BASE + 0x01dc)
++#define    MCFG_ADDR_S0_LCEP_CNTL                            (MCFG_BASE + 0x01e0)
++#define    MCFG_ADDR_S0_LCEP_WCHNL                           (MCFG_BASE + 0x01e4)
++#define    MCFG_ADDR_S0_LCEP_RCHNL                           (MCFG_BASE + 0x01e8)
++#define    MCFG_ADDR_S0_LCEP_RESP                            (MCFG_BASE + 0x01ec)
++#define    MCFG_ADDR_S1_LCEP_CNTL                            (MCFG_BASE + 0x01f0)
++#define    MCFG_ADDR_S1_LCEP_WCHNL                           (MCFG_BASE + 0x01f4)
++#define    MCFG_ADDR_S1_LCEP_RCHNL                           (MCFG_BASE + 0x01f8)
++#define    MCFG_ADDR_S1_LCEP_RESP                            (MCFG_BASE + 0x01fc)
++#define    MCFG_ADDR_S0_LCEY_CNTL                            (MCFG_BASE + 0x0200)
++#define    MCFG_ADDR_S0_LCEY_WCHNL                           (MCFG_BASE + 0x0204)
++#define    MCFG_ADDR_S0_LCEY_RCHNL                           (MCFG_BASE + 0x0208)
++#define    MCFG_ADDR_S0_LCEY_RESP                            (MCFG_BASE + 0x020c)
++#define    MCFG_ADDR_S1_LCEY_CNTL                            (MCFG_BASE + 0x0210)
++#define    MCFG_ADDR_S1_LCEY_WCHNL                           (MCFG_BASE + 0x0214)
++#define    MCFG_ADDR_S1_LCEY_RCHNL                           (MCFG_BASE + 0x0218)
++#define    MCFG_ADDR_S1_LCEY_RESP                            (MCFG_BASE + 0x021c)
++#define    MCFG_ADDR_ADR_VSHD_CNTL                           (MCFG_BASE + 0x0300)
++#define    MCFG_ADDR_ADR_VSHD_WCHNL                          (MCFG_BASE + 0x0304)
++#define    MCFG_ADDR_ADR_VSHD_RCHNL                          (MCFG_BASE + 0x0308)
++#define    MCFG_ADDR_ADR_VSHD_RESP                           (MCFG_BASE + 0x030c)
++#define    MCFG_ADDR_WDR_VSHD_CNTL                           (MCFG_BASE + 0x0310)
++#define    MCFG_ADDR_WDR_VSHD_WCHNL                          (MCFG_BASE + 0x0314)
++#define    MCFG_ADDR_WDR_VSHD_RCHNL                          (MCFG_BASE + 0x0318)
++#define    MCFG_ADDR_WDR_VSHD_RESP                           (MCFG_BASE + 0x031c)
++#define    MCFG_ADDR_MSCA_VSHD_CNTL                          (MCFG_BASE + 0x0320)
++#define    MCFG_ADDR_MSCA_VSHD_WCHNL                         (MCFG_BASE + 0x0324)
++#define    MCFG_ADDR_MSCA_VSHD_RCHNL                         (MCFG_BASE + 0x0328)
++#define    MCFG_ADDR_MSCA_VSHD_RESP                          (MCFG_BASE + 0x032c)
++#define    MCFG_ADDR_ADR_VSHD_REGPAR                         (MCFG_BASE + 0x0400)
++#define    MCFG_ADDR_ADR_VSHD_MEMPAR                         (MCFG_BASE + 0x0404)
++#define    MCFG_ADDR_ADR_VSHD_START                          (MCFG_BASE + 0x0408)
++#define    MCFG_ADDR_ADR_VSHD_DONE                           (MCFG_BASE + 0x040c)
++#define    MCFG_ADDR_WDR_VSHD_REGPAR                         (MCFG_BASE + 0x0410)
++#define    MCFG_ADDR_WDR_VSHD_MEMPAR                         (MCFG_BASE + 0x0414)
++#define    MCFG_ADDR_WDR_VSHD_START                          (MCFG_BASE + 0x0418)
++#define    MCFG_ADDR_WDR_VSHD_DONE                           (MCFG_BASE + 0x041c)
++#define    MCFG_ADDR_MSCA_VSHD_CNTRL                         (MCFG_BASE + 0x0420)
++
++//============================================================
++// MSCA ADDRESS
++//============================================================
++#define    MAIN_MSCA_ADDR_CH_WORK_EN                          (MSCALER0_BASE + 0x0008)
++#define    MAIN_MSCA_ADDR_FORCE                               (MSCALER0_BASE + 0x000c)
++#define    MAIN_MSCA_ADDR_CTRL                                (MSCALER0_BASE + 0x0010)
++#define    MAIN_MSCA_ADDR_MASK_EN                             (MSCALER0_BASE + 0x0014)
++#define    MAIN_MSCA_ADDR_OSD_EN                              (MSCALER0_BASE + 0x0018)
++#define    MAIN_MSCA_ADDR_COEF_FIX_EN                         (MSCALER0_BASE + 0x0028)
++#define    MAIN_MSCA_ADDR_MIRR_FLIP_RSMP_SAMP_DONE            (MSCALER0_BASE + 0x002c)
++#define    MAIN_MSCA_ADDR_CLK_GATE_EN                         (MSCALER0_BASE + 0x0030)
++#define    MAIN_MSCA_ADDR_CLK_GATE                            (MSCALER0_BASE + 0x0034)
++#define    MAIN_MSCA_ADDR_OSD_COEF_R                          (MSCALER0_BASE + 0x0050)
++#define    MAIN_MSCA_ADDR_OSD_COEF_G                          (MSCALER0_BASE + 0x0054)
++#define    MAIN_MSCA_ADDR_OSD_COEF_B                          (MSCALER0_BASE + 0x0058)
++#define    MAIN_MSCA_ADDR_OSD_COEF_OFT                        (MSCALER0_BASE + 0x005c)
++#define    MAIN_MSCA_ADDR_OSD_MODE                            (MSCALER0_BASE + 0x0060)
++#define    MAIN_MSCA_ADDR_OSD_ARGB_TYPE                       (MSCALER0_BASE + 0x0064)
++#define    MAIN_MSCA_ADDR_CH0_PRIO                            (MSCALER0_BASE + 0x0070)
++#define    MAIN_MSCA_ADDR_CH1_PRIO                            (MSCALER0_BASE + 0x0074)
++#define    MAIN_MSCA_ADDR_CH2_PRIO                            (MSCALER0_BASE + 0x0078)
++#define    MAIN_MSCA_ADDR_SRC_RSZ_POS                         (MSCALER0_BASE + 0x0080)
++#define    MAIN_MSCA_ADDR_SRC_RSZ_SIZE                        (MSCALER0_BASE + 0x0084)
++#define    MAIN_MSCA_ADDR_COEF_SEL                            (MSCALER0_BASE + 0x0088)
++#define    MAIN_MSCA_ADDR_CH0_BEFORE_IRQ                      (MSCALER0_BASE + 0x0090)
++#define    MAIN_MSCA_ADDR_CH1_BEFORE_IRQ                      (MSCALER0_BASE + 0x0094)
++#define    MAIN_MSCA_ADDR_CH2_BEFORE_IRQ                      (MSCALER0_BASE + 0x0098)
++#define    MAIN_MSCA_ADDR_CH0_FCROP_POS                       (MSCALER0_BASE + 0x00a0)
++#define    MAIN_MSCA_ADDR_CH0_FCROP_IMG                       (MSCALER0_BASE + 0x00a4)
++#define    MAIN_MSCA_ADDR_CH1_FCROP_POS                       (MSCALER0_BASE + 0x00a8)
++#define    MAIN_MSCA_ADDR_CH1_FCROP_IMG                       (MSCALER0_BASE + 0x00ac)
++#define    MAIN_MSCA_ADDR_CH2_FCROP_POS                       (MSCALER0_BASE + 0x00b0)
++#define    MAIN_MSCA_ADDR_CH2_FCROP_IMG                       (MSCALER0_BASE + 0x00b4)
++#define    MAIN_MSCA_ADDR_WORK_STAT                           (MSCALER0_BASE + 0x00e0)
++#define    MAIN_MSCA_ADDR_SYS_PRO_CLK_EN                      (MSCALER0_BASE + 0x00f0)
++#define    MAIN_MSCA_ADDR_CH0_CLK_NUM                         (MSCALER0_BASE + 0x00f4)
++#define    MAIN_MSCA_ADDR_CH1_CLK_NUM                         (MSCALER0_BASE + 0x00f8)
++#define    MAIN_MSCA_ADDR_CH2_CLK_NUM                         (MSCALER0_BASE + 0x00fc)
++#define    MAIN_MSCA_ADDR_CH0_RSZ_SIZE                        (MSCALER0_BASE + 0x0100)
++#define    MAIN_MSCA_ADDR_CH0_RSZ_STEP                        (MSCALER0_BASE + 0x0104)
++#define    MAIN_MSCA_ADDR_CH0_CROP_POS                        (MSCALER0_BASE + 0x0128)
++#define    MAIN_MSCA_ADDR_CH0_CROP_SIZE                       (MSCALER0_BASE + 0x012c)
++#define    MAIN_MSCA_ADDR_CH0_FR_CTRL_LOOP                    (MSCALER0_BASE + 0x0130)
++#define    MAIN_MSCA_ADDR_CH0_FR_CTRL_MASK                    (MSCALER0_BASE + 0x0134)
++#define    MAIN_MSCA_ADDR_CH0_MS0_POS                         (MSCALER0_BASE + 0x0138)
++#define    MAIN_MSCA_ADDR_CH0_MS0_SIZE                        (MSCALER0_BASE + 0x013c)
++#define    MAIN_MSCA_ADDR_CH0_MS0_VALUE                       (MSCALER0_BASE + 0x0140)
++#define    MAIN_MSCA_ADDR_CH0_MS1_POS                         (MSCALER0_BASE + 0x0144)
++#define    MAIN_MSCA_ADDR_CH0_MS1_SIZE                        (MSCALER0_BASE + 0x0148)
++#define    MAIN_MSCA_ADDR_CH0_MS1_VALUE                       (MSCALER0_BASE + 0x014c)
++#define    MAIN_MSCA_ADDR_CH0_MS2_POS                         (MSCALER0_BASE + 0x0150)
++#define    MAIN_MSCA_ADDR_CH0_MS2_SIZE                        (MSCALER0_BASE + 0x0154)
++#define    MAIN_MSCA_ADDR_CH0_MS2_VALUE                       (MSCALER0_BASE + 0x0158)
++#define    MAIN_MSCA_ADDR_CH0_MS3_POS                         (MSCALER0_BASE + 0x015c)
++#define    MAIN_MSCA_ADDR_CH0_MS3_SIZE                        (MSCALER0_BASE + 0x0160)
++#define    MAIN_MSCA_ADDR_CH0_MS3_VALUE                       (MSCALER0_BASE + 0x0164)
++#define    MAIN_MSCA_ADDR_CH0_OUT_FMT                         (MSCALER0_BASE + 0x0168)
++#define    MAIN_MSCA_ADDR_CH0_DMAOUT_Y_ADDR                   (MSCALER0_BASE + 0x016c)
++#define    MAIN_MSCA_ADDR_CH0_Y_ADDR_FIFO_STA                 (MSCALER0_BASE + 0x0170)
++#define    MAIN_MSCA_ADDR_CH0_DMAOUT_Y_LAST_ADDR              (MSCALER0_BASE + 0x0174)
++#define    MAIN_MSCA_ADDR_CH0_Y_LAST_ADDR_FIFO_STA            (MSCALER0_BASE + 0x017c)
++#define    MAIN_MSCA_ADDR_CH0_DMAOUT_Y_STRIDE                 (MSCALER0_BASE + 0x0180)
++#define    MAIN_MSCA_ADDR_CH0_DMAOUT_UV_ADDR                  (MSCALER0_BASE + 0x0184)
++#define    MAIN_MSCA_ADDR_CH0_UV_ADDR_FIFO_STA                (MSCALER0_BASE + 0x0188)
++#define    MAIN_MSCA_ADDR_CH0_DMAOUT_UV_LAST_ADDR             (MSCALER0_BASE + 0x018c)
++#define    MAIN_MSCA_ADDR_CH0_UV_LAST_ADDR_FIFO_STA           (MSCALER0_BASE + 0x0194)
++#define    MAIN_MSCA_ADDR_CH0_DMAOUT_UV_STRIDE                (MSCALER0_BASE + 0x0198)
++#define    MAIN_MSCA_ADDR_CH0_DMAOUT_Y_ADDR_CLR               (MSCALER0_BASE + 0x019c)
++#define    MAIN_MSCA_ADDR_CH0_DMAOUT_UV_ADDR_CLR              (MSCALER0_BASE + 0x01a0)
++#define    MAIN_MSCA_ADDR_CH0_DMAOUT_Y_LAST_ADDR_CLR          (MSCALER0_BASE + 0x01a4)
++#define    MAIN_MSCA_ADDR_CH0_DMAOUT_UV_LAST_ADDR_CLR         (MSCALER0_BASE + 0x01a8)
++#define    MAIN_MSCA_ADDR_CH0_DMAOUT_Y_ADDR_SEL               (MSCALER0_BASE + 0x01ac)
++#define    MAIN_MSCA_ADDR_CH0_DMAOUT_UV_ADDR_SEL              (MSCALER0_BASE + 0x01b0)
++#define    MAIN_MSCA_ADDR_CH0_COE_ZERO_VRSZ_H                 (MSCALER0_BASE + 0x01c0)
++#define    MAIN_MSCA_ADDR_CH0_COE_ZERO_VRSZ_L                 (MSCALER0_BASE + 0x01c4)
++#define    MAIN_MSCA_ADDR_CH0_COE_ZERO_HRSZ_H                 (MSCALER0_BASE + 0x01c8)
++#define    MAIN_MSCA_ADDR_CH0_COE_ZERO_HRSZ_L                 (MSCALER0_BASE + 0x01cc)
++#define    MAIN_MSCA_ADDR_CH0_COE_OFT                         (MSCALER0_BASE + 0x01d0)
++#define    MAIN_MSCA_ADDR_CH0_ARF                             (MSCALER0_BASE + 0x01f0)
++#define    MAIN_MSCA_ADDR_CH0_CLR                             (MSCALER0_BASE + 0x01f4)
++#define    MAIN_MSCA_ADDR_CH1_RSZ_SIZE                        (MSCALER0_BASE + 0x0200)
++#define    MAIN_MSCA_ADDR_CH1_RSZ_STEP                        (MSCALER0_BASE + 0x0204)
++#define    MAIN_MSCA_ADDR_CH1_CROP_POS                        (MSCALER0_BASE + 0x0228)
++#define    MAIN_MSCA_ADDR_CH1_CROP_SIZE                       (MSCALER0_BASE + 0x022c)
++#define    MAIN_MSCA_ADDR_CH1_FR_CTRL_LOOP                    (MSCALER0_BASE + 0x0230)
++#define    MAIN_MSCA_ADDR_CH1_FR_CTRL_MASK                    (MSCALER0_BASE + 0x0234)
++#define    MAIN_MSCA_ADDR_CH1_MS0_POS                         (MSCALER0_BASE + 0x0238)
++#define    MAIN_MSCA_ADDR_CH1_MS0_SIZE                        (MSCALER0_BASE + 0x023c)
++#define    MAIN_MSCA_ADDR_CH1_MS0_VALUE                       (MSCALER0_BASE + 0x0240)
++#define    MAIN_MSCA_ADDR_CH1_MS1_POS                         (MSCALER0_BASE + 0x0244)
++#define    MAIN_MSCA_ADDR_CH1_MS1_SIZE                        (MSCALER0_BASE + 0x0248)
++#define    MAIN_MSCA_ADDR_CH1_MS1_VALUE                       (MSCALER0_BASE + 0x024c)
++#define    MAIN_MSCA_ADDR_CH1_MS2_POS                         (MSCALER0_BASE + 0x0250)
++#define    MAIN_MSCA_ADDR_CH1_MS2_SIZE                        (MSCALER0_BASE + 0x0254)
++#define    MAIN_MSCA_ADDR_CH1_MS2_VALUE                       (MSCALER0_BASE + 0x0258)
++#define    MAIN_MSCA_ADDR_CH1_MS3_POS                         (MSCALER0_BASE + 0x025c)
++#define    MAIN_MSCA_ADDR_CH1_MS3_SIZE                        (MSCALER0_BASE + 0x0260)
++#define    MAIN_MSCA_ADDR_CH1_MS3_VALUE                       (MSCALER0_BASE + 0x0264)
++#define    MAIN_MSCA_ADDR_CH1_OUT_FMT                         (MSCALER0_BASE + 0x0268)
++#define    MAIN_MSCA_ADDR_CH1_DMAOUT_Y_ADDR                   (MSCALER0_BASE + 0x026c)
++#define    MAIN_MSCA_ADDR_CH1_Y_ADDR_FIFO_STA                 (MSCALER0_BASE + 0x0270)
++#define    MAIN_MSCA_ADDR_CH1_DMAOUT_Y_LAST_ADDR              (MSCALER0_BASE + 0x0274)
++#define    MAIN_MSCA_ADDR_CH1_Y_LAST_ADDR_FIFO_STA            (MSCALER0_BASE + 0x027c)
++#define    MAIN_MSCA_ADDR_CH1_DMAOUT_Y_STRIDE                 (MSCALER0_BASE + 0x0280)
++#define    MAIN_MSCA_ADDR_CH1_DMAOUT_UV_ADDR                  (MSCALER0_BASE + 0x0284)
++#define    MAIN_MSCA_ADDR_CH1_UV_ADDR_FIFO_STA                (MSCALER0_BASE + 0x0288)
++#define    MAIN_MSCA_ADDR_CH1_DMAOUT_UV_LAST_ADDR             (MSCALER0_BASE + 0x028c)
++#define    MAIN_MSCA_ADDR_CH1_UV_LAST_ADDR_FIFO_STA           (MSCALER0_BASE + 0x0294)
++#define    MAIN_MSCA_ADDR_CH1_DMAOUT_UV_STRIDE                (MSCALER0_BASE + 0x0298)
++#define    MAIN_MSCA_ADDR_CH1_DMAOUT_Y_ADDR_CLR               (MSCALER0_BASE + 0x029c)
++#define    MAIN_MSCA_ADDR_CH1_DMAOUT_UV_ADDR_CLR              (MSCALER0_BASE + 0x02a0)
++#define    MAIN_MSCA_ADDR_CH1_DMAOUT_Y_LAST_ADDR_CLR          (MSCALER0_BASE + 0x02a4)
++#define    MAIN_MSCA_ADDR_CH1_DMAOUT_UV_LAST_ADDR_CLR         (MSCALER0_BASE + 0x02a8)
++#define    MAIN_MSCA_ADDR_CH1_DMAOUT_Y_ADDR_SEL               (MSCALER0_BASE + 0x02ac)
++#define    MAIN_MSCA_ADDR_CH1_DMAOUT_UV_ADDR_SEL              (MSCALER0_BASE + 0x02b0)
++#define    MAIN_MSCA_ADDR_CH1_COE_ZERO_VRSZ_H                 (MSCALER0_BASE + 0x02c0)
++#define    MAIN_MSCA_ADDR_CH1_COE_ZERO_VRSZ_L                 (MSCALER0_BASE + 0x02c4)
++#define    MAIN_MSCA_ADDR_CH1_COE_ZERO_HRSZ_H                 (MSCALER0_BASE + 0x02c8)
++#define    MAIN_MSCA_ADDR_CH1_COE_ZERO_HRSZ_L                 (MSCALER0_BASE + 0x02cc)
++#define    MAIN_MSCA_ADDR_CH1_COE_OFT                         (MSCALER0_BASE + 0x02d0)
++#define    MAIN_MSCA_ADDR_CH1_ARF                             (MSCALER0_BASE + 0x02f0)
++#define    MAIN_MSCA_ADDR_CH1_CLR                             (MSCALER0_BASE + 0x02f4)
++#define    MAIN_MSCA_ADDR_CH2_RSZ_SIZE                        (MSCALER0_BASE + 0x0300)
++#define    MAIN_MSCA_ADDR_CH2_RSZ_STEP                        (MSCALER0_BASE + 0x0304)
++#define    MAIN_MSCA_ADDR_CH2_CROP_POS                        (MSCALER0_BASE + 0x0328)
++#define    MAIN_MSCA_ADDR_CH2_CROP_SIZE                       (MSCALER0_BASE + 0x032c)
++#define    MAIN_MSCA_ADDR_CH2_FR_CTRL_LOOP                    (MSCALER0_BASE + 0x0330)
++#define    MAIN_MSCA_ADDR_CH2_FR_CTRL_MASK                    (MSCALER0_BASE + 0x0334)
++#define    MAIN_MSCA_ADDR_CH2_MS0_POS                         (MSCALER0_BASE + 0x0338)
++#define    MAIN_MSCA_ADDR_CH2_MS0_SIZE                        (MSCALER0_BASE + 0x033c)
++#define    MAIN_MSCA_ADDR_CH2_MS0_VALUE                       (MSCALER0_BASE + 0x0340)
++#define    MAIN_MSCA_ADDR_CH2_MS1_POS                         (MSCALER0_BASE + 0x0344)
++#define    MAIN_MSCA_ADDR_CH2_MS1_SIZE                        (MSCALER0_BASE + 0x0348)
++#define    MAIN_MSCA_ADDR_CH2_MS1_VALUE                       (MSCALER0_BASE + 0x034c)
++#define    MAIN_MSCA_ADDR_CH2_MS2_POS                         (MSCALER0_BASE + 0x0350)
++#define    MAIN_MSCA_ADDR_CH2_MS2_SIZE                        (MSCALER0_BASE + 0x0354)
++#define    MAIN_MSCA_ADDR_CH2_MS2_VALUE                       (MSCALER0_BASE + 0x0358)
++#define    MAIN_MSCA_ADDR_CH2_MS3_POS                         (MSCALER0_BASE + 0x035c)
++#define    MAIN_MSCA_ADDR_CH2_MS3_SIZE                        (MSCALER0_BASE + 0x0360)
++#define    MAIN_MSCA_ADDR_CH2_MS3_VALUE                       (MSCALER0_BASE + 0x0364)
++#define    MAIN_MSCA_ADDR_CH2_OUT_FMT                         (MSCALER0_BASE + 0x0368)
++#define    MAIN_MSCA_ADDR_CH2_DMAOUT_Y_ADDR                   (MSCALER0_BASE + 0x036c)
++#define    MAIN_MSCA_ADDR_CH2_Y_ADDR_FIFO_STA                 (MSCALER0_BASE + 0x0370)
++#define    MAIN_MSCA_ADDR_CH2_DMAOUT_Y_LAST_ADDR              (MSCALER0_BASE + 0x0374)
++#define    MAIN_MSCA_ADDR_CH2_Y_LAST_ADDR_FIFO_STA            (MSCALER0_BASE + 0x037c)
++#define    MAIN_MSCA_ADDR_CH2_DMAOUT_Y_STRIDE                 (MSCALER0_BASE + 0x0380)
++#define    MAIN_MSCA_ADDR_CH2_DMAOUT_UV_ADDR                  (MSCALER0_BASE + 0x0384)
++#define    MAIN_MSCA_ADDR_CH2_UV_ADDR_FIFO_STA                (MSCALER0_BASE + 0x0388)
++#define    MAIN_MSCA_ADDR_CH2_DMAOUT_UV_LAST_ADDR             (MSCALER0_BASE + 0x038c)
++#define    MAIN_MSCA_ADDR_CH2_UV_LAST_ADDR_FIFO_STA           (MSCALER0_BASE + 0x0394)
++#define    MAIN_MSCA_ADDR_CH2_DMAOUT_UV_STRIDE                (MSCALER0_BASE + 0x0398)
++#define    MAIN_MSCA_ADDR_CH2_DMAOUT_Y_ADDR_CLR               (MSCALER0_BASE + 0x039c)
++#define    MAIN_MSCA_ADDR_CH2_DMAOUT_UV_ADDR_CLR              (MSCALER0_BASE + 0x03a0)
++#define    MAIN_MSCA_ADDR_CH2_DMAOUT_Y_LAST_ADDR_CLR          (MSCALER0_BASE + 0x03a4)
++#define    MAIN_MSCA_ADDR_CH2_DMAOUT_UV_LAST_ADDR_CLR         (MSCALER0_BASE + 0x03a8)
++#define    MAIN_MSCA_ADDR_CH2_DMAOUT_Y_ADDR_SEL               (MSCALER0_BASE + 0x03ac)
++#define    MAIN_MSCA_ADDR_CH2_DMAOUT_UV_ADDR_SEL              (MSCALER0_BASE + 0x03b0)
++#define    MAIN_MSCA_ADDR_CH2_COE_ZERO_VRSZ_H                 (MSCALER0_BASE + 0x03c0)
++#define    MAIN_MSCA_ADDR_CH2_COE_ZERO_VRSZ_L                 (MSCALER0_BASE + 0x03c4)
++#define    MAIN_MSCA_ADDR_CH2_COE_ZERO_HRSZ_H                 (MSCALER0_BASE + 0x03c8)
++#define    MAIN_MSCA_ADDR_CH2_COE_ZERO_HRSZ_L                 (MSCALER0_BASE + 0x03cc)
++#define    MAIN_MSCA_ADDR_CH2_COE_OFT                         (MSCALER0_BASE + 0x03d0)
++#define    MAIN_MSCA_ADDR_CH2_ARF                             (MSCALER0_BASE + 0x03f0)
++#define    MAIN_MSCA_ADDR_CH2_CLR                             (MSCALER0_BASE + 0x03f4)
++#define    MAIN_MSCA_ADDR_CH0_LINE0_POS                       (MSCALER0_BASE + 0x0400)
++#define    MAIN_MSCA_ADDR_CH0_LINE0_SIZE                      (MSCALER0_BASE + 0x0404)
++#define    MAIN_MSCA_ADDR_CH0_LINE0_PAR0                      (MSCALER0_BASE + 0x0408)
++#define    MAIN_MSCA_ADDR_CH0_LINE0_PAR1                      (MSCALER0_BASE + 0x040c)
++#define    MAIN_MSCA_ADDR_CH0_LINE1_POS                       (MSCALER0_BASE + 0x0410)
++#define    MAIN_MSCA_ADDR_CH0_LINE1_SIZE                      (MSCALER0_BASE + 0x0414)
++#define    MAIN_MSCA_ADDR_CH0_LINE1_PAR0                      (MSCALER0_BASE + 0x0418)
++#define    MAIN_MSCA_ADDR_CH0_LINE1_PAR1                      (MSCALER0_BASE + 0x041c)
++#define    MAIN_MSCA_ADDR_CH0_LINE2_POS                       (MSCALER0_BASE + 0x0420)
++#define    MAIN_MSCA_ADDR_CH0_LINE2_SIZE                      (MSCALER0_BASE + 0x0424)
++#define    MAIN_MSCA_ADDR_CH0_LINE2_PAR0                      (MSCALER0_BASE + 0x0428)
++#define    MAIN_MSCA_ADDR_CH0_LINE2_PAR1                      (MSCALER0_BASE + 0x042c)
++#define    MAIN_MSCA_ADDR_CH0_LINE3_POS                       (MSCALER0_BASE + 0x0430)
++#define    MAIN_MSCA_ADDR_CH0_LINE3_SIZE                      (MSCALER0_BASE + 0x0434)
++#define    MAIN_MSCA_ADDR_CH0_LINE3_PAR0                      (MSCALER0_BASE + 0x0438)
++#define    MAIN_MSCA_ADDR_CH0_LINE3_PAR1                      (MSCALER0_BASE + 0x043c)
++#define    MAIN_MSCA_ADDR_CH0_LINE4_POS                       (MSCALER0_BASE + 0x0440)
++#define    MAIN_MSCA_ADDR_CH0_LINE4_SIZE                      (MSCALER0_BASE + 0x0444)
++#define    MAIN_MSCA_ADDR_CH0_LINE4_PAR0                      (MSCALER0_BASE + 0x0448)
++#define    MAIN_MSCA_ADDR_CH0_LINE4_PAR1                      (MSCALER0_BASE + 0x044c)
++#define    MAIN_MSCA_ADDR_CH0_LINE5_POS                       (MSCALER0_BASE + 0x0450)
++#define    MAIN_MSCA_ADDR_CH0_LINE5_SIZE                      (MSCALER0_BASE + 0x0454)
++#define    MAIN_MSCA_ADDR_CH0_LINE5_PAR0                      (MSCALER0_BASE + 0x0458)
++#define    MAIN_MSCA_ADDR_CH0_LINE5_PAR1                      (MSCALER0_BASE + 0x045c)
++#define    MAIN_MSCA_ADDR_CH0_LINE6_POS                       (MSCALER0_BASE + 0x0460)
++#define    MAIN_MSCA_ADDR_CH0_LINE6_SIZE                      (MSCALER0_BASE + 0x0464)
++#define    MAIN_MSCA_ADDR_CH0_LINE6_PAR0                      (MSCALER0_BASE + 0x0468)
++#define    MAIN_MSCA_ADDR_CH0_LINE6_PAR1                      (MSCALER0_BASE + 0x046c)
++#define    MAIN_MSCA_ADDR_CH0_LINE7_POS                       (MSCALER0_BASE + 0x0470)
++#define    MAIN_MSCA_ADDR_CH0_LINE7_SIZE                      (MSCALER0_BASE + 0x0474)
++#define    MAIN_MSCA_ADDR_CH0_LINE7_PAR0                      (MSCALER0_BASE + 0x0478)
++#define    MAIN_MSCA_ADDR_CH0_LINE7_PAR1                      (MSCALER0_BASE + 0x047c)
++#define    MAIN_MSCA_ADDR_CH0_LINE8_POS                       (MSCALER0_BASE + 0x0480)
++#define    MAIN_MSCA_ADDR_CH0_LINE8_SIZE                      (MSCALER0_BASE + 0x0484)
++#define    MAIN_MSCA_ADDR_CH0_LINE8_PAR0                      (MSCALER0_BASE + 0x0488)
++#define    MAIN_MSCA_ADDR_CH0_LINE8_PAR1                      (MSCALER0_BASE + 0x048c)
++#define    MAIN_MSCA_ADDR_CH0_LINE9_POS                       (MSCALER0_BASE + 0x0490)
++#define    MAIN_MSCA_ADDR_CH0_LINE9_SIZE                      (MSCALER0_BASE + 0x0494)
++#define    MAIN_MSCA_ADDR_CH0_LINE9_PAR0                      (MSCALER0_BASE + 0x0498)
++#define    MAIN_MSCA_ADDR_CH0_LINE9_PAR1                      (MSCALER0_BASE + 0x049c)
++#define    MAIN_MSCA_ADDR_CH0_LINE10_POS                      (MSCALER0_BASE + 0x04a0)
++#define    MAIN_MSCA_ADDR_CH0_LINE10_SIZE                     (MSCALER0_BASE + 0x04a4)
++#define    MAIN_MSCA_ADDR_CH0_LINE10_PAR0                     (MSCALER0_BASE + 0x04a8)
++#define    MAIN_MSCA_ADDR_CH0_LINE10_PAR1                     (MSCALER0_BASE + 0x04ac)
++#define    MAIN_MSCA_ADDR_CH0_LINE11_POS                      (MSCALER0_BASE + 0x04b0)
++#define    MAIN_MSCA_ADDR_CH0_LINE11_SIZE                     (MSCALER0_BASE + 0x04b4)
++#define    MAIN_MSCA_ADDR_CH0_LINE11_PAR0                     (MSCALER0_BASE + 0x04b8)
++#define    MAIN_MSCA_ADDR_CH0_LINE11_PAR1                     (MSCALER0_BASE + 0x04bc)
++#define    MAIN_MSCA_ADDR_CH0_LINE12_POS                      (MSCALER0_BASE + 0x04c0)
++#define    MAIN_MSCA_ADDR_CH0_LINE12_SIZE                     (MSCALER0_BASE + 0x04c4)
++#define    MAIN_MSCA_ADDR_CH0_LINE12_PAR0                     (MSCALER0_BASE + 0x04c8)
++#define    MAIN_MSCA_ADDR_CH0_LINE12_PAR1                     (MSCALER0_BASE + 0x04cc)
++#define    MAIN_MSCA_ADDR_CH0_LINE13_POS                      (MSCALER0_BASE + 0x04d0)
++#define    MAIN_MSCA_ADDR_CH0_LINE13_SIZE                     (MSCALER0_BASE + 0x04d4)
++#define    MAIN_MSCA_ADDR_CH0_LINE13_PAR0                     (MSCALER0_BASE + 0x04d8)
++#define    MAIN_MSCA_ADDR_CH0_LINE13_PAR1                     (MSCALER0_BASE + 0x04dc)
++#define    MAIN_MSCA_ADDR_CH0_LINE14_POS                      (MSCALER0_BASE + 0x04e0)
++#define    MAIN_MSCA_ADDR_CH0_LINE14_SIZE                     (MSCALER0_BASE + 0x04e4)
++#define    MAIN_MSCA_ADDR_CH0_LINE14_PAR0                     (MSCALER0_BASE + 0x04e8)
++#define    MAIN_MSCA_ADDR_CH0_LINE14_PAR1                     (MSCALER0_BASE + 0x04ec)
++#define    MAIN_MSCA_ADDR_CH0_LINE15_POS                      (MSCALER0_BASE + 0x04f0)
++#define    MAIN_MSCA_ADDR_CH0_LINE15_SIZE                     (MSCALER0_BASE + 0x04f4)
++#define    MAIN_MSCA_ADDR_CH0_LINE15_PAR0                     (MSCALER0_BASE + 0x04f8)
++#define    MAIN_MSCA_ADDR_CH0_LINE15_PAR1                     (MSCALER0_BASE + 0x04fc)
++#define    MAIN_MSCA_ADDR_CH1_LINE0_POS                       (MSCALER0_BASE + 0x0500)
++#define    MAIN_MSCA_ADDR_CH1_LINE0_SIZE                      (MSCALER0_BASE + 0x0504)
++#define    MAIN_MSCA_ADDR_CH1_LINE0_PAR0                      (MSCALER0_BASE + 0x0508)
++#define    MAIN_MSCA_ADDR_CH1_LINE0_PAR1                      (MSCALER0_BASE + 0x050c)
++#define    MAIN_MSCA_ADDR_CH1_LINE1_POS                       (MSCALER0_BASE + 0x0510)
++#define    MAIN_MSCA_ADDR_CH1_LINE1_SIZE                      (MSCALER0_BASE + 0x0514)
++#define    MAIN_MSCA_ADDR_CH1_LINE1_PAR0                      (MSCALER0_BASE + 0x0518)
++#define    MAIN_MSCA_ADDR_CH1_LINE1_PAR1                      (MSCALER0_BASE + 0x051c)
++#define    MAIN_MSCA_ADDR_CH1_LINE2_POS                       (MSCALER0_BASE + 0x0520)
++#define    MAIN_MSCA_ADDR_CH1_LINE2_SIZE                      (MSCALER0_BASE + 0x0524)
++#define    MAIN_MSCA_ADDR_CH1_LINE2_PAR0                      (MSCALER0_BASE + 0x0528)
++#define    MAIN_MSCA_ADDR_CH1_LINE2_PAR1                      (MSCALER0_BASE + 0x052c)
++#define    MAIN_MSCA_ADDR_CH1_LINE3_POS                       (MSCALER0_BASE + 0x0530)
++#define    MAIN_MSCA_ADDR_CH1_LINE3_SIZE                      (MSCALER0_BASE + 0x0534)
++#define    MAIN_MSCA_ADDR_CH1_LINE3_PAR0                      (MSCALER0_BASE + 0x0538)
++#define    MAIN_MSCA_ADDR_CH1_LINE3_PAR1                      (MSCALER0_BASE + 0x053c)
++#define    MAIN_MSCA_ADDR_CH1_LINE4_POS                       (MSCALER0_BASE + 0x0540)
++#define    MAIN_MSCA_ADDR_CH1_LINE4_SIZE                      (MSCALER0_BASE + 0x0544)
++#define    MAIN_MSCA_ADDR_CH1_LINE4_PAR0                      (MSCALER0_BASE + 0x0548)
++#define    MAIN_MSCA_ADDR_CH1_LINE4_PAR1                      (MSCALER0_BASE + 0x054c)
++#define    MAIN_MSCA_ADDR_CH1_LINE5_POS                       (MSCALER0_BASE + 0x0550)
++#define    MAIN_MSCA_ADDR_CH1_LINE5_SIZE                      (MSCALER0_BASE + 0x0554)
++#define    MAIN_MSCA_ADDR_CH1_LINE5_PAR0                      (MSCALER0_BASE + 0x0558)
++#define    MAIN_MSCA_ADDR_CH1_LINE5_PAR1                      (MSCALER0_BASE + 0x055c)
++#define    MAIN_MSCA_ADDR_CH1_LINE6_POS                       (MSCALER0_BASE + 0x0560)
++#define    MAIN_MSCA_ADDR_CH1_LINE6_SIZE                      (MSCALER0_BASE + 0x0564)
++#define    MAIN_MSCA_ADDR_CH1_LINE6_PAR0                      (MSCALER0_BASE + 0x0568)
++#define    MAIN_MSCA_ADDR_CH1_LINE6_PAR1                      (MSCALER0_BASE + 0x056c)
++#define    MAIN_MSCA_ADDR_CH1_LINE7_POS                       (MSCALER0_BASE + 0x0570)
++#define    MAIN_MSCA_ADDR_CH1_LINE7_SIZE                      (MSCALER0_BASE + 0x0574)
++#define    MAIN_MSCA_ADDR_CH1_LINE7_PAR0                      (MSCALER0_BASE + 0x0578)
++#define    MAIN_MSCA_ADDR_CH1_LINE7_PAR1                      (MSCALER0_BASE + 0x057c)
++#define    MAIN_MSCA_ADDR_CH1_LINE8_POS                       (MSCALER0_BASE + 0x0580)
++#define    MAIN_MSCA_ADDR_CH1_LINE8_SIZE                      (MSCALER0_BASE + 0x0584)
++#define    MAIN_MSCA_ADDR_CH1_LINE8_PAR0                      (MSCALER0_BASE + 0x0588)
++#define    MAIN_MSCA_ADDR_CH1_LINE8_PAR1                      (MSCALER0_BASE + 0x058c)
++#define    MAIN_MSCA_ADDR_CH1_LINE9_POS                       (MSCALER0_BASE + 0x0590)
++#define    MAIN_MSCA_ADDR_CH1_LINE9_SIZE                      (MSCALER0_BASE + 0x0594)
++#define    MAIN_MSCA_ADDR_CH1_LINE9_PAR0                      (MSCALER0_BASE + 0x0598)
++#define    MAIN_MSCA_ADDR_CH1_LINE9_PAR1                      (MSCALER0_BASE + 0x059c)
++#define    MAIN_MSCA_ADDR_CH1_LINE10_POS                      (MSCALER0_BASE + 0x05a0)
++#define    MAIN_MSCA_ADDR_CH1_LINE10_SIZE                     (MSCALER0_BASE + 0x05a4)
++#define    MAIN_MSCA_ADDR_CH1_LINE10_PAR0                     (MSCALER0_BASE + 0x05a8)
++#define    MAIN_MSCA_ADDR_CH1_LINE10_PAR1                     (MSCALER0_BASE + 0x05ac)
++#define    MAIN_MSCA_ADDR_CH1_LINE11_POS                      (MSCALER0_BASE + 0x05b0)
++#define    MAIN_MSCA_ADDR_CH1_LINE11_SIZE                     (MSCALER0_BASE + 0x05b4)
++#define    MAIN_MSCA_ADDR_CH1_LINE11_PAR0                     (MSCALER0_BASE + 0x05b8)
++#define    MAIN_MSCA_ADDR_CH1_LINE11_PAR1                     (MSCALER0_BASE + 0x05bc)
++#define    MAIN_MSCA_ADDR_CH1_LINE12_POS                      (MSCALER0_BASE + 0x05c0)
++#define    MAIN_MSCA_ADDR_CH1_LINE12_SIZE                     (MSCALER0_BASE + 0x05c4)
++#define    MAIN_MSCA_ADDR_CH1_LINE12_PAR0                     (MSCALER0_BASE + 0x05c8)
++#define    MAIN_MSCA_ADDR_CH1_LINE12_PAR1                     (MSCALER0_BASE + 0x05cc)
++#define    MAIN_MSCA_ADDR_CH1_LINE13_POS                      (MSCALER0_BASE + 0x05d0)
++#define    MAIN_MSCA_ADDR_CH1_LINE13_SIZE                     (MSCALER0_BASE + 0x05d4)
++#define    MAIN_MSCA_ADDR_CH1_LINE13_PAR0                     (MSCALER0_BASE + 0x05d8)
++#define    MAIN_MSCA_ADDR_CH1_LINE13_PAR1                     (MSCALER0_BASE + 0x05dc)
++#define    MAIN_MSCA_ADDR_CH1_LINE14_POS                      (MSCALER0_BASE + 0x05e0)
++#define    MAIN_MSCA_ADDR_CH1_LINE14_SIZE                     (MSCALER0_BASE + 0x05e4)
++#define    MAIN_MSCA_ADDR_CH1_LINE14_PAR0                     (MSCALER0_BASE + 0x05e8)
++#define    MAIN_MSCA_ADDR_CH1_LINE14_PAR1                     (MSCALER0_BASE + 0x05ec)
++#define    MAIN_MSCA_ADDR_CH1_LINE15_POS                      (MSCALER0_BASE + 0x05f0)
++#define    MAIN_MSCA_ADDR_CH1_LINE15_SIZE                     (MSCALER0_BASE + 0x05f4)
++#define    MAIN_MSCA_ADDR_CH1_LINE15_PAR0                     (MSCALER0_BASE + 0x05f8)
++#define    MAIN_MSCA_ADDR_CH1_LINE15_PAR1                     (MSCALER0_BASE + 0x05fc)
++#define    MAIN_MSCA_ADDR_CH0_OSD0_POS                        (MSCALER0_BASE + 0x0600)
++#define    MAIN_MSCA_ADDR_CH0_OSD0_SIZE                       (MSCALER0_BASE + 0x0604)
++#define    MAIN_MSCA_ADDR_CH0_OSD0_ADDR                       (MSCALER0_BASE + 0x0608)
++#define    MAIN_MSCA_ADDR_CH0_OSD0_STRIDE                     (MSCALER0_BASE + 0x060c)
++#define    MAIN_MSCA_ADDR_CH0_OSD1_POS                        (MSCALER0_BASE + 0x0610)
++#define    MAIN_MSCA_ADDR_CH0_OSD1_SIZE                       (MSCALER0_BASE + 0x0614)
++#define    MAIN_MSCA_ADDR_CH0_OSD1_ADDR                       (MSCALER0_BASE + 0x0618)
++#define    MAIN_MSCA_ADDR_CH0_OSD1_STRIDE                     (MSCALER0_BASE + 0x061c)
++#define    MAIN_MSCA_ADDR_CH0_OSD2_POS                        (MSCALER0_BASE + 0x0620)
++#define    MAIN_MSCA_ADDR_CH0_OSD2_SIZE                       (MSCALER0_BASE + 0x0624)
++#define    MAIN_MSCA_ADDR_CH0_OSD2_ADDR                       (MSCALER0_BASE + 0x0628)
++#define    MAIN_MSCA_ADDR_CH0_OSD2_STRIDE                     (MSCALER0_BASE + 0x062c)
++#define    MAIN_MSCA_ADDR_CH0_OSD3_POS                        (MSCALER0_BASE + 0x0630)
++#define    MAIN_MSCA_ADDR_CH0_OSD3_SIZE                       (MSCALER0_BASE + 0x0634)
++#define    MAIN_MSCA_ADDR_CH0_OSD3_ADDR                       (MSCALER0_BASE + 0x0638)
++#define    MAIN_MSCA_ADDR_CH0_OSD3_STRIDE                     (MSCALER0_BASE + 0x063c)
++#define    MAIN_MSCA_ADDR_CH0_OSD4_POS                        (MSCALER0_BASE + 0x0640)
++#define    MAIN_MSCA_ADDR_CH0_OSD4_SIZE                       (MSCALER0_BASE + 0x0644)
++#define    MAIN_MSCA_ADDR_CH0_OSD4_ADDR                       (MSCALER0_BASE + 0x0648)
++#define    MAIN_MSCA_ADDR_CH0_OSD4_STRIDE                     (MSCALER0_BASE + 0x064c)
++#define    MAIN_MSCA_ADDR_CH0_OSD5_POS                        (MSCALER0_BASE + 0x0650)
++#define    MAIN_MSCA_ADDR_CH0_OSD5_SIZE                       (MSCALER0_BASE + 0x0654)
++#define    MAIN_MSCA_ADDR_CH0_OSD5_ADDR                       (MSCALER0_BASE + 0x0658)
++#define    MAIN_MSCA_ADDR_CH0_OSD5_STRIDE                     (MSCALER0_BASE + 0x065c)
++#define    MAIN_MSCA_ADDR_CH0_OSD6_POS                        (MSCALER0_BASE + 0x0660)
++#define    MAIN_MSCA_ADDR_CH0_OSD6_SIZE                       (MSCALER0_BASE + 0x0664)
++#define    MAIN_MSCA_ADDR_CH0_OSD6_ADDR                       (MSCALER0_BASE + 0x0668)
++#define    MAIN_MSCA_ADDR_CH0_OSD6_STRIDE                     (MSCALER0_BASE + 0x066c)
++#define    MAIN_MSCA_ADDR_CH0_OSD7_POS                        (MSCALER0_BASE + 0x0670)
++#define    MAIN_MSCA_ADDR_CH0_OSD7_SIZE                       (MSCALER0_BASE + 0x0674)
++#define    MAIN_MSCA_ADDR_CH0_OSD7_ADDR                       (MSCALER0_BASE + 0x0678)
++#define    MAIN_MSCA_ADDR_CH0_OSD7_STRIDE                     (MSCALER0_BASE + 0x067c)
++#define    MAIN_MSCA_ADDR_CH1_OSD0_POS                        (MSCALER0_BASE + 0x0680)
++#define    MAIN_MSCA_ADDR_CH1_OSD0_SIZE                       (MSCALER0_BASE + 0x0684)
++#define    MAIN_MSCA_ADDR_CH1_OSD0_ADDR                       (MSCALER0_BASE + 0x0688)
++#define    MAIN_MSCA_ADDR_CH1_OSD0_STRIDE                     (MSCALER0_BASE + 0x068c)
++#define    MAIN_MSCA_ADDR_CH1_OSD1_POS                        (MSCALER0_BASE + 0x0690)
++#define    MAIN_MSCA_ADDR_CH1_OSD1_SIZE                       (MSCALER0_BASE + 0x0694)
++#define    MAIN_MSCA_ADDR_CH1_OSD1_ADDR                       (MSCALER0_BASE + 0x0698)
++#define    MAIN_MSCA_ADDR_CH1_OSD1_STRIDE                     (MSCALER0_BASE + 0x069c)
++#define    MAIN_MSCA_ADDR_CH1_OSD2_POS                        (MSCALER0_BASE + 0x06a0)
++#define    MAIN_MSCA_ADDR_CH1_OSD2_SIZE                       (MSCALER0_BASE + 0x06a4)
++#define    MAIN_MSCA_ADDR_CH1_OSD2_ADDR                       (MSCALER0_BASE + 0x06a8)
++#define    MAIN_MSCA_ADDR_CH1_OSD2_STRIDE                     (MSCALER0_BASE + 0x06ac)
++#define    MAIN_MSCA_ADDR_CH1_OSD3_POS                        (MSCALER0_BASE + 0x06b0)
++#define    MAIN_MSCA_ADDR_CH1_OSD3_SIZE                       (MSCALER0_BASE + 0x06b4)
++#define    MAIN_MSCA_ADDR_CH1_OSD3_ADDR                       (MSCALER0_BASE + 0x06b8)
++#define    MAIN_MSCA_ADDR_CH1_OSD3_STRIDE                     (MSCALER0_BASE + 0x06bc)
++#define    MAIN_MSCA_ADDR_CH1_OSD4_POS                        (MSCALER0_BASE + 0x06c0)
++#define    MAIN_MSCA_ADDR_CH1_OSD4_SIZE                       (MSCALER0_BASE + 0x06c4)
++#define    MAIN_MSCA_ADDR_CH1_OSD4_ADDR                       (MSCALER0_BASE + 0x06c8)
++#define    MAIN_MSCA_ADDR_CH1_OSD4_STRIDE                     (MSCALER0_BASE + 0x06cc)
++#define    MAIN_MSCA_ADDR_CH1_OSD5_POS                        (MSCALER0_BASE + 0x06d0)
++#define    MAIN_MSCA_ADDR_CH1_OSD5_SIZE                       (MSCALER0_BASE + 0x06d4)
++#define    MAIN_MSCA_ADDR_CH1_OSD5_ADDR                       (MSCALER0_BASE + 0x06d8)
++#define    MAIN_MSCA_ADDR_CH1_OSD5_STRIDE                     (MSCALER0_BASE + 0x06dc)
++#define    MAIN_MSCA_ADDR_CH1_OSD6_POS                        (MSCALER0_BASE + 0x06e0)
++#define    MAIN_MSCA_ADDR_CH1_OSD6_SIZE                       (MSCALER0_BASE + 0x06e4)
++#define    MAIN_MSCA_ADDR_CH1_OSD6_ADDR                       (MSCALER0_BASE + 0x06e8)
++#define    MAIN_MSCA_ADDR_CH1_OSD6_STRIDE                     (MSCALER0_BASE + 0x06ec)
++#define    MAIN_MSCA_ADDR_CH1_OSD7_POS                        (MSCALER0_BASE + 0x06f0)
++#define    MAIN_MSCA_ADDR_CH1_OSD7_SIZE                       (MSCALER0_BASE + 0x06f4)
++#define    MAIN_MSCA_ADDR_CH1_OSD7_ADDR                       (MSCALER0_BASE + 0x06f8)
++#define    MAIN_MSCA_ADDR_CH1_OSD7_STRIDE                     (MSCALER0_BASE + 0x06fc)
++#define    MAIN_MSCA_ADDR_BACK_DOOR                           (MSCALER0_BASE + 0x0700)
++#define    MAIN_MSCA_ADDR_DBG__00_00                          (MSCALER0_BASE + 0x0710)
++#define    MAIN_MSCA_ADDR_DBG__01_01                          (MSCALER0_BASE + 0x0714)
++#define    MAIN_MSCA_ADDR_DBG__02_02                          (MSCALER0_BASE + 0x0718)
++#define    MAIN_MSCA_ADDR_DBG__03_03                          (MSCALER0_BASE + 0x071c)
++#define    MAIN_MSCA_ADDR_DBG__04_04                          (MSCALER0_BASE + 0x0720)
++#define    MAIN_MSCA_ADDR_DBG__05_05                          (MSCALER0_BASE + 0x0724)
++#define    MAIN_MSCA_ADDR_DBG__06_06                          (MSCALER0_BASE + 0x0728)
++#define    MAIN_MSCA_ADDR_DBG__07_07                          (MSCALER0_BASE + 0x072c)
++#define    MAIN_MSCA_ADDR_DBG__08_08                          (MSCALER0_BASE + 0x0730)
++#define    MAIN_MSCA_ADDR_DBG__09_09                          (MSCALER0_BASE + 0x0734)
++#define    MAIN_MSCA_ADDR_DBG__10_10                          (MSCALER0_BASE + 0x0738)
++#define    MAIN_MSCA_ADDR_DBG__11_11                          (MSCALER0_BASE + 0x073c)
++#define    MAIN_MSCA_ADDR_DBG__12_12                          (MSCALER0_BASE + 0x0740)
++#define    MAIN_MSCA_ADDR_DBG__13_13                          (MSCALER0_BASE + 0x0744)
++#define    MAIN_MSCA_ADDR_DBG__14_14                          (MSCALER0_BASE + 0x0748)
++#define    MAIN_MSCA_ADDR_DBG__15_15                          (MSCALER0_BASE + 0x074c)
++#define    MAIN_MSCA_ADDR_DBG__16_16                          (MSCALER0_BASE + 0x0750)
++#define    MAIN_MSCA_ADDR_DBG__17_17                          (MSCALER0_BASE + 0x0754)
++#define    MAIN_MSCA_ADDR_DBG__18_18                          (MSCALER0_BASE + 0x0758)
++#define    MAIN_MSCA_ADDR_DBG__19_19                          (MSCALER0_BASE + 0x075c)
++#define    MAIN_MSCA_ADDR_DBG__20_20                          (MSCALER0_BASE + 0x0760)
++#define    MAIN_MSCA_ADDR_DBG__21_21                          (MSCALER0_BASE + 0x0764)
++#define    MAIN_MSCA_ADDR_DBG__22_22                          (MSCALER0_BASE + 0x0768)
++#define    MAIN_MSCA_ADDR_DBG__23_23                          (MSCALER0_BASE + 0x076c)
++#define    MAIN_MSCA_ADDR_DBG__24_24                          (MSCALER0_BASE + 0x0770)
++#define    MAIN_MSCA_ADDR_DBG__25_25                          (MSCALER0_BASE + 0x0774)
++#define    MAIN_MSCA_ADDR_DBG__26_26                          (MSCALER0_BASE + 0x0778)
++#define    MAIN_MSCA_ADDR_DBG__27_27                          (MSCALER0_BASE + 0x077c)
++#define    MAIN_MSCA_ADDR_DBG__28_28                          (MSCALER0_BASE + 0x0780)
++#define    MAIN_MSCA_ADDR_DBG__29_29                          (MSCALER0_BASE + 0x0784)
++#define    MAIN_MSCA_ADDR_DBG__30_30                          (MSCALER0_BASE + 0x0788)
++#define    MAIN_MSCA_ADDR_DBG__31_31                          (MSCALER0_BASE + 0x078c)
++#define    MAIN_MSCA_ADDR_DBG__32_32                          (MSCALER0_BASE + 0x0790)
++#define    MAIN_MSCA_ADDR_DBG__33_33                          (MSCALER0_BASE + 0x0794)
++#define    MAIN_MSCA_ADDR_DBG__34_34                          (MSCALER0_BASE + 0x0798)
++#define    MAIN_MSCA_ADDR_DBG__35_35                          (MSCALER0_BASE + 0x079c)
++#define    MAIN_MSCA_ADDR_DBG__36_36                          (MSCALER0_BASE + 0x07a0)
++#define    MAIN_MSCA_ADDR_DBG__37_37                          (MSCALER0_BASE + 0x07a4)
++#define    MAIN_MSCA_ADDR_DBG__38_38                          (MSCALER0_BASE + 0x07a8)
++#define    MAIN_MSCA_ADDR_DBG__39_39                          (MSCALER0_BASE + 0x07ac)
++#define    MAIN_MSCA_ADDR_DBG__40_40                          (MSCALER0_BASE + 0x07b0)
++#define    MAIN_MSCA_ADDR_DBG__41_41                          (MSCALER0_BASE + 0x07b4)
++#define    MAIN_MSCA_ADDR_DBG__42_42                          (MSCALER0_BASE + 0x07b8)
++#define    MAIN_MSCA_ADDR_DBG__43_43                          (MSCALER0_BASE + 0x07bc)
++#define    MAIN_MSCA_ADDR_DBG__44_44                          (MSCALER0_BASE + 0x07c0)
++#define    MAIN_MSCA_ADDR_DBG__45_45                          (MSCALER0_BASE + 0x07c4)
++#define    MAIN_MSCA_ADDR_DBG__46_46                          (MSCALER0_BASE + 0x07c8)
++#define    MAIN_MSCA_ADDR_DBG__47_47                          (MSCALER0_BASE + 0x07cc)
++#define    MAIN_MSCA_ADDR_DBG__48_48                          (MSCALER0_BASE + 0x07d0)
++#define    MAIN_MSCA_ADDR_DBG__49_49                          (MSCALER0_BASE + 0x07d4)
++#define    MAIN_MSCA_ADDR_DBG__50_50                          (MSCALER0_BASE + 0x07d8)
++#define    MAIN_MSCA_ADDR_DBG__51_51                          (MSCALER0_BASE + 0x07dc)
++#define    MAIN_MSCA_ADDR_DBG__52_52                          (MSCALER0_BASE + 0x07e0)
++#define    MAIN_MSCA_ADDR_DBG__53_53                          (MSCALER0_BASE + 0x07e4)
++#define    MAIN_MSCA_ADDR_DBG__54_54                          (MSCALER0_BASE + 0x07e8)
++#define    MAIN_MSCA_ADDR_DBG__55_55                          (MSCALER0_BASE + 0x07ec)
++#define    MAIN_MSCA_ADDR_DBG__56_56                          (MSCALER0_BASE + 0x07f0)
++#define    MAIN_MSCA_ADDR_DBG__57_57                          (MSCALER0_BASE + 0x07f4)
++#define    MAIN_MSCA_ADDR_DBG__58_58                          (MSCALER0_BASE + 0x07f8)
++#define    MAIN_MSCA_ADDR_DBG__59_59                          (MSCALER0_BASE + 0x07fc)
++#define    MAIN_MSCA_ADDR_DBG__60_60                          (MSCALER0_BASE + 0x0800)
++
++#define    SEC_MSCA_ADDR_CH_WORK_EN                           (MSCALER1_BASE + 0x0008)
++#define    SEC_MSCA_ADDR_FORCE                                (MSCALER1_BASE + 0x000c)
++#define    SEC_MSCA_ADDR_CTRL                                 (MSCALER1_BASE + 0x0010)
++#define    SEC_MSCA_ADDR_MASK_EN                              (MSCALER1_BASE + 0x0014)
++#define    SEC_MSCA_ADDR_OSD_EN                               (MSCALER1_BASE + 0x0018)
++#define    SEC_MSCA_ADDR_COEF_FIX_EN                          (MSCALER1_BASE + 0x0028)
++#define    SEC_MSCA_ADDR_MIRR_FLIP_RSMP_SAMP_DONE             (MSCALER1_BASE + 0x002c)
++#define    SEC_MSCA_ADDR_CLK_GATE_EN                          (MSCALER1_BASE + 0x0030)
++#define    SEC_MSCA_ADDR_CLK_GATE                             (MSCALER1_BASE + 0x0034)
++#define    SEC_MSCA_ADDR_OSD_COEF_R                           (MSCALER1_BASE + 0x0050)
++#define    SEC_MSCA_ADDR_OSD_COEF_G                           (MSCALER1_BASE + 0x0054)
++#define    SEC_MSCA_ADDR_OSD_COEF_B                           (MSCALER1_BASE + 0x0058)
++#define    SEC_MSCA_ADDR_OSD_COEF_OFT                         (MSCALER1_BASE + 0x005c)
++#define    SEC_MSCA_ADDR_OSD_MODE                             (MSCALER1_BASE + 0x0060)
++#define    SEC_MSCA_ADDR_OSD_ARGB_TYPE                        (MSCALER1_BASE + 0x0064)
++#define    SEC_MSCA_ADDR_CH0_PRIO                             (MSCALER1_BASE + 0x0070)
++#define    SEC_MSCA_ADDR_CH1_PRIO                             (MSCALER1_BASE + 0x0074)
++#define    SEC_MSCA_ADDR_CH2_PRIO                             (MSCALER1_BASE + 0x0078)
++#define    SEC_MSCA_ADDR_SRC_RSZ_POS                          (MSCALER1_BASE + 0x0080)
++#define    SEC_MSCA_ADDR_SRC_RSZ_SIZE                         (MSCALER1_BASE + 0x0084)
++#define    SEC_MSCA_ADDR_COEF_SEL                             (MSCALER1_BASE + 0x0088)
++#define    SEC_MSCA_ADDR_CH0_BEFORE_IRQ                       (MSCALER1_BASE + 0x0090)
++#define    SEC_MSCA_ADDR_CH1_BEFORE_IRQ                       (MSCALER1_BASE + 0x0094)
++#define    SEC_MSCA_ADDR_CH2_BEFORE_IRQ                       (MSCALER1_BASE + 0x0098)
++#define    SEC_MSCA_ADDR_CH0_FCROP_POS                        (MSCALER1_BASE + 0x00a0)
++#define    SEC_MSCA_ADDR_CH0_FCROP_IMG                        (MSCALER1_BASE + 0x00a4)
++#define    SEC_MSCA_ADDR_CH1_FCROP_POS                        (MSCALER1_BASE + 0x00a8)
++#define    SEC_MSCA_ADDR_CH1_FCROP_IMG                        (MSCALER1_BASE + 0x00ac)
++#define    SEC_MSCA_ADDR_CH2_FCROP_POS                        (MSCALER1_BASE + 0x00b0)
++#define    SEC_MSCA_ADDR_CH2_FCROP_IMG                        (MSCALER1_BASE + 0x00b4)
++#define    SEC_MSCA_ADDR_WORK_STAT                            (MSCALER1_BASE + 0x00e0)
++#define    SEC_MSCA_ADDR_SYS_PRO_CLK_EN                       (MSCALER1_BASE + 0x00f0)
++#define    SEC_MSCA_ADDR_CH0_CLK_NUM                          (MSCALER1_BASE + 0x00f4)
++#define    SEC_MSCA_ADDR_CH1_CLK_NUM                          (MSCALER1_BASE + 0x00f8)
++#define    SEC_MSCA_ADDR_CH2_CLK_NUM                          (MSCALER1_BASE + 0x00fc)
++#define    SEC_MSCA_ADDR_CH0_RSZ_SIZE                         (MSCALER1_BASE + 0x0100)
++#define    SEC_MSCA_ADDR_CH0_RSZ_STEP                         (MSCALER1_BASE + 0x0104)
++#define    SEC_MSCA_ADDR_CH0_CROP_POS                         (MSCALER1_BASE + 0x0128)
++#define    SEC_MSCA_ADDR_CH0_CROP_SIZE                        (MSCALER1_BASE + 0x012c)
++#define    SEC_MSCA_ADDR_CH0_FR_CTRL_LOOP                     (MSCALER1_BASE + 0x0130)
++#define    SEC_MSCA_ADDR_CH0_FR_CTRL_MASK                     (MSCALER1_BASE + 0x0134)
++#define    SEC_MSCA_ADDR_CH0_MS0_POS                          (MSCALER1_BASE + 0x0138)
++#define    SEC_MSCA_ADDR_CH0_MS0_SIZE                         (MSCALER1_BASE + 0x013c)
++#define    SEC_MSCA_ADDR_CH0_MS0_VALUE                        (MSCALER1_BASE + 0x0140)
++#define    SEC_MSCA_ADDR_CH0_MS1_POS                          (MSCALER1_BASE + 0x0144)
++#define    SEC_MSCA_ADDR_CH0_MS1_SIZE                         (MSCALER1_BASE + 0x0148)
++#define    SEC_MSCA_ADDR_CH0_MS1_VALUE                        (MSCALER1_BASE + 0x014c)
++#define    SEC_MSCA_ADDR_CH0_MS2_POS                          (MSCALER1_BASE + 0x0150)
++#define    SEC_MSCA_ADDR_CH0_MS2_SIZE                         (MSCALER1_BASE + 0x0154)
++#define    SEC_MSCA_ADDR_CH0_MS2_VALUE                        (MSCALER1_BASE + 0x0158)
++#define    SEC_MSCA_ADDR_CH0_MS3_POS                          (MSCALER1_BASE + 0x015c)
++#define    SEC_MSCA_ADDR_CH0_MS3_SIZE                         (MSCALER1_BASE + 0x0160)
++#define    SEC_MSCA_ADDR_CH0_MS3_VALUE                        (MSCALER1_BASE + 0x0164)
++#define    SEC_MSCA_ADDR_CH0_OUT_FMT                          (MSCALER1_BASE + 0x0168)
++#define    SEC_MSCA_ADDR_CH0_DMAOUT_Y_ADDR                    (MSCALER1_BASE + 0x016c)
++#define    SEC_MSCA_ADDR_CH0_Y_ADDR_FIFO_STA                  (MSCALER1_BASE + 0x0170)
++#define    SEC_MSCA_ADDR_CH0_DMAOUT_Y_LAST_ADDR               (MSCALER1_BASE + 0x0174)
++#define    SEC_MSCA_ADDR_CH0_Y_LAST_ADDR_FIFO_STA             (MSCALER1_BASE + 0x017c)
++#define    SEC_MSCA_ADDR_CH0_DMAOUT_Y_STRIDE                  (MSCALER1_BASE + 0x0180)
++#define    SEC_MSCA_ADDR_CH0_DMAOUT_UV_ADDR                   (MSCALER1_BASE + 0x0184)
++#define    SEC_MSCA_ADDR_CH0_UV_ADDR_FIFO_STA                 (MSCALER1_BASE + 0x0188)
++#define    SEC_MSCA_ADDR_CH0_DMAOUT_UV_LAST_ADDR              (MSCALER1_BASE + 0x018c)
++#define    SEC_MSCA_ADDR_CH0_UV_LAST_ADDR_FIFO_STA            (MSCALER1_BASE + 0x0194)
++#define    SEC_MSCA_ADDR_CH0_DMAOUT_UV_STRIDE                 (MSCALER1_BASE + 0x0198)
++#define    SEC_MSCA_ADDR_CH0_DMAOUT_Y_ADDR_CLR                (MSCALER1_BASE + 0x019c)
++#define    SEC_MSCA_ADDR_CH0_DMAOUT_UV_ADDR_CLR               (MSCALER1_BASE + 0x01a0)
++#define    SEC_MSCA_ADDR_CH0_DMAOUT_Y_LAST_ADDR_CLR           (MSCALER1_BASE + 0x01a4)
++#define    SEC_MSCA_ADDR_CH0_DMAOUT_UV_LAST_ADDR_CLR          (MSCALER1_BASE + 0x01a8)
++#define    SEC_MSCA_ADDR_CH0_DMAOUT_Y_ADDR_SEL                (MSCALER1_BASE + 0x01ac)
++#define    SEC_MSCA_ADDR_CH0_DMAOUT_UV_ADDR_SEL               (MSCALER1_BASE + 0x01b0)
++#define    SEC_MSCA_ADDR_CH0_COE_ZERO_VRSZ_H                  (MSCALER1_BASE + 0x01c0)
++#define    SEC_MSCA_ADDR_CH0_COE_ZERO_VRSZ_L                  (MSCALER1_BASE + 0x01c4)
++#define    SEC_MSCA_ADDR_CH0_COE_ZERO_HRSZ_H                  (MSCALER1_BASE + 0x01c8)
++#define    SEC_MSCA_ADDR_CH0_COE_ZERO_HRSZ_L                  (MSCALER1_BASE + 0x01cc)
++#define    SEC_MSCA_ADDR_CH0_COE_OFT                          (MSCALER1_BASE + 0x01d0)
++#define    SEC_MSCA_ADDR_CH0_ARF                              (MSCALER1_BASE + 0x01f0)
++#define    SEC_MSCA_ADDR_CH0_CLR                              (MSCALER1_BASE + 0x01f4)
++#define    SEC_MSCA_ADDR_CH1_RSZ_SIZE                         (MSCALER1_BASE + 0x0200)
++#define    SEC_MSCA_ADDR_CH1_RSZ_STEP                         (MSCALER1_BASE + 0x0204)
++#define    SEC_MSCA_ADDR_CH1_CROP_POS                         (MSCALER1_BASE + 0x0228)
++#define    SEC_MSCA_ADDR_CH1_CROP_SIZE                        (MSCALER1_BASE + 0x022c)
++#define    SEC_MSCA_ADDR_CH1_FR_CTRL_LOOP                     (MSCALER1_BASE + 0x0230)
++#define    SEC_MSCA_ADDR_CH1_FR_CTRL_MASK                     (MSCALER1_BASE + 0x0234)
++#define    SEC_MSCA_ADDR_CH1_MS0_POS                          (MSCALER1_BASE + 0x0238)
++#define    SEC_MSCA_ADDR_CH1_MS0_SIZE                         (MSCALER1_BASE + 0x023c)
++#define    SEC_MSCA_ADDR_CH1_MS0_VALUE                        (MSCALER1_BASE + 0x0240)
++#define    SEC_MSCA_ADDR_CH1_MS1_POS                          (MSCALER1_BASE + 0x0244)
++#define    SEC_MSCA_ADDR_CH1_MS1_SIZE                         (MSCALER1_BASE + 0x0248)
++#define    SEC_MSCA_ADDR_CH1_MS1_VALUE                        (MSCALER1_BASE + 0x024c)
++#define    SEC_MSCA_ADDR_CH1_MS2_POS                          (MSCALER1_BASE + 0x0250)
++#define    SEC_MSCA_ADDR_CH1_MS2_SIZE                         (MSCALER1_BASE + 0x0254)
++#define    SEC_MSCA_ADDR_CH1_MS2_VALUE                        (MSCALER1_BASE + 0x0258)
++#define    SEC_MSCA_ADDR_CH1_MS3_POS                          (MSCALER1_BASE + 0x025c)
++#define    SEC_MSCA_ADDR_CH1_MS3_SIZE                         (MSCALER1_BASE + 0x0260)
++#define    SEC_MSCA_ADDR_CH1_MS3_VALUE                        (MSCALER1_BASE + 0x0264)
++#define    SEC_MSCA_ADDR_CH1_OUT_FMT                          (MSCALER1_BASE + 0x0268)
++#define    SEC_MSCA_ADDR_CH1_DMAOUT_Y_ADDR                    (MSCALER1_BASE + 0x026c)
++#define    SEC_MSCA_ADDR_CH1_Y_ADDR_FIFO_STA                  (MSCALER1_BASE + 0x0270)
++#define    SEC_MSCA_ADDR_CH1_DMAOUT_Y_LAST_ADDR               (MSCALER1_BASE + 0x0274)
++#define    SEC_MSCA_ADDR_CH1_Y_LAST_ADDR_FIFO_STA             (MSCALER1_BASE + 0x027c)
++#define    SEC_MSCA_ADDR_CH1_DMAOUT_Y_STRIDE                  (MSCALER1_BASE + 0x0280)
++#define    SEC_MSCA_ADDR_CH1_DMAOUT_UV_ADDR                   (MSCALER1_BASE + 0x0284)
++#define    SEC_MSCA_ADDR_CH1_UV_ADDR_FIFO_STA                 (MSCALER1_BASE + 0x0288)
++#define    SEC_MSCA_ADDR_CH1_DMAOUT_UV_LAST_ADDR              (MSCALER1_BASE + 0x028c)
++#define    SEC_MSCA_ADDR_CH1_UV_LAST_ADDR_FIFO_STA            (MSCALER1_BASE + 0x0294)
++#define    SEC_MSCA_ADDR_CH1_DMAOUT_UV_STRIDE                 (MSCALER1_BASE + 0x0298)
++#define    SEC_MSCA_ADDR_CH1_DMAOUT_Y_ADDR_CLR                (MSCALER1_BASE + 0x029c)
++#define    SEC_MSCA_ADDR_CH1_DMAOUT_UV_ADDR_CLR               (MSCALER1_BASE + 0x02a0)
++#define    SEC_MSCA_ADDR_CH1_DMAOUT_Y_LAST_ADDR_CLR           (MSCALER1_BASE + 0x02a4)
++#define    SEC_MSCA_ADDR_CH1_DMAOUT_UV_LAST_ADDR_CLR          (MSCALER1_BASE + 0x02a8)
++#define    SEC_MSCA_ADDR_CH1_DMAOUT_Y_ADDR_SEL                (MSCALER1_BASE + 0x02ac)
++#define    SEC_MSCA_ADDR_CH1_DMAOUT_UV_ADDR_SEL               (MSCALER1_BASE + 0x02b0)
++#define    SEC_MSCA_ADDR_CH1_COE_ZERO_VRSZ_H                  (MSCALER1_BASE + 0x02c0)
++#define    SEC_MSCA_ADDR_CH1_COE_ZERO_VRSZ_L                  (MSCALER1_BASE + 0x02c4)
++#define    SEC_MSCA_ADDR_CH1_COE_ZERO_HRSZ_H                  (MSCALER1_BASE + 0x02c8)
++#define    SEC_MSCA_ADDR_CH1_COE_ZERO_HRSZ_L                  (MSCALER1_BASE + 0x02cc)
++#define    SEC_MSCA_ADDR_CH1_COE_OFT                          (MSCALER1_BASE + 0x02d0)
++#define    SEC_MSCA_ADDR_CH1_ARF                              (MSCALER1_BASE + 0x02f0)
++#define    SEC_MSCA_ADDR_CH1_CLR                              (MSCALER1_BASE + 0x02f4)
++#define    SEC_MSCA_ADDR_CH2_RSZ_SIZE                         (MSCALER1_BASE + 0x0300)
++#define    SEC_MSCA_ADDR_CH2_RSZ_STEP                         (MSCALER1_BASE + 0x0304)
++#define    SEC_MSCA_ADDR_CH2_CROP_POS                         (MSCALER1_BASE + 0x0328)
++#define    SEC_MSCA_ADDR_CH2_CROP_SIZE                        (MSCALER1_BASE + 0x032c)
++#define    SEC_MSCA_ADDR_CH2_FR_CTRL_LOOP                     (MSCALER1_BASE + 0x0330)
++#define    SEC_MSCA_ADDR_CH2_FR_CTRL_MASK                     (MSCALER1_BASE + 0x0334)
++#define    SEC_MSCA_ADDR_CH2_MS0_POS                          (MSCALER1_BASE + 0x0338)
++#define    SEC_MSCA_ADDR_CH2_MS0_SIZE                         (MSCALER1_BASE + 0x033c)
++#define    SEC_MSCA_ADDR_CH2_MS0_VALUE                        (MSCALER1_BASE + 0x0340)
++#define    SEC_MSCA_ADDR_CH2_MS1_POS                          (MSCALER1_BASE + 0x0344)
++#define    SEC_MSCA_ADDR_CH2_MS1_SIZE                         (MSCALER1_BASE + 0x0348)
++#define    SEC_MSCA_ADDR_CH2_MS1_VALUE                        (MSCALER1_BASE + 0x034c)
++#define    SEC_MSCA_ADDR_CH2_MS2_POS                          (MSCALER1_BASE + 0x0350)
++#define    SEC_MSCA_ADDR_CH2_MS2_SIZE                         (MSCALER1_BASE + 0x0354)
++#define    SEC_MSCA_ADDR_CH2_MS2_VALUE                        (MSCALER1_BASE + 0x0358)
++#define    SEC_MSCA_ADDR_CH2_MS3_POS                          (MSCALER1_BASE + 0x035c)
++#define    SEC_MSCA_ADDR_CH2_MS3_SIZE                         (MSCALER1_BASE + 0x0360)
++#define    SEC_MSCA_ADDR_CH2_MS3_VALUE                        (MSCALER1_BASE + 0x0364)
++#define    SEC_MSCA_ADDR_CH2_OUT_FMT                          (MSCALER1_BASE + 0x0368)
++#define    SEC_MSCA_ADDR_CH2_DMAOUT_Y_ADDR                    (MSCALER1_BASE + 0x036c)
++#define    SEC_MSCA_ADDR_CH2_Y_ADDR_FIFO_STA                  (MSCALER1_BASE + 0x0370)
++#define    SEC_MSCA_ADDR_CH2_DMAOUT_Y_LAST_ADDR               (MSCALER1_BASE + 0x0374)
++#define    SEC_MSCA_ADDR_CH2_Y_LAST_ADDR_FIFO_STA             (MSCALER1_BASE + 0x037c)
++#define    SEC_MSCA_ADDR_CH2_DMAOUT_Y_STRIDE                  (MSCALER1_BASE + 0x0380)
++#define    SEC_MSCA_ADDR_CH2_DMAOUT_UV_ADDR                   (MSCALER1_BASE + 0x0384)
++#define    SEC_MSCA_ADDR_CH2_UV_ADDR_FIFO_STA                 (MSCALER1_BASE + 0x0388)
++#define    SEC_MSCA_ADDR_CH2_DMAOUT_UV_LAST_ADDR              (MSCALER1_BASE + 0x038c)
++#define    SEC_MSCA_ADDR_CH2_UV_LAST_ADDR_FIFO_STA            (MSCALER1_BASE + 0x0394)
++#define    SEC_MSCA_ADDR_CH2_DMAOUT_UV_STRIDE                 (MSCALER1_BASE + 0x0398)
++#define    SEC_MSCA_ADDR_CH2_DMAOUT_Y_ADDR_CLR                (MSCALER1_BASE + 0x039c)
++#define    SEC_MSCA_ADDR_CH2_DMAOUT_UV_ADDR_CLR               (MSCALER1_BASE + 0x03a0)
++#define    SEC_MSCA_ADDR_CH2_DMAOUT_Y_LAST_ADDR_CLR           (MSCALER1_BASE + 0x03a4)
++#define    SEC_MSCA_ADDR_CH2_DMAOUT_UV_LAST_ADDR_CLR          (MSCALER1_BASE + 0x03a8)
++#define    SEC_MSCA_ADDR_CH2_DMAOUT_Y_ADDR_SEL                (MSCALER1_BASE + 0x03ac)
++#define    SEC_MSCA_ADDR_CH2_DMAOUT_UV_ADDR_SEL               (MSCALER1_BASE + 0x03b0)
++#define    SEC_MSCA_ADDR_CH2_COE_ZERO_VRSZ_H                  (MSCALER1_BASE + 0x03c0)
++#define    SEC_MSCA_ADDR_CH2_COE_ZERO_VRSZ_L                  (MSCALER1_BASE + 0x03c4)
++#define    SEC_MSCA_ADDR_CH2_COE_ZERO_HRSZ_H                  (MSCALER1_BASE + 0x03c8)
++#define    SEC_MSCA_ADDR_CH2_COE_ZERO_HRSZ_L                  (MSCALER1_BASE + 0x03cc)
++#define    SEC_MSCA_ADDR_CH2_COE_OFT                          (MSCALER1_BASE + 0x03d0)
++#define    SEC_MSCA_ADDR_CH2_ARF                              (MSCALER1_BASE + 0x03f0)
++#define    SEC_MSCA_ADDR_CH2_CLR                              (MSCALER1_BASE + 0x03f4)
++#define    SEC_MSCA_ADDR_CH0_LINE0_POS                        (MSCALER1_BASE + 0x0400)
++#define    SEC_MSCA_ADDR_CH0_LINE0_SIZE                       (MSCALER1_BASE + 0x0404)
++#define    SEC_MSCA_ADDR_CH0_LINE0_PAR0                       (MSCALER1_BASE + 0x0408)
++#define    SEC_MSCA_ADDR_CH0_LINE0_PAR1                       (MSCALER1_BASE + 0x040c)
++#define    SEC_MSCA_ADDR_CH0_LINE1_POS                        (MSCALER1_BASE + 0x0410)
++#define    SEC_MSCA_ADDR_CH0_LINE1_SIZE                       (MSCALER1_BASE + 0x0414)
++#define    SEC_MSCA_ADDR_CH0_LINE1_PAR0                       (MSCALER1_BASE + 0x0418)
++#define    SEC_MSCA_ADDR_CH0_LINE1_PAR1                       (MSCALER1_BASE + 0x041c)
++#define    SEC_MSCA_ADDR_CH0_LINE2_POS                        (MSCALER1_BASE + 0x0420)
++#define    SEC_MSCA_ADDR_CH0_LINE2_SIZE                       (MSCALER1_BASE + 0x0424)
++#define    SEC_MSCA_ADDR_CH0_LINE2_PAR0                       (MSCALER1_BASE + 0x0428)
++#define    SEC_MSCA_ADDR_CH0_LINE2_PAR1                       (MSCALER1_BASE + 0x042c)
++#define    SEC_MSCA_ADDR_CH0_LINE3_POS                        (MSCALER1_BASE + 0x0430)
++#define    SEC_MSCA_ADDR_CH0_LINE3_SIZE                       (MSCALER1_BASE + 0x0434)
++#define    SEC_MSCA_ADDR_CH0_LINE3_PAR0                       (MSCALER1_BASE + 0x0438)
++#define    SEC_MSCA_ADDR_CH0_LINE3_PAR1                       (MSCALER1_BASE + 0x043c)
++#define    SEC_MSCA_ADDR_CH0_LINE4_POS                        (MSCALER1_BASE + 0x0440)
++#define    SEC_MSCA_ADDR_CH0_LINE4_SIZE                       (MSCALER1_BASE + 0x0444)
++#define    SEC_MSCA_ADDR_CH0_LINE4_PAR0                       (MSCALER1_BASE + 0x0448)
++#define    SEC_MSCA_ADDR_CH0_LINE4_PAR1                       (MSCALER1_BASE + 0x044c)
++#define    SEC_MSCA_ADDR_CH0_LINE5_POS                        (MSCALER1_BASE + 0x0450)
++#define    SEC_MSCA_ADDR_CH0_LINE5_SIZE                       (MSCALER1_BASE + 0x0454)
++#define    SEC_MSCA_ADDR_CH0_LINE5_PAR0                       (MSCALER1_BASE + 0x0458)
++#define    SEC_MSCA_ADDR_CH0_LINE5_PAR1                       (MSCALER1_BASE + 0x045c)
++#define    SEC_MSCA_ADDR_CH0_LINE6_POS                        (MSCALER1_BASE + 0x0460)
++#define    SEC_MSCA_ADDR_CH0_LINE6_SIZE                       (MSCALER1_BASE + 0x0464)
++#define    SEC_MSCA_ADDR_CH0_LINE6_PAR0                       (MSCALER1_BASE + 0x0468)
++#define    SEC_MSCA_ADDR_CH0_LINE6_PAR1                       (MSCALER1_BASE + 0x046c)
++#define    SEC_MSCA_ADDR_CH0_LINE7_POS                        (MSCALER1_BASE + 0x0470)
++#define    SEC_MSCA_ADDR_CH0_LINE7_SIZE                       (MSCALER1_BASE + 0x0474)
++#define    SEC_MSCA_ADDR_CH0_LINE7_PAR0                       (MSCALER1_BASE + 0x0478)
++#define    SEC_MSCA_ADDR_CH0_LINE7_PAR1                       (MSCALER1_BASE + 0x047c)
++#define    SEC_MSCA_ADDR_CH0_LINE8_POS                        (MSCALER1_BASE + 0x0480)
++#define    SEC_MSCA_ADDR_CH0_LINE8_SIZE                       (MSCALER1_BASE + 0x0484)
++#define    SEC_MSCA_ADDR_CH0_LINE8_PAR0                       (MSCALER1_BASE + 0x0488)
++#define    SEC_MSCA_ADDR_CH0_LINE8_PAR1                       (MSCALER1_BASE + 0x048c)
++#define    SEC_MSCA_ADDR_CH0_LINE9_POS                        (MSCALER1_BASE + 0x0490)
++#define    SEC_MSCA_ADDR_CH0_LINE9_SIZE                       (MSCALER1_BASE + 0x0494)
++#define    SEC_MSCA_ADDR_CH0_LINE9_PAR0                       (MSCALER1_BASE + 0x0498)
++#define    SEC_MSCA_ADDR_CH0_LINE9_PAR1                       (MSCALER1_BASE + 0x049c)
++#define    SEC_MSCA_ADDR_CH0_LINE10_POS                       (MSCALER1_BASE + 0x04a0)
++#define    SEC_MSCA_ADDR_CH0_LINE10_SIZE                      (MSCALER1_BASE + 0x04a4)
++#define    SEC_MSCA_ADDR_CH0_LINE10_PAR0                      (MSCALER1_BASE + 0x04a8)
++#define    SEC_MSCA_ADDR_CH0_LINE10_PAR1                      (MSCALER1_BASE + 0x04ac)
++#define    SEC_MSCA_ADDR_CH0_LINE11_POS                       (MSCALER1_BASE + 0x04b0)
++#define    SEC_MSCA_ADDR_CH0_LINE11_SIZE                      (MSCALER1_BASE + 0x04b4)
++#define    SEC_MSCA_ADDR_CH0_LINE11_PAR0                      (MSCALER1_BASE + 0x04b8)
++#define    SEC_MSCA_ADDR_CH0_LINE11_PAR1                      (MSCALER1_BASE + 0x04bc)
++#define    SEC_MSCA_ADDR_CH0_LINE12_POS                       (MSCALER1_BASE + 0x04c0)
++#define    SEC_MSCA_ADDR_CH0_LINE12_SIZE                      (MSCALER1_BASE + 0x04c4)
++#define    SEC_MSCA_ADDR_CH0_LINE12_PAR0                      (MSCALER1_BASE + 0x04c8)
++#define    SEC_MSCA_ADDR_CH0_LINE12_PAR1                      (MSCALER1_BASE + 0x04cc)
++#define    SEC_MSCA_ADDR_CH0_LINE13_POS                       (MSCALER1_BASE + 0x04d0)
++#define    SEC_MSCA_ADDR_CH0_LINE13_SIZE                      (MSCALER1_BASE + 0x04d4)
++#define    SEC_MSCA_ADDR_CH0_LINE13_PAR0                      (MSCALER1_BASE + 0x04d8)
++#define    SEC_MSCA_ADDR_CH0_LINE13_PAR1                      (MSCALER1_BASE + 0x04dc)
++#define    SEC_MSCA_ADDR_CH0_LINE14_POS                       (MSCALER1_BASE + 0x04e0)
++#define    SEC_MSCA_ADDR_CH0_LINE14_SIZE                      (MSCALER1_BASE + 0x04e4)
++#define    SEC_MSCA_ADDR_CH0_LINE14_PAR0                      (MSCALER1_BASE + 0x04e8)
++#define    SEC_MSCA_ADDR_CH0_LINE14_PAR1                      (MSCALER1_BASE + 0x04ec)
++#define    SEC_MSCA_ADDR_CH0_LINE15_POS                       (MSCALER1_BASE + 0x04f0)
++#define    SEC_MSCA_ADDR_CH0_LINE15_SIZE                      (MSCALER1_BASE + 0x04f4)
++#define    SEC_MSCA_ADDR_CH0_LINE15_PAR0                      (MSCALER1_BASE + 0x04f8)
++#define    SEC_MSCA_ADDR_CH0_LINE15_PAR1                      (MSCALER1_BASE + 0x04fc)
++#define    SEC_MSCA_ADDR_CH1_LINE0_POS                        (MSCALER1_BASE + 0x0500)
++#define    SEC_MSCA_ADDR_CH1_LINE0_SIZE                       (MSCALER1_BASE + 0x0504)
++#define    SEC_MSCA_ADDR_CH1_LINE0_PAR0                       (MSCALER1_BASE + 0x0508)
++#define    SEC_MSCA_ADDR_CH1_LINE0_PAR1                       (MSCALER1_BASE + 0x050c)
++#define    SEC_MSCA_ADDR_CH1_LINE1_POS                        (MSCALER1_BASE + 0x0510)
++#define    SEC_MSCA_ADDR_CH1_LINE1_SIZE                       (MSCALER1_BASE + 0x0514)
++#define    SEC_MSCA_ADDR_CH1_LINE1_PAR0                       (MSCALER1_BASE + 0x0518)
++#define    SEC_MSCA_ADDR_CH1_LINE1_PAR1                       (MSCALER1_BASE + 0x051c)
++#define    SEC_MSCA_ADDR_CH1_LINE2_POS                        (MSCALER1_BASE + 0x0520)
++#define    SEC_MSCA_ADDR_CH1_LINE2_SIZE                       (MSCALER1_BASE + 0x0524)
++#define    SEC_MSCA_ADDR_CH1_LINE2_PAR0                       (MSCALER1_BASE + 0x0528)
++#define    SEC_MSCA_ADDR_CH1_LINE2_PAR1                       (MSCALER1_BASE + 0x052c)
++#define    SEC_MSCA_ADDR_CH1_LINE3_POS                        (MSCALER1_BASE + 0x0530)
++#define    SEC_MSCA_ADDR_CH1_LINE3_SIZE                       (MSCALER1_BASE + 0x0534)
++#define    SEC_MSCA_ADDR_CH1_LINE3_PAR0                       (MSCALER1_BASE + 0x0538)
++#define    SEC_MSCA_ADDR_CH1_LINE3_PAR1                       (MSCALER1_BASE + 0x053c)
++#define    SEC_MSCA_ADDR_CH1_LINE4_POS                        (MSCALER1_BASE + 0x0540)
++#define    SEC_MSCA_ADDR_CH1_LINE4_SIZE                       (MSCALER1_BASE + 0x0544)
++#define    SEC_MSCA_ADDR_CH1_LINE4_PAR0                       (MSCALER1_BASE + 0x0548)
++#define    SEC_MSCA_ADDR_CH1_LINE4_PAR1                       (MSCALER1_BASE + 0x054c)
++#define    SEC_MSCA_ADDR_CH1_LINE5_POS                        (MSCALER1_BASE + 0x0550)
++#define    SEC_MSCA_ADDR_CH1_LINE5_SIZE                       (MSCALER1_BASE + 0x0554)
++#define    SEC_MSCA_ADDR_CH1_LINE5_PAR0                       (MSCALER1_BASE + 0x0558)
++#define    SEC_MSCA_ADDR_CH1_LINE5_PAR1                       (MSCALER1_BASE + 0x055c)
++#define    SEC_MSCA_ADDR_CH1_LINE6_POS                        (MSCALER1_BASE + 0x0560)
++#define    SEC_MSCA_ADDR_CH1_LINE6_SIZE                       (MSCALER1_BASE + 0x0564)
++#define    SEC_MSCA_ADDR_CH1_LINE6_PAR0                       (MSCALER1_BASE + 0x0568)
++#define    SEC_MSCA_ADDR_CH1_LINE6_PAR1                       (MSCALER1_BASE + 0x056c)
++#define    SEC_MSCA_ADDR_CH1_LINE7_POS                        (MSCALER1_BASE + 0x0570)
++#define    SEC_MSCA_ADDR_CH1_LINE7_SIZE                       (MSCALER1_BASE + 0x0574)
++#define    SEC_MSCA_ADDR_CH1_LINE7_PAR0                       (MSCALER1_BASE + 0x0578)
++#define    SEC_MSCA_ADDR_CH1_LINE7_PAR1                       (MSCALER1_BASE + 0x057c)
++#define    SEC_MSCA_ADDR_CH1_LINE8_POS                        (MSCALER1_BASE + 0x0580)
++#define    SEC_MSCA_ADDR_CH1_LINE8_SIZE                       (MSCALER1_BASE + 0x0584)
++#define    SEC_MSCA_ADDR_CH1_LINE8_PAR0                       (MSCALER1_BASE + 0x0588)
++#define    SEC_MSCA_ADDR_CH1_LINE8_PAR1                       (MSCALER1_BASE + 0x058c)
++#define    SEC_MSCA_ADDR_CH1_LINE9_POS                        (MSCALER1_BASE + 0x0590)
++#define    SEC_MSCA_ADDR_CH1_LINE9_SIZE                       (MSCALER1_BASE + 0x0594)
++#define    SEC_MSCA_ADDR_CH1_LINE9_PAR0                       (MSCALER1_BASE + 0x0598)
++#define    SEC_MSCA_ADDR_CH1_LINE9_PAR1                       (MSCALER1_BASE + 0x059c)
++#define    SEC_MSCA_ADDR_CH1_LINE10_POS                       (MSCALER1_BASE + 0x05a0)
++#define    SEC_MSCA_ADDR_CH1_LINE10_SIZE                      (MSCALER1_BASE + 0x05a4)
++#define    SEC_MSCA_ADDR_CH1_LINE10_PAR0                      (MSCALER1_BASE + 0x05a8)
++#define    SEC_MSCA_ADDR_CH1_LINE10_PAR1                      (MSCALER1_BASE + 0x05ac)
++#define    SEC_MSCA_ADDR_CH1_LINE11_POS                       (MSCALER1_BASE + 0x05b0)
++#define    SEC_MSCA_ADDR_CH1_LINE11_SIZE                      (MSCALER1_BASE + 0x05b4)
++#define    SEC_MSCA_ADDR_CH1_LINE11_PAR0                      (MSCALER1_BASE + 0x05b8)
++#define    SEC_MSCA_ADDR_CH1_LINE11_PAR1                      (MSCALER1_BASE + 0x05bc)
++#define    SEC_MSCA_ADDR_CH1_LINE12_POS                       (MSCALER1_BASE + 0x05c0)
++#define    SEC_MSCA_ADDR_CH1_LINE12_SIZE                      (MSCALER1_BASE + 0x05c4)
++#define    SEC_MSCA_ADDR_CH1_LINE12_PAR0                      (MSCALER1_BASE + 0x05c8)
++#define    SEC_MSCA_ADDR_CH1_LINE12_PAR1                      (MSCALER1_BASE + 0x05cc)
++#define    SEC_MSCA_ADDR_CH1_LINE13_POS                       (MSCALER1_BASE + 0x05d0)
++#define    SEC_MSCA_ADDR_CH1_LINE13_SIZE                      (MSCALER1_BASE + 0x05d4)
++#define    SEC_MSCA_ADDR_CH1_LINE13_PAR0                      (MSCALER1_BASE + 0x05d8)
++#define    SEC_MSCA_ADDR_CH1_LINE13_PAR1                      (MSCALER1_BASE + 0x05dc)
++#define    SEC_MSCA_ADDR_CH1_LINE14_POS                       (MSCALER1_BASE + 0x05e0)
++#define    SEC_MSCA_ADDR_CH1_LINE14_SIZE                      (MSCALER1_BASE + 0x05e4)
++#define    SEC_MSCA_ADDR_CH1_LINE14_PAR0                      (MSCALER1_BASE + 0x05e8)
++#define    SEC_MSCA_ADDR_CH1_LINE14_PAR1                      (MSCALER1_BASE + 0x05ec)
++#define    SEC_MSCA_ADDR_CH1_LINE15_POS                       (MSCALER1_BASE + 0x05f0)
++#define    SEC_MSCA_ADDR_CH1_LINE15_SIZE                      (MSCALER1_BASE + 0x05f4)
++#define    SEC_MSCA_ADDR_CH1_LINE15_PAR0                      (MSCALER1_BASE + 0x05f8)
++#define    SEC_MSCA_ADDR_CH1_LINE15_PAR1                      (MSCALER1_BASE + 0x05fc)
++#define    SEC_MSCA_ADDR_CH0_OSD0_POS                         (MSCALER1_BASE + 0x0600)
++#define    SEC_MSCA_ADDR_CH0_OSD0_SIZE                        (MSCALER1_BASE + 0x0604)
++#define    SEC_MSCA_ADDR_CH0_OSD0_ADDR                        (MSCALER1_BASE + 0x0608)
++#define    SEC_MSCA_ADDR_CH0_OSD0_STRIDE                      (MSCALER1_BASE + 0x060c)
++#define    SEC_MSCA_ADDR_CH0_OSD1_POS                         (MSCALER1_BASE + 0x0610)
++#define    SEC_MSCA_ADDR_CH0_OSD1_SIZE                        (MSCALER1_BASE + 0x0614)
++#define    SEC_MSCA_ADDR_CH0_OSD1_ADDR                        (MSCALER1_BASE + 0x0618)
++#define    SEC_MSCA_ADDR_CH0_OSD1_STRIDE                      (MSCALER1_BASE + 0x061c)
++#define    SEC_MSCA_ADDR_CH0_OSD2_POS                         (MSCALER1_BASE + 0x0620)
++#define    SEC_MSCA_ADDR_CH0_OSD2_SIZE                        (MSCALER1_BASE + 0x0624)
++#define    SEC_MSCA_ADDR_CH0_OSD2_ADDR                        (MSCALER1_BASE + 0x0628)
++#define    SEC_MSCA_ADDR_CH0_OSD2_STRIDE                      (MSCALER1_BASE + 0x062c)
++#define    SEC_MSCA_ADDR_CH0_OSD3_POS                         (MSCALER1_BASE + 0x0630)
++#define    SEC_MSCA_ADDR_CH0_OSD3_SIZE                        (MSCALER1_BASE + 0x0634)
++#define    SEC_MSCA_ADDR_CH0_OSD3_ADDR                        (MSCALER1_BASE + 0x0638)
++#define    SEC_MSCA_ADDR_CH0_OSD3_STRIDE                      (MSCALER1_BASE + 0x063c)
++#define    SEC_MSCA_ADDR_CH0_OSD4_POS                         (MSCALER1_BASE + 0x0640)
++#define    SEC_MSCA_ADDR_CH0_OSD4_SIZE                        (MSCALER1_BASE + 0x0644)
++#define    SEC_MSCA_ADDR_CH0_OSD4_ADDR                        (MSCALER1_BASE + 0x0648)
++#define    SEC_MSCA_ADDR_CH0_OSD4_STRIDE                      (MSCALER1_BASE + 0x064c)
++#define    SEC_MSCA_ADDR_CH0_OSD5_POS                         (MSCALER1_BASE + 0x0650)
++#define    SEC_MSCA_ADDR_CH0_OSD5_SIZE                        (MSCALER1_BASE + 0x0654)
++#define    SEC_MSCA_ADDR_CH0_OSD5_ADDR                        (MSCALER1_BASE + 0x0658)
++#define    SEC_MSCA_ADDR_CH0_OSD5_STRIDE                      (MSCALER1_BASE + 0x065c)
++#define    SEC_MSCA_ADDR_CH0_OSD6_POS                         (MSCALER1_BASE + 0x0660)
++#define    SEC_MSCA_ADDR_CH0_OSD6_SIZE                        (MSCALER1_BASE + 0x0664)
++#define    SEC_MSCA_ADDR_CH0_OSD6_ADDR                        (MSCALER1_BASE + 0x0668)
++#define    SEC_MSCA_ADDR_CH0_OSD6_STRIDE                      (MSCALER1_BASE + 0x066c)
++#define    SEC_MSCA_ADDR_CH0_OSD7_POS                         (MSCALER1_BASE + 0x0670)
++#define    SEC_MSCA_ADDR_CH0_OSD7_SIZE                        (MSCALER1_BASE + 0x0674)
++#define    SEC_MSCA_ADDR_CH0_OSD7_ADDR                        (MSCALER1_BASE + 0x0678)
++#define    SEC_MSCA_ADDR_CH0_OSD7_STRIDE                      (MSCALER1_BASE + 0x067c)
++#define    SEC_MSCA_ADDR_CH1_OSD0_POS                         (MSCALER1_BASE + 0x0680)
++#define    SEC_MSCA_ADDR_CH1_OSD0_SIZE                        (MSCALER1_BASE + 0x0684)
++#define    SEC_MSCA_ADDR_CH1_OSD0_ADDR                        (MSCALER1_BASE + 0x0688)
++#define    SEC_MSCA_ADDR_CH1_OSD0_STRIDE                      (MSCALER1_BASE + 0x068c)
++#define    SEC_MSCA_ADDR_CH1_OSD1_POS                         (MSCALER1_BASE + 0x0690)
++#define    SEC_MSCA_ADDR_CH1_OSD1_SIZE                        (MSCALER1_BASE + 0x0694)
++#define    SEC_MSCA_ADDR_CH1_OSD1_ADDR                        (MSCALER1_BASE + 0x0698)
++#define    SEC_MSCA_ADDR_CH1_OSD1_STRIDE                      (MSCALER1_BASE + 0x069c)
++#define    SEC_MSCA_ADDR_CH1_OSD2_POS                         (MSCALER1_BASE + 0x06a0)
++#define    SEC_MSCA_ADDR_CH1_OSD2_SIZE                        (MSCALER1_BASE + 0x06a4)
++#define    SEC_MSCA_ADDR_CH1_OSD2_ADDR                        (MSCALER1_BASE + 0x06a8)
++#define    SEC_MSCA_ADDR_CH1_OSD2_STRIDE                      (MSCALER1_BASE + 0x06ac)
++#define    SEC_MSCA_ADDR_CH1_OSD3_POS                         (MSCALER1_BASE + 0x06b0)
++#define    SEC_MSCA_ADDR_CH1_OSD3_SIZE                        (MSCALER1_BASE + 0x06b4)
++#define    SEC_MSCA_ADDR_CH1_OSD3_ADDR                        (MSCALER1_BASE + 0x06b8)
++#define    SEC_MSCA_ADDR_CH1_OSD3_STRIDE                      (MSCALER1_BASE + 0x06bc)
++#define    SEC_MSCA_ADDR_CH1_OSD4_POS                         (MSCALER1_BASE + 0x06c0)
++#define    SEC_MSCA_ADDR_CH1_OSD4_SIZE                        (MSCALER1_BASE + 0x06c4)
++#define    SEC_MSCA_ADDR_CH1_OSD4_ADDR                        (MSCALER1_BASE + 0x06c8)
++#define    SEC_MSCA_ADDR_CH1_OSD4_STRIDE                      (MSCALER1_BASE + 0x06cc)
++#define    SEC_MSCA_ADDR_CH1_OSD5_POS                         (MSCALER1_BASE + 0x06d0)
++#define    SEC_MSCA_ADDR_CH1_OSD5_SIZE                        (MSCALER1_BASE + 0x06d4)
++#define    SEC_MSCA_ADDR_CH1_OSD5_ADDR                        (MSCALER1_BASE + 0x06d8)
++#define    SEC_MSCA_ADDR_CH1_OSD5_STRIDE                      (MSCALER1_BASE + 0x06dc)
++#define    SEC_MSCA_ADDR_CH1_OSD6_POS                         (MSCALER1_BASE + 0x06e0)
++#define    SEC_MSCA_ADDR_CH1_OSD6_SIZE                        (MSCALER1_BASE + 0x06e4)
++#define    SEC_MSCA_ADDR_CH1_OSD6_ADDR                        (MSCALER1_BASE + 0x06e8)
++#define    SEC_MSCA_ADDR_CH1_OSD6_STRIDE                      (MSCALER1_BASE + 0x06ec)
++#define    SEC_MSCA_ADDR_CH1_OSD7_POS                         (MSCALER1_BASE + 0x06f0)
++#define    SEC_MSCA_ADDR_CH1_OSD7_SIZE                        (MSCALER1_BASE + 0x06f4)
++#define    SEC_MSCA_ADDR_CH1_OSD7_ADDR                        (MSCALER1_BASE + 0x06f8)
++#define    SEC_MSCA_ADDR_CH1_OSD7_STRIDE                      (MSCALER1_BASE + 0x06fc)
++#define    SEC_MSCA_ADDR_BACK_DOOR                            (MSCALER1_BASE + 0x0700)
++#define    SEC_MSCA_ADDR_DBG__00_00                           (MSCALER1_BASE + 0x0710)
++#define    SEC_MSCA_ADDR_DBG__01_01                           (MSCALER1_BASE + 0x0714)
++#define    SEC_MSCA_ADDR_DBG__02_02                           (MSCALER1_BASE + 0x0718)
++#define    SEC_MSCA_ADDR_DBG__03_03                           (MSCALER1_BASE + 0x071c)
++#define    SEC_MSCA_ADDR_DBG__04_04                           (MSCALER1_BASE + 0x0720)
++#define    SEC_MSCA_ADDR_DBG__05_05                           (MSCALER1_BASE + 0x0724)
++#define    SEC_MSCA_ADDR_DBG__06_06                           (MSCALER1_BASE + 0x0728)
++#define    SEC_MSCA_ADDR_DBG__07_07                           (MSCALER1_BASE + 0x072c)
++#define    SEC_MSCA_ADDR_DBG__08_08                           (MSCALER1_BASE + 0x0730)
++#define    SEC_MSCA_ADDR_DBG__09_09                           (MSCALER1_BASE + 0x0734)
++#define    SEC_MSCA_ADDR_DBG__10_10                           (MSCALER1_BASE + 0x0738)
++#define    SEC_MSCA_ADDR_DBG__11_11                           (MSCALER1_BASE + 0x073c)
++#define    SEC_MSCA_ADDR_DBG__12_12                           (MSCALER1_BASE + 0x0740)
++#define    SEC_MSCA_ADDR_DBG__13_13                           (MSCALER1_BASE + 0x0744)
++#define    SEC_MSCA_ADDR_DBG__14_14                           (MSCALER1_BASE + 0x0748)
++#define    SEC_MSCA_ADDR_DBG__15_15                           (MSCALER1_BASE + 0x074c)
++#define    SEC_MSCA_ADDR_DBG__16_16                           (MSCALER1_BASE + 0x0750)
++#define    SEC_MSCA_ADDR_DBG__17_17                           (MSCALER1_BASE + 0x0754)
++#define    SEC_MSCA_ADDR_DBG__18_18                           (MSCALER1_BASE + 0x0758)
++#define    SEC_MSCA_ADDR_DBG__19_19                           (MSCALER1_BASE + 0x075c)
++#define    SEC_MSCA_ADDR_DBG__20_20                           (MSCALER1_BASE + 0x0760)
++#define    SEC_MSCA_ADDR_DBG__21_21                           (MSCALER1_BASE + 0x0764)
++#define    SEC_MSCA_ADDR_DBG__22_22                           (MSCALER1_BASE + 0x0768)
++#define    SEC_MSCA_ADDR_DBG__23_23                           (MSCALER1_BASE + 0x076c)
++#define    SEC_MSCA_ADDR_DBG__24_24                           (MSCALER1_BASE + 0x0770)
++#define    SEC_MSCA_ADDR_DBG__25_25                           (MSCALER1_BASE + 0x0774)
++#define    SEC_MSCA_ADDR_DBG__26_26                           (MSCALER1_BASE + 0x0778)
++#define    SEC_MSCA_ADDR_DBG__27_27                           (MSCALER1_BASE + 0x077c)
++#define    SEC_MSCA_ADDR_DBG__28_28                           (MSCALER1_BASE + 0x0780)
++#define    SEC_MSCA_ADDR_DBG__29_29                           (MSCALER1_BASE + 0x0784)
++#define    SEC_MSCA_ADDR_DBG__30_30                           (MSCALER1_BASE + 0x0788)
++#define    SEC_MSCA_ADDR_DBG__31_31                           (MSCALER1_BASE + 0x078c)
++#define    SEC_MSCA_ADDR_DBG__32_32                           (MSCALER1_BASE + 0x0790)
++#define    SEC_MSCA_ADDR_DBG__33_33                           (MSCALER1_BASE + 0x0794)
++#define    SEC_MSCA_ADDR_DBG__34_34                           (MSCALER1_BASE + 0x0798)
++#define    SEC_MSCA_ADDR_DBG__35_35                           (MSCALER1_BASE + 0x079c)
++#define    SEC_MSCA_ADDR_DBG__36_36                           (MSCALER1_BASE + 0x07a0)
++#define    SEC_MSCA_ADDR_DBG__37_37                           (MSCALER1_BASE + 0x07a4)
++#define    SEC_MSCA_ADDR_DBG__38_38                           (MSCALER1_BASE + 0x07a8)
++#define    SEC_MSCA_ADDR_DBG__39_39                           (MSCALER1_BASE + 0x07ac)
++#define    SEC_MSCA_ADDR_DBG__40_40                           (MSCALER1_BASE + 0x07b0)
++#define    SEC_MSCA_ADDR_DBG__41_41                           (MSCALER1_BASE + 0x07b4)
++#define    SEC_MSCA_ADDR_DBG__42_42                           (MSCALER1_BASE + 0x07b8)
++#define    SEC_MSCA_ADDR_DBG__43_43                           (MSCALER1_BASE + 0x07bc)
++#define    SEC_MSCA_ADDR_DBG__44_44                           (MSCALER1_BASE + 0x07c0)
++#define    SEC_MSCA_ADDR_DBG__45_45                           (MSCALER1_BASE + 0x07c4)
++#define    SEC_MSCA_ADDR_DBG__46_46                           (MSCALER1_BASE + 0x07c8)
++#define    SEC_MSCA_ADDR_DBG__47_47                           (MSCALER1_BASE + 0x07cc)
++#define    SEC_MSCA_ADDR_DBG__48_48                           (MSCALER1_BASE + 0x07d0)
++#define    SEC_MSCA_ADDR_DBG__49_49                           (MSCALER1_BASE + 0x07d4)
++#define    SEC_MSCA_ADDR_DBG__50_50                           (MSCALER1_BASE + 0x07d8)
++#define    SEC_MSCA_ADDR_DBG__51_51                           (MSCALER1_BASE + 0x07dc)
++#define    SEC_MSCA_ADDR_DBG__52_52                           (MSCALER1_BASE + 0x07e0)
++#define    SEC_MSCA_ADDR_DBG__53_53                           (MSCALER1_BASE + 0x07e4)
++#define    SEC_MSCA_ADDR_DBG__54_54                           (MSCALER1_BASE + 0x07e8)
++#define    SEC_MSCA_ADDR_DBG__55_55                           (MSCALER1_BASE + 0x07ec)
++#define    SEC_MSCA_ADDR_DBG__56_56                           (MSCALER1_BASE + 0x07f0)
++#define    SEC_MSCA_ADDR_DBG__57_57                           (MSCALER1_BASE + 0x07f4)
++#define    SEC_MSCA_ADDR_DBG__58_58                           (MSCALER1_BASE + 0x07f8)
++#define    SEC_MSCA_ADDR_DBG__59_59                           (MSCALER1_BASE + 0x07fc)
++#define    SEC_MSCA_ADDR_DBG__60_60                           (MSCALER1_BASE + 0x0800)
++
++#define    MSCA_ADDR_CH_WORK_EN                               (MSCALER0_BASE + 0x0008)
++#define    MSCA_ADDR_FORCE                                    (MSCALER0_BASE + 0x000C)
++#define    MSCA_ADDR_CTRL                                     (MSCALER0_BASE + 0x0010)
++#define    MSCA_ADDR_MASK_EN                                  (MSCALER0_BASE + 0x0014)
++#define    MSCA_ADDR_OSD_EN                                   (MSCALER0_BASE + 0x0018)
++#define    MSCA_ADDR_MIRR_FLIP_RSMP_SAMP_DONE                 (MSCALER0_BASE + 0x002c)
++#define    MSCA_ADDR_OSD_MODE                                 (MSCALER0_BASE + 0x0060)
++#define    MSCA_ADDR_OSD_ARGB_TYPE                            (MSCALER0_BASE + 0x0064)
++#define    MSCA_ADDR_SRC_RSZ_POS                              (MSCALER0_BASE + 0x0080)
++#define    MSCA_ADDR_SRC_RSZ_SIZE                             (MSCALER0_BASE + 0x0084)
++
++#define    MSCA_ADDR_CHx_FCROP_POS(n)                         (MSCALER0_BASE + 0x00a0 + (n * 0x008))
++#define    MSCA_ADDR_CHx_FCROP_IMG(n)                         (MSCALER0_BASE + 0x00a4 + (n * 0x008))
++#define    MSCA_ADDR_CHx_RSZ_SIZE(n)                          (MSCALER0_BASE + 0x0100 + (n * 0x100))
++#define    MSCA_ADDR_CHx_RSZ_STEP(n)                          (MSCALER0_BASE + 0x0104 + (n * 0x100))
++#define    MSCA_ADDR_CHx_CROP_POS(n)                          (MSCALER0_BASE + 0x0128 + (n * 0x100))
++#define    MSCA_ADDR_CHx_CROP_SIZE(n)                         (MSCALER0_BASE + 0x012c + (n * 0x100))
++#define    MSCA_ADDR_CHx_FR_CTRL_LOOP(n)                      (MSCALER0_BASE + 0x0130 + (n * 0x100))
++#define    MSCA_ADDR_CHx_FR_CTRL_MASK(n)                      (MSCALER0_BASE + 0x0134 + (n * 0x100))
++#define    MSCA_ADDR_CHx_OUT_FMT(n)                           (MSCALER0_BASE + 0x0168 + (n * 0x100))
++#define    MSCA_ADDR_CHx_DMAOUT_Y_ADDR(n)                     (MSCALER0_BASE + 0x016c + (n * 0x100))
++#define    MSCA_ADDR_CHx_Y_ADDR_FIFO_STA(n)                   (MSCALER0_BASE + 0x0170 + (n * 0x100))
++#define    MSCA_ADDR_CHx_DMAOUT_Y_LAST_ADDR(n)                (MSCALER0_BASE + 0x0174 + (n * 0x100))
++#define    MSCA_ADDR_CHx_Y_LAST_ADDR_FIFO_STA(n)              (MSCALER0_BASE + 0x017c + (n * 0x100))
++#define    MSCA_ADDR_CHx_DMAOUT_Y_STRIDE(n)                   (MSCALER0_BASE + 0x0180 + (n * 0x100))
++#define    MSCA_ADDR_CHx_DMAOUT_UV_ADDR(n)                    (MSCALER0_BASE + 0x0184 + (n * 0x100))
++#define    MSCA_ADDR_CHx_UV_ADDR_FIFO_STA(n)                  (MSCALER0_BASE + 0x0188 + (n * 0x100))
++#define    MSCA_ADDR_CHx_DMAOUT_UV_LAST_ADDR(n)               (MSCALER0_BASE + 0x018c + (n * 0x100))
++#define    MSCA_ADDR_CHx_UV_LAST_ADDR_FIFO_STA(n)             (MSCALER0_BASE + 0x0194 + (n * 0x100))
++#define    MSCA_ADDR_CHx_DMAOUT_UV_STRIDE(n)                  (MSCALER0_BASE + 0x0198 + (n * 0x100))
++#define    MSCA_ADDR_CHx_DMAOUT_Y_ADDR_CLR(n)                 (MSCALER0_BASE + 0x019c + (n * 0x100))
++#define    MSCA_ADDR_CHx_DMAOUT_UV_ADDR_CLR(n)                (MSCALER0_BASE + 0x01a0 + (n * 0x100))
++#define    MSCA_ADDR_CHx_DMAOUT_Y_LAST_ADDR_CLR(n)            (MSCALER0_BASE + 0x01a4 + (n * 0x100))
++#define    MSCA_ADDR_CHx_DMAOUT_UV_LAST_ADDR_CLR(n)           (MSCALER0_BASE + 0x01a8 + (n * 0x100))
++#define    MSCA_ADDR_CHx_DMAOUT_Y_ADDR_SEL(n)                 (MSCALER0_BASE + 0x01ac + (n * 0x100))
++#define    MSCA_ADDR_CHx_DMAOUT_UV_ADDR_SEL(n)                (MSCALER0_BASE + 0x01b0 + (n * 0x100))
++#define    MSCA_ADDR_CHx_COE_ZERO_VRSZ_H(n)                   (MSCALER0_BASE + 0x01c0 + (n * 0x100))
++#define    MSCA_ADDR_CHx_COE_ZERO_VRSZ_L(n)                   (MSCALER0_BASE + 0x01c4 + (n * 0x100))
++#define    MSCA_ADDR_CHx_COE_ZERO_HRSZ_H(n)                   (MSCALER0_BASE + 0x01c8 + (n * 0x100))
++#define    MSCA_ADDR_CHx_COE_ZERO_HRSZ_L(n)                   (MSCALER0_BASE + 0x01cc + (n * 0x100))
++#define    MSCA_ADDR_CHx_COE_OFT(n)                           (MSCALER0_BASE + 0x01d0 + (n * 0x100))
++#define    MSCA_ADDR_CHx_ARF(n)                               (MSCALER0_BASE + 0x01f0 + (n * 0x100))
++#define    MSCA_ADDR_CHx_CLR(n)                               (MSCALER0_BASE + 0x01f4 + (n * 0x100))
++
++#define    MSCA_ADDR_CHx_MSx_POS(n,k)                         (MSCALER0_BASE + 0x0138 + (n * 0x100) + (k * 0x0c))
++#define    MSCA_ADDR_CHx_MSx_SIZE(n,k)                        (MSCALER0_BASE + 0x013c + (n * 0x100) + (k * 0x0c))
++#define    MSCA_ADDR_CHx_MSx_VALUE(n,k)                       (MSCALER0_BASE + 0x0140 + (n * 0x100) + (k * 0x0c))
++
++#define    MSCA_ADDR_CHx_LINEx_POS(n,k)                       (MSCALER0_BASE + 0x0400 + (n * 0x100) + (k * 0x10))
++#define    MSCA_ADDR_CHx_LINEx_SIZE(n,k)                      (MSCALER0_BASE + 0x0404 + (n * 0x100) + (k * 0x10))
++#define    MSCA_ADDR_CHx_LINEx_PAR0(n,k)                      (MSCALER0_BASE + 0x0408 + (n * 0x100) + (k * 0x10))
++#define    MSCA_ADDR_CHx_LINEx_PAR1(n,k)                      (MSCALER0_BASE + 0x040c + (n * 0x100) + (k * 0x10))
++
++#define    MSCA_ADDR_CHx_OSDx_POS(n,k)                        (MSCALER0_BASE + 0x0600 + (n * 0x100) + (k * 0x10))
++#define    MSCA_ADDR_CHx_OSDx_SIZE(n,k)                       (MSCALER0_BASE + 0x0604 + (n * 0x100) + (k * 0x10))
++#define    MSCA_ADDR_CHx_OSDx_ADDR(n,k)                       (MSCALER0_BASE + 0x0608 + (n * 0x100) + (k * 0x10))
++#define    MSCA_ADDR_CHx_OSDx_STRIDE(n,k)                     (MSCALER0_BASE + 0x060c + (n * 0x100) + (k * 0x10))
++//============================================================
++// RESP ADDRESS
++//============================================================
++#define    RESP_ADDR_INT_CNTRL                                (RESP_BASE + 0x0000)
++
++#define    CH0_FRM_DONE_INT                                   (1 << 0)
++#define    CH1_FRM_DONE_INT                                   (1 << 1)
++#define    CH2_FRM_DONE_INT                                   (1 << 2)
++#define    AWB_STATIC_INT                                     (1 << 3)
++#define    AE_STATIC_INT                                      (1 << 4)
++#define    AE_HIST_INT                                        (1 << 5)
++#define    AF_STATIC_INT                                      (1 << 6)
++#define    GSM_STATIC_INT                                     (1 << 7)
++#define    LCE_STATIC_INT                                     (1 << 8)
++#define    ADR_STATIC_INT                                     (1 << 9)
++#define    DEFOG_STATIC_INT                                   (1 << 10)
++#define    WDR_STATIC_INT                                     (1 << 11)
++#define    STOP_FINISH_INT                                    (1 << 12)
++#define    CH0_FRM_DONE_BF_INT                                (1 << 13)
++#define    CH1_FRM_DONE_BF_INT                                (1 << 14)
++#define    CH2_FRM_DONE_BF_INT                                (1 << 15)
++#define    SDNS_STATIC_INT                                    (1 << 16)
++#define    RESP_ADDR_INT_COMMON_0_EN                          (RESP_BASE + 0x0020)
++#define    RESP_ADDR_INT_COMMON_0_CLR                         (RESP_BASE + 0x0024)
++#define    RESP_ADDR_INT_COMMON_0_INFO                        (RESP_BASE + 0x0028)
++#define    RESP_ADDR_INT_COMMON_1_EN                          (RESP_BASE + 0x0030)
++#define    RESP_ADDR_INT_COMMON_1_CLR                         (RESP_BASE + 0x0034)
++#define    RESP_ADDR_INT_COMMON_1_INFO                        (RESP_BASE + 0x0038)
++
++#define    BROKEN_FRAME_INT						      (1 << 4)
++#define    IP_OF_ERR_INT						      (1 << 5)
++#define    RESP_ADDR_INT_UNUSUAL_0_EN                         (RESP_BASE + 0x0060)
++#define    RESP_ADDR_INT_UNUSUAL_0_CLR                        (RESP_BASE + 0x0064)
++#define    RESP_ADDR_INT_UNUSUAL_0_INFO                       (RESP_BASE + 0x0068)
++#define    RESP_ADDR_INT_UNUSUAL_1_EN                         (RESP_BASE + 0x0070)
++#define    RESP_ADDR_INT_UNUSUAL_1_CLR                        (RESP_BASE + 0x0074)
++#define    RESP_ADDR_INT_UNUSUAL_1_INFO                       (RESP_BASE + 0x0078)
++#define    RESP_ADDR_INT_BACKUP_0_EN                          (RESP_BASE + 0x00A0)
++#define    RESP_ADDR_INT_BACKUP_0_CLR                         (RESP_BASE + 0x00A4)
++#define    RESP_ADDR_INT_BACKUP_0_INFO                        (RESP_BASE + 0x00A8)
++#define    RESP_ADDR_INT_BACKUP_1_EN                          (RESP_BASE + 0x00B0)
++#define    RESP_ADDR_INT_BACKUP_1_CLR                         (RESP_BASE + 0x00B4)
++#define    RESP_ADDR_INT_BACKUP_1_INFO                        (RESP_BASE + 0x00B8)
++#define    RESP_ADDR_BP_INFO                                  (RESP_BASE + 0x0100)
++#define    RESP_ADDR_POSITIO_0_INFO                           (RESP_BASE + 0x0200)
++#define    RESP_ADDR_POSITIO_1_INFO                           (RESP_BASE + 0x0204)
++#define    RESP_ADDR_POSITIO_2_INFO                           (RESP_BASE + 0x0208)
++#define    RESP_ADDR_POSITIO_3_INFO                           (RESP_BASE + 0x020C)
++#define    RESP_ADDR_POSITIO_4_INFO                           (RESP_BASE + 0x0210)
++#define    RESP_ADDR_POSITIO_5_INFO                           (RESP_BASE + 0x0214)
++#define    RESP_ADDR_POSITIO_6_INFO                           (RESP_BASE + 0x0218)
++#define    RESP_ADDR_POSITIO_7_INFO                           (RESP_BASE + 0x021C)
++#define    RESP_ADDR_POSITIO_8_INFO                           (RESP_BASE + 0x0220)
++#define    RESP_ADDR_POSITIO_9_INFO                           (RESP_BASE + 0x0224)
++#define    RESP_ADDR_POSITIO_10_INFO                          (RESP_BASE + 0x0228)
++#define    RESP_ADDR_POSITIO_11_INFO                          (RESP_BASE + 0x022C)
++#define    RESP_ADDR_POSITIO_12_INFO                          (RESP_BASE + 0x0230)
++#define    RESP_ADDR_POSITIO_13_INFO                          (RESP_BASE + 0x0234)
++#define    RESP_ADDR_POSITIO_14_INFO                          (RESP_BASE + 0x0238)
++#define    RESP_ADDR_POSITIO_15_INFO                          (RESP_BASE + 0x023C)
++#define    RESP_ADDR_POSITIO_16_INFO                          (RESP_BASE + 0x0240)
++#define    RESP_ADDR_POSITIO_17_INFO                          (RESP_BASE + 0x0244)
++#define    RESP_ADDR_POSITIO_18_INFO                          (RESP_BASE + 0x0248)
++#define    RESP_ADDR_POSITIO_19_INFO                          (RESP_BASE + 0x024C)
++#define    RESP_ADDR_POSITIO_20_INFO                          (RESP_BASE + 0x0250)
++#define    RESP_ADDR_POSITIO_21_INFO                          (RESP_BASE + 0x0254)
++#define    RESP_ADDR_POSITIO_22_INFO                          (RESP_BASE + 0x0258)
++#define    RESP_ADDR_POSITIO_23_INFO                          (RESP_BASE + 0x025C)
++#define    RESP_ADDR_POSITIO_24_INFO                          (RESP_BASE + 0x0260)
++#define    RESP_ADDR_POSITIO_25_INFO                          (RESP_BASE + 0x0264)
++#define    RESP_ADDR_POSITIO_26_INFO                          (RESP_BASE + 0x0268)
++#define    RESP_ADDR_POSITIO_27_INFO                          (RESP_BASE + 0x026C)
++#define    RESP_ADDR_POSITIO_28_INFO                          (RESP_BASE + 0x0270)
++#define    RESP_ADDR_POSITIO_29_INFO                          (RESP_BASE + 0x0274)
++#define    RESP_ADDR_POSITIO_30_INFO                          (RESP_BASE + 0x0278)
++#define    RESP_ADDR_POSITIO_31_INFO                          (RESP_BASE + 0x027C)
++#define    RESP_ADDR_FRM_INTVAL_CNTRL                         (RESP_BASE + 0x0300)
++#define    RESP_ADDR_FRM_INTVAL_ORG                           (RESP_BASE + 0x0304)
++#define    RESP_ADDR_FRM_INTVAL_LCK                           (RESP_BASE + 0x0308)
++
++//============================================================
++// TSTP ADDRESS
++//============================================================
++#define TSTP_ADDR_RAW_TOTAL(n)                          (TSTP_BASE(n) + 0x0000)
++#define TSTP_ADDR_RAW_SEL(n)                          (TSTP_BASE(n) + 0x0004)
++#define TSTP_ADDR_RAW_IRVAL0(n)                          (TSTP_BASE(n) + 0x0008)
++#define TSTP_ADDR_RAW_IRVAL1(n)                          (TSTP_BASE(n) + 0x000c)
++#define TSTP_ADDR_RGB_TOTAL(n)                          (TSTP_BASE(n) + 0x0010)
++#define TSTP_ADDR_RGB_SEL(n)                          (TSTP_BASE(n) + 0x0014)
++#define TSTP_ADDR_YUV_TOTAL(n)                          (TSTP_BASE(n) + 0x0020)
++#define TSTP_ADDR_YUV_SEL(n)                          (TSTP_BASE(n) + 0x0024)
++#define TSTP_ADDR_WDR_SEL(n)                          (TSTP_BASE(n) + 0x0028)
++#define TSTP_ADDR_DRAW_EN(n)                          (TSTP_BASE(n) + 0x0030)
++#define TSTP_ADDR_MARK0_PAR(n)                          (TSTP_BASE(n) + 0x0040)
++#define TSTP_ADDR_MARK1_PAR0(n)                          (TSTP_BASE(n) + 0x0050)
++#define TSTP_ADDR_MARK1_PAR1(n)                          (TSTP_BASE(n) + 0x0054)
++#define TSTP_ADDR_MARK1_PAR2(n)                          (TSTP_BASE(n) + 0x0058)
++#define TSTP_ADDR_MARK1_PAR3(n)                          (TSTP_BASE(n) + 0x005c)
++#define TSTP_ADDR_MARK1_PAR4(n)                          (TSTP_BASE(n) + 0x0060)
++#define TSTP_ADDR_MARK1_PAR5(n)                          (TSTP_BASE(n) + 0x0064)
++#define TSTP_ADDR_MARK1_PAR6(n)                          (TSTP_BASE(n) + 0x0068)
++#define TSTP_ADDR_MARK1_PAR7(n)                          (TSTP_BASE(n) + 0x006c)
++#define TSTP_ADDR_MARK1_PAR8(n)                          (TSTP_BASE(n) + 0x0070)
++#define TSTP_ADDR_MARK1_PAR9(n)                          (TSTP_BASE(n) + 0x0074)
++#define TSTP_ADDR_MARK1_PAR10(n)                          (TSTP_BASE(n) + 0x0078)
++#define TSTP_ADDR_MARK1_PAR11(n)                          (TSTP_BASE(n) + 0x007c)
++#define TSTP_ADDR_MARK1_PAR12(n)                          (TSTP_BASE(n) + 0x0080)
++#define TSTP_ADDR_MARK1_PAR13(n)                          (TSTP_BASE(n) + 0x0084)
++#define TSTP_ADDR_MARK1_PAR14(n)                          (TSTP_BASE(n) + 0x0088)
++#define TSTP_ADDR_MARK1_PAR15(n)                          (TSTP_BASE(n) + 0x008c)
++#define TSTP_ADDR_MARK1_PAR16(n)                          (TSTP_BASE(n) + 0x0090)
++#define TSTP_ADDR_MARK2_PAR0(n)                          (TSTP_BASE(n) + 0x00a0)
++#define TSTP_ADDR_MARK2_PAR1(n)                          (TSTP_BASE(n) + 0x00a4)
++#define TSTP_ADDR_MARK2_PAR2(n)                          (TSTP_BASE(n) + 0x00a8)
++
++#define	   TIZIANO_ISP_IRQ_AWB_STATIC                          (3)
++#define	   TIZIANO_ISP_IRQ_AE_STATIC			       (4)
++#define	   TIZIANO_ISP_IRQ_AE_HIST			       (5)
++#define	   TIZIANO_ISP_IRQ_AF_STATIC                          (6)
++#define	   TIZIANO_ISP_IRQ_GSM_STATIC                     (7)
++#define	   TIZIANO_ISP_IRQ_LCE_STATIC                          (8)
++#define	   TIZIANO_ISP_IRQ_ADR_STATIC                          (9)
++#define	   TIZIANO_ISP_IRQ_DEFOG_STATIC                        (10)
++#define    TIZIANO_ISP_IRQ_WDR_MAIN_STATIC                     (11)
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-sensor.h b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-sensor.h
+new file mode 100644
+index 000000000..55c4fea1c
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-sensor.h
+@@ -0,0 +1,97 @@
++#ifndef __ISP_SENSOR_H__
++#define __ISP_SENSOR_H__
++
++#define V4L2_CID_USER_ANALOG_GAIN_SHORT             (V4L2_CID_USER_BASE + 0x1090)
++#define V4L2_CID_USER_EXPOSURE_SHORT             (V4L2_CID_USER_BASE + 0x1091)
++
++enum  mipi_sensor_data_type_value {
++	YUV422_8BIT = 0x1e,
++	RAW8 = 0x2a,
++	RAW10 = 0x2b,
++	RAW12 = 0x2c,
++};
++
++enum tx_sensor_frm_mode {
++	TX_SENSOR_DEFAULT_FRAME_MODE = 0,
++	TX_SENSOR_WDR_2_FRAME_MODE,
++	TX_SENSOR_WDR_3_FRAME_MODE,
++	TX_SENSOR_WDR_4_FRAME_MODE,
++};
++
++enum tx_sensor_mode {
++	TX_SENSOR_DEFAULT_MODE = 0,
++	TX_SENSOR_NOT_VC_MODE,
++	TX_SENSOR_VC_MODE,
++};
++
++enum tx_sensor_csi_fmt {
++	TX_SENSOR_RAW8 = 0,
++	TX_SENSOR_RAW10,
++	TX_SENSOR_RAW12,
++};
++
++typedef enum {
++	SENSOR_MIPI_OTHER_MODE,
++	SENSOR_MIPI_SONY_MODE,
++}sensor_mipi_mode;
++
++struct mipi_cfg {
++	unsigned int clk;
++	unsigned int twidth;
++	unsigned int theight;
++	sensor_mipi_mode mipi_mode;
++	unsigned int hcrop_diff_en;
++	unsigned int mipi_vcomp_en;
++	unsigned int mipi_hcomp_en;
++	unsigned short mipi_crop_start0x;
++	unsigned short mipi_crop_start0y;
++	unsigned short mipi_crop_start1x;
++	unsigned short mipi_crop_start1y;
++	unsigned short mipi_crop_start2x;
++	unsigned short mipi_crop_start2y;
++	unsigned short mipi_crop_start3x;
++	unsigned short mipi_crop_start3y;
++	unsigned int line_sync_mode;
++	unsigned int work_start_flag;
++	unsigned int data_type_en;
++	enum  mipi_sensor_data_type_value data_type_value;
++	unsigned int del_start;
++	unsigned int sensor_fid_mode;
++	enum tx_sensor_frm_mode sensor_frame_mode;
++	enum tx_sensor_mode sensor_mode;
++	enum tx_sensor_csi_fmt sensor_csi_fmt;
++};
++
++struct dvp_cfg {
++
++};
++
++typedef enum {
++	START_FIELD_ODD,
++	START_FIELD_EVEN,
++}start_field;
++
++typedef enum {
++	EAV_BF_SAV,
++	SAV_BF_EAV,
++}bt_sav_eav;
++
++struct bt_cfg {
++	unsigned int interlace_en;
++	start_field start_field;
++	bt_sav_eav bt_sav_eav;
++};
++
++struct sensor_info {
++	unsigned int fps;
++	unsigned int total_width;
++	unsigned int total_height;
++	int wdr_en;
++	union {
++		struct mipi_cfg mipi_cfg;
++		struct dvp_cfg dvp_cfg;
++		struct bt_cfg bt_cfg;
++	};
++};
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-video-mplane.c b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-video-mplane.c
+new file mode 100644
+index 000000000..3c06e109b
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-video-mplane.c
+@@ -0,0 +1,729 @@
++#include <linux/clk.h>
++#include <linux/media-bus-format.h>
++#include <linux/media.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_graph.h>
++#include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
++#include <linux/pm_domain.h>
++#include <linux/slab.h>
++#include <linux/videodev2.h>
++#include <linux/component.h>
++#include <linux/mutex.h>
++
++#include <media/media-device.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-event.h>
++#include <media/v4l2-ioctl.h>
++#include <media/v4l2-dev.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++
++#include "isp-drv.h"
++#define ISP_VIDEO_DRIVER_NAME	"ispvideo"
++
++
++
++static struct v4l2_subdev *
++isp_video_remote_subdev(struct isp_video_device *ispvideo, u32 *pad)
++{
++        struct media_pad *remote;
++
++	printk("------%s, %d\n", __func__, __LINE__);
++
++        remote = media_entity_remote_pad(&ispvideo->pad);
++
++        if (remote == NULL ||
++            media_entity_type(remote->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
++                return NULL;
++
++        if (pad)
++                *pad = remote->index;
++
++        return media_entity_to_v4l2_subdev(remote->entity);
++}
++
++
++/* -----------------------------------------------------------------------------
++ * V4L2 ioctls
++ */
++
++static int
++isp_video_querycap(struct file *file, void *fh, struct v4l2_capability *cap)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++
++        strlcpy(cap->driver, ISP_VIDEO_DRIVER_NAME, sizeof(cap->driver));
++        strlcpy(cap->card, ispvideo->video.name, sizeof(cap->card));
++        strlcpy(cap->bus_info, "media", sizeof(cap->bus_info));
++
++	cap->capabilities = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING | V4L2_CAP_DEVICE_CAPS;
++
++	cap->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING;
++
++        return 0;
++}
++
++static int isp_video_enum_fmt_vid_cap_mplane(struct file *file, void *fh,
++					    struct v4l2_fmtdesc *f)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	const struct isp_video_format *fmt = NULL;
++
++	fmt = ispvideo->ops->find_format(NULL, NULL, f->index);
++	if(fmt == NULL) {
++		return -EINVAL;
++	}
++	strlcpy(f->description, fmt->name, sizeof(f->description));
++	f->pixelformat = fmt->fourcc;
++
++	return 0;
++}
++static int
++isp_video_g_fmt_vid_cap_mplane(struct file *file, void *fh, struct v4l2_format *format)
++{
++        struct isp_video_ctx *ctx = to_isp_video_ctx(fh);
++        struct isp_video_device *ispvideo = video_drvdata(file);
++
++	printk("------%s, %d\n", __func__, __LINE__);
++
++        //mutex_lock(&ispvideo->mutex);
++	if(ctx->format.type == 0) {
++		dev_warn(ispvideo->dev, "Format not setted before calling g_fmt\n");
++	} else {
++        	*format = ctx->format;
++	}
++        //mutex_unlock(&ispvideo->mutex);
++
++        return 0;
++}
++
++static int
++__isp_video_try_format(struct isp_video_device *ispvideo, struct v4l2_pix_format_mplane *pix_mp,
++		const struct isp_video_format **ofmt)
++{
++	struct v4l2_plane_pix_format *plane_fmt;
++	struct isp_video_format *fmt = NULL;
++
++	fmt = ispvideo->ops->find_format(&pix_mp->pixelformat, NULL, -1);
++	if(fmt == NULL) {
++		dev_err(ispvideo->dev, "Cannot find appropriate format for pix->pixelformat:[%x]\n", pix_mp->pixelformat);
++		return -EINVAL;
++	}
++
++	pix_mp->colorspace = fmt->colorspace;
++	pix_mp->field = V4L2_FIELD_NONE;
++	pix_mp->pixelformat = fmt->fourcc;
++	pix_mp->num_planes = fmt->num_planes;
++
++	plane_fmt = &pix_mp->plane_fmt[0];
++	plane_fmt->bytesperline = pix_mp->width * fmt->depth[0] / 8;
++	plane_fmt->sizeimage = plane_fmt->bytesperline * pix_mp->height;
++
++	plane_fmt = &pix_mp->plane_fmt[1];
++	plane_fmt->bytesperline = pix_mp->width * fmt->depth[1] / 8;
++	plane_fmt->sizeimage = plane_fmt->bytesperline * pix_mp->height;
++
++	if(ofmt) {
++		*ofmt = fmt;
++	}
++
++	/*TODO, bound width and height!*/
++	printk("=======%s,%d, pixelformat: %x, widht: %d, height: %d, num_planes: %d\n", __func__, __LINE__, pix_mp->pixelformat, pix_mp->width, pix_mp->height, pix_mp->num_planes);
++
++	return 0;
++}
++
++static void to_v4l2_mbus_framefmt(struct isp_video_device *ispvideo, struct v4l2_format *format, struct v4l2_mbus_framefmt *fmt)
++{
++	struct v4l2_pix_format_mplane *pix_mp = &format->fmt.pix_mp;
++	struct isp_video_format *ispfmt = NULL;
++
++	ispfmt = ispvideo->ops->find_format(&pix_mp->pixelformat, NULL, -1);
++
++	fmt->width = pix_mp->width;
++	fmt->height = pix_mp->height;
++	fmt->code = ispfmt->mbus_code;
++	fmt->field = pix_mp->field;
++	fmt->colorspace = pix_mp->colorspace;
++	fmt->ycbcr_enc = pix_mp->ycbcr_enc;
++	fmt->quantization = pix_mp->quantization;
++	fmt->xfer_func = pix_mp->xfer_func;
++}
++
++static int
++isp_video_s_fmt_vid_cap_mplane(struct file *file, void *fh, struct v4l2_format *format)
++{
++        struct isp_video_ctx *ctx = to_isp_video_ctx(fh);
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	struct v4l2_subdev *sd = NULL;
++	struct v4l2_subdev_format subdev_fmt;
++	unsigned int pad = 0;
++	int ret = 0;
++
++	if(vb2_is_busy(&ctx->queue)) {
++		return -EBUSY;
++	}
++
++	ret = __isp_video_try_format(ispvideo, &format->fmt.pix_mp, NULL);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "Failed to set format cap!\n");
++		return -EINVAL;
++	}
++
++	sd = isp_video_remote_subdev(ispvideo, &pad);
++	if(sd == NULL) {
++		return -EINVAL;
++	}
++
++	ctx->format = *format;
++
++	to_v4l2_mbus_framefmt(ispvideo, format, &subdev_fmt.format);
++
++	subdev_fmt.pad = pad;
++	subdev_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++
++	ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &subdev_fmt);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "Failed to set subdev format\n");
++		return -EINVAL;
++	}
++
++	//printk("-%s, %d--ctx: %x--queue: %x, queue->lock: %x\n", __func__, __LINE__, ctx, &ctx->queue, ctx->queue.lock);
++	return 0;
++}
++
++static int
++isp_video_try_format_cap_mplane(struct file *file, void *fh, struct v4l2_format *format)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	int ret = 0;
++
++	printk("-----------%s, %d------------\n", __func__, __LINE__);
++
++	ret = __isp_video_try_format(ispvideo, &format->fmt.pix_mp, NULL);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "Try format cap mplane error!\n");
++		return -EINVAL;
++	}
++	return 0;
++}
++
++static int
++isp_video_cropcap(struct file *file, void *fh, struct v4l2_cropcap *cropcap)
++{
++	printk("-----------%s, %d------------\n", __func__, __LINE__);
++	return 0;
++}
++
++static int
++isp_video_get_crop(struct file *file, void *fh, struct v4l2_crop *crop)
++{
++	printk("-----------%s, %d------------\n", __func__, __LINE__);
++	return 0;
++}
++
++static int
++isp_video_set_crop(struct file *file, void *fh, const struct v4l2_crop *crop)
++{
++	printk("-----------%s, %d------------\n", __func__, __LINE__);
++	return 0;
++}
++
++static int isp_video_enum_input(struct file *file, void *priv,
++				 struct v4l2_input *inp)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++
++	if (inp->index != 0)
++		return -EINVAL;
++
++	/* default is camera */
++	inp->type = V4L2_INPUT_TYPE_CAMERA;
++	inp->std = ispvideo->video.tvnorms;
++	strcpy(inp->name, "Camera");
++
++	return 0;
++}
++
++static int isp_video_g_input(struct file *file, void *priv, unsigned int *i)
++{
++	*i = 0;
++
++	return 0;
++}
++
++static int isp_video_s_input(struct file *file, void *priv, unsigned int i)
++{
++	if (i > 0)
++		return -EINVAL;
++
++	return 0;
++}
++
++static const struct v4l2_ioctl_ops isp_video_ioctl_ops = {
++        .vidioc_querycap                = isp_video_querycap,
++	.vidioc_enum_fmt_vid_cap_mplane	= isp_video_enum_fmt_vid_cap_mplane,
++        .vidioc_g_fmt_vid_cap_mplane    = isp_video_g_fmt_vid_cap_mplane,
++        .vidioc_s_fmt_vid_cap_mplane    = isp_video_s_fmt_vid_cap_mplane,
++        .vidioc_try_fmt_vid_cap_mplane  = isp_video_try_format_cap_mplane,
++        .vidioc_cropcap                 = isp_video_cropcap,
++        .vidioc_g_crop                  = isp_video_get_crop,
++        .vidioc_s_crop                  = isp_video_set_crop,
++        .vidioc_reqbufs                 = vb2_ioctl_reqbufs,
++        .vidioc_querybuf                = vb2_ioctl_querybuf,
++        .vidioc_qbuf                    = vb2_ioctl_qbuf,
++        .vidioc_dqbuf                   = vb2_ioctl_dqbuf,
++        .vidioc_streamon                = vb2_ioctl_streamon,
++        .vidioc_streamoff               = vb2_ioctl_streamoff,
++	.vidioc_enum_input		= isp_video_enum_input,
++	.vidioc_g_input			= isp_video_g_input,
++	.vidioc_s_input			= isp_video_s_input,
++};
++
++/* -----------------------------------------------------------------------------
++ * Video queue operations
++ */
++
++static int isp_video_queue_setup(struct vb2_queue *queue,
++                                 const void *parg,
++                                 unsigned int *count, unsigned int *num_planes,
++                                 unsigned int sizes[], void *alloc_ctxs[])
++{
++        struct isp_video_ctx *ctx = vb2_get_drv_priv(queue);
++        struct isp_video_device *ispvideo = ctx->ispvideo;
++	struct v4l2_format *format = &ctx->format;
++	int i = 0;
++
++	if(*num_planes) {
++		for(i = 0; i < *num_planes; i++) {
++			if(sizes[i] < format->fmt.pix_mp.plane_fmt[i].sizeimage) {
++				return -EINVAL;
++			}
++		}
++	} else {
++		*num_planes = format->fmt.pix_mp.num_planes;
++		for(i = 0; i < *num_planes; i++) {
++			sizes[i] = format->fmt.pix_mp.plane_fmt[i].sizeimage;
++			alloc_ctxs[i] = ispvideo->alloc_ctx;
++		}
++	}
++
++	/*MAX_BUFFER_NUMS:*/
++	if(*count >= 3) {
++		*count = 3;
++	}
++
++        return 0;
++}
++
++static int isp_video_buffer_prepare(struct vb2_buffer *buf)
++{
++	struct isp_video_ctx *ctx = vb2_get_drv_priv(buf->vb2_queue);
++	struct v4l2_format *format = &ctx->format;
++	struct v4l2_pix_format_mplane *pix_mp = &format->fmt.pix_mp;
++	int i;
++
++	for(i = 0; i < buf->num_planes; i++) {
++		vb2_set_plane_payload(buf, i, pix_mp->plane_fmt[i].sizeimage);
++	}
++
++        return 0;
++}
++
++static void isp_video_buffer_queue(struct vb2_buffer *buf)
++{
++        struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(buf);
++	struct isp_video_ctx *ctx = vb2_get_drv_priv(buf->vb2_queue);
++	struct isp_video_buffer *isp_buffer = to_isp_buffer(vbuf);
++	struct isp_video_device *ispvideo = ctx->ispvideo;
++	int ret = 0;
++
++	ret = ispvideo->ops->qbuf(ispvideo, isp_buffer);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "failed to queue buf!\n");
++	}
++}
++
++static int isp_video_subdev_init(struct isp_video_device *ispvideo)
++{
++	struct media_entity *entity = &ispvideo->video.entity;
++	struct v4l2_subdev *sd = NULL;
++	struct media_pad *pad = NULL;
++	int ret = 0;
++
++	/*subdevs reset.*/
++	while(1) {
++		pad = &entity->pads[0];
++		/*直到找到该pipeline上的仅有一个FL_SOURCE pad设备.*/
++		if(!(pad->flags & MEDIA_PAD_FL_SINK))
++			break;
++
++		pad = media_entity_remote_pad(pad);
++		if (pad == NULL ||
++				media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
++			break;
++		entity = pad->entity;
++		sd = media_entity_to_v4l2_subdev(entity);
++
++		/*stream on*/
++		v4l2_set_subdev_hostdata(sd, ispvideo);
++		ret = v4l2_subdev_call(sd, core, init, 1);
++		if(ret < 0 && ret != -ENOIOCTLCMD) {
++			dev_err(ispvideo->dev, "failed to reset subdev[%s]\n", entity->name);
++		} else {
++			ret = 0;
++		}
++	}
++
++	return ret;
++}
++
++static int isp_video_subdev_reset(struct isp_video_device *ispvideo)
++{
++	struct media_entity *entity = &ispvideo->video.entity;
++	struct v4l2_subdev *sd = NULL;
++	struct media_pad *pad = NULL;
++	int ret = 0;
++
++	/*subdevs reset.*/
++	while(1) {
++		pad = &entity->pads[0];
++		/*直到找到该pipeline上的仅有一个FL_SOURCE pad设备.*/
++		if(!(pad->flags & MEDIA_PAD_FL_SINK))
++			break;
++
++		pad = media_entity_remote_pad(pad);
++		if (pad == NULL ||
++				media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
++			break;
++		entity = pad->entity;
++		sd = media_entity_to_v4l2_subdev(entity);
++
++		/*stream on*/
++		v4l2_set_subdev_hostdata(sd, ispvideo);
++		ret = v4l2_subdev_call(sd, core, reset, 1);
++		if(ret < 0 && ret != -ENOIOCTLCMD) {
++			dev_err(ispvideo->dev, "failed to reset subdev[%s]\n", entity->name);
++		} else {
++			ret = 0;
++		}
++	}
++
++	return ret;
++
++}
++
++static int isp_video_subdev_stream(struct isp_video_device *ispvideo, int enable)
++{
++	struct media_entity *entity = &ispvideo->video.entity;
++	struct v4l2_subdev *sd = NULL;
++	struct media_pad *pad = NULL;
++	int ret = 0;
++
++	/*subdevs stream on.*/
++	while(1) {
++		pad = &entity->pads[0];
++		/*直到找到该pipeline上的仅有一个FL_SOURCE pad设备.*/
++		if(!(pad->flags & MEDIA_PAD_FL_SINK))
++			break;
++
++		pad = media_entity_remote_pad(pad);
++		if (pad == NULL ||
++				media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
++			break;
++		entity = pad->entity;
++		sd = media_entity_to_v4l2_subdev(entity);
++
++		/*stream on*/
++		v4l2_set_subdev_hostdata(sd, ispvideo);
++		ret = v4l2_subdev_call(sd, video, s_stream, enable);
++		if(ret < 0) {
++			dev_err(ispvideo->dev, "unable to start stream[%s]\n", entity->name);
++		}
++
++	}
++
++	return ret;
++}
++
++static int isp_video_start_streaming(struct vb2_queue *q, unsigned int count)
++{
++	struct isp_video_ctx *ctx = vb2_get_drv_priv(q);
++	struct isp_video_device *ispvideo = ctx->ispvideo;
++	struct media_entity *entity = &ispvideo->video.entity;
++	struct isp_pipeline *pipe = &ispvideo->pipe;
++	int ret = 0;
++	printk("-----*********  -%s, %d\n", __func__, __LINE__);
++
++	mutex_lock(&ispvideo->stream_lock);
++	ret = media_entity_pipeline_start(entity, &pipe->pipeline);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "Failed to start pipeline\n");
++		goto err_pipeline_start;
++	}
++
++	ret = isp_video_subdev_reset(ispvideo);
++
++
++	ret = isp_video_subdev_init(ispvideo);
++
++
++	ret = isp_video_subdev_stream(ispvideo, 1);
++
++	if(ret < 0) {
++		goto err_start_stream;
++	}
++
++	mutex_unlock(&ispvideo->stream_lock);
++
++	return 0;
++
++err_start_stream:
++	media_entity_pipeline_stop(entity);
++err_pipeline_start:
++	mutex_unlock(&ispvideo->stream_lock);
++	return ret;
++}
++static void isp_video_stop_streaming(struct vb2_queue *q)
++{
++	struct isp_video_ctx *ctx = vb2_get_drv_priv(q);
++	struct isp_video_device *ispvideo = ctx->ispvideo;
++	struct media_entity *entity = &ispvideo->video.entity;
++	//struct isp_pipeline *pipe = &ispvideo->pipe;
++	struct v4l2_subdev *sd = NULL;
++	struct media_pad *pad = NULL;
++	unsigned int is_streaming = 0;
++	int ret = 0;
++
++	mutex_lock(&ispvideo->stream_lock);
++
++	is_streaming = vb2_is_streaming(q);
++
++	if(!is_streaming)
++		goto done;
++
++	/*subdevs stream off.*/
++	while(1) {
++		pad = &entity->pads[0];
++		/*直到找到该pipeline上的仅有一个FL_SOURCE pad设备.*/
++		if(!(pad->flags & MEDIA_PAD_FL_SINK))
++			break;
++
++		pad = media_entity_remote_pad(pad);
++		if (pad == NULL ||
++				media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
++			break;
++		entity = pad->entity;
++		sd = media_entity_to_v4l2_subdev(entity);
++
++		/*stream on*/
++		v4l2_set_subdev_hostdata(sd, ispvideo);
++		ret = v4l2_subdev_call(sd, video, s_stream, 0);
++		if(ret < 0) {
++			dev_err(ispvideo->dev, "unable to start stream[%s]\n", entity->name);
++			break;
++		}
++
++	}
++	media_entity_pipeline_stop(&ispvideo->video.entity);
++
++done:
++	mutex_unlock(&ispvideo->stream_lock);
++}
++
++static const struct vb2_ops isp_video_queue_ops = {
++        .queue_setup = isp_video_queue_setup,
++        .buf_prepare = isp_video_buffer_prepare,
++        .buf_queue = isp_video_buffer_queue,
++	.start_streaming = isp_video_start_streaming,
++	.stop_streaming = isp_video_stop_streaming,
++};
++
++
++static int isp_video_open(struct file *file)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	struct video_device *vdev = &ispvideo->video;
++	struct isp_video_ctx *ctx = NULL;
++	struct vb2_queue *queue = NULL;
++	int ret = 0;
++	printk("-----name: %s %s, %d \n", ispvideo->name, __func__, __LINE__);
++        mutex_lock(&ispvideo->mutex);
++	if(ispvideo->queue != NULL) {
++		mutex_unlock(&ispvideo->mutex);
++		return -EBUSY;
++	}
++
++	ctx = kzalloc(sizeof(struct isp_video_ctx), GFP_KERNEL);
++	if(IS_ERR_OR_NULL(ctx)) {
++		dev_err(ispvideo->ispcam->dev, "Failed to alloc ctx for isp_video_ctx\n");
++		ret = -ENOMEM;
++		goto err_ctx_alloc;
++	}
++
++	v4l2_fh_init(&ctx->fh, &ispvideo->video);
++	v4l2_fh_add(&ctx->fh);
++
++	queue = &ctx->queue;
++	queue->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
++	queue->io_modes = VB2_MMAP;
++	queue->drv_priv = ctx;
++	queue->ops = &isp_video_queue_ops;
++	queue->mem_ops = &vb2_dma_contig_memops;
++	queue->buf_struct_size = sizeof(struct isp_video_buffer);
++	queue->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
++	queue->lock = &ispvideo->queue_lock;
++
++	ret = vb2_queue_init(&ctx->queue);
++	if(ret < 0) {
++		goto err_vb2_queue_init;
++	}
++
++	ctx->ispvideo = ispvideo;
++	vdev->queue = ispvideo->queue = queue;
++
++	file->private_data = &ctx->fh;
++
++	mutex_unlock(&ispvideo->mutex);
++
++	return 0;
++err_vb2_queue_init:
++	v4l2_fh_del(&ctx->fh);
++	kfree(ctx);
++err_ctx_alloc:
++	mutex_unlock(&ispvideo->mutex);
++	return ret;
++}
++static int isp_video_release(struct file *file)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	struct video_device *vdev = &ispvideo->video;
++	struct v4l2_fh *fh = file->private_data;
++	struct isp_video_ctx *ctx = to_isp_video_ctx(fh);
++
++	printk("-----name: %s %s, %d \n", ispvideo->name, __func__, __LINE__);
++	/*lock*/
++
++	mutex_lock(&ispvideo->mutex);
++
++	vb2_queue_release(&ctx->queue);
++	v4l2_fh_del(&ctx->fh);
++	v4l2_fh_exit(&ctx->fh);
++
++	kfree(ctx);
++	file->private_data = NULL;
++	vdev->queue = ispvideo->queue = NULL;
++
++	mutex_unlock(&ispvideo->mutex);
++
++	/*unlock*/
++
++	return 0;
++}
++
++#if 0
++static unsigned int isp_video_poll(struct file *file, poll_table *wait)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	struct v4l2_fh *fh = file->private_data;
++	struct isp_video_ctx *ctx = to_isp_video_ctx(fh);
++	int ret = 0;
++	printk("-----name: %s %s, %d \n", ispvideo->name, __func__, __LINE__);
++
++	mutex_lock(&ispvideo->queue_lock);
++	ret = vb2_poll(&ctx->queue, file, wait);
++	mutex_unlock(&ispvideo->queue_lock);
++
++	return ret;
++}
++
++static int isp_video_mmap(struct file *file, struct vm_area_struct *vma)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct v4l2_fh *fh = file->private_data;
++	struct isp_video_ctx *ctx = to_isp_video_ctx(fh);
++	printk("-----name: %s %s, %d \n", ispvideo->name, __func__, __LINE__);
++
++	return vb2_mmap(&ctx->queue, vma);
++}
++#endif
++
++static struct v4l2_file_operations isp_video_fops = {
++        .owner = THIS_MODULE,
++        .unlocked_ioctl = video_ioctl2,
++        .open = isp_video_open,
++        .release = isp_video_release,
++        .poll = vb2_fop_poll, /*isp_video_poll,*/
++        .mmap = vb2_fop_mmap, /*isp_video_mmap,*/
++};
++
++
++int isp_video_init(struct isp_video_device *ispvideo, char *name, const struct isp_video_ops *video_ops)
++{
++	int ret = 0;
++	struct video_device *video = &ispvideo->video;
++
++
++	/*创建buffer分�器*/
++	ispvideo->alloc_ctx = ingenic_vb2_dma_contig_init_ctx(ispvideo->ispcam->dev);
++	if(IS_ERR(ispvideo)) {
++		return -ENOMEM;
++	}
++
++	/*�始化一个sink pad*/
++	ispvideo->pad.flags = MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
++	ret = media_entity_pads_init(&video->entity, 1, &ispvideo->pad);
++	if(ret < 0) {
++		/*TODO: error case*/
++	}
++
++	mutex_init(&ispvideo->queue_lock);
++	mutex_init(&ispvideo->mutex);
++	mutex_init(&ispvideo->stream_lock);
++
++	snprintf(video->name, sizeof(video->name), "isp-%s", name);
++	video->fops = &isp_video_fops;
++	video->ioctl_ops = &isp_video_ioctl_ops;
++	video->release = video_device_release_empty;
++
++	ispvideo->name = video->name;
++	ispvideo->ops = video_ops;
++	ispvideo->dev = ispvideo->ispcam->dev;
++
++	video_set_drvdata(&ispvideo->video, ispvideo);
++
++	return 0;
++
++}
++
++int isp_video_cleanup(struct isp_video_device *ispvideo)
++{
++
++	return 0;
++}
++
++int isp_video_register(struct isp_video_device *ispvideo, struct v4l2_device *v4l2_dev)
++{
++	struct video_device *video = &ispvideo->video;
++	int ret = 0;
++
++	video->v4l2_dev = v4l2_dev;
++
++	ret = video_register_device(video, VFL_TYPE_GRABBER, -1);
++	if(ret < 0) {
++	/*TODO: error case*/
++	}
++
++	dev_info(ispvideo->dev, "register video device %s @ /dev/video%d ok\n", video->name, video->index);
++
++	return ret;
++}
++int isp_video_unregister(struct isp_video_device *ispvideo)
++{
++
++	return 0;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-video.c b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-video.c
+new file mode 100644
+index 000000000..04abbf3bc
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp-video.c
+@@ -0,0 +1,992 @@
++#include <linux/clk.h>
++#include <linux/media-bus-format.h>
++#include <linux/media.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_graph.h>
++#include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
++#include <linux/pm_domain.h>
++#include <linux/slab.h>
++#include <linux/videodev2.h>
++#include <linux/component.h>
++#include <linux/mutex.h>
++
++#include <media/media-device.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-event.h>
++#include <media/v4l2-ioctl.h>
++#include <media/v4l2-dev.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++
++#include "isp-drv.h"
++#define ISP_VIDEO_DRIVER_NAME	"ispvideo"
++
++int isp_max_buffer_num = 3;
++module_param(isp_max_buffer_num, int, 0644);
++MODULE_PARM_DESC(isp_max_buffer_num, "isp max buffer numer");
++
++int isp_force_img_depth = 0;
++module_param(isp_force_img_depth, int, 0644);
++MODULE_PARM_DESC(isp_force_img_depth, "force fmt depth, usefull when need mem more than real fmt.");
++
++struct sensor_id_t {
++	unsigned int sensor_id;
++	bool available;
++};
++
++struct sensor_id_t sensor_id_pool[2] = {
++	{.sensor_id = 0,
++	.available = true},
++	{.sensor_id = 1,
++	.available = true},
++};
++
++static int get_sensor_id(void)
++{
++	int i;
++	for(i=0; i < 2; i++) {
++		if(sensor_id_pool[i].available){
++			sensor_id_pool[i].available = false;
++			return sensor_id_pool[i].sensor_id;
++		}
++	}
++	return -1;
++}
++
++static void put_sensor_id(unsigned int sensor_id)
++{
++	sensor_id_pool[sensor_id].available = true;
++}
++
++struct mutex sensor_id_lock;
++
++static struct v4l2_subdev *
++isp_video_remote_subdev(struct isp_video_device *ispvideo, u32 *pad)
++{
++        struct media_pad *remote;
++
++        remote = media_entity_remote_pad(&ispvideo->pad);
++
++        if (remote == NULL || !is_media_entity_v4l2_subdev(remote->entity))
++                return NULL;
++
++        if (pad)
++                *pad = remote->index;
++
++        return media_entity_to_v4l2_subdev(remote->entity);
++}
++
++
++/* -----------------------------------------------------------------------------
++ * V4L2 ioctls
++ */
++
++static int
++isp_video_querycap(struct file *file, void *fh, struct v4l2_capability *cap)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++
++        strlcpy(cap->driver, ISP_VIDEO_DRIVER_NAME, sizeof(cap->driver));
++        strlcpy(cap->card, ispvideo->video.name, sizeof(cap->card));
++        strlcpy(cap->bus_info, "media", sizeof(cap->bus_info));
++
++	cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING | V4L2_CAP_DEVICE_CAPS;
++
++	cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
++
++        return 0;
++}
++
++static int isp_video_enum_fmt_vid_cap(struct file *file, void *fh,
++					    struct v4l2_fmtdesc *f)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	const struct isp_video_format *fmt = NULL;
++
++	fmt = ispvideo->ops->find_format(NULL, NULL, f->index);
++	if(fmt == NULL) {
++		return -EINVAL;
++	}
++	strlcpy(f->description, fmt->name, sizeof(f->description));
++	f->pixelformat = fmt->fourcc;
++
++	return 0;
++}
++static int
++isp_video_g_fmt_vid_cap(struct file *file, void *fh, struct v4l2_format *format)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++        struct isp_video_ctx *ctx = ispvideo->ctx;
++
++        //mutex_lock(&ispvideo->mutex);
++	if(ctx->format.type == 0) {
++		dev_warn(ispvideo->dev, "Format not setted before calling g_fmt\n");
++	} else {
++        	*format = ctx->format;
++	}
++        //mutex_unlock(&ispvideo->mutex);
++
++        return 0;
++}
++
++static int
++__isp_video_try_format(struct isp_video_ctx *ctx, struct v4l2_pix_format *pix,
++		const struct isp_video_format **ofmt)
++{
++	struct isp_video_format *fmt = NULL;
++	struct isp_video_device *ispvideo = ctx->ispvideo;
++	unsigned int depth = 0;
++	unsigned int use_depth = 0;
++	int i;
++
++	fmt = ispvideo->ops->find_format(&pix->pixelformat, NULL, -1);
++	if(fmt == NULL) {
++		dev_err(ispvideo->dev, "Cannot find appropriate format for pix->pixelformat:[%x]\n", pix->pixelformat);
++		return -EINVAL;
++	}
++	ispvideo->current_format = fmt;
++
++	for(i = 0; i < fmt->num_planes; i++) {
++		depth += fmt->depth[i];
++	}
++
++	pix->colorspace = fmt->colorspace;
++	pix->field = V4L2_FIELD_NONE;
++	pix->pixelformat = fmt->fourcc;
++	pix->bytesperline = pix->width * depth / 8;
++	//pix->sizeimage = pix->bytesperline * pix->height;
++
++	use_depth = isp_force_img_depth > depth ? isp_force_img_depth : depth;
++	pix->sizeimage = pix->width * use_depth / 8 * pix->height;
++
++	ctx->uv_offset = pix->width * fmt->depth[0] * pix->height / 8;
++	ctx->payload_size = pix->bytesperline * pix->height;
++
++	if(ofmt) {
++		*ofmt = fmt;
++	}
++
++	/*TODO, bound width and height!*/
++	//printk("=======%s,%d, pixelformat: %x, widht: %d, height: %d, num_planes: %d, uv_offset: %d\n", __func__, __LINE__, pix->pixelformat, pix->width, pix->height, fmt->num_planes, ctx->uv_offset);
++
++	return 0;
++}
++
++static void to_v4l2_mbus_framefmt(struct isp_video_device *ispvideo, struct v4l2_format *format, struct v4l2_mbus_framefmt *fmt)
++{
++	struct v4l2_pix_format *pix = &format->fmt.pix;
++	struct isp_video_format *ispfmt = NULL;
++
++	ispfmt = ispvideo->ops->find_format(&pix->pixelformat, NULL, -1);
++
++	fmt->width = pix->width;
++	fmt->height = pix->height;
++	fmt->code = ispfmt->mbus_code;
++	fmt->field = pix->field;
++	fmt->colorspace = pix->colorspace;
++	fmt->ycbcr_enc = pix->ycbcr_enc;
++	fmt->quantization = pix->quantization;
++	fmt->xfer_func = pix->xfer_func;
++}
++
++static int
++isp_video_s_fmt_vid_cap(struct file *file, void *fh, struct v4l2_format *format)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	struct isp_video_ctx *ctx = ispvideo->ctx;
++	struct v4l2_subdev *sd = NULL;
++	struct v4l2_subdev_format subdev_fmt;
++	unsigned int pad = 0;
++	int ret = 0;
++
++
++	if(vb2_is_busy(&ctx->queue)) {
++		return -EBUSY;
++	}
++
++	ret = __isp_video_try_format(ctx, &format->fmt.pix, NULL);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "Failed to set format cap!\n");
++		return -EINVAL;
++	}
++
++	sd = isp_video_remote_subdev(ispvideo, &pad);
++	if(sd == NULL) {
++		return -EINVAL;
++	}
++	v4l2_set_subdev_hostdata(sd, ispvideo);
++
++	ctx->format = *format;
++
++	to_v4l2_mbus_framefmt(ispvideo, format, &subdev_fmt.format);
++
++	subdev_fmt.pad = pad;
++	subdev_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++
++	ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &subdev_fmt);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "Failed to set subdev format\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int
++isp_video_try_format_cap(struct file *file, void *fh, struct v4l2_format *format)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	struct isp_video_ctx *ctx = ispvideo->ctx;
++	int ret = 0;
++
++	ret = __isp_video_try_format(ctx, &format->fmt.pix, NULL);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "Try format cap error!\n");
++		return -EINVAL;
++	}
++	return 0;
++}
++
++static int isp_video_pixelaspect(struct file *file, void *fh, int buf_type, struct v4l2_fract *aspect)
++{
++	printk("-----------%s, %d------------\n", __func__, __LINE__);
++	return 0;
++}
++
++static int
++isp_video_cropcap(struct file *file, void *fh, struct v4l2_cropcap *cropcap)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct mscaler_device 	*mscaler= ispcam->mscaler;
++	int ret = 0;
++
++	ret = v4l2_subdev_call(&mscaler->sd, video, cropcap, cropcap);
++
++	return ret;
++}
++
++static int
++isp_video_get_crop(struct file *file, void *fh, struct v4l2_crop *crop)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct mscaler_device 	*mscaler= ispcam->mscaler;
++	int ret = 0;
++
++	ret = v4l2_subdev_call(&mscaler->sd, video, g_crop, crop);
++
++	return ret;
++}
++
++static int
++isp_video_set_crop(struct file *file, void *fh, const struct v4l2_crop *crop)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct mscaler_device 	*mscaler= ispcam->mscaler;
++	int ret = 0;
++
++	ret = v4l2_subdev_call(&mscaler->sd, video, s_crop, crop);
++
++	return ret;
++}
++
++static int isp_video_get_selection(struct file *file, void *fh, struct v4l2_selection *s)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct v4l2_subdev *sd = NULL;
++	struct v4l2_subdev_selection sel = {0};
++	int ret = 0;
++	int pad = 0;
++
++	sd = isp_video_remote_subdev(ispvideo, &pad);
++	sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	sel.pad = pad;
++	sel.target = s->target;
++	ret = v4l2_subdev_call(sd, pad, get_selection, NULL, &sel);
++	memcpy(&s->r, &sel.r, sizeof(struct v4l2_rect));
++
++	return ret;
++}
++
++static int isp_video_set_selection(struct file *file, void *fh, struct v4l2_selection *s)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct isp_video_ctx *ctx = ispvideo->ctx;
++	struct v4l2_format *format = &ctx->format;
++	struct v4l2_subdev *sd = NULL;
++	struct v4l2_subdev_selection sel;
++	int ret = 0;
++	int pad = 0;
++
++	sd = isp_video_remote_subdev(ispvideo, &pad);
++	sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	sel.pad = pad;
++	sel.flags = s->flags;
++	sel.target = s->target;
++	memcpy(&sel.r, &s->r, sizeof(struct v4l2_rect));
++	ret = v4l2_subdev_call(sd, pad, set_selection, NULL, &sel);
++
++	format->fmt.pix.width = sel.r.width;
++	format->fmt.pix.height = sel.r.height;
++	ret = __isp_video_try_format(ctx, &format->fmt.pix, NULL);
++
++	return ret;
++}
++
++static int isp_video_enum_input(struct file *file, void *priv,
++				 struct v4l2_input *inp)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++
++	if (inp->index != 0)
++		return -EINVAL;
++
++	/* default is camera */
++	inp->type = V4L2_INPUT_TYPE_CAMERA;
++	inp->std = ispvideo->video.tvnorms;
++	strcpy(inp->name, "Camera");
++
++	return 0;
++}
++
++static int isp_video_g_input(struct file *file, void *priv, unsigned int *i)
++{
++	*i = 0;
++
++	return 0;
++}
++
++static int isp_video_s_input(struct file *file, void *priv, unsigned int i)
++{
++	if (i > 0)
++		return -EINVAL;
++
++	return 0;
++}
++
++int isp_video_enum_framesizes(struct file *file, void *fh, struct v4l2_frmsizeenum *fsize)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct mscaler_device 	*mscaler= ispcam->mscaler;
++	struct v4l2_subdev_frame_size_enum fse;
++	int ret = 0;
++
++	fse.code = fsize->pixel_format;
++	fse.index = fsize->index;
++
++	ret = v4l2_subdev_call(&mscaler->sd, pad, enum_frame_size, NULL, &fse);
++	if (ret < 0)
++		return ret;
++
++	fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
++	fsize->discrete.width = fse.min_width;
++	fsize->discrete.height = fse.min_height;
++	return 0;
++}
++
++int isp_video_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a){
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct isp_async_device	*isd	= &ispcam->isd[0];
++	int ret = 0;
++	struct v4l2_subdev_frame_interval interval;
++
++	interval.pad = 0;
++	ret = v4l2_subdev_call(isd->sd, video, g_frame_interval, &interval);
++	if(ret < 0) {
++		return ret;
++	}
++	a->parm.capture.timeperframe.numerator = interval.interval.numerator;
++	a->parm.capture.timeperframe.denominator = interval.interval.denominator;
++	return 0;
++}
++
++extern int isp_video_s_ctrl(struct file *file, void *fh, struct v4l2_control *a);
++extern int isp_video_g_ctrl(struct file *file, void *fh, struct v4l2_control *a);
++
++extern int bypass_video_s_ctrl(struct file *file, void *fh, struct v4l2_control *a);
++extern int bypass_video_g_ctrl(struct file *file, void *fh, struct v4l2_control *a);
++
++static const struct v4l2_ioctl_ops isp_video_ioctl_ops = {
++	.vidioc_querycap                = isp_video_querycap,
++	.vidioc_enum_fmt_vid_cap	= isp_video_enum_fmt_vid_cap,
++	.vidioc_g_fmt_vid_cap    	= isp_video_g_fmt_vid_cap,
++	.vidioc_s_fmt_vid_cap   	= isp_video_s_fmt_vid_cap,
++	.vidioc_try_fmt_vid_cap  	= isp_video_try_format_cap,
++	.vidioc_cropcap                 = isp_video_cropcap,
++	.vidioc_g_crop                  = isp_video_get_crop,
++	.vidioc_s_crop                  = isp_video_set_crop,
++	.vidioc_g_selection             = isp_video_get_selection,
++	.vidioc_s_selection             = isp_video_set_selection,
++	.vidioc_g_pixelaspect		= isp_video_pixelaspect,
++	.vidioc_reqbufs                 = vb2_ioctl_reqbufs,
++	.vidioc_querybuf                = vb2_ioctl_querybuf,
++	.vidioc_qbuf                    = vb2_ioctl_qbuf,
++	.vidioc_dqbuf                   = vb2_ioctl_dqbuf,
++	.vidioc_expbuf			= vb2_ioctl_expbuf,
++	.vidioc_streamon                = vb2_ioctl_streamon,
++	.vidioc_streamoff               = vb2_ioctl_streamoff,
++	.vidioc_enum_input		= isp_video_enum_input,
++	.vidioc_g_input			= isp_video_g_input,
++	.vidioc_s_input			= isp_video_s_input,
++	.vidioc_enum_framesizes		= isp_video_enum_framesizes,
++	.vidioc_g_parm			= isp_video_g_parm,
++	.vidioc_s_ctrl			= isp_video_s_ctrl,
++	.vidioc_g_ctrl			= isp_video_g_ctrl,
++};
++
++static const struct v4l2_ioctl_ops bypass_video_ioctl_ops = {
++        .vidioc_querycap                = isp_video_querycap,	/**/
++	.vidioc_enum_fmt_vid_cap	= isp_video_enum_fmt_vid_cap,
++        .vidioc_g_fmt_vid_cap    	= isp_video_g_fmt_vid_cap,
++        .vidioc_s_fmt_vid_cap   	= isp_video_s_fmt_vid_cap,
++        .vidioc_try_fmt_vid_cap  	= isp_video_try_format_cap,
++	.vidioc_g_pixelaspect		= isp_video_pixelaspect,
++        .vidioc_reqbufs                 = vb2_ioctl_reqbufs,
++        .vidioc_querybuf                = vb2_ioctl_querybuf,
++        .vidioc_qbuf                    = vb2_ioctl_qbuf,
++        .vidioc_dqbuf                   = vb2_ioctl_dqbuf,
++	.vidioc_expbuf			= vb2_ioctl_expbuf,
++        .vidioc_streamon                = vb2_ioctl_streamon,
++        .vidioc_streamoff               = vb2_ioctl_streamoff,
++	.vidioc_enum_input		= isp_video_enum_input,	/**/
++	.vidioc_g_input			= isp_video_g_input,
++	.vidioc_s_input			= isp_video_s_input,
++	.vidioc_enum_framesizes		= isp_video_enum_framesizes,
++	.vidioc_g_parm			= isp_video_g_parm,  /**/
++//	.vidioc_s_ctrl			= bypass_video_s_ctrl,
++//	.vidioc_g_ctrl			= bypass_video_g_ctrl,
++};
++
++/* -----------------------------------------------------------------------------
++ * Video queue operations
++ */
++
++static int isp_video_queue_setup(struct vb2_queue *queue,
++                                 unsigned int *count, unsigned int *num_planes,
++                                 unsigned int sizes[], struct device *alloc_ctxs[])
++{
++        struct isp_video_ctx *ctx = vb2_get_drv_priv(queue);
++        struct isp_video_device *ispvideo = ctx->ispvideo;
++	struct v4l2_format *format = &ctx->format;
++
++	*num_planes = 1;
++
++	sizes[0] = format->fmt.pix.sizeimage;
++	if(sizes[0] == 0) {
++		dev_err(ispvideo->dev, "queue setup 0 sizeimage\n");
++		return -EINVAL;
++	}
++
++	alloc_ctxs[0] = ispvideo->ispcam->dev;
++
++	/*MAX_BUFFER_NUMS:*/
++	if(ispvideo->bypass)
++		isp_max_buffer_num = 5;
++	if(*count >= isp_max_buffer_num) {
++		*count = isp_max_buffer_num;
++	}
++
++	ispvideo->max_buffer_num = *count;
++
++        return 0;
++}
++
++static int isp_video_buffer_prepare(struct vb2_buffer *buf)
++{
++	struct isp_video_ctx *ctx = vb2_get_drv_priv(buf->vb2_queue);
++
++	//vb2_set_plane_payload(buf, 0, format->fmt.pix.sizeimage);
++	vb2_set_plane_payload(buf, 0, ctx->payload_size);
++        return 0;
++}
++
++static void isp_video_buffer_queue(struct vb2_buffer *buf)
++{
++        struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(buf);
++	struct isp_video_ctx *ctx = vb2_get_drv_priv(buf->vb2_queue);
++	struct isp_video_buffer *isp_buffer = to_isp_buffer(vbuf);
++	struct isp_video_device *ispvideo = ctx->ispvideo;
++	int ret = 0;
++
++	isp_buffer->uv_offset = ctx->uv_offset;
++
++	ret = ispvideo->ops->qbuf(ispvideo, isp_buffer);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "failed to queue buf!\n");
++	}
++}
++
++static int isp_video_subdev_init(struct isp_video_device *ispvideo)
++{
++	struct media_entity *entity = &ispvideo->video.entity;
++	struct v4l2_subdev *sd = NULL;
++	struct media_pad *pad = NULL;
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	int ret = 0;
++
++	/*subdevs reset.*/
++	while(1) {
++		pad = &entity->pads[0];
++		/*直到找到该pipeline上的仅有一个FL_SOURCE pad设备.*/
++		if(!(pad->flags & MEDIA_PAD_FL_SINK))
++			break;
++
++		pad = media_entity_remote_pad(pad);
++		if (pad == NULL || !is_media_entity_v4l2_subdev(pad->entity))
++			break;
++		entity = pad->entity;
++		sd = media_entity_to_v4l2_subdev(entity);
++
++		/*stream on*/
++		v4l2_set_subdev_hostdata(sd, ispvideo);
++		ret = v4l2_subdev_call(sd, core, init, ispcam->sensor_id);
++		if(ret < 0 && ret != -ENOIOCTLCMD) {
++			dev_err(ispvideo->dev, "failed to init subdev[%s]\n", entity->name);
++			break;
++		} else {
++			ret = 0;
++		}
++	}
++
++	return ret;
++}
++
++static int isp_video_subdev_reset(struct isp_video_device *ispvideo)
++{
++	struct media_entity *entity = &ispvideo->video.entity;
++	struct v4l2_subdev *sd = NULL;
++	struct media_pad *pad = NULL;
++	int ret = 0;
++
++	/*subdevs reset.*/
++	while(1) {
++		pad = &entity->pads[0];
++		/*直到找到该pipeline上的仅有一个FL_SOURCE pad设备.*/
++		if(!(pad->flags & MEDIA_PAD_FL_SINK))
++			break;
++
++		pad = media_entity_remote_pad(pad);
++		if (pad == NULL || !is_media_entity_v4l2_subdev(pad->entity))
++			break;
++		entity = pad->entity;
++		sd = media_entity_to_v4l2_subdev(entity);
++
++		/*stream on*/
++		v4l2_set_subdev_hostdata(sd, ispvideo);
++		ret = v4l2_subdev_call(sd, core, reset, 1);
++		if(ret < 0 && ret != -ENOIOCTLCMD) {
++			dev_err(ispvideo->dev, "failed to reset subdev[%s]\n", entity->name);
++		} else {
++			ret = 0;
++		}
++	}
++
++	return ret;
++
++}
++
++
++static int isp_video_subdev_streamon(struct isp_video_device *ispvideo)
++{
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct mscaler_device 	*mscaler= ispcam->mscaler;
++	struct isp_device 	*isp	= ispcam->isp;
++	struct vic_device	*vic	= ispcam->vic;
++	struct csi_device 	*csi	= ispcam->csi;
++	struct isp_async_device	*isd	= &ispcam->isd[0];
++	int ret = 0;
++
++	if(!ispvideo->bypass) {
++		v4l2_set_subdev_hostdata(&mscaler->sd, ispvideo);
++		ret = v4l2_subdev_call(&mscaler->sd, video, s_stream, 1);
++		if(ret < 0) {
++			goto mscaler_streamon_err;
++		}
++
++		ret = v4l2_subdev_call(&isp->sd, video, s_stream, 1);
++		if(ret < 0) {
++			goto isp_streamon_err;
++		}
++	}
++
++	if(csi && (isd->bus_type == V4L2_MBUS_CSI2_DPHY)) {
++		ret = v4l2_subdev_call(&csi->sd, video, s_stream, 1);
++		if(ret < 0) {
++			goto csi_streamon_err;
++		}
++	}
++
++	if(!isd->enabled) {
++		ret = v4l2_subdev_call(isd->sd, video, s_stream, 1);
++		if(ret < 0) {
++			goto isd_streamon_err;
++		}
++	}
++	isd->enabled++;
++
++	ret = v4l2_subdev_call(&vic->sd, video, s_stream, 1);
++	if(ret < 0) {
++		goto vic_streamon_err;
++	}
++
++	return ret;
++vic_streamon_err:
++	isd->enabled--;
++	if(!isd->enabled) {
++		ret = v4l2_subdev_call(isd->sd, video, s_stream, 0);
++	}
++isd_streamon_err:
++	if(csi && (isd->bus_type == V4L2_MBUS_CSI2_DPHY))
++		v4l2_subdev_call(&csi->sd, video, s_stream, 0);
++csi_streamon_err:
++	if(!ispvideo->bypass)
++		v4l2_subdev_call(&isp->sd, video, s_stream, 0);
++isp_streamon_err:
++	if(!ispvideo->bypass)
++		v4l2_subdev_call(&mscaler->sd, video, s_stream, 0);
++mscaler_streamon_err:
++	dev_err(ispvideo->dev, "start stream error\n");
++	return ret;
++}
++
++static int isp_video_subdev_streamoff(struct isp_video_device *ispvideo)
++{
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct mscaler_device 	*mscaler= ispcam->mscaler;
++	struct isp_device 	*isp	= ispcam->isp;
++	struct vic_device	*vic	= ispcam->vic;
++	struct csi_device 	*csi	= ispcam->csi;
++	struct isp_async_device	*isd	= &ispcam->isd[0];
++	int ret = 0;
++
++	//global ispcam device mutex.
++	if(!ispvideo->bypass) {
++		v4l2_set_subdev_hostdata(&mscaler->sd, ispvideo);
++		ret = v4l2_subdev_call(&mscaler->sd, video, s_stream, 0);
++		if(ret < 0) {
++			goto err;
++		}
++
++		ret = v4l2_subdev_call(&isp->sd, video, s_stream, 0);
++		if(ret < 0) {
++			goto err;
++		}
++	}
++
++	if(csi && (isd->bus_type == V4L2_MBUS_CSI2_DPHY)) {
++		ret = v4l2_subdev_call(&csi->sd, video, s_stream, 0);
++		if(ret < 0) {
++			goto err;
++		}
++	}
++
++	isd->enabled--;
++	if(!isd->enabled) {
++		ret = v4l2_subdev_call(isd->sd, video, s_stream, 0);
++		if(ret < 0) {
++			goto err;
++		}
++	}
++
++	ret = v4l2_subdev_call(&vic->sd, video, s_stream, 0);
++	if(ret < 0) {
++		goto err;
++	}
++
++	return ret;
++err:
++	dev_err(ispvideo->dev, "start stream error\n");
++	return ret;
++
++}
++
++static int isp_video_subdev_stream(struct isp_video_device *ispvideo, int enable)
++{
++	int ret = 0;
++
++	//mutex lock.
++
++	if(enable) {
++		ret = isp_video_subdev_streamon(ispvideo);
++	} else {
++		ret = isp_video_subdev_streamoff(ispvideo);
++	}
++
++	return ret;
++}
++
++static int isp_video_start_streaming(struct vb2_queue *q, unsigned int count)
++{
++	struct isp_video_ctx *ctx = vb2_get_drv_priv(q);
++	struct isp_video_device *ispvideo = ctx->ispvideo;
++	struct media_entity *entity = &ispvideo->video.entity;
++	struct isp_pipeline *pipe = &ispvideo->pipe;
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	int ret = 0;
++
++	mutex_lock(&ispcam->mutex);
++
++	mutex_lock(&ispvideo->stream_lock);
++
++	if(ispcam->enabled++ == 0) {
++		mutex_lock(&sensor_id_lock);
++		ispcam->sensor_id = get_sensor_id();
++		//printk("~~~~~~~~~~~~~~sensor_id = %d\n", ispcam->sensor_id);
++		if(ispcam->sensor_id < 0)
++			goto err_get_sensor_id;
++		mutex_unlock(&sensor_id_lock);
++		ret = media_pipeline_start(entity, &pipe->pipeline);
++		if(ret < 0) {
++			dev_err(ispvideo->dev, "Failed to start pipeline\n");
++			goto err_pipeline_start;
++		}
++
++		ret = isp_video_subdev_reset(ispvideo);
++		ret = isp_video_subdev_init(ispvideo);
++		if(ret) {
++			dev_err(ispvideo->dev, "Failed to init subdev\n");
++			goto err_subdev_init;
++		}
++	}
++
++	ret = isp_video_subdev_stream(ispvideo, 1);
++
++	if(ret < 0) {
++		goto err_start_stream;
++	}
++
++	mutex_unlock(&ispvideo->stream_lock);
++
++	mutex_unlock(&ispcam->mutex);
++	return 0;
++
++err_start_stream:
++err_subdev_init:
++	media_pipeline_stop(entity);
++err_pipeline_start:
++	put_sensor_id(ispcam->sensor_id);
++err_get_sensor_id:
++	ispcam->enabled--;
++	mutex_unlock(&ispvideo->stream_lock);
++	mutex_unlock(&ispcam->mutex);
++	return ret;
++}
++static void isp_video_stop_streaming(struct vb2_queue *q)
++{
++	struct isp_video_ctx *ctx = vb2_get_drv_priv(q);
++	struct isp_video_device *ispvideo = ctx->ispvideo;
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	unsigned int is_streaming = 0;
++	int ret = 0;
++
++	mutex_lock(&ispcam->mutex);
++
++	mutex_lock(&ispvideo->stream_lock);
++
++
++
++	is_streaming = vb2_is_streaming(q);
++
++	if(!is_streaming)
++		goto done;
++
++	ret = isp_video_subdev_stream(ispvideo, 0);
++
++	if(--ispcam->enabled > 0) {
++		goto finish;
++	}
++
++	mutex_lock(&sensor_id_lock);
++	put_sensor_id(ispcam->sensor_id);
++	mutex_unlock(&sensor_id_lock);
++	media_pipeline_stop(&ispvideo->video.entity);
++
++finish:
++done:
++	mutex_unlock(&ispvideo->stream_lock);
++	mutex_unlock(&ispcam->mutex);
++}
++
++static const struct vb2_ops isp_video_queue_ops = {
++        .queue_setup = isp_video_queue_setup,
++        .buf_prepare = isp_video_buffer_prepare,
++        .buf_queue = isp_video_buffer_queue,
++	.start_streaming = isp_video_start_streaming,
++	.stop_streaming = isp_video_stop_streaming,
++};
++
++
++static int isp_video_open(struct file *file)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	struct video_device *vdev = &ispvideo->video;
++	struct isp_video_ctx *ctx = NULL;
++	struct vb2_queue *queue = NULL;
++	int ret = 0;
++        mutex_lock(&ispvideo->mutex);
++	if(ispvideo->queue != NULL) {
++		mutex_unlock(&ispvideo->mutex);
++		return -EBUSY;
++	}
++
++	ctx = kzalloc(sizeof(struct isp_video_ctx), GFP_KERNEL);
++	if(IS_ERR_OR_NULL(ctx)) {
++		dev_err(ispvideo->ispcam->dev, "Failed to alloc ctx for isp_video_ctx\n");
++		ret = -ENOMEM;
++		goto err_ctx_alloc;
++	}
++
++	v4l2_fh_init(&ctx->fh, &ispvideo->video);
++	v4l2_fh_add(&ctx->fh);
++
++	queue = &ctx->queue;
++	queue->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++	queue->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
++	queue->drv_priv = ctx;
++	queue->ops = &isp_video_queue_ops;
++	queue->mem_ops = &ingenic_vb2_dma_contig_memops;
++	queue->buf_struct_size = sizeof(struct isp_video_buffer);
++	queue->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
++	queue->lock = &ispvideo->queue_lock;
++
++	ret = vb2_queue_init(&ctx->queue);
++	if(ret < 0) {
++		goto err_vb2_queue_init;
++	}
++
++	ctx->ispvideo = ispvideo;
++	ispvideo->ctx = ctx;
++	vdev->queue = ispvideo->queue = queue;
++
++	file->private_data = &ctx->fh;
++
++	mutex_unlock(&ispvideo->mutex);
++
++	return 0;
++err_vb2_queue_init:
++	v4l2_fh_del(&ctx->fh);
++	kfree(ctx);
++err_ctx_alloc:
++	mutex_unlock(&ispvideo->mutex);
++	return ret;
++}
++static int isp_video_release(struct file *file)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	struct video_device *vdev = &ispvideo->video;
++	struct isp_video_ctx *ctx = ispvideo->ctx;
++
++	/*lock*/
++
++	mutex_lock(&ispvideo->mutex);
++
++	vb2_queue_release(&ctx->queue);
++	v4l2_fh_del(&ctx->fh);
++	v4l2_fh_exit(&ctx->fh);
++
++	kfree(ctx);
++	file->private_data = NULL;
++	vdev->queue = ispvideo->queue = NULL;
++
++	mutex_unlock(&ispvideo->mutex);
++
++	/*unlock*/
++
++	return 0;
++}
++
++const static struct v4l2_file_operations isp_video_fops = {
++        .owner = THIS_MODULE,
++        .unlocked_ioctl = video_ioctl2,
++        .open = isp_video_open,
++        .release = isp_video_release,
++        .poll = vb2_fop_poll, /*isp_video_poll,*/
++        .mmap = vb2_fop_mmap, /*isp_video_mmap,*/
++};
++
++
++int isp_video_init(struct isp_video_device *ispvideo, char *name, const struct isp_video_ops *video_ops)
++{
++	int ret = 0;
++	struct video_device *video = &ispvideo->video;
++	struct media_entity *entity = &video->entity;
++	struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
++
++
++	/*创建buffer分�器*/
++	ispvideo->alloc_ctx = ingenic_vb2_dma_contig_init_ctx(ispvideo->ispcam->dev);
++	if(IS_ERR(ispvideo)) {
++		return -ENOMEM;
++	}
++
++	/*�始化一个sink pad*/
++	ispvideo->pad.flags = MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
++	ret = media_entity_pads_init(&video->entity, 1, &ispvideo->pad);
++	if(ret < 0) {
++		/*TODO: error case*/
++	}
++	sd->owner = THIS_MODULE;
++	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++	sd->entity.function = MEDIA_ENT_F_IO_V4L;
++
++	mutex_init(&ispvideo->queue_lock);
++	mutex_init(&ispvideo->mutex);
++	mutex_init(&ispvideo->stream_lock);
++
++	snprintf(video->name, sizeof(video->name), "isp-%s", name);
++	video->fops = &isp_video_fops;
++
++	if(ispvideo->bypass)
++		video->ioctl_ops = &bypass_video_ioctl_ops;
++        else
++		video->ioctl_ops = &isp_video_ioctl_ops;
++
++	video->release = video_device_release_empty;
++	video->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
++
++	ispvideo->name = video->name;
++	ispvideo->ops = video_ops;
++	ispvideo->dev = ispvideo->ispcam->dev;
++
++	video_set_drvdata(&ispvideo->video, ispvideo);
++
++	return 0;
++
++}
++
++int isp_video_cleanup(struct isp_video_device *ispvideo)
++{
++
++	return 0;
++}
++
++int isp_video_register(struct isp_video_device *ispvideo, struct v4l2_device *v4l2_dev, int nr)
++{
++	struct video_device *video = &ispvideo->video;
++	int ret = 0;
++
++	video->v4l2_dev = v4l2_dev;
++
++	ret = video_register_device(video, VFL_TYPE_VIDEO, nr);
++	if(ret < 0) {
++	/*TODO: error case*/
++	}
++
++	dev_info(ispvideo->dev, "register video device %s @ /dev/video%d ok\n", video->name, video->num);
++	mutex_init(&sensor_id_lock);
++
++	return ret;
++}
++int isp_video_unregister(struct isp_video_device *ispvideo)
++{
++
++	return 0;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/isp.c b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp.c
+new file mode 100644
+index 000000000..219554c5d
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/isp.c
+@@ -0,0 +1,1173 @@
++#include <linux/clk.h>
++#include <linux/media-bus-format.h>
++#include <linux/media.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_graph.h>
++#include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
++#include <linux/pm_domain.h>
++#include <linux/slab.h>
++#include <linux/videodev2.h>
++#include <linux/component.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/kthread.h>
++
++#include <media/media-device.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-event.h>
++
++
++
++#include "isp-drv.h"
++#include "isp-regs.h"
++#include "tiziano-isp.h"
++
++int isp_clk = 300000000;
++module_param(isp_clk, int, S_IRUGO);
++MODULE_PARM_DESC(isp_clk, "isp core clock");
++
++struct isp_device *g_isp_device[2] = {0};
++unsigned int MAIN_ISP_INDEX;
++unsigned int SEC_ISP_INDEX;
++unsigned int flag;
++unsigned int isp_enabled;
++
++static inline unsigned int isp_reg_readl(struct isp_device *isp, unsigned int reg)
++{
++	return readl(isp->iobase + reg);
++}
++
++static inline void isp_reg_writel(struct isp_device *isp, unsigned int reg, unsigned int val)
++{
++	writel(val, isp->iobase + reg);
++}
++
++
++
++/* interface used by isp-core.*/
++int system_reg_write(unsigned int reg, unsigned int value)
++{
++	struct isp_device *isp = g_isp_device[0];
++	isp_reg_writel(isp, reg, value);
++	return 0;
++}
++
++unsigned int  system_reg_read(unsigned int reg)
++{
++	struct isp_device *isp = g_isp_device[0];
++	return isp_reg_readl(isp, reg);
++}
++
++int system_irq_func_main_set(int irq, void *func)
++{
++	struct isp_device *core = g_isp_device[MAIN_ISP_INDEX];
++
++	core->irq_func_cb[irq] = func;
++	return 0;
++}
++
++int system_irq_func_sec_set(int irq, void *func)
++{
++	struct isp_device *core = g_isp_device[SEC_ISP_INDEX];
++
++	core->irq_func_cb[irq] = func;
++	return 0;
++}
++
++static int isp_cpm_stop(struct isp_device *isp)
++{
++	int timeout = 0xffffff;
++	unsigned int value = 0;
++
++
++	/*stop request*/
++	value = readl(isp->cpm_reset);
++	value |= 1 << isp->bit_stp;
++	writel(value, isp->cpm_reset);
++
++	/*stop ack*/
++	while(!(readl(isp->cpm_reset) & (1 << isp->bit_ack)) && --timeout);
++
++	if(timeout == 0) {
++		dev_err(isp->dev, "isp wait stop timeout\n");
++		return -ETIMEDOUT;
++	}
++	return 0;
++}
++
++static int isp_cpm_reset(struct isp_device *isp)
++{
++	int timeout = 0xffffff;
++	unsigned int value = 0;
++
++	/*stop request*/
++	value = readl(isp->cpm_reset);
++	value |= 1 << isp->bit_stp;
++	writel(value, isp->cpm_reset);
++
++	/*stop ack*/
++	while(!(readl(isp->cpm_reset) & (1 << isp->bit_ack)) && --timeout);
++
++	if(timeout == 0) {
++		dev_err(isp->dev, "isp wait stop timeout\n");
++		return -ETIMEDOUT;
++	}
++
++	/* activate reset */
++	value = readl(isp->cpm_reset);
++	value &= ~(1 << isp->bit_stp);
++	value |= 1 << isp->bit_sr;
++	writel(value, isp->cpm_reset);
++
++	/* deactive reset */
++	value = readl(isp->cpm_reset);
++	value &= ~(1 << isp->bit_sr);
++	writel(value, isp->cpm_reset);
++
++	return 0;
++}
++
++static int ingenic_isp_parse_dt(struct isp_device * isp)
++{
++	struct device *dev = isp->dev;
++	unsigned int cpm_reset = 0;
++	int ret = 0;
++
++	of_property_read_u32(dev->of_node, "ingenic,index", &isp->index);
++	of_property_read_u32(dev->of_node, "ingenic,cpm_reset", &cpm_reset);
++	of_property_read_u32(dev->of_node, "ingenic,bit_sr", &isp->bit_sr);
++	of_property_read_u32(dev->of_node, "ingenic,bit_stp", &isp->bit_stp);
++	of_property_read_u32(dev->of_node, "ingenic,bit_ack", &isp->bit_ack);
++
++	isp->cpm_reset = (void __iomem *)cpm_reset;
++
++	return ret;
++}
++
++#if 0
++int isp_load_params(tisp_init_param_t *iparam, char *bpath)
++{
++	struct file *file = NULL;
++	struct inode *inode = NULL;
++	mm_segment_t old_fs;
++	loff_t fsize = 0;
++	loff_t *pos = NULL;
++	tisp_bin_t attr;
++	unsigned int ret = 0;
++
++	char file_name[64] = {0};
++
++	old_fs = get_fs();
++	set_fs(KERNEL_DS);
++
++	if(strlen(bpath))
++		sprintf(attr.bname, bpath);
++	else
++		snprintf(attr.bname, sizeof(attr.bname), "/etc/sensor/%s-x2500.bin", iparam->sensor);
++	sprintf(bpath, attr.bname);
++	sprintf(file_name, attr.bname);
++
++	/* open file */
++	file = filp_open(file_name, O_RDONLY, 0);
++	if (file < 0 || IS_ERR(file)) {
++		printk("ISP: open %s file for isp calibrate read failed\n", file_name);
++		ret = -1;
++		iparam->tuned_params = NULL;
++		goto failed_open_file;
++	} 
++
++	/* read file */
++	inode = file->f_inode;
++	fsize = inode->i_size;
++	pos = &(file->f_pos);
++
++	if(iparam->tuned_params == NULL){
++		iparam->tuned_params = kzalloc(fsize, GFP_KERNEL);
++		if(iparam->tuned_params == NULL){
++			printk("%s[%d]: Failed to alloc %lld KB buffer!\n",__func__,__LINE__, fsize >> 10);
++			ret = -1;
++			goto failed_malloc_data;
++		}
++		iparam->tuned_params_size = fsize;
++	}
++
++	vfs_read(file, iparam->tuned_params, fsize, pos);
++
++failed_malloc_data:
++	filp_close(file, NULL);
++	set_fs(old_fs);
++failed_open_file:
++	return ret;
++}
++
++int isp_release_params(tisp_init_param_t *iparam)
++{
++	if(iparam->tuned_params) {
++		kfree(iparam->tuned_params);
++		iparam->tuned_params = NULL;
++		iparam->tuned_params_size = 0;
++	}
++
++	return 0;
++}
++#endif
++
++static int isp_subdev_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct isp_device *isp = v4l2_get_subdevdata(sd);
++	struct ispcam_device *ispcam = isp->ispcam;
++	struct v4l2_subdev_format *input_fmt = &isp->formats[ISP_PAD_SINK];
++	tisp_init_param_t iparam = {0};
++	int ret = 0;
++
++	if(isp_enabled == 0) {
++		ret = isp_cpm_reset(isp);
++		if(ret) {
++			return ret;
++		}
++	}
++
++	isp->sensor_id = val;
++	if(val == 0) {
++		MAIN_ISP_INDEX = isp->index;
++		//printk("MIAN_ISP_INDEC is %d\n",isp->index);
++	} else if(val == 1) {
++		SEC_ISP_INDEX = isp->index;
++		//printk("SEC_ISP_INDEC is %d\n",isp->index);
++	}
++
++	iparam.width = input_fmt->format.width;
++	iparam.height = input_fmt->format.height;
++
++	iparam.WdrEn = isp->sensor_info->wdr_en;
++	iparam.sensorId = isp->sensor_id;  //the sensor id:mark the struct for sensor 0/1
++	memcpy(&iparam.multi_mode, &isp->multi_mode, sizeof(multisensor_mode_t));
++
++	switch(input_fmt->format.code) {
++		case MEDIA_BUS_FMT_SBGGR8_1X8:
++		case MEDIA_BUS_FMT_SGBRG8_1X8:
++		case MEDIA_BUS_FMT_SGRBG8_1X8:
++		case MEDIA_BUS_FMT_SRGGB8_1X8:
++			iparam.bayer = 0;
++			break;
++		case MEDIA_BUS_FMT_SBGGR10_1X10:
++		case MEDIA_BUS_FMT_SGBRG10_1X10:
++		case MEDIA_BUS_FMT_SGRBG10_1X10:
++		case MEDIA_BUS_FMT_SRGGB10_1X10:
++			iparam.bayer = 1 << 16;
++			break;
++		case MEDIA_BUS_FMT_SBGGR12_1X12:
++		case MEDIA_BUS_FMT_SGBRG12_1X12:
++		case MEDIA_BUS_FMT_SGRBG12_1X12:
++		case MEDIA_BUS_FMT_SRGGB12_1X12:
++			iparam.bayer = 2 << 16;
++			break;
++		default:
++			dev_err(isp->dev, "%s[%d] the format(0x%08x) of input couldn't be handled!\n",
++					__func__,__LINE__, input_fmt->format.code);
++			return -EINVAL;
++			break;
++	}
++	switch(input_fmt->format.code) {
++		case MEDIA_BUS_FMT_SBGGR8_1X8:
++		case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
++		case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE:
++		case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
++		case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE:
++		case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE:
++		case MEDIA_BUS_FMT_SBGGR10_1X10:
++		case MEDIA_BUS_FMT_SBGGR12_1X12:
++			iparam.bayer += 1;
++			break;
++		case MEDIA_BUS_FMT_SGBRG8_1X8:
++		case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
++		case MEDIA_BUS_FMT_SGBRG10_1X10:
++		case MEDIA_BUS_FMT_SGBRG12_1X12:
++			iparam.bayer += 3;
++			break;
++		case MEDIA_BUS_FMT_SGRBG8_1X8:
++		case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
++		case MEDIA_BUS_FMT_SGRBG10_1X10:
++		case MEDIA_BUS_FMT_SGRBG12_1X12:
++			iparam.bayer += 2;
++			break;
++		case MEDIA_BUS_FMT_SRGGB8_1X8:
++		case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
++		case MEDIA_BUS_FMT_SRGGB10_1X10:
++		case MEDIA_BUS_FMT_SRGGB12_1X12:
++			iparam.bayer += 0;
++			break;
++		default:
++			dev_err(isp->dev, "%s[%d] the format(0x%08x) of input couldn't be handled!\n",
++					__func__,__LINE__, input_fmt->format.code);
++			return -EINVAL;
++			break;
++	}
++
++
++	strncpy(iparam.sensor, ispcam->isd[0].sd->dev->driver->name, sizeof(iparam.sensor));
++	iparam.sensor_info.fps = isp->sensor_info->fps;
++	iparam.sensor_info.total_width = isp->sensor_info->total_width;
++	iparam.sensor_info.total_height = isp->sensor_info->total_height;
++
++	if(isp->sensor_id == 0)
++		ret = tisp_main_init(&iparam, isp->bpath.path);
++	else if(isp->sensor_id == 1)
++		ret = tisp_sec_init(&iparam, isp->bpath.path);
++
++	if(ret)
++		return ret;
++
++	tisp_stream_on(&iparam);
++	system_reg_write(SEC_MSCA_ADDR_FORCE, 1);
++
++	return 0;
++}
++
++/* interface should be removed. */
++static int isp_subdev_reset(struct v4l2_subdev *sd, u32 val)
++{
++	//struct isp_device *isp = v4l2_get_subdevdata(sd);
++	int ret = 0;
++
++//	ret = isp_cpm_reset(isp);
++
++	return ret;
++}
++
++static const struct v4l2_subdev_core_ops isp_subdev_core_ops = {
++	.init	= isp_subdev_init,
++	.reset = isp_subdev_reset,
++        .log_status = v4l2_ctrl_subdev_log_status,
++        .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
++        .unsubscribe_event = v4l2_event_subdev_unsubscribe,
++};
++
++static int isp_subdev_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct isp_device *isp = v4l2_get_subdevdata(sd);
++	struct media_pad *remote = NULL;
++	struct v4l2_subdev *remote_sd = NULL;
++	struct v4l2_subdev_format remote_subdev_fmt;
++	int ret = 0;
++
++	remote = media_entity_remote_pad(&isp->pads[ISP_PAD_SINK]);
++	remote_sd = media_entity_to_v4l2_subdev(remote->entity);
++
++	/*获��当�格�，�制到输出格�.*/
++	remote_subdev_fmt.pad = remote->index;
++	remote_subdev_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	ret = v4l2_subdev_call(remote_sd, pad, get_fmt, NULL, &remote_subdev_fmt);
++	if(ret < 0) {
++		dev_err(isp->dev, "Failed to get_fmt from remote pad\n");
++		return -EINVAL;
++	}
++
++	/*本身ISP时没有格�区别的， 这里必须从VIC获�，�ISP的SINK_PAD.*/
++	if(format->pad == ISP_PAD_SOURCE) {
++		memcpy(&format->format, &remote_subdev_fmt.format, sizeof(format->format));
++	} else {
++		dev_warn(isp->dev, "ISP_PAD_SOURCE should be set!\n");
++	}
++
++	isp->formats[ISP_PAD_SINK] = isp->formats[ISP_PAD_SOURCE] = *format;
++	isp->sensor_info = (struct sensor_info *)*(unsigned int *)format->format.reserved;
++
++	//printk("----%s, %d, format->pad: %d\n", __func__, __LINE__, format->pad);
++	return 0;
++}
++
++static int isp_subdev_set_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct isp_device *isp = v4l2_get_subdevdata(sd);
++	struct media_pad *remote = NULL;
++	struct v4l2_subdev *remote_sd = NULL;
++	int ret = 0;
++
++	remote = media_entity_remote_pad(&isp->pads[ISP_PAD_SINK]);
++	remote_sd = media_entity_to_v4l2_subdev(remote->entity);
++
++	ret = v4l2_subdev_call(remote_sd, pad, set_fmt, NULL, format);
++	if(ret < 0) {
++		dev_dbg(isp->dev, "Failed to set_fmt from remote pad\n");
++	}
++
++	return 0;
++}
++
++static const struct v4l2_subdev_pad_ops isp_subdev_pad_ops = {
++        .set_fmt                = isp_subdev_set_fmt,
++        .get_fmt                = isp_subdev_get_fmt,
++	/*
++        .init_cfg               = isp_subdev_init_cfg,
++        .enum_mbus_code         = isp_subdev_enum_mbus_code,
++        .enum_frame_size        = isp_subdev_enum_frame_size,
++	*/
++};
++
++static int isp_fw_process(void *data)
++{
++        while(!kthread_should_stop()){
++                tisp_fw_process(0);
++        }
++        return 0;
++}
++
++static int isp_fw_process1(void *data)
++{
++        while(!kthread_should_stop()){
++                tisp_fw_process(1);
++        }
++        return 0;
++}
++
++
++
++dma_addr_t wdr_paddr;
++void *wdr_vaddr;
++int wdr_size;
++
++dma_addr_t dualsensor_paddr;
++void *dualsensor_vaddr;
++int dualsensor_size;
++
++
++int isp_set_wdr(struct isp_device *isp)
++{
++	struct v4l2_subdev_format *input_fmt = &isp->formats[ISP_PAD_SINK];
++	int width = input_fmt->format.width;
++	int height = input_fmt->format.height;
++	uint32_t tsize = width* height * 2 * 2;
++	wdr_size = tsize;
++	wdr_vaddr = dma_alloc_noncoherent(isp->ispcam->dev, tsize, &wdr_paddr, DMA_BIDIRECTIONAL, GFP_KERNEL);
++	if(!wdr_vaddr || !wdr_paddr)
++		return -ENOMEM;
++	system_reg_write(IPC_ADDR_DF_CH0_ADDR, wdr_paddr);
++	system_reg_write(IPC_ADDR_DF_CH0_SIZE , tsize / 2);
++	system_reg_write(IPC_ADDR_DF_CHN_COMP_EN, 0x0);
++	system_reg_write(IPC_ADDR_DF_CH1_ADDR, wdr_paddr);
++	system_reg_write(IPC_ADDR_DF_CH1_SIZE , tsize / 2);
++	return 0;
++}
++
++int isp_set_mdns(struct isp_device *isp)
++{
++
++	struct v4l2_subdev_format *input_fmt = &isp->formats[ISP_PAD_SINK];
++	int width = input_fmt->format.width;
++	int height = input_fmt->format.height;
++	uint32_t tsize = 0;
++	uint32_t tmpsize = 0;
++	uint32_t stride = 0;
++	uint32_t mdns_res_end_point_y;
++	uint32_t mdns_res_end_point_c;
++	int vinum = isp->sensor_id;
++	dma_addr_t mdns_paddr = 0;
++
++	/*get mdns bufinfo*/
++	//Ref Y
++	stride = ((width + 15) / 16) * 16;
++	tmpsize = stride * height + ((stride * height) >> 5) ;
++	tmpsize = ((tmpsize + 1023) / 1024 * 1024);
++	mdns_res_end_point_y = tmpsize / 256;
++	tsize += tmpsize;
++
++	//Ref UV
++	stride = ((width + 31) / 32) * 32;
++	tmpsize = stride*height / 2 + ((stride*height / 2)>>6);
++	tmpsize = ((tmpsize + 1023) / 1024 * 1024);
++	mdns_res_end_point_c = tmpsize / 256;
++	tsize += tmpsize;
++
++	//Bsn
++	stride = ((((width + 7) / 8) + 15) / 16) * 16;
++	tmpsize = (stride * height) / 4;
++	tmpsize = ((tmpsize + 1023) / 1024 * 1024);
++	tsize += tmpsize;
++
++	//Ass
++	stride = ((width + 31) / 32) * 32;
++	tmpsize = stride * height / 2;
++	tmpsize = ((tmpsize + 1023) / 1024 * 1024);
++	tsize += tmpsize;
++
++	//Lynne
++	stride = ((width + 31) / 32) * 16;
++	tmpsize = stride * height / 4;
++	tmpsize = ((tmpsize + 1023) / 1024 * 1024);
++	tsize += tmpsize;
++
++	//	bufinfo.paddr = 0;
++	//	bufinfo.size = tsize;
++	isp->buf_info[MDNS_BUF].size = tsize;
++	isp->buf_info[MDNS_BUF].vaddr = dma_alloc_noncoherent(isp->ispcam->dev, tsize, &isp->buf_info[MDNS_BUF].paddr, DMA_BIDIRECTIONAL, GFP_KERNEL);
++	if(!isp->buf_info[MDNS_BUF].vaddr || !isp->buf_info[MDNS_BUF].paddr)
++		return -ENOMEM;
++
++	mdns_paddr = isp->buf_info[MDNS_BUF].paddr;
++	tsize = 0;
++
++	/*set mdns bufinfo*/
++	//Ref Y
++	stride = ((width + 15) / 16) * 16;
++	tmpsize = stride * height + ((stride * height) >> 5) ;
++	tmpsize = ((tmpsize + 1023) / 1024 * 1024);
++	mdns_res_end_point_y = tmpsize / 256;
++	system_reg_write(MDNS_ADDR_YRESENDPOINT(vinum), mdns_res_end_point_y);
++	system_reg_write(MDNS_ADDR_YREF_ADDR(vinum), mdns_paddr + tsize);
++	system_reg_write(MDNS_ADDR_YREF_STRIDE(vinum), stride);
++	tsize += tmpsize;
++	if (tsize > isp->buf_info[MDNS_BUF].size) {
++		dev_err(isp->dev, "[ %s:%d ] buf size too small\n", __func__, __LINE__);
++		return -EFAULT;
++	}
++
++	//REF UV
++	stride = ((width + 31) / 32) * 32;
++	tmpsize = stride*height / 2 + ((stride*height / 2)>>6);
++	tmpsize = ((tmpsize + 1023) / 1024 * 1024);
++	mdns_res_end_point_c = tmpsize / 256;
++	system_reg_write(MDNS_ADDR_CRESENDPOINT(vinum), mdns_res_end_point_c);
++	system_reg_write(MDNS_ADDR_CREF_ADDR(vinum), mdns_paddr + tsize);
++	system_reg_write(MDNS_ADDR_CREF_STRIDE(vinum), stride);
++	tsize += tmpsize;
++	if (tsize > isp->buf_info[MDNS_BUF].size) {
++		dev_err(isp->dev, "[ %s:%d ] buf size too small\n", __func__, __LINE__);
++		return -EFAULT;
++	}
++
++	//Bsn
++	stride = ((((width + 7) / 8) + 15) / 16) * 16;
++	tmpsize = (stride * height) / 4;
++	tmpsize = ((tmpsize + 1023) /1024 * 1024);
++	system_reg_write(MDNS_ADDR_BSN_ADDR(vinum), mdns_paddr + tsize);
++	system_reg_write(MDNS_ADDR_BSN_STRIDE(vinum), stride);
++	tsize += tmpsize;
++	if (tsize > isp->buf_info[MDNS_BUF].size) {
++		dev_err(isp->dev, "[ %s:%d ] buf size too small\n", __func__, __LINE__);
++		return -EFAULT;
++	}
++
++	//Ass
++	stride = ((width + 31) / 32) * 32;
++	tmpsize = stride * height / 2;
++	tmpsize = ((tmpsize + 1023) /1024 * 1024);
++	system_reg_write(MDNS_ADDR_ASS_ADDR(vinum), mdns_paddr + tsize);
++	system_reg_write(MDNS_ADDR_ASS_STRIDE(vinum), stride);
++	tsize += tmpsize;
++	if (tsize > isp->buf_info[MDNS_BUF].size) {
++		dev_err(isp->dev, "[ %s:%d ] buf size too small\n", __func__, __LINE__);
++		return -EFAULT;
++	}
++
++	//Lynne
++	stride = ((width + 31) / 32) * 16;
++	tmpsize = stride * height / 4;
++	tmpsize = ((tmpsize + 1023) / 1024 * 1024);
++	system_reg_write(MDNS_ADDR_LYN_ADDR(vinum), mdns_paddr + tsize);
++	system_reg_write(MDNS_ADDR_LYN_STRIDE(vinum), stride);
++	tsize += tmpsize;
++	if (tsize > isp->buf_info[MDNS_BUF].size) {
++		dev_err(isp->dev, "[ %s:%d ] buf size too small\n", __func__, __LINE__);
++		return -EFAULT;
++	}
++	return 0;
++}
++
++int isp_set_dualsensor_buf(struct isp_device *isp)
++{
++	struct v4l2_subdev_format *input_fmt = NULL;
++	uint32_t tsize = 0;
++	input_fmt = &g_isp_device[MAIN_ISP_INDEX]->formats[ISP_PAD_SINK];
++	tsize += input_fmt->format.width * input_fmt->format.height * 2 * 2;
++	input_fmt = &g_isp_device[SEC_ISP_INDEX]->formats[ISP_PAD_SINK];
++	tsize += input_fmt->format.width * input_fmt->format.height * 2 * 2;
++
++	dualsensor_size = tsize;
++	if(!dualsensor_vaddr && !dualsensor_paddr) {
++		dualsensor_vaddr = dma_alloc_noncoherent(isp->ispcam->dev, tsize, &dualsensor_paddr, DMA_BIDIRECTIONAL, GFP_KERNEL);
++		if(!dualsensor_vaddr || !dualsensor_paddr)
++			return -ENOMEM;
++	}
++
++	input_fmt = &g_isp_device[MAIN_ISP_INDEX]->formats[ISP_PAD_SINK];
++	system_reg_write(IPC_ADDR_DF_CH1_ADDR, dualsensor_paddr);
++	system_reg_write(IPC_ADDR_DF_CH3_ADDR, dualsensor_paddr + tsize / 2);
++
++	system_reg_write(IPC_ADDR_DF_CH1_SIZE, tsize / 2);
++	system_reg_write(IPC_ADDR_DF_CH3_SIZE, tsize / 2);
++
++	system_reg_write(IPC_ADDR_DUAL_M3_ORI_MODE  , 0x0);
++	system_reg_write(IPC_ADDR_M3_V0_URGENT_THRES, 0x60);
++	system_reg_write(IPC_ADDR_M3_V1_URGENT_THRES, 0x60);
++	system_reg_write(IPC_ADDR_M3_V0_V0_THRES    , (input_fmt->format.width * input_fmt->format.height * 9 / 8)/ 256); /* width * height * 1.5 * 0.75 */
++	system_reg_write(IPC_ADDR_M3_V0_V1_THRES    , 0x0);
++	system_reg_write(IPC_ADDR_M3_V1_V0_THRES    , 0x0);
++	input_fmt = &g_isp_device[MAIN_ISP_INDEX]->formats[ISP_PAD_SINK];
++	system_reg_write(IPC_ADDR_M3_V1_V1_THRES    , (input_fmt->format.width * input_fmt->format.height * 9 / 8)/ 256);
++
++	system_reg_write(0x101c, 0x3000); //IPC OVER FLOW
++	system_reg_write(0x1020, 0x3000);
++	system_reg_write(0x1024, 0x3000);
++	system_reg_write(0x1028, 0x3000);
++
++	return 0;
++	/*
++	bufinfo.paddr = 0;
++	bufinfo.size = vin->vi_max_width * vin->vi_max_height * 2 * 4;
++	vin = &core->vin[0];
++	bufinfo.size += vin->vi_max_width * vin->vi_max_height * 2 * 4;
++	*/
++}
++
++
++static int isp_subdev_streamon(struct v4l2_subdev *sd) {
++	struct isp_device *isp = v4l2_get_subdevdata(sd);
++	unsigned long flags = 0;
++	int ret = 0;
++
++	if(isp->enabled++ > 0) {
++		return 0;
++	}
++
++	ret = isp_set_mdns(isp);
++	if(ret)
++		goto set_mdns_err;
++
++	if(isp->sensor_info->wdr_en) {
++		ret = isp_set_wdr(isp);
++		if(ret)
++			goto set_wdr_err;
++	}
++
++#ifndef CONFIG_INGENIC_ISP_V2_SENSOR_NUM_ONE
++	ret = isp_set_dualsensor_buf(isp); /*dual sensor all cached mode*/
++	if(ret)
++		goto set_dualsensor_buf_err;
++#endif
++
++	if(isp_enabled == 0)
++	{
++		tisp_activate_all();
++		tisp_process_init();
++		ret = tisp_enable_tuning();
++		if(ret)
++			goto enable_tuning_err;
++	}
++
++	/*For event engine.*/
++	if(isp->sensor_id == 0) {
++		g_isp_device[0]->process_thread = kthread_run(isp_fw_process, isp, "isp_fw_process");
++		if(IS_ERR_OR_NULL(g_isp_device[0]->process_thread)){
++			dev_err(isp->dev, "%s[%d] kthread_run was failed!\n",__func__,__LINE__);
++			ret = -EINVAL;
++		}
++		if(ret)
++			goto process_thread_err;
++		/*enable irq*/
++		spin_lock_irqsave(&isp->lock, flags);
++		system_reg_write(RESP_ADDR_INT_COMMON_0_EN, 0xffffffff); //common intp
++		//system_reg_write(RESP_ADDR_INT_UNUSUAL_0_EN, 0xffffffff); //unusual intp
++		//system_reg_write(RESP_ADDR_INT_BACKUP_0_EN, 1 << 27); //back0 intp
++		spin_unlock_irqrestore(&isp->lock, flags);
++	} else if (isp->sensor_id == 1) {
++		g_isp_device[1]->process_thread = kthread_run(isp_fw_process1, isp, "isp_fw_process1");
++		if(IS_ERR_OR_NULL(g_isp_device[1]->process_thread)){
++			dev_err(isp->dev, "%s[%d] kthread_run was failed!\n",__func__,__LINE__);
++			ret = -EINVAL;
++		}
++		if(ret)
++			goto process_thread_err;
++		/*enable irq*/
++		spin_lock_irqsave(&isp->lock, flags);
++		system_reg_write(RESP_ADDR_INT_COMMON_1_EN, 0xffffffff); //common intp
++		spin_unlock_irqrestore(&isp->lock, flags);
++	}
++
++	tisp_ipc_triger();
++	isp_enabled++;
++
++	return 0;
++
++
++process_thread_err:
++	if(isp_enabled == 1) {
++		tisp_disable_tuning();
++		tisp_process_deinit(isp->sensor_id);
++		tisp_slake_all();
++	}
++enable_tuning_err:
++#ifndef CONFIG_INGENIC_ISP_V2_SENSOR_NUM_ONE
++	if(dualsensor_vaddr && dualsensor_paddr) {
++		dma_free_noncoherent(g_isp_device[MAIN_ISP_INDEX]->ispcam->dev, dualsensor_size, dualsensor_vaddr, dualsensor_paddr, DMA_BIDIRECTIONAL);
++	}
++#endif
++set_dualsensor_buf_err:
++	dualsensor_vaddr = 0;
++	dualsensor_paddr = 0;
++	if(isp->sensor_info->wdr_en && wdr_vaddr && wdr_paddr){
++		dma_free_noncoherent(isp->ispcam->dev, wdr_size, wdr_vaddr, wdr_paddr, DMA_BIDIRECTIONAL);
++	}
++set_wdr_err:
++	wdr_vaddr = 0;
++	wdr_paddr = 0;
++	if(isp->buf_info[MDNS_BUF].vaddr && isp->buf_info[MDNS_BUF].paddr)
++		dma_free_noncoherent(isp->ispcam->dev, isp->buf_info[MDNS_BUF].size, isp->buf_info[MDNS_BUF].vaddr, isp->buf_info[MDNS_BUF].paddr, DMA_BIDIRECTIONAL);
++set_mdns_err:
++	isp->buf_info[MDNS_BUF].vaddr = 0;
++	isp->buf_info[MDNS_BUF].paddr = 0;
++	isp->enabled--;
++	return ret;
++}
++
++unsigned int sensor1_deinit_flag;
++static int isp_subdev_streamoff(struct v4l2_subdev *sd) {
++	struct isp_device *isp = v4l2_get_subdevdata(sd);
++	unsigned long flags = 0;
++	unsigned int top_val = 0;
++	int timeout = 0xffffff;
++
++	if(--isp->enabled > 0) {
++		return 0;
++	}
++
++	if(isp->sensor_info->wdr_en && wdr_vaddr && wdr_paddr){
++		dma_free_noncoherent(isp->ispcam->dev, wdr_size, wdr_vaddr, wdr_paddr, DMA_BIDIRECTIONAL);
++		wdr_vaddr = 0;
++		wdr_paddr = 0;
++	}
++
++	if(isp->sensor_id == 0) {
++		/*disable irq*/
++		spin_lock_irqsave(&isp->lock, flags);
++		system_reg_write(RESP_ADDR_INT_COMMON_0_EN, 0x0); //common intp
++		spin_unlock_irqrestore(&isp->lock, flags);
++		kthread_stop(g_isp_device[0]->process_thread);
++		tisp_deinit(0);
++	} else if(isp->sensor_id == 1) {
++		/*disable irq*/
++		spin_lock_irqsave(&isp->lock, flags);
++		system_reg_write(RESP_ADDR_INT_COMMON_1_EN, 0x0); //common intp
++		spin_unlock_irqrestore(&isp->lock, flags);
++		kthread_stop(g_isp_device[1]->process_thread);
++		tisp_deinit(1);
++	}
++
++	if(--isp_enabled == 0) {
++		tisp_disable_tuning();
++		tisp_slake_all();
++#ifndef CONFIG_INGENIC_ISP_V2_SENSOR_NUM_ONE
++		if(dualsensor_vaddr && dualsensor_paddr) {
++			dma_free_noncoherent(g_isp_device[MAIN_ISP_INDEX]->ispcam->dev, dualsensor_size, dualsensor_vaddr, dualsensor_paddr, DMA_BIDIRECTIONAL);
++			dualsensor_vaddr = 0;
++			dualsensor_paddr = 0;
++		}
++#endif
++	}
++	tisp_process_deinit(isp->sensor_id);
++
++	if(isp->buf_info[MDNS_BUF].vaddr && isp->buf_info[MDNS_BUF].paddr) {
++		dma_free_noncoherent(isp->ispcam->dev, isp->buf_info[MDNS_BUF].size, isp->buf_info[MDNS_BUF].vaddr, isp->buf_info[MDNS_BUF].paddr, DMA_BIDIRECTIONAL);
++		isp->buf_info[MDNS_BUF].vaddr = 0;
++		isp->buf_info[MDNS_BUF].paddr = 0;
++	}
++
++	system_reg_write(SEC_MSCA_ADDR_FORCE, 1);
++
++	if(isp_enabled == 0) {
++		top_val = system_reg_read(TOP_ADDR_STOP_CON);
++		system_reg_write(TOP_ADDR_STOP_CON, top_val | 0x1);
++		while(timeout--){
++			top_val = system_reg_read(TOP_ADDR_STOP_STATE);
++			if(top_val & 0x01)
++				break;
++		}
++
++		if(timeout == 0) {
++			dev_err(isp->dev, "isp wait stop timeout\n");
++			return -ETIMEDOUT;
++		}
++
++		top_val = system_reg_read(TOP_ADDR_TOP_RST);
++		system_reg_write(TOP_ADDR_TOP_RST, top_val | ALL_RST);
++		system_reg_write(TOP_ADDR_TOP_RST, top_val & (~ALL_RST));
++	}
++
++	return 0;
++}
++
++
++
++static int isp_subdev_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	if(enable)
++		return isp_subdev_streamon(sd);
++	else
++		return isp_subdev_streamoff(sd);
++}
++
++
++static const struct v4l2_subdev_video_ops isp_subdev_video_ops = {
++        .s_stream = isp_subdev_s_stream,
++};
++
++
++static const struct v4l2_subdev_ops isp_subdev_ops = {
++        .core = &isp_subdev_core_ops,
++        .pad = &isp_subdev_pad_ops,
++        .video = &isp_subdev_video_ops,
++};
++static ssize_t
++dump_isp(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	//struct isp_device *isp = dev_get_drvdata(dev);
++	char *p = buf;
++
++	/*
++	p += sprintf(p, "TOP_CTRL_ADDR_VERSION            :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_VERSION            ));
++	p += sprintf(p, "TOP_CTRL_ADDR_FM_SIZE            :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_FM_SIZE            ));
++	p += sprintf(p, "TOP_CTRL_ADDR_BAYER_TYPE         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_BAYER_TYPE         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_BYPASS_CON         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_BYPASS_CON         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TOP_CON            :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TOP_CON            ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TOP_STATE          :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TOP_STATE          ));
++	p += sprintf(p, "TOP_CTRL_ADDR_LINE_SPACE         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_LINE_SPACE         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_REG_CON            :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_REG_CON            ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_RC_TRIG        :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_RC_TRIG        ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_RC_CON         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_RC_CON         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_RC_ADDR        :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_RC_ADDR        ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_RC_STATE       :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_RC_STATE       ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_RC_APB_WR_DATA :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_RC_APB_WR_DATA ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_RC_APB_WR_ADDR :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_RC_APB_WR_ADDR ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_RD_CON         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_RD_CON         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_WR_CON         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_WR_CON         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_FR_WR_CON      :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_FR_WR_CON      ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_STA_WR_CON     :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_STA_WR_CON     ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_RD_DEBUG       :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_RD_DEBUG       ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_WR_DEBUG       :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_WR_DEBUG       ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_FR_WR_DEBUG    :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_FR_WR_DEBUG    ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_STA_WR_DEBUG   :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_STA_WR_DEBUG   ));
++	p += sprintf(p, "TOP_CTRL_ADDR_INT_EN             :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_INT_EN             ));
++	p += sprintf(p, "TOP_CTRL_ADDR_INT_REG            :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_INT_REG            ));
++	p += sprintf(p, "TOP_CTRL_ADDR_INT_CLR            :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_INT_CLR            ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TP_FREERUN         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TP_FREERUN         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TP_CON             :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TP_CON             ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TP_SIZE            :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TP_SIZE            ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TP_FONT            :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TP_FONT            ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TP_FLICK           :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TP_FLICK           ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TP_CS_TYPE         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TP_CS_TYPE         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TP_CS_FCLO         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TP_CS_FCLO         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TP_CS_BCLO         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TP_CS_BCLO         ));
++*/
++	return p - buf;
++}
++
++
++static DEVICE_ATTR(dump_isp, S_IRUGO|S_IWUSR, dump_isp, NULL);
++
++static struct attribute *isp_debug_attrs[] = {
++        &dev_attr_dump_isp.attr,
++	NULL,
++};
++
++static struct attribute_group isp_debug_attr_group = {
++        .name   = "debug",
++        .attrs  = isp_debug_attrs,
++};
++
++
++static int isp_comp_bind(struct device *comp, struct device *master,
++                              void *master_data)
++{
++	struct isp_device *isp = dev_get_drvdata(comp);
++	struct ispcam_device *ispcam = (struct ispcam_device *)master_data;
++	struct v4l2_device *v4l2_dev = &ispcam->v4l2_dev;
++	struct v4l2_subdev *sd = &isp->sd;
++	int ret = 0;
++
++	//dev_info(comp, "----dev_name(comp): %s----%s, %d \n", dev_name(comp), __func__, __LINE__);
++
++	/* link subdev to master.*/
++	isp->ispcam = (void *)ispcam;
++	ispcam->isp = isp;
++
++	/*1. register supported subdev ctrls.*/
++
++
++	/*2. init v4l2_subdev*/
++
++	v4l2_subdev_init(sd, &isp_subdev_ops);
++
++	sd->owner = THIS_MODULE;
++	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++	strscpy(sd->name, dev_name(comp), sizeof(sd->name));
++	v4l2_set_subdevdata(sd, isp);
++
++
++	/* init isp pads. */
++	isp->pads = kzalloc(sizeof(struct media_pad) * ISP_NUM_PADS, GFP_KERNEL);
++	if(!isp->pads) {
++		ret = -ENOMEM;
++		goto err_alloc_pads;
++	}
++	isp->pads[0].index = ISP_PAD_SINK;
++	isp->pads[0].flags = MEDIA_PAD_FL_SINK;
++	isp->pads[1].index = ISP_PAD_SOURCE;
++	isp->pads[1].flags = MEDIA_PAD_FL_SOURCE;
++
++	ret = media_entity_pads_init(&sd->entity, ISP_NUM_PADS, isp->pads);
++
++	/*3. register v4l2_subdev*/
++	sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_COMPOSER;
++	ret = v4l2_device_register_subdev(v4l2_dev, sd);
++	if(ret < 0) {
++		dev_err(comp, "Failed to register v4l2_subdev for isp\n");
++		goto err_subdev_register;
++	}
++
++	return 0;
++err_subdev_register:
++err_alloc_pads:
++	return ret;
++}
++
++
++static void isp_comp_unbind(struct device *comp, struct device *master,
++                                 void *master_data)
++{
++        struct isp_device *isp = dev_get_drvdata(comp);
++
++	dev_info(comp, "---TODO:--%p---%s, %d \n", isp,  __func__, __LINE__);
++
++}
++
++static const struct component_ops isp_comp_ops = {
++        .bind = isp_comp_bind,
++        .unbind = isp_comp_unbind,
++};
++
++static irqreturn_t isp_irq_handler(int irq, void *data)
++{
++	struct isp_device *isp = (struct isp_device *)data;
++	bool handled = 0;
++	unsigned int status, status_sec;
++	int ret = 0;
++	int i = 0;
++
++	spin_lock(&isp->lock);
++	/*read irq_flags*/
++	status = isp_reg_readl(isp, RESP_ADDR_INT_COMMON_0_INFO);
++	status_sec = isp_reg_readl(isp, RESP_ADDR_INT_COMMON_1_INFO);
++//	printk("0x%08x 0x%08x\n", status,status_sec);
++
++	/*1. process irq by subdev.*/
++#if 1
++	if(status) {
++		ret = v4l2_subdev_call(&g_isp_device[MAIN_ISP_INDEX]->ispcam->mscaler->sd, core, interrupt_service_routine, status, &handled);
++		if(ret < 0) {
++
++		}
++	}
++
++	if(status_sec) {
++		ret = v4l2_subdev_call(&g_isp_device[SEC_ISP_INDEX]->ispcam->mscaler->sd, core, interrupt_service_routine, status_sec, &handled);
++		if(ret < 0) {
++
++		}
++	}
++#endif
++#if 1
++	if (status & CH0_FRM_DONE_BF_INT)
++		tisp_hardware_reg_refresh(0);
++
++	if (status_sec & CH0_FRM_DONE_BF_INT)
++		tisp_hardware_reg_refresh(1);
++#endif
++
++	/*2. isp-core irq callbacks */
++	for(i = 0; i < 32; i++) {
++		if(status & (1 << i) && g_isp_device[MAIN_ISP_INDEX]->irq_func_cb[i]) {
++			ret = g_isp_device[MAIN_ISP_INDEX]->irq_func_cb[i]();
++			if(ret < 0) {
++
++			}
++		}
++		if(status_sec & (1 << i) && g_isp_device[SEC_ISP_INDEX]->irq_func_cb[i]) {
++			ret = g_isp_device[SEC_ISP_INDEX]->irq_func_cb[i]();
++			if(ret < 0) {
++
++			}
++		}
++	}
++
++	/*clear irq_flags*/
++	isp_reg_writel(isp, RESP_ADDR_INT_COMMON_0_CLR, status);
++	isp_reg_writel(isp, RESP_ADDR_INT_COMMON_1_CLR, status_sec);
++	spin_unlock(&isp->lock);
++	return IRQ_HANDLED;
++}
++
++static int ingenic_isp_probe(struct platform_device *pdev)
++{
++
++	struct isp_device *isp = NULL;
++	int ret = 0;
++
++	isp = kzalloc(sizeof(struct isp_device), GFP_KERNEL);
++	if(!isp) {
++		pr_err("Failed to alloc isp dev [%s]\n", pdev->name);
++		return -ENOMEM;
++	}
++
++	isp->dev = &pdev->dev;
++	platform_set_drvdata(pdev, isp);
++
++
++	ingenic_isp_parse_dt(isp);
++
++#ifdef CONFIG_INGENIC_ISP_V2_SENSOR_NUM_ONE
++	isp->multi_mode.sensor_num = IMPISP_TOTAL_ONE;
++#else
++	isp->multi_mode.sensor_num = IMPISP_TOTAL_TWO;
++#endif
++	isp->multi_mode.dual_mode = IMPISP_DUALSENSOR_DUAL_ALLCACHED_MODE;
++	isp->multi_mode.joint_mode = IMPISP_NOT_JOINT;
++
++	ret = component_add(isp->dev, &isp_comp_ops);
++	if(ret < 0) {
++		dev_err(isp->dev, "Failed to add component isp!\n");
++	}
++
++	g_isp_device[isp->index] = isp;
++
++	isp->iobase = (unsigned int *)0xb3300000;
++	isp->irq = 31+8;
++
++	spin_lock_init(&isp->lock);
++
++	if(!flag){
++	//	ret = devm_request_irq(isp->dev, isp->irq, isp_irq_handler, 0,
++	//			dev_name(isp->dev), isp);
++
++		ret = request_irq(isp->irq, isp_irq_handler, 0,
++				dev_name(isp->dev), isp);
++
++		if(ret) {
++			dev_err(isp->dev, "request irq failed!\n");
++			goto err_request_irq;
++		}
++
++
++		isp->div_clk = of_clk_get(isp->dev->of_node, 0);
++		if(!isp->div_clk) {
++			dev_err(isp->dev, "failed to get isp div_clk\n");
++			goto err_div_clk;
++		}
++
++		clk_set_rate(isp->div_clk, isp_clk);
++
++		clk_prepare_enable(isp->div_clk);
++
++		isp->gate_clk = of_clk_get(isp->dev->of_node, 1);
++		if(!isp->gate_clk) {
++			dev_err(isp->dev, "failed to get isp gate_clk\n");
++			goto err_gate_clk;
++		}
++
++		clk_prepare_enable(isp->gate_clk);
++
++
++		ret = sysfs_create_group(&isp->dev->kobj, &isp_debug_attr_group);
++		if (ret) {
++			dev_err(isp->dev, "device create sysfs group failed\n");
++
++			ret = -EINVAL;
++			goto err_sys_group;
++		}
++		flag = 1;
++	}
++
++	return 0;
++err_sys_group:
++err_gate_clk:
++err_div_clk:
++err_request_irq:
++	return ret;
++}
++
++
++
++static int ingenic_isp_remove(struct platform_device *pdev)
++{
++	struct isp_device *isp = dev_get_drvdata(&pdev->dev);
++
++	clk_disable_unprepare(isp->power_clk);
++	clk_disable_unprepare(isp->gate_clk);
++	clk_disable_unprepare(isp->div_clk);
++	return 0;
++}
++
++
++
++static const struct of_device_id ingenic_isp_dt_match[] = {
++        { .compatible = "ingenic,x2500-isp" },
++        { }
++};
++
++MODULE_DEVICE_TABLE(of, ingenic_isp_dt_match);
++
++static int __maybe_unused ingenic_isp_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	struct isp_device *isp = dev_get_drvdata(&pdev->dev);
++
++	if(isp->enabled){
++		dev_err(isp->dev, "faild to suspend, isp is streaming on\n");
++		return -EBUSY;
++	}
++
++	isp_cpm_stop(isp);
++	clk_disable_unprepare(isp->power_clk);
++	clk_disable_unprepare(isp->gate_clk);
++	clk_disable_unprepare(isp->div_clk);
++
++        return 0;
++}
++
++static int __maybe_unused ingenic_isp_resume(struct platform_device *pdev)
++{
++	struct isp_device *isp = dev_get_drvdata(&pdev->dev);
++
++	clk_prepare_enable(isp->div_clk);
++	clk_prepare_enable(isp->gate_clk);
++	clk_prepare_enable(isp->power_clk);
++	isp_cpm_reset(isp);
++
++        return 0;
++}
++
++static struct platform_driver ingenic_isp_driver = {
++        .probe = ingenic_isp_probe,
++        .remove = ingenic_isp_remove,
++	.suspend = ingenic_isp_suspend,
++	.resume = ingenic_isp_resume,
++        .driver = {
++                .name = "ingenic-isp",
++                .of_match_table = ingenic_isp_dt_match,
++        },
++};
++
++module_platform_driver(ingenic_isp_driver);
++
++MODULE_ALIAS("platform:ingenic-isp");
++MODULE_DESCRIPTION("ingenic isp subsystem");
++MODULE_AUTHOR("qipengzhen <aric.pzqi@ingenic.com>");
++MODULE_LICENSE("GPL v2");
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/mscaler-bdev.c b/module_drivers/drivers/media/platform/ingenic-isp-v2/mscaler-bdev.c
+new file mode 100644
+index 000000000..3bd1bb032
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/mscaler-bdev.c
+@@ -0,0 +1,255 @@
++#include <linux/kthread.h>
++#include <linux/list.h>
++#include <linux/wait.h>
++#include <linux/time.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++
++#include <media/videobuf2-v4l2.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++
++#include "helix_drv.h"
++#include "jpge.h"
++
++#include "isp-drv.h"
++
++
++int ms_bdev_qbuf(struct mscaler_backend_device *ms_bdev, struct isp_video_buffer *isp_buffer)
++{
++
++	unsigned long flags;
++
++//	printk("--------%s, %d\n", __func__, __LINE__);
++
++	spin_lock_irqsave(&ms_bdev->lock, flags);
++
++	list_add_tail(&isp_buffer->list_entry, &ms_bdev->processing_list);
++
++	spin_unlock_irqrestore(&ms_bdev->lock, flags);
++
++	/* wakeup possible process thread. */
++	wake_up(&ms_bdev->wq);
++}
++
++
++static int ms_bdev_kthread(void *data)
++{
++
++	struct mscaler_backend_device *ms_bdev = data;
++	int ret = 0;
++	unsigned long flags;
++
++	struct ingenic_venc_ctx *ctx = ms_bdev->ctx;
++	struct jpge_ctx *jpge_ctx = &ctx->jpge_ctx;
++
++	struct video_frame_buffer src_frame;
++
++	while(1) {
++
++		if(kthread_should_stop())
++			break;
++
++
++		ret = wait_event_interruptible(ms_bdev->wq, !list_empty(&ms_bdev->processing_list) || ms_bdev->activated == 0);
++		if(ret || ms_bdev->activated ==  0) {
++			/*wakeup by interrupt?*/
++			/* STOP*/
++			continue;
++		}
++
++		spin_lock_irqsave(&ms_bdev->lock, flags);
++		struct isp_video_buffer *isp_buffer = list_first_entry_or_null(&ms_bdev->processing_list, struct isp_video_buffer, list_entry);
++
++		if(!isp_buffer) {
++			dev_err(ms_bdev->dev, "No Buffer available!\n");
++		} else {
++
++			list_del(&isp_buffer->list_entry);
++		}
++		spin_unlock_irqrestore(&ms_bdev->lock, flags);
++
++		struct vb2_v4l2_buffer *vb2 = &isp_buffer->vb2;
++
++
++		mutex_lock(&ctx->dev->dev_mutex);
++		/* Processing ....*/
++
++		memset(&src_frame, 0, sizeof(struct video_frame_buffer));
++
++		src_frame.num_planes = 2;
++		src_frame.fb_addr[0].pa = ingenic_vb2_dma_contig_plane_dma_addr(&vb2->vb2_buf, 0);
++		src_frame.fb_addr[1].pa = src_frame.fb_addr[0].pa + isp_buffer->uv_offset;
++
++		src_frame.fb_addr[0].va = vb2_plane_vaddr(&vb2->vb2_buf, 0);
++		src_frame.fb_addr[1].va = src_frame.fb_addr[0].va + isp_buffer->uv_offset;
++
++		src_frame.fb_addr[0].size = isp_buffer->uv_offset;
++		src_frame.fb_addr[1].size = vb2_get_plane_payload(&vb2->vb2_buf, 0) - src_frame.fb_addr[0].size;
++
++		dma_sync_single_for_device(ms_bdev->dev,(unsigned long)jpge_ctx->bs->pa, jpge_ctx->bs->size, DMA_FROM_DEVICE);
++
++		jpeg_encoder_encode(jpge_ctx, &src_frame, jpge_ctx->bs);
++
++		memcpy(vb2_plane_vaddr(&vb2->vb2_buf, 0), jpge_ctx->bs->va, jpge_ctx->bslen);
++
++		vb2_set_plane_payload(&vb2->vb2_buf, 0, jpge_ctx->bslen);
++
++#if 0
++		wait_process_buffer();
++
++		done_process_buffer();
++#endif
++		mutex_unlock(&ctx->dev->dev_mutex);
++//		printk("----done_processing_buffer: %d\n", isp_buffer->vb2.vb2_buf.index);
++		vb2_buffer_done(&isp_buffer->vb2.vb2_buf, VB2_BUF_STATE_DONE);
++
++	}
++
++	return 0;
++}
++
++
++static int venc_create_ctx(struct mscaler_backend_device *ms_bdev)
++{
++
++	struct ingenic_venc_ctx *ctx = kzalloc(sizeof(struct ingenic_venc_ctx), GFP_KERNEL);
++	struct h264e_ctx * h264e_ctx = NULL;
++	struct jpge_ctx * jpge_ctx = NULL;
++	struct ingenic_vcodec_mem *bs = NULL;
++	int ret = 0;
++
++	if(ctx == NULL) {
++		return -ENOMEM;
++	}
++
++	ctx->dev = ingenic_venc_dev_get();
++
++	mutex_lock(&ctx->dev->dev_mutex);
++
++#if 0
++	if (!ctx->dev->id_counter) {
++		vpu_on(ctx->dev);
++	}
++#endif
++
++	ctx->id = ctx->dev->id_counter++;
++	init_waitqueue_head(&ctx->queue);
++
++	mutex_unlock(&ctx->dev->dev_mutex);
++
++	ms_bdev->ctx = ctx;
++
++	/*switch FMT: JPEG H264.*/
++	jpge_ctx = &ctx->jpge_ctx;
++	ctx->codec_id = CODEC_ID_JPGE;
++
++	ret = jpeg_encoder_init(jpge_ctx);
++	jpeg_encoder_set_priv(jpge_ctx, ctx);
++
++
++	jpeg_encoder_set_fmt(jpge_ctx, ms_bdev->width, ms_bdev->height, HELIX_NV12_MODE);
++
++	ret = jpeg_encoder_alloc_workbuf(jpge_ctx);
++	if(ret < 0) {
++		goto err_alloc_workbuf;
++	}
++
++	/* alloc bs output buffer. */
++	bs = kzalloc(sizeof(struct ingenic_vcodec_mem), GFP_KERNEL);
++	if(!bs) {
++		goto err_bs_alloc;
++	}
++	bs->size = ms_bdev->width * ms_bdev->height;
++
++	bs->va = dma_alloc_noncoherent(ms_bdev->dev, bs->size, &bs->pa, GFP_KERNEL);
++	if(!bs->va) {
++		goto err_bs_va_alloc;
++	}
++
++	jpge_ctx->bs = bs;
++
++
++	return 0;
++err_bs_va_alloc:
++	kfree(bs);
++err_bs_alloc:
++	jpeg_encoder_free_workbuf(jpge_ctx);
++err_alloc_workbuf:
++	jpeg_encoder_deinit(jpge_ctx);
++
++	kfree(ctx);
++	ms_bdev->ctx = NULL;
++	return ret;
++}
++
++static int venc_free_ctx(struct mscaler_backend_device *ms_bdev)
++{
++	struct ingenic_venc_ctx *ctx = ms_bdev->ctx;
++	struct jpge_ctx *jpge_ctx = &ctx->jpge_ctx;
++	struct ingenic_vcodec_mem *bs = jpge_ctx->bs;
++
++
++
++	mutex_lock(&ctx->dev->dev_mutex);
++#if 0
++	if (!--ctx->dev->id_counter) {
++		vpu_off(ctx->dev);
++	}
++#endif
++	mutex_unlock(&ctx->dev->dev_mutex);
++
++	dma_free_noncoherent(ms_bdev->dev, bs->size, bs->va, bs->pa);
++	kfree(bs);
++
++	jpeg_encoder_free_workbuf(jpge_ctx);
++	jpeg_encoder_deinit(jpge_ctx);
++
++	kfree(ctx);
++}
++
++
++int ms_bdev_init(struct mscaler_backend_device *ms_bdev)
++{
++	int ret = 0;
++	printk("--------%s, %d\n", __func__, __LINE__);
++
++	ret = venc_create_ctx(ms_bdev);
++	if(ret < 0) {
++		return -EINVAL;
++	}
++
++	spin_lock_init(&ms_bdev->lock);
++	INIT_LIST_HEAD(&ms_bdev->processing_list);
++	init_waitqueue_head(&ms_bdev->wq);
++
++	ms_bdev->process_thread = kthread_run(ms_bdev_kthread, ms_bdev, "ms-bdev-ch%d", ms_bdev->ch);
++	if(IS_ERR_OR_NULL(ms_bdev->process_thread)) {
++
++		dev_err(ms_bdev->dev, "Failed to run kthread for ms-bdev-ch%d", ms_bdev->ch);
++
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++int ms_bdev_deinit(struct mscaler_backend_device *ms_bdev)
++{
++
++	printk("--------%s, %d\n", __func__, __LINE__);
++
++	if(!ms_bdev->activated) {
++		return 0;
++	}
++
++
++	kthread_stop(ms_bdev->process_thread);
++
++	ms_bdev->process_thread = NULL;
++
++	venc_free_ctx(ms_bdev);
++
++	memset(ms_bdev, 0, sizeof(struct mscaler_backend_device));
++
++	return 0;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/mscaler-regs.h b/module_drivers/drivers/media/platform/ingenic-isp-v2/mscaler-regs.h
+new file mode 100644
+index 000000000..dfbbb43bf
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/mscaler-regs.h
+@@ -0,0 +1,80 @@
++#ifndef	__INGENIC_ISP_MSCALER_REGS_H__
++#define __INGENIC_ISP_MSCALER_REGS_H__
++
++#define MSCA_BASE	0
++
++//============================================================
++// Mscaler
++//============================================================
++#define    MSCA_CH_EN                        (MSCA_BASE+0x008)
++#define    MSCA_INT_STA                      (MSCA_BASE+0x00C)
++#define    MSCA_INT_MSK                      (MSCA_BASE+0x010)
++#define    MSCA_MASK_EN                      (MSCA_BASE+0x014)
++#define    MSCA_DMAOUT_ARB                   (MSCA_BASE+0x018)
++#define    MSCA_CLK_GATE_EN                  (MSCA_BASE+0x01C)
++#define    MSCA_CLK_DIS                      (MSCA_BASE+0x020)
++#define    MSCA_SRC_IN                       (MSCA_BASE+0x030)
++#define    MSCA_SRC_SIZE                     (MSCA_BASE+0x034)
++#define    MSCA_GLO_RSZ_COEF_WR              (MSCA_BASE+0x040)
++#define    MSCA_SYS_PRO_CLK_EN               (MSCA_BASE+0x050)
++#define    MSCA_DS0_CLK_NUM                  (MSCA_BASE+0x054)
++#define    MSCA_DS1_CLK_NUM                  (MSCA_BASE+0x058)
++#define    MSCA_DS2_CLK_NUM                  (MSCA_BASE+0x05C)
++
++#define CHx_RSZ_OSIZE(n)				(MSCA_BASE+(0x0100*(n))+0x100)
++#define CHx_RSZ_STEP(n)					(MSCA_BASE+(0x0100*(n))+0x104)
++
++#define CHx_CROP_OPOS(n)				(MSCA_BASE+(0x0100*(n))+0x128)
++#define CHx_CROP_OSIZE(n)				(MSCA_BASE+(0x0100*(n))+0x12c)
++#define CHx_FRA_CTRL_LOOP(n)				(MSCA_BASE+(0x0100*(n))+0x130)
++#define CHx_FRA_CTRL_MASK(n)				(MSCA_BASE+(0x0100*(n))+0x134)
++#define CHx_MSx_POS(n,m)				(MSCA_BASE+(0x0100*(n))+0x138+(0x0c*(m)))
++#define CHx_MSx_SIZE(n,m)				(MSCA_BASE+(0x0100*(n))+0x13c+(0x0c*(m)))
++#define CHx_MSx_VALUE(n,m)				(MSCA_BASE+(0x0100*(n))+0x140+(0x0c*(m)))
++#define CHx_MS0_POS(n)					(MSCA_BASE+(0x0100*(n))+0x138)
++#define CHx_MS0_SIZE(n)					(MSCA_BASE+(0x0100*(n))+0x13c)
++#define CHx_MS0_VALUE(n)				(MSCA_BASE+(0x0100*(n))+0x140)
++#define CHx_MS1_POS(n)					(MSCA_BASE+(0x0100*(n))+0x144)
++#define CHx_MS1_SIZE(n)					(MSCA_BASE+(0x0100*(n))+0x148)
++#define CHx_MS1_VALUE(n)				(MSCA_BASE+(0x0100*(n))+0x14c)
++#define CHx_MS2_POS(n)					(MSCA_BASE+(0x0100*(n))+0x150)
++#define CHx_MS2_SIZE(n)					(MSCA_BASE+(0x0100*(n))+0x154)
++#define CHx_MS2_VALUE(n)				(MSCA_BASE+(0x0100*(n))+0x158)
++#define CHx_MS3_POS(n)					(MSCA_BASE+(0x0100*(n))+0x15c)
++#define CHx_MS3_SIZE(n)					(MSCA_BASE+(0x0100*(n))+0x160)
++#define CHx_MS3_VALUE(n)				(MSCA_BASE+(0x0100*(n))+0x164)
++#define CHx_OUT_FMT(n)					(MSCA_BASE+(0x0100*(n))+0x168)
++#define CHx_DMAOUT_Y_ADDR(n)				(MSCA_BASE+(0x0100*(n))+0x16c)
++#define CHx_Y_ADDR_FIFO_STA(n)				(MSCA_BASE+(0x0100*(n))+0x170)
++#define CHx_DMAOUT_Y_LAST_ADDR(n)			(MSCA_BASE+(0x0100*(n))+0x174)
++#define CHx_DMAOUT_Y_LAST_STATS_NUM(n)			(MSCA_BASE+(0x0100*(n))+0x178)
++#define CHx_Y_LAST_ADDR_FIFO_STA(n)			(MSCA_BASE+(0x0100*(n))+0x17c)
++#define CHx_DMAOUT_Y_STRI(n)				(MSCA_BASE+(0x0100*(n))+0x180)
++#define CHx_DMAOUT_UV_ADDR(n)				(MSCA_BASE+(0x0100*(n))+0x184)
++#define CHx_UV_ADDR_FIFO_STA(n)				(MSCA_BASE+(0x0100*(n))+0x188)
++#define CHx_DMAOUT_UV_LAST_ADDR(n)			(MSCA_BASE+(0x0100*(n))+0x18c)
++#define CHx_DMAOUT_UV_LAST_STATS_NUM(n)			(MSCA_BASE+(0x0100*(n))+0x190)
++#define CHx_UV_LAST_ADDR_FIFO_STA(n)			(MSCA_BASE+(0x0100*(n))+0x194)
++#define CHx_DMAOUT_UV_STRI(n)				(MSCA_BASE+(0x0100*(n))+0x198)
++#define CHx_DMAOUT_Y_ADDR_CLR(n)			(MSCA_BASE+(0x0100*(n))+0x19c)
++#define CHx_DMAOUT_UV_ADDR_CLR(n)			(MSCA_BASE+(0x0100*(n))+0x1a0)
++#define CHx_DMAOUT_Y_LAST_ADDR_CLR(n)			(MSCA_BASE+(0x0100*(n))+0x1a4)
++#define CHx_DMAOUT_UV_LAST_ADDR_CLR(n)			(MSCA_BASE+(0x0100*(n))+0x1a8)
++#define CHx_DMAOUT_Y_ADDR_SEL(n)			(MSCA_BASE+(0x0100*(n))+0x1ac)
++#define CHx_DMAOUT_UV_ADDR_SEL(n)			(MSCA_BASE+(0x0100*(n))+0x1b0)
++
++#define MSCA_CH0_FRM_DONE_INT	(0)
++#define MSCA_CH1_FRM_DONE_INT	(1)
++#define MSCA_CH2_FRM_DONE_INT	(2)
++#define MSCA_CH0_CROP_ERR_INT	(3)
++#define MSCA_CH1_CROP_ERR_INT	(4)
++#define MSCA_CH2_CROP_ERR_INT	(5)
++
++#define CHx_OUT_FMT_NV12 0x0
++#define CHx_OUT_FMT_NV21 0x1
++#define CHx_OUT_FMT_ARGB8888 0x2
++#define CHx_OUT_FMT_RGB565 0x3
++#define CHx_OUT_FMT_Y_OUT_ONLY (1 << 6)
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/mscaler.c b/module_drivers/drivers/media/platform/ingenic-isp-v2/mscaler.c
+new file mode 100644
+index 000000000..d72c464d6
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/mscaler.c
+@@ -0,0 +1,1411 @@
++#include <linux/clk.h>
++#include <linux/media-bus-format.h>
++#include <linux/media.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_graph.h>
++#include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
++#include <linux/pm_domain.h>
++#include <linux/slab.h>
++#include <linux/videodev2.h>
++#include <linux/component.h>
++#include <linux/time.h>
++#include <linux/delay.h>
++
++#include <media/media-device.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-event.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++#include <media/videobuf2-v4l2.h>
++#include <media/ingenic_video_nr.h>
++
++#include "isp-drv.h"
++#include "mscaler-regs.h"
++
++static void dump_mscaler_regs(struct mscaler_device *mscaler);
++
++static struct isp_video_format mscaler_output_formats[] = {
++	{
++		.name     = "NV12, Y/CbCr 4:2:0",
++		.fourcc   = V4L2_PIX_FMT_NV12,
++		.depth    = {8, 4},
++		.num_planes = 2,
++		.mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "NV21, Y/CrCb 4:2:0",
++		.fourcc   = V4L2_PIX_FMT_NV21,
++		.depth    = {8, 4},
++		.num_planes = 2,
++		.mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "GREY, Greyscale",
++		.fourcc   = V4L2_PIX_FMT_GREY,
++		.depth    = {8},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_Y8_1X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++#ifdef CONFIG_MSCA_BDEV
++	{
++		.name     = "JFIF JPEG",
++		.fourcc   = V4L2_PIX_FMT_JPEG,
++		.depth    = {8},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_JPEG_1X8,
++		.colorspace = V4L2_COLORSPACE_JPEG,
++	},
++	{
++		.name     = "H264 with start codes",
++		.fourcc   = V4L2_PIX_FMT_H264,
++		.depth    = {8},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_JPEG_1X8,
++		.colorspace = V4L2_COLORSPACE_JPEG,
++	},
++#endif
++	/*
++	{
++		.name     = "RGB565, RGB-5-6-5",
++		.fourcc   = V4L2_PIX_FMT_RGB565,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_RGB565_1X16,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "ARGB32, ARGB-8-8-8-8",
++		.fourcc   = V4L2_PIX_FMT_ARGB32,
++		.depth    = {32},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_ARGB8888_1X32,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	*/
++};
++
++struct ingenic_isp_framesizes {
++	u32 fourcc;
++	struct v4l2_frmsize_discrete discrete;
++};
++
++static const struct ingenic_isp_framesizes ingenic_isp_framesizes[] = {
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {320, 240},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {240, 320},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {640, 480},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {480, 640},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {960, 720},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {720, 960},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {1280, 720},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {1280, 960},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {1920, 1080},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {320, 240},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {240, 320},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {640, 480},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {480, 640},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {960, 720},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {720, 960},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {1280, 720},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {1280, 960},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {1920, 1080},
++	}
++};
++
++struct mask_kobj_attr {
++	struct kobj_attribute attr;
++	unsigned int id;
++};
++
++#define to_mask_attr(attr)     \
++	container_of(attr, struct mask_kobj_attr, attr)
++
++static inline void mscaler_reg_writel(struct mscaler_device *mscaler, unsigned int reg, unsigned int val)
++{
++	writel(val, mscaler->iobase + reg);
++}
++
++static inline unsigned int mscaler_reg_readl(struct mscaler_device *mscaler, unsigned int reg)
++{
++	return readl(mscaler->iobase + reg);
++}
++
++
++/* isp video 回调函数，用�寻找当�支�的输出视频格�，由于mscaler�以输出，vic也�以输出，所以这里设计�回调的方�.*/
++
++/**
++ * @brief
++ *
++ * @param pixelformat	如果pixelformat�为空，则使用pixelformat匹�.
++ * @param mbus_code
++ * @param index
++ *
++ * @return
++ */
++struct isp_video_format *mscaler_find_format(const u32 *pixelformat, const u32 *mbus_code, int index)
++{
++	int i;
++	struct isp_video_format *fmt = NULL;
++
++	for(i = 0; i < ARRAY_SIZE(mscaler_output_formats); i++) {
++		fmt = &mscaler_output_formats[i];
++
++		if(pixelformat && fmt->fourcc == *pixelformat) {
++			return fmt;
++		}
++		if(mbus_code && fmt->mbus_code == *mbus_code) {
++			return fmt;
++		}
++
++		if(index == i) {
++			return fmt;
++		}
++	}
++
++	return NULL;
++}
++
++
++/* In irq context. */
++static int mscaler_irq_notify_ch_done(struct mscaler_device *mscaler, int ch)
++{
++	struct isp_video_buffer *isp_buffer = NULL;
++	//unsigned int y_last_addr = 0;
++	//unsigned int uv_last_addr = 0;
++	unsigned int fifo_empty = 0;
++	unsigned int fifo_full = 0;
++	unsigned int y_fifo_st = 0, uv_fifo_st = 0;
++	dma_addr_t y_addr = 0;
++	dma_addr_t uv_addr = 0;
++	struct vb2_buffer *vb2_buf = NULL;
++
++	spin_lock(&mscaler->lock);
++	/*由于mscaler stop stream时, ISP �能还会产生中断,这个时候�用处�*/
++	if(mscaler->state[ch] == 0) {
++		spin_unlock(&mscaler->lock);
++		return 0;
++	}
++
++	isp_buffer = list_first_entry_or_null(&mscaler->dma_queued_list[ch], struct isp_video_buffer, list_entry);
++	if(!isp_buffer) {
++		dev_err(mscaler->dev, "[warning] no isp_buffer found in dma_queued_list when interrupt happend!\n");
++		spin_unlock(&mscaler->lock);
++		return 0;
++	}
++
++	list_del(&isp_buffer->list_entry);
++
++
++//	y_last_addr = mscaler_reg_readl(mscaler, CHx_DMAOUT_Y_LAST_ADDR(ch));
++
++//	uv_last_addr = mscaler_reg_readl(mscaler, CHx_DMAOUT_UV_LAST_ADDR(ch));
++
++	/*TODO Sequence.*/
++	//if(isp_buffer->vb2.vb2_buf.state == VB2_BUF_STATE_ACTIVE)
++	isp_buffer->vb2.vb2_buf.timestamp = ktime_get_ns();
++	isp_buffer->vb2.sequence = mscaler->framenum[ch]++;
++
++#ifdef CONFIG_MSCA_BDEV
++	/*如果�端设备存在，则调用ms_bdev_qbuf,交给�端处�.*/
++	if(mscaler->bdev[ch].activated) {
++		ms_bdev_qbuf(&mscaler->bdev[ch], isp_buffer);
++	} else {
++		vb2_buffer_done(&isp_buffer->vb2.vb2_buf, VB2_BUF_STATE_DONE);
++	}
++#else
++	vb2_buffer_done(&isp_buffer->vb2.vb2_buf, VB2_BUF_STATE_DONE);
++#endif
++
++	y_fifo_st = mscaler_reg_readl(mscaler, CHx_Y_ADDR_FIFO_STA(ch));
++	uv_fifo_st = mscaler_reg_readl(mscaler, CHx_UV_ADDR_FIFO_STA(ch));
++
++	if((y_fifo_st & (1<<0)) && (uv_fifo_st & (1<<0))) {
++		fifo_empty = 1;
++	} else if((y_fifo_st & (1<<4)) || (uv_fifo_st & (1<<4))) {
++		fifo_full = 1;
++	}
++
++	/* 如果stream on了，就写入硬件.*/
++	if(mscaler->state[ch] == 1 && !fifo_full) {
++		isp_buffer = list_first_entry_or_null(&mscaler->dma_pending_list[ch], struct isp_video_buffer, list_entry);
++		if(isp_buffer){
++			vb2_buf = &isp_buffer->vb2.vb2_buf;
++			/*Y*/
++			y_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 0);
++			mscaler_reg_writel(mscaler, CHx_DMAOUT_Y_ADDR(ch), y_addr);
++
++			uv_addr = y_addr + isp_buffer->uv_offset;
++			/*UV*/
++			if(vb2_buf->num_planes == 2) {
++				uv_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 1);
++			}
++			mscaler_reg_writel(mscaler, CHx_DMAOUT_UV_ADDR(ch), uv_addr);
++			list_del(&isp_buffer->list_entry);
++			list_add_tail(&isp_buffer->list_entry, &mscaler->dma_queued_list[ch]);
++		}
++	}
++
++	spin_unlock(&mscaler->lock);
++
++	return 0;
++}
++
++static int mscaler_interrupt_service_routine(struct v4l2_subdev *sd,
++						u32 status, bool *handled)
++{
++	struct mscaler_device *mscaler = v4l2_get_subdevdata(sd);
++	int ret = 0;
++
++	/*�管心 mscaler的三个ch的done中断和crop出错的中断.*/
++	if(status & (1 << MSCA_CH0_FRM_DONE_INT)) {
++		ret = mscaler_irq_notify_ch_done(mscaler, 0);
++	}
++	if(status & (1 << MSCA_CH1_FRM_DONE_INT)) {
++		ret = mscaler_irq_notify_ch_done(mscaler, 1);
++	}
++
++	if(status & (1 << MSCA_CH2_FRM_DONE_INT)) {
++		ret = mscaler_irq_notify_ch_done(mscaler, 2);
++	}
++
++	/*TODO: add handler.*/
++
++	return ret;
++}
++
++static int mscaler_subdev_init(struct v4l2_subdev *sd, u32 val)
++{
++	struct mscaler_device *mscaler = v4l2_get_subdevdata(sd);
++	mscaler->sensor_id = val;
++	if(val == 0)
++		mscaler->iobase = (void __iomem *)0xb3316000;
++	else if(val == 1)
++		mscaler->iobase = (void __iomem *)0xb3317000;
++	return 0;
++}
++
++static int mscaler_subdev_reset(struct v4l2_subdev *sd, u32 val)
++{
++	return 0;
++}
++
++static const struct v4l2_subdev_core_ops mscaler_subdev_core_ops = {
++	.init	= mscaler_subdev_init,
++	.reset = mscaler_subdev_reset,
++        .log_status = v4l2_ctrl_subdev_log_status,
++        .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
++        .unsubscribe_event = v4l2_event_subdev_unsubscribe,
++	.interrupt_service_routine = mscaler_interrupt_service_routine,
++};
++
++static unsigned int ch_to_pad[] = {
++	MSCALER_PAD_SOURCE_CH0,
++	MSCALER_PAD_SOURCE_CH1,
++	MSCALER_PAD_SOURCE_CH2
++};
++
++static int pad_to_ch(int pad)
++{
++	switch(pad) {
++		case MSCALER_PAD_SOURCE_CH0:
++			return 0;
++		case MSCALER_PAD_SOURCE_CH1:
++			return 1;
++		case MSCALER_PAD_SOURCE_CH2:
++			return 2;
++		default:
++			return -EINVAL;
++	}
++}
++
++static int mscaler_enum_mbus_code(struct v4l2_subdev *sd,
++			      struct v4l2_subdev_pad_config *cfg,
++			      struct v4l2_subdev_mbus_code_enum *code)
++{
++	//printk("------%s, %d, sd->name: %s\n", __func__, __LINE__, sd->name);
++
++	if(code->index >= ARRAY_SIZE(mscaler_output_formats)) {
++		dev_err(sd->dev, "too many mbus formats!\n");
++		return -EINVAL;
++	}
++
++	code->code = mscaler_output_formats[code->index].mbus_code;
++
++	return 0;
++}
++static int mscaler_enum_frame_size(struct v4l2_subdev *sd,
++			       struct v4l2_subdev_pad_config *cfg,
++			       struct v4l2_subdev_frame_size_enum *fse)
++{
++	int index = fse->index;
++	int num_valid = -1;
++	int i = 0;
++	if(index >= ARRAY_SIZE(ingenic_isp_framesizes))
++		return -EINVAL;
++
++	for(i = 0; i < ARRAY_SIZE(ingenic_isp_framesizes); i++) {
++		if(fse->code != ingenic_isp_framesizes[i].fourcc)
++			continue;
++		if(index == ++num_valid) {
++			fse->max_height = ingenic_isp_framesizes[i].discrete.height;
++			fse->min_height = fse->max_height;
++			fse->max_width = ingenic_isp_framesizes[i].discrete.width;
++			fse->min_width = fse->max_width;
++			return 0;
++		}
++	}
++	return -EINVAL;
++}
++
++static int mscaler_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct mscaler_device *mscaler = v4l2_get_subdevdata(sd);
++	struct v4l2_mbus_framefmt *framefmt = NULL;
++	//printk("------%s, %d, sd->name: %s\n", __func__, __LINE__, sd->name);
++
++	if(format->which == V4L2_SUBDEV_FORMAT_TRY) {
++		framefmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
++	} else {
++		framefmt = &mscaler->formats[format->pad].format;
++	}
++
++	format->format = *framefmt;
++
++	return 0;
++}
++
++static int mscaler_set_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct mscaler_device *mscaler = v4l2_get_subdevdata(sd);
++	struct isp_video_device *ispvideo = v4l2_get_subdev_hostdata(sd);
++	struct media_pad *remote = NULL;
++	struct v4l2_subdev *remote_sd = NULL;
++	struct v4l2_subdev_format remote_subdev_fmt = {0};
++	int ch = 0;
++	int i = 0, ret = 0;
++
++	for(i = 0; i < MSCALER_MAX_CH; i++) {
++		if(ispvideo == &mscaler->ispvideo[i]) {
++			ch = i;
++			break;
++		}
++	}
++
++	//printk("%s, %d, width: %d, height: %d, mbus_code: %x\n", __func__, __LINE__, format->format.width, format->format.height, format->format.code);
++
++	mscaler->formats[format->pad] = *format;
++
++	remote = media_entity_remote_pad(&mscaler->pads[MSCALER_PAD_SINK]);
++	remote_sd = media_entity_to_v4l2_subdev(remote->entity);
++
++	memcpy(&remote_subdev_fmt, format, sizeof(struct v4l2_subdev_format));
++	remote_subdev_fmt.pad = remote->index;
++	remote_subdev_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	ret = v4l2_subdev_call(remote_sd, pad, set_fmt, NULL, &remote_subdev_fmt);
++	if(ret < 0) {
++		dev_dbg(mscaler->dev, "Failed to set_fmt from remote pad\n");
++	}
++
++	memset(&remote_subdev_fmt, 0, sizeof(struct v4l2_subdev_format));
++	remote_subdev_fmt.pad = remote->index;
++	remote_subdev_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	ret = v4l2_subdev_call(remote_sd, pad, get_fmt, NULL, &remote_subdev_fmt);
++	if(ret < 0) {
++		dev_err(mscaler->dev, "Failed to get_fmt from remote pad\n");
++		return -EINVAL;
++	}
++
++	memcpy(&mscaler->formats[MSCALER_PAD_SINK], &remote_subdev_fmt, sizeof(struct v4l2_subdev_format));
++
++	/*def crop info.*/
++	mscaler->attr[ch].fcrop_en = 0;
++	mscaler->attr[ch].fcrop_x = 0;
++	mscaler->attr[ch].fcrop_y = 0;
++	mscaler->attr[ch].fcrop_width = mscaler->formats[MSCALER_PAD_SINK].format.width;
++	mscaler->attr[ch].fcrop_height = mscaler->formats[MSCALER_PAD_SINK].format.height;
++	mscaler->attr[ch].scaler_en = 0;
++	mscaler->attr[ch].scaler_width = mscaler->formats[format->pad].format.width;
++	mscaler->attr[ch].scaler_height = mscaler->formats[format->pad].format.height;
++	mscaler->attr[ch].crop_en = 0;
++	mscaler->attr[ch].crop_x = 0;
++	mscaler->attr[ch].crop_y = 0;
++	mscaler->attr[ch].crop_width = mscaler->formats[format->pad].format.width;
++	mscaler->attr[ch].crop_height = mscaler->formats[format->pad].format.height;
++
++	return 0;
++}
++
++static int mscaler_get_selection(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, struct v4l2_subdev_selection *sel)
++{
++	struct mscaler_device *mscaler = v4l2_get_subdevdata(sd);
++	struct v4l2_subdev_format *output_fmt = NULL;
++	int ch = pad_to_ch(sel->pad);
++
++	if(ch < 0)
++		return -EINVAL;
++
++	output_fmt = &mscaler->formats[sel->pad];
++	if(sel->target == V4L2_SEL_TGT_CROP || sel->target == V4L2_SEL_TGT_CROP_DEFAULT){
++		sel->r.left = mscaler->attr[ch].crop_x;
++		sel->r.top = mscaler->attr[ch].crop_y;
++		sel->r.width = mscaler->attr[ch].crop_width;
++		sel->r.height = mscaler->attr[ch].crop_height;
++	} else if(sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
++		sel->r.left = 0;
++		sel->r.top = 0;
++		sel->r.width = output_fmt->format.width;
++		sel->r.height = output_fmt->format.height;
++	} else {
++		dev_warn(mscaler->dev, "unsupported selection target!\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int mscaler_set_selection(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, struct v4l2_subdev_selection *sel)
++{
++	struct mscaler_device *mscaler = v4l2_get_subdevdata(sd);
++	int ch = pad_to_ch(sel->pad);
++
++	if(ch < 0)
++		return -EINVAL;
++
++	if(sel->flags == V4L2_SEL_FLAG_GE) {
++		dev_warn(mscaler->dev, "unsupported selection flags!\n");
++		return -EINVAL;
++	}
++
++	if(sel->target == V4L2_SEL_TGT_CROP){
++		mscaler->attr[ch].crop_en = 1;
++		mscaler->attr[ch].crop_x = sel->r.left;
++		mscaler->attr[ch].crop_y = sel->r.top;
++		mscaler->attr[ch].crop_width = sel->r.width;
++		mscaler->attr[ch].crop_height = sel->r.height;
++	} else {
++		dev_warn(mscaler->dev, "unsupported selection target!\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static const struct v4l2_subdev_pad_ops mscaler_subdev_pad_ops = {
++        .enum_mbus_code         = mscaler_enum_mbus_code,
++        .enum_frame_size        = mscaler_enum_frame_size,
++        .get_fmt                = mscaler_get_fmt,
++        .set_fmt                = mscaler_set_fmt,
++        .get_selection          = mscaler_get_selection,
++        .set_selection          = mscaler_set_selection,
++};
++
++static int mscaler_stream_enable(struct mscaler_device *mscaler, int ch)
++{
++	struct v4l2_subdev_format *input_fmt = &mscaler->formats[MSCALER_PAD_SINK];
++	struct v4l2_subdev_format *output_fmt = &mscaler->formats[ch_to_pad[ch]];
++	unsigned long flags = 0;
++	int ret = 0;
++	struct isp_video_buffer *isp_buffer = NULL;
++	struct isp_video_buffer *tmp = NULL;
++	dma_addr_t y_addr = 0;
++	dma_addr_t uv_addr = 0;
++	unsigned int fifo_empty = 0;
++	unsigned int fifo_full = 0;
++	unsigned int y_fifo_st = 0, uv_fifo_st = 0;
++	struct vb2_buffer *vb2_buf = NULL;
++	tisp_channel_attr_t attr;
++
++	dev_dbg(mscaler->dev, "-----input_fmt->format.width: %d, input_fmt->format.height: %d\n", input_fmt->format.width, input_fmt->format.height);
++	dev_dbg(mscaler->dev, "-----output_fmt->format.width: %d, output_fmt->format.height: %d\n", output_fmt->format.width, output_fmt->format.height);
++
++	spin_lock_irqsave(&mscaler->lock, flags);
++
++	memset(&attr, 0, sizeof(tisp_channel_attr_t));
++
++	/*TODO fcrop*/
++	/*TODO output_fmt*/
++
++	if(mscaler->sensor_id == 0)
++		tisp_channel_main_attr_set(ch, &mscaler->attr[ch]);
++	else if(mscaler->sensor_id == 1)
++		tisp_channel_sec_attr_set(ch, &mscaler->attr[ch]);
++	mscaler->state[ch] = 1;
++	mscaler->framenum[ch] = 0;
++
++	/*因为ISP��的执行时间时在stream_on的时候，这个时候上层qbuf已�调用了，
++	 * 如果部将这些buffer�新加入硬件队列，则会出现问题.*/
++	list_for_each_entry_safe(isp_buffer, tmp, &mscaler->dma_pending_list[ch], list_entry) {
++		y_fifo_st = mscaler_reg_readl(mscaler, CHx_Y_ADDR_FIFO_STA(ch));
++		uv_fifo_st = mscaler_reg_readl(mscaler, CHx_UV_ADDR_FIFO_STA(ch));
++		if((y_fifo_st & (1<<0)) && (uv_fifo_st & (1<<0))) {
++			fifo_empty = 1;
++		} else if((y_fifo_st & (1<<4)) || (uv_fifo_st & (1<<4))) {
++			fifo_full = 1;
++		}
++		if(fifo_full)
++			break;
++
++		vb2_buf = &isp_buffer->vb2.vb2_buf;
++		/*Y*/
++		y_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 0);
++		mscaler_reg_writel(mscaler, CHx_DMAOUT_Y_ADDR(ch), y_addr);
++
++		uv_addr = y_addr + isp_buffer->uv_offset;
++		if(vb2_buf->num_planes == 2) {
++			uv_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 1);
++		}
++		mscaler_reg_writel(mscaler, CHx_DMAOUT_UV_ADDR(ch), uv_addr);
++		list_del(&isp_buffer->list_entry);
++		list_add_tail(&isp_buffer->list_entry, &mscaler->dma_queued_list[ch]);
++	}
++	if(mscaler->sensor_id == 0)
++		tisp_channel_main_start(ch);
++	else if(mscaler->sensor_id == 1)
++		tisp_channel_sec_start(ch);
++
++	spin_unlock_irqrestore(&mscaler->lock, flags);
++
++#ifdef CONFIG_MSCA_BDEV
++	if(mscaler->bdev[ch].activated == 1) {
++		ret = ms_bdev_init(&mscaler->bdev[ch]);
++		if(ret < 0) {
++			return -EINVAL;
++		}
++	}
++#endif
++
++	return ret;
++}
++
++static int mscaler_stream_disable(struct mscaler_device *mscaler, int ch)
++{
++	unsigned long flags = 0;
++	int ret = 0;
++	unsigned int timeout = 0xffffff;
++	struct isp_video_buffer *isp_buffer = NULL;
++	struct isp_video_buffer *tmp = NULL;
++
++
++	spin_lock_irqsave(&mscaler->lock, flags);
++
++	if(mscaler->sensor_id == 0)
++		tisp_channel_main_stop(ch);
++	else
++		tisp_channel_sec_stop(ch);
++
++	spin_unlock_irqrestore(&mscaler->lock, flags);
++
++	/* polling status to make sure channel stopped.*/
++	/*
++	do {
++		val = mscaler_reg_readl(mscaler, MSCA_CH_STA);
++
++	} while(!!((val & (1<<ch)) << 0) && --timeout);
++	*/
++
++	if(!timeout) {
++		dev_err(mscaler->dev, "[Warning] mscaler disable timeout!\n");
++	}
++
++	spin_lock_irqsave(&mscaler->lock, flags);
++
++	/* clear fifo*/
++	mscaler_reg_writel(mscaler, CHx_DMAOUT_Y_ADDR_CLR(ch), 1);
++	mscaler_reg_writel(mscaler, CHx_DMAOUT_UV_ADDR_CLR(ch), 1);
++	mscaler_reg_writel(mscaler, CHx_DMAOUT_Y_LAST_ADDR_CLR(ch), 1);
++	mscaler_reg_writel(mscaler, CHx_DMAOUT_UV_LAST_ADDR_CLR(ch), 1);
++
++
++	list_for_each_entry_safe(isp_buffer, tmp, &mscaler->dma_queued_list[ch], list_entry) {
++		struct vb2_buffer *vb2_buf = &isp_buffer->vb2.vb2_buf;
++		vb2_buffer_done(vb2_buf, VB2_BUF_STATE_ERROR);
++		list_del(&isp_buffer->list_entry);
++	}
++	list_for_each_entry_safe(isp_buffer, tmp, &mscaler->dma_pending_list[ch], list_entry) {
++		struct vb2_buffer *vb2_buf = &isp_buffer->vb2.vb2_buf;
++		vb2_buffer_done(vb2_buf, VB2_BUF_STATE_ERROR);
++		list_del(&isp_buffer->list_entry);
++	}
++
++	mscaler->state[ch] = 0;
++	spin_unlock_irqrestore(&mscaler->lock, flags);
++
++#ifdef CONFIG_MSCA_BDEV
++	if(mscaler->bdev[ch].activated) {
++		ms_bdev_deinit(&mscaler->bdev[ch]);
++		mscaler->bdev[ch].activated = 0;
++	}
++#endif
++
++	return ret;
++}
++
++static int mscaler_subdev_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct mscaler_device *mscaler = v4l2_get_subdevdata(sd);
++	struct isp_video_device *ispvideo = v4l2_get_subdev_hostdata(sd);
++	int ch = 0;
++	int i = 0, ret = 0;
++
++	for(i = 0; i < MSCALER_MAX_CH; i++) {
++		if(ispvideo == &mscaler->ispvideo[i]) {
++			ch = i;
++			break;
++		}
++	}
++
++//	printk("%s,%d, sd->video_device->name:%s, ispvideo: %p, ch = %d, enable = %d\n", __func__, __LINE__, sd->devnode->name, ispvideo, ch, enable);
++	/*获�当�channel.*/
++	if(enable) {
++		ret = mscaler_stream_enable(mscaler, ch);
++		//dump_mscaler_regs(mscaler);
++	} else {
++		ret = mscaler_stream_disable(mscaler, ch);
++	}
++
++	if(ret < 0) {
++		dev_err(mscaler->dev, "enable stream error!\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int mscaler_subdev_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *cc)
++{
++	struct mscaler_device *mscaler = v4l2_get_subdevdata(sd);
++	struct isp_video_device *ispvideo = v4l2_get_subdev_hostdata(sd);
++	struct v4l2_subdev_format *input_fmt = NULL;
++	int ch = 0;
++	int i = 0, ret = 0;
++
++	for(i = 0; i < MSCALER_MAX_CH; i++) {
++		if(ispvideo == &mscaler->ispvideo[i]) {
++			ch = i;
++			break;
++		}
++	}
++
++	input_fmt = &mscaler->formats[MSCALER_PAD_SINK];
++
++	cc->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++	cc->bounds.left = 0;
++	cc->bounds.top = 0;
++	cc->bounds.width = input_fmt->format.width;
++	cc->bounds.height = input_fmt->format.height;
++	cc->defrect.left = 0;
++	cc->defrect.top = 0;
++	cc->defrect.width = input_fmt->format.width;
++	cc->defrect.height = input_fmt->format.height;
++	cc->pixelaspect.numerator = input_fmt->format.height;
++	cc->pixelaspect.denominator = input_fmt->format.width;
++
++	return ret;
++}
++
++static int mscaler_subdev_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *crop)
++{
++	struct mscaler_device *mscaler = v4l2_get_subdevdata(sd);
++	struct isp_video_device *ispvideo = v4l2_get_subdev_hostdata(sd);
++	int ch = 0;
++	int i = 0, ret = 0;
++
++	for(i = 0; i < MSCALER_MAX_CH; i++) {
++		if(ispvideo == &mscaler->ispvideo[i]) {
++			ch = i;
++			break;
++		}
++	}
++
++	crop->c.top = mscaler->attr[ch].fcrop_y;
++	crop->c.left = mscaler->attr[ch].fcrop_x;
++	crop->c.width = mscaler->attr[ch].fcrop_width;
++	crop->c.height = mscaler->attr[ch].fcrop_height;
++
++	return ret;
++}
++
++static int mscaler_subdev_s_crop(struct v4l2_subdev *sd, const struct v4l2_crop *crop)
++{
++	struct mscaler_device *mscaler = v4l2_get_subdevdata(sd);
++	struct isp_video_device *ispvideo = v4l2_get_subdev_hostdata(sd);
++	int ch = 0;
++	int i = 0, ret = 0;
++
++	for(i = 0; i < MSCALER_MAX_CH; i++) {
++		if(ispvideo == &mscaler->ispvideo[i]) {
++			ch = i;
++			break;
++		}
++	}
++
++	mscaler->attr[ch].fcrop_en = 1;
++	mscaler->attr[ch].fcrop_y = crop->c.top;
++	mscaler->attr[ch].fcrop_x = crop->c.left;
++	mscaler->attr[ch].fcrop_width = crop->c.width;
++	mscaler->attr[ch].fcrop_height = crop->c.height;
++
++	return ret;
++}
++
++
++static const struct v4l2_subdev_video_ops mscaler_subdev_video_ops = {
++	.s_stream = mscaler_subdev_s_stream,
++	.cropcap = mscaler_subdev_cropcap,
++	.g_crop = mscaler_subdev_g_crop,
++	.s_crop = mscaler_subdev_s_crop,
++};
++
++
++static const struct v4l2_subdev_ops mscaler_subdev_ops = {
++        .core = &mscaler_subdev_core_ops,
++        .pad = &mscaler_subdev_pad_ops,
++        .video = &mscaler_subdev_video_ops,
++};
++
++
++static int mscaler_video_qbuf(struct isp_video_device *ispvideo, struct isp_video_buffer *isp_buffer)
++{
++	struct mscaler_device *mscaler = ispvideo->ispcam->mscaler;
++	struct vb2_buffer *vb2_buf = NULL;
++	int ch = 0;
++	unsigned long flags = 0;
++	unsigned int fifo_empty = 0;
++	unsigned int fifo_full = 0;
++	unsigned int y_fifo_st = 0, uv_fifo_st = 0;
++	dma_addr_t y_addr = 0;
++	dma_addr_t uv_addr = 0;
++
++	int i = 0;
++	for(i = 0; i < MSCALER_MAX_CH; i++) {
++		if(ispvideo == &mscaler->ispvideo[i]) {
++			ch = i;
++			break;
++		}
++	}
++
++	spin_lock_irqsave(&mscaler->lock, flags);
++
++	list_add_tail(&isp_buffer->list_entry, &mscaler->dma_pending_list[ch]);
++
++	if(mscaler->iobase){
++		y_fifo_st = mscaler_reg_readl(mscaler, CHx_Y_ADDR_FIFO_STA(ch));
++		uv_fifo_st = mscaler_reg_readl(mscaler, CHx_UV_ADDR_FIFO_STA(ch));
++
++		if((y_fifo_st & (1<<0)) && (uv_fifo_st & (1<<0))) {
++			fifo_empty = 1;
++		} else if((y_fifo_st & (1<<4)) || (uv_fifo_st & (1<<4))) {
++			fifo_full = 1;
++		}
++
++		if(mscaler->state[ch] == 1 && !fifo_full) {
++			isp_buffer = list_first_entry_or_null(&mscaler->dma_pending_list[ch], struct isp_video_buffer, list_entry);
++			if(isp_buffer){
++				vb2_buf = &isp_buffer->vb2.vb2_buf;
++				/*Y*/
++				y_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 0);
++				mscaler_reg_writel(mscaler, CHx_DMAOUT_Y_ADDR(ch), y_addr);
++
++				uv_addr = y_addr + isp_buffer->uv_offset;
++				/*UV*/
++				if(vb2_buf->num_planes == 2) {
++					uv_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 1);
++				}
++				mscaler_reg_writel(mscaler, CHx_DMAOUT_UV_ADDR(ch), uv_addr);
++				list_del(&isp_buffer->list_entry);
++				list_add_tail(&isp_buffer->list_entry, &mscaler->dma_queued_list[ch]);
++			}
++		}
++	}
++
++	spin_unlock_irqrestore(&mscaler->lock, flags);
++
++	//printk("-----%s,%d queued buffer y_addr: 0x%08x, uv: 0x%08x on ch: %d\n", __func__, __LINE__, y_addr, uv_addr, ch);
++
++	return 0;
++}
++
++static const struct isp_video_ops mscaler_video_ops = {
++	.find_format 	= mscaler_find_format,
++	.qbuf		= mscaler_video_qbuf,
++};
++
++static ssize_t
++dump_mscaler(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct mscaler_device *mscaler = dev_get_drvdata(dev);
++	char *p = buf;
++	int i = 0;
++
++	p += sprintf(p, "MSCA_CH_EN     :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_CH_EN));
++	p += sprintf(p, "MSCA_INT_STA   :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_INT_STA));
++	p += sprintf(p, "MSCA_INT_MSK   :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_INT_MSK));
++	p += sprintf(p, "MSCA_MASK_EN   :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_MASK_EN));
++	p += sprintf(p, "MSCA_DMAOUT_ARB:0x%08x\n", mscaler_reg_readl(mscaler, MSCA_DMAOUT_ARB));
++	p += sprintf(p, "MSCA_CLK_GATE_EN:0x%08x\n", mscaler_reg_readl(mscaler, MSCA_CLK_GATE_EN));
++	p += sprintf(p, "MSCA_CLK_DIS   :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_CLK_DIS));
++	p += sprintf(p, "MSCA_SRC_IN    :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_SRC_IN));
++	p += sprintf(p, "MSCA_SRC_SIZE  :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_SRC_SIZE));
++	p += sprintf(p, "MSCA_GLO_RSZ_COEF_WR:0x%08x\n", mscaler_reg_readl(mscaler, MSCA_GLO_RSZ_COEF_WR));
++	p += sprintf(p, "MSCA_SYS_PRO_CLK_EN :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_SYS_PRO_CLK_EN));
++	p += sprintf(p, "MSCA_DS0_CLK_NUM    :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_DS0_CLK_NUM));
++	p += sprintf(p, "MSCA_DS1_CLK_NUM    :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_DS1_CLK_NUM));
++	p += sprintf(p, "MSCA_DS2_CLK_NUM    :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_DS2_CLK_NUM));
++
++	for(i = 0; i < MSCALER_MAX_CH; i++) {
++
++		p += sprintf(p, "CHx_RSZ_OSIZE(%d)	:0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_RSZ_OSIZE(i)));
++		p += sprintf(p, "CHx_RSZ_STEP(%d)       :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_RSZ_STEP(i)));
++		p += sprintf(p, "CHx_CROP_OPOS(%d)      :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_CROP_OPOS(i)));
++		p += sprintf(p, "CHx_CROP_OSIZE(%d)     :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_CROP_OSIZE(i)));
++		p += sprintf(p, "CHx_FRA_CTRL_LOOP(%d)  :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_FRA_CTRL_LOOP(i)));
++		p += sprintf(p, "CHx_FRA_CTRL_MASK(%d)  :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_FRA_CTRL_MASK(i)));
++		p += sprintf(p, "CHx_MS0_POS(%d)        :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS0_POS(i)));
++		p += sprintf(p, "CHx_MS0_SIZE(%d)       :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS0_SIZE(i)));
++		p += sprintf(p, "CHx_MS0_VALUE(%d)      :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS0_VALUE(i)));
++		p += sprintf(p, "CHx_MS1_POS(%d)        :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS1_POS(i)));
++		p += sprintf(p, "CHx_MS1_SIZE(%d)       :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS1_SIZE(i)));
++		p += sprintf(p, "CHx_MS1_VALUE(%d)      :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS1_VALUE(i)));
++		p += sprintf(p, "CHx_MS2_POS(%d)        :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS2_POS(i)));
++		p += sprintf(p, "CHx_MS2_SIZE(%d)       :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS2_SIZE(i)));
++		p += sprintf(p, "CHx_MS2_VALUE(%d)      :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS2_VALUE(i)));
++		p += sprintf(p, "CHx_MS3_POS(%d)        :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS3_POS(i)));
++		p += sprintf(p, "CHx_MS3_SIZE(%d)       :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS3_SIZE(i)));
++		p += sprintf(p, "CHx_MS3_VALUE(%d)      :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS3_VALUE(i)));
++		p += sprintf(p, "CHx_OUT_FMT(%d)        :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_OUT_FMT(i)));
++		p += sprintf(p, "CHx_DMAOUT_Y_ADDR(%d)  :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_Y_ADDR(i)));
++		p += sprintf(p, "CHx_Y_ADDR_FIFO_STA(%d):0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_Y_ADDR_FIFO_STA(i)));
++	//	p += sprintf(p, "CHx_DMAOUT_Y_LAST_ADDR(%d)              :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_Y_LAST_ADDR(i)));
++	//	p += sprintf(p, "CHx_DMAOUT_Y_LAST_STATS_NUM(%d)         :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_Y_LAST_STATS_NUM(i)));
++		p += sprintf(p, "CHx_Y_LAST_ADDR_FIFO_STA(%d):0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_Y_LAST_ADDR_FIFO_STA(i)));
++		p += sprintf(p, "CHx_DMAOUT_Y_STRI(%d)       :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_Y_STRI(i)));
++		p += sprintf(p, "CHx_DMAOUT_UV_ADDR(%d)      :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_UV_ADDR(i)));
++		p += sprintf(p, "CHx_UV_ADDR_FIFO_STA(%d)    :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_UV_ADDR_FIFO_STA(i)));
++	//	p += sprintf(p, "CHx_DMAOUT_UV_LAST_ADDR(%d) :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_UV_LAST_ADDR(i)));
++	//	p += sprintf(p, "CHx_DMAOUT_UV_LAST_STATS_NUM(%d)        :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_UV_LAST_STATS_NUM(i)));
++		p += sprintf(p, "CHx_UV_LAST_ADDR_FIFO_STA(%d):0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_UV_LAST_ADDR_FIFO_STA(i)));
++		p += sprintf(p, "CHx_DMAOUT_UV_STRI(%d)       :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_UV_STRI(i)));
++		p += sprintf(p, "CHx_DMAOUT_Y_ADDR_CLR(%d)    :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_Y_ADDR_CLR(i)));
++		p += sprintf(p, "CHx_DMAOUT_UV_ADDR_CLR(%d)   :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_UV_ADDR_CLR(i)));
++		p += sprintf(p, "CHx_DMAOUT_Y_LAST_ADDR_CLR(%d):0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_Y_LAST_ADDR_CLR(i)));
++		p += sprintf(p, "CHx_DMAOUT_UV_LAST_ADDR_CLR(%d):0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_UV_LAST_ADDR_CLR(i)));
++		p += sprintf(p, "CHx_DMAOUT_Y_ADDR_SEL(%d)    :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_Y_ADDR_SEL(i)));
++		p += sprintf(p, "CHx_DMAOUT_UV_ADDR_SEL(%d)   :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_UV_ADDR_SEL(i)));
++	}
++
++	return p - buf;
++}
++
++
++static DEVICE_ATTR(dump_mscaler, S_IRUGO|S_IWUSR, dump_mscaler, NULL);
++
++static struct attribute *mscaler_debug_attrs[] = {
++        &dev_attr_dump_mscaler.attr,
++	NULL,
++};
++
++static struct attribute_group mscaler_debug_attr_group = {
++        .name   = "debug",
++        .attrs  = mscaler_debug_attrs,
++};
++
++
++#define to_mscaler_device(kobj) dev_get_drvdata(container_of(kobj->parent->parent, struct device, kobj))
++
++static ssize_t mask_enable_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch = kobj->name[2] - '0';
++	char *p = buf;
++	unsigned int tmp = 0;
++
++	tmp = mscaler_reg_readl(mscaler, MSCA_MASK_EN);
++	p += sprintf(p, "%d\n", (tmp >> ch) & 1);
++
++	return p - buf;
++}
++
++static ssize_t mask_enable_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch = kobj->name[2] - '0';
++	unsigned int tmp = 0;
++	int enable = simple_strtol(buf, NULL, 10);
++
++	tmp = mscaler_reg_readl(mscaler, MSCA_MASK_EN);
++	if(enable == 1)
++		tmp |= 1 << ch;
++	else if(enable == 0)
++		tmp &= ~(1 << ch);
++	else
++		return -EINVAL;
++
++	mscaler_reg_writel(mscaler, MSCA_MASK_EN, tmp);
++	return count;
++}
++
++static struct kobj_attribute enable_attribute =
++__ATTR(enable,S_IRUGO|S_IWUSR, mask_enable_show, mask_enable_store);
++
++
++static ssize_t mask_pos_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch= kobj->name[2] - '0';
++	int mask = to_mask_attr(attr)->id;
++	char *p = buf;
++	unsigned int tmp = 0;
++
++	tmp = mscaler_reg_readl(mscaler, CHx_MSx_POS(ch,mask));
++	p += sprintf(p, "x:%d\ty:%d\n", tmp >> 16, tmp & 0xffff);
++
++	return p - buf;
++}
++
++static ssize_t mask_pos_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch= kobj->name[2] - '0';
++	int mask = to_mask_attr(attr)->id;
++	char *p;
++	char *s = (char *)buf;
++	int pos_x, pos_y;
++
++	p = strsep(&s, "*");
++	if(!s) {
++		return -EINVAL;
++	}
++
++	pos_x = simple_strtoul(p, NULL, 10);
++	pos_y = simple_strtoul(s, NULL, 10);
++
++	mscaler_reg_writel(mscaler, CHx_MSx_POS(ch,mask), (pos_x << 16) | pos_y);
++	return count;
++}
++
++static ssize_t mask_size_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch= kobj->name[2] - '0';
++	int mask = to_mask_attr(attr)->id;
++	char *p = buf;
++	unsigned int tmp = 0;
++
++	tmp = mscaler_reg_readl(mscaler, CHx_MSx_SIZE(ch,mask));
++	p += sprintf(p, "width:%d\theight:%d\n", tmp >> 16, tmp & 0xffff);
++
++	return p - buf;
++}
++
++static ssize_t mask_size_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch= kobj->name[2] - '0';
++	int mask = to_mask_attr(attr)->id;
++	char *p;
++	char *s = (char *)buf;
++	int width, height;
++
++	p = strsep(&s, "*");
++	if(!s) {
++		return -EINVAL;
++	}
++
++	width = simple_strtoul(p, NULL, 10);
++	height = simple_strtoul(s, NULL, 10);
++
++	mscaler_reg_writel(mscaler, CHx_MSx_SIZE(ch,mask), (width << 16) | height);
++	return count;
++}
++static ssize_t mask_color_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch= kobj->name[2] - '0';
++	int mask = to_mask_attr(attr)->id;
++	char *p = buf;
++	unsigned int tmp = 0;
++
++	tmp = mscaler_reg_readl(mscaler, CHx_MSx_VALUE(ch,mask));
++	p += sprintf(p, "0x%08x\n", tmp);
++
++	return p - buf;
++}
++
++static ssize_t mask_color_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch= kobj->name[2] - '0';
++	int mask = to_mask_attr(attr)->id;
++	char *p;
++	char *s = (char *)buf;
++	int value = 0;
++
++	p = strsep(&s, "x");
++	if(!s) {
++		return -EINVAL;
++	}
++
++	value = simple_strtoul(s, NULL, 16);
++
++	mscaler_reg_writel(mscaler, CHx_MSx_VALUE(ch,mask), value);
++	return count;
++}
++
++#define MASK_ATTR(mask, _name, _mode, _show, _store)          \
++{                                                       \
++	.attr   = __ATTR(_name, _mode, _show, _store),  \
++	.id     = mask,                                                \
++}
++
++
++#define MASK_ATTRIBUTE(_name, _mode, _show, _store)                                                    \
++	static struct mask_kobj_attr kobj_attr_##_name##mask0 = MASK_ATTR(0, _name, _mode, _show, _store); \
++	static struct mask_kobj_attr kobj_attr_##_name##mask1 = MASK_ATTR(1, _name, _mode, _show, _store); \
++	static struct mask_kobj_attr kobj_attr_##_name##mask2 = MASK_ATTR(2, _name, _mode, _show, _store); \
++	static struct mask_kobj_attr kobj_attr_##_name##mask3 = MASK_ATTR(3, _name, _mode, _show, _store)
++
++MASK_ATTRIBUTE(pos, S_IRUGO|S_IWUSR, mask_pos_show, mask_pos_store);
++MASK_ATTRIBUTE(size, S_IRUGO|S_IWUSR, mask_size_show, mask_size_store);
++MASK_ATTRIBUTE(color, S_IRUGO|S_IWUSR, mask_color_show, mask_color_store);
++
++#define MASK_ATTRIBUTE_GROUP(name)                                     \
++	static struct attribute *mscaler_##name##_attrs[] = {               \
++		&kobj_attr_pos##name.attr.attr,                     \
++		&kobj_attr_size##name.attr.attr,                      \
++		&kobj_attr_color##name.attr.attr,                  \
++		NULL,                                                   \
++	};
++
++MASK_ATTRIBUTE_GROUP(mask0);
++MASK_ATTRIBUTE_GROUP(mask1);
++MASK_ATTRIBUTE_GROUP(mask2);
++MASK_ATTRIBUTE_GROUP(mask3);
++
++
++static struct attribute_group mscaler_mask0_group = {
++	.name = "mask0",
++	.attrs = mscaler_mask0_attrs,
++};
++static struct attribute_group mscaler_mask1_group = {
++	.name = "mask1",
++	.attrs = mscaler_mask1_attrs,
++};
++static struct attribute_group mscaler_mask2_group = {
++	.name = "mask2",
++	.attrs = mscaler_mask2_attrs,
++};
++static struct attribute_group mscaler_mask3_group = {
++	.name = "mask3",
++	.attrs = mscaler_mask3_attrs,
++};
++
++
++static const struct attribute_group *mscaler_maskx_groups[] = {
++	&mscaler_mask0_group,
++	&mscaler_mask1_group,
++	&mscaler_mask2_group,
++	&mscaler_mask3_group,
++	NULL,
++};
++
++static void __maybe_unused dump_mscaler_regs(struct mscaler_device *mscaler)
++{
++	char *buf = kzalloc(4 * 1024, GFP_KERNEL);
++	int ret = 0;
++
++	ret = dump_mscaler(mscaler->dev, NULL, buf);
++
++	printk("%s", buf);
++
++	kfree(buf);
++}
++
++int mscaler_video_nr_map[2][3] = {
++	{INGENIC_MSCA0_CH0_VIDEO_NR , INGENIC_MSCA0_CH1_VIDEO_NR , INGENIC_MSCA0_CH2_VIDEO_NR},
++	{INGENIC_MSCA1_CH0_VIDEO_NR , INGENIC_MSCA1_CH1_VIDEO_NR , INGENIC_MSCA1_CH2_VIDEO_NR},
++
++};
++
++static int mscaler_comp_bind(struct device *comp, struct device *master,
++                              void *master_data)
++{
++	struct mscaler_device *mscaler = dev_get_drvdata(comp);
++	struct ispcam_device *ispcam = (struct ispcam_device *)master_data;
++	struct v4l2_device *v4l2_dev = &ispcam->v4l2_dev;
++	struct v4l2_subdev *sd = &mscaler->sd;
++	int i = 0;
++	int ret = 0;
++	int nr = -1;
++
++	//dev_info(comp, "----dev_name(comp): %s----%s, %d \n", dev_name(comp), __func__, __LINE__);
++
++	/* link subdev to master.*/
++	mscaler->ispcam = (void *)ispcam;
++	ispcam->mscaler = mscaler;
++
++	/*1. register supported subdev ctrls.*/
++
++
++	/*2. init v4l2_subdev*/
++
++	v4l2_subdev_init(sd, &mscaler_subdev_ops);
++
++	sd->owner = THIS_MODULE;
++	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++	strscpy(sd->name, dev_name(comp), sizeof(sd->name));
++	v4l2_set_subdevdata(sd, mscaler);
++
++
++	/* init mscaler pads. */
++	mscaler->pads = kzalloc(sizeof(struct media_pad) * MSCALER_NUM_PADS, GFP_KERNEL);
++	if(!mscaler->pads) {
++		ret = -ENOMEM;
++		goto err_alloc_pads;
++	}
++	mscaler->pads[0].index = MSCALER_PAD_SINK;
++	mscaler->pads[0].flags = MEDIA_PAD_FL_SINK;
++	mscaler->pads[1].index = MSCALER_PAD_SOURCE_CH0;
++	mscaler->pads[1].flags = MEDIA_PAD_FL_SOURCE;
++	mscaler->pads[2].index = MSCALER_PAD_SOURCE_CH1;
++	mscaler->pads[2].flags = MEDIA_PAD_FL_SOURCE;
++	mscaler->pads[3].index = MSCALER_PAD_SOURCE_CH2;
++	mscaler->pads[3].flags = MEDIA_PAD_FL_SOURCE;
++
++	ret = media_entity_pads_init(&sd->entity, MSCALER_NUM_PADS, mscaler->pads);
++
++	/*3. register v4l2_subdev*/
++	sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER;
++	ret = v4l2_device_register_subdev(v4l2_dev, sd);
++	if(ret < 0) {
++		dev_err(comp, "Failed to register v4l2_subdev for mscaler\n");
++		goto err_subdev_register;
++	}
++
++	/*create mask dir*/
++	mscaler->mask_kobj = kobject_create_and_add("mask", &mscaler->dev->kobj);
++	if (!mscaler->mask_kobj) {
++		dev_err(mscaler->dev, "device create kobject failed\n");
++		ret = -EINVAL;
++		goto err_mask_kobj;
++	}
++
++
++	for(i = 0; i < MSCALER_MAX_CH; i++) {
++		struct isp_video_device *ispvideo = &mscaler->ispvideo[i];
++		char name[32];
++		sprintf(name, "%s-ch%d", dev_name(mscaler->dev), i);
++
++		ispvideo->ispcam = ispcam;
++		ret = isp_video_init(ispvideo, name, &mscaler_video_ops);
++		if(ret < 0){
++			/*TODO*/
++		}
++
++		nr = mscaler_video_nr_map[ispcam->dev_nr][i];
++		ret = isp_video_register(ispvideo, &ispcam->v4l2_dev, nr);
++		if(ret < 0){
++			/*TODO*/
++		}
++
++		/*create mask/chx dir*/
++		sprintf(name, "ch%d", i);
++		mscaler->mask_ch_kobj[i] = kobject_create_and_add(name, mscaler->mask_kobj);
++		if (!mscaler->mask_ch_kobj[i]) {
++			dev_err(mscaler->dev, "device create kobject failed\n");
++			ret = -EINVAL;
++			goto err_mask_ch_kobj;
++		}
++
++		/*create enable attr*/
++		ret = sysfs_create_file(mscaler->mask_ch_kobj[i], &enable_attribute.attr);
++		if(ret){
++			dev_err(mscaler->dev, "device create sys file failed\n");
++			goto err_mask_create_file;
++		}
++
++		/*create mask/chx/maskx dir*/
++		ret = sysfs_create_groups(mscaler->mask_ch_kobj[i], mscaler_maskx_groups);
++		if(ret){
++			dev_err(mscaler->dev, "device create sys groups failed\n");
++			goto err_mask_create_groups;
++		}
++
++	}
++	return 0;
++err_mask_create_groups:
++err_mask_create_file:
++err_mask_ch_kobj:
++err_mask_kobj:
++err_subdev_register:
++err_alloc_pads:
++	return ret;
++}
++
++
++static void mscaler_comp_unbind(struct device *comp, struct device *master,
++                                 void *master_data)
++{
++        struct mscaler_device *mscaler = dev_get_drvdata(comp);
++
++	dev_info(comp, "----TODO: %p----%s, %d \n", mscaler, __func__, __LINE__);
++
++}
++
++static const struct component_ops mscaler_comp_ops = {
++        .bind = mscaler_comp_bind,
++        .unbind = mscaler_comp_unbind,
++};
++
++
++
++
++static int ingenic_mscaler_probe(struct platform_device *pdev)
++{
++
++	struct mscaler_device *mscaler = NULL;
++	int ret = 0;
++	int i = 0;
++
++	mscaler = kzalloc(sizeof(struct mscaler_device), GFP_KERNEL);
++	if(!mscaler) {
++		pr_err("Failed to alloc mscaler dev [%s]\n", pdev->name);
++		return -ENOMEM;
++	}
++
++	mscaler->dev = &pdev->dev;
++	platform_set_drvdata(pdev, mscaler);
++
++	spin_lock_init(&mscaler->lock);
++
++	for(i = 0; i < MSCALER_MAX_CH; i++) {
++		INIT_LIST_HEAD(&mscaler->dma_queued_list[i]);
++		INIT_LIST_HEAD(&mscaler->dma_pending_list[i]);
++	}
++
++	ret = sysfs_create_group(&mscaler->dev->kobj, &mscaler_debug_attr_group);
++	if (ret) {
++		dev_err(mscaler->dev, "device create sysfs group failed\n");
++
++		ret = -EINVAL;
++		goto err_sys_group;
++	}
++
++
++	ret = component_add(mscaler->dev, &mscaler_comp_ops);
++	if(ret < 0) {
++		dev_err(mscaler->dev, "Failed to add component mscaler!\n");
++	}
++
++	return 0;
++err_sys_group:
++	return ret;
++}
++
++
++
++static int ingenic_mscaler_remove(struct platform_device *pdev)
++{
++
++	return 0;
++}
++
++
++
++static const struct of_device_id ingenic_mscaler_dt_match[] = {
++        { .compatible = "ingenic,x2500-mscaler" },
++        { }
++};
++
++MODULE_DEVICE_TABLE(of, ingenic_mscaler_dt_match);
++
++static int __maybe_unused ingenic_mscaler_suspend(struct platform_device *pdev, pm_message_t state)
++{
++        return 0;
++}
++
++static int __maybe_unused ingenic_mscaler_resume(struct platform_device *pdev)
++{
++        return 0;
++}
++
++static struct platform_driver ingenic_mscaler_driver = {
++        .probe = ingenic_mscaler_probe,
++        .remove = ingenic_mscaler_remove,
++	.suspend = ingenic_mscaler_suspend,
++	.resume = ingenic_mscaler_resume,
++        .driver = {
++                .name = "ingenic-mscaler",
++                .of_match_table = ingenic_mscaler_dt_match,
++        },
++};
++
++module_platform_driver(ingenic_mscaler_driver);
++
++MODULE_ALIAS("platform:ingenic-mscaler");
++MODULE_DESCRIPTION("ingenic mscaler subsystem");
++MODULE_AUTHOR("qipengzhen <aric.pzqi@ingenic.com>");
++MODULE_LICENSE("GPL v2");
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/sensor.c b/module_drivers/drivers/media/platform/ingenic-isp-v2/sensor.c
+new file mode 100644
+index 000000000..e04dfe508
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/sensor.c
+@@ -0,0 +1,463 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++
++#include "isp-drv.h"
++
++#define to_sensor_device(isp) 	&isp->ispcam->sensor
++
++extern unsigned int MAIN_ISP_INDEX;
++extern unsigned int SEC_ISP_INDEX;
++
++extern struct isp_device *g_isp_device[2];
++struct isp_device *index_to_isp_device(int isp_index)
++{
++	if(isp_index == 0)
++		return g_isp_device[0];
++	else if(isp_index == 1)
++		return g_isp_device[1];
++	else{
++		printk("unsupported isp index!\n");
++		return NULL;
++	}
++}
++
++static void sensor_hw_reset_enable(void)
++{
++//	printk("----%s, %d\n", __func__, __LINE__);
++}
++
++static void sensor_hw_reset_disable(void)
++{
++//	printk("----%s, %d\n", __func__, __LINE__);
++}
++
++static int32_t sensor_alloc_analog_gain(int32_t gain, sensor_context_t *p_ctx)
++{
++	/* printk("result gain is 0x%x\n",again); */
++	return gain;
++}
++
++static int32_t sensor_alloc_analog_gain_short(int32_t gain, sensor_context_t *p_ctx)
++{
++	/* printk("result gain is 0x%x\n",again); */
++	return gain;
++}
++
++static int32_t sensor_alloc_digital_gain(int32_t gain, sensor_context_t *p_ctx)
++{
++//	printk("----%s, %d, gain: %d\n", __func__, __LINE__, gain);
++
++	/* printk("result gain is 0x%x\n",p_ctx->dgain); */
++	return gain;
++}
++
++static uint32_t sensor_alloc_integration_time(uint32_t int_time, sensor_context_t *p_ctx)
++{
++	p_ctx->it = int_time;
++	return int_time;
++}
++
++static uint32_t sensor_alloc_integration_time_short(uint32_t int_time, sensor_context_t *p_ctx)
++{
++	p_ctx->it_short = int_time;
++	return int_time;
++}
++
++static void sensor_set_integration_time(uint16_t int_time, sensor_param_t* param)
++{
++	int isp_index = -1;
++	struct isp_device *isp = NULL;
++	struct sensor_device *sensor = NULL;
++	struct v4l2_control exposure;
++	int ret = 0;
++
++	if(param->sensor_ctx.sensor_id == 0)
++		isp_index = MAIN_ISP_INDEX;
++	else if(param->sensor_ctx.sensor_id == 1)
++		isp_index = SEC_ISP_INDEX;
++	isp = index_to_isp_device(isp_index);
++	sensor = to_sensor_device(isp);
++
++	exposure.id = V4L2_CID_EXPOSURE;
++	exposure.value = int_time;
++
++	ret = v4l2_s_ctrl(NULL, sensor->isd->sd->ctrl_handler, &exposure);
++	if(ret < 0) {
++		dev_err(isp->dev, "failed to set exposure!\n");
++	}
++}
++
++static void sensor_set_integration_time_short(uint16_t int_time, sensor_param_t* param)
++{
++	int isp_index = -1;
++	struct isp_device *isp = NULL;
++	struct sensor_device *sensor = NULL;
++	struct v4l2_control exposure;
++	int ret = 0;
++
++	if(param->sensor_ctx.sensor_id == 0)
++		isp_index = MAIN_ISP_INDEX;
++	else if(param->sensor_ctx.sensor_id == 1)
++		isp_index = SEC_ISP_INDEX;
++	isp = index_to_isp_device(isp_index);
++	sensor = to_sensor_device(isp);
++
++	exposure.id = V4L2_CID_USER_EXPOSURE_SHORT;
++	exposure.value = int_time;
++
++	ret = v4l2_s_ctrl(NULL, sensor->isd->sd->ctrl_handler, &exposure);
++	if(ret < 0) {
++		dev_err(isp->dev, "failed to set exposure!\n");
++	}
++}
++
++static void sensor_set_analog_gain(uint32_t again_reg_val, sensor_context_t *p_ctx)
++{
++	int isp_index = -1;
++	struct isp_device *isp = NULL;
++	struct sensor_device *sensor = NULL;
++	struct v4l2_control analog;
++	int ret = 0;
++
++	if(p_ctx->sensor_id == 0)
++		isp_index = MAIN_ISP_INDEX;
++	else if(p_ctx->sensor_id == 1)
++		isp_index = SEC_ISP_INDEX;
++	isp = index_to_isp_device(isp_index);
++	sensor = to_sensor_device(isp);
++
++	analog.id = V4L2_CID_ANALOGUE_GAIN;
++	analog.value = again_reg_val;
++
++	ret = v4l2_s_ctrl(NULL, sensor->isd->sd->ctrl_handler, &analog);
++	if(ret < 0) {
++		printk("error s_ctrl, ret: %d\n", ret);
++	}
++}
++
++static void sensor_get_analog_gain(uint32_t *again_reg_val, sensor_context_t *p_ctx)
++{
++	int isp_index = -1;
++	struct isp_device *isp = NULL;
++	struct sensor_device *sensor = NULL;
++	struct v4l2_control analog;
++	int ret = 0;
++
++	if(p_ctx->sensor_id == 0)
++		isp_index = MAIN_ISP_INDEX;
++	else if(p_ctx->sensor_id == 1)
++		isp_index = SEC_ISP_INDEX;
++	isp = index_to_isp_device(isp_index);
++	sensor = to_sensor_device(isp);
++
++	analog.id = V4L2_CID_ANALOGUE_GAIN;
++	analog.value = 0;
++
++	ret = v4l2_g_ctrl(sensor->isd->sd->ctrl_handler, &analog);
++	if(ret < 0) {
++		printk("error s_ctrl, ret: %d\n", ret);
++	}
++
++
++	*again_reg_val = analog.value;
++}
++
++static void sensor_set_analog_gain_short(uint32_t again_reg_val, sensor_context_t *p_ctx)
++{
++	int isp_index = -1;
++	struct isp_device *isp = NULL;
++	struct sensor_device *sensor = NULL;
++	struct v4l2_control analog;
++	int ret = 0;
++
++	if(p_ctx->sensor_id == 0)
++		isp_index = MAIN_ISP_INDEX;
++	else if(p_ctx->sensor_id == 1)
++		isp_index = SEC_ISP_INDEX;
++	isp = index_to_isp_device(isp_index);
++	sensor = to_sensor_device(isp);
++
++	analog.id = V4L2_CID_USER_ANALOG_GAIN_SHORT;
++	analog.value = again_reg_val;
++
++	ret = v4l2_s_ctrl(NULL, sensor->isd->sd->ctrl_handler, &analog);
++	if(ret < 0) {
++		printk("error s_ctrl, ret: %d\n", ret);
++	}
++}
++
++static void sensor_get_analog_gain_short(uint32_t *again_reg_val, sensor_context_t *p_ctx)
++{
++	int isp_index = -1;
++	struct isp_device *isp = NULL;
++	struct sensor_device *sensor = NULL;
++	struct v4l2_control analog;
++	int ret = 0;
++
++	if(p_ctx->sensor_id == 0)
++		isp_index = MAIN_ISP_INDEX;
++	else if(p_ctx->sensor_id == 1)
++		isp_index = SEC_ISP_INDEX;
++	isp = index_to_isp_device(isp_index);
++	sensor = to_sensor_device(isp);
++
++	analog.id = V4L2_CID_USER_ANALOG_GAIN_SHORT;
++	analog.value = 0;
++
++	ret = v4l2_g_ctrl(sensor->isd->sd->ctrl_handler, &analog);
++	if(ret < 0) {
++		printk("error s_ctrl, ret: %d\n", ret);
++	}
++
++
++	*again_reg_val = analog.value;
++}
++
++static void sensor_set_digital_gain(uint32_t dgain_reg_val, sensor_context_t *p_ctx)
++{
++	int isp_index = -1;
++	struct isp_device *isp = NULL;
++	struct sensor_device *sensor = NULL;
++	struct v4l2_control control;
++	int ret = 0;
++
++	if(p_ctx->sensor_id == 0)
++		isp_index = MAIN_ISP_INDEX;
++	else if(p_ctx->sensor_id == 1)
++		isp_index = SEC_ISP_INDEX;
++	isp = index_to_isp_device(isp_index);
++	sensor = to_sensor_device(isp);
++
++	control.id = V4L2_CID_GAIN;
++	control.value = dgain_reg_val;
++
++	ret = v4l2_s_ctrl(NULL, sensor->isd->sd->ctrl_handler, &control);
++	if(ret < 0) {
++		printk("error s_ctrl, ret: %d\n", ret);
++	}
++}
++
++#if 0
++static int sensor_get_digital_gain(uint32_t *dgain_reg_val, sensor_context_t *p_ctx)
++{
++	int isp_index = -1;
++	struct isp_device *isp = NULL;
++	struct sensor_device *sensor = NULL;
++	struct v4l2_control control;
++	int ret = 0;
++
++	if(p_ctx->sensor_id == 0)
++		isp_index = MAIN_ISP_INDEX;
++	else if(p_ctx->sensor_id == 1)
++		isp_index = SEC_ISP_INDEX;
++	isp = index_to_isp_device(isp_index);
++	sensor = to_sensor_device(isp);
++
++	control.id = V4L2_CID_GAIN;
++	control.value = 0;
++
++	ret = v4l2_g_ctrl(sensor->isd->sd->ctrl_handler, &control);
++	if(ret < 0) {
++		printk("error s_ctrl, ret: %d\n", ret);
++	}
++
++	*dgain_reg_val = control.value;
++
++	return ret;
++}
++#endif
++
++#if 1
++static uint16_t sensor_get_normal_fps(sensor_param_t* param)
++{
++//	printk("----%s, %d\n", __func__, __LINE__);
++	return 0;
++}
++
++static uint16_t sensor_read_black_pedestal(int i,uint32_t gain)
++{
++//	printk("----%s, %d\n", __func__, __LINE__);
++	return 0;
++}
++
++static void sensor_set_mode(uint8_t mode, sensor_param_t* param)
++{
++//	printk("----%s, %d\n", __func__, __LINE__);
++}
++
++static void sensor_start_changes(sensor_context_t *p_ctx)
++{
++//	printk("----%s, %d\n", __func__, __LINE__);
++}
++
++static void sensor_end_changes(sensor_context_t *p_ctx)
++{
++//	printk("----%s, %d\n", __func__, __LINE__);
++}
++
++
++static uint16_t sensor_get_id(sensor_context_t *p_ctx)
++{
++//	printk("----%s, %d\n", __func__, __LINE__);
++
++	return 0;
++}
++
++static void sensor_set_wdr_mode(uint8_t mode, sensor_param_t* param)
++{
++//	printk("----%s, %d\n", __func__, __LINE__);
++}
++
++static uint32_t sensor_fps_control(uint8_t fps, sensor_param_t* param)
++{
++
++//	printk("----%s, %d\n", __func__, __LINE__);
++	return 0;
++}
++
++static void sensor_disable_isp(sensor_context_t *p_ctx)
++{
++//	printk("----%s, %d\n", __func__, __LINE__);
++}
++
++static uint32_t sensor_get_lines_per_second(sensor_param_t* param)
++{
++	uint32_t lines_per_second=0;
++//	printk("----%s, %d\n", __func__, __LINE__);
++	return lines_per_second;
++}
++#endif
++
++
++extern tisp_init_par_t tisp_par_info;
++void sensor_init(sensor_control_t *ctrl, int vinum)
++{
++	struct isp_device *isp = NULL;
++	struct sensor_device *sensor = NULL;
++	struct v4l2_queryctrl query;
++	tisp_init_param_t *sensor_info = &tisp_par_info.sensor[vinum];
++	int ret = 0;
++	int isp_index = -1;
++
++	if(vinum == 0)
++		isp_index = MAIN_ISP_INDEX;
++	else if(vinum == 1)
++		isp_index = SEC_ISP_INDEX;
++
++	isp = g_isp_device[isp_index];
++	sensor = to_sensor_device(isp);
++
++	query.id = V4L2_CID_EXPOSURE;
++	query.type = V4L2_CTRL_TYPE_INTEGER;
++	ret = v4l2_queryctrl(sensor->isd->sd->ctrl_handler, &query);
++	if(ret < 0) {
++		dev_err(isp->dev, "query sensor V4L2_CID_EXPOSURE failed\n");
++	}
++
++	ctrl->param[vinum].integration_time_min = query.minimum;
++	ctrl->param[vinum].integration_time_max = query.maximum;
++
++	query.id = V4L2_CID_USER_EXPOSURE_SHORT;
++	query.type = V4L2_CTRL_TYPE_INTEGER;
++	ret = v4l2_queryctrl(sensor->isd->sd->ctrl_handler, &query);
++	if(ret < 0) {
++		dev_err(isp->dev, "query sensor V4L2_CID_USER_EXPOSURE_SHORT failed\n");
++	}
++
++	ctrl->param[vinum].integration_time_min_short = query.minimum;
++	ctrl->param[vinum].integration_time_max_short = query.maximum;
++
++	query.id = V4L2_CID_ANALOGUE_GAIN;
++	query.type = V4L2_CTRL_TYPE_INTEGER;
++	ret = v4l2_queryctrl(sensor->isd->sd->ctrl_handler, &query);
++	if(ret < 0) {
++		dev_err(isp->dev, "query sensor V4L2_CID_ANALOGUE_GAIN failed\n");
++	}
++	ctrl->param[vinum].again_log2_max = query.maximum;
++
++	query.id = V4L2_CID_USER_ANALOG_GAIN_SHORT;
++	query.type = V4L2_CTRL_TYPE_INTEGER;
++	ret = v4l2_queryctrl(sensor->isd->sd->ctrl_handler, &query);
++	if(ret < 0) {
++		dev_err(isp->dev, "query sensor V4L2_CID_USER_ANALOG_GAIN failed\n");
++	}
++	ctrl->param[vinum].again_log2_max_short = query.maximum;
++
++
++	query.id = V4L2_CID_GAIN;
++	query.type = V4L2_CTRL_TYPE_INTEGER;
++	ret = v4l2_queryctrl(sensor->isd->sd->ctrl_handler, &query);
++	if(ret < 0) {
++		dev_err(isp->dev, "queyr sensor V4L2_CID_GAIN failed\n");
++	}
++	ctrl->param[vinum].dgain_log2_max = query.maximum;
++
++#if 1
++	/*fill sensor_info*/
++	sensor_info->sensor_info.max_again = ctrl->param[vinum].again_log2_max;       //the format is .16
++	sensor_info->sensor_info.max_again_short = ctrl->param[vinum].again_log2_max_short;       //the format is .16
++	sensor_info->sensor_info.max_dgain = ctrl->param[vinum].dgain_log2_max;      //the format is .16
++// 	sensor_info->sensor_info.again = core->vin.attr->again;
++// 	sensor_info->sensor_info.dgain = core->vin.attr->dgain;
++// 	sensor_info->sensor_info.fps = core->vin.fps;
++	sensor_info->sensor_info.min_integration_time = ctrl->param[vinum].integration_time_min;
++	sensor_info->sensor_info.max_integration_time = ctrl->param[vinum].integration_time_max;
++	sensor_info->sensor_info.min_integration_time_short = ctrl->param[vinum].integration_time_min_short;
++	sensor_info->sensor_info.max_integration_time_short = ctrl->param[vinum].integration_time_max_short;
++// 	sensor_info->sensor_info.min_integration_time_native = core->vin.attr->min_integration_time_native;
++// 	sensor_info->sensor_info.max_integration_time_native = core->vin.attr->max_integration_time_native;
++// 	sensor_info->sensor_info.integration_time_limit = core->vin.attr->integration_time_limit;
++// 	sensor_info->sensor_info.integration_time = core->vin.attr->integration_time;
++// 	sensor_info->sensor_info.total_width = core->vin.attr->total_width;
++// 	sensor_info->sensor_info.total_height = core->vin.attr->total_height;
++// 	sensor_info->sensor_info.integration_time_apply_delay = core->vin.attr->integration_time_apply_delay;
++// 	sensor_info->sensor_info.again_apply_delay = core->vin.attr->again_apply_delay;
++// 	sensor_info->sensor_info.dgain_apply_delay = core->vin.attr->dgain_apply_delay;
++//	sensor_info->sensor_info.one_line_expr_in_us = core->vin.attr->one_line_expr_in_us;
++#endif
++
++	ctrl->hw_reset_disable = sensor_hw_reset_disable;
++	ctrl->hw_reset_enable = sensor_hw_reset_enable;
++	ctrl->alloc_analog_gain = sensor_alloc_analog_gain;
++	ctrl->alloc_analog_gain_short = sensor_alloc_analog_gain_short;
++	ctrl->alloc_digital_gain = sensor_alloc_digital_gain;
++	ctrl->alloc_integration_time = sensor_alloc_integration_time;
++	ctrl->alloc_integration_time_short = sensor_alloc_integration_time_short;
++	ctrl->set_integration_time = sensor_set_integration_time;
++	ctrl->set_integration_time_short = sensor_set_integration_time_short;
++	ctrl->start_changes = sensor_start_changes;
++	ctrl->end_changes = sensor_end_changes;
++	ctrl->set_analog_gain = sensor_set_analog_gain;
++	ctrl->get_analog_gain = sensor_get_analog_gain;
++	ctrl->set_analog_gain_short = sensor_set_analog_gain_short;
++	ctrl->get_analog_gain_short = sensor_get_analog_gain_short;
++	ctrl->set_digital_gain = sensor_set_digital_gain;
++	ctrl->get_normal_fps = sensor_get_normal_fps;
++	ctrl->read_black_pedestal = sensor_read_black_pedestal;
++	ctrl->set_mode = sensor_set_mode;
++	ctrl->set_wdr_mode = sensor_set_wdr_mode;
++	ctrl->fps_control = sensor_fps_control;
++	ctrl->get_id = sensor_get_id;
++	ctrl->disable_isp = sensor_disable_isp;
++	ctrl->get_lines_per_second = sensor_get_lines_per_second;
++}
++
++
++int sensor_device_probe(struct sensor_device *sensor, struct ispcam_device *ispcam)
++{
++	int ret = 0;
++	sensor->ispcam = ispcam;
++	sensor->isp = ispcam->isp;
++	sensor->isd = &ispcam->isd[0];
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(sensor_device_probe);
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/tx-vic-regs.h b/module_drivers/drivers/media/platform/ingenic-isp-v2/tx-vic-regs.h
+new file mode 100755
+index 000000000..012c6e1b3
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/tx-vic-regs.h
+@@ -0,0 +1,182 @@
++#ifndef __VIC_REG_H__
++#define __VIC_REG_H__
++
++#define VIC_BASE(n)                                  (0x0 + 0x00000 + n * 0x10000)
++
++//#define VIC_DB_CFG                                  0x10
++#define DVP_DATA_POS                                (1<<24)
++#define DVP_RGB_ORDER                               (1<<21)
++#define DVP_RAW_ALIG                                (1<<20)
++#define DVP_DATA_TYPE                               (17)
++#define DVP_RAW8                                    (0<<DVP_DATA_TYPE)
++#define DVP_RAW10                                   (1<<DVP_DATA_TYPE)
++#define DVP_RAW12                                   (2<<DVP_DATA_TYPE)
++#define DVP_YUV422_16BIT                            (3<<DVP_DATA_TYPE)
++#define DVP_RGB565_16BIT                            (4<<DVP_DATA_TYPE)
++#define DVP_BRG565_16BIT                            (5<<DVP_DATA_TYPE)
++#define DVP_YUV422_8BIT                             (6<<DVP_DATA_TYPE)
++#define DVP_RGB565_8BIT                             (7<<DVP_DATA_TYPE)
++
++#define DVP_TIMEING_MODE                            (1<<15)
++#define DVP_SONY_MODE                               (2 << 15)
++#define BT_INTF_WIDE                                (1<<11)
++#define BT_LINE_MODE                                (1<<10)
++#define BT_601_TIMING_MODE                          (1<<9)
++#define YUV_DATA_ORDER                              (4)
++#define UYVY                                        (0<<YUV_DATA_ORDER)
++#define VYUY                                        (1<<YUV_DATA_ORDER)
++#define YUYV                                        (2<<YUV_DATA_ORDER)
++#define YVYU                                        (3<<YUV_DATA_ORDER)
++#define FIRST_FIELD_TYPE                            (1<<3)
++#define INTERLACE_EN                                (1<<2)
++#define HSYN_POLAR                                  (1<<1)
++#define VSYN_POLAR                                  (1<<0)
++
++//#define VIC_HCNT0                                   0x04
++//#define VIC_HCNT1                                   0x08
++
++
++//#define VIC_FRM_ECC                                0x08
++#define FRAME_ECC_EN                               (1<<0)
++#define FRAME_ECC_MODE                             (1<<1)
++//#define VIC_INTF_TYPE                              0x0C
++#define INTF_TYPE_BT656                            0x0
++#define INTF_TYPE_BT601                            0x1
++#define INTF_TYPE_MIPI                             0x2
++#define INTF_TYPE_DVP                              0x3
++#define INTF_TYPE_BT1120                           0x4
++
++//#define VIC_RESOLUTION                             0x04
++#define H_RESOLUTION                               (1<<16)
++#define V_RESOLUTION                               (1)
++
++
++//#define VIC_IDI_TYPE                               (0x14)/* VIC_INPUT_MIPI */
++#define MIPI_RAW8                                  0x0
++#define MIPI_RAW10                                 0x1
++#define MIPI_RAW12                                 0x2
++#define MIPI_RGB555                                0x3
++#define MIPI_RGB565                                0x4
++#define MIPI_RGB666                                0x5
++#define MIPI_RGB888                                0x6
++#define MIPI_YUV422                                0x7
++#define MIPI_YUV422_10BIT                          0x8
++
++//#define VIC_AB_VALUE                               (0x18)
++#define A_VALUE                                    (1<<16)
++#define B_VALUE                                    (1)
++
++//#define VIC_GLOBAL_CFG                             (0x50)
++#define ISP_PRESET_MODE1                           (0<<5)
++#define ISP_PRESET_MODE2                           (1<<5)
++#define ISP_PRESET_MODE3                           (2<<5)
++#define VCKE_EN                                    (1<<4)
++#define BLANK_EN                                   (2)
++#define AB_MODE_SELECT                             (0)
++
++#//define VIC_CONTROL                                (0x0)
++#define VIC_RESET                                  (1<<4)
++#define GLB_SAFE_RST                               (1<<3)
++#define GLB_RST                                    (1<<2)
++#define REG_ENABLE                                 (1<<1)
++#define VIC_SRART                                  (1<<0)
++
++#define    HCROP_DIFF_EN                                     25
++#define    VCOMP_EN                                          24
++#define    HCOMP_EN                                          23
++#define    LINE_SYNC_MODE                                    22
++#define    WORK_START_FLAG                                   20
++#define    DATA_TYPE_EN                                      18
++#define    DATA_TYPE_VALUE                                   12
++#define    DEL_START                                         8
++#define    SENSOR_FRM_NUM                                    4
++#define    SENSOR_FID_MODE                                   2
++#define    SENSOR_MODE                                       0
++
++#define VIC_DMA_OUTPUT_MAX_WIDTH                   3840
++
++
++
++#define VIC_ADDR_VIC_CTRL(n)                                  (VIC_BASE(n) + 0x0000)
++#define VIC_ADDR_VIC_RES(n)                                   (VIC_BASE(n) + 0x0004)
++#define VIC_ADDR_VIC_FRM_ECC(n)                               (VIC_BASE(n) + 0x0008)
++#define VIC_ADDR_VIC_IN_INTF(n)                               (VIC_BASE(n) + 0x000c)
++#define VIC_ADDR_VIC_IN_DVP(n)                                (VIC_BASE(n) + 0x0010)
++#define VIC_ADDR_VIC_IN_CSI_FMT(n)                            (VIC_BASE(n) + 0x0014)
++#define VIC_ADDR_VIC_IN_HOR_PARA0(n)                          (VIC_BASE(n) + 0x0018)
++#define VIC_ADDR_VIC_IN_HOR_PARA1(n)                          (VIC_BASE(n) + 0x001c)
++#define VIC_ADDR_VIC_IN_VER_PARA0(n)                          (VIC_BASE(n) + 0x0030)
++#define VIC_ADDR_VIC_IN_VER_PARA1(n)                          (VIC_BASE(n) + 0x0034)
++#define VIC_ADDR_VIC_IN_VER_PARA2(n)                          (VIC_BASE(n) + 0x0038)
++#define VIC_ADDR_VIC_IN_VER_PARA3(n)                          (VIC_BASE(n) + 0x003c)
++#define VIC_ADDR_VIC_VLD_LINE_SAV(n)                          (VIC_BASE(n) + 0x0060)
++#define VIC_ADDR_VIC_VLD_LINE_EAV(n)                          (VIC_BASE(n) + 0x0064)
++#define VIC_ADDR_VIC_VLD_FRM_SAV(n)                           (VIC_BASE(n) + 0x0070)
++#define VIC_ADDR_VIC_VLD_FRM_EAV(n)                           (VIC_BASE(n) + 0x0074)
++#define VIC_ADDR_VIC_VC_CONTROL(n)                            (VIC_BASE(n) + 0x008c)
++#define VIC_ADDR_VIC_VC_CONTROL_CH0_PIX(n)                    (VIC_BASE(n) + 0x0090)
++#define VIC_ADDR_VIC_VC_CONTROL_CH1_PIX(n)                    (VIC_BASE(n) + 0x0094)
++#define VIC_ADDR_VIC_VC_CONTROL_CH2_PIX(n)                    (VIC_BASE(n) + 0x0098)
++#define VIC_ADDR_VIC_VC_CONTROL_CH3_PIX(n)                    (VIC_BASE(n) + 0x009c)
++#define VIC_ADDR_VIC_VC_CONTROL_CH0_LINE(n)                   (VIC_BASE(n) + 0x00a0)
++#define VIC_ADDR_VIC_VC_CONTROL_CH1_LINE(n)                   (VIC_BASE(n) + 0x00a4)
++#define VIC_ADDR_VIC_VC_CONTROL_CH2_LINE(n)                   (VIC_BASE(n) + 0x00a8)
++#define VIC_ADDR_VIC_VC_CONTROL_CH3_LINE(n)                   (VIC_BASE(n) + 0x00ac)
++#define VIC_ADDR_VIC_VC_CONTROL_FIFO_USE(n)                   (VIC_BASE(n) + 0x00b0)
++#define VIC_ADDR_MIPI_ALL_WIDTH_4BYTE(n)                      (VIC_BASE(n) + 0x0100)
++#define VIC_ADDR_MIPI_VCROP_DEL01(n)                          (VIC_BASE(n) + 0x0104)
++#define VIC_ADDR_MIPI_VCROP_DEL23(n)                          (VIC_BASE(n) + 0x0108)
++#define VIC_ADDR_MIPI_SENSOR_CONTROL(n)                       (VIC_BASE(n) + 0x010c)
++#define VIC_ADDR_MIPI_HCROP_CH0(n)                            (VIC_BASE(n) + 0x0110)
++#define VIC_ADDR_MIPI_HCROP_CH1(n)                            (VIC_BASE(n) + 0x0114)
++#define VIC_ADDR_MIPI_HCROP_CH2(n)                            (VIC_BASE(n) + 0x0118)
++#define VIC_ADDR_MIPI_HCROP_CH3(n)                            (VIC_BASE(n) + 0x011c)
++#define VIC_ADDR_VC_CONTROL_CONTROL(n)                        (VIC_BASE(n) + 0x01a0)
++#define VIC_ADDR_VC_CONTROL_DELEY(n)                          (VIC_BASE(n) + 0x01a4)
++#define VIC_ADDR_VC_CONTROL_TIZIANO_ROUTE(n)                  (VIC_BASE(n) + 0x01a8)
++#define VIC_ADDR_VC_CONTROL_DMAOUT_ROUTE(n)                   (VIC_BASE(n) + 0x01ac)
++#define VIC_ADDR_VC_CONTROL_DELEY_BLK(n)                      (VIC_BASE(n) + 0x01b0)
++#define VIC_ADDR_VC_CONTROL_LIMIT(n)                          (VIC_BASE(n) + 0x01b4)
++#define VIC_ADDR_VIC_INT_STATU(n)                             (VIC_BASE(n) + 0x01e0)
++#define VIC_ADDR_VIC_INT_STATU2(n)                            (VIC_BASE(n) + 0x01e4)
++#define VIC_ADDR_VIC_INT_MASK(n)                              (VIC_BASE(n) + 0x01e8)
++#define VIC_ADDR_VIC_INT_MASK2(n)                             (VIC_BASE(n) + 0x01ec)
++#define VIC_ADDR_VIC_INT_CLR(n)                               (VIC_BASE(n) + 0x01f0)
++#define VIC_ADDR_VIC_INT_CLR2(n)                              (VIC_BASE(n) + 0x01f4)
++#define VIC_ADDR_DMA_CONFIGURE(n)                             (VIC_BASE(n) + 0x0300)
++#define VIC_ADDR_DMA_RESOLUTION(n)                            (VIC_BASE(n) + 0x0304)
++#define VIC_ADDR_DMA_RESET(n)                                 (VIC_BASE(n) + 0x0308)
++#define VIC_ADDR_DMA_Y_CH_STRIDE(n)                           (VIC_BASE(n) + 0x0310)
++#define VIC_ADDR_DMA_UV_CH_STRIDE(n)                          (VIC_BASE(n) + 0x0314)
++#define VIC_ADDR_DMA_Y_CH0_BANK0_ADDR(n)                      (VIC_BASE(n) + 0x0318)
++#define VIC_ADDR_DMA_Y_CH0_BANK1_ADDR(n)                      (VIC_BASE(n) + 0x031c)
++#define VIC_ADDR_DMA_Y_CH0_BANK2_ADDR(n)                      (VIC_BASE(n) + 0x0320)
++#define VIC_ADDR_DMA_Y_CH0_BANK3_ADDR(n)                      (VIC_BASE(n) + 0x0324)
++#define VIC_ADDR_DMA_Y_CH0_BANK4_ADDR(n)                      (VIC_BASE(n) + 0x0328)
++#define VIC_ADDR_DMA_UV_CH0_BANK0_ADDR(n)                     (VIC_BASE(n) + 0x032c)
++#define VIC_ADDR_DMA_UV_CH0_BANK1_ADDR(n)                     (VIC_BASE(n) + 0x0330)
++#define VIC_ADDR_DMA_UV_CH0_BANK2_ADDR(n)                     (VIC_BASE(n) + 0x0334)
++#define VIC_ADDR_DMA_UV_CH0_BANK3_ADDR(n)                     (VIC_BASE(n) + 0x0338)
++#define VIC_ADDR_DMA_UV_CH0_BANK4_ADDR(n)                     (VIC_BASE(n) + 0x033c)
++#define VIC_ADDR_DMA_Y_CH1_BANK0_ADDR(n)                      (VIC_BASE(n) + 0x0340)
++#define VIC_ADDR_DMA_Y_CH1_BANK1_ADDR(n)                      (VIC_BASE(n) + 0x0344)
++#define VIC_ADDR_DMA_Y_CH1_BANK2_ADDR(n)                      (VIC_BASE(n) + 0x0348)
++#define VIC_ADDR_DMA_Y_CH1_BANK3_ADDR(n)                      (VIC_BASE(n) + 0x034c)
++#define VIC_ADDR_DMA_Y_CH1_BANK4_ADDR(n)                      (VIC_BASE(n) + 0x0350)
++#define VIC_ADDR_DMA_UV_CH1_BANK0_ADDR(n)                     (VIC_BASE(n) + 0x0354)
++#define VIC_ADDR_DMA_UV_CH1_BANK1_ADDR(n)                     (VIC_BASE(n) + 0x0358)
++#define VIC_ADDR_DMA_UV_CH1_BANK2_ADDR(n)                     (VIC_BASE(n) + 0x035c)
++#define VIC_ADDR_DMA_UV_CH1_BANK3_ADDR(n)                     (VIC_BASE(n) + 0x0360)
++#define VIC_ADDR_DMA_UV_CH1_BANK4_ADDR(n)                     (VIC_BASE(n) + 0x0364)
++#define VIC_ADDR_DMA_Y_CH0_ADDR(n)                            (VIC_BASE(n) + 0x0380)
++#define VIC_ADDR_DMA_UV_CH0_ADDR(n)                           (VIC_BASE(n) + 0x0384)
++#define VIC_ADDR_DMA_Y_CH1_ADDR(n)                            (VIC_BASE(n) + 0x0388)
++#define VIC_ADDR_DMA_UV_CH1_ADDR(n)                           (VIC_BASE(n) + 0x038c)
++#define VIC_ADDR_VC_CONTROL_INPUT_MUX_OUTROUTE(n)             (VIC_BASE(n) + 0x01c0)
++
++#define INPUT_MXU_MIPI_EN                                     (1 << 0)
++#define INPUT_MXU_OUT                                         (1 << 1)
++#define INPUT_MXU_DVP_EN                                      (1 << 4)
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/vic-regs.h b/module_drivers/drivers/media/platform/ingenic-isp-v2/vic-regs.h
+new file mode 100644
+index 000000000..ed7c728f9
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/vic-regs.h
+@@ -0,0 +1,174 @@
++#ifndef __INGENIC_ISP_VIC_REG_H__
++#define __INGENIC_ISP_VIC_REG_H__
++
++#define VIC_CONTROL			0x00
++#define VIC_RESOLUTION	 		0x04
++#define VIC_FRM_ECC                     0x08
++#define VIC_INTF_TYPE                   0x0C
++#define VIC_IN_DVP			0x10
++#define VIC_IN_CSI_FMT                  0x14
++#define VIC_IN_HOR_PARA0                0x18
++#define VIC_IN_HOR_PARA1                0x1C
++#define VIC_IN_VER_PARA0                0x30
++#define VIC_IN_VER_PARA1                0x34
++#define VIC_IN_VER_PARA2                0x38
++#define VIC_IN_VER_PARA3                0x3C
++#define VIC_VLD_LINE_SAV		0x60
++#define VIC_VLD_LINE_EAV		0x64
++#define VIC_VLD_FRM_SAV			0x70
++#define VIC_VLD_FRM_EAV			0x74
++#define VIC_VC_CONTROL			0x8C
++#define VIC_VC_CONTROL_CH0_PIX		0x90
++#define VIC_VC_CONTROL_CH1_PIX		0x94
++#define VIC_VC_CONTROL_CH2_PIX		0x98
++#define VIC_VC_CONTROL_CH3_PIX		0x9C
++#define VIC_VC_CONTROL_CH0_LINE		0xA0
++#define VIC_VC_CONTROL_CH1_LINE		0xA4
++#define VIC_VC_CONTROL_CH2_LINE		0xA8
++#define VIC_VC_CONTROL_CH3_LINE		0xAC
++#define VIC_VC_CONTROL_FIFO_USE		0xB0
++#define MIPI_ALL_WIDTH_4BYTE		0x100
++#define MIPI_VCROP_DEL01		0x104
++#define MIPI_VCROP_DEL23		0x108
++#define MIPI_SENSOR_CONTROL		0x10C
++#define MIPI_HCROP_CH0			0x110
++#define MIPI_HCROP_CH1          0x114
++#define MIPI_HCROP_CH2          0x118
++#define MIPI_HCROP_CH3          0x11c
++#define VIC_CONTROL_CONTROL		0x1A0
++#define VIC_CONTROL_DELAY		0x1A4
++#define VIC_CONTROL_TIZIANO_ROUTE	0x1A8
++#define VIC_CONTROL_DMA_ROUTE		0x1AC
++#define VIC_CONTROL_DELEY_BLK       0x1B0
++#define VIC_CONTROL_LIMIT           0x1B4
++#define VIC_CONTROL_INPUT_MUX_OUTROUTE             0x01C0
++#define VIC_INT_STA			0X1E0
++#define VIC_INT_STA2			0X1E4
++#define VIC_INT_MASK			0x1E8
++#define VIC_INT_MASK2			0x1EC
++#define VIC_INT_CLR			0x1F0
++#define VIC_INT_CLR2			0x1F4
++/*DMA register*/
++#define VIC_DMA_OUTPUT_MAX_WIDTH 2688
++#define VIC_DMA_CONFIG			0x300
++#define VIC_DMA_RESOLUTION		0x304
++#define VIC_DMA_RESET			0x308
++#define VIC_DMA_Y_STRID			0x310
++#define VIC_DMA_UV_STRID		0x314
++#define VIC_DMA_Y_CH0_BUF0			0x318
++#define VIC_DMA_Y_CH0_BUF1			0x31c
++#define VIC_DMA_Y_CH0_BUF2			0x320
++#define VIC_DMA_Y_CH0_BUF3			0x324
++#define VIC_DMA_Y_CH0_BUF4			0x328
++#define VIC_DMA_UV_CH0_BUF0			0x32c
++#define VIC_DMA_UV_CH0_BUF1			0x330
++#define VIC_DMA_UV_CH0_BUF2			0x334
++#define VIC_DMA_UV_CH0_BUF3			0x338
++#define VIC_DMA_UV_CH0_BUF4			0x33c
++#define VIC_DMA_Y_CH1_BUF0			0x340
++#define VIC_DMA_Y_CH1_BUF1			0x344
++#define VIC_DMA_Y_CH1_BUF2			0x348
++#define VIC_DMA_Y_CH1_BUF3			0x34c
++#define VIC_DMA_Y_CH1_BUF4			0x350
++#define VIC_DMA_UV_CH1_BUF0			0x354
++#define VIC_DMA_UV_CH1_BUF1			0x358
++#define VIC_DMA_UV_CH1_BUF2			0x35c
++#define VIC_DMA_UV_CH1_BUF3			0x360
++#define VIC_DMA_UV_CH1_BUF4			0x364
++
++/*TIMESTAMP registers*/
++#define VIC_TS_ENABLE			0x360	/* 控制使能*/
++    #define TS_COUNTER_EN			(1 << 0)/*使能计数器*/
++    #define TS_VIC_DMA_EN			(1 << 4)/*使能VIC DMA的timstsamp*/
++    #define TS_MS_CH0_EN			(1 << 5)/*使能MSCALER CH0 ts*/
++    #define TS_MS_CH1_EN			(1 << 6)/*使能MSCALER CH1 ts*/
++    #define TS_MS_CH2_EN			(1 << 7)/*使能MSCALER CH2 ts*/
++#define VIC_TS_COUNTER			0x368	/* 多少个ISP时钟周期计数一次 */
++/* timestamp 写入到帧数�中的�移�置.*/
++#define VIC_TS_DMA_OFFSET		0x370
++#define VIC_TS_MS_CH0_OFFSET		0x374
++#define VIC_TS_MS_CH1_OFFSET		0x378
++#define VIC_TS_MS_CH2_OFFSET		0x37c
++
++
++#define    HCROP_DIFF_EN                                     25
++#define    VCOMP_EN                                          24
++#define    HCOMP_EN                                          23
++#define    LINE_SYNC_MODE                                    22
++#define    WORK_START_FLAG                                   20
++#define    DATA_TYPE_EN                                      18
++#define    DATA_TYPE_VALUE                                   12
++#define    DEL_START                                         8
++#define    SENSOR_FRM_NUM                                    4
++#define    SENSOR_FID_MODE                                   2
++#define    SENSOR_MODE                                       0
++
++
++
++/*VIC_CONTROL*/
++//#define VIC_RESET			(1<<4)
++#define GLB_RST				(1<<2)
++#define REG_ENABLE			(1<<1)
++#define VIC_START			(1<<0)
++
++/*VIC_RESOLUTION*/
++#define H_RESOLUTION			(1<<16)
++#define V_RESOLUTION			(1)
++
++/*VIC_FRM_ECC*/
++#define FRAME_ECC_EN		       (1<<0)
++#define FRAME_ECC_MODE		       (1<<1)
++
++/*VIC_INTF_TYPE*/
++#define INTF_TYPE_BT656			0x0
++#define INTF_TYPE_BT601			0x1
++#define INTF_TYPE_MIPI			0x2
++#define INTF_TYPE_DVP			0x3
++#define INTF_TYPE_BT1120		0x4
++
++/*VIC_IN_DVP*/
++#define DVP_DATA_POS			(1<<24)
++#define DVP_RGB_ORDER			(1<<21)
++#define DVP_RAW_ALIG			(1<<20)
++#define DVP_DATA_TYPE			(17)
++#define DVP_RAW8			(0<<DVP_DATA_TYPE)
++#define DVP_RAW10			(1<<DVP_DATA_TYPE)
++#define DVP_RAW12			(2<<DVP_DATA_TYPE)
++#define DVP_YUV422_16BIT		(3<<DVP_DATA_TYPE)
++//#define DVP_RGB565_16BIT		(4<<DVP_DATA_TYPE)
++//#define DVP_BRG565_16BIT		(5<<DVP_DATA_TYPE)
++#define DVP_YUV422_8BIT			(6<<DVP_DATA_TYPE)
++//#define DVP_RGB565_8BIT			(7<<DVP_DATA_TYPE)
++#define DVP_TIMEING_MODE		(1<<15)
++#define DVP_HSYNC_MODE			(1 << 15)
++#define DVP_SONY_MODE			(2 << 15)
++#define BT_INTF_WIDE			(1<<11)
++#define BT_LINE_MODE			(1<<10)
++#define BT_601_TIMING_MODE		(1<<9)
++#define YUV_DATA_ORDER			(4)
++#define YVYU				(0<<YUV_DATA_ORDER)
++#define YUYV				(1<<YUV_DATA_ORDER)
++#define VYUY				(2<<YUV_DATA_ORDER)
++#define UYVY				(3<<YUV_DATA_ORDER)
++#define FIRST_FIELD_TYPE		(1<<3)
++#define INTERLACE_EN			(1<<2)
++#define HSYN_POLAR			(1<<1)
++#define VSYN_POLAR			(1<<0)
++
++/*VIC_IN_CSI_FMT*/
++#define MIPI_RAW8			0x0
++#define MIPI_RAW10			0x1
++#define MIPI_RAW12			0x2
++//#define MIPI_RGB555			0x3
++//#define MIPI_RGB565			0x4
++//#define MIPI_RGB666			0x5
++//#define MIPI_RGB888			0x6
++#define MIPI_YUV422			0x7
++//#define MIPI_YUV422_10BIT		0x8
++
++/*INPUT_MUX_OUTROUTE*/
++#define INPUT_MXU_MIPI_EN		(1 << 0)
++#define INPUT_MXU_OUT			(1 << 1)
++#define INPUT_MXU_DVP_EN		(1 << 4)
++
++#endif/* __VIC_REG_H__ */
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp-v2/vic.c b/module_drivers/drivers/media/platform/ingenic-isp-v2/vic.c
+new file mode 100644
+index 000000000..359f5699a
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp-v2/vic.c
+@@ -0,0 +1,1486 @@
++#include <linux/clk.h>
++#include <linux/media-bus-format.h>
++#include <linux/media.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_graph.h>
++#include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
++#include <linux/pm_domain.h>
++#include <linux/slab.h>
++#include <linux/videodev2.h>
++#include <linux/component.h>
++#include <linux/clk.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/kthread.h>
++#include <linux/delay.h>
++
++#include <media/media-device.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-event.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++#include <media/ingenic_video_nr.h>
++
++#include "isp-drv.h"
++#include "vic-regs.h"
++
++#define VIC_STOP_BUFFER_COUNT 2
++#define VIC_RESTART_BUFFER_COUNT 3
++
++int count_period = 256;
++module_param(count_period, int, S_IRUGO);
++MODULE_PARM_DESC(count_period, "vic counter period");
++
++int vic_stop_counter = 0;
++module_param(vic_stop_counter, int, S_IRUGO);
++MODULE_PARM_DESC(vic_stop_counter, "vic0 bypass mode stop counter");
++
++int dma_debug_en = 0;
++module_param(dma_debug_en, int, 0664);
++MODULE_PARM_DESC(dma_debug_en, "vic dma debug mode enable");
++
++struct isp_video_format vic_mipi_formats[] = {
++	/*yuv420*/
++	{
++		.name     = "NV12, Y/CbCr 4:2:0",
++		.fourcc   = V4L2_PIX_FMT_NV12,
++		.depth    = {8, 4},
++		.num_planes = 2,
++		.mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	{
++		.name     = "NV21, Y/CbCr 4:2:0",
++		.fourcc   = V4L2_PIX_FMT_NV21,
++		.depth    = {8, 4},
++		.num_planes = 2,
++		.mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++
++	/*yuv422 */
++	{
++		.name     = "YUV422, YUYV",
++		.fourcc   = V4L2_PIX_FMT_YUYV,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	{
++		.name     = "YUV422, YVYU",
++		.fourcc   = V4L2_PIX_FMT_YVYU,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	{
++		.name     = "YUV422, UYVY",
++		.fourcc   = V4L2_PIX_FMT_UYVY,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	{
++		.name     = "YUV422, VYUY",
++		.fourcc   = V4L2_PIX_FMT_VYUY,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	/* dvp: Y8_1X8 */
++	{
++		.name     = "Y8, GREY",
++		.fourcc   = V4L2_PIX_FMT_GREY,
++		.depth    = {8},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_Y8_1X8,
++		.colorspace = V4L2_COLORSPACE_RAW,
++	},
++	/* RAW8 */
++	{
++		.name     = "RAW8, 8  BGBG.. GRGR..",
++		.fourcc   = V4L2_PIX_FMT_SBGGR8,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW8, 8  GBGB.. RGRG..",
++		.fourcc   = V4L2_PIX_FMT_SGBRG8,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW8, 8  GRGR.. BGBG..",
++		.fourcc   = V4L2_PIX_FMT_SGRBG8,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW8, 8  RGRG.. GBGB..",
++		.fourcc   = V4L2_PIX_FMT_SRGGB8,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	/* RAW10 */
++	{
++		.name     = "RAW10, 10  BGBG.. GRGR..",
++		.fourcc   = V4L2_PIX_FMT_SBGGR10,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW10, 10  GBGB.. RGRG..",
++		.fourcc   = V4L2_PIX_FMT_SGBRG10,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW10, 10  GRGR.. BGBG..",
++		.fourcc   = V4L2_PIX_FMT_SGRBG10,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW10, 10  RGRG.. GBGB..",
++		.fourcc   = V4L2_PIX_FMT_SRGGB10,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	/* RAW12 */
++	{
++		.name     = "RAW12, 12  BGBG.. GRGR..",
++		.fourcc   = V4L2_PIX_FMT_SBGGR12,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW12, 12  GBGB.. RGRG..",
++		.fourcc   = V4L2_PIX_FMT_SGBRG12,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW12, 12  GRGR.. BGBG..",
++		.fourcc   = V4L2_PIX_FMT_SGRBG12,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW12, 12  RGRG.. GBGB..",
++		.fourcc   = V4L2_PIX_FMT_SRGGB12,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++};
++
++struct isp_video_format vic_dvp_formats = {
++
++};
++
++
++static inline void vic_reg_writel(struct vic_device *vic, unsigned int reg, unsigned int val)
++{
++	writel(val, vic->iobase + reg);
++}
++
++static inline unsigned int vic_reg_readl(struct vic_device *vic, unsigned int reg)
++{
++	return readl(vic->iobase + reg);
++}
++
++
++static int ingenic_vic_parse_dt(struct vic_device * vic)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++unsigned int mux_out;
++static int vic_subdev_core_init(struct v4l2_subdev *sd, u32 ispcam_enabled)
++{
++	struct vic_device *vic = v4l2_get_subdevdata(sd);
++	if((ispcam_enabled == 0 && vic->iobase == (unsigned int *)0xb3380000) || (ispcam_enabled == 1 && vic->iobase == (unsigned int *)0xb3390000))
++		mux_out = 0;
++	else
++		mux_out = INPUT_MXU_OUT;
++	return 0;
++}
++
++static const struct v4l2_subdev_core_ops vic_subdev_core_ops = {
++		.init = vic_subdev_core_init,
++        .log_status = v4l2_ctrl_subdev_log_status,
++        .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
++        .unsubscribe_event = v4l2_event_subdev_unsubscribe,
++};
++
++static int vic_subdev_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct vic_device *vic = v4l2_get_subdevdata(sd);
++	struct media_pad *remote = NULL;
++	struct v4l2_subdev *remote_sd = NULL;
++	struct v4l2_subdev_format remote_subdev_fmt;
++	int ret = 0;
++
++	remote = media_entity_remote_pad(&vic->pads[VIC_PAD_SINK]);
++	remote_sd = media_entity_to_v4l2_subdev(remote->entity);
++
++	/*获��当�格�，�制到输出格�.*/
++	remote_subdev_fmt.pad = remote->index;
++	remote_subdev_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	ret = v4l2_subdev_call(remote_sd, pad, get_fmt, NULL, &remote_subdev_fmt);
++	if(ret < 0) {
++		dev_err(vic->dev, "Failed to get_fmt from remote pad\n");
++		return -EINVAL;
++	}
++
++	memcpy(&format->format, &remote_subdev_fmt.format, sizeof(format->format));
++
++	vic->formats[VIC_PAD_SINK] = vic->formats[VIC_PAD_SOURCE] = *format;
++
++	//printk("----%s, %d, format->pad: %d\n", __func__, __LINE__, format->pad);
++	return 0;
++}
++
++static int vic_subdev_set_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct vic_device *vic = v4l2_get_subdevdata(sd);
++	struct media_pad *remote = NULL;
++	struct v4l2_subdev *remote_sd = NULL;
++	struct v4l2_subdev_format remote_subdev_fmt;
++	int ret = 0;
++
++	dev_dbg(vic->dev, "%s, %d, width: %d, height: %d, mbus_code: %x\n", __func__, __LINE__, format->format.width, format->format.height, format->format.code);
++
++	vic->formats[VIC_PAD_SOURCE] = *format;
++
++	remote = media_entity_remote_pad(&vic->pads[VIC_PAD_SINK]);
++	remote_sd = media_entity_to_v4l2_subdev(remote->entity);
++
++	ret = v4l2_subdev_call(remote_sd, pad, set_fmt, NULL, format);
++	if(ret < 0) {
++		dev_dbg(vic->dev, "Failed to set_fmt from remote pad\n");
++	}
++
++	/*获��当�格�，�制到输出格�.*/
++	remote_subdev_fmt.pad = remote->index;
++	remote_subdev_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	ret = v4l2_subdev_call(remote_sd, pad, get_fmt, NULL, &remote_subdev_fmt);
++	if(ret < 0) {
++		dev_err(vic->dev, "Failed to get_fmt from remote pad\n");
++		printk("Failed to get_fmt from remote pad\n");
++		return -EINVAL;
++	}
++
++	memcpy(&vic->formats[VIC_PAD_SINK], &remote_subdev_fmt, sizeof(struct v4l2_subdev_format));
++	vic->sensor_info = (struct sensor_info *)*(unsigned int *)remote_subdev_fmt.format.reserved;
++
++	return 0;
++}
++
++
++static const struct v4l2_subdev_pad_ops vic_subdev_pad_ops = {
++	.get_fmt		= vic_subdev_get_fmt,
++	.set_fmt		= vic_subdev_set_fmt,
++};
++
++
++static int vic_cfg_stream_mipi(struct vic_device *vic)
++{
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	//struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2 = ispcam_get_bus_mipi_csi2(vic->ispcam);
++	struct mipi_cfg *mipi_cfg = &vic->sensor_info->mipi_cfg;
++	//unsigned int timeout = 10000;
++	unsigned int mipi_sensor_ctl = 0;
++
++	dev_dbg(vic->dev, "%s, %d, input_fmt->format.width: %d, intput_fmt->format.height: %d\n",
++			__func__, __LINE__, input_fmt->format.width, input_fmt->format.height);
++
++
++	if(mipi_cfg->mipi_mode == SENSOR_MIPI_SONY_MODE) {
++		dev_info(vic->dev, "[ %s:%d ] sensor type is SONY_MIPI!\n", __func__, __LINE__);
++		/*imx307 nomal*/
++		vic_reg_writel(vic, VIC_IN_DVP, (0x0 << 31 | 0x0 <<24 | 0x1 << 17 | 0x0 << 11 | 0x0 << 4));
++		vic_reg_writel(vic, VIC_CONTROL_CONTROL, 0x00100010);
++	} else {
++		dev_info(vic->dev, "[ %s:%d ] sensor type is OTHER_MIPI!\n", __func__, __LINE__);
++		vic_reg_writel(vic, VIC_CONTROL_DELAY, (10 << 16) | (10));
++	}
++
++	vic_reg_writel(vic, VIC_INTF_TYPE, INTF_TYPE_MIPI);
++
++	switch(input_fmt->format.code) {
++		case MEDIA_BUS_FMT_SBGGR8_1X8:
++		case MEDIA_BUS_FMT_SGBRG8_1X8:
++		case MEDIA_BUS_FMT_SGRBG8_1X8:
++		case MEDIA_BUS_FMT_SRGGB8_1X8:
++			vic_reg_writel(vic, VIC_IN_CSI_FMT,MIPI_RAW8);//RAW8
++			vic_reg_writel(vic, MIPI_ALL_WIDTH_4BYTE, (mipi_cfg->twidth * 8 % 32) ? (mipi_cfg->twidth * 8 / 32)+ 1 : (mipi_cfg->twidth * 8 / 32));
++			break;
++		case    MEDIA_BUS_FMT_SBGGR10_1X10:
++		case    MEDIA_BUS_FMT_SGBRG10_1X10:
++		case    MEDIA_BUS_FMT_SGRBG10_1X10:
++		case    MEDIA_BUS_FMT_SRGGB10_1X10:
++			vic_reg_writel(vic, VIC_IN_CSI_FMT,MIPI_RAW10);//RAW10
++			vic_reg_writel(vic, MIPI_ALL_WIDTH_4BYTE, (mipi_cfg->twidth * 10 % 32) ? (mipi_cfg->twidth * 10 / 32)+ 1 : (mipi_cfg->twidth * 10 / 32));
++			break;
++		case    MEDIA_BUS_FMT_SBGGR12_1X12:
++		case    MEDIA_BUS_FMT_SGBRG12_1X12:
++		case    MEDIA_BUS_FMT_SGRBG12_1X12:
++		case    MEDIA_BUS_FMT_SRGGB12_1X12:
++			vic_reg_writel(vic, VIC_IN_CSI_FMT,MIPI_RAW12);//RAW12
++			vic_reg_writel(vic, MIPI_ALL_WIDTH_4BYTE, (mipi_cfg->twidth * 12 % 32) ? (mipi_cfg->twidth * 12 / 32)+ 1 : (mipi_cfg->twidth * 12 / 32));
++			break;
++		case MEDIA_BUS_FMT_Y8_1X8 :
++			vic_reg_writel(vic, VIC_IN_CSI_FMT, MIPI_YUV422);//YUV422
++			vic_reg_writel(vic, MIPI_ALL_WIDTH_4BYTE, (mipi_cfg->twidth*2 * 8 % 32) ? (mipi_cfg->twidth*2 * 8 / 32)+ 1 : (mipi_cfg->twidth*2 * 8 / 32));
++			break;
++		case MEDIA_BUS_FMT_YUYV8_2X8 :
++		case MEDIA_BUS_FMT_YVYU8_2X8 :
++		case MEDIA_BUS_FMT_UYVY8_2X8 :
++		case MEDIA_BUS_FMT_VYUY8_2X8 :
++			vic_reg_writel(vic, VIC_IN_CSI_FMT, MIPI_YUV422);//YUV422
++			vic_reg_writel(vic, MIPI_ALL_WIDTH_4BYTE, (mipi_cfg->twidth * 8 % 32) ? (mipi_cfg->twidth * 8 / 32)+ 1 : (mipi_cfg->twidth * 8 / 32));
++			break;
++		default:
++			dev_err(vic->dev, "unsupported mbus fmt: %x\n", input_fmt->format.code);
++			return -EINVAL;
++	}
++
++	vic_reg_writel(vic, VIC_CONTROL_CONTROL, mipi_cfg->sensor_mode << SENSOR_MODE | mipi_cfg->sensor_frame_mode << SENSOR_FRM_NUM);
++
++	mipi_sensor_ctl = mipi_cfg->hcrop_diff_en << HCROP_DIFF_EN | mipi_cfg->mipi_vcomp_en << VCOMP_EN | mipi_cfg->mipi_hcomp_en << HCOMP_EN |mipi_cfg->line_sync_mode << LINE_SYNC_MODE | mipi_cfg->work_start_flag << WORK_START_FLAG | mipi_cfg->data_type_en << DATA_TYPE_EN | mipi_cfg->data_type_value << DATA_TYPE_VALUE | mipi_cfg->del_start << DEL_START | mipi_cfg->sensor_frame_mode << SENSOR_FRM_NUM | mipi_cfg->sensor_fid_mode << SENSOR_FID_MODE | mipi_cfg->sensor_mode << SENSOR_MODE;
++	vic_reg_writel(vic, MIPI_SENSOR_CONTROL, mipi_sensor_ctl);
++
++	vic_reg_writel(vic, MIPI_HCROP_CH0, (mipi_cfg->twidth << 16) | mipi_cfg->mipi_crop_start0x);
++	vic_reg_writel(vic, MIPI_HCROP_CH1, mipi_cfg->mipi_crop_start1x);
++	vic_reg_writel(vic, MIPI_HCROP_CH2, mipi_cfg->mipi_crop_start2x);
++	vic_reg_writel(vic, MIPI_HCROP_CH3, mipi_cfg->mipi_crop_start3x);
++
++	vic_reg_writel(vic, MIPI_VCROP_DEL01, mipi_cfg->mipi_crop_start1y << 16 | mipi_cfg->mipi_crop_start0y);
++	vic_reg_writel(vic, MIPI_VCROP_DEL23, mipi_cfg->mipi_crop_start3y << 16 | mipi_cfg->mipi_crop_start2y);
++
++	return 0;
++}
++
++static int vic_cfg_stream_dvp(struct vic_device *vic)
++{
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	struct v4l2_fwnode_bus_parallel *parallel = ispcam_get_bus_parallel(vic->ispcam);
++	//struct dvp_cfg *dvp_cfg = &vic->sensor_info->dvp_cfg;
++	unsigned int input_cfg = 0;
++
++	vic->frame_capture_counter = 0; /* reset counter */
++	vic->global_reset = 0;
++
++	dev_dbg(vic->dev, "parallel->flags: 0x%x\n", parallel->flags);
++	dev_dbg(vic->dev, "parallel->bus_width: %d\n", parallel->bus_width);
++	dev_dbg(vic->dev, "parallel->data_shift: %d\n", parallel->data_shift);
++	vic_reg_writel(vic, VIC_INTF_TYPE, INTF_TYPE_DVP);
++	switch(input_fmt->format.code) {
++		case MEDIA_BUS_FMT_SBGGR8_1X8:
++		case MEDIA_BUS_FMT_SGBRG8_1X8:
++		case MEDIA_BUS_FMT_SGRBG8_1X8:
++		case MEDIA_BUS_FMT_SRGGB8_1X8:
++			if(parallel->data_shift) {
++				input_cfg = DVP_RAW8 | DVP_RAW_ALIG;
++			} else {
++				input_cfg = DVP_RAW8;
++			}
++			break;
++		case MEDIA_BUS_FMT_SBGGR10_1X10:
++		case MEDIA_BUS_FMT_SGBRG10_1X10:
++		case MEDIA_BUS_FMT_SGRBG10_1X10:
++		case MEDIA_BUS_FMT_SRGGB10_1X10:
++			if(parallel->data_shift) {
++				input_cfg = DVP_RAW10 | DVP_RAW_ALIG;
++			} else {
++				input_cfg = DVP_RAW10;
++			}
++			break;
++		case MEDIA_BUS_FMT_SBGGR12_1X12:
++		case MEDIA_BUS_FMT_SGBRG12_1X12:
++		case MEDIA_BUS_FMT_SGRBG12_1X12:
++		case MEDIA_BUS_FMT_SRGGB12_1X12:
++			input_cfg = DVP_RAW12;
++			break;
++		case MEDIA_BUS_FMT_UYVY8_1_5X8 :
++		case MEDIA_BUS_FMT_VYUY8_1_5X8 :
++		case MEDIA_BUS_FMT_YUYV8_1_5X8 :
++		case MEDIA_BUS_FMT_YVYU8_1_5X8 :
++		case MEDIA_BUS_FMT_YUYV8_1X16 :
++		case MEDIA_BUS_FMT_YUYV8_2X8 :
++		case MEDIA_BUS_FMT_YVYU8_2X8 :
++		case MEDIA_BUS_FMT_UYVY8_2X8 :
++		case MEDIA_BUS_FMT_VYUY8_2X8 :
++		case MEDIA_BUS_FMT_Y8_1X8 :
++			input_cfg = DVP_YUV422_8BIT;
++			break;
++
++		default:
++			dev_err(vic->dev, "unsupported input formats\n");
++			return -EINVAL;
++	}
++	if(parallel->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) {
++		input_cfg |= HSYN_POLAR;
++	}
++	if(parallel->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) {
++		input_cfg |= VSYN_POLAR;
++	}
++	vic_reg_writel(vic, VIC_IN_DVP, input_cfg);
++	/*dev_info(vic->dev, "VIC_IN_DVP	input_cfg=0x%x\n", input_cfg);
++	if (input_fmt->format.width>2048 && input_fmt->format.height == 1) {
++		vic_reg_writel(vic, VIC_IN_DVP, 0x6<<17 | 1<<1 | 1<<0);    //cisadc, 0x6<<17 | 1<<1 | 1<<0;
++	}*/
++	/*TODO: hblank and vblank*/
++
++	if(input_fmt->format.code == MEDIA_BUS_FMT_YUYV8_2X8)
++		vic_reg_writel(vic, VIC_IN_HOR_PARA0, input_fmt->format.width * 2 + 0 /*hblank*/);
++	else
++		vic_reg_writel(vic, VIC_IN_HOR_PARA0, input_fmt->format.width + 0 /*hblank*/);
++	// vc control
++	vic_reg_writel(vic, VIC_CONTROL_DELAY, 0x10 << 16 | 0x10);
++	vic_reg_writel(vic, VIC_CONTROL_DELEY_BLK, 0x10);
++	vic_reg_writel(vic, VIC_CONTROL_LIMIT, 0);
++
++	return 0;
++}
++
++static int vic_cfg_stream_bt1120(struct vic_device *vic)
++{
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	struct v4l2_fwnode_bus_parallel *parallel = ispcam_get_bus_parallel(vic->ispcam);
++	struct bt_cfg *bt_cfg = &vic->sensor_info->bt_cfg;
++	unsigned int input_cfg = 0;
++
++	vic->frame_capture_counter = 0; /* reset counter */
++	vic->global_reset = 0;
++
++	dev_dbg(vic->dev, "parallel->flags: 0x%x\n", parallel->flags);
++	dev_dbg(vic->dev, "parallel->bus_width: %d\n", parallel->bus_width);
++	dev_dbg(vic->dev, "parallel->data_shift: %d\n", parallel->data_shift);
++	vic_reg_writel(vic, VIC_INTF_TYPE, INTF_TYPE_BT1120);
++
++	switch(input_fmt->format.code) {
++		case MEDIA_BUS_FMT_YUYV8_2X8 :
++			input_cfg |= YUYV;
++			break;
++		case MEDIA_BUS_FMT_YVYU8_2X8 :
++			input_cfg |= YVYU;
++			break;
++		case MEDIA_BUS_FMT_UYVY8_2X8 :
++			input_cfg |= UYVY;
++			break;
++		case MEDIA_BUS_FMT_VYUY8_2X8 :
++			input_cfg |= VYUY;
++			break;
++		default:
++			dev_err(vic->dev, "unsupported input formats\n");
++			return -EINVAL;
++	}
++
++	if(parallel->bus_width == 16) {
++		input_cfg |= BT_INTF_WIDE;
++		input_cfg |= DVP_YUV422_16BIT;
++	} else
++		input_cfg |= DVP_YUV422_8BIT;
++
++	if(bt_cfg->interlace_en)
++		input_cfg |= INTERLACE_EN;
++	if(bt_cfg->bt_sav_eav == SAV_BF_EAV)
++		input_cfg |= BT_LINE_MODE;
++
++	vic_reg_writel(vic, VIC_IN_DVP, input_cfg);
++	/*dev_info(vic->dev, "VIC_IN_DVP	input_cfg=0x%x\n", input_cfg);
++	if (input_fmt->format.width>2048 && input_fmt->format.height == 1) {
++		vic_reg_writel(vic, VIC_IN_DVP, 0x6<<17 | 1<<1 | 1<<0);    //cisadc, 0x6<<17 | 1<<1 | 1<<0;
++	}*/
++	/*TODO: hblank and vblank*/
++
++	vic_reg_writel(vic, VIC_IN_HOR_PARA0, input_fmt->format.width + 0 /*hblank*/);
++	// vc control
++	vic_reg_writel(vic, VIC_CONTROL_DELAY, 0x10 << 16 | 0x10);
++	vic_reg_writel(vic, VIC_CONTROL_DELEY_BLK, 0x10);
++	vic_reg_writel(vic, VIC_CONTROL_LIMIT, 0);
++
++	return 0;
++}
++
++static int vic_subdev_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct vic_device *vic = v4l2_get_subdevdata(sd);
++	struct isp_async_device *isd = &vic->ispcam->isd[0];	/*TODO: 默认支�一个asd.*/
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	struct isp_video_device *ispvideo = v4l2_get_subdev_hostdata(sd);
++	struct isp_video_buffer *isp_buffer = NULL;
++	struct isp_video_buffer *tmp = NULL;
++	int ret = 0;
++	unsigned long flags;
++	int width;
++	unsigned int regval;
++	unsigned int y_stride;
++	unsigned int uv_stride;
++
++	spin_lock_irqsave(&vic->lock, flags);
++	/*hw configure.*/
++	if(enable) {
++
++		if(vic->enabled++ > 0) {
++			goto finish;
++		}
++
++		/* set width */
++		switch(input_fmt->format.code) {
++		case MEDIA_BUS_FMT_Y8_1X8 :
++			input_fmt->format.width /= 2; /*  */
++			width = input_fmt->format.width;
++			break;
++			/* TODO: NV21/NV12 */
++		default:
++			width = input_fmt->format.width;
++		}
++
++#if 0
++		/* enable timestamp .*/
++		vic_reg_writel(vic, VIC_TS_COUNTER, count_period - 1);
++		vic_reg_writel(vic, VIC_TS_DMA_OFFSET, 0);
++		vic_reg_writel(vic, VIC_TS_MS_CH0_OFFSET, 0);
++		vic_reg_writel(vic, VIC_TS_MS_CH1_OFFSET, 0);
++		vic_reg_writel(vic, VIC_TS_MS_CH2_OFFSET, 0);
++		vic_reg_writel(vic, VIC_TS_ENABLE, TS_COUNTER_EN |
++				TS_VIC_DMA_EN | TS_MS_CH0_EN |
++				TS_MS_CH1_EN | TS_MS_CH2_EN);
++#endif
++
++		/*confgure hw and start*/
++		if(isd->bus_type == V4L2_MBUS_CSI2_DPHY) {
++			ret = vic_cfg_stream_mipi(vic);
++			mux_out |= INPUT_MXU_MIPI_EN;
++		} else if(isd->bus_type == V4L2_MBUS_PARALLEL){
++			ret = vic_cfg_stream_dvp(vic);
++			mux_out |= INPUT_MXU_DVP_EN;
++		} else if(isd->bus_type == V4L2_MBUS_BT656) {
++			ret = vic_cfg_stream_bt1120(vic);
++			mux_out |= INPUT_MXU_DVP_EN;
++		}
++
++		vic_reg_writel(vic, VIC_RESOLUTION, (width << 16) |
++				input_fmt->format.height);
++
++		if(ispvideo->bypass == 1) {
++			if(dma_debug_en) {
++				printk("please disable vic dma debug mode\ntry \"echo 0 > /sys/module/vic/parameters/dma_debug_en\"\n");
++				goto finish;
++			}
++			/*DMA config*/
++			regval = 0;
++			/*TODO: fmts.*/
++			switch(ispvideo->current_format->fourcc) {
++			case V4L2_PIX_FMT_YUYV :
++				regval |= 3<<8; /* Y1UY2V */
++				regval |= 3<<0; /* mode 3: YUV422 */
++				y_stride = width * 2;
++				uv_stride = width * 2;
++				break;
++			case V4L2_PIX_FMT_YVYU :
++				regval |= 2<<8; /* Y2VY1U */
++				regval |= 3<<0; /* mode 3: YUV422 */
++				y_stride = width * 2;
++				uv_stride = width * 2;
++				break;
++			case V4L2_PIX_FMT_UYVY :
++				regval |= 1<<8; /* UY1VY2 */
++				regval |= 3<<0; /* mode 3: YUV422 */
++				y_stride = width * 2;
++				uv_stride = width * 2;
++				break;
++			case V4L2_PIX_FMT_VYUY :
++				regval |= 0<<8; /* VY2UY1 */
++				regval |= 3<<0; /* mode 3: YUV422 */
++				y_stride = width * 2;
++				uv_stride = width * 2;
++				break;
++			case V4L2_PIX_FMT_GREY :
++				regval |= 3<<0; /* mode 3: YUV422 */
++				y_stride = width * 2;
++				uv_stride = width * 2;
++				break;
++			case V4L2_PIX_FMT_NV12 :
++				regval |= 6<<0; /* mode 6: NV12 */
++				y_stride = width;
++				uv_stride = width;
++				break;
++			case V4L2_PIX_FMT_NV21 :
++				regval |= 7<<0; /* mode 7: NV12 */
++				y_stride = width;
++				uv_stride = width;
++				break;
++			case V4L2_PIX_FMT_SBGGR8:
++			case V4L2_PIX_FMT_SGBRG8:
++			case V4L2_PIX_FMT_SGRBG8:
++			case V4L2_PIX_FMT_SRGGB8:
++			case V4L2_PIX_FMT_SBGGR10:
++			case V4L2_PIX_FMT_SGBRG10:
++			case V4L2_PIX_FMT_SGRBG10:
++			case V4L2_PIX_FMT_SRGGB10:
++			case V4L2_PIX_FMT_SBGGR12:
++			case V4L2_PIX_FMT_SGBRG12:
++			case V4L2_PIX_FMT_SGRBG12:
++			case V4L2_PIX_FMT_SRGGB12:
++				regval |= 0;
++				y_stride = width * 2;
++				uv_stride = width * 2;
++				break;
++			default:
++				dev_info(vic->dev, "%s(), TODO: DMA config, input_fmt->format.code=0x%x\n",
++					 __func__, input_fmt->format.code);
++				return -EINVAL;
++			}
++			regval |= 1 << 31; /* enable dma */
++			regval |= (ispvideo->max_buffer_num - 1) << 3;
++			regval |= 8 << 16; /*max outout num*/
++			vic_reg_writel(vic, VIC_DMA_CONFIG, regval);
++
++			vic_reg_writel(vic, VIC_DMA_RESOLUTION, (width << 16) |
++				       input_fmt->format.height);
++			vic_reg_writel(vic, VIC_DMA_Y_STRID, y_stride);
++			vic_reg_writel(vic, VIC_DMA_UV_STRID, uv_stride);
++
++			vic_reg_writel(vic, VIC_CONTROL_TIZIANO_ROUTE, 0);
++			if(isd->bus_type == V4L2_MBUS_CSI2_DPHY)
++				vic_reg_writel(vic, VIC_CONTROL_DMA_ROUTE, 0x4440);
++			else
++				vic_reg_writel(vic, VIC_CONTROL_DMA_ROUTE, 0x4210);
++			vic_reg_writel(vic, VIC_INT_MASK, 0x0);
++			vic_reg_writel(vic, VIC_INT_MASK2, 0x0);
++			/*
++			if(input_fmt->format.width > 2048) {
++				if(0 && input_fmt->format.height > 1)
++					vic_reg_writel(vic, VIC_CONTROL_LIMIT, (1 << 31)|((input_fmt->format.width / 8 * 3) << 16));
++				else
++					vic_reg_writel(vic, VIC_CONTROL_LIMIT, (1 << 31)|(512<<16)); // cisadc, height==1, width > 2048
++			}
++			*/
++			vic->framenum = 0;
++
++		} else {
++			if(vic->sensor_info->wdr_en)
++				vic_reg_writel(vic, VIC_CONTROL_TIZIANO_ROUTE, 0x4410);
++			else
++				vic_reg_writel(vic, VIC_CONTROL_TIZIANO_ROUTE, 0x4404);
++			if(dma_debug_en)
++				if(vic->sensor_info->wdr_en)
++					vic_reg_writel(vic, VIC_CONTROL_DMA_ROUTE, 0x4410);
++				else{
++					if(isd->bus_type == V4L2_MBUS_CSI2_DPHY)
++						vic_reg_writel(vic, VIC_CONTROL_DMA_ROUTE, 0x4440);
++					else
++						vic_reg_writel(vic, VIC_CONTROL_DMA_ROUTE, 0x4210);
++				}
++			else
++				vic_reg_writel(vic, VIC_CONTROL_DMA_ROUTE, 0);
++			vic_reg_writel(vic, VIC_INT_MASK, 0);
++			vic_reg_writel(vic, VIC_INT_MASK2, 0);
++
++			vic_reg_writel(vic, VIC_CONTROL, GLB_RST);
++		}
++
++		vic_reg_writel(vic, VIC_CONTROL_INPUT_MUX_OUTROUTE, mux_out);
++		if(vic->iobase == (unsigned int *)0xb3390000 && *(volatile unsigned int *)0xb33801c0 == 0)
++			*(volatile unsigned int *)0xb33801c0 = 0x02;
++
++		/*
++		vic_reg_writel(vic, VIC_CONTROL, REG_ENABLE);
++		unsigned int timeout  = 0xfffff;
++		while(vic_reg_readl(vic,VIC_CONTROL) && --timeout);
++		if(!timeout) {
++			dev_err(vic->dev, "wait vic init timeout!\n");
++		}
++		*/
++		vic_reg_writel(vic, VIC_CONTROL, VIC_START);
++
++
++	} else {
++		/*reset flags*/
++		vic->buffer_index = 0;
++		vic->stop_flag = 0;
++		vic_stop_counter = 0;
++
++		if(--vic->enabled) {
++			goto finish;
++		}
++
++		/* disable timestamp */
++		vic_reg_writel(vic, VIC_TS_COUNTER, 0);
++		vic_reg_writel(vic, VIC_TS_ENABLE, 0);
++
++		if(ispvideo->bypass) {
++			/*disable dma*/
++			vic_reg_writel(vic, VIC_DMA_CONFIG, 0);
++			/*disable contro limit*/
++			if(input_fmt->format.width > 2048)
++				vic_reg_writel(vic, VIC_CONTROL_LIMIT, 0);
++		}
++
++		/* keep reset*/
++		vic_reg_writel(vic, VIC_CONTROL, GLB_RST);
++
++		/* stop vic. */
++		list_for_each_entry_safe(isp_buffer, tmp, &vic->dma_queued_list, list_entry) {
++			struct vb2_buffer *vb2_buf = &isp_buffer->vb2.vb2_buf;
++			vb2_buffer_done(vb2_buf, VB2_BUF_STATE_ERROR);
++			list_del(&isp_buffer->list_entry);
++			vic->buffer_count--;
++		}
++
++	}
++
++finish:
++	spin_unlock_irqrestore(&vic->lock, flags);
++
++	return ret;
++}
++
++
++static const struct v4l2_subdev_video_ops vic_subdev_video_ops = {
++        .s_stream = vic_subdev_s_stream,
++};
++static const struct v4l2_subdev_ops vic_subdev_ops = {
++        .core = &vic_subdev_core_ops,
++        .pad = &vic_subdev_pad_ops,
++        .video = &vic_subdev_video_ops,
++};
++
++struct isp_video_format *vic_find_format(const u32 *pixelformat, const u32 *mbus_code, int index)
++{
++	int i;
++	struct isp_video_format *fmt = NULL;
++
++	for(i = 0; i < ARRAY_SIZE(vic_mipi_formats); i++) {
++		fmt = &vic_mipi_formats[i];
++
++		if(pixelformat && fmt->fourcc == *pixelformat) {
++			return fmt;
++		}
++		if(mbus_code && fmt->mbus_code == *mbus_code) {
++			return fmt;
++		}
++
++		if(index == i) {
++			return fmt;
++		}
++	}
++
++	return NULL;
++}
++
++static int vic_video_qbuf(struct isp_video_device *ispvideo, struct isp_video_buffer *isp_buffer)
++{
++	struct vic_device *vic = ispvideo->ispcam->vic;
++	struct vb2_buffer *vb2_buf = NULL;
++	struct isp_video_buffer *tmp = NULL;
++	unsigned long flags = 0;
++	dma_addr_t y_addr = 0;
++	dma_addr_t uv_addr = 0;
++	unsigned int regval;
++
++	spin_lock_irqsave(&vic->lock, flags);
++
++	vb2_buf = &isp_buffer->vb2.vb2_buf;
++
++	list_add_tail(&isp_buffer->list_entry, &vic->dma_queued_list);
++	vic->buffer_count++;
++
++
++	/*Y*/
++	y_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 0);
++	vic_reg_writel(vic, VIC_DMA_Y_CH0_BUF0 + vic->buffer_index * 4, y_addr);
++
++	uv_addr = y_addr + isp_buffer->uv_offset;
++	/*UV*/
++	if(vb2_buf->num_planes == 2) {
++		uv_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 1);
++	}
++	vic_reg_writel(vic, VIC_DMA_UV_CH0_BUF0 + vic->buffer_index * 4, uv_addr);
++
++	vic->buffer_index++;
++	vic->buffer_index %= ispvideo->max_buffer_num;
++
++	if(vic->buffer_count >= VIC_RESTART_BUFFER_COUNT && vic->stop_flag)
++	{
++		/*reset flags*/
++		vic->stop_flag = 0;
++		vic->buffer_index = 0;
++
++		/*buffers in the list refill in register*/
++		list_for_each_entry_safe(isp_buffer, tmp, &vic->dma_queued_list, list_entry) {
++
++			vb2_buf = &isp_buffer->vb2.vb2_buf;
++			/*Y*/
++			y_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 0);
++			vic_reg_writel(vic, VIC_DMA_Y_CH0_BUF0 + vic->buffer_index * 4, y_addr);
++
++			uv_addr = y_addr + isp_buffer->uv_offset;
++			/*UV*/
++			if(vb2_buf->num_planes == 2) {
++				uv_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 1);
++			}
++			vic_reg_writel(vic, VIC_DMA_UV_CH0_BUF0 + vic->buffer_index * 4, uv_addr);
++
++			vic->buffer_index++;
++			vic->buffer_index %= ispvideo->max_buffer_num;
++
++		}
++		/*restart*/
++		regval = vic_reg_readl(vic, VIC_DMA_CONFIG);
++		vic_reg_writel(vic, VIC_DMA_RESET, 1);
++		vic_reg_writel(vic, VIC_DMA_RESET, 0);
++		regval |= 1 << 31; /* enable dma */
++		regval &= ~(0xf<<3); /* reset dma buffer num */
++		regval |= (ispvideo->max_buffer_num - 1) << 3;
++		vic_reg_writel(vic, VIC_DMA_CONFIG, regval);
++		/* lgwang, re-start vic */
++		if (vic->global_reset) {
++			vic_reg_writel(vic, VIC_CONTROL, 0x1);
++			vic->global_reset = 0;
++		}
++		goto done;
++	}
++
++done:
++	spin_unlock_irqrestore(&vic->lock, flags);
++
++	return 0;
++}
++
++static const struct isp_video_ops vic_video_ops = {
++	.find_format 	= vic_find_format,
++	.qbuf		= vic_video_qbuf,
++};
++
++static ssize_t
++dump_vic(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct vic_device *vic = dev_get_drvdata(dev);
++	char *p = buf;
++
++	p += sprintf(p, "VIC_CONTROL			:0x%08x\n", vic_reg_readl(vic, VIC_CONTROL));
++	p += sprintf(p, "VIC_RESOLUTION                 :0x%08x\n", vic_reg_readl(vic, VIC_RESOLUTION));
++	p += sprintf(p, "VIC_FRM_ECC                    :0x%08x\n", vic_reg_readl(vic, VIC_FRM_ECC));
++	p += sprintf(p, "VIC_INTF_TYPE                  :0x%08x\n", vic_reg_readl(vic, VIC_INTF_TYPE));
++	p += sprintf(p, "VIC_IN_DVP                     :0x%08x\n", vic_reg_readl(vic, VIC_IN_DVP));
++	p += sprintf(p, "VIC_IN_CSI_FMT                 :0x%08x\n", vic_reg_readl(vic, VIC_IN_CSI_FMT));
++	p += sprintf(p, "VIC_IN_HOR_PARA0               :0x%08x\n", vic_reg_readl(vic, VIC_IN_HOR_PARA0));
++	p += sprintf(p, "VIC_IN_HOR_PARA1               :0x%08x\n", vic_reg_readl(vic, VIC_IN_HOR_PARA1));
++	p += sprintf(p, "VIC_IN_VER_PARA0               :0x%08x\n", vic_reg_readl(vic, VIC_IN_VER_PARA0));
++	p += sprintf(p, "VIC_IN_VER_PARA1               :0x%08x\n", vic_reg_readl(vic, VIC_IN_VER_PARA1));
++	p += sprintf(p, "VIC_IN_VER_PARA2               :0x%08x\n", vic_reg_readl(vic, VIC_IN_VER_PARA2));
++	p += sprintf(p, "VIC_IN_VER_PARA3               :0x%08x\n", vic_reg_readl(vic, VIC_IN_VER_PARA3));
++	p += sprintf(p, "VIC_VLD_LINE_SAV               :0x%08x\n", vic_reg_readl(vic, VIC_VLD_LINE_SAV));
++	p += sprintf(p, "VIC_VLD_LINE_EAV               :0x%08x\n", vic_reg_readl(vic, VIC_VLD_LINE_EAV));
++	p += sprintf(p, "VIC_VLD_FRM_SAV                :0x%08x\n", vic_reg_readl(vic, VIC_VLD_FRM_SAV));
++	p += sprintf(p, "VIC_VLD_FRM_EAV                :0x%08x\n", vic_reg_readl(vic, VIC_VLD_FRM_EAV));
++	p += sprintf(p, "VIC_VC_CONTROL                 :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL));
++	p += sprintf(p, "VIC_VC_CONTROL_CH0_PIX         :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_CH0_PIX));
++	p += sprintf(p, "VIC_VC_CONTROL_CH1_PIX         :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_CH1_PIX));
++	p += sprintf(p, "VIC_VC_CONTROL_CH2_PIX         :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_CH2_PIX));
++	p += sprintf(p, "VIC_VC_CONTROL_CH3_PIX         :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_CH3_PIX));
++	p += sprintf(p, "VIC_VC_CONTROL_CH0_LINE        :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_CH0_LINE));
++	p += sprintf(p, "VIC_VC_CONTROL_CH1_LINE        :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_CH1_LINE));
++	p += sprintf(p, "VIC_VC_CONTROL_CH2_LINE        :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_CH2_LINE));
++	p += sprintf(p, "VIC_VC_CONTROL_CH3_LINE        :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_CH3_LINE));
++	p += sprintf(p, "VIC_VC_CONTROL_FIFO_USE        :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_FIFO_USE));
++	p += sprintf(p, "MIPI_ALL_WIDTH_4BYTE           :0x%08x\n", vic_reg_readl(vic, MIPI_ALL_WIDTH_4BYTE));
++	p += sprintf(p, "MIPI_VCROP_DEL01               :0x%08x\n", vic_reg_readl(vic, MIPI_VCROP_DEL01));
++	p += sprintf(p, "MIPI_SENSOR_CONTROL            :0x%08x\n", vic_reg_readl(vic, MIPI_SENSOR_CONTROL));
++	p += sprintf(p, "MIPI_HCROP_CH0                 :0x%08x\n", vic_reg_readl(vic, MIPI_HCROP_CH0));
++	p += sprintf(p, "VIC_CONTROL_LIMIT              :0x%08x\n", vic_reg_readl(vic, VIC_CONTROL_LIMIT));
++	p += sprintf(p, "VIC_CONTROL_DELAY              :0x%08x\n", vic_reg_readl(vic, VIC_CONTROL_DELAY));
++	p += sprintf(p, "VIC_CONTROL_TIZIANO_ROUTE      :0x%08x\n", vic_reg_readl(vic, VIC_CONTROL_TIZIANO_ROUTE));
++	p += sprintf(p, "VIC_CONTROL_DMA_ROUTE          :0x%08x\n", vic_reg_readl(vic, VIC_CONTROL_DMA_ROUTE));
++	p += sprintf(p, "VIC_INT_STA                    :0x%08x\n", vic_reg_readl(vic, VIC_INT_STA));
++	p += sprintf(p, "VIC_INT_MASK                   :0x%08x\n", vic_reg_readl(vic, VIC_INT_MASK));
++	p += sprintf(p, "VIC_INT_CLR                    :0x%08x\n", vic_reg_readl(vic, VIC_INT_CLR));
++	p += sprintf(p, "VIC_DMA_CONFIG        :0x%08x\n", vic_reg_readl(vic, VIC_DMA_CONFIG));
++	p += sprintf(p, "VIC_DMA_RESOLUTION    :0x%08x\n", vic_reg_readl(vic, VIC_DMA_RESOLUTION));
++	p += sprintf(p, "VIC_DMA_RESET         :0x%08x\n", vic_reg_readl(vic, VIC_DMA_RESET));
++	p += sprintf(p, "VIC_DMA_Y_STRID       :0x%08x\n", vic_reg_readl(vic, VIC_DMA_Y_STRID));
++	p += sprintf(p, "VIC_DMA_Y_CH0_BUF0        :0x%08x\n", vic_reg_readl(vic, VIC_DMA_Y_CH0_BUF0));
++	p += sprintf(p, "VIC_DMA_Y_CH0_BUF1        :0x%08x\n", vic_reg_readl(vic, VIC_DMA_Y_CH0_BUF1));
++	p += sprintf(p, "VIC_DMA_Y_CH0_BUF2        :0x%08x\n", vic_reg_readl(vic, VIC_DMA_Y_CH0_BUF2));
++	p += sprintf(p, "VIC_DMA_Y_CH0_BUF3        :0x%08x\n", vic_reg_readl(vic, VIC_DMA_Y_CH0_BUF3));
++	p += sprintf(p, "VIC_DMA_Y_CH0_BUF4        :0x%08x\n", vic_reg_readl(vic, VIC_DMA_Y_CH0_BUF4));
++	p += sprintf(p, "VIC_DMA_UV_STRID      :0x%08x\n", vic_reg_readl(vic, VIC_DMA_UV_STRID));
++	p += sprintf(p, "VIC_DMA_UV_CH0_BUF0       :0x%08x\n", vic_reg_readl(vic, VIC_DMA_UV_CH0_BUF0));
++	p += sprintf(p, "VIC_DMA_UV_CH0_BUF1       :0x%08x\n", vic_reg_readl(vic, VIC_DMA_UV_CH0_BUF1));
++	p += sprintf(p, "VIC_DMA_UV_CH0_BUF2       :0x%08x\n", vic_reg_readl(vic, VIC_DMA_UV_CH0_BUF2));
++	p += sprintf(p, "VIC_DMA_UV_CH0_BUF3       :0x%08x\n", vic_reg_readl(vic, VIC_DMA_UV_CH0_BUF3));
++	p += sprintf(p, "VIC_DMA_UV_CH0_BUF4       :0x%08x\n", vic_reg_readl(vic, VIC_DMA_UV_CH0_BUF4));
++
++
++
++	return p - buf;
++}
++
++ssize_t vic_dma_debug(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct vic_device *vic = dev_get_drvdata(dev);
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	unsigned int imagesize = 0;
++	unsigned int lineoffset = 0;
++	unsigned int num = 0;
++	int loop = 100;
++	struct file *fd = NULL;
++	mm_segment_t old_fs;
++	loff_t *pos;
++	int ret = 0;
++
++	if (!strncmp(buf, "snapraw", sizeof("snapraw")-1)) {
++		if(!dma_debug_en) {
++			printk("please enable vic dma debug mode\ntry \"echo 1 > /sys/module/vic/parameters/dma_debug_en\"\n");
++			return -EINVAL;
++		}
++
++		lineoffset = input_fmt->format.width * 2;
++		imagesize = lineoffset * input_fmt->format.height;
++		dev_info(vic->dev, "width is %d,height is %d,imagesize is %d\n",input_fmt->format.width,input_fmt->format.height,imagesize);
++		if(input_fmt->format.width > VIC_DMA_OUTPUT_MAX_WIDTH){
++			return -EINVAL;
++		}
++		if(vic->snap_paddr){
++			return -EBUSY;
++		}
++
++		if(vic->sensor_info->wdr_en)
++			num = 2;
++		else
++			num = 1;
++		vic->snap_vaddr = kmalloc(imagesize * num, GFP_KERNEL);
++
++		if(vic->snap_vaddr){
++			vic->snap_paddr = virt_to_phys((void *)vic->snap_vaddr);
++			vic_reg_writel(vic, VIC_DMA_RESET, 0x01);
++			vic_reg_writel(vic, VIC_DMA_RESOLUTION, input_fmt->format.width << 16 | input_fmt->format.height);
++			vic_reg_writel(vic, VIC_DMA_Y_STRID, lineoffset);
++			vic_reg_writel(vic, VIC_DMA_Y_CH0_BUF0, vic->snap_paddr);
++			if(vic->sensor_info->wdr_en)
++				vic_reg_writel(vic, VIC_DMA_Y_CH1_BUF0, vic->snap_paddr + imagesize);
++			vic_reg_writel(vic, VIC_DMA_CONFIG,
++			(1	<< 31) // enable dma
++			| (num	<< 16) // get > max
++			| (0	<<  3) // use buffer num
++			| (0	<<  0) // raw
++			);
++			while(loop){
++				ret = wait_for_completion_interruptible(&vic->snap_comp);
++				if (ret >= 0)
++					break;
++				loop--;
++			}
++			if(!loop){
++				dev_err(vic->dev, "snapraw timeout!\n");
++				goto exit;
++			}
++
++			vic->dma_complete = 0;
++			/* save raw */
++			fd = filp_open("/tmp/snap.raw", O_CREAT | O_WRONLY | O_TRUNC, 00766);
++			if (fd < 0) {
++				dev_err(vic->dev, "Failed to open /tmp/snap.raw\n");
++				goto exit;
++			}
++
++			/* write file */
++			old_fs = get_fs();
++			set_fs(KERNEL_DS);
++			pos = &(fd->f_pos);
++			vfs_write(fd, vic->snap_vaddr, imagesize, pos);
++			if(vic->sensor_info->wdr_en)
++				vfs_write(fd, vic->snap_vaddr + imagesize, imagesize, pos);
++			filp_close(fd, NULL);
++			set_fs(old_fs);
++		}
++	}
++
++exit:
++	kfree(vic->snap_vaddr);
++	vic->snap_paddr = 0;
++
++	return count;
++}
++
++static DEVICE_ATTR(dump_vic, S_IRUGO|S_IWUSR, dump_vic, NULL);
++static DEVICE_ATTR(vic_dma_debug, S_IRUGO|S_IWUSR, NULL, vic_dma_debug);
++
++static struct attribute *vic_debug_attrs[] = {
++        &dev_attr_dump_vic.attr,
++#ifdef CONFIG_VIC_DMA_ROUTE
++	&dev_attr_vic_dma_debug.attr,
++#endif
++	NULL,
++};
++
++static struct attribute_group vic_debug_attr_group = {
++        .name   = "debug",
++        .attrs  = vic_debug_attrs,
++};
++
++int bypass_video_g_ctrl(struct file *file, void *fh, struct v4l2_control *a)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct isp_device 	*isp	= ispcam->isp;
++	struct sensor_device *sensor = &isp->ispcam->sensor;
++	int ret = 0;
++
++	ret = v4l2_g_ctrl(sensor->isd->sd->ctrl_handler, a);
++	if(ret < 0) {
++		dev_err(isp->dev, "failed to get ID:%d!\n", a->id);
++	}
++	return ret;
++}
++
++int bypass_video_s_ctrl(struct file *file, void *fh, struct v4l2_control *a)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct isp_device 	*isp	= ispcam->isp;
++	struct sensor_device *sensor = &isp->ispcam->sensor;
++	int ret = 0;
++
++	ret = v4l2_s_ctrl(NULL, sensor->isd->sd->ctrl_handler, a);
++	if(ret < 0) {
++		dev_err(isp->dev, "failed to set ID:%d!\n", a->id);
++	}
++	return ret;
++}
++
++int vic_video_nr_map[3] = {
++	INGENIC_VIC0_VIDEO_NR,
++	INGENIC_VIC1_VIDEO_NR,
++	INGENIC_VIC2_VIDEO_NR,
++};
++
++static int vic_comp_bind(struct device *comp, struct device *master,
++                              void *master_data)
++{
++	struct vic_device *vic = dev_get_drvdata(comp);
++	struct ispcam_device *ispcam = (struct ispcam_device *)master_data;
++	struct v4l2_device *v4l2_dev = &ispcam->v4l2_dev;
++	struct v4l2_subdev *sd = &vic->sd;
++	int ret = 0;
++	int nr = vic_video_nr_map[ispcam->dev_nr];
++	struct isp_video_device *ispvideo = &vic->ispvideo;
++	char name[32];
++
++	//dev_info(comp, "--------%s, %d \n", __func__, __LINE__);
++	/* link subdev to master.*/
++	vic->ispcam = (void *)ispcam;
++	ispcam->vic = vic;
++
++	v4l2_subdev_init(sd, &vic_subdev_ops);
++
++
++	sd->owner = THIS_MODULE;
++	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++	strscpy(sd->name, dev_name(comp), sizeof(sd->name));
++	v4l2_set_subdevdata(sd, vic);
++
++	/* init vic pads. */
++	vic->pads = kzalloc(sizeof(struct media_pad) * VIC_NUM_PADS, GFP_KERNEL);
++	if(!vic->pads) {
++		ret = -ENOMEM;
++		goto err_alloc_pads;
++	}
++	vic->pads[0].index = VIC_PAD_SINK;
++	vic->pads[0].flags = MEDIA_PAD_FL_SINK;	/* CSI->VIC, MIPI Interface*/
++	vic->pads[1].index = VIC_PAD_SOURCE;
++	vic->pads[1].flags = MEDIA_PAD_FL_SOURCE;
++
++	ret = media_entity_pads_init(&sd->entity, VIC_NUM_PADS, vic->pads);
++
++	/*3. register v4l2_subdev*/
++	sd->entity.function = MEDIA_ENT_F_IO_V4L;
++	ret = v4l2_device_register_subdev(v4l2_dev, sd);
++	if(ret < 0) {
++		dev_err(comp, "Failed to register v4l2_subdev for vic\n");
++		goto err_subdev_register;
++	}
++
++#ifdef CONFIG_VIC_DMA_ROUTE
++	init_completion(&vic->snap_comp);
++
++	ispvideo->ispcam = ispcam;
++	ispvideo->bypass = 1;
++	sprintf(name, "%s", dev_name(vic->dev));
++	ret = isp_video_init(ispvideo, name, &vic_video_ops);
++	if(ret < 0) {
++		/*TODO:*/
++
++	}
++
++	ret = isp_video_register(ispvideo, &ispcam->v4l2_dev, nr);
++	if(ret < 0) {
++		/*TODO:*/
++	};
++#endif
++
++err_subdev_register:
++err_alloc_pads:
++
++
++	return ret;
++}
++
++
++static void vic_comp_unbind(struct device *comp, struct device *master,
++                                 void *master_data)
++{
++        struct vic_device *vic = dev_get_drvdata(comp);
++
++	dev_info(comp, "---TODO: %p-----%s, %d \n", vic, __func__, __LINE__);
++
++}
++
++static const struct component_ops vic_comp_ops = {
++        .bind = vic_comp_bind,
++        .unbind = vic_comp_unbind,
++};
++
++static int vic_err[13] = {0};
++
++static irqreturn_t vic_irq_handler(int irq, void *data)
++{
++	struct vic_device *vic = (struct vic_device *)data;
++	unsigned int status = 0;
++	unsigned int status2 = 0;
++	struct isp_video_buffer *isp_buffer = NULL;
++	unsigned int regval = 0;
++	unsigned int complete_num = 0;
++
++	spin_lock(&vic->lock);
++	status = vic_reg_readl(vic, VIC_INT_STA);
++	status2 = vic_reg_readl(vic, VIC_INT_STA2);
++//	printk("VIC_INT_STA=%x\n", status);
++//	printk("VIC_INT_STA2=%x\n", status2);
++	/* DMA FRAME DONE */
++	if(status2 & (1 << 0)) {
++		vic->frame_capture_counter++;
++		//printk(KERN_DEBUG "%d: vic->buffer_count=0x%x\n", vic->frame_capture_counter, vic->buffer_count);
++
++#ifdef CONFIG_VIC_DMA_ROUTE
++		if(dma_debug_en){
++			vic->dma_complete++;
++		} else {
++			isp_buffer = list_first_entry_or_null(&vic->dma_queued_list, struct isp_video_buffer, list_entry);
++			if(!isp_buffer) {
++				dev_err(vic->dev, "[warning] no isp_buffer found in dma_queued_list when interrupt happend!\n");
++				goto done;
++			}
++
++			list_del(&isp_buffer->list_entry);
++			vic->buffer_count--;
++
++			isp_buffer->vb2.vb2_buf.timestamp = ktime_get_ns();
++			isp_buffer->vb2.sequence = vic->framenum++;
++
++			vb2_buffer_done(&isp_buffer->vb2.vb2_buf, VB2_BUF_STATE_DONE);
++
++			if(vic->buffer_count <= VIC_STOP_BUFFER_COUNT)
++			{
++				vic->stop_flag = 1;
++				regval = vic_reg_readl(vic, VIC_DMA_CONFIG);
++				regval &= ~(1 << 31);
++				vic_reg_writel(vic, VIC_DMA_CONFIG, regval);
++				vic_stop_counter++;
++				goto done;
++			}
++		}
++#endif
++	}
++
++	if(status2 & (1 << 1))
++		if(dma_debug_en)
++			vic->dma_complete++;
++
++#if 0
++	if(status & (1 << 9)) {
++		//dev_err(vic->dev,
++		printk(KERN_DEBUG "vic->frame_capture_counter=%d, Image output limit too small! VIC_INT_STA=%x\n", vic->frame_capture_counter, status);
++		/* lgwang -- reset vic */
++		vic->global_reset = 1;
++		vic_reg_writel(vic, VIC_CONTROL, 0x4);
++		vic->stop_flag = 1;
++		vic_stop_counter++;
++	}
++#endif
++	if((1 << 9) & status) {
++		vic_err[11]++;
++		dev_err(vic->dev, "Err [VIC_INT] : frame asfifo ovf!!!!!\n");
++	}
++	if((1 << 10) & status) {
++		vic_err[0]++;
++		dev_err(vic->dev, "Err [VIC_INT] : hor err ch0 !!!!!\n");
++	}
++	if((1 << 11) & status) {
++		vic_err[12]++;
++		dev_err(vic->dev, "Err [VIC_INT] : hor err ch1 !!!!!\n");
++	}
++	if((1 << 12) & status) {
++		vic_err[12]++;
++		dev_err(vic->dev, "Err [VIC_INT] : hor err ch2 !!!!!\n");
++	}
++	if((1 << 13) & status) {
++		vic_err[12]++;
++		dev_err(vic->dev, "Err [VIC_INT] : hor err ch3 !!!!!\n");
++	}
++	if((1 << 14) & status) {
++		vic_err[1]++;
++		dev_err(vic->dev, "Err [VIC_INT] : ver err ch0 !!!!!\n");
++	}
++	if((1 << 15) & status) {
++		vic_err[12]++;
++		dev_err(vic->dev, "Err [VIC_INT] : ver err ch1 !!!!!\n");
++	}
++	if((1 << 16) & status) {
++		vic_err[12]++;
++		dev_err(vic->dev, "Err [VIC_INT] : ver err ch2 !!!!!\n");
++	}
++	if((1 << 17) & status) {
++		vic_err[12]++;
++		dev_err(vic->dev, "Err [VIC_INT] : ver err ch3 !!!!!\n");
++	}
++	if((1 << 18) & status) {
++		vic_err[2]++;
++		dev_err(vic->dev, "Err [VIC_INT] : hvf err !!!!!\n");
++	}
++	if((1 << 19) & status) {
++		vic_err[3]++;
++		dev_err(vic->dev, "Err [VIC_INT] : dvp hcomp err!!!!\n");
++	}
++	if((1 << 20) & status) {
++		vic_err[4]++;
++		dev_err(vic->dev, "Err [VIC_INT] : dma syfifo ovf!!!\n");
++	}
++	if((1 << 21) & status) {
++		vic_err[5]++;
++		dev_err(vic->dev, "Err [VIC_INT] : control limit err!!!\n");
++	}
++	if((1 << 22) & status) {
++		vic_err[6]++;
++		dev_err(vic->dev, "Err [VIC_INT] : image syfifo ovf !!!\n");
++	}
++	if((1 << 23) & status) {
++		vic_err[7]++;
++		dev_err(vic->dev, "Err [VIC_INT] : mipi fid asfifo ovf!!!\n");
++	}
++	if((1 << 24) & status) {
++		vic_err[8]++;
++		dev_err(vic->dev, "Err [VIC_INT] : mipi ch0 hcomp err !!!\n");
++	}
++	if((1 << 25) & status) {
++		vic_err[12]++;
++		dev_err(vic->dev, "Err [VIC_INT] : mipi ch1 hcomp err !!!\n");
++	}
++	if((1 << 26) & status) {
++		vic_err[12]++;
++		dev_err(vic->dev, "Err [VIC_INT] : mipi ch2 hcomp err !!!\n");
++	}
++	if((1 << 27) & status) {
++		vic_err[12]++;
++		dev_err(vic->dev, "Err [VIC_INT] : mipi ch3 hcomp err !!!\n");
++	}
++	if((1 << 28) & status) {
++		vic_err[9]++;
++		dev_err(vic->dev, "Err [VIC_INT] : mipi ch0 vcomp err !!!\n");
++	}
++	if((1 << 29) & status) {
++		vic_err[12]++;
++		dev_err(vic->dev, "Err [VIC_INT] : mipi ch1 vcomp err !!!\n");
++	}
++	if((1 << 30) & status) {
++		vic_err[12]++;
++		dev_err(vic->dev, "Err [VIC_INT] : mipi ch2 vcomp err !!!\n");
++	}
++	if((1 << 31) & status) {
++		vic_err[12]++;
++		dev_err(vic->dev, "Err [VIC_INT] : mipi ch3 vcomp err !!!\n");
++	}
++
++	if(dma_debug_en)
++	{
++		if(vic->sensor_info->wdr_en)
++			complete_num = 2;
++		else
++			complete_num = 1;
++
++		if(vic->dma_complete == complete_num)
++		{
++			vic_reg_writel(vic, VIC_DMA_CONFIG, 0);
++			complete(&vic->snap_comp);
++		}
++	}
++done:
++	vic_reg_writel(vic, VIC_INT_CLR, status);
++	vic_reg_writel(vic, VIC_INT_CLR2, status2);
++	spin_unlock(&vic->lock);
++	return IRQ_HANDLED;
++
++}
++
++static int ingenic_vic_probe(struct platform_device *pdev)
++{
++
++	struct vic_device *vic = NULL;
++	struct resource *regs = NULL;
++	int ret = 0;
++
++	vic = kzalloc(sizeof(struct vic_device), GFP_KERNEL);
++	if(!vic) {
++		pr_err("Failed to alloc vic dev [%s]\n", pdev->name);
++		return -ENOMEM;
++	}
++
++	vic->dev = &pdev->dev;
++	platform_set_drvdata(pdev, vic);
++
++
++	ingenic_vic_parse_dt(vic);
++
++	vic->irq = platform_get_irq(pdev, 0);
++	if(vic->irq < 0) {
++		dev_warn(&pdev->dev, "No CSI IRQ specified\n");
++	}
++
++	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if(!regs) {
++		dev_err(&pdev->dev, "No iomem resource!\n");
++		goto err_get_resource;
++	}
++
++	vic->iobase = devm_ioremap_resource(&pdev->dev, regs);
++	if(!vic->iobase) {
++		goto err_ioremap;
++	}
++
++	spin_lock_init(&vic->lock);
++	INIT_LIST_HEAD(&vic->dma_queued_list);
++
++	ret = devm_request_irq(vic->dev, vic->irq, vic_irq_handler, 0,
++			dev_name(vic->dev), vic);
++	if(ret) {
++		dev_err(vic->dev, "request irq failed!\n");
++		goto err_request_irq;
++	}
++
++	ret = sysfs_create_group(&vic->dev->kobj, &vic_debug_attr_group);
++	if (ret) {
++		dev_err(vic->dev, "device create sysfs group failed\n");
++
++		ret = -EINVAL;
++		goto err_sys_group;
++	}
++
++	ret = component_add(vic->dev, &vic_comp_ops);
++	if(ret < 0) {
++		dev_err(vic->dev, "Failed to add component vic!\n");
++		goto err_component;
++	}
++
++	return 0;
++err_component:
++err_sys_group:
++err_request_irq:
++err_ioremap:
++err_get_resource:
++	return ret;
++}
++
++
++
++static int ingenic_vic_remove(struct platform_device *pdev)
++{
++
++	return 0;
++}
++
++
++
++static const struct of_device_id ingenic_vic_dt_match[] = {
++        { .compatible = "ingenic,x2500-vic" },
++        { }
++};
++
++MODULE_DEVICE_TABLE(of, ingenic_vic_dt_match);
++
++static int __maybe_unused ingenic_vic_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	struct vic_device *vic = dev_get_drvdata(&pdev->dev);
++
++	if(vic->enabled){
++		dev_err(vic->dev, "faild to suspend, vic is streaming on\n");
++		return -EBUSY;
++	}
++
++        return 0;
++}
++
++static int __maybe_unused ingenic_vic_resume(struct platform_device *pdev)
++{
++        return 0;
++}
++
++static struct platform_driver ingenic_vic_driver = {
++        .probe = ingenic_vic_probe,
++        .remove = ingenic_vic_remove,
++	.suspend = ingenic_vic_suspend,
++	.resume = ingenic_vic_resume,
++        .driver = {
++                .name = "ingenic-vic",
++                .of_match_table = ingenic_vic_dt_match,
++        },
++};
++
++module_platform_driver(ingenic_vic_driver);
++
++MODULE_ALIAS("platform:ingenic-vic");
++MODULE_DESCRIPTION("ingenic vic subsystem");
++MODULE_AUTHOR("qipengzhen <aric.pzqi@ingenic.com>");
++MODULE_LICENSE("GPL v2");
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/Kconfig b/module_drivers/drivers/media/platform/ingenic-isp/Kconfig
+new file mode 100644
+index 000000000..d4a2e5b98
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/Kconfig
+@@ -0,0 +1,113 @@
++config VIC_DMA_ROUTE
++	bool "vic dma out route enable"
++	default n
++	depends on VIDEO_INGENIC_ISP
++
++config MSCA_BDEV
++	bool "mscaler bdev support"
++	default n
++	depends on VIDEO_INGENIC_ISP
++
++# halley5 board
++menuconfig HALLEY5_CAMERA_BOARD
++	bool "halley5_camera_board"
++	depends on VIDEO_INGENIC_ISP
++	default n
++	help
++	  Say Y here to enable support for halley5_camera_boards.
++
++config RD_X2000_HALLEY5_CAMERA_1V0
++	bool "halley5 camera driver for RD_X2000_HALLEY5_CAMERA_1V0"
++	depends on HALLEY5_CAMERA_BOARD
++	select INGENIC_ISP_CAMERA_AR0144
++	select INGENIC_ISP_CAMERA_AR0234
++
++config RD_X2000_HALLEY5_CAMERA_2V1
++	bool "halley5 camera driver for RD_X2000_HALLEY5_CAMERA_2V1"
++	depends on HALLEY5_CAMERA_BOARD
++	select INGENIC_ISP_CAMERA_OV2735B
++	select INGENIC_ISP_CAMERA_OV2735A
++
++config RD_X2000_HALLEY5_CAMERA_4V2
++	bool "halley5 camera driver for RD_X2000_HALLEY5_CAMERA_4V2"
++	depends on HALLEY5_CAMERA_BOARD
++	select INGENIC_ISP_CAMERA_OV2735B
++	select INGENIC_ISP_CAMERA_OV2735A
++
++config RD_X2000_HALLEY5_CAMERA_4V3
++	bool "halley5 camera driver for RD_X2000_HALLEY5_CAMERA_4V3"
++	depends on HALLEY5_CAMERA_BOARD
++	select INGENIC_ISP_CAMERA_OV2735A
++	select V4L2_FWNODE
++
++config RD_X2000_HALLEY5_CAMERA_3V2
++	bool "halley5 camera driver for RD_X2000_HALLEY5_CAMERA_3V2"
++	depends on HALLEY5_CAMERA_BOARD
++	select INGENIC_ISP_CAMERA_OV4689
++
++choice
++	prompt "ov4689 resolution and frame rate select"
++	depends on RD_X2000_HALLEY5_CAMERA_3V2
++	default OV4689_1080P_30FPS
++	help
++	Select ov4689 sensor's resolution and frame rate that driver supported.
++
++config OV4689_1080P_120FPS
++	bool "OV4689_1080P_120fps"
++	depends on RD_X2000_HALLEY5_CAMERA_3V2 || CAMERA_V10
++
++config OV4689_1080P_30FPS
++	bool "OV4689_1080P_30fps"
++	depends on RD_X2000_HALLEY5_CAMERA_3V2 || CAMERA_V10
++
++config OV4689_2048X1520_30FPS
++	bool "ov4689_2048x1520_30fps"
++	depends on RD_X2000_HALLEY5_CAMERA_3V2 || CAMERA_V10
++endchoice
++
++config RD_X2000_HALLEY5_CAMERA_5V0
++	bool "halley5 camera driver for RD_X2000_HALLEY5_CAMERA_5V0"
++	depends on HALLEY5_CAMERA_BOARD
++	select INGENIC_ISP_CAMERA_AR0144
++
++config RD_X2500_HIPPO_CAMERA_1V1
++	bool "halley5 camera driver for RD_X2500_HIPPO_CAMERA_1V1"
++	depends on HALLEY5_CAMERA_BOARD
++	select INGENIC_ISP_CAMERA_SC230AI
++
++# gewu board
++menuconfig GEWU_CAMERA_BOARD
++	bool "gewu_camera_board"
++	depends on VIDEO_INGENIC_ISP
++	default n
++	help
++	  Say Y here to enable support for gewu_camera_boards.
++
++config CAMERA_V10
++	bool "gewu camera driver for CAMERA_1.0"
++	depends on GEWU_CAMERA_BOARD
++	select INGENIC_ISP_CAMERA_OV4689
++
++choice
++	prompt "ov4689 resolution and frame rate select"
++	depends on CAMERA_V10
++	default GEWU_OV4689_1080P_30FPS
++	help
++	Select ov4689 sensor's resolution and frame rate that driver supported.
++
++config GEWU_OV4689_1080P_120FPS
++	bool "OV4689_1080P_120fps"
++	select OV4689_1080P_120FPS
++	depends on CAMERA_V10
++
++config GEWU_OV4689_1080P_30FPS
++	bool "OV4689_1080P_30fps"
++	select OV4689_1080P_30FPS
++	depends on CAMERA_V10
++
++config GEWU_OV4689_2048X1520_30FPS
++	bool "ov4689_2048x1520_30fps"
++	select OV4689_2048X1520_30FPS
++	depends on CAMERA_V10
++endchoice
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/Makefile b/module_drivers/drivers/media/platform/ingenic-isp/Makefile
+new file mode 100644
+index 000000000..afd5f085b
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/Makefile
+@@ -0,0 +1,20 @@
++obj-y	+= isp-drv.o
++obj-y	+= csi.o
++obj-y	+= mscaler.o
++obj-y	+= vic.o
++obj-y	+= isp.o
++obj-y	+= sensor.o
++obj-y	+= isp-video.o
++obj-y	+= isp-core-tuning.o
++obj-$(CONFIG_MSCA_BDEV)	+= mscaler-bdev.o
++
++ccflags-y += -I$(srctree)/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc
++ccflags-$(CONFIG_MSCA_BDEV) += -I$(srctree)/module_drivers/drivers/media/platform/ingenic-vcodec/helix
++obj-y	+= isp-core/
++
++FILE=$(srctree)/module_drivers/drivers/media/platform/ingenic-isp/isp-core/isp-core.a_shipped
++ifeq ($(FILE), $(wildcard $(FILE)))
++$(error "please remove overlay isp-core.a_shipped")
++endif
++
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/csi-regs.h b/module_drivers/drivers/media/platform/ingenic-isp/csi-regs.h
+new file mode 100644
+index 000000000..56c0fddd8
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/csi-regs.h
+@@ -0,0 +1,51 @@
++#ifndef __INGENIC_ISP_CSI_H__
++#define __INGENIC_ISP_CSI_H__
++
++#define VERSION				0x00
++#define N_LANES				0x04
++#define PHY_SHUTDOWNZ			0x08
++#define DPHY_RSTZ			0x0C
++#define CSI2_RESETN			0x10
++#define PHY_STATE			0x14
++#define DATA_IDS_1			0x18
++#define DATA_IDS_2			0x1C
++#define ERR1				0x20
++#define ERR2				0x24
++#define MASK1				0x28
++#define MASK2				0x2C
++#define PHY_TST_CTRL0       		0x30
++#define PHY_TST_CTRL1       		0x34
++
++#define VC0_FRAME_NUM			0x40	/*[31:16] FS End, [15:0] FS Start*/
++#define VC1_FRAME_NUM			0x44
++#define VC2_FRAME_NUM			0x48
++#define VC3_FRAME_NUM			0x4c
++#define VC0_LINE_NUM			0x50	/*[31:16] Line End, [15:0] Line Start*/
++#define VC1_LINE_NUM			0x54
++#define VC2_LINE_NUM			0x58
++#define VC3_LINE_NUM			0x60
++
++#define csi_readl(port, reg)						\
++	__raw_readl((unsigned int *)((port)->base + reg))
++#define csi_writel(port, reg, value)					\
++	__raw_writel((value), (unsigned int *)((port)->base + reg))
++
++#define csi_core_writel(csi, addr, value)				\
++	writel(value, (unsigned int *)((csi)->iobase + addr))
++#define csi_core_readl(csi, addr)					\
++	readl((unsigned int *)((csi)->iobase + addr))
++
++
++#define CSI_PHY_IOBASE	0x10076000
++#define CSI_PHY_1C2C_MODE	0xc4
++#define CSI_PHY_PRECOUNTER_IN_CLK	0xb8
++#define CSI_PHY_PRECOUNTER_IN_DATA	0xbc
++
++#define csi_phy_writel(csi, addr, value)					\
++	writel(value, (unsigned int *)((csi)->phy_base + addr))
++
++#define csi_phy_readl(csi, addr)						\
++       	readl((unsigned int *)((csi)->phy_base + addr))
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/csi.c b/module_drivers/drivers/media/platform/ingenic-isp/csi.c
+new file mode 100644
+index 000000000..4df28ed54
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/csi.c
+@@ -0,0 +1,482 @@
++#include <linux/clk.h>
++#include <linux/media-bus-format.h>
++#include <linux/media.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_graph.h>
++#include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
++#include <linux/pm_domain.h>
++#include <linux/slab.h>
++#include <linux/videodev2.h>
++#include <linux/component.h>
++
++#include <media/media-device.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-event.h>
++
++
++#include "isp-drv.h"
++#include "csi-regs.h"
++
++static const struct v4l2_subdev_core_ops csi_subdev_core_ops = {
++        .log_status = v4l2_ctrl_subdev_log_status,
++        .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
++        .unsubscribe_event = v4l2_event_subdev_unsubscribe,
++};
++
++static int csi_subdev_set_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct csi_device *csi = v4l2_get_subdevdata(sd);
++	struct media_pad *remote = NULL;
++	struct v4l2_subdev *remote_sd = NULL;
++	int ret = 0;
++
++	remote = media_entity_remote_pad(&csi->pads[CSI_PAD_SINK]);
++	remote_sd = media_entity_to_v4l2_subdev(remote->entity);
++
++	ret = v4l2_subdev_call(remote_sd, pad, set_fmt, NULL, format);
++	if(ret < 0) {
++		dev_dbg(csi->dev, "Failed to set_fmt from remote pad\n");
++	}
++
++	return 0;
++}
++static int csi_subdev_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct csi_device *csi = v4l2_get_subdevdata(sd);
++	struct media_pad *remote = NULL;
++	struct v4l2_subdev *remote_sd = NULL;
++	struct v4l2_subdev_format remote_subdev_fmt;
++	int ret = 0;
++
++	remote = media_entity_remote_pad(&csi->pads[CSI_PAD_SINK]);
++	remote_sd = media_entity_to_v4l2_subdev(remote->entity);
++
++	/*获��当�格�，�制到输出格�.*/
++	remote_subdev_fmt.pad = remote->index;
++	remote_subdev_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	ret = v4l2_subdev_call(remote_sd, pad, get_fmt, NULL, &remote_subdev_fmt);
++	if(ret < 0) {
++		dev_err(csi->dev, "Failed to get_fmt from remote pad\n");
++		return -EINVAL;
++	}
++
++	memcpy(&format->format, &remote_subdev_fmt.format, sizeof(format->format));
++
++	//printk("----%s, %d, format->pad: %d\n", __func__, __LINE__, format->pad);
++	return 0;
++}
++
++
++static const struct v4l2_subdev_pad_ops csi_subdev_pad_ops = {
++        .set_fmt                = csi_subdev_set_fmt,
++        .get_fmt                = csi_subdev_get_fmt,
++	/*
++        .init_cfg               = csi_subdev_init_cfg,
++        .enum_mbus_code         = csi_subdev_enum_mbus_code,
++        .enum_frame_size        = csi_subdev_enum_frame_size,
++        .get_fmt                = csi_subdev_get_fmt,
++	*/
++};
++
++struct phy_reseter {
++	struct csi_device *csi[2];
++	unsigned int phy_started[2];
++};
++
++struct phy_reseter global_phy_reseter = {
++	.csi = {NULL, NULL},
++	.phy_started = {0, 0}
++};
++
++DEFINE_SPINLOCK(reset_lock);
++
++static unsigned char csi_core_write_part(struct csi_device *csi,unsigned int address,
++                                                unsigned int data, unsigned char shift, unsigned char width)
++{
++        unsigned int mask = (1 << width) - 1;
++        unsigned int temp = csi_core_readl(csi, address);
++
++        temp &= ~(mask << shift);
++        temp |= (data & mask) << shift;
++        csi_core_writel(csi, address, temp);
++
++        return 0;
++}
++
++static inline int csi_core_write_io(unsigned int iobase, unsigned int address, unsigned int data, unsigned char shift, unsigned char width)
++{
++        unsigned int mask = (1 << width) - 1;
++        unsigned int temp = readl((unsigned int *)(iobase + address));
++
++        temp &= ~(mask << shift);
++        temp |= (data & mask) << shift;
++        writel(temp, (unsigned int *)(iobase + address));
++	return 0;
++}
++
++
++#define CSI0_IOBASE	0xb0074000
++#define CSI1_IOBASE	0xb0073000
++static int csi_phy_start(struct csi_device *csi, struct phy_reseter *reseter)
++{
++	unsigned long flags;
++	/*already reseted.*/
++	spin_lock_irqsave(&reset_lock, flags);
++	if(reseter->phy_started[0] || reseter->phy_started[1]) {
++		reseter->phy_started[csi->reset_index] = 1;
++		spin_unlock_irqrestore(&reset_lock, flags);
++		return 0;
++	}
++
++	/* CSI0 and CSI1 reset at the same time. */
++	csi_core_write_io(CSI0_IOBASE, DPHY_RSTZ, 0, 0, 1);
++	csi_core_write_io(CSI1_IOBASE, DPHY_RSTZ, 0, 0, 1);
++
++	csi_core_write_io(CSI0_IOBASE, DPHY_RSTZ, 1, 0, 1);
++	csi_core_write_io(CSI1_IOBASE, DPHY_RSTZ, 1, 0, 1);
++
++	reseter->phy_started[csi->reset_index] = 1;
++	spin_unlock_irqrestore(&reset_lock, flags);
++
++
++	return 0;
++}
++
++static void csi_phy_stop(struct csi_device *csi, struct phy_reseter *reseter)
++{
++
++	unsigned long flags;
++
++	/* CSI2_RESET */
++	spin_lock_irqsave(&reset_lock, flags);
++	csi_core_write_part(csi, CSI2_RESETN, 0, 0, 1);
++
++	reseter->phy_started[csi->reset_index] = 0;
++
++	if((reseter->phy_started[0] == 0) && (reseter->phy_started[1] == 0)) {
++		/* shutdown phy. */
++		csi_core_write_io(CSI0_IOBASE, DPHY_RSTZ, 0, 0, 1);
++		csi_core_write_io(CSI1_IOBASE, DPHY_RSTZ, 0, 0, 1);
++	}
++
++	spin_unlock_irqrestore(&reset_lock, flags);
++}
++
++static int csi_subdev_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct csi_device *csi = v4l2_get_subdevdata(sd);
++	struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2 = ispcam_get_bus_mipi_csi2(csi->ispcam);
++	unsigned short nlanes = mipi_csi2->num_data_lanes;
++
++	if(enable) {
++		if(csi->enabled++ > 0) {
++			return 0;
++		}
++
++		if(nlanes > 2)
++			csi_phy_writel(csi, CSI_PHY_1C2C_MODE, 0);	/*1c mode.*/
++		else
++			csi_phy_writel(csi, CSI_PHY_1C2C_MODE, 1);	/*2c mode.*/
++		csi_core_writel(csi, N_LANES, nlanes - 1);
++		csi_phy_start(csi, &global_phy_reseter);
++
++		/* CSI2_RESET */
++		csi_core_write_part(csi, CSI2_RESETN, 0, 0, 1);
++		csi_core_write_part(csi, CSI2_RESETN, 1, 0, 1);
++
++	} else {
++
++		if(--csi->enabled > 0) {
++			return 0;
++		}
++		csi_phy_stop(csi, &global_phy_reseter);
++	}
++
++	return 0;
++}
++
++
++static const struct v4l2_subdev_video_ops csi_subdev_video_ops = {
++        .s_stream = csi_subdev_s_stream,
++};
++
++
++static const struct v4l2_subdev_ops csi_subdev_ops = {
++        .core = &csi_subdev_core_ops,
++        .pad = &csi_subdev_pad_ops,
++        .video = &csi_subdev_video_ops,
++};
++
++static ssize_t
++dump_csi(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct csi_device *csi = dev_get_drvdata(dev);
++	char *p = buf;
++
++	p += sprintf(p, "VERSION	:0x%08x\n",	csi_core_readl(csi, VERSION));
++	p += sprintf(p, "N_LANES	:0x%08x\n",	csi_core_readl(csi, N_LANES));
++	p += sprintf(p, "PHY_SHUTDOWNZ	:0x%08x\n",	csi_core_readl(csi, PHY_SHUTDOWNZ));
++	p += sprintf(p, "DPHY_RSTZ	:0x%08x\n",	csi_core_readl(csi, DPHY_RSTZ));
++	p += sprintf(p, "CSI2_RESETN	:0x%08x\n",	csi_core_readl(csi, CSI2_RESETN));
++	p += sprintf(p, "PHY_STATE	:0x%08x\n",	csi_core_readl(csi, PHY_STATE));
++	p += sprintf(p, "DATA_IDS_1	:0x%08x\n",	csi_core_readl(csi, DATA_IDS_1));
++	p += sprintf(p, "DATA_IDS_2	:0x%08x\n",	csi_core_readl(csi, DATA_IDS_2));
++	p += sprintf(p, "ERR1		:0x%08x\n",	csi_core_readl(csi, ERR1));
++	p += sprintf(p, "ERR2		:0x%08x\n",	csi_core_readl(csi, ERR2));
++	p += sprintf(p, "MASK1		:0x%08x\n",	csi_core_readl(csi, MASK1));
++	p += sprintf(p, "MASK2		:0x%08x\n",	csi_core_readl(csi, MASK2));
++	p += sprintf(p, "PHY_TST_CTRL0  :0x%08x\n",	csi_core_readl(csi, PHY_TST_CTRL0));
++	p += sprintf(p, "PHY_TST_CTRL1  :0x%08x\n",	csi_core_readl(csi, PHY_TST_CTRL1));
++	p += sprintf(p, "VC0_FRAME_NUM	:0x%08x\n",	csi_core_readl(csi, VC0_FRAME_NUM));
++	p += sprintf(p, "VC1_FRAME_NUM	:0x%08x\n",	csi_core_readl(csi, VC1_FRAME_NUM));
++	p += sprintf(p, "VC2_FRAME_NUM	:0x%08x\n",	csi_core_readl(csi, VC2_FRAME_NUM));
++	p += sprintf(p, "VC3_FRAME_NUM	:0x%08x\n",	csi_core_readl(csi, VC3_FRAME_NUM));
++	p += sprintf(p, "VC0_LINE_NUM	:0x%08x\n",	csi_core_readl(csi, VC0_LINE_NUM));
++	p += sprintf(p, "VC1_LINE_NUM	:0x%08x\n",	csi_core_readl(csi, VC1_LINE_NUM));
++	p += sprintf(p, "VC2_LINE_NUM	:0x%08x\n",	csi_core_readl(csi, VC2_LINE_NUM));
++	p += sprintf(p, "VC3_LINE_NUM	:0x%08x\n",	csi_core_readl(csi, VC3_LINE_NUM));
++
++	p += sprintf(p, "CSI_PHY_1C2C_MODE :0x%08x\n", 	csi_phy_readl(csi, CSI_PHY_1C2C_MODE));
++
++	return p - buf;
++}
++
++
++static DEVICE_ATTR(dump_csi, S_IRUGO|S_IWUSR, dump_csi, NULL);
++
++static struct attribute *csi_debug_attrs[] = {
++        &dev_attr_dump_csi.attr,
++	NULL,
++};
++
++static struct attribute_group csi_debug_attr_group = {
++        .name   = "debug",
++        .attrs  = csi_debug_attrs,
++};
++
++
++static int csi_comp_bind(struct device *comp, struct device *master,
++                              void *master_data)
++{
++	struct csi_device *csi = dev_get_drvdata(comp);
++	struct ispcam_device *ispcam = (struct ispcam_device *)master_data;
++	struct v4l2_device *v4l2_dev = &ispcam->v4l2_dev;
++	struct v4l2_subdev *sd = &csi->sd;
++	int ret = 0;
++
++	//dev_info(comp, "----dev_name(comp): %s----%s, %d \n", dev_name(comp), __func__, __LINE__);
++
++	/* link subdev to master.*/
++	csi->ispcam = (void *)ispcam;
++	ispcam->csi = csi;
++
++	/*1. register supported subdev ctrls.*/
++
++
++	/*2. init v4l2_subdev*/
++
++	v4l2_subdev_init(sd, &csi_subdev_ops);
++
++	sd->owner = THIS_MODULE;
++	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++	strscpy(sd->name, dev_name(comp), sizeof(sd->name));
++	v4l2_set_subdevdata(sd, csi);
++
++
++	/* init csi pads. */
++	csi->pads = kzalloc(sizeof(struct media_pad) * CSI_NUM_PADS, GFP_KERNEL);
++	if(!csi->pads) {
++		ret = -ENOMEM;
++		goto err_alloc_pads;
++	}
++	csi->pads[0].index = CSI_PAD_SINK;
++	csi->pads[0].flags = MEDIA_PAD_FL_SINK;
++	csi->pads[1].index = CSI_PAD_SOURCE;
++	csi->pads[1].flags = MEDIA_PAD_FL_SOURCE;
++
++	ret = media_entity_pads_init(&sd->entity, CSI_NUM_PADS, csi->pads);
++
++	/*3. register v4l2_subdev*/
++	sd->entity.function = MEDIA_ENT_F_IO_V4L;
++	ret = v4l2_device_register_subdev(v4l2_dev, sd);
++	if(ret < 0) {
++		dev_err(comp, "Failed to register v4l2_subdev for csi\n");
++		goto err_subdev_register;
++	}
++
++
++	return 0;
++err_subdev_register:
++err_alloc_pads:
++	return ret;
++}
++
++
++static void csi_comp_unbind(struct device *comp, struct device *master,
++                                 void *master_data)
++{
++        struct csi_device *csi = dev_get_drvdata(comp);
++
++	dev_info(comp, "----TODO-implement unbind: %p---%s, %d \n",csi, __func__, __LINE__);
++}
++
++
++
++static const struct component_ops csi_comp_ops = {
++        .bind = csi_comp_bind,
++        .unbind = csi_comp_unbind,
++};
++
++
++static int ingenic_csi_probe(struct platform_device *pdev)
++{
++
++	struct csi_device *csi = NULL;
++	struct resource *regs = NULL;
++
++	int ret = 0;
++	int i = 0;
++
++	csi = kzalloc(sizeof(struct csi_device), GFP_KERNEL);
++	if(!csi) {
++		pr_err("Failed to alloc csi dev [%s]\n", pdev->name);
++		return -ENOMEM;
++	}
++
++	csi->dev = &pdev->dev;
++	platform_set_drvdata(pdev, csi);
++	dev_set_drvdata(csi->dev, csi);
++
++	csi->irq = platform_get_irq(pdev, 0);
++	if(csi->irq < 0) {
++		dev_warn(&pdev->dev, "No CSI IRQ specified\n");
++	}
++
++	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if(!regs) {
++		dev_err(&pdev->dev, "No iomem resource!\n");
++		goto err_get_resource;
++	}
++
++	csi->iobase = devm_ioremap_resource(&pdev->dev, regs);
++	if(!csi->iobase) {
++		goto err_ioremap;
++	}
++
++	of_property_read_u32(csi->dev->of_node, "clk_precounter", &csi->clk_precounter);
++	of_property_read_u32(csi->dev->of_node, "data_precounter", &csi->data_precounter);
++
++	csi->phy_base = CSI_PHY_IOBASE | 0xa0000000;
++
++	/*TODO: clk*/
++	csi->gate_clk = of_clk_get(csi->dev->of_node, 0);
++	if(!csi->gate_clk) {
++		dev_err(csi->dev, "failed to get gate clk\n");
++		goto err_gate_clk;
++	}
++	clk_prepare_enable(csi->gate_clk);
++
++	if(csi->clk_precounter)
++		csi_phy_writel(csi, CSI_PHY_PRECOUNTER_IN_CLK, csi->clk_precounter);
++	if(csi->data_precounter)
++		csi_phy_writel(csi, CSI_PHY_PRECOUNTER_IN_DATA, csi->data_precounter);
++
++	ret = sysfs_create_group(&csi->dev->kobj, &csi_debug_attr_group);
++	if (ret) {
++		dev_err(csi->dev, "device create sysfs group failed\n");
++
++		ret = -EINVAL;
++		goto err_sys_group;
++	}
++
++	for(i = 0; i < 2; i++) {
++		if(global_phy_reseter.csi[i] == NULL) {
++			global_phy_reseter.csi[i] = csi;
++			csi->reset_index = i;
++			break;
++		}
++	}
++
++	ret = component_add(csi->dev, &csi_comp_ops);
++	if(ret < 0) {
++		dev_err(csi->dev, "Failed to add component csi!\n");
++	}
++
++	return 0;
++err_sys_group:
++err_gate_clk:
++err_ioremap:
++err_get_resource:
++
++	return ret;
++}
++
++
++
++static int ingenic_csi_remove(struct platform_device *pdev)
++{
++	struct csi_device *csi = dev_get_drvdata(&pdev->dev);
++
++	clk_disable_unprepare(csi->gate_clk);
++	return 0;
++}
++
++
++
++static const struct of_device_id ingenic_csi_dt_match[] = {
++        { .compatible = "ingenic,x2000-csi" },
++        { .compatible = "ingenic,m300-csi" },
++        { }
++};
++
++MODULE_DEVICE_TABLE(of, ingenic_csi_dt_match);
++
++static int __maybe_unused ingenic_csi_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	struct csi_device *csi = dev_get_drvdata(&pdev->dev);
++
++	if(csi->enabled){
++		dev_err(csi->dev, "faild to suspend, csi is streaming on\n");
++		return -EBUSY;
++	}
++
++	clk_disable_unprepare(csi->gate_clk);
++        return 0;
++}
++
++static int __maybe_unused ingenic_csi_resume(struct platform_device *pdev)
++{
++	struct csi_device *csi = dev_get_drvdata(&pdev->dev);
++
++	clk_prepare_enable(csi->gate_clk);
++        return 0;
++}
++
++
++static struct platform_driver ingenic_csi_driver = {
++        .probe = ingenic_csi_probe,
++        .remove = ingenic_csi_remove,
++	.suspend = ingenic_csi_suspend,
++	.resume = ingenic_csi_resume,
++        .driver = {
++                .name = "ingenic-csi",
++                .of_match_table = ingenic_csi_dt_match,
++        },
++};
++
++module_platform_driver(ingenic_csi_driver);
++
++MODULE_ALIAS("platform:ingenic-csi");
++MODULE_DESCRIPTION("ingenic csi subsystem");
++MODULE_AUTHOR("qipengzhen <aric.pzqi@ingenic.com>");
++MODULE_LICENSE("GPL v2");
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-core-tuning.c b/module_drivers/drivers/media/platform/ingenic-isp/isp-core-tuning.c
+new file mode 100644
+index 000000000..cb05679f1
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-core-tuning.c
+@@ -0,0 +1,1130 @@
++#include <linux/videodev2.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include "isp-drv.h"
++
++static inline int apical_isp_hflip_s_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	int ret = 0;
++	unsigned int value = 0;
++	value = isp->ctrls.hflip;
++
++	tisp_mirror_enable(&core->core_tuning, value);
++
++	return ret;
++}
++
++static inline int apical_isp_vflip_s_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	int ret = 0;
++	unsigned int value = 0;
++	value = isp->ctrls.vflip;
++
++	tisp_flip_enable(&core->core_tuning, value);
++
++	return ret;
++}
++
++static inline int apical_isp_sat_s_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	struct ispcam_device *ispcam = isp->ispcam;
++	struct vic_device *vic = ispcam->vic;
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	unsigned int value = 128;
++	int ret = 0;
++
++	if (input_fmt->format.code == MEDIA_BUS_FMT_YUYV8_1X16) {
++		return ret;
++	}
++	/* the original value */
++	value = isp->ctrls.sat & 0xff;
++	tisp_set_saturation(&core->core_tuning, value);
++
++	return ret;
++}
++
++static inline int apical_isp_sat_g_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	struct ispcam_device *ispcam = isp->ispcam;
++	struct vic_device *vic = ispcam->vic;
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	unsigned int value = 128;
++	int ret = 0;
++
++	if(input_fmt->format.code == MEDIA_BUS_FMT_YUYV8_1X16){
++		return ret;
++	}
++	/* the original value */
++	value = tisp_get_saturation(&core->core_tuning);
++	isp->ctrls.contrast = value;
++
++	return ret;
++}
++
++static inline int apical_isp_bright_s_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	struct ispcam_device *ispcam = isp->ispcam;
++	struct vic_device *vic = ispcam->vic;
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	unsigned int value = 128;
++	int ret = 0;
++
++	if (input_fmt->format.code == MEDIA_BUS_FMT_YUYV8_1X16) {
++		return ret;
++	}
++	/* the original value */
++	value = isp->ctrls.bright & 0xff;
++	tisp_set_brightness(&core->core_tuning, value);
++
++	return ret;
++}
++
++static inline int apical_isp_bright_g_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	struct ispcam_device *ispcam = isp->ispcam;
++	struct vic_device *vic = ispcam->vic;
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	unsigned int value = 128;
++	int ret = 0;
++
++	if (input_fmt->format.code == MEDIA_BUS_FMT_YUYV8_1X16) {
++		return ret;
++	}
++	/* the original value */
++	value = tisp_get_brightness(&core->core_tuning);
++	isp->ctrls.bright = value;
++
++	return ret;
++}
++
++static inline int apical_isp_contrast_s_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	struct ispcam_device *ispcam = isp->ispcam;
++	struct vic_device *vic = ispcam->vic;
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	unsigned int value = 128;
++	int ret = 0;
++
++	if (input_fmt->format.code == MEDIA_BUS_FMT_YUYV8_1X16) {
++		return ret;
++	}
++	/* the original value */
++	value = isp->ctrls.contrast & 0xff;
++	tisp_set_contrast(&core->core_tuning, value);
++
++	return ret;
++}
++
++static inline int apical_isp_contrast_g_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	struct ispcam_device *ispcam = isp->ispcam;
++	struct vic_device *vic = ispcam->vic;
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	unsigned int value = 128;
++	int ret = 0;
++
++	if (input_fmt->format.code == MEDIA_BUS_FMT_YUYV8_1X16) {
++		return ret;
++	}
++	/* the original value */
++	value = tisp_get_contrast(&core->core_tuning);
++	isp->ctrls.contrast = value;
++
++	return ret;
++}
++
++static inline int apical_isp_sharp_s_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	struct ispcam_device *ispcam = isp->ispcam;
++	struct vic_device *vic = ispcam->vic;
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	unsigned int value = 128;
++	int ret = 0;
++
++	if(input_fmt->format.code == MEDIA_BUS_FMT_YUYV8_1X16){
++		return ret;
++	}
++	/* the original value */
++	value = isp->ctrls.sharp & 0xff;
++	tisp_set_sharpness(&core->core_tuning, value);
++
++	return ret;
++}
++
++static inline int apical_isp_sharp_g_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	struct ispcam_device *ispcam = isp->ispcam;
++	struct vic_device *vic = ispcam->vic;
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	unsigned int value = 128;
++	int ret = 0;
++
++	if (input_fmt->format.code == MEDIA_BUS_FMT_YUYV8_1X16) {
++		return ret;
++	}
++	/* the original value */
++	value = tisp_get_sharpness(&core->core_tuning);
++	isp->ctrls.sharp = value;
++
++	return ret;
++}
++
++
++static int ispcore_exp_auto_s_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	tisp_ev_attr_t ae_attr;
++	int ret = 0;
++	/*
++	 * control->value.
++	 *	0: 自动�光.
++	 *	1: 手动�光.
++	 *	2. 快门优先.
++	 *	3. 光圈优先.
++	 * */
++
++	ret = tisp_g_ev_attr(&core->core_tuning, &ae_attr);
++	if (isp->ctrls.exp_auto == V4L2_EXPOSURE_AUTO) {
++		ae_attr.manual_it = 0;
++	} else if(isp->ctrls.exp_auto == V4L2_EXPOSURE_MANUAL) {
++		ae_attr.manual_it = 1;
++	}
++
++	ret = tisp_s_ae_attr(&core->core_tuning, ae_attr);
++
++	return ret;
++}
++
++/* 获�当��光方�.*/
++static int ispcore_exp_auto_g_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	tisp_ev_attr_t ae_attr;
++	int ret = 0;
++
++	ret = tisp_g_ev_attr(&core->core_tuning, &ae_attr);
++
++	isp->ctrls.exp_auto = ae_attr.manual_it == 0 ? V4L2_EXPOSURE_AUTO : V4L2_EXPOSURE_MANUAL;
++
++	return ret;
++}
++
++/* 设置�光等级. eg: [-4, 4]
++ *
++ *  相对�光时间. 从 [-4, 4] -> [inte_min, inte_max]
++ * */
++static int ispcore_exp_s_control(tisp_core_t *core)
++{
++
++	return 0;
++}
++
++static int ispcore_exp_g_control(tisp_core_t *core)
++{
++
++	return 0;
++}
++
++/* 设置�光时间. */
++static int ispcore_exp_abs_s_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	tisp_ev_attr_t ae_attr;
++	int ret = 0;
++
++	ret = tisp_g_ev_attr(&core->core_tuning, &ae_attr);
++	if (ae_attr.manual_it) {
++		ae_attr.integration_time = isp->ctrls.exp_abs;
++		ret = tisp_s_ae_attr(&core->core_tuning, ae_attr);
++	} else {
++		dev_warn(isp->dev, "set exp_abs while in exposure [auto] mode.\n");
++	}
++
++	return ret;
++}
++
++static int ispcore_exp_abs_g_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	tisp_ev_attr_t ae_attr;
++	int ret = 0;
++
++	ret = tisp_g_ev_attr(&core->core_tuning, &ae_attr);
++
++	isp->ctrls.exp_abs = ae_attr.integration_time;
++
++	return ret;
++}
++
++/*设置自动增益控制方�
++ * 0: 自动增益控制
++ * 1: 手动增益控制.
++ * */
++static inline int ispcore_auto_gain_s_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	tisp_ev_attr_t ae_attr;
++	int ret = 0;
++	ret = tisp_g_ev_attr(&core->core_tuning, &ae_attr);
++
++	if (isp->ctrls.auto_gain == 0 ) {
++		ae_attr.manual_ag = 0;
++	} else if (isp->ctrls.auto_gain == 1 ){
++		ae_attr.manual_ag = 1;
++	}
++
++	ret = tisp_s_ae_attr_ag(&core->core_tuning, ae_attr);
++
++	return ret;
++}
++
++/*获�自动增益控制方�.*/
++static inline int ispcore_auto_gain_g_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	tisp_ev_attr_t ae_attr;
++	int ret = 0;
++	ret = tisp_g_ev_attr(&core->core_tuning, &ae_attr);
++
++	isp->ctrls.auto_gain = ae_attr.manual_ag;
++
++	return ret;
++}
++
++/*手动增益控制模�下，设置当�增益.*/
++static inline int ispcore_gain_s_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	tisp_ev_attr_t ae_attr;
++	int ret = 0;
++	ret = tisp_g_ev_attr(&core->core_tuning, &ae_attr);
++
++	if (ae_attr.manual_ag) {
++		ae_attr.again = isp->ctrls.gain;
++		ret = tisp_s_ae_attr_ag(&core->core_tuning, ae_attr);
++	} else {
++		dev_warn(isp->dev, "set gain_s warning while in gain mode.\n");
++	}
++
++	return ret;
++}
++
++static inline int ispcore_gain_g_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	tisp_ev_attr_t ae_attr;
++	int ret = 0;
++	ret = tisp_g_ev_attr(&core->core_tuning, &ae_attr);
++
++	isp->ctrls.gain = ae_attr.again;
++
++	return ret;
++}
++
++static inline int ispcore_auto_wb_s_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	tisp_wb_attr_t *wb_attr = &isp->ctrls.wb_attr;
++	int ret = 0;
++
++	ret = tisp_s_wb_frz_attr(&core->core_tuning, 0);
++	switch(isp->ctrls.auto_wb) {
++	case 1:
++		wb_attr->tisp_wb_manual = 0;
++		ret = tisp_s_wb_attr(&core->core_tuning, *wb_attr);
++		break;
++	case 0:
++		wb_attr->tisp_wb_manual = 1;
++		ret = tisp_s_wb_attr(&core->core_tuning, *wb_attr);
++		ret = tisp_s_wb_frz_attr(&core->core_tuning, 1);
++		break;
++	default:
++		break;
++	}
++	return ret;
++}
++
++
++static inline int ispcore_auto_n_wb_s_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	tisp_wb_attr_t *wb_attr = &isp->ctrls.wb_attr;
++	int ret = 0;
++
++	ret = tisp_s_wb_frz_attr(&core->core_tuning, 0);
++	switch(isp->ctrls.wb) {
++	case V4L2_WHITE_BALANCE_AUTO:
++		wb_attr->tisp_wb_manual = 0;
++		ret = tisp_s_wb_attr(&core->core_tuning, *wb_attr);
++		break;
++	case V4L2_WHITE_BALANCE_MANUAL:
++		wb_attr->tisp_wb_manual = 1;
++		ret = tisp_s_wb_attr(&core->core_tuning, *wb_attr);
++		ret = tisp_s_wb_frz_attr(&core->core_tuning, 1);
++		break;
++	case V4L2_WHITE_BALANCE_FLASH:
++		wb_attr->tisp_wb_manual = 2;
++		ret = tisp_s_wb_attr(&core->core_tuning, *wb_attr);
++		break;
++	case V4L2_WHITE_BALANCE_FLUORESCENT:
++		wb_attr->tisp_wb_manual = 3;
++		ret = tisp_s_wb_attr(&core->core_tuning, *wb_attr);
++		break;
++	case V4L2_WHITE_BALANCE_CLOUDY:
++		wb_attr->tisp_wb_manual = 4;
++		ret = tisp_s_wb_attr(&core->core_tuning, *wb_attr);
++		break;
++	case V4L2_WHITE_BALANCE_HORIZON:
++		wb_attr->tisp_wb_manual = 5;
++		ret = tisp_s_wb_attr(&core->core_tuning, *wb_attr);
++		break;
++	case V4L2_WHITE_BALANCE_DAYLIGHT:
++		wb_attr->tisp_wb_manual = 6;
++		ret = tisp_s_wb_attr(&core->core_tuning, *wb_attr);
++		break;
++	case V4L2_WHITE_BALANCE_FLUORESCENT_H:
++		wb_attr->tisp_wb_manual = 7;
++		ret = tisp_s_wb_attr(&core->core_tuning, *wb_attr);
++		break;
++	case V4L2_WHITE_BALANCE_INCANDESCENT:
++		wb_attr->tisp_wb_manual = 8;
++		ret = tisp_s_wb_attr(&core->core_tuning, *wb_attr);
++		break;
++	case V4L2_WHITE_BALANCE_SHADE:
++		wb_attr->tisp_wb_manual = 9;
++		ret = tisp_s_wb_attr(&core->core_tuning, *wb_attr);
++		ret = tisp_s_wb_frz_attr(&core->core_tuning, 1);
++		break;
++	default:
++		break;
++	}
++	return ret;
++}
++
++
++static inline int ispcore_red_wb_s_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	tisp_wb_attr_t *wb_attr = &isp->ctrls.wb_attr;
++	int ret = 0;
++
++	wb_attr->tisp_wb_rg = isp->ctrls.red_wb;
++	return ret;
++}
++
++
++static inline int ispcore_blue_wb_s_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	tisp_wb_attr_t *wb_attr = &isp->ctrls.wb_attr;
++	int ret = 0;
++
++	wb_attr->tisp_wb_bg = isp->ctrls.blue_wb;
++	return ret;
++}
++
++
++static inline int ispcore_do_wb_s_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	tisp_wb_attr_t *wb_attr = &isp->ctrls.wb_attr;
++	int ret = 0;
++
++	ret = tisp_s_wb_frz_attr(&core->core_tuning, 0);
++	ret = tisp_s_wb_attr(&core->core_tuning, *wb_attr);
++	return ret;
++}
++
++
++static inline int ispcore_auto_wb_g_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	tisp_wb_attr_t wb_attr;
++	int ret = 0;
++
++	ret = tisp_g_wb_attr(&core->core_tuning, &wb_attr);
++	switch( wb_attr.tisp_wb_manual ) {
++	case 0:
++		isp->ctrls.auto_wb = V4L2_WHITE_BALANCE_AUTO;
++		break;
++	case 1:
++		isp->ctrls.auto_wb = V4L2_WHITE_BALANCE_MANUAL;
++		break;
++	default:
++		break;
++	}
++	return ret;
++}
++
++
++static inline int ispcore_auto_n_wb_g_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	tisp_wb_attr_t wb_attr;
++	int ret = 0;
++
++	ret = tisp_g_wb_attr(&core->core_tuning, &wb_attr);
++	switch( wb_attr.tisp_wb_manual ) {
++	case 0:
++	        isp->ctrls.wb = V4L2_WHITE_BALANCE_AUTO;
++		break;
++	case 1:
++		isp->ctrls.wb = V4L2_WHITE_BALANCE_MANUAL;
++		break;
++	case 2:
++		isp->ctrls.wb = V4L2_WHITE_BALANCE_FLASH;
++		break;
++	case 3:
++		isp->ctrls.wb = V4L2_WHITE_BALANCE_FLUORESCENT;
++		break;
++	case 4:
++		isp->ctrls.wb = V4L2_WHITE_BALANCE_CLOUDY;
++		break;
++	case 5:
++		isp->ctrls.wb = V4L2_WHITE_BALANCE_HORIZON;
++		break;
++	case 6:
++		isp->ctrls.wb = V4L2_WHITE_BALANCE_DAYLIGHT;
++		break;
++	case 7:
++		isp->ctrls.wb = V4L2_WHITE_BALANCE_FLUORESCENT_H;
++		break;
++	case 8:
++		isp->ctrls.wb = V4L2_WHITE_BALANCE_INCANDESCENT;
++		break;
++	case 9:
++		isp->ctrls.wb = V4L2_WHITE_BALANCE_SHADE;
++		break;
++	default:
++		break;
++	}
++	return ret;
++}
++
++static inline int ispcore_red_wb_g_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	tisp_wb_attr_t wb_attr;
++	int ret = 0;
++
++	ret = tisp_g_wb_attr(&core->core_tuning, &wb_attr);
++	if (wb_attr.tisp_wb_manual == 0) {
++		isp->ctrls.red_wb = 65536 / wb_attr.tisp_wb_rg_sta_weight;
++	} else {
++		isp->ctrls.red_wb = wb_attr.tisp_wb_rg;
++	}
++	return ret;
++}
++
++static inline int ispcore_blue_wb_g_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	tisp_wb_attr_t wb_attr;
++	int ret = 0;
++
++	ret = tisp_g_wb_attr(&core->core_tuning, &wb_attr);
++	if (wb_attr.tisp_wb_manual == 0) {
++		isp->ctrls.blue_wb = 65536 / wb_attr.tisp_wb_bg_sta_weight;
++	} else {
++		isp->ctrls.blue_wb = wb_attr.tisp_wb_bg;
++	}
++	return ret;
++}
++
++
++static inline int apical_isp_hilightdepress_s_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	struct ispcam_device *ispcam = isp->ispcam;
++	struct vic_device *vic = ispcam->vic;
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	unsigned int value = 0;
++	int ret = 0;
++
++	if(input_fmt->format.code == MEDIA_BUS_FMT_YUYV8_1X16){
++		return ret;
++	}
++	value = isp->ctrls.hill;
++	ret = tisp_s_Hilightdepress(&core->core_tuning, value);
++
++	return ret;
++}
++
++
++static inline int apical_isp_hilightdepress_g_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	struct ispcam_device *ispcam = isp->ispcam;
++	struct vic_device *vic = ispcam->vic;
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	int ret=0;
++
++	if(input_fmt->format.code == MEDIA_BUS_FMT_YUYV8_1X16){
++		return -1;
++	}
++	ret = tisp_g_Hilightdepress(&core->core_tuning, &isp->ctrls.hill);
++
++	return 0;
++}
++
++
++static inline int flicker_value_v4l2_to_tuning(int val)
++{
++	int ret = 0;
++	switch(val){
++	case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED:
++		ret = 0;
++		break;
++	case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
++		ret = 50;
++		break;
++	case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
++		ret = 60;
++		break;
++	default:
++		ret = -EINVAL;
++		break;
++	}
++
++	return ret;
++}
++
++
++static inline int apical_isp_flicker_s_control(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	int ret = 0;
++
++	ret = tisp_s_antiflick(&core->core_tuning, flicker_value_v4l2_to_tuning(isp->ctrls.flicker));
++	if(ret != 0)
++		dev_err(isp->dev, "set flicker failed!!!\n");
++
++	return ret;
++}
++
++static int apical_isp_module_s_attr(tisp_core_t *core)
++{
++	tisp_module_control_t module;
++	struct isp_device *isp = core->priv_data;
++	module.key = isp->ctrls.module;
++
++	tisp_s_module_control(&core->core_tuning, module);
++
++	return 0;
++}
++
++static int apical_isp_module_g_attr(tisp_core_t *core)
++{
++	tisp_module_control_t module;
++	struct isp_device *isp = core->priv_data;
++	int ret = 0;
++
++	tisp_g_module_control(&core->core_tuning, &module);
++	isp->ctrls.module = module.key;
++
++	return ret;
++}
++
++static inline int apical_isp_day_or_night_s_ctrl(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	int ret = 0;
++	TISP_MODE_DN_E dn = isp->ctrls.daynight;
++
++	tisp_day_or_night_s_ctrl(&core->core_tuning, dn);
++
++	return ret;
++}
++
++static inline int apical_isp_day_or_night_g_ctrl(tisp_core_t *core)
++{
++	struct isp_device *isp = core->priv_data;
++	TISP_MODE_DN_E dn ;
++
++	dn = tisp_day_or_night_g_ctrl(&core->core_tuning);
++	isp->ctrls.daynight = dn;
++
++	return 0;
++}
++
++
++static int apical_isp_ae_luma_g_ctrl(tisp_core_t *core)
++{
++	unsigned char luma;
++	struct isp_device *isp = core->priv_data;
++	struct v4l2_subdev_format *input_fmt = &isp->formats[ISP_PAD_SINK];
++	int width = input_fmt->format.width;
++	int height = input_fmt->format.height;
++
++	tisp_g_ae_luma(&core->core_tuning, &luma, width, height);
++	isp->ctrls.luma = luma;
++
++	return 0;
++}
++
++int isp_core_tuning_param_sync(tisp_core_t *core)
++{
++	int ret = 0;
++	struct isp_device *isp = core->priv_data;
++	struct v4l2_control *control;
++	control = kzalloc(sizeof(struct v4l2_control), GFP_KERNEL);
++
++	if (isp->ctrls.hflip_pending) {
++		ret = apical_isp_hflip_s_control(core);
++		isp->ctrls.hflip_pending = 0;
++	}
++	if (isp->ctrls.vflip_pending) {
++		ret = apical_isp_vflip_s_control(core);
++		isp->ctrls.vflip_pending = 0;
++	}
++	if (isp->ctrls.sat_pending) {
++		ret = apical_isp_sat_s_control(core);
++		isp->ctrls.sat_pending = 0;
++	}
++	if (isp->ctrls.bright_pending) {
++		ret = apical_isp_bright_s_control(core);
++		isp->ctrls.bright_pending = 0;
++	}
++	if (isp->ctrls.contrast_pending) {
++		ret = apical_isp_contrast_s_control(core);
++		isp->ctrls.contrast_pending = 0;
++	}
++	if (isp->ctrls.sharp_pending) {
++		ret = apical_isp_sharp_s_control(core);
++		isp->ctrls.sharp_pending = 0;
++	}
++	if (isp->ctrls.exp_auto_pending) {
++		ret = ispcore_exp_auto_s_control(core);
++		isp->ctrls.exp_auto_pending = 0;
++	}
++	if (isp->ctrls.exp_abs_pending) {
++		ret = ispcore_exp_abs_s_control(core);
++		isp->ctrls.exp_abs_pending = 0;
++	}
++	if (isp->ctrls.auto_gain_pending) {
++		ret = ispcore_auto_gain_s_control(core);
++		isp->ctrls.auto_gain_pending = 0;
++	}
++	if (isp->ctrls.gain_pending) {
++		ret = ispcore_gain_s_control(core);
++		isp->ctrls.gain_pending = 0;
++	}
++	if (isp->ctrls.wb_pending) {
++		ret = ispcore_auto_n_wb_s_control(core);
++		isp->ctrls.wb_pending = 0;
++	}
++	if (isp->ctrls.auto_wb_pending) {
++		ret = ispcore_auto_wb_s_control(core);
++		isp->ctrls.auto_wb_pending = 0;
++	}
++	if (isp->ctrls.red_wb_pending) {
++		ret = ispcore_red_wb_s_control(core);
++		isp->ctrls.red_wb_pending = 0;
++	}
++	if (isp->ctrls.blue_wb_pending) {
++		ret = ispcore_blue_wb_s_control(core);
++		isp->ctrls.blue_wb_pending = 0;
++	}
++	if (isp->ctrls.do_wb_pending) {
++		ret = ispcore_do_wb_s_control(core);
++		isp->ctrls.do_wb_pending = 0;
++	}
++	if (isp->ctrls.hill_pending) {
++		ret = apical_isp_hilightdepress_s_control(core);
++		isp->ctrls.hill_pending = 0;
++	}
++	if (isp->ctrls.flicker_pending) {
++		ret = apical_isp_flicker_s_control(core);
++		isp->ctrls.flicker_pending = 0;
++	}
++	if (isp->ctrls.module_pending) {
++		ret = apical_isp_module_s_attr(core);
++		isp->ctrls.module_pending = 0;
++	}
++	if (isp->ctrls.daynight_pending) {
++		ret = apical_isp_day_or_night_s_ctrl(core);
++		isp->ctrls.daynight_pending = 0;
++	}
++	return ret;
++}
++
++
++static int isp_video_g_ctrl_inited(struct isp_device *isp, struct v4l2_control *a)
++{
++	tisp_core_t *core = &isp->core;
++	int ret = 0;
++
++	switch (a->id) {
++	case V4L2_CID_HFLIP:
++		a->value = isp->ctrls.hflip;
++		break;
++	case V4L2_CID_VFLIP:
++		a->value = isp->ctrls.vflip;
++		break;
++	case V4L2_CID_SATURATION:
++		ret = apical_isp_sat_g_control(core);
++		a->value = isp->ctrls.sat;
++		break;
++	case V4L2_CID_BRIGHTNESS:
++		ret = apical_isp_bright_g_control(core);
++		a->value = isp->ctrls.bright;
++		break;
++	case V4L2_CID_CONTRAST:
++		ret = apical_isp_contrast_g_control(core);
++		a->value = isp->ctrls.contrast;
++		break;
++	case V4L2_CID_SHARPNESS:
++		ret = apical_isp_sharp_g_control(core);
++		a->value = isp->ctrls.sharp;
++		break;
++	case V4L2_CID_EXPOSURE_AUTO:
++		ret = ispcore_exp_auto_g_control(core);
++		a->value = isp->ctrls.exp_auto;
++		break;
++	case V4L2_CID_EXPOSURE_ABSOLUTE:
++		ret = ispcore_exp_abs_g_control(core);
++		a->value = isp->ctrls.exp_abs;
++		break;
++	case V4L2_CID_EXPOSURE:
++		ret = ispcore_exp_g_control(core);
++		break;
++	case V4L2_CID_AUTOGAIN:
++		ret = ispcore_auto_gain_g_control(core);
++		a->value = isp->ctrls.auto_gain;
++		break;
++	case V4L2_CID_GAIN:
++		ret = ispcore_gain_g_control(core);
++		a->value = isp->ctrls.gain;
++		break;
++	case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
++		ret = ispcore_auto_n_wb_g_control(core);
++		a->value = isp->ctrls.wb;
++		break;
++	case V4L2_CID_AUTO_WHITE_BALANCE:
++		ret = ispcore_auto_wb_g_control(core);
++		a->value = isp->ctrls.auto_wb;
++		break;
++	case V4L2_CID_RED_BALANCE:
++		ret = ispcore_red_wb_g_control(core);
++		a->value = isp->ctrls.red_wb;
++		break;
++	case V4L2_CID_BLUE_BALANCE:
++		ret = ispcore_blue_wb_g_control(core);
++		a->value = isp->ctrls.blue_wb;
++		break;
++	case IMAGE_TUNING_CID_HILIGHTDEPRESS:
++		ret = apical_isp_hilightdepress_g_control(core);
++		a->value = isp->ctrls.hill;
++		break;
++	case V4L2_CID_POWER_LINE_FREQUENCY:
++		a->value = isp->ctrls.flicker;
++		break;
++	case IMAGE_TUNING_CID_MODULE_CONTROL:
++		ret = apical_isp_module_g_attr(core);
++		a->value = isp->ctrls.module;
++		break;
++	case IMAGE_TUNING_CID_DAY_OR_NIGHT:
++		ret = apical_isp_day_or_night_g_ctrl(core);
++		a->value = isp->ctrls.daynight;
++		break;
++	case IMAGE_TUNING_CID_AE_LUMA:
++		ret = apical_isp_ae_luma_g_ctrl(core);
++		a->value = isp->ctrls.luma;
++		break;
++	default:
++		ret = -EPERM;
++		break;
++	}
++	return ret;
++}
++
++
++static int isp_video_g_ctrl_noinited(struct isp_device *isp, struct v4l2_control *a)
++{
++	int ret = 0;
++
++	switch (a->id) {
++	case V4L2_CID_HFLIP:
++		a->value = isp->ctrls.hflip;
++		break;
++	case V4L2_CID_VFLIP:
++		a->value = isp->ctrls.vflip;
++		break;
++	case V4L2_CID_SATURATION:
++		a->value = isp->ctrls.sat;
++		break;
++	case V4L2_CID_BRIGHTNESS:
++		a->value = isp->ctrls.bright;
++		break;
++	case V4L2_CID_CONTRAST:
++		a->value = isp->ctrls.contrast;
++		break;
++	case V4L2_CID_SHARPNESS:
++		a->value = isp->ctrls.sharp;
++		break;
++	case V4L2_CID_EXPOSURE_AUTO:
++		a->value = isp->ctrls.exp_auto;
++		break;
++	case V4L2_CID_EXPOSURE_ABSOLUTE:
++		a->value = isp->ctrls.exp_abs;
++		break;
++	case V4L2_CID_AUTOGAIN:
++		a->value = isp->ctrls.auto_gain;
++		break;
++	case V4L2_CID_GAIN:
++		a->value = isp->ctrls.gain;
++		break;
++	case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
++		a->value = isp->ctrls.wb;
++		break;
++	case V4L2_CID_AUTO_WHITE_BALANCE:
++		a->value = isp->ctrls.auto_wb;
++		break;
++	case V4L2_CID_RED_BALANCE:
++		a->value = isp->ctrls.red_wb;
++		break;
++	case V4L2_CID_BLUE_BALANCE:
++		a->value = isp->ctrls.blue_wb;
++		break;
++	case IMAGE_TUNING_CID_HILIGHTDEPRESS:
++		a->value = isp->ctrls.hill;
++		break;
++	case V4L2_CID_POWER_LINE_FREQUENCY:
++		a->value = isp->ctrls.flicker;
++		break;
++	case IMAGE_TUNING_CID_MODULE_CONTROL:
++		a->value = isp->ctrls.module;
++		break;
++	case IMAGE_TUNING_CID_DAY_OR_NIGHT:
++		a->value = isp->ctrls.daynight;
++		break;
++	case IMAGE_TUNING_CID_AE_LUMA:
++		a->value = isp->ctrls.luma;
++		break;
++	default:
++		ret = -EPERM;
++		break;
++	}
++	return ret;
++}
++
++
++int isp_video_g_ctrl(struct file *file, void *fh, struct v4l2_control *a)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct isp_device 	*isp	= ispcam->isp;
++	int ret = 0;
++
++	if (isp->core_inited) {
++		ret = isp_video_g_ctrl_inited(isp, a);
++	} else {
++		ret = isp_video_g_ctrl_noinited(isp, a);
++	}
++
++	return ret;
++}
++
++static int isp_video_s_ctrl_inited(struct isp_device *isp, struct v4l2_control *a)
++{
++	tisp_core_t *core = &isp->core;
++	int ret = 0;
++
++	switch (a->id) {
++	case V4L2_CID_HFLIP:
++		isp->ctrls.hflip = a->value;
++		ret = apical_isp_hflip_s_control(core);
++		break;
++	case V4L2_CID_VFLIP:
++		isp->ctrls.vflip = a->value;
++		ret = apical_isp_vflip_s_control(core);
++		break;
++	case V4L2_CID_SATURATION:
++		isp->ctrls.sat = a->value;
++		ret = apical_isp_sat_s_control(core);
++		break;
++	case V4L2_CID_BRIGHTNESS:
++		isp->ctrls.bright = a->value;
++		ret = apical_isp_bright_s_control(core);
++		break;
++	case V4L2_CID_CONTRAST:
++		isp->ctrls.contrast = a->value;
++		ret = apical_isp_contrast_s_control(core);
++		break;
++	case V4L2_CID_SHARPNESS:
++		isp->ctrls.sharp = a->value;
++		ret = apical_isp_sharp_s_control(core);
++		break;
++	case V4L2_CID_EXPOSURE_AUTO:
++		isp->ctrls.exp_auto = a->value;
++		ret = ispcore_exp_auto_s_control(core);
++		break;
++	case V4L2_CID_EXPOSURE_ABSOLUTE:
++		isp->ctrls.exp_abs = a->value;
++		ret = ispcore_exp_abs_s_control(core);
++		break;
++	case V4L2_CID_EXPOSURE:
++		ret = ispcore_exp_s_control(core);
++		break;
++	case V4L2_CID_AUTOGAIN:
++		isp->ctrls.auto_gain = a->value;
++		ret = ispcore_auto_gain_s_control(core);
++		break;
++	case V4L2_CID_GAIN:
++		isp->ctrls.gain = a->value;
++		ret = ispcore_gain_s_control(core);
++		break;
++	case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
++		isp->ctrls.wb    = a->value;
++		ret = ispcore_auto_n_wb_s_control(core);
++		break;
++	case V4L2_CID_AUTO_WHITE_BALANCE:
++		isp->ctrls.auto_wb    = a->value;
++		ret = ispcore_auto_wb_s_control(core);
++		break;
++	case V4L2_CID_RED_BALANCE:
++		isp->ctrls.red_wb    = a->value;
++		ret = ispcore_red_wb_s_control(core);
++		break;
++	case V4L2_CID_BLUE_BALANCE:
++		isp->ctrls.blue_wb    = a->value;
++		ret = ispcore_blue_wb_s_control(core);
++		break;
++	case V4L2_CID_DO_WHITE_BALANCE:
++		ret = ispcore_do_wb_s_control(core);
++		break;
++	case IMAGE_TUNING_CID_HILIGHTDEPRESS:
++		isp->ctrls.hill = a->value;
++		ret = apical_isp_hilightdepress_s_control(core);
++		break;
++	case V4L2_CID_POWER_LINE_FREQUENCY:
++		isp->ctrls.flicker = a->value;
++		ret = apical_isp_flicker_s_control(core);
++		break;
++	case IMAGE_TUNING_CID_MODULE_CONTROL:
++		isp->ctrls.module = a->value;
++		ret = apical_isp_module_s_attr(core);
++		break;
++	case IMAGE_TUNING_CID_DAY_OR_NIGHT:
++		isp->ctrls.daynight = a->value;
++		ret = apical_isp_day_or_night_s_ctrl(core);
++		break;
++	default:
++		ret = -EPERM;
++		break;
++	}
++	return ret;
++}
++
++static int isp_video_s_ctrl_noinited(struct isp_device *isp, struct v4l2_control *a)
++{
++	int ret = 0;
++
++	switch (a->id) {
++	case V4L2_CID_HFLIP:
++		isp->ctrls.hflip = a->value;
++		isp->ctrls.hflip_pending = 1;
++		break;
++	case V4L2_CID_VFLIP:
++		isp->ctrls.vflip = a->value;
++		isp->ctrls.vflip_pending = 1;
++		break;
++	case V4L2_CID_SATURATION:
++		isp->ctrls.sat = a->value;
++		isp->ctrls.sat_pending = 1;
++		break;
++	case V4L2_CID_BRIGHTNESS:
++		isp->ctrls.bright = a->value;
++		isp->ctrls.bright_pending = 1;
++		break;
++	case V4L2_CID_CONTRAST:
++		isp->ctrls.contrast = a->value;
++		isp->ctrls.contrast_pending = 1;
++		break;
++	case V4L2_CID_SHARPNESS:
++		isp->ctrls.sharp = a->value;
++		isp->ctrls.sharp_pending = 1;
++		break;
++	case V4L2_CID_EXPOSURE_AUTO:
++		isp->ctrls.exp_auto = a->value;
++		isp->ctrls.exp_auto_pending = 1;
++		break;
++	case V4L2_CID_EXPOSURE_ABSOLUTE:
++		isp->ctrls.exp_abs = a->value;
++		isp->ctrls.exp_abs_pending = 1;
++		break;
++	case V4L2_CID_AUTOGAIN:
++		isp->ctrls.auto_gain = a->value;
++		isp->ctrls.auto_gain_pending = 1;
++		break;
++	case V4L2_CID_GAIN:
++		isp->ctrls.gain = a->value;
++		isp->ctrls.gain_pending = 1;
++		break;
++	case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
++		isp->ctrls.wb    = a->value;
++		isp->ctrls.wb_pending = 1;
++		break;
++	case V4L2_CID_AUTO_WHITE_BALANCE:
++		isp->ctrls.auto_wb    = a->value;
++		isp->ctrls.auto_wb_pending = 1;
++		break;
++	case V4L2_CID_RED_BALANCE:
++		isp->ctrls.red_wb    = a->value;
++		isp->ctrls.red_wb_pending = 1;
++		break;
++	case V4L2_CID_BLUE_BALANCE:
++		isp->ctrls.blue_wb    = a->value;
++		isp->ctrls.blue_wb_pending = 1;
++		break;
++	case V4L2_CID_DO_WHITE_BALANCE:
++		isp->ctrls.do_wb_pending = 1;
++		break;
++	case IMAGE_TUNING_CID_HILIGHTDEPRESS:
++		isp->ctrls.hill = a->value;
++		isp->ctrls.hill_pending = 1;
++		break;
++	case V4L2_CID_POWER_LINE_FREQUENCY:
++		isp->ctrls.flicker = a->value;
++		isp->ctrls.flicker_pending = 1;
++		break;
++	case IMAGE_TUNING_CID_MODULE_CONTROL:
++		isp->ctrls.module = a->value;
++		isp->ctrls.module_pending = 1;
++		break;
++	case IMAGE_TUNING_CID_DAY_OR_NIGHT:
++		isp->ctrls.daynight = a->value;
++		isp->ctrls.daynight_pending = 1;
++		break;
++	default:
++		ret = -EPERM;
++		break;
++	}
++	return ret;
++}
++
++int isp_video_s_ctrl(struct file *file, void *fh, struct v4l2_control *a)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct isp_device 	*isp	= ispcam->isp;
++	int ret = 0;
++
++	if (isp->core_inited) {
++		ret = isp_video_s_ctrl_inited(isp, a);
++	} else {
++		ret = isp_video_s_ctrl_noinited(isp, a);
++	}
++	return ret;
++}
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-core/Makefile b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/Makefile
+new file mode 100644
+index 000000000..d0cd033a6
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/Makefile
+@@ -0,0 +1,3 @@
++obj-y	+= src/
++obj-y	+= tiziano_priv.o
++obj-y	+= tiziano_netlink.o
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/system_sensor_drv.h b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/system_sensor_drv.h
+new file mode 100644
+index 000000000..e17e497b2
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/system_sensor_drv.h
+@@ -0,0 +1,85 @@
++#ifndef __SENSOR_DRV_H__
++#define __SENSOR_DRV_H__
++
++#include <linux/types.h>
++
++#define LOG2_GAIN_SHIFT 16
++
++typedef struct _sensor_context_t
++{
++	uint16_t again;
++	uint16_t dgain;
++	uint8_t n_context;
++	uint8_t wdr_mode;
++	uint16_t again_x2;
++	uint16_t dgain_coarse;
++	uint16_t dgain_fine;
++	uint8_t column_buffer_gain_index;
++} sensor_context_t;
++
++typedef struct _image_resolution_t
++{
++	uint16_t width;
++	uint16_t height;
++} image_resolution_t;
++
++typedef struct _sensor_param_t
++{
++	uint8_t mode;
++	image_resolution_t total;
++	image_resolution_t active;
++	sensor_context_t sensor_ctx;
++	int32_t again_log2_max;
++	int32_t dgain_log2_max;
++	uint32_t integration_time_min;
++	uint32_t integration_time_max;
++	uint32_t integration_time_long_max;
++	uint32_t integration_time_limit;
++	uint16_t day_light_integration_time_max;
++	uint8_t integration_time_apply_delay;
++	uint8_t analog_gain_apply_delay;
++	uint8_t digital_gain_apply_delay;
++	int32_t xoffset;
++	int32_t yoffset;
++	int32_t anti_flicker_pos;
++	uint32_t lines_per_second;
++} sensor_param_t;
++
++typedef struct _sensor_control_t
++{
++	sensor_param_t param;
++	void *priv_data;	/*handle to ispcore*/
++
++} sensor_control_t;
++
++struct sensor_control_ops {
++
++	void (*hw_reset_disable)(sensor_control_t *ctrl);
++	void (*hw_reset_enable)(sensor_control_t *ctrl);
++	int32_t (*alloc_analog_gain)(sensor_control_t *ctrl, int32_t gain, sensor_context_t *p_ctx);
++	int32_t (*alloc_digital_gain)(sensor_control_t *ctrl, int32_t gain, sensor_context_t *p_ctx);
++	void (*alloc_integration_time)(sensor_control_t *ctrl, uint16_t *int_time, sensor_context_t *p_ctx);
++	void (*set_integration_time)(sensor_control_t *ctrl, uint16_t int_time, sensor_param_t *param);
++	void (*start_changes)(sensor_control_t *ctrl, sensor_context_t *p_ctx);
++	void (*end_changes)(sensor_control_t *ctrl, sensor_context_t *p_ctx);
++	void (*set_analog_gain)(sensor_control_t *ctrl, uint32_t again_reg_val, sensor_context_t *p_ctx);
++	int (*get_analog_gain)(sensor_control_t *ctrl, uint32_t *again_reg_val, sensor_context_t *p_ctx);
++	void (*set_digital_gain)(sensor_control_t *ctrl, uint32_t dgain_reg_val, sensor_context_t *p_ctx);
++	int (*get_digital_gain)(sensor_control_t *ctrl, uint32_t *dgain_reg_val, sensor_context_t *p_ctx);
++	uint16_t (*get_normal_fps)(sensor_control_t *ctrl, sensor_param_t *param);
++	uint16_t (*read_black_pedestal)(sensor_control_t *ctrl, int i, uint32_t gain);
++	void (*set_mode)(sensor_control_t *ctrl, uint8_t mode, sensor_param_t *param);
++	void (*set_wdr_mode)(sensor_control_t *ctrl, uint8_t wdr, sensor_param_t *param);
++	uint32_t (*fps_control)(sensor_control_t *ctrl, uint8_t fps, sensor_param_t *param);
++	uint16_t (*get_id)(sensor_control_t *ctrl);
++	void (*disable_isp)(sensor_control_t *ctrl);
++	uint32_t (*get_lines_per_second)(sensor_control_t *ctrl, sensor_param_t *param);
++
++};
++
++typedef sensor_control_t *sensor_control_ptr_t;
++
++void sensor_init(sensor_control_ptr_t, void *ispcore);
++int sensor_early_init(void *ispcore);
++
++#endif /* __SENSOR_DRV_H__ */
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_core.h b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_core.h
+new file mode 100644
+index 000000000..b89fa186a
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_core.h
+@@ -0,0 +1,1223 @@
++#ifndef __TIZIANO_ISP_CORE_API_H__
++#define __TIZIANO_ISP_CORE_API_H__
++
++#include "system_sensor_drv.h"
++#include "tiziano_core_tuning.h"
++#include "tiziano_isp.h"
++#include "tiziano_sys.h"
++#include "tiziano_priv.h"
++
++/*
++   -----------core---------
++   | awb, gamma,
++
++*/
++
++/* --------- defog ---------*/
++
++typedef struct Tiziano_Isp_Defog_Ct_Detect_Para
++{
++  uint32_t *DefogBlockRStat        ;
++  uint32_t *DefogBlockGStat        ;
++  uint32_t *DefogBlockBStat        ;
++  uint32_t *DefogBlockYStat        ;
++  uint32_t *DefogBlockDetailStat   ;
++  uint32_t *DefogBlockVarianceStat ;
++  uint32_t *DefogDefogBlockTX      ;
++  uint32_t *DefogDefogBlockTY      ;
++  uint32_t *DefogDetailX           ;
++  uint32_t *DefogDetailY           ;
++  uint32_t *DefogColorVarX         ;
++  uint32_t *DefogColorVarY         ;
++  uint32_t *DefogFpgaPara          ;
++  uint32_t *DefogBlockTransmitT    ;
++  uint32_t *DefogBlockAirLightR    ;
++  uint32_t *DefogBlockAirLightG    ;
++  uint32_t *DefogBlockAirLightB    ;
++}Isp_Defog_Ct_Detect_Para;
++
++typedef struct tisp_defog {
++	uint32_t ev_now;
++	uint32_t ev_changed;
++
++	uint32_t defog_ev_list[9];
++	uint32_t defog_trsy0_list[9];
++	uint32_t defog_trsy1_list[9];
++	uint32_t defog_trsy2_list[9];
++	uint32_t defog_trsy3_list[9];
++	uint32_t defog_trsy4_list[9];
++	uint32_t defog_rgbra_list[9];
++	uint32_t defog_meam_block_r[200];
++	uint32_t defog_meam_block_g[200];
++	uint32_t defog_meam_block_b[200];
++	uint32_t defog_meam_block_y[200];
++	uint32_t defog_variance_block[200];
++	uint32_t defog_detial_block[200];
++	uint32_t defog_defog_block_t_x[5];
++	uint32_t defog_defog_block_t_y[5];
++	uint32_t defog_detail_x[5];
++	uint32_t defog_detail_y[5];
++	uint32_t defog_color_var_x[5];
++	uint32_t defog_color_var_y[5];
++	uint32_t defog_fpga_para[8];
++	uint32_t param_defog_weightlut20[32];
++	uint32_t param_defog_weightlut02[32];
++	uint32_t param_defog_weightlut12[32];
++	uint32_t param_defog_weightlut22[32];
++	uint32_t param_defog_weightlut21[32];
++	uint32_t param_defog_ct_par_array[4];
++	uint32_t param_defog_dark_ct_array[14];
++	uint32_t param_defog_over_expo_w_array[11];
++	uint32_t param_defog_dark_spe_w_array[11];
++	uint32_t param_defog_col_ct_array[14];
++	uint32_t param_defog_cent3_w_dis_array[24];
++	uint32_t param_defog_cent5_w_dis_array[31];
++	uint32_t param_defog_blk_trans_array[10];
++	uint32_t param_defog_detail_ct_array[10];
++	uint32_t param_defog_col_var_array[10];
++	uint32_t param_defog_soft_ct_par_array[6];
++
++	uint32_t defog_block_transmit_t[200];
++	uint32_t defog_block_air_light_r[200];
++	uint32_t defog_block_air_light_g[200];
++	uint32_t defog_block_air_light_b[200];
++
++	Isp_Defog_Ct_Detect_Para TizianoDefogStructMe;
++
++	void *core;
++} tisp_defog_t;
++
++
++/* -------- adr -------- */
++typedef struct Tiziano_Isp_Adr_Ct_Detect_Para
++{
++	int *CtcKneepointX;
++	int *CtcKneepointMux;
++	int *MinKneepointX;
++	int *MinKneepointY;
++	int *MapKneepointX;
++	int *MapKneepointY;
++	int *ContrastWDistance;
++	int *AdrHist;
++	int *AdrBlockY;
++	int *AdrBlockHist;
++	int *TmBaseLut;
++	int *AdrGamX;
++	int *AdrGamY;
++	int *AdrMapMode;
++	int *AdrLightEnd;
++	int *AdrBlockLight;
++}Isp_Adr_Ct_Detect_Para;
++
++typedef struct tisp_adr {
++
++	unsigned int ev_changed;
++	unsigned int ev_now;
++	unsigned int width_def;
++	unsigned int height_def;
++	unsigned int adr_ratio;
++	uint32_t adr_ev_list[9];
++	uint32_t adr_ligb_list[9];
++	uint32_t adr_mapb1_list[9];
++	uint32_t adr_mapb2_list[9];
++	uint32_t adr_mapb3_list[9];
++	uint32_t adr_mapb4_list[9];
++	uint32_t adr_blp2_list[9];
++
++	Isp_Adr_Ct_Detect_Para TizianoAdrFpgaStructMe;
++
++	uint32_t param_adr_ct_par_array[8];
++	uint32_t param_adr_weight_20_lut_array[32];
++	uint32_t param_adr_weight_02_lut_array[32];
++	uint32_t param_adr_weight_12_lut_array[32];
++	uint32_t param_adr_weight_22_lut_array[32];
++	uint32_t param_adr_weight_21_lut_array[32];
++	uint32_t param_adr_ctc_kneepoint_array[8];
++	uint32_t param_adr_min_kneepoint_array[23];
++	uint32_t param_adr_map_kneepoint_array[23];
++	uint32_t param_adr_coc_kneepoint_array[21];
++	uint32_t param_adr_centre_w_dis_array[31];
++	uint32_t param_adr_contrast_w_dis_array[32];
++	uint32_t param_adr_stat_block_hist_diff_array[4];
++
++	uint32_t adr_block_y[20];
++	uint32_t adr_block_hist[100];
++	uint32_t adr_hist[512];
++
++	uint32_t ctc_kneepoint_x[4];
++	uint32_t ctc_kneepoint_mux[4];
++	uint32_t min_kneepoint_x[11];
++	uint32_t min_kneepoint_y[11];
++	/* {0,2,4,6,8,30,60,70,80,100,120}; */
++	uint32_t min_kneepoint_pow[12];
++	uint32_t map_kneepoint_x[11];
++	uint32_t map_kneepoint_y[220];
++	uint32_t map_kneepoint_pow[12];
++	uint32_t coc_kneepoint_x[11];
++	uint32_t coc_kneepoint_pow[10];
++	uint32_t centre_w_distance[31];
++	uint32_t contrast_w_distance[32];
++
++	uint32_t adr_stat_block_hist_diff[4];
++	uint32_t adr_tm_base_lut[9];
++	uint32_t adr_gam_x[129];
++	uint32_t adr_gam_y[129];
++	uint32_t adr_light_end[29];
++	uint32_t adr_block_light[15];
++	uint32_t adr_map_mode[11];
++	uint32_t histSub_4096[9];
++	uint32_t histSub_4096_out[9];
++	uint32_t histSub_4096_diff[8];
++
++
++
++
++
++
++	void *core;
++} tisp_adr_t;
++
++/*ae struct*/
++typedef struct {
++	uint32_t tisp_ae_manual;
++	uint32_t tisp_ae_sensor_again;
++	uint32_t tisp_ae_sensor_dgain;
++	uint32_t tisp_ae_sensor_integration_time;
++	uint32_t tisp_ae_isp_dgian;
++	uint32_t tisp_ae_max_sensor_again;
++	uint32_t tisp_ae_max_sensor_dgain;
++	uint32_t tisp_ae_max_sensor_integration_time;
++	uint32_t tisp_ae_max_isp_dgain;
++	uint32_t tisp_ae_ev;
++	uint32_t tisp_ae_tgain_db;
++	uint32_t tisp_ae_again_db;
++	uint32_t tisp_ae_ir;
++	uint32_t tisp_ae_it_manual;
++	uint32_t tisp_ae_ag_manual;
++	uint32_t tisp_ae_dg_manual;
++} tisp_ae_ctrls_t;
++
++typedef struct {
++	uint32_t tisp_ae_sensor_agian;
++	uint32_t tisp_ae_sensor_dgian;
++	uint32_t tisp_ae_sensor_integration_time;
++	uint32_t tisp_ae_isp_dgian;
++} tisp_ae_ctrls_internal_t;
++
++typedef struct Tiziano_Isp_Ae_Wmean_Param {
++	uint32_t *a_ae_array_d;
++	uint32_t *a_ae_array_m;
++	uint32_t *a_ae_array_s;
++	uint32_t *a_ae_array_ir;
++	uint32_t *a_ae_array_dc;
++	uint32_t *a_ae_array_sc;
++	uint32_t *a_ae_parameter;
++	uint32_t *a_ae_zone_weight;
++	uint32_t *a_exp_parameter;
++	uint32_t *a_ae_stat;
++	uint32_t *a_scene_roui_weight;
++	uint32_t *a_scene_roi_weight;
++	uint32_t *a_log2_lut;
++	uint32_t *a_weight_lut;
++	uint32_t *a_AePointPos;
++} Isp_Ae_Wmean_Param;
++
++typedef struct Tiziano_Isp_Ae_Tune_Param {
++	uint32_t *a_exp_parameter;
++	uint32_t *a_ev_list;
++	uint32_t *a_lum_list;
++	uint32_t *a_at_list;
++	uint32_t *a_ae_result;
++	uint32_t *a_ae_reg;
++	uint32_t *a_ae_stat;
++	uint32_t *a_ae_wm_q;
++	uint32_t *a_flicker_t;
++	uint32_t *a_deflicker_para;
++	uint32_t *a_ae_ev_step;
++	uint32_t *a_ae_scene_mode_th;
++	uint32_t *a_ae_stable_tol;
++	uint32_t *a_AePointPos;
++	uint32_t *a_ae_hist_ir_array;
++	uint32_t *a_ae_nodes_num;
++	uint32_t *a_ae_compensation;
++} Isp_Ae_Tune_Param;
++
++typedef struct tisp_ae {
++	int ftune;
++	uint32_t min_it;
++	uint32_t min_ag;
++	uint32_t min_dg;
++	uint32_t y_zone[15][15];
++	uint32_t y_zone_last[15][15];
++	spinlock_t slock;
++	spinlock_t slock_hist;
++	spinlock_t aelock;
++	tisp_ae_sta_t tisp_ae_hist;
++	tisp_ae_sta_t tisp_ae_hist_last;
++	int ae_first;
++	int expt_first_frame;
++
++	Isp_Ae_Wmean_Param IspAeWmeanParam;
++	Isp_Ae_Tune_Param IspAeTuneParam;
++	tisp_ae_ctrls_t tisp_ae_ctrls;
++	tisp_ae_ctrls_internal_t ae_ctrls;
++
++	uint32_t ae_array_d[225];
++	uint32_t ae_array_m[225];
++	uint32_t ae_array_s[225];
++	uint32_t ae_array_ir[225];
++	uint32_t ae_array_dc[225];
++	uint32_t ae_array_sc[225];
++
++	uint32_t ae_hist_array[256];
++	uint32_t ae_hist_ir_array[256];
++	uint32_t _ae_reg[4]; //--->awb
++	uint32_t _ae_ev;
++	uint32_t ae_dn_refresh_flag;
++	uint32_t ae_compensation;
++	uint32_t ae_ev_init_strict;
++	uint32_t ae_ev_init_en;
++
++	/*parameter*/
++	uint32_t _ae_parameter[38];
++	uint32_t ae_switch_night_mode[4];
++	uint32_t _AePointPos[2];
++	uint32_t _exp_parameter[11];
++	uint32_t ae_ev_step[5];
++	uint32_t ae_stable_tol[4];
++	uint32_t _ev_list[10];
++	uint32_t _lum_list[6];
++	uint32_t _at_list[10];
++	uint32_t _deflicker_para[3];
++	uint32_t _flicker_t[6];
++	uint32_t _deflick_lut[120];
++	uint32_t _nodes_num;
++	uint32_t _scene_para[11];
++	uint32_t ae_scene_mode_th[4];
++	uint32_t _log2_lut[20];
++	uint32_t _weight_lut[20];
++	uint32_t _ae_zone_weight[225];
++	uint32_t _scene_roui_weight[225];
++	uint32_t _scene_roi_weight[225];
++	uint32_t ev_cache[10];
++	uint32_t ad_cache[10];
++	uint32_t ag_cache[9];
++	uint32_t dg_cache[9];
++
++	/*find ones*/
++	uint32_t _ae_result[4];
++	uint32_t _ae_stat[5];
++	uint32_t _ae_wm_q[15];
++
++	int trig;
++	int force_trig;
++	int trig_deflick;
++	int trig_cal;
++
++	uint32_t again_old;
++	uint32_t again_new;
++	uint32_t total_gain_old;
++	uint32_t total_gain_new;
++	uint32_t ag_old;
++	uint32_t dg_old;
++	uint32_t ag_new;
++	uint32_t dg_new;
++	uint32_t EffectFrame;
++	int32_t EffectCount;
++
++	void *core;
++} tisp_ae_t;
++
++/*awb struct*/
++typedef struct Tiziano_Isp_Awb_Ct_Detect_Param {
++	unsigned int *auint16LightSrc;
++	unsigned int uint16LightSrcNum;
++	unsigned int *auint32CtTh;
++	unsigned int *auint32CtThPara;
++	unsigned int *auint16RgBgWeight;
++	unsigned int uint32HorZone;
++	unsigned int uint32VerZone;
++	unsigned int *auint16RgPos;
++	unsigned int *auint16BgPos;
++	unsigned int *auint16ColorTempMesh;
++	unsigned int *auint16AwbWght;
++	uint32_t *auint64AwbDisTw;
++	unsigned int *uint32AwbCt;
++	unsigned int *auint32LsWLut;
++	unsigned int *auint32AwbPointPos;
++} ISP_AWB_CT_DETECT_PARAM;
++
++typedef struct Tiziano_Isp_Awb_Fpga_Param
++{
++	unsigned int *a_r_sum;
++	unsigned int *a_g_sum;
++	unsigned int *a_b_sum;
++	unsigned int *a_pix_cnt;
++	unsigned int *a_awb_cof;
++	unsigned int *a_awb_mf_para;
++	unsigned int *a_awb_parameter;
++	unsigned int  pixel_cnt_th;
++	uint32_t *a_awb_static;
++	unsigned int *a_AwbPointPos;
++} ISP_AWB_FPGA_PARAM;
++
++typedef struct tisp_awb {
++	tisp_wb_attr_t tisp_wb_attr;
++	int awb_moa;
++	int awb_frz;
++	int awb_first;
++	uint32_t awb_dn_refresh_flag;
++	ISP_AWB_FPGA_PARAM IspAwbFpgaParam;
++	ISP_AWB_CT_DETECT_PARAM IspAwbCtDetectParam;
++	unsigned int awb_array_r[225];
++	unsigned int awb_array_g[225];
++	unsigned int awb_array_b[225];
++	unsigned int awb_array_p[225];
++
++	unsigned int awb_rg_global;
++	unsigned int awb_bg_global;
++	unsigned int awb_pix_cnt[2];
++
++	uint32_t zone_rgbg_last[450];
++	uint32_t zone_rgbg[450];
++	unsigned int zone_pix_cnt[225];
++	unsigned int awb_gain_original[2];
++	unsigned int first_frame;
++	int offet_thres;
++
++	/*parameter*/
++	unsigned int _awb_parameter[45];
++	unsigned int _pixel_cnt_th;
++	unsigned int _awb_lowlight_rg_th[2];
++	unsigned int _AwbPointPos[2];
++	unsigned int _awb_cof[2];
++	unsigned int _awb_mf_para[6];
++	unsigned int _awb_mode[3];
++	// ce_detcet
++	unsigned int _awb_ct;
++	unsigned int _awb_ct_last;
++	uint32_t  _wb_static[2];
++	unsigned int _light_src[20];
++	unsigned int _light_src_num;
++	unsigned int _rg_pos[15];
++	unsigned int _bg_pos[15];
++	unsigned int _awb_ct_th_ot_luxhigh[4];
++	unsigned int _awb_ct_th_ot_luxlow[4];
++	unsigned int _awb_ct_th_in[4];
++	unsigned int _awb_ct_para_ot[2];
++	unsigned int _awb_ct_para_in[2];
++	uint32_t _awb_dis_tw[3];
++	unsigned int _rgbg_weight[225];
++	unsigned int _color_temp_mesh[225];
++	unsigned int _awb_wght[225];
++	unsigned int _rgbg_weight_ot[225];
++	unsigned int _ls_w_lut[514];
++	uint32_t _ev;
++
++	void *core;			/*pointer to isp core top.*/
++} tisp_awb_t;
++
++typedef struct tisp_gamma {
++	u32 tiziano_gamma_lut[129];
++	void *core;			/*pinter to isp core.*/
++} tisp_gamma_t;
++
++/* ------ af ------- */
++
++typedef struct TizianoIsp_Af_Static_Param {
++	unsigned int *a_af_zone;
++	unsigned int *a_af_array_fird0;
++	unsigned int *a_af_array_fird1;
++	unsigned int *a_af_array_iird0;
++	unsigned int *a_af_array_iird1;
++	unsigned int *a_af_array_y_sum;
++	unsigned int *a_af_array_high_luma_cnt;
++	unsigned int *a_af_weight;
++	unsigned int *a_af_fv;
++	unsigned int *a_af_fvwmean;
++	uint32_t *a_af_tilt;
++	uint32_t *a_AfPointPos;
++	uint32_t width;
++	uint32_t height;
++} Isp_Af_Static_Param;
++
++typedef struct tisp_af {
++	Isp_Af_Static_Param IspAfStaticParam;
++	uint32_t af_array_fird0[225];
++	uint32_t af_array_fird1[225];
++	uint32_t af_array_iird0[225];
++	uint32_t af_array_iird1[225];
++	uint32_t af_array_y_sum[225];
++	uint32_t af_array_high_luma_cnt[225];
++	unsigned int stAFParam_Zone[36];
++	unsigned int stAFParam_ThresEnable[13];
++	unsigned int stAFParam_FIR0_V[5];
++	unsigned int stAFParam_FIR0_Ldg[8];
++	unsigned int stAFParam_FIR0_Coring[4];
++	unsigned int stAFParam_FIR1_V[5];
++	unsigned int stAFParam_FIR1_Ldg[8];
++	unsigned int stAFParam_FIR1_Coring[4];
++	unsigned int stAFParam_IIR0_H[10];
++	unsigned int stAFParam_IIR0_Ldg[8];
++	unsigned int stAFParam_IIR0_Coring[4];
++	unsigned int stAFParam_IIR1_H[10];
++	unsigned int stAFParam_IIR1_Ldg[8];
++	unsigned int stAFParam_IIR1_Coring[4];
++
++	/******Algorithm Param********/
++	uint32_t AFParam_PointPos[2];
++	uint32_t AFParam_Fv_Alt;
++	/* Alpha,Belta,Delta,Theta,BlendShift */
++	uint32_t AFParam_Tilt[5]; //[0 ~ 1] * 64 6bit point float
++
++	unsigned int AFParam_FvWmean[15];
++	unsigned int AFParam_Fv[3];
++	/* Fv1-->Alpha*h1+(1-Alpha)*v1 */
++	/* Fv2-->Belta*h2+(1-Belta)*v2 */
++	/* Fv -->Delta*Fv1+Theta*Fv2 */
++
++	unsigned int AFWeight_Param[225];
++
++	unsigned int FvWmean_num;
++
++	tisp_af_attr af_attr;
++	unsigned char af_set_trig;
++
++
++	void *core;
++} tisp_af_t;
++
++typedef struct tisp_gib {
++	uint32_t trig_set_deir;
++	/*parameter*/
++	uint32_t tiziano_gib_config_line[6];
++	uint32_t tiziano_gib_r_g_linear[2];
++	uint32_t tiziano_gib_b_ir_linear[2];
++
++	uint32_t tiziano_gib_deirm_blc_r_linear[9];
++	uint32_t tiziano_gib_deirm_blc_gr_linear[9];
++	uint32_t tiziano_gib_deirm_blc_gb_linear[9];
++	uint32_t tiziano_gib_deirm_blc_b_linear[9];
++	uint32_t tiziano_gib_deirm_blc_ir_linear[9];
++
++	uint32_t gib_ir_value[2];
++	uint32_t gib_ir_point[4];
++	uint32_t gib_ir_reser[15];
++	uint32_t tiziano_gib_deir_r_h[33];
++	uint32_t tiziano_gib_deir_g_h[33];
++	uint32_t tiziano_gib_deir_b_h[33];
++
++	uint32_t tiziano_gib_deir_r_m[33];
++	uint32_t tiziano_gib_deir_g_m[33];
++
++	uint32_t tiziano_gib_deir_b_m[33];
++
++	uint32_t tiziano_gib_deir_r_l[33];
++	uint32_t tiziano_gib_deir_g_l[33];
++	uint32_t tiziano_gib_deir_b_l[33];
++
++	uint32_t tiziano_gib_deir_matrix_h[15];
++	uint32_t tiziano_gib_deir_matrix_m[15];
++	uint32_t tiziano_gib_deir_matrix_l[15];
++	void *core;
++} tisp_gib_t;
++
++typedef struct tisp_lsc {
++	uint32_t lut_num;
++	uint32_t mesh_scale;
++	uint32_t lut_stride;
++	uint32_t mesh_size[2];
++	uint32_t a_linear[2047];
++	uint32_t t_linear[2047];
++	uint32_t d_linear[2047];
++	uint32_t mesh_lsc_str[9];
++	uint32_t lsc_change_flag;
++	uint32_t lsc_change_flag_last;
++	uint32_t tiziano_lsc_ct_points[4];
++	uint32_t ct;
++	uint32_t ct_last;
++	uint32_t lsc_gain_thres;
++	uint32_t lsc_gain_old;
++	uint32_t gain_no_change;
++	void *core;
++} tisp_lsc_t;
++
++
++/*ccm struct*/
++struct tisp_ccm_real {
++	uint32_t first_tune;
++	uint32_t ev_old;
++	uint32_t ev_threshold;
++	uint32_t ct_old;
++	uint32_t ct_threshold;
++	uint32_t cm_sat;
++};
++typedef struct tisp_ccm {
++
++	uint32_t tiziano_ccm_dp_cfg[1];
++	uint32_t tiziano_ccm_a_linear[9];
++	uint32_t tiziano_ccm_t_linear[9];
++	uint32_t tiziano_ccm_d_linear[9];
++	uint32_t tiziano_linear_value;
++	int32_t ccm_parameter[9];
++
++	uint32_t _ev;
++	uint32_t _ct;
++	struct tisp_ccm_real ccm_real;
++
++	int32_t _ccm_a_parameter[9];
++	int32_t _ccm_t_parameter[9];
++	int32_t _ccm_d_parameter[9];
++	uint32_t cm_ev_list[9];
++	uint32_t cm_sat_list[9];
++	uint32_t cm_awb_list[2];
++	void *core;
++} tisp_ccm_t;
++
++typedef struct tisp_dmsc {
++	int32_t dmsc_uu_np_array[16];
++	int32_t dmsc_sp_d_sigma_3_np_array[16];
++	int32_t dmsc_sp_d_w_wei_np_array[16];
++	int32_t dmsc_sp_d_b_wei_np_array[16];
++	int32_t dmsc_sp_ud_w_wei_np_array[16];
++	int32_t dmsc_sp_ud_b_wei_np_array[16];
++	/* out option */
++	int32_t dmsc_out_opt;
++	/* direction(hv aa hvaa value) tuning parameters */
++	int32_t dmsc_hv_thres_1_array[9];
++	int32_t dmsc_hv_stren_array[9];
++	int32_t dmsc_aa_thres_1_array[9];
++	int32_t dmsc_aa_stren_array[9];
++	int32_t dmsc_hvaa_thres_1_array[9];
++	int32_t dmsc_hvaa_stren_array[9];
++	int32_t dmsc_dir_par_array[9];
++	/* std and uu value tuning parameters */
++	int32_t dmsc_uu_thres_array[9];
++	int32_t dmsc_uu_stren_array[9];
++	int32_t dmsc_uu_par_array[3];
++	/* alias tuning parameters */
++	int32_t dmsc_alias_stren_array[9];
++	int32_t dmsc_alias_thres_1_array[9];
++	int32_t dmsc_alias_thres_2_array[9];
++	int32_t dmsc_alias_dir_thres_array[9];
++	int32_t dmsc_alias_par_array[4];
++	/* rgb nor blur wei tuning parameters */
++	int32_t dmsc_nor_alias_thres_array[9];
++	int32_t dmsc_nor_par_array[4];
++	/* d sharpen tuning parameters */
++	int32_t dmsc_sp_d_w_stren_array[9];
++	int32_t dmsc_sp_d_b_stren_array[9];
++	int32_t dmsc_sp_d_brig_thres_array[9];
++	int32_t dmsc_sp_d_dark_thres_array[9];
++	int32_t dmsc_sp_d_par_array[8];
++	/* ud sharpen tuning parameters */
++	int32_t dmsc_sp_ud_w_stren_array[9];
++	int32_t dmsc_sp_ud_b_stren_array[9];
++	int32_t dmsc_sp_ud_brig_thres_array[9];
++	int32_t dmsc_sp_ud_dark_thres_array[9];
++	int32_t dmsc_sp_ud_par_array[8];
++	/* sp wei tuning parameters */
++	int32_t dmsc_sp_alias_thres_array[9];
++	int32_t dmsc_sp_alias_par_array[2];
++	/* alias rgb tuning parameters */
++	int32_t dmsc_rgb_dir_thres_array[9];
++	int32_t dmsc_rgb_alias_stren_array[9];
++	int32_t dmsc_rgb_alias_par_array[2];
++	/* fc tuning parameters */
++	int32_t dmsc_fc_alias_stren_array[9];
++	int32_t dmsc_fc_t1_thres_array[9];
++	int32_t dmsc_fc_t1_stren_array[9];
++	int32_t dmsc_fc_t2_stren_array[9];
++	int32_t dmsc_fc_t3_stren_array[9];
++	int32_t dmsc_fc_par_array[9];
++
++	uint32_t dmsc_hv_thres_1_intp;
++	uint32_t dmsc_hv_stren_intp;
++	uint32_t dmsc_aa_thres_1_intp;
++	uint32_t dmsc_aa_stren_intp;
++	uint32_t dmsc_hvaa_thres_1_intp;
++	uint32_t dmsc_hvaa_stren_intp;
++	uint32_t dmsc_uu_thres_intp;
++	uint32_t dmsc_uu_stren_intp;
++	uint32_t dmsc_alias_stren_intp;
++	uint32_t dmsc_alias_thres_1_intp;
++	uint32_t dmsc_alias_thres_2_intp;
++	uint32_t dmsc_alias_dir_thres_intp;
++	uint32_t dmsc_nor_alias_thres_intp;
++	uint32_t dmsc_sp_d_w_stren_intp;
++	uint32_t dmsc_sp_d_b_stren_intp;
++	uint32_t dmsc_sp_d_brig_thres_intp;
++	uint32_t dmsc_sp_d_dark_thres_intp;
++	uint32_t dmsc_sp_ud_w_stren_intp;
++	uint32_t dmsc_sp_ud_b_stren_intp;
++	uint32_t dmsc_sp_ud_brig_thres_intp;
++	uint32_t dmsc_sp_ud_dark_thres_intp;
++	uint32_t dmsc_sp_alias_thres_intp;
++	uint32_t dmsc_rgb_dir_thres_intp;
++	uint32_t dmsc_rgb_alias_stren_intp;
++	uint32_t dmsc_fc_alias_stren_intp;
++	uint32_t dmsc_fc_t1_thres_intp;
++	uint32_t dmsc_fc_t1_stren_intp;
++	uint32_t dmsc_fc_t2_stren_intp;
++	uint32_t dmsc_fc_t3_stren_intp;
++
++	uint32_t gain_old;
++	uint32_t gain_thres;
++	uint32_t shadow_en;
++
++	void *core;
++} tisp_dmsc_t;
++
++typedef struct tisp_sharpen {
++	int32_t sharpen_uu_np_array[16];    //8 bits  0~255
++	int32_t sharpen_v1_sigma_np_array[16];    //5 bits  0~16
++	int32_t sharpen_w_wei_np_array[16];    //6 bits  0~32
++	int32_t sharpen_b_wei_np_array[16];    //6 bits  0~32
++	int32_t sharpen_uu_thres_array[9];
++	int32_t sharpen_uu_stren_array[9];
++	int32_t sharpen_uu_par_array[3];
++	int32_t sharpen_pixel_thres_array[9];
++	int32_t sharpen_w_stren_array[9];
++	int32_t sharpen_b_stren_array[9];
++	int32_t sharpen_brig_thres_array[9];
++	int32_t sharpen_dark_thres_array[9];
++	int32_t sharpen_con_par_array[8];
++
++	/* sharpen intp parameters */
++	uint32_t sharpen_uu_thres_intp;
++	uint32_t sharpen_uu_stren_intp;
++	uint32_t sharpen_pixel_thres_intp;
++	uint32_t sharpen_w_stren_intp;
++	uint32_t sharpen_b_stren_intp;
++	uint32_t sharpen_birg_thres_intp;
++	uint32_t sharpen_dark_thres_intp;
++
++	uint32_t gain_old;
++	uint32_t gain_thres;
++	uint32_t shadow_en;
++	void *core;
++} tisp_sharpen_t;
++
++typedef struct tisp_sdns {
++	int32_t sdns_top_func_array[2];
++	int32_t sdns_y_dtl_thres_array[9];
++	int32_t sdns_y_fus_slope_array[9];
++	int32_t sdns_y_lum_divop_array[9];
++	int32_t sdns_y_dtl_segop_array[9];
++	int32_t sdns_y_fus_segop_array[9];
++	int32_t sdns_y_lum_segop_array[9];
++	int32_t sdns_y_dsp_segop_array[9];
++	int32_t sdns_y_bsp_segop_array[9];
++	int32_t sdns_y_dtl_stren_array[9];
++	int32_t sdns_y_fus_stren_array[9];
++	int32_t sdns_y_lum_stren_array[9];
++	int32_t sdns_y_dsp_stren_array[9];
++	int32_t sdns_y_bsp_stren_array[9];
++	int32_t sdns_y_dtl_npv_0_array[9];
++	int32_t sdns_y_dtl_npv_1_array[9];
++	int32_t sdns_y_dtl_npv_2_array[9];
++	int32_t sdns_y_dtl_npv_3_array[9];
++	int32_t sdns_y_dtl_npv_4_array[9];
++	int32_t sdns_y_fus_npv_array[16];
++	int32_t sdns_y_lum_npv_array[16];
++	int32_t sdns_y_dsp_npv_array[16];
++	int32_t sdns_y_bsp_npv_array[16];
++	int32_t sdns_y_bil_stren_array[9];
++	int32_t sdns_y_bil_npv_array[15];
++	int32_t sdns_c_bas_wei_array[9];
++	int32_t sdns_c_fus_mod_array[9];
++	int32_t sdns_c_flu_cal_array[9];
++	int32_t sdns_c_flu_stren_array[9];
++	int32_t sdns_c_flu_npv_array[16];
++
++	/* sdns intp parameters */
++	uint32_t sdns_y_dtl_thres_intp;
++	uint32_t sdns_y_fus_slope_intp;
++	uint32_t sdns_y_lum_divop_intp;
++	uint32_t sdns_y_dtl_segop_intp;
++	uint32_t sdns_y_fus_segop_intp;
++	uint32_t sdns_y_lum_segop_intp;
++	uint32_t sdns_y_dsp_segop_intp;
++	uint32_t sdns_y_bsp_segop_intp;
++	uint32_t sdns_y_dtl_stren_intp;
++	uint32_t sdns_y_fus_stren_intp;
++	uint32_t sdns_y_lum_stren_intp;
++	uint32_t sdns_y_dsp_stren_intp;
++	uint32_t sdns_y_bsp_stren_intp;
++	uint32_t sdns_y_bil_stren_intp;
++	uint32_t sdns_y_dtl_npv_0_intp;
++	uint32_t sdns_y_dtl_npv_1_intp;
++	uint32_t sdns_y_dtl_npv_2_intp;
++	uint32_t sdns_y_dtl_npv_3_intp;
++	uint32_t sdns_y_dtl_npv_4_intp;
++	uint32_t sdns_c_bas_wei_intp;
++	uint32_t sdns_c_fus_mod_intp;
++	uint32_t sdns_c_flu_cal_intp;
++	uint32_t sdns_c_flu_stren_intp;
++
++	uint32_t gain_old;
++	uint32_t gain_thres;
++	void *core;
++} tisp_sdns_t;
++
++/* ----------- dpc ------------*/
++typedef struct tisp_dpc {
++	/* dpc parameters */
++	int32_t ctr_md_np_array[16];
++	int32_t rdns_uu_np_array[16];
++	int32_t rdns_g_lum_np_array[16];
++	int32_t rdns_g_std_np_array[16];
++	int32_t rdns_rb_lum_np_array[16];
++	int32_t rdns_rb_std_np_array[16];
++	int32_t dpc_s_text_thres_array[9];
++	int32_t dpc_s_con_par_array[5];
++	int32_t dpc_d_m1_level_array[9];
++	int32_t dpc_d_m1_l0_fthres_array[9];
++	int32_t dpc_d_m1_l0_dthres_array[9];
++	int32_t dpc_d_m1_l1_hthres_array[9];
++	int32_t dpc_d_m1_l1_lthres_array[9];
++	int32_t dpc_d_m1_l1_d1_thres_array[9];
++	int32_t dpc_d_m1_l1_d2_thres_array[9];
++	int32_t dpc_d_m1_con_par_array[14];
++	int32_t dpc_d_m2_level_array[9];
++	int32_t dpc_d_m2_l0_thres_array[9];
++	int32_t dpc_d_m2_l1_ldthres_array[9];
++	int32_t dpc_d_m2_l1_pdthres_array[9];
++	int32_t dpc_d_m2_con_par_array[6];
++	int32_t ctr_stren_array[9];
++	int32_t ctr_md_thres_array[9];
++	int32_t ctr_el_thres_array[9];
++	int32_t ctr_eh_thres_array[9];
++	int32_t ctr_con_par_array[5];
++	int32_t rdns_stren_array[9];
++	int32_t rdns_std_thres_array[9];
++	int32_t rdns_y_fthres_array[9];
++	int32_t rdns_y_tthres_array[9];
++	int32_t rdns_uv_fthres_array[9];
++	int32_t rdns_uv_tthres_array[9];
++	int32_t rdns_con_par_array[10];
++	int32_t dpc_s_text_thres_intp;
++	int32_t dpc_d_m1_level_intp;
++	int32_t dpc_d_m1_l0_fthres_intp;
++	int32_t dpc_d_m1_l0_dthres_intp;
++	int32_t dpc_d_m1_l1_hthres_intp;
++	int32_t dpc_d_m1_l1_lthres_intp;
++	int32_t dpc_d_m1_l1_d1_thres_intp;
++	int32_t dpc_d_m1_l1_d2_thres_intp;
++	int32_t dpc_d_m2_level_intp;
++	int32_t dpc_d_m2_l0_thres_intp;
++	int32_t dpc_d_m2_l1_ldthres_intp;
++	int32_t dpc_d_m2_l1_pdthres_intp;
++	int32_t ctr_stren_intp;
++	int32_t ctr_md_thres_intp;
++	int32_t ctr_el_thres_intp;
++	int32_t ctr_eh_thres_intp;
++	int32_t rdns_stren_intp;
++	int32_t rdns_std_thres_intp;
++	int32_t rdns_y_fthres_intp;
++	int32_t rdns_y_tthres_intp;
++	int32_t rdns_uv_fthres_intp;
++	int32_t rdns_uv_tthres_intp;
++	void *core;
++} tisp_dpc_t;
++
++/* --------- mdns --------------*/
++
++typedef struct tisp_mdns {
++	int vin_width;
++	int vin_height;
++
++	/* mdns parameters */
++	int32_t mdns_top_func_array[24];
++	int32_t mdns_sta_size_array[9];
++	int32_t mdns_pbt_size_array[9];
++	int32_t mdns_pbt_ponit_array[2];
++	int32_t mdns_y_sad_thres_array[9];
++	int32_t mdns_y_sta_thres_array[9];
++	int32_t mdns_y_pbt_thres_array[9];
++	int32_t mdns_y_sad_stren_array[9];
++	int32_t mdns_y_sta_stren_array[9];
++	int32_t mdns_y_pbt_stren_array[9];
++	int32_t mdns_y_sad_win_opt_array[9];
++	int32_t mdns_y_sta_win_opt_array[9];
++	int32_t mdns_y_pbt_win_opt_array[9];
++	int32_t mdns_y_sad_win_wei_array[9];
++	int32_t mdns_y_sta_win_wei_array[9];
++	int32_t mdns_y_pbt_win_wei_array[9];
++	int32_t mdns_y_sta_mv_num_array[9];
++	int32_t mdns_y_pbt_mv_num_array[9];
++	int32_t mdns_y_sta_mx_num_array[9];
++	int32_t mdns_y_pbt_mx_num_array[9];
++	int32_t mdns_y_sad_npv_array[4];
++	int32_t mdns_y_sta_npv_array[32];
++	int32_t mdns_y_pbt_npv_array[32];
++	int32_t mdns_y_ref_wei_min_array[9];
++	int32_t mdns_y_ref_wei_max_array[9];
++	int32_t mdns_y_edge_type_array[1];
++	int32_t mdns_y_edge_win_array[9];
++	int32_t mdns_y_bi_thres_array[9];
++	int32_t mdns_y_smj_thres_array[9];
++	int32_t mdns_y_shp_swei_array[9];
++	int32_t mdns_y_shp_mwei_array[9];
++	int32_t mdns_y_cs_bhold_array[9];
++	int32_t mdns_y_cm_bhold_array[9];
++	int32_t mdns_y_rs_bhold_array[9];
++	int32_t mdns_y_rm_bhold_array[9];
++	int32_t mdns_y_cs_bwin_array[9];
++	int32_t mdns_y_cm_bwin_array[9];
++	int32_t mdns_y_rs_bwin_array[9];
++	int32_t mdns_y_rm_bwin_array[9];
++	int32_t mdns_y_cs_iwin_array[9];
++	int32_t mdns_y_cm_iwin_array[9];
++	int32_t mdns_y_rs_iwin_array[9];
++	int32_t mdns_y_rm_iwin_array[9];
++	int32_t mdns_y_cs_ewin_array[9];
++	int32_t mdns_y_cm_ewin_array[9];
++	int32_t mdns_y_rs_ewin_array[9];
++	int32_t mdns_y_rm_ewin_array[9];
++	int32_t mdns_y_cs_sego_array[9];
++	int32_t mdns_y_cm_sego_array[9];
++	int32_t mdns_y_rs_sego_array[9];
++	int32_t mdns_y_rm_sego_array[9];
++	int32_t mdns_y_cs_stren_array[9];
++	int32_t mdns_y_cm_stren_array[9];
++	int32_t mdns_y_rs_stren_array[9];
++	int32_t mdns_y_rm_stren_array[9];
++	int32_t mdns_y_cs_npv_array[16];
++	int32_t mdns_y_cm_npv_array[16];
++	int32_t mdns_y_rs_npv_array[16];
++	int32_t mdns_y_rm_npv_array[16];
++	int32_t mdns_y_shp_c_0_npv_array[9];
++	int32_t mdns_y_shp_c_1_npv_array[9];
++	int32_t mdns_y_shp_c_2_npv_array[9];
++	int32_t mdns_y_shp_c_3_npv_array[9];
++	int32_t mdns_y_shp_c_4_npv_array[9];
++	int32_t mdns_y_shp_c_5_npv_array[9];
++	int32_t mdns_y_shp_c_6_npv_array[9];
++	int32_t mdns_y_shp_c_7_npv_array[9];
++	int32_t mdns_y_shp_c_8_npv_array[9];
++	int32_t mdns_y_shp_c_9_npv_array[9];
++	int32_t mdns_y_shp_c_a_npv_array[9];
++	int32_t mdns_y_shp_c_b_npv_array[9];
++	int32_t mdns_y_shp_c_c_npv_array[9];
++	int32_t mdns_y_shp_c_d_npv_array[9];
++	int32_t mdns_y_shp_c_e_npv_array[9];
++	int32_t mdns_y_shp_c_f_npv_array[9];
++	int32_t mdns_y_shp_r_0_npv_array[9];
++	int32_t mdns_y_shp_r_1_npv_array[9];
++	int32_t mdns_y_shp_r_2_npv_array[9];
++	int32_t mdns_y_shp_r_3_npv_array[9];
++	int32_t mdns_y_shp_r_4_npv_array[9];
++	int32_t mdns_y_shp_r_5_npv_array[9];
++	int32_t mdns_y_shp_r_6_npv_array[9];
++	int32_t mdns_y_shp_r_7_npv_array[9];
++	int32_t mdns_y_shp_r_8_npv_array[9];
++	int32_t mdns_y_shp_r_9_npv_array[9];
++	int32_t mdns_y_shp_r_a_npv_array[9];
++	int32_t mdns_y_shp_r_b_npv_array[9];
++	int32_t mdns_y_shp_r_c_npv_array[9];
++	int32_t mdns_y_shp_r_d_npv_array[9];
++	int32_t mdns_y_shp_r_e_npv_array[9];
++	int32_t mdns_y_shp_r_f_npv_array[9];
++	int32_t mdns_y_adj_cnr_array[4];
++	int32_t mdns_y_fluct_lmt_array[8];
++	int32_t mdns_y_adj_sta_array[9];
++	int32_t mdns_y_adj_tedg_s_array[9];
++	int32_t mdns_y_adj_wedg_s_array[9];
++	int32_t mdns_y_adj_tedg_n_array[8];
++	int32_t mdns_y_adj_wedg_n_array[8];
++	int32_t mdns_y_adj_lum_win_array[1];
++	int32_t mdns_y_adj_tlum_s_array[9];
++	int32_t mdns_y_adj_wlum_s_array[9];
++	int32_t mdns_y_adj_tlum_n_array[16];
++	int32_t mdns_y_adj_wlum_n_array[16];
++	int32_t mdns_c_sad_thres_array[9];
++	int32_t mdns_c_sad_win_opt_array[9];
++	int32_t mdns_c_sad_stren_array[9];
++	int32_t mdns_c_sta_stren_array[9];
++	int32_t mdns_c_pbt_stren_array[9];
++	int32_t mdns_c_sad_npv_array[4];
++	int32_t mdns_c_sta_npv_array[32];
++	int32_t mdns_c_pbt_npv_array[32];
++	int32_t mdns_c_ref_wei_min_array[9];
++	int32_t mdns_c_ref_wei_max_array[9];
++	int32_t mdns_c_cur_blur_array[9];
++	int32_t mdns_c_ref_blur_array[9];
++	int32_t mdns_c_smj_thres_array[9];
++	int32_t mdns_c_sfla_boh_t_array[9];
++	int32_t mdns_c_sfla_cut_t_array[9];
++	int32_t mdns_c_sfla_boh_s_array[9];
++	int32_t mdns_c_sfla_cut_s_array[9];
++	int32_t mdns_c_mfla_boh_t_array[9];
++	int32_t mdns_c_mfla_cut_t_array[9];
++	int32_t mdns_c_mfla_boh_s_array[9];
++	int32_t mdns_c_mfla_cut_s_array[9];
++	int32_t mdns_c_adj_cnr_array[4];
++	int32_t mdns_c_adj_sta_array[6];
++	int32_t mdns_c_adj_tcrm_s_array[9];
++	int32_t mdns_c_adj_wcrm_s_array[9];
++	int32_t mdns_c_adj_tcrm_n_array[8];
++	int32_t mdns_c_adj_wcrm_n_array[8];
++
++	/* mdns intp parameters */
++	uint32_t mdns_sta_size_intp;
++	uint32_t mdns_pbt_size_intp;
++	uint32_t mdns_y_sad_thres_intp;
++	uint32_t mdns_y_sta_thres_intp;
++	uint32_t mdns_y_pbt_thres_intp;
++	uint32_t mdns_y_sad_stren_intp;
++	uint32_t mdns_y_sta_stren_intp;
++	uint32_t mdns_y_pbt_stren_intp;
++	uint32_t mdns_y_sad_win_opt_intp;
++	uint32_t mdns_y_sta_win_opt_intp;
++	uint32_t mdns_y_pbt_win_opt_intp;
++	uint32_t mdns_y_sad_win_wei_intp;
++	uint32_t mdns_y_sta_win_wei_intp;
++	uint32_t mdns_y_pbt_win_wei_intp;
++	uint32_t mdns_y_sta_mv_num_intp;
++	uint32_t mdns_y_pbt_mv_num_intp;
++	uint32_t mdns_y_sta_mx_num_intp;
++	uint32_t mdns_y_pbt_mx_num_intp;
++	uint32_t mdns_y_ref_wei_min_intp;
++	uint32_t mdns_y_ref_wei_max_intp;
++	uint32_t mdns_y_edge_win_intp;
++	uint32_t mdns_y_bi_thres_intp;
++	uint32_t mdns_y_smj_thres_intp;
++	uint32_t mdns_y_shp_swei_intp;
++	uint32_t mdns_y_shp_mwei_intp;
++	uint32_t mdns_y_cs_bhold_intp;
++	uint32_t mdns_y_cm_bhold_intp;
++	uint32_t mdns_y_rs_bhold_intp;
++	uint32_t mdns_y_rm_bhold_intp;
++	uint32_t mdns_y_cs_bwin_intp;
++	uint32_t mdns_y_cm_bwin_intp;
++	uint32_t mdns_y_rs_bwin_intp;
++	uint32_t mdns_y_rm_bwin_intp;
++	uint32_t mdns_y_cs_iwin_intp;
++	uint32_t mdns_y_cm_iwin_intp;
++	uint32_t mdns_y_rs_iwin_intp;
++	uint32_t mdns_y_rm_iwin_intp;
++	uint32_t mdns_y_cs_ewin_intp;
++	uint32_t mdns_y_cm_ewin_intp;
++	uint32_t mdns_y_rs_ewin_intp;
++	uint32_t mdns_y_rm_ewin_intp;
++	uint32_t mdns_y_cs_sego_intp;
++	uint32_t mdns_y_cm_sego_intp;
++	uint32_t mdns_y_rs_sego_intp;
++	uint32_t mdns_y_rm_sego_intp;
++	uint32_t mdns_y_cs_stren_intp;
++	uint32_t mdns_y_cm_stren_intp;
++	uint32_t mdns_y_rs_stren_intp;
++	uint32_t mdns_y_rm_stren_intp;
++	uint32_t mdns_y_shp_c_0_npv_intp;
++	uint32_t mdns_y_shp_c_1_npv_intp;
++	uint32_t mdns_y_shp_c_2_npv_intp;
++	uint32_t mdns_y_shp_c_3_npv_intp;
++	uint32_t mdns_y_shp_c_4_npv_intp;
++	uint32_t mdns_y_shp_c_5_npv_intp;
++	uint32_t mdns_y_shp_c_6_npv_intp;
++	uint32_t mdns_y_shp_c_7_npv_intp;
++	uint32_t mdns_y_shp_c_8_npv_intp;
++	uint32_t mdns_y_shp_c_9_npv_intp;
++	uint32_t mdns_y_shp_c_a_npv_intp;
++	uint32_t mdns_y_shp_c_b_npv_intp;
++	uint32_t mdns_y_shp_c_c_npv_intp;
++	uint32_t mdns_y_shp_c_d_npv_intp;
++	uint32_t mdns_y_shp_c_e_npv_intp;
++	uint32_t mdns_y_shp_c_f_npv_intp;
++	uint32_t mdns_y_shp_r_0_npv_intp;
++	uint32_t mdns_y_shp_r_1_npv_intp;
++	uint32_t mdns_y_shp_r_2_npv_intp;
++	uint32_t mdns_y_shp_r_3_npv_intp;
++	uint32_t mdns_y_shp_r_4_npv_intp;
++	uint32_t mdns_y_shp_r_5_npv_intp;
++	uint32_t mdns_y_shp_r_6_npv_intp;
++	uint32_t mdns_y_shp_r_7_npv_intp;
++	uint32_t mdns_y_shp_r_8_npv_intp;
++	uint32_t mdns_y_shp_r_9_npv_intp;
++	uint32_t mdns_y_shp_r_a_npv_intp;
++	uint32_t mdns_y_shp_r_b_npv_intp;
++	uint32_t mdns_y_shp_r_c_npv_intp;
++	uint32_t mdns_y_shp_r_d_npv_intp;
++	uint32_t mdns_y_shp_r_e_npv_intp;
++	uint32_t mdns_y_shp_r_f_npv_intp;
++	uint32_t mdns_y_adj_tedg_s_intp;
++	uint32_t mdns_y_adj_wedg_s_intp;
++	uint32_t mdns_y_adj_tlum_s_intp;
++	uint32_t mdns_y_adj_wlum_s_intp;
++	uint32_t mdns_c_sad_thres_intp;
++	uint32_t mdns_c_sad_win_opt_intp;
++	uint32_t mdns_c_sad_stren_intp;
++	uint32_t mdns_c_sta_stren_intp;
++	uint32_t mdns_c_pbt_stren_intp;
++	uint32_t mdns_c_ref_wei_min_intp;
++	uint32_t mdns_c_ref_wei_max_intp;
++	uint32_t mdns_c_cur_blur_intp;
++	uint32_t mdns_c_ref_blur_intp;
++	uint32_t mdns_c_smj_thres_intp;
++	uint32_t mdns_c_sfla_boh_t_intp;
++	uint32_t mdns_c_sfla_cut_t_intp;
++	uint32_t mdns_c_sfla_boh_s_intp;
++	uint32_t mdns_c_sfla_cut_s_intp;
++	uint32_t mdns_c_mfla_boh_t_intp;
++	uint32_t mdns_c_mfla_cut_t_intp;
++	uint32_t mdns_c_mfla_boh_s_intp;
++	uint32_t mdns_c_mfla_cut_s_intp;
++	uint32_t mdns_c_adj_tcrm_s_intp;
++	uint32_t mdns_c_adj_wcrm_s_intp;
++	void *core;
++} tisp_mdns_t;
++
++/* -------- clm --------*/
++typedef struct tisp_clm {
++	int32_t tiziano_clm_h_lut[30 * 7 * 5];
++	int32_t tiziano_clm_s_lut[30 * 7 * 5];
++	int32_t tiziano_clm_s_reg[420];
++	int32_t tiziano_clm_h_reg[420];
++	uint32_t tiziano_clm_lut_shift;
++
++	void *core;
++} tisp_clm_t;
++
++
++/* ------------ hldc ------------*/
++typedef struct tisp_hldc {
++	uint32_t hldc_con_par_array[18];
++
++	void *core;
++} tisp_hldc_t;
++
++typedef int32_t (*net_event_cb)(void *cb_data, void *data, uint32_t len);
++typedef struct tisp_netlink {
++	struct sock *nlsk;
++	net_event_cb net_event_process;
++	void *cb_data;
++} tisp_netlink_t;
++
++
++/*------------param_op-----------*/
++typedef struct {
++	uint32_t msg_type;
++	uint32_t msg_data1;
++	uint32_t msg_data2;
++	uint32_t msg_data3;
++	uint32_t msg_data4;
++	uint32_t msg_ret;
++	uint8_t  msg_buf[0];
++} tisp_param_op_msg_t;
++
++typedef struct tisp_param_operate {
++	tisp_param_op_msg_t *opmsg;	/*tisp_param_op_msg_t 类型.*/
++	tisp_netlink_t nl;
++
++	void *core;
++} tisp_param_operate_t;
++
++
++/* ---------- event ----------*/
++enum {
++	//ae
++	TISP_EVENT_TYPE_START = 0,
++	TISP_EVENT_TYPE_EXIT = TISP_EVENT_TYPE_START,
++	TISP_EVENT_TYPE_AE_PROCESS,
++	TISP_EVENT_TYPE_ADR_PROCESS,
++	TISP_EVENT_TYPE_DEFOG_PROCESS,
++	TISP_EVENT_TYPE_AE_TGAIN_UPDATE,
++	TISP_EVENT_TYPE_AE_AGAIN_UPDATE,
++	//for awb
++	TISP_EVENT_TYPE_AE_EV,
++	TISP_EVENT_TYPE_AE_IR,
++	TISP_EVENT_TYPE_AWB_CT,
++	//for awb
++	TISP_EVENT_TYPE_WB_STAITCS,
++	TISP_EVENT_TYPE_MAX,
++};
++
++#define TISP_PROCESS_EVENT_NUM 20
++
++typedef struct {
++	struct list_head entry;
++	uint32_t type;
++	uint64_t data1;
++	uint64_t data2;
++	uint64_t data3;
++	uint64_t data4;
++} tisp_event_t;
++
++typedef struct {
++	struct completion event_compl;
++	tisp_event_t events[TISP_PROCESS_EVENT_NUM];
++	struct list_head event_working;
++	struct list_head event_free;
++	spinlock_t event_slock;
++} tisp_event_info_t;
++
++typedef int32_t (*event_process_cb)(void *cb_data, uint64_t data1, uint64_t data2, uint64_t data3, uint64_t data4);
++
++/* event manager .*/
++typedef struct tisp_event_mg {
++	tisp_event_info_t tevent_info;
++
++	event_process_cb cb[TISP_EVENT_TYPE_MAX];
++	void *cb_data[TISP_EVENT_TYPE_MAX];
++
++	void *core;
++
++} tisp_event_mg_t;
++
++
++
++typedef struct tisp_core {
++	tisp_info_t tispinfo;
++
++	sensor_control_t sensor_ctrl;
++	struct sensor_control_ops *sensor_ctrl_ops;
++
++	tisp_custom_effect_t custom_eff;
++	tisp_mdns_ratio_t mdns_ratio;
++	int deir_en;
++	int ae_switch;
++	uint32_t topreg_val;
++	tisp_init_param_t sensor_info;
++
++	/* sub handles. */
++	tisp_awb_t awb;
++	tisp_gamma_t gamma;
++	tisp_defog_t defog;
++	tisp_adr_t   adr;
++	tisp_ae_t    ae;
++	tisp_af_t    af;
++	tisp_gib_t   gib;
++	tisp_dmsc_t  dmsc;
++	tisp_lsc_t   lsc;
++	tisp_ccm_t   ccm;
++	tisp_sharpen_t sharpen;
++	tisp_dpc_t   dpc;
++	tisp_sdns_t  sdns;
++	tisp_mdns_t  mdns;
++	tisp_clm_t   clm;
++	tisp_hldc_t  hldc;
++	tisp_param_operate_t param_operate;
++
++	tisp_core_tuning_t core_tuning;
++	tisp_event_mg_t tisp_event_mg;
++
++	void *tuned_params;
++	loff_t tuned_params_size;
++
++	void *priv_data;
++} tisp_core_t;
++
++int tisp_core_init(tisp_core_t *core, tisp_init_param_t *p, void *priv_data);
++int tisp_core_deinit(tisp_core_t *core);
++
++int tisp_channel_start(tisp_core_t *core, int chx);
++int tisp_channel_start_restore(tisp_core_t *core);
++int tisp_channel_stop(tisp_core_t *core, int chx);
++int tisp_channel_stop_save(tisp_core_t *core);
++int tisp_channel_attr_set(tisp_core_t *core, int chx ,tisp_channel_attr_t * cattr);
++int tisp_channel_attr_set_crop_scaler(tisp_core_t *core, int chx ,tisp_channel_attr_t * cattr);
++
++int tisp_fw_process(tisp_core_t *core);
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_core_tuning.h b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_core_tuning.h
+new file mode 100644
+index 000000000..5d351588e
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_core_tuning.h
+@@ -0,0 +1,170 @@
++#ifndef __TIZIANO_TIZIANO_CORE_TUNING_H__
++#define __TIZIANO_TIZIANO_CORE_TUNING_H__
++#include "tiziano_isp.h"
++
++extern int day_night;
++
++typedef enum tisp_mode_day_and_night {
++	TISP_MODE_DAY_MODE,
++	TISP_MODE_NIGHT_MODE,
++	TISP_MODE_BUTT,
++} TISP_MODE_DN_E;
++
++typedef struct tisp_custom_effect {
++	unsigned char brightness;
++	unsigned char sharpness;
++	unsigned char contrast;
++	unsigned char saturation;
++	unsigned int brightness_ori_day[20];
++	unsigned int brightness_ori_night[20];
++	unsigned int saturation_ori_day[9];
++	unsigned int sharpen_ori_day[36];
++	unsigned int sharpen_ori_night[36];
++
++} tisp_custom_effect_t;
++
++typedef struct tisp_mdns_ratio {
++	int dysad_thres_def_day[9];
++	int dysta_thres_def_day[9];
++	int dypbt_thres_def_day[9];
++	int dywei_max_def_day[9];
++	int dywei_min_def_day[9];
++	int dysad_thres_def_night[9];
++	int dysta_thres_def_night[9];
++	int dypbt_thres_def_night[9];
++	int dywei_max_def_night[9];
++	int dywei_min_def_night[9];
++} tisp_mdns_ratio_t;
++
++typedef struct tisp_ncu_info {
++	uint32_t width;
++	uint32_t height;
++	uint32_t sta_y_block_size;
++	uint32_t sta_y_stride;
++	uint32_t sta_y_buf_size;
++} tisp_ncu_info_t;
++
++typedef struct tisp_gamma_lut{
++	unsigned int gamma[129];
++} tisp_gamma_lut_t;
++
++typedef struct tisp_3a_weight{
++	unsigned int weight[225];
++} tisp_3a_weight_t;
++
++typedef struct tisp_zone_info{
++	unsigned int zone[15][15];
++} tisp_zone_info_t;
++
++typedef struct tisp_ev_attr {
++	unsigned int integration_time;
++	unsigned int ev;
++	unsigned int expr_us;
++	unsigned int ev_log2;
++	unsigned int again;
++	unsigned int dgain;
++	unsigned int gain_log2;
++	unsigned int total_gain;
++	unsigned int max_again;
++	unsigned int max_isp_dgain;
++	unsigned int sensor_dgain;
++	unsigned int max_sensor_dgain;
++	int manual_it;
++	int manual_ag;
++	int manual_isp_dgain;
++} tisp_ev_attr_t;
++
++typedef struct tisp_ae_ex_min {
++	unsigned int min_it;
++	unsigned int min_again;
++} tisp_ae_ex_min_t;
++
++typedef union tisp_module_control {
++	unsigned int key;
++	struct {
++		unsigned int bitBypassDPC : 1; /* [0]  */
++		unsigned int bitBypassGIB : 1; /* [1]  */
++		unsigned int bitBypassLSC : 1; /* [2]  */
++		unsigned int bitBypassAWB : 1; /* [3]  */
++		unsigned int bitBypassADR : 1; /* [4]  */
++		unsigned int bitBypassDMSC : 1; /* [5]  */
++		unsigned int bitBypassCCM : 1; /* [6]  */
++		unsigned int bitBypassGAMMA : 1; /* [7]  */
++		unsigned int bitBypassDEFOG : 1; /* [8]  */
++		unsigned int bitBypassCLM : 1; /* [9]  */
++		unsigned int bitBypassYSHARPEN : 1; /* [10]  */
++		unsigned int bitBypassMDNS : 1; /* [11]  */
++		unsigned int bitBypassSDNS : 1; /* [12]  */
++		unsigned int bitBypassHLDC : 1; /* [13]  */
++		unsigned int bitBypassTP : 1; /* [14]  */
++		unsigned int bitBypassFONT : 1; /* [15]  */
++		unsigned int bitRsv : 15; /* [16 ~ 30]  */
++		unsigned int bitRsv2 : 1; /* [31]  */
++	};
++} tisp_module_control_t;
++
++
++
++typedef struct tisp_core_tuning {
++	int day_night;
++	int flicker_hz;
++	void *core;	/*tisp_core_t in tiziano_core.h*/
++} tisp_core_tuning_t;
++
++
++int32_t tisp_day_or_night_s_ctrl(tisp_core_tuning_t *core_tuning, TISP_MODE_DN_E dn);
++TISP_MODE_DN_E tisp_day_or_night_g_ctrl(tisp_core_tuning_t *core_tuning);
++void tisp_mirror_enable(tisp_core_tuning_t *core_tuning, int en);
++void tisp_flip_enable(tisp_core_tuning_t *core_tuning, int en);
++int tisp_set_fps(tisp_core_tuning_t *core_tuning, int fps);
++
++void tisp_set_brightness(tisp_core_tuning_t *core_tuning, unsigned char brightness);
++void tisp_set_sharpness(tisp_core_tuning_t *core_tuning, unsigned char sharpness);
++void tisp_set_saturation(tisp_core_tuning_t *core_tuning, unsigned char saturation);
++void tisp_set_contrast(tisp_core_tuning_t *core_tuning, unsigned char contrast);
++
++unsigned char tisp_get_brightness(tisp_core_tuning_t *core_tuning);
++unsigned char tisp_get_sharpness(tisp_core_tuning_t *core_tuning);
++unsigned char tisp_get_saturation(tisp_core_tuning_t *core_tuning);
++unsigned char tisp_get_contrast(tisp_core_tuning_t *core_tuning);
++void tisp_top_sel(tisp_core_tuning_t *core_tuning, int sel);
++int tisp_g_ncuinfo(tisp_core_tuning_t *core_tuning, tisp_ncu_info_t *ncuinfo);
++unsigned int tisp_top_read(tisp_core_tuning_t *core_tuning);
++int tisp_s_antiflick(tisp_core_tuning_t *core_tuning, int hz);
++int tisp_s_Hilightdepress(tisp_core_tuning_t *core_tuning, unsigned int strength);
++int tisp_g_Hilightdepress(tisp_core_tuning_t *core_tuning, unsigned int *strength);
++int tisp_s_Gamma(tisp_core_tuning_t *core_tuning, tisp_gamma_lut_t *gammas);
++int tisp_g_Gamma(tisp_core_tuning_t *core_tuning, tisp_gamma_lut_t *gammag);
++int tisp_s_aeroi_weight(tisp_core_tuning_t *core_tuning, tisp_3a_weight_t * roi_weight);
++int tisp_g_aeroi_weight(tisp_core_tuning_t *core_tuning, tisp_3a_weight_t * roi_weight);
++int tisp_s_aezone_weight(tisp_core_tuning_t *core_tuning, tisp_3a_weight_t * zone_weight);
++int tisp_g_aezone_weight(tisp_core_tuning_t *core_tuning, tisp_3a_weight_t * zone_weight);
++int tisp_g_ev_attr(tisp_core_tuning_t *core_tuning, tisp_ev_attr_t *ev_attr);
++int tisp_g_wb_attr(tisp_core_tuning_t *core_tuning, tisp_wb_attr_t *wb_attr);
++int tisp_s_wb_frz_attr(tisp_core_tuning_t *core_tuning, unsigned char frz);
++int tisp_s_wb_attr(tisp_core_tuning_t *core_tuning, tisp_wb_attr_t wb_attr);
++int tisp_g_ae_hist(tisp_core_tuning_t *core_tuning, tisp_ae_sta_t *ae_hist);
++int tisp_s_ae_hist(tisp_core_tuning_t *core_tuning, tisp_ae_sta_t ae_hist);
++int tisp_s_3dns_ratio(tisp_core_tuning_t *core_tuning, unsigned int ratio);
++int tisp_s_ae_attr(tisp_core_tuning_t *core_tuning, tisp_ev_attr_t ae_attr);
++int tisp_s_ae_attr_ag(tisp_core_tuning_t *core_tuning, tisp_ev_attr_t ae_attr);
++int tisp_g_ae_attr(tisp_core_tuning_t *core_tuning, tisp_ev_attr_t *ae_attr);
++int tisp_s_ae_min(tisp_core_tuning_t *core_tuning, tisp_ae_ex_min_t ae_min);
++int tisp_g_ae_min(tisp_core_tuning_t *core_tuning, tisp_ae_ex_min_t *ae_min);
++int tisp_g_ae_zone(tisp_core_tuning_t *core_tuning, tisp_zone_info_t *ae_zone);
++void tisp_g_ae_luma(tisp_core_tuning_t *core_tuning, unsigned char *luma, int width, int height);
++int tisp_g_af_metric(tisp_core_tuning_t *core_tuning, unsigned int *metric);
++int tisp_g_af_attr(tisp_core_tuning_t *core_tuning, tisp_af_attr *af_info);
++int tisp_s_af_attr(tisp_core_tuning_t *core_tuning, tisp_af_attr af_info);
++int tisp_s_af_weight(tisp_core_tuning_t *core_tuning, tisp_3a_weight_t * af_weight);
++int tisp_g_af_weight(tisp_core_tuning_t *core_tuning, tisp_3a_weight_t * af_weight);
++void tisp_s_wb_frz(tisp_core_tuning_t *core_tuning, unsigned char frz);
++void tisp_g_wb_frz(tisp_core_tuning_t *core_tuning, unsigned char *frz);
++void tisp_s_module_control(tisp_core_tuning_t *core_tuning, tisp_module_control_t top);
++void tisp_g_module_control(tisp_core_tuning_t *core_tuning, tisp_module_control_t *top);
++void tisp_s_ev_start(tisp_core_tuning_t *core_tuning, unsigned int ev_start);
++void tisp_s_max_again(tisp_core_tuning_t *core_tuning, unsigned int max_again);
++void tisp_s_max_isp_dgain(tisp_core_tuning_t *core_tuning, unsigned int max_isp_dgain);
++int tisp_g_drc_strength(tisp_core_tuning_t *core_tuning, unsigned int *strength);
++int tisp_s_drc_strength(tisp_core_tuning_t *core_tuning, unsigned int strength);
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_isp.h b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_isp.h
+new file mode 100755
+index 000000000..e756bbee2
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_isp.h
+@@ -0,0 +1,104 @@
++#ifndef __TIZIANO_ISP_H__
++#define __TIZIANO_ISP_H__
++
++typedef struct {
++	unsigned int max_again;	//the format is .16
++	unsigned int max_dgain;	//the format is .16
++	unsigned int again;
++	unsigned int dgain;
++	unsigned int fps;
++	unsigned short min_integration_time;
++	unsigned short min_integration_time_native;
++	unsigned short max_integration_time_native;
++	unsigned short integration_time_limit;
++	unsigned int integration_time;
++	unsigned short total_width;
++	unsigned short total_height;
++	unsigned short max_integration_time;
++	unsigned short integration_time_apply_delay;
++	unsigned short again_apply_delay;
++	unsigned short dgain_apply_delay;
++	unsigned short one_line_expr_in_us;
++} sensor_info_t;
++
++typedef struct {
++	int width;
++	int height;
++	int bayer;
++	char sensor[16];
++	sensor_info_t sensor_info;
++} tisp_init_param_t;
++
++typedef struct {
++	int sensor_width;
++	int sensor_height;
++	unsigned int buf_ae_num;
++	unsigned int buf_ae_vaddr;
++	unsigned int buf_ae_paddr;
++	unsigned int buf_aehist_num;
++	unsigned int buf_aehist_vaddr;
++	unsigned int buf_aehist_paddr;
++	unsigned int buf_awb_num;
++	unsigned int buf_awb_vaddr;
++	unsigned int buf_awb_paddr;
++	unsigned int buf_adr_num;
++	unsigned int buf_adr_vaddr;
++	unsigned int buf_adr_paddr;
++	unsigned int buf_defog_num;
++	unsigned int buf_defog_vaddr;
++	unsigned int buf_defog_paddr;
++	unsigned int buf_af_num;
++	unsigned int buf_af_vaddr;
++	unsigned int buf_af_paddr;
++
++} tisp_info_t;
++
++
++typedef struct {
++	int scaler_en;
++	int scaler_width;
++	int scaler_height;
++	int crop_en;
++	int crop_x;
++	int crop_y;
++	int crop_width;
++	int crop_height;
++} tisp_channel_attr_t;
++
++
++
++typedef struct {
++	uint32_t tisp_wb_manual;
++	uint32_t tisp_wb_rg;
++	uint32_t tisp_wb_bg;
++	uint32_t tisp_wb_rg_sta_global;
++	uint32_t tisp_wb_bg_sta_global;
++	uint32_t tisp_wb_rg_sta_weight;
++	uint32_t tisp_wb_bg_sta_weight;
++} tisp_wb_attr_t;
++
++typedef struct {
++	int ae_hist[256];
++	int ae_hist_5bin[5];
++	int ae_hist_nodes[4];
++	int ae_hist_hv[2];
++} tisp_ae_sta_t;
++
++typedef struct {
++	unsigned int af_metrics;
++	unsigned int af_metrics_alt;
++	unsigned char af_enable;
++	unsigned char af_metrics_shift;
++	unsigned short af_delta;
++	unsigned short af_theta;
++	unsigned short af_hilight_th;
++	unsigned short af_alpha_alt;
++	unsigned char  af_hstart;
++	unsigned char  af_vstart;
++	unsigned char  af_stat_nodeh;
++	unsigned char  af_stat_nodev;
++} tisp_af_attr;
++
++//extern tisp_ae_ctrls_t tisp_ae_ctrls;
++extern tisp_init_param_t sensor_info;
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_netlink.h b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_netlink.h
+new file mode 100644
+index 000000000..06a6adf00
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_netlink.h
+@@ -0,0 +1,12 @@
++#ifndef __TIZIANO_NETLINK_H__
++#define __TIZIANO_NETLINK_H__
++#include "tiziano_core.h"
++
++int32_t netlink_send_msg(tisp_netlink_t *nl, int8_t *pbuf, uint16_t len);
++int32_t tisp_netlink_event_set_cb(tisp_netlink_t *nl, net_event_cb cb, void *cb_data);
++
++int32_t tisp_netlink_init(tisp_netlink_t *nl);
++
++void tisp_netlink_exit(tisp_netlink_t *nl);
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_priv.h b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_priv.h
+new file mode 100644
+index 000000000..abd92e6fb
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_priv.h
+@@ -0,0 +1,47 @@
++#ifndef __TIZIANO_PRIV_H__
++#define __TIZIANO_PRIV_H__
++
++
++#include <linux/slab.h>
++#include <linux/irqreturn.h>
++#include <linux/dma-mapping.h>
++#include <linux/delay.h>
++#include <linux/list.h>
++
++#include <linux/dma-direct.h>
++#include <linux/dma-map-ops.h>
++#include <linux/highmem.h>
++
++#include <asm/cache.h>
++#include <asm/cpu-type.h>
++#include <asm/dma-coherence.h>
++#include <asm/io.h>
++
++#include <stdbool.h>
++
++void *isp_kmalloc(size_t size, gfp_t flags);
++void isp_kfree(void *objp);
++
++void isp_spin_lock_init(spinlock_t *lock);
++void _isp_spin_lock_irqsave(spinlock_t *lock, unsigned long *flags);
++#define isp_spin_lock_irqsave(lock, flags) \
++	_isp_spin_lock_irqsave(lock, (&flags));
++void isp_spin_unlock_irqrestore(spinlock_t *lock, unsigned long flags);
++
++#define ISP_DMA_BIDIRECTIONAL DMA_BIDIRECTIONAL
++void isp_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
++			 enum dma_data_direction direction);
++
++void ISP_INIT_LIST_HEAD(struct list_head *list);
++void isp_list_add_tail(struct list_head *new, struct list_head *head);
++#define isp_list_first_entry(ptr, type, member) list_first_entry(ptr, type, member)
++void isp_list_del(struct list_head *entry);
++int isp_list_empty(const struct list_head *head);
++
++void isp_complete(struct completion *);
++unsigned long isp_wait_for_completion_timeout(struct completion *x, unsigned long timeout);
++void isp_init_completion(struct completion *x);
++
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_sys.h b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_sys.h
+new file mode 100644
+index 000000000..8abaeafb0
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/inc/tiziano_sys.h
+@@ -0,0 +1,10 @@
++#ifndef __TIZIANO_SYS_H__
++#define __TIZIANO_SYS_H__
++
++extern int system_reg_write(void *hdl, unsigned int reg, unsigned int value);
++extern unsigned int  system_reg_read(void *hdl, unsigned int reg);
++extern int system_lock(void *hdl);
++extern int system_unlock(void *hdl);
++extern int system_irq_func_set(void *hdl, int irq, void *func, void *data);
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-core/src/Makefile b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/src/Makefile
+new file mode 100644
+index 000000000..e3c2e981f
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/src/Makefile
+@@ -0,0 +1,2 @@
++obj-y +=	isp-core.a
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-core/tiziano_netlink.c b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/tiziano_netlink.c
+new file mode 100644
+index 000000000..eaee433df
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/tiziano_netlink.c
+@@ -0,0 +1,125 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/timer.h>
++#include <linux/time.h>
++#include <linux/types.h>
++#include <net/sock.h>
++#include <net/netlink.h>
++#include "inc/tiziano_netlink.h"
++
++#define NETLINK_USER	22
++#define USER_MSG		(NETLINK_USER + 1)
++#define USER_PORT		50
++
++#if 0
++static struct sock *nlsk = NULL;
++#endif
++struct nl_sock_map {
++	tisp_netlink_t *nl;
++	struct sock *nlsk;
++};
++
++#define MAX_NL_SK	2
++struct nl_sock_map nl_sock_map[MAX_NL_SK] = {NULL};
++
++static tisp_netlink_t * sock_to_nl(struct sock *sk)
++{
++	int i = 0;
++	for(i = 0; i < MAX_NL_SK; i++) {
++		if(nl_sock_map[i].nlsk == sk) {
++			return nl_sock_map[i].nl;
++		}
++	}
++
++	return NULL;
++}
++
++//net_event_cb net_event_process = NULL;
++
++int32_t netlink_send_msg(tisp_netlink_t *nl, int8_t *pbuf, uint16_t len)
++{
++	int32_t ret;
++	struct sk_buff *nl_skb;
++	struct nlmsghdr *nlh;
++	nl_skb = nlmsg_new(len, GFP_ATOMIC);
++	if (!nl_skb) {
++		pr_err("%s,%d: netlink_alloc_skb error\n", __func__, __LINE__);
++		return -1;
++	}
++	nlh = nlmsg_put(nl_skb, 0, 0, USER_MSG, len, 0);
++	if (nlh == NULL) {
++		pr_err("%s,%d: nlmsg_put() error\n", __func__, __LINE__);
++		nlmsg_free(nl_skb);
++		return -1;
++	}
++	memcpy(nlmsg_data(nlh), pbuf, len);
++	ret = netlink_unicast(nl->nlsk, nl_skb, USER_PORT, MSG_DONTWAIT);
++	return ret;
++}
++
++static void netlink_rcv_msg(struct sk_buff *skb)
++{
++	struct nlmsghdr *nlh = NULL;
++	struct sock *sock = skb->sk;
++	tisp_netlink_t * nl = sock_to_nl(sock);
++	void *data = NULL;
++
++	if (skb->len >= nlmsg_total_size(0)) {
++		nlh = nlmsg_hdr(skb);
++		data = NLMSG_DATA(nlh);
++		if (data) {
++			if (NULL != nl->net_event_process) {
++				nl->net_event_process(nl->cb_data, data, nlmsg_len(nlh));
++			}
++			//netlink_send_msg(data, nlmsg_len(nlh));
++		}
++	}
++}
++
++struct netlink_kernel_cfg nlcfg = {
++	.input  = netlink_rcv_msg,
++};
++
++int32_t tisp_netlink_event_set_cb(tisp_netlink_t *nl, net_event_cb cb, void *cb_data)
++{
++	nl->net_event_process = cb;
++	nl->cb_data = cb_data;
++	return 0;
++}
++
++int32_t tisp_netlink_init(tisp_netlink_t *nl)
++{
++//	pr_err("%s,%d: \n", __func__, __LINE__);
++	int i;
++	nl->nlsk = (struct sock *)netlink_kernel_create(&init_net, USER_MSG, &nlcfg);
++	if (!nl->nlsk) {
++		pr_err("%s,%d: create netlink socket error.\n", __func__, __LINE__);
++		return -1;
++	}
++
++	for(i = 0; i < MAX_NL_SK; i++) {
++		if(nl_sock_map[i].nl == NULL || nl_sock_map[i].nlsk == NULL) {
++			nl_sock_map[i].nl = nl;
++			nl_sock_map[i].nlsk = nl->nlsk;
++		}
++	}
++//	pr_err("%s,%d: \n", __func__, __LINE__);
++	return 0;
++}
++
++void tisp_netlink_exit(tisp_netlink_t *nl)
++{
++	int i;
++
++	if (nl->nlsk != NULL && nl->nlsk->sk_socket != NULL) {
++		sock_release(nl->nlsk->sk_socket);
++	}
++
++	for(i = 0; i < MAX_NL_SK; i++) {
++		if(nl_sock_map[i].nl == nl) {
++			nl_sock_map[i].nl = NULL;
++			nl_sock_map[i].nlsk = NULL;
++		}
++	}
++
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-core/tiziano_priv.c b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/tiziano_priv.c
+new file mode 100644
+index 000000000..6fe89ab66
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-core/tiziano_priv.c
+@@ -0,0 +1,56 @@
++#include "inc/tiziano_priv.h"
++
++void *isp_kmalloc(size_t size, gfp_t flags){
++	return kmalloc(size, flags);
++}
++
++void isp_kfree(void *objp){
++	kfree(objp);
++}
++
++void isp_spin_lock_init(spinlock_t *lock){
++	spin_lock_init(lock);
++}
++
++void _isp_spin_lock_irqsave(spinlock_t *lock, unsigned long *flags){
++	spin_lock_irqsave(lock, *flags);
++}
++
++void isp_spin_unlock_irqrestore(spinlock_t *lock, unsigned long flags){
++	spin_unlock_irqrestore(lock, flags);
++}
++
++void isp_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
++			 enum dma_data_direction direction)
++{
++	arch_sync_dma_for_device(virt_to_phys(vaddr),size,direction);
++}
++
++
++void ISP_INIT_LIST_HEAD(struct list_head *list){
++	INIT_LIST_HEAD(list);
++}
++
++void isp_list_add_tail(struct list_head *new, struct list_head *head){
++	list_add_tail(new, head);
++}
++
++void isp_list_del(struct list_head *entry){
++	list_del(entry);
++}
++
++int isp_list_empty(const struct list_head *head){
++	return list_empty(head);
++}
++
++void isp_complete(struct completion *com){
++	complete(com);
++}
++
++unsigned long isp_wait_for_completion_timeout(struct completion *x, unsigned long timeout){
++	return wait_for_completion_timeout(x, timeout);
++}
++
++void isp_init_completion(struct completion *x){
++	init_completion(x);
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-drv.c b/module_drivers/drivers/media/platform/ingenic-isp/isp-drv.c
+new file mode 100644
+index 000000000..b79ed2f9b
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-drv.c
+@@ -0,0 +1,451 @@
++#include <linux/clk.h>
++#include <linux/media-bus-format.h>
++#include <linux/media.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_graph.h>
++#include <linux/of_platform.h>
++#include <linux/of_reserved_mem.h>
++#include <linux/pm_runtime.h>
++#include <linux/pm_domain.h>
++#include <linux/slab.h>
++#include <linux/videodev2.h>
++#include <linux/component.h>
++
++#include <media/media-device.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-fwnode.h>
++
++#include "isp-drv.h"
++
++
++static const struct of_device_id ingenic_isp_dt_match[];
++
++static int ingenic_isp_parse_dt(struct ispcam_device * ispcam)
++{
++	struct device *dev = ispcam->dev;
++	struct device_node *node = NULL;
++	struct v4l2_async_notifier *notifier = &ispcam->notifier;
++	struct platform_device *pdev = NULL;
++	struct v4l2_async_subdev *asd = NULL;
++	const char *compatible = NULL;
++	unsigned int cplen = 0;
++	int ret = 0;
++
++
++	for_each_child_of_node(dev->of_node, node) {
++		compatible = of_get_property(node, "compatible", &cplen);
++
++		if(!compatible && (cplen == 0)) {
++			continue;
++		}
++		if(!of_device_is_available(node)) {
++			continue;
++		}
++		pdev = of_platform_device_create(node, NULL,dev);
++		if(!pdev) {
++			printk("failed to populate_platform_device, node->full_name");
++		}
++
++		ispcam->subdevs[ispcam->subdev_num++] = pdev;
++		if(ispcam->subdev_num > MAX_SUB_DEVS) {
++			printk("too many sub platform devices!\n");
++			return -EINVAL;
++		}
++	}
++
++
++	printk("start parse remote-endpoint!\n");
++	asd = devm_kzalloc(dev, MAX_ASYNC_SUBDEVS * sizeof(*notifier->sd->asd), GFP_KERNEL);
++
++	/* 解�endpoint, 远程端点，建立关系, 在下�注册回调，等注册完�通知.创建video_device.*/
++
++	while((node = of_graph_get_next_endpoint(dev->of_node, node))) {
++
++		/*TODO: 构建与vep对应的数�结构，存储从dts中传入的数�.*/
++		ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(node), &ispcam->vep[ispcam->asd_num]);
++		if(ret < 0) {
++			of_node_put(node);
++			return -EINVAL;
++		}
++		ispcam->isd[ispcam->asd_num].bus_type = ispcam->vep[ispcam->asd_num].bus_type;
++		ispcam->isd[ispcam->asd_num].parallel = ispcam->vep[ispcam->asd_num].bus.parallel;
++		ispcam->isd[ispcam->asd_num].mipi_csi2 = ispcam->vep[ispcam->asd_num].bus.mipi_csi2;
++
++
++		asd->match.fwnode = fwnode_graph_get_remote_port_parent(of_fwnode_handle(node));
++		asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
++
++		of_node_put(node);
++
++
++
++		v4l2_async_notifier_init(&ispcam->notifier);
++
++		ret = v4l2_async_notifier_add_subdev(&ispcam->notifier, asd);
++		if (ret) {
++			fwnode_handle_put(asd->match.fwnode);
++			return ret;
++		}
++
++
++		ispcam->asd_num ++;
++	}
++
++#if 0
++
++	printk("dump subdevs ------------ pdevs:\n");
++	int i;
++	for(i = 0; i < ispcam->subdev_num; i++) {
++		printk("---sudev: %d, name: %s\n", i, ispcam->subdevs[i]->name);
++	}
++
++	printk("dump async subdevs!\n");
++	/*dump of parse subdevs.*/
++	for(i = 0; i < ispcam->asd_num; i++) {
++		asd = &ispcam->isd[i].asd;
++		printk("asd: %d, asd->match.of.node->full_name: %s\n", i, asd->match.fwnode->dev->of_node->full_name);
++	}
++
++#endif
++	return ret;
++}
++
++static int ispcam_asd_notifier_bound(struct v4l2_async_notifier *async,
++                                     struct v4l2_subdev *subdev,
++                                     struct v4l2_async_subdev *asd)
++{
++        struct ispcam_device *ispcam = container_of(async, struct ispcam_device,
++                                              notifier);
++	struct isp_async_device *isd = &ispcam->isd[0];
++
++	struct media_entity *entity = &subdev->entity; /*SOURCE_PAD*/
++	int i = 0;
++	int ret = 0;
++
++	if(entity->num_pads == 0) {
++		dev_err(ispcam->dev, "%s, %d No pad found in async entity(%s)\n", __func__, __LINE__, subdev->name);
++		return -EINVAL;
++	}
++
++	for(i = 0; i < entity->num_pads; i++) {
++		if(entity->pads[i].flags & MEDIA_PAD_FL_SOURCE)
++			break;
++	}
++
++
++	if(i == entity->num_pads) {
++		dev_err(ispcam->dev, "%s, %d, no source pad in async entity (%s)\n", __func__, __LINE__, subdev->name);
++		return -EINVAL;
++	}
++
++	isd->source_pad = i;
++
++	isd->sd = subdev;
++	/*TODO: pass common args from isp host to sensor driver.*/
++	isd->sd->host_priv = NULL;
++
++
++	ret = sensor_device_probe(&ispcam->sensor, ispcam);
++	if(ret < 0) {
++		/*TODO*/
++	}
++
++	dev_info(ispcam->dev, "%s, %d\n", __func__, __LINE__);
++
++	return 0;
++}
++
++static int ispcam_asd_notifier_complete(struct v4l2_async_notifier *async)
++{
++        struct ispcam_device *ispcam = container_of(async, struct ispcam_device,
++                                              notifier);
++
++	int ret = 0;
++	struct media_entity *input = NULL;		/*SINK PAD*/
++	unsigned int flags = 0;
++	unsigned int pad = 0;
++	struct isp_async_device *isd = &ispcam->isd[0];
++
++	dev_info(ispcam->dev, "%s, %d\n", __func__, __LINE__);
++	/*1. 绑定所有的�component,确�所有的�的硬件设备在线, �设备会在里�进行subdev的�始化和注册等�作.*/
++	ret = component_bind_all(ispcam->dev, ispcam);
++	if(ret < 0) {
++		goto err_component_bind_all;
++	}
++
++	/*CSI	<->	VIC*/
++
++	/*VIC	<->	ISP*/
++	//printk("creating link vic to isp\n");
++	ret = media_create_pad_link(
++			&ispcam->vic->sd.entity, VIC_PAD_SOURCE,
++			&ispcam->isp->sd.entity, ISP_PAD_SINK, MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
++
++#ifdef CONFIG_VIC_DMA_ROUTE
++	/*VIC <-> Memory*/
++	ret = media_create_pad_link(
++			&ispcam->vic->sd.entity, VIC_PAD_SOURCE,
++			&ispcam->vic->ispvideo.video.entity, ISP_VIDEO_PAD_SINK, MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
++#endif
++
++	/*ISP	<->	MSCALER*/
++	//printk("creating link isp to mscaler\n");
++	ret = media_create_pad_link(
++			&ispcam->isp->sd.entity, ISP_PAD_SOURCE,
++			&ispcam->mscaler->sd.entity, MSCALER_PAD_SINK, MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
++
++	/*Sensor -> 0]CSI[1 -> 0]VIC[1 -> 0]ISP[1 -> 0]Mscaler[1 -> ]Memory*/
++	//printk("creating link from mscaler to isp-video\n");
++	ret = media_create_pad_link(
++			&ispcam->mscaler->sd.entity, MSCALER_PAD_SOURCE_CH0,
++			&ispcam->mscaler->ispvideo[0].video.entity, ISP_VIDEO_PAD_SINK, MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
++
++	if(MSCALER_MAX_CH > 1) {
++		/*CH1*/
++		ret = media_create_pad_link(
++				&ispcam->mscaler->sd.entity, MSCALER_PAD_SOURCE_CH1,
++				&ispcam->mscaler->ispvideo[1].video.entity, ISP_VIDEO_PAD_SINK, MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
++	}
++	/*CH2*/
++	if(MSCALER_MAX_CH > 2) {
++		ret = media_create_pad_link(
++				&ispcam->mscaler->sd.entity, MSCALER_PAD_SOURCE_CH2,
++				&ispcam->mscaler->ispvideo[2].video.entity, ISP_VIDEO_PAD_SINK, MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
++	}
++	if(isd->bus_type == V4L2_MBUS_CSI2_DPHY) {
++		dev_info(ispcam->dev, "creating link csi to vic\n");
++		if(!ispcam->csi) {
++			dev_err(ispcam->dev, "*** Error: MIPI Sensor Found while CSI not enabled in dts ***\n");
++			return -EINVAL;
++		}
++		/*1. connect csi to vic.*/
++		ret = media_create_pad_link(
++				&ispcam->csi->sd.entity, CSI_PAD_SOURCE,
++				&ispcam->vic->sd.entity, VIC_PAD_SINK, MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
++		/*connect to csi pad*/
++		input = &ispcam->csi->sd.entity;
++		flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
++		pad = CSI_PAD_SINK;
++	} else if(isd->bus_type == V4L2_MBUS_PARALLEL) {
++		dev_info(ispcam->dev, "creating link dvp to vic.\n");
++		/*connect to vic dvp port.*/
++		input = &ispcam->vic->sd.entity;
++		pad =	VIC_PAD_SINK;
++		flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
++
++	} else {
++		dev_err(ispcam->dev, "Unsupported v4l2 mbus type.\n");
++		return -EINVAL;
++	}
++	/* connect sensor to csi or vic. */
++	ret = media_create_pad_link(&isd->sd->entity, isd->source_pad,
++			input, pad, MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
++	if(ret < 0) {
++		dev_err(ispcam->dev, "%s, %d, failed to create link from [%s] to [%s]\n",
++				__func__, __LINE__, isd->sd->entity.name, input->name);
++		return -EINVAL;
++	}
++
++	/* Expose all subdev's nodes*/
++	ret = v4l2_device_register_subdev_nodes(&ispcam->v4l2_dev);
++	if (ret) {
++		dev_err(ispcam->mdev.dev,
++				"vimc subdev nodes registration failed (err=%d)\n",
++				ret);
++		goto err_register_subdev_nodes;
++	}
++
++	return 0;
++err_register_subdev_nodes:
++err_component_bind_all:
++	return ret;
++}
++
++
++
++static int ispcam_comp_bind(struct device *master)
++{
++        struct ispcam_device *ispcam = platform_get_drvdata(to_platform_device(master));
++	int ret = 0;
++	struct v4l2_async_notifier_operations ops = {
++		.bound = ispcam_asd_notifier_bound,
++		.complete = ispcam_asd_notifier_complete,
++	};
++	dev_info(master, "master component bind.!\n");
++	media_device_init(&ispcam->mdev);
++
++	/* Register the v4l2 struct */
++	ret = v4l2_device_register(ispcam->mdev.dev, &ispcam->v4l2_dev);
++	if (ret) {
++		dev_err(ispcam->mdev.dev,
++				"v4l2 device register failed (err=%d)\n", ret);
++		return ret;
++	}
++
++	ret = media_device_register(&ispcam->mdev);
++	if(ret < 0) {
++		dev_err(ispcam->mdev.dev, "media device register failed\n");
++		goto err_media_device_register;
++	}
++
++
++
++
++	/*3. 注册异步设备完�通知,确�所有的sensor在线.在完�通知里�进行media_device和link的创建.*/
++
++	ispcam->notifier.ops = &ops;
++	ret = v4l2_async_notifier_register(&ispcam->v4l2_dev, &ispcam->notifier);
++	if(ret < 0) {
++		goto err_v4l2_async_notifier_register;
++	}
++
++
++	return 0;
++err_v4l2_async_notifier_register:
++err_media_device_register:
++	return ret;
++}
++
++static void ispcam_comp_unbind(struct device *master)
++{
++        struct ispcam_device *ispcam = platform_get_drvdata(to_platform_device(master));
++
++        dev_info(master, "TODO: %p master component unbind!\n", ispcam);
++
++}
++
++
++static const struct component_master_ops ispcam_comp_ops = {
++        .bind = ispcam_comp_bind,
++        .unbind = ispcam_comp_unbind,
++};
++
++
++static int comp_compare(struct device *comp, void *data)
++{
++	return comp == data;
++}
++
++static int ingenic_isp_probe(struct platform_device *pdev)
++{
++
++	struct ispcam_device *ispcam = NULL;
++	struct component_match *match = NULL;
++	const struct of_device_id *of_match;
++	struct ispcam_data *data = NULL;
++	int ret;
++	int i;
++	char *dev_nr = NULL;
++
++	ispcam = kzalloc(sizeof(struct ispcam_device), GFP_KERNEL);
++	if(!ispcam) {
++		pr_err("Failed to alloc ispcam dev [%s]\n", pdev->name);
++		return -ENOMEM;
++	}
++
++	ispcam->dev = &pdev->dev;
++	platform_set_drvdata(pdev, ispcam);
++
++	of_match = of_match_node(ingenic_isp_dt_match, pdev->dev.of_node);
++	if (!of_match){
++		return -ENODEV;
++	}
++
++	data = (struct ispcam_data *)of_match->data;
++	if(data->chip_name)
++		memcpy(ispcam->chip_name, data->chip_name, sizeof(ispcam->chip_name));
++	else
++		return -ENODEV;
++
++	ingenic_isp_parse_dt(ispcam);
++
++	for(i = 0; i < ispcam->subdev_num; i++) {
++		component_match_add(ispcam->dev, &match, comp_compare, &ispcam->subdevs[i]->dev);
++	}
++
++
++	mutex_init(&ispcam->mutex);
++	ispcam->v4l2_dev.mdev = &ispcam->mdev;
++
++	ispcam->mdev.dev = ispcam->dev;
++	strlcpy(ispcam->mdev.model, "ingenic-isp", sizeof(ispcam->mdev.model));
++
++	dev_nr = strchr(pdev->name, '@');
++	if(!dev_nr){
++		dev_err(ispcam->dev, "failed to get dev_nr\n");
++		return -ENODEV;
++	}
++	ispcam->dev_nr = dev_nr[1]-'0';
++
++	/* add self to component */
++	ret = component_master_add_with_match(ispcam->dev, &ispcam_comp_ops, match);
++	if(ret < 0) {
++		dev_err(ispcam->dev, "failed to add component master\n");
++		/*TODO*/
++	}
++
++	ret = of_reserved_mem_device_init(ispcam->dev);
++	if(ret)
++		dev_warn(ispcam->dev, "failed to init reserved mem\n");
++
++	return 0;
++
++
++	return ret;
++}
++
++
++
++static int ingenic_isp_remove(struct platform_device *pdev)
++{
++
++	return 0;
++}
++
++struct ispcam_data ingenic_x2000_camera_data = {
++	.chip_name = "x2000",
++};
++
++struct ispcam_data ingenic_m300_camera_data = {
++	.chip_name = "m300",
++};
++
++static const struct of_device_id ingenic_isp_dt_match[] = {
++        { .compatible = "ingenic,x2000-isp-camera", .data = (void *)&ingenic_x2000_camera_data},
++        { .compatible = "ingenic,m300-isp-camera", .data = (void *)&ingenic_m300_camera_data},
++        { }
++};
++
++MODULE_DEVICE_TABLE(of, ingenic_isp_dt_match);
++
++static int __maybe_unused ingenic_isp_drv_suspend(struct platform_device *pdev, pm_message_t state)
++{
++        return 0;
++}
++
++static int __maybe_unused ingenic_isp_drv_resume(struct platform_device *pdev)
++{
++        return 0;
++}
++
++static struct platform_driver ingenic_isp_driver = {
++        .probe = ingenic_isp_probe,
++        .remove = ingenic_isp_remove,
++	.suspend = ingenic_isp_drv_suspend,
++	.resume = ingenic_isp_drv_resume,
++        .driver = {
++                .name = "ingenic-ispdrv",
++                .of_match_table = ingenic_isp_dt_match,
++        },
++};
++
++module_platform_driver(ingenic_isp_driver);
++
++MODULE_ALIAS("platform:ingenic-ispdrv");
++MODULE_DESCRIPTION("ingenic isp subsystem");
++MODULE_AUTHOR("qipengzhen <aric.pzqi@ingenic.com>");
++MODULE_LICENSE("GPL v2");
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-drv.h b/module_drivers/drivers/media/platform/ingenic-isp/isp-drv.h
+new file mode 100644
+index 000000000..3b2451ba7
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-drv.h
+@@ -0,0 +1,415 @@
++#ifndef __INGENIC_ISP_DRV_H__
++#define __INGENIC_ISP_DRV_H__
++
++#include <linux/clk.h>
++
++#include <media/media-device.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-fwnode.h>
++#include <media/videobuf2-core.h>
++#include <media/videobuf2-v4l2.h>
++
++
++#include "tiziano_core.h"
++#include "isp-sensor.h"
++
++
++#define 	MAX_SUB_DEVS		5
++#define 	MAX_ASYNC_SUBDEVS	1	/*�个ISP�时最大支�1个sensor.*/
++#define 	MSCALER_MAX_CH		3
++
++
++struct isp_video_format {
++	const char *name;
++	unsigned int fourcc;
++	unsigned int depth[3];	/*max 3 plane*/
++	unsigned int mbus_code;
++	unsigned int num_planes;
++	enum v4l2_colorspace colorspace;
++};
++
++struct isp_pipeline {
++	struct media_pipeline pipeline;
++};
++
++
++#define to_isp_buffer(buf)      container_of(buf, struct isp_video_buffer, vb2)
++struct isp_video_buffer {
++	struct vb2_v4l2_buffer vb2;
++	struct list_head list_entry;
++	unsigned int uv_offset;	/* 当使用single plane的buffer时,表明uv的�移大�.*/
++	int uv_value_filled;
++	unsigned int uv_value_backup[MSCALER_MAX_CH];
++};
++
++/*�个mscaler_video_device代表一个数�节点示例, mscaler有三个channel，所有三个video_device.*/
++/*通用video_device， mscaler 的三个channel�以注册, vic也�以注册，所以通称为isp_video_device.*/
++#define ISP_VIDEO_PAD_SINK	0
++#define ISP_VIDEO_NUM_PADS	1
++struct isp_video_device {
++	char *name;
++
++	struct video_device video;
++	struct device *dev;
++
++	struct media_pad pad;
++
++	struct ispcam_device *ispcam;
++
++	void *alloc_ctx;
++	struct vb2_queue *queue;
++	struct mutex queue_lock;
++
++	struct mutex mutex;
++
++	struct mutex stream_lock;
++	struct isp_pipeline pipe;
++
++
++	struct v4l2_format format;
++	struct isp_video_format *(*find_format)(const u32 *pixelformat, const u32 *mbus_code, int index);
++	const struct isp_video_ops *ops;
++
++	int bypass;	/*bypass isp.*/
++	unsigned int max_buffer_num;	/*max vb2 num*/
++};
++
++struct isp_video_ops {
++	/**/
++	struct isp_video_format *(*find_format)(const u32 *pixelformat, const u32 *mbus_code, int index);
++
++	/*qbuf*/
++	/*called by VIDIOC_QBUF in isp-video.c*/
++	int (*qbuf)(struct isp_video_device *ispvideo, struct isp_video_buffer *isp_buffer);
++};
++
++/* isp-core-tuning*/
++struct isp_core_tuning_ctrl {
++	tisp_wb_attr_t wb_attr;
++	unsigned int luma;
++
++	unsigned int hflip;
++	unsigned int vflip;
++	unsigned int sat;
++	unsigned int bright;
++	unsigned int contrast;
++	unsigned int sharp;
++	unsigned int exp_auto;
++	unsigned int exp_abs;
++	unsigned int auto_gain;
++	unsigned int gain;
++	unsigned int hill;
++	unsigned int flicker;
++	unsigned int module;
++	TISP_MODE_DN_E daynight;
++	unsigned int wb;
++	unsigned int auto_wb;
++	unsigned int red_wb;
++	unsigned int blue_wb;
++
++
++	char hflip_pending;
++	char vflip_pending;
++	char sat_pending;
++	char bright_pending;
++	char contrast_pending;
++	char sharp_pending;
++	char exp_auto_pending;
++	char exp_abs_pending;
++	char auto_gain_pending;
++	char gain_pending;
++	char hill_pending;
++	char flicker_pending;
++	char module_pending;
++	char daynight_pending;
++	char wb_pending;
++	char auto_wb_pending;
++	char red_wb_pending;
++	char blue_wb_pending;
++	char do_wb_pending;
++};
++
++enum isp_image_tuning_private_cmd_id {
++	IMAGE_TUNING_CID_MODULE_CONTROL = V4L2_CID_PRIVATE_BASE,
++	IMAGE_TUNING_CID_DAY_OR_NIGHT,
++	IMAGE_TUNING_CID_AE_LUMA,
++	IMAGE_TUNING_CID_HILIGHTDEPRESS,
++};
++
++#define CSI_PAD_SINK	0
++#define CSI_PAD_SOURCE	1
++#define CSI_NUM_PADS	2
++struct csi_device {
++	struct device *dev;
++	int irq;
++	void __iomem *iobase;
++	unsigned int phy_base;
++	struct ispcam_device *ispcam;	/*struct ispcam_device*/
++
++	struct v4l2_subdev sd;
++
++	struct media_pad *pads;
++
++	struct clk *gate_clk;
++
++	int reset_index;
++	int enabled;
++
++	int clk_precounter;
++	int data_precounter;
++};
++
++
++#define	VIC_PAD_SINK		0
++#define VIC_PAD_SOURCE		1
++#define	VIC_NUM_PADS		2
++struct vic_device {
++	struct device *dev;
++
++	int irq;
++	void __iomem *iobase;
++	struct ispcam_device *ispcam;	/*struct ispcam_device*/
++
++	struct v4l2_subdev sd;
++
++	struct media_pad *pads;
++	struct isp_video_device ispvideo;	/*VIC support video out*/
++	struct v4l2_subdev_format formats[VIC_NUM_PADS];
++
++	unsigned int active_sink_pad;
++
++	struct list_head dma_queued_list;
++	spinlock_t lock;
++	int enabled;
++
++	unsigned int buffer_index;
++	int buffer_count;
++	int stop_flag;
++	int global_reset;
++	int frame_capture_counter;
++
++	unsigned int framenum;
++
++	unsigned int snap_paddr;
++	void* snap_vaddr;
++	struct completion snap_comp;
++	struct sensor_info *sensor_info;
++};
++
++#define ISP_PAD_SINK	0
++#define ISP_PAD_SOURCE	1
++#define ISP_NUM_PADS	2
++struct isp_device {
++	struct device *dev;
++	int irq;
++	void __iomem *iobase;
++	struct ispcam_device *ispcam;
++
++	void __iomem *cpm_reset;
++	unsigned int bit_sr;
++	unsigned int bit_stp;
++	unsigned int bit_ack;
++
++	struct v4l2_subdev sd;
++
++	struct media_pad *pads;
++	struct v4l2_subdev_format formats[ISP_NUM_PADS];
++
++	struct clk *div_clk;
++	struct clk *gate_clk;
++	struct clk *power_clk;
++
++	struct task_struct *process_thread;
++	tisp_core_t core;
++	int enabled;
++
++	/* IRQ callbacks.*/
++	int (*irq_func_cb[32])(void*);
++	void *irq_func_data[32];
++
++	struct isp_core_tuning_ctrl ctrls;
++	struct sensor_info *sensor_info;
++	int core_inited;
++};
++
++
++#ifdef CONFIG_MSCA_BDEV
++struct mscaler_backend_device {
++	struct device *dev;
++	struct list_head processing_list;
++	spinlock_t lock;
++	wait_queue_head_t wq;
++
++	struct task_struct *process_thread;
++
++	/* mscaler output fmt. */
++	unsigned int width;
++	unsigned int height;
++	unsigned int fmt;
++	unsigned int ch;	/*which channel this backend device belongs to.*/
++
++	int activated;	/* is bdev activated??*/
++
++	struct ingenic_venc_ctx *ctx;
++};
++#endif
++
++struct yonly_ctrl_filled {
++	unsigned int uv_value;
++	unsigned int yonly_enable;
++};
++
++/*MSCALER最大支�3个ch输出，�个ch支���的缩放等级. 这里�使用1个channel.*/
++#define MSCALER_MAX_CH			3
++#define MSCALER_PAD_SINK		0
++#define MSCALER_PAD_SOURCE_CH0		1
++#define MSCALER_PAD_SOURCE_CH1		2
++#define MSCALER_PAD_SOURCE_CH2		3
++#define MSCALER_NUM_PADS		4
++struct mscaler_device {
++	struct device *dev;
++	int irq;
++	void __iomem *iobase;
++	struct ispcam_device *ispcam;
++
++	struct v4l2_subdev sd;
++	struct media_pad *pads;
++
++	struct list_head dma_queued_list[MSCALER_MAX_CH];
++	struct list_head dma_pending_list[MSCALER_MAX_CH];
++
++	struct isp_video_device ispvideo[MSCALER_MAX_CH];
++	/*包�了输入pad和输出pad的format*/
++	struct v4l2_subdev_format formats[MSCALER_NUM_PADS];
++	struct v4l2_subdev_selection sel[MSCALER_MAX_CH];
++
++	spinlock_t lock;
++
++	unsigned int state[MSCALER_MAX_CH];	/*0: stopped, 1: streaming*/
++	unsigned int framenum[MSCALER_MAX_CH];
++
++	struct kobject *mask_kobj;
++	struct kobject *mask_ch_kobj[MSCALER_MAX_CH];
++	struct kobject *yonly_kobj;
++	struct kobject *yonly_ch_kobj[MSCALER_MAX_CH];
++	struct yonly_ctrl_filled  yonly_cf[MSCALER_MAX_CH];
++
++#ifdef CONFIG_MSCA_BDEV
++	struct mscaler_backend_device bdev[MSCALER_MAX_CH];
++#endif
++};
++
++
++/* �个 isp_async_device 代表一个异步注册的 sensor设备. */
++struct isp_async_device {
++	struct v4l2_subdev *sd;
++	struct v4l2_async_subdev asd;
++	int index;
++
++	enum v4l2_mbus_type bus_type;
++	struct v4l2_fwnode_bus_parallel parallel;
++	struct v4l2_fwnode_bus_mipi_csi2 mipi_csi2;
++
++	int enabled;
++
++	unsigned int	source_pad;
++};
++
++struct sensor_device {
++	struct isp_async_device *isd;
++
++	struct ispcam_device *ispcam;
++	struct isp_device *isp;
++
++};
++
++
++
++
++#define to_isp_video_ctx(fh)  container_of(fh, struct isp_video_ctx, fh)
++
++/*every open create one ctx, should only one ctx is running at a time*/
++struct isp_video_ctx {
++	struct isp_video_device *ispvideo;
++
++	struct v4l2_fh	fh;	/*handle*/
++	struct vb2_queue queue;
++	struct v4l2_format format;
++	unsigned int uv_offset;
++	unsigned int payload_size;
++};
++
++#define SUBDEV_PAD_SINK		0
++#define SUBDEV_PAD_SOURCE	1
++#define SUBDEV_NUM_PADS		2
++
++
++struct ispcam_data {
++	char chip_name[32];
++};
++
++struct ispcam_device {
++	struct device *dev;
++	struct platform_device *subdevs[MAX_SUB_DEVS];
++	unsigned int subdev_num;
++	char chip_name[32];
++	int dev_nr;
++
++	struct media_device mdev;
++	struct v4l2_device v4l2_dev;
++	struct v4l2_async_notifier notifier;	/*异步通知，用�接收sensor注册完�信�.*/
++
++	/*TODO: 应该�会支�一个sensor, MAX_ASYNC_SUBDEVS 应该为1*/
++	struct isp_async_device	isd[MAX_ASYNC_SUBDEVS];
++	//struct v4l2_async_subdev asd[MAX_ASYNC_SUBDEVS];
++	unsigned int asd_num;		/*实际的async device个数，从endpoint中解�出�的.*/
++	struct v4l2_fwnode_endpoint	vep[MAX_ASYNC_SUBDEVS];	/*�个异步设备对应到一个端点上.*/
++
++	int enabled;
++
++	struct mutex	mutex;
++	struct isp_device 	*isp;
++	struct csi_device 	*csi;
++	struct vic_device 	*vic;
++	struct mscaler_device 	*mscaler;
++	struct sensor_device 	sensor;
++
++};
++
++
++/* isp-video*/
++extern int isp_video_init(struct isp_video_device *ispvideo, char *name, const struct isp_video_ops *ops);
++
++extern int isp_video_cleanup(struct isp_video_device *ispvideo);
++
++extern int isp_video_register(struct isp_video_device *ispvideo, struct v4l2_device *v4l2_dev, int nr);
++
++extern int isp_video_unregister(struct isp_video_device *ispvideo);
++
++static inline struct v4l2_fwnode_bus_parallel *ispcam_get_bus_parallel(struct ispcam_device *ispcam)
++{
++	return &ispcam->isd[0].parallel;
++}
++
++static inline struct v4l2_fwnode_bus_mipi_csi2 *ispcam_get_bus_mipi_csi2(struct ispcam_device *ispcam)
++{
++	return &ispcam->isd[0].mipi_csi2;
++}
++
++/* sensor */
++int sensor_device_probe(struct sensor_device *sensor, struct ispcam_device *ispcam);
++/* tuning */
++int isp_core_tuning_param_sync(tisp_core_t *core);
++
++#ifdef CONFIG_MSCA_BDEV
++/* mscaler backend */
++int ms_bdev_init(struct mscaler_backend_device *ms_bdev);
++
++int ms_bdev_deinit(struct mscaler_backend_device *ms_bdev);
++
++int ms_bdev_qbuf(struct mscaler_backend_device *ms_bdev, struct isp_video_buffer *isp_buffer);
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-regs.h b/module_drivers/drivers/media/platform/ingenic-isp/isp-regs.h
+new file mode 100755
+index 000000000..d86106afa
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-regs.h
+@@ -0,0 +1,1450 @@
++#ifndef TIZIANO_MAP__H
++#define TIZIANO_MAP__H
++#ifndef TIZIANO_BASE
++#define TIZIANO_BASE  0x0
++#endif
++#ifndef TIZIANO_MAN
++#define TIZIANO_MAN 3
++#endif
++
++//============================================================
++// BASE ADDRESS
++//============================================================
++#define    VIC_BASE              (TIZIANO_BASE + 0x10000)
++#define    TOP_BASE              (TIZIANO_BASE + 0x00000)
++#define    IP_BASE               (TIZIANO_BASE + 0x00100)
++#define    DPC_BASE              (TIZIANO_BASE + 0x00200)
++#define    GIB_BASE              (TIZIANO_BASE + 0x00400)
++#define    LSC_BASE              (TIZIANO_BASE + 0x00500)
++#define    AG_BASE               (TIZIANO_BASE + 0x00600)
++#define    AE_BASE               (TIZIANO_BASE + 0x00700)
++#define    AWB_BASE              (TIZIANO_BASE + 0x00800)
++#define    AF_BASE               (TIZIANO_BASE + 0x00900)
++#define    ADR_BASE              (TIZIANO_BASE + 0x00A00)
++#define    IRINT_BASE            (TIZIANO_BASE + 0x00F00)
++#define    DMSC_BASE             (TIZIANO_BASE + 0x01000)
++#define    CCM_BASE              (TIZIANO_BASE + 0x01200)
++#define    DEFOG_BASE            (TIZIANO_BASE + 0x01300)
++#define    CSC_BASE              (TIZIANO_BASE + 0x01700)
++#define    CLM_BASE              (TIZIANO_BASE + 0x01800)
++#define    SP_BASE               (TIZIANO_BASE + 0x01900)
++#define    MDNS_BASE             (TIZIANO_BASE + 0x01B00)
++#define    SDNS_BASE             (TIZIANO_BASE + 0x02000)
++#define    HLDC_BASE             (TIZIANO_BASE + 0x02200)
++#define    MSCA_BASE             (TIZIANO_BASE + 0x02300)
++
++#define    DPC_MEM_BASE          (TIZIANO_BASE + 0x04000)
++#define    LSC_MEM_BASE          (TIZIANO_BASE + 0x06000)
++#define    GIB_MEM_BASE          (TIZIANO_BASE + 0x08000)
++#define    AE_HIST_MEM_BASE      (TIZIANO_BASE + 0x08200)
++#define    R_GAMMA_MEM_BASE      (TIZIANO_BASE + 0x08A00)
++#define    G_GAMMA_MEM_BASE      (TIZIANO_BASE + 0x08C00)
++#define    B_GAMMA_MEM_BASE      (TIZIANO_BASE + 0x08E00)
++#define    DEFOG_MEM_BASE        (TIZIANO_BASE + 0x09000)
++#define    CLM_H_0_MEM_BASE      (TIZIANO_BASE + 0x0A000)
++#define    CLM_H_1_MEM_BASE      (TIZIANO_BASE + 0x0A800)
++#define    CLM_S_0_MEM_BASE      (TIZIANO_BASE + 0x0B000)
++#define    CLM_S_1_MEM_BASE      (TIZIANO_BASE + 0x0B800)
++
++//============================================================
++// VIC
++//============================================================
++#define    VIC_ADDR_CONTROL                       (VIC_BASE + 0x00)
++#define    VIC_ADDR_RESOLUTION                    (VIC_BASE + 0x04)
++#define    VIC_ADDR_FRAME_ECC                     (VIC_BASE + 0x08)
++#define    VIC_ADDR_INTF_TYPE                     (VIC_BASE + 0x0C)
++#define    VIC_ADDR_BT_CFG                        (VIC_BASE + 0x10)
++#define    VIC_ADDR_PCLK_GATE                     (VIC_BASE + 0x1C)
++#define    VIC_ADDR_HOR_PARA0                     (VIC_BASE + 0x20)
++#define    VIC_ADDR_HOR_PARA1                     (VIC_BASE + 0x24)
++#define    VIC_ADDR_VER_PARA0                     (VIC_BASE + 0x30)
++#define    VIC_ADDR_VER_PARA1                     (VIC_BASE + 0x34)
++#define    VIC_ADDR_VER_PARA2                     (VIC_BASE + 0x38)
++#define    VIC_ADDR_VER_PARA3                     (VIC_BASE + 0x3C)
++#define    VIC_ADDR_GLB_CFG                       (VIC_BASE + 0x50)
++#define    VIC_ADDR_AB_VLA                        (VIC_BASE + 0x54)
++#define    VIC_ADDR_HBLK_R                        (VIC_BASE + 0x58)
++#define    VIC_ADDR_VBLK_R                        (VIC_BASE + 0x5C)
++#define    VIC_ADDR_SAV_VALUE0                    (VIC_BASE + 0x60)
++#define    VIC_ADDR_EAV_VALUE0                    (VIC_BASE + 0x64)
++#define    VIC_ADDR_SAV_VALUE1                    (VIC_BASE + 0x68)
++#define    VIC_ADDR_EAV_VALUE1                    (VIC_BASE + 0x6C)
++#define    VIC_ADDR_SAV_VALUE2                    (VIC_BASE + 0x70)
++#define    VIC_ADDR_EAV_VALUE2                    (VIC_BASE + 0x74)
++#define    VIC_ADDR_WORK_STATE                    (VIC_BASE + 0x0090)
++#define    VIC_ADDR_PIX_REG                       (VIC_BASE + 0x0094)
++#define    VIC_ADDR_LINE_REG                      (VIC_BASE + 0x0098)
++#define    VIC_ADDR_OFIFO_CNT                     (VIC_BASE + 0x009C)
++#define    VIC_ADDR_BF_BAR_CTRL                   (VIC_BASE + 0x00A0)
++#define    VIC_ADDR_BF_BAR_BLANK                  (VIC_BASE + 0x00A4)
++#define    VIC_ADDR_AF_BAR_CTRL                   (VIC_BASE + 0x00B0)
++#define    VIC_ADDR_AF_BAR_BLANK                  (VIC_BASE + 0x00B4)
++#define    VIC_ADDR_WHITE_BAR                     (VIC_BASE + 0x00C0)
++#define    VIC_ADDR_BLACK_BAR                     (VIC_BASE + 0x00C4)
++#define    VIC_ADDR_BLUE_BAR                      (VIC_BASE + 0x00C8)
++#define    VIC_ADDR_GREEN_BAR                     (VIC_BASE + 0x00CC)
++#define    VIC_ADDR_RED_BAR                       (VIC_BASE + 0x00D0)
++#define    VIC_ADDR_CYAN_BAR                      (VIC_BASE + 0x00D4)
++#define    VIC_ADDR_YELLOW_BAR                    (VIC_BASE + 0x00D8)
++#define    VIC_ADDR_MAGENTA_BAR                   (VIC_BASE + 0x00DC)
++#define    VIC_ADDR_WHITE_BAR2                    (VIC_BASE + 0x00E0)
++#define    VIC_ADDR_BLACK_BAR2                    (VIC_BASE + 0x00E4)
++#define    VIC_ADDR_BLUE_BAR2                     (VIC_BASE + 0x00E8)
++#define    VIC_ADDR_GREEN_BAR2                    (VIC_BASE + 0x00EC)
++#define    VIC_ADDR_RED_BAR2                      (VIC_BASE + 0x00F0)
++#define    VIC_ADDR_CYAN_BAR2                     (VIC_BASE + 0x00F4)
++#define    VIC_ADDR_YELLOW_BAR2                   (VIC_BASE + 0x00F8)
++#define    VIC_ADDR_MAGENTA_BAR2                  (VIC_BASE + 0x00FC)
++#define    VIC_ADDR_INT_STA                       (VIC_BASE + 0x0100)
++#define    VIC_ADDR_INT_MASK                      (VIC_BASE + 0x0104)
++#define    VIC_ADDR_INT_CLR                       (VIC_BASE + 0x0108)
++#define    VIC_ADDR_DMA_CONFIGURE                 (VIC_BASE + 0x0200)
++#define    VIC_ADDR_DMA_RES_R                     (VIC_BASE + 0x0204)
++#define    VIC_ADDR_DMA_RESET                     (VIC_BASE + 0x0208)
++#define    VIC_ADDR_DMA_Y_CH_BANK_CONTROL         (VIC_BASE + 0x0210)
++#define    VIC_ADDR_DMA_Y_CH_LINE_STRIDE          (VIC_BASE + 0x0214)
++#define    VIC_ADDR_DMA_Y_CH_BANK0_ADDR           (VIC_BASE + 0x0218)
++#define    VIC_ADDR_DMA_Y_CH_BANK1_ADDR           (VIC_BASE + 0x021c)
++#define    VIC_ADDR_DMA_Y_CH_BANK2_ADDR           (VIC_BASE + 0x0220)
++#define    VIC_ADDR_DMA_Y_CH_BANK3_ADDR           (VIC_BASE + 0x0224)
++#define    VIC_ADDR_DMA_Y_CH_BANK4_ADDR           (VIC_BASE + 0x0228)
++#define    VIC_ADDR_DMA_UV_CH_BANK_CONTROL        (VIC_BASE + 0x0230)
++#define    VIC_ADDR_DMA_UV_CH_LINE_STRIDE         (VIC_BASE + 0x0234)
++#define    VIC_ADDR_DMA_UV_CH_BANK0_ADDR          (VIC_BASE + 0x0238)
++#define    VIC_ADDR_DMA_UV_CH_BANK1_ADDR          (VIC_BASE + 0x023c)
++#define    VIC_ADDR_DMA_UV_CH_BANK2_ADDR          (VIC_BASE + 0x0240)
++#define    VIC_ADDR_DMA_UV_CH_BANK3_ADDR          (VIC_BASE + 0x0244)
++#define    VIC_ADDR_DMA_UV_CH_BANK4_ADDR          (VIC_BASE + 0x0248)
++#define    VIC_ADDR_SYFIFO_USED                   (VIC_BASE + 0x0300)
++#define    VIC_ADDR_FR_DONE_CNT                   (VIC_BASE + 0x0304)
++#define    VIC_ADDR_DVP_SIZE                      (VIC_BASE + 0x0308)
++#define    VIC_ADDR_DVP_WORK_STA                  (VIC_BASE + 0x030C)
++
++
++//============================================================
++// TOP
++//============================================================
++#define    DPC			(0 << 0)
++#define    GIB			(0 << 1)
++#define    LSC			(0 << 2)
++#define    AWB			(0 << 3)
++#define    ADR			(1 << 4)
++#define    DMS			(0 << 5)
++#define    CCM			(0 << 6)
++#define    GAMMA		(0 << 7)
++#define	   DEFOG		(1 << 8)
++#define    CLM			(0 << 9)
++#define    Y_SHARPEN		(0 << 10)
++#define    MDNS			(0 << 11)
++#define    SDNS			(0 << 12)
++#define    HLDC			(1 << 13)
++#define    TP			(1 << 14)
++#define    FONT			(1 << 15)
++#define    SEL			(0 << 31)
++#define    TIZIANO_BYPASS_INIT (DPC|GIB|LSC|AWB|ADR|DMS|CCM|GAMMA|DEFOG|CLM|Y_SHARPEN|MDNS|SDNS|HLDC|TP|FONT|SEL)
++
++#define    TIZIANO_FM_SIZE				(TOP_BASE + 0X0004)
++#define    TIZIANO_BATER_TYPE				(TOP_BASE + 0X0008)
++#define    TIZAINO_BYPASS_CON				(TOP_BASE + 0X000C)
++#define    TIZIANO_TOP_CON				(TOP_BASE + 0X0010)
++#define    TIZIANO_REG_CON				(TOP_BASE + 0X001C)
++#define    TIZAINO_INT_EN				(TOP_BASE + 0X0080)
++
++#define    TOP_CTRL_ADDR_VERSION                        (TOP_BASE + 0x0000)
++#define    TOP_CTRL_ADDR_FM_SIZE                        (TOP_BASE + 0x0004)
++#define    TOP_CTRL_ADDR_BAYER_TYPE                     (TOP_BASE + 0x0008)
++#define    TOP_CTRL_ADDR_BYPASS_CON                     (TOP_BASE + 0x000C)
++#define    TOP_CTRL_ADDR_TOP_CON                        (TOP_BASE + 0x0010)
++#define    TOP_CTRL_ADDR_TOP_STATE                      (TOP_BASE + 0x0014)
++#define    TOP_CTRL_ADDR_LINE_SPACE                     (TOP_BASE + 0x0018)
++#define    TOP_CTRL_ADDR_REG_CON                        (TOP_BASE + 0x001C)
++#define    TOP_CTRL_ADDR_DMA_RC_TRIG                    (TOP_BASE + 0x0030)
++#define    TOP_CTRL_ADDR_DMA_RC_CON                     (TOP_BASE + 0x0034)
++#define    TOP_CTRL_ADDR_DMA_RC_ADDR                    (TOP_BASE + 0x0038)
++#define    TOP_CTRL_ADDR_DMA_RC_STATE                   (TOP_BASE + 0x003C)
++#define    TOP_CTRL_ADDR_DMA_RC_APB_WR_DATA             (TOP_BASE + 0x0040)
++#define    TOP_CTRL_ADDR_DMA_RC_APB_WR_ADDR             (TOP_BASE + 0x0044)
++#define    TOP_CTRL_ADDR_DMA_RD_CON                     (TOP_BASE + 0x0050)
++#define    TOP_CTRL_ADDR_DMA_WR_CON                     (TOP_BASE + 0x0054)
++#define    TOP_CTRL_ADDR_DMA_FR_WR_CON                  (TOP_BASE + 0x0058)
++#define    TOP_CTRL_ADDR_DMA_STA_WR_CON                 (TOP_BASE + 0x005C)
++#define    TOP_CTRL_ADDR_DMA_RD_DEBUG                   (TOP_BASE + 0x0060)
++#define    TOP_CTRL_ADDR_DMA_WR_DEBUG                   (TOP_BASE + 0x0064)
++#define    TOP_CTRL_ADDR_DMA_FR_WR_DEBUG                (TOP_BASE + 0x0068)
++#define    TOP_CTRL_ADDR_DMA_STA_WR_DEBUG               (TOP_BASE + 0x006C)
++#define    TOP_CTRL_ADDR_INT_EN                         (TOP_BASE + 0x0080)
++#define    TOP_CTRL_ADDR_INT_REG                        (TOP_BASE + 0x0084)
++#define    TOP_CTRL_ADDR_INT_CLR                        (TOP_BASE + 0x0088)
++#define    TOP_CTRL_ADDR_TP_FREERUN                     (TOP_BASE + 0x00A0)
++#define    TOP_CTRL_ADDR_TP_CON                         (TOP_BASE + 0x00A4)
++#define    TOP_CTRL_ADDR_TP_SIZE                        (TOP_BASE + 0x00A8)
++#define    TOP_CTRL_ADDR_TP_FONT                        (TOP_BASE + 0x00AC)
++#define    TOP_CTRL_ADDR_TP_FLICK                       (TOP_BASE + 0x00B0)
++#define    TOP_CTRL_ADDR_TP_CS_TYPE                     (TOP_BASE + 0x00B4)
++#define    TOP_CTRL_ADDR_TP_CS_FCLO                     (TOP_BASE + 0x00B8)
++#define    TOP_CTRL_ADDR_TP_CS_BCLO                     (TOP_BASE + 0x00BC)
++
++//============================================================
++// Input Interface
++//============================================================
++#define    INPUT_CTRL_ADDR_IP_TRIG                      (IP_BASE + 0x0000)
++#define    INPUT_CTRL_ADDR_CONTROL                      (IP_BASE + 0x0004)
++#define    INPUT_CTRL_ADDR_CHK_TRIG                     (IP_BASE + 0x0008)
++#define    INPUT_CTRL_ADDR_CHK_TIME                     (IP_BASE + 0x000C)
++#define    INPUT_CTRL_ADDR_CHK_CNT                      (IP_BASE + 0x0010)
++#define    INPUT_CTRL_ADDR_CHK_FR_CNT                   (IP_BASE + 0x0014)
++#define    INPUT_CTRL_ADDR_IP_STATE                     (IP_BASE + 0x0018)
++#define    INPUT_CTRL_ADDR_IN_CNT                       (IP_BASE + 0x001C)
++#define    INPUT_CTRL_ADDR_OUT_CNT                      (IP_BASE + 0x0020)
++
++//============================================================
++// DPC
++//============================================================
++#define    DPC_ADDR_SYNC                          (DPC_BASE + 0x0000)
++#define    DPC_ADDR_S_EN                          (DPC_BASE + 0x0004)
++#define    DPC_ADDR_S_OC_BLEND_ALPHA              (DPC_BASE + 0x0008)
++#define    DPC_ADDR_OC_BLEND_ALPHA                (DPC_BASE + 0x000C)
++#define    DPC_ADDR_SD_LV1_SLOPE                  (DPC_BASE + 0x0010)
++#define    DPC_ADDR_SD_LV2_SLOPE                  (DPC_BASE + 0x0014)
++#define    DPC_ADDR_LS_BLEND_ALPHA_RB             (DPC_BASE + 0x0018)
++#define    DPC_ADDR_LV1_DIFF_THRES_RB             (DPC_BASE + 0x001C)
++#define    DPC_ADDR_SD_LV2_DIFF_THRES_RB          (DPC_BASE + 0x0020)
++#define    DPC_ADDR_SD_LV2_P0_THRES_RB            (DPC_BASE + 0x0024)
++#define    DPC_ADDR_SD_LV2_P2_THRES_RB            (DPC_BASE + 0x0028)
++#define    DPC_ADDR_SD_LV2_P0_DIST_THRES_RB       (DPC_BASE + 0x002C)
++#define    DPC_ADDR_SD_LV2_P2_DIST_THRES_RB       (DPC_BASE + 0x0030)
++#define    DPC_ADDR_LD_LV2_THRES_RB               (DPC_BASE + 0x0034)
++#define    DPC_ADDR_LS_BLEND_ALPHA_G              (DPC_BASE + 0x0038)
++#define    DPC_ADDR_LV1_DIFF_THRES_G              (DPC_BASE + 0x003C)
++#define    DPC_ADDR_SD_LV2_DIFF_THRES_G           (DPC_BASE + 0x0040)
++#define    DPC_ADDR_SD_LV2_P0_THRES_G             (DPC_BASE + 0x0044)
++#define    DPC_ADDR_SD_LV2_P2_THRES_G             (DPC_BASE + 0x0048)
++#define    DPC_ADDR_SD_LV2_P0_DIST_THRES_G        (DPC_BASE + 0x004C)
++#define    DPC_ADDR_SD_LV2_P2_DIST_THRES_G        (DPC_BASE + 0x0050)
++#define    DPC_ADDR_LD_LV2_THRES_G                (DPC_BASE + 0x0054)
++#define    DPC_ADDR_CTR_FUNC_EN                   (DPC_BASE + 0x0058)
++#define    DPC_ADDR_CTR_MD_SEG_OPT                (DPC_BASE + 0x005C)
++#define    DPC_ADDR_CTR_BASE_THRES                (DPC_BASE + 0x0060)
++#define    DPC_ADDR_RDNS_FUNC_EN                  (DPC_BASE + 0x0064)
++#define    DPC_ADDR_RDNS_FLAT_THRES               (DPC_BASE + 0x0068)
++#define    DPC_ADDR_RDNS_TEXT_THRES               (DPC_BASE + 0x006C)
++#define    DPC_ADDR_RDNS_SIGMA_X1                 (DPC_BASE + 0x0070)
++#define    DPC_ADDR_RDNS_STD                      (DPC_BASE + 0x0074)
++#define    DPC_ADDR_RDNS_RB_GAUS_SIGMA            (DPC_BASE + 0x0078)
++#define    DPC_ADDR_RDNS_G_SIGMA_X                (DPC_BASE + 0x007C)
++#define    DPC_ADDR_RDNS_G_SIGMA_S                (DPC_BASE + 0x0080)
++#define    DPC_ADDR_RDNS_RB_SIGMA_X               (DPC_BASE + 0x0084)
++#define    DPC_ADDR_RDNS_RB_SIGMA_S               (DPC_BASE + 0x0088)
++#define    DPC_ADDR_CTR_MD_NP_ARRAY_RG0           (DPC_BASE + 0x008C)
++#define    DPC_ADDR_CTR_MD_NP_ARRAY_RG1           (DPC_BASE + 0x0090)
++#define    DPC_ADDR_CTR_MD_NP_ARRAY_RG2           (DPC_BASE + 0x0094)
++#define    DPC_ADDR_CTR_MD_NP_ARRAY_RG3           (DPC_BASE + 0x0098)
++#define    DPC_ADDR_RDNS_STD_NP_ARRAY_RG0         (DPC_BASE + 0x009C)
++#define    DPC_ADDR_RDNS_STD_NP_ARRAY_RG1         (DPC_BASE + 0x00A0)
++#define    DPC_ADDR_RDNS_STD_NP_ARRAY_RG2         (DPC_BASE + 0x00A4)
++#define    DPC_ADDR_RDNS_STD_NP_ARRAY_RG3         (DPC_BASE + 0x00A8)
++#define    DPC_ADDR_RDNS_STD_NP_ARRAY_RG4         (DPC_BASE + 0x00AC)
++#define    DPC_ADDR_RDNS_STD_NP_ARRAY_RG5         (DPC_BASE + 0x00B0)
++#define    DPC_ADDR_RDNS_STD_NP_ARRAY_RG6         (DPC_BASE + 0x00B4)
++#define    DPC_ADDR_RDNS_STD_NP_ARRAY_RG7         (DPC_BASE + 0x00B8)
++#define    DPC_ADDR_RDNS_G_LUM_NP_ARRAY_RG0       (DPC_BASE + 0x00BC)
++#define    DPC_ADDR_RDNS_G_LUM_NP_ARRAY_RG1       (DPC_BASE + 0x00C0)
++#define    DPC_ADDR_RDNS_G_LUM_NP_ARRAY_RG2       (DPC_BASE + 0x00C4)
++#define    DPC_ADDR_RDNS_G_LUM_NP_ARRAY_RG3       (DPC_BASE + 0x00C8)
++#define    DPC_ADDR_RDNS_G_LUM_NP_ARRAY_RG4       (DPC_BASE + 0x00CC)
++#define    DPC_ADDR_RDNS_G_LUM_NP_ARRAY_RG5       (DPC_BASE + 0x00D0)
++#define    DPC_ADDR_RDNS_G_LUM_NP_ARRAY_RG6       (DPC_BASE + 0x00D4)
++#define    DPC_ADDR_RDNS_G_LUM_NP_ARRAY_RG7       (DPC_BASE + 0x00D8)
++#define    DPC_ADDR_RDNS_G_STD_NP_ARRAY_RG0       (DPC_BASE + 0x00DC)
++#define    DPC_ADDR_RDNS_G_STD_NP_ARRAY_RG1       (DPC_BASE + 0x00E0)
++#define    DPC_ADDR_RDNS_G_STD_NP_ARRAY_RG2       (DPC_BASE + 0x00E4)
++#define    DPC_ADDR_RDNS_G_STD_NP_ARRAY_RG3       (DPC_BASE + 0x00E8)
++#define    DPC_ADDR_RDNS_G_STD_NP_ARRAY_RG4       (DPC_BASE + 0x00EC)
++#define    DPC_ADDR_RDNS_G_STD_NP_ARRAY_RG5       (DPC_BASE + 0x00F0)
++#define    DPC_ADDR_RDNS_G_STD_NP_ARRAY_RG6       (DPC_BASE + 0x00F4)
++#define    DPC_ADDR_RDNS_G_STD_NP_ARRAY_RG7       (DPC_BASE + 0x00F8)
++#define    DPC_ADDR_RDNS_RB_LUM_NP_ARRAY_RG0      (DPC_BASE + 0x00FC)
++#define    DPC_ADDR_RDNS_RB_LUM_NP_ARRAY_RG1      (DPC_BASE + 0x0100)
++#define    DPC_ADDR_RDNS_RB_LUM_NP_ARRAY_RG2      (DPC_BASE + 0x0104)
++#define    DPC_ADDR_RDNS_RB_LUM_NP_ARRAY_RG3      (DPC_BASE + 0x0108)
++#define    DPC_ADDR_RDNS_RB_LUM_NP_ARRAY_RG4      (DPC_BASE + 0x010C)
++#define    DPC_ADDR_RDNS_RB_LUM_NP_ARRAY_RG5      (DPC_BASE + 0x0110)
++#define    DPC_ADDR_RDNS_RB_LUM_NP_ARRAY_RG6      (DPC_BASE + 0x0114)
++#define    DPC_ADDR_RDNS_RB_LUM_NP_ARRAY_RG7      (DPC_BASE + 0x0118)
++#define    DPC_ADDR_RDNS_RB_STD_NP_ARRAY_RG0      (DPC_BASE + 0x011C)
++#define    DPC_ADDR_RDNS_RB_STD_NP_ARRAY_RG1      (DPC_BASE + 0x0120)
++#define    DPC_ADDR_RDNS_RB_STD_NP_ARRAY_RG2      (DPC_BASE + 0x0124)
++#define    DPC_ADDR_RDNS_RB_STD_NP_ARRAY_RG3      (DPC_BASE + 0x0128)
++#define    DPC_ADDR_RDNS_RB_STD_NP_ARRAY_RG4      (DPC_BASE + 0x012C)
++#define    DPC_ADDR_RDNS_RB_STD_NP_ARRAY_RG5      (DPC_BASE + 0x0130)
++#define    DPC_ADDR_RDNS_RB_STD_NP_ARRAY_RG6      (DPC_BASE + 0x0134)
++#define    DPC_ADDR_RDNS_RB_STD_NP_ARRAY_RG7      (DPC_BASE + 0x0138)
++#define    DPC_ADDR_SDP_NUM                       (DPC_BASE + 0x013C)
++#define    DPC_ADDR_SP_DEBUG_REG_0                (DPC_BASE + 0x0140)
++#define    DPC_ADDR_SP_DEBUG_REG_1                (DPC_BASE + 0x0144)
++
++//============================================================
++// GIB
++//============================================================
++#define    GIB_ADDR_REG_CTRL                      (GIB_BASE + 0x0000)
++#define    GIB_ADDR_CONFIG                        (GIB_BASE + 0x0004)
++#define    GIB_ADDR_R_G                           (GIB_BASE + 0x0008)
++#define    GIB_ADDR_B_IR                          (GIB_BASE + 0x000c)
++#define    GIB_ADDR_DEIRM_R12                     (GIB_BASE + 0x0010)
++#define    GIB_ADDR_DEIRM_R34                     (GIB_BASE + 0x0014)
++#define    GIB_ADDR_DEIRM_C1                      (GIB_BASE + 0x0018)
++#define    GIB_ADDR_DEIRM_G12                     (GIB_BASE + 0x001c)
++#define    GIB_ADDR_DEIRM_G34                     (GIB_BASE + 0x0020)
++#define    GIB_ADDR_DEIRM_C2                      (GIB_BASE + 0x0024)
++#define    GIB_ADDR_DEIRM_B12                     (GIB_BASE + 0x0028)
++#define    GIB_ADDR_DEIRM_B34                     (GIB_BASE + 0x002c)
++#define    GIB_ADDR_DEIRM_C3                      (GIB_BASE + 0x0030)
++#define    GIB_ADDR_DEIRM_BLC12                   (GIB_BASE + 0x0034)
++#define    GIB_ADDR_DEIRM_BLC34                   (GIB_BASE + 0x0038)
++#define    GIB_ADDR_DEIRM_BLC5                    (GIB_BASE + 0x003c)
++#define    GIB_ADDR_DEBUG0                        (GIB_BASE + 0x0040)
++#define    GIB_DEIR_R_BASE                        (GIB_MEM_BASE + 0x0000)
++#define    GIB_DEIR_G_BASE                        (GIB_MEM_BASE + 0x0080)
++#define    GIB_DEIR_B_BASE                        (GIB_MEM_BASE + 0x0100)
++
++//============================================================
++// LSC
++//============================================================
++#define    LSC_ADDR_T_VERSION                     (LSC_BASE + 0x0000)
++#define    LSC_ADDR_T_DBG_SEL                     (LSC_BASE + 0x0004)
++#define    LSC_ADDR_T_DBG_VALUE                   (LSC_BASE + 0x0008)
++#define    LSC_ADDR_MESH_SIZE                     (LSC_BASE + 0x0010)
++#define    LSC_ADDR_MESH_SCALE                    (LSC_BASE + 0x0014)
++#define    LSC_ADDR_LUT_STRIDE                    (LSC_BASE + 0x0018)
++
++//============================================================
++// AG
++//============================================================
++#define    AWB_GAIN_ADDR_REG_CTRL                 (AG_BASE + 0x0000)
++#define    AWB_GAIN_ADDR_R_G                      (AG_BASE + 0x0004)
++#define    AWB_GAIN_ADDR_B_IR                     (AG_BASE + 0x0008)
++#define    AWB_GAIN_ADDR_DEBUG0                   (AG_BASE + 0x000c)
++
++//============================================================
++// AE
++//============================================================
++#define    AE_STAT_ADDR_REG_CTRL                  (AE_BASE + 0x0000)
++#define    AE_STAT_ADDR_ZONE_NUM_START            (AE_BASE + 0x0004)
++#define    AE_STAT_ADDR_HOR_ZONE_SIZE_14          (AE_BASE + 0x0008)
++#define    AE_STAT_ADDR_HOR_ZONE_SIZE_58          (AE_BASE + 0x000c)
++#define    AE_STAT_ADDR_HOR_ZONE_SIZE_912         (AE_BASE + 0x0010)
++#define    AE_STAT_ADDR_HOR_ZONE_SIZE_1315        (AE_BASE + 0x0014)
++#define    AE_STAT_ADDR_VER_ZONE_SIZE_14          (AE_BASE + 0x0018)
++#define    AE_STAT_ADDR_VER_ZONE_SIZE_58          (AE_BASE + 0x001c)
++#define    AE_STAT_ADDR_VER_ZONE_SIZE_912         (AE_BASE + 0x0020)
++#define    AE_STAT_ADDR_VER_ZONE_SIZE_1315        (AE_BASE + 0x0024)
++#define    AE_STAT_ADDR_LUM_TH_FREQ               (AE_BASE + 0x0028)
++#define    AE_STAT_ADDR_AE_DMA_BASE_1             (AE_BASE + 0x002c)
++#define    AE_STAT_ADDR_AE_DMA_BASE_2             (AE_BASE + 0x0030)
++#define    AE_STAT_ADDR_AE_DMA_BASE_3             (AE_BASE + 0x0034)
++#define    AE_STAT_ADDR_AE_DMA_BASE_4             (AE_BASE + 0x0038)
++#define    AE_STAT_ADDR_HIST_DMA_BASE_1           (AE_BASE + 0x003c)
++#define    AE_STAT_ADDR_HIST_DMA_BASE_2           (AE_BASE + 0x0040)
++#define    AE_STAT_ADDR_HIST_DMA_BASE_3           (AE_BASE + 0x0044)
++#define    AE_STAT_ADDR_HIST_DMA_BASE_4           (AE_BASE + 0x0048)
++#define    AE_STAT_ADDR_DMA_BASE_NUM              (AE_BASE + 0x004c)
++#define    AE_STAT_ADDR_DMA_INFO                  (AE_BASE + 0x0050)
++#define    AE_STAT_ADDR_DEBUG0                    (AE_BASE + 0x0054)
++#define    AE_STAT_ADDR_DEBUG1                    (AE_BASE + 0x0058)
++
++//============================================================
++// AWB
++//============================================================
++#define    AWB_STAT_ADDR_REG_CTRL                 (AWB_BASE + 0x0000)
++#define    AWB_STAT_ADDR_ZONE_NUM_START           (AWB_BASE + 0x0004)
++#define    AWB_STAT_ADDR_HOR_ZONE_SIZE_14         (AWB_BASE + 0x0008)
++#define    AWB_STAT_ADDR_HOR_ZONE_SIZE_58         (AWB_BASE + 0x000c)
++#define    AWB_STAT_ADDR_HOR_ZONE_SIZE_912        (AWB_BASE + 0x0010)
++#define    AWB_STAT_ADDR_HOR_ZONE_SIZE_1315       (AWB_BASE + 0x0014)
++#define    AWB_STAT_ADDR_VER_ZONE_SIZE_14         (AWB_BASE + 0x0018)
++#define    AWB_STAT_ADDR_VER_ZONE_SIZE_58         (AWB_BASE + 0x001c)
++#define    AWB_STAT_ADDR_VER_ZONE_SIZE_912        (AWB_BASE + 0x0020)
++#define    AWB_STAT_ADDR_VER_ZONE_SIZE_1315       (AWB_BASE + 0x0024)
++#define    AWB_STAT_ADDR_RG_TH                    (AWB_BASE + 0x0028)
++#define    AWB_STAT_ADDR_BG_TH                    (AWB_BASE + 0x002c)
++#define    AWB_STAT_ADDR_K1_A1                    (AWB_BASE + 0x0030)
++#define    AWB_STAT_ADDR_K2_A2                    (AWB_BASE + 0x0034)
++#define    AWB_STAT_ADDR_LUM_TH_FREQ              (AWB_BASE + 0x0038)
++#define    AWB_STAT_ADDR_AWB_DMA_BASE_1           (AWB_BASE + 0x003c)
++#define    AWB_STAT_ADDR_AWB_DMA_BASE_2           (AWB_BASE + 0x0040)
++#define    AWB_STAT_ADDR_AWB_DMA_BASE_3           (AWB_BASE + 0x0044)
++#define    AWB_STAT_ADDR_AWB_DMA_BASE_4           (AWB_BASE + 0x0048)
++#define    AWB_STAT_ADDR_DMA_BASE_NUM             (AWB_BASE + 0x004c)
++#define    AWB_STAT_ADDR_DMA_INFO                 (AWB_BASE + 0x0050)
++#define    AWB_STAT_ADDR_DEBUG0                   (AWB_BASE + 0x0054)
++#define    AWB_STAT_ADDR_DEBUG1                   (AWB_BASE + 0x0058)
++
++//============================================================
++// AF
++//============================================================
++#define    AF_STAT_ADDR_REG_CTRL                  (AF_BASE + 0x0000)
++#define    AF_STAT_ADDR_ZONE_NUM_START            (AF_BASE + 0x0004)
++#define    AF_STAT_ADDR_HOR_ZONE_SIZE_14          (AF_BASE + 0x0008)
++#define    AF_STAT_ADDR_HOR_ZONE_SIZE_58          (AF_BASE + 0x000c)
++#define    AF_STAT_ADDR_HOR_ZONE_SIZE_912         (AF_BASE + 0x0010)
++#define    AF_STAT_ADDR_HOR_ZONE_SIZE_1315        (AF_BASE + 0x0014)
++#define    AF_STAT_ADDR_VER_ZONE_SIZE_14          (AF_BASE + 0x0018)
++#define    AF_STAT_ADDR_VER_ZONE_SIZE_58          (AF_BASE + 0x001c)
++#define    AF_STAT_ADDR_VER_ZONE_SIZE_912         (AF_BASE + 0x0020)
++#define    AF_STAT_ADDR_VER_ZONE_SIZE_1315        (AF_BASE + 0x0024)
++#define    AF_STAT_ADDR_FREQ_IIR_EN_LUM_TH        (AF_BASE + 0x0028)
++#define    AF_STAT_ADDR_LDG_COR_EN                (AF_BASE + 0x002c)
++#define    AF_STAT_ADDR_FIR0_G1_G2                (AF_BASE + 0x0030)
++#define    AF_STAT_ADDR_FIR0_G3_G4                (AF_BASE + 0x0034)
++#define    AF_STAT_ADDR_FIR0_G5                   (AF_BASE + 0x0038)
++#define    AF_STAT_ADDR_FIR1_G1_G2                (AF_BASE + 0x003c)
++#define    AF_STAT_ADDR_FIR1_G3_G4                (AF_BASE + 0x0040)
++#define    AF_STAT_ADDR_FIR1_G5                   (AF_BASE + 0x0044)
++#define    AF_STAT_ADDR_IIR0_G1_G3                (AF_BASE + 0x0048)
++#define    AF_STAT_ADDR_IIR0_G4_G5                (AF_BASE + 0x004c)
++#define    AF_STAT_ADDR_IIR0_G6_G8                (AF_BASE + 0x0050)
++#define    AF_STAT_ADDR_IIR0_G9_G10               (AF_BASE + 0x0054)
++#define    AF_STAT_ADDR_IIR1_G1_G3                (AF_BASE + 0x0058)
++#define    AF_STAT_ADDR_IIR1_G4_G5                (AF_BASE + 0x005c)
++#define    AF_STAT_ADDR_IIR1_G6_G8                (AF_BASE + 0x0060)
++#define    AF_STAT_ADDR_IIR1_G9_G10               (AF_BASE + 0x0064)
++#define    AF_STAT_ADDR_LDG_FIR0_LOW              (AF_BASE + 0x0068)
++#define    AF_STAT_ADDR_LDG_FIR0_HIGH             (AF_BASE + 0x006c)
++#define    AF_STAT_ADDR_LDG_FIR1_LOW              (AF_BASE + 0x0070)
++#define    AF_STAT_ADDR_LDG_FIR1_HIGH             (AF_BASE + 0x0074)
++#define    AF_STAT_ADDR_LDG_IIR0_LOW              (AF_BASE + 0x0078)
++#define    AF_STAT_ADDR_LDG_IIR0_HIGH             (AF_BASE + 0x007c)
++#define    AF_STAT_ADDR_LDG_IIR1_LOW              (AF_BASE + 0x0080)
++#define    AF_STAT_ADDR_LDG_IIR1_HIGH             (AF_BASE + 0x0084)
++#define    AF_STAT_ADDR_COR_F0_TH_LH              (AF_BASE + 0x0088)
++#define    AF_STAT_ADDR_COR_F0_SLP_LIM            (AF_BASE + 0x008c)
++#define    AF_STAT_ADDR_COR_F1_TH_LH              (AF_BASE + 0x0090)
++#define    AF_STAT_ADDR_COR_F1_SLP_LIM            (AF_BASE + 0x0094)
++#define    AF_STAT_ADDR_COR_I0_TH_LH              (AF_BASE + 0x0098)
++#define    AF_STAT_ADDR_COR_I0_SLP_LIM            (AF_BASE + 0x009c)
++#define    AF_STAT_ADDR_COR_I1_TH_LH              (AF_BASE + 0x00a0)
++#define    AF_STAT_ADDR_COR_I1_SLP_LIM            (AF_BASE + 0x00a4)
++#define    AF_STAT_ADDR_AF_DMA_BASE_1             (AF_BASE + 0x00a8)
++#define    AF_STAT_ADDR_AF_DMA_BASE_2             (AF_BASE + 0x00ac)
++#define    AF_STAT_ADDR_AF_DMA_BASE_3             (AF_BASE + 0x00b0)
++#define    AF_STAT_ADDR_AF_DMA_BASE_4             (AF_BASE + 0x00b4)
++#define    AF_STAT_ADDR_DMA_BASE_NUM              (AF_BASE + 0x00b8)
++#define    AF_STAT_ADDR_DMA_INFO                  (AF_BASE + 0x00bc)
++#define    AF_STAT_ADDR_DEBUG0                    (AF_BASE + 0x00c0)
++
++//============================================================
++// ADR
++//============================================================
++#define    ADR_ADDR_T_VERSION                     (ADR_BASE + 0x0000)
++#define    ADR_ADDR_T_DBG_SEL                     (ADR_BASE + 0x0004)
++#define    ADR_ADDR_T_DEG_VALUE                   (ADR_BASE + 0x0008)
++#define    ADR_ADDR_STEP_PAR                      (ADR_BASE + 0x000C)
++#define    ADR_ADDR_BLK_COORD_M_P_0               (ADR_BASE + 0x0010)
++#define    ADR_ADDR_BLK_COORD_M_P_1               (ADR_BASE + 0x0014)
++#define    ADR_ADDR_BLK_COORD_M_P_2               (ADR_BASE + 0x0018)
++#define    ADR_ADDR_BLK_COORD_N_P_0               (ADR_BASE + 0x001C)
++#define    ADR_ADDR_BLK_COORD_N_P_1               (ADR_BASE + 0x0020)
++#define    ADR_ADDR_BLK_COORD_N_P_2               (ADR_BASE + 0x0024)
++#define    ADR_ADDR_CEN_DIS_P_0                   (ADR_BASE + 0x0028)
++#define    ADR_ADDR_CEN_DIS_P_1                   (ADR_BASE + 0x002C)
++#define    ADR_ADDR_CEN_DIS_P_2                   (ADR_BASE + 0x0030)
++#define    ADR_ADDR_CEN_DIS_P_3                   (ADR_BASE + 0x0034)
++#define    ADR_ADDR_CEN_DIS_P_4                   (ADR_BASE + 0x0038)
++#define    ADR_ADDR_CEN_DIS_P_5                   (ADR_BASE + 0x003C)
++#define    ADR_ADDR_CEN_DIS_P_6                   (ADR_BASE + 0x0040)
++#define    ADR_ADDR_CEN_DIS_P_7                   (ADR_BASE + 0x0044)
++#define    ADR_ADDR_CEN_DIS_P_8                   (ADR_BASE + 0x0048)
++#define    ADR_ADDR_CEN_DIS_P_9                   (ADR_BASE + 0x004C)
++#define    ADR_ADDR_CEN_DIS_P_A                   (ADR_BASE + 0x0050)
++#define    ADR_ADDR_CEN_DIS_P_B                   (ADR_BASE + 0x0054)
++#define    ADR_ADDR_CEN_DIS_P_C                   (ADR_BASE + 0x0058)
++#define    ADR_ADDR_CEN_DIS_P_D                   (ADR_BASE + 0x005C)
++#define    ADR_ADDR_CEN_DIS_P_E                   (ADR_BASE + 0x0060)
++#define    ADR_ADDR_CEN_DIS_P_F                   (ADR_BASE + 0x0064)
++#define    ADR_ADDR_MAP_KPOINT_X_P0               (ADR_BASE + 0x0068)
++#define    ADR_ADDR_MAP_KPOINT_X_P1               (ADR_BASE + 0x006C)
++#define    ADR_ADDR_MAP_KPOINT_X_P2               (ADR_BASE + 0x0070)
++#define    ADR_ADDR_MAP_KPOINT_X_P3               (ADR_BASE + 0x0074)
++#define    ADR_ADDR_MAP_KPOINT_X_P4               (ADR_BASE + 0x0078)
++#define    ADR_ADDR_MAP_KPOINT_X_P5               (ADR_BASE + 0x007C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P00_0            (ADR_BASE + 0x0080)
++#define    ADR_ADDR_MAP_KPOINT_Y_P00_1            (ADR_BASE + 0x0084)
++#define    ADR_ADDR_MAP_KPOINT_Y_P00_2            (ADR_BASE + 0x0088)
++#define    ADR_ADDR_MAP_KPOINT_Y_P00_3            (ADR_BASE + 0x008C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P00_4            (ADR_BASE + 0x0090)
++#define    ADR_ADDR_MAP_KPOINT_Y_P00_5            (ADR_BASE + 0x0094)
++#define    ADR_ADDR_MAP_KPOINT_Y_P01_0            (ADR_BASE + 0x0098)
++#define    ADR_ADDR_MAP_KPOINT_Y_P01_1            (ADR_BASE + 0x009C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P01_2            (ADR_BASE + 0x00A0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P01_3            (ADR_BASE + 0x00A4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P01_4            (ADR_BASE + 0x00A8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P01_5            (ADR_BASE + 0x00AC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P02_0            (ADR_BASE + 0x00B0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P02_1            (ADR_BASE + 0x00B4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P02_2            (ADR_BASE + 0x00B8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P02_3            (ADR_BASE + 0x00BC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P02_4            (ADR_BASE + 0x00C0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P02_5            (ADR_BASE + 0x00C4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P03_0            (ADR_BASE + 0x00C8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P03_1            (ADR_BASE + 0x00CC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P03_2            (ADR_BASE + 0x00D0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P03_3            (ADR_BASE + 0x00D4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P03_4            (ADR_BASE + 0x00D8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P03_5            (ADR_BASE + 0x00DC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P04_0            (ADR_BASE + 0x00E0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P04_1            (ADR_BASE + 0x00E4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P04_2            (ADR_BASE + 0x00E8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P04_3            (ADR_BASE + 0x00EC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P04_4            (ADR_BASE + 0x00F0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P04_5            (ADR_BASE + 0x00F4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P05_0            (ADR_BASE + 0x00F8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P05_1            (ADR_BASE + 0x00FC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P05_2            (ADR_BASE + 0x0100)
++#define    ADR_ADDR_MAP_KPOINT_Y_P05_3            (ADR_BASE + 0x0104)
++#define    ADR_ADDR_MAP_KPOINT_Y_P05_4            (ADR_BASE + 0x0108)
++#define    ADR_ADDR_MAP_KPOINT_Y_P05_5            (ADR_BASE + 0x010C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P06_0            (ADR_BASE + 0x0110)
++#define    ADR_ADDR_MAP_KPOINT_Y_P06_1            (ADR_BASE + 0x0114)
++#define    ADR_ADDR_MAP_KPOINT_Y_P06_2            (ADR_BASE + 0x0118)
++#define    ADR_ADDR_MAP_KPOINT_Y_P06_3            (ADR_BASE + 0x011C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P06_4            (ADR_BASE + 0x0120)
++#define    ADR_ADDR_MAP_KPOINT_Y_P06_5            (ADR_BASE + 0x0124)
++#define    ADR_ADDR_MAP_KPOINT_Y_P07_0            (ADR_BASE + 0x0128)
++#define    ADR_ADDR_MAP_KPOINT_Y_P07_1            (ADR_BASE + 0x012C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P07_2            (ADR_BASE + 0x0130)
++#define    ADR_ADDR_MAP_KPOINT_Y_P07_3            (ADR_BASE + 0x0134)
++#define    ADR_ADDR_MAP_KPOINT_Y_P07_4            (ADR_BASE + 0x0138)
++#define    ADR_ADDR_MAP_KPOINT_Y_P07_5            (ADR_BASE + 0x013C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P08_0            (ADR_BASE + 0x0140)
++#define    ADR_ADDR_MAP_KPOINT_Y_P08_1            (ADR_BASE + 0x0144)
++#define    ADR_ADDR_MAP_KPOINT_Y_P08_2            (ADR_BASE + 0x0148)
++#define    ADR_ADDR_MAP_KPOINT_Y_P08_3            (ADR_BASE + 0x014C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P08_4            (ADR_BASE + 0x0150)
++#define    ADR_ADDR_MAP_KPOINT_Y_P08_5            (ADR_BASE + 0x0154)
++#define    ADR_ADDR_MAP_KPOINT_Y_P09_0            (ADR_BASE + 0x0158)
++#define    ADR_ADDR_MAP_KPOINT_Y_P09_1            (ADR_BASE + 0x015C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P09_2            (ADR_BASE + 0x0160)
++#define    ADR_ADDR_MAP_KPOINT_Y_P09_3            (ADR_BASE + 0x0164)
++#define    ADR_ADDR_MAP_KPOINT_Y_P09_4            (ADR_BASE + 0x0168)
++#define    ADR_ADDR_MAP_KPOINT_Y_P09_5            (ADR_BASE + 0x016C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P10_0            (ADR_BASE + 0x0170)
++#define    ADR_ADDR_MAP_KPOINT_Y_P10_1            (ADR_BASE + 0x0174)
++#define    ADR_ADDR_MAP_KPOINT_Y_P10_2            (ADR_BASE + 0x0178)
++#define    ADR_ADDR_MAP_KPOINT_Y_P10_3            (ADR_BASE + 0x017C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P10_4            (ADR_BASE + 0x0180)
++#define    ADR_ADDR_MAP_KPOINT_Y_P10_5            (ADR_BASE + 0x0184)
++#define    ADR_ADDR_MAP_KPOINT_Y_P11_0            (ADR_BASE + 0x0188)
++#define    ADR_ADDR_MAP_KPOINT_Y_P11_1            (ADR_BASE + 0x018C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P11_2            (ADR_BASE + 0x0190)
++#define    ADR_ADDR_MAP_KPOINT_Y_P11_3            (ADR_BASE + 0x0194)
++#define    ADR_ADDR_MAP_KPOINT_Y_P11_4            (ADR_BASE + 0x0198)
++#define    ADR_ADDR_MAP_KPOINT_Y_P11_5            (ADR_BASE + 0x019C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P12_0            (ADR_BASE + 0x01A0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P12_1            (ADR_BASE + 0x01A4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P12_2            (ADR_BASE + 0x01A8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P12_3            (ADR_BASE + 0x01AC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P12_4            (ADR_BASE + 0x01B0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P12_5            (ADR_BASE + 0x01B4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P13_0            (ADR_BASE + 0x01B8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P13_1            (ADR_BASE + 0x01BC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P13_2            (ADR_BASE + 0x01C0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P13_3            (ADR_BASE + 0x01C4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P13_4            (ADR_BASE + 0x01C8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P13_5            (ADR_BASE + 0x01CC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P14_0            (ADR_BASE + 0x01D0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P14_1            (ADR_BASE + 0x01D4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P14_2            (ADR_BASE + 0x01D8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P14_3            (ADR_BASE + 0x01DC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P14_4            (ADR_BASE + 0x01E0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P14_5            (ADR_BASE + 0x01E4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P15_0            (ADR_BASE + 0x01E8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P15_1            (ADR_BASE + 0x01EC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P15_2            (ADR_BASE + 0x01F0)
++#define    ADR_ADDR_MAP_KPOINT_Y_P15_3            (ADR_BASE + 0x01F4)
++#define    ADR_ADDR_MAP_KPOINT_Y_P15_4            (ADR_BASE + 0x01F8)
++#define    ADR_ADDR_MAP_KPOINT_Y_P15_5            (ADR_BASE + 0x01FC)
++#define    ADR_ADDR_MAP_KPOINT_Y_P16_0            (ADR_BASE + 0x0200)
++#define    ADR_ADDR_MAP_KPOINT_Y_P16_1            (ADR_BASE + 0x0204)
++#define    ADR_ADDR_MAP_KPOINT_Y_P16_2            (ADR_BASE + 0x0208)
++#define    ADR_ADDR_MAP_KPOINT_Y_P16_3            (ADR_BASE + 0x020C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P16_4            (ADR_BASE + 0x0210)
++#define    ADR_ADDR_MAP_KPOINT_Y_P16_5            (ADR_BASE + 0x0214)
++#define    ADR_ADDR_MAP_KPOINT_Y_P17_0            (ADR_BASE + 0x0218)
++#define    ADR_ADDR_MAP_KPOINT_Y_P17_1            (ADR_BASE + 0x021C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P17_2            (ADR_BASE + 0x0220)
++#define    ADR_ADDR_MAP_KPOINT_Y_P17_3            (ADR_BASE + 0x0224)
++#define    ADR_ADDR_MAP_KPOINT_Y_P17_4            (ADR_BASE + 0x0228)
++#define    ADR_ADDR_MAP_KPOINT_Y_P17_5            (ADR_BASE + 0x022C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P18_0            (ADR_BASE + 0x0230)
++#define    ADR_ADDR_MAP_KPOINT_Y_P18_1            (ADR_BASE + 0x0234)
++#define    ADR_ADDR_MAP_KPOINT_Y_P18_2            (ADR_BASE + 0x0238)
++#define    ADR_ADDR_MAP_KPOINT_Y_P18_3            (ADR_BASE + 0x023C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P18_4            (ADR_BASE + 0x0240)
++#define    ADR_ADDR_MAP_KPOINT_Y_P18_5            (ADR_BASE + 0x0244)
++#define    ADR_ADDR_MAP_KPOINT_Y_P19_0            (ADR_BASE + 0x0248)
++#define    ADR_ADDR_MAP_KPOINT_Y_P19_1            (ADR_BASE + 0x024C)
++#define    ADR_ADDR_MAP_KPOINT_Y_P19_2            (ADR_BASE + 0x0250)
++#define    ADR_ADDR_MAP_KPOINT_Y_P19_3            (ADR_BASE + 0x0254)
++#define    ADR_ADDR_MAP_KPOINT_Y_P19_4            (ADR_BASE + 0x0258)
++#define    ADR_ADDR_MAP_KPOINT_Y_P19_5            (ADR_BASE + 0x025C)
++#define    ADR_ADDR_WEILUT20_P0                   (ADR_BASE + 0x0260)
++#define    ADR_ADDR_WEILUT20_P1                   (ADR_BASE + 0x0264)
++#define    ADR_ADDR_WEILUT20_P2                   (ADR_BASE + 0x0268)
++#define    ADR_ADDR_WEILUT20_P3                   (ADR_BASE + 0x026C)
++#define    ADR_ADDR_WEILUT20_P4                   (ADR_BASE + 0x0270)
++#define    ADR_ADDR_WEILUT20_P5                   (ADR_BASE + 0x0274)
++#define    ADR_ADDR_WEILUT20_P6                   (ADR_BASE + 0x0278)
++#define    ADR_ADDR_WEILUT20_P7                   (ADR_BASE + 0x027C)
++#define    ADR_ADDR_WEILUT02_P0                   (ADR_BASE + 0x0280)
++#define    ADR_ADDR_WEILUT02_P1                   (ADR_BASE + 0x0284)
++#define    ADR_ADDR_WEILUT02_P2                   (ADR_BASE + 0x0288)
++#define    ADR_ADDR_WEILUT02_P3                   (ADR_BASE + 0x028C)
++#define    ADR_ADDR_WEILUT02_P4                   (ADR_BASE + 0x0290)
++#define    ADR_ADDR_WEILUT02_P5                   (ADR_BASE + 0x0294)
++#define    ADR_ADDR_WEILUT02_P6                   (ADR_BASE + 0x0298)
++#define    ADR_ADDR_WEILUT02_P7                   (ADR_BASE + 0x029C)
++#define    ADR_ADDR_WEILUT12_P0                   (ADR_BASE + 0x02A0)
++#define    ADR_ADDR_WEILUT12_P1                   (ADR_BASE + 0x02A4)
++#define    ADR_ADDR_WEILUT12_P2                   (ADR_BASE + 0x02A8)
++#define    ADR_ADDR_WEILUT12_P3                   (ADR_BASE + 0x02AC)
++#define    ADR_ADDR_WEILUT12_P4                   (ADR_BASE + 0x02B0)
++#define    ADR_ADDR_WEILUT12_P5                   (ADR_BASE + 0x02B4)
++#define    ADR_ADDR_WEILUT12_P6                   (ADR_BASE + 0x02B8)
++#define    ADR_ADDR_WEILUT12_P7                   (ADR_BASE + 0x02BC)
++#define    ADR_ADDR_WEILUT22_P0                   (ADR_BASE + 0x02C0)
++#define    ADR_ADDR_WEILUT22_P1                   (ADR_BASE + 0x02C4)
++#define    ADR_ADDR_WEILUT22_P2                   (ADR_BASE + 0x02C8)
++#define    ADR_ADDR_WEILUT22_P3                   (ADR_BASE + 0x02CC)
++#define    ADR_ADDR_WEILUT22_P4                   (ADR_BASE + 0x02D0)
++#define    ADR_ADDR_WEILUT22_P5                   (ADR_BASE + 0x02D4)
++#define    ADR_ADDR_WEILUT22_P6                   (ADR_BASE + 0x02D8)
++#define    ADR_ADDR_WEILUT22_P7                   (ADR_BASE + 0x02DC)
++#define    ADR_ADDR_WEILUT21_P0                   (ADR_BASE + 0x02E0)
++#define    ADR_ADDR_WEILUT21_P1                   (ADR_BASE + 0x02E4)
++#define    ADR_ADDR_WEILUT21_P2                   (ADR_BASE + 0x02E8)
++#define    ADR_ADDR_WEILUT21_P3                   (ADR_BASE + 0x02EC)
++#define    ADR_ADDR_WEILUT21_P4                   (ADR_BASE + 0x02F0)
++#define    ADR_ADDR_WEILUT21_P5                   (ADR_BASE + 0x02F4)
++#define    ADR_ADDR_WEILUT21_P6                   (ADR_BASE + 0x02F8)
++#define    ADR_ADDR_WEILUT21_P7                   (ADR_BASE + 0x02FC)
++#define    ADR_ADDR_MAP_KPOINT_POW_P0             (ADR_BASE + 0x0300)
++#define    ADR_ADDR_MAP_KPOINT_POW_P1             (ADR_BASE + 0x0304)
++#define    ADR_ADDR_MAP_KPOINT_POW_P2             (ADR_BASE + 0x0308)
++#define    ADR_ADDR_CTC_KPOINT_X_P0               (ADR_BASE + 0x0310)
++#define    ADR_ADDR_CTC_KPOINT_X_P1               (ADR_BASE + 0x0314)
++#define    ADR_ADDR_CON_W_DIS_P00                 (ADR_BASE + 0x0320)
++#define    ADR_ADDR_CON_W_DIS_P01                 (ADR_BASE + 0x0324)
++#define    ADR_ADDR_CON_W_DIS_P02                 (ADR_BASE + 0x0328)
++#define    ADR_ADDR_CON_W_DIS_P03                 (ADR_BASE + 0x032C)
++#define    ADR_ADDR_CON_W_DIS_P04                 (ADR_BASE + 0x0330)
++#define    ADR_ADDR_CON_W_DIS_P05                 (ADR_BASE + 0x0334)
++#define    ADR_ADDR_CON_W_DIS_P06                 (ADR_BASE + 0x0338)
++#define    ADR_ADDR_CON_W_DIS_P07                 (ADR_BASE + 0x033C)
++#define    ADR_ADDR_CON_W_DIS_P08                 (ADR_BASE + 0x0340)
++#define    ADR_ADDR_CON_W_DIS_P09                 (ADR_BASE + 0x0344)
++#define    ADR_ADDR_CON_W_DIS_P10                 (ADR_BASE + 0x0348)
++#define    ADR_ADDR_CON_W_DIS_P11                 (ADR_BASE + 0x034C)
++#define    ADR_ADDR_CON_W_DIS_P12                 (ADR_BASE + 0x0350)
++#define    ADR_ADDR_CON_W_DIS_P13                 (ADR_BASE + 0x0354)
++#define    ADR_ADDR_CON_W_DIS_P14                 (ADR_BASE + 0x0358)
++#define    ADR_ADDR_CON_W_DIS_P15                 (ADR_BASE + 0x035C)
++#define    ADR_ADDR_CON_W_DIS_P16                 (ADR_BASE + 0x0360)
++#define    ADR_ADDR_CON_W_DIS_P17                 (ADR_BASE + 0x0364)
++#define    ADR_ADDR_CON_W_DIS_P18                 (ADR_BASE + 0x0368)
++#define    ADR_ADDR_CON_W_DIS_P19                 (ADR_BASE + 0x036C)
++#define    ADR_ADDR_CON_W_DIS_P20                 (ADR_BASE + 0x0370)
++#define    ADR_ADDR_CON_W_DIS_P21                 (ADR_BASE + 0x0374)
++#define    ADR_ADDR_CON_W_DIS_P22                 (ADR_BASE + 0x0378)
++#define    ADR_ADDR_CON_W_DIS_P23                 (ADR_BASE + 0x037C)
++#define    ADR_ADDR_CON_W_DIS_P24                 (ADR_BASE + 0x0380)
++#define    ADR_ADDR_CON_W_DIS_P25                 (ADR_BASE + 0x0384)
++#define    ADR_ADDR_CON_W_DIS_P26                 (ADR_BASE + 0x0388)
++#define    ADR_ADDR_CON_W_DIS_P27                 (ADR_BASE + 0x038C)
++#define    ADR_ADDR_CON_W_DIS_P28                 (ADR_BASE + 0x0390)
++#define    ADR_ADDR_CON_W_DIS_P29                 (ADR_BASE + 0x0394)
++#define    ADR_ADDR_CON_W_DIS_P30                 (ADR_BASE + 0x0398)
++#define    ADR_ADDR_CON_W_DIS_P31                 (ADR_BASE + 0x039C)
++#define    ADR_ADDR_CTC_KPOINT_MUX_P0             (ADR_BASE + 0x03A0)
++#define    ADR_ADDR_CTC_KPOINT_MUX_P1             (ADR_BASE + 0x03A4)
++#define    ADR_ADDR_CTC_RATIO                     (ADR_BASE + 0x03A8)
++#define    ADR_ADDR_MIN_KPOINT_X_P0               (ADR_BASE + 0x03B0)
++#define    ADR_ADDR_MIN_KPOINT_X_P1               (ADR_BASE + 0x03B4)
++#define    ADR_ADDR_MIN_KPOINT_X_P2               (ADR_BASE + 0x03B8)
++#define    ADR_ADDR_MIN_KPOINT_X_P3               (ADR_BASE + 0x03BC)
++#define    ADR_ADDR_MIN_KPOINT_X_P4               (ADR_BASE + 0x03C0)
++#define    ADR_ADDR_MIN_KPOINT_X_P5               (ADR_BASE + 0x03C4)
++#define    ADR_ADDR_MIN_KPOINT_Y_P0               (ADR_BASE + 0x03C8)
++#define    ADR_ADDR_MIN_KPOINT_Y_P1               (ADR_BASE + 0x03CC)
++#define    ADR_ADDR_MIN_KPOINT_Y_P2               (ADR_BASE + 0x03D0)
++#define    ADR_ADDR_MIN_KPOINT_Y_P3               (ADR_BASE + 0x03D4)
++#define    ADR_ADDR_MIN_KPOINT_Y_P4               (ADR_BASE + 0x03D8)
++#define    ADR_ADDR_MIN_KPOINT_Y_P5               (ADR_BASE + 0x03DC)
++#define    ADR_ADDR_MIN_KPOINT_POW_P0             (ADR_BASE + 0x03E0)
++#define    ADR_ADDR_MIN_KPOINT_POW_P1             (ADR_BASE + 0x03E4)
++#define    ADR_ADDR_MIN_KPOINT_POW_P2             (ADR_BASE + 0x03E8)
++#define    ADR_ADDR_COC_KPOINT_X_P0               (ADR_BASE + 0x03F0)
++#define    ADR_ADDR_COC_KPOINT_X_P1               (ADR_BASE + 0x03F4)
++#define    ADR_ADDR_COC_KPOINT_X_P2               (ADR_BASE + 0x03F8)
++#define    ADR_ADDR_COC_KPOINT_X_P3               (ADR_BASE + 0x03FC)
++#define    ADR_ADDR_COC_KPOINT_X_P4               (ADR_BASE + 0x0400)
++#define    ADR_ADDR_COC_KPOINT_X_P5               (ADR_BASE + 0x0404)
++#define    ADR_ADDR_COC_THRES                     (ADR_BASE + 0x0408)
++#define    ADR_ADDR_COC_STREN                     (ADR_BASE + 0x040C)
++#define    ADR_ADDR_COC_MODE                      (ADR_BASE + 0x0410)
++#define    ADR_ADDR_COC_KPOINT_POW_P0             (ADR_BASE + 0x0414)
++#define    ADR_ADDR_COC_KPOINT_POW_P1             (ADR_BASE + 0x0418)
++#define    ADR_ADDR_COC_KPOINT_POW_P2             (ADR_BASE + 0x041C)
++#define    ADR_ADDR_STAT_BLOCK_DIFF_P_0           (ADR_BASE + 0x0420)
++#define    ADR_ADDR_STAT_BLOCK_DIFF_P_1           (ADR_BASE + 0x0424)
++#define    ADR_ADDR_BANK_ADDR_P0                  (ADR_BASE + 0x0428)
++#define    ADR_ADDR_BANK_ADDR_P1                  (ADR_BASE + 0x042C)
++#define    ADR_ADDR_BANK_ADDR_P2                  (ADR_BASE + 0x0430)
++#define    ADR_ADDR_BANK_ADDR_P3                  (ADR_BASE + 0x0434)
++#define    ADR_ADDR_BANK_NUMBER                   (ADR_BASE + 0x0438)
++#define    ADR_ADDR_FRAME_ADDR                    (ADR_BASE + 0x043C)
++#define    ADR_ADDR_FRAME_ID                      (ADR_BASE + 0x0440)
++#define    ADR_ADDR_FRAME_RATE                    (ADR_BASE + 0x0444)
++#define    ADR_ADDR_SHADOW_CTRL                   (ADR_BASE + 0x0448)
++#define    ADR_ADDR_DEBUG_SIGNAL_0                (ADR_BASE + 0x0450)
++#define    ADR_ADDR_DEBUG_SIGNAL_1                (ADR_BASE + 0x0454)
++#define    ADR_ADDR_DEBUG_SIGNAL_2                (ADR_BASE + 0x0458)
++#define    ADR_ADDR_DEBUG_SIGNAL_3                (ADR_BASE + 0x045C)
++#define    ADR_ADDR_DEBUG_SIGNAL_4                (ADR_BASE + 0x0460)
++#define    ADR_ADDR_DEBUG_SIGNAL_5                (ADR_BASE + 0x0464)
++
++//============================================================
++// IRINT
++//============================================================
++#define    IRINT_ADDR_T_VERSION                   (IRINT_BASE + 0x0000)
++#define    IRINT_ADDR_T_DBG_SEL                   (IRINT_BASE + 0x0004)
++#define    IRINT_ADDR_T_DBG_VALUE                 (IRINT_BASE + 0x0008)
++#define    IRINT_ADDR_DIFF_PAR                    (IRINT_BASE + 0x0010)
++#define    IRINT_ADDR_MIN_PAR                     (IRINT_BASE + 0x0014)
++
++//============================================================
++// DMSC
++//============================================================
++#define    DMSC_ADDR_SYNC                         (DMSC_BASE + 0x0000)
++#define    DMSC_ADDR_G_STD_STREN                  (DMSC_BASE + 0x0004)
++#define    DMSC_ADDR_UU_THRES                     (DMSC_BASE + 0x0008)
++#define    DMSC_ADDR_ALIAS_DIR_DIFF               (DMSC_BASE + 0x000C)
++#define    DMSC_ADDR_WIN5_HV_EDGE_THRES           (DMSC_BASE + 0x0010)
++#define    DMSC_ADDR_HV_EDGE_THRES                (DMSC_BASE + 0x0014)
++#define    DMSC_ADDR_HV_EDGE                      (DMSC_BASE + 0x0020)
++#define    DMSC_ADDR_AA_EDGE_THRES                (DMSC_BASE + 0x0024)
++#define    DMSC_ADDR_AA_EDGE                      (DMSC_BASE + 0x0028)
++#define    DMSC_ADDR_HVAA_EDGE_THRES              (DMSC_BASE + 0x002C)
++#define    DMSC_ADDR_HVAA_EDGE                    (DMSC_BASE + 0x0030)
++#define    DMSC_ADDR_ALIAS_STREN                  (DMSC_BASE + 0x0034)
++#define    DMSC_ADDR_ALIAS_THRES                  (DMSC_BASE + 0x0038)
++#define    DMSC_ADDR_NOR_ALIAS_BLUR               (DMSC_BASE + 0x003C)
++#define    DMSC_ADDR_NOR_UU_WEI_STREN             (DMSC_BASE + 0x0040)
++#define    DMSC_ADDR_SP_D_V2_SIGMA                (DMSC_BASE + 0x0044)
++#define    DMSC_ADDR_SP_D_W_SP_STREN              (DMSC_BASE + 0x0048)
++#define    DMSC_ADDR_SP_D_LL_STREN                (DMSC_BASE + 0x004C)
++#define    DMSC_ADDR_SP_D_LL_THRES                (DMSC_BASE + 0x0050)
++#define    DMSC_ADDR_SP_D_W_LIMIT                 (DMSC_BASE + 0x0054)
++#define    DMSC_ADDR_SP_D_B_LIMIT                 (DMSC_BASE + 0x0058)
++#define    DMSC_ADDR_SP_UD_V2_SIGMA               (DMSC_BASE + 0x005C)
++#define    DMSC_ADDR_SP_UD_W_SP_STREN             (DMSC_BASE + 0x0060)
++#define    DMSC_ADDR_SP_UD_LL_STREN               (DMSC_BASE + 0x0064)
++#define    DMSC_ADDR_SP_UD_LL_THRES               (DMSC_BASE + 0x0068)
++#define    DMSC_ADDR_SP_UD_W_LIMIT                (DMSC_BASE + 0x006C)
++#define    DMSC_ADDR_SP_UD_B_LIMIT                (DMSC_BASE + 0x0070)
++#define    DMSC_ADDR_SP_NOR_ALIAS_THRES           (DMSC_BASE + 0x0074)
++#define    DMSC_ADDR_ALIAS_FUSION_THRES           (DMSC_BASE + 0x0078)
++#define    DMSC_ADDR_ALIAS_DIR_INTP_SP_STREN      (DMSC_BASE + 0x007C)
++#define    DMSC_ADDR_FC_ALIAS_STREN               (DMSC_BASE + 0x0080)
++#define    DMSC_ADDR_FC_ALIAS_THRES               (DMSC_BASE + 0x0084)
++#define    DMSC_ADDR_FC_NOR_SAT_THRES             (DMSC_BASE + 0x0088)
++#define    DMSC_ADDR_FC_TEXT_THRES                (DMSC_BASE + 0x008C)
++#define    DMSC_ADDR_FC_NOR_EDGE_SLOPE            (DMSC_BASE + 0x0090)
++#define    DMSC_ADDR_UU_NP_ARRAY_RG0              (DMSC_BASE + 0x0094)
++#define    DMSC_ADDR_UU_NP_ARRAY_RG1              (DMSC_BASE + 0x0098)
++#define    DMSC_ADDR_UU_NP_ARRAY_RG2              (DMSC_BASE + 0x009C)
++#define    DMSC_ADDR_UU_NP_ARRAY_RG3              (DMSC_BASE + 0x00A0)
++#define    DMSC_ADDR_UU_NP_ARRAY_RG4              (DMSC_BASE + 0x00A4)
++#define    DMSC_ADDR_UU_NP_ARRAY_RG5              (DMSC_BASE + 0x00A8)
++#define    DMSC_ADDR_UU_NP_ARRAY_RG6              (DMSC_BASE + 0x00AC)
++#define    DMSC_ADDR_UU_NP_ARRAY_RG7              (DMSC_BASE + 0x00B0)
++#define    DMSC_ADDR_SP_D_SIGMA_3_NP_ARRAY_RG0    (DMSC_BASE + 0x00B4)
++#define    DMSC_ADDR_SP_D_SIGMA_3_NP_ARRAY_RG1    (DMSC_BASE + 0x00B8)
++#define    DMSC_ADDR_SP_D_SIGMA_3_NP_ARRAY_RG2    (DMSC_BASE + 0x00BC)
++#define    DMSC_ADDR_SP_D_W_WEI_NP_ARRAY_RG0      (DMSC_BASE + 0x00C0)
++#define    DMSC_ADDR_SP_D_W_WEI_NP_ARRAY_RG1      (DMSC_BASE + 0x00C4)
++#define    DMSC_ADDR_SP_D_W_WEI_NP_ARRAY_RG2      (DMSC_BASE + 0x00C8)
++#define    DMSC_ADDR_SP_D_W_WEI_NP_ARRAY_RG3      (DMSC_BASE + 0x00CC)
++#define    DMSC_ADDR_SP_D_B_WEI_NP_ARRAY_RG0      (DMSC_BASE + 0x00D0)
++#define    DMSC_ADDR_SP_D_B_WEI_NP_ARRAY_RG1      (DMSC_BASE + 0x00D4)
++#define    DMSC_ADDR_SP_D_B_WEI_NP_ARRAY_RG2      (DMSC_BASE + 0x00D8)
++#define    DMSC_ADDR_SP_D_B_WEI_NP_ARRAY_RG3      (DMSC_BASE + 0x00DC)
++#define    DMSC_ADDR_SP_UD_W_WEI_NP_ARRAY_RG0     (DMSC_BASE + 0x00E0)
++#define    DMSC_ADDR_SP_UD_W_WEI_NP_ARRAY_RG1     (DMSC_BASE + 0x00E4)
++#define    DMSC_ADDR_SP_UD_W_WEI_NP_ARRAY_RG2     (DMSC_BASE + 0x00E8)
++#define    DMSC_ADDR_SP_UD_W_WEI_NP_ARRAY_RG3     (DMSC_BASE + 0x00EC)
++#define    DMSC_ADDR_SP_UD_B_WEI_NP_ARRAY_RG0     (DMSC_BASE + 0x00F0)
++#define    DMSC_ADDR_SP_UD_B_WEI_NP_ARRAY_RG1     (DMSC_BASE + 0x00F4)
++#define    DMSC_ADDR_SP_UD_B_WEI_NP_ARRAY_RG2     (DMSC_BASE + 0x00F8)
++#define    DMSC_ADDR_SP_UD_B_WEI_NP_ARRAY_RG3     (DMSC_BASE + 0x00FC)
++#define    DMSC_ADDR_OUT_OPT                      (DMSC_BASE + 0x0100)
++#define    DMSC_ADDR_SP_DEBUG_REG_0               (DMSC_BASE + 0x0104)
++#define    DMSC_ADDR_SP_DEBUG_REG_1               (DMSC_BASE + 0x0108)
++#define    DMSC_ADDR_FC_TEXT_2_STREN              (DMSC_BASE + 0x010C)
++#define    DMSC_ADDR_FC_TEXT_2_THRES              (DMSC_BASE + 0x0110)
++#define    DMSC_ADDR_FC_THRES_H_1                 (DMSC_BASE + 0x0114)
++#define    DMSC_ADDR_FC_THRES_H_2                 (DMSC_BASE + 0x0118)
++
++//============================================================
++// CCM
++//============================================================
++#define    CCM_ADDR_REG_CTRL                      (CCM_BASE + 0x0000)
++#define    CCM_ADDR_CCM_RRRG                      (CCM_BASE + 0x0004)
++#define    CCM_ADDR_CCM_RBGR                      (CCM_BASE + 0x0008)
++#define    CCM_ADDR_CCM_GGGB                      (CCM_BASE + 0x000c)
++#define    CCM_ADDR_CCM_BRBG                      (CCM_BASE + 0x0010)
++#define    CCM_ADDR_CCM_BB                        (CCM_BASE + 0x0014)
++#define    CCM_ADDR_DP_CFG                        (CCM_BASE + 0x0018)
++#define    CCM_ADDR_DP_SLOP                       (CCM_BASE + 0x001c)
++#define    CCM_ADDR_SAT_THRES                     (CCM_BASE + 0x0020)
++
++//===============================================
++// DEFOG
++//===============================================
++#define    DEFOG_ADDR_BLOCK_COORD_M_01_00         (DEFOG_BASE + 0x0000)
++#define    DEFOG_ADDR_BLOCK_COORD_M_03_02         (DEFOG_BASE + 0x0004)
++#define    DEFOG_ADDR_BLOCK_COORD_M_05_04         (DEFOG_BASE + 0x0008)
++#define    DEFOG_ADDR_BLOCK_COORD_M_07_06         (DEFOG_BASE + 0x000C)
++#define    DEFOG_ADDR_BLOCK_COORD_M_09_08         (DEFOG_BASE + 0x0010)
++#define    DEFOG_ADDR_BLOCK_COORD_M____10         (DEFOG_BASE + 0x0014)
++#define    DEFOG_ADDR_BLOCK_COORD_N_01_00         (DEFOG_BASE + 0x0020)
++#define    DEFOG_ADDR_BLOCK_COORD_N_03_02         (DEFOG_BASE + 0x0024)
++#define    DEFOG_ADDR_BLOCK_COORD_N_05_04         (DEFOG_BASE + 0x0028)
++#define    DEFOG_ADDR_BLOCK_COORD_N_07_06         (DEFOG_BASE + 0x002C)
++#define    DEFOG_ADDR_BLOCK_COORD_N_09_08         (DEFOG_BASE + 0x0030)
++#define    DEFOG_ADDR_BLOCK_COORD_N_11_10         (DEFOG_BASE + 0x0034)
++#define    DEFOG_ADDR_BLOCK_COORD_N_13_12         (DEFOG_BASE + 0x0038)
++#define    DEFOG_ADDR_BLOCK_COORD_N_15_14         (DEFOG_BASE + 0x003C)
++#define    DEFOG_ADDR_BLOCK_COORD_N_17_16         (DEFOG_BASE + 0x0040)
++#define    DEFOG_ADDR_BLOCK_COORD_N_19_18         (DEFOG_BASE + 0x0044)
++#define    DEFOG_ADDR_BLOCK_COORD_N____20         (DEFOG_BASE + 0x0048)
++#define    DEFOG_ADDR_CT3X3_DIS_01_00             (DEFOG_BASE + 0x0050)
++#define    DEFOG_ADDR_CT3X3_DIS_03_02             (DEFOG_BASE + 0x0054)
++#define    DEFOG_ADDR_CT3X3_DIS_05_04             (DEFOG_BASE + 0x0058)
++#define    DEFOG_ADDR_CT3X3_DIS_07_06             (DEFOG_BASE + 0x005C)
++#define    DEFOG_ADDR_CT3X3_DIS_09_08             (DEFOG_BASE + 0x0060)
++#define    DEFOG_ADDR_CT3X3_DIS_11_10             (DEFOG_BASE + 0x0064)
++#define    DEFOG_ADDR_CT3X3_DIS_13_12             (DEFOG_BASE + 0x0068)
++#define    DEFOG_ADDR_CT3X3_DIS_15_14             (DEFOG_BASE + 0x006C)
++#define    DEFOG_ADDR_CT3X3_DIS_17_16             (DEFOG_BASE + 0x0070)
++#define    DEFOG_ADDR_CT3X3_DIS_19_18             (DEFOG_BASE + 0x0074)
++#define    DEFOG_ADDR_CT3X3_DIS_21_20             (DEFOG_BASE + 0x0078)
++#define    DEFOG_ADDR_CT3X3_DIS_23_22             (DEFOG_BASE + 0x007C)
++#define    DEFOG_ADDR_CT5X5_DIS_01_00             (DEFOG_BASE + 0x0080)
++#define    DEFOG_ADDR_CT5X5_DIS_03_02             (DEFOG_BASE + 0x0084)
++#define    DEFOG_ADDR_CT5X5_DIS_05_04             (DEFOG_BASE + 0x0088)
++#define    DEFOG_ADDR_CT5X5_DIS_07_06             (DEFOG_BASE + 0x008C)
++#define    DEFOG_ADDR_CT5X5_DIS_09_08             (DEFOG_BASE + 0x0090)
++#define    DEFOG_ADDR_CT5X5_DIS_11_10             (DEFOG_BASE + 0x0094)
++#define    DEFOG_ADDR_CT5X5_DIS_13_12             (DEFOG_BASE + 0x0098)
++#define    DEFOG_ADDR_CT5X5_DIS_15_14             (DEFOG_BASE + 0x009C)
++#define    DEFOG_ADDR_CT5X5_DIS_17_16             (DEFOG_BASE + 0x00A0)
++#define    DEFOG_ADDR_CT5X5_DIS_19_18             (DEFOG_BASE + 0x00A4)
++#define    DEFOG_ADDR_CT5X5_DIS_21_20             (DEFOG_BASE + 0x00A8)
++#define    DEFOG_ADDR_CT5X5_DIS_23_22             (DEFOG_BASE + 0x00AC)
++#define    DEFOG_ADDR_CT5X5_DIS_25_24             (DEFOG_BASE + 0x00B0)
++#define    DEFOG_ADDR_CT5X5_DIS_27_26             (DEFOG_BASE + 0x00B4)
++#define    DEFOG_ADDR_CT5X5_DIS_29_28             (DEFOG_BASE + 0x00B8)
++#define    DEFOG_ADDR_CT5X5_DIS_31_30             (DEFOG_BASE + 0x00BC)
++#define    DEFOG_ADDR_WEIGHTLUT02_05_00           (DEFOG_BASE + 0x00C0)
++#define    DEFOG_ADDR_WEIGHTLUT02_11_06           (DEFOG_BASE + 0x00C4)
++#define    DEFOG_ADDR_WEIGHTLUT02_17_12           (DEFOG_BASE + 0x00C8)
++#define    DEFOG_ADDR_WEIGHTLUT02_23_18           (DEFOG_BASE + 0x00CC)
++#define    DEFOG_ADDR_WEIGHTLUT02_29_24           (DEFOG_BASE + 0x00D0)
++#define    DEFOG_ADDR_WEIGHTLUT02_31_30           (DEFOG_BASE + 0x00D4)
++#define    DEFOG_ADDR_WEIGHTLUT20_05_00           (DEFOG_BASE + 0x00E0)
++#define    DEFOG_ADDR_WEIGHTLUT20_11_06           (DEFOG_BASE + 0x00E4)
++#define    DEFOG_ADDR_WEIGHTLUT20_17_12           (DEFOG_BASE + 0x00E8)
++#define    DEFOG_ADDR_WEIGHTLUT20_23_18           (DEFOG_BASE + 0x00EC)
++#define    DEFOG_ADDR_WEIGHTLUT20_29_24           (DEFOG_BASE + 0x00F0)
++#define    DEFOG_ADDR_WEIGHTLUT20_31_30           (DEFOG_BASE + 0x00F4)
++#define    DEFOG_ADDR_WEIGHTLUT21_05_00           (DEFOG_BASE + 0x0100)
++#define    DEFOG_ADDR_WEIGHTLUT21_11_06           (DEFOG_BASE + 0x0104)
++#define    DEFOG_ADDR_WEIGHTLUT21_17_12           (DEFOG_BASE + 0x0108)
++#define    DEFOG_ADDR_WEIGHTLUT21_23_18           (DEFOG_BASE + 0x010C)
++#define    DEFOG_ADDR_WEIGHTLUT21_29_24           (DEFOG_BASE + 0x0110)
++#define    DEFOG_ADDR_WEIGHTLUT21_31_30           (DEFOG_BASE + 0x0114)
++#define    DEFOG_ADDR_WEIGHTLUT12_05_00           (DEFOG_BASE + 0x0120)
++#define    DEFOG_ADDR_WEIGHTLUT12_11_06           (DEFOG_BASE + 0x0124)
++#define    DEFOG_ADDR_WEIGHTLUT12_17_12           (DEFOG_BASE + 0x0128)
++#define    DEFOG_ADDR_WEIGHTLUT12_23_18           (DEFOG_BASE + 0x012C)
++#define    DEFOG_ADDR_WEIGHTLUT12_29_24           (DEFOG_BASE + 0x0130)
++#define    DEFOG_ADDR_WEIGHTLUT12_31_30           (DEFOG_BASE + 0x0134)
++#define    DEFOG_ADDR_WEIGHTLUT22_05_00           (DEFOG_BASE + 0x0140)
++#define    DEFOG_ADDR_WEIGHTLUT22_11_06           (DEFOG_BASE + 0x0144)
++#define    DEFOG_ADDR_WEIGHTLUT22_17_12           (DEFOG_BASE + 0x0148)
++#define    DEFOG_ADDR_WEIGHTLUT22_23_18           (DEFOG_BASE + 0x014C)
++#define    DEFOG_ADDR_WEIGHTLUT22_29_24           (DEFOG_BASE + 0x0150)
++#define    DEFOG_ADDR_WEIGHTLUT22_31_30           (DEFOG_BASE + 0x0154)
++#define    DEFOG_ADDR_BANK_BUFF_NUM               (DEFOG_BASE + 0x0160)
++#define    DEFOG_ADDR_BANK_ADDR_0                 (DEFOG_BASE + 0x0164)
++#define    DEFOG_ADDR_BANK_ADDR_1                 (DEFOG_BASE + 0x0168)
++#define    DEFOG_ADDR_BANK_ADDR_2                 (DEFOG_BASE + 0x016C)
++#define    DEFOG_ADDR_BANK_ADDR_3                 (DEFOG_BASE + 0x0170)
++#define    DEFOG_ADDR_PARA                        (DEFOG_BASE + 0x0180)
++#define    DEFOG_ADDR_CLOR_CTRL_X3210             (DEFOG_BASE + 0x0190)
++#define    DEFOG_ADDR_CLOR_CTRL_Y3210             (DEFOG_BASE + 0x0194)
++#define    DEFOG_ADDR_CLOR_CTRL_XY44              (DEFOG_BASE + 0x0198)
++#define    DEFOG_ADDR_CLOR_CTRL_POW3210           (DEFOG_BASE + 0x019C)
++#define    DEFOG_ADDR_TRANS_DARK_CTRL_X3210       (DEFOG_BASE + 0x01A0)
++#define    DEFOG_ADDR_TRANS_DARK_CTRL_Y3210       (DEFOG_BASE + 0x01A4)
++#define    DEFOG_ADDR_TRANS_DARK_CTRL_XY44        (DEFOG_BASE + 0x01A8)
++#define    DEFOG_ADDR_TRANS_DARK_CTRL_POW3210     (DEFOG_BASE + 0x01AC)
++#define    DEFOG_ADDR_OVEREXPO_WGT_X3210          (DEFOG_BASE + 0x01B0)
++#define    DEFOG_ADDR_OVEREXPO_WGT_Y3210          (DEFOG_BASE + 0x01B4)
++#define    DEFOG_ADDR_OVEREXPO_WGT_POW210         (DEFOG_BASE + 0x01B8)
++#define    DEFOG_ADDR_DARKSPC_WGT_X3210           (DEFOG_BASE + 0x01C0)
++#define    DEFOG_ADDR_DARKSPC_WGT_Y3210           (DEFOG_BASE + 0x01C4)
++#define    DEFOG_ADDR_DARKSPC_WGT_POW210          (DEFOG_BASE + 0x01C8)
++#define    DEFOG_ADDR_FRAME_RATE                  (DEFOG_BASE + 0x01D0)
++#define    DEFOG_ADDR_CTRL                        (DEFOG_BASE + 0x01E0)
++#define    DEFOG_ADDR_FRAME_ADDR                  (DEFOG_BASE + 0x0200)
++#define    DEFOG_ADDR_FRAME_ID                    (DEFOG_BASE + 0x0204)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_0              (DEFOG_BASE + 0x0208)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_1              (DEFOG_BASE + 0x020C)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_2              (DEFOG_BASE + 0x0210)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_3              (DEFOG_BASE + 0x0214)
++#define    DEFOG_ADDR_DEBUG_SIGNAL_4              (DEFOG_BASE + 0x0218)
++#define    DEFOG_ADDR_BLOCK_CFG_SEL		  (DEFOG_BASE + 0x0220)
++#define	   DEFOG_ADDR_BLOCK_CFG_BASE		  (DEFOG_BASE + 0x0224)
++
++//============================================================
++// CSC
++//============================================================
++#define    CSC_ADDR_CTRL                          (CSC_BASE + 0x0000)
++#define    CSC_ADDR_SUB                           (CSC_BASE + 0x0004)
++#define    CSC_ADDR_PAR_0                         (CSC_BASE + 0x0010)
++#define    CSC_ADDR_PAR_1                         (CSC_BASE + 0x0014)
++#define    CSC_ADDR_PAR_2                         (CSC_BASE + 0x0018)
++#define    CSC_ADDR_OFF_SET                       (CSC_BASE + 0x0020)
++#define    CSC_ADDR_CLIP                          (CSC_BASE + 0x0030)
++
++//============================================================
++// CLM
++//============================================================
++#define    CLM_ADDR_REG_CTRL                      (CLM_BASE + 0x0000)
++#define    CLM_ADDR_LUT_SHIFT                     (CLM_BASE + 0x0004)
++#define    CLM_ADDR_CSC_RB                        (CLM_BASE + 0x0008)
++#define    CLM_ADDR_CSC_G                         (CLM_BASE + 0x000c)
++#define    CLM_ADDR_CSC_U                         (CLM_BASE + 0x0010)
++#define    CLM_ADDR_CSC_V                         (CLM_BASE + 0x0014)
++#define    CLM_ADDR_CSC_Y                         (CLM_BASE + 0x0018)
++#define    CLM_ADDR_CA_S_THRES                    (CLM_BASE + 0x001c)
++#define    CLM_ADDR_CA_S_SLOP                     (CLM_BASE + 0x0020)
++#define    CLM_ADDR_CA_V_THRES                    (CLM_BASE + 0x0024)
++#define    CLM_ADDR_CA_V_SLOP                     (CLM_BASE + 0x0028)
++#define    CLM_ADDR_DEBUG0                        (CLM_BASE + 0x002c)
++
++//============================================================
++// Sharpen
++//============================================================
++#define    SHARPEN_ADDR_SYNC                  (SP_BASE + 0x0000)
++#define    SHARPEN_ADDR_STD_DIV_OPT           (SP_BASE + 0x0004)
++#define    SHARPEN_ADDR_V2_SIGMA              (SP_BASE + 0x0008)
++#define    SHARPEN_ADDR_W_WEI_SEG_OPT         (SP_BASE + 0x000C)
++#define    SHARPEN_ADDR_STREN                 (SP_BASE + 0x0010)
++#define    SHARPEN_ADDR_THRES                 (SP_BASE + 0x0014)
++#define    SHARPEN_ADDR_UU_SLOPE              (SP_BASE + 0x0018)
++#define    SHARPEN_ADDR_UU_NP_ARRAY_RG0       (SP_BASE + 0x001C)
++#define    SHARPEN_ADDR_UU_NP_ARRAY_RG1       (SP_BASE + 0x0020)
++#define    SHARPEN_ADDR_UU_NP_ARRAY_RG2       (SP_BASE + 0x0024)
++#define    SHARPEN_ADDR_UU_NP_ARRAY_RG3       (SP_BASE + 0x0028)
++#define    SHARPEN_ADDR_V1_SIGMA_NP_ARRAY_RG0 (SP_BASE + 0x002C)
++#define    SHARPEN_ADDR_V1_SIGMA_NP_ARRAY_RG1 (SP_BASE + 0x0030)
++#define    SHARPEN_ADDR_V1_SIGMA_NP_ARRAY_RG2 (SP_BASE + 0x0034)
++#define    SHARPEN_ADDR_W_WEI_NP_ARRAY_RG0    (SP_BASE + 0x0038)
++#define    SHARPEN_ADDR_W_WEI_NP_ARRAY_RG1    (SP_BASE + 0x003C)
++#define    SHARPEN_ADDR_W_WEI_NP_ARRAY_RG2    (SP_BASE + 0x0040)
++#define    SHARPEN_ADDR_W_WEI_NP_ARRAY_RG3    (SP_BASE + 0x0044)
++#define    SHARPEN_ADDR_B_WEI_NP_ARRAY_RG0    (SP_BASE + 0x0048)
++#define    SHARPEN_ADDR_B_WEI_NP_ARRAY_RG1    (SP_BASE + 0x004C)
++#define    SHARPEN_ADDR_B_WEI_NP_ARRAY_RG2    (SP_BASE + 0x0050)
++#define    SHARPEN_ADDR_B_WEI_NP_ARRAY_RG3    (SP_BASE + 0x0054)
++
++//============================================================
++// MDNS
++//============================================================
++#define    MDNS_ADDR_T_VERSION                    (MDNS_BASE + 0x0000)
++#define    MDNS_ADDR_REG_CTRL                     (MDNS_BASE + 0x0004)
++#define    MDNS_ADDR_DBG_SEL                      (MDNS_BASE + 0x0008)
++#define    MDNS_ADDR_DBG_VALUE                    (MDNS_BASE + 0x000C)
++#define    MDNS_ADDR_Y_REF_BASE_ADDR              (MDNS_BASE + 0x0010)
++#define    MDNS_ADDR_Y_REF_STRIDE                 (MDNS_BASE + 0x0014)
++#define    MDNS_ADDR_Y_REF_FRM_SIZE               (MDNS_BASE + 0x0018)
++#define    MDNS_ADDR_Y_REF_FRM_NUM                (MDNS_BASE + 0x001C)
++#define    MDNS_ADDR_UV_REF_BASE_ADDR             (MDNS_BASE + 0x0020)
++#define    MDNS_ADDR_UV_REF_STRIDE                (MDNS_BASE + 0x0024)
++#define    MDNS_ADDR_UV_REF_FRM_SIZE              (MDNS_BASE + 0x0028)
++#define    MDNS_ADDR_UV_REF_FRM_NUM               (MDNS_BASE + 0x002C)
++#define    MDNS_ADDR_STA_BASE_ADDR                (MDNS_BASE + 0x0030)
++#define    MDNS_ADDR_STA_STRIDE                   (MDNS_BASE + 0x0034)
++#define    MDNS_ADDR_STA_FRM_SIZE                 (MDNS_BASE + 0x0038)
++#define    MDNS_ADDR_STA_FRM_NUM                  (MDNS_BASE + 0x003C)
++#define    MDNS_ADDR_PBT_BASE_ADDR                (MDNS_BASE + 0x0040)
++#define    MDNS_ADDR_PBT_STRIDE                   (MDNS_BASE + 0x0044)
++#define    MDNS_ADDR_PBT_FRM_SIZE                 (MDNS_BASE + 0x0048)
++#define    MDNS_ADDR_PBT_FRM_NUM                  (MDNS_BASE + 0x004C)
++#define    MDNS_ADDR_T_FRM_NUM                    (MDNS_BASE + 0x0050)
++#define    MDNS_ADDR_T_TOP_FUN                    (MDNS_BASE + 0x0060)
++#define    MDNS_ADDR_STA_OVER_CFG                 (MDNS_BASE + 0x0070)
++#define    MDNS_ADDR_STA_WIN_CFG                  (MDNS_BASE + 0x0074)
++#define    MDNS_ADDR_STA_BLK_SIZE                 (MDNS_BASE + 0x0078)
++#define    MDNS_ADDR_STA_BLK_NUM                  (MDNS_BASE + 0x007C)
++#define    MDNS_ADDR_STA_MAX_NUM                  (MDNS_BASE + 0x0080)
++#define    MDNS_ADDR_STA_DIFF_THRES               (MDNS_BASE + 0x0084)
++#define    MDNS_ADDR_STA_MV_NUM_THRES00           (MDNS_BASE + 0x0090)
++#define    MDNS_ADDR_STA_MV_NUM_THRES01           (MDNS_BASE + 0x0094)
++#define    MDNS_ADDR_STA_MV_NUM_THRES10           (MDNS_BASE + 0x0098)
++#define    MDNS_ADDR_STA_MV_NUM_THRES11           (MDNS_BASE + 0x009C)
++#define    MDNS_ADDR_PBT_START_POINT              (MDNS_BASE + 0x00A0)
++#define    MDNS_ADDR_PBT_WIN_SIZE                 (MDNS_BASE + 0x00A4)
++#define    MDNS_ADDR_PBT_OVER_CFG                 (MDNS_BASE + 0x00B0)
++#define    MDNS_ADDR_PBT_WIN_CFG                  (MDNS_BASE + 0x00B4)
++#define    MDNS_ADDR_PBT_BLK_SIZE                 (MDNS_BASE + 0x00B8)
++#define    MDNS_ADDR_PBT_BLK_NUM                  (MDNS_BASE + 0x00BC)
++#define    MDNS_ADDR_PBT_MAX_NUM                  (MDNS_BASE + 0x00C0)
++#define    MDNS_ADDR_PBT_DIFF_THRES               (MDNS_BASE + 0x00C4)
++#define    MDNS_ADDR_PBT_MV_NUM_THRES00           (MDNS_BASE + 0x00D0)
++#define    MDNS_ADDR_PBT_MV_NUM_THRES01           (MDNS_BASE + 0x00D4)
++#define    MDNS_ADDR_PBT_MV_NUM_THRES10           (MDNS_BASE + 0x00D8)
++#define    MDNS_ADDR_PBT_MV_NUM_THRES11           (MDNS_BASE + 0x00DC)
++#define    MDNS_ADDR_Y_CUT_VALUE                  (MDNS_BASE + 0x00E0)
++#define    MDNS_ADDR_Y_EDGE_PAR                   (MDNS_BASE + 0x00E4)
++#define    MDNS_ADDR_Y_BI_PAR0                    (MDNS_BASE + 0x00E8)
++#define    MDNS_ADDR_Y_BI_PAR1                    (MDNS_BASE + 0x00EC)
++#define    MDNS_ADDR_Y_TCA_PAR                    (MDNS_BASE + 0x00F0)
++#define    MDNS_ADDR_Y_TEA_T_PAR0                 (MDNS_BASE + 0x00F4)
++#define    MDNS_ADDR_Y_TEA_T_PAR1                 (MDNS_BASE + 0x00F8)
++#define    MDNS_ADDR_Y_TEA_V_PAR0                 (MDNS_BASE + 0x00FC)
++#define    MDNS_ADDR_Y_TEA_V_PAR1                 (MDNS_BASE + 0x0100)
++#define    MDNS_ADDR_Y_TEA_W_PAR0                 (MDNS_BASE + 0x0104)
++#define    MDNS_ADDR_Y_TEA_W_PAR1                 (MDNS_BASE + 0x0108)
++#define    MDNS_ADDR_Y_TLA_WIN_OPT                (MDNS_BASE + 0x010C)
++#define    MDNS_ADDR_Y_TLA_T_PAR0                 (MDNS_BASE + 0x0110)
++#define    MDNS_ADDR_Y_TLA_T_PAR1                 (MDNS_BASE + 0x0114)
++#define    MDNS_ADDR_Y_TLA_T_PAR2                 (MDNS_BASE + 0x0118)
++#define    MDNS_ADDR_Y_TLA_T_PAR3                 (MDNS_BASE + 0x011C)
++#define    MDNS_ADDR_Y_TLA_V_PAR0                 (MDNS_BASE + 0x0120)
++#define    MDNS_ADDR_Y_TLA_V_PAR1                 (MDNS_BASE + 0x0124)
++#define    MDNS_ADDR_Y_TLA_V_PAR2                 (MDNS_BASE + 0x0128)
++#define    MDNS_ADDR_Y_TLA_V_PAR3                 (MDNS_BASE + 0x012C)
++#define    MDNS_ADDR_Y_TLA_W_PAR0                 (MDNS_BASE + 0x0130)
++#define    MDNS_ADDR_Y_TLA_W_PAR1                 (MDNS_BASE + 0x0134)
++#define    MDNS_ADDR_Y_TLA_W_PAR2                 (MDNS_BASE + 0x0138)
++#define    MDNS_ADDR_Y_TLA_W_PAR3                 (MDNS_BASE + 0x013C)
++#define    MDNS_ADDR_Y_SAD_CFG                    (MDNS_BASE + 0x0140)
++#define    MDNS_ADDR_Y_STA_WEI_PAR0               (MDNS_BASE + 0x0150)
++#define    MDNS_ADDR_Y_STA_WEI_PAR1               (MDNS_BASE + 0x0154)
++#define    MDNS_ADDR_Y_STA_WEI_PAR2               (MDNS_BASE + 0x0158)
++#define    MDNS_ADDR_Y_STA_WEI_PAR3               (MDNS_BASE + 0x015C)
++#define    MDNS_ADDR_Y_STA_WEI_PAR4               (MDNS_BASE + 0x0160)
++#define    MDNS_ADDR_Y_STA_WEI_PAR5               (MDNS_BASE + 0x0164)
++#define    MDNS_ADDR_Y_STA_WEI_PAR6               (MDNS_BASE + 0x0168)
++#define    MDNS_ADDR_Y_STA_WEI_PAR7               (MDNS_BASE + 0x016C)
++#define    MDNS_ADDR_Y_STA_WEI_PAR8               (MDNS_BASE + 0x0170)
++#define    MDNS_ADDR_Y_STA_WEI_PAR9               (MDNS_BASE + 0x0174)
++#define    MDNS_ADDR_Y_STA_WEI_PARa               (MDNS_BASE + 0x0178)
++#define    MDNS_ADDR_Y_STA_WEI_PARb               (MDNS_BASE + 0x017C)
++#define    MDNS_ADDR_Y_STA_WEI_PARc               (MDNS_BASE + 0x0180)
++#define    MDNS_ADDR_Y_STA_WEI_PARd               (MDNS_BASE + 0x0184)
++#define    MDNS_ADDR_Y_STA_WEI_PARe               (MDNS_BASE + 0x0188)
++#define    MDNS_ADDR_Y_STA_WEI_PARf               (MDNS_BASE + 0x018C)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR0               (MDNS_BASE + 0x0190)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR1               (MDNS_BASE + 0x0194)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR2               (MDNS_BASE + 0x0198)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR3               (MDNS_BASE + 0x019C)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR4               (MDNS_BASE + 0x01A0)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR5               (MDNS_BASE + 0x01A4)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR6               (MDNS_BASE + 0x01A8)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR7               (MDNS_BASE + 0x01AC)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR8               (MDNS_BASE + 0x01B0)
++#define    MDNS_ADDR_Y_PBT_WEI_PAR9               (MDNS_BASE + 0x01B4)
++#define    MDNS_ADDR_Y_PBT_WEI_PARa               (MDNS_BASE + 0x01B8)
++#define    MDNS_ADDR_Y_PBT_WEI_PARb               (MDNS_BASE + 0x01BC)
++#define    MDNS_ADDR_Y_PBT_WEI_PARc               (MDNS_BASE + 0x01C0)
++#define    MDNS_ADDR_Y_PBT_WEI_PARd               (MDNS_BASE + 0x01C4)
++#define    MDNS_ADDR_Y_PBT_WEI_PARe               (MDNS_BASE + 0x01C8)
++#define    MDNS_ADDR_Y_PBT_WEI_PARf               (MDNS_BASE + 0x01CC)
++#define    MDNS_ADDR_Y_WSA_S_PAR                  (MDNS_BASE + 0x01D0)
++#define    MDNS_ADDR_Y_WSA_M_PAR                  (MDNS_BASE + 0x01D4)
++#define    MDNS_ADDR_Y_WFA_PAR                    (MDNS_BASE + 0x01D8)
++#define    MDNS_ADDR_Y_REF_WEI_LMT                (MDNS_BASE + 0x01DC)
++#define    MDNS_ADDR_Y_REF_WEI_SGM_X_PAR0         (MDNS_BASE + 0x01E0)
++#define    MDNS_ADDR_Y_REF_WEI_SGM_X_PAR1         (MDNS_BASE + 0x01E4)
++#define    MDNS_ADDR_Y_REF_WEI_SGM_X_PAR2         (MDNS_BASE + 0x01E8)
++#define    MDNS_ADDR_Y_REF_WEI_SGM_Y_PAR0         (MDNS_BASE + 0x01EC)
++#define    MDNS_ADDR_Y_REF_WEI_SGM_Y_PAR1         (MDNS_BASE + 0x01F0)
++#define    MDNS_ADDR_Y_REF_WEI_SGM_S_PAR0         (MDNS_BASE + 0x01F4)
++#define    MDNS_ADDR_Y_REF_WEI_SGM_S_PAR1         (MDNS_BASE + 0x01F8)
++#define    MDNS_ADDR_Y_FS_MV_JUDGE_THRES          (MDNS_BASE + 0x01FC)
++#define    MDNS_ADDR_Y_FS_S_CUR_SHP_WIN_OPT       (MDNS_BASE + 0x0200)
++#define    MDNS_ADDR_Y_FS_S_CUR_SHP_STREN_P0      (MDNS_BASE + 0x0204)
++#define    MDNS_ADDR_Y_FS_S_CUR_SHP_STREN_P1      (MDNS_BASE + 0x0208)
++#define    MDNS_ADDR_Y_FS_S_CUR_SHP_STREN_P2      (MDNS_BASE + 0x020C)
++#define    MDNS_ADDR_Y_FS_S_CUR_SHP_STREN_P3      (MDNS_BASE + 0x0210)
++#define    MDNS_ADDR_Y_FS_S_REF_SHP_WIN_OPT       (MDNS_BASE + 0x0214)
++#define    MDNS_ADDR_Y_FS_S_REF_SHP_STREN_P0      (MDNS_BASE + 0x0218)
++#define    MDNS_ADDR_Y_FS_S_REF_SHP_STREN_P1      (MDNS_BASE + 0x021C)
++#define    MDNS_ADDR_Y_FS_S_REF_SHP_STREN_P2      (MDNS_BASE + 0x0220)
++#define    MDNS_ADDR_Y_FS_S_REF_SHP_STREN_P3      (MDNS_BASE + 0x0224)
++#define    MDNS_ADDR_Y_FS_S_SHP_WEI               (MDNS_BASE + 0x0228)
++#define    MDNS_ADDR_Y_FS_M_CUR_SHP_WIN_OPT       (MDNS_BASE + 0x022C)
++#define    MDNS_ADDR_Y_FS_M_CUR_SHP_STREN_P0      (MDNS_BASE + 0x0230)
++#define    MDNS_ADDR_Y_FS_M_CUR_SHP_STREN_P1      (MDNS_BASE + 0x0234)
++#define    MDNS_ADDR_Y_FS_M_CUR_SHP_STREN_P2      (MDNS_BASE + 0x0238)
++#define    MDNS_ADDR_Y_FS_M_CUR_SHP_STREN_P3      (MDNS_BASE + 0x023C)
++#define    MDNS_ADDR_Y_FS_M_REF_SHP_WIN_OPT       (MDNS_BASE + 0x0240)
++#define    MDNS_ADDR_Y_FS_M_REF_SHP_STREN_P0      (MDNS_BASE + 0x0244)
++#define    MDNS_ADDR_Y_FS_M_REF_SHP_STREN_P1      (MDNS_BASE + 0x0248)
++#define    MDNS_ADDR_Y_FS_M_REF_SHP_STREN_P2      (MDNS_BASE + 0x024C)
++#define    MDNS_ADDR_Y_FS_M_REF_SHP_STREN_P3      (MDNS_BASE + 0x0250)
++#define    MDNS_ADDR_Y_FS_M_SHP_WEI               (MDNS_BASE + 0x0254)
++#define    MDNS_ADDR_Y_FS_SHP_CUR_STA_WEI_P0      (MDNS_BASE + 0x0258)
++#define    MDNS_ADDR_Y_FS_SHP_CUR_STA_WEI_P1      (MDNS_BASE + 0x025C)
++#define    MDNS_ADDR_Y_FS_SHP_REF_STA_WEI_P0      (MDNS_BASE + 0x0260)
++#define    MDNS_ADDR_Y_FS_SHP_REF_STA_WEI_P1      (MDNS_BASE + 0x0264)
++#define    MDNS_ADDR_Y_FS_SHP_CUR_FLUCT_PAR       (MDNS_BASE + 0x0268)
++#define    MDNS_ADDR_Y_FS_SHP_REF_FLUCT_PAR       (MDNS_BASE + 0x026C)
++#define    MDNS_ADDR_UV_CUT_VALUE                 (MDNS_BASE + 0x0280)
++#define    MDNS_ADDR_UV_SAD_CFG                   (MDNS_BASE + 0x0284)
++#define    MDNS_ADDR_UV_TCA_PAR                   (MDNS_BASE + 0x0290)
++#define    MDNS_ADDR_UV_TMA_T_PAR0                (MDNS_BASE + 0x0294)
++#define    MDNS_ADDR_UV_TMA_T_PAR1                (MDNS_BASE + 0x0298)
++#define    MDNS_ADDR_UV_TMA_V_PAR0                (MDNS_BASE + 0x029C)
++#define    MDNS_ADDR_UV_TMA_V_PAR1                (MDNS_BASE + 0x02a0)
++#define    MDNS_ADDR_UV_TMA_W_PAR0                (MDNS_BASE + 0x02a4)
++#define    MDNS_ADDR_UV_TMA_W_PAR1                (MDNS_BASE + 0x02a8)
++#define    MDNS_ADDR_UV_STA_WEI_PAR0              (MDNS_BASE + 0x02b0)
++#define    MDNS_ADDR_UV_STA_WEI_PAR1              (MDNS_BASE + 0x02b4)
++#define    MDNS_ADDR_UV_STA_WEI_PAR2              (MDNS_BASE + 0x02b8)
++#define    MDNS_ADDR_UV_STA_WEI_PAR3              (MDNS_BASE + 0x02bC)
++#define    MDNS_ADDR_UV_STA_WEI_PAR4              (MDNS_BASE + 0x02c0)
++#define    MDNS_ADDR_UV_STA_WEI_PAR5              (MDNS_BASE + 0x02c4)
++#define    MDNS_ADDR_UV_STA_WEI_PAR6              (MDNS_BASE + 0x02c8)
++#define    MDNS_ADDR_UV_STA_WEI_PAR7              (MDNS_BASE + 0x02cC)
++#define    MDNS_ADDR_UV_STA_WEI_PAR8              (MDNS_BASE + 0x02d0)
++#define    MDNS_ADDR_UV_STA_WEI_PAR9              (MDNS_BASE + 0x02d4)
++#define    MDNS_ADDR_UV_STA_WEI_PARa              (MDNS_BASE + 0x02d8)
++#define    MDNS_ADDR_UV_STA_WEI_PARb              (MDNS_BASE + 0x02dC)
++#define    MDNS_ADDR_UV_STA_WEI_PARc              (MDNS_BASE + 0x02e0)
++#define    MDNS_ADDR_UV_STA_WEI_PARd              (MDNS_BASE + 0x02e4)
++#define    MDNS_ADDR_UV_STA_WEI_PARe              (MDNS_BASE + 0x02e8)
++#define    MDNS_ADDR_UV_STA_WEI_PARf              (MDNS_BASE + 0x02eC)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR0              (MDNS_BASE + 0x02f0)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR1              (MDNS_BASE + 0x02f4)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR2              (MDNS_BASE + 0x02f8)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR3              (MDNS_BASE + 0x02fC)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR4              (MDNS_BASE + 0x0300)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR5              (MDNS_BASE + 0x0304)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR6              (MDNS_BASE + 0x0308)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR7              (MDNS_BASE + 0x030C)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR8              (MDNS_BASE + 0x0310)
++#define    MDNS_ADDR_UV_PBT_WEI_PAR9              (MDNS_BASE + 0x0314)
++#define    MDNS_ADDR_UV_PBT_WEI_PARa              (MDNS_BASE + 0x0318)
++#define    MDNS_ADDR_UV_PBT_WEI_PARb              (MDNS_BASE + 0x031C)
++#define    MDNS_ADDR_UV_PBT_WEI_PARc              (MDNS_BASE + 0x0320)
++#define    MDNS_ADDR_UV_PBT_WEI_PARd              (MDNS_BASE + 0x0324)
++#define    MDNS_ADDR_UV_PBT_WEI_PARe              (MDNS_BASE + 0x0328)
++#define    MDNS_ADDR_UV_PBT_WEI_PARf              (MDNS_BASE + 0x032C)
++#define    MDNS_ADDR_UV_WSA_S_PAR                 (MDNS_BASE + 0x0330)
++#define    MDNS_ADDR_UV_WSA_M_PAR                 (MDNS_BASE + 0x0334)
++#define    MDNS_ADDR_UV_REF_WEI_LMT               (MDNS_BASE + 0x0338)
++#define    MDNS_ADDR_UV_REF_WEI_SGM_X_PAR0        (MDNS_BASE + 0x0340)
++#define    MDNS_ADDR_UV_REF_WEI_SGM_X_PAR1        (MDNS_BASE + 0x0344)
++#define    MDNS_ADDR_UV_REF_WEI_SGM_X_PAR2        (MDNS_BASE + 0x0348)
++#define    MDNS_ADDR_UV_REF_WEI_SGM_Y_PAR0        (MDNS_BASE + 0x034C)
++#define    MDNS_ADDR_UV_REF_WEI_SGM_Y_PAR1        (MDNS_BASE + 0x0350)
++#define    MDNS_ADDR_UV_REF_WEI_SGM_S_PAR0        (MDNS_BASE + 0x0354)
++#define    MDNS_ADDR_UV_REF_WEI_SGM_S_PAR1        (MDNS_BASE + 0x0358)
++#define    MDNS_ADDR_UV_FS_MV_JUDGE_THRES         (MDNS_BASE + 0x035C)
++#define    MDNS_ADDR_UV_FC_TYPE                   (MDNS_BASE + 0x0360)
++#define    MDNS_ADDR_UV_FC_S_PAR0                 (MDNS_BASE + 0x0370)
++#define    MDNS_ADDR_UV_FC_S_PAR1                 (MDNS_BASE + 0x0374)
++#define    MDNS_ADDR_UV_FC_M_PAR0                 (MDNS_BASE + 0x0378)
++#define    MDNS_ADDR_UV_FC_M_PAR1                 (MDNS_BASE + 0x037C)
++#define    MDNS_ADDR_UV_BLUR_WEI                  (MDNS_BASE + 0x0380)
++
++//============================================================
++// SDNS
++//============================================================
++#define    SDNS_ADDR_T_VERSION                    (SDNS_BASE + 0x0000)
++#define    SDNS_ADDR_REG_CTRL                     (SDNS_BASE + 0x0004)
++#define    SDNS_ADDR_DBG_SEL                      (SDNS_BASE + 0x0008)
++#define    SDNS_ADDR_DBG_VALUE                    (SDNS_BASE + 0x000C)
++#define    SDNS_ADDR_Y_FUN_EN                     (SDNS_BASE + 0x0010)
++#define    SDNS_ADDR_Y_COM_PAR0                   (SDNS_BASE + 0x0014)
++#define    SDNS_ADDR_Y_COM_PAR1                   (SDNS_BASE + 0x0018)
++#define    SDNS_ADDR_Y_FUSION_PAR0                (SDNS_BASE + 0x001C)
++#define    SDNS_ADDR_Y_FUSION_PAR1                (SDNS_BASE + 0x0020)
++#define    SDNS_ADDR_Y_FUSION_PAR2                (SDNS_BASE + 0x0024)
++#define    SDNS_ADDR_Y_FUSION_PAR3                (SDNS_BASE + 0x0028)
++#define    SDNS_ADDR_Y_DETAIL_PAR0                (SDNS_BASE + 0x002C)
++#define    SDNS_ADDR_Y_DETAIL_PAR1                (SDNS_BASE + 0x0030)
++#define    SDNS_ADDR_Y_DETAIL_PAR2                (SDNS_BASE + 0x0034)
++#define    SDNS_ADDR_Y_DETAIL_PAR3                (SDNS_BASE + 0x0038)
++#define    SDNS_ADDR_Y_LUMA_PAR0                  (SDNS_BASE + 0x003C)
++#define    SDNS_ADDR_Y_LUMA_PAR1                  (SDNS_BASE + 0x0040)
++#define    SDNS_ADDR_Y_LUMA_PAR2                  (SDNS_BASE + 0x0044)
++#define    SDNS_ADDR_Y_LUMA_PAR3                  (SDNS_BASE + 0x0048)
++#define    SDNS_ADDR_Y_BSHP_PAR0                  (SDNS_BASE + 0x004C)
++#define    SDNS_ADDR_Y_BSHP_PAR1                  (SDNS_BASE + 0x0050)
++#define    SDNS_ADDR_Y_BSHP_PAR2                  (SDNS_BASE + 0x0054)
++#define    SDNS_ADDR_Y_BSHP_PAR3                  (SDNS_BASE + 0x0058)
++#define    SDNS_ADDR_Y_DSHP_PAR0                  (SDNS_BASE + 0x005C)
++#define    SDNS_ADDR_Y_DSHP_PAR1                  (SDNS_BASE + 0x0060)
++#define    SDNS_ADDR_Y_DSHP_PAR2                  (SDNS_BASE + 0x0064)
++#define    SDNS_ADDR_Y_DSHP_PAR3                  (SDNS_BASE + 0x0068)
++#define    SDNS_ADDR_Y_BI_PAR0                    (SDNS_BASE + 0x006C)
++#define    SDNS_ADDR_Y_BI_PAR1                    (SDNS_BASE + 0x0070)
++#define    SDNS_ADDR_Y_BI_PAR2                    (SDNS_BASE + 0x0074)
++#define    SDNS_ADDR_Y_BI_PAR3                    (SDNS_BASE + 0x0078)
++#define    SDNS_ADDR_UV_FUN_EN                    (SDNS_BASE + 0x0080)
++#define    SDNS_ADDR_UV_COM_PAR                   (SDNS_BASE + 0x0084)
++#define    SDNS_ADDR_UV_FUSION_PAR0               (SDNS_BASE + 0x0088)
++#define    SDNS_ADDR_UV_FUSION_PAR1               (SDNS_BASE + 0x008C)
++#define    SDNS_ADDR_UV_FUSION_PAR2               (SDNS_BASE + 0x0090)
++#define    SDNS_ADDR_UV_FUSION_PAR3               (SDNS_BASE + 0x0094)
++
++//============================================================
++// HLDC
++//============================================================
++#define    HLDC_ADDR_REG_CTRL                     (HLDC_BASE + 0x0000)
++#define    HLDC_ADDR_DIS_Y_COEFF_X                (HLDC_BASE + 0x0004)
++#define    HLDC_ADDR_DIS_UV_COEFF_X               (HLDC_BASE + 0x0008)
++#define    HLDC_ADDR_P1_Y_VAL                     (HLDC_BASE + 0x000C)
++#define    HLDC_ADDR_P1_UV_VAL                    (HLDC_BASE + 0x0010)
++#define    HLDC_ADDR_R2_Y_REP                     (HLDC_BASE + 0x0014)
++#define    HLDC_ADDR_R2_UV_REP                    (HLDC_BASE + 0x0018)
++#define    HLDC_ADDR_Y_OFFSET                     (HLDC_BASE + 0x001C)
++#define    HLDC_ADDR_UV_OFFSET                    (HLDC_BASE + 0x0020)
++#define    HLDC_ADDR_LINE_BLK_Y                   (HLDC_BASE + 0x0024)
++#define    HLDC_ADDR_LINE_BLK_UV                  (HLDC_BASE + 0x0028)
++
++//============================================================
++// Mscaler
++//============================================================
++#define    MSCA_CTRL                         (MSCA_BASE+0x000)
++#define    MSCA_CH_EN                        (MSCA_BASE+0x004)
++#define    MSCA_CH_STA                       (MSCA_BASE+0x008)
++#define    MSCA_INT_STA                      (MSCA_BASE+0x00C)
++#define    MSCA_INT_MSK                      (MSCA_BASE+0x010)
++#define    MSCA_INT_CLR                      (MSCA_BASE+0x014)
++#define    MSCA_DMAOUT_ARB                   (MSCA_BASE+0x018)
++#define    MSCA_CLK_GATE_EN                  (MSCA_BASE+0x01C)
++#define    MSCA_CLK_DIS                      (MSCA_BASE+0x020)
++#define    MSCA_SRC_IN                       (MSCA_BASE+0x030)
++#define    MSCA_SRC_SIZE                     (MSCA_BASE+0x034)
++#define    MSCA_GLO_RSZ_COEF_WR              (MSCA_BASE+0x040)
++#define    MSCA_SYS_PRO_CLK_EN               (MSCA_BASE+0x050)
++#define    MSCA_DS0_CLK_NUM                  (MSCA_BASE+0x054)
++#define    MSCA_DS1_CLK_NUM                  (MSCA_BASE+0x058)
++#define    MSCA_DS2_CLK_NUM                  (MSCA_BASE+0x05C)
++
++//ds0
++#define    MSCA_ADDR_DS0_RSZ_SIZE                 (MSCA_BASE+0x100)
++#define    MSCA_ADDR_DS0_RSZ_STEP                 (MSCA_BASE+0x104)
++#define    MSCA_ADDR_DS0_CROP_POS                 (MSCA_BASE+0x128)
++#define    MSCA_ADDR_DS0_CROP_SIZE                (MSCA_BASE+0x12C)
++#define    MSCA_ADDR_DS0_FRA_RATE_LOOP            (MSCA_BASE+0x130)
++#define    MSCA_ADDR_DS0_FRA_RATE_MASK            (MSCA_BASE+0x134)
++#define    MSCA_ADDR_DS0_MASK0_POS                (MSCA_BASE+0x138)
++#define    MSCA_ADDR_DS0_MASK0_SIZE               (MSCA_BASE+0x13C)
++#define    MSCA_ADDR_DS0_MASK0_ARGB               (MSCA_BASE+0x140)
++#define    MSCA_ADDR_DS0_MASK1_POS                (MSCA_BASE+0x144)
++#define    MSCA_ADDR_DS0_MASK1_SIZE               (MSCA_BASE+0x148)
++#define    MSCA_ADDR_DS0_MASK1_ARGB               (MSCA_BASE+0x14C)
++#define    MSCA_ADDR_DS0_MASK2_POS                (MSCA_BASE+0x150)
++#define    MSCA_ADDR_DS0_MASK2_SIZE               (MSCA_BASE+0x154)
++#define    MSCA_ADDR_DS0_MASK2_ARGB               (MSCA_BASE+0x158)
++#define    MSCA_ADDR_DS0_MASK3_POS                (MSCA_BASE+0x15C)
++#define    MSCA_ADDR_DS0_MASK3_SIZE               (MSCA_BASE+0x160)
++#define    MSCA_ADDR_DS0_MASK3_ARGB               (MSCA_BASE+0x164)
++#define    MSCA_ADDR_DS0_DMAOUT_FMT               (MSCA_BASE+0x168)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_ADDR            (MSCA_BASE+0x16C)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_FIFO_STA        (MSCA_BASE+0x170)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_LAST_ADDR       (MSCA_BASE+0x174)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_LAST_STATS_NUM  (MSCA_BASE+0x178)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_LAST_FIFO_STA   (MSCA_BASE+0x17C)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_STR             (MSCA_BASE+0x180)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_ADDR           (MSCA_BASE+0x184)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_FIFO_STA       (MSCA_BASE+0x188)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_LAST_ADDR      (MSCA_BASE+0x18C)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_LAST_STATS_NUM (MSCA_BASE+0x190)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_LAST_FIFO_STA  (MSCA_BASE+0x194)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_STR            (MSCA_BASE+0x198)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_FIFO_CLR        (MSCA_BASE+0x19C)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_FIFO_CLR       (MSCA_BASE+0x1A0)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_LAST_FIFO_CLR   (MSCA_BASE+0x1A4)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_LAST_FIFO_CLR  (MSCA_BASE+0x1A8)
++#define    MSCA_ADDR_DS0_DMAOUT_Y_ADDR_SEL        (MSCA_BASE+0x1AC)
++#define    MSCA_ADDR_DS0_DMAOUT_UV_ADDR_SEL       (MSCA_BASE+0x1B0)
++
++//-- ds1
++#define    MSCA_ADDR_DS1_RSZ_SIZE                 (MSCA_BASE+0x200)
++#define    MSCA_ADDR_DS1_RSZ_STEP                 (MSCA_BASE+0x204)
++#define    MSCA_ADDR_DS1_CROP_POS                 (MSCA_BASE+0x228)
++#define    MSCA_ADDR_DS1_CROP_SIZE                (MSCA_BASE+0x22C)
++#define    MSCA_ADDR_DS1_FRA_RATE_LOOP            (MSCA_BASE+0x230)
++#define    MSCA_ADDR_DS1_FRA_RATE_MASK            (MSCA_BASE+0x234)
++#define    MSCA_ADDR_DS1_MASK0_POS                (MSCA_BASE+0x238)
++#define    MSCA_ADDR_DS1_MASK0_SIZE               (MSCA_BASE+0x23C)
++#define    MSCA_ADDR_DS1_MASK0_ARGB               (MSCA_BASE+0x240)
++#define    MSCA_ADDR_DS1_MASK1_POS                (MSCA_BASE+0x244)
++#define    MSCA_ADDR_DS1_MASK1_SIZE               (MSCA_BASE+0x248)
++#define    MSCA_ADDR_DS1_MASK1_ARGB               (MSCA_BASE+0x24C)
++#define    MSCA_ADDR_DS1_MASK2_POS                (MSCA_BASE+0x250)
++#define    MSCA_ADDR_DS1_MASK2_SIZE               (MSCA_BASE+0x254)
++#define    MSCA_ADDR_DS1_MASK2_ARGB               (MSCA_BASE+0x258)
++#define    MSCA_ADDR_DS1_MASK3_POS                (MSCA_BASE+0x25C)
++#define    MSCA_ADDR_DS1_MASK3_SIZE               (MSCA_BASE+0x260)
++#define    MSCA_ADDR_DS1_MASK3_ARGB               (MSCA_BASE+0x264)
++#define    MSCA_ADDR_DS1_DMAOUT_FMT               (MSCA_BASE+0x268)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_ADDR            (MSCA_BASE+0x26C)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_FIFO_STA        (MSCA_BASE+0x270)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_LAST_ADDR       (MSCA_BASE+0x274)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_LAST_STATS_NUM  (MSCA_BASE+0x278)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_LAST_FIFO_STA   (MSCA_BASE+0x27C)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_STR             (MSCA_BASE+0x280)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_ADDR           (MSCA_BASE+0x284)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_FIFO_STA       (MSCA_BASE+0x288)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_LAST_ADDR      (MSCA_BASE+0x28C)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_LAST_STATS_NUM (MSCA_BASE+0x290)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_LAST_FIFO_STA  (MSCA_BASE+0x294)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_STR            (MSCA_BASE+0x298)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_FIFO_CLR        (MSCA_BASE+0x29C)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_FIFO_CLR       (MSCA_BASE+0x2A0)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_LAST_FIFO_CLR   (MSCA_BASE+0x2A4)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_LAST_FIFO_CLR  (MSCA_BASE+0x2A8)
++#define    MSCA_ADDR_DS1_DMAOUT_Y_ADDR_SEL        (MSCA_BASE+0x2AC)
++#define    MSCA_ADDR_DS1_DMAOUT_UV_ADDR_SEL       (MSCA_BASE+0x2B0)
++
++
++//-- ds2
++#define    MSCA_ADDR_DS2_RSZ_SIZE                 (MSCA_BASE+0x300)
++#define    MSCA_ADDR_DS2_RSZ_STEP                 (MSCA_BASE+0x304)
++#define    MSCA_ADDR_DS2_CROP_POS                 (MSCA_BASE+0x328)
++#define    MSCA_ADDR_DS2_CROP_SIZE                (MSCA_BASE+0x32C)
++#define    MSCA_ADDR_DS2_FRA_RATE_LOOP            (MSCA_BASE+0x330)
++#define    MSCA_ADDR_DS2_FRA_RATE_MASK            (MSCA_BASE+0x334)
++#define    MSCA_ADDR_DS2_MASK0_POS                (MSCA_BASE+0x338)
++#define    MSCA_ADDR_DS2_MASK0_SIZE               (MSCA_BASE+0x33C)
++#define    MSCA_ADDR_DS2_MASK0_ARGB               (MSCA_BASE+0x340)
++#define    MSCA_ADDR_DS2_MASK1_POS                (MSCA_BASE+0x344)
++#define    MSCA_ADDR_DS2_MASK1_SIZE               (MSCA_BASE+0x348)
++#define    MSCA_ADDR_DS2_MASK1_ARGB               (MSCA_BASE+0x34C)
++#define    MSCA_ADDR_DS2_MASK2_POS                (MSCA_BASE+0x350)
++#define    MSCA_ADDR_DS2_MASK2_SIZE               (MSCA_BASE+0x354)
++#define    MSCA_ADDR_DS2_MASK2_ARGB               (MSCA_BASE+0x358)
++#define    MSCA_ADDR_DS2_MASK3_POS                (MSCA_BASE+0x35C)
++#define    MSCA_ADDR_DS2_MASK3_SIZE               (MSCA_BASE+0x360)
++#define    MSCA_ADDR_DS2_MASK3_ARGB               (MSCA_BASE+0x364)
++#define    MSCA_ADDR_DS2_DMAOUT_FMT               (MSCA_BASE+0x368)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_ADDR            (MSCA_BASE+0x36C)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_FIFO_STA        (MSCA_BASE+0x370)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_LAST_ADDR       (MSCA_BASE+0x374)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_LAST_STATS_NUM  (MSCA_BASE+0x378)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_LAST_FIFO_STA   (MSCA_BASE+0x37C)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_STR             (MSCA_BASE+0x380)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_ADDR           (MSCA_BASE+0x384)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_FIFO_STA       (MSCA_BASE+0x388)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_LAST_ADDR      (MSCA_BASE+0x38C)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_LAST_STATS_NUM (MSCA_BASE+0x390)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_LAST_FIFO_STA  (MSCA_BASE+0x394)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_STR            (MSCA_BASE+0x398)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_FIFO_CLR        (MSCA_BASE+0x39C)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_FIFO_CLR       (MSCA_BASE+0x3A0)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_LAST_FIFO_CLR   (MSCA_BASE+0x3A4)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_LAST_FIFO_CLR  (MSCA_BASE+0x3A8)
++#define    MSCA_ADDR_DS2_DMAOUT_Y_ADDR_SEL        (MSCA_BASE+0x3AC)
++#define    MSCA_ADDR_DS2_DMAOUT_UV_ADDR_SEL       (MSCA_BASE+0x3B0)
++
++//--DEBUG
++#define    MSCA_ADDR_VRSZ_Y_DBG_SEL               (MSCA_BASE+0x080)
++#define    MSCA_ADDR_VRSZ_UV_DBG_SEL              (MSCA_BASE+0x084)
++#define    MSCA_ADDR_DS0_DMA_OUT_DBG0_SEL         (MSCA_BASE+0x088)
++#define    MSCA_ADDR_DS0_DMA_OUT_DBG1_SEL         (MSCA_BASE+0x08C)
++#define    MSCA_ADDR_DS0_DMA_OUT_DBG2_SEL         (MSCA_BASE+0x090)
++#define    MSCA_ADDR_DS1_DMA_OUT_DBG0_SEL         (MSCA_BASE+0x094)
++#define    MSCA_ADDR_DS1_DMA_OUT_DBG1_SEL         (MSCA_BASE+0x098)
++#define    MSCA_ADDR_DS1_DMA_OUT_DBG2_SEL         (MSCA_BASE+0x09C)
++#define    MSCA_ADDR_DS2_DMA_OUT_DBG0_SEL         (MSCA_BASE+0x0A0)
++#define    MSCA_ADDR_DS2_DMA_OUT_DBG1_SEL         (MSCA_BASE+0x0A4)
++#define    MSCA_ADDR_DS2_DMA_OUT_DBG2_SEL         (MSCA_BASE+0x0A8)
++#define    MSCA_ADDR_DS0_HRSZ_Y_DBG_SEL           (MSCA_BASE+0x0AC)
++#define    MSCA_ADDR_DS0_HRSZ_UV_DBG_SEL          (MSCA_BASE+0x0B0)
++#define    MSCA_ADDR_DS1_HRSZ_Y_DBG_SEL           (MSCA_BASE+0x0B4)
++#define    MSCA_ADDR_DS1_HRSZ_UV_DBG_SEL          (MSCA_BASE+0x0B8)
++#define    MSCA_ADDR_DS2_HRSZ_Y_DBG_SEL           (MSCA_BASE+0x0BC)
++#define    MSCA_ADDR_DS2_HRSZ_UV_DBG_SEL          (MSCA_BASE+0x0C0)
++#define    MSCA_ADDR_BP_BUS0_DBG_SEL              (MSCA_BASE+0x0C4)
++#define    MSCA_ADDR_BP_BUS1_DBG_SEL              (MSCA_BASE+0x0C8)
++#define    MSCA_ADDR_BP_BUS2_DBG_SEL              (MSCA_BASE+0x0CC)
++#define    MSCA_ADDR_STP_DBG_SEL                  (MSCA_BASE+0x0D0)
++
++#define    MSCA_ADDR_DS0_CRC_Y_SEL                (MSCA_BASE+0x0E0)
++#define    MSCA_ADDR_DS0_CRC_UV_SEL               (MSCA_BASE+0x0E4)
++#define    MSCA_ADDR_DS1_CRC_Y_SEL                (MSCA_BASE+0x0E8)
++#define    MSCA_ADDR_DS1_CRC_UV_SEL               (MSCA_BASE+0x0EC)
++#define    MSCA_ADDR_DS2_CRC_Y_SEL                (MSCA_BASE+0x0F0)
++#define    MSCA_ADDR_DS2_CRC_UV_SEL               (MSCA_BASE+0x0F4)
++
++#define CHx_RSZ_OSIZE(n)				(MSCA_BASE+(0x0100*(n))+0x100)
++#define CHx_RSZ_STEP(n)					(MSCA_BASE+(0x0100*(n))+0x104)
++
++#define CHx_CROP_OPOS(n)				(MSCA_BASE+(0x0100*(n))+0x128)
++#define CHx_CROP_OSIZE(n)				(MSCA_BASE+(0x0100*(n))+0x12c)
++#define CHx_FRA_CTRL_LOOP(n)				(MSCA_BASE+(0x0100*(n))+0x130)
++#define CHx_FRA_CTRL_MASK(n)				(MSCA_BASE+(0x0100*(n))+0x134)
++#define CHx_MS0_POS(n)					(MSCA_BASE+(0x0100*(n))+0x138)
++#define CHx_MS0_SIZE(n)					(MSCA_BASE+(0x0100*(n))+0x13c)
++#define CHx_MS0_VALUE(n)				(MSCA_BASE+(0x0100*(n))+0x140)
++#define CHx_MS1_POS(n)					(MSCA_BASE+(0x0100*(n))+0x144)
++#define CHx_MS1_SIZE(n)					(MSCA_BASE+(0x0100*(n))+0x148)
++#define CHx_MS1_VALUE(n)				(MSCA_BASE+(0x0100*(n))+0x14c)
++#define CHx_MS2_POS(n)					(MSCA_BASE+(0x0100*(n))+0x150)
++#define CHx_MS2_SIZE(n)					(MSCA_BASE+(0x0100*(n))+0x154)
++#define CHx_MS2_VALUE(n)				(MSCA_BASE+(0x0100*(n))+0x158)
++#define CHx_MS3_POS(n)					(MSCA_BASE+(0x0100*(n))+0x15c)
++#define CHx_MS3_SIZE(n)					(MSCA_BASE+(0x0100*(n))+0x160)
++#define CHx_MS3_VALUE(n)				(MSCA_BASE+(0x0100*(n))+0x164)
++#define CHx_OUT_FMT(n)					(MSCA_BASE+(0x0100*(n))+0x168)
++#define CHx_DMAOUT_Y_ADDR(n)				(MSCA_BASE+(0x0100*(n))+0x16c)
++#define CHx_Y_ADDR_FIFO_STA(n)				(MSCA_BASE+(0x0100*(n))+0x170)
++#define CHx_DMAOUT_Y_LAST_ADDR(n)			(MSCA_BASE+(0x0100*(n))+0x174)
++#define CHx_DMAOUT_Y_LAST_STATS_NUM(n)			(MSCA_BASE+(0x0100*(n))+0x178)
++#define CHx_Y_LAST_ADDR_FIFO_STA(n)			(MSCA_BASE+(0x0100*(n))+0x17c)
++#define CHx_DMAOUT_Y_STRI(n)				(MSCA_BASE+(0x0100*(n))+0x180)
++#define CHx_DMAOUT_UV_ADDR(n)				(MSCA_BASE+(0x0100*(n))+0x184)
++#define CHx_UV_ADDR_FIFO_STA(n)				(MSCA_BASE+(0x0100*(n))+0x188)
++#define CHx_DMAOUT_UV_LAST_ADDR(n)			(MSCA_BASE+(0x0100*(n))+0x18c)
++#define CHx_DMAOUT_UV_LAST_STATS_NUM(n)			(MSCA_BASE+(0x0100*(n))+0x190)
++#define CHx_UV_LAST_ADDR_FIFO_STA(n)			(MSCA_BASE+(0x0100*(n))+0x194)
++#define CHx_DMAOUT_UV_STRI(n)				(MSCA_BASE+(0x0100*(n))+0x198)
++#define CHx_DMAOUT_Y_ADDR_CLR(n)			(MSCA_BASE+(0x0100*(n))+0x19c)
++#define CHx_DMAOUT_UV_ADDR_CLR(n)			(MSCA_BASE+(0x0100*(n))+0x1a0)
++#define CHx_DMAOUT_Y_LAST_ADDR_CLR(n)			(MSCA_BASE+(0x0100*(n))+0x1a4)
++#define CHx_DMAOUT_UV_LAST_ADDR_CLR(n)			(MSCA_BASE+(0x0100*(n))+0x1a8)
++#define CHx_DMAOUT_Y_ADDR_SEL(n)			(MSCA_BASE+(0x0100*(n))+0x1ac)
++#define CHx_DMAOUT_UV_ADDR_SEL(n)			(MSCA_BASE+(0x0100*(n))+0x1b0)
++
++#define TIZIANO_ISP_IRQ_ISP_FRD                        (0)
++#define TIZIANO_ISP_IRQ_STOP                           (4)
++#define TIZIANO_ISP_IRQ_CTM_STATIC                     (8)
++#define TIZIANO_ISP_IRQ_AE_STATIC                      (16)
++#define TIZIANO_ISP_IRQ_AE_HIST                        (17)
++#define TIZIANO_ISP_IRQ_AWB_STATIC                     (18)
++#define TIZIANO_ISP_IRQ_AF_STATIC                      (19)
++#define TIZIANO_ISP_IRQ_ADR_STATIC                     (20)
++#define TIZIANO_ISP_IRQ_DEFOG_STATIC                   (21)
++#define TIZIANO_ISP_IRQ_DMAOUT_FRD                     (23)
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-sensor.h b/module_drivers/drivers/media/platform/ingenic-isp/isp-sensor.h
+new file mode 100644
+index 000000000..a35fb51c4
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-sensor.h
+@@ -0,0 +1,80 @@
++#ifndef __ISP_SENSOR_H__
++#define __ISP_SENSOR_H__
++
++#define V4L2_CID_USER_ANALOG_GAIN_SHORT             (V4L2_CID_USER_BASE + 0x1090)
++#define V4L2_CID_USER_EXPOSURE_SHORT             (V4L2_CID_USER_BASE + 0x1091)
++
++enum  mipi_sensor_data_type_value {
++	YUV422_8BIT = 0x1e,
++	RAW8 = 0x2a,
++	RAW10 = 0x2b,
++	RAW12 = 0x2c,
++};
++
++enum tx_sensor_frm_mode {
++	TX_SENSOR_DEFAULT_FRAME_MODE = 0,
++	TX_SENSOR_WDR_2_FRAME_MODE,
++	TX_SENSOR_WDR_3_FRAME_MODE,
++	TX_SENSOR_WDR_4_FRAME_MODE,
++};
++
++enum tx_sensor_mode {
++	TX_SENSOR_DEFAULT_MODE = 0,
++	TX_SENSOR_NOT_VC_MODE,
++	TX_SENSOR_VC_MODE,
++};
++
++enum tx_sensor_csi_fmt {
++	TX_SENSOR_RAW8 = 0,
++	TX_SENSOR_RAW10,
++	TX_SENSOR_RAW12,
++};
++
++typedef enum {
++	SENSOR_MIPI_OTHER_MODE,
++	SENSOR_MIPI_SONY_MODE,
++}sensor_mipi_mode;
++
++struct mipi_cfg {
++	unsigned int clk;
++	unsigned int twidth;
++	unsigned int theight;
++	sensor_mipi_mode mipi_mode;
++	unsigned int hcrop_diff_en;
++	unsigned int mipi_vcomp_en;
++	unsigned int mipi_hcomp_en;
++	unsigned short mipi_crop_start0x;
++	unsigned short mipi_crop_start0y;
++	unsigned short mipi_crop_start1x;
++	unsigned short mipi_crop_start1y;
++	unsigned short mipi_crop_start2x;
++	unsigned short mipi_crop_start2y;
++	unsigned short mipi_crop_start3x;
++	unsigned short mipi_crop_start3y;
++	unsigned int line_sync_mode;
++	unsigned int work_start_flag;
++	unsigned int data_type_en;
++	enum  mipi_sensor_data_type_value data_type_value;
++	unsigned int del_start;
++	unsigned int sensor_fid_mode;
++	enum tx_sensor_frm_mode sensor_frame_mode;
++	enum tx_sensor_mode sensor_mode;
++	enum tx_sensor_csi_fmt sensor_csi_fmt;
++};
++
++struct dvp_cfg {
++
++};
++
++struct sensor_info {
++	unsigned int fps;
++	unsigned int total_width;
++	unsigned int total_height;
++	int wdr_en;
++	union {
++		struct mipi_cfg mipi_cfg;
++		struct dvp_cfg dvp_cfg;
++	};
++};
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-video-mplane.c b/module_drivers/drivers/media/platform/ingenic-isp/isp-video-mplane.c
+new file mode 100644
+index 000000000..52dd774b5
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-video-mplane.c
+@@ -0,0 +1,729 @@
++#include <linux/clk.h>
++#include <linux/media-bus-format.h>
++#include <linux/media.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_graph.h>
++#include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
++#include <linux/pm_domain.h>
++#include <linux/slab.h>
++#include <linux/videodev2.h>
++#include <linux/component.h>
++#include <linux/mutex.h>
++
++#include <media/media-device.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-event.h>
++#include <media/v4l2-ioctl.h>
++#include <media/v4l2-dev.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++
++#include "isp-drv.h"
++#define ISP_VIDEO_DRIVER_NAME	"ispvideo"
++
++
++
++static struct v4l2_subdev *
++isp_video_remote_subdev(struct isp_video_device *ispvideo, u32 *pad)
++{
++        struct media_pad *remote;
++
++	printk("------%s, %d\n", __func__, __LINE__);
++
++        remote = media_entity_remote_pad(&ispvideo->pad);
++
++        if (remote == NULL ||
++            media_entity_type(remote->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
++                return NULL;
++
++        if (pad)
++                *pad = remote->index;
++
++        return media_entity_to_v4l2_subdev(remote->entity);
++}
++
++
++/* -----------------------------------------------------------------------------
++ * V4L2 ioctls
++ */
++
++static int
++isp_video_querycap(struct file *file, void *fh, struct v4l2_capability *cap)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++
++        strlcpy(cap->driver, ISP_VIDEO_DRIVER_NAME, sizeof(cap->driver));
++        strlcpy(cap->card, ispvideo->video.name, sizeof(cap->card));
++        strlcpy(cap->bus_info, "media", sizeof(cap->bus_info));
++
++	cap->capabilities = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING | V4L2_CAP_DEVICE_CAPS;
++
++	cap->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING;
++
++        return 0;
++}
++
++static int isp_video_enum_fmt_vid_cap_mplane(struct file *file, void *fh,
++					    struct v4l2_fmtdesc *f)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	const struct isp_video_format *fmt = NULL;
++
++	fmt = ispvideo->ops->find_format(NULL, NULL, f->index);
++	if(fmt == NULL) {
++		return -EINVAL;
++	}
++	strlcpy(f->description, fmt->name, sizeof(f->description));
++	f->pixelformat = fmt->fourcc;
++
++	return 0;
++}
++static int
++isp_video_g_fmt_vid_cap_mplane(struct file *file, void *fh, struct v4l2_format *format)
++{
++        struct isp_video_ctx *ctx = to_isp_video_ctx(fh);
++        struct isp_video_device *ispvideo = video_drvdata(file);
++
++	printk("------%s, %d\n", __func__, __LINE__);
++
++        //mutex_lock(&ispvideo->mutex);
++	if(ctx->format.type == 0) {
++		dev_warn(ispvideo->dev, "Format not setted before calling g_fmt\n");
++	} else {
++        	*format = ctx->format;
++	}
++        //mutex_unlock(&ispvideo->mutex);
++
++        return 0;
++}
++
++static int
++__isp_video_try_format(struct isp_video_device *ispvideo, struct v4l2_pix_format_mplane *pix_mp,
++		const struct isp_video_format **ofmt)
++{
++	struct v4l2_plane_pix_format *plane_fmt;
++	struct isp_video_format *fmt = NULL;
++
++	fmt = ispvideo->ops->find_format(&pix_mp->pixelformat, NULL, -1);
++	if(fmt == NULL) {
++		dev_err(ispvideo->dev, "Cannot find appropriate format for pix->pixelformat:[%x]\n", pix_mp->pixelformat);
++		return -EINVAL;
++	}
++
++	pix_mp->colorspace = fmt->colorspace;
++	pix_mp->field = V4L2_FIELD_NONE;
++	pix_mp->pixelformat = fmt->fourcc;
++	pix_mp->num_planes = fmt->num_planes;
++
++	plane_fmt = &pix_mp->plane_fmt[0];
++	plane_fmt->bytesperline = pix_mp->width * fmt->depth[0] / 8;
++	plane_fmt->sizeimage = plane_fmt->bytesperline * pix_mp->height;
++
++	plane_fmt = &pix_mp->plane_fmt[1];
++	plane_fmt->bytesperline = pix_mp->width * fmt->depth[1] / 8;
++	plane_fmt->sizeimage = plane_fmt->bytesperline * pix_mp->height;
++
++	if(ofmt) {
++		*ofmt = fmt;
++	}
++
++	/*TODO, bound width and height!*/
++	printk("=======%s,%d, pixelformat: %x, widht: %d, height: %d, num_planes: %d\n", __func__, __LINE__, pix_mp->pixelformat, pix_mp->width, pix_mp->height, pix_mp->num_planes);
++
++	return 0;
++}
++
++static void to_v4l2_mbus_framefmt(struct isp_video_device *ispvideo, struct v4l2_format *format, struct v4l2_mbus_framefmt *fmt)
++{
++	struct v4l2_pix_format_mplane *pix_mp = &format->fmt.pix_mp;
++	struct isp_video_format *ispfmt = NULL;
++
++	ispfmt = ispvideo->ops->find_format(&pix_mp->pixelformat, NULL, -1);
++
++	fmt->width = pix_mp->width;
++	fmt->height = pix_mp->height;
++	fmt->code = ispfmt->mbus_code;
++	fmt->field = pix_mp->field;
++	fmt->colorspace = pix_mp->colorspace;
++	fmt->ycbcr_enc = pix_mp->ycbcr_enc;
++	fmt->quantization = pix_mp->quantization;
++	fmt->xfer_func = pix_mp->xfer_func;
++}
++
++static int
++isp_video_s_fmt_vid_cap_mplane(struct file *file, void *fh, struct v4l2_format *format)
++{
++        struct isp_video_ctx *ctx = to_isp_video_ctx(fh);
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	struct v4l2_subdev *sd = NULL;
++	struct v4l2_subdev_format subdev_fmt;
++	unsigned int pad = 0;
++	int ret = 0;
++
++	if(vb2_is_busy(&ctx->queue)) {
++		return -EBUSY;
++	}
++
++	ret = __isp_video_try_format(ispvideo, &format->fmt.pix_mp, NULL);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "Failed to set format cap!\n");
++		return -EINVAL;
++	}
++
++	sd = isp_video_remote_subdev(ispvideo, &pad);
++	if(sd == NULL) {
++		return -EINVAL;
++	}
++
++	ctx->format = *format;
++
++	to_v4l2_mbus_framefmt(ispvideo, format, &subdev_fmt.format);
++
++	subdev_fmt.pad = pad;
++	subdev_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++
++	ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &subdev_fmt);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "Failed to set subdev format\n");
++		return -EINVAL;
++	}
++
++	//printk("-%s, %d--ctx: %x--queue: %x, queue->lock: %x\n", __func__, __LINE__, ctx, &ctx->queue, ctx->queue.lock);
++	return 0;
++}
++
++static int
++isp_video_try_format_cap_mplane(struct file *file, void *fh, struct v4l2_format *format)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	int ret = 0;
++
++	printk("-----------%s, %d------------\n", __func__, __LINE__);
++
++	ret = __isp_video_try_format(ispvideo, &format->fmt.pix_mp, NULL);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "Try format cap mplane error!\n");
++		return -EINVAL;
++	}
++	return 0;
++}
++
++static int
++isp_video_cropcap(struct file *file, void *fh, struct v4l2_cropcap *cropcap)
++{
++	printk("-----------%s, %d------------\n", __func__, __LINE__);
++	return 0;
++}
++
++static int
++isp_video_get_crop(struct file *file, void *fh, struct v4l2_crop *crop)
++{
++	printk("-----------%s, %d------------\n", __func__, __LINE__);
++	return 0;
++}
++
++static int
++isp_video_set_crop(struct file *file, void *fh, const struct v4l2_crop *crop)
++{
++	printk("-----------%s, %d------------\n", __func__, __LINE__);
++	return 0;
++}
++
++static int isp_video_enum_input(struct file *file, void *priv,
++				 struct v4l2_input *inp)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++
++	if (inp->index != 0)
++		return -EINVAL;
++
++	/* default is camera */
++	inp->type = V4L2_INPUT_TYPE_CAMERA;
++	inp->std = ispvideo->video.tvnorms;
++	strcpy(inp->name, "Camera");
++
++	return 0;
++}
++
++static int isp_video_g_input(struct file *file, void *priv, unsigned int *i)
++{
++	*i = 0;
++
++	return 0;
++}
++
++static int isp_video_s_input(struct file *file, void *priv, unsigned int i)
++{
++	if (i > 0)
++		return -EINVAL;
++
++	return 0;
++}
++
++static const struct v4l2_ioctl_ops isp_video_ioctl_ops = {
++        .vidioc_querycap                = isp_video_querycap,
++	.vidioc_enum_fmt_vid_cap_mplane	= isp_video_enum_fmt_vid_cap_mplane,
++        .vidioc_g_fmt_vid_cap_mplane    = isp_video_g_fmt_vid_cap_mplane,
++        .vidioc_s_fmt_vid_cap_mplane    = isp_video_s_fmt_vid_cap_mplane,
++        .vidioc_try_fmt_vid_cap_mplane  = isp_video_try_format_cap_mplane,
++        .vidioc_cropcap                 = isp_video_cropcap,
++        .vidioc_g_crop                  = isp_video_get_crop,
++        .vidioc_s_crop                  = isp_video_set_crop,
++        .vidioc_reqbufs                 = vb2_ioctl_reqbufs,
++        .vidioc_querybuf                = vb2_ioctl_querybuf,
++        .vidioc_qbuf                    = vb2_ioctl_qbuf,
++        .vidioc_dqbuf                   = vb2_ioctl_dqbuf,
++        .vidioc_streamon                = vb2_ioctl_streamon,
++        .vidioc_streamoff               = vb2_ioctl_streamoff,
++	.vidioc_enum_input		= isp_video_enum_input,
++	.vidioc_g_input			= isp_video_g_input,
++	.vidioc_s_input			= isp_video_s_input,
++};
++
++/* -----------------------------------------------------------------------------
++ * Video queue operations
++ */
++
++static int isp_video_queue_setup(struct vb2_queue *queue,
++                                 const void *parg,
++                                 unsigned int *count, unsigned int *num_planes,
++                                 unsigned int sizes[], void *alloc_ctxs[])
++{
++        struct isp_video_ctx *ctx = vb2_get_drv_priv(queue);
++        struct isp_video_device *ispvideo = ctx->ispvideo;
++	struct v4l2_format *format = &ctx->format;
++	int i = 0;
++
++	if(*num_planes) {
++		for(i = 0; i < *num_planes; i++) {
++			if(sizes[i] < format->fmt.pix_mp.plane_fmt[i].sizeimage) {
++				return -EINVAL;
++			}
++		}
++	} else {
++		*num_planes = format->fmt.pix_mp.num_planes;
++		for(i = 0; i < *num_planes; i++) {
++			sizes[i] = format->fmt.pix_mp.plane_fmt[i].sizeimage;
++			alloc_ctxs[i] = ispvideo->alloc_ctx;
++		}
++	}
++
++	/*MAX_BUFFER_NUMS:*/
++	if(*count >= 3) {
++		*count = 3;
++	}
++
++        return 0;
++}
++
++static int isp_video_buffer_prepare(struct vb2_buffer *buf)
++{
++	struct isp_video_ctx *ctx = vb2_get_drv_priv(buf->vb2_queue);
++	struct v4l2_format *format = &ctx->format;
++	struct v4l2_pix_format_mplane *pix_mp = &format->fmt.pix_mp;
++	int i;
++
++	for(i = 0; i < buf->num_planes; i++) {
++		vb2_set_plane_payload(buf, i, pix_mp->plane_fmt[i].sizeimage);
++	}
++
++        return 0;
++}
++
++static void isp_video_buffer_queue(struct vb2_buffer *buf)
++{
++        struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(buf);
++	struct isp_video_ctx *ctx = vb2_get_drv_priv(buf->vb2_queue);
++	struct isp_video_buffer *isp_buffer = to_isp_buffer(vbuf);
++	struct isp_video_device *ispvideo = ctx->ispvideo;
++	int ret = 0;
++
++	ret = ispvideo->ops->qbuf(ispvideo, isp_buffer);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "failed to queue buf!\n");
++	}
++}
++
++static int isp_video_subdev_init(struct isp_video_device *ispvideo)
++{
++	struct media_entity *entity = &ispvideo->video.entity;
++	struct v4l2_subdev *sd = NULL;
++	struct media_pad *pad = NULL;
++	int ret = 0;
++
++	/*subdevs reset.*/
++	while(1) {
++		pad = &entity->pads[0];
++		/*直到找到该pipeline上的仅有一个FL_SOURCE pad设备.*/
++		if(!(pad->flags & MEDIA_PAD_FL_SINK))
++			break;
++
++		pad = media_entity_remote_pad(pad);
++		if (pad == NULL ||
++				media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
++			break;
++		entity = pad->entity;
++		sd = media_entity_to_v4l2_subdev(entity);
++
++		/*stream on*/
++		v4l2_set_subdev_hostdata(sd, ispvideo);
++		ret = v4l2_subdev_call(sd, core, init, 1);
++		if(ret < 0 && ret != -ENOIOCTLCMD) {
++			dev_err(ispvideo->dev, "failed to reset subdev[%s]\n", entity->name);
++		} else {
++			ret = 0;
++		}
++	}
++
++	return ret;
++}
++
++static int isp_video_subdev_reset(struct isp_video_device *ispvideo)
++{
++	struct media_entity *entity = &ispvideo->video.entity;
++	struct v4l2_subdev *sd = NULL;
++	struct media_pad *pad = NULL;
++	int ret = 0;
++
++	/*subdevs reset.*/
++	while(1) {
++		pad = &entity->pads[0];
++		/*直到找到该pipeline上的仅有一个FL_SOURCE pad设备.*/
++		if(!(pad->flags & MEDIA_PAD_FL_SINK))
++			break;
++
++		pad = media_entity_remote_pad(pad);
++		if (pad == NULL ||
++				media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
++			break;
++		entity = pad->entity;
++		sd = media_entity_to_v4l2_subdev(entity);
++
++		/*stream on*/
++		v4l2_set_subdev_hostdata(sd, ispvideo);
++		ret = v4l2_subdev_call(sd, core, reset, 1);
++		if(ret < 0 && ret != -ENOIOCTLCMD) {
++			dev_err(ispvideo->dev, "failed to reset subdev[%s]\n", entity->name);
++		} else {
++			ret = 0;
++		}
++	}
++
++	return ret;
++
++}
++
++static int isp_video_subdev_stream(struct isp_video_device *ispvideo, int enable)
++{
++	struct media_entity *entity = &ispvideo->video.entity;
++	struct v4l2_subdev *sd = NULL;
++	struct media_pad *pad = NULL;
++	int ret = 0;
++
++	/*subdevs stream on.*/
++	while(1) {
++		pad = &entity->pads[0];
++		/*直到找到该pipeline上的仅有一个FL_SOURCE pad设备.*/
++		if(!(pad->flags & MEDIA_PAD_FL_SINK))
++			break;
++
++		pad = media_entity_remote_pad(pad);
++		if (pad == NULL ||
++				media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
++			break;
++		entity = pad->entity;
++		sd = media_entity_to_v4l2_subdev(entity);
++
++		/*stream on*/
++		v4l2_set_subdev_hostdata(sd, ispvideo);
++		ret = v4l2_subdev_call(sd, video, s_stream, enable);
++		if(ret < 0) {
++			dev_err(ispvideo->dev, "unable to start stream[%s]\n", entity->name);
++		}
++
++	}
++
++	return ret;
++}
++
++static int isp_video_start_streaming(struct vb2_queue *q, unsigned int count)
++{
++	struct isp_video_ctx *ctx = vb2_get_drv_priv(q);
++	struct isp_video_device *ispvideo = ctx->ispvideo;
++	struct media_entity *entity = &ispvideo->video.entity;
++	struct isp_pipeline *pipe = &ispvideo->pipe;
++	int ret = 0;
++	printk("-----*********  -%s, %d\n", __func__, __LINE__);
++
++	mutex_lock(&ispvideo->stream_lock);
++	ret = media_entity_pipeline_start(entity, &pipe->pipeline);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "Failed to start pipeline\n");
++		goto err_pipeline_start;
++	}
++
++	ret = isp_video_subdev_reset(ispvideo);
++
++
++	ret = isp_video_subdev_init(ispvideo);
++
++
++	ret = isp_video_subdev_stream(ispvideo, 1);
++
++	if(ret < 0) {
++		goto err_start_stream;
++	}
++
++	mutex_unlock(&ispvideo->stream_lock);
++
++	return 0;
++
++err_start_stream:
++	media_entity_pipeline_stop(entity);
++err_pipeline_start:
++	mutex_unlock(&ispvideo->stream_lock);
++	return ret;
++}
++static void isp_video_stop_streaming(struct vb2_queue *q)
++{
++	struct isp_video_ctx *ctx = vb2_get_drv_priv(q);
++	struct isp_video_device *ispvideo = ctx->ispvideo;
++	struct media_entity *entity = &ispvideo->video.entity;
++	//struct isp_pipeline *pipe = &ispvideo->pipe;
++	struct v4l2_subdev *sd = NULL;
++	struct media_pad *pad = NULL;
++	unsigned int is_streaming = 0;
++	int ret = 0;
++
++	mutex_lock(&ispvideo->stream_lock);
++
++	is_streaming = vb2_is_streaming(q);
++
++	if(!is_streaming)
++		goto done;
++
++	/*subdevs stream off.*/
++	while(1) {
++		pad = &entity->pads[0];
++		/*直到找到该pipeline上的仅有一个FL_SOURCE pad设备.*/
++		if(!(pad->flags & MEDIA_PAD_FL_SINK))
++			break;
++
++		pad = media_entity_remote_pad(pad);
++		if (pad == NULL ||
++				media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
++			break;
++		entity = pad->entity;
++		sd = media_entity_to_v4l2_subdev(entity);
++
++		/*stream on*/
++		v4l2_set_subdev_hostdata(sd, ispvideo);
++		ret = v4l2_subdev_call(sd, video, s_stream, 0);
++		if(ret < 0) {
++			dev_err(ispvideo->dev, "unable to start stream[%s]\n", entity->name);
++			break;
++		}
++
++	}
++	media_entity_pipeline_stop(&ispvideo->video.entity);
++
++done:
++	mutex_unlock(&ispvideo->stream_lock);
++}
++
++static const struct vb2_ops isp_video_queue_ops = {
++        .queue_setup = isp_video_queue_setup,
++        .buf_prepare = isp_video_buffer_prepare,
++        .buf_queue = isp_video_buffer_queue,
++	.start_streaming = isp_video_start_streaming,
++	.stop_streaming = isp_video_stop_streaming,
++};
++
++
++static int isp_video_open(struct file *file)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	struct video_device *vdev = &ispvideo->video;
++	struct isp_video_ctx *ctx = NULL;
++	struct vb2_queue *queue = NULL;
++	int ret = 0;
++	printk("-----name: %s %s, %d \n", ispvideo->name, __func__, __LINE__);
++        mutex_lock(&ispvideo->mutex);
++	if(ispvideo->queue != NULL) {
++		mutex_unlock(&ispvideo->mutex);
++		return -EBUSY;
++	}
++
++	ctx = kzalloc(sizeof(struct isp_video_ctx), GFP_KERNEL);
++	if(IS_ERR_OR_NULL(ctx)) {
++		dev_err(ispvideo->ispcam->dev, "Failed to alloc ctx for isp_video_ctx\n");
++		ret = -ENOMEM;
++		goto err_ctx_alloc;
++	}
++
++	v4l2_fh_init(&ctx->fh, &ispvideo->video);
++	v4l2_fh_add(&ctx->fh);
++
++	queue = &ctx->queue;
++	queue->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
++	queue->io_modes = VB2_MMAP;
++	queue->drv_priv = ctx;
++	queue->ops = &isp_video_queue_ops;
++	queue->mem_ops = &vb2_dma_contig_memops;
++	queue->buf_struct_size = sizeof(struct isp_video_buffer);
++	queue->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
++	queue->lock = &ispvideo->queue_lock;
++
++	ret = vb2_queue_init(&ctx->queue);
++	if(ret < 0) {
++		goto err_vb2_queue_init;
++	}
++
++	ctx->ispvideo = ispvideo;
++	vdev->queue = ispvideo->queue = queue;
++
++	file->private_data = &ctx->fh;
++
++	mutex_unlock(&ispvideo->mutex);
++
++	return 0;
++err_vb2_queue_init:
++	v4l2_fh_del(&ctx->fh);
++	kfree(ctx);
++err_ctx_alloc:
++	mutex_unlock(&ispvideo->mutex);
++	return ret;
++}
++static int isp_video_release(struct file *file)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	struct video_device *vdev = &ispvideo->video;
++	struct v4l2_fh *fh = file->private_data;
++	struct isp_video_ctx *ctx = to_isp_video_ctx(fh);
++
++	printk("-----name: %s %s, %d \n", ispvideo->name, __func__, __LINE__);
++	/*lock*/
++
++	mutex_lock(&ispvideo->mutex);
++
++	vb2_queue_release(&ctx->queue);
++	v4l2_fh_del(&ctx->fh);
++	v4l2_fh_exit(&ctx->fh);
++
++	kfree(ctx);
++	file->private_data = NULL;
++	vdev->queue = ispvideo->queue = NULL;
++
++	mutex_unlock(&ispvideo->mutex);
++
++	/*unlock*/
++
++	return 0;
++}
++
++#if 0
++static unsigned int isp_video_poll(struct file *file, poll_table *wait)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	struct v4l2_fh *fh = file->private_data;
++	struct isp_video_ctx *ctx = to_isp_video_ctx(fh);
++	int ret = 0;
++	printk("-----name: %s %s, %d \n", ispvideo->name, __func__, __LINE__);
++
++	mutex_lock(&ispvideo->queue_lock);
++	ret = vb2_poll(&ctx->queue, file, wait);
++	mutex_unlock(&ispvideo->queue_lock);
++
++	return ret;
++}
++
++static int isp_video_mmap(struct file *file, struct vm_area_struct *vma)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct v4l2_fh *fh = file->private_data;
++	struct isp_video_ctx *ctx = to_isp_video_ctx(fh);
++	printk("-----name: %s %s, %d \n", ispvideo->name, __func__, __LINE__);
++
++	return vb2_mmap(&ctx->queue, vma);
++}
++#endif
++
++static struct v4l2_file_operations isp_video_fops = {
++        .owner = THIS_MODULE,
++        .unlocked_ioctl = video_ioctl2,
++        .open = isp_video_open,
++        .release = isp_video_release,
++        .poll = vb2_fop_poll, /*isp_video_poll,*/
++        .mmap = vb2_fop_mmap, /*isp_video_mmap,*/
++};
++
++
++int isp_video_init(struct isp_video_device *ispvideo, char *name, const struct isp_video_ops *video_ops)
++{
++	int ret = 0;
++	struct video_device *video = &ispvideo->video;
++
++
++	/*创建buffer分�器*/
++	ispvideo->alloc_ctx = ingenic_vb2_dma_contig_init_ctx(ispvideo->ispcam->dev);
++	if(IS_ERR(ispvideo)) {
++		return -ENOMEM;
++	}
++
++	/*�始化一个sink pad*/
++	ispvideo->pad.flags = MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
++	ret = media_entity_init(&video->entity, 1, &ispvideo->pad, 0);
++	if(ret < 0) {
++		/*TODO: error case*/
++	}
++
++	mutex_init(&ispvideo->queue_lock);
++	mutex_init(&ispvideo->mutex);
++	mutex_init(&ispvideo->stream_lock);
++
++	snprintf(video->name, sizeof(video->name), "isp-%s", name);
++	video->fops = &isp_video_fops;
++	video->ioctl_ops = &isp_video_ioctl_ops;
++	video->release = video_device_release_empty;
++
++	ispvideo->name = video->name;
++	ispvideo->ops = video_ops;
++	ispvideo->dev = ispvideo->ispcam->dev;
++
++	video_set_drvdata(&ispvideo->video, ispvideo);
++
++	return 0;
++
++}
++
++int isp_video_cleanup(struct isp_video_device *ispvideo)
++{
++
++	return 0;
++}
++
++int isp_video_register(struct isp_video_device *ispvideo, struct v4l2_device *v4l2_dev)
++{
++	struct video_device *video = &ispvideo->video;
++	int ret = 0;
++
++	video->v4l2_dev = v4l2_dev;
++
++	ret = video_register_device(video, VFL_TYPE_GRABBER, -1);
++	if(ret < 0) {
++	/*TODO: error case*/
++	}
++
++	dev_info(ispvideo->dev, "register video device %s @ /dev/video%d ok\n", video->name, video->index);
++
++	return ret;
++}
++int isp_video_unregister(struct isp_video_device *ispvideo)
++{
++
++	return 0;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp-video.c b/module_drivers/drivers/media/platform/ingenic-isp/isp-video.c
+new file mode 100644
+index 000000000..5ef05bd74
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp-video.c
+@@ -0,0 +1,890 @@
++#include <linux/clk.h>
++#include <linux/media-bus-format.h>
++#include <linux/media.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_graph.h>
++#include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
++#include <linux/pm_domain.h>
++#include <linux/slab.h>
++#include <linux/videodev2.h>
++#include <linux/component.h>
++#include <linux/mutex.h>
++
++#include <media/media-device.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-event.h>
++#include <media/v4l2-ioctl.h>
++#include <media/v4l2-dev.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++
++#include "isp-drv.h"
++#define ISP_VIDEO_DRIVER_NAME	"ispvideo"
++
++int isp_max_buffer_num = 3;
++module_param(isp_max_buffer_num, int, 0644);
++MODULE_PARM_DESC(isp_max_buffer_num, "isp max buffer numer");
++
++int isp_force_img_depth = 12;
++module_param(isp_force_img_depth, int, 0644);
++MODULE_PARM_DESC(isp_force_img_depth, "force fmt depth, usefull when need mem more than real fmt.");
++
++static struct v4l2_subdev *
++isp_video_remote_subdev(struct isp_video_device *ispvideo, u32 *pad)
++{
++        struct media_pad *remote;
++
++        remote = media_entity_remote_pad(&ispvideo->pad);
++
++        if (remote == NULL || !is_media_entity_v4l2_subdev(remote->entity))
++                return NULL;
++
++	if (pad)
++                *pad = remote->index;
++
++        return media_entity_to_v4l2_subdev(remote->entity);
++}
++
++
++/* -----------------------------------------------------------------------------
++ * V4L2 ioctls
++ */
++
++static int
++isp_video_querycap(struct file *file, void *fh, struct v4l2_capability *cap)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++
++        strlcpy(cap->driver, ISP_VIDEO_DRIVER_NAME, sizeof(cap->driver));
++        strlcpy(cap->card, ispvideo->video.name, sizeof(cap->card));
++        strlcpy(cap->bus_info, "media", sizeof(cap->bus_info));
++
++	cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING | V4L2_CAP_DEVICE_CAPS;
++
++	cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
++
++        return 0;
++}
++
++static int isp_video_enum_fmt_vid_cap(struct file *file, void *fh,
++					    struct v4l2_fmtdesc *f)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	const struct isp_video_format *fmt = NULL;
++
++	fmt = ispvideo->ops->find_format(NULL, NULL, f->index);
++	if(fmt == NULL) {
++		return -EINVAL;
++	}
++	strlcpy(f->description, fmt->name, sizeof(f->description));
++	f->pixelformat = fmt->fourcc;
++
++	return 0;
++}
++static int
++isp_video_g_fmt_vid_cap(struct file *file, void *fh, struct v4l2_format *format)
++{
++        struct isp_video_ctx *ctx = to_isp_video_ctx(fh);
++        struct isp_video_device *ispvideo = video_drvdata(file);
++
++        //mutex_lock(&ispvideo->mutex);
++	if(ctx->format.type == 0) {
++		dev_warn(ispvideo->dev, "Format not setted before calling g_fmt\n");
++	} else {
++        	*format = ctx->format;
++	}
++        //mutex_unlock(&ispvideo->mutex);
++
++        return 0;
++}
++
++static int
++__isp_video_try_format(struct isp_video_ctx *ctx, struct v4l2_pix_format *pix,
++		const struct isp_video_format **ofmt)
++{
++	struct isp_video_format *fmt = NULL;
++	struct isp_video_device *ispvideo = ctx->ispvideo;
++	unsigned int depth = 0;
++	unsigned int use_depth = 0;
++	int i;
++
++	fmt = ispvideo->ops->find_format(&pix->pixelformat, NULL, -1);
++	if(fmt == NULL) {
++		dev_err(ispvideo->dev, "Cannot find appropriate format for pix->pixelformat:[%x]\n", pix->pixelformat);
++		return -EINVAL;
++	}
++
++	for(i = 0; i < fmt->num_planes; i++) {
++		depth += fmt->depth[i];
++	}
++
++	pix->colorspace = fmt->colorspace;
++	pix->field = V4L2_FIELD_NONE;
++	pix->pixelformat = fmt->fourcc;
++	pix->bytesperline = pix->width * depth / 8;
++	//pix->sizeimage = pix->bytesperline * pix->height;
++
++	use_depth = isp_force_img_depth > depth ? isp_force_img_depth : depth;
++	pix->sizeimage = pix->width * use_depth / 8 * pix->height;
++
++	ctx->uv_offset = pix->width * fmt->depth[0] * pix->height / 8;
++	ctx->payload_size = pix->bytesperline * pix->height;
++
++	if(ofmt) {
++		*ofmt = fmt;
++	}
++
++	/*TODO, bound width and height!*/
++	//printk("=======%s,%d, pixelformat: %x, widht: %d, height: %d, num_planes: %d, uv_offset: %d\n", __func__, __LINE__, pix->pixelformat, pix->width, pix->height, fmt->num_planes, ctx->uv_offset);
++
++	return 0;
++}
++
++static void to_v4l2_mbus_framefmt(struct isp_video_device *ispvideo, struct v4l2_format *format, struct v4l2_mbus_framefmt *fmt)
++{
++	struct v4l2_pix_format *pix = &format->fmt.pix;
++	struct isp_video_format *ispfmt = NULL;
++
++	ispfmt = ispvideo->ops->find_format(&pix->pixelformat, NULL, -1);
++
++	fmt->width = pix->width;
++	fmt->height = pix->height;
++	fmt->code = ispfmt->mbus_code;
++	fmt->field = pix->field;
++	fmt->colorspace = pix->colorspace;
++	fmt->ycbcr_enc = pix->ycbcr_enc;
++	fmt->quantization = pix->quantization;
++	fmt->xfer_func = pix->xfer_func;
++}
++
++static int
++isp_video_s_fmt_vid_cap(struct file *file, void *fh, struct v4l2_format *format)
++{
++        struct isp_video_ctx *ctx = to_isp_video_ctx(fh);
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	struct v4l2_subdev *sd = NULL;
++	struct v4l2_subdev_format subdev_fmt;
++	unsigned int pad = 0;
++	int ret = 0;
++
++
++	if(vb2_is_busy(&ctx->queue)) {
++		return -EBUSY;
++	}
++
++	ret = __isp_video_try_format(ctx, &format->fmt.pix, NULL);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "Failed to set format cap!\n");
++		return -EINVAL;
++	}
++
++	sd = isp_video_remote_subdev(ispvideo, &pad);
++	if(sd == NULL) {
++		return -EINVAL;
++	}
++	v4l2_set_subdev_hostdata(sd, ispvideo);
++
++	ctx->format = *format;
++
++	to_v4l2_mbus_framefmt(ispvideo, format, &subdev_fmt.format);
++
++	subdev_fmt.pad = pad;
++	subdev_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++
++	ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &subdev_fmt);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "Failed to set subdev format\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int
++isp_video_try_format_cap(struct file *file, void *fh, struct v4l2_format *format)
++{
++        struct isp_video_ctx *ctx = to_isp_video_ctx(fh);
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	int ret = 0;
++
++	ret = __isp_video_try_format(ctx, &format->fmt.pix, NULL);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "Try format cap error!\n");
++		return -EINVAL;
++	}
++	return 0;
++}
++
++static int isp_video_pixelaspect(struct file *file, void *fh, int buf_type, struct v4l2_fract *aspect)
++{
++	printk("-----------%s, %d------------\n", __func__, __LINE__);
++	return 0;
++}
++
++static int
++isp_video_get_selection(struct file *file, void *fh, struct v4l2_selection *s)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct v4l2_subdev *sd = NULL;
++	struct v4l2_subdev_selection sel = {0};
++	int ret = 0;
++	int pad = 0;
++
++	sd = isp_video_remote_subdev(ispvideo, &pad);
++	sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	sel.pad = pad;
++	sel.target = s->target;
++	ret = v4l2_subdev_call(sd, pad, get_selection, NULL, &sel);
++	memcpy(&s->r, &sel.r, sizeof(struct v4l2_rect));
++
++	return ret;
++}
++
++static int
++isp_video_set_selection(struct file *file, void *fh, struct v4l2_selection *s)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++        struct isp_video_ctx *ctx = to_isp_video_ctx(fh);
++	struct v4l2_format *format = &ctx->format;
++	struct v4l2_subdev *sd = NULL;
++	struct v4l2_subdev_selection sel;
++	int ret = 0;
++	int pad = 0;
++
++	sd = isp_video_remote_subdev(ispvideo, &pad);
++	sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	sel.pad = pad;
++	sel.flags = s->flags;
++	sel.target = s->target;
++	memcpy(&sel.r, &s->r, sizeof(struct v4l2_rect));
++	ret = v4l2_subdev_call(sd, pad, set_selection, NULL, &sel);
++	if(ret)
++		return ret;
++
++	format->fmt.pix.width = sel.r.width;
++	format->fmt.pix.height = sel.r.height;
++	ret = __isp_video_try_format(ctx, &format->fmt.pix, NULL);
++
++	return ret;
++}
++
++static int isp_video_enum_input(struct file *file, void *priv,
++				 struct v4l2_input *inp)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++
++	if (inp->index != 0)
++		return -EINVAL;
++
++	/* default is camera */
++	inp->type = V4L2_INPUT_TYPE_CAMERA;
++	inp->std = ispvideo->video.tvnorms;
++	strcpy(inp->name, "Camera");
++
++	return 0;
++}
++
++static int isp_video_g_input(struct file *file, void *priv, unsigned int *i)
++{
++	*i = 0;
++
++	return 0;
++}
++
++static int isp_video_s_input(struct file *file, void *priv, unsigned int i)
++{
++	if (i > 0)
++		return -EINVAL;
++
++	return 0;
++}
++
++int isp_video_enum_framesizes(struct file *file, void *fh, struct v4l2_frmsizeenum *fsize)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct mscaler_device 	*mscaler= ispcam->mscaler;
++	struct v4l2_subdev_frame_size_enum fse;
++	int ret = 0;
++
++	fse.code = fsize->pixel_format;
++	fse.index = fsize->index;
++
++	ret = v4l2_subdev_call(&mscaler->sd, pad, enum_frame_size, NULL, &fse);
++	if (ret < 0)
++		return ret;
++
++	fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
++	fsize->discrete.width = fse.min_width;
++	fsize->discrete.height = fse.min_height;
++	return 0;
++}
++
++int isp_video_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a){
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct isp_async_device	*isd	= &ispcam->isd[0];
++	int ret = 0;
++	struct v4l2_subdev_frame_interval interval;
++
++	interval.pad = 0;
++	ret = v4l2_subdev_call(isd->sd, video, g_frame_interval, &interval);
++	if(ret < 0) {
++		return ret;
++	}
++
++	a->parm.capture.timeperframe.numerator = interval.interval.numerator;
++	a->parm.capture.timeperframe.denominator = interval.interval.denominator;
++
++	return 0;
++}
++
++extern int isp_video_s_ctrl(struct file *file, void *fh, struct v4l2_control *a);
++extern int isp_video_g_ctrl(struct file *file, void *fh, struct v4l2_control *a);
++
++extern int bypass_video_s_ctrl(struct file *file, void *fh, struct v4l2_control *a);
++extern int bypass_video_g_ctrl(struct file *file, void *fh, struct v4l2_control *a);
++
++static const struct v4l2_ioctl_ops isp_video_ioctl_ops = {
++	.vidioc_querycap                = isp_video_querycap,
++	.vidioc_enum_fmt_vid_cap	= isp_video_enum_fmt_vid_cap,
++	.vidioc_g_fmt_vid_cap    	= isp_video_g_fmt_vid_cap,
++	.vidioc_s_fmt_vid_cap   	= isp_video_s_fmt_vid_cap,
++	.vidioc_try_fmt_vid_cap  	= isp_video_try_format_cap,
++	.vidioc_g_pixelaspect		= isp_video_pixelaspect,
++	.vidioc_g_selection		= isp_video_get_selection,
++	.vidioc_s_selection		= isp_video_set_selection,
++	.vidioc_reqbufs                 = vb2_ioctl_reqbufs,
++	.vidioc_querybuf                = vb2_ioctl_querybuf,
++	.vidioc_qbuf                    = vb2_ioctl_qbuf,
++	.vidioc_dqbuf                   = vb2_ioctl_dqbuf,
++	.vidioc_expbuf			= vb2_ioctl_expbuf,
++	.vidioc_streamon                = vb2_ioctl_streamon,
++	.vidioc_streamoff               = vb2_ioctl_streamoff,
++	.vidioc_enum_input		= isp_video_enum_input,
++	.vidioc_g_input			= isp_video_g_input,
++	.vidioc_s_input			= isp_video_s_input,
++	.vidioc_enum_framesizes		= isp_video_enum_framesizes,
++	.vidioc_g_parm			= isp_video_g_parm,
++	.vidioc_s_ctrl			= isp_video_s_ctrl,
++	.vidioc_g_ctrl			= isp_video_g_ctrl,
++};
++
++static const struct v4l2_ioctl_ops bypass_video_ioctl_ops = {
++        .vidioc_querycap                = isp_video_querycap,	/**/
++	.vidioc_enum_fmt_vid_cap	= isp_video_enum_fmt_vid_cap,
++        .vidioc_g_fmt_vid_cap    	= isp_video_g_fmt_vid_cap,
++        .vidioc_s_fmt_vid_cap   	= isp_video_s_fmt_vid_cap,
++        .vidioc_try_fmt_vid_cap  	= isp_video_try_format_cap,
++	.vidioc_g_pixelaspect		= isp_video_pixelaspect,
++        .vidioc_reqbufs                 = vb2_ioctl_reqbufs,
++        .vidioc_querybuf                = vb2_ioctl_querybuf,
++        .vidioc_qbuf                    = vb2_ioctl_qbuf,
++        .vidioc_dqbuf                   = vb2_ioctl_dqbuf,
++	.vidioc_expbuf			= vb2_ioctl_expbuf,
++        .vidioc_streamon                = vb2_ioctl_streamon,
++        .vidioc_streamoff               = vb2_ioctl_streamoff,
++	.vidioc_enum_input		= isp_video_enum_input,	/**/
++	.vidioc_g_input			= isp_video_g_input,
++	.vidioc_s_input			= isp_video_s_input,
++	.vidioc_enum_framesizes		= isp_video_enum_framesizes,
++	.vidioc_g_parm			= isp_video_g_parm,  /**/
++	.vidioc_s_ctrl			= bypass_video_s_ctrl,
++	.vidioc_g_ctrl			= bypass_video_g_ctrl,
++};
++
++/* -----------------------------------------------------------------------------
++ * Video queue operations
++ */
++
++static int isp_video_queue_setup(struct vb2_queue *queue,
++                                 unsigned int *count, unsigned int *num_planes,
++                                 unsigned int sizes[], struct device *alloc_ctxs[])
++{
++        struct isp_video_ctx *ctx = vb2_get_drv_priv(queue);
++        struct isp_video_device *ispvideo = ctx->ispvideo;
++	struct v4l2_format *format = &ctx->format;
++
++	*num_planes = 1;
++
++	sizes[0] = format->fmt.pix.sizeimage;
++	if(sizes[0] == 0) {
++		dev_err(ispvideo->dev, "queue setup 0 sizeimage\n");
++		return -EINVAL;
++	}
++
++	alloc_ctxs[0] = ispvideo->ispcam->dev;
++
++	/*MAX_BUFFER_NUMS:*/
++	if(ispvideo->bypass)
++		isp_max_buffer_num = 5;
++	if(*count >= isp_max_buffer_num) {
++		*count = isp_max_buffer_num;
++	}
++
++	ispvideo->max_buffer_num = *count;
++
++        return 0;
++}
++
++static int isp_video_buffer_prepare(struct vb2_buffer *buf)
++{
++	struct isp_video_ctx *ctx = vb2_get_drv_priv(buf->vb2_queue);
++
++	//vb2_set_plane_payload(buf, 0, format->fmt.pix.sizeimage);
++	vb2_set_plane_payload(buf, 0, ctx->payload_size);
++        return 0;
++}
++
++static void isp_video_buffer_queue(struct vb2_buffer *buf)
++{
++        struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(buf);
++	struct isp_video_ctx *ctx = vb2_get_drv_priv(buf->vb2_queue);
++	struct isp_video_buffer *isp_buffer = to_isp_buffer(vbuf);
++	struct isp_video_device *ispvideo = ctx->ispvideo;
++	int ret = 0;
++
++	isp_buffer->uv_offset = ctx->uv_offset;
++
++	ret = ispvideo->ops->qbuf(ispvideo, isp_buffer);
++	if(ret < 0) {
++		dev_err(ispvideo->dev, "failed to queue buf!\n");
++	}
++}
++
++static int isp_video_subdev_init(struct isp_video_device *ispvideo)
++{
++	struct media_entity *entity = &ispvideo->video.entity;
++	struct v4l2_subdev *sd = NULL;
++	struct media_pad *pad = NULL;
++	int ret = 0;
++
++	/*subdevs reset.*/
++	while(1) {
++		pad = &entity->pads[0];
++		/*直到找到该pipeline上的仅有一个FL_SOURCE pad设备.*/
++		if(!(pad->flags & MEDIA_PAD_FL_SINK))
++			break;
++
++		pad = media_entity_remote_pad(pad);
++		if (pad == NULL || !is_media_entity_v4l2_subdev(pad->entity))
++			break;
++		entity = pad->entity;
++		sd = media_entity_to_v4l2_subdev(entity);
++
++		/*stream on*/
++		v4l2_set_subdev_hostdata(sd, ispvideo);
++		ret = v4l2_subdev_call(sd, core, init, 1);
++		if(ret < 0 && ret != -ENOIOCTLCMD) {
++			dev_err(ispvideo->dev, "failed to reset subdev[%s]\n", entity->name);
++		} else {
++			ret = 0;
++		}
++	}
++
++	return ret;
++}
++
++static int isp_video_subdev_reset(struct isp_video_device *ispvideo)
++{
++	struct media_entity *entity = &ispvideo->video.entity;
++	struct v4l2_subdev *sd = NULL;
++	struct media_pad *pad = NULL;
++	int ret = 0;
++
++	/*subdevs reset.*/
++	while(1) {
++		pad = &entity->pads[0];
++		/*直到找到该pipeline上的仅有一个FL_SOURCE pad设备.*/
++		if(!(pad->flags & MEDIA_PAD_FL_SINK))
++			break;
++
++		pad = media_entity_remote_pad(pad);
++		if (pad == NULL || !is_media_entity_v4l2_subdev(pad->entity))
++			break;
++		entity = pad->entity;
++		sd = media_entity_to_v4l2_subdev(entity);
++
++		/*stream on*/
++		v4l2_set_subdev_hostdata(sd, ispvideo);
++		ret = v4l2_subdev_call(sd, core, reset, 1);
++		if(ret < 0 && ret != -ENOIOCTLCMD) {
++			dev_err(ispvideo->dev, "failed to reset subdev[%s]\n", entity->name);
++		} else {
++			ret = 0;
++		}
++	}
++
++	return ret;
++
++}
++
++
++static int isp_video_subdev_streamon(struct isp_video_device *ispvideo)
++{
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct mscaler_device 	*mscaler= ispcam->mscaler;
++	struct isp_device 	*isp	= ispcam->isp;
++	struct vic_device	*vic	= ispcam->vic;
++	struct csi_device 	*csi	= ispcam->csi;
++	struct isp_async_device	*isd	= &ispcam->isd[0];
++	int ret = 0;
++
++	if(!ispvideo->bypass) {
++		v4l2_set_subdev_hostdata(&mscaler->sd, ispvideo);
++		ret = v4l2_subdev_call(&mscaler->sd, video, s_stream, 1);
++		if(ret < 0) {
++			goto err;
++		}
++
++		ret = v4l2_subdev_call(&isp->sd, video, s_stream, 1);
++		if(ret < 0) {
++			goto err;
++		}
++	}
++
++	if(csi && (isd->bus_type == V4L2_MBUS_CSI2_DPHY)) {
++		ret = v4l2_subdev_call(&csi->sd, video, s_stream, 1);
++		if(ret < 0) {
++			goto err;
++		}
++	}
++
++	if(!isd->enabled) {
++		ret = v4l2_subdev_call(isd->sd, video, s_stream, 1);
++		if(ret < 0) {
++			goto err;
++		}
++	}
++	isd->enabled++;
++
++	ret = v4l2_subdev_call(&vic->sd, video, s_stream, 1);
++	if(ret < 0) {
++		goto err;
++	}
++
++	return ret;
++err:
++	dev_err(ispvideo->dev, "start stream error\n");
++	return ret;
++}
++
++static int isp_video_subdev_streamoff(struct isp_video_device *ispvideo)
++{
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct mscaler_device 	*mscaler= ispcam->mscaler;
++	struct isp_device 	*isp	= ispcam->isp;
++	struct vic_device	*vic	= ispcam->vic;
++	struct csi_device 	*csi	= ispcam->csi;
++	struct isp_async_device	*isd	= &ispcam->isd[0];
++	int ret = 0;
++
++	//global ispcam device mutex.
++	if(!ispvideo->bypass) {
++		v4l2_set_subdev_hostdata(&mscaler->sd, ispvideo);
++		ret = v4l2_subdev_call(&mscaler->sd, video, s_stream, 0);
++		if(ret < 0) {
++			goto err;
++		}
++
++		ret = v4l2_subdev_call(&isp->sd, video, s_stream, 0);
++		if(ret < 0) {
++			goto err;
++		}
++	}
++
++	if(csi && (isd->bus_type == V4L2_MBUS_CSI2_DPHY)) {
++		ret = v4l2_subdev_call(&csi->sd, video, s_stream, 0);
++		if(ret < 0) {
++			goto err;
++		}
++	}
++
++	isd->enabled--;
++	if(!isd->enabled) {
++		ret = v4l2_subdev_call(isd->sd, video, s_stream, 0);
++		if(ret < 0) {
++			goto err;
++		}
++	}
++
++	ret = v4l2_subdev_call(&vic->sd, video, s_stream, 0);
++	if(ret < 0) {
++		goto err;
++	}
++
++	return ret;
++err:
++	dev_err(ispvideo->dev, "start stream error\n");
++	return ret;
++
++}
++
++static int isp_video_subdev_stream(struct isp_video_device *ispvideo, int enable)
++{
++	int ret = 0;
++
++	if(enable) {
++		ret = isp_video_subdev_streamon(ispvideo);
++	} else {
++		ret = isp_video_subdev_streamoff(ispvideo);
++	}
++
++	return ret;
++}
++
++static int isp_video_start_streaming(struct vb2_queue *q, unsigned int count)
++{
++	struct isp_video_ctx *ctx = vb2_get_drv_priv(q);
++	struct isp_video_device *ispvideo = ctx->ispvideo;
++	struct media_entity *entity = &ispvideo->video.entity;
++	struct isp_pipeline *pipe = &ispvideo->pipe;
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	int ret = 0;
++
++	mutex_lock(&ispcam->mutex);
++
++	mutex_lock(&ispvideo->stream_lock);
++
++	if(ispcam->enabled++ == 0) {
++		ret = media_pipeline_start(entity, &pipe->pipeline);
++		if(ret < 0) {
++			dev_err(ispvideo->dev, "Failed to start pipeline\n");
++			goto err_pipeline_start;
++		}
++
++		ret = isp_video_subdev_reset(ispvideo);
++		ret = isp_video_subdev_init(ispvideo);
++	}
++
++	ret = isp_video_subdev_stream(ispvideo, 1);
++
++	if(ret < 0) {
++		goto err_start_stream;
++	}
++
++	mutex_unlock(&ispvideo->stream_lock);
++
++	mutex_unlock(&ispcam->mutex);
++	return 0;
++
++err_start_stream:
++	media_pipeline_stop(entity);
++err_pipeline_start:
++	mutex_unlock(&ispvideo->stream_lock);
++	mutex_unlock(&ispcam->mutex);
++	return ret;
++}
++static void isp_video_stop_streaming(struct vb2_queue *q)
++{
++	struct isp_video_ctx *ctx = vb2_get_drv_priv(q);
++	struct isp_video_device *ispvideo = ctx->ispvideo;
++	//struct isp_pipeline *pipe = &ispvideo->pipe;
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	unsigned int is_streaming = 0;
++	int ret = 0;
++
++	mutex_lock(&ispcam->mutex);
++
++	mutex_lock(&ispvideo->stream_lock);
++
++
++
++	is_streaming = vb2_is_streaming(q);
++
++	if(!is_streaming)
++		goto done;
++
++	ret = isp_video_subdev_stream(ispvideo, 0);
++
++	if(--ispcam->enabled > 0) {
++		goto finish;
++	}
++
++	media_pipeline_stop(&ispvideo->video.entity);
++
++finish:
++done:
++	mutex_unlock(&ispvideo->stream_lock);
++	mutex_unlock(&ispcam->mutex);
++}
++
++static const struct vb2_ops isp_video_queue_ops = {
++        .queue_setup = isp_video_queue_setup,
++        .buf_prepare = isp_video_buffer_prepare,
++        .buf_queue = isp_video_buffer_queue,
++	.start_streaming = isp_video_start_streaming,
++	.stop_streaming = isp_video_stop_streaming,
++};
++
++
++static int isp_video_open(struct file *file)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	struct video_device *vdev = &ispvideo->video;
++	struct isp_video_ctx *ctx = NULL;
++	struct vb2_queue *queue = NULL;
++	int ret = 0;
++        mutex_lock(&ispvideo->mutex);
++	if(ispvideo->queue != NULL) {
++		mutex_unlock(&ispvideo->mutex);
++		return -EBUSY;
++	}
++
++	ctx = kzalloc(sizeof(struct isp_video_ctx), GFP_KERNEL);
++	if(IS_ERR_OR_NULL(ctx)) {
++		dev_err(ispvideo->ispcam->dev, "Failed to alloc ctx for isp_video_ctx\n");
++		ret = -ENOMEM;
++		goto err_ctx_alloc;
++	}
++
++	v4l2_fh_init(&ctx->fh, &ispvideo->video);
++	v4l2_fh_add(&ctx->fh);
++
++	queue = &ctx->queue;
++	queue->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++	queue->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
++	queue->drv_priv = ctx;
++	queue->ops = &isp_video_queue_ops;
++	queue->mem_ops = &ingenic_vb2_dma_contig_memops;
++	queue->buf_struct_size = sizeof(struct isp_video_buffer);
++	queue->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
++	queue->lock = &ispvideo->queue_lock;
++
++	ret = vb2_queue_init(&ctx->queue);
++	if(ret < 0) {
++		goto err_vb2_queue_init;
++	}
++
++	ctx->ispvideo = ispvideo;
++	ctx->format.type = queue->type;
++	vdev->queue = ispvideo->queue = queue;
++
++	file->private_data = &ctx->fh;
++
++	mutex_unlock(&ispvideo->mutex);
++
++	return 0;
++err_vb2_queue_init:
++	v4l2_fh_del(&ctx->fh);
++	kfree(ctx);
++err_ctx_alloc:
++	mutex_unlock(&ispvideo->mutex);
++	return ret;
++}
++static int isp_video_release(struct file *file)
++{
++        struct isp_video_device *ispvideo = video_drvdata(file);
++	struct video_device *vdev = &ispvideo->video;
++	struct v4l2_fh *fh = file->private_data;
++	struct isp_video_ctx *ctx = to_isp_video_ctx(fh);
++
++	/*lock*/
++
++	mutex_lock(&ispvideo->mutex);
++
++	vb2_queue_release(&ctx->queue);
++	v4l2_fh_del(&ctx->fh);
++	v4l2_fh_exit(&ctx->fh);
++
++	kfree(ctx);
++	file->private_data = NULL;
++	vdev->queue = ispvideo->queue = NULL;
++
++	mutex_unlock(&ispvideo->mutex);
++
++	/*unlock*/
++
++	return 0;
++}
++
++static struct v4l2_file_operations isp_video_fops = {
++        .owner = THIS_MODULE,
++        .unlocked_ioctl = video_ioctl2,
++        .open = isp_video_open,
++        .release = isp_video_release,
++        .poll = vb2_fop_poll, /*isp_video_poll,*/
++        .mmap = vb2_fop_mmap, /*isp_video_mmap,*/
++};
++
++
++int isp_video_init(struct isp_video_device *ispvideo, char *name, const struct isp_video_ops *video_ops)
++{
++	int ret = 0;
++	struct video_device *video = &ispvideo->video;
++	struct media_entity *entity = &video->entity;
++	struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
++
++
++	/*创建buffer分�器*/
++	ispvideo->alloc_ctx = ingenic_vb2_dma_contig_init_ctx(ispvideo->ispcam->dev);
++	if(IS_ERR(ispvideo)) {
++		return -ENOMEM;
++	}
++
++	/*�始化一个sink pad*/
++	ispvideo->pad.flags = MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
++	ret = media_entity_pads_init(&video->entity, 1, &ispvideo->pad);
++	if(ret < 0) {
++		/*TODO: error case*/
++	}
++
++	sd->owner = THIS_MODULE;
++	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++	sd->entity.function = MEDIA_ENT_F_IO_V4L;
++
++	mutex_init(&ispvideo->queue_lock);
++	mutex_init(&ispvideo->mutex);
++	mutex_init(&ispvideo->stream_lock);
++
++	snprintf(video->name, sizeof(video->name), "isp-%s", name);
++	video->fops = &isp_video_fops;
++
++	if(ispvideo->bypass)
++		video->ioctl_ops = &bypass_video_ioctl_ops;
++        else
++		video->ioctl_ops = &isp_video_ioctl_ops;
++
++	video->release = video_device_release_empty;
++	video->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
++
++	ispvideo->name = video->name;
++	ispvideo->ops = video_ops;
++	ispvideo->dev = ispvideo->ispcam->dev;
++
++	video_set_drvdata(&ispvideo->video, ispvideo);
++
++	return 0;
++}
++
++int isp_video_cleanup(struct isp_video_device *ispvideo)
++{
++
++	return 0;
++}
++
++int isp_video_register(struct isp_video_device *ispvideo, struct v4l2_device *v4l2_dev, int nr)
++{
++	struct video_device *video = &ispvideo->video;
++	int ret = 0;
++
++	video->v4l2_dev = v4l2_dev;
++
++	ret = video_register_device(video, VFL_TYPE_VIDEO, nr);
++	if(ret < 0) {
++	/*TODO: error case*/
++	}
++
++	dev_info(ispvideo->dev, "register video device %s @ /dev/video%d ok\n", video->name, video->num);
++
++	return ret;
++}
++int isp_video_unregister(struct isp_video_device *ispvideo)
++{
++
++	return 0;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/isp.c b/module_drivers/drivers/media/platform/ingenic-isp/isp.c
+new file mode 100644
+index 000000000..7ddb43e7f
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/isp.c
+@@ -0,0 +1,785 @@
++#include <linux/clk.h>
++#include <linux/media-bus-format.h>
++#include <linux/media.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_graph.h>
++#include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
++#include <linux/pm_domain.h>
++#include <linux/slab.h>
++#include <linux/videodev2.h>
++#include <linux/component.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/kthread.h>
++
++#include <media/media-device.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-event.h>
++
++
++
++#include "isp-drv.h"
++#include "isp-regs.h"
++#include "tiziano_core.h"
++
++int isp_clk = 300000000;
++module_param(isp_clk, int, S_IRUGO);
++MODULE_PARM_DESC(isp_clk, "isp core clock");
++
++DEFINE_SPINLOCK(isp_cpm_lock);
++
++static inline unsigned int isp_reg_readl(struct isp_device *isp, unsigned int reg)
++{
++	return readl(isp->iobase + reg);
++}
++
++static inline void isp_reg_writel(struct isp_device *isp, unsigned int reg, unsigned int val)
++{
++	writel(val, isp->iobase + reg);
++}
++
++
++
++/* interface used by isp-core.*/
++int system_reg_write(void *isp, unsigned int reg, unsigned int value)
++{
++	isp_reg_writel(isp, reg, value);
++	return 0;
++}
++
++unsigned int  system_reg_read(void *isp, unsigned int reg)
++{
++	return isp_reg_readl(isp, reg);
++}
++
++int system_irq_func_set(void *hdl, int irq, void *func, void *data)
++{
++	struct isp_device *core = hdl;
++
++	core->irq_func_cb[irq] = func;
++	core->irq_func_data[irq] = data;
++	return 0;
++}
++
++static int isp_cpm_stop(struct isp_device *isp)
++{
++	int timeout = 0xffffff;
++	unsigned int value = 0;
++
++
++	spin_lock(&isp_cpm_lock);
++	/*stop request*/
++	value = readl(isp->cpm_reset);
++	value |= 1 << isp->bit_stp;
++	writel(value, isp->cpm_reset);
++
++	/*stop ack*/
++	while(!(readl(isp->cpm_reset) & (1 << isp->bit_ack)) && --timeout);
++
++	if(timeout == 0) {
++		spin_unlock(&isp_cpm_lock);
++		dev_err(isp->dev, "isp wait stop timeout\n");
++		return -ETIMEDOUT;
++	}
++
++	spin_unlock(&isp_cpm_lock);
++	return 0;
++}
++
++static int isp_cpm_reset(struct isp_device *isp)
++{
++	int timeout = 0xffffff;
++	unsigned int value = 0;
++	int ret = 0;
++
++
++	spin_lock(&isp_cpm_lock);
++	/*stop request*/
++	value = readl(isp->cpm_reset);
++	value |= 1 << isp->bit_stp;
++	writel(value, isp->cpm_reset);
++
++	/*stop ack*/
++	while(!(readl(isp->cpm_reset) & (1 << isp->bit_ack)) && --timeout);
++
++	if(timeout == 0) {
++		dev_err(isp->dev, "isp wait stop timeout\n");
++		ret = -ETIMEDOUT;
++		goto reset_timeout;
++	}
++
++	/* activate reset */
++	value = readl(isp->cpm_reset);
++	value &= ~(1 << isp->bit_stp);
++	value |= 1 << isp->bit_sr;
++	writel(value, isp->cpm_reset);
++
++	/* deactive reset */
++	value = readl(isp->cpm_reset);
++	value &= ~(1 << isp->bit_sr);
++	writel(value, isp->cpm_reset);
++
++	spin_unlock(&isp_cpm_lock);
++	return 0;
++
++reset_timeout:
++	spin_unlock(&isp_cpm_lock);
++	return ret;
++}
++
++static int ingenic_isp_parse_dt(struct isp_device * isp)
++{
++	struct device *dev = isp->dev;
++	unsigned int cpm_reset = 0;
++	int ret = 0;
++
++	of_property_read_u32(dev->of_node, "ingenic,cpm_reset", &cpm_reset);
++	of_property_read_u32(dev->of_node, "ingenic,bit_sr", &isp->bit_sr);
++	of_property_read_u32(dev->of_node, "ingenic,bit_stp", &isp->bit_stp);
++	of_property_read_u32(dev->of_node, "ingenic,bit_ack", &isp->bit_ack);
++
++	isp->cpm_reset = (void __iomem *)cpm_reset;
++
++	return ret;
++}
++
++
++/* interface should be removed. */
++static int isp_subdev_init(struct v4l2_subdev *sd, u32 val)
++{
++
++	return 0;
++}
++
++/* interface should be removed. */
++static int isp_subdev_reset(struct v4l2_subdev *sd, u32 val)
++{
++	struct isp_device *isp = v4l2_get_subdevdata(sd);
++	int ret = 0;
++
++	ret = isp_cpm_reset(isp);
++
++	return ret;
++}
++
++static const struct v4l2_subdev_core_ops isp_subdev_core_ops = {
++	.init	= isp_subdev_init,
++	.reset = isp_subdev_reset,
++        .log_status = v4l2_ctrl_subdev_log_status,
++        .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
++        .unsubscribe_event = v4l2_event_subdev_unsubscribe,
++};
++
++static int isp_subdev_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct isp_device *isp = v4l2_get_subdevdata(sd);
++	struct media_pad *remote = NULL;
++	struct v4l2_subdev *remote_sd = NULL;
++	struct v4l2_subdev_format remote_subdev_fmt;
++	int ret = 0;
++
++	remote = media_entity_remote_pad(&isp->pads[ISP_PAD_SINK]);
++	remote_sd = media_entity_to_v4l2_subdev(remote->entity);
++
++	/*获��当�格�，�制到输出格�.*/
++	remote_subdev_fmt.pad = remote->index;
++	remote_subdev_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	ret = v4l2_subdev_call(remote_sd, pad, get_fmt, NULL, &remote_subdev_fmt);
++	if(ret < 0) {
++		dev_err(isp->dev, "Failed to get_fmt from remote pad\n");
++		return -EINVAL;
++	}
++
++	/*本身ISP时没有格�区别的， 这里必须从VIC获�，�ISP的SINK_PAD.*/
++	if(format->pad == ISP_PAD_SOURCE) {
++		memcpy(&format->format, &remote_subdev_fmt.format, sizeof(format->format));
++	} else {
++		dev_warn(isp->dev, "ISP_PAD_SOURCE should be set!\n");
++	}
++
++	isp->formats[ISP_PAD_SINK] = isp->formats[ISP_PAD_SOURCE] = *format;
++	isp->sensor_info = (struct sensor_info *)*(unsigned int *)format->format.reserved;
++
++	//printk("----%s, %d, format->pad: %d\n", __func__, __LINE__, format->pad);
++	return 0;
++}
++
++static int isp_subdev_set_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct isp_device *isp = v4l2_get_subdevdata(sd);
++	struct media_pad *remote = NULL;
++	struct v4l2_subdev *remote_sd = NULL;
++	int ret = 0;
++
++	remote = media_entity_remote_pad(&isp->pads[ISP_PAD_SINK]);
++	remote_sd = media_entity_to_v4l2_subdev(remote->entity);
++
++	ret = v4l2_subdev_call(remote_sd, pad, set_fmt, NULL, format);
++	if(ret < 0) {
++		dev_dbg(isp->dev, "Failed to set_fmt from remote pad\n");
++	}
++
++	return 0;
++}
++
++static const struct v4l2_subdev_pad_ops isp_subdev_pad_ops = {
++        .set_fmt                = isp_subdev_set_fmt,
++        .get_fmt                = isp_subdev_get_fmt,
++	/*
++        .init_cfg               = isp_subdev_init_cfg,
++        .enum_mbus_code         = isp_subdev_enum_mbus_code,
++        .enum_frame_size        = isp_subdev_enum_frame_size,
++	*/
++};
++
++enum isp_bayer_type {
++	TIZIANO_BAYER_TYPE_RGGB = 0,
++	TIZIANO_BAYER_TYPE_BGGR,
++	TIZIANO_BAYER_TYPE_GRBG,
++	TIZIANO_BAYER_TYPE_GBRG
++};
++
++
++static int isp_fw_process(void *data)
++{
++        struct isp_device *isp = (struct isp_device *)data;
++
++        while(!kthread_should_stop()){
++                tisp_fw_process(&isp->core);
++        }
++        return 0;
++}
++
++
++static int isp_load_params(struct isp_device *isp)
++{
++	struct v4l2_subdev_format *input_fmt = &isp->formats[ISP_PAD_SINK];
++	struct ispcam_device *ispcam = isp->ispcam;
++	unsigned int ret = 0;
++	struct file *file = NULL;
++	struct inode *inode = NULL;
++	mm_segment_t old_fs;
++	loff_t fsize = 0;
++	loff_t *pos = NULL;
++
++	char file_name[64] = {0};
++
++	old_fs = get_fs();
++	set_fs(KERNEL_DS);
++
++	snprintf(file_name, sizeof(file_name), "/etc/sensor/%s-%s-%d-%d.bin", ispcam->isd[0].sd->dev->driver->name, ispcam->chip_name, input_fmt->format.width, input_fmt->format.height);
++	file = filp_open(file_name, O_RDONLY, 0);
++	if (file < 0 || IS_ERR(file)) {
++		dev_dbg(isp->dev, "ISP: open %s file for isp calibrate read failed\n", file_name);
++
++		snprintf(file_name, sizeof(file_name), "/etc/sensor/%s-%s.bin", ispcam->isd[0].sd->dev->driver->name, ispcam->chip_name);
++		file = filp_open(file_name, O_RDONLY, 0);
++		if (file < 0 || IS_ERR(file)) {
++			dev_dbg(isp->dev, "ISP: open %s file for isp calibrate read failed\n", file_name);
++			ret = -1;
++			isp->core.tuned_params = NULL;
++			goto failed_open_file;
++		}
++	}
++
++	/* read file */
++	inode = file->f_inode;
++	fsize = inode->i_size;
++	pos = &(file->f_pos);
++
++	if(isp->core.tuned_params == NULL){
++		isp->core.tuned_params = kzalloc(fsize, GFP_KERNEL);
++		if(isp->core.tuned_params == NULL){
++			dev_err(isp->dev, "%s[%d]: Failed to alloc %lld KB buffer!\n",__func__,__LINE__, fsize >> 10);
++			ret = -1;
++			goto failed_malloc_data;
++		}
++		isp->core.tuned_params_size = fsize;
++	}
++
++	vfs_read(file, isp->core.tuned_params, fsize, pos);
++
++failed_malloc_data:
++	filp_close(file, NULL);
++	set_fs(old_fs);
++failed_open_file:
++	return ret;
++}
++
++static int isp_release_params(struct isp_device *isp)
++{
++	if(isp->core.tuned_params) {
++		kfree(isp->core.tuned_params);
++		isp->core.tuned_params = NULL;
++		isp->core.tuned_params_size = 0;
++	}
++
++	return 0;
++}
++
++static int isp_subdev_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct isp_device *isp = v4l2_get_subdevdata(sd);
++	struct ispcam_device *ispcam = isp->ispcam;
++	struct v4l2_subdev_format *input_fmt = &isp->formats[ISP_PAD_SINK];
++
++	tisp_init_param_t iparam;
++
++	if(enable) {
++
++		if(isp->enabled++ > 0) {
++			return 0;
++		}
++
++		iparam.width = input_fmt->format.width;
++		iparam.height = input_fmt->format.height;
++
++
++		switch(input_fmt->format.code) {
++			case MEDIA_BUS_FMT_SBGGR8_1X8:
++			case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
++			case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE:
++			case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
++			case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE:
++			case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE:
++			case MEDIA_BUS_FMT_SBGGR10_1X10:
++			case MEDIA_BUS_FMT_SBGGR12_1X12:
++				//				printk("BGGR\n");
++				iparam.bayer = 2;
++				break;
++			case MEDIA_BUS_FMT_SGBRG8_1X8:
++			case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
++			case MEDIA_BUS_FMT_SGBRG10_1X10:
++			case MEDIA_BUS_FMT_SGBRG12_1X12:
++				//				printk("GBRG\n");
++				iparam.bayer = 3;
++				break;
++			case MEDIA_BUS_FMT_SGRBG8_1X8:
++			case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
++			case MEDIA_BUS_FMT_SGRBG10_1X10:
++			case MEDIA_BUS_FMT_SGRBG12_1X12:
++				iparam.bayer = 1;
++				//				printk("GRBG\n");
++				break;
++			case MEDIA_BUS_FMT_SRGGB8_1X8:
++			case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
++			case MEDIA_BUS_FMT_SRGGB10_1X10:
++			case MEDIA_BUS_FMT_SRGGB12_1X12:
++				iparam.bayer = 0;
++				//				printk("RGGB\n");
++				break;
++			default:
++				dev_err(isp->dev, "%s[%d] the format(0x%08x) of input couldn't be handled!\n",
++						__func__,__LINE__, input_fmt->format.code);
++				return -EINVAL;
++				break;
++		}
++
++
++		strncpy(iparam.sensor, ispcam->isd[0].sd->dev->driver->name, sizeof(iparam.sensor));
++		iparam.sensor_info.fps = isp->sensor_info->fps;
++		iparam.sensor_info.total_width = isp->sensor_info->total_width;
++		iparam.sensor_info.total_height = isp->sensor_info->total_height;
++
++
++		isp_load_params(isp);
++		tisp_core_init(&isp->core, &iparam, isp);
++		isp->core_inited = 1;
++		isp_core_tuning_param_sync(&isp->core);
++
++		isp_release_params(isp);
++
++		/*For event engine.*/
++		isp->process_thread = kthread_run(isp_fw_process, isp, "isp_fw_process");
++		if(IS_ERR_OR_NULL(isp->process_thread)){
++			dev_err(isp->dev, "%s[%d] kthread_run was failed!\n",__func__,__LINE__);
++			return -EINVAL;
++		}
++
++
++		isp_reg_writel(isp, TOP_CTRL_ADDR_INT_EN, 0x283f03ff);
++#if 0
++		iparam.sensor_info.max_again = core->vin.attr->max_again;       //the format is .16
++		iparam.sensor_info.max_dgain = core->vin.attr->max_dgain;       //the format is .16
++		iparam.sensor_info.again = core->vin.attr->again;
++		iparam.sensor_info.dgain = core->vin.attr->dgain;
++		iparam.sensor_info.fps = core->vin.fps;
++		iparam.sensor_info.min_integration_time = core->vin.attr->min_integration_time;
++		iparam.sensor_info.min_integration_time_native = core->vin.attr->min_integration_time_native;
++		iparam.sensor_info.max_integration_time_native = core->vin.attr->max_integration_time_native;
++		iparam.sensor_info.integration_time_limit = core->vin.attr->integration_time_limit;
++		iparam.sensor_info.integration_time = core->vin.attr->integration_time;
++		iparam.sensor_info.total_width = core->vin.attr->total_width;
++		iparam.sensor_info.total_height = core->vin.attr->total_height;
++		iparam.sensor_info.max_integration_time = core->vin.attr->max_integration_time;
++		iparam.sensor_info.integration_time_apply_delay = core->vin.attr->integration_time_apply_delay;
++		iparam.sensor_info.again_apply_delay = core->vin.attr->again_apply_delay;
++		iparam.sensor_info.dgain_apply_delay = core->vin.attr->dgain_apply_delay;
++		iparam.sensor_info.one_line_expr_in_us = core->vin.attr->one_line_expr_in_us;
++#endif
++
++	} else {
++
++		if(--isp->enabled > 0) {
++			return 0;
++		}
++		/*disable irq.*/
++		isp_reg_writel(isp, TOP_CTRL_ADDR_INT_EN, 0);
++		/* isp tirger */
++		isp_reg_writel(isp, INPUT_CTRL_ADDR_IP_TRIG, 0x0);
++
++		kthread_stop(isp->process_thread);
++
++		tisp_core_deinit(&isp->core);
++		isp->core_inited = 0;
++
++	}
++
++	return 0;
++}
++
++
++static const struct v4l2_subdev_video_ops isp_subdev_video_ops = {
++        .s_stream = isp_subdev_s_stream,
++};
++
++
++static const struct v4l2_subdev_ops isp_subdev_ops = {
++        .core = &isp_subdev_core_ops,
++        .pad = &isp_subdev_pad_ops,
++        .video = &isp_subdev_video_ops,
++};
++static ssize_t
++dump_isp(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct isp_device *isp = dev_get_drvdata(dev);
++	char *p = buf;
++
++	p += sprintf(p, "TOP_CTRL_ADDR_VERSION            :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_VERSION            ));
++	p += sprintf(p, "TOP_CTRL_ADDR_FM_SIZE            :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_FM_SIZE            ));
++	p += sprintf(p, "TOP_CTRL_ADDR_BAYER_TYPE         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_BAYER_TYPE         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_BYPASS_CON         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_BYPASS_CON         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TOP_CON            :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TOP_CON            ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TOP_STATE          :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TOP_STATE          ));
++	p += sprintf(p, "TOP_CTRL_ADDR_LINE_SPACE         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_LINE_SPACE         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_REG_CON            :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_REG_CON            ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_RC_TRIG        :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_RC_TRIG        ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_RC_CON         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_RC_CON         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_RC_ADDR        :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_RC_ADDR        ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_RC_STATE       :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_RC_STATE       ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_RC_APB_WR_DATA :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_RC_APB_WR_DATA ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_RC_APB_WR_ADDR :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_RC_APB_WR_ADDR ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_RD_CON         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_RD_CON         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_WR_CON         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_WR_CON         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_FR_WR_CON      :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_FR_WR_CON      ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_STA_WR_CON     :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_STA_WR_CON     ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_RD_DEBUG       :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_RD_DEBUG       ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_WR_DEBUG       :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_WR_DEBUG       ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_FR_WR_DEBUG    :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_FR_WR_DEBUG    ));
++	p += sprintf(p, "TOP_CTRL_ADDR_DMA_STA_WR_DEBUG   :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_DMA_STA_WR_DEBUG   ));
++	p += sprintf(p, "TOP_CTRL_ADDR_INT_EN             :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_INT_EN             ));
++	p += sprintf(p, "TOP_CTRL_ADDR_INT_REG            :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_INT_REG            ));
++	p += sprintf(p, "TOP_CTRL_ADDR_INT_CLR            :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_INT_CLR            ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TP_FREERUN         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TP_FREERUN         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TP_CON             :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TP_CON             ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TP_SIZE            :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TP_SIZE            ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TP_FONT            :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TP_FONT            ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TP_FLICK           :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TP_FLICK           ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TP_CS_TYPE         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TP_CS_TYPE         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TP_CS_FCLO         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TP_CS_FCLO         ));
++	p += sprintf(p, "TOP_CTRL_ADDR_TP_CS_BCLO         :0x%08x\n", isp_reg_readl(isp, TOP_CTRL_ADDR_TP_CS_BCLO         ));
++
++	return p - buf;
++}
++
++
++static DEVICE_ATTR(dump_isp, S_IRUGO|S_IWUSR, dump_isp, NULL);
++
++static struct attribute *isp_debug_attrs[] = {
++        &dev_attr_dump_isp.attr,
++	NULL,
++};
++
++static struct attribute_group isp_debug_attr_group = {
++        .name   = "debug",
++        .attrs  = isp_debug_attrs,
++};
++
++
++static int isp_comp_bind(struct device *comp, struct device *master,
++                              void *master_data)
++{
++	struct isp_device *isp = dev_get_drvdata(comp);
++	struct ispcam_device *ispcam = (struct ispcam_device *)master_data;
++	struct v4l2_device *v4l2_dev = &ispcam->v4l2_dev;
++	struct v4l2_subdev *sd = &isp->sd;
++	int ret = 0;
++
++	//dev_info(comp, "----dev_name(comp): %s----%s, %d \n", dev_name(comp), __func__, __LINE__);
++
++	/* link subdev to master.*/
++	isp->ispcam = (void *)ispcam;
++	ispcam->isp = isp;
++
++	/*1. register supported subdev ctrls.*/
++
++
++	/*2. init v4l2_subdev*/
++
++	v4l2_subdev_init(sd, &isp_subdev_ops);
++
++	sd->owner = THIS_MODULE;
++	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++	strscpy(sd->name, dev_name(comp), sizeof(sd->name));
++	v4l2_set_subdevdata(sd, isp);
++
++
++	/* init isp pads. */
++	isp->pads = kzalloc(sizeof(struct media_pad) * ISP_NUM_PADS, GFP_KERNEL);
++	if(!isp->pads) {
++		ret = -ENOMEM;
++		goto err_alloc_pads;
++	}
++	isp->pads[0].index = ISP_PAD_SINK;
++	isp->pads[0].flags = MEDIA_PAD_FL_SINK;
++	isp->pads[1].index = ISP_PAD_SOURCE;
++	isp->pads[1].flags = MEDIA_PAD_FL_SOURCE;
++
++	ret = media_entity_pads_init(&sd->entity, ISP_NUM_PADS, isp->pads);
++
++	/*3. register v4l2_subdev*/
++	sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_COMPOSER;
++	ret = v4l2_device_register_subdev(v4l2_dev, sd);
++	if(ret < 0) {
++		dev_err(comp, "Failed to register v4l2_subdev for isp\n");
++		goto err_subdev_register;
++	}
++
++	return 0;
++err_subdev_register:
++err_alloc_pads:
++	return ret;
++}
++
++
++static void isp_comp_unbind(struct device *comp, struct device *master,
++                                 void *master_data)
++{
++        struct isp_device *isp = dev_get_drvdata(comp);
++
++	dev_info(comp, "---TODO:--%p---%s, %d \n", isp,  __func__, __LINE__);
++
++}
++
++static const struct component_ops isp_comp_ops = {
++        .bind = isp_comp_bind,
++        .unbind = isp_comp_unbind,
++};
++
++static irqreturn_t isp_irq_handler(int irq, void *data)
++{
++	struct isp_device *isp = (struct isp_device *)data;
++	struct ispcam_device *ispcam = isp->ispcam;
++	struct mscaler_device *mscaler = ispcam->mscaler;
++	struct v4l2_subdev *sd = &mscaler->sd;
++	bool handled = 0;
++	unsigned int status;
++	int ret = 0;
++	int i = 0;
++
++	/*read irq_flags*/
++	status = isp_reg_readl(isp, TOP_CTRL_ADDR_INT_REG);
++
++
++	/*1. process irq by subdev.*/
++	ret = v4l2_subdev_call(sd, core, interrupt_service_routine, status, &handled);
++	if(ret < 0) {
++
++	}
++
++	/*2. isp-core irq callbacks */
++	for(i = 0; i < 32; i++) {
++		if(status & (1 << i) && isp->irq_func_cb[i]) {
++			ret = isp->irq_func_cb[i](isp->irq_func_data[i]);
++			if(ret < 0) {
++
++			}
++		}
++	}
++	/*clear irq_flags*/
++	isp_reg_writel(isp, TOP_CTRL_ADDR_INT_CLR, status);
++
++
++	return IRQ_HANDLED;
++}
++
++static int ingenic_isp_probe(struct platform_device *pdev)
++{
++
++	struct isp_device *isp = NULL;
++	int ret = 0;
++	struct resource *regs = NULL;
++
++	isp = kzalloc(sizeof(struct isp_device), GFP_KERNEL);
++	if(!isp) {
++		pr_err("Failed to alloc isp dev [%s]\n", pdev->name);
++		return -ENOMEM;
++	}
++
++	isp->dev = &pdev->dev;
++	platform_set_drvdata(pdev, isp);
++
++
++	ingenic_isp_parse_dt(isp);
++
++	isp->irq = platform_get_irq(pdev, 0);
++	if(isp->irq < 0) {
++		dev_warn(&pdev->dev, "No ISP IRQ specified\n");
++	}
++
++	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if(!regs) {
++		dev_err(&pdev->dev, "No iomem resource!\n");
++		goto err_get_resource;
++	}
++
++	isp->iobase = devm_ioremap_resource(&pdev->dev, regs);
++	if(!isp->iobase) {
++		goto err_ioremap;
++	}
++
++	ret = devm_request_irq(isp->dev, isp->irq, isp_irq_handler, 0,
++			dev_name(isp->dev), isp);
++	if(ret) {
++		dev_err(isp->dev, "request irq failed!\n");
++		goto err_request_irq;
++	}
++
++	isp->div_clk = of_clk_get(isp->dev->of_node, 0);
++	if(!isp->div_clk) {
++		dev_err(isp->dev, "failed to get isp div_clk\n");
++		goto err_div_clk;
++	}
++
++	clk_set_rate(isp->div_clk, isp_clk);
++
++	clk_prepare_enable(isp->div_clk);
++
++	isp->gate_clk = of_clk_get(isp->dev->of_node, 1);
++	if(!isp->gate_clk) {
++		dev_err(isp->dev, "failed to get isp gate_clk\n");
++		goto err_gate_clk;
++	}
++
++	clk_prepare_enable(isp->gate_clk);
++
++	isp->power_clk = of_clk_get(isp->dev->of_node, 2);
++	if(!isp->power_clk) {
++		dev_err(isp->dev, "failed to get isp power clk!\n");
++		goto err_power_clk;
++	}
++	clk_prepare_enable(isp->power_clk);
++
++	ret = sysfs_create_group(&isp->dev->kobj, &isp_debug_attr_group);
++	if (ret) {
++		dev_err(isp->dev, "device create sysfs group failed\n");
++
++		ret = -EINVAL;
++		goto err_sys_group;
++	}
++
++
++	ret = component_add(isp->dev, &isp_comp_ops);
++	if(ret < 0) {
++		dev_err(isp->dev, "Failed to add component isp!\n");
++	}
++
++	return 0;
++err_sys_group:
++err_power_clk:
++err_gate_clk:
++err_div_clk:
++err_request_irq:
++err_ioremap:
++err_get_resource:
++	return ret;
++}
++
++
++
++static int ingenic_isp_remove(struct platform_device *pdev)
++{
++	struct isp_device *isp = dev_get_drvdata(&pdev->dev);
++
++	clk_disable_unprepare(isp->power_clk);
++	clk_disable_unprepare(isp->gate_clk);
++	clk_disable_unprepare(isp->div_clk);
++	return 0;
++}
++
++
++
++static const struct of_device_id ingenic_isp_dt_match[] = {
++        { .compatible = "ingenic,x2000-isp" },
++        { .compatible = "ingenic,m300-isp" },
++        { }
++};
++
++MODULE_DEVICE_TABLE(of, ingenic_isp_dt_match);
++
++static int __maybe_unused ingenic_isp_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	struct isp_device *isp = dev_get_drvdata(&pdev->dev);
++
++	if(isp->enabled){
++		dev_err(isp->dev, "faild to suspend, isp is streaming on\n");
++		return -EBUSY;
++	}
++
++	isp_cpm_stop(isp);
++	clk_disable_unprepare(isp->power_clk);
++	clk_disable_unprepare(isp->gate_clk);
++	clk_disable_unprepare(isp->div_clk);
++
++        return 0;
++}
++
++static int __maybe_unused ingenic_isp_resume(struct platform_device *pdev)
++{
++	struct isp_device *isp = dev_get_drvdata(&pdev->dev);
++
++	clk_prepare_enable(isp->div_clk);
++	clk_prepare_enable(isp->gate_clk);
++	clk_prepare_enable(isp->power_clk);
++	isp_cpm_reset(isp);
++
++        return 0;
++}
++
++static struct platform_driver ingenic_isp_driver = {
++        .probe = ingenic_isp_probe,
++        .remove = ingenic_isp_remove,
++	.suspend = ingenic_isp_suspend,
++	.resume = ingenic_isp_resume,
++        .driver = {
++                .name = "ingenic-isp",
++                .of_match_table = ingenic_isp_dt_match,
++        },
++};
++
++module_platform_driver(ingenic_isp_driver);
++
++MODULE_ALIAS("platform:ingenic-isp");
++MODULE_DESCRIPTION("ingenic isp subsystem");
++MODULE_AUTHOR("qipengzhen <aric.pzqi@ingenic.com>");
++MODULE_LICENSE("GPL v2");
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/mscaler-bdev.c b/module_drivers/drivers/media/platform/ingenic-isp/mscaler-bdev.c
+new file mode 100644
+index 000000000..3bd1bb032
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/mscaler-bdev.c
+@@ -0,0 +1,255 @@
++#include <linux/kthread.h>
++#include <linux/list.h>
++#include <linux/wait.h>
++#include <linux/time.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++
++#include <media/videobuf2-v4l2.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++
++#include "helix_drv.h"
++#include "jpge.h"
++
++#include "isp-drv.h"
++
++
++int ms_bdev_qbuf(struct mscaler_backend_device *ms_bdev, struct isp_video_buffer *isp_buffer)
++{
++
++	unsigned long flags;
++
++//	printk("--------%s, %d\n", __func__, __LINE__);
++
++	spin_lock_irqsave(&ms_bdev->lock, flags);
++
++	list_add_tail(&isp_buffer->list_entry, &ms_bdev->processing_list);
++
++	spin_unlock_irqrestore(&ms_bdev->lock, flags);
++
++	/* wakeup possible process thread. */
++	wake_up(&ms_bdev->wq);
++}
++
++
++static int ms_bdev_kthread(void *data)
++{
++
++	struct mscaler_backend_device *ms_bdev = data;
++	int ret = 0;
++	unsigned long flags;
++
++	struct ingenic_venc_ctx *ctx = ms_bdev->ctx;
++	struct jpge_ctx *jpge_ctx = &ctx->jpge_ctx;
++
++	struct video_frame_buffer src_frame;
++
++	while(1) {
++
++		if(kthread_should_stop())
++			break;
++
++
++		ret = wait_event_interruptible(ms_bdev->wq, !list_empty(&ms_bdev->processing_list) || ms_bdev->activated == 0);
++		if(ret || ms_bdev->activated ==  0) {
++			/*wakeup by interrupt?*/
++			/* STOP*/
++			continue;
++		}
++
++		spin_lock_irqsave(&ms_bdev->lock, flags);
++		struct isp_video_buffer *isp_buffer = list_first_entry_or_null(&ms_bdev->processing_list, struct isp_video_buffer, list_entry);
++
++		if(!isp_buffer) {
++			dev_err(ms_bdev->dev, "No Buffer available!\n");
++		} else {
++
++			list_del(&isp_buffer->list_entry);
++		}
++		spin_unlock_irqrestore(&ms_bdev->lock, flags);
++
++		struct vb2_v4l2_buffer *vb2 = &isp_buffer->vb2;
++
++
++		mutex_lock(&ctx->dev->dev_mutex);
++		/* Processing ....*/
++
++		memset(&src_frame, 0, sizeof(struct video_frame_buffer));
++
++		src_frame.num_planes = 2;
++		src_frame.fb_addr[0].pa = ingenic_vb2_dma_contig_plane_dma_addr(&vb2->vb2_buf, 0);
++		src_frame.fb_addr[1].pa = src_frame.fb_addr[0].pa + isp_buffer->uv_offset;
++
++		src_frame.fb_addr[0].va = vb2_plane_vaddr(&vb2->vb2_buf, 0);
++		src_frame.fb_addr[1].va = src_frame.fb_addr[0].va + isp_buffer->uv_offset;
++
++		src_frame.fb_addr[0].size = isp_buffer->uv_offset;
++		src_frame.fb_addr[1].size = vb2_get_plane_payload(&vb2->vb2_buf, 0) - src_frame.fb_addr[0].size;
++
++		dma_sync_single_for_device(ms_bdev->dev,(unsigned long)jpge_ctx->bs->pa, jpge_ctx->bs->size, DMA_FROM_DEVICE);
++
++		jpeg_encoder_encode(jpge_ctx, &src_frame, jpge_ctx->bs);
++
++		memcpy(vb2_plane_vaddr(&vb2->vb2_buf, 0), jpge_ctx->bs->va, jpge_ctx->bslen);
++
++		vb2_set_plane_payload(&vb2->vb2_buf, 0, jpge_ctx->bslen);
++
++#if 0
++		wait_process_buffer();
++
++		done_process_buffer();
++#endif
++		mutex_unlock(&ctx->dev->dev_mutex);
++//		printk("----done_processing_buffer: %d\n", isp_buffer->vb2.vb2_buf.index);
++		vb2_buffer_done(&isp_buffer->vb2.vb2_buf, VB2_BUF_STATE_DONE);
++
++	}
++
++	return 0;
++}
++
++
++static int venc_create_ctx(struct mscaler_backend_device *ms_bdev)
++{
++
++	struct ingenic_venc_ctx *ctx = kzalloc(sizeof(struct ingenic_venc_ctx), GFP_KERNEL);
++	struct h264e_ctx * h264e_ctx = NULL;
++	struct jpge_ctx * jpge_ctx = NULL;
++	struct ingenic_vcodec_mem *bs = NULL;
++	int ret = 0;
++
++	if(ctx == NULL) {
++		return -ENOMEM;
++	}
++
++	ctx->dev = ingenic_venc_dev_get();
++
++	mutex_lock(&ctx->dev->dev_mutex);
++
++#if 0
++	if (!ctx->dev->id_counter) {
++		vpu_on(ctx->dev);
++	}
++#endif
++
++	ctx->id = ctx->dev->id_counter++;
++	init_waitqueue_head(&ctx->queue);
++
++	mutex_unlock(&ctx->dev->dev_mutex);
++
++	ms_bdev->ctx = ctx;
++
++	/*switch FMT: JPEG H264.*/
++	jpge_ctx = &ctx->jpge_ctx;
++	ctx->codec_id = CODEC_ID_JPGE;
++
++	ret = jpeg_encoder_init(jpge_ctx);
++	jpeg_encoder_set_priv(jpge_ctx, ctx);
++
++
++	jpeg_encoder_set_fmt(jpge_ctx, ms_bdev->width, ms_bdev->height, HELIX_NV12_MODE);
++
++	ret = jpeg_encoder_alloc_workbuf(jpge_ctx);
++	if(ret < 0) {
++		goto err_alloc_workbuf;
++	}
++
++	/* alloc bs output buffer. */
++	bs = kzalloc(sizeof(struct ingenic_vcodec_mem), GFP_KERNEL);
++	if(!bs) {
++		goto err_bs_alloc;
++	}
++	bs->size = ms_bdev->width * ms_bdev->height;
++
++	bs->va = dma_alloc_noncoherent(ms_bdev->dev, bs->size, &bs->pa, GFP_KERNEL);
++	if(!bs->va) {
++		goto err_bs_va_alloc;
++	}
++
++	jpge_ctx->bs = bs;
++
++
++	return 0;
++err_bs_va_alloc:
++	kfree(bs);
++err_bs_alloc:
++	jpeg_encoder_free_workbuf(jpge_ctx);
++err_alloc_workbuf:
++	jpeg_encoder_deinit(jpge_ctx);
++
++	kfree(ctx);
++	ms_bdev->ctx = NULL;
++	return ret;
++}
++
++static int venc_free_ctx(struct mscaler_backend_device *ms_bdev)
++{
++	struct ingenic_venc_ctx *ctx = ms_bdev->ctx;
++	struct jpge_ctx *jpge_ctx = &ctx->jpge_ctx;
++	struct ingenic_vcodec_mem *bs = jpge_ctx->bs;
++
++
++
++	mutex_lock(&ctx->dev->dev_mutex);
++#if 0
++	if (!--ctx->dev->id_counter) {
++		vpu_off(ctx->dev);
++	}
++#endif
++	mutex_unlock(&ctx->dev->dev_mutex);
++
++	dma_free_noncoherent(ms_bdev->dev, bs->size, bs->va, bs->pa);
++	kfree(bs);
++
++	jpeg_encoder_free_workbuf(jpge_ctx);
++	jpeg_encoder_deinit(jpge_ctx);
++
++	kfree(ctx);
++}
++
++
++int ms_bdev_init(struct mscaler_backend_device *ms_bdev)
++{
++	int ret = 0;
++	printk("--------%s, %d\n", __func__, __LINE__);
++
++	ret = venc_create_ctx(ms_bdev);
++	if(ret < 0) {
++		return -EINVAL;
++	}
++
++	spin_lock_init(&ms_bdev->lock);
++	INIT_LIST_HEAD(&ms_bdev->processing_list);
++	init_waitqueue_head(&ms_bdev->wq);
++
++	ms_bdev->process_thread = kthread_run(ms_bdev_kthread, ms_bdev, "ms-bdev-ch%d", ms_bdev->ch);
++	if(IS_ERR_OR_NULL(ms_bdev->process_thread)) {
++
++		dev_err(ms_bdev->dev, "Failed to run kthread for ms-bdev-ch%d", ms_bdev->ch);
++
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++int ms_bdev_deinit(struct mscaler_backend_device *ms_bdev)
++{
++
++	printk("--------%s, %d\n", __func__, __LINE__);
++
++	if(!ms_bdev->activated) {
++		return 0;
++	}
++
++
++	kthread_stop(ms_bdev->process_thread);
++
++	ms_bdev->process_thread = NULL;
++
++	venc_free_ctx(ms_bdev);
++
++	memset(ms_bdev, 0, sizeof(struct mscaler_backend_device));
++
++	return 0;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/mscaler-regs.h b/module_drivers/drivers/media/platform/ingenic-isp/mscaler-regs.h
+new file mode 100644
+index 000000000..d7a2de2cc
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/mscaler-regs.h
+@@ -0,0 +1,82 @@
++#ifndef	__INGENIC_ISP_MSCALER_REGS_H__
++#define __INGENIC_ISP_MSCALER_REGS_H__
++
++#define MSCA_BASE	0
++
++//============================================================
++// Mscaler
++//============================================================
++#define    MSCA_CTRL                         (MSCA_BASE+0x000)
++#define    MSCA_CH_EN                        (MSCA_BASE+0x004)
++#define    MSCA_CH_STA                       (MSCA_BASE+0x008)
++#define    MSCA_INT_STA                      (MSCA_BASE+0x00C)
++#define    MSCA_INT_MSK                      (MSCA_BASE+0x010)
++#define    MSCA_INT_CLR                      (MSCA_BASE+0x014)
++#define    MSCA_DMAOUT_ARB                   (MSCA_BASE+0x018)
++#define    MSCA_CLK_GATE_EN                  (MSCA_BASE+0x01C)
++#define    MSCA_CLK_DIS                      (MSCA_BASE+0x020)
++#define    MSCA_SRC_IN                       (MSCA_BASE+0x030)
++#define    MSCA_SRC_SIZE                     (MSCA_BASE+0x034)
++#define    MSCA_GLO_RSZ_COEF_WR              (MSCA_BASE+0x040)
++#define    MSCA_SYS_PRO_CLK_EN               (MSCA_BASE+0x050)
++#define    MSCA_DS0_CLK_NUM                  (MSCA_BASE+0x054)
++#define    MSCA_DS1_CLK_NUM                  (MSCA_BASE+0x058)
++#define    MSCA_DS2_CLK_NUM                  (MSCA_BASE+0x05C)
++
++#define CHx_RSZ_OSIZE(n)				(MSCA_BASE+(0x0100*(n))+0x100)
++#define CHx_RSZ_STEP(n)					(MSCA_BASE+(0x0100*(n))+0x104)
++
++#define CHx_CROP_OPOS(n)				(MSCA_BASE+(0x0100*(n))+0x128)
++#define CHx_CROP_OSIZE(n)				(MSCA_BASE+(0x0100*(n))+0x12c)
++#define CHx_FRA_CTRL_LOOP(n)				(MSCA_BASE+(0x0100*(n))+0x130)
++#define CHx_FRA_CTRL_MASK(n)				(MSCA_BASE+(0x0100*(n))+0x134)
++#define CHx_MSx_POS(n,m)				(MSCA_BASE+(0x0100*(n))+0x138+(0x0c*(m)))
++#define CHx_MSx_SIZE(n,m)				(MSCA_BASE+(0x0100*(n))+0x13c+(0x0c*(m)))
++#define CHx_MSx_VALUE(n,m)				(MSCA_BASE+(0x0100*(n))+0x140+(0x0c*(m)))
++#define CHx_MS0_POS(n)					(MSCA_BASE+(0x0100*(n))+0x138)
++#define CHx_MS0_SIZE(n)					(MSCA_BASE+(0x0100*(n))+0x13c)
++#define CHx_MS0_VALUE(n)				(MSCA_BASE+(0x0100*(n))+0x140)
++#define CHx_MS1_POS(n)					(MSCA_BASE+(0x0100*(n))+0x144)
++#define CHx_MS1_SIZE(n)					(MSCA_BASE+(0x0100*(n))+0x148)
++#define CHx_MS1_VALUE(n)				(MSCA_BASE+(0x0100*(n))+0x14c)
++#define CHx_MS2_POS(n)					(MSCA_BASE+(0x0100*(n))+0x150)
++#define CHx_MS2_SIZE(n)					(MSCA_BASE+(0x0100*(n))+0x154)
++#define CHx_MS2_VALUE(n)				(MSCA_BASE+(0x0100*(n))+0x158)
++#define CHx_MS3_POS(n)					(MSCA_BASE+(0x0100*(n))+0x15c)
++#define CHx_MS3_SIZE(n)					(MSCA_BASE+(0x0100*(n))+0x160)
++#define CHx_MS3_VALUE(n)				(MSCA_BASE+(0x0100*(n))+0x164)
++#define CHx_OUT_FMT(n)					(MSCA_BASE+(0x0100*(n))+0x168)
++#define CHx_DMAOUT_Y_ADDR(n)				(MSCA_BASE+(0x0100*(n))+0x16c)
++#define CHx_Y_ADDR_FIFO_STA(n)				(MSCA_BASE+(0x0100*(n))+0x170)
++#define CHx_DMAOUT_Y_LAST_ADDR(n)			(MSCA_BASE+(0x0100*(n))+0x174)
++#define CHx_DMAOUT_Y_LAST_STATS_NUM(n)			(MSCA_BASE+(0x0100*(n))+0x178)
++#define CHx_Y_LAST_ADDR_FIFO_STA(n)			(MSCA_BASE+(0x0100*(n))+0x17c)
++#define CHx_DMAOUT_Y_STRI(n)				(MSCA_BASE+(0x0100*(n))+0x180)
++#define CHx_DMAOUT_UV_ADDR(n)				(MSCA_BASE+(0x0100*(n))+0x184)
++#define CHx_UV_ADDR_FIFO_STA(n)				(MSCA_BASE+(0x0100*(n))+0x188)
++#define CHx_DMAOUT_UV_LAST_ADDR(n)			(MSCA_BASE+(0x0100*(n))+0x18c)
++#define CHx_DMAOUT_UV_LAST_STATS_NUM(n)			(MSCA_BASE+(0x0100*(n))+0x190)
++#define CHx_UV_LAST_ADDR_FIFO_STA(n)			(MSCA_BASE+(0x0100*(n))+0x194)
++#define CHx_DMAOUT_UV_STRI(n)				(MSCA_BASE+(0x0100*(n))+0x198)
++#define CHx_DMAOUT_Y_ADDR_CLR(n)			(MSCA_BASE+(0x0100*(n))+0x19c)
++#define CHx_DMAOUT_UV_ADDR_CLR(n)			(MSCA_BASE+(0x0100*(n))+0x1a0)
++#define CHx_DMAOUT_Y_LAST_ADDR_CLR(n)			(MSCA_BASE+(0x0100*(n))+0x1a4)
++#define CHx_DMAOUT_UV_LAST_ADDR_CLR(n)			(MSCA_BASE+(0x0100*(n))+0x1a8)
++#define CHx_DMAOUT_Y_ADDR_SEL(n)			(MSCA_BASE+(0x0100*(n))+0x1ac)
++#define CHx_DMAOUT_UV_ADDR_SEL(n)			(MSCA_BASE+(0x0100*(n))+0x1b0)
++
++#define MSCA_CH0_FRM_DONE_INT	(0)
++#define MSCA_CH1_FRM_DONE_INT	(1)
++#define MSCA_CH2_FRM_DONE_INT	(2)
++#define MSCA_CH0_CROP_ERR_INT	(3)
++#define MSCA_CH1_CROP_ERR_INT	(4)
++#define MSCA_CH2_CROP_ERR_INT	(5)
++
++#define CHx_OUT_FMT_NV12 0x0
++#define CHx_OUT_FMT_NV21 0x1
++#define CHx_OUT_FMT_ARGB8888 0x2
++#define CHx_OUT_FMT_RGB565 0x3
++#define CHx_OUT_FMT_Y_OUT_ONLY (1 << 6)
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/mscaler.c b/module_drivers/drivers/media/platform/ingenic-isp/mscaler.c
+new file mode 100644
+index 000000000..9517419f7
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/mscaler.c
+@@ -0,0 +1,1531 @@
++#include <linux/clk.h>
++#include <linux/media-bus-format.h>
++#include <linux/media.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_graph.h>
++#include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
++#include <linux/pm_domain.h>
++#include <linux/slab.h>
++#include <linux/videodev2.h>
++#include <linux/component.h>
++#include <linux/time.h>
++#include <linux/delay.h>
++
++#include <media/media-device.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-event.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++#include <media/videobuf2-v4l2.h>
++#include <media/ingenic_video_nr.h>
++
++#include "isp-drv.h"
++#include "mscaler-regs.h"
++
++static void dump_mscaler_regs(struct mscaler_device *mscaler);
++
++static struct isp_video_format mscaler_output_formats[] = {
++	{
++		.name     = "NV12, Y/CbCr 4:2:0",
++		.fourcc   = V4L2_PIX_FMT_NV12,
++		.depth    = {8, 4},
++		.num_planes = 2,
++		.mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "NV21, Y/CrCb 4:2:0",
++		.fourcc   = V4L2_PIX_FMT_NV21,
++		.depth    = {8, 4},
++		.num_planes = 2,
++		.mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "GREY, Greyscale",
++		.fourcc   = V4L2_PIX_FMT_GREY,
++		.depth    = {8},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_Y8_1X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++#ifdef CONFIG_MSCA_BDEV
++	{
++		.name     = "JFIF JPEG",
++		.fourcc   = V4L2_PIX_FMT_JPEG,
++		.depth    = {8},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_JPEG_1X8,
++		.colorspace = V4L2_COLORSPACE_JPEG,
++	},
++	{
++		.name     = "H264 with start codes",
++		.fourcc   = V4L2_PIX_FMT_H264,
++		.depth    = {8},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_JPEG_1X8,
++		.colorspace = V4L2_COLORSPACE_JPEG,
++	},
++#endif
++	/*
++	{
++		.name     = "RGB565, RGB-5-6-5",
++		.fourcc   = V4L2_PIX_FMT_RGB565,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_RGB565_1X16,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "ARGB32, ARGB-8-8-8-8",
++		.fourcc   = V4L2_PIX_FMT_ARGB32,
++		.depth    = {32},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_ARGB8888_1X32,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	*/
++};
++
++struct ingenic_isp_framesizes {
++	u32 fourcc;
++	struct v4l2_frmsize_discrete discrete;
++};
++
++static const struct ingenic_isp_framesizes ingenic_isp_framesizes[] = {
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {320, 240},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {240, 320},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {640, 480},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {480, 640},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {960, 720},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {720, 960},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {1280, 720},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {1280, 960},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.discrete = {1920, 1080},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {320, 240},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {240, 320},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {640, 480},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {480, 640},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {960, 720},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {720, 960},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {1280, 720},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {1280, 960},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.discrete = {1920, 1080},
++	}
++};
++
++struct mask_kobj_attr {
++	struct kobj_attribute attr;
++	unsigned int id;
++};
++
++#define to_mask_attr(attr)     \
++	container_of(attr, struct mask_kobj_attr, attr)
++
++static inline void mscaler_reg_writel(struct mscaler_device *mscaler, unsigned int reg, unsigned int val)
++{
++	writel(val, mscaler->iobase + reg);
++}
++
++static inline unsigned int mscaler_reg_readl(struct mscaler_device *mscaler, unsigned int reg)
++{
++	return readl(mscaler->iobase + reg);
++}
++
++
++/* isp video 回调函数，用�寻找当�支�的输出视频格�，由于mscaler�以输出，vic也�以输出，所以这里设计�回调的方�.*/
++
++/**
++ * @brief
++ *
++ * @param pixelformat	如果pixelformat�为空，则使用pixelformat匹�.
++ * @param mbus_code
++ * @param index
++ *
++ * @return
++ */
++struct isp_video_format *mscaler_find_format(const u32 *pixelformat, const u32 *mbus_code, int index)
++{
++	int i;
++	struct isp_video_format *fmt = NULL;
++
++	for(i = 0; i < ARRAY_SIZE(mscaler_output_formats); i++) {
++		fmt = &mscaler_output_formats[i];
++
++		if(pixelformat && fmt->fourcc == *pixelformat) {
++			return fmt;
++		}
++		if(mbus_code && fmt->mbus_code == *mbus_code) {
++			return fmt;
++		}
++
++		if(index == i) {
++			return fmt;
++		}
++	}
++
++	return NULL;
++}
++
++
++/* In irq context. */
++static int mscaler_irq_notify_ch_done(struct mscaler_device *mscaler, int ch)
++{
++	struct isp_video_buffer *isp_buffer = NULL;
++	unsigned int y_last_addr = 0;
++	unsigned int uv_last_addr = 0;
++	unsigned int y_frame_num = 0;
++	unsigned int uv_frame_num = 0;
++	unsigned int fifo_empty = 0;
++	unsigned int fifo_full = 0;
++	unsigned int y_fifo_st = 0, uv_fifo_st = 0;
++	dma_addr_t y_addr = 0;
++	dma_addr_t uv_addr = 0;
++	struct vb2_buffer *vb2_buf = NULL;
++
++	//printk("------%s, ch: %d\n", __func__, ch);
++
++
++	spin_lock(&mscaler->lock);
++	/*由于mscaler stop stream时, ISP �能还会产生中断,这个时候�用处�*/
++	if(mscaler->state[ch] == 0) {
++		spin_unlock(&mscaler->lock);
++		return 0;
++	}
++
++	isp_buffer = list_first_entry_or_null(&mscaler->dma_queued_list[ch], struct isp_video_buffer, list_entry);
++	if(!isp_buffer) {
++		dev_err(mscaler->dev, "[warning] no isp_buffer found in dma_queued_list when interrupt happend!\n");
++		spin_unlock(&mscaler->lock);
++		return 0;
++	}
++
++	list_del(&isp_buffer->list_entry);
++
++
++	y_last_addr = mscaler_reg_readl(mscaler, CHx_DMAOUT_Y_LAST_ADDR(ch));
++	y_frame_num = mscaler_reg_readl(mscaler, CHx_DMAOUT_Y_LAST_STATS_NUM(ch));
++
++	uv_last_addr = mscaler_reg_readl(mscaler, CHx_DMAOUT_UV_LAST_ADDR(ch));
++	uv_frame_num = mscaler_reg_readl(mscaler, CHx_DMAOUT_UV_LAST_STATS_NUM(ch));
++
++	/*TODO Sequence.*/
++	//if(isp_buffer->vb2.vb2_buf.state == VB2_BUF_STATE_ACTIVE)
++	isp_buffer->vb2.vb2_buf.timestamp = ktime_get_ns();
++	isp_buffer->vb2.sequence = mscaler->framenum[ch]++;
++
++#ifdef CONFIG_MSCA_BDEV
++	/*如果�端设备存在，则调用ms_bdev_qbuf,交给�端处�.*/
++	if(mscaler->bdev[ch].activated) {
++		ms_bdev_qbuf(&mscaler->bdev[ch], isp_buffer);
++	} else {
++		vb2_buffer_done(&isp_buffer->vb2.vb2_buf, VB2_BUF_STATE_DONE);
++	}
++#else
++	vb2_buffer_done(&isp_buffer->vb2.vb2_buf, VB2_BUF_STATE_DONE);
++#endif
++
++	y_fifo_st = mscaler_reg_readl(mscaler, CHx_Y_ADDR_FIFO_STA(ch));
++	uv_fifo_st = mscaler_reg_readl(mscaler, CHx_UV_ADDR_FIFO_STA(ch));
++
++	if((y_fifo_st & (1<<0)) && (uv_fifo_st & (1<<0))) {
++		fifo_empty = 1;
++	} else if((y_fifo_st & (1<<4)) || (uv_fifo_st & (1<<4))) {
++		fifo_full = 1;
++	}
++
++	/* 如果stream on了，就写入硬件.*/
++	if(mscaler->state[ch] == 1 && !fifo_full) {
++		isp_buffer = list_first_entry_or_null(&mscaler->dma_pending_list[ch], struct isp_video_buffer, list_entry);
++		if(isp_buffer){
++			vb2_buf = &isp_buffer->vb2.vb2_buf;
++			/*Y*/
++			y_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 0);
++			mscaler_reg_writel(mscaler, CHx_DMAOUT_Y_ADDR(ch), y_addr);
++
++			uv_addr = y_addr + isp_buffer->uv_offset;
++			/*UV*/
++			if(vb2_buf->num_planes == 2) {
++				uv_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 1);
++			}
++			mscaler_reg_writel(mscaler, CHx_DMAOUT_UV_ADDR(ch), uv_addr);
++			list_del(&isp_buffer->list_entry);
++			list_add_tail(&isp_buffer->list_entry, &mscaler->dma_queued_list[ch]);
++		}
++	}
++
++	spin_unlock(&mscaler->lock);
++
++	return 0;
++}
++
++static int mscaler_interrupt_service_routine(struct v4l2_subdev *sd,
++						u32 status, bool *handled)
++{
++	struct mscaler_device *mscaler = v4l2_get_subdevdata(sd);
++	int ret = 0;
++
++	/*�管心 mscaler的三个ch的done中断和crop出错的中断.*/
++	if(status & (1 << MSCA_CH0_FRM_DONE_INT)) {
++		ret = mscaler_irq_notify_ch_done(mscaler, 0);
++	}
++	if(status & (1 << MSCA_CH1_FRM_DONE_INT)) {
++		ret = mscaler_irq_notify_ch_done(mscaler, 1);
++	}
++
++	if(status & (1 << MSCA_CH2_FRM_DONE_INT)) {
++		ret = mscaler_irq_notify_ch_done(mscaler, 2);
++	}
++
++	/*TODO: add handler.*/
++	if(status & (1 << MSCA_CH0_CROP_ERR_INT)) {
++
++	}
++	if(status & (1 << MSCA_CH1_CROP_ERR_INT)) {
++
++	}
++	if(status & (1 << MSCA_CH2_CROP_ERR_INT)) {
++
++	}
++
++	return ret;
++}
++
++static int mscaler_subdev_init(struct v4l2_subdev *sd, u32 val)
++{
++
++	return 0;
++}
++
++static int mscaler_subdev_reset(struct v4l2_subdev *sd, u32 val)
++{
++	return 0;
++}
++
++static const struct v4l2_subdev_core_ops mscaler_subdev_core_ops = {
++	.init	= mscaler_subdev_init,
++	.reset = mscaler_subdev_reset,
++        .log_status = v4l2_ctrl_subdev_log_status,
++        .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
++        .unsubscribe_event = v4l2_event_subdev_unsubscribe,
++	.interrupt_service_routine = mscaler_interrupt_service_routine,
++};
++
++static unsigned int ch_to_pad[] = {
++	MSCALER_PAD_SOURCE_CH0,
++	MSCALER_PAD_SOURCE_CH1,
++	MSCALER_PAD_SOURCE_CH2
++};
++
++static int pad_to_ch(int pad)
++{
++	switch(pad) {
++		case MSCALER_PAD_SOURCE_CH0:
++			return 0;
++		case MSCALER_PAD_SOURCE_CH1:
++			return 1;
++		case MSCALER_PAD_SOURCE_CH2:
++			return 2;
++		default:
++			return -EINVAL;
++	}
++}
++
++static int mscaler_enum_mbus_code(struct v4l2_subdev *sd,
++			      struct v4l2_subdev_pad_config *cfg,
++			      struct v4l2_subdev_mbus_code_enum *code)
++{
++	//printk("------%s, %d, sd->name: %s\n", __func__, __LINE__, sd->name);
++
++	if(code->index >= ARRAY_SIZE(mscaler_output_formats)) {
++		dev_err(sd->dev, "too many mbus formats!\n");
++		return -EINVAL;
++	}
++
++	code->code = mscaler_output_formats[code->index].mbus_code;
++
++	return 0;
++}
++static int mscaler_enum_frame_size(struct v4l2_subdev *sd,
++			       struct v4l2_subdev_pad_config *cfg,
++			       struct v4l2_subdev_frame_size_enum *fse)
++{
++	int index = fse->index;
++	int num_valid = -1;
++	int i = 0;
++	if(index >= ARRAY_SIZE(ingenic_isp_framesizes))
++		return -EINVAL;
++
++	for(i = 0; i < ARRAY_SIZE(ingenic_isp_framesizes); i++) {
++		if(fse->code != ingenic_isp_framesizes[i].fourcc)
++			continue;
++		if(index == ++num_valid) {
++			fse->max_height = ingenic_isp_framesizes[i].discrete.height;
++			fse->min_height = fse->max_height;
++			fse->max_width = ingenic_isp_framesizes[i].discrete.width;
++			fse->min_width = fse->max_width;
++			return 0;
++		}
++	}
++	return -EINVAL;
++}
++
++static int mscaler_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct mscaler_device *mscaler = v4l2_get_subdevdata(sd);
++	struct v4l2_mbus_framefmt *framefmt = NULL;
++	//printk("------%s, %d, sd->name: %s\n", __func__, __LINE__, sd->name);
++
++	if(format->which == V4L2_SUBDEV_FORMAT_TRY) {
++		framefmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
++	} else {
++		framefmt = &mscaler->formats[format->pad].format;
++	}
++
++	format->format = *framefmt;
++
++	return 0;
++}
++
++static int mscaler_set_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct mscaler_device *mscaler = v4l2_get_subdevdata(sd);
++	struct media_pad *remote = NULL;
++	struct v4l2_subdev *remote_sd = NULL;
++	struct v4l2_subdev_format remote_subdev_fmt;
++	struct isp_video_device *ispvideo = v4l2_get_subdev_hostdata(sd);
++	int ch = 0, i = 0, ret = 0;
++	for(i = 0; i < MSCALER_MAX_CH; i++) {
++		if(ispvideo == &mscaler->ispvideo[i]) {
++			ch = i;
++			break;
++		}
++	}
++
++	//printk("%s, %d, width: %d, height: %d, mbus_code: %x\n", __func__, __LINE__, format->format.width, format->format.height, format->format.code);
++
++	mscaler->formats[format->pad] = *format;
++
++	remote = media_entity_remote_pad(&mscaler->pads[MSCALER_PAD_SINK]);
++	remote_sd = media_entity_to_v4l2_subdev(remote->entity);
++
++	ret = v4l2_subdev_call(remote_sd, pad, set_fmt, NULL, format);
++	if(ret < 0) {
++		dev_dbg(mscaler->dev, "Failed to set_fmt from remote pad\n");
++	}
++
++	remote_subdev_fmt.pad = remote->index;
++	remote_subdev_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	ret = v4l2_subdev_call(remote_sd, pad, get_fmt, NULL, &remote_subdev_fmt);
++	if(ret < 0) {
++		dev_err(mscaler->dev, "Failed to get_fmt from remote pad\n");
++		return -EINVAL;
++	}
++
++	memcpy(&mscaler->formats[MSCALER_PAD_SINK], &remote_subdev_fmt, sizeof(struct v4l2_subdev_format));
++
++	/*def crop info.*/
++	mscaler->sel[ch].r.left = 0;
++	mscaler->sel[ch].r.top = 0;
++	mscaler->sel[ch].r.width = format->format.width;
++	mscaler->sel[ch].r.height = format->format.height;
++
++	return 0;
++}
++
++static int mscaler_get_selection(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, struct v4l2_subdev_selection *sel)
++{
++	struct mscaler_device *mscaler = v4l2_get_subdevdata(sd);
++	struct v4l2_subdev_format *output_fmt = NULL;
++	int ch = pad_to_ch(sel->pad);
++
++	if(ch < 0)
++		return -EINVAL;
++
++	output_fmt = &mscaler->formats[sel->pad];
++	if(sel->target == V4L2_SEL_TGT_CROP || sel->target == V4L2_SEL_TGT_CROP_DEFAULT){
++		memcpy(&sel->r, &mscaler->sel[ch].r, sizeof(struct v4l2_rect));
++	} else if(sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
++		sel->r.left = 0;
++		sel->r.top = 0;
++		sel->r.width = output_fmt->format.width;
++		sel->r.height = output_fmt->format.height;
++	} else {
++		dev_warn(mscaler->dev, "unsupported selection target!\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int mscaler_set_selection(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, struct v4l2_subdev_selection *sel)
++{
++	struct mscaler_device *mscaler = v4l2_get_subdevdata(sd);
++	struct v4l2_subdev_format *output_fmt = NULL;
++	int ch = pad_to_ch(sel->pad);
++
++	if(ch < 0)
++		return -EINVAL;
++
++	if(sel->flags == V4L2_SEL_FLAG_GE) {
++		dev_warn(mscaler->dev, "unsupported selection flags!\n");
++		return -EINVAL;
++	}
++
++	output_fmt = &mscaler->formats[sel->pad];
++	if(sel->r.top + sel->r.height > output_fmt->format.height ||
++			sel->r.left + sel->r.width > output_fmt->format.width) {
++		dev_warn(mscaler->dev, "selection out of range! please check the boundry.\n");
++		return -EINVAL;
++	}
++
++	if(sel->target == V4L2_SEL_TGT_CROP){
++		memcpy(&mscaler->sel[ch].r, &sel->r, sizeof(struct v4l2_rect));
++	} else {
++		dev_warn(mscaler->dev, "unsupported selection target!\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++
++static const struct v4l2_subdev_pad_ops mscaler_subdev_pad_ops = {
++        .enum_mbus_code         = mscaler_enum_mbus_code,
++        .enum_frame_size        = mscaler_enum_frame_size,
++        .get_fmt                = mscaler_get_fmt,
++        .set_fmt                = mscaler_set_fmt,
++        .get_selection          = mscaler_get_selection,
++        .set_selection          = mscaler_set_selection,
++};
++
++static int mscaler_stream_enable(struct mscaler_device *mscaler, int ch)
++{
++	struct v4l2_subdev_format *input_fmt = &mscaler->formats[MSCALER_PAD_SINK];
++	struct v4l2_subdev_format *output_fmt = &mscaler->formats[ch_to_pad[ch]];
++	unsigned long flags = 0;
++	unsigned int step_w = 0, step_h = 0;
++	unsigned int val = 0;
++	int ret = 0;
++	struct isp_video_buffer *isp_buffer = NULL;
++	struct isp_video_buffer *tmp = NULL;
++	dma_addr_t y_addr = 0;
++	dma_addr_t uv_addr = 0;
++	unsigned int fifo_empty = 0;
++	unsigned int fifo_full = 0;
++	unsigned int y_fifo_st = 0, uv_fifo_st = 0;
++	struct vb2_buffer *vb2_buf = NULL;
++
++	dev_dbg(mscaler->dev, "-----input_fmt->format.width: %d, input_fmt->format.height: %d\n", input_fmt->format.width, input_fmt->format.height);
++	dev_dbg(mscaler->dev, "-----output_fmt->format.width: %d, output_fmt->format.height: %d\n", output_fmt->format.width, output_fmt->format.height);
++
++	spin_lock_irqsave(&mscaler->lock, flags);
++	/*1. mscaler_hw_configure.*/
++	mscaler_reg_writel(mscaler, CHx_RSZ_OSIZE(ch), (output_fmt->format.width << 16) | (output_fmt->format.height));
++
++	step_w = input_fmt->format.width * 512 / output_fmt->format.width;
++	step_h = input_fmt->format.height * 512 / output_fmt->format.height;
++
++	mscaler_reg_writel(mscaler, CHx_RSZ_STEP(ch), step_w << 16 | step_h);
++
++	/*Crop info.*/
++	mscaler_reg_writel(mscaler, CHx_CROP_OPOS(ch), (mscaler->sel[ch].r.left << 16) | mscaler->sel[ch].r.top);
++	mscaler_reg_writel(mscaler, CHx_CROP_OSIZE(ch), (mscaler->sel[ch].r.width << 16) | mscaler->sel[ch].r.height);
++
++	mscaler_reg_writel(mscaler, CHx_DMAOUT_Y_STRI(ch), mscaler->sel[ch].r.width);
++	mscaler_reg_writel(mscaler, CHx_DMAOUT_UV_STRI(ch), mscaler->sel[ch].r.width);
++
++	val = mscaler_reg_readl(mscaler, MSCA_DMAOUT_ARB);
++	val |= 1 << (ch + 1);
++	mscaler_reg_writel(mscaler, MSCA_DMAOUT_ARB, val);
++
++	/*output fmt set*/
++	switch(output_fmt->format.code){
++		case MEDIA_BUS_FMT_YUYV8_2X8:
++			val = CHx_OUT_FMT_NV12;
++			break;
++		case MEDIA_BUS_FMT_YVYU8_2X8:
++			val = CHx_OUT_FMT_NV21;
++			break;
++		case MEDIA_BUS_FMT_Y8_1X8:
++			val = CHx_OUT_FMT_NV12;
++			val |= CHx_OUT_FMT_Y_OUT_ONLY;
++			break;
++#ifdef CONFIG_MSCA_BDEV
++		case MEDIA_BUS_FMT_JPEG_1X8:
++			val = CHx_OUT_FMT_NV12;
++
++			mscaler->bdev[ch].width = output_fmt->format.width;
++			mscaler->bdev[ch].height = output_fmt->format.height;
++			//mscaler->bdev[ch].fmt	= CHx_OUT_FMT_NV12;
++			mscaler->bdev[ch].ch = ch;
++			mscaler->bdev[ch].dev = mscaler->dev;
++			mscaler->bdev[ch].activated = 1;	// 使用bdev进行格�转�.
++			break;
++	//	case MEDIA_BUS_FMT_RGB565_1X16:
++	//		val = CHx_OUT_FMT_RGB565;
++	//		break;
++	//	case MEDIA_BUS_FMT_ARGB8888_1X32:
++	//		val = CHx_OUT_FMT_ARGB8888;
++	//		break;
++#endif
++		default:
++			printk("output format not supported!\n");
++	}
++	if(mscaler->yonly_cf[ch].yonly_enable) {
++		val |= CHx_OUT_FMT_Y_OUT_ONLY;
++	}
++	mscaler_reg_writel(mscaler, CHx_OUT_FMT(ch), val);
++
++
++	/*2. mscaler_hw_start*/
++	val = mscaler_reg_readl(mscaler, MSCA_CH_EN);
++	val |= 1 << ch;
++	val |= (1 << 8) << ch; //fix_vrsz_en
++	val |= (1 << 11) << ch; //fix_hrsz_en
++	mscaler_reg_writel(mscaler, MSCA_CH_EN, val);
++
++	mscaler->state[ch] = 1;
++	mscaler->framenum[ch] = 0;
++
++	/*因为ISP��的执行时间时在stream_on的时候，这个时候上层qbuf已�调用了，
++	 * 如果部将这些buffer�新加入硬件队列，则会出现问题.*/
++	list_for_each_entry_safe(isp_buffer, tmp, &mscaler->dma_pending_list[ch], list_entry) {
++		y_fifo_st = mscaler_reg_readl(mscaler, CHx_Y_ADDR_FIFO_STA(ch));
++		uv_fifo_st = mscaler_reg_readl(mscaler, CHx_UV_ADDR_FIFO_STA(ch));
++		if((y_fifo_st & (1<<0)) && (uv_fifo_st & (1<<0))) {
++			fifo_empty = 1;
++		} else if((y_fifo_st & (1<<4)) || (uv_fifo_st & (1<<4))) {
++			fifo_full = 1;
++		}
++		if(fifo_full)
++			break;
++
++		vb2_buf = &isp_buffer->vb2.vb2_buf;
++		/*Y*/
++		y_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 0);
++		mscaler_reg_writel(mscaler, CHx_DMAOUT_Y_ADDR(ch), y_addr);
++
++		uv_addr = y_addr + isp_buffer->uv_offset;
++		if(vb2_buf->num_planes == 2) {
++			uv_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 1);
++		}
++		mscaler_reg_writel(mscaler, CHx_DMAOUT_UV_ADDR(ch), uv_addr);
++		list_del(&isp_buffer->list_entry);
++		list_add_tail(&isp_buffer->list_entry, &mscaler->dma_queued_list[ch]);
++	}
++
++	spin_unlock_irqrestore(&mscaler->lock, flags);
++
++#ifdef CONFIG_MSCA_BDEV
++	if(mscaler->bdev[ch].activated == 1) {
++		ret = ms_bdev_init(&mscaler->bdev[ch]);
++		if(ret < 0) {
++			return -EINVAL;
++		}
++	}
++#endif
++
++	return ret;
++}
++
++static int mscaler_stream_disable(struct mscaler_device *mscaler, int ch)
++{
++	unsigned long flags = 0;
++	unsigned int val = 0;
++	int ret = 0;
++	unsigned int timeout = 0xffffff;
++	struct isp_video_buffer *isp_buffer = NULL;
++	struct isp_video_buffer *tmp = NULL;
++
++
++	spin_lock_irqsave(&mscaler->lock, flags);
++
++	val = mscaler_reg_readl(mscaler, MSCA_CH_EN);
++	val &= ~(1 << ch);
++	mscaler_reg_writel(mscaler, MSCA_CH_EN, val);
++
++	spin_unlock_irqrestore(&mscaler->lock, flags);
++
++	/* polling status to make sure channel stopped.*/
++	do {
++		val = mscaler_reg_readl(mscaler, MSCA_CH_STA);
++
++	} while(!!((val & (1<<ch)) << 0) && --timeout);
++
++
++	if(!timeout) {
++		dev_err(mscaler->dev, "[Warning] mscaler disable timeout!\n");
++	}
++
++	spin_lock_irqsave(&mscaler->lock, flags);
++
++	/* clear fifo*/
++	mscaler_reg_writel(mscaler, CHx_DMAOUT_Y_ADDR_CLR(ch), 1);
++	mscaler_reg_writel(mscaler, CHx_DMAOUT_UV_ADDR_CLR(ch), 1);
++	mscaler_reg_writel(mscaler, CHx_DMAOUT_Y_LAST_ADDR_CLR(ch), 1);
++	mscaler_reg_writel(mscaler, CHx_DMAOUT_UV_LAST_ADDR_CLR(ch), 1);
++
++
++	list_for_each_entry_safe(isp_buffer, tmp, &mscaler->dma_queued_list[ch], list_entry) {
++		struct vb2_buffer *vb2_buf = &isp_buffer->vb2.vb2_buf;
++		vb2_buffer_done(vb2_buf, VB2_BUF_STATE_ERROR);
++		list_del(&isp_buffer->list_entry);
++	}
++	list_for_each_entry_safe(isp_buffer, tmp, &mscaler->dma_pending_list[ch], list_entry) {
++		struct vb2_buffer *vb2_buf = &isp_buffer->vb2.vb2_buf;
++		vb2_buffer_done(vb2_buf, VB2_BUF_STATE_ERROR);
++		list_del(&isp_buffer->list_entry);
++	}
++
++
++	mscaler->state[ch] = 0;
++	spin_unlock_irqrestore(&mscaler->lock, flags);
++
++#ifdef CONFIG_MSCA_BDEV
++	if(mscaler->bdev[ch].activated) {
++		ms_bdev_deinit(&mscaler->bdev[ch]);
++		mscaler->bdev[ch].activated = 0;
++	}
++#endif
++
++	return ret;
++}
++
++static int mscaler_subdev_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct mscaler_device *mscaler = v4l2_get_subdevdata(sd);
++	struct isp_video_device *ispvideo = v4l2_get_subdev_hostdata(sd);
++	int ch = 0;
++	int i = 0, ret = 0;
++
++	for(i = 0; i < MSCALER_MAX_CH; i++) {
++		if(ispvideo == &mscaler->ispvideo[i]) {
++			ch = i;
++			break;
++		}
++	}
++
++//	printk("%s,%d, sd->video_device->name:%s, ispvideo: %p, ch = %d, enable = %d\n", __func__, __LINE__, sd->devnode->name, ispvideo, ch, enable);
++	/*获�当�channel.*/
++	if(enable) {
++		ret = mscaler_stream_enable(mscaler, ch);
++		//dump_mscaler_regs(mscaler);
++	} else {
++		ret = mscaler_stream_disable(mscaler, ch);
++	}
++
++	if(ret < 0) {
++		dev_err(mscaler->dev, "enable stream error!\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++
++static const struct v4l2_subdev_video_ops mscaler_subdev_video_ops = {
++        .s_stream = mscaler_subdev_s_stream,
++};
++
++
++static const struct v4l2_subdev_ops mscaler_subdev_ops = {
++        .core = &mscaler_subdev_core_ops,
++        .pad = &mscaler_subdev_pad_ops,
++        .video = &mscaler_subdev_video_ops,
++};
++
++
++static int mscaler_video_qbuf(struct isp_video_device *ispvideo, struct isp_video_buffer *isp_buffer)
++{
++	struct mscaler_device *mscaler = ispvideo->ispcam->mscaler;
++	struct vb2_buffer *vb2_buf = NULL;
++	int ch = 0;
++	unsigned long flags = 0;
++	unsigned int fifo_empty = 0;
++	unsigned int fifo_full = 0;
++	unsigned int y_fifo_st = 0, uv_fifo_st = 0;
++	dma_addr_t y_addr = 0;
++	dma_addr_t uv_addr = 0;
++	unsigned char *virt_uv_addr = NULL;
++	unsigned int uv_size = 0;
++	unsigned int uv_value;
++
++	int i = 0;
++	for(i = 0; i < MSCALER_MAX_CH; i++) {
++		if(ispvideo == &mscaler->ispvideo[i]) {
++			ch = i;
++			break;
++		}
++	}
++
++	spin_lock_irqsave(&mscaler->lock, flags);
++
++	list_add_tail(&isp_buffer->list_entry, &mscaler->dma_pending_list[ch]);
++
++	y_fifo_st = mscaler_reg_readl(mscaler, CHx_Y_ADDR_FIFO_STA(ch));
++	uv_fifo_st = mscaler_reg_readl(mscaler, CHx_UV_ADDR_FIFO_STA(ch));
++
++	if((y_fifo_st & (1<<0)) && (uv_fifo_st & (1<<0))) {
++		fifo_empty = 1;
++	} else if((y_fifo_st & (1<<4)) || (uv_fifo_st & (1<<4))) {
++		fifo_full = 1;
++	}
++
++	uv_value = mscaler->yonly_cf[ch].uv_value ;
++	/* 如果stream on了，就写入硬件.*/
++	if(mscaler->state[ch] == 1 && !fifo_full) {
++		isp_buffer = list_first_entry_or_null(&mscaler->dma_pending_list[ch], struct isp_video_buffer, list_entry);
++		vb2_buf = &isp_buffer->vb2.vb2_buf;
++		/*Y*/
++		y_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 0);
++		mscaler_reg_writel(mscaler, CHx_DMAOUT_Y_ADDR(ch), y_addr);
++
++		/*UV*/
++		if(vb2_buf->num_planes == 2) {
++			uv_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 1);
++			virt_uv_addr = vb2_plane_vaddr(vb2_buf, 1);
++			uv_size = vb2_plane_size(vb2_buf, 1);
++		} else {
++			uv_addr = y_addr + isp_buffer->uv_offset;
++			virt_uv_addr = vb2_plane_vaddr(vb2_buf, 0) + isp_buffer->uv_offset;
++			uv_size = vb2_plane_size(vb2_buf, 0) - isp_buffer->uv_offset;
++		}
++
++		if(mscaler->yonly_cf[ch].yonly_enable) {
++			if( isp_buffer->uv_value_backup[ch] != uv_value)
++				isp_buffer->uv_value_filled = 0;
++			if(!isp_buffer->uv_value_filled) {
++				memset(virt_uv_addr, uv_value, uv_size);
++				isp_buffer->uv_value_backup[ch] = uv_value;
++				isp_buffer->uv_value_filled = 1;
++			}
++		} else {
++			if(isp_buffer->uv_value_filled)
++				isp_buffer->uv_value_filled = 0;
++		}
++
++		mscaler_reg_writel(mscaler, CHx_DMAOUT_UV_ADDR(ch), uv_addr);
++		list_del(&isp_buffer->list_entry);
++		list_add_tail(&isp_buffer->list_entry, &mscaler->dma_queued_list[ch]);
++	}
++
++	spin_unlock_irqrestore(&mscaler->lock, flags);
++
++	//printk("-----%s,%d queued buffer y_addr: 0x%08x, uv: 0x%08x on ch: %d\n", __func__, __LINE__, y_addr, uv_addr, ch);
++
++	return 0;
++}
++
++static const struct isp_video_ops mscaler_video_ops = {
++	.find_format 	= mscaler_find_format,
++	.qbuf		= mscaler_video_qbuf,
++};
++
++static ssize_t
++dump_mscaler(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct mscaler_device *mscaler = dev_get_drvdata(dev);
++	char *p = buf;
++	int i = 0;
++
++	p += sprintf(p, "MSCA_CTRL	:0x%08x\n", mscaler_reg_readl(mscaler, MSCA_CTRL));
++	p += sprintf(p, "MSCA_CH_EN     :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_CH_EN));
++	p += sprintf(p, "MSCA_CH_STA    :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_CH_STA));
++	p += sprintf(p, "MSCA_INT_STA   :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_INT_STA));
++	p += sprintf(p, "MSCA_INT_MSK   :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_INT_MSK));
++	p += sprintf(p, "MSCA_INT_CLR   :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_INT_CLR));
++	p += sprintf(p, "MSCA_DMAOUT_ARB:0x%08x\n", mscaler_reg_readl(mscaler, MSCA_DMAOUT_ARB));
++	p += sprintf(p, "MSCA_CLK_GATE_EN:0x%08x\n", mscaler_reg_readl(mscaler, MSCA_CLK_GATE_EN));
++	p += sprintf(p, "MSCA_CLK_DIS   :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_CLK_DIS));
++	p += sprintf(p, "MSCA_SRC_IN    :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_SRC_IN));
++	p += sprintf(p, "MSCA_SRC_SIZE  :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_SRC_SIZE));
++	p += sprintf(p, "MSCA_GLO_RSZ_COEF_WR:0x%08x\n", mscaler_reg_readl(mscaler, MSCA_GLO_RSZ_COEF_WR));
++	p += sprintf(p, "MSCA_SYS_PRO_CLK_EN :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_SYS_PRO_CLK_EN));
++	p += sprintf(p, "MSCA_DS0_CLK_NUM    :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_DS0_CLK_NUM));
++	p += sprintf(p, "MSCA_DS1_CLK_NUM    :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_DS1_CLK_NUM));
++	p += sprintf(p, "MSCA_DS2_CLK_NUM    :0x%08x\n", mscaler_reg_readl(mscaler, MSCA_DS2_CLK_NUM));
++
++	for(i = 0; i < MSCALER_MAX_CH; i++) {
++
++		p += sprintf(p, "CHx_RSZ_OSIZE(%d)	:0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_RSZ_OSIZE(i)));
++		p += sprintf(p, "CHx_RSZ_STEP(%d)       :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_RSZ_STEP(i)));
++		p += sprintf(p, "CHx_CROP_OPOS(%d)      :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_CROP_OPOS(i)));
++		p += sprintf(p, "CHx_CROP_OSIZE(%d)     :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_CROP_OSIZE(i)));
++		p += sprintf(p, "CHx_FRA_CTRL_LOOP(%d)  :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_FRA_CTRL_LOOP(i)));
++		p += sprintf(p, "CHx_FRA_CTRL_MASK(%d)  :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_FRA_CTRL_MASK(i)));
++		p += sprintf(p, "CHx_MS0_POS(%d)        :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS0_POS(i)));
++		p += sprintf(p, "CHx_MS0_SIZE(%d)       :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS0_SIZE(i)));
++		p += sprintf(p, "CHx_MS0_VALUE(%d)      :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS0_VALUE(i)));
++		p += sprintf(p, "CHx_MS1_POS(%d)        :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS1_POS(i)));
++		p += sprintf(p, "CHx_MS1_SIZE(%d)       :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS1_SIZE(i)));
++		p += sprintf(p, "CHx_MS1_VALUE(%d)      :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS1_VALUE(i)));
++		p += sprintf(p, "CHx_MS2_POS(%d)        :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS2_POS(i)));
++		p += sprintf(p, "CHx_MS2_SIZE(%d)       :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS2_SIZE(i)));
++		p += sprintf(p, "CHx_MS2_VALUE(%d)      :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS2_VALUE(i)));
++		p += sprintf(p, "CHx_MS3_POS(%d)        :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS3_POS(i)));
++		p += sprintf(p, "CHx_MS3_SIZE(%d)       :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS3_SIZE(i)));
++		p += sprintf(p, "CHx_MS3_VALUE(%d)      :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_MS3_VALUE(i)));
++		p += sprintf(p, "CHx_OUT_FMT(%d)        :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_OUT_FMT(i)));
++		p += sprintf(p, "CHx_DMAOUT_Y_ADDR(%d)  :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_Y_ADDR(i)));
++		p += sprintf(p, "CHx_Y_ADDR_FIFO_STA(%d):0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_Y_ADDR_FIFO_STA(i)));
++	//	p += sprintf(p, "CHx_DMAOUT_Y_LAST_ADDR(%d)              :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_Y_LAST_ADDR(i)));
++	//	p += sprintf(p, "CHx_DMAOUT_Y_LAST_STATS_NUM(%d)         :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_Y_LAST_STATS_NUM(i)));
++		p += sprintf(p, "CHx_Y_LAST_ADDR_FIFO_STA(%d):0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_Y_LAST_ADDR_FIFO_STA(i)));
++		p += sprintf(p, "CHx_DMAOUT_Y_STRI(%d)       :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_Y_STRI(i)));
++		p += sprintf(p, "CHx_DMAOUT_UV_ADDR(%d)      :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_UV_ADDR(i)));
++		p += sprintf(p, "CHx_UV_ADDR_FIFO_STA(%d)    :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_UV_ADDR_FIFO_STA(i)));
++	//	p += sprintf(p, "CHx_DMAOUT_UV_LAST_ADDR(%d) :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_UV_LAST_ADDR(i)));
++	//	p += sprintf(p, "CHx_DMAOUT_UV_LAST_STATS_NUM(%d)        :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_UV_LAST_STATS_NUM(i)));
++		p += sprintf(p, "CHx_UV_LAST_ADDR_FIFO_STA(%d):0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_UV_LAST_ADDR_FIFO_STA(i)));
++		p += sprintf(p, "CHx_DMAOUT_UV_STRI(%d)       :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_UV_STRI(i)));
++		p += sprintf(p, "CHx_DMAOUT_Y_ADDR_CLR(%d)    :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_Y_ADDR_CLR(i)));
++		p += sprintf(p, "CHx_DMAOUT_UV_ADDR_CLR(%d)   :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_UV_ADDR_CLR(i)));
++		p += sprintf(p, "CHx_DMAOUT_Y_LAST_ADDR_CLR(%d):0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_Y_LAST_ADDR_CLR(i)));
++		p += sprintf(p, "CHx_DMAOUT_UV_LAST_ADDR_CLR(%d):0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_UV_LAST_ADDR_CLR(i)));
++		p += sprintf(p, "CHx_DMAOUT_Y_ADDR_SEL(%d)    :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_Y_ADDR_SEL(i)));
++		p += sprintf(p, "CHx_DMAOUT_UV_ADDR_SEL(%d)   :0x%08x\n", i, mscaler_reg_readl(mscaler, CHx_DMAOUT_UV_ADDR_SEL(i)));
++	}
++
++	return p - buf;
++}
++
++
++static DEVICE_ATTR(dump_mscaler, S_IRUGO|S_IWUSR, dump_mscaler, NULL);
++
++static struct attribute *mscaler_debug_attrs[] = {
++        &dev_attr_dump_mscaler.attr,
++	NULL,
++};
++
++static struct attribute_group mscaler_debug_attr_group = {
++        .name   = "debug",
++        .attrs  = mscaler_debug_attrs,
++};
++
++
++#define to_mscaler_device(kobj) dev_get_drvdata(container_of(kobj->parent->parent, struct device, kobj))
++
++static ssize_t uv_value_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch = kobj->name[2] - '0';
++	char *p = buf;
++	unsigned int uv_value= mscaler->yonly_cf[ch].uv_value ;
++
++	p += sprintf(p, "0x%x\n", uv_value);
++
++	return p - buf;
++}
++
++static ssize_t uv_value_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch = kobj->name[2] - '0';
++	mscaler->yonly_cf[ch].uv_value = simple_strtol(buf, NULL, 10);
++
++	return count;
++}
++
++static struct kobj_attribute uv_value_attribute =
++__ATTR(uv_value,S_IRUGO|S_IWUSR, uv_value_show, uv_value_store);
++
++static ssize_t yonly_enable_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch = kobj->name[2] - '0';
++	char *p = buf;
++	unsigned int enable= mscaler->yonly_cf[ch].yonly_enable ;
++
++	p += sprintf(p, "%d\n", enable);
++
++	return p - buf;
++}
++
++static ssize_t yonly_enable_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch = kobj->name[2] - '0';
++	struct v4l2_subdev_format *output_fmt = &mscaler->formats[ch_to_pad[ch]];
++	int enable = simple_strtol(buf, NULL, 10);
++	unsigned int val = 0;
++
++	if(enable == 1)
++		mscaler->yonly_cf[ch].yonly_enable=1;
++	else if(enable == 0)
++		mscaler->yonly_cf[ch].yonly_enable=0;
++	else
++		return -EINVAL;
++
++	if((output_fmt->format.code != MEDIA_BUS_FMT_YUYV8_2X8)
++			&& (output_fmt->format.code != MEDIA_BUS_FMT_YVYU8_2X8)) {
++		/*�记录enable状�，此时�能没有start_streaming, �能确定格�.*/
++		return count;
++	}
++
++	val = mscaler_reg_readl(mscaler, CHx_OUT_FMT(ch));
++	if(enable) {
++		val |= CHx_OUT_FMT_Y_OUT_ONLY;
++	} else {
++		val &= ~(CHx_OUT_FMT_Y_OUT_ONLY);
++	}
++	mscaler_reg_writel(mscaler, CHx_OUT_FMT(ch), val);
++
++	return count;
++}
++
++static struct kobj_attribute yonly_enable_attribute =
++__ATTR(enable,S_IRUGO|S_IWUSR, yonly_enable_show, yonly_enable_store);
++
++static ssize_t mask_enable_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch = kobj->name[2] - '0';
++	char *p = buf;
++	unsigned int tmp = 0;
++
++	tmp = mscaler_reg_readl(mscaler, MSCA_CH_EN);
++	p += sprintf(p, "%d\n", (tmp >> (ch + 3)) & 1);
++
++	return p - buf;
++}
++
++static ssize_t mask_enable_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch = kobj->name[2] - '0';
++	unsigned int tmp = 0;
++	int enable = simple_strtol(buf, NULL, 10);
++
++	tmp = mscaler_reg_readl(mscaler, MSCA_CH_EN);
++	if(enable == 1)
++		tmp |= 1 << (ch + 3);
++	else if(enable == 0)
++		tmp &= ~(1 << (ch + 3));
++	else
++		return -EINVAL;
++
++	mscaler_reg_writel(mscaler, MSCA_CH_EN, tmp);
++	return count;
++}
++
++static struct kobj_attribute enable_attribute =
++__ATTR(enable,S_IRUGO|S_IWUSR, mask_enable_show, mask_enable_store);
++
++
++static ssize_t mask_pos_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch= kobj->name[2] - '0';
++	int mask = to_mask_attr(attr)->id;
++	char *p = buf;
++	unsigned int tmp = 0;
++
++	tmp = mscaler_reg_readl(mscaler, CHx_MSx_POS(ch,mask));
++	p += sprintf(p, "x:%d\ty:%d\n", tmp >> 16, tmp & 0xffff);
++
++	return p - buf;
++}
++
++static ssize_t mask_pos_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch= kobj->name[2] - '0';
++	int mask = to_mask_attr(attr)->id;
++	char *p;
++	char *s = (char *)buf;
++	int pos_x, pos_y;
++
++	p = strsep(&s, "*");
++	if(!s) {
++		return -EINVAL;
++	}
++
++	pos_x = simple_strtoul(p, NULL, 10);
++	pos_y = simple_strtoul(s, NULL, 10);
++
++	mscaler_reg_writel(mscaler, CHx_MSx_POS(ch,mask), (pos_x << 16) | pos_y);
++	return count;
++}
++
++static ssize_t mask_size_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch= kobj->name[2] - '0';
++	int mask = to_mask_attr(attr)->id;
++	char *p = buf;
++	unsigned int tmp = 0;
++
++	tmp = mscaler_reg_readl(mscaler, CHx_MSx_SIZE(ch,mask));
++	p += sprintf(p, "width:%d\theight:%d\n", tmp >> 16, tmp & 0xffff);
++
++	return p - buf;
++}
++
++static ssize_t mask_size_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch= kobj->name[2] - '0';
++	int mask = to_mask_attr(attr)->id;
++	char *p;
++	char *s = (char *)buf;
++	int width, height;
++
++	p = strsep(&s, "*");
++	if(!s) {
++		return -EINVAL;
++	}
++
++	width = simple_strtoul(p, NULL, 10);
++	height = simple_strtoul(s, NULL, 10);
++
++	mscaler_reg_writel(mscaler, CHx_MSx_SIZE(ch,mask), (width << 16) | height);
++	return count;
++}
++static ssize_t mask_color_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch= kobj->name[2] - '0';
++	int mask = to_mask_attr(attr)->id;
++	char *p = buf;
++	unsigned int tmp = 0;
++
++	tmp = mscaler_reg_readl(mscaler, CHx_MSx_VALUE(ch,mask));
++	p += sprintf(p, "0x%08x\n", tmp);
++
++	return p - buf;
++}
++
++static ssize_t mask_color_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count)
++{
++	struct mscaler_device *mscaler = to_mscaler_device(kobj);
++	int ch= kobj->name[2] - '0';
++	int mask = to_mask_attr(attr)->id;
++	char *p;
++	char *s = (char *)buf;
++	int value = 0;
++
++	p = strsep(&s, "x");
++	if(!s) {
++		return -EINVAL;
++	}
++
++	value = simple_strtoul(s, NULL, 16);
++
++	mscaler_reg_writel(mscaler, CHx_MSx_VALUE(ch,mask), value);
++	return count;
++	return count;
++}
++
++#define MASK_ATTR(mask, _name, _mode, _show, _store)          \
++{                                                       \
++	.attr   = __ATTR(_name, _mode, _show, _store),  \
++	.id     = mask,                                                \
++}
++
++
++#define MASK_ATTRIBUTE(_name, _mode, _show, _store)                                                    \
++	static struct mask_kobj_attr kobj_attr_##_name##mask0 = MASK_ATTR(0, _name, _mode, _show, _store); \
++	static struct mask_kobj_attr kobj_attr_##_name##mask1 = MASK_ATTR(1, _name, _mode, _show, _store); \
++	static struct mask_kobj_attr kobj_attr_##_name##mask2 = MASK_ATTR(2, _name, _mode, _show, _store); \
++	static struct mask_kobj_attr kobj_attr_##_name##mask3 = MASK_ATTR(3, _name, _mode, _show, _store)
++
++MASK_ATTRIBUTE(pos, S_IRUGO|S_IWUSR, mask_pos_show, mask_pos_store);
++MASK_ATTRIBUTE(size, S_IRUGO|S_IWUSR, mask_size_show, mask_size_store);
++MASK_ATTRIBUTE(color, S_IRUGO|S_IWUSR, mask_color_show, mask_color_store);
++
++#define MASK_ATTRIBUTE_GROUP(name)                                     \
++	static struct attribute *mscaler_##name##_attrs[] = {               \
++		&kobj_attr_pos##name.attr.attr,                     \
++		&kobj_attr_size##name.attr.attr,                      \
++		&kobj_attr_color##name.attr.attr,                  \
++		NULL,                                                   \
++	};
++
++MASK_ATTRIBUTE_GROUP(mask0);
++MASK_ATTRIBUTE_GROUP(mask1);
++MASK_ATTRIBUTE_GROUP(mask2);
++MASK_ATTRIBUTE_GROUP(mask3);
++
++
++static struct attribute_group mscaler_mask0_group = {
++	.name = "mask0",
++	.attrs = mscaler_mask0_attrs,
++};
++static struct attribute_group mscaler_mask1_group = {
++	.name = "mask1",
++	.attrs = mscaler_mask1_attrs,
++};
++static struct attribute_group mscaler_mask2_group = {
++	.name = "mask2",
++	.attrs = mscaler_mask2_attrs,
++};
++static struct attribute_group mscaler_mask3_group = {
++	.name = "mask3",
++	.attrs = mscaler_mask3_attrs,
++};
++
++
++static const struct attribute_group *mscaler_maskx_groups[] = {
++	&mscaler_mask0_group,
++	&mscaler_mask1_group,
++	&mscaler_mask2_group,
++	&mscaler_mask3_group,
++	NULL,
++};
++
++static void __maybe_unused dump_mscaler_regs(struct mscaler_device *mscaler)
++{
++	char *buf = kzalloc(4 * 1024, GFP_KERNEL);
++	int ret = 0;
++
++	ret = dump_mscaler(mscaler->dev, NULL, buf);
++
++	printk("%s", buf);
++
++	kfree(buf);
++}
++
++int mscaler_video_nr_map[2][3] = {
++	{INGENIC_MSCA0_CH0_VIDEO_NR, INGENIC_MSCA0_CH1_VIDEO_NR, INGENIC_MSCA0_CH2_VIDEO_NR},
++	{INGENIC_MSCA1_CH0_VIDEO_NR, INGENIC_MSCA1_CH1_VIDEO_NR, INGENIC_MSCA1_CH2_VIDEO_NR},
++
++};
++
++static int mscaler_comp_bind(struct device *comp, struct device *master,
++                              void *master_data)
++{
++	struct mscaler_device *mscaler = dev_get_drvdata(comp);
++	struct ispcam_device *ispcam = (struct ispcam_device *)master_data;
++	struct v4l2_device *v4l2_dev = &ispcam->v4l2_dev;
++	struct v4l2_subdev *sd = &mscaler->sd;
++	int i = 0;
++	int ret = 0;
++	int nr = -1;
++
++	//dev_info(comp, "----dev_name(comp): %s----%s, %d \n", dev_name(comp), __func__, __LINE__);
++
++	/* link subdev to master.*/
++	mscaler->ispcam = (void *)ispcam;
++	ispcam->mscaler = mscaler;
++
++	/*1. register supported subdev ctrls.*/
++
++
++	/*2. init v4l2_subdev*/
++
++	v4l2_subdev_init(sd, &mscaler_subdev_ops);
++
++	sd->owner = THIS_MODULE;
++	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++	strscpy(sd->name, dev_name(comp), sizeof(sd->name));
++	v4l2_set_subdevdata(sd, mscaler);
++
++
++	/* init mscaler pads. */
++	mscaler->pads = kzalloc(sizeof(struct media_pad) * MSCALER_NUM_PADS, GFP_KERNEL);
++	if(!mscaler->pads) {
++		ret = -ENOMEM;
++		goto err_alloc_pads;
++	}
++	mscaler->pads[0].index = MSCALER_PAD_SINK;
++	mscaler->pads[0].flags = MEDIA_PAD_FL_SINK;
++	mscaler->pads[1].index = MSCALER_PAD_SOURCE_CH0;
++	mscaler->pads[1].flags = MEDIA_PAD_FL_SOURCE;
++	mscaler->pads[2].index = MSCALER_PAD_SOURCE_CH1;
++	mscaler->pads[2].flags = MEDIA_PAD_FL_SOURCE;
++	mscaler->pads[3].index = MSCALER_PAD_SOURCE_CH2;
++	mscaler->pads[3].flags = MEDIA_PAD_FL_SOURCE;
++
++	ret = media_entity_pads_init(&sd->entity, MSCALER_NUM_PADS, mscaler->pads);
++
++	/*3. register v4l2_subdev*/
++	sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER;
++	ret = v4l2_device_register_subdev(v4l2_dev, sd);
++	if(ret < 0) {
++		dev_err(comp, "Failed to register v4l2_subdev for mscaler\n");
++		goto err_subdev_register;
++	}
++
++	/*create mask dir*/
++	mscaler->mask_kobj = kobject_create_and_add("mask", &mscaler->dev->kobj);
++	if (!mscaler->mask_kobj) {
++		dev_err(mscaler->dev, "device create kobject failed\n");
++		ret = -EINVAL;
++		goto err_mask_kobj;
++	}
++	mscaler->yonly_kobj = kobject_create_and_add("yonly", &mscaler->dev->kobj);
++	if (!mscaler->yonly_kobj) {
++		dev_err(mscaler->dev, "device create kobject failed\n");
++		ret = -EINVAL;
++		goto err_yonly_kobj;
++	}
++
++
++	for(i = 0; i < MSCALER_MAX_CH; i++) {
++		struct isp_video_device *ispvideo = &mscaler->ispvideo[i];
++		char name[32];
++		sprintf(name, "%s-ch%d", dev_name(mscaler->dev), i);
++
++		ispvideo->ispcam = ispcam;
++		ispvideo->video.v4l2_dev = &ispcam->v4l2_dev;
++		ret = isp_video_init(ispvideo, name, &mscaler_video_ops);
++		if(ret < 0){
++			/*TODO*/
++		}
++
++		nr = mscaler_video_nr_map[ispcam->dev_nr][i];
++		ret = isp_video_register(ispvideo, &ispcam->v4l2_dev, nr);
++		if(ret < 0){
++			/*TODO*/
++		}
++
++		/*create mask/chx dir*/
++		sprintf(name, "ch%d", i);
++		mscaler->mask_ch_kobj[i] = kobject_create_and_add(name, mscaler->mask_kobj);
++		if (!mscaler->mask_ch_kobj[i]) {
++			dev_err(mscaler->dev, "device create kobject failed\n");
++			ret = -EINVAL;
++			goto err_mask_ch_kobj;
++		}
++
++		/*create yonly/chx dir*/
++		sprintf(name, "ch%d", i);
++		mscaler->yonly_ch_kobj[i] = kobject_create_and_add(name, mscaler->yonly_kobj);
++		if (!mscaler->yonly_ch_kobj[i]) {
++			dev_err(mscaler->dev, "device create kobject failed\n");
++			ret = -EINVAL;
++			goto err_yonly_ch_kobj;
++		}
++
++		/*create enable attr*/
++		ret = sysfs_create_file(mscaler->mask_ch_kobj[i], &enable_attribute.attr);
++		if(ret){
++			dev_err(mscaler->dev, "device create sys file failed\n");
++			goto err_mask_create_file;
++		}
++
++		/*create yonly enable attr*/
++		ret = sysfs_create_file(mscaler->yonly_ch_kobj[i], &yonly_enable_attribute.attr);
++		if(ret){
++			dev_err(mscaler->dev, "device create sys file failed\n");
++			goto err_yonly_create_file;
++		}
++
++		/*create yonly uv attr*/
++		ret = sysfs_create_file(mscaler->yonly_ch_kobj[i], &uv_value_attribute.attr);
++		if(ret){
++			dev_err(mscaler->dev, "device create sys file failed\n");
++			goto err_yonly_create_file;
++		}
++		mscaler->yonly_cf[i].uv_value = 0x80;
++
++		/*create mask/chx/maskx dir*/
++		ret = sysfs_create_groups(mscaler->mask_ch_kobj[i], mscaler_maskx_groups);
++		if(ret){
++			dev_err(mscaler->dev, "device create sys groups failed\n");
++			goto err_mask_create_groups;
++		}
++
++	}
++	return 0;
++err_mask_create_groups:
++err_mask_create_file:
++err_yonly_create_file:
++err_mask_ch_kobj:
++err_yonly_ch_kobj:
++err_mask_kobj:
++err_yonly_kobj:
++err_subdev_register:
++err_alloc_pads:
++	return ret;
++}
++
++
++static void mscaler_comp_unbind(struct device *comp, struct device *master,
++                                 void *master_data)
++{
++        struct mscaler_device *mscaler = dev_get_drvdata(comp);
++
++	dev_info(comp, "----TODO: %p----%s, %d \n", mscaler, __func__, __LINE__);
++
++}
++
++static const struct component_ops mscaler_comp_ops = {
++        .bind = mscaler_comp_bind,
++        .unbind = mscaler_comp_unbind,
++};
++
++
++
++
++static int ingenic_mscaler_probe(struct platform_device *pdev)
++{
++
++	struct mscaler_device *mscaler = NULL;
++	struct resource *regs = NULL;
++	int ret = 0;
++	int i = 0;
++
++	mscaler = kzalloc(sizeof(struct mscaler_device), GFP_KERNEL);
++	if(!mscaler) {
++		pr_err("Failed to alloc mscaler dev [%s]\n", pdev->name);
++		return -ENOMEM;
++	}
++
++	mscaler->dev = &pdev->dev;
++	platform_set_drvdata(pdev, mscaler);
++
++
++	mscaler->irq = platform_get_irq(pdev, 0);
++	if(mscaler->irq < 0) {
++		dev_warn(&pdev->dev, "No MScaler IRQ specified\n");
++	}
++
++	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if(!regs) {
++		dev_err(&pdev->dev, "No iomem resource!\n");
++		goto err_get_resource;
++	}
++
++	mscaler->iobase = devm_ioremap_resource(&pdev->dev, regs);
++	if(!mscaler->iobase) {
++		goto err_ioremap;
++	}
++
++	spin_lock_init(&mscaler->lock);
++
++	for(i = 0; i < MSCALER_MAX_CH; i++) {
++		INIT_LIST_HEAD(&mscaler->dma_queued_list[i]);
++		INIT_LIST_HEAD(&mscaler->dma_pending_list[i]);
++	}
++
++	ret = sysfs_create_group(&mscaler->dev->kobj, &mscaler_debug_attr_group);
++	if (ret) {
++		dev_err(mscaler->dev, "device create sysfs group failed\n");
++
++		ret = -EINVAL;
++		goto err_sys_group;
++	}
++
++
++	ret = component_add(mscaler->dev, &mscaler_comp_ops);
++	if(ret < 0) {
++		dev_err(mscaler->dev, "Failed to add component mscaler!\n");
++	}
++
++	return 0;
++err_sys_group:
++err_ioremap:
++err_get_resource:
++
++	return ret;
++}
++
++
++
++static int ingenic_mscaler_remove(struct platform_device *pdev)
++{
++
++	return 0;
++}
++
++
++
++static const struct of_device_id ingenic_mscaler_dt_match[] = {
++        { .compatible = "ingenic,x2000-mscaler" },
++        { .compatible = "ingenic,m300-mscaler" },
++        { }
++};
++
++MODULE_DEVICE_TABLE(of, ingenic_mscaler_dt_match);
++
++static int __maybe_unused ingenic_mscaler_suspend(struct platform_device *pdev, pm_message_t state)
++{
++        return 0;
++}
++
++static int __maybe_unused ingenic_mscaler_resume(struct platform_device *pdev)
++{
++        return 0;
++}
++
++static struct platform_driver ingenic_mscaler_driver = {
++        .probe = ingenic_mscaler_probe,
++        .remove = ingenic_mscaler_remove,
++	.suspend = ingenic_mscaler_suspend,
++	.resume = ingenic_mscaler_resume,
++        .driver = {
++                .name = "ingenic-mscaler",
++                .of_match_table = ingenic_mscaler_dt_match,
++        },
++};
++
++module_platform_driver(ingenic_mscaler_driver);
++
++MODULE_ALIAS("platform:ingenic-mscaler");
++MODULE_DESCRIPTION("ingenic mscaler subsystem");
++MODULE_AUTHOR("qipengzhen <aric.pzqi@ingenic.com>");
++MODULE_LICENSE("GPL v2");
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/sensor.c b/module_drivers/drivers/media/platform/ingenic-isp/sensor.c
+new file mode 100644
+index 000000000..08342aed0
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/sensor.c
+@@ -0,0 +1,302 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-mediabus.h>
++#include <media/v4l2-image-sizes.h>
++
++#include "isp-drv.h"
++
++
++#define to_isp_device(c) 	(struct isp_device *)c->priv_data
++#define to_sensor_device(isp) 	&isp->ispcam->sensor
++
++static void sensor_hw_reset_enable(sensor_control_t *ctrl)
++{
++	printk("----%s, %d\n", __func__, __LINE__);
++}
++
++static void sensor_hw_reset_disable(sensor_control_t *ctrl)
++{
++	printk("----%s, %d\n", __func__, __LINE__);
++}
++
++static int32_t sensor_alloc_analog_gain(sensor_control_t *ctrl, int32_t gain, sensor_context_t *p_ctx)
++{
++	/* printk("result gain is 0x%x\n",again); */
++	return gain;
++}
++
++static int32_t sensor_alloc_digital_gain(sensor_control_t *ctrl, int32_t gain, sensor_context_t *p_ctx)
++{
++	printk("----%s, %d, gain: %d\n", __func__, __LINE__, gain);
++
++	/* printk("result gain is 0x%x\n",p_ctx->dgain); */
++	return gain;
++}
++
++static void sensor_alloc_integration_time(sensor_control_t *ctrl, uint16_t *int_time, sensor_context_t *p_ctx)
++{
++	printk("----%s, %d\n", __func__, __LINE__);
++}
++
++static void sensor_set_integration_time(sensor_control_t *ctrl, uint16_t int_time, sensor_param_t* param)
++{
++	struct isp_device *isp = to_isp_device(ctrl);
++	struct sensor_device *sensor = to_sensor_device(isp);
++	struct v4l2_control exposure;
++	int ret = 0;
++
++	exposure.id = V4L2_CID_EXPOSURE;
++	exposure.value = int_time;
++
++	ret = v4l2_s_ctrl(NULL, sensor->isd->sd->ctrl_handler, &exposure);
++	if(ret < 0) {
++		dev_err(isp->dev, "failed to set exposure!\n");
++	}
++}
++
++static void sensor_set_analog_gain(sensor_control_t *ctrl, uint32_t again_reg_val, sensor_context_t *p_ctx)
++{
++	struct isp_device *isp = to_isp_device(ctrl);
++	struct sensor_device *sensor = to_sensor_device(isp);
++	struct v4l2_control analog;
++	int ret = 0;
++
++	analog.id = V4L2_CID_ANALOGUE_GAIN;
++	analog.value = again_reg_val;
++
++	ret = v4l2_s_ctrl(NULL, sensor->isd->sd->ctrl_handler, &analog);
++	if(ret < 0) {
++		printk("error s_ctrl, ret: %d\n", ret);
++	}
++}
++
++static int sensor_get_analog_gain(sensor_control_t *ctrl, uint32_t *again_reg_val, sensor_context_t *p_ctx)
++{
++	struct isp_device *isp = to_isp_device(ctrl);
++	struct sensor_device *sensor = to_sensor_device(isp);
++	struct v4l2_control analog;
++	int ret = 0;
++
++	analog.id = V4L2_CID_ANALOGUE_GAIN;
++	analog.value = 0;
++
++	ret = v4l2_g_ctrl(sensor->isd->sd->ctrl_handler, &analog);
++	if(ret < 0) {
++		printk("error s_ctrl, ret: %d\n", ret);
++	}
++
++
++	*again_reg_val = analog.value;
++
++	return ret;
++}
++
++
++static void sensor_set_digital_gain(sensor_control_t *ctrl, uint32_t dgain_reg_val, sensor_context_t *p_ctx)
++{
++	struct isp_device *isp = to_isp_device(ctrl);
++	struct sensor_device *sensor = to_sensor_device(isp);
++	struct v4l2_control control;
++	int ret = 0;
++
++	control.id = V4L2_CID_GAIN;
++	control.value = dgain_reg_val;
++
++	ret = v4l2_s_ctrl(NULL, sensor->isd->sd->ctrl_handler, &control);
++	if(ret < 0) {
++		printk("error s_ctrl, ret: %d\n", ret);
++	}
++}
++
++static int sensor_get_digital_gain(sensor_control_t *ctrl, uint32_t *dgain_reg_val, sensor_context_t *p_ctx)
++{
++	struct isp_device *isp = to_isp_device(ctrl);
++	struct sensor_device *sensor = to_sensor_device(isp);
++	struct v4l2_control control;
++	int ret = 0;
++
++	control.id = V4L2_CID_GAIN;
++	control.value = 0;
++
++	ret = v4l2_g_ctrl(sensor->isd->sd->ctrl_handler, &control);
++	if(ret < 0) {
++		printk("error s_ctrl, ret: %d\n", ret);
++	}
++
++	*dgain_reg_val = control.value;
++
++	return ret;
++}
++
++
++static uint16_t sensor_get_normal_fps(sensor_control_t *ctrl, sensor_param_t* param)
++{
++	printk("----%s, %d\n", __func__, __LINE__);
++	return 0;
++}
++
++static uint16_t sensor_read_black_pedestal(sensor_control_t *ctrl, int i,uint32_t gain)
++{
++	printk("----%s, %d\n", __func__, __LINE__);
++	return 0;
++}
++
++static void sensor_set_mode(sensor_control_t *ctrl, uint8_t mode, sensor_param_t* param)
++{
++	printk("----%s, %d\n", __func__, __LINE__);
++}
++
++static void sensor_start_changes(sensor_control_t *ctrl, sensor_context_t *p_ctx)
++{
++	printk("----%s, %d\n", __func__, __LINE__);
++}
++
++static void sensor_end_changes(sensor_control_t *ctrl, sensor_context_t *p_ctx)
++{
++	printk("----%s, %d\n", __func__, __LINE__);
++}
++
++static uint16_t sensor_get_id(sensor_control_t *ctrl)
++{
++	printk("----%s, %d\n", __func__, __LINE__);
++
++	return 0;
++}
++
++static void sensor_set_wdr_mode(sensor_control_t *ctrl, uint8_t mode, sensor_param_t* param)
++{
++	printk("----%s, %d\n", __func__, __LINE__);
++}
++
++static uint32_t sensor_fps_control(sensor_control_t *ctrl, uint8_t fps, sensor_param_t* param)
++{
++
++	printk("----%s, %d\n", __func__, __LINE__);
++	return 0;
++}
++
++static void sensor_disable_isp(sensor_control_t *ctrl)
++{
++	printk("----%s, %d\n", __func__, __LINE__);
++}
++
++static uint32_t sensor_get_lines_per_second(sensor_control_t *ctrl, sensor_param_t* param)
++{
++	uint32_t lines_per_second=0;
++	printk("----%s, %d\n", __func__, __LINE__);
++	return lines_per_second;
++}
++
++struct sensor_control_ops sensor_ctrl_ops = {
++	.hw_reset_disable 	= sensor_hw_reset_disable,
++	.hw_reset_enable 	= sensor_hw_reset_enable,
++	.alloc_analog_gain 	= sensor_alloc_analog_gain,
++	.alloc_digital_gain 	= sensor_alloc_digital_gain,
++	.alloc_integration_time = sensor_alloc_integration_time,
++	.set_integration_time 	= sensor_set_integration_time,
++	.start_changes 		= sensor_start_changes,
++	.end_changes 		= sensor_end_changes,
++	.set_analog_gain 	= sensor_set_analog_gain,
++	.get_analog_gain 	= sensor_get_analog_gain,
++	.set_digital_gain 	= sensor_set_digital_gain,
++	.get_digital_gain 	= sensor_get_digital_gain,
++	.get_normal_fps 	= sensor_get_normal_fps,
++	.read_black_pedestal 	= sensor_read_black_pedestal,
++	.set_mode 		= sensor_set_mode,
++	.set_wdr_mode 		= sensor_set_wdr_mode,
++	.fps_control 		= sensor_fps_control,
++	.get_id			= sensor_get_id,
++	.disable_isp		= sensor_disable_isp,
++	.get_lines_per_second	= sensor_get_lines_per_second
++};
++
++void sensor_init(sensor_control_t *ctrl, void *priv_data)
++{
++	tisp_core_t *core = priv_data;
++	struct isp_device *isp = core->priv_data;
++	struct sensor_device *sensor = to_sensor_device(isp);
++	struct v4l2_queryctrl query;
++	tisp_init_param_t *sensor_info = &core->sensor_info;
++	int ret = 0;
++
++	query.id = V4L2_CID_EXPOSURE;
++	query.type = V4L2_CTRL_TYPE_INTEGER;
++	ret = v4l2_queryctrl(sensor->isd->sd->ctrl_handler, &query);
++	if(ret < 0) {
++		dev_err(isp->dev, "query sensor V4L2_CID_EXPOSURE failed\n");
++	}
++
++	ctrl->param.integration_time_min = query.minimum;
++	ctrl->param.integration_time_max = query.maximum;
++
++	query.id = V4L2_CID_ANALOGUE_GAIN;
++	query.type = V4L2_CTRL_TYPE_INTEGER;
++	ret = v4l2_queryctrl(sensor->isd->sd->ctrl_handler, &query);
++	if(ret < 0) {
++		dev_err(isp->dev, "query sensor V4L2_CID_ANALOGUE_GAIN failed\n");
++	}
++	ctrl->param.again_log2_max = query.maximum;
++
++
++	query.id = V4L2_CID_GAIN;
++	query.type = V4L2_CTRL_TYPE_INTEGER;
++	ret = v4l2_queryctrl(sensor->isd->sd->ctrl_handler, &query);
++	if(ret < 0) {
++		dev_err(isp->dev, "queyr sensor V4L2_CID_GAIN failed\n");
++	}
++	ctrl->param.dgain_log2_max = query.maximum;
++
++#if 0
++	struct tx_isp_video_in *vin = &core->vin;
++	struct tx_isp_sensor_attribute *attr = vin->attr;
++
++	ctrl->param.again_log2_max = 		attr->max_again;
++	ctrl->param.dgain_log2_max= 		attr->max_dgain;
++	ctrl->param.integration_time_apply_delay = attr->integration_time_apply_delay;
++	ctrl->param.analog_gain_apply_delay = 	attr->again_apply_delay;
++	ctrl->param.digital_gain_apply_delay = 	attr->dgain_apply_delay;
++	ctrl->param.integration_time_min = 	attr->min_integration_time;
++	ctrl->param.integration_time_max = 	attr->max_integration_time;
++#endif
++	ctrl->priv_data = isp;
++	isp->core.sensor_ctrl_ops = &sensor_ctrl_ops;
++
++	/*fill sensor_info*/
++	sensor_info->sensor_info.max_again = ctrl->param.again_log2_max;       //the format is .16
++	sensor_info->sensor_info.max_dgain = ctrl->param.dgain_log2_max;      //the format is .16
++// 	sensor_info->sensor_info.again = core->vin.attr->again;
++// 	sensor_info->sensor_info.dgain = core->vin.attr->dgain;
++// 	sensor_info->sensor_info.fps = core->vin.fps;
++	sensor_info->sensor_info.min_integration_time = ctrl->param.integration_time_min;
++	sensor_info->sensor_info.max_integration_time = ctrl->param.integration_time_max;
++// 	sensor_info->sensor_info.min_integration_time_native = core->vin.attr->min_integration_time_native;
++// 	sensor_info->sensor_info.max_integration_time_native = core->vin.attr->max_integration_time_native;
++// 	sensor_info->sensor_info.integration_time_limit = core->vin.attr->integration_time_limit;
++// 	sensor_info->sensor_info.integration_time = core->vin.attr->integration_time;
++// 	sensor_info->sensor_info.total_width = core->vin.attr->total_width;
++// 	sensor_info->sensor_info.total_height = core->vin.attr->total_height;
++// 	sensor_info->sensor_info.integration_time_apply_delay = core->vin.attr->integration_time_apply_delay;
++// 	sensor_info->sensor_info.again_apply_delay = core->vin.attr->again_apply_delay;
++// 	sensor_info->sensor_info.dgain_apply_delay = core->vin.attr->dgain_apply_delay;
++//	sensor_info->sensor_info.one_line_expr_in_us = core->vin.attr->one_line_expr_in_us;
++
++}
++
++
++
++int sensor_device_probe(struct sensor_device *sensor, struct ispcam_device *ispcam)
++{
++	int ret = 0;
++	sensor->ispcam = ispcam;
++	sensor->isp = ispcam->isp;
++	sensor->isd = &ispcam->isd[0];
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(sensor_device_probe);
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/vic-regs.h b/module_drivers/drivers/media/platform/ingenic-isp/vic-regs.h
+new file mode 100644
+index 000000000..46d8fa84a
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/vic-regs.h
+@@ -0,0 +1,157 @@
++#ifndef __INGENIC_ISP_VIC_REG_H__
++#define __INGENIC_ISP_VIC_REG_H__
++
++#define VIC_CONTROL			0x00
++#define VIC_RESOLUTION	 		0x04
++#define VIC_FRM_ECC                     0x08
++#define VIC_INTF_TYPE                   0x0C
++#define VIC_IN_DVP			0x10
++#define VIC_IN_CSI_FMT                  0x14
++#define VIC_IN_HOR_PARA0                0x18
++#define VIC_IN_HOR_PARA1                0x1C
++#define VIC_BK_CB_CTRL	                0x28
++#define VIC_BK_CB_BLK	                0x2C
++#define VIC_IN_VER_PARA0                0x30
++#define VIC_IN_VER_PARA1                0x34
++#define VIC_IN_VER_PARA2                0x38
++#define VIC_IN_VER_PARA3                0x3C
++#define VIC_VLD_LINE_SAV		0x60
++#define VIC_VLD_LINE_EAV		0x64
++#define VIC_VLD_FRM_SAV			0x70
++#define VIC_VLD_FRM_EAV			0x74
++#define VIC_VC_CONTROL			0x8C
++#define VIC_VC_CONTROL_CH0_PIX		0x90
++#define VIC_VC_CONTROL_CH1_PIX		0x94
++#define VIC_VC_CONTROL_CH2_PIX		0x98
++#define VIC_VC_CONTROL_CH3_PIX		0x9C
++#define VIC_VC_CONTROL_CH0_LINE		0xA0
++#define VIC_VC_CONTROL_CH1_LINE		0xA4
++#define VIC_VC_CONTROL_CH2_LINE		0xA8
++#define VIC_VC_CONTROL_CH3_LINE		0xAC
++#define VIC_VC_CONTROL_FIFO_USE		0xB0
++#define VIC_CB_1ST			0xC0
++#define VIC_CB_2ND			0xC4
++#define VIC_CB_3RD			0xC8
++#define VIC_CB_4TH			0xCC
++#define VIC_CB_5TH			0xD0
++#define VIC_CB_6TH			0xD4
++#define VIC_CB_7TH			0xD8
++#define VIC_CB_8TH			0xDC
++#define VIC_CB2_1ST			0xE0
++#define VIC_CB2_2ND			0xE4
++#define VIC_CB2_3RD			0xE8
++#define VIC_CB2_4TH			0xEC
++#define VIC_CB2_5TH			0xF0
++#define VIC_CB2_6TH			0xF4
++#define VIC_CB2_7TH			0xF8
++#define VIC_CB2_8TH			0xFC
++#define MIPI_ALL_WIDTH_4BYTE		0x100
++#define MIPI_VCROP_DEL01		0x104
++#define MIPI_SENSOR_CONTROL		0x10C
++#define MIPI_HCROP_CH0			0x110
++#define MIPI_VCROP_SHADOW_CFG		0x120
++#define VIC_CONTROL_LIMIT		0x1A0
++#define VIC_CONTROL_DELAY		0x1A4
++#define VIC_CONTROL_TIZIANO_ROUTE	0x1A8
++#define VIC_CONTROL_DMA_ROUTE		0x1B0
++#define VIC_INT_STA			0X1E0
++#define VIC_INT_MASK			0x1E8
++#define VIC_INT_CLR			0x1F0
++/*DMA register*/
++#define VIC_DMA_OUTPUT_MAX_WIDTH 2688
++#define VIC_DMA_CONFIG			0x300
++#define VIC_DMA_RESOLUTION		0x304
++#define VIC_DMA_RESET			0x308
++#define VIC_DMA_Y_STRID			0x314
++#define VIC_DMA_Y_BUF0			0x318
++#define VIC_DMA_Y_BUF1			0x31c
++#define VIC_DMA_Y_BUF2			0x320
++#define VIC_DMA_Y_BUF3			0x324
++#define VIC_DMA_Y_BUF4			0x328
++#define VIC_DMA_UV_STRID		0x334
++#define VIC_DMA_UV_BUF0			0x338
++#define VIC_DMA_UV_BUF1			0x33c
++#define VIC_DMA_UV_BUF2			0x340
++#define VIC_DMA_UV_BUF3			0x344
++#define VIC_DMA_UV_BUF4			0x348
++
++/*TIMESTAMP registers*/
++#define VIC_TS_ENABLE			0x360	/* 控制使能*/
++    #define TS_COUNTER_EN			(1 << 0)/*使能计数器*/
++    #define TS_VIC_DMA_EN			(1 << 4)/*使能VIC DMA的timstsamp*/
++    #define TS_MS_CH0_EN			(1 << 5)/*使能MSCALER CH0 ts*/
++    #define TS_MS_CH1_EN			(1 << 6)/*使能MSCALER CH1 ts*/
++    #define TS_MS_CH2_EN			(1 << 7)/*使能MSCALER CH2 ts*/
++#define VIC_TS_COUNTER			0x368	/* 多少个ISP时钟周期计数一次 */
++/* timestamp 写入到帧数�中的�移�置.*/
++#define VIC_TS_DMA_OFFSET		0x370
++#define VIC_TS_MS_CH0_OFFSET		0x374
++#define VIC_TS_MS_CH1_OFFSET		0x378
++#define VIC_TS_MS_CH2_OFFSET		0x37c
++
++
++
++
++
++/*VIC_CONTROL*/
++//#define VIC_RESET			(1<<4)
++#define GLB_RST				(1<<2)
++#define REG_ENABLE			(1<<1)
++#define VIC_START			(1<<0)
++
++/*VIC_RESOLUTION*/
++#define H_RESOLUTION			(1<<16)
++#define V_RESOLUTION			(1)
++
++/*VIC_FRM_ECC*/
++#define FRAME_ECC_EN		       (1<<0)
++#define FRAME_ECC_MODE		       (1<<1)
++
++/*VIC_INTF_TYPE*/
++#define INTF_TYPE_BT656			0x0
++#define INTF_TYPE_BT601			0x1
++#define INTF_TYPE_MIPI			0x2
++#define INTF_TYPE_DVP			0x3
++#define INTF_TYPE_BT1120		0x4
++
++/*VIC_IN_DVP*/
++#define DVP_DATA_POS			(1<<24)
++#define DVP_RGB_ORDER			(1<<21)
++#define DVP_RAW_ALIG			(1<<20)
++#define DVP_DATA_TYPE			(17)
++#define DVP_RAW8			(0<<DVP_DATA_TYPE)
++#define DVP_RAW10			(1<<DVP_DATA_TYPE)
++#define DVP_RAW12			(2<<DVP_DATA_TYPE)
++#define DVP_YUV422_16BIT		(3<<DVP_DATA_TYPE)
++//#define DVP_RGB565_16BIT		(4<<DVP_DATA_TYPE)
++//#define DVP_BRG565_16BIT		(5<<DVP_DATA_TYPE)
++#define DVP_YUV422_8BIT			(6<<DVP_DATA_TYPE)
++//#define DVP_RGB565_8BIT			(7<<DVP_DATA_TYPE)
++#define DVP_TIMEING_MODE		(1<<15)
++#define DVP_HSYNC_MODE			(1 << 15)
++#define DVP_SONY_MODE			(2 << 15)
++#define BT_INTF_WIDE			(1<<11)
++#define BT_LINE_MODE			(1<<10)
++#define BT_601_TIMING_MODE		(1<<9)
++#define YUV_DATA_ORDER			(4)
++#define YVYU				(0<<YUV_DATA_ORDER)
++#define YUYV				(1<<YUV_DATA_ORDER)
++#define VYUY				(2<<YUV_DATA_ORDER)
++#define UYVY				(3<<YUV_DATA_ORDER)
++#define FIRST_FIELD_TYPE		(1<<3)
++#define INTERLACE_EN			(1<<2)
++#define HSYN_POLAR			(1<<1)
++#define VSYN_POLAR			(1<<0)
++
++/*VIC_IN_CSI_FMT*/
++#define MIPI_RAW8			0x0
++#define MIPI_RAW10			0x1
++#define MIPI_RAW12			0x2
++//#define MIPI_RGB555			0x3
++//#define MIPI_RGB565			0x4
++//#define MIPI_RGB666			0x5
++//#define MIPI_RGB888			0x6
++#define MIPI_YUV422			0x7
++//#define MIPI_YUV422_10BIT		0x8
++
++#endif/* __VIC_REG_H__ */
+diff --git a/module_drivers/drivers/media/platform/ingenic-isp/vic.c b/module_drivers/drivers/media/platform/ingenic-isp/vic.c
+new file mode 100644
+index 000000000..707f9c943
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-isp/vic.c
+@@ -0,0 +1,1224 @@
++//#define DEBUG
++#include <linux/clk.h>
++#include <linux/media-bus-format.h>
++#include <linux/media.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_graph.h>
++#include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
++#include <linux/pm_domain.h>
++#include <linux/slab.h>
++#include <linux/videodev2.h>
++#include <linux/component.h>
++#include <linux/clk.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/kthread.h>
++#include <linux/delay.h>
++
++#include <media/media-device.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-event.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++#include <media/ingenic_video_nr.h>
++
++#include "isp-drv.h"
++#include "vic-regs.h"
++
++#define VIC_STOP_BUFFER_COUNT 2
++#define VIC_RESTART_BUFFER_COUNT 3
++
++int count_period = 256;
++module_param(count_period, int, S_IRUGO);
++MODULE_PARM_DESC(count_period, "vic counter period");
++
++int vic_stop_counter = 0;
++module_param(vic_stop_counter, int, S_IRUGO);
++MODULE_PARM_DESC(vic_stop_counter, "vic0 bypass mode stop counter");
++
++int dma_debug_en = 0;
++module_param(dma_debug_en, int, 0664);
++MODULE_PARM_DESC(dma_debug_en, "vic dma debug mode enable");
++
++int timestamp_en = 0;
++module_param(timestamp_en, int, 0664);
++MODULE_PARM_DESC(timestamp_en, "vic dma debug mode enable");
++
++struct isp_video_format vic_mipi_formats[] = {
++	/*yuv422 */
++	{
++		.name     = "YUV422, YUYV",
++		.fourcc   = V4L2_PIX_FMT_YUYV,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	{
++		.name     = "YUV422, YVYU",
++		.fourcc   = V4L2_PIX_FMT_YVYU,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	{
++		.name     = "YUV422, UYVY",
++		.fourcc   = V4L2_PIX_FMT_UYVY,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	{
++		.name     = "YUV422, VYUY",
++		.fourcc   = V4L2_PIX_FMT_VYUY,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
++		.colorspace = V4L2_COLORSPACE_DEFAULT,
++	},
++	/* dvp: Y8_1X8 */
++	{
++		.name     = "Y8, GREY",
++		.fourcc   = V4L2_PIX_FMT_GREY,
++		.depth    = {8},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_Y8_1X8,
++		.colorspace = V4L2_COLORSPACE_RAW,
++	},
++	/* RAW8 */
++	{
++		.name     = "RAW8, 8  BGBG.. GRGR..",
++		.fourcc   = V4L2_PIX_FMT_SBGGR8,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW8, 8  GBGB.. RGRG..",
++		.fourcc   = V4L2_PIX_FMT_SGBRG8,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW8, 8  GRGR.. BGBG..",
++		.fourcc   = V4L2_PIX_FMT_SGRBG8,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW8, 8  RGRG.. GBGB..",
++		.fourcc   = V4L2_PIX_FMT_SRGGB8,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	/* RAW10 */
++	{
++		.name     = "RAW10, 10  BGBG.. GRGR..",
++		.fourcc   = V4L2_PIX_FMT_SBGGR10,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW10, 10  GBGB.. RGRG..",
++		.fourcc   = V4L2_PIX_FMT_SGBRG10,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW10, 10  GRGR.. BGBG..",
++		.fourcc   = V4L2_PIX_FMT_SGRBG10,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW10, 10  RGRG.. GBGB..",
++		.fourcc   = V4L2_PIX_FMT_SRGGB10,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	/* RAW12 */
++	{
++		.name     = "RAW12, 12  BGBG.. GRGR..",
++		.fourcc   = V4L2_PIX_FMT_SBGGR12,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW12, 12  GBGB.. RGRG..",
++		.fourcc   = V4L2_PIX_FMT_SGBRG12,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW12, 12  GRGR.. BGBG..",
++		.fourcc   = V4L2_PIX_FMT_SGRBG12,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++	{
++		.name     = "RAW12, 12  RGRG.. GBGB..",
++		.fourcc   = V4L2_PIX_FMT_SRGGB12,
++		.depth    = {16},
++		.num_planes = 1,
++		.mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
++		.colorspace = V4L2_COLORSPACE_SRGB,
++	},
++};
++
++struct isp_video_format vic_dvp_formats = {
++
++};
++
++
++static inline void vic_reg_writel(struct vic_device *vic, unsigned int reg, unsigned int val)
++{
++	writel(val, vic->iobase + reg);
++}
++
++static inline unsigned int vic_reg_readl(struct vic_device *vic, unsigned int reg)
++{
++	return readl(vic->iobase + reg);
++}
++
++
++static int ingenic_vic_parse_dt(struct vic_device * vic)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++static const struct v4l2_subdev_core_ops vic_subdev_core_ops = {
++        .log_status = v4l2_ctrl_subdev_log_status,
++        .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
++        .unsubscribe_event = v4l2_event_subdev_unsubscribe,
++};
++
++static int vic_subdev_get_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct vic_device *vic = v4l2_get_subdevdata(sd);
++	struct media_pad *remote = NULL;
++	struct v4l2_subdev *remote_sd = NULL;
++	struct v4l2_subdev_format remote_subdev_fmt;
++	int ret = 0;
++
++	remote = media_entity_remote_pad(&vic->pads[VIC_PAD_SINK]);
++	remote_sd = media_entity_to_v4l2_subdev(remote->entity);
++
++	/*获��当�格�，�制到输出格�.*/
++	remote_subdev_fmt.pad = remote->index;
++	remote_subdev_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	ret = v4l2_subdev_call(remote_sd, pad, get_fmt, NULL, &remote_subdev_fmt);
++	if(ret < 0) {
++		dev_err(vic->dev, "Failed to get_fmt from remote pad\n");
++		return -EINVAL;
++	}
++
++	memcpy(&format->format, &remote_subdev_fmt.format, sizeof(format->format));
++
++	vic->formats[VIC_PAD_SINK] = vic->formats[VIC_PAD_SOURCE] = *format;
++
++	//printk("----%s, %d, format->pad: %d\n", __func__, __LINE__, format->pad);
++	return 0;
++}
++
++static int vic_subdev_set_fmt(struct v4l2_subdev *sd,
++		       struct v4l2_subdev_pad_config *cfg,
++		       struct v4l2_subdev_format *format)
++{
++	struct vic_device *vic = v4l2_get_subdevdata(sd);
++	struct media_pad *remote = NULL;
++	struct v4l2_subdev *remote_sd = NULL;
++	struct v4l2_subdev_format remote_subdev_fmt;
++	int ret = 0;
++
++	dev_dbg(vic->dev, "%s, %d, width: %d, height: %d, mbus_code: %x\n", __func__, __LINE__, format->format.width, format->format.height, format->format.code);
++
++	vic->formats[VIC_PAD_SOURCE] = *format;
++
++	remote = media_entity_remote_pad(&vic->pads[VIC_PAD_SINK]);
++	remote_sd = media_entity_to_v4l2_subdev(remote->entity);
++
++	ret = v4l2_subdev_call(remote_sd, pad, set_fmt, NULL, format);
++	if(ret < 0) {
++		dev_dbg(vic->dev, "Failed to set_fmt from remote pad\n");
++	}
++
++	/*获��当�格�，�制到输出格�.*/
++	remote_subdev_fmt.pad = remote->index;
++	remote_subdev_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
++	ret = v4l2_subdev_call(remote_sd, pad, get_fmt, NULL, &remote_subdev_fmt);
++	if(ret < 0) {
++		dev_err(vic->dev, "Failed to get_fmt from remote pad\n");
++		return -EINVAL;
++	}
++
++	memcpy(&vic->formats[VIC_PAD_SINK], &remote_subdev_fmt, sizeof(struct v4l2_subdev_format));
++	vic->sensor_info = (struct sensor_info *)*(unsigned int *)remote_subdev_fmt.format.reserved;
++
++	return 0;
++}
++
++
++static const struct v4l2_subdev_pad_ops vic_subdev_pad_ops = {
++	.get_fmt		= vic_subdev_get_fmt,
++	.set_fmt		= vic_subdev_set_fmt,
++};
++
++
++static int vic_cfg_stream_mipi(struct vic_device *vic)
++{
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	struct mipi_cfg *mipi_cfg = &vic->sensor_info->mipi_cfg;
++	//unsigned int timeout = 10000;
++	int mwidth = mipi_cfg->twidth;
++
++	dev_dbg(vic->dev, "%s, %d, input_fmt->format.width: %d, intput_fmt->format.height: %d\n",
++		__func__, __LINE__, input_fmt->format.width, input_fmt->format.height);
++	dev_dbg(vic->dev, "%s, %d, mipi_cfg->twidth: %d\n",
++		__func__, __LINE__, mipi_cfg->twidth);
++
++	vic_reg_writel(vic, VIC_INTF_TYPE, INTF_TYPE_MIPI);
++
++	if (input_fmt->format.code == MEDIA_BUS_FMT_Y8_1X8) {
++		mwidth /= 2; /* (y8 width)/2 = yuv422 width */
++	}
++
++	switch(input_fmt->format.code) {
++		case MEDIA_BUS_FMT_SBGGR8_1X8:
++		case MEDIA_BUS_FMT_SGBRG8_1X8:
++		case MEDIA_BUS_FMT_SGRBG8_1X8:
++		case MEDIA_BUS_FMT_SRGGB8_1X8:
++			vic_reg_writel(vic, VIC_IN_CSI_FMT,MIPI_RAW8);//RAW8
++			vic_reg_writel(vic, MIPI_ALL_WIDTH_4BYTE, ((mwidth * 8 / 32) + !!(mwidth * 8 % 32)));
++			break;
++		case    MEDIA_BUS_FMT_SBGGR10_1X10:
++		case    MEDIA_BUS_FMT_SGBRG10_1X10:
++		case    MEDIA_BUS_FMT_SGRBG10_1X10:
++		case    MEDIA_BUS_FMT_SRGGB10_1X10:
++			vic_reg_writel(vic, VIC_IN_CSI_FMT,MIPI_RAW10);//RAW10
++			vic_reg_writel(vic, MIPI_ALL_WIDTH_4BYTE, ((mwidth * 10 / 32) + !!(mwidth * 10 % 32)));
++			break;
++		case    MEDIA_BUS_FMT_SBGGR12_1X12:
++		case    MEDIA_BUS_FMT_SGBRG12_1X12:
++		case    MEDIA_BUS_FMT_SGRBG12_1X12:
++		case    MEDIA_BUS_FMT_SRGGB12_1X12:
++			vic_reg_writel(vic, VIC_IN_CSI_FMT,MIPI_RAW12);//RAW12
++			vic_reg_writel(vic, MIPI_ALL_WIDTH_4BYTE, ((mwidth * 12 / 32) + !!(mwidth * 12 % 32)));
++			break;
++		case MEDIA_BUS_FMT_Y8_1X8 :
++		case MEDIA_BUS_FMT_YUYV8_2X8 :
++		case MEDIA_BUS_FMT_YVYU8_2X8 :
++		case MEDIA_BUS_FMT_UYVY8_2X8 :
++		case MEDIA_BUS_FMT_VYUY8_2X8 :
++			vic_reg_writel(vic, VIC_IN_CSI_FMT, MIPI_YUV422);//YUV422
++			vic_reg_writel(vic, MIPI_ALL_WIDTH_4BYTE, ((mwidth * 8 / 32) + !!(mwidth * 8 % 32)));
++			break;
++		default:
++			dev_err(vic->dev, "unsupported mbus fmt: %x\n", input_fmt->format.code);
++			return -EINVAL;
++	}
++	vic_reg_writel(vic, MIPI_VCROP_DEL01,  mipi_cfg->mipi_crop_start0y);
++	vic_reg_writel(vic, MIPI_HCROP_CH0, (mwidth << 16) | mipi_cfg->mipi_crop_start0x);
++
++	return 0;
++}
++
++static int vic_cfg_stream_dvp(struct vic_device *vic)
++{
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	struct v4l2_fwnode_bus_parallel *parallel = ispcam_get_bus_parallel(vic->ispcam);
++	unsigned int input_cfg = 0;
++	int width = input_fmt->format.width;
++
++	if (input_fmt->format.code == MEDIA_BUS_FMT_Y8_1X8) {
++		width /= 2; /* (y8 width)/2 = yuv422 width */
++	}
++
++	vic->frame_capture_counter = 0; /* reset counter */
++	vic->global_reset = 0;
++
++	dev_dbg(vic->dev, "parallel->flags: 0x%x\n", parallel->flags);
++	dev_dbg(vic->dev, "parallel->bus_width: %d\n", parallel->bus_width);
++	dev_dbg(vic->dev, "parallel->data_shift: %d\n", parallel->data_shift);
++	vic_reg_writel(vic, VIC_INTF_TYPE, INTF_TYPE_DVP);
++	switch(input_fmt->format.code) {
++		case MEDIA_BUS_FMT_SBGGR8_1X8:
++		case MEDIA_BUS_FMT_SGBRG8_1X8:
++		case MEDIA_BUS_FMT_SGRBG8_1X8:
++		case MEDIA_BUS_FMT_SRGGB8_1X8:
++			if(parallel->data_shift) {
++				input_cfg = DVP_RAW8 | DVP_RAW_ALIG;
++			} else {
++				input_cfg = DVP_RAW8;
++			}
++			break;
++		case MEDIA_BUS_FMT_SBGGR10_1X10:
++		case MEDIA_BUS_FMT_SGBRG10_1X10:
++		case MEDIA_BUS_FMT_SGRBG10_1X10:
++		case MEDIA_BUS_FMT_SRGGB10_1X10:
++			if(parallel->data_shift) {
++				input_cfg = DVP_RAW10 | DVP_RAW_ALIG;
++			} else {
++				input_cfg = DVP_RAW10;
++			}
++			break;
++		case MEDIA_BUS_FMT_SBGGR12_1X12:
++		case MEDIA_BUS_FMT_SGBRG12_1X12:
++		case MEDIA_BUS_FMT_SGRBG12_1X12:
++		case MEDIA_BUS_FMT_SRGGB12_1X12:
++			input_cfg = DVP_RAW12;
++			break;
++		case MEDIA_BUS_FMT_UYVY8_1_5X8 :
++		case MEDIA_BUS_FMT_VYUY8_1_5X8 :
++		case MEDIA_BUS_FMT_YUYV8_1_5X8 :
++		case MEDIA_BUS_FMT_YVYU8_1_5X8 :
++		case MEDIA_BUS_FMT_YUYV8_1X16 :
++		case MEDIA_BUS_FMT_YUYV8_2X8 :
++		case MEDIA_BUS_FMT_YVYU8_2X8 :
++		case MEDIA_BUS_FMT_UYVY8_2X8 :
++		case MEDIA_BUS_FMT_VYUY8_2X8 :
++		case MEDIA_BUS_FMT_Y8_1X8 :
++			input_cfg = DVP_YUV422_8BIT;
++			break;
++
++		default:
++			dev_err(vic->dev, "unsupported input formats\n");
++			return -EINVAL;
++	}
++	if(parallel->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) {
++		input_cfg |= HSYN_POLAR;
++	}
++	if(parallel->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) {
++		input_cfg |= VSYN_POLAR;
++	}
++	vic_reg_writel(vic, VIC_IN_DVP, input_cfg);
++	/*dev_info(vic->dev, "VIC_IN_DVP	input_cfg=0x%x\n", input_cfg);
++	if (input_fmt->format.width>2048 && input_fmt->format.height == 1) {
++		vic_reg_writel(vic, VIC_IN_DVP, 0x6<<17 | 1<<1 | 1<<0);    //cisadc, 0x6<<17 | 1<<1 | 1<<0;
++	}*/
++	/*TODO: hblank and vblank*/
++
++	vic_reg_writel(vic, VIC_IN_HOR_PARA0, width + 0 /*hblank*/);
++
++	return 0;
++}
++
++static int vic_subdev_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct vic_device *vic = v4l2_get_subdevdata(sd);
++	struct isp_async_device *isd = &vic->ispcam->isd[0];	/*TODO: 默认支�一个asd.*/
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	struct isp_video_device *ispvideo = v4l2_get_subdev_hostdata(sd);
++	struct isp_video_buffer *isp_buffer = NULL;
++	struct isp_video_buffer *tmp = NULL;
++	int ret = 0;
++	unsigned long flags;
++	int width;
++	unsigned int regval;
++
++	spin_lock_irqsave(&vic->lock, flags);
++	/*hw configure.*/
++	if(enable) {
++
++		if(vic->enabled++ > 0) {
++			goto finish;
++		}
++
++		/* set width */
++		switch(input_fmt->format.code) {
++		case MEDIA_BUS_FMT_Y8_1X8 :
++			width = input_fmt->format.width/2; /* (y8 width)/2 = yuv422 width */
++			break;
++			/* TODO: NV21/NV12 */
++		default:
++			width = input_fmt->format.width;
++		}
++
++		/* enable timestamp .*/
++		if(timestamp_en) {
++			vic_reg_writel(vic, VIC_TS_COUNTER, count_period - 1);
++			vic_reg_writel(vic, VIC_TS_DMA_OFFSET, 0);
++			vic_reg_writel(vic, VIC_TS_MS_CH0_OFFSET, 0);
++			vic_reg_writel(vic, VIC_TS_MS_CH1_OFFSET, 0);
++			vic_reg_writel(vic, VIC_TS_MS_CH2_OFFSET, 0);
++			vic_reg_writel(vic, VIC_TS_ENABLE, TS_COUNTER_EN |
++					TS_VIC_DMA_EN | TS_MS_CH0_EN |
++					TS_MS_CH1_EN | TS_MS_CH2_EN);
++		}
++
++		/*confgure hw and start*/
++		if(isd->bus_type == V4L2_MBUS_CSI2_DPHY) {
++			ret = vic_cfg_stream_mipi(vic);
++		} else {
++			ret = vic_cfg_stream_dvp(vic);
++		}
++
++		vic_reg_writel(vic, VIC_RESOLUTION, (width << 16) |
++				input_fmt->format.height);
++
++		vic_reg_writel(vic, VIC_CONTROL_DELAY, (10 << 0| 10 << 16));
++
++		if(ispvideo->bypass == 1) {
++			if(dma_debug_en) {
++				printk("please disable vic dma debug mode\ntry \"echo 0 > /sys/module/vic/parameters/dma_debug_en\"\n");
++				goto finish;
++			}
++			/*DMA config*/
++			regval = 0;
++			/*TODO: fmts.*/
++			switch(input_fmt->format.code) {
++			case MEDIA_BUS_FMT_UYVY8_1_5X8 :
++			case MEDIA_BUS_FMT_VYUY8_1_5X8 :
++			case MEDIA_BUS_FMT_YUYV8_1_5X8 :
++			case MEDIA_BUS_FMT_YVYU8_1_5X8 :
++			case MEDIA_BUS_FMT_YUYV8_1X16 :
++			case MEDIA_BUS_FMT_YUYV8_2X8 :
++				regval |= 1<<8; /* Y1UY2V */
++				regval |= 3<<0; /* mode 3: YUV422 */
++				break;
++			case MEDIA_BUS_FMT_YVYU8_2X8 :
++				regval |= 0<<8; /* Y2VY1U */
++				regval |= 3<<0; /* mode 3: YUV422 */
++				break;
++			case MEDIA_BUS_FMT_UYVY8_2X8 :
++				regval |= 3<<8; /* UY1VY2 */
++				regval |= 3<<0; /* mode 3: YUV422 */
++				break;
++			case MEDIA_BUS_FMT_VYUY8_2X8 :
++				regval |= 2<<8; /* VY2UY1 */
++				regval |= 3<<0; /* mode 3: YUV422 */
++				break;
++			case MEDIA_BUS_FMT_Y8_1X8 :
++				//regval |= 0<<8; /* Y2VY1U */
++				//regval |= 1<<8; /* Y1UY2V */
++				//regval |= 2<<8; /* VY2UY1 */
++				//regval |= 3<<8; /* Y1UY2V(U1Y1V1Y2) */
++				regval |= 3<<0; /* mode 3: YUV422 */
++				break;
++				/* TODO: NV21/NV12 */
++			case MEDIA_BUS_FMT_SBGGR8_1X8:
++			case MEDIA_BUS_FMT_SGBRG8_1X8:
++			case MEDIA_BUS_FMT_SGRBG8_1X8:
++			case MEDIA_BUS_FMT_SRGGB8_1X8:
++			case MEDIA_BUS_FMT_SBGGR10_1X10:
++			case MEDIA_BUS_FMT_SGBRG10_1X10:
++			case MEDIA_BUS_FMT_SGRBG10_1X10:
++			case MEDIA_BUS_FMT_SRGGB10_1X10:
++			case MEDIA_BUS_FMT_SBGGR12_1X12:
++			case MEDIA_BUS_FMT_SGBRG12_1X12:
++			case MEDIA_BUS_FMT_SGRBG12_1X12:
++			case MEDIA_BUS_FMT_SRGGB12_1X12:
++				regval |= 0;
++				break;
++			default:
++				dev_info(vic->dev, "%s(), TODO: DMA config, input_fmt->format.code=0x%x\n",
++					 __func__, input_fmt->format.code);
++				return -EINVAL;
++			}
++			regval |= 1 << 31; /* enable dma */
++			regval |= (ispvideo->max_buffer_num - 1) << 3;
++			vic_reg_writel(vic, VIC_DMA_CONFIG, regval);
++
++			vic_reg_writel(vic, VIC_DMA_RESOLUTION, (width << 16) |
++				       input_fmt->format.height);
++			vic_reg_writel(vic, VIC_DMA_Y_STRID, width*2);
++			vic_reg_writel(vic, VIC_DMA_UV_STRID, width*2);
++
++			vic_reg_writel(vic, VIC_CONTROL_TIZIANO_ROUTE, 0);
++			vic_reg_writel(vic, VIC_CONTROL_DMA_ROUTE, 1);
++			/*TODO:*/
++			vic_reg_writel(vic, VIC_INT_MASK, 0x3ff7f);
++			if(input_fmt->format.width > 2048) {
++				if(input_fmt->format.height > 1)
++					vic_reg_writel(vic, VIC_CONTROL_LIMIT, (1 << 31)|((input_fmt->format.width / 8 * 3) << 16));
++				else
++					vic_reg_writel(vic, VIC_CONTROL_LIMIT, (1 << 31)|(512<<16)); // cisadc, height==1, width > 2048
++			}
++			vic->framenum = 0;
++
++		} else {
++			vic_reg_writel(vic, VIC_CONTROL_TIZIANO_ROUTE, 1);
++			if(dma_debug_en)
++				vic_reg_writel(vic, VIC_CONTROL_DMA_ROUTE, 1);
++			else
++				vic_reg_writel(vic, VIC_CONTROL_DMA_ROUTE, 0);
++			vic_reg_writel(vic, VIC_INT_MASK, 0x3ff7f);
++		}
++
++		vic_reg_writel(vic, VIC_CONTROL, ~GLB_RST);
++		vic_reg_writel(vic, VIC_CONTROL, REG_ENABLE);
++#if 0
++		unsigned int timeout  = 0xfffff;
++		while(vic_reg_readl(vic,VIC_CONTROL) && --timeout);
++		if(!timeout) {
++			dev_err(vic->dev, "wait vic init timeout!\n");
++		}
++#endif
++
++		vic_reg_writel(vic, VIC_CONTROL, VIC_START);
++
++
++	} else {
++		/*reset flags*/
++		vic->buffer_index = 0;
++		vic->stop_flag = 0;
++		vic_stop_counter = 0;
++
++		if(--vic->enabled) {
++			goto finish;
++		}
++
++		/* disable timestamp */
++		vic_reg_writel(vic, VIC_TS_COUNTER, 0);
++		vic_reg_writel(vic, VIC_TS_ENABLE, 0);
++
++		if(ispvideo->bypass) {
++			/*disable dma*/
++			vic_reg_writel(vic, VIC_DMA_CONFIG, 0);
++			/*disable contro limit*/
++			if(input_fmt->format.width > 2048)
++				vic_reg_writel(vic, VIC_CONTROL_LIMIT, 0);
++		}
++
++		/* keep reset*/
++		vic_reg_writel(vic, VIC_CONTROL, GLB_RST);
++
++		/* stop vic. */
++		list_for_each_entry_safe(isp_buffer, tmp, &vic->dma_queued_list, list_entry) {
++			struct vb2_buffer *vb2_buf = &isp_buffer->vb2.vb2_buf;
++			vb2_buffer_done(vb2_buf, VB2_BUF_STATE_ERROR);
++			list_del(&isp_buffer->list_entry);
++			vic->buffer_count--;
++		}
++
++	}
++
++finish:
++	spin_unlock_irqrestore(&vic->lock, flags);
++
++	return ret;
++}
++
++
++static const struct v4l2_subdev_video_ops vic_subdev_video_ops = {
++        .s_stream = vic_subdev_s_stream,
++};
++static const struct v4l2_subdev_ops vic_subdev_ops = {
++        .core = &vic_subdev_core_ops,
++        .pad = &vic_subdev_pad_ops,
++        .video = &vic_subdev_video_ops,
++};
++
++struct isp_video_format *vic_find_format(const u32 *pixelformat, const u32 *mbus_code, int index)
++{
++	int i;
++	struct isp_video_format *fmt = NULL;
++
++	for(i = 0; i < ARRAY_SIZE(vic_mipi_formats); i++) {
++		fmt = &vic_mipi_formats[i];
++
++		if(pixelformat && fmt->fourcc == *pixelformat) {
++			return fmt;
++		}
++		if(mbus_code && fmt->mbus_code == *mbus_code) {
++			return fmt;
++		}
++
++		if(index == i) {
++			return fmt;
++		}
++	}
++
++	return NULL;
++}
++
++static int vic_video_qbuf(struct isp_video_device *ispvideo, struct isp_video_buffer *isp_buffer)
++{
++	struct vic_device *vic = ispvideo->ispcam->vic;
++	struct vb2_buffer *vb2_buf = NULL;
++	struct isp_video_buffer *tmp = NULL;
++	unsigned long flags = 0;
++	dma_addr_t y_addr = 0;
++	dma_addr_t uv_addr = 0;
++	unsigned int regval;
++
++	spin_lock_irqsave(&vic->lock, flags);
++
++	vb2_buf = &isp_buffer->vb2.vb2_buf;
++
++	list_add_tail(&isp_buffer->list_entry, &vic->dma_queued_list);
++	vic->buffer_count++;
++
++
++	/*Y*/
++	y_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 0);
++	vic_reg_writel(vic, VIC_DMA_Y_BUF0 + vic->buffer_index * 4, y_addr);
++
++	uv_addr = y_addr + isp_buffer->uv_offset;
++	/*UV*/
++	if(vb2_buf->num_planes == 2) {
++		uv_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 1);
++	}
++	vic_reg_writel(vic, VIC_DMA_UV_BUF0 + vic->buffer_index * 4, uv_addr);
++
++	vic->buffer_index++;
++	vic->buffer_index %= ispvideo->max_buffer_num;
++
++	if(vic->buffer_count >= VIC_RESTART_BUFFER_COUNT && vic->stop_flag)
++	{
++		/*reset flags*/
++		vic->stop_flag = 0;
++		vic->buffer_index = 0;
++
++		/*buffers in the list refill in register*/
++		list_for_each_entry_safe(isp_buffer, tmp, &vic->dma_queued_list, list_entry) {
++
++			vb2_buf = &isp_buffer->vb2.vb2_buf;
++			/*Y*/
++			y_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 0);
++			vic_reg_writel(vic, VIC_DMA_Y_BUF0 + vic->buffer_index * 4, y_addr);
++
++			uv_addr = y_addr + isp_buffer->uv_offset;
++			/*UV*/
++			if(vb2_buf->num_planes == 2) {
++				uv_addr = ingenic_vb2_dma_contig_plane_dma_addr(vb2_buf, 1);
++			}
++			vic_reg_writel(vic, VIC_DMA_UV_BUF0 + vic->buffer_index * 4, uv_addr);
++
++			vic->buffer_index++;
++			vic->buffer_index %= ispvideo->max_buffer_num;
++
++		}
++		/*restart*/
++		regval = vic_reg_readl(vic, VIC_DMA_CONFIG);
++		vic_reg_writel(vic, VIC_DMA_RESET, 1);
++		vic_reg_writel(vic, VIC_DMA_RESET, 0);
++		regval |= 1 << 31; /* enable dma */
++		regval &= ~(0xf<<3); /* reset dma buffer num */
++		regval |= (ispvideo->max_buffer_num - 1) << 3;
++		vic_reg_writel(vic, VIC_DMA_CONFIG, regval);
++		/* lgwang, re-start vic */
++		if (vic->global_reset) {
++			vic_reg_writel(vic, VIC_CONTROL, 0x1);
++			vic->global_reset = 0;
++		}
++		goto done;
++	}
++
++done:
++	spin_unlock_irqrestore(&vic->lock, flags);
++
++	return 0;
++}
++
++static const struct isp_video_ops vic_video_ops = {
++	.find_format 	= vic_find_format,
++	.qbuf		= vic_video_qbuf,
++};
++
++static ssize_t
++dump_vic(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct vic_device *vic = dev_get_drvdata(dev);
++	char *p = buf;
++
++	p += sprintf(p, "VIC_CONTROL			:0x%08x\n", vic_reg_readl(vic, VIC_CONTROL));
++	p += sprintf(p, "VIC_RESOLUTION                 :0x%08x\n", vic_reg_readl(vic, VIC_RESOLUTION));
++	p += sprintf(p, "VIC_FRM_ECC                    :0x%08x\n", vic_reg_readl(vic, VIC_FRM_ECC));
++	p += sprintf(p, "VIC_INTF_TYPE                  :0x%08x\n", vic_reg_readl(vic, VIC_INTF_TYPE));
++	p += sprintf(p, "VIC_IN_DVP                     :0x%08x\n", vic_reg_readl(vic, VIC_IN_DVP));
++	p += sprintf(p, "VIC_IN_CSI_FMT                 :0x%08x\n", vic_reg_readl(vic, VIC_IN_CSI_FMT));
++	p += sprintf(p, "VIC_IN_HOR_PARA0               :0x%08x\n", vic_reg_readl(vic, VIC_IN_HOR_PARA0));
++	p += sprintf(p, "VIC_IN_HOR_PARA1               :0x%08x\n", vic_reg_readl(vic, VIC_IN_HOR_PARA1));
++	p += sprintf(p, "VIC_BK_CB_CTRL                 :0x%08x\n", vic_reg_readl(vic, VIC_BK_CB_CTRL));
++	p += sprintf(p, "VIC_BK_CB_BLK                  :0x%08x\n", vic_reg_readl(vic, VIC_BK_CB_BLK));
++	p += sprintf(p, "VIC_IN_VER_PARA0               :0x%08x\n", vic_reg_readl(vic, VIC_IN_VER_PARA0));
++	p += sprintf(p, "VIC_IN_VER_PARA1               :0x%08x\n", vic_reg_readl(vic, VIC_IN_VER_PARA1));
++	p += sprintf(p, "VIC_IN_VER_PARA2               :0x%08x\n", vic_reg_readl(vic, VIC_IN_VER_PARA2));
++	p += sprintf(p, "VIC_IN_VER_PARA3               :0x%08x\n", vic_reg_readl(vic, VIC_IN_VER_PARA3));
++	p += sprintf(p, "VIC_VLD_LINE_SAV               :0x%08x\n", vic_reg_readl(vic, VIC_VLD_LINE_SAV));
++	p += sprintf(p, "VIC_VLD_LINE_EAV               :0x%08x\n", vic_reg_readl(vic, VIC_VLD_LINE_EAV));
++	p += sprintf(p, "VIC_VLD_FRM_SAV                :0x%08x\n", vic_reg_readl(vic, VIC_VLD_FRM_SAV));
++	p += sprintf(p, "VIC_VLD_FRM_EAV                :0x%08x\n", vic_reg_readl(vic, VIC_VLD_FRM_EAV));
++	p += sprintf(p, "VIC_VC_CONTROL                 :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL));
++	p += sprintf(p, "VIC_VC_CONTROL_CH0_PIX         :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_CH0_PIX));
++	p += sprintf(p, "VIC_VC_CONTROL_CH1_PIX         :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_CH1_PIX));
++	p += sprintf(p, "VIC_VC_CONTROL_CH2_PIX         :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_CH2_PIX));
++	p += sprintf(p, "VIC_VC_CONTROL_CH3_PIX         :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_CH3_PIX));
++	p += sprintf(p, "VIC_VC_CONTROL_CH0_LINE        :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_CH0_LINE));
++	p += sprintf(p, "VIC_VC_CONTROL_CH1_LINE        :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_CH1_LINE));
++	p += sprintf(p, "VIC_VC_CONTROL_CH2_LINE        :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_CH2_LINE));
++	p += sprintf(p, "VIC_VC_CONTROL_CH3_LINE        :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_CH3_LINE));
++	p += sprintf(p, "VIC_VC_CONTROL_FIFO_USE        :0x%08x\n", vic_reg_readl(vic, VIC_VC_CONTROL_FIFO_USE));
++	p += sprintf(p, "VIC_CB_1ST                     :0x%08x\n", vic_reg_readl(vic, VIC_CB_1ST));
++	p += sprintf(p, "VIC_CB_2ND                     :0x%08x\n", vic_reg_readl(vic, VIC_CB_2ND));
++	p += sprintf(p, "VIC_CB_3RD                     :0x%08x\n", vic_reg_readl(vic, VIC_CB_3RD));
++	p += sprintf(p, "VIC_CB_4TH                     :0x%08x\n", vic_reg_readl(vic, VIC_CB_4TH));
++	p += sprintf(p, "VIC_CB_5TH                     :0x%08x\n", vic_reg_readl(vic, VIC_CB_5TH));
++	p += sprintf(p, "VIC_CB_6TH                     :0x%08x\n", vic_reg_readl(vic, VIC_CB_6TH));
++	p += sprintf(p, "VIC_CB_7TH                     :0x%08x\n", vic_reg_readl(vic, VIC_CB_7TH));
++	p += sprintf(p, "VIC_CB_8TH                     :0x%08x\n", vic_reg_readl(vic, VIC_CB_8TH));
++	p += sprintf(p, "VIC_CB2_1ST                    :0x%08x\n", vic_reg_readl(vic, VIC_CB2_1ST));
++	p += sprintf(p, "VIC_CB2_2ND                    :0x%08x\n", vic_reg_readl(vic, VIC_CB2_2ND));
++	p += sprintf(p, "VIC_CB2_3RD                    :0x%08x\n", vic_reg_readl(vic, VIC_CB2_3RD));
++	p += sprintf(p, "VIC_CB2_4TH                    :0x%08x\n", vic_reg_readl(vic, VIC_CB2_4TH));
++	p += sprintf(p, "VIC_CB2_5TH                    :0x%08x\n", vic_reg_readl(vic, VIC_CB2_5TH));
++	p += sprintf(p, "VIC_CB2_6TH                    :0x%08x\n", vic_reg_readl(vic, VIC_CB2_6TH));
++	p += sprintf(p, "VIC_CB2_7TH                    :0x%08x\n", vic_reg_readl(vic, VIC_CB2_7TH));
++	p += sprintf(p, "VIC_CB2_8TH                    :0x%08x\n", vic_reg_readl(vic, VIC_CB2_8TH));
++	p += sprintf(p, "MIPI_ALL_WIDTH_4BYTE           :0x%08x\n", vic_reg_readl(vic, MIPI_ALL_WIDTH_4BYTE));
++	p += sprintf(p, "MIPI_VCROP_DEL01               :0x%08x\n", vic_reg_readl(vic, MIPI_VCROP_DEL01));
++	p += sprintf(p, "MIPI_SENSOR_CONTROL            :0x%08x\n", vic_reg_readl(vic, MIPI_SENSOR_CONTROL));
++	p += sprintf(p, "MIPI_HCROP_CH0                 :0x%08x\n", vic_reg_readl(vic, MIPI_HCROP_CH0));
++	p += sprintf(p, "MIPI_VCROP_SHADOW_CFG          :0x%08x\n", vic_reg_readl(vic, MIPI_VCROP_SHADOW_CFG));
++	p += sprintf(p, "VIC_CONTROL_LIMIT              :0x%08x\n", vic_reg_readl(vic, VIC_CONTROL_LIMIT));
++	p += sprintf(p, "VIC_CONTROL_DELAY              :0x%08x\n", vic_reg_readl(vic, VIC_CONTROL_DELAY));
++	p += sprintf(p, "VIC_CONTROL_TIZIANO_ROUTE      :0x%08x\n", vic_reg_readl(vic, VIC_CONTROL_TIZIANO_ROUTE));
++	p += sprintf(p, "VIC_CONTROL_DMA_ROUTE          :0x%08x\n", vic_reg_readl(vic, VIC_CONTROL_DMA_ROUTE));
++	p += sprintf(p, "VIC_INT_STA                    :0x%08x\n", vic_reg_readl(vic, VIC_INT_STA));
++	p += sprintf(p, "VIC_INT_MASK                   :0x%08x\n", vic_reg_readl(vic, VIC_INT_MASK));
++	p += sprintf(p, "VIC_INT_CLR                    :0x%08x\n", vic_reg_readl(vic, VIC_INT_CLR));
++	p += sprintf(p, "VIC_DMA_CONFIG        :0x%08x\n", vic_reg_readl(vic, VIC_DMA_CONFIG));
++	p += sprintf(p, "VIC_DMA_RESOLUTION    :0x%08x\n", vic_reg_readl(vic, VIC_DMA_RESOLUTION));
++	p += sprintf(p, "VIC_DMA_RESET         :0x%08x\n", vic_reg_readl(vic, VIC_DMA_RESET));
++	p += sprintf(p, "VIC_DMA_Y_STRID       :0x%08x\n", vic_reg_readl(vic, VIC_DMA_Y_STRID));
++	p += sprintf(p, "VIC_DMA_Y_BUF0        :0x%08x\n", vic_reg_readl(vic, VIC_DMA_Y_BUF0));
++	p += sprintf(p, "VIC_DMA_Y_BUF1        :0x%08x\n", vic_reg_readl(vic, VIC_DMA_Y_BUF1));
++	p += sprintf(p, "VIC_DMA_Y_BUF2        :0x%08x\n", vic_reg_readl(vic, VIC_DMA_Y_BUF2));
++	p += sprintf(p, "VIC_DMA_Y_BUF3        :0x%08x\n", vic_reg_readl(vic, VIC_DMA_Y_BUF3));
++	p += sprintf(p, "VIC_DMA_Y_BUF4        :0x%08x\n", vic_reg_readl(vic, VIC_DMA_Y_BUF4));
++	p += sprintf(p, "VIC_DMA_UV_STRID      :0x%08x\n", vic_reg_readl(vic, VIC_DMA_UV_STRID));
++	p += sprintf(p, "VIC_DMA_UV_BUF0       :0x%08x\n", vic_reg_readl(vic, VIC_DMA_UV_BUF0));
++	p += sprintf(p, "VIC_DMA_UV_BUF1       :0x%08x\n", vic_reg_readl(vic, VIC_DMA_UV_BUF1));
++	p += sprintf(p, "VIC_DMA_UV_BUF2       :0x%08x\n", vic_reg_readl(vic, VIC_DMA_UV_BUF2));
++	p += sprintf(p, "VIC_DMA_UV_BUF3       :0x%08x\n", vic_reg_readl(vic, VIC_DMA_UV_BUF3));
++	p += sprintf(p, "VIC_DMA_UV_BUF4       :0x%08x\n", vic_reg_readl(vic, VIC_DMA_UV_BUF4));
++
++
++
++	return p - buf;
++}
++
++ssize_t vic_dma_debug(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct vic_device *vic = dev_get_drvdata(dev);
++	struct v4l2_subdev_format *input_fmt = &vic->formats[VIC_PAD_SINK];
++	unsigned int imagesize = 0;
++	unsigned int lineoffset = 0;
++	int loop = 100;
++	struct file *fd = NULL;
++	mm_segment_t old_fs;
++	loff_t *pos;
++	int ret = 0;
++
++	if (!strncmp(buf, "snapraw", sizeof("snapraw")-1)) {
++		if(!dma_debug_en) {
++			printk("please enable vic dma debug mode\ntry \"echo 1 > /sys/module/vic/parameters/dma_debug_en\"\n");
++			return -EINVAL;
++		}
++
++		lineoffset = input_fmt->format.width * 2;
++		imagesize = lineoffset * input_fmt->format.height;
++		dev_info(vic->dev, "width is %d,height is %d,imagesize is %d\n",input_fmt->format.width,input_fmt->format.height,imagesize);
++		if(input_fmt->format.width > VIC_DMA_OUTPUT_MAX_WIDTH){
++			return -EINVAL;
++		}
++		if(vic->snap_paddr){
++			return -EBUSY;
++		}
++
++		vic->snap_vaddr = kmalloc(imagesize, GFP_KERNEL);
++		if(vic->snap_vaddr){
++			vic->snap_paddr = virt_to_phys((void *)vic->snap_vaddr);
++			vic_reg_writel(vic, VIC_DMA_RESET, 0x01);
++			vic_reg_writel(vic, VIC_DMA_RESOLUTION, input_fmt->format.width << 16 | input_fmt->format.height);
++			vic_reg_writel(vic, VIC_DMA_Y_STRID, lineoffset);
++			vic_reg_writel(vic, VIC_DMA_Y_BUF0, vic->snap_paddr);
++			vic_reg_writel(vic, VIC_DMA_CONFIG, 0x1<<31);
++			while(loop){
++				ret = wait_for_completion_interruptible(&vic->snap_comp);
++				if (ret >= 0)
++					break;
++				loop--;
++			}
++			if(!loop){
++				dev_err(vic->dev, "snapraw timeout!\n");
++				goto exit;
++			}
++			/* save raw */
++			fd = filp_open("/tmp/snap.raw", O_CREAT | O_WRONLY | O_TRUNC, 00766);
++			if (fd < 0) {
++				dev_err(vic->dev, "Failed to open /tmp/snap.raw\n");
++				goto exit;
++			}
++
++			/* write file */
++			old_fs = get_fs();
++			set_fs(KERNEL_DS);
++			pos = &(fd->f_pos);
++			vfs_write(fd, vic->snap_vaddr, imagesize, pos);
++			filp_close(fd, NULL);
++			set_fs(old_fs);
++		}
++	}
++
++exit:
++	kfree(vic->snap_vaddr);
++	vic->snap_paddr = 0;
++
++	return count;
++}
++
++static DEVICE_ATTR(dump_vic, S_IRUGO|S_IWUSR, dump_vic, NULL);
++static DEVICE_ATTR(vic_dma_debug, S_IRUGO|S_IWUSR, NULL, vic_dma_debug);
++
++static struct attribute *vic_debug_attrs[] = {
++        &dev_attr_dump_vic.attr,
++#ifdef CONFIG_VIC_DMA_ROUTE
++	&dev_attr_vic_dma_debug.attr,
++#endif
++	NULL,
++};
++
++static struct attribute_group vic_debug_attr_group = {
++        .name   = "debug",
++        .attrs  = vic_debug_attrs,
++};
++
++int bypass_video_g_ctrl(struct file *file, void *fh, struct v4l2_control *a)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct isp_device 	*isp	= ispcam->isp;
++	struct sensor_device *sensor = &isp->ispcam->sensor;
++	int ret = 0;
++
++	ret = v4l2_g_ctrl(sensor->isd->sd->ctrl_handler,a);
++	if(ret < 0) {
++		dev_err(isp->dev, "failed to get ID:%d!\n", a->id);
++	}
++	return ret;
++}
++
++int bypass_video_s_ctrl(struct file *file, void *fh, struct v4l2_control *a)
++{
++	struct isp_video_device *ispvideo = video_drvdata(file);
++	struct ispcam_device 	*ispcam = ispvideo->ispcam;
++	struct isp_device 	*isp	= ispcam->isp;
++	struct sensor_device *sensor = &isp->ispcam->sensor;
++	int ret = 0;
++
++	ret = v4l2_s_ctrl(NULL,sensor->isd->sd->ctrl_handler,a);
++	if(ret < 0) {
++		dev_err(isp->dev, "failed to set ID:%d!\n", a->id);
++	}
++	return ret;
++}
++
++int vic_video_nr_map[2] = {
++	INGENIC_VIC0_VIDEO_NR,
++	INGENIC_VIC1_VIDEO_NR,
++};
++
++static int vic_comp_bind(struct device *comp, struct device *master,
++                              void *master_data)
++{
++	struct vic_device *vic = dev_get_drvdata(comp);
++	struct ispcam_device *ispcam = (struct ispcam_device *)master_data;
++	struct v4l2_device *v4l2_dev = &ispcam->v4l2_dev;
++	struct v4l2_subdev *sd = &vic->sd;
++	int ret = 0;
++	int nr = vic_video_nr_map[ispcam->dev_nr];
++	struct isp_video_device *ispvideo = &vic->ispvideo;
++	char name[32];
++
++	//dev_info(comp, "--------%s, %d \n", __func__, __LINE__);
++	/* link subdev to master.*/
++	vic->ispcam = (void *)ispcam;
++	ispcam->vic = vic;
++
++	v4l2_subdev_init(sd, &vic_subdev_ops);
++
++
++	sd->owner = THIS_MODULE;
++	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++	strscpy(sd->name, dev_name(comp), sizeof(sd->name));
++	v4l2_set_subdevdata(sd, vic);
++
++	/* init vic pads. */
++	vic->pads = kzalloc(sizeof(struct media_pad) * VIC_NUM_PADS, GFP_KERNEL);
++	if(!vic->pads) {
++		ret = -ENOMEM;
++		goto err_alloc_pads;
++	}
++	vic->pads[0].index = VIC_PAD_SINK;
++	vic->pads[0].flags = MEDIA_PAD_FL_SINK;	/* CSI->VIC, MIPI Interface*/
++	vic->pads[1].index = VIC_PAD_SOURCE;
++	vic->pads[1].flags = MEDIA_PAD_FL_SOURCE;
++
++	ret = media_entity_pads_init(&sd->entity, VIC_NUM_PADS, vic->pads);
++
++	/*3. register v4l2_subdev*/
++	sd->entity.function = MEDIA_ENT_F_IO_V4L;
++	ret = v4l2_device_register_subdev(v4l2_dev, sd);
++	if(ret < 0) {
++		dev_err(comp, "Failed to register v4l2_subdev for vic\n");
++		goto err_subdev_register;
++	}
++
++#ifdef CONFIG_VIC_DMA_ROUTE
++	init_completion(&vic->snap_comp);
++
++	ispvideo->ispcam = ispcam;
++	ispvideo->bypass = 1;
++	sprintf(name, "%s", dev_name(vic->dev));
++	ispvideo->video.v4l2_dev = &ispcam->v4l2_dev;
++	ret = isp_video_init(ispvideo, name, &vic_video_ops);
++	if(ret < 0) {
++		/*TODO:*/
++
++	}
++
++	ret = isp_video_register(ispvideo, &ispcam->v4l2_dev, nr);
++	if(ret < 0) {
++		/*TODO:*/
++	};
++#endif
++
++err_subdev_register:
++err_alloc_pads:
++
++
++	return ret;
++}
++
++
++static void vic_comp_unbind(struct device *comp, struct device *master,
++                                 void *master_data)
++{
++        struct vic_device *vic = dev_get_drvdata(comp);
++
++	dev_info(comp, "---TODO: %p-----%s, %d \n", vic, __func__, __LINE__);
++
++}
++
++static const struct component_ops vic_comp_ops = {
++        .bind = vic_comp_bind,
++        .unbind = vic_comp_unbind,
++};
++
++static irqreturn_t vic_irq_handler(int irq, void *data)
++{
++	struct vic_device *vic = (struct vic_device *)data;
++	unsigned int status = 0;
++	struct isp_video_buffer *isp_buffer = NULL;
++	unsigned int regval;
++
++	spin_lock(&vic->lock);
++	status = vic_reg_readl(vic, VIC_INT_STA);
++	//printk(KERN_DEBUG "VIC_INT_STA=%x\n", status);
++	/* DMA FRAME DONE */
++	if(status & (1 << 7)) {
++		vic->frame_capture_counter++;
++		//printk(KERN_DEBUG "%d: vic->buffer_count=0x%x\n", vic->frame_capture_counter, vic->buffer_count);
++
++#ifdef CONFIG_VIC_DMA_ROUTE
++		if(dma_debug_en){
++			vic_reg_writel(vic, VIC_DMA_CONFIG, 0);
++			complete(&vic->snap_comp);
++		} else {
++			isp_buffer = list_first_entry_or_null(&vic->dma_queued_list, struct isp_video_buffer, list_entry);
++			if(!isp_buffer) {
++				dev_err(vic->dev, "[warning] no isp_buffer found in dma_queued_list when interrupt happend!\n");
++				goto done;
++			}
++
++			list_del(&isp_buffer->list_entry);
++			vic->buffer_count--;
++
++			isp_buffer->vb2.vb2_buf.timestamp = ktime_get_ns();
++			isp_buffer->vb2.sequence = vic->framenum++;
++
++			vb2_buffer_done(&isp_buffer->vb2.vb2_buf, VB2_BUF_STATE_DONE);
++
++			if(vic->buffer_count <= VIC_STOP_BUFFER_COUNT)
++			{
++				vic->stop_flag = 1;
++				regval = vic_reg_readl(vic, VIC_DMA_CONFIG);
++				regval &= ~(1 << 31);
++				vic_reg_writel(vic, VIC_DMA_CONFIG, regval);
++				vic_stop_counter++;
++				goto done;
++			}
++		}
++#endif
++	}
++
++	if(status & (1 << 9)) {
++		//dev_err(vic->dev,
++		printk(KERN_DEBUG "vic->frame_capture_counter=%d, Image output limit too small! VIC_INT_STA=%x\n", vic->frame_capture_counter, status);
++		/* lgwang -- reset vic */
++		vic->global_reset = 1;
++		vic_reg_writel(vic, VIC_CONTROL, 0x4);
++		vic->stop_flag = 1;
++		vic_stop_counter++;
++	}
++
++done:
++	vic_reg_writel(vic, VIC_INT_CLR, status);
++	spin_unlock(&vic->lock);
++	return IRQ_HANDLED;
++
++}
++
++static int ingenic_vic_probe(struct platform_device *pdev)
++{
++
++	struct vic_device *vic = NULL;
++	struct resource *regs = NULL;
++	int ret = 0;
++
++	vic = kzalloc(sizeof(struct vic_device), GFP_KERNEL);
++	if(!vic) {
++		pr_err("Failed to alloc vic dev [%s]\n", pdev->name);
++		return -ENOMEM;
++	}
++
++	vic->dev = &pdev->dev;
++	platform_set_drvdata(pdev, vic);
++
++
++	ingenic_vic_parse_dt(vic);
++
++	vic->irq = platform_get_irq(pdev, 0);
++	if(vic->irq < 0) {
++		dev_warn(&pdev->dev, "No CSI IRQ specified\n");
++	}
++
++	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if(!regs) {
++		dev_err(&pdev->dev, "No iomem resource!\n");
++		goto err_get_resource;
++	}
++
++	vic->iobase = devm_ioremap_resource(&pdev->dev, regs);
++	if(!vic->iobase) {
++		goto err_ioremap;
++	}
++
++	spin_lock_init(&vic->lock);
++	INIT_LIST_HEAD(&vic->dma_queued_list);
++
++	ret = devm_request_irq(vic->dev, vic->irq, vic_irq_handler, 0,
++			dev_name(vic->dev), vic);
++	if(ret) {
++		dev_err(vic->dev, "request irq failed!\n");
++		goto err_request_irq;
++	}
++
++	ret = sysfs_create_group(&vic->dev->kobj, &vic_debug_attr_group);
++	if (ret) {
++		dev_err(vic->dev, "device create sysfs group failed\n");
++
++		ret = -EINVAL;
++		goto err_sys_group;
++	}
++
++	ret = component_add(vic->dev, &vic_comp_ops);
++	if(ret < 0) {
++		dev_err(vic->dev, "Failed to add component vic!\n");
++		goto err_component;
++	}
++
++	return 0;
++err_component:
++err_sys_group:
++err_request_irq:
++err_ioremap:
++err_get_resource:
++	return ret;
++}
++
++
++
++static int ingenic_vic_remove(struct platform_device *pdev)
++{
++
++	return 0;
++}
++
++
++
++static const struct of_device_id ingenic_vic_dt_match[] = {
++        { .compatible = "ingenic,x2000-vic" },
++        { .compatible = "ingenic,m300-vic" },
++        { }
++};
++
++MODULE_DEVICE_TABLE(of, ingenic_vic_dt_match);
++
++static int __maybe_unused ingenic_vic_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	struct vic_device *vic = dev_get_drvdata(&pdev->dev);
++
++	if(vic->enabled){
++		dev_err(vic->dev, "faild to suspend, vic is streaming on\n");
++		return -EBUSY;
++	}
++
++        return 0;
++}
++
++static int __maybe_unused ingenic_vic_resume(struct platform_device *pdev)
++{
++        return 0;
++}
++
++static struct platform_driver ingenic_vic_driver = {
++        .probe = ingenic_vic_probe,
++        .remove = ingenic_vic_remove,
++	.suspend = ingenic_vic_suspend,
++	.resume = ingenic_vic_resume,
++        .driver = {
++                .name = "ingenic-vic",
++                .of_match_table = ingenic_vic_dt_match,
++        },
++};
++
++module_platform_driver(ingenic_vic_driver);
++
++MODULE_ALIAS("platform:ingenic-vic");
++MODULE_DESCRIPTION("ingenic vic subsystem");
++MODULE_AUTHOR("qipengzhen <aric.pzqi@ingenic.com>");
++MODULE_LICENSE("GPL v2");
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-rotate/Kconfig b/module_drivers/drivers/media/platform/ingenic-rotate/Kconfig
+new file mode 100644
+index 000000000..8cc9e556a
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-rotate/Kconfig
+@@ -0,0 +1,8 @@
++config VIDEO_INGENIC_ROTATE
++        depends on VIDEO_DEV && VIDEO_V4L2
++        tristate "Ingenic rotate driver"
++        select VIDEOBUF2_DMA_CONTIG_INGENIC
++        select V4L2_MEM2MEM_DEV
++        help
++          This is a v4l2 driver for Ingenic rotate
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-rotate/Makefile b/module_drivers/drivers/media/platform/ingenic-rotate/Makefile
+new file mode 100644
+index 000000000..1fa30b670
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-rotate/Makefile
+@@ -0,0 +1,2 @@
++ingenic_rotate-y := rotate.o rotate-hw.o
++obj-$(CONFIG_VIDEO_INGENIC_ROTATE) += ingenic_rotate.o
+diff --git a/module_drivers/drivers/media/platform/ingenic-rotate/rotate-hw.c b/module_drivers/drivers/media/platform/ingenic-rotate/rotate-hw.c
+new file mode 100644
+index 000000000..fefc6de7d
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-rotate/rotate-hw.c
+@@ -0,0 +1,317 @@
++/* * drivers/media/platform/ingenic_rotate/rotate-hw.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * Author:clwang<chunlei.wang@ingenic.com>
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/io.h>
++#include <linux/delay.h>
++
++#include "rotate.h"
++#include "rotate-regs.h"
++
++void dump_rot_reg(struct ingenic_rot_dev *dev)
++{
++	printk("-----------------rot_reg------------------\n");
++	printk("ROT_FRM_CFG_ADDR:    0x%lx\n",reg_read(dev, ROT_FRM_CFG_ADDR));
++	printk("ROT_FRM_SIZE:	     0x%lx\n",reg_read(dev, ROT_FRM_SIZE));
++	printk("ROT_GLB_CFG:         0x%lx\n",reg_read(dev, ROT_GLB_CFG));
++	printk("ROT_CTRL:            0x%lx\n",reg_read(dev, ROT_CTRL));
++	printk("ROT_ST:              0x%lx\n",reg_read(dev, ROT_ST));
++	printk("ROT_CLR_ST:          0x%lx\n",reg_read(dev, ROT_CLR_ST));
++	printk("ROT_INT_MASK:        0x%lx\n",reg_read(dev, ROT_INT_MASK));
++	printk("ROT_RDMA_SITE:       0x%lx\n",reg_read(dev, ROT_RDMA_SITE));
++	printk("ROT_WDMA_SITE:       0x%lx\n",reg_read(dev, ROT_WDMA_SITE));
++	printk("ROT_QOS_CTRL:        0x%lx\n",reg_read(dev, ROT_QOS_CTRL));
++	printk("ROT_QOS_CFG:         0x%lx\n",reg_read(dev, ROT_QOS_CFG));
++	printk("-----------------rot_reg------------------\n");
++}
++
++void dump_rot_desc(struct ingenic_rot_desc *desc)
++{
++	printk("-----------------rot_desc------------------\n");
++	printk("rot_des		     0x%x\n",(uint32_t)desc);
++	printk("NextCfgAddr:         0x%x\n",desc->NextCfgAddr);
++	printk("SrcBufferAddr:       0x%x\n",desc->SrcBufferAddr);
++	printk("SrcStride:           0x%x\n",desc->SrcStride);
++	printk("FrameStop:           0x%x\n",desc->FrameStop.d32);
++	printk("TargetBufferAddr:    0x%x\n",desc->TargetBufferAddr);
++	printk("TargetStride:        0x%x\n",desc->TargetStride);
++	printk("irq_ctrl:            0x%x\n",desc->irq_ctrl.d32);
++	printk("-----------------rot_desc------------------\n");
++}
++
++void dump_rot_desc_reg(struct ingenic_rot_dev *dev)
++{
++	reg_write(dev, ROT_CTRL, ROT_DES_CNT_RST);
++	printk("-----------------rot_desc_reg------------------\n");
++	printk("NextCfgAddr:         0x%lx\n",reg_read(dev, ROT_DS_FRM_DES));
++	printk("SrcBufferAddr:       0x%lx\n",reg_read(dev, ROT_DS_FRM_DES));
++	printk("SrcStride:           0x%lx\n",reg_read(dev, ROT_DS_FRM_DES));
++	printk("FrameStop:           0x%lx\n",reg_read(dev, ROT_DS_FRM_DES));
++	printk("TargetBufferAddr:    0x%lx\n",reg_read(dev, ROT_DS_FRM_DES));
++	printk("TargetStride:        0x%lx\n",reg_read(dev, ROT_DS_FRM_DES));
++	printk("irq_ctrl:            0x%lx\n",reg_read(dev, ROT_DS_FRM_DES));
++	printk("-----------------rot_desc_reg------------------\n");
++}
++
++void dump_all(struct ingenic_rot_dev *dev)
++{
++	struct ingenic_rot_ctx *ctx;
++
++	ctx = dev->curr;
++
++	dump_rot_reg(dev);
++	dump_rot_desc_reg(dev);
++	dump_rot_desc(ctx->desc[0]);
++}
++
++void rot_clr_irq(struct ingenic_rot_dev *dev)
++{
++	uint32_t flag;
++
++	flag = reg_read(dev, ROT_INT_MASK) & reg_read(dev, ROT_ST);
++	if(flag & ROT_EOF) {
++		reg_write(dev, ROT_CLR_ST, ROT_CLR_EOF);
++	}
++	if(flag & ROT_SOF) {
++		reg_write(dev, ROT_CLR_ST, ROT_CLR_SOF);
++	}
++	if(flag & ROT_GEN_STOP_ACK) {
++		reg_write(dev, ROT_CLR_ST, ROT_GEN_STOP_ACK);
++	}
++}
++
++int wait_rot_state(struct ingenic_rot_dev *dev, int32_t state, uint32_t flag)
++{
++	unsigned long timeout = 100000;
++	while((	(!(reg_read(dev, ROT_ST) & state)) == flag) && timeout) {
++		timeout--;
++		udelay(10);
++	}
++	if(timeout <= 0) {
++		printk("wait state timeout! state = %d, ROT_ST = 0x%lx\n", state, reg_read(dev, ROT_ST));
++		return -1;
++	}
++	return 0;
++}
++
++void rot_set_src_desc(struct ingenic_rot_dev *dev, dma_addr_t addr)
++{
++	struct ingenic_rot_ctx *ctx;
++	struct ingenic_rot_desc *desc;
++	struct rot_frm_info *frm_info;
++
++	ctx = dev->curr;
++	desc = ctx->desc[0];
++	frm_info = &ctx->in;
++
++	desc->NextCfgAddr = ctx->desc_phys[0];
++	desc->SrcBufferAddr = addr;
++	desc->SrcStride = frm_info->width;
++}
++
++void rot_set_dst_desc(struct ingenic_rot_dev *dev, dma_addr_t addr)
++{
++	struct ingenic_rot_ctx *ctx;
++	struct ingenic_rot_desc *desc;
++	struct rot_frm_info *frm_info;
++
++	ctx = dev->curr;
++	desc = ctx->desc[0];
++	frm_info = &ctx->out;
++
++	desc->TargetBufferAddr = addr;
++
++	if((ctx->angle == 90) || (ctx->angle == 270))
++		desc->TargetStride = frm_info->height;
++	else
++		desc->TargetStride = frm_info->width;
++}
++
++void rot_set_hflip(struct ingenic_rot_dev *dev, uint32_t hflip)
++{
++	uint32_t cfg;
++
++	cfg = reg_read(dev, ROT_GLB_CFG);
++	if(hflip)
++		cfg |= ROT_H_MIRROR;
++	else
++		cfg &= ~ROT_H_MIRROR;
++
++	reg_write(dev, ROT_GLB_CFG, cfg);
++}
++
++void rot_set_vflip(struct ingenic_rot_dev *dev, uint32_t vflip)
++{
++	uint32_t cfg;
++
++	cfg = reg_read(dev, ROT_GLB_CFG);
++	if(vflip)
++		cfg |= ROT_V_MIRROR;
++	else
++		cfg &= ~ROT_V_MIRROR;
++
++	reg_write(dev, ROT_GLB_CFG, cfg);
++}
++
++void rot_set_angle(struct ingenic_rot_dev *dev, uint32_t angle)
++{
++	uint32_t cfg;
++
++	cfg = reg_read(dev, ROT_GLB_CFG);
++	switch(angle) {
++	case 0:
++		cfg |= ROT_ANGLE_0;
++		break;
++	case 90:
++		cfg |= ROT_ANGLE_90;
++		break;
++	case 180:
++		cfg |= ROT_ANGLE_180;
++		break;
++	case 270:
++		cfg |= ROT_ANGLE_270;
++		break;
++	default:
++		printk("!!!!!Not support angle!\n");
++		break;
++	}
++
++	reg_write(dev, ROT_GLB_CFG, cfg);
++}
++
++void rot_set_dst_cfg(struct ingenic_rot_dev *dev, struct rot_frm_info *out)
++{
++	uint32_t cfg;
++
++	cfg = reg_read(dev, ROT_GLB_CFG);
++	switch(out->fmt->fourcc) {
++	case V4L2_PIX_FMT_RGB32:
++	case V4L2_PIX_FMT_XRGB32:
++	case V4L2_PIX_FMT_ARGB32:
++		cfg |= ROT_WDMA_FMT_ARGB8888;
++		break;
++	case V4L2_PIX_FMT_RGB565:
++		cfg |= ROT_WDMA_FMT_RGB565;
++		break;
++	case V4L2_PIX_FMT_RGB555:
++		cfg |= ROT_WDMA_FMT_RGB555;
++		break;
++	case V4L2_PIX_FMT_YUYV:
++		cfg |= ROT_WDMA_FMT_YUV422;
++		break;
++	default:
++		printk("!!!!!Not support fmt!\n");
++		break;
++	}
++	reg_write(dev, ROT_GLB_CFG, cfg);
++}
++
++void rot_set_src_cfg(struct ingenic_rot_dev *dev, struct rot_frm_info *in)
++{
++	uint32_t cfg;
++	uint32_t frm_size = 0;
++
++	frm_size |= in->width << ROT_FRM_WIDTH_LBIT;
++	frm_size  |= in->height << ROT_FRM_HEIGHT_LBIT;
++	reg_write(dev, ROT_FRM_SIZE, frm_size);
++
++	cfg = reg_read(dev, ROT_GLB_CFG);
++	switch(in->fmt->fourcc) {
++	case V4L2_PIX_FMT_ARGB32:
++	case V4L2_PIX_FMT_RGB32:
++		cfg |= ROT_RDMA_FMT_ARGB8888;
++		break;
++	case V4L2_PIX_FMT_XRGB32:
++		cfg |= ROT_RDMA_FMT_RGB888;
++		break;
++	case V4L2_PIX_FMT_ABGR32:
++	case V4L2_PIX_FMT_BGR32:
++		cfg |= ROT_RDMA_FMT_ARGB8888;
++		cfg |= ROT_RDMA_ORDER_BGR;
++		break;
++	case V4L2_PIX_FMT_XBGR32:
++		cfg |= ROT_RDMA_FMT_RGB888;
++		cfg |= ROT_RDMA_ORDER_BGR;
++		break;
++	case V4L2_PIX_FMT_RGB565:
++		cfg |= ROT_RDMA_FMT_RGB565;
++		break;
++	case V4L2_PIX_FMT_RGB555:
++		cfg |= ROT_RDMA_FMT_RGB555;
++		break;
++	case V4L2_PIX_FMT_ARGB555:
++		cfg |= ROT_RDMA_FMT_RGB1555;
++		break;
++	case V4L2_PIX_FMT_YUYV:
++		cfg |= ROT_RDMA_FMT_YUV422;
++		break;
++	default:
++		printk("!!!!!Not support fmt!\n");
++		break;
++	}
++	reg_write(dev, ROT_GLB_CFG, cfg);
++}
++
++#define CPM_ROT_SOFT_RESET	(0x1 << 17)
++#define CPM_SOFT_RESET		(0xb00000c4)
++void rot_cpm_reset(void)
++{
++	outl(CPM_ROT_SOFT_RESET, CPM_SOFT_RESET);
++	udelay(2);
++	outl(0, CPM_SOFT_RESET);
++}
++
++void rot_reset(struct ingenic_rot_dev *dev)
++{
++	struct ingenic_rot_ctx *ctx;
++	uint32_t cfg = 0;
++	int i;
++
++	ctx = dev->curr;
++
++	for(i = 0; i < ROT_DESC_NUM; i++) {
++		memset(ctx->desc[i], 0, sizeof(struct ingenic_rot_desc));
++	}
++#if defined(ROT_GEN_STOP) || defined(ROT_QCK_STOP)
++	ctx->desc[0]->FrameStop.b.stop = 0;
++#else
++	ctx->desc[0]->FrameStop.b.stop = 1;
++#endif
++	ctx->desc[0]->irq_ctrl.d32 = ROT_EOF_MASK | ROT_SOF_MASK;
++	cfg = ROT_WDMA_BURST_32 | ROT_RDMA_BURST_32;
++	cfg |= ROT_RDMA_ORDER_RGB;
++
++	/* ahb0 = 300M 720p 60fps */
++	reg_write(dev, ROT_QOS_CFG, (reg_read(dev, ROT_QOS_CFG) & (~0xff)) | 13);
++	/* Set rot qos value */
++	reg_write(dev, ROT_QOS_CTRL, 0x1);
++	reg_write(dev, ROT_GLB_CFG, cfg);
++	reg_write(dev, ROT_FRM_CFG_ADDR, ctx->desc_phys[0]);
++}
++
++void rot_start(struct ingenic_rot_dev *dev)
++{
++	reg_write(dev, ROT_INT_MASK, ROT_EOF_MASK);
++	reg_write(dev, ROT_CTRL, ROT_START);
++}
++
++void rot_qck_stop(struct ingenic_rot_dev *dev)
++{
++	reg_write(dev, ROT_CTRL, ROT_QCK_STP);
++	return;
++}
++
++void rot_gen_stop(struct ingenic_rot_dev *dev)
++{
++	reg_write(dev, ROT_CTRL, ROT_GEN_STP);
++	return;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-rotate/rotate-regs.h b/module_drivers/drivers/media/platform/ingenic-rotate/rotate-regs.h
+new file mode 100644
+index 000000000..e66d6c643
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-rotate/rotate-regs.h
+@@ -0,0 +1,204 @@
++/* * drivers/media/platform/ingenic_rotate/rotate-regs.h
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * Author:clwang<chunlei.wang@ingenic.com>
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#ifndef __ROTATER_REG_H__
++#define __ROTATER_REG_H__
++
++/*-------------------------------------------------------------------------------
++ *			      Rotater Register Offset
++ * -----------------------------------------------------------------------------*/
++
++
++/* RW	32	0x0000_0000	frame descriptor's addres */
++#define	ROT_FRM_CFG_ADDR		        (0x0000)
++/* RW	32	0x0000_0000	frame's size */
++#define	ROT_FRM_SIZE				(0x0004)
++/* RW	32	0x0000_0000	global config */
++#define	ROT_GLB_CFG				(0x0008)
++/* -W	32	0x0000_0000	rotate control */
++#define	ROT_CTRL			        (0x000c)
++/* R-	32	0x0000_0000	rotate status */
++#define	ROT_ST				        (0x0010)
++/* R-	32	0x0000_0000	rotarer clear status */
++#define	ROT_CLR_ST			        (0x0014)
++/* -W	32	0x0000_0000	rotator interrupt mask */
++#define	ROT_INT_MASK				(0x0018)
++/* RW	32	0x0000_0000	RDMA`s current site */
++#define	ROT_RDMA_SITE			        (0x0020)
++/* RW	32	0x0000_0000	WDMA`s current site */
++#define	ROT_WDMA_SITE			        (0x0024)
++/* R-	32	0x0000_0000	Read the frame configure */
++#define	ROT_DS_FRM_DES				(0x0028)
++/* RW	32	0x0000_0000	Rotator QOS config */
++#define	ROT_QOS_CTRL				(0x0030)
++#define	ROT_QOS_CFG				(0x0034)
++
++
++/*-------------------------------------------------------------------------------
++ *			DPU Registers Bits Field Define
++ * -----------------------------------------------------------------------------*/
++
++
++/* frame's size(ROT_FRM_SIZE) bit field define */
++
++/* Frame's width */
++#define ROT_FRM_WIDTH_LBIT			(0)
++#define ROT_FRM_WIDTH_HBIT			(10)
++#define ROT_FRM_WIDTH_MASK	      \
++	GENMASK(ROT_FRM_WIDTH_HBIT, ROT_FRM_WIDTH_LBIT)
++/* Frame's height */
++#define ROT_FRM_HEIGHT_LBIT			(16)
++#define ROT_FRM_HEIGHT_HBIT			(26)
++#define ROT_FRM_HEIGHT_MASK	      \
++	GENMASK(ROT_FRM_HEIGHT_HBIT, ROT_FRM_HEIGHT_LBIT)
++
++/* global config(ROT_GLB_CFG) bit field define */
++
++/* RDMA max length of the block DMA's burst. */
++#define ROT_RDMA_BURST_LEN_LBIT			(0)
++#define ROT_RDMA_BURST_LEN_HBIT			(1)
++#define ROT_RDMA_BURST_LEN_MASK	      \
++	GENMASK(ROT_RDMA_BURST_LEN_HBIT, ROT_RDMA_BURST_LEN_LBIT)
++
++#define	ROT_RDMA_BURST_4		(0) << ROT_RDMA_BURST_LEN_LBIT
++#define	ROT_RDMA_BURST_8		(1) << ROT_RDMA_BURST_LEN_LBIT
++#define	ROT_RDMA_BURST_16		(2) << ROT_RDMA_BURST_LEN_LBIT
++#define	ROT_RDMA_BURST_32		(3) << ROT_RDMA_BURST_LEN_LBIT
++/* WDMA max length of the block DMA's burst. */
++#define ROT_WDMA_BURST_LEN_LBIT			(2)
++#define ROT_WDMA_BURST_LEN_HBIT			(3)
++#define ROT_WDMA_BURST_LEN_MASK	      \
++	GENMASK(ROT_WDMA_BURST_LEN_HBIT, ROT_WDMA_BURST_LEN_LBIT)
++
++#define	ROT_WDMA_BURST_4		(0) << ROT_WDMA_BURST_LEN_LBIT
++#define	ROT_WDMA_BURST_8		(1) << ROT_WDMA_BURST_LEN_LBIT
++#define	ROT_WDMA_BURST_16		(2) << ROT_WDMA_BURST_LEN_LBIT
++#define	ROT_WDMA_BURST_32		(3) << ROT_WDMA_BURST_LEN_LBIT
++/* Rotater angle. */
++#define ROT_ANGLE_LBIT			(4)
++#define ROT_ANGLE_HBIT			(5)
++#define ROT_ANGLE_MASK		      \
++	GENMASK(ROT_ANGLE_HBIT, ROT_ANGLE_LBIT)
++
++#define	ROT_ANGLE_0			(0) << ROT_ANGLE_LBIT
++#define	ROT_ANGLE_90			(1) << ROT_ANGLE_LBIT
++#define	ROT_ANGLE_180			(2) << ROT_ANGLE_LBIT
++#define	ROT_ANGLE_270			(3) << ROT_ANGLE_LBIT
++/* Vertical mirror */
++#define	ROT_V_MIRROR			BIT(6)
++/* Horizontal mirror */
++#define	ROT_H_MIRROR			BIT(7)
++/* Target format. */
++#define ROT_WDMA_FMT_LBIT			(12)
++#define ROT_WDMA_FMT_HBIT			(13)
++#define ROT_WDMA_FMT_MASK	      \
++	GENMASK(ROT_WDMA_FMT_HBIT, ROT_WDMA_FMT_LBIT)
++
++#define	ROT_WDMA_FMT_ARGB8888		(0) << ROT_WDMA_FMT_LBIT
++#define	ROT_WDMA_FMT_RGB565		(1) << ROT_WDMA_FMT_LBIT
++#define	ROT_WDMA_FMT_RGB555		(2) << ROT_WDMA_FMT_LBIT
++#define	ROT_WDMA_FMT_YUV422		(3) << ROT_WDMA_FMT_LBIT
++/* RDMA ORDER. */
++#define ROT_RDMA_ORDER_LBIT			(16)
++#define ROT_RDMA_ORDER_HBIT			(18)
++#define ROT_RDMA_ORDER_MASK	      \
++	GENMASK(ROT_RDMA_ORDER_HBIT, ROT_RDMA_ORDER_LBIT)
++
++#define	ROT_RDMA_ORDER_RGB      	(0) << ROT_RDMA_ORDER_LBIT
++#define	ROT_RDMA_ORDER_RBG		(1) << ROT_RDMA_ORDER_LBIT
++#define	ROT_RDMA_ORDER_GRB		(2) << ROT_RDMA_ORDER_LBIT
++#define	ROT_RDMA_ORDER_GBR		(3) << ROT_RDMA_ORDER_LBIT
++#define	ROT_RDMA_ORDER_BRG		(4) << ROT_RDMA_ORDER_LBIT
++#define	ROT_RDMA_ORDER_BGR		(5) << ROT_RDMA_ORDER_LBIT
++/* RDMA format. */
++#define ROT_RDMA_FMT_LBIT			(24)
++#define ROT_RDMA_FMT_HBIT			(27)
++#define ROT_RDMA_FMT_MASK	      \
++	GENMASK(ROT_RDMA_FMT_HBIT, ROT_RDMA_FMT_LBIT)
++
++#define	ROT_RDMA_FMT_RGB555		(0) << ROT_RDMA_FMT_LBIT
++#define	ROT_RDMA_FMT_RGB1555		(1) << ROT_RDMA_FMT_LBIT
++#define	ROT_RDMA_FMT_RGB565		(2) << ROT_RDMA_FMT_LBIT
++#define	ROT_RDMA_FMT_RGB888		(4) << ROT_RDMA_FMT_LBIT
++#define	ROT_RDMA_FMT_ARGB8888		(5) << ROT_RDMA_FMT_LBIT
++#define	ROT_RDMA_FMT_YUV422		(10) << ROT_RDMA_FMT_LBIT
++
++/* rotate control(ROT_CTRL) bit field define */
++
++/* START */
++#define	ROT_START			BIT(0)
++/* QCK_STOP */
++#define	ROT_QCK_STP			BIT(1)
++/* GEN_STOP */
++#define	ROT_GEN_STP			BIT(2)
++/* Reset the counter of FRM_DES */
++#define ROT_DES_CNT_RST			BIT(3)
++
++/* rotate status(ROT_SATUS) bit field define */
++
++/* Rotater is working */
++#define	ROT_WORKING			BIT(0)
++/* Rotater is general stop */
++#define	ROT_GEN_STOP_ACK		BIT(1)
++/* One frame read end */
++#define	ROT_EOF				BIT(2)
++/* One frme read start */
++#define	ROT_SOF				BIT(3)
++/* Mask of ROT_GEN_STOP_ACK */
++#define	ROT_GSA_MASK_ST			BIT(17)
++/* Mask of FRM_END */
++#define	ROT_EOF_MASK_ST			BIT(18)
++/* Mask of FRM_START */
++#define	ROT_SOF_MASK_ST			BIT(19)
++
++/* rotarer clear status(ROT_CLR_ST) bit field define */
++
++/* Clear general stop acknowledge */
++#define	ROT_CLR_GEN_STOP_ACK		BIT(1)
++/* Clear FRM_END */
++#define	ROT_CLR_EOF			BIT(2)
++/* Clear FRM_START */
++#define	ROT_CLR_SOF			BIT(3)
++
++/* rotator interrupt mask(ROT_INT_MASK) bit field define */
++
++/* Mask general stop acknowledge */
++#define	ROT_GSA_MASK			BIT(1)
++/* Mask FRM_END */
++#define	ROT_EOF_MASK			BIT(2)
++/* Mask FRM_START */
++#define	ROT_SOF_MASK			BIT(3)
++
++/* rotator QOS config (ROT_QOS) bit field define */
++
++/* STD_CLK */
++#define ROT_STD_CLK_LBIT			(0)
++#define ROT_STD_CLK_HBIT			(7)
++#define ROT_STD_CLK_MASK	      \
++	GENMASK(ROT_STD_CLK_HBIT, ROT_STD_CLK_LBIT)
++/* STD_THR0 */
++#define ROT_STD_THR0_LBIT			(8)
++#define ROT_STD_THR0_HBIT			(15)
++#define ROT_STD_THR0_MASK	      \
++	GENMASK(ROT_STD_THR0_HBIT, ROT_STD_THR0_LBIT)
++/* STD_THR1 */
++#define ROT_STD_THR1_LBIT			(16)
++#define ROT_STD_THR1_HBIT			(23)
++#define ROT_STD_THR1_MASK	      \
++	GENMASK(ROT_STD_THR1_HBIT, ROT_STD_THR1_LBIT)
++/* STD_THR2 */
++#define ROT_STD_THR2_LBIT			(24)
++#define ROT_STD_THR2_HBIT			(31)
++#define ROT_STD_THR2_MASK	      \
++	GENMASK(ROT_STD_THR2_HBIT, ROT_STD_THR2_LBIT)
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-rotate/rotate.c b/module_drivers/drivers/media/platform/ingenic-rotate/rotate.c
+new file mode 100644
+index 000000000..f09e60380
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-rotate/rotate.c
+@@ -0,0 +1,876 @@
++/* * drivers/media/platform/ingenic_rotate/rotate.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * Author:clwang<chunlei.wang@ingenic.com>
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/module.h>
++#include <linux/fs.h>
++#include <linux/version.h>
++#include <linux/timer.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/of.h>
++
++#include <linux/platform_device.h>
++#include <media/v4l2-mem2mem.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ioctl.h>
++#include <media/videobuf2-core.h>
++//#include <media/videobuf2-dma-contig.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++#include <media/ingenic_video_nr.h>
++#include <linux/of_reserved_mem.h>
++
++#include "rotate.h"
++#include "rotate-regs.h"
++
++#define fh2ctx(__fh) container_of(__fh, struct ingenic_rot_ctx, fh)
++
++static ktime_t time_now, time_last;
++static long interval_in_ns;
++
++static struct rot_fmt formats[] = {
++	{
++		.name	= "ARGB_8888",
++		.fourcc	= V4L2_PIX_FMT_ARGB32,
++		.depth	= 32,
++		.types	= MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
++	},
++	{
++		.name	= "RGB_8888",
++		.fourcc	= V4L2_PIX_FMT_RGB32,
++		.depth	= 32,
++		.types	= MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
++	},
++	{
++		.name	= "RGB_8888",
++		.fourcc	= V4L2_PIX_FMT_XRGB32,
++		.depth	= 32,
++		.types	= MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
++	},
++	{
++		.name	= "ABGR_8888",
++		.fourcc	= V4L2_PIX_FMT_ABGR32,
++		.depth	= 32,
++		.types	= MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
++	},
++	{
++		.name	= "BGR_8888",
++		.fourcc	= V4L2_PIX_FMT_BGR32,
++		.depth	= 32,
++		.types	= MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
++	},
++	{
++		.name	= "BGR_8888",
++		.fourcc	= V4L2_PIX_FMT_XBGR32,
++		.depth	= 32,
++		.types	= MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
++	},
++	{
++		.name	= "RGB_565",
++		.fourcc	= V4L2_PIX_FMT_RGB565,
++		.depth	= 16,
++		.types	= MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
++	},
++	{
++		.name	= "RGB_555",
++		.fourcc	= V4L2_PIX_FMT_RGB555,
++		.depth	= 16,
++		.types	= MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
++	},
++	{
++		.name	= "ARGB_1555",
++		.fourcc	= V4L2_PIX_FMT_ARGB555,
++		.depth	= 16,
++		.types	= MEM2MEM_OUTPUT,
++	},
++	{
++		.name	= "YUV 422P",
++		.fourcc	= V4L2_PIX_FMT_YUYV,
++		.depth	= 16,
++		.types	= MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
++	},
++};
++#define NUM_FORMATS ARRAY_SIZE(formats)
++
++static struct rot_fmt *find_fmt(struct v4l2_format *f)
++{
++	unsigned int i;
++	for (i = 0; i < NUM_FORMATS; i++) {
++		if (formats[i].fourcc == f->fmt.pix.pixelformat)
++			return &formats[i];
++	}
++	return NULL;
++}
++
++
++static struct rot_frm_info *get_frame(struct ingenic_rot_ctx *ctx,
++		enum v4l2_buf_type type)
++{
++	switch (type) {
++	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++		return &ctx->in;
++	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++		return &ctx->out;
++	default:
++		return ERR_PTR(-EINVAL);
++	}
++}
++
++static int rot_queue_setup(struct vb2_queue *vq,
++			   unsigned int *nbuffers, unsigned int *nplanes,
++			   unsigned int sizes[], struct device *alloc_ctxs[])
++{
++	struct ingenic_rot_ctx *ctx = vb2_get_drv_priv(vq);
++	struct rot_frm_info *f = get_frame(ctx, vq->type);
++
++	if (IS_ERR(f))
++		return PTR_ERR(f);
++
++	*nplanes = 1;
++	sizes[0] = f->size;
++	alloc_ctxs[0] = ctx->dev->dev;
++
++	if (*nbuffers == 0)
++		*nbuffers = 1;
++
++	return 0;
++}
++
++static int rot_buf_prepare(struct vb2_buffer *vb)
++{
++	struct ingenic_rot_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
++	struct rot_frm_info *f = get_frame(ctx, vb->vb2_queue->type);
++
++	if (IS_ERR(f))
++		return PTR_ERR(f);
++	vb2_set_plane_payload(vb, 0, f->size);
++	return 0;
++}
++
++static void rot_buf_queue(struct vb2_buffer *vb)
++{
++	struct ingenic_rot_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
++	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
++
++	if (ctx->m2m_ctx)
++		v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
++}
++
++
++static struct vb2_ops rot_qops = {
++	.queue_setup	= rot_queue_setup,
++	.buf_prepare	= rot_buf_prepare,
++	.buf_queue	= rot_buf_queue,
++};
++
++static int queue_init(void *priv, struct vb2_queue *src_vq,
++						struct vb2_queue *dst_vq)
++{
++	struct ingenic_rot_ctx *ctx = priv;
++	int ret;
++
++	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
++	src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
++	src_vq->drv_priv = ctx;
++	src_vq->ops = &rot_qops;
++	src_vq->mem_ops = &ingenic_vb2_dma_contig_memops;
++	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
++	src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
++	src_vq->lock = &ctx->dev->mutex;
++
++	ret = vb2_queue_init(src_vq);
++	if (ret)
++		return ret;
++
++	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++	dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
++	dst_vq->drv_priv = ctx;
++	dst_vq->ops = &rot_qops;
++	dst_vq->mem_ops = &ingenic_vb2_dma_contig_memops;
++	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
++	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
++	dst_vq->lock = &ctx->dev->mutex;
++
++	return vb2_queue_init(dst_vq);
++}
++
++static int rot_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct ingenic_rot_ctx *ctx = container_of(ctrl->handler, struct ingenic_rot_ctx,
++								ctrl_handler);
++	unsigned long flags;
++
++	spin_lock_irqsave(&ctx->dev->ctrl_lock, flags);
++	switch (ctrl->id) {
++	case V4L2_CID_HFLIP:
++		ctx->hflip = ctx->ctrl_hflip->val;
++		break;
++	case V4L2_CID_VFLIP:
++		ctx->vflip = ctx->ctrl_vflip->val;
++		break;
++	case V4L2_CID_ROTATE:
++		ctx->angle = ctx->ctrl_rot->val;
++		break;
++	}
++	spin_unlock_irqrestore(&ctx->dev->ctrl_lock, flags);
++	return 0;
++}
++
++static const struct v4l2_ctrl_ops rot_ctrl_ops = {
++	.s_ctrl		= rot_s_ctrl,
++};
++
++static int rot_setup_ctrls(struct ingenic_rot_ctx *ctx)
++{
++	struct ingenic_rot_dev *dev = ctx->dev;
++
++	v4l2_ctrl_handler_init(&ctx->ctrl_handler, 3);
++
++	ctx->ctrl_hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &rot_ctrl_ops,
++						V4L2_CID_HFLIP, 0, 1, 1, 0);
++
++	ctx->ctrl_vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &rot_ctrl_ops,
++						V4L2_CID_VFLIP, 0, 1, 1, 0);
++	ctx->ctrl_rot = v4l2_ctrl_new_std(&ctx->ctrl_handler, &rot_ctrl_ops,
++						V4L2_CID_ROTATE, 0, 270, 90, 0);
++
++	if (ctx->ctrl_handler.error) {
++		int err = ctx->ctrl_handler.error;
++		v4l2_err(&dev->v4l2_dev, "rot_setup_ctrls failed\n");
++		v4l2_ctrl_handler_free(&ctx->ctrl_handler);
++		return err;
++	}
++
++	return 0;
++}
++
++static void rot_update_info(struct ingenic_rot_ctx *ctx)
++{
++	struct rot_frm_info *in, *out;
++
++	in = &ctx->in;
++	out = &ctx->out;
++
++	in->width = DEFAULT_WIDTH;
++	in->height = DEFAULT_HEIGHT;
++	in->fmt = &formats[1];
++	in->bytesperline = DEFAULT_WIDTH * in->fmt->depth >> 3;
++	in->size = in->bytesperline * in->height;
++
++	out->width = DEFAULT_WIDTH;
++	out->height = DEFAULT_HEIGHT;
++	out->fmt = &formats[0];
++	out->bytesperline = DEFAULT_WIDTH * out->fmt->depth >> 3;
++	out->size = out->bytesperline * out->height;
++}
++
++static int rot_reqdesc(struct ingenic_rot_ctx *ctx)
++{
++	struct ingenic_rot_dev *dev = ctx->dev;
++	struct video_device *vfd = dev->vfd;
++	int i, size;
++
++	size = sizeof(struct ingenic_rot_desc) * ROT_DESC_NUM;
++	vfd->dev.coherent_dma_mask = DMA_BIT_MASK(32);
++	ctx->desc[0] = (struct ingenic_rot_desc *)dma_alloc_coherent(&vfd->dev, size,
++						&ctx->desc_phys[0], GFP_KERNEL);
++	if (!ctx->desc[0]) {
++		dev_err(&vfd->dev, "dma_alloc_coherent of size %d failed\n", size);
++		return -ENOMEM;
++	}
++
++	for(i = 1; i < ROT_DESC_NUM; i++) {
++		ctx->desc[i] = ctx->desc[0] + i;
++		ctx->desc_phys[i] = ctx->desc_phys[0] + i*sizeof(struct ingenic_rot_desc);
++	}
++	return 0;
++}
++
++static void rot_freedesc(struct ingenic_rot_ctx *ctx)
++{
++	struct ingenic_rot_dev *dev = ctx->dev;
++	struct video_device *vfd = dev->vfd;
++	int size;
++
++	size = sizeof(struct ingenic_rot_desc) * ROT_DESC_NUM;
++	dma_free_coherent(&vfd->dev, size, ctx->desc[0], ctx->desc_phys[0]);
++}
++
++static int rot_open(struct file *file)
++{
++	struct ingenic_rot_dev *dev = video_drvdata(file);
++	struct ingenic_rot_ctx *ctx = NULL;
++	int ret = 0;
++
++	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
++	if (!ctx)
++		return -ENOMEM;
++
++	if (mutex_lock_interruptible(&dev->mutex)) {
++		kfree(ctx);
++		return -ERESTARTSYS;
++	}
++	ctx->dev = dev;
++
++	/* Set default formats */
++	rot_update_info(ctx);
++
++	ret = rot_reqdesc(ctx);
++	if(ret) {
++		goto free;
++	}
++
++	v4l2_fh_init(&ctx->fh, video_devdata(file));
++	ctx->fh.ctrl_handler = &ctx->ctrl_handler;
++	file->private_data = &ctx->fh;
++	v4l2_fh_add(&ctx->fh);
++
++	ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
++	if (IS_ERR(ctx->m2m_ctx)) {
++		ret = PTR_ERR(ctx->m2m_ctx);
++		goto err;
++	}
++	ctx->fh.m2m_ctx = ctx->m2m_ctx;
++
++	ret = rot_setup_ctrls(ctx);
++	if(ret)
++		goto err;
++
++	/* Write the default values to the ctx struct */
++	v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
++
++	clk_prepare_enable(dev->clk);
++
++	mutex_unlock(&dev->mutex);
++
++	return 0;
++err:
++	rot_freedesc(ctx);
++	v4l2_fh_del(&ctx->fh);
++	v4l2_fh_exit(&ctx->fh);
++free:
++	mutex_unlock(&dev->mutex);
++	kfree(ctx);
++	return ret;
++}
++
++static int rot_release(struct file *file)
++{
++	struct ingenic_rot_dev *dev = video_drvdata(file);
++	struct ingenic_rot_ctx *ctx = fh2ctx(file->private_data);
++
++	clk_disable_unprepare(dev->clk);
++
++	mutex_lock(&dev->mutex);
++	v4l2_m2m_ctx_release(ctx->m2m_ctx);
++	mutex_unlock(&dev->mutex);
++	v4l2_ctrl_handler_free(&ctx->ctrl_handler);
++	v4l2_fh_del(&ctx->fh);
++	v4l2_fh_exit(&ctx->fh);
++	rot_freedesc(ctx);
++	kfree(ctx);
++	return 0;
++}
++
++static int vidioc_querycap(struct file *file, void *priv,
++				struct v4l2_capability *cap)
++{
++	strncpy(cap->driver, JZ_ROT_NAME, sizeof(cap->driver) - 1);
++	strncpy(cap->card, JZ_ROT_NAME, sizeof(cap->card) - 1);
++	cap->bus_info[0] = 0;
++	cap->version = KERNEL_VERSION(1, 0, 0);
++	/*
++	 * This is only a mem-to-mem video device. The capture and output
++	 * device capability flags are left only for backward compatibility
++	 * and are scheduled for removal.
++	 */
++	cap->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M;
++	cap->capabilities =  cap->device_caps |
++		V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
++		V4L2_CAP_DEVICE_CAPS;
++
++	return 0;
++}
++
++static int enum_fmt(struct v4l2_fmtdesc *f, u32 type)
++{
++	int i, num;
++	struct rot_fmt *fmt;
++
++	num = 0;
++	for (i = 0; i < NUM_FORMATS; ++i) {
++		if (formats[i].types & type) {
++			/* index-th format of type type found ? */
++			if (num == f->index)
++				break;
++			/* Correct type but haven't reached our index yet,
++			 * just increment per-type index */
++			++num;
++		}
++	}
++
++	if (i < NUM_FORMATS) {
++		/* Format found */
++		fmt = &formats[i];
++		strncpy(f->description, fmt->name, sizeof(f->description) - 1);
++		f->pixelformat = fmt->fourcc;
++		return 0;
++	}
++
++	/* Format not found */
++	return -EINVAL;
++}
++
++static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
++				   struct v4l2_fmtdesc *f)
++{
++	return enum_fmt(f, MEM2MEM_CAPTURE);
++}
++
++static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
++				   struct v4l2_fmtdesc *f)
++{
++	return enum_fmt(f, MEM2MEM_OUTPUT);
++}
++
++static inline struct ingenic_rot_ctx *fh_to_ctx(struct v4l2_fh *fh)
++{
++	return container_of(fh, struct ingenic_rot_ctx, fh);
++}
++
++static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f)
++{
++	struct ingenic_rot_ctx *ctx = fh_to_ctx(prv);
++	struct vb2_queue *vq;
++	struct rot_frm_info *frm;
++
++	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
++	if (!vq)
++		return -EINVAL;
++	frm = get_frame(ctx, f->type);
++	if (IS_ERR(frm))
++		return PTR_ERR(frm);
++
++	f->fmt.pix.width		= frm->width;
++	f->fmt.pix.height		= frm->height;
++	f->fmt.pix.field		= V4L2_FIELD_NONE;
++	f->fmt.pix.pixelformat		= frm->fmt->fourcc;
++	f->fmt.pix.bytesperline		= (frm->width * frm->fmt->depth) >> 3;
++	f->fmt.pix.sizeimage		= frm->size;
++	return 0;
++}
++
++static int vidioc_try_fmt(struct file *file, void *prv, struct v4l2_format *f)
++{
++	struct rot_fmt *fmt;
++	enum v4l2_field *field;
++
++	fmt = find_fmt(f);
++	if (!fmt)
++		return -EINVAL;
++
++	field = &f->fmt.pix.field;
++	if (*field == V4L2_FIELD_ANY)
++		*field = V4L2_FIELD_NONE;
++	else if (*field != V4L2_FIELD_NONE)
++		return -EINVAL;
++
++	if (f->fmt.pix.width > MAX_WIDTH
++		|| f->fmt.pix.height > MAX_HEIGHT
++		|| f->fmt.pix.width < MIN_WIDTH
++		|| f->fmt.pix.height < MIN_HEIGHT) {
++		return -EINVAL;
++	}
++
++	f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3;
++	f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
++	return 0;
++}
++
++static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f)
++{
++	struct ingenic_rot_ctx *ctx = fh_to_ctx(prv);
++	struct ingenic_rot_dev *dev = ctx->dev;
++	struct vb2_queue *vq;
++	struct rot_frm_info *frm;
++	struct rot_fmt *fmt;
++	int ret = 0;
++
++	/* Adjust all values accordingly to the hardware capabilities
++	 * and chosen format. */
++	ret = vidioc_try_fmt(file, prv, f);
++	if (ret)
++		return ret;
++	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
++	if (vb2_is_busy(vq)) {
++		v4l2_err(&dev->v4l2_dev, "queue (%d) bust\n", f->type);
++		return -EBUSY;
++	}
++	frm = get_frame(ctx, f->type);
++	if (IS_ERR(frm))
++		return PTR_ERR(frm);
++	fmt = find_fmt(f);
++	if (!fmt)
++		return -EINVAL;
++	frm->width	= f->fmt.pix.width;
++	frm->height	= f->fmt.pix.height;
++	frm->size	= f->fmt.pix.sizeimage;
++	frm->fmt	= fmt;
++	frm->bytesperline	= f->fmt.pix.bytesperline;
++	return 0;
++}
++
++static int vidioc_streamon(struct file *file, void *priv,
++					enum v4l2_buf_type type)
++{
++	struct ingenic_rot_ctx *ctx = priv;
++
++	return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
++}
++
++static int vidioc_streamoff(struct file *file, void *priv,
++					enum v4l2_buf_type type)
++{
++	struct ingenic_rot_ctx *ctx = priv;
++
++	return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
++}
++
++/* Need change, One frame spends times */
++#define ROT_TIMEOUT 400
++
++static void job_abort(void *prv)
++{
++	struct ingenic_rot_ctx *ctx = prv;
++	struct ingenic_rot_dev *dev = ctx->dev;
++	int ret;
++
++	if (dev->curr == NULL) /* No job currently running */
++		return;
++
++	ret = wait_event_timeout(dev->irq_queue,
++		dev->curr == NULL,
++		msecs_to_jiffies(ROT_TIMEOUT));
++	if(!ret) {
++		struct vb2_v4l2_buffer *src_vb, *dst_vb;
++
++		rot_cpm_reset();
++		src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
++		dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
++		dst_vb->vb2_buf.timestamp = src_vb->vb2_buf.timestamp;
++		dst_vb->timecode = src_vb->timecode;
++		dst_vb->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
++		dst_vb->flags |=
++			src_vb->flags
++			& V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
++
++		v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_ERROR);
++		v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_ERROR);
++
++		v4l2_m2m_job_finish(dev->m2m_dev,
++				    ctx->m2m_ctx);
++		dev->curr = NULL;
++	}
++}
++
++static void device_run(void *prv)
++{
++	struct ingenic_rot_ctx *ctx = prv;
++	struct ingenic_rot_dev *dev = ctx->dev;
++	struct vb2_v4l2_buffer *src, *dst;
++	unsigned long flags;
++
++	dev->curr = ctx;
++
++	src = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
++	dst = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
++
++	spin_lock_irqsave(&dev->ctrl_lock, flags);
++
++	rot_reset(dev);
++
++	rot_set_src_cfg(dev, &ctx->in);
++	rot_set_src_desc(dev, ingenic_vb2_dma_contig_plane_dma_addr(&src->vb2_buf, 0));
++
++	rot_set_dst_cfg(dev, &ctx->out);
++	rot_set_dst_desc(dev, ingenic_vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0));
++
++	rot_set_angle(dev, ctx->angle);
++	rot_set_vflip(dev, ctx->vflip);
++	rot_set_hflip(dev, ctx->hflip);
++
++	time_now = ktime_get();
++
++	rot_start(dev);
++
++#ifdef ROT_GEN_STOP
++	rot_gen_stop(dev);
++#endif
++
++	spin_unlock_irqrestore(&dev->ctrl_lock, flags);
++}
++
++static irqreturn_t rot_irq_handler(int irq, void *prv)
++{
++	struct ingenic_rot_dev *dev = prv;
++	struct ingenic_rot_ctx *ctx = dev->curr;
++	struct vb2_v4l2_buffer *src, *dst;
++
++	time_last = ktime_get();
++	interval_in_ns = time_last - time_now;
++
++	rot_clr_irq(dev);
++
++	if(unlikely(ctx == NULL)) {
++		printk("Rotater:ctx == NULL\n");
++		return IRQ_HANDLED;
++	}
++
++	src = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
++	if(unlikely(src == NULL)) {
++		printk("Rotater:src == NULL\n");
++		return IRQ_HANDLED;
++	}
++	dst = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
++	if(unlikely(dst == NULL)) {
++		printk("Rotater:dst == NULL\n");
++		return IRQ_HANDLED;
++	}
++
++	dst->timecode = src->timecode;
++	dst->vb2_buf.timestamp = src->vb2_buf.timestamp;
++
++	v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE);
++	v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
++	v4l2_m2m_job_finish(dev->m2m_dev, ctx->m2m_ctx);
++
++	dev->curr = NULL;
++#ifdef ROT_QCK_STOP
++	rot_qck_stop(dev);
++#endif
++#if defined(ROT_GEN_STOP) || defined(ROT_QCK_STOP)
++	schedule_work(&dev->rot_work);
++#endif
++	wake_up(&dev->irq_queue);
++	return IRQ_HANDLED;
++}
++
++#if defined(ROT_GEN_STOP) || defined(ROT_QCK_STOP)
++static void rot_wait_dev_end(struct work_struct *rot_work)
++{
++	struct ingenic_rot_dev *dev;
++
++	dev = container_of(rot_work, struct ingenic_rot_dev, rot_work);
++	wait_rot_state(dev, ROT_WORKING, 0);
++}
++#endif
++
++static const struct v4l2_file_operations rot_fops = {
++	.owner		= THIS_MODULE,
++	.open		= rot_open,
++	.release	= rot_release,
++	.poll		= v4l2_m2m_fop_poll,
++	.unlocked_ioctl	= video_ioctl2,
++	.mmap		= v4l2_m2m_fop_mmap,
++};
++
++static const struct v4l2_ioctl_ops rot_ioctl_ops = {
++	.vidioc_querycap		= vidioc_querycap,
++
++	.vidioc_enum_fmt_vid_cap	= vidioc_enum_fmt_vid_cap,
++	.vidioc_g_fmt_vid_cap		= vidioc_g_fmt,
++	.vidioc_try_fmt_vid_cap		= vidioc_try_fmt,
++	.vidioc_s_fmt_vid_cap		= vidioc_s_fmt,
++
++	.vidioc_enum_fmt_vid_out	= vidioc_enum_fmt_vid_out,
++	.vidioc_g_fmt_vid_out		= vidioc_g_fmt,
++	.vidioc_try_fmt_vid_out		= vidioc_try_fmt,
++	.vidioc_s_fmt_vid_out		= vidioc_s_fmt,
++
++	.vidioc_reqbufs			= v4l2_m2m_ioctl_reqbufs,
++	.vidioc_querybuf		= v4l2_m2m_ioctl_querybuf,
++	.vidioc_qbuf			= v4l2_m2m_ioctl_qbuf,
++	.vidioc_dqbuf			= v4l2_m2m_ioctl_dqbuf,
++
++	.vidioc_streamon		= vidioc_streamon,
++	.vidioc_streamoff		= vidioc_streamoff,
++};
++
++static struct video_device rot_videodev = {
++	.name		= "ingenic-rot",
++	.fops		= &rot_fops,
++	.ioctl_ops	= &rot_ioctl_ops,
++	.minor		= -1,
++	.release	= video_device_release,
++	.vfl_dir	= VFL_DIR_M2M,
++};
++
++static struct v4l2_m2m_ops rot_m2m_ops = {
++	.device_run	= device_run,
++	.job_abort	= job_abort,
++};
++
++static int ingenic_rot_probe(struct platform_device *pdev)
++{
++	struct ingenic_rot_dev *dev;
++	struct video_device *vfd;
++	struct resource *res;
++	int ret = 0;
++
++	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
++	if (!dev)
++		return -ENOMEM;
++
++	dev->dev = &pdev->dev;
++	spin_lock_init(&dev->ctrl_lock);
++	mutex_init(&dev->mutex);
++	atomic_set(&dev->num_inst, 0);
++	init_waitqueue_head(&dev->irq_queue);
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++	dev->regs = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(dev->regs))
++		return PTR_ERR(dev->regs);
++
++	/* interrupt service routine registration */
++	dev->irq = ret = platform_get_irq(pdev, 0);
++	if (dev->irq < 0) {
++		dev_err(&pdev->dev, "cannot find IRQ\n");
++		return ret;
++	}
++
++	ret = devm_request_irq(&pdev->dev, dev->irq, rot_irq_handler,
++						0, pdev->name, dev);
++	if (ret) {
++		dev_err(&pdev->dev, "failed to install IRQ\n");
++		return ret;
++	}
++
++	/* clocks */
++	dev->clk = clk_get(&pdev->dev, "gate_rot");
++	if (IS_ERR(dev->clk)) {
++		dev_err(&pdev->dev, "cannot get clock\n");
++		ret = PTR_ERR(dev->clk);
++		return ret;
++	}
++	dev_dbg(&pdev->dev, "rot clock source %p\n", dev->clk);
++
++#if defined(ROT_QCK_STOP) || defined(ROT_GEN_STOP)
++	INIT_WORK(&dev->rot_work, rot_wait_dev_end);
++#endif
++	dev->alloc_ctx = ingenic_vb2_dma_contig_init_ctx(&pdev->dev);
++	if (IS_ERR(dev->alloc_ctx)) {
++		ret = PTR_ERR(dev->alloc_ctx);
++		goto clk_get_rollback;
++	}
++
++	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
++	if (ret)
++		goto alloc_ctx_cleanup;
++	vfd = video_device_alloc();
++	if (!vfd) {
++		v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
++		ret = -ENOMEM;
++		goto unreg_v4l2_dev;
++	}
++	*vfd = rot_videodev;
++	vfd->lock = &dev->mutex;
++	vfd->v4l2_dev = &dev->v4l2_dev;
++	vfd->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M;
++
++	ret = video_register_device(vfd, VFL_TYPE_VIDEO, INGENIC_ROTATE_VIDEO_NR);
++	if (ret) {
++		v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
++		goto rel_vdev;
++	}
++	video_set_drvdata(vfd, dev);
++	snprintf(vfd->name, sizeof(vfd->name), "%s", rot_videodev.name);
++	dev->vfd = vfd;
++	v4l2_info(&dev->v4l2_dev, "device registered as /dev/video%d\n",
++								vfd->num);
++	platform_set_drvdata(pdev, dev);
++	dev->m2m_dev = v4l2_m2m_init(&rot_m2m_ops);
++	if (IS_ERR(dev->m2m_dev)) {
++		v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
++		ret = PTR_ERR(dev->m2m_dev);
++		goto unreg_video_dev;
++	}
++
++	ret = of_reserved_mem_device_init(&pdev->dev);
++	if(ret)
++		dev_warn(&pdev->dev, "failed to init reserved mem\n");
++
++	return 0;
++
++unreg_video_dev:
++	video_unregister_device(dev->vfd);
++rel_vdev:
++	video_device_release(vfd);
++unreg_v4l2_dev:
++	v4l2_device_unregister(&dev->v4l2_dev);
++alloc_ctx_cleanup:
++	ingenic_vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
++clk_get_rollback:
++	clk_put(dev->clk);
++
++	return ret;
++}
++
++static int ingenic_rot_remove(struct platform_device *pdev)
++{
++	struct ingenic_rot_dev *dev = (struct ingenic_rot_dev *)platform_get_drvdata(pdev);
++
++	v4l2_info(&dev->v4l2_dev, "Removing " JZ_ROT_NAME);
++	v4l2_m2m_release(dev->m2m_dev);
++	video_unregister_device(dev->vfd);
++	video_device_release(dev->vfd);
++	v4l2_device_unregister(&dev->v4l2_dev);
++	ingenic_vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
++	clk_put(dev->clk);
++	return 0;
++}
++
++static const struct of_device_id ingenic_rotate_match[] = {
++	{
++		.compatible = "ingenic,x2000-rotate",
++		.data = NULL,
++	},
++	{
++		.compatible = "ingenic,m300-rotate",
++		.data = NULL,
++	},
++	{ },
++};
++
++MODULE_DEVICE_TABLE(of, ingenic_rotate_match);
++
++
++static struct platform_driver rot_pdrv = {
++	.probe		= ingenic_rot_probe,
++	.remove		= ingenic_rot_remove,
++	.driver		= {
++		.owner = THIS_MODULE,
++		.of_match_table	= of_match_ptr(ingenic_rotate_match),
++		.name = JZ_ROT_NAME,
++		.owner = THIS_MODULE,
++	},
++};
++
++module_platform_driver(rot_pdrv);
++
++MODULE_AUTHOR("clwang<chunlei.wang@ingenic.com>");
++MODULE_DESCRIPTION("X2000 rotate driver");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/media/platform/ingenic-rotate/rotate.h b/module_drivers/drivers/media/platform/ingenic-rotate/rotate.h
+new file mode 100644
+index 000000000..5fdf650f8
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-rotate/rotate.h
+@@ -0,0 +1,150 @@
++/* * drivers/media/platform/ingenic_rotate/rotate.h
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * Author:clwang<chunlei.wang@ingenic.com>
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#ifndef __ROTATER_H__
++#define __ROTATER_H__
++
++#include <linux/platform_device.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++
++#define JZ_ROT_NAME "jz-rot"
++#define ROT_DESC_NUM 1
++
++#define DEFAULT_WIDTH		(100)
++#define DEFAULT_HEIGHT		(100)
++
++#define MIN_WIDTH		(4)
++#define MIN_HEIGHT		(4)
++#define MAX_WIDTH		(2047)
++#define MAX_HEIGHT		(2047)
++
++#define MEM2MEM_CAPTURE	(1 << 0)
++#define MEM2MEM_OUTPUT	(1 << 1)
++
++//#define ROT_QCK_STOP
++//#define ROT_GEN_STOP
++
++typedef unsigned int uint32_t;
++typedef unsigned short uint16_t;
++typedef unsigned char uint8_t;
++
++typedef union frame_stop {
++	uint32_t d32;
++	struct {
++		uint32_t stop:1;
++		uint32_t reserve31_1:31;
++	} b;
++} frame_stop_t;
++
++typedef union irq_ctrl {
++	uint32_t d32;
++	struct {
++		uint32_t reserve1_0:2;
++		uint32_t eof_mask:1;
++		uint32_t sof_mask:1;
++		uint32_t reserve31_4:28;
++	} b;
++} irq_ctrl_t;
++
++struct ingenic_rot_desc {
++	uint32_t	NextCfgAddr;
++	uint32_t	SrcBufferAddr;
++	uint32_t	SrcStride;
++	frame_stop_t	FrameStop;
++	uint32_t	TargetBufferAddr;
++	uint32_t	TargetStride;
++	irq_ctrl_t	irq_ctrl;
++} __attribute__ ((aligned(8)));
++
++struct rot_fmt {
++	char	*name;
++	u32	fourcc;
++	int	depth;
++	u32	types;
++};
++
++struct rot_frm_info {
++	uint32_t	width;
++	uint32_t	height;
++
++	struct rot_fmt	*fmt;
++
++	uint32_t	bytesperline;
++	uint32_t	size;
++};
++
++struct ingenic_rot_ctx {
++	struct v4l2_fh		fh;
++	struct ingenic_rot_dev	*dev;
++	struct v4l2_m2m_ctx	*m2m_ctx;
++	struct v4l2_ctrl_handler ctrl_handler;
++	struct rot_frm_info	in;
++	struct rot_frm_info	out;
++	struct v4l2_ctrl	*ctrl_hflip;
++	struct v4l2_ctrl	*ctrl_vflip;
++	struct v4l2_ctrl	*ctrl_rot;
++	uint32_t		vflip;
++	uint32_t		hflip;
++	uint32_t		angle;
++	struct ingenic_rot_desc		*desc[ROT_DESC_NUM];
++	dma_addr_t		desc_phys[ROT_DESC_NUM];
++};
++
++struct ingenic_rot_dev {
++	struct device		*dev;
++	struct v4l2_device	v4l2_dev;
++	struct v4l2_m2m_dev	*m2m_dev;
++	struct video_device	*vfd;
++	struct mutex		mutex;
++	spinlock_t		ctrl_lock;
++	atomic_t		num_inst;
++	struct vb2_alloc_ctx	*alloc_ctx;
++	void __iomem		*regs;
++	struct clk		*clk;
++	struct ingenic_rot_ctx	*curr;
++	int irq;
++	wait_queue_head_t	irq_queue;
++#if defined(ROT_QCK_STOP) || defined(ROT_GEN_STOP)
++	struct work_struct rot_work;
++#endif
++};
++
++static inline unsigned long reg_read(struct ingenic_rot_dev *dev, int offset)
++{
++	return readl(dev->regs + offset);
++}
++
++static inline void reg_write(struct ingenic_rot_dev *dev, int offset, unsigned long val)
++{
++	writel(val, dev->regs + offset);
++}
++
++void rot_set_src_desc(struct ingenic_rot_dev *dev, dma_addr_t addr);
++void rot_set_dst_desc(struct ingenic_rot_dev *dev, dma_addr_t addr);
++void rot_set_hflip(struct ingenic_rot_dev *dev, uint32_t hflip);
++void rot_set_vflip(struct ingenic_rot_dev *dev, uint32_t vflip);
++void rot_set_angle(struct ingenic_rot_dev *dev, uint32_t angle);
++void rot_set_dst_cfg(struct ingenic_rot_dev *dev, struct rot_frm_info *out);
++void rot_set_src_cfg(struct ingenic_rot_dev *dev, struct rot_frm_info *in);
++int wait_rot_state(struct ingenic_rot_dev *dev, int32_t state, uint32_t flag);
++void dump_all(struct ingenic_rot_dev *dev);
++void dump_rot_desc_reg(struct ingenic_rot_dev *dev);
++void dump_rot_desc(struct ingenic_rot_desc *desc);
++void rot_clr_irq(struct ingenic_rot_dev *dev);
++void rot_gen_stop(struct ingenic_rot_dev *dev);
++void rot_qck_stop(struct ingenic_rot_dev *dev);
++void rot_start(struct ingenic_rot_dev *dev);
++void rot_reset(struct ingenic_rot_dev *dev);
++void rot_cpm_reset(void);
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/Kconfig b/module_drivers/drivers/media/platform/ingenic-vcodec/Kconfig
+new file mode 100644
+index 000000000..50f3106f1
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/Kconfig
+@@ -0,0 +1,16 @@
++config VIDEO_INGENIC_VCODEC
++        tristate "V4L2 driver for ingenic Video Codec"
++        depends on VIDEO_DEV && VIDEO_V4L2
++        select V4L2_MEM2MEM_DEV
++        select VIDEOBUF2_DMA_CONTIG_INGENIC
++        select VIDEOBUF2_DMA_CONTIG
++
++config INGENIC_HELIX
++	tristate "[ENC] ingenic video helix"
++	depends on VIDEO_INGENIC_VCODEC
++config INGENIC_FELIX
++	tristate "[DEC] ingenic video felix"
++	depends on VIDEO_INGENIC_VCODEC
++
++
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/Makefile b/module_drivers/drivers/media/platform/ingenic-vcodec/Makefile
+new file mode 100644
+index 000000000..3e3f2408b
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/Makefile
+@@ -0,0 +1,2 @@
++obj-y += helix/
++obj-y += felix/
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/Makefile b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/Makefile
+new file mode 100644
+index 000000000..01459285d
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/Makefile
+@@ -0,0 +1,29 @@
++
++ccflags-y += -I$(srctree)/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/
++ccflags-y += -I$(srctree)/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include
++
++ingenic_felix-y :=	felix_drv.o \
++			felix_ops.o \
++			libh264/api/jzm_h264_dec.o\
++			libh264/src/log.o	\
++			libh264/src/mem.o	\
++			libh264/src/h264_picture.o		\
++			libh264/src/golomb.o		\
++			libh264/src/h264data.o		\
++			libh264/src/h264_refs.o		\
++			libh264/src/mathtables.o		\
++			libh264/src/h2645_parse.o		\
++			libh264/src/h264_parse.o		\
++			libh264/src/h264_direct.o		\
++			libh264/src/h264_ps.o		\
++			libh264/src/h264_sei.o		\
++			libh264/src/buffer.o		\
++			libh264/src/vpu_ops.o		\
++			libh264/src/h264_slice.o		\
++			libh264/src/h264dec.o
++
++obj-$(CONFIG_INGENIC_FELIX) += ingenic_felix.o
++
++
++
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/felix_drv.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/felix_drv.c
+new file mode 100644
+index 000000000..bf865381e
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/felix_drv.c
+@@ -0,0 +1,658 @@
++/*
++ * Copyright (c) 2014 Ingenic Inc.
++ * Author: qipengzhen <aric.pzqi@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/module.h>
++#include <linux/time.h>
++#include <linux/sched.h>
++#include <linux/wait.h>
++#include <linux/of_device.h>
++#include <linux/of_reserved_mem.h>
++#include <linux/of.h>
++#include <media/v4l2-event.h>
++#include <media/v4l2-mem2mem.h>
++//#include <media/videobuf2-dma-contig.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++#include <linux/pm_runtime.h>
++#include <linux/clk.h>
++#include <linux/of_address.h>
++#include <media/ingenic_video_nr.h>
++
++#include "felix_drv.h"
++#include "felix_ops.h"
++
++#include "h264dec.h"
++
++#undef pr_debug
++#define pr_debug pr_info
++
++
++/*
++TODO: do not support multi ctx for now.
++*/
++
++static int vpu_on(struct ingenic_vdec_dev *dev);
++static int vpu_off(struct ingenic_vdec_dev *dev);
++extern struct vpu_ops ingenic_vpu_ops;
++
++static int fops_vcodec_open(struct file *file)
++{
++	struct ingenic_vdec_dev *dev = video_drvdata(file);
++	struct ingenic_vdec_ctx *ctx = NULL;
++	int ret = 0;
++
++//	printk("%s:%d sizeof(*ctx): %d, sizeof(AVCodecContext):%d, sizeof(H264Context):%d\n", __func__, __LINE__, sizeof(*ctx), sizeof(AVCodecContext), sizeof(H264Context));
++
++	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
++	if(!ctx)
++		return -ENOMEM;
++
++	ctx->avctx = kzalloc(sizeof(AVCodecContext), GFP_KERNEL);
++	if(!ctx->avctx) {
++		kfree(ctx);
++		return -ENOMEM;
++	}
++
++	ctx->h = kzalloc(sizeof(H264Context), GFP_KERNEL);
++	if(!ctx->h) {
++		kfree(ctx->avctx);
++		kfree(ctx);
++		return -ENOMEM;
++	}
++	ctx->avctx->priv_data = ctx->h;
++	//ctx->avctx->flags2 |= AV_CODEC_FLAG2_CHUNKS;
++	//ctx->avctx->debug |= FF_DEBUG_PICT_INFO;
++	ctx->h->devmem_ctx.dev = dev->dev;
++
++	ret = h264_decode_init(ctx->avctx);
++	if(ret < 0) {
++		kfree(ctx->h);
++		kfree(ctx->avctx);
++		kfree(ctx);
++		return -EINVAL;
++	}
++
++	h264_set_vpu_ops(ctx->h, ctx, &ingenic_vpu_ops);
++
++	mutex_lock(&dev->dev_mutex);
++
++	mutex_init(&ctx->lock);
++
++	if (!dev->id_counter) {
++		vpu_on(dev);
++	}
++
++	ctx->id = dev->id_counter++;
++	v4l2_fh_init(&ctx->fh, video_devdata(file));
++	file->private_data = &ctx->fh;
++	v4l2_fh_add(&ctx->fh);
++	//INIT_LIST_HEAD(&ctx->list);
++	ctx->dev = dev;
++	init_waitqueue_head(&ctx->queue);
++
++
++	ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &ingenic_vcodec_vdec_queue_init);
++	if(IS_ERR((__force void *)ctx->m2m_ctx)) {
++		ret = PTR_ERR((__force void *)ctx->m2m_ctx);
++
++		goto err_m2m_ctx_init;
++	}
++
++	ingenic_vcodec_init_default_params(ctx);
++	pr_debug("Create instance [%d]@%p m2m_ctx=%p\n",
++			ctx->id, ctx, ctx->m2m_ctx);
++
++	mutex_unlock(&dev->dev_mutex);
++
++	pr_debug("%s vcodec [%d]\n", dev_name(dev->dev), ctx->id);
++
++	return ret;
++err_m2m_ctx_init:
++	v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
++	v4l2_fh_del(&ctx->fh);
++	v4l2_fh_exit(&ctx->fh);
++	kfree(ctx->h);
++	kfree(ctx->avctx);
++	kfree(ctx);
++	mutex_unlock(&dev->dev_mutex);
++	return ret;
++}
++
++static int fops_vcodec_release(struct file *file)
++{
++
++	struct ingenic_vdec_dev *dev = video_drvdata(file);
++	struct ingenic_vdec_ctx *ctx = fh_to_ctx(file->private_data);
++
++	pr_debug("[%d] vcodec release\n", ctx->id);
++
++	mutex_lock(&dev->dev_mutex);
++
++	v4l2_fh_del(&ctx->fh);
++	v4l2_fh_exit(&ctx->fh);
++	v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
++	v4l2_m2m_ctx_release(ctx->m2m_ctx);
++
++
++	ingenic_vcodec_deinit_default_params(ctx);
++
++	h264_decode_end(ctx->avctx);
++
++	if(ctx->avctx)
++		kfree(ctx->avctx);
++
++	if(ctx->h)
++		kfree(ctx->h);
++
++	kfree(ctx);
++
++	if (!(--dev->id_counter)) {
++		vpu_off(dev);
++	}
++
++
++	mutex_unlock(&dev->dev_mutex);
++
++	return 0;
++}
++
++static unsigned int fops_vcodec_poll(struct file *file,
++				    struct poll_table_struct *wait)
++{
++	struct ingenic_vdec_dev *dev = video_drvdata(file);
++	struct ingenic_vdec_ctx *ctx = fh_to_ctx(file->private_data);
++	unsigned int ret = 0;
++
++	if(mutex_lock_interruptible(&dev->dev_mutex)) {
++		return -ERESTARTSYS;
++	}
++
++	ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
++
++	mutex_unlock(&dev->dev_mutex);
++
++	return ret;
++}
++
++static int fops_vcodec_mmap(struct file *file,
++			   struct vm_area_struct *vma)
++{
++	struct ingenic_vdec_ctx *ctx = fh_to_ctx(file->private_data);
++
++	return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
++}
++
++static const struct v4l2_file_operations ingenic_vdec_fops = {
++	.owner 		= THIS_MODULE,
++	.open		= fops_vcodec_open,
++	.release	= fops_vcodec_release,
++	.poll		= fops_vcodec_poll,
++	.unlocked_ioctl = video_ioctl2,
++	.mmap		= fops_vcodec_mmap,
++};
++
++
++#define vpu_readl(dev, offset)	\
++	readl(dev->reg_base + (offset))
++
++#define vpu_writel(dev, offset, data)	\
++	writel((data), dev->reg_base + (offset))
++
++static void inline vpu_clear_bits(struct ingenic_vdec_dev *dev, unsigned int offset, unsigned int bits)
++{
++	unsigned int val = vpu_readl(dev, offset);
++	val &= ~bits;
++	vpu_writel(dev, offset, val);
++}
++
++
++#define REG_VPU_STATUS ( *(volatile unsigned int*)0xb3200034 )
++#define REG_VPU_LOCK ( *(volatile unsigned int*)0xb329004c )
++#define REG_VPUCDR ( *(volatile unsigned int*)0xb0000030 )
++#define REG_CPM_VPU_SWRST ( *(volatile unsigned int*)0xb00000c4 )
++#define REG_VPU_TLBBASE (*(volatile unsigned int *)(0x30 + 0xb3200000))
++#define CPM_VPU_SR           (0x1<<31)
++#define CPM_VPU_STP          (0x1<<30)
++#define CPM_VPU_ACK          (0x1<<29)
++
++
++
++#define REG_VPU_GLBC      0x00000
++#define VPU_INTE_ACFGERR     (0x1<<20)
++#define VPU_INTE_TLBERR      (0x1<<18)
++#define VPU_INTE_BSERR       (0x1<<17)
++#define VPU_INTE_ENDF        (0x1<<16)
++
++#define REG_VPU_STAT      0x00034
++#define VPU_STAT_ENDF    (0x1<<0)
++#define VPU_STAT_BPF     (0x1<<1)
++#define VPU_STAT_ACFGERR (0x1<<2)
++#define VPU_STAT_TIMEOUT (0x1<<3)
++#define VPU_STAT_JPGEND  (0x1<<4)
++#define VPU_STAT_BSERR   (0x1<<7)
++
++#define VPU_STAT_TLBERR  (0x1F<<10)
++#define VPU_STAT_SLDERR  (0x1<<16)
++
++#define REG_VPU_JPGC_STAT 0xE0008
++#define JPGC_STAT_ENDF   (0x1<<31)
++
++#define REG_VPU_SDE_STAT  0x90000
++#define SDE_STAT_BSEND   (0x1<<1)
++
++#define REG_VPU_DBLK_STAT 0x70070
++#define DBLK_STAT_DOEND  (0x1<<0)
++
++#define REG_VPU_AUX_STAT  0xA0010
++#define AUX_STAT_MIRQP   (0x1<<0)
++
++static irqreturn_t ingenic_vpu_irq(int irq, void *priv)
++{
++	struct ingenic_vdec_dev *dev = (struct ingenic_vdec_dev *)priv;
++	struct ingenic_vdec_ctx *ctx = dev->curr_ctx;
++	H264Context *h = ctx->h;
++	vpu_ctx_t *vpu_ctx = &h->vpu_ctx;
++	unsigned long flags;
++
++	unsigned int vpu_stat;
++	unsigned int sde_stat;
++	int err = 0;
++
++#define check_vpu_status(STAT, fmt, args...) do {       \
++		if(vpu_stat & STAT)                     \
++		dev_err(dev->dev, fmt, ##args); 	\
++	}while(0)
++
++	spin_lock_irqsave(&dev->spinlock, flags);
++
++	vpu_stat = vpu_readl(dev, REG_SCH_STAT);
++	sde_stat = vpu_readl(dev, REG_SDE_STAT);
++
++	if(vpu_stat) {
++		if(vpu_stat & VPU_STAT_ENDF) {
++			if(vpu_stat & VPU_STAT_JPGEND) {
++				dev_dbg(dev->dev, "JPG successfully done!\n");
++				vpu_stat = vpu_readl(dev, REG_VPU_JPGC_STAT);
++				vpu_clear_bits(dev, REG_VPU_JPGC_STAT,
++						JPGC_STAT_ENDF);
++			} else {
++				dev_dbg(dev->dev, "SCH successfully done!\n");
++				vpu_clear_bits(dev, REG_VPU_SDE_STAT,
++						SDE_STAT_BSEND);
++				vpu_clear_bits(dev, REG_VPU_DBLK_STAT,
++						DBLK_STAT_DOEND);
++			}
++		} else {
++			err = 1;
++			check_vpu_status(VPU_STAT_SLDERR, "SHLD error!\n");
++			check_vpu_status(VPU_STAT_TLBERR, "TLB error! Addr is 0x%08x\n",
++					vpu_readl(dev, REG_VPU_STAT));
++			check_vpu_status(VPU_STAT_BSERR, "BS error!\n");
++			check_vpu_status(VPU_STAT_ACFGERR, "ACFG error!\n");
++			check_vpu_status(VPU_STAT_TIMEOUT, "TIMEOUT error!\n");
++			vpu_clear_bits(dev,REG_VPU_GLBC, (VPU_INTE_ACFGERR |
++						VPU_INTE_TLBERR | VPU_INTE_BSERR |
++						VPU_INTE_ENDF));
++		}
++	} else {
++		if(vpu_readl(dev,REG_VPU_AUX_STAT) & AUX_STAT_MIRQP) {
++			dev_dbg(dev->dev, "AUX successfully done!\n");
++			vpu_clear_bits(dev, REG_VPU_AUX_STAT, AUX_STAT_MIRQP);
++		} else {
++			dev_dbg(dev->dev, "illegal interrupt happened!\n");
++			err = 1;
++			return IRQ_HANDLED;
++		}
++	}
++
++	ctx->int_cond = 1;
++	vpu_ctx->error = err;
++	vpu_ctx->sch_stat = vpu_stat;
++	vpu_ctx->sde_stat = sde_stat;
++	//ctx->int_status = vpu_stat;
++	spin_unlock_irqrestore(&dev->spinlock, flags);
++
++	wake_up_interruptible(&ctx->queue);
++
++	return IRQ_HANDLED;
++}
++
++
++static void vpu_dump_regs(struct ingenic_vdec_dev *dev)
++{
++
++#if 1
++	/*SDE*/
++	printk("REG_SDE_STAT:		0x%x\n", vpu_readl(dev, REG_SDE_STAT));
++	printk("REG_SDE_CFG0:		0x%x\n", vpu_readl(dev, REG_SDE_CFG0));
++	printk("REG_SDE_CFG1:		0x%x\n", vpu_readl(dev, REG_SDE_CFG1));
++	printk("REG_SDE_CFG13:		0x%x\n", vpu_readl(dev, REG_SDE_CFG13));
++	printk("REG_SDE_CFG14:		0x%x\n", vpu_readl(dev, REG_SDE_CFG14));
++	printk("REG_DBLK_GSTA:		0x%x\n", vpu_readl(dev, REG_DBLK_GSTA));
++	printk("REG_VMAU_POS:		0x%x\n", vpu_readl(dev, REG_VMAU_POS));
++	printk("REG_SCH_STAT:		0x%x\n", vpu_readl(dev, REG_SCH_STAT));
++#endif
++}
++
++
++#define VPU_RUN_TIMEOUT_MS	(3000)
++
++#ifdef CONFIG_SOC_M200
++static int vpu_reset_m200(struct ingenic_vdec_dev *dev)
++{
++	int timeout = 0xffffff;
++
++	REG_CPM_VPU_SWRST |= CPM_VPU_STP;
++	while(!(REG_CPM_VPU_SWRST & CPM_VPU_ACK) && --timeout)
++		        ;
++
++	if(!timeout) {
++		dev_err(dev->dev,
++				"[%d:%d] wait stop ack timeout when stop VPU\n",
++				current->tgid, current->pid);
++	}
++
++	REG_CPM_VPU_SWRST = ((REG_CPM_VPU_SWRST | CPM_VPU_SR) & ~CPM_VPU_STP);
++	REG_CPM_VPU_SWRST = (REG_CPM_VPU_SWRST & ~CPM_VPU_SR & ~CPM_VPU_STP);
++	REG_VPU_LOCK = 0;
++
++	return 0;
++}
++#endif
++
++/********************************************
++  SW_RESET (VPU software reset)
++*********************************************/
++#define REG_CFGC_SW_RESET    0x00000
++#define REG_CFGC_RST         (0x1<<30)
++#define REG_CFGC_RST_CLR     (0x0<<30)
++#define REG_CFGC_EARB_STAT   0x0000d
++#define REG_CFGC_EARB_EMPT   (0x20000)
++
++static int vpu_reset_x2000(struct ingenic_vdec_dev *dev)
++{
++	int timeout = 0xffff;
++	vpu_writel(dev, REG_CFGC_SW_RESET, REG_CFGC_RST);
++	while((vpu_readl(dev, REG_CFGC_EARB_STAT) & REG_CFGC_EARB_EMPT) && --timeout);
++
++	if(!timeout) {
++		printk("vpu reset timeout!\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++static int vpu_reset(struct ingenic_vdec_dev *dev)
++{
++#ifdef CONFIG_SOC_M200
++	return vpu_reset_m200(dev);
++#else
++	return vpu_reset_x2000(dev);
++#endif
++}
++
++/*global clk on.*/
++static int vpu_on(struct ingenic_vdec_dev *dev)
++{
++	clk_prepare_enable(dev->clk_gate);
++	__asm__ __volatile__ (
++			"mfc0  $2, $16,  7   \n\t"
++			"ori   $2, $2, 0x340 \n\t"
++			"andi  $2, $2, 0x3ff \n\t"
++			"mtc0  $2, $16,  7  \n\t"
++			"nop                  \n\t");
++
++	return 0;
++}
++
++/* shutdown */
++static int vpu_off(struct ingenic_vdec_dev *dev)
++{
++	clk_disable_unprepare(dev->clk_gate);
++
++	return 0;
++}
++
++
++static int ingenic_vpu_start(void *priv)
++{
++	struct ingenic_vdec_ctx *ctx = (struct ingenic_vdec_ctx *)priv;
++	struct ingenic_vdec_dev *dev = ctx->dev;
++	H264Context *h = ctx->h;
++	vpu_ctx_t *vpu_ctx = &h->vpu_ctx;
++
++	unsigned int sch_glbc = 0;
++	unsigned int des_pa;
++	unsigned long flags;
++	int ret = 0;
++
++
++	mutex_lock(&ctx->lock);
++
++	des_pa = vpu_ctx->desc_pa;
++
++	spin_lock_irqsave(&dev->spinlock, flags);
++
++	/* 是�是将vpu_start 和 wait放在一起，更加��一些
++	 * 针对ctx �加�处�, ��curr_ctx在一次处�期间�会�生�化.
++	 * */
++	dev->curr_ctx = ctx;
++	ctx->int_cond = 0;
++
++
++	/* vpu reset ... */
++	vpu_reset(dev);
++
++	/*TODO: 如果使用tlb，此处�修改.*/
++	sch_glbc = SCH_GLBC_HIAXI | SCH_INTE_ACFGERR | SCH_INTE_BSERR | SCH_INTE_ENDF;
++		/*|SCH_INTE_ENDF | SCH_INTE_TLBERR | SCH_INTE_BSFULL;*/
++
++	vpu_writel(dev, REG_SCH_GLBC, sch_glbc);
++
++	/*trigger start.*/
++	vpu_writel(dev, REG_VDMA_TASKRG, VDMA_ACFG_DHA(des_pa) | VDMA_ACFG_RUN);
++
++	/* wait event time out ... */
++	spin_unlock_irqrestore(&dev->spinlock, flags);
++
++	ret = wait_event_interruptible_timeout(ctx->queue, ctx->int_cond, msecs_to_jiffies(VPU_RUN_TIMEOUT_MS));
++	if(!ret) {
++		pr_err("wait vpu run timeout!\n");
++		printk("efe_stat %x, sch_stat %x\n", vpu_readl(dev, REG_EFE_STAT), vpu_readl(dev, REG_SCH_STAT));
++
++		vpu_dump_regs(dev);
++		ret = -ETIMEDOUT;
++	} else if(ret == -ERESTARTSYS) {
++		pr_err("vpu interrupted by a signal!\n");
++
++	}
++
++	mutex_unlock(&ctx->lock);
++	return ret;
++}
++
++static int ingenic_vpu_wait(void *priv)
++{
++	return 0;
++}
++
++static int ingenic_vpu_stop(void *priv)
++{
++	return 0;
++}
++
++struct vpu_ops ingenic_vpu_ops = {
++	.start = ingenic_vpu_start,
++	.wait = ingenic_vpu_wait,
++	.end = ingenic_vpu_stop,
++};
++
++static int ingenic_vcodec_probe(struct platform_device *pdev)
++{
++	struct ingenic_vdec_dev *dev;
++	struct video_device *vfd;
++	int ret;
++
++	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
++	if(!dev)
++		return -ENOMEM;
++
++	dev->dev = &pdev->dev;
++	dev->plat_dev = pdev;
++
++	/*io,clk,irq*/
++
++	dev->reg_base = of_iomap(pdev->dev.of_node, 0);;
++	if(IS_ERR(dev->reg_base)) {
++		ret = -ENODEV;
++		goto err_ioremap;
++	}
++
++	/*TODO: clk pm ...*/
++	dev->irq = platform_get_irq(pdev, 0);
++	ret = devm_request_irq(&pdev->dev, dev->irq, ingenic_vpu_irq, 0, pdev->name, dev);
++	if(ret ) {
++		dev_err(&pdev->dev, "Failed to request vpu irq!\n");
++		goto err_irq;
++	}
++
++	dev->clk_gate = clk_get(&pdev->dev, "power_felix");
++	if (IS_ERR(dev->clk_gate)) {
++		ret = PTR_ERR(dev->clk_gate);
++		goto err_get_clk_gate;
++	}
++
++	spin_lock_init(&dev->spinlock);
++	mutex_init(&dev->dev_mutex);
++
++	dev->alloc_ctx = ingenic_vb2_dma_contig_init_ctx(&pdev->dev);
++	if(IS_ERR(dev->alloc_ctx)) {
++		ret = -ENOMEM;
++		goto err_ctx;
++	}
++
++	snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name), "%s", "ingenic-v4l2-felix");
++
++	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
++	if(ret) {
++		dev_err(&pdev->dev, "Failed to register v4l2_dev\n");
++		goto err_v4l2;
++	}
++
++	vfd = video_device_alloc();
++	if(!vfd) {
++		dev_err(&pdev->dev, "Failed to alloc video device!\n");
++		ret = -ENOMEM;
++		goto err_vdev;
++	}
++
++
++	vfd->fops 	= &ingenic_vdec_fops;
++	vfd->ioctl_ops 	= &ingenic_vdec_ioctl_ops;
++	vfd->release 	= video_device_release;
++	vfd->lock 	= &dev->dev_mutex;
++	vfd->v4l2_dev	= &dev->v4l2_dev;
++	vfd->vfl_dir	= VFL_DIR_M2M;
++	vfd->device_caps	= V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
++
++	snprintf(vfd->name, sizeof(vfd->name), "%s", INGENIC_VCODEC_DEC_NAME);
++
++	video_set_drvdata(vfd, dev);
++	dev->vfd = vfd;
++	platform_set_drvdata(pdev, dev);
++
++	dev->m2m_dev = v4l2_m2m_init(&ingenic_vdec_m2m_ops);
++	if(IS_ERR((__force void *)dev->m2m_dev)) {
++		dev_err(&pdev->dev, "Failed to init m2m device!\n");
++		ret = PTR_ERR((__force void *)dev->m2m_dev);
++		goto err_m2m;
++	}
++
++	dev->dec_workqueue = alloc_ordered_workqueue(INGENIC_VCODEC_DEC_NAME,
++				WQ_MEM_RECLAIM | WQ_FREEZABLE);
++	if(!dev->dec_workqueue) {
++		dev_err(&pdev->dev, "Failed to create decode workqueue\n");
++		ret = -EINVAL;
++		goto err_workq;
++	}
++
++	ret = video_register_device(vfd, VFL_TYPE_VIDEO, INGENIC_FELIX_VIDEO_NR);
++	if(ret) {
++		dev_err(&pdev->dev, "Failed to register video device!\n");
++		goto err_video_reg;
++	}
++
++	ret = of_reserved_mem_device_init(dev->dev);
++	if(ret)
++		dev_warn(&pdev->dev, "failed to init reserved mem\n");
++
++	dev_info(&pdev->dev, "h264decoder(felix) registered as /dev/video%d\n",
++	 		vfd->num);
++
++	return 0;
++err_video_reg:
++err_workq:
++err_m2m:
++err_vdev:
++err_v4l2:
++	ingenic_vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
++err_ctx:
++//err_get_clk_cgu:
++err_get_clk_gate:
++err_irq:
++err_ioremap:
++	return ret;
++}
++
++static int ingenic_vcodec_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id felix_of_match[] = {
++	{ .compatible = "ingenic,x2000-felix"},
++	{ .compatible = "ingenic,m300-felix"},
++	{},
++};
++
++static struct platform_driver ingenic_vcodec_driver = {
++	.probe = ingenic_vcodec_probe,
++	.remove = ingenic_vcodec_remove,
++	.driver = {
++		.name = INGENIC_VCODEC_DEC_NAME,
++		.of_match_table = felix_of_match,
++	},
++};
++
++static int __init felix_device_init(void)
++{
++	platform_driver_register(&ingenic_vcodec_driver);
++	return 0;
++}
++
++static void __exit felix_device_exit(void)
++{
++	platform_driver_unregister(&ingenic_vcodec_driver);
++}
++
++module_init(felix_device_init);
++module_exit(felix_device_exit);
++
++
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Ingenic Video Codec v4l2 encoder driver.");
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/felix_drv.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/felix_drv.h
+new file mode 100644
+index 000000000..39e352671
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/felix_drv.h
+@@ -0,0 +1,159 @@
++#ifndef __INGENIC_FELIX_DRV_H__
++#define __INGENIC_FELIX_DRV_H__
++
++#include <linux/platform_device.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ioctl.h>
++#include <media/videobuf2-core.h>
++
++#include "avcodec.h"
++#include "frame.h"
++#include "h264dec.h"
++
++
++#define INGENIC_VCODEC_DEC_NAME "felix-vdec"
++#define INGENIC_VCODEC_MAX_PLANES	3
++
++enum ingenic_fmt_type {
++	INGENIC_FMT_FRAME = 0,
++	INGENIC_FMT_DEC = 1,
++};
++
++enum felix_raw_format {
++	FELIX_TILE_MODE = 0,
++	FELIX_420P_MODE = 4,	/* not support */
++	FELIX_NV12_MODE = 8,
++	FELIX_NV21_MODE = 12,	/* not support */
++	FELIX_FORMAT_NONE,
++};
++
++struct ingenic_video_fmt {
++	u32 fourcc;
++	enum ingenic_fmt_type type;
++	u32 num_planes;
++	enum felix_raw_format format;
++};
++
++struct ingenic_vcodec_framesizes {
++	u32 fourcc;
++	struct v4l2_frmsize_stepwise stepwise;
++};
++
++enum ingenic_vcodec_state {
++	INGENIC_STATE_IDLE = 0,
++	INGENIC_STATE_HEADER,
++	INGENIC_STATE_RUNNING,
++	INGENIC_STATE_ABORT,
++};
++
++
++/* private vcode buf related to each vb2, TODO: will implement in future. */
++/*
++ *	这里的大�必须是struct v4l2_m2m_buffer.
++ * */
++struct ingenic_vcodec_buf {
++	struct vb2_v4l2_buffer vb;
++	struct list_head list;	//struct v4l2_m2m_buffer
++
++	/*下��是自己�有的数�结构.*/
++	AVFrame frame;
++	int is_last_frame;	/*End of Stream.*/
++};
++
++enum ingenic_q_type {
++	INGENIC_Q_DATA_SRC = 0,
++	INGENIC_Q_DATA_DST = 1,
++};
++
++struct ingenic_vcodec_q_data {
++	unsigned int    visible_width;
++	unsigned int    visible_height;
++	unsigned int    coded_width;
++	unsigned int    coded_height;
++	enum v4l2_field field;
++	unsigned int    bytesperline[INGENIC_VCODEC_MAX_PLANES];
++	unsigned int    sizeimage[INGENIC_VCODEC_MAX_PLANES];
++	unsigned int    real_sizeimage[INGENIC_VCODEC_MAX_PLANES];
++	struct ingenic_video_fmt    *fmt;
++};
++
++/*  vpu hw ctx ?? */
++
++
++
++
++/* Each open creates a ctx ? */
++struct ingenic_vdec_ctx {
++
++	struct ingenic_vdec_dev *dev;
++	struct v4l2_fh fh;
++	struct v4l2_m2m_ctx *m2m_ctx;
++
++	struct v4l2_ctrl_handler ctrl_hdl;
++
++	int id;	/* used for debug ?*/
++
++	struct ingenic_vcodec_q_data q_data[2];
++
++	wait_queue_head_t queue;
++	int output_stopped;
++	int capture_stopped;
++
++	enum ingenic_vcodec_state state;
++
++	enum v4l2_colorspace colorspace;
++	struct work_struct decode_work;
++
++	struct ingenic_vcodec_buf *empty_flush_buf;
++
++	int int_cond;
++	struct mutex lock;
++
++	AVCodecContext *avctx;
++	H264Context *h;
++
++};
++
++
++struct ingenic_vdec_dev {
++	struct v4l2_device v4l2_dev;
++	struct video_device *vfd;
++	struct device *dev;
++
++	struct v4l2_m2m_dev *m2m_dev;
++	struct platform_device *plat_dev;
++
++	struct mutex dev_mutex;
++
++	/* TODO: add workqueue*/
++	struct workqueue_struct *dec_workqueue;
++
++	spinlock_t spinlock;
++
++	struct ingenic_vdec_ctx *curr_ctx;
++	struct vb2_dc_conf *alloc_ctx;
++
++	int id_counter;
++
++	void __iomem *reg_base;
++	int irq;
++	struct clk *clk_gate;
++	struct clk *clk;
++};
++
++
++/* -----------------------------------helpler-------------------------------------*/
++static inline struct ingenic_vdec_ctx *fh_to_ctx(struct v4l2_fh *fh)
++{
++	return container_of(fh, struct ingenic_vdec_ctx, fh);
++}
++
++static inline struct ingenic_vdec_ctx *ctrl_to_ctx(struct v4l2_ctrl *ctrl)
++{
++	return container_of(ctrl->handler, struct ingenic_vdec_ctx, ctrl_hdl);
++}
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/felix_ops.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/felix_ops.c
+new file mode 100644
+index 000000000..d7e038d28
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/felix_ops.c
+@@ -0,0 +1,1235 @@
++/*
++*	Copyright (c) 2014 Ingenic Inc.
++*	Author: qipengzhen <aric.pzqi@ingenic.com>
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License version 2 as
++* published by the Free Software Foundation.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++* GNU General Public License for more details.
++*
++*/
++
++#include <linux/module.h>
++#include <media/v4l2-event.h>
++#include <media/v4l2-mem2mem.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++
++#include <linux/slab.h>
++#include <linux/crc32.h>
++
++#include "felix_drv.h"
++#include "felix_ops.h"
++
++#undef pr_debug
++#define pr_debug pr_info
++
++#define fh_to_ctx(__fh) container_of(__fh, struct ingenic_vdec_ctx, fh)
++
++#define pixelformat_str(a) a >> 0, a >> 8, a >> 16, a >> 24
++
++
++#define INGENIC_VDEC_MIN_W	160U
++#define INGENIC_VDEC_MIN_H	120U
++#define INGENIC_VDEC_MAX_W	2560U
++#define INGENIC_VDEC_MAX_H	2048U
++
++
++/*#define MAX_SUPPORT_FRAME_BUFFERS 16*/
++
++#define MAX_SUPPORT_FRAME_BUFFERS 6
++
++#define av_frame_to_vcode_buf(f)	\
++		container_of(f, struct ingenic_vcodec_buf, frame) \
++
++
++static unsigned int max_frame_buffers = MAX_SUPPORT_FRAME_BUFFERS;
++module_param(max_frame_buffers, uint, S_IRUGO | S_IWUSR);
++
++static struct ingenic_video_fmt ingenic_video_formats[] = {
++	/* out */
++	{
++		.fourcc = V4L2_PIX_FMT_H264,
++		.type = INGENIC_FMT_DEC,
++		.num_planes = 1,
++		.format = FELIX_FORMAT_NONE,
++	},
++#ifndef CONFIG_SOC_M200
++	/* cap */
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.type = INGENIC_FMT_FRAME,
++		.num_planes = 2,
++		.format = FELIX_NV12_MODE,
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.type = INGENIC_FMT_FRAME,
++		.num_planes = 2,
++		.format = FELIX_NV21_MODE,
++	},
++#endif
++	{
++		.fourcc = V4L2_PIX_FMT_JZ420B,
++		.type   = INGENIC_FMT_FRAME,
++		.num_planes = 2,
++		.format = FELIX_TILE_MODE,
++	}
++};
++
++#define NUM_FORMATS		ARRAY_SIZE(ingenic_video_formats)
++#define OUT_FMT_IDX		0
++#define NUM_OUT_FORMATS		1
++#define CAP_FMT_IDX 		(OUT_FMT_IDX + NUM_OUT_FORMATS)
++
++static const struct ingenic_vcodec_framesizes ingenic_vcodec_framesizes[] = {
++	{
++		.fourcc = V4L2_PIX_FMT_H264,
++		.stepwise = { INGENIC_VDEC_MIN_W, INGENIC_VDEC_MAX_W, 2,
++			      INGENIC_VDEC_MIN_H, INGENIC_VDEC_MAX_H, 2},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.stepwise = { INGENIC_VDEC_MIN_W, INGENIC_VDEC_MAX_W, 2,
++			      INGENIC_VDEC_MIN_H, INGENIC_VDEC_MAX_H, 2},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.stepwise = { INGENIC_VDEC_MIN_W, INGENIC_VDEC_MAX_W, 2,
++			      INGENIC_VDEC_MIN_H, INGENIC_VDEC_MAX_H, 2},
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_JZ420B,
++		.stepwise = { INGENIC_VDEC_MIN_W, INGENIC_VDEC_MAX_W, 2,
++			      INGENIC_VDEC_MIN_H, INGENIC_VDEC_MAX_H, 2},
++	},
++};
++
++#define NUM_SUPPORTED_FRAMESIZE		ARRAY_SIZE(ingenic_vcodec_framesizes)
++
++static int vidioc_querycap(struct file *file, void *priv,
++			struct v4l2_capability *cap)
++{
++	strlcpy(cap->driver, INGENIC_VCODEC_DEC_NAME, sizeof(cap->driver));
++	strlcpy(cap->bus_info, "vpu-felix", sizeof(cap->bus_info));
++	strlcpy(cap->card, "vpu-felix", sizeof(cap->card));
++
++	cap->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M_MPLANE;
++	cap->capabilities = cap->device_caps | V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING |
++                    V4L2_CAP_VIDEO_CAPTURE_MPLANE |
++                    V4L2_CAP_VIDEO_OUTPUT_MPLANE |
++		    V4L2_CAP_DEVICE_CAPS;
++
++	return 0;
++}
++
++
++static int vidioc_enum_fmt(struct v4l2_fmtdesc *f, bool output_queue)
++{
++	struct ingenic_video_fmt *fmt;
++	int i,j = 0;
++
++
++	for(i = 0; i < NUM_FORMATS; i++) {
++		if(output_queue && ingenic_video_formats[i].type != INGENIC_FMT_DEC)
++			continue;
++		if(!output_queue && ingenic_video_formats[i].type != INGENIC_FMT_FRAME)
++			continue;
++
++		if(j == f->index) {
++			fmt = &ingenic_video_formats[i];
++			f->pixelformat = fmt->fourcc;
++			memset(f->reserved, 0, sizeof(f->reserved));
++			return 0;
++		}
++
++		j++;
++	}
++
++	return -EINVAL;
++}
++
++static int vidioc_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
++					struct v4l2_fmtdesc *f)
++{
++	return vidioc_enum_fmt(f, false);
++}
++static int vidioc_enum_fmt_vid_out_mplane(struct file *file, void *priv,
++					struct v4l2_fmtdesc *f)
++{
++	return vidioc_enum_fmt(f, true);
++}
++
++static int vidioc_try_fmt(struct v4l2_format *f, struct ingenic_video_fmt *fmt)
++{
++	struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
++	int i;
++
++	pix_fmt_mp->field = V4L2_FIELD_NONE;
++
++	if(f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
++		pix_fmt_mp->num_planes = 1;
++		pix_fmt_mp->plane_fmt[0].bytesperline = 0;
++	} else if(f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE){
++		int tmp_w, tmp_h;
++
++		pix_fmt_mp->height = clamp(pix_fmt_mp->height,
++					INGENIC_VDEC_MIN_H,
++					INGENIC_VDEC_MAX_H);
++		pix_fmt_mp->width = clamp(pix_fmt_mp->width,
++					INGENIC_VDEC_MIN_W,
++					INGENIC_VDEC_MAX_W);
++
++		tmp_w = pix_fmt_mp->width;
++		tmp_h = pix_fmt_mp->height;
++
++
++#if 0
++		v4l_bound_align_image(&pix_fmt_mp->width,
++					INGENIC_VDEC_MIN_W,
++					INGENIC_VDEC_MAX_W, 7,	//128Bytes align
++					&pix_fmt_mp->height,
++					INGENIC_VDEC_MIN_H,
++					INGENIC_VDEC_MAX_H, 0, 0);
++		/*v4l2_bound_align_image will only round near, will round_down width.*/
++#endif
++		tmp_w = ALIGN(pix_fmt_mp->width, 128);
++		tmp_h = pix_fmt_mp->height;
++		pr_debug("tmp_w %d tmp_h %d, w %d h %d\n",
++				tmp_w, tmp_h,
++				pix_fmt_mp->width,
++				pix_fmt_mp->height);
++
++
++		pix_fmt_mp->num_planes = fmt->num_planes;
++		pix_fmt_mp->plane_fmt[0].sizeimage =
++				tmp_w * tmp_h;
++
++		pix_fmt_mp->plane_fmt[0].bytesperline = tmp_w;
++
++		if(pix_fmt_mp->num_planes == 2) {
++			pix_fmt_mp->plane_fmt[1].sizeimage =
++				tmp_w * tmp_h / 2;
++			pix_fmt_mp->plane_fmt[2].sizeimage = 0;
++
++			pix_fmt_mp->plane_fmt[1].bytesperline = tmp_w;
++			pix_fmt_mp->plane_fmt[2].bytesperline = 0;
++		} else if(pix_fmt_mp->num_planes == 3) {
++			pix_fmt_mp->plane_fmt[1].sizeimage =
++			pix_fmt_mp->plane_fmt[2].sizeimage =
++				(tmp_w * tmp_h) / 4;
++
++			pix_fmt_mp->plane_fmt[1].bytesperline =
++			pix_fmt_mp->plane_fmt[2].bytesperline =
++				tmp_w / 2;
++		}
++	}
++
++	for(i = 0; i < pix_fmt_mp->num_planes; i++) {
++		memset(&(pix_fmt_mp->plane_fmt[i].reserved[0]), 0x0,
++				sizeof(pix_fmt_mp->plane_fmt[0].reserved));
++	}
++
++//	pix_fmt_mp->flags = 0;
++
++	memset(&pix_fmt_mp->reserved, 0x0,
++			sizeof(pix_fmt_mp->reserved));
++
++	return 0;
++}
++
++static struct ingenic_vcodec_q_data *ingenic_vcodec_get_q_data(struct ingenic_vdec_ctx *ctx,
++							enum v4l2_buf_type type)
++{
++	if(V4L2_TYPE_IS_OUTPUT(type))
++		return &ctx->q_data[INGENIC_Q_DATA_SRC];
++
++	return &ctx->q_data[INGENIC_Q_DATA_DST];
++}
++
++static struct ingenic_video_fmt *ingenic_vcodec_find_format(struct v4l2_format *f)
++{
++	struct ingenic_video_fmt *fmt;
++	int i;
++
++	for(i = 0; i < NUM_FORMATS; i++) {
++		fmt = &ingenic_video_formats[i];
++		if(fmt->fourcc == f->fmt.pix_mp.pixelformat)
++			return fmt;
++	}
++
++	return NULL;
++}
++
++static int vidioc_s_fmt_cap(struct file *file, void *priv,
++			struct v4l2_format *f)
++{
++
++	struct ingenic_vdec_ctx *ctx = fh_to_ctx(priv);
++	struct vb2_queue *vq;
++	struct ingenic_vcodec_q_data *q_data;
++	struct ingenic_video_fmt *fmt;
++	unsigned int pixelformat;
++	int i, ret;
++
++	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
++	if(!vq) {
++		pr_err("failed to get cap vq !\n");
++		return -EINVAL;
++	}
++
++	if(vb2_is_busy(vq)) {
++		pr_err("cap vq is busy!\n");
++		return -EINVAL;
++	}
++
++	q_data = ingenic_vcodec_get_q_data(ctx, f->type);
++	if(!q_data) {
++		pr_err("fail to get cap q data!\n");
++		return -EINVAL;
++	}
++
++
++	fmt = ingenic_vcodec_find_format(f);
++	if(!fmt) {
++		/* change to the first support cap format.*/
++		f->fmt.pix.pixelformat = ingenic_video_formats[CAP_FMT_IDX].fourcc;
++		/* if buf type MPLANE, use pix_mp ..*/
++		f->fmt.pix_mp.pixelformat = ingenic_video_formats[CAP_FMT_IDX].fourcc;
++		fmt = ingenic_vcodec_find_format(f);
++	}
++
++
++	q_data->fmt = fmt;
++
++	ret = vidioc_try_fmt(f, q_data->fmt);
++	if(ret)
++		return ret;
++
++	q_data->coded_width = ALIGN(f->fmt.pix_mp.width, 128);
++	q_data->coded_height = ALIGN(f->fmt.pix_mp.height, 16);
++	q_data->visible_width = f->fmt.pix_mp.width;
++	q_data->visible_height = f->fmt.pix_mp.height;
++	q_data->field = f->fmt.pix_mp.field;
++
++	for(i = 0; i < f->fmt.pix_mp.num_planes; i++) {
++		struct v4l2_plane_pix_format *plane_fmt;
++
++		plane_fmt = &f->fmt.pix_mp.plane_fmt[i];
++		q_data->bytesperline[i] = plane_fmt->bytesperline;
++		q_data->sizeimage[i] = plane_fmt->sizeimage;
++		q_data->real_sizeimage[i] = q_data->sizeimage[i] / q_data->visible_height * ALIGN(q_data->visible_height, 16);
++	}
++
++	pixelformat = f->fmt.pix_mp.pixelformat;
++	switch(pixelformat) {
++		case V4L2_PIX_FMT_NV12:
++			h264_set_output_format(ctx->h, VPU_FORMAT_NV12, q_data->coded_width, q_data->coded_height);
++			break;
++		case V4L2_PIX_FMT_NV21:
++			h264_set_output_format(ctx->h, VPU_FORMAT_NV21, q_data->coded_width, q_data->coded_height);
++			break;
++		case V4L2_PIX_FMT_JZ420B:
++			h264_set_output_format(ctx->h, VPU_FORMAT_TILE420, q_data->coded_width, q_data->coded_height);
++			break;
++		default:
++			pr_err("Unsupported pix fmt: %x\n", pixelformat);
++			ret = -EINVAL;
++			break;
++	}
++
++
++	return ret;
++}
++
++static int vidioc_s_fmt_out(struct file *file, void *priv,
++			struct v4l2_format *f)
++{
++	struct ingenic_vdec_ctx *ctx = fh_to_ctx(priv);
++	struct vb2_queue *vq;
++	struct ingenic_vcodec_q_data *q_data;
++	struct ingenic_video_fmt *fmt;
++	struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
++	int ret, i;
++
++	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
++	if(!vq) {
++		pr_err("fail to get out vq!\n");
++		return -EINVAL;
++	}
++	if(vb2_is_busy(vq)) {
++		pr_err("out vq is busy!\n");
++		return -EINVAL;
++	}
++
++	q_data = ingenic_vcodec_get_q_data(ctx, f->type);
++	if(!q_data) {
++		pr_err("failed to get out q_data!\n");
++		return -EINVAL;
++	}
++
++
++	fmt = ingenic_vcodec_find_format(f);
++	if(!fmt) {
++		/* change to the first support cap format.*/
++		f->fmt.pix.pixelformat = ingenic_video_formats[OUT_FMT_IDX].fourcc;
++		f->fmt.pix_mp.pixelformat = ingenic_video_formats[OUT_FMT_IDX].fourcc;
++		fmt = ingenic_vcodec_find_format(f);
++	}
++
++
++	pix_fmt_mp->height = clamp(pix_fmt_mp->height,
++			INGENIC_VDEC_MIN_H,
++			INGENIC_VDEC_MAX_H);
++	pix_fmt_mp->width = clamp(pix_fmt_mp->width,
++			INGENIC_VDEC_MIN_W,
++			INGENIC_VDEC_MAX_W);
++
++	q_data->visible_width = f->fmt.pix_mp.width;
++	q_data->visible_height = f->fmt.pix_mp.height;
++	q_data->fmt = fmt;
++	ret = vidioc_try_fmt(f, q_data->fmt);
++	if (ret)
++		return ret;
++
++	q_data->coded_width = ALIGN(f->fmt.pix_mp.width, 128);
++	q_data->coded_height = ALIGN(f->fmt.pix_mp.height, 16);
++
++	q_data->field = f->fmt.pix_mp.field;
++	ctx->colorspace = f->fmt.pix_mp.colorspace;
++	//ctx->ycbcr_enc = f->fmt.pix_mp.ycbcr_enc;
++	//ctx->quantization = f->fmt.pix_mp.quantization;
++	//ctx->xfer_func = f->fmt.pix_mp.xfer_func;
++
++
++	for (i = 0; i < f->fmt.pix_mp.num_planes; i++) {
++		struct v4l2_plane_pix_format *plane_fmt;
++
++		plane_fmt = &f->fmt.pix_mp.plane_fmt[i];
++		q_data->bytesperline[i] = plane_fmt->bytesperline;
++		q_data->sizeimage[i] = plane_fmt->sizeimage;
++		q_data->real_sizeimage[i] = plane_fmt->sizeimage;
++	}
++
++	{ /* set capture as same as output, necessary for gstream v4l2videodec. */
++		struct v4l2_format fmt;
++		memset(&fmt, 0, sizeof(struct v4l2_format));
++		fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
++		fmt.fmt.pix_mp.width = f->fmt.pix_mp.width;
++		fmt.fmt.pix_mp.height = f->fmt.pix_mp.height;
++		vidioc_s_fmt_cap(file, priv, &fmt);
++	}
++
++
++
++	return 0;
++}
++
++static int vidioc_g_fmt(struct file *file, void *priv,
++			struct v4l2_format *f)
++{
++
++	struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
++	struct ingenic_vdec_ctx *ctx = fh_to_ctx(priv);
++	struct vb2_queue *vq;
++	struct ingenic_vcodec_q_data *q_data;
++	int i;
++
++	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
++	if (!vq)
++		return -EINVAL;
++
++	q_data = ingenic_vcodec_get_q_data(ctx, f->type);
++
++	if (q_data->fmt == NULL)
++		return -EINVAL;
++
++	pix->width = q_data->visible_width;
++	pix->height = q_data->visible_height;
++	pix->pixelformat = q_data->fmt->fourcc;
++	pix->field = q_data->field;
++	pix->num_planes = q_data->fmt->num_planes;
++	for (i = 0; i < pix->num_planes; i++) {
++		pix->plane_fmt[i].bytesperline = q_data->bytesperline[i];
++		pix->plane_fmt[i].sizeimage = q_data->sizeimage[i];
++		memset(&(pix->plane_fmt[i].reserved[0]), 0x0,
++				sizeof(pix->plane_fmt[i].reserved));
++	}
++
++//	pix->flags = 0;
++	pix->colorspace = ctx->colorspace;
++//	pix->ycbcr_enc = ctx->ycbcr_enc;
++//	pix->quantization = ctx->quantization;
++//	pix->xfer_func = ctx->xfer_func;
++
++	return 0;
++}
++
++static int vidioc_try_fmt_vid_cap_mplane(struct file *file, void *priv,
++			struct v4l2_format *f)
++{
++	struct ingenic_video_fmt *fmt;
++	struct ingenic_vdec_ctx *ctx = fh_to_ctx(priv);
++
++	fmt = ingenic_vcodec_find_format(f);
++	if (!fmt) {
++		f->fmt.pix.pixelformat = ingenic_video_formats[CAP_FMT_IDX].fourcc;
++		f->fmt.pix_mp.pixelformat = ingenic_video_formats[CAP_FMT_IDX].fourcc;
++		fmt = ingenic_vcodec_find_format(f);
++	}
++	f->fmt.pix_mp.colorspace = ctx->colorspace;
++	//f->fmt.pix_mp.ycbcr_enc = ctx->ycbcr_enc;
++	//f->fmt.pix_mp.quantization = ctx->quantization;
++	//f->fmt.pix_mp.xfer_func = ctx->xfer_func;
++
++	return vidioc_try_fmt(f, fmt);
++}
++
++static int vidioc_try_fmt_vid_out_mplane(struct file *file, void *priv,
++			struct v4l2_format *f)
++{
++
++	struct ingenic_video_fmt *fmt;
++
++	fmt = ingenic_vcodec_find_format(f);
++	if (!fmt) {
++		f->fmt.pix.pixelformat = ingenic_video_formats[OUT_FMT_IDX].fourcc;
++		f->fmt.pix_mp.pixelformat = ingenic_video_formats[OUT_FMT_IDX].fourcc;
++		fmt = ingenic_vcodec_find_format(f);
++	}
++	if (!f->fmt.pix_mp.colorspace) {
++		f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_REC709;
++	//	f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
++	//	f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT;
++	//	f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT;
++	}
++
++	return vidioc_try_fmt(f, fmt);
++}
++
++static int vidioc_reqbufs(struct file *file, void *priv,
++			struct v4l2_requestbuffers *reqbufs)
++{
++	struct ingenic_vdec_ctx *ctx = fh_to_ctx(priv);
++
++	return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
++}
++
++static int vidioc_querybuf(struct file *file, void *priv,
++			struct v4l2_buffer *buf)
++{
++	struct ingenic_vdec_ctx *ctx = fh_to_ctx(priv);
++
++	return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
++
++}
++
++static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
++{
++	struct ingenic_vdec_ctx *ctx = fh_to_ctx(priv);
++	int ret = 0;
++
++	if(ctx->state == INGENIC_STATE_ABORT) {
++		return -EIO;
++	}
++
++	ret = v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
++
++#if 0
++	{
++		struct vb2_queue *vq;
++		vq = v4l2_m2m_get_vq(ctx->m2m_ctx, buf->type);
++		printk("---%s, %d, index: %d, type:%d [%s], state:%d\n",
++				__func__, __LINE__, buf->index, buf->type, buf->type == 10 ? "OUTPUT":"CAPTUR", vq->bufs[buf->index]->state);
++	}
++#endif
++	return ret;
++}
++
++static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
++{
++	struct ingenic_vdec_ctx *ctx = fh_to_ctx(priv);
++	int ret = 0;
++
++	ret = v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
++	if(buf->flags & V4L2_BUF_FLAG_LAST)
++		buf->flags &= ~V4L2_BUF_FLAG_LAST;
++#if 0
++	{
++		struct vb2_queue *vq;
++		vq = v4l2_m2m_get_vq(ctx->m2m_ctx, buf->type);
++		printk("---%s, %d, index: %d, type:%d [%s], state:%d\n",
++				__func__, __LINE__, buf->index, buf->type, buf->type == 10 ? "OUTPUT":"CAPTUR", vq->bufs[buf->index]->state);
++	}
++#endif
++	return ret;
++}
++
++static int vidioc_expbuf(struct file *file, void *priv,
++	struct v4l2_exportbuffer *eb)
++{
++
++	struct ingenic_vdec_ctx *ctx = fh_to_ctx(priv);
++
++	return v4l2_m2m_expbuf(file, ctx->m2m_ctx, eb);
++}
++
++static int vidioc_create_bufs(struct file *file, void *priv,
++			      struct v4l2_create_buffers *create)
++{
++	struct ingenic_vdec_ctx *ctx = fh_to_ctx(priv);
++	struct ingenic_vcodec_q_data *q_data = NULL;
++	struct ingenic_video_fmt *fmt = NULL;
++
++	q_data = ingenic_vcodec_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
++	fmt = q_data->fmt;
++
++	if(fmt->fourcc == V4L2_PIX_FMT_JZ420B && create->count < 2)
++		create->count = 2;
++
++	return v4l2_m2m_create_bufs(file, ctx->m2m_ctx, create);
++}
++static int vidioc_prepare_buf(struct file *file, void *fh, struct v4l2_buffer *b)
++{
++
++	return 0;
++}
++
++static int vidioc_streamon(struct file *file, void *priv,
++			enum v4l2_buf_type type)
++{
++	struct ingenic_vdec_ctx *ctx = fh_to_ctx(priv);
++
++	return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
++}
++
++static int vidioc_streamoff(struct file *file, void *priv,
++			enum v4l2_buf_type type)
++{
++	struct ingenic_vdec_ctx *ctx = fh_to_ctx(priv);
++
++	return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
++}
++
++
++static int vidioc_g_selection(struct file *file, void *priv,
++			struct v4l2_selection *s)
++{
++	struct ingenic_vdec_ctx *ctx = fh_to_ctx(priv);
++	struct ingenic_vcodec_q_data *q_data;
++
++	q_data = ingenic_vcodec_get_q_data(ctx, s->type);
++
++	s->r.left = 0;
++	s->r.top = 0;
++	s->r.width = q_data->visible_width;
++	s->r.height = q_data->visible_height;
++
++	return 0;
++}
++
++static int vidioc_s_selection(struct file *file, void *priv,
++			struct v4l2_selection *s)
++{
++	return 0;
++}
++
++static int vidioc_enum_framesizes(struct file *file, void *fh,
++				struct v4l2_frmsizeenum *fsize)
++{
++	int i = 0;
++	if(fsize->index != 0)
++		return -EINVAL;
++
++	for(i = 0; i < NUM_SUPPORTED_FRAMESIZE; i++) {
++		if(fsize->pixel_format != ingenic_vcodec_framesizes[i].fourcc)
++			continue;
++
++		fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
++		fsize->stepwise = ingenic_vcodec_framesizes[i].stepwise;
++		return 0;
++	}
++
++	return -EINVAL;
++}
++
++static int vidioc_enum_frameintervals(struct file *file, void *priv,
++			    struct v4l2_frmivalenum *fe)
++{
++	if (fe->index)
++		return -EINVAL;
++
++	fe->type = V4L2_FRMIVAL_TYPE_STEPWISE;
++
++	fe->stepwise.min.numerator = 1;
++	fe->stepwise.min.denominator = 0;
++
++	fe->stepwise.max.numerator = 1001;
++	fe->stepwise.max.denominator = 80000;
++
++	fe->stepwise.step.numerator = 1;
++	fe->stepwise.step.denominator = 1;
++	return 0;
++}
++
++static int vidioc_try_decoder_cmd (struct file *file, void *priv,
++		struct v4l2_decoder_cmd *cmd)
++{
++	switch (cmd->cmd) {
++		case V4L2_DEC_CMD_STOP:
++		case V4L2_DEC_CMD_START:
++			if (cmd->flags != 0) {
++				pr_err("cmd->flags=%u", cmd->flags);
++				return -EINVAL;
++			}
++			break;
++		default:
++			return -EINVAL;
++	}
++
++
++	return 0;
++}
++static int vidioc_decoder_cmd (struct file *file, void *priv,
++		struct v4l2_decoder_cmd *cmd)
++{
++	struct ingenic_vdec_ctx *ctx = fh_to_ctx(priv);
++	struct vb2_queue *src_vq, *dst_vq;
++	int ret = 0;
++
++	ret = vidioc_try_decoder_cmd(file, priv, cmd);
++	if(ret < 0) {
++		return ret;
++	}
++
++	dst_vq = v4l2_m2m_get_vq(ctx->m2m_ctx,
++			V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
++	switch(cmd->cmd) {
++		case V4L2_DEC_CMD_STOP:
++			src_vq = v4l2_m2m_get_vq(ctx->m2m_ctx,
++					V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
++			if (!vb2_is_streaming(src_vq)) {
++				pr_info("Output stream is off. No need to flush.");
++				return 0;
++			}
++			if (!vb2_is_streaming(dst_vq)) {
++				pr_info("Capture stream is off. No need to flush.");
++				return 0;
++			}
++
++
++			v4l2_m2m_buf_queue(ctx->m2m_ctx, &ctx->empty_flush_buf->vb);
++
++			v4l2_m2m_try_schedule(ctx->m2m_ctx);
++			break;
++		case V4L2_DEC_CMD_START:
++			vb2_clear_last_buffer_dequeued(dst_vq);
++			break;
++
++		default:
++			return -EINVAL;
++
++	}
++
++	return 0;
++}
++
++
++
++const struct v4l2_ioctl_ops ingenic_vdec_ioctl_ops = {
++
++	/* VIDIOC_QUERYCAP handler */
++	.vidioc_querycap		= vidioc_querycap,
++
++	/* VIDIOC_ENUM_FMT handlers */
++	.vidioc_enum_fmt_vid_cap 	= vidioc_enum_fmt_vid_cap_mplane,
++	.vidioc_enum_fmt_vid_out 	= vidioc_enum_fmt_vid_out_mplane,
++
++	/* VIDIOC_G_FMT handlers */
++	.vidioc_g_fmt_vid_cap_mplane	= vidioc_g_fmt,
++	.vidioc_g_fmt_vid_out_mplane	= vidioc_g_fmt,
++
++	/* VIDIOC_S_FMT handlers */
++	.vidioc_s_fmt_vid_cap_mplane	= vidioc_s_fmt_cap,
++	.vidioc_s_fmt_vid_out_mplane	= vidioc_s_fmt_out,
++
++	/* VIDIOC_TRY_FMT handlers */
++	.vidioc_try_fmt_vid_cap_mplane	= vidioc_try_fmt_vid_cap_mplane,
++	.vidioc_try_fmt_vid_out_mplane	= vidioc_try_fmt_vid_out_mplane,
++
++	/* Buffer handlers */
++	.vidioc_reqbufs			= vidioc_reqbufs,
++	.vidioc_querybuf		= vidioc_querybuf,
++	.vidioc_qbuf			= vidioc_qbuf,
++	.vidioc_dqbuf			= vidioc_dqbuf,
++	.vidioc_expbuf			= vidioc_expbuf,
++
++	.vidioc_create_bufs		= vidioc_create_bufs,
++	.vidioc_prepare_buf		= vidioc_prepare_buf,
++
++	/* Stream on/off */
++	.vidioc_streamon		= vidioc_streamon,
++	.vidioc_streamoff		= vidioc_streamoff,
++
++	/* Crop ioctls */
++	.vidioc_g_selection		= vidioc_g_selection,
++	.vidioc_s_selection		= vidioc_s_selection,
++
++	.vidioc_decoder_cmd		= vidioc_decoder_cmd,
++	.vidioc_try_decoder_cmd		= vidioc_try_decoder_cmd,
++
++	.vidioc_enum_framesizes		= vidioc_enum_framesizes,
++
++	.vidioc_enum_frameintervals = vidioc_enum_frameintervals,
++	.vidioc_subscribe_event		= v4l2_ctrl_subscribe_event,
++	.vidioc_unsubscribe_event	= v4l2_event_unsubscribe,
++
++};
++
++
++static void __maybe_unused dump_vb2_buffer(struct vb2_buffer *vb2, const char *str)
++{
++	int i;
++	printk("======dump vb2: %s=========\n", str);
++	printk("vb2->num_planes:        %d\n", vb2->num_planes);
++	printk("vb2->index:    %d\n", vb2->index);
++	printk("vb2->type:     %d\n", vb2->type);
++	//printk("vb2->v4l2_buf.sequence: %d\n", vb2->v4l2_buf.sequence);
++	//printk("vb2->v4l2_buf.length:   %d\n", vb2->v4l2_buf.length);
++	for(i = 0; i < vb2->num_planes; i++) {
++		printk("planes@	%d : \n", i);
++		printk("\tbyteused: 	%d\n", vb2->planes[i].bytesused);
++		printk("\tlength: 	%d\n", vb2->planes[i].length);
++
++		printk("\tvaddr: 0x%p\n", vb2_plane_vaddr(vb2, i));
++		printk("\tpaddr: 0x%08x\n", ingenic_vb2_dma_contig_plane_dma_addr(vb2, i));
++
++		/* data from vaddr to vaddr + length */
++		print_hex_dump(KERN_INFO, "data@ ", DUMP_PREFIX_ADDRESS, 16, 1, vb2_plane_vaddr(vb2, i), 128, true);
++
++		printk("----------------------------------------\n");
++	}
++}
++
++static void ingenic_vdec_worker(struct work_struct *work)
++{
++	struct ingenic_vdec_ctx *ctx = container_of(work, struct ingenic_vdec_ctx, decode_work);
++	struct vb2_v4l2_buffer *src_buf, *dst_buf;
++	struct ingenic_vcodec_buf *vcodec_src_buf;
++	AVCodecContext *avctx = ctx->avctx;
++	H264Context *h = ctx->h;
++	AVFrame *f = NULL;
++	AVPacket avpkt;
++	int got_frame = 0;
++	int ret = 0;
++	int decode_error = 0;
++	int eos = 0;
++
++
++	src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
++	if(src_buf == NULL) {
++		pr_info("src_buf empty\n");
++		v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->m2m_ctx);
++		return;
++	}
++	dst_buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
++	if(dst_buf == NULL) {
++		pr_info("dst_buf empty\n");
++		v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->m2m_ctx);
++		return;
++	}
++
++	//dump_vb2_buffer(src_buf, "src_buf");
++
++	if(src_buf->vb2_buf.planes[0].bytesused > src_buf->vb2_buf.planes[0].length) {
++		printk("**** Error, src_buf out of range [%d > %d]\n", src_buf->vb2_buf.planes[0].bytesused, src_buf->vb2_buf.planes[0].length);
++	}
++
++
++	vcodec_src_buf = container_of(src_buf, struct ingenic_vcodec_buf, vb);
++
++	/*如果当�处�的是empty buf, �用处�解�，直接从队列中删除src_buf.*/
++	if((vcodec_src_buf->is_last_frame == true) ||
++		(src_buf->vb2_buf.planes[0].bytesused == 0)) {
++
++		/*Got Empty stream, End of stream.*/
++		eos = 1;
++		v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
++
++		/*将vpu残留的中间buffer全部还给内核.*/
++		goto done;
++	}
++
++	src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
++	dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
++
++
++	avpkt.size = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
++	avpkt.data_pa = ingenic_vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
++	if (src_buf->vb2_buf.memory == VB2_MEMORY_USERPTR)
++		avpkt.data = phys_to_virt(avpkt.data_pa);
++	else
++		avpkt.data = vb2_plane_vaddr(&src_buf->vb2_buf, 0);
++
++	if(dst_buf) {
++		struct ingenic_vcodec_buf *buf = container_of(dst_buf,
++				struct ingenic_vcodec_buf, vb);
++
++		dst_buf->vb2_buf.timestamp = src_buf->vb2_buf.timestamp;
++		dst_buf->timecode = src_buf->timecode;
++		dst_buf->sequence = src_buf->sequence;
++
++		h264_enqueue_frame(h, &buf->frame);
++	}
++
++	ret = h264_decode_frame(avctx, NULL, &got_frame, &avpkt);
++	if(ret < 0) {
++		decode_error = 1;
++	}
++
++	if(got_frame) {
++		/*drain display frame*/
++		f = h264_dequeue_frame(h);
++		if(f) {
++			struct ingenic_vcodec_buf *done_buf = av_frame_to_vcode_buf(f);
++			//printk("------done_buf: %x done frame f: %x-----buf->index:%d, f->index: %d\n", done_buf, f, done_buf->vb.v4l2_buf.index, f->index);
++
++
++			vb2_set_plane_payload(&done_buf->vb.vb2_buf, 0, f->buf[0]->size);
++			vb2_set_plane_payload(&done_buf->vb.vb2_buf, 1, f->buf[1]->size);
++			//dump_vb2_buffer(&done_buf->vb, "dst_buf");
++			v4l2_m2m_buf_done(&done_buf->vb, VB2_BUF_STATE_DONE);
++		}
++	}
++
++	v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
++
++done:
++	if((decode_error) || (eos)) {
++
++		if(eos) {
++			while((dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx))) {
++				dst_buf->vb2_buf.planes[0].bytesused = 0;
++				dst_buf->flags |= V4L2_BUF_FLAG_DONE;
++				dst_buf->flags |= V4L2_BUF_FLAG_LAST;
++				dst_buf->vb2_buf.timestamp = ktime_get();
++				/*��两个的时间戳�一样.*/
++				dst_buf->vb2_buf.timestamp = ktime_add_ns(dst_buf->vb2_buf.timestamp, 10);
++				/* work around, return buffer to userspace with 0 byteused. */
++				v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
++			}
++		}
++
++		/* retrain all enqueued frame, do not stop decode.*/
++		while((f = h264_get_queued_frame(h))) {
++			struct ingenic_vcodec_buf *err_buf = av_frame_to_vcode_buf(f);
++			vb2_set_plane_payload(&err_buf->vb.vb2_buf, 0, 0);
++			vb2_set_plane_payload(&err_buf->vb.vb2_buf, 1, 0);
++			v4l2_m2m_buf_done(&err_buf->vb, VB2_BUF_STATE_ERROR);
++		}
++
++		while((f = h264_dequeue_frame(h))) {
++			struct ingenic_vcodec_buf *err_buf = av_frame_to_vcode_buf(f);
++			vb2_set_plane_payload(&err_buf->vb.vb2_buf, 0, 0);
++			vb2_set_plane_payload(&err_buf->vb.vb2_buf, 1, 0);
++			v4l2_m2m_buf_done(&err_buf->vb, VB2_BUF_STATE_ERROR);
++		}
++	}
++
++	v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->m2m_ctx);
++}
++
++static void m2mops_vdec_device_run(void *priv)
++{
++	struct ingenic_vdec_ctx *ctx = priv;
++	struct ingenic_vdec_dev *dev = ctx->dev;
++
++	queue_work(dev->dec_workqueue, &ctx->decode_work);
++}
++
++static int m2mops_vdec_job_ready(void *m2m_priv)
++{
++	struct ingenic_vdec_ctx *ctx = m2m_priv;
++
++	if(ctx->state == INGENIC_STATE_ABORT || ctx->state == INGENIC_STATE_IDLE) {
++		pr_info("job not ready, ctx->state %d\n", ctx->state);
++		return 0;
++	}
++
++	return 1;
++}
++
++
++static void m2mops_vdec_job_abort(void *priv)
++{
++	struct ingenic_vdec_ctx *ctx = priv;
++	ctx->state = INGENIC_STATE_ABORT;
++}
++
++const struct v4l2_m2m_ops ingenic_vdec_m2m_ops = {
++	.device_run		= m2mops_vdec_device_run,
++	.job_ready		= m2mops_vdec_job_ready,
++	.job_abort		= m2mops_vdec_job_abort,
++};
++
++static int vb2ops_vcodec_queue_setup(struct vb2_queue *vq,
++				unsigned int *nbuffers,
++				unsigned int *nplanes,
++				unsigned int sizes[],
++				struct device *alloc_ctxs[])
++{
++	struct ingenic_vdec_ctx *ctx = vb2_get_drv_priv(vq);
++	struct ingenic_vcodec_q_data *q_data;
++	int i;
++
++	q_data = ingenic_vcodec_get_q_data(ctx, vq->type);
++	if(q_data == NULL)
++		return -EINVAL;
++
++	if(*nplanes) {
++		for(i = 0; i < *nplanes; i++) {
++			sizes[i] = q_data->real_sizeimage[i];
++			if(sizes[i] < q_data->real_sizeimage[i]) {
++				return -EINVAL;
++			}
++		}
++	} else {
++		*nplanes = q_data->fmt->num_planes;
++		for (i = 0; i < *nplanes; i++) {
++			sizes[i] = q_data->real_sizeimage[i];
++			alloc_ctxs[i] = ctx->dev->dev;
++		}
++	}
++
++	if(*nbuffers > max_frame_buffers)
++		*nbuffers = max_frame_buffers;
++
++	return 0;
++}
++
++static int vb2ops_vcodec_buf_prepare(struct vb2_buffer *vb)
++{
++	struct ingenic_vdec_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
++	struct ingenic_vcodec_q_data *q_data;
++	int i;
++
++	q_data = ingenic_vcodec_get_q_data(ctx, vb->vb2_queue->type);
++
++	for(i = 0; i < q_data->fmt->num_planes; i++) {
++		if(vb2_plane_size(vb, i) > q_data->real_sizeimage[i]) {
++
++			pr_err("Failed to prepare buf!\n");
++
++			return -EINVAL;
++		}
++	}
++
++	return 0;
++}
++
++
++static int vb2ops_vcodec_buf_init(struct vb2_buffer *vb)
++{
++	struct ingenic_vcodec_buf *buf = container_of(to_vb2_v4l2_buffer(vb),
++                                struct ingenic_vcodec_buf, vb);
++
++	int i;
++	AVFrame *f = &buf->frame;
++
++	f->index = vb->index;
++	for(i = 0; i < vb->num_planes; i++) {
++		f->buf[i] = av_buffer_create(vb2_plane_vaddr(vb, i),
++					ingenic_vb2_dma_contig_plane_dma_addr(vb, i),
++					vb2_plane_size(vb, i)
++					);
++	}
++	return 0;
++}
++static void vb2ops_vcodec_buf_cleanup(struct vb2_buffer *vb)
++{
++	struct ingenic_vcodec_buf *buf = container_of(to_vb2_v4l2_buffer(vb),
++                                struct ingenic_vcodec_buf, vb);
++	int i;
++	AVFrame *f = &buf->frame;
++
++	for(i = 0; i < vb->num_planes; i++) {
++		av_buffer_del(f->buf[i]);
++	}
++}
++
++static void vb2ops_vcodec_buf_queue(struct vb2_buffer *vb)
++{
++	struct ingenic_vdec_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
++	v4l2_m2m_buf_queue(ctx->m2m_ctx, to_vb2_v4l2_buffer(vb));
++	return;
++}
++
++static void vb2ops_vcodec_buf_finish(struct vb2_buffer *vb)
++{
++	return;
++}
++
++
++static int vb2ops_vcodec_start_streaming(struct vb2_queue *q, unsigned int count)
++{
++	struct ingenic_vdec_ctx *ctx = vb2_get_drv_priv(q);
++	struct ingenic_vcodec_q_data *q_data_src;
++	struct ingenic_vcodec_q_data *q_data_dst;
++
++	if(V4L2_TYPE_IS_OUTPUT(q->type)) {
++		ctx->output_stopped = 0;
++	} else {
++		ctx->capture_stopped = 0;
++	}
++
++	if(ctx->output_stopped  || ctx->capture_stopped)
++		return 0;
++
++	q_data_src = ingenic_vcodec_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
++	q_data_dst = ingenic_vcodec_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
++
++	ctx->state = INGENIC_STATE_RUNNING;
++	return 0;
++}
++
++static void vb2ops_vcodec_stop_streaming(struct vb2_queue *q)
++{
++
++	struct ingenic_vdec_ctx *ctx = vb2_get_drv_priv(q);
++	struct vb2_v4l2_buffer *src_buf, *dst_buf;
++	H264Context *h = ctx->h;
++	AVFrame *f = NULL;
++
++	if(q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
++
++		while((dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx))) {
++			dst_buf->vb2_buf.planes[0].bytesused = 0;
++			dst_buf->flags |= V4L2_BUF_FLAG_DONE;
++			dst_buf->vb2_buf.timestamp = ktime_get();
++			/*��两个的时间戳�一样.*/
++			dst_buf->vb2_buf.timestamp = ktime_add_ns(dst_buf->vb2_buf.timestamp, 10);
++			/* work around, return buffer to userspace with 0 byteused. */
++			v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
++		}
++
++		while((f = h264_get_queued_frame(h))) {
++			struct ingenic_vcodec_buf *err_buf = av_frame_to_vcode_buf(f);
++			vb2_set_plane_payload(&err_buf->vb.vb2_buf, 0, 0);
++			vb2_set_plane_payload(&err_buf->vb.vb2_buf, 1, 0);
++			v4l2_m2m_buf_done(&err_buf->vb, VB2_BUF_STATE_DONE);
++		}
++
++		while((f = h264_dequeue_frame(h))) {
++			struct ingenic_vcodec_buf *err_buf = av_frame_to_vcode_buf(f);
++			vb2_set_plane_payload(&err_buf->vb.vb2_buf, 0, 0);
++			vb2_set_plane_payload(&err_buf->vb.vb2_buf, 1, 0);
++			v4l2_m2m_buf_done(&err_buf->vb, VB2_BUF_STATE_DONE);
++		}
++
++	} else {
++		while((src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx))) {
++			v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
++		}
++	}
++
++	if(q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
++		ctx->capture_stopped = 1;
++	else
++		ctx->output_stopped = 1;
++
++	if((ctx->capture_stopped && ctx->output_stopped) == 0) {
++		return;
++	}
++
++	ctx->state = INGENIC_STATE_IDLE;
++
++	return;
++}
++
++static const struct vb2_ops ingenic_vcodec_vb2_ops = {
++	.queue_setup		= vb2ops_vcodec_queue_setup,
++	.buf_prepare		= vb2ops_vcodec_buf_prepare,
++	.buf_init		= vb2ops_vcodec_buf_init,
++	.buf_cleanup		= vb2ops_vcodec_buf_cleanup,
++	.buf_queue		= vb2ops_vcodec_buf_queue,
++	.buf_finish		= vb2ops_vcodec_buf_finish,
++	.wait_prepare		= vb2_ops_wait_prepare,
++	.wait_finish		= vb2_ops_wait_finish,
++	.start_streaming	= vb2ops_vcodec_start_streaming,
++	.stop_streaming		= vb2ops_vcodec_stop_streaming,
++};
++
++int ingenic_vcodec_vdec_queue_init(void *priv, struct vb2_queue *src_vq,
++	struct vb2_queue *dst_vq)
++{
++	struct ingenic_vdec_ctx *ctx = priv;
++	int ret = 0;
++
++	src_vq->type		= V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
++	src_vq->io_modes	= VB2_DMABUF | VB2_MMAP | VB2_USERPTR;
++	src_vq->drv_priv	= ctx;
++	src_vq->buf_struct_size	= sizeof(struct ingenic_vcodec_buf);
++	src_vq->ops		= &ingenic_vcodec_vb2_ops;
++	src_vq->mem_ops		= &ingenic_vb2_dma_contig_memops;
++	src_vq->lock		= &ctx->dev->dev_mutex;
++	src_vq->timestamp_flags  = V4L2_BUF_FLAG_TIMESTAMP_COPY;
++	src_vq->dev		= ctx->dev->dev;
++
++	ret = vb2_queue_init(src_vq);
++	if(ret)
++		return ret;
++
++
++	dst_vq->type		= V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
++	dst_vq->io_modes	= VB2_DMABUF | VB2_MMAP | VB2_USERPTR;
++	dst_vq->drv_priv	= ctx;
++	dst_vq->buf_struct_size	= sizeof(struct ingenic_vcodec_buf);
++	dst_vq->ops		= &ingenic_vcodec_vb2_ops;
++	dst_vq->mem_ops		= &ingenic_vb2_dma_contig_memops;
++	dst_vq->lock		= &ctx->dev->dev_mutex;
++	dst_vq->timestamp_flags  = V4L2_BUF_FLAG_TIMESTAMP_COPY;
++	dst_vq->dev		= ctx->dev->dev;
++
++	ret = vb2_queue_init(dst_vq);
++	if(ret) {
++		vb2_queue_release(src_vq);
++	}
++
++	return ret;
++}
++
++
++int ingenic_vcodec_init_default_params(struct ingenic_vdec_ctx *ctx)
++{
++	struct vb2_queue *src_vq;
++	int ret = 0;
++	ctx->capture_stopped = 1;
++	ctx->output_stopped = 1;
++	ctx->state = INGENIC_STATE_IDLE;
++	INIT_WORK(&ctx->decode_work, ingenic_vdec_worker);
++
++	src_vq = v4l2_m2m_get_vq(ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
++
++	ctx->empty_flush_buf = kzalloc(sizeof(struct ingenic_vcodec_buf), GFP_KERNEL);
++	if(!ctx->empty_flush_buf) {
++		pr_err("failed to alloc empty_flush_buf\n");
++		return -ENOMEM;
++	}
++
++	ctx->empty_flush_buf->vb.vb2_buf.vb2_queue = src_vq;
++	ctx->empty_flush_buf->is_last_frame = true;
++
++
++	return ret;
++}
++
++int ingenic_vcodec_deinit_default_params(struct ingenic_vdec_ctx *ctx)
++{
++
++	kfree(ctx->empty_flush_buf);
++
++	return 0;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/felix_ops.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/felix_ops.h
+new file mode 100644
+index 000000000..26099956c
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/felix_ops.h
+@@ -0,0 +1,15 @@
++#ifndef __FELIX_OPS_H__
++#define __FELIX_OPS_H__
++
++
++extern const struct v4l2_ioctl_ops ingenic_vdec_ioctl_ops;
++extern const struct v4l2_m2m_ops ingenic_vdec_m2m_ops;
++
++int ingenic_vcodec_vdec_queue_init(void *priv, struct vb2_queue *src_vq,
++	struct vb2_queue *dst_vq);
++
++int ingenic_vcodec_init_default_params(struct ingenic_vdec_ctx *ctx);
++
++int ingenic_vcodec_deinit_default_params(struct ingenic_vdec_ctx *ctx);
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/Makefile b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/Makefile
+new file mode 100644
+index 000000000..f2bf4c329
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/Makefile
+@@ -0,0 +1,25 @@
++ifneq ($(KERNELRELEASE),)
++obj-y += api/jzm_h264_dec.o
++
++obj-y += src/
++
++else
++#KDIR := "/home1/pzqi/Manhatton-halley2-v2.0-release/kernel/"
++KDIR := "/home/boysic/work/dorado/platform/kernel"
++EXTRA_CFLAGS := -I`pwd` -I`pwd`/include
++all:
++	$(MAKE) -C $(KDIR) M=`pwd` modules EXTRA_CFLAGS+=$(EXTRA_CFLAGS)
++
++clean:
++	rm -f libavcodec/api/.*.cmd
++	rm -f libavcodec/api/*.o
++	rm -f libavcodec/.*.cmd
++	rm -f libavcodec/*.mod.c
++	rm -f libavcodec/*.order
++	rm -f libavcodec/*.o
++	rm -f libavcodec/*.ko
++	rm -f libavutil/.*.cmd
++	rm -f libavutil/.*.o
++	rm -f libavutil/*.o
++endif
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/api/jzm_h264_dec.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/api/jzm_h264_dec.c
+new file mode 100644
+index 000000000..958d4ec2e
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/api/jzm_h264_dec.c
+@@ -0,0 +1,1123 @@
++#ifndef _JZM_H264_API_C_
++#define _JZM_H264_API_C_
++
++#include "jzm_h264_dec.h"
++
++__place_k0_data__ unsigned lps_comb[128]={
++  0xefcfaffe,0xefcfafff,0xe2c4a6fe,0xe2c4a6ff,0xd7ba9dfe,0xd7ba9dff,0xccb195f4,0xccb195f5,
++  0xc2a88de6,0xc2a88de7,0xb89f86dc,0xb89f86dd,0xae977fd0,0xae977fd1,0xa58f79c6,0xa58f79c7,
++  0x9d8873bc,0x9d8873bd,0x95816db2,0x95816db3,0x8d7a67a8,0x8d7a67a9,0x867462a0,0x867462a1,
++  0x7f6e5d98,0x7f6e5d99,0x79685890,0x79685891,0x73635488,0x73635489,0x6d5e4f82,0x6d5e4f83,
++  0x67594b7a,0x67594b7b,0x62554774,0x62554775,0x5d50446e,0x5d50446f,0x584c4068,0x584c4069,
++  0x54483d64,0x54483d65,0x4f443a5e,0x4f443a5f,0x4b41375a,0x4b41375b,0x473e3454,0x473e3455,
++  0x443a3150,0x443a3151,0x40372f4c,0x40372f4d,0x3d352c48,0x3d352c49,0x3a322a44,0x3a322a45,
++  0x372f2840,0x372f2841,0x342d263e,0x342d263f,0x312a243a,0x312a243b,0x2f282238,0x2f282239,
++  0x2c262034,0x2c262035,0x2a241e32,0x2a241e33,0x28221d2e,0x28221d2f,0x26201b2c,0x26201b2d,
++  0x241f1a2a,0x241f1a2b,0x221d1928,0x221d1929,0x201c1726,0x201c1727,0x1e1a1624,0x1e1a1625,
++  0x1d191522,0x1d191523,0x1b181420,0x1b181421,0x1a16131e,0x1a16131f,0x1815121c,0x1815121d,
++  0x1714111a,0x1714111b,0x1613101a,0x1613101b,0x15120f18,0x15120f19,0x14110e16,0x14110e17,
++  0x13100d16,0x13100d17,0x120f0d14,0x120f0d15,0x110e0c14,0x110e0c15,0x100e0b12,0x100e0b13,
++  0xf0d0b12,0xf0d0b13,0xe0c0a10,0xe0c0a11,0xd0b0a10,0xd0b0a11,0xd0b090e,0xd0b090f,0xc0a080e,
++  0xc0a080f,0xb0a080c,0xb0a080d,0xb09080c,0xb09080d,0xa09070c,0xa09070d,0xa08070a,0xa08070b,
++  0x908060a,0x908060b,0x807060a,0x807060b,0x1010102,0x1010103
++};
++
++__place_k0_data__ struct SDE_VLC_STA sde_vlc2_sta[7] = {
++  {0  , 128, 6}, // vlc_tables_coeff_token_table_0
++  {128, 116, 5}, // vlc_tables_coeff_token_table_1
++  {256, 104, 6}, // vlc_tables_coeff_token_table_2
++  {384,  64, 6}, // vlc_tables_coeff_token_table_3
++  {512,  70, 6}, // vlc_tables_chroma_dc_coeff_token_table
++  {640,  74, 6}, // vlc_tables_total_zeros_table_0
++  {768,  96, 6}, // vlc_tables_run7_table
++};
++__place_k0_data__ unsigned short sde_vlc2_table[7][128]={
++  { // 0
++    0xa020, 0x887c, 0x806c, 0x200f, 0x100a, 0x100a, 0x100a, 0x100a,
++    0x0805, 0x0805, 0x0805, 0x0805, 0x0805, 0x0805, 0x0805, 0x0805,
++    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 32
++    0xa040, 0x9070, 0x8078, 0x807a, 0x2023, 0x201a, 0x2015, 0x2010,
++    0x181f, 0x181f, 0x1816, 0x1816, 0x1811, 0x1811, 0x180c, 0x180c,
++    0x101b, 0x101b, 0x101b, 0x101b, 0x1012, 0x1012, 0x1012, 0x1012,
++    0x100d, 0x100d, 0x100d, 0x100d, 0x1008, 0x1008, 0x1008, 0x1008, // 64
++    0x4001, 0x2035, 0x8060, 0x8062, 0x8064, 0x8066, 0x8068, 0x806a,
++    0x203b, 0x2036, 0x2031, 0x2030, 0x2037, 0x2032, 0x202d, 0x202c,
++    0x1833, 0x1833, 0x182e, 0x182e, 0x1829, 0x1829, 0x1828, 0x1828,
++    0x182f, 0x182f, 0x182a, 0x182a, 0x1825, 0x1825, 0x1824, 0x1824, // 96
++    0x0040, 0x0042, 0x0041, 0x003c, 0x0043, 0x003e, 0x003d, 0x0038, // 104
++    0x003f, 0x003a, 0x0039, 0x0034, 0x0009, 0x0004, 0x4000, 0x4000, // 112
++    0x1020, 0x1026, 0x1021, 0x101c, 0x102b, 0x1022, 0x101d, 0x1018, // 120
++    0x0027, 0x001e, 0x0019, 0x0014, 0x0817, 0x080e, 0x0013, 0x0013, // 128
++  },
++  { // 1
++    0xa020, 0x8868, 0x806c, 0x806e, 0x8070, 0x8072, 0x2017, 0x2009,
++    0x1813, 0x1813, 0x180f, 0x180f, 0x100a, 0x100a, 0x100a, 0x100a,
++    0x0805, 0x0805, 0x0805, 0x0805, 0x0805, 0x0805, 0x0805, 0x0805,
++    0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800,
++    0x9840, 0x9050, 0x8858, 0x885c, 0x8060, 0x8062, 0x8064, 0x8066,
++    0x1827, 0x1827, 0x181e, 0x181e, 0x181d, 0x181d, 0x1818, 0x1818,
++    0x1014, 0x1014, 0x1014, 0x1014, 0x101a, 0x101a, 0x101a, 0x101a,
++    0x1019, 0x1019, 0x1019, 0x1019, 0x1010, 0x1010, 0x1010, 0x1010,
++    0x4001, 0x4001, 0x103f, 0x103f, 0x1843, 0x1842, 0x1841, 0x1840,
++    0x183d, 0x183c, 0x183e, 0x1839, 0x103a, 0x103a, 0x1038, 0x1038,
++    0x103b, 0x1036, 0x1035, 0x1034, 0x1037, 0x1032, 0x1031, 0x1030,
++    0x082c, 0x082e, 0x082d, 0x0828, 0x0833, 0x082a, 0x0829, 0x0824,
++    0x002f, 0x0026, 0x0025, 0x0020, 0x002b, 0x0022, 0x0021, 0x001c,
++    0x0823, 0x0816, 0x0815, 0x080c, 0x001f, 0x0012, 0x0011, 0x0008,
++    0x001b, 0x000e, 0x000d, 0x0004,
++  },
++  { // 2
++    0x9840, 0x9050, 0x8858, 0x885c, 0x8060, 0x8062, 0x8064, 0x8066,
++    0x280c, 0x281e, 0x281d, 0x2808, 0x2827, 0x281a, 0x2819, 0x2804,
++    0x2015, 0x2015, 0x2016, 0x2016, 0x2011, 0x2011, 0x2012, 0x2012,
++    0x200d, 0x200d, 0x2023, 0x2023, 0x200e, 0x200e, 0x2009, 0x2009,
++    0x181f, 0x181f, 0x181f, 0x181f, 0x181b, 0x181b, 0x181b, 0x181b,
++    0x1817, 0x1817, 0x1817, 0x1817, 0x1813, 0x1813, 0x1813, 0x1813,
++    0x180f, 0x180f, 0x180f, 0x180f, 0x180a, 0x180a, 0x180a, 0x180a,
++    0x1805, 0x1805, 0x1805, 0x1805, 0x1800, 0x1800, 0x1800, 0x1800,
++    0x4001, 0x1840, 0x1843, 0x1842, 0x1841, 0x183c, 0x183f, 0x183e,
++    0x183d, 0x1838, 0x183b, 0x183a, 0x1839, 0x1834, 0x1035, 0x1035,
++    0x1030, 0x1036, 0x1031, 0x102c, 0x1037, 0x1032, 0x102d, 0x1028,
++    0x0833, 0x082e, 0x0829, 0x0824, 0x082f, 0x082a, 0x0825, 0x0820,
++    0x001c, 0x0018, 0x0026, 0x0014, 0x002b, 0x0022, 0x0021, 0x0010,
++  },
++  { // 3
++    0x2804, 0x2805, 0x4001, 0x2800, 0x2808, 0x2809, 0x280a, 0x4001,
++    0x280c, 0x280d, 0x280e, 0x280f, 0x2810, 0x2811, 0x2812, 0x2813,
++    0x2814, 0x2815, 0x2816, 0x2817, 0x2818, 0x2819, 0x281a, 0x281b,
++    0x281c, 0x281d, 0x281e, 0x281f, 0x2820, 0x2821, 0x2822, 0x2823,
++    0x2824, 0x2825, 0x2826, 0x2827, 0x2828, 0x2829, 0x282a, 0x282b,
++    0x282c, 0x282d, 0x282e, 0x282f, 0x2830, 0x2831, 0x2832, 0x2833,
++    0x2834, 0x2835, 0x2836, 0x2837, 0x2838, 0x2839, 0x283a, 0x283b,
++    0x283c, 0x283d, 0x283e, 0x283f, 0x2840, 0x2841, 0x2842, 0x2843,
++  },
++  { // 4
++    0x8840, 0x8044, 0x2810, 0x280c, 0x2808, 0x280f, 0x2809, 0x2804,
++    0x100a, 0x100a, 0x100a, 0x100a, 0x100a, 0x100a, 0x100a, 0x100a,
++    0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800,
++    0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800,
++    0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
++    0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
++    0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
++    0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
++    0x0013, 0x0013, 0x0812, 0x0811, 0x000e, 0x000d,
++  },
++  {
++    0x9040, 0x8048, 0x2808, 0x2807, 0x2006, 0x2006, 0x2005, 0x2005,
++    0x1804, 0x1804, 0x1804, 0x1804, 0x1803, 0x1803, 0x1803, 0x1803,
++    0x1002, 0x1002, 0x1002, 0x1002, 0x1002, 0x1002, 0x1002, 0x1002,
++    0x1001, 0x1001, 0x1001, 0x1001, 0x1001, 0x1001, 0x1001, 0x1001,
++    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++    0x4001, 0x100f, 0x100e, 0x100d, 0x080c, 0x080c, 0x080b, 0x080b,
++    0x000a, 0x0009,
++  },
++  {
++    0xa040, 0x2809, 0x2008, 0x2008, 0x1807, 0x1807, 0x1807, 0x1807,
++    0x1006, 0x1006, 0x1006, 0x1006, 0x1006, 0x1006, 0x1006, 0x1006,
++    0x1005, 0x1005, 0x1005, 0x1005, 0x1005, 0x1005, 0x1005, 0x1005,
++    0x1004, 0x1004, 0x1004, 0x1004, 0x1004, 0x1004, 0x1004, 0x1004,
++    0x1003, 0x1003, 0x1003, 0x1003, 0x1003, 0x1003, 0x1003, 0x1003,
++    0x1002, 0x1002, 0x1002, 0x1002, 0x1002, 0x1002, 0x1002, 0x1002,
++    0x1001, 0x1001, 0x1001, 0x1001, 0x1001, 0x1001, 0x1001, 0x1001,
++    0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000,
++    0x4001, 0x200e, 0x180d, 0x180d, 0x100c, 0x100c, 0x100c, 0x100c,
++    0x080b, 0x080b, 0x080b, 0x080b, 0x080b, 0x080b, 0x080b, 0x080b,
++    0x000a, 0x000a, 0x000a, 0x000a, 0x000a, 0x000a, 0x000a, 0x000a,
++    0x000a, 0x000a, 0x000a, 0x000a, 0x000a, 0x000a, 0x000a, 0x000a,
++  },
++};
++
++__place_k0_data__ char cabac_context_init_I[460][2] =
++{
++    /* 0 - 10 */
++    { 20, -15 }, {  2, 54 },  {  3,  74 }, { 20, -15 },
++    {  2,  54 }, {  3, 74 },  { -28,127 }, { -23, 104 },
++    { -6,  53 }, { -1, 54 },  {  7,  51 },
++
++    /* 11 - 23 unsused for I */
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },
++
++    /* 24- 39 */
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++
++    /* 40 - 53 */
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },
++
++    /* 54 - 59 */
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },
++
++    /* 60 - 69 */
++    { 0, 41 },   { 0, 63 },   { 0, 63 },     { 0, 63 },
++    { -9, 83 },  { 4, 86 },   { 0, 97 },     { -7, 72 },
++    { 13, 41 },  { 3, 62 },
++
++    /* 70 -> 87 */
++    { 0, 11 },   { 1, 55 },   { 0, 69 },     { -17, 127 },
++    { -13, 102 },{ 0, 82 },   { -7, 74 },    { -21, 107 },
++    { -27, 127 },{ -31, 127 },{ -24, 127 },  { -18, 95 },
++    { -27, 127 },{ -21, 114 },{ -30, 127 },  { -17, 123 },
++    { -12, 115 },{ -16, 122 },
++
++    /* 88 -> 104 */
++    { -11, 115 },{ -12, 63 }, { -2, 68 },    { -15, 84 },
++    { -13, 104 },{ -3, 70 },  { -8, 93 },    { -10, 90 },
++    { -30, 127 },{ -1, 74 },  { -6, 97 },    { -7, 91 },
++    { -20, 127 },{ -4, 56 },  { -5, 82 },    { -7, 76 },
++    { -22, 125 },
++
++    /* 105 -> 135 */
++    { -7, 93 },  { -11, 87 }, { -3, 77 },    { -5, 71 },
++    { -4, 63 },  { -4, 68 },  { -12, 84 },   { -7, 62 },
++    { -7, 65 },  { 8, 61 },   { 5, 56 },     { -2, 66 },
++    { 1, 64 },   { 0, 61 },   { -2, 78 },    { 1, 50 },
++    { 7, 52 },   { 10, 35 },  { 0, 44 },     { 11, 38 },
++    { 1, 45 },   { 0, 46 },   { 5, 44 },     { 31, 17 },
++    { 1, 51 },   { 7, 50 },   { 28, 19 },    { 16, 33 },
++    { 14, 62 },  { -13, 108 },{ -15, 100 },
++
++    /* 136 -> 165 */
++    { -13, 101 },{ -13, 91 }, { -12, 94 },   { -10, 88 },
++    { -16, 84 }, { -10, 86 }, { -7, 83 },    { -13, 87 },
++    { -19, 94 }, { 1, 70 },   { 0, 72 },     { -5, 74 },
++    { 18, 59 },  { -8, 102 }, { -15, 100 },  { 0, 95 },
++    { -4, 75 },  { 2, 72 },   { -11, 75 },   { -3, 71 },
++    { 15, 46 },  { -13, 69 }, { 0, 62 },     { 0, 65 },
++    { 21, 37 },  { -15, 72 }, { 9, 57 },     { 16, 54 },
++    { 0, 62 },   { 12, 72 },
++
++    /* 166 -> 196 */
++    { 24, 0 },   { 15, 9 },   { 8, 25 },     { 13, 18 },
++    { 15, 9 },   { 13, 19 },  { 10, 37 },    { 12, 18 },
++    { 6, 29 },   { 20, 33 },  { 15, 30 },    { 4, 45 },
++    { 1, 58 },   { 0, 62 },   { 7, 61 },     { 12, 38 },
++    { 11, 45 },  { 15, 39 },  { 11, 42 },    { 13, 44 },
++    { 16, 45 },  { 12, 41 },  { 10, 49 },    { 30, 34 },
++    { 18, 42 },  { 10, 55 },  { 17, 51 },    { 17, 46 },
++    { 0, 89 },   { 26, -19 }, { 22, -17 },
++
++    /* 197 -> 226 */
++    { 26, -17 }, { 30, -25 }, { 28, -20 },   { 33, -23 },
++    { 37, -27 }, { 33, -23 }, { 40, -28 },   { 38, -17 },
++    { 33, -11 }, { 40, -15 }, { 41, -6 },    { 38, 1 },
++    { 41, 17 },  { 30, -6 },  { 27, 3 },     { 26, 22 },
++    { 37, -16 }, { 35, -4 },  { 38, -8 },    { 38, -3 },
++    { 37, 3 },   { 38, 5 },   { 42, 0 },     { 35, 16 },
++    { 39, 22 },  { 14, 48 },  { 27, 37 },    { 21, 60 },
++    { 12, 68 },  { 2, 97 },
++
++    /* 227 -> 251 */
++    { -3, 71 },  { -6, 42 },  { -5, 50 },    { -3, 54 },
++    { -2, 62 },  { 0, 58 },   { 1, 63 },     { -2, 72 },
++    { -1, 74 },  { -9, 91 },  { -5, 67 },    { -5, 27 },
++    { -3, 39 },  { -2, 44 },  { 0, 46 },     { -16, 64 },
++    { -8, 68 },  { -10, 78 }, { -6, 77 },    { -10, 86 },
++    { -12, 92 }, { -15, 55 }, { -10, 60 },   { -6, 62 },
++    { -4, 65 },
++
++    /* 252 -> 275 */
++    { -12, 73 }, { -8, 76 },  { -7, 80 },    { -9, 88 },
++    { -17, 110 },{ -11, 97 }, { -20, 84 },   { -11, 79 },
++    { -6, 73 },  { -4, 74 },  { -13, 86 },   { -13, 96 },
++    { -11, 97 }, { -19, 117 },{ -8, 78 },    { -5, 33 },
++    { -4, 48 },  { -2, 53 },  { -3, 62 },    { -13, 71 },
++    { -10, 79 }, { -12, 86 }, { -13, 90 },   { -14, 97 },
++
++    /* 276 a bit special (not used, bypass is used instead) */
++    { 0, 0 },
++
++    /* 277 -> 307 */
++    { -6, 93 },  { -6, 84 },  { -8, 79 },    { 0, 66 },
++    { -1, 71 },  { 0, 62 },   { -2, 60 },    { -2, 59 },
++    { -5, 75 },  { -3, 62 },  { -4, 58 },    { -9, 66 },
++    { -1, 79 },  { 0, 71 },   { 3, 68 },     { 10, 44 },
++    { -7, 62 },  { 15, 36 },  { 14, 40 },    { 16, 27 },
++    { 12, 29 },  { 1, 44 },   { 20, 36 },    { 18, 32 },
++    { 5, 42 },   { 1, 48 },   { 10, 62 },    { 17, 46 },
++    { 9, 64 },   { -12, 104 },{ -11, 97 },
++
++    /* 308 -> 337 */
++    { -16, 96 }, { -7, 88 },  { -8, 85 },    { -7, 85 },
++    { -9, 85 },  { -13, 88 }, { 4, 66 },     { -3, 77 },
++    { -3, 76 },  { -6, 76 },  { 10, 58 },    { -1, 76 },
++    { -1, 83 },  { -7, 99 },  { -14, 95 },   { 2, 95 },
++    { 0, 76 },   { -5, 74 },  { 0, 70 },     { -11, 75 },
++    { 1, 68 },   { 0, 65 },   { -14, 73 },   { 3, 62 },
++    { 4, 62 },   { -1, 68 },  { -13, 75 },   { 11, 55 },
++    { 5, 64 },   { 12, 70 },
++
++    /* 338 -> 368 */
++    { 15, 6 },   { 6, 19 },   { 7, 16 },     { 12, 14 },
++    { 18, 13 },  { 13, 11 },  { 13, 15 },    { 15, 16 },
++    { 12, 23 },  { 13, 23 },  { 15, 20 },    { 14, 26 },
++    { 14, 44 },  { 17, 40 },  { 17, 47 },    { 24, 17 },
++    { 21, 21 },  { 25, 22 },  { 31, 27 },    { 22, 29 },
++    { 19, 35 },  { 14, 50 },  { 10, 57 },    { 7, 63 },
++    { -2, 77 },  { -4, 82 },  { -3, 94 },    { 9, 69 },
++    { -12, 109 },{ 36, -35 }, { 36, -34 },
++
++    /* 369 -> 398 */
++    { 32, -26 }, { 37, -30 }, { 44, -32 },   { 34, -18 },
++    { 34, -15 }, { 40, -15 }, { 33, -7 },    { 35, -5 },
++    { 33, 0 },   { 38, 2 },   { 33, 13 },    { 23, 35 },
++    { 13, 58 },  { 29, -3 },  { 26, 0 },     { 22, 30 },
++    { 31, -7 },  { 35, -15 }, { 34, -3 },    { 34, 3 },
++    { 36, -1 },  { 34, 5 },   { 32, 11 },    { 35, 5 },
++    { 34, 12 },  { 39, 11 },  { 30, 29 },    { 34, 26 },
++    { 29, 39 },  { 19, 66 },
++
++    /* 399 -> 435 */
++    {  31,  21 }, {  31,  31 }, {  25,  50 },
++    { -17, 120 }, { -20, 112 }, { -18, 114 }, { -11,  85 },
++    { -15,  92 }, { -14,  89 }, { -26,  71 }, { -15,  81 },
++    { -14,  80 }, {   0,  68 }, { -14,  70 }, { -24,  56 },
++    { -23,  68 }, { -24,  50 }, { -11,  74 }, {  23, -13 },
++    {  26, -13 }, {  40, -15 }, {  49, -14 }, {  44,   3 },
++    {  45,   6 }, {  44,  34 }, {  33,  54 }, {  19,  82 },
++    {  -3,  75 }, {  -1,  23 }, {   1,  34 }, {   1,  43 },
++    {   0,  54 }, {  -2,  55 }, {   0,  61 }, {   1,  64 },
++    {   0,  68 }, {  -9,  92 },
++
++    /* 436 -> 459 */
++    { -14, 106 }, { -13,  97 }, { -15,  90 }, { -12,  90 },
++    { -18,  88 }, { -10,  73 }, {  -9,  79 }, { -14,  86 },
++    { -10,  73 }, { -10,  70 }, { -10,  69 }, {  -5,  66 },
++    {  -9,  64 }, {  -5,  58 }, {   2,  59 }, {  21, -10 },
++    {  24, -11 }, {  28,  -8 }, {  28,  -1 }, {  29,   3 },
++    {  29,   9 }, {  35,  20 }, {  29,  36 }, {  14,  67 }
++};
++__place_k0_data__ char cabac_context_init_PB[3][460][2] =
++{
++    /* i_cabac_init_idc == 0 */
++    {
++        /* 0 - 10 */
++        {  20, -15 }, {   2,  54 }, {   3,  74 }, {  20, -15 },
++        {   2,  54 }, {   3,  74 }, { -28, 127 }, { -23, 104 },
++        {  -6,  53 }, {  -1,  54 }, {   7,  51 },
++
++        /* 11 - 23 */
++        {  23,  33 }, {  23,   2 }, {  21,   0 }, {   1,   9 },
++        {   0,  49 }, { -37, 118 }, {   5,  57 }, { -13,  78 },
++        { -11,  65 }, {   1,  62 }, {  12,  49 }, {  -4,  73 },
++        {  17,  50 },
++
++        /* 24 - 39 */
++        {  18,  64 }, {   9,  43 }, {  29,   0 }, {  26,  67 },
++        {  16,  90 }, {   9, 104 }, { -46, 127 }, { -20, 104 },
++        {   1,  67 }, { -13,  78 }, { -11,  65 }, {   1,  62 },
++        {  -6,  86 }, { -17,  95 }, {  -6,  61 }, {   9,  45 },
++
++        /* 40 - 53 */
++        {  -3,  69 }, {  -6,  81 }, { -11,  96 }, {   6,  55 },
++        {   7,  67 }, {  -5,  86 }, {   2,  88 }, {   0,  58 },
++        {  -3,  76 }, { -10,  94 }, {   5,  54 }, {   4,  69 },
++        {  -3,  81 }, {   0,  88 },
++
++        /* 54 - 59 */
++        {  -7,  67 }, {  -5,  74 }, {  -4,  74 }, {  -5,  80 },
++        {  -7,  72 }, {   1,  58 },
++
++        /* 60 - 69 */
++        {   0,  41 }, {   0,  63 }, {   0,  63 }, { 0, 63 },
++        {  -9,  83 }, {   4,  86 }, {   0,  97 }, { -7, 72 },
++        {  13,  41 }, {   3,  62 },
++
++        /* 70 - 87 */
++        {   0,  45 }, {  -4,  78 }, {  -3,  96 }, { -27,  126 },
++        { -28,  98 }, { -25, 101 }, { -23,  67 }, { -28,  82 },
++        { -20,  94 }, { -16,  83 }, { -22, 110 }, { -21,  91 },
++        { -18, 102 }, { -13,  93 }, { -29, 127 }, {  -7,  92 },
++        {  -5,  89 }, {  -7,  96 }, { -13, 108 }, {  -3,  46 },
++        {  -1,  65 }, {  -1,  57 }, {  -9,  93 }, {  -3,  74 },
++        {  -9,  92 }, {  -8,  87 }, { -23, 126 }, {   5,  54 },
++        {   6,  60 }, {   6,  59 }, {   6,  69 }, {  -1,  48 },
++        {   0,  68 }, {  -4,  69 }, {  -8,  88 },
++
++        /* 105 -> 165 */
++        {  -2,  85 }, {  -6,  78 }, {  -1,  75 }, {  -7,  77 },
++        {   2,  54 }, {   5,  50 }, {  -3,  68 }, {   1,  50 },
++        {   6,  42 }, {  -4,  81 }, {   1,  63 }, {  -4,  70 },
++        {   0,  67 }, {   2,  57 }, {  -2,  76 }, {  11,  35 },
++        {   4,  64 }, {   1,  61 }, {  11,  35 }, {  18,  25 },
++        {  12,  24 }, {  13,  29 }, {  13,  36 }, { -10,  93 },
++        {  -7,  73 }, {  -2,  73 }, {  13,  46 }, {   9,  49 },
++        {  -7, 100 }, {   9,  53 }, {   2,  53 }, {   5,  53 },
++        {  -2,  61 }, {   0,  56 }, {   0,  56 }, { -13,  63 },
++        {  -5,  60 }, {  -1,  62 }, {   4,  57 }, {  -6,  69 },
++        {   4,  57 }, {  14,  39 }, {   4,  51 }, {  13,  68 },
++        {   3,  64 }, {   1,  61 }, {   9,  63 }, {   7,  50 },
++        {  16,  39 }, {   5,  44 }, {   4,  52 }, {  11,  48 },
++        {  -5,  60 }, {  -1,  59 }, {   0,  59 }, {  22,  33 },
++        {   5,  44 }, {  14,  43 }, {  -1,  78 }, {   0,  60 },
++        {   9,  69 },
++
++        /* 166 - 226 */
++        {  11,  28 }, {   2,  40 }, {   3,  44 }, {   0,  49 },
++        {   0,  46 }, {   2,  44 }, {   2,  51 }, {   0,  47 },
++        {   4,  39 }, {   2,  62 }, {   6,  46 }, {   0,  54 },
++        {   3,  54 }, {   2,  58 }, {   4,  63 }, {   6,  51 },
++        {   6,  57 }, {   7,  53 }, {   6,  52 }, {   6,  55 },
++        {  11,  45 }, {  14,  36 }, {   8,  53 }, {  -1,  82 },
++        {   7,  55 }, {  -3,  78 }, {  15,  46 }, {  22,  31 },
++        {  -1,  84 }, {  25,   7 }, {  30,  -7 }, {  28,   3 },
++        {  28,   4 }, {  32,   0 }, {  34,  -1 }, {  30,   6 },
++        {  30,   6 }, {  32,   9 }, {  31,  19 }, {  26,  27 },
++        {  26,  30 }, {  37,  20 }, {  28,  34 }, {  17,  70 },
++        {   1,  67 }, {   5,  59 }, {   9,  67 }, {  16,  30 },
++        {  18,  32 }, {  18,  35 }, {  22,  29 }, {  24,  31 },
++        {  23,  38 }, {  18,  43 }, {  20,  41 }, {  11,  63 },
++        {   9,  59 }, {   9,  64 }, {  -1,  94 }, {  -2,  89 },
++        {  -9, 108 },
++
++        /* 227 - 275 */
++        {  -6,  76 }, {  -2,  44 }, {   0,  45 }, {   0,  52 },
++        {  -3,  64 }, {  -2,  59 }, {  -4,  70 }, {  -4,  75 },
++        {  -8,  82 }, { -17, 102 }, {  -9,  77 }, {   3,  24 },
++        {   0,  42 }, {   0,  48 }, {   0,  55 }, {  -6,  59 },
++        {  -7,  71 }, { -12,  83 }, { -11,  87 }, { -30, 119 },
++        {   1,  58 }, {  -3,  29 }, {  -1,  36 }, {   1,  38 },
++        {   2,  43 }, {  -6,  55 }, {   0,  58 }, {   0,  64 },
++        {  -3,  74 }, { -10,  90 }, {   0,  70 }, {  -4,  29 },
++        {   5,  31 }, {   7,  42 }, {   1,  59 }, {  -2,  58 },
++        {  -3,  72 }, {  -3,  81 }, { -11,  97 }, {   0,  58 },
++        {   8,   5 }, {  10,  14 }, {  14,  18 }, {  13,  27 },
++        {   2,  40 }, {   0,  58 }, {  -3,  70 }, {  -6,  79 },
++        {  -8,  85 },
++
++        /* 276 a bit special (not used, bypass is used instead) */
++        { 0, 0 },
++
++        /* 277 - 337 */
++        { -13, 106 }, { -16, 106 }, { -10,  87 }, { -21, 114 },
++        { -18, 110 }, { -14,  98 }, { -22, 110 }, { -21, 106 },
++        { -18, 103 }, { -21, 107 }, { -23, 108 }, { -26, 112 },
++        { -10,  96 }, { -12,  95 }, {  -5,  91 }, {  -9,  93 },
++        { -22,  94 }, {  -5,  86 }, {   9,  67 }, {  -4,  80 },
++        { -10,  85 }, {  -1,  70 }, {   7,  60 }, {   9,  58 },
++        {   5,  61 }, {  12,  50 }, {  15,  50 }, {  18,  49 },
++        {  17,  54 }, {  10,  41 }, {   7,  46 }, {  -1,  51 },
++        {   7,  49 }, {   8,  52 }, {   9,  41 }, {   6,  47 },
++        {   2,  55 }, {  13,  41 }, {  10,  44 }, {   6,  50 },
++        {   5,  53 }, {  13,  49 }, {   4,  63 }, {   6,  64 },
++        {  -2,  69 }, {  -2,  59 }, {   6,  70 }, {  10,  44 },
++        {   9,  31 }, {  12,  43 }, {   3,  53 }, {  14,  34 },
++        {  10,  38 }, {  -3,  52 }, {  13,  40 }, {  17,  32 },
++        {   7,  44 }, {   7,  38 }, {  13,  50 }, {  10,  57 },
++        {  26,  43 },
++
++        /* 338 - 398 */
++        {  14,  11 }, {  11,  14 }, {   9,  11 }, {  18,  11 },
++        {  21,   9 }, {  23,  -2 }, {  32, -15 }, {  32, -15 },
++        {  34, -21 }, {  39, -23 }, {  42, -33 }, {  41, -31 },
++        {  46, -28 }, {  38, -12 }, {  21,  29 }, {  45, -24 },
++        {  53, -45 }, {  48, -26 }, {  65, -43 }, {  43, -19 },
++        {  39, -10 }, {  30,   9 }, {  18,  26 }, {  20,  27 },
++        {   0,  57 }, { -14,  82 }, {  -5,  75 }, { -19,  97 },
++        { -35, 125 }, {  27,   0 }, {  28,   0 }, {  31,  -4 },
++        {  27,   6 }, {  34,   8 }, {  30,  10 }, {  24,  22 },
++        {  33,  19 }, {  22,  32 }, {  26,  31 }, {  21,  41 },
++        {  26,  44 }, {  23,  47 }, {  16,  65 }, {  14,  71 },
++        {   8,  60 }, {   6,  63 }, {  17,  65 }, {  21,  24 },
++        {  23,  20 }, {  26,  23 }, {  27,  32 }, {  28,  23 },
++        {  28,  24 }, {  23,  40 }, {  24,  32 }, {  28,  29 },
++        {  23,  42 }, {  19,  57 }, {  22,  53 }, {  22,  61 },
++        {  11,  86 },
++
++        /* 399 - 435 */
++        {  12,  40 }, {  11,  51 }, {  14,  59 },
++        {  -4,  79 }, {  -7,  71 }, {  -5,  69 }, {  -9,  70 },
++        {  -8,  66 }, { -10,  68 }, { -19,  73 }, { -12,  69 },
++        { -16,  70 }, { -15,  67 }, { -20,  62 }, { -19,  70 },
++        { -16,  66 }, { -22,  65 }, { -20,  63 }, {   9,  -2 },
++        {  26,  -9 }, {  33,  -9 }, {  39,  -7 }, {  41,  -2 },
++        {  45,   3 }, {  49,   9 }, {  45,  27 }, {  36,  59 },
++        {  -6,  66 }, {  -7,  35 }, {  -7,  42 }, {  -8,  45 },
++        {  -5,  48 }, { -12,  56 }, {  -6,  60 }, {  -5,  62 },
++        {  -8,  66 }, {  -8,  76 },
++
++        /* 436 - 459 */
++        {  -5,  85 }, {  -6,  81 }, { -10,  77 }, {  -7,  81 },
++        { -17,  80 }, { -18,  73 }, {  -4,  74 }, { -10,  83 },
++        {  -9,  71 }, {  -9,  67 }, {  -1,  61 }, {  -8,  66 },
++        { -14,  66 }, {   0,  59 }, {   2,  59 }, {  21, -13 },
++        {  33, -14 }, {  39,  -7 }, {  46,  -2 }, {  51,   2 },
++        {  60,   6 }, {  61,  17 }, {  55,  34 }, {  42,  62 },
++    },
++
++    /* i_cabac_init_idc == 1 */
++    {
++        /* 0 - 10 */
++        {  20, -15 }, {   2,  54 }, {   3,  74 }, {  20, -15 },
++        {   2,  54 }, {   3,  74 }, { -28, 127 }, { -23, 104 },
++        {  -6,  53 }, {  -1,  54 }, {   7,  51 },
++
++        /* 11 - 23 */
++        {  22,  25 }, {  34,   0 }, {  16,   0 }, {  -2,   9 },
++        {   4,  41 }, { -29, 118 }, {   2,  65 }, {  -6,  71 },
++        { -13,  79 }, {   5,  52 }, {   9,  50 }, {  -3,  70 },
++        {  10,  54 },
++
++        /* 24 - 39 */
++        {  26,  34 }, {  19,  22 }, {  40,   0 }, {  57,   2 },
++        {  41,  36 }, {  26,  69 }, { -45, 127 }, { -15, 101 },
++        {  -4,  76 }, {  -6,  71 }, { -13,  79 }, {   5,  52 },
++        {   6,  69 }, { -13,  90 }, {   0,  52 }, {   8,  43 },
++
++        /* 40 - 53 */
++        {  -2,  69 },{  -5,  82 },{ -10,  96 },{   2,  59 },
++        {   2,  75 },{  -3,  87 },{  -3,  100 },{   1,  56 },
++        {  -3,  74 },{  -6,  85 },{   0,  59 },{  -3,  81 },
++        {  -7,  86 },{  -5,  95 },
++
++        /* 54 - 59 */
++        {  -1,  66 },{  -1,  77 },{   1,  70 },{  -2,  86 },
++        {  -5,  72 },{   0,  61 },
++
++        /* 60 - 69 */
++        { 0, 41 },   { 0, 63 },   { 0, 63 },     { 0, 63 },
++        { -9, 83 },  { 4, 86 },   { 0, 97 },     { -7, 72 },
++        { 13, 41 },  { 3, 62 },
++
++        /* 70 - 104 */
++        {  13,  15 }, {   7,  51 }, {   2,  80 }, { -39, 127 },
++        { -18,  91 }, { -17,  96 }, { -26,  81 }, { -35,  98 },
++        { -24, 102 }, { -23,  97 }, { -27, 119 }, { -24,  99 },
++        { -21, 110 }, { -18, 102 }, { -36, 127 }, {   0,  80 },
++        {  -5,  89 }, {  -7,  94 }, {  -4,  92 }, {   0,  39 },
++        {   0,  65 }, { -15,  84 }, { -35, 127 }, {  -2,  73 },
++        { -12, 104 }, {  -9,  91 }, { -31, 127 }, {   3,  55 },
++        {   7,  56 }, {   7,  55 }, {   8,  61 }, {  -3,  53 },
++        {   0,  68 }, {  -7,  74 }, {  -9,  88 },
++
++        /* 105 -> 165 */
++        { -13, 103 }, { -13,  91 }, {  -9,  89 }, { -14,  92 },
++        {  -8,  76 }, { -12,  87 }, { -23, 110 }, { -24, 105 },
++        { -10,  78 }, { -20, 112 }, { -17,  99 }, { -78, 127 },
++        { -70, 127 }, { -50, 127 }, { -46, 127 }, {  -4,  66 },
++        {  -5,  78 }, {  -4,  71 }, {  -8,  72 }, {   2,  59 },
++        {  -1,  55 }, {  -7,  70 }, {  -6,  75 }, {  -8,  89 },
++        { -34, 119 }, {  -3,  75 }, {  32,  20 }, {  30,  22 },
++        { -44, 127 }, {   0,  54 }, {  -5,  61 }, {   0,  58 },
++        {  -1,  60 }, {  -3,  61 }, {  -8,  67 }, { -25,  84 },
++        { -14,  74 }, {  -5,  65 }, {   5,  52 }, {   2,  57 },
++        {   0,  61 }, {  -9,  69 }, { -11,  70 }, {  18,  55 },
++        {  -4,  71 }, {   0,  58 }, {   7,  61 }, {   9,  41 },
++        {  18,  25 }, {   9,  32 }, {   5,  43 }, {   9,  47 },
++        {   0,  44 }, {   0,  51 }, {   2,  46 }, {  19,  38 },
++        {  -4,  66 }, {  15,  38 }, {  12,  42 }, {   9,  34 },
++        {   0,  89 },
++
++        /* 166 - 226 */
++        {   4,  45 }, {  10,  28 }, {  10,  31 }, {  33, -11 },
++        {  52, -43 }, {  18,  15 }, {  28,   0 }, {  35, -22 },
++        {  38, -25 }, {  34,   0 }, {  39, -18 }, {  32, -12 },
++        { 102, -94 }, {   0,   0 }, {  56, -15 }, {  33,  -4 },
++        {  29,  10 }, {  37,  -5 }, {  51, -29 }, {  39,  -9 },
++        {  52, -34 }, {  69, -58 }, {  67, -63 }, {  44,  -5 },
++        {  32,   7 }, {  55, -29 }, {  32,   1 }, {   0,   0 },
++        {  27,  36 }, {  33, -25 }, {  34, -30 }, {  36, -28 },
++        {  38, -28 }, {  38, -27 }, {  34, -18 }, {  35, -16 },
++        {  34, -14 }, {  32,  -8 }, {  37,  -6 }, {  35,   0 },
++        {  30,  10 }, {  28,  18 }, {  26,  25 }, {  29,  41 },
++        {   0,  75 }, {   2,  72 }, {   8,  77 }, {  14,  35 },
++        {  18,  31 }, {  17,  35 }, {  21,  30 }, {  17,  45 },
++        {  20,  42 }, {  18,  45 }, {  27,  26 }, {  16,  54 },
++        {   7,  66 }, {  16,  56 }, {  11,  73 }, {  10,  67 },
++        { -10, 116 },
++
++        /* 227 - 275 */
++        { -23, 112 }, { -15,  71 }, {  -7,  61 }, {   0,  53 },
++        {  -5,  66 }, { -11,  77 }, {  -9,  80 }, {  -9,  84 },
++        { -10,  87 }, { -34, 127 }, { -21, 101 }, {  -3,  39 },
++        {  -5,  53 }, {  -7,  61 }, { -11,  75 }, { -15,  77 },
++        { -17,  91 }, { -25, 107 }, { -25, 111 }, { -28, 122 },
++        { -11,  76 }, { -10,  44 }, { -10,  52 }, { -10,  57 },
++        {  -9,  58 }, { -16,  72 }, {  -7,  69 }, {  -4,  69 },
++        {  -5,  74 }, {  -9,  86 }, {   2,  66 }, {  -9,  34 },
++        {   1,  32 }, {  11,  31 }, {   5,  52 }, {  -2,  55 },
++        {  -2,  67 }, {   0,  73 }, {  -8,  89 }, {   3,  52 },
++        {   7,   4 }, {  10,   8 }, {  17,   8 }, {  16,  19 },
++        {   3,  37 }, {  -1,  61 }, {  -5,  73 }, {  -1,  70 },
++        {  -4,  78 },
++
++        /* 276 a bit special (not used, bypass is used instead) */
++        { 0, 0 },
++
++        /* 277 - 337 */
++        { -21, 126 }, { -23, 124 }, { -20, 110 }, { -26, 126 },
++        { -25, 124 }, { -17, 105 }, { -27, 121 }, { -27, 117 },
++        { -17, 102 }, { -26, 117 }, { -27, 116 }, { -33, 122 },
++        { -10,  95 }, { -14, 100 }, {  -8,  95 }, { -17, 111 },
++        { -28, 114 }, {  -6,  89 }, {  -2,  80 }, {  -4,  82 },
++        {  -9,  85 }, {  -8,  81 }, {  -1,  72 }, {   5,  64 },
++        {   1,  67 }, {   9,  56 }, {   0,  69 }, {   1,  69 },
++        {   7,  69 }, {  -7,  69 }, {  -6,  67 }, { -16,  77 },
++        {  -2,  64 }, {   2,  61 }, {  -6,  67 }, {  -3,  64 },
++        {   2,  57 }, {  -3,  65 }, {  -3,  66 }, {   0,  62 },
++        {   9,  51 }, {  -1,  66 }, {  -2,  71 }, {  -2,  75 },
++        {  -1,  70 }, {  -9,  72 }, {  14,  60 }, {  16,  37 },
++        {   0,  47 }, {  18,  35 }, {  11,  37 }, {  12,  41 },
++        {  10,  41 }, {   2,  48 }, {  12,  41 }, {  13,  41 },
++        {   0,  59 }, {   3,  50 }, {  19,  40 }, {   3,  66 },
++        {  18,  50 },
++
++        /* 338 - 398 */
++        {  19,  -6 }, {  18,  -6 }, {  14,   0 }, {  26, -12 },
++        {  31, -16 }, {  33, -25 }, {  33, -22 }, {  37, -28 },
++        {  39, -30 }, {  42, -30 }, {  47, -42 }, {  45, -36 },
++        {  49, -34 }, {  41, -17 }, {  32,   9 }, {  69, -71 },
++        {  63, -63 }, {  66, -64 }, {  77, -74 }, {  54, -39 },
++        {  52, -35 }, {  41, -10 }, {  36,   0 }, {  40,  -1 },
++        {  30,  14 }, {  28,  26 }, {  23,  37 }, {  12,  55 },
++        {  11,  65 }, {  37, -33 }, {  39, -36 }, {  40, -37 },
++        {  38, -30 }, {  46, -33 }, {  42, -30 }, {  40, -24 },
++        {  49, -29 }, {  38, -12 }, {  40, -10 }, {  38,  -3 },
++        {  46,  -5 }, {  31,  20 }, {  29,  30 }, {  25,  44 },
++        {  12,  48 }, {  11,  49 }, {  26,  45 }, {  22,  22 },
++        {  23,  22 }, {  27,  21 }, {  33,  20 }, {  26,  28 },
++        {  30,  24 }, {  27,  34 }, {  18,  42 }, {  25,  39 },
++        {  18,  50 }, {  12,  70 }, {  21,  54 }, {  14,  71 },
++        {  11,  83 },
++
++        /* 399 - 435 */
++        {  25,  32 }, {  21,  49 }, {  21,  54 },
++        {  -5,  85 }, {  -6,  81 }, { -10,  77 }, {  -7,  81 },
++        { -17,  80 }, { -18,  73 }, {  -4,  74 }, { -10,  83 },
++        {  -9,  71 }, {  -9,  67 }, {  -1,  61 }, {  -8,  66 },
++        { -14,  66 }, {   0,  59 }, {   2,  59 }, {  17, -10 },
++        {  32, -13 }, {  42,  -9 }, {  49,  -5 }, {  53,   0 },
++        {  64,   3 }, {  68,  10 }, {  66,  27 }, {  47,  57 },
++        {  -5,  71 }, {   0,  24 }, {  -1,  36 }, {  -2,  42 },
++        {  -2,  52 }, {  -9,  57 }, {  -6,  63 }, {  -4,  65 },
++        {  -4,  67 }, {  -7,  82 },
++
++        /* 436 - 459 */
++        {  -3,  81 }, {  -3,  76 }, {  -7,  72 }, {  -6,  78 },
++        { -12,  72 }, { -14,  68 }, {  -3,  70 }, {  -6,  76 },
++        {  -5,  66 }, {  -5,  62 }, {   0,  57 }, {  -4,  61 },
++        {  -9,  60 }, {   1,  54 }, {   2,  58 }, {  17, -10 },
++        {  32, -13 }, {  42,  -9 }, {  49,  -5 }, {  53,   0 },
++        {  64,   3 }, {  68,  10 }, {  66,  27 }, {  47,  57 },
++    },
++
++    /* i_cabac_init_idc == 2 */
++    {
++        /* 0 - 10 */
++        {  20, -15 }, {   2,  54 }, {   3,  74 }, {  20, -15 },
++        {   2,  54 }, {   3,  74 }, { -28, 127 }, { -23, 104 },
++        {  -6,  53 }, {  -1,  54 }, {   7,  51 },
++
++        /* 11 - 23 */
++        {  29,  16 }, {  25,   0 }, {  14,   0 }, { -10,  51 },
++        {  -3,  62 }, { -27,  99 }, {  26,  16 }, {  -4,  85 },
++        { -24, 102 }, {   5,  57 }, {   6,  57 }, { -17,  73 },
++        {  14,  57 },
++
++        /* 24 - 39 */
++        {  20,  40 }, {  20,  10 }, {  29,   0 }, {  54,   0 },
++        {  37,  42 }, {  12,  97 }, { -32, 127 }, { -22, 117 },
++        {  -2,  74 }, {  -4,  85 }, { -24, 102 }, {   5,  57 },
++        {  -6,  93 }, { -14,  88 }, {  -6,  44 }, {   4,  55 },
++
++        /* 40 - 53 */
++        { -11,  89 },{ -15,  103 },{ -21,  116 },{  19,  57 },
++        {  20,  58 },{   4,  84 },{   6,  96 },{   1,  63 },
++        {  -5,  85 },{ -13,  106 },{   5,  63 },{   6,  75 },
++        {  -3,  90 },{  -1,  101 },
++
++        /* 54 - 59 */
++        {   3,  55 },{  -4,  79 },{  -2,  75 },{ -12,  97 },
++        {  -7,  50 },{   1,  60 },
++
++        /* 60 - 69 */
++        { 0, 41 },   { 0, 63 },   { 0, 63 },     { 0, 63 },
++        { -9, 83 },  { 4, 86 },   { 0, 97 },     { -7, 72 },
++        { 13, 41 },  { 3, 62 },
++
++        /* 70 - 104 */
++        {   7,  34 }, {  -9,  88 }, { -20, 127 }, { -36, 127 },
++        { -17,  91 }, { -14,  95 }, { -25,  84 }, { -25,  86 },
++        { -12,  89 }, { -17,  91 }, { -31, 127 }, { -14,  76 },
++        { -18, 103 }, { -13,  90 }, { -37, 127 }, {  11,  80 },
++        {   5,  76 }, {   2,  84 }, {   5,  78 }, {  -6,  55 },
++        {   4,  61 }, { -14,  83 }, { -37, 127 }, {  -5,  79 },
++        { -11, 104 }, { -11,  91 }, { -30, 127 }, {   0,  65 },
++        {  -2,  79 }, {   0,  72 }, {  -4,  92 }, {  -6,  56 },
++        {   3,  68 }, {  -8,  71 }, { -13,  98 },
++
++        /* 105 -> 165 */
++        {  -4,  86 }, { -12,  88 }, {  -5,  82 }, {  -3,  72 },
++        {  -4,  67 }, {  -8,  72 }, { -16,  89 }, {  -9,  69 },
++        {  -1,  59 }, {   5,  66 }, {   4,  57 }, {  -4,  71 },
++        {  -2,  71 }, {   2,  58 }, {  -1,  74 }, {  -4,  44 },
++        {  -1,  69 }, {   0,  62 }, {  -7,  51 }, {  -4,  47 },
++        {  -6,  42 }, {  -3,  41 }, {  -6,  53 }, {   8,  76 },
++        {  -9,  78 }, { -11,  83 }, {   9,  52 }, {   0,  67 },
++        {  -5,  90 }, {   1,  67 }, { -15,  72 }, {  -5,  75 },
++        {  -8,  80 }, { -21,  83 }, { -21,  64 }, { -13,  31 },
++        { -25,  64 }, { -29,  94 }, {   9,  75 }, {  17,  63 },
++        {  -8,  74 }, {  -5,  35 }, {  -2,  27 }, {  13,  91 },
++        {   3,  65 }, {  -7,  69 }, {   8,  77 }, { -10,  66 },
++        {   3,  62 }, {  -3,  68 }, { -20,  81 }, {   0,  30 },
++        {   1,   7 }, {  -3,  23 }, { -21,  74 }, {  16,  66 },
++        { -23, 124 }, {  17,  37 }, {  44, -18 }, {  50, -34 },
++        { -22, 127 },
++
++        /* 166 - 226 */
++        {   4,  39 }, {   0,  42 }, {   7,  34 }, {  11,  29 },
++        {   8,  31 }, {   6,  37 }, {   7,  42 }, {   3,  40 },
++        {   8,  33 }, {  13,  43 }, {  13,  36 }, {   4,  47 },
++        {   3,  55 }, {   2,  58 }, {   6,  60 }, {   8,  44 },
++        {  11,  44 }, {  14,  42 }, {   7,  48 }, {   4,  56 },
++        {   4,  52 }, {  13,  37 }, {   9,  49 }, {  19,  58 },
++        {  10,  48 }, {  12,  45 }, {   0,  69 }, {  20,  33 },
++        {   8,  63 }, {  35, -18 }, {  33, -25 }, {  28,  -3 },
++        {  24,  10 }, {  27,   0 }, {  34, -14 }, {  52, -44 },
++        {  39, -24 }, {  19,  17 }, {  31,  25 }, {  36,  29 },
++        {  24,  33 }, {  34,  15 }, {  30,  20 }, {  22,  73 },
++        {  20,  34 }, {  19,  31 }, {  27,  44 }, {  19,  16 },
++        {  15,  36 }, {  15,  36 }, {  21,  28 }, {  25,  21 },
++        {  30,  20 }, {  31,  12 }, {  27,  16 }, {  24,  42 },
++        {   0,  93 }, {  14,  56 }, {  15,  57 }, {  26,  38 },
++        { -24, 127 },
++
++        /* 227 - 275 */
++        { -24, 115 }, { -22,  82 }, {  -9,  62 }, {   0,  53 },
++        {   0,  59 }, { -14,  85 }, { -13,  89 }, { -13,  94 },
++        { -11,  92 }, { -29, 127 }, { -21, 100 }, { -14,  57 },
++        { -12,  67 }, { -11,  71 }, { -10,  77 }, { -21,  85 },
++        { -16,  88 }, { -23, 104 }, { -15,  98 }, { -37, 127 },
++        { -10,  82 }, {  -8,  48 }, {  -8,  61 }, {  -8,  66 },
++        {  -7,  70 }, { -14,  75 }, { -10,  79 }, {  -9,  83 },
++        { -12,  92 }, { -18, 108 }, {  -4,  79 }, { -22,  69 },
++        { -16,  75 }, {  -2,  58 }, {   1,  58 }, { -13,  78 },
++        {  -9,  83 }, {  -4,  81 }, { -13,  99 }, { -13,  81 },
++        {  -6,  38 }, { -13,  62 }, {  -6,  58 }, {  -2,  59 },
++        { -16,  73 }, { -10,  76 }, { -13,  86 }, {  -9,  83 },
++        { -10,  87 },
++
++        /* 276 a bit special (not used, bypass is used instead) */
++        { 0, 0 },
++
++        /* 277 - 337 */
++        { -22, 127 }, { -25, 127 }, { -25, 120 }, { -27, 127 },
++        { -19, 114 }, { -23, 117 }, { -25, 118 }, { -26, 117 },
++        { -24, 113 }, { -28, 118 }, { -31, 120 }, { -37, 124 },
++        { -10,  94 }, { -15, 102 }, { -10,  99 }, { -13, 106 },
++        { -50, 127 }, {  -5,  92 }, {  17,  57 }, {  -5,  86 },
++        { -13,  94 }, { -12,  91 }, {  -2,  77 }, {   0,  71 },
++        {  -1,  73 }, {   4,  64 }, {  -7,  81 }, {   5,  64 },
++        {  15,  57 }, {   1,  67 }, {   0,  68 }, { -10,  67 },
++        {   1,  68 }, {   0,  77 }, {   2,  64 }, {   0,  68 },
++        {  -5,  78 }, {   7,  55 }, {   5,  59 }, {   2,  65 },
++        {  14,  54 }, {  15,  44 }, {   5,  60 }, {   2,  70 },
++        {  -2,  76 }, { -18,  86 }, {  12,  70 }, {   5,  64 },
++        { -12,  70 }, {  11,  55 }, {   5,  56 }, {   0,  69 },
++        {   2,  65 }, {  -6,  74 }, {   5,  54 }, {   7,  54 },
++        {  -6,  76 }, { -11,  82 }, {  -2,  77 }, {  -2,  77 },
++        {  25,  42 },
++
++        /* 338 - 398 */
++        {  17, -13 }, {  16,  -9 }, {  17, -12 }, {  27, -21 },
++        {  37, -30 }, {  41, -40 }, {  42, -41 }, {  48, -47 },
++        {  39, -32 }, {  46, -40 }, {  52, -51 }, {  46, -41 },
++        {  52, -39 }, {  43, -19 }, {  32,  11 }, {  61, -55 },
++        {  56, -46 }, {  62, -50 }, {  81, -67 }, {  45, -20 },
++        {  35,  -2 }, {  28,  15 }, {  34,   1 }, {  39,   1 },
++        {  30,  17 }, {  20,  38 }, {  18,  45 }, {  15,  54 },
++        {   0,  79 }, {  36, -16 }, {  37, -14 }, {  37, -17 },
++        {  32,   1 }, {  34,  15 }, {  29,  15 }, {  24,  25 },
++        {  34,  22 }, {  31,  16 }, {  35,  18 }, {  31,  28 },
++        {  33,  41 }, {  36,  28 }, {  27,  47 }, {  21,  62 },
++        {  18,  31 }, {  19,  26 }, {  36,  24 }, {  24,  23 },
++        {  27,  16 }, {  24,  30 }, {  31,  29 }, {  22,  41 },
++        {  22,  42 }, {  16,  60 }, {  15,  52 }, {  14,  60 },
++        {   3,  78 }, { -16, 123 }, {  21,  53 }, {  22,  56 },
++        {  25,  61 },
++
++        /* 399 - 435 */
++        {  21,  33 }, {  19,  50 }, {  17,  61 },
++        {  -3,  78 }, {  -8,  74 }, {  -9,  72 }, { -10,  72 },
++        { -18,  75 }, { -12,  71 }, { -11,  63 }, {  -5,  70 },
++        { -17,  75 }, { -14,  72 }, { -16,  67 }, {  -8,  53 },
++        { -14,  59 }, {  -9,  52 }, { -11,  68 }, {   9,  -2 },
++        {  30, -10 }, {  31,  -4 }, {  33,  -1 }, {  33,   7 },
++        {  31,  12 }, {  37,  23 }, {  31,  38 }, {  20,  64 },
++        {  -9,  71 }, {  -7,  37 }, {  -8,  44 }, { -11,  49 },
++        { -10,  56 }, { -12,  59 }, {  -8,  63 }, {  -9,  67 },
++        {  -6,  68 }, { -10,  79 },
++
++        /* 436 - 459 */
++        {  -3,  78 }, {  -8,  74 }, {  -9,  72 }, { -10,  72 },
++        { -18,  75 }, { -12,  71 }, { -11,  63 }, {  -5,  70 },
++        { -17,  75 }, { -14,  72 }, { -16,  67 }, {  -8,  53 },
++        { -14,  59 }, {  -9,  52 }, { -11,  68 }, {   9,  -2 },
++        {  30, -10 }, {  31,  -4 }, {  33,  -1 }, {  33,   7 },
++        {  31,  12 }, {  37,  23 }, {  31,  38 }, {  20,  64 },
++    }
++};
++
++
++
++static inline int jzm_clip2(int a, int min, int max)
++{
++  if (a < min)      return min;
++  else if (a > max) return max;
++  else              return a;
++}
++
++void jzm_h264_slice_init_vdma(struct JZM_H264 * st_h264)
++{
++  int i, j;
++  volatile unsigned int *chn = (volatile unsigned int *)st_h264->des_va;
++
++  /*------------------------------------------------------
++    scheduler
++    ------------------------------------------------------*/
++  GEN_VDMA_ACFG(chn, REG_SCH_SCHC, 0, 0x0);
++  if (st_h264->slice_type == JZM_H264_I_TYPE) {
++    GEN_VDMA_ACFG(chn, REG_SCH_BND, 0, SCH_CH3_HID(HID_DBLK) | SCH_CH2_HID(HID_VMAU) | SCH_DEPTH(DESP_FIFO_WIDTH));
++    GEN_VDMA_ACFG(chn, REG_SCH_SCHG0, 0, 0x0);
++    GEN_VDMA_ACFG(chn, REG_SCH_SCHE1, 0, 0x0);
++    GEN_VDMA_ACFG(chn, REG_SCH_SCHE2, 0, 0x0);
++    GEN_VDMA_ACFG(chn, REG_SCH_SCHE3, 0, 0x0);
++    GEN_VDMA_ACFG(chn, REG_SCH_SCHE4, 0, 0x0);
++    GEN_VDMA_ACFG(chn, REG_SCH_SCHC, 0, SCH_CH2_PE | SCH_CH3_PE);
++    GEN_VDMA_ACFG(chn, REG_SCH_BND, 0, SCH_CH3_HID(HID_DBLK) | SCH_CH2_HID(HID_VMAU) |
++		  SCH_DEPTH(DESP_FIFO_WIDTH) | SCH_BND_G0F2 | SCH_BND_G0F3);
++  } else {
++    GEN_VDMA_ACFG(chn, REG_SCH_BND, 0, SCH_CH3_HID(HID_DBLK) | SCH_CH2_HID(HID_VMAU) | SCH_CH1_HID(HID_MCE) |
++		  SCH_DEPTH(DESP_FIFO_WIDTH));
++    GEN_VDMA_ACFG(chn, REG_SCH_SCHG0, 0, 0x0);
++    GEN_VDMA_ACFG(chn, REG_SCH_SCHE1, 0, 0x0);
++    GEN_VDMA_ACFG(chn, REG_SCH_SCHE2, 0, 0x0);
++    GEN_VDMA_ACFG(chn, REG_SCH_SCHE3, 0, 0x0);
++    GEN_VDMA_ACFG(chn, REG_SCH_SCHE4, 0, 0x0);
++    GEN_VDMA_ACFG(chn, REG_SCH_SCHC, 0, SCH_CH1_PE | SCH_CH2_PE | SCH_CH3_PE);
++    GEN_VDMA_ACFG(chn, REG_SCH_BND, 0, SCH_CH3_HID(HID_DBLK) | SCH_CH2_HID(HID_VMAU) | SCH_CH1_HID(HID_MCE) |
++		  SCH_DEPTH(DESP_FIFO_WIDTH) | SCH_BND_G0F1 | SCH_BND_G0F2 | SCH_BND_G0F3);
++  }
++
++  /*------------------------------------------------------
++    vmau
++    ------------------------------------------------------*/
++  GEN_VDMA_ACFG(chn, REG_VMAU_GBL_RUN, 0, VMAU_RESET);
++  GEN_VDMA_ACFG(chn, REG_VMAU_GBL_CTR, 0, 0);
++  GEN_VDMA_ACFG(chn, REG_VMAU_VIDEO_TYPE, 0, VMAU_FMT_H264);
++  GEN_VDMA_ACFG(chn, REG_VMAU_NCCHN_ADDR, 0, VMAU_DESP_ADDR);
++  GEN_VDMA_ACFG(chn, REG_VMAU_DEC_DONE, 0, VPU_BASE + REG_SCH_SCHE2);
++  GEN_VDMA_ACFG(chn, REG_VMAU_Y_GS, 0, st_h264->mb_width*16);
++  GEN_VDMA_ACFG(chn, REG_VMAU_GBL_CTR, 0, (VMAU_CTRL_FIFO_M | VMAU_CTRL_TO_DBLK));
++  GEN_VDMA_ACFG(chn, REG_VMAU_POS, 0, ((st_h264->start_mb_x & 0xff) | ((st_h264->start_mb_y & 0xff)<<16)));
++  unsigned int qt_ram_addr = REG_VMAU_QT;
++  unsigned int *tbl_ptr = (unsigned int *)st_h264->scaling_matrix8;
++  for ( i = 0 ; i < 32; i++) {
++    GEN_VDMA_ACFG(chn, (qt_ram_addr+i*4), 0, tbl_ptr[i]);
++  }
++  qt_ram_addr = REG_VMAU_QT + 32*4;
++  tbl_ptr = (unsigned int *)st_h264->scaling_matrix4;
++  for ( i = 0 ; i < 24; i++) {
++    GEN_VDMA_ACFG(chn, (qt_ram_addr+i*4), 0, tbl_ptr[i]);
++  }
++
++  /*------------------------------------------------------
++    dblk
++    ------------------------------------------------------*/
++  GEN_VDMA_ACFG(chn, REG_DBLK_TRIG, 0, DBLK_RESET);
++  GEN_VDMA_ACFG(chn, REG_DBLK_DHA, 0, DBLK_DESP_ADDR);
++  GEN_VDMA_ACFG(chn, REG_DBLK_GENDA, 0, VPU_BASE + REG_SCH_SCHE3);
++  GEN_VDMA_ACFG(chn, REG_DBLK_GSIZE, 0, st_h264->mb_width | (st_h264->mb_height << 16));
++  int normal_first_slice = (st_h264->start_mb_x == 0) && (st_h264->start_mb_y == 0);
++  GEN_VDMA_ACFG(chn, REG_DBLK_GPOS, 0, ((st_h264->start_mb_x & 0x3ff) |
++					((st_h264->start_mb_y & 0x3ff)<<16) |
++					((!normal_first_slice)<<31))
++		);
++  GEN_VDMA_ACFG(chn, REG_DBLK_GPIC_YA, 0, st_h264->dec_result_y);
++  GEN_VDMA_ACFG(chn, REG_DBLK_GPIC_CA, 0, st_h264->dec_result_uv);
++  GEN_VDMA_ACFG(chn, REG_DBLK_GP_ENDA, 0, DBLK_GP_ENDF_BASE);
++#define DEBLK_VTR_FMT_I 0
++#define DEBLK_VTR_FMT_P (1<<3)
++#define DEBLK_VTR_FMT_B (2<<3)
++#define DEBLK_VTR_BETA_SFT (16)
++#define DEBLK_VTR_BETA_MSK (0xff)
++#define DEBLK_VTR_ALPHA_SFT (24)
++#define DEBLK_VTR_ALPHA_MSK (0xff)
++  unsigned int h264_vtr = ((st_h264->slice_type == JZM_H264_I_TYPE) ? DEBLK_VTR_FMT_I :
++			   ((st_h264->slice_type == JZM_H264_P_TYPE) ? DEBLK_VTR_FMT_P : DEBLK_VTR_FMT_B)
++			   ) | DBLK_FMT_H264;
++  h264_vtr = h264_vtr | ((st_h264->slice_beta_offset & DEBLK_VTR_BETA_MSK) << DEBLK_VTR_BETA_SFT)
++    | ((st_h264->slice_alpha_c0_offset & DEBLK_VTR_ALPHA_MSK) << DEBLK_VTR_ALPHA_SFT);
++  GEN_VDMA_ACFG(chn, REG_DBLK_VTR, 0, h264_vtr);
++  GEN_VDMA_ACFG(chn, REG_DBLK_GPIC_STR, 0, (st_h264->mb_width*256) | (st_h264->mb_width*128)<<16);
++
++  GEN_VDMA_ACFG(chn, REG_DBLK_GPIC_Y1A, 0, st_h264->dec_result1_y);
++  GEN_VDMA_ACFG(chn, REG_DBLK_GPIC_C1A, 0, st_h264->dec_result1_uv);
++  GEN_VDMA_ACFG(chn, REG_DBLK_GPIC_STR1, 0, (st_h264->frm_y_stride) | (st_h264->frm_c_stride)<<16);
++  GEN_VDMA_ACFG(chn, REG_DBLK_CTRL, 0, 0x1 | (st_h264->new_odma_flag)<<6 | (st_h264->new_odma_format)<<7 | (0<<8) | (1 << 9));
++
++  GEN_VDMA_ACFG(chn, REG_DBLK_TRIG, 0, DBLK_SLICE_RUN);
++  //GEN_VDMA_ACFG(chn, REG_DBLK_CTRL, 0, 0x1);
++  //write_reg(DBLK_GP_ENDF_BASE, -1);
++
++  /*------------------------------------------------------
++    motion
++    ------------------------------------------------------*/
++  //video_motion_init(H264_QPEL, H264_EPEL);
++  int intpid  = H264_QPEL;
++  int cintpid = H264_EPEL;
++  for(i=0; i<16; i++){
++    GEN_VDMA_ACFG(chn, REG_MCE_CH1_ILUT+i*8, 0,
++		  MCE_CH1_IINFO(IntpFMT[intpid][i].intp[0],/*intp1*/
++				IntpFMT[intpid][i].tap,/*tap*/
++				IntpFMT[intpid][i].intp_pkg[0],/*intp1_pkg*/
++				IntpFMT[intpid][i].hldgl,/*hldgl*/
++				IntpFMT[intpid][i].avsdgl,/*avsdgl*/
++				IntpFMT[intpid][i].intp_dir[0],/*intp0_dir*/
++				IntpFMT[intpid][i].intp_rnd[0],/*intp0_rnd*/
++				IntpFMT[intpid][i].intp_sft[0],/*intp0_sft*/
++				IntpFMT[intpid][i].intp_sintp[0],/*sintp0*/
++				IntpFMT[intpid][i].intp_srnd[0],/*sintp0_rnd*/
++				IntpFMT[intpid][i].intp_sbias[0]/*sintp0_bias*/
++				));
++    GEN_VDMA_ACFG(chn, REG_MCE_CH1_ILUT+i*8+4, 0,
++		  MCE_CH1_IINFO(IntpFMT[intpid][i].intp[1],/*intp1*/
++				0,/*tap*/
++				IntpFMT[intpid][i].intp_pkg[1],/*intp1_pkg*/
++				IntpFMT[intpid][i].hldgl,/*hldgl*/
++				IntpFMT[intpid][i].avsdgl,/*avsdgl*/
++				IntpFMT[intpid][i].intp_dir[1],/*intp1_dir*/
++				IntpFMT[intpid][i].intp_rnd[1],/*intp1_rnd*/
++				IntpFMT[intpid][i].intp_sft[1],/*intp1_sft*/
++				IntpFMT[intpid][i].intp_sintp[1],/*sintp1*/
++				IntpFMT[intpid][i].intp_srnd[1],/*sintp1_rnd*/
++				IntpFMT[intpid][i].intp_sbias[1]/*sintp1_bias*/
++				));
++    GEN_VDMA_ACFG(chn, REG_MCE_CH1_CLUT+i*8+4, 0,
++		  MCE_RLUT_WT(IntpFMT[intpid][i].intp_coef[0][7],/*coef8*/
++			      IntpFMT[intpid][i].intp_coef[0][6],/*coef7*/
++			      IntpFMT[intpid][i].intp_coef[0][5],/*coef6*/
++			      IntpFMT[intpid][i].intp_coef[0][4]/*coef5*/
++			      ));
++    GEN_VDMA_ACFG(chn, REG_MCE_CH1_CLUT+i*8, 0,
++		  MCE_RLUT_WT(IntpFMT[intpid][i].intp_coef[0][3],/*coef8*/
++			      IntpFMT[intpid][i].intp_coef[0][2],/*coef7*/
++			      IntpFMT[intpid][i].intp_coef[0][1],/*coef6*/
++			      IntpFMT[intpid][i].intp_coef[0][0]/*coef5*/
++			      ));
++    GEN_VDMA_ACFG(chn, REG_MCE_CH1_CLUT+(i+16)*8+4, 0,
++		  MCE_RLUT_WT(IntpFMT[intpid][i].intp_coef[1][7],/*coef8*/
++			      IntpFMT[intpid][i].intp_coef[1][6],/*coef7*/
++			      IntpFMT[intpid][i].intp_coef[1][5],/*coef6*/
++			      IntpFMT[intpid][i].intp_coef[1][4]/*coef5*/
++			      ));
++    GEN_VDMA_ACFG(chn, REG_MCE_CH1_CLUT+(i+16)*8, 0,
++		  MCE_RLUT_WT(IntpFMT[intpid][i].intp_coef[1][3],/*coef8*/
++			      IntpFMT[intpid][i].intp_coef[1][2],/*coef7*/
++			      IntpFMT[intpid][i].intp_coef[1][1],/*coef6*/
++			      IntpFMT[intpid][i].intp_coef[1][0]/*coef5*/
++			      ));
++    GEN_VDMA_ACFG(chn, REG_MCE_CH2_ILUT+i*8, 0,
++		  MCE_CH2_IINFO(IntpFMT[cintpid][i].intp[0],
++				IntpFMT[cintpid][i].intp_dir[0],
++				IntpFMT[cintpid][i].intp_sft[0],
++				IntpFMT[cintpid][i].intp_coef[0][0],
++				IntpFMT[cintpid][i].intp_coef[0][1],
++				IntpFMT[cintpid][i].intp_rnd[0]) );
++    GEN_VDMA_ACFG(chn, REG_MCE_CH2_ILUT+i*8+4, 0,
++		  MCE_CH2_IINFO(IntpFMT[cintpid][i].intp[1],
++				IntpFMT[cintpid][i].intp_dir[1],
++				IntpFMT[cintpid][i].intp_sft[1],
++				IntpFMT[cintpid][i].intp_coef[1][0],
++				IntpFMT[cintpid][i].intp_coef[1][1],
++				IntpFMT[cintpid][i].intp_rnd[1]) );
++  }
++#define STAT_PFE_SFT        2
++#define STAT_PFE_MSK        0x1
++#define STAT_LKE_SFT        1
++#define STAT_LKE_MSK        0x1
++#define STAT_TKE_SFT        0
++#define STAT_TKE_MSK        0x1
++#define MCE_PRI             (0x3 << 9)
++  GEN_VDMA_ACFG(chn, REG_MCE_CH1_STAT, 0, ((1 & STAT_PFE_MSK )<<STAT_PFE_SFT ) |
++		((1 & STAT_LKE_MSK )<<STAT_LKE_SFT ) |
++		((1 & STAT_TKE_MSK )<<STAT_TKE_SFT ) );
++  GEN_VDMA_ACFG(chn, REG_MCE_CH2_STAT, 0, ((1 & STAT_PFE_MSK )<<STAT_PFE_SFT ) |
++		((1 & STAT_LKE_MSK )<<STAT_LKE_SFT ) |
++		((1 & STAT_TKE_MSK )<<STAT_TKE_SFT ) );
++  GEN_VDMA_ACFG(chn, (REG_MCE_CTRL), 0, MCE_COMP_AUTO_EXPD | MCE_CH2_EN | MCE_CLKG_EN | MCE_PRI |
++		MCE_OFA_EN | MCE_CACHE_FLUSH | MCE_EN );
++  GEN_VDMA_ACFG(chn, (REG_MCE_CH1_BINFO), 0, MCE_BINFO(AryFMT[intpid], 0, 0, 0, SubPel[intpid]-1));
++  GEN_VDMA_ACFG(chn, (REG_MCE_CH2_BINFO), 0, MCE_BINFO(0, 0, 0, 0, 0));
++
++  GEN_VDMA_ACFG(chn, (REG_MCE_CH1_PINFO), 0, 0);
++  GEN_VDMA_ACFG(chn, (REG_MCE_CH2_PINFO), 0, 0);
++
++  for(i=0; i<16; i++){
++    GEN_VDMA_ACFG(chn, REG_MCE_CH1_RLUT+(i)*8, 0, MCE_RLUT_WT(0,0,st_h264->luma_weight[0][i], st_h264->luma_offset[0][i]));
++    GEN_VDMA_ACFG(chn, REG_MCE_CH1_RLUT+(i)*8+4, 0, st_h264->mc_ref_y[0][i]);
++    GEN_VDMA_ACFG(chn, REG_MCE_CH2_RLUT+(i)*8, 0, MCE_RLUT_WT(st_h264->chroma_weight[0][i][1], st_h264->chroma_offset[0][i][1],
++							      st_h264->chroma_weight[0][i][0], st_h264->chroma_offset[0][i][0]));
++    GEN_VDMA_ACFG(chn, REG_MCE_CH2_RLUT+(i)*8+4, 0, st_h264->mc_ref_c[0][i]);
++    GEN_VDMA_ACFG(chn, REG_MCE_CH1_RLUT+(16+i)*8, 0, MCE_RLUT_WT(0,0,st_h264->luma_weight[1][i], st_h264->luma_offset[1][i]));
++    GEN_VDMA_ACFG(chn, REG_MCE_CH1_RLUT+(16+i)*8+4, 0, st_h264->mc_ref_y[1][i]);
++    GEN_VDMA_ACFG(chn, REG_MCE_CH2_RLUT+(16+i)*8, 0, MCE_RLUT_WT(st_h264->chroma_weight[1][i][1], st_h264->chroma_offset[1][i][1],
++								 st_h264->chroma_weight[1][i][0], st_h264->chroma_offset[1][i][0]));
++    GEN_VDMA_ACFG(chn, REG_MCE_CH2_RLUT+(16+i)*8+4, 0, st_h264->mc_ref_c[1][i]);
++  }
++
++  for(j=0; j<16; j++){
++    for(i=0; i<16; i+=4){
++      GEN_VDMA_ACFG(chn, (MOTION_IWTA_BASE+j*16+i), 0, *((int*)(&st_h264->implicit_weight[j][i])));
++    }
++  }
++  GEN_VDMA_ACFG(chn, REG_MCE_IWTA, 0, MOTION_IWTA_BASE);
++
++  GEN_VDMA_ACFG(chn, (REG_MCE_CH1_WINFO), 0, MCE_WINFO(0, (st_h264->use_weight == IS_WT1),
++						       st_h264->use_weight, 1, st_h264->luma_log2_weight_denom, 5, 0, 0));
++  GEN_VDMA_ACFG(chn, (REG_MCE_CH1_WTRND), 0, MCE_WTRND(0, 1<<5));
++  GEN_VDMA_ACFG(chn, (REG_MCE_CH2_WINFO1), 0, MCE_WINFO(0, st_h264->use_weight_chroma && (st_h264->use_weight == IS_WT1),
++							st_h264->use_weight, 1, st_h264->chroma_log2_weight_denom, 5, 0, 0));
++  GEN_VDMA_ACFG(chn, (REG_MCE_CH2_WINFO2), 0, MCE_WINFO(0, 0, 0, 0, 0, 5, 0, 0));
++  GEN_VDMA_ACFG(chn, (REG_MCE_CH2_WTRND), 0, MCE_WTRND(1<<5, 1<<5));
++
++  GEN_VDMA_ACFG(chn, REG_MCE_CH1_STRD, 0, MCE_STRD(st_h264->mb_width*16, 0, DOUT_Y_STRD));
++  GEN_VDMA_ACFG(chn, REG_MCE_GEOM, 0, MCE_GEOM(st_h264->mb_height*16,st_h264->mb_width*16));
++  GEN_VDMA_ACFG(chn, REG_MCE_CH2_STRD, 0, MCE_STRD(st_h264->mb_width*16, 0, DOUT_C_STRD));
++  GEN_VDMA_ACFG(chn, REG_MCE_DSA, 0, VPU_BASE + REG_SCH_SCHE1);
++  GEN_VDMA_ACFG(chn, REG_MCE_DDC, 0, MC_DESP_ADDR);
++
++  /*------------------------------------------------------
++    sde
++    ------------------------------------------------------*/
++  // multi-slice
++#if 0
++  int start_mb_num= st_h264->start_mb_x + st_h264->start_mb_y * st_h264->mb_width;
++  int slice_start_mx = st_h264->start_mb_x;
++  int slice_start_my = st_h264->start_mb_y;
++  if (st_h264->slice_num == 0) {
++    for (i=0; i<32; i++)
++      st_h264->curr_frm_slice_start_mb[i] = INT_MAX;
++  }
++  int ref_frm_start_mb = 0;
++  if ( (st_h264->slice_type == JZM_H264_B_TYPE) && (st_h264->slice_num)) {
++    for (i=0; i<32; i++){
++      if ( (start_mb_num >= st_h264->ref_frm_slice_start_mb[i]) &&
++	   (start_mb_num < st_h264->ref_frm_slice_start_mb[i+1]) )
++	break;
++    }
++    ref_frm_start_mb = st_h264->ref_frm_slice_start_mb[i];
++  }
++  st_h264->curr_frm_slice_start_mb[st_h264->slice_num] = start_mb_num;
++#else
++  int start_mb_num = st_h264->start_mb_x + st_h264->start_mb_y * st_h264->mb_width;
++  int slice_start_mx = st_h264->start_mb_x;
++  int slice_start_my = st_h264->start_mb_y;
++  int ref_frm_start_mb = start_mb_num;
++#endif
++
++  // bs init
++  unsigned int bs_addr = st_h264->bs_buffer;
++  unsigned int bs_ofst = st_h264->bs_index;
++#if 0
++  for (i=0; i<sde_bs_len; i++) {
++    ((int*)sde_bs_buffer)[i] = ((int*)bs_addr)[i];
++  }
++  bs_addr = sde_bs_buffer;
++#endif
++
++  GEN_VDMA_ACFG(chn, REG_SDE_STAT, 0, 0);
++  GEN_VDMA_ACFG(chn, REG_SDE_SL_GEOM, 0, SDE_SL_GEOM(st_h264->mb_height,st_h264->mb_width,slice_start_my,slice_start_mx));
++  GEN_VDMA_ACFG(chn, REG_SDE_GL_CTRL, 0, 1);
++  GEN_VDMA_ACFG(chn, REG_SDE_CODEC_ID, 0, (1 << 0));
++  unsigned int cfg_0 = (((!st_h264->cabac) << 0) +
++			(((st_h264->slice_type) & 0x7) << 1) +
++			(((st_h264->field_picture) & 0x1) << 4) +
++			(((st_h264->transform_8x8_mode) & 0x1) << 5) +
++			(((st_h264->constrained_intra_pred) & 0x1) << 6) +
++			(((st_h264->direct_8x8_inference_flag) & 0x1) << 7) +
++			(((st_h264->direct_spatial_mv_pred) & 0x1) << 8) +
++			((1 & 0x1) << 9) + /*dir_max_word_64*/
++			(((st_h264->x264_build > 33) & 0x1) << 10) +
++			(((!st_h264->x264_build) & 0x1) << 11) +
++			((st_h264->dblk_left_en & 0x1) << 14) +
++			((st_h264->dblk_top_en & 0x1) << 15) +
++			((st_h264->ref_count_0 & 0xF) << 16) +
++			((st_h264->ref_count_1 & 0xF) << 20) +
++			((bs_ofst & 0x1F) << 24) +
++			0 );
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG0, 0, cfg_0);
++  unsigned int cfg_1 = (((st_h264->qscale & 0xFF) << 0) +
++			(((st_h264->deblocking_filter) & 0x1) << 8) +
++			0);
++  //GEN_VDMA_ACFG(chn, REG_SDE_CFG1, 0, cfg_1 );
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG1, 0, (cfg_1 +
++				       ((st_h264->bs_rbsp_en & 0x1) << 16)) );
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG2, 0, bs_addr);
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG3, 0, TOP_NEI_ADDR);
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG4, 0, RESIDUAL_DOUT_ADDR);
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG5, 0, VMAU_DESP_ADDR);
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG6, 0, DBLK_DESP_ADDR);
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG7, 0, DBLK_MV_ADDR);
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG8, 0, MC_DESP_ADDR);
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG9, 0,  st_h264->ref_frm_ctrl  + ref_frm_start_mb*2*4);
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG10, 0, st_h264->ref_frm_mv    + ref_frm_start_mb*32*4);
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG11, 0, st_h264->curr_frm_ctrl + start_mb_num*2*4);
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG12, 0, st_h264->curr_frm_mv   + start_mb_num*32*4);
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG13, 0, (start_mb_num & 0xFFFF) + (((start_mb_num - ref_frm_start_mb) & 0xFFFF) << 16));
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG14, 0, st_h264->bs_size_in_bits);
++
++  // ctx table init
++  unsigned int * sde_table_base = REG_SDE_CTX_TBL;
++  if (st_h264->cabac) {
++    unsigned char state;
++    for( i= 0; i < 460; i++ ) {
++      int pre;
++      if( st_h264->slice_type == JZM_H264_I_TYPE )
++	pre = jzm_clip2( ((cabac_context_init_I[i][0] * st_h264->qscale) >>4 ) + cabac_context_init_I[i][1], 1, 126 );
++      else
++	pre = jzm_clip2( ((cabac_context_init_PB[st_h264->cabac_init_idc][i][0] * st_h264->qscale) >>4 ) + cabac_context_init_PB[st_h264->cabac_init_idc][i][1], 1, 126 );
++      if( pre <= 63 )
++	state = 2 * ( 63 - pre ) + 0;
++      else
++	state = 2 * ( pre - 64 ) + 1;
++      GEN_VDMA_ACFG(chn, sde_table_base+i, 0, lps_comb[state]);
++    }
++    GEN_VDMA_ACFG(chn, sde_table_base+276, 0, lps_comb[126]);
++  } else {
++    int tbl;
++    for (tbl = 0; tbl < 7; tbl++) {
++      unsigned int * hw_base = sde_table_base + (sde_vlc2_sta[tbl].ram_ofst >> 1);
++      unsigned int * tbl_base = (unsigned int *)&sde_vlc2_table[tbl][0];
++      int size = (sde_vlc2_sta[tbl].size + 1) >> 1;
++      for (i = 0; i < size; i++){
++	GEN_VDMA_ACFG(chn, hw_base+i, 0, tbl_base[i]);
++      }
++    }
++  }
++  // direct prediction scal table
++  for (i=0; i<16; i++) {
++    GEN_VDMA_ACFG(chn, sde_table_base + 480 + i, 0, st_h264->dir_scale_table[i]);
++  }
++  // set chroma_qp table
++  unsigned int * sde_cqp_tbl = REG_SDE_CQP_TBL;
++  for(i=0;i<128;i++) {
++    GEN_VDMA_ACFG(chn, sde_cqp_tbl + i, 0, st_h264->chroma_qp_table[i]);
++  }
++
++  GEN_VDMA_ACFG(chn, (REG_SDE_SL_CTRL), VDMA_ACFG_TERM, SDE_MB_RUN);
++}
++
++#endif // _JZM_H264_API_C_
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/api/jzm_h264_dec.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/api/jzm_h264_dec.h
+new file mode 100644
+index 000000000..e8943f8b2
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/api/jzm_h264_dec.h
+@@ -0,0 +1,125 @@
++#ifndef _JZM_H264_API_H_
++#define _JZM_H264_API_H_
++
++#include "jzm_vpu.h"
++
++/*-------------- vmem def --------------*/
++#define VRAM_TCSM1_BASE (VPU_BASE + 0xC0000)
++#define VRAM_SRAM_BASE  (VPU_BASE + 0xF0000)
++#ifdef  JZM_SIMPLE
++#define DESP_FIFO_WIDTH 3
++#else
++#define DESP_FIFO_WIDTH 4
++#endif //JZM_SIMPLE
++#define DESP_FIFO_DEPTH (1 << DESP_FIFO_WIDTH)
++#define VRAM_SCH_FIFO_DEPTH DESP_FIFO_DEPTH
++#define TOP_NEI_ADDR (VRAM_TCSM1_BASE)
++#ifdef  JZM_SIMPLE
++#define TOP_NEI_SIZE (80*16*4)
++#else
++#define TOP_NEI_SIZE (128*16*4)
++#endif //JZM_SIMPLE
++#define MC_DESP_ADDR (TOP_NEI_ADDR + TOP_NEI_SIZE)
++#define MC_DESP_ONE_SIZE (128*4)
++#define MC_DESP_SIZE (MC_DESP_ONE_SIZE*DESP_FIFO_DEPTH)
++#define DBLK_MV_ADDR (MC_DESP_ADDR + MC_DESP_SIZE)
++#define DBLK_MV_ONE_SIZE (64*4)
++#define DBLK_MV_SIZE (DBLK_MV_ONE_SIZE*DESP_FIFO_DEPTH)
++#define VMAU_DESP_ADDR (DBLK_MV_ADDR + DBLK_MV_SIZE)
++#define VMAU_DESP_ONE_SIZE (16*4)
++#define VMAU_DESP_SIZE (VMAU_DESP_ONE_SIZE*DESP_FIFO_DEPTH)
++#define DBLK_DESP_ADDR (VMAU_DESP_ADDR + VMAU_DESP_SIZE)
++#define DBLK_DESP_ONE_SIZE (8*4)
++#define DBLK_DESP_SIZE (DBLK_DESP_ONE_SIZE*DESP_FIFO_DEPTH)
++#define MOTION_IWTA_BASE ((DBLK_DESP_ADDR+DBLK_DESP_SIZE + 1024) & 0xFFFFFC00)
++#define MOTION_IWTA_SIZE (2048)
++#define MOTION_DSA_BASE (MOTION_IWTA_BASE + MOTION_IWTA_SIZE)
++#define MAU_ENDF_BASE (MOTION_DSA_BASE+4)//(MAU_SRC_BASE + MAU_SRC_SIZE)
++#define DBLK_ENDF_BASE ( MAU_ENDF_BASE + 4 )
++#define DBLK_GP_ENDF_BASE ( DBLK_ENDF_BASE + 4 )
++#define TCSM1_END (MAU_SRC_BASE+MAU_SRC_SIZE)
++#define RESIDUAL_DOUT_ADDR (VRAM_SRAM_BASE)
++#define RESIDUAL_DOUT_ONE_SIZE (256*4)
++#define RESIDUAL_DOUT_SIZE (RESIDUAL_DOUT_ONE_SIZE*DESP_FIFO_DEPTH)
++#define SRAM_END (RESIDUAL_DOUT_ADDR+RESIDUAL_DOUT_SIZE)
++#define PMON_BUF (SRAM_END)
++
++/*----------------------------*/
++#define JZM_H264_I_TYPE 1
++#define JZM_H264_P_TYPE 2
++#define JZM_H264_B_TYPE 4
++
++#define ROA_ALN     256
++#define DOUT_Y_STRD 16
++#define DOUT_C_STRD 8
++
++typedef struct JZM_H264{
++  unsigned short start_mb_x;
++  unsigned short start_mb_y;
++  unsigned short mb_width;
++  unsigned short mb_height;
++  unsigned char slice_num;
++  unsigned char slice_type;
++  unsigned char qscale;                       /* s->qscale */
++  unsigned char field_picture;
++  unsigned char cabac;                        /* h->pps.cabac */
++  unsigned char transform_8x8_mode;           /* !!h->pps.transform_8x8_mode */
++  unsigned char constrained_intra_pred;       /* !!h->pps.constrained_intra_pred */
++  unsigned char direct_8x8_inference_flag;    /* !!h->pps.direct_8x8_inference_flag */
++  unsigned char direct_spatial_mv_pred;       /* !!h->direct_spatial_mv_pred */
++  unsigned char ref_count_0;                  /* h->ref_count[0] */
++  unsigned char ref_count_1;                  /* h->ref_count[1] */
++  unsigned char deblocking_filter;            /* !!h->deblocking_filter */
++  int dblk_left_en;
++  int dblk_top_en;
++  int x264_build;                   /* h->x264_build */
++  int slice_alpha_c0_offset;
++  int slice_beta_offset;
++  unsigned long bs_buffer;           /* s->gb.buffer */
++  unsigned int bs_index;            /* s->gb.index */
++  unsigned int bs_size_in_bits;            /* s->gb.index */
++  int cabac_init_idc;
++/*   int * curr_frm_slice_start_mb; */
++/*   int * ref_frm_slice_start_mb; */
++  unsigned int ref_frm_ctrl;
++  unsigned int ref_frm_mv;
++  unsigned int curr_frm_ctrl;
++  unsigned int curr_frm_mv;
++  unsigned int dir_scale_table[16];
++  unsigned int chroma_qp_table[128];
++  unsigned char scaling_matrix8[6][64]; //2x64
++  unsigned char scaling_matrix4[6][16];
++  unsigned int tlb_phy_addr;
++  unsigned int dec_result_y;
++  unsigned int dec_result_uv;
++  unsigned int mc_ref_y[2][16];
++  unsigned int mc_ref_c[2][16];
++  unsigned int luma_weight[2][16];
++  unsigned int luma_offset[2][16];
++  unsigned int chroma_weight[2][16][2];
++  unsigned int chroma_offset[2][16][2];
++  unsigned char implicit_weight[16][16];
++  unsigned int use_weight;
++  unsigned int use_weight_chroma;
++  unsigned int luma_log2_weight_denom;
++  unsigned int chroma_log2_weight_denom;
++  int * des_va, * des_pa;
++  unsigned char new_odma_flag;
++  unsigned char new_odma_format; //0: nv12, 1: nv21.
++  unsigned int dec_result1_y;
++  unsigned int dec_result1_uv;
++  unsigned int frm_y_stride;
++  unsigned int frm_c_stride;
++  unsigned int bs_rbsp_en;
++} jzm_h264;
++
++struct SDE_VLC_STA
++{
++  int ram_ofst;
++  int size;
++  int lvl0_len;
++};
++
++extern void jzm_h264_slice_init_vdma(struct JZM_H264 * st_h264);
++
++#endif // _JZM_H264_API_H_
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/api/jzm_vpu.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/api/jzm_vpu.h
+new file mode 100644
+index 000000000..dd4d69495
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/api/jzm_vpu.h
+@@ -0,0 +1,2674 @@
++/****************************************************************
++*****************************************************************/
++#ifndef __JZM_VPU_H__
++#define __JZM_VPU_H__
++
++/****************************************************************
++  VPU register map
++*****************************************************************/
++
++#ifdef JZM_HUNT_SIM
++# include "hunt.h"
++#else
++# define __place_k0_data__
++# define __place_k0_text__
++#endif
++
++#define VPU_BASE             0x13200000
++
++#define	HID_SCH	             0x0
++#define	HID_VDMA	     0x1
++#define	HID_EFE	             0x4
++#define	HID_MCE		     0x5
++#define	HID_DBLK	     0x7
++#define	HID_VMAU	     0x8
++#define	HID_SDE		     0x9
++#define	HID_AUX		     0xA
++#define	HID_TCSM	     0xB
++#define	HID_JPGC	     0xE
++#define HID_SRAM             0xF
++
++#define VPU_MAX_MB_WIDTH     256
++
++#define MSCOPE_START(mbnum)  write_reg(VPU_BASE+0x24, mbnum)
++#define MSCOPE_STOP()        write_reg(VPU_BASE+0x28, 0)
++
++/********************************************
++  SCH (Scheduler)
++*********************************************/
++#define TCSM_FLUSH           0xc0000
++#define REG_SCH_GLBC         0x00000
++#define SCH_GLBC_SLDE        (0x1<<31)
++#define SCH_GLBC_TLBE        (0x1<<30)
++#define SCH_GLBC_TLBINV      (0x1<<29)
++#define SCH_INTE_ACFGERR     (0x1<<20)
++#define SCH_INTE_TLBERR      (0x1<<18)
++#define SCH_INTE_BSERR       (0x1<<17)
++#define SCH_INTE_ENDF        (0x1<<16)
++#define SCH_GLBC_HIMAP       (0x1<<15)
++#define SCH_GLBC_HIAXI       (0x1<<9)
++#define SCH_GLBC_EPRI0       (0x0<<7)
++#define SCH_GLBC_EPRI1       (0x1<<7)
++#define SCH_GLBC_EPRI2       (0x2<<7)
++#define SCH_GLBC_EPRI3       (0x3<<7)
++
++#define REG_SCH_TLBA         0x00030
++
++#define REG_SCH_STAT         0x00034
++
++#define REG_SCH_SLDE0        0x00040
++#define REG_SCH_SLDE1        0x00044
++#define REG_SCH_SLDE2        0x00048
++#define REG_SCH_SLDE3        0x0004C
++#define SCH_SLD_VTAG(val)    (((val) & 0xFFF)<<20)
++#define SCH_SLD_MASK(val)    (((val) & 0xFFF)<<8)
++#define SCH_SLD_VLD          (0x1<<0)
++
++#define REG_SCH_SCHC         0x00060
++#define SCH_CH1_PCH(ch)      (((ch) & 0x3)<<0)
++#define SCH_CH2_PCH(ch)      (((ch) & 0x3)<<8)
++#define SCH_CH3_PCH(ch)      (((ch) & 0x3)<<16)
++#define SCH_CH4_PCH(ch)      (((ch) & 0x3)<<24)
++#define SCH_CH1_PE           (0x1<<2)
++#define SCH_CH2_PE           (0x1<<10)
++#define SCH_CH3_PE           (0x1<<18)
++#define SCH_CH4_PE           (0x1<<26)
++#define SCH_CH1_GS0          (0x0<<3)
++#define SCH_CH1_GS1          (0x1<<3)
++#define SCH_CH2_GS0          (0x0<<11)
++#define SCH_CH2_GS1          (0x1<<11)
++#define SCH_CH3_GS0          (0x0<<19)
++#define SCH_CH3_GS1          (0x1<<19)
++#define SCH_CH4_GS0          (0x0<<27)
++#define SCH_CH4_GS1          (0x1<<27)
++
++#define REG_SCH_BND          0x00064
++#define SCH_CH1_HID(hid)     (((hid) & 0xF)<<16)
++#define SCH_CH2_HID(hid)     (((hid) & 0xF)<<20)
++#define SCH_CH3_HID(hid)     (((hid) & 0xF)<<24)
++#define SCH_CH4_HID(hid)     (((hid) & 0xF)<<28)
++#define SCH_BND_G0F1         (0x1<<0)
++#define SCH_BND_G0F2         (0x1<<1)
++#define SCH_BND_G0F3         (0x1<<2)
++#define SCH_BND_G0F4         (0x1<<3)
++#define SCH_BND_G1F1         (0x1<<4)
++#define SCH_BND_G1F2         (0x1<<5)
++#define SCH_BND_G1F3         (0x1<<6)
++#define SCH_BND_G1F4         (0x1<<7)
++#define SCH_DEPTH(val)       (((val-1) & 0xF)<<8)
++
++#define REG_SCH_SCHG0        0x00068
++#define REG_SCH_SCHG1        0x0006C
++#define REG_SCH_SCHE1        0x00070
++#define REG_SCH_SCHE2        0x00074
++#define REG_SCH_SCHE3        0x00078
++#define REG_SCH_SCHE4        0x0007C
++
++#define DSA_SCH_CH1          (VPU_BASE | REG_SCH_SCHE1)
++#define DSA_SCH_CH2          (VPU_BASE | REG_SCH_SCHE2)
++#define DSA_SCH_CH3          (VPU_BASE | REG_SCH_SCHE3)
++#define DSA_SCH_CH4          (VPU_BASE | REG_SCH_SCHE4)
++
++/********************************************
++  VDMA (VPU general-purpose DMA)
++*********************************************/
++#define REG_VDMA_LOCK        0x10000
++#define REG_VDMA_UNLK        0x10004
++
++#define REG_VDMA_TASKRG      0x10008
++#define VDMA_ACFG_RUN        (0x1)
++#define VDMA_DESC_RUN        (0x3)
++#define VDMA_ACFG_CLR        (0x8)
++#define VDMA_ACFG_SAFE       (0x4)
++#define VDMA_ACFG_DHA(a)     (((unsigned int)(a)) & 0xFFFFFF80)
++#define VDMA_DESC_DHA(a)     (((unsigned int)(a)) & 0xFFFF0)
++
++#define REG_VDMA_TASKST      0x1000C
++#define VDMA_ACFG_ERR        (0x1<<3)
++#define VDMA_ACFG_END        (0x1<<2)
++#define VDMA_DESC_END        (0x1<<1)
++#define VDMA_VPU_BUSY        (0x1<<0)
++
++#define VDMA_DESC_EXTSEL     (0x1<<0)
++#define VDMA_DESC_TLBSEL     (0x1<<1)
++#define VDMA_DESC_LK         (0x1<<31)
++
++#define VDMA_ACFG_VLD        (0x1<<31)
++#define VDMA_ACFG_TERM       (0x1<<30)
++#define VDMA_ACFG_IDX(a)     (((unsigned int)(a)) & 0xFFFFC)
++
++#define GEN_VDMA_ACFG(chn, reg, lk, val)                 \
++({*chn++ = val;                                          \
++  *chn++ = (VDMA_ACFG_VLD | (lk) | VDMA_ACFG_IDX(reg));  \
++})
++
++/********************************************
++  EFE (Encoder Front End)
++*********************************************/
++#define REG_EFE_CTRL         0x40000
++#define EFE_BP_MBY(mb)       (((mb) & 0xFF)<<24)
++#define EFE_BP_MBX(mb)       (((mb) & 0xFF)<<16)
++#define EFE_X264_QP(qp)      (((qp) & 0x3F)<<8)
++#define EFE_DBLK_EN          (0x1<<5)
++#define EFE_SLICE_TYPE(a)    (((a) & 0x1)<<4)
++#define EFE_DEBUG_EN         (0x1<<2)
++#define EFE_EN               (0x1<<1)
++#define EFE_RUN              (0x1<<0)
++
++#define REG_EFE_GEOM         0x40004
++#define EFE_FST_MBY(mb)      (((mb) & 0xFF)<<24)
++#define EFE_FST_MBX(mb)      (((0/*FIXME*/) & 0xFF)<<16)
++#define EFE_LST_MBY(mb)      (((mb) & 0xFF)<<8)
++#define EFE_LST_MBX(mb)      (((mb) & 0xFF)<<0)
++
++#define REG_EFE_COEF_BA      0x4000C
++#define REG_EFE_RAWY_SBA     0x40010
++#define REG_EFE_RAWC_SBA     0x40014
++#define REG_EFE_TOPMV_BA     0x40018
++#define REG_EFE_TOPPA_BA     0x4001C
++#define REG_EFE_MECHN_BA     0x40020
++#define REG_EFE_MAUCHN_BA    0x40024
++#define REG_EFE_DBLKCHN_BA   0x40028
++#define REG_EFE_SDECHN_BA    0x4002C
++#define REG_EFE_RAW_DBA      0x40030
++#define REG_EFE_MVRP         0x40100
++#define REG_EFE_STAT         0x40110
++
++/********************************************
++  MCE (Motion Compensation/Estimation COMBO)
++*********************************************/
++#define REG_MCE_CTRL         0x50000
++#define MCE_ESTI_MAX_BDIA(a) (((a) & 0xF)<<28)
++#define MCE_ESTI_MAX_SDIA(a) (((a) & 0xF)<<24)
++#define MCE_ESTI_USE_PMV     (0x1<<22)
++#define MCE_ESTI_INTPEL      (0x0<<20)
++#define MCE_ESTI_HPEL        (0x2<<20)
++#define MCE_ESTI_QPEL        (0x3<<20)
++#define MCE_ESTI_PUT_MET     (0x1<<19)
++#define MCE_COMP_AUTO_EXPD   (0x1<<17)
++#define MCE_CH2_EN           (0x1<<11)
++#define MCE_CLKG_EN          (0x1<<8)
++#define MCE_OFA_EN           (0x1<<7)
++#define MCE_MODE_COMP        (0x0<<4)
++#define MCE_MODE_ESTI        (0x1<<4)
++#define MCE_CACHE_FLUSH      (0x1<<3)
++#define MCE_EN               (0x1<<0)
++
++#define REG_MCE_CH1_STAT     0x50004
++#define REG_MCE_CH2_STAT     0x50804
++#define MCE_PREF_END         (0x1<<2)
++#define MCE_LINK_END         (0x1<<1)
++#define MCE_TASK_END         (0x1<<0)
++
++#define REG_MCE_MVPA         0x5000C
++#define REG_MCE_IWTA         0x5000C
++
++#define REG_MCE_CH1_PINFO    0x50020
++#define REG_MCE_CH2_PINFO    0x50820
++#define MCE_PINFO(rgr, its, its_sft, its_scale, its_rnd) \
++( ((rgr) & 0x1)<<31 |                                    \
++  ((its) & 0x1)<<28 |                                    \
++  ((its_sft) & 0x7)<<24 |                                \
++  ((its_scale) & 0xFF)<<16 |                             \
++  ((its_rnd) & 0xFFFF)<<0                                \
++)
++
++#define REG_MCE_CH1_WINFO    0x50024
++#define REG_MCE_CH2_WINFO1   0x50824
++#define REG_MCE_CH2_WINFO2   0x50828
++#define MCE_WINFO(wt, wtpd, wtmd, biavg_rnd, wt_denom,   \
++                  wt_sft, wt_lcoef, wt_rcoef)            \
++( ((wt) & 0x1)<<31 |                                     \
++  ((wtpd) & 0x1)<<30 |                                   \
++  ((wtmd) & 0x3)<<28 |                                   \
++  ((biavg_rnd) & 0x1)<<27 |                              \
++  ((wt_denom) & 0x7)<<24 |                               \
++  ((wt_sft) & 0xF)<<16 |                                 \
++  ((wt_lcoef) & 0xFF)<<8 |                               \
++  ((wt_rcoef) & 0xFF)<<0                                 \
++)
++
++#define REG_MCE_CH1_WTRND    0x5002C
++#define REG_MCE_CH2_WTRND    0x5082C
++#define MCE_WTRND(wt2_rnd, wt1_rnd)                      \
++( ((wt2_rnd) & 0xFFFF)<<16 |                             \
++  ((wt1_rnd) & 0xFFFF)<<0                                \
++)
++
++#define REG_MCE_CH1_BINFO    0x50030
++#define REG_MCE_CH2_BINFO    0x50830
++#define MCE_BINFO(ary, expdy, expdx, ilmd, pel)          \
++( ((ary) & 0x1)<<31 |                                    \
++  ((expdy) & 0xF)<<24 |                                  \
++  ((expdx) & 0xF)<<20 |                                  \
++  ((ilmd) & 0x3)<<16 |                                   \
++  ((pel) & 0x3)<<14                                      \
++)
++
++#define REG_MCE_CH1_IINFO1   0x50034
++#define REG_MCE_CH1_IINFO2   0x50038
++#define MCE_CH1_IINFO(intp, tap, pkg, hldgl, avsdgl,     \
++                      intp_dir, intp_rnd, intp_sft,      \
++                      sintp, sintp_rnd, sintp_bias)      \
++( ((intp) & 0x1)<<31 |                                   \
++  ((tap) & 0x3)<<28 |                                    \
++  ((pkg) & 0x1)<<27 |                                    \
++  ((hldgl) & 0x1)<<26 |                                  \
++  ((avsdgl) & 0x1)<<25 |                                 \
++  ((intp_dir) & 0x1)<<24 |                               \
++  ((intp_rnd) & 0xFF)<<16 |                              \
++  ((intp_sft) & 0xF)<<8 |                                \
++  ((sintp) & 0x1)<<2 |                                   \
++  ((sintp_rnd) & 0x1)<<1 |                               \
++  ((sintp_bias) & 0x1)<<0                                \
++)
++
++#define REG_MCE_CH2_IINFO1   0x50834
++#define REG_MCE_CH2_IINFO2   0x50838
++#define MCE_CH2_IINFO(intp, intp_dir, intp_sft,          \
++                      intp_lcoef, intp_rcoef, intp_rnd)  \
++( ((intp) & 0x1)<<31 |                                   \
++  ((intp_dir) & 0x1)<<15 |                               \
++  ((intp_sft) & 0x7)<<12 |                               \
++  ((intp_lcoef) & 0x7)<<9 |                              \
++  ((intp_rcoef) & 0x7)<<6 |                              \
++  ((intp_rnd) & 0x3F)<<0                                 \
++)
++
++#define REG_MCE_CH1_TAP1L    0x5003C
++#define REG_MCE_CH1_TAP2L    0x50040
++#define REG_MCE_CH1_TAP1M    0x50044
++#define REG_MCE_CH1_TAP2M    0x50048
++#define MCE_CH1_TAP(c1, c2, c3, c4)                      \
++( ((c4) & 0xFF)<<24 |                                    \
++  ((c3) & 0xFF)<<16 |                                    \
++  ((c2) & 0xFF)<<8 |                                     \
++  ((c1) & 0xFF)<<0                                       \
++)
++
++#define REG_MCE_CH1_STRD     0x5004C
++#define REG_MCE_CH2_STRD     0x5084C
++#define MCE_STRD(ref_strd, raw_strd, dst_strd)           \
++( ((ref_strd) & 0xFFF)<<16 |                             \
++  ((raw_strd) & 0xFF)<<8 |                               \
++  ((dst_strd) & 0xFF)<<0                                 \
++)
++
++#define REG_MCE_GEOM         0x50050
++#define MCE_GEOM(frm_height, frm_width)                  \
++( ((frm_height) & 0xFFF)<<16 |                           \
++  ((frm_width) & 0xFFF)<<0                               \
++)
++
++#define REG_MCE_DDC          0x50054
++#define MCE_TDD_RUN          0x1<<0
++
++#define REG_MCE_DSA          0x50058
++
++#define REG_MCE_ESTIC        0x5005C
++#define MCE_ESTIC(fsct, fsst, fsce, fsse)                \
++( ((fsct) & 0xFFFF)<<16 |                                \
++  ((fsst) & 0xF)<<4 |                                    \
++  ((fsce) & 0x1)<<1 |                                    \
++  ((fsse) & 0x1)<<0                                      \
++)
++
++#define REG_MCE_CH1_RLUT     0x50300
++#define REG_MCE_CH2_RLUT     0x50B00
++#define MCE_RLUT_WT(wcoef2, wofst2, wcoef1, wofst1)      \
++( ((wcoef2) & 0xFF)<<24 |                                \
++  ((wofst2) & 0xFF)<<16 |                                \
++  ((wcoef1) & 0xFF)<<8 |                                 \
++  ((wofst1) & 0xFF)<<0                                   \
++)
++
++#define REG_MCE_CH1_CLUT     0x50400
++
++#define REG_MCE_CH1_ILUT     0x50500
++#define REG_MCE_CH2_ILUT     0x50D00
++
++/*Motion TDD*/
++#define MCE_TDD_COMP_HEAD(vld, lk, ch1pel, ch2pel,       \
++                          posmd, mvmd, tkn, mby, mbx)    \
++( ((vld) & 0x1)<<31 |                                    \
++  ((lk) & 0x1)<<30 |                                     \
++  ((ch1pel) & 0x1)<<27 |                                 \
++  ((ch2pel) & 0x3)<<25 |                                 \
++  ((posmd) & 0x1)<<24 |                                  \
++  ((mvmd) & 0x1)<<23 |                                   \
++  ((tkn) & 0x7F)<<16 |                                   \
++  ((mby) & 0xFF)<<8 |                                    \
++  ((mbx) & 0xFF)<<0                                      \
++)
++#define MCE_TDD_COMP_MV(mvy, mvx)                        \
++( ((mvy) & 0xFFFF)<<16 |                                 \
++  ((mvx) & 0xFFFF)<<0                                    \
++)
++#define MCE_TDD_COMP_CMD(bidir, refdir, fld, fldsel,     \
++                         rgr, its, doe,	cflo, ypos,      \
++                         lilmd, cilmd, list,		 \
++		         boy, box, bh, bw, pos) 	 \
++( ((bidir) & 0x1)<<31 |                                  \
++  ((refdir) & 0x1)<<30 |                                 \
++  ((fld) & 0x1)<<29 |                                    \
++  ((fldsel) & 0x1)<<28 |                                 \
++  ((rgr) & 0x1)<<27 |                                    \
++  ((its) & 0x1)<<26 |                                    \
++  ((doe) & 0x1)<<25 |                                    \
++  ((cflo) & 0x1)<<24 |                                   \
++  ((ypos) & 0xF)<<20 |                                   \
++  ((lilmd) & 0x3)<<18 |                                  \
++  ((cilmd) & 0x3)<<16 |                                  \
++  ((list) & 0xF)<<12 |                                   \
++  ((boy) & 0x3)<<10 |                                    \
++  ((box) & 0x3)<<8 |                                     \
++  ((bh) & 0x3)<<6 |                                      \
++  ((bw) & 0x3)<<4 |                                      \
++  ((pos) & 0xF)<<0                                       \
++)
++#define MCE_TDD_ESTI(vld, lk, dmy, pmc, list,            \
++                     boy, box, bh, bw, mby, mbx)         \
++( ((vld) & 0x1)<<31 |                                    \
++  ((lk) & 0x1)<<30 |                                     \
++  ((dmy) & 0x1)<<27 |                                    \
++  ((pmc) & 0x1)<<26 |                                    \
++  ((list) & 0x3)<<24 |                                   \
++  ((boy) & 0x3)<<22 |                                    \
++  ((box) & 0x3)<<20 |                                    \
++  ((bh) & 0x3)<<18 |                                     \
++  ((bw) & 0x3)<<16 |                                     \
++  ((mby) & 0xFF)<<8 |                                    \
++  ((mbx) & 0xFF)<<0                                      \
++)
++#define MCE_TDD_CFG(vld, lk, cidx)                       \
++( 0x1<<28 |                                              \
++  ((vld) & 0x1)<<31 |                                    \
++  ((lk) & 0x1)<<30 |                                     \
++  ((cidx) & 0xFFF)<<0                                    \
++)
++#define MCE_TDD_SYNC(vld, lk, crst, id)                  \
++( 0x1<<29 |                                              \
++  ((vld) & 0x1)<<31 |                                    \
++  ((lk) & 0x1)<<30 |                                     \
++  ((crst) & 0x1)<<27 |                                   \
++  ((id) & 0xFFFF)<<0                                     \
++)
++
++/********************************************
++  VMAU (VPU Matrix Arithmetic Unit)
++*********************************************/
++#define REG_VMAU_MCBP        0x80000
++
++#define REG_VMAU_QTPARA      0x80004
++
++#define REG_VMAU_MAIN_ADDR   0x80008
++
++#define REG_VMAU_NCCHN_ADDR  0x8000C
++
++#define REG_VMAU_CHN_LEN     0x80010
++
++#define REG_VMAU_ACBP        0x80014
++
++#define REG_VMAU_CPREDM_TLV  0x80018
++
++#define REG_VMAU_YPREDM0     0x8001C
++
++#define REG_VMAU_YPREDM1     0x80020
++
++#define REG_VMAU_GBL_RUN     0x80040
++#define VMAU_RUN             0x1
++#define VMAU_STOP            0x2
++#define VMAU_RESET           0x4
++
++#define REG_VMAU_GBL_CTR     0x80044
++#define VMAU_CTRL_FIFO_M     0x1
++#define VMAU_CTRL_IRQ_EN     0x10
++#define VMAU_CTRL_SLPOW      0x10000
++#define VMAU_CTRL_TO_DBLK    0x1000000
++
++#define REG_VMAU_STATUS      0x80048
++
++#define REG_VMAU_CCHN_ADDR   0x8004C
++
++#define REG_VMAU_VIDEO_TYPE  0x80050
++#define VMAU_FMT_H264        0x1
++#define VMAU_FMT_RV9         0x2
++#define VMAU_FMT_VC1         0x3
++#define VMAU_FMT_MPEG2       0x4
++#define VMAU_FMT_MPEG4       0x5
++#define VMAU_FMT_VP8         0x6
++#define VMAU_MODE_DEC        (0x0<<11)
++#define VMAU_MODE_ENC        (0x1<<11)
++
++#define REG_VMAU_Y_GS        0x80054
++
++#define REG_VMAU_DEC_DONE    0x80058
++
++#define REG_VMAU_ENC_DONE    0x8005C
++
++#define REG_VMAU_POS         0x80060
++
++#define REG_VMAU_MCF_STA     0x80064
++
++#define REG_VMAU_DEC_YADDR   0x80068
++
++#define REG_VMAU_DEC_UADDR   0x8006C
++
++#define REG_VMAU_DEC_VADDR   0x80070
++
++#define REG_VMAU_DEC_STR     0x80074
++
++#define REG_VMAU_MEML        0x84000
++#define REG_VMAU_QT          0x88000
++
++/********************************************
++  DBLK (deblock)
++*********************************************/
++#define REG_DBLK_DHA         0x70000
++
++#define REG_DBLK_TRIG        0x70060
++#define DBLK_RUN             0x1
++#define DBLK_STOP            0x2
++#define DBLK_RESET           0x4
++#define DBLK_SLICE_RUN       0x8
++
++#define REG_DBLK_CTRL        0x70064
++#define DBLK_CTRL(expand, rotate, loop_filter)           \
++( ((expand) & 0x1)<<4 |                                  \
++  ((rotate) & 0x3)<<1 |                                  \
++  ((loop_filter) & 0x1)<<0                               \
++)
++
++#define REG_DBLK_VTR         0x70068
++#define DBLK_FMT_H264        0x1
++#define DBLK_FMT_RV9         0x2
++#define DBLK_FMT_VC1         0x3
++#define DBLK_FMT_MPEG2       0x4
++#define DBLK_FMT_MPEG4       0x5
++#define DBLK_FMT_VP8         0x6
++#define DBLK_FRM_I           0x0
++#define DBLK_FRM_P           0x1
++#define DBLK_FRM_B           0x2
++#define DBLK_VTR(beta, alpha, vp8_spl, vp8_kf,           \
++                 frm_typ, video_fmt)                     \
++( ((beta) & 0xFF)<<24 |                                  \
++  ((alpha) & 0xFF)<<16 |                                 \
++  ((vp8_spl) & 0x1)<<9 |                                 \
++  ((vp8_kf) & 0x1)<<5 |                                  \
++  ((frm_typ) & 0x3)<<3 |                                 \
++  ((video_fmt) & 0x7)<<0                                 \
++)
++
++#define REG_DBLK_FSTA        0x7006C
++
++#define REG_DBLK_GSTA        0x70070
++
++#define REG_DBLK_GSIZE       0x70074
++#define DBLK_GSIZE(mb_height, mb_width)                  \
++( ((mb_height) & 0xFFFF)<<16 |                           \
++  ((mb_width) & 0xFFFF)<<0                               \
++)
++
++#define REG_DBLK_GENDA       0x70078
++
++#define REG_DBLK_GPOS        0x7007C
++#define DBLK_GPOS(first_mby, first_mbx)                  \
++( ((first_mby) & 0xFFFF)<<16 |                           \
++  ((first_mbx) & 0xFFFF)<<0                              \
++)
++
++#define REG_DBLK_GPIC_STR    0x70080
++#define DBLK_GPIC_STR(dst_strd_c, dst_strd_y)            \
++( ((dst_strd_c) & 0xFFFF)<<16 |                          \
++  ((dst_strd_y) & 0xFFFF)<<0                             \
++)
++
++#define REG_DBLK_GPIC_YA     0x70084
++
++#define REG_DBLK_GPIC_CA     0x70088
++
++#define REG_DBLK_GP_ENDA     0x7008C
++
++#define REG_DBLK_SLICE_ENDA  0x70090
++
++#define REG_DBLK_BLK_CTRL    0x70094
++
++#define REG_DBLK_BLK_FIFO    0x70098
++
++#define REG_DBLK_GPIC_Y1A    0x700A0
++
++#define REG_DBLK_GPIC_C1A    0x700A4
++
++#define REG_DBLK_GPIC_STR1   0x700A8
++
++/********************************************
++  SDE (stream parser/encoding)
++*********************************************/
++#define REG_SDE_STAT         0x90000
++
++#define REG_SDE_SL_CTRL      0x90004
++#define SDE_SLICE_INIT       (0x1<<1)
++#define SDE_MB_RUN           (0x1<<0)
++
++#define REG_SDE_SL_GEOM      0x90008
++#define SDE_SL_GEOM(mb_height, mb_width,                 \
++                    first_mby, first_mbx)                \
++( ((mb_height) & 0xFF)<<24 |                             \
++  ((mb_width) & 0xFF)<<16 |                              \
++  ((first_mby) & 0xFF)<<8 |                              \
++  ((first_mbx) & 0xFF)<<0                                \
++)
++
++#define REG_SDE_GL_CTRL      0x9000C
++#define SDE_BP(mby, mbx)                                 \
++( ((mby) & 0xFF)<<24 |                                   \
++  ((mbx) & 0xFF)<<16                                     \
++)
++#define SDE_MODE_AUTO        (0x0<<4)
++#define SDE_MODE_STEP        (0x1<<4)
++#define SDE_MODE_DEBUG       (0x2<<4)
++#define SDE_EN               (0x1<<0)
++
++#define REG_SDE_CODEC_ID     0x90010
++#define SDE_FMT_H264_DEC     (0x1<<0)
++#define SDE_FMT_H264_ENC     (0x1<<1)
++#define SDE_FMT_VP8_DEC      (0x1<<2)
++#define SDE_FMT_VC1_DEC      (0x1<<3)
++#define SDE_FMT_MPEG2_DEC    (0x1<<4)
++
++#define REG_SDE_CFG0         0x90014
++#define REG_SDE_CFG1         0x90018
++#define REG_SDE_CFG2         0x9001C
++#define REG_SDE_CFG3         0x90020
++#define REG_SDE_CFG4         0x90024
++#define REG_SDE_CFG5         0x90028
++#define REG_SDE_CFG6         0x9002C
++#define REG_SDE_CFG7         0x90030
++#define REG_SDE_CFG8         0x90034
++#define REG_SDE_CFG9         0x90038
++#define REG_SDE_CFG10        0x9003C
++#define REG_SDE_CFG11        0x90040
++#define REG_SDE_CFG12        0x90044
++#define REG_SDE_CFG13        0x90048
++#define REG_SDE_CFG14        0x9004C
++#define REG_SDE_CFG15        0x90050
++
++#define REG_SDE_CTX_TBL      0x92000
++#define REG_SDE_CQP_TBL      0x93800
++
++/****************************************************************
++  VPU tables
++*****************************************************************/
++/********************************************
++  Motion interpolation programable table
++*********************************************/
++#define IS_SKIRT  0
++#define IS_MIRROR 1
++
++#define IS_BIAVG  0
++#define IS_WT1    1
++#define IS_WT2    2
++#define IS_FIXWT  3
++
++#define IS_ILUT0  0
++#define IS_ILUT1  2
++#define IS_EC     1
++
++#define IS_TCS     1
++#define NOT_TCS    0
++#define IS_SCS     1
++#define NOT_SCS    0
++#define IS_HLDGL   1
++#define NOT_HLDGL  0
++#define IS_AVSDGL  1
++#define NOT_AVSDGL 0
++
++#define INTP_HDIR  0
++#define INTP_VDIR  1
++
++enum IntpID {
++  MPEG_HPEL = 0,
++  MPEG_QPEL,
++  H264_QPEL,
++  H264_EPEL,
++  RV8_TPEL,
++  RV9_QPEL,
++  RV9_CPEL,
++  WMV2_QPEL,
++  VC1_QPEL,
++  AVS_QPEL,
++  VP6_QPEL,
++  VP8_QPEL,
++  VP8_EPEL,
++  VP8_BIL,
++  VP8_FPEL, /*full-pixel for chroma*/
++};
++
++enum PosID {
++  H0V0 = 0,
++  H1V0,
++  H2V0,
++  H3V0,
++  H0V1,
++  H1V1,
++  H2V1,
++  H3V1,
++  H0V2,
++  H1V2,
++  H2V2,
++  H3V2,
++  H0V3,
++  H1V3,
++  H2V3,
++  H3V3,
++};
++
++enum TapTYP {
++  TAP2 = 0,
++  TAP4,
++  TAP6,
++  TAP8,
++};
++
++enum SPelSFT {
++  HPEL = 1,
++  QPEL,
++  EPEL,
++};
++
++typedef struct IntpFMT_t{
++  char tap;
++  char intp_pkg[2];
++  char hldgl;
++  char avsdgl;
++  char intp[2];
++  char intp_dir[2];
++  char intp_coef[2][8];
++  char intp_rnd[2];
++  char intp_sft[2];
++  char intp_sintp[2];
++  char intp_srnd[2];
++  char intp_sbias[2];
++}IntpFMT_t;
++
++__place_k0_data__
++static char AryFMT[] = {IS_SKIRT, IS_MIRROR, IS_SKIRT, IS_SKIRT,
++			IS_SKIRT, IS_SKIRT, IS_SKIRT, IS_SKIRT,
++			IS_SKIRT, IS_SKIRT, IS_SKIRT, IS_SKIRT,
++			IS_SKIRT, IS_SKIRT, IS_SKIRT, IS_SKIRT};
++
++__place_k0_data__
++static char SubPel[] = {HPEL, QPEL, QPEL, EPEL,
++			QPEL, QPEL, QPEL, QPEL,
++			QPEL, QPEL, QPEL, QPEL,
++			EPEL, HPEL, QPEL, QPEL};
++
++__place_k0_data__
++static IntpFMT_t IntpFMT[][16] = {
++  {
++    /************* MPEG_HPEL ***************/
++    {/*H0V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0},
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0},
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0},
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H2V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0},
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0},
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H0V1*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0},
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V1*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2},
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H2V1*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2},
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V1*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2},
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H0V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0},
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2},
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H2V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2},
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2},
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H0V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0},
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2},
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H2V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2},
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2},
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++  },
++
++  {
++    /************* MPEG_QPEL ***************/
++    {/*H0V0*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0},
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0},
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1},{0},},
++      {/*intp_rnd*/15, 0},
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1},{0},},
++      {/*intp_rnd*/15, 0},
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1},{0},},
++      {/*intp_rnd*/15, 0},
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H0V1*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1},{0},},
++      {/*intp_rnd*/15, 0},
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15},
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/1, 1},
++      {/*intp_srnd*/1, 1},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15},
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15},
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/1, 1},
++      {/*intp_srnd*/1, 1},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H0V2*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1},{0},},
++      {/*intp_rnd*/15, 0},
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15},
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15},
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15},
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H0V3*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1},{0},},
++      {/*intp_rnd*/15, 0},
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H1V3*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15},
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/1, 1},
++      {/*intp_srnd*/1, 1},
++      {/*intp_sbias*/0, 1},
++    },
++    {/*H2V3*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15},
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 1},
++    },
++    {/*H3V3*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15},
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/1, 1},
++      {/*intp_srnd*/1, 1},
++      {/*intp_sbias*/1, 1},
++    },
++  },
++
++  {
++    /************* H264_QPEL ***************/
++    {/*H0V0*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0},
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0},
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/16, 0},
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/16, 0},
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/16, 0},
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H0V1*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/16, 0},
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP6, {NOT_TCS, IS_SCS}, IS_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 16},
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 0},
++      {/*intp_sft*/5, 10},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/
++      TAP6, {NOT_TCS, IS_SCS}, IS_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 16},
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H0V2*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/16, 0},
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 0},
++      {/*intp_sft*/5, 10},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 0},
++      {/*intp_sft*/5, 10},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 0},
++      {/*intp_sft*/5, 10},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 1},
++    },
++    {/*H0V3*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/16, 0},
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H1V3*/
++      TAP6, {NOT_TCS, IS_SCS}, IS_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 16},
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 1},
++    },
++    {/*H2V3*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 0},
++      {/*intp_sft*/5, 10},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 1},
++    },
++    {/*H3V3*/
++      TAP6, {NOT_TCS, IS_SCS}, IS_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 16},
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/1, 1},
++    },
++  },
++
++  {
++    /************* H264_EPEL ***************/
++    {/*H0V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0},
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0},
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/0},
++    {/*H2V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/4, 0},
++      {/*intp_sft*/3, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V0*/0},
++    {/*H0V1*/0},
++    {/*H1V1*/0},
++    {/*H2V1*/0},
++    {/*H3V1*/0},
++    {/*H0V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/4, 0},
++      {/*intp_sft*/3, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V2*/0},
++    {/*H2V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/0, 32},
++      {/*intp_sft*/0, 6},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V2*/0},
++    {/*H0V3*/0},
++    {/*H1V3*/0},
++    {/*H2V3*/0},
++    {/*H3V3*/0},
++  },
++
++  {
++    /************* RV8_TPEL ***************/
++    {/*H0V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0},
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0},
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{-1, 12, 6, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0},
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{-1, 6, 12, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0},
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/0},
++    {/*H0V1*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{-1, 12, 6, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0},
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 12, 6, -1, 0, 0, 0, 0}, {-1, 12, 6, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/8, 0}, //{0,128}
++      {/*intp_sft*/0, 8},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 6, 12, -1, 0, 0, 0, 0}, {-1, 12, 6, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/8, 0}, //{0,128}
++      {/*intp_sft*/0, 8},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/0},
++    {/*H0V2*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{-1, 6, 12, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0},
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 12, 6, -1, 0, 0, 0, 0}, {-1, 6, 12, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/8, 0}, //{0,128}
++      {/*intp_sft*/0, 8},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 6, 12, -1, 0, 0, 0, 0}, {-1, 6, 12, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/8, 0}, //{0,128}
++      {/*intp_sft*/0, 8},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/0},
++    {/*H0V3*/0},
++    {/*H1V3*/0},
++    {/*H2V3*/0},
++    {/*H3V3*/0},
++  },
++
++  {
++    /************* RV9_QPEL ***************/
++    {/*H0V0*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0},
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0},
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{1, -5, 52, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/32, 0},
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/16, 0},
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{1, -5, 20, 52, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/32, 0},
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V1*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{1, -5, 52, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/32, 0},
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -5, 52, 20, -5, 1, 0, 0}, {1, -5, 52, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/32, 32},
++      {/*intp_sft*/6, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 52, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 32},
++      {/*intp_sft*/5, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -5, 20, 52, -5, 1, 0, 0}, {1, -5, 52, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/32, 32},
++      {/*intp_sft*/6, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V2*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/16, 0},
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -5, 52, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/32, 16},
++      {/*intp_sft*/6, 5},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 16},
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -5, 20, 52, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/32, 16},
++      {/*intp_sft*/6, 5},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V3*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{1, -5, 20, 52, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/32, 0},
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V3*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -5, 52, 20, -5, 1, 0, 0}, {1, -5, 20, 52, -5, 1, 0, 0},},
++      {/*intp_rnd*/32, 32},
++      {/*intp_sft*/6, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V3*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 52, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 32},
++      {/*intp_sft*/5, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 2},
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++  },
++
++  {
++    /************* RV9_CPEL ***************/
++    {/*H0V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0},
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0},
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0},
++      {/*intp_sft*/2, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0},
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0},
++      {/*intp_sft*/2, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V1*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/2, 0},
++      {/*intp_sft*/2, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0}, {3, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 7},
++      {/*intp_sft*/0, 4},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {3, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 4},
++      {/*intp_sft*/0, 3},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0}, {3, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 7},
++      {/*intp_sft*/0, 4},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0},
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 4},
++      {/*intp_sft*/0, 3},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 1},
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 4},
++      {/*intp_sft*/0, 3},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/2, 0},
++      {/*intp_sft*/2, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0}, {1, 3, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 7},
++      {/*intp_sft*/0, 4},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 3, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 4},
++      {/*intp_sft*/0, 3},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 1},
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++  },
++
++  {
++    /************* WMV2_QPEL ***************/
++    {/*H0V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0},
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0},
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0},
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0},
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0},
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H0V1*/0},
++    {/*H1V1*/0},
++    {/*H2V1*/0},
++    {/*H3V1*/0},
++    {/*H0V2*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0},
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR},
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0}, {-1, 9, 9, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/8, 8},
++      {/*intp_sft*/4, 4},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR},
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0}, {-1, 9, 9, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/8, 8},
++      {/*intp_sft*/4, 4},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR},
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0}, {-1, 9, 9, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/8, 8},
++      {/*intp_sft*/4, 4},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 1},
++    },
++    {/*H0V3*/0},
++    {/*H1V3*/0},
++    {/*H2V3*/0},
++    {/*H3V3*/0},
++  },
++
++  {
++    /************* VC1_QPEL ***************/
++    {/*H0V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0},
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0},
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{-4, 53, 18, -3, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/32, 0},
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0},
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{-3, 18, 53, -4, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/32, 0},
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V1*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{-4, 53, 18, -3, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/31, 0},
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR},
++      {/*intp_coef*/{-4, 53, 18, -3, 0, 0, 0, 0}, {-4, 53, 18, -3, 0, 0, 0, 0},},
++      {/*intp_rnd*/31, 32},
++      {/*intp_sft*/6, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR},
++      {/*intp_coef*/{-4, 53, 18, -3, 0, 0, 0, 0}, {-1, 9, 9, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/31, 8},
++      {/*intp_sft*/6, 4},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR},
++      {/*intp_coef*/{-4, 53, 18, -3, 0, 0, 0, 0}, {-3, 18, 53, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/31, 32},
++      {/*intp_sft*/6, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V2*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/7, 0},
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR},
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0}, {-4, 53, 18, -3, 0, 0, 0, 0},},
++      {/*intp_rnd*/7, 32},
++      {/*intp_sft*/4, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR},
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0}, {-1, 9, 9, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/7, 8},
++      {/*intp_sft*/4, 4},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR},
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0}, {-3, 18, 53, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/7, 32},
++      {/*intp_sft*/4, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V3*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{-3, 18, 53, -4, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/31, 0},
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V3*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR},
++      {/*intp_coef*/{-3, 18, 53, -4, 0, 0, 0, 0}, {-4, 53, 18, -3, 0, 0, 0, 0},},
++      {/*intp_rnd*/31, 32},
++      {/*intp_sft*/6, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V3*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR},
++      {/*intp_coef*/{-3, 18, 53, -4, 0, 0, 0, 0}, {-1, 9, 9, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/31, 8},
++      {/*intp_sft*/6, 4},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V3*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR},
++      {/*intp_coef*/{-3, 18, 53, -4, 0, 0, 0, 0}, {-3, 18, 53, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/31, 32},
++      {/*intp_sft*/6, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++  },
++
++  {
++    /************* AVS_QPEL ***************/
++    {/*H0V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0},
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0},
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{-1, -2, 96, 42, -7, 0, 0, 0},{0},},
++      {/*intp_rnd*/64, 0},
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{-1, 5, 5, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/4, 0},
++      {/*intp_sft*/3, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{0, -7, 42, 96, -2, -1, 0, 0},{0},},
++      {/*intp_rnd*/64, 0},
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V1*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{-1, -2, 96, 42, -7, 0, 0, 0},{0},},
++      {/*intp_rnd*/64, 0},
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, IS_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 5, 5, -1, 0, 0, 0, 0}, {-1, 5, -5, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 32},
++      {/*intp_sft*/0, 6},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{0, -1, 5, 5, -1, 0, 0, 0}, {-1, -2, 96, 42, -7, 0, 0, 0},},
++      {/*intp_rnd*/64, 0}, //{0,512}
++      {/*intp_sft*/0, 10},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, IS_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 5, 5, -1, 0, 0, 0, 0}, {-1, 5, -5, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 32},
++      {/*intp_sft*/0, 6},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H0V2*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{-1, 5, 5, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/4, 0},
++      {/*intp_sft*/3, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, -2, 96, 42, -7, 0, 0, 0}, {0, -1, 5, 5, -1, 0, 0, 0},},
++      {/*intp_rnd*/64, 0}, //{0,512}
++      {/*intp_sft*/0, 10},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 5, 5, -1, 0, 0, 0, 0}, {-1, 5, 5, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 32},
++      {/*intp_sft*/0, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{0, -7, 42, 96, -2, -1, 0, 0}, {0, -1, 5, 5, -1, 0, 0, 0},},
++      {/*intp_rnd*/64, 0}, //{0,512}
++      {/*intp_sft*/0, 10},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V3*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{0, -7, 42, 96, -2, -1, 0, 0}, {0},},
++      {/*intp_rnd*/64, 0},
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V3*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, IS_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 5, 5, -1, 0, 0, 0, 0}, {-1, 5, -5, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 32},
++      {/*intp_sft*/0, 6},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 1},
++    },
++    {/*H2V3*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{0, -1, 5, 5, -1, 0, 0, 0}, {0, -7, 42, 96, -2, -1, 0, 0},},
++      {/*intp_rnd*/64, 0}, //{0,512}
++      {/*intp_sft*/0, 10},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V3*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, IS_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 5, 5, -1, 0, 0, 0, 0}, {-1, 5, -5, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 32},
++      {/*intp_sft*/0, 6},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/1, 1},
++    },
++  },
++
++  {
++    /************* VP6_QPEL ***************/
++    {/*H0V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0},
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0},
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{-4, 109, 24, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/64, 0},
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{-4, 68, 68, -4, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/64, 0},
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{-1, 24, 109, -4, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/64, 0},
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V1*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{-4, 109, 24, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/64, 0},
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-4, 109, 24, -1, 0, 0, 0, 0}, {-4, 109, 24, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-4, 68, 68, -4, 0, 0, 0, 0}, {-4, 109, 24, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 24, 109, -4, 0, 0, 0, 0}, {-4, 109, 24, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V2*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{-4, 68, 68, -4, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/64, 0},
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-4, 109, 24, -1, 0, 0, 0, 0}, {-4, 68, 68, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-4, 68, 68, -4, 0, 0, 0, 0}, {-4, 68, 68, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 24, 109, -4, 0, 0, 0, 0}, {-4, 68, 68, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V3*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{-1, 24, 109, -4, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/64, 0},
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V3*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-4, 109, 24, -1, 0, 0, 0, 0}, {-1, 24, 109, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V3*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-4, 68, 68, -4, 0, 0, 0, 0}, {-1, 24, 109, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V3*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{-1, 24, 109, -4, 0, 0, 0, 0}, {-1, 24, 109, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++  },
++
++  {
++    /************* VP8_QPEL ***************/
++    {/*H0V0*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0},
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0},
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{2, -11, 108, 36, -8, 1, 0, 0},{0},},
++      {/*intp_rnd*/64, 0},
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{3, -16, 77, 77, -16, 3, 0, 0},{0},},
++      {/*intp_rnd*/64, 0},
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{1, -8, 36, 108, -11, 2, 0, 0},{0},},
++      {/*intp_rnd*/64, 0},
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V1*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{2, -11, 108, 36, -8, 1, 0, 0}, {0},},
++      {/*intp_rnd*/64, 0},
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{2, -11, 108, 36, -8, 1, 0, 0}, {2, -11, 108, 36, -8, 1, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{3, -16, 77, 77, -16, 3, 0, 0}, {2, -11, 108, 36, -8, 1, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -8, 36, 108, -11, 2, 0, 0}, {2, -11, 108, 36, -8, 1, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V2*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{3, -16, 77, 77, -16, 3, 0, 0},{0},},
++      {/*intp_rnd*/64, 0},
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{2, -11, 108, 36, -8, 1, 0, 0}, {3, -16, 77, 77, -16, 3, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{3, -16, 77, 77, -16, 3, 0, 0}, {3, -16, 77, 77, -16, 3, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -8, 36, 108, -11, 2, 0, 0}, {3, -16, 77, 77, -16, 3, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V3*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{1, -8, 36, 108, -11, 2, 0, 0},{0},},
++      {/*intp_rnd*/64, 0},
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V3*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{2, -11, 108, 36, -8, 1, 0, 0}, {1, -8, 36, 108, -11, 2, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V3*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{3, -16, 77, 77, -16, 3, 0, 0}, {1, -8, 36, 108, -11, 2, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V3*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, -8, 36, 108, -11, 2, 0, 0}, {1, -8, 36, 108, -11, 2, 0, 0},},
++      {/*intp_rnd*/64, 64},
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++  },
++
++  {
++    /************* VP8_EPEL ***************/
++    {/*H0V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0},
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0},
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/0},
++    {/*H2V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/4, 0},
++      {/*intp_sft*/3, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V0*/0},
++    {/*H0V1*/0},
++    {/*H1V1*/0},
++    {/*H2V1*/0},
++    {/*H3V1*/0},
++    {/*H0V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/4, 0},
++      {/*intp_sft*/3, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V2*/0},
++    {/*H2V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/4, 4},
++      {/*intp_sft*/3, 3},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V2*/0},
++    {/*H0V3*/0},
++    {/*H1V3*/0},
++    {/*H2V3*/0},
++    {/*H3V3*/0},
++  },
++
++  {
++    /************* VP8_BIL ***************/
++    {/*H0V0*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0},
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0},
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/2, 0},
++      {/*intp_sft*/2, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H2V0*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0},
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V0*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0},
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/2, 0},
++      {/*intp_sft*/2, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H0V1*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/2, 0},
++      {/*intp_sft*/2, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V1*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0},{3, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/2, 2},
++      {/*intp_sft*/2, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H2V1*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{3, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/1, 2},
++      {/*intp_sft*/1, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V1*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0},{3, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/2, 2},
++      {/*intp_sft*/2, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H0V2*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0},
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V2*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0},{1, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/2, 1},
++      {/*intp_sft*/2, 1},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H2V2*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{1, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/1, 1},
++      {/*intp_sft*/1, 1},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V2*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0},{1, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/2, 1},
++      {/*intp_sft*/2, 1},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H0V3*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0},
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/2, 0},
++      {/*intp_sft*/2, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V3*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0},{1, 3, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/2, 2},
++      {/*intp_sft*/2, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H2V3*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{1, 3, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/1, 2},
++      {/*intp_sft*/1, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V3*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR},
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0},{1, 3, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/2, 2},
++      {/*intp_sft*/2, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++  },
++
++  {
++    /************* VP8_FPEL ***************/
++    {/*H0V0*/0},
++    {/*H1V0*/0},
++    {/*H2V0*/0},
++    {/*H3V0*/0},
++    {/*H0V1*/0},
++    {/*H1V1*/0},
++    {/*H2V1*/0},
++    {/*H3V1*/0},
++    {/*H0V2*/0},
++    {/*H1V2*/0},
++    {/*H2V2*/0},
++    {/*H3V2*/0},
++    {/*H0V3*/0},
++    {/*H1V3*/0},
++    {/*H2V3*/0},
++    {/*H3V3*/0},
++  },
++};
++
++#endif /*__JZM_VPU_H__*/
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/avassert.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/avassert.h
+new file mode 100644
+index 000000000..c71f51f1e
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/avassert.h
+@@ -0,0 +1,53 @@
++#ifndef AVUTIL_AVASSERT_H
++#define AVUTIL_AVASSERT_H
++
++#ifdef __KERNEL__
++#else
++#include <stdlib.h>
++#endif
++//#include "avutil.h"
++#include "log.h"
++
++/**
++ * assert() equivalent, that is always enabled.
++ */
++#define av_assert0(cond) do {                                           \
++    if (!(cond)) {                                                      \
++        av_log(NULL, AV_LOG_PANIC, "Assertion %s failed at %s:%d\n",    \
++               cond, __FILE__, __LINE__);                 \
++    }                                                                   \
++} while (0)
++
++#define assert(cond)	av_assert0(cond)
++
++
++/**
++ * assert() equivalent, that does not lie in speed critical code.
++ * These asserts() thus can be enabled without fearing speed loss.
++ */
++#if defined(ASSERT_LEVEL) && ASSERT_LEVEL > 0
++#define av_assert1(cond) av_assert0(cond)
++#else
++#define av_assert1(cond) ((void)0)
++#endif
++
++
++/**
++ * assert() equivalent, that does lie in speed critical code.
++ */
++#if defined(ASSERT_LEVEL) && ASSERT_LEVEL > 1
++#define av_assert2(cond) av_assert0(cond)
++#define av_assert2_fpu() av_assert0_fpu()
++#else
++#define av_assert2(cond) ((void)0)
++#define av_assert2_fpu() ((void)0)
++#endif
++
++/**
++ * Assert that floating point operations can be executed.
++ *
++ * This will av_assert0() that the cpu is not in MMX state on X86
++ */
++void av_assert0_fpu(void);
++
++#endif /* AVUTIL_AVASSERT_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/avcodec.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/avcodec.h
+new file mode 100644
+index 000000000..b312fe4d7
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/avcodec.h
+@@ -0,0 +1,404 @@
++#ifndef __AVCODEC_H__
++#define __AVCODEC_H__
++
++#include "buffer.h"
++#include "frame.h"
++
++/**
++ * Allow decoders to produce frames with data planes that are not aligned
++ * to CPU requirements (e.g. due to cropping).
++ */
++#define AV_CODEC_FLAG_UNALIGNED       (1 <<  0)
++/**
++ * Use fixed qscale.
++ */
++#define AV_CODEC_FLAG_QSCALE          (1 <<  1)
++/**
++ * 4 MV per MB allowed / advanced prediction for H.263.
++ */
++#define AV_CODEC_FLAG_4MV             (1 <<  2)
++/**
++ * Output even those frames that might be corrupted.
++ */
++#define AV_CODEC_FLAG_OUTPUT_CORRUPT  (1 <<  3)
++/**
++ * Use qpel MC.
++ */
++#define AV_CODEC_FLAG_QPEL            (1 <<  4)
++/**
++ * Use internal 2pass ratecontrol in first pass mode.
++ */
++#define AV_CODEC_FLAG_PASS1           (1 <<  9)
++/**
++ * Use internal 2pass ratecontrol in second pass mode.
++ */
++#define AV_CODEC_FLAG_PASS2           (1 << 10)
++/**
++ * loop filter.
++ */
++#define AV_CODEC_FLAG_LOOP_FILTER     (1 << 11)
++/**
++ * Only decode/encode grayscale.
++ */
++#define AV_CODEC_FLAG_GRAY            (1 << 13)
++/**
++ * error[?] variables will be set during encoding.
++ */
++#define AV_CODEC_FLAG_PSNR            (1 << 15)
++/**
++ * Input bitstream might be truncated at a random location
++ * instead of only at frame boundaries.
++ */
++#define AV_CODEC_FLAG_TRUNCATED       (1 << 16)
++/**
++ * Use interlaced DCT.
++ */
++#define AV_CODEC_FLAG_INTERLACED_DCT  (1 << 18)
++/**
++ * Force low delay.
++ */
++#define AV_CODEC_FLAG_LOW_DELAY       (1 << 19)
++/**
++ * Place global headers in extradata instead of every keyframe.
++ */
++#define AV_CODEC_FLAG_GLOBAL_HEADER   (1 << 22)
++/**
++ * Use only bitexact stuff (except (I)DCT).
++ */
++#define AV_CODEC_FLAG_BITEXACT        (1 << 23)
++/* Fx : Flag for H.263+ extra options */
++/**
++ * H.263 advanced intra coding / MPEG-4 AC prediction
++ */
++#define AV_CODEC_FLAG_AC_PRED         (1 << 24)
++/**
++ * interlaced motion estimation
++ */
++#define AV_CODEC_FLAG_INTERLACED_ME   (1 << 29)
++#define AV_CODEC_FLAG_CLOSED_GOP      (1U << 31)
++
++/**
++ * Allow non spec compliant speedup tricks.
++ */
++#define AV_CODEC_FLAG2_FAST           (1 <<  0)
++/**
++ * Skip bitstream encoding.
++ */
++#define AV_CODEC_FLAG2_NO_OUTPUT      (1 <<  2)
++/**
++ * Place global headers at every keyframe instead of in extradata.
++ */
++#define AV_CODEC_FLAG2_LOCAL_HEADER   (1 <<  3)
++
++/**
++ * timecode is in drop frame format. DEPRECATED!!!!
++ */
++#define AV_CODEC_FLAG2_DROP_FRAME_TIMECODE (1 << 13)
++
++/**
++ * Input bitstream might be truncated at a packet boundaries
++ * instead of only at frame boundaries.
++ */
++#define AV_CODEC_FLAG2_CHUNKS         (1 << 15)
++/**
++ * Discard cropping information from SPS.
++ */
++#define AV_CODEC_FLAG2_IGNORE_CROP    (1 << 16)
++
++/**
++ * Show all frames before the first keyframe
++ */
++#define AV_CODEC_FLAG2_SHOW_ALL       (1 << 22)
++/**
++ * Export motion vectors through frame side data
++ */
++#define AV_CODEC_FLAG2_EXPORT_MVS     (1 << 28)
++/**
++ * Do not skip samples and export skip information as frame side data
++ */
++#define AV_CODEC_FLAG2_SKIP_MANUAL    (1 << 29)
++/**
++ * Do not reset ASS ReadOrder field on flush (subtitles decoding)
++ */
++#define AV_CODEC_FLAG2_RO_FLUSH_NOOP  (1 << 30)
++
++/**
++ * Identify the syntax and semantics of the bitstream.
++ * The principle is roughly:
++ * Two decoders with the same ID can decode the same streams.
++ * Two encoders with the same ID can encode compatible streams.
++ * There may be slight deviations from the principle due to implementation
++ * details.
++ *
++ * If you add a codec ID to this list, add it so that
++ * 1. no value of an existing codec ID changes (that would break ABI),
++ * 2. it is as close as possible to similar codecs
++ *
++ * After adding new codec IDs, do not forget to add an entry to the codec
++ * descriptor list and bump libavcodec minor version.
++ */
++enum AVCodecID {
++    AV_CODEC_ID_NONE,
++
++    AV_CODEC_ID_H264
++};
++
++
++typedef struct AVCodecContext {
++
++
++    int log_level_offset;
++
++    enum AVCodecID   codec_id;
++
++    /**
++     * AV_CODEC_FLAG_*.
++     * - encoding: Set by user.
++     * - decoding: Set by user.
++     */
++    int flags;
++
++    /**
++     * AV_CODEC_FLAG2_*
++     * - encoding: Set by user.
++     * - decoding: Set by user.
++     */
++    int flags2;
++
++    /**
++     * number of reference frames
++     * - encoding: Set by user.
++     * - decoding: Set by lavc.
++     */
++    int refs;
++
++    /* video only */
++    /**
++     * picture width / height.
++     *
++     * @note Those fields may not match the values of the last
++     * AVFrame output by avcodec_decode_video2 due frame
++     * reordering.
++     *
++     * - encoding: MUST be set by user.
++     * - decoding: May be set by the user before opening the decoder if known e.g.
++     *             from the container. Some decoders will require the dimensions
++     *             to be set by the caller. During decoding, the decoder may
++     *             overwrite those values as required while parsing the data.
++     */
++    int width, height;
++
++    /**
++     * Bitstream width / height, may be different from width/height e.g. when
++     * the decoded frame is cropped before being output or lowres is enabled.
++     *
++     * @note Those field may not match the value of the last
++     * AVFrame output by avcodec_receive_frame() due frame
++     * reordering.
++     *
++     * - encoding: unused
++     * - decoding: May be set by the user before opening the decoder if known
++     *             e.g. from the container. During decoding, the decoder may
++     *             overwrite those values as required while parsing the data.
++     */
++    int coded_width, coded_height;
++
++    /**
++     * Size of the frame reordering buffer in the decoder.
++     * For MPEG-2 it is 1 IPB or 0 low delay IP.
++     * - encoding: Set by libavcodec.
++     * - decoding: Set by libavcodec.
++     */
++    int has_b_frames;
++
++    /**
++     * debug
++     * - encoding: Set by user.
++     * - decoding: Set by user.
++     */
++    int debug;
++#define FF_DEBUG_PICT_INFO   1
++#define FF_DEBUG_RC          2
++#define FF_DEBUG_BITSTREAM   4
++#define FF_DEBUG_MB_TYPE     8
++#define FF_DEBUG_QP          16
++
++#define FF_DEBUG_DCT_COEFF   0x00000040
++#define FF_DEBUG_SKIP        0x00000080
++#define FF_DEBUG_STARTCODE   0x00000100
++#define FF_DEBUG_ER          0x00000400
++#define FF_DEBUG_MMCO        0x00000800
++#define FF_DEBUG_BUGS        0x00001000
++
++#define FF_DEBUG_BUFFERS     0x00008000
++#define FF_DEBUG_THREADS     0x00010000
++#define FF_DEBUG_GREEN_MD    0x00800000
++#define FF_DEBUG_NOMC        0x01000000
++
++    /**
++     * Error recognition; may misdetect some more or less valid parts as errors.
++     * - encoding: unused
++     * - decoding: Set by user.
++     */
++    int err_recognition;
++
++/**
++ * Verify checksums embedded in the bitstream (could be of either encoded or
++ * decoded data, depending on the codec) and print an error message on mismatch.
++ * If AV_EF_EXPLODE is also set, a mismatching checksum will result in the
++ * decoder returning an error.
++ */
++#define AV_EF_CRCCHECK  (1<<0)
++#define AV_EF_BITSTREAM (1<<1)          ///< detect bitstream specification deviations
++#define AV_EF_BUFFER    (1<<2)          ///< detect improper bitstream length
++#define AV_EF_EXPLODE   (1<<3)          ///< abort decoding on minor error detection
++
++#define AV_EF_IGNORE_ERR (1<<15)        ///< ignore errors and continue
++#define AV_EF_CAREFUL    (1<<16)        ///< consider things that violate the spec, are fast to calculate and have not been seen in the wild as errors
++#define AV_EF_COMPLIANT  (1<<17)        ///< consider all spec non compliances as errors
++#define AV_EF_AGGRESSIVE (1<<18)        ///< consider things that a sane encoder should not do as an error
++
++    /**
++     * profile
++     * - encoding: Set by user.
++     * - decoding: Set by libavcodec.
++     */
++     int profile;
++#define FF_PROFILE_UNKNOWN -99
++#define FF_PROFILE_RESERVED -100
++
++#define FF_PROFILE_AAC_MAIN 0
++#define FF_PROFILE_AAC_LOW  1
++#define FF_PROFILE_AAC_SSR  2
++#define FF_PROFILE_AAC_LTP  3
++#define FF_PROFILE_AAC_HE   4
++#define FF_PROFILE_AAC_HE_V2 28
++#define FF_PROFILE_AAC_LD   22
++#define FF_PROFILE_AAC_ELD  38
++#define FF_PROFILE_MPEG2_AAC_LOW 128
++#define FF_PROFILE_MPEG2_AAC_HE  131
++
++#define FF_PROFILE_DNXHD         0
++#define FF_PROFILE_DNXHR_LB      1
++#define FF_PROFILE_DNXHR_SQ      2
++#define FF_PROFILE_DNXHR_HQ      3
++#define FF_PROFILE_DNXHR_HQX     4
++#define FF_PROFILE_DNXHR_444     5
++
++#define FF_PROFILE_DTS         20
++#define FF_PROFILE_DTS_ES      30
++#define FF_PROFILE_DTS_96_24   40
++#define FF_PROFILE_DTS_HD_HRA  50
++#define FF_PROFILE_DTS_HD_MA   60
++#define FF_PROFILE_DTS_EXPRESS 70
++
++#define FF_PROFILE_MPEG2_422    0
++#define FF_PROFILE_MPEG2_HIGH   1
++#define FF_PROFILE_MPEG2_SS     2
++#define FF_PROFILE_MPEG2_SNR_SCALABLE  3
++#define FF_PROFILE_MPEG2_MAIN   4
++#define FF_PROFILE_MPEG2_SIMPLE 5
++
++#define FF_PROFILE_H264_CONSTRAINED  (1<<9)  // 8+1; constraint_set1_flag
++#define FF_PROFILE_H264_INTRA        (1<<11) // 8+3; constraint_set3_flag
++
++#define FF_PROFILE_H264_BASELINE             66
++#define FF_PROFILE_H264_CONSTRAINED_BASELINE (66|FF_PROFILE_H264_CONSTRAINED)
++#define FF_PROFILE_H264_MAIN                 77
++#define FF_PROFILE_H264_EXTENDED             88
++#define FF_PROFILE_H264_HIGH                 100
++#define FF_PROFILE_H264_HIGH_10              110
++#define FF_PROFILE_H264_HIGH_10_INTRA        (110|FF_PROFILE_H264_INTRA)
++#define FF_PROFILE_H264_MULTIVIEW_HIGH       118
++#define FF_PROFILE_H264_HIGH_422             122
++#define FF_PROFILE_H264_HIGH_422_INTRA       (122|FF_PROFILE_H264_INTRA)
++#define FF_PROFILE_H264_STEREO_HIGH          128
++#define FF_PROFILE_H264_HIGH_444             144
++#define FF_PROFILE_H264_HIGH_444_PREDICTIVE  244
++#define FF_PROFILE_H264_HIGH_444_INTRA       (244|FF_PROFILE_H264_INTRA)
++#define FF_PROFILE_H264_CAVLC_444            44
++
++#define FF_PROFILE_VC1_SIMPLE   0
++#define FF_PROFILE_VC1_MAIN     1
++#define FF_PROFILE_VC1_COMPLEX  2
++#define FF_PROFILE_VC1_ADVANCED 3
++
++#define FF_PROFILE_MPEG4_SIMPLE                     0
++#define FF_PROFILE_MPEG4_SIMPLE_SCALABLE            1
++#define FF_PROFILE_MPEG4_CORE                       2
++#define FF_PROFILE_MPEG4_MAIN                       3
++#define FF_PROFILE_MPEG4_N_BIT                      4
++#define FF_PROFILE_MPEG4_SCALABLE_TEXTURE           5
++#define FF_PROFILE_MPEG4_SIMPLE_FACE_ANIMATION      6
++#define FF_PROFILE_MPEG4_BASIC_ANIMATED_TEXTURE     7
++#define FF_PROFILE_MPEG4_HYBRID                     8
++#define FF_PROFILE_MPEG4_ADVANCED_REAL_TIME         9
++#define FF_PROFILE_MPEG4_CORE_SCALABLE             10
++#define FF_PROFILE_MPEG4_ADVANCED_CODING           11
++#define FF_PROFILE_MPEG4_ADVANCED_CORE             12
++#define FF_PROFILE_MPEG4_ADVANCED_SCALABLE_TEXTURE 13
++#define FF_PROFILE_MPEG4_SIMPLE_STUDIO             14
++#define FF_PROFILE_MPEG4_ADVANCED_SIMPLE           15
++
++#define FF_PROFILE_JPEG2000_CSTREAM_RESTRICTION_0   1
++#define FF_PROFILE_JPEG2000_CSTREAM_RESTRICTION_1   2
++#define FF_PROFILE_JPEG2000_CSTREAM_NO_RESTRICTION  32768
++#define FF_PROFILE_JPEG2000_DCINEMA_2K              3
++#define FF_PROFILE_JPEG2000_DCINEMA_4K              4
++
++#define FF_PROFILE_VP9_0                            0
++#define FF_PROFILE_VP9_1                            1
++#define FF_PROFILE_VP9_2                            2
++#define FF_PROFILE_VP9_3                            3
++
++#define FF_PROFILE_HEVC_MAIN                        1
++#define FF_PROFILE_HEVC_MAIN_10                     2
++#define FF_PROFILE_HEVC_MAIN_STILL_PICTURE          3
++#define FF_PROFILE_HEVC_REXT                        4
++
++#define FF_PROFILE_AV1_MAIN                         0
++#define FF_PROFILE_AV1_HIGH                         1
++#define FF_PROFILE_AV1_PROFESSIONAL                 2
++
++#define FF_PROFILE_MJPEG_HUFFMAN_BASELINE_DCT            0xc0
++#define FF_PROFILE_MJPEG_HUFFMAN_EXTENDED_SEQUENTIAL_DCT 0xc1
++#define FF_PROFILE_MJPEG_HUFFMAN_PROGRESSIVE_DCT         0xc2
++#define FF_PROFILE_MJPEG_HUFFMAN_LOSSLESS                0xc3
++#define FF_PROFILE_MJPEG_JPEG_LS                         0xf7
++
++#define FF_PROFILE_SBC_MSBC                         1
++
++    /**
++     * level
++     * - encoding: Set by user.
++     * - decoding: Set by libavcodec.
++     */
++     int level;
++#define FF_LEVEL_UNKNOWN -99
++
++    void *priv_data;
++
++} AVCodecContext;
++
++/**
++ * @ingroup lavc_decoding
++ * Required number of additionally allocated bytes at the end of the input bitstream for decoding.
++ * This is mainly needed because some optimized bitstream readers read
++ * 32 or 64 bit at once and could read over the end.<br>
++ * Note: If the first 23 bits of the additional bytes are not 0, then damaged
++ * MPEG bitstreams could cause overread and segfault.
++ */
++#define AV_INPUT_BUFFER_PADDING_SIZE 64
++
++
++typedef struct AVPacket {
++
++	uint8_t *data;
++	unsigned int data_pa;	/*physical address of data.*/
++	int	size;
++
++} AVPacket;
++
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/bswap.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/bswap.h
+new file mode 100644
+index 000000000..e63a3eab3
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/bswap.h
+@@ -0,0 +1,54 @@
++#ifndef AVUTIL_BSWAP_H
++#define AVUTIL_BSWAP_H
++
++//#include "libavutil/avconfig.h"
++//#include "attributes.h"
++
++#define AV_BSWAP16C(x) (((x) << 8 & 0xff00)  | ((x) >> 8 & 0x00ff))
++#define AV_BSWAP32C(x) (AV_BSWAP16C(x) << 16 | AV_BSWAP16C((x) >> 16))
++#define AV_BSWAP64C(x) (AV_BSWAP32C(x) << 32 | AV_BSWAP32C((x) >> 32))
++
++#define AV_BSWAPC(s, x) AV_BSWAP##s##C(x)
++
++#ifndef av_bswap16
++static inline const uint16_t av_bswap16(uint16_t x)
++{
++    x= (x>>8) | (x<<8);
++    return x;
++}
++#endif
++
++#ifndef av_bswap32
++static inline const uint32_t av_bswap32(uint32_t x)
++{
++    return AV_BSWAP32C(x);
++}
++#endif
++
++#ifndef av_bswap64
++static inline uint64_t const av_bswap64(uint64_t x)
++{
++    return (uint64_t)av_bswap32(x) << 32 | av_bswap32(x >> 32);
++}
++#endif
++
++// be2ne ... big-endian to native-endian
++// le2ne ... little-endian to native-endian
++
++#define av_be2ne16(x) av_bswap16(x)
++#define av_be2ne32(x) av_bswap32(x)
++#define av_be2ne64(x) av_bswap64(x)
++#define av_le2ne16(x) (x)
++#define av_le2ne32(x) (x)
++#define av_le2ne64(x) (x)
++#define AV_BE2NEC(s, x) AV_BSWAPC(s, x)
++#define AV_LE2NEC(s, x) (x)
++
++#define AV_BE2NE16C(x) AV_BE2NEC(16, x)
++#define AV_BE2NE32C(x) AV_BE2NEC(32, x)
++#define AV_BE2NE64C(x) AV_BE2NEC(64, x)
++#define AV_LE2NE16C(x) AV_LE2NEC(16, x)
++#define AV_LE2NE32C(x) AV_LE2NEC(32, x)
++#define AV_LE2NE64C(x) AV_LE2NEC(64, x)
++
++#endif /* AVUTIL_BSWAP_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/buffer.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/buffer.h
+new file mode 100644
+index 000000000..24b3b5dcf
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/buffer.h
+@@ -0,0 +1,70 @@
++#ifndef __BUFFER_H__
++#define __BUFFER_H__
++
++#include "devmem.h"
++
++#define DMA_TO_DEVICE		DEVMEM_SYNC_TO_DEVICE
++#define DMA_FROM_DEVICE 	DEVMEM_SYNC_FROM_DEVICE
++
++struct devmem_ctx;
++
++typedef struct devmem_ops {
++	int (*alloc)(struct devmem_ctx *ctx, devmem_info_t *di);
++	void (*free)(struct devmem_ctx *ctx, devmem_info_t *di);
++	void (*sync)(struct devmem_ctx *ctx, devmem_info_t *di);
++
++} devmem_ops_t;
++
++typedef struct devmem_ctx {
++	int fd;
++	devmem_ops_t *ops;
++	struct device *dev;
++} devmem_ctx_t;
++
++int devmem_ctx_init(devmem_ctx_t *ctx, devmem_ops_t *ops);
++void devmem_ctx_uninit(devmem_ctx_t *ctx);
++
++
++
++
++typedef struct AVBuffer {
++	unsigned char *buffer;
++	unsigned int buffer_pa;	/* physical address of buffer. */
++	unsigned int size;
++
++	devmem_info_t di;	/*mem info used by devmem allocator.*/
++} AVBuffer;
++
++
++
++
++/*
++ * create: 	use exists buffer fill AVBuffer struct.
++ * alloc:	allocate for AVBuffer.
++ * free:	free AVBuffer.
++ *
++ * */
++
++
++/**
++ * @brief 使用已�分�好的内存，创建AVBuffer结构体.
++ * 	  caller: 必须���内存有效.
++ *
++ * @param va  va 是虚拟地�
++ * @param pa  pa 是对应的物�地�，给到dma使用.
++ * @param size
++ * @param buf 输出buf.
++ *
++ * @return
++ */
++AVBuffer *av_buffer_create(char *va, unsigned int pa, unsigned int size);
++void av_buffer_del(AVBuffer *buf);
++
++AVBuffer *av_buffer_alloc(devmem_ctx_t *ctx, unsigned int size);
++
++
++void av_buffer_sync(devmem_ctx_t *ctx, AVBuffer *buf, int dir);
++
++
++void av_buffer_free(devmem_ctx_t *ctx, AVBuffer *buf);
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/bytestream.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/bytestream.h
+new file mode 100644
+index 000000000..b11e725fb
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/bytestream.h
+@@ -0,0 +1,358 @@
++#ifndef AVCODEC_BYTESTREAM_H
++#define AVCODEC_BYTESTREAM_H
++
++#ifdef __KERNEL__
++#include <linux/fs.h>
++#else
++#include <stdint.h>
++#include <string.h>
++#endif
++
++#include "avassert.h"
++#include "common.h"
++#include "intreadwrite.h"
++
++typedef struct GetByteContext {
++    const uint8_t *buffer, *buffer_end, *buffer_start;
++} GetByteContext;
++
++typedef struct PutByteContext {
++    uint8_t *buffer, *buffer_end, *buffer_start;
++    int eof;
++} PutByteContext;
++
++#define DEF(type, name, bytes, read, write)                                  \
++static inline type bytestream_get_ ## name(const uint8_t **b)        \
++{                                                                              \
++    (*b) += bytes;                                                             \
++    return read(*b - bytes);                                                   \
++}                                                                              \
++static inline void bytestream_put_ ## name(uint8_t **b,              \
++                                                     const type value)         \
++{                                                                              \
++    write(*b, value);                                                          \
++    (*b) += bytes;                                                             \
++}                                                                              \
++static inline void bytestream2_put_ ## name ## u(PutByteContext *p,  \
++                                                           const type value)   \
++{                                                                              \
++    bytestream_put_ ## name(&p->buffer, value);                                \
++}                                                                              \
++static inline void bytestream2_put_ ## name(PutByteContext *p,       \
++                                                      const type value)        \
++{                                                                              \
++    if (!p->eof && (p->buffer_end - p->buffer >= bytes)) {                     \
++        write(p->buffer, value);                                               \
++        p->buffer += bytes;                                                    \
++    } else                                                                     \
++        p->eof = 1;                                                            \
++}                                                                              \
++static inline type bytestream2_get_ ## name ## u(GetByteContext *g)  \
++{                                                                              \
++    return bytestream_get_ ## name(&g->buffer);                                \
++}                                                                              \
++static inline type bytestream2_get_ ## name(GetByteContext *g)       \
++{                                                                              \
++    if (g->buffer_end - g->buffer < bytes) {                                   \
++        g->buffer = g->buffer_end;                                             \
++        return 0;                                                              \
++    }                                                                          \
++    return bytestream2_get_ ## name ## u(g);                                   \
++}                                                                              \
++static inline type bytestream2_peek_ ## name(GetByteContext *g)      \
++{                                                                              \
++    if (g->buffer_end - g->buffer < bytes)                                     \
++        return 0;                                                              \
++    return read(g->buffer);                                                    \
++}
++
++DEF(uint64_t,     le64, 8, AV_RL64, AV_WL64)
++DEF(unsigned int, le32, 4, AV_RL32, AV_WL32)
++DEF(unsigned int, le24, 3, AV_RL24, AV_WL24)
++DEF(unsigned int, le16, 2, AV_RL16, AV_WL16)
++DEF(uint64_t,     be64, 8, AV_RB64, AV_WB64)
++DEF(unsigned int, be32, 4, AV_RB32, AV_WB32)
++DEF(unsigned int, be24, 3, AV_RB24, AV_WB24)
++DEF(unsigned int, be16, 2, AV_RB16, AV_WB16)
++DEF(unsigned int, byte, 1, AV_RB8 , AV_WB8)
++
++#if AV_HAVE_BIGENDIAN
++#   define bytestream2_get_ne16  bytestream2_get_be16
++#   define bytestream2_get_ne24  bytestream2_get_be24
++#   define bytestream2_get_ne32  bytestream2_get_be32
++#   define bytestream2_get_ne64  bytestream2_get_be64
++#   define bytestream2_get_ne16u bytestream2_get_be16u
++#   define bytestream2_get_ne24u bytestream2_get_be24u
++#   define bytestream2_get_ne32u bytestream2_get_be32u
++#   define bytestream2_get_ne64u bytestream2_get_be64u
++#   define bytestream2_put_ne16  bytestream2_put_be16
++#   define bytestream2_put_ne24  bytestream2_put_be24
++#   define bytestream2_put_ne32  bytestream2_put_be32
++#   define bytestream2_put_ne64  bytestream2_put_be64
++#   define bytestream2_peek_ne16 bytestream2_peek_be16
++#   define bytestream2_peek_ne24 bytestream2_peek_be24
++#   define bytestream2_peek_ne32 bytestream2_peek_be32
++#   define bytestream2_peek_ne64 bytestream2_peek_be64
++#else
++#   define bytestream2_get_ne16  bytestream2_get_le16
++#   define bytestream2_get_ne24  bytestream2_get_le24
++#   define bytestream2_get_ne32  bytestream2_get_le32
++#   define bytestream2_get_ne64  bytestream2_get_le64
++#   define bytestream2_get_ne16u bytestream2_get_le16u
++#   define bytestream2_get_ne24u bytestream2_get_le24u
++#   define bytestream2_get_ne32u bytestream2_get_le32u
++#   define bytestream2_get_ne64u bytestream2_get_le64u
++#   define bytestream2_put_ne16  bytestream2_put_le16
++#   define bytestream2_put_ne24  bytestream2_put_le24
++#   define bytestream2_put_ne32  bytestream2_put_le32
++#   define bytestream2_put_ne64  bytestream2_put_le64
++#   define bytestream2_peek_ne16 bytestream2_peek_le16
++#   define bytestream2_peek_ne24 bytestream2_peek_le24
++#   define bytestream2_peek_ne32 bytestream2_peek_le32
++#   define bytestream2_peek_ne64 bytestream2_peek_le64
++#endif
++
++static inline void bytestream2_init(GetByteContext *g,
++                                              const uint8_t *buf,
++                                              int buf_size)
++{
++    av_assert0(buf_size >= 0);
++    g->buffer       = buf;
++    g->buffer_start = buf;
++    g->buffer_end   = buf + buf_size;
++}
++
++static inline void bytestream2_init_writer(PutByteContext *p,
++                                                     uint8_t *buf,
++                                                     int buf_size)
++{
++    av_assert0(buf_size >= 0);
++    p->buffer       = buf;
++    p->buffer_start = buf;
++    p->buffer_end   = buf + buf_size;
++    p->eof          = 0;
++}
++
++static inline unsigned int bytestream2_get_bytes_left(GetByteContext *g)
++{
++    return g->buffer_end - g->buffer;
++}
++
++static inline unsigned int bytestream2_get_bytes_left_p(PutByteContext *p)
++{
++    return p->buffer_end - p->buffer;
++}
++
++static inline void bytestream2_skip(GetByteContext *g,
++                                              unsigned int size)
++{
++    g->buffer += FFMIN(g->buffer_end - g->buffer, size);
++}
++
++static inline void bytestream2_skipu(GetByteContext *g,
++                                               unsigned int size)
++{
++    g->buffer += size;
++}
++
++static inline void bytestream2_skip_p(PutByteContext *p,
++                                                unsigned int size)
++{
++    int size2;
++    if (p->eof)
++        return;
++    size2 = FFMIN(p->buffer_end - p->buffer, size);
++    if (size2 != size)
++        p->eof = 1;
++    p->buffer += size2;
++}
++
++static inline int bytestream2_tell(GetByteContext *g)
++{
++    return (int)(g->buffer - g->buffer_start);
++}
++
++static inline int bytestream2_tell_p(PutByteContext *p)
++{
++    return (int)(p->buffer - p->buffer_start);
++}
++
++static inline int bytestream2_size(GetByteContext *g)
++{
++    return (int)(g->buffer_end - g->buffer_start);
++}
++
++static inline int bytestream2_size_p(PutByteContext *p)
++{
++    return (int)(p->buffer_end - p->buffer_start);
++}
++
++static inline int bytestream2_seek(GetByteContext *g,
++                                             int offset,
++                                             int whence)
++{
++    switch (whence) {
++    case SEEK_CUR:
++        offset     = av_clip(offset, -(g->buffer - g->buffer_start),
++                             g->buffer_end - g->buffer);
++        g->buffer += offset;
++        break;
++    case SEEK_END:
++        offset    = av_clip(offset, -(g->buffer_end - g->buffer_start), 0);
++        g->buffer = g->buffer_end + offset;
++        break;
++    case SEEK_SET:
++        offset    = av_clip(offset, 0, g->buffer_end - g->buffer_start);
++        g->buffer = g->buffer_start + offset;
++        break;
++    default:
++        return AVERROR(EINVAL);
++    }
++    return bytestream2_tell(g);
++}
++
++static inline int bytestream2_seek_p(PutByteContext *p,
++                                               int offset,
++                                               int whence)
++{
++    p->eof = 0;
++    switch (whence) {
++    case SEEK_CUR:
++        if (p->buffer_end - p->buffer < offset)
++            p->eof = 1;
++        offset     = av_clip(offset, -(p->buffer - p->buffer_start),
++                             p->buffer_end - p->buffer);
++        p->buffer += offset;
++        break;
++    case SEEK_END:
++        if (offset > 0)
++            p->eof = 1;
++        offset    = av_clip(offset, -(p->buffer_end - p->buffer_start), 0);
++        p->buffer = p->buffer_end + offset;
++        break;
++    case SEEK_SET:
++        if (p->buffer_end - p->buffer_start < offset)
++            p->eof = 1;
++        offset    = av_clip(offset, 0, p->buffer_end - p->buffer_start);
++        p->buffer = p->buffer_start + offset;
++        break;
++    default:
++        return AVERROR(EINVAL);
++    }
++    return bytestream2_tell_p(p);
++}
++
++static inline unsigned int bytestream2_get_buffer(GetByteContext *g,
++                                                            uint8_t *dst,
++                                                            unsigned int size)
++{
++    int size2 = FFMIN(g->buffer_end - g->buffer, size);
++    memcpy(dst, g->buffer, size2);
++    g->buffer += size2;
++    return size2;
++}
++
++static inline unsigned int bytestream2_get_bufferu(GetByteContext *g,
++                                                             uint8_t *dst,
++                                                             unsigned int size)
++{
++    memcpy(dst, g->buffer, size);
++    g->buffer += size;
++    return size;
++}
++
++static inline unsigned int bytestream2_put_buffer(PutByteContext *p,
++                                                            const uint8_t *src,
++                                                            unsigned int size)
++{
++    int size2;
++    if (p->eof)
++        return 0;
++    size2 = FFMIN(p->buffer_end - p->buffer, size);
++    if (size2 != size)
++        p->eof = 1;
++    memcpy(p->buffer, src, size2);
++    p->buffer += size2;
++    return size2;
++}
++
++static inline unsigned int bytestream2_put_bufferu(PutByteContext *p,
++                                                             const uint8_t *src,
++                                                             unsigned int size)
++{
++    memcpy(p->buffer, src, size);
++    p->buffer += size;
++    return size;
++}
++
++static inline void bytestream2_set_buffer(PutByteContext *p,
++                                                    const uint8_t c,
++                                                    unsigned int size)
++{
++    int size2;
++    if (p->eof)
++        return;
++    size2 = FFMIN(p->buffer_end - p->buffer, size);
++    if (size2 != size)
++        p->eof = 1;
++    memset(p->buffer, c, size2);
++    p->buffer += size2;
++}
++
++static inline void bytestream2_set_bufferu(PutByteContext *p,
++                                                     const uint8_t c,
++                                                     unsigned int size)
++{
++    memset(p->buffer, c, size);
++    p->buffer += size;
++}
++
++static inline unsigned int bytestream2_get_eof(PutByteContext *p)
++{
++    return p->eof;
++}
++
++static inline unsigned int bytestream2_copy_bufferu(PutByteContext *p,
++                                                              GetByteContext *g,
++                                                              unsigned int size)
++{
++    memcpy(p->buffer, g->buffer, size);
++    p->buffer += size;
++    g->buffer += size;
++    return size;
++}
++
++static inline unsigned int bytestream2_copy_buffer(PutByteContext *p,
++                                                             GetByteContext *g,
++                                                             unsigned int size)
++{
++    int size2;
++
++    if (p->eof)
++        return 0;
++    size  = FFMIN(g->buffer_end - g->buffer, size);
++    size2 = FFMIN(p->buffer_end - p->buffer, size);
++    if (size2 != size)
++        p->eof = 1;
++
++    return bytestream2_copy_bufferu(p, g, size2);
++}
++
++static inline unsigned int bytestream_get_buffer(const uint8_t **b,
++                                                           uint8_t *dst,
++                                                           unsigned int size)
++{
++    memcpy(dst, *b, size);
++    (*b) += size;
++    return size;
++}
++
++static inline void bytestream_put_buffer(uint8_t **b,
++                                                   const uint8_t *src,
++                                                   unsigned int size)
++{
++    memcpy(*b, src, size);
++    (*b) += size;
++}
++
++#endif /* AVCODEC_BYTESTREAM_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/common.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/common.h
+new file mode 100644
+index 000000000..11dad8f04
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/common.h
+@@ -0,0 +1,476 @@
++#ifndef AVUTIL_COMMON_H
++#define AVUTIL_COMMON_H
++
++#ifdef __KERNEL__
++#include <linux/errno.h>
++//#include <linux/types.h>
++#include <linux/limits.h>
++#include <linux/string.h>
++#include <linux/kernel.h>
++//#include "pstdint.h"
++
++typedef long intptr_t;
++#define printf printk
++
++# define INT16_MAX (32767)
++
++#else
++
++#include <errno.h>
++#include <inttypes.h>
++#include <limits.h>
++#include <math.h>
++#include <stdint.h>
++#include <stdio.h>
++#include <stdlib.h>
++#endif
++
++//#include "attributes.h"
++//#include "macros.h"
++//#include "version.h"
++//#include "libavutil/avconfig.h"
++
++#   define AV_NE(be, le) (le)
++
++//rounded division & shift
++#define RSHIFT(a,b) ((a) > 0 ? ((a) + ((1<<(b))>>1))>>(b) : ((a) + ((1<<(b))>>1)-1)>>(b))
++/* assume b>0 */
++#define ROUNDED_DIV(a,b) (((a)>0 ? (a) + ((b)>>1) : (a) - ((b)>>1))/(b))
++/* Fast a/(1<<b) rounded toward +inf. Assume a>=0 and b>=0 */
++#define AV_CEIL_RSHIFT(a,b) (!av_builtin_constant_p(b) ? -((-(a)) >> (b)) \
++                                                       : ((a) + (1<<(b)) - 1) >> (b))
++/* Backwards compat. */
++#define FF_CEIL_RSHIFT AV_CEIL_RSHIFT
++
++#define FFUDIV(a,b) (((a)>0 ?(a):(a)-(b)+1) / (b))
++#define FFUMOD(a,b) ((a)-(b)*FFUDIV(a,b))
++
++/**
++ * Absolute value, Note, INT_MIN / INT64_MIN result in undefined behavior as they
++ * are not representable as absolute values of their type. This is the same
++ * as with *abs()
++ * @see FFNABS()
++ */
++#define FFABS(a) ((a) >= 0 ? (a) : (-(a)))
++#define FFSIGN(a) ((a) > 0 ? 1 : -1)
++
++/**
++ * Negative Absolute value.
++ * this works for all integers of all types.
++ * As with many macros, this evaluates its argument twice, it thus must not have
++ * a sideeffect, that is FFNABS(x++) has undefined behavior.
++ */
++#define FFNABS(a) ((a) <= 0 ? (a) : (-(a)))
++
++/**
++ * Comparator.
++ * For two numerical expressions x and y, gives 1 if x > y, -1 if x < y, and 0
++ * if x == y. This is useful for instance in a qsort comparator callback.
++ * Furthermore, compilers are able to optimize this to branchless code, and
++ * there is no risk of overflow with signed types.
++ * As with many macros, this evaluates its argument multiple times, it thus
++ * must not have a side-effect.
++ */
++#define FFDIFFSIGN(x,y) (((x)>(y)) - ((x)<(y)))
++
++#define FFMAX(a,b) ((a) > (b) ? (a) : (b))
++#define FFMAX3(a,b,c) FFMAX(FFMAX(a,b),c)
++#define FFMIN(a,b) ((a) > (b) ? (b) : (a))
++#define FFMIN3(a,b,c) FFMIN(FFMIN(a,b),c)
++
++#define FFSWAP(type,a,b) do{type SWAP_tmp= b; b= a; a= SWAP_tmp;}while(0)
++#define FF_ARRAY_ELEMS(a) (sizeof(a) / sizeof((a)[0]))
++
++/* misc math functions */
++
++#ifdef HAVE_AV_CONFIG_H
++#   include "config.h"
++#   include "intmath.h"
++#endif
++
++/* Pull in unguarded fallback defines at the end of this file. */
++#include "common.h"
++
++#ifndef av_log2
++const int av_log2(unsigned v);
++#endif
++
++#ifndef av_log2_16bit
++const int av_log2_16bit(unsigned v);
++#endif
++
++/**
++ * Clip a signed integer value into the amin-amax range.
++ * @param a value to clip
++ * @param amin minimum value of the clip range
++ * @param amax maximum value of the clip range
++ * @return clipped value
++ */
++static inline const int av_clip_c(int a, int amin, int amax)
++{
++#if defined(HAVE_AV_CONFIG_H) && defined(ASSERT_LEVEL) && ASSERT_LEVEL >= 2
++    if (amin > amax) abort();
++#endif
++    if      (a < amin) return amin;
++    else if (a > amax) return amax;
++    else               return a;
++}
++
++/**
++ * Clip a signed 64bit integer value into the amin-amax range.
++ * @param a value to clip
++ * @param amin minimum value of the clip range
++ * @param amax maximum value of the clip range
++ * @return clipped value
++ */
++static inline const int64_t av_clip64_c(int64_t a, int64_t amin, int64_t amax)
++{
++#if defined(HAVE_AV_CONFIG_H) && defined(ASSERT_LEVEL) && ASSERT_LEVEL >= 2
++    if (amin > amax) abort();
++#endif
++    if      (a < amin) return amin;
++    else if (a > amax) return amax;
++    else               return a;
++}
++
++/**
++ * Clip a signed integer value into the 0-255 range.
++ * @param a value to clip
++ * @return clipped value
++ */
++static inline const uint8_t av_clip_uint8_c(int a)
++{
++    if (a&(~0xFF)) return (~a)>>31;
++    else           return a;
++}
++
++/**
++ * Clip a signed integer value into the -128,127 range.
++ * @param a value to clip
++ * @return clipped value
++ */
++static inline const int8_t av_clip_int8_c(int a)
++{
++    if ((a+0x80U) & ~0xFF) return (a>>31) ^ 0x7F;
++    else                  return a;
++}
++
++/**
++ * Clip a signed integer value into the 0-65535 range.
++ * @param a value to clip
++ * @return clipped value
++ */
++static inline const uint16_t av_clip_uint16_c(int a)
++{
++    if (a&(~0xFFFF)) return (~a)>>31;
++    else             return a;
++}
++
++/**
++ * Clip a signed integer value into the -32768,32767 range.
++ * @param a value to clip
++ * @return clipped value
++ */
++static inline const int16_t av_clip_int16_c(int a)
++{
++    if ((a+0x8000U) & ~0xFFFF) return (a>>31) ^ 0x7FFF;
++    else                      return a;
++}
++
++/**
++ * Clip a signed integer into the -(2^p),(2^p-1) range.
++ * @param  a value to clip
++ * @param  p bit position to clip at
++ * @return clipped value
++ */
++static inline const int av_clip_intp2_c(int a, int p)
++{
++    if (((unsigned)a + (1 << p)) & ~((2 << p) - 1))
++        return (a >> 31) ^ ((1 << p) - 1);
++    else
++        return a;
++}
++
++/**
++ * Clip a signed integer to an unsigned power of two range.
++ * @param  a value to clip
++ * @param  p bit position to clip at
++ * @return clipped value
++ */
++static inline const unsigned av_clip_uintp2_c(int a, int p)
++{
++    if (a & ~((1<<p) - 1)) return (~a) >> 31 & ((1<<p) - 1);
++    else                   return  a;
++}
++
++/**
++ * Clear high bits from an unsigned integer starting with specific bit position
++ * @param  a value to clip
++ * @param  p bit position to clip at
++ * @return clipped value
++ */
++static inline const unsigned av_mod_uintp2_c(unsigned a, unsigned p)
++{
++    return a & ((1 << p) - 1);
++}
++
++/**
++ * Clip a float value into the amin-amax range.
++ * @param a value to clip
++ * @param amin minimum value of the clip range
++ * @param amax maximum value of the clip range
++ * @return clipped value
++ */
++static inline const float av_clipf_c(float a, float amin, float amax)
++{
++#if defined(HAVE_AV_CONFIG_H) && defined(ASSERT_LEVEL) && ASSERT_LEVEL >= 2
++    if (amin > amax) abort();
++#endif
++    if      (a < amin) return amin;
++    else if (a > amax) return amax;
++    else               return a;
++}
++
++/**
++ * Clip a double value into the amin-amax range.
++ * @param a value to clip
++ * @param amin minimum value of the clip range
++ * @param amax maximum value of the clip range
++ * @return clipped value
++ */
++static inline const double av_clipd_c(double a, double amin, double amax)
++{
++#if defined(HAVE_AV_CONFIG_H) && defined(ASSERT_LEVEL) && ASSERT_LEVEL >= 2
++    if (amin > amax) abort();
++#endif
++    if      (a < amin) return amin;
++    else if (a > amax) return amax;
++    else               return a;
++}
++
++/** Compute ceil(log2(x)).
++ * @param x value used to compute ceil(log2(x))
++ * @return computed ceiling of log2(x)
++ */
++static inline const int av_ceil_log2_c(int x)
++{
++    return av_log2((x - 1) << 1);
++}
++
++/**
++ * Count number of bits set to one in x
++ * @param x value to count bits of
++ * @return the number of bits set to one in x
++ */
++static inline const int av_popcount_c(uint32_t x)
++{
++    x -= (x >> 1) & 0x55555555;
++    x = (x & 0x33333333) + ((x >> 2) & 0x33333333);
++    x = (x + (x >> 4)) & 0x0F0F0F0F;
++    x += x >> 8;
++    return (x + (x >> 16)) & 0x3F;
++}
++
++/**
++ * Count number of bits set to one in x
++ * @param x value to count bits of
++ * @return the number of bits set to one in x
++ */
++static inline const int av_popcount64_c(uint64_t x)
++{
++    return av_popcount((uint32_t)x) + av_popcount((uint32_t)(x >> 32));
++}
++
++static inline const int av_parity_c(uint32_t v)
++{
++    return av_popcount(v) & 1;
++}
++
++#define MKTAG(a,b,c,d) ((a) | ((b) << 8) | ((c) << 16) | ((unsigned)(d) << 24))
++#define MKBETAG(a,b,c,d) ((d) | ((c) << 8) | ((b) << 16) | ((unsigned)(a) << 24))
++
++/**
++ * Convert a UTF-8 character (up to 4 bytes) to its 32-bit UCS-4 encoded form.
++ *
++ * @param val      Output value, must be an lvalue of type uint32_t.
++ * @param GET_BYTE Expression reading one byte from the input.
++ *                 Evaluated up to 7 times (4 for the currently
++ *                 assigned Unicode range).  With a memory buffer
++ *                 input, this could be *ptr++.
++ * @param ERROR    Expression to be evaluated on invalid input,
++ *                 typically a goto statement.
++ *
++ * @warning ERROR should not contain a loop control statement which
++ * could interact with the internal while loop, and should force an
++ * exit from the macro code (e.g. through a goto or a return) in order
++ * to prevent undefined results.
++ */
++#define GET_UTF8(val, GET_BYTE, ERROR)\
++    val= (GET_BYTE);\
++    {\
++        uint32_t top = (val & 128) >> 1;\
++        if ((val & 0xc0) == 0x80 || val >= 0xFE)\
++            ERROR\
++        while (val & top) {\
++            int tmp= (GET_BYTE) - 128;\
++            if(tmp>>6)\
++                ERROR\
++            val= (val<<6) + tmp;\
++            top <<= 5;\
++        }\
++        val &= (top << 1) - 1;\
++    }
++
++/**
++ * Convert a UTF-16 character (2 or 4 bytes) to its 32-bit UCS-4 encoded form.
++ *
++ * @param val       Output value, must be an lvalue of type uint32_t.
++ * @param GET_16BIT Expression returning two bytes of UTF-16 data converted
++ *                  to native byte order.  Evaluated one or two times.
++ * @param ERROR     Expression to be evaluated on invalid input,
++ *                  typically a goto statement.
++ */
++#define GET_UTF16(val, GET_16BIT, ERROR)\
++    val = GET_16BIT;\
++    {\
++        unsigned int hi = val - 0xD800;\
++        if (hi < 0x800) {\
++            val = GET_16BIT - 0xDC00;\
++            if (val > 0x3FFU || hi > 0x3FFU)\
++                ERROR\
++            val += (hi<<10) + 0x10000;\
++        }\
++    }\
++
++/**
++ * @def PUT_UTF8(val, tmp, PUT_BYTE)
++ * Convert a 32-bit Unicode character to its UTF-8 encoded form (up to 4 bytes long).
++ * @param val is an input-only argument and should be of type uint32_t. It holds
++ * a UCS-4 encoded Unicode character that is to be converted to UTF-8. If
++ * val is given as a function it is executed only once.
++ * @param tmp is a temporary variable and should be of type uint8_t. It
++ * represents an intermediate value during conversion that is to be
++ * output by PUT_BYTE.
++ * @param PUT_BYTE writes the converted UTF-8 bytes to any proper destination.
++ * It could be a function or a statement, and uses tmp as the input byte.
++ * For example, PUT_BYTE could be "*output++ = tmp;" PUT_BYTE will be
++ * executed up to 4 times for values in the valid UTF-8 range and up to
++ * 7 times in the general case, depending on the length of the converted
++ * Unicode character.
++ */
++#define PUT_UTF8(val, tmp, PUT_BYTE)\
++    {\
++        int bytes, shift;\
++        uint32_t in = val;\
++        if (in < 0x80) {\
++            tmp = in;\
++            PUT_BYTE\
++        } else {\
++            bytes = (av_log2(in) + 4) / 5;\
++            shift = (bytes - 1) * 6;\
++            tmp = (256 - (256 >> bytes)) | (in >> shift);\
++            PUT_BYTE\
++            while (shift >= 6) {\
++                shift -= 6;\
++                tmp = 0x80 | ((in >> shift) & 0x3f);\
++                PUT_BYTE\
++            }\
++        }\
++    }
++
++/**
++ * @def PUT_UTF16(val, tmp, PUT_16BIT)
++ * Convert a 32-bit Unicode character to its UTF-16 encoded form (2 or 4 bytes).
++ * @param val is an input-only argument and should be of type uint32_t. It holds
++ * a UCS-4 encoded Unicode character that is to be converted to UTF-16. If
++ * val is given as a function it is executed only once.
++ * @param tmp is a temporary variable and should be of type uint16_t. It
++ * represents an intermediate value during conversion that is to be
++ * output by PUT_16BIT.
++ * @param PUT_16BIT writes the converted UTF-16 data to any proper destination
++ * in desired endianness. It could be a function or a statement, and uses tmp
++ * as the input byte.  For example, PUT_BYTE could be "*output++ = tmp;"
++ * PUT_BYTE will be executed 1 or 2 times depending on input character.
++ */
++#define PUT_UTF16(val, tmp, PUT_16BIT)\
++    {\
++        uint32_t in = val;\
++        if (in < 0x10000) {\
++            tmp = in;\
++            PUT_16BIT\
++        } else {\
++            tmp = 0xD800 | ((in - 0x10000) >> 10);\
++            PUT_16BIT\
++            tmp = 0xDC00 | ((in - 0x10000) & 0x3FF);\
++            PUT_16BIT\
++        }\
++    }\
++
++
++
++#include "mem.h"
++
++#ifdef HAVE_AV_CONFIG_H
++#    include "internal.h"
++#endif /* HAVE_AV_CONFIG_H */
++
++#endif /* AVUTIL_COMMON_H */
++
++/*
++ * The following definitions are outside the multiple inclusion guard
++ * to ensure they are immediately available in intmath.h.
++ */
++#ifndef av_ceil_log2
++#   define av_ceil_log2     av_ceil_log2_c
++#endif
++#ifndef av_clip
++#   define av_clip          av_clip_c
++#endif
++#ifndef av_clip64
++#   define av_clip64        av_clip64_c
++#endif
++#ifndef av_clip_uint8
++#   define av_clip_uint8    av_clip_uint8_c
++#endif
++#ifndef av_clip_int8
++#   define av_clip_int8     av_clip_int8_c
++#endif
++#ifndef av_clip_uint16
++#   define av_clip_uint16   av_clip_uint16_c
++#endif
++#ifndef av_clip_int16
++#   define av_clip_int16    av_clip_int16_c
++#endif
++#ifndef av_clip_intp2
++#   define av_clip_intp2    av_clip_intp2_c
++#endif
++#ifndef av_clip_uintp2
++#   define av_clip_uintp2   av_clip_uintp2_c
++#endif
++#ifndef av_mod_uintp2
++#   define av_mod_uintp2    av_mod_uintp2_c
++#endif
++#ifndef av_sat_dadd32
++#   define av_sat_dadd32    av_sat_dadd32_c
++#endif
++#ifndef av_sat_sub32
++#   define av_sat_sub32     av_sat_sub32_c
++#endif
++#ifndef av_sat_dsub32
++#   define av_sat_dsub32    av_sat_dsub32_c
++#endif
++#ifndef av_clipf
++#   define av_clipf         av_clipf_c
++#endif
++#ifndef av_clipd
++#   define av_clipd         av_clipd_c
++#endif
++#ifndef av_popcount
++#   define av_popcount      av_popcount_c
++#endif
++#ifndef av_popcount64
++#   define av_popcount64    av_popcount64_c
++#endif
++#ifndef av_parity
++#   define av_parity        av_parity_c
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/devmem.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/devmem.h
+new file mode 100644
+index 000000000..2277659b0
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/devmem.h
+@@ -0,0 +1,26 @@
++#ifndef __DEVMEM_H__
++#define __DEVMEM_H__
++
++typedef struct devmem_info {
++	unsigned long userptr;
++	unsigned long paddr;
++	unsigned long length;
++	unsigned long kva;
++	int coherent;
++	int sync_dir;
++} devmem_info_t;
++
++#define DEVMEM_MAGIC	'D'
++
++#define DEVMEM_SYNC_NONE	0
++#define DEVMEM_SYNC_TO_DEVICE	1
++#define DEVMEM_SYNC_FROM_DEVICE	2
++
++#define DEVMEM_ALLOC	_IOWR(DEVMEM_MAGIC, 10, devmem_info_t)
++#define DEVMEM_FREE	_IOW(DEVMEM_MAGIC, 11, devmem_info_t)
++#define DEVMEM_SYNC	_IOW(DEVMEM_MAGIC, 12, devmem_info_t)
++
++
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/error.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/error.h
+new file mode 100644
+index 000000000..fb538d122
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/error.h
+@@ -0,0 +1,108 @@
++#ifndef AVUTIL_ERROR_H
++#define AVUTIL_ERROR_H
++
++#ifdef __KERNEL__
++#include <linux/errno.h>
++#include <linux/types.h>
++#else
++#include <errno.h>
++#include <stddef.h>
++#endif
++
++/**
++ * @addtogroup lavu_error
++ *
++ * @{
++ */
++
++
++/* error handling */
++#if EDOM > 0
++#define AVERROR(e) (-(e))   ///< Returns a negative error code from a POSIX error code, to return from library functions.
++#define AVUNERROR(e) (-(e)) ///< Returns a POSIX error code from a library function error return value.
++#else
++/* Some platforms have E* and errno already negated. */
++#define AVERROR(e) (e)
++#define AVUNERROR(e) (e)
++#endif
++
++#define FFERRTAG(a, b, c, d) (-(int)MKTAG(a, b, c, d))
++
++#define AVERROR_BSF_NOT_FOUND      FFERRTAG(0xF8,'B','S','F') ///< Bitstream filter not found
++#define AVERROR_BUG                FFERRTAG( 'B','U','G','!') ///< Internal bug, also see AVERROR_BUG2
++#define AVERROR_BUFFER_TOO_SMALL   FFERRTAG( 'B','U','F','S') ///< Buffer too small
++#define AVERROR_DECODER_NOT_FOUND  FFERRTAG(0xF8,'D','E','C') ///< Decoder not found
++#define AVERROR_DEMUXER_NOT_FOUND  FFERRTAG(0xF8,'D','E','M') ///< Demuxer not found
++#define AVERROR_ENCODER_NOT_FOUND  FFERRTAG(0xF8,'E','N','C') ///< Encoder not found
++#define AVERROR_EOF                FFERRTAG( 'E','O','F',' ') ///< End of file
++#define AVERROR_EXIT               FFERRTAG( 'E','X','I','T') ///< Immediate exit was requested; the called function should not be restarted
++#define AVERROR_EXTERNAL           FFERRTAG( 'E','X','T',' ') ///< Generic error in an external library
++#define AVERROR_FILTER_NOT_FOUND   FFERRTAG(0xF8,'F','I','L') ///< Filter not found
++#define AVERROR_INVALIDDATA        FFERRTAG( 'I','N','D','A') ///< Invalid data found when processing input
++#define AVERROR_MUXER_NOT_FOUND    FFERRTAG(0xF8,'M','U','X') ///< Muxer not found
++#define AVERROR_OPTION_NOT_FOUND   FFERRTAG(0xF8,'O','P','T') ///< Option not found
++#define AVERROR_PATCHWELCOME       FFERRTAG( 'P','A','W','E') ///< Not yet implemented in FFmpeg, patches welcome
++#define AVERROR_PROTOCOL_NOT_FOUND FFERRTAG(0xF8,'P','R','O') ///< Protocol not found
++
++#define AVERROR_STREAM_NOT_FOUND   FFERRTAG(0xF8,'S','T','R') ///< Stream not found
++/**
++ * This is semantically identical to AVERROR_BUG
++ * it has been introduced in Libav after our AVERROR_BUG and with a modified value.
++ */
++#define AVERROR_BUG2               FFERRTAG( 'B','U','G',' ')
++#define AVERROR_UNKNOWN            FFERRTAG( 'U','N','K','N') ///< Unknown error, typically from an external library
++#define AVERROR_EXPERIMENTAL       (-0x2bb2afa8) ///< Requested feature is flagged experimental. Set strict_std_compliance if you really want to use it.
++#define AVERROR_INPUT_CHANGED      (-0x636e6701) ///< Input changed between calls. Reconfiguration is required. (can be OR-ed with AVERROR_OUTPUT_CHANGED)
++#define AVERROR_OUTPUT_CHANGED     (-0x636e6702) ///< Output changed between calls. Reconfiguration is required. (can be OR-ed with AVERROR_INPUT_CHANGED)
++/* HTTP & RTSP errors */
++#define AVERROR_HTTP_BAD_REQUEST   FFERRTAG(0xF8,'4','0','0')
++#define AVERROR_HTTP_UNAUTHORIZED  FFERRTAG(0xF8,'4','0','1')
++#define AVERROR_HTTP_FORBIDDEN     FFERRTAG(0xF8,'4','0','3')
++#define AVERROR_HTTP_NOT_FOUND     FFERRTAG(0xF8,'4','0','4')
++#define AVERROR_HTTP_OTHER_4XX     FFERRTAG(0xF8,'4','X','X')
++#define AVERROR_HTTP_SERVER_ERROR  FFERRTAG(0xF8,'5','X','X')
++
++#define AV_ERROR_MAX_STRING_SIZE 64
++
++/**
++ * Put a description of the AVERROR code errnum in errbuf.
++ * In case of failure the global variable errno is set to indicate the
++ * error. Even in case of failure av_strerror() will print a generic
++ * error message indicating the errnum provided to errbuf.
++ *
++ * @param errnum      error code to describe
++ * @param errbuf      buffer to which description is written
++ * @param errbuf_size the size in bytes of errbuf
++ * @return 0 on success, a negative value if a description for errnum
++ * cannot be found
++ */
++int av_strerror(int errnum, char *errbuf, size_t errbuf_size);
++
++/**
++ * Fill the provided buffer with a string containing an error string
++ * corresponding to the AVERROR code errnum.
++ *
++ * @param errbuf         a buffer
++ * @param errbuf_size    size in bytes of errbuf
++ * @param errnum         error code to describe
++ * @return the buffer in input, filled with the error description
++ * @see av_strerror()
++ */
++static inline char *av_make_error_string(char *errbuf, size_t errbuf_size, int errnum)
++{
++    av_strerror(errnum, errbuf, errbuf_size);
++    return errbuf;
++}
++
++/**
++ * Convenience macro, the return value should be used only directly in
++ * function arguments but never stand-alone.
++ */
++#define av_err2str(errnum) \
++    av_make_error_string((char[AV_ERROR_MAX_STRING_SIZE]){0}, AV_ERROR_MAX_STRING_SIZE, errnum)
++
++/**
++ * @}
++ */
++
++#endif /* AVUTIL_ERROR_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/frame.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/frame.h
+new file mode 100644
+index 000000000..0e5b0b0fb
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/frame.h
+@@ -0,0 +1,308 @@
++#ifndef AVUTIL_FRAME_H
++#define AVUTIL_FRAME_H
++
++
++#include "list.h"
++#include "buffer.h"
++
++#define AVBufferRef AVBuffer
++
++enum AVPictureType {
++    AV_PICTURE_TYPE_NONE = 0, ///< Undefined
++    AV_PICTURE_TYPE_I,     ///< Intra
++    AV_PICTURE_TYPE_P,     ///< Predicted
++    AV_PICTURE_TYPE_B,     ///< Bi-dir predicted
++    AV_PICTURE_TYPE_S,     ///< S(GMC)-VOP MPEG-4
++    AV_PICTURE_TYPE_SI,    ///< Switching Intra
++    AV_PICTURE_TYPE_SP,    ///< Switching Predicted
++    AV_PICTURE_TYPE_BI,    ///< BI type
++};
++
++typedef struct AVFrame {
++#define AV_NUM_DATA_POINTERS 4
++    /**
++     * pointer to the picture/channel planes.
++     * This might be different from the first allocated byte
++     *
++     * Some decoders access areas outside 0,0 - width,height, please
++     * see avcodec_align_dimensions2(). Some filters and swscale can read
++     * up to 16 bytes beyond the planes, if these filters are to be used,
++     * then 16 extra bytes must be allocated.
++     *
++     * NOTE: Except for hwaccel formats, pointers not needed by the format
++     * MUST be set to NULL.
++     */
++    uint8_t *data[AV_NUM_DATA_POINTERS];
++
++    /**
++     * For video, size in bytes of each picture line.
++     * For audio, size in bytes of each plane.
++     *
++     * For audio, only linesize[0] may be set. For planar audio, each channel
++     * plane must be the same size.
++     *
++     * For video the linesizes should be multiples of the CPUs alignment
++     * preference, this is 16 or 32 for modern desktop CPUs.
++     * Some code requires such alignment other code can be slower without
++     * correct alignment, for yet other it makes no difference.
++     *
++     * @note The linesize may be larger than the size of usable data -- there
++     * may be extra padding present for performance reasons.
++     */
++    int linesize[AV_NUM_DATA_POINTERS];
++
++    /*当�Frame是�完�.是��被使用.*/
++    struct list_head queued_entry;
++    int queued;        /*表示当�Frame已�在队列当中.*/
++    struct list_head done_entry;
++    int index;
++
++
++    /**
++     * pointers to the data planes/channels.
++     *
++     * For video, this should simply point to data[].
++     *
++     * For planar audio, each channel has a separate data pointer, and
++     * linesize[0] contains the size of each channel buffer.
++     * For packed audio, there is just one data pointer, and linesize[0]
++     * contains the total size of the buffer for all channels.
++     *
++     * Note: Both data and extended_data should always be set in a valid frame,
++     * but for planar audio with more channels that can fit in data,
++     * extended_data must be used in order to access all channels.
++     */
++    uint8_t **extended_data;
++
++    /**
++     * @name Video dimensions
++     * Video frames only. The coded dimensions (in pixels) of the video frame,
++     * i.e. the size of the rectangle that contains some well-defined values.
++     *
++     * @note The part of the frame intended for display/presentation is further
++     * restricted by the @ref cropping "Cropping rectangle".
++     * @{
++     */
++    int width, height;
++    /**
++     * @}
++     */
++
++    /**
++     * number of audio samples (per channel) described by this frame
++     */
++    int nb_samples;
++
++    /**
++     * format of the frame, -1 if unknown or unset
++     * Values correspond to enum AVPixelFormat for video frames,
++     * enum AVSampleFormat for audio)
++     */
++    int format;
++
++    /**
++     * 1 -> keyframe, 0-> not
++     */
++    int key_frame;
++
++    /**
++     * Picture type of the frame.
++     */
++    enum AVPictureType pict_type;
++
++    /**
++     * Sample aspect ratio for the video frame, 0/1 if unknown/unspecified.
++     */
++    //AVRational sample_aspect_ratio;
++
++    /**
++     * Presentation timestamp in time_base units (time when frame should be shown to user).
++     */
++    int64_t pts;
++
++    /**
++     * DTS copied from the AVPacket that triggered returning this frame. (if frame threading isn't used)
++     * This is also the Presentation time of this AVFrame calculated from
++     * only AVPacket.dts values without pts values.
++     */
++    int64_t pkt_dts;
++
++    /**
++     * picture number in bitstream order
++     */
++    int coded_picture_number;
++    /**
++     * picture number in display order
++     */
++    int display_picture_number;
++
++    /**
++     * quality (between 1 (good) and FF_LAMBDA_MAX (bad))
++     */
++    int quality;
++
++    /**
++     * for some private data of the user
++     */
++    void *opaque;
++
++    /**
++     * When decoding, this signals how much the picture must be delayed.
++     * extra_delay = repeat_pict / (2*fps)
++     */
++    int repeat_pict;
++
++    /**
++     * The content of the picture is interlaced.
++     */
++    int interlaced_frame;
++
++    /**
++     * If the content is interlaced, is top field displayed first.
++     */
++    int top_field_first;
++
++    /**
++     * Tell user application that palette has changed from previous frame.
++     */
++    int palette_has_changed;
++
++    /**
++     * reordered opaque 64 bits (generally an integer or a double precision float
++     * PTS but can be anything).
++     * The user sets AVCodecContext.reordered_opaque to represent the input at
++     * that time,
++     * the decoder reorders values as needed and sets AVFrame.reordered_opaque
++     * to exactly one of the values provided by the user through AVCodecContext.reordered_opaque
++     * @deprecated in favor of pkt_pts
++     */
++    int64_t reordered_opaque;
++
++    /**
++     * Sample rate of the audio data.
++     */
++    int sample_rate;
++
++    /**
++     * Channel layout of the audio data.
++     */
++    uint64_t channel_layout;
++
++    /**
++     * AVBuffer references backing the data for this frame. If all elements of
++     * this array are NULL, then this frame is not reference counted. This array
++     * must be filled contiguously -- if buf[i] is non-NULL then buf[j] must
++     * also be non-NULL for all j < i.
++     *
++     * There may be at most one AVBuffer per data plane, so for video this array
++     * always contains all the references. For planar audio with more than
++     * AV_NUM_DATA_POINTERS channels, there may be more buffers than can fit in
++     * this array. Then the extra AVBufferRef pointers are stored in the
++     * extended_buf array.
++     */
++    AVBufferRef *buf[AV_NUM_DATA_POINTERS];
++
++/**
++ * @defgroup lavu_frame_flags AV_FRAME_FLAGS
++ * @ingroup lavu_frame
++ * Flags describing additional frame properties.
++ *
++ * @{
++ */
++
++/**
++ * The frame data may be corrupted, e.g. due to decoding errors.
++ */
++#define AV_FRAME_FLAG_CORRUPT       (1 << 0)
++/**
++ * A flag to mark the frames which need to be decoded, but shouldn't be output.
++ */
++#define AV_FRAME_FLAG_DISCARD   (1 << 2)
++/**
++ * @}
++ */
++
++    /**
++     * Frame flags, a combination of @ref lavu_frame_flags
++     */
++    int flags;
++
++    /**
++     * frame timestamp estimated using various heuristics, in stream time base
++     * - encoding: unused
++     * - decoding: set by libavcodec, read by user.
++     */
++    int64_t best_effort_timestamp;
++
++    /**
++     * reordered pos from the last AVPacket that has been input into the decoder
++     * - encoding: unused
++     * - decoding: Read by user.
++     */
++    int64_t pkt_pos;
++
++    /**
++     * duration of the corresponding packet, expressed in
++     * AVStream->time_base units, 0 if unknown.
++     * - encoding: unused
++     * - decoding: Read by user.
++     */
++    int64_t pkt_duration;
++
++    /**
++     * decode error flags of the frame, set to a combination of
++     * FF_DECODE_ERROR_xxx flags if the decoder produced a frame, but there
++     * were errors during the decoding.
++     * - encoding: unused
++     * - decoding: set by libavcodec, read by user.
++     */
++    int decode_error_flags;
++#define FF_DECODE_ERROR_INVALID_BITSTREAM   1
++#define FF_DECODE_ERROR_MISSING_REFERENCE   2
++
++    /**
++     * number of audio channels, only used for audio.
++     * - encoding: unused
++     * - decoding: Read by user.
++     */
++    int channels;
++
++    /**
++     * size of the corresponding packet containing the compressed
++     * frame.
++     * It is set to a negative value if unknown.
++     * - encoding: unused
++     * - decoding: set by libavcodec, read by user.
++     */
++    int pkt_size;
++
++    /**
++     * @anchor cropping
++     * @name Cropping
++     * Video frames only. The number of pixels to discard from the the
++     * top/bottom/left/right border of the frame to obtain the sub-rectangle of
++     * the frame intended for presentation.
++     * @{
++     */
++    size_t crop_top;
++    size_t crop_bottom;
++    size_t crop_left;
++    size_t crop_right;
++    /**
++     * @}
++     */
++
++} AVFrame;
++
++/**
++ * Get the buffer reference a given data plane is stored in.
++ *
++ * @param plane index of the data plane of interest in frame->extended_data.
++ *
++ * @return the buffer reference that contains the plane or NULL if the input
++ * frame is not valid.
++ */
++AVBufferRef *av_frame_get_plane_buffer(AVFrame *frame, int plane);
++
++
++#endif /* AVUTIL_FRAME_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/get_bits.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/get_bits.h
+new file mode 100644
+index 000000000..b38b8b7bf
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/get_bits.h
+@@ -0,0 +1,810 @@
++#ifndef AVCODEC_GET_BITS_H
++#define AVCODEC_GET_BITS_H
++
++#include "common.h"
++#include "intreadwrite.h"
++#include "log.h"
++#include "avassert.h"
++#include "avcodec.h"
++#include "mathops.h"
++//#include "vlc.h"
++
++#define UNCHECKED_BITSTREAM_READER 1
++
++/*
++ * Safe bitstream reading:
++ * optionally, the get_bits API can check to ensure that we
++ * don't read past input buffer boundaries. This is protected
++ * with CONFIG_SAFE_BITSTREAM_READER at the global level, and
++ * then below that with UNCHECKED_BITSTREAM_READER at the per-
++ * decoder level. This means that decoders that check internally
++ * can "#define UNCHECKED_BITSTREAM_READER 1" to disable
++ * overread checks.
++ * Boundary checking causes a minor performance penalty so for
++ * applications that won't want/need this, it can be disabled
++ * globally using "#define CONFIG_SAFE_BITSTREAM_READER 0".
++ */
++#ifndef UNCHECKED_BITSTREAM_READER
++#define UNCHECKED_BITSTREAM_READER !CONFIG_SAFE_BITSTREAM_READER
++#endif
++
++#ifndef CACHED_BITSTREAM_READER
++#define CACHED_BITSTREAM_READER 0
++#endif
++
++typedef struct GetBitContext {
++    const uint8_t *buffer, *buffer_end;
++#if CACHED_BITSTREAM_READER
++    uint64_t cache;
++    unsigned bits_left;
++#endif
++    int index;
++    int size_in_bits;
++    int size_in_bits_plus8;
++} GetBitContext;
++
++static inline unsigned int get_bits(GetBitContext *s, int n);
++static inline void skip_bits(GetBitContext *s, int n);
++static inline unsigned int show_bits(GetBitContext *s, int n);
++
++/* Bitstream reader API docs:
++ * name
++ *   arbitrary name which is used as prefix for the internal variables
++ *
++ * gb
++ *   getbitcontext
++ *
++ * OPEN_READER(name, gb)
++ *   load gb into local variables
++ *
++ * CLOSE_READER(name, gb)
++ *   store local vars in gb
++ *
++ * UPDATE_CACHE(name, gb)
++ *   Refill the internal cache from the bitstream.
++ *   After this call at least MIN_CACHE_BITS will be available.
++ *
++ * GET_CACHE(name, gb)
++ *   Will output the contents of the internal cache,
++ *   next bit is MSB of 32 or 64 bits (FIXME 64 bits).
++ *
++ * SHOW_UBITS(name, gb, num)
++ *   Will return the next num bits.
++ *
++ * SHOW_SBITS(name, gb, num)
++ *   Will return the next num bits and do sign extension.
++ *
++ * SKIP_BITS(name, gb, num)
++ *   Will skip over the next num bits.
++ *   Note, this is equivalent to SKIP_CACHE; SKIP_COUNTER.
++ *
++ * SKIP_CACHE(name, gb, num)
++ *   Will remove the next num bits from the cache (note SKIP_COUNTER
++ *   MUST be called before UPDATE_CACHE / CLOSE_READER).
++ *
++ * SKIP_COUNTER(name, gb, num)
++ *   Will increment the internal bit counter (see SKIP_CACHE & SKIP_BITS).
++ *
++ * LAST_SKIP_BITS(name, gb, num)
++ *   Like SKIP_BITS, to be used if next call is UPDATE_CACHE or CLOSE_READER.
++ *
++ * BITS_LEFT(name, gb)
++ *   Return the number of bits left
++ *
++ * For examples see get_bits, show_bits, skip_bits, get_vlc.
++ */
++
++#if CACHED_BITSTREAM_READER
++#   define MIN_CACHE_BITS 64
++#elif defined LONG_BITSTREAM_READER
++#   define MIN_CACHE_BITS 32
++#else
++#   define MIN_CACHE_BITS 25
++#endif
++
++#if !CACHED_BITSTREAM_READER
++
++#define OPEN_READER_NOSIZE(name, gb)            \
++    unsigned int name ## _index = (gb)->index;  \
++    unsigned int __maybe_unused name ## _cache
++
++#if UNCHECKED_BITSTREAM_READER
++#define OPEN_READER(name, gb) OPEN_READER_NOSIZE(name, gb)
++
++#define BITS_AVAILABLE(name, gb) 1
++#else
++#define OPEN_READER(name, gb)                   \
++    OPEN_READER_NOSIZE(name, gb);               \
++    unsigned int name ## _size_plus8 = (gb)->size_in_bits_plus8
++
++#define BITS_AVAILABLE(name, gb) name ## _index < name ## _size_plus8
++#endif
++
++#define CLOSE_READER(name, gb) (gb)->index = name ## _index
++
++# ifdef LONG_BITSTREAM_READER
++
++# define UPDATE_CACHE_LE(name, gb) name ## _cache = \
++      AV_RL64((gb)->buffer + (name ## _index >> 3)) >> (name ## _index & 7)
++
++# define UPDATE_CACHE_BE(name, gb) name ## _cache = \
++      AV_RB64((gb)->buffer + (name ## _index >> 3)) >> (32 - (name ## _index & 7))
++
++#else
++
++# define UPDATE_CACHE_LE(name, gb) name ## _cache = \
++      AV_RL32((gb)->buffer + (name ## _index >> 3)) >> (name ## _index & 7)
++
++# define UPDATE_CACHE_BE(name, gb) name ## _cache = \
++      AV_RB32((gb)->buffer + (name ## _index >> 3)) << (name ## _index & 7)
++
++#endif
++
++
++#ifdef BITSTREAM_READER_LE
++
++# define UPDATE_CACHE(name, gb) UPDATE_CACHE_LE(name, gb)
++
++# define SKIP_CACHE(name, gb, num) name ## _cache >>= (num)
++
++#else
++
++# define UPDATE_CACHE(name, gb) UPDATE_CACHE_BE(name, gb)
++
++# define SKIP_CACHE(name, gb, num) name ## _cache <<= (num)
++
++#endif
++
++#if UNCHECKED_BITSTREAM_READER
++#   define SKIP_COUNTER(name, gb, num) name ## _index += (num)
++#else
++#   define SKIP_COUNTER(name, gb, num) \
++    name ## _index = FFMIN(name ## _size_plus8, name ## _index + (num))
++#endif
++
++#define BITS_LEFT(name, gb) ((int)((gb)->size_in_bits - name ## _index))
++
++#define SKIP_BITS(name, gb, num)                \
++    do {                                        \
++        SKIP_CACHE(name, gb, num);              \
++        SKIP_COUNTER(name, gb, num);            \
++    } while (0)
++
++#define LAST_SKIP_BITS(name, gb, num) SKIP_COUNTER(name, gb, num)
++
++#define SHOW_UBITS_LE(name, gb, num) zero_extend(name ## _cache, num)
++#define SHOW_SBITS_LE(name, gb, num) sign_extend(name ## _cache, num)
++
++#define SHOW_UBITS_BE(name, gb, num) NEG_USR32(name ## _cache, num)
++#define SHOW_SBITS_BE(name, gb, num) NEG_SSR32(name ## _cache, num)
++
++#ifdef BITSTREAM_READER_LE
++#   define SHOW_UBITS(name, gb, num) SHOW_UBITS_LE(name, gb, num)
++#   define SHOW_SBITS(name, gb, num) SHOW_SBITS_LE(name, gb, num)
++#else
++#   define SHOW_UBITS(name, gb, num) SHOW_UBITS_BE(name, gb, num)
++#   define SHOW_SBITS(name, gb, num) SHOW_SBITS_BE(name, gb, num)
++#endif
++
++#define GET_CACHE(name, gb) ((uint32_t) name ## _cache)
++
++#endif
++
++static inline int get_bits_count(const GetBitContext *s)
++{
++#if CACHED_BITSTREAM_READER
++    return s->index - s->bits_left;
++#else
++    return s->index;
++#endif
++}
++
++#if CACHED_BITSTREAM_READER
++static inline void refill_32(GetBitContext *s)
++{
++#if !UNCHECKED_BITSTREAM_READER
++    if (s->index >> 3 >= s->buffer_end - s->buffer)
++        return;
++#endif
++
++#ifdef BITSTREAM_READER_LE
++    s->cache       = (uint64_t)AV_RL32(s->buffer + (s->index >> 3)) << s->bits_left | s->cache;
++#else
++    s->cache       = s->cache | (uint64_t)AV_RB32(s->buffer + (s->index >> 3)) << (32 - s->bits_left);
++#endif
++    s->index     += 32;
++    s->bits_left += 32;
++}
++
++static inline void refill_64(GetBitContext *s)
++{
++#if !UNCHECKED_BITSTREAM_READER
++    if (s->index >> 3 >= s->buffer_end - s->buffer)
++        return;
++#endif
++
++#ifdef BITSTREAM_READER_LE
++    s->cache = AV_RL64(s->buffer + (s->index >> 3));
++#else
++    s->cache = AV_RB64(s->buffer + (s->index >> 3));
++#endif
++    s->index += 64;
++    s->bits_left = 64;
++}
++
++static inline uint64_t get_val(GetBitContext *s, unsigned n, int is_le)
++{
++    uint64_t ret;
++    av_assert2(n>0 && n<=63);
++    if (is_le) {
++        ret = s->cache & ((UINT64_C(1) << n) - 1);
++        s->cache >>= n;
++    } else {
++        ret = s->cache >> (64 - n);
++        s->cache <<= n;
++    }
++    s->bits_left -= n;
++    return ret;
++}
++
++static inline unsigned show_val(const GetBitContext *s, unsigned n)
++{
++#ifdef BITSTREAM_READER_LE
++    return s->cache & ((UINT64_C(1) << n) - 1);
++#else
++    return s->cache >> (64 - n);
++#endif
++}
++#endif
++
++/**
++ * Skips the specified number of bits.
++ * @param n the number of bits to skip,
++ *          For the UNCHECKED_BITSTREAM_READER this must not cause the distance
++ *          from the start to overflow int32_t. Staying within the bitstream + padding
++ *          is sufficient, too.
++ */
++static inline void skip_bits_long(GetBitContext *s, int n)
++{
++#if CACHED_BITSTREAM_READER
++    skip_bits(s, n);
++#else
++#if UNCHECKED_BITSTREAM_READER
++    s->index += n;
++#else
++    s->index += av_clip(n, -s->index, s->size_in_bits_plus8 - s->index);
++#endif
++#endif
++}
++
++#if CACHED_BITSTREAM_READER
++static inline void skip_remaining(GetBitContext *s, unsigned n)
++{
++#ifdef BITSTREAM_READER_LE
++    s->cache >>= n;
++#else
++    s->cache <<= n;
++#endif
++    s->bits_left -= n;
++}
++#endif
++
++/**
++ * Read MPEG-1 dc-style VLC (sign bit + mantissa with no MSB).
++ * if MSB not set it is negative
++ * @param n length in bits
++ */
++static inline int get_xbits(GetBitContext *s, int n)
++{
++#if CACHED_BITSTREAM_READER
++    int32_t cache = show_bits(s, 32);
++    int sign = ~cache >> 31;
++    skip_remaining(s, n);
++
++    return ((((uint32_t)(sign ^ cache)) >> (32 - n)) ^ sign) - sign;
++#else
++    register int sign;
++    register int32_t cache;
++    OPEN_READER(re, s);
++    av_assert2(n>0 && n<=25);
++    UPDATE_CACHE(re, s);
++    cache = GET_CACHE(re, s);
++    sign  = ~cache >> 31;
++    LAST_SKIP_BITS(re, s, n);
++    CLOSE_READER(re, s);
++    return (NEG_USR32(sign ^ cache, n) ^ sign) - sign;
++#endif
++}
++
++#if !CACHED_BITSTREAM_READER
++static inline int get_xbits_le(GetBitContext *s, int n)
++{
++    register int sign;
++    register int32_t cache;
++    OPEN_READER(re, s);
++    av_assert2(n>0 && n<=25);
++    UPDATE_CACHE_LE(re, s);
++    cache = GET_CACHE(re, s);
++    sign  = sign_extend(~cache, n) >> 31;
++    LAST_SKIP_BITS(re, s, n);
++    CLOSE_READER(re, s);
++    return (zero_extend(sign ^ cache, n) ^ sign) - sign;
++}
++#endif
++
++static inline int get_sbits(GetBitContext *s, int n)
++{
++    register int tmp;
++#if CACHED_BITSTREAM_READER
++    av_assert2(n>0 && n<=25);
++    tmp = sign_extend(get_bits(s, n), n);
++#else
++    OPEN_READER(re, s);
++    av_assert2(n>0 && n<=25);
++    UPDATE_CACHE(re, s);
++    tmp = SHOW_SBITS(re, s, n);
++    LAST_SKIP_BITS(re, s, n);
++    CLOSE_READER(re, s);
++#endif
++    return tmp;
++}
++
++/**
++ * Read 1-25 bits.
++ */
++static inline unsigned int get_bits(GetBitContext *s, int n)
++{
++    register int tmp;
++#if CACHED_BITSTREAM_READER
++
++    av_assert2(n>0 && n<=32);
++    if (n > s->bits_left) {
++        refill_32(s);
++        if (s->bits_left < 32)
++            s->bits_left = n;
++    }
++
++#ifdef BITSTREAM_READER_LE
++    tmp = get_val(s, n, 1);
++#else
++    tmp = get_val(s, n, 0);
++#endif
++#else
++    OPEN_READER(re, s);
++    av_assert2(n>0 && n<=25);
++    UPDATE_CACHE(re, s);
++    tmp = SHOW_UBITS(re, s, n);
++    LAST_SKIP_BITS(re, s, n);
++    CLOSE_READER(re, s);
++#endif
++    return tmp;
++}
++
++/**
++ * Read 0-25 bits.
++ */
++static inline int get_bitsz(GetBitContext *s, int n)
++{
++    return n ? get_bits(s, n) : 0;
++}
++
++static inline unsigned int get_bits_le(GetBitContext *s, int n)
++{
++#if CACHED_BITSTREAM_READER
++    av_assert2(n>0 && n<=32);
++    if (n > s->bits_left) {
++        refill_32(s);
++        if (s->bits_left < 32)
++            s->bits_left = n;
++    }
++
++    return get_val(s, n, 1);
++#else
++    register int tmp;
++    OPEN_READER(re, s);
++    av_assert2(n>0 && n<=25);
++    UPDATE_CACHE_LE(re, s);
++    tmp = SHOW_UBITS_LE(re, s, n);
++    LAST_SKIP_BITS(re, s, n);
++    CLOSE_READER(re, s);
++    return tmp;
++#endif
++}
++
++/**
++ * Show 1-25 bits.
++ */
++static inline unsigned int show_bits(GetBitContext *s, int n)
++{
++    register int tmp;
++#if CACHED_BITSTREAM_READER
++    if (n > s->bits_left)
++        refill_32(s);
++
++    tmp = show_val(s, n);
++#else
++    OPEN_READER_NOSIZE(re, s);
++    av_assert2(n>0 && n<=25);
++    UPDATE_CACHE(re, s);
++    tmp = SHOW_UBITS(re, s, n);
++#endif
++    return tmp;
++}
++
++static inline void skip_bits(GetBitContext *s, int n)
++{
++#if CACHED_BITSTREAM_READER
++    if (n < s->bits_left)
++        skip_remaining(s, n);
++    else {
++        n -= s->bits_left;
++        s->cache = 0;
++        s->bits_left = 0;
++
++        if (n >= 64) {
++            unsigned skip = (n / 8) * 8;
++
++            n -= skip;
++            s->index += skip;
++        }
++        refill_64(s);
++        if (n)
++            skip_remaining(s, n);
++    }
++#else
++    OPEN_READER(re, s);
++    LAST_SKIP_BITS(re, s, n);
++    CLOSE_READER(re, s);
++#endif
++}
++
++static inline unsigned int get_bits1(GetBitContext *s)
++{
++#if CACHED_BITSTREAM_READER
++    if (!s->bits_left)
++        refill_64(s);
++
++#ifdef BITSTREAM_READER_LE
++    return get_val(s, 1, 1);
++#else
++    return get_val(s, 1, 0);
++#endif
++#else
++    unsigned int index = s->index;
++    uint8_t result     = s->buffer[index >> 3];
++#ifdef BITSTREAM_READER_LE
++    result >>= index & 7;
++    result  &= 1;
++#else
++    result <<= index & 7;
++    result >>= 8 - 1;
++#endif
++#if !UNCHECKED_BITSTREAM_READER
++    if (s->index < s->size_in_bits_plus8)
++#endif
++        index++;
++    s->index = index;
++
++    return result;
++#endif
++}
++
++static inline unsigned int show_bits1(GetBitContext *s)
++{
++    return show_bits(s, 1);
++}
++
++static inline void skip_bits1(GetBitContext *s)
++{
++    skip_bits(s, 1);
++}
++
++/**
++ * Read 0-32 bits.
++ */
++static inline unsigned int get_bits_long(GetBitContext *s, int n)
++{
++    av_assert2(n>=0 && n<=32);
++    if (!n) {
++        return 0;
++#if CACHED_BITSTREAM_READER
++    }
++    return get_bits(s, n);
++#else
++    } else if (n <= MIN_CACHE_BITS) {
++        return get_bits(s, n);
++    } else {
++#ifdef BITSTREAM_READER_LE
++        unsigned ret = get_bits(s, 16);
++        return ret | (get_bits(s, n - 16) << 16);
++#else
++        unsigned ret = get_bits(s, 16) << (n - 16);
++        return ret | get_bits(s, n - 16);
++#endif
++    }
++#endif
++}
++
++/**
++ * Read 0-64 bits.
++ */
++static inline uint64_t get_bits64(GetBitContext *s, int n)
++{
++    if (n <= 32) {
++        return get_bits_long(s, n);
++    } else {
++#ifdef BITSTREAM_READER_LE
++        uint64_t ret = get_bits_long(s, 32);
++        return ret | (uint64_t) get_bits_long(s, n - 32) << 32;
++#else
++        uint64_t ret = (uint64_t) get_bits_long(s, n - 32) << 32;
++        return ret | get_bits_long(s, 32);
++#endif
++    }
++}
++
++/**
++ * Read 0-32 bits as a signed integer.
++ */
++static inline int get_sbits_long(GetBitContext *s, int n)
++{
++    // sign_extend(x, 0) is undefined
++    if (!n)
++        return 0;
++
++    return sign_extend(get_bits_long(s, n), n);
++}
++
++/**
++ * Show 0-32 bits.
++ */
++static inline unsigned int show_bits_long(GetBitContext *s, int n)
++{
++    if (n <= MIN_CACHE_BITS) {
++        return show_bits(s, n);
++    } else {
++        GetBitContext gb = *s;
++        return get_bits_long(&gb, n);
++    }
++}
++
++static inline int check_marker(void *logctx, GetBitContext *s, const char *msg)
++{
++    int bit = get_bits1(s);
++    if (!bit)
++        av_log(logctx, AV_LOG_INFO, "Marker bit missing at %d of %d %s\n",
++               get_bits_count(s) - 1, s->size_in_bits, msg);
++
++    return bit;
++}
++
++/**
++ * Initialize GetBitContext.
++ * @param buffer bitstream buffer, must be AV_INPUT_BUFFER_PADDING_SIZE bytes
++ *        larger than the actual read bits because some optimized bitstream
++ *        readers read 32 or 64 bit at once and could read over the end
++ * @param bit_size the size of the buffer in bits
++ * @return 0 on success, AVERROR_INVALIDDATA if the buffer_size would overflow.
++ */
++static inline int init_get_bits(GetBitContext *s, const uint8_t *buffer,
++                                int bit_size)
++{
++    int buffer_size;
++    int ret = 0;
++
++    if (bit_size >= INT_MAX - FFMAX(7, AV_INPUT_BUFFER_PADDING_SIZE*8) || bit_size < 0 || !buffer) {
++        bit_size    = 0;
++        buffer      = NULL;
++        ret         = AVERROR_INVALIDDATA;
++    }
++
++    buffer_size = (bit_size + 7) >> 3;
++
++    s->buffer             = buffer;
++    s->size_in_bits       = bit_size;
++    s->size_in_bits_plus8 = bit_size + 8;
++    s->buffer_end         = buffer + buffer_size;
++    s->index              = 0;
++
++#if CACHED_BITSTREAM_READER
++    refill_64(s);
++#endif
++
++    return ret;
++}
++
++/**
++ * Initialize GetBitContext.
++ * @param buffer bitstream buffer, must be AV_INPUT_BUFFER_PADDING_SIZE bytes
++ *        larger than the actual read bits because some optimized bitstream
++ *        readers read 32 or 64 bit at once and could read over the end
++ * @param byte_size the size of the buffer in bytes
++ * @return 0 on success, AVERROR_INVALIDDATA if the buffer_size would overflow.
++ */
++static inline int init_get_bits8(GetBitContext *s, const uint8_t *buffer,
++                                 int byte_size)
++{
++    if (byte_size > INT_MAX / 8 || byte_size < 0)
++        byte_size = -1;
++    return init_get_bits(s, buffer, byte_size * 8);
++}
++
++static inline const uint8_t *align_get_bits(GetBitContext *s)
++{
++    int n = -get_bits_count(s) & 7;
++    if (n)
++        skip_bits(s, n);
++    return s->buffer + (s->index >> 3);
++}
++
++#if 0
++/**
++ * If the vlc code is invalid and max_depth=1, then no bits will be removed.
++ * If the vlc code is invalid and max_depth>1, then the number of bits removed
++ * is undefined.
++ */
++#define GET_VLC(code, name, gb, table, bits, max_depth)         \
++    do {                                                        \
++        int n, nb_bits;                                         \
++        unsigned int index;                                     \
++                                                                \
++        index = SHOW_UBITS(name, gb, bits);                     \
++        code  = table[index][0];                                \
++        n     = table[index][1];                                \
++                                                                \
++        if (max_depth > 1 && n < 0) {                           \
++            LAST_SKIP_BITS(name, gb, bits);                     \
++            UPDATE_CACHE(name, gb);                             \
++                                                                \
++            nb_bits = -n;                                       \
++                                                                \
++            index = SHOW_UBITS(name, gb, nb_bits) + code;       \
++            code  = table[index][0];                            \
++            n     = table[index][1];                            \
++            if (max_depth > 2 && n < 0) {                       \
++                LAST_SKIP_BITS(name, gb, nb_bits);              \
++                UPDATE_CACHE(name, gb);                         \
++                                                                \
++                nb_bits = -n;                                   \
++                                                                \
++                index = SHOW_UBITS(name, gb, nb_bits) + code;   \
++                code  = table[index][0];                        \
++                n     = table[index][1];                        \
++            }                                                   \
++        }                                                       \
++        SKIP_BITS(name, gb, n);                                 \
++    } while (0)
++
++#define GET_RL_VLC(level, run, name, gb, table, bits,  \
++                   max_depth, need_update)                      \
++    do {                                                        \
++        int n, nb_bits;                                         \
++        unsigned int index;                                     \
++                                                                \
++        index = SHOW_UBITS(name, gb, bits);                     \
++        level = table[index].level;                             \
++        n     = table[index].len;                               \
++                                                                \
++        if (max_depth > 1 && n < 0) {                           \
++            SKIP_BITS(name, gb, bits);                          \
++            if (need_update) {                                  \
++                UPDATE_CACHE(name, gb);                         \
++            }                                                   \
++                                                                \
++            nb_bits = -n;                                       \
++                                                                \
++            index = SHOW_UBITS(name, gb, nb_bits) + level;      \
++            level = table[index].level;                         \
++            n     = table[index].len;                           \
++            if (max_depth > 2 && n < 0) {                       \
++                LAST_SKIP_BITS(name, gb, nb_bits);              \
++                if (need_update) {                              \
++                    UPDATE_CACHE(name, gb);                     \
++                }                                               \
++                nb_bits = -n;                                   \
++                                                                \
++                index = SHOW_UBITS(name, gb, nb_bits) + level;  \
++                level = table[index].level;                     \
++                n     = table[index].len;                       \
++            }                                                   \
++        }                                                       \
++        run = table[index].run;                                 \
++        SKIP_BITS(name, gb, n);                                 \
++    } while (0)
++
++/* Return the LUT element for the given bitstream configuration. */
++static inline int set_idx(GetBitContext *s, int code, int *n, int *nb_bits,
++                          VLC_TYPE (*table)[2])
++{
++    unsigned idx;
++
++    *nb_bits = -*n;
++    idx = show_bits(s, *nb_bits) + code;
++    *n = table[idx][1];
++
++    return table[idx][0];
++}
++
++/**
++ * Parse a vlc code.
++ * @param bits is the number of bits which will be read at once, must be
++ *             identical to nb_bits in init_vlc()
++ * @param max_depth is the number of times bits bits must be read to completely
++ *                  read the longest vlc code
++ *                  = (max_vlc_length + bits - 1) / bits
++ * @returns the code parsed or -1 if no vlc matches
++ */
++static inline int get_vlc2(GetBitContext *s, VLC_TYPE (*table)[2],
++                                     int bits, int max_depth)
++{
++#if CACHED_BITSTREAM_READER
++    int nb_bits;
++    unsigned idx = show_bits(s, bits);
++    int code = table[idx][0];
++    int n    = table[idx][1];
++
++    if (max_depth > 1 && n < 0) {
++        skip_remaining(s, bits);
++        code = set_idx(s, code, &n, &nb_bits, table);
++        if (max_depth > 2 && n < 0) {
++            skip_remaining(s, nb_bits);
++            code = set_idx(s, code, &n, &nb_bits, table);
++        }
++    }
++    skip_remaining(s, n);
++
++    return code;
++#else
++    int code;
++
++    OPEN_READER(re, s);
++    UPDATE_CACHE(re, s);
++
++    GET_VLC(code, re, s, table, bits, max_depth);
++
++    CLOSE_READER(re, s);
++
++    return code;
++#endif
++}
++#endif
++
++static inline int decode012(GetBitContext *gb)
++{
++    int n;
++    n = get_bits1(gb);
++    if (n == 0)
++        return 0;
++    else
++        return get_bits1(gb) + 1;
++}
++
++static inline int decode210(GetBitContext *gb)
++{
++    if (get_bits1(gb))
++        return 0;
++    else
++        return 2 - get_bits1(gb);
++}
++
++static inline int get_bits_left(GetBitContext *gb)
++{
++    return gb->size_in_bits - get_bits_count(gb);
++}
++
++static inline int skip_1stop_8data_bits(GetBitContext *gb)
++{
++    if (get_bits_left(gb) <= 0)
++        return AVERROR_INVALIDDATA;
++
++    while (get_bits1(gb)) {
++        skip_bits(gb, 8);
++        if (get_bits_left(gb) <= 0)
++            return AVERROR_INVALIDDATA;
++    }
++
++    return 0;
++}
++
++
++#endif /* AVCODEC_GET_BITS_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/golomb.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/golomb.h
+new file mode 100644
+index 000000000..6ad02b412
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/golomb.h
+@@ -0,0 +1,715 @@
++#ifndef AVCODEC_GOLOMB_H
++#define AVCODEC_GOLOMB_H
++
++
++//#include <libavutil/internal.h>
++
++#include "get_bits.h"
++#include "put_bits.h"
++
++#define INVALID_VLC           0x80000000
++
++extern const uint8_t ff_golomb_vlc_len[512];
++extern const uint8_t ff_ue_golomb_vlc_code[512];
++extern const  int8_t ff_se_golomb_vlc_code[512];
++extern const uint8_t ff_ue_golomb_len[256];
++
++extern const uint8_t ff_interleaved_golomb_vlc_len[256];
++extern const uint8_t ff_interleaved_ue_golomb_vlc_code[256];
++extern const  int8_t ff_interleaved_se_golomb_vlc_code[256];
++extern const uint8_t ff_interleaved_dirac_golomb_vlc_code[256];
++
++/**
++ * Read an unsigned Exp-Golomb code in the range 0 to 8190.
++ *
++ * @returns the read value or a negative error code.
++ */
++static inline int get_ue_golomb(GetBitContext *gb)
++{
++    unsigned int buf;
++
++#if CACHED_BITSTREAM_READER
++    buf = show_bits_long(gb, 32);
++
++    if (buf >= (1 << 27)) {
++        buf >>= 32 - 9;
++        skip_bits_long(gb, ff_golomb_vlc_len[buf]);
++
++        return ff_ue_golomb_vlc_code[buf];
++    } else {
++        int log = 2 * av_log2(buf) - 31;
++        buf >>= log;
++        buf--;
++        skip_bits_long(gb, 32 - log);
++
++        return buf;
++    }
++#else
++    OPEN_READER(re, gb);
++    UPDATE_CACHE(re, gb);
++    buf = GET_CACHE(re, gb);
++
++    if (buf >= (1 << 27)) {
++        buf >>= 32 - 9;
++        LAST_SKIP_BITS(re, gb, ff_golomb_vlc_len[buf]);
++        CLOSE_READER(re, gb);
++
++        return ff_ue_golomb_vlc_code[buf];
++    } else {
++        int log = 2 * av_log2(buf) - 31;
++        LAST_SKIP_BITS(re, gb, 32 - log);
++        CLOSE_READER(re, gb);
++        if (log < 7) {
++            av_log(NULL, AV_LOG_ERROR, "Invalid UE golomb code\n");
++            return AVERROR_INVALIDDATA;
++        }
++        buf >>= log;
++        buf--;
++
++        return buf;
++    }
++#endif
++}
++
++/**
++ * Read an unsigned Exp-Golomb code in the range 0 to UINT32_MAX-1.
++ */
++static inline unsigned get_ue_golomb_long(GetBitContext *gb)
++{
++    unsigned buf, log;
++
++    buf = show_bits_long(gb, 32);
++    log = 31 - av_log2(buf);
++    skip_bits_long(gb, log);
++
++    return get_bits_long(gb, log + 1) - 1;
++}
++
++/**
++ * read unsigned exp golomb code, constraint to a max of 31.
++ * the return value is undefined if the stored value exceeds 31.
++ */
++static inline int get_ue_golomb_31(GetBitContext *gb)
++{
++    unsigned int buf;
++
++#if CACHED_BITSTREAM_READER
++    buf = show_bits_long(gb, 32);
++
++    buf >>= 32 - 9;
++    skip_bits_long(gb, ff_golomb_vlc_len[buf]);
++#else
++
++    OPEN_READER(re, gb);
++    UPDATE_CACHE(re, gb);
++    buf = GET_CACHE(re, gb);
++
++    buf >>= 32 - 9;
++    LAST_SKIP_BITS(re, gb, ff_golomb_vlc_len[buf]);
++    CLOSE_READER(re, gb);
++#endif
++
++    return ff_ue_golomb_vlc_code[buf];
++}
++
++static inline unsigned get_interleaved_ue_golomb(GetBitContext *gb)
++{
++    uint32_t buf;
++
++#if CACHED_BITSTREAM_READER
++    buf = show_bits_long(gb, 32);
++
++    if (buf & 0xAA800000) {
++        buf >>= 32 - 8;
++        skip_bits_long(gb, ff_interleaved_golomb_vlc_len[buf]);
++
++        return ff_interleaved_ue_golomb_vlc_code[buf];
++    } else {
++        unsigned ret = 1;
++
++        do {
++            buf >>= 32 - 8;
++            skip_bits_long(gb, FFMIN(ff_interleaved_golomb_vlc_len[buf], 8));
++
++            if (ff_interleaved_golomb_vlc_len[buf] != 9) {
++                ret <<= (ff_interleaved_golomb_vlc_len[buf] - 1) >> 1;
++                ret  |= ff_interleaved_dirac_golomb_vlc_code[buf];
++                break;
++            }
++            ret = (ret << 4) | ff_interleaved_dirac_golomb_vlc_code[buf];
++            buf = show_bits_long(gb, 32);
++        } while (get_bits_left(gb) > 0);
++
++        return ret - 1;
++    }
++#else
++    OPEN_READER(re, gb);
++    UPDATE_CACHE(re, gb);
++    buf = GET_CACHE(re, gb);
++
++    if (buf & 0xAA800000) {
++        buf >>= 32 - 8;
++        LAST_SKIP_BITS(re, gb, ff_interleaved_golomb_vlc_len[buf]);
++        CLOSE_READER(re, gb);
++
++        return ff_interleaved_ue_golomb_vlc_code[buf];
++    } else {
++        unsigned ret = 1;
++
++        do {
++            buf >>= 32 - 8;
++            LAST_SKIP_BITS(re, gb,
++                           FFMIN(ff_interleaved_golomb_vlc_len[buf], 8));
++
++            if (ff_interleaved_golomb_vlc_len[buf] != 9) {
++                ret <<= (ff_interleaved_golomb_vlc_len[buf] - 1) >> 1;
++                ret  |= ff_interleaved_dirac_golomb_vlc_code[buf];
++                break;
++            }
++            ret = (ret << 4) | ff_interleaved_dirac_golomb_vlc_code[buf];
++            UPDATE_CACHE(re, gb);
++            buf = GET_CACHE(re, gb);
++        } while (ret<0x8000000U && BITS_AVAILABLE(re, gb));
++
++        CLOSE_READER(re, gb);
++        return ret - 1;
++    }
++#endif
++}
++
++/**
++ * read unsigned truncated exp golomb code.
++ */
++static inline int get_te0_golomb(GetBitContext *gb, int range)
++{
++    av_assert2(range >= 1);
++
++    if (range == 1)
++        return 0;
++    else if (range == 2)
++        return get_bits1(gb) ^ 1;
++    else
++        return get_ue_golomb(gb);
++}
++
++/**
++ * read unsigned truncated exp golomb code.
++ */
++static inline int get_te_golomb(GetBitContext *gb, int range)
++{
++    av_assert2(range >= 1);
++
++    if (range == 2)
++        return get_bits1(gb) ^ 1;
++    else
++        return get_ue_golomb(gb);
++}
++
++/**
++ * read signed exp golomb code.
++ */
++static inline int get_se_golomb(GetBitContext *gb)
++{
++    unsigned int buf;
++
++#if CACHED_BITSTREAM_READER
++    buf = show_bits_long(gb, 32);
++
++    if (buf >= (1 << 27)) {
++        buf >>= 32 - 9;
++        skip_bits_long(gb, ff_golomb_vlc_len[buf]);
++
++        return ff_se_golomb_vlc_code[buf];
++    } else {
++        int log = 2 * av_log2(buf) - 31;
++        buf >>= log;
++
++        skip_bits_long(gb, 32 - log);
++
++        if (buf & 1)
++            buf = -(buf >> 1);
++        else
++            buf = (buf >> 1);
++
++        return buf;
++    }
++#else
++    OPEN_READER(re, gb);
++    UPDATE_CACHE(re, gb);
++    buf = GET_CACHE(re, gb);
++
++    if (buf >= (1 << 27)) {
++        buf >>= 32 - 9;
++        LAST_SKIP_BITS(re, gb, ff_golomb_vlc_len[buf]);
++        CLOSE_READER(re, gb);
++
++        return ff_se_golomb_vlc_code[buf];
++    } else {
++        int log = av_log2(buf), sign;
++        LAST_SKIP_BITS(re, gb, 31 - log);
++        UPDATE_CACHE(re, gb);
++        buf = GET_CACHE(re, gb);
++
++        buf >>= log;
++
++        LAST_SKIP_BITS(re, gb, 32 - log);
++        CLOSE_READER(re, gb);
++
++        sign = -(buf & 1);
++        buf  = ((buf >> 1) ^ sign) - sign;
++
++        return buf;
++    }
++#endif
++}
++
++static inline int get_se_golomb_long(GetBitContext *gb)
++{
++    unsigned int buf = get_ue_golomb_long(gb);
++    int sign = (buf & 1) - 1;
++    return ((buf >> 1) ^ sign) + 1;
++}
++
++static inline int get_interleaved_se_golomb(GetBitContext *gb)
++{
++    unsigned int buf;
++
++#if CACHED_BITSTREAM_READER
++    buf = show_bits_long(gb, 32);
++
++    if (buf & 0xAA800000) {
++        buf >>= 32 - 8;
++        skip_bits_long(gb, ff_interleaved_golomb_vlc_len[buf]);
++
++        return ff_interleaved_se_golomb_vlc_code[buf];
++    } else {
++        int log;
++        skip_bits(gb, 8);
++        buf |= 1 | show_bits_long(gb, 24);
++
++        if ((buf & 0xAAAAAAAA) == 0)
++            return INVALID_VLC;
++
++        for (log = 31; (buf & 0x80000000) == 0; log--)
++            buf = (buf << 2) - ((buf << log) >> (log - 1)) + (buf >> 30);
++
++        skip_bits_long(gb, 63 - 2 * log - 8);
++
++        return (signed) (((((buf << log) >> log) - 1) ^ -(buf & 0x1)) + 1) >> 1;
++    }
++#else
++    OPEN_READER(re, gb);
++    UPDATE_CACHE(re, gb);
++    buf = GET_CACHE(re, gb);
++
++    if (buf & 0xAA800000) {
++        buf >>= 32 - 8;
++        LAST_SKIP_BITS(re, gb, ff_interleaved_golomb_vlc_len[buf]);
++        CLOSE_READER(re, gb);
++
++        return ff_interleaved_se_golomb_vlc_code[buf];
++    } else {
++        int log;
++        LAST_SKIP_BITS(re, gb, 8);
++        UPDATE_CACHE(re, gb);
++        buf |= 1 | (GET_CACHE(re, gb) >> 8);
++
++        if ((buf & 0xAAAAAAAA) == 0)
++            return INVALID_VLC;
++
++        for (log = 31; (buf & 0x80000000) == 0; log--)
++            buf = (buf << 2) - ((buf << log) >> (log - 1)) + (buf >> 30);
++
++        LAST_SKIP_BITS(re, gb, 63 - 2 * log - 8);
++        CLOSE_READER(re, gb);
++
++        return (signed) (((((buf << log) >> log) - 1) ^ -(buf & 0x1)) + 1) >> 1;
++    }
++#endif
++}
++
++static inline int dirac_get_se_golomb(GetBitContext *gb)
++{
++    uint32_t ret = get_interleaved_ue_golomb(gb);
++
++    if (ret) {
++        int sign = -get_bits1(gb);
++        ret = (ret ^ sign) - sign;
++    }
++
++    return ret;
++}
++
++/**
++ * read unsigned golomb rice code (ffv1).
++ */
++static inline int get_ur_golomb(GetBitContext *gb, int k, int limit,
++                                int esc_len)
++{
++    unsigned int buf;
++    int log;
++
++#if CACHED_BITSTREAM_READER
++    buf = show_bits_long(gb, 32);
++
++    log = av_log2(buf);
++
++    if (log > 31 - limit) {
++        buf >>= log - k;
++        buf  += (30 - log) << k;
++        skip_bits_long(gb, 32 + k - log);
++
++        return buf;
++    } else {
++        skip_bits_long(gb, limit);
++        buf = get_bits_long(gb, esc_len);
++
++        return buf + limit - 1;
++    }
++#else
++    OPEN_READER(re, gb);
++    UPDATE_CACHE(re, gb);
++    buf = GET_CACHE(re, gb);
++
++    log = av_log2(buf);
++
++    if (log > 31 - limit) {
++        buf >>= log - k;
++        buf  += (30U - log) << k;
++        LAST_SKIP_BITS(re, gb, 32 + k - log);
++        CLOSE_READER(re, gb);
++
++        return buf;
++    } else {
++        LAST_SKIP_BITS(re, gb, limit);
++        UPDATE_CACHE(re, gb);
++
++        buf = SHOW_UBITS(re, gb, esc_len);
++
++        LAST_SKIP_BITS(re, gb, esc_len);
++        CLOSE_READER(re, gb);
++
++        return buf + limit - 1;
++    }
++#endif
++}
++
++/**
++ * read unsigned golomb rice code (jpegls).
++ */
++static inline int get_ur_golomb_jpegls(GetBitContext *gb, int k, int limit,
++                                       int esc_len)
++{
++    unsigned int buf;
++    int log;
++
++#if CACHED_BITSTREAM_READER
++    buf = show_bits_long(gb, 32);
++
++    log = av_log2(buf);
++
++    if (log - k >= 1 && 32 - log < limit) {
++        buf >>= log - k;
++        buf  += (30 - log) << k;
++        skip_bits_long(gb, 32 + k - log);
++
++        return buf;
++    } else {
++        int i;
++        for (i = 0;
++             i < limit && get_bits1(gb) == 0 && get_bits_left(gb) > 0;
++             i++);
++
++        if (i < limit - 1) {
++            buf = get_bits_long(gb, k);
++
++            return buf + (i << k);
++        } else if (i == limit - 1) {
++            buf = get_bits_long(gb, esc_len);
++
++            return buf + 1;
++        } else
++            return -1;
++    }
++#else
++    OPEN_READER(re, gb);
++    UPDATE_CACHE(re, gb);
++    buf = GET_CACHE(re, gb);
++
++    log = av_log2(buf);
++
++    av_assert2(k <= 31);
++
++    if (log - k >= 32 - MIN_CACHE_BITS + (MIN_CACHE_BITS == 32) &&
++        32 - log < limit) {
++        buf >>= log - k;
++        buf  += (30U - log) << k;
++        LAST_SKIP_BITS(re, gb, 32 + k - log);
++        CLOSE_READER(re, gb);
++
++        return buf;
++    } else {
++        int i;
++        for (i = 0; i < limit && SHOW_UBITS(re, gb, 1) == 0; i++) {
++            if (gb->size_in_bits <= re_index) {
++                CLOSE_READER(re, gb);
++                return -1;
++            }
++            LAST_SKIP_BITS(re, gb, 1);
++            UPDATE_CACHE(re, gb);
++        }
++        SKIP_BITS(re, gb, 1);
++
++        if (i < limit - 1) {
++            if (k) {
++                if (k > MIN_CACHE_BITS - 1) {
++                    buf = SHOW_UBITS(re, gb, 16) << (k-16);
++                    LAST_SKIP_BITS(re, gb, 16);
++                    UPDATE_CACHE(re, gb);
++                    buf |= SHOW_UBITS(re, gb, k-16);
++                    LAST_SKIP_BITS(re, gb, k-16);
++                } else {
++                    buf = SHOW_UBITS(re, gb, k);
++                    LAST_SKIP_BITS(re, gb, k);
++                }
++            } else {
++                buf = 0;
++            }
++
++            buf += ((unsigned)i << k);
++        } else if (i == limit - 1) {
++            buf = SHOW_UBITS(re, gb, esc_len);
++            LAST_SKIP_BITS(re, gb, esc_len);
++
++            buf ++;
++        } else {
++            buf = -1;
++        }
++        CLOSE_READER(re, gb);
++        return buf;
++    }
++#endif
++}
++
++/**
++ * read signed golomb rice code (ffv1).
++ */
++static inline int get_sr_golomb(GetBitContext *gb, int k, int limit,
++                                int esc_len)
++{
++    unsigned v = get_ur_golomb(gb, k, limit, esc_len);
++    return (v >> 1) ^ -(v & 1);
++}
++
++/**
++ * read signed golomb rice code (flac).
++ */
++static inline int get_sr_golomb_flac(GetBitContext *gb, int k, int limit,
++                                     int esc_len)
++{
++    unsigned v = get_ur_golomb_jpegls(gb, k, limit, esc_len);
++    return (v >> 1) ^ -(v & 1);
++}
++
++/**
++ * read unsigned golomb rice code (shorten).
++ */
++static inline unsigned int get_ur_golomb_shorten(GetBitContext *gb, int k)
++{
++    return get_ur_golomb_jpegls(gb, k, INT_MAX, 0);
++}
++
++/**
++ * read signed golomb rice code (shorten).
++ */
++static inline int get_sr_golomb_shorten(GetBitContext *gb, int k)
++{
++    int uvar = get_ur_golomb_jpegls(gb, k + 1, INT_MAX, 0);
++    return (uvar >> 1) ^ -(uvar & 1);
++}
++
++#ifdef TRACE
++
++static inline int get_ue(GetBitContext *s, const char *file, const char *func,
++                         int line)
++{
++    int show = show_bits(s, 24);
++    int pos  = get_bits_count(s);
++    int i    = get_ue_golomb(s);
++    int len  = get_bits_count(s) - pos;
++    int bits = show >> (24 - len);
++
++    av_log(NULL, AV_LOG_DEBUG, "%5d %2d %3d ue  @%5d in %s %s:%d\n",
++           bits, len, i, pos, file, func, line);
++
++    return i;
++}
++
++static inline int get_se(GetBitContext *s, const char *file, const char *func,
++                         int line)
++{
++    int show = show_bits(s, 24);
++    int pos  = get_bits_count(s);
++    int i    = get_se_golomb(s);
++    int len  = get_bits_count(s) - pos;
++    int bits = show >> (24 - len);
++
++    av_log(NULL, AV_LOG_DEBUG, "%5d %2d %3d se  @%5d in %s %s:%d\n",
++           bits, len, i, pos, file, func, line);
++
++    return i;
++}
++
++static inline int get_te(GetBitContext *s, int r, char *file, const char *func,
++                         int line)
++{
++    int show = show_bits(s, 24);
++    int pos  = get_bits_count(s);
++    int i    = get_te0_golomb(s, r);
++    int len  = get_bits_count(s) - pos;
++    int bits = show >> (24 - len);
++
++    av_log(NULL, AV_LOG_DEBUG, "%5d %2d %3d te  @%5d in %s %s:%d\n",
++           bits, len, i, pos, file, func, line);
++
++    return i;
++}
++
++#define get_ue_golomb(a) get_ue(a, __FILE__, __func__, __LINE__)
++#define get_se_golomb(a) get_se(a, __FILE__, __func__, __LINE__)
++#define get_te_golomb(a, r)  get_te(a, r, __FILE__, __func__, __LINE__)
++#define get_te0_golomb(a, r) get_te(a, r, __FILE__, __func__, __LINE__)
++
++#endif /* TRACE */
++
++/**
++ * write unsigned exp golomb code. 2^16 - 2 at most
++ */
++static inline void set_ue_golomb(PutBitContext *pb, int i)
++{
++    av_assert2(i >= 0);
++    av_assert2(i <= 0xFFFE);
++
++    if (i < 256)
++        put_bits(pb, ff_ue_golomb_len[i], i + 1);
++    else {
++        int e = av_log2(i + 1);
++        put_bits(pb, 2 * e + 1, i + 1);
++    }
++}
++
++/**
++ * write unsigned exp golomb code. 2^32-2 at most.
++ */
++static inline void set_ue_golomb_long(PutBitContext *pb, uint32_t i)
++{
++    av_assert2(i <= (UINT32_MAX - 1));
++
++    if (i < 256)
++        put_bits(pb, ff_ue_golomb_len[i], i + 1);
++    else {
++        int e = av_log2(i + 1);
++        put_bits64(pb, 2 * e + 1, i + 1);
++    }
++}
++
++/**
++ * write truncated unsigned exp golomb code.
++ */
++static inline void set_te_golomb(PutBitContext *pb, int i, int range)
++{
++    av_assert2(range >= 1);
++    av_assert2(i <= range);
++
++    if (range == 2)
++        put_bits(pb, 1, i ^ 1);
++    else
++        set_ue_golomb(pb, i);
++}
++
++/**
++ * write signed exp golomb code. 16 bits at most.
++ */
++static inline void set_se_golomb(PutBitContext *pb, int i)
++{
++    i = 2 * i - 1;
++    if (i < 0)
++        i ^= -1;    //FIXME check if gcc does the right thing
++    set_ue_golomb(pb, i);
++}
++
++/**
++ * write unsigned golomb rice code (ffv1).
++ */
++static inline void set_ur_golomb(PutBitContext *pb, int i, int k, int limit,
++                                 int esc_len)
++{
++    int e;
++
++    av_assert2(i >= 0);
++
++    e = i >> k;
++    if (e < limit)
++        put_bits(pb, e + k + 1, (1 << k) + av_mod_uintp2(i, k));
++    else
++        put_bits(pb, limit + esc_len, i - limit + 1);
++}
++
++/**
++ * write unsigned golomb rice code (jpegls).
++ */
++static inline void set_ur_golomb_jpegls(PutBitContext *pb, int i, int k,
++                                        int limit, int esc_len)
++{
++    int e;
++
++    av_assert2(i >= 0);
++
++    e = (i >> k) + 1;
++    if (e < limit) {
++        while (e > 31) {
++            put_bits(pb, 31, 0);
++            e -= 31;
++        }
++        put_bits(pb, e, 1);
++        if (k)
++            put_sbits(pb, k, i);
++    } else {
++        while (limit > 31) {
++            put_bits(pb, 31, 0);
++            limit -= 31;
++        }
++        put_bits(pb, limit, 1);
++        put_bits(pb, esc_len, i - 1);
++    }
++}
++
++/**
++ * write signed golomb rice code (ffv1).
++ */
++static inline void set_sr_golomb(PutBitContext *pb, int i, int k, int limit,
++                                 int esc_len)
++{
++    int v;
++
++    v  = -2 * i - 1;
++    v ^= (v >> 31);
++
++    set_ur_golomb(pb, v, k, limit, esc_len);
++}
++
++/**
++ * write signed golomb rice code (flac).
++ */
++static inline void set_sr_golomb_flac(PutBitContext *pb, int i, int k,
++                                      int limit, int esc_len)
++{
++    int v;
++
++    v  = -2 * i - 1;
++    v ^= (v >> 31);
++
++    set_ur_golomb_jpegls(pb, v, k, limit, esc_len);
++}
++
++#endif /* AVCODEC_GOLOMB_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264.h
+new file mode 100644
+index 000000000..7a1fb6d68
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264.h
+@@ -0,0 +1,113 @@
++/*
++ * This file is part of FFmpeg.
++ *
++ * FFmpeg is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU Lesser General Public
++ * License as published by the Free Software Foundation; either
++ * version 2.1 of the License, or (at your option) any later version.
++ *
++ * FFmpeg is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * Lesser General Public License for more details.
++ *
++ * You should have received a copy of the GNU Lesser General Public
++ * License along with FFmpeg; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/**
++ * @file
++ * H.264 common definitions
++ */
++
++#ifndef AVCODEC_H264_H
++#define AVCODEC_H264_H
++
++#define QP_MAX_NUM (51 + 6*6)           // The maximum supported qp
++
++/*
++ * Table 7-1 – NAL unit type codes, syntax element categories, and NAL unit type classes in
++ * T-REC-H.264-201704
++ */
++enum {
++    H264_NAL_UNSPECIFIED     = 0,
++    H264_NAL_SLICE           = 1,
++    H264_NAL_DPA             = 2,
++    H264_NAL_DPB             = 3,
++    H264_NAL_DPC             = 4,
++    H264_NAL_IDR_SLICE       = 5,
++    H264_NAL_SEI             = 6,
++    H264_NAL_SPS             = 7,
++    H264_NAL_PPS             = 8,
++    H264_NAL_AUD             = 9,
++    H264_NAL_END_SEQUENCE    = 10,
++    H264_NAL_END_STREAM      = 11,
++    H264_NAL_FILLER_DATA     = 12,
++    H264_NAL_SPS_EXT         = 13,
++    H264_NAL_PREFIX          = 14,
++    H264_NAL_SUB_SPS         = 15,
++    H264_NAL_DPS             = 16,
++    H264_NAL_RESERVED17      = 17,
++    H264_NAL_RESERVED18      = 18,
++    H264_NAL_AUXILIARY_SLICE = 19,
++    H264_NAL_EXTEN_SLICE     = 20,
++    H264_NAL_DEPTH_EXTEN_SLICE = 21,
++    H264_NAL_RESERVED22      = 22,
++    H264_NAL_RESERVED23      = 23,
++    H264_NAL_UNSPECIFIED24   = 24,
++    H264_NAL_UNSPECIFIED25   = 25,
++    H264_NAL_UNSPECIFIED26   = 26,
++    H264_NAL_UNSPECIFIED27   = 27,
++    H264_NAL_UNSPECIFIED28   = 28,
++    H264_NAL_UNSPECIFIED29   = 29,
++    H264_NAL_UNSPECIFIED30   = 30,
++    H264_NAL_UNSPECIFIED31   = 31,
++};
++
++
++enum {
++    // 7.4.2.1.1: seq_parameter_set_id is in [0, 31].
++    H264_MAX_SPS_COUNT = 32,
++    // 7.4.2.2: pic_parameter_set_id is in [0, 255].
++    H264_MAX_PPS_COUNT = 256,
++
++    // A.3: MaxDpbFrames is bounded above by 16.
++    H264_MAX_DPB_FRAMES = 16,
++    // 7.4.2.1.1: max_num_ref_frames is in [0, MaxDpbFrames], and
++    // each reference frame can have two fields.
++    H264_MAX_REFS       = 2 * H264_MAX_DPB_FRAMES,
++
++    // 7.4.3.1: modification_of_pic_nums_idc is not equal to 3 at most
++    // num_ref_idx_lN_active_minus1 + 1 times (that is, once for each
++    // possible reference), then equal to 3 once.
++    H264_MAX_RPLM_COUNT = H264_MAX_REFS + 1,
++
++    // 7.4.3.3: in the worst case, we begin with a full short-term
++    // reference picture list.  Each picture in turn is moved to the
++    // long-term list (type 3) and then discarded from there (type 2).
++    // Then, we set the length of the long-term list (type 4), mark
++    // the current picture as long-term (type 6) and terminate the
++    // process (type 0).
++    H264_MAX_MMCO_COUNT = H264_MAX_REFS * 2 + 3,
++
++    // A.2.1, A.2.3: profiles supporting FMO constrain
++    // num_slice_groups_minus1 to be in [0, 7].
++    H264_MAX_SLICE_GROUPS = 8,
++
++    // E.2.2: cpb_cnt_minus1 is in [0, 31].
++    H264_MAX_CPB_CNT = 32,
++
++    // A.3: in table A-1 the highest level allows a MaxFS of 139264.
++    H264_MAX_MB_PIC_SIZE = 139264,
++    // A.3.1, A.3.2: PicWidthInMbs and PicHeightInMbs are constrained
++    // to be not greater than sqrt(MaxFS * 8).  Hence height/width are
++    // bounded above by sqrt(139264 * 8) = 1055.5 macroblocks.
++    H264_MAX_MB_WIDTH    = 1055,
++    H264_MAX_MB_HEIGHT   = 1055,
++    H264_MAX_WIDTH       = H264_MAX_MB_WIDTH  * 16,
++    H264_MAX_HEIGHT      = H264_MAX_MB_HEIGHT * 16,
++};
++
++
++#endif /* AVCODEC_H264_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h2645_parse.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h2645_parse.h
+new file mode 100644
+index 000000000..6f817b803
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h2645_parse.h
+@@ -0,0 +1,93 @@
++#ifndef AVCODEC_H2645_PARSE_H
++#define AVCODEC_H2645_PARSE_H
++
++
++#include "avcodec.h"
++#include "get_bits.h"
++
++#define MAX_MBPAIR_SIZE (256*1024) // a tighter bound could be calculated if someone cares about a few bytes
++#define MAX_NALS_PER_PACKET	(8)
++
++typedef struct H2645NAL {
++    int size;
++    const uint8_t *data;
++
++    /**
++     * Size, in bits, of just the data, excluding the stop bit and any trailing
++     * padding. I.e. what HEVC calls SODB.
++     */
++    int size_bits;
++
++    int raw_size;
++    const uint8_t *raw_data;
++
++    GetBitContext gb;
++
++    /**
++     * NAL unit type
++     */
++    int type;
++
++    /**
++     * HEVC only, nuh_temporal_id_plus_1 - 1
++     */
++    int temporal_id;
++
++    int skipped_bytes;
++    int skipped_bytes_pos_size;
++    int *skipped_bytes_pos;
++    /**
++     * H.264 only, nal_ref_idc
++     */
++    int ref_idc;
++} H2645NAL;
++
++/* an input packet split into unescaped NAL units */
++typedef struct H2645Packet {
++    H2645NAL *nals;
++    int nb_nals;
++    int nals_allocated;
++} H2645Packet;
++
++/**
++ * Extract the raw (unescaped) bitstream.
++ */
++int ff_h2645_extract_rbsp(const uint8_t *src, int length,
++                          H2645NAL *nal, int small_padding);
++
++/**
++ * Split an input packet into NAL units.
++ */
++int ff_h2645_packet_split(H2645Packet *pkt, const uint8_t *buf, int length,
++                          void *logctx, int is_nalff, int nal_length_size,
++                          int small_padding);
++
++/**
++ * Free all the allocated memory in the packet.
++ */
++void ff_h2645_packet_uninit(H2645Packet *pkt);
++
++static inline int get_nalsize(int nal_length_size, const uint8_t *buf,
++                              int buf_size, int *buf_index, void *logctx)
++{
++    int i, nalsize = 0;
++
++    if (*buf_index >= buf_size - nal_length_size) {
++        // the end of the buffer is reached, refill it
++        return AVERROR(EAGAIN);
++    }
++
++    /*�设nal_length_size 为4 , 就是将buf里�的内容转��实际的大�????
++     *那么buffer里�的内容是什么呢？
++     * */
++    for (i = 0; i < nal_length_size; i++)
++        nalsize = ((unsigned)nalsize << 8) | buf[(*buf_index)++];
++    if (nalsize <= 0 || nalsize > buf_size - *buf_index) {
++        av_log(logctx, AV_LOG_ERROR,
++               "Invalid NAL unit size (%d > %d).\n", nalsize, buf_size - *buf_index);
++        return AVERROR_INVALIDDATA;
++    }
++    return nalsize;
++}
++
++#endif /* AVCODEC_H2645_PARSE_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264_parse.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264_parse.h
+new file mode 100644
+index 000000000..ec49093b1
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264_parse.h
+@@ -0,0 +1,70 @@
++#ifndef AVCODEC_H264_PARSE_H
++#define AVCODEC_H264_PARSE_H
++
++#include "get_bits.h"
++#include "h264_ps.h"
++
++typedef struct H264PredWeightTable {
++    int use_weight;
++    int use_weight_chroma;
++    int luma_log2_weight_denom;
++    int chroma_log2_weight_denom;
++    int luma_weight_flag[2];    ///< 7.4.3.2 luma_weight_lX_flag
++    int chroma_weight_flag[2];  ///< 7.4.3.2 chroma_weight_lX_flag
++    // The following 2 can be changed to int8_t but that causes a 10 CPU cycles speed loss
++    int luma_weight[48][2][2];
++    int chroma_weight[48][2][2][2];
++    int implicit_weight[48][48][2];
++} H264PredWeightTable;
++
++typedef struct H264POCContext {
++    int poc_lsb;
++    int poc_msb;
++    int delta_poc_bottom;
++    int delta_poc[2];
++    int frame_num;
++    int prev_poc_msb;           ///< poc_msb of the last reference pic for POC type 0
++    int prev_poc_lsb;           ///< poc_lsb of the last reference pic for POC type 0
++    int frame_num_offset;       ///< for POC type 2
++    int prev_frame_num_offset;  ///< for POC type 2
++    int prev_frame_num;         ///< frame_num of the last pic for POC type 1/2
++} H264POCContext;
++
++int ff_h264_pred_weight_table(GetBitContext *gb, const SPS *sps,
++                              const int *ref_count, int slice_type_nos,
++                              H264PredWeightTable *pwt,
++                              int picture_structure, void *logctx);
++
++/**
++ * Check if the top & left blocks are available if needed & change the
++ * dc mode so it only uses the available blocks.
++ */
++int ff_h264_check_intra4x4_pred_mode(int8_t *pred_mode_cache, void *logctx,
++                                     int top_samples_available, int left_samples_available);
++
++/**
++ * Check if the top & left blocks are available if needed & change the
++ * dc mode so it only uses the available blocks.
++ */
++int ff_h264_check_intra_pred_mode(void *logctx, int top_samples_available,
++                                  int left_samples_available,
++                                  int mode, int is_chroma);
++
++int ff_h264_parse_ref_count(int *plist_count, int ref_count[2],
++                            GetBitContext *gb, const PPS *pps,
++                            int slice_type_nos, int picture_structure, void *logctx);
++
++int ff_h264_init_poc(int pic_field_poc[2], int *pic_poc,
++                     const SPS *sps, H264POCContext *poc,
++                     int picture_structure, int nal_ref_idc);
++
++int ff_h264_decode_extradata(const uint8_t *data, int size, H264ParamSets *ps,
++                             int *is_avc, int *nal_length_size,
++                             int err_recognition, void *logctx);
++
++/**
++ * compute profile from sps
++ */
++int ff_h264_get_profile(const SPS *sps);
++
++#endif /* AVCODEC_H264_PARSE_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264_ps.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264_ps.h
+new file mode 100644
+index 000000000..61ce1d584
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264_ps.h
+@@ -0,0 +1,184 @@
++#ifndef AVCODEC_H264_PS_H
++#define AVCODEC_H264_PS_H
++
++//#include "libavutil/buffer.h"
++//#include "libavutil/pixfmt.h"
++//#include "libavutil/rational.h"
++
++#include "avcodec.h"
++#include "get_bits.h"
++#include "h264.h"
++
++#if 0
++#define MAX_SPS_COUNT          32
++#define MAX_PPS_COUNT         256
++#endif
++
++#define MAX_SPS_COUNT          3
++#define MAX_PPS_COUNT         4
++#define MAX_LOG2_MAX_FRAME_NUM    (12 + 4)
++
++typedef struct AVRational{
++    int num; ///< Numerator
++    int den; ///< Denominator
++} AVRational;
++
++static const AVRational ff_h264_pixel_aspect[17] = {
++    {   0,  1 },
++    {   1,  1 },
++    {  12, 11 },
++    {  10, 11 },
++    {  16, 11 },
++    {  40, 33 },
++    {  24, 11 },
++    {  20, 11 },
++    {  32, 11 },
++    {  80, 33 },
++    {  18, 11 },
++    {  15, 11 },
++    {  64, 33 },
++    { 160, 99 },
++    {   4,  3 },
++    {   3,  2 },
++    {   2,  1 },
++};
++/**
++ * Sequence parameter set
++ */
++typedef struct SPS {
++    unsigned int sps_id;
++    int profile_idc;
++    int level_idc;
++    int chroma_format_idc;
++    int transform_bypass;              ///< qpprime_y_zero_transform_bypass_flag
++    int log2_max_frame_num;            ///< log2_max_frame_num_minus4 + 4
++    int poc_type;                      ///< pic_order_cnt_type
++    int log2_max_poc_lsb;              ///< log2_max_pic_order_cnt_lsb_minus4
++    int delta_pic_order_always_zero_flag;
++    int offset_for_non_ref_pic;
++    int offset_for_top_to_bottom_field;
++    int poc_cycle_length;              ///< num_ref_frames_in_pic_order_cnt_cycle
++    int ref_frame_count;               ///< num_ref_frames
++    int gaps_in_frame_num_allowed_flag;
++    int mb_width;                      ///< pic_width_in_mbs_minus1 + 1
++    ///< (pic_height_in_map_units_minus1 + 1) * (2 - frame_mbs_only_flag)
++    int mb_height;
++    int frame_mbs_only_flag;
++    int mb_aff;                        ///< mb_adaptive_frame_field_flag
++    int direct_8x8_inference_flag;
++    int crop;                          ///< frame_cropping_flag
++
++    /* those 4 are already in luma samples */
++    unsigned int crop_left;            ///< frame_cropping_rect_left_offset
++    unsigned int crop_right;           ///< frame_cropping_rect_right_offset
++    unsigned int crop_top;             ///< frame_cropping_rect_top_offset
++    unsigned int crop_bottom;          ///< frame_cropping_rect_bottom_offset
++    int vui_parameters_present_flag;
++    AVRational sar;
++    int video_signal_type_present_flag;
++    int full_range;
++    int colour_description_present_flag;
++#if 0
++    enum AVColorPrimaries color_primaries;
++    enum AVColorTransferCharacteristic color_trc;
++    enum AVColorSpace colorspace;
++#endif
++    int timing_info_present_flag;
++    uint32_t num_units_in_tick;
++    uint32_t time_scale;
++    int fixed_frame_rate_flag;
++    //short offset_for_ref_frame[256]; // FIXME dyn aloc?
++    short offset_for_ref_frame[128]; // FIXME dyn aloc?
++    int bitstream_restriction_flag;
++    int num_reorder_frames;
++    int scaling_matrix_present;
++    uint8_t scaling_matrix4[6][16];
++    uint8_t scaling_matrix8[6][64];
++    int nal_hrd_parameters_present_flag;
++    int vcl_hrd_parameters_present_flag;
++    int pic_struct_present_flag;
++    int time_offset_length;
++    int cpb_cnt;                          ///< See H.264 E.1.2
++    int initial_cpb_removal_delay_length; ///< initial_cpb_removal_delay_length_minus1 + 1
++    int cpb_removal_delay_length;         ///< cpb_removal_delay_length_minus1 + 1
++    int dpb_output_delay_length;          ///< dpb_output_delay_length_minus1 + 1
++    int bit_depth_luma;                   ///< bit_depth_luma_minus8 + 8
++    int bit_depth_chroma;                 ///< bit_depth_chroma_minus8 + 8
++    int residual_color_transform_flag;    ///< residual_colour_transform_flag
++    int constraint_set_flags;             ///< constraint_set[0-3]_flag
++#if 0
++    uint8_t data[4096];
++    size_t data_size;
++#endif
++} SPS;
++
++/**
++ * Picture parameter set
++ */
++typedef struct PPS {
++    unsigned int sps_id;
++    int cabac;                  ///< entropy_coding_mode_flag
++    int pic_order_present;      ///< pic_order_present_flag
++    int slice_group_count;      ///< num_slice_groups_minus1 + 1
++    int mb_slice_group_map_type;
++    unsigned int ref_count[2];  ///< num_ref_idx_l0/1_active_minus1 + 1
++    int weighted_pred;          ///< weighted_pred_flag
++    int weighted_bipred_idc;
++    int init_qp;                ///< pic_init_qp_minus26 + 26
++    int init_qs;                ///< pic_init_qs_minus26 + 26
++    int chroma_qp_index_offset[2];
++    int deblocking_filter_parameters_present; ///< deblocking_filter_parameters_present_flag
++    int constrained_intra_pred;     ///< constrained_intra_pred_flag
++    int redundant_pic_cnt_present;  ///< redundant_pic_cnt_present_flag
++    int transform_8x8_mode;         ///< transform_8x8_mode_flag
++    uint8_t scaling_matrix4[6][16];
++    uint8_t scaling_matrix8[6][64];
++    uint8_t chroma_qp_table[2][QP_MAX_NUM+1];  ///< pre-scaled (with chroma_qp_index_offset) version of qp_table
++    int chroma_qp_diff;
++#if 0
++    uint8_t data[4096];
++    size_t data_size;
++#endif
++
++#if 0
++    uint32_t dequant4_buffer[6][QP_MAX_NUM + 1][16];
++    uint32_t dequant8_buffer[6][QP_MAX_NUM + 1][64];
++    uint32_t(*dequant4_coeff[6])[16];
++    uint32_t(*dequant8_coeff[6])[64];
++#endif
++} PPS;
++
++typedef struct H264ParamSets {
++#if 0
++    AVBufferRef *sps_list[MAX_SPS_COUNT];
++    AVBufferRef *pps_list[MAX_PPS_COUNT];
++
++    AVBufferRef *pps_ref;
++    AVBufferRef *sps_ref;
++#endif
++
++    SPS sps_list[MAX_SPS_COUNT];
++    PPS pps_list[MAX_PPS_COUNT];
++    /* currently active parameters sets */
++    const PPS *pps;
++    const SPS *sps;
++} H264ParamSets;
++
++/**
++ * Decode SPS
++ */
++int ff_h264_decode_seq_parameter_set(GetBitContext *gb, AVCodecContext *avctx,
++                                     H264ParamSets *ps, int ignore_truncation);
++
++/**
++ * Decode PPS
++ */
++int ff_h264_decode_picture_parameter_set(GetBitContext *gb, AVCodecContext *avctx,
++                                         H264ParamSets *ps, int bit_length);
++
++/**
++ * Uninit H264 param sets structure.
++ */
++void ff_h264_ps_uninit(H264ParamSets *ps);
++
++#endif /* AVCODEC_H264_PS_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264_sei.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264_sei.h
+new file mode 100644
+index 000000000..ed81d46e3
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264_sei.h
+@@ -0,0 +1,189 @@
++#ifndef AVCODEC_H264_SEI_H
++#define AVCODEC_H264_SEI_H
++
++#include "get_bits.h"
++
++/**
++ * SEI message types
++ */
++typedef enum {
++    H264_SEI_TYPE_BUFFERING_PERIOD       = 0,   ///< buffering period (H.264, D.1.1)
++    H264_SEI_TYPE_PIC_TIMING             = 1,   ///< picture timing
++    H264_SEI_TYPE_PAN_SCAN_RECT          = 2,   ///< pan-scan rectangle
++    H264_SEI_TYPE_FILLER_PAYLOAD         = 3,   ///< filler data
++    H264_SEI_TYPE_USER_DATA_REGISTERED   = 4,   ///< registered user data as specified by Rec. ITU-T T.35
++    H264_SEI_TYPE_USER_DATA_UNREGISTERED = 5,   ///< unregistered user data
++    H264_SEI_TYPE_RECOVERY_POINT         = 6,   ///< recovery point (frame # to decoder sync)
++    H264_SEI_TYPE_FRAME_PACKING          = 45,  ///< frame packing arrangement
++    H264_SEI_TYPE_DISPLAY_ORIENTATION    = 47,  ///< display orientation
++    H264_SEI_TYPE_GREEN_METADATA         = 56,  ///< GreenMPEG information
++    H264_SEI_TYPE_MASTERING_DISPLAY_COLOUR_VOLUME = 137,  ///< mastering display properties
++    H264_SEI_TYPE_ALTERNATIVE_TRANSFER   = 147, ///< alternative transfer
++} H264_SEI_Type;
++
++/**
++ * pic_struct in picture timing SEI message
++ */
++typedef enum {
++    H264_SEI_PIC_STRUCT_FRAME             = 0, ///<  0: %frame
++    H264_SEI_PIC_STRUCT_TOP_FIELD         = 1, ///<  1: top field
++    H264_SEI_PIC_STRUCT_BOTTOM_FIELD      = 2, ///<  2: bottom field
++    H264_SEI_PIC_STRUCT_TOP_BOTTOM        = 3, ///<  3: top field, bottom field, in that order
++    H264_SEI_PIC_STRUCT_BOTTOM_TOP        = 4, ///<  4: bottom field, top field, in that order
++    H264_SEI_PIC_STRUCT_TOP_BOTTOM_TOP    = 5, ///<  5: top field, bottom field, top field repeated, in that order
++    H264_SEI_PIC_STRUCT_BOTTOM_TOP_BOTTOM = 6, ///<  6: bottom field, top field, bottom field repeated, in that order
++    H264_SEI_PIC_STRUCT_FRAME_DOUBLING    = 7, ///<  7: %frame doubling
++    H264_SEI_PIC_STRUCT_FRAME_TRIPLING    = 8  ///<  8: %frame tripling
++} H264_SEI_PicStructType;
++
++/**
++ * frame_packing_arrangement types
++ */
++typedef enum {
++    H264_SEI_FPA_TYPE_CHECKERBOARD        = 0,
++    H264_SEI_FPA_TYPE_INTERLEAVE_COLUMN   = 1,
++    H264_SEI_FPA_TYPE_INTERLEAVE_ROW      = 2,
++    H264_SEI_FPA_TYPE_SIDE_BY_SIDE        = 3,
++    H264_SEI_FPA_TYPE_TOP_BOTTOM          = 4,
++    H264_SEI_FPA_TYPE_INTERLEAVE_TEMPORAL = 5,
++    H264_SEI_FPA_TYPE_2D                  = 6,
++} H264_SEI_FpaType;
++
++typedef struct H264SEITimeCode {
++    /* When not continuously receiving full timecodes, we have to reference
++       the previous timecode received */
++    int full;
++    int frame;
++    int seconds;
++    int minutes;
++    int hours;
++    int dropframe;
++} H264SEITimeCode;
++
++typedef struct H264SEIPictureTiming {
++    int present;
++    H264_SEI_PicStructType pic_struct;
++
++    /**
++     * Bit set of clock types for fields/frames in picture timing SEI message.
++     * For each found ct_type, appropriate bit is set (e.g., bit 1 for
++     * interlaced).
++     */
++    int ct_type;
++
++    /**
++     * dpb_output_delay in picture timing SEI message, see H.264 C.2.2
++     */
++    int dpb_output_delay;
++
++    /**
++     * cpb_removal_delay in picture timing SEI message, see H.264 C.1.2
++     */
++    int cpb_removal_delay;
++
++    /**
++     * Maximum three timecodes in a pic_timing SEI.
++     */
++    H264SEITimeCode timecode[3];
++
++    /**
++     * Number of timecode in use
++     */
++    int timecode_cnt;
++} H264SEIPictureTiming;
++
++typedef struct H264SEIAFD {
++    int present;
++    uint8_t active_format_description;
++} H264SEIAFD;
++
++typedef struct H264SEIA53Caption {
++#if 0
++    AVBufferRef *buf_ref;
++#endif
++} H264SEIA53Caption;
++
++typedef struct H264SEIUnregistered {
++    int x264_build;
++} H264SEIUnregistered;
++
++typedef struct H264SEIRecoveryPoint {
++    /**
++     * recovery_frame_cnt
++     *
++     * Set to -1 if no recovery point SEI message found or to number of frames
++     * before playback synchronizes. Frames having recovery point are key
++     * frames.
++     */
++    int recovery_frame_cnt;
++} H264SEIRecoveryPoint;
++
++typedef struct H264SEIBufferingPeriod {
++    int present;   ///< Buffering period SEI flag
++    int initial_cpb_removal_delay[32];  ///< Initial timestamps for CPBs
++} H264SEIBufferingPeriod;
++
++typedef struct H264SEIFramePacking {
++    int present;
++    int arrangement_id;
++    int arrangement_cancel_flag;  ///< is previous arrangement canceled, -1 if never received
++    H264_SEI_FpaType arrangement_type;
++    int arrangement_repetition_period;
++    int content_interpretation_type;
++    int quincunx_sampling_flag;
++    int current_frame_is_frame0_flag;
++} H264SEIFramePacking;
++
++typedef struct H264SEIDisplayOrientation {
++    int present;
++    int anticlockwise_rotation;
++    int hflip, vflip;
++} H264SEIDisplayOrientation;
++
++typedef struct H264SEIGreenMetaData {
++    uint8_t green_metadata_type;
++    uint8_t period_type;
++    uint16_t num_seconds;
++    uint16_t num_pictures;
++    uint8_t percent_non_zero_macroblocks;
++    uint8_t percent_intra_coded_macroblocks;
++    uint8_t percent_six_tap_filtering;
++    uint8_t percent_alpha_point_deblocking_instance;
++    uint8_t xsd_metric_type;
++    uint16_t xsd_metric_value;
++} H264SEIGreenMetaData;
++
++typedef struct H264SEIAlternativeTransfer {
++    int present;
++    int preferred_transfer_characteristics;
++} H264SEIAlternativeTransfer;
++
++typedef struct H264SEIContext {
++    H264SEIPictureTiming picture_timing;
++    H264SEIAFD afd;
++    H264SEIA53Caption a53_caption;
++    H264SEIUnregistered unregistered;
++    H264SEIRecoveryPoint recovery_point;
++    H264SEIBufferingPeriod buffering_period;
++    H264SEIFramePacking frame_packing;
++    H264SEIDisplayOrientation display_orientation;
++    H264SEIGreenMetaData green_metadata;
++    H264SEIAlternativeTransfer alternative_transfer;
++} H264SEIContext;
++
++struct H264ParamSets;
++
++int ff_h264_sei_decode(H264SEIContext *h, GetBitContext *gb,
++                       const struct H264ParamSets *ps, void *logctx);
++
++/**
++ * Reset SEI values at the beginning of the frame.
++ */
++void ff_h264_sei_uninit(H264SEIContext *h);
++
++/**
++ * Get stereo_mode string from the h264 frame_packing_arrangement
++ */
++const char *ff_h264_sei_stereo_mode(const H264SEIFramePacking *h);
++
++#endif /* AVCODEC_H264_SEI_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264data.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264data.h
+new file mode 100644
+index 000000000..fdf6c4292
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264data.h
+@@ -0,0 +1,41 @@
++#ifndef AVCODEC_H264DATA_H
++#define AVCODEC_H264DATA_H
++
++
++#include "h264dec.h"
++
++extern const uint8_t ff_h264_golomb_to_pict_type[5];
++extern const uint8_t ff_h264_golomb_to_intra4x4_cbp[48];
++extern const uint8_t ff_h264_golomb_to_inter_cbp[48];
++
++extern const uint8_t ff_h264_chroma_dc_scan[4];
++extern const uint8_t ff_h264_chroma422_dc_scan[8];
++
++typedef struct IMbInfo {
++    uint16_t type;
++    uint8_t pred_mode;
++    uint8_t cbp;
++} IMbInfo;
++
++extern const IMbInfo ff_h264_i_mb_type_info[26];
++
++typedef struct PMbInfo {
++    uint16_t type;
++    uint8_t partition_count;
++} PMbInfo;
++
++extern const PMbInfo ff_h264_p_mb_type_info[5];
++extern const PMbInfo ff_h264_p_sub_mb_type_info[4];
++extern const PMbInfo ff_h264_b_mb_type_info[23];
++extern const PMbInfo ff_h264_b_sub_mb_type_info[13];
++
++
++extern const uint8_t ff_h264_dequant4_coeff_init[6][3];
++extern const uint8_t ff_h264_dequant8_coeff_init_scan[16];
++extern const uint8_t ff_h264_dequant8_coeff_init[6][6];
++extern const uint8_t ff_h264_quant_rem6[QP_MAX_NUM + 1];
++extern const uint8_t ff_h264_quant_div6[QP_MAX_NUM + 1];
++
++extern const uint8_t ff_h264_chroma_qp[7][QP_MAX_NUM + 1];
++
++#endif /* AVCODEC_H264DATA_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264dec.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264dec.h
+new file mode 100644
+index 000000000..1ceb50128
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/h264dec.h
+@@ -0,0 +1,622 @@
++#ifndef AVCODEC_H264DEC_H
++#define AVCODEC_H264DEC_H
++
++//#include "libavutil/intreadwrite.h"
++#include "list.h"
++#include "api/jzm_h264_dec.h"
++
++#include "buffer.h"
++#include "vpu_ops.h"
++
++#include "h264_parse.h"
++#include "h264_ps.h"
++#include "h264_sei.h"
++#include "h2645_parse.h"
++#include "mpegutils.h"
++
++//#define H264_MAX_PICTURE_COUNT 36
++#define H264_MAX_PICTURE_COUNT 16
++
++#define MAX_MMCO_COUNT         66
++
++#define MAX_DELAYED_PIC_COUNT  8
++
++/* Compiling in interlaced support reduces the speed
++ * of progressive decoding by about 2%. */
++#define ALLOW_INTERLACE
++
++#define FMO 0
++
++/**
++ * The maximum number of slices supported by the decoder.
++ * must be a power of 2
++ */
++#define MAX_SLICES 32
++
++#ifdef ALLOW_INTERLACE
++#define MB_MBAFF(h)    (h)->mb_mbaff
++#define MB_FIELD(sl)  (sl)->mb_field_decoding_flag
++#define FRAME_MBAFF(h) (h)->mb_aff_frame
++#define FIELD_PICTURE(h) ((h)->picture_structure != PICT_FRAME)
++#define LEFT_MBS 2
++#define LTOP     0
++#define LBOT     1
++#define LEFT(i)  (i)
++#else
++#define MB_MBAFF(h)      0
++#define MB_FIELD(sl)     0
++#define FRAME_MBAFF(h)   0
++#define FIELD_PICTURE(h) 0
++#undef  IS_INTERLACED
++#define IS_INTERLACED(mb_type) 0
++#define LEFT_MBS 1
++#define LTOP     0
++#define LBOT     0
++#define LEFT(i)  0
++#endif
++#define FIELD_OR_MBAFF_PICTURE(h) (FRAME_MBAFF(h) || FIELD_PICTURE(h))
++
++#ifndef CABAC
++#define CABAC(h) (h)->ps.pps->cabac
++#endif
++
++#define CHROMA(h)    ((h)->ps.sps->chroma_format_idc)
++#define CHROMA422(h) ((h)->ps.sps->chroma_format_idc == 2)
++#define CHROMA444(h) ((h)->ps.sps->chroma_format_idc == 3)
++
++#define MB_TYPE_REF0       MB_TYPE_ACPRED // dirty but it fits in 16 bit
++#define MB_TYPE_8x8DCT     0x01000000
++#define IS_REF0(a)         ((a) & MB_TYPE_REF0)
++#define IS_8x8DCT(a)       ((a) & MB_TYPE_8x8DCT)
++
++#define FFALIGN(x, a) (((x)+(a)-1)&~((a)-1))
++/**
++ * Memory management control operation opcode.
++ */
++typedef enum MMCOOpcode {
++    MMCO_END = 0,
++    MMCO_SHORT2UNUSED,
++    MMCO_LONG2UNUSED,
++    MMCO_SHORT2LONG,
++    MMCO_SET_MAX_LONG,
++    MMCO_RESET,
++    MMCO_LONG,
++} MMCOOpcode;
++
++/**
++ * Memory management control operation.
++ */
++typedef struct MMCO {
++    MMCOOpcode opcode;
++    int short_pic_num;  ///< pic_num without wrapping (pic_num & max_pic_num)
++    int long_arg;       ///< index, pic_num, or num long refs depending on opcode
++} MMCO;
++
++typedef struct H264Picture {
++    AVFrame *f;
++    //ThreadFrame tf;
++
++    AVBuffer *frm_info_ctrl;
++    AVBuffer *frm_info_mv;
++
++    AVBuffer *dec_result_y;
++    AVBuffer *dec_result_uv;
++
++    int field_poc[2];       ///< top/bottom POC
++    int poc;                ///< frame POC
++    int frame_num;          ///< frame_num (raw frame_num from slice header)
++    int mmco_reset;         /**< MMCO_RESET set this 1. Reordering code must
++                                 not mix pictures before and after MMCO_RESET. */
++    int pic_id;             /**< pic_num (short -> no wrap version of pic_num,
++                                 pic_num & max_pic_num; long -> long_pic_num) */
++    int long_ref;           ///< 1->long term reference 0->short term reference
++    int ref_poc[2][2][32];  ///< POCs of the frames/fields used as reference (FIXME need per slice)
++    int ref_count[2][2];    ///< number of entries in ref_poc         (FIXME need per slice)
++    int mbaff;              ///< 1 -> MBAFF frame 0-> not MBAFF
++    int field_picture;      ///< whether or not picture was encoded in separate fields
++
++    int reference;
++    int recovered;          ///< picture at IDR or recovery point + recovery count
++    int invalid_gap;
++    int sei_recovery_frame_cnt;
++
++} H264Picture;
++
++typedef struct H264Ref {
++    uint8_t *data[3];
++    int linesize[3];
++
++    int reference;
++    int poc;
++    int pic_id;
++
++    H264Picture *parent;
++} H264Ref;
++
++typedef struct H264SliceContext {
++    struct H264Context *h264;
++    GetBitContext gb;
++    //ERContext er;
++
++    int slice_num;
++    int slice_type;
++    int slice_type_nos;         ///< S free slice type (SI/SP are remapped to I/P)
++    int slice_type_fixed;
++
++    int qscale;
++    int chroma_qp[2];   // QPc
++    int qp_thresh;      ///< QP threshold to skip loopfilter
++    int last_qscale_diff;
++
++    // deblock
++    int deblocking_filter;          ///< disable_deblocking_filter_idc with 1 <-> 0
++    int slice_alpha_c0_offset;
++    int slice_beta_offset;
++
++    H264PredWeightTable pwt;
++
++    int prev_mb_skipped;
++    int next_mb_skipped;
++
++    int chroma_pred_mode;
++    int intra16x16_pred_mode;
++
++    ptrdiff_t linesize, uvlinesize;
++    ptrdiff_t mb_linesize;  ///< may be equal to s->linesize or s->linesize * 2, for mbaff
++    ptrdiff_t mb_uvlinesize;
++
++    int mb_x, mb_y;
++    int mb_xy;
++    int resync_mb_x;
++    int resync_mb_y;
++    unsigned int first_mb_addr;
++    // index of the first MB of the next slice
++    int next_slice_idx;
++    int mb_skip_run;
++    int is_complex;
++
++    int picture_structure;
++    int mb_field_decoding_flag;
++    int mb_mbaff;               ///< mb_aff_frame && mb_field_decoding_flag
++
++    int redundant_pic_count;
++
++    /**
++     * number of neighbors (top and/or left) that used 8x8 dct
++     */
++    int neighbor_transform_size;
++
++    int direct_spatial_mv_pred;
++    int col_parity;
++    int col_fieldoff;
++
++    int cbp;
++    int top_cbp;
++    int left_cbp;
++
++    int dist_scale_factor[32];
++    int dist_scale_factor_field[2][32];
++    int map_col_to_list0[2][16 + 32];
++    int map_col_to_list0_field[2][2][16 + 32];
++
++    /**
++     * num_ref_idx_l0/1_active_minus1 + 1
++     */
++    unsigned int ref_count[2];          ///< counts frames or fields, depending on current mb mode
++    unsigned int list_count;
++    H264Ref ref_list[2][48];        /**< 0..15: frame refs, 16..47: mbaff field refs.
++                                         *   Reordered version of default_ref_list
++                                         *   according to picture reordering in slice header */
++    struct {
++        uint8_t op;
++        uint32_t val;
++    } ref_modifications[2][32];
++    int nb_ref_modifications[2];
++
++    unsigned int pps_id;
++
++    const uint8_t *intra_pcm_ptr;
++    int16_t *dc_val_base;
++
++    uint8_t *bipred_scratchpad;
++    uint8_t *edge_emu_buffer;
++    uint8_t (*top_borders[2])[(16 * 3) * 2];
++    int bipred_scratchpad_allocated;
++    int edge_emu_buffer_allocated;
++    int top_borders_allocated[2];
++
++    int cabac_init_idc;
++
++    MMCO mmco[MAX_MMCO_COUNT];
++    int  nb_mmco;
++    int explicit_ref_marking;
++
++    int frame_num;
++    int poc_lsb;
++    int delta_poc_bottom;
++    int delta_poc[2];
++    int curr_pic_num;
++    int max_pic_num;
++} H264SliceContext;
++
++
++#define SOC_TYPE_M200		1
++#define SOC_TYPE_X2000		2
++
++#define VPU_FORMAT_TILE420	1
++#define VPU_FORMAT_NV12		2
++#define VPU_FORMAT_NV21		3
++/**
++ * H264Context
++ */
++typedef struct H264Context {
++    AVCodecContext *avctx;
++
++    unsigned int api_version;
++    unsigned int format;	/* output format.*/
++    jzm_h264 *st_h264;	/* 硬件解�器�柄.*/
++
++#define DMA_DESC_SIZE	(128*1024)
++    AVBuffer *dma_desc;
++
++    devmem_ctx_t devmem_ctx;	/*设备内存分�器�柄.*/
++    vpu_ctx_t vpu_ctx;		/*vpu硬件控制�柄*/
++
++    H264Picture DPB[H264_MAX_PICTURE_COUNT];
++    H264Picture *cur_pic_ptr;
++    //H264Picture cur_pic;
++    //H264Picture last_pic_for_ec;
++
++    /*
++     * 解��次调用一次output_frame，将图象放入output_picture_list;
++     * 未�会将output_picture_list,��output_frame_list.�用�存放解��的帧信�.
++     *
++     * */
++    struct list_head done_list;	/* 完�的frame列表.*/
++    struct list_head queued_list;	/*�以用于解�的frame_buffer list.*/
++
++    H264SliceContext *slice_ctx;
++    int            nb_slice_ctx;
++    int            nb_slice_ctx_queued;
++
++    H2645Packet pkt;
++
++    int pixel_shift;    ///< 0 for 8-bit H.264, 1 for high-bit-depth H.264
++
++    /* coded dimensions -- 16 * mb w/h */
++    int width, height;
++    int chroma_x_shift, chroma_y_shift;
++
++    int droppable;
++    int coded_picture_number;
++
++    int context_initialized;
++    int flags;
++    int workaround_bugs;
++    int x264_build;
++    /* Set when slice threading is used and at least one slice uses deblocking
++     * mode 1 (i.e. across slice boundaries). Then we disable the loop filter
++     * during normal MB decoding and execute it serially at the end.
++     */
++    int postpone_filter;
++
++    /*
++     * Set to 1 when the current picture is IDR, 0 otherwise.
++     */
++    int picture_idr;
++
++    int crop_left;
++    int crop_right;
++    int crop_top;
++    int crop_bottom;
++
++
++#define LIST_NOT_USED -1 // FIXME rename?
++#define PART_NOT_AVAILABLE -2
++
++    int b_stride;       // FIXME use s->b4_stride
++    uint16_t *slice_table;      ///< slice_table_base + 2*mb_stride + 1
++
++    // interlacing specific flags
++    int mb_aff_frame;
++    int picture_structure;
++    int first_field;
++
++    uint8_t *list_counts;               ///< Array of list_count per MB specifying the slice type
++
++    int mb_y;
++    int mb_height, mb_width;
++    int mb_stride;
++    int mb_num;
++
++    // =============================================================
++    // Things below are not used in the MB or more inner code
++
++    int nal_ref_idc;
++    int nal_unit_type;
++
++    int has_slice;          ///< slice NAL is found in the packet, set by decode_nal_units, its state does not need to be preserved outside h264_decode_frame()
++
++    /**
++     * Used to parse AVC variant of H.264
++     */
++    int is_avc;           ///< this flag is != 0 if codec is avc1
++    int nal_length_size;  ///< Number of bytes used for nal length (1, 2 or 4)
++
++    int bit_depth_luma;         ///< luma bit depth from sps to detect changes
++    int chroma_format_idc;      ///< chroma format from sps to detect changes
++
++    H264ParamSets ps;
++
++   // uint16_t *slice_table_base;
++
++    H264POCContext poc;
++
++    H264Ref default_ref[2];
++    H264Picture *short_ref[32];
++    H264Picture *long_ref[32];
++    H264Picture *delayed_pic[MAX_DELAYED_PIC_COUNT + 2]; // FIXME size?
++    int last_pocs[MAX_DELAYED_PIC_COUNT];
++    H264Picture *next_output_pic;
++    int next_outputed_poc;
++
++    /**
++     * memory management control operations buffer.
++     */
++    MMCO mmco[MAX_MMCO_COUNT];
++    int  nb_mmco;
++    int mmco_reset;
++    int explicit_ref_marking;
++
++    int long_ref_count;     ///< number of actual long term references
++    int short_ref_count;    ///< number of actual short term references
++
++    /**
++     * @name Members for slice based multithreading
++     * @{
++     */
++    /**
++     * current slice number, used to initialize slice_num of each thread/context
++     */
++    int current_slice;
++
++    /** @} */
++
++    /**
++     * Complement sei_pic_struct
++     * SEI_PIC_STRUCT_TOP_BOTTOM and SEI_PIC_STRUCT_BOTTOM_TOP indicate interlaced frames.
++     * However, soft telecined frames may have these values.
++     * This is used in an attempt to flag soft telecine progressive.
++     */
++    int prev_interlaced_frame;
++
++    /**
++     * Are the SEI recovery points looking valid.
++     */
++    int valid_recovery_point;
++
++    /**
++     * recovery_frame is the frame_num at which the next frame should
++     * be fully constructed.
++     *
++     * Set to -1 when not expecting a recovery point.
++     */
++    int recovery_frame;
++
++/**
++ * We have seen an IDR, so all the following frames in coded order are correctly
++ * decodable.
++ */
++#define FRAME_RECOVERED_IDR  (1 << 0)
++/**
++ * Sufficient number of frames have been decoded since a SEI recovery point,
++ * so all the following frames in presentation order are correct.
++ */
++#define FRAME_RECOVERED_SEI  (1 << 1)
++
++    int frame_recovered;    ///< Initial frame has been completely recovered
++
++    int has_recovery_point;
++
++    int missing_fields;
++
++    /* for frame threading, this is set to 1
++     * after finish_setup() has been called, so we cannot modify
++     * some context properties (which are supposed to stay constant between
++     * slices) anymore */
++    int setup_finished;
++
++    int cur_chroma_format_idc;
++    int cur_bit_depth_luma;
++    //int16_t slice_row[MAX_SLICES]; ///< to detect when MAX_SLICES is too low
++
++    /* original AVCodecContext dimensions, used to handle container
++     * cropping */
++    int width_from_caller;
++    int height_from_caller;
++
++    unsigned int coded_width;
++    unsigned int coded_height;
++
++    int enable_er;
++
++    //H264SEIContext sei;
++    //int ref2frm[MAX_SLICES][2][64];     ///< reference to frame number lists, used in the loop filter, the first 2 are for -2,-1
++} H264Context;
++
++extern const uint16_t ff_h264_mb_sizes[4];
++
++/**
++ * Reconstruct bitstream slice_type.
++ */
++int ff_h264_get_slice_type(const H264SliceContext *sl);
++
++/**
++ * Allocate tables.
++ * needs width/height
++ */
++int ff_h264_alloc_tables(H264Context *h);
++
++int ff_h264_decode_ref_pic_list_reordering(H264SliceContext *sl, void *logctx);
++int ff_h264_build_ref_list(H264Context *h, H264SliceContext *sl);
++void ff_h264_remove_all_refs(H264Context *h);
++
++/**
++ * Execute the reference picture marking (memory management control operations).
++ */
++int ff_h264_execute_ref_pic_marking(H264Context *h);
++
++int ff_h264_decode_ref_pic_marking(H264SliceContext *sl, GetBitContext *gb,
++                                   const H2645NAL *nal, void *logctx);
++
++void ff_h264_hl_decode_mb(const H264Context *h, H264SliceContext *sl);
++void ff_h264_decode_init_vlc(void);
++
++#if 0
++/**
++ * Decode a macroblock
++ * @return 0 if OK, ER_AC_ERROR / ER_DC_ERROR / ER_MV_ERROR on error
++ */
++int ff_h264_decode_mb_cavlc(const H264Context *h, H264SliceContext *sl);
++
++/**
++ * Decode a CABAC coded macroblock
++ * @return 0 if OK, ER_AC_ERROR / ER_DC_ERROR / ER_MV_ERROR on error
++ */
++int ff_h264_decode_mb_cabac(const H264Context *h, H264SliceContext *sl);
++#endif
++
++void ff_h264_init_cabac_states(const H264Context *h, H264SliceContext *sl);
++
++void ff_h264_direct_dist_scale_factor(const H264Context *const h, H264SliceContext *sl);
++void ff_h264_direct_ref_list_init(const H264Context *const h, H264SliceContext *sl);
++void ff_h264_pred_direct_motion(const H264Context *const h, H264SliceContext *sl,
++                                int *mb_type);
++
++void ff_h264_filter_mb_fast(const H264Context *h, H264SliceContext *sl, int mb_x, int mb_y,
++                            uint8_t *img_y, uint8_t *img_cb, uint8_t *img_cr,
++                            unsigned int linesize, unsigned int uvlinesize);
++void ff_h264_filter_mb(const H264Context *h, H264SliceContext *sl, int mb_x, int mb_y,
++                       uint8_t *img_y, uint8_t *img_cb, uint8_t *img_cr,
++                       unsigned int linesize, unsigned int uvlinesize);
++
++/*
++ * o-o o-o
++ *  / / /
++ * o-o o-o
++ *  ,---'
++ * o-o o-o
++ *  / / /
++ * o-o o-o
++ */
++
++/* Scan8 organization:
++ *    0 1 2 3 4 5 6 7
++ * 0  DY    y y y y y
++ * 1        y Y Y Y Y
++ * 2        y Y Y Y Y
++ * 3        y Y Y Y Y
++ * 4        y Y Y Y Y
++ * 5  DU    u u u u u
++ * 6        u U U U U
++ * 7        u U U U U
++ * 8        u U U U U
++ * 9        u U U U U
++ * 10 DV    v v v v v
++ * 11       v V V V V
++ * 12       v V V V V
++ * 13       v V V V V
++ * 14       v V V V V
++ * DY/DU/DV are for luma/chroma DC.
++ */
++
++#define LUMA_DC_BLOCK_INDEX   48
++#define CHROMA_DC_BLOCK_INDEX 49
++
++// This table must be here because scan8[constant] must be known at compiletime
++static const uint8_t scan8[16 * 3 + 3] = {
++    4 +  1 * 8, 5 +  1 * 8, 4 +  2 * 8, 5 +  2 * 8,
++    6 +  1 * 8, 7 +  1 * 8, 6 +  2 * 8, 7 +  2 * 8,
++    4 +  3 * 8, 5 +  3 * 8, 4 +  4 * 8, 5 +  4 * 8,
++    6 +  3 * 8, 7 +  3 * 8, 6 +  4 * 8, 7 +  4 * 8,
++    4 +  6 * 8, 5 +  6 * 8, 4 +  7 * 8, 5 +  7 * 8,
++    6 +  6 * 8, 7 +  6 * 8, 6 +  7 * 8, 7 +  7 * 8,
++    4 +  8 * 8, 5 +  8 * 8, 4 +  9 * 8, 5 +  9 * 8,
++    6 +  8 * 8, 7 +  8 * 8, 6 +  9 * 8, 7 +  9 * 8,
++    4 + 11 * 8, 5 + 11 * 8, 4 + 12 * 8, 5 + 12 * 8,
++    6 + 11 * 8, 7 + 11 * 8, 6 + 12 * 8, 7 + 12 * 8,
++    4 + 13 * 8, 5 + 13 * 8, 4 + 14 * 8, 5 + 14 * 8,
++    6 + 13 * 8, 7 + 13 * 8, 6 + 14 * 8, 7 + 14 * 8,
++    0 +  0 * 8, 0 +  5 * 8, 0 + 10 * 8
++};
++
++static inline uint32_t pack16to32(unsigned a, unsigned b)
++{
++    return (a & 0xFFFF) + (b << 16);
++}
++
++static inline uint16_t pack8to16(unsigned a, unsigned b)
++{
++    return (a & 0xFF) + (b << 8);
++}
++
++/**
++ * Get the chroma qp.
++ */
++static inline int get_chroma_qp(const PPS *pps, int t, int qscale)
++{
++    return pps->chroma_qp_table[t][qscale];
++}
++
++int ff_h264_field_end(H264Context *h, H264SliceContext *sl, int in_setup);
++
++int ff_h264_ref_picture(H264Context *h, H264Picture *dst, H264Picture *src);
++void ff_h264_unref_picture(H264Context *h, H264Picture *pic);
++void ff_h264_release_picture(H264Context *h, H264Picture *pic);
++
++int ff_h264_slice_context_init(H264Context *h, H264SliceContext *sl);
++
++void ff_h264_draw_horiz_band(const H264Context *h, H264SliceContext *sl, int y, int height);
++
++int ff_h264_decode_slice_header(H264Context *h, H264SliceContext *sl,
++                                const H2645NAL *nal);
++/**
++ * Submit a slice for decoding.
++ *
++ * Parse the slice header, starting a new field/frame if necessary. If any
++ * slices are queued for the previous field, they are decoded.
++ */
++int ff_h264_queue_decode_slice(H264Context *h, const H2645NAL *nal);
++int ff_h264_execute_decode_slices(H264Context *h);
++int ff_h264_update_thread_context(AVCodecContext *dst,
++                                  const AVCodecContext *src);
++
++void ff_h264_flush_change(H264Context *h);
++
++void ff_h264_free_tables(H264Context *h);
++#if 0
++void ff_h264_set_erpic(ERPicture *dst, H264Picture *src);
++#endif
++int h264_enqueue_frame(H264Context *h, AVFrame *f);
++AVFrame *h264_get_queued_frame(H264Context *h);	/*get frame from queued list.*/
++AVFrame *h264_dequeue_frame(H264Context *h);
++
++int h264_decode_frame(AVCodecContext *avctx, void *data,
++                             int *got_frame, AVPacket *avpkt);
++
++int h264_decode_init(AVCodecContext *avctx);
++int h264_decode_end(AVCodecContext *avctx);
++int h264_set_vpu_ops(H264Context *h, void *priv_data, struct vpu_ops *ops);
++
++static inline void h264_set_output_format(H264Context *h, int format, unsigned int coded_width, unsigned int coded_height)
++{
++	h->format = format;
++	h->coded_width = coded_width;
++	h->coded_height = coded_height;
++}
++static inline int h264_get_output_format(H264Context *h)
++{
++	return h->format;
++}
++
++#endif /* AVCODEC_H264DEC_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/intreadwrite.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/intreadwrite.h
+new file mode 100644
+index 000000000..d7a3f08a7
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/intreadwrite.h
+@@ -0,0 +1,509 @@
++#ifndef AVUTIL_INTREADWRITE_H
++#define AVUTIL_INTREADWRITE_H
++
++#ifdef __KERNEL__
++#else
++#include <stdint.h>
++#endif
++
++//#include "libavutil/avconfig.h"
++//#include "attributes.h"
++#include "bswap.h"
++
++typedef union {
++    uint64_t u64;
++    uint32_t u32[2];
++    uint16_t u16[4];
++    uint8_t  u8 [8];
++    double   f64;
++    float    f32[2];
++} av_alias64;
++
++typedef union {
++    uint32_t u32;
++    uint16_t u16[2];
++    uint8_t  u8 [4];
++    float    f32;
++} av_alias32;
++
++typedef union {
++    uint16_t u16;
++    uint8_t  u8 [2];
++} av_alias16;
++
++
++/*
++ * Map AV_RNXX <-> AV_R[BL]XX for all variants provided by per-arch headers.
++ */
++
++#   if    defined(AV_RN16) && !defined(AV_RL16)
++#       define AV_RL16(p) AV_RN16(p)
++#   elif !defined(AV_RN16) &&  defined(AV_RL16)
++#       define AV_RN16(p) AV_RL16(p)
++#   endif
++
++#   if    defined(AV_WN16) && !defined(AV_WL16)
++#       define AV_WL16(p, v) AV_WN16(p, v)
++#   elif !defined(AV_WN16) &&  defined(AV_WL16)
++#       define AV_WN16(p, v) AV_WL16(p, v)
++#   endif
++
++#   if    defined(AV_RN24) && !defined(AV_RL24)
++#       define AV_RL24(p) AV_RN24(p)
++#   elif !defined(AV_RN24) &&  defined(AV_RL24)
++#       define AV_RN24(p) AV_RL24(p)
++#   endif
++
++#   if    defined(AV_WN24) && !defined(AV_WL24)
++#       define AV_WL24(p, v) AV_WN24(p, v)
++#   elif !defined(AV_WN24) &&  defined(AV_WL24)
++#       define AV_WN24(p, v) AV_WL24(p, v)
++#   endif
++
++#   if    defined(AV_RN32) && !defined(AV_RL32)
++#       define AV_RL32(p) AV_RN32(p)
++#   elif !defined(AV_RN32) &&  defined(AV_RL32)
++#       define AV_RN32(p) AV_RL32(p)
++#   endif
++
++#   if    defined(AV_WN32) && !defined(AV_WL32)
++#       define AV_WL32(p, v) AV_WN32(p, v)
++#   elif !defined(AV_WN32) &&  defined(AV_WL32)
++#       define AV_WN32(p, v) AV_WL32(p, v)
++#   endif
++
++#   if    defined(AV_RN48) && !defined(AV_RL48)
++#       define AV_RL48(p) AV_RN48(p)
++#   elif !defined(AV_RN48) &&  defined(AV_RL48)
++#       define AV_RN48(p) AV_RL48(p)
++#   endif
++
++#   if    defined(AV_WN48) && !defined(AV_WL48)
++#       define AV_WL48(p, v) AV_WN48(p, v)
++#   elif !defined(AV_WN48) &&  defined(AV_WL48)
++#       define AV_WN48(p, v) AV_WL48(p, v)
++#   endif
++
++#   if    defined(AV_RN64) && !defined(AV_RL64)
++#       define AV_RL64(p) AV_RN64(p)
++#   elif !defined(AV_RN64) &&  defined(AV_RL64)
++#       define AV_RN64(p) AV_RL64(p)
++#   endif
++
++#   if    defined(AV_WN64) && !defined(AV_WL64)
++#       define AV_WL64(p, v) AV_WN64(p, v)
++#   elif !defined(AV_WN64) &&  defined(AV_WL64)
++#       define AV_WN64(p, v) AV_WL64(p, v)
++#   endif
++
++
++/*
++ * Define AV_[RW]N helper macros to simplify definitions not provided
++ * by per-arch headers.
++ */
++
++#if defined(__GNUC__)
++
++union unaligned_64 { uint64_t l; } __attribute__((packed));
++union unaligned_32 { uint32_t l; } __attribute__((packed));
++union unaligned_16 { uint16_t l; } __attribute__((packed));
++
++#   define AV_RN(s, p) (((const union unaligned_##s *) (p))->l)
++#   define AV_WN(s, p, v) ((((union unaligned_##s *) (p))->l) = (v))
++
++#elif defined(_MSC_VER) && (defined(_M_ARM) || defined(_M_X64) || defined(_M_ARM64)) && AV_HAVE_FAST_UNALIGNED
++
++#   define AV_RN(s, p) (*((const __unaligned uint##s##_t*)(p)))
++#   define AV_WN(s, p, v) (*((__unaligned uint##s##_t*)(p)) = (v))
++
++#elif AV_HAVE_FAST_UNALIGNED
++
++#   define AV_RN(s, p) (((const av_alias##s*)(p))->u##s)
++#   define AV_WN(s, p, v) (((av_alias##s*)(p))->u##s = (v))
++
++#else
++
++#ifndef AV_RB16
++#   define AV_RB16(x)                           \
++    ((((const uint8_t*)(x))[0] << 8) |          \
++      ((const uint8_t*)(x))[1])
++#endif
++#ifndef AV_WB16
++#   define AV_WB16(p, val) do {                 \
++        uint16_t d = (val);                     \
++        ((uint8_t*)(p))[1] = (d);               \
++        ((uint8_t*)(p))[0] = (d)>>8;            \
++    } while(0)
++#endif
++
++#ifndef AV_RL16
++#   define AV_RL16(x)                           \
++    ((((const uint8_t*)(x))[1] << 8) |          \
++      ((const uint8_t*)(x))[0])
++#endif
++#ifndef AV_WL16
++#   define AV_WL16(p, val) do {                 \
++        uint16_t d = (val);                     \
++        ((uint8_t*)(p))[0] = (d);               \
++        ((uint8_t*)(p))[1] = (d)>>8;            \
++    } while(0)
++#endif
++
++#ifndef AV_RB32
++#   define AV_RB32(x)                                \
++    (((uint32_t)((const uint8_t*)(x))[0] << 24) |    \
++               (((const uint8_t*)(x))[1] << 16) |    \
++               (((const uint8_t*)(x))[2] <<  8) |    \
++                ((const uint8_t*)(x))[3])
++#endif
++#ifndef AV_WB32
++#   define AV_WB32(p, val) do {                 \
++        uint32_t d = (val);                     \
++        ((uint8_t*)(p))[3] = (d);               \
++        ((uint8_t*)(p))[2] = (d)>>8;            \
++        ((uint8_t*)(p))[1] = (d)>>16;           \
++        ((uint8_t*)(p))[0] = (d)>>24;           \
++    } while(0)
++#endif
++
++#ifndef AV_RL32
++#   define AV_RL32(x)                                \
++    (((uint32_t)((const uint8_t*)(x))[3] << 24) |    \
++               (((const uint8_t*)(x))[2] << 16) |    \
++               (((const uint8_t*)(x))[1] <<  8) |    \
++                ((const uint8_t*)(x))[0])
++#endif
++#ifndef AV_WL32
++#   define AV_WL32(p, val) do {                 \
++        uint32_t d = (val);                     \
++        ((uint8_t*)(p))[0] = (d);               \
++        ((uint8_t*)(p))[1] = (d)>>8;            \
++        ((uint8_t*)(p))[2] = (d)>>16;           \
++        ((uint8_t*)(p))[3] = (d)>>24;           \
++    } while(0)
++#endif
++
++#ifndef AV_RB64
++#   define AV_RB64(x)                                   \
++    (((uint64_t)((const uint8_t*)(x))[0] << 56) |       \
++     ((uint64_t)((const uint8_t*)(x))[1] << 48) |       \
++     ((uint64_t)((const uint8_t*)(x))[2] << 40) |       \
++     ((uint64_t)((const uint8_t*)(x))[3] << 32) |       \
++     ((uint64_t)((const uint8_t*)(x))[4] << 24) |       \
++     ((uint64_t)((const uint8_t*)(x))[5] << 16) |       \
++     ((uint64_t)((const uint8_t*)(x))[6] <<  8) |       \
++      (uint64_t)((const uint8_t*)(x))[7])
++#endif
++#ifndef AV_WB64
++#   define AV_WB64(p, val) do {                 \
++        uint64_t d = (val);                     \
++        ((uint8_t*)(p))[7] = (d);               \
++        ((uint8_t*)(p))[6] = (d)>>8;            \
++        ((uint8_t*)(p))[5] = (d)>>16;           \
++        ((uint8_t*)(p))[4] = (d)>>24;           \
++        ((uint8_t*)(p))[3] = (d)>>32;           \
++        ((uint8_t*)(p))[2] = (d)>>40;           \
++        ((uint8_t*)(p))[1] = (d)>>48;           \
++        ((uint8_t*)(p))[0] = (d)>>56;           \
++    } while(0)
++#endif
++
++#ifndef AV_RL64
++#   define AV_RL64(x)                                   \
++    (((uint64_t)((const uint8_t*)(x))[7] << 56) |       \
++     ((uint64_t)((const uint8_t*)(x))[6] << 48) |       \
++     ((uint64_t)((const uint8_t*)(x))[5] << 40) |       \
++     ((uint64_t)((const uint8_t*)(x))[4] << 32) |       \
++     ((uint64_t)((const uint8_t*)(x))[3] << 24) |       \
++     ((uint64_t)((const uint8_t*)(x))[2] << 16) |       \
++     ((uint64_t)((const uint8_t*)(x))[1] <<  8) |       \
++      (uint64_t)((const uint8_t*)(x))[0])
++#endif
++#ifndef AV_WL64
++#   define AV_WL64(p, val) do {                 \
++        uint64_t d = (val);                     \
++        ((uint8_t*)(p))[0] = (d);               \
++        ((uint8_t*)(p))[1] = (d)>>8;            \
++        ((uint8_t*)(p))[2] = (d)>>16;           \
++        ((uint8_t*)(p))[3] = (d)>>24;           \
++        ((uint8_t*)(p))[4] = (d)>>32;           \
++        ((uint8_t*)(p))[5] = (d)>>40;           \
++        ((uint8_t*)(p))[6] = (d)>>48;           \
++        ((uint8_t*)(p))[7] = (d)>>56;           \
++    } while(0)
++#endif
++
++#if AV_HAVE_BIGENDIAN
++#   define AV_RN(s, p)    AV_RB##s(p)
++#   define AV_WN(s, p, v) AV_WB##s(p, v)
++#else
++#   define AV_RN(s, p)    AV_RL##s(p)
++#   define AV_WN(s, p, v) AV_WL##s(p, v)
++#endif
++
++#endif /* HAVE_FAST_UNALIGNED */
++
++#ifndef AV_RN16
++#   define AV_RN16(p) AV_RN(16, p)
++#endif
++
++#ifndef AV_RN32
++#   define AV_RN32(p) AV_RN(32, p)
++#endif
++
++#ifndef AV_RN64
++#   define AV_RN64(p) AV_RN(64, p)
++#endif
++
++#ifndef AV_WN16
++#   define AV_WN16(p, v) AV_WN(16, p, v)
++#endif
++
++#ifndef AV_WN32
++#   define AV_WN32(p, v) AV_WN(32, p, v)
++#endif
++
++#ifndef AV_WN64
++#   define AV_WN64(p, v) AV_WN(64, p, v)
++#endif
++
++#   define AV_RB(s, p)    av_bswap##s(AV_RN##s(p))
++#   define AV_WB(s, p, v) AV_WN##s(p, av_bswap##s(v))
++#   define AV_RL(s, p)    AV_RN##s(p)
++#   define AV_WL(s, p, v) AV_WN##s(p, v)
++
++#define AV_RB8(x)     (((const uint8_t*)(x))[0])
++#define AV_WB8(p, d)  do { ((uint8_t*)(p))[0] = (d); } while(0)
++
++#define AV_RL8(x)     AV_RB8(x)
++#define AV_WL8(p, d)  AV_WB8(p, d)
++
++#ifndef AV_RB16
++#   define AV_RB16(p)    AV_RB(16, p)
++#endif
++#ifndef AV_WB16
++#   define AV_WB16(p, v) AV_WB(16, p, v)
++#endif
++
++#ifndef AV_RL16
++#   define AV_RL16(p)    AV_RL(16, p)
++#endif
++#ifndef AV_WL16
++#   define AV_WL16(p, v) AV_WL(16, p, v)
++#endif
++
++#ifndef AV_RB32
++#   define AV_RB32(p)    AV_RB(32, p)
++#endif
++#ifndef AV_WB32
++#   define AV_WB32(p, v) AV_WB(32, p, v)
++#endif
++
++#ifndef AV_RL32
++#   define AV_RL32(p)    AV_RL(32, p)
++#endif
++#ifndef AV_WL32
++#   define AV_WL32(p, v) AV_WL(32, p, v)
++#endif
++
++#ifndef AV_RB64
++#   define AV_RB64(p)    AV_RB(64, p)
++#endif
++#ifndef AV_WB64
++#   define AV_WB64(p, v) AV_WB(64, p, v)
++#endif
++
++#ifndef AV_RL64
++#   define AV_RL64(p)    AV_RL(64, p)
++#endif
++#ifndef AV_WL64
++#   define AV_WL64(p, v) AV_WL(64, p, v)
++#endif
++
++#ifndef AV_RB24
++#   define AV_RB24(x)                           \
++    ((((const uint8_t*)(x))[0] << 16) |         \
++     (((const uint8_t*)(x))[1] <<  8) |         \
++      ((const uint8_t*)(x))[2])
++#endif
++#ifndef AV_WB24
++#   define AV_WB24(p, d) do {                   \
++        ((uint8_t*)(p))[2] = (d);               \
++        ((uint8_t*)(p))[1] = (d)>>8;            \
++        ((uint8_t*)(p))[0] = (d)>>16;           \
++    } while(0)
++#endif
++
++#ifndef AV_RL24
++#   define AV_RL24(x)                           \
++    ((((const uint8_t*)(x))[2] << 16) |         \
++     (((const uint8_t*)(x))[1] <<  8) |         \
++      ((const uint8_t*)(x))[0])
++#endif
++#ifndef AV_WL24
++#   define AV_WL24(p, d) do {                   \
++        ((uint8_t*)(p))[0] = (d);               \
++        ((uint8_t*)(p))[1] = (d)>>8;            \
++        ((uint8_t*)(p))[2] = (d)>>16;           \
++    } while(0)
++#endif
++
++#ifndef AV_RB48
++#   define AV_RB48(x)                                     \
++    (((uint64_t)((const uint8_t*)(x))[0] << 40) |         \
++     ((uint64_t)((const uint8_t*)(x))[1] << 32) |         \
++     ((uint64_t)((const uint8_t*)(x))[2] << 24) |         \
++     ((uint64_t)((const uint8_t*)(x))[3] << 16) |         \
++     ((uint64_t)((const uint8_t*)(x))[4] <<  8) |         \
++      (uint64_t)((const uint8_t*)(x))[5])
++#endif
++#ifndef AV_WB48
++#   define AV_WB48(p, darg) do {                \
++        uint64_t d = (darg);                    \
++        ((uint8_t*)(p))[5] = (d);               \
++        ((uint8_t*)(p))[4] = (d)>>8;            \
++        ((uint8_t*)(p))[3] = (d)>>16;           \
++        ((uint8_t*)(p))[2] = (d)>>24;           \
++        ((uint8_t*)(p))[1] = (d)>>32;           \
++        ((uint8_t*)(p))[0] = (d)>>40;           \
++    } while(0)
++#endif
++
++#ifndef AV_RL48
++#   define AV_RL48(x)                                     \
++    (((uint64_t)((const uint8_t*)(x))[5] << 40) |         \
++     ((uint64_t)((const uint8_t*)(x))[4] << 32) |         \
++     ((uint64_t)((const uint8_t*)(x))[3] << 24) |         \
++     ((uint64_t)((const uint8_t*)(x))[2] << 16) |         \
++     ((uint64_t)((const uint8_t*)(x))[1] <<  8) |         \
++      (uint64_t)((const uint8_t*)(x))[0])
++#endif
++#ifndef AV_WL48
++#   define AV_WL48(p, darg) do {                \
++        uint64_t d = (darg);                    \
++        ((uint8_t*)(p))[0] = (d);               \
++        ((uint8_t*)(p))[1] = (d)>>8;            \
++        ((uint8_t*)(p))[2] = (d)>>16;           \
++        ((uint8_t*)(p))[3] = (d)>>24;           \
++        ((uint8_t*)(p))[4] = (d)>>32;           \
++        ((uint8_t*)(p))[5] = (d)>>40;           \
++    } while(0)
++#endif
++
++/*
++ * The AV_[RW]NA macros access naturally aligned data
++ * in a type-safe way.
++ */
++
++#define AV_RNA(s, p)    (((const av_alias##s*)(p))->u##s)
++#define AV_WNA(s, p, v) (((av_alias##s*)(p))->u##s = (v))
++
++#ifndef AV_RN16A
++#   define AV_RN16A(p) AV_RNA(16, p)
++#endif
++
++#ifndef AV_RN32A
++#   define AV_RN32A(p) AV_RNA(32, p)
++#endif
++
++#ifndef AV_RN64A
++#   define AV_RN64A(p) AV_RNA(64, p)
++#endif
++
++#ifndef AV_WN16A
++#   define AV_WN16A(p, v) AV_WNA(16, p, v)
++#endif
++
++#ifndef AV_WN32A
++#   define AV_WN32A(p, v) AV_WNA(32, p, v)
++#endif
++
++#ifndef AV_WN64A
++#   define AV_WN64A(p, v) AV_WNA(64, p, v)
++#endif
++
++/*
++ * The AV_COPYxxU macros are suitable for copying data to/from unaligned
++ * memory locations.
++ */
++
++#define AV_COPYU(n, d, s) AV_WN##n(d, AV_RN##n(s));
++
++#ifndef AV_COPY16U
++#   define AV_COPY16U(d, s) AV_COPYU(16, d, s)
++#endif
++
++#ifndef AV_COPY32U
++#   define AV_COPY32U(d, s) AV_COPYU(32, d, s)
++#endif
++
++#ifndef AV_COPY64U
++#   define AV_COPY64U(d, s) AV_COPYU(64, d, s)
++#endif
++
++#ifndef AV_COPY128U
++#   define AV_COPY128U(d, s)                                    \
++    do {                                                        \
++        AV_COPY64U(d, s);                                       \
++        AV_COPY64U((char *)(d) + 8, (const char *)(s) + 8);     \
++    } while(0)
++#endif
++
++/* Parameters for AV_COPY*, AV_SWAP*, AV_ZERO* must be
++ * naturally aligned. They may be implemented using MMX,
++ * so emms_c() must be called before using any float code
++ * afterwards.
++ */
++
++#define AV_COPY(n, d, s) \
++    (((av_alias##n*)(d))->u##n = ((const av_alias##n*)(s))->u##n)
++
++#ifndef AV_COPY16
++#   define AV_COPY16(d, s) AV_COPY(16, d, s)
++#endif
++
++#ifndef AV_COPY32
++#   define AV_COPY32(d, s) AV_COPY(32, d, s)
++#endif
++
++#ifndef AV_COPY64
++#   define AV_COPY64(d, s) AV_COPY(64, d, s)
++#endif
++
++#ifndef AV_COPY128
++#   define AV_COPY128(d, s)                    \
++    do {                                       \
++        AV_COPY64(d, s);                       \
++        AV_COPY64((char*)(d)+8, (char*)(s)+8); \
++    } while(0)
++#endif
++
++#define AV_SWAP(n, a, b) FFSWAP(av_alias##n, *(av_alias##n*)(a), *(av_alias##n*)(b))
++
++#ifndef AV_SWAP64
++#   define AV_SWAP64(a, b) AV_SWAP(64, a, b)
++#endif
++
++#define AV_ZERO(n, d) (((av_alias##n*)(d))->u##n = 0)
++
++#ifndef AV_ZERO16
++#   define AV_ZERO16(d) AV_ZERO(16, d)
++#endif
++
++#ifndef AV_ZERO32
++#   define AV_ZERO32(d) AV_ZERO(32, d)
++#endif
++
++#ifndef AV_ZERO64
++#   define AV_ZERO64(d) AV_ZERO(64, d)
++#endif
++
++#ifndef AV_ZERO128
++#   define AV_ZERO128(d)         \
++    do {                         \
++        AV_ZERO64(d);            \
++        AV_ZERO64((char*)(d)+8); \
++    } while(0)
++#endif
++
++#endif /* AVUTIL_INTREADWRITE_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/list.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/list.h
+new file mode 100644
+index 000000000..dcdd1ac72
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/list.h
+@@ -0,0 +1,169 @@
++#ifndef LIST_H
++#define LIST_H
++
++#ifdef __KERNEL__
++#include <linux/list.h>
++
++#else
++
++/*
++ * Copied from include/linux/...
++ */
++
++#undef offsetof
++#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
++
++/**
++ * container_of - cast a member of a structure out to the containing structure
++ * @ptr:        the pointer to the member.
++ * @type:       the type of the container struct this is embedded in.
++ * @member:     the name of the member within the struct.
++ *
++ */
++#define container_of(ptr, type, member) ({                      \
++	const typeof( ((type *)0)->member ) *__mptr = (ptr);    \
++	(type *)( (char *)__mptr - offsetof(type,member) );})
++
++
++struct list_head {
++	struct list_head *next, *prev;
++};
++
++
++#define LIST_HEAD_INIT(name) { &(name), &(name) }
++
++#define LIST_HEAD(name) \
++	struct list_head name = LIST_HEAD_INIT(name)
++
++static inline void INIT_LIST_HEAD(struct list_head *list)
++{
++        list->next = list;
++        list->prev = list;
++}
++
++
++/**
++ * list_entry - get the struct for this entry
++ * @ptr:	the &struct list_head pointer.
++ * @type:	the type of the struct this is embedded in.
++ * @member:	the name of the list_struct within the struct.
++ */
++#define list_entry(ptr, type, member) \
++	container_of(ptr, type, member)
++
++/**
++ * list_first_entry - get the first element from a list
++ * @ptr:        the list head to take the element from.
++ * @type:       the type of the struct this is embedded in.
++ * @member:     the name of the list_struct within the struct.
++ *
++ * Note, that list is expected to be not empty.
++ */
++#define list_first_entry(ptr, type, member) \
++        list_entry((ptr)->next, type, member)
++
++/**
++ * list_first_entry_or_null - get the first element from a list
++ * @ptr:        the list head to take the element from.
++ * @type:       the type of the struct this is embedded in.
++ * @member:     the name of the list_struct within the struct.
++ *
++ * Note that if the list is empty, it returns NULL.
++ */
++#define list_first_entry_or_null(ptr, type, member) \
++        (!list_empty(ptr) ? list_first_entry(ptr, type, member) : NULL)
++
++
++/**
++ * list_for_each_entry	-	iterate over list of given type
++ * @pos:	the type * to use as a loop cursor.
++ * @head:	the head for your list.
++ * @member:	the name of the list_struct within the struct.
++ */
++#define list_for_each_entry(pos, head, member)				\
++	for (pos = list_entry((head)->next, typeof(*pos), member);	\
++	     &pos->member != (head); 	\
++	     pos = list_entry(pos->member.next, typeof(*pos), member))
++
++/**
++ * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry
++ * @pos:	the type * to use as a loop cursor.
++ * @n:		another type * to use as temporary storage
++ * @head:	the head for your list.
++ * @member:	the name of the list_struct within the struct.
++ */
++#define list_for_each_entry_safe(pos, n, head, member)			\
++	for (pos = list_entry((head)->next, typeof(*pos), member),	\
++		n = list_entry(pos->member.next, typeof(*pos), member);	\
++	     &pos->member != (head);					\
++	     pos = n, n = list_entry(n->member.next, typeof(*n), member))
++
++/**
++ * list_empty - tests whether a list is empty
++ * @head: the list to test.
++ */
++static inline int list_empty(const struct list_head *head)
++{
++	return head->next == head;
++}
++
++/*
++ * Insert a new entry between two known consecutive entries.
++ *
++ * This is only for internal list manipulation where we know
++ * the prev/next entries already!
++ */
++static inline void __list_add(struct list_head *_new,
++			      struct list_head *prev,
++			      struct list_head *next)
++{
++	next->prev = _new;
++	_new->next = next;
++	_new->prev = prev;
++	prev->next = _new;
++}
++
++/**
++ * list_add_tail - add a new entry
++ * @new: new entry to be added
++ * @head: list head to add it before
++ *
++ * Insert a new entry before the specified head.
++ * This is useful for implementing queues.
++ */
++static inline void list_add_tail(struct list_head *_new, struct list_head *head)
++{
++	__list_add(_new, head->prev, head);
++}
++
++/*
++ * Delete a list entry by making the prev/next entries
++ * point to each other.
++ *
++ * This is only for internal list manipulation where we know
++ * the prev/next entries already!
++ */
++static inline void __list_del(struct list_head *prev, struct list_head *next)
++{
++	next->prev = prev;
++	prev->next = next;
++}
++
++#define LIST_POISON1  ((void *) 0x00100100)
++#define LIST_POISON2  ((void *) 0x00200200)
++/**
++ * list_del - deletes entry from list.
++ * @entry: the element to delete from the list.
++ * Note: list_empty() on entry does not return true after this, the entry is
++ * in an undefined state.
++ */
++static inline void list_del(struct list_head *entry)
++{
++	__list_del(entry->prev, entry->next);
++	entry->next = (struct list_head*)LIST_POISON1;
++	entry->prev = (struct list_head*)LIST_POISON2;
++}
++
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/log.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/log.h
+new file mode 100644
+index 000000000..2f0345dcc
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/log.h
+@@ -0,0 +1,341 @@
++#ifndef AVUTIL_LOG_H
++#define AVUTIL_LOG_H
++
++#include <stdarg.h>
++//#include "attributes.h"
++//#include "version.h"
++
++typedef enum {
++    AV_CLASS_CATEGORY_NA = 0,
++    AV_CLASS_CATEGORY_INPUT,
++    AV_CLASS_CATEGORY_OUTPUT,
++    AV_CLASS_CATEGORY_MUXER,
++    AV_CLASS_CATEGORY_DEMUXER,
++    AV_CLASS_CATEGORY_ENCODER,
++    AV_CLASS_CATEGORY_DECODER,
++    AV_CLASS_CATEGORY_FILTER,
++    AV_CLASS_CATEGORY_BITSTREAM_FILTER,
++    AV_CLASS_CATEGORY_SWSCALER,
++    AV_CLASS_CATEGORY_SWRESAMPLER,
++    AV_CLASS_CATEGORY_DEVICE_VIDEO_OUTPUT = 40,
++    AV_CLASS_CATEGORY_DEVICE_VIDEO_INPUT,
++    AV_CLASS_CATEGORY_DEVICE_AUDIO_OUTPUT,
++    AV_CLASS_CATEGORY_DEVICE_AUDIO_INPUT,
++    AV_CLASS_CATEGORY_DEVICE_OUTPUT,
++    AV_CLASS_CATEGORY_DEVICE_INPUT,
++    AV_CLASS_CATEGORY_NB  ///< not part of ABI/API
++}AVClassCategory;
++
++#define AV_IS_INPUT_DEVICE(category) \
++    (((category) == AV_CLASS_CATEGORY_DEVICE_VIDEO_INPUT) || \
++     ((category) == AV_CLASS_CATEGORY_DEVICE_AUDIO_INPUT) || \
++     ((category) == AV_CLASS_CATEGORY_DEVICE_INPUT))
++
++#define AV_IS_OUTPUT_DEVICE(category) \
++    (((category) == AV_CLASS_CATEGORY_DEVICE_VIDEO_OUTPUT) || \
++     ((category) == AV_CLASS_CATEGORY_DEVICE_AUDIO_OUTPUT) || \
++     ((category) == AV_CLASS_CATEGORY_DEVICE_OUTPUT))
++
++struct AVOptionRanges;
++
++/**
++ * Describe the class of an AVClass context structure. That is an
++ * arbitrary struct of which the first field is a pointer to an
++ * AVClass struct (e.g. AVCodecContext, AVFormatContext etc.).
++ */
++typedef struct AVClass {
++    /**
++     * The name of the class; usually it is the same name as the
++     * context structure type to which the AVClass is associated.
++     */
++    const char* class_name;
++
++    /**
++     * A pointer to a function which returns the name of a context
++     * instance ctx associated with the class.
++     */
++    const char* (*item_name)(void* ctx);
++
++    /**
++     * a pointer to the first option specified in the class if any or NULL
++     *
++     * @see av_set_default_options()
++     */
++    const struct AVOption *option;
++
++    /**
++     * LIBAVUTIL_VERSION with which this structure was created.
++     * This is used to allow fields to be added without requiring major
++     * version bumps everywhere.
++     */
++
++    int version;
++
++    /**
++     * Offset in the structure where log_level_offset is stored.
++     * 0 means there is no such variable
++     */
++    int log_level_offset_offset;
++
++    /**
++     * Offset in the structure where a pointer to the parent context for
++     * logging is stored. For example a decoder could pass its AVCodecContext
++     * to eval as such a parent context, which an av_log() implementation
++     * could then leverage to display the parent context.
++     * The offset can be NULL.
++     */
++    int parent_log_context_offset;
++
++    /**
++     * Return next AVOptions-enabled child or NULL
++     */
++    void* (*child_next)(void *obj, void *prev);
++
++    /**
++     * Return an AVClass corresponding to the next potential
++     * AVOptions-enabled child.
++     *
++     * The difference between child_next and this is that
++     * child_next iterates over _already existing_ objects, while
++     * child_class_next iterates over _all possible_ children.
++     */
++    const struct AVClass* (*child_class_next)(const struct AVClass *prev);
++
++    /**
++     * Category used for visualization (like color)
++     * This is only set if the category is equal for all objects using this class.
++     * available since version (51 << 16 | 56 << 8 | 100)
++     */
++    AVClassCategory category;
++
++    /**
++     * Callback to return the category.
++     * available since version (51 << 16 | 59 << 8 | 100)
++     */
++    AVClassCategory (*get_category)(void* ctx);
++
++    /**
++     * Callback to return the supported/allowed ranges.
++     * available since version (52.12)
++     */
++    int (*query_ranges)(struct AVOptionRanges **, void *obj, const char *key, int flags);
++} AVClass;
++
++/**
++ * @addtogroup lavu_log
++ *
++ * @{
++ *
++ * @defgroup lavu_log_constants Logging Constants
++ *
++ * @{
++ */
++
++/**
++ * Print no output.
++ */
++#define AV_LOG_QUIET    -8
++
++/**
++ * Something went really wrong and we will crash now.
++ */
++#define AV_LOG_PANIC     0
++
++/**
++ * Something went wrong and recovery is not possible.
++ * For example, no header was found for a format which depends
++ * on headers or an illegal combination of parameters is used.
++ */
++#define AV_LOG_FATAL     8
++
++/**
++ * Something went wrong and cannot losslessly be recovered.
++ * However, not all future data is affected.
++ */
++#define AV_LOG_ERROR    16
++
++/**
++ * Something somehow does not look correct. This may or may not
++ * lead to problems. An example would be the use of '-vstrict -2'.
++ */
++#define AV_LOG_WARNING  24
++
++/**
++ * Standard information.
++ */
++#define AV_LOG_INFO     32
++
++/**
++ * Detailed information.
++ */
++#define AV_LOG_VERBOSE  40
++
++/**
++ * Stuff which is only useful for libav* developers.
++ */
++#define AV_LOG_DEBUG    48
++
++/**
++ * Extremely verbose debugging, useful for libav* development.
++ */
++#define AV_LOG_TRACE    56
++
++#define AV_LOG_MAX_OFFSET (AV_LOG_TRACE - AV_LOG_QUIET)
++
++/**
++ * @}
++ */
++
++/**
++ * Sets additional colors for extended debugging sessions.
++ * @code
++   av_log(ctx, AV_LOG_DEBUG|AV_LOG_C(134), "Message in purple\n");
++   @endcode
++ * Requires 256color terminal support. Uses outside debugging is not
++ * recommended.
++ */
++#define AV_LOG_C(x) ((x) << 8)
++
++/**
++ * Send the specified message to the log if the level is less than or equal
++ * to the current av_log_level. By default, all logging messages are sent to
++ * stderr. This behavior can be altered by setting a different logging callback
++ * function.
++ * @see av_log_set_callback
++ *
++ * @param avcl A pointer to an arbitrary struct of which the first field is a
++ *        pointer to an AVClass struct or NULL if general log.
++ * @param level The importance level of the message expressed using a @ref
++ *        lavu_log_constants "Logging Constant".
++ * @param fmt The format string (printf-compatible) that specifies how
++ *        subsequent arguments are converted to output.
++ */
++void av_log(void *avcl, int level, const char *fmt, ...);
++
++
++/**
++ * Send the specified message to the log if the level is less than or equal
++ * to the current av_log_level. By default, all logging messages are sent to
++ * stderr. This behavior can be altered by setting a different logging callback
++ * function.
++ * @see av_log_set_callback
++ *
++ * @param avcl A pointer to an arbitrary struct of which the first field is a
++ *        pointer to an AVClass struct.
++ * @param level The importance level of the message expressed using a @ref
++ *        lavu_log_constants "Logging Constant".
++ * @param fmt The format string (printf-compatible) that specifies how
++ *        subsequent arguments are converted to output.
++ * @param vl The arguments referenced by the format string.
++ */
++void av_vlog(void *avcl, int level, const char *fmt, va_list vl);
++
++/**
++ * Get the current log level
++ *
++ * @see lavu_log_constants
++ *
++ * @return Current log level
++ */
++int av_log_get_level(void);
++
++/**
++ * Set the log level
++ *
++ * @see lavu_log_constants
++ *
++ * @param level Logging level
++ */
++void av_log_set_level(int level);
++
++/**
++ * Set the logging callback
++ *
++ * @note The callback must be thread safe, even if the application does not use
++ *       threads itself as some codecs are multithreaded.
++ *
++ * @see av_log_default_callback
++ *
++ * @param callback A logging function with a compatible signature.
++ */
++void av_log_set_callback(void (*callback)(void*, int, const char*, va_list));
++
++/**
++ * Default logging callback
++ *
++ * It prints the message to stderr, optionally colorizing it.
++ *
++ * @param avcl A pointer to an arbitrary struct of which the first field is a
++ *        pointer to an AVClass struct.
++ * @param level The importance level of the message expressed using a @ref
++ *        lavu_log_constants "Logging Constant".
++ * @param fmt The format string (printf-compatible) that specifies how
++ *        subsequent arguments are converted to output.
++ * @param vl The arguments referenced by the format string.
++ */
++void av_log_default_callback(void *avcl, int level, const char *fmt,
++                             va_list vl);
++
++/**
++ * Return the context name
++ *
++ * @param  ctx The AVClass context
++ *
++ * @return The AVClass class_name
++ */
++const char* av_default_item_name(void* ctx);
++AVClassCategory av_default_get_category(void *ptr);
++
++/**
++ * Format a line of log the same way as the default callback.
++ * @param line          buffer to receive the formatted line
++ * @param line_size     size of the buffer
++ * @param print_prefix  used to store whether the prefix must be printed;
++ *                      must point to a persistent integer initially set to 1
++ */
++void av_log_format_line(void *ptr, int level, const char *fmt, va_list vl,
++                        char *line, int line_size, int *print_prefix);
++
++/**
++ * Format a line of log the same way as the default callback.
++ * @param line          buffer to receive the formatted line;
++ *                      may be NULL if line_size is 0
++ * @param line_size     size of the buffer; at most line_size-1 characters will
++ *                      be written to the buffer, plus one null terminator
++ * @param print_prefix  used to store whether the prefix must be printed;
++ *                      must point to a persistent integer initially set to 1
++ * @return Returns a negative value if an error occurred, otherwise returns
++ *         the number of characters that would have been written for a
++ *         sufficiently large buffer, not including the terminating null
++ *         character. If the return value is not less than line_size, it means
++ *         that the log message was truncated to fit the buffer.
++ */
++int av_log_format_line2(void *ptr, int level, const char *fmt, va_list vl,
++                        char *line, int line_size, int *print_prefix);
++
++/**
++ * Skip repeated messages, this requires the user app to use av_log() instead of
++ * (f)printf as the 2 would otherwise interfere and lead to
++ * "Last message repeated x times" messages below (f)printf messages with some
++ * bad luck.
++ * Also to receive the last, "last repeated" line if any, the user app must
++ * call av_log(NULL, AV_LOG_QUIET, "%s", ""); at the end
++ */
++#define AV_LOG_SKIP_REPEATED 1
++
++/**
++ * Include the log severity in messages originating from codecs.
++ *
++ * Results in messages such as:
++ * [rawvideo @ 0xDEADBEEF] [error] encode did not produce valid pts
++ */
++#define AV_LOG_PRINT_LEVEL 2
++
++void av_log_set_flags(int arg);
++int av_log_get_flags(void);
++
++/**
++ * @}
++ */
++
++#endif /* AVUTIL_LOG_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/mathops.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/mathops.h
+new file mode 100644
+index 000000000..d8266b305
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/mathops.h
+@@ -0,0 +1,63 @@
++#ifndef __MATHOPS_H__
++#define __MATHOPS_H__
++
++#ifdef __KERNEL__
++#include <linux/types.h>
++#endif
++
++
++#define MAX_NEG_CROP 1024
++extern const uint32_t ff_inverse[257];
++extern const uint8_t ff_sqrt_tab[256];
++extern const uint8_t ff_crop_tab[256 + 2 * MAX_NEG_CROP];
++extern const uint8_t ff_zigzag_direct[64];
++extern const uint8_t ff_zigzag_scan[16+1];
++
++#ifndef NEG_SSR32
++#   define NEG_SSR32(a,s) ((( int32_t)(a))>>(32-(s)))
++#endif
++
++#ifndef NEG_USR32
++#   define NEG_USR32(a,s) (((uint32_t)(a))>>(32-(s)))
++#endif
++
++
++#ifndef ff_ctz
++#define ff_ctz(v) __builtin_ctz(v)
++#endif
++#ifndef ff_ctzll
++#define ff_ctzll(v) __builtin_ctzll(v)
++#endif
++#ifndef ff_clz
++#define ff_clz(v) __builtin_clz(v)
++#endif
++
++#ifndef ff_log2
++#define ff_log2(x) (31 - __builtin_clz((x)|1))
++#endif
++
++#ifndef ff_log2_16bit
++#define ff_log2_16bit	ff_log2
++#endif
++
++#define av_log2	ff_log2
++
++
++#ifndef sign_extend
++static inline int sign_extend(int val, unsigned bits)
++{
++    unsigned shift = 8 * sizeof(int) - bits;
++    union { unsigned u; int s; } v = { (unsigned) val << shift };
++    return v.s >> shift;
++}
++#endif
++
++#ifndef zero_extend
++static inline unsigned zero_extend(unsigned val, unsigned bits)
++{
++    return (val << ((8 * sizeof(int)) - bits)) >> ((8 * sizeof(int)) - bits);
++}
++#endif
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/mem.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/mem.h
+new file mode 100644
+index 000000000..7b36d4b44
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/mem.h
+@@ -0,0 +1,71 @@
++#ifndef AVUTIL_MEM_H
++#define AVUTIL_MEM_H
++
++#ifdef __KERNEL__
++#else
++#include <limits.h>
++#include <stdint.h>
++#endif
++
++//#include "attributes.h"
++#include "error.h"
++
++void *av_malloc(size_t size) ;//av_malloc_attrib av_alloc_size(1);
++
++void *av_mallocz(size_t size);
++
++void *av_malloc_array(size_t nmemb, size_t size);
++
++void *av_mallocz_array(size_t nmemb, size_t size);
++
++void *av_calloc(size_t nmemb, size_t size);
++
++void *av_realloc(void *ptr, size_t size);
++
++int av_reallocp(void *ptr, size_t size);
++
++void *av_realloc_f(void *ptr, size_t nelem, size_t elsize);
++
++void *av_realloc_array(void *ptr, size_t nmemb, size_t size);
++
++int av_reallocp_array(void *ptr, size_t nmemb, size_t size);
++
++void *av_fast_realloc(void *ptr, unsigned int *size, size_t min_size);
++
++void av_fast_malloc(void *ptr, unsigned int *size, size_t min_size);
++
++void av_fast_mallocz(void *ptr, unsigned int *size, size_t min_size);
++
++void av_free(void *ptr);
++
++void av_freep(void *ptr);
++
++char *av_strdup(const char *s);
++
++char *av_strndup(const char *s, size_t len);
++
++void *av_memdup(const void *p, size_t size);
++
++void av_memcpy_backptr(uint8_t *dst, int back, int cnt);
++
++/**
++ * Multiply two `size_t` values checking for overflow.
++ *
++ * @param[in]  a,b Operands of multiplication
++ * @param[out] r   Pointer to the result of the operation
++ * @return 0 on success, AVERROR(EINVAL) on overflow
++ */
++static inline int av_size_mult(size_t a, size_t b, size_t *r)
++{
++    size_t t = a * b;
++    /* Hack inspired from glibc: don't try the division if nelem and elsize
++     * are both less than sqrt(SIZE_MAX). */
++    if ((a | b) >= ((size_t)1 << (sizeof(size_t) * 4)) && a && t / a != b)
++        return AVERROR(EINVAL);
++    *r = t;
++    return 0;
++}
++
++void av_max_alloc(size_t max);
++
++#endif /* AVUTIL_MEM_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/mpegutils.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/mpegutils.h
+new file mode 100644
+index 000000000..6c3d6f764
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/mpegutils.h
+@@ -0,0 +1,27 @@
++#ifndef __MPEGUTILS_H__
++#define __MPEGUTILS_H__
++
++
++/**
++ * Return value for header parsers if frame is not coded.
++ * */
++#define FRAME_SKIPPED 100
++
++/* picture type */
++#define PICT_TOP_FIELD     1
++#define PICT_BOTTOM_FIELD  2
++#define PICT_FRAME         3
++
++/**
++ * Value of Picture.reference when Picture is not a reference picture, but
++ * is held for delayed output.
++ */
++#define DELAYED_PIC_REF 4
++
++#define MAX_MB_BYTES    (30 * 16 * 16 * 3 / 8 + 120)
++#define MAX_FCODE        7
++
++
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/put_bits.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/put_bits.h
+new file mode 100644
+index 000000000..32b96432c
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/put_bits.h
+@@ -0,0 +1,337 @@
++#ifndef AVCODEC_PUT_BITS_H
++#define AVCODEC_PUT_BITS_H
++
++#include "intreadwrite.h"
++#include "avassert.h"
++
++typedef struct PutBitContext {
++    uint32_t bit_buf;
++    int bit_left;
++    uint8_t *buf, *buf_ptr, *buf_end;
++    int size_in_bits;
++} PutBitContext;
++
++/**
++ * Initialize the PutBitContext s.
++ *
++ * @param buffer the buffer where to put bits
++ * @param buffer_size the size in bytes of buffer
++ */
++static inline void init_put_bits(PutBitContext *s, uint8_t *buffer,
++                                 int buffer_size)
++{
++    if (buffer_size < 0) {
++        buffer_size = 0;
++        buffer      = NULL;
++    }
++
++    s->size_in_bits = 8 * buffer_size;
++    s->buf          = buffer;
++    s->buf_end      = s->buf + buffer_size;
++    s->buf_ptr      = s->buf;
++    s->bit_left     = 32;
++    s->bit_buf      = 0;
++}
++
++/**
++ * Rebase the bit writer onto a reallocated buffer.
++ *
++ * @param buffer the buffer where to put bits
++ * @param buffer_size the size in bytes of buffer,
++ *                    must be larger than the previous size
++ */
++static inline void rebase_put_bits(PutBitContext *s, uint8_t *buffer,
++                                   int buffer_size)
++{
++    av_assert0(8*buffer_size > s->size_in_bits);
++
++    s->buf_end = buffer + buffer_size;
++    s->buf_ptr = buffer + (s->buf_ptr - s->buf);
++    s->buf     = buffer;
++    s->size_in_bits = 8 * buffer_size;
++}
++
++/**
++ * @return the total number of bits written to the bitstream.
++ */
++static inline int put_bits_count(PutBitContext *s)
++{
++    return (s->buf_ptr - s->buf) * 8 + 32 - s->bit_left;
++}
++
++/**
++ * @return the number of bits available in the bitstream.
++ */
++static inline int put_bits_left(PutBitContext* s)
++{
++    return (s->buf_end - s->buf_ptr) * 8 - 32 + s->bit_left;
++}
++
++/**
++ * Pad the end of the output stream with zeros.
++ */
++static inline void flush_put_bits(PutBitContext *s)
++{
++#ifndef BITSTREAM_WRITER_LE
++    if (s->bit_left < 32)
++        s->bit_buf <<= s->bit_left;
++#endif
++    while (s->bit_left < 32) {
++        av_assert0(s->buf_ptr < s->buf_end);
++#ifdef BITSTREAM_WRITER_LE
++        *s->buf_ptr++ = s->bit_buf;
++        s->bit_buf  >>= 8;
++#else
++        *s->buf_ptr++ = s->bit_buf >> 24;
++        s->bit_buf  <<= 8;
++#endif
++        s->bit_left  += 8;
++    }
++    s->bit_left = 32;
++    s->bit_buf  = 0;
++}
++
++static inline void flush_put_bits_le(PutBitContext *s)
++{
++    while (s->bit_left < 32) {
++        av_assert0(s->buf_ptr < s->buf_end);
++        *s->buf_ptr++ = s->bit_buf;
++        s->bit_buf  >>= 8;
++        s->bit_left  += 8;
++    }
++    s->bit_left = 32;
++    s->bit_buf  = 0;
++}
++
++#ifdef BITSTREAM_WRITER_LE
++#define avpriv_align_put_bits align_put_bits_unsupported_here
++#define avpriv_put_string ff_put_string_unsupported_here
++#define avpriv_copy_bits avpriv_copy_bits_unsupported_here
++#else
++/**
++ * Pad the bitstream with zeros up to the next byte boundary.
++ */
++void avpriv_align_put_bits(PutBitContext *s);
++
++/**
++ * Put the string string in the bitstream.
++ *
++ * @param terminate_string 0-terminates the written string if value is 1
++ */
++void avpriv_put_string(PutBitContext *pb, const char *string,
++                       int terminate_string);
++
++/**
++ * Copy the content of src to the bitstream.
++ *
++ * @param length the number of bits of src to copy
++ */
++void avpriv_copy_bits(PutBitContext *pb, const uint8_t *src, int length);
++#endif
++
++/**
++ * Write up to 31 bits into a bitstream.
++ * Use put_bits32 to write 32 bits.
++ */
++static inline void put_bits(PutBitContext *s, int n, unsigned int value)
++{
++    unsigned int bit_buf;
++    int bit_left;
++
++    av_assert2(n <= 31 && value < (1U << n));
++
++    bit_buf  = s->bit_buf;
++    bit_left = s->bit_left;
++
++    /* XXX: optimize */
++#ifdef BITSTREAM_WRITER_LE
++    bit_buf |= value << (32 - bit_left);
++    if (n >= bit_left) {
++        if (3 < s->buf_end - s->buf_ptr) {
++            AV_WL32(s->buf_ptr, bit_buf);
++            s->buf_ptr += 4;
++        } else {
++            av_log(NULL, AV_LOG_ERROR, "Internal error, put_bits buffer too small\n");
++            av_assert2(0);
++        }
++        bit_buf     = value >> bit_left;
++        bit_left   += 32;
++    }
++    bit_left -= n;
++#else
++    if (n < bit_left) {
++        bit_buf     = (bit_buf << n) | value;
++        bit_left   -= n;
++    } else {
++        bit_buf   <<= bit_left;
++        bit_buf    |= value >> (n - bit_left);
++        if (3 < s->buf_end - s->buf_ptr) {
++            AV_WB32(s->buf_ptr, bit_buf);
++            s->buf_ptr += 4;
++        } else {
++            av_log(NULL, AV_LOG_ERROR, "Internal error, put_bits buffer too small\n");
++            av_assert2(0);
++        }
++        bit_left   += 32 - n;
++        bit_buf     = value;
++    }
++#endif
++
++    s->bit_buf  = bit_buf;
++    s->bit_left = bit_left;
++}
++
++static inline void put_bits_le(PutBitContext *s, int n, unsigned int value)
++{
++    unsigned int bit_buf;
++    int bit_left;
++
++    av_assert2(n <= 31 && value < (1U << n));
++
++    bit_buf  = s->bit_buf;
++    bit_left = s->bit_left;
++
++    bit_buf |= value << (32 - bit_left);
++    if (n >= bit_left) {
++        if (3 < s->buf_end - s->buf_ptr) {
++            AV_WL32(s->buf_ptr, bit_buf);
++            s->buf_ptr += 4;
++        } else {
++            av_log(NULL, AV_LOG_ERROR, "Internal error, put_bits buffer too small\n");
++            av_assert2(0);
++        }
++        bit_buf     = value >> bit_left;
++        bit_left   += 32;
++    }
++    bit_left -= n;
++
++    s->bit_buf  = bit_buf;
++    s->bit_left = bit_left;
++}
++
++static inline void put_sbits(PutBitContext *pb, int n, int32_t value)
++{
++    av_assert2(n >= 0 && n <= 31);
++
++    put_bits(pb, n, av_mod_uintp2(value, n));
++}
++
++/**
++ * Write exactly 32 bits into a bitstream.
++ */
++static void __maybe_unused put_bits32(PutBitContext *s, uint32_t value)
++{
++    unsigned int bit_buf;
++    int bit_left;
++
++    bit_buf  = s->bit_buf;
++    bit_left = s->bit_left;
++
++#ifdef BITSTREAM_WRITER_LE
++    bit_buf |= value << (32 - bit_left);
++    if (3 < s->buf_end - s->buf_ptr) {
++        AV_WL32(s->buf_ptr, bit_buf);
++        s->buf_ptr += 4;
++    } else {
++        av_log(NULL, AV_LOG_ERROR, "Internal error, put_bits buffer too small\n");
++        av_assert2(0);
++    }
++    bit_buf     = (uint64_t)value >> bit_left;
++#else
++    bit_buf     = (uint64_t)bit_buf << bit_left;
++    bit_buf    |= value >> (32 - bit_left);
++    if (3 < s->buf_end - s->buf_ptr) {
++        AV_WB32(s->buf_ptr, bit_buf);
++        s->buf_ptr += 4;
++    } else {
++        av_log(NULL, AV_LOG_ERROR, "Internal error, put_bits buffer too small\n");
++        av_assert2(0);
++    }
++    bit_buf     = value;
++#endif
++
++    s->bit_buf  = bit_buf;
++    s->bit_left = bit_left;
++}
++
++/**
++ * Write up to 64 bits into a bitstream.
++ */
++static inline void put_bits64(PutBitContext *s, int n, uint64_t value)
++{
++    av_assert2((n == 64) || (n < 64 && value < (UINT64_C(1) << n)));
++
++    if (n < 32)
++        put_bits(s, n, value);
++    else if (n == 32)
++        put_bits32(s, value);
++    else if (n < 64) {
++        uint32_t lo = value & 0xffffffff;
++        uint32_t hi = value >> 32;
++#ifdef BITSTREAM_WRITER_LE
++        put_bits32(s, lo);
++        put_bits(s, n - 32, hi);
++#else
++        put_bits(s, n - 32, hi);
++        put_bits32(s, lo);
++#endif
++    } else {
++        uint32_t lo = value & 0xffffffff;
++        uint32_t hi = value >> 32;
++#ifdef BITSTREAM_WRITER_LE
++        put_bits32(s, lo);
++        put_bits32(s, hi);
++#else
++        put_bits32(s, hi);
++        put_bits32(s, lo);
++#endif
++
++    }
++}
++
++/**
++ * Return the pointer to the byte where the bitstream writer will put
++ * the next bit.
++ */
++static inline uint8_t *put_bits_ptr(PutBitContext *s)
++{
++    return s->buf_ptr;
++}
++
++/**
++ * Skip the given number of bytes.
++ * PutBitContext must be flushed & aligned to a byte boundary before calling this.
++ */
++static inline void skip_put_bytes(PutBitContext *s, int n)
++{
++    av_assert2((put_bits_count(s) & 7) == 0);
++    av_assert2(s->bit_left == 32);
++    av_assert0(n <= s->buf_end - s->buf_ptr);
++    s->buf_ptr += n;
++}
++
++/**
++ * Skip the given number of bits.
++ * Must only be used if the actual values in the bitstream do not matter.
++ * If n is 0 the behavior is undefined.
++ */
++static inline void skip_put_bits(PutBitContext *s, int n)
++{
++    s->bit_left -= n;
++    s->buf_ptr  -= 4 * (s->bit_left >> 5);
++    s->bit_left &= 31;
++}
++
++/**
++ * Change the end of the buffer.
++ *
++ * @param size the new size in bytes of the buffer where to put bits
++ */
++static inline void set_put_bits_buffer_size(PutBitContext *s, int size)
++{
++    av_assert0(size <= INT_MAX/8 - 32);
++    s->buf_end = s->buf + size;
++    s->size_in_bits = 8*size;
++}
++
++#endif /* AVCODEC_PUT_BITS_H */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/vpu_ops.h b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/vpu_ops.h
+new file mode 100644
+index 000000000..e983558b4
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/include/vpu_ops.h
+@@ -0,0 +1,45 @@
++#ifndef __VPU_OPS_H__
++#define __VPU_OPS_H__
++
++#include "api/jzm_vpu.h"
++
++struct vpu_ops;
++struct vpu_ctx;
++
++typedef struct vpu_ctx {
++	int fd;	/*vpu handle*/
++	unsigned int vpu_base;
++	struct vpu_ops *ops;
++
++	unsigned int desc_va;
++	unsigned int desc_pa;
++
++	unsigned int sch_stat;
++	unsigned int sde_stat;
++	unsigned int error;
++
++	void *priv;
++} vpu_ctx_t;
++
++struct vpu_ops {
++	int (*start)(void *priv);
++	int (*wait)(void *priv);
++	int (*end)(void *priv);
++};
++
++#define WAIT_COMPLETE		0
++#define CMD_VPU_RESET           105
++
++
++int vpu_ctx_init(struct vpu_ctx *ctx);
++void vpu_ctx_uninit(struct vpu_ctx *ctx);
++
++int vpu_hw_start(struct vpu_ctx *ctx);
++
++int vpu_hw_wait(struct vpu_ctx *ctx);
++
++int vpu_hw_end(struct vpu_ctx *ctx);
++
++int vpu_ctx_set_ops(struct vpu_ctx *ctx, void *priv, struct vpu_ops *ops);
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/Makefile b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/Makefile
+new file mode 100644
+index 000000000..370727f89
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/Makefile
+@@ -0,0 +1,25 @@
++ccflags-y += -I$(srctree)/drivers/media/platform/ingenic-vcodec/felix/libh264/
++ccflags-y += -I$(srctree)/drivers/media/platform/ingenic-vcodec/felix/libh264/include/
++
++
++libh264-y +=	\
++	log.o	\
++	mem.o	\
++	h264_picture.o		\
++	golomb.o		\
++	h264data.o		\
++	h264_refs.o		\
++	mathtables.o		\
++	h2645_parse.o		\
++	h264_parse.o		\
++	h264_direct.o		\
++	h264_ps.o		\
++	h264_sei.o		\
++	buffer.o		\
++	vpu_ops.o		\
++	h264_slice.o		\
++	h264dec.o
++
++obj-y += libh264.o
++
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/buffer.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/buffer.c
+new file mode 100644
+index 000000000..f07110efc
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/buffer.c
+@@ -0,0 +1,194 @@
++#ifdef __KERNEL__
++#include <linux/dma-mapping.h>
++
++#else
++#include <stdio.h>
++#include <sys/types.h>
++#include <sys/stat.h>
++#include <sys/mman.h>
++#include <fcntl.h>
++#include <sys/ioctl.h>
++#endif
++
++#include "error.h"
++#include "mem.h"
++#include "devmem.h"
++#include "buffer.h"
++
++#define DEBUG_MM_ALLOC	1
++//#define DEBUG_MM_ALLOC_PRINT
++
++static int devmem_alloc(devmem_ctx_t *ctx, devmem_info_t *di)
++{
++	int ret = 0;
++	dma_addr_t dma_addr;
++	di->coherent = 0;
++
++	if(di->coherent) {
++		di->kva = (unsigned long)dma_alloc_coherent(ctx->dev, di->length, &dma_addr, GFP_KERNEL);
++	} else {
++		di->kva = (unsigned long)dma_alloc_noncoherent(ctx->dev, di->length, &dma_addr, DMA_BIDIRECTIONAL, GFP_KERNEL);
++	}
++
++	if(!di->kva)
++		return -ENOMEM;
++
++	di->paddr = dma_addr;
++	di->userptr = di->kva;	/* kernel mode, userptr = kernel address */
++	return ret;
++}
++
++static void devmem_free(devmem_ctx_t *ctx, devmem_info_t *di)
++{
++	if(di->coherent) {
++		dma_free_coherent(ctx->dev, di->length, (void *)di->kva, (dma_addr_t)di->paddr);
++	} else {
++		dma_free_noncoherent(ctx->dev, di->length, (void *)di->kva, (dma_addr_t)di->paddr, DMA_BIDIRECTIONAL);
++	}
++}
++
++static void devmem_sync(devmem_ctx_t *ctx, devmem_info_t *di)
++{
++	if(di->coherent)
++		return;
++
++	dma_sync_single_for_device(ctx->dev, (dma_addr_t)(di->paddr), di->length, di->sync_dir);
++
++}
++
++#ifdef DEBUG_MM_ALLOC
++struct debug_mm_alloc {
++	unsigned long alloc_size[128];
++	unsigned long index;
++
++	unsigned long long total_alloc_size;
++	unsigned long long total_alloc_cnt;
++	unsigned long long total_free_size;
++	unsigned long long total_free_cnt;
++} dbg_alloc;
++#endif
++
++int devmem_ctx_init(devmem_ctx_t *ctx, devmem_ops_t *ops)
++{
++
++#ifdef DEBUG_MM_ALLOC
++	memset(&dbg_alloc, 0, sizeof(struct debug_mm_alloc));
++#endif
++
++	return 0;
++}
++
++void devmem_ctx_uninit(devmem_ctx_t *ctx)
++{
++
++}
++
++
++/**
++ * @brief 使用已�分�好的内存，创建AVBuffer结构体.
++ * 	  caller: 必须���内存有效.
++ *
++ * @param va  va 是虚拟地�
++ * @param pa  pa 是对应的物�地�，给到dma使用.
++ * @param size
++ * @param buf 输出buf.
++ *
++ * @return
++ */
++
++AVBuffer *av_buffer_create(char *va, unsigned int pa, unsigned int size)
++{
++	AVBuffer *buf = av_malloc(sizeof(AVBuffer));
++
++	if(!buf)
++		return NULL;
++
++	buf->buffer = va;
++	buf->buffer_pa = pa;
++	buf->size = size;
++	return buf;
++}
++
++void av_buffer_del(AVBuffer *buf)
++{
++	if(buf)
++		av_free(buf);
++}
++
++AVBuffer *av_buffer_alloc(devmem_ctx_t *ctx, unsigned int size)
++{
++	AVBuffer *buf = av_mallocz(sizeof(AVBuffer));
++	int ret;
++
++	if(!buf) {
++		return NULL;
++	}
++
++	buf->di.length = size;
++
++	ret = devmem_alloc(ctx, &buf->di);
++	if(ret < 0) {
++		goto err_alloc;
++	}
++
++	buf->buffer = buf->di.userptr;
++	buf->buffer_pa = buf->di.paddr;
++	buf->size = size;
++
++#ifdef DEBUG_MM_ALLOC
++	dbg_alloc.total_alloc_size += buf->size;
++	dbg_alloc.total_alloc_cnt ++;
++#ifdef DEBUG_MM_ALLOC_PRINT
++	printk("total_alloc_cnt: %llu, alloc_size: %d, total_alloc_size: %llu, total_free_size:%llu, total_free_cnt:%llu\n",
++			dbg_alloc.total_alloc_cnt, size, dbg_alloc.total_alloc_size, dbg_alloc.total_free_size, dbg_alloc.total_free_cnt);
++#endif
++#endif
++
++
++	return buf;
++err_alloc:
++#ifdef DEBUG_MM_ALLOC
++	printk("total_alloc_cnt: %llu, alloc_size: %d, total_alloc_size: %llu, total_free_size:%llu, total_free_cnt:%llu\n",
++			dbg_alloc.total_alloc_cnt, size, dbg_alloc.total_alloc_size, dbg_alloc.total_free_size, dbg_alloc.total_free_cnt);
++#endif
++	av_freep(buf);
++	return NULL;
++}
++
++
++
++void av_buffer_sync(devmem_ctx_t *ctx, AVBuffer *buf, int dir)
++{
++	buf->di.sync_dir = dir;
++
++	devmem_sync(ctx, &buf->di);
++}
++
++
++void av_buffer_free(devmem_ctx_t *ctx, AVBuffer *buf)
++{
++	if(!buf)
++		return;
++
++	if(buf->buffer) {
++#ifdef DEBUG_MM_ALLOC
++		dbg_alloc.total_free_size += buf->size;
++		dbg_alloc.total_free_cnt ++;
++#endif
++		devmem_free(ctx, &buf->di);
++		buf->buffer = NULL;
++	}
++
++
++	av_free(buf);
++}
++
++void av_buffer_dump(void)
++{
++#ifdef DEBUG_MM_ALLOC
++	printk("total_alloc_cnt: %llu, total_alloc_size: %llu, total_free_size:%llu, total_free_cnt:%llu\n",
++			dbg_alloc.total_alloc_cnt, dbg_alloc.total_alloc_size, dbg_alloc.total_free_size, dbg_alloc.total_free_cnt);
++#endif
++
++}
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/golomb.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/golomb.c
+new file mode 100644
+index 000000000..0f4af0e7d
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/golomb.c
+@@ -0,0 +1,145 @@
++#include "common.h"
++
++const uint8_t ff_golomb_vlc_len[512]={
++19,17,15,15,13,13,13,13,11,11,11,11,11,11,11,11,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
++7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
++5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
++5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
++3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
++3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
++3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
++3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
++1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
++1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
++1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
++1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
++1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
++1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
++1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
++1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1
++};
++
++const uint8_t ff_ue_golomb_vlc_code[512]={
++32,32,32,32,32,32,32,32,31,32,32,32,32,32,32,32,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,
++ 7, 7, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9,10,10,10,10,11,11,11,11,12,12,12,12,13,13,13,13,14,14,14,14,
++ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
++ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
++};
++
++const int8_t ff_se_golomb_vlc_code[512]={
++ 17, 17, 17, 17, 17, 17, 17, 17, 16, 17, 17, 17, 17, 17, 17, 17,  8, -8,  9, -9, 10,-10, 11,-11, 12,-12, 13,-13, 14,-14, 15,-15,
++  4,  4,  4,  4, -4, -4, -4, -4,  5,  5,  5,  5, -5, -5, -5, -5,  6,  6,  6,  6, -6, -6, -6, -6,  7,  7,  7,  7, -7, -7, -7, -7,
++  2,  2,  2,  2,  2,  2,  2,  2,  2,  2,  2,  2,  2,  2,  2,  2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2, -2,
++  3,  3,  3,  3,  3,  3,  3,  3,  3,  3,  3,  3,  3,  3,  3,  3, -3, -3, -3, -3, -3, -3, -3, -3, -3, -3, -3, -3, -3, -3, -3, -3,
++  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,
++  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,
++ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
++ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
++  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
++  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
++  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
++  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
++  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
++  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
++  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
++  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
++};
++
++
++const uint8_t ff_ue_golomb_len[256]={
++ 1, 3, 3, 5, 5, 5, 5, 7, 7, 7, 7, 7, 7, 7, 7, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,11,
++11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,13,
++13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,
++13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,15,
++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,
++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,
++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,
++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,17,
++};
++
++const uint8_t ff_interleaved_golomb_vlc_len[256]={
++9,9,7,7,9,9,7,7,5,5,5,5,5,5,5,5,
++9,9,7,7,9,9,7,7,5,5,5,5,5,5,5,5,
++3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
++3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
++9,9,7,7,9,9,7,7,5,5,5,5,5,5,5,5,
++9,9,7,7,9,9,7,7,5,5,5,5,5,5,5,5,
++3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
++3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
++1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
++1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
++1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
++1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
++1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
++1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
++1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
++1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
++};
++
++const uint8_t ff_interleaved_ue_golomb_vlc_code[256]={
++ 15,16,7, 7, 17,18,8, 8, 3, 3, 3, 3, 3, 3, 3, 3,
++ 19,20,9, 9, 21,22,10,10,4, 4, 4, 4, 4, 4, 4, 4,
++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++ 23,24,11,11,25,26,12,12,5, 5, 5, 5, 5, 5, 5, 5,
++ 27,28,13,13,29,30,14,14,6, 6, 6, 6, 6, 6, 6, 6,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++};
++
++const int8_t ff_interleaved_se_golomb_vlc_code[256]={
++  8, -8,  4,  4,  9, -9, -4, -4,  2,  2,  2,  2,  2,  2,  2,  2,
++ 10,-10,  5,  5, 11,-11, -5, -5, -2, -2, -2, -2, -2, -2, -2, -2,
++  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,
++  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,
++ 12,-12,  6,  6, 13,-13, -6, -6,  3,  3,  3,  3,  3,  3,  3,  3,
++ 14,-14,  7,  7, 15,-15, -7, -7, -3, -3, -3, -3, -3, -3, -3, -3,
++ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
++ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
++  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
++  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
++  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
++  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
++  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
++  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
++  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
++  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
++};
++
++const uint8_t ff_interleaved_dirac_golomb_vlc_code[256]={
++0, 1, 0, 0, 2, 3, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
++4, 5, 2, 2, 6, 7, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1,
++0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++8, 9, 4, 4, 10,11,5, 5, 2, 2, 2, 2, 2, 2, 2, 2,
++12,13,6, 6, 14,15,7, 7, 3, 3, 3, 3, 3, 3, 3, 3,
++1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,};
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h2645_parse.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h2645_parse.c
+new file mode 100644
+index 000000000..7cca5fe4e
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h2645_parse.c
+@@ -0,0 +1,401 @@
++#ifdef __KERNEL__
++#include <linux/string.h>
++#else
++#include <string.h>
++#endif
++
++#include "intreadwrite.h"
++#include "mem.h"
++
++#include "bytestream.h"
++#include "h264.h"
++#include "h2645_parse.h"
++
++int ff_h2645_extract_rbsp(const uint8_t *src, int length,
++                	H2645NAL *nal, int small_padding)
++{
++    int i;
++    int consumed = length;
++
++    nal->skipped_bytes = 0;
++#define STARTCODE_TEST                                                  \
++        if (i + 2 < length && src[i + 1] == 0 && src[i + 2] < 3) {     \
++            if (src[i + 2] != 3 && src[i + 2] != 0) {                   \
++                /* startcode, so we must be past the end */             \
++                length = i;                                             \
++            }                                                           \
++            break;                                                      \
++        }
++
++    for (i = 0; i + 1 < length; i += 2) {
++        if (src[i])
++            continue;
++        if (i > 0 && src[i - 1] == 0)
++            i--;
++        STARTCODE_TEST;
++    }
++    consumed = i;
++    nal->data = nal->raw_data = src;
++    nal->size = nal->raw_size = consumed + 1;
++    return consumed;
++}
++
++static const char *hevc_nal_type_name[64] = {
++    "TRAIL_N", // HEVC_NAL_TRAIL_N
++    "TRAIL_R", // HEVC_NAL_TRAIL_R
++    "TSA_N", // HEVC_NAL_TSA_N
++    "TSA_R", // HEVC_NAL_TSA_R
++    "STSA_N", // HEVC_NAL_STSA_N
++    "STSA_R", // HEVC_NAL_STSA_R
++    "RADL_N", // HEVC_NAL_RADL_N
++    "RADL_R", // HEVC_NAL_RADL_R
++    "RASL_N", // HEVC_NAL_RASL_N
++    "RASL_R", // HEVC_NAL_RASL_R
++    "RSV_VCL_N10", // HEVC_NAL_VCL_N10
++    "RSV_VCL_R11", // HEVC_NAL_VCL_R11
++    "RSV_VCL_N12", // HEVC_NAL_VCL_N12
++    "RSV_VLC_R13", // HEVC_NAL_VCL_R13
++    "RSV_VCL_N14", // HEVC_NAL_VCL_N14
++    "RSV_VCL_R15", // HEVC_NAL_VCL_R15
++    "BLA_W_LP", // HEVC_NAL_BLA_W_LP
++    "BLA_W_RADL", // HEVC_NAL_BLA_W_RADL
++    "BLA_N_LP", // HEVC_NAL_BLA_N_LP
++    "IDR_W_RADL", // HEVC_NAL_IDR_W_RADL
++    "IDR_N_LP", // HEVC_NAL_IDR_N_LP
++    "CRA_NUT", // HEVC_NAL_CRA_NUT
++    "IRAP_IRAP_VCL22", // HEVC_NAL_IRAP_VCL22
++    "IRAP_IRAP_VCL23", // HEVC_NAL_IRAP_VCL23
++    "RSV_VCL24", // HEVC_NAL_RSV_VCL24
++    "RSV_VCL25", // HEVC_NAL_RSV_VCL25
++    "RSV_VCL26", // HEVC_NAL_RSV_VCL26
++    "RSV_VCL27", // HEVC_NAL_RSV_VCL27
++    "RSV_VCL28", // HEVC_NAL_RSV_VCL28
++    "RSV_VCL29", // HEVC_NAL_RSV_VCL29
++    "RSV_VCL30", // HEVC_NAL_RSV_VCL30
++    "RSV_VCL31", // HEVC_NAL_RSV_VCL31
++    "VPS", // HEVC_NAL_VPS
++    "SPS", // HEVC_NAL_SPS
++    "PPS", // HEVC_NAL_PPS
++    "AUD", // HEVC_NAL_AUD
++    "EOS_NUT", // HEVC_NAL_EOS_NUT
++    "EOB_NUT", // HEVC_NAL_EOB_NUT
++    "FD_NUT", // HEVC_NAL_FD_NUT
++    "SEI_PREFIX", // HEVC_NAL_SEI_PREFIX
++    "SEI_SUFFIX", // HEVC_NAL_SEI_SUFFIX
++    "RSV_NVCL41", // HEVC_NAL_RSV_NVCL41
++    "RSV_NVCL42", // HEVC_NAL_RSV_NVCL42
++    "RSV_NVCL43", // HEVC_NAL_RSV_NVCL43
++    "RSV_NVCL44", // HEVC_NAL_RSV_NVCL44
++    "RSV_NVCL45", // HEVC_NAL_RSV_NVCL45
++    "RSV_NVCL46", // HEVC_NAL_RSV_NVCL46
++    "RSV_NVCL47", // HEVC_NAL_RSV_NVCL47
++    "UNSPEC48", // HEVC_NAL_UNSPEC48
++    "UNSPEC49", // HEVC_NAL_UNSPEC49
++    "UNSPEC50", // HEVC_NAL_UNSPEC50
++    "UNSPEC51", // HEVC_NAL_UNSPEC51
++    "UNSPEC52", // HEVC_NAL_UNSPEC52
++    "UNSPEC53", // HEVC_NAL_UNSPEC53
++    "UNSPEC54", // HEVC_NAL_UNSPEC54
++    "UNSPEC55", // HEVC_NAL_UNSPEC55
++    "UNSPEC56", // HEVC_NAL_UNSPEC56
++    "UNSPEC57", // HEVC_NAL_UNSPEC57
++    "UNSPEC58", // HEVC_NAL_UNSPEC58
++    "UNSPEC59", // HEVC_NAL_UNSPEC59
++    "UNSPEC60", // HEVC_NAL_UNSPEC60
++    "UNSPEC61", // HEVC_NAL_UNSPEC61
++    "UNSPEC62", // HEVC_NAL_UNSPEC62
++    "UNSPEC63", // HEVC_NAL_UNSPEC63
++};
++
++static const char *hevc_nal_unit_name(int nal_type)
++{
++    av_assert0(nal_type >= 0 && nal_type < 64);
++    return hevc_nal_type_name[nal_type];
++}
++
++static const char *h264_nal_type_name[32] = {
++    "Unspecified 0", //H264_NAL_UNSPECIFIED
++    "Coded slice of a non-IDR picture", // H264_NAL_SLICE
++    "Coded slice data partition A", // H264_NAL_DPA
++    "Coded slice data partition B", // H264_NAL_DPB
++    "Coded slice data partition C", // H264_NAL_DPC
++    "IDR", // H264_NAL_IDR_SLICE
++    "SEI", // H264_NAL_SEI
++    "SPS", // H264_NAL_SPS
++    "PPS", // H264_NAL_PPS
++    "AUD", // H264_NAL_AUD
++    "End of sequence", // H264_NAL_END_SEQUENCE
++    "End of stream", // H264_NAL_END_STREAM
++    "Filler data", // H264_NAL_FILLER_DATA
++    "SPS extension", // H264_NAL_SPS_EXT
++    "Prefix", // H264_NAL_PREFIX
++    "Subset SPS", // H264_NAL_SUB_SPS
++    "Depth parameter set", // H264_NAL_DPS
++    "Reserved 17", // H264_NAL_RESERVED17
++    "Reserved 18", // H264_NAL_RESERVED18
++    "Auxiliary coded picture without partitioning", // H264_NAL_AUXILIARY_SLICE
++    "Slice extension", // H264_NAL_EXTEN_SLICE
++    "Slice extension for a depth view or a 3D-AVC texture view", // H264_NAL_DEPTH_EXTEN_SLICE
++    "Reserved 22", // H264_NAL_RESERVED22
++    "Reserved 23", // H264_NAL_RESERVED23
++    "Unspecified 24", // H264_NAL_UNSPECIFIED24
++    "Unspecified 25", // H264_NAL_UNSPECIFIED25
++    "Unspecified 26", // H264_NAL_UNSPECIFIED26
++    "Unspecified 27", // H264_NAL_UNSPECIFIED27
++    "Unspecified 28", // H264_NAL_UNSPECIFIED28
++    "Unspecified 29", // H264_NAL_UNSPECIFIED29
++    "Unspecified 30", // H264_NAL_UNSPECIFIED30
++    "Unspecified 31", // H264_NAL_UNSPECIFIED31
++};
++
++static const char *h264_nal_unit_name(int nal_type)
++{
++    av_assert0(nal_type >= 0 && nal_type < 32);
++    return h264_nal_type_name[nal_type];
++}
++
++static int get_bit_length(H2645NAL *nal, int skip_trailing_zeros)
++{
++    int size = nal->size;
++    int v;
++
++    while (skip_trailing_zeros && size > 0 && nal->data[size - 1] == 0)
++        size--;
++
++    if (!size)
++        return 0;
++
++    v = nal->data[size - 1];
++
++    if (size > INT_MAX / 8)
++        return AVERROR(ERANGE);
++    size *= 8;
++
++    /* remove the stop bit and following trailing zeros,
++     * or nothing for damaged bitstreams */
++    if (v)
++        size -= ff_ctz(v) + 1;
++
++    return size;
++}
++
++/**
++ * @return AVERROR_INVALIDDATA if the packet is not a valid NAL unit,
++ * 0 if the unit should be skipped, 1 otherwise
++ */
++static int hevc_parse_nal_header(H2645NAL *nal, void *logctx)
++{
++    GetBitContext *gb = &nal->gb;
++    int nuh_layer_id;
++
++    if (get_bits1(gb) != 0)
++        return AVERROR_INVALIDDATA;
++
++    nal->type = get_bits(gb, 6);
++
++    nuh_layer_id   = get_bits(gb, 6);
++    nal->temporal_id = get_bits(gb, 3) - 1;
++    if (nal->temporal_id < 0)
++        return AVERROR_INVALIDDATA;
++
++    av_log(logctx, AV_LOG_DEBUG,
++           "nal_unit_type: %d(%s), nuh_layer_id: %d, temporal_id: %d\n",
++           nal->type, hevc_nal_unit_name(nal->type), nuh_layer_id, nal->temporal_id);
++
++    return nuh_layer_id == 0;
++}
++
++static int h264_parse_nal_header(H2645NAL *nal, void *logctx)
++{
++    GetBitContext *gb = &nal->gb;
++    char *src;
++    char *dst;
++    unsigned int si, di;
++    int removed_bytes = 0;
++    unsigned int length = 0;
++
++    if (get_bits1(gb) != 0)
++        return AVERROR_INVALIDDATA;
++
++    nal->ref_idc = get_bits(gb, 2);
++    nal->type    = get_bits(gb, 5);
++
++    if(nal->type != H264_NAL_SLICE && nal->type != H264_NAL_IDR_SLICE) {
++	    si = di = 0;
++	    src = dst = (char*)nal->data;
++	    length = nal->size;
++	    while (si + 2 < length) {
++		    // remove escapes (very rare 1:2^22)
++		    if (src[si + 2] > 3) {
++			    dst[di++] = src[si++];
++			    dst[di++] = src[si++];
++		    } else if (src[si] == 0 && src[si + 1] == 0 && src[si + 2] == 3) {
++				    dst[di++] = 0;
++				    dst[di++] = 0;
++				    si       += 3;
++		    }
++		    dst[di++] = src[si++];
++	    }
++
++	    while (si < length)
++		    dst[di++] = src[si++];
++
++        removed_bytes = si - di;
++
++        nal->size -= removed_bytes;
++
++    }
++
++    av_log(logctx, AV_LOG_DEBUG,
++           "nal_unit_type: %d(%s), nal_ref_idc: %d\n",
++           nal->type, h264_nal_unit_name(nal->type), nal->ref_idc);
++
++    return 1;
++}
++
++static int find_next_start_code(const uint8_t *buf, const uint8_t *next_avc)
++{
++    int i = 0;
++
++    if (buf + 3 >= next_avc)
++        return next_avc - buf;
++
++    while (buf + i + 3 < next_avc) {
++        if (buf[i] == 0 && buf[i + 1] == 0 && buf[i + 2] == 1)
++            break;
++        i++;
++    }
++    return i + 3;
++}
++
++extern void hexdump(unsigned char *buf, int len);
++
++int ff_h2645_packet_split(H2645Packet *pkt, const uint8_t *buf, int length,
++                          void *logctx, int is_nalff, int nal_length_size,
++                          int small_padding)
++{
++    GetByteContext bc;
++    int consumed, ret = 0;
++    int next_avc = is_nalff ? 0 : length; //如果nal时全FF, 说明没有下一个avc， �则下一个avc就是buffer的长度??
++    int64_t padding = small_padding ? 0 : MAX_MBPAIR_SIZE;
++
++    /* buffer是输入的原始��.*/
++    bytestream2_init(&bc, buf, length);
++
++
++    pkt->nb_nals = 0;
++    while (bytestream2_get_bytes_left(&bc) >= 4) {
++        H2645NAL *nal;
++        int extract_length = 0;
++        int skip_trailing_zeros = 1;
++
++	int buf_index;
++
++	if (bytestream2_tell(&bc) > next_avc)
++		av_log(logctx, AV_LOG_WARNING, "Exceeded next NALFF position, re-syncing.\n");
++
++	buf_index = find_next_start_code(bc.buffer, buf + next_avc);
++
++	bytestream2_skip(&bc, buf_index);
++
++	if (!bytestream2_get_bytes_left(&bc)) {
++		if (pkt->nb_nals > 0) {
++			// No more start codes: we discarded some irrelevant
++			// bytes at the end of the packet.
++			return 0;
++		} else {
++			av_log(logctx, AV_LOG_ERROR, "No start code is found.\n");
++			return AVERROR_INVALIDDATA;
++		}
++	}
++
++	extract_length = FFMIN(bytestream2_get_bytes_left(&bc), next_avc - bytestream2_tell(&bc));
++
++	if (bytestream2_tell(&bc) >= next_avc) {
++		/* skip to the start of the next NAL */
++		bytestream2_skip(&bc, next_avc - bytestream2_tell(&bc));
++		continue;
++	}
++
++	if (pkt->nals_allocated < pkt->nb_nals + 1) {
++		int new_size = pkt->nals_allocated + 1;
++		void *tmp = av_realloc_array(pkt->nals, new_size, sizeof(*pkt->nals));
++
++		if (!tmp)
++			return AVERROR(ENOMEM);
++
++		if(new_size > MAX_NALS_PER_PACKET) {
++			av_log(logctx, AV_LOG_WARNING,
++					"Too Many nals (%d) in one packet, max is (%d)\n",
++					new_size, MAX_NALS_PER_PACKET);
++			return AVERROR(ENOMEM);
++		}
++
++		pkt->nals = tmp;
++		memset(pkt->nals + pkt->nals_allocated, 0,
++				(new_size - pkt->nals_allocated) * sizeof(*pkt->nals));
++
++		nal = &pkt->nals[pkt->nb_nals];
++#if 0
++		nal->skipped_bytes_pos_size = 1024; // initial buffer size
++		nal->skipped_bytes_pos = av_malloc_array(nal->skipped_bytes_pos_size, sizeof(*nal->skipped_bytes_pos));
++		if (!nal->skipped_bytes_pos)
++			return AVERROR(ENOMEM);
++#endif
++		pkt->nals_allocated = new_size;
++	}
++	nal = &pkt->nals[pkt->nb_nals];
++
++	/*�� rbsp, 并且去掉 0x000003 �列中的0x03. */
++	consumed = ff_h2645_extract_rbsp(bc.buffer, extract_length, nal, small_padding);
++	if (consumed < 0)
++		return consumed;
++
++	if (is_nalff && (extract_length != consumed) && extract_length)
++		av_log(logctx, AV_LOG_DEBUG,
++				"NALFF: Consumed only %d bytes instead of %d\n",
++				consumed, extract_length);
++
++#if 0
++	printk("----nal->data:%x, nal->size:%d\n", nal->data, nal->size);
++	hexdump(nal->data, 32);
++#endif
++
++	/* 解�出�的nal递增....*/
++
++	pkt->nb_nals++;
++
++	bytestream2_skip(&bc, consumed);
++
++	nal->size_bits = get_bit_length(nal, skip_trailing_zeros);
++
++	ret = init_get_bits(&nal->gb, nal->data, nal->size_bits);
++	if (ret < 0)
++		return ret;
++
++	ret = h264_parse_nal_header(nal, logctx);
++
++	if (ret <= 0 || nal->size <= 0 || nal->size_bits <= 0) {
++		if (ret < 0) {
++			av_log(logctx, AV_LOG_ERROR, "Invalid NAL unit %d, skipping.\n",
++					nal->type);
++		}
++		pkt->nb_nals--;
++	}
++    }
++
++    return 0;
++}
++
++
++void ff_h2645_packet_uninit(H2645Packet *pkt)
++{
++    int i;
++#if 0
++    for (i = 0; i < pkt->nals_allocated; i++) {
++        av_freep(&pkt->nals[i].skipped_bytes_pos);
++    }
++#endif
++    av_freep(&pkt->nals);
++    pkt->nals_allocated = 0;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_direct.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_direct.c
+new file mode 100644
+index 000000000..3c41fab78
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_direct.c
+@@ -0,0 +1,146 @@
++#include "avcodec.h"
++#include "h264dec.h"
++#include "h264_ps.h"
++
++static int get_scale_factor(H264SliceContext *sl,
++                            int poc, int poc1, int i)
++{
++    int poc0 = sl->ref_list[0][i].poc;
++    int64_t pocdiff = poc1 - (int64_t)poc0;
++    int td = av_clip_int8(pocdiff);
++
++    if (pocdiff != (int)pocdiff)
++        av_log(sl->h264->avctx, AV_LOG_WARNING, "pocdiff overflow\n");
++
++    if (td == 0 || sl->ref_list[0][i].parent->long_ref) {
++        return 256;
++    } else {
++        int64_t pocdiff0 = poc - (int64_t)poc0;
++        int tb = av_clip_int8(pocdiff0);
++        int tx = (16384 + (FFABS(td) >> 1)) / td;
++
++        if (pocdiff0 != (int)pocdiff0)
++            av_log(sl->h264->avctx, AV_LOG_DEBUG, "pocdiff0 overflow\n");
++
++        return av_clip_intp2((tb * tx + 32) >> 6, 10);
++    }
++}
++
++void ff_h264_direct_dist_scale_factor(const H264Context *const h,
++                                      H264SliceContext *sl)
++{
++    const int poc  = FIELD_PICTURE(h) ? h->cur_pic_ptr->field_poc[h->picture_structure == PICT_BOTTOM_FIELD]
++                                      : h->cur_pic_ptr->poc;
++    const int poc1 = sl->ref_list[1][0].poc;
++    int i, field;
++
++    if (FRAME_MBAFF(h))
++        for (field = 0; field < 2; field++) {
++            const int poc  = h->cur_pic_ptr->field_poc[field];
++            const int poc1 = sl->ref_list[1][0].parent->field_poc[field];
++            for (i = 0; i < 2 * sl->ref_count[0]; i++)
++                sl->dist_scale_factor_field[field][i ^ field] =
++                    get_scale_factor(sl, poc, poc1, i + 16);
++        }
++
++    for (i = 0; i < sl->ref_count[0]; i++)
++        sl->dist_scale_factor[i] = get_scale_factor(sl, poc, poc1, i);
++}
++
++static void fill_colmap(const H264Context *h, H264SliceContext *sl,
++                        int map[2][16 + 32], int list,
++                        int field, int colfield, int mbafi)
++{
++    H264Picture *const ref1 = sl->ref_list[1][0].parent;
++    int j, old_ref, rfield;
++    int start  = mbafi ? 16                       : 0;
++    int end    = mbafi ? 16 + 2 * sl->ref_count[0] : sl->ref_count[0];
++    int interl = mbafi || h->picture_structure != PICT_FRAME;
++
++    /* bogus; fills in for missing frames */
++    memset(map[list], 0, sizeof(map[list]));
++
++    for (rfield = 0; rfield < 2; rfield++) {
++        for (old_ref = 0; old_ref < ref1->ref_count[colfield][list]; old_ref++) {
++            int poc = ref1->ref_poc[colfield][list][old_ref];
++
++            if (!interl)
++                poc |= 3;
++            // FIXME: store all MBAFF references so this is not needed
++            else if (interl && (poc & 3) == 3)
++                poc = (poc & ~3) + rfield + 1;
++
++            for (j = start; j < end; j++) {
++                if (4 * sl->ref_list[0][j].parent->frame_num +
++                    (sl->ref_list[0][j].reference & 3) == poc) {
++                    int cur_ref = mbafi ? (j - 16) ^ field : j;
++                    if (ref1->mbaff)
++                        map[list][2 * old_ref + (rfield ^ field) + 16] = cur_ref;
++                    if (rfield == field || !interl)
++                        map[list][old_ref] = cur_ref;
++                    break;
++                }
++            }
++        }
++    }
++}
++
++void ff_h264_direct_ref_list_init(const H264Context *const h, H264SliceContext *sl)
++{
++    H264Ref *const ref1 = &sl->ref_list[1][0];
++    H264Picture *const cur = h->cur_pic_ptr;
++    int list, j, field;
++    int sidx     = (h->picture_structure & 1) ^ 1;
++    int ref1sidx = (ref1->reference      & 1) ^ 1;
++
++    for (list = 0; list < sl->list_count; list++) {
++        cur->ref_count[sidx][list] = sl->ref_count[list];
++        for (j = 0; j < sl->ref_count[list]; j++)
++            cur->ref_poc[sidx][list][j] = 4 * sl->ref_list[list][j].parent->frame_num +
++                                          (sl->ref_list[list][j].reference & 3);
++    }
++
++    if (h->picture_structure == PICT_FRAME) {
++        memcpy(cur->ref_count[1], cur->ref_count[0], sizeof(cur->ref_count[0]));
++        memcpy(cur->ref_poc[1],   cur->ref_poc[0],   sizeof(cur->ref_poc[0]));
++    }
++
++    if (h->current_slice == 0) {
++        cur->mbaff = FRAME_MBAFF(h);
++    } else {
++        av_assert0(cur->mbaff == FRAME_MBAFF(h));
++    }
++
++    sl->col_fieldoff = 0;
++
++    if (sl->list_count != 2 || !sl->ref_count[1])
++        return;
++
++    if (h->picture_structure == PICT_FRAME) {
++        int cur_poc  = h->cur_pic_ptr->poc;
++        int *col_poc = sl->ref_list[1][0].parent->field_poc;
++        if (col_poc[0] == INT_MAX && col_poc[1] == INT_MAX) {
++            av_log(h->avctx, AV_LOG_ERROR, "co located POCs unavailable\n");
++            sl->col_parity = 1;
++        } else
++            sl->col_parity = (FFABS(col_poc[0] - (int64_t)cur_poc) >=
++                              FFABS(col_poc[1] - (int64_t)cur_poc));
++        ref1sidx =
++        sidx     = sl->col_parity;
++    // FL -> FL & differ parity
++    } else if (!(h->picture_structure & sl->ref_list[1][0].reference) &&
++               !sl->ref_list[1][0].parent->mbaff) {
++        sl->col_fieldoff = 2 * sl->ref_list[1][0].reference - 3;
++    }
++
++    if (sl->slice_type_nos != AV_PICTURE_TYPE_B || sl->direct_spatial_mv_pred)
++        return;
++
++    for (list = 0; list < 2; list++) {
++        fill_colmap(h, sl, sl->map_col_to_list0, list, sidx, ref1sidx, 0);
++        if (FRAME_MBAFF(h))
++            for (field = 0; field < 2; field++)
++                fill_colmap(h, sl, sl->map_col_to_list0_field[field], list, field,
++                            field, 1);
++    }
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_parse.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_parse.c
+new file mode 100644
+index 000000000..7a6114537
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_parse.c
+@@ -0,0 +1,279 @@
++#include "bytestream.h"
++#include "get_bits.h"
++#include "golomb.h"
++#include "h264.h"
++#include "h264dec.h"
++#include "h264_parse.h"
++#include "h264_ps.h"
++
++int ff_h264_pred_weight_table(GetBitContext *gb, const SPS *sps,
++                              const int *ref_count, int slice_type_nos,
++                              H264PredWeightTable *pwt,
++                              int picture_structure, void *logctx)
++{
++    int list, i, j;
++    int luma_def, chroma_def;
++
++    pwt->use_weight             = 0;
++    pwt->use_weight_chroma      = 0;
++
++    pwt->luma_log2_weight_denom = get_ue_golomb(gb);
++    if (pwt->luma_log2_weight_denom > 7U) {
++        av_log(logctx, AV_LOG_ERROR, "luma_log2_weight_denom %d is out of range\n", pwt->luma_log2_weight_denom);
++        pwt->luma_log2_weight_denom = 0;
++    }
++    luma_def = 1 << pwt->luma_log2_weight_denom;
++
++    if (sps->chroma_format_idc) {
++        pwt->chroma_log2_weight_denom = get_ue_golomb(gb);
++        if (pwt->chroma_log2_weight_denom > 7U) {
++            av_log(logctx, AV_LOG_ERROR, "chroma_log2_weight_denom %d is out of range\n", pwt->chroma_log2_weight_denom);
++            pwt->chroma_log2_weight_denom = 0;
++        }
++        chroma_def = 1 << pwt->chroma_log2_weight_denom;
++    }
++
++    for (list = 0; list < 2; list++) {
++        pwt->luma_weight_flag[list]   = 0;
++        pwt->chroma_weight_flag[list] = 0;
++        for (i = 0; i < ref_count[list]; i++) {
++            int luma_weight_flag, chroma_weight_flag;
++
++            luma_weight_flag = get_bits1(gb);
++            if (luma_weight_flag) {
++                pwt->luma_weight[i][list][0] = get_se_golomb(gb);
++                pwt->luma_weight[i][list][1] = get_se_golomb(gb);
++                if ((int8_t)pwt->luma_weight[i][list][0] != pwt->luma_weight[i][list][0] ||
++                    (int8_t)pwt->luma_weight[i][list][1] != pwt->luma_weight[i][list][1])
++                    goto out_range_weight;
++                if (pwt->luma_weight[i][list][0] != luma_def ||
++                    pwt->luma_weight[i][list][1] != 0) {
++                    pwt->use_weight             = 1;
++                    pwt->luma_weight_flag[list] = 1;
++                }
++            } else {
++		if(luma_def > 127) {
++			luma_def = 127;
++		}
++                pwt->luma_weight[i][list][0] = luma_def;
++                pwt->luma_weight[i][list][1] = 0;
++            }
++
++            if (sps->chroma_format_idc) {
++                chroma_weight_flag = get_bits1(gb);
++                if (chroma_weight_flag) {
++                    int j;
++                    for (j = 0; j < 2; j++) {
++                        pwt->chroma_weight[i][list][j][0] = get_se_golomb(gb);
++                        pwt->chroma_weight[i][list][j][1] = get_se_golomb(gb);
++                        if ((int8_t)pwt->chroma_weight[i][list][j][0] != pwt->chroma_weight[i][list][j][0] ||
++                            (int8_t)pwt->chroma_weight[i][list][j][1] != pwt->chroma_weight[i][list][j][1]) {
++                            pwt->chroma_weight[i][list][j][0] = chroma_def;
++                            pwt->chroma_weight[i][list][j][1] = 0;
++                            goto out_range_weight;
++                        }
++                        if (pwt->chroma_weight[i][list][j][0] != chroma_def ||
++                            pwt->chroma_weight[i][list][j][1] != 0) {
++                            pwt->use_weight_chroma        = 1;
++                            pwt->chroma_weight_flag[list] = 1;
++                        }
++                    }
++                } else {
++                    int j;
++                    for (j = 0; j < 2; j++) {
++			if(chroma_def > 127) {
++				chroma_def = 127;
++			}
++                        pwt->chroma_weight[i][list][j][0] = chroma_def;
++                        pwt->chroma_weight[i][list][j][1] = 0;
++                    }
++                }
++            }
++
++            // for MBAFF
++            if (picture_structure == PICT_FRAME) {
++                pwt->luma_weight[16 + 2 * i][list][0] = pwt->luma_weight[16 + 2 * i + 1][list][0] = pwt->luma_weight[i][list][0];
++                pwt->luma_weight[16 + 2 * i][list][1] = pwt->luma_weight[16 + 2 * i + 1][list][1] = pwt->luma_weight[i][list][1];
++                if (sps->chroma_format_idc) {
++                    for (j = 0; j < 2; j++) {
++                        pwt->chroma_weight[16 + 2 * i][list][j][0] = pwt->chroma_weight[16 + 2 * i + 1][list][j][0] = pwt->chroma_weight[i][list][j][0];
++                        pwt->chroma_weight[16 + 2 * i][list][j][1] = pwt->chroma_weight[16 + 2 * i + 1][list][j][1] = pwt->chroma_weight[i][list][j][1];
++                    }
++                }
++            }
++        }
++        if (slice_type_nos != AV_PICTURE_TYPE_B)
++            break;
++    }
++    pwt->use_weight = pwt->use_weight || pwt->use_weight_chroma;
++    return 0;
++out_range_weight:
++    av_log(logctx, AV_LOG_WARNING, "Out of range weight");
++    return AVERROR_INVALIDDATA;
++}
++
++
++int ff_h264_parse_ref_count(int *plist_count, int ref_count[2],
++                            GetBitContext *gb, const PPS *pps,
++                            int slice_type_nos, int picture_structure, void *logctx)
++{
++    int list_count;
++    int num_ref_idx_active_override_flag;
++
++    // set defaults, might be overridden a few lines later
++    ref_count[0] = pps->ref_count[0];
++    ref_count[1] = pps->ref_count[1];
++
++    if (slice_type_nos != AV_PICTURE_TYPE_I) {
++        unsigned max[2];
++        max[0] = max[1] = picture_structure == PICT_FRAME ? 15 : 31;
++
++        num_ref_idx_active_override_flag = get_bits1(gb);
++
++        if (num_ref_idx_active_override_flag) {
++            ref_count[0] = get_ue_golomb(gb) + 1;
++            if (slice_type_nos == AV_PICTURE_TYPE_B) {
++                ref_count[1] = get_ue_golomb(gb) + 1;
++            } else
++                // full range is spec-ok in this case, even for frames
++                ref_count[1] = 1;
++        }
++
++        if (ref_count[0] - 1 > max[0] || ref_count[1] - 1 > max[1]) {
++            av_log(logctx, AV_LOG_ERROR, "reference overflow %u > %u or %u > %u\n",
++                   ref_count[0] - 1, max[0], ref_count[1] - 1, max[1]);
++            ref_count[0] = ref_count[1] = 0;
++            *plist_count = 0;
++            goto fail;
++        }
++
++        if (slice_type_nos == AV_PICTURE_TYPE_B)
++            list_count = 2;
++        else
++            list_count = 1;
++    } else {
++        list_count   = 0;
++        ref_count[0] = ref_count[1] = 0;
++    }
++
++    *plist_count = list_count;
++
++    return 0;
++fail:
++    *plist_count = 0;
++    ref_count[0] = 0;
++    ref_count[1] = 0;
++    return AVERROR_INVALIDDATA;
++}
++
++int ff_h264_init_poc(int pic_field_poc[2], int *pic_poc,
++                     const SPS *sps, H264POCContext *pc,
++                     int picture_structure, int nal_ref_idc)
++{
++    const int max_frame_num = 1 << sps->log2_max_frame_num;
++    int64_t field_poc[2];
++
++    pc->frame_num_offset = pc->prev_frame_num_offset;
++    if (pc->frame_num < pc->prev_frame_num)
++        pc->frame_num_offset += max_frame_num;
++
++    if (sps->poc_type == 0) {
++        const int max_poc_lsb = 1 << sps->log2_max_poc_lsb;
++
++        if (pc->poc_lsb < pc->prev_poc_lsb &&
++            pc->prev_poc_lsb - pc->poc_lsb >= max_poc_lsb / 2)
++            pc->poc_msb = pc->prev_poc_msb + max_poc_lsb;
++        else if (pc->poc_lsb > pc->prev_poc_lsb &&
++                 pc->prev_poc_lsb - pc->poc_lsb < -max_poc_lsb / 2)
++            pc->poc_msb = pc->prev_poc_msb - max_poc_lsb;
++        else
++            pc->poc_msb = pc->prev_poc_msb;
++        field_poc[0] =
++        field_poc[1] = pc->poc_msb + pc->poc_lsb;
++        if (picture_structure == PICT_FRAME)
++            field_poc[1] += pc->delta_poc_bottom;
++    } else if (sps->poc_type == 1) {
++        int abs_frame_num;
++        int64_t expected_delta_per_poc_cycle, expectedpoc;
++        int i;
++
++        if (sps->poc_cycle_length != 0)
++            abs_frame_num = pc->frame_num_offset + pc->frame_num;
++        else
++            abs_frame_num = 0;
++
++        if (nal_ref_idc == 0 && abs_frame_num > 0)
++            abs_frame_num--;
++
++        expected_delta_per_poc_cycle = 0;
++        for (i = 0; i < sps->poc_cycle_length; i++)
++            // FIXME integrate during sps parse
++            expected_delta_per_poc_cycle += sps->offset_for_ref_frame[i];
++
++        if (abs_frame_num > 0) {
++            int poc_cycle_cnt          = (abs_frame_num - 1) / sps->poc_cycle_length;
++            int frame_num_in_poc_cycle = (abs_frame_num - 1) % sps->poc_cycle_length;
++
++            expectedpoc = poc_cycle_cnt * expected_delta_per_poc_cycle;
++            for (i = 0; i <= frame_num_in_poc_cycle; i++)
++                expectedpoc = expectedpoc + sps->offset_for_ref_frame[i];
++        } else
++            expectedpoc = 0;
++
++        if (nal_ref_idc == 0)
++            expectedpoc = expectedpoc + sps->offset_for_non_ref_pic;
++
++        field_poc[0] = expectedpoc + pc->delta_poc[0];
++        field_poc[1] = field_poc[0] + sps->offset_for_top_to_bottom_field;
++
++        if (picture_structure == PICT_FRAME)
++            field_poc[1] += pc->delta_poc[1];
++    } else {
++        int poc = 2 * (pc->frame_num_offset + pc->frame_num);
++
++        if (!nal_ref_idc)
++            poc--;
++
++        field_poc[0] = poc;
++        field_poc[1] = poc;
++    }
++
++    if (   field_poc[0] != (int)field_poc[0]
++        || field_poc[1] != (int)field_poc[1])
++        return AVERROR_INVALIDDATA;
++
++    if (picture_structure != PICT_BOTTOM_FIELD)
++        pic_field_poc[0] = field_poc[0];
++    if (picture_structure != PICT_TOP_FIELD)
++        pic_field_poc[1] = field_poc[1];
++    *pic_poc = FFMIN(pic_field_poc[0], pic_field_poc[1]);
++
++    return 0;
++}
++
++/**
++ * Compute profile from profile_idc and constraint_set?_flags.
++ *
++ * @param sps SPS
++ *
++ * @return profile as defined by FF_PROFILE_H264_*
++ */
++int ff_h264_get_profile(const SPS *sps)
++{
++    int profile = sps->profile_idc;
++
++    switch (sps->profile_idc) {
++    case FF_PROFILE_H264_BASELINE:
++        // constraint_set1_flag set to 1
++        profile |= (sps->constraint_set_flags & 1 << 1) ? FF_PROFILE_H264_CONSTRAINED : 0;
++        break;
++    case FF_PROFILE_H264_HIGH_10:
++    case FF_PROFILE_H264_HIGH_422:
++    case FF_PROFILE_H264_HIGH_444_PREDICTIVE:
++        // constraint_set3_flag set to 1
++        profile |= (sps->constraint_set_flags & 1 << 3) ? FF_PROFILE_H264_INTRA : 0;
++        break;
++    }
++
++    return profile;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_picture.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_picture.c
+new file mode 100644
+index 000000000..5583bafaf
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_picture.c
+@@ -0,0 +1,56 @@
++#include "avassert.h"
++#include "avcodec.h"
++#include "h264dec.h"
++#include "h264data.h"
++#include "mpegutils.h"
++
++void ff_h264_unref_picture(H264Context *h, H264Picture *pic)
++{
++    if (!pic->f || !pic->f->buf[0])
++        return;
++
++}
++
++int ff_h264_ref_picture(H264Context *h, H264Picture *dst, H264Picture *src)
++{
++    int i;
++
++    for (i = 0; i < 2; i++)
++        dst->field_poc[i] = src->field_poc[i];
++
++    memcpy(dst->ref_poc,   src->ref_poc,   sizeof(src->ref_poc));
++    memcpy(dst->ref_count, src->ref_count, sizeof(src->ref_count));
++
++    dst->poc           = src->poc;
++    dst->frame_num     = src->frame_num;
++    dst->mmco_reset    = src->mmco_reset;
++    dst->long_ref      = src->long_ref;
++    dst->mbaff         = src->mbaff;
++    dst->field_picture = src->field_picture;
++    dst->reference     = src->reference;
++    dst->recovered     = src->recovered;
++    dst->invalid_gap   = src->invalid_gap;
++
++    return 0;
++}
++
++int ff_h264_field_end(H264Context *h, H264SliceContext *sl, int in_setup)
++{
++    int err = 0;
++    h->mb_y = 0;
++
++
++    if (in_setup || 1 /*|| !(avctx->active_thread_type & FF_THREAD_FRAME)*/) {
++        if (!h->droppable) {
++            err = ff_h264_execute_ref_pic_marking(h);
++            h->poc.prev_poc_msb = h->poc.poc_msb;
++            h->poc.prev_poc_lsb = h->poc.poc_lsb;
++        }
++        h->poc.prev_frame_num_offset = h->poc.frame_num_offset;
++        h->poc.prev_frame_num        = h->poc.frame_num;
++    }
++
++    h->current_slice = 0;
++
++    return err;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_ps.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_ps.c
+new file mode 100644
+index 000000000..6c5bc4c99
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_ps.c
+@@ -0,0 +1,779 @@
++#ifdef __KERNEL__
++#else
++#include <inttypes.h>
++#endif
++
++#include "mathops.h"
++#include "avcodec.h"
++#include "h264data.h"
++#include "h264_ps.h"
++#include "golomb.h"
++
++#define MIN_LOG2_MAX_FRAME_NUM    4
++
++#define EXTENDED_SAR       255
++
++static const uint8_t default_scaling4[2][16] = {
++    {  6, 13, 20, 28, 13, 20, 28, 32,
++      20, 28, 32, 37, 28, 32, 37, 42 },
++    { 10, 14, 20, 24, 14, 20, 24, 27,
++      20, 24, 27, 30, 24, 27, 30, 34 }
++};
++
++static const uint8_t default_scaling8[2][64] = {
++    {  6, 10, 13, 16, 18, 23, 25, 27,
++      10, 11, 16, 18, 23, 25, 27, 29,
++      13, 16, 18, 23, 25, 27, 29, 31,
++      16, 18, 23, 25, 27, 29, 31, 33,
++      18, 23, 25, 27, 29, 31, 33, 36,
++      23, 25, 27, 29, 31, 33, 36, 38,
++      25, 27, 29, 31, 33, 36, 38, 40,
++      27, 29, 31, 33, 36, 38, 40, 42 },
++    {  9, 13, 15, 17, 19, 21, 22, 24,
++      13, 13, 17, 19, 21, 22, 24, 25,
++      15, 17, 19, 21, 22, 24, 25, 27,
++      17, 19, 21, 22, 24, 25, 27, 28,
++      19, 21, 22, 24, 25, 27, 28, 30,
++      21, 22, 24, 25, 27, 28, 30, 32,
++      22, 24, 25, 27, 28, 30, 32, 33,
++      24, 25, 27, 28, 30, 32, 33, 35 }
++};
++
++/* maximum number of MBs in the DPB for a given level */
++static const int level_max_dpb_mbs[][2] = {
++    { 10, 396       },
++    { 11, 900       },
++    { 12, 2376      },
++    { 13, 2376      },
++    { 20, 2376      },
++    { 21, 4752      },
++    { 22, 8100      },
++    { 30, 8100      },
++    { 31, 18000     },
++    { 32, 20480     },
++    { 40, 32768     },
++    { 41, 32768     },
++    { 42, 34816     },
++    { 50, 110400    },
++    { 51, 184320    },
++    { 52, 184320    },
++};
++
++static inline int decode_hrd_parameters(GetBitContext *gb, AVCodecContext *avctx,
++                                        SPS *sps)
++{
++    int cpb_count, i;
++    cpb_count = get_ue_golomb_31(gb) + 1;
++
++    if (cpb_count > 32U) {
++        av_log(avctx, AV_LOG_ERROR, "cpb_count %d invalid\n", cpb_count);
++        return AVERROR_INVALIDDATA;
++    }
++
++    get_bits(gb, 4); /* bit_rate_scale */
++    get_bits(gb, 4); /* cpb_size_scale */
++    for (i = 0; i < cpb_count; i++) {
++        get_ue_golomb_long(gb); /* bit_rate_value_minus1 */
++        get_ue_golomb_long(gb); /* cpb_size_value_minus1 */
++        get_bits1(gb);          /* cbr_flag */
++    }
++    sps->initial_cpb_removal_delay_length = get_bits(gb, 5) + 1;
++    sps->cpb_removal_delay_length         = get_bits(gb, 5) + 1;
++    sps->dpb_output_delay_length          = get_bits(gb, 5) + 1;
++    sps->time_offset_length               = get_bits(gb, 5);
++    sps->cpb_cnt                          = cpb_count;
++    return 0;
++}
++
++static inline int decode_vui_parameters(GetBitContext *gb, AVCodecContext *avctx,
++                                        SPS *sps)
++{
++    int aspect_ratio_info_present_flag;
++    unsigned int aspect_ratio_idc;
++
++    aspect_ratio_info_present_flag = get_bits1(gb);
++
++    if (aspect_ratio_info_present_flag) {
++        aspect_ratio_idc = get_bits(gb, 8);
++        if (aspect_ratio_idc == EXTENDED_SAR) {
++            sps->sar.num = get_bits(gb, 16);
++            sps->sar.den = get_bits(gb, 16);
++        } else if (aspect_ratio_idc < FF_ARRAY_ELEMS(ff_h264_pixel_aspect)) {
++            sps->sar = ff_h264_pixel_aspect[aspect_ratio_idc];
++        } else {
++            av_log(avctx, AV_LOG_ERROR, "illegal aspect ratio\n");
++            return AVERROR_INVALIDDATA;
++        }
++    } else {
++        sps->sar.num =
++        sps->sar.den = 0;
++    }
++
++    if (get_bits1(gb))      /* overscan_info_present_flag */
++        get_bits1(gb);      /* overscan_appropriate_flag */
++
++    sps->video_signal_type_present_flag = get_bits1(gb);
++    if (sps->video_signal_type_present_flag) {
++        get_bits(gb, 3);                 /* video_format */
++        sps->full_range = get_bits1(gb); /* video_full_range_flag */
++
++        sps->colour_description_present_flag = get_bits1(gb);
++        if (sps->colour_description_present_flag) {
++            get_bits(gb, 8); /* colour_primaries */
++            get_bits(gb, 8); /* transfer_characteristics */
++            get_bits(gb, 8); /* matrix_coefficients */
++	
++#if 0
++            sps->color_primaries = get_bits(gb, 8); /* colour_primaries */
++            sps->color_trc       = get_bits(gb, 8); /* transfer_characteristics */
++            sps->colorspace      = get_bits(gb, 8); /* matrix_coefficients */
++            // Set invalid values to "unspecified"
++            if (!av_color_primaries_name(sps->color_primaries))
++                sps->color_primaries = AVCOL_PRI_UNSPECIFIED;
++            if (!av_color_transfer_name(sps->color_trc))
++                sps->color_trc = AVCOL_TRC_UNSPECIFIED;
++            if (!av_color_space_name(sps->colorspace))
++                sps->colorspace = AVCOL_SPC_UNSPECIFIED;
++#endif
++        }
++    }
++
++    /* chroma_location_info_present_flag */
++    if (get_bits1(gb)) {
++        /* chroma_sample_location_type_top_field */
++#if 0
++        avctx->chroma_sample_location = get_ue_golomb(gb) + 1;
++#else
++	get_ue_golomb(gb);
++#endif
++        get_ue_golomb(gb);  /* chroma_sample_location_type_bottom_field */
++    }
++
++    if (show_bits1(gb) && get_bits_left(gb) < 10) {
++        av_log(avctx, AV_LOG_WARNING, "Truncated VUI\n");
++        return 0;
++    }
++
++    sps->timing_info_present_flag = get_bits1(gb);
++    if (sps->timing_info_present_flag) {
++        unsigned num_units_in_tick = get_bits_long(gb, 32);
++        unsigned time_scale        = get_bits_long(gb, 32);
++        if (!num_units_in_tick || !time_scale) {
++            av_log(avctx, AV_LOG_ERROR,
++                   "time_scale/num_units_in_tick invalid or unsupported (%u/%u)\n",
++                   time_scale, num_units_in_tick);
++            sps->timing_info_present_flag = 0;
++        } else {
++            sps->num_units_in_tick = num_units_in_tick;
++            sps->time_scale = time_scale;
++        }
++        sps->fixed_frame_rate_flag = get_bits1(gb);
++    }
++
++    sps->nal_hrd_parameters_present_flag = get_bits1(gb);
++    if (sps->nal_hrd_parameters_present_flag)
++        if (decode_hrd_parameters(gb, avctx, sps) < 0)
++            return AVERROR_INVALIDDATA;
++    sps->vcl_hrd_parameters_present_flag = get_bits1(gb);
++    if (sps->vcl_hrd_parameters_present_flag)
++        if (decode_hrd_parameters(gb, avctx, sps) < 0)
++            return AVERROR_INVALIDDATA;
++    if (sps->nal_hrd_parameters_present_flag ||
++        sps->vcl_hrd_parameters_present_flag)
++        get_bits1(gb);     /* low_delay_hrd_flag */
++    sps->pic_struct_present_flag = get_bits1(gb);
++    if (!get_bits_left(gb))
++        return 0;
++    sps->bitstream_restriction_flag = get_bits1(gb);
++    if (sps->bitstream_restriction_flag) {
++        get_bits1(gb);     /* motion_vectors_over_pic_boundaries_flag */
++        get_ue_golomb(gb); /* max_bytes_per_pic_denom */
++        get_ue_golomb(gb); /* max_bits_per_mb_denom */
++        get_ue_golomb(gb); /* log2_max_mv_length_horizontal */
++        get_ue_golomb(gb); /* log2_max_mv_length_vertical */
++        sps->num_reorder_frames = get_ue_golomb(gb);
++        get_ue_golomb(gb); /*max_dec_frame_buffering*/
++
++        if (get_bits_left(gb) < 0) {
++            sps->num_reorder_frames         = 0;
++            sps->bitstream_restriction_flag = 0;
++        }
++
++        if (sps->num_reorder_frames > 16U
++            /* max_dec_frame_buffering || max_dec_frame_buffering > 16 */) {
++            av_log(avctx, AV_LOG_ERROR,
++                   "Clipping illegal num_reorder_frames %d\n",
++                   sps->num_reorder_frames);
++            sps->num_reorder_frames = 16;
++            return AVERROR_INVALIDDATA;
++        }
++    }
++
++    return 0;
++}
++
++static int decode_scaling_list(GetBitContext *gb, uint8_t *factors, int size,
++                                const uint8_t *jvt_list,
++                                const uint8_t *fallback_list)
++{
++    int i, last = 8, next = 8;
++    const uint8_t *scan = size == 16 ? ff_zigzag_scan : ff_zigzag_direct;
++    if (!get_bits1(gb)) /* matrix not written, we use the predicted one */
++        memcpy(factors, fallback_list, size * sizeof(uint8_t));
++    else
++        for (i = 0; i < size; i++) {
++            if (next) {
++                int v = get_se_golomb(gb);
++                if (v < -128 || v > 127) {
++                    av_log(NULL, AV_LOG_ERROR, "delta scale %d is invalid\n", v);
++                    return AVERROR_INVALIDDATA;
++                }
++                next = (last + v) & 0xff;
++            }
++            if (!i && !next) { /* matrix not written, we use the preset one */
++                memcpy(factors, jvt_list, size * sizeof(uint8_t));
++                break;
++            }
++            last = factors[scan[i]] = next ? next : last;
++        }
++    return 0;
++}
++
++/* returns non zero if the provided SPS scaling matrix has been filled */
++static int decode_scaling_matrices(GetBitContext *gb, const SPS *sps,
++                                    const PPS *pps, int is_sps,
++                                    uint8_t(*scaling_matrix4)[16],
++                                    uint8_t(*scaling_matrix8)[64])
++{
++    int fallback_sps = !is_sps && sps->scaling_matrix_present;
++    const uint8_t *fallback[4] = {
++        fallback_sps ? sps->scaling_matrix4[0] : default_scaling4[0],
++        fallback_sps ? sps->scaling_matrix4[3] : default_scaling4[1],
++        fallback_sps ? sps->scaling_matrix8[0] : default_scaling8[0],
++        fallback_sps ? sps->scaling_matrix8[3] : default_scaling8[1]
++    };
++    int ret = 0;
++    if (get_bits1(gb)) {
++        ret |= decode_scaling_list(gb, scaling_matrix4[0], 16, default_scaling4[0], fallback[0]);        // Intra, Y
++        ret |= decode_scaling_list(gb, scaling_matrix4[1], 16, default_scaling4[0], scaling_matrix4[0]); // Intra, Cr
++        ret |= decode_scaling_list(gb, scaling_matrix4[2], 16, default_scaling4[0], scaling_matrix4[1]); // Intra, Cb
++        ret |= decode_scaling_list(gb, scaling_matrix4[3], 16, default_scaling4[1], fallback[1]);        // Inter, Y
++        ret |= decode_scaling_list(gb, scaling_matrix4[4], 16, default_scaling4[1], scaling_matrix4[3]); // Inter, Cr
++        ret |= decode_scaling_list(gb, scaling_matrix4[5], 16, default_scaling4[1], scaling_matrix4[4]); // Inter, Cb
++        if (is_sps || pps->transform_8x8_mode) {
++            ret |= decode_scaling_list(gb, scaling_matrix8[0], 64, default_scaling8[0], fallback[2]); // Intra, Y
++            ret |= decode_scaling_list(gb, scaling_matrix8[3], 64, default_scaling8[1], fallback[3]); // Inter, Y
++            if (sps->chroma_format_idc == 3) {
++                ret |= decode_scaling_list(gb, scaling_matrix8[1], 64, default_scaling8[0], scaling_matrix8[0]); // Intra, Cr
++                ret |= decode_scaling_list(gb, scaling_matrix8[4], 64, default_scaling8[1], scaling_matrix8[3]); // Inter, Cr
++                ret |= decode_scaling_list(gb, scaling_matrix8[2], 64, default_scaling8[0], scaling_matrix8[1]); // Intra, Cb
++                ret |= decode_scaling_list(gb, scaling_matrix8[5], 64, default_scaling8[1], scaling_matrix8[4]); // Inter, Cb
++            }
++        }
++        if (!ret)
++            ret = is_sps;
++    }
++
++    return ret;
++}
++
++void ff_h264_ps_uninit(H264ParamSets *ps)
++{
++    int i;
++
++    ps->pps = NULL;
++    ps->sps = NULL;
++}
++
++int ff_h264_decode_seq_parameter_set(GetBitContext *gb, AVCodecContext *avctx,
++                                     H264ParamSets *ps, int ignore_truncation)
++{
++    int profile_idc, level_idc, constraint_set_flags = 0;
++    unsigned int sps_id;
++    int i, log2_max_frame_num_minus4;
++    SPS *sps;
++    int ret;
++
++    profile_idc           = get_bits(gb, 8);
++    constraint_set_flags |= get_bits1(gb) << 0;   // constraint_set0_flag
++    constraint_set_flags |= get_bits1(gb) << 1;   // constraint_set1_flag
++    constraint_set_flags |= get_bits1(gb) << 2;   // constraint_set2_flag
++    constraint_set_flags |= get_bits1(gb) << 3;   // constraint_set3_flag
++    constraint_set_flags |= get_bits1(gb) << 4;   // constraint_set4_flag
++    constraint_set_flags |= get_bits1(gb) << 5;   // constraint_set5_flag
++    skip_bits(gb, 2);                             // reserved_zero_2bits
++    level_idc = get_bits(gb, 8);
++    sps_id    = get_ue_golomb_31(gb);
++
++    if (sps_id >= MAX_SPS_COUNT) {
++        av_log(avctx, AV_LOG_ERROR, "sps_id %u out of range\n", sps_id);
++        goto fail;
++    }
++
++    sps = &ps->sps_list[sps_id];
++
++    sps->sps_id               = sps_id;
++    sps->time_offset_length   = 24;
++    sps->profile_idc          = profile_idc;
++    sps->constraint_set_flags = constraint_set_flags;
++    sps->level_idc            = level_idc;
++    sps->full_range           = -1;
++
++    memset(sps->scaling_matrix4, 16, sizeof(sps->scaling_matrix4));
++    memset(sps->scaling_matrix8, 16, sizeof(sps->scaling_matrix8));
++    sps->scaling_matrix_present = 0;
++//    sps->colorspace = 2; //AVCOL_SPC_UNSPECIFIED
++
++    if (sps->profile_idc == 100 ||  // High profile
++        sps->profile_idc == 110 ||  // High10 profile
++        sps->profile_idc == 122 ||  // High422 profile
++        sps->profile_idc == 244 ||  // High444 Predictive profile
++        sps->profile_idc ==  44 ||  // Cavlc444 profile
++        sps->profile_idc ==  83 ||  // Scalable Constrained High profile (SVC)
++        sps->profile_idc ==  86 ||  // Scalable High Intra profile (SVC)
++        sps->profile_idc == 118 ||  // Stereo High profile (MVC)
++        sps->profile_idc == 128 ||  // Multiview High profile (MVC)
++        sps->profile_idc == 138 ||  // Multiview Depth High profile (MVCD)
++        sps->profile_idc == 144) {  // old High444 profile
++        sps->chroma_format_idc = get_ue_golomb_31(gb);
++        if (sps->chroma_format_idc > 3U) {
++            av_log(avctx, AV_LOG_ERROR, "chroma_format_idc %u",
++                                  sps->chroma_format_idc);
++            goto fail;
++        } else if (sps->chroma_format_idc == 3) {
++            sps->residual_color_transform_flag = get_bits1(gb);
++            if (sps->residual_color_transform_flag) {
++                av_log(avctx, AV_LOG_ERROR, "separate color planes are not supported\n");
++                goto fail;
++            }
++        }
++        sps->bit_depth_luma   = get_ue_golomb(gb) + 8;
++        sps->bit_depth_chroma = get_ue_golomb(gb) + 8;
++        if (sps->bit_depth_chroma != sps->bit_depth_luma) {
++            av_log(avctx, AV_LOG_ERROR,
++                                  "Different chroma and luma bit depth");
++            goto fail;
++        }
++        if (sps->bit_depth_luma   < 8 || sps->bit_depth_luma   > 14 ||
++            sps->bit_depth_chroma < 8 || sps->bit_depth_chroma > 14) {
++            av_log(avctx, AV_LOG_ERROR, "illegal bit depth value (%d, %d)\n",
++                   sps->bit_depth_luma, sps->bit_depth_chroma);
++            goto fail;
++        }
++        sps->transform_bypass = get_bits1(gb);
++        ret = decode_scaling_matrices(gb, sps, NULL, 1,
++                                      sps->scaling_matrix4, sps->scaling_matrix8);
++        if (ret < 0)
++            goto fail;
++        sps->scaling_matrix_present |= ret;
++    } else {
++        sps->chroma_format_idc = 1;
++        sps->bit_depth_luma    = 8;
++        sps->bit_depth_chroma  = 8;
++    }
++
++    log2_max_frame_num_minus4 = get_ue_golomb(gb);
++    if (log2_max_frame_num_minus4 < MIN_LOG2_MAX_FRAME_NUM - 4 ||
++        log2_max_frame_num_minus4 > MAX_LOG2_MAX_FRAME_NUM - 4) {
++        av_log(avctx, AV_LOG_ERROR,
++               "log2_max_frame_num_minus4 out of range (0-12): %d\n",
++               log2_max_frame_num_minus4);
++        goto fail;
++    }
++    sps->log2_max_frame_num = log2_max_frame_num_minus4 + 4;
++
++    sps->poc_type = get_ue_golomb_31(gb);
++
++    if (sps->poc_type == 0) { // FIXME #define
++        unsigned t = get_ue_golomb(gb);
++        if (t>12) {
++            av_log(avctx, AV_LOG_ERROR, "log2_max_poc_lsb (%d) is out of range\n", t);
++            goto fail;
++        }
++        sps->log2_max_poc_lsb = t + 4;
++    } else if (sps->poc_type == 1) { // FIXME #define
++        sps->delta_pic_order_always_zero_flag = get_bits1(gb);
++        sps->offset_for_non_ref_pic           = get_se_golomb(gb);
++        sps->offset_for_top_to_bottom_field   = get_se_golomb(gb);
++        sps->poc_cycle_length                 = get_ue_golomb(gb);
++
++        if ((unsigned)sps->poc_cycle_length >=
++            FF_ARRAY_ELEMS(sps->offset_for_ref_frame)) {
++            av_log(avctx, AV_LOG_ERROR,
++                   "poc_cycle_length overflow %d\n", sps->poc_cycle_length);
++            goto fail;
++        }
++
++        for (i = 0; i < sps->poc_cycle_length; i++)
++            sps->offset_for_ref_frame[i] = get_se_golomb(gb);
++    } else if (sps->poc_type != 2) {
++        av_log(avctx, AV_LOG_ERROR, "illegal POC type %d\n", sps->poc_type);
++        goto fail;
++    }
++
++    sps->ref_frame_count = get_ue_golomb_31(gb);
++    if (sps->ref_frame_count > MAX_DELAYED_PIC_COUNT) {
++        av_log(avctx, AV_LOG_ERROR,
++               "too many reference frames %d\n", sps->ref_frame_count);
++        goto fail;
++    }
++    sps->gaps_in_frame_num_allowed_flag = get_bits1(gb);
++    sps->mb_width                       = get_ue_golomb(gb) + 1;
++    sps->mb_height                      = get_ue_golomb(gb) + 1;
++
++    sps->frame_mbs_only_flag = get_bits1(gb);
++
++    if (sps->mb_height >= INT_MAX / 2U) {
++        av_log(avctx, AV_LOG_ERROR, "height overflow\n");
++        goto fail;
++    }
++    sps->mb_height *= 2 - sps->frame_mbs_only_flag;
++
++    if (!sps->frame_mbs_only_flag)
++        sps->mb_aff = get_bits1(gb);
++    else
++        sps->mb_aff = 0;
++
++    if ((unsigned)sps->mb_width  >= INT_MAX / 16 ||
++        (unsigned)sps->mb_height >= INT_MAX / 16 || 0 ){
++        //av_image_check_size(16 * sps->mb_width,
++        //                    16 * sps->mb_height, 0, avctx)) {
++        av_log(avctx, AV_LOG_ERROR, "mb_width/height overflow\n");
++        goto fail;
++    }
++
++    sps->direct_8x8_inference_flag = get_bits1(gb);
++
++#ifndef ALLOW_INTERLACE
++    if (sps->mb_aff)
++        av_log(avctx, AV_LOG_ERROR,
++               "MBAFF support not included; enable it at compile-time.\n");
++#endif
++    sps->crop = get_bits1(gb);
++    if (sps->crop) {
++        unsigned int crop_left   = get_ue_golomb(gb);
++        unsigned int crop_right  = get_ue_golomb(gb);
++        unsigned int crop_top    = get_ue_golomb(gb);
++        unsigned int crop_bottom = get_ue_golomb(gb);
++        int width  = 16 * sps->mb_width;
++        int height = 16 * sps->mb_height;
++
++        if (avctx->flags2 & AV_CODEC_FLAG2_IGNORE_CROP) {
++            av_log(avctx, AV_LOG_DEBUG, "discarding sps cropping, original "
++                                           "values are l:%d r:%d t:%d b:%d\n",
++                   crop_left, crop_right, crop_top, crop_bottom);
++
++            sps->crop_left   =
++            sps->crop_right  =
++            sps->crop_top    =
++            sps->crop_bottom = 0;
++        } else {
++            int vsub   = (sps->chroma_format_idc == 1) ? 1 : 0;
++            int hsub   = (sps->chroma_format_idc == 1 ||
++                          sps->chroma_format_idc == 2) ? 1 : 0;
++            int step_x = 1 << hsub;
++            int step_y = (2 - sps->frame_mbs_only_flag) << vsub;
++
++            if (crop_left  > (unsigned)INT_MAX / 4 / step_x ||
++                crop_right > (unsigned)INT_MAX / 4 / step_x ||
++                crop_top   > (unsigned)INT_MAX / 4 / step_y ||
++                crop_bottom> (unsigned)INT_MAX / 4 / step_y ||
++                (crop_left + crop_right ) * step_x >= width ||
++                (crop_top  + crop_bottom) * step_y >= height
++            ) {
++                av_log(avctx, AV_LOG_ERROR, "crop values invalid %d %d %d %d / %d %d\n", crop_left, crop_right, crop_top, crop_bottom, width, height);
++                goto fail;
++            }
++
++            sps->crop_left   = crop_left   * step_x;
++            sps->crop_right  = crop_right  * step_x;
++            sps->crop_top    = crop_top    * step_y;
++            sps->crop_bottom = crop_bottom * step_y;
++        }
++    } else {
++        sps->crop_left   =
++        sps->crop_right  =
++        sps->crop_top    =
++        sps->crop_bottom =
++        sps->crop        = 0;
++    }
++
++    sps->vui_parameters_present_flag = get_bits1(gb);
++    if (sps->vui_parameters_present_flag) {
++        int ret = decode_vui_parameters(gb, avctx, sps);
++        if (ret < 0)
++            goto fail;
++    }
++
++    if (get_bits_left(gb) < 0) {
++        av_log(avctx, ignore_truncation ? AV_LOG_WARNING : AV_LOG_ERROR,
++               "Overread %s by %d bits\n", sps->vui_parameters_present_flag ? "VUI" : "SPS", -get_bits_left(gb));
++        if (!ignore_truncation)
++            goto fail;
++    }
++
++    /* if the maximum delay is not stored in the SPS, derive it based on the
++     * level */
++    if (!sps->bitstream_restriction_flag &&
++        (sps->ref_frame_count /*|| avctx->strict_std_compliance >= FF_COMPLIANCE_STRICT*/)) {
++        sps->num_reorder_frames = MAX_DELAYED_PIC_COUNT - 1;
++        for (i = 0; i < FF_ARRAY_ELEMS(level_max_dpb_mbs); i++) {
++            if (level_max_dpb_mbs[i][0] == sps->level_idc) {
++                sps->num_reorder_frames = FFMIN(level_max_dpb_mbs[i][1] / (sps->mb_width * sps->mb_height),
++                                                sps->num_reorder_frames);
++                break;
++            }
++        }
++    }
++
++    if (!sps->sar.den)
++        sps->sar.den = 1;
++
++    if (avctx->debug & FF_DEBUG_PICT_INFO) {
++        static const char csp[4][5] = { "Gray", "420", "422", "444" };
++        av_log(avctx, AV_LOG_DEBUG,
++               "sps:%u profile:%d/%d poc:%d ref:%d %dx%d %s %s crop:%u/%u/%u/%u %s %s %d/%d b%d reo:%d\n",
++               sps_id, sps->profile_idc, sps->level_idc,
++               sps->poc_type,
++               sps->ref_frame_count,
++               sps->mb_width, sps->mb_height,
++               sps->frame_mbs_only_flag ? "FRM" : (sps->mb_aff ? "MB-AFF" : "PIC-AFF"),
++               sps->direct_8x8_inference_flag ? "8B8" : "",
++               sps->crop_left, sps->crop_right,
++               sps->crop_top, sps->crop_bottom,
++               sps->vui_parameters_present_flag ? "VUI" : "",
++               csp[sps->chroma_format_idc],
++               sps->timing_info_present_flag ? sps->num_units_in_tick : 0,
++               sps->timing_info_present_flag ? sps->time_scale : 0,
++               sps->bit_depth_luma,
++               sps->bitstream_restriction_flag ? sps->num_reorder_frames : -1
++               );
++    }
++
++    return 0;
++
++fail:
++    return AVERROR_INVALIDDATA;
++}
++
++#if 0
++static void init_dequant8_coeff_table(PPS *pps, const SPS *sps)
++{
++    int i, j, q, x;
++    const int max_qp = 51 + 6 * (sps->bit_depth_luma - 8);
++
++    for (i = 0; i < 6; i++) {
++        pps->dequant8_coeff[i] = pps->dequant8_buffer[i];
++        for (j = 0; j < i; j++)
++            if (!memcmp(pps->scaling_matrix8[j], pps->scaling_matrix8[i],
++                        64 * sizeof(uint8_t))) {
++                pps->dequant8_coeff[i] = pps->dequant8_buffer[j];
++                break;
++            }
++        if (j < i)
++            continue;
++
++        for (q = 0; q < max_qp + 1; q++) {
++            int shift = ff_h264_quant_div6[q];
++            int idx   = ff_h264_quant_rem6[q];
++            for (x = 0; x < 64; x++)
++                pps->dequant8_coeff[i][q][(x >> 3) | ((x & 7) << 3)] =
++                    ((uint32_t)ff_h264_dequant8_coeff_init[idx][ff_h264_dequant8_coeff_init_scan[((x >> 1) & 12) | (x & 3)]] *
++                     pps->scaling_matrix8[i][x]) << shift;
++        }
++    }
++}
++
++static void init_dequant4_coeff_table(PPS *pps, const SPS *sps)
++{
++    int i, j, q, x;
++    const int max_qp = 51 + 6 * (sps->bit_depth_luma - 8);
++    for (i = 0; i < 6; i++) {
++        pps->dequant4_coeff[i] = pps->dequant4_buffer[i];
++        for (j = 0; j < i; j++)
++            if (!memcmp(pps->scaling_matrix4[j], pps->scaling_matrix4[i],
++                        16 * sizeof(uint8_t))) {
++                pps->dequant4_coeff[i] = pps->dequant4_buffer[j];
++                break;
++            }
++        if (j < i)
++            continue;
++
++        for (q = 0; q < max_qp + 1; q++) {
++            int shift = ff_h264_quant_div6[q] + 2;
++            int idx   = ff_h264_quant_rem6[q];
++            for (x = 0; x < 16; x++)
++                pps->dequant4_coeff[i][q][(x >> 2) | ((x << 2) & 0xF)] =
++                    ((uint32_t)ff_h264_dequant4_coeff_init[idx][(x & 1) + ((x >> 2) & 1)] *
++                     pps->scaling_matrix4[i][x]) << shift;
++        }
++    }
++}
++
++static void init_dequant_tables(PPS *pps, const SPS *sps)
++{
++    int i, x;
++    init_dequant4_coeff_table(pps, sps);
++    memset(pps->dequant8_coeff, 0, sizeof(pps->dequant8_coeff));
++
++    if (pps->transform_8x8_mode)
++        init_dequant8_coeff_table(pps, sps);
++    if (sps->transform_bypass) {
++        for (i = 0; i < 6; i++)
++            for (x = 0; x < 16; x++)
++                pps->dequant4_coeff[i][0][x] = 1 << 6;
++        if (pps->transform_8x8_mode)
++            for (i = 0; i < 6; i++)
++                for (x = 0; x < 64; x++)
++                    pps->dequant8_coeff[i][0][x] = 1 << 6;
++    }
++}
++#endif
++static void build_qp_table(PPS *pps, int t, int index, const int depth)
++{
++    int i;
++    const int max_qp = 51 + 6 * (depth - 8);
++    for (i = 0; i < max_qp + 1; i++)
++        pps->chroma_qp_table[t][i] =
++            ff_h264_chroma_qp[depth - 8][av_clip(i + index, 0, max_qp)];
++}
++
++static int more_rbsp_data_in_pps(const SPS *sps, void *logctx)
++{
++    int profile_idc = sps->profile_idc;
++
++    if ((profile_idc == 66 || profile_idc == 77 ||
++         profile_idc == 88) && (sps->constraint_set_flags & 7)) {
++        av_log(logctx, AV_LOG_VERBOSE,
++               "Current profile doesn't provide more RBSP data in PPS, skipping\n");
++        return 0;
++    }
++
++    return 1;
++}
++
++int ff_h264_decode_picture_parameter_set(GetBitContext *gb, AVCodecContext *avctx,
++                                         H264ParamSets *ps, int bit_length)
++{
++    const SPS *sps;
++    unsigned int pps_id = get_ue_golomb(gb);
++    PPS *pps;
++    int qp_bd_offset;
++    int bits_left;
++    int ret;
++
++    if (pps_id >= MAX_PPS_COUNT) {
++        av_log(avctx, AV_LOG_ERROR, "pps_id %u out of range\n", pps_id);
++        return AVERROR_INVALIDDATA;
++    }
++
++    pps = &ps->pps_list[pps_id];
++
++
++    pps->sps_id = get_ue_golomb_31(gb);
++    if ((unsigned)pps->sps_id >= MAX_SPS_COUNT ||
++        !&ps->sps_list[pps->sps_id]) {
++        av_log(avctx, AV_LOG_ERROR, "sps_id %u out of range, max: %u\n", pps->sps_id, MAX_SPS_COUNT);
++        ret = AVERROR_INVALIDDATA;
++        goto fail;
++    }
++    sps = &ps->sps_list[pps->sps_id];
++
++    if (sps->bit_depth_luma > 14) {
++        av_log(avctx, AV_LOG_ERROR,
++               "Invalid luma bit depth=%d\n",
++               sps->bit_depth_luma);
++        ret = AVERROR_INVALIDDATA;
++        goto fail;
++    } else if (sps->bit_depth_luma == 11 || sps->bit_depth_luma == 13) {
++        av_log(avctx, AV_LOG_ERROR,
++               "Unimplemented luma bit depth=%d",
++               sps->bit_depth_luma);
++        ret = AVERROR_PATCHWELCOME;
++        goto fail;
++    }
++
++    pps->cabac             = get_bits1(gb);
++    pps->pic_order_present = get_bits1(gb);
++    pps->slice_group_count = get_ue_golomb(gb) + 1;
++    if (pps->slice_group_count > 1) {
++        pps->mb_slice_group_map_type = get_ue_golomb(gb);
++        av_log(avctx, AV_LOG_ERROR, "FMO not supported\n");
++    }
++    pps->ref_count[0] = get_ue_golomb(gb) + 1;
++    pps->ref_count[1] = get_ue_golomb(gb) + 1;
++    if (pps->ref_count[0] - 1 > 32 - 1 || pps->ref_count[1] - 1 > 32 - 1) {
++        av_log(avctx, AV_LOG_ERROR, "reference overflow (pps)\n");
++        ret = AVERROR_INVALIDDATA;
++        goto fail;
++    }
++
++    qp_bd_offset = 6 * (sps->bit_depth_luma - 8);
++
++    pps->weighted_pred                        = get_bits1(gb);
++    pps->weighted_bipred_idc                  = get_bits(gb, 2);
++    pps->init_qp                              = get_se_golomb(gb) + 26U + qp_bd_offset;
++    pps->init_qs                              = get_se_golomb(gb) + 26U + qp_bd_offset;
++    pps->chroma_qp_index_offset[0]            = get_se_golomb(gb);
++    if (pps->chroma_qp_index_offset[0] < -12 || pps->chroma_qp_index_offset[0] > 12) {
++        ret = AVERROR_INVALIDDATA;
++        goto fail;
++    }
++
++    pps->deblocking_filter_parameters_present = get_bits1(gb);
++    pps->constrained_intra_pred               = get_bits1(gb);
++    pps->redundant_pic_cnt_present            = get_bits1(gb);
++
++    pps->transform_8x8_mode = 0;
++    memcpy(pps->scaling_matrix4, sps->scaling_matrix4,
++           sizeof(pps->scaling_matrix4));
++    memcpy(pps->scaling_matrix8, sps->scaling_matrix8,
++           sizeof(pps->scaling_matrix8));
++
++    bits_left = bit_length - get_bits_count(gb);
++    if (bits_left > 0 && more_rbsp_data_in_pps(sps, avctx)) {
++        pps->transform_8x8_mode = get_bits1(gb);
++        ret = decode_scaling_matrices(gb, sps, pps, 0,
++                                pps->scaling_matrix4, pps->scaling_matrix8);
++        if (ret < 0)
++            goto fail;
++        // second_chroma_qp_index_offset
++        pps->chroma_qp_index_offset[1] = get_se_golomb(gb);
++        if (pps->chroma_qp_index_offset[1] < -12 || pps->chroma_qp_index_offset[1] > 12) {
++            ret = AVERROR_INVALIDDATA;
++            goto fail;
++        }
++    } else {
++        pps->chroma_qp_index_offset[1] = pps->chroma_qp_index_offset[0];
++    }
++
++    build_qp_table(pps, 0, pps->chroma_qp_index_offset[0],
++                   sps->bit_depth_luma);
++    build_qp_table(pps, 1, pps->chroma_qp_index_offset[1],
++                   sps->bit_depth_luma);
++
++    //init_dequant_tables(pps, sps);
++
++    if (pps->chroma_qp_index_offset[0] != pps->chroma_qp_index_offset[1])
++        pps->chroma_qp_diff = 1;
++
++    if (avctx->debug & FF_DEBUG_PICT_INFO) {
++        av_log(avctx, AV_LOG_DEBUG,
++               "pps:%u sps:%u %s slice_groups:%d ref:%u/%u %s qp:%d/%d/%d/%d %s %s %s %s\n",
++               pps_id, pps->sps_id,
++               pps->cabac ? "CABAC" : "CAVLC",
++               pps->slice_group_count,
++               pps->ref_count[0], pps->ref_count[1],
++               pps->weighted_pred ? "weighted" : "",
++               pps->init_qp, pps->init_qs, pps->chroma_qp_index_offset[0], pps->chroma_qp_index_offset[1],
++               pps->deblocking_filter_parameters_present ? "LPAR" : "",
++               pps->constrained_intra_pred ? "CONSTR" : "",
++               pps->redundant_pic_cnt_present ? "REDU" : "",
++               pps->transform_8x8_mode ? "8x8DCT" : "");
++    }
++
++    return 0;
++
++fail:
++    return ret;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_refs.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_refs.c
+new file mode 100644
+index 000000000..39cff53d4
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_refs.c
+@@ -0,0 +1,948 @@
++#ifdef __KERNEL__
++#else
++#include <inttypes.h>
++#endif
++
++#include "avassert.h"
++#include "avcodec.h"
++#include "h264.h"
++#include "h264dec.h"
++#include "golomb.h"
++#include "mpegutils.h"
++
++
++static void pic_as_field(H264Ref *pic, const int parity)
++{
++    int i;
++    for (i = 0; i < FF_ARRAY_ELEMS(pic->data); ++i) {
++        if (parity == PICT_BOTTOM_FIELD)
++            pic->data[i]   += pic->linesize[i];
++        pic->reference      = parity;
++        pic->linesize[i] *= 2;
++    }
++    pic->poc = pic->parent->field_poc[parity == PICT_BOTTOM_FIELD];
++}
++
++static void ref_from_h264pic(H264Ref *dst, H264Picture *src)
++{
++    memcpy(dst->data,     src->f->data,     sizeof(dst->data));
++    memcpy(dst->linesize, src->f->linesize, sizeof(dst->linesize));
++    dst->reference = src->reference;
++    dst->poc       = src->poc;
++    dst->pic_id    = src->pic_id;
++    dst->parent = src;
++}
++
++static int split_field_copy(H264Ref *dest, H264Picture *src, int parity, int id_add)
++{
++    int match = !!(src->reference & parity);
++
++    if (match) {
++        ref_from_h264pic(dest, src);
++        if (parity != PICT_FRAME) {
++            pic_as_field(dest, parity);
++            dest->pic_id *= 2;
++            dest->pic_id += id_add;
++        }
++    }
++
++    return match;
++}
++
++static int build_def_list(H264Ref *def, int def_len,
++                          H264Picture * const *in, int len, int is_long, int sel)
++{
++    int  i[2] = { 0 };
++    int index = 0;
++
++    while (i[0] < len || i[1] < len) {
++
++	    /*直到 创建的个数大于len? 或者in[]picture存在并且 两个的帧类型相�?*/
++        while (i[0] < len && !(in[i[0]] && (in[i[0]]->reference & sel)))
++            i[0]++;
++        while (i[1] < len && !(in[i[1]] && (in[i[1]]->reference & (sel ^ 3))))
++            i[1]++;
++        if (i[0] < len) {
++            av_assert0(index < def_len);
++            in[i[0]]->pic_id = is_long ? i[0] : in[i[0]]->frame_num;
++            split_field_copy(&def[index++], in[i[0]++], sel, 1);
++        }
++        if (i[1] < len) {
++            av_assert0(index < def_len);
++            in[i[1]]->pic_id = is_long ? i[1] : in[i[1]]->frame_num;
++            split_field_copy(&def[index++], in[i[1]++], sel ^ 3, 0);
++        }
++    }
++
++    return index;
++}
++
++static int add_sorted(H264Picture **sorted, H264Picture * const *src,
++                      int len, int limit, int dir)
++{
++    int i, best_poc;
++    int out_i = 0;
++
++    for (;;) {
++        best_poc = dir ? INT_MIN : INT_MAX;
++
++        for (i = 0; i < len; i++) {
++            const int poc = src[i]->poc;
++            if (((poc > limit) ^ dir) && ((poc < best_poc) ^ dir)) {
++                best_poc      = poc;
++                sorted[out_i] = src[i];
++            }
++        }
++        if (best_poc == (dir ? INT_MIN : INT_MAX))
++            break;
++        limit = sorted[out_i++]->poc - dir;
++    }
++    return out_i;
++}
++
++static int mismatches_ref(const H264Context *h, const H264Picture *pic)
++{
++    const AVFrame *f = pic->f;
++    return (h->cur_pic_ptr->f->width  != f->width ||
++            h->cur_pic_ptr->f->height != f->height ||
++            h->cur_pic_ptr->f->format != f->format);
++}
++
++static void h264_initialise_ref_list(H264Context *h, H264SliceContext *sl)
++{
++    int i, len;
++    int j;
++
++    if (sl->slice_type_nos == AV_PICTURE_TYPE_B) {
++        H264Picture *sorted[32];
++        int cur_poc, list;
++        int lens[2];
++
++	/*mbaff �帧场��自适应。*/
++	/*如果时场图片，*/
++        if (FIELD_PICTURE(h))
++            cur_poc = h->cur_pic_ptr->field_poc[h->picture_structure == PICT_BOTTOM_FIELD];
++        else
++            cur_poc = h->cur_pic_ptr->poc;
++
++	/*
++	 * 两个链表
++	 * list0 是��预测
++	 * list1 是��预测 �有B帧�会有list1。
++	 *
++	 * 根�pic_order_count�计算???
++	 *
++	 * */
++        for (list = 0; list < 2; list++) {
++            len  = add_sorted(sorted,       h->short_ref, h->short_ref_count, cur_poc, 1 ^ list);
++            len += add_sorted(sorted + len, h->short_ref, h->short_ref_count, cur_poc, 0 ^ list);
++            av_assert0(len <= 32);
++
++	    /*构建短的�考列表*/
++            len  = build_def_list(sl->ref_list[list], FF_ARRAY_ELEMS(sl->ref_list[0]),
++                                  sorted, len, 0, h->picture_structure);
++	    /*长�考*/
++            len += build_def_list(sl->ref_list[list] + len,
++                                  FF_ARRAY_ELEMS(sl->ref_list[0]) - len,
++                                  h->long_ref, 16, 1, h->picture_structure);
++            av_assert0(len <= 32);
++
++            if (len < sl->ref_count[list])
++                memset(&sl->ref_list[list][len], 0, sizeof(H264Ref) * (sl->ref_count[list] - len));
++            lens[list] = len;
++        }
++
++        if (lens[0] == lens[1] && lens[1] > 1) {
++            for (i = 0; i < lens[0] &&
++                        sl->ref_list[0][i].parent->f->buf[0]->buffer ==
++                        sl->ref_list[1][i].parent->f->buf[0]->buffer; i++);
++            if (i == lens[0]) {
++                FFSWAP(H264Ref, sl->ref_list[1][0], sl->ref_list[1][1]);
++            }
++        }
++    } else {
++	    /* 构建默认的 ref_list[0] 的短�考帧*/
++	    /*ref_list 是最终�过排�的�考列表, 短期�考帧和长期�考帧. */
++	    /* 这里h->short_ref_count�能为0，比如当�slice是IDR帧, 或者mmco_reset �求���考列表时.
++	     *
++	     * 这里的short_ref与long_ref对应的是截至到上一帧，被用于标记的�考帧内容.
++	     * 这里主�是�将short_ref放入到ref_list当中. 为什么�能直接放入呢？？？？？？
++	     *
++	     * */
++        len  = build_def_list(sl->ref_list[0], FF_ARRAY_ELEMS(sl->ref_list[0]),
++                              h->short_ref, h->short_ref_count, 0, h->picture_structure);
++
++	/*长�考*/
++        len += build_def_list(sl->ref_list[0] + len,
++                              FF_ARRAY_ELEMS(sl->ref_list[0]) - len,
++                              h-> long_ref, 16, 1, h->picture_structure);
++        av_assert0(len <= 32);
++
++	/*如果构建的长度大于解�出�的ref_count， 将len到ref_count的内容清零：====》 ��了�???*/
++	/*�考列表中剩余的信�清零.*/
++
++        if (len < sl->ref_count[0])
++            memset(&sl->ref_list[0][len], 0, sizeof(H264Ref) * (sl->ref_count[0] - len));
++    }
++#ifdef TRACE
++    for (i = 0; i < sl->ref_count[0]; i++) {
++        ff_tlog(h->avctx, "List0: %s fn:%d 0x%p\n",
++                (sl->ref_list[0][i].parent ? (sl->ref_list[0][i].parent->long_ref ? "LT" : "ST") : "??"),
++                sl->ref_list[0][i].pic_id,
++                sl->ref_list[0][i].data[0]);
++    }
++    if (sl->slice_type_nos == AV_PICTURE_TYPE_B) {
++        for (i = 0; i < sl->ref_count[1]; i++) {
++            ff_tlog(h->avctx, "List1: %s fn:%d 0x%p\n",
++                    (sl->ref_list[1][i].parent ? (sl->ref_list[1][i].parent->long_ref ? "LT" : "ST") : "??"),
++                    sl->ref_list[1][i].pic_id,
++                    sl->ref_list[1][i].data[0]);
++        }
++    }
++#endif
++
++    for (j = 0; j<1+(sl->slice_type_nos == AV_PICTURE_TYPE_B); j++) {
++        for (i = 0; i < sl->ref_count[j]; i++) {
++            if (sl->ref_list[j][i].parent) {
++                if (mismatches_ref(h, sl->ref_list[j][i].parent)) {
++                    av_log(h->avctx, AV_LOG_ERROR, "Discarding mismatching reference\n");
++                    memset(&sl->ref_list[j][i], 0, sizeof(sl->ref_list[j][i]));
++                }
++            }
++        }
++    }
++    /*默认�考0�？？？*/
++    for (i = 0; i < sl->list_count; i++)
++        h->default_ref[i] = sl->ref_list[i][0];
++}
++
++/**
++ * print short term list
++ */
++static void print_short_term(const H264Context *h)
++{
++    uint32_t i;
++    if (h->avctx->debug & FF_DEBUG_MMCO) {
++        av_log(h->avctx, AV_LOG_DEBUG, "short term list:\n");
++        for (i = 0; i < h->short_ref_count; i++) {
++            H264Picture *pic = h->short_ref[i];
++            av_log(h->avctx, AV_LOG_DEBUG, "%u fn:%d poc:%d %p\n",
++                   i, pic->frame_num, pic->poc, pic->f->data[0]);
++        }
++    }
++}
++
++/**
++ * print long term list
++ */
++static void print_long_term(const H264Context *h)
++{
++    uint32_t i;
++    if (h->avctx->debug & FF_DEBUG_MMCO) {
++        av_log(h->avctx, AV_LOG_DEBUG, "long term list:\n");
++        for (i = 0; i < 16; i++) {
++            H264Picture *pic = h->long_ref[i];
++            if (pic) {
++                av_log(h->avctx, AV_LOG_DEBUG, "%u fn:%d poc:%d %p\n",
++                       i, pic->frame_num, pic->poc, pic->f->data[0]);
++            }
++        }
++    }
++}
++
++/**
++ * Extract structure information about the picture described by pic_num in
++ * the current decoding context (frame or field). Note that pic_num is
++ * picture number without wrapping (so, 0<=pic_num<max_pic_num).
++ * @param pic_num picture number for which to extract structure information
++ * @param structure one of PICT_XXX describing structure of picture
++ *                      with pic_num
++ * @return frame number (short term) or long term index of picture
++ *         described by pic_num
++ */
++static int pic_num_extract(const H264Context *h, int pic_num, int *structure)
++{
++    *structure = h->picture_structure;
++
++    /* ��的方法是
++     * 如果当�图片为场图片，如果pic_num为�数 ---> 修改类型为 PICT_FIELD_XXX??
++     *
++     *
++     * */
++    if (FIELD_PICTURE(h)) {
++        if (!(pic_num & 1))
++            /* opposite field */
++            *structure ^= PICT_FRAME;
++        pic_num >>= 1;
++    }
++
++    return pic_num;
++}
++
++static void h264_fill_mbaff_ref_list(H264SliceContext *sl)
++{
++    int list, i, j;
++    for (list = 0; list < sl->list_count; list++) {
++        for (i = 0; i < sl->ref_count[list]; i++) {
++            H264Ref *frame = &sl->ref_list[list][i];
++            H264Ref *field = &sl->ref_list[list][16 + 2 * i];
++
++            field[0] = *frame;
++
++            for (j = 0; j < 3; j++)
++                field[0].linesize[j] <<= 1;
++            field[0].reference = PICT_TOP_FIELD;
++            field[0].poc       = field[0].parent->field_poc[0];
++
++            field[1] = field[0];
++
++            for (j = 0; j < 3; j++)
++                field[1].data[j] += frame->parent->f->linesize[j];
++            field[1].reference = PICT_BOTTOM_FIELD;
++            field[1].poc       = field[1].parent->field_poc[1];
++        }
++    }
++}
++
++int ff_h264_build_ref_list(H264Context *h, H264SliceContext *sl)
++{
++    int list, index, pic_structure;
++
++    print_short_term(h);
++    print_long_term(h);
++
++    h264_initialise_ref_list(h, sl);
++
++    for (list = 0; list < sl->list_count; list++) {
++        int pred = sl->curr_pic_num;  // framenum
++
++	/* 根�slice_header里的list reordering 语法，�排�??*/
++        for (index = 0; index < sl->nb_ref_modifications[list]; index++) {
++		/*循环迭代，指导modification_of_pic_nums_idc == 3*/
++            unsigned int modification_of_pic_nums_idc = sl->ref_modifications[list][index].op;
++            unsigned int                          val = sl->ref_modifications[list][index].val;
++            unsigned int pic_id;
++            int i;
++            H264Picture *ref = NULL;
++
++            switch (modification_of_pic_nums_idc) {
++            case 0:
++            case 1: {
++
++		/*
++		 *   0: 短期�考帧�排�， abs_diff_pic_num_minus1会出现在��中，从当�图�的PicNum�去 (abs_diff_pic_num_minus1 + 1) �指明需��排�的图�。
++		 *   1: 短期�考帧�排�， abs_diff_pic_num_minus1会出现在��中，从当�图�的PicNum加上 (abs_diff_pic_num_minus1 + 1) �指明需��排�的图�。
++		 *   2: 长期�考帧�排�， long_term_pic_num会出现在��中，指明需��排�的图�。
++		 *   3: 结�循环，退出�排��作。
++		 *
++		 * */
++
++                const unsigned int abs_diff_pic_num = val + 1;
++                int frame_num;
++
++                if (abs_diff_pic_num > sl->max_pic_num) {
++                    av_log(h->avctx, AV_LOG_ERROR,
++                           "abs_diff_pic_num overflow\n");
++                    return AVERROR_INVALIDDATA;
++                }
++
++
++                if (modification_of_pic_nums_idc == 0)
++                    pred -= abs_diff_pic_num;
++                else
++                    pred += abs_diff_pic_num;
++
++		/* pred 已�修改为需�冲排�的图�了.. */
++
++		/* 指明需��排�的图�. round(sl->max_pic_num) */
++                pred &= sl->max_pic_num - 1;
++
++		/*根�修改�的pred��其frame_num， 帧�.*/
++                frame_num = pic_num_extract(h, pred, &pic_structure);
++
++		/*�历短期�考帧列表*/
++                for (i = h->short_ref_count - 1; i >= 0; i--) {
++                    ref = h->short_ref[i];
++                    assert(ref->reference);
++                    assert(!ref->long_ref);
++		    /*如果计算出�的frame_num在短期�考列表中，并且？？*/
++                    if (ref->frame_num == frame_num &&
++                        (ref->reference & pic_structure))
++                        break;
++                }
++
++		/*如果i >=0, 说明在short_ref中存在frame_num了?, 修改�考帧的pic_id为计算出�的pred.???? */
++
++		/*那么 ref->frame_num 什么时候修改呢？？？？？？？ */
++
++		/* frame_num 和 pic_id 的关系.........??*/
++
++		/* 这里的pic_id 为什么�是计算出�的poc?
++		 * 更新�考列表的pic_id????
++		 * */
++                if (i >= 0)
++                    ref->pic_id = pred;
++                break;
++            }
++            case 2: {
++                int long_idx;
++                pic_id = val; // long_term_pic_idx
++
++                long_idx = pic_num_extract(h, pic_id, &pic_structure);
++
++                if (long_idx > 31U) {
++                    av_log(h->avctx, AV_LOG_ERROR,
++                           "long_term_pic_idx overflow\n");
++                    return AVERROR_INVALIDDATA;
++                }
++                ref = h->long_ref[long_idx];
++                assert(!(ref && !ref->reference));
++                if (ref && (ref->reference & pic_structure)) {
++                    ref->pic_id = pic_id;
++                    assert(ref->long_ref);
++                    i = 0;
++                } else {
++                    i = -1;
++                }
++                break;
++            }
++            default:
++                av_assert0(0);
++            }
++
++            if (i < 0) {
++                av_log(h->avctx, AV_LOG_ERROR,
++                       "reference picture missing during reorder\n");
++                memset(&sl->ref_list[list][index], 0, sizeof(sl->ref_list[0][0])); // FIXME
++            } else {
++
++		    /*�历 �个list 的ref_count, ref_count是通过��解�出�的....*/
++
++                for (i = index; i + 1 < sl->ref_count[list]; i++) {
++
++			/*如果�个ref_list的parent存在， parent是个什么鬼？干什么用的？？*/
++
++			/* parent 应该时当�Ref所属的Pic？？？？*/
++
++			/*�知�为什么�parent。。。。*/
++			/*�考列表中对应的图片与当�的ref一致.*/
++                    if (sl->ref_list[list][i].parent &&
++                        ref->long_ref == sl->ref_list[list][i].parent->long_ref &&
++                        ref->pic_id   == sl->ref_list[list][i].pic_id)
++                        break;
++                }
++                for (; i > index; i--) {
++                    sl->ref_list[list][i] = sl->ref_list[list][i - 1];
++                }
++
++		/*填充修改ref_list的内容....*/
++		/*将对应的图片放到ref_list中.*/
++                ref_from_h264pic(&sl->ref_list[list][index], ref);
++                if (FIELD_PICTURE(h)) {
++                    pic_as_field(&sl->ref_list[list][index], pic_structure);
++                }
++            }
++        }
++    }
++
++    /*�历 ref_list， 有效性和default ref_list。？？？*/
++    for (list = 0; list < sl->list_count; list++) {
++        for (index = 0; index < sl->ref_count[list]; index++) {
++            if (   !sl->ref_list[list][index].parent
++                || (!FIELD_PICTURE(h) && (sl->ref_list[list][index].reference&3) != 3)) {
++                int i;
++                av_log(h->avctx, AV_LOG_ERROR, "Missing reference picture, default is %d\n", h->default_ref[list].poc);
++                for (i = 0; i < FF_ARRAY_ELEMS(h->last_pocs); i++)
++                    h->last_pocs[i] = INT_MIN;
++                if (h->default_ref[list].parent
++                    && !(!FIELD_PICTURE(h) && (h->default_ref[list].reference&3) != 3))
++                    sl->ref_list[list][index] = h->default_ref[list];
++                else
++                    return -1;
++            }
++           // av_assert0(av_buffer_get_ref_count(sl->ref_list[list][index].parent->f->buf[0]) > 0);
++        }
++    }
++
++    /*如果帧场自适应的，填充帧场自适应�考列表.*/
++    if (FRAME_MBAFF(h))
++        h264_fill_mbaff_ref_list(sl);
++
++    return 0;
++}
++
++int ff_h264_decode_ref_pic_list_reordering(H264SliceContext *sl, void *logctx)
++{
++    int list, index;
++
++    sl->nb_ref_modifications[0] = 0;
++    sl->nb_ref_modifications[1] = 0;
++
++    for (list = 0; list < sl->list_count; list++) {
++        if (!get_bits1(&sl->gb))    // ref_pic_list_modification_flag_l[01]
++            continue;
++
++        for (index = 0; ; index++) {
++            unsigned int op = get_ue_golomb_31(&sl->gb);
++
++            if (op == 3)
++                break;
++
++            if (index >= sl->ref_count[list]) {
++                av_log(logctx, AV_LOG_ERROR, "reference count overflow\n");
++                return AVERROR_INVALIDDATA;
++            } else if (op > 2) {
++                av_log(logctx, AV_LOG_ERROR,
++                       "illegal modification_of_pic_nums_idc %u\n",
++                       op);
++                return AVERROR_INVALIDDATA;
++            }
++            sl->ref_modifications[list][index].val = get_ue_golomb_long(&sl->gb);
++            sl->ref_modifications[list][index].op  = op;
++            sl->nb_ref_modifications[list]++;
++        }
++    }
++
++    return 0;
++}
++
++/**
++ * Mark a picture as no longer needed for reference. The refmask
++ * argument allows unreferencing of individual fields or the whole frame.
++ * If the picture becomes entirely unreferenced, but is being held for
++ * display purposes, it is marked as such.
++ * @param refmask mask of fields to unreference; the mask is bitwise
++ *                anded with the reference marking of pic
++ * @return non-zero if pic becomes entirely unreferenced (except possibly
++ *         for display purposes) zero if one of the fields remains in
++ *         reference
++ */
++static inline int unreference_pic(H264Context *h, H264Picture *pic, int refmask)
++{
++    int i;
++    if (pic->reference &= refmask) {
++        return 0;
++    } else {
++        for(i = 0; h->delayed_pic[i]; i++)
++            if(pic == h->delayed_pic[i]){
++                pic->reference = DELAYED_PIC_REF;
++                break;
++            }
++        return 1;
++    }
++}
++
++/**
++ * Find a H264Picture in the short term reference list by frame number.
++ * @param frame_num frame number to search for
++ * @param idx the index into h->short_ref where returned picture is found
++ *            undefined if no picture found.
++ * @return pointer to the found picture, or NULL if no pic with the provided
++ *                 frame number is found
++ */
++static H264Picture *find_short(H264Context *h, int frame_num, int *idx)
++{
++    int i;
++
++    for (i = 0; i < h->short_ref_count; i++) {
++        H264Picture *pic = h->short_ref[i];
++        if (h->avctx->debug & FF_DEBUG_MMCO)
++            av_log(h->avctx, AV_LOG_DEBUG, "%d %d %p\n", i, pic->frame_num, pic);
++        if (pic->frame_num == frame_num) {
++            *idx = i;
++            return pic;
++        }
++    }
++    return NULL;
++}
++
++/**
++ * Remove a picture from the short term reference list by its index in
++ * that list.  This does no checking on the provided index; it is assumed
++ * to be valid. Other list entries are shifted down.
++ * @param i index into h->short_ref of picture to remove.
++ */
++static void remove_short_at_index(H264Context *h, int i)
++{
++    assert(i >= 0 && i < h->short_ref_count);
++    h->short_ref[i] = NULL;
++    if (--h->short_ref_count)
++        memmove(&h->short_ref[i], &h->short_ref[i + 1],
++                (h->short_ref_count - i) * sizeof(H264Picture*));
++}
++
++/**
++ * @return the removed picture or NULL if an error occurs
++ */
++static H264Picture *remove_short(H264Context *h, int frame_num, int ref_mask)
++{
++    H264Picture *pic;
++    int i;
++
++    if (h->avctx->debug & FF_DEBUG_MMCO)
++        av_log(h->avctx, AV_LOG_DEBUG, "remove short %d count %d\n", frame_num, h->short_ref_count);
++
++    pic = find_short(h, frame_num, &i);
++    if (pic) {
++        if (unreference_pic(h, pic, ref_mask))
++            remove_short_at_index(h, i);
++    }
++
++    return pic;
++}
++
++/**
++ * Remove a picture from the long term reference list by its index in
++ * that list.
++ * @return the removed picture or NULL if an error occurs
++ */
++static H264Picture *remove_long(H264Context *h, int i, int ref_mask)
++{
++    H264Picture *pic;
++
++    pic = h->long_ref[i];
++    if (pic) {
++        if (unreference_pic(h, pic, ref_mask)) {
++            assert(h->long_ref[i]->long_ref == 1);
++            h->long_ref[i]->long_ref = 0;
++            h->long_ref[i]           = NULL;
++            h->long_ref_count--;
++        }
++    }
++
++    return pic;
++}
++
++void ff_h264_remove_all_refs(H264Context *h)
++{
++    int i;
++
++    for (i = 0; i < 16; i++) {
++        remove_long(h, i, 0);
++    }
++    assert(h->long_ref_count == 0);
++
++#if 0
++    /*使用short_ref当中的第一帧作为错误��的图片. 先�处�. */
++    if (h->short_ref_count && !h->last_pic_for_ec.f->data[0]) {
++        ff_h264_unref_picture(h, &h->last_pic_for_ec);
++        ff_h264_ref_picture(h, &h->last_pic_for_ec, h->short_ref[0]);
++    }
++#endif
++
++    for (i = 0; i < h->short_ref_count; i++) {
++        unreference_pic(h, h->short_ref[i], 0);
++        h->short_ref[i] = NULL;
++    }
++    h->short_ref_count = 0;
++
++    memset(h->default_ref, 0, sizeof(h->default_ref));
++}
++
++static void generate_sliding_window_mmcos(H264Context *h)
++{
++    MMCO *mmco = h->mmco;
++    int nb_mmco = 0;
++
++    if (h->short_ref_count &&
++        h->long_ref_count + h->short_ref_count >= h->ps.sps->ref_frame_count &&
++        !(FIELD_PICTURE(h) && !h->first_field && h->cur_pic_ptr->reference)) {
++        mmco[0].opcode        = MMCO_SHORT2UNUSED;
++        mmco[0].short_pic_num = h->short_ref[h->short_ref_count - 1]->frame_num;
++        nb_mmco               = 1;
++        if (FIELD_PICTURE(h)) {
++            mmco[0].short_pic_num *= 2;
++            mmco[1].opcode         = MMCO_SHORT2UNUSED;
++            mmco[1].short_pic_num  = mmco[0].short_pic_num + 1;
++            nb_mmco                = 2;
++        }
++    }
++
++    h->nb_mmco = nb_mmco;
++}
++
++int ff_h264_execute_ref_pic_marking(H264Context *h)
++{
++    MMCO *mmco = h->mmco;
++    int mmco_count;
++    int i, j;
++    int pps_ref_count[2] = {0};
++    int current_ref_assigned = 0, err = 0;
++    H264Picture *pic;
++
++    if (!h->ps.sps) {
++        av_log(h->avctx, AV_LOG_ERROR, "SPS is unset\n");
++        err = AVERROR_INVALIDDATA;
++        goto out;
++    }
++
++    /* �么使用滑动窗�标记，�么使用上�解�出�的mmco进行标记. */
++    if (!h->explicit_ref_marking)
++        generate_sliding_window_mmcos(h);
++    mmco_count = h->nb_mmco;
++
++    if ((h->avctx->debug & FF_DEBUG_MMCO) && mmco_count == 0)
++        av_log(h->avctx, AV_LOG_DEBUG, "no mmco here\n");
++
++    for (i = 0; i < mmco_count; i++) {
++        int structure, frame_num;
++        if (h->avctx->debug & FF_DEBUG_MMCO)
++            av_log(h->avctx, AV_LOG_DEBUG, "mmco:%d %d %d\n", h->mmco[i].opcode,
++                   h->mmco[i].short_pic_num, h->mmco[i].long_arg);
++
++        if (mmco[i].opcode == MMCO_SHORT2UNUSED ||
++            mmco[i].opcode == MMCO_SHORT2LONG) {
++            frame_num = pic_num_extract(h, mmco[i].short_pic_num, &structure);
++            pic       = find_short(h, frame_num, &j);
++            if (!pic) {
++                if (mmco[i].opcode != MMCO_SHORT2LONG ||
++                    !h->long_ref[mmco[i].long_arg]    ||
++                    h->long_ref[mmco[i].long_arg]->frame_num != frame_num) {
++                    av_log(h->avctx, h->short_ref_count ? AV_LOG_ERROR : AV_LOG_DEBUG, "mmco: unref short failure\n");
++                    err = AVERROR_INVALIDDATA;
++                }
++                continue;
++            }
++        }
++
++        switch (mmco[i].opcode) {
++        case MMCO_SHORT2UNUSED:
++            if (h->avctx->debug & FF_DEBUG_MMCO)
++                av_log(h->avctx, AV_LOG_DEBUG, "mmco: unref short %d count %d\n",
++                       h->mmco[i].short_pic_num, h->short_ref_count);
++            remove_short(h, frame_num, structure ^ PICT_FRAME);
++            break;
++        case MMCO_SHORT2LONG:
++                if (h->long_ref[mmco[i].long_arg] != pic)
++                    remove_long(h, mmco[i].long_arg, 0);
++
++                remove_short_at_index(h, j);
++                h->long_ref[ mmco[i].long_arg ] = pic;
++                if (h->long_ref[mmco[i].long_arg]) {
++                    h->long_ref[mmco[i].long_arg]->long_ref = 1;
++                    h->long_ref_count++;
++                }
++            break;
++        case MMCO_LONG2UNUSED:
++            j   = pic_num_extract(h, mmco[i].long_arg, &structure);
++            pic = h->long_ref[j];
++            if (pic) {
++                remove_long(h, j, structure ^ PICT_FRAME);
++            } else if (h->avctx->debug & FF_DEBUG_MMCO)
++                av_log(h->avctx, AV_LOG_DEBUG, "mmco: unref long failure\n");
++            break;
++        case MMCO_LONG:
++                    // Comment below left from previous code as it is an interesting note.
++                    /* First field in pair is in short term list or
++                     * at a different long term index.
++                     * This is not allowed; see 7.4.3.3, notes 2 and 3.
++                     * Report the problem and keep the pair where it is,
++                     * and mark this field valid.
++                     */
++            if (h->short_ref[0] == h->cur_pic_ptr) {
++                av_log(h->avctx, AV_LOG_ERROR, "mmco: cannot assign current picture to short and long at the same time\n");
++                remove_short_at_index(h, 0);
++            }
++
++            /* make sure the current picture is not already assigned as a long ref */
++            if (h->cur_pic_ptr->long_ref) {
++                for (j = 0; j < FF_ARRAY_ELEMS(h->long_ref); j++) {
++                    if (h->long_ref[j] == h->cur_pic_ptr) {
++                        if (j != mmco[i].long_arg)
++                            av_log(h->avctx, AV_LOG_ERROR, "mmco: cannot assign current picture to 2 long term references\n");
++                        remove_long(h, j, 0);
++                    }
++                }
++            }
++
++            if (h->long_ref[mmco[i].long_arg] != h->cur_pic_ptr) {
++                av_assert0(!h->cur_pic_ptr->long_ref);
++                remove_long(h, mmco[i].long_arg, 0);
++
++                h->long_ref[mmco[i].long_arg]           = h->cur_pic_ptr;
++                h->long_ref[mmco[i].long_arg]->long_ref = 1;
++                h->long_ref_count++;
++            }
++
++            h->cur_pic_ptr->reference |= h->picture_structure;
++            current_ref_assigned = 1;
++            break;
++        case MMCO_SET_MAX_LONG:
++            assert(mmco[i].long_arg <= 16);
++            // just remove the long term which index is greater than new max
++            for (j = mmco[i].long_arg; j < 16; j++) {
++                remove_long(h, j, 0);
++            }
++            break;
++        case MMCO_RESET:
++            while (h->short_ref_count) {
++                remove_short(h, h->short_ref[0]->frame_num, 0);
++            }
++            for (j = 0; j < 16; j++) {
++                remove_long(h, j, 0);
++            }
++            h->poc.frame_num = h->cur_pic_ptr->frame_num = 0;
++            h->mmco_reset = 1;
++            h->cur_pic_ptr->mmco_reset = 1;
++            for (j = 0; j < MAX_DELAYED_PIC_COUNT; j++)
++                h->last_pocs[j] = INT_MIN;
++            break;
++        default: assert(0);
++        }
++    }
++
++    if (!current_ref_assigned) {
++        /* Second field of complementary field pair; the first field of
++         * which is already referenced. If short referenced, it
++         * should be first entry in short_ref. If not, it must exist
++         * in long_ref; trying to put it on the short list here is an
++         * error in the encoded bit stream (ref: 7.4.3.3, NOTE 2 and 3).
++         */
++        if (h->short_ref_count && h->short_ref[0] == h->cur_pic_ptr) {
++            /* Just mark the second field valid */
++            h->cur_pic_ptr->reference |= h->picture_structure;
++        } else if (h->cur_pic_ptr->long_ref) {
++            av_log(h->avctx, AV_LOG_ERROR, "illegal short term reference "
++                                           "assignment for second field "
++                                           "in complementary field pair "
++                                           "(first field is long term)\n");
++            err = AVERROR_INVALIDDATA;
++        } else {
++            pic = remove_short(h, h->cur_pic_ptr->frame_num, 0);
++            if (pic) {
++                av_log(h->avctx, AV_LOG_ERROR, "illegal short term buffer state detected\n");
++                err = AVERROR_INVALIDDATA;
++            }
++
++	    /*整体将short_ref往�移动一个�元, 将当�图�放入short_ref第一�*/
++            if (h->short_ref_count)
++                memmove(&h->short_ref[1], &h->short_ref[0],
++                        h->short_ref_count * sizeof(H264Picture*));
++
++            h->short_ref[0] = h->cur_pic_ptr;
++            h->short_ref_count++;
++            h->cur_pic_ptr->reference |= h->picture_structure;
++        }
++    }
++
++    if (h->long_ref_count + h->short_ref_count > FFMAX(h->ps.sps->ref_frame_count, 1)) {
++
++        /* We have too many reference frames, probably due to corrupted
++         * stream. Need to discard one frame. Prevents overrun of the
++         * short_ref and long_ref buffers.
++         */
++        av_log(h->avctx, AV_LOG_ERROR,
++               "number of reference frames (%d+%d) exceeds max (%d; probably "
++               "corrupt input), discarding one\n",
++               h->long_ref_count, h->short_ref_count, h->ps.sps->ref_frame_count);
++        err = AVERROR_INVALIDDATA;
++
++        if (h->long_ref_count && !h->short_ref_count) {
++            for (i = 0; i < 16; ++i)
++                if (h->long_ref[i])
++                    break;
++
++            assert(i < 16);
++            remove_long(h, i, 0);
++        } else {
++            pic = h->short_ref[h->short_ref_count - 1];
++            remove_short(h, pic->frame_num, 0);
++        }
++    }
++
++    for (i = 0; i<h->short_ref_count; i++) {
++        pic = h->short_ref[i];
++        if (pic->invalid_gap) {
++            int d = av_mod_uintp2(h->cur_pic_ptr->frame_num - pic->frame_num, h->ps.sps->log2_max_frame_num);
++            if (d > h->ps.sps->ref_frame_count)
++                remove_short(h, pic->frame_num, 0);
++        }
++    }
++
++    print_short_term(h);
++    print_long_term(h);
++
++    for (i = 0; i < FF_ARRAY_ELEMS(h->ps.pps_list); i++) {
++        if (&h->ps.pps_list[i]) {
++            const PPS *pps = &h->ps.pps_list[i];
++            pps_ref_count[0] = FFMAX(pps_ref_count[0], pps->ref_count[0]);
++            pps_ref_count[1] = FFMAX(pps_ref_count[1], pps->ref_count[1]);
++        }
++    }
++
++    // Detect unmarked random access points
++    if (   err >= 0
++        && h->long_ref_count==0
++        && (   h->short_ref_count<=2
++            || pps_ref_count[0] <= 2 && pps_ref_count[1] <= 1 && h->avctx->has_b_frames
++            || pps_ref_count[0] <= 1 + (h->picture_structure != PICT_FRAME) && pps_ref_count[1] <= 1)
++        && pps_ref_count[0]<=2 + (h->picture_structure != PICT_FRAME) + (2*!h->has_recovery_point)
++        && h->cur_pic_ptr->f->pict_type == AV_PICTURE_TYPE_I){
++        h->cur_pic_ptr->recovered |= 1;
++        if(!h->avctx->has_b_frames)
++            h->frame_recovered |= FRAME_RECOVERED_SEI;
++    }
++
++out:
++    return (h->avctx->err_recognition & AV_EF_EXPLODE) ? err : 0;
++}
++
++int ff_h264_decode_ref_pic_marking(H264SliceContext *sl, GetBitContext *gb,
++                                   const H2645NAL *nal, void *logctx)
++{
++    int i;
++    MMCO *mmco = sl->mmco;
++    int nb_mmco = 0;
++
++    if (nal->type == H264_NAL_IDR_SLICE) { // FIXME fields
++        skip_bits1(gb); // broken_link
++        if (get_bits1(gb)) {
++            mmco[0].opcode   = MMCO_LONG;
++            mmco[0].long_arg = 0;
++            nb_mmco          = 1;
++        }
++        sl->explicit_ref_marking = 1;
++    } else {
++        sl->explicit_ref_marking = get_bits1(gb);
++        if (sl->explicit_ref_marking) {
++            for (i = 0; i < MAX_MMCO_COUNT; i++) {
++                MMCOOpcode opcode = get_ue_golomb_31(gb);
++
++                mmco[i].opcode = opcode;
++                if (opcode == MMCO_SHORT2UNUSED || opcode == MMCO_SHORT2LONG) {
++                    mmco[i].short_pic_num =
++                        (sl->curr_pic_num - get_ue_golomb_long(gb) - 1) &
++                            (sl->max_pic_num - 1);
++                }
++                if (opcode == MMCO_SHORT2LONG || opcode == MMCO_LONG2UNUSED ||
++                    opcode == MMCO_LONG || opcode == MMCO_SET_MAX_LONG) {
++                    unsigned int long_arg = get_ue_golomb_31(gb);
++                    if (long_arg >= 32 ||
++                        (long_arg >= 16 && !(opcode == MMCO_SET_MAX_LONG &&
++                                             long_arg == 16) &&
++                         !(opcode == MMCO_LONG2UNUSED && FIELD_PICTURE(sl)))) {
++                        av_log(logctx, AV_LOG_ERROR,
++                               "illegal long ref in memory management control "
++                               "operation %d\n", opcode);
++                        return -1;
++                    }
++                    mmco[i].long_arg = long_arg;
++                }
++
++                if (opcode > (unsigned) MMCO_LONG) {
++                    av_log(logctx, AV_LOG_ERROR,
++                           "illegal memory management control operation %d\n",
++                           opcode);
++                    return -1;
++                }
++                if (opcode == MMCO_END)
++                    break;
++            }
++            nb_mmco = i;
++        }
++    }
++
++    sl->nb_mmco = nb_mmco;
++
++    return 0;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_sei.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_sei.c
+new file mode 100644
+index 000000000..3adc081b0
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_sei.c
+@@ -0,0 +1,508 @@
++#include "avcodec.h"
++#include "get_bits.h"
++#include "golomb.h"
++#include "h264_ps.h"
++#include "h264_sei.h"
++//#include "internal.h"
++
++#define AVERROR_PS_NOT_FOUND      FFERRTAG(0xF8,'?','P','S')
++
++static const uint8_t sei_num_clock_ts_table[9] = {
++    1, 1, 1, 2, 2, 3, 3, 2, 3
++};
++
++void ff_h264_sei_uninit(H264SEIContext *h)
++{
++    h->recovery_point.recovery_frame_cnt = -1;
++
++    h->picture_timing.dpb_output_delay  = 0;
++    h->picture_timing.cpb_removal_delay = -1;
++
++    h->picture_timing.present      = 0;
++    h->buffering_period.present    = 0;
++    h->frame_packing.present       = 0;
++    h->display_orientation.present = 0;
++    h->afd.present                 =  0;
++#if 0
++    av_buffer_unref(&h->a53_caption.buf_ref);
++#endif
++}
++
++static int decode_picture_timing(H264SEIPictureTiming *h, GetBitContext *gb,
++                                 const H264ParamSets *ps, void *logctx)
++{
++    int i;
++    const SPS *sps = ps->sps;
++
++    for (i = 0; i<MAX_SPS_COUNT; i++)
++        if ((!sps || !sps->log2_max_frame_num) && &ps->sps_list[i])
++	    sps = &ps->sps_list[i];
++           // sps = (const SPS *)ps->sps_list[i]->data;
++
++    if (!sps) {
++        av_log(logctx, AV_LOG_ERROR, "SPS unavailable in decode_picture_timing\n");
++        return AVERROR_PS_NOT_FOUND;
++    }
++
++    if (sps->nal_hrd_parameters_present_flag ||
++        sps->vcl_hrd_parameters_present_flag) {
++        h->cpb_removal_delay = get_bits_long(gb, sps->cpb_removal_delay_length);
++        h->dpb_output_delay  = get_bits_long(gb, sps->dpb_output_delay_length);
++    }
++    if (sps->pic_struct_present_flag) {
++        unsigned int i, num_clock_ts;
++
++        h->pic_struct = get_bits(gb, 4);
++        h->ct_type    = 0;
++
++        if (h->pic_struct > H264_SEI_PIC_STRUCT_FRAME_TRIPLING)
++            return AVERROR_INVALIDDATA;
++
++        num_clock_ts = sei_num_clock_ts_table[h->pic_struct];
++        h->timecode_cnt = 0;
++        for (i = 0; i < num_clock_ts; i++) {
++            if (get_bits(gb, 1)) {                      /* clock_timestamp_flag */
++                H264SEITimeCode *tc = &h->timecode[h->timecode_cnt++];
++                unsigned int full_timestamp_flag;
++                unsigned int counting_type, cnt_dropped_flag;
++                h->ct_type |= 1 << get_bits(gb, 2);
++                skip_bits(gb, 1);                       /* nuit_field_based_flag */
++                counting_type = get_bits(gb, 5);        /* counting_type */
++                full_timestamp_flag = get_bits(gb, 1);
++                skip_bits(gb, 1);                       /* discontinuity_flag */
++                cnt_dropped_flag = get_bits(gb, 1);      /* cnt_dropped_flag */
++                if (cnt_dropped_flag && counting_type > 1 && counting_type < 7)
++                    tc->dropframe = 1;
++                tc->frame = get_bits(gb, 8);         /* n_frames */
++                if (full_timestamp_flag) {
++                    tc->full = 1;
++                    tc->seconds = get_bits(gb, 6); /* seconds_value 0..59 */
++                    tc->minutes = get_bits(gb, 6); /* minutes_value 0..59 */
++                    tc->hours = get_bits(gb, 5);   /* hours_value 0..23 */
++                } else {
++                    tc->seconds = tc->minutes = tc->hours = tc->full = 0;
++                    if (get_bits(gb, 1)) {             /* seconds_flag */
++                        tc->seconds = get_bits(gb, 6);
++                        if (get_bits(gb, 1)) {         /* minutes_flag */
++                            tc->minutes = get_bits(gb, 6);
++                            if (get_bits(gb, 1))       /* hours_flag */
++                                tc->hours = get_bits(gb, 5);
++                        }
++                    }
++                }
++
++                if (sps->time_offset_length > 0)
++                    skip_bits(gb,
++                              sps->time_offset_length); /* time_offset */
++            }
++        }
++
++        av_log(logctx, AV_LOG_DEBUG, "ct_type:%X pic_struct:%d\n",
++               h->ct_type, h->pic_struct);
++    }
++
++    h->present = 1;
++    return 0;
++}
++
++static int decode_registered_user_data_afd(H264SEIAFD *h, GetBitContext *gb, int size)
++{
++    int flag;
++
++    if (size-- < 1)
++        return AVERROR_INVALIDDATA;
++    skip_bits(gb, 1);               // 0
++    flag = get_bits(gb, 1);         // active_format_flag
++    skip_bits(gb, 6);               // reserved
++
++    if (flag) {
++        if (size-- < 1)
++            return AVERROR_INVALIDDATA;
++        skip_bits(gb, 4);           // reserved
++        h->active_format_description = get_bits(gb, 4);
++        h->present                   = 1;
++    }
++
++    return 0;
++}
++
++static int decode_registered_user_data_closed_caption(H264SEIA53Caption *h,
++                                                     GetBitContext *gb, void *logctx,
++                                                     int size)
++{
++    int flag;
++    int user_data_type_code;
++    int cc_count;
++    av_log(logctx, AV_LOG_ERROR, "TODO: not implemented: %d, %d\n", __func__, __LINE__);
++
++    if (size < 3)
++        return AVERROR(EINVAL);
++
++    user_data_type_code = get_bits(gb, 8);
++    if (user_data_type_code == 0x3) {
++        skip_bits(gb, 1);           // reserved
++
++        flag = get_bits(gb, 1);     // process_cc_data_flag
++        if (flag) {
++            skip_bits(gb, 1);       // zero bit
++            cc_count = get_bits(gb, 5);
++            skip_bits(gb, 8);       // reserved
++            size -= 2;
++
++            if (cc_count && size >= cc_count * 3) {
++#if 0
++                int old_size = h->buf_ref ? h->buf_ref->size : 0;
++                const uint64_t new_size = (old_size + cc_count
++                                           * UINT64_C(3));
++                int i, ret;
++
++                if (new_size > INT_MAX)
++                    return AVERROR(EINVAL);
++#endif
++#if 0
++                /* Allow merging of the cc data from two fields. */
++                ret = av_buffer_realloc(&h->buf_ref, new_size);
++                if (ret < 0)
++                    return ret;
++
++                /* Use of av_buffer_realloc assumes buffer is writeable */
++                for (i = 0; i < cc_count; i++) {
++                    h->buf_ref->data[old_size++] = get_bits(gb, 8);
++                    h->buf_ref->data[old_size++] = get_bits(gb, 8);
++                    h->buf_ref->data[old_size++] = get_bits(gb, 8);
++                }
++#else
++		int i;
++                for (i = 0; i < cc_count; i++) {
++                    skip_bits(gb, 8);
++                    skip_bits(gb, 8);
++                    skip_bits(gb, 8);
++                }
++
++#endif
++                skip_bits(gb, 8);   // marker_bits
++            }
++        }
++    } else {
++        int i;
++        for (i = 0; i < size - 1; i++)
++            skip_bits(gb, 8);
++    }
++    return 0;
++}
++
++static int decode_registered_user_data(H264SEIContext *h, GetBitContext *gb,
++                                       void *logctx, int size)
++{
++    uint32_t country_code;
++    uint32_t user_identifier;
++
++    if (size < 7)
++        return AVERROR_INVALIDDATA;
++    size -= 7;
++
++    country_code = get_bits(gb, 8); // itu_t_t35_country_code
++    if (country_code == 0xFF) {
++        skip_bits(gb, 8);           // itu_t_t35_country_code_extension_byte
++        size--;
++    }
++
++    /* itu_t_t35_payload_byte follows */
++    skip_bits(gb, 8);              // terminal provider code
++    skip_bits(gb, 8);              // terminal provider oriented code
++    user_identifier = get_bits_long(gb, 32);
++
++    switch (user_identifier) {
++        case MKBETAG('D', 'T', 'G', '1'):       // afd_data
++            return decode_registered_user_data_afd(&h->afd, gb, size);
++        case MKBETAG('G', 'A', '9', '4'):       // closed captions
++            return decode_registered_user_data_closed_caption(&h->a53_caption, gb,
++                                                              logctx, size);
++        default:
++            skip_bits(gb, size * 8);
++            break;
++    }
++
++    return 0;
++}
++
++static int decode_unregistered_user_data(H264SEIUnregistered *h, GetBitContext *gb,
++                                         void *logctx, int size)
++{
++    uint8_t *user_data;
++    int e, build, i;
++
++    if (size < 16 || size >= INT_MAX - 16)
++        return AVERROR_INVALIDDATA;
++
++    user_data = av_malloc(16 + size + 1);
++    if (!user_data)
++        return AVERROR(ENOMEM);
++
++    for (i = 0; i < size + 16; i++)
++        user_data[i] = get_bits(gb, 8);
++
++    user_data[i] = 0;
++    e = sscanf(user_data + 16, "x264 - core %d", &build);
++    if (e == 1 && build > 0)
++        h->x264_build = build;
++    if (e == 1 && build == 1 && !strncmp(user_data+16, "x264 - core 0000", 16))
++        h->x264_build = 67;
++
++    av_free(user_data);
++    return 0;
++}
++
++static int decode_recovery_point(H264SEIRecoveryPoint *h, GetBitContext *gb, void *logctx)
++{
++    unsigned recovery_frame_cnt = get_ue_golomb_long(gb);
++
++    if (recovery_frame_cnt >= (1<<MAX_LOG2_MAX_FRAME_NUM)) {
++        av_log(logctx, AV_LOG_ERROR, "recovery_frame_cnt %u is out of range\n", recovery_frame_cnt);
++        return AVERROR_INVALIDDATA;
++    }
++
++    h->recovery_frame_cnt = recovery_frame_cnt;
++    /* 1b exact_match_flag,
++     * 1b broken_link_flag,
++     * 2b changing_slice_group_idc */
++    skip_bits(gb, 4);
++
++    return 0;
++}
++
++static int decode_buffering_period(H264SEIBufferingPeriod *h, GetBitContext *gb,
++                                   const H264ParamSets *ps, void *logctx)
++{
++    unsigned int sps_id;
++    int sched_sel_idx;
++    const SPS *sps;
++
++    sps_id = get_ue_golomb_31(gb);
++    if (sps_id > 31 || ! &ps->sps_list[sps_id]) {
++        av_log(logctx, AV_LOG_ERROR,
++               "non-existing SPS %d referenced in buffering period\n", sps_id);
++        return sps_id > 31 ? AVERROR_INVALIDDATA : AVERROR_PS_NOT_FOUND;
++    }
++    //sps = (const SPS*)ps->sps_list[sps_id]->data;
++    sps = &ps->sps_list[sps_id];
++
++    // NOTE: This is really so duplicated in the standard... See H.264, D.1.1
++    if (sps->nal_hrd_parameters_present_flag) {
++        for (sched_sel_idx = 0; sched_sel_idx < sps->cpb_cnt; sched_sel_idx++) {
++            h->initial_cpb_removal_delay[sched_sel_idx] =
++                get_bits_long(gb, sps->initial_cpb_removal_delay_length);
++            // initial_cpb_removal_delay_offset
++            skip_bits(gb, sps->initial_cpb_removal_delay_length);
++        }
++    }
++    if (sps->vcl_hrd_parameters_present_flag) {
++        for (sched_sel_idx = 0; sched_sel_idx < sps->cpb_cnt; sched_sel_idx++) {
++            h->initial_cpb_removal_delay[sched_sel_idx] =
++                get_bits_long(gb, sps->initial_cpb_removal_delay_length);
++            // initial_cpb_removal_delay_offset
++            skip_bits(gb, sps->initial_cpb_removal_delay_length);
++        }
++    }
++
++    h->present = 1;
++    return 0;
++}
++
++static int decode_frame_packing_arrangement(H264SEIFramePacking *h,
++                                            GetBitContext *gb)
++{
++    h->arrangement_id          = get_ue_golomb_long(gb);
++    h->arrangement_cancel_flag = get_bits1(gb);
++    h->present = !h->arrangement_cancel_flag;
++
++    if (h->present) {
++        h->arrangement_type = get_bits(gb, 7);
++        h->quincunx_sampling_flag         = get_bits1(gb);
++        h->content_interpretation_type    = get_bits(gb, 6);
++
++        // spatial_flipping_flag, frame0_flipped_flag, field_views_flag
++        skip_bits(gb, 3);
++        h->current_frame_is_frame0_flag = get_bits1(gb);
++        // frame0_self_contained_flag, frame1_self_contained_flag
++        skip_bits(gb, 2);
++
++        if (!h->quincunx_sampling_flag && h->arrangement_type != 5)
++            skip_bits(gb, 16);      // frame[01]_grid_position_[xy]
++        skip_bits(gb, 8);           // frame_packing_arrangement_reserved_byte
++        h->arrangement_repetition_period = get_ue_golomb_long(gb);
++    }
++    skip_bits1(gb);                 // frame_packing_arrangement_extension_flag
++
++    return 0;
++}
++
++static int decode_display_orientation(H264SEIDisplayOrientation *h,
++                                      GetBitContext *gb)
++{
++    h->present = !get_bits1(gb);
++
++    if (h->present) {
++        h->hflip = get_bits1(gb);     // hor_flip
++        h->vflip = get_bits1(gb);     // ver_flip
++
++        h->anticlockwise_rotation = get_bits(gb, 16);
++        get_ue_golomb_long(gb);       // display_orientation_repetition_period
++        skip_bits1(gb);               // display_orientation_extension_flag
++    }
++
++    return 0;
++}
++
++static int decode_green_metadata(H264SEIGreenMetaData *h, GetBitContext *gb)
++{
++    h->green_metadata_type = get_bits(gb, 8);
++
++    if (h->green_metadata_type == 0) {
++        h->period_type = get_bits(gb, 8);
++
++        if (h->period_type == 2)
++            h->num_seconds = get_bits(gb, 16);
++        else if (h->period_type == 3)
++            h->num_pictures = get_bits(gb, 16);
++
++        h->percent_non_zero_macroblocks            = get_bits(gb, 8);
++        h->percent_intra_coded_macroblocks         = get_bits(gb, 8);
++        h->percent_six_tap_filtering               = get_bits(gb, 8);
++        h->percent_alpha_point_deblocking_instance = get_bits(gb, 8);
++
++    } else if (h->green_metadata_type == 1) {
++        h->xsd_metric_type  = get_bits(gb, 8);
++        h->xsd_metric_value = get_bits(gb, 16);
++    }
++
++    return 0;
++}
++
++static int decode_alternative_transfer(H264SEIAlternativeTransfer *h,
++                                       GetBitContext *gb)
++{
++    h->present = 1;
++    h->preferred_transfer_characteristics = get_bits(gb, 8);
++    return 0;
++}
++
++int ff_h264_sei_decode(H264SEIContext *h, GetBitContext *gb,
++                       const H264ParamSets *ps, void *logctx)
++{
++    int master_ret = 0;
++
++    while (get_bits_left(gb) > 16 && show_bits(gb, 16)) {
++        int type = 0;
++        unsigned size = 0;
++        unsigned next;
++        int ret  = 0;
++
++        do {
++            if (get_bits_left(gb) < 8)
++                return AVERROR_INVALIDDATA;
++            type += show_bits(gb, 8);
++        } while (get_bits(gb, 8) == 255);
++
++        do {
++            if (get_bits_left(gb) < 8)
++                return AVERROR_INVALIDDATA;
++            size += show_bits(gb, 8);
++        } while (get_bits(gb, 8) == 255);
++
++        if (size > get_bits_left(gb) / 8) {
++            av_log(logctx, AV_LOG_ERROR, "SEI type %d size %d truncated at %d\n",
++                   type, 8*size, get_bits_left(gb));
++            return AVERROR_INVALIDDATA;
++        }
++        next = get_bits_count(gb) + 8 * size;
++
++        switch (type) {
++        case H264_SEI_TYPE_PIC_TIMING: // Picture timing SEI
++            ret = decode_picture_timing(&h->picture_timing, gb, ps, logctx);
++            break;
++        case H264_SEI_TYPE_USER_DATA_REGISTERED:
++            ret = decode_registered_user_data(h, gb, logctx, size);
++            break;
++        case H264_SEI_TYPE_USER_DATA_UNREGISTERED:
++            ret = decode_unregistered_user_data(&h->unregistered, gb, logctx, size);
++            break;
++        case H264_SEI_TYPE_RECOVERY_POINT:
++            ret = decode_recovery_point(&h->recovery_point, gb, logctx);
++            break;
++        case H264_SEI_TYPE_BUFFERING_PERIOD:
++            ret = decode_buffering_period(&h->buffering_period, gb, ps, logctx);
++            break;
++        case H264_SEI_TYPE_FRAME_PACKING:
++            ret = decode_frame_packing_arrangement(&h->frame_packing, gb);
++            break;
++        case H264_SEI_TYPE_DISPLAY_ORIENTATION:
++            ret = decode_display_orientation(&h->display_orientation, gb);
++            break;
++        case H264_SEI_TYPE_GREEN_METADATA:
++            ret = decode_green_metadata(&h->green_metadata, gb);
++            break;
++        case H264_SEI_TYPE_ALTERNATIVE_TRANSFER:
++            ret = decode_alternative_transfer(&h->alternative_transfer, gb);
++            break;
++        default:
++            av_log(logctx, AV_LOG_DEBUG, "unknown SEI type %d\n", type);
++        }
++        if (ret < 0 && ret != AVERROR_PS_NOT_FOUND)
++            return ret;
++        if (ret < 0)
++            master_ret = ret;
++
++        skip_bits_long(gb, next - get_bits_count(gb));
++
++        // FIXME check bits here
++        align_get_bits(gb);
++    }
++
++    return master_ret;
++}
++
++const char *ff_h264_sei_stereo_mode(const H264SEIFramePacking *h)
++{
++    if (h->arrangement_cancel_flag == 0) {
++        switch (h->arrangement_type) {
++            case H264_SEI_FPA_TYPE_CHECKERBOARD:
++                if (h->content_interpretation_type == 2)
++                    return "checkerboard_rl";
++                else
++                    return "checkerboard_lr";
++            case H264_SEI_FPA_TYPE_INTERLEAVE_COLUMN:
++                if (h->content_interpretation_type == 2)
++                    return "col_interleaved_rl";
++                else
++                    return "col_interleaved_lr";
++            case H264_SEI_FPA_TYPE_INTERLEAVE_ROW:
++                if (h->content_interpretation_type == 2)
++                    return "row_interleaved_rl";
++                else
++                    return "row_interleaved_lr";
++            case H264_SEI_FPA_TYPE_SIDE_BY_SIDE:
++                if (h->content_interpretation_type == 2)
++                    return "right_left";
++                else
++                    return "left_right";
++            case H264_SEI_FPA_TYPE_TOP_BOTTOM:
++                if (h->content_interpretation_type == 2)
++                    return "bottom_top";
++                else
++                    return "top_bottom";
++            case H264_SEI_FPA_TYPE_INTERLEAVE_TEMPORAL:
++                if (h->content_interpretation_type == 2)
++                    return "block_rl";
++                else
++                    return "block_lr";
++            case H264_SEI_FPA_TYPE_2D:
++            default:
++                return "mono";
++        }
++    } else if (h->arrangement_cancel_flag == 1) {
++        return "mono";
++    } else {
++        return NULL;
++    }
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_slice.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_slice.c
+new file mode 100644
+index 000000000..c658fda5f
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264_slice.c
+@@ -0,0 +1,1730 @@
++#include <linux/dma-mapping.h>
++#include "avassert.h"
++#include "avcodec.h"
++#include "h264.h"
++#include "h264dec.h"
++#include "h264data.h"
++#include "h264_ps.h"
++#include "golomb.h"
++#include "mathops.h"
++#include "mpegutils.h"
++#include "api/jzm_h264_dec.h"
++
++void hexdump(unsigned char *buf, int len);
++
++
++static void release_picture(H264Context *h, H264Picture *pic)
++{
++	if(!pic->f)
++		return;
++
++    	pic->f->data[0] = NULL;
++    	pic->f->data[1] = NULL;
++    	pic->f->linesize[0] = 0;
++    	pic->f->linesize[1] = 0;
++	pic->f = NULL;
++
++	av_buffer_free(&h->devmem_ctx, pic->frm_info_ctrl);
++	av_buffer_free(&h->devmem_ctx, pic->frm_info_mv);
++	if(h->format == VPU_FORMAT_NV12 || h->format == VPU_FORMAT_NV21) {
++		av_buffer_free(&h->devmem_ctx, pic->dec_result_y);
++		av_buffer_free(&h->devmem_ctx, pic->dec_result_uv);
++	}
++}
++
++void ff_h264_release_picture(H264Context *h, H264Picture *pic)
++{
++	release_picture(h, pic);
++}
++
++static void release_unused_pictures(H264Context *h, int remove_current)
++{
++    int i;
++
++    /* release non reference frames */
++    for (i = 0; i < H264_MAX_PICTURE_COUNT; i++) {
++        //if (!h->DPB[i].inuse && !h->DPB[i].reference &&
++        if (h->DPB[i].f && !h->DPB[i].reference &&
++            (remove_current || &h->DPB[i] != h->cur_pic_ptr)) {
++
++	    release_picture(h, &h->DPB[i]);
++            ff_h264_unref_picture(h, &h->DPB[i]);
++        }
++    }
++}
++
++static int alloc_picture(H264Context *h, H264Picture *pic)
++{
++    int i, ret = 0;
++    AVFrame *f = NULL;
++    unsigned int mb_array_size = 0;
++
++    f = list_first_entry_or_null(&h->queued_list, AVFrame, queued_entry);
++    if(!f) {
++	av_log(h->avctx, AV_LOG_ERROR, "cannot get AVframe from queued_list.");
++	return AVERROR(ENOMEM);
++    }
++
++    f->data[0] = f->buf[0]->buffer;
++    f->data[1] = f->buf[1]->buffer;
++    f->linesize[0] = f->buf[0]->size;
++    f->linesize[1] = f->buf[1]->size;
++
++    mb_array_size = h->mb_width * h->mb_height;
++
++#define SDE_FMV_ADS	(1 << 8)
++    pic->frm_info_ctrl = av_buffer_alloc(&h->devmem_ctx, mb_array_size * sizeof(unsigned int) * 2 + SDE_FMV_ADS);
++    if(!pic->frm_info_ctrl){
++	av_log(NULL, AV_LOG_ERROR, "Failed to alloc frm_info_ctrl!\n");
++	ret = AVERROR(ENOMEM);
++	goto err_frm_info_ctrl;
++    }
++    pic->frm_info_mv = av_buffer_alloc(&h->devmem_ctx, mb_array_size * sizeof(unsigned int) * 32 + SDE_FMV_ADS);
++    if(!pic->frm_info_mv) {
++	av_log(NULL, AV_LOG_ERROR, "aFailed to alloc frm_info_mv!\n");
++	ret = AVERROR(ENOMEM);
++	goto err_frm_info_mv;
++    }
++
++
++    if(h->format == VPU_FORMAT_NV12 || h->format == VPU_FORMAT_NV21) {
++	pic->dec_result_y = av_buffer_alloc(&h->devmem_ctx, h->width * h->height);
++	if(!pic->dec_result_y) {
++		av_log(NULL, AV_LOG_ERROR, "aFailed to alloc dec_result_y!\n");
++		ret = AVERROR(ENOMEM);
++		goto err_dec_result_y;
++	}
++	pic->dec_result_uv = av_buffer_alloc(&h->devmem_ctx, h->width * h->height / 2);
++	if(!pic->dec_result_uv) {
++		av_log(NULL, AV_LOG_ERROR, "aFailed to alloc dec_result_uv!\n");
++		ret = AVERROR(ENOMEM);
++		goto err_dec_result_uv;
++	}
++    } else {
++	/* reference to output buffer.*/
++	pic->dec_result_y  = f->buf[0];
++	pic->dec_result_uv = f->buf[1];
++    }
++
++    pic->f = f;
++
++    list_del(&f->queued_entry);
++
++    return 0;
++
++err_dec_result_uv:
++    av_buffer_free(&h->devmem_ctx, pic->dec_result_y);
++err_dec_result_y:
++    av_buffer_free(&h->devmem_ctx, pic->frm_info_mv);
++err_frm_info_mv:
++    av_buffer_free(&h->devmem_ctx, pic->frm_info_ctrl);
++err_frm_info_ctrl:
++fail:
++    ff_h264_unref_picture(h, pic);
++    return (ret < 0) ? ret : AVERROR(ENOMEM);
++}
++
++static int find_unused_picture(H264Context *h)
++{
++    int i;
++
++    for (i = 0; i < H264_MAX_PICTURE_COUNT; i++) {
++	if(!h->DPB[i].f)
++            return i;
++    }
++
++    return AVERROR_INVALIDDATA;
++}
++
++
++static int h264_slice_header_init(H264Context *h);
++
++
++static int h264_frame_start(H264Context *h)
++{
++    H264Picture *pic;
++    int i, ret;
++    const int pixel_shift = h->pixel_shift;
++    int c[4] = {
++        1<<(h->ps.sps->bit_depth_luma-1),
++        1<<(h->ps.sps->bit_depth_chroma-1),
++        1<<(h->ps.sps->bit_depth_chroma-1),
++        -1
++    };
++
++    release_unused_pictures(h, 1);
++    h->cur_pic_ptr = NULL;
++
++
++    i = find_unused_picture(h);
++    if (i < 0) {
++        av_log(h->avctx, AV_LOG_ERROR, "no frame buffer available\n");
++        return i;
++    }
++    pic = &h->DPB[i];
++
++    if ((ret = alloc_picture(h, pic)) < 0)
++        return ret;
++
++    pic->reference              = h->droppable ? 0 : h->picture_structure;
++    pic->f->coded_picture_number = h->coded_picture_number++;
++    pic->field_picture          = h->picture_structure != PICT_FRAME;
++    pic->frame_num               = h->poc.frame_num;
++    /*
++     * Zero key_frame here; IDR markings per slice in frame or fields are ORed
++     * in later.
++     * See decode_nal_units().
++     */
++    pic->f->key_frame = 0;
++    pic->mmco_reset  = 0;
++    pic->recovered   = 0;
++    pic->invalid_gap = 0;
++#if 0
++    pic->sei_recovery_frame_cnt = h->sei.recovery_point.recovery_frame_cnt;
++#endif
++
++    pic->f->pict_type = h->slice_ctx[0].slice_type;
++
++    pic->f->crop_left   = h->crop_left;
++    pic->f->crop_right  = h->crop_right;
++    pic->f->crop_top    = h->crop_top;
++    pic->f->crop_bottom = h->crop_bottom;
++
++    h->cur_pic_ptr = pic;
++
++    for (i = 0; i < h->nb_slice_ctx; i++) {
++        h->slice_ctx[i].linesize   = h->cur_pic_ptr->f->linesize[0];
++        h->slice_ctx[i].uvlinesize = h->cur_pic_ptr->f->linesize[1];
++    }
++
++    /* We mark the current picture as non-reference after allocating it, so
++     * that if we break out due to an error it can be released automatically
++     * in the next ff_mpv_frame_start().
++     */
++    h->cur_pic_ptr->reference = 0;
++
++    h->cur_pic_ptr->field_poc[0] = h->cur_pic_ptr->field_poc[1] = INT_MAX;
++
++    h->next_output_pic = NULL;
++
++    h->postpone_filter = 0;
++
++    h->mb_aff_frame = h->ps.sps->mb_aff && (h->picture_structure == PICT_FRAME);
++
++#if 0
++    if (h->sei.unregistered.x264_build >= 0)
++        h->x264_build = h->sei.unregistered.x264_build;
++#endif
++
++    //assert(h->cur_pic_ptr->long_ref == 0);
++
++    return 0;
++}
++
++/**
++ * Initialize implicit_weight table.
++ * @param field  0/1 initialize the weight for interlaced MBAFF
++ *                -1 initializes the rest
++ */
++static void implicit_weight_table(const H264Context *h, H264SliceContext *sl, int field)
++{
++    int ref0, ref1, i, cur_poc, ref_start, ref_count0, ref_count1;
++
++    for (i = 0; i < 2; i++) {
++        sl->pwt.luma_weight_flag[i]   = 0;
++        sl->pwt.chroma_weight_flag[i] = 0;
++    }
++
++    if (field < 0) {
++        if (h->picture_structure == PICT_FRAME) {
++            cur_poc = h->cur_pic_ptr->poc;
++        } else {
++            cur_poc = h->cur_pic_ptr->field_poc[h->picture_structure - 1];
++        }
++        if (sl->ref_count[0] == 1 && sl->ref_count[1] == 1 && !FRAME_MBAFF(h) &&
++            sl->ref_list[0][0].poc + (int64_t)sl->ref_list[1][0].poc == 2LL * cur_poc) {
++            sl->pwt.use_weight        = 0;
++            sl->pwt.use_weight_chroma = 0;
++            return;
++        }
++        ref_start  = 0;
++        ref_count0 = sl->ref_count[0];
++        ref_count1 = sl->ref_count[1];
++    } else {
++        cur_poc    = h->cur_pic_ptr->field_poc[field];
++        ref_start  = 16;
++        ref_count0 = 16 + 2 * sl->ref_count[0];
++        ref_count1 = 16 + 2 * sl->ref_count[1];
++    }
++
++    sl->pwt.use_weight               = 2;
++    sl->pwt.use_weight_chroma        = 2;
++    sl->pwt.luma_log2_weight_denom   = 5;
++    sl->pwt.chroma_log2_weight_denom = 5;
++
++    for (ref0 = ref_start; ref0 < ref_count0; ref0++) {
++        int64_t poc0 = sl->ref_list[0][ref0].poc;
++        for (ref1 = ref_start; ref1 < ref_count1; ref1++) {
++            int w = 32;
++            if (!sl->ref_list[0][ref0].parent->long_ref && !sl->ref_list[1][ref1].parent->long_ref) {
++                int poc1 = sl->ref_list[1][ref1].poc;
++                int td   = av_clip_int8(poc1 - poc0);
++                if (td) {
++                    int tb = av_clip_int8(cur_poc - poc0);
++                    int tx = (16384 + (FFABS(td) >> 1)) / td;
++                    int dist_scale_factor = (tb * tx + 32) >> 8;
++                    if (dist_scale_factor >= -64 && dist_scale_factor <= 128)
++                        w = 64 - dist_scale_factor;
++                }
++            }
++            if (field < 0) {
++                sl->pwt.implicit_weight[ref0][ref1][0] =
++                sl->pwt.implicit_weight[ref0][ref1][1] = w;
++            } else {
++                sl->pwt.implicit_weight[ref0][ref1][field] = w;
++            }
++        }
++    }
++}
++
++/* export coded and cropped frame dimensions to AVCodecContext */
++static int init_dimensions(H264Context *h)
++{
++    const SPS *sps = (const SPS*)h->ps.sps;
++    int cr = sps->crop_right;
++    int cl = sps->crop_left;
++    int ct = sps->crop_top;
++    int cb = sps->crop_bottom;
++    int width  = h->width  - (cr + cl);
++    int height = h->height - (ct + cb);
++    av_assert0(sps->crop_right + sps->crop_left < (unsigned)h->width);
++    av_assert0(sps->crop_top + sps->crop_bottom < (unsigned)h->height);
++
++    /* handle container cropping */
++    if (h->width_from_caller > 0 && h->height_from_caller > 0     &&
++        !sps->crop_top && !sps->crop_left                         &&
++        FFALIGN(h->width_from_caller,  16) == FFALIGN(width,  16) &&
++        FFALIGN(h->height_from_caller, 16) == FFALIGN(height, 16) &&
++        h->width_from_caller  <= width &&
++        h->height_from_caller <= height) {
++        width  = h->width_from_caller;
++        height = h->height_from_caller;
++        cl = 0;
++        ct = 0;
++        cr = h->width - width;
++        cb = h->height - height;
++    } else {
++        h->width_from_caller  = 0;
++        h->height_from_caller = 0;
++    }
++
++    h->avctx->coded_width  = h->width;
++    h->avctx->coded_height = h->height;
++    h->avctx->width        = width;
++    h->avctx->height       = height;
++    h->crop_right          = cr;
++    h->crop_left           = cl;
++    h->crop_top            = ct;
++    h->crop_bottom         = cb;
++
++    return 0;
++}
++
++static int h264_slice_header_init(H264Context *h)
++{
++    const SPS *sps = h->ps.sps;
++    int i, ret;
++
++    h->first_field           = 0;
++    h->prev_interlaced_frame = 1;
++
++    if (sps->bit_depth_luma < 8 || sps->bit_depth_luma > 14 ||
++        sps->bit_depth_luma == 11 || sps->bit_depth_luma == 13
++    ) {
++        av_log(h->avctx, AV_LOG_ERROR, "Unsupported bit depth %d\n",
++               sps->bit_depth_luma);
++        ret = AVERROR_INVALIDDATA;
++        goto fail;
++    }
++
++    h->cur_bit_depth_luma         = sps->bit_depth_luma;
++    h->cur_chroma_format_idc      = sps->chroma_format_idc;
++    h->pixel_shift                = sps->bit_depth_luma > 8;
++    h->chroma_format_idc          = sps->chroma_format_idc;
++    h->bit_depth_luma             = sps->bit_depth_luma;
++
++
++    h->context_initialized = 1;
++
++    return 0;
++fail:
++    h->context_initialized = 0;
++    return ret;
++}
++
++
++static int h264_init_ps(H264Context *h, const H264SliceContext *sl, int first_slice)
++{
++    const SPS *sps;
++    int needs_reinit = 0, must_reinit, ret;
++
++    if (first_slice) {
++	h->ps.pps = &h->ps.pps_list[sl->pps_id];
++    }
++
++    if (h->ps.sps != &h->ps.sps_list[h->ps.pps->sps_id]) {
++	h->ps.sps = &h->ps.sps_list[h->ps.pps->sps_id];
++
++        if (h->mb_width  != h->ps.sps->mb_width ||
++            h->mb_height != h->ps.sps->mb_height ||
++            h->cur_bit_depth_luma    != h->ps.sps->bit_depth_luma ||
++            h->cur_chroma_format_idc != h->ps.sps->chroma_format_idc
++        )
++            needs_reinit = 1;
++
++        if (h->bit_depth_luma    != h->ps.sps->bit_depth_luma ||
++            h->chroma_format_idc != h->ps.sps->chroma_format_idc)
++            needs_reinit         = 1;
++    }
++    sps = h->ps.sps;
++
++    must_reinit = (h->context_initialized &&
++                    (   16*sps->mb_width != h->avctx->coded_width
++                     || 16*sps->mb_height != h->avctx->coded_height
++                     || h->cur_bit_depth_luma    != sps->bit_depth_luma
++                     || h->cur_chroma_format_idc != sps->chroma_format_idc
++                     || h->mb_width  != sps->mb_width
++                     || h->mb_height != sps->mb_height
++                    ));
++
++    if (!h->setup_finished) {
++        h->avctx->profile = ff_h264_get_profile(sps);
++        h->avctx->level   = sps->level_idc;
++        h->avctx->refs    = sps->ref_frame_count;
++
++        h->mb_width  = sps->mb_width;
++        h->mb_height = sps->mb_height;
++        h->mb_num    = h->mb_width * h->mb_height;
++        h->mb_stride = h->mb_width + 1;
++
++        h->b_stride = h->mb_width * 4;
++
++        h->chroma_y_shift = sps->chroma_format_idc <= 1; // 400 uses yuv420p
++
++        h->width  = 16 * h->mb_width;
++        h->height = 16 * h->mb_height;
++
++        ret = init_dimensions(h);
++        if (ret < 0)
++            return ret;
++    }
++
++    if (!h->context_initialized || must_reinit || needs_reinit) {
++        int flush_changes = h->context_initialized;
++        h->context_initialized = 0;
++        if (sl != h->slice_ctx) {
++            av_log(h->avctx, AV_LOG_ERROR,
++                   "changing width %d -> %d / height %d -> %d on "
++                   "slice %d\n",
++                   h->width, h->avctx->coded_width,
++                   h->height, h->avctx->coded_height,
++                   h->current_slice + 1);
++            return AVERROR_INVALIDDATA;
++        }
++
++        av_assert1(first_slice);
++
++        if (flush_changes)
++            ff_h264_flush_change(h);
++
++        if ((ret = h264_slice_header_init(h)) < 0) {
++            av_log(h->avctx, AV_LOG_ERROR,
++                   "h264_slice_header_init() failed\n");
++            return ret;
++        }
++    }
++
++    return 0;
++}
++
++static int h264_select_output_frame(H264Context *h)
++{
++    const SPS *sps = h->ps.sps;
++    H264Picture *out = h->cur_pic_ptr;
++    H264Picture *cur = h->cur_pic_ptr;
++    int i, pics, out_of_order, out_idx;
++
++    cur->mmco_reset = h->mmco_reset;
++    h->mmco_reset = 0;
++
++    if (sps->bitstream_restriction_flag
++	/*|| h->avctx->strict_std_compliance >= FF_COMPLIANCE_STRICT*/) {
++        h->avctx->has_b_frames = FFMAX(h->avctx->has_b_frames, sps->num_reorder_frames);
++    }
++
++    for (i = 0; 1; i++) {
++
++        if(i == MAX_DELAYED_PIC_COUNT || cur->poc < h->last_pocs[i]){
++            if(i)
++                h->last_pocs[i-1] = cur->poc;
++            break;
++        } else if(i) {
++            h->last_pocs[i-1]= h->last_pocs[i];
++        }
++    }
++
++    out_of_order = MAX_DELAYED_PIC_COUNT - i;
++    if(   cur->f->pict_type == AV_PICTURE_TYPE_B
++       || (h->last_pocs[MAX_DELAYED_PIC_COUNT-2] > INT_MIN && h->last_pocs[MAX_DELAYED_PIC_COUNT-1] - (int64_t)h->last_pocs[MAX_DELAYED_PIC_COUNT-2] > 2))
++        out_of_order = FFMAX(out_of_order, 1);
++    if (out_of_order == MAX_DELAYED_PIC_COUNT) {
++        av_log(h->avctx, AV_LOG_VERBOSE, "Invalid POC %d<%d\n", cur->poc, h->last_pocs[0]);
++        for (i = 1; i < MAX_DELAYED_PIC_COUNT; i++)
++            h->last_pocs[i] = INT_MIN;
++        h->last_pocs[0] = cur->poc;
++        cur->mmco_reset = 1;
++    } else if(h->avctx->has_b_frames < out_of_order && !sps->bitstream_restriction_flag){
++	int loglevel = AV_LOG_WARNING;
++        av_log(h->avctx, loglevel, "Increasing reorder buffer to %d\n", out_of_order);
++        h->avctx->has_b_frames = out_of_order;
++    }
++
++    pics = 0;
++    while (h->delayed_pic[pics])
++        pics++;
++
++    av_assert0(pics <= MAX_DELAYED_PIC_COUNT);
++
++    h->delayed_pic[pics++] = cur;
++    if (cur->reference == 0)
++        cur->reference = DELAYED_PIC_REF;
++
++    out     = h->delayed_pic[0];
++    out_idx = 0;
++    for (i = 1; h->delayed_pic[i] &&
++                !h->delayed_pic[i]->f->key_frame &&
++                !h->delayed_pic[i]->mmco_reset;
++         i++)
++        if (h->delayed_pic[i]->poc < out->poc) {
++            out     = h->delayed_pic[i];
++            out_idx = i;
++        }
++
++
++    if (h->avctx->has_b_frames == 0 &&
++        (h->delayed_pic[0]->f->key_frame || h->delayed_pic[0]->mmco_reset))
++        h->next_outputed_poc = INT_MIN;
++    out_of_order = out->poc < h->next_outputed_poc;
++
++    if (out_of_order || pics > h->avctx->has_b_frames) {
++        out->reference &= ~DELAYED_PIC_REF;
++        for (i = out_idx; h->delayed_pic[i]; i++)
++            h->delayed_pic[i] = h->delayed_pic[i + 1];
++    }
++    if (!out_of_order && pics > h->avctx->has_b_frames) {
++        h->next_output_pic = out;
++        if (out_idx == 0 && h->delayed_pic[0] && (h->delayed_pic[0]->f->key_frame || h->delayed_pic[0]->mmco_reset)) {
++            h->next_outputed_poc = INT_MIN;
++        } else
++            h->next_outputed_poc = out->poc;
++
++        if (out->recovered) {
++            // We have reached an recovery point and all frames after it in
++            // display order are "recovered".
++            h->frame_recovered |= FRAME_RECOVERED_SEI;
++        }
++        out->recovered |= !!(h->frame_recovered & FRAME_RECOVERED_SEI);
++
++        if (!out->recovered) {
++                h->next_output_pic = NULL;
++#if 0
++            if (!(h->avctx->flags & AV_CODEC_FLAG_OUTPUT_CORRUPT) &&
++                !(h->avctx->flags2 & AV_CODEC_FLAG2_SHOW_ALL)) {
++                h->next_output_pic = NULL;
++            } else {
++                out->f->flags |= AV_FRAME_FLAG_CORRUPT;
++            }
++#endif
++        }
++    } else {
++        av_log(h->avctx, AV_LOG_DEBUG, "no picture %s\n", out_of_order ? "ooo" : "");
++    }
++
++    return 0;
++}
++
++/* This function is called right after decoding the slice header for a first
++ * slice in a field (or a frame). It decides whether we are decoding a new frame
++ * or a second field in a pair and does the necessary setup.
++ */
++static int h264_field_start(H264Context *h, const H264SliceContext *sl,
++                            const H2645NAL *nal, int first_slice)
++{
++    int i;
++    const SPS *sps;
++
++    int last_pic_structure, last_pic_droppable, ret;
++
++    ret = h264_init_ps(h, sl, first_slice);
++    if (ret < 0)
++        return ret;
++
++    sps = h->ps.sps;
++
++    if (sps && sps->bitstream_restriction_flag &&
++        h->avctx->has_b_frames < sps->num_reorder_frames) {
++        h->avctx->has_b_frames = sps->num_reorder_frames;
++    }
++
++    last_pic_droppable   = h->droppable;
++    last_pic_structure   = h->picture_structure;
++    h->droppable         = (nal->ref_idc == 0);
++    h->picture_structure = sl->picture_structure;
++
++    h->poc.frame_num        = sl->frame_num;
++    h->poc.poc_lsb          = sl->poc_lsb;
++    h->poc.delta_poc_bottom = sl->delta_poc_bottom;
++    h->poc.delta_poc[0]     = sl->delta_poc[0];
++    h->poc.delta_poc[1]     = sl->delta_poc[1];
++
++    /* Shorten frame num gaps so we don't have to allocate reference
++     * frames just to throw them away */
++    if (h->poc.frame_num != h->poc.prev_frame_num) {
++        int unwrap_prev_frame_num = h->poc.prev_frame_num;
++        int max_frame_num         = 1 << sps->log2_max_frame_num;
++
++        if (unwrap_prev_frame_num > h->poc.frame_num)
++            unwrap_prev_frame_num -= max_frame_num;
++
++        if ((h->poc.frame_num - unwrap_prev_frame_num) > sps->ref_frame_count) {
++            unwrap_prev_frame_num = (h->poc.frame_num - sps->ref_frame_count) - 1;
++            if (unwrap_prev_frame_num < 0)
++                unwrap_prev_frame_num += max_frame_num;
++
++            h->poc.prev_frame_num = unwrap_prev_frame_num;
++        }
++    }
++
++    /* See if we have a decoded first field looking for a pair...
++     * Here, we're using that to see if we should mark previously
++     * decode frames as "finished".
++     * We have to do that before the "dummy" in-between frame allocation,
++     * since that can modify h->cur_pic_ptr. */
++    if (h->first_field) {
++        int last_field = last_pic_structure == PICT_BOTTOM_FIELD;
++        av_assert0(h->cur_pic_ptr);
++        av_assert0(h->cur_pic_ptr->f->buf[0]);
++        //assert(h->cur_pic_ptr->reference != DELAYED_PIC_REF);
++
++        /* figure out if we have a complementary field pair */
++        if (!FIELD_PICTURE(h) || h->picture_structure == last_pic_structure) {
++            /* Previous field is unmatched. Don't display it, but let it
++             * remain for reference if marked as such. */
++            if (last_pic_structure != PICT_FRAME) {
++            }
++        } else {
++            if (h->cur_pic_ptr->frame_num != h->poc.frame_num) {
++                /* This and previous field were reference, but had
++                 * different frame_nums. Consider this field first in
++                 * pair. Throw away previous field except for reference
++                 * purposes. */
++                if (last_pic_structure != PICT_FRAME) {
++                }
++            } else {
++                /* Second field in complementary pair */
++                if (!((last_pic_structure   == PICT_TOP_FIELD &&
++                       h->picture_structure == PICT_BOTTOM_FIELD) ||
++                      (last_pic_structure   == PICT_BOTTOM_FIELD &&
++                       h->picture_structure == PICT_TOP_FIELD))) {
++                    av_log(h->avctx, AV_LOG_ERROR,
++                           "Invalid field mode combination %d/%d\n",
++                           last_pic_structure, h->picture_structure);
++                    h->picture_structure = last_pic_structure;
++                    h->droppable         = last_pic_droppable;
++                    return AVERROR_INVALIDDATA;
++                } else if (last_pic_droppable != h->droppable) {
++                    av_log(h->avctx, AV_LOG_ERROR,
++                                          "Found reference and non-reference fields in the same frame, which");
++                    h->picture_structure = last_pic_structure;
++                    h->droppable         = last_pic_droppable;
++                    return AVERROR_PATCHWELCOME;
++                }
++            }
++        }
++    }
++
++    while (h->poc.frame_num != h->poc.prev_frame_num && !h->first_field &&
++           h->poc.frame_num != (h->poc.prev_frame_num + 1) % (1 << sps->log2_max_frame_num)) {
++        H264Picture *prev = h->short_ref_count ? h->short_ref[0] : NULL;
++        av_log(h->avctx, AV_LOG_DEBUG, "Frame num gap %d %d\n",
++               h->poc.frame_num, h->poc.prev_frame_num);
++        if (!sps->gaps_in_frame_num_allowed_flag)
++            for(i=0; i<FF_ARRAY_ELEMS(h->last_pocs); i++)
++                h->last_pocs[i] = INT_MIN;
++
++        ret = h264_frame_start(h);
++        if (ret < 0) {
++            h->first_field = 0;
++            return ret;
++        }
++
++        h->poc.prev_frame_num++;
++        h->poc.prev_frame_num        %= 1 << sps->log2_max_frame_num;
++        h->cur_pic_ptr->frame_num = h->poc.prev_frame_num;
++        h->cur_pic_ptr->invalid_gap = !sps->gaps_in_frame_num_allowed_flag;
++        h->explicit_ref_marking = 0;
++        ret = ff_h264_execute_ref_pic_marking(h);
++        if (ret < 0 && (h->avctx->err_recognition & AV_EF_EXPLODE))
++            return ret;
++    }
++
++    /* See if we have a decoded first field looking for a pair...
++     * We're using that to see whether to continue decoding in that
++     * frame, or to allocate a new one. */
++    if (h->first_field) {
++        av_assert0(h->cur_pic_ptr);
++        av_assert0(h->cur_pic_ptr->f->buf[0]);
++        //assert(h->cur_pic_ptr->reference != DELAYED_PIC_REF);
++
++        /* figure out if we have a complementary field pair */
++        if (!FIELD_PICTURE(h) || h->picture_structure == last_pic_structure) {
++            /* Previous field is unmatched. Don't display it, but let it
++             * remain for reference if marked as such. */
++            h->missing_fields ++;
++            h->cur_pic_ptr = NULL;
++            h->first_field = FIELD_PICTURE(h);
++        } else {
++            h->missing_fields = 0;
++            if (h->cur_pic_ptr->frame_num != h->poc.frame_num) {
++                /* This and the previous field had different frame_nums.
++                 * Consider this field first in pair. Throw away previous
++                 * one except for reference purposes. */
++                h->first_field = 1;
++                h->cur_pic_ptr = NULL;
++            } else if (h->cur_pic_ptr->reference & DELAYED_PIC_REF) {
++                /* This frame was already output, we cannot draw into it
++                 * anymore.
++                 */
++                h->first_field = 1;
++                h->cur_pic_ptr = NULL;
++            } else {
++                /* Second field in complementary pair */
++                h->first_field = 0;
++            }
++        }
++    } else {
++        /* Frame or first field in a potentially complementary pair */
++        h->first_field = FIELD_PICTURE(h);
++    }
++
++    if (!FIELD_PICTURE(h) || h->first_field) {
++        if (h264_frame_start(h) < 0) {
++            h->first_field = 0;
++            return AVERROR_INVALIDDATA;
++        }
++    } else {
++        int field = h->picture_structure == PICT_BOTTOM_FIELD;
++        release_unused_pictures(h, 0);
++    }
++
++
++    ret = ff_h264_init_poc(h->cur_pic_ptr->field_poc, &h->cur_pic_ptr->poc,
++                     h->ps.sps, &h->poc, h->picture_structure, nal->ref_idc);
++    if (ret < 0)
++        return ret;
++
++    memcpy(h->mmco, sl->mmco, sl->nb_mmco * sizeof(*h->mmco));
++    h->nb_mmco = sl->nb_mmco;
++    h->explicit_ref_marking = sl->explicit_ref_marking;
++
++    h->picture_idr = nal->type == H264_NAL_IDR_SLICE;
++
++    h->cur_pic_ptr->f->key_frame |= (nal->type == H264_NAL_IDR_SLICE);
++
++    if (nal->type == H264_NAL_IDR_SLICE ||
++        (h->recovery_frame == h->poc.frame_num && nal->ref_idc)) {
++        h->recovery_frame         = -1;
++        h->cur_pic_ptr->recovered = 1;
++    }
++    // If we have an IDR, all frames after it in decoded order are
++    // "recovered".
++    if (nal->type == H264_NAL_IDR_SLICE)
++        h->frame_recovered |= FRAME_RECOVERED_IDR;
++
++    h->cur_pic_ptr->recovered |= h->frame_recovered;
++
++    /* Set the frame properties/side data. Only done for the second field in
++     * field coded frames, since some SEI information is present for each field
++     * and is merged by the SEI parsing code. */
++    if (!FIELD_PICTURE(h) || !h->first_field || h->missing_fields > 1) {
++
++        ret = h264_select_output_frame(h);
++        if (ret < 0)
++            return ret;
++    }
++
++    return 0;
++}
++
++static int h264_slice_header_parse(const H264Context *h, H264SliceContext *sl,
++                                   const H2645NAL *nal)
++{
++    const SPS *sps;
++    const PPS *pps;
++    int ret;
++    unsigned int slice_type, tmp, i;
++    int field_pic_flag, bottom_field_flag;
++    int first_slice = sl == h->slice_ctx && !h->current_slice;
++    int picture_structure;
++
++    if (first_slice)
++        av_assert0(!h->setup_finished);
++
++    sl->first_mb_addr = get_ue_golomb_long(&sl->gb);
++
++    slice_type = get_ue_golomb_31(&sl->gb);
++    if (slice_type > 9) {
++        av_log(h->avctx, AV_LOG_ERROR,
++               "slice type %d too large at %d\n",
++               slice_type, sl->first_mb_addr);
++        return AVERROR_INVALIDDATA;
++    }
++    if (slice_type > 4) {
++        slice_type -= 5;
++        sl->slice_type_fixed = 1;
++    } else
++        sl->slice_type_fixed = 0;
++
++    slice_type         = ff_h264_golomb_to_pict_type[slice_type];
++    sl->slice_type     = slice_type;
++    sl->slice_type_nos = slice_type & 3;
++
++    if (nal->type  == H264_NAL_IDR_SLICE &&
++        sl->slice_type_nos != AV_PICTURE_TYPE_I) {
++        av_log(h->avctx, AV_LOG_ERROR, "A non-intra slice in an IDR NAL unit.\n");
++        return AVERROR_INVALIDDATA;
++    }
++
++    sl->pps_id = get_ue_golomb(&sl->gb);
++    if (sl->pps_id >= MAX_PPS_COUNT) {
++        av_log(h->avctx, AV_LOG_ERROR, "pps_id %u out of range, max:%u\n", sl->pps_id, MAX_PPS_COUNT);
++        return AVERROR_INVALIDDATA;
++    }
++    if (!&h->ps.pps_list[sl->pps_id]) {
++        av_log(h->avctx, AV_LOG_ERROR,
++               "non-existing PPS %u referenced\n",
++               sl->pps_id);
++        return AVERROR_INVALIDDATA;
++    }
++#if 0
++    pps = (const PPS*)h->ps.pps_list[sl->pps_id]->data;
++#else
++    pps = &h->ps.pps_list[sl->pps_id];
++#endif
++    if (!&h->ps.sps_list[pps->sps_id]) {
++        av_log(h->avctx, AV_LOG_ERROR,
++               "non-existing SPS %u referenced\n", pps->sps_id);
++        return AVERROR_INVALIDDATA;
++    }
++    sps = &h->ps.sps_list[pps->sps_id];
++
++    sl->frame_num = get_bits(&sl->gb, sps->log2_max_frame_num);
++    if (!first_slice) {
++        if (h->poc.frame_num != sl->frame_num) {
++            av_log(h->avctx, AV_LOG_ERROR, "Frame num change from %d to %d\n",
++                   h->poc.frame_num, sl->frame_num);
++//            return AVERROR_INVALIDDATA;
++        }
++    }
++
++    sl->mb_mbaff       = 0;
++
++    if (sps->frame_mbs_only_flag) {
++        picture_structure = PICT_FRAME;
++    } else {
++        if (!sps->direct_8x8_inference_flag && slice_type == AV_PICTURE_TYPE_B) {
++            av_log(h->avctx, AV_LOG_ERROR, "This stream was generated by a broken encoder, invalid 8x8 inference\n");
++            return -1;
++        }
++        field_pic_flag = get_bits1(&sl->gb);
++        if (field_pic_flag) {
++            bottom_field_flag = get_bits1(&sl->gb);
++            picture_structure = PICT_TOP_FIELD + bottom_field_flag;
++        } else {
++            picture_structure = PICT_FRAME;
++        }
++    }
++    sl->picture_structure      = picture_structure;
++    sl->mb_field_decoding_flag = picture_structure != PICT_FRAME;
++
++    if (picture_structure == PICT_FRAME) {
++        sl->curr_pic_num = sl->frame_num;
++        sl->max_pic_num  = 1 << sps->log2_max_frame_num;
++    } else {
++        sl->curr_pic_num = 2 * sl->frame_num + 1;
++        sl->max_pic_num  = 1 << (sps->log2_max_frame_num + 1);
++    }
++
++    if (nal->type == H264_NAL_IDR_SLICE)
++        get_ue_golomb_long(&sl->gb); /* idr_pic_id */
++
++    if (sps->poc_type == 0) {
++        sl->poc_lsb = get_bits(&sl->gb, sps->log2_max_poc_lsb);
++
++        if (pps->pic_order_present == 1 && picture_structure == PICT_FRAME)
++            sl->delta_poc_bottom = get_se_golomb(&sl->gb);
++    }
++
++    if (sps->poc_type == 1 && !sps->delta_pic_order_always_zero_flag) {
++        sl->delta_poc[0] = get_se_golomb(&sl->gb);
++
++        if (pps->pic_order_present == 1 && picture_structure == PICT_FRAME)
++            sl->delta_poc[1] = get_se_golomb(&sl->gb);
++    }
++
++    sl->redundant_pic_count = 0;
++    if (pps->redundant_pic_cnt_present)
++        sl->redundant_pic_count = get_ue_golomb(&sl->gb);
++
++    if (sl->slice_type_nos == AV_PICTURE_TYPE_B)
++        sl->direct_spatial_mv_pred = get_bits1(&sl->gb);
++
++    ret = ff_h264_parse_ref_count(&sl->list_count, sl->ref_count,
++                                  &sl->gb, pps, sl->slice_type_nos,
++                                  picture_structure, h->avctx);
++    if (ret < 0)
++        return ret;
++
++    if (sl->slice_type_nos != AV_PICTURE_TYPE_I) {
++       ret = ff_h264_decode_ref_pic_list_reordering(sl, h->avctx);
++       if (ret < 0) {
++           sl->ref_count[1] = sl->ref_count[0] = 0;
++           return ret;
++       }
++    }
++
++    sl->pwt.use_weight = 0;
++    for (i = 0; i < 2; i++) {
++        sl->pwt.luma_weight_flag[i]   = 0;
++        sl->pwt.chroma_weight_flag[i] = 0;
++    }
++    if ((pps->weighted_pred && sl->slice_type_nos == AV_PICTURE_TYPE_P) ||
++        (pps->weighted_bipred_idc == 1 &&
++         sl->slice_type_nos == AV_PICTURE_TYPE_B)) {
++        ret = ff_h264_pred_weight_table(&sl->gb, sps, sl->ref_count,
++                                  sl->slice_type_nos, &sl->pwt,
++                                  picture_structure, h->avctx);
++        if (ret < 0)
++            return ret;
++    }
++
++    sl->explicit_ref_marking = 0;
++    if (nal->ref_idc) {
++        ret = ff_h264_decode_ref_pic_marking(sl, &sl->gb, nal, h->avctx);
++        if (ret < 0 && (h->avctx->err_recognition & AV_EF_EXPLODE))
++            return AVERROR_INVALIDDATA;
++    }
++
++    if (sl->slice_type_nos != AV_PICTURE_TYPE_I && pps->cabac) {
++        tmp = get_ue_golomb_31(&sl->gb);
++        if (tmp > 2) {
++            av_log(h->avctx, AV_LOG_ERROR, "cabac_init_idc %u overflow\n", tmp);
++            return AVERROR_INVALIDDATA;
++        }
++        sl->cabac_init_idc = tmp;
++    }
++
++    sl->last_qscale_diff = 0;
++    tmp = pps->init_qp + (unsigned)get_se_golomb(&sl->gb);
++    if (tmp > 51 + 6 * (sps->bit_depth_luma - 8)) {
++        av_log(h->avctx, AV_LOG_ERROR, "QP %u out of range\n", tmp);
++        return AVERROR_INVALIDDATA;
++    }
++    sl->qscale       = tmp;
++    sl->chroma_qp[0] = get_chroma_qp(pps, 0, sl->qscale);
++    sl->chroma_qp[1] = get_chroma_qp(pps, 1, sl->qscale);
++    // FIXME qscale / qp ... stuff
++    if (sl->slice_type == AV_PICTURE_TYPE_SP)
++        get_bits1(&sl->gb); /* sp_for_switch_flag */
++    if (sl->slice_type == AV_PICTURE_TYPE_SP ||
++        sl->slice_type == AV_PICTURE_TYPE_SI)
++        get_se_golomb(&sl->gb); /* slice_qs_delta */
++
++    sl->deblocking_filter     = 1;
++    sl->slice_alpha_c0_offset = 0;
++    sl->slice_beta_offset     = 0;
++    if (pps->deblocking_filter_parameters_present) {
++        tmp = get_ue_golomb_31(&sl->gb);
++        if (tmp > 2) {
++            av_log(h->avctx, AV_LOG_ERROR,
++                   "deblocking_filter_idc %u out of range\n", tmp);
++            return AVERROR_INVALIDDATA;
++        }
++        sl->deblocking_filter = tmp;
++        if (sl->deblocking_filter < 2)
++            sl->deblocking_filter ^= 1;  // 1<->0
++
++        if (sl->deblocking_filter) {
++            int slice_alpha_c0_offset_div2 = get_se_golomb(&sl->gb);
++            int slice_beta_offset_div2     = get_se_golomb(&sl->gb);
++            if (slice_alpha_c0_offset_div2 >  6 ||
++                slice_alpha_c0_offset_div2 < -6 ||
++                slice_beta_offset_div2 >  6     ||
++                slice_beta_offset_div2 < -6) {
++                av_log(h->avctx, AV_LOG_ERROR,
++                       "deblocking filter parameters %d %d out of range\n",
++                       slice_alpha_c0_offset_div2, slice_beta_offset_div2);
++                return AVERROR_INVALIDDATA;
++            }
++            sl->slice_alpha_c0_offset = slice_alpha_c0_offset_div2 * 2;
++            sl->slice_beta_offset     = slice_beta_offset_div2 * 2;
++        }
++    }
++
++    return 0;
++}
++
++/* do all the per-slice initialization needed before we can start decoding the
++ * actual MBs */
++static int h264_slice_init(H264Context *h, H264SliceContext *sl,
++                           const H2645NAL *nal)
++{
++    int i, j, ret = 0;
++
++    if (h->picture_idr && nal->type != H264_NAL_IDR_SLICE) {
++        av_log(h->avctx, AV_LOG_ERROR, "Invalid mix of IDR and non-IDR slices\n");
++        return AVERROR_INVALIDDATA;
++    }
++
++    av_assert1(h->mb_num == h->mb_width * h->mb_height);
++    if (sl->first_mb_addr << FIELD_OR_MBAFF_PICTURE(h) >= h->mb_num ||
++        sl->first_mb_addr >= h->mb_num) {
++        av_log(h->avctx, AV_LOG_ERROR, "first_mb_in_slice overflow\n");
++        return AVERROR_INVALIDDATA;
++    }
++
++    sl->mb_x =  sl->first_mb_addr % h->mb_width;
++    sl->mb_y = (sl->first_mb_addr / h->mb_width) <<
++                                 FIELD_OR_MBAFF_PICTURE(h);
++    av_assert1(sl->mb_y < h->mb_height);
++
++    ret = ff_h264_build_ref_list(h, sl);
++    if (ret < 0)
++        return ret;
++
++    if (h->ps.pps->weighted_bipred_idc == 2 &&
++        sl->slice_type_nos == AV_PICTURE_TYPE_B) {
++        implicit_weight_table(h, sl, -1);
++        if (FRAME_MBAFF(h)) {
++            implicit_weight_table(h, sl, 0);
++            implicit_weight_table(h, sl, 1);
++        }
++    }
++
++    if (sl->slice_type_nos == AV_PICTURE_TYPE_B && !sl->direct_spatial_mv_pred)
++        ff_h264_direct_dist_scale_factor(h, sl);
++    if (!h->setup_finished)
++        ff_h264_direct_ref_list_init(h, sl);
++    sl->qp_thresh = 15 -
++                   FFMIN(sl->slice_alpha_c0_offset, sl->slice_beta_offset) -
++                   FFMAX3(0,
++                          h->ps.pps->chroma_qp_index_offset[0],
++                          h->ps.pps->chroma_qp_index_offset[1]) +
++                   6 * (h->ps.sps->bit_depth_luma - 8);
++
++    sl->slice_num       = ++h->current_slice;
++
++    return 0;
++}
++
++void dump_slice_header(H264SliceContext *sl)
++{
++        printf("sl->slice_num: %d\n", sl->slice_num);
++        printf("sl->slice_type: %d\n", sl->slice_type);
++        printf("sl->slice_type_nos: %d\n", sl->slice_type_nos);
++
++        printf("sl->mb_x: %d\n", sl->mb_x);
++        printf("sl->mb_y: %d\n", sl->mb_y);
++	printf("sl->ref_count[0]: %d, sl->ref_count[1]:%d\n", sl->ref_count[0], sl->ref_count[1]);
++        printf("sl->mb_mbaff: %d\n", sl->mb_mbaff);
++        printf("sl->frame_num: %d\n", sl->frame_num);
++        printf("sl->curr_pic_num: %d\n", sl->curr_pic_num);
++        printf("sl->delta_poc_bottom: %d\n", sl->delta_poc_bottom);
++}
++
++
++#define MAX_SLICE_HEADER_SIZE 32
++int ff_h264_queue_decode_slice(H264Context *h, const H2645NAL *nal)
++{
++    H264SliceContext *sl = h->slice_ctx + h->nb_slice_ctx_queued;
++    int first_slice = sl == h->slice_ctx && !h->current_slice;
++    int ret;
++    unsigned char slice_header[MAX_SLICE_HEADER_SIZE];
++    unsigned char removed_at[10];
++    GetBitContext sh_gb;
++
++    sl->gb = nal->gb;
++
++    /*1. copy 256 raw data.*/
++    memcpy(slice_header, nal->gb.buffer, 32);
++
++
++//    hexdump(slice_header, 32);
++
++    /*2. remove 0x3 from slice_header */
++    char *src;
++    char *dst;
++    unsigned int si, di;
++    int removed_bytes = 0;
++    unsigned int length = 0;
++    int i = 0;
++
++    unsigned int slice_data_index = 0;
++
++    ret = init_get_bits(&sh_gb, slice_header, MAX_SLICE_HEADER_SIZE * 8);
++    sh_gb.index += 8;
++
++    /* Try to remove 0x3 in slice header. */
++    si = di = 0;
++    src = dst = slice_header;
++    length = MAX_SLICE_HEADER_SIZE;
++    while (si + 2 < length) {
++	    // remove escapes (very rare 1:2^22)
++	    if (src[si + 2] > 3) {
++		    dst[di++] = src[si++];
++		    dst[di++] = src[si++];
++	    } else if (src[si] == 0 && src[si + 1] == 0 && src[si + 2] == 3) {
++		    dst[di++] = 0;
++		    dst[di++] = 0;
++		    si       += 3;
++		    removed_at[i++] = (si-1) * 8;
++	    }
++	    dst[di++] = src[si++];
++    }
++
++    while (si < length)
++	    dst[di++] = src[si++];
++    removed_bytes = si - di;
++
++    sl->gb = sh_gb;
++    ret = h264_slice_header_parse(h, sl, nal);
++    if (ret < 0)
++        return ret;
++
++    slice_data_index = sl->gb.index;
++
++#if 0
++    for(i = 0; i < removed_bytes; i++) {
++    	if(removed_at[i] < sl->gb.index) {
++		slice_data_index += 8;
++	}
++    }
++#endif
++
++    sl->gb = nal->gb;
++    sl->gb.index = slice_data_index;
++
++    //dump_slice_header(sl);
++
++    // discard redundant pictures
++    if (sl->redundant_pic_count > 0) {
++        sl->ref_count[0] = sl->ref_count[1] = 0;
++        return 0;
++    }
++
++    /*如果第一个macroblock地�为0, ？？？？*/
++    if (sl->first_mb_addr == 0 || !h->current_slice) {
++        if (h->setup_finished) {
++            av_log(h->avctx, AV_LOG_ERROR, "Too many fields\n");
++            return AVERROR_INVALIDDATA;
++        }
++    }
++
++    if (!h->current_slice)
++        av_assert0(sl == h->slice_ctx);
++
++    if (!first_slice) {
++        const PPS *pps = &h->ps.pps_list[sl->pps_id];
++
++        if (h->ps.pps->sps_id != pps->sps_id ||
++            h->ps.pps->transform_8x8_mode != pps->transform_8x8_mode /*||
++            (h->setup_finished && h->ps.pps != pps)*/) {
++            av_log(h->avctx, AV_LOG_ERROR, "PPS changed between slices\n");
++            return AVERROR_INVALIDDATA;
++        }
++        if (h->ps.sps != &h->ps.sps_list[h->ps.pps->sps_id]) {
++            av_log(h->avctx, AV_LOG_ERROR,
++               "SPS changed in the middle of the frame\n");
++            return AVERROR_INVALIDDATA;
++        }
++    }
++
++    if (h->current_slice == 0) {
++        ret = h264_field_start(h, sl, nal, first_slice);
++        if (ret < 0)
++            return ret;
++    } else {
++        if (h->picture_structure != sl->picture_structure ||
++            h->droppable         != (nal->ref_idc == 0)) {
++            av_log(h->avctx, AV_LOG_ERROR,
++                   "Changing field mode (%d -> %d) between slices is not allowed\n",
++                   h->picture_structure, sl->picture_structure);
++            return AVERROR_INVALIDDATA;
++        } else if (!h->cur_pic_ptr) {
++            av_log(h->avctx, AV_LOG_ERROR,
++                   "unset cur_pic_ptr on slice %d\n",
++                   h->current_slice + 1);
++            return AVERROR_INVALIDDATA;
++        }
++    }
++
++    ret = h264_slice_init(h, sl, nal);
++    if (ret < 0)
++        return ret;
++
++    h->nb_slice_ctx_queued++;
++
++    return 0;
++}
++
++int ff_h264_get_slice_type(const H264SliceContext *sl)
++{
++    switch (sl->slice_type) {
++    case AV_PICTURE_TYPE_P:
++        return 0;
++    case AV_PICTURE_TYPE_B:
++        return 1;
++    case AV_PICTURE_TYPE_I:
++        return 2;
++    case AV_PICTURE_TYPE_SP:
++        return 3;
++    case AV_PICTURE_TYPE_SI:
++        return 4;
++    default:
++        return AVERROR_INVALIDDATA;
++    }
++}
++
++void dump_st_h264(struct JZM_H264 *st_h264)
++{
++	printf("st_h264->des_va			     :0x%x\n", st_h264->des_va			);
++	printf("st_h264->slice_type                  :0x%x\n", st_h264->slice_type              );
++	printf("st_h264->slice_num                   :0x%x\n", st_h264->slice_num               );
++	printf("st_h264->start_mb_x                  :0x%x\n", st_h264->start_mb_x              );
++	printf("st_h264->start_mb_y                  :0x%x\n", st_h264->start_mb_y              );
++	printf("st_h264->mb_width                    :0x%x\n", st_h264->mb_width                );
++	printf("st_h264->mb_height                   :0x%x\n", st_h264->mb_height               );
++	printf("st_h264->field_picture               :0x%x\n", st_h264->field_picture           );
++	printf("st_h264->cabac                       :0x%x\n", st_h264->cabac                   );
++	printf("st_h264->qscale                      :0x%x\n", st_h264->qscale                  );
++	printf("st_h264->transform_8x8_mode          :0x%x\n", st_h264->transform_8x8_mode      );
++	printf("st_h264->constrained_intra_pred      :0x%x\n", st_h264->constrained_intra_pred  );
++	printf("st_h264->direct_8x8_inference_flag   :0x%x\n", st_h264->direct_8x8_inference_flag);
++	printf("st_h264->direct_spatial_mv_pred      :0x%x\n", st_h264->direct_spatial_mv_pred  );
++	printf("st_h264->x264_build                  :0x%x\n", st_h264->x264_build              );
++	printf("st_h264->ref_count_0                 :0x%x\n", st_h264->ref_count_0             );
++	printf("st_h264->ref_count_1                 :0x%x\n", st_h264->ref_count_1             );
++	printf("st_h264->deblocking_filter           :0x%x\n", st_h264->deblocking_filter       );
++	printf("st_h264->slice_alpha_c0_offset       :0x%x\n", st_h264->slice_alpha_c0_offset   );
++	printf("st_h264->slice_beta_offset           :0x%x\n", st_h264->slice_beta_offset       );
++	printf("st_h264->bs_buffer                   :0x%x\n", st_h264->bs_buffer               );
++	printf("st_h264->bs_index                    :0x%x\n", st_h264->bs_index                );
++	printf("st_h264->bs_size_in_bits             :0x%x\n", st_h264->bs_size_in_bits         );
++	printf("st_h264->cabac_init_idc              :0x%x\n", st_h264->cabac_init_idc          );
++	printf("st_h264->ref_frm_ctrl                :0x%x\n", st_h264->ref_frm_ctrl            );
++	printf("st_h264->ref_frm_mv                  :0x%x\n", st_h264->ref_frm_mv              );
++	printf("st_h264->curr_frm_ctrl               :0x%x\n", st_h264->curr_frm_ctrl           );
++	printf("st_h264->curr_frm_mv                 :0x%x\n", st_h264->curr_frm_mv             );
++	printf("st_h264->use_weight                  :0x%x\n", st_h264->use_weight              );
++	printf("st_h264->use_weight_chroma           :0x%x\n", st_h264->use_weight_chroma       );
++	printf("st_h264->use_weight_chroma           :0x%x\n", st_h264->use_weight_chroma       );
++	printf("st_h264->luma_log2_weight_denom      :0x%x\n", st_h264->luma_log2_weight_denom  );
++	printf("st_h264->chroma_log2_weight_denom    :0x%x\n", st_h264->chroma_log2_weight_denom);
++	printf("st_h264->dblk_left_en                :0x%x\n", st_h264->dblk_left_en            );
++	printf("st_h264->dblk_top_en                 :0x%x\n", st_h264->dblk_top_en             );
++	printf("st_h264->dec_result_y                :0x%x\n", st_h264->dec_result_y            );
++	printf("st_h264->dec_result_uv               :0x%x\n", st_h264->dec_result_uv           );
++	printf("st_h264->new_odma_flag		     :0x%x\n", st_h264->new_odma_flag		);
++	printf("st_h264->new_odma_format	     :0x%x\n", st_h264->new_odma_format		);
++	printf("st_h264->dec_result1_y		     :0x%x\n", st_h264->dec_result1_y		);
++	printf("st_h264->dec_result1_uv		     :0x%x\n", st_h264->dec_result1_uv		);
++	printf("st_h264->frm_y_stride		     :0x%x\n", st_h264->frm_y_stride		);
++	printf("st_h264->frm_c_stride		     :0x%x\n", st_h264->frm_c_stride		);
++	printf("st_h264->bs_rbsp_en		     :0x%x\n", st_h264->bs_rbsp_en		);
++
++	int i;
++	printf("st_h264->dir_scale_table:    \n--------------------\n");
++	for (i=0; i<16/4; i++) {
++		printf("%x   %x   %x   %x\n", st_h264->dir_scale_table[i], st_h264->dir_scale_table[i+1], st_h264->dir_scale_table[i+2], st_h264->dir_scale_table[i+3]);
++	}
++	printf("--------------------------------------------------\n");
++
++#if 1
++
++	printf("st_h264->mc_ref_y[0]: \n");
++	for(i = 0; i < 16; i++) {
++		printf("%x ", st_h264->mc_ref_y[0][i]);
++
++	}
++	printf("\n");
++	printf("st_h264->mc_ref_c[0]: \n");
++	for(i = 0; i < 16; i++) {
++		printf("%x ", st_h264->mc_ref_c[0][i]);
++
++	}
++	printf("\n");
++	printf("st_h264->mc_ref_y[1]: \n");
++	for(i = 0; i < 16; i++) {
++		printf("%x ", st_h264->mc_ref_y[1][i]);
++
++	}
++	printf("\n");
++	printf("st_h264->mc_ref_c[1]: \n");
++	for(i = 0; i < 16; i++) {
++		printf("%x ", st_h264->mc_ref_c[1][i]);
++
++	}
++	printf("\n");
++
++	printf("st_h264->chroma_qp_table:---------------\n");
++	for (i=0; i<128/16; i++) {
++		int j;
++		for(j = i * 16; j < i * 16 + 16; j++) {
++			printf("%08x  ", st_h264->chroma_qp_table[j]);
++		}
++		printf("\n");
++	}
++
++	printf("##luma_weight:\n");
++	for(i = 0; i<2; i++) {
++		int j;
++		for(j = 0; j< 16; j++) {
++			printf("%08d  ", st_h264->luma_weight[i][j]);
++		}
++		printf("\n");
++	}
++	printf("luma_offset:\n");
++	for(i = 0; i<2; i++) {
++		int j;
++		for(j = 0; j< 16; j++) {
++			printf("%08d  ", st_h264->luma_offset[i][j]);
++		}
++		printf("\n");
++	}
++
++	printf("##chroma_weight:\n");
++	for(i = 0; i<2; i++) {
++		int j;
++		for(j = 0; j< 16; j++) {
++			int k;
++			if(!(j%8))
++				printf("\n");
++			for(k = 0 ; k < 2; k ++)
++				printf("%08d ", st_h264->chroma_weight[i][j][k]);
++
++
++		}
++		printf("\n");
++	}
++	printf("chroma_offset:\n");
++	for(i = 0; i<2; i++) {
++		int j;
++		for(j = 0; j< 16; j++) {
++			int k;
++			if(!(j%8))
++				printf("\n");
++			for(k = 0; k < 2; k++) {
++				printf("%08d ", st_h264->chroma_offset[i][j][k]);
++			}
++		}
++		printf("\n");
++	}
++
++	printf("### implicit_weight !\n");
++	for(i = 0; i<16; i++) {
++		int j;
++		for(j = 0; j < 16; j++) {
++			printf("%08d ",st_h264->implicit_weight[i][j]);
++		}
++		printf("\n");
++	}
++
++	printf("dump matrix 4x4:\n");
++	for(i=0; i< 6; i++) {
++		int j;
++		for(j = 0; j < 16; j++) {
++			printf("%08d ", st_h264->scaling_matrix4[i][j]);
++		}
++		printf("\n");
++	}
++
++	printf("dump matrix 8x8:\n");
++	for(i = 0; i <2; i++) {
++		int j;
++		for(j=0; j<64; j++) {
++			if(!(j%16))
++				printf("%08d ", st_h264->scaling_matrix8[i][j]);
++		}
++		printf("\n");
++	}
++#endif
++
++
++}
++
++void hexdump(unsigned char *buf, int len)
++{
++	int i;
++
++	for (i = 0; i < len; i++) {
++		if ((i % 16) == 0)
++			printf("%s%08x: ", i ? "\n" : "",
++					(unsigned int)&buf[i]);
++		printf("%02x ", buf[i]);
++	}
++	printf("\n");
++}
++
++void dump_bs_buffer(struct JZM_H264 *st_h264, char *bs, unsigned long len)
++{
++	int i;
++	printf("dump bs buffer- bs_index :%d, %s\n", st_h264->bs_index, st_h264->bs_index % 8 ? "Not 8Bits align": "8Bits align");
++	printf("----\n");
++	int bs_index = st_h264->bs_index;
++	unsigned char *bs_buffer = bs;
++	/* dump 32bytes more after bs_index */
++	for(i = 0; i < bs_index/8 + 32; i++) {
++		printf("%02x", bs_buffer[i]);
++		if(bs_index > i*8) {
++			printf(". ");
++		} else if(bs_index == i*8) {
++			printf("=>");
++		} else {
++			printf(" ");
++		}
++	}
++	printf("\n----\n");
++
++	printf("bs @ start:\n");
++	hexdump(bs, 64);
++	printf("bs @ end:\n");
++	hexdump(bs + len - 64, 64);
++}
++
++void dump_picture(H264Picture *pic)
++{
++	AVFrame *f = pic->f;
++	printf("######## dump H264Picture #########\n");
++
++	printf("dump_picture f:%p\n", f);
++	printf("f->buf[0]: %p\n", f->buf[0]);
++	printf("f->buf[1]: %p\n", f->buf[1]);
++	printf("f->buf[0]->buffer_pa: %lx\n", f->buf[0]->buffer_pa);
++	printf("f->buf[1]->buffer_pa: %lx\n", f->buf[1]->buffer_pa);
++	printf("pic->frame_num: %d\n", pic->frame_num);
++
++}
++
++#if 0
++#include <sys/types.h>
++#include <sys/stat.h>
++#include <fcntl.h>
++#endif
++
++
++static int decode_slice(struct AVCodecContext *avctx, void *arg)
++{
++
++	/*我怎么知��解�这一帧图片，�是对于B帧的解��延�处��??? */
++    H264SliceContext *sl = arg;
++    const H264Context *h = sl->h264;
++    H264Picture *cur_pic = h->cur_pic_ptr;
++    jzm_h264 *st_h264 = h->st_h264;
++    int lf_x_start = sl->mb_x;
++    int orig_deblock = sl->deblocking_filter;
++    int ret;
++    int i;
++    unsigned int offset_y, offset_uv;
++
++    for(i = 0; i < H264_MAX_PICTURE_COUNT; i++) {
++	    if(h->cur_pic_ptr == &h->DPB[i])
++		    break;
++    }
++
++
++#if 0
++    printf("use: %d in DPB\n", i);
++    dump_picture(h->cur_pic_ptr);
++    printf("---decode_slice----\n");
++    printf("ref_count[0]: %d\n", sl->ref_count[0]);
++    printf("ref_count[1]: %d\n", sl->ref_count[1]);
++    printf("list_count: %d\n", sl->list_count);
++    for(i = 0; i < sl->ref_count[0]; i++) {
++    	printf("H264Ref[i] : %x\n", &sl->ref_list[0][i]);
++    }
++#endif
++
++    if(h->width > h->coded_width || h->height > h->coded_height) {
++	printf("App allocated buffer is too small, which is illegal.\n");
++	printf("BS parsed width:%d, height:%d, while allocated width: %d, height: %d\n", h->width, h->height, h->coded_width, h->coded_height);
++	return AVERROR(EINVAL);
++    }
++
++    st_h264->slice_type = (sl->slice_type==AV_PICTURE_TYPE_B) ? JZM_H264_B_TYPE	\
++			  :(sl->slice_type==AV_PICTURE_TYPE_P) ? JZM_H264_P_TYPE \
++			  :JZM_H264_I_TYPE;
++
++    st_h264->slice_num                   = sl->slice_num-1;
++    st_h264->start_mb_x                  = sl->mb_x;
++    st_h264->start_mb_y                  = sl->mb_y;
++    st_h264->mb_width                    = h->mb_width;
++    st_h264->mb_height                   = h->mb_height;
++    st_h264->field_picture               = sl->picture_structure != PICT_FRAME;
++    st_h264->cabac                       = h->ps.pps->cabac;
++    st_h264->qscale                      = sl->qscale;
++    st_h264->transform_8x8_mode          = !!h->ps.pps->transform_8x8_mode;
++    st_h264->constrained_intra_pred      = !!h->ps.pps->constrained_intra_pred;
++    st_h264->direct_8x8_inference_flag   = !!h->ps.sps->direct_8x8_inference_flag;
++    st_h264->direct_spatial_mv_pred      = !!sl->direct_spatial_mv_pred;
++    st_h264->x264_build                  = 0xffff;
++    st_h264->ref_count_0                 = sl->ref_count[0] - 1;
++    st_h264->ref_count_1                 = sl->ref_count[1] - 1;
++    st_h264->deblocking_filter           = !!sl->deblocking_filter;
++    st_h264->slice_alpha_c0_offset       = sl->slice_alpha_c0_offset;
++    st_h264->slice_beta_offset           = sl->slice_beta_offset;
++
++	/*sl->gb.buffer 转物�地�. */
++    //st_h264->bs_buffer			 = h->pkt.rbsp_buf->buffer_pa + sl->gb.buffer - h->pkt.rbsp_buf->buffer;
++    st_h264->bs_buffer			 = (unsigned int)sl->gb.buffer & 0x1fffffff;
++    st_h264->bs_index                    = sl->gb.index;
++    st_h264->bs_size_in_bits             = sl->gb.size_in_bits;
++
++#if 1	/*在M200上需�处�以下bs_addr，�则会出bs_error.
++	原�media部门�供的api在api内部会�处�，现在需�在外�作处�了.
++	*/
++    unsigned int bs_addr;
++    unsigned int bs_ofst;
++    if (st_h264->cabac) {
++	    int n = (-st_h264->bs_index) & 7;
++	    if(n) st_h264->bs_index += n;
++	    bs_addr = st_h264->bs_buffer + (st_h264->bs_index >> 3);
++	    bs_ofst = (bs_addr & 0x3) << 3;
++	    bs_addr = bs_addr & (~0x3);
++	    st_h264->bs_rbsp_en 		 = 1;
++    } else {
++	    bs_addr = (unsigned int)(st_h264->bs_buffer + (st_h264->bs_index >> 3)) & (~0x3);
++	    bs_ofst = ((((unsigned int)st_h264->bs_buffer & 0x3) << 3) + ((unsigned int)st_h264->bs_index & 0x1F)) & 0x1F;
++	    unsigned int slice_bs_size = st_h264->bs_size_in_bits - st_h264->bs_index + bs_ofst;
++	    //st_h264->bs_size_in_bits = slice_bs_size;
++
++	    char *src, *dst;
++	    unsigned long length;
++	    int si, di;
++	    int removed_bytes = 0;
++	    si = di = 0;
++
++	    src = dst = (char*)sl->gb.buffer;
++	    length = (sl->gb.size_in_bits + 7) / 8;
++
++	    while (si + 2 < length) {
++		    // remove escapes (very rare 1:2^22)
++		    if (src[si + 2] > 3) {
++			    dst[di++] = src[si++];
++			    dst[di++] = src[si++];
++		    } else if (src[si] == 0 && src[si + 1] == 0 && src[si + 2] == 3) {
++				    dst[di++] = 0;
++				    dst[di++] = 0;
++				    si       += 3;
++		    }
++		    dst[di++] = src[si++];
++	    }
++
++	    while (si < length)
++		    dst[di++] = src[si++];
++
++	    removed_bytes = si - di;
++
++	    st_h264->bs_size_in_bits = slice_bs_size - 8 * removed_bytes;
++	    dma_sync_single_for_device(h->devmem_ctx.dev, (dma_addr_t)(virt_to_phys((void *)dst)), di, DMA_TO_DEVICE);
++
++	    st_h264->bs_rbsp_en 		 = 0;
++    }
++
++    st_h264->bs_buffer = bs_addr;	/*　slice_header之�的slice_data*/
++    st_h264->bs_index  = bs_ofst;
++
++#endif
++
++    st_h264->cabac_init_idc              = sl->cabac_init_idc;
++    if(sl->ref_list[1][0].parent) {
++	st_h264->ref_frm_ctrl                = sl->ref_list[1][0].parent->frm_info_ctrl->buffer_pa;
++    }
++    if(sl->ref_list[1][0].parent) {
++	st_h264->ref_frm_mv                  = sl->ref_list[1][0].parent->frm_info_mv->buffer_pa;
++    }
++    st_h264->curr_frm_ctrl               = cur_pic->frm_info_ctrl->buffer_pa;
++    st_h264->curr_frm_mv                 = cur_pic->frm_info_mv->buffer_pa;
++
++#if 0
++    /*新版的api没有这两个��.*/
++    st_h264->curr_frm_slice_start_mb     = cur_pic->frm_info_slice_start_mb;
++    st_h264->ref_frm_slice_start_mb      = sl->ref_list[1][0].frm_info_slice_start_mb;
++#endif
++    st_h264->use_weight                  = sl->pwt.use_weight;
++    st_h264->use_weight_chroma           = sl->pwt.use_weight_chroma;
++    st_h264->luma_log2_weight_denom      = sl->pwt.luma_log2_weight_denom;
++    st_h264->chroma_log2_weight_denom    = sl->pwt.chroma_log2_weight_denom;
++    st_h264->dblk_left_en                = /*h->s.mb_x!=*/0;
++    st_h264->dblk_top_en                 = /*h->s.mb_y!=*/0;
++
++#define ROUND_UP(x, align) (((int) (x) + (align - 1)) & ~(align - 1))
++
++    if(h->format == VPU_FORMAT_NV12 || h->format == VPU_FORMAT_NV21) {
++	st_h264->new_odma_flag = 1;	/* enable new output dma */
++	st_h264->new_odma_format = h->format == VPU_FORMAT_NV12 ? 0 : 1;	/*0: NV12, 1 : NV21*/
++	//st_h264->dec_result1_y = cur_pic->f->buf[0]->buffer_pa;
++	//st_h264->dec_result1_uv = cur_pic->f->buf[1]->buffer_pa;
++	st_h264->frm_y_stride = ROUND_UP(h->width, 128);
++	st_h264->frm_c_stride = st_h264->frm_y_stride;
++
++	offset_y = st_h264->start_mb_y * 16 * st_h264->frm_y_stride + st_h264->start_mb_x * 16;
++	offset_uv = st_h264->start_mb_y * 8 * st_h264->frm_y_stride + st_h264->start_mb_x * 16;
++	st_h264->dec_result1_y = cur_pic->f->buf[0]->buffer_pa + offset_y;
++	st_h264->dec_result1_uv = cur_pic->f->buf[1]->buffer_pa + offset_uv;
++
++    } else {
++	st_h264->new_odma_flag = 0;
++    }
++
++    /* see alloc_picture()*/
++    st_h264->dec_result_y = cur_pic->dec_result_y->buffer_pa;
++    st_h264->dec_result_uv = cur_pic->dec_result_uv->buffer_pa;
++
++    for (i=0; i<16; i++) {
++	    st_h264->dir_scale_table[i] = sl->map_col_to_list0[0][i] + (sl->map_col_to_list0[1][i] << 5) + (sl->dist_scale_factor[i] << 16);
++    }
++
++    for (i=0; i<128; i++) {
++
++	    unsigned int qp_c0 = h->ps.pps->chroma_qp_table[0][i] & 0xFF;
++	    unsigned int qp_c1 = h->ps.pps->chroma_qp_table[1][i] & 0xFF;
++	    unsigned int qp_c0_d6 = qp_c0/6;
++	    unsigned int qp_c0_m6 = qp_c0%6;
++	    unsigned int qp_c1_d6 = qp_c1/6;
++	    unsigned int qp_c1_m6 = qp_c1%6;
++	    st_h264->chroma_qp_table[i] = ((((((qp_c1_d6 & 0xF) + ((qp_c1_m6 & 0x7) << 4)) << 7) +
++					    (((qp_c0_d6 & 0xF) + ((qp_c0_m6 & 0x7) << 4)) << 0) ) << 16) +
++			    ((qp_c1 & 0x3F) << 6) +
++			    ((qp_c0 & 0x3F) << 0)
++			    );
++    }
++
++
++    for (i=0; i<16; i++) {
++	    H264Picture *parent;
++	    parent = sl->ref_list[0][i].parent;
++
++	    st_h264->mc_ref_y[0][i] = parent ? parent->dec_result_y->buffer_pa: 0;
++	    st_h264->mc_ref_c[0][i] = parent ? parent->dec_result_uv->buffer_pa : 0;
++
++	    parent = sl->ref_list[1][i].parent;
++	    st_h264->mc_ref_y[1][i] = parent? parent->dec_result_y->buffer_pa : 0;
++	    st_h264->mc_ref_c[1][i] = parent? parent->dec_result_uv->buffer_pa : 0;
++
++	    int j;
++	    for (j=0; j<2; j++) {
++		    st_h264->luma_weight[j][i]      = sl->pwt.luma_weight[i][j][0];
++		    st_h264->chroma_weight[j][i][0] = sl->pwt.chroma_weight[i][j][0][0];
++		    st_h264->chroma_weight[j][i][1] = sl->pwt.chroma_weight[i][j][1][0];
++		    st_h264->luma_offset[j][i]      = sl->pwt.luma_weight[i][j][1];
++		    st_h264->chroma_offset[j][i][0] = sl->pwt.chroma_weight[i][j][0][1];
++		    st_h264->chroma_offset[j][i][1] = sl->pwt.chroma_weight[i][j][1][1];
++	    }
++	    for (j=0; j<16; j++) {
++		    st_h264->implicit_weight[i][j] = sl->pwt.implicit_weight[i][j][0];
++	    }
++    }
++
++    memcpy(st_h264->scaling_matrix4, h->ps.pps->scaling_matrix4, sizeof(h->ps.pps->scaling_matrix4));
++    memcpy(st_h264->scaling_matrix8, h->ps.pps->scaling_matrix8, sizeof(h->ps.pps->scaling_matrix8));
++
++    st_h264->des_va = (int *)h->dma_desc->buffer;
++
++#if 0
++    dump_st_h264(h->st_h264);
++    dump_bs_buffer(h->st_h264, st_h264->bs_buffer | 0x80000000, (st_h264->bs_size_in_bits + 7) / 8);
++#endif
++
++    jzm_h264_slice_init_vdma(st_h264);
++
++
++    //memset(st_h264->dec_result_y | 0x80000000, 0, 256);
++    //memset(st_h264->dec_result_uv | 0x80000000, 0, 256);
++
++    av_buffer_sync((void*)&h->devmem_ctx, h->dma_desc, DMA_TO_DEVICE);
++    //av_buffer_sync(&h->devmem_ctx, h->pkt.rbsp_buf, DMA_TO_DEVICE);
++
++    ret = vpu_hw_start((void*)&h->vpu_ctx);
++    if(ret < 0) {
++	    printf("h->mb_width: %d, h->mb_height: %d, current_decode mb_y: %d, mb_x: %d\n",
++		h->mb_width, h->mb_height, (h->vpu_ctx.sde_stat >> 24) & 0xff, (h->vpu_ctx.sde_stat >> 16) & 0xff);
++	    //return AVERROR(EINVAL);
++    }
++
++    vpu_hw_wait((void*)&h->vpu_ctx);
++
++    if(h->vpu_ctx.error) {
++	    sl->mb_y = h->mb_height;
++    } else {
++
++	    sl->mb_y = (h->vpu_ctx.sde_stat >> 24) & 0xff;
++    }
++//    printf("----------decode_slice done ----------------\n");
++
++    return ret;
++}
++
++/**
++ * Call decode_slice() for each context.
++ *
++ * @param h h264 master context
++ */
++int ff_h264_execute_decode_slices(H264Context *h)
++{
++    AVCodecContext *const avctx = h->avctx;
++    H264SliceContext *sl;
++    int context_count = h->nb_slice_ctx_queued;
++    int ret = 0;
++    int i, j;
++
++
++    h->slice_ctx[0].next_slice_idx = INT_MAX;
++
++    if (/*h->avctx->hwaccel || */context_count < 1)
++        return 0;
++
++    av_assert0(context_count && h->slice_ctx[context_count - 1].mb_y < h->mb_height);
++
++    /* context_count 是�是�以�解为由多少个线程or ???*/
++    if (context_count == 1) {
++
++        h->slice_ctx[0].next_slice_idx = h->mb_width * h->mb_height;
++        h->postpone_filter = 0;
++
++	/* 能够到这里说明已�确切的知��解�的SLICE.*/
++        ret = decode_slice(avctx, &h->slice_ctx[0]);
++	/*设置当�解�到了哪一个mb*/
++        h->mb_y = h->slice_ctx[0].mb_y;
++        if (ret < 0) {
++            h->next_output_pic = NULL;
++            goto finish;
++	}
++    } else {
++	av_log(NULL, AV_LOG_ERROR, "too many context in decode queue!\n");
++	ret = -EINVAL;
++    }
++
++finish:
++    h->nb_slice_ctx_queued = 0;
++    return ret;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264data.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264data.c
+new file mode 100644
+index 000000000..f3a30e4d3
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264data.c
+@@ -0,0 +1,114 @@
++#include "avcodec.h"
++#include "h264dec.h"
++#include "h264data.h"
++
++const uint8_t ff_h264_golomb_to_pict_type[5] = {
++    AV_PICTURE_TYPE_P, AV_PICTURE_TYPE_B, AV_PICTURE_TYPE_I,
++    AV_PICTURE_TYPE_SP, AV_PICTURE_TYPE_SI
++};
++
++const uint8_t ff_h264_golomb_to_intra4x4_cbp[48] = {
++    47, 31, 15, 0,  23, 27, 29, 30, 7,  11, 13, 14, 39, 43, 45, 46,
++    16, 3,  5,  10, 12, 19, 21, 26, 28, 35, 37, 42, 44, 1,  2,  4,
++    8,  17, 18, 20, 24, 6,  9,  22, 25, 32, 33, 34, 36, 40, 38, 41
++};
++
++const uint8_t ff_h264_golomb_to_inter_cbp[48] = {
++    0,  16, 1,  2,  4,  8,  32, 3,  5,  10, 12, 15, 47, 7,  11, 13,
++    14, 6,  9,  31, 35, 37, 42, 44, 33, 34, 36, 40, 39, 43, 45, 46,
++    17, 18, 20, 24, 19, 21, 26, 28, 23, 27, 29, 30, 22, 25, 38, 41
++};
++
++const uint8_t ff_h264_chroma_dc_scan[4] = {
++    (0 + 0 * 2) * 16, (1 + 0 * 2) * 16,
++    (0 + 1 * 2) * 16, (1 + 1 * 2) * 16,
++};
++
++const uint8_t ff_h264_chroma422_dc_scan[8] = {
++    (0 + 0 * 2) * 16, (0 + 1 * 2) * 16,
++    (1 + 0 * 2) * 16, (0 + 2 * 2) * 16,
++    (0 + 3 * 2) * 16, (1 + 1 * 2) * 16,
++    (1 + 2 * 2) * 16, (1 + 3 * 2) * 16,
++};
++
++const uint8_t ff_h264_dequant4_coeff_init[6][3] = {
++    { 10, 13, 16 },
++    { 11, 14, 18 },
++    { 13, 16, 20 },
++    { 14, 18, 23 },
++    { 16, 20, 25 },
++    { 18, 23, 29 },
++};
++
++const uint8_t ff_h264_dequant8_coeff_init_scan[16] = {
++    0, 3, 4, 3, 3, 1, 5, 1, 4, 5, 2, 5, 3, 1, 5, 1
++};
++
++const uint8_t ff_h264_dequant8_coeff_init[6][6] = {
++    { 20, 18, 32, 19, 25, 24 },
++    { 22, 19, 35, 21, 28, 26 },
++    { 26, 23, 42, 24, 33, 31 },
++    { 28, 25, 45, 26, 35, 33 },
++    { 32, 28, 51, 30, 40, 38 },
++    { 36, 32, 58, 34, 46, 43 },
++};
++
++const uint8_t ff_h264_quant_rem6[QP_MAX_NUM + 1] = {
++    0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2,
++    3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5,
++    0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2,
++    3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5,
++    0, 1, 2, 3,
++};
++
++const uint8_t ff_h264_quant_div6[QP_MAX_NUM + 1] = {
++    0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3,  3,  3,
++    3, 3, 3, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6,  6,  6,
++    7, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 10, 10, 10,
++   10,10,10,11,11,11,11,11,11,12,12,12,12,12,12,13,13,13, 13, 13, 13,
++   14,14,14,14,
++};
++
++#define QP(qP, depth) ((qP) + 6 * ((depth) - 8))
++
++#define CHROMA_QP_TABLE_END(d)                                          \
++    QP(0,  d), QP(1,  d), QP(2,  d), QP(3,  d), QP(4,  d), QP(5,  d),   \
++    QP(6,  d), QP(7,  d), QP(8,  d), QP(9,  d), QP(10, d), QP(11, d),   \
++    QP(12, d), QP(13, d), QP(14, d), QP(15, d), QP(16, d), QP(17, d),   \
++    QP(18, d), QP(19, d), QP(20, d), QP(21, d), QP(22, d), QP(23, d),   \
++    QP(24, d), QP(25, d), QP(26, d), QP(27, d), QP(28, d), QP(29, d),   \
++    QP(29, d), QP(30, d), QP(31, d), QP(32, d), QP(32, d), QP(33, d),   \
++    QP(34, d), QP(34, d), QP(35, d), QP(35, d), QP(36, d), QP(36, d),   \
++    QP(37, d), QP(37, d), QP(37, d), QP(38, d), QP(38, d), QP(38, d),   \
++    QP(39, d), QP(39, d), QP(39, d), QP(39, d)
++
++const uint8_t ff_h264_chroma_qp[7][QP_MAX_NUM + 1] = {
++    { CHROMA_QP_TABLE_END(8) },
++    { 0, 1, 2, 3, 4, 5,
++      CHROMA_QP_TABLE_END(9) },
++    { 0, 1, 2, 3,  4,  5,
++      6, 7, 8, 9, 10, 11,
++      CHROMA_QP_TABLE_END(10) },
++    { 0,  1, 2, 3,  4,  5,
++      6,  7, 8, 9, 10, 11,
++      12,13,14,15, 16, 17,
++      CHROMA_QP_TABLE_END(11) },
++    { 0,  1, 2, 3,  4,  5,
++      6,  7, 8, 9, 10, 11,
++      12,13,14,15, 16, 17,
++      18,19,20,21, 22, 23,
++      CHROMA_QP_TABLE_END(12) },
++    { 0,  1, 2, 3,  4,  5,
++      6,  7, 8, 9, 10, 11,
++      12,13,14,15, 16, 17,
++      18,19,20,21, 22, 23,
++      24,25,26,27, 28, 29,
++      CHROMA_QP_TABLE_END(13) },
++    { 0,  1, 2, 3,  4,  5,
++      6,  7, 8, 9, 10, 11,
++      12,13,14,15, 16, 17,
++      18,19,20,21, 22, 23,
++      24,25,26,27, 28, 29,
++      30,31,32,33, 34, 35,
++      CHROMA_QP_TABLE_END(14) },
++};
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264dec.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264dec.c
+new file mode 100644
+index 000000000..c458e0066
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/h264dec.c
+@@ -0,0 +1,613 @@
++#include "avassert.h"
++#include "avcodec.h"
++#include "h264.h"
++#include "h264dec.h"
++#include "h2645_parse.h"
++#include "h264data.h"
++#include "h264_ps.h"
++#include "golomb.h"
++#include "mathops.h"
++
++
++/**
++ * Init context
++ * Allocate buffers which are not shared amongst multiple threads.
++ */
++
++AVFrame *h264_dequeue_frame(H264Context *h)
++{
++	int index = 0;
++	AVFrame *f = NULL;
++
++	f = list_first_entry_or_null(&h->done_list, AVFrame, done_entry);
++
++	if(!f) {
++		return NULL;
++	}
++
++	/*remove picture from output picture list.*/
++	list_del(&f->done_entry);
++
++	/*返回AVFrame.*/
++	return f;
++}
++
++int h264_enqueue_frame(H264Context *h, AVFrame *f)
++{
++	INIT_LIST_HEAD(&f->queued_entry);
++
++	list_add_tail(&f->queued_entry, &h->queued_list);
++	f->queued = 1;
++
++	return 0;
++}
++
++AVFrame * h264_get_queued_frame(H264Context *h)
++{
++	AVFrame *f = NULL;
++	int i;
++
++	/* 1. AVFrame From DPB, which is in processing. */
++	for (i = 0; i < H264_MAX_PICTURE_COUNT; i++) {
++		f = h->DPB[i].f;
++		if(f && f->queued) {
++			f->queued = 0;
++			return f;
++		}
++	}
++
++	f = list_first_entry_or_null(&h->queued_list, AVFrame, queued_entry);
++	if(!f) {
++		return NULL;
++	}
++
++	/*remove picture from output picture list.*/
++	list_del(&f->queued_entry);
++
++	return f;
++}
++
++static int h264_init_context(AVCodecContext *avctx, H264Context *h)
++{
++    int i;
++    int ret;
++
++    h->avctx                 = avctx;
++    h->cur_chroma_format_idc = -1;
++
++    h->width_from_caller     = avctx->width;
++    h->height_from_caller    = avctx->height;
++    h->format		     = VPU_FORMAT_TILE420;
++
++    h->picture_structure     = PICT_FRAME;
++
++    h->flags                 = avctx->flags;
++    h->poc.prev_poc_msb      = 1 << 16;
++    h->recovery_frame        = -1;
++    h->frame_recovered       = 0;
++    h->poc.prev_frame_num    = -1;
++
++    h->next_outputed_poc = INT_MIN;
++    for (i = 0; i < MAX_DELAYED_PIC_COUNT; i++)
++        h->last_pocs[i] = INT_MIN;
++
++    h->nb_slice_ctx = 1;
++    h->slice_ctx = av_mallocz_array(h->nb_slice_ctx, sizeof(*h->slice_ctx));
++    if (!h->slice_ctx) {
++        h->nb_slice_ctx = 0;
++        return AVERROR(ENOMEM);
++    }
++
++    for (i = 0; i < H264_MAX_PICTURE_COUNT; i++) {
++        h->DPB[i].f = NULL;
++    }
++
++
++    ret = devmem_ctx_init(&h->devmem_ctx, NULL);
++    if(ret < 0) {
++    	return AVERROR(EINVAL);
++    }
++
++
++    h->st_h264 = av_mallocz(sizeof(*h->st_h264));
++    if(!h->st_h264)
++	    return AVERROR(ENOMEM);
++
++    h->dma_desc = av_buffer_alloc(&h->devmem_ctx, DMA_DESC_SIZE);
++    if(!h->dma_desc)
++	    return AVERROR(ENOMEM);
++    memset(h->dma_desc->buffer, 0, DMA_DESC_SIZE);
++
++    ret = vpu_ctx_init(&h->vpu_ctx);
++    if(ret < 0)
++	    return AVERROR(EINVAL);
++    h->vpu_ctx.desc_va = h->dma_desc->buffer;
++    h->vpu_ctx.desc_pa = h->dma_desc->buffer_pa;
++
++    for (i = 0; i < h->nb_slice_ctx; i++)
++        h->slice_ctx[i].h264 = h;
++
++    INIT_LIST_HEAD(&h->done_list);
++    INIT_LIST_HEAD(&h->queued_list);
++
++    return 0;
++}
++
++extern void av_buffer_dump(void);
++int h264_decode_end(AVCodecContext *avctx)
++{
++    H264Context *h = avctx->priv_data;
++    int i;
++
++    ff_h264_remove_all_refs(h);
++
++    for (i = 0; i < H264_MAX_PICTURE_COUNT; i++) {
++        ff_h264_unref_picture(h, &h->DPB[i]);
++	ff_h264_release_picture(h, &h->DPB[i]);
++    }
++    memset(h->delayed_pic, 0, sizeof(h->delayed_pic));
++
++    h->cur_pic_ptr = NULL;
++
++    av_freep(&h->slice_ctx);
++    h->nb_slice_ctx = 0;
++
++    av_buffer_free(&h->devmem_ctx, h->dma_desc);
++
++    av_free(h->st_h264);
++
++
++#if 0
++    ff_h264_sei_uninit(&h->sei);
++#endif
++    ff_h264_ps_uninit(&h->ps);
++
++    ff_h2645_packet_uninit(&h->pkt);
++
++    vpu_ctx_uninit(&h->vpu_ctx);
++    devmem_ctx_uninit(&h->devmem_ctx);
++
++    av_buffer_dump();
++
++    return 0;
++}
++
++//static AVOnce h264_vlc_init = AV_ONCE_INIT;
++
++int h264_decode_init(AVCodecContext *avctx)
++{
++    H264Context *h = avctx->priv_data;
++    int ret;
++
++    ret = h264_init_context(avctx, h);
++    if (ret < 0)
++        return ret;
++
++    ff_h264_flush_change(h);
++
++    av_log(avctx, AV_LOG_ERROR, "h264_decode_init done!\n");
++
++    return 0;
++}
++
++int h264_set_vpu_ops(H264Context *h, void *priv_data, struct vpu_ops *ops)
++{
++	return vpu_ctx_set_ops(&h->vpu_ctx, priv_data, ops);
++}
++
++/**
++ * instantaneous decoder refresh.
++ */
++static void idr(H264Context *h)
++{
++    int i;
++    ff_h264_remove_all_refs(h);
++    h->poc.prev_frame_num        =
++    h->poc.prev_frame_num_offset = 0;
++    h->poc.frame_num= 0;
++    h->poc.prev_poc_msb          = 1<<16;
++    h->poc.prev_poc_lsb          = 0;
++    for (i = 0; i < MAX_DELAYED_PIC_COUNT; i++)
++        h->last_pocs[i] = INT_MIN;
++}
++
++/* forget old pics after a seek */
++void ff_h264_flush_change(H264Context *h)
++{
++    int i, j;
++
++    h->next_outputed_poc = INT_MIN;
++    h->prev_interlaced_frame = 1;
++    idr(h);
++
++    h->poc.prev_frame_num = -1;
++    if (h->cur_pic_ptr) {
++        h->cur_pic_ptr->reference = 0;
++        for (j=i=0; h->delayed_pic[i]; i++)
++            if (h->delayed_pic[i] != h->cur_pic_ptr)
++                h->delayed_pic[j++] = h->delayed_pic[i];
++        h->delayed_pic[j] = NULL;
++    }
++
++    h->first_field = 0;
++    h->recovery_frame = -1;
++    h->frame_recovered = 0;
++    h->current_slice = 0;
++    h->mmco_reset = 1;
++}
++
++/* forget old pics after a seek */
++static void flush_dpb(AVCodecContext *avctx)
++{
++    H264Context *h = avctx->priv_data;
++    int i;
++
++    memset(h->delayed_pic, 0, sizeof(h->delayed_pic));
++
++    ff_h264_flush_change(h);
++#if 0
++    ff_h264_sei_uninit(&h->sei);
++#endif
++
++    for (i = 0; i < H264_MAX_PICTURE_COUNT; i++)
++        ff_h264_unref_picture(h, &h->DPB[i]);
++    h->cur_pic_ptr = NULL;
++
++    h->mb_y = 0;
++
++    h->context_initialized = 0;
++}
++
++static int get_last_needed_nal(H264Context *h)
++{
++    int nals_needed = 0;
++    int first_slice = 0;
++    int i, ret;
++
++    for (i = 0; i < h->pkt.nb_nals; i++) {
++        H2645NAL *nal = &h->pkt.nals[i];
++        GetBitContext gb;
++
++        /* packets can sometimes contain multiple PPS/SPS,
++         * e.g. two PAFF field pictures in one packet, or a demuxer
++         * which splits NALs strangely if so, when frame threading we
++         * can't start the next thread until we've read all of them */
++        switch (nal->type) {
++        case H264_NAL_SPS:
++        case H264_NAL_PPS:
++            nals_needed = i;
++            break;
++        case H264_NAL_DPA:
++        case H264_NAL_IDR_SLICE:
++        case H264_NAL_SLICE:
++            ret = init_get_bits8(&gb, nal->data + 1, nal->size - 1);
++            if (ret < 0) {
++                av_log(h->avctx, AV_LOG_ERROR, "Invalid zero-sized VCL NAL unit\n");
++                if (h->avctx->err_recognition & AV_EF_EXPLODE)
++                    return ret;
++
++                break;
++            }
++            if (!get_ue_golomb_long(&gb) ||  // first_mb_in_slice
++                !first_slice ||
++                first_slice != nal->type)
++                nals_needed = i;
++            if (!first_slice)
++                first_slice = nal->type;
++        }
++    }
++
++    return nals_needed;
++}
++
++static int decode_nal_units(H264Context *h, const uint8_t *buf, int buf_size)
++{
++    AVCodecContext *const avctx = h->avctx;
++    int nals_needed = 0; ///< number of NALs that need decoding before the next frame thread starts
++    int idr_cleared=0;
++    int i, ret = 0;
++
++    h->has_slice = 0;
++    h->nal_unit_type= 0;
++
++#if 0
++    h->current_slice = 0;
++    if (!h->first_field) {
++	    h->cur_pic_ptr = NULL;
++	    ff_h264_sei_uninit(&h->sei);
++    }
++#endif
++
++#if 0
++    if (h->nal_length_size == 4) {
++        if (buf_size > 8 && AV_RB32(buf) == 1 && AV_RB32(buf+5) > (unsigned)buf_size) {
++            h->is_avc = 0;
++        }else if(buf_size > 3 && AV_RB32(buf) > 1 && AV_RB32(buf) <= (unsigned)buf_size)
++            h->is_avc = 1;
++    }
++#endif
++    ret = ff_h2645_packet_split(&h->pkt, buf, buf_size, avctx, 0,
++                                h->nal_length_size, 0);
++    if (ret < 0) {
++        av_log(avctx, AV_LOG_ERROR,
++               "Error splitting the input into NAL units.\n");
++        return ret;
++    }
++
++    if (nals_needed < 0)
++        return nals_needed;
++
++    for (i = 0; i < h->pkt.nb_nals; i++) {
++        H2645NAL *nal = &h->pkt.nals[i];
++        int max_slice_ctx, err;
++        // FIXME these should stop being context-global variables
++        h->nal_ref_idc   = nal->ref_idc;
++        h->nal_unit_type = nal->type;
++
++        err = 0;
++        switch (nal->type) {
++        case H264_NAL_IDR_SLICE:
++            if ((nal->data[1] & 0xFC) == 0x98) {
++                av_log(h->avctx, AV_LOG_ERROR, "Invalid inter IDR frame\n");
++                h->next_outputed_poc = INT_MIN;
++                ret = -1;
++                goto end;
++            }
++            if(!idr_cleared) {
++                idr(h); // FIXME ensure we don't lose some frames if there is reordering
++            }
++            idr_cleared = 1;
++            h->has_recovery_point = 1;
++        case H264_NAL_SLICE:
++            h->has_slice = 1;
++
++	    	/* current_slice = 0 的。。。*/
++            if ((err = ff_h264_queue_decode_slice(h, nal))) {
++		    /*如果入队出错, 将 ref_count都清0.*/
++                H264SliceContext *sl = h->slice_ctx + h->nb_slice_ctx_queued;
++                sl->ref_count[0] = sl->ref_count[1] = 0;
++                break;
++            }
++
++
++            if((ret = ff_h264_execute_decode_slices(h)) < 0) {
++		flush_dpb(h->avctx);
++		printk("===============%s, %d, ret:%d\n", __func__, __LINE__, ret);
++		goto end;
++	    }
++            break;
++        case H264_NAL_DPA:
++        case H264_NAL_DPB:
++        case H264_NAL_DPC:
++            av_log(avctx, AV_LOG_ERROR, "data partitioning");
++            break;
++        case H264_NAL_SEI:
++#if 0
++            ret = ff_h264_sei_decode(&h->sei, &nal->gb, &h->ps, avctx);
++            h->has_recovery_point = h->has_recovery_point || h->sei.recovery_point.recovery_frame_cnt != -1;
++#endif
++#if 0
++            if (avctx->debug & FF_DEBUG_GREEN_MD)
++                debug_green_metadata(&h->sei.green_metadata, h->avctx);
++#endif
++#if 0
++            if (ret < 0 && (h->avctx->err_recognition & AV_EF_EXPLODE))
++                goto end;
++#endif
++            break;
++        case H264_NAL_SPS: {
++            GetBitContext tmp_gb = nal->gb;
++
++            if (ff_h264_decode_seq_parameter_set(&tmp_gb, avctx, &h->ps, 0) >= 0)
++                break;
++
++            av_log(h->avctx, AV_LOG_DEBUG,
++                   "SPS decoding failure, trying again with the complete NAL\n");
++            init_get_bits8(&tmp_gb, nal->raw_data + 1, nal->raw_size - 1);
++            if (ff_h264_decode_seq_parameter_set(&tmp_gb, avctx, &h->ps, 0) >= 0)
++                break;
++            ff_h264_decode_seq_parameter_set(&nal->gb, avctx, &h->ps, 1);
++            break;
++        }
++        case H264_NAL_PPS:
++            ret = ff_h264_decode_picture_parameter_set(&nal->gb, avctx, &h->ps,
++                                                       nal->size_bits);
++
++            if (ret < 0 && (h->avctx->err_recognition & AV_EF_EXPLODE))
++                goto end;
++            break;
++        case H264_NAL_AUD:
++        case H264_NAL_END_SEQUENCE:
++        case H264_NAL_END_STREAM:
++        case H264_NAL_FILLER_DATA:
++        case H264_NAL_SPS_EXT:
++        case H264_NAL_AUXILIARY_SLICE:
++            break;
++        default:
++            av_log(avctx, AV_LOG_DEBUG, "Unknown NAL code: %d (%d bits)\n",
++                   nal->type, nal->size_bits);
++        }
++
++        if (err < 0) {
++            av_log(h->avctx, AV_LOG_ERROR, "decode_slice_header error\n");
++	    ret = AVERROR_INVALIDDATA;
++	    goto end;
++        }
++    }
++
++#if 0
++    ret = ff_h264_execute_decode_slices(h);
++    if (ret < 0 && (h->avctx->err_recognition & AV_EF_EXPLODE))
++        goto end;
++#endif
++    ret = 0;
++end:
++    return (ret < 0) ? ret : buf_size;
++}
++
++/**
++ * Return the number of bytes consumed for building the current frame.
++ */
++static int get_consumed_bytes(int pos, int buf_size)
++{
++    if (pos == 0)
++        pos = 1;        // avoid infinite loops (I doubt that is needed but...)
++    if (pos + 10 > buf_size)
++        pos = buf_size; // oops ;)
++
++    return pos;
++}
++
++static int output_frame(H264Context *h, AVFrame *dst, H264Picture *srcp)
++{
++
++    AVFrame *f = srcp->f;
++
++    f->queued = 0;
++    INIT_LIST_HEAD(&f->done_entry);
++
++    list_add_tail(&f->done_entry, &h->done_list);
++
++    if(dst) {
++	    memcpy(dst, f, sizeof(AVFrame));
++    }
++    return 0;
++}
++
++static int is_extra(const uint8_t *buf, int buf_size)
++{
++    int cnt= buf[5]&0x1f;
++    const uint8_t *p= buf+6;
++    if (!cnt)
++        return 0;
++    while(cnt--){
++        int nalsize= AV_RB16(p) + 2;
++        if(nalsize > buf_size - (p-buf) || (p[2] & 0x9F) != 7)
++            return 0;
++        p += nalsize;
++    }
++    cnt = *(p++);
++    if(!cnt)
++        return 0;
++    while(cnt--){
++        int nalsize= AV_RB16(p) + 2;
++        if(nalsize > buf_size - (p-buf) || (p[2] & 0x9F) != 8)
++            return 0;
++        p += nalsize;
++    }
++    return 1;
++}
++
++static int finalize_frame(H264Context *h, AVFrame *dst, H264Picture *out, int *got_frame)
++{
++    int ret;
++
++     if(out->recovered) {
++
++        ret = output_frame(h, dst, out);
++        if (ret < 0)
++            return ret;
++
++        *got_frame = 1;
++    }
++
++    return 0;
++}
++
++static int send_next_delayed_frame(H264Context *h, AVFrame *dst_frame,
++                                   int *got_frame, int buf_index)
++{
++    int ret, i, out_idx;
++    H264Picture *out = h->delayed_pic[0];
++
++    h->cur_pic_ptr = NULL;
++    h->first_field = 0;
++
++    out_idx = 0;
++    for (i = 1;
++         h->delayed_pic[i] &&
++         !h->delayed_pic[i]->f->key_frame &&
++         !h->delayed_pic[i]->mmco_reset;
++         i++)
++        if (h->delayed_pic[i]->poc < out->poc) {
++            out     = h->delayed_pic[i];
++            out_idx = i;
++        }
++
++    for (i = out_idx; h->delayed_pic[i]; i++)
++        h->delayed_pic[i] = h->delayed_pic[i + 1];
++
++    if (out) {
++        out->reference &= ~DELAYED_PIC_REF;
++        ret = finalize_frame(h, dst_frame, out, got_frame);
++        if (ret < 0)
++            return ret;
++    }
++
++    return buf_index;
++}
++
++/**
++ * @brief 	解�一个packet中包�的帧数�,有�能有数�，有�能没有.通过got_frame指示.
++ *
++ * @param avctx	�柄
++ * @param data	输出buffer.
++ * @param got_frame 是�有数�
++ * @param avpkt 输入数�.
++ *
++ * @return <0，解�出错 >=0 返回消耗的数�长度.
++ */
++int h264_decode_frame(AVCodecContext *avctx, void *data,
++                             int *got_frame, AVPacket *avpkt)
++{
++    const uint8_t *buf = avpkt->data;  /* ��地�*/
++    int buf_size       = avpkt->size;  /* ��大�*/
++    H264Context *h     = avctx->priv_data;
++    AVFrame *pict      = data; /*解�到的buffer.*/
++    int buf_index;
++    int ret;
++
++    h->flags = avctx->flags;
++    h->setup_finished = 0;
++    h->nb_slice_ctx_queued = 0;
++
++    /* end of stream, output what is still in the buffers */
++    if (buf_size == 0)
++        return send_next_delayed_frame(h, pict, got_frame, 0); /*为什么��delayed_frame， �明白. */
++
++    /* *************�点处�的内容 *******/
++    buf_index = decode_nal_units(h, buf, buf_size);
++    if (buf_index < 0)
++        return AVERROR_INVALIDDATA;
++
++    if (!h->cur_pic_ptr && h->nal_unit_type == H264_NAL_END_SEQUENCE) {
++        av_assert0(buf_index <= buf_size);
++        return send_next_delayed_frame(h, pict, got_frame, buf_index);
++    }
++
++
++#if 0
++    if ((!h->cur_pic_ptr || !h->has_slice)) {
++        if (/*avctx->skip_frame >= AVDISCARD_NONREF ||*/
++            buf_size >= 4 && !memcmp("Q264", buf, 4))
++            return buf_size;
++        av_log(avctx, AV_LOG_ERROR, "no frame!\n");
++        return AVERROR_INVALIDDATA;
++    }
++#endif
++
++
++    if(h->mb_y >= h->mb_height && h->mb_height) {
++	    if ((ret = ff_h264_field_end(h, &h->slice_ctx[0], 0)) < 0)
++		    return ret;
++
++	    if (h->next_output_pic) {
++		    ret = finalize_frame(h, pict, h->next_output_pic, got_frame);
++		    if (ret < 0)
++			    return ret;
++	    }
++    }
++
++    return get_consumed_bytes(buf_index, buf_size);
++}
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/hexdump.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/hexdump.c
+new file mode 100644
+index 000000000..1d91aa534
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/hexdump.c
+@@ -0,0 +1,13 @@
++
++void hexdump(unsigned char *buf, int len)
++{
++	int i;
++
++	for (i = 0; i < len; i++) {
++		if ((i % 16) == 0)
++			printf("%s%08x: ", i ? "\n" : "",
++					(unsigned int)&buf[i]);
++		printf("%02x ", buf[i]);
++	}
++	printf("\n");
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/log.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/log.c
+new file mode 100644
+index 000000000..c1d544651
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/log.c
+@@ -0,0 +1,108 @@
++//#include "config.h"
++
++#ifdef __KERNEL__
++#else
++#include <stdarg.h>
++#include <stdlib.h>
++#endif
++#include "common.h"
++//#include "internal.h"
++#include "log.h"
++
++
++#define LINE_SZ 1024
++
++
++static int av_log_level = AV_LOG_INFO;
++static int flags;
++
++#define MAX_LOG_BUFFER_SIZE	1024
++unsigned char print_buffer[MAX_LOG_BUFFER_SIZE];
++void av_log_default_callback(void* ptr, int level, const char* fmt, va_list vl)
++{
++	int n = 0;
++	n = vsprintf(print_buffer, fmt, vl);
++	if(n > MAX_LOG_BUFFER_SIZE) {
++		printf("%s,%d, log too large.!\n", __func__, __LINE__);
++		return;
++	}
++
++	if(level < av_log_level)
++		printf(print_buffer);
++}
++
++static void (*av_log_callback)(void*, int, const char*, va_list) =
++    av_log_default_callback;
++
++void av_log(void* avcl, int level, const char *fmt, ...)
++{
++    va_list vl;
++    va_start(vl, fmt);
++    av_vlog(avcl, level, fmt, vl);
++    va_end(vl);
++}
++
++void av_vlog(void* avcl, int level, const char *fmt, va_list vl)
++{
++    void (*log_callback)(void*, int, const char*, va_list) = av_log_callback;
++    if (log_callback)
++        log_callback(avcl, level, fmt, vl);
++}
++
++int av_log_get_level(void)
++{
++    return av_log_level;
++}
++
++void av_log_set_level(int level)
++{
++    av_log_level = level;
++}
++
++void av_log_set_flags(int arg)
++{
++    flags = arg;
++}
++
++int av_log_get_flags(void)
++{
++    return flags;
++}
++
++void av_log_set_callback(void (*callback)(void*, int, const char*, va_list))
++{
++    av_log_callback = callback;
++
++}
++
++static void missing_feature_sample(int sample, void *avc, const char *msg,
++                                   va_list argument_list)
++{
++    av_vlog(avc, AV_LOG_WARNING, msg, argument_list);
++    av_log(avc, AV_LOG_WARNING, " is not implemented. Update your FFmpeg "
++           "version to the newest one from Git. If the problem still "
++           "occurs, it means that your file has a feature which has not "
++           "been implemented.\n");
++    if (sample)
++        av_log(avc, AV_LOG_WARNING, "If you want to help, upload a sample "
++               "of this file to ftp://upload.ffmpeg.org/incoming/ "
++               "and contact the ffmpeg-devel mailing list. (ffmpeg-devel@ffmpeg.org)\n");
++}
++
++void avpriv_request_sample(void *avc, const char *msg, ...)
++{
++    va_list argument_list;
++
++    va_start(argument_list, msg);
++    missing_feature_sample(1, avc, msg, argument_list);
++    va_end(argument_list);
++}
++
++void avpriv_report_missing_feature(void *avc, const char *msg, ...)
++{
++    va_list argument_list;
++
++    va_start(argument_list, msg);
++    missing_feature_sample(0, avc, msg, argument_list);
++    va_end(argument_list);
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/mathtables.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/mathtables.c
+new file mode 100644
+index 000000000..fd5da07ee
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/mathtables.c
+@@ -0,0 +1,98 @@
++#ifdef __KERNEL__
++#include <linux/types.h>
++#else
++#include <stdint.h>
++#endif
++
++#include "mathops.h"
++
++/* a*inverse[b]>>32 == a/b for all 0<=a<=16909558 && 2<=b<=256
++ * for a>16909558, is an overestimate by less than 1 part in 1<<24 */
++const uint32_t ff_inverse[257]={
++         0, 4294967295U,2147483648U,1431655766, 1073741824,  858993460,  715827883,  613566757,
++ 536870912,  477218589,  429496730,  390451573,  357913942,  330382100,  306783379,  286331154,
++ 268435456,  252645136,  238609295,  226050911,  214748365,  204522253,  195225787,  186737709,
++ 178956971,  171798692,  165191050,  159072863,  153391690,  148102321,  143165577,  138547333,
++ 134217728,  130150525,  126322568,  122713352,  119304648,  116080198,  113025456,  110127367,
++ 107374183,  104755300,  102261127,   99882961,   97612894,   95443718,   93368855,   91382283,
++  89478486,   87652394,   85899346,   84215046,   82595525,   81037119,   79536432,   78090315,
++  76695845,   75350304,   74051161,   72796056,   71582789,   70409300,   69273667,   68174085,
++  67108864,   66076420,   65075263,   64103990,   63161284,   62245903,   61356676,   60492498,
++  59652324,   58835169,   58040099,   57266231,   56512728,   55778797,   55063684,   54366675,
++  53687092,   53024288,   52377650,   51746594,   51130564,   50529028,   49941481,   49367441,
++  48806447,   48258060,   47721859,   47197443,   46684428,   46182445,   45691142,   45210183,
++  44739243,   44278014,   43826197,   43383509,   42949673,   42524429,   42107523,   41698712,
++  41297763,   40904451,   40518560,   40139882,   39768216,   39403370,   39045158,   38693400,
++  38347923,   38008561,   37675152,   37347542,   37025581,   36709123,   36398028,   36092163,
++  35791395,   35495598,   35204650,   34918434,   34636834,   34359739,   34087043,   33818641,
++  33554432,   33294321,   33038210,   32786010,   32537632,   32292988,   32051995,   31814573,
++  31580642,   31350127,   31122952,   30899046,   30678338,   30460761,   30246249,   30034737,
++  29826162,   29620465,   29417585,   29217465,   29020050,   28825284,   28633116,   28443493,
++  28256364,   28071682,   27889399,   27709467,   27531842,   27356480,   27183338,   27012373,
++  26843546,   26676816,   26512144,   26349493,   26188825,   26030105,   25873297,   25718368,
++  25565282,   25414008,   25264514,   25116768,   24970741,   24826401,   24683721,   24542671,
++  24403224,   24265352,   24129030,   23994231,   23860930,   23729102,   23598722,   23469767,
++  23342214,   23216040,   23091223,   22967740,   22845571,   22724695,   22605092,   22486740,
++  22369622,   22253717,   22139007,   22025474,   21913099,   21801865,   21691755,   21582751,
++  21474837,   21367997,   21262215,   21157475,   21053762,   20951060,   20849356,   20748635,
++  20648882,   20550083,   20452226,   20355296,   20259280,   20164166,   20069941,   19976593,
++  19884108,   19792477,   19701685,   19611723,   19522579,   19434242,   19346700,   19259944,
++  19173962,   19088744,   19004281,   18920561,   18837576,   18755316,   18673771,   18592933,
++  18512791,   18433337,   18354562,   18276457,   18199014,   18122225,   18046082,   17970575,
++  17895698,   17821442,   17747799,   17674763,   17602325,   17530479,   17459217,   17388532,
++  17318417,   17248865,   17179870,   17111424,   17043522,   16976156,   16909321,   16843010,
++  16777216
++};
++
++const uint8_t ff_sqrt_tab[256]={
++  0, 16, 23, 28, 32, 36, 40, 43, 46, 48, 51, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 77, 79, 80, 82, 84, 85, 87, 88, 90,
++ 91, 92, 94, 95, 96, 98, 99,100,102,103,104,105,107,108,109,110,111,112,114,115,116,117,118,119,120,121,122,123,124,125,126,127,
++128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,144,145,146,147,148,149,150,151,151,152,153,154,155,156,156,
++157,158,159,160,160,161,162,163,164,164,165,166,167,168,168,169,170,171,171,172,173,174,174,175,176,176,177,178,179,179,180,181,
++182,182,183,184,184,185,186,186,187,188,188,189,190,190,191,192,192,193,194,194,195,196,196,197,198,198,199,200,200,201,202,202,
++203,204,204,205,205,206,207,207,208,208,209,210,210,211,212,212,213,213,214,215,215,216,216,217,218,218,219,219,220,220,221,222,
++222,223,223,224,224,225,226,226,227,227,228,228,229,230,230,231,231,232,232,233,233,234,235,235,236,236,237,237,238,238,239,239,
++240,240,241,242,242,243,243,244,244,245,245,246,246,247,247,248,248,249,249,250,250,251,251,252,252,253,253,254,254,255,255,255
++};
++
++#define times4(x) x, x, x, x
++#define times256(x) times4(times4(times4(times4(times4(x)))))
++
++const uint8_t ff_crop_tab[256 + 2 * MAX_NEG_CROP] = {
++times256(0x00),
++0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,
++0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F,
++0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2A,0x2B,0x2C,0x2D,0x2E,0x2F,
++0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F,
++0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F,
++0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,
++0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,
++0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7A,0x7B,0x7C,0x7D,0x7E,0x7F,
++0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,
++0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,
++0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,
++0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF,
++0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,
++0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF,
++0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,
++0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF,
++times256(0xFF)
++};
++
++const uint8_t ff_zigzag_direct[64] = {
++    0,   1,  8, 16,  9,  2,  3, 10,
++    17, 24, 32, 25, 18, 11,  4,  5,
++    12, 19, 26, 33, 40, 48, 41, 34,
++    27, 20, 13,  6,  7, 14, 21, 28,
++    35, 42, 49, 56, 57, 50, 43, 36,
++    29, 22, 15, 23, 30, 37, 44, 51,
++    58, 59, 52, 45, 38, 31, 39, 46,
++    53, 60, 61, 54, 47, 55, 62, 63
++};
++
++const uint8_t ff_zigzag_scan[16+1] = {
++    0 + 0 * 4, 1 + 0 * 4, 0 + 1 * 4, 0 + 2 * 4,
++    1 + 1 * 4, 2 + 0 * 4, 3 + 0 * 4, 2 + 1 * 4,
++    1 + 2 * 4, 0 + 3 * 4, 1 + 3 * 4, 2 + 2 * 4,
++    3 + 1 * 4, 3 + 2 * 4, 2 + 3 * 4, 3 + 3 * 4,
++};
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/mem.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/mem.c
+new file mode 100644
+index 000000000..d0dadb208
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/mem.c
+@@ -0,0 +1,311 @@
++//#include "config.h"
++
++#ifdef __KERNEL__
++#include <linux/slab.h>
++#define malloc(size)		kmalloc(size, GFP_KERNEL)
++#define realloc(ptr, size)	krealloc(ptr, size, GFP_KERNEL)
++#define free(ptr)		kfree(ptr)
++
++#else
++#include <limits.h>
++#include <stdint.h>
++#include <stdlib.h>
++#include <string.h>
++#include <malloc.h>
++#endif
++
++#include "avassert.h"
++//#include "avutil.h"
++#include "common.h"
++//#include "dynarray.h"
++//#include "intreadwrite.h"
++#include "mem.h"
++
++#if 0
++#ifdef MALLOC_PREFIX
++
++#define malloc         AV_JOIN(MALLOC_PREFIX, malloc)
++#define memalign       AV_JOIN(MALLOC_PREFIX, memalign)
++#define posix_memalign AV_JOIN(MALLOC_PREFIX, posix_memalign)
++#define realloc        AV_JOIN(MALLOC_PREFIX, realloc)
++#define free           AV_JOIN(MALLOC_PREFIX, free)
++
++void *malloc(size_t size);
++void *memalign(size_t align, size_t size);
++int   posix_memalign(void **ptr, size_t align, size_t size);
++void *realloc(void *ptr, size_t size);
++void  free(void *ptr);
++
++#endif /* MALLOC_PREFIX */
++#endif
++
++
++
++/* NOTE: if you want to override these functions with your own
++ * implementations (not recommended) you have to link libav* as
++ * dynamic libraries and remove -Wl,-Bsymbolic from the linker flags.
++ * Note that this will cost performance. */
++
++static size_t max_alloc_size= INT_MAX;
++
++void av_max_alloc(size_t max){
++    max_alloc_size = max;
++}
++
++void *av_malloc(size_t size)
++{
++    void *ptr = NULL;
++
++    /* let's disallow possibly ambiguous cases */
++    if (size > (max_alloc_size - 32))
++        return NULL;
++
++    ptr = malloc(size);
++
++    if(!ptr && !size) {
++        size = 1;
++        ptr= av_malloc(1);
++    }
++
++    return ptr;
++}
++
++void *av_realloc(void *ptr, size_t size)
++{
++    /* let's disallow possibly ambiguous cases */
++    if (size > (max_alloc_size - 32))
++        return NULL;
++
++    return realloc(ptr, size + !size);
++}
++
++void *av_realloc_f(void *ptr, size_t nelem, size_t elsize)
++{
++    size_t size;
++    void *r;
++
++    if (av_size_mult(elsize, nelem, &size)) {
++        av_free(ptr);
++        return NULL;
++    }
++    r = av_realloc(ptr, size);
++    if (!r)
++        av_free(ptr);
++    return r;
++}
++
++int av_reallocp(void *ptr, size_t size)
++{
++    void *val;
++
++    if (!size) {
++        av_freep(ptr);
++        return 0;
++    }
++
++    memcpy(&val, ptr, sizeof(val));
++    val = av_realloc(val, size);
++
++    if (!val) {
++        av_freep(ptr);
++        return AVERROR(ENOMEM);
++    }
++
++    memcpy(ptr, &val, sizeof(val));
++    return 0;
++}
++
++void *av_malloc_array(size_t nmemb, size_t size)
++{
++    if (!size || nmemb >= INT_MAX / size)
++        return NULL;
++    return av_malloc(nmemb * size);
++}
++
++void *av_mallocz_array(size_t nmemb, size_t size)
++{
++    if (!size || nmemb >= INT_MAX / size)
++        return NULL;
++    return av_mallocz(nmemb * size);
++}
++
++void *av_realloc_array(void *ptr, size_t nmemb, size_t size)
++{
++    if (!size || nmemb >= INT_MAX / size)
++        return NULL;
++    return av_realloc(ptr, nmemb * size);
++}
++
++int av_reallocp_array(void *ptr, size_t nmemb, size_t size)
++{
++    void *val;
++
++    memcpy(&val, ptr, sizeof(val));
++    val = av_realloc_f(val, nmemb, size);
++    memcpy(ptr, &val, sizeof(val));
++    if (!val && nmemb && size)
++        return AVERROR(ENOMEM);
++
++    return 0;
++}
++
++void av_free(void *ptr)
++{
++    free(ptr);
++}
++
++void av_freep(void *arg)
++{
++    void *val;
++
++    memcpy(&val, arg, sizeof(val));
++    memcpy(arg, &(void *){ NULL }, sizeof(val));
++    av_free(val);
++}
++
++void *av_mallocz(size_t size)
++{
++    void *ptr = av_malloc(size);
++    if (ptr)
++        memset(ptr, 0, size);
++    return ptr;
++}
++
++void *av_calloc(size_t nmemb, size_t size)
++{
++    if (size <= 0 || nmemb >= INT_MAX / size)
++        return NULL;
++    return av_mallocz(nmemb * size);
++}
++
++char *av_strdup(const char *s)
++{
++    char *ptr = NULL;
++    if (s) {
++        size_t len = strlen(s) + 1;
++        ptr = av_realloc(NULL, len);
++        if (ptr)
++            memcpy(ptr, s, len);
++    }
++    return ptr;
++}
++
++char *av_strndup(const char *s, size_t len)
++{
++    char *ret = NULL, *end;
++
++    if (!s)
++        return NULL;
++
++    end = memchr(s, 0, len);
++    if (end)
++        len = end - s;
++
++    ret = av_realloc(NULL, len + 1);
++    if (!ret)
++        return NULL;
++
++    memcpy(ret, s, len);
++    ret[len] = 0;
++    return ret;
++}
++
++void *av_memdup(const void *p, size_t size)
++{
++    void *ptr = NULL;
++    if (p) {
++        ptr = av_malloc(size);
++        if (ptr)
++            memcpy(ptr, p, size);
++    }
++    return ptr;
++}
++
++void av_memcpy_backptr(uint8_t *dst, int back, int cnt)
++{
++#if 0
++    const uint8_t *src = &dst[-back];
++    if (!back)
++        return;
++
++    if (back == 1) {
++        memset(dst, *src, cnt);
++    } else if (back == 2) {
++        fill16(dst, cnt);
++    } else if (back == 3) {
++        fill24(dst, cnt);
++    } else if (back == 4) {
++        fill32(dst, cnt);
++    } else {
++        if (cnt >= 16) {
++            int blocklen = back;
++            while (cnt > blocklen) {
++                memcpy(dst, src, blocklen);
++                dst       += blocklen;
++                cnt       -= blocklen;
++                blocklen <<= 1;
++            }
++            memcpy(dst, src, cnt);
++            return;
++        }
++        if (cnt >= 8) {
++            AV_COPY32U(dst,     src);
++            AV_COPY32U(dst + 4, src + 4);
++            src += 8;
++            dst += 8;
++            cnt -= 8;
++        }
++        if (cnt >= 4) {
++            AV_COPY32U(dst, src);
++            src += 4;
++            dst += 4;
++            cnt -= 4;
++        }
++        if (cnt >= 2) {
++            AV_COPY16U(dst, src);
++            src += 2;
++            dst += 2;
++            cnt -= 2;
++        }
++        if (cnt)
++            *dst = *src;
++    }
++#endif
++}
++
++void *av_fast_realloc(void *ptr, unsigned int *size, size_t min_size)
++{
++#if 0
++    if (min_size <= *size)
++        return ptr;
++
++    if (min_size > max_alloc_size - 32) {
++        *size = 0;
++        return NULL;
++    }
++
++    min_size = FFMIN(max_alloc_size - 32, FFMAX(min_size + min_size / 16 + 32, min_size));
++
++    ptr = av_realloc(ptr, min_size);
++    /* we could set this to the unmodified min_size but this is safer
++     * if the user lost the ptr and uses NULL now
++     */
++    if (!ptr)
++        min_size = 0;
++
++    *size = min_size;
++#endif
++    return ptr;
++}
++
++#if 0
++void av_fast_malloc(void *ptr, unsigned int *size, size_t min_size)
++{
++    ff_fast_malloc(ptr, size, min_size, 0);
++}
++
++void av_fast_mallocz(void *ptr, unsigned int *size, size_t min_size)
++{
++    ff_fast_malloc(ptr, size, min_size, 1);
++}
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/vpu_ops.c b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/vpu_ops.c
+new file mode 100644
+index 000000000..3684fb631
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/felix/libh264/src/vpu_ops.c
+@@ -0,0 +1,170 @@
++#ifdef __KERNEL__
++#else
++#include <stdio.h>
++#include <sys/types.h>
++#include <sys/stat.h>
++#include <fcntl.h>
++#include <sys/mman.h>
++#endif
++
++#include "vpu_ops.h"
++
++
++static struct vpu_ctx *gvpu_ctx;
++
++int vpu_ctx_set_ops(struct vpu_ctx *ctx, void *priv, struct vpu_ops *ops)
++{
++	ctx->priv = priv;
++	ctx->ops = ops;
++
++	return 0;
++}
++
++#ifdef __KERNEL__
++
++static int vpu_start(void *priv)
++{
++	 return 0;
++}
++
++
++static int vpu_wait(void *priv)
++{
++	int ret = 0;
++
++	return ret;
++}
++
++
++static int vpu_end(void *priv)
++{
++	return 0;
++}
++
++
++struct vpu_ops hw_vpu_ops = {
++	.start = vpu_start,
++	.wait = vpu_wait,
++	.end = vpu_end,
++};
++
++int vpu_ctx_init(struct vpu_ctx *ctx)
++{
++
++	/*ops will be replaced.*/
++	ctx->ops = &hw_vpu_ops;
++	ctx->priv = ctx;
++	gvpu_ctx = ctx;
++	return 0;
++}
++
++
++void vpu_ctx_uninit(struct vpu_ctx *ctx)
++{
++}
++
++
++#else
++
++static int vpu_start(struct vpu_ctx *ctx)
++{
++	unsigned int glbc = 0;
++	int ret = 0;
++	/*reset vpu*/
++	ret = ioctl(ctx->fd, CMD_VPU_RESET, 0);
++
++	/* this function will set st_h264 var dma */
++	glbc = (SCH_GLBC_HIAXI | SCH_INTE_ACFGERR | SCH_INTE_BSERR | SCH_INTE_ENDF);
++	 *((volatile unsigned int *)(ctx->vpu_base + REG_SCH_GLBC)) = glbc;
++
++	 /* start vmd regs config */
++	 *(volatile unsigned int *)(ctx->vpu_base + REG_VDMA_TASKRG) = (ctx->desc_pa & 0xffffff80) | 0x1;
++
++	 return 0;
++}
++
++
++static int vpu_wait(struct vpu_ctx *ctx)
++{
++
++	int vpu_status, ret;
++
++	ret = ioctl(ctx->fd, WAIT_COMPLETE, &vpu_status);
++	if((vpu_status & 0x1) == 1){
++		//printf("wait vpu ops complete done success.\n");
++	} else {
++		printf("vpu sch status=0x%08x,vdma status=0x%08x,vdma dha=0x%08x, sde id=0x%08x,sde cfg0=0x%08x,sde bsaddr=0x%08x\n",
++				*(volatile unsigned int *)(ctx->vpu_base + REG_SCH_STAT),
++				*(volatile unsigned int *)(ctx->vpu_base + REG_VDMA_TASKST),
++				*(volatile unsigned int *)(ctx->vpu_base + REG_VDMA_TASKRG),
++				*(volatile unsigned int *)(ctx->vpu_base + REG_SDE_CODEC_ID),
++				*(volatile unsigned int *)(ctx->vpu_base + REG_SDE_CFG0),
++				*(volatile unsigned int *)(ctx->vpu_base + REG_SDE_CFG2)
++		      );
++
++		printf("sde status=0x%08x\n", *(volatile unsigned int *)(ctx->vpu_base + REG_SDE_STAT));
++	};
++
++	return ret;
++}
++
++
++static int vpu_end(struct vpu_ctx *ctx)
++{
++	printf("vpu_end -----\n");
++
++	return 0;
++}
++
++
++struct vpu_ops hw_vpu_ops = {
++	.start = vpu_start,
++	.wait = vpu_wait,
++	.end = vpu_end,
++};
++
++
++
++
++
++#define VPU_DEVICE_NAME	"/dev/jz-vpu"
++#define VPU_IOSIZE	(0xF0000 - 1)
++int vpu_ctx_init(struct vpu_ctx *ctx)
++{
++	ctx->fd = open("/dev/jz-vpu", O_RDWR);
++	if(ctx->fd < 0) {
++		printf("failed to open vpu devie!\n");
++		return -1;
++	}
++
++	ctx->vpu_base = mmap(NULL, VPU_IOSIZE, PROT_READ | PROT_WRITE, MAP_SHARED,  ctx->fd, VPU_BASE);
++
++	ctx->ops = &hw_vpu_ops;
++	ctx->priv = ctx;
++	gvpu_ctx = ctx;
++	return 0;
++}
++
++void vpu_ctx_uninit(struct vpu_ctx *ctx)
++{
++	close(ctx->fd);
++
++	munmap(ctx->vpu_base, VPU_IOSIZE);
++}
++#endif
++
++int vpu_hw_start(struct vpu_ctx *ctx)
++{
++	return ctx->ops->start(ctx->priv);
++}
++int vpu_hw_wait(struct vpu_ctx *ctx)
++{
++	return ctx->ops->wait(ctx->priv);
++}
++
++int vpu_hw_end(struct vpu_ctx *ctx)
++{
++	return ctx->ops->end(ctx->priv);
++}
++
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/Makefile b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/Makefile
+new file mode 100644
+index 000000000..934baeea2
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/Makefile
+@@ -0,0 +1,17 @@
++ingenic_helix-y :=	helix_drv.o \
++			jpge.o \
++			jpgd.o \
++			default_sliceinfo.o \
++			helix_ops.o \
++			api/helix_x264_enc.o \
++			api/helix_jpeg_enc.o \
++			api/helix_jpeg_dec.o \
++			h264enc/set.o  \
++			h264enc/cabac.o \
++			h264enc/common.o \
++			h264enc/slice.o \
++			h264e_rc.o \
++			h264e_rc_nl.o
++
++obj-$(CONFIG_INGENIC_HELIX) += ingenic_helix.o
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/README b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/README
+new file mode 100644
+index 000000000..7b97beed1
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/README
+@@ -0,0 +1,4 @@
++
++helix-drv.c   <---- v4l2 implementation.
++helix-ctrl.c  <---- helix controller driver.
++helix-x264-enc.c <---- encoder APIs.
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix.h
+new file mode 100755
+index 000000000..071117e92
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix.h
+@@ -0,0 +1,3459 @@
++/****************************************************************
++*****************************************************************/
++#ifndef __HELIX_H__
++#define __HELIX_H__
++
++/****************************************************************
++  VPU register map
++*****************************************************************/
++#define JZM_V2_TLB
++
++#ifdef JZM_HUNT_SIM
++#include "hunt.h"
++#else
++#ifndef __place_k0_data__
++#define __place_k0_data__
++#endif
++#ifndef __place_k0_text__
++#define __place_k0_text__
++#endif
++#endif
++
++#define VPU_BASE             0x13300000
++
++#define	HID_SCH	             0x0
++#define	HID_JRFD	     0x1
++#define	HID_EMC	             0x3
++#define	HID_EFE	             0x4
++#define	HID_MCE		     0x5
++#define HID_ODMA             0x6
++#define	HID_DBLK	     0x7
++#define	HID_VMAU	     0x8
++#define	HID_SDE		     0x9
++#define	HID_AUX		     0xA
++#define	HID_TCSM	     0xB
++#define	HID_IFA	             0xB //fixme
++#define	HID_JPGC	     0xE
++#define HID_SRAM             0xF
++
++#define VPU_MAX_MB_WIDTH     256
++
++#define MSCOPE_START(mbnum)  write_reg(VPU_BASE+0x24, mbnum)
++#define MSCOPE_STOP()        write_reg(VPU_BASE+0x28, 0)
++
++/********************************************
++  SCH (Scheduler)
++*********************************************/
++#define TCSM_FLUSH           0xc0000
++#define REG_SCH_GLBC         0x00000
++#define SCH_GLBC_SLDE        (0x1<<31)
++#ifdef JZM_V2_TLB
++# define SCH_TLBE_JPGC       (0x1<<26)
++# define SCH_TLBE_DBLK       (0x1<<25)
++# define SCH_TLBE_SDE        (0x1<<24)
++# define SCH_TLBE_EFE        (0x1<<23)
++# define SCH_TLBE_VDMA       (0x1<<22)
++# define SCH_TLBE_MCE        (0x1<<21)
++#else
++# define SCH_GLBC_TLBE       (0x1<<30)
++# define SCH_GLBC_TLBINV     (0x1<<29)
++#endif
++#define SCH_INTE_RESERR      (0x1<<29)
++#define SCH_INTE_BSFULL      (0x1<<28)
++#define SCH_INTE_ACFGERR     (0x1<<20)
++#define SCH_INTE_TLBERR      (0x1<<18)
++#define SCH_INTE_BSERR       (0x1<<17)
++#define SCH_INTE_ENDF        (0x1<<16)
++#define SCH_GLBC_HIMAP       (0x1<<15)
++#define SCH_GLBC_HIAXI       (0x1<<9)
++#define SCH_GLBC_EPRI0       (0x0<<7)
++#define SCH_GLBC_EPRI1       (0x1<<7)
++#define SCH_GLBC_EPRI2       (0x2<<7)
++#define SCH_GLBC_EPRI3       (0x3<<7)
++
++#define REG_SCH_TLBA         0x00030
++
++#ifdef JZM_V2_TLB
++# define REG_SCH_TLBC        0x00050
++# define SCH_TLBC_VPN        (0xFFFFF000)
++# define SCH_TLBC_RIDX(idx)  (((idx) & 0xFF)<<4)
++# define SCH_TLBC_INVLD      (0x1<<1)
++# define SCH_TLBC_RETRY      (0x1<<0)
++
++# define REG_SCH_TLBV        0x00054
++# define SCH_TLBV_CNM(cnm)   (((cnm) & 0xFFF)<<16)
++# define SCH_TLBV_GCN(gcn)   (((gcn) & 0xFFF)<<0)
++# define SCH_TLBV_RCI_MC     (0x1<<30)
++# define SCH_TLBV_RCI_EFE    (0x1<<31)
++#endif
++
++#define REG_SCH_STAT         0x00034
++#define SCH_STAT_ENDF    (0x1<<0)  
++#define SCH_STAT_BPF     (0x1<<1)  
++#define SCH_STAT_ACFGERR (0x1<<2)  
++#define SCH_STAT_TIMEOUT (0x1<<3)  
++#define SCH_STAT_JPGEND  (0x1<<4)  
++#define SCH_STAT_BSERR   (0x1<<7)  
++#define SCH_STAT_TLBERR  (0x1F<<10)
++#define SCH_STAT_SLDERR  (0x1<<16) 
++
++
++#define REG_SCH_SLDE0        0x00040
++#define REG_SCH_SLDE1        0x00044
++#define REG_SCH_SLDE2        0x00048
++#define REG_SCH_SLDE3        0x0004C
++#define SCH_SLD_VTAG(val)    (((val) & 0xFFF)<<20)
++#define SCH_SLD_MASK(val)    (((val) & 0xFFF)<<8)
++#define SCH_SLD_VLD          (0x1<<0)
++
++#define REG_SCH_SCHC         0x00060
++#define SCH_CH1_PCH(ch)      (((ch) & 0x3)<<0)
++#define SCH_CH2_PCH(ch)      (((ch) & 0x3)<<8)
++#define SCH_CH3_PCH(ch)      (((ch) & 0x3)<<16)
++#define SCH_CH4_PCH(ch)      (((ch) & 0x3)<<24)
++#define SCH_CH1_PE           (0x1<<2)
++#define SCH_CH2_PE           (0x1<<10)
++#define SCH_CH3_PE           (0x1<<18)
++#define SCH_CH4_PE           (0x1<<26)
++#define SCH_CH1_GS0          (0x0<<3)
++#define SCH_CH1_GS1          (0x1<<3)
++#define SCH_CH2_GS0          (0x0<<11)
++#define SCH_CH2_GS1          (0x1<<11)
++#define SCH_CH3_GS0          (0x0<<19)
++#define SCH_CH3_GS1          (0x1<<19)
++#define SCH_CH4_GS0          (0x0<<27)
++#define SCH_CH4_GS1          (0x1<<27)
++
++#define REG_SCH_BND          0x00064
++#define SCH_CH1_HID(hid)     (((hid) & 0xF)<<16)       
++#define SCH_CH2_HID(hid)     (((hid) & 0xF)<<20)
++#define SCH_CH3_HID(hid)     (((hid) & 0xF)<<24)       
++#define SCH_CH4_HID(hid)     (((hid) & 0xF)<<28)       
++#define SCH_BND_G0F1         (0x1<<0)
++#define SCH_BND_G0F2         (0x1<<1)
++#define SCH_BND_G0F3         (0x1<<2)
++#define SCH_BND_G0F4         (0x1<<3)
++#define SCH_BND_G1F1         (0x1<<4)
++#define SCH_BND_G1F2         (0x1<<5)
++#define SCH_BND_G1F3         (0x1<<6)
++#define SCH_BND_G1F4         (0x1<<7)
++#define SCH_DEPTH(val)       (((val-1) & 0xF)<<8)
++
++#define REG_SCH_SCHG0        0x00068
++#define REG_SCH_SCHG1        0x0006C
++#define REG_SCH_SCHE1        0x00070
++#define REG_SCH_SCHE2        0x00074
++#define REG_SCH_SCHE3        0x00078
++#define REG_SCH_SCHE4        0x0007C
++
++#define DSA_SCH_CH1          (VPU_BASE | REG_SCH_SCHE1)
++#define DSA_SCH_CH2          (VPU_BASE | REG_SCH_SCHE2)
++#define DSA_SCH_CH3          (VPU_BASE | REG_SCH_SCHE3)
++#define DSA_SCH_CH4          (VPU_BASE | REG_SCH_SCHE4)
++
++/********************************************
++  SW_RESET (VPU software reset)
++*********************************************/
++#define REG_CFGC_SW_RESET    0x00004
++#define CFGC_SW_RESET_RST         (0x1<<1)
++#define CFGC_SW_RESET_RST_CLR     (0x0<<1)
++#define CFGC_SW_RESET_EARB_EMPT   (0x4)
++/********************************************
++  VDMA (VPU general-purpose DMA)
++*********************************************/
++#define REG_VDMA_LOCK        0x10000
++#define REG_VDMA_UNLK        0x10004
++
++#define REG_VDMA_TASKRG      0x10008
++#define VDMA_ACFG_RUN        (0x1)
++#define VDMA_DESC_RUN        (0x3)
++#define VDMA_ACFG_CLR        (0x8)
++#define VDMA_ACFG_SAFE       (0x4)
++#define VDMA_ACFG_DHA(a)     (((unsigned int)(a)) & 0xFFFFFF80)
++#define VDMA_DESC_DHA(a)     (((unsigned int)(a)) & 0xFFFF0)
++
++#define REG_CFGC_ACM_CTRL    0x00084
++#define REG_CFGC_ACM_STAT    0x00088
++#define REG_CFGC_ACM_DHA     0x0008C
++
++#define REG_VDMA_TASKST      0x1000C
++#define VDMA_ACFG_ERR        (0x1<<3)
++#define VDMA_ACFG_END        (0x1<<2)
++#define VDMA_DESC_END        (0x1<<1)
++#define VDMA_VPU_BUSY        (0x1<<0)
++
++#define VDMA_DESC_EXTSEL     (0x1<<0)
++#define VDMA_DESC_TLBSEL     (0x1<<1)
++#define VDMA_DESC_LK         (0x1<<31)
++
++#define VDMA_ACFG_VLD        (0x1<<31)
++#define VDMA_ACFG_TERM       (0x1<<30)
++#define VDMA_ACFG_IDX(a)     (((unsigned int)(a)) & 0xFFFFC)
++
++#ifdef RW_REG_TEST
++#define GEN_VDMA_ACFG(chn, reg, term, val)  write_reg(VPU_BASE+(reg), val)
++#else
++#define GEN_VDMA_ACFG(chn, reg, term, val)			\
++  ({*chn++ = val;						\
++    *chn++ = (VDMA_ACFG_VLD | (term) | VDMA_ACFG_IDX(reg));	\
++  })
++#endif
++
++#define REG_EMC_FRM_SIZE     0x30000
++#define REG_EMC_BS_ADDR      0x30004
++#define REG_EMC_DBLK_ADDR    0x30008
++#define REG_EMC_RECON_ADDR   0x3000c
++#define REG_EMC_MV_ADDR      0x30010
++#define REG_EMC_SE_ADDR      0x30014
++#define REG_EMC_QPT_ADDR     0x30018
++#define REG_EMC_RC_RADDR     0x3001c
++#define REG_EMC_MOS_ADDR     0x30020
++#define REG_EMC_SLV_INIT     0x30024
++#define REG_EMC_DEBUG_INFO0  0x30028
++#define REG_EMC_DEBUG_INFO1  0x3002c
++#define REG_EMC_CRC_INFO0    0x30030
++#define REG_EMC_CRC_INFO1    0x30034
++#define REG_EMC_CRC_INFO2    0x30038
++#define REG_EMC_CRC_INFO3    0x3003c
++#define REG_EMC_BS_SIZE      0x30040
++#define REG_EMC_BS_STAT      0x30044
++#define REG_EMC_RC_WADDR     0x30048
++#define REG_EMC_CPX_ADDR     0x3004c
++#define REG_EMC_MOD_ADDR     0x30050
++#define REG_EMC_SAD_ADDR     0x30054
++#define REG_EMC_NCU_ADDR     0x30058
++
++/********************************************
++  EFE (Encoder Front End)
++*********************************************/
++#define REG_EFE_CTRL         0x40000
++#define EFE_TSE(en)          (((en) & 0x1)<<31)
++#define EFE_FMVP(en)         (((en) & 0x1)<<30)
++#define EFE_ID_X264          (0x0<<14)
++#define EFE_ID_JPEG          (0x1<<14)
++#define EFE_ID_VP8           (0x2<<14)
++#define EFE_X264_QP(qp)      (((qp) & 0x3F)<<8)
++#define EFE_VP8_QTB(qtb)     (((qtb) & 0x7f)<<22)
++#define EFE_VP8_QIDX(qp)     (((qp) & 0x3F)<<8)
++#define EFE_VP8_LF(lf)       ((lf & 0x3F)<<16)
++#define EFE_HALN8_FLAG(en)   (((en) & 0x1)<<7)
++#define EFE_STEP_MODE(en)    (((en) & 0x1)<<6)
++#define EFE_DBLK_EN          (0x1<<5)
++#define EFE_SLICE_TYPE(a)    (((a) & 0x1)<<4)
++#define EFE_PLANE_TILE       (0x0<<2)
++#define EFE_PLANE_420P       (0x1<<2)
++#define EFE_PLANE_NV12       (0x2<<2)
++#define EFE_PLANE_NV21       (0x3<<2)
++#define EFE_EN               (0x1<<1)
++#define EFE_RUN              (0x1<<0)
++
++#define REG_EFE_GEOM         0x40004
++#define EFE_FST_MBY(mb)      (((mb) & 0xFF)<<24)
++#define EFE_FST_MBX(mb)      (((0/*FIXME*/) & 0xFF)<<16)
++#define EFE_LST_MBY(mb)      (((mb) & 0xFF)<<8)
++#define EFE_LST_MBX(mb)      (((mb) & 0xFF)<<0)
++#define EFE_JPGC_LST_MBY(mb) (((mb) & 0xFFFF)<<16)
++#define EFE_JPGC_LST_MBX(mb) ((mb) & 0xFFFF)
++
++#define REG_EFE_COEF_BA      0x4000C
++#define REG_EFE_RAWY_SBA     0x40010
++#define REG_EFE_RAWC_SBA     0x40014
++#define REG_EFE_RAWU_SBA     0x40014
++#define REG_EFE_TOPMV_BA     0x40018
++#define REG_EFE_TOPPA_BA     0x4001C
++#define REG_EFE_MECHN_BA     0x40020
++#define REG_EFE_MAUCHN_BA    0x40024
++#define REG_EFE_DBLKCHN_BA   0x40028
++#define REG_EFE_SDECHN_BA    0x4002C
++#define REG_EFE_RAW_DBA      0x40030
++#define REG_EFE_RAWV_SBA     0x40034
++
++#define REG_EFE_ROI_MAX_QP       0x40040
++#define REG_EFE_ROI_BASE_INFO0   0x40044
++#define REG_EFE_ROI_BASE_INFO1   0x40048
++#define REG_EFE_ROI_POS_INFO0    0x4004C
++#define REG_EFE_ROI_POS_INFO1    0x40050
++#define REG_EFE_ROI_POS_INFO2    0x40054
++#define REG_EFE_ROI_POS_INFO3    0x40058
++#define REG_EFE_ROI_POS_INFO4    0x4005C
++#define REG_EFE_ROI_POS_INFO5    0x40060
++#define REG_EFE_ROI_POS_INFO6    0x40064
++#define REG_EFE_ROI_POS_INFO7    0x40068
++
++#define REG_EFE_QP_GEN_TAB       0x4006C
++
++#define REG_EFE_QPG_CTRL         0x40074
++#define REG_EFE_QPG_CFG0         0x40078
++#define REG_EFE_QPG_CFG1         0x4007C
++#define REG_EFE_QPG_CFG2         0x40080
++#define REG_EFE_QPG_CFG3         0x40084
++#define REG_EFE_QPG_CFG4         0x40088
++#define REG_EFE_QPG_CFG5         0x4008C
++#define REG_EFE_QPG_CFG6         0x40090
++#define REG_EFE_QPG_RGNC_A       0x40094
++#define REG_EFE_QPG_RGNC_B       0x40098
++#define REG_EFE_QPG_RGNC_C       0x4009C
++#define REG_EFE_QPG_RGNC_D       0x400A0
++#define REG_EFE_QP_SUM           0x400A4
++
++#define	REG_EFE_EIGEN_CFG0	 0x400C0
++#define	REG_EFE_EIGEN_CFG1	 0x400C4
++#define	REG_EFE_EIGEN_CFG2	 0x400C8
++#define	REG_EFE_EIGEN_CFG3	 0x400CC
++#define	REG_EFE_EIGEN_CFG4	 0x400D0
++#define	REG_EFE_EIGEN_CFG5	 0x400D4
++#define	REG_EFE_EIGEN_CFG6	 0x400D8
++#define	REG_EFE_DIFFY_CFG	 0x400DC
++#define	REG_EFE_DIFFU_CFG	 0x400E0
++#define	REG_EFE_DIFFV_CFG	 0x400E4
++
++#define	REG_EFE_SKIN_CTRL	 0x400AC
++#define	REG_EFE_SKIN_PTHD0	 0x400B0
++#define	REG_EFE_SKIN_PTHD1	 0x400B4
++#define	REG_EFE_SKIN_PTHD2	 0x400B8
++#define	REG_EFE_SKIN_QP_OFST	 0x400BC
++#define	REG_EFE_SKIN_PARAM0	 0x400E8
++#define	REG_EFE_SKIN_PARAM1	 0x400EC
++#define	REG_EFE_SKIN_PARAM2	 0x400F0
++
++#define REG_EFE_RAW_STRD     0x40038
++#define EFE_RAW_STRDY(y)     (((y) & 0xFFFF)<<16)
++#define EFE_RAW_STRDC(c)     (((c) & 0xFFFF)<<0)
++
++#define REG_EFE_DBG_INFO     0x4003C
++#define EFE_DBG_EN           (0x1<<31)
++#define EFE_DBG_BP_MBX(x)    (((x) & 0xFFF)<<0)
++#define EFE_DBG_BP_MBY(y)    (((y) & 0xFFF)<<16)
++
++#define REG_EFE_MVRP         0x40100
++#define REG_EFE_SSAD         0x40108
++#define REG_EFE_DCS          0x4010C
++#define EFE_DCS_CLR(th)      (0x1<<(th & 0xF))
++#define EFE_DCS_EN(en)       (((en) & 0x1)<<16)
++#define EFE_DCS_RT(rt)       (((rt) & 0xF)<<20)
++#define EFE_DCS_OTH(oth)     (((oth) & 0xF)<<24)
++#define REG_EFE_STAT         0x40110
++#define REG_EFE_CQP_OFST     0x40120
++
++#define EFE_RC_QPO_CFG(c4, c3, c2, c1)		\
++( ((c4) & 0x3F)<<18 |                           \
++  ((c3) & 0x3F)<<12 |                           \
++  ((c2) & 0x3F)<<6 |                            \
++  ((c1) & 0x3F)<<0                              \
++)
++
++#define REG_EFE_RC_MINFO    0x40128
++#define EFE_RC_MB_EN        (0x1<<0)
++#define EFE_RC_MBGP_NUM(a)  (((a) & 0x3fff)<<1)
++#define EFE_RC_MAD_CFG_RDY  (0x1<<15)
++#define REG_EFE_RC_BINFO0   0x4012C
++#define EFE_RC_BU_EN        (0x1<<0)
++#define EFE_RC_BU_NUM(a)    (((a) & 0x7f)<<1)
++#define EFE_RC_BU_CFG(a)    (((a) & 0x1)<<8)
++#define EFE_RC_SLICE_TP(a)  (((a) & 0x1)<<10)
++#define REG_EFE_RC_BINFO1   0x40130
++#define EFE_RC_BU_SIZE(a)   (((a) & 0x3fff)<<0)
++#define EFE_RC_BU_LSIZE(a)  (((a) & 0x3fff)<<14)
++#define REG_EFE_RC_GP0THD   0x40134
++#define REG_EFE_RC_GP1THD    0x40138
++#define REG_EFE_RC_GP2THD    0x4013C
++#define REG_EFE_RC_TBS      0x40140
++#define REG_EFE_RC_BNQA0    0x40144
++#define REG_EFE_RC_BPQA0    0x40148
++#define REG_EFE_RC_BNQA1    0x4014C
++#define REG_EFE_RC_BPQA1    0x40150
++#define REG_EFE_RC_MNQCS    0x40154
++#define REG_EFE_RC_MPQCS    0x40158
++#define REG_EFE_RC_MTBQ     0x4015C
++#define REG_EFE_RC_MRFQ     0x40160
++#define REG_EFE_RC_MAMIN    0x40164
++#define REG_EFE_RC_MAMAX    0x40168
++#define REG_EFE_RC_BBS      0x4016C
++
++/********************************************
++  MCE (Motion Compensation/Estimation COMBO)
++*********************************************/
++//GLB_CTRL
++#define REG_MCE_GLB_CTRL        0x50000
++#define MCE_GLB_CTRL_FMV0(a)    (((a) & 0xf)<<31)
++#define MCE_GLB_CTRL_STEP1(a)   (((a) & 0xf)<<27)
++#define MCE_GLB_CTRL_STEP0(a)   (((a) & 0xf)<<23)
++#define MCE_GLB_CTRL_MSTEP(a)   (((a) & 0x1)<<22)
++#define MCE_GLB_CTRL_RBS(a)     (((a) & 0xff)<<14)
++#define MCE_GLB_CTRL_FMS(a)     (((a) & 0x7)<<11)
++#define MCE_GLB_CTRL_FRMMV(a)   (((a) & 0x1)<<10)
++#define MCE_GLB_CTRL_GLBMV(a)   (((a) & 0x1)<<9)
++#define MCE_GLB_CTRL_DCT8(a)    (((a) & 0x1)<<8)
++#define MCE_GLB_CTRL_JRFD(a)    (((a) & 0x1)<<7)
++#define MCE_GLB_CTRL_MREF(a)    (((a) & 0x1)<<6)
++#define MCE_GLB_CTRL_PSKIP(a)   (((a) & 0x1)<<5)
++#define MCE_GLB_CTRL_RM(a)      (((a) & 0x1)<<4)
++#define MCE_GLB_CTRL_BF         (0x1<<3)
++#define MCE_GLB_CTRL_CGE        (0x1<<2)
++#define MCE_GLB_CTRL_WM         (0x1<<1)
++#define MCE_GLB_CTRL_INIT       (0x1<<0)
++
++//COMP_CTRL
++#define REG_MCE_COMP_CTRL       0x50010
++#define MCE_COMP_CTRL_CCE       (0x1<<31)
++#define MCE_COMP_CTRL_CWT(a)    (((a) & 0x3)<<26)
++#define MCE_COMP_CTRL_CRR       (0x1<<25)
++#define MCE_COMP_CTRL_CIC       (0x1<<24)
++#define MCE_COMP_CTRL_CAT       (0x1<<23)
++#define MCE_COMP_CTRL_CTAP(a)   (((a) & 0x3)<<20)
++#define MCE_COMP_CTRL_CSPT(a)   (((a) & 0x3)<<18)
++#define MCE_COMP_CTRL_CSPP(a)   (((a) & 0x3)<<16)
++#define MCE_COMP_CTRL_YCE       (0x1<<15)
++#define MCE_COMP_CTRL_YWT(a)    (((a) & 0x3)<<10)
++#define MCE_COMP_CTRL_YRR       (0x1<<9)
++#define MCE_COMP_CTRL_YIC       (0x1<<8)
++#define MCE_COMP_CTRL_YAT       (0x1<<7)
++#define MCE_COMP_CTRL_YTAP(a)   (((a) & 0x3)<<4)
++#define MCE_COMP_CTRL_YSPT(a)   (((a) & 0x3)<<2)
++#define MCE_COMP_CTRL_YSPP(a)   (((a) & 0x3)<<0)
++
++#define MCE_WT_BIAVG            0
++#define MCE_WT_UNIWT            1
++#define MCE_WT_BIWT             2
++#define MCE_WT_IMWT             3
++
++#define MCE_TAP_TAP2            0
++#define MCE_TAP_TAP4            1
++#define MCE_TAP_TAP6            2
++#define MCE_TAP_TAP8            3
++
++#define MCE_SPT_AUTO            0
++#define MCE_SPT_SPEC            1
++#define MCE_SPT_BILI            2
++#define MCE_SPT_SYMM            3
++
++#define MCE_SPP_HPEL            0
++#define MCE_SPP_QPEL            1
++#define MCE_SPP_EPEL            2
++
++//ESTI_CTRL
++#define REG_MCE_ESTI_CTRL       0x50040
++#define MCE_ESTI_CTRL_LSP(a)    (((a) & 0xF)<<28)
++#define MCE_ESTI_CTRL_FBG(a)    (((a) & 0x1)<<27)
++#define MCE_ESTI_CTRL_CLMV      (0x1<<26)
++#define MCE_ESTI_CTRL_SCL(a)    (((a) & 0x3)<<24)
++#define MCE_ESTI_CTRL_MSS(a)    (((a) & 0xFF)<<16)
++#define MCE_ESTI_CTRL_QRL(a)    (((a) & 0x3)<<14)
++#define MCE_ESTI_CTRL_HRL(a)    (((a) & 0x3)<<12)
++#define MCE_ESTI_CTRL_BDIR(a)   (((a) & 0x1)<<10)
++#define MCE_ESTI_CTRL_PUE_64X64 (0x1<<9)
++#define MCE_ESTI_CTRL_PUE_32X32 (0x1<<6)
++#define MCE_ESTI_CTRL_PUE_32X16 (0x1<<5)
++#define MCE_ESTI_CTRL_PUE_16X32 (0x1<<4)
++#define MCE_ESTI_CTRL_PUE_16X16 (0x1<<3)
++#define MCE_ESTI_CTRL_PUE_16X8  (0x1<<2)
++#define MCE_ESTI_CTRL_PUE_8X16  (0x1<<1)
++#define MCE_ESTI_CTRL_PUE_8X8   (0x1<<0)
++
++//MRGI
++#define REG_MCE_MRGI            0x50044
++#define MCE_MRGI_MRGE_64X64     (0x1<<9)
++#define MCE_MRGI_MRGE_32X32     (0x1<<6)
++#define MCE_MRGI_MRGE_32X16     (0x1<<5)
++#define MCE_MRGI_MRGE_16X32     (0x1<<4)
++#define MCE_MRGI_MRGE_16X16     (0x1<<3)
++#define MCE_MRGI_MRGE_16X8      (0x1<<2)
++#define MCE_MRGI_MRGE_8X16      (0x1<<1)
++#define MCE_MRGI_MRGE_8X8       (0x1<<0)
++
++//MVR
++#define REG_MCE_MVR             0x50048
++#define MCE_MVR_MVRY(a)         (((a) & 0xFFFF)<<16)
++#define MCE_MVR_MVRX(a)         (((a) & 0xFFFF)<<0)
++
++//FRM_SIZE
++#define REG_MCE_FRM_SIZE        0x50060
++#define MCE_FRM_SIZE_FH(a)      (((a) & 0xFFFF)<<16)
++#define MCE_FRM_SIZE_FW(a)      (((a) & 0xFFFF)<<0)
++#define MCE_FRM_SIZE_LRE(a)     (((a) & 0x1)<<14)
++#define MCE_FRM_SIZE_RRE(a)     (((a) & 0x1)<<15)
++#define MCE_FRM_SIZE_TRE(a)     (((a) & 0x1)<<30)
++#define MCE_FRM_SIZE_BRE(a)     (((a) & 0x1)<<31)
++
++//FSC
++#define REG_MCE_FSC             0x5004C
++#define MCE_FSC_FSE(a)          (((a) & 0x1)<<31)
++#define MCE_FSC_FSMD(a)          (((a) & 0x1)<<30)
++#define MCE_FSC_RECY(a)         (((a) & 0x7F)<<24)
++#define MCE_FSC_RECX(a)         (((a) & 0xFF)<<16)
++#define MCE_FSC_PERY(a)         (((a) & 0xFF)<<8)
++#define MCE_FSC_PERX(a)         (((a) & 0xFF)<<0)
++
++//FRM_STRD
++#define REG_MCE_FRM_STRD        0x50064
++#define MCE_FRM_STRD_STRDC(a)   (((a) & 0xFFFF)<<16)
++#define MCE_FRM_STRD_STRDY(a)   (((a) & 0xFFFF)<<0)
++
++//SLC_SPOS
++#define REG_MCE_SLC_SPOS        0x50068
++#define MCE_SLC_SPOS_CU64Y(a)   (((a) & 0xFF)<<8)
++#define MCE_SLC_SPOS_CU64X(a)   (((a) & 0xFF)<<0)
++
++//REF
++#define REG_MCE_REFY0        0x5006C
++#define REG_MCE_REFC0        0x50070
++
++#define REG_MCE_REFY1        0x50074
++#define REG_MCE_REFC1        0x50078
++
++#define REG_MCE_REFY0_1      0x50110  //!!!
++#define REG_MCE_REFC0_1      0x50114
++
++//GLB MV
++#define REG_MCE_GLB_MV       0x5007C
++#define MCE_GLB_MVX(a)       (((a) & 0xFFF)<<0)
++#define MCE_GLB_MVY(a)       (((a) & 0xFFF)<<16)
++
++//RLUT
++#define SLUT_MCE_RLUT(l, i)     (0x50800 + (i)*8 + (l)*0x80)
++
++//ILUT
++#define SLUT_MCE_ILUT_Y         0x50900
++#define SLUT_MCE_ILUT_C         0x50980
++#define MCE_ILUT_INFO(fir, clip, idgl, edgl, dir,        \
++                      rnd, sft, savg, srnd, sbias)       \
++( ((fir) & 0x1)<<31 |                                    \
++  ((clip) & 0x1)<<27 |                                   \
++  ((idgl) & 0x1)<<26 |                                   \
++  ((edgl) & 0x1)<<25 |                                   \
++  ((dir) & 0x1)<<24 |                                    \
++  ((rnd) & 0xFF)<<16 |                                   \
++  ((sft) & 0xF)<<8 |                                     \
++  ((savg) & 0x1)<<2 |                                    \
++  ((srnd) & 0x1)<<1 |                                    \
++  ((sbias) & 0x1)<<0                                     \
++)
++
++//CLUT
++#define SLUT_MCE_CLUT_Y         0x50A00
++#define SLUT_MCE_CLUT_C         0x50B00
++#define MCE_CLUT_INFO(c4, c3, c2, c1)                    \
++( ((c4) & 0xFF)<<24 |                                    \
++  ((c3) & 0xFF)<<16 |                                    \
++  ((c2) & 0xFF)<<8 |                                     \
++  ((c1) & 0xFF)<<0                                       \
++)
++
++//CHAIN/TMV/SYNC ADDR
++
++#define REG_MCE_TMV_BA          0x50104
++#define REG_MCE_CHN_SYNC        0x50108
++#define REG_MCE_CHN_BA          0x5010C
++
++/********************************************
++  VMAU (VPU Matrix Arithmetic Unit)
++*********************************************/
++#define REG_VMAU_MCBP        0x80000
++
++#define REG_VMAU_QTPARA      0x80004
++
++#define REG_VMAU_MAIN_ADDR   0x80008
++
++#define REG_VMAU_NCCHN_ADDR  0x8000C
++
++#define REG_VMAU_CHN_LEN     0x80010
++
++#define REG_VMAU_ACBP        0x80014
++
++#define REG_VMAU_CPREDM_TLV  0x80018
++
++#define REG_VMAU_YPREDM0     0x8001C
++
++#define REG_VMAU_YPREDM1     0x80020
++
++
++#define REG_VMAU_TOP_BASE    0x80028
++
++#define REG_VMAU_CTX         0x8002C
++
++#define REG_VMAU_MD_CFG0     0x80030
++#define VMAU_MD_SLICE_I(a)   (((a) & 0x1)<<0)
++#define VMAU_MD_SLICE_P(a)   (((a) & 0x1)<<1)
++#define VMAU_MD_IS_DECODE(a) (((a) & 0x1)<<4)
++#define VMAU_MD_I4_DIS(a)    (((a) & 0x1)<<8)
++#define VMAU_MD_I16_DIS(a)   (((a) & 0x1)<<9)
++#define VMAU_MD_PSKIP_DIS(a) (((a) & 0x1)<<10)
++#define VMAU_MD_P_L0_DIS(a)  (((a) & 0x1)<<11)
++#define VMAU_MD_I8_DIS(a)    (((a) & 0x1)<<12)
++#define VMAU_MD_PT8_DIS(a)   (((a) & 0x1)<<13)
++#define VMAU_MD_DREF_EN(a)   (((a) & 0x1)<<14)
++#define VMAU_MD_DCT8_EN(a)   (((a) & 0x1)<<15)
++#define VMAU_MD_FRM_REDGE(a) (((a) & 0xFF)<<16)
++#define VMAU_MD_FRM_BEDGE(a) (((a) & 0xFF)<<24)
++
++#define REG_VMAU_MD_CFG1     0x80034
++#define VMAU_IPMY_BIAS_EN(a) (((a) & 0x1)<<0)
++#define VMAU_IPMC_BIAS_EN(a) (((a) & 0x1)<<1)
++#define VMAU_COST_BIAS_EN(a) (((a) & 0x1)<<2)
++#define VMAU_CSSE_BIAS_EN(a) (((a) & 0x1)<<3)
++#define VMAU_JMLAMBDA2_EN(a) (((a) & 0x1)<<4)
++#define VMAU_INTER_NEI_EN(a) (((a) & 0x1)<<5)
++#define VMAU_SKIP_BIAS_EN(a) (((a) & 0x3)<<6)
++#define VMAU_LMD_BIAS_EN(a)  (((a) & 0x1)<<8)
++#define VMAU_INFO_EN(a)      (((a) & 0x1)<<9)
++#define VMAU_DCM_EN(a)       (((a) & 0x1)<<10)
++#define VMAU_MVDS_ALL(a)     (((a) & 0x1)<<12)
++#define VMAU_MVDS_ABS(a)     (((a) & 0x1)<<13)
++#define VMAU_MVS_ALL(a)      (((a) & 0x1)<<14)
++#define VMAU_MVS_ABS(a)      (((a) & 0x1)<<15)
++#define VMAU_P_L0_BIAS(a)    (((a) & 0xF)<<16)
++#define VMAU_PSKIP_BIAS(a)   (((a) & 0xF)<<20)
++#define VMAU_I4_BIAS(a)      (((a) & 0xF)<<24)
++#define VMAU_I16_BIAS(a)     (((a) & 0xF)<<28)
++
++#define REG_VMAU_MD_CFG2     0x80038
++#define VMAU_IPM_BIAS_0(a)   (((a) & 0xF)<<0)
++#define VMAU_IPM_BIAS_1(a)   (((a) & 0xF)<<4)
++#define VMAU_IPM_BIAS_2(a)   (((a) & 0xF)<<8)
++#define VMAU_IPM_BIAS_QP0(a) (((a) & 0x3F)<<12)
++#define VMAU_IPM_BIAS_QP1(a) (((a) & 0x3F)<<18)
++#define VMAU_MD_FBC_EP(a)    (((a) & 0xFF)<<24)
++
++#define REG_VMAU_MD_CFG3     0x8003C
++#define VMAU_CSSE_BIAS_0(a)   (((a) & 0xF)<<0)
++#define VMAU_CSSE_BIAS_1(a)   (((a) & 0xF)<<4)
++#define VMAU_CSSE_BIAS_2(a)   (((a) & 0xF)<<8)
++#define VMAU_CSSE_BIAS_QP0(a) (((a) & 0x3F)<<12)
++#define VMAU_CSSE_BIAS_QP1(a) (((a) & 0x3F)<<18)
++#define VMAU_LMD_BIAS(a)      (((a) & 0xF)<<24)
++#define VMAU_PL0_FS_DIS(a)    (((a) & 0x1)<<28)
++#define VMAU_PT8_FS_DIS(a)    (((a) & 0x1)<<29)
++#define VMAU_PL0_COST_MAX(a)  (((a) & 0x1)<<30)
++#define VMAU_PT8_COST_MAX(a)  (((a) & 0x1)<<31)
++
++#define REG_VMAU_GBL_RUN     0x80040
++#define VMAU_RUN             0x1
++#define VMAU_STOP            0x2
++#define VMAU_RESET           0x4
++
++#define REG_VMAU_GBL_CTR     0x80044
++#define VMAU_CTRL_FIFO_M     0x1
++#define VMAU_CTRL_IRQ_EN     0x10
++#define VMAU_CTRL_SLPOW      0x10000
++#define VMAU_CTRL_TO_DBLK    0x1000000
++#define VMAU_LAMBDA_THRETH(a) (((a) & 0x3)<<25)
++
++#define REG_VMAU_STATUS      0x80048
++
++#define REG_VMAU_CCHN_ADDR   0x8004C
++
++#define REG_VMAU_VIDEO_TYPE  0x80050
++#define VMAU_FMT_H264        0x1
++#define VMAU_FMT_RV9         0x2
++#define VMAU_FMT_VC1         0x3
++#define VMAU_FMT_MPEG2       0x4
++#define VMAU_FMT_MPEG4       0x5
++#define VMAU_FMT_VP8         0x6
++#define VMAU_I4_MSK(a)       (((a) & 0x1)<<3)
++#define VMAU_I16_MSK(a)      (((a) & 0x1)<<4)
++#define VMAU_I8_MSK(a)       (((a) & 0x1)<<5)
++#define VMAU_PT8_MSK(a)      (((a) & 0x1)<<6)
++#define VMAU_MODE_DEC        (0x0<<11)
++#define VMAU_MODE_ENC        (0x1<<11)
++#define VMAU_IS_ISLICE(a)    (((a) & 0x1)<<12)
++#define VMAU_PREDM_MSK(a)    (((a) & 0x1FFFF)<<14)
++#define VMAU_TSE(en)         (((en) & 0x1)<<31)
++
++#define REG_VMAU_Y_GS        0x80054
++#define VMAU_FRM_WID(a)      (((a) & 0x3FFF)<<0)
++#define VMAU_FRM_HEI(a)      (((a) & 0x3FFF)<<16)
++
++#define REG_VMAU_DEC_DONE    0x80058
++
++#define REG_VMAU_ENC_DONE    0x8005C
++
++#define REG_VMAU_POS         0x80060
++
++#define REG_VMAU_MCF_STA     0x80064
++
++#define REG_VMAU_DEC_YADDR   0x80068
++
++#define REG_VMAU_DEC_UADDR   0x8006C
++
++#define REG_VMAU_DEC_VADDR   0x80070
++
++#define REG_VMAU_DEC_STR     0x80074
++
++#define REG_VMAU_DEADZONE    0x80078
++#define VMAU_DEADZONE0_IY(a) (((a) & 0xFF)<<0)
++#define VMAU_DEADZONE1_PY(a) (((a) & 0xFF)<<8)
++#define VMAU_DEADZONE2_IC(a) (((a) & 0xFF)<<16)
++#define VMAU_DEADZONE3_PC(a) (((a) & 0xFF)<<24)
++
++#define REG_VMAU_ACMASK      0x8007C
++
++#define REG_VMAU_MD_CFG4     0x800D8
++#define VMAU_YSSE_THR(a)     (((a) & 0xFFFFFF)<<0)
++#define VMAU_I8_BIAS(a)      (((a) & 0xF)<<24)
++#define VMAU_PT8_BIAS(a)     (((a) & 0xF)<<28)
++
++#define REG_VMAU_MD_CFG5     0x800DC
++#define VMAU_CSSE_THR(a)     (((a) & 0xFFFFFF)<<0)
++#define VMAU_CQP_OFFSET(a)   (((a) & 0x1F)<<24)
++#define VMAU_I4_COST_MAX(a)  (((a) & 0x1)<<29)
++#define VMAU_I8_COST_MAX(a)  (((a) & 0x1)<<30)
++#define VMAU_I16_COST_MAX(a) (((a) & 0x1)<<31)
++
++#define REG_VMAU_MD_CFG6     0x800FC
++#define VMAU_DCM_PARAM(a)    (((a) & 0xFFFFFF)<<0)
++#define VMAU_SDE_PRIOR(a)    (((a) & 0xF)<<24)
++#define VMAU_DB_PRIOR(a)     (((a) & 0xF)<<28)
++
++#define REG_VMAU_MD_CFG7     0x80114
++#define VMAU_CFG_SIZE_X(a)   (((a) & 0xF)<<0)
++#define VMAU_CFG_SIZE_Y(a)   (((a) & 0xF)<<4)
++#define VMAU_CFG_IW_THR(a)   (((a) & 0x1FF)<<8)
++#define VMAU_CFG_BASEQP(a)   (((a) & 0x3F)<<17)
++#define VMAU_CFG_ALPHA(a)    (((a) & 0xFF)<<23)
++#define VMAU_PS_COST_MAX(a)  (((a) & 0x1)<<31)
++
++#define REG_VMAU_MD_CFG8     0x80118
++#define VMAU_CFG_MVR_THR1(a) (((a) & 0x7FFF)<<0)
++#define VMAU_CFG_MVR_THR2(a) (((a) & 0x1FFFF)<<15)
++
++#define REG_VMAU_MD_CFG9     0x8011C
++#define VMAU_CFG_MVR_THR3(a) (((a) & 0xFFFFF)<<0)
++#define VMAU_CFG_BETA(a)     (((a) & 0xFF)<<20)
++
++#define REG_VMAU_MD_CFG10    0x80190
++
++#define REG_VMAU_MD_CFG11    0x80194
++#define VMAU_CFG_MD_RBIAS(a)   (((a) & 0xf) << 21)
++#define VMAU_CFG_MD_RBIAS_EN(a) (((a) & 1) << 25)
++#define VMAU_CFG_MD_PCDC_N0(a) (((a) & 7) << 26)
++#define VMAU_CFG_MD_IFA_VLD(a) (((a) & 1) << 29)
++#define VMAU_CFG_MD_SLV_VLD(a) (((a) & 1) << 30)
++#define VMAU_CFG_MD_SET_VLD(a) (((a) & 1) << 31)
++
++#define REG_VMAU_MD_MODE     0x80198
++
++#define REG_VMAU_DEADZONE1   0x8019C
++
++#define REG_VMAU_IPRED_CFG0   0x801C0
++#define VMAU_IP_MD_VAL(a)     (((a) & 0x1)<<30)
++#define VMAU_IP_REF_NEB_4(a)  (((a) & 0x1)<<29)
++#define VMAU_IP_REF_NEB_8(a)  (((a) & 0x1)<<28)
++#define VMAU_IP_REF_PRD_C(a)  (((a) & 0xF)<<24)
++#define VMAU_IP_REF_PRD_4(a)  (((a) & 0xF)<<20)
++#define VMAU_IP_REF_PRD_8(a)  (((a) & 0xF)<<16)
++#define VMAU_IP_REF_PRD_16(a) (((a) & 0xF)<<12)
++#define VMAU_IP_REF_CUV_EN(a) (((a) & 0x1)<<11)
++#define VMAU_IP_REF_C4_EN(a)  (((a) & 0x1)<<10)
++#define VMAU_IP_REF_C8_EN(a)  (((a) & 0x1)<<9)
++#define VMAU_IP_REF_C16_EN(a) (((a) & 0x1)<<8)
++#define VMAU_IP_REF_LMDUV_EN(a) (((a) & 0x1)<<7)
++#define VMAU_IP_REF_LMD4_EN(a)  (((a) & 0x1)<<6)
++#define VMAU_IP_REF_LMD8_EN(a)  (((a) & 0x1)<<5)
++#define VMAU_IP_REF_LMD16_EN(a) (((a) & 0x1)<<4)
++#define VMAU_IP_REF_BITUV_EN(a) (((a) & 0x1)<<3)
++#define VMAU_IP_REF_BIT4_EN(a)  (((a) & 0x1)<<2)
++#define VMAU_IP_REF_BIT8_EN(a)  (((a) & 0x1)<<1)
++#define VMAU_IP_REF_BIT16_EN(a) (((a) & 0x1)<<0)
++
++#define REG_VMAU_IPRED_CFG1  0x801C4
++#define VMAU_IP_REF_4_BIT0(a)  (((a) & 0xF)<<0)
++#define VMAU_IP_REF_4_BIT1(a)  (((a) & 0xF)<<4)
++#define VMAU_IP_REF_4_BIT2(a)  (((a) & 0xF)<<8)
++#define VMAU_IP_REF_4_BIT3(a)  (((a) & 0xF)<<12)
++#define VMAU_IP_REF_8_BIT0(a)  (((a) & 0xF)<<16)
++#define VMAU_IP_REF_8_BIT1(a)  (((a) & 0xF)<<20)
++#define VMAU_IP_REF_8_BIT2(a)  (((a) & 0xF)<<24)
++#define VMAU_IP_REF_8_BIT3(a)  (((a) & 0xF)<<28)
++
++#define REG_VMAU_IPRED_CFG2  0x801C8
++#define VMAU_IP_REF_16_BIT0(a) (((a) & 0xF)<<0)
++#define VMAU_IP_REF_16_BIT1(a) (((a) & 0xF)<<4)
++#define VMAU_IP_REF_16_BIT2(a) (((a) & 0xF)<<8)
++#define VMAU_IP_REF_16_BIT3(a) (((a) & 0xF)<<12)
++#define VMAU_IP_REF_C_BIT0(a)  (((a) & 0xF)<<16)
++#define VMAU_IP_REF_C_BIT1(a)  (((a) & 0xF)<<20)
++#define VMAU_IP_REF_C_BIT2(a)  (((a) & 0xF)<<24)
++#define VMAU_IP_REF_C_BIT3(a)  (((a) & 0xF)<<28)
++
++#define REG_VMAU_IPRED_CFG3  0x801CC
++#define VMAU_IP_REF_LMD16_IFO(a) (((a) & 0xF)<<0)
++#define VMAU_IP_REF_LMD8_IFO(a)  (((a) & 0xF)<<4)
++#define VMAU_IP_REF_LMD4_IFO(a)  (((a) & 0xF)<<8)
++#define VMAU_IP_REF_LMDUV_IFO(a) (((a) & 0xF)<<12)
++#define VMAU_IP_REF_NEB_8REF(a)  (((a) & 0xF)<<16)
++#define VMAU_IP_REF_NEB_4REF(a)  (((a) & 0xF)<<20)
++
++#define REG_VMAU_IPRED_CFG4  0x801D0
++#define VMAU_IP_REF_C4_IFO(a)  (((a) & 0xFFFF)<<0)
++#define VMAU_IP_REF_C8_IFO(a)  (((a) & 0xFFFF)<<16)
++
++#define REG_VMAU_IPRED_CFG5  0x801D4
++#define VMAU_IP_REF_C16_IFO(a)  (((a) & 0xFFFF)<<0)
++#define VMAU_IP_REF_CUV_IFO(a)  (((a) & 0xFFFF)<<16)
++
++#define REG_VMAU_MEML        0x84000
++
++#define REG_VMAU_QT          0x88000
++
++#define REG_VMAU_CTX_CFBC    0x80174
++
++/********************************************
++  DBLK (deblock)
++*********************************************/
++#define REG_DBLK_DHA         0x70000
++
++#define REG_DBLK_CFG         0x7005C
++#define DBLK_CFG_ALPHA(a)    (((a) & 0x1F)<<0)
++#define DBLK_CFG_BETA(a)     (((a) & 0x1F)<<8)
++#define DBLK_CFG_NO_LFT(a)   (((a) & 0x1)<<17)
++
++#define REG_DBLK_TRIG        0x70060
++#define DBLK_RUN             0x1
++#define DBLK_STOP            0x2
++#define DBLK_RESET           0x4
++#define DBLK_SLICE_RUN       0x8
++
++#define REG_DBLK_CTRL        0x70064
++#define DBLK_CTRL(expand, rotate, loop_filter)           \
++( ((expand) & 0x1)<<4 |                                  \
++  ((rotate) & 0x3)<<1 |                                  \
++  ((loop_filter) & 0x1)<<0                               \
++)
++
++#define REG_DBLK_VTR         0x70068
++#define DBLK_FMT_H264        0x1
++#define DBLK_FMT_RV9         0x2
++#define DBLK_FMT_VC1         0x3
++#define DBLK_FMT_MPEG2       0x4
++#define DBLK_FMT_MPEG4       0x5
++#define DBLK_FMT_VP8         0x6
++#define DBLK_FRM_I           0x0
++#define DBLK_FRM_P           0x1
++#define DBLK_FRM_B           0x2
++#define DBLK_VTR(beta, alpha, vp8_spl, vp8_kf,           \
++                 frm_typ, video_fmt)                     \
++( ((beta) & 0xFF)<<24 |                                  \
++  ((alpha) & 0xFF)<<16 |                                 \
++  ((vp8_spl) & 0x1)<<9 |                                 \
++  ((vp8_kf) & 0x1)<<5 |                                  \
++  ((frm_typ) & 0x3)<<3 |                                 \
++  ((video_fmt) & 0x7)<<0                                 \
++)
++
++#define REG_DBLK_FSTA        0x7006C
++
++#define REG_DBLK_GSTA        0x70070
++#define DBLK_STAT_DOEND  (0x1<<0)
++
++#define REG_DBLK_GSIZE       0x70074
++#define DBLK_GSIZE(mb_height, mb_width)                  \
++( ((mb_height) & 0xFFFF)<<16 |                           \
++  ((mb_width) & 0xFFFF)<<0                               \
++)
++
++#define REG_DBLK_GENDA       0x70078
++
++#define REG_DBLK_GPOS        0x7007C
++#define DBLK_GPOS(first_mby, first_mbx)                  \
++( ((first_mby) & 0xFFFF)<<16 |                           \
++  ((first_mbx) & 0xFFFF)<<0                              \
++)
++
++#define REG_DBLK_GPIC_STR    0x70080
++#define DBLK_GPIC_STR(dst_strd_c, dst_strd_y)            \
++( ((dst_strd_c) & 0xFFFF)<<16 |                          \
++  ((dst_strd_y) & 0xFFFF)<<0                             \
++)
++
++#define REG_DBLK_GPIC_YA     0x70084
++
++#define REG_DBLK_GPIC_CA     0x70088
++
++#define REG_DBLK_GP_ENDA     0x7008C
++
++#define REG_DBLK_SLICE_ENDA  0x70090
++
++#define REG_DBLK_BLK_CTRL    0x70094
++
++#define REG_DBLK_BLK_FIFO    0x70098
++
++#define REG_DBLK_MOS_CFG     0x70240
++#define REG_DBLK_MOS_ADDR    0x70244
++#define DBLK_MOS_BASE_ADDR   VPU_BASE + 0xC7000
++#define REG_DBLK_MOS_CRC     0x70248
++/********************************************
++  SDE (stream parser/encoding)
++*********************************************/
++#define REG_SDE_STAT         0x90000
++#define SDE_STAT_BSEND	     (0x1<<1)
++
++#define REG_SDE_SL_CTRL      0x90004
++#define SDE_SLICE_INIT       (0x1<<1)
++#define SDE_MB_RUN           (0x1<<0)
++
++#define REG_SDE_SL_GEOM      0x90008
++#define SDE_SL_GEOM(mb_height, mb_width,                 \
++                    first_mby, first_mbx)                \
++( ((mb_height) & 0xFF)<<24 |                             \
++  ((mb_width) & 0xFF)<<16 |                              \
++  ((first_mby) & 0xFF)<<8 |                              \
++  ((first_mbx) & 0xFF)<<0                                \
++)
++
++#define REG_SDE_GL_CTRL      0x9000C
++#define SDE_BP(mby, mbx)                                 \
++( ((mby) & 0xFF)<<24 |                                   \
++  ((mbx) & 0xFF)<<16                                     \
++)
++#define SDE_MODE_AUTO        (0x0<<4)
++#define SDE_MODE_STEP        (0x1<<4)
++#define SDE_MODE_DEBUG       (0x2<<4)
++#define SDE_EN               (0x1<<0)
++
++#define REG_SDE_CODEC_ID     0x90010
++#define SDE_FMT_H264_DEC     (0x1<<0)
++#define SDE_FMT_H264_ENC     (0x1<<1)
++#define SDE_FMT_VP8_DEC      (0x1<<2)
++#define SDE_FMT_VC1_DEC      (0x1<<3)
++#define SDE_FMT_MPEG2_DEC    (0x1<<4)
++#define SDE_FMT_VP8_ENC      (0x1<<5)
++
++#define REG_SDE_CFG0         0x90014
++#define REG_SDE_CFG1         0x90018
++#define REG_SDE_CFG2         0x9001C
++#define REG_SDE_CFG3         0x90020
++#define REG_SDE_CFG4         0x90024
++#define REG_SDE_CFG5         0x90028
++#define REG_SDE_CFG6         0x9002C
++#define REG_SDE_CFG7         0x90030
++#define REG_SDE_CFG8         0x90034
++#define REG_SDE_CFG9         0x90038
++#define REG_SDE_CFG10        0x9003C
++#define REG_SDE_CFG11        0x90040
++#define REG_SDE_CFG12        0x90044
++#define REG_SDE_CFG13        0x90048
++#define REG_SDE_CFG14        0x9004C
++#define REG_SDE_CFG15        0x90050
++
++#define REG_SDE_CTX_TBL      0x92000
++#define REG_SDE_CQP_TBL      0x93800
++
++/****************************************************************
++  JPGC (jpeg codec) 
++*****************************************************************/
++#define REG_JPGC_TRIG        0xE0000
++#define REG_JPGC_GLBI        0xE0004
++#define REG_JPGC_STAT        0xE0008
++#define JPGC_STAT_ENDF       (0x1<<31)
++#define REG_JPGC_BSA         0xE000C
++#define REG_JPGC_P0A         0xE0010
++#define REG_JPGC_P1A         0xE0014
++#define REG_JPGC_P2A         0xE0018
++#define REG_JPGC_P3A         0xE001C
++#define REG_JPGC_NMCU        0xE0028
++#define REG_JPGC_NRSM        0xE002C
++#define REG_JPGC_P0C         0xE0030
++#define REG_JPGC_P1C         0xE0034
++#define REG_JPGC_P2C         0xE0038
++#define REG_JPGC_P3C         0xE003C
++#define REG_JPGC_WIDTH       0xE0040
++#define REG_JPGC_MCUS        0xE0064
++#define REG_JPGC_ZIGM0       0xE1000
++#define REG_JPGC_ZIGM1       0xE1100
++#define REG_JPGC_HUFB        0xE1200
++#define REG_JPGC_HUFM        0xE1300
++#define REG_JPGC_QMEM        0xE1400
++#define REG_JPGC_HUFE        0xE1800
++#define REG_JPGC_HUFS        0xE1800
++
++#define JPGC_CORE_OPEN      (0x1<<0)
++#define JPGC_BS_TRIG        (0x1<<1)
++#define JPGC_PP_TRIG        (0x1<<2)
++#define JPGC_TERM           (0x1<<3)
++#define JPGC_RSTER_MD       (0x1<<8)
++
++/****************************************************************
++  ODMA  
++*****************************************************************/
++
++#define REG_ODMA_TRIG 0x60000
++#define REG_ODMA_CTRL 0x60004
++#define REG_ODMA_BDYA 0x60008
++#define REG_ODMA_BDCA 0x6000C
++#define REG_ODMA_BSTR 0x60010
++#define REG_ODMA_HDYA 0x60014
++#define REG_ODMA_HDCA 0x60018
++#define REG_ODMA_SPYA 0x6001C
++#define REG_ODMA_SPCA 0x60020
++
++#define ODMA_REC_STRDY(y)     (((y) & 0xFFFF)<<16)
++#define ODMA_REC_STRDC(c)     (((c) & 0xFFFF)<<0)
++
++/****************************************************************
++  JRFD  
++*****************************************************************/
++
++#define REG_JRFD_TRIG 0x10000
++#define REG_JRFD_CTRL 0x10004
++#define REG_JRFD_HDYA 0x10008
++#define REG_JRFD_HDCA 0x1000C
++#define REG_JRFD_HSTR 0x10010
++#define REG_JRFD_BDYA 0x10014
++#define REG_JRFD_BDCA 0x10018
++#define REG_JRFD_BSTR 0x1001C
++#define REG_JRFD_MHDY 0x10020
++#define REG_JRFD_MHDC 0x10024
++#define REG_JRFD_MBDY 0x10028
++#define REG_JRFD_MBDC 0x1002C
++
++#define JRFD_BODY_STRDY(y)     (((y) & 0xFFFF)<<16)
++#define JRFD_BODY_STRDC(c)     (((c) & 0xFFFF)<<0)
++
++/****************************************************************
++  IFA
++*****************************************************************/
++#define REG_IFA_CTRL            0xB0000
++#define REG_IFA_FRM_SIZE        0xB0004
++#define REG_IFA_RAWY_BA         0xB0008
++#define REG_IFA_RAWC_BA         0xB000C
++#define REG_IFA_RAW_STR         0xB0010
++#define REG_IFA_REFY_BA0        0xB0014
++#define REG_IFA_REFC_BA0        0xB0018
++#define REG_IFA_THRD_Y          0xB001C
++#define REG_IFA_THRD_C          0xB0020
++#define REG_IFA_REFY_BA1        0xB0030
++#define REG_IFA_REFC_BA1        0xB0034
++
++#define IFA_CTRL_INIT           ( 0x1 << 0 )
++#define IFA_CTRL_UV_EN(a)       ( (a&0x1) << 1 )
++#define IFA_CTRL_RRS_SY(a)      ( (a&0x3) << 2 )
++#define IFA_CTRL_RRS_SC(a)      ( (a&0x1) << 4 )
++#define IFA_CTRL_DDR_DW(a)      ( (a&0x1) << 5 )
++#define IFA_CTRL_RRS_EN(a)      ( (a&0x1) << 6 )
++#define IFA_CTRL_DUMP_EN(a)     ( (a&0x1) << 7 )
++#define IFA_CTRL_REF_BIDX(a)    ( (a&0xff) << 8 )
++#define IFA_CTRL_CGE            (0x1<<16) //1 mean close clk-gate, 0 default open
++#define IFA_CTRL_RAW_TYPE(a)    ( (a&0x1) << 17 )
++
++#define IFA_FRM_W(a)      ( (a&0xFFF) << 0 )
++#define IFA_FRM_H(a)      ( (a&0xFFF) << 16 )
++
++#define IFA_STR_Y(a)      ( (a&0xFFFF) << 0 )
++#define IFA_STR_C(a)      ( (a&0xFFFF) << 16 )
++
++#define IFA_THRD_U(a)      ( (a&0x3FFF) << 0 )
++#define IFA_THRD_V(a)      ( (a&0x3FFF) << 16 )
++
++
++/****************************************************************
++  VPU tables
++*****************************************************************/
++
++/********************************************
++  Motion interpolation programable table
++*********************************************/
++#define IS_SKIRT  0
++#define IS_MIRROR 1
++
++#define IS_BIAVG  0
++#define IS_WT1    1
++#define IS_WT2    2
++#define IS_FIXWT  3
++
++#define IS_ILUT0  0
++#define IS_ILUT1  2
++#define IS_EC     1
++
++#define IS_TCS     1
++#define NOT_TCS    0
++#define IS_SCS     1
++#define NOT_SCS    0
++#define IS_HLDGL   1
++#define NOT_HLDGL  0
++#define IS_AVSDGL  1
++#define NOT_AVSDGL 0
++
++#define INTP_HDIR  0
++#define INTP_VDIR  1
++
++enum IntpID {
++  MPEG_HPEL = 0,
++  MPEG_QPEL,
++  H264_QPEL,
++  H264_EPEL,
++  RV8_TPEL,
++  RV9_QPEL,
++  RV9_CPEL,
++  WMV2_QPEL,
++  VC1_QPEL,
++  AVS_QPEL,
++  VP6_QPEL,
++  VP8_QPEL,
++  VP8_EPEL,
++  VP8_BIL,
++  VP8_FPEL, /*full-pixel for chroma*/ 
++  HEVC_QPEL,
++  HEVC_EPEL,
++};
++
++enum PosID {
++  H0V0 = 0,
++  H1V0,
++  H2V0,
++  H3V0,
++  H0V1,
++  H1V1,
++  H2V1,
++  H3V1,
++  H0V2,
++  H1V2,
++  H2V2,
++  H3V2,
++  H0V3,
++  H1V3,
++  H2V3,
++  H3V3,
++};
++
++enum TapTYP {
++  TAP2 = 0,
++  TAP4,
++  TAP6,
++  TAP8,
++};
++
++enum SPelSFT {
++  HPEL = 0,
++  QPEL,
++  EPEL,
++};
++
++typedef struct IntpFMT_t{
++  char tap;
++  char intp_pkg[2];
++  char hldgl;
++  char avsdgl;
++  char intp[2];
++  char intp_dir[2];
++  char intp_coef[2][8];
++  char intp_rnd[2];
++  char intp_sft[2];
++  char intp_sintp[2];
++  char intp_srnd[2];
++  char intp_sbias[2];
++}IntpFMT_t;
++
++//__place_k0_data__
++//static char AryFMT[] = {
++//    IS_SKIRT, IS_MIRROR, IS_SKIRT, IS_SKIRT,
++//    IS_SKIRT, IS_SKIRT, IS_SKIRT, IS_SKIRT, 
++//    IS_SKIRT, IS_SKIRT, IS_SKIRT, IS_SKIRT, 
++//    IS_SKIRT, IS_SKIRT, IS_SKIRT, IS_SKIRT, IS_SKIRT, 
++//};
++// 
++//__place_k0_data__
++//static char SubPel[] = {
++//    HPEL, QPEL, QPEL, EPEL, 
++//    QPEL, QPEL, QPEL, QPEL,
++//    QPEL, QPEL, QPEL, QPEL, 
++//    EPEL, HPEL, QPEL, QPEL, EPEL
++//};
++
++__place_k0_data__
++static IntpFMT_t IntpFMT[][16] = {
++  {
++    /************* MPEG_HPEL ***************/
++    {/*H0V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0}, 
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0}, 
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H2V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0}, 
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0}, 
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H0V1*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0}, 
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V1*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2}, 
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H2V1*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2}, 
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V1*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2}, 
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H0V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0}, 
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2}, 
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H2V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2}, 
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2}, 
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H0V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0}, 
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2}, 
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H2V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2}, 
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0} },
++      {/*intp_rnd*/0, 2}, 
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++  },
++  
++  {
++    /************* MPEG_QPEL ***************/
++    {/*H0V0*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0}, 
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1},{0},},
++      {/*intp_rnd*/15, 0}, 
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1},{0},},
++      {/*intp_rnd*/15, 0}, 
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1},{0},},
++      {/*intp_rnd*/15, 0}, 
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H0V1*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1},{0},},
++      {/*intp_rnd*/15, 0}, 
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15}, 
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/1, 1},
++      {/*intp_srnd*/1, 1},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15}, 
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15}, 
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/1, 1},
++      {/*intp_srnd*/1, 1},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H0V2*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1},{0},},
++      {/*intp_rnd*/15, 0}, 
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15}, 
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15}, 
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15}, 
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H0V3*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1},{0},},
++      {/*intp_rnd*/15, 0}, 
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H1V3*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15}, 
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/1, 1},
++      {/*intp_srnd*/1, 1},
++      {/*intp_sbias*/0, 1},
++    },
++    {/*H2V3*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15}, 
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 1},
++    },
++    {/*H3V3*/
++      TAP8, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 3, -6, 20, 20, -6, 3, -1}, {-1, 3, -6, 20, 20, -6, 3, -1},},
++      {/*intp_rnd*/15, 15}, 
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/1, 1},
++      {/*intp_srnd*/1, 1},
++      {/*intp_sbias*/1, 1},
++    },
++  },
++
++  {
++    /************* H264_QPEL ***************/
++    {/*H0V0*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0}, 
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/16, 0}, 
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/16, 0}, 
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/16, 0}, 
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H0V1*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/16, 0}, 
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP6, {IS_TCS, IS_SCS}, IS_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 16}, 
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 0}, 
++      {/*intp_sft*/5, 10},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/
++      TAP6, {IS_TCS, IS_SCS}, IS_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 16}, 
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H0V2*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/16, 0}, 
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 0}, 
++      {/*intp_sft*/5, 10},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 0}, 
++      {/*intp_sft*/5, 10},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 0}, 
++      {/*intp_sft*/5, 10},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 1},
++    },
++    {/*H0V3*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/16, 0}, 
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H1V3*/
++      TAP6, {IS_TCS, IS_SCS}, IS_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 16}, 
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 1},
++    },
++    {/*H2V3*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 0}, 
++      {/*intp_sft*/5, 10},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 1},
++    },
++    {/*H3V3*/
++      TAP6, {IS_TCS, IS_SCS}, IS_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 16}, 
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/1, 1},
++    },
++  },
++
++  {
++    /************* H264_EPEL ***************/
++    {/*H0V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0}, 
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/0},
++    {/*H2V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/4, 0}, 
++      {/*intp_sft*/3, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V0*/0},
++    {/*H0V1*/0},
++    {/*H1V1*/0},
++    {/*H2V1*/0},
++    {/*H3V1*/0},
++    {/*H0V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/4, 0}, 
++      {/*intp_sft*/3, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V2*/0},
++    {/*H2V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/0, 32}, 
++      {/*intp_sft*/0, 6},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V2*/0},
++    {/*H0V3*/0},
++    {/*H1V3*/0},
++    {/*H2V3*/0},
++    {/*H3V3*/0},
++  },
++
++  {
++    /************* RV8_TPEL ***************/
++    {/*H0V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0}, 
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-1, 12, 6, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0}, 
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-1, 6, 12, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0}, 
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/0},
++    {/*H0V1*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{-1, 12, 6, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0}, 
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 12, 6, -1, 0, 0, 0, 0}, {-1, 12, 6, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/8, 0}, //{0,128}
++      {/*intp_sft*/0, 8},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 6, 12, -1, 0, 0, 0, 0}, {-1, 12, 6, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/8, 0}, //{0,128}
++      {/*intp_sft*/0, 8},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/0},
++    {/*H0V2*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{-1, 6, 12, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0}, 
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 12, 6, -1, 0, 0, 0, 0}, {-1, 6, 12, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/8, 0}, //{0,128}
++      {/*intp_sft*/0, 8},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 6, 12, -1, 0, 0, 0, 0}, {-1, 6, 12, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/8, 0}, //{0,128}
++      {/*intp_sft*/0, 8},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/0},
++    {/*H0V3*/0},
++    {/*H1V3*/0},
++    {/*H2V3*/0},
++    {/*H3V3*/0},
++  },
++
++  {
++    /************* RV9_QPEL ***************/
++    {/*H0V0*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0}, 
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{1, -5, 52, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/16, 0}, 
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{1, -5, 20, 52, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V1*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{1, -5, 52, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -5, 52, 20, -5, 1, 0, 0}, {1, -5, 52, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/32, 32}, 
++      {/*intp_sft*/6, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 52, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 32}, 
++      {/*intp_sft*/5, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -5, 20, 52, -5, 1, 0, 0}, {1, -5, 52, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/32, 32}, 
++      {/*intp_sft*/6, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V2*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/16, 0}, 
++      {/*intp_sft*/5, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -5, 52, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/32, 16}, 
++      {/*intp_sft*/6, 5},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 16}, 
++      {/*intp_sft*/5, 5},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -5, 20, 52, -5, 1, 0, 0}, {1, -5, 20, 20, -5, 1, 0, 0},},
++      {/*intp_rnd*/32, 16}, 
++      {/*intp_sft*/6, 5},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V3*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{1, -5, 20, 52, -5, 1, 0, 0},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V3*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -5, 52, 20, -5, 1, 0, 0}, {1, -5, 20, 52, -5, 1, 0, 0},},
++      {/*intp_rnd*/32, 32}, 
++      {/*intp_sft*/6, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V3*/
++      TAP6, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -5, 20, 20, -5, 1, 0, 0}, {1, -5, 20, 52, -5, 1, 0, 0},},
++      {/*intp_rnd*/16, 32}, 
++      {/*intp_sft*/5, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 2}, 
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++  },
++
++  {
++    /************* RV9_CPEL ***************/
++    {/*H0V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0}, 
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0}, 
++      {/*intp_sft*/2, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0}, 
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0}, 
++      {/*intp_sft*/2, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V1*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/2, 0}, 
++      {/*intp_sft*/2, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0}, {3, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 7}, 
++      {/*intp_sft*/0, 4},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {3, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 4}, 
++      {/*intp_sft*/0, 3},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0}, {3, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 7}, 
++      {/*intp_sft*/0, 4},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 4}, 
++      {/*intp_sft*/0, 3},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 1}, 
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 4}, 
++      {/*intp_sft*/0, 3},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/2, 0}, 
++      {/*intp_sft*/2, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0}, {1, 3, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 7}, 
++      {/*intp_sft*/0, 4},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 3, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 4}, 
++      {/*intp_sft*/0, 3},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V3*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0}, {1, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 1}, 
++      {/*intp_sft*/0, 2},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++  },
++
++  {
++    /************* WMV2_QPEL ***************/
++    {/*H0V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0}, 
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0}, 
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0}, 
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0}, 
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/1, 0},
++      {/*intp_srnd*/1, 0},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H0V1*/0},
++    {/*H1V1*/0},
++    {/*H2V1*/0},
++    {/*H3V1*/0},
++    {/*H0V2*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0}, 
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR}, 
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0}, {-1, 9, 9, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/8, 8}, 
++      {/*intp_sft*/4, 4},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR}, 
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0}, {-1, 9, 9, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/8, 8}, 
++      {/*intp_sft*/4, 4},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR}, 
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0}, {-1, 9, 9, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/8, 8}, 
++      {/*intp_sft*/4, 4},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 1},
++    },
++    {/*H0V3*/0},
++    {/*H1V3*/0},
++    {/*H2V3*/0},
++    {/*H3V3*/0},
++  },
++
++  {
++    /************* VC1_QPEL ***************/
++    {/*H0V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0}, 
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-4, 53, 18, -3, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/8, 0}, 
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-3, 18, 53, -4, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V1*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{-4, 53, 18, -3, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/31, 0}, 
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR}, 
++      {/*intp_coef*/{-4, 53, 18, -3, 0, 0, 0, 0}, {-4, 53, 18, -3, 0, 0, 0, 0},},
++      {/*intp_rnd*/31, 32}, 
++      {/*intp_sft*/6, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR}, 
++      {/*intp_coef*/{-4, 53, 18, -3, 0, 0, 0, 0}, {-1, 9, 9, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/31, 8}, 
++      {/*intp_sft*/6, 4},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR},
++      {/*intp_coef*/{-4, 53, 18, -3, 0, 0, 0, 0}, {-3, 18, 53, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/31, 32},
++      {/*intp_sft*/6, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V2*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/7, 0}, 
++      {/*intp_sft*/4, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR}, 
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0}, {-4, 53, 18, -3, 0, 0, 0, 0},},
++      {/*intp_rnd*/7, 32}, 
++      {/*intp_sft*/4, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR}, 
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0}, {-1, 9, 9, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/7, 8}, 
++      {/*intp_sft*/4, 4},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR}, 
++      {/*intp_coef*/{-1, 9, 9, -1, 0, 0, 0, 0}, {-3, 18, 53, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/7, 32}, 
++      {/*intp_sft*/4, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V3*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{-3, 18, 53, -4, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/31, 0}, 
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V3*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR}, 
++      {/*intp_coef*/{-3, 18, 53, -4, 0, 0, 0, 0}, {-4, 53, 18, -3, 0, 0, 0, 0},},
++      {/*intp_rnd*/31, 32}, 
++      {/*intp_sft*/6, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V3*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR}, 
++      {/*intp_coef*/{-3, 18, 53, -4, 0, 0, 0, 0}, {-1, 9, 9, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/31, 8}, 
++      {/*intp_sft*/6, 4},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V3*/
++      TAP4, {NOT_TCS, IS_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_VDIR, INTP_HDIR}, 
++      {/*intp_coef*/{-3, 18, 53, -4, 0, 0, 0, 0}, {-3, 18, 53, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/31, 32}, 
++      {/*intp_sft*/6, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++  },
++
++  {
++    /************* AVS_QPEL ***************/
++    {/*H0V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0}, 
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-1, -2, 96, 42, -7, 0, 0, 0},{0},},
++      {/*intp_rnd*/64, 0}, 
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-1, 5, 5, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/4, 0}, 
++      {/*intp_sft*/3, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{0, -7, 42, 96, -2, -1, 0, 0},{0},},
++      {/*intp_rnd*/64, 0}, 
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V1*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{-1, -2, 96, 42, -7, 0, 0, 0},{0},},
++      {/*intp_rnd*/64, 0}, 
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, IS_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 5, 5, -1, 0, 0, 0, 0}, {-1, 5, -5, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 32}, 
++      {/*intp_sft*/0, 6},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{0, -1, 5, 5, -1, 0, 0, 0}, {-1, -2, 96, 42, -7, 0, 0, 0},},
++      {/*intp_rnd*/64, 0}, //{0,512} 
++      {/*intp_sft*/0, 10},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, IS_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 5, 5, -1, 0, 0, 0, 0}, {-1, 5, -5, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 32}, 
++      {/*intp_sft*/0, 6},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/1, 0},
++    },
++    {/*H0V2*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{-1, 5, 5, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/4, 0}, 
++      {/*intp_sft*/3, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, -2, 96, 42, -7, 0, 0, 0}, {0, -1, 5, 5, -1, 0, 0, 0},},
++      {/*intp_rnd*/64, 0}, //{0,512} 
++      {/*intp_sft*/0, 10},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 5, 5, -1, 0, 0, 0, 0}, {-1, 5, 5, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 32}, 
++      {/*intp_sft*/0, 6},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{0, -7, 42, 96, -2, -1, 0, 0}, {0, -1, 5, 5, -1, 0, 0, 0},},
++      {/*intp_rnd*/64, 0}, //{0,512} 
++      {/*intp_sft*/0, 10},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V3*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{0, -7, 42, 96, -2, -1, 0, 0}, {0},},
++      {/*intp_rnd*/64, 0}, 
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V3*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, IS_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 5, 5, -1, 0, 0, 0, 0}, {-1, 5, -5, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 32}, 
++      {/*intp_sft*/0, 6},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/0, 1},
++    },
++    {/*H2V3*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{0, -1, 5, 5, -1, 0, 0, 0}, {0, -7, 42, 96, -2, -1, 0, 0},},
++      {/*intp_rnd*/64, 0}, //{0,512} 
++      {/*intp_sft*/0, 10},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V3*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, IS_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 5, 5, -1, 0, 0, 0, 0}, {-1, 5, -5, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/0, 32}, 
++      {/*intp_sft*/0, 6},
++      {/*intp_sintp*/0, 1},
++      {/*intp_srnd*/0, 1},
++      {/*intp_sbias*/1, 1},
++    },
++  },
++
++  {
++    /************* VP6_QPEL ***************/
++    {/*H0V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0}, 
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-4, 109, 24, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/64, 0}, 
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-4, 68, 68, -4, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/64, 0}, 
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-1, 24, 109, -4, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/64, 0}, 
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V1*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{-4, 109, 24, -1, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/64, 0}, 
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-4, 109, 24, -1, 0, 0, 0, 0}, {-4, 109, 24, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-4, 68, 68, -4, 0, 0, 0, 0}, {-4, 109, 24, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 24, 109, -4, 0, 0, 0, 0}, {-4, 109, 24, -1, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V2*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{-4, 68, 68, -4, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/64, 0}, 
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-4, 109, 24, -1, 0, 0, 0, 0}, {-4, 68, 68, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-4, 68, 68, -4, 0, 0, 0, 0}, {-4, 68, 68, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 24, 109, -4, 0, 0, 0, 0}, {-4, 68, 68, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V3*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{-1, 24, 109, -4, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/64, 0}, 
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V3*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-4, 109, 24, -1, 0, 0, 0, 0}, {-1, 24, 109, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V3*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-4, 68, 68, -4, 0, 0, 0, 0}, {-1, 24, 109, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V3*/
++      TAP4, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 24, 109, -4, 0, 0, 0, 0}, {-1, 24, 109, -4, 0, 0, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++  },
++
++  {
++    /************* VP8_QPEL ***************/
++    {/*H0V0*/
++      TAP6, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0}, 
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{2, -11, 108, 36, -8, 1, 0, 0},{0},},
++      {/*intp_rnd*/64, 0}, 
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{3, -16, 77, 77, -16, 3, 0, 0},{0},},
++      {/*intp_rnd*/64, 0}, 
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{1, -8, 36, 108, -11, 2, 0, 0},{0},},
++      {/*intp_rnd*/64, 0}, 
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V1*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{2, -11, 108, 36, -8, 1, 0, 0}, {0},},
++      {/*intp_rnd*/64, 0}, 
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{2, -11, 108, 36, -8, 1, 0, 0}, {2, -11, 108, 36, -8, 1, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{3, -16, 77, 77, -16, 3, 0, 0}, {2, -11, 108, 36, -8, 1, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -8, 36, 108, -11, 2, 0, 0}, {2, -11, 108, 36, -8, 1, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V2*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{3, -16, 77, 77, -16, 3, 0, 0},{0},},
++      {/*intp_rnd*/64, 0}, 
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{2, -11, 108, 36, -8, 1, 0, 0}, {3, -16, 77, 77, -16, 3, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{3, -16, 77, 77, -16, 3, 0, 0}, {3, -16, 77, 77, -16, 3, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -8, 36, 108, -11, 2, 0, 0}, {3, -16, 77, 77, -16, 3, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V3*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{1, -8, 36, 108, -11, 2, 0, 0},{0},},
++      {/*intp_rnd*/64, 0}, 
++      {/*intp_sft*/7, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V3*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{2, -11, 108, 36, -8, 1, 0, 0}, {1, -8, 36, 108, -11, 2, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V3*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{3, -16, 77, 77, -16, 3, 0, 0}, {1, -8, 36, 108, -11, 2, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V3*/
++      TAP6, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, -8, 36, 108, -11, 2, 0, 0}, {1, -8, 36, 108, -11, 2, 0, 0},},
++      {/*intp_rnd*/64, 64}, 
++      {/*intp_sft*/7, 7},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++  },
++
++  {
++    /************* VP8_EPEL ***************/
++    {/*H0V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0}, 
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/0},
++    {/*H2V0*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/4, 0}, 
++      {/*intp_sft*/3, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V0*/0},
++    {/*H0V1*/0},
++    {/*H1V1*/0},
++    {/*H2V1*/0},
++    {/*H3V1*/0},
++    {/*H0V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/4, 0}, 
++      {/*intp_sft*/3, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V2*/0},
++    {/*H2V2*/
++      TAP2, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/4, 4}, 
++      {/*intp_sft*/3, 3},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V2*/0},
++    {/*H0V3*/0},
++    {/*H1V3*/0},
++    {/*H2V3*/0},
++    {/*H3V3*/0},
++  },
++
++  {
++    /************* VP8_BIL ***************/
++    {/*H0V0*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0}, 
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/2, 0}, 
++      {/*intp_sft*/2, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H2V0*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0}, 
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V0*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/2, 0}, 
++      {/*intp_sft*/2, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H0V1*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/2, 0}, 
++      {/*intp_sft*/2, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V1*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0},{3, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/2, 2}, 
++      {/*intp_sft*/2, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H2V1*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{3, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/1, 2}, 
++      {/*intp_sft*/1, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V1*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0},{3, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/2, 2}, 
++      {/*intp_sft*/2, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H0V2*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/1, 0}, 
++      {/*intp_sft*/1, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V2*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0},{1, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/2, 1}, 
++      {/*intp_sft*/2, 1},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H2V2*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{1, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/1, 1}, 
++      {/*intp_sft*/1, 1},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V2*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0},{1, 1, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/2, 1}, 
++      {/*intp_sft*/2, 1},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H0V3*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/2, 0}, 
++      {/*intp_sft*/2, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V3*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{3, 1, 0, 0, 0, 0, 0, 0},{1, 3, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/2, 2}, 
++      {/*intp_sft*/2, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H2V3*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 1, 0, 0, 0, 0, 0, 0},{1, 3, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/1, 2}, 
++      {/*intp_sft*/1, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H3V3*/
++      TAP2, {IS_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{1, 3, 0, 0, 0, 0, 0, 0},{1, 3, 0, 0, 0, 0, 0, 0},},
++      {/*intp_rnd*/2, 2}, 
++      {/*intp_sft*/2, 2},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++  },
++
++  {
++    /************* VP8_FPEL ***************/
++    {/*H0V0*/0},
++    {/*H1V0*/0},
++    {/*H2V0*/0},
++    {/*H3V0*/0},
++    {/*H0V1*/0},
++    {/*H1V1*/0},
++    {/*H2V1*/0},
++    {/*H3V1*/0},
++    {/*H0V2*/0},
++    {/*H1V2*/0},
++    {/*H2V2*/0},
++    {/*H3V2*/0},
++    {/*H0V3*/0},
++    {/*H1V3*/0},
++    {/*H2V3*/0},
++    {/*H3V3*/0},
++  },
++
++  {
++    /************* HEVC_QPEL ***************/
++    {/*H0V0*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0}, 
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-1, 4, -10, 58, 17, -5, 1, 0},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{-1, 4, -11, 40, 40, -11, 4, -1},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, 0}, 
++      {/*intp_coef*/{0, 1, -5, 17, 58, -10, 4, -1},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V1*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{-1, 4, -10, 58, 17, -5, 1, 0},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V1*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 4, -10, 58, 17, -5, 1, 0},{-1, 4, -10, 58, 17, -5, 1, 0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/0, 12},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V1*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 4, -11, 40, 40, -11, 4, -1},{-1, 4, -10, 58, 17, -5, 1, 0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/0, 12},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V1*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{0, 1, -5, 17, 58, -10, 4, -1},{-1, 4, -10, 58, 17, -5, 1, 0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/0, 12},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V2*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{-1, 4, -11, 40, 40, -11, 4, -1},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 4, -10, 58, 17, -5, 1, 0},{-1, 4, -11, 40, 40, -11, 4, -1},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/0, 12},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 4, -11, 40, 40, -11, 4, -1},{-1, 4, -11, 40, 40, -11, 4, -1},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/0, 12},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{0, 1, -5, 17, 58, -10, 4, -1},{-1, 4, -11, 40, 40, -11, 4, -1},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/0, 12},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V3*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_VDIR, 0}, 
++      {/*intp_coef*/{0, 1, -5, 17, 58, -10, 4, -1},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V3*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 4, -10, 58, 17, -5, 1, 0},{0, 1, -5, 17, 58, -10, 4, -1},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/0, 12},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V3*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-1, 4, -11, 40, 40, -11, 4, -1},{0, 1, -5, 17, 58, -10, 4, -1},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/0, 12},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V3*/
++      TAP8, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 1}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{0, 1, -5, 17, 58, -10, 4, -1},{0, 1, -5, 17, 58, -10, 4, -1},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/0, 12},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++  },
++
++  {
++    /************* HEVC_EPEL ***************/
++    {/*H0V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0}, 
++      {/*intp_coef*/{1, 0, 0, 0, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0},
++      {/*intp_srnd*/0},
++      {/*intp_sbias*/0},
++    },
++    {/*H1V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-2, 58, 10, -2, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 12},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-4, 54, 16, -2, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 12},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-6, 46, 28, -4, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 12},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H4V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-4, 36, 36, -4, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 12},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H5V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-4, 28, 46, -6, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 12},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H6V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-2, 16, 54, -4, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 12},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H7V0*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/1, 0}, {INTP_HDIR, INTP_VDIR}, 
++      {/*intp_coef*/{-2, 10, 58, -2, 0, 0, 0, 0},{0},},
++      {/*intp_rnd*/32, 0}, 
++      {/*intp_sft*/6, 12},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V2*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0, 0}, 
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V2*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0, 0}, 
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V2*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0, 0}, 
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V2*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0, 0}, 
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H0V3*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0, 0}, 
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H1V3*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0, 0}, 
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H2V3*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0, 0}, 
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++    {/*H3V3*/
++      TAP4, {NOT_TCS, NOT_SCS}, NOT_HLDGL, NOT_AVSDGL,
++      {/*intp*/0, 0}, {0, 0}, 
++      {/*intp_coef*/{0},{0},},
++      {/*intp_rnd*/0, 0}, 
++      {/*intp_sft*/0, 0},
++      {/*intp_sintp*/0, 0},
++      {/*intp_srnd*/0, 0},
++      {/*intp_sbias*/0, 0},
++    },
++  },
++
++};
++
++#endif /*__HELIX_H__*/
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_jpeg_dec.c b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_jpeg_dec.c
+new file mode 100644
+index 000000000..66b093f2a
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_jpeg_dec.c
+@@ -0,0 +1,51 @@
++#include "helix_jpeg_dec.h"
++
++void JPEGD_SliceInit(_JPEGD_SliceInfo *s)
++{
++  unsigned int i;
++  volatile unsigned int *chn = (volatile unsigned int *)s->des_va;
++
++  GEN_VDMA_ACFG(chn, TCSM_FLUSH, 0, 0x0);
++
++  /* Open clock configuration */
++  GEN_VDMA_ACFG(chn, REG_JPGC_GLBI, 0, OPEN_CLOCK);
++
++  /**************************************************
++   Huffman Encode Table configuration
++  *************************************************/
++  for(i=0; i<HUFFMIN_LEN; i++)
++    GEN_VDMA_ACFG(chn, REG_JPGC_HUFM+i*4, 0,*(s->huffmin++) );
++  for(i=0; i<HUFFBASE_LEN; i++)
++    GEN_VDMA_ACFG(chn, REG_JPGC_HUFB+i*4, 0,*(s->huffbase++));
++  for(i=0; i<HUFFSYMB_LEN; i++)
++    GEN_VDMA_ACFG(chn, REG_JPGC_HUFS+i*4, 0,*(s->huffsymb++));
++  /**************************************************
++   Quantization Table configuration
++  *************************************************/
++  for(i=0; i<QMEM_LEN; i++)
++    GEN_VDMA_ACFG(chn, REG_JPGC_QMEM+i*4, 0,*(s->qmem++));
++
++  /**************************************************
++   REGs configuration
++  *************************************************/
++  GEN_VDMA_ACFG(chn, REG_JPGC_STAT, 0, 0);
++  GEN_VDMA_ACFG(chn, REG_JPGC_BSA, 0,(uint32_t)s->bsa);
++  GEN_VDMA_ACFG(chn,REG_JPGC_P0A,0, (uint32_t)s->p0a);
++  GEN_VDMA_ACFG(chn,REG_JPGC_P1A, 0,(uint32_t)s->p1a );
++  GEN_VDMA_ACFG(chn,REG_JPGC_NMCU,0, s->nmcu);
++  GEN_VDMA_ACFG(chn,REG_JPGC_NRSM,0, s->nrsm);
++  GEN_VDMA_ACFG(chn,REG_JPGC_WIDTH,0, s->width);
++  GEN_VDMA_ACFG(chn,REG_JPGC_P0C,0, s->pxc[0]);/* component 0 configure information NBLK<<4| QT<<2| HA<<1| HD */
++  GEN_VDMA_ACFG(chn,REG_JPGC_P1C,0, s->pxc[1]);
++  GEN_VDMA_ACFG(chn,REG_JPGC_P2C,0, s->pxc[2]);
++  GEN_VDMA_ACFG(chn,REG_JPGC_P3C,0, s->pxc[3]);
++
++  GEN_VDMA_ACFG(chn,REG_JPGC_GLBI,0, (YUV420PVH /*P0V|P0H*/|
++			JPGC_NCOL /*NCOL*/ |
++			JPGC_DEC/*DE*/ |
++			JPGC_EN  /*ENABLE*/) );
++
++  GEN_VDMA_ACFG(chn,REG_JPGC_TRIG,VDMA_ACFG_TERM,JPGC_BS_TRIG|JPGC_PP_TRIG | JPGC_CORE_OPEN);
++
++
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_jpeg_dec.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_jpeg_dec.h
+new file mode 100644
+index 000000000..bdaa6dbc1
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_jpeg_dec.h
+@@ -0,0 +1,72 @@
++/****************************************************************
++*****************************************************************/
++
++#ifndef __JZM_JPEG_DEC_H__
++#define __JZM_JPEG_DEC_H__
++#include "helix.h"
++
++#ifdef __KERNEL__
++#include <linux/types.h>
++#include <linux/printk.h>
++#include <asm-generic/div64.h>
++#define printf printk
++#endif
++
++
++#define JPGC_EN        (0x1)        /* JPGC enable signal */
++
++#define YUV420P0C      (0x30)       /* component 0 configure information NBLK<<4| QT<<2| HA<<1| HD */
++#define YUV420P1C      (0x03)       /* component 1 configure information NBLK<<4| QT<<2| HA<<1| HD */
++#define YUV420P2C      (0x03)       /* component 2 configure information NBLK<<4| QT<<2| HA<<1| HD */
++#define YUV420P3C      (0xf0)       /* component 3 configure information NBLK<<4| QT<<2| HA<<1| HD */
++
++#define YUV420PVH      (0x0a<<16)   /* component vertical/horizontal size of MCU:P3H P3V P2H P2V P1H P1V P0H P0V */
++#define JPGC_RSM       (0x1<<2)     /* JPGC rstart marker enable signal */
++#define JPGC_SPEC      (0x0<<1)     /* YUV420 mode */
++#define JPGC_UNIV      (0x1<<1)     /* YUV444 or YUV422 mode */
++#define JPGC_DEC       (0x1<<3)     /* JPGC decode signal: 1 (decode); 0(encode) */
++#define OPEN_CLOCK     (0x1)        /* open the core clock */
++#define JPGC_NCOL      (0x2<<4)     /* color numbers of a MCU minus 1,it always 2 for YUV color space */
++#define STAT_CLEAN     (0x0)        /* clean the STAT register */
++#define CORE_RST       (0x1<<6)     /* JPGC core reset ,high active */
++#define JPGC_EFE       (0x1<<8)     /* JPGC EFE source */
++#define VRAM_RAWY_BA   (VPU_BASE | 0xF0000)
++#define VRAM_RAWC_BA   (VRAM_RAWY_BA + 256)
++
++#if 0
++/* JPEG Decode quantization table select level */
++typedef enum {
++  LOW_QUALITY,
++  MEDIUMS_QUALITY,
++  HIGH_QUALITY
++} QUANT_QUALITY;
++#endif
++
++#define HUFFMIN_LEN	16
++#define HUFFBASE_LEN	64
++#define HUFFSYMB_LEN	336
++#define QMEM_LEN	256
++
++/*
++  _JPEGD_SliceInfo:
++  JPEG Decoder Slice Level Information
++ */
++typedef struct{
++    uint32_t *des_va, des_pa;
++    uint32_t bsa;                       /* bitstream buffer address  */
++    uint32_t p0a, p1a;                  /* componet 0-3 plane buffer address */
++    uint8_t nrsm;                       /* Re-Sync-Marker gap number */
++    uint32_t nmcu;                      /* number of MCU minus one */
++    uint32_t width;                     /* yuv nv12 frame width, bit15: 1,NV12, 0,TILE .(1 << 15) | (mb_width - 1)*/
++    int *huffmin  ;
++    int *huffbase ;
++    int *huffsymb ;
++    int *qmem  ;
++    uint32_t pxc[4];			/* component 0~3 config info */
++
++}_JPEGD_SliceInfo;
++
++
++
++void JPEGD_SliceInit(_JPEGD_SliceInfo *s);
++#endif// __JZM_JPEG_ENC_H__
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_jpeg_enc.c b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_jpeg_enc.c
+new file mode 100644
+index 000000000..59550079a
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_jpeg_enc.c
+@@ -0,0 +1,241 @@
++#include "helix_jpeg_enc.h"
++
++__place_k0_data__
++uint32_t huffenc[HUFNUM][HUFFENC_LEN] = {
++  {0x100,  0x101,  0x204,  0x30b,  0x41a,  0x678,  0x7f8,  0x9f6,
++   0xf82,  0xf83,  0x30c,  0x41b,  0x679,  0x8f6,  0xaf6,  0xf84,
++   0xf85,  0xf86,  0xf87,  0xf88,  0x41c,  0x7f9,  0x9f7,  0xbf4,
++   0xf89,  0xf8a,  0xf8b,  0xf8c,  0xf8d,  0xf8e,  0x53a,  0x8f7,
++   0xbf5,  0xf8f,  0xf90,  0xf91,  0xf92,  0xf93,  0xf94,  0xf95,
++   0x53b,  0x9f8,  0xf96,  0xf97,  0xf98,  0xf99,  0xf9a,  0xf9b,
++   0xf9c,  0xf9d,  0x67a,  0xaf7,  0xf9e,  0xf9f,  0xfa0,  0xfa1,
++   0xfa2,  0xfa3,  0xfa4,  0xfa5,  0x67b,  0xbf6,  0xfa6,  0xfa7,
++   0xfa8,  0xfa9,  0xfaa,  0xfab,  0xfac,  0xfad,  0x7fa,  0xbf7,
++   0xfae,  0xfaf,  0xfb0,  0xfb1,  0xfb2,  0xfb3,  0xfb4,  0xfb5,
++   0x8f8,  0xec0,  0xfb6,  0xfb7,  0xfb8,  0xfb9,  0xfba,  0xfbb,
++   0xfbc,  0xfbd,  0x8f9,  0xfbe,  0xfbf,  0xfc0,  0xfc1,  0xfc2,
++   0xfc3,  0xfc4,  0xfc5,  0xfc6,  0x8fa,  0xfc7,  0xfc8,  0xfc9,
++   0xfca,  0xfcb,  0xfcc,  0xfcd,  0xfce,  0xfcf,  0x9f9,  0xfd0,
++   0xfd1,  0xfd2,  0xfd3,  0xfd4,  0xfd5,  0xfd6,  0xfd7,  0xfd8,
++   0x9fa,  0xfd9,  0xfda,  0xfdb,  0xfdc,  0xfdd,  0xfde,  0xfdf,
++   0xfe0,  0xfe1,  0xaf8,  0xfe2,  0xfe3,  0xfe4,  0xfe5,  0xfe6,
++   0xfe7,  0xfe8,  0xfe9,  0xfea,  0xfeb,  0xfec,  0xfed,  0xfee,
++   0xfef,  0xff0,  0xff1,  0xff2,  0xff3,  0xff4,  0xff5,  0xff6,
++   0xff7,  0xff8,  0xff9,  0xffa,  0xffb,  0xffc,  0xffd,  0xffe,
++   0x30a,  0xaf9,  0xfff,  0xfff,  0xfff,  0xfff,  0xfff,  0xfff,
++   0xfd0,  0xfd1,  0xfd2,  0xfd3,  0xfd4,  0xfd5,  0xfd6,  0xfd7,
++   0x101,  0x204,  0x30a,  0x418,  0x419,  0x538,  0x678,  0x8f4,
++   0x9f6,  0xbf4,  0x30b,  0x539,  0x7f6,  0x8f5,  0xaf6,  0xbf5,
++   0xf88,  0xf89,  0xf8a,  0xf8b,  0x41a,  0x7f7,  0x9f7,  0xbf6,
++   0xec2,  0xf8c,  0xf8d,  0xf8e,  0xf8f,  0xf90,  0x41b,  0x7f8,
++   0x9f8,  0xbf7,  0xf91,  0xf92,  0xf93,  0xf94,  0xf95,  0xf96,
++   0x53a,  0x8f6,  0xf97,  0xf98,  0xf99,  0xf9a,  0xf9b,  0xf9c,
++   0xf9d,  0xf9e,  0x53b,  0x9f9,  0xf9f,  0xfa0,  0xfa1,  0xfa2,
++   0xfa3,  0xfa4,  0xfa5,  0xfa6,  0x679,  0xaf7,  0xfa7,  0xfa8,
++   0xfa9,  0xfaa,  0xfab,  0xfac,  0xfad,  0xfae,  0x67a,  0xaf8,
++   0xfaf,  0xfb0,  0xfb1,  0xfb2,  0xfb3,  0xfb4,  0xfb5,  0xfb6,
++   0x7f9,  0xfb7,  0xfb8,  0xfb9,  0xfba,  0xfbb,  0xfbc,  0xfbd,
++   0xfbe,  0xfbf,  0x8f7,  0xfc0,  0xfc1,  0xfc2,  0xfc3,  0xfc4,
++   0xfc5,  0xfc6,  0xfc7,  0xfc8,  0x8f8,  0xfc9,  0xfca,  0xfcb,
++   0xfcc,  0xfcd,  0xfce,  0xfcf,  0xfd0,  0xfd1,  0x8f9,  0xfd2,
++   0xfd3,  0xfd4,  0xfd5,  0xfd6,  0xfd7,  0xfd8,  0xfd9,  0xfda,
++   0x8fa,  0xfdb,  0xfdc,  0xfdd,  0xfde,  0xfdf,  0xfe0,  0xfe1,
++   0xfe2,  0xfe3,  0xaf9,  0xfe4,  0xfe5,  0xfe6,  0xfe7,  0xfe8,
++   0xfe9,  0xfea,  0xfeb,  0xfec,  0xde0,  0xfed,  0xfee,  0xfef,
++   0xff0,  0xff1,  0xff2,  0xff3,  0xff4,  0xff5,  0xec3,  0xff6,
++   0xff7,  0xff8,  0xff9,  0xffa,  0xffb,  0xffc,  0xffd,  0xffe,
++   0x100,  0x9fa,  0xfff,  0xfff,  0xfff,  0xfff,  0xfff,  0xfff,
++   0xfd0,  0xfd1,  0xfd2,  0xfd3,  0xfd4,  0xfd5,  0xfd6,  0xfd7,
++   0x100,  0x202,  0x203,  0x204,  0x205,  0x206,  0x30e,  0x41e,
++   0x53e,  0x67e,  0x7fe,  0x8fe,  0xfff,  0xfff,  0xfff,  0xfff,
++   0x100,  0x101,  0x102,  0x206,  0x30e,  0x41e,  0x53e,  0x67e,
++   0x7fe,  0x8fe,  0x9fe,  0xafe,  0xfff,  0xfff,  0xfff,  0xfff}
++};
++
++__place_k0_data__
++uint32_t qmem[QTNUM][QMEM_LEN] = {
++  //normal quantization table
++  {0x0100, 0x0155, 0x0155, 0x0a49, 0x0155, 0x0b33, 0x0100, 0x0a49,
++   0x0a49, 0x0a49, 0x09c7, 0x09c7, 0x0100, 0x00cd, 0x0955, 0x08cd,
++   0x093b, 0x0955, 0x12e9, 0x12e9, 0x0955, 0x251f, 0x11c7, 0x11af,
++   0x0911, 0x08cd, 0x1a35, 0x113b, 0x2421, 0x1111, 0x1a35, 0x113b,
++   0x1a49, 0x1a49, 0x0880, 0x19c7, 0x10b2, 0x10d2, 0x0880, 0x10f1,
++   0x10ba, 0x10ea, 0x1a49, 0x1a49, 0x10cd, 0x1095, 0x231f, 0x10ba,
++   0x1955, 0x229d, 0x193b, 0x193b, 0x193b, 0x2421, 0x10d2, 0x223f,
++   0x2219, 0x2249, 0x10a4, 0x1911, 0x10b2, 0x2d05, 0x193b, 0x10a4,
++   0x09c7, 0x09c7, 0x09c7, 0x0955, 0x12e9, 0x0955, 0x1155, 0x093b,
++   0x093b, 0x1155, 0x10a4, 0x23e1, 0x1a49, 0x23e1, 0x10a4, 0x10a4,
++   0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4,
++   0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4,
++   0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4,
++   0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4,
++   0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4,
++   0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4, 0x10a4,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
++  //finer quantization table
++  {0x0155, 0x0200, 0x0200, 0x0b33, 0x0200, 0x0200, 0x0155, 0x0b33,
++   0x0b33, 0x0b33, 0x0155, 0x0155, 0x0155, 0x0155, 0x0100, 0x093b,
++   0x09c7, 0x0100, 0x0a49, 0x0a49, 0x0100, 0x0911, 0x12e9, 0x0955,
++   0x09c7, 0x093b, 0x11c7, 0x0080, 0x11af, 0x11af, 0x11c7, 0x0080,
++   0x11c7, 0x08f1, 0x08cd, 0x08ba, 0x1a49, 0x1155, 0x08cd, 0x08c3,
++   0x1a5f, 0x08c3, 0x08f1, 0x11c7, 0x251f, 0x23e1, 0x251f, 0x1a5f,
++   0x1a35, 0x1111, 0x0880, 0x0880, 0x0880, 0x11af, 0x1155, 0x10ea,
++   0x19bb, 0x10f1, 0x2421, 0x19bb, 0x1a49, 0x2421, 0x0880, 0x1111,
++   0x0155, 0x0155, 0x0155, 0x0100, 0x0a49, 0x0100, 0x0911, 0x09c7,
++   0x09c7, 0x0911, 0x1111, 0x08c3, 0x11c7, 0x08c3, 0x1111, 0x1111,
++   0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111,
++   0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111,
++   0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111,
++   0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111,
++   0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111,
++   0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111, 0x1111,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
++  //finest quantization table
++  {0x02ab, 0x0400, 0x0400, 0x0400, 0x0400, 0x0400, 0x02ab, 0x0400,
++   0x0400, 0x0400, 0x02ab, 0x02ab, 0x02ab, 0x02ab, 0x02ab, 0x0b33,
++   0x0200, 0x02ab, 0x02ab, 0x02ab, 0x02ab, 0x0155, 0x0200, 0x0b33,
++   0x0200, 0x0b33, 0x0a49, 0x0155, 0x0a49, 0x0a49, 0x0a49, 0x0155,
++   0x0a49, 0x0155, 0x0a49, 0x0100, 0x00cd, 0x09c7, 0x0a49, 0x0100,
++   0x00cd, 0x0100, 0x0155, 0x0a49, 0x09c7, 0x0955, 0x09c7, 0x00cd,
++   0x00cd, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x0a49, 0x09c7, 0x0955,
++   0x093b, 0x0955, 0x12e9, 0x093b, 0x00cd, 0x12e9, 0x12e9, 0x12e9,
++   0x02ab, 0x02ab, 0x02ab, 0x02ab, 0x02ab, 0x02ab, 0x0155, 0x0200,
++   0x0200, 0x0155, 0x12e9, 0x0100, 0x0a49, 0x0100, 0x12e9, 0x12e9,
++   0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9,
++   0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9,
++   0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9,
++   0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9,
++   0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9,
++   0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9, 0x12e9,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
++   0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
++};
++
++
++void JPEGE_SliceInit(_JPEGE_SliceInfo *s)
++{
++  unsigned int i;
++  volatile unsigned int *chn = (volatile unsigned int *)s->des_va;
++
++  GEN_VDMA_ACFG(chn, TCSM_FLUSH, 0, 0x0);
++
++  /* Open clock configuration */
++  GEN_VDMA_ACFG(chn, REG_JPGC_GLBI, 0, OPEN_CLOCK);
++
++  /**************************************************
++   Huffman Encode Table configuration
++  *************************************************/
++  for(i=0; i<HUFFENC_LEN; i++)
++    GEN_VDMA_ACFG(chn, REG_JPGC_HUFE+i*4, 0, huffenc[s->huffenc_sel][i]);
++
++  /**************************************************
++   Quantization Table configuration
++  *************************************************/
++  for(i=0; i<QMEM_LEN; i++)
++    GEN_VDMA_ACFG(chn, REG_JPGC_QMEM+i*4, 0, qmem[s->ql_sel][i]);
++
++  /**************************************************
++   REGs configuration
++  *************************************************/
++  GEN_VDMA_ACFG(chn, REG_JPGC_STAT, 0, STAT_CLEAN);
++  GEN_VDMA_ACFG(chn, REG_JPGC_BSA, 0, s->bsa);
++
++  if(s->raw_format) { /* NV12 or NV21 */
++    GEN_VDMA_ACFG(chn, REG_JPGC_P0A, 0, VRAM_RAWY_BA);
++  } else {/* TILE */
++    GEN_VDMA_ACFG(chn, REG_JPGC_P0A, 0, s->p0a);
++    GEN_VDMA_ACFG(chn, REG_JPGC_P1A, 0, s->p1a);
++  }
++
++  GEN_VDMA_ACFG(chn, REG_JPGC_NMCU, 0, s->nmcu);
++  GEN_VDMA_ACFG(chn, REG_JPGC_NRSM, 0, s->nrsm);
++
++  GEN_VDMA_ACFG(chn, REG_JPGC_P0C, 0, YUV420P0C);
++  GEN_VDMA_ACFG(chn, REG_JPGC_P1C, 0, YUV420P1C);
++  GEN_VDMA_ACFG(chn, REG_JPGC_P2C, 0, YUV420P2C);
++
++  if(s->raw_format) {
++    GEN_VDMA_ACFG(chn, REG_JPGC_GLBI, 0, (YUV420PVH                 |
++					  JPGC_NCOL                 |
++					  JPGC_SPEC     /* MODE */  |
++					  JPGC_EFE                  |
++					  JPGC_EN));
++
++    GEN_VDMA_ACFG(chn, REG_JPGC_TRIG, 0, JPGC_BS_TRIG | JPGC_PP_TRIG | JPGC_CORE_OPEN);
++
++  }else{
++    GEN_VDMA_ACFG(chn, REG_JPGC_GLBI, 0, (YUV420PVH                 |
++					  JPGC_NCOL                 |
++					  JPGC_SPEC     /* MODE */  |
++					  JPGC_EN));
++
++    GEN_VDMA_ACFG(chn, REG_JPGC_TRIG, VDMA_ACFG_TERM, JPGC_BS_TRIG | JPGC_PP_TRIG | JPGC_CORE_OPEN);
++  }
++
++
++  /**************************************************
++   EFE configuration
++  *************************************************/
++  if(s->raw_format) {
++    GEN_VDMA_ACFG(chn, REG_EFE_GEOM, 0, (EFE_JPGC_LST_MBY(s->mb_height-1) |
++					 EFE_JPGC_LST_MBX(s->mb_width-1) ) );
++
++    GEN_VDMA_ACFG(chn, REG_EFE_RAWY_SBA, 0, s->raw[0]);
++    GEN_VDMA_ACFG(chn, REG_EFE_RAWU_SBA, 0, s->raw[1]);
++    GEN_VDMA_ACFG(chn, REG_EFE_RAWV_SBA, 0, s->raw[2]);
++    GEN_VDMA_ACFG(chn, REG_EFE_RAW_STRD, 0, (EFE_RAW_STRDY(s->stride[0]) |
++					     EFE_RAW_STRDC(s->stride[1]) ) );
++
++    GEN_VDMA_ACFG(chn, REG_EFE_RAW_DBA, 0, VRAM_RAWY_BA);
++    GEN_VDMA_ACFG(chn, REG_EFE_CTRL, VDMA_ACFG_TERM, (EFE_PLANE_NV12 |
++						      EFE_ID_JPEG    |
++						      EFE_EN         |
++						      (s->raw_format)|
++						      EFE_RUN) );
++  }
++
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_jpeg_enc.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_jpeg_enc.h
+new file mode 100644
+index 000000000..48fbbbc11
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_jpeg_enc.h
+@@ -0,0 +1,81 @@
++/****************************************************************
++*****************************************************************/
++
++#ifndef __JZM_JPEG_ENC_H__
++#define __JZM_JPEG_ENC_H__
++#include "helix.h"
++
++#ifdef __KERNEL__
++#include <linux/types.h>
++#include <linux/printk.h>
++#include <asm-generic/div64.h>
++#define printf printk
++#endif
++
++#define HUFFENC_LEN    (384)        /* Huffman encoder  table lenth */
++#define QMEM_LEN       (256)        /* Quantization table lenth */
++#define HUFNUM         (1)          /* Huffman encode table number */
++#define QTNUM          (3)          /* Quantization table number */
++#define YUV420P0C      (0x30)       /* component 0 configure information NBLK<<4| QT<<2| HA<<1| HD */
++#define YUV420P1C      (0x07)       /* component 1 configure information NBLK<<4| QT<<2| HA<<1| HD */
++#define YUV420P2C      (0x07)       /* component 2 configure information NBLK<<4| QT<<2| HA<<1| HD */
++#define YUV420PVH      (0x0a<<16)   /* component vertical/horizontal size of MCU:P3H P3V P2H P2V P1H P1V P0H P0V */
++#define JPGC_RSM       (0x1<<2)     /* JPGC rstart marker enable signal */
++#define JPGC_SPEC      (0x0<<1)     /* YUV420 mode */
++#define JPGC_UNIV      (0x1<<1)     /* YUV444 or YUV422 mode */
++#define JPGC_EN        (0x1)        /* JPGC enable signal */
++#define OPEN_CLOCK     (0x1)        /* open the core clock */
++#define JPGC_NCOL      (0x2<<4)     /* color numbers of a MCU minus 1,it always 2 for YUV color space */
++#define STAT_CLEAN     (0x0)        /* clean the STAT register */
++#define CORE_RST       (0x1<<6)     /* JPGC core reset ,high active */
++#define JPGC_EFE       (0x1<<8)     /* JPGC EFE source */
++#define VRAM_RAWY_BA   (VPU_BASE | 0xF0000)
++#define VRAM_RAWC_BA   (VRAM_RAWY_BA + 256)
++
++#if 0
++/* JPEG encode quantization table select level */
++typedef enum {
++  LOW_QUALITY,
++  MEDIUMS_QUALITY,
++  HIGH_QUALITY
++} QUANT_QUALITY;
++#endif
++
++/*
++  _JPEGE_SliceInfo:
++  JPEG Encoder Slice Level Information
++ */
++
++typedef struct _JPEGE_SliceInfo {
++  uint32_t *des_va, des_pa;
++  uint8_t ncol;                   /* number of color/components of a MCU minus one */
++  uint8_t rsm;                    /* Re-sync-marker enable */
++  uint32_t bsa;                   /* bitstream buffer address  */
++  uint32_t p0a, p1a;              /* componet 0-3 plane buffer address */
++  uint8_t nrsm;                   /* Re-Sync-Marker gap number */
++  uint32_t nmcu;                  /* number of MCU minus one */
++  uint32_t raw[3];                /*{rawy, rawu, rawv} or {rawy, rawc, N/C}*/
++  uint32_t stride[2];             /*{stride_y, stride_c}, only used in raster raw*/
++  uint32_t mb_height;
++  uint32_t mb_width;
++  uint8_t raw_format;
++
++  /* Quantization level select,0-2 level */
++  int ql_sel;
++  uint8_t huffenc_sel;           /* Huffman ENC Table select */
++}_JPEGE_SliceInfo;
++
++
++__place_k0_data__
++extern uint32_t huffenc[HUFNUM][HUFFENC_LEN];
++
++__place_k0_data__
++extern uint32_t qmem[QTNUM][QMEM_LEN];
++
++/*
++  JPEGE_SliceInit(_JPEGE_SliceInfo *s)
++  @param s: slice information structure
++ */
++
++void JPEGE_SliceInit(_JPEGE_SliceInfo *s);
++#endif// __JZM_JPEG_ENC_H__
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_x264_enc.c b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_x264_enc.c
+new file mode 100644
+index 000000000..a98315e35
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_x264_enc.c
+@@ -0,0 +1,1647 @@
++#include "helix_x264_enc.h"
++#define MB_WID ((s->frame_width + 15) / 16)
++#define MB_HEI ((s->frame_height + 15) / 16)
++__place_k0_data__
++static uint32_t lps_range[64] = {
++  0xeeceaefc,  0xe1c3a5fc,  0xd6b99cfc,  0xcbb094f2,
++  0xc1a78ce4,  0xb79e85da,  0xad967ece,  0xa48e78c4,
++  0x9c8772ba,  0x94806cb0,  0x8c7966a6,  0x8573619e,
++  0x7e6d5c96,  0x7867578e,  0x72625386,  0x6c5d4e80,
++  0x66584a78,  0x61544672,  0x5c4f436c,  0x574b3f66,
++  0x53473c62,  0x4e43395c,  0x4a403658,  0x463d3352,
++  0x4339304e,  0x3f362e4a,  0x3c342b46,  0x39312942,
++  0x362e273e,  0x332c253c,  0x30292338,  0x2e272136,
++  0x2b251f32,  0x29231d30,  0x27211c2c,  0x251f1a2a,
++  0x231e1928,  0x211c1826,  0x1f1b1624,  0x1d191522,
++  0x1c181420,  0x1a17131e,  0x1915121c,  0x1714111a,
++  0x16131018,  0x15120f18,  0x14110e16,  0x13100d14,
++  0x120f0c14,  0x110e0c12,  0x100d0b12,  0x0f0d0a10,
++  0x0e0c0a10,  0x0d0b090e,  0x0c0a090e,  0x0c0a080c,
++  0x0b09070c,  0x0a09070a,  0x0a08070a,  0x0908060a,
++  0x09070608,  0x08070508,  0x07060508,  0x00000000,
++};
++
++
++
++#define C_SPE_ADD_MB_NUM 3
++void BUF_SHARE_CFG(_H264E_SliceInfo *s, uint32_t *buf_addr_group, uint8_t *buf_ref_mby_size, uint8_t *buf_odma_spe_flag, uint8_t *buf_odma_alg_flag)
++{
++  int beyond_size = (s->buf_share_size + 1) * 64;
++
++  int c_pxl_space = (s->mb_width*16)*(s->mb_height*8);
++  int y_space = (s->mb_width*16)*(s->mb_height*16+beyond_size);
++  int c_space = (s->mb_width*16)*(s->mb_height*8+(beyond_size/2));
++  int y_every_space = (s->mb_width*16)*beyond_size;
++  int c_every_space = (s->mb_width*16)*(beyond_size/2);
++
++  int mb_total = s->mb_width * s->mb_height;
++
++  int spe_frm = 0;
++  int spe_ad_flag = 0;
++  int spe_mi_flag = 0;
++  int last_spe_ad_flag = 0;
++  int last_spe_mi_flag = 0;
++  int c_ofst_addr_n = ((s->frame_idx)*c_every_space)/c_space;
++  int last_c_ofst_addr_n = ((s->frame_idx-1)*c_every_space)/c_space;
++
++  if(mb_total%2){
++    //spe_frm = 1;
++  }
++
++  //buf_beyond_yaddr
++  buf_addr_group[0] = s->fb[0][0] + y_space;
++  //buf_beyond_caddr
++  buf_addr_group[1] = spe_frm ? s->fb[0][1] + c_space + (128*C_SPE_ADD_MB_NUM) : s->fb[0][1] + c_space;
++  int tmp_beyond_caddr = spe_frm ? s->fb[0][1] + c_space + 128 : s->fb[0][1] + c_space;
++
++  //calc last frame addr
++  int last_y_ofst_addr = s->frame_idx == 0 ? 0 : ((s->frame_idx-1)*y_every_space)%y_space;
++  int last_y_tmp_addr  = last_y_ofst_addr ? (buf_addr_group[0] - last_y_ofst_addr) : s->fb[0][0];
++
++  int last_c_ofst_addr = s->frame_idx == 0 ? 0 : ((s->frame_idx-1)*c_every_space)%c_space;
++  int last_c_tmp_addr  = last_c_ofst_addr ? (tmp_beyond_caddr - last_c_ofst_addr) : s->fb[0][1];
++
++  if(spe_frm & last_c_tmp_addr != s->fb[0][1]){
++    if(last_c_ofst_addr_n%2){
++      last_c_tmp_addr -= 256;
++      last_spe_mi_flag = 1;
++    }
++
++    if(last_c_tmp_addr%256){
++      last_c_tmp_addr += 128;
++      last_spe_ad_flag = 1;
++    }
++
++    if((last_c_tmp_addr + c_every_space > buf_addr_group[1]) & last_spe_mi_flag){
++      last_c_tmp_addr += 256;
++    }
++  }
++
++
++  //refy_addr_ba0
++  buf_addr_group[4]  = s->frame_idx == 0 ? s->fb[0][0] : last_y_tmp_addr;
++  //refy_addr_ba1
++  buf_addr_group[5]  = s->fb[0][0];
++  //refc_addr_ba0
++  buf_addr_group[6]  = s->frame_idx == 0 ? s->fb[0][1] : last_c_tmp_addr;
++  //refc_addr_ba1
++  buf_addr_group[7]  = s->fb[0][1];
++  //ref_mby_size
++  *buf_ref_mby_size  = !s->buf_share_en ? 0xff : ((buf_addr_group[0] - buf_addr_group[4])/(s->mb_width*16))/16 - 1;
++
++
++  int y_ofst_addr   = (s->frame_idx*y_every_space)%y_space;
++  int y_tmp_addr    = y_ofst_addr ? (buf_addr_group[0] - y_ofst_addr) : s->fb[0][0];
++  //buf_start_yaddr
++  buf_addr_group[2]   = s->frame_idx == 0 ? s->fb[0][0] : y_tmp_addr;
++
++  int c_ofst_addr   = (s->frame_idx*c_every_space)%c_space;
++  int c_tmp_addr    = c_ofst_addr ? (tmp_beyond_caddr - c_ofst_addr) : s->fb[0][1];
++  //buf_start_caddr
++  buf_addr_group[3]   = s->frame_idx == 0 ? s->fb[0][1] : c_tmp_addr;
++
++  int spe_flag = 1;
++  if(spe_frm & buf_addr_group[3] != s->fb[0][1]){
++    if(c_ofst_addr_n%2){
++      buf_addr_group[3] -= 256;
++      spe_mi_flag = 1;
++    }
++
++    if(buf_addr_group[3]%256){
++      buf_addr_group[3] += 128;
++      spe_ad_flag = 1;
++    }
++
++    if((buf_addr_group[3] + c_every_space > buf_addr_group[1]) & spe_mi_flag){
++      buf_addr_group[3] += 256;
++      spe_flag = 0;
++    }
++
++  }
++
++  *buf_odma_spe_flag = spe_flag;
++
++  int alg_flag = 0;
++  int c_pxl_space_row = s->mb_width*16*8;
++  if(((buf_addr_group[1] - (128*C_SPE_ADD_MB_NUM)) - buf_addr_group[3])% c_pxl_space_row == 0 )
++    alg_flag = 1;
++
++  *buf_odma_alg_flag = alg_flag;
++}
++
++
++
++void H264E_SliceInit(_H264E_SliceInfo *s)
++{
++  unsigned int i, j/*, tmp = 0*/;
++  volatile unsigned int *chn = (volatile unsigned int *)s->des_va;
++
++  GEN_VDMA_ACFG(chn, TCSM_FLUSH, 0, 0);
++
++
++  /**************************************************
++   buf share cfg
++   *************************************************/
++
++  uint32_t buf_addr_group[8];
++  uint8_t buf_ref_mby_size;
++  uint8_t buf_odma_spe_flag;
++  uint8_t buf_odma_alg_flag;
++
++  BUF_SHARE_CFG(s, buf_addr_group, &buf_ref_mby_size, &buf_odma_spe_flag, &buf_odma_alg_flag);
++
++  uint32_t buf_beyond_yaddr = buf_addr_group[0];
++  uint32_t buf_beyond_caddr = buf_addr_group[1];
++  uint32_t buf_start_yaddr  = buf_addr_group[2];
++  uint32_t buf_start_caddr  = buf_addr_group[3];
++  uint32_t refy_addr_ba0 = buf_addr_group[4];
++  uint32_t refy_addr_ba1 = buf_addr_group[5];
++  uint32_t refc_addr_ba0 = buf_addr_group[6];
++  uint32_t refc_addr_ba1 = buf_addr_group[7];
++  uint8_t  ref_mby_size = buf_ref_mby_size;
++  uint8_t  odma_spe_flag = buf_odma_spe_flag;
++  uint8_t  odma_alg_flag = buf_odma_alg_flag;
++
++  if(0){
++  printf("[BUF_SHARE] frame_idx: %d,  y_start: 0x%x, y_base: 0x%x, y_beyond: 0x%x, spe_flag: %d, alg_flag: %d\n",
++	 s->frame_idx,buf_addr_group[2],s->fb[0][0],buf_addr_group[0],odma_spe_flag,odma_alg_flag);
++  printf("                            c_start: 0x%x, c_base: 0x%x, c_beyond: 0x%x\n",
++	 buf_addr_group[3],s->fb[0][1],buf_addr_group[1]);
++  printf("                            ifa_y0: 0x%x, ifa_y1: 0x%x, ifa_c0: 0x%x, ifa_c1: 0x%x, mby: %d\n",
++	 buf_addr_group[4],buf_addr_group[5],buf_addr_group[6],buf_addr_group[7],buf_ref_mby_size);
++  }
++
++  /**************************************************
++   EFE configuration
++   *************************************************/
++  GEN_VDMA_ACFG(chn, REG_EFE_GEOM, 0, (EFE_FST_MBY(s->first_mby) |
++				       EFE_LST_MBY(s->last_mby) |
++				       EFE_LST_MBX(MB_WID-1)) );
++
++  GEN_VDMA_ACFG(chn, REG_EFE_COEF_BA, 0, VRAM_MAU_RESA);
++  GEN_VDMA_ACFG(chn, REG_EFE_RAWY_SBA, 0, s->raw[0]);
++  GEN_VDMA_ACFG(chn, REG_EFE_RAWU_SBA, 0, s->raw[1]);
++  GEN_VDMA_ACFG(chn, REG_EFE_RAWV_SBA, 0, s->raw[2]);
++  GEN_VDMA_ACFG(chn, REG_EFE_RAW_STRD, 0, (EFE_RAW_STRDY(s->stride[0]) |
++					   EFE_RAW_STRDC(s->stride[1]) ) );
++  GEN_VDMA_ACFG(chn, REG_EFE_TOPMV_BA, 0, VRAM_TOPMV_BA);
++  GEN_VDMA_ACFG(chn, REG_EFE_TOPPA_BA, 0, VRAM_TOPPA_BA);
++  GEN_VDMA_ACFG(chn, REG_EFE_MECHN_BA, 0, VRAM_ME_CHN_BASE);
++  GEN_VDMA_ACFG(chn, REG_EFE_MAUCHN_BA, 0, VRAM_MAU_CHN_BASE);
++  GEN_VDMA_ACFG(chn, REG_EFE_DBLKCHN_BA, 0, VRAM_DBLK_CHN_BASE);
++  GEN_VDMA_ACFG(chn, REG_EFE_SDECHN_BA, 0, VRAM_SDE_CHN_BASE);
++  GEN_VDMA_ACFG(chn, REG_EFE_RAW_DBA, 0, VRAM_RAWY_BA);
++
++  GEN_VDMA_ACFG(chn, REG_EFE_ROI_MAX_QP, 0, s->max_qp);
++
++  GEN_VDMA_ACFG(chn, REG_EFE_ROI_BASE_INFO0, 0,
++		(( (s->roi_info[3].roi_qp & 0x3F) <<2 |
++		   (s->roi_info[3].roi_md & 0x1)  <<1 |
++		   (s->roi_info[3].roi_en & 0x1)  <<0 ) << 24) |
++		(( (s->roi_info[2].roi_qp & 0x3F) <<2 |
++		   (s->roi_info[2].roi_md & 0x1)  <<1 |
++		   (s->roi_info[2].roi_en & 0x1)  <<0 ) << 16) |
++		(( (s->roi_info[1].roi_qp & 0x3F) <<2 |
++		   (s->roi_info[1].roi_md & 0x1)  <<1 |
++		   (s->roi_info[1].roi_en & 0x1)  <<0 ) << 8) |
++		(( (s->roi_info[0].roi_qp & 0x3F) <<2 |
++		   (s->roi_info[0].roi_md & 0x1)  <<1 |
++		   (s->roi_info[0].roi_en & 0x1)  <<0 ) << 0)
++		);
++
++  GEN_VDMA_ACFG(chn, REG_EFE_ROI_BASE_INFO1, 0,
++		(( (s->roi_info[7].roi_qp & 0x3F) <<2 |
++		   (s->roi_info[7].roi_md & 0x1)  <<1 |
++		   (s->roi_info[7].roi_en & 0x1)  <<0 ) << 24) |
++		(( (s->roi_info[6].roi_qp & 0x3F) <<2 |
++		   (s->roi_info[6].roi_md & 0x1)  <<1 |
++		   (s->roi_info[6].roi_en & 0x1)  <<0 ) << 16) |
++		(( (s->roi_info[5].roi_qp & 0x3F) <<2 |
++		   (s->roi_info[5].roi_md & 0x1)  <<1 |
++		   (s->roi_info[5].roi_en & 0x1)  <<0 ) << 8) |
++		(( (s->roi_info[4].roi_qp & 0x3F) <<2 |
++		   (s->roi_info[4].roi_md & 0x1)  <<1 |
++		   (s->roi_info[4].roi_en & 0x1)  <<0 ) << 0)
++		);
++
++
++  GEN_VDMA_ACFG(chn, REG_EFE_ROI_POS_INFO0, 0,
++		( (s->roi_info[0].roi_bmby & 0xFF) << 24 |
++		  (s->roi_info[0].roi_umby & 0xFF) << 16 |
++		  (s->roi_info[0].roi_rmbx & 0xFF) << 8  |
++		  (s->roi_info[0].roi_lmbx & 0xFF) << 0  )
++		);
++
++  GEN_VDMA_ACFG(chn, REG_EFE_ROI_POS_INFO1, 0,
++		( (s->roi_info[1].roi_bmby & 0xFF) << 24 |
++		  (s->roi_info[1].roi_umby & 0xFF) << 16 |
++		  (s->roi_info[1].roi_rmbx & 0xFF) << 8  |
++		  (s->roi_info[1].roi_lmbx & 0xFF) << 0  )
++		);
++
++  GEN_VDMA_ACFG(chn, REG_EFE_ROI_POS_INFO2, 0,
++		( (s->roi_info[2].roi_bmby & 0xFF) << 24 |
++		  (s->roi_info[2].roi_umby & 0xFF) << 16 |
++		  (s->roi_info[2].roi_rmbx & 0xFF) << 8  |
++		  (s->roi_info[2].roi_lmbx & 0xFF) << 0  )
++		);
++
++  GEN_VDMA_ACFG(chn, REG_EFE_ROI_POS_INFO3, 0,
++		( (s->roi_info[3].roi_bmby & 0xFF) << 24 |
++		  (s->roi_info[3].roi_umby & 0xFF) << 16 |
++		  (s->roi_info[3].roi_rmbx & 0xFF) << 8  |
++		  (s->roi_info[3].roi_lmbx & 0xFF) << 0  )
++		);
++
++  GEN_VDMA_ACFG(chn, REG_EFE_ROI_POS_INFO4, 0,
++		( (s->roi_info[4].roi_bmby & 0xFF) << 24 |
++		  (s->roi_info[4].roi_umby & 0xFF) << 16 |
++		  (s->roi_info[4].roi_rmbx & 0xFF) << 8  |
++		  (s->roi_info[4].roi_lmbx & 0xFF) << 0  )
++		);
++
++  GEN_VDMA_ACFG(chn, REG_EFE_ROI_POS_INFO5, 0,
++		( (s->roi_info[5].roi_bmby & 0xFF) << 24 |
++		  (s->roi_info[5].roi_umby & 0xFF) << 16 |
++		  (s->roi_info[5].roi_rmbx & 0xFF) << 8  |
++		  (s->roi_info[5].roi_lmbx & 0xFF) << 0  )
++		);
++
++  GEN_VDMA_ACFG(chn, REG_EFE_ROI_POS_INFO6, 0,
++		( (s->roi_info[6].roi_bmby & 0xFF) << 24 |
++		  (s->roi_info[6].roi_umby & 0xFF) << 16 |
++		  (s->roi_info[6].roi_rmbx & 0xFF) << 8  |
++		  (s->roi_info[6].roi_lmbx & 0xFF) << 0  )
++		);
++
++  GEN_VDMA_ACFG(chn, REG_EFE_ROI_POS_INFO7, 0,
++		( (s->roi_info[7].roi_bmby & 0xFF) << 24 |
++		  (s->roi_info[7].roi_umby & 0xFF) << 16 |
++		  (s->roi_info[7].roi_rmbx & 0xFF) << 8  |
++		  (s->roi_info[7].roi_lmbx & 0xFF) << 0  )
++		);
++
++  GEN_VDMA_ACFG(chn, REG_EFE_QP_GEN_TAB, 0, ( (VRAM_QP_TAB_BA & 0xFFFFF) |
++					      ((s->qp_tab_len & 0x7FF) << 20) |
++					      (s->qp_tab_mode & 0x1)<<31) );
++  /*
++  for(i=0; i<s->qp_tab_len;i++){
++    GEN_VDMA_ACFG(chn, VRAM_QP_TAB_BA+i*4, 0, *(s->qp_tab+i));
++  }
++  */
++  GEN_VDMA_ACFG(chn, REG_EFE_CQP_OFST, 0, (s->cqp_offset & 0x1F));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_SSAD, 0, 0);
++
++  GEN_VDMA_ACFG(chn, REG_EFE_DCS, 0,
++		( EFE_DCS_EN(s->daisy_chain_en) |
++		  EFE_DCS_OTH(s->curr_thread_id) |
++		  EFE_DCS_RT(4) )
++		);
++  /*
++  GEN_VDMA_ACFG(chn, REG_EFE_QPG_CTRL , 0, (s->sas_en       << 0 |
++					    s->crp_en       << 1 |
++					    s->sas_mthd     << 2 |
++					    0               << 3 |
++					    s->rc_bu_level  << 4 |
++					    s->rc_wait_en   << 7 |
++					    s->base_qp      << 8 |
++					    s->rc_mb_level  << 14 |
++					    s->min_qp       << 16 |
++					    s->qp_tab_en    << 22 |
++					    s->mbrc_qpg_sel << 23 | // 0 : only mbrc_ofst valid;  1: both mbrc_ofst and qpg_ofst valid
++					    s->max_qp       << 24 |
++					    s->mbrc_enable  << 30 |
++					    s->mbrc_wait    << 31 ));
++  */
++  GEN_VDMA_ACFG(chn, REG_EFE_QPG_CTRL , 0, (s->sas_en       << 0 |
++					    s->crp_en       << 1 |
++					    s->sas_mthd     << 2 |
++					    0               << 3 |
++					    s->rc_bu_level  << 4 |
++					    s->rc_bu_wait_en   << 7 |
++					    s->base_qp      << 8 |
++					    s->rc_mb_level  << 14 |
++					    s->min_qp       << 16 |
++					    s->qp_tab_en    << 22 |
++					    s->mbrc_qpg_sel << 23 |//0:mb_rc effect, 1:mb_rc + qpg effect
++					    s->max_qp       << 24 |
++					    s->rc_mb_wait_en  << 30 |
++					    (s->rc_mb_en & 0x1) << 31 ));//mb_rc_en
++
++  GEN_VDMA_ACFG(chn, REG_EFE_QPG_CFG0, 0, ((s->qpg_flt_thd[0] & 0x7) << 0 |
++					   (s->qpg_flt_thd[1] & 0x7) << 4 |
++					   (s->qpg_flt_thd[2] & 0xF) << 8 |
++					   (s->qpg_flt_thd[3] & 0x7) << 12 |
++					   (s->qpg_flt_thd[4] & 0x7) << 16 ));
++
++
++  GEN_VDMA_ACFG(chn, REG_EFE_QPG_CFG1 , 0, (s->qpg_mb_thd[0] << 0 |
++					    s->qpg_mb_thd[1] << 16 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_QPG_CFG2 , 0, (s->qpg_mb_thd[2] << 0 |
++					    s->qpg_mb_thd[3] << 16 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_QPG_CFG3 , 0, (s->qpg_mb_thd[4] << 0 |
++					    s->qpg_mb_thd[5] << 16 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_QPG_CFG4 , 0, (s->qpg_mb_thd[6] << 0 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_QPG_CFG5 , 0, ((s->qpg_mbqp_ofst[0] & 0x3F) << 0 |
++					    (s->qpg_mbqp_ofst[1] & 0x3F) << 8 |
++					    (s->qpg_mbqp_ofst[2] & 0x3F) << 16 |
++					    (s->qpg_mbqp_ofst[3] & 0x3F) << 24 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_QPG_CFG6 , 0, ((s->qpg_mbqp_ofst[4] & 0x3F) << 0 |
++					    (s->qpg_mbqp_ofst[5] & 0x3F) << 8 |
++					    (s->qpg_mbqp_ofst[6] & 0x3F) << 16 |
++					    (s->qpg_mbqp_ofst[7] & 0x3F) << 24 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_EIGEN_CFG0 , 0, ((s->force_i16 & 0x1) << 0 |
++					      (s->refresh_en & 0x1) << 1 |
++					      (s->refresh_mode & 0x1) << 2 |
++					      (s->refresh_bias & 0x7) << 3 |
++					      (s->sas_eigen_en & 0x1)    << 6 |
++					      (s->crp_eigen_en & 0x1)    << 7 |
++					      (s->sas_eigen_dump & 0x1)  << 8 |
++					      (s->crp_eigen_dump & 0x1)  << 9 |
++					      (s->cplx_thd_sel & 0x1) << 10 |
++					      (s->diff_cplx_sel & 0x1) << 11 |
++					      (s->diff_thd_sel & 0x3) << 12 |
++					      (s->mb_mode_use & 0x1)  << 14 |
++					      (s->rrs_en & 0x1) << 15 |
++					      (s->refresh_cplx_thd & 0xFF) << 16 |
++					      (s->i16dc_cplx_thd & 0xFF) << 24 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_EIGEN_CFG1 , 0, ((s->i16dc_qp_base & 0x3F) << 0 |
++					      (s->i16dc_qp_sel & 0x1) << 6 |
++					      (s->i16_qp_base & 0x3F) << 8 |
++					      (s->i16_qp_sel & 0x1) << 14 |
++					      (s->diff_qp_base[0] & 0x3F) << 16 |
++					      (s->diff_qp_sel[0] & 0x1) << 22 |
++					      (s->diff_qp_base[1] & 0x3F) << 24 |
++					      (s->diff_qp_sel[1] & 0x1) << 30 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_EIGEN_CFG2 , 0, ((s->cplx_thd_idx[0] & 0x7) << 0 |
++					      (s->cplx_thd_idx[1] & 0x7) << 3 |
++					      (s->cplx_thd_idx[2] & 0x7) << 6 |
++					      (s->cplx_thd_idx[3] & 0x7) << 9 |
++					      (s->cplx_thd_idx[4] & 0x7) << 12 |
++					      (s->cplx_thd_idx[5] & 0x7) << 15 |
++					      (s->cplx_thd_idx[6] & 0x7) << 18 |
++					      (s->cplx_thd_idx[7] & 0x7) << 21 |
++					      (s->cplx_thd_idx[8] & 0x7) << 24 |
++					      (s->cplx_thd_idx[9] & 0x7) << 27 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_EIGEN_CFG3 , 0, ((s->cplx_thd_idx[10] & 0x7) << 0 |
++					      (s->cplx_thd_idx[11] & 0x7) << 3 |
++					      (s->cplx_thd_idx[12] & 0x7) << 6 |
++					      (s->cplx_thd_idx[13] & 0x7) << 9 |
++					      (s->cplx_thd_idx[14] & 0x7) << 12 |
++					      (s->cplx_thd_idx[15] & 0x7) << 15 |
++					      (s->cplx_thd_idx[16] & 0x7) << 18 |
++					      (s->cplx_thd_idx[17] & 0x7) << 21 |
++					      (s->cplx_thd_idx[18] & 0x7) << 24 |
++					      (s->cplx_thd_idx[19] & 0x7) << 27 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_EIGEN_CFG4 , 0, ((s->cplx_thd_idx[20] & 0x7) << 0 |
++					      (s->cplx_thd_idx[21] & 0x7) << 3 |
++					      (s->cplx_thd_idx[22] & 0x7) << 6 |
++					      (s->cplx_thd_idx[23] & 0x7) << 9 |
++					      (s->diff_cplx_thd & 0xFF) << 24 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_EIGEN_CFG5 , 0, ((s->cplx_thd[0] & 0xFF) << 0 |
++					      (s->cplx_thd[1] & 0xFF) << 8 |
++					      (s->cplx_thd[2] & 0xFF) << 16 |
++					      (s->cplx_thd[3] & 0xFF) << 24 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_EIGEN_CFG6 , 0, ((s->cplx_thd[4] & 0xFF) << 0 |
++					      (s->cplx_thd[5] & 0xFF) << 8 |
++					      (s->cplx_thd[6] & 0xFF) << 16 |
++					      (s->cplx_thd[7] & 0xFF) << 24 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_DIFFY_CFG , 0, ((s->diff_thd_base[0] & 0xFFFF) << 0 |
++					     (s->diff_thd_ofst[0] & 0xFFFF) << 16 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_DIFFU_CFG , 0, ((s->diff_thd_base[1] & 0xFFFF) << 0 |
++					     (s->diff_thd_ofst[1] & 0xFFFF) << 16 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_DIFFV_CFG , 0, ((s->diff_thd_base[2] & 0xFFFF) << 0 |
++					     (s->diff_thd_ofst[2] & 0xFFFF) << 16 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_SKIN_CTRL , 0, ((s->skin_dt_en & 0x1) << 0 |
++					     (s->skin_lvl & 0x3) << 1 |
++					     (s->ncu_mov_en & 0x1) << 3 |
++					     (s->skin_cnt_thd & 0x7F) << 8 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_SKIN_PTHD0 , 0, ((s->skin_pxlu_thd[0][0] & 0xFF) << 0 |
++					      (s->skin_pxlu_thd[0][1] & 0xFF) << 8 |
++					      (s->skin_pxlv_thd[0][0] & 0xFF) << 16 |
++					      (s->skin_pxlv_thd[0][1] & 0xFF) << 24 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_SKIN_PTHD1 , 0, ((s->skin_pxlu_thd[1][0] & 0xFF) << 0 |
++					      (s->skin_pxlu_thd[1][1] & 0xFF) << 8 |
++					      (s->skin_pxlv_thd[1][0] & 0xFF) << 16 |
++					      (s->skin_pxlv_thd[1][1] & 0xFF) << 24 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_SKIN_PTHD2 , 0, ((s->skin_pxlu_thd[2][0] & 0xFF) << 0 |
++					      (s->skin_pxlu_thd[2][1] & 0xFF) << 8 |
++					      (s->skin_pxlv_thd[2][0] & 0xFF) << 16 |
++					      (s->skin_pxlv_thd[2][1] & 0xFF) << 24 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_SKIN_QP_OFST , 0, ((s->skin_qp_ofst[0] & 0x3F) << 0 |
++						(s->skin_qp_ofst[1] & 0x3F) << 8 |
++						(s->skin_qp_ofst[2] & 0x3F) << 16 |
++						(s->skin_qp_ofst[3] & 0x3F) << 24 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_SKIN_PARAM0 , 0, ((s->mult_factor[0] & 0xF) << 0 |
++					       (s->shift_factor[0][0] & 0x7) << 4 |
++					       (s->shift_factor[0][1] & 0x7) << 8 |
++					       (s->skin_ofst[1] & 0x3FF) << 11 |
++					       (s->skin_ofst[0] & 0x3FF) << 21 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_SKIN_PARAM1 , 0, ((s->mult_factor[1] & 0xF) << 0 |
++					       (s->shift_factor[1][0] & 0x7) << 8 |
++					       (s->shift_factor[1][1] & 0x7) << 12 |
++					       (s->shift_factor[1][2] & 0x7) << 16 |
++					       (s->skin_ofst[2] & 0x3FF) << 20 ));
++
++  GEN_VDMA_ACFG(chn, REG_EFE_SKIN_PARAM2 , 0, ((s->mult_factor[2] & 0xF) << 0 |
++					       (s->shift_factor[2][0] & 0x7) << 8 |
++					       (s->shift_factor[2][1] & 0x7) << 12 |
++					       (s->shift_factor[2][2] & 0x7) << 16 |
++					       (s->skin_ofst[3] & 0x3FF) << 20 ));
++
++  /**************************************************
++   RC configuration
++   *************************************************/
++  if(s->rc_mb_en){ //rate ctrl
++    //fprintf(stderr,"s->rc_bu_wait_en:%d\n",s->rc_bu_wait_en);
++    //fprintf(stderr,"s->last_bu_size:%d, s->rc_bu_size:%d\n",s->last_bu_size, s->rc_bu_size);
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_BINFO1, 0, EFE_RC_BU_LSIZE(s->last_bu_size) | EFE_RC_BU_SIZE(s->rc_bu_size));
++    //fprintf(stderr,"s->tar_bs_thd[0]:%d, s->tar_bs_thd[1]:%d\n",s->tar_bs_thd[0],s->tar_bs_thd[1]);
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_GP0THD, 0, ((s->tar_bs_thd[0] & 0xFFFF) << 0 |
++					      (s->tar_bs_thd[1] & 0xFFFF) << 16));
++    //fprintf(stderr,"s->tar_bs_thd[2]:%d, s->tar_bs_thd[3]:%d\n",s->tar_bs_thd[2],s->tar_bs_thd[3]);
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_GP1THD, 0, ((s->tar_bs_thd[2] & 0xFFFF) << 0 |
++					      (s->tar_bs_thd[3] & 0xFFFF) << 16));
++    //fprintf(stderr,"s->tar_bs_thd[4]:%d, s->tar_bs_thd[5]:%d\n",s->tar_bs_thd[4],s->tar_bs_thd[5]);
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_GP2THD, 0, ((s->tar_bs_thd[4] & 0xFFFF) << 0 |
++					      (s->tar_bs_thd[5] & 0xFFFF) << 16));
++    //fprintf(stderr,"s->rc_frm_tbs:%d\n",s->rc_frm_tbs & 0x7FFFFFFF);
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_TBS,    0, s->rc_frm_tbs & 0x7FFFFFFF);
++    //fprintf(stderr,"s->bu_alg0_qpo[2]:%d, s->bu_alg0_qpo[1]:%d, s->bu_alg0_qpo[0]:%d\n",s->bu_alg0_qpo[2], s->bu_alg0_qpo[1], s->bu_alg0_qpo[0]);
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_BNQA0, 0, EFE_RC_QPO_CFG(0, s->bu_alg0_qpo[2], s->bu_alg0_qpo[1], s->bu_alg0_qpo[0]));
++    //fprintf(stderr,"s->bu_alg0_qpo[5]:%d, s->bu_alg0_qpo[4]:%d, s->bu_alg0_qpo[3]:%d\n",s->bu_alg0_qpo[5], s->bu_alg0_qpo[4], s->bu_alg0_qpo[3]);
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_BPQA0, 0, EFE_RC_QPO_CFG(0, s->bu_alg0_qpo[5], s->bu_alg0_qpo[4], s->bu_alg0_qpo[3]));
++    //fprintf(stderr,"s->bu_alg1_qpo[2]:%d, s->bu_alg1_qpo[1]:%d, s->bu_alg1_qpo[0]:%d\n",s->bu_alg1_qpo[2], s->bu_alg1_qpo[1], s->bu_alg1_qpo[0]);
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_BNQA1, 0, EFE_RC_QPO_CFG(0, s->bu_alg1_qpo[2], s->bu_alg1_qpo[1], s->bu_alg1_qpo[0]));
++    //fprintf(stderr,"s->bu_alg1_qpo[5]:%d, s->bu_alg1_qpo[4]:%d, s->bu_alg1_qpo[3]:%d\n",s->bu_alg1_qpo[5], s->bu_alg1_qpo[4], s->bu_alg1_qpo[3]);
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_BPQA1, 0, EFE_RC_QPO_CFG(0, s->bu_alg1_qpo[5], s->bu_alg1_qpo[4], s->bu_alg1_qpo[3]));
++    //fprintf(stderr,"s->mb_cs_qpo[2]:%d, s->mb_cs_qpo[1]:%d, s->mb_cs_qpo[0]:%d\n",s->mb_cs_qpo[2], s->mb_cs_qpo[1], s->mb_cs_qpo[0]);
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_MNQCS, 0, EFE_RC_QPO_CFG(0, s->mb_cs_qpo[2], s->mb_cs_qpo[1], s->mb_cs_qpo[0]));
++    //fprintf(stderr,"s->mb_cs_qpo[6]:%d, s->mb_cs_qpo[5]:%d, s->mb_cs_qpo[4]:%d, s->mb_cs_qpo[3]:%d\n",
++    //s->mb_cs_qpo[6], s->mb_cs_qpo[5], s->mb_cs_qpo[4], s->mb_cs_qpo[3]);
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_MPQCS, 0, EFE_RC_QPO_CFG(s->mb_cs_qpo[6], s->mb_cs_qpo[5], s->mb_cs_qpo[4], s->mb_cs_qpo[3]));
++    //fprintf(stderr,"s->mb_top_bs_qpo[1]:%d, s->mb_top_bs_qpo[0]:%d\n",s->mb_top_bs_qpo[1], s->mb_top_bs_qpo[0]);
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_MTBQ, 0, EFE_RC_QPO_CFG(0, 0, s->mb_top_bs_qpo[1], s->mb_top_bs_qpo[0]));
++    //fprintf(stderr,"s->mb_rinfo_qpo[1]:%d, s->mb_rinfo_qpo[0]:%d\n",s->mb_rinfo_qpo[1], s->mb_rinfo_qpo[0]);
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_MRFQ, 0, EFE_RC_QPO_CFG(0, 0, s->mb_rinfo_qpo[1], s->mb_rinfo_qpo[0]));
++    //fprintf(stderr,"s->mb_target_avg_bs[1]:%d, s->mb_target_avg_bs[0]:%d\n",s->mb_target_avg_bs[1], s->mb_target_avg_bs[0]);
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_MAMIN, 0, s->mb_target_avg_bs[0] & 0x3FFFF);
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_MAMAX, 0, s->mb_target_avg_bs[1] & 0x3FFFF);
++    //fprintf(stderr,"s->rc_bu_num:%d, s->mb_gp_num:%d\n",s->rc_bu_num, s->mb_gp_num);
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_BBS, 0, s->avg_bu_bs & 0x7FFFFF);
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_MINFO, 0, (//EFE_RC_MAD_CFG_RDY |
++					     EFE_RC_MBGP_NUM(s->mb_gp_num) |
++					     (s->rc_mb_en & 0x1)));
++    char rc_slice_type = s->rc_frm_tbs ? s->frame_type : 0;
++    GEN_VDMA_ACFG(chn, REG_EFE_RC_BINFO0, 0, (EFE_RC_SLICE_TP(rc_slice_type) |
++                          EFE_RC_BU_CFG(s->rc_bcfg_mode) |
++					      EFE_RC_BU_NUM(s->rc_bu_num) |
++					      ((s->rc_mb_en>>1) & 0x1)));
++  }
++
++  /**************************************************
++   JRFD configuration
++   *************************************************/
++  GEN_VDMA_ACFG(chn, REG_JRFD_CTRL, 0, (((1==2)<<31) | /* 2:NV21 ,1:NV12*/
++					(2 << 28) |//sim_lvl
++					(s->jrfd_enable << 27) |
++					(s->frame_height << 14) |
++					s->frame_width));
++  GEN_VDMA_ACFG(chn, REG_JRFD_HDYA, 0, s->jh[1][0]);
++  GEN_VDMA_ACFG(chn, REG_JRFD_HDCA, 0, s->jh[1][1]);
++
++  GEN_VDMA_ACFG(chn, REG_JRFD_HSTR, 0, (((s->cm_head_total & 0xffff) << 16) | (s->lm_head_total & 0xffff)) );
++
++  GEN_VDMA_ACFG(chn, REG_JRFD_BDYA, 0, s->fb[1][0]);//tile Y address
++  GEN_VDMA_ACFG(chn, REG_JRFD_BDCA, 0, s->fb[1][1]); //tile C address
++
++  GEN_VDMA_ACFG(chn, REG_JRFD_BSTR, 0,
++		JRFD_BODY_STRDY(((s->frame_width+15)/16)*16) |
++		JRFD_BODY_STRDC(((s->frame_width+15)/16)*8) );
++
++  GEN_VDMA_ACFG(chn, REG_JRFD_MHDY, 0, s->jh[2][0]);
++  GEN_VDMA_ACFG(chn, REG_JRFD_MHDC, 0, s->jh[2][1]);
++  GEN_VDMA_ACFG(chn, REG_JRFD_MBDY, 0, s->fb[2][0]);
++  GEN_VDMA_ACFG(chn, REG_JRFD_MBDC, 0, s->fb[2][1]);
++
++  GEN_VDMA_ACFG(chn, REG_JRFD_TRIG, 0, ((1 << 5) |//init
++					(0 << 4)  //ckg low means do clock-gating
++					));//enable_tile
++
++  /**************************************************
++   Motion configuration
++  *************************************************/
++  if(s->frame_type){
++    //set CHAIN/TMV/SYNC ADDR
++    GEN_VDMA_ACFG(chn, REG_MCE_CHN_BA, 0, VRAM_ME_CHN_BASE);//chn
++    GEN_VDMA_ACFG(chn, REG_MCE_TMV_BA, 0, VRAM_TOPMV_BA);//tmv
++    GEN_VDMA_ACFG(chn, REG_MCE_CHN_SYNC, 0, VRAM_ME_DSA);//sync
++
++    //set frame size
++    GEN_VDMA_ACFG(chn, REG_MCE_FRM_SIZE, 0,
++		  MCE_FRM_SIZE_FH(s->frame_height-1) |
++		  MCE_FRM_SIZE_FW(s->frame_width-1) |
++		  MCE_FRM_SIZE_LRE(s->frm_re[0]) |
++		  MCE_FRM_SIZE_RRE(s->frm_re[1]) |
++		  MCE_FRM_SIZE_TRE(s->frm_re[2]) |
++		  MCE_FRM_SIZE_BRE(s->frm_re[3]) );
++
++    //set frame stride
++    GEN_VDMA_ACFG(chn, REG_MCE_FRM_STRD, 0,
++		  MCE_FRM_STRD_STRDC(((s->frame_width+15)/16)*16) |
++		  MCE_FRM_STRD_STRDY(((s->frame_width+15)/16)*16) );
++
++    //set COMP_CTRL
++    GEN_VDMA_ACFG(chn, REG_MCE_COMP_CTRL, 0,
++		  MCE_COMP_CTRL_CCE |
++		  MCE_COMP_CTRL_CTAP(MCE_TAP_TAP2) |
++		  MCE_COMP_CTRL_CSPT(MCE_SPT_BILI) |
++		  MCE_COMP_CTRL_CSPP(MCE_SPP_EPEL) |
++		  MCE_COMP_CTRL_YCE |
++		  MCE_COMP_CTRL_YTAP(MCE_TAP_TAP6) |
++		  MCE_COMP_CTRL_YSPT(MCE_SPT_AUTO) |
++		  MCE_COMP_CTRL_YSPP(MCE_SPP_QPEL) );
++
++    //set ESTI_CTRL
++    unsigned int esti_ctrl = 0;
++    esti_ctrl |= (MCE_ESTI_CTRL_LSP(s->lambda_scale_parameter) |
++		  MCE_ESTI_CTRL_SCL(s->scl)/*trbl mvp*/ |
++		  MCE_ESTI_CTRL_FBG(0) |
++		  MCE_ESTI_CTRL_CLMV |
++		  MCE_ESTI_CTRL_MSS(s->max_sech_step_i) |
++		  MCE_ESTI_CTRL_QRL(s->qpel_en) |
++		  MCE_ESTI_CTRL_HRL(s->hpel_en) );
++
++    esti_ctrl |= MCE_ESTI_CTRL_PUE_16X16;
++
++    GEN_VDMA_ACFG(chn, REG_MCE_ESTI_CTRL, 0, esti_ctrl);
++
++    //set MRGI
++    unsigned int merg_info = 0;
++    GEN_VDMA_ACFG(chn, REG_MCE_MRGI, 0, merg_info);
++
++    //set MVR
++    GEN_VDMA_ACFG(chn, REG_MCE_MVR, 0,
++		  MCE_MVR_MVRY(s->max_mvry_i*4) |
++		  MCE_MVR_MVRX(s->max_mvrx_i*4) );
++    if(s->buf_share_en){
++      GEN_VDMA_ACFG(chn, REG_MCE_REFY0, 0, refy_addr_ba0);
++      GEN_VDMA_ACFG(chn, REG_MCE_REFC0, 0, refc_addr_ba0);
++      GEN_VDMA_ACFG(chn, REG_MCE_REFY0_1, 0, refy_addr_ba1);
++      GEN_VDMA_ACFG(chn, REG_MCE_REFC0_1, 0, refc_addr_ba1);
++    }
++    else {
++      GEN_VDMA_ACFG(chn, REG_MCE_REFY0, 0, s->fb[1][0]);
++      GEN_VDMA_ACFG(chn, REG_MCE_REFC0, 0, s->fb[1][1]);
++      GEN_VDMA_ACFG(chn, REG_MCE_REFY0_1, 0, s->fb[3][0]);
++      GEN_VDMA_ACFG(chn, REG_MCE_REFC0_1, 0, s->fb[3][1]);
++    }
++    GEN_VDMA_ACFG(chn, REG_MCE_REFY1, 0, s->fb[2][0]);
++    GEN_VDMA_ACFG(chn, REG_MCE_REFC1, 0, s->fb[2][1]);
++
++    GEN_VDMA_ACFG(chn, REG_MCE_SLC_SPOS, 0, 0);
++    GEN_VDMA_ACFG(chn, REG_MCE_FSC, 0,
++		  MCE_FSC_FSE(s->fs_en) |
++		  MCE_FSC_FSMD(s->fs_md) |
++		  MCE_FSC_PERX(s->fs_px) |
++		  MCE_FSC_PERY(s->fs_py) |
++		  MCE_FSC_RECX(s->fs_rx) |
++		  MCE_FSC_RECY(s->fs_ry)
++		  );
++    GEN_VDMA_ACFG(chn, REG_MCE_GLB_MV, 0, MCE_GLB_MVX(s->glb_mvx) | MCE_GLB_MVY(s->glb_mvy));
++    /**/
++    GEN_VDMA_ACFG(chn, REG_MCE_GLB_CTRL, 0, (MCE_GLB_CTRL_FMV0(s->force_mv0_en) |
++					     MCE_GLB_CTRL_MSTEP(s->me_step_en) |
++					     MCE_GLB_CTRL_STEP1(s->me_step_1) |
++					     MCE_GLB_CTRL_STEP0(s->me_step_0) |
++					     MCE_GLB_CTRL_RBS(ref_mby_size) |
++					     MCE_GLB_CTRL_FMS(s->frm_mv_size) |
++					     MCE_GLB_CTRL_FRMMV(s->frm_mv_en) |
++					     MCE_GLB_CTRL_GLBMV(s->glb_mv_en) |
++					     MCE_GLB_CTRL_DCT8(s->dct8x8_en) |
++                                             MCE_GLB_CTRL_PSKIP(s->pskip_en) | MCE_GLB_CTRL_INIT |
++					     MCE_GLB_CTRL_MREF(s->mref_en) | MCE_GLB_CTRL_RM(s->ref_mode) |
++					     MCE_GLB_CTRL_JRFD(!s->jrfd_enable)));
++  }
++  /**************************************************
++   VMAU configuration
++   *************************************************/
++  GEN_VDMA_ACFG(chn, REG_VMAU_GBL_RUN, 0, VMAU_RESET);
++  GEN_VDMA_ACFG(chn, REG_VMAU_VIDEO_TYPE, 0, (VMAU_MODE_ENC | 6<<7
++					      | VMAU_I4_MSK(0)
++					      | VMAU_I16_MSK(0)
++					      | VMAU_I8_MSK(0)
++					      | VMAU_PT8_MSK(0)
++					      | VMAU_IS_ISLICE(!s->frame_type)
++					      | VMAU_PREDM_MSK(s->intra_mode_msk & 0x1ffff)
++					      | VMAU_TSE(s->use_intra_in_pframe)) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_NCCHN_ADDR, 0, VRAM_MAU_CHN_BASE);
++  GEN_VDMA_ACFG(chn, REG_VMAU_ENC_DONE, 0, VRAM_MAU_ENC_SYNA);
++  GEN_VDMA_ACFG(chn, REG_VMAU_DEC_DONE, 0, VRAM_MAU_DEC_SYNA);
++  GEN_VDMA_ACFG(chn, REG_VMAU_Y_GS, 0, (VMAU_FRM_WID(MB_WID*16)
++					| VMAU_FRM_HEI(MB_HEI*16)) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_GBL_CTR, 0, (VMAU_CTRL_TO_DBLK
++					   | VMAU_CTRL_FIFO_M
++					   | VMAU_LAMBDA_THRETH((s->intra_mode_msk >> 17) & 0x3) ) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_DEADZONE, 0, ( VMAU_DEADZONE0_IY(s->deadzone[0])
++					     | VMAU_DEADZONE1_PY(s->deadzone[1])
++					     | VMAU_DEADZONE2_IC(s->deadzone[2])
++					     | VMAU_DEADZONE3_PC(s->deadzone[3]) ) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_DEADZONE1, 0, ((s->deadzone[4] & 0x3f) << 0 |
++					     (s->deadzone[5] & 0x3f) << 6 |
++					     (s->deadzone[6] & 0x3f) << 12 |
++					     (s->deadzone[7] & 0x3f) << 18 |
++					     (s->deadzone[8] & 0x3f) << 24));
++  GEN_VDMA_ACFG(chn, REG_VMAU_TOP_BASE, 0, VRAM_TOPPA_BA );
++  GEN_VDMA_ACFG(chn, REG_VMAU_MD_CFG0, 0, ( VMAU_MD_SLICE_I(!s->frame_type)
++					    | VMAU_MD_SLICE_P(s->frame_type)
++					    | VMAU_MD_I4_DIS(0)
++					    | VMAU_MD_I16_DIS(0)
++					    | VMAU_MD_PSKIP_DIS(0)
++					    | VMAU_MD_P_L0_DIS(0)
++					    | VMAU_MD_I8_DIS(0)
++					    | VMAU_MD_PT8_DIS(0)
++					    | VMAU_MD_DREF_EN(s->mref_en)
++					    | VMAU_MD_DCT8_EN(s->dct8x8_en)
++					    | VMAU_MD_FRM_REDGE(MB_WID - 1)
++					    | VMAU_MD_FRM_BEDGE(MB_HEI - 1) ) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_MD_CFG1, 0, ( VMAU_IPMY_BIAS_EN(s->intra_lambda_y_bias_en)
++					    | VMAU_IPMC_BIAS_EN(s->intra_lambda_c_bias_en)
++					    | VMAU_COST_BIAS_EN(s->cost_bias_en)
++					    | VMAU_CSSE_BIAS_EN(s->chroma_sse_bias_en)
++					    | VMAU_JMLAMBDA2_EN(s->jm_lambda2_en)
++					    | VMAU_INTER_NEI_EN(s->inter_nei_en)
++					    | VMAU_SKIP_BIAS_EN(s->skip_bias_en)
++					    | VMAU_LMD_BIAS_EN(s->sse_lambda_bias_en)
++					    | VMAU_INFO_EN(s->info_en)
++					    | VMAU_DCM_EN(s->dcm_en)
++					    | VMAU_MVDS_ALL(s->mvd_sum_all)
++					    | VMAU_MVDS_ABS(s->mvd_sum_abs)
++					    | VMAU_MVS_ALL(s->mv_sum_all)
++					    | VMAU_MVS_ABS(s->mv_sum_abs)
++					    | VMAU_P_L0_BIAS(s->cost_bias_p_l0)
++					    | VMAU_PSKIP_BIAS(s->cost_bias_p_skip)
++					    | VMAU_I4_BIAS(s->cost_bias_i_4x4)
++					    | VMAU_I16_BIAS(s->cost_bias_i_16x16) ) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_MD_CFG2, 0, ( VMAU_IPM_BIAS_0(s->intra_lambda_bias_0)
++					    | VMAU_IPM_BIAS_1(s->intra_lambda_bias_1)
++					    | VMAU_IPM_BIAS_2(s->intra_lambda_bias_2)
++					    | VMAU_IPM_BIAS_QP0(s->intra_lambda_bias_qp0)
++					    | VMAU_IPM_BIAS_QP1(s->intra_lambda_bias_qp1)
++					    | VMAU_MD_FBC_EP(s->fbc_ep) ) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_MD_CFG3, 0, ( VMAU_CSSE_BIAS_0(s->chroma_sse_bias_0)
++					    | VMAU_CSSE_BIAS_1(s->chroma_sse_bias_1)
++					    | VMAU_CSSE_BIAS_2(s->chroma_sse_bias_2)
++					    | VMAU_CSSE_BIAS_QP0(s->chroma_sse_bias_qp0)
++					    | VMAU_CSSE_BIAS_QP1(s->chroma_sse_bias_qp1)
++					    | VMAU_LMD_BIAS(s->sse_lambda_bias)
++					    | VMAU_PL0_FS_DIS(s->p_skip_pl0f_dis)
++					    | VMAU_PT8_FS_DIS(s->p_skip_pt8f_dis)
++					    | VMAU_PL0_COST_MAX(s->p_l0_dis)
++					    | VMAU_PT8_COST_MAX(s->p_t8_dis)
++                                            ) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_MD_CFG4, 0, ( VMAU_YSSE_THR(s->ysse_thr)
++					    | VMAU_I8_BIAS(s->cost_bias_i_8x8)
++					    | VMAU_PT8_BIAS(s->cost_bias_p_t8)
++                                            ) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_MD_CFG5, 0, ( VMAU_CSSE_THR(s->csse_thr)
++					    | VMAU_CQP_OFFSET(s->cqp_offset)
++					    | VMAU_I4_COST_MAX(s->i_4x4_dis)
++					    | VMAU_I8_COST_MAX(s->i_8x8_dis)
++					    | VMAU_I16_COST_MAX(s->i_16x16_dis)
++                                            ) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_MD_CFG6, 0, ( VMAU_DCM_PARAM(s->dcm_param)
++                                            | VMAU_SDE_PRIOR(s->sde_prior)
++                                            | VMAU_DB_PRIOR(s->db_prior)
++                                            ) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_MD_CFG7, 0, ( VMAU_CFG_SIZE_X(s->cfg_size_x)
++					    | VMAU_CFG_SIZE_Y(s->cfg_size_y)
++					    | VMAU_CFG_IW_THR(s->cfg_iw_thr)
++                                            | VMAU_CFG_BASEQP(s->base_qp)
++                                            | VMAU_CFG_ALPHA(s->alpha_c0_offset)
++                                            | VMAU_PS_COST_MAX(s->p_skip_dis)
++                                            ) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_MD_CFG8, 0, ( VMAU_CFG_MVR_THR1(s->cfg_mvr_thr1)
++					    | VMAU_CFG_MVR_THR2(s->cfg_mvr_thr2) ) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_MD_CFG9, 0, ( VMAU_CFG_MVR_THR3(s->cfg_mvr_thr3)
++                                            | VMAU_CFG_BETA(s->beta_offset)
++                                            ) );
++
++  /* eigen leverages mode decision */
++  int set_modectrl_bit0 = s->mb_mode_use & 0x1;
++  int set_modectrl_bit2 = s->rrs_en || s->force_i16 || s->refresh_en;
++  GEN_VDMA_ACFG(chn, REG_VMAU_MD_CFG11, 0, ( VMAU_CFG_MD_RBIAS(s->refresh_bias)
++                                             | VMAU_CFG_MD_RBIAS_EN(1)
++                                             | VMAU_CFG_MD_PCDC_N0(s->mode_ctrl >> 3 & 7)
++                                             | VMAU_CFG_MD_IFA_VLD(set_modectrl_bit2)
++                                             | VMAU_CFG_MD_SLV_VLD(0)
++                                             | VMAU_CFG_MD_SET_VLD((s->mode_ctrl & 0x2) || set_modectrl_bit0)
++                                            ) );
++
++  GEN_VDMA_ACFG(chn, REG_VMAU_ACMASK, 0, (s->acmask_mode<<14) + 2 ); /* 2 for TEST: rd file */
++
++  for (j = 0; j < 40; ++j)
++    GEN_VDMA_ACFG(chn, REG_VMAU_MD_MODE, 0, s->mode_ctrl_param[j] );
++
++  for (j = 0; j < 42; j++)
++    GEN_VDMA_ACFG(chn, REG_VMAU_CTX, 0, s->state[ j<10 ? ( !s->frame_type ? j+3 : j+14 )
++						  : j<22 ? j-10+73
++						  : j<28 ? j-22+64 : j-28+40 ] );
++
++  for( j = 0; j < 225; j++)
++    GEN_VDMA_ACFG(chn, REG_VMAU_CTX_CFBC, 0, s->state[ j<4  ? j+85 :       //LUMA_DC_SIGNCG
++						       j<19 ? j-4+105 :    //LUMA_DC_SIGN
++						       j<34 ? j-19+166 :   //LUMA_DC_LAST
++						       j<44 ? j-34+227 :   //LUMA_DC_LEVEL
++						       j<48 ? j-44+89  :   //LUMA_AC_SIGNCG
++						       j<62 ? j-48+120 :   //LUMA_AC_SIGN
++						       j<76 ? j-62+181 :   //LUMA_AC_LAST
++						       j<86 ? j-76+237 :   //LUMA_AC_LEVEL
++						       j<90 ? j-86+93  :   //LUMA_44_SIGNCG
++						       j<105 ? j-90+134  :  //LUMA_44_SIGN
++						       j<120 ? j-105+195  : //LUMA_44_LAST
++						       j<130 ? j-120+247  : //LUMA_44_LEVEL
++						       j<134 ? j-130+97   : //CHROMA_DC_SIGNCG
++						       j<137 ? j-134+149  : //CHROMA_DC_SIGN
++						       j<140 ? j-137+210  : //CHROMA_DC_LAST
++						       j<149 ? j-140+257  : //CHROMA_DC_LEVEL
++						       j<153 ? j-149+101  : //CHROMA_AC_SIGNCG
++						       j<167 ? j-153+152  : //CHROMA_AC_SIGN
++						       j<181 ? j-167+213  : //CHROMA_AC_LAST
++						       j<191 ? j-181+266  : //CHROMA_AC_LEVEL
++						       j<206 ? j-191+402  : //LUMA_88_SIGN
++						       j<215 ? j-206+417  : //LUMA_88_LAST
++						       j-215+426            //LUMA_88_LEVEL
++						       ] );
++
++
++
++#if 0
++  for(j=0; j<4; j++){
++    for(i=0; i<4; i++){
++      GEN_VDMA_ACFG(chn, REG_VMAU_QT+tmp, 0, *(int *)(&s->scaling_list[j][i*4]) );
++      tmp += 4;
++    }
++  }
++  for(j=0; j<4; j++){
++    for (i=0; i<8; i++){
++      int tmp0 = (1ULL << 8) / s->scaling_list[j][2*i];
++      int tmp1 = (1ULL << 8) / s->scaling_list[j][2*i+1];
++      GEN_VDMA_ACFG(chn, REG_VMAU_QT+tmp, 0, ((tmp0 & 0xFFFF) | (tmp1<<16)) );
++      tmp += 4;
++    }
++  }
++#endif
++  GEN_VDMA_ACFG(chn, REG_VMAU_IPRED_CFG0, 0, (VMAU_IP_MD_VAL(s->force_i16dc) |
++					      VMAU_IP_REF_NEB_4(s->ref_neb_4) |
++					      VMAU_IP_REF_NEB_8(s->ref_neb_8) |
++					      VMAU_IP_REF_PRD_C(s->pri_uv) |
++					      VMAU_IP_REF_PRD_16(s->pri_16) |
++					      VMAU_IP_REF_PRD_8(s->pri_8) |
++					      VMAU_IP_REF_PRD_4(s->pri_4) |
++					      VMAU_IP_REF_C4_EN(s->c_4_en) |
++					      VMAU_IP_REF_C8_EN(s->c_8_en) |
++					      VMAU_IP_REF_C16_EN(s->c_16_en) |
++					      VMAU_IP_REF_CUV_EN(s->c_uv_en) |
++					      VMAU_IP_REF_LMD4_EN(s->lamb_4_en) |
++					      VMAU_IP_REF_LMD8_EN(s->lamb_8_en) |
++					      VMAU_IP_REF_LMD16_EN(s->lamb_16_en) |
++					      VMAU_IP_REF_LMDUV_EN(s->lamb_uv_en) |
++					      VMAU_IP_REF_BIT4_EN(s->bit_4_en) |
++					      VMAU_IP_REF_BIT8_EN(s->bit_8_en) |
++					      VMAU_IP_REF_BIT16_EN(s->bit_16_en) |
++					      VMAU_IP_REF_BITUV_EN(s->bit_uv_en) ) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_IPRED_CFG1, 0, (VMAU_IP_REF_4_BIT0(s->bit_4[0]) |
++					      VMAU_IP_REF_4_BIT1(s->bit_4[1]) |
++					      VMAU_IP_REF_4_BIT2(s->bit_4[2]) |
++					      VMAU_IP_REF_4_BIT3(s->bit_4[3]) |
++					      VMAU_IP_REF_8_BIT0(s->bit_8[0]) |
++					      VMAU_IP_REF_8_BIT1(s->bit_8[1]) |
++					      VMAU_IP_REF_8_BIT2(s->bit_8[2]) |
++					      VMAU_IP_REF_8_BIT3(s->bit_8[3]) ) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_IPRED_CFG2, 0, (VMAU_IP_REF_C_BIT0(s->bit_uv[0]) |
++					      VMAU_IP_REF_C_BIT1(s->bit_uv[1]) |
++					      VMAU_IP_REF_C_BIT2(s->bit_uv[2]) |
++					      VMAU_IP_REF_C_BIT3(s->bit_uv[3]) |
++					      VMAU_IP_REF_16_BIT0(s->bit_16[0]) |
++					      VMAU_IP_REF_16_BIT1(s->bit_16[1]) |
++					      VMAU_IP_REF_16_BIT2(s->bit_16[2]) |
++					      VMAU_IP_REF_16_BIT3(s->bit_16[3]) ) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_IPRED_CFG3, 0, (VMAU_IP_REF_LMDUV_IFO(s->lambda_infouv) |
++					      VMAU_IP_REF_LMD16_IFO(s->lambda_info16) |
++					      VMAU_IP_REF_LMD8_IFO(s->lambda_info8) |
++					      VMAU_IP_REF_LMD4_IFO(s->lambda_info4) |
++					      VMAU_IP_REF_NEB_4REF(s->ref_4) |
++					      VMAU_IP_REF_NEB_8REF(s->ref_8) ) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_IPRED_CFG4, 0, (VMAU_IP_REF_C4_IFO((s->const_4[0]<<0) |
++								 (s->const_4[1]<<4) |
++								 (s->const_4[2]<<8) |
++								 (s->const_4[3]<<12) ) |
++					      VMAU_IP_REF_C8_IFO((s->const_8[0]<<0) |
++								 (s->const_8[1]<<4) |
++								 (s->const_8[2]<<8) |
++								 (s->const_8[3]<<12) ) ) );
++  GEN_VDMA_ACFG(chn, REG_VMAU_IPRED_CFG5, 0, (VMAU_IP_REF_C16_IFO((s->const_16[0]<<0) |
++								  (s->const_16[1]<<4) |
++								  (s->const_16[2]<<8) |
++								  (s->const_16[3]<<12) ) |
++					      VMAU_IP_REF_CUV_IFO((s->const_uv[0]<<0) |
++								  (s->const_uv[1]<<4) |
++								  (s->const_uv[2]<<8) |
++								  (s->const_uv[3]<<12) ) ) );
++
++
++  if (1) { //configure scalinglist8
++    uint8_t scaling_list_z[2][64];
++    int kk, jj;
++    for (kk = 0; kk < 2; kk++) {
++      for (jj = 0; jj < 64; jj++) {
++	int jj_x = jj%8; //0 ~ 7
++	int jj_y = jj/8; //0 ~ 7
++	int jj_xx = jj_x%4; //0~3
++	int jj_xy = jj_x/4; //0~1
++	int jj_yx = jj_y%4; //0~3
++	int jj_yy = jj_y/4; //0~1
++	int zz = 16 * (jj_yy*2 + jj_xy) + 4*jj_yx + jj_xx;
++	scaling_list_z[kk][zz] = s->scaling_list8[kk][jj];
++      }
++    }
++    int ofst = 0 ;
++    for (kk = 0; kk < 2; kk++) {
++      for (jj = 0; jj < 32; jj++) {
++#ifdef __KERNEL__
++	unsigned long long t = 1ULL << 12;
++	do_div(t, scaling_list_z[kk][2*jj + 0]);
++	int t0 = (int)t;
++
++	t = 1ULL << 12;
++	do_div(t, scaling_list_z[kk][2*jj + 1]);
++	int t1 = (int)t;
++#else
++	int t0 = (1ULL << 12)/scaling_list_z[kk][2*jj+0];
++	int t1 = (1ULL << 12)/scaling_list_z[kk][2*jj+1];
++#endif
++	int tt = ((t0 & 0xfff) |
++		  (t1 & 0xfff) << 12);
++	GEN_VDMA_ACFG(chn, (VPU_BASE | 0x80800) + ofst, 0, tt );
++
++	ofst += 4;
++      }
++    }
++    for (kk = 0; kk < 2; kk++) {
++      for (jj = 0; jj < 16; jj++) {
++	int t0 = scaling_list_z[kk][4*jj+0];
++	int t1 = scaling_list_z[kk][4*jj+1];
++	int t2 = scaling_list_z[kk][4*jj+2];
++	int t3 = scaling_list_z[kk][4*jj+3];
++	int tt = ((t0 & 0x3f) |
++		  (t1 & 0x3f) << 6 |
++		  (t2 & 0x3f) << 12 |
++		  (t3 & 0x3f) << 18);
++	GEN_VDMA_ACFG(chn, (VPU_BASE | 0x80800) + ofst, 0, tt );
++	ofst += 4;
++      }
++    }
++  }
++
++  GEN_VDMA_ACFG(chn, REG_VMAU_GBL_RUN, 0, VMAU_RUN );
++
++  /**************************************************
++   DBLK configuration
++   *************************************************/
++#if 0
++  GEN_VDMA_ACFG(chn, REG_DBLK_TRIG, 0, DBLK_RESET);
++  GEN_VDMA_ACFG(chn, REG_DBLK_DHA, 0, VRAM_DBLK_CHN_BASE);
++  GEN_VDMA_ACFG(chn, REG_DBLK_GENDA, 0, VRAM_DBLK_CHN_SYNA);
++  GEN_VDMA_ACFG(chn, REG_DBLK_GSIZE, 0, DBLK_GSIZE(MB_HEI, MB_WID) );
++  GEN_VDMA_ACFG(chn, REG_DBLK_GPOS, 0, DBLK_GPOS(s->first_mby, 0) );
++  GEN_VDMA_ACFG(chn, REG_DBLK_CTRL, 0, DBLK_CTRL(0, s->rotate, s->deblock) );
++  GEN_VDMA_ACFG(chn, REG_DBLK_GPIC_YA, 0, s->fb[0][0]/* - (MB_WID+3)*256*/);
++  GEN_VDMA_ACFG(chn, REG_DBLK_GPIC_CA, 0, s->fb[0][1]/* - (MB_WID+3)*128*/);
++  GEN_VDMA_ACFG(chn, REG_DBLK_GP_ENDA, 0, VRAM_DBLK_DOUT_SYNA);
++  GEN_VDMA_ACFG(chn, REG_DBLK_GPIC_STR, 0, DBLK_GPIC_STR(MB_WID*128, MB_WID*256) );
++  GEN_VDMA_ACFG(chn, REG_DBLK_VTR, 0, DBLK_VTR(s->beta_offset, s->alpha_c0_offset, 0, 0,
++					       s->frame_type, DBLK_FMT_H264) );
++  GEN_VDMA_ACFG(chn, REG_DBLK_TRIG, 0, DBLK_SLICE_RUN);
++  //mosaic
++  GEN_VDMA_ACFG(chn, REG_DBLK_MOS_CFG, 0, ( ((s->mos_sthd[1] & 0xF) << 28) |
++					    ((s->mos_sthd[0] & 0xF) << 24) |
++					    ((s->mos_gthd[1] & 0xFF) << 16) |
++					    ((s->mos_gthd[0] & 0xFF) << 8)  |
++					    (s->mosaic_en & 0x1) ) );
++  GEN_VDMA_ACFG(chn, REG_DBLK_MOS_ADDR, 0, DBLK_MOS_BASE_ADDR);
++#else
++  GEN_VDMA_ACFG(chn, REG_DBLK_CFG, 0, ( DBLK_CFG_ALPHA(s->alpha_c0_offset + 12)
++                                        | DBLK_CFG_BETA(s->beta_offset + 12)
++                                        | DBLK_CFG_NO_LFT(!s->deblock) ) );
++  GEN_VDMA_ACFG(chn, REG_DBLK_TRIG, 0, DBLK_SLICE_RUN);
++#endif
++  /**************************************************
++   SDE configuration
++   *************************************************/
++  GEN_VDMA_ACFG(chn, REG_SDE_STAT, 0, 0);
++  GEN_VDMA_ACFG(chn, REG_SDE_GL_CTRL, 0, (SDE_MODE_STEP | SDE_EN) );
++  GEN_VDMA_ACFG(chn, REG_SDE_SL_GEOM, 0, SDE_SL_GEOM(MB_HEI, MB_WID,
++						     s->first_mby, 0) );
++  GEN_VDMA_ACFG(chn, REG_SDE_CODEC_ID, 0, SDE_FMT_H264_ENC);
++  //slice_info0 {desp_link_en[1], auto_syn_en[0]}
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG0, 0, 0x3);
++  //slice_info1 {qp[8], slice_type[0]}
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG1, 0, ((s->qp << 8) |
++				       (s->bs_head_en << 20) |//rbsp enable
++				       (s->bs_rbsp_en << 7) |//rbsp enable
++				       (s->mref_en << 6) | /*dual-ref enable*/
++				       (s->dct8x8_en << 5) | /*dct8x8 enable*/
++				       (s->skip_en << 4) |
++				       (s->frame_type + 1)) );
++  //desp_addr
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG2, 0, VRAM_SDE_CHN_BASE);
++  //sync_addr
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG3, 0, VRAM_SDE_SYNA);
++  //bs_addr
++  GEN_VDMA_ACFG(chn, REG_SDE_CFG4, 0, s->bs);
++  //context table
++  for(i=0; i<460; i++){
++    int idx = s->state[i];
++    if(idx <= 63)
++      idx = 63 - idx;
++    else
++      idx -= 64;
++    GEN_VDMA_ACFG(chn, REG_SDE_CTX_TBL+i*4, 0,
++		  (lps_range[idx] | ((s->state[i]>>6) & 0x1)) );
++  }
++  //init sync
++  GEN_VDMA_ACFG(chn, REG_SDE_SL_CTRL, 0, SDE_SLICE_INIT);
++  /**************************************************
++   EMC init
++   *************************************************/
++  char use_ddr_slow_mode=0;
++  if((((s->frame_width+15)/16)-1)>32)
++    use_ddr_slow_mode = 0;
++  else
++    use_ddr_slow_mode = 1;
++
++  GEN_VDMA_ACFG(chn, REG_EMC_FRM_SIZE, 0,
++		(0x0) << 20 | //bs_full intc before slice end
++		(s->bs_size_en) << 19 | //bs space ctrl by bs_size
++		use_ddr_slow_mode << 18 | //ddr use slow mode
++		(s->qp_tab_en & 0x1) << 17 | //qp table en
++		//(s->i_4x4_dis & 0x1) << 16 | //4x4 close
++		(((s->frame_height+15)/16)-1) << 8 |
++		(((s->frame_width+15)/16)-1) );
++  GEN_VDMA_ACFG(chn, REG_EMC_BS_ADDR, 0, VDMA_ACFG_DHA(s->emc_bs_pa));
++  GEN_VDMA_ACFG(chn, REG_EMC_DBLK_ADDR, 0, VDMA_ACFG_DHA(s->emc_dblk_pa));
++  GEN_VDMA_ACFG(chn, REG_EMC_RECON_ADDR, 0, VDMA_ACFG_DHA(s->emc_recon_pa));
++  GEN_VDMA_ACFG(chn, REG_EMC_MV_ADDR, 0, VDMA_ACFG_DHA(s->emc_mv_pa));
++  GEN_VDMA_ACFG(chn, REG_EMC_SE_ADDR, 0, VDMA_ACFG_DHA(s->emc_se_pa));
++  
++
++  if((s->rc_mb_en & 0x1) && s->frame_type){//mb_rc+bu_rc or only mb_rc
++    for(i=0;i<s->mb_gp_num;i++){
++
++      int mb_gp_wth = (s->mb_width + 1) / 2;
++      int mb_gp_wth_for_bu = mb_gp_wth << (s->rc_bu_level - 1);
++      uint32_t r_idx = i;
++      uint32_t bdry_2algn = (s->mb_width % 2) == 0;
++      uint32_t mb_rinfo0_valid = 1;
++      uint32_t mb_rinfo1_valid = !bdry_2algn && ((r_idx % mb_gp_wth) == (mb_gp_wth-1)) ? 0 : 1;
++      uint32_t bu_rinfo_valid = (r_idx % mb_gp_wth_for_bu) == (mb_gp_wth_for_bu-1) ? 1 : 0;
++      uint32_t bu_rinfo_idx = r_idx / mb_gp_wth_for_bu;
++      uint32_t bdry_n2algn_num;
++      if(bdry_2algn)
++	bdry_n2algn_num = 0;
++      else
++	bdry_n2algn_num = r_idx / ((s->mb_width+1)/2);
++
++      uint32_t mb_ref_info0 = s->mb_ref_info[r_idx*2 - bdry_n2algn_num] & 0x7fff;
++      uint32_t mb_ref_info1 = s->mb_ref_info[r_idx*2+1 - bdry_n2algn_num] & 0x7fff;
++      uint32_t mb_rinfo0 = (mb_rinfo0_valid<<15) | mb_ref_info0;
++      uint32_t mb_rinfo1 = (mb_rinfo1_valid<<31) | (mb_ref_info1<<16);
++      uint32_t bu_rinfo = (bu_rinfo_valid<<31) | (s->bu_ref_info[bu_rinfo_idx] & 0x7fffffff);
++      //fprintf(stderr,"i:%d,mb_ref_info0:0x%x,mb_ref_info1:0x%x,s->bu_ref_info:0x%x\n",i,mb_ref_info0,mb_ref_info1,s->bu_ref_info[bu_rinfo_idx] & 0x7fffffff);
++      //fprintf(stderr,"s->mb_width:%d, mb_gp_wth:%d, s->rc_bu_level:%d, mb_gp_wth_for_bu:%d, r_idx:%d\n",s->mb_width, mb_gp_wth, s->rc_bu_level, mb_gp_wth_for_bu, r_idx);
++      //fprintf(stderr,"mb_rinfo0:0x%x,mb_rinfo1:0x%x,bu_rinfo:0x%x\n",mb_rinfo0,mb_rinfo1,bu_rinfo);
++      s->emc_rc_va[i*2] = mb_rinfo1 | mb_rinfo0;
++      s->emc_rc_va[i*2+1] = bu_rinfo;
++      //fprintf(stderr,"s->emc_rc_va[%d]:0x%x,s->emc_rc_va[%d]:0x%x\n",i*2,s->emc_rc_va[i*2],i*2+1,s->emc_rc_va[i*2+1]);
++    }
++    GEN_VDMA_ACFG(chn, REG_EMC_RC_RADDR, 0, VDMA_ACFG_DHA(s->emc_rc_pa));
++  }else if((s->rc_mb_en & 0x2) && s->frame_type){//only bu_rc
++    for(i=0;i<s->rc_bu_num;i++){
++      uint32_t bu_rinfo = (1<<31) | (s->bu_ref_info[i] & 0x7fffffff);
++      s->emc_rc_va[i*2+1] = bu_rinfo;
++    }
++    GEN_VDMA_ACFG(chn, REG_EMC_RC_RADDR, 0, VDMA_ACFG_DHA(s->emc_rc_pa));
++  }
++  if(s->rc_mb_en)
++    GEN_VDMA_ACFG(chn, REG_EMC_RC_WADDR, 0, VDMA_ACFG_DHA(s->emc_rc_pa));
++
++  if(s->qp_tab_en){
++    for(i=0;i<s->qp_tab_len;i++)
++      s->emc_qpt_va[i] = s->qp_tab[i];
++  }
++  if(s->ncu_mov_en){
++    for(i=0;i<s->ncu_move_len;i++)
++      s->emc_ncu_va[i] = s->ncu_move_info[i];
++  }
++
++  if(s->mb_mode_use){
++    int mb_mode_len = (s->mb_width * s->mb_height + 1) / 2;
++    for(i=0;i<mb_mode_len;i++)
++      s->emc_mod_va[i] = s->mb_mode_info[i];
++  }
++
++
++  //rintf(stderr,"s->emc_qpt_va[0]=%x\n",s->emc_qpt_va[0]);
++  //rintf(stderr,"s->emc_qpt_va[1]=%x\n",s->emc_qpt_va[1]);
++  //rintf(stderr,"s->emc_qpt_va[2]=%x\n",s->emc_qpt_va[2]);
++  GEN_VDMA_ACFG(chn, REG_EMC_QPT_ADDR, 0, VDMA_ACFG_DHA(s->emc_qpt_pa));
++  GEN_VDMA_ACFG(chn, REG_EMC_CPX_ADDR, 0, VDMA_ACFG_DHA(s->emc_cpx_pa));
++  GEN_VDMA_ACFG(chn, REG_EMC_MOD_ADDR, 0, VDMA_ACFG_DHA(s->emc_mod_pa));
++  GEN_VDMA_ACFG(chn, REG_EMC_NCU_ADDR, 0, VDMA_ACFG_DHA(s->emc_ncu_pa));
++  GEN_VDMA_ACFG(chn, REG_EMC_SAD_ADDR, 0, VDMA_ACFG_DHA(s->emc_sad_pa));
++  GEN_VDMA_ACFG(chn, REG_EMC_BS_SIZE, 0, s->bs_size);
++  GEN_VDMA_ACFG(chn, REG_EMC_SLV_INIT, 0, 0x1);
++  /**************************************************
++   TOPMV/TOPPA init
++   *************************************************/
++/*   for(i=0; i<256; i++){ */
++/*     write_reg(VRAM_TOPMV_BA+i*4, 0); */
++/*     write_reg(VRAM_TOPPA_BA+i*4, 0); */
++/*   } */
++
++  /**************************************************
++   SCH configuration
++   *************************************************/
++  GEN_VDMA_ACFG(chn, REG_SCH_SCHC, 0, 0);
++  GEN_VDMA_ACFG(chn, REG_SCH_BND, 0, 0);
++  GEN_VDMA_ACFG(chn, REG_SCH_SCHG0, 0, 0);
++  GEN_VDMA_ACFG(chn, REG_SCH_SCHG1, 0, 0);
++  GEN_VDMA_ACFG(chn, REG_SCH_SCHE1, 0, 0);
++  GEN_VDMA_ACFG(chn, REG_SCH_SCHE2, 0, 0);
++  GEN_VDMA_ACFG(chn, REG_SCH_SCHE3, 0, 0);
++  GEN_VDMA_ACFG(chn, REG_SCH_SCHE4, 0, 0);
++
++#if 1
++  GEN_VDMA_ACFG(chn, REG_SCH_SCHC, 0, (SCH_CH4_GS1 | SCH_CH4_PCH(0) |
++				       SCH_CH3_GS1 | SCH_CH3_PCH(0) |
++				       SCH_CH2_GS0 | SCH_CH2_PE | SCH_CH2_PCH(0) |
++				       SCH_CH1_GS0 | SCH_CH1_PCH(0) |
++				       (s->frame_type & 0x1)<<2 ) );
++
++  GEN_VDMA_ACFG(chn, REG_SCH_BND, 0, (SCH_CH4_HID(HID_SDE) | SCH_CH3_HID(HID_DBLK) |
++				      SCH_CH2_HID(HID_VMAU) | SCH_CH1_HID(HID_MCE) |
++				      SCH_DEPTH(SCH_FIFO_DEPTH) |
++				      SCH_BND_G0F2 |
++				      (s->frame_type & 0x1)<<0 ) );
++#else
++  GEN_VDMA_ACFG(chn, REG_SCH_SCHC, 0, (SCH_CH4_GS1 | SCH_CH4_PE | SCH_CH4_PCH(0) |
++				       SCH_CH3_GS1 | SCH_CH3_PE | SCH_CH3_PCH(0) |
++				       SCH_CH2_GS0 | SCH_CH2_PE | SCH_CH2_PCH(0) |
++				       SCH_CH1_GS0 | SCH_CH1_PCH(0) |
++				       (s->frame_type & 0x1)<<2 ) );
++
++  GEN_VDMA_ACFG(chn, REG_SCH_BND, 0, (SCH_CH4_HID(HID_SDE) | SCH_CH3_HID(HID_DBLK) |
++				      SCH_CH2_HID(HID_VMAU) | SCH_CH1_HID(HID_MCE) |
++				      SCH_DEPTH(SCH_FIFO_DEPTH) |
++				      SCH_BND_G1F4 | SCH_BND_G1F3 |
++				      SCH_BND_G0F4 | SCH_BND_G0F3 | SCH_BND_G0F2 |
++				      (s->frame_type & 0x1)<<0 ) );
++#endif
++
++  /**************************************************
++   ODMA configuration
++   *************************************************/
++  //when buf share is new addr(dynamic), else old addr(static)
++  paddr_t odma_y_addr = s->buf_share_en ? buf_start_yaddr : s->fb[0][0];
++  paddr_t odma_c_addr = s->buf_share_en ? buf_start_caddr : s->fb[0][1];
++  //when buf share is base addr, else head addr
++  paddr_t odma_com_addr0  = s->buf_share_en ? s->fb[0][0] : s->jh[0][0];
++  paddr_t odma_com_addr1  = s->buf_share_en ? s->fb[0][1] : s->jh[0][1];
++  //when buf share is beyond addr, else head spe addr
++  paddr_t odma_com_addr2  = s->buf_share_en ? buf_beyond_yaddr : s->spe_y_addr;
++  paddr_t odma_com_addr3  = s->buf_share_en ? buf_beyond_caddr : s->spe_c_addr;
++
++  GEN_VDMA_ACFG(chn, REG_ODMA_CTRL, 0, (odma_spe_flag << 31 |
++					(s->buf_share_en << 30) |//buf share
++					(odma_alg_flag << 29) |
++					(s->jrfc_enable  << 28) |//compress_flag
++					(s->frame_height << 14) |
++					s->frame_width));
++
++  GEN_VDMA_ACFG(chn, REG_ODMA_BDYA, 0, odma_y_addr);
++  GEN_VDMA_ACFG(chn, REG_ODMA_BDCA, 0, odma_c_addr);
++
++  GEN_VDMA_ACFG(chn, REG_ODMA_BSTR, 0,
++		ODMA_REC_STRDY(((s->frame_width+15)/16)*16) |
++		ODMA_REC_STRDC(((s->frame_width+15)/16)*8) );
++
++
++  GEN_VDMA_ACFG(chn, REG_ODMA_HDYA, 0, odma_com_addr0);
++  GEN_VDMA_ACFG(chn, REG_ODMA_HDCA, 0, odma_com_addr1);
++  GEN_VDMA_ACFG(chn, REG_ODMA_SPYA, 0, odma_com_addr2);
++  GEN_VDMA_ACFG(chn, REG_ODMA_SPCA, 0, odma_com_addr3);
++
++
++  GEN_VDMA_ACFG(chn, REG_ODMA_TRIG, 0,
++		((0 << 6) |  //0 is crc en
++		 (1 << 5) | //init
++		 (0 << 4)  //ckg low means do clock-gating
++		 ));
++
++
++  /**************************************************
++   IFA configuration
++   *************************************************/
++
++  GEN_VDMA_ACFG(chn, REG_IFA_FRM_SIZE, 0, (IFA_FRM_W(s->frame_width-1)  |
++					   IFA_FRM_H(s->frame_height-1) ) );
++  GEN_VDMA_ACFG(chn, REG_IFA_RAWY_BA, 0,  s->raw[0]);
++  GEN_VDMA_ACFG(chn, REG_IFA_RAWC_BA, 0,  s->raw[1]);
++  if(s->buf_share_en){
++    GEN_VDMA_ACFG(chn, REG_IFA_REFY_BA0, 0,  refy_addr_ba0);
++    GEN_VDMA_ACFG(chn, REG_IFA_REFC_BA0, 0,  refc_addr_ba0);
++    GEN_VDMA_ACFG(chn, REG_IFA_REFY_BA1, 0,  refy_addr_ba1);
++    GEN_VDMA_ACFG(chn, REG_IFA_REFC_BA1, 0,  refc_addr_ba1);
++  }
++  else {
++    GEN_VDMA_ACFG(chn, REG_IFA_REFY_BA0, 0,  s->fb[1][0]);
++    GEN_VDMA_ACFG(chn, REG_IFA_REFC_BA0, 0,  s->fb[1][1]);
++    GEN_VDMA_ACFG(chn, REG_IFA_REFY_BA1, 0,  s->fb[3][0]);
++    GEN_VDMA_ACFG(chn, REG_IFA_REFC_BA1, 0,  s->fb[3][1]);
++  }
++
++  GEN_VDMA_ACFG(chn, REG_IFA_RAW_STR, 0,  (IFA_STR_Y(s->stride[0]) |
++					   IFA_STR_C(s->stride[1]) ) );
++  GEN_VDMA_ACFG(chn, REG_IFA_THRD_Y, 0,  s->rrs_thrd_y);
++  GEN_VDMA_ACFG(chn, REG_IFA_THRD_C, 0,  (IFA_THRD_U(s->rrs_thrd_u) |
++					  IFA_THRD_V(s->rrs_thrd_v) ) );
++  GEN_VDMA_ACFG(chn, REG_IFA_CTRL, 0, (IFA_CTRL_RAW_TYPE(s->raw_format == EFE_PLANE_NV12) |
++				       IFA_CTRL_REF_BIDX(ref_mby_size) |
++				       IFA_CTRL_RRS_EN(s->rrs_en)       |
++				       IFA_CTRL_DUMP_EN(s->rrs_dump_en) |
++				       IFA_CTRL_DDR_DW(!s->jrfd_enable) |
++				       IFA_CTRL_RRS_SC(s->rrs_size_c)   |
++				       IFA_CTRL_RRS_SY(s->rrs_size_y)   |
++				       IFA_CTRL_UV_EN(s->rrs_uv_en)     |
++				       IFA_CTRL_INIT ) );
++  
++  //sde slice header
++  if(s->bs_head_en){
++    //printf("bs_head_rest\n");
++    GEN_VDMA_ACFG(chn, REG_SDE_CFG5, 0, 0x1);
++    //slice header lenth
++    //printf("s->bs_head_len=0x%x\n",s->bs_head_len-1);
++    GEN_VDMA_ACFG(chn, REG_SDE_CFG6, 0, s->bs_head_len-1);
++    for(i=0; i<(s->bs_head_len+3)/4; i++){
++      //printf("s->bs_head_va[%x]=%x\n",i,s->bs_head_va[i]);
++      GEN_VDMA_ACFG(chn, REG_SDE_CFG7, 0, s->bs_head_va[i]);
++    }
++    //printf("bs_head_work\n");
++    GEN_VDMA_ACFG(chn, REG_SDE_CFG5, 0, 0x2);
++  }
++  //efe start
++  uint8_t align8_flag = (s->frame_height & 0xF) != 0;
++
++  GEN_VDMA_ACFG(chn, REG_EFE_CTRL, VDMA_ACFG_TERM, (EFE_TSE(s->use_intra_in_pframe) |
++						    EFE_FMVP(s->use_fast_mvp) |
++						    (0/*s->size_mode*/ << 29) |
++						    s->raw_format |
++						    EFE_X264_QP(s->qp) |
++						    EFE_HALN8_FLAG(align8_flag) |
++						    EFE_STEP_MODE(s->step_mode) |
++						    EFE_DBLK_EN |
++						    EFE_SLICE_TYPE(s->frame_type) |
++						    EFE_EN | EFE_RUN) );
++}
++
++#ifndef __KERNEL__
++#define printk printf
++#endif
++
++void H264E_DumpInfo(_H264E_SliceInfo *s)
++{
++    printk(" emc_qpt_va              : %p\n",s->emc_qpt_va);
++    printk(" emc_rc_va               : %p\n",s->emc_rc_va);
++    printk(" emc_cpx_va              : %p\n",s->emc_cpx_va);
++    printk(" emc_mod_va              : %p\n",s->emc_mod_va);
++    printk(" emc_ncu_va              : %p\n",s->emc_ncu_va);
++    printk(" emc_sad_va              : %p\n",s->emc_sad_va);
++    printk(" mb_mode_info            : %p\n",s->mb_mode_info);
++
++    printk("s->des_va   = 0x%08x\n", (unsigned int)s->des_va);
++    printk("s->des_pa   = 0x%08x\n", (unsigned int)s->des_pa);
++    //	printk("s->emc_bs_va = 0x%08x\n", s->emc_bs_va);
++    printk("s->emc_bs_pa = 0x%08x\n", s->emc_bs_pa);
++
++    /*x2000 add*/
++    printk(" bs_head_en = %d\n", s->bs_head_en);
++    printk(" bs_head_va = 0x%08x\n", (unsigned int)s->bs_head_va);
++    printk(" bs_head_len = 0x%d\n", (unsigned int)s->bs_head_len);
++    printk(" bs_rbsp_en = %d\n", s->bs_rbsp_en);
++
++    printk(" stride[0]    = %d\n", s->stride[0]);
++    printk(" stride[1]    = %d\n", s->stride[1]);
++    printk(" state	= 0x%08x\n", (unsigned int)s->state);
++    printk(" raw[0]   = 0x%08x\n", s->raw[0]);
++    printk(" raw[1]   = 0x%08x\n", s->raw[1]);
++    printk(" raw[2]   = 0x%08x\n", s->raw[2]);
++    printk(" fb[0][0] = 0x%08x\n", s->fb[0][0]);
++    printk(" fb[0][1] = 0x%08x\n", s->fb[0][1]);
++    printk(" fb[1][0] = 0x%08x\n", s->fb[1][0]);
++    printk(" fb[1][1] = 0x%08x\n", s->fb[1][1]);
++    printk(" fb[2][0] = 0x%08x\n", s->fb[2][0]);
++    printk(" fb[2][1] = 0x%08x\n", s->fb[2][1]);
++    printk(" jh[0][0] = 0x%08x\n", s->jh[0][0]);
++    printk(" jh[0][1] = 0x%08x\n", s->jh[0][1]);
++    printk(" jh[1][0] = 0x%08x\n", s->jh[1][0]);
++    printk(" jh[1][1] = 0x%08x\n", s->jh[1][1]);
++    printk(" jh[2][0] = 0x%08x\n", s->jh[2][0]);
++    printk(" jh[2][1] = 0x%08x\n", s->jh[2][1]);
++    printk(" spe_y_addr = 0x%08x\n", s->spe_y_addr);
++    printk(" spe_c_addr = 0x%08x\n", s->spe_c_addr);
++    printk(" emc_recon_pa= 0x%08x\n", s->emc_recon_pa);
++    printk(" emc_qpt_pa  = 0x%08x\n", s->emc_qpt_pa);
++    printk(" emc_mv_pa   = 0x%08x\n", s->emc_mv_pa);
++    printk(" emc_se_pa   = 0x%08x\n", s->emc_se_pa);
++    printk(" emc_rc_pa   = 0x%08x\n", s->emc_rc_pa);
++    printk(" emc_cpx_pa  = 0x%08x\n", s->emc_cpx_pa);
++    printk(" emc_mod_pa  = 0x%08x\n", s->emc_mod_pa);
++    printk(" emc_ncu_pa  = 0x%08x\n", s->emc_ncu_pa);
++    printk(" emc_sad_pa  = 0x%08x\n", s->emc_sad_pa);
++    /* 1. rc output [11]*/
++    {
++        printk(" frame_type              : %d\n",s->frame_type);
++        printk(" mb_width                : %d\n",s->mb_width);
++        printk(" mb_height               : %d\n",s->mb_height);
++        printk(" frame_width             : %d\n",s->frame_width);
++        printk(" frame_height            : %d\n",s->frame_height);
++        printk(" first_mby               : %d\n",s->first_mby);
++        printk(" last_mby                : %d\n",s->last_mby);
++        printk(" qp                      : %d\n",s->qp);
++        printk(" base_qp                 : %d\n",s->base_qp);
++        printk(" max_qp                  : %d\n",s->max_qp);
++        printk(" min_qp                  : %d\n",s->min_qp);
++    }
++    /* 2. motion cfg [25]*/
++    {
++        printk(" frm_re[0]              : %d\n",s->frm_re[0]);
++        printk(" frm_re[1]              : %d\n",s->frm_re[1]);
++        printk(" frm_re[2]              : %d\n",s->frm_re[2]);
++        printk(" frm_re[3]              : %d\n",s->frm_re[3]);
++        printk(" pskip_en               : %d\n",s->pskip_en);
++        printk(" mref_en                : %d\n",s->mref_en);
++        printk(" scl                    : %d\n",s->scl);
++        printk(" hpel_en                : %d\n",s->hpel_en);
++        printk(" qpel_en                : %d\n",s->qpel_en);
++        printk(" ref_mode               : %d\n",s->ref_mode);
++        printk(" max_sech_step_i        : %d\n",s->max_sech_step_i);
++        printk(" max_mvrx_i             : %d\n",s->max_mvrx_i);
++        printk(" max_mvry_i             : %d\n",s->max_mvry_i);
++        printk(" lambda_scale_parameter : %d\n",s->lambda_scale_parameter);
++        printk(" fs_en                  : %d\n",s->fs_en);
++        printk(" fs_md                  : %d\n",s->fs_md);
++        printk(" fs_px                  : %d\n",s->fs_px);
++        printk(" fs_py                  : %d\n",s->fs_py);
++        printk(" fs_rx                  : %d\n",s->fs_rx);
++        printk(" fs_ry                  : %d\n",s->fs_ry);
++        printk(" frm_mv_en              : %d\n",s->frm_mv_en);
++        printk(" frm_mv_size            : %d\n",s->frm_mv_size);
++        printk(" glb_mv_en              : %d\n",s->glb_mv_en);
++        printk(" glb_mvx                : %d\n",s->glb_mvx);
++        printk(" glb_mvy                : %d\n",s->glb_mvy);
++        printk(" me_step_en             : %d\n",s->me_step_en);
++        printk(" me_step_0              : %d\n",s->me_step_0);
++        printk(" me_step_1              : %d\n",s->me_step_1);
++    }
++    /* 3. quant cfg [4]*/
++    {
++        int i=0,j=0;
++        printk(" dct8x8_en    : %d\n",s->dct8x8_en);
++        for (i=0;i<4;i++)
++            for (j=0;j<16;j++)
++                printk(" scaling_list[%d][%d] : %d\n",i,j,s->scaling_list[i][j]);
++        for (i=0;i<2;i++)
++            for (j=0;j<64;j++)
++                printk(" scaling_list8[%d][%d] : %d\n",i,j,s->scaling_list8[i][j]);
++        for (i=0;i<9;i++)
++            printk(" deadzone[%d] : %d\n",i,s->deadzone[i]);
++    }
++
++    /* 4. loop filter cfg [4]*/
++    {
++        printk(" deblock                : %d\n",s->deblock);
++        printk(" rotate                 : %d\n",s->rotate);
++        printk(" alpha_c0_offset        : %d\n",s->alpha_c0_offset);
++        printk(" beta_offset            : %d\n",s->beta_offset);
++    }
++    /* 5. do not douch, default value [56]*/
++    {
++        printk(" acmask_mode : %d\n",s->acmask_mode);
++        printk(" intra_mode_msk : %d\n",s->intra_mode_msk);
++        printk(" i_4x4_dis              : %d\n",s->i_4x4_dis);
++        printk(" i_8x8_dis              : %d\n",s->i_8x8_dis);
++        printk(" i_16x16_dis            : %d\n",s->i_16x16_dis);
++        printk(" p_l0_dis               : %d\n",s->p_l0_dis);
++        printk(" p_t8_dis               : %d\n",s->p_t8_dis);
++        printk(" p_skip_dis             : %d\n",s->p_skip_dis);
++        printk(" p_skip_pl0f_dis        : %d\n",s->p_skip_pl0f_dis);
++        printk(" p_skip_pt8f_dis        : %d\n",s->p_skip_pt8f_dis);
++
++        printk(" cost_bias_en           : %d\n",s->cost_bias_en);
++        printk(" cost_bias_i_4x4        : %d\n",s->cost_bias_i_4x4);
++        printk(" cost_bias_i_8x8        : %d\n",s->cost_bias_i_8x8);
++        printk(" cost_bias_i_16x16      : %d\n",s->cost_bias_i_16x16);
++        printk(" cost_bias_p_l0         : %d\n",s->cost_bias_p_l0);
++        printk(" cost_bias_p_t8         : %d\n",s->cost_bias_p_t8);
++        printk(" cost_bias_p_skip       : %d\n",s->cost_bias_p_skip);
++
++        printk(" intra_lambda_y_bias_en : %d\n",s->intra_lambda_y_bias_en);
++        printk(" intra_lambda_c_bias_en : %d\n",s->intra_lambda_c_bias_en);
++        printk(" intra_lambda_bias_qp0  : %d\n",s->intra_lambda_bias_qp0);
++        printk(" intra_lambda_bias_qp1  : %d\n",s->intra_lambda_bias_qp1);
++        printk(" intra_lambda_bias_0    : %d\n",s->intra_lambda_bias_0);
++        printk(" intra_lambda_bias_1    : %d\n",s->intra_lambda_bias_1);
++        printk(" intra_lambda_bias_2    : %d\n",s->intra_lambda_bias_2);
++
++        printk(" chroma_sse_bias_en     : %d\n",s->chroma_sse_bias_en);
++        printk(" chroma_sse_bias_qp0    : %d\n",s->chroma_sse_bias_qp0);
++        printk(" chroma_sse_bias_qp1    : %d\n",s->chroma_sse_bias_qp1);
++        printk(" chroma_sse_bias_0      : %d\n",s->chroma_sse_bias_0);
++        printk(" chroma_sse_bias_1      : %d\n",s->chroma_sse_bias_1);
++        printk(" chroma_sse_bias_2      : %d\n",s->chroma_sse_bias_2);
++
++        printk(" sse_lambda_bias_en     : %d\n",s->sse_lambda_bias_en);
++        printk(" sse_lambda_bias        : %d\n",s->sse_lambda_bias);
++        printk(" fbc_ep                 : %d\n",s->fbc_ep);
++        printk(" jm_lambda2_en          : %d\n",s->jm_lambda2_en);
++        printk(" inter_nei_en           : %d\n",s->inter_nei_en);
++        printk(" skip_bias_en           : %d\n",s->skip_bias_en);
++
++        printk(" ysse_thr               : %d\n",s->ysse_thr);
++        printk(" csse_thr               : %d\n",s->csse_thr);
++        printk(" dcm_en                 : %d\n",s->dcm_en);
++        printk(" dcm_param              : %d\n",s->dcm_param);
++        printk(" sde_prior              : %d\n",s->sde_prior);
++        printk(" db_prior               : %d\n",s->db_prior);
++
++        printk(" use_intra_in_pframe    : %d\n",s->use_intra_in_pframe);
++        printk(" use_fast_mvp           : %d\n",s->use_fast_mvp);
++        printk(" skip_en                : %d\n",s->skip_en);
++        printk(" cqp_offset             : %d\n",s->cqp_offset);
++
++        printk(" daisy_chain_en         : %d\n",s->daisy_chain_en);
++        printk(" curr_thread_id         : %d\n",s->curr_thread_id);
++        printk(" qp_tab_mode            : %d\n",s->qp_tab_mode);
++        printk(" bs_size_en             : %d\n",s-> bs_size_en);
++        printk(" bs_size                : %d\n",s->bs_size);
++        printk(" raw_format             : %d\n",s->raw_format);
++
++        printk(" size_mode              : %d\n",s->size_mode);
++        printk(" step_mode              : %d\n",s->step_mode);
++        printk(" mode_ctrl              : %d\n",s->mode_ctrl);
++        int i=0;
++        for (i=0;i<40;i++)
++            printk("mode_ctrl_param[%d] : %d\n",i,s->mode_ctrl_param[i]);
++
++    }
++    /* 6. select hardware output mode [11]*/
++    {
++        printk(" info_en                : %d\n",s->info_en);
++        printk(" mvd_sum_all            : %d\n",s->mvd_sum_all);
++        printk(" mvd_sum_abs            : %d\n",s->mvd_sum_abs);
++        printk(" mv_sum_all             : %d\n",s->mv_sum_all);
++        printk(" mv_sum_abs             : %d\n",s->mv_sum_abs);
++
++
++        printk(" cfg_size_x             : %d\n",s->cfg_size_x);
++        printk(" cfg_size_y             : %d\n",s->cfg_size_y);
++        printk(" cfg_iw_thr             : %d\n",s->cfg_iw_thr);
++
++        printk(" cfg_mvr_thr1           : %d\n",s->cfg_mvr_thr1);
++        printk(" cfg_mvr_thr2           : %d\n",s->cfg_mvr_thr2);
++        printk(" cfg_mvr_thr3           : %d\n",s->cfg_mvr_thr3);
++    }
++    /* 7. ipred bit&lambda ctrl [33]*/
++    {
++        printk(" mb_mode_val            : %d\n",s->mb_mode_val);
++        printk(" bit_16_en              : %d\n",s->bit_16_en);
++        printk(" bit_8_en               : %d\n",s->bit_8_en);
++        printk(" bit_4_en               : %d\n",s->bit_4_en);
++        printk(" bit_uv_en              : %d\n",s->bit_uv_en);
++        printk(" lamb_16_en             : %d\n",s->lamb_16_en);
++        printk(" lamb_8_en              : %d\n",s->lamb_8_en);
++        printk(" lamb_4_en              : %d\n",s->lamb_4_en);
++        printk(" lamb_uv_en             : %d\n",s->lamb_uv_en);
++        printk(" lamb_uv_en             : %d\n",s->c_16_en);
++        printk(" c_8_en                 : %d\n",s->c_8_en);
++        printk(" c_4_en                 : %d\n",s->c_4_en);
++        printk(" c_uv_en                : %d\n",s->c_uv_en);
++        printk(" pri_16                 : %d\n",s->pri_16);
++        printk(" pri_8                  : %d\n",s->pri_8);
++        printk(" pri_4                  : %d\n",s->pri_4);
++        printk(" pri_uv                 : %d\n",s->pri_uv);
++        printk(" ref_neb_4              : %d\n",s->ref_neb_4);
++        printk(" ref_neb_8              : %d\n",s->ref_neb_8);
++        printk(" lambda_info16          : %d\n",s->lambda_info16);
++        printk(" lambda_info8           : %d\n",s->lambda_info8);
++        printk(" lambda_info4           : %d\n",s->lambda_info4);
++        printk(" lambda_infouv          : %d\n",s->lambda_infouv);
++        printk(" ref_4                  : %d\n",s->ref_4);
++        printk(" ref_8                  : %d\n",s->ref_8);
++
++        int i=0;
++        for (i=0;i<4;i++)
++            printk(" bit_16[%d]             : %d\n",i,s->bit_16[i]);
++        for (i=0;i<4;i++)
++            printk(" bit_uv[%d]             : %d\n",i,s->bit_uv[i]);
++        for (i=0;i<4;i++)
++            printk(" bit_4[%d]              : %d\n",i,s->bit_4[i]);
++        for (i=0;i<4;i++)
++            printk(" bit_8[%d]              : %d\n",i,s->bit_8[i]);
++        for (i=0;i<4;i++)
++            printk(" const_16[%d]           : %d\n",i,s->const_16[i]);
++        for (i=0;i<4;i++)
++            printk(" const_uv[%d]           : %d\n",i,s->const_uv[i]);
++        for (i=0;i<4;i++)
++            printk(" const_4[%d]            : %d\n",i,s->const_4[i]);
++        for (i=0;i<4;i++)
++            printk(" const_8[%d]            : %d\n",i,s->const_8[i]);
++    }
++    /* 9. jrfc,jrfd [5]*/
++    {
++        printk(" jrfcd_flag              : %d\n",s->jrfcd_flag);
++        printk(" jrfc_enable             : %d\n",s->jrfc_enable);
++        printk(" jrfd_enable             : %d\n",s->jrfd_enable);
++        printk(" lm_head_total           : %d\n",s->lm_head_total);
++        printk(" cm_head_total           : %d\n",s->cm_head_total);
++    }
++    /* 10. eigen cfg for mosaic, color error [42]*/
++    {
++        printk(" mb_mode_use             : %d\n",s->mb_mode_use);
++        printk(" force_i16dc             : %d\n",s->force_i16dc);//ipred
++        printk(" force_i16               : %d\n",s->force_i16);
++        printk(" refresh_en              : %d\n",s->refresh_en);
++        printk(" refresh_mode            : %d\n",s->refresh_mode);
++        printk(" refresh_bias            : %d\n",s->refresh_bias);
++        printk(" refresh_cplx_thd        : %d\n",s->refresh_cplx_thd);
++        printk(" cplx_thd_sel            : %d\n",s->cplx_thd_sel);
++        printk(" diff_cplx_sel           : %d\n",s->diff_cplx_sel);
++        printk(" diff_thd_sel            : %d\n",s->diff_thd_sel);
++        printk(" i16dc_cplx_thd          : %d\n",s->i16dc_cplx_thd);
++        printk(" i16dc_qp_base           : %d\n",s->i16dc_qp_base);
++        printk(" i16dc_qp_sel            : %d\n",s->i16dc_qp_sel);
++        printk(" i16_qp_base             : %d\n",s->i16_qp_base);
++        printk(" i16_qp_sel              : %d\n",s->i16_qp_sel);
++        printk(" diff_cplx_thd           : %d\n",s->diff_cplx_thd);
++
++        int i=0;
++        for (i=0;i<2;i++)
++            printk(" diff_qp_base[%d]        : %d\n",i,s->diff_qp_base[i]);
++        for (i=0;i<2;i++)
++            printk(" diff_qp_sel[%d]         : %d\n",i,s->diff_qp_sel[i]);
++        for (i=0;i<24;i++)
++            printk(" cplx_thd_idx[%d]        : %d\n",i,s->cplx_thd_idx[i]);
++        for (i=0;i<8;i++)
++            printk(" cplx_thd[%d]            : %d\n",i,s->cplx_thd[i]);
++        for (i=0;i<3;i++)
++            printk(" diff_thd_base[%d]       : %d\n",i,s->diff_thd_base[i]);
++        for (i=0;i<3;i++)
++            printk(" diff_thd_ofst[%d]       : %d\n",i,s->diff_thd_ofst[i]);
++        printk(" sas_eigen_en            : %d\n",s->sas_eigen_en);
++        printk(" crp_eigen_en            : %d\n",s->crp_eigen_en);
++        printk(" sas_eigen_dump          : %d\n",s->sas_eigen_dump);
++        printk(" crp_eigen_dump          : %d\n",s->crp_eigen_dump);
++        printk(" rrs_en                  : %d\n",s->rrs_en);
++        printk(" rrs_dump_en             : %d\n",s->rrs_dump_en);
++        printk(" rrs_uv_en               : %d\n",s->rrs_uv_en);
++        printk(" rrs_size_y              : %d\n",s->rrs_size_y);
++        printk(" rrs_size_c              : %d\n",s->rrs_size_c);
++        printk(" rrs_thrd_y              : %d\n",s->rrs_thrd_y);
++        printk(" rrs_thrd_u              : %d\n",s->rrs_thrd_u);
++        printk(" rrs_thrd_v              : %d\n",s->rrs_thrd_v);
++    }
++    /* 11. skin judge cfg [14]*/
++    {
++        printk(" skin_dt_en              : %d\n",s->skin_dt_en);
++        printk(" skin_lvl                : %d\n",s->skin_lvl);
++        printk(" skin_cnt_thd            : %d\n",s->skin_cnt_thd);
++        printk(" ncu_mov_en              : %d\n",s->ncu_mov_en);
++        printk(" ncu_move_len            : %d\n",s->ncu_move_len);
++        if (s->ncu_move_info == NULL)
++            printk(" ncu_move_info is NULL \n");
++        else
++            printk(" ncu_move_info       : %p\n",s->ncu_move_info);
++        printk(" buf_share_en            : %d\n",s->buf_share_en);
++        printk(" buf_share_size          : %d\n",s->buf_share_size);
++        printk(" frame_idx               : %d\n",s->frame_idx);
++        printk(" is_first_Pframe         : %d\n",s->is_first_Pframe);
++        int i=0,j=0;
++        for (i=0;i<3;i++)
++            for (j=0;j<2;j++)
++                printk(" skin_pxlu_thd[%d][%d] : %d\n",i,j,s->skin_pxlu_thd[i][j]);
++        for (i=0;i<3;i++)
++            for (j=0;j<2;j++)
++                printk(" skin_pxlv_thd[%d][%d] : %d\n",i,j,s->skin_pxlv_thd[i][j]);
++        for (i=0;i<4;i++)
++            printk(" skin_qp_ofst[%d] : %d\n",i,s->skin_qp_ofst[i]);
++        for (i=0;i<3;i++)
++            printk(" mult_factor[%d] : %d\n",i,s->mult_factor[i]);
++        for (i=0;i<3;i++)
++            for (j=0;j<3;j++)
++                printk(" shift_factor[%d][%d] : %d\n",i,j,s->shift_factor[i][j]);
++        for (i=0;i<4;i++)
++            printk(" skin_ofst[%d] : %d\n",i,s->skin_ofst[i]);
++    }
++    /* 12.qpg */
++    {
++        /* qp map */
++        printk(" qp_tab_en               : %d\n",s->qp_tab_en);
++        printk(" qp_tab_len              : %d\n",s->qp_tab_len);
++        if (s->qp_tab == NULL)
++            printk(" qp_tab is NULL");
++        else
++            printk(" qp_tab : %p\n", s->qp_tab);
++        int i=0;
++        for (i=0;i<8;i++) {
++            printk("roi_en[%d]   : %d\n",i,s->roi_info[i].roi_en);
++            printk("roi_md[%d]   : %d\n",i,s->roi_info[i].roi_md);
++            printk("roi_qp[%d]   : %d\n",i,s->roi_info[i].roi_qp);
++            printk("roi_lmbx[%d] : %d\n",i,s->roi_info[i].roi_lmbx);
++            printk("roi_rmbx[%d] : %d\n",i,s->roi_info[i].roi_rmbx);
++            printk("roi_umby[%d] : %d\n",i,s->roi_info[i].roi_umby);
++            printk("roi_bmby[%d] : %d\n",i,s->roi_info[i].roi_bmby);
++        }
++        /* qp cplx */
++        printk(" sas_en                  : %d\n",s->sas_en);
++        printk(" crp_en                  : %d\n",s->crp_en);
++        printk(" sas_mthd                : %d\n",s->sas_mthd);
++        for (i=0;i<7;i++)
++            printk(" qpg_mb_thd[%d] : %d\n", i,s->qpg_mb_thd[i]);
++        for (i=0;i<8;i++)
++            printk(" qpg_mbqp_ofst[%d] : %d\n", i,s->qpg_mbqp_ofst[i]);
++        for (i=0;i<5;i++)
++            printk(" qpg_flt_thd[%d] : %d\n", i,s->qpg_flt_thd[i]);
++        printk(" mbrc_qpg_sel            : %d\n",s->mbrc_qpg_sel);
++        /* bu rc */
++        printk(" rc_mb_en                : %d\n",s->rc_mb_en);
++        printk(" rc_bu_wait_en           : %d\n",s->rc_bu_wait_en);
++        printk(" rc_mb_wait_en           : %d\n",s->rc_mb_wait_en);
++        printk(" rc_bu_num               : %d\n",s->rc_bu_num);
++        printk(" rc_bu_size              : %d\n",s->rc_bu_size);
++        printk(" rc_bu_level             : %d\n",s->rc_bu_level);
++        printk(" rc_mb_level             : %d\n",s->rc_mb_level);
++        if (s->mb_ref_info == NULL)
++            printk(" mb_ref_info is NULL");
++        else
++            printk(" mb_ref_info : %p\n", s->mb_ref_info);
++        if (s->bu_ref_info == NULL)
++            printk(" bu_ref_info is NULL");
++        else
++            printk(" bu_ref_info : %p\n", s->bu_ref_info);
++        printk(" rc_frm_tbs              : %d\n",s->rc_frm_tbs);
++        printk(" avg_bu_bs               : %d\n",s->avg_bu_bs);
++        for (i=0;i<6;i++)
++            printk(" tar_bs_thd[%d] : %d\n",s->tar_bs_thd[i]);
++        for (i=0;i<6;i++)
++            printk(" tar_bs_thd[%d] : %d\n",s->bu_alg0_qpo[i]);
++        for (i=0;i<6;i++)
++            printk(" bu_alg1_qpo[%d] : %d\n",s->bu_alg1_qpo[i]);
++        for (i=0;i<7;i++)
++            printk(" mb_cs_qpo[%d] : %d\n",s->mb_cs_qpo[i]);
++        for (i=0;i<2;i++)
++            printk(" mb_top_bs_qpo[%d] : %d\n",s->mb_top_bs_qpo[i]);
++        for (i=0;i<2;i++)
++            printk(" mb_rinfo_qpo[%d] : %d\n",s->mb_rinfo_qpo[i]);
++        for (i=0;i<2;i++)
++            printk(" mb_target_avg_bs[%d] : %d\n",s->mb_target_avg_bs[i]);
++        printk(" mb_gp_num               : %d\n",s->mb_gp_num);
++        printk(" last_bu_size            : %d\n",s->last_bu_size);
++        printk(" rc_bcfg_mode            : %d\n",s->rc_bcfg_mode);
++    }
++
++}
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_x264_enc.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_x264_enc.h
+new file mode 100644
+index 000000000..bbb342163
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/api/helix_x264_enc.h
+@@ -0,0 +1,418 @@
++/****************************************************************
++*****************************************************************/
++
++#ifndef __JZM_X264_ENC_H__
++#define __JZM_X264_ENC_H__
++#include "helix.h"
++
++#ifdef __KERNEL__
++#include <linux/types.h>
++#include <linux/printk.h>
++#include <asm-generic/div64.h>
++#define printf printk
++
++#else
++#include <stdint.h>
++#include <stdio.h>
++
++#endif
++
++#define SCH_FIFO_DEPTH      16
++
++/************************************************************
++ CHN Space Allocation
++ ************************************************************/
++#define VRAM_DUMMY          (VPU_BASE | 0xFFFFC)
++
++#define VRAM_MAU_RESA       (VPU_BASE | 0xC0000)  //residual address
++#define VRAM_MAU_RES_SIZE   (SCH_FIFO_DEPTH*256*4)
++
++#define VRAM_RAWY_BA        (VPU_BASE | 0xF0000)
++#define VRAM_RAWC_BA        (VRAM_RAWY_BA + 256)
++#define VRAM_RAW_SIZE       (SCH_FIFO_DEPTH*128*4)
++
++#define VRAM_TOPPA_BA       (VRAM_MAU_RESA+VRAM_MAU_RES_SIZE)  //recover address
++#define VRAM_TOPMV_BA       (VRAM_TOPPA_BA+VPU_MAX_MB_WIDTH*8)
++
++#define VRAM_MAU_CHN_BASE   (VRAM_TOPMV_BA+VPU_MAX_MB_WIDTH*4)
++#define VRAM_MAU_CHN_SIZE   (SCH_FIFO_DEPTH*16*4)
++#define VRAM_DBLK_CHN_BASE  (VRAM_MAU_CHN_BASE + VRAM_MAU_CHN_SIZE)
++#define VRAM_DBLK_CHN_SIZE  (SCH_FIFO_DEPTH*16*4)
++#define VRAM_ME_CHN_BASE    (VRAM_DBLK_CHN_BASE + VRAM_DBLK_CHN_SIZE)
++#define VRAM_ME_CHN_SIZE    (SCH_FIFO_DEPTH*8*4)
++#define VRAM_SDE_CHN_BASE   (VRAM_ME_CHN_BASE + VRAM_ME_CHN_SIZE)
++#define VRAM_SDE_CHN_SIZE   (SCH_FIFO_DEPTH*8*4)
++#define VRAM_QP_TAB_BA      (VRAM_SDE_CHN_BASE + VRAM_SDE_CHN_SIZE)
++
++#define VRAM_ME_DSA         DSA_SCH_CH1
++#define VRAM_MAU_DEC_SYNA   DSA_SCH_CH2
++#define VRAM_DBLK_CHN_SYNA  DSA_SCH_CH3
++#define VRAM_SDE_SYNA       DSA_SCH_CH4
++
++#define VRAM_MAU_ENC_SYNA   VRAM_DUMMY
++#define VRAM_DBLK_DOUT_SYNA VRAM_DUMMY
++
++#define VRAM_ME_MVPA        (VPU_BASE | REG_EFE_MVRP)
++
++#define EMC_SIZE        (1 << 21)
++#define DBLK_SIZE       (1 << 20)
++#define RECON_SIZE      (1 << 18)
++#define MV_SIZE         (1 << 11)
++#define SE_SIZE         (1 << 11)
++#define QPT_SIZE        (1<<14)
++#define RC_SIZE         (1<<15)
++#define CPX_SIZE        (1<<17)
++#define MOD_SIZE        (1<<15)
++#define SAD_SIZE        (1<<17)
++#define ENCU_SIZE        (1<<13)
++#define BEYOND_MAX_SIZE 64*3
++
++typedef unsigned int paddr_t;
++
++#define __ALN32__ __attribute__ ((aligned(4)))
++
++typedef struct ROI_info{
++  uint8_t roi_en;
++  uint8_t roi_md;
++  int8_t  roi_qp;
++  uint8_t roi_lmbx;
++  uint8_t roi_rmbx;
++  uint8_t roi_umby;
++  uint8_t roi_bmby;
++} roi_info_t;
++
++/*
++  _H264E_SliceInfo:
++  H264 Encoder Slice Level Information
++ */
++typedef struct _H264E_SliceInfo {
++  /*basic*/
++  uint8_t frame_type;
++  uint8_t mb_width;
++  uint8_t mb_height;
++  uint8_t first_mby;
++  uint8_t last_mby;  //for multi-slice
++
++  /* motion */
++  int frame_width;
++  int frame_height;
++  uint8_t frm_re[4];
++  uint8_t pskip_en;
++  uint8_t force_mv0_en;
++  uint8_t mref_en;
++  uint8_t dct8x8_en;
++  uint8_t scl;
++  uint8_t hpel_en;
++  uint8_t qpel_en;
++  uint8_t ref_mode;
++  uint32_t max_sech_step_i;
++  uint32_t max_mvrx_i;
++  uint32_t max_mvry_i;
++  uint8_t lambda_scale_parameter;
++  uint8_t fs_en; //fs function enable
++  uint32_t fs_md; //fs step mode, 0: 1, 1: 3
++  uint8_t fs_px; //fs period x
++  uint8_t fs_py; //fs period y
++  uint8_t fs_rx; //fs range x, must be multiples of 3
++  uint8_t fs_ry; //fs range y, must be multiples of 3
++  uint8_t frm_mv_en; //add a frame level mv
++  uint8_t frm_mv_size; //mv enable after x mb, x=2^(size+8)
++  uint8_t glb_mv_en;  //global mv enable
++  int glb_mvx;  //global mvx value
++  int glb_mvy;  //global mvy value
++  uint8_t me_step_en; //auto-modify max step number
++  uint8_t me_step_0; //step number threshold 0
++  uint8_t me_step_1; //step number threshold 1
++  /*vmau scaling list*/
++  uint8_t __ALN32__ scaling_list[4][16];
++  uint8_t __ALN32__ scaling_list8[2][64];
++  int deadzone[9];
++  uint32_t acmask_mode;
++
++  uint32_t intra_mode_msk;
++
++  uint8_t i_4x4_dis;
++  uint8_t i_8x8_dis;
++  uint8_t i_16x16_dis;
++  uint8_t p_l0_dis;
++  uint8_t p_t8_dis;
++  uint8_t p_skip_dis;
++  uint8_t p_skip_pl0f_dis;
++  uint8_t p_skip_pt8f_dis;
++
++  uint8_t cost_bias_en;
++  uint8_t cost_bias_i_4x4;
++  uint8_t cost_bias_i_8x8;
++  uint8_t cost_bias_i_16x16;
++  uint8_t cost_bias_p_l0;
++  uint8_t cost_bias_p_t8;
++  uint8_t cost_bias_p_skip;
++
++  uint8_t intra_lambda_y_bias_en;
++  uint8_t intra_lambda_c_bias_en;
++  uint8_t intra_lambda_bias_qp0;
++  uint8_t intra_lambda_bias_qp1;
++  uint8_t intra_lambda_bias_0;
++  uint8_t intra_lambda_bias_1;
++  uint8_t intra_lambda_bias_2;
++
++  uint8_t chroma_sse_bias_en;
++  uint8_t chroma_sse_bias_qp0;
++  uint8_t chroma_sse_bias_qp1;
++  uint8_t chroma_sse_bias_0;
++  uint8_t chroma_sse_bias_1;
++  uint8_t chroma_sse_bias_2;
++
++  uint8_t sse_lambda_bias_en;
++  uint8_t sse_lambda_bias;
++
++  uint8_t fbc_ep;
++  uint8_t jm_lambda2_en;
++  uint8_t inter_nei_en;
++  uint8_t skip_bias_en;
++
++  uint8_t info_en;
++  uint8_t mvd_sum_all;
++  uint8_t mvd_sum_abs;
++  uint8_t mv_sum_all;
++  uint8_t mv_sum_abs;
++
++  uint32_t ysse_thr;
++  uint32_t csse_thr;
++
++  uint8_t  cfg_size_x;
++  uint8_t  cfg_size_y;
++  uint16_t cfg_iw_thr;
++
++  uint16_t cfg_mvr_thr1;
++  uint32_t cfg_mvr_thr2;
++  uint32_t cfg_mvr_thr3;
++
++  uint8_t  dcm_en;
++  uint32_t dcm_param;
++
++  uint8_t  sde_prior;
++  uint8_t  db_prior;
++  /*ipred bit&lambda ctrl*/
++  uint8_t  mb_mode_val;
++  uint8_t  bit_16_en;
++  uint8_t  bit_8_en;
++  uint8_t  bit_4_en;
++  uint8_t  bit_uv_en;
++  uint8_t  lamb_16_en;
++  uint8_t  lamb_8_en;
++  uint8_t  lamb_4_en;
++  uint8_t  lamb_uv_en;
++  uint8_t  c_16_en;
++  uint8_t  c_8_en;
++  uint8_t  c_4_en;
++  uint8_t  c_uv_en;
++  uint8_t  pri_16;
++  uint8_t  pri_8;
++  uint8_t  pri_4;
++  uint8_t  pri_uv;
++  uint8_t  ref_neb_4;
++  uint8_t  ref_neb_8;
++  uint8_t  bit_16[4];
++  uint8_t  bit_uv[4];
++  uint8_t  bit_4[4];
++  uint8_t  bit_8[4];
++  uint8_t  lambda_info16;
++  uint8_t  lambda_info8;
++  uint8_t  lambda_info4;
++  uint8_t  lambda_infouv;
++  uint8_t  ref_4;
++  uint8_t  ref_8;
++  uint8_t  const_16[4];
++  uint8_t  const_uv[4];
++  uint8_t  const_4[4];
++  uint8_t  const_8[4];
++
++  /*loop filter*/
++  uint8_t deblock;
++  uint8_t rotate;
++  int8_t alpha_c0_offset;
++  int8_t beta_offset;
++
++  /*cabac*/
++  uint8_t *state;
++  paddr_t bs;             /*BS output address*/
++  uint8_t bs_rbsp_en;     /*BS rbsp enable*/
++  uint8_t bs_head_en;     /*read BS header enable*/
++  uint8_t bs_head_len;    /*read BS header lenth*/
++  paddr_t *bs_head_va;     /*read BS header data addr*/
++  paddr_t bs_head_pa;     /*read BS header data addr*/
++  uint8_t qp;
++  uint8_t  bs_size_en;
++  uint32_t bs_size;
++
++  uint8_t skip_en;
++  int8_t cqp_offset;
++  /*mode decision*/
++  uint8_t use_intra_in_pframe;
++  uint8_t use_fast_mvp;
++
++  uint8_t mode_ctrl;
++  uint32_t mode_ctrl_param[40];
++
++  /*frame buffer address: all of the buffers should be 256byte aligned!*/
++  paddr_t fb[3][2];       /*{curr, ref}{tile_y, tile_c}*/
++  paddr_t raw[3];         /*{rawy, rawu, rawv} or {rawy, rawc, N/C}*/
++  int stride[2];          /*{stride_y, stride_c}, only used in raster raw*/
++
++  /* RAW plane format */
++  uint8_t raw_format;
++
++  uint8_t size_mode;
++  uint8_t step_mode;
++  /*descriptor address*/
++  paddr_t *des_va, des_pa;
++  paddr_t emc_bs_pa;
++  paddr_t *emc_dblk_va,emc_dblk_pa;
++  paddr_t *emc_recon_va,emc_recon_pa;
++  paddr_t *emc_mv_va,emc_mv_pa;
++  paddr_t *emc_se_va,emc_se_pa;
++  paddr_t *emc_qpt_va, emc_qpt_pa;
++  paddr_t *emc_rc_va, emc_rc_pa;
++  paddr_t *emc_cpx_va, emc_cpx_pa;
++  paddr_t *emc_mod_va, emc_mod_pa;
++  paddr_t *emc_ncu_va, emc_ncu_pa;
++  paddr_t *emc_sad_va, emc_sad_pa;
++
++  /*TLB address*/
++  paddr_t tlba;
++
++  /* ROI info */
++  roi_info_t roi_info[8];
++  uint8_t base_qp;
++  uint8_t max_qp;
++  uint8_t min_qp;
++
++  uint8_t qp_tab_mode;
++  uint8_t qp_tab_en;
++  uint32_t qp_tab_len;
++  uint32_t *qp_tab;
++  uint8_t sas_en;
++  uint8_t crp_en;
++  uint8_t sas_mthd;
++  uint16_t qpg_mb_thd[7];
++  int8_t qpg_mbqp_ofst[8];
++  uint8_t qpg_flt_thd[5];
++  uint8_t mbrc_qpg_sel; //whether use crp/sas qp offset or not, when MB rate control enable.
++
++  /* rate ctrl */
++  uint8_t rc_mb_en;
++  uint8_t rc_bu_wait_en;// efe chn wait rc qp offset en
++  uint8_t rc_mb_wait_en;// efe chn wait rc qp offset en
++  uint8_t rc_bu_num;// total basic unit number
++  uint16_t rc_bu_size;// mb number in a basic unit
++  uint8_t rc_bu_level;// 1:1line 2:2line 3:4line 4:8line 5:16line 6:32line 7:64line
++  uint8_t rc_mb_level;// 0:skip 1mb, 1:skip 2mb, 2:skip 4mb, 3:skip 8mb
++  int32_t *mb_ref_info;
++  int32_t *bu_ref_info;
++  uint32_t rc_frm_tbs;
++  uint32_t avg_bu_bs;
++  uint16_t tar_bs_thd[6];
++  int8_t bu_alg0_qpo[6];
++  int8_t bu_alg1_qpo[6];
++  int8_t mb_cs_qpo[7];
++  int8_t mb_top_bs_qpo[2];
++  int8_t mb_rinfo_qpo[2];
++  uint16_t mb_target_avg_bs[2];
++  uint16_t mb_gp_num;
++  uint16_t last_bu_size;
++  uint8_t rc_bcfg_mode;
++
++  //mosaic
++  uint8_t mosaic_en;
++  uint8_t mos_gthd[2];
++  uint8_t mos_sthd[2];
++  /* VPU Daisy Chain setting */
++  uint8_t daisy_chain_en;
++  uint8_t curr_thread_id;
++
++  //odma,jrfc,jrfd
++  uint8_t jrfcd_flag;
++  uint8_t jrfc_enable;
++  uint8_t jrfd_enable;
++  uint32_t lm_head_total;
++  uint32_t cm_head_total;
++  paddr_t jh[3][2];       /*head addr {curr, ref0, ref1}{y, c}*/
++  paddr_t spe_y_addr;
++  paddr_t spe_c_addr;
++
++  //eigen cfg
++  uint8_t     mb_mode_use;
++  uint32_t    *mb_mode_info;
++  uint8_t     force_i16dc;//ipred
++  uint8_t     force_i16;
++  uint8_t     refresh_en;
++  uint8_t     refresh_mode;
++  uint8_t     refresh_bias;
++  uint8_t     refresh_cplx_thd;
++  uint8_t     cplx_thd_sel;
++  uint8_t     diff_cplx_sel;
++  uint8_t     diff_thd_sel;
++  uint8_t     i16dc_cplx_thd;
++  uint8_t     i16dc_qp_base;
++  uint8_t     i16dc_qp_sel;
++  uint8_t     i16_qp_base;
++  uint8_t     i16_qp_sel;
++  uint8_t     diff_cplx_thd;
++  uint8_t     diff_qp_base[2];
++  uint8_t     diff_qp_sel[2];
++  uint8_t     cplx_thd_idx[24];
++  uint8_t     cplx_thd[8];
++  uint16_t    diff_thd_base[3];
++  uint16_t    diff_thd_ofst[3];
++  uint8_t     sas_eigen_en;
++  uint8_t     crp_eigen_en;
++  uint8_t     sas_eigen_dump;
++  uint8_t     crp_eigen_dump;
++  //ifa
++  uint8_t     rrs_en;
++  uint8_t     rrs_dump_en;
++  uint8_t     rrs_uv_en;
++  uint8_t     rrs_size_y; //0: 4, 1: 8, 2: 12, 3: 16
++  uint8_t     rrs_size_c; //0: 4, 1: 8
++  uint16_t    rrs_thrd_y; //threshold
++  uint16_t    rrs_thrd_u;
++  uint16_t    rrs_thrd_v;
++
++  //skin
++  uint8_t     skin_dt_en;
++  uint8_t     skin_lvl;
++  uint8_t     skin_cnt_thd;
++  uint8_t     skin_pxlu_thd[3][2];
++  uint8_t     skin_pxlv_thd[3][2];
++  int8_t      skin_qp_ofst[4];
++  uint8_t     mult_factor[3];
++  uint8_t     shift_factor[3][3];//[0][]:0.4, [1][]:0.6, [2][]: 5.1
++  uint16_t    skin_ofst[4];//[0]: 1.5, [1]:0.4, [2]:0.6, [3]: 5.1
++  uint8_t     ncu_mov_en;
++  uint32_t    ncu_move_len;
++  uint32_t    *ncu_move_info;
++  //buf-share
++  uint8_t     buf_share_en;
++  uint8_t     buf_share_size;
++  uint32_t    frame_idx;
++  uint8_t     is_first_Pframe;
++}_H264E_SliceInfo;
++
++typedef struct _H264E_SliceInfo H264E_SliceInfo_t;
++
++
++/*
++  H264E_SliceInit(_H264E_SliceInfo *s)
++  @param s: slice information structure
++ */
++void H264E_SliceInit(_H264E_SliceInfo *s);
++void H264E_DumpInfo(_H264E_SliceInfo *s);
++
++
++/*
++	default _H264_SliceInfo.
++*/
++extern _H264E_SliceInfo default_H264E_Sliceinfo;
++
++#endif /*__JZM_H264E_H__*/
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/default_sliceinfo.c b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/default_sliceinfo.c
+new file mode 100644
+index 000000000..8a0b85675
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/default_sliceinfo.c
+@@ -0,0 +1,362 @@
++#include "api/helix_x264_enc.h"
++
++_H264E_SliceInfo default_H264E_Sliceinfo = {
++	.frame_type = 1,
++	.mb_width = 22,
++	.mb_height = 18,
++	.first_mby = 0,
++	.last_mby = 17,
++	.frame_width = 352,
++	.frame_height = 288,
++
++	.frm_re = {0x00, 0x00, 0x00, 0x00},
++	.pskip_en = 1,
++	.mref_en = 0,
++	.dct8x8_en = 0,
++	.scl = 0x03,
++	.hpel_en = 0x01,
++	.qpel_en = 0x01,
++	.ref_mode = 0x01,
++	.max_sech_step_i = 0x3f,
++	.max_mvrx_i = 0x1f4,
++	.max_mvry_i = 0x1f4,
++	.lambda_scale_parameter = 0x08,
++	.fs_en = 0x00,
++	.fs_md = 0x00,
++	.fs_px = 0x00,
++	.fs_py = 0x00,
++	.fs_rx = -1,
++	.fs_ry = -1,
++	.frm_mv_en = 0x00,
++	.frm_mv_size = 0x00,
++	.glb_mv_en = 0x00,
++	.glb_mvx = 0,
++	.glb_mvy = 0,
++	.me_step_en = 0x0,
++	.me_step_0 = 0x0,
++	.me_step_1 = 0x0,
++	.scaling_list = {
++		{0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, },
++		{0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, },
++		{0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, },
++		{0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, },
++	},
++	.scaling_list8 = {
++		{0x06, 0x0a, 0x0d, 0x10, 0x12, 0x16, 0x18, 0x1a, 0x0a, 0x0b, 0x10, 0x12, 0x16, 0x18, 0x1a, 0x1c, 0x0d, 0x10, 0x12, 0x16, 0x18, 0x1a, 0x1c, 0x1e, 0x10, 0x12, 0x16, 0x18, 0x1a, 0x1c, 0x1e, 0x20, 0x12, 0x16, 0x18, 0x1a, 0x1c, 0x1e, 0x20, 0x23, 0x16, 0x18, 0x1a, 0x1c, 0x1e, 0x20, 0x23, 0x25, 0x18, 0x1a, 0x1c, 0x1e, 0x20, 0x23, 0x25, 0x27, 0x1a, 0x1c, 0x1e, 0x20, 0x23, 0x25, 0x27, 0x29, },
++		{0x09, 0x0d, 0x0f, 0x11, 0x13, 0x15, 0x16, 0x18, 0x0d, 0x0d, 0x11, 0x13, 0x15, 0x16, 0x18, 0x19, 0x0f, 0x11, 0x13, 0x15, 0x16, 0x18, 0x19, 0x1b, 0x11, 0x13, 0x15, 0x16, 0x18, 0x19, 0x1b, 0x1c, 0x13, 0x15, 0x16, 0x18, 0x19, 0x1b, 0x1c, 0x1e, 0x15, 0x16, 0x18, 0x19, 0x1b, 0x1c, 0x1e, 0x20, 0x16, 0x18, 0x19, 0x1b, 0x1c, 0x1e, 0x20, 0x21, 0x18, 0x19, 0x1b, 0x1c, 0x1e, 0x20, 0x21, 0x23, },
++	},
++
++	.deadzone =  { 0x00000015, 0x0000000b, 0x00000015, 0x0000000b, 0x00000015, 0x0000000b, 0x00000015, 0x00000015, 0x0000000b},
++	.acmask_mode = 0x000095ea,
++	.intra_mode_msk = 0x0,
++	.i_4x4_dis = 0x0,
++	.i_8x8_dis = 0x0,
++	.i_16x16_dis = 0x0,
++	.p_l0_dis = 0x0,
++	.p_t8_dis = 0x0,
++	.p_skip_dis = 0x0,
++	.p_skip_pl0f_dis = 0x0,
++	.p_skip_pt8f_dis = 0x0,
++	.cost_bias_en = 0x0,
++	.cost_bias_i_4x4 = 0x0,
++	.cost_bias_i_8x8 = 0x0,
++	.cost_bias_i_16x16 = 0x0,
++	.cost_bias_p_l0 = 0x0,
++	.cost_bias_p_t8 = 0x0,
++	.cost_bias_p_skip = 0x0,
++	.intra_lambda_y_bias_en = 0x0,
++	.intra_lambda_c_bias_en = 0x0,
++	.intra_lambda_bias_qp0 = 0x0,
++	.intra_lambda_bias_qp1 = 0x0,
++	.intra_lambda_bias_0 = 0x0,
++	.intra_lambda_bias_1 = 0x0,
++	.intra_lambda_bias_2 = 0x0,
++	.chroma_sse_bias_en = 0x0,
++	.chroma_sse_bias_qp0 = 0x0,
++	.chroma_sse_bias_qp1 = 0x0,
++	.chroma_sse_bias_0 = 0x0,
++	.chroma_sse_bias_1 = 0x0,
++	.chroma_sse_bias_2 = 0x0,
++	.sse_lambda_bias_en = 0x0,
++	.sse_lambda_bias = 0x0,
++	.fbc_ep = 0xcc,
++	.jm_lambda2_en = 0x0,
++	.inter_nei_en = 0x0,
++	.skip_bias_en = 0x0,
++	.info_en = 0x1,
++	.mvd_sum_all = 0x0,
++	.mvd_sum_abs = 0x0,
++	.mv_sum_all = 0x0,
++	.mv_sum_abs = 0x0,
++	.ysse_thr = 0x0,
++	.csse_thr = 0x0,
++	.cfg_size_x = 0x4,
++	.cfg_size_y = 0x4,
++	.cfg_iw_thr = 0x0,
++	.cfg_mvr_thr1 = 0x0,
++	.cfg_mvr_thr2 = 0x0,
++	.cfg_mvr_thr3 = 0x0,
++	.dcm_en = 0x0,
++	.dcm_param = 0x4304,
++	.sde_prior = 0x5,
++	.db_prior = 0x5,
++	.mb_mode_val = 0x1,
++	.bit_16_en = 0x0,
++	.bit_8_en = 0x1,
++	.bit_4_en = 0x1,
++	.bit_uv_en = 0x0,
++	.lamb_16_en = 0x0,
++	.lamb_8_en = 0x0,
++	.lamb_4_en = 0x0,
++	.lamb_uv_en = 0x0,
++	.c_16_en = 0x0,
++	.c_8_en = 0x0,
++	.c_4_en = 0x0,
++	.c_uv_en = 0x0,
++	.pri_16 = 0x0,
++	.pri_8 = 0x0,
++	.pri_4 = 0x0,
++	.pri_uv = 0x0,
++	.ref_neb_4 = 0x1,
++	.ref_neb_8 = 0x1,
++	.bit_16 = {0,0,0,0},
++	.bit_uv = {0,0,0,0},
++	.bit_4 = {4,4,4,4},
++	.bit_8 = {4,4,4,4},
++	.lambda_info16 = 0x0,
++	.lambda_info8 = 0x0,
++	.lambda_info4 = 0x0,
++	.lambda_infouv = 0x0,
++	.ref_4 = 0x4,
++	.ref_8 = 0x3,
++	.const_16 = {0,0,0,0},
++	.const_uv = {0,0,0,0},
++	.const_4 = {0,0,0,0},
++	.const_8 = {0,0,0,0},
++	.deblock = 1,
++	.rotate = 0,
++	.alpha_c0_offset = 0,
++	.beta_offset = 0,
++	.state = 0xf7edfc94,
++	.bs = 0x00000000,
++	.qp = 0x26,
++	.bs_size_en = 0x1,
++	.bs_size = 0x800,
++	.skip_en = 1,
++	.cqp_offset = 0,
++	.use_intra_in_pframe = 0x1,
++	.use_fast_mvp = 0x0,
++	.mode_ctrl = 0x0,
++	.mode_ctrl_param = {0},
++	.fb = {{0,0},{0,0},{0,0}},
++	.raw = {0,0,0},
++	.stride = {0,0},
++	.raw_format = 8,
++	.size_mode = 0,
++	.step_mode = 0,
++	.des_va = 0,
++	.des_pa = 0,
++	.emc_bs_pa = 0,
++	.emc_dblk_pa = 0,
++//	.emc_bs_va = 0,
++	.emc_dblk_va = 0,
++	.emc_recon_va = 0,
++	.emc_mv_va = 0,
++	.emc_se_va = 0,
++	.emc_recon_va = 0,
++	.emc_recon_pa = 0,
++	.emc_mv_pa = 0,
++	.emc_se_pa = 0,
++	.emc_qpt_va = 0,
++	.emc_qpt_pa = 0,
++	.emc_rc_va = 0,
++	.emc_rc_pa = 0,
++	.emc_cpx_va = 0,
++	.emc_cpx_pa = 0,
++	.emc_mod_va = 0,
++	.emc_mod_pa = 0,
++	.emc_ncu_va = 0,
++	.emc_ncu_pa = 0,
++	.emc_sad_va = 0,
++	.emc_sad_pa = 0,
++	.tlba = 0,
++	.roi_info = {
++		{0,0,0,0,0,0,0},
++		{0,0,0,0,0,0,0},
++		{0,0,0,0,0,0,0},
++		{0,0,0,0,0,0,0},
++		{0,0,0,0,0,0,0},
++		{0,0,0,0,0,0,0},
++		{0,0,0,0,0,0,0},
++		{0,0,0,0,0,0,0},
++	},
++	.base_qp = 38,
++	.max_qp = 51,
++	.min_qp = 26,
++	.qp_tab_mode = 0,
++	.qp_tab_en = 0,
++	.qp_tab_len = 0,
++	.qp_tab = NULL,
++	.sas_en = 0,
++	.crp_en = 0,
++	.sas_mthd = 0,
++	.qpg_mb_thd = {0,0,0,0,0,0,0},
++	.qpg_mbqp_ofst = {0,0,0,0,0,0,0},
++	.qpg_flt_thd = {0,0,0,0,0},
++	.mbrc_qpg_sel = 0,
++	.rc_mb_en = 0,
++	.rc_bu_wait_en = 0,
++	.rc_mb_wait_en = 0,
++	.rc_bu_num = 0x00000012,
++	.rc_bu_size = 0x00000016,
++	.rc_bu_level = 1,
++	.rc_mb_level = 2,
++	.mb_ref_info = NULL,
++	.bu_ref_info = NULL,
++	.rc_frm_tbs = 1000,
++	.avg_bu_bs = 55,
++	.tar_bs_thd = {500, 1000, 1500, 2000, 2500, 3000},
++	.bu_alg0_qpo = {1,2,3,4,5,6},
++	.bu_alg1_qpo = {1,1,1,1,1,1},
++	.mb_cs_qpo = {-3,-2,-1,0,1,2,3},
++	.mb_top_bs_qpo = {-1, 1},
++	.mb_rinfo_qpo = {-1, 1},
++	.mb_target_avg_bs = {2,2},
++	.mb_gp_num = 198,
++	.last_bu_size = 22,
++	.rc_bcfg_mode = 0,
++	.mosaic_en = 0,
++	.mos_gthd = {1,4},
++	.mos_sthd = {8,6},
++	.daisy_chain_en = 0,
++	.curr_thread_id = 5,
++	.jrfcd_flag = 0,
++	.jrfc_enable = 0,
++	.jrfd_enable = 0,
++	.lm_head_total = 0,
++	.cm_head_total = 0,
++	.jh = {{0,0}, {0,0}, {0,0}},
++	.spe_y_addr = 0,
++	.spe_c_addr = 0,
++	.mb_mode_use = 0,
++	.mb_mode_info = NULL,
++	.force_i16dc = 1,
++	.force_i16 = 1,
++	.refresh_en = 0,
++	.refresh_mode = 0,
++	.refresh_bias = 10,
++	.refresh_cplx_thd = 4,
++	.cplx_thd_sel = 0,
++	.diff_cplx_sel = 0,
++	.diff_thd_sel = 0,
++	.i16dc_cplx_thd = 3,
++	.i16dc_qp_base = 33,
++	.i16dc_qp_sel = 0,
++	.i16_qp_base = 28,
++	.i16_qp_sel = 0,
++	.diff_cplx_thd = 10,
++	.diff_qp_base = {33,33},
++	.diff_qp_sel = {0, 0},
++	.cplx_thd_idx = {
++		0, /*cplx_thd_idx[0]*/
++		0, /*cplx_thd_idx[1]*/
++		1, /*cplx_thd_idx[2]*/
++		1, /*cplx_thd_idx[3]*/
++		1, /*cplx_thd_idx[4]*/
++		1, /*cplx_thd_idx[5]*/
++		1, /*cplx_thd_idx[6]*/
++		2, /*cplx_thd_idx[7]*/
++		2, /*cplx_thd_idx[8]*/
++		2, /*cplx_thd_idx[9]*/
++		2, /*cplx_thd_idx[10]*/
++		2, /*cplx_thd_idx[11]*/
++		2, /*cplx_thd_idx[12]*/
++		2, /*cplx_thd_idx[13]*/
++		2, /*cplx_thd_idx[14]*/
++		2, /*cplx_thd_idx[15]*/
++		2, /*cplx_thd_idx[16]*/
++		2, /*cplx_thd_idx[17]*/
++		2, /*cplx_thd_idx[18]*/
++		2, /*cplx_thd_idx[19]*/
++		3, /*cplx_thd_idx[20]*/
++		3, /*cplx_thd_idx[21]*/
++		3, /*cplx_thd_idx[22]*/
++		3, /*cplx_thd_idx[23]*/
++	},
++
++	.cplx_thd = {
++		0, /*cplx_thd[0]*/
++		5, /*cplx_thd[1]*/
++		10, /*cplx_thd[2]*/
++		15, /*cplx_thd[3]*/
++		0, /*cplx_thd[4]*/
++		0, /*cplx_thd[5]*/
++		0, /*cplx_thd[6]*/
++		0, /*cplx_thd[7]*/
++	},
++
++	.diff_thd_base = {
++		384, /*diff_thd_base[0]*/
++		96, /*diff_thd_base[1]*/
++		96, /*diff_thd_base[2]*/
++	},
++
++	.diff_thd_ofst = {
++		48, /*diff_thd_ofst[0]*/
++		12, /*diff_thd_ofst[1]*/
++		12, /*diff_thd_ofst[2]*/
++	},
++	.sas_eigen_en = 0,
++	.crp_eigen_en = 0,
++	.sas_eigen_dump = 0,
++	.crp_eigen_dump = 0,
++	.rrs_en = 0,
++	.rrs_dump_en = 1,
++	.rrs_uv_en = 0,
++	.rrs_size_y = 16,
++	.rrs_size_c = 8,
++	.rrs_thrd_y = 624,
++	.rrs_thrd_u = 156,
++	.rrs_thrd_v = 156,
++	.skin_dt_en = 0,
++	.skin_lvl = 0,
++	.skin_cnt_thd = 20,
++	.skin_pxlu_thd = {
++		{100, 130, },
++		{40, 110, },
++		{120, 160, },
++	},
++	.skin_pxlv_thd = {
++		{140, 175, },
++		{120, 155, },
++		{165, 225, },
++	},
++	.skin_qp_ofst = {
++		-8, /*skin_qp_ofst[0]*/
++		-4, /*skin_qp_ofst[1]*/
++		-2, /*skin_qp_ofst[2]*/
++		1, /*skin_qp_ofst[3]*/
++	},
++	.mult_factor = {
++		3, /*mult_factor[0]*/
++		9, /*mult_factor[1]*/
++		5, /*mult_factor[2]*/
++	},
++	.shift_factor = {
++		{3, 5, 8, },
++		{4, 5, 6, },
++		{4, 5, 6, },
++	},
++	.skin_ofst = {
++		97, /*skin_ofst[0]*/
++		183, /*skin_ofst[1]*/
++		271, /*skin_ofst[2]*/
++		884, /*skin_ofst[3]*/
++	},
++	.ncu_mov_en = 0,
++	.ncu_move_len = 0,
++	.ncu_move_info = NULL,
++	.buf_share_en = 0,
++	.buf_share_size = 0,
++	.frame_idx = 2,
++};
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e.c b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e.c
+new file mode 100644
+index 000000000..3cb4aaf1d
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e.c
+@@ -0,0 +1,1408 @@
++/*
++* Copyright© 2014 Ingenic Semiconductor Co.,Ltd
++*
++* Author: qipengzhen <aric.pzqi@ingenic.com>
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License version 2 as
++* published by the Free Software Foundation.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++* GNU General Public License for more details.
++*
++*/
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <media/v4l2-mem2mem.h>
++
++#include "api/helix_x264_enc.h"
++
++#include "h264enc/common.h"
++#include "h264enc/set.h"
++#include "h264e.h"
++#include "helix_drv.h"
++
++
++static uint8_t cqm_8iy_tab[64] = {
++    6+10,10+10,13+10,16+10,18+10,23+10,25+10,27+10,
++    10+10,11+10,16+10,18+10,23+10,25+10,27+10,29+10,
++    13+10,16+10,18+10,23+10,25+10,27+10,29+10,31+10,
++    16+10,18+10,23+10,25+10,27+10,29+10,31+10,33+10,
++    18+10,23+10,25+10,27+10,29+10,31+10,33+10,36+10,
++    23+10,25+10,27+10,29+10,31+10,33+10,36+10,38+10,
++    25+10,27+10,29+10,31+10,33+10,36+10,38+10,40+10,
++    27+10,29+10,31+10,33+10,36+10,38+10,40+10,42+10
++};
++static uint8_t cqm_8py_tab[64] = {
++    9+10,13+10,15+10,17+10,19+10,21+10,22+10,24+10,
++    13+10,13+10,17+10,19+10,21+10,22+10,24+10,25+10,
++    15+10,17+10,19+10,21+10,22+10,24+10,25+10,27+10,
++    17+10,19+10,21+10,22+10,24+10,25+10,27+10,28+10,
++    19+10,21+10,22+10,24+10,25+10,27+10,28+10,30+10,
++    21+10,22+10,24+10,25+10,27+10,28+10,30+10,32+10,
++    22+10,24+10,25+10,27+10,28+10,30+10,32+10,33+10,
++    24+10,25+10,27+10,28+10,30+10,32+10,33+10,35+10
++};
++
++
++/* static int      rc_deadzone[9]         = {0x1d,0x12,0x15,0xb,0x1d,0x12,0x1d,0x15,0xb}; */
++static uint16_t rc_skin_ofst[4]        = {97, 183, 271, 884};//[0]: 1.5, [1]:0.4, [2]:0.6, [3]: 5.1
++static uint8_t  rc_mult_factor[3]      = {3,9,5};
++//static int8_t   rc_skin_qp_ofst[4]     = {-3, -2, -1, 0};
++static int8_t   rc_skin_qp_ofst[4]     = {-6, -4, -2, 0};
++static uint8_t  rc_skin_pxlu_thd[3][2] = {{100, 120},{50, 100},{120, 150}};
++static uint8_t  rc_skin_pxlv_thd[3][2] = {{140, 175},{125, 140},{175, 225}};
++static uint8_t  rc_shift_factor[3][3]  = {{3,5,8},{4,5,6},{4,5,6}};//[0][]:0.4, [1][]:0.6, [2][]: 5.1
++
++
++static unsigned add_sps_pps_iframe = 1;
++module_param(add_sps_pps_iframe, uint, S_IRUGO | S_IWUSR);
++
++/*TODO: export to high level ????*/
++int h264e_set_params(struct h264e_ctx *ctx, unsigned id, unsigned int val)
++{
++	int ret = 0;
++
++
++	return ret;
++}
++
++int h264e_get_params(struct h264e_ctx *ctx, int id)
++{
++	unsigned int val = 0;
++
++	return val;
++}
++
++int h264e_set_fmt(struct h264e_ctx *ctx, int width, int height, int format)
++{
++	struct h264e_params *p = &ctx->p;
++	int ret = 0;
++
++
++	p->width = width;
++	p->height = height;
++	switch(format) {
++		case HELIX_NV12_MODE:
++		case HELIX_NV21_MODE:
++		case HELIX_TILE_MODE:
++		case HELIX_420P_MODE:
++			p->format = format;
++			break;
++		default:
++			pr_err("Unsupported pix fmt: %x\n", format);
++			ret = -EINVAL;
++			break;
++	}
++
++	ctx->framesize = width * height;
++
++	return ret;
++}
++
++//to profile_idc
++static int __maybe_unused v4l2_profile(int i_profile_idc)
++{
++	switch (i_profile_idc) {
++		case PROFILE_BASELINE:           return V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE;
++		case PROFILE_MAIN:               return V4L2_MPEG_VIDEO_H264_PROFILE_MAIN;
++		case PROFILE_HIGH10:             return V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10;
++		case PROFILE_HIGH422:            return V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422;
++		case PROFILE_HIGH444_PREDICTIVE: return V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE;
++		default: return -EINVAL;
++	}
++
++}
++
++static int __maybe_unused h264e_profile_idc(int v4l2_profile)
++{
++	switch (v4l2_profile) {
++		case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE: 		return PROFILE_BASELINE;
++		case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN: 		return PROFILE_MAIN;
++		case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10: 		return PROFILE_HIGH10;
++		case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422: 		return PROFILE_HIGH422;
++		case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE: 	return PROFILE_HIGH444_PREDICTIVE;
++		default: return -EINVAL;
++	}
++}
++
++static int __maybe_unused v4l2_h264_level(int i_level_idc)
++{
++	switch (i_level_idc) {
++		case 10: return V4L2_MPEG_VIDEO_H264_LEVEL_1_0;
++		case 9:  return V4L2_MPEG_VIDEO_H264_LEVEL_1B;
++		case 11: return V4L2_MPEG_VIDEO_H264_LEVEL_1_1;
++		case 12: return V4L2_MPEG_VIDEO_H264_LEVEL_1_2;
++		case 13: return V4L2_MPEG_VIDEO_H264_LEVEL_1_3;
++		case 20: return V4L2_MPEG_VIDEO_H264_LEVEL_2_0;
++		case 21: return V4L2_MPEG_VIDEO_H264_LEVEL_2_1;
++		case 22: return V4L2_MPEG_VIDEO_H264_LEVEL_2_2;
++		case 30: return V4L2_MPEG_VIDEO_H264_LEVEL_3_0;
++		case 31: return V4L2_MPEG_VIDEO_H264_LEVEL_3_1;
++		case 32: return V4L2_MPEG_VIDEO_H264_LEVEL_3_2;
++		case 40: return V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
++		case 41: return V4L2_MPEG_VIDEO_H264_LEVEL_4_1;
++		default: return -EINVAL;
++	}
++}
++
++static int h264e_level_idc(int level)
++{
++	switch (level) {
++		case V4L2_MPEG_VIDEO_H264_LEVEL_1_0: return 10;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_1B:  return 9;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_1_1: return 11;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_1_2: return 12;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_1_3: return 13;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_2_0: return 20;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_2_1: return 21;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_2_2: return 22;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_3_0: return 30;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_3_1: return 31;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_3_2: return 32;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_4_0: return 40;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_4_1: return 41;
++		default: return -EINVAL;
++	}
++}
++
++/* ----------------------------- Picture Parameter Sets ---------------*/
++static void h264e_sps_init(struct h264e_ctx *ctx, h264_sps_t *sps, int i_id)
++{
++	struct h264e_params *p = &ctx->p;
++	int max_frame_num = 1;
++
++	sps->i_id 			= i_id;
++	sps->i_mb_width 		= C_ALIGN(p->width, 16) / 16;
++	sps->i_mb_height 		= C_ALIGN(p->height, 16) / 16;
++	sps->i_chroma_format_idc 	= CHROMA_420;
++	sps->b_qpprime_y_zero_transform_bypass = 0;
++	sps->i_profile_idc 		= h264e_profile_idc(p->h264_profile);
++	sps->b_constraint_set0 		= sps->i_profile_idc == PROFILE_BASELINE;
++	sps->b_constraint_set1 		=  sps->i_profile_idc <= PROFILE_MAIN;
++	sps->b_constraint_set2 		= 0;
++	sps->b_constraint_set3 		= 0;
++
++	sps->i_level_idc 		= h264e_level_idc(p->h264_level);
++	if((sps->i_level_idc == 9) && (sps->i_profile_idc == PROFILE_BASELINE || sps->i_profile_idc == PROFILE_MAIN)) {
++		sps->b_constraint_set0 	= 1; /* level 1b with Baseline or Main profile is signalled via constraint_set3 */
++		sps->i_level_idc 	= 11;
++	}
++
++
++	sps->i_num_ref_frames 		= p->max_ref_pic;
++	sps->vui.i_num_reorder_frames 	= 0;
++	sps->vui.i_max_dec_frame_buffering = sps->i_num_ref_frames;
++
++	sps->i_log2_max_frame_num 	= 4;
++	while((1 << sps->i_log2_max_frame_num) <= max_frame_num)
++		sps->i_log2_max_frame_num++;
++
++	sps->i_poc_type = 2;
++
++	if(sps->i_poc_type == 0) {
++	}
++
++	sps->b_vui = 0;
++
++	sps->b_gaps_in_frame_num_value_allowed = 0;
++	sps->b_frame_mbs_only = 1;
++	if(!sps->b_frame_mbs_only)
++		sps->i_mb_height = (sps->i_mb_height + 1) & ~1;
++	sps->b_mb_adaptive_frame_field = p->interlaced;
++	sps->b_direct8x8_inference = 1;
++	sps->b_crop = 0;
++
++//	h264_sps_init_reconfigurable(sps, sw);
++
++
++	sps->vui.b_overscan_info_present = 0;
++	sps->vui.b_overscan_info = 0;
++
++	sps->i_cqm_preset = 0;
++	sps->b_avcintra = 0;
++
++}
++
++static void h264e_pps_init(struct h264e_ctx *ctx, h264_pps_t *pps, int i_id, h264_sps_t *sps)
++{
++	struct h264e_params *p = &ctx->p;
++
++	pps->i_id = i_id;
++	pps->i_sps_id = sps->i_id;
++	pps->b_cabac = p->i_cabac;
++
++	pps->b_pic_order = 0;
++	pps->i_num_slice_groups = 1; /* base & main profile.*/
++
++	pps->i_num_ref_idx_l0_default_active = p->max_ref_pic;
++	pps->i_num_ref_idx_l1_default_active = 1;
++
++	pps->b_weighted_pred = 0;
++	pps->b_weighted_bipred = 0;
++
++	pps->i_pic_init_qp = 0;
++	pps->i_pic_init_qs = 26;
++
++	pps->i_chroma_qp_index_offset = 0;
++	pps->b_deblocking_filter_control = 0;
++	pps->b_constrained_intra_pred = 0;
++	pps->b_redundant_pic_cnt = 0;
++
++	pps->b_transform_8x8_mode = p->h264_8x8_transform;
++}
++
++
++static int encapsulate_nal(bs_t *s, int s_off, char *dst, int i_type, int i_ref_idc)
++{
++
++	uint8_t *src = s->p_start + s_off;
++	uint8_t *end = src + (bs_pos(s) / 8);
++	char *orig_dst = dst;
++
++	/* prefix */
++	*dst++ = 0x00;
++	*dst++ = 0x00;
++	*dst++ = 0x00;
++	*dst++ = 0x01;
++
++	/* nal header */
++	*dst++ = (0 << 7) | (i_ref_idc << 5) | (i_type);
++
++	if(src < end) *dst++ = *src++;
++	if(src < end) *dst++ = *src++;
++	while( src < end )
++	{
++		if( src[0] <= 0x03 && !src[-2] && !src[-1] ) {
++			*dst++ = 0x03;
++		}
++		*dst++ = *src++;
++	}
++
++	return dst - orig_dst;
++}
++
++/**
++* @h264e_generate_headers generate sps/pps headers according to params.
++*			and store the header until encoder closed.
++* @ctx h264e_ctx.
++*
++* @Return 0
++*/
++int h264e_generate_headers(struct h264e_ctx *ctx)
++{
++	/* used to encode header for tmp.*/
++	char *bs_tmp = NULL;
++	char *bs_header = ctx->bs_header;
++	bs_t bs;
++	int bs_size = 0;
++	h264_sps_t *sps = NULL;
++	h264_pps_t *pps = NULL;
++
++	bs_tmp = kzalloc(MAX_BS_HEADER_SIZE, GFP_KERNEL);
++	if(!bs_tmp) {
++		return -ENOMEM;
++	}
++
++	sps = &ctx->sps;
++	pps = &ctx->pps;
++
++	h264e_sps_init(ctx, sps, 0);
++	h264e_pps_init(ctx, pps, 0, sps);
++
++	/* 1. encode sps */
++	bs_init(&bs, bs_tmp, MAX_BS_HEADER_SIZE);
++	h264e_sps_write(&bs, sps);
++
++	bs_size = encapsulate_nal(&bs, 0, bs_header, NAL_SPS, NAL_PRIORITY_HIGHEST);
++
++	ctx->bs_header_size += bs_size;
++	bs_header	    += bs_size;
++
++	/* 2. encode pps */
++	bs_init(&bs, bs_tmp, MAX_BS_HEADER_SIZE);
++	h264e_pps_write(&bs, sps, pps);
++
++	bs_size = encapsulate_nal(&bs, 0, bs_header, NAL_PPS, NAL_PRIORITY_HIGHEST);
++	ctx->bs_header_size += bs_size;
++	bs_header 	   += bs_size;
++
++
++	if(ctx->bs_header_size > (MAX_BS_HEADER_SIZE - 512)) {
++		pr_warn("bs_header buffer almost overflow!\n");
++	}
++
++	/* 3. encode sei */
++
++	/* 4. encode more */
++
++	/* release temp buffer. */
++	kfree(bs_tmp);
++	return 0;
++}
++
++static int h264e_slice_init(struct h264e_ctx * ctx, int i_nal_type)
++{
++	if(i_nal_type == NAL_SLICE_IDR) {
++
++		h264e_slice_header_init(&ctx->sh, &ctx->sps, &ctx->pps, ctx->p.i_idr_pic_id, ctx->i_frame, ctx->p.i_qp);
++		ctx->p.i_idr_pic_id ^= 1;
++	} else {
++		h264e_slice_header_init(&ctx->sh, &ctx->sps, &ctx->pps, -1, ctx->i_frame, ctx->p.p_qp);
++
++		ctx->sh.i_num_ref_idx_l0_active = 1;
++		ctx->sh.i_num_ref_idx_l1_active = 1;
++	}
++
++	return 0;
++}
++
++#if 0
++void H264E_DumpInfo(_H264E_SliceInfo *s)
++{
++    printk(" emc_qpt_va              : %p\n",s->emc_qpt_va);
++    printk(" emc_rc_va               : %p\n",s->emc_rc_va);
++    printk(" emc_cpx_va              : %p\n",s->emc_cpx_va);
++    printk(" emc_mod_va              : %p\n",s->emc_mod_va);
++    printk(" emc_ncu_va              : %p\n",s->emc_ncu_va);
++    printk(" emc_sad_va              : %p\n",s->emc_sad_va);
++    printk(" mb_mode_info            : %p\n",s->mb_mode_info);
++
++    printk("s->des_va   = 0x%08x\n", (unsigned int)s->des_va);
++    printk("s->des_pa   = 0x%08x\n", (unsigned int)s->des_pa);
++    //	printk("s->emc_bs_va = 0x%08x\n", s->emc_bs_va);
++    printk("s->emc_bs_pa = 0x%08x\n", s->emc_bs_pa);
++
++    /*x2000 add*/
++    printk(" bs_head_en = %d\n", s->bs_head_en);
++    printk(" bs_head_va = 0x%08x\n", (unsigned int)s->bs_head_va);
++    printk(" bs_head_len = 0x%d\n", (unsigned int)s->bs_head_len);
++    printk(" bs_rbsp_en = %d\n", s->bs_rbsp_en);
++
++    printk(" stride[0]    = %d\n", s->stride[0]);
++    printk(" stride[1]    = %d\n", s->stride[1]);
++    printk(" state	= 0x%08x\n", (unsigned int)s->state);
++    printk(" raw[0]   = 0x%08x\n", s->raw[0]);
++    printk(" raw[1]   = 0x%08x\n", s->raw[1]);
++    printk(" raw[2]   = 0x%08x\n", s->raw[2]);
++    printk(" fb[0][0] = 0x%08x\n", s->fb[0][0]);
++    printk(" fb[0][1] = 0x%08x\n", s->fb[0][1]);
++    printk(" fb[1][0] = 0x%08x\n", s->fb[1][0]);
++    printk(" fb[1][1] = 0x%08x\n", s->fb[1][1]);
++    printk(" fb[2][0] = 0x%08x\n", s->fb[2][0]);
++    printk(" fb[2][1] = 0x%08x\n", s->fb[2][1]);
++    printk(" jh[0][0] = 0x%08x\n", s->jh[0][0]);
++    printk(" jh[0][1] = 0x%08x\n", s->jh[0][1]);
++    printk(" jh[1][0] = 0x%08x\n", s->jh[1][0]);
++    printk(" jh[1][1] = 0x%08x\n", s->jh[1][1]);
++    printk(" jh[2][0] = 0x%08x\n", s->jh[2][0]);
++    printk(" jh[2][1] = 0x%08x\n", s->jh[2][1]);
++    printk(" spe_y_addr = 0x%08x\n", s->spe_y_addr);
++    printk(" spe_c_addr = 0x%08x\n", s->spe_c_addr);
++    printk(" emc_recon_pa= 0x%08x\n", s->emc_recon_pa);
++    printk(" emc_qpt_pa  = 0x%08x\n", s->emc_qpt_pa);
++    printk(" emc_mv_pa   = 0x%08x\n", s->emc_mv_pa);
++    printk(" emc_se_pa   = 0x%08x\n", s->emc_se_pa);
++    printk(" emc_rc_pa   = 0x%08x\n", s->emc_rc_pa);
++    printk(" emc_cpx_pa  = 0x%08x\n", s->emc_cpx_pa);
++    printk(" emc_mod_pa  = 0x%08x\n", s->emc_mod_pa);
++    printk(" emc_ncu_pa  = 0x%08x\n", s->emc_ncu_pa);
++    printk(" emc_sad_pa  = 0x%08x\n", s->emc_sad_pa);
++    /* 1. rc output [11]*/
++    {
++        printk(" frame_type              : %d\n",s->frame_type);
++        printk(" mb_width                : %d\n",s->mb_width);
++        printk(" mb_height               : %d\n",s->mb_height);
++        printk(" frame_width             : %d\n",s->frame_width);
++        printk(" frame_height            : %d\n",s->frame_height);
++        printk(" first_mby               : %d\n",s->first_mby);
++        printk(" last_mby                : %d\n",s->last_mby);
++        printk(" qp                      : %d\n",s->qp);
++        printk(" base_qp                 : %d\n",s->base_qp);
++        printk(" max_qp                  : %d\n",s->max_qp);
++        printk(" min_qp                  : %d\n",s->min_qp);
++    }
++    /* 2. motion cfg [25]*/
++    {
++        printk(" frm_re[0]              : %d\n",s->frm_re[0]);
++        printk(" frm_re[1]              : %d\n",s->frm_re[1]);
++        printk(" frm_re[2]              : %d\n",s->frm_re[2]);
++        printk(" frm_re[3]              : %d\n",s->frm_re[3]);
++        printk(" pskip_en               : %d\n",s->pskip_en);
++        printk(" mref_en                : %d\n",s->mref_en);
++        printk(" scl                    : %d\n",s->scl);
++        printk(" hpel_en                : %d\n",s->hpel_en);
++        printk(" qpel_en                : %d\n",s->qpel_en);
++        printk(" ref_mode               : %d\n",s->ref_mode);
++        printk(" max_sech_step_i        : %d\n",s->max_sech_step_i);
++        printk(" max_mvrx_i             : %d\n",s->max_mvrx_i);
++        printk(" max_mvry_i             : %d\n",s->max_mvry_i);
++        printk(" lambda_scale_parameter : %d\n",s->lambda_scale_parameter);
++        printk(" fs_en                  : %d\n",s->fs_en);
++        printk(" fs_md                  : %d\n",s->fs_md);
++        printk(" fs_px                  : %d\n",s->fs_px);
++        printk(" fs_py                  : %d\n",s->fs_py);
++        printk(" fs_rx                  : %d\n",s->fs_rx);
++        printk(" fs_ry                  : %d\n",s->fs_ry);
++        printk(" frm_mv_en              : %d\n",s->frm_mv_en);
++        printk(" frm_mv_size            : %d\n",s->frm_mv_size);
++        printk(" glb_mv_en              : %d\n",s->glb_mv_en);
++        printk(" glb_mvx                : %d\n",s->glb_mvx);
++        printk(" glb_mvy                : %d\n",s->glb_mvy);
++        printk(" me_step_en             : %d\n",s->me_step_en);
++        printk(" me_step_0              : %d\n",s->me_step_0);
++        printk(" me_step_1              : %d\n",s->me_step_1);
++    }
++    /* 3. quant cfg [4]*/
++    {
++        int i=0,j=0;
++        printk(" dct8x8_en    : %d\n",s->dct8x8_en);
++        for (i=0;i<4;i++)
++            for (j=0;j<16;j++)
++                printk(" scaling_list[%d][%d] : %d\n",i,j,s->scaling_list[i][j]);
++        for (i=0;i<2;i++)
++            for (j=0;j<64;j++)
++                printk(" scaling_list8[%d][%d] : %d\n",i,j,s->scaling_list8[i][j]);
++        for (i=0;i<9;i++)
++            printk(" deadzone[%d] : %d\n",i,s->deadzone[i]);
++    }
++
++    /* 4. loop filter cfg [4]*/
++    {
++        printk(" deblock                : %d\n",s->deblock);
++        printk(" rotate                 : %d\n",s->rotate);
++        printk(" alpha_c0_offset        : %d\n",s->alpha_c0_offset);
++        printk(" beta_offset            : %d\n",s->beta_offset);
++    }
++    /* 5. do not douch, default value [56]*/
++    {
++        printk(" acmask_mode : %d\n",s->acmask_mode);
++        printk(" intra_mode_msk : %d\n",s->intra_mode_msk);
++        printk(" i_4x4_dis              : %d\n",s->i_4x4_dis);
++        printk(" i_8x8_dis              : %d\n",s->i_8x8_dis);
++        printk(" i_16x16_dis            : %d\n",s->i_16x16_dis);
++        printk(" p_l0_dis               : %d\n",s->p_l0_dis);
++        printk(" p_t8_dis               : %d\n",s->p_t8_dis);
++        printk(" p_skip_dis             : %d\n",s->p_skip_dis);
++        printk(" p_skip_pl0f_dis        : %d\n",s->p_skip_pl0f_dis);
++        printk(" p_skip_pt8f_dis        : %d\n",s->p_skip_pt8f_dis);
++
++        printk(" cost_bias_en           : %d\n",s->cost_bias_en);
++        printk(" cost_bias_i_4x4        : %d\n",s->cost_bias_i_4x4);
++        printk(" cost_bias_i_8x8        : %d\n",s->cost_bias_i_8x8);
++        printk(" cost_bias_i_16x16      : %d\n",s->cost_bias_i_16x16);
++        printk(" cost_bias_p_l0         : %d\n",s->cost_bias_p_l0);
++        printk(" cost_bias_p_t8         : %d\n",s->cost_bias_p_t8);
++        printk(" cost_bias_p_skip       : %d\n",s->cost_bias_p_skip);
++
++        printk(" intra_lambda_y_bias_en : %d\n",s->intra_lambda_y_bias_en);
++        printk(" intra_lambda_c_bias_en : %d\n",s->intra_lambda_c_bias_en);
++        printk(" intra_lambda_bias_qp0  : %d\n",s->intra_lambda_bias_qp0);
++        printk(" intra_lambda_bias_qp1  : %d\n",s->intra_lambda_bias_qp1);
++        printk(" intra_lambda_bias_0    : %d\n",s->intra_lambda_bias_0);
++        printk(" intra_lambda_bias_1    : %d\n",s->intra_lambda_bias_1);
++        printk(" intra_lambda_bias_2    : %d\n",s->intra_lambda_bias_2);
++
++        printk(" chroma_sse_bias_en     : %d\n",s->chroma_sse_bias_en);
++        printk(" chroma_sse_bias_qp0    : %d\n",s->chroma_sse_bias_qp0);
++        printk(" chroma_sse_bias_qp1    : %d\n",s->chroma_sse_bias_qp1);
++        printk(" chroma_sse_bias_0      : %d\n",s->chroma_sse_bias_0);
++        printk(" chroma_sse_bias_1      : %d\n",s->chroma_sse_bias_1);
++        printk(" chroma_sse_bias_2      : %d\n",s->chroma_sse_bias_2);
++
++        printk(" sse_lambda_bias_en     : %d\n",s->sse_lambda_bias_en);
++        printk(" sse_lambda_bias        : %d\n",s->sse_lambda_bias);
++        printk(" fbc_ep                 : %d\n",s->fbc_ep);
++        printk(" jm_lambda2_en          : %d\n",s->jm_lambda2_en);
++        printk(" inter_nei_en           : %d\n",s->inter_nei_en);
++        printk(" skip_bias_en           : %d\n",s->skip_bias_en);
++
++        printk(" ysse_thr               : %d\n",s->ysse_thr);
++        printk(" csse_thr               : %d\n",s->csse_thr);
++        printk(" dcm_en                 : %d\n",s->dcm_en);
++        printk(" dcm_param              : %d\n",s->dcm_param);
++        printk(" sde_prior              : %d\n",s->sde_prior);
++        printk(" db_prior               : %d\n",s->db_prior);
++
++        printk(" use_intra_in_pframe    : %d\n",s->use_intra_in_pframe);
++        printk(" use_fast_mvp           : %d\n",s->use_fast_mvp);
++        printk(" skip_en                : %d\n",s->skip_en);
++        printk(" cqp_offset             : %d\n",s->cqp_offset);
++
++        printk(" daisy_chain_en         : %d\n",s->daisy_chain_en);
++        printk(" curr_thread_id         : %d\n",s->curr_thread_id);
++        printk(" qp_tab_mode            : %d\n",s->qp_tab_mode);
++        printk(" bs_size_en             : %d\n",s-> bs_size_en);
++        printk(" bs_size                : %d\n",s->bs_size);
++        printk(" raw_format             : %d\n",s->raw_format);
++
++        printk(" size_mode              : %d\n",s->size_mode);
++        printk(" step_mode              : %d\n",s->step_mode);
++        printk(" mode_ctrl              : %d\n",s->mode_ctrl);
++        int i=0;
++        for (i=0;i<40;i++)
++            printk("mode_ctrl_param[%d] : %d\n",i,s->mode_ctrl_param[i]);
++
++    }
++    /* 6. select hardware output mode [11]*/
++    {
++        printk(" info_en                : %d\n",s->info_en);
++        printk(" mvd_sum_all            : %d\n",s->mvd_sum_all);
++        printk(" mvd_sum_abs            : %d\n",s->mvd_sum_abs);
++        printk(" mv_sum_all             : %d\n",s->mv_sum_all);
++        printk(" mv_sum_abs             : %d\n",s->mv_sum_abs);
++
++
++        printk(" cfg_size_x             : %d\n",s->cfg_size_x);
++        printk(" cfg_size_y             : %d\n",s->cfg_size_y);
++        printk(" cfg_iw_thr             : %d\n",s->cfg_iw_thr);
++
++        printk(" cfg_mvr_thr1           : %d\n",s->cfg_mvr_thr1);
++        printk(" cfg_mvr_thr2           : %d\n",s->cfg_mvr_thr2);
++        printk(" cfg_mvr_thr3           : %d\n",s->cfg_mvr_thr3);
++    }
++    /* 7. ipred bit&lambda ctrl [33]*/
++    {
++        printk(" mb_mode_val            : %d\n",s->mb_mode_val);
++        printk(" bit_16_en              : %d\n",s->bit_16_en);
++        printk(" bit_8_en               : %d\n",s->bit_8_en);
++        printk(" bit_4_en               : %d\n",s->bit_4_en);
++        printk(" bit_uv_en              : %d\n",s->bit_uv_en);
++        printk(" lamb_16_en             : %d\n",s->lamb_16_en);
++        printk(" lamb_8_en              : %d\n",s->lamb_8_en);
++        printk(" lamb_4_en              : %d\n",s->lamb_4_en);
++        printk(" lamb_uv_en             : %d\n",s->lamb_uv_en);
++        printk(" lamb_uv_en             : %d\n",s->c_16_en);
++        printk(" c_8_en                 : %d\n",s->c_8_en);
++        printk(" c_4_en                 : %d\n",s->c_4_en);
++        printk(" c_uv_en                : %d\n",s->c_uv_en);
++        printk(" pri_16                 : %d\n",s->pri_16);
++        printk(" pri_8                  : %d\n",s->pri_8);
++        printk(" pri_4                  : %d\n",s->pri_4);
++        printk(" pri_uv                 : %d\n",s->pri_uv);
++        printk(" ref_neb_4              : %d\n",s->ref_neb_4);
++        printk(" ref_neb_8              : %d\n",s->ref_neb_8);
++        printk(" lambda_info16          : %d\n",s->lambda_info16);
++        printk(" lambda_info8           : %d\n",s->lambda_info8);
++        printk(" lambda_info4           : %d\n",s->lambda_info4);
++        printk(" lambda_infouv          : %d\n",s->lambda_infouv);
++        printk(" ref_4                  : %d\n",s->ref_4);
++        printk(" ref_8                  : %d\n",s->ref_8);
++
++        int i=0;
++        for (i=0;i<4;i++)
++            printk(" bit_16[%d]             : %d\n",i,s->bit_16[i]);
++        for (i=0;i<4;i++)
++            printk(" bit_uv[%d]             : %d\n",i,s->bit_uv[i]);
++        for (i=0;i<4;i++)
++            printk(" bit_4[%d]              : %d\n",i,s->bit_4[i]);
++        for (i=0;i<4;i++)
++            printk(" bit_8[%d]              : %d\n",i,s->bit_8[i]);
++        for (i=0;i<4;i++)
++            printk(" const_16[%d]           : %d\n",i,s->const_16[i]);
++        for (i=0;i<4;i++)
++            printk(" const_uv[%d]           : %d\n",i,s->const_uv[i]);
++        for (i=0;i<4;i++)
++            printk(" const_4[%d]            : %d\n",i,s->const_4[i]);
++        for (i=0;i<4;i++)
++            printk(" const_8[%d]            : %d\n",i,s->const_8[i]);
++    }
++    /* 9. jrfc,jrfd [5]*/
++    {
++        printk(" jrfcd_flag              : %d\n",s->jrfcd_flag);
++        printk(" jrfc_enable             : %d\n",s->jrfc_enable);
++        printk(" jrfd_enable             : %d\n",s->jrfd_enable);
++        printk(" lm_head_total           : %d\n",s->lm_head_total);
++        printk(" cm_head_total           : %d\n",s->cm_head_total);
++    }
++    /* 10. eigen cfg for mosaic, color error [42]*/
++    {
++        printk(" mb_mode_use             : %d\n",s->mb_mode_use);
++        printk(" force_i16dc             : %d\n",s->force_i16dc);//ipred
++        printk(" force_i16               : %d\n",s->force_i16);
++        printk(" refresh_en              : %d\n",s->refresh_en);
++        printk(" refresh_mode            : %d\n",s->refresh_mode);
++        printk(" refresh_bias            : %d\n",s->refresh_bias);
++        printk(" refresh_cplx_thd        : %d\n",s->refresh_cplx_thd);
++        printk(" cplx_thd_sel            : %d\n",s->cplx_thd_sel);
++        printk(" diff_cplx_sel           : %d\n",s->diff_cplx_sel);
++        printk(" diff_thd_sel            : %d\n",s->diff_thd_sel);
++        printk(" i16dc_cplx_thd          : %d\n",s->i16dc_cplx_thd);
++        printk(" i16dc_qp_base           : %d\n",s->i16dc_qp_base);
++        printk(" i16dc_qp_sel            : %d\n",s->i16dc_qp_sel);
++        printk(" i16_qp_base             : %d\n",s->i16_qp_base);
++        printk(" i16_qp_sel              : %d\n",s->i16_qp_sel);
++        printk(" diff_cplx_thd           : %d\n",s->diff_cplx_thd);
++
++        int i=0;
++        for (i=0;i<2;i++)
++            printk(" diff_qp_base[%d]        : %d\n",i,s->diff_qp_base[i]);
++        for (i=0;i<2;i++)
++            printk(" diff_qp_sel[%d]         : %d\n",i,s->diff_qp_sel[i]);
++        for (i=0;i<24;i++)
++            printk(" cplx_thd_idx[%d]        : %d\n",i,s->cplx_thd_idx[i]);
++        for (i=0;i<8;i++)
++            printk(" cplx_thd[%d]            : %d\n",i,s->cplx_thd[i]);
++        for (i=0;i<3;i++)
++            printk(" diff_thd_base[%d]       : %d\n",i,s->diff_thd_base[i]);
++        for (i=0;i<3;i++)
++            printk(" diff_thd_ofst[%d]       : %d\n",i,s->diff_thd_ofst[i]);
++        printk(" sas_eigen_en            : %d\n",s->sas_eigen_en);
++        printk(" crp_eigen_en            : %d\n",s->crp_eigen_en);
++        printk(" sas_eigen_dump          : %d\n",s->sas_eigen_dump);
++        printk(" crp_eigen_dump          : %d\n",s->crp_eigen_dump);
++        printk(" rrs_en                  : %d\n",s->rrs_en);
++        printk(" rrs_dump_en             : %d\n",s->rrs_dump_en);
++        printk(" rrs_uv_en               : %d\n",s->rrs_uv_en);
++        printk(" rrs_size_y              : %d\n",s->rrs_size_y);
++        printk(" rrs_size_c              : %d\n",s->rrs_size_c);
++        printk(" rrs_thrd_y              : %d\n",s->rrs_thrd_y);
++        printk(" rrs_thrd_u              : %d\n",s->rrs_thrd_u);
++        printk(" rrs_thrd_v              : %d\n",s->rrs_thrd_v);
++    }
++    /* 11. skin judge cfg [14]*/
++    {
++        printk(" skin_dt_en              : %d\n",s->skin_dt_en);
++        printk(" skin_lvl                : %d\n",s->skin_lvl);
++        printk(" skin_cnt_thd            : %d\n",s->skin_cnt_thd);
++        printk(" ncu_mov_en              : %d\n",s->ncu_mov_en);
++        printk(" ncu_move_len            : %d\n",s->ncu_move_len);
++        if (s->ncu_move_info == NULL)
++            printk(" ncu_move_info is NULL \n");
++        else
++            printk(" ncu_move_info       : %p\n",s->ncu_move_info);
++        printk(" buf_share_en            : %d\n",s->buf_share_en);
++        printk(" buf_share_size          : %d\n",s->buf_share_size);
++        printk(" frame_idx               : %d\n",s->frame_idx);
++        printk(" is_first_Pframe         : %d\n",s->is_first_Pframe);
++        int i=0,j=0;
++        for (i=0;i<3;i++)
++            for (j=0;j<2;j++)
++                printk(" skin_pxlu_thd[%d][%d] : %d\n",i,j,s->skin_pxlu_thd[i][j]);
++        for (i=0;i<3;i++)
++            for (j=0;j<2;j++)
++                printk(" skin_pxlv_thd[%d][%d] : %d\n",i,j,s->skin_pxlv_thd[i][j]);
++        for (i=0;i<4;i++)
++            printk(" skin_qp_ofst[%d] : %d\n",i,s->skin_qp_ofst[i]);
++        for (i=0;i<3;i++)
++            printk(" mult_factor[%d] : %d\n",i,s->mult_factor[i]);
++        for (i=0;i<3;i++)
++            for (j=0;j<3;j++)
++                printk(" shift_factor[%d][%d] : %d\n",i,j,s->shift_factor[i][j]);
++        for (i=0;i<4;i++)
++            printk(" skin_ofst[%d] : %d\n",i,s->skin_ofst[i]);
++    }
++    /* 12.qpg */
++    {
++        /* qp map */
++        printk(" qp_tab_en               : %d\n",s->qp_tab_en);
++        printk(" qp_tab_len              : %d\n",s->qp_tab_len);
++        if (s->qp_tab == NULL)
++            printk(" qp_tab is NULL");
++        else
++            printk(" qp_tab : %p\n", s->qp_tab);
++        int i=0;
++        for (i=0;i<8;i++) {
++            printk("roi_en[%d]   : %d\n",i,s->roi_info[i].roi_en);
++            printk("roi_md[%d]   : %d\n",i,s->roi_info[i].roi_md);
++            printk("roi_qp[%d]   : %d\n",i,s->roi_info[i].roi_qp);
++            printk("roi_lmbx[%d] : %d\n",i,s->roi_info[i].roi_lmbx);
++            printk("roi_rmbx[%d] : %d\n",i,s->roi_info[i].roi_rmbx);
++            printk("roi_umby[%d] : %d\n",i,s->roi_info[i].roi_umby);
++            printk("roi_bmby[%d] : %d\n",i,s->roi_info[i].roi_bmby);
++        }
++        /* qp cplx */
++        printk(" sas_en                  : %d\n",s->sas_en);
++        printk(" crp_en                  : %d\n",s->crp_en);
++        printk(" sas_mthd                : %d\n",s->sas_mthd);
++        for (i=0;i<7;i++)
++            printk(" qpg_mb_thd[%d] : %d\n", i,s->qpg_mb_thd[i]);
++        for (i=0;i<8;i++)
++            printk(" qpg_mbqp_ofst[%d] : %d\n", i,s->qpg_mbqp_ofst[i]);
++        for (i=0;i<5;i++)
++            printk(" qpg_flt_thd[%d] : %d\n", i,s->qpg_flt_thd[i]);
++        printk(" mbrc_qpg_sel            : %d\n",s->mbrc_qpg_sel);
++        /* bu rc */
++        printk(" rc_mb_en                : %d\n",s->rc_mb_en);
++        printk(" rc_bu_wait_en           : %d\n",s->rc_bu_wait_en);
++        printk(" rc_mb_wait_en           : %d\n",s->rc_mb_wait_en);
++        printk(" rc_bu_num               : %d\n",s->rc_bu_num);
++        printk(" rc_bu_size              : %d\n",s->rc_bu_size);
++        printk(" rc_bu_level             : %d\n",s->rc_bu_level);
++        printk(" rc_mb_level             : %d\n",s->rc_mb_level);
++        if (s->mb_ref_info == NULL)
++            printk(" mb_ref_info is NULL");
++        else
++            printk(" mb_ref_info : %p\n", s->mb_ref_info);
++        if (s->bu_ref_info == NULL)
++            printk(" bu_ref_info is NULL");
++        else
++            printk(" bu_ref_info : %p\n", s->bu_ref_info);
++        printk(" rc_frm_tbs              : %d\n",s->rc_frm_tbs);
++        printk(" avg_bu_bs               : %d\n",s->avg_bu_bs);
++        for (i=0;i<6;i++)
++            printk(" tar_bs_thd[%d] : %d\n",s->tar_bs_thd[i]);
++        for (i=0;i<6;i++)
++            printk(" tar_bs_thd[%d] : %d\n",s->bu_alg0_qpo[i]);
++        for (i=0;i<6;i++)
++            printk(" bu_alg1_qpo[%d] : %d\n",s->bu_alg1_qpo[i]);
++        for (i=0;i<7;i++)
++            printk(" mb_cs_qpo[%d] : %d\n",s->mb_cs_qpo[i]);
++        for (i=0;i<2;i++)
++            printk(" mb_top_bs_qpo[%d] : %d\n",s->mb_top_bs_qpo[i]);
++        for (i=0;i<2;i++)
++            printk(" mb_rinfo_qpo[%d] : %d\n",s->mb_rinfo_qpo[i]);
++        for (i=0;i<2;i++)
++            printk(" mb_target_avg_bs[%d] : %d\n",s->mb_target_avg_bs[i]);
++        printk(" mb_gp_num               : %d\n",s->mb_gp_num);
++        printk(" last_bu_size            : %d\n",s->last_bu_size);
++        printk(" rc_bcfg_mode            : %d\n",s->rc_bcfg_mode);
++    }
++
++}
++#endif
++
++
++static int h264e_fill_slice_info(struct h264e_ctx *ctx, unsigned int sh_size_in_bits)
++{
++	int i = 0;
++	int ret = 0;
++	unsigned char bmap[3][3] = {
++		{0, 2, 1},
++		{1, 0, 2},
++		{2, 1, 0}
++	};
++
++	unsigned char *bufidx = bmap[ctx->i_frame % 3];
++	H264E_SliceInfo_t *s = ctx->s;
++
++
++	h264_sps_t *sps 	= &ctx->sps;
++	h264_pps_t *pps 	= &ctx->pps;
++
++	/* 1. rc output [11] */
++	{
++		s->mb_width 			= sps->i_mb_width;
++		s->mb_height 			= sps->i_mb_height;
++
++		s->frame_type 			= ctx->sh.i_type == M_SLICE_TYPE_I ? 0:1;
++		s->first_mby 			= 0;
++		s->last_mby 			= s->mb_height - 1;
++		s->frame_width 			= ctx->p.width;
++		s->frame_height 		= ctx->p.height;
++		s->qp				= ctx->sh.i_type == M_SLICE_TYPE_I ? ctx->p.i_qp : ctx->p.p_qp;
++		s->base_qp			= s->qp;
++		s->max_qp			= ctx->p.h264_max_qp;
++		s->min_qp			= ctx->p.h264_min_qp;
++
++
++		s->bs_head_en 			= 1;	/*X2000 new add, fix value*/
++		s->bs_head_va 			= (paddr_t *)ctx->slice_header;
++		s->bs_head_len 			= (sh_size_in_bits + 7) / 8;
++		s->bs_rbsp_en 			= 1;
++	}
++
++	/*2. motion cfg [25]*/
++	{
++		s->frm_re[0] 			= 0;/*sipe->frm_re0A;*/
++		s->frm_re[1] 			= 0;/*sipe->frm_re1A;*/
++		s->frm_re[2] 			= 0;/*sipe->frm_re2A;*/
++		s->frm_re[3] 			= 0;/*sipe->frm_re3A;*/
++
++		s->pskip_en               	= 1;
++		s->mref_en                	= 0;
++		s->scl                    	= 3;/*sipe->scl;*/
++		s->hpel_en                	= 1;/*sipe->hpel_en;*/
++		s->qpel_en                	= 1;/*sipe->qpel_en;*/
++		s->ref_mode               	= 1;
++		s->max_sech_step_i        	= 63;/*sipe->max_sech_step_i;*/
++		s->max_mvrx_i             	= 255;/*sipe->max_mvrx_i;*/          //FixMe, for the buf_share_size is 3 when bufshare function opened
++		s->max_mvry_i             	= 255;/*sipe->max_mvry_i;*/          //FixMe, for the buf_share_size is 3 when bufshare function opened
++		s->lambda_scale_parameter 	= 8;
++
++		if(s->mb_width > 50 && s->mb_height > 38) {
++			s->fs_en   			= 1;/*sipe->fs_en;*/
++			s->fs_md   			= 0;/*sipe->fs_md;*/
++			s->fs_px   			= 3;/*sipe->fs_px;*/
++			s->fs_py   			= 3;/*sipe->fs_py;*/
++			s->fs_rx   			= 8;/*sipe->fs_rx;*/
++			s->fs_ry   			= 8;/*sipe->fs_ry;*/
++		} else {
++			s->fs_en   			= 0;/*sipe->fs_en;*/
++			s->fs_md   			= 0;/*sipe->fs_md;*/
++			s->fs_px   			= 0;/*sipe->fs_px;*/
++			s->fs_py   			= 0;/*sipe->fs_py;*/
++			s->fs_rx   			= 0;/*sipe->fs_rx;*/
++			s->fs_ry   			= 0;/*sipe->fs_ry;*/
++		}
++
++		s->frm_mv_en   			= 1;/*sipe->frm_mv_en;*/
++		s->frm_mv_size 			= 3;/*sipe->frm_mv_size;*/
++		s->glb_mv_en   			= 1;/*sipe->glb_mv_en;*/
++#if 0
++		if((frm->mvCnt & 0xffff) == 0 || ((frm->mvCnt >> 16) & 0xffff) == 0) {
++			s->glb_mvx   		= 0;
++			s->glb_mvy   		= 0;
++		} else {
++			s->glb_mvx   		= frm->mvxSum / (frm->mvCnt & 0xffff);
++			s->glb_mvy   		= frm->mvySum / ((frm->mvCnt >> 16) & 0xffff);
++		}
++#endif
++		s->me_step_en 			= 1; /*sipe->me_step_en;*/
++		s->me_step_0  			= 8; /*sipe->me_step_0;*/
++		s->me_step_1  			= 10;/*sipe->me_step_1;*/
++	}
++
++	/*3. quant cfg [4]*/
++	{
++		s->dct8x8_en = 0;
++		memset(s->scaling_list, 0x10, sizeof(s->scaling_list));
++		memcpy(s->scaling_list8[0], cqm_8iy_tab, sizeof(uint8_t) * 64);
++		memcpy(s->scaling_list8[1], cqm_8py_tab, sizeof(uint8_t) * 64);
++
++		s->deadzone[0] = 0x15;
++		s->deadzone[1] = 0x0b;
++		s->deadzone[2] = 0x15;
++		s->deadzone[3] = 0x0b;
++		s->deadzone[4] = 0x15;
++		s->deadzone[5] = 0x0b;
++		s->deadzone[6] = 0x15;
++		s->deadzone[7] = 0x15;
++		s->deadzone[8] = 0x0b;
++	}
++
++	/*4.loop filter cfg [4] */
++	{
++		s->deblock 			= ctx->p.deblock;
++		s->rotate 			= 0;
++		s->alpha_c0_offset 		= 0;
++		s->beta_offset			= 0;
++	}
++
++	/*5.*/
++	{
++		s->acmask_mode             	= 0x3fffe; /*sipe->acmask_mode;*/
++		s->intra_mode_msk          	= 0;
++		s->i_4x4_dis               	= 0;
++		s->i_8x8_dis               	= 0;
++		s->i_16x16_dis             	= 0;
++		s->p_l0_dis                	= 0;
++		s->p_t8_dis                	= 0;
++		s->p_skip_dis              	= 0;
++		s->p_skip_pl0f_dis         	= 0;
++		s->p_skip_pt8f_dis         	= 0;
++
++		s->cost_bias_en            	= 0;
++		s->cost_bias_i_4x4         	= 0;
++		s->cost_bias_i_8x8         	= 0;
++		s->cost_bias_i_16x16       	= 0;
++		s->cost_bias_p_l0          	= 0;
++		s->cost_bias_p_t8          	= 0;
++		s->cost_bias_p_skip        	= 0;
++
++		s->intra_lambda_y_bias_en  	= 0;
++		s->intra_lambda_c_bias_en  	= 0;
++		s->intra_lambda_bias_qp0   	= 0;
++		s->intra_lambda_bias_qp1   	= 0;
++		s->intra_lambda_bias_0     	= 0;
++		s->intra_lambda_bias_1     	= 0;
++		s->intra_lambda_bias_2     	= 0;
++
++		s->chroma_sse_bias_en      	= 0;
++		s->chroma_sse_bias_qp0     	= 0;
++		s->chroma_sse_bias_qp1     	= 0;
++		s->chroma_sse_bias_0       	= 0;
++		s->chroma_sse_bias_1       	= 0;
++		s->chroma_sse_bias_2       	= 0;
++
++		s->sse_lambda_bias_en      	= 0;
++		s->sse_lambda_bias         	= 0;
++		s->fbc_ep                  	= 204;
++		s->jm_lambda2_en           	= 0; /*sipe->jm_lambda2_en;*/
++		s->inter_nei_en            	= 0; /*sipe->inter_nei_en;*/
++		s->skip_bias_en            	= 0; /*sipe->skip_bias_en;*/
++		s->ysse_thr                	= 0;
++		s->csse_thr                	= 0;
++		s->dcm_en                  	= 0; /*sipe->dcm_en;*/
++		s->dcm_param               	= 0x4304; /*sipe->dcm_param;*/
++		s->sde_prior               	= 5;
++		s->db_prior                	= 5;
++
++		s->use_intra_in_pframe     	= 1;/*sipe->use_intra_in_pframe;*/
++		s->use_fast_mvp            	= 1;
++
++		s->skip_en                 	= 1;
++		s->cqp_offset              	= 0;/*sipe->cqp_offset;*/
++
++		s->daisy_chain_en          	= 0;
++		s->curr_thread_id          	= 0;
++		s->qp_tab_mode             	= 0;
++
++		s->bs_size_en              	= 1;
++		s->bs_size                 	= 1024;
++		s->raw_format              	= 8;
++		s->size_mode               	= 0;
++		s->step_mode               	= 0;
++		s->mode_ctrl               	= 0;
++
++		memset(s->mode_ctrl_param,  0, sizeof(s->mode_ctrl_param));
++
++	}
++
++	/* 6. select hardware output mode [11]*/
++	{
++		s->info_en      		= 1;
++		s->mvd_sum_all  		= 0;
++		s->mvd_sum_abs  		= 0;
++		s->mv_sum_all   		= 1;
++		s->mv_sum_abs   		= 1;
++
++		s->cfg_size_x   		= 1;
++		s->cfg_size_y   		= 1;
++		s->cfg_iw_thr   		= 0;
++
++		s->cfg_mvr_thr1 		= 0;
++		s->cfg_mvr_thr2 		= 0;
++		s->cfg_mvr_thr3 		= 0;
++	}
++
++	/* 7. ipred bit&lambda ctrl [33]*/
++	{
++		s->mb_mode_val   		= 1;
++		s->bit_16_en     		= 0;
++		s->bit_8_en      		= 1;
++		s->bit_4_en      		= 1;
++		s->bit_uv_en     		= 0;
++		s->lamb_16_en    		= 0;
++		s->lamb_8_en     		= 0;
++		s->lamb_4_en     		= 0;
++		s->lamb_uv_en    		= 0;
++		s->c_16_en       		= 0;
++		s->c_8_en        		= 0;
++		s->c_4_en        		= 0;
++		s->c_uv_en       		= 0;
++		s->pri_16        		= 0;
++		s->pri_8         		= 0;
++		s->pri_4         		= 0;
++		s->pri_uv        		= 0;
++		s->ref_neb_4     		= 1;
++		s->ref_neb_8     		= 1;
++		s->lambda_info16 		= 0;
++		s->lambda_info8  		= 0;
++		s->lambda_info4  		= 0;
++		s->lambda_infouv 		= 0;
++		s->ref_4         		= 4;
++		s->ref_8         		= 3;
++		memset(s->bit_16,   0,  sizeof(s->bit_16));
++		memset(s->bit_uv,   0,  sizeof(s->bit_uv));
++		for (i = 0; i < 4; ++i)
++			s->bit_4[i] = 4;
++		for (i = 0; i < 4; ++i)
++			s->bit_8[i] = 4;
++		memset(s->const_16, 0,  sizeof(s->const_16));
++		memset(s->const_uv, 0,  sizeof(s->const_uv));
++		memset(s->const_4,  0,  sizeof(s->const_4));
++		memset(s->const_8,  0,  sizeof(s->const_8));
++	}
++
++
++	/* 9. jrfc,jrfd [5]*/
++	{
++		s->jrfcd_flag = 0;
++		s->jrfc_enable = 0;
++		s->jrfd_enable = 0;
++		s->lm_head_total = ((ctx->p.width+31) >> 5) * ((ctx->p.height+15) >> 4);
++		s->cm_head_total = ((ctx->p.width+63) >> 6) * ((ctx->p.height+15) >> 4);
++	}
++
++
++	/* 10. eigen cfg for mosaic, color error [42]*/
++	{
++		//x264_sinfo_eigenValue_cfg(rc,p,s);
++	}
++
++	/*11. skin judge cfg[14]*/
++	{
++		/*TODO.*/
++		s->skin_dt_en     = 0; //sipe->skin_dt_en;
++		s->skin_lvl       = 0; //sipe->skin_lvl;
++		s->skin_cnt_thd   = 20; //sipe->skin_cnt_thd;
++		s->ncu_mov_en     = 0;
++		s->ncu_move_len   = 20;
++		s->ncu_move_info  = NULL;
++		s->buf_share_en   = 0;
++		s->buf_share_size = 0;
++		s->frame_idx      = 0;
++		//s->is_first_Pframe = 0;
++
++		memcpy(s->skin_pxlu_thd, rc_skin_pxlu_thd, sizeof(s->skin_pxlu_thd));
++		memcpy(s->skin_pxlv_thd, rc_skin_pxlv_thd, sizeof(s->skin_pxlv_thd));
++		memcpy(s->skin_qp_ofst,  rc_skin_qp_ofst,  sizeof(s->skin_qp_ofst));
++		memcpy(s->mult_factor,   rc_mult_factor,   sizeof(s->mult_factor));
++		memcpy(s->shift_factor,  rc_shift_factor,  sizeof(s->shift_factor));
++		memcpy(s->skin_ofst,     rc_skin_ofst,     sizeof(s->skin_ofst));
++	}
++
++	/* 12.qpg */
++	{
++		//h264_get_mb_qp(p,s);
++	}
++
++	s->state 		= ctx->cb.state;
++	s->raw_format 		= ctx->p.format;
++
++	s->stride[0] 		= s->frame_width;
++	s->stride[1]		= s->raw_format == HELIX_420P_MODE ?
++				  s->frame_width / 2 : s->frame_width;
++	for(i = 0; i < ctx->frame->num_planes; i++) {
++		s->raw[i] = ctx->frame->fb_addr[i].pa;
++	}
++
++	for(i = 0; i < 3; i++) {
++		s->fb[i][0] = ctx->fb[bufidx[i]].yaddr_pa;
++		s->fb[i][1] = ctx->fb[bufidx[i]].caddr_pa;
++	}
++
++	s->des_va 	= ctx->desc;
++	s->des_pa 	= ctx->desc_pa;
++
++	s->emc_bs_pa = ctx->bs->pa;
++
++	s->emc_dblk_va 	= ctx->emc_buf;
++	s->emc_recon_va = s->emc_dblk_va + DBLK_SIZE;
++	s->emc_mv_va 	= s->emc_recon_va + RECON_SIZE;
++	s->emc_se_va 	= s->emc_mv_va + MV_SIZE;
++	s->emc_qpt_va 	= s->emc_se_va + SE_SIZE;
++	s->emc_rc_va 	= s->emc_qpt_va + QPT_SIZE;
++	s->emc_cpx_va 	= s->emc_rc_va + RC_SIZE;
++	s->emc_mod_va 	= s->emc_cpx_va + CPX_SIZE;
++	s->emc_sad_va 	= s->emc_mod_va + MOD_SIZE;
++	s->emc_ncu_va 	= s->emc_sad_va + SAD_SIZE;
++
++	s->emc_dblk_pa 	= ctx->emc_buf_pa;
++	s->emc_recon_pa = s->emc_dblk_pa + DBLK_SIZE;
++	s->emc_mv_pa 	= s->emc_recon_pa + RECON_SIZE;
++	s->emc_se_pa 	= s->emc_mv_pa + MV_SIZE;
++	s->emc_qpt_pa 	= s->emc_se_pa + SE_SIZE;
++	s->emc_rc_pa 	= s->emc_qpt_pa + QPT_SIZE;
++	s->emc_cpx_pa 	= s->emc_rc_pa + RC_SIZE;
++	s->emc_mod_pa 	= s->emc_cpx_pa + CPX_SIZE;
++	s->emc_sad_pa 	= s->emc_mod_pa + MOD_SIZE;
++	s->emc_ncu_pa 	= s->emc_sad_pa + SAD_SIZE;
++
++
++	H264E_SliceInit(s);
++//	H264E_DumpInfo(s);
++
++	dma_cache_sync(NULL, ctx->desc, ctx->vdma_chain_len, DMA_TO_DEVICE);
++
++	return ret;
++}
++
++static int h264e_encode_slice(struct h264e_ctx *ctx, int force_idr, int *keyframe)
++{
++	int idr = 0;
++	int i_nal_type = 0;
++	int i_nal_ref_idc = 0;
++	bs_t bs;
++	int ret = 0;
++	unsigned int encoded_header_size = 0;
++
++	/*decide I/P Frame*/
++	if(!(ctx->i_frame % ctx->p.gop_size) || force_idr) {
++		ctx->i_frame = 0;
++		idr = 1;
++	}
++
++	/* only I/P support.*/
++	if(idr) {
++		i_nal_type = NAL_SLICE_IDR;
++		i_nal_ref_idc = NAL_PRIORITY_HIGHEST;
++		ctx->sh.i_type = M_SLICE_TYPE_I;
++		*keyframe = 1;
++	} else {
++		i_nal_type = NAL_SLICE;
++		i_nal_ref_idc = NAL_PRIORITY_HIGH;
++		ctx->sh.i_type = M_SLICE_TYPE_P;
++		*keyframe = 0;
++	}
++
++	if(*keyframe && add_sps_pps_iframe) {
++		/* insert sps/pps.*/
++		encoded_header_size = h264e_encode_headers(ctx, ctx->bs);
++		ctx->bs->va += encoded_header_size;
++		ctx->bs->pa += encoded_header_size;
++	}
++
++	bs_init(&bs, ctx->slice_header, MAX_SLICE_HEADER_SIZE);
++
++	ret = h264e_slice_init(ctx, i_nal_type);
++	if(ret < 0)
++		return ret;
++
++	/*1. nal_header*/
++	bs_write(&bs, 8, 0x00);
++	bs_write(&bs, 8, 0xFF);
++	bs_write(&bs, 8, 0x00);
++	bs_write(&bs, 8, 0x01);
++	/* nal header */
++	bs_write(&bs, 8, (0 << 7 | (i_nal_ref_idc << 5) | (i_nal_type)));
++
++	/*2. slice_header, */
++	h264e_slice_header_write(&bs, &ctx->sh, i_nal_ref_idc);
++
++
++	if(ctx->p.i_cabac) {
++		bs_align_1(&bs);
++		h264_cabac_context_init(&ctx->cb, ctx->sh.i_type, ctx->sh.i_qp_delta, ctx->sh.i_cabac_init_idc);
++	}
++
++	unsigned int slice_header_size = bs_pos(&bs);
++	unsigned int slice_header_len = (slice_header_size + 7) / 8;
++	h264e_fill_slice_info(ctx, slice_header_size);
++
++	//print_hex_dump(KERN_INFO, "sl_header@", DUMP_PREFIX_ADDRESS, 16, 1, ctx->slice_header, 64, 1);
++
++	ret = ingenic_vpu_start(ctx->priv);
++	if(ret < 0) {
++		return ret;
++	}
++
++	//print_hex_dump(KERN_INFO, "bs@", DUMP_PREFIX_ADDRESS, 16, 1, ctx->bs->va, ctx->r_bs_len, 1);
++
++	ctx->encoded_bs_len = encoded_header_size + ctx->r_bs_len + ctx->r_rbsp_len + slice_header_len;
++
++	unsigned char *xp = (unsigned char *)((unsigned long)ctx->bs->va | 0xa0000000);
++	xp[0] = 0x00;
++	xp[1] = 0x00;
++	xp[2] = 0x00;
++
++	//printk("-----------%s, %d, vpu ctx->r_bs_len: %d, ctx->r_rbsp_len: %d, ctx->encoded_bs_len: %d\n", __func__, __LINE__, ctx->r_bs_len, ctx->r_rbsp_len, ctx->encoded_bs_len);
++
++	ctx->i_frame++;
++	ctx->frameindex++;
++
++	return ret;
++}
++
++/* add 0xff nal .*/
++static int h264e_filler_nal(int size, char *p)
++{
++        if (size < 6)
++                return -EINVAL;
++
++        p[0] = 0x00;
++        p[1] = 0x00;
++        p[2] = 0x00;
++        p[3] = 0x01;
++        p[4] = 0x0c;
++        memset(p + 5, 0xff, size - 6);
++        /* Add rbsp stop bit and trailing at the end */
++        p[size - 1] = 0x80;
++
++        return 0;
++}
++
++static int h264e_padding(int size, char *p)
++{
++	int ret = 0;
++
++	if(size == 0)
++		return 0;
++
++        ret = h264e_filler_nal(size, p);
++	if(ret < 0)
++		return ret;
++
++        return size;
++}
++
++int h264e_encode_headers(struct h264e_ctx *ctx, struct ingenic_vcodec_mem *bs)
++{
++	int ret = 0;
++	unsigned int align = 0;
++
++	if(ctx->encoded_bs_len != 0) {
++		pr_info("set encoded_bs_len to 0 before encode!\n");
++	}
++
++	memcpy(bs->va, ctx->bs_header, ctx->bs_header_size);
++
++	if(ctx->p.h264_hdr_mode == V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME) {
++
++		/*align to 256*/
++		align = (ctx->bs_header_size + 255) / 256 * 256;
++
++		ret = h264e_padding(align - ctx->bs_header_size, bs->va + ctx->bs_header_size);
++		ctx->encoded_bs_len = align;
++	} else {
++		ctx->encoded_bs_len = ctx->bs_header_size;
++	}
++
++	ret = ctx->encoded_bs_len;
++
++	return ret;
++}
++
++int h264e_encode(struct h264e_ctx *ctx, struct video_frame_buffer *frame,
++		struct ingenic_vcodec_mem *bs, int force_idr, int *keyframe)
++{
++	int ret = 0;
++	ctx->frame = frame;
++	ctx->bs = bs;
++
++	ret = h264e_encode_slice(ctx, force_idr, keyframe);
++
++	/* output bistream */
++
++	return ret;
++}
++
++
++
++/* start streaming.*/
++int h264e_alloc_workbuf(struct h264e_ctx *ctx)
++{
++	struct ingenic_venc_ctx *venc_ctx = ctx->priv;
++	int allocate_fb = 0;
++	int ret = 0;
++	int i = 0;
++
++	ctx->bs_header = kzalloc(MAX_BS_HEADER_SIZE, GFP_KERNEL);
++	if(!ctx->bs_header) {
++		pr_err("Failed to alloc memory for bs_header\n");
++		return -ENOMEM;
++	}
++	ctx->bs_header_size = 0;
++
++
++	ctx->desc = dma_alloc_noncoherent(venc_ctx->dev->dev, ctx->vdma_chain_len, &ctx->desc_pa, GFP_KERNEL);
++	if(!ctx->desc) {
++		pr_err("Failed to alloc vpu desc buffer!\n");
++		ret = -ENOMEM;
++		goto err_desc;
++	}
++
++
++	/* init yaddr. */
++	for(i = 0; i < 3; i++) {
++		ctx->fb[i].yaddr = NULL;
++		ctx->fb[i].caddr = NULL;
++	}
++
++	for(i = 0; i < 3; i++) {
++		ctx->fb[i].yaddr = dma_alloc_coherent(venc_ctx->dev->dev, ctx->framesize, &ctx->fb[i].yaddr_pa, GFP_KERNEL);
++		ctx->fb[i].caddr = dma_alloc_coherent(venc_ctx->dev->dev, ctx->framesize/2, &ctx->fb[i].caddr_pa, GFP_KERNEL);
++
++		allocate_fb = i;
++		if(!ctx->fb[i].yaddr || !ctx->fb[i].caddr) {
++			ret = -ENOMEM;
++			goto err_fb;
++		}
++	}
++
++	ctx->emc_buf = dma_alloc_coherent(venc_ctx->dev->dev, EMC_SIZE, &ctx->emc_buf_pa, GFP_KERNEL);
++	if(!ctx->emc_buf) {
++		pr_err("Failed to alloc vpu emc_buf!\n");
++		ret = -ENOMEM;
++		goto err_emc_buf;
++	}
++
++	return ret;
++
++err_emc_buf:
++err_fb:
++	for(i = 0; i < 3; i++) {
++		if(ctx->fb[i].yaddr) {
++			dma_free_coherent(venc_ctx->dev->dev, ctx->framesize, ctx->fb[i].yaddr, ctx->fb[i].yaddr_pa);
++		}
++		if(ctx->fb[i].caddr) {
++			dma_free_coherent(venc_ctx->dev->dev, ctx->framesize/2, ctx->fb[i].caddr, ctx->fb[i].caddr_pa);
++		}
++
++	}
++
++	dma_free_noncoherent(venc_ctx->dev->dev, ctx->vdma_chain_len, ctx->desc, ctx->desc_pa);
++err_desc:
++	kfree(ctx->bs_header);
++	ctx->bs_header = NULL;
++
++	return ret;
++}
++
++/* stop streaming.*/
++int h264e_free_workbuf(struct h264e_ctx *ctx)
++{
++	struct ingenic_venc_ctx *venc_ctx = ctx->priv;
++	int i;
++
++	if(ctx->bs_header) {
++		kfree(ctx->bs_header);
++		ctx->bs_header = NULL;
++	}
++	dma_free_noncoherent(venc_ctx->dev->dev, ctx->vdma_chain_len, ctx->desc, ctx->desc_pa);
++	dma_free_coherent(venc_ctx->dev->dev, EMC_SIZE, ctx->emc_buf, ctx->emc_buf_pa);
++
++	for(i = 0; i < 3; i++) {
++		dma_free_coherent(venc_ctx->dev->dev, ctx->framesize, ctx->fb[i].yaddr, ctx->fb[i].yaddr_pa);
++		dma_free_coherent(venc_ctx->dev->dev, ctx->framesize/2, ctx->fb[i].caddr, ctx->fb[i].caddr_pa);
++	}
++	return 0;
++}
++
++int h264e_encoder_init(struct h264e_ctx *ctx)
++{
++	struct h264e_params *p = NULL;
++	H264E_SliceInfo_t *s = NULL;
++
++	s = kzalloc(sizeof(H264E_SliceInfo_t), GFP_KERNEL);
++	if(!s) {
++		return -ENOMEM;
++	}
++
++	p = &ctx->p;
++	ctx->s = s;
++
++	ctx->vdma_chain_len 	= 40960 + 256;
++	ctx->frameindex		= 0;
++	ctx->i_frame		= 0;
++
++	p->height		= 240;
++	p->width		= 160;
++	p->max_ref_pic		= 1;
++	p->gop_size		= 50;
++	p->i_idr_pic_id		= 0;
++	p->i_global_qp 		= 30;
++	p->h264_profile		= V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE;
++	p->h264_level		= V4L2_MPEG_VIDEO_H264_LEVEL_1_0;
++	p->i_cabac		= 1;
++	p->interlaced		= 0;
++	p->h264_8x8_transform	= 0;
++	p->h264_hdr_mode	= V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME;
++	p->h264_min_qp		= 0;
++	p->h264_max_qp		= 51;
++	p->i_qp			= 30;
++	p->p_qp			= 30;
++	p->deblock		= 0;
++
++	h264_cabac_init();
++
++	return 0;
++}
++
++int h264e_encoder_deinit(struct h264e_ctx *ctx)
++{
++	if(!ctx)
++		return 0;
++
++	if(ctx->s)
++		kfree(ctx->s);
++	return 0;
++}
++
++void h264e_set_priv(struct h264e_ctx *ctx, void *data)
++{
++	ctx->priv = data;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e.h
+new file mode 100644
+index 000000000..8dbec650c
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e.h
+@@ -0,0 +1,134 @@
++#ifndef __H264E_H__
++#define __H264E_H__
++
++#include "api/helix_x264_enc.h"
++
++#include "h264enc/common.h"
++#include "helix_buf.h"
++
++/**
++* @bitrate, set by V4L2_CID_MPEG_VIDEO_BITRATE.
++* @gop_size, group of picture when h264 encoding.
++*/
++struct h264e_params {
++
++	/* params modify by s_ctrl*/
++	uint32_t bitrate;
++	uint32_t framerate;
++	int h264_hdr_mode;
++#if 0
++	uint8_t h264_intra_qp;
++	uint8_t h264_inter_qp;
++#endif
++	uint8_t	i_qp;
++	uint8_t p_qp;
++	uint8_t h264_min_qp;
++	uint8_t h264_max_qp;
++	uint8_t h264_profile;
++	uint8_t h264_level;
++	uint8_t gop_size;
++	uint8_t frame_rc_enable;
++	uint8_t mb_rc_enable;
++	uint8_t num_bframe;
++	uint8_t interlaced;
++	uint8_t max_ref_pic;
++	uint8_t h264_8x8_transform;
++
++	uint8_t i_cabac; /*is cabac entropy?*/
++
++	int i_idr_pic_id;
++	int i_global_qp;
++
++	uint8_t deblock;
++
++
++
++	int height;
++	int width;
++	int format;
++
++};
++
++
++#define MAX_BS_HEADER_SIZE	1024	/* maybe enough for header only.*/
++#define MAX_SLICE_HEADER_SIZE	128	/* 128bytes of slice header bs.*/
++
++struct h264e_ctx {
++	unsigned char *bs_header; /* buffer to store sps/pps/sei headers. */
++	unsigned int bs_header_size;	/* buffer size. */
++
++	unsigned char slice_header[128]; /*store slice buffer.*/
++
++	int vdma_chain_len;
++	unsigned int framesize;
++	/*根�height,width分�的,*/
++	struct  h264_ref_tile fb[3]; /*�考body buffer.按frame申请*/
++	struct  h264_ref_tile jh[3]; /*�考header buffer.按frame申请*/
++
++	unsigned int *emc_buf;	    /* 128KBytes固定空间*/
++	dma_addr_t emc_buf_pa;
++
++	unsigned int *desc;	    /* descriptor, 40960+256, 固定大�*/
++	dma_addr_t desc_pa;
++
++
++	struct video_frame_buffer *frame; /* input picture frame. */
++	struct ingenic_vcodec_mem *bs; /* output slice data. exclude slice header? */
++	struct ingenic_vcodec_mem bs_tmp_buf; /* temperary buf for now., used to store vpu output buffer. then memory cp to userspace. */
++
++	unsigned int src_crc;	/*Debug*/
++
++
++	h264_sps_t sps;
++	h264_pps_t pps;
++	h264_slice_header_t sh;
++	h264_cabac_t cb;	/*cabac state*/
++
++	int i_frame;	/* (i_frame + 1) % gop_size */
++
++	/* modify after encode frame*/
++	unsigned long frameindex;
++	unsigned int status;
++	unsigned int r_bs_len;		/*result bs len.*/
++	unsigned int r_rbsp_len; 	/*0x03 的个数.*/
++	unsigned int encoded_bs_len;	/* encoded bs_len */
++
++	struct h264e_params p;
++	H264E_SliceInfo_t *s;
++
++	void *priv;
++};
++
++#define EMC_SIZE        (1<<19)
++#define DBLK_SIZE       (0)
++#define RECON_SIZE      (0)
++#define MV_SIZE         (1 << 11)
++#define SE_SIZE         (1 << 11)
++#define QPT_SIZE        (1<<14)
++#define RC_SIZE         (1<<15)
++#define CPX_SIZE        (1<<17)
++#define MOD_SIZE        (1<<15)
++#define SAD_SIZE        (1<<17)
++#define ENCU_SIZE        (1<<13)
++#define BEYOND_MAX_SIZE 64*3
++
++
++
++extern int h264e_generate_headers(struct h264e_ctx *ctx);
++
++extern int h264e_encode_headers(struct h264e_ctx *ctx, struct ingenic_vcodec_mem *bs);
++
++extern int h264e_encode(struct h264e_ctx *ctx, struct video_frame_buffer *frame, struct ingenic_vcodec_mem *bs, int force_idr, int *keyframe);
++
++extern int h264e_set_fmt(struct h264e_ctx *ctx, int width, int height, int format);
++extern int h264e_alloc_workbuf(struct h264e_ctx *ctx);
++
++extern int h264e_free_workbuf(struct h264e_ctx *ctx);
++
++extern int h264e_encoder_init(struct h264e_ctx *ctx);
++
++extern int h264e_encoder_deinit(struct h264e_ctx *ctx);
++
++extern void h264e_set_priv(struct h264e_ctx *ctx, void *data);
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e_rc.c b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e_rc.c
+new file mode 100644
+index 000000000..da25a5d31
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e_rc.c
+@@ -0,0 +1,664 @@
++/*
++* Copyright© 2014 Ingenic Semiconductor Co.,Ltd
++*
++* Author: qipengzhen <aric.pzqi@ingenic.com>
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License version 2 as
++* published by the Free Software Foundation.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++* GNU General Public License for more details.
++*
++*/
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <media/v4l2-mem2mem.h>
++#include <linux/netlink.h>
++#include <net/sock.h>
++
++#include "api/helix_x264_enc.h"
++#include "h264enc/common.h"
++#include "h264enc/set.h"
++#include "h264e_rc_nl.h"
++#include "h264e_rc.h"
++#include "helix_drv.h"
++
++static unsigned add_sps_pps_iframe = 1;
++module_param(add_sps_pps_iframe, uint, S_IRUGO | S_IWUSR);
++
++#define MAX_REF_FRAMES	1
++#define NUM_WORK_BUFFERS (MAX_REF_FRAMES + 1)
++
++#if NUM_WORK_BUFFERS > 2
++
++#error "Multi refrence encoding not support Yet, NUM_WORK_BUFFERS should be 2."
++
++#endif
++
++/*TODO: export to high level ????*/
++int h264e_set_params(struct h264e_ctx *ctx, unsigned id, unsigned int val)
++{
++	int ret = 0;
++
++
++	return ret;
++}
++
++int h264e_get_params(struct h264e_ctx *ctx, int id)
++{
++	unsigned int val = 0;
++
++	return val;
++}
++
++int h264e_set_fmt(struct h264e_ctx *ctx, int width, int height, int format)
++{
++	struct h264e_params *p = &ctx->p;
++	unsigned int align_w = width;
++	unsigned int align_h = height;
++
++	int ret = 0;
++
++
++	p->width = width;
++	p->height = height;
++	switch(format) {
++		case HELIX_NV12_MODE:
++		case HELIX_NV21_MODE:
++		case HELIX_TILE_MODE:
++		case HELIX_420P_MODE:
++			p->format = format;
++			break;
++		default:
++			pr_err("Unsupported pix fmt: %x\n", format);
++			ret = -EINVAL;
++			break;
++	}
++
++	align_w = ALIGN(width, 16);
++	align_h = ALIGN(height, 16);
++
++	ctx->framesize = align_w * align_h;
++
++	h264e_nl_rc_video_cfg(ctx, &ctx->p);
++
++	return ret;
++}
++
++//to profile_idc
++static int __maybe_unused v4l2_profile(int i_profile_idc)
++{
++	switch (i_profile_idc) {
++		case PROFILE_BASELINE:           return V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE;
++		case PROFILE_MAIN:               return V4L2_MPEG_VIDEO_H264_PROFILE_MAIN;
++		case PROFILE_HIGH10:             return V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10;
++		case PROFILE_HIGH422:            return V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422;
++		case PROFILE_HIGH444_PREDICTIVE: return V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE;
++		default: return -EINVAL;
++	}
++
++}
++
++static int __maybe_unused h264e_profile_idc(int v4l2_profile)
++{
++	switch (v4l2_profile) {
++		case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE: 		return PROFILE_BASELINE;
++		case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN: 		return PROFILE_MAIN;
++		case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10: 		return PROFILE_HIGH10;
++		case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422: 		return PROFILE_HIGH422;
++		case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE: 	return PROFILE_HIGH444_PREDICTIVE;
++		default: return -EINVAL;
++	}
++}
++
++static int __maybe_unused v4l2_h264_level(int i_level_idc)
++{
++	switch (i_level_idc) {
++		case 10: return V4L2_MPEG_VIDEO_H264_LEVEL_1_0;
++		case 9:  return V4L2_MPEG_VIDEO_H264_LEVEL_1B;
++		case 11: return V4L2_MPEG_VIDEO_H264_LEVEL_1_1;
++		case 12: return V4L2_MPEG_VIDEO_H264_LEVEL_1_2;
++		case 13: return V4L2_MPEG_VIDEO_H264_LEVEL_1_3;
++		case 20: return V4L2_MPEG_VIDEO_H264_LEVEL_2_0;
++		case 21: return V4L2_MPEG_VIDEO_H264_LEVEL_2_1;
++		case 22: return V4L2_MPEG_VIDEO_H264_LEVEL_2_2;
++		case 30: return V4L2_MPEG_VIDEO_H264_LEVEL_3_0;
++		case 31: return V4L2_MPEG_VIDEO_H264_LEVEL_3_1;
++		case 32: return V4L2_MPEG_VIDEO_H264_LEVEL_3_2;
++		case 40: return V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
++		case 41: return V4L2_MPEG_VIDEO_H264_LEVEL_4_1;
++		default: return -EINVAL;
++	}
++}
++
++static int h264e_level_idc(int level)
++{
++	switch (level) {
++		case V4L2_MPEG_VIDEO_H264_LEVEL_1_0: return 10;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_1B:  return 9;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_1_1: return 11;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_1_2: return 12;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_1_3: return 13;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_2_0: return 20;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_2_1: return 21;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_2_2: return 22;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_3_0: return 30;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_3_1: return 31;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_3_2: return 32;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_4_0: return 40;
++		case V4L2_MPEG_VIDEO_H264_LEVEL_4_1: return 41;
++		default: return -EINVAL;
++	}
++}
++
++/* ----------------------------- Picture Parameter Sets ---------------*/
++static void h264e_sps_init(struct h264e_ctx *ctx, h264_sps_t *sps, int i_id)
++{
++	struct h264e_params *p = &ctx->p;
++	int max_frame_num = 1;
++
++	sps->i_id 			= i_id;
++	sps->i_mb_width 		= C_ALIGN(p->width, 16) / 16;
++	sps->i_mb_height 		= C_ALIGN(p->height, 16) / 16;
++	sps->i_chroma_format_idc 	= CHROMA_420;
++	sps->b_qpprime_y_zero_transform_bypass = 0;
++	sps->i_profile_idc 		= h264e_profile_idc(p->h264_profile);
++	sps->b_constraint_set0 		= sps->i_profile_idc == PROFILE_BASELINE;
++	sps->b_constraint_set1 		=  sps->i_profile_idc <= PROFILE_MAIN;
++	sps->b_constraint_set2 		= 0;
++	sps->b_constraint_set3 		= 0;
++
++	sps->i_level_idc 		= h264e_level_idc(p->h264_level);
++	if((sps->i_level_idc == 9) && (sps->i_profile_idc == PROFILE_BASELINE || sps->i_profile_idc == PROFILE_MAIN)) {
++		sps->b_constraint_set0 	= 1; /* level 1b with Baseline or Main profile is signalled via constraint_set3 */
++		sps->i_level_idc 	= 11;
++	}
++
++
++	sps->i_num_ref_frames 		= p->max_ref_pic;
++	sps->vui.i_num_reorder_frames 	= 0;
++	sps->vui.i_max_dec_frame_buffering = sps->i_num_ref_frames;
++
++	sps->i_log2_max_frame_num 	= 4;
++	while((1 << sps->i_log2_max_frame_num) <= max_frame_num)
++		sps->i_log2_max_frame_num++;
++
++	sps->i_poc_type = 2;
++
++	if(sps->i_poc_type == 0) {
++	}
++
++	sps->b_vui = 0;
++
++	sps->b_gaps_in_frame_num_value_allowed = 0;
++	sps->b_frame_mbs_only = 1;
++	if(!sps->b_frame_mbs_only)
++		sps->i_mb_height = (sps->i_mb_height + 1) & ~1;
++	sps->b_mb_adaptive_frame_field = p->interlaced;
++	sps->b_direct8x8_inference = 1;
++	sps->crop.i_left = 0;
++	sps->crop.i_right = sps->i_mb_width * 16 - p->width;
++	sps->crop.i_top = 0;
++	sps->crop.i_bottom = sps->i_mb_height * 16 - p->height;
++
++	if(sps->crop.i_right || sps->crop.i_bottom) {
++		sps->b_crop = 1;
++	} else {
++		sps->b_crop = 0;
++	}
++
++//	h264_sps_init_reconfigurable(sps, sw);
++
++
++	sps->vui.b_overscan_info_present = 0;
++	sps->vui.b_overscan_info = 0;
++
++	sps->i_cqm_preset = 0;
++	sps->b_avcintra = 0;
++
++}
++
++static void h264e_pps_init(struct h264e_ctx *ctx, h264_pps_t *pps, int i_id, h264_sps_t *sps)
++{
++	struct h264e_params *p = &ctx->p;
++
++	pps->i_id = i_id;
++	pps->i_sps_id = sps->i_id;
++	pps->b_cabac = sps->i_profile_idc < PROFILE_MAIN ? 0 : p->i_cabac;
++
++	pps->b_pic_order = 0;
++	pps->i_num_slice_groups = 1; /* base & main profile.*/
++
++	pps->i_num_ref_idx_l0_default_active = p->max_ref_pic;
++	pps->i_num_ref_idx_l1_default_active = 1;
++
++	pps->b_weighted_pred = 0;
++	pps->b_weighted_bipred = 0;
++
++	pps->i_pic_init_qp = 26;
++	pps->i_pic_init_qs = 26;
++
++	pps->i_chroma_qp_index_offset = 0;
++	pps->b_deblocking_filter_control = 0;
++	pps->b_constrained_intra_pred = 0;
++	pps->b_redundant_pic_cnt = 0;
++
++	pps->b_transform_8x8_mode = p->h264_8x8_transform;
++}
++
++
++static int encapsulate_nal(bs_t *s, int s_off, char *dst, int i_type, int i_ref_idc)
++{
++
++	uint8_t *src = s->p_start + s_off;
++	uint8_t *end = src + (bs_pos(s) / 8);
++	char *orig_dst = dst;
++
++	/* prefix */
++	*dst++ = 0x00;
++	*dst++ = 0x00;
++	*dst++ = 0x00;
++	*dst++ = 0x01;
++
++	/* nal header */
++	*dst++ = (0 << 7) | (i_ref_idc << 5) | (i_type);
++
++	if(src < end) *dst++ = *src++;
++	if(src < end) *dst++ = *src++;
++	while( src < end )
++	{
++		if( src[0] <= 0x03 && !src[-2] && !src[-1] ) {
++			*dst++ = 0x03;
++		}
++		*dst++ = *src++;
++	}
++
++	return dst - orig_dst;
++}
++
++/**
++* @h264e_generate_headers generate sps/pps headers according to params.
++*			and store the header until encoder closed.
++* @ctx h264e_ctx.
++*
++* @Return 0
++*/
++int h264e_generate_headers(struct h264e_ctx *ctx, int is_stream_on)
++{
++	/* used to encode header for tmp.*/
++	char *bs_tmp = NULL;
++	char *bs_header = ctx->bs_header;
++	bs_t bs;
++	int bs_size = 0;
++	h264_sps_t *sps = NULL;
++	h264_pps_t *pps = NULL;
++	ctx->bs_header_size = 0;
++
++	bs_tmp = kzalloc(MAX_BS_HEADER_SIZE, GFP_KERNEL);
++	if(!bs_tmp) {
++		return -ENOMEM;
++	}
++
++	sps = &ctx->sps;
++	pps = &ctx->pps;
++
++	h264e_sps_init(ctx, sps, 0);
++	h264e_pps_init(ctx, pps, 0, sps);
++
++	/* 1. encode sps */
++	bs_init(&bs, bs_tmp, MAX_BS_HEADER_SIZE);
++	h264e_sps_write(&bs, sps);
++
++	bs_size = encapsulate_nal(&bs, 0, bs_header, NAL_SPS, NAL_PRIORITY_HIGHEST);
++
++	ctx->bs_header_size += bs_size;
++	bs_header	    += bs_size;
++
++	/* 2. encode pps */
++	bs_init(&bs, bs_tmp, MAX_BS_HEADER_SIZE);
++	h264e_pps_write(&bs, sps, pps);
++
++	bs_size = encapsulate_nal(&bs, 0, bs_header, NAL_PPS, NAL_PRIORITY_HIGHEST);
++	ctx->bs_header_size += bs_size;
++	bs_header 	   += bs_size;
++
++
++	if(ctx->bs_header_size > (MAX_BS_HEADER_SIZE)) {
++		pr_warn("bs_header buffer almost overflow!\n");
++	}
++
++	/* 3. encode sei */
++
++	/* 4. encode more */
++
++	if(is_stream_on) {
++
++		struct nl_header_info h_info;
++
++		memcpy(&h_info.pps, pps, sizeof(h264_pps_t));
++		memcpy(&h_info.sps, sps, sizeof(h264_sps_t));
++
++		h264e_nl_setup_headers(ctx, &h_info);
++	}
++
++	/* release temp buffer. */
++	kfree(bs_tmp);
++	return 0;
++}
++
++/* add 0xff nal .*/
++static int h264e_filler_nal(int size, char *p)
++{
++        if (size < 6)
++                return -EINVAL;
++
++        p[0] = 0x00;
++        p[1] = 0x00;
++        p[2] = 0x00;
++        p[3] = 0x01;
++        p[4] = 0x0c;
++        memset(p + 5, 0xff, size - 6);
++        /* Add rbsp stop bit and trailing at the end */
++        p[size - 1] = 0x80;
++
++        return 0;
++}
++
++static int h264e_padding(int size, char *p)
++{
++	int ret = 0;
++
++	if(size == 0)
++		return 0;
++
++        ret = h264e_filler_nal(size, p);
++	if(ret < 0)
++		return ret;
++
++        return size;
++}
++
++int h264e_encode_headers(struct h264e_ctx *ctx, struct ingenic_vcodec_mem *bs)
++{
++	int ret = 0;
++	unsigned int align = 0;
++
++	if(ctx->encoded_bs_len != 0) {
++		pr_info("set encoded_bs_len to 0 before encode!\n");
++	}
++
++	memcpy(bs->va, ctx->bs_header, ctx->bs_header_size);
++
++	/*align to 256*/
++	align = (ctx->bs_header_size + 255) / 256 * 256;
++	ret = h264e_padding(align - ctx->bs_header_size, bs->va + ctx->bs_header_size);
++	ctx->encoded_bs_len = align;
++
++	ret = ctx->encoded_bs_len;
++
++	return ret;
++}
++
++void xhexdump(unsigned char *buf, int len)
++{
++	int i;
++
++	for (i = 0; i < len; i++) {
++		if ((i % 16) == 0)
++			printf("%s%08x: ", i ? "\n" : "",
++					(unsigned int)&buf[i]);
++		printf("%02x ", buf[i]);
++	}
++	printf("\n");
++}
++
++
++int h264e_encode(struct h264e_ctx *ctx, struct video_frame_buffer *frame,
++		struct ingenic_vcodec_mem *bs_mem, int force_idr, int *keyframe)
++{
++	struct ingenic_venc_ctx *venc_ctx = ctx->priv;
++	unsigned int slice_header_size = 0;
++	unsigned int slice_header_len = 0;
++	int idr = 0;
++	int i_nal_type = 0;
++	int i_nal_ref_idc = 0;
++	bs_t bs;
++	int ret = 0;
++	int i = 0;
++#if 0
++	unsigned char bmap[3][3] = {
++		{0, 2, 1},
++		{1, 0, 2},
++		{2, 1, 0}
++	};
++#endif
++
++	unsigned char bmap[2][2] = {
++		{0, 1},
++		{1, 0},
++	};
++	unsigned int encoded_header_size = 0;
++
++	struct h264e_frame_start_params p;
++
++	memset(&p, 0, sizeof(struct h264e_frame_start_params));
++
++	ctx->frame = frame;
++	ctx->bs = bs_mem;
++
++	if(!(ctx->i_frame % ctx->p.gop_size) || force_idr) {
++		ctx->i_frame = 0;
++		idr = 1;
++	}
++
++	unsigned char *bufidx = bmap[ctx->i_frame % NUM_WORK_BUFFERS];
++
++	p.bIFrmReq = idr;
++	if(idr) {
++		p.frmSkipType = 0;
++	} else {
++		p.frmSkipType = 1;
++	}
++
++	p.raw_format	= ctx->p.format;
++	for(i = 0; i < ctx->frame->num_planes; i++) {
++		p.raw[i] = ctx->frame->fb_addr[i].pa;
++	}
++
++	for(i = 0; i < NUM_WORK_BUFFERS; i++) {
++		p.fb[i][0] = ctx->fb[bufidx[i]].yaddr_pa;
++		p.fb[i][1] = ctx->fb[bufidx[i]].caddr_pa;
++	}
++
++	p.stride[0] 		= ctx->p.width;
++	p.stride[1]		= p.raw_format == HELIX_420P_MODE ?
++				  ctx->p.width / 2 : ctx->p.width;
++
++	if(idr) {
++		*keyframe = idr;
++		if(*keyframe && add_sps_pps_iframe) {
++			/* insert sps/pps.*/
++			encoded_header_size = h264e_encode_headers(ctx, ctx->bs);
++			ctx->bs->va += encoded_header_size;
++			ctx->bs->pa += encoded_header_size;
++		}
++
++	}
++
++	p.emc_bs_pa = ctx->bs->pa;
++	p.emc_dblk_pa = ctx->emc_buf_pa;
++
++	h264e_nl_rc_frame_start(ctx, &p);
++
++	dma_sync_single_for_device(venc_ctx->dev->dev, ctx->desc_pa, ctx->vdma_chain_len, DMA_TO_DEVICE);
++
++	/*2. �动编�器硬件，开始编�*/
++	ret = ingenic_vpu_start(ctx->priv);
++	if(ret < 0) {
++		return ret;
++	}
++
++	//print_hex_dump(KERN_INFO, "bs@", DUMP_PREFIX_ADDRESS, 16, 1, ctx->bs->va, 64, 1);
++
++
++	ctx->encoded_bs_len = encoded_header_size + ctx->r_bs_len + ctx->r_rbsp_len + p.slice_header_len;
++
++	unsigned char *xp = (unsigned char *)((unsigned long)ctx->bs->va | 0xa0000000);
++	xp[0] = 0x00;
++	xp[1] = 0x00;
++	xp[2] = 0x00;
++
++
++	struct h264e_frame_end_params ep;
++	ep.u32FrmActBs = ctx->r_bs_len * 8;
++	h264e_nl_rc_frame_end(ctx, &ep);
++
++
++	//printk("ctx->encoded_bs_len: %d\n", ctx->encoded_bs_len);
++
++	ctx->i_frame++;
++
++	return ret;
++}
++
++
++
++/* start streaming.*/
++int h264e_alloc_workbuf(struct h264e_ctx *ctx)
++{
++	struct ingenic_venc_ctx *venc_ctx = ctx->priv;
++	int allocate_fb = 0;
++	int ret = 0;
++	int i = 0;
++
++
++
++	/* init yaddr. */
++	for(i = 0; i < 3; i++) {
++		ctx->fb[i].yaddr = NULL;
++		ctx->fb[i].caddr = NULL;
++	}
++
++	for(i = 0; i < NUM_WORK_BUFFERS; i++) {
++		ctx->fb[i].yaddr = dma_alloc_coherent(venc_ctx->dev->dev, ctx->framesize, &ctx->fb[i].yaddr_pa, GFP_KERNEL);
++		ctx->fb[i].caddr = dma_alloc_coherent(venc_ctx->dev->dev, ctx->framesize/2, &ctx->fb[i].caddr_pa, GFP_KERNEL);
++
++		allocate_fb = i;
++		if(!ctx->fb[i].yaddr || !ctx->fb[i].caddr) {
++			ret = -ENOMEM;
++			goto err_fb;
++		}
++	}
++
++	return ret;
++
++err_emc_buf:
++err_fb:
++	for(i = 0; i < NUM_WORK_BUFFERS; i++) {
++		if(ctx->fb[i].yaddr) {
++			dma_free_coherent(venc_ctx->dev->dev, ctx->framesize, ctx->fb[i].yaddr, ctx->fb[i].yaddr_pa);
++		}
++		if(ctx->fb[i].caddr) {
++			dma_free_coherent(venc_ctx->dev->dev, ctx->framesize/2, ctx->fb[i].caddr, ctx->fb[i].caddr_pa);
++		}
++
++	}
++
++	return ret;
++}
++
++/* stop streaming.*/
++int h264e_free_workbuf(struct h264e_ctx *ctx)
++{
++	struct ingenic_venc_ctx *venc_ctx = ctx->priv;
++	int i;
++
++	for(i = 0; i < NUM_WORK_BUFFERS; i++) {
++		dma_free_coherent(venc_ctx->dev->dev, ctx->framesize, ctx->fb[i].yaddr, ctx->fb[i].yaddr_pa);
++		dma_free_coherent(venc_ctx->dev->dev, ctx->framesize/2, ctx->fb[i].caddr, ctx->fb[i].caddr_pa);
++	}
++	return 0;
++}
++
++int h264e_encoder_init(struct h264e_ctx *ctx)
++{
++	struct ingenic_venc_ctx *venc_ctx = ctx->priv;
++	struct h264e_params *p = NULL;
++	int ret = 0;
++
++	ctx->emc_buf = dma_alloc_coherent(venc_ctx->dev->dev, EMC_SIZE, &ctx->emc_buf_pa, GFP_KERNEL);
++	if(!ctx->emc_buf) {
++		pr_err("Failed to alloc vpu emc_buf!\n");
++		ret = -ENOMEM;
++		goto err_emc_buf;
++	}
++
++
++
++	p = &ctx->p;
++
++	ctx->vdma_chain_len 	= 40960 + 256;
++	ctx->frameindex		= 0;
++	ctx->i_frame		= 0;
++
++	p->height		= 240;
++	p->width		= 160;
++	p->max_ref_pic		= 1;
++	p->i_idr_pic_id		= 0;
++	p->i_global_qp 		= 30;
++	p->i_cabac		= 1;
++	p->interlaced		= 0;
++	p->h264_8x8_transform	= 0;
++	p->deblock		= 0;
++//	p->h264_hdr_mode	= 1;
++
++	ctx->desc = dma_alloc_noncoherent(venc_ctx->dev->dev, ctx->vdma_chain_len, &ctx->desc_pa, DMA_BIDIRECTIONAL, GFP_KERNEL);
++	if(!ctx->desc) {
++		pr_err("Failed to alloc vpu desc buffer!\n");
++		ret = -ENOMEM;
++		goto err_desc;
++	}
++
++	struct nl_ctx_info info;
++
++	info.emc_buf_paddr	= (unsigned int)ctx->emc_buf_pa;
++	info.desc_paddr		= (unsigned int)ctx->desc_pa;
++	info.rc_mode		= p->rc_mode;
++
++	ret = h264e_nl_init_ctx(ctx, &info);
++
++	return ret;
++err_desc:
++err_emc_buf:
++
++	return ret;
++}
++
++int h264e_encoder_deinit(struct h264e_ctx *ctx)
++{
++	struct ingenic_venc_ctx *venc_ctx = ctx->priv;
++	if(!ctx)
++		return 0;
++
++	if(ctx->emc_buf) {
++		dma_free_coherent(venc_ctx->dev->dev, EMC_SIZE, ctx->emc_buf, ctx->emc_buf_pa);
++		ctx->emc_buf = NULL;
++	}
++
++	if(ctx->desc) {
++		dma_free_noncoherent(venc_ctx->dev->dev, ctx->vdma_chain_len, ctx->desc, ctx->desc_pa, DMA_BIDIRECTIONAL);
++		ctx->desc = NULL;
++	}
++
++	h264e_nl_free_ctx(ctx);
++
++	return 0;
++}
++
++void h264e_set_priv(struct h264e_ctx *ctx, void *data)
++{
++	ctx->priv = data;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e_rc.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e_rc.h
+new file mode 100644
+index 000000000..a9d3a5a59
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e_rc.h
+@@ -0,0 +1,85 @@
++#ifndef __H264E_H__
++#define __H264E_H__
++
++
++#include "h264enc/common.h"
++#include "h264enc/set.h"
++#include "h264e_rc_proto.h"
++
++#include "helix_buf.h"
++
++
++
++#define MAX_BS_HEADER_SIZE	256	/* maybe enough for header only.*/
++#define MAX_SLICE_HEADER_SIZE	128	/* 128bytes of slice header bs.*/
++
++struct h264e_ctx {
++	unsigned char bs_header[MAX_BS_HEADER_SIZE]; /* buffer to store sps/pps/sei headers. */
++	unsigned int bs_header_size;	/* buffer size. */
++
++	unsigned char slice_header[128]; /*store slice buffer.*/
++
++	int vdma_chain_len;
++	unsigned int framesize;
++	/*根�height,width分�的,*/
++	struct  h264_ref_tile fb[3]; /*�考body buffer.按frame申请*/
++	struct  h264_ref_tile jh[3]; /*�考header buffer.按frame申请*/
++
++	unsigned int *emc_buf;	    /* 128KBytes固定空间*/
++	dma_addr_t emc_buf_pa;
++
++	unsigned int *desc;	    /* descriptor, 40960+256, 固定大�*/
++	dma_addr_t desc_pa;
++
++
++	struct video_frame_buffer *frame; /* input picture frame. */
++	struct ingenic_vcodec_mem *bs; /* output slice data. exclude slice header? */
++	struct ingenic_vcodec_mem bs_tmp_buf; /* temperary buf for now., used to store vpu output buffer. then memory cp to userspace. */
++
++	unsigned int src_crc;	/*Debug*/
++
++
++	h264_sps_t sps;
++	h264_pps_t pps;
++	h264_slice_header_t sh;
++	h264_cabac_t cb;	/*cabac state*/
++
++	int i_frame;	/* (i_frame + 1) % gop_size */
++
++	/* modify after encode frame*/
++	unsigned long frameindex;
++	unsigned int status;
++	unsigned int r_bs_len;		/*result bs len.*/
++	unsigned int r_rbsp_len; 	/*0x03 的个数.*/
++	unsigned int encoded_bs_len;	/* encoded bs_len */
++
++	struct h264e_params p;
++	unsigned int pid;	/*netlink port*/
++#define H264E_MAX_NL_MSG	1024
++	unsigned char recved_msg[H264E_MAX_NL_MSG];	/* netlink received msg.*/
++	struct completion msg_complete;
++
++	void *priv;
++};
++
++extern int h264e_generate_headers(struct h264e_ctx *ctx, int is_stream_on);
++
++extern int h264e_encode_headers(struct h264e_ctx *ctx, struct ingenic_vcodec_mem *bs);
++
++extern int h264e_encode(struct h264e_ctx *ctx, struct video_frame_buffer *frame, struct ingenic_vcodec_mem *bs, int force_idr, int *keyframe);
++
++extern int h264e_set_fmt(struct h264e_ctx *ctx, int width, int height, int format);
++extern int h264e_alloc_workbuf(struct h264e_ctx *ctx);
++
++extern int h264e_free_workbuf(struct h264e_ctx *ctx);
++
++extern int h264e_encoder_init(struct h264e_ctx *ctx);
++
++extern int h264e_encoder_deinit(struct h264e_ctx *ctx);
++
++extern void h264e_set_priv(struct h264e_ctx *ctx, void *data);
++
++
++extern int h264e_netlink_test(void);
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e_rc_nl.c b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e_rc_nl.c
+new file mode 100644
+index 000000000..dcfc9fce3
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e_rc_nl.c
+@@ -0,0 +1,285 @@
++#include <linux/netlink.h>
++#include <net/sock.h>
++
++#include "h264e_rc.h"
++#include "h264e_rc_nl.h"
++
++
++
++
++static struct sock *nl_sk;
++static DEFINE_MUTEX(netlink_mutex);
++static int h264e_rc_server_online = 0;
++
++//static DECLARE_COMPLETION(msg_complete);
++
++static int h264e_netlink_send_msg(struct h264e_ctx *ctx, void *buf, unsigned int len)
++{
++	struct sk_buff *skb = NULL;
++	struct nlmsghdr *nlh;
++	int ret = 0;
++	int timeout = 0;
++
++
++	skb = nlmsg_new(len, GFP_ATOMIC);
++	if(!skb) {
++		pr_err("nlmsg_new error!\n");
++		return -ENOMEM;
++	}
++
++	nlh = nlmsg_put(skb, ctx->pid, 0, 0, len, 0);
++	if(!nlh) {
++		kfree(skb);
++		pr_err("nlmsg_put error!\n");
++		return -EINVAL;
++	}
++
++	memcpy(nlmsg_data(nlh), buf, len);
++
++
++	/*wait for completion.*/
++
++	reinit_completion(&ctx->msg_complete);
++
++	ret = netlink_unicast(nl_sk, skb, ctx->pid, 0);
++
++	timeout = wait_for_completion_timeout(&ctx->msg_complete, msecs_to_jiffies(30));
++	if(!timeout) {
++		printk("h264e nl send msg timeout!\n");
++		return -ETIMEDOUT;
++	}
++
++#if 0
++	//return netlink_unicast(nl_sk, skb, pid, MSG_DONTWAIT);
++	while(!wait_msg_recv) {
++		msleep(1);
++	}
++#endif
++
++	return ret;
++}
++
++static int h264e_netlink_rcv_msg(struct sk_buff *skb, struct nlmsghdr *nlh, struct netlink_ext_ack *extack)
++{
++
++	struct h264e_nl_msg *msg = NLMSG_DATA(nlh);
++	struct h264e_ctx *ctx = NULL;
++
++	switch (nlh->nlmsg_type) {
++		default:
++		//	pr_err("unknown nlmsg_type\n");
++			break;
++	}
++
++	switch (msg->cmd) {
++		case VPU_CMD_SERVER_ONLINE:
++			h264e_rc_server_online = 1;
++			break;
++		case VPU_CMD_SERVER_OFFLINE:
++			h264e_rc_server_online = 0;
++			break;
++
++		default:
++			break;
++	}
++
++	ctx = (struct h264e_ctx *)msg->ctx_id;
++
++	if(ctx) {
++		if((nlh->nlmsg_len - NLMSG_HDRLEN) > H264E_MAX_NL_MSG) {
++			printk("recved msg too long: %d, max: %d\n", nlh->nlmsg_len, H264E_MAX_NL_MSG);
++		} else {
++			memcpy(ctx->recved_msg, NLMSG_DATA(nlh), nlh->nlmsg_len - NLMSG_HDRLEN);
++		}
++
++		complete(&ctx->msg_complete);
++	}
++
++
++	return 0;
++}
++
++static void h264e_netlink_rcv(struct sk_buff *skb)
++{
++	mutex_lock(&netlink_mutex);
++	netlink_rcv_skb(skb, &h264e_netlink_rcv_msg);
++	mutex_unlock(&netlink_mutex);
++}
++
++static int start_h264e_server(void)
++{
++#if 0
++	const char *server = "/usr/bin/h264e-nl-server"
++	static const char *argv[MAX_INIT_ARGS+2] = { "/usr/bin/h264e-nl-server", NULL, };
++#endif
++
++	if(h264e_rc_server_online) {
++		return 0;
++	}
++
++
++#if 0
++	return do_execve(getname_kernel(),
++        (const char __user *const __user *)argv_init,
++        (const char __user *const __user *)envp_init);
++#endif
++
++	/*kernel start h264e_rc_server.*/
++
++	/*wait for h264e_rc_server_online = 1.*/
++	return 0;
++}
++
++int h264e_netlink_test(void)
++{
++	struct netlink_kernel_cfg nl_cfg = {
++		.input  = h264e_netlink_rcv,
++	};
++
++
++	nl_sk = netlink_kernel_create(&init_net, NETLINK_H264_ENCODER, &nl_cfg);
++	if(!nl_sk) {
++		printk("failed to create netlink\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++
++/*调用远程的创建上下文.*/
++int h264e_nl_init_ctx(struct h264e_ctx *ctx, struct nl_ctx_info *info)
++{
++	/*远端主�处�的内容.*/
++	int id = 0;
++	unsigned int msg_len = sizeof(struct h264e_nl_msg) + sizeof(struct nl_ctx_info);
++
++	if(!h264e_rc_server_online) {
++		printk("h264e server not online\n");
++		return -EINVAL;
++	}
++
++	struct h264e_nl_msg *msg = kmalloc(msg_len, GFP_KERNEL);
++
++#if 0
++	if(!netlink_has_listeners(nl_sk, 1)) {
++		printk("h264e netlink has no listeners, start server first!\n");
++		return -EINVAL;
++	}
++#endif
++
++	ctx->pid = NETLINK_H264_PORT;
++	init_completion(&ctx->msg_complete);
++
++	msg->ctx_id = ctx;	/*以ctx的地�作为ctx_id*/
++	msg->cmd = VPU_CMD_CREATE_CTX;
++	memcpy(msg->buf, info, sizeof(struct nl_ctx_info));
++
++	h264e_netlink_send_msg(ctx, msg, msg_len);
++
++
++	/*wait done.*/
++
++	kfree(msg);
++
++	/*return values. */
++	msg = (struct h264e_nl_msg *)ctx->recved_msg;
++
++	return msg->ret_val;
++}
++
++/*释放远端的上下文�柄.*/
++int h264e_nl_free_ctx(struct h264e_ctx *ctx)
++{
++
++	struct h264e_nl_msg msg;
++
++
++	msg.ctx_id = ctx;
++	msg.cmd = VPU_CMD_FREE_CTX;
++
++	h264e_netlink_send_msg(ctx, &msg, sizeof(struct h264e_nl_msg));
++
++	return 0;
++}
++
++int h264e_nl_setup_headers(struct h264e_ctx *ctx, struct nl_header_info *info)
++{
++	unsigned int msg_len = sizeof(struct h264e_nl_msg) + sizeof(struct nl_header_info);
++	struct h264e_nl_msg *msg = NULL;
++
++	if(!h264e_rc_server_online) {
++		printk("%s, %d h264e server not online\n", __func__, __LINE__);
++		return -EINVAL;
++	}
++
++
++	msg = kmalloc(msg_len, GFP_KERNEL);
++	msg->ctx_id = ctx;
++	msg->cmd = VPU_CMD_SETUP_HEADERS;
++
++
++	memcpy(msg->buf, info, sizeof(struct nl_header_info));
++
++	h264e_netlink_send_msg(ctx, msg, msg_len);
++
++	kfree(msg);
++
++
++	return 0;
++}
++
++int h264e_nl_rc_video_cfg(struct h264e_ctx *ctx, struct h264e_params *p)
++{
++	unsigned int msg_len = sizeof(struct h264e_nl_msg) + sizeof(struct h264e_params);
++	struct h264e_nl_msg *msg = kmalloc(msg_len, GFP_KERNEL);
++
++	msg->ctx_id = ctx;
++	msg->cmd = VPU_CMD_RC_VIDEO_CFG;
++
++	memcpy(msg->buf, p, sizeof(struct h264e_params));
++
++	h264e_netlink_send_msg(ctx, msg, msg_len);
++
++
++	kfree(msg);
++	return 0;
++}
++
++int h264e_nl_rc_frame_start(struct h264e_ctx *ctx, struct h264e_frame_start_params *p)
++{
++	unsigned int msg_len = sizeof(struct h264e_nl_msg) + sizeof(struct h264e_frame_start_params);
++	struct h264e_nl_msg *msg = kmalloc(msg_len, GFP_KERNEL);
++
++	msg->ctx_id = ctx;
++	msg->cmd = VPU_CMD_RC_FRAME_START;
++
++	memcpy(msg->buf, p, sizeof(struct h264e_frame_start_params));
++	h264e_netlink_send_msg(ctx, msg, msg_len);
++	/*wait.*/
++
++	kfree(msg);
++
++	/*return values. */
++	msg = (struct h264e_nl_msg *)ctx->recved_msg;
++	memcpy(p, msg->buf, sizeof(struct h264e_frame_start_params));
++
++	return 0;
++}
++
++int h264e_nl_rc_frame_end(struct h264e_ctx *ctx, struct h264e_frame_end_params *p)
++{
++	unsigned int msg_len = sizeof(struct h264e_nl_msg) + sizeof(struct h264e_frame_end_params);
++	struct h264e_nl_msg *msg = kmalloc(msg_len, GFP_KERNEL);
++
++	msg->ctx_id = ctx;
++	msg->cmd = VPU_CMD_RC_FRAME_END;
++
++	memcpy(msg->buf, p, sizeof(struct h264e_frame_end_params));
++	h264e_netlink_send_msg(ctx, msg, msg_len);
++
++	/*wait.*/
++
++	kfree(msg);
++	return 0;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e_rc_nl.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e_rc_nl.h
+new file mode 100644
+index 000000000..666a9e301
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e_rc_nl.h
+@@ -0,0 +1,16 @@
++#ifndef __H264E_RC_NL_H__
++#define __H264E_RC_NL_H__
++
++
++#include "h264e_rc_proto.h"
++#include "h264e_rc.h"
++
++
++int h264e_nl_init_ctx(struct h264e_ctx *ctx, struct nl_ctx_info *info);
++int h264e_nl_free_ctx(struct h264e_ctx *ctx);
++int h264e_nl_setup_headers(struct h264e_ctx *ctx, struct nl_header_info *info);
++int h264e_nl_rc_video_cfg(struct h264e_ctx *ctx, struct h264e_params *p);
++int h264e_nl_rc_frame_start(struct h264e_ctx *ctx, struct h264e_frame_start_params *p);
++int h264e_nl_rc_frame_end(struct h264e_ctx *ctx, struct h264e_frame_end_params *p);
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e_rc_proto.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e_rc_proto.h
+new file mode 100644
+index 000000000..e80a7898a
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264e_rc_proto.h
+@@ -0,0 +1,113 @@
++#ifndef __H264E_RC_PROTO_H__
++#define __H264E_RC_PROTO_H__
++
++
++/* 创建ctx时，内核�供的地�信�. */
++struct nl_ctx_info {
++	unsigned int vpu_rc_paddr;	/*内核申请的VPU_RC_S 的物�地�.*/
++	unsigned int slice_info_paddr;	/*内核申请的Sliceinfo_t 的物�地�.*/
++	unsigned int emc_buf_paddr;	/*内核申请的emc_buf的物�地�.*/
++	unsigned int desc_paddr;	/*内核申请的dma buf的物�地�.*/
++	uint8_t rc_mode;
++};
++
++struct nl_header_info {
++	h264_pps_t pps;
++	h264_sps_t sps;
++};
++
++/**
++* @bitrate, set by V4L2_CID_MPEG_VIDEO_BITRATE.
++* @gop_size, group of picture when h264 encoding.
++*
++* used by kernel and app. params across kernel and app. for video_cfg.
++*/
++struct h264e_params {
++
++	/* params modify by s_ctrl*/
++	uint32_t bitrate;
++	uint32_t framerate;
++	int h264_hdr_mode;
++#if 0
++	uint8_t h264_intra_qp;
++	uint8_t h264_inter_qp;
++#endif
++	uint8_t	i_qp;
++	uint8_t p_qp;
++	uint8_t h264_min_qp;
++	uint8_t h264_max_qp;
++	uint8_t h264_profile;
++	uint8_t h264_level;
++	uint8_t gop_size;
++	uint8_t frame_rc_enable;
++	uint8_t mb_rc_enable;
++	uint8_t num_bframe;
++	uint8_t interlaced;
++	uint8_t max_ref_pic;
++	uint8_t h264_8x8_transform;
++	uint8_t rc_mode;
++
++	uint8_t i_cabac; /*is cabac entropy?*/
++
++	int i_idr_pic_id;
++	int i_global_qp;
++
++	uint8_t deblock;
++
++	int height;
++	int width;
++	int format;
++
++};
++
++struct h264e_frame_start_params {
++	unsigned int bIFrmReq;
++	unsigned int frmSkipType;
++
++
++	/* Slice info. */
++	//unsigned int des_pa;
++	unsigned int raw_format;
++	unsigned int emc_bs_pa;
++	unsigned int emc_dblk_pa;
++
++	/* VPU input buffer address. */
++	unsigned int raw[3];
++	unsigned int fb[3][2];
++	unsigned int stride[2];
++
++	unsigned int slice_header_len; /*TO kernel.*/
++};
++
++struct h264e_frame_end_params {
++	unsigned int u32FrmActBs;
++};
++
++enum {
++	VPU_CMD_CREATE_CTX = 1,
++	VPU_CMD_FREE_CTX,
++	VPU_CMD_SETUP_HEADERS,
++	VPU_CMD_EPRC_SET_DEFAULT,
++	VPU_CMD_RC_VIDEO_CFG,
++	VPU_CMD_RC_FRAME_START,
++	VPU_CMD_RC_FRAME_END,
++	VPU_CMD_SERVER_ONLINE,	/*From server to kernel*/
++	VPU_CMD_SERVER_OFFLINE, /*From server to kernel*/
++};
++
++struct h264e_nl_msg {
++	unsigned int ctx_id;	/*当�msg对应的ctx id. 当命令为VPU_CMD_CREATE_CTX 时，此值由应用server填充.*/
++	unsigned int cmd;	/*当�msg对应的调用命令.*/
++	int ret_val;
++
++	unsigned char buf[0];	/*Dynamic malloc buffer.*/
++};
++
++
++#define NETLINK_H264_ENCODER	30
++#define MAXPALOAD	64
++
++#define NETLINK_H264_PORT	0x26402640
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/bitstream.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/bitstream.h
+new file mode 100644
+index 000000000..4fbe594a5
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/bitstream.h
+@@ -0,0 +1,242 @@
++#ifndef __BITSTREAM_H__
++#define __BITSTREAM_H__
++
++typedef struct {
++	uint8_t *p_start;
++	uint8_t *p;
++	uint8_t *p_end;
++
++	uintptr_t cur_bits;
++	int i_left;
++	int i_bits_encoded;
++} bs_t;
++
++
++
++
++/* Unions for type-punning.
++ * Mn: load or store n bits, aligned, native-endian
++ * CPn: copy n bits, aligned, native-endian
++ * we don't use memcpy for CPn because memcpy's args aren't assumed to be aligned */
++typedef union { uint16_t i; uint8_t  c[2]; } h264_union16_t;
++typedef union { uint32_t i; uint16_t b[2]; uint8_t  c[4]; } h264_union32_t;
++typedef union { uint64_t i; uint32_t a[2]; uint16_t b[4]; uint8_t c[8]; } h264_union64_t;
++typedef struct { uint64_t i[2]; } h264_uint128_t;
++typedef union { h264_uint128_t i; uint64_t a[2]; uint32_t b[4]; uint16_t c[8]; uint8_t d[16]; } h264_union128_t;
++#define M16(src) (((h264_union16_t*)(src))->i)
++#define M32(src) (((h264_union32_t*)(src))->i)
++#define M64(src) (((h264_union64_t*)(src))->i)
++#define M128(src) (((h264_union128_t*)(src))->i)
++#define M128_ZERO ((h264_uint128_t){{0,0}})
++#define CP16(dst,src) M16(dst) = M16(src)
++#define CP32(dst,src) M32(dst) = M32(src)
++#define CP64(dst,src) M64(dst) = M64(src)
++#define CP128(dst,src) M128(dst) = M128(src)
++
++
++
++
++/*
++	p_data必须按WORD地�对�。
++*/
++static inline void bs_init(bs_t *s, void *p_data, int i_data)
++{
++	s->p = s->p_start = (uint8_t *)p_data;
++	s->p_end = (uint8_t *)p_data + i_data;
++	s->i_left = WORD_SIZE * 8;
++	s->cur_bits = endian_fix32(M32(s->p));
++	s->cur_bits >>= 32;
++}
++
++static inline int bs_pos(bs_t *s)
++{
++	return (8 * (s->p - s->p_start) + (WORD_SIZE*8) - s->i_left);
++}
++
++static inline void bs_flush(bs_t *s)
++{
++	M32( s->p ) = endian_fix32( s->cur_bits << (s->i_left&31) );
++	s->p += WORD_SIZE - (s->i_left >> 3);
++	s->i_left = WORD_SIZE*8;
++}
++
++static inline void bs_realign(bs_t *s)
++{
++	int offset = ((intptr_t)s->p & 3);
++	if( offset )
++	{
++		s->p       = (uint8_t*)s->p - offset;
++		s->i_left  = (WORD_SIZE - offset)*8;
++		s->cur_bits = endian_fix32( M32(s->p) );
++		s->cur_bits >>= (4-offset)*8;
++	}
++}
++
++static inline void bs_write( bs_t *s, int i_count, uint32_t i_bits )
++{
++	if( i_count < s->i_left )
++	{
++		s->cur_bits = (s->cur_bits << i_count) | i_bits;
++		s->i_left -= i_count;
++	}
++	else
++	{
++		i_count -= s->i_left;
++		s->cur_bits = (s->cur_bits << s->i_left) | (i_bits >> i_count);
++		M32( s->p ) = endian_fix( s->cur_bits );
++		s->p += 4;
++		s->cur_bits = i_bits;
++		s->i_left = 32 - i_count;
++	}
++}
++
++
++/* Special case to eliminate branch in normal bs_write. */
++/* Golomb never writes an even-size code, so this is only used in slice headers. */
++static inline void bs_write32( bs_t *s, uint32_t i_bits )
++{
++	bs_write( s, 16, i_bits >> 16 );
++	bs_write( s, 16, i_bits );
++}
++
++static inline void bs_write1( bs_t *s, uint32_t i_bit )
++{
++    s->cur_bits <<= 1;
++    s->cur_bits |= i_bit;
++    s->i_left--;
++    if( s->i_left == WORD_SIZE*8-32 )
++    {
++        M32( s->p ) = endian_fix32( s->cur_bits );
++        s->p += 4;
++        s->i_left = WORD_SIZE*8;
++    }
++}
++
++static inline void bs_align_0( bs_t *s )
++{
++    bs_write( s, s->i_left&7, 0 );
++    bs_flush( s );
++}
++static inline void bs_align_1( bs_t *s )
++{
++    bs_write( s, s->i_left&7, (1 << (s->i_left&7)) - 1 );
++    bs_flush( s );
++}
++static inline void bs_align_10( bs_t *s )
++{
++    if( s->i_left&7 )
++        bs_write( s, s->i_left&7, 1 << ( (s->i_left&7) - 1 ) );
++    bs_flush( s );
++}
++
++/* golomb functions */
++
++static const uint8_t x264_ue_size_tab[256] =
++{
++     1, 1, 3, 3, 5, 5, 5, 5, 7, 7, 7, 7, 7, 7, 7, 7,
++     9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
++    11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,
++    11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,
++    13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,
++    13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,
++    13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,
++    13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,
++    15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,
++    15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,
++    15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,
++    15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,
++    15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,
++    15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,
++    15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,
++    15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,
++};
++
++static inline void bs_write_ue_big( bs_t *s, unsigned int val )
++{
++    int size = 0;
++    int tmp = ++val;
++    if( tmp >= 0x10000 )
++    {
++        size = 32;
++        tmp >>= 16;
++    }
++    if( tmp >= 0x100 )
++    {
++        size += 16;
++        tmp >>= 8;
++    }
++    size += x264_ue_size_tab[tmp];
++    bs_write( s, size>>1, 0 );
++    bs_write( s, (size>>1)+1, val );
++}
++
++/* Only works on values under 255. */
++static inline void bs_write_ue( bs_t *s, int val )
++{
++    bs_write( s, x264_ue_size_tab[val+1], val+1 );
++}
++static inline void bs_write_se( bs_t *s, int val )
++{
++    int size = 0;
++    /* Faster than (val <= 0 ? -val*2+1 : val*2) */
++    /* 4 instructions on x86, 3 on ARM */
++    int tmp = 1 - val*2;
++    if( tmp < 0 ) tmp = val*2;
++    val = tmp;
++
++    if( tmp >= 0x100 )
++    {
++        size = 16;
++        tmp >>= 8;
++    }
++    size += x264_ue_size_tab[tmp];
++    bs_write( s, size, val );
++}
++
++static inline void bs_write_te( bs_t *s, int x, int val )
++{
++    if( x == 1 )
++        bs_write1( s, 1^val );
++    else //if( x > 1 )
++        bs_write_ue( s, val );
++}
++
++static inline void bs_rbsp_trailing( bs_t *s )
++{
++	bs_write1( s, 1 );
++	bs_write( s, s->i_left&7, 0  );
++}
++
++static inline int bs_size_ue( unsigned int val )
++{
++	return x264_ue_size_tab[val+1];
++}
++
++static inline int bs_size_ue_big( unsigned int val )
++{
++	if( val < 255 )
++		return x264_ue_size_tab[val+1];
++	else
++		return x264_ue_size_tab[(val+1)>>8] + 16;
++}
++
++static inline int bs_size_se( int val )
++{
++	int tmp = 1 - val*2;
++	if( tmp < 0 ) tmp = val*2;
++	if( tmp < 256 )
++		return x264_ue_size_tab[tmp];
++	else
++		return x264_ue_size_tab[tmp>>8]+16;
++}
++
++static inline int bs_size_te( int x, int val )
++{
++	if( x == 1 )
++		return 1;
++	else //if( x > 1 )
++		return x264_ue_size_tab[val+1];
++}
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/cabac.c b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/cabac.c
+new file mode 100644
+index 000000000..df2d12f9f
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/cabac.c
+@@ -0,0 +1,1334 @@
++#include "common.h"
++
++static const int8_t h264_cabac_context_init_I[1024][2] =
++{
++    /* 0 - 10 */
++    { 20, -15 }, {  2, 54 },  {  3,  74 }, { 20, -15 },
++    {  2,  54 }, {  3, 74 },  { -28,127 }, { -23, 104 },
++    { -6,  53 }, { -1, 54 },  {  7,  51 },
++
++    /* 11 - 23 unused for I */
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },
++
++    /* 24- 39 */
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++
++    /* 40 - 53 */
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },
++
++    /* 54 - 59 */
++    { 0, 0 },    { 0, 0 },    { 0, 0 },      { 0, 0 },
++    { 0, 0 },    { 0, 0 },
++
++    /* 60 - 69 */
++    { 0, 41 },   { 0, 63 },   { 0, 63 },     { 0, 63 },
++    { -9, 83 },  { 4, 86 },   { 0, 97 },     { -7, 72 },
++    { 13, 41 },  { 3, 62 },
++
++    /* 70 -> 87 */
++    { 0, 11 },   { 1, 55 },   { 0, 69 },     { -17, 127 },
++    { -13, 102 },{ 0, 82 },   { -7, 74 },    { -21, 107 },
++    { -27, 127 },{ -31, 127 },{ -24, 127 },  { -18, 95 },
++    { -27, 127 },{ -21, 114 },{ -30, 127 },  { -17, 123 },
++    { -12, 115 },{ -16, 122 },
++
++    /* 88 -> 104 */
++    { -11, 115 },{ -12, 63 }, { -2, 68 },    { -15, 84 },
++    { -13, 104 },{ -3, 70 },  { -8, 93 },    { -10, 90 },
++    { -30, 127 },{ -1, 74 },  { -6, 97 },    { -7, 91 },
++    { -20, 127 },{ -4, 56 },  { -5, 82 },    { -7, 76 },
++    { -22, 125 },
++
++    /* 105 -> 135 */
++    { -7, 93 },  { -11, 87 }, { -3, 77 },    { -5, 71 },
++    { -4, 63 },  { -4, 68 },  { -12, 84 },   { -7, 62 },
++    { -7, 65 },  { 8, 61 },   { 5, 56 },     { -2, 66 },
++    { 1, 64 },   { 0, 61 },   { -2, 78 },    { 1, 50 },
++    { 7, 52 },   { 10, 35 },  { 0, 44 },     { 11, 38 },
++    { 1, 45 },   { 0, 46 },   { 5, 44 },     { 31, 17 },
++    { 1, 51 },   { 7, 50 },   { 28, 19 },    { 16, 33 },
++    { 14, 62 },  { -13, 108 },{ -15, 100 },
++
++    /* 136 -> 165 */
++    { -13, 101 },{ -13, 91 }, { -12, 94 },   { -10, 88 },
++    { -16, 84 }, { -10, 86 }, { -7, 83 },    { -13, 87 },
++    { -19, 94 }, { 1, 70 },   { 0, 72 },     { -5, 74 },
++    { 18, 59 },  { -8, 102 }, { -15, 100 },  { 0, 95 },
++    { -4, 75 },  { 2, 72 },   { -11, 75 },   { -3, 71 },
++    { 15, 46 },  { -13, 69 }, { 0, 62 },     { 0, 65 },
++    { 21, 37 },  { -15, 72 }, { 9, 57 },     { 16, 54 },
++    { 0, 62 },   { 12, 72 },
++
++    /* 166 -> 196 */
++    { 24, 0 },   { 15, 9 },   { 8, 25 },     { 13, 18 },
++    { 15, 9 },   { 13, 19 },  { 10, 37 },    { 12, 18 },
++    { 6, 29 },   { 20, 33 },  { 15, 30 },    { 4, 45 },
++    { 1, 58 },   { 0, 62 },   { 7, 61 },     { 12, 38 },
++    { 11, 45 },  { 15, 39 },  { 11, 42 },    { 13, 44 },
++    { 16, 45 },  { 12, 41 },  { 10, 49 },    { 30, 34 },
++    { 18, 42 },  { 10, 55 },  { 17, 51 },    { 17, 46 },
++    { 0, 89 },   { 26, -19 }, { 22, -17 },
++
++    /* 197 -> 226 */
++    { 26, -17 }, { 30, -25 }, { 28, -20 },   { 33, -23 },
++    { 37, -27 }, { 33, -23 }, { 40, -28 },   { 38, -17 },
++    { 33, -11 }, { 40, -15 }, { 41, -6 },    { 38, 1 },
++    { 41, 17 },  { 30, -6 },  { 27, 3 },     { 26, 22 },
++    { 37, -16 }, { 35, -4 },  { 38, -8 },    { 38, -3 },
++    { 37, 3 },   { 38, 5 },   { 42, 0 },     { 35, 16 },
++    { 39, 22 },  { 14, 48 },  { 27, 37 },    { 21, 60 },
++    { 12, 68 },  { 2, 97 },
++
++    /* 227 -> 251 */
++    { -3, 71 },  { -6, 42 },  { -5, 50 },    { -3, 54 },
++    { -2, 62 },  { 0, 58 },   { 1, 63 },     { -2, 72 },
++    { -1, 74 },  { -9, 91 },  { -5, 67 },    { -5, 27 },
++    { -3, 39 },  { -2, 44 },  { 0, 46 },     { -16, 64 },
++    { -8, 68 },  { -10, 78 }, { -6, 77 },    { -10, 86 },
++    { -12, 92 }, { -15, 55 }, { -10, 60 },   { -6, 62 },
++    { -4, 65 },
++
++    /* 252 -> 275 */
++    { -12, 73 }, { -8, 76 },  { -7, 80 },    { -9, 88 },
++    { -17, 110 },{ -11, 97 }, { -20, 84 },   { -11, 79 },
++    { -6, 73 },  { -4, 74 },  { -13, 86 },   { -13, 96 },
++    { -11, 97 }, { -19, 117 },{ -8, 78 },    { -5, 33 },
++    { -4, 48 },  { -2, 53 },  { -3, 62 },    { -13, 71 },
++    { -10, 79 }, { -12, 86 }, { -13, 90 },   { -14, 97 },
++
++    /* 276 a bit special (not used, h264_cabac_encode_bypass is used instead) */
++    { 0, 0 },
++
++    /* 277 -> 307 */
++    { -6, 93 },  { -6, 84 },  { -8, 79 },    { 0, 66 },
++    { -1, 71 },  { 0, 62 },   { -2, 60 },    { -2, 59 },
++    { -5, 75 },  { -3, 62 },  { -4, 58 },    { -9, 66 },
++    { -1, 79 },  { 0, 71 },   { 3, 68 },     { 10, 44 },
++    { -7, 62 },  { 15, 36 },  { 14, 40 },    { 16, 27 },
++    { 12, 29 },  { 1, 44 },   { 20, 36 },    { 18, 32 },
++    { 5, 42 },   { 1, 48 },   { 10, 62 },    { 17, 46 },
++    { 9, 64 },   { -12, 104 },{ -11, 97 },
++
++    /* 308 -> 337 */
++    { -16, 96 }, { -7, 88 },  { -8, 85 },    { -7, 85 },
++    { -9, 85 },  { -13, 88 }, { 4, 66 },     { -3, 77 },
++    { -3, 76 },  { -6, 76 },  { 10, 58 },    { -1, 76 },
++    { -1, 83 },  { -7, 99 },  { -14, 95 },   { 2, 95 },
++    { 0, 76 },   { -5, 74 },  { 0, 70 },     { -11, 75 },
++    { 1, 68 },   { 0, 65 },   { -14, 73 },   { 3, 62 },
++    { 4, 62 },   { -1, 68 },  { -13, 75 },   { 11, 55 },
++    { 5, 64 },   { 12, 70 },
++
++    /* 338 -> 368 */
++    { 15, 6 },   { 6, 19 },   { 7, 16 },     { 12, 14 },
++    { 18, 13 },  { 13, 11 },  { 13, 15 },    { 15, 16 },
++    { 12, 23 },  { 13, 23 },  { 15, 20 },    { 14, 26 },
++    { 14, 44 },  { 17, 40 },  { 17, 47 },    { 24, 17 },
++    { 21, 21 },  { 25, 22 },  { 31, 27 },    { 22, 29 },
++    { 19, 35 },  { 14, 50 },  { 10, 57 },    { 7, 63 },
++    { -2, 77 },  { -4, 82 },  { -3, 94 },    { 9, 69 },
++    { -12, 109 },{ 36, -35 }, { 36, -34 },
++
++    /* 369 -> 398 */
++    { 32, -26 }, { 37, -30 }, { 44, -32 },   { 34, -18 },
++    { 34, -15 }, { 40, -15 }, { 33, -7 },    { 35, -5 },
++    { 33, 0 },   { 38, 2 },   { 33, 13 },    { 23, 35 },
++    { 13, 58 },  { 29, -3 },  { 26, 0 },     { 22, 30 },
++    { 31, -7 },  { 35, -15 }, { 34, -3 },    { 34, 3 },
++    { 36, -1 },  { 34, 5 },   { 32, 11 },    { 35, 5 },
++    { 34, 12 },  { 39, 11 },  { 30, 29 },    { 34, 26 },
++    { 29, 39 },  { 19, 66 },
++
++    /* 399 -> 435 */
++    {  31,  21 }, {  31,  31 }, {  25,  50 },
++    { -17, 120 }, { -20, 112 }, { -18, 114 }, { -11,  85 },
++    { -15,  92 }, { -14,  89 }, { -26,  71 }, { -15,  81 },
++    { -14,  80 }, {   0,  68 }, { -14,  70 }, { -24,  56 },
++    { -23,  68 }, { -24,  50 }, { -11,  74 }, {  23, -13 },
++    {  26, -13 }, {  40, -15 }, {  49, -14 }, {  44,   3 },
++    {  45,   6 }, {  44,  34 }, {  33,  54 }, {  19,  82 },
++    {  -3,  75 }, {  -1,  23 }, {   1,  34 }, {   1,  43 },
++    {   0,  54 }, {  -2,  55 }, {   0,  61 }, {   1,  64 },
++    {   0,  68 }, {  -9,  92 },
++
++    /* 436 -> 459 */
++    { -14, 106 }, { -13,  97 }, { -15,  90 }, { -12,  90 },
++    { -18,  88 }, { -10,  73 }, {  -9,  79 }, { -14,  86 },
++    { -10,  73 }, { -10,  70 }, { -10,  69 }, {  -5,  66 },
++    {  -9,  64 }, {  -5,  58 }, {   2,  59 }, {  21, -10 },
++    {  24, -11 }, {  28,  -8 }, {  28,  -1 }, {  29,   3 },
++    {  29,   9 }, {  35,  20 }, {  29,  36 }, {  14,  67 },
++
++    /* 460 -> 1024 */
++    { -17, 123 }, { -12, 115 }, { -16, 122 }, { -11, 115 },
++    { -12,  63 }, {  -2,  68 }, { -15,  84 }, { -13, 104 },
++    {  -3,  70 }, {  -8,  93 }, { -10,  90 }, { -30, 127 },
++    { -17, 123 }, { -12, 115 }, { -16, 122 }, { -11, 115 },
++    { -12,  63 }, {  -2,  68 }, { -15,  84 }, { -13, 104 },
++    {  -3,  70 }, {  -8,  93 }, { -10,  90 }, { -30, 127 },
++    {  -7,  93 }, { -11,  87 }, {  -3,  77 }, {  -5,  71 },
++    {  -4,  63 }, {  -4,  68 }, { -12,  84 }, {  -7,  62 },
++    {  -7,  65 }, {   8,  61 }, {   5,  56 }, {  -2,  66 },
++    {   1,  64 }, {   0,  61 }, {  -2,  78 }, {   1,  50 },
++    {   7,  52 }, {  10,  35 }, {   0,  44 }, {  11,  38 },
++    {   1,  45 }, {   0,  46 }, {   5,  44 }, {  31,  17 },
++    {   1,  51 }, {   7,  50 }, {  28,  19 }, {  16,  33 },
++    {  14,  62 }, { -13, 108 }, { -15, 100 }, { -13, 101 },
++    { -13,  91 }, { -12,  94 }, { -10,  88 }, { -16,  84 },
++    { -10,  86 }, {  -7,  83 }, { -13,  87 }, { -19,  94 },
++    {   1,  70 }, {   0,  72 }, {  -5,  74 }, {  18,  59 },
++    {  -7,  93 }, { -11,  87 }, {  -3,  77 }, {  -5,  71 },
++    {  -4,  63 }, {  -4,  68 }, { -12,  84 }, {  -7,  62 },
++    {  -7,  65 }, {   8,  61 }, {   5,  56 }, {  -2,  66 },
++    {   1,  64 }, {   0,  61 }, {  -2,  78 }, {   1,  50 },
++    {   7,  52 }, {  10,  35 }, {   0,  44 }, {  11,  38 },
++    {   1,  45 }, {   0,  46 }, {   5,  44 }, {  31,  17 },
++    {   1,  51 }, {   7,  50 }, {  28,  19 }, {  16,  33 },
++    {  14,  62 }, { -13, 108 }, { -15, 100 }, { -13, 101 },
++    { -13,  91 }, { -12,  94 }, { -10,  88 }, { -16,  84 },
++    { -10,  86 }, {  -7,  83 }, { -13,  87 }, { -19,  94 },
++    {   1,  70 }, {   0,  72 }, {  -5,  74 }, {  18,  59 },
++    {  24,   0 }, {  15,   9 }, {   8,  25 }, {  13,  18 },
++    {  15,   9 }, {  13,  19 }, {  10,  37 }, {  12,  18 },
++    {   6,  29 }, {  20,  33 }, {  15,  30 }, {   4,  45 },
++    {   1,  58 }, {   0,  62 }, {   7,  61 }, {  12,  38 },
++    {  11,  45 }, {  15,  39 }, {  11,  42 }, {  13,  44 },
++    {  16,  45 }, {  12,  41 }, {  10,  49 }, {  30,  34 },
++    {  18,  42 }, {  10,  55 }, {  17,  51 }, {  17,  46 },
++    {   0,  89 }, {  26, -19 }, {  22, -17 }, {  26, -17 },
++    {  30, -25 }, {  28, -20 }, {  33, -23 }, {  37, -27 },
++    {  33, -23 }, {  40, -28 }, {  38, -17 }, {  33, -11 },
++    {  40, -15 }, {  41,  -6 }, {  38,   1 }, {  41,  17 },
++    {  24,   0 }, {  15,   9 }, {   8,  25 }, {  13,  18 },
++    {  15,   9 }, {  13,  19 }, {  10,  37 }, {  12,  18 },
++    {   6,  29 }, {  20,  33 }, {  15,  30 }, {   4,  45 },
++    {   1,  58 }, {   0,  62 }, {   7,  61 }, {  12,  38 },
++    {  11,  45 }, {  15,  39 }, {  11,  42 }, {  13,  44 },
++    {  16,  45 }, {  12,  41 }, {  10,  49 }, {  30,  34 },
++    {  18,  42 }, {  10,  55 }, {  17,  51 }, {  17,  46 },
++    {   0,  89 }, {  26, -19 }, {  22, -17 }, {  26, -17 },
++    {  30, -25 }, {  28, -20 }, {  33, -23 }, {  37, -27 },
++    {  33, -23 }, {  40, -28 }, {  38, -17 }, {  33, -11 },
++    {  40, -15 }, {  41,  -6 }, {  38,   1 }, {  41,  17 },
++    { -17, 120 }, { -20, 112 }, { -18, 114 }, { -11,  85 },
++    { -15,  92 }, { -14,  89 }, { -26,  71 }, { -15,  81 },
++    { -14,  80 }, {   0,  68 }, { -14,  70 }, { -24,  56 },
++    { -23,  68 }, { -24,  50 }, { -11,  74 }, { -14, 106 },
++    { -13,  97 }, { -15,  90 }, { -12,  90 }, { -18,  88 },
++    { -10,  73 }, {  -9,  79 }, { -14,  86 }, { -10,  73 },
++    { -10,  70 }, { -10,  69 }, {  -5,  66 }, {  -9,  64 },
++    {  -5,  58 }, {   2,  59 }, {  23, -13 }, {  26, -13 },
++    {  40, -15 }, {  49, -14 }, {  44,   3 }, {  45,   6 },
++    {  44,  34 }, {  33,  54 }, {  19,  82 }, {  21, -10 },
++    {  24, -11 }, {  28,  -8 }, {  28,  -1 }, {  29,   3 },
++    {  29,   9 }, {  35,  20 }, {  29,  36 }, {  14,  67 },
++    {  -3,  75 }, {  -1,  23 }, {   1,  34 }, {   1,  43 },
++    {   0,  54 }, {  -2,  55 }, {   0,  61 }, {   1,  64 },
++    {   0,  68 }, {  -9,  92 }, { -17, 120 }, { -20, 112 },
++    { -18, 114 }, { -11,  85 }, { -15,  92 }, { -14,  89 },
++    { -26,  71 }, { -15,  81 }, { -14,  80 }, {   0,  68 },
++    { -14,  70 }, { -24,  56 }, { -23,  68 }, { -24,  50 },
++    { -11,  74 }, { -14, 106 }, { -13,  97 }, { -15,  90 },
++    { -12,  90 }, { -18,  88 }, { -10,  73 }, {  -9,  79 },
++    { -14,  86 }, { -10,  73 }, { -10,  70 }, { -10,  69 },
++    {  -5,  66 }, {  -9,  64 }, {  -5,  58 }, {   2,  59 },
++    {  23, -13 }, {  26, -13 }, {  40, -15 }, {  49, -14 },
++    {  44,   3 }, {  45,   6 }, {  44,  34 }, {  33,  54 },
++    {  19,  82 }, {  21, -10 }, {  24, -11 }, {  28,  -8 },
++    {  28,  -1 }, {  29,   3 }, {  29,   9 }, {  35,  20 },
++    {  29,  36 }, {  14,  67 }, {  -3,  75 }, {  -1,  23 },
++    {   1,  34 }, {   1,  43 }, {   0,  54 }, {  -2,  55 },
++    {   0,  61 }, {   1,  64 }, {   0,  68 }, {  -9,  92 },
++    {  -6,  93 }, {  -6,  84 }, {  -8,  79 }, {   0,  66 },
++    {  -1,  71 }, {   0,  62 }, {  -2,  60 }, {  -2,  59 },
++    {  -5,  75 }, {  -3,  62 }, {  -4,  58 }, {  -9,  66 },
++    {  -1,  79 }, {   0,  71 }, {   3,  68 }, {  10,  44 },
++    {  -7,  62 }, {  15,  36 }, {  14,  40 }, {  16,  27 },
++    {  12,  29 }, {   1,  44 }, {  20,  36 }, {  18,  32 },
++    {   5,  42 }, {   1,  48 }, {  10,  62 }, {  17,  46 },
++    {   9,  64 }, { -12, 104 }, { -11,  97 }, { -16,  96 },
++    {  -7,  88 }, {  -8,  85 }, {  -7,  85 }, {  -9,  85 },
++    { -13,  88 }, {   4,  66 }, {  -3,  77 }, {  -3,  76 },
++    {  -6,  76 }, {  10,  58 }, {  -1,  76 }, {  -1,  83 },
++    {  -6,  93 }, {  -6,  84 }, {  -8,  79 }, {   0,  66 },
++    {  -1,  71 }, {   0,  62 }, {  -2,  60 }, {  -2,  59 },
++    {  -5,  75 }, {  -3,  62 }, {  -4,  58 }, {  -9,  66 },
++    {  -1,  79 }, {   0,  71 }, {   3,  68 }, {  10,  44 },
++    {  -7,  62 }, {  15,  36 }, {  14,  40 }, {  16,  27 },
++    {  12,  29 }, {   1,  44 }, {  20,  36 }, {  18,  32 },
++    {   5,  42 }, {   1,  48 }, {  10,  62 }, {  17,  46 },
++    {   9,  64 }, { -12, 104 }, { -11,  97 }, { -16,  96 },
++    {  -7,  88 }, {  -8,  85 }, {  -7,  85 }, {  -9,  85 },
++    { -13,  88 }, {   4,  66 }, {  -3,  77 }, {  -3,  76 },
++    {  -6,  76 }, {  10,  58 }, {  -1,  76 }, {  -1,  83 },
++    {  15,   6 }, {   6,  19 }, {   7,  16 }, {  12,  14 },
++    {  18,  13 }, {  13,  11 }, {  13,  15 }, {  15,  16 },
++    {  12,  23 }, {  13,  23 }, {  15,  20 }, {  14,  26 },
++    {  14,  44 }, {  17,  40 }, {  17,  47 }, {  24,  17 },
++    {  21,  21 }, {  25,  22 }, {  31,  27 }, {  22,  29 },
++    {  19,  35 }, {  14,  50 }, {  10,  57 }, {   7,  63 },
++    {  -2,  77 }, {  -4,  82 }, {  -3,  94 }, {   9,  69 },
++    { -12, 109 }, {  36, -35 }, {  36, -34 }, {  32, -26 },
++    {  37, -30 }, {  44, -32 }, {  34, -18 }, {  34, -15 },
++    {  40, -15 }, {  33,  -7 }, {  35,  -5 }, {  33,   0 },
++    {  38,   2 }, {  33,  13 }, {  23,  35 }, {  13,  58 },
++    {  15,   6 }, {   6,  19 }, {   7,  16 }, {  12,  14 },
++    {  18,  13 }, {  13,  11 }, {  13,  15 }, {  15,  16 },
++    {  12,  23 }, {  13,  23 }, {  15,  20 }, {  14,  26 },
++    {  14,  44 }, {  17,  40 }, {  17,  47 }, {  24,  17 },
++    {  21,  21 }, {  25,  22 }, {  31,  27 }, {  22,  29 },
++    {  19,  35 }, {  14,  50 }, {  10,  57 }, {   7,  63 },
++    {  -2,  77 }, {  -4,  82 }, {  -3,  94 }, {   9,  69 },
++    { -12, 109 }, {  36, -35 }, {  36, -34 }, {  32, -26 },
++    {  37, -30 }, {  44, -32 }, {  34, -18 }, {  34, -15 },
++    {  40, -15 }, {  33,  -7 }, {  35,  -5 }, {  33,   0 },
++    {  38,   2 }, {  33,  13 }, {  23,  35 }, {  13,  58 },
++    {  -3,  71 }, {  -6,  42 }, {  -5,  50 }, {  -3,  54 },
++    {  -2,  62 }, {   0,  58 }, {   1,  63 }, {  -2,  72 },
++    {  -1,  74 }, {  -9,  91 }, {  -5,  67 }, {  -5,  27 },
++    {  -3,  39 }, {  -2,  44 }, {   0,  46 }, { -16,  64 },
++    {  -8,  68 }, { -10,  78 }, {  -6,  77 }, { -10,  86 },
++    { -12,  92 }, { -15,  55 }, { -10,  60 }, {  -6,  62 },
++    {  -4,  65 }, { -12,  73 }, {  -8,  76 }, {  -7,  80 },
++    {  -9,  88 }, { -17, 110 }, {  -3,  71 }, {  -6,  42 },
++    {  -5,  50 }, {  -3,  54 }, {  -2,  62 }, {   0,  58 },
++    {   1,  63 }, {  -2,  72 }, {  -1,  74 }, {  -9,  91 },
++    {  -5,  67 }, {  -5,  27 }, {  -3,  39 }, {  -2,  44 },
++    {   0,  46 }, { -16,  64 }, {  -8,  68 }, { -10,  78 },
++    {  -6,  77 }, { -10,  86 }, { -12,  92 }, { -15,  55 },
++    { -10,  60 }, {  -6,  62 }, {  -4,  65 }, { -12,  73 },
++    {  -8,  76 }, {  -7,  80 }, {  -9,  88 }, { -17, 110 },
++    {  -3,  70 }, {  -8,  93 }, { -10,  90 }, { -30, 127 },
++    {  -3,  70 }, {  -8,  93 }, { -10,  90 }, { -30, 127 },
++    {  -3,  70 }, {  -8,  93 }, { -10,  90 }, { -30, 127 }
++};
++
++static const int8_t h264_cabac_context_init_PB[3][1024][2] =
++{
++    /* i_cabac_init_idc == 0 */
++    {
++        /* 0 - 10 */
++        {  20, -15 }, {   2,  54 }, {   3,  74 }, {  20, -15 },
++        {   2,  54 }, {   3,  74 }, { -28, 127 }, { -23, 104 },
++        {  -6,  53 }, {  -1,  54 }, {   7,  51 },
++
++        /* 11 - 23 */
++        {  23,  33 }, {  23,   2 }, {  21,   0 }, {   1,   9 },
++        {   0,  49 }, { -37, 118 }, {   5,  57 }, { -13,  78 },
++        { -11,  65 }, {   1,  62 }, {  12,  49 }, {  -4,  73 },
++        {  17,  50 },
++
++        /* 24 - 39 */
++        {  18,  64 }, {   9,  43 }, {  29,   0 }, {  26,  67 },
++        {  16,  90 }, {   9, 104 }, { -46, 127 }, { -20, 104 },
++        {   1,  67 }, { -13,  78 }, { -11,  65 }, {   1,  62 },
++        {  -6,  86 }, { -17,  95 }, {  -6,  61 }, {   9,  45 },
++
++        /* 40 - 53 */
++        {  -3,  69 }, {  -6,  81 }, { -11,  96 }, {   6,  55 },
++        {   7,  67 }, {  -5,  86 }, {   2,  88 }, {   0,  58 },
++        {  -3,  76 }, { -10,  94 }, {   5,  54 }, {   4,  69 },
++        {  -3,  81 }, {   0,  88 },
++
++        /* 54 - 59 */
++        {  -7,  67 }, {  -5,  74 }, {  -4,  74 }, {  -5,  80 },
++        {  -7,  72 }, {   1,  58 },
++
++        /* 60 - 69 */
++        {   0,  41 }, {   0,  63 }, {   0,  63 }, { 0, 63 },
++        {  -9,  83 }, {   4,  86 }, {   0,  97 }, { -7, 72 },
++        {  13,  41 }, {   3,  62 },
++
++        /* 70 - 87 */
++        {   0,  45 }, {  -4,  78 }, {  -3,  96 }, { -27,  126 },
++        { -28,  98 }, { -25, 101 }, { -23,  67 }, { -28,  82 },
++        { -20,  94 }, { -16,  83 }, { -22, 110 }, { -21,  91 },
++        { -18, 102 }, { -13,  93 }, { -29, 127 }, {  -7,  92 },
++        {  -5,  89 }, {  -7,  96 }, { -13, 108 }, {  -3,  46 },
++        {  -1,  65 }, {  -1,  57 }, {  -9,  93 }, {  -3,  74 },
++        {  -9,  92 }, {  -8,  87 }, { -23, 126 }, {   5,  54 },
++        {   6,  60 }, {   6,  59 }, {   6,  69 }, {  -1,  48 },
++        {   0,  68 }, {  -4,  69 }, {  -8,  88 },
++
++        /* 105 -> 165 */
++        {  -2,  85 }, {  -6,  78 }, {  -1,  75 }, {  -7,  77 },
++        {   2,  54 }, {   5,  50 }, {  -3,  68 }, {   1,  50 },
++        {   6,  42 }, {  -4,  81 }, {   1,  63 }, {  -4,  70 },
++        {   0,  67 }, {   2,  57 }, {  -2,  76 }, {  11,  35 },
++        {   4,  64 }, {   1,  61 }, {  11,  35 }, {  18,  25 },
++        {  12,  24 }, {  13,  29 }, {  13,  36 }, { -10,  93 },
++        {  -7,  73 }, {  -2,  73 }, {  13,  46 }, {   9,  49 },
++        {  -7, 100 }, {   9,  53 }, {   2,  53 }, {   5,  53 },
++        {  -2,  61 }, {   0,  56 }, {   0,  56 }, { -13,  63 },
++        {  -5,  60 }, {  -1,  62 }, {   4,  57 }, {  -6,  69 },
++        {   4,  57 }, {  14,  39 }, {   4,  51 }, {  13,  68 },
++        {   3,  64 }, {   1,  61 }, {   9,  63 }, {   7,  50 },
++        {  16,  39 }, {   5,  44 }, {   4,  52 }, {  11,  48 },
++        {  -5,  60 }, {  -1,  59 }, {   0,  59 }, {  22,  33 },
++        {   5,  44 }, {  14,  43 }, {  -1,  78 }, {   0,  60 },
++        {   9,  69 },
++
++        /* 166 - 226 */
++        {  11,  28 }, {   2,  40 }, {   3,  44 }, {   0,  49 },
++        {   0,  46 }, {   2,  44 }, {   2,  51 }, {   0,  47 },
++        {   4,  39 }, {   2,  62 }, {   6,  46 }, {   0,  54 },
++        {   3,  54 }, {   2,  58 }, {   4,  63 }, {   6,  51 },
++        {   6,  57 }, {   7,  53 }, {   6,  52 }, {   6,  55 },
++        {  11,  45 }, {  14,  36 }, {   8,  53 }, {  -1,  82 },
++        {   7,  55 }, {  -3,  78 }, {  15,  46 }, {  22,  31 },
++        {  -1,  84 }, {  25,   7 }, {  30,  -7 }, {  28,   3 },
++        {  28,   4 }, {  32,   0 }, {  34,  -1 }, {  30,   6 },
++        {  30,   6 }, {  32,   9 }, {  31,  19 }, {  26,  27 },
++        {  26,  30 }, {  37,  20 }, {  28,  34 }, {  17,  70 },
++        {   1,  67 }, {   5,  59 }, {   9,  67 }, {  16,  30 },
++        {  18,  32 }, {  18,  35 }, {  22,  29 }, {  24,  31 },
++        {  23,  38 }, {  18,  43 }, {  20,  41 }, {  11,  63 },
++        {   9,  59 }, {   9,  64 }, {  -1,  94 }, {  -2,  89 },
++        {  -9, 108 },
++
++        /* 227 - 275 */
++        {  -6,  76 }, {  -2,  44 }, {   0,  45 }, {   0,  52 },
++        {  -3,  64 }, {  -2,  59 }, {  -4,  70 }, {  -4,  75 },
++        {  -8,  82 }, { -17, 102 }, {  -9,  77 }, {   3,  24 },
++        {   0,  42 }, {   0,  48 }, {   0,  55 }, {  -6,  59 },
++        {  -7,  71 }, { -12,  83 }, { -11,  87 }, { -30, 119 },
++        {   1,  58 }, {  -3,  29 }, {  -1,  36 }, {   1,  38 },
++        {   2,  43 }, {  -6,  55 }, {   0,  58 }, {   0,  64 },
++        {  -3,  74 }, { -10,  90 }, {   0,  70 }, {  -4,  29 },
++        {   5,  31 }, {   7,  42 }, {   1,  59 }, {  -2,  58 },
++        {  -3,  72 }, {  -3,  81 }, { -11,  97 }, {   0,  58 },
++        {   8,   5 }, {  10,  14 }, {  14,  18 }, {  13,  27 },
++        {   2,  40 }, {   0,  58 }, {  -3,  70 }, {  -6,  79 },
++        {  -8,  85 },
++
++        /* 276 a bit special (not used, h264_cabac_encode_bypass is used instead) */
++        { 0, 0 },
++
++        /* 277 - 337 */
++        { -13, 106 }, { -16, 106 }, { -10,  87 }, { -21, 114 },
++        { -18, 110 }, { -14,  98 }, { -22, 110 }, { -21, 106 },
++        { -18, 103 }, { -21, 107 }, { -23, 108 }, { -26, 112 },
++        { -10,  96 }, { -12,  95 }, {  -5,  91 }, {  -9,  93 },
++        { -22,  94 }, {  -5,  86 }, {   9,  67 }, {  -4,  80 },
++        { -10,  85 }, {  -1,  70 }, {   7,  60 }, {   9,  58 },
++        {   5,  61 }, {  12,  50 }, {  15,  50 }, {  18,  49 },
++        {  17,  54 }, {  10,  41 }, {   7,  46 }, {  -1,  51 },
++        {   7,  49 }, {   8,  52 }, {   9,  41 }, {   6,  47 },
++        {   2,  55 }, {  13,  41 }, {  10,  44 }, {   6,  50 },
++        {   5,  53 }, {  13,  49 }, {   4,  63 }, {   6,  64 },
++        {  -2,  69 }, {  -2,  59 }, {   6,  70 }, {  10,  44 },
++        {   9,  31 }, {  12,  43 }, {   3,  53 }, {  14,  34 },
++        {  10,  38 }, {  -3,  52 }, {  13,  40 }, {  17,  32 },
++        {   7,  44 }, {   7,  38 }, {  13,  50 }, {  10,  57 },
++        {  26,  43 },
++
++        /* 338 - 398 */
++        {  14,  11 }, {  11,  14 }, {   9,  11 }, {  18,  11 },
++        {  21,   9 }, {  23,  -2 }, {  32, -15 }, {  32, -15 },
++        {  34, -21 }, {  39, -23 }, {  42, -33 }, {  41, -31 },
++        {  46, -28 }, {  38, -12 }, {  21,  29 }, {  45, -24 },
++        {  53, -45 }, {  48, -26 }, {  65, -43 }, {  43, -19 },
++        {  39, -10 }, {  30,   9 }, {  18,  26 }, {  20,  27 },
++        {   0,  57 }, { -14,  82 }, {  -5,  75 }, { -19,  97 },
++        { -35, 125 }, {  27,   0 }, {  28,   0 }, {  31,  -4 },
++        {  27,   6 }, {  34,   8 }, {  30,  10 }, {  24,  22 },
++        {  33,  19 }, {  22,  32 }, {  26,  31 }, {  21,  41 },
++        {  26,  44 }, {  23,  47 }, {  16,  65 }, {  14,  71 },
++        {   8,  60 }, {   6,  63 }, {  17,  65 }, {  21,  24 },
++        {  23,  20 }, {  26,  23 }, {  27,  32 }, {  28,  23 },
++        {  28,  24 }, {  23,  40 }, {  24,  32 }, {  28,  29 },
++        {  23,  42 }, {  19,  57 }, {  22,  53 }, {  22,  61 },
++        {  11,  86 },
++
++        /* 399 -> 435 */
++        {  12,  40 }, {  11,  51 }, {  14,  59 },
++        {  -4,  79 }, {  -7,  71 }, {  -5,  69 }, {  -9,  70 },
++        {  -8,  66 }, { -10,  68 }, { -19,  73 }, { -12,  69 },
++        { -16,  70 }, { -15,  67 }, { -20,  62 }, { -19,  70 },
++        { -16,  66 }, { -22,  65 }, { -20,  63 }, {   9,  -2 },
++        {  26,  -9 }, {  33,  -9 }, {  39,  -7 }, {  41,  -2 },
++        {  45,   3 }, {  49,   9 }, {  45,  27 }, {  36,  59 },
++        {  -6,  66 }, {  -7,  35 }, {  -7,  42 }, {  -8,  45 },
++        {  -5,  48 }, { -12,  56 }, {  -6,  60 }, {  -5,  62 },
++        {  -8,  66 }, {  -8,  76 },
++
++        /* 436 -> 459 */
++        {  -5,  85 }, {  -6,  81 }, { -10,  77 }, {  -7,  81 },
++        { -17,  80 }, { -18,  73 }, {  -4,  74 }, { -10,  83 },
++        {  -9,  71 }, {  -9,  67 }, {  -1,  61 }, {  -8,  66 },
++        { -14,  66 }, {   0,  59 }, {   2,  59 }, {  21, -13 },
++        {  33, -14 }, {  39,  -7 }, {  46,  -2 }, {  51,   2 },
++        {  60,   6 }, {  61,  17 }, {  55,  34 }, {  42,  62 },
++
++        /* 460 - 1024 */
++        {  -7,  92 }, {  -5,  89 }, {  -7,  96 }, { -13, 108 },
++        {  -3,  46 }, {  -1,  65 }, {  -1,  57 }, {  -9,  93 },
++        {  -3,  74 }, {  -9,  92 }, {  -8,  87 }, { -23, 126 },
++        {  -7,  92 }, {  -5,  89 }, {  -7,  96 }, { -13, 108 },
++        {  -3,  46 }, {  -1,  65 }, {  -1,  57 }, {  -9,  93 },
++        {  -3,  74 }, {  -9,  92 }, {  -8,  87 }, { -23, 126 },
++        {  -2,  85 }, {  -6,  78 }, {  -1,  75 }, {  -7,  77 },
++        {   2,  54 }, {   5,  50 }, {  -3,  68 }, {   1,  50 },
++        {   6,  42 }, {  -4,  81 }, {   1,  63 }, {  -4,  70 },
++        {   0,  67 }, {   2,  57 }, {  -2,  76 }, {  11,  35 },
++        {   4,  64 }, {   1,  61 }, {  11,  35 }, {  18,  25 },
++        {  12,  24 }, {  13,  29 }, {  13,  36 }, { -10,  93 },
++        {  -7,  73 }, {  -2,  73 }, {  13,  46 }, {   9,  49 },
++        {  -7, 100 }, {   9,  53 }, {   2,  53 }, {   5,  53 },
++        {  -2,  61 }, {   0,  56 }, {   0,  56 }, { -13,  63 },
++        {  -5,  60 }, {  -1,  62 }, {   4,  57 }, {  -6,  69 },
++        {   4,  57 }, {  14,  39 }, {   4,  51 }, {  13,  68 },
++        {  -2,  85 }, {  -6,  78 }, {  -1,  75 }, {  -7,  77 },
++        {   2,  54 }, {   5,  50 }, {  -3,  68 }, {   1,  50 },
++        {   6,  42 }, {  -4,  81 }, {   1,  63 }, {  -4,  70 },
++        {   0,  67 }, {   2,  57 }, {  -2,  76 }, {  11,  35 },
++        {   4,  64 }, {   1,  61 }, {  11,  35 }, {  18,  25 },
++        {  12,  24 }, {  13,  29 }, {  13,  36 }, { -10,  93 },
++        {  -7,  73 }, {  -2,  73 }, {  13,  46 }, {   9,  49 },
++        {  -7, 100 }, {   9,  53 }, {   2,  53 }, {   5,  53 },
++        {  -2,  61 }, {   0,  56 }, {   0,  56 }, { -13,  63 },
++        {  -5,  60 }, {  -1,  62 }, {   4,  57 }, {  -6,  69 },
++        {   4,  57 }, {  14,  39 }, {   4,  51 }, {  13,  68 },
++        {  11,  28 }, {   2,  40 }, {   3,  44 }, {   0,  49 },
++        {   0,  46 }, {   2,  44 }, {   2,  51 }, {   0,  47 },
++        {   4,  39 }, {   2,  62 }, {   6,  46 }, {   0,  54 },
++        {   3,  54 }, {   2,  58 }, {   4,  63 }, {   6,  51 },
++        {   6,  57 }, {   7,  53 }, {   6,  52 }, {   6,  55 },
++        {  11,  45 }, {  14,  36 }, {   8,  53 }, {  -1,  82 },
++        {   7,  55 }, {  -3,  78 }, {  15,  46 }, {  22,  31 },
++        {  -1,  84 }, {  25,   7 }, {  30,  -7 }, {  28,   3 },
++        {  28,   4 }, {  32,   0 }, {  34,  -1 }, {  30,   6 },
++        {  30,   6 }, {  32,   9 }, {  31,  19 }, {  26,  27 },
++        {  26,  30 }, {  37,  20 }, {  28,  34 }, {  17,  70 },
++        {  11,  28 }, {   2,  40 }, {   3,  44 }, {   0,  49 },
++        {   0,  46 }, {   2,  44 }, {   2,  51 }, {   0,  47 },
++        {   4,  39 }, {   2,  62 }, {   6,  46 }, {   0,  54 },
++        {   3,  54 }, {   2,  58 }, {   4,  63 }, {   6,  51 },
++        {   6,  57 }, {   7,  53 }, {   6,  52 }, {   6,  55 },
++        {  11,  45 }, {  14,  36 }, {   8,  53 }, {  -1,  82 },
++        {   7,  55 }, {  -3,  78 }, {  15,  46 }, {  22,  31 },
++        {  -1,  84 }, {  25,   7 }, {  30,  -7 }, {  28,   3 },
++        {  28,   4 }, {  32,   0 }, {  34,  -1 }, {  30,   6 },
++        {  30,   6 }, {  32,   9 }, {  31,  19 }, {  26,  27 },
++        {  26,  30 }, {  37,  20 }, {  28,  34 }, {  17,  70 },
++        {  -4,  79 }, {  -7,  71 }, {  -5,  69 }, {  -9,  70 },
++        {  -8,  66 }, { -10,  68 }, { -19,  73 }, { -12,  69 },
++        { -16,  70 }, { -15,  67 }, { -20,  62 }, { -19,  70 },
++        { -16,  66 }, { -22,  65 }, { -20,  63 }, {  -5,  85 },
++        {  -6,  81 }, { -10,  77 }, {  -7,  81 }, { -17,  80 },
++        { -18,  73 }, {  -4,  74 }, { -10,  83 }, {  -9,  71 },
++        {  -9,  67 }, {  -1,  61 }, {  -8,  66 }, { -14,  66 },
++        {   0,  59 }, {   2,  59 }, {   9,  -2 }, {  26,  -9 },
++        {  33,  -9 }, {  39,  -7 }, {  41,  -2 }, {  45,   3 },
++        {  49,   9 }, {  45,  27 }, {  36,  59 }, {  21, -13 },
++        {  33, -14 }, {  39,  -7 }, {  46,  -2 }, {  51,   2 },
++        {  60,   6 }, {  61,  17 }, {  55,  34 }, {  42,  62 },
++        {  -6,  66 }, {  -7,  35 }, {  -7,  42 }, {  -8,  45 },
++        {  -5,  48 }, { -12,  56 }, {  -6,  60 }, {  -5,  62 },
++        {  -8,  66 }, {  -8,  76 }, {  -4,  79 }, {  -7,  71 },
++        {  -5,  69 }, {  -9,  70 }, {  -8,  66 }, { -10,  68 },
++        { -19,  73 }, { -12,  69 }, { -16,  70 }, { -15,  67 },
++        { -20,  62 }, { -19,  70 }, { -16,  66 }, { -22,  65 },
++        { -20,  63 }, {  -5,  85 }, {  -6,  81 }, { -10,  77 },
++        {  -7,  81 }, { -17,  80 }, { -18,  73 }, {  -4,  74 },
++        { -10,  83 }, {  -9,  71 }, {  -9,  67 }, {  -1,  61 },
++        {  -8,  66 }, { -14,  66 }, {   0,  59 }, {   2,  59 },
++        {   9,  -2 }, {  26,  -9 }, {  33,  -9 }, {  39,  -7 },
++        {  41,  -2 }, {  45,   3 }, {  49,   9 }, {  45,  27 },
++        {  36,  59 }, {  21, -13 }, {  33, -14 }, {  39,  -7 },
++        {  46,  -2 }, {  51,   2 }, {  60,   6 }, {  61,  17 },
++        {  55,  34 }, {  42,  62 }, {  -6,  66 }, {  -7,  35 },
++        {  -7,  42 }, {  -8,  45 }, {  -5,  48 }, { -12,  56 },
++        {  -6,  60 }, {  -5,  62 }, {  -8,  66 }, {  -8,  76 },
++        { -13, 106 }, { -16, 106 }, { -10,  87 }, { -21, 114 },
++        { -18, 110 }, { -14,  98 }, { -22, 110 }, { -21, 106 },
++        { -18, 103 }, { -21, 107 }, { -23, 108 }, { -26, 112 },
++        { -10,  96 }, { -12,  95 }, {  -5,  91 }, {  -9,  93 },
++        { -22,  94 }, {  -5,  86 }, {   9,  67 }, {  -4,  80 },
++        { -10,  85 }, {  -1,  70 }, {   7,  60 }, {   9,  58 },
++        {   5,  61 }, {  12,  50 }, {  15,  50 }, {  18,  49 },
++        {  17,  54 }, {  10,  41 }, {   7,  46 }, {  -1,  51 },
++        {   7,  49 }, {   8,  52 }, {   9,  41 }, {   6,  47 },
++        {   2,  55 }, {  13,  41 }, {  10,  44 }, {   6,  50 },
++        {   5,  53 }, {  13,  49 }, {   4,  63 }, {   6,  64 },
++        { -13, 106 }, { -16, 106 }, { -10,  87 }, { -21, 114 },
++        { -18, 110 }, { -14,  98 }, { -22, 110 }, { -21, 106 },
++        { -18, 103 }, { -21, 107 }, { -23, 108 }, { -26, 112 },
++        { -10,  96 }, { -12,  95 }, {  -5,  91 }, {  -9,  93 },
++        { -22,  94 }, {  -5,  86 }, {   9,  67 }, {  -4,  80 },
++        { -10,  85 }, {  -1,  70 }, {   7,  60 }, {   9,  58 },
++        {   5,  61 }, {  12,  50 }, {  15,  50 }, {  18,  49 },
++        {  17,  54 }, {  10,  41 }, {   7,  46 }, {  -1,  51 },
++        {   7,  49 }, {   8,  52 }, {   9,  41 }, {   6,  47 },
++        {   2,  55 }, {  13,  41 }, {  10,  44 }, {   6,  50 },
++        {   5,  53 }, {  13,  49 }, {   4,  63 }, {   6,  64 },
++        {  14,  11 }, {  11,  14 }, {   9,  11 }, {  18,  11 },
++        {  21,   9 }, {  23,  -2 }, {  32, -15 }, {  32, -15 },
++        {  34, -21 }, {  39, -23 }, {  42, -33 }, {  41, -31 },
++        {  46, -28 }, {  38, -12 }, {  21,  29 }, {  45, -24 },
++        {  53, -45 }, {  48, -26 }, {  65, -43 }, {  43, -19 },
++        {  39, -10 }, {  30,   9 }, {  18,  26 }, {  20,  27 },
++        {   0,  57 }, { -14,  82 }, {  -5,  75 }, { -19,  97 },
++        { -35, 125 }, {  27,   0 }, {  28,   0 }, {  31,  -4 },
++        {  27,   6 }, {  34,   8 }, {  30,  10 }, {  24,  22 },
++        {  33,  19 }, {  22,  32 }, {  26,  31 }, {  21,  41 },
++        {  26,  44 }, {  23,  47 }, {  16,  65 }, {  14,  71 },
++        {  14,  11 }, {  11,  14 }, {   9,  11 }, {  18,  11 },
++        {  21,   9 }, {  23,  -2 }, {  32, -15 }, {  32, -15 },
++        {  34, -21 }, {  39, -23 }, {  42, -33 }, {  41, -31 },
++        {  46, -28 }, {  38, -12 }, {  21,  29 }, {  45, -24 },
++        {  53, -45 }, {  48, -26 }, {  65, -43 }, {  43, -19 },
++        {  39, -10 }, {  30,   9 }, {  18,  26 }, {  20,  27 },
++        {   0,  57 }, { -14,  82 }, {  -5,  75 }, { -19,  97 },
++        { -35, 125 }, {  27,   0 }, {  28,   0 }, {  31,  -4 },
++        {  27,   6 }, {  34,   8 }, {  30,  10 }, {  24,  22 },
++        {  33,  19 }, {  22,  32 }, {  26,  31 }, {  21,  41 },
++        {  26,  44 }, {  23,  47 }, {  16,  65 }, {  14,  71 },
++        {  -6,  76 }, {  -2,  44 }, {   0,  45 }, {   0,  52 },
++        {  -3,  64 }, {  -2,  59 }, {  -4,  70 }, {  -4,  75 },
++        {  -8,  82 }, { -17, 102 }, {  -9,  77 }, {   3,  24 },
++        {   0,  42 }, {   0,  48 }, {   0,  55 }, {  -6,  59 },
++        {  -7,  71 }, { -12,  83 }, { -11,  87 }, { -30, 119 },
++        {   1,  58 }, {  -3,  29 }, {  -1,  36 }, {   1,  38 },
++        {   2,  43 }, {  -6,  55 }, {   0,  58 }, {   0,  64 },
++        {  -3,  74 }, { -10,  90 }, {  -6,  76 }, {  -2,  44 },
++        {   0,  45 }, {   0,  52 }, {  -3,  64 }, {  -2,  59 },
++        {  -4,  70 }, {  -4,  75 }, {  -8,  82 }, { -17, 102 },
++        {  -9,  77 }, {   3,  24 }, {   0,  42 }, {   0,  48 },
++        {   0,  55 }, {  -6,  59 }, {  -7,  71 }, { -12,  83 },
++        { -11,  87 }, { -30, 119 }, {   1,  58 }, {  -3,  29 },
++        {  -1,  36 }, {   1,  38 }, {   2,  43 }, {  -6,  55 },
++        {   0,  58 }, {   0,  64 }, {  -3,  74 }, { -10,  90 },
++        {  -3,  74 }, {  -9,  92 }, {  -8,  87 }, { -23, 126 },
++        {  -3,  74 }, {  -9,  92 }, {  -8,  87 }, { -23, 126 },
++        {  -3,  74 }, {  -9,  92 }, {  -8,  87 }, { -23, 126 }
++    },
++
++    /* i_cabac_init_idc == 1 */
++    {
++        /* 0 - 10 */
++        {  20, -15 }, {   2,  54 }, {   3,  74 }, {  20, -15 },
++        {   2,  54 }, {   3,  74 }, { -28, 127 }, { -23, 104 },
++        {  -6,  53 }, {  -1,  54 }, {   7,  51 },
++
++        /* 11 - 23 */
++        {  22,  25 }, {  34,   0 }, {  16,   0 }, {  -2,   9 },
++        {   4,  41 }, { -29, 118 }, {   2,  65 }, {  -6,  71 },
++        { -13,  79 }, {   5,  52 }, {   9,  50 }, {  -3,  70 },
++        {  10,  54 },
++
++        /* 24 - 39 */
++        {  26,  34 }, {  19,  22 }, {  40,   0 }, {  57,   2 },
++        {  41,  36 }, {  26,  69 }, { -45, 127 }, { -15, 101 },
++        {  -4,  76 }, {  -6,  71 }, { -13,  79 }, {   5,  52 },
++        {   6,  69 }, { -13,  90 }, {   0,  52 }, {   8,  43 },
++
++        /* 40 - 53 */
++        {  -2,  69 },{  -5,  82 },{ -10,  96 },{   2,  59 },
++        {   2,  75 },{  -3,  87 },{  -3,  100 },{   1,  56 },
++        {  -3,  74 },{  -6,  85 },{   0,  59 },{  -3,  81 },
++        {  -7,  86 },{  -5,  95 },
++
++        /* 54 - 59 */
++        {  -1,  66 },{  -1,  77 },{   1,  70 },{  -2,  86 },
++        {  -5,  72 },{   0,  61 },
++
++        /* 60 - 69 */
++        { 0, 41 },   { 0, 63 },   { 0, 63 },     { 0, 63 },
++        { -9, 83 },  { 4, 86 },   { 0, 97 },     { -7, 72 },
++        { 13, 41 },  { 3, 62 },
++
++        /* 70 - 104 */
++        {  13,  15 }, {   7,  51 }, {   2,  80 }, { -39, 127 },
++        { -18,  91 }, { -17,  96 }, { -26,  81 }, { -35,  98 },
++        { -24, 102 }, { -23,  97 }, { -27, 119 }, { -24,  99 },
++        { -21, 110 }, { -18, 102 }, { -36, 127 }, {   0,  80 },
++        {  -5,  89 }, {  -7,  94 }, {  -4,  92 }, {   0,  39 },
++        {   0,  65 }, { -15,  84 }, { -35, 127 }, {  -2,  73 },
++        { -12, 104 }, {  -9,  91 }, { -31, 127 }, {   3,  55 },
++        {   7,  56 }, {   7,  55 }, {   8,  61 }, {  -3,  53 },
++        {   0,  68 }, {  -7,  74 }, {  -9,  88 },
++
++        /* 105 -> 165 */
++        { -13, 103 }, { -13,  91 }, {  -9,  89 }, { -14,  92 },
++        {  -8,  76 }, { -12,  87 }, { -23, 110 }, { -24, 105 },
++        { -10,  78 }, { -20, 112 }, { -17,  99 }, { -78, 127 },
++        { -70, 127 }, { -50, 127 }, { -46, 127 }, {  -4,  66 },
++        {  -5,  78 }, {  -4,  71 }, {  -8,  72 }, {   2,  59 },
++        {  -1,  55 }, {  -7,  70 }, {  -6,  75 }, {  -8,  89 },
++        { -34, 119 }, {  -3,  75 }, {  32,  20 }, {  30,  22 },
++        { -44, 127 }, {   0,  54 }, {  -5,  61 }, {   0,  58 },
++        {  -1,  60 }, {  -3,  61 }, {  -8,  67 }, { -25,  84 },
++        { -14,  74 }, {  -5,  65 }, {   5,  52 }, {   2,  57 },
++        {   0,  61 }, {  -9,  69 }, { -11,  70 }, {  18,  55 },
++        {  -4,  71 }, {   0,  58 }, {   7,  61 }, {   9,  41 },
++        {  18,  25 }, {   9,  32 }, {   5,  43 }, {   9,  47 },
++        {   0,  44 }, {   0,  51 }, {   2,  46 }, {  19,  38 },
++        {  -4,  66 }, {  15,  38 }, {  12,  42 }, {   9,  34 },
++        {   0,  89 },
++
++        /* 166 - 226 */
++        {   4,  45 }, {  10,  28 }, {  10,  31 }, {  33, -11 },
++        {  52, -43 }, {  18,  15 }, {  28,   0 }, {  35, -22 },
++        {  38, -25 }, {  34,   0 }, {  39, -18 }, {  32, -12 },
++        { 102, -94 }, {   0,   0 }, {  56, -15 }, {  33,  -4 },
++        {  29,  10 }, {  37,  -5 }, {  51, -29 }, {  39,  -9 },
++        {  52, -34 }, {  69, -58 }, {  67, -63 }, {  44,  -5 },
++        {  32,   7 }, {  55, -29 }, {  32,   1 }, {   0,   0 },
++        {  27,  36 }, {  33, -25 }, {  34, -30 }, {  36, -28 },
++        {  38, -28 }, {  38, -27 }, {  34, -18 }, {  35, -16 },
++        {  34, -14 }, {  32,  -8 }, {  37,  -6 }, {  35,   0 },
++        {  30,  10 }, {  28,  18 }, {  26,  25 }, {  29,  41 },
++        {   0,  75 }, {   2,  72 }, {   8,  77 }, {  14,  35 },
++        {  18,  31 }, {  17,  35 }, {  21,  30 }, {  17,  45 },
++        {  20,  42 }, {  18,  45 }, {  27,  26 }, {  16,  54 },
++        {   7,  66 }, {  16,  56 }, {  11,  73 }, {  10,  67 },
++        { -10, 116 },
++
++        /* 227 - 275 */
++        { -23, 112 }, { -15,  71 }, {  -7,  61 }, {   0,  53 },
++        {  -5,  66 }, { -11,  77 }, {  -9,  80 }, {  -9,  84 },
++        { -10,  87 }, { -34, 127 }, { -21, 101 }, {  -3,  39 },
++        {  -5,  53 }, {  -7,  61 }, { -11,  75 }, { -15,  77 },
++        { -17,  91 }, { -25, 107 }, { -25, 111 }, { -28, 122 },
++        { -11,  76 }, { -10,  44 }, { -10,  52 }, { -10,  57 },
++        {  -9,  58 }, { -16,  72 }, {  -7,  69 }, {  -4,  69 },
++        {  -5,  74 }, {  -9,  86 }, {   2,  66 }, {  -9,  34 },
++        {   1,  32 }, {  11,  31 }, {   5,  52 }, {  -2,  55 },
++        {  -2,  67 }, {   0,  73 }, {  -8,  89 }, {   3,  52 },
++        {   7,   4 }, {  10,   8 }, {  17,   8 }, {  16,  19 },
++        {   3,  37 }, {  -1,  61 }, {  -5,  73 }, {  -1,  70 },
++        {  -4,  78 },
++
++        /* 276 a bit special (not used, h264_cabac_encode_bypass is used instead) */
++        { 0, 0 },
++
++        /* 277 - 337 */
++        { -21, 126 }, { -23, 124 }, { -20, 110 }, { -26, 126 },
++        { -25, 124 }, { -17, 105 }, { -27, 121 }, { -27, 117 },
++        { -17, 102 }, { -26, 117 }, { -27, 116 }, { -33, 122 },
++        { -10,  95 }, { -14, 100 }, {  -8,  95 }, { -17, 111 },
++        { -28, 114 }, {  -6,  89 }, {  -2,  80 }, {  -4,  82 },
++        {  -9,  85 }, {  -8,  81 }, {  -1,  72 }, {   5,  64 },
++        {   1,  67 }, {   9,  56 }, {   0,  69 }, {   1,  69 },
++        {   7,  69 }, {  -7,  69 }, {  -6,  67 }, { -16,  77 },
++        {  -2,  64 }, {   2,  61 }, {  -6,  67 }, {  -3,  64 },
++        {   2,  57 }, {  -3,  65 }, {  -3,  66 }, {   0,  62 },
++        {   9,  51 }, {  -1,  66 }, {  -2,  71 }, {  -2,  75 },
++        {  -1,  70 }, {  -9,  72 }, {  14,  60 }, {  16,  37 },
++        {   0,  47 }, {  18,  35 }, {  11,  37 }, {  12,  41 },
++        {  10,  41 }, {   2,  48 }, {  12,  41 }, {  13,  41 },
++        {   0,  59 }, {   3,  50 }, {  19,  40 }, {   3,  66 },
++        {  18,  50 },
++
++        /* 338 - 398 */
++        {  19,  -6 }, {  18,  -6 }, {  14,   0 }, {  26, -12 },
++        {  31, -16 }, {  33, -25 }, {  33, -22 }, {  37, -28 },
++        {  39, -30 }, {  42, -30 }, {  47, -42 }, {  45, -36 },
++        {  49, -34 }, {  41, -17 }, {  32,   9 }, {  69, -71 },
++        {  63, -63 }, {  66, -64 }, {  77, -74 }, {  54, -39 },
++        {  52, -35 }, {  41, -10 }, {  36,   0 }, {  40,  -1 },
++        {  30,  14 }, {  28,  26 }, {  23,  37 }, {  12,  55 },
++        {  11,  65 }, {  37, -33 }, {  39, -36 }, {  40, -37 },
++        {  38, -30 }, {  46, -33 }, {  42, -30 }, {  40, -24 },
++        {  49, -29 }, {  38, -12 }, {  40, -10 }, {  38,  -3 },
++        {  46,  -5 }, {  31,  20 }, {  29,  30 }, {  25,  44 },
++        {  12,  48 }, {  11,  49 }, {  26,  45 }, {  22,  22 },
++        {  23,  22 }, {  27,  21 }, {  33,  20 }, {  26,  28 },
++        {  30,  24 }, {  27,  34 }, {  18,  42 }, {  25,  39 },
++        {  18,  50 }, {  12,  70 }, {  21,  54 }, {  14,  71 },
++        {  11,  83 },
++
++        /* 399 -> 435 */
++        {  25,  32 }, {  21,  49 }, {  21,  54 },
++        {  -5,  85 }, {  -6,  81 }, { -10,  77 }, {  -7,  81 },
++        { -17,  80 }, { -18,  73 }, {  -4,  74 }, { -10,  83 },
++        {  -9,  71 }, {  -9,  67 }, {  -1,  61 }, {  -8,  66 },
++        { -14,  66 }, {   0,  59 }, {   2,  59 }, {  17, -10 },
++        {  32, -13 }, {  42,  -9 }, {  49,  -5 }, {  53,   0 },
++        {  64,   3 }, {  68,  10 }, {  66,  27 }, {  47,  57 },
++        {  -5,  71 }, {   0,  24 }, {  -1,  36 }, {  -2,  42 },
++        {  -2,  52 }, {  -9,  57 }, {  -6,  63 }, {  -4,  65 },
++        {  -4,  67 }, {  -7,  82 },
++
++        /* 436 -> 459 */
++        {  -3,  81 }, {  -3,  76 }, {  -7,  72 }, {  -6,  78 },
++        { -12,  72 }, { -14,  68 }, {  -3,  70 }, {  -6,  76 },
++        {  -5,  66 }, {  -5,  62 }, {   0,  57 }, {  -4,  61 },
++        {  -9,  60 }, {   1,  54 }, {   2,  58 }, {  17, -10 },
++        {  32, -13 }, {  42,  -9 }, {  49,  -5 }, {  53,   0 },
++        {  64,   3 }, {  68,  10 }, {  66,  27 }, {  47,  57 },
++
++        /* 460 - 1024 */
++        {   0,  80 }, {  -5,  89 }, {  -7,  94 }, {  -4,  92 },
++        {   0,  39 }, {   0,  65 }, { -15,  84 }, { -35, 127 },
++        {  -2,  73 }, { -12, 104 }, {  -9,  91 }, { -31, 127 },
++        {   0,  80 }, {  -5,  89 }, {  -7,  94 }, {  -4,  92 },
++        {   0,  39 }, {   0,  65 }, { -15,  84 }, { -35, 127 },
++        {  -2,  73 }, { -12, 104 }, {  -9,  91 }, { -31, 127 },
++        { -13, 103 }, { -13,  91 }, {  -9,  89 }, { -14,  92 },
++        {  -8,  76 }, { -12,  87 }, { -23, 110 }, { -24, 105 },
++        { -10,  78 }, { -20, 112 }, { -17,  99 }, { -78, 127 },
++        { -70, 127 }, { -50, 127 }, { -46, 127 }, {  -4,  66 },
++        {  -5,  78 }, {  -4,  71 }, {  -8,  72 }, {   2,  59 },
++        {  -1,  55 }, {  -7,  70 }, {  -6,  75 }, {  -8,  89 },
++        { -34, 119 }, {  -3,  75 }, {  32,  20 }, {  30,  22 },
++        { -44, 127 }, {   0,  54 }, {  -5,  61 }, {   0,  58 },
++        {  -1,  60 }, {  -3,  61 }, {  -8,  67 }, { -25,  84 },
++        { -14,  74 }, {  -5,  65 }, {   5,  52 }, {   2,  57 },
++        {   0,  61 }, {  -9,  69 }, { -11,  70 }, {  18,  55 },
++        { -13, 103 }, { -13,  91 }, {  -9,  89 }, { -14,  92 },
++        {  -8,  76 }, { -12,  87 }, { -23, 110 }, { -24, 105 },
++        { -10,  78 }, { -20, 112 }, { -17,  99 }, { -78, 127 },
++        { -70, 127 }, { -50, 127 }, { -46, 127 }, {  -4,  66 },
++        {  -5,  78 }, {  -4,  71 }, {  -8,  72 }, {   2,  59 },
++        {  -1,  55 }, {  -7,  70 }, {  -6,  75 }, {  -8,  89 },
++        { -34, 119 }, {  -3,  75 }, {  32,  20 }, {  30,  22 },
++        { -44, 127 }, {   0,  54 }, {  -5,  61 }, {   0,  58 },
++        {  -1,  60 }, {  -3,  61 }, {  -8,  67 }, { -25,  84 },
++        { -14,  74 }, {  -5,  65 }, {   5,  52 }, {   2,  57 },
++        {   0,  61 }, {  -9,  69 }, { -11,  70 }, {  18,  55 },
++        {   4,  45 }, {  10,  28 }, {  10,  31 }, {  33, -11 },
++        {  52, -43 }, {  18,  15 }, {  28,   0 }, {  35, -22 },
++        {  38, -25 }, {  34,   0 }, {  39, -18 }, {  32, -12 },
++        { 102, -94 }, {   0,   0 }, {  56, -15 }, {  33,  -4 },
++        {  29,  10 }, {  37,  -5 }, {  51, -29 }, {  39,  -9 },
++        {  52, -34 }, {  69, -58 }, {  67, -63 }, {  44,  -5 },
++        {  32,   7 }, {  55, -29 }, {  32,   1 }, {   0,   0 },
++        {  27,  36 }, {  33, -25 }, {  34, -30 }, {  36, -28 },
++        {  38, -28 }, {  38, -27 }, {  34, -18 }, {  35, -16 },
++        {  34, -14 }, {  32,  -8 }, {  37,  -6 }, {  35,   0 },
++        {  30,  10 }, {  28,  18 }, {  26,  25 }, {  29,  41 },
++        {   4,  45 }, {  10,  28 }, {  10,  31 }, {  33, -11 },
++        {  52, -43 }, {  18,  15 }, {  28,   0 }, {  35, -22 },
++        {  38, -25 }, {  34,   0 }, {  39, -18 }, {  32, -12 },
++        { 102, -94 }, {   0,   0 }, {  56, -15 }, {  33,  -4 },
++        {  29,  10 }, {  37,  -5 }, {  51, -29 }, {  39,  -9 },
++        {  52, -34 }, {  69, -58 }, {  67, -63 }, {  44,  -5 },
++        {  32,   7 }, {  55, -29 }, {  32,   1 }, {   0,   0 },
++        {  27,  36 }, {  33, -25 }, {  34, -30 }, {  36, -28 },
++        {  38, -28 }, {  38, -27 }, {  34, -18 }, {  35, -16 },
++        {  34, -14 }, {  32,  -8 }, {  37,  -6 }, {  35,   0 },
++        {  30,  10 }, {  28,  18 }, {  26,  25 }, {  29,  41 },
++        {  -5,  85 }, {  -6,  81 }, { -10,  77 }, {  -7,  81 },
++        { -17,  80 }, { -18,  73 }, {  -4,  74 }, { -10,  83 },
++        {  -9,  71 }, {  -9,  67 }, {  -1,  61 }, {  -8,  66 },
++        { -14,  66 }, {   0,  59 }, {   2,  59 }, {  -3,  81 },
++        {  -3,  76 }, {  -7,  72 }, {  -6,  78 }, { -12,  72 },
++        { -14,  68 }, {  -3,  70 }, {  -6,  76 }, {  -5,  66 },
++        {  -5,  62 }, {   0,  57 }, {  -4,  61 }, {  -9,  60 },
++        {   1,  54 }, {   2,  58 }, {  17, -10 }, {  32, -13 },
++        {  42,  -9 }, {  49,  -5 }, {  53,   0 }, {  64,   3 },
++        {  68,  10 }, {  66,  27 }, {  47,  57 }, {  17, -10 },
++        {  32, -13 }, {  42,  -9 }, {  49,  -5 }, {  53,   0 },
++        {  64,   3 }, {  68,  10 }, {  66,  27 }, {  47,  57 },
++        {  -5,  71 }, {   0,  24 }, {  -1,  36 }, {  -2,  42 },
++        {  -2,  52 }, {  -9,  57 }, {  -6,  63 }, {  -4,  65 },
++        {  -4,  67 }, {  -7,  82 }, {  -5,  85 }, {  -6,  81 },
++        { -10,  77 }, {  -7,  81 }, { -17,  80 }, { -18,  73 },
++        {  -4,  74 }, { -10,  83 }, {  -9,  71 }, {  -9,  67 },
++        {  -1,  61 }, {  -8,  66 }, { -14,  66 }, {   0,  59 },
++        {   2,  59 }, {  -3,  81 }, {  -3,  76 }, {  -7,  72 },
++        {  -6,  78 }, { -12,  72 }, { -14,  68 }, {  -3,  70 },
++        {  -6,  76 }, {  -5,  66 }, {  -5,  62 }, {   0,  57 },
++        {  -4,  61 }, {  -9,  60 }, {   1,  54 }, {   2,  58 },
++        {  17, -10 }, {  32, -13 }, {  42,  -9 }, {  49,  -5 },
++        {  53,   0 }, {  64,   3 }, {  68,  10 }, {  66,  27 },
++        {  47,  57 }, {  17, -10 }, {  32, -13 }, {  42,  -9 },
++        {  49,  -5 }, {  53,   0 }, {  64,   3 }, {  68,  10 },
++        {  66,  27 }, {  47,  57 }, {  -5,  71 }, {   0,  24 },
++        {  -1,  36 }, {  -2,  42 }, {  -2,  52 }, {  -9,  57 },
++        {  -6,  63 }, {  -4,  65 }, {  -4,  67 }, {  -7,  82 },
++        { -21, 126 }, { -23, 124 }, { -20, 110 }, { -26, 126 },
++        { -25, 124 }, { -17, 105 }, { -27, 121 }, { -27, 117 },
++        { -17, 102 }, { -26, 117 }, { -27, 116 }, { -33, 122 },
++        { -10,  95 }, { -14, 100 }, {  -8,  95 }, { -17, 111 },
++        { -28, 114 }, {  -6,  89 }, {  -2,  80 }, {  -4,  82 },
++        {  -9,  85 }, {  -8,  81 }, {  -1,  72 }, {   5,  64 },
++        {   1,  67 }, {   9,  56 }, {   0,  69 }, {   1,  69 },
++        {   7,  69 }, {  -7,  69 }, {  -6,  67 }, { -16,  77 },
++        {  -2,  64 }, {   2,  61 }, {  -6,  67 }, {  -3,  64 },
++        {   2,  57 }, {  -3,  65 }, {  -3,  66 }, {   0,  62 },
++        {   9,  51 }, {  -1,  66 }, {  -2,  71 }, {  -2,  75 },
++        { -21, 126 }, { -23, 124 }, { -20, 110 }, { -26, 126 },
++        { -25, 124 }, { -17, 105 }, { -27, 121 }, { -27, 117 },
++        { -17, 102 }, { -26, 117 }, { -27, 116 }, { -33, 122 },
++        { -10,  95 }, { -14, 100 }, {  -8,  95 }, { -17, 111 },
++        { -28, 114 }, {  -6,  89 }, {  -2,  80 }, {  -4,  82 },
++        {  -9,  85 }, {  -8,  81 }, {  -1,  72 }, {   5,  64 },
++        {   1,  67 }, {   9,  56 }, {   0,  69 }, {   1,  69 },
++        {   7,  69 }, {  -7,  69 }, {  -6,  67 }, { -16,  77 },
++        {  -2,  64 }, {   2,  61 }, {  -6,  67 }, {  -3,  64 },
++        {   2,  57 }, {  -3,  65 }, {  -3,  66 }, {   0,  62 },
++        {   9,  51 }, {  -1,  66 }, {  -2,  71 }, {  -2,  75 },
++        {  19,  -6 }, {  18,  -6 }, {  14,   0 }, {  26, -12 },
++        {  31, -16 }, {  33, -25 }, {  33, -22 }, {  37, -28 },
++        {  39, -30 }, {  42, -30 }, {  47, -42 }, {  45, -36 },
++        {  49, -34 }, {  41, -17 }, {  32,   9 }, {  69, -71 },
++        {  63, -63 }, {  66, -64 }, {  77, -74 }, {  54, -39 },
++        {  52, -35 }, {  41, -10 }, {  36,   0 }, {  40,  -1 },
++        {  30,  14 }, {  28,  26 }, {  23,  37 }, {  12,  55 },
++        {  11,  65 }, {  37, -33 }, {  39, -36 }, {  40, -37 },
++        {  38, -30 }, {  46, -33 }, {  42, -30 }, {  40, -24 },
++        {  49, -29 }, {  38, -12 }, {  40, -10 }, {  38,  -3 },
++        {  46,  -5 }, {  31,  20 }, {  29,  30 }, {  25,  44 },
++        {  19,  -6 }, {  18,  -6 }, {  14,   0 }, {  26, -12 },
++        {  31, -16 }, {  33, -25 }, {  33, -22 }, {  37, -28 },
++        {  39, -30 }, {  42, -30 }, {  47, -42 }, {  45, -36 },
++        {  49, -34 }, {  41, -17 }, {  32,   9 }, {  69, -71 },
++        {  63, -63 }, {  66, -64 }, {  77, -74 }, {  54, -39 },
++        {  52, -35 }, {  41, -10 }, {  36,   0 }, {  40,  -1 },
++        {  30,  14 }, {  28,  26 }, {  23,  37 }, {  12,  55 },
++        {  11,  65 }, {  37, -33 }, {  39, -36 }, {  40, -37 },
++        {  38, -30 }, {  46, -33 }, {  42, -30 }, {  40, -24 },
++        {  49, -29 }, {  38, -12 }, {  40, -10 }, {  38,  -3 },
++        {  46,  -5 }, {  31,  20 }, {  29,  30 }, {  25,  44 },
++        { -23, 112 }, { -15,  71 }, {  -7,  61 }, {   0,  53 },
++        {  -5,  66 }, { -11,  77 }, {  -9,  80 }, {  -9,  84 },
++        { -10,  87 }, { -34, 127 }, { -21, 101 }, {  -3,  39 },
++        {  -5,  53 }, {  -7,  61 }, { -11,  75 }, { -15,  77 },
++        { -17,  91 }, { -25, 107 }, { -25, 111 }, { -28, 122 },
++        { -11,  76 }, { -10,  44 }, { -10,  52 }, { -10,  57 },
++        {  -9,  58 }, { -16,  72 }, {  -7,  69 }, {  -4,  69 },
++        {  -5,  74 }, {  -9,  86 }, { -23, 112 }, { -15,  71 },
++        {  -7,  61 }, {   0,  53 }, {  -5,  66 }, { -11,  77 },
++        {  -9,  80 }, {  -9,  84 }, { -10,  87 }, { -34, 127 },
++        { -21, 101 }, {  -3,  39 }, {  -5,  53 }, {  -7,  61 },
++        { -11,  75 }, { -15,  77 }, { -17,  91 }, { -25, 107 },
++        { -25, 111 }, { -28, 122 }, { -11,  76 }, { -10,  44 },
++        { -10,  52 }, { -10,  57 }, {  -9,  58 }, { -16,  72 },
++        {  -7,  69 }, {  -4,  69 }, {  -5,  74 }, {  -9,  86 },
++        {  -2,  73 }, { -12, 104 }, {  -9,  91 }, { -31, 127 },
++        {  -2,  73 }, { -12, 104 }, {  -9,  91 }, { -31, 127 },
++        {  -2,  73 }, { -12, 104 }, {  -9,  91 }, { -31, 127 }
++    },
++
++    /* i_cabac_init_idc == 2 */
++    {
++        /* 0 - 10 */
++        {  20, -15 }, {   2,  54 }, {   3,  74 }, {  20, -15 },
++        {   2,  54 }, {   3,  74 }, { -28, 127 }, { -23, 104 },
++        {  -6,  53 }, {  -1,  54 }, {   7,  51 },
++
++        /* 11 - 23 */
++        {  29,  16 }, {  25,   0 }, {  14,   0 }, { -10,  51 },
++        {  -3,  62 }, { -27,  99 }, {  26,  16 }, {  -4,  85 },
++        { -24, 102 }, {   5,  57 }, {   6,  57 }, { -17,  73 },
++        {  14,  57 },
++
++        /* 24 - 39 */
++        {  20,  40 }, {  20,  10 }, {  29,   0 }, {  54,   0 },
++        {  37,  42 }, {  12,  97 }, { -32, 127 }, { -22, 117 },
++        {  -2,  74 }, {  -4,  85 }, { -24, 102 }, {   5,  57 },
++        {  -6,  93 }, { -14,  88 }, {  -6,  44 }, {   4,  55 },
++
++        /* 40 - 53 */
++        { -11,  89 },{ -15,  103 },{ -21,  116 },{  19,  57 },
++        {  20,  58 },{   4,  84 },{   6,  96 },{   1,  63 },
++        {  -5,  85 },{ -13,  106 },{   5,  63 },{   6,  75 },
++        {  -3,  90 },{  -1,  101 },
++
++        /* 54 - 59 */
++        {   3,  55 },{  -4,  79 },{  -2,  75 },{ -12,  97 },
++        {  -7,  50 },{   1,  60 },
++
++        /* 60 - 69 */
++        { 0, 41 },   { 0, 63 },   { 0, 63 },     { 0, 63 },
++        { -9, 83 },  { 4, 86 },   { 0, 97 },     { -7, 72 },
++        { 13, 41 },  { 3, 62 },
++
++        /* 70 - 104 */
++        {   7,  34 }, {  -9,  88 }, { -20, 127 }, { -36, 127 },
++        { -17,  91 }, { -14,  95 }, { -25,  84 }, { -25,  86 },
++        { -12,  89 }, { -17,  91 }, { -31, 127 }, { -14,  76 },
++        { -18, 103 }, { -13,  90 }, { -37, 127 }, {  11,  80 },
++        {   5,  76 }, {   2,  84 }, {   5,  78 }, {  -6,  55 },
++        {   4,  61 }, { -14,  83 }, { -37, 127 }, {  -5,  79 },
++        { -11, 104 }, { -11,  91 }, { -30, 127 }, {   0,  65 },
++        {  -2,  79 }, {   0,  72 }, {  -4,  92 }, {  -6,  56 },
++        {   3,  68 }, {  -8,  71 }, { -13,  98 },
++
++        /* 105 -> 165 */
++        {  -4,  86 }, { -12,  88 }, {  -5,  82 }, {  -3,  72 },
++        {  -4,  67 }, {  -8,  72 }, { -16,  89 }, {  -9,  69 },
++        {  -1,  59 }, {   5,  66 }, {   4,  57 }, {  -4,  71 },
++        {  -2,  71 }, {   2,  58 }, {  -1,  74 }, {  -4,  44 },
++        {  -1,  69 }, {   0,  62 }, {  -7,  51 }, {  -4,  47 },
++        {  -6,  42 }, {  -3,  41 }, {  -6,  53 }, {   8,  76 },
++        {  -9,  78 }, { -11,  83 }, {   9,  52 }, {   0,  67 },
++        {  -5,  90 }, {   1,  67 }, { -15,  72 }, {  -5,  75 },
++        {  -8,  80 }, { -21,  83 }, { -21,  64 }, { -13,  31 },
++        { -25,  64 }, { -29,  94 }, {   9,  75 }, {  17,  63 },
++        {  -8,  74 }, {  -5,  35 }, {  -2,  27 }, {  13,  91 },
++        {   3,  65 }, {  -7,  69 }, {   8,  77 }, { -10,  66 },
++        {   3,  62 }, {  -3,  68 }, { -20,  81 }, {   0,  30 },
++        {   1,   7 }, {  -3,  23 }, { -21,  74 }, {  16,  66 },
++        { -23, 124 }, {  17,  37 }, {  44, -18 }, {  50, -34 },
++        { -22, 127 },
++
++        /* 166 - 226 */
++        {   4,  39 }, {   0,  42 }, {   7,  34 }, {  11,  29 },
++        {   8,  31 }, {   6,  37 }, {   7,  42 }, {   3,  40 },
++        {   8,  33 }, {  13,  43 }, {  13,  36 }, {   4,  47 },
++        {   3,  55 }, {   2,  58 }, {   6,  60 }, {   8,  44 },
++        {  11,  44 }, {  14,  42 }, {   7,  48 }, {   4,  56 },
++        {   4,  52 }, {  13,  37 }, {   9,  49 }, {  19,  58 },
++        {  10,  48 }, {  12,  45 }, {   0,  69 }, {  20,  33 },
++        {   8,  63 }, {  35, -18 }, {  33, -25 }, {  28,  -3 },
++        {  24,  10 }, {  27,   0 }, {  34, -14 }, {  52, -44 },
++        {  39, -24 }, {  19,  17 }, {  31,  25 }, {  36,  29 },
++        {  24,  33 }, {  34,  15 }, {  30,  20 }, {  22,  73 },
++        {  20,  34 }, {  19,  31 }, {  27,  44 }, {  19,  16 },
++        {  15,  36 }, {  15,  36 }, {  21,  28 }, {  25,  21 },
++        {  30,  20 }, {  31,  12 }, {  27,  16 }, {  24,  42 },
++        {   0,  93 }, {  14,  56 }, {  15,  57 }, {  26,  38 },
++        { -24, 127 },
++
++        /* 227 - 275 */
++        { -24, 115 }, { -22,  82 }, {  -9,  62 }, {   0,  53 },
++        {   0,  59 }, { -14,  85 }, { -13,  89 }, { -13,  94 },
++        { -11,  92 }, { -29, 127 }, { -21, 100 }, { -14,  57 },
++        { -12,  67 }, { -11,  71 }, { -10,  77 }, { -21,  85 },
++        { -16,  88 }, { -23, 104 }, { -15,  98 }, { -37, 127 },
++        { -10,  82 }, {  -8,  48 }, {  -8,  61 }, {  -8,  66 },
++        {  -7,  70 }, { -14,  75 }, { -10,  79 }, {  -9,  83 },
++        { -12,  92 }, { -18, 108 }, {  -4,  79 }, { -22,  69 },
++        { -16,  75 }, {  -2,  58 }, {   1,  58 }, { -13,  78 },
++        {  -9,  83 }, {  -4,  81 }, { -13,  99 }, { -13,  81 },
++        {  -6,  38 }, { -13,  62 }, {  -6,  58 }, {  -2,  59 },
++        { -16,  73 }, { -10,  76 }, { -13,  86 }, {  -9,  83 },
++        { -10,  87 },
++
++        /* 276 a bit special (not used, h264_cabac_encode_bypass is used instead) */
++        { 0, 0 },
++
++        /* 277 - 337 */
++        { -22, 127 }, { -25, 127 }, { -25, 120 }, { -27, 127 },
++        { -19, 114 }, { -23, 117 }, { -25, 118 }, { -26, 117 },
++        { -24, 113 }, { -28, 118 }, { -31, 120 }, { -37, 124 },
++        { -10,  94 }, { -15, 102 }, { -10,  99 }, { -13, 106 },
++        { -50, 127 }, {  -5,  92 }, {  17,  57 }, {  -5,  86 },
++        { -13,  94 }, { -12,  91 }, {  -2,  77 }, {   0,  71 },
++        {  -1,  73 }, {   4,  64 }, {  -7,  81 }, {   5,  64 },
++        {  15,  57 }, {   1,  67 }, {   0,  68 }, { -10,  67 },
++        {   1,  68 }, {   0,  77 }, {   2,  64 }, {   0,  68 },
++        {  -5,  78 }, {   7,  55 }, {   5,  59 }, {   2,  65 },
++        {  14,  54 }, {  15,  44 }, {   5,  60 }, {   2,  70 },
++        {  -2,  76 }, { -18,  86 }, {  12,  70 }, {   5,  64 },
++        { -12,  70 }, {  11,  55 }, {   5,  56 }, {   0,  69 },
++        {   2,  65 }, {  -6,  74 }, {   5,  54 }, {   7,  54 },
++        {  -6,  76 }, { -11,  82 }, {  -2,  77 }, {  -2,  77 },
++        {  25,  42 },
++
++        /* 338 - 398 */
++        {  17, -13 }, {  16,  -9 }, {  17, -12 }, {  27, -21 },
++        {  37, -30 }, {  41, -40 }, {  42, -41 }, {  48, -47 },
++        {  39, -32 }, {  46, -40 }, {  52, -51 }, {  46, -41 },
++        {  52, -39 }, {  43, -19 }, {  32,  11 }, {  61, -55 },
++        {  56, -46 }, {  62, -50 }, {  81, -67 }, {  45, -20 },
++        {  35,  -2 }, {  28,  15 }, {  34,   1 }, {  39,   1 },
++        {  30,  17 }, {  20,  38 }, {  18,  45 }, {  15,  54 },
++        {   0,  79 }, {  36, -16 }, {  37, -14 }, {  37, -17 },
++        {  32,   1 }, {  34,  15 }, {  29,  15 }, {  24,  25 },
++        {  34,  22 }, {  31,  16 }, {  35,  18 }, {  31,  28 },
++        {  33,  41 }, {  36,  28 }, {  27,  47 }, {  21,  62 },
++        {  18,  31 }, {  19,  26 }, {  36,  24 }, {  24,  23 },
++        {  27,  16 }, {  24,  30 }, {  31,  29 }, {  22,  41 },
++        {  22,  42 }, {  16,  60 }, {  15,  52 }, {  14,  60 },
++        {   3,  78 }, { -16, 123 }, {  21,  53 }, {  22,  56 },
++        {  25,  61 },
++
++        /* 399 -> 435 */
++        {  21,  33 }, {  19,  50 }, {  17,  61 },
++        {  -3,  78 }, {  -8,  74 }, {  -9,  72 }, { -10,  72 },
++        { -18,  75 }, { -12,  71 }, { -11,  63 }, {  -5,  70 },
++        { -17,  75 }, { -14,  72 }, { -16,  67 }, {  -8,  53 },
++        { -14,  59 }, {  -9,  52 }, { -11,  68 }, {   9,  -2 },
++        {  30, -10 }, {  31,  -4 }, {  33,  -1 }, {  33,   7 },
++        {  31,  12 }, {  37,  23 }, {  31,  38 }, {  20,  64 },
++        {  -9,  71 }, {  -7,  37 }, {  -8,  44 }, { -11,  49 },
++        { -10,  56 }, { -12,  59 }, {  -8,  63 }, {  -9,  67 },
++        {  -6,  68 }, { -10,  79 },
++
++        /* 436 -> 459 */
++        {  -3,  78 }, {  -8,  74 }, {  -9,  72 }, { -10,  72 },
++        { -18,  75 }, { -12,  71 }, { -11,  63 }, {  -5,  70 },
++        { -17,  75 }, { -14,  72 }, { -16,  67 }, {  -8,  53 },
++        { -14,  59 }, {  -9,  52 }, { -11,  68 }, {   9,  -2 },
++        {  30, -10 }, {  31,  -4 }, {  33,  -1 }, {  33,   7 },
++        {  31,  12 }, {  37,  23 }, {  31,  38 }, {  20,  64 },
++
++        /* 460 - 1024 */
++        {  11,  80 }, {   5,  76 }, {   2,  84 }, {   5,  78 },
++        {  -6,  55 }, {   4,  61 }, { -14,  83 }, { -37, 127 },
++        {  -5,  79 }, { -11, 104 }, { -11,  91 }, { -30, 127 },
++        {  11,  80 }, {   5,  76 }, {   2,  84 }, {   5,  78 },
++        {  -6,  55 }, {   4,  61 }, { -14,  83 }, { -37, 127 },
++        {  -5,  79 }, { -11, 104 }, { -11,  91 }, { -30, 127 },
++        {  -4,  86 }, { -12,  88 }, {  -5,  82 }, {  -3,  72 },
++        {  -4,  67 }, {  -8,  72 }, { -16,  89 }, {  -9,  69 },
++        {  -1,  59 }, {   5,  66 }, {   4,  57 }, {  -4,  71 },
++        {  -2,  71 }, {   2,  58 }, {  -1,  74 }, {  -4,  44 },
++        {  -1,  69 }, {   0,  62 }, {  -7,  51 }, {  -4,  47 },
++        {  -6,  42 }, {  -3,  41 }, {  -6,  53 }, {   8,  76 },
++        {  -9,  78 }, { -11,  83 }, {   9,  52 }, {   0,  67 },
++        {  -5,  90 }, {   1,  67 }, { -15,  72 }, {  -5,  75 },
++        {  -8,  80 }, { -21,  83 }, { -21,  64 }, { -13,  31 },
++        { -25,  64 }, { -29,  94 }, {   9,  75 }, {  17,  63 },
++        {  -8,  74 }, {  -5,  35 }, {  -2,  27 }, {  13,  91 },
++        {  -4,  86 }, { -12,  88 }, {  -5,  82 }, {  -3,  72 },
++        {  -4,  67 }, {  -8,  72 }, { -16,  89 }, {  -9,  69 },
++        {  -1,  59 }, {   5,  66 }, {   4,  57 }, {  -4,  71 },
++        {  -2,  71 }, {   2,  58 }, {  -1,  74 }, {  -4,  44 },
++        {  -1,  69 }, {   0,  62 }, {  -7,  51 }, {  -4,  47 },
++        {  -6,  42 }, {  -3,  41 }, {  -6,  53 }, {   8,  76 },
++        {  -9,  78 }, { -11,  83 }, {   9,  52 }, {   0,  67 },
++        {  -5,  90 }, {   1,  67 }, { -15,  72 }, {  -5,  75 },
++        {  -8,  80 }, { -21,  83 }, { -21,  64 }, { -13,  31 },
++        { -25,  64 }, { -29,  94 }, {   9,  75 }, {  17,  63 },
++        {  -8,  74 }, {  -5,  35 }, {  -2,  27 }, {  13,  91 },
++        {   4,  39 }, {   0,  42 }, {   7,  34 }, {  11,  29 },
++        {   8,  31 }, {   6,  37 }, {   7,  42 }, {   3,  40 },
++        {   8,  33 }, {  13,  43 }, {  13,  36 }, {   4,  47 },
++        {   3,  55 }, {   2,  58 }, {   6,  60 }, {   8,  44 },
++        {  11,  44 }, {  14,  42 }, {   7,  48 }, {   4,  56 },
++        {   4,  52 }, {  13,  37 }, {   9,  49 }, {  19,  58 },
++        {  10,  48 }, {  12,  45 }, {   0,  69 }, {  20,  33 },
++        {   8,  63 }, {  35, -18 }, {  33, -25 }, {  28,  -3 },
++        {  24,  10 }, {  27,   0 }, {  34, -14 }, {  52, -44 },
++        {  39, -24 }, {  19,  17 }, {  31,  25 }, {  36,  29 },
++        {  24,  33 }, {  34,  15 }, {  30,  20 }, {  22,  73 },
++        {   4,  39 }, {   0,  42 }, {   7,  34 }, {  11,  29 },
++        {   8,  31 }, {   6,  37 }, {   7,  42 }, {   3,  40 },
++        {   8,  33 }, {  13,  43 }, {  13,  36 }, {   4,  47 },
++        {   3,  55 }, {   2,  58 }, {   6,  60 }, {   8,  44 },
++        {  11,  44 }, {  14,  42 }, {   7,  48 }, {   4,  56 },
++        {   4,  52 }, {  13,  37 }, {   9,  49 }, {  19,  58 },
++        {  10,  48 }, {  12,  45 }, {   0,  69 }, {  20,  33 },
++        {   8,  63 }, {  35, -18 }, {  33, -25 }, {  28,  -3 },
++        {  24,  10 }, {  27,   0 }, {  34, -14 }, {  52, -44 },
++        {  39, -24 }, {  19,  17 }, {  31,  25 }, {  36,  29 },
++        {  24,  33 }, {  34,  15 }, {  30,  20 }, {  22,  73 },
++        {  -3,  78 }, {  -8,  74 }, {  -9,  72 }, { -10,  72 },
++        { -18,  75 }, { -12,  71 }, { -11,  63 }, {  -5,  70 },
++        { -17,  75 }, { -14,  72 }, { -16,  67 }, {  -8,  53 },
++        { -14,  59 }, {  -9,  52 }, { -11,  68 }, {  -3,  78 },
++        {  -8,  74 }, {  -9,  72 }, { -10,  72 }, { -18,  75 },
++        { -12,  71 }, { -11,  63 }, {  -5,  70 }, { -17,  75 },
++        { -14,  72 }, { -16,  67 }, {  -8,  53 }, { -14,  59 },
++        {  -9,  52 }, { -11,  68 }, {   9,  -2 }, {  30, -10 },
++        {  31,  -4 }, {  33,  -1 }, {  33,   7 }, {  31,  12 },
++        {  37,  23 }, {  31,  38 }, {  20,  64 }, {   9,  -2 },
++        {  30, -10 }, {  31,  -4 }, {  33,  -1 }, {  33,   7 },
++        {  31,  12 }, {  37,  23 }, {  31,  38 }, {  20,  64 },
++        {  -9,  71 }, {  -7,  37 }, {  -8,  44 }, { -11,  49 },
++        { -10,  56 }, { -12,  59 }, {  -8,  63 }, {  -9,  67 },
++        {  -6,  68 }, { -10,  79 }, {  -3,  78 }, {  -8,  74 },
++        {  -9,  72 }, { -10,  72 }, { -18,  75 }, { -12,  71 },
++        { -11,  63 }, {  -5,  70 }, { -17,  75 }, { -14,  72 },
++        { -16,  67 }, {  -8,  53 }, { -14,  59 }, {  -9,  52 },
++        { -11,  68 }, {  -3,  78 }, {  -8,  74 }, {  -9,  72 },
++        { -10,  72 }, { -18,  75 }, { -12,  71 }, { -11,  63 },
++        {  -5,  70 }, { -17,  75 }, { -14,  72 }, { -16,  67 },
++        {  -8,  53 }, { -14,  59 }, {  -9,  52 }, { -11,  68 },
++        {   9,  -2 }, {  30, -10 }, {  31,  -4 }, {  33,  -1 },
++        {  33,   7 }, {  31,  12 }, {  37,  23 }, {  31,  38 },
++        {  20,  64 }, {   9,  -2 }, {  30, -10 }, {  31,  -4 },
++        {  33,  -1 }, {  33,   7 }, {  31,  12 }, {  37,  23 },
++        {  31,  38 }, {  20,  64 }, {  -9,  71 }, {  -7,  37 },
++        {  -8,  44 }, { -11,  49 }, { -10,  56 }, { -12,  59 },
++        {  -8,  63 }, {  -9,  67 }, {  -6,  68 }, { -10,  79 },
++        { -22, 127 }, { -25, 127 }, { -25, 120 }, { -27, 127 },
++        { -19, 114 }, { -23, 117 }, { -25, 118 }, { -26, 117 },
++        { -24, 113 }, { -28, 118 }, { -31, 120 }, { -37, 124 },
++        { -10,  94 }, { -15, 102 }, { -10,  99 }, { -13, 106 },
++        { -50, 127 }, {  -5,  92 }, {  17,  57 }, {  -5,  86 },
++        { -13,  94 }, { -12,  91 }, {  -2,  77 }, {   0,  71 },
++        {  -1,  73 }, {   4,  64 }, {  -7,  81 }, {   5,  64 },
++        {  15,  57 }, {   1,  67 }, {   0,  68 }, { -10,  67 },
++        {   1,  68 }, {   0,  77 }, {   2,  64 }, {   0,  68 },
++        {  -5,  78 }, {   7,  55 }, {   5,  59 }, {   2,  65 },
++        {  14,  54 }, {  15,  44 }, {   5,  60 }, {   2,  70 },
++        { -22, 127 }, { -25, 127 }, { -25, 120 }, { -27, 127 },
++        { -19, 114 }, { -23, 117 }, { -25, 118 }, { -26, 117 },
++        { -24, 113 }, { -28, 118 }, { -31, 120 }, { -37, 124 },
++        { -10,  94 }, { -15, 102 }, { -10,  99 }, { -13, 106 },
++        { -50, 127 }, {  -5,  92 }, {  17,  57 }, {  -5,  86 },
++        { -13,  94 }, { -12,  91 }, {  -2,  77 }, {   0,  71 },
++        {  -1,  73 }, {   4,  64 }, {  -7,  81 }, {   5,  64 },
++        {  15,  57 }, {   1,  67 }, {   0,  68 }, { -10,  67 },
++        {   1,  68 }, {   0,  77 }, {   2,  64 }, {   0,  68 },
++        {  -5,  78 }, {   7,  55 }, {   5,  59 }, {   2,  65 },
++        {  14,  54 }, {  15,  44 }, {   5,  60 }, {   2,  70 },
++        {  17, -13 }, {  16,  -9 }, {  17, -12 }, {  27, -21 },
++        {  37, -30 }, {  41, -40 }, {  42, -41 }, {  48, -47 },
++        {  39, -32 }, {  46, -40 }, {  52, -51 }, {  46, -41 },
++        {  52, -39 }, {  43, -19 }, {  32,  11 }, {  61, -55 },
++        {  56, -46 }, {  62, -50 }, {  81, -67 }, {  45, -20 },
++        {  35,  -2 }, {  28,  15 }, {  34,   1 }, {  39,   1 },
++        {  30,  17 }, {  20,  38 }, {  18,  45 }, {  15,  54 },
++        {   0,  79 }, {  36, -16 }, {  37, -14 }, {  37, -17 },
++        {  32,   1 }, {  34,  15 }, {  29,  15 }, {  24,  25 },
++        {  34,  22 }, {  31,  16 }, {  35,  18 }, {  31,  28 },
++        {  33,  41 }, {  36,  28 }, {  27,  47 }, {  21,  62 },
++        {  17, -13 }, {  16,  -9 }, {  17, -12 }, {  27, -21 },
++        {  37, -30 }, {  41, -40 }, {  42, -41 }, {  48, -47 },
++        {  39, -32 }, {  46, -40 }, {  52, -51 }, {  46, -41 },
++        {  52, -39 }, {  43, -19 }, {  32,  11 }, {  61, -55 },
++        {  56, -46 }, {  62, -50 }, {  81, -67 }, {  45, -20 },
++        {  35,  -2 }, {  28,  15 }, {  34,   1 }, {  39,   1 },
++        {  30,  17 }, {  20,  38 }, {  18,  45 }, {  15,  54 },
++        {   0,  79 }, {  36, -16 }, {  37, -14 }, {  37, -17 },
++        {  32,   1 }, {  34,  15 }, {  29,  15 }, {  24,  25 },
++        {  34,  22 }, {  31,  16 }, {  35,  18 }, {  31,  28 },
++        {  33,  41 }, {  36,  28 }, {  27,  47 }, {  21,  62 },
++        { -24, 115 }, { -22,  82 }, {  -9,  62 }, {   0,  53 },
++        {   0,  59 }, { -14,  85 }, { -13,  89 }, { -13,  94 },
++        { -11,  92 }, { -29, 127 }, { -21, 100 }, { -14,  57 },
++        { -12,  67 }, { -11,  71 }, { -10,  77 }, { -21,  85 },
++        { -16,  88 }, { -23, 104 }, { -15,  98 }, { -37, 127 },
++        { -10,  82 }, {  -8,  48 }, {  -8,  61 }, {  -8,  66 },
++        {  -7,  70 }, { -14,  75 }, { -10,  79 }, {  -9,  83 },
++        { -12,  92 }, { -18, 108 }, { -24, 115 }, { -22,  82 },
++        {  -9,  62 }, {   0,  53 }, {   0,  59 }, { -14,  85 },
++        { -13,  89 }, { -13,  94 }, { -11,  92 }, { -29, 127 },
++        { -21, 100 }, { -14,  57 }, { -12,  67 }, { -11,  71 },
++        { -10,  77 }, { -21,  85 }, { -16,  88 }, { -23, 104 },
++        { -15,  98 }, { -37, 127 }, { -10,  82 }, {  -8,  48 },
++        {  -8,  61 }, {  -8,  66 }, {  -7,  70 }, { -14,  75 },
++        { -10,  79 }, {  -9,  83 }, { -12,  92 }, { -18, 108 },
++        {  -5,  79 }, { -11, 104 }, { -11,  91 }, { -30, 127 },
++        {  -5,  79 }, { -11, 104 }, { -11,  91 }, { -30, 127 },
++        {  -5,  79 }, { -11, 104 }, { -11,  91 }, { -30, 127 }
++    }
++};
++
++const uint8_t h264_cabac_range_lps[64][4] =
++{
++    {  2,   2,   2,   2}, {  6,   7,   8,   9}, {  6,   7,   9,  10}, {  6,   8,   9,  11},
++    {  7,   8,  10,  11}, {  7,   9,  10,  12}, {  7,   9,  11,  12}, {  8,   9,  11,  13},
++    {  8,  10,  12,  14}, {  9,  11,  12,  14}, {  9,  11,  13,  15}, { 10,  12,  14,  16},
++    { 10,  12,  15,  17}, { 11,  13,  15,  18}, { 11,  14,  16,  19}, { 12,  14,  17,  20},
++    { 12,  15,  18,  21}, { 13,  16,  19,  22}, { 14,  17,  20,  23}, { 14,  18,  21,  24},
++    { 15,  19,  22,  25}, { 16,  20,  23,  27}, { 17,  21,  25,  28}, { 18,  22,  26,  30},
++    { 19,  23,  27,  31}, { 20,  24,  29,  33}, { 21,  26,  30,  35}, { 22,  27,  32,  37},
++    { 23,  28,  33,  39}, { 24,  30,  35,  41}, { 26,  31,  37,  43}, { 27,  33,  39,  45},
++    { 29,  35,  41,  48}, { 30,  37,  43,  50}, { 32,  39,  46,  53}, { 33,  41,  48,  56},
++    { 35,  43,  51,  59}, { 37,  45,  54,  62}, { 39,  48,  56,  65}, { 41,  50,  59,  69},
++    { 43,  53,  63,  72}, { 46,  56,  66,  76}, { 48,  59,  69,  80}, { 51,  62,  73,  85},
++    { 53,  65,  77,  89}, { 56,  69,  81,  94}, { 59,  72,  86,  99}, { 62,  76,  90, 104},
++    { 66,  80,  95, 110}, { 69,  85, 100, 116}, { 73,  89, 105, 122}, { 77,  94, 111, 128},
++    { 81,  99, 117, 135}, { 85, 104, 123, 142}, { 90, 110, 130, 150}, { 95, 116, 137, 158},
++    {100, 122, 144, 166}, {105, 128, 152, 175}, {111, 135, 160, 185}, {116, 142, 169, 195},
++    {123, 150, 178, 205}, {128, 158, 187, 216}, {128, 167, 197, 227}, {128, 176, 208, 240}
++};
++
++const uint8_t h264_cabac_transition[128][2] =
++{
++    {  0,   0}, {  1,   1}, {  2,  50}, { 51,   3}, {  2,  50}, { 51,   3}, {  4,  52}, { 53,   5},
++    {  6,  52}, { 53,   7}, {  8,  52}, { 53,   9}, { 10,  54}, { 55,  11}, { 12,  54}, { 55,  13},
++    { 14,  54}, { 55,  15}, { 16,  56}, { 57,  17}, { 18,  56}, { 57,  19}, { 20,  56}, { 57,  21},
++    { 22,  58}, { 59,  23}, { 24,  58}, { 59,  25}, { 26,  60}, { 61,  27}, { 28,  60}, { 61,  29},
++    { 30,  60}, { 61,  31}, { 32,  62}, { 63,  33}, { 34,  62}, { 63,  35}, { 36,  64}, { 65,  37},
++    { 38,  66}, { 67,  39}, { 40,  66}, { 67,  41}, { 42,  66}, { 67,  43}, { 44,  68}, { 69,  45},
++    { 46,  68}, { 69,  47}, { 48,  70}, { 71,  49}, { 50,  72}, { 73,  51}, { 52,  72}, { 73,  53},
++    { 54,  74}, { 75,  55}, { 56,  74}, { 75,  57}, { 58,  76}, { 77,  59}, { 60,  78}, { 79,  61},
++    { 62,  78}, { 79,  63}, { 64,  80}, { 81,  65}, { 66,  82}, { 83,  67}, { 68,  82}, { 83,  69},
++    { 70,  84}, { 85,  71}, { 72,  84}, { 85,  73}, { 74,  88}, { 89,  75}, { 76,  88}, { 89,  77},
++    { 78,  90}, { 91,  79}, { 80,  90}, { 91,  81}, { 82,  94}, { 95,  83}, { 84,  94}, { 95,  85},
++    { 86,  96}, { 97,  87}, { 88,  96}, { 97,  89}, { 90, 100}, {101,  91}, { 92, 100}, {101,  93},
++    { 94, 102}, {103,  95}, { 96, 104}, {105,  97}, { 98, 104}, {105,  99}, {100, 108}, {109, 101},
++    {102, 108}, {109, 103}, {104, 110}, {111, 105}, {106, 112}, {113, 107}, {108, 114}, {115, 109},
++    {110, 116}, {117, 111}, {112, 118}, {119, 113}, {114, 118}, {119, 115}, {116, 122}, {123, 117},
++    {118, 122}, {123, 119}, {120, 124}, {125, 121}, {122, 126}, {127, 123}, {124, 127}, {126, 125}
++};
++
++const uint8_t h264_cabac_renorm_shift[64] =
++{
++    6,5,4,4,3,3,3,3,2,2,2,2,2,2,2,2,
++    1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
++    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
++    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
++};
++
++/* -ln2(probability) */
++const uint16_t h264_cabac_entropy[128] =
++{
++    C_FIX8(0.0273), C_FIX8(5.7370), C_FIX8(0.0288), C_FIX8(5.6618),
++    C_FIX8(0.0303), C_FIX8(5.5866), C_FIX8(0.0320), C_FIX8(5.5114),
++    C_FIX8(0.0337), C_FIX8(5.4362), C_FIX8(0.0355), C_FIX8(5.3610),
++    C_FIX8(0.0375), C_FIX8(5.2859), C_FIX8(0.0395), C_FIX8(5.2106),
++    C_FIX8(0.0416), C_FIX8(5.1354), C_FIX8(0.0439), C_FIX8(5.0602),
++    C_FIX8(0.0463), C_FIX8(4.9851), C_FIX8(0.0488), C_FIX8(4.9099),
++    C_FIX8(0.0515), C_FIX8(4.8347), C_FIX8(0.0543), C_FIX8(4.7595),
++    C_FIX8(0.0572), C_FIX8(4.6843), C_FIX8(0.0604), C_FIX8(4.6091),
++    C_FIX8(0.0637), C_FIX8(4.5339), C_FIX8(0.0671), C_FIX8(4.4588),
++    C_FIX8(0.0708), C_FIX8(4.3836), C_FIX8(0.0747), C_FIX8(4.3083),
++    C_FIX8(0.0788), C_FIX8(4.2332), C_FIX8(0.0832), C_FIX8(4.1580),
++    C_FIX8(0.0878), C_FIX8(4.0828), C_FIX8(0.0926), C_FIX8(4.0076),
++    C_FIX8(0.0977), C_FIX8(3.9324), C_FIX8(0.1032), C_FIX8(3.8572),
++    C_FIX8(0.1089), C_FIX8(3.7820), C_FIX8(0.1149), C_FIX8(3.7068),
++    C_FIX8(0.1214), C_FIX8(3.6316), C_FIX8(0.1282), C_FIX8(3.5565),
++    C_FIX8(0.1353), C_FIX8(3.4813), C_FIX8(0.1429), C_FIX8(3.4061),
++    C_FIX8(0.1510), C_FIX8(3.3309), C_FIX8(0.1596), C_FIX8(3.2557),
++    C_FIX8(0.1686), C_FIX8(3.1805), C_FIX8(0.1782), C_FIX8(3.1053),
++    C_FIX8(0.1884), C_FIX8(3.0301), C_FIX8(0.1992), C_FIX8(2.9549),
++    C_FIX8(0.2107), C_FIX8(2.8797), C_FIX8(0.2229), C_FIX8(2.8046),
++    C_FIX8(0.2358), C_FIX8(2.7294), C_FIX8(0.2496), C_FIX8(2.6542),
++    C_FIX8(0.2642), C_FIX8(2.5790), C_FIX8(0.2798), C_FIX8(2.5038),
++    C_FIX8(0.2964), C_FIX8(2.4286), C_FIX8(0.3142), C_FIX8(2.3534),
++    C_FIX8(0.3331), C_FIX8(2.2782), C_FIX8(0.3532), C_FIX8(2.2030),
++    C_FIX8(0.3748), C_FIX8(2.1278), C_FIX8(0.3979), C_FIX8(2.0527),
++    C_FIX8(0.4226), C_FIX8(1.9775), C_FIX8(0.4491), C_FIX8(1.9023),
++    C_FIX8(0.4776), C_FIX8(1.8271), C_FIX8(0.5082), C_FIX8(1.7519),
++    C_FIX8(0.5412), C_FIX8(1.6767), C_FIX8(0.5768), C_FIX8(1.6015),
++    C_FIX8(0.6152), C_FIX8(1.5263), C_FIX8(0.6568), C_FIX8(1.4511),
++    C_FIX8(0.7020), C_FIX8(1.3759), C_FIX8(0.7513), C_FIX8(1.3008),
++    C_FIX8(0.8050), C_FIX8(1.2256), C_FIX8(0.8638), C_FIX8(1.1504),
++    C_FIX8(0.9285), C_FIX8(1.0752), C_FIX8(1.0000), C_FIX8(1.0000)
++};
++
++uint8_t h264_cabac_contexts[4][QP_MAX_SPEC+1][1024];
++
++void h264_cabac_init(void)
++{
++	int i = 0, j = 0, qp = 0;
++    int ctx_count = 460;
++    for( i = 0; i < 4; i++ )
++    {
++        const int8_t (*cabac_context_init)[1024][2] = i == 0 ? &h264_cabac_context_init_I
++                                                             : &h264_cabac_context_init_PB[i-1];
++        for( qp = 0; qp <= QP_MAX_SPEC; qp++ )
++            for( j = 0; j < ctx_count; j++ )
++            {
++                h264_cabac_contexts[i][qp][j] = c_clip3( (((*cabac_context_init)[j][0] * qp) >> 4) + (*cabac_context_init)[j][1], 1, 126 );
++            }
++    }
++}
++
++/*****************************************************************************
++ *
++ *****************************************************************************/
++void h264_cabac_context_init(h264_cabac_t *cb, int i_slice_type, int i_qp, int i_model )
++{
++    memcpy( cb->state, h264_cabac_contexts[i_slice_type == M_SLICE_TYPE_I ? 0 : i_model + 1][i_qp], 460);
++}
++
++#if 0
++void h264_cabac_encode_init_core( h264_cabac_t *cb )
++{
++    cb->i_low   = 0;
++    cb->i_range = 0x01FE;
++    cb->i_queue = -9; // the first bit will be shifted away and not written
++    cb->i_bytes_outstanding = 0;
++}
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/cabac.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/cabac.h
+new file mode 100644
+index 000000000..046039199
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/cabac.h
+@@ -0,0 +1,28 @@
++#ifndef __CABAC_H__
++#define __CABAC_H__
++
++#include "common.h"
++
++typedef struct
++{
++    /* state */
++    int i_low;
++    int i_range;
++
++    uint8_t *p_start;
++    uint8_t *p;
++    uint8_t *p_end;
++
++    /* context */
++    uint8_t state[1024];
++
++} h264_cabac_t;
++
++extern void h264_cabac_init(void);
++extern void h264_cabac_context_init(h264_cabac_t *cb, int i_slice_type, int i_qp, int i_model );
++
++
++
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/common.c b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/common.c
+new file mode 100644
+index 000000000..04ee83639
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/common.c
+@@ -0,0 +1,11 @@
++#include "common.h"
++
++
++
++int c_clip3(int v, int i_min, int i_max)
++{
++    return ((v < i_min) ? i_min : ((v > i_max) ? i_max : v));
++}
++
++
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/common.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/common.h
+new file mode 100644
+index 000000000..2fba2c09c
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/common.h
+@@ -0,0 +1,58 @@
++#ifndef __H264ENC_COMMON_H__
++#define __H264ENC_COMMON_H__
++
++#ifdef __KERNEL__
++#include <linux/types.h>
++#include <linux/string.h>
++#else
++
++#include <stdint.h>
++#include <unistd.h>
++#include <string.h>
++#endif
++
++#include "osdep.h"
++#include "bitstream.h"
++#include "set.h"
++#include "slice.h"
++#include "cabac.h"
++#include "nal.h"
++
++#define C_MIN(a,b)                      ((a)<(b) ? (a) : (b))
++#define C_MAX(a,b)                      ((a)>(b) ? (a) : (b))
++#define C_MIN3(a,b,c)           C_MIN((a),C_MIN((b),(c)))
++#define C_MAX3(a,b,c)           C_MAX((a),C_MAX((b),(c)))
++#define C_MIN4(a,b,c,d)         C_MIN((a),C_MIN3((b),(c),(d)))
++#define C_MAX4(a,b,c,d)         C_MAX((a),C_MAX3((b),(c),(d)))
++#define C_XCHG(type,a,b)        do{ type t = a; a = b; b = t; } while(0)
++#define C_FIX8(f)                       ((int)(f*(1<<8)+.5))
++#define C_ALIGN(x,a)            (((x)+((a)-1))&~((a)-1))
++#define ARRAY_ELEMS(a)          ((sizeof(a))/(sizeof(a[0])))
++
++
++extern int c_clip3(int v, int i_min, int i_max);
++
++enum profile_e
++{
++	PROFILE_BASELINE = 66,
++	PROFILE_MAIN	= 77,
++	PROFILE_HIGH	= 100,
++	PROFILE_HIGH10  = 110,
++	PROFILE_HIGH422 = 122,
++	PROFILE_HIGH444_PREDICTIVE = 244,
++};
++
++
++enum chroma_format_e
++{
++    CHROMA_400 = 0,
++    CHROMA_420 = 1,
++    CHROMA_422 = 2,
++    CHROMA_444 = 3,
++};
++
++
++
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/nal.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/nal.h
+new file mode 100644
+index 000000000..3cd24317e
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/nal.h
+@@ -0,0 +1,59 @@
++#ifndef __H264_NAL_H__
++#define __H264_NAL_H__
++
++
++/****************************************************************************
++ * NAL structure and functions
++ ****************************************************************************/
++
++enum nal_unit_type_e
++{
++    NAL_UNKNOWN     = 0,
++    NAL_SLICE       = 1,
++    NAL_SLICE_DPA   = 2,
++    NAL_SLICE_DPB   = 3,
++    NAL_SLICE_DPC   = 4,
++    NAL_SLICE_IDR   = 5,    /* ref_idc != 0 */
++    NAL_SEI         = 6,    /* ref_idc == 0 */
++    NAL_SPS         = 7,
++    NAL_PPS         = 8,
++    NAL_AUD         = 9,
++    NAL_FILLER      = 12,
++    /* ref_idc == 0 for 6,9,10,11,12 */
++};
++
++enum nal_priority_e
++{
++    NAL_PRIORITY_DISPOSABLE = 0,
++    NAL_PRIORITY_LOW        = 1,
++    NAL_PRIORITY_HIGH       = 2,
++    NAL_PRIORITY_HIGHEST    = 3,
++};
++
++
++/* The data within the payload is already NAL-encapsulated; the ref_idc and type
++ * are merely in the struct for easy access by the calling application.
++ * All data returned in an h264_nal_t, including the data in p_payload, is no longer
++ * valid after the next call to h264_encoder_encode.  Thus it must be used or copied
++ * before calling h264_encoder_encode or h264_encoder_headers again. */
++typedef struct h264_nal_t
++{
++    int i_ref_idc;  /* nal_priority_e */
++    int i_type;     /* nal_unit_type_e */
++    int b_long_startcode;
++    int i_first_mb; /* If this NAL is a slice, the index of the first MB in the slice. */
++    int i_last_mb;  /* If this NAL is a slice, the index of the last MB in the slice. */
++
++    /* Size of payload (including any padding) in bytes. */
++    int     i_payload;
++    /* If param->b_annexb is set, Annex-B bytestream with startcode.
++     * Otherwise, startcode is replaced with a 4-byte size.
++     * This size is the size used in mp4/similar muxing; it is equal to i_payload-4 */
++    uint8_t *p_payload;
++
++    /* Size of padding in bytes. */
++    int i_padding;
++} h264_nal_t;
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/osdep.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/osdep.h
+new file mode 100644
+index 000000000..3c22b6af4
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/osdep.h
+@@ -0,0 +1,39 @@
++#ifndef __OSDEP_H__
++#define __OSDEP_H__
++
++#define WORD_SIZE sizeof(void *) /*4 Bytes*/
++
++
++#ifdef __KERNEL__
++typedef long intptr_t;
++
++typedef unsigned char uint8_t;
++typedef unsigned short uint16_t;
++typedef unsigned int uint32_t;
++typedef unsigned long long uint64_t;
++#endif
++
++
++static inline uint32_t endian_fix32( uint32_t x )
++{
++	return (x<<24) + ((x<<8)&0xff0000) + ((x>>8)&0xff00) + (x>>24);
++
++}
++static inline uint64_t endian_fix64( uint64_t x )
++{
++	return endian_fix32(x>>32) + ((uint64_t)endian_fix32(x)<<32);
++}
++static inline intptr_t endian_fix( intptr_t x )
++{
++	return WORD_SIZE == 8 ? endian_fix64(x) : endian_fix32(x);
++}
++static inline uint16_t endian_fix16( uint16_t x )
++{
++	return (x<<8)|(x>>8);
++}
++
++
++
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/set.c b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/set.c
+new file mode 100644
+index 000000000..bea400d06
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/set.c
+@@ -0,0 +1,141 @@
++#ifdef __KERNEL__
++#include <linux/printk.h>
++#else
++
++#define printk printf
++#endif
++#include "common.h"
++
++void dump_sps(h264_sps_t *sps)
++{
++	printk("---sps->i_profile_idc %d\n", sps->i_profile_idc);
++	printk("---sps->b_constraint_set0 %d\n", sps->b_constraint_set0);
++	printk("---sps->b_constraint_set1 %d\n", sps->b_constraint_set1);
++	printk("---sps->b_constraint_set2 %d\n", sps->b_constraint_set2);
++	printk("---sps->b_constraint_set3 %d\n", sps->b_constraint_set3);
++
++	printk("---sps->i_level_idc %d\n", sps->i_level_idc);
++	printk("---sps->i_id %d\n", sps->i_id);
++	printk("---sps->i_num_ref_frames %d\n", sps->i_num_ref_frames);
++	printk("---sps->i_mb_width %d\n", sps->i_mb_width);
++	printk("---sps->i_mb_height %d\n", sps->i_mb_height);
++}
++
++void dump_pps(h264_pps_t *pps)
++{
++	printk("---pps->i_sps_id %d\n", pps->i_sps_id);
++	printk("---pps->b_cabac %d\n", pps->b_cabac);
++	printk("---pps->i_num_slice_groups %d\n", pps->i_num_slice_groups);
++}
++
++void h264e_sps_write(bs_t *s, h264_sps_t *sps)
++{
++	bs_realign(s);
++	bs_write(s, 8, sps->i_profile_idc);
++
++	bs_write1(s, sps->b_constraint_set0);
++	bs_write1(s, sps->b_constraint_set1);
++	bs_write1(s, sps->b_constraint_set2);
++	bs_write1(s, sps->b_constraint_set3);
++
++	bs_write(s, 4, 0); //reserved_zero_4bits; /* equal to 0*/
++	bs_write(s, 8, sps->i_level_idc);
++	bs_write_ue(s, sps->i_id);
++
++	bs_write_ue(s, sps->i_log2_max_frame_num - 4); // log2_max_frame_num_minus4;
++	bs_write_ue(s, sps->i_poc_type); // pic_order_cnt_type;
++	if(sps->i_poc_type == 0)
++		bs_write_ue(s, sps->i_log2_max_poc_lsb - 4);
++
++	bs_write_ue( s, sps->i_num_ref_frames );
++	bs_write1( s, sps->b_gaps_in_frame_num_value_allowed );
++	bs_write_ue( s, sps->i_mb_width - 1 ); /*pic_width_in_mbs_minus1*/
++	bs_write_ue( s, (sps->i_mb_height >> !sps->b_frame_mbs_only) - 1);
++	bs_write1( s, sps->b_frame_mbs_only );
++
++	if( !sps->b_frame_mbs_only )
++		bs_write1( s, sps->b_mb_adaptive_frame_field );
++	bs_write1( s, sps->b_direct8x8_inference );
++
++	bs_write1( s, sps->b_crop );
++	if( sps->b_crop )
++	{
++		int h_shift = sps->i_chroma_format_idc == CHROMA_420 || sps->i_chroma_format_idc == CHROMA_422;
++		int v_shift = sps->i_chroma_format_idc == CHROMA_420;
++		bs_write_ue( s, sps->crop.i_left   >> h_shift );
++		bs_write_ue( s, sps->crop.i_right  >> h_shift );
++		bs_write_ue( s, sps->crop.i_top    >> v_shift );
++		bs_write_ue( s, sps->crop.i_bottom >> v_shift );
++	}
++
++	bs_write1( s, sps->b_vui );
++	if(sps->b_vui) {
++	}
++
++	bs_rbsp_trailing( s );
++	bs_flush( s );
++}
++
++void h264e_pps_write(bs_t *s, h264_sps_t *sps, h264_pps_t *pps)
++{
++	bs_realign(s);
++	bs_write_ue(s, pps->i_id);
++	bs_write_ue(s, pps->i_sps_id);
++
++	bs_write1(s, pps->b_cabac);
++	bs_write1(s, pps->b_pic_order);
++	bs_write_ue(s, pps->i_num_slice_groups - 1);
++
++	bs_write_ue(s, pps->i_num_ref_idx_l0_default_active - 1);
++	bs_write_ue(s, pps->i_num_ref_idx_l1_default_active - 1);
++	bs_write1(s, pps->b_weighted_pred);
++	bs_write(s, 2, pps->b_weighted_bipred);
++
++	bs_write_se(s, pps->i_pic_init_qp - 26);
++	bs_write_se(s, pps->i_pic_init_qs - 26);
++	bs_write_se(s, pps->i_chroma_qp_index_offset);
++
++	bs_write1(s, pps->b_deblocking_filter_control);
++	bs_write1(s, pps->b_constrained_intra_pred);
++	bs_write1(s, pps->b_redundant_pic_cnt);
++
++	if(pps->b_transform_8x8_mode) {
++
++		bs_write1(s, pps->b_transform_8x8_mode);
++		bs_write1(s, 0);
++
++		bs_write_se(s, pps->i_chroma_qp_index_offset);
++
++	}
++
++	bs_rbsp_trailing(s);
++	bs_flush(s);
++}
++
++
++void h264e_sei_write(bs_t *s, uint8_t *payload, int payload_size, int payload_type)
++{
++	int i;
++	bs_realign( s );
++	for( i = 0; i <= payload_type-255; i += 255 )
++		bs_write( s, 8, 255 );
++	bs_write( s, 8, payload_type-i );
++
++	for( i = 0; i <= payload_size-255; i += 255 )
++		bs_write( s, 8, 255 );
++	bs_write( s, 8, payload_size-i );
++
++	for( i = 0; i < payload_size; i++ )
++		bs_write( s, 8, payload[i] );
++
++	bs_rbsp_trailing( s );
++	bs_flush( s );
++}
++
++int h264e_sei_version_write(bs_t *s)
++{
++	return 0;
++}
++
++
++
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/set.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/set.h
+new file mode 100644
+index 000000000..dbcac827f
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/set.h
+@@ -0,0 +1,150 @@
++#ifndef H264_SET_H
++#define H264_SET_H
++
++#include "bitstream.h"
++
++typedef struct
++{
++    int i_id;
++
++    int i_profile_idc;
++    int i_level_idc;
++
++    int b_constraint_set0;
++    int b_constraint_set1;
++    int b_constraint_set2;
++    int b_constraint_set3;
++
++    int i_log2_max_frame_num;
++
++    int i_poc_type;
++    /* poc 0 */
++    int i_log2_max_poc_lsb;
++
++    int i_num_ref_frames;
++    int b_gaps_in_frame_num_value_allowed;
++    int i_mb_width;
++    int i_mb_height;
++    int b_frame_mbs_only;
++    int b_mb_adaptive_frame_field;
++    int b_direct8x8_inference;
++
++    int b_crop;
++    struct
++    {
++        int i_left;
++        int i_right;
++        int i_top;
++        int i_bottom;
++    } crop;
++
++    int b_vui;
++    struct
++    {
++        int b_aspect_ratio_info_present;
++        int i_sar_width;
++        int i_sar_height;
++
++        int b_overscan_info_present;
++        int b_overscan_info;
++
++        int b_signal_type_present;
++        int i_vidformat;
++        int b_fullrange;
++        int b_color_description_present;
++        int i_colorprim;
++        int i_transfer;
++        int i_colmatrix;
++
++        int b_chroma_loc_info_present;
++        int i_chroma_loc_top;
++        int i_chroma_loc_bottom;
++
++        int b_timing_info_present;
++        uint32_t i_num_units_in_tick;
++        uint32_t i_time_scale;
++        int b_fixed_frame_rate;
++
++        int b_nal_hrd_parameters_present;
++        int b_vcl_hrd_parameters_present;
++
++        struct
++        {
++            int i_cpb_cnt;
++            int i_bit_rate_scale;
++            int i_cpb_size_scale;
++            int i_bit_rate_value;
++            int i_cpb_size_value;
++            int i_bit_rate_unscaled;
++            int i_cpb_size_unscaled;
++            int b_cbr_hrd;
++
++            int i_initial_cpb_removal_delay_length;
++            int i_cpb_removal_delay_length;
++            int i_dpb_output_delay_length;
++            int i_time_offset_length;
++        } hrd;
++
++        int b_pic_struct_present;
++        int b_bitstream_restriction;
++        int b_motion_vectors_over_pic_boundaries;
++        int i_max_bytes_per_pic_denom;
++        int i_max_bits_per_mb_denom;
++        int i_log2_max_mv_length_horizontal;
++        int i_log2_max_mv_length_vertical;
++        int i_num_reorder_frames;
++        int i_max_dec_frame_buffering;
++
++        /* FIXME to complete */
++    } vui;
++
++    int b_qpprime_y_zero_transform_bypass;
++    int i_chroma_format_idc;
++
++    int b_avcintra;
++    int i_cqm_preset;
++    const uint8_t *scaling_list[8]; /* could be 12, but we don't allow separate Cb/Cr lists */
++
++} h264_sps_t;
++
++typedef struct
++{
++    int i_id;
++    int i_sps_id;
++
++    int b_cabac;
++
++    int b_pic_order;
++    int i_num_slice_groups;
++
++    int i_num_ref_idx_l0_default_active;
++    int i_num_ref_idx_l1_default_active;
++
++    int b_weighted_pred;
++    int b_weighted_bipred;
++
++    int i_pic_init_qp;
++    int i_pic_init_qs;
++
++    int i_chroma_qp_index_offset;
++
++    int b_deblocking_filter_control;
++    int b_constrained_intra_pred;
++    int b_redundant_pic_cnt;
++
++    int b_transform_8x8_mode;
++
++} h264_pps_t;
++
++
++
++extern void h264e_sps_write(bs_t *s, h264_sps_t *sps);
++
++extern void h264e_pps_write(bs_t *s, h264_sps_t *sps, h264_pps_t *pps);
++
++extern void h264e_sei_write(bs_t *s, uint8_t *payload, int payload_size, int payload_type);
++
++extern int h264e_sei_version_write(bs_t *s);
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/slice.c b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/slice.c
+new file mode 100644
+index 000000000..ce8cdcf8f
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/slice.c
+@@ -0,0 +1,162 @@
++#include "cabac.h"
++#include "slice.h"
++
++#ifdef __KERNEL__
++#include <linux/printk.h>
++
++#define printf printk
++#endif
++
++
++
++void xdump_slice_header(h264_slice_header_t *sh)
++{
++	printf("sh->i_type			: %d\n", sh->i_type);
++	printf("sh->i_first_mb			: %d\n", sh->i_first_mb);
++	printf("sh->i_last_mb			: %d\n", sh->i_last_mb);
++	printf("sh->i_pps_id			: %d\n", sh->i_pps_id);
++	printf("sh->i_frame_num			: %d\n", sh->i_frame_num);
++	printf("sh->b_mbaff			: %d\n", sh->b_mbaff);
++	printf("sh->b_field_pic			: %d\n", sh->b_field_pic);
++	printf("sh->b_bottom_field		: %d\n", sh->b_bottom_field);
++	printf("sh->i_idr_pic_id		: %d\n", sh->i_idr_pic_id);
++	printf("sh->i_poc			: %d\n", sh->i_poc);
++	printf("sh->i_delta_poc_bottom		: %d\n", sh->i_delta_poc_bottom);
++	printf("sh->i_delta_poc[0]:		: %d\n", sh->i_delta_poc[0]);
++	printf("sh->i_delta_poc[1]:		: %d\n", sh->i_delta_poc[1]);
++	printf("sh->b_direct_spatial_mv_pred	: %d\n", sh->b_direct_spatial_mv_pred);
++	printf("sh->b_num_ref_idx_override	: %d\n", sh->b_num_ref_idx_override);
++	printf("sh->i_num_ref_idx_l0_active	: %d\n", sh->i_num_ref_idx_l0_active);
++	printf("sh->i_num_ref_idx_l1_active	: %d\n", sh->i_num_ref_idx_l1_active);
++
++
++	printf("sh->i_cabac_init_idc		: %d\n", sh->i_cabac_init_idc);
++	printf("sh->i_qp			: %d\n", sh->i_qp);
++	printf("sh->i_qp_delta			: %d\n", sh->i_qp_delta);
++	printf("sh->b_sp_for_swidth		: %d\n", sh->b_sp_for_swidth);
++	printf("sh->i_qs_delta			: %d\n", sh->i_qs_delta);
++
++
++}
++
++void h264e_slice_header_init(h264_slice_header_t *sh,
++				h264_sps_t *sps, h264_pps_t *pps,
++				int i_idr_pic_id, int i_frame, int i_qp)
++{
++	sh->sps = sps;
++	sh->pps = pps;
++
++	sh->i_first_mb = 0;
++	sh->i_last_mb = sps->i_mb_width * sps->i_mb_height - 1;
++	sh->i_pps_id = pps->i_id;
++	sh->i_frame_num = i_frame;
++
++	sh->b_mbaff = 0;
++	sh->b_field_pic = 0;
++	sh->b_bottom_field = 0;
++
++	sh->i_idr_pic_id = i_idr_pic_id;
++
++	sh->i_poc = 0;
++	sh->i_delta_poc_bottom = 0;
++	sh->i_delta_poc[0] = 0;
++	sh->i_delta_poc[1] = 0;
++
++
++	sh->i_redundant_pic_cnt = 0;
++
++	sh->b_num_ref_idx_override = 0;
++	sh->i_num_ref_idx_l0_active = 1;
++	sh->i_num_ref_idx_l1_active = 1;
++
++	sh->b_ref_pic_list_reordering[0] = 0;
++	sh->b_ref_pic_list_reordering[1] = 0;
++
++
++	sh->i_cabac_init_idc = 0;
++
++	sh->i_qp = SPEC_QP(i_qp);
++	sh->i_qp_delta = sh->i_qp - pps->i_pic_init_qp;
++
++	sh->b_sp_for_swidth = 0;
++	sh->i_qs_delta = 0;
++
++	sh->i_disable_deblocking_filter_idc = 1;
++	sh->i_alpha_c0_offset = 0;
++	sh->i_beta_offset = 0;
++}
++
++
++void h264e_slice_header_write(bs_t *s, h264_slice_header_t *sh, int i_nal_ref_idc)
++{
++	/*Do not support mbaff*/
++	bs_write_ue(s, sh->i_first_mb);
++	bs_write_ue(s, sh->i_type + 5);
++	bs_write_ue(s, sh->i_pps_id);
++	bs_write(s, sh->sps->i_log2_max_frame_num, sh->i_frame_num & ((1 << sh->sps->i_log2_max_frame_num) - 1));
++
++	/*mbs only*/
++
++	if(sh->i_idr_pic_id >= 0)
++		bs_write_ue(s, sh->i_idr_pic_id);
++
++
++	if(sh->i_type == M_SLICE_TYPE_P || sh->i_type == M_SLICE_TYPE_B) {
++		bs_write1(s, sh->b_num_ref_idx_override);
++		if(sh->b_num_ref_idx_override) {
++			bs_write_ue(s, sh->i_num_ref_idx_l0_active - 1);
++			if(sh->i_type == M_SLICE_TYPE_B)
++				bs_write_ue(s, sh->i_num_ref_idx_l1_active - 1);
++		}
++
++	}
++
++	if(sh->i_type != M_SLICE_TYPE_I) {
++		bs_write1(s, sh->b_ref_pic_list_reordering[0]);
++		if(sh->b_ref_pic_list_reordering[0]) {
++			int i;
++			for(i = 0; i < sh->i_num_ref_idx_l0_active; i++) {
++				bs_write_ue(s, sh->ref_pic_list_order[0][i].idc);
++				bs_write_ue(s, sh->ref_pic_list_order[0][i].arg);
++			}
++
++			bs_write_ue(s, 3);
++		}
++	}
++
++	if(i_nal_ref_idc != 0) {
++		if(sh->i_idr_pic_id >= 0) {
++			bs_write1(s, 0);
++			bs_write1(s, 0);
++		} else {
++			bs_write1( s, sh->i_mmco_command_count > 0 ); /* adaptive_ref_pic_marking_mode_flag */
++			if( sh->i_mmco_command_count > 0 )
++			{
++				int i = 0;
++				for(i = 0; i < sh->i_mmco_command_count; i++ )
++				{
++					bs_write_ue( s, 1 ); /* mark short term ref as unused */
++					bs_write_ue( s, sh->mmco[i].i_difference_of_pic_nums - 1 );
++				}
++				bs_write_ue( s, 0 ); /* end command list */
++			}
++
++		}
++
++	}
++
++	if( sh->pps->b_cabac && sh->i_type != M_SLICE_TYPE_I )
++		bs_write_ue( s, sh->i_cabac_init_idc );
++
++	bs_write_se( s, sh->i_qp_delta );      /* slice qp delta */
++
++	if( sh->pps->b_deblocking_filter_control )
++	{
++		bs_write_ue( s, sh->i_disable_deblocking_filter_idc );
++		if( sh->i_disable_deblocking_filter_idc != 1 )
++		{
++			bs_write_se( s, sh->i_alpha_c0_offset >> 1 );
++			bs_write_se( s, sh->i_beta_offset >> 1 );
++		}
++	}
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/slice.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/slice.h
+new file mode 100644
+index 000000000..c4fdb929f
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/h264enc/slice.h
+@@ -0,0 +1,99 @@
++#ifndef __H264_SLICE_H__
++#define __H264_SLICE_H__
++
++#include "common.h"
++
++enum slice_type_e
++{
++    M_SLICE_TYPE_P  = 0,
++    M_SLICE_TYPE_B  = 1,
++    M_SLICE_TYPE_I  = 2,
++};
++
++
++
++
++#define MAX(X, Y) ((X) >= (Y) ? (X) : (Y))
++#define MIN(X, Y) ((X) <= (Y) ? (X) : (Y))
++
++#define QP_MAX_SPEC             (51)
++
++#define X264_REF_MAX	1
++#define SPEC_QP(x)              MIN((x), QP_MAX_SPEC)
++
++
++typedef struct
++{
++	h264_sps_t *sps;
++	h264_pps_t *pps;
++
++	int i_type;
++	int i_first_mb;
++	int i_last_mb;
++
++	int i_pps_id;
++
++	int i_frame_num;
++
++	int b_mbaff;
++	int b_field_pic;
++	int b_bottom_field;
++
++	int i_idr_pic_id;   /* -1 if nal_type != 5 */
++
++	int i_poc;
++	int i_delta_poc_bottom;
++
++	int i_delta_poc[2];
++	int i_redundant_pic_cnt;
++
++	int b_direct_spatial_mv_pred;
++
++	int b_num_ref_idx_override;
++	int i_num_ref_idx_l0_active;
++	int i_num_ref_idx_l1_active;
++
++	int b_ref_pic_list_reordering[2];
++	struct
++	{
++		int idc;
++		int arg;
++	} ref_pic_list_order[2][X264_REF_MAX];
++
++#if 0
++	/* 使用默认的加�预测 */
++	/* P-frame weighting */
++	int b_weighted_pred;
++	x264_weight_t weight[X264_REF_MAX*2][3];
++#endif
++	int i_mmco_remove_from_end;
++	int i_mmco_command_count;
++	struct /* struct for future expansion */
++	{
++		int i_difference_of_pic_nums;
++		int i_poc;
++	} mmco[X264_REF_MAX];
++
++	int i_cabac_init_idc;
++
++	int i_qp;
++	int i_qp_delta;
++	int b_sp_for_swidth;
++	int i_qs_delta;
++
++	/* deblocking filter */
++	int i_disable_deblocking_filter_idc;
++	int i_alpha_c0_offset;
++	int i_beta_offset;
++} h264_slice_header_t;
++
++
++extern void h264e_slice_header_init(h264_slice_header_t *sh,
++				h264_sps_t *sps, h264_pps_t *pps,
++				int i_idr_pic_id, int i_frame, int i_qp);
++
++extern void h264e_slice_header_write(bs_t *s, h264_slice_header_t *sh, int i_nal_ref_idc);
++
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/helix_buf.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/helix_buf.h
+new file mode 100644
+index 000000000..b977e0071
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/helix_buf.h
+@@ -0,0 +1,45 @@
++#ifndef __HELIX_BUF_H__
++#define __HELIX_BUF_H__
++
++enum helix_raw_format {
++	HELIX_TILE_MODE = 0,
++	HELIX_420P_MODE = 4,
++	HELIX_NV12_MODE = 8,
++	HELIX_NV21_MODE = 12,
++};
++
++
++/* JPEG encode quantization table select level */
++typedef enum {
++  LOW_QUALITY,
++  MEDIUMS_QUALITY,
++  HIGH_QUALITY
++} QUANT_QUALITY;
++
++
++struct h264_ref_tile {
++	unsigned int *yaddr;
++	unsigned int *caddr;
++
++	dma_addr_t yaddr_pa;
++	dma_addr_t caddr_pa;
++};
++
++
++/* basic memory description. */
++struct ingenic_vcodec_mem {
++	size_t size;
++	void *va;
++	dma_addr_t pa;
++};
++
++struct video_frame_buffer {
++	struct ingenic_vcodec_mem fb_addr[3];// MAX_PLANES.
++	int num_planes;
++};
++
++
++
++extern int ingenic_vpu_start(void *priv);
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/helix_drv.c b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/helix_drv.c
+new file mode 100644
+index 000000000..dd7d70547
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/helix_drv.c
+@@ -0,0 +1,550 @@
++/*
++* Copyright© 2014 Ingenic Semiconductor Co.,Ltd
++*
++* Author: qipengzhen <aric.pzqi@ingenic.com>
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License version 2 as
++* published by the Free Software Foundation.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++* GNU General Public License for more details.
++*
++*/
++
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/module.h>
++#include <linux/time.h>
++#include <linux/sched.h>
++#include <linux/wait.h>
++#include <linux/of_device.h>
++#include <linux/of_reserved_mem.h>
++#include <linux/of.h>
++#include <media/v4l2-event.h>
++#include <media/v4l2-mem2mem.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++#include <linux/pm_runtime.h>
++#include <linux/of_address.h>
++#include <linux/clk.h>
++#include <media/ingenic_video_nr.h>
++
++#include "helix_drv.h"
++#include "helix_ops.h"
++
++static int vpu_on(struct ingenic_venc_dev *dev);
++static int vpu_off(struct ingenic_venc_dev *dev);
++
++struct ingenic_venc_dev *g_dev = NULL;
++
++
++static int fops_vcodec_open(struct file *file)
++{
++	struct ingenic_venc_dev *dev = video_drvdata(file);
++	struct ingenic_venc_ctx *ctx = NULL;
++	int ret = 0;
++
++	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
++	if(!ctx)
++		return -ENOMEM;
++
++	mutex_lock(&dev->dev_mutex);
++
++	if (!dev->id_counter) {
++		vpu_on(dev);
++	}
++
++	ctx->id = dev->id_counter++;
++	v4l2_fh_init(&ctx->fh, video_devdata(file));
++	file->private_data = &ctx->fh;
++	v4l2_fh_add(&ctx->fh);
++	//INIT_LIST_HEAD(&ctx->list);
++	ctx->dev = dev;
++	init_waitqueue_head(&ctx->queue);
++
++	ingenic_vcodec_enc_init_default_params(ctx);
++
++	ret = ingenic_vcodec_enc_ctrls_setup(ctx);
++	if(ret) {
++		dev_err(ctx->dev->dev, "Failed to setup ctrls() %d\n", ret);
++		goto err_ctrls_setup;
++	}
++
++	ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev_enc, ctx, &ingenic_vcodec_enc_queue_init);
++	if(IS_ERR((__force void *)ctx->m2m_ctx)) {
++		ret = PTR_ERR((__force void *)ctx->m2m_ctx);
++
++		goto err_m2m_ctx_init;
++	}
++
++
++
++	mutex_unlock(&dev->dev_mutex);
++
++	dev_info(ctx->dev->dev, "Create instance [%d]@%p m2m_ctx=%p\n",
++			ctx->id, ctx, ctx->m2m_ctx);
++
++
++	dev_info(ctx->dev->dev, "%s vcodec [%d]\n", dev_name(dev->dev), ctx->id);
++
++	return ret;
++err_m2m_ctx_init:
++	v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
++err_ctrls_setup:
++	v4l2_fh_del(&ctx->fh);
++	v4l2_fh_exit(&ctx->fh);
++	kfree(ctx);
++	mutex_unlock(&dev->dev_mutex);
++	return ret;
++}
++
++static int fops_vcodec_release(struct file *file)
++{
++
++	struct ingenic_venc_dev *dev = video_drvdata(file);
++	struct ingenic_venc_ctx *ctx = fh_to_ctx(file->private_data);
++
++	dev_info(ctx->dev->dev, "[%d] encoder release\n", ctx->id);
++
++	mutex_lock(&dev->dev_mutex);
++
++	v4l2_fh_del(&ctx->fh);
++	v4l2_fh_exit(&ctx->fh);
++	v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
++	v4l2_m2m_ctx_release(ctx->m2m_ctx);
++	ingenic_vcodec_enc_deinit_default_params(ctx);
++
++	if (!(--dev->id_counter)) {
++		vpu_off(dev);
++	}
++
++	kfree(ctx);
++
++	mutex_unlock(&dev->dev_mutex);
++
++	return 0;
++}
++
++static unsigned int fops_vcodec_poll(struct file *file,
++				    struct poll_table_struct *wait)
++{
++	struct ingenic_venc_dev *dev = video_drvdata(file);
++	struct ingenic_venc_ctx *ctx = fh_to_ctx(file->private_data);
++	unsigned int ret = 0;
++
++	if(mutex_lock_interruptible(&dev->dev_mutex)) {
++		return -ERESTARTSYS;
++	}
++
++	ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
++
++	mutex_unlock(&dev->dev_mutex);
++
++	return ret;
++}
++
++static int fops_vcodec_mmap(struct file *file,
++			   struct vm_area_struct *vma)
++{
++	struct ingenic_venc_ctx *ctx = fh_to_ctx(file->private_data);
++
++	return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
++}
++
++static const struct v4l2_file_operations ingenic_venc_fops = {
++	.owner 		= THIS_MODULE,
++	.open		= fops_vcodec_open,
++	.release	= fops_vcodec_release,
++	.poll		= fops_vcodec_poll,
++	.unlocked_ioctl = video_ioctl2,
++	.mmap		= fops_vcodec_mmap,
++};
++
++
++#define vpu_readl(dev, offset)	\
++	readl(dev->reg_base + (offset))
++
++#define vpu_writel(dev, offset, data)	\
++	writel((data), dev->reg_base + (offset))
++
++static void inline vpu_clear_bits(struct ingenic_venc_dev *dev, unsigned int offset, unsigned int bits)
++{
++	unsigned int val = vpu_readl(dev, offset);
++	val &= ~bits;
++	vpu_writel(dev, offset, val);
++}
++
++
++static irqreturn_t ingenic_vpu_irq(int irq, void *priv)
++{
++	struct ingenic_venc_dev *dev = (struct ingenic_venc_dev *)priv;
++	struct ingenic_venc_ctx *ctx = dev->curr_ctx;
++	struct h264e_ctx *h264e_ctx = &ctx->h264e_ctx;
++	struct jpge_ctx *jpge_ctx = &ctx->jpge_ctx;
++
++	unsigned long flags;
++
++	unsigned int efe_stat;
++	unsigned int sch_stat;
++
++	spin_lock_irqsave(&dev->spinlock, flags);
++
++	ctx->int_cond = 1;
++
++	efe_stat = vpu_readl(dev, REG_EFE_STAT);
++	sch_stat = vpu_readl(dev, REG_SCH_STAT);
++
++	/* disable all interrupts. */
++	vpu_clear_bits(dev, REG_SCH_GLBC, 0x3f << 16);
++	if(sch_stat & SCH_STAT_ENDF){
++
++		if(sch_stat & SCH_STAT_JPGEND) {
++
++			jpge_ctx->bslen = vpu_readl(dev, REG_JPGC_STAT) & 0xffffff;
++
++			vpu_clear_bits(dev, REG_JPGC_STAT, JPGC_STAT_ENDF);
++		} else if(sch_stat & SCH_STAT_ENDF) {
++			h264e_ctx->r_bs_len = vpu_readl(dev, REG_SDE_CFG9);
++			h264e_ctx->r_rbsp_len = vpu_readl(dev, REG_SDE_CFG10);
++			h264e_ctx->encoded_bs_len = h264e_ctx->r_bs_len;
++
++			vpu_clear_bits(dev, REG_SDE_STAT, SDE_STAT_BSEND);
++			vpu_clear_bits(dev, REG_DBLK_GSTA, DBLK_STAT_DOEND);
++			/*wakeup ...*/
++		} else if(sch_stat & SCH_STAT_TIMEOUT){
++			dev_err(ctx->dev->dev, "Sch h264 Timeout !\n");
++		} else {
++			/*Error handling ...!*/
++
++			dev_err(ctx->dev->dev, "stat error %x\n", sch_stat);
++			/*wakeup ...*/
++		}
++
++	}
++	ctx->int_status = sch_stat;
++	spin_unlock_irqrestore(&dev->spinlock, flags);
++
++	wake_up_interruptible(&ctx->queue);
++
++
++	return IRQ_HANDLED;
++}
++
++
++static void vpu_dump_regs(struct ingenic_venc_dev *dev)
++{
++
++	/* EMC */
++	dev_info(dev->dev, "REG_EMC_FRM_SIZE :	%d\n", vpu_readl(dev, REG_EMC_FRM_SIZE));
++	dev_info(dev->dev, "REG_EMC_BS_ADDR :	0x%x\n", vpu_readl(dev, REG_EMC_BS_ADDR));
++	dev_info(dev->dev, "REG_EMC_DBLK_ADDR:	0x%x\n", vpu_readl(dev, REG_EMC_DBLK_ADDR));
++	dev_info(dev->dev, "REG_EMC_RECON_ADDR:	0x%x\n", vpu_readl(dev, REG_EMC_RECON_ADDR));
++	dev_info(dev->dev, "REG_EMC_MV_ADDR:	0x%x\n", vpu_readl(dev, REG_EMC_MV_ADDR));
++	dev_info(dev->dev, "REG_EMC_SE_ADDR:	0x%x\n", vpu_readl(dev, REG_EMC_SE_ADDR));
++	dev_info(dev->dev, "REG_EMC_QPT_ADDR:	0x%x\n", vpu_readl(dev, REG_EMC_QPT_ADDR));
++	dev_info(dev->dev, "REG_EMC_RC_RADDR:	0x%x\n", vpu_readl(dev, REG_EMC_RC_RADDR));
++	dev_info(dev->dev, "REG_EMC_MOS_ADDR:	0x%x\n", vpu_readl(dev, REG_EMC_MOS_ADDR));
++	dev_info(dev->dev, "REG_EMC_SLV_INIT:	0x%x\n", vpu_readl(dev, REG_EMC_SLV_INIT));
++	dev_info(dev->dev, "REG_EMC_BS_SIZE:	0x%x\n", vpu_readl(dev, REG_EMC_BS_SIZE));
++	dev_info(dev->dev, "REG_EMC_BS_STAT:	0x%x\n", vpu_readl(dev, REG_EMC_BS_STAT));
++}
++
++#define REG_VPU_STATUS ( *(volatile unsigned int*)0xb3200034 )
++#define REG_VPU_LOCK ( *(volatile unsigned int*)0xb329004c )
++#define REG_VPUCDR ( *(volatile unsigned int*)0xb0000030 )
++#define REG_CPM_VPU_SWRST ( *(volatile unsigned int*)0xb00000c4 )
++#define REG_VPU_TLBBASE (*(volatile unsigned int *)(0x30 + 0xb3200000))
++#define CPM_VPU_SR           (0x1<<31)
++#define CPM_VPU_STP          (0x1<<30)
++#define CPM_VPU_ACK          (0x1<<29)
++
++#if 0
++static int vpu_reset(struct ingenic_venc_dev *dev)
++{
++	int timeout = 0xffffff;
++
++	REG_CPM_VPU_SWRST |= CPM_VPU_STP;
++	while(!(REG_CPM_VPU_SWRST & CPM_VPU_ACK) && --timeout)
++		        ;
++
++	if(!timeout) {
++		printk("wait reset timeout!\n");
++	}
++
++	REG_CPM_VPU_SWRST = ((REG_CPM_VPU_SWRST | CPM_VPU_SR) & ~CPM_VPU_STP);
++	REG_CPM_VPU_SWRST = (REG_CPM_VPU_SWRST & ~CPM_VPU_SR & ~CPM_VPU_STP);
++	REG_VPU_LOCK = 0;
++
++	return 0;
++}
++#endif
++/*global clk on.*/
++static int vpu_on(struct ingenic_venc_dev *dev)
++{
++	clk_prepare_enable(dev->clk_gate);
++	__asm__ __volatile__ (
++			"mfc0  $2, $16,  7   \n\t"
++			"ori   $2, $2, 0x340 \n\t"
++			"andi  $2, $2, 0x3ff \n\t"
++			"mtc0  $2, $16,  7  \n\t"
++			"nop                  \n\t");
++
++	return 0;
++}
++
++static int vpu_off(struct ingenic_venc_dev *dev)
++{
++	clk_disable_unprepare(dev->clk_gate);
++
++	return 0;
++}
++
++#define VPU_RUN_TIMEOUT_MS	(3000)
++int ingenic_vpu_start(void *priv)
++{
++	struct ingenic_venc_ctx *ctx = (struct ingenic_venc_ctx *)priv;
++	struct ingenic_venc_dev *dev = ctx->dev;
++	struct h264e_ctx *h264e_ctx = &ctx->h264e_ctx;
++	struct jpge_ctx *jpge_ctx = &ctx->jpge_ctx;
++	struct jpgd_ctx *jpgd_ctx = &ctx->jpgd_ctx;
++	unsigned int sch_glbc = 0;
++	unsigned int des_pa;
++	unsigned long flags;
++	int timeout = 0xffff;
++	int ret = 0;
++
++	/* TODO: add lock.*/
++	dev->curr_ctx = ctx;
++
++	if(ctx->codec_id == CODEC_ID_H264E) {
++		des_pa = h264e_ctx->desc_pa;
++	} else if(ctx->codec_id == CODEC_ID_JPGE) {
++		des_pa = jpge_ctx->desc_pa;
++	} else if(ctx->codec_id == CODEC_ID_JPGD) {
++		des_pa = jpgd_ctx->desc_pa;
++	}
++
++	vpu_on(dev);
++
++	spin_lock_irqsave(&dev->spinlock, flags);
++	ctx->int_cond = 0;
++
++	/*X2000 RESET*/
++	/* vpu reset ... */
++	vpu_writel(dev, REG_CFGC_SW_RESET, CFGC_SW_RESET_RST);
++	while(!(vpu_readl(dev, REG_CFGC_SW_RESET) & CFGC_SW_RESET_EARB_EMPT) && --timeout);
++	if(!timeout) {
++		dev_err(ctx->dev->dev, "%s, vpu_reset timeout!\n", __func__);
++		spin_unlock_irqrestore(&dev->spinlock, flags);
++		return -EINVAL;
++	}
++
++	sch_glbc = SCH_GLBC_HIAXI | SCH_INTE_ACFGERR | SCH_INTE_BSERR |
++		SCH_INTE_ENDF | SCH_INTE_TLBERR | SCH_INTE_BSFULL;
++
++
++	/* type jpege, jpegd, h264e.*/
++	vpu_writel(dev, REG_SCH_GLBC, sch_glbc);
++
++	/*trigger start.*/
++	vpu_writel(dev, REG_CFGC_ACM_CTRL, VDMA_ACFG_DHA(des_pa) | VDMA_ACFG_RUN);
++
++	/* wait event time out ... */
++	spin_unlock_irqrestore(&dev->spinlock, flags);
++
++	ret = wait_event_interruptible_timeout(ctx->queue, ctx->int_cond, msecs_to_jiffies(VPU_RUN_TIMEOUT_MS));
++	if(!ret) {
++		dev_err(ctx->dev->dev, "wait vpu run timeout!\n");
++		dev_err(ctx->dev->dev, "efe_stat %x, sch_stat %x\n", vpu_readl(dev, REG_EFE_STAT), vpu_readl(dev, REG_SCH_STAT));
++
++		vpu_dump_regs(dev);
++		ret = -ETIMEDOUT;
++	} else if(ret == -ERESTARTSYS) {
++		dev_err(ctx->dev->dev, "vpu interrupted by a signal!\n");
++
++	}
++
++	vpu_off(dev);
++
++	return ret;
++}
++
++int ingenic_vpu_stop(struct ingenic_venc_dev *dev)
++{
++	return 0;
++}
++
++static int ingeic_vcodec_probe(struct platform_device *pdev)
++{
++	struct ingenic_venc_dev *dev;
++	struct video_device *vfd_enc;
++	int ret;
++
++	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
++	if(!dev)
++		return -ENOMEM;
++
++	ingenic_venc_dev_set(dev);
++
++	dev->dev = &pdev->dev;
++	dev->plat_dev = pdev;
++
++	/*io,clk,irq*/
++
++	dev->reg_base = of_iomap(pdev->dev.of_node, 0);;
++	if(IS_ERR(dev->reg_base)) {
++		ret = -ENODEV;
++		goto err_ioremap;
++	}
++	/*TODO: clk pm ...*/
++	dev->irq = platform_get_irq(pdev, 0);
++	ret = devm_request_irq(&pdev->dev, dev->irq, ingenic_vpu_irq, 0, pdev->name, dev);
++	if(ret ) {
++		dev_err(&pdev->dev, "Failed to request vpu irq!\n");
++		goto err_irq;
++	}
++
++	/*clk_gate, power*/
++	dev->clk_gate = clk_get(&pdev->dev, "power_helix");
++	if (IS_ERR(dev->clk_gate)) {
++		ret = PTR_ERR(dev->clk_gate);
++		goto err_get_clk_gate;
++	}
++
++#if 0
++	dev->clk = clk_get(dev->dev,"cgu_vpu");
++	if (IS_ERR(dev->clk)) {
++		ret = PTR_ERR(dev->clk);
++		goto err_get_clk_cgu;
++	}
++
++	clk_set_rate(dev->clk, 300000000);
++#endif
++
++
++
++	spin_lock_init(&dev->spinlock);
++	mutex_init(&dev->dev_mutex);
++
++	dev->alloc_ctx = ingenic_vb2_dma_contig_init_ctx(&pdev->dev);
++	if(IS_ERR(dev->alloc_ctx)) {
++		ret = -ENOMEM;
++		goto err_ctx;
++	}
++
++	snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name), "%s", "ingenic-v4l2-helix");
++
++	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
++	if(ret) {
++		dev_err(&pdev->dev, "Failed to register v4l2_dev\n");
++		goto err_v4l2;
++	}
++
++	vfd_enc = video_device_alloc();
++	if(!vfd_enc) {
++		dev_err(&pdev->dev, "Failed to alloc video device!\n");
++		ret = -ENOMEM;
++		goto err_vdev;
++	}
++
++
++	vfd_enc->fops 		= &ingenic_venc_fops;
++	vfd_enc->ioctl_ops 	= &ingenic_venc_ioctl_ops;
++	vfd_enc->release 	= video_device_release;
++	vfd_enc->lock 		= &dev->dev_mutex;
++	vfd_enc->v4l2_dev	= &dev->v4l2_dev;
++	vfd_enc->vfl_dir	= VFL_DIR_M2M;
++
++	snprintf(vfd_enc->name, sizeof(vfd_enc->name), "%s", INGENIC_VCODEC_ENC_NAME);
++
++	video_set_drvdata(vfd_enc, dev);
++	dev->vfd_enc = vfd_enc;
++	platform_set_drvdata(pdev, dev);
++
++	dev->m2m_dev_enc = v4l2_m2m_init(&ingenic_venc_m2m_ops);
++	if(IS_ERR((__force void *)dev->m2m_dev_enc)) {
++		dev_err(&pdev->dev, "Failed to init m2m device!\n");
++		ret = PTR_ERR((__force void *)dev->m2m_dev_enc);
++		goto err_m2m;
++	}
++
++	dev->encode_workqueue = alloc_ordered_workqueue(INGENIC_VCODEC_ENC_NAME,
++				WQ_MEM_RECLAIM | WQ_FREEZABLE);
++	if(!dev->encode_workqueue) {
++		dev_err(&pdev->dev, "Failed to create encode workqueue\n");
++		ret = -EINVAL;
++		goto err_workq;
++	}
++
++
++	vfd_enc->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE | V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
++	ret = video_register_device(vfd_enc, VFL_TYPE_VIDEO, INGENIC_HELIX_VIDEO_NR);
++	if(ret) {
++		dev_err(&pdev->dev, "Failed to register video device!\n");
++		goto err_video_reg;
++	}
++
++	ret = of_reserved_mem_device_init(dev->dev);
++	if(ret)
++		dev_warn(&pdev->dev, "failed to init reserved mem\n");
++
++	h264e_netlink_test();
++
++	dev_info(&pdev->dev, "encoder(helix) registered as /dev/video%d\n",
++	 		vfd_enc->num);
++
++	return 0;
++err_reserved_mem_init:
++err_video_reg:
++err_workq:
++err_m2m:
++err_vdev:
++err_v4l2:
++err_ctx:
++err_get_clk_cgu:
++err_get_clk_gate:
++err_irq:
++err_ioremap:
++	return ret;
++}
++
++static int ingeic_vcodec_remove(struct platform_device *pdev)
++{
++
++	return 0;
++}
++
++static const struct of_device_id helix_of_match[] = {
++	{ .compatible = "ingenic,x2000-helix"},
++	{ .compatible = "ingenic,m300-helix"},
++	{},
++};
++
++static struct platform_driver ingenic_vcodec_driver = {
++	.probe = ingeic_vcodec_probe,
++	.remove = ingeic_vcodec_remove,
++	.driver = {
++		.name = INGENIC_VCODEC_ENC_NAME,
++		.of_match_table = helix_of_match,
++	},
++};
++
++static int __init helix_driver_init(void)
++{
++	return platform_driver_register(&ingenic_vcodec_driver);
++}
++
++static void __exit helix_driver_exit(void)
++{
++	platform_driver_unregister(&ingenic_vcodec_driver);
++}
++module_init(helix_driver_init);
++module_exit(helix_driver_exit);
++
++
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Ingenic Video Codec v4l2 encoder driver.");
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/helix_drv.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/helix_drv.h
+new file mode 100644
+index 000000000..22aacb139
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/helix_drv.h
+@@ -0,0 +1,177 @@
++#ifndef __INGENIC_HELIX_DRV_H__
++#define __INGENIC_HELIX_DRV_H__
++
++#include <linux/platform_device.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ioctl.h>
++#include <media/videobuf2-core.h>
++
++//#include "api/helix_x264_enc.h"
++//#include "api/helix_jpeg_enc.h"
++#include "api/helix.h"
++#include "helix_buf.h"
++
++#include "h264e_rc.h"
++#include "jpge.h"
++#include "jpgd.h"
++
++
++#define INGENIC_VCODEC_ENC_NAME	"helix-venc"
++#define INGENIC_VCODEC_MAX_PLANES	3
++
++
++enum ingenic_fmt_type {
++	INGENIC_FMT_FRAME 	= 0,
++	INGENIC_FMT_ENC 	= 1,
++	INGENIC_FMT_DEC 	= 2,
++};
++
++struct ingenic_video_fmt {
++	u32 fourcc;
++	enum ingenic_fmt_type type;
++	u32 num_planes;
++	enum helix_raw_format format;
++};
++
++struct ingenic_codec_framesizes {
++	u32 fourcc;
++	struct v4l2_frmsize_stepwise stepwise;
++};
++
++struct ingenic_video_buf {
++	struct vb2_v4l2_buffer vb;
++	struct list_head list;
++
++	struct video_frame_buffer buf;
++};
++
++
++enum ingenic_q_type {
++	INGENIC_Q_DATA_SRC = 0,
++	INGENIC_Q_DATA_DST = 1,
++};
++
++/* Queue Data. */
++struct ingenic_venc_q_data {
++	unsigned int    visible_width;
++	unsigned int    visible_height;
++	unsigned int    coded_width;
++	unsigned int    coded_height;
++	enum v4l2_field field;
++	unsigned int    bytesperline[INGENIC_VCODEC_MAX_PLANES];
++	unsigned int    sizeimage[INGENIC_VCODEC_MAX_PLANES];
++	struct ingenic_video_fmt    *fmt;
++
++
++};
++
++/*
++  when ctx is created, IDLE
++  when start_streaming, START,
++  when abort, ABORT,
++*/
++
++enum ingenic_venc_state {
++	INGENIC_STATE_IDLE = 0,
++	INGENIC_STATE_HEADER,
++	INGENIC_STATE_RUNNING,
++	INGENIC_STATE_ABORT,
++};
++
++/* v4l2 set parm to sw_parm, */
++/* sw_parm api to sliceinfo. */
++/* Sliceinfo to dma desc. */
++
++/* helix_ctrl_if_start. */
++
++struct ingenic_venc_ctx {
++	struct ingenic_venc_dev *dev;
++
++	struct v4l2_fh fh;
++	struct v4l2_m2m_ctx *m2m_ctx;
++
++
++	struct v4l2_ctrl_handler ctrl_hdl;
++
++	int id;
++
++	int capture_stopped;
++	int output_stopped;
++
++	struct ingenic_venc_q_data q_data[2];
++	enum ingenic_venc_state state;
++
++	wait_queue_head_t queue;
++
++	int int_cond;
++	int int_status;
++
++	struct work_struct encode_work;
++	enum v4l2_colorspace colorspace;
++	//enum v4l2_ycbcr_encoding ycbcr_enc;
++	//enum v4l2_quantization quantization;
++	//enum v4l2_xfer_func xfer_func;
++
++	int codec_id;
++#define CODEC_ID_H264E	1
++#define CODEC_ID_JPGE	2
++#define CODEC_ID_JPGD	3
++	union {
++		struct h264e_ctx h264e_ctx;
++		struct jpge_ctx jpge_ctx;
++		struct jpgd_ctx jpgd_ctx;
++	};
++
++};
++
++
++struct ingenic_venc_dev {
++
++	struct v4l2_device v4l2_dev;
++	struct video_device *vfd_enc;
++	struct device *dev;
++
++	struct v4l2_m2m_dev *m2m_dev_enc;
++	struct platform_device *plat_dev;
++
++	struct mutex dev_mutex;
++	struct workqueue_struct *encode_workqueue;
++
++	spinlock_t spinlock;
++
++	struct ingenic_venc_ctx *curr_ctx;
++	struct vb2_dc_conf *alloc_ctx;
++
++	int id_counter;
++
++	void __iomem *reg_base;
++	int irq;
++	struct clk *clk_gate;
++	struct clk *clk;
++};
++
++
++static inline struct ingenic_venc_ctx *fh_to_ctx(struct v4l2_fh *fh)
++{
++	return container_of(fh, struct ingenic_venc_ctx, fh);
++}
++
++static inline struct ingenic_venc_ctx *ctrl_to_ctx(struct v4l2_ctrl *ctrl)
++{
++	return container_of(ctrl->handler, struct ingenic_venc_ctx, ctrl_hdl);
++}
++
++/* 内核全局g_dev.*/
++extern struct ingenic_venc_dev *g_dev;
++static inline void ingenic_venc_dev_set(struct ingenic_venc_dev *dev)
++{
++	g_dev = dev;
++}
++static inline struct ingenic_venc_dev *ingenic_venc_dev_get(void)
++{
++	return g_dev;
++}
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/helix_ops.c b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/helix_ops.c
+new file mode 100644
+index 000000000..4b26f5b65
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/helix_ops.c
+@@ -0,0 +1,1354 @@
++/*
++* Copyright© 2014 Ingenic Semiconductor Co.,Ltd
++*
++* Author: qipengzhen <aric.pzqi@ingenic.com>
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License version 2 as
++* published by the Free Software Foundation.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++* GNU General Public License for more details.
++*
++*/
++
++#include <media/v4l2-event.h>
++#include <media/v4l2-mem2mem.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++
++#include <linux/slab.h>
++#include <linux/crc32.h>
++
++#include "helix_drv.h"
++#include "helix_ops.h"
++
++#include "api/helix.h"
++
++#include "h264e_rc.h"
++#include "jpge.h"
++#include "jpgd.h"
++
++
++#define fh_to_ctx(__fh) container_of(__fh, struct ingenic_venc_ctx, fh)
++#define NUM_SUPPORTED_FRAMESIZE		3
++
++#define INGENIC_VENC_MIN_W	160U
++#define INGENIC_VENC_MIN_H	120U
++#define INGENIC_VENC_MAX_W	2560U
++#define INGENIC_VENC_MAX_H	2048U
++
++#define MAX_SUPPORT_FRAME_BUFFERS 3
++
++
++
++#define pixelformat_str(a) a >> 0, a >> 8, a >> 16, a >> 24
++
++
++static struct ingenic_video_fmt ingenic_video_formats[] = {
++	/* output */
++	{
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.type	= INGENIC_FMT_FRAME,
++		.num_planes = 2,
++		.format = HELIX_NV12_MODE,
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_NV21,
++		.type = INGENIC_FMT_FRAME,
++		.num_planes = 2,
++		.format = HELIX_NV21_MODE,
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_YUV420,
++		.type = INGENIC_FMT_FRAME,
++		.num_planes = 3,
++		.format = HELIX_420P_MODE,
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_JPEG,
++		.type = INGENIC_FMT_DEC,
++		.num_planes = 1,
++	},
++	/*capture*/
++	/* video encoder idx */
++	{
++		.fourcc = V4L2_PIX_FMT_H264,
++		.type = INGENIC_FMT_ENC,
++		.num_planes = 1,
++	},
++	{
++		.fourcc = V4L2_PIX_FMT_JPEG,
++		.type = INGENIC_FMT_ENC,
++		.num_planes = 1,
++	},
++	{	/* jpeg decoder */
++		.fourcc = V4L2_PIX_FMT_NV12,
++		.type	= INGENIC_FMT_FRAME,
++		.num_planes = 2,
++		.format = HELIX_NV12_MODE,
++	},
++
++};
++
++#define NUM_FORMATS	ARRAY_SIZE(ingenic_video_formats)
++#define OUT_FMT_IDX	0
++#define CAP_FMT_IDX 	(ARRAY_SIZE(ingenic_video_formats) - 4)
++
++static const struct ingenic_codec_framesizes ingenic_venc_framesizes[] = {
++	{
++		.fourcc = V4L2_PIX_FMT_H264,
++		.stepwise = { INGENIC_VENC_MIN_W, INGENIC_VENC_MAX_W, 16,
++			      INGENIC_VENC_MIN_H, INGENIC_VENC_MAX_H, 16},
++	},
++};
++
++static struct ingenic_venc_q_data *ingenic_venc_get_q_data(struct ingenic_venc_ctx *ctx,
++							enum v4l2_buf_type type);
++
++
++static int vidioc_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct ingenic_venc_ctx *ctx = ctrl_to_ctx(ctrl);
++	struct h264e_ctx *h264e_ctx = &ctx->h264e_ctx;
++	struct h264e_params *h264_p = &h264e_ctx->p;
++	struct jpge_ctx *jpge_ctx = &ctx->jpge_ctx;
++	struct jpge_params *jpge_p = &jpge_ctx->p;
++	int ret = 0;
++
++	switch(ctrl->id) {
++	case V4L2_CID_MPEG_VIDEO_BITRATE:
++		dev_dbg(ctx->dev->dev, "V4L2_CID_MPEG_VIDEO_BITRATE val = %d\n", ctrl->val);
++		h264_p->bitrate = ctrl->val;
++		break;
++#if 0
++	case V4L2_CID_MPEG_VIDEO_B_FRAMES:
++		dev_dbg(ctx->dev->dev, "V4L2_CID_MPEG_VIDEO_B_FRAMES val = %d\n", ctrl->val);
++		break;
++#endif
++	case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
++		dev_dbg(ctx->dev->dev, "V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP val = %d\n", ctrl->val);
++		h264_p->i_qp = ctrl->val;
++		break;
++	case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
++		dev_dbg(ctx->dev->dev, "V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP val = %d\n", ctrl->val);
++		h264_p->p_qp = ctrl->val;
++		break;
++	case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE:
++		dev_dbg(ctx->dev->dev, "V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE val = %d\n", ctrl->val);
++		h264_p->frame_rc_enable = ctrl->val;
++		break;
++	case V4L2_CID_MPEG_VIDEO_H264_MIN_QP:
++		dev_dbg(ctx->dev->dev, "V4L2_CID_MPEG_VIDEO_H264_MIN_QP val = %d\n", ctrl->val);
++		h264_p->h264_min_qp = ctrl->val;
++		break;
++	case V4L2_CID_MPEG_VIDEO_H264_MAX_QP:
++		dev_dbg(ctx->dev->dev, "V4L2_CID_MPEG_VIDEO_H264_MAX_QP val = %d\n", ctrl->val);
++		h264_p->h264_max_qp = ctrl->val;
++		break;
++	case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
++		dev_dbg(ctx->dev->dev, "V4L2_CID_MPEG_VIDEO_HEADER_MODE val = %d\n", ctrl->val);
++		h264_p->h264_hdr_mode = ctrl->val;
++		break;
++	case V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE:
++		dev_dbg(ctx->dev->dev, "V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE val = %d\n", ctrl->val);
++		h264_p->mb_rc_enable = ctrl->val;
++		break;
++	case V4L2_CID_MPEG_VIDEO_H264_PROFILE:
++		dev_dbg(ctx->dev->dev, "V4L2_CID_MPEG_VIDEO_H264_PROFILE val = %d\n", ctrl->val);
++		h264_p->h264_profile = ctrl->val;
++		break;
++	case V4L2_CID_MPEG_VIDEO_H264_LEVEL:
++		dev_dbg(ctx->dev->dev, "V4L2_CID_MPEG_VIDEO_H264_LEVEL val = %d\n", ctrl->val);
++		h264_p->h264_level = ctrl->val;
++		break;
++	case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:
++		dev_dbg(ctx->dev->dev, "V4L2_CID_MPEG_VIDEO_BITRATE_MODE val = %d\n", ctrl->val);
++		h264_p->rc_mode = ctrl->val;
++		break;
++	case V4L2_CID_MPEG_VIDEO_H264_I_PERIOD:
++		dev_dbg(ctx->dev->dev, "V4L2_CID_MPEG_VIDEO_H264_I_PERIOD val = %d\n", ctrl->val);
++		break;
++
++	case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
++		dev_dbg(ctx->dev->dev, "V4L2_CID_MPEG_VIDEO_GOP_SIZE val = %d\n", ctrl->val);
++		h264_p->gop_size = ctrl->val;
++		break;
++
++	case V4L2_CID_JPEG_COMPRESSION_QUALITY:
++		dev_info(ctx->dev->dev, "V4L2_CID_JPEG_COMPRESSION_QUALITY = %d\n", ctrl->val);
++		jpge_p->compr_quality = ctrl->val;
++		break;
++
++	default:
++		ret = -EINVAL;
++		break;
++	}
++
++	return ret;
++
++}
++
++static const struct v4l2_ctrl_ops ingenic_venc_ctrl_ops = {
++	.s_ctrl = vidioc_s_ctrl,
++};
++
++static int vidioc_enum_fmt(struct v4l2_fmtdesc *f, bool output_queue)
++{
++	struct ingenic_video_fmt *fmt;
++	int i,j = 0;
++
++	int start_index = output_queue ? OUT_FMT_IDX : CAP_FMT_IDX;
++
++	for(i = start_index; i < NUM_FORMATS; i++) {
++
++		if(j == f->index) {
++			fmt = &ingenic_video_formats[i];
++			f->pixelformat = fmt->fourcc;
++			memset(f->reserved, 0, sizeof(f->reserved));
++			return 0;
++		}
++
++		j++;
++	}
++
++	return -EINVAL;
++}
++
++
++static int vidioc_enum_framesizes(struct file *file, void *fh,
++				struct v4l2_frmsizeenum *fsize)
++{
++	int i = 0;
++	if(fsize->index != 0)
++		return -EINVAL;
++
++	for(i = 0; i < NUM_SUPPORTED_FRAMESIZE; i++) {
++		if(fsize->pixel_format != ingenic_venc_framesizes[i].fourcc)
++			continue;
++
++		fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
++		fsize->stepwise = ingenic_venc_framesizes[i].stepwise;
++		return 0;
++	}
++
++	return -EINVAL;
++}
++
++static int vidioc_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
++					struct v4l2_fmtdesc *f)
++{
++	return vidioc_enum_fmt(f, false);
++}
++static int vidioc_enum_fmt_vid_out_mplane(struct file *file, void *priv,
++					struct v4l2_fmtdesc *f)
++{
++	return vidioc_enum_fmt(f, true);
++}
++
++static int vidioc_querycap(struct file *file, void *priv,
++			struct v4l2_capability *cap)
++{
++	strlcpy(cap->driver, INGENIC_VCODEC_ENC_NAME, sizeof(cap->driver));
++	strlcpy(cap->bus_info, "vpu-helix", sizeof(cap->bus_info));
++	strlcpy(cap->card, "vpu-helix", sizeof(cap->card));
++
++	cap->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING |
++                    V4L2_CAP_VIDEO_CAPTURE_MPLANE |
++                    V4L2_CAP_VIDEO_OUTPUT_MPLANE;
++	cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
++
++	return 0;
++}
++
++
++static int vidioc_s_parm(struct file *file, void *priv,
++			struct v4l2_streamparm *a)
++{
++	if(a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
++		return -EINVAL;
++
++	return 0;
++}
++
++static ssize_t
++h264e_encoded_headers(struct ingenic_venc_ctx *ctx)
++{
++	struct h264e_ctx *h264e_ctx = &ctx->h264e_ctx;
++	struct ingenic_venc_q_data *q_data_src;
++	struct ingenic_venc_q_data *q_data_dst;
++	int ret = 0;
++
++	q_data_src = ingenic_venc_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
++	q_data_dst = ingenic_venc_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
++
++	ret = h264e_set_fmt(h264e_ctx, q_data_src->coded_width,
++			q_data_src->coded_height, q_data_src->fmt->format);
++	if(ret < 0) {
++		return ret;
++	}
++
++	ret = h264e_generate_headers(h264e_ctx, 0);
++	if(ret < 0)
++		return ret;
++
++	return h264e_ctx->bs_header_size;
++}
++
++struct h264_header {
++	unsigned int size;
++	unsigned char header;
++};
++
++static int vidioc_g_parm(struct file *file, void *priv,
++			struct v4l2_streamparm *a)
++{
++	struct ingenic_venc_ctx *ctx = fh_to_ctx(priv);
++	struct vb2_queue *vq;
++	struct ingenic_venc_q_data *q_data;
++	struct ingenic_video_fmt *fmt;
++	struct h264e_ctx *h264e_ctx = &ctx->h264e_ctx;
++	struct h264_header *h = (struct h264_header *)a->parm.raw_data;
++	unsigned int *size = 0;
++
++	if(ctx->codec_id == CODEC_ID_H264E) {
++		h264e_encoded_headers(ctx);
++
++		h->size = h264e_ctx->bs_header_size;
++		memcpy(&h->header, h264e_ctx->bs_header, h264e_ctx->bs_header_size);
++	}
++	return 0;
++}
++
++static struct ingenic_venc_q_data *ingenic_venc_get_q_data(struct ingenic_venc_ctx *ctx,
++							enum v4l2_buf_type type)
++{
++	if(V4L2_TYPE_IS_OUTPUT(type))
++		return &ctx->q_data[INGENIC_Q_DATA_SRC];
++
++	return &ctx->q_data[INGENIC_Q_DATA_DST];
++}
++
++static struct ingenic_video_fmt *ingenic_venc_find_format(struct v4l2_format *f, int isout)
++{
++	struct ingenic_video_fmt *fmt;
++	int i;
++	int start_index = isout ? OUT_FMT_IDX : CAP_FMT_IDX;
++
++	for(i = start_index; i < NUM_FORMATS; i++) {
++		fmt = &ingenic_video_formats[i];
++		if(fmt->fourcc == f->fmt.pix_mp.pixelformat)
++			return fmt;
++	}
++
++	return NULL;
++}
++
++static int vidioc_try_fmt(struct v4l2_format *f, struct ingenic_video_fmt *fmt)
++{
++	struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
++	int i;
++
++	pix_fmt_mp->field = V4L2_FIELD_NONE;
++
++	if(fmt->type == INGENIC_FMT_FRAME) {
++		int tmp_w, tmp_h;
++
++		pix_fmt_mp->height = clamp(pix_fmt_mp->height,
++				INGENIC_VENC_MIN_H,
++				INGENIC_VENC_MAX_H);
++		pix_fmt_mp->width = clamp(pix_fmt_mp->width,
++				INGENIC_VENC_MIN_W,
++				INGENIC_VENC_MAX_W);
++
++#if 1
++		tmp_w = ALIGN(pix_fmt_mp->width, 16);
++		tmp_h = pix_fmt_mp->height;
++		/*tmp_h = ALIGN(pix_fmt_mp->height, 16);*/
++		pr_info("tmp_w %d tmp_h %d, w %d h %d\n",
++				tmp_w, tmp_h,
++				pix_fmt_mp->width,
++				pix_fmt_mp->height);
++#else
++		tmp_w = pix_fmt_mp->width;
++		tmp_h = pix_fmt_mp->height;
++#endif
++		pix_fmt_mp->num_planes = fmt->num_planes;
++		pix_fmt_mp->plane_fmt[0].sizeimage =
++				tmp_w * tmp_h;
++
++		pix_fmt_mp->plane_fmt[0].bytesperline = tmp_w;
++
++		if(pix_fmt_mp->num_planes == 2) {
++			pix_fmt_mp->plane_fmt[1].sizeimage =
++				tmp_w * tmp_h / 2;
++			pix_fmt_mp->plane_fmt[2].sizeimage = 0;
++
++			pix_fmt_mp->plane_fmt[1].bytesperline = tmp_w;
++			pix_fmt_mp->plane_fmt[2].bytesperline = 0;
++		} else if(pix_fmt_mp->num_planes == 3) {
++			pix_fmt_mp->plane_fmt[1].sizeimage =
++				pix_fmt_mp->plane_fmt[2].sizeimage =
++				(tmp_w * tmp_h) / 4;
++
++			pix_fmt_mp->plane_fmt[1].bytesperline =
++				pix_fmt_mp->plane_fmt[2].bytesperline =
++				tmp_w / 2;
++		}
++
++	} else {
++		pix_fmt_mp->num_planes = 1;
++		pix_fmt_mp->plane_fmt[0].bytesperline = 0;
++
++		/*restrict output bs buffer size, max width * height.
++		  sizeimage can be set by userspace.
++		*/
++		if(pix_fmt_mp->plane_fmt[0].sizeimage) {
++			pix_fmt_mp->plane_fmt[0].sizeimage = min(pix_fmt_mp->plane_fmt[0].sizeimage , pix_fmt_mp->width * pix_fmt_mp->height * 3 / 4);
++		} else {
++			pix_fmt_mp->plane_fmt[0].sizeimage = pix_fmt_mp->width * pix_fmt_mp->height * 3 / 4;
++		}
++	}
++
++	for(i = 0; i < pix_fmt_mp->num_planes; i++) {
++		memset(&(pix_fmt_mp->plane_fmt[i].reserved[0]), 0x0,
++				sizeof(pix_fmt_mp->plane_fmt[0].reserved));
++	}
++
++//	pix_fmt_mp->flags = 0;
++
++	memset(&pix_fmt_mp->reserved, 0x0,
++			sizeof(pix_fmt_mp->reserved));
++
++	return 0;
++}
++
++static int vidioc_s_fmt_cap(struct file *file, void *priv,
++			struct v4l2_format *f)
++{
++
++	struct ingenic_venc_ctx *ctx = fh_to_ctx(priv);
++	struct vb2_queue *vq;
++	struct ingenic_venc_q_data *q_data;
++	struct ingenic_video_fmt *fmt;
++	struct h264e_ctx *h264e_ctx = &ctx->h264e_ctx;
++	struct jpge_ctx *jpge_ctx = &ctx->jpge_ctx;
++	int i, ret;
++
++	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
++	if(!vq) {
++		dev_err(ctx->dev->dev, "failed to get cap vq !\n");
++		return -EINVAL;
++	}
++
++	if(vb2_is_busy(vq)) {
++		dev_err(ctx->dev->dev, "cap vq is busy!\n");
++		return -EINVAL;
++	}
++
++	q_data = ingenic_venc_get_q_data(ctx, f->type);
++	if(!q_data) {
++		dev_err(ctx->dev->dev, "fail to get cap q data!\n");
++		return -EINVAL;
++	}
++
++
++	fmt = ingenic_venc_find_format(f, 0);
++	if(!fmt) {
++		/* change to the first support cap format.*/
++		f->fmt.pix.pixelformat = ingenic_video_formats[CAP_FMT_IDX].fourcc;
++		/* if buf type MPLANE, use pix_mp ..*/
++		f->fmt.pix_mp.pixelformat = ingenic_video_formats[CAP_FMT_IDX].fourcc;
++		fmt = ingenic_venc_find_format(f, 0);
++	}
++
++
++	q_data->fmt = fmt;
++
++	ret = vidioc_try_fmt(f, q_data->fmt);
++	if(ret)
++		return ret;
++
++	q_data->coded_width = f->fmt.pix_mp.width;
++	q_data->coded_height = f->fmt.pix_mp.height;
++	q_data->field = f->fmt.pix_mp.field;
++
++	for(i = 0; i < f->fmt.pix_mp.num_planes; i++) {
++		struct v4l2_plane_pix_format *plane_fmt;
++
++		plane_fmt = &f->fmt.pix_mp.plane_fmt[i];
++		q_data->bytesperline[i] = plane_fmt->bytesperline;
++		q_data->sizeimage[i] = plane_fmt->sizeimage;
++	}
++
++	/* init hw interface. */
++	if(f->fmt.pix_mp.pixelformat == V4L2_PIX_FMT_H264) {
++		ctx->codec_id = CODEC_ID_H264E;
++
++		h264e_set_priv(h264e_ctx, ctx);
++		ret = h264e_encoder_init(h264e_ctx);
++
++	} else if(f->fmt.pix_mp.pixelformat == V4L2_PIX_FMT_JPEG) {
++		ctx->codec_id = CODEC_ID_JPGE;
++
++		jpeg_encoder_set_priv(jpge_ctx, ctx);
++		ret = jpeg_encoder_init(jpge_ctx);
++
++	}
++
++	return ret;
++}
++
++
++static int vidioc_s_fmt_out(struct file *file, void *priv,
++			struct v4l2_format *f)
++{
++	struct ingenic_venc_ctx *ctx = fh_to_ctx(priv);
++	struct vb2_queue *vq;
++	struct ingenic_venc_q_data *q_data;
++	struct ingenic_video_fmt *fmt;
++	struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp;
++	struct jpgd_ctx *jpgd_ctx = &ctx->jpgd_ctx;
++	int ret, i;
++
++	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
++	if(!vq) {
++		dev_err(ctx->dev->dev, "fail to get out vq!\n");
++		return -EINVAL;
++	}
++	if(vb2_is_busy(vq)) {
++		dev_err(ctx->dev->dev, "out vq is busy!\n");
++		return -EINVAL;
++	}
++
++	q_data = ingenic_venc_get_q_data(ctx, f->type);
++	if(!q_data) {
++		dev_err(ctx->dev->dev, "failed to get out q_data!\n");
++		return -EINVAL;
++	}
++
++
++	dev_dbg(ctx->dev->dev, "s_fmt_out f->fmt %x, %c%c%c%c \n", f->fmt.pix_mp.pixelformat, pixelformat_str(f->fmt.pix_mp.pixelformat));
++	fmt = ingenic_venc_find_format(f, 1);
++	if(!fmt) {
++		/* change to the first support cap format.*/
++		f->fmt.pix.pixelformat = ingenic_video_formats[OUT_FMT_IDX].fourcc;
++		f->fmt.pix_mp.pixelformat = ingenic_video_formats[OUT_FMT_IDX].fourcc;
++		fmt = ingenic_venc_find_format(f, 1);
++	}
++
++
++	pix_fmt_mp->height = clamp(pix_fmt_mp->height,
++			INGENIC_VENC_MIN_H,
++			INGENIC_VENC_MAX_H);
++	pix_fmt_mp->width = clamp(pix_fmt_mp->width,
++			INGENIC_VENC_MIN_W,
++			INGENIC_VENC_MAX_W);
++
++	q_data->visible_width = f->fmt.pix_mp.width;
++	q_data->visible_height = f->fmt.pix_mp.height;
++	q_data->fmt = fmt;
++	ret = vidioc_try_fmt(f, q_data->fmt);
++	if (ret)
++		return ret;
++
++	q_data->coded_width = f->fmt.pix_mp.width;
++	q_data->coded_height = f->fmt.pix_mp.height;
++
++	dev_dbg(ctx->dev->dev, "s_fmt_out q_data->coded_width: %d, q_data->coded_height: %d\n",
++			q_data->coded_width, q_data->coded_height);
++
++	q_data->field = f->fmt.pix_mp.field;
++	ctx->colorspace = f->fmt.pix_mp.colorspace;
++	//ctx->ycbcr_enc = f->fmt.pix_mp.ycbcr_enc;
++	//ctx->quantization = f->fmt.pix_mp.quantization;
++	//ctx->xfer_func = f->fmt.pix_mp.xfer_func;
++
++
++	for (i = 0; i < f->fmt.pix_mp.num_planes; i++) {
++		struct v4l2_plane_pix_format *plane_fmt;
++
++		plane_fmt = &f->fmt.pix_mp.plane_fmt[i];
++		q_data->bytesperline[i] = plane_fmt->bytesperline;
++		q_data->sizeimage[i] = plane_fmt->sizeimage;
++	}
++
++	if(f->fmt.pix_mp.pixelformat == V4L2_PIX_FMT_JPEG) {
++		ctx->codec_id = CODEC_ID_JPGD;
++
++		jpeg_decoder_set_priv(jpgd_ctx, ctx);
++		jpeg_decoder_init(jpgd_ctx);
++	}
++
++
++	return 0;
++}
++
++static int vidioc_g_fmt(struct file *file, void *priv,
++			struct v4l2_format *f)
++{
++
++	struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
++	struct ingenic_venc_ctx *ctx = fh_to_ctx(priv);
++	struct vb2_queue *vq;
++	struct ingenic_venc_q_data *q_data;
++	int i;
++
++	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
++	if (!vq)
++		return -EINVAL;
++
++	q_data = ingenic_venc_get_q_data(ctx, f->type);
++
++	pix->width = q_data->coded_width;
++	pix->height = q_data->coded_height;
++	pix->pixelformat = q_data->fmt->fourcc;
++	pix->field = q_data->field;
++	pix->num_planes = q_data->fmt->num_planes;
++	for (i = 0; i < pix->num_planes; i++) {
++		pix->plane_fmt[i].bytesperline = q_data->bytesperline[i];
++		pix->plane_fmt[i].sizeimage = q_data->sizeimage[i];
++		memset(&(pix->plane_fmt[i].reserved[0]), 0x0,
++				sizeof(pix->plane_fmt[i].reserved));
++	}
++
++//	pix->flags = 0;
++	pix->colorspace = ctx->colorspace;
++//	pix->ycbcr_enc = ctx->ycbcr_enc;
++//	pix->quantization = ctx->quantization;
++//	pix->xfer_func = ctx->xfer_func;
++
++
++	dev_dbg(ctx->dev->dev, "g_fmt f->type %d\n", f->type);
++	dev_dbg(ctx->dev->dev, "pixel_format = %x, %c%c%c%c\n", pix->pixelformat, pixelformat_str(pix->pixelformat));
++	dev_dbg(ctx->dev->dev, "pix->num_planes %d\n", pix->num_planes);
++
++	return 0;
++}
++
++
++static int vidioc_try_fmt_vid_cap_mplane(struct file *file, void *priv,
++			struct v4l2_format *f)
++{
++	struct ingenic_video_fmt *fmt;
++	struct ingenic_venc_ctx *ctx = fh_to_ctx(priv);
++
++	fmt = ingenic_venc_find_format(f, 0);
++	if (!fmt) {
++		f->fmt.pix.pixelformat = ingenic_video_formats[CAP_FMT_IDX].fourcc;
++		f->fmt.pix_mp.pixelformat = ingenic_video_formats[CAP_FMT_IDX].fourcc;
++		fmt = ingenic_venc_find_format(f, 0);
++	}
++	f->fmt.pix_mp.colorspace = ctx->colorspace;
++	//f->fmt.pix_mp.ycbcr_enc = ctx->ycbcr_enc;
++	//f->fmt.pix_mp.quantization = ctx->quantization;
++	//f->fmt.pix_mp.xfer_func = ctx->xfer_func;
++
++	return vidioc_try_fmt(f, fmt);
++}
++
++static int vidioc_try_fmt_vid_out_mplane(struct file *file, void *priv,
++			struct v4l2_format *f)
++{
++
++	struct ingenic_video_fmt *fmt;
++
++	fmt = ingenic_venc_find_format(f, 1);
++	if (!fmt) {
++		f->fmt.pix.pixelformat = ingenic_video_formats[OUT_FMT_IDX].fourcc;
++		f->fmt.pix_mp.pixelformat = ingenic_video_formats[OUT_FMT_IDX].fourcc;
++		fmt = ingenic_venc_find_format(f, 1);
++	}
++	if (!f->fmt.pix_mp.colorspace) {
++		f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_REC709;
++	//	f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
++	//	f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT;
++	//	f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT;
++	}
++
++	return vidioc_try_fmt(f, fmt);
++}
++
++static int vidioc_g_selection(struct file *file, void *priv,
++			struct v4l2_selection *s)
++{
++	// TODO
++
++	return 0;
++}
++
++static int vidioc_s_selection(struct file *file, void *priv,
++			struct v4l2_selection *s)
++{
++	//TODO
++	return 0;
++}
++
++
++static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
++{
++	struct ingenic_venc_ctx *ctx = fh_to_ctx(priv);
++
++	if(ctx->state == INGENIC_STATE_ABORT) {
++		return -EIO;
++	}
++
++	return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
++}
++
++static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
++{
++	struct ingenic_venc_ctx *ctx = fh_to_ctx(priv);
++	return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
++}
++
++static int vidioc_streamon(struct file *file, void *priv,
++			enum v4l2_buf_type type)
++{
++	struct ingenic_venc_ctx *ctx = fh_to_ctx(priv);
++
++	return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
++}
++
++static int vidioc_streamoff(struct file *file, void *priv,
++			enum v4l2_buf_type type)
++{
++	struct ingenic_venc_ctx *ctx = fh_to_ctx(priv);
++
++	return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
++}
++
++static int vidioc_reqbufs(struct file *file, void *priv,
++			struct v4l2_requestbuffers *reqbufs)
++{
++	struct ingenic_venc_ctx *ctx = fh_to_ctx(priv);
++
++	return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
++
++}
++
++static int vidioc_querybuf(struct file *file, void *priv,
++			struct v4l2_buffer *buf)
++{
++	struct ingenic_venc_ctx *ctx = fh_to_ctx(priv);
++
++	return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
++
++}
++
++static int vidioc_expbuf(struct file *file, void *priv,
++	struct v4l2_exportbuffer *eb)
++{
++
++	struct ingenic_venc_ctx *ctx = fh_to_ctx(priv);
++
++	return v4l2_m2m_expbuf(file, ctx->m2m_ctx, eb);
++}
++
++static int vidioc_create_bufs(struct file *file, void *priv,
++			      struct v4l2_create_buffers *create)
++{
++	struct ingenic_venc_ctx *ctx = fh_to_ctx(priv);
++
++	return v4l2_m2m_create_bufs(file, ctx->m2m_ctx, create);
++}
++static int vidioc_prepare_buf(struct file *file, void *fh, struct v4l2_buffer *b)
++{
++	return 0;
++}
++
++const struct v4l2_ioctl_ops ingenic_venc_ioctl_ops = {
++
++	.vidioc_streamon		= vidioc_streamon,
++	.vidioc_streamoff		= vidioc_streamoff,
++
++	.vidioc_reqbufs			= vidioc_reqbufs,
++	.vidioc_querybuf		= vidioc_querybuf,
++	.vidioc_qbuf			= vidioc_qbuf,
++	.vidioc_dqbuf			= vidioc_dqbuf,
++
++	.vidioc_querycap		= vidioc_querycap,
++	.vidioc_enum_fmt_vid_cap 	= vidioc_enum_fmt_vid_cap_mplane,
++	.vidioc_enum_fmt_vid_out 	= vidioc_enum_fmt_vid_out_mplane,
++	.vidioc_enum_framesizes		= vidioc_enum_framesizes,
++
++	.vidioc_try_fmt_vid_cap_mplane	= vidioc_try_fmt_vid_cap_mplane,
++	.vidioc_try_fmt_vid_out_mplane	= vidioc_try_fmt_vid_out_mplane,
++	.vidioc_expbuf			= vidioc_expbuf,
++	.vidioc_subscribe_event		= v4l2_ctrl_subscribe_event,
++	.vidioc_unsubscribe_event	= v4l2_event_unsubscribe,
++
++	.vidioc_s_parm			= vidioc_s_parm,
++	.vidioc_g_parm			= vidioc_g_parm,
++	.vidioc_s_fmt_vid_cap_mplane	= vidioc_s_fmt_cap,
++	.vidioc_s_fmt_vid_out_mplane	= vidioc_s_fmt_out,
++
++	.vidioc_g_fmt_vid_cap_mplane	= vidioc_g_fmt,
++	.vidioc_g_fmt_vid_out_mplane	= vidioc_g_fmt,
++
++	.vidioc_create_bufs		= vidioc_create_bufs,
++	.vidioc_prepare_buf		= vidioc_prepare_buf,
++
++	.vidioc_g_selection		= vidioc_g_selection,
++	.vidioc_s_selection		= vidioc_s_selection,
++};
++
++
++static int vb2ops_venc_queue_setup(struct vb2_queue *vq,
++				unsigned int *nbuffers,
++				unsigned int *nplanes,
++				unsigned int sizes[],
++				struct device *alloc_ctxs[])
++{
++	struct ingenic_venc_ctx *ctx = vb2_get_drv_priv(vq);
++	struct ingenic_venc_q_data *q_data;
++	int i;
++
++	q_data = ingenic_venc_get_q_data(ctx, vq->type);
++	if(q_data == NULL)
++		return -EINVAL;
++
++	if(*nplanes) {
++		for(i = 0; i < *nplanes; i++) {
++			if(vq->memory != VB2_MEMORY_USERPTR){
++				q_data->sizeimage[i] = q_data->sizeimage[i]/q_data->coded_height * ALIGN(q_data->coded_height, 16);
++				sizes[i]= sizes[i] / q_data->coded_height * ALIGN(q_data->coded_height, 16);
++			}
++			if(sizes[i] < q_data->sizeimage[i]) {
++				return -EINVAL;
++			}
++		}
++	} else {
++		*nplanes = q_data->fmt->num_planes;
++		for (i = 0; i < *nplanes; i++) {
++			sizes[i] = q_data->sizeimage[i];
++			alloc_ctxs[i] = ctx->dev->dev;
++		}
++	}
++
++
++	dev_dbg(ctx->dev->dev, "*nplanes %d, sizes[0] %d\n", *nplanes, sizes[0]);
++	for(i = 0; i<*nplanes ; i++) {
++		dev_dbg(ctx->dev->dev, "plane %d, sizes[%d] %d, type  %d\n", i, i, sizes[i], vq->type);
++	}
++
++	if(*nbuffers > MAX_SUPPORT_FRAME_BUFFERS)
++		*nbuffers = MAX_SUPPORT_FRAME_BUFFERS;
++
++	return 0;
++}
++
++static int vb2ops_venc_buf_prepare(struct vb2_buffer *vb)
++{
++	struct ingenic_venc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
++	struct ingenic_venc_q_data *q_data;
++	int i;
++
++	q_data = ingenic_venc_get_q_data(ctx, vb->vb2_queue->type);
++
++	for(i = 0; i < q_data->fmt->num_planes; i++) {
++		if(vb2_plane_size(vb, i) > q_data->sizeimage[i]) {
++
++			dev_err(ctx->dev->dev, "Failed to prepare buf!\n");
++
++			return -EINVAL;
++		}
++	}
++
++	return 0;
++}
++
++static void vb2ops_venc_buf_queue(struct vb2_buffer *vb)
++{
++	struct ingenic_venc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
++
++	v4l2_m2m_buf_queue(ctx->m2m_ctx, to_vb2_v4l2_buffer(vb));
++	return;
++}
++
++
++static int vb2ops_venc_start_streaming(struct vb2_queue *q, unsigned int count)
++{
++	struct ingenic_venc_ctx *ctx = vb2_get_drv_priv(q);
++	struct ingenic_venc_q_data *q_data_src;
++	struct ingenic_venc_q_data *q_data_dst;
++	struct h264e_ctx *h264e_ctx = &ctx->h264e_ctx;
++	struct jpge_ctx *jpge_ctx = &ctx->jpge_ctx;
++	struct jpgd_ctx *jpgd_ctx = &ctx->jpgd_ctx;
++	int ret = 0;
++
++	if(V4L2_TYPE_IS_OUTPUT(q->type)) {
++		ctx->output_stopped = 0;
++	} else {
++		ctx->capture_stopped = 0;
++	}
++
++	if(ctx->output_stopped || ctx->capture_stopped)
++		return 0;
++
++	q_data_src = ingenic_venc_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
++	q_data_dst = ingenic_venc_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
++
++	if(ctx->codec_id == CODEC_ID_H264E) {
++		dev_info(ctx->dev->dev, "h264 start streaming \n");
++		ret = h264e_set_fmt(h264e_ctx, q_data_src->coded_width,
++			q_data_src->coded_height, q_data_src->fmt->format);
++		if(ret < 0) {
++			return ret;
++		}
++		ret = h264e_alloc_workbuf(h264e_ctx);
++		if(ret < 0) {
++			dev_err(ctx->dev->dev, "h264e failed to alloc work buffer!\n");
++			return ret;
++		}
++		ctx->state = INGENIC_STATE_HEADER;
++
++		ret = h264e_generate_headers(h264e_ctx, 1);
++		if(ret < 0)
++			return ret;
++
++	} else if(ctx->codec_id == CODEC_ID_JPGE) {
++		dev_info(ctx->dev->dev, "jpge start streaming \n");
++
++		ret = jpeg_encoder_set_fmt(jpge_ctx, q_data_src->coded_width,
++			q_data_src->coded_height, q_data_src->fmt->format);
++		if(ret < 0) {
++			return ret;
++		}
++		ret = jpeg_encoder_alloc_workbuf(jpge_ctx);
++		if(ret < 0) {
++			dev_err(ctx->dev->dev, "jpge failed to alloc work buffer!\n");
++			return ret;
++		}
++		ctx->state = INGENIC_STATE_RUNNING;
++
++	} else if(ctx->codec_id == CODEC_ID_JPGD) {
++		dev_info(ctx->dev->dev, "jpgd start streaming \n");
++
++		ret = jpeg_decoder_set_fmt(jpgd_ctx, q_data_dst->coded_width,
++			q_data_dst->coded_height, q_data_dst->fmt->format);
++		if(ret < 0) {
++			return ret;
++		}
++		ret = jpeg_decoder_alloc_workbuf(jpgd_ctx);
++		if(ret < 0) {
++			dev_err(ctx->dev->dev, "jpgd failed to alloc work buffer!\n");
++			return ret;
++		}
++		ctx->state = INGENIC_STATE_RUNNING;
++
++	} else {
++		dev_info(ctx->dev->dev, "Invalid Codec ID: %d\n", ctx->codec_id);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static void vb2ops_venc_stop_streaming(struct vb2_queue *q)
++{
++
++	struct ingenic_venc_ctx *ctx = vb2_get_drv_priv(q);
++	struct vb2_v4l2_buffer *src_buf, *dst_buf;
++	struct ingenic_venc_q_data *q_data_src;
++	struct ingenic_venc_q_data *q_data_dst;
++	struct h264e_ctx *h264e_ctx = &ctx->h264e_ctx;
++	struct jpge_ctx *jpge_ctx = &ctx->jpge_ctx;
++	struct jpgd_ctx *jpgd_ctx = &ctx->jpgd_ctx;
++
++//	if(q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
++
++	/* KERNEL 3.10 .*/
++		while((dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx))) {
++			dst_buf->vb2_buf.planes[0].bytesused = 0;
++			dst_buf->flags |= V4L2_BUF_FLAG_DONE;
++//			ktime_get_real_ts64(&dst_buf->vb2_buf.timestamp);
++			dst_buf->vb2_buf.timestamp = ktime_get();
++			/*��两个的时间戳�一样.*/
++			dst_buf->vb2_buf.timestamp = ktime_add_ns(dst_buf->vb2_buf.timestamp, 10);
++			/* work around, return buffer to userspace with 0 byteused. */
++			v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
++		}
++//	} else {
++		while((src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx))) {
++			v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
++		}
++//	}
++
++	if(q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
++		ctx->capture_stopped = 1;
++	else
++		ctx->output_stopped = 1;
++
++	if((ctx->capture_stopped && ctx->output_stopped) == 0) {
++		return;
++	}
++
++	q_data_src = ingenic_venc_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
++	q_data_dst = ingenic_venc_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
++
++	switch(ctx->codec_id) {
++		case CODEC_ID_H264E:
++			dev_info(ctx->dev->dev, "h264 stop streaming !\n");
++			h264e_free_workbuf(h264e_ctx);
++			break;
++		case CODEC_ID_JPGE:
++			dev_info(ctx->dev->dev, "jpge stop streaming !\n");
++			jpeg_encoder_free_workbuf(jpge_ctx);
++			break;
++		case CODEC_ID_JPGD:
++			dev_info(ctx->dev->dev, "jpgd stop streaming !\n");
++			jpeg_decoder_free_workbuf(jpgd_ctx);
++			break;
++		default:
++			break;
++	}
++
++	ctx->state = INGENIC_STATE_IDLE;
++	return;
++}
++
++static const struct vb2_ops ingenic_venc_vb2_ops = {
++	.queue_setup		= vb2ops_venc_queue_setup,
++	.buf_prepare		= vb2ops_venc_buf_prepare,
++	.buf_queue		= vb2ops_venc_buf_queue,
++	.wait_prepare		= vb2_ops_wait_prepare,
++	.wait_finish		= vb2_ops_wait_finish,
++	.start_streaming	= vb2ops_venc_start_streaming,
++	.stop_streaming		= vb2ops_venc_stop_streaming,
++};
++
++static void ingenic_venc_worker(struct work_struct *work)
++{
++
++	struct ingenic_venc_ctx *ctx = container_of(work, struct ingenic_venc_ctx, encode_work);
++	struct ingenic_venc_dev *dev = ctx->dev;
++	struct vb2_v4l2_buffer *src_buf, *dst_buf;
++	struct ingenic_video_buf *src_video_buf, *dst_video_buf;
++
++	struct video_frame_buffer *src_frame = NULL;
++	struct video_frame_buffer *dst_frame = NULL;
++
++	struct h264e_ctx *h264e_ctx = &ctx->h264e_ctx;
++	struct jpge_ctx *jpge_ctx = &ctx->jpge_ctx;
++	struct jpgd_ctx *jpgd_ctx = &ctx->jpgd_ctx;
++	int force_idr = 0;
++	int keyframe = 0;
++
++	int i = 0;
++	int ret = 0;
++
++
++	src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
++	src_video_buf = container_of(src_buf, struct ingenic_video_buf, vb);
++	src_frame = &src_video_buf->buf;
++
++	memset(src_frame, 0, sizeof(src_frame));
++	src_frame->num_planes = src_buf->vb2_buf.num_planes;
++	for(i = 0; i < src_buf->vb2_buf.num_planes; i++) {
++		src_frame->fb_addr[i].pa = ingenic_vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, i);
++		if (src_buf->vb2_buf.memory == VB2_MEMORY_USERPTR)
++			src_frame->fb_addr[i].va = phys_to_virt(src_frame->fb_addr[i].pa);
++		else
++			src_frame->fb_addr[i].va = vb2_plane_vaddr(&src_buf->vb2_buf, i);
++
++		src_frame->fb_addr[i].size = vb2_get_plane_payload(&src_buf->vb2_buf, i);
++
++#if 0
++		printk("---va %x, length %d, bytesused %d\n", vb2_plane_vaddr(src_buf, i),
++				(size_t)src_buf->vb2_buf.planes[i].length,
++				src_buf->vb2_buf.planes[i].bytesused);
++
++		print_hex_dump(KERN_INFO, "input", DUMP_PREFIX_ADDRESS, 16, 1, src_frame->fb_addr[i].va, 64, 1);
++#endif
++	}
++
++	dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
++	dst_buf->vb2_buf.planes[0].bytesused = 0;
++	dst_video_buf = container_of(dst_buf, struct ingenic_video_buf, vb);
++	dst_frame = &dst_video_buf->buf;
++	dst_frame->num_planes = dst_buf->vb2_buf.num_planes;
++
++	if(ctx->state == INGENIC_STATE_HEADER) {
++
++		if(ctx->codec_id != CODEC_ID_H264E) {
++			dev_err(ctx->dev->dev, "invalid state!\n");
++			ctx->state = INGENIC_STATE_ABORT;
++			return;
++		}
++		dst_frame->fb_addr[0].pa = ingenic_vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
++		if (dst_buf->vb2_buf.memory == VB2_MEMORY_USERPTR)
++			dst_frame->fb_addr[0].va = phys_to_virt(dst_frame->fb_addr[0].pa);
++		else
++			dst_frame->fb_addr[0].va = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);
++
++		h264e_ctx->encoded_bs_len = 0;
++		ret = h264e_encode_headers(h264e_ctx, &dst_frame->fb_addr[0]);
++		if(ret < 0) {
++			ctx->state = INGENIC_STATE_ABORT;
++			return;
++		}
++#if 0 //TODO:
++		if(h264e_ctx->p.h264_hdr_mode == V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME) {
++			dst_frame->fb_addr[0].va += h264e_ctx->encoded_bs_len;
++			dst_frame->fb_addr[0].pa += h264e_ctx->encoded_bs_len;
++			dst_buf->vb2_buf.planes[0].bytesused = h264e_ctx->encoded_bs_len;
++		} else {
++
++			dst_buf->vb2_buf.planes[0].bytesused = h264e_ctx->encoded_bs_len;
++			dst_buf->vb2_buf.timestamp = src_buf->vb2_buf.timestamp;
++			dst_buf->timecode = src_buf->timecode;
++
++			v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
++
++			dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
++			if(!dst_buf) {
++				dev_err(ctx->dev->dev, "Failed to get dst buf!\n");
++				ctx->state = INGENIC_STATE_ABORT;
++				return;
++			}
++
++			dst_frame->fb_addr[0].pa = ingenic_vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
++			if (dst_buf->vb2_buf.memory == VB2_MEMORY_USERPTR)
++				dst_frame->fb_addr[0].va = phys_to_virt(dst_frame->fb_addr[0].pa);
++			else
++				dst_frame->fb_addr[0].va = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);
++
++			dst_buf->vb2_buf.planes[0].bytesused = 0;
++		}
++#endif
++
++		ctx->state = INGENIC_STATE_RUNNING;
++	} else {
++		for(i = 0; i < dst_buf->vb2_buf.num_planes; i++) {
++			dst_frame->fb_addr[i].pa = ingenic_vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, i);
++			if (dst_buf->vb2_buf.memory == VB2_MEMORY_USERPTR)
++				dst_frame->fb_addr[i].va = phys_to_virt(dst_frame->fb_addr[i].pa);
++			else
++				dst_frame->fb_addr[i].va = vb2_plane_vaddr(&dst_buf->vb2_buf, i);
++		}
++		//bs_buf->size = (size_t)dst_buf->vb2_buf.planes[0].length;
++	}
++
++	switch(ctx->codec_id) {
++		case CODEC_ID_H264E:
++			h264e_ctx->encoded_bs_len = 0;
++			if(src_buf->flags & V4L2_BUF_FLAG_KEYFRAME) {
++				force_idr = 1;
++			}
++
++			ret = h264e_encode(h264e_ctx, src_frame, &dst_frame->fb_addr[0], force_idr, &keyframe);
++
++			if(keyframe) {
++				dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
++			} else {
++				dst_buf->flags &= ~V4L2_BUF_FLAG_KEYFRAME;
++			}
++			dst_buf->vb2_buf.planes[0].bytesused += h264e_ctx->encoded_bs_len; /* returned bs size. */
++			if(dst_buf->vb2_buf.planes[0].bytesused > dst_buf->vb2_buf.planes[0].length) {
++				dev_err(dev->dev, "[dangerous] vpu output bs length too large, system will crash!! encoded_bs_len: %d\n",
++					h264e_ctx->encoded_bs_len);
++				ctx->state = INGENIC_STATE_ABORT;
++			}
++			break;
++		case CODEC_ID_JPGE:
++
++			ret = jpeg_encoder_encode(jpge_ctx, src_frame, &dst_frame->fb_addr[0]);
++			if(ret < 0) {
++				ctx->state = INGENIC_STATE_ABORT;
++			}
++
++			vb2_set_plane_payload(&dst_buf->vb2_buf, 0, jpge_ctx->bslen);
++
++			//dst_buf->vb2_buf.planes[0].bytesused = jpge_ctx->bslen;
++			break;
++		case CODEC_ID_JPGD:
++			/*src bs? dst raw? */
++			ret = jpeg_decoder_decode(jpgd_ctx, &src_frame->fb_addr[0], dst_frame);
++			if(ret < 0) {
++				ctx->state = INGENIC_STATE_ABORT;
++			}
++
++			break;
++		default:
++			break;
++	}
++
++	v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
++
++	dst_buf->vb2_buf.timestamp = src_buf->vb2_buf.timestamp;
++	dst_buf->timecode = src_buf->timecode;
++	dst_buf->sequence = src_buf->sequence;
++
++//	printk("dst_buf->timestamp.tv_sec: %ld, dst_buf->timestamp.tv_usec: %ld, sequence: %d, bytesused: %d\n", dst_buf->timestamp.tv_sec, dst_buf->timestamp.tv_usec, dst_buf->sequence, vb2_get_plane_payload(&dst_buf->vb2_buf, 0));
++
++	v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
++
++	v4l2_m2m_job_finish(ctx->dev->m2m_dev_enc, ctx->m2m_ctx);
++}
++
++static void m2mops_venc_device_run(void * priv)
++{
++	struct ingenic_venc_ctx *ctx = priv;
++	struct ingenic_venc_dev *dev = ctx->dev;
++
++	queue_work(dev->encode_workqueue, &ctx->encode_work);
++}
++
++static int m2mops_venc_job_ready(void *m2m_priv)
++{
++	struct ingenic_venc_ctx *ctx = m2m_priv;
++
++	if(ctx->state == INGENIC_STATE_ABORT || ctx->state == INGENIC_STATE_IDLE) {
++		dev_info(ctx->dev->dev, "job not ready, ctx->state %d\n", ctx->state);
++		return 0;
++	}
++
++	return 1;
++}
++
++
++static void m2mops_venc_job_abort(void *priv)
++{
++	struct ingenic_venc_ctx *ctx = priv;
++
++	ctx->state = INGENIC_STATE_ABORT;
++}
++
++const struct v4l2_m2m_ops ingenic_venc_m2m_ops = {
++	.device_run		= m2mops_venc_device_run,
++	.job_ready		= m2mops_venc_job_ready,
++	.job_abort		= m2mops_venc_job_abort,
++};
++
++
++
++int ingenic_vcodec_enc_init_default_params(struct ingenic_venc_ctx *ctx)
++{
++
++	int ret = 0;
++
++
++	ctx->capture_stopped = 1;
++	ctx->output_stopped = 1;
++
++	//ctx->m2m_ctx->q_lock = &ctx->dev->dev_mutex;
++	//ctx->fh.m2m_ctx = ctx->m2m_ctx;
++	ctx->fh.ctrl_handler = &ctx->ctrl_hdl;
++	INIT_WORK(&ctx->encode_work, ingenic_venc_worker);
++
++	return ret;
++}
++
++int ingenic_vcodec_enc_deinit_default_params(struct ingenic_venc_ctx *ctx)
++{
++
++	struct h264e_ctx *h264e_ctx = &ctx->h264e_ctx;
++	struct jpge_ctx *jpge_ctx = &ctx->jpge_ctx;
++	struct jpgd_ctx *jpgd_ctx = &ctx->jpgd_ctx;
++
++	switch(ctx->codec_id) {
++		case CODEC_ID_H264E:
++			h264e_encoder_deinit(h264e_ctx);
++			break;
++		case CODEC_ID_JPGE:
++			jpeg_encoder_deinit(jpge_ctx);
++			break;
++		case CODEC_ID_JPGD:
++			jpeg_decoder_deinit(jpgd_ctx);
++			break;
++		default:
++			break;
++	}
++
++	return 0;
++}
++
++
++#define INGENIC_MAX_CTRLS_HINT	20
++int ingenic_vcodec_enc_ctrls_setup(struct ingenic_venc_ctx *ctx)
++{
++	const struct v4l2_ctrl_ops *ops = &ingenic_venc_ctrl_ops;
++	struct v4l2_ctrl_handler *handler = &ctx->ctrl_hdl;
++
++	v4l2_ctrl_handler_init(handler, INGENIC_MAX_CTRLS_HINT);
++
++	v4l2_ctrl_new_std(handler, ops, V4L2_CID_JPEG_COMPRESSION_QUALITY,
++			0, 2, 1, 1);
++	v4l2_ctrl_new_std(handler, ops, V4L2_CID_MPEG_VIDEO_BITRATE,
++			1, 4000000, 1, 4000000);
++	v4l2_ctrl_new_std(handler, ops, V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP,
++			0, 51, 1, 30);
++	v4l2_ctrl_new_std(handler, ops, V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP,
++			0, 51, 1, 30);
++//	v4l2_ctrl_new_std(handler, ops, V4L2_CID_MPEG_VIDEO_B_FRAMES,
++//			0, 2, 1, 0);
++	v4l2_ctrl_new_std(handler, ops, V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE,
++			0, 1, 1, 1);
++	v4l2_ctrl_new_std(handler, ops, V4L2_CID_MPEG_VIDEO_H264_MAX_QP,
++			0, 51, 1, 40);
++	v4l2_ctrl_new_std(handler, ops, V4L2_CID_MPEG_VIDEO_H264_MIN_QP,
++			0, 51, 1, 10);
++	v4l2_ctrl_new_std(handler, ops, V4L2_CID_MPEG_VIDEO_H264_I_PERIOD,
++			0, 65535, 1, 0);
++	v4l2_ctrl_new_std(handler, ops, V4L2_CID_MPEG_VIDEO_GOP_SIZE,
++			0, 65535, 1, 50);
++	v4l2_ctrl_new_std(handler, ops, V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE,
++			0, 1, 1, 0);
++	v4l2_ctrl_new_std_menu(handler, ops,
++			V4L2_CID_MPEG_VIDEO_HEADER_MODE,
++			V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
++			0, V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME);
++	v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_MPEG_VIDEO_H264_PROFILE,
++			V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
++			0, V4L2_MPEG_VIDEO_H264_PROFILE_MAIN);
++	v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_MPEG_VIDEO_H264_LEVEL,
++			V4L2_MPEG_VIDEO_H264_LEVEL_4_2,
++			0, V4L2_MPEG_VIDEO_H264_LEVEL_3_0);
++	v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
++			V4L2_MPEG_VIDEO_BITRATE_MODE_CQ,
++			0, V4L2_MPEG_VIDEO_BITRATE_MODE_CBR);
++	if (handler->error) {
++		dev_err(ctx->dev->dev, "Init control handler fail %d\n",
++				handler->error);
++		return handler->error;
++	}
++
++	v4l2_ctrl_handler_setup(&ctx->ctrl_hdl);
++
++	return 0;
++}
++
++int ingenic_vcodec_enc_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
++{
++	struct ingenic_venc_ctx *ctx = priv;
++	int ret = 0;
++
++	src_vq->type		= V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
++	src_vq->io_modes	= VB2_DMABUF | VB2_MMAP | VB2_USERPTR;
++	src_vq->drv_priv	= ctx;
++	src_vq->buf_struct_size	= sizeof(struct ingenic_video_buf);
++	src_vq->ops		= &ingenic_venc_vb2_ops;
++	src_vq->mem_ops		= &ingenic_vb2_dma_contig_memops;
++	src_vq->lock		= &ctx->dev->dev_mutex;
++	src_vq->timestamp_flags  = V4L2_BUF_FLAG_TIMESTAMP_COPY;
++	src_vq->dev		= ctx->dev->dev;
++
++	ret = vb2_queue_init(src_vq);
++	if(ret)
++		return ret;
++
++
++	dst_vq->type		= V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
++	dst_vq->io_modes	= VB2_DMABUF | VB2_MMAP | VB2_USERPTR;
++	dst_vq->drv_priv	= ctx;
++	dst_vq->buf_struct_size	= sizeof(struct ingenic_video_buf);
++	dst_vq->ops		= &ingenic_venc_vb2_ops;
++	dst_vq->mem_ops		= &ingenic_vb2_dma_contig_memops;
++	dst_vq->lock		= &ctx->dev->dev_mutex;
++	dst_vq->timestamp_flags  = V4L2_BUF_FLAG_TIMESTAMP_COPY;
++	dst_vq->dev		= ctx->dev->dev;
++
++	return vb2_queue_init(dst_vq);
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/helix_ops.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/helix_ops.h
+new file mode 100644
+index 000000000..7eb7d8627
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/helix_ops.h
+@@ -0,0 +1,17 @@
++#ifndef __INGENIC_HELIX_OPS_H__
++#define __INGENIC_HELIX_OPS_H__
++
++
++extern const struct v4l2_ioctl_ops ingenic_venc_ioctl_ops;
++extern const struct v4l2_m2m_ops ingenic_venc_m2m_ops;
++
++
++
++int ingenic_vcodec_enc_init_default_params(struct ingenic_venc_ctx *ctx);
++int ingenic_vcodec_enc_deinit_default_params(struct ingenic_venc_ctx *ctx);
++
++int ingenic_vcodec_enc_ctrls_setup(struct ingenic_venc_ctx *ctx);
++int ingenic_vcodec_enc_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq);
++
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpgd.c b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpgd.c
+new file mode 100644
+index 000000000..c7d56bd50
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpgd.c
+@@ -0,0 +1,569 @@
++/*
++* Copyright© 2014 Ingenic Semiconductor Co.,Ltd
++*
++* Author: qipengzhen <aric.pzqi@ingenic.com>
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License version 2 as
++* published by the Free Software Foundation.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++* GNU General Public License for more details.
++*
++*/
++
++#include <linux/slab.h>
++#include <media/v4l2-mem2mem.h>
++
++
++#include "helix_buf.h"
++#include "helix_drv.h"
++#include "jpgd.h"
++
++static void __maybe_unused dump_slice_info(_JPEGD_SliceInfo *s)
++{
++	printk("s->des_va:	%08x\n", (unsigned int)s->des_va);
++	printk("s->des_pa:	%08x\n", s->des_pa);
++	printk("s->bsa:		%08x\n", s->bsa);
++	printk("s->p0a:		%08x\n", s->p0a);
++	printk("s->p1a:		%08x\n", s->p1a);
++	printk("s->nrsm:	%d\n", s->nrsm);
++	printk("s->nmcu:	%d\n", s->nmcu);
++	printk("s->pxc[0]:	%x\n", s->pxc[0]);
++	printk("s->pxc[1]:	%x\n", s->pxc[1]);
++	printk("s->pxc[2]:	%x\n", s->pxc[2]);
++	printk("s->pxc[3]:	%x\n", s->pxc[3]);
++}
++
++static int jpgd_fill_slice_info(struct jpgd_ctx *ctx)
++{
++	struct jpgd_params *p = &ctx->p;
++	_JPEGD_SliceInfo *s = ctx->s;
++	int ret = 0;
++
++	s->des_va 	= ctx->desc;
++	s->des_pa 	= ctx->desc_pa;
++	s->bsa	  	= ctx->bs->pa;
++	s->p0a	  	= ctx->frame->fb_addr[0].pa;
++	s->p1a	  	= ctx->frame->fb_addr[1].pa;
++	s->nrsm	  	= 0;
++	s->nmcu	  	= ((p->height + 15) / 16) * ((p->width + 15) / 16) - 1;
++	s->huffmin 	= p->huffmin;
++	s->huffbase 	= p->hea;
++	s->huffsymb 	= p->heb;
++	s->qmem     	= (int *)p->qt;
++
++	if(p->format == HELIX_NV12_MODE) {
++		s->width = 1 << 15 | ((p->width + 15) / 16 - 1);
++	}
++	s->pxc[0]	= p->pxc[0];
++	s->pxc[1]	= p->pxc[1];
++	s->pxc[2]	= p->pxc[2];
++	s->pxc[3]	= p->pxc[3];
++
++	return ret;
++}
++
++/* decode header info to params ??*/
++static int jpgd_decode_header(struct jpgd_ctx *ctx)
++{
++	struct ingenic_venc_ctx *venc_ctx = ctx->priv;
++	struct ingenic_vcodec_mem *bs = ctx->bs;
++	struct jpgd_params *p = &ctx->p;
++	unsigned char *pbuf = bs->va;
++	int bslen = bs->size;
++	unsigned char *bsend = bs->va + bs->size;
++
++	int hbase, hb, abase, bbase, dc, ht;
++	int i,j,n,v,c,nrst,nm,code,hid;
++
++	int ncol;
++	int l[16];
++	int nblk[4] = {0};
++	int qt_sel[4] = {0};
++	int ha_sel[4] = {0};
++	int hd_sel[4] = {0};
++	int is_sos = 0;
++
++	unsigned char *dst_bs = bs->va;
++	unsigned char *dst_bslen = 0;
++	unsigned int min0, min1, min2, min3;
++
++	nrst = nm = ncol = 0;
++	/* init default table ?*/
++	for(i = 0; i < 384; i++) {
++		p->huffenc[i] = 0xfff;
++	}
++	for(i = 168, j = 0xfd0; i < 176; i++, j++) {
++		p->huffenc[i] = j;
++	}
++	for(i = 344, j = 0xfd0; i < 352; i++, j++) {
++		p->huffenc[i] = j;
++	}
++
++	for(i=162;i<174;i++)
++		p->heb[i]=0;
++
++	for(i=0;i<4;i++)
++		for(j=0;j<64;j++)
++			p->qt[i][j] = 0;
++
++	while(1) {
++
++		if(is_sos || pbuf >= bsend) {
++			break;
++		}
++
++		c = *pbuf++;
++		if(c != 0xff)
++			continue;
++
++
++		while((c = *pbuf++) == 0xff);
++		if(c == 0) {
++			/* not a marker */
++			continue;
++		}
++marker:
++		switch(c) {
++			case 0xc0 : // Baseline (0, 0)
++			case 0xc1 : // Ext. Sequential, Huffman (0, 0)
++			case 0xc2 : // Progressive, Huffman (1, 0)
++			case 0xc3 : // Lossless, Huffman
++			case 0xc5 : // Differential Sequential, Huffman
++			case 0xc6 : // Differential Progressive, Huffman
++			case 0xc7 : // Differential Lossless, Huffman
++			case 0xc9 : // Extended Sequential, Arithmetic (0, 1)
++			case 0xca : // Progressive, Arithmetic (1, 1)
++			case 0xcb : // Lossless, Huffman
++			case 0xcd : // Differential Sequential, Arithmetic
++			case 0xce : // Differential Progressive, Arithmetic
++			case 0xcf : // Differential Lossless, Arithmetic
++
++				pbuf += 3;
++				p->height = (*pbuf++ << 8) | *pbuf++;
++				p->width  = (*pbuf++ << 8) | *pbuf++;
++				ncol	  = *pbuf++;
++
++				for(i = 0; i < ncol; i++) {
++					pbuf++;
++					nblk[i] = *pbuf++;
++					qt_sel[i] = *pbuf++;
++				}
++				break;
++			case 0xc4 :
++				/* DHT marker detected */
++				/* Get the lenght of the marker segment */
++				// Lh : HT length (16b)
++				n = (*pbuf++ << 8) | *pbuf++;
++
++				/* reduce 2 ?*/
++				n -= 2;
++
++				while(n) {
++					/* Get the type of table */
++					v= *pbuf++; // Tc & Th
++					// Tc : Table class (4b)
++					//      0 = DC or lossless table
++					//      1 = AC table
++					// Th : HT destination identifier
++					// - specifies 1 of 4 possible destinations at the decoder into
++					// which HT shall be installed.
++
++					/* Reduce marker segment byte count */
++					n--;
++
++					hid = v>>4 ? 2 : 0;
++					hid |= v&15 ? 1 : 0;
++					switch(hid){
++						case 1:
++							hbase = 368;
++							break;
++						case 2:
++							hbase = 0;
++							break;
++						case 3:
++							hbase = 176;
++							break;
++						default :
++							hbase = 352;
++							break;
++					}
++					if((v>>4))
++						abase = 0;
++					else
++						abase = 1;
++
++					dc = abase;
++					ht = v&15;
++					abase |=ht<<1;
++					switch(abase){
++						case 1 :
++						case 3 :
++							bbase = 162;
++							break;
++						case 2 :
++							bbase = 174;
++							break;
++						default :
++							bbase = 0;
++							break;
++					}
++					abase <<= 4;
++
++					/* Memory initialization */
++					for(i = abase; i < abase+16; i++)
++						p->hea[i] = 255;
++					/* Get the number of codes for each length */
++					// Lj : # of Huffman codes of length i
++					// - specifies the # of Huffman codes for each of 16 possible lengths
++					// allowed by spec. BITS
++					for(i = 0; i < 16; i++) {
++						l[i] = *pbuf++;
++					}
++					/* Reduce marker segment byte count */
++					n -= 16;
++					code = 0;
++					for(i=0; i<16; i++,abase++) {
++						p->min[abase] = code;
++						p->hea[abase] = bbase - code;
++						if(l[i]) {
++							// Vi,j : associated with each Huffman code
++							// - specifies, for each i the value associated with each Huffman code
++							// of length i.  HUFFVAL
++							for(j=0; j<l[i]; j++,bbase++){
++								v = *pbuf++;
++								/* Reduce marker segment byte count */
++								n--;
++								if(dc){
++									p->huffenc[hbase+v]= (i<<8) | (code&0xff);
++									v &= 15;
++									if(ht)
++										v <<= 4;
++									p->heb[bbase] |= v;
++								} else{
++									if(v == 0)
++										hb = 160;
++									else if(v == 0xf0)
++										hb = 161;
++									else
++										hb = (v>>4)*10 + (v&0xf) - 1;
++									p->huffenc[hbase+hb] = (i<<8) | (code&0xff);
++									p->heb[bbase] = v;
++								}
++								code++;
++							}
++
++						}
++						code <<= 1;
++					}
++				}
++				break;
++			case 0xc8 :
++				break;
++
++			case 0xcc :
++				break;
++			/* M_RST0 ~ M_RST7, ignore? */
++			case 0xd0 :
++			case 0xd1 :
++			case 0xd2 :
++			case 0xd3 :
++			case 0xd4 :
++			case 0xd5 :
++			case 0xd6 :
++			case 0xd7 :
++				break;
++			/* M_SOI */
++			case 0xd8 :
++				break;
++			/* M_EOI */
++			case 0xd9 :
++				*dst_bs++ = 0xff;
++				dst_bslen++;
++				*dst_bs++ = 0xd9;
++				dst_bslen++;
++				break;
++			/* M_SOS */
++			case 0xda :
++				pbuf += 2;
++				n= *pbuf++; //Ns (# of image components)
++
++				for(i=0;i<n;i++){
++					// Cs, Td&Ta
++					pbuf++;
++
++					ha_sel[i] = hd_sel[i] = *pbuf++;
++					ha_sel[i] = (ha_sel[i] & 0x30)>>4;
++					hd_sel[i] = hd_sel[i] & 0x3;
++				}
++				pbuf++; //Ss
++				pbuf++; //Se
++				pbuf++; //Ah&Al
++				/* TODO... */
++				/* BS left can be decoded by vpu.*/
++				is_sos = 1;
++
++				break;
++			case 0xdb :
++				// Lq : QT Length (16b)
++				v = (*pbuf++ << 8) | *pbuf++;
++				int len = v-2;
++				while (len > 0) {
++					int prec;
++					v = *pbuf++;
++					// Pq : QT element precision (4b)
++					// - specifies the precision of the Qk values.
++					//   0 indicates 8-bits Qk values.
++					//   1 indicates 16-bits Qk values
++					prec = v >> 4;
++					// Tq : QT destination identifier (4b)
++					// - specifies one of 4 possible destnations at the decoder into
++					// which the QT shall be installed.
++					n = v&15;
++					if(n > 3){
++						/*ijpegd_log(h, C_LOG_DEBUG, "error QT\n");*/
++					}
++					for(i=0;i<64;i++) {
++						// Qk: Quantization table element
++						// k is the index in the zigzag ordering of the DCT coeff
++						// JPC only do 8-bit Qk! (ie, Pq shall be 0)
++						if(prec){
++							p->qt[n][i] = (*pbuf++ << 8) | *pbuf++;
++						} else {
++							p->qt[n][i] = (*pbuf++);
++						}
++					}
++					len -= 64+1;
++					if(prec) {
++						len -= 64;
++					}
++				}
++				break;
++			case 0xdd :
++				// Lr : restart interval segment length (16b)
++				// - specifies the length of the paramenters in the DRI segment
++				pbuf += 2;
++				// Ri : restart interval (16b)
++				// - specifies the number of MCU in the restart interval.
++				nrst = (*pbuf++ << 8) | *pbuf++;
++				break;
++			case 0xe0 :/* All these markers are ignored */
++			case 0xe1 :
++			case 0xe2 :
++			case 0xe3 :
++			case 0xe4 :
++			case 0xe5 :
++			case 0xe6 :
++			case 0xe7 :
++			case 0xe8 :
++			case 0xe9 :
++			case 0xea :
++			case 0xeb :
++			case 0xec :
++			case 0xed :
++			case 0xee :
++			case 0xef :
++			case 0xf0 :
++			case 0xf1 :
++			case 0xf2 :
++			case 0xf3 :
++			case 0xf4 :
++			case 0xf5 :
++			case 0xf6 :
++			case 0xf7 :
++			case 0xf8 :
++			case 0xf9 :
++			case 0xfa :
++			case 0xfb :
++			case 0xfc :
++			case 0xfd :
++			case 0xfe :
++				v = (*pbuf++ << 8) | *pbuf++;
++				v-=2;
++				pbuf += v;
++				break;
++			default :
++				break;
++		}
++
++	}
++
++	for(i = 0; i < 64;) {
++		v = p->min[i++]&1;
++		v <<= 2;
++		v |= p->min[i++]&3;
++		v <<= 3;
++		v |= p->min[i++]&7;
++		min3 = (v>>2) & 0xF;
++		//ijpegd_log(h, C_LOG_DEBUG, fpo,"%x",v>>2);
++		v <<= 4;
++		v |= p->min[i++]&15;
++		v <<= 5;
++		v |= p->min[i++]&31;
++		v <<= 6;
++		v |= p->min[i++]&63;
++		v <<=7;
++		v |= p->min[i++]&127;
++		v <<=8;
++		v |=p->min[i++]&255;
++		min2 = v & 0xFFFFFFFF;
++		//ijpegd_log(h, C_LOG_DEBUG, fpo,"%08x",v);
++		v = p->min[i++]&255;
++		v <<= 8;
++		v |= p->min[i++]&255;
++		v <<= 8;
++		v |= p->min[i++]&255;
++		v <<= 8;
++		v |= p->min[i++]&255;
++		//ijpegd_log(h, C_LOG_DEBUG, fpo,"%08x",v);
++		min1 = v & 0xFFFFFFFF;
++		v = p->min[i++]&255;
++		v <<= 8;
++		v |= p->min[i++]&255;
++		v <<= 8;
++		v |= p->min[i++]&255;
++		v <<= 8;
++		v |= p->min[i++]&255;
++		min0 = v & 0xFFFFFFFF;
++
++
++		p->huffmin[i / 4 - 4] = min0;
++		p->huffmin[i / 4 - 3] = min1;
++		p->huffmin[i / 4 - 2] = min2;
++		p->huffmin[i / 4 - 1] = min3;
++	}
++
++	/* huffbase */
++	for(i = 0; i < 64; i++) {// hea
++		p->hea[i] = p->hea[i] & 0x1FF;
++	}
++	/* huffsymb */
++	for(i = 0; i < 336; i++) {
++		p->heb[i] = p->heb[i] & 0xFF;
++	}
++
++	for(i = 0; i < 4; i++) {
++		p->pxc[i] = (nblk[i] & 0x3) * ((nblk[i] & 0x30) >> 4) - 1;
++		p->pxc[i] = (p->pxc[i] & 0xf) << 4;
++		p->pxc[i] |= qt_sel[i] << 2 |
++			((ha_sel[i] & 0x1) << 1) |
++			((hd_sel[i] & 0x1) << 0);
++	}
++
++	ctx->header_size = pbuf - (unsigned char *)bs->va;
++
++	memcpy(bs->va, pbuf, bslen - ctx->header_size);
++	dma_sync_single_for_device(venc_ctx->dev->dev, bs->pa, bslen - ctx->header_size, DMA_TO_DEVICE);
++
++	return 0;
++}
++
++int jpeg_decoder_decode(struct jpgd_ctx *ctx, struct ingenic_vcodec_mem *bs, struct video_frame_buffer *frame)
++{
++	int ret = 0;
++
++	ctx->frame = frame;
++	ctx->bs = bs;
++
++	ret = jpgd_decode_header(ctx);
++
++	jpgd_fill_slice_info(ctx);
++	//dump_slice_info(ctx->s);
++
++	JPEGD_SliceInit(ctx->s);
++
++	ret = ingenic_vpu_start(ctx->priv);
++	if(ret < 0) {
++		return ret;
++	}
++
++	return ret;
++}
++
++
++int jpeg_decoder_set_fmt(struct jpgd_ctx *ctx, int width, int height, int format)
++{
++	struct jpgd_params *p = &ctx->p;
++	int ret = 0;
++
++	switch(format) {
++		case HELIX_NV12_MODE:
++		case HELIX_TILE_MODE:
++			p->format = format;
++			break;
++		default:
++			pr_err("Unsupported pix fmt: %x\n", format);
++			ret = -EINVAL;
++			break;
++	}
++
++	return ret;
++}
++
++
++int jpeg_decoder_alloc_workbuf(struct jpgd_ctx *ctx)
++{
++	struct ingenic_venc_ctx *venc_ctx = ctx->priv;
++	struct jpgd_params *p = &ctx->p;
++	int ret = 0;
++
++	ctx->desc = dma_alloc_coherent(venc_ctx->dev->dev, ctx->vdma_chain_len, &ctx->desc_pa, GFP_KERNEL);
++	if(!ctx->desc) {
++		pr_err("Failed to alloc desc memory!\n");
++		ret = -ENOMEM;
++		goto err_desc;
++	}
++
++
++	return ret;
++err_desc:
++	return ret;
++}
++int jpeg_decoder_free_workbuf(struct jpgd_ctx *ctx)
++{
++	struct ingenic_venc_ctx *venc_ctx = ctx->priv;
++	dma_free_coherent(venc_ctx->dev->dev, ctx->vdma_chain_len, ctx->desc, ctx->desc_pa);
++
++	return 0;
++}
++
++
++int jpeg_decoder_init(struct jpgd_ctx *ctx)
++{
++	struct jpgd_params *p = NULL;
++	_JPEGD_SliceInfo *s = NULL;
++
++
++	s = kzalloc(sizeof(_JPEGD_SliceInfo), GFP_KERNEL);
++	if(!s) {
++		return -ENOMEM;
++	}
++
++	p = &ctx->p;
++	ctx->s = s;
++	ctx->vdma_chain_len = 40960 + 256;
++
++	return 0;
++}
++
++
++int jpeg_decoder_deinit(struct jpgd_ctx *ctx)
++{
++	if(!ctx)
++		return 0;
++
++	if(ctx->s) {
++		kfree(ctx->s);
++	}
++
++
++	return 0;
++}
++
++void jpeg_decoder_set_priv(struct jpgd_ctx *ctx, void *data)
++{
++	ctx->priv = data;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpgd.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpgd.h
+new file mode 100644
+index 000000000..143fb9ea5
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpgd.h
+@@ -0,0 +1,54 @@
++#ifndef __JPGD_H__
++#define __JPGD_H__
++
++
++#include "api/helix_jpeg_dec.h"
++
++struct jpgd_params {
++	int hea[64];
++	int heb[336];
++	int huffmin[64];
++	int qt[4][64];
++
++	int huffenc[384];
++	int min[64];
++	unsigned int pxc[4];	/* component x config */
++
++	int width;
++	int height;
++	int format;	/*input format?*/
++};
++
++struct jpgd_ctx {
++	int vdma_chain_len;
++
++	unsigned int *desc;
++	dma_addr_t desc_pa;
++
++	struct video_frame_buffer *frame;	/* raw frame.*/
++	struct ingenic_vcodec_mem *bs;		/* output bs.*/
++
++	unsigned int header_size;		/*jpg header*/
++	unsigned int bslen;			/*decoder output bslen*/
++
++	struct jpgd_params p;
++	_JPEGD_SliceInfo *s;
++	void *priv;
++};
++
++
++extern int jpeg_decoder_decode(struct jpgd_ctx *ctx, struct ingenic_vcodec_mem *bs, struct video_frame_buffer *frame);
++
++extern int jpeg_decoder_set_fmt(struct jpgd_ctx *ctx, int width, int height, int format);
++
++extern int jpeg_decoder_alloc_workbuf(struct jpgd_ctx *ctx);
++
++extern int jpeg_decoder_free_workbuf(struct jpgd_ctx *ctx);
++
++extern int jpeg_decoder_init(struct jpgd_ctx *ctx);
++
++extern int jpeg_decoder_deinit(struct jpgd_ctx *ctx);
++
++extern void jpeg_decoder_set_priv(struct jpgd_ctx *ctx, void *data);
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpge.c b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpge.c
+new file mode 100644
+index 000000000..b23fd46e6
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpge.c
+@@ -0,0 +1,330 @@
++/*
++* Copyright© 2014 Ingenic Semiconductor Co.,Ltd
++*
++* Author: qipengzhen <aric.pzqi@ingenic.com>
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License version 2 as
++* published by the Free Software Foundation.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++* GNU General Public License for more details.
++*
++*/
++
++
++#include <linux/slab.h>
++#include <media/v4l2-mem2mem.h>
++
++
++#include "helix_buf.h"
++#include "helix_drv.h"
++
++#include "jpge.h"
++
++#include "jpge/ht.h"
++#include "jpge/qt.h"
++#include "jpge/head.h"
++
++static void __maybe_unused dump_slice_info(_JPEGE_SliceInfo *s)
++{
++	printk("s->des_va:	%08x\n", (unsigned int)s->des_va);
++	printk("s->des_pa:	%08x\n", s->des_pa);
++	printk("s->ncol:	%d\n", s->ncol);
++	printk("s->rsm:		%d\n", s->rsm);
++	printk("s->bsa:		%08x\n", s->bsa);
++	printk("s->p0a:		%08x\n", s->p0a);
++	printk("s->p1a:		%08x\n", s->p1a);
++	printk("s->nrsm:	%d\n", s->nrsm);
++	printk("s->raw[0]:	%08x\n", s->raw[0]);
++	printk("s->raw[1]:	%08x\n", s->raw[1]);
++	printk("s->raw[2]:	%08x\n", s->raw[2]);
++	printk("s->stride[0]:	%d\n", s->stride[0]);
++	printk("s->stride[1]:	%d\n", s->stride[1]);
++	printk("s->mb_height:	%d\n", s->mb_height);
++	printk("s->mb_width:	%d\n", s->mb_width);
++	printk("s->nmcu:	%d\n", s->nmcu);
++	printk("s->raw_format:	%d(%s)\n", s->raw_format,
++			s->raw_format == 8 ? "NV12" :
++			s->raw_format == 12 ? "NV21" :
++			s->raw_format == 0 ? "TILE(unsupported)" : "invalid");
++	printk("s->ql_sel:	%d(%s)\n", s->ql_sel,
++			s->ql_sel == LOW_QUALITY ? "low_quality":
++			s->ql_sel == MEDIUMS_QUALITY ? "mediums_quality":
++			s->ql_sel == HIGH_QUALITY ? "high_quality" : "invld");
++	printk("s->huffenc_sel:	%d\n", s->huffenc_sel);
++}
++
++static int jpge_fill_slice_info(struct jpge_ctx *ctx)
++{
++	struct jpge_params *p = &ctx->p;
++	_JPEGE_SliceInfo *s = ctx->s;
++	int ret = 0;
++
++	s->des_va = ctx->desc;
++	s->des_pa = ctx->desc_pa;
++
++	s->ncol = 2;	/* unused? */
++	s->rsm = 0;
++	s->bsa = ctx->bs->pa + ctx->header_size;
++	s->p0a = 0;
++	s->p1a = 0;
++	s->nrsm = 0;
++
++	s->raw[0] = ctx->frame->fb_addr[0].pa;	/*Y*/
++	s->raw[1] = ctx->frame->fb_addr[1].pa;	/*U for 420p or UV for nv12*/
++	s->raw[2] = ctx->frame->fb_addr[2].pa;	/*V for 420p*/
++
++	s->stride[0] = s->stride[1] = p->width;
++
++	s->mb_height = (p->height + 15) / 16;
++	s->mb_width = p->width / 16;
++	s->nmcu = s->mb_height * s->mb_width - 1;
++	s->raw_format = p->format;
++	s->ql_sel = p->compr_quality;
++	s->huffenc_sel = 0;	/*only one huffenc table?*/
++
++	return ret;
++}
++
++static int jpge_gen_header(struct jpge_ctx *ctx)
++{
++	struct ingenic_vcodec_mem *bs = ctx->bs;
++	struct jpge_params *p = &ctx->p;
++	int ql_sel = p->compr_quality;
++	char *pbuf = bs->va;
++	char *ptr = NULL;
++	int i,j;
++	int header_size;
++	int padsize;
++
++	/* SOI 文件开始 */
++	*pbuf++ = 0xff;
++	*pbuf++ = M_SOI;
++
++	/* DQT -- 0 */
++	*pbuf++ = 0xff;
++	*pbuf++ = M_DQT;
++	*pbuf++ = 0x0;
++	*pbuf++ = 0x43;
++	*pbuf++ = 0x0;
++
++	ptr = (char *)&qt[ql_sel][0];
++	for(i = 0; i < 64; i++)
++		*pbuf++ = *ptr++;
++
++	/* DQT -- 1*/
++	*pbuf++ = 0xff;
++	*pbuf++ = M_DQT;
++	*pbuf++ = 0;
++	*pbuf++ = 0x43;
++	*pbuf++ = 0x01;
++	for(i = 0; i < 64; i++) {
++		*pbuf++ = *ptr++;
++	}
++
++	/* SOF */
++	*pbuf++ = 0xff;
++	*pbuf++ = M_SOF0;
++	*pbuf++ = 0x0;
++	*pbuf++ = 0x11;				//Lf = 17
++	*pbuf++ = 8;				//8bit sample
++	*pbuf++ = (p->height & 0xff00) >> 8;	//Y=height
++	*pbuf++ = p->height & 0xff;
++	*pbuf++ = (p->width & 0xff00) >> 8;	//X=width
++	*pbuf++ = p->width & 0xff;
++	*pbuf++ = 3;				//Nf=3, number of component, Y U V
++	*pbuf++ = 1;				//采样系数, Component Y 设置.
++	*pbuf++ = 0x22;				//Hori:2 Vertical:2 水平采样系数和垂直采样系数.
++	*pbuf++ = 0x00;				//使用�化表0.
++	*pbuf++ = 2;				//Component Cb.
++	*pbuf++ = 0x11;				//H:1 V:1
++	*pbuf++ = 0x1;				//使用�化表1.
++	*pbuf++ = 3;				//Component Cr.
++	*pbuf++ = 0x11;				//H:1 V:1
++	*pbuf++ = 0x1;				//使用�化表1.
++
++	/* DHT -- lumia DC/AC, Chromia DC/AC */
++	for(j = 0; j < 4; j++) {
++		*pbuf++ = 0xff;
++		*pbuf++ = M_DHT;
++		*pbuf++ = (ht_size[j] & 0xff00) >> 8;	//ht_size
++		*pbuf++ = ht_size[j] & 0xff;
++		*pbuf++ = dht_sel[j];			//dht_sel; ?
++		for(i = 0; i < 16; i++) {
++			*pbuf++ = ht_len[j][i];
++		}
++
++		for(i = 0; i < 16; i++) {
++			int m;
++			for(m = 0; m < ht_len[j][i]; m++) {
++				*pbuf++ = ht_val[j][i][m];
++			}
++		}
++	}
++
++
++	/*添加0xff,填充header到256字节对�. 已知SOS 段14字节*/
++	header_size = pbuf - (char *)bs->va + 14;
++	padsize = 256 - header_size % 256;
++
++	memset(pbuf, 0xff, padsize);
++	pbuf += padsize;
++
++	//header_size = (header_size + 255) / 256 * 256; // align to 256;
++
++	/* SOS */
++	*pbuf++ = 0xff;
++	*pbuf++ = M_SOS;
++	//Ls = 12
++	*pbuf++ = 0x0;
++	*pbuf++ = 0xC;
++	//Ns
++	*pbuf++ = 0x3;
++	//Cs1 - Y
++	*pbuf++ = 0x1;
++	//Td, Ta
++	*pbuf++ = 0x00;
++	//Cs2 - U
++	*pbuf++ = 0x2;
++	//Td, Ta
++	*pbuf++ = 0x11;
++	//Cs3 - V
++	*pbuf++ = 0x3;
++	//Td, Ta
++	*pbuf++ = 0x11;
++	//Ss
++	*pbuf++ = 0x00;
++	//Se
++	*pbuf++ = 0x3f;
++	//Ah, Al
++	*pbuf++ = 0x0;
++
++	ctx->header_size = pbuf - (char *)bs->va;
++	return 0;
++}
++
++int jpeg_encoder_encode(struct jpge_ctx *ctx, struct video_frame_buffer *frame, struct ingenic_vcodec_mem *bs)
++{
++	int ret = 0;
++	char *pbuf = NULL;
++
++	ctx->frame = frame;
++	bs->va = (unsigned long)bs->va | 0xa0000000;	//使用uncache地�生�头信�.影�效率.
++	ctx->bs = bs;
++
++	ret = jpge_gen_header(ctx);
++
++	jpge_fill_slice_info(ctx);
++	//dump_slice_info(ctx->s);
++
++	JPEGE_SliceInit(ctx->s);
++
++	ret = ingenic_vpu_start(ctx->priv);
++	if(ret < 0) {
++		return ret;
++	}
++
++	/* Modify bslen.
++		total bslen = header_size + vpu encoded bslen.
++	*/
++	ctx->bslen = ctx->header_size + ctx->bslen;
++
++	pbuf = bs->va + ctx->bslen;
++	/* EOI */
++	*pbuf++ = 0xff;
++	*pbuf++ = 0xd9;
++
++	ctx->bslen += 2;
++
++	return ret;
++}
++
++
++int jpeg_encoder_set_fmt(struct jpge_ctx *ctx, int width, int height, int format)
++{
++	struct jpge_params *p = &ctx->p;
++	int ret = 0;
++
++	p->width = width;
++	p->height = height;
++
++	switch(format) {
++		case HELIX_NV12_MODE:
++		case HELIX_NV21_MODE:
++			p->format = format;
++			break;
++		default:
++			pr_err("Unsupported pix fmt: %x\n", format);
++			ret = -EINVAL;
++			break;
++	}
++
++	return ret;
++}
++
++
++int jpeg_encoder_alloc_workbuf(struct jpge_ctx *ctx)
++{
++	struct ingenic_venc_ctx *venc_ctx = ctx->priv;
++	int ret = 0;
++
++	ctx->desc = dma_alloc_coherent(venc_ctx->dev->dev, ctx->vdma_chain_len, &ctx->desc_pa, GFP_KERNEL);
++	if(!ctx->desc) {
++		pr_err("Failed to alloc desc memory!\n");
++		ret = -ENOMEM;
++		goto err_desc;
++	}
++
++
++	return ret;
++err_desc:
++	return ret;
++}
++
++int jpeg_encoder_free_workbuf(struct jpge_ctx *ctx)
++{
++	struct ingenic_venc_ctx *venc_ctx = ctx->priv;
++	dma_free_coherent(venc_ctx->dev->dev, ctx->vdma_chain_len, ctx->desc, ctx->desc_pa);
++
++	return 0;
++}
++
++
++int jpeg_encoder_init(struct jpge_ctx *ctx)
++{
++	struct jpge_params *p = NULL;
++	_JPEGE_SliceInfo *s = NULL;
++
++	s = kzalloc(sizeof(_JPEGE_SliceInfo), GFP_KERNEL);
++	if(!s) {
++		return -ENOMEM;
++	}
++
++	p = &ctx->p;
++	ctx->s = s;
++	ctx->vdma_chain_len = 40960 + 256;
++
++	return 0;
++}
++
++
++int jpeg_encoder_deinit(struct jpge_ctx *ctx)
++{
++	if(!ctx)
++		return 0;
++
++	if(ctx->s) {
++		kfree(ctx->s);
++	}
++
++
++	return 0;
++}
++
++void jpeg_encoder_set_priv(struct jpge_ctx *ctx, void *data)
++{
++	ctx->priv = data;
++}
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpge.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpge.h
+new file mode 100644
+index 000000000..d8d1a4f65
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpge.h
+@@ -0,0 +1,46 @@
++#ifndef __JPGE_H__
++#define __JPGE_H__
++
++#include "api/helix_jpeg_enc.h"
++
++struct jpge_params {
++	int compr_quality;
++
++	int width;
++	int height;
++	int format;	/*input format?*/
++};
++
++struct jpge_ctx {
++	int vdma_chain_len;
++
++	unsigned int *desc;
++	dma_addr_t desc_pa;
++
++	struct video_frame_buffer *frame;	/* raw frame.*/
++	struct ingenic_vcodec_mem *bs;		/* output bs.*/
++
++	unsigned int header_size;		/*jpg header*/
++	unsigned int bslen;			/*encoder output bslen*/
++
++	struct jpge_params p;
++	_JPEGE_SliceInfo *s;
++	void *priv;
++};
++
++
++extern int jpeg_encoder_encode(struct jpge_ctx *ctx, struct video_frame_buffer *frame, struct ingenic_vcodec_mem *bs);
++
++extern int jpeg_encoder_set_fmt(struct jpge_ctx *ctx, int width, int height, int format);
++
++extern int jpeg_encoder_alloc_workbuf(struct jpge_ctx *ctx);
++
++extern int jpeg_encoder_free_workbuf(struct jpge_ctx *ctx);
++
++extern int jpeg_encoder_init(struct jpge_ctx *ctx);
++
++extern int jpeg_encoder_deinit(struct jpge_ctx *ctx);
++
++extern void jpeg_encoder_set_priv(struct jpge_ctx *ctx, void *data);
++
++#endif
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpge/head.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpge/head.h
+new file mode 100644
+index 000000000..17d1188b9
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpge/head.h
+@@ -0,0 +1,72 @@
++#ifndef __HEAD_H__
++#define __HEAD_H__
++
++char dht_sel[] = {0x00, 0x10, 0x01, 0x11};
++
++typedef enum {			/* JPEG marker codes */
++	M_SOF0  = 0xc0,
++	M_SOF1  = 0xc1,
++	M_SOF2  = 0xc2,
++	M_SOF3  = 0xc3,
++
++	M_SOF5  = 0xc5,
++	M_SOF6  = 0xc6,
++	M_SOF7  = 0xc7,
++
++	M_JPG   = 0xc8,
++	M_SOF9  = 0xc9,
++	M_SOF10 = 0xca,
++	M_SOF11 = 0xcb,
++
++	M_SOF13 = 0xcd,
++	M_SOF14 = 0xce,
++	M_SOF15 = 0xcf,
++
++	M_DHT   = 0xc4,
++
++	M_DAC   = 0xcc,
++
++	M_RST0  = 0xd0,
++	M_RST1  = 0xd1,
++	M_RST2  = 0xd2,
++	M_RST3  = 0xd3,
++	M_RST4  = 0xd4,
++	M_RST5  = 0xd5,
++	M_RST6  = 0xd6,
++	M_RST7  = 0xd7,
++
++	M_SOI   = 0xd8,
++	M_EOI   = 0xd9,
++	M_SOS   = 0xda,
++	M_DQT   = 0xdb,
++	M_DNL   = 0xdc,
++	M_DRI   = 0xdd,
++	M_DHP   = 0xde,
++	M_EXP   = 0xdf,
++
++	M_APP0  = 0xe0,
++	M_APP1  = 0xe1,
++	M_APP2  = 0xe2,
++	M_APP3  = 0xe3,
++	M_APP4  = 0xe4,
++	M_APP5  = 0xe5,
++	M_APP6  = 0xe6,
++	M_APP7  = 0xe7,
++	M_APP8  = 0xe8,
++	M_APP9  = 0xe9,
++	M_APP10 = 0xea,
++	M_APP11 = 0xeb,
++	M_APP12 = 0xec,
++	M_APP13 = 0xed,
++	M_APP14 = 0xee,
++	M_APP15 = 0xef,
++
++	M_JPG0  = 0xf0,
++	M_JPG13 = 0xfd,
++	M_COM   = 0xfe,
++
++	M_TEM   = 0x01,
++
++	M_ERROR = 0x100
++} JPEG_MARKER;
++#endif /* __HEAD_H__ */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpge/ht.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpge/ht.h
+new file mode 100644
+index 000000000..addf25528
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpge/ht.h
+@@ -0,0 +1,90 @@
++#ifndef __HT_H__
++#define __HT_H__
++unsigned int ht_size[4] = {31, 181, 31, 181, };
++
++unsigned char ht_len[4][16] = {
++  {0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, },
++  {0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 125, },
++  {0, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, },
++  {0, 2, 1, 2, 4, 4, 3, 4, 7, 5, 4, 4, 0, 1, 2, 119, },
++};
++
++unsigned char ht_val[4][16][256] = {
++	{    {0},
++	     {0x00, },
++	     {0x01, 0x02, 0x03, 0x04, 0x05, },
++	     {0x06, },
++	     {0x07, },
++	     {0x08, },
++	     {0x09, },
++	     {0x0a, },
++	     {0x0b, },
++	     {0},
++	     {0},
++	     {0},
++	     {0},
++	     {0},
++	     {0},
++	     {0},
++	},
++	{    {0},
++	     {0x01, 0x02, },
++	     {0x03, },
++	     {0x00, 0x04, 0x11, },
++	     {0x05, 0x12, 0x21, },
++	     {0x31, 0x41, },
++	     {0x06, 0x13, 0x51, 0x61, },
++	     {0x07, 0x22, 0x71, },
++	     {0x14, 0x32, 0x81, 0x91, 0xa1, },
++	     {0x08, 0x23, 0x42, 0xb1, 0xc1, },
++	     {0x15, 0x52, 0xd1, 0xf0, },
++	     {0x24, 0x33, 0x62, 0x72, },
++	     {0},
++	     {0},
++	     {0x82, },
++	     {0x09, 0x0a, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a,
++	      0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x83, 0x84, 0x85, 0x86,
++	      0x87, 0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
++	      0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
++	      0xe8, 0xe9, 0xea, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, },
++	},
++	{    {0},
++	     {0x00, 0x01, 0x02, },
++	     {0x03, },
++	     {0x04, },
++	     {0x05, },
++	     {0x06, },
++	     {0x07, },
++	     {0x08, },
++	     {0x09, },
++	     {0x0a, },
++	     {0x0b, },
++	     {0},
++	     {0},
++	     {0},
++	     {0},
++	     {0},
++	},
++	{    {0},
++	     {0x00, 0x01, },
++	     {0x02, },
++	     {0x03, 0x11, },
++	     {0x04, 0x05, 0x21, 0x31, },
++	     {0x06, 0x12, 0x41, 0x51, },
++	     {0x07, 0x61, 0x71, },
++	     {0x13, 0x22, 0x32, 0x81, },
++	     {0x08, 0x14, 0x42, 0x91, 0xa1, 0xb1, 0xc1, },
++	     {0x09, 0x23, 0x33, 0x52, 0xf0, },
++	     {0x15, 0x62, 0x72, 0xd1, },
++	     {0x0a, 0x16, 0x24, 0x34, },
++	     {0},
++	     {0xe1, },
++	     {0x25, 0xf1, },
++	     {0x17, 0x18, 0x19, 0x1a, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x53, 0x54, 0x55, 0x56,
++	      0x57, 0x58, 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88,
++	      0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8,
++	      0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8,
++	      0xe9, 0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, },
++	},
++};
++#endif /* __HT_H__ */
+diff --git a/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpge/qt.h b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpge/qt.h
+new file mode 100644
+index 000000000..255abcd97
+--- /dev/null
++++ b/module_drivers/drivers/media/platform/ingenic-vcodec/helix/jpge/qt.h
+@@ -0,0 +1,58 @@
++unsigned char qt[3][128] = {
++	{
++		0x08,0x06,0x06,0x07,0x06,0x05,0x08,0x07,
++		0x07,0x07,0x09,0x09,0x08,0x0a,0x0c,0x14,
++		0x0d,0x0c,0x0b,0x0b,0x0c,0x19,0x12,0x13,
++		0x0f,0x14,0x1d,0x1a,0x1f,0x1e,0x1d,0x1a,
++		0x1c,0x1c,0x20,0x24,0x2e,0x27,0x20,0x22,
++		0x2c,0x23,0x1c,0x1c,0x28,0x37,0x29,0x2c,
++		0x30,0x31,0x34,0x34,0x34,0x1f,0x27,0x39,
++		0x3d,0x38,0x32,0x3c,0x2e,0x33,0x34,0x32,
++		0x09,0x09,0x09,0x0c,0x0b,0x0c,0x18,0x0d,
++		0x0d,0x18,0x32,0x21,0x1c,0x21,0x32,0x32,
++		0x32,0x32,0x32,0x32,0x32,0x32,0x32,0x32,
++		0x32,0x32,0x32,0x32,0x32,0x32,0x32,0x32,
++		0x32,0x32,0x32,0x32,0x32,0x32,0x32,0x32,
++		0x32,0x32,0x32,0x32,0x32,0x32,0x32,0x32,
++		0x32,0x32,0x32,0x32,0x32,0x32,0x32,0x32,
++		0x32,0x32,0x32,0x32,0x32,0x32,0x32,0x32,
++	},
++
++	{
++		0x06, 0x04, 0x04, 0x05, 0x04, 0x04, 0x06, 0x05,
++		0x05, 0x05, 0x06, 0x06, 0x06, 0x06, 0x08, 0x0d,
++		0x09, 0x08, 0x07, 0x07, 0x08, 0x0f, 0x0b, 0x0c,
++		0x09, 0x0d, 0x12, 0x10, 0x13, 0x13, 0x12, 0x10,
++		0x12, 0x11, 0x14, 0x16, 0x1c, 0x18, 0x14, 0x15,
++		0x1b, 0x15, 0x11, 0x12, 0x19, 0x21, 0x19, 0x1b,
++		0x1d, 0x1e, 0x20, 0x20, 0x20, 0x13, 0x18, 0x23,
++		0x25, 0x22, 0x1f, 0x25, 0x1c, 0x1f, 0x20, 0x1e,
++		0x06, 0x06, 0x06, 0x08, 0x07, 0x08, 0x0f, 0x09,
++		0x09, 0x0f, 0x1e, 0x15, 0x12, 0x15, 0x1e, 0x1e,
++		0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e,
++		0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e,
++		0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e,
++		0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e,
++		0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e,
++		0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e,
++	},
++
++	{
++		0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x03, 0x02,
++		0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x05,
++		0x04, 0x03, 0x03, 0x03, 0x03, 0x06, 0x04, 0x05,
++		0x04, 0x05, 0x07, 0x06, 0x07, 0x07, 0x07, 0x06,
++		0x07, 0x06, 0x07, 0x08, 0x0a, 0x09, 0x07, 0x08,
++		0x0a, 0x08, 0x06, 0x07, 0x09, 0x0c, 0x09, 0x0a,
++		0x0a, 0x0b, 0x0b, 0x0b, 0x0b, 0x07, 0x09, 0x0c,
++		0x0d, 0x0c, 0x0b, 0x0d, 0x0a, 0x0b, 0x0b, 0x0b,
++		0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x06, 0x04,
++		0x04, 0x06, 0x0b, 0x08, 0x07, 0x08, 0x0b, 0x0b,
++		0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b,
++		0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b,
++		0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b,
++		0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b,
++		0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b,
++		0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b,
++	}
++};
+diff --git a/module_drivers/drivers/media/v4l2-core/Kconfig b/module_drivers/drivers/media/v4l2-core/Kconfig
+new file mode 100644
+index 000000000..43af1cb6a
+--- /dev/null
++++ b/module_drivers/drivers/media/v4l2-core/Kconfig
+@@ -0,0 +1,12 @@
++config VIDEOBUF2_DMA_CONTIG_INGENIC
++        tristate
++        depends on HAS_DMA
++        select VIDEOBUF2_CORE
++        select VIDEOBUF2_MEMOPS
++        select DMA_SHARED_BUFFER
++
++
++config CAMERA_RESERVE_KB_SIZE
++        int "Reserve memory for camera noncoherent memory. Unit:KByte"
++        default 0
++        depends on VIDEOBUF2_DMA_CONTIG_INGENIC
+diff --git a/module_drivers/drivers/media/v4l2-core/Makefile b/module_drivers/drivers/media/v4l2-core/Makefile
+new file mode 100644
+index 000000000..ab7b95dd2
+--- /dev/null
++++ b/module_drivers/drivers/media/v4l2-core/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_VIDEOBUF2_DMA_CONTIG_INGENIC) += videobuf2-dma-contig-ingenic.o
+diff --git a/module_drivers/drivers/media/v4l2-core/videobuf2-dma-contig-ingenic.c b/module_drivers/drivers/media/v4l2-core/videobuf2-dma-contig-ingenic.c
+new file mode 100644
+index 000000000..b2674e58c
+--- /dev/null
++++ b/module_drivers/drivers/media/v4l2-core/videobuf2-dma-contig-ingenic.c
+@@ -0,0 +1,893 @@
++/*
++ * videobuf2-dma-contig.c - DMA contig memory allocator for videobuf2
++ *
++ * Copyright (C) 2010 Samsung Electronics
++ *
++ * Author: Pawel Osciak <pawel@osciak.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation.
++ */
++
++#include <linux/dma-buf.h>
++#include <linux/module.h>
++#include <linux/scatterlist.h>
++#include <linux/sched.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/dma-mapping.h>
++
++#include <media/videobuf2-v4l2.h>
++#include <media/videobuf2-dma-contig.h>
++#include <media/videobuf2-memops.h>
++#include <linux/vmalloc.h>
++struct reserve_memmg{
++	struct list_head list;
++	long start;
++	long size;
++
++};
++struct vb2_dc_conf {
++	struct device		*dev;
++	void *reserve_addr;
++	dma_addr_t reserve_phy_addr;
++	unsigned long reserve_size;
++	struct list_head top;
++};
++
++struct vb2_dc_buf {
++	struct device			*dev;
++	void				*vaddr;
++	unsigned long			size;
++	dma_addr_t			dma_addr;
++	enum dma_data_direction		dma_dir;
++	struct sg_table			*dma_sgt;
++	struct frame_vector		*vec;
++
++	/* MMAP related */
++	struct vb2_vmarea_handler	handler;
++	atomic_t			refcount;
++	struct sg_table			*sgt_base;
++
++	/* DMABUF related */
++	struct dma_buf_attachment	*db_attach;
++	struct reserve_memmg *rsvmem;
++};
++
++/*********************************************/
++/*        scatterlist table functions        */
++/*********************************************/
++
++
++static void vb2_dc_sgt_foreach_page(struct sg_table *sgt,
++	void (*cb)(struct page *pg))
++{
++	struct scatterlist *s;
++	unsigned int i;
++
++	for_each_sg(sgt->sgl, s, sgt->orig_nents, i) {
++		struct page *page = sg_page(s);
++		unsigned int n_pages = PAGE_ALIGN(s->offset + s->length)
++			>> PAGE_SHIFT;
++		unsigned int j;
++
++		for (j = 0; j < n_pages; ++j, ++page)
++			cb(page);
++	}
++}
++
++static unsigned long vb2_dc_get_contiguous_size(struct sg_table *sgt)
++{
++	struct scatterlist *s;
++	dma_addr_t expected = sg_dma_address(sgt->sgl);
++	unsigned int i;
++	unsigned long size = 0;
++
++	for_each_sg(sgt->sgl, s, sgt->nents, i) {
++		if (sg_dma_address(s) != expected)
++			break;
++		expected = sg_dma_address(s) + sg_dma_len(s);
++		size += sg_dma_len(s);
++	}
++	return size;
++}
++
++/*********************************************/
++/*         callbacks for all buffers         */
++/*********************************************/
++
++static void *vb2_dc_cookie(void *buf_priv)
++{
++	struct vb2_dc_buf *buf = buf_priv;
++
++	return &buf->dma_addr;
++}
++
++static void *vb2_dc_vaddr(void *buf_priv)
++{
++	struct vb2_dc_buf *buf = buf_priv;
++
++	if (!buf->vaddr && buf->db_attach)
++		buf->vaddr = dma_buf_vmap(buf->db_attach->dmabuf);
++
++	return buf->vaddr;
++}
++
++static unsigned int vb2_dc_num_users(void *buf_priv)
++{
++	struct vb2_dc_buf *buf = buf_priv;
++
++	return atomic_read(&buf->refcount);
++}
++
++static void vb2_dc_prepare(void *buf_priv)
++{
++	struct vb2_dc_buf *buf = buf_priv;
++	struct sg_table *sgt = buf->dma_sgt;
++
++	/* DMABUF exporter will flush the cache for us */
++	//if (!sgt || buf->db_attach)
++	if (buf->db_attach)
++		return;
++	if(!sgt)
++	{
++//		dma_sync_single_for_device(buf->dev,(unsigned long)buf->vaddr,buf->size,buf->dma_dir);
++		dma_sync_single_for_device(buf->dev,(unsigned long)buf->dma_addr,buf->size,buf->dma_dir);
++	}else {
++		dma_sync_sg_for_device(buf->dev, sgt->sgl, sgt->orig_nents, buf->dma_dir);
++	}
++}
++
++static void vb2_dc_finish(void *buf_priv)
++{
++	struct vb2_dc_buf *buf = buf_priv;
++	struct sg_table *sgt = buf->dma_sgt;
++
++	/* DMABUF exporter will flush the cache for us */
++	//if (!sgt || buf->db_attach)
++	if(buf->db_attach)
++		return;
++	if(!sgt)
++		dma_sync_single_for_device(buf->dev,(unsigned long)buf->dma_addr,buf->size,buf->dma_dir);
++	else
++		dma_sync_sg_for_cpu(buf->dev, sgt->sgl, sgt->orig_nents, buf->dma_dir);
++}
++
++/*********************************************/
++/*        callbacks for MMAP buffers         */
++/*********************************************/
++static void vb2_dc_put(void *buf_priv)
++{
++	struct vb2_dc_buf *buf = buf_priv;
++	if (!atomic_dec_and_test(&buf->refcount))
++		return;
++
++	if (buf->sgt_base) {
++		sg_free_table(buf->sgt_base);
++		kfree(buf->sgt_base);
++	}
++
++	if(buf->rsvmem)
++	{
++		list_del(&buf->rsvmem->list);
++		vfree(buf->rsvmem);
++	}else
++		dma_free_noncoherent(buf->dev, buf->size, buf->vaddr, buf->dma_addr, DMA_BIDIRECTIONAL);
++
++
++
++	put_device(buf->dev);
++	kfree(buf);
++}
++
++static struct reserve_memmg* reserve_mem_alloc(struct vb2_dc_conf *conf,int size)
++{
++	struct reserve_memmg *pos,*next,*alloc_list = NULL;
++
++	list_for_each_entry(pos,&conf->top,list){
++		if(!list_is_last(&pos->list,&conf->top))
++		{
++			next = list_entry(pos->list.next,struct reserve_memmg,list);
++			//printk("-->pos: %ld next: %ld\n",pos->start,next->start);
++			if(next->start - (pos->start + pos->size) >= size){
++				alloc_list = vzalloc(sizeof(struct reserve_memmg));
++				alloc_list->start = pos->start + pos->size;
++				alloc_list->size = size;
++				list_add(&alloc_list->list,&pos->list);
++				printk("->alloc: %ld\n",alloc_list->start);
++				return alloc_list;
++			}
++		}else break;
++	}
++	if(list_empty(&conf->top))
++	{
++		if(conf->reserve_size < size){
++			return 0;
++		}
++		alloc_list = vzalloc(sizeof(struct reserve_memmg));
++		alloc_list->start = 0;
++		alloc_list->size = size;
++		list_add(&alloc_list->list,&conf->top);
++		printk("first alloc: %ld\n",alloc_list->start);
++	}else{
++		if(conf->reserve_size - (pos->start + pos->size) < size)
++			return 0;
++		alloc_list = vzalloc(sizeof(struct reserve_memmg));
++
++		alloc_list->start = pos->start + pos->size;
++		alloc_list->size = size;
++		list_add_tail(&alloc_list->list,&conf->top);
++		printk("tail alloc: %ld\n",alloc_list->start);
++	}
++	return alloc_list;
++
++}
++static void *vb2_dc_alloc(struct device *dev, unsigned long attrs,
++				unsigned long size,
++				enum dma_data_direction dma_dir, gfp_t gfp_flags)
++{
++	struct vb2_dc_buf *buf;
++
++	buf = kzalloc(sizeof *buf, GFP_KERNEL);
++	if (!buf)
++		return ERR_PTR(-ENOMEM);
++
++#if 0
++	if(conf->reserve_size > 0){
++		struct reserve_memmg* m;
++		m = reserve_mem_alloc(conf,size);
++		if(m)
++		{
++			buf->vaddr = m->start + conf->reserve_addr;
++			buf->dma_addr = m->start + (unsigned long)conf->reserve_phy_addr;
++			buf->rsvmem = m;
++			printk("alloc addr %p\n",buf->vaddr);
++		}
++	}
++#endif
++	if(!buf->vaddr)
++	{
++		buf->vaddr = dma_alloc_noncoherent(dev, size, &buf->dma_addr, DMA_BIDIRECTIONAL,
++			GFP_KERNEL | gfp_flags);
++		if (!buf->vaddr) {
++			dev_err(dev, "dma_alloc_noncoherent of size %ld failed\n", size);
++			kfree(buf);
++			return ERR_PTR(-ENOMEM);
++		}
++	}
++	/* Prevent the device from being released while the buffer is used */
++	buf->dev = get_device(dev);
++	buf->size = size;
++	buf->dma_dir = dma_dir;
++
++	buf->handler.refcount = (refcount_t *)&buf->refcount;
++	buf->handler.put = vb2_dc_put;
++	buf->handler.arg = buf;
++
++	atomic_inc(&buf->refcount);
++
++	return buf;
++}
++
++int dma_common_mmap_cached(struct device *dev, struct vm_area_struct *vma,
++	void *cpu_addr, dma_addr_t dma_addr, size_t size)
++{
++	int ret = -ENXIO;
++#ifdef CONFIG_MMU
++	unsigned long user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
++	unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
++	unsigned long pfn = page_to_pfn(virt_to_page(cpu_addr));
++	unsigned long off = vma->vm_pgoff;
++
++//      vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
++	pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
++//    pgprot_val(vma->vm_page_prot) |= _CACHE_CACHABLE_WA; /* Write-Acceleration */
++	pgprot_val(vma->vm_page_prot) |= _CACHE_CACHABLE_NONCOHERENT;
++//	pgprot_val(vma->vm_page_prot) |= _CACHE_UNCACHED;
++//	printk(KERN_DEBUG "__videobuf_mmap_mapper() vma->vm_page_prot=%x cpu_addr:%p\n", vma->vm_page_prot,cpu_addr);
++
++	//if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
++	//	return ret;
++
++	if (off < count && user_count <= (count - off)) {
++		ret = remap_pfn_range(vma, vma->vm_start,
++			pfn + off,
++			user_count << PAGE_SHIFT,
++			vma->vm_page_prot);
++	}
++#endif  /* CONFIG_MMU */
++
++	return ret;
++}
++
++static int vb2_dc_mmap(void *buf_priv, struct vm_area_struct *vma)
++{
++	struct vb2_dc_buf *buf = buf_priv;
++	int ret;
++
++	if (!buf) {
++		printk(KERN_ERR "No buffer to map\n");
++		return -EINVAL;
++	}
++
++	/*
++	 * dma_mmap_* uses vm_pgoff as in-buffer offset, but we want to
++	 * map whole buffer
++	 */
++	vma->vm_pgoff = 0;
++
++	/* ret = dma_mmap_coherent(buf->dev, vma, buf->vaddr, */
++	/* 	buf->dma_addr, buf->size); */
++	ret = dma_common_mmap_cached(buf->dev, vma, buf->vaddr,
++		buf->dma_addr, buf->size);
++
++	if (ret) {
++		pr_err("Remapping memory failed, error: %d\n", ret);
++		return ret;
++	}
++
++	vma->vm_flags		|= VM_DONTEXPAND | VM_DONTDUMP;
++	vma->vm_private_data	= &buf->handler;
++	vma->vm_ops		= &vb2_common_vm_ops;
++
++	vma->vm_ops->open(vma);
++
++	pr_debug("%s: mapped dma addr 0x%08lx at 0x%08lx, size %ld\n",
++		__func__, (unsigned long)buf->dma_addr, vma->vm_start,
++		buf->size);
++
++	return 0;
++}
++
++/*********************************************/
++/*         DMABUF ops for exporters          */
++/*********************************************/
++
++struct vb2_dc_attachment {
++	struct sg_table sgt;
++	enum dma_data_direction dma_dir;
++};
++
++static int vb2_dc_dmabuf_ops_attach(struct dma_buf *dbuf, struct dma_buf_attachment *dbuf_attach)
++{
++	struct vb2_dc_attachment *attach;
++	unsigned int i;
++	struct scatterlist *rd, *wr;
++	struct sg_table *sgt;
++	struct vb2_dc_buf *buf = dbuf->priv;
++	int ret;
++
++	attach = kzalloc(sizeof(*attach), GFP_KERNEL);
++	if (!attach)
++		return -ENOMEM;
++
++	sgt = &attach->sgt;
++	/* Copy the buf->base_sgt scatter list to the attachment, as we can't
++	 * map the same scatter list to multiple attachments at the same time.
++	 */
++	ret = sg_alloc_table(sgt, buf->sgt_base->orig_nents, GFP_KERNEL);
++	if (ret) {
++		kfree(attach);
++		return -ENOMEM;
++	}
++
++	rd = buf->sgt_base->sgl;
++	wr = sgt->sgl;
++	for (i = 0; i < sgt->orig_nents; ++i) {
++		sg_set_page(wr, sg_page(rd), rd->length, rd->offset);
++		rd = sg_next(rd);
++		wr = sg_next(wr);
++	}
++
++	attach->dma_dir = DMA_NONE;
++	dbuf_attach->priv = attach;
++
++	return 0;
++}
++
++static void vb2_dc_dmabuf_ops_detach(struct dma_buf *dbuf,
++	struct dma_buf_attachment *db_attach)
++{
++	struct vb2_dc_attachment *attach = db_attach->priv;
++	struct sg_table *sgt;
++
++	if (!attach)
++		return;
++
++	sgt = &attach->sgt;
++
++	/* release the scatterlist cache */
++	if (attach->dma_dir != DMA_NONE)
++		dma_unmap_sg(db_attach->dev, sgt->sgl, sgt->orig_nents,
++			attach->dma_dir);
++	sg_free_table(sgt);
++	kfree(attach);
++	db_attach->priv = NULL;
++}
++
++static struct sg_table *vb2_dc_dmabuf_ops_map(
++	struct dma_buf_attachment *db_attach, enum dma_data_direction dma_dir)
++{
++	struct vb2_dc_attachment *attach = db_attach->priv;
++	/* stealing dmabuf mutex to serialize map/unmap operations */
++	struct mutex *lock = &db_attach->dmabuf->lock;
++	struct sg_table *sgt;
++
++	mutex_lock(lock);
++
++	sgt = &attach->sgt;
++	/* return previously mapped sg table */
++	if (attach->dma_dir == dma_dir) {
++		mutex_unlock(lock);
++		return sgt;
++	}
++
++	/* release any previous cache */
++	if (attach->dma_dir != DMA_NONE) {
++		dma_unmap_sg(db_attach->dev, sgt->sgl, sgt->orig_nents,
++			attach->dma_dir);
++		attach->dma_dir = DMA_NONE;
++	}
++
++	/* mapping to the client with new direction */
++	sgt->nents = dma_map_sg(db_attach->dev, sgt->sgl, sgt->orig_nents,
++				dma_dir);
++	if (!sgt->nents) {
++		pr_err("failed to map scatterlist\n");
++		mutex_unlock(lock);
++		return ERR_PTR(-EIO);
++	}
++
++	attach->dma_dir = dma_dir;
++
++	mutex_unlock(lock);
++
++	return sgt;
++}
++
++static void vb2_dc_dmabuf_ops_unmap(struct dma_buf_attachment *db_attach,
++	struct sg_table *sgt, enum dma_data_direction dma_dir)
++{
++	/* nothing to be done here */
++}
++
++static void vb2_dc_dmabuf_ops_release(struct dma_buf *dbuf)
++{
++	/* drop reference obtained in vb2_dc_get_dmabuf */
++	vb2_dc_put(dbuf->priv);
++}
++
++static void *vb2_dc_dmabuf_ops_kmap(struct dma_buf *dbuf, unsigned long pgnum)
++{
++	struct vb2_dc_buf *buf = dbuf->priv;
++
++	return buf->vaddr + pgnum * PAGE_SIZE;
++}
++
++static void *vb2_dc_dmabuf_ops_vmap(struct dma_buf *dbuf)
++{
++	struct vb2_dc_buf *buf = dbuf->priv;
++
++	return buf->vaddr;
++}
++
++static int vb2_dc_dmabuf_ops_mmap(struct dma_buf *dbuf,
++	struct vm_area_struct *vma)
++{
++	return vb2_dc_mmap(dbuf->priv, vma);
++}
++
++static struct dma_buf_ops vb2_dc_dmabuf_ops = {
++	.attach = vb2_dc_dmabuf_ops_attach,
++	.detach = vb2_dc_dmabuf_ops_detach,
++	.map_dma_buf = vb2_dc_dmabuf_ops_map,
++	.unmap_dma_buf = vb2_dc_dmabuf_ops_unmap,
++	.vmap = vb2_dc_dmabuf_ops_vmap,
++	.mmap = vb2_dc_dmabuf_ops_mmap,
++	.release = vb2_dc_dmabuf_ops_release,
++};
++
++static struct sg_table *vb2_dc_get_base_sgt(struct vb2_dc_buf *buf)
++{
++	int ret;
++	struct sg_table *sgt;
++
++	sgt = kmalloc(sizeof(*sgt), GFP_KERNEL);
++	if (!sgt) {
++		dev_err(buf->dev, "failed to alloc sg table\n");
++		return NULL;
++	}
++
++	ret = dma_get_sgtable(buf->dev, sgt, buf->vaddr, buf->dma_addr,
++		buf->size);
++	if (ret < 0) {
++		dev_err(buf->dev, "failed to get scatterlist from DMA API\n");
++		kfree(sgt);
++		return NULL;
++	}
++
++	return sgt;
++}
++
++static struct dma_buf *vb2_dc_get_dmabuf(void *buf_priv, unsigned long flags)
++{
++	struct vb2_dc_buf *buf = buf_priv;
++	struct dma_buf *dbuf;
++	DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
++
++	exp_info.ops = &vb2_dc_dmabuf_ops;
++	exp_info.size = buf->size;
++	exp_info.flags = flags;
++	exp_info.priv = buf;
++
++	if (!buf->sgt_base)
++		buf->sgt_base = vb2_dc_get_base_sgt(buf);
++
++	if (WARN_ON(!buf->sgt_base))
++		return NULL;
++
++	dbuf = dma_buf_export(&exp_info);
++	if (IS_ERR(dbuf))
++		return NULL;
++
++	/* dmabuf keeps reference to vb2 buffer */
++	atomic_inc(&buf->refcount);
++
++	return dbuf;
++}
++
++/*********************************************/
++/*       callbacks for USERPTR buffers       */
++/*********************************************/
++
++static void vb2_dc_put_userptr(void *buf_priv)
++{
++	struct vb2_dc_buf *buf = buf_priv;
++	struct sg_table *sgt = buf->dma_sgt;
++	int i;
++	struct page **pages;
++
++	if (sgt) {
++		unsigned long attrs = 0;
++
++		attrs = DMA_ATTR_SKIP_CPU_SYNC;
++		/*
++		 * No need to sync to CPU, it's already synced to the CPU
++		 * since the finish() memop will have been called before this.
++		 */
++		dma_unmap_sg_attrs(buf->dev, sgt->sgl, sgt->orig_nents,
++				   buf->dma_dir, attrs);
++		pages = frame_vector_pages(buf->vec);
++		/* sgt should exist only if vector contains pages... */
++		BUG_ON(IS_ERR(pages));
++		for (i = 0; i < frame_vector_count(buf->vec); i++)
++			set_page_dirty_lock(pages[i]);
++		sg_free_table(sgt);
++		kfree(sgt);
++	}
++	vb2_destroy_framevec(buf->vec);
++	kfree(buf);
++}
++
++/*
++ * For some kind of reserved memory there might be no struct page available,
++ * so all that can be done to support such 'pages' is to try to convert
++ * pfn to dma address or at the last resort just assume that
++ * dma address == physical address (like it has been assumed in earlier version
++ * of videobuf2-dma-contig
++ */
++
++#ifdef __arch_pfn_to_dma
++static inline dma_addr_t vb2_dc_pfn_to_dma(struct device *dev, unsigned long pfn)
++{
++	return (dma_addr_t)__arch_pfn_to_dma(dev, pfn);
++}
++#elif defined(__pfn_to_bus)
++static inline dma_addr_t vb2_dc_pfn_to_dma(struct device *dev, unsigned long pfn)
++{
++	return (dma_addr_t)__pfn_to_bus(pfn);
++}
++#elif defined(__pfn_to_phys)
++static inline dma_addr_t vb2_dc_pfn_to_dma(struct device *dev, unsigned long pfn)
++{
++	return (dma_addr_t)__pfn_to_phys(pfn);
++}
++#else
++static inline dma_addr_t vb2_dc_pfn_to_dma(struct device *dev, unsigned long pfn)
++{
++	/* really, we cannot do anything better at this point */
++	return (dma_addr_t)(pfn) << PAGE_SHIFT;
++}
++#endif
++
++static void *vb2_dc_get_userptr(struct device *dev, unsigned long vaddr,
++	unsigned long size, enum dma_data_direction dma_dir)
++{
++	struct vb2_dc_buf *buf;
++	struct frame_vector *vec;
++	unsigned long offset;
++	int n_pages, i;
++	int ret = 0;
++	struct sg_table *sgt;
++	unsigned long contig_size;
++	unsigned long dma_align = dma_get_cache_alignment();
++	unsigned long attrs = 0;
++
++	attrs = DMA_ATTR_SKIP_CPU_SYNC;
++
++	/* Only cache aligned DMA transfers are reliable */
++	if (!IS_ALIGNED(vaddr | size, dma_align)) {
++		pr_debug("user data must be aligned to %lu bytes\n", dma_align);
++		return ERR_PTR(-EINVAL);
++	}
++
++	if (!size) {
++		pr_debug("size is zero\n");
++		return ERR_PTR(-EINVAL);
++	}
++
++	buf = kzalloc(sizeof *buf, GFP_KERNEL);
++	if (!buf)
++		return ERR_PTR(-ENOMEM);
++
++	buf->dev = dev;
++	buf->dma_dir = dma_dir;
++
++	offset = vaddr & ~PAGE_MASK;
++	vec = vb2_create_framevec(vaddr, size);
++	if (IS_ERR(vec)) {
++		ret = PTR_ERR(vec);
++		goto fail_buf;
++	}
++	buf->vec = vec;
++	n_pages = frame_vector_count(vec);
++	ret = frame_vector_to_pages(vec);
++	if (ret < 0) {
++		unsigned long *nums = frame_vector_pfns(vec);
++
++		/*
++		 * Failed to convert to pages... Check the memory is physically
++		 * contiguous and use direct mapping
++		 */
++		for (i = 1; i < n_pages; i++)
++			if (nums[i-1] + 1 != nums[i])
++				goto fail_pfnvec;
++		buf->dma_addr = vb2_dc_pfn_to_dma(buf->dev, nums[0]);
++		goto out;
++	}
++
++	sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
++	if (!sgt) {
++		pr_err("failed to allocate sg table\n");
++		ret = -ENOMEM;
++		goto fail_pfnvec;
++	}
++
++	ret = sg_alloc_table_from_pages(sgt, frame_vector_pages(vec), n_pages,
++		offset, size, GFP_KERNEL);
++	if (ret) {
++		pr_err("failed to initialize sg table\n");
++		goto fail_sgt;
++	}
++
++	/*
++	 * No need to sync to the device, this will happen later when the
++	 * prepare() memop is called.
++	 */
++	sgt->nents = dma_map_sg_attrs(buf->dev, sgt->sgl, sgt->orig_nents,
++				      buf->dma_dir, attrs);
++	if (sgt->nents <= 0) {
++		pr_err("failed to map scatterlist\n");
++		ret = -EIO;
++		goto fail_sgt_init;
++	}
++
++	contig_size = vb2_dc_get_contiguous_size(sgt);
++	if (contig_size < size) {
++		pr_err("contiguous mapping is too small %lu/%lu\n",
++			contig_size, size);
++		ret = -EFAULT;
++		goto fail_map_sg;
++	}
++
++	buf->dma_addr = sg_dma_address(sgt->sgl);
++	buf->dma_sgt = sgt;
++out:
++	buf->size = size;
++
++	return buf;
++
++fail_map_sg:
++	dma_unmap_sg_attrs(buf->dev, sgt->sgl, sgt->orig_nents,
++			   buf->dma_dir, attrs);
++
++fail_sgt_init:
++	sg_free_table(sgt);
++
++fail_sgt:
++	kfree(sgt);
++
++fail_pfnvec:
++	vb2_destroy_framevec(vec);
++
++fail_buf:
++	kfree(buf);
++
++	return ERR_PTR(ret);
++}
++
++/*********************************************/
++/*       callbacks for DMABUF buffers        */
++/*********************************************/
++
++static int vb2_dc_map_dmabuf(void *mem_priv)
++{
++	struct vb2_dc_buf *buf = mem_priv;
++	struct sg_table *sgt;
++	unsigned long contig_size;
++
++	if (WARN_ON(!buf->db_attach)) {
++		pr_err("trying to pin a non attached buffer\n");
++		return -EINVAL;
++	}
++
++	if (WARN_ON(buf->dma_sgt)) {
++		pr_err("dmabuf buffer is already pinned\n");
++		return 0;
++	}
++
++	/* get the associated scatterlist for this buffer */
++	sgt = dma_buf_map_attachment(buf->db_attach, buf->dma_dir);
++	if (IS_ERR(sgt)) {
++		pr_err("Error getting dmabuf scatterlist\n");
++		return -EINVAL;
++	}
++
++	/* checking if dmabuf is big enough to store contiguous chunk */
++	contig_size = vb2_dc_get_contiguous_size(sgt);
++	if (contig_size < buf->size) {
++		pr_err("contiguous chunk is too small %lu/%lu b\n",
++			contig_size, buf->size);
++		dma_buf_unmap_attachment(buf->db_attach, sgt, buf->dma_dir);
++		return -EFAULT;
++	}
++
++	buf->dma_addr = sg_dma_address(sgt->sgl);
++	buf->dma_sgt = sgt;
++	buf->vaddr = NULL;
++
++	return 0;
++}
++
++static void vb2_dc_unmap_dmabuf(void *mem_priv)
++{
++	struct vb2_dc_buf *buf = mem_priv;
++	struct sg_table *sgt = buf->dma_sgt;
++
++	if (WARN_ON(!buf->db_attach)) {
++		pr_err("trying to unpin a not attached buffer\n");
++		return;
++	}
++
++	if (WARN_ON(!sgt)) {
++		pr_err("dmabuf buffer is already unpinned\n");
++		return;
++	}
++
++	if (buf->vaddr) {
++		dma_buf_vunmap(buf->db_attach->dmabuf, buf->vaddr);
++		buf->vaddr = NULL;
++	}
++	dma_buf_unmap_attachment(buf->db_attach, sgt, buf->dma_dir);
++
++	buf->dma_addr = 0;
++	buf->dma_sgt = NULL;
++}
++
++static void vb2_dc_detach_dmabuf(void *mem_priv)
++{
++	struct vb2_dc_buf *buf = mem_priv;
++
++	/* if vb2 works correctly you should never detach mapped buffer */
++	if (WARN_ON(buf->dma_addr))
++		vb2_dc_unmap_dmabuf(buf);
++
++	/* detach this attachment */
++	dma_buf_detach(buf->db_attach->dmabuf, buf->db_attach);
++	kfree(buf);
++}
++
++static void *vb2_dc_attach_dmabuf(struct device *dev, struct dma_buf *dbuf,
++	unsigned long size, enum dma_data_direction dma_dir)
++{
++	struct vb2_dc_buf *buf;
++	struct dma_buf_attachment *dba;
++
++	if (dbuf->size < size)
++		return ERR_PTR(-EFAULT);
++
++	buf = kzalloc(sizeof(*buf), GFP_KERNEL);
++	if (!buf)
++		return ERR_PTR(-ENOMEM);
++
++	buf->dev = dev;
++	/* create attachment for the dmabuf with the user device */
++	dba = dma_buf_attach(dbuf, buf->dev);
++	if (IS_ERR(dba)) {
++		pr_err("failed to attach dmabuf\n");
++		kfree(buf);
++		return dba;
++	}
++
++	buf->dma_dir = dma_dir;
++	buf->size = size;
++	buf->db_attach = dba;
++
++	return buf;
++}
++
++/*********************************************/
++/*       DMA CONTIG exported functions       */
++/*********************************************/
++
++const struct vb2_mem_ops ingenic_vb2_dma_contig_memops = {
++	.alloc		= vb2_dc_alloc,
++	.put		= vb2_dc_put,
++	.get_dmabuf	= vb2_dc_get_dmabuf,
++	.cookie		= vb2_dc_cookie,
++	.vaddr		= vb2_dc_vaddr,
++	.mmap		= vb2_dc_mmap,
++	.get_userptr	= vb2_dc_get_userptr,
++	.put_userptr	= vb2_dc_put_userptr,
++	.prepare	= vb2_dc_prepare,
++	.finish		= vb2_dc_finish,
++	.map_dmabuf	= vb2_dc_map_dmabuf,
++	.unmap_dmabuf	= vb2_dc_unmap_dmabuf,
++	.attach_dmabuf	= vb2_dc_attach_dmabuf,
++	.detach_dmabuf	= vb2_dc_detach_dmabuf,
++	.num_users	= vb2_dc_num_users,
++};
++EXPORT_SYMBOL_GPL(ingenic_vb2_dma_contig_memops);
++
++static int reserve_size = CONFIG_CAMERA_RESERVE_KB_SIZE; //unit: kb.
++static int __init set_camera_reserve(char *str)
++{
++	reserve_size = simple_strtoul(str, &str, 0);
++	return 1;
++}
++
++__setup("camera_reserve", set_camera_reserve);
++
++
++void *ingenic_vb2_dma_contig_init_ctx(struct device *dev)
++{
++	struct vb2_dc_conf *conf;
++
++	conf = kzalloc(sizeof *conf, GFP_KERNEL);
++	if (!conf)
++		return ERR_PTR(-ENOMEM);
++
++	conf->dev = dev;
++	if(reserve_size > 0){
++		conf->reserve_addr = dma_alloc_noncoherent(dev, reserve_size * 1024, &conf->reserve_phy_addr, DMA_BIDIRECTIONAL, GFP_KERNEL);
++		if(conf->reserve_addr)
++			conf->reserve_size = reserve_size * 1024;
++		printk("camera reserve memory size %dKByte Addr:%p\n",reserve_size,conf->reserve_addr);
++	}
++
++	INIT_LIST_HEAD(&conf->top);
++	return conf;
++}
++EXPORT_SYMBOL_GPL(ingenic_vb2_dma_contig_init_ctx);
++
++void ingenic_vb2_dma_contig_cleanup_ctx(void *alloc_ctx)
++{
++	if (!IS_ERR_OR_NULL(alloc_ctx))
++		kfree(alloc_ctx);
++}
++EXPORT_SYMBOL_GPL(ingenic_vb2_dma_contig_cleanup_ctx);
++
++MODULE_DESCRIPTION("DMA-contig memory handling routines for videobuf2");
++MODULE_AUTHOR("Pawel Osciak <pawel@osciak.com>");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/mfd/Kconfig b/module_drivers/drivers/mfd/Kconfig
+new file mode 100644
+index 000000000..4e365ce9c
+--- /dev/null
++++ b/module_drivers/drivers/mfd/Kconfig
+@@ -0,0 +1,75 @@
++config MFD_INGENIC_SADC_V13
++	tristate "[SADC] Support for the Ingenic SADC core"
++	select MFD_CORE
++	depends on MACH_XBURST || MACH_XBURST2
++	help
++	  Say yes here if you want support for the SADC unit in the Ingenic SoC.
++	  This driver is necessary for Ingenic_battery driver.
++
++config MFD_INGENIC_SADC_AUX
++	tristate "[SADC] Support for the Ingenic SADC AUX"
++	select MFD_CORE
++	depends on MACH_XBURST || MACH_XBURST2
++	help
++	  Say yes here if you want support for the SADC unit in the Ingenic SoC.
++	  This driver is necessary for ingenic_battery driver.
++if MFD_INGENIC_SADC_AUX
++	config SADC_AUX_VERF_3V3
++	bool "Ingenic sadc aux reference voltage 3.3V."
++	depends on SOC_X1600
++	default y
++	help
++	  Select ingenic sadc reference voltage.
++
++	config SADC_AUX_VERF_1V8
++	bool "Ingenic sadc aux reference voltage 1.8V."
++	depends on SOC_X2000_V12 || SOC_M300 || SOC_X2100 || SOC_X2500
++	default y
++	help
++	  Select ingenic sadc reference voltage.
++
++
++	config SADC_AUX_12BIT
++	bool "ingenic sadc aux 12bit"
++	depends on SOC_X2500 || SOC_X1600
++	default y
++
++	config SADC_AUX_10BIT
++	bool "ingenic sadc aux 10bit"
++	depends on SOC_X2000_V12 || SOC_M300 || SOC_X2100
++	default y
++endif
++
++config MFD_INGENIC_TCU
++	bool "[TCU] Ingenic tcu driver"
++	select MFD_CORE
++	select GENERIC_IRQ_CHIP
++	depends on SOC_X2000_V12 || SOC_X2000 || SOC_M300 || SOC_X2100 || SOC_X1600
++	help
++	  Say yes here if you want support for the TCU unit in the ingenic SoC.
++	  This driver is necessary for ingenic pwm or counter.
++
++config MFD_INGENIC_TCU_V1
++	bool "[TCU] Ingenic tcu driver v1"
++	select MFD_CORE
++	select GENERIC_IRQ_CHIP
++	depends on SOC_X2500
++	default n
++	help
++	  Say yes here if you want support for the TCU unit in the ingenic SoC.
++	  This driver is necessary for ingenic pwm or counter.
++
++
++config MFD_RICOH619
++	bool "Ricoh RC5T619 Power Management system device"
++	depends on I2C=y
++	select MFD_CORE
++	select REGMAP_I2C
++	help
++	  Select this option to get support for the RICOH619 Power
++	  Management system device.
++	  This driver provides common support for accessing the device
++	  through i2c interface. The device supports multiple sub-devices
++	  like GPIO, interrupts, RTC, LDO and DCDC regulators, onkey.
++	  Additional drivers must be enabled in order to use the
++	  different functionality of the device.
+diff --git a/module_drivers/drivers/mfd/Makefile b/module_drivers/drivers/mfd/Makefile
+new file mode 100644
+index 000000000..925a35cce
+--- /dev/null
++++ b/module_drivers/drivers/mfd/Makefile
+@@ -0,0 +1,5 @@
++obj-$(CONFIG_MFD_RICOH619)      += ricoh619.o ricoh619-irq.o
++obj-$(CONFIG_MFD_INGENIC_SADC_V13)      += ingenic_adc_v13.o
++obj-$(CONFIG_MFD_INGENIC_SADC_AUX)      += ingenic_adc_aux.o
++obj-$(CONFIG_MFD_INGENIC_TCU)   += ingenic-tcu.o
++obj-$(CONFIG_MFD_INGENIC_TCU_V1)        += ingenic-tcu_v1.o
+diff --git a/module_drivers/drivers/mfd/ingenic-tcu.c b/module_drivers/drivers/mfd/ingenic-tcu.c
+new file mode 100644
+index 000000000..d6b935539
+--- /dev/null
++++ b/module_drivers/drivers/mfd/ingenic-tcu.c
+@@ -0,0 +1,908 @@
++/*
++ * ingenic_tcu.c - ingenic Soc TCU MFD driver.
++ *
++ * Copyright (C) 2020 Ingenic Semiconductor Co., Ltd.
++ * Written by wssong <wenshuo.song@ingenic.com>.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <irq.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/ctype.h>
++#include <linux/syscore_ops.h>
++#include <linux/mutex.h>
++#include <asm/div64.h>
++#include <linux/mfd/core.h>
++#include <linux/mfd/ingenic-tcu_v2.h>
++#include <linux/clk.h>
++
++#define NR_TCU_CHNS TCU_NR_IRQS
++
++#define DE_WARNING	0
++
++
++static inline void ingenic_tcu_full_mask(struct ingenic_tcu_chn *tcu_chn);
++static inline void ingenic_tcu_half_mask(struct ingenic_tcu_chn *tcu_chn);
++
++static struct ingenic_tcu_chn g_tcu_chn[NR_TCU_CHNS] = {{0}};
++
++/*Timer Counter Enable/Disable Register*/
++static inline void ingenic_tcu_set_enable(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_writel(tcu_chn->tcu, TCU_TESR, 1 << tcu_chn->index);
++}
++
++static inline void ingenic_tcu_set_disable(struct ingenic_tcu_chn *tcu_chn)
++{
++	u32 tcsr;
++
++	spin_lock(&tcu_chn->tcu->lock);
++	ingenic_tcu_full_mask(tcu_chn);
++	ingenic_tcu_half_mask(tcu_chn);
++	tcu_writel(tcu_chn->tcu, TCU_TECR, 1 << tcu_chn->index);
++	if ((tcu_chn->capture_num & CAPTURE_LOOP_FLAGS) != 0) {
++		tcsr = tcu_readl(tcu_chn->tcu,CHN_CAP(tcu_chn->index)) & ~CAP_NUM_MSK;
++		tcu_writel(tcu_chn->tcu,CHN_CAP(tcu_chn->index),tcsr);
++	}
++
++	tcu_chn->en_flag = 0;
++	spin_unlock(&tcu_chn->tcu->lock);
++}
++
++/*Timer Stop Set/Clr Register*/
++static inline void ingenic_tcu_set_stop(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_writel(tcu_chn->tcu, TCU_TSSR, 1 << tcu_chn->index);
++}
++
++static inline void ingenic_tcu_clr_stop(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_writel(tcu_chn->tcu, TCU_TSCR, 1 << tcu_chn->index);
++}
++
++/*Timer Mast Register set/clr operation and flag clr operation (full)*/
++static inline void ingenic_tcu_full_mask(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_writel(tcu_chn->tcu, TCU_TMSR, 1 << tcu_chn->index);
++}
++
++static inline void ingenic_tcu_full_unmask(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_writel(tcu_chn->tcu, TCU_TMCR, 1 << tcu_chn->index);
++}
++
++static inline void ingenic_tcu_clear_full_flag(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_writel(tcu_chn->tcu, TCU_TFCR, 1 << tcu_chn->index);
++}
++
++/*Timer Mast Register set/clr operation and flag clr operation (half)*/
++static inline void ingenic_tcu_half_mask(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_writel(tcu_chn->tcu, TCU_TMSR, 1 << (tcu_chn->index + 16));
++}
++
++static inline void ingenic_tcu_half_unmask(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_writel(tcu_chn->tcu, TCU_TMCR, 1 << (tcu_chn->index + 16));
++}
++
++static inline void ingenic_tcu_clear_half_flag(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_writel(tcu_chn->tcu, TCU_TFCR, 1 << (tcu_chn->index + 16));
++}
++
++/*Timer Control Register select the TCNT count clock frequency*/
++static inline void ingenic_tcu_set_prescale(struct ingenic_tcu_chn *tcu_chn, enum tcu_prescale prescale)
++{
++	u32 tcsr = tcu_chn_readl(tcu_chn, CHN_TCSR) & ~CSR_DIV_MSK;
++	tcu_chn_writel(tcu_chn, CHN_TCSR, tcsr | (prescale << 3));
++}
++
++/*Timer Counter clear to zero*/
++static inline void ingenic_tcu_clear_tcnt(struct ingenic_tcu_chn *tcu_chn)
++{
++	tcu_chn_writel(tcu_chn, CHN_TCNT, 0);
++}
++
++/*Timer Data FULL/HALF Register*/
++static inline void ingenic_tcu_set_chn_full(struct ingenic_tcu_chn *tcu_chn, unsigned int value)
++{
++	tcu_chn_writel(tcu_chn, CHN_TDFR, value);
++}
++
++static inline void ingenic_tcu_set_chn_half(struct ingenic_tcu_chn *tcu_chn, unsigned int value)
++{
++	tcu_chn_writel(tcu_chn, CHN_TDHR, value);
++}
++
++/*Timer Control Register set count mode */
++static inline void ingenic_tcu_set_count_mode(struct ingenic_tcu_chn *tcu_chn, enum tcu_count_mode count_mode)
++{
++	u32 tcsr = tcu_chn_readl(tcu_chn, CHN_TCSR) & ~(CSR_CM_MSK);
++	tcu_chn_writel(tcu_chn, CHN_TCSR, tcsr | count_mode << 22);
++}
++
++/*Timer control set  pos and neg*/
++static inline void ingenic_tcu_set_pos(struct ingenic_tcu_chn *tcu_chn,unsigned int offset)
++{
++	u32 tcsr;
++	if (offset > 15 && offset < 22){
++		tcsr = tcu_chn_readl(tcu_chn,CHN_TCSR) | TCU_CONTROL_BIT(offset);
++		tcu_chn_writel(tcu_chn,CHN_TCSR, tcsr);
++	}
++}
++
++static inline void ingenic_tcu_set_neg(struct ingenic_tcu_chn *tcu_chn,unsigned int offset)
++{
++	u32 tcsr;
++	if (offset > 15 && offset < 22){
++		tcsr = tcu_chn_readl(tcu_chn,CHN_TCSR) | TCU_CONTROL_BIT(offset);
++		tcu_chn_writel(tcu_chn,CHN_TCSR, tcsr);
++	}
++
++}
++
++static inline void ingenic_tcu_set_pos_neg(struct ingenic_tcu_chn *tcu_chn,unsigned int offset,unsigned int offset1)
++{
++	ingenic_tcu_set_pos(tcu_chn,offset);
++	ingenic_tcu_set_neg(tcu_chn,offset1);
++}
++
++static inline void ingenic_tcu_clr_pos_neg(struct ingenic_tcu_chn *tcu_chn,unsigned int bit)
++{
++	u32 tcsr = tcu_chn_readl(tcu_chn, CHN_TCSR) & ~(TCU_CONTROL_BIT(bit) | TCU_CONTROL_BIT((bit + 1)));
++	tcu_chn_writel(tcu_chn,CHN_TCSR,tcsr);
++}
++
++/*Timer control config signal pos and neg*/
++static inline void ingenic_tcu_config_sig_pos_neg(struct ingenic_tcu_chn *tcu_chn, enum tcu_clksrc clksrc)
++{
++	switch(clksrc){
++		case TCU_CLKSRC_EXT :
++			ingenic_tcu_clr_pos_neg(tcu_chn ,CLK_POS);
++			switch(tcu_chn->sig_ext){
++				case SIG_NEG_EN :
++					ingenic_tcu_set_neg(tcu_chn,CLK_NEG);
++					break;
++				case SIG_POS_EN :
++					ingenic_tcu_set_pos(tcu_chn,CLK_POS);
++					break;
++				case SIG_POS_NEG_EN :
++					ingenic_tcu_set_pos_neg(tcu_chn,CLK_POS,CLK_NEG);
++					break;
++				default :
++					break;
++			}
++			break;
++		case TCU_CLKSRC_GPIO0 :
++			ingenic_tcu_clr_pos_neg(tcu_chn,GPIO0_POS);
++			switch(tcu_chn->sig_gpio0){
++				case SIG_NEG_EN :
++					ingenic_tcu_set_neg(tcu_chn,GPIO0_NEG);
++					break;
++				case SIG_POS_EN :
++					ingenic_tcu_set_pos(tcu_chn,GPIO0_POS);
++					break;
++				case SIG_POS_NEG_EN :
++					ingenic_tcu_set_pos_neg(tcu_chn,GPIO0_NEG,GPIO0_POS);
++					break;
++				default :
++					break;
++			}
++			break;
++		case TCU_CLKSRC_GPIO1 :
++			ingenic_tcu_clr_pos_neg(tcu_chn,GPIO1_POS);
++			switch(tcu_chn->sig_gpio1){
++				case SIG_NEG_EN :
++					ingenic_tcu_set_neg(tcu_chn,GPIO1_NEG);
++					break;
++				case SIG_POS_EN :
++					ingenic_tcu_set_pos(tcu_chn,GPIO1_POS);
++					break;
++				case SIG_POS_NEG_EN :
++					ingenic_tcu_set_pos_neg(tcu_chn,GPIO1_POS,GPIO1_NEG);
++					break;
++				default :
++					break;
++			}
++			break;
++		default :
++			break;
++	}
++}
++
++/*Timer Control Register select timer clock input and counting mode pos or neg*/
++static inline void ingenic_tcu_set_clksrc(struct ingenic_tcu_chn *tcu_chn, enum tcu_clksrc ext, enum tcu_clksrc gpio0,enum tcu_clksrc gpio1)
++{
++	u32 tcsr;
++	ingenic_tcu_config_sig_pos_neg(tcu_chn, ext);
++	ingenic_tcu_config_sig_pos_neg(tcu_chn, gpio0);
++	ingenic_tcu_config_sig_pos_neg(tcu_chn, gpio1);
++	tcsr = tcu_chn_readl(tcu_chn, CHN_TCSR) & ~(ONE_BIT_OFFSET(2) | ONE_BIT_OFFSET(6) |ONE_BIT_OFFSET(7));
++	tcu_chn_writel(tcu_chn, CHN_TCSR, tcsr | ext | gpio0 | gpio1);
++}
++
++static inline void ingenic_tcu_set_shutdown(struct ingenic_tcu_chn *tcu_chn)
++{
++	if(tcu_chn->shutdown_mode) {
++		tcu_chn_writel(tcu_chn, CHN_TCSR, tcu_chn_readl(tcu_chn, CHN_TCSR) | (TCU_CONTROL_BIT(15)));
++	}else {
++		tcu_chn_writel(tcu_chn, CHN_TCSR, tcu_chn_readl(tcu_chn, CHN_TCSR) & ~(TCU_CONTROL_BIT(15)));
++	}
++}
++
++static inline void ingenic_tcu_irq_mode(struct ingenic_tcu_chn *tcu_chn)
++{
++	switch (tcu_chn->irq_type) {
++		case NULL_IRQ_MODE :
++			ingenic_tcu_full_mask(tcu_chn);
++			ingenic_tcu_half_mask(tcu_chn);
++			break;
++		case FULL_IRQ_MODE :
++			ingenic_tcu_full_unmask(tcu_chn);
++			ingenic_tcu_half_mask(tcu_chn);
++			break;
++		case HALF_IRQ_MODE :
++			ingenic_tcu_full_mask(tcu_chn);
++			ingenic_tcu_half_unmask(tcu_chn);
++			break;
++		case FULL_HALF_IRQ_MODE :
++			ingenic_tcu_full_unmask(tcu_chn);
++			ingenic_tcu_half_unmask(tcu_chn);
++			break;
++		default:
++			break;
++	}
++}
++
++/*config gate work mode */
++static inline void ingenic_tcu_config_gate_mode(struct ingenic_tcu_chn *tcu_chn)
++{
++	u32 tcsr;
++	if (tcu_chn->gate_pola){
++		tcu_chn_writel(tcu_chn, CHN_TCSR, tcu_chn_readl(tcu_chn, CHN_TCSR) | (TCU_CONTROL_BIT(14)));
++	}else{
++		tcu_chn_writel(tcu_chn, CHN_TCSR, tcu_chn_readl(tcu_chn, CHN_TCSR) & ~(TCU_CONTROL_BIT(14)));
++	}
++	tcsr = tcu_chn_readl(tcu_chn, CHN_TCSR) & ~(CSR_GATE_MSK);
++	tcu_chn_writel(tcu_chn, CHN_TCSR, tcsr | tcu_chn->gate_sel << 11);
++}
++
++/*config direction work mode*/
++static inline void ingenic_tcu_config_direction_mode(struct ingenic_tcu_chn *tcu_chn)
++{
++	u32 tcsr;
++	if(tcu_chn->dir_pola){
++		tcu_chn_writel(tcu_chn, CHN_TCSR, tcu_chn_readl(tcu_chn, CHN_TCSR) | (TCU_CONTROL_BIT(13)));
++	}else{
++		tcu_chn_writel(tcu_chn, CHN_TCSR, tcu_chn_readl(tcu_chn, CHN_TCSR) & ~(TCU_CONTROL_BIT(13)));
++	}
++	tcsr = tcu_chn_readl(tcu_chn, CHN_TCSR) & ~(CSR_DIR_MSK);
++	tcu_chn_writel(tcu_chn, CHN_TCSR, tcsr | tcu_chn->dir_sel << 8);
++}
++
++/*config quadrature work mode*/
++static inline void ingenic_tcu_config_quadrature_mode(struct ingenic_tcu_chn *tcu_chn)
++{
++	u32 tcsr;
++	if(tcu_chn->dir_pola){
++		tcu_chn_writel(tcu_chn, CHN_TCSR, tcu_chn_readl(tcu_chn, CHN_TCSR) | (TCU_CONTROL_BIT(13)));
++	}else{
++		tcu_chn_writel(tcu_chn, CHN_TCSR, tcu_chn_readl(tcu_chn, CHN_TCSR) & ~(TCU_CONTROL_BIT(13)));
++	}
++	tcu_chn->clk_ext = TCU_CLKSRC_EXT;
++	tcu_chn->clk_gpio0 = TCU_CLKSRC_GPIO0;
++	tcu_chn->clk_gpio1 = TCU_CLKSRC_GPIO1;
++	tcu_chn->dir_sel = DIR_SEL_GPIO_QUA;
++	tcu_chn->sig_gpio0 = SIG_POS_NEG_EN;
++	tcu_chn->sig_gpio1 = SIG_POS_NEG_EN;
++	tcsr = tcu_chn_readl(tcu_chn, CHN_TCSR) & ~(CSR_DIR_MSK);
++	tcu_chn_writel(tcu_chn, CHN_TCSR, tcsr | tcu_chn->dir_sel << 8);
++
++}
++
++/*config pos work mode*/
++static inline void ingenic_tcu_config_pos_mode(struct ingenic_tcu_chn *tcu_chn)
++{
++	u32 tcsr;
++	if (tcu_chn->pos_sel > 0 && tcu_chn->pos_sel < 4){
++	tcsr = tcu_readl(tcu_chn->tcu,CHN_CAP(tcu_chn->index)) & ~(CAP_SEL_MSK);
++	tcu_writel(tcu_chn->tcu,CHN_CAP(tcu_chn->index),tcsr | tcu_chn->pos_sel << 16);
++	}
++}
++
++/*config capture work mode*/
++static inline void ingenic_tcu_config_capture_mode(struct ingenic_tcu_chn *tcu_chn)
++{
++	u32 tcsr;
++	if (tcu_chn->capture_sel >= 0 && tcu_chn->capture_sel < 3){
++	tcsr = tcu_readl(tcu_chn->tcu,CHN_CAP(tcu_chn->index)) & ~(CAP_SEL_MSK | CAP_NUM_MSK);
++	tcu_writel(tcu_chn->tcu,CHN_CAP(tcu_chn->index),tcsr | tcu_chn->capture_sel << 16 | tcu_chn->capture_num );
++	}
++}
++
++/*config filter work mode*/
++static inline void ingenic_tcu_config_filter_mode(struct ingenic_tcu_chn *tcu_chn)
++{
++	u32 tcsr;
++	tcsr = tcu_readl(tcu_chn->tcu,CHN_FIL_VAL(tcu_chn->index)) & ~(FIL_VAL_GPIO1_MSK | FIL_VAL_GPIO0_MSK);
++	tcu_writel(tcu_chn->tcu,CHN_FIL_VAL(tcu_chn->index),tcsr | tcu_chn->fil_a_num | tcu_chn->fil_b_num << 16 );
++}
++
++/*Choose a working mode*/
++static inline void ingenic_tcu_sel_work_mode(struct ingenic_tcu_chn *tcu_chn)
++{
++	switch(tcu_chn->mode_sel){
++		case GENERAL_MODE :
++			break;
++		case GATE_MODE :
++			ingenic_tcu_config_gate_mode(tcu_chn);
++			break;
++		case DIRECTION_MODE :
++			ingenic_tcu_config_direction_mode(tcu_chn);
++			break;
++		case QUADRATURE_MODE :
++			ingenic_tcu_config_quadrature_mode(tcu_chn);
++			break;
++		case POS_MODE :
++			ingenic_tcu_config_pos_mode(tcu_chn);
++			break;
++		case CAPTURE_MODE :
++			ingenic_tcu_config_capture_mode(tcu_chn);
++			break;
++		case FILTER_MODE :
++			ingenic_tcu_config_filter_mode(tcu_chn);
++			break;
++		default :
++			break;
++	}
++
++}
++
++void sws_pr_debug(struct ingenic_tcu_chn *tcu_chn)
++{
++	static int count = 0;
++	count ++;
++	printk("\n\n----------------------------------------count N0.%d----------------------------------------------------\n\n",count);
++	printk("-stop-----addr-%08x-value-%08x-----------\n",(unsigned int)(tcu_chn->tcu->iomem + TCU_TSR),tcu_readl(tcu_chn->tcu,TCU_TSR));
++	printk("-mask-----addr-%08x-value-%08x-----------\n",(unsigned int)(tcu_chn->tcu->iomem + TCU_TMR),tcu_readl(tcu_chn->tcu,TCU_TMR));
++	printk("-enable---addr-%08x-value-%08x-----------\n",(unsigned int)(tcu_chn->tcu->iomem + TCU_TER),tcu_readl(tcu_chn->tcu,TCU_TER));
++	printk("-flag-----addr-%08x-value-%08x-----------\n",(unsigned int)(tcu_chn->tcu->iomem + TCU_TFR),tcu_readl(tcu_chn->tcu,TCU_TFR));
++	printk("-Control--addr-%08x-value-%08x-----------\n",(unsigned int)(tcu_chn->tcu->iomem + tcu_chn->reg_base + CHN_TCSR),tcu_chn_readl(tcu_chn,CHN_TCSR));
++	printk("-full-----addr-%08x-value-%08x-----------\n",(unsigned int)(tcu_chn->tcu->iomem + tcu_chn->reg_base + CHN_TDFR),tcu_chn_readl(tcu_chn,CHN_TDFR));
++	printk("-half-   -addr-%08x-value-%08x-----------\n",(unsigned int)(tcu_chn->tcu->iomem + tcu_chn->reg_base + CHN_TDHR),tcu_chn_readl(tcu_chn,CHN_TDHR));
++	printk("-TCNT-----addr-%08x-value-%08x-----------\n",(unsigned int)(tcu_chn->tcu->iomem + tcu_chn->reg_base + CHN_TCNT),tcu_chn_readl(tcu_chn,CHN_TCNT));
++	printk("-CAP reg_base-------value-%08x-----------\n",tcu_readl(tcu_chn->tcu,CHN_CAP(tcu_chn->index)));
++	printk("-CAP_VAL register---value-%08x-----------\n",tcu_readl(tcu_chn->tcu,CHN_CAP_VAL(tcu_chn->index)));
++}
++EXPORT_SYMBOL_GPL(sws_pr_debug);
++
++
++void ingenic_tcu_clear_irq_flag(struct ingenic_tcu_chn *tcu_chn)
++{
++	ingenic_tcu_clear_full_flag(tcu_chn);
++	ingenic_tcu_clear_half_flag(tcu_chn);
++}
++
++EXPORT_SYMBOL_GPL(ingenic_tcu_clear_irq_flag);
++
++void ingenic_tcu_config_chn(struct ingenic_tcu_chn *tcu_chn)
++{
++
++	spin_lock(&tcu_chn->tcu->lock);
++	/* Clear IRQ flag */
++	ingenic_tcu_clear_irq_flag(tcu_chn);
++
++	/* Config IRQ */
++	ingenic_tcu_irq_mode(tcu_chn);
++
++	/*select work mode*/
++	ingenic_tcu_sel_work_mode(tcu_chn);
++
++	/*full num and half num*/
++	ingenic_tcu_set_chn_full(tcu_chn,tcu_chn->full_num);
++	ingenic_tcu_set_chn_half(tcu_chn,tcu_chn->half_num);
++
++	/*TCNT clear to 0*/
++	ingenic_tcu_clear_tcnt(tcu_chn);
++
++	/* shutdown mode */
++	ingenic_tcu_set_shutdown(tcu_chn);
++
++	/* prescale */
++	if(!(tcu_readl(tcu_chn->tcu,TCU_TER) & (1 << tcu_chn->index)))
++		ingenic_tcu_set_prescale(tcu_chn, tcu_chn->prescale);
++
++	/* clk source */
++	ingenic_tcu_set_clksrc(tcu_chn, tcu_chn->clk_ext, tcu_chn->clk_gpio0,tcu_chn->clk_gpio1);
++
++	/*select counter mode*/
++	ingenic_tcu_set_count_mode(tcu_chn,tcu_chn->count_mode);
++	spin_unlock(&tcu_chn->tcu->lock);
++}
++EXPORT_SYMBOL_GPL(ingenic_tcu_config_chn);
++
++#if DE_WARNING
++static void ingenic_tcu_irq_mask(void)
++{
++	unsigned long flags;
++
++	int id ;
++	for(id = 0; id < NR_TCU_CHNS; id++){
++		if(g_tcu_chn[id].en_flag){
++			spin_lock_irqsave(&g_tcu_chn[id].tcu->lock, flags);
++			switch (g_tcu_chn[id].irq_type) {
++				case FULL_IRQ_MODE :
++					ingenic_tcu_full_mask(&g_tcu_chn[id]);
++					break;
++				case HALF_IRQ_MODE :
++					ingenic_tcu_half_mask(&g_tcu_chn[id]);
++					break;
++				case FULL_HALF_IRQ_MODE :
++					ingenic_tcu_full_mask(&g_tcu_chn[id]);
++					ingenic_tcu_half_mask(&g_tcu_chn[id]);
++					break;
++				default:
++					break;
++			}
++			spin_unlock_irqrestore(&g_tcu_chn[id].tcu->lock, flags);
++		}
++	}
++}
++#endif
++
++#if DE_WARNING
++static void ingenic_tcu_irq_unmask(void)
++{
++	unsigned long flags;
++	int id ;
++	for(id = 0; id < NR_TCU_CHNS; id++){
++		if(g_tcu_chn[id].en_flag){
++			spin_lock_irqsave(&g_tcu_chn[id].tcu->lock, flags);
++			switch (g_tcu_chn[id].irq_type) {
++				case FULL_IRQ_MODE :
++					ingenic_tcu_full_unmask(&g_tcu_chn[id]);
++					break;
++				case HALF_IRQ_MODE :
++					ingenic_tcu_half_unmask(&g_tcu_chn[id]);
++					break;
++				case FULL_HALF_IRQ_MODE :
++					ingenic_tcu_full_unmask(&g_tcu_chn[id]);
++					ingenic_tcu_half_unmask(&g_tcu_chn[id]);
++					break;
++				default:
++					break;
++			}
++			spin_unlock_irqrestore(&g_tcu_chn[id].tcu->lock, flags);
++		}
++	}
++}
++#endif
++
++static void ingenic_tcu_irq_ack(struct ingenic_tcu *tcu)
++{
++	unsigned long flags;
++	unsigned long tmp;
++	int id ;
++	int i;
++	int times = timeout;
++
++	for(id = 0; id < NR_TCU_CHNS; id++){
++		if(g_tcu_chn[id].en_flag){
++			spin_lock_irqsave(&g_tcu_chn[id].tcu->lock, flags);
++			switch (g_tcu_chn[id].irq_type) {
++				case FULL_IRQ_MODE :
++					ingenic_tcu_clear_full_flag(&g_tcu_chn[id]);
++					break;
++				case HALF_IRQ_MODE :
++					ingenic_tcu_clear_half_flag(&g_tcu_chn[id]);
++					break;
++				case FULL_HALF_IRQ_MODE :
++					ingenic_tcu_clear_full_flag(&g_tcu_chn[id]);
++					ingenic_tcu_clear_half_flag(&g_tcu_chn[id]);
++					break;
++				default:
++					break;
++			}
++
++			if(g_tcu_chn[id].gpio_trigger) {
++				tmp = ingenic_tcu_store_flag_st(tcu);
++				i = 0;
++				while(tmp) {
++					if(tmp & (1 << i)) {
++						tmp &= ~(1 << i);
++						ingenic_tcu_store_flag_clr(&g_tcu_chn[i]);
++						printk("%d %d %d\n",__LINE__, i ,ingenic_tcu_store_val(&g_tcu_chn[i]));
++					}
++
++					if (times-- == 0)
++						break;
++					i++;
++				}
++			}
++			spin_unlock_irqrestore(&g_tcu_chn[id].tcu->lock, flags);
++		}
++	}
++}
++
++/*This is a simple configuration test demo*/
++static void ingenic_tcu_config_attr(int id,enum tcu_mode_sel mode_sel)
++{
++	int i = 0;
++	g_tcu_chn[id].mode_sel = mode_sel;
++	g_tcu_chn[id].irq_type = FULL_IRQ_MODE;
++	g_tcu_chn[id].full_num = 0xffff;
++	g_tcu_chn[id].half_num = 0x5000;
++	g_tcu_chn[id].prescale = TCU_PRESCALE_1;
++
++	g_tcu_chn[id].count_value = 0;
++	g_tcu_chn[id].shutdown_mode = 0;
++	g_tcu_chn[id].en_flag = 1;
++
++	/*In order to facilitate testing,
++	 * it has no practical significance.*/
++	switch(g_tcu_chn[id].mode_sel){
++		case GENERAL_MODE:
++			/*Enable external clock to use rising edge counting , result TCNT != 0*/
++			g_tcu_chn[id].clk_ext = TCU_CLKSRC_EXT;
++			g_tcu_chn[id].sig_ext = SIG_POS_EN;
++			break;
++		case GATE_MODE:
++			/*gate signal hold on 0,counter start when control signal is 1,result TCNT == 0*/
++			g_tcu_chn[id].gate_sel = GATE_SEL_HZ;
++			g_tcu_chn[id].gate_pola = GATE_POLA_HIGH;
++			g_tcu_chn[id].clk_ext = TCU_CLKSRC_EXT;
++			g_tcu_chn[id].sig_ext = SIG_POS_EN;
++			break;
++		case DIRECTION_MODE:
++			/*use gpio0 with direction signa. counter sub when control signal is 1.result TCNT add and sub */
++			g_tcu_chn[id].clk_gpio0 = TCU_CLKSRC_GPIO0;
++			g_tcu_chn[id].dir_sel = DIR_SEL_GPIO0;
++			g_tcu_chn[id].dir_pola = DIR_POLA_HIGH;
++			g_tcu_chn[id].clk_ext = TCU_CLKSRC_EXT;
++			g_tcu_chn[id].sig_ext = SIG_POS_EN;
++			break;
++		case POS_MODE:
++			/*TCNT is cleared on the rising edge of gpio0.*/
++			g_tcu_chn[id].clk_ext = TCU_CLKSRC_EXT;
++			g_tcu_chn[id].sig_ext = SIG_POS_EN;
++			/*gpio0 pos clear count*/
++			g_tcu_chn[id].clk_gpio0 = TCU_CLKSRC_GPIO0;
++			g_tcu_chn[id].sig_gpio0 = SIG_POS_EN;
++			g_tcu_chn[id].capture_sel = GPIO0_POS_CLR;
++			break;
++		case CAPTURE_MODE:
++			/*Use ext_clk to capture the duty cycle of gpio0, result CAP_VAL register have value*/
++			g_tcu_chn[id].clk_ext = TCU_CLKSRC_EXT;
++			g_tcu_chn[id].sig_ext = SIG_POS_EN;
++			g_tcu_chn[id].clk_gpio0 = TCU_CLKSRC_GPIO0;
++			g_tcu_chn[id].capture_sel = CAPTURE_GPIO0;
++			g_tcu_chn[id].capture_num = 0xa0;
++			break;
++		case FILTER_MODE:
++			/*for easy test set max*/
++			g_tcu_chn[id].clk_gpio0 = TCU_CLKSRC_GPIO0;
++			g_tcu_chn[id].sig_gpio0 = SIG_POS_EN;
++			g_tcu_chn[id].fil_a_num = 0x3ff;
++			g_tcu_chn[id].fil_b_num = 0x3ff;
++			break;
++		default:
++			 break;
++	}
++
++	if(g_tcu_chn[id].gpio_trigger) {
++		ingenic_tcu_store_mask_set(&g_tcu_chn[id]);
++		ingenic_tcu_store_neg_enable(&g_tcu_chn[id]);
++		ingenic_tcu_store_enable(&g_tcu_chn[id]);
++		ingenic_tcu_store_mask_clr(&g_tcu_chn[id]);
++	}
++
++	ingenic_tcu_config_chn(&g_tcu_chn[id]);
++	ingenic_tcu_enable_counter(&g_tcu_chn[id]);
++	ingenic_tcu_start_counter(&g_tcu_chn[id]);
++
++	if(!g_tcu_chn[id].gpio_trigger) {
++		for(i = 0; i < 20 ;i++)
++			sws_pr_debug(&g_tcu_chn[id]);
++	}
++}
++
++
++static irqreturn_t ingenic_tcu_interrupt(int irq, void *dev_id)
++{
++	struct ingenic_tcu *tcu = (struct ingenic_tcu *)(dev_id);
++	if(tcu_readl(tcu,TCU_TFR) & TCU_FLAG_RD){
++	}else{
++	      ingenic_tcu_irq_ack(tcu);
++	}
++	return IRQ_HANDLED;
++}
++
++static irqreturn_t ingenic_tcu_trigger_interrupt(int irq, void *dev_id)
++{
++	struct ingenic_tcu *tcu = (struct ingenic_tcu *)(dev_id);
++	unsigned long flags;
++	unsigned long tmp;
++	int i;
++	int times = timeout;
++
++	spin_lock_irqsave(&tcu->lock, flags);
++	tmp = ingenic_tcu_store_flag_st(tcu);
++	i = 0;
++	while(tmp) {
++		if(tmp & (1 << i)) {
++			tmp &= ~(1 << i);
++			ingenic_tcu_store_flag_clr(&g_tcu_chn[i]);
++			printk("%d %d %d\n",__LINE__, i ,ingenic_tcu_store_val(&g_tcu_chn[i]));
++		}
++
++		if (times-- == 0)
++			break;
++
++		i++;
++	}
++	spin_unlock_irqrestore(&tcu->lock, flags);
++
++	return IRQ_HANDLED;
++}
++
++static ssize_t tcu_show_enable(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	int i;
++	int ret = 0;
++	ret += sprintf(buf + ret, "\nmode_sel :\n");
++	ret += sprintf(buf + ret, "0:GENERAL_MODE 1:GATE_MODE 2:DIRECTION_MODE 3:QUADRATURE_MODE\n");
++	ret += sprintf(buf + ret, "4:POS_MODE 5:CAPTURE_MODE 6:FILTER_MODE\n\n");
++	ret += sprintf(buf + ret, "####################example####################\n");
++	ret += sprintf(buf + ret, "## echo channel_id mode_sel gpio_trigger > enable \n");
++	ret += sprintf(buf + ret, "## echo channel_id > disable \n\n");
++	for (i = 0; i < NR_TCU_CHNS ; i++) {
++		if(g_tcu_chn[i].en_flag)
++			ret += sprintf(buf + ret, "channel: %02d enable\n", i);
++		else
++			ret += sprintf(buf + ret, "channel: %02d disable\n", i);
++	}
++	return ret;
++}
++
++static ssize_t tcu_store_enable(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	int channel_id;
++	int mode_id;
++	enum tcu_mode_sel mode_sel;
++	const char *str = buf;
++	int ret_count = 0;
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count)
++			return count;
++	}
++	channel_id = simple_strtoul(str, (char **)&str, 10);
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count)
++			return count;
++	}
++	mode_id = simple_strtoul(str, (char **)&str, 10);
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count)
++			g_tcu_chn[channel_id].gpio_trigger = 0;
++	}
++	g_tcu_chn[channel_id].gpio_trigger = simple_strtoul(str, (char **)&str, 10);
++
++	switch(mode_id){
++		case 0: mode_sel = GENERAL_MODE;
++			break;
++		case 1: mode_sel = GATE_MODE;
++			break;
++		case 2: mode_sel = DIRECTION_MODE;
++			break;
++		case 3: mode_sel = QUADRATURE_MODE;
++			break;
++		case 4: mode_sel = POS_MODE;
++			break;
++		case 5: mode_sel = CAPTURE_MODE;
++			break;
++		case 6: mode_sel = FILTER_MODE;
++			break;
++		default: mode_sel = GENERAL_MODE;
++			 break;
++	}
++
++	if(channel_id >= 0 && channel_id < 8){
++		if(g_tcu_chn[channel_id].en_flag){
++			printk("channel %d already enable \n",channel_id);
++			return -1;
++		}
++
++		printk("mode_id = %d \n",mode_id);
++		ingenic_tcu_config_attr(channel_id,mode_sel);
++	}else
++		printk("Please select the correct channel 0 ~ 7 range.\n");
++	return count;
++}
++
++static ssize_t tcu_store_disable(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	int id;
++	const char *str = buf;
++	int ret_count = 0;
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count)
++			return count;
++	}
++
++	id = simple_strtoul(str, (char **)&str, 10);
++
++	if(id >= 0 && id < 8){
++		if(!g_tcu_chn[id].en_flag){
++			printk("channel %d already disable \n",id);
++			return -1;
++		}
++
++		if(g_tcu_chn[id].gpio_trigger) {
++			ingenic_tcu_store_mask_clr(&g_tcu_chn[id]);
++			ingenic_tcu_store_neg_disable(&g_tcu_chn[id]);
++			ingenic_tcu_store_disable(&g_tcu_chn[id]);
++		}
++		ingenic_tcu_set_disable(&g_tcu_chn[id]);
++	}else
++		printk("Please select the correct channel 0 ~ 7 range.\n");
++	return count;
++}
++
++
++static struct device_attribute tcu_device_attributes[] = {
++	__ATTR(enable, S_IRUGO|S_IWUSR, tcu_show_enable, tcu_store_enable),
++	__ATTR(disable, S_IRUGO|S_IWUSR, tcu_show_enable, tcu_store_disable),
++};
++
++
++static int ingenic_tcu_probe(struct platform_device *pdev)
++{
++	struct ingenic_tcu *tcu;
++	int  i, ret = 0;
++
++	tcu = kmalloc(sizeof(struct ingenic_tcu), GFP_KERNEL);
++	if (!tcu) {
++		dev_err(&pdev->dev, "Failed to allocate driver struct\n");
++		return -ENOMEM;
++	}
++
++	tcu->irq = platform_get_irq(pdev, 0);
++	if (tcu->irq < 0) {
++		dev_err(&pdev->dev, "Failed to get platform irq\n");
++		ret = tcu->irq;
++		goto err_free;
++	}
++
++	tcu->irq_trigger = platform_get_irq(pdev, 1);
++	if (tcu->irq_trigger < 0) {
++		dev_err(&pdev->dev, "not support irq trigger function\n");
++		ret = tcu->irq_trigger;
++	} else {
++		ret = request_irq(tcu->irq_trigger,ingenic_tcu_trigger_interrupt,
++				IRQF_SHARED | IRQF_TRIGGER_LOW,"ingenic-tcu-tri-interrupt",tcu);
++
++		if (ret) {
++			dev_err(&pdev->dev, "request_irq failed !! %d-\n",tcu->irq_trigger);
++		}
++	}
++
++	tcu->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!tcu->res) {
++		dev_err(&pdev->dev, "No iomem resource\n");
++		ret = -ENXIO;
++		goto err_ioremap;
++	}
++
++	tcu->clk = devm_clk_get(&pdev->dev,"gate_tcu");
++	clk_prepare_enable(tcu->clk);
++
++	tcu->iomem = ioremap(tcu->res->start, resource_size(tcu->res));
++	if (!tcu->iomem)
++		goto err_mfd_add;
++
++	spin_lock_init(&tcu->lock);
++
++	ret = request_irq(tcu->irq,ingenic_tcu_interrupt,
++			IRQF_SHARED | IRQF_TRIGGER_LOW,"ingenic-tcu-interrupt",tcu);
++	if (ret) {
++		dev_err(&pdev->dev, "request_irq failed !! %d-\n",tcu->irq);
++		goto err_mfd_add;
++	}
++
++	platform_set_drvdata(pdev, tcu);
++
++	for (i = 0; i < NR_TCU_CHNS; i++) {
++		g_tcu_chn[i].index = i;
++		g_tcu_chn[i].capture_num = 0;
++		g_tcu_chn[i].count_value = 0;
++		g_tcu_chn[i].fil_a_num	 = 0;
++		g_tcu_chn[i].fil_b_num	 = 0;
++		g_tcu_chn[i].reg_base	 = TCU_FULL0 + i * TCU_CHN_OFFSET;
++		g_tcu_chn[i].irq_type	 = NULL_IRQ_MODE;
++		g_tcu_chn[i].clk_ext	 = TCU_CLKSRC_NULL;
++		g_tcu_chn[i].clk_gpio0	 = TCU_CLKSRC_NULL;
++		g_tcu_chn[i].clk_gpio1	 = TCU_CLKSRC_NULL;
++		g_tcu_chn[i].prescale	 = TCU_PRESCALE_64;
++		g_tcu_chn[i].shutdown_mode = 0;
++		g_tcu_chn[i].count_mode	 = COUNT_MODE_FCZ;
++		g_tcu_chn[i].mode_sel	 = GENERAL_MODE;
++		g_tcu_chn[i].gate_pola	 = GATE_POLA_LOW;
++		g_tcu_chn[i].gate_sel	 = GATE_SEL_HZ;
++		g_tcu_chn[i].dir_sel	 = DIR_SEL_HH;
++		g_tcu_chn[i].dir_pola	 = DIR_POLA_LOW;
++		g_tcu_chn[i].en_flag	 = 0;
++		g_tcu_chn[i].tcu	 = tcu;
++		g_tcu_chn[i].gpio_trigger = 0;
++	}
++
++	for (i = 0; i < ARRAY_SIZE(tcu_device_attributes); i++) {
++		ret = device_create_file(&pdev->dev, &tcu_device_attributes[i]);
++		if (ret)
++			dev_warn(&pdev->dev, "attribute %d create failed", i);
++	}
++	printk("ingenic TCU driver register completed\n");
++	return 0;
++
++err_mfd_add:
++	iounmap(tcu->iomem);
++err_ioremap:
++	release_resource(tcu->res);
++err_free:
++	kfree(tcu);
++	return ret;
++}
++
++static int ingenic_tcu_remove(struct platform_device *pdev)
++{
++	struct ingenic_tcu *tcu = platform_get_drvdata(pdev);
++
++	clk_disable_unprepare(tcu->clk);
++	iounmap(tcu->iomem);
++	release_resource(tcu->res);
++	platform_set_drvdata(pdev, NULL);
++	free_irq(tcu->irq,tcu);
++	kfree(tcu);
++
++	return 0;
++}
++static const struct of_device_id tcu_match[] = {
++	{ .compatible = "ingenic,tcu", .data = NULL },
++	{},
++};
++MODULE_DEVICE_TABLE(of, tcu_match);
++
++static struct platform_driver ingenic_tcu_driver = {
++	.probe	= ingenic_tcu_probe,
++	.remove	= ingenic_tcu_remove,
++	.driver = {
++		.name = "ingenic-tcu",
++		.of_match_table = tcu_match,
++	},
++};
++
++module_platform_driver(ingenic_tcu_driver);
++
++MODULE_AUTHOR("wssong <wenshuo.song@ingenic.com>");
++MODULE_DESCRIPTION("Ingenic TCU driver");
++MODULE_ALIAS("platform:x2000_v2-tcu");
++MODULE_LICENSE("GPL v2");
+diff --git a/module_drivers/drivers/mfd/ingenic-tcu_v1.c b/module_drivers/drivers/mfd/ingenic-tcu_v1.c
+new file mode 100644
+index 000000000..76b6c6f42
+--- /dev/null
++++ b/module_drivers/drivers/mfd/ingenic-tcu_v1.c
+@@ -0,0 +1,942 @@
++/*
++ * ingenic-tcu.c - Inegnic Soc TCU MFD driver.
++ *
++ * Copyright (C) 2015 Ingenic Semiconductor Co., Ltd.
++ * Written by bo.liu <bo.liu@ingenic.com>.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/platform_device.h>
++#include <linux/of_platform.h>
++#include <linux/of_irq.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/syscore_ops.h>
++//#include <linux/wakelock.h>
++#include <linux/mutex.h>
++#include <linux/mfd/core.h>
++#include <linux/mfd/ingenic-tcu_v1.h>
++#include <linux/clk.h>
++
++#define WDT_TDR			(0x00)  /* rw, 32, 0x???????? */
++#define WDT_TCER		(0x04)  /* rw, 32, 0x???????? */
++#define WDT_TCNT		(0x08)  /* rw, 32, 0x???????? */
++#define WDT_TCSR		(0x0c)  /* rw, 32, 0x???????? */
++
++#define TCU_TSTR		(0xF0)  /* Timer Status Register,Only Used In Tcu2 Mode */
++#define TCU_TSTSR		(0xF4)  /* Timer Status Set Register */
++#define TCU_TSTCR		(0xF8)  /* Timer Status Clear Register */
++#define TCU_TSR			(0x1C)  /* Timer Stop Register */
++#define TCU_TSSR		(0x2C)  /* Timer Stop Set Register */
++#define TCU_TSCR		(0x3C)  /* Timer Stop Clear Register */
++#define TCU_TER			(0x10)  /* Timer Counter Enable Register */
++#define TCU_TESR		(0x14)  /* Timer Counter Enable Set Register */
++#define TCU_TECR		(0x18)  /* Timer Counter Enable Clear Register */
++#define TCU_TFR			(0x20)  /* Timer Flag Register */
++#define TCU_TFSR		(0x24)  /* Timer Flag Set Register */
++#define TCU_TFCR		(0x28)  /* Timer Flag Clear Register */
++#define TCU_TMR			(0x30)  /* Timer Mask Register */
++#define TCU_TMSR		(0x34)  /* Timer Mask Set Register */
++#define TCU_TMCR		(0x38)  /* Timer Mask Clear Register */
++
++#define CH_TDFR(n)		(0x40 + (n)*0x10)		/* Timer Data Full Reg */
++#define CH_TDHR(n)		(0x44 + (n)*0x10)		/* Timer Data Half Reg */
++#define CH_TCNT(n)		(0x48 + (n)*0x10)		/* Timer Counter Reg */
++#define CH_TCSR(n)		(0x4C + (n)*0x10)		/* Timer Control Reg */
++
++#define TCSR_PWM_BYPASS	(1 << 11)		/* clear counter to 0, only used in TCU2 mode */
++#define TCSR_CNT_CLRZ	(1 << 10)		/* clear counter to 0, only used in TCU2 mode */
++#define TCSR_PWM_SD		(1 << 9)		/* shut down the pwm output only used in TCU1 mode */
++#define TCSR_PWM_HIGH	(1 << 8)		/* selects an initial output level for pwm output */
++#define TCSR_PWM_EN		(1 << 7)		/* pwm pin output enable */
++#define TCSR_PWM_IN		(1 << 6)		/* pwm pin output enable */
++
++struct ingenic_tcu {
++	void __iomem *base;
++	struct device *dev;
++	struct clk *clk;
++	struct device_node *np;
++	struct irq_domain *irq_domain;
++	struct mfd_cell * tcu_cells;
++	struct ingenic_tcu_chn *tcu_chn;
++
++	char idmap[32];
++	int channel_mask;
++	int irq_tcu0;
++	int irq_tcu1;
++	int irq_tcu2;
++	int channel_num;
++	int channel_irq_num;
++	spinlock_t lock;
++};
++
++#define TCU_DEBUG 0
++
++static struct ingenic_tcu *tcu;
++
++static inline int tcu_readl(struct ingenic_tcu *tcu, unsigned int reg_addr)
++{
++	return readl(tcu->base + reg_addr);
++}
++static inline void tcu_writel(struct ingenic_tcu *tcu, unsigned int reg_addr,
++							  unsigned int val)
++{
++	writel(val, tcu->base + reg_addr);
++}
++#if TCU_DEBUG
++static void tcu_dump(int id)
++{
++	printk("====================================channel %d===================================\n", id);
++
++	if(id == 16){
++		printk("tcu_readl(WDT_TDR %x) = %x\n", (unsigned int)(tcu->base + WDT_TDR), tcu_readl(tcu, WDT_TDR));
++		printk("tcu_readl(WDT_TCER %x) = %x\n", (unsigned int)(tcu->base + WDT_TCER), tcu_readl(tcu, WDT_TCER));
++		printk("tcu_readl(WDT_TCNT %x) = %x\n", (unsigned int)(tcu->base + WDT_TCNT), tcu_readl(tcu, WDT_TCNT));
++		printk("tcu_readl(WDT_TCSR %x) = %x\n", (unsigned int)(tcu->base + WDT_TCSR), tcu_readl(tcu, WDT_TCSR));
++		printk("tcu_readl(TCU_TSR %x) = %x\n", (unsigned int)(tcu->base + TCU_TSR), tcu_readl(tcu, TCU_TSR));
++		return;
++	}
++
++	printk("tcu_readl(CH_TDFR(id) %x) = %x\n", (unsigned int)(tcu->base + CH_TDFR(id)), tcu_readl(tcu, CH_TDFR(id)));
++	printk("tcu_readl(CH_TDHR(id) %x) = %x\n", (unsigned int)(tcu->base + CH_TDHR(id)), tcu_readl(tcu, CH_TDHR(id)));
++	printk("tcu_readl(CH_TCNT(id) %x) = %x\n", (unsigned int)(tcu->base + CH_TCNT(id)), tcu_readl(tcu, CH_TCNT(id)));
++	printk("tcu_readl(CH_TCSR(id) %x) = %x\n", (unsigned int)(tcu->base + CH_TCSR(id)), tcu_readl(tcu, CH_TCSR(id)));
++
++	printk("tcu_readl(TCU_TSTR %x) = %x\n", (unsigned int)(tcu->base + TCU_TSTR), tcu_readl(tcu, TCU_TSTR));
++	printk("tcu_readl(TCU_TSR %x) = %x\n", (unsigned int)(tcu->base + TCU_TSR), tcu_readl(tcu, TCU_TSR));
++	printk("tcu_readl(TCU_TER %x) = %x\n", (unsigned int)(tcu->base + TCU_TER), tcu_readl(tcu, TCU_TER));
++	printk("tcu_readl(TCU_TFR %x) = %x\n", (unsigned int)(tcu->base + TCU_TFR), tcu_readl(tcu, TCU_TFR));
++	printk("tcu_readl(TCU_TMR %x) = %x\n", (unsigned int)(tcu->base + TCU_TMR), tcu_readl(tcu, TCU_TMR));
++	printk("=======================================================================\n");
++}
++#endif
++
++static inline void tcu_mask_full_irq(int id)
++{
++	tcu_writel(tcu, TCU_TMSR, 1 << id);
++}
++static inline void tcu_unmask_full_irq(int id)
++{
++	tcu_writel(tcu, TCU_TMCR, 1 << id);
++}
++static inline void tcu_clear_full_irq(int id)
++{
++	tcu_writel(tcu, TCU_TFCR, 1 << id);
++}
++static inline void tcu_mask_half_irq(int id)
++{
++	tcu_writel(tcu, TCU_TMSR, 1 << (id + 16));
++}
++static inline void tcu_unmask_half_irq(int id)
++{
++	tcu_writel(tcu, TCU_TMCR, 1 << (id + 16));
++}
++static inline void tcu_clear_half_irq(int id)
++{
++	tcu_writel(tcu, TCU_TFCR, 1 << (id + 16));
++}
++
++void tcu_enable_counter(int id)
++{
++	tcu_writel(tcu, TCU_TESR, BIT(id));
++}
++EXPORT_SYMBOL_GPL(tcu_enable_counter);
++
++void tcu_disable_counter(int id)
++{
++	int index = tcu->idmap[id];
++	struct ingenic_tcu_chn *chn = &tcu->tcu_chn[index];
++	tcu_writel(tcu, TCU_TECR, BIT(id));
++	if (chn->cib.mode == TCU_MODE2) {
++		int timeout = 5000;
++		while ((tcu_readl(tcu, TCU_TSTR) & (1 << id)) || (timeout--));
++		if(!timeout){
++			dev_err(tcu->dev, "channel %d:the reset of counter is not finished now\n", id);
++		}
++	}
++}
++EXPORT_SYMBOL_GPL(tcu_disable_counter);
++
++void tcu_start_counter(int id)
++{
++	tcu_writel(tcu, TCU_TSCR, BIT(id));
++}
++EXPORT_SYMBOL_GPL(tcu_start_counter);
++
++void tcu_stop_counter(int id)
++{
++	tcu_writel(tcu, TCU_TSSR, BIT(id));
++}
++EXPORT_SYMBOL_GPL(tcu_stop_counter);
++
++void tcu_set_counter(int id, unsigned int val)
++{
++	tcu_writel(tcu, CH_TCNT(id), val);
++}
++EXPORT_SYMBOL_GPL(tcu_set_counter);
++
++int tcu_get_counter(int id)
++{
++	return tcu_readl(tcu, CH_TCNT(id));
++}
++EXPORT_SYMBOL_GPL(tcu_get_counter);
++
++static inline void tcu_disable_all_channel(void)
++{
++	/* Timer irqs are unmasked by default, mask them */
++	tcu_writel(tcu, TCU_TMSR, 0x00ff00ff);
++	/* Stop all timer counter */
++	tcu_writel(tcu, TCU_TECR, 0x000080ff);
++	/* Disable all timer clocks except for those used as system timers */
++	tcu_writel(tcu, TCU_TSSR, 0x000000ff);
++}
++
++static int tcu_pwm_output_enable(int id)
++{
++	unsigned int val;
++
++	val = tcu_readl(tcu, CH_TCSR(id));
++	val |= TCSR_PWM_EN;
++	tcu_writel(tcu, CH_TCSR(id), val);
++
++	return 0;
++}
++
++static void tcu_pwm_output_disable(int id)
++{
++	unsigned int val;
++	val = tcu_readl(tcu, CH_TCSR(id));
++	val &= ~TCSR_PWM_EN;
++	tcu_writel(tcu, CH_TCSR(id), val);
++}
++
++static int tcu_pwm_bypass_enable(int id)
++{
++	unsigned int val;
++
++	val = tcu_readl(tcu, CH_TCSR(id));
++	if(val & TCU_CLKSRC_PCK) {
++		dev_err(tcu->dev, "TCU %d pwm bypass is not support clk source pck\n", id);
++		return -ENXIO;
++	}
++	val |= TCSR_PWM_BYPASS;
++	tcu_writel(tcu, CH_TCSR(id), val);
++
++	return 0;
++}
++
++static int tcu_pwm_bypass_disable(int id)
++{
++	unsigned int val;
++
++	val = tcu_readl(tcu, CH_TCSR(id));
++	val &= ~TCSR_PWM_BYPASS;
++	tcu_writel(tcu, CH_TCSR(id), val);
++
++	return 0;
++}
++
++static void tcu_clear_counter_to_zero(int id)
++{
++	int index = tcu->idmap[id];
++	struct ingenic_tcu_chn *chn = &tcu->tcu_chn[index];
++	if (chn->cib.mode == TCU_MODE2) {
++		unsigned int val = tcu_readl(tcu, CH_TCSR(id));
++		tcu_writel(tcu, CH_TCSR(id), (val | TCSR_CNT_CLRZ));
++	}
++
++	tcu_writel(tcu, CH_TCNT(id), 0);
++}
++
++static void set_tcu_full_half_value(int id, unsigned int full_num,
++									unsigned int half_num)
++{
++	tcu_writel(tcu, CH_TDFR(id), full_num);
++	tcu_writel(tcu, CH_TDHR(id), half_num);
++}
++
++static void tcu_set_pwm_shutdown(int id, unsigned int shutdown)
++{
++	unsigned int val;
++
++	val = tcu_readl(tcu, CH_TCSR(id));
++	if (shutdown)
++		val |= TCSR_PWM_SD;
++	else
++		val &= ~TCSR_PWM_SD;
++	tcu_writel(tcu, CH_TCSR(id), val);
++}
++
++static void tcu_set_start_state(int id)
++{
++	/*fix this*/
++	/*tcu_disable_counter(id);*/
++	tcu_start_counter(id);
++
++        /* TCSR just keep, which will be update follow process
++           in function ingenic_tcu_config
++           tcu_writel(tcu, CH_TCSR(id), 0);
++         */
++}
++
++static void tcu_pwm_input_enable(int id)
++{
++	unsigned int val;
++
++	val = tcu_readl(tcu, CH_TCSR(id));
++	val |= TCSR_PWM_IN;
++	tcu_writel(tcu, CH_TCSR(id), val);
++}
++
++static void tcu_pwm_input_disable(int id)
++{
++	unsigned int val;
++
++	val = tcu_readl(tcu, CH_TCSR(id));
++	val &= ~TCSR_PWM_IN;
++	tcu_writel(tcu, CH_TCSR(id), val);
++}
++
++static int tcu_clock_enable(struct platform_device *pdev)
++{
++	if (!(tcu->channel_mask & BIT(pdev->id))) {
++		dev_err(&pdev->dev,
++				"current tcu channel %d busy\n",pdev->id);
++		return -EINVAL;
++	}
++
++	if(pdev->id != 16)
++		tcu_enable_counter(pdev->id);
++
++	tcu_start_counter(pdev->id);
++	tcu->channel_mask &= ~(BIT(pdev->id));
++	return 0;
++}
++
++static int tcu_clock_disable(struct platform_device *pdev)
++{
++	struct ingenic_tcu *tcu = dev_get_drvdata(pdev->dev.parent);
++	int id = pdev->id;
++	int index = tcu->idmap[id];
++	struct ingenic_tcu_chn *chn = &tcu->tcu_chn[index];
++
++	if(id != 16) {
++		switch (chn->irq_type) {
++		case FULL_IRQ_MODE :
++			tcu_unmask_full_irq(id);
++			tcu_clear_full_irq(id);
++			break;
++		case HALF_IRQ_MODE :
++			tcu_unmask_half_irq(id);
++			tcu_clear_half_irq(id);
++			break;
++		case FULL_HALF_IRQ_MODE :
++			tcu_unmask_full_irq(id);
++			tcu_unmask_half_irq(id);
++			tcu_clear_full_irq(id);
++			tcu_clear_half_irq(id);
++			break;
++		default :
++			break;
++		}
++		if(chn->is_count_clear) {
++			unsigned long flags;
++
++			tcu_disable_counter(id);
++			spin_lock_irqsave(&tcu->lock, flags);
++			tcu_clear_counter_to_zero(id);
++			spin_unlock_irqrestore(&tcu->lock, flags);
++		}
++	}
++	tcu_stop_counter(id);
++	tcu->channel_mask |= BIT(pdev->id);
++	return 0;
++}
++
++int ingenic_tcu_counter_begin(struct ingenic_tcu_chn *chn)
++{
++	int ret = 0;
++
++	if (chn->is_pwm) {
++		unsigned long flags;
++
++		spin_lock_irqsave(&tcu->lock, flags);
++		tcu_pwm_output_enable(chn->cib.id);
++		spin_unlock_irqrestore(&tcu->lock, flags);
++	}
++	tcu_enable_counter(chn->cib.id);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(ingenic_tcu_counter_begin);
++
++void ingenic_tcu_counter_stop(struct ingenic_tcu_chn *chn)
++{
++	if (chn->is_pwm) {
++		unsigned long flags;
++
++		spin_lock_irqsave(&tcu->lock, flags);
++		tcu_pwm_output_disable(chn->cib.id);
++		spin_unlock_irqrestore(&tcu->lock, flags);
++	}
++
++	tcu_disable_counter(chn->cib.id);
++}
++EXPORT_SYMBOL_GPL(ingenic_tcu_counter_stop);
++
++void ingenic_tcu_set_period(int id, uint16_t period)
++{
++	tcu_writel(tcu, CH_TDFR(id), period);
++}
++EXPORT_SYMBOL_GPL(ingenic_tcu_set_period);
++
++void ingenic_tcu_set_duty(int id, uint16_t duty)
++{
++	tcu_writel(tcu, CH_TDHR(id), duty);
++}
++EXPORT_SYMBOL_GPL(ingenic_tcu_set_duty);
++
++void ingenic_tcu_set_prescale(int id, enum tcu_prescale prescale)
++{
++	unsigned int val;
++	/* unsigned long flags; */
++
++	//spin_lock_irqsave(&tcu->lock, flags);
++	val = tcu_readl(tcu, CH_TCSR(id));
++	val &= ~(0x7 << 3);
++	val |= (prescale << 3);
++	tcu_writel(tcu, CH_TCSR(id), val);
++	//spin_unlock_irqrestore(&tcu->lock, flags);
++}
++EXPORT_SYMBOL_GPL(ingenic_tcu_set_prescale);
++
++void ingenic_tcu_set_pwm_output_init_level(int id, int level)
++{
++	unsigned int val;
++	/* unsigned long flags; */
++
++	//spin_lock_irqsave(&tcu->lock, flags);
++	val = tcu_readl(tcu, CH_TCSR(id));
++	if (level)
++		val |= (TCSR_PWM_HIGH);
++	else
++		val &= ~(TCSR_PWM_HIGH);
++	tcu_writel(tcu, CH_TCSR(id), val);
++	//spin_unlock_irqrestore(&tcu->lock, flags);
++}
++EXPORT_SYMBOL_GPL(ingenic_tcu_set_pwm_output_init_level);
++
++void ingenic_tcu_set_clksrc(int id, enum tcu_clksrc src)
++{
++	unsigned int val;
++	/* unsigned long flags; */
++
++	//spin_lock_irqsave(&tcu->lock, flags);
++	val = tcu_readl(tcu, CH_TCSR(id));
++	val &= ~0x7;
++	val |= src;
++	tcu_writel(tcu, CH_TCSR(id), val);
++
++	//spin_unlock_irqrestore(&tcu->lock, flags);
++}
++EXPORT_SYMBOL_GPL(ingenic_tcu_set_clksrc);
++
++int ingenic_tcu_get_count(int id)
++{
++	if(id == 1 || id == 2) {
++		int i = 0;
++		int tmp = 0;
++
++		while ((tmp == 0) && (i < 5)) {
++			tmp = tcu_readl(tcu, TCU_TSTR) & (1 << (id + 16));
++			i++;
++		}
++		if (tmp == 0)
++			return -EINVAL;
++	}
++	return tcu_get_counter(id);
++}
++EXPORT_SYMBOL_GPL(ingenic_tcu_get_count);
++
++void ingenic_tcu_channel_to_virq(struct ingenic_tcu_chn *chn)
++{
++	int index;
++
++	if(chn->cib.id == 5) {
++		chn->virq[0] = tcu->irq_tcu1;
++		return;
++	}
++	if(chn->cib.id == 15) {
++		chn->virq[0] = tcu->irq_tcu0;
++		return;
++	}
++	index = chn->cib.id * 2;
++
++	switch (chn->irq_type) {
++	case FULL_IRQ_MODE :
++		chn->virq[0] = irq_create_mapping(tcu->irq_domain, index);
++		break;
++	case HALF_IRQ_MODE :
++		chn->virq[1] = irq_create_mapping(tcu->irq_domain, index + 1);
++		break;
++	case FULL_HALF_IRQ_MODE :
++		chn->virq[0] = irq_create_mapping(tcu->irq_domain, index);
++		chn->virq[1] = irq_create_mapping(tcu->irq_domain, index + 1);
++		break;
++	default:
++		break;
++	}
++
++	if(chn->virq[0] < 0 || chn->virq[1] < 0)
++		return;
++
++	if(chn->virq[0])
++		irq_set_chip_data(chn->virq[0], chn);
++
++	if(chn->virq[1])
++		irq_set_chip_data(chn->virq[1], chn);
++}
++EXPORT_SYMBOL_GPL(ingenic_tcu_channel_to_virq);
++
++void ingenic_watchdog_set_count(unsigned int value)
++{
++	tcu_writel(tcu, WDT_TCNT, value);
++}
++EXPORT_SYMBOL_GPL(ingenic_watchdog_set_count);
++
++void ingenic_watchdog_config(unsigned int tcsr_val, unsigned int timeout_value)
++{
++	tcu_writel(tcu, WDT_TCER, 0);
++	tcu_writel(tcu, WDT_TCSR, tcsr_val);
++	tcu_writel(tcu, WDT_TDR, timeout_value);
++	tcu_writel(tcu, WDT_TCNT, 0);
++	tcu_writel(tcu, WDT_TCER, 1);
++}
++EXPORT_SYMBOL_GPL(ingenic_watchdog_config);
++
++static inline void tcu_disable_current_channel(int id)
++{
++	/* Stop current timer counter */
++  tcu_disable_counter(id);
++	/* Disable current timer clocks except for those used as system timers */
++  tcu_stop_counter(id);
++}
++
++struct mfd_cell *request_cell(int id)
++{
++	int i;
++	if (!(tcu->channel_mask & BIT(id))) {
++		dev_err(tcu->dev,
++				"current tcu channel %d busy\n",id);
++		return NULL;
++	}
++
++  tcu_disable_current_channel(id);
++	i = tcu->idmap[id];
++	tcu->channel_mask &= ~(BIT(id));
++
++	return &(tcu->tcu_cells[i]);
++}
++EXPORT_SYMBOL_GPL(request_cell);
++
++void free_cell(int id)
++{
++	tcu->channel_mask |= BIT(id);
++}
++EXPORT_SYMBOL_GPL(free_cell);
++
++static int check_pwm_is_availabl(struct ingenic_tcu_chn *chn)
++{
++	int id = chn->cib.id;
++	if(id != 15) {
++		if(chn->is_pwm && !(chn->cib.func & PWM_FUNC)) {
++			dev_err(tcu->dev, "channel %d not support pwm function\n", id);
++			return -1;
++		} else if(!chn->is_pwm && !(chn->cib.func & TRACKBALL_FUNC)) {
++			dev_err(tcu->dev, "channel %d not support trackball function\n", id);
++			return -1;
++		}
++		if(chn->pwm_in_en && !chn->cib.pwmin) {
++			dev_err(tcu->dev, "channel %d not support pwm in function\n", id);
++			return -1;
++		}
++	}
++	return 0;
++}
++
++int ingenic_tcu_config(struct ingenic_tcu_chn *chn)
++{
++    unsigned long flags;
++    int id = chn->cib.id;
++
++    if(check_pwm_is_availabl(chn) < 0)
++	return -1;
++    /*
++      tcu lock should be used to lock all tcu register update.
++      example: led-pwm work thread and pwm suspend maybe update TSR
++      at the same time.
++     */
++    spin_lock_irqsave(&tcu->lock, flags);
++    tcu_set_start_state(id);
++
++    tcu_clear_full_irq(id);
++    tcu_clear_half_irq(id);
++
++    switch (chn->irq_type) {
++    case NULL_IRQ_MODE :
++        tcu_mask_full_irq(id);
++        tcu_mask_half_irq(id);
++        tcu_clear_full_irq(id);
++        tcu_clear_half_irq(id);
++        break;
++    case FULL_IRQ_MODE :
++        tcu_unmask_full_irq(id);
++        tcu_mask_half_irq(id);
++        tcu_clear_full_irq(id);
++        break;
++    case HALF_IRQ_MODE :
++        tcu_mask_full_irq(id);
++        tcu_unmask_half_irq(id);
++	tcu_clear_half_irq(id);
++	break;
++    case FULL_HALF_IRQ_MODE :
++	tcu_unmask_full_irq(id);
++	tcu_unmask_half_irq(id);
++	tcu_clear_full_irq(id);
++	tcu_clear_half_irq(id);
++	break;
++    default :
++	break;
++    }
++
++    ingenic_tcu_set_pwm_output_init_level(id, chn->init_level);
++    if(chn->cib.mode == TCU_MODE1) {
++	    tcu_set_pwm_shutdown(id, chn->shutdown_mode);
++    }
++
++    if (chn->is_pwm) {
++	    /*
++	       configure just do configuer, pwm should
++	       be enable through pwm_enable interface.
++	       This is standard usage of pwm interface.
++	       */
++	    if(chn->pwm_bapass_mode) {
++		    if(chn->clk_src == TCU_CLKSRC_PCK) {
++			    dev_err(tcu->dev, "the current version can not bypass pclk\n");
++		    }
++		    tcu_pwm_bypass_enable(id);
++	    } else {
++		    tcu_pwm_bypass_disable(id);
++	    }
++    } else {
++	    tcu_pwm_output_disable(id);
++    }
++
++    ingenic_tcu_set_prescale(id, chn->clk_div);
++    set_tcu_full_half_value(id, chn->full_num, chn->half_num);
++    if (chn->pwm_in_en)
++	    tcu_pwm_input_enable(id);
++    else
++	    tcu_pwm_input_disable(id);
++    ingenic_tcu_set_clksrc(id, chn->clk_src);
++    tcu_clear_counter_to_zero(id);
++
++    spin_unlock_irqrestore(&tcu->lock, flags);
++    return 0;
++}
++EXPORT_SYMBOL_GPL(ingenic_tcu_config);
++
++static void tcu_irq_mask(struct irq_data *data)
++{
++	struct ingenic_tcu_chn *chn = irq_data_get_irq_chip_data(data);
++	int id = chn->cib.id;
++
++	switch (chn->irq_type) {
++	case FULL_IRQ_MODE :
++		tcu_mask_full_irq(id);
++		break;
++	case HALF_IRQ_MODE :
++		tcu_mask_half_irq(id);
++		break;
++	case FULL_HALF_IRQ_MODE :
++		tcu_mask_full_irq(id);
++		tcu_mask_half_irq(id);
++		break;
++	default:
++		break;
++	}
++}
++
++static void tcu_irq_unmask(struct irq_data *data)
++{
++	struct ingenic_tcu_chn *chn = irq_data_get_irq_chip_data(data);
++	int id = chn->cib.id;
++
++	switch (chn->irq_type) {
++	case FULL_IRQ_MODE :
++		tcu_unmask_full_irq(id);
++		break;
++	case HALF_IRQ_MODE :
++		tcu_unmask_half_irq(id);
++		break;
++	case FULL_HALF_IRQ_MODE :
++		tcu_unmask_full_irq(id);
++		tcu_unmask_half_irq(id);
++		break;
++	default:
++		break;
++	}
++}
++
++static void tcu_mask_and_ack_irq(struct irq_data *data)
++{
++	struct ingenic_tcu_chn *chn = irq_data_get_irq_chip_data(data);
++	int id = chn->cib.id;
++
++	switch (chn->irq_type) {
++	case FULL_IRQ_MODE :
++		tcu_mask_full_irq(id);
++		tcu_clear_full_irq(id);
++		break;
++	case HALF_IRQ_MODE :
++		tcu_mask_half_irq(id);
++		tcu_clear_half_irq(id);
++		break;
++	case FULL_HALF_IRQ_MODE :
++		tcu_mask_full_irq(id);
++		tcu_mask_half_irq(id);
++		tcu_clear_full_irq(id);
++		tcu_clear_half_irq(id);
++		break;
++	default :
++		break;
++	}
++}
++
++static struct irq_chip tcu_irq_chip = {
++	.name = "ingenic-tcu_v1",
++	.irq_disable = tcu_mask_and_ack_irq,
++	.irq_enable = tcu_irq_unmask,
++	.irq_unmask	= tcu_irq_unmask,
++	.irq_mask	= tcu_irq_mask,
++	.irq_mask_ack = tcu_mask_and_ack_irq,
++};
++
++static int tcu2_irq_domain_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw)
++{
++	struct ingenic_tcu *tcu = d->host_data;
++
++	irq_set_chip_data(virq, tcu);
++	irq_set_chip_and_handler(virq, &tcu_irq_chip, handle_level_irq);
++	return 0;
++}
++
++static const struct irq_domain_ops tcu2_irq_domain_ops = {
++	.map = tcu2_irq_domain_map,
++	.xlate = irq_domain_xlate_onetwocell,
++};
++
++static void tcu_irq_demux(struct irq_desc *desc)
++{
++	struct ingenic_tcu *tcu = irq_desc_get_handler_data(desc);
++	unsigned long pend, mask, tcu2_pend = 0;
++
++	pend = readl(tcu->base + TCU_TFR);
++	mask = readl(tcu->base + TCU_TMR) | (1 << 5 | 1 << (5 + 16));
++
++	pend = pend & ~(mask);
++	while(pend) {
++		struct ingenic_tcu_chn *chn;
++		int index;
++
++		tcu2_pend = ffs(pend) - 1;
++		index = tcu->idmap[tcu2_pend];
++		chn = &tcu->tcu_chn[index];
++		if ((pend & 0xffff)){
++			generic_handle_irq(chn->virq[FULL_BIT]);
++		} else {
++			generic_handle_irq(chn->virq[HALF_BIT]);
++		}
++		pend &= ~(1 << tcu2_pend);
++	}
++}
++
++static int __init setup_tcu_irq(struct ingenic_tcu *tcu)
++{
++	irq_set_chip_and_handler(tcu->irq_tcu0, &tcu_irq_chip, handle_level_irq);
++	irq_set_chip_and_handler(tcu->irq_tcu1, &tcu_irq_chip, handle_level_irq);
++
++	tcu->irq_domain = irq_domain_add_linear(tcu->np, tcu->channel_irq_num, &tcu2_irq_domain_ops, (void *)tcu);
++	if(!tcu->irq_domain) {
++		pr_err("Failed to add tcu irq into irq domain\n");
++		return -ENOMEM;
++	}
++	irq_set_chained_handler_and_data(tcu->irq_tcu2, tcu_irq_demux, tcu);
++
++	return 0;
++}
++
++static int init_mfd_cells(struct ingenic_tcu *tcu, struct mfd_cell *cells)
++{
++	struct device_node *child;
++	int i = 0, ret;
++
++	for_each_child_of_node(tcu->np, child) {
++		const char *tmp = NULL;
++		int id;
++		struct ingenic_tcu_chn *chn = &tcu->tcu_chn[i];
++
++		ret = of_property_read_u32(child, "ingenic,channel-info", &chn->chn_info);
++		if (ret < 0) {
++			dev_err(tcu->dev, "Cannot get ingenic,channel-info\n");
++			return -ENOENT;
++		}
++		ret = of_property_read_string(child, "compatible", &tmp);
++		if (ret < 0) {
++			dev_err(tcu->dev, "Cannot get compatible string\n");
++			return -ENOENT;
++		}
++
++		id = chn->cib.id;
++		tcu->idmap[id] = i;
++		tcu->channel_mask |= BIT(id);
++		chn->enable = tcu_start_counter;
++		chn->disable = tcu_stop_counter;
++		cells[i].id = id;
++		cells[i].name = tmp;
++		cells[i].pdata_size = sizeof(struct ingenic_tcu_chn);
++		cells[i].of_compatible = tmp;
++		cells[i].platform_data = chn;
++		cells[i].enable = tcu_clock_enable;
++		cells[i].disable = tcu_clock_disable;
++		i ++;
++	}
++	/* for(i = 0; i < tcu->channel_num; i++) { */
++	/* 	printk("id = %d, name = %s, of_com = %s\n", cells[i].id, cells[i].name, cells[i].of_compatible); */
++	/* } */
++	return 0;
++}
++static int ingenic_tcu_probe(struct platform_device *pdev)
++{
++	struct resource *res;
++	int ret = 0;
++
++	tcu = devm_kzalloc(&pdev->dev, sizeof(struct ingenic_tcu), GFP_KERNEL);
++	if (!tcu) {
++		dev_err(&pdev->dev, "Failed to allocate driver structure\n");
++		return -ENOMEM;
++	}
++
++	tcu->np = pdev->dev.of_node;
++	tcu->dev = &pdev->dev;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (res == NULL) {
++		dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
++		return -ENOENT;
++	}
++	tcu->base = ioremap(res->start, resource_size(res));
++	if (tcu->base == NULL) {
++		dev_err(&pdev->dev, "Cannot map IO\n");
++		return -ENXIO;
++	}
++	tcu->irq_tcu0 = of_irq_get_byname(tcu->np, "tcu_int0");
++	if (tcu->irq_tcu0 < 0) {
++		dev_err(tcu->dev, "int0:unable to get IRQ from DT, %d\n", tcu->irq_tcu0);
++		return -ENXIO;
++	}
++	tcu->irq_tcu1 = of_irq_get_byname(tcu->np, "tcu_int1");
++	if (tcu->irq_tcu1 < 0) {
++		dev_err(tcu->dev, "int1:unable to get IRQ from DT, %d\n", tcu->irq_tcu1);
++		return -ENXIO;
++	}
++	tcu->irq_tcu2 = of_irq_get_byname(tcu->np, "tcu_int2");
++	if (tcu->irq_tcu2 < 0) {
++		dev_err(tcu->dev, "int2:unable to get IRQ from DT, %d\n", tcu->irq_tcu2);
++		return -ENXIO;
++	}
++
++	tcu->clk = devm_clk_get(tcu->dev,"gate_tcu");
++	clk_prepare_enable(tcu->clk);
++
++	tcu->channel_num = of_get_child_count(tcu->np);
++	tcu->tcu_chn = devm_kzalloc(tcu->dev, sizeof(struct ingenic_tcu_chn) * tcu->channel_num,
++								GFP_KERNEL);
++	if (!tcu->tcu_chn) {
++		dev_err(tcu->dev, "Failed to allocate driver structure tcu_channel\n");
++		return -ENOMEM;
++	}
++	tcu->channel_irq_num = (tcu->channel_num - 1) * 2;
++
++	setup_tcu_irq(tcu);
++
++	spin_lock_init(&tcu->lock);
++	platform_set_drvdata(pdev, tcu);
++
++	tcu->tcu_cells = devm_kzalloc(tcu->dev, sizeof(struct mfd_cell) * tcu->channel_num,
++						 GFP_KERNEL);
++	if (!tcu->tcu_cells) {
++		dev_err(tcu->dev, "Failed to allocate driver structure cells\n");
++		return -ENOMEM;
++	}
++
++	init_mfd_cells(tcu, tcu->tcu_cells);
++
++	ret = mfd_add_devices(&pdev->dev, 0, tcu->tcu_cells,
++						  tcu->channel_num, res, tcu->irq_tcu0, NULL);
++
++	dev_info(&pdev->dev, "Ingenic TCU driver register completed ret = %d\n", ret);
++
++	return 0;
++}
++
++static int ingenic_tcu_remove(struct platform_device *pdev)
++{
++	struct ingenic_tcu *tcu = platform_get_drvdata(pdev);
++
++	clk_disable_unprepare(tcu->clk);
++
++	mfd_remove_devices(&pdev->dev);
++
++	irq_set_handler_data(tcu->irq_tcu0, NULL);
++	irq_set_chained_handler(tcu->irq_tcu0, NULL);
++
++	irq_set_handler_data(tcu->irq_tcu1, NULL);
++	irq_set_chained_handler(tcu->irq_tcu1, NULL);
++
++	platform_set_drvdata(pdev, NULL);
++
++	devm_kfree(&pdev->dev, tcu);
++
++	return 0;
++}
++
++static const struct of_device_id tcu_match[] = {
++	{ .compatible = "ingenic,x2500-tcu", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, tcu_match);
++
++static struct platform_driver ingenic_tcu_driver = {
++	.probe	= ingenic_tcu_probe,
++	.remove	= ingenic_tcu_remove,
++	.driver = {
++		.name = "ingenic-tcu_v1",
++		.of_match_table = tcu_match,
++	},
++};
++
++module_platform_driver(ingenic_tcu_driver);
++
++MODULE_DESCRIPTION("ingenic SoC TCU driver");
++MODULE_AUTHOR("bo.liu <bo.liu@ingenic.com>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-tcu");
+diff --git a/module_drivers/drivers/mfd/ingenic_adc_aux.c b/module_drivers/drivers/mfd/ingenic_adc_aux.c
+new file mode 100644
+index 000000000..dcb56467b
+--- /dev/null
++++ b/module_drivers/drivers/mfd/ingenic_adc_aux.c
+@@ -0,0 +1,362 @@
++/**
++ * drivers/mfd/ingenic-adc-aux.c
++ *
++ * aux1 aux2 channels voltage sample interface for Ingenic SoC
++ *
++ * Copyright(C)2012 Ingenic Semiconductor Co., LTD.
++ * http://www.ingenic.cn
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License.
++ */
++
++#include <linux/err.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/io.h>
++#include <linux/cdev.h>
++#include <linux/spinlock.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++#include <linux/proc_fs.h>
++#include <linux/mfd/core.h>
++#include <linux/delay.h>
++#include <linux/vmalloc.h>/*for vfree*/
++#include <linux/miscdevice.h>
++
++#include <irq.h>
++
++#ifdef CONFIG_SADC_AUX_VERF_3V3
++static unsigned int VREF_ADC = 3300;
++#else
++static unsigned int VREF_ADC = 1800;
++#endif
++
++#ifdef CONFIG_SADC_AUX_12BIT
++#define AUXCONST	4096
++#define AUX_VOLT_LOW	0xfff
++#define AUX_VOLT_HIGH	0xfff0000
++#else
++#define AUXCONST   1024
++#define AUX_VOLT_LOW	0x3ff
++#define AUX_VOLT_HIGH	0x3ff0000
++#endif
++
++#define ADC_MAGIC_NUMBER	'A'
++#define ADC_ENABLE			_IO(ADC_MAGIC_NUMBER, 11)
++#define ADC_DISABLE			_IO(ADC_MAGIC_NUMBER, 22)
++#define ADC_SET_VREF		_IOW(ADC_MAGIC_NUMBER, 33, unsigned int)
++
++#ifndef BITS_H2L
++#define BITS_H2L(msb, lsb)  ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))
++#endif
++
++/**
++ *  * INIT_COMPLETION - reinitialize a completion structure
++ *   * @x:  completion structure to be reinitialized
++ *    *
++ *     * This macro should be used to reinitialize a completion structure so it can
++ *      * be reused. This is especially important after complete_all() is used.
++ *       */
++#define INIT_COMPLETION(x)      ((x).done = 0)
++
++
++struct ingenic_adc_aux {
++	struct platform_device *pdev;
++
++	struct resource *mem;
++	void __iomem *base;
++
++	int irq;
++
++	const struct mfd_cell *cell;
++
++	unsigned int voltage;
++
++	struct completion read_completion;
++
++	struct miscdevice mdev;
++};
++
++
++enum aux_ch {
++	SADC_AUX0,
++	SADC_AUX1,
++	SADC_AUX2,
++	SADC_AUX3,
++	SADC_AUX4,
++	SADC_AUX5,
++};
++extern int ingenic_adc_set_config(struct device *dev, uint32_t mask, uint32_t val);
++
++static irqreturn_t ingenic_ingenic_adc_aux_irq_handler(int irq, void *devid)
++{
++	struct ingenic_adc_aux *ingenic_adc_aux = (struct ingenic_adc_aux *)devid;
++
++	complete(&ingenic_adc_aux->read_completion);
++
++	return IRQ_HANDLED;
++}
++
++static int ingenic_adc_aux_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	//struct ingenic_adc_aux *adc_aux = platform_get_drvdata(pdev);
++	//adc_aux->cell->disable(pdev);
++	return 0;
++}
++
++static int ingenic_adc_aux_resume(struct platform_device *pdev)
++{
++	//struct ingenic_adc_aux *adc_aux = platform_get_drvdata(pdev);
++	//adc_aux->cell->enable(pdev);
++	return 0;
++}
++
++int ingenic_adc_aux_sample_volt(enum aux_ch channels,struct ingenic_adc_aux *ingenic_adc_aux)
++{
++	unsigned long tmp;
++	unsigned int sadc_volt = 0;
++
++	if (!ingenic_adc_aux) {
++		printk("ingenic_adc_aux is null ! return\n");
++		return -EINVAL;
++	}
++
++	INIT_COMPLETION(ingenic_adc_aux->read_completion);
++
++	ingenic_adc_aux->cell->enable(ingenic_adc_aux->pdev);
++	enable_irq(ingenic_adc_aux->irq);
++
++restart:
++	tmp = wait_for_completion_interruptible_timeout(&ingenic_adc_aux->read_completion, HZ);
++	if (tmp > 0) {
++		if( (channels == 0) || (channels ==2 ) )
++			sadc_volt = readl(ingenic_adc_aux->base) & AUX_VOLT_LOW;
++		else
++			sadc_volt = (readl(ingenic_adc_aux->base - 2) & AUX_VOLT_HIGH) >> 16;
++	} else if(tmp == -ERESTARTSYS){
++		goto restart;
++	}
++	else {
++		sadc_volt = tmp ? tmp : -ETIMEDOUT;
++	}
++
++	if (sadc_volt < 0) {
++		printk("ingenic_adc_aux read value error!!\n");
++		disable_irq(ingenic_adc_aux->irq);
++		ingenic_adc_aux->cell->disable(ingenic_adc_aux->pdev);
++		return -EIO;
++	}
++
++	disable_irq(ingenic_adc_aux->irq);
++	ingenic_adc_aux->cell->disable(ingenic_adc_aux->pdev);
++
++	sadc_volt = sadc_volt * VREF_ADC / AUXCONST;
++
++	return sadc_volt;
++}
++
++
++int ingenic_adc_aux_open(struct inode *inode, struct file *filp)
++{
++	//struct miscdevice *dev = filp->private_data;
++	//struct ingenic_adc_aux *axu = container_of(dev, struct ingenic_adc_aux, mdev);
++	return 0;
++}
++
++int ingenic_adc_aux_release(struct inode *inode, struct file *filp)
++{
++	return 0;
++}
++
++ssize_t ingenic_adc_aux_read(struct file *filp, char *buf, size_t len, loff_t *off)
++{
++	unsigned int sadc_val = 0;
++	struct miscdevice *dev = filp->private_data;
++	struct ingenic_adc_aux *aux = container_of(dev, struct ingenic_adc_aux, mdev);
++
++	sadc_val = ingenic_adc_aux_sample_volt(aux->pdev->id,aux);
++	if (sadc_val < 0) {
++		printk("ingenic_adc_aux read value error !!\n");
++		return -EINVAL;
++	}
++
++	if(copy_to_user(buf, &sadc_val, sizeof(int))) {
++		return -EFAULT;
++	}
++
++	return sizeof(int);
++}
++
++static long ingenic_adc_aux_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
++{
++	int ret = 0;
++	struct miscdevice *dev = filp->private_data;
++	struct ingenic_adc_aux *adc_aux = container_of(dev, struct ingenic_adc_aux, mdev);
++
++	if(_IOC_TYPE(cmd) == ADC_MAGIC_NUMBER) {
++		switch (cmd) {
++			case ADC_ENABLE:
++				ret = adc_aux->cell->enable(adc_aux->pdev);
++				break;
++			case ADC_DISABLE:
++				ret = adc_aux->cell->disable(adc_aux->pdev);
++				break;
++			case ADC_SET_VREF:
++				VREF_ADC = *(unsigned int *)arg;
++				printk("VREF_ADC=%d\n",VREF_ADC);
++				break;
++			default:
++				ret = -1;
++				printk("%s:unsupported ioctl cmd\n",__func__);
++		}
++	}
++
++
++	return ret;
++}
++
++struct file_operations ingenic_adc_aux_fops= {
++	.owner= THIS_MODULE,
++	.open= ingenic_adc_aux_open,
++	.release= ingenic_adc_aux_release,
++	.read= ingenic_adc_aux_read,
++	.unlocked_ioctl= ingenic_adc_aux_ioctl,
++};
++
++extern int key_fun_init(struct ingenic_adc_aux *ingenic_adc_aux);
++static int ingenic_adc_aux_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	char aux_name[20];
++
++	struct ingenic_adc_aux *ingenic_adc_aux = NULL;
++
++	ingenic_adc_aux = kzalloc(sizeof(*ingenic_adc_aux), GFP_KERNEL);
++	if (!ingenic_adc_aux) {
++		dev_err(&pdev->dev, "Failed to allocate driver structre\n");
++		return -ENOMEM;
++	}
++
++	ingenic_adc_aux->cell = mfd_get_cell(pdev);
++	if (!ingenic_adc_aux->cell) {
++		ret = -ENOENT;
++		dev_err(&pdev->dev, "Failed to get mfd cell for ingenic_adc_aux!\n");
++		goto err_free;
++	}
++
++	ingenic_adc_aux->irq = platform_get_irq(pdev, 0);
++	if (ingenic_adc_aux->irq < 0) {
++		ret = ingenic_adc_aux->irq;
++		dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
++		goto err_free;
++	}
++
++	ingenic_adc_aux->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!ingenic_adc_aux->mem) {
++		ret = -ENOENT;
++		dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
++		goto err_free;
++	}
++
++	ingenic_adc_aux->mem = request_mem_region(ingenic_adc_aux->mem->start,
++			resource_size(ingenic_adc_aux->mem), pdev->name);
++	if (!ingenic_adc_aux->mem) {
++		ret = -EBUSY;
++		dev_err(&pdev->dev, "Failed to request mmio memory region\n");
++		goto err_free;
++	}
++
++	ingenic_adc_aux->base = ioremap(ingenic_adc_aux->mem->start,resource_size(ingenic_adc_aux->mem));
++	if (!ingenic_adc_aux->base) {
++		ret = -EBUSY;
++		dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
++		goto err_free;
++	}
++
++	ingenic_adc_aux->pdev = pdev;
++	ingenic_adc_aux->mdev.minor = MISC_DYNAMIC_MINOR;
++	sprintf(aux_name, "ingenic_adc_aux_%d", pdev->id);
++	ingenic_adc_aux->mdev.name = aux_name;
++	ingenic_adc_aux->mdev.fops = &ingenic_adc_aux_fops;
++
++	ret = misc_register(&ingenic_adc_aux->mdev);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "misc_register failed\n");
++		goto err_free;
++	}
++
++	init_completion(&ingenic_adc_aux->read_completion);
++
++	ret = request_irq(ingenic_adc_aux->irq, ingenic_ingenic_adc_aux_irq_handler, 0, pdev->name, ingenic_adc_aux);
++	if (ret) {
++		dev_err(&pdev->dev, "Failed to request irq %d\n", ret);
++		goto err_free;
++	}
++
++	disable_irq(ingenic_adc_aux->irq);
++
++	platform_set_drvdata(pdev, ingenic_adc_aux);
++
++#ifdef CONFIG_ADC_BASED_KEY_FUN
++	if (!strncmp(aux_name, "ingenic_adc_aux_1", strlen("ingenic_adc_aux_1")))
++		key_fun_init(ingenic_adc_aux);
++#endif
++
++	printk("ingenic sadc aux%d probe success\n", pdev->id);
++	return 0;
++
++err_free :
++	kfree(ingenic_adc_aux);
++	return ret;
++
++}
++
++static int ingenic_adc_aux_remove(struct platform_device *pdev)
++{
++	struct ingenic_adc_aux *ingenic_adc_aux = platform_get_drvdata(pdev);
++
++	misc_deregister(&ingenic_adc_aux->mdev);
++	free_irq(ingenic_adc_aux->irq, ingenic_adc_aux);
++	iounmap(ingenic_adc_aux->base);
++	release_mem_region(ingenic_adc_aux->mem->start,resource_size(ingenic_adc_aux->mem));
++	kfree(ingenic_adc_aux);
++
++	return 0;
++}
++
++static struct platform_driver ingenic_adc_aux_driver = {
++	.probe	= ingenic_adc_aux_probe,
++	.remove	= ingenic_adc_aux_remove,
++	.driver = {
++		.name	= "ingenic-aux",
++		.owner	= THIS_MODULE,
++	},
++	.suspend	= ingenic_adc_aux_suspend,
++	.resume		= ingenic_adc_aux_resume,
++};
++
++static int __init ingenic_adc_aux_init(void)
++{
++	platform_driver_register(&ingenic_adc_aux_driver);
++
++	return 0;
++}
++
++static void __exit ingenic_adc_aux_exit(void)
++{
++	platform_driver_unregister(&ingenic_adc_aux_driver);
++}
++
++module_init(ingenic_adc_aux_init);
++module_exit(ingenic_adc_aux_exit);
++
++MODULE_ALIAS("platform: ingenic ingenic_adc_aux");
++MODULE_AUTHOR("Guo Xu<xu.guo@ingenic.com>");
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("ingenic adc aux sample driver");
+diff --git a/module_drivers/drivers/mfd/ingenic_adc_v13.c b/module_drivers/drivers/mfd/ingenic_adc_v13.c
+new file mode 100644
+index 000000000..84d080927
+--- /dev/null
++++ b/module_drivers/drivers/mfd/ingenic_adc_v13.c
+@@ -0,0 +1,517 @@
++/* drivers/mfd/ingenic_adc.c
++ *
++ * Copyright (C) 2012 Ingenic Semiconductor Co., Ltd.
++ *      http://www.ingenic.com
++ *      Sun Jiwei<jwsun@ingenic.cn>
++ * ingenic4780 SOC ADC device core
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This driver is designed to control the usage of the ADC block between
++ * the touchscreen and any other drivers that may need to use it, such as
++ * the hwmon driver.
++ */
++
++#include <linux/err.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++
++#include <linux/delay.h>
++#include <linux/clk.h>
++#include <linux/mfd/core.h>
++
++#include <linux/mfd/ingenic_adc.h>
++#include <irq.h>
++#include <linux/of_irq.h>
++
++#define INGENIC_REG_ADC_ENABLE       0x00
++#define INGENIC_REG_ADC_CTRL         0x08
++#define INGENIC_REG_ADC_STATUS       0x0c
++
++#define INGENIC_REG_ADC_AUX_BASE     0x10
++#define INGENIC_REG_ADC_CLKDIV	     0x20
++/*
++ *the following registeres is for touchscreen<junyang@ingenic.cn>
++ */
++#define CLKDIV		120
++#define CLKDIV_US       2
++#define CLKDIV_MS       200
++
++#define INGENIC_ADC_IRQ_NUM	8
++
++static const struct of_device_id sadc_match[];
++
++struct ingenic_adc_priv {
++	unsigned int aux_channels;
++};
++
++struct ingenic_adc {
++	struct resource *mem;
++	void __iomem *base;
++
++	int irq;
++	int irq_base;
++	struct irq_domain *irq_domain;
++	struct device_node *np;
++	struct resource *aux_res_ptr;
++	struct mfd_cell *adc_cells;
++
++	struct clk *clk;
++	atomic_t clk_ref;
++
++	spinlock_t lock;
++	const struct ingenic_adc_priv *priv;/*soc data*/
++};
++
++static inline void ingenic_adc_irq_set_masked(struct ingenic_adc *adc, int irq,
++		bool masked)
++{
++	unsigned long flags;
++	uint8_t val;
++
++	irq -= adc->irq_base;
++
++	spin_lock_irqsave(&adc->lock, flags);
++
++	val = readb(adc->base + INGENIC_REG_ADC_CTRL);
++	if (masked) {
++		val |= BIT(irq);
++	}
++	else {
++		val &= ~BIT(irq);
++	}
++	writeb(val, adc->base + INGENIC_REG_ADC_CTRL);
++
++	spin_unlock_irqrestore(&adc->lock, flags);
++}
++
++static void ingenic_adc_irq_mask(struct irq_data *data)
++{
++	struct ingenic_adc *adc = irq_data_get_irq_chip_data(data);
++	ingenic_adc_irq_set_masked(adc, data->irq, true);
++}
++
++static void ingenic_adc_irq_unmask(struct irq_data *data)
++{
++	struct ingenic_adc *adc = irq_data_get_irq_chip_data(data);
++	ingenic_adc_irq_set_masked(adc, data->irq, false);
++}
++
++static void ingenic_adc_irq_ack(struct irq_data *data)
++{
++	struct ingenic_adc *adc = irq_data_get_irq_chip_data(data);
++	unsigned int irq = data->irq - adc->irq_base;
++	writeb(BIT(irq), adc->base + INGENIC_REG_ADC_STATUS);
++}
++
++static struct irq_chip ingenic_adc_irq_chip = {
++	.name = "ingenic-adc",
++	.irq_mask = ingenic_adc_irq_mask,
++	.irq_disable = ingenic_adc_irq_mask,
++	.irq_unmask = ingenic_adc_irq_unmask,
++	.irq_ack = ingenic_adc_irq_ack,
++};
++
++static void ingenic_adc_irq_demux(struct irq_desc *desc)
++{
++	struct ingenic_adc *adc = irq_desc_get_handler_data(desc);
++	uint8_t status;
++	unsigned int i;
++
++	status = readb(adc->base + INGENIC_REG_ADC_STATUS);
++
++	for (i = 0; i < adc->priv->aux_channels; i++) {
++		if (status & BIT(i)) {
++			generic_handle_irq(irq_find_mapping(adc->irq_domain, i));
++		}
++	}
++}
++
++
++static inline void ingenic_adc_enable(struct ingenic_adc *adc)
++{
++	uint16_t val;
++
++	if (atomic_inc_return(&adc->clk_ref) == 1) {
++		val = readw(adc->base + INGENIC_REG_ADC_ENABLE);
++		val &= ~BIT(15);
++		writew(val, adc->base + INGENIC_REG_ADC_ENABLE);
++		msleep(5);
++	}
++}
++
++static inline void ingenic_adc_disable(struct ingenic_adc *adc)
++{
++	uint16_t val;
++
++	if (atomic_dec_return(&adc->clk_ref) == 0) {
++		val = readw(adc->base + INGENIC_REG_ADC_ENABLE);
++		val |= BIT(15);
++		writew(val, adc->base + INGENIC_REG_ADC_ENABLE);
++	}
++}
++
++static inline void ingenic_adc_set_enabled(struct ingenic_adc *adc, int engine,
++		bool enabled)
++{
++	unsigned long flags;
++	uint16_t val;
++
++	spin_lock_irqsave(&adc->lock, flags);
++
++	val = readw(adc->base + INGENIC_REG_ADC_ENABLE);
++	if (enabled) {
++		val |= BIT(engine);
++	}
++	else {
++		val &= ~BIT(engine);
++	}
++	writew(val, adc->base + INGENIC_REG_ADC_ENABLE);
++
++	spin_unlock_irqrestore(&adc->lock, flags);
++}
++
++static int ingenic_adc_cell_enable(struct platform_device *pdev)
++{
++	struct ingenic_adc *adc = dev_get_drvdata(pdev->dev.parent);
++
++	ingenic_adc_enable(adc);
++	ingenic_adc_set_enabled(adc, pdev->id, true);
++
++	return 0;
++}
++
++static int ingenic_adc_cell_disable(struct platform_device *pdev)
++{
++	struct ingenic_adc *adc = dev_get_drvdata(pdev->dev.parent);
++
++	ingenic_adc_set_enabled(adc, pdev->id, false);
++	ingenic_adc_disable(adc);
++
++	return 0;
++}
++
++
++int adc_write_reg(struct device *dev ,uint8_t addr_offset,uint32_t mask,uint32_t val)
++{
++	struct ingenic_adc *adc = dev_get_drvdata(dev);
++	unsigned long flags;
++	uint32_t value;
++	if(!adc)
++		return -ENODEV;
++	spin_lock_irqsave(&adc->lock,flags);
++
++	value = readl(adc->base + addr_offset);
++	value &= ~mask;
++	value |= val;
++	writel(value,adc->base + addr_offset);
++	spin_unlock_irqrestore(&adc->lock,flags);
++	return 0;
++}
++uint32_t adc_read_reg(struct device *dev,uint8_t addr_offset)
++{
++	struct ingenic_adc *adc = dev_get_drvdata(dev);
++	unsigned long flags;
++	uint32_t ret;
++	if(!adc)
++		return -ENODEV;
++	spin_lock_irqsave(&adc->lock,flags);
++	ret = readl(adc->base + addr_offset);
++	spin_unlock_irqrestore(&adc->lock,flags);
++	return ret;
++}
++
++
++static void ingenic_adc_clk_div(struct ingenic_adc *adc, const unsigned char clkdiv,
++		const unsigned char clkdiv_us, const unsigned short clkdiv_ms)
++{
++	unsigned int val;
++
++	val = clkdiv | (clkdiv_us << 8) | (clkdiv_ms << 16);
++	writel(val, adc->base + INGENIC_REG_ADC_CLKDIV);
++}
++
++static int ingenic_alloc_aux_resources(struct ingenic_adc *adc)
++{
++	struct resource *r = NULL;
++	unsigned int i = 0;
++
++	adc->aux_res_ptr = kzalloc(sizeof(struct resource) * adc->priv->aux_channels * 2, GFP_KERNEL);
++	if(!adc->aux_res_ptr) {
++		return -ENOMEM;
++	}
++
++	for(i = 0; i < adc->priv->aux_channels; i++) {
++		r = &adc->aux_res_ptr[i * 2];
++		r[0].start = i;
++		r[0].flags = IORESOURCE_IRQ;
++		r[1].start = INGENIC_REG_ADC_AUX_BASE + 2 * i;
++		r[1].end   = INGENIC_REG_ADC_AUX_BASE + 2 * i + 1;
++		r[1].flags = IORESOURCE_MEM;
++	}
++	return 0;
++}
++
++static int ingenic_alloc_adc_cells(struct ingenic_adc *adc)
++{
++	unsigned int i;
++
++	adc->adc_cells = kzalloc(sizeof(struct mfd_cell) * adc->priv->aux_channels, GFP_KERNEL);
++	if(!adc->adc_cells) {
++		return -ENOMEM;
++	}
++
++	for(i = 0; i < adc->priv->aux_channels; i++) {
++		adc->adc_cells[i].id = i;
++		adc->adc_cells[i].name = "ingenic-aux";
++		adc->adc_cells[i].num_resources = 2;
++		adc->adc_cells[i].resources = &adc->aux_res_ptr[i * 2];
++		adc->adc_cells[i].enable = ingenic_adc_cell_enable;
++		adc->adc_cells[i].disable = ingenic_adc_cell_disable;
++	}
++	return 0;
++}
++
++static int adc_irq_domain_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw)
++{
++	struct ingenic_adc *adc = d->host_data;
++	if(hw == 0) {
++		adc->irq_base = virq;
++	}
++	irq_set_chip_data(virq, adc);
++	irq_set_chip_and_handler(virq, &ingenic_adc_irq_chip, handle_level_irq);
++	return 0;
++}
++
++static const struct irq_domain_ops ingenic_adc_irq_domain_ops = {
++	.map = adc_irq_domain_map,
++	.xlate = irq_domain_xlate_onetwocell,
++};
++
++static int setup_adc_irq(struct ingenic_adc *adc, struct device_node *np)
++{
++	int i, ret;
++
++	adc->irq = irq_of_parse_and_map(np, 0);
++	if (!adc->irq)
++		return -EINVAL;
++
++	adc->irq_domain = irq_domain_add_linear(np, adc->priv->aux_channels, &ingenic_adc_irq_domain_ops, (void *)adc);
++	if (!adc->irq_domain)
++		return -ENOMEM;
++
++	for(i = 0; i < adc->priv->aux_channels; i++) {
++		ret = irq_create_mapping(adc->irq_domain, i);
++		if(ret < 0) {
++			return -1;
++		}
++	}
++	irq_set_handler_data(adc->irq, adc);
++	irq_set_chained_handler(adc->irq, ingenic_adc_irq_demux);
++
++	return 0;
++}
++
++
++static int ingenic_adc_probe(struct platform_device *pdev)
++{
++	int ret;
++	struct ingenic_adc *adc;
++	struct device_node *np;
++	struct resource *mem_base;
++	const struct of_device_id *match;
++	unsigned char clkdiv, clkdiv_us;
++	unsigned short clkdiv_ms;
++
++	np = pdev->dev.of_node;
++
++	adc = kmalloc(sizeof(*adc), GFP_KERNEL);
++	if (!adc) {
++		dev_err(&pdev->dev, "Failed to allocate driver structre\n");
++		return -ENOMEM;
++	}
++
++	match = of_match_node(sadc_match, pdev->dev.of_node);
++	if (!match)
++		return -ENODEV;
++
++	adc->priv = match->data;
++
++	adc->irq = platform_get_irq(pdev, 0);
++	if (adc->irq < 0) {
++		ret = adc->irq;
++		dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
++		goto err_free;
++	}
++
++	mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!mem_base) {
++		ret = -ENOENT;
++		dev_err(&pdev->dev, "Failed to get platform mmio resource");
++		goto err_free;
++	}
++
++	adc->mem = request_mem_region(mem_base->start, INGENIC_REG_ADC_STATUS, pdev->name);
++	if (!adc->mem) {
++		ret = -EBUSY;
++		dev_err(&pdev->dev, "Failed to request mmio memory region\n");
++		goto err_free;
++	}
++
++	adc->base = ioremap(adc->mem->start, resource_size(adc->mem));
++	if (!adc->base) {
++		ret = -EBUSY;
++		dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
++		goto err_release_mem_region;
++	}
++
++	adc->clk = clk_get(&pdev->dev, "gate_sadc");
++	if (IS_ERR(adc->clk)) {
++		ret = PTR_ERR(adc->clk);
++		dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
++		goto err_iounmap;
++	}
++
++	ret = ingenic_alloc_aux_resources(adc);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to allocate aux resources: %d\n", ret);
++		goto err_free;
++	}
++
++	ret = ingenic_alloc_adc_cells(adc);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to allocate adc cells: %d\n", ret);
++		goto err_free;
++	}
++
++	ret = setup_adc_irq(adc, np);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to setup adc irq: %d\n", ret);
++		goto err_free;
++	}
++
++	spin_lock_init(&adc->lock);
++	atomic_set(&adc->clk_ref, 0);
++
++	platform_set_drvdata(pdev, adc);
++
++	clk_prepare_enable(adc->clk);
++
++	writew(0x8000, adc->base + INGENIC_REG_ADC_ENABLE);
++	writew(0xffff, adc->base + INGENIC_REG_ADC_CTRL);
++
++	clkdiv = CLKDIV - 1;
++	clkdiv_us = CLKDIV_US - 1;
++	clkdiv_ms = CLKDIV_MS - 1;
++
++	ingenic_adc_clk_div(adc, clkdiv, clkdiv_us, clkdiv_ms);
++
++	ret = mfd_add_devices(&pdev->dev, 0, adc->adc_cells, adc->priv->aux_channels, mem_base, adc->irq_base, NULL);
++	if (ret < 0) {
++		goto err_clk_put;
++	}
++
++	printk("ingenic SADC driver registeres over!\n");
++
++	return 0;
++
++err_clk_put:
++	clk_put(adc->clk);
++err_iounmap:
++	platform_set_drvdata(pdev, NULL);
++	iounmap(adc->base);
++err_release_mem_region:
++	release_mem_region(adc->mem->start, resource_size(adc->mem));
++err_free:
++	kfree(adc->aux_res_ptr);
++	kfree(adc->adc_cells);
++	kfree(adc);
++
++	return ret;
++}
++
++static int ingenic_adc_remove(struct platform_device *pdev)
++{
++	struct ingenic_adc *adc = platform_get_drvdata(pdev);
++
++	clk_disable_unprepare(adc->clk);
++	mfd_remove_devices(&pdev->dev);
++
++	irq_set_handler_data(adc->irq, NULL);
++	irq_set_chained_handler(adc->irq, NULL);
++
++	iounmap(adc->base);
++	release_mem_region(adc->mem->start, resource_size(adc->mem));
++
++	clk_put(adc->clk);
++
++	platform_set_drvdata(pdev, NULL);
++
++	kfree(adc->aux_res_ptr);
++	kfree(adc->adc_cells);
++	kfree(adc);
++
++	return 0;
++}
++
++
++static const struct ingenic_adc_priv x1600_adc_priv[] = {
++	{.aux_channels = 4,},
++};
++static const struct ingenic_adc_priv x2000_adc_priv[] = {
++	{.aux_channels = 6,},
++};
++static const struct ingenic_adc_priv x2500_adc_priv[] = {
++	{.aux_channels = 4,},
++};
++static const struct ingenic_adc_priv x2100_adc_priv[] = {
++	{.aux_channels = 6,},
++};
++static const struct ingenic_adc_priv m300_adc_priv[] = {
++	{.aux_channels = 6,},
++};
++
++static const struct of_device_id sadc_match[] = {
++	{ .compatible = "ingenic,x2000-sadc",.data = (void*)&x2000_adc_priv},
++	{ .compatible = "ingenic,x2500-sadc",.data = (void*)&x2500_adc_priv},
++	{ .compatible = "ingenic,x1600-sadc",.data = (void*)&x1600_adc_priv},
++	{ .compatible = "ingenic,x2100-sadc",.data = (void*)&x2100_adc_priv},
++	{ .compatible = "ingenic,m300-sadc",.data = (void*)&m300_adc_priv},
++	{},
++};
++MODULE_DEVICE_TABLE(of, sadc_match);
++
++struct platform_driver ingenic_adc_driver = {
++	.probe	= ingenic_adc_probe,
++	.remove	= ingenic_adc_remove,
++	.driver = {
++		.name	= "ingenic-adc",
++		.owner	= THIS_MODULE,
++		.of_match_table = sadc_match,
++	},
++};
++
++static int __init ingenic_adc_init(void)
++{
++	return platform_driver_register(&ingenic_adc_driver);
++}
++module_init(ingenic_adc_init);
++
++static void __exit ingenic_adc_exit(void)
++{
++	platform_driver_unregister(&ingenic_adc_driver);
++}
++module_exit(ingenic_adc_exit);
++
++MODULE_DESCRIPTION("ingenic SOC ADC driver");
++MODULE_AUTHOR("Guo Xu<xu.guo@ingenic.com>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:T15-adc");
+diff --git a/module_drivers/drivers/mfd/ricoh619-irq.c b/module_drivers/drivers/mfd/ricoh619-irq.c
+new file mode 100644
+index 000000000..f29a72b9b
+--- /dev/null
++++ b/module_drivers/drivers/mfd/ricoh619-irq.c
+@@ -0,0 +1,565 @@
++/*
++ * Interrupt driver for RICOH619 power management chip.
++ *
++ * Copyright (C) 2020 Ingenic Semiconductor Co., Ltd.
++ * Author: cljiang <conglong.jiang@ingenic.com>
++ *
++ * Based on code
++ *	drivers/mfd/ricoh619-irq.c
++ *	Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
++ *	Author: Laxman dewangan <ldewangan@nvidia.com>
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/i2c.h>
++#include <linux/mfd/ricoh619.h>
++#include <linux/regmap.h>
++#include <linux/irqdomain.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/of_platform.h>
++#include <linux/of_gpio.h>
++
++enum int_type {
++    SYS_INT  = 0x1,
++    DCDC_INT = 0x2,
++    RTC_INT  = 0x4,
++    ADC_INT  = 0x8,
++    GPIO_INT = 0x10,
++    CHG_INT = 0x40,
++};
++
++struct ricoh619_irq_st {
++	struct device *dev;
++	struct regmap *regmap;
++    int         gpio_base;
++    struct gpio_chip    gpio_chip;
++    int         irq_base;
++    /*  struct irq_chip     irq_chip; */
++    int         chip_irq;
++    struct mutex        irq_lock;
++    unsigned long       group_irq_en[MAX_MAIN_INTERRUPT];
++
++    /* For main interrupt bits in INTC */
++    u8          intc_inten_cache;
++    u8          intc_inten_reg;
++
++    /* For group interrupt bits and address */
++    u8          irq_en_cache[MAX_INTERRUPT_MASKS];
++    u8          irq_en_reg[MAX_INTERRUPT_MASKS];
++
++    /* For gpio edge */
++    u8          gpedge_cache[MAX_GPEDGE_REG];
++    u8          gpedge_reg[MAX_GPEDGE_REG];
++
++    int         bank_num;
++};
++
++struct ricoh619_irq_data {
++	u8	int_type;
++	u8	master_bit;
++	u8	int_en_bit;
++	u8	mask_reg_index;
++	int	grp_index;
++};
++
++#define RICOH619_IRQ(_int_type, _master_bit, _grp_index, _int_bit, _mask_ind) \
++	{						\
++		.int_type	= _int_type,		\
++		.master_bit	= _master_bit,		\
++		.grp_index	= _grp_index,		\
++		.int_en_bit	= _int_bit,		\
++		.mask_reg_index	= _mask_ind,		\
++	}
++static struct ricoh619_irq_st *ricoh619 = NULL;
++
++static const struct ricoh619_irq_data ricoh619_irqs[RICOH619_NR_IRQS] = {
++	[RICOH619_IRQ_POWER_ON]		= RICOH619_IRQ(SYS_INT,  0, 0, 0, 0),
++	[RICOH619_IRQ_EXTIN]		= RICOH619_IRQ(SYS_INT,  0, 1, 1, 0),
++	[RICOH619_IRQ_PRE_VINDT]	= RICOH619_IRQ(SYS_INT,  0, 2, 2, 0),
++	[RICOH619_IRQ_PREOT]		= RICOH619_IRQ(SYS_INT,  0, 3, 3, 0),
++	[RICOH619_IRQ_POWER_OFF]	= RICOH619_IRQ(SYS_INT,  0, 4, 4, 0),
++	[RICOH619_IRQ_NOE_OFF]		= RICOH619_IRQ(SYS_INT,  0, 5, 5, 0),
++	[RICOH619_IRQ_WD]		= RICOH619_IRQ(SYS_INT,  0, 6, 6, 0),
++
++	[RICOH619_IRQ_DC1LIM]		= RICOH619_IRQ(DCDC_INT, 1, 0, 0, 1),
++	[RICOH619_IRQ_DC2LIM]		= RICOH619_IRQ(DCDC_INT, 1, 1, 1, 1),
++	[RICOH619_IRQ_DC3LIM]		= RICOH619_IRQ(DCDC_INT, 1, 2, 2, 1),
++	[RICOH619_IRQ_DC4LIM]		= RICOH619_IRQ(DCDC_INT, 1, 3, 3, 1),
++	[RICOH619_IRQ_DC5LIM]		= RICOH619_IRQ(DCDC_INT, 1, 4, 4, 1),
++
++	[RICOH619_IRQ_CTC]		= RICOH619_IRQ(RTC_INT,  2, 0, 0, 2),
++	[RICOH619_IRQ_DALE]		= RICOH619_IRQ(RTC_INT,  2, 1, 6, 2),
++
++	[RICOH619_IRQ_ILIMLIR]		= RICOH619_IRQ(ADC_INT,  3, 0, 0, 3),
++	[RICOH619_IRQ_VBATLIR]		= RICOH619_IRQ(ADC_INT,  3, 1, 1, 3),
++	[RICOH619_IRQ_VADPLIR]		= RICOH619_IRQ(ADC_INT,  3, 2, 2, 3),
++	[RICOH619_IRQ_VUSBLIR]		= RICOH619_IRQ(ADC_INT,  3, 3, 3, 3),
++	[RICOH619_IRQ_VSYSLIR]		= RICOH619_IRQ(ADC_INT,  3, 4, 4, 3),
++	[RICOH619_IRQ_VTHMLIR]		= RICOH619_IRQ(ADC_INT,  3, 5, 5, 3),
++	[RICOH619_IRQ_AIN1LIR]		= RICOH619_IRQ(ADC_INT,  3, 6, 6, 3),
++	[RICOH619_IRQ_AIN0LIR]		= RICOH619_IRQ(ADC_INT,  3, 7, 7, 3),
++
++	[RICOH619_IRQ_ILIMHIR]		= RICOH619_IRQ(ADC_INT,  3, 8, 0, 4),
++	[RICOH619_IRQ_VBATHIR]		= RICOH619_IRQ(ADC_INT,  3, 9, 1, 4),
++	[RICOH619_IRQ_VADPHIR]		= RICOH619_IRQ(ADC_INT,  3, 10, 2, 4),
++	[RICOH619_IRQ_VUSBHIR]		= RICOH619_IRQ(ADC_INT,  3, 11, 3, 4),
++	[RICOH619_IRQ_VSYSHIR]		= RICOH619_IRQ(ADC_INT,  3, 12, 4, 4),
++	[RICOH619_IRQ_VTHMHIR]		= RICOH619_IRQ(ADC_INT,  3, 13, 5, 4),
++	[RICOH619_IRQ_AIN1HIR]		= RICOH619_IRQ(ADC_INT,  3, 14, 6, 4),
++	[RICOH619_IRQ_AIN0HIR]		= RICOH619_IRQ(ADC_INT,  3, 15, 7, 4),
++
++	[RICOH619_IRQ_ADC_ENDIR]	= RICOH619_IRQ(ADC_INT,  3, 16, 0, 5),
++
++	[RICOH619_IRQ_GPIO0]		= RICOH619_IRQ(GPIO_INT, 4, 0, 0, 6),
++	[RICOH619_IRQ_GPIO1]		= RICOH619_IRQ(GPIO_INT, 4, 1, 1, 6),
++	[RICOH619_IRQ_GPIO2]		= RICOH619_IRQ(GPIO_INT, 4, 2, 2, 6),
++	[RICOH619_IRQ_GPIO3]		= RICOH619_IRQ(GPIO_INT, 4, 3, 3, 6),
++	[RICOH619_IRQ_GPIO4]		= RICOH619_IRQ(GPIO_INT, 4, 4, 4, 6),
++
++	[RICOH619_IRQ_FVADPDETSINT]	= RICOH619_IRQ(CHG_INT, 6, 0, 0, 8),
++	[RICOH619_IRQ_FVUSBDETSINT]	= RICOH619_IRQ(CHG_INT, 6, 1, 1, 8),
++	[RICOH619_IRQ_FVADPLVSINT]	= RICOH619_IRQ(CHG_INT, 6, 2, 2, 8),
++	[RICOH619_IRQ_FVUSBLVSINT]	= RICOH619_IRQ(CHG_INT, 6, 3, 3, 8),
++	[RICOH619_IRQ_FWVADPSINT]	= RICOH619_IRQ(CHG_INT, 6, 4, 4, 8),
++	[RICOH619_IRQ_FWVUSBSINT]	= RICOH619_IRQ(CHG_INT, 6, 5, 5, 8),
++
++	[RICOH619_IRQ_FONCHGINT]	= RICOH619_IRQ(CHG_INT, 6, 6, 0, 9),
++	[RICOH619_IRQ_FCHGCMPINT]	= RICOH619_IRQ(CHG_INT, 6, 7, 1, 9),
++	[RICOH619_IRQ_FBATOPENINT]	= RICOH619_IRQ(CHG_INT, 6, 8, 2, 9),
++	[RICOH619_IRQ_FSLPMODEINT]	= RICOH619_IRQ(CHG_INT, 6, 9, 3, 9),
++	[RICOH619_IRQ_FBTEMPJTA1INT]	= RICOH619_IRQ(CHG_INT, 6, 10, 4, 9),
++	[RICOH619_IRQ_FBTEMPJTA2INT]	= RICOH619_IRQ(CHG_INT, 6, 11, 5, 9),
++	[RICOH619_IRQ_FBTEMPJTA3INT]	= RICOH619_IRQ(CHG_INT, 6, 12, 6, 9),
++	[RICOH619_IRQ_FBTEMPJTA4INT]	= RICOH619_IRQ(CHG_INT, 6, 13, 7, 9),
++
++	[RICOH619_IRQ_FCURTERMINT]	= RICOH619_IRQ(CHG_INT, 6, 14, 0, 10),
++	[RICOH619_IRQ_FVOLTERMINT]	= RICOH619_IRQ(CHG_INT, 6, 15, 1, 10),
++	[RICOH619_IRQ_FICRVSINT]	= RICOH619_IRQ(CHG_INT, 6, 16, 2, 10),
++	[RICOH619_IRQ_FPOOR_CHGCURINT]	= RICOH619_IRQ(CHG_INT, 6, 17, 3, 10),
++	[RICOH619_IRQ_FOSCFDETINT1]	= RICOH619_IRQ(CHG_INT, 6, 18, 4, 10),
++	[RICOH619_IRQ_FOSCFDETINT2]	= RICOH619_IRQ(CHG_INT, 6, 19, 5, 10),
++	[RICOH619_IRQ_FOSCFDETINT3]	= RICOH619_IRQ(CHG_INT, 6, 20, 6, 10),
++	[RICOH619_IRQ_FOSCMDETINT]	= RICOH619_IRQ(CHG_INT, 6, 21, 7, 10),
++
++	[RICOH619_IRQ_FDIEOFFINT]	= RICOH619_IRQ(CHG_INT, 6, 22, 0, 11),
++	[RICOH619_IRQ_FDIEERRINT]	= RICOH619_IRQ(CHG_INT, 6, 23, 1, 11),
++	[RICOH619_IRQ_FBTEMPERRINT]	= RICOH619_IRQ(CHG_INT, 6, 24, 2, 11),
++	[RICOH619_IRQ_FVBATOVINT]	= RICOH619_IRQ(CHG_INT, 6, 25, 3, 11),
++	[RICOH619_IRQ_FTTIMOVINT]	= RICOH619_IRQ(CHG_INT, 6, 26, 4, 11),
++	[RICOH619_IRQ_FRTIMOVINT]	= RICOH619_IRQ(CHG_INT, 6, 27, 5, 11),
++	[RICOH619_IRQ_FVADPOVSINT]	= RICOH619_IRQ(CHG_INT, 6, 28, 6, 11),
++	[RICOH619_IRQ_FVUSBOVSINT]	= RICOH619_IRQ(CHG_INT, 6, 29, 7, 11),
++
++	[RICOH619_IRQ_FGCDET]		= RICOH619_IRQ(CHG_INT, 6, 30, 0, 12),
++	[RICOH619_IRQ_FPCDET]		= RICOH619_IRQ(CHG_INT, 6, 31, 1, 12),
++	[RICOH619_IRQ_FWARN_ADP]	= RICOH619_IRQ(CHG_INT, 6, 32, 3, 12),
++};
++
++static int gpedge_add[] = {
++    RICOH619_GPEDGE1,
++    RICOH619_GPEDGE2,
++};
++
++static int irq_en_add[] = {
++    RICOH619_PWRIREN,
++    RICOH619_DCIREN,
++    RICOH619_RTCCNT1,
++    RICOH619_EN_ADCIR1,
++    RICOH619_EN_ADCIR2,
++    RICOH619_EN_ADCIR3,
++    RICOH619_EN_GPIR,
++    RICOH619_EN_GPIR,
++    RICOH619_CHGCTRL_IRFMASK,
++    RICOH619_CHGSTAT_IRFMASK1,
++    RICOH619_CHGSTAT_IRFMASK2,
++    RICOH619_CHGERR_IRFMASK,
++    RICOH619_CHGEXTIF_IRFMASK,
++};
++
++static int irq_mon_add[] = {
++    RICOH619_PWRIRQ,        /* RICOH619_INT_MON_SYS, */
++    RICOH619_DCIRQ,       /* RICOH619_INT_MON_DCDC, */
++    RICOH619_RTCCNT2,        /* RICOH619_INT_MON_RTC, */
++    RICOH619_IR_ADC1,
++    RICOH619_IR_ADC2,
++    RICOH619_IR_ADC3,
++    RICOH619_IR_GPR,
++    RICOH619_IR_GPF,
++    RICOH619_CHGCTRL_IRR,     /* RICOH619_INT_MON_CHGCTR, */
++    RICOH619_CHGSTAT_IRR1,    /* RICOH619_INT_MON_CHGSTS1, */
++    RICOH619_CHGSTAT_IRR2,   /* RICOH619_INT_MON_CHGSTS2, */
++    RICOH619_CHGERR_IRR,     /* RICOH619_INT_MON_CHGERR */
++    RICOH619_CHGEXTIF_IRR,    /* RICOH619_INT_MON_CHGEXTIF */
++};
++
++static int irq_clr_add[] = {
++    RICOH619_PWRIRQ,
++	RICOH619_DCIRQ,
++	RICOH619_RTCCNT2,
++	RICOH619_IR_ADC1,
++	RICOH619_IR_ADC2,
++	RICOH619_IR_ADC3,
++	RICOH619_IR_GPR,
++	RICOH619_IR_GPF,
++	RICOH619_CHGCTRL_IRR,
++	RICOH619_CHGSTAT_IRR1,
++	RICOH619_CHGSTAT_IRR2,
++	RICOH619_CHGERR_IRR,
++	RICOH619_CHGEXTIF_IRR,
++};
++static int main_int_type[] = {
++    SYS_INT,
++    DCDC_INT,
++    RTC_INT,
++    ADC_INT,
++    ADC_INT,
++    ADC_INT,
++    GPIO_INT,
++    GPIO_INT,
++    CHG_INT,
++    CHG_INT,
++    CHG_INT,
++    CHG_INT,
++    CHG_INT,
++};
++
++
++static irqreturn_t ricoh619_irq_thread_handler(int virq, void *data)
++{
++    struct ricoh619_irq_st *ricoh619 = data;
++    u8 int_sts[MAX_INTERRUPT_MASKS];
++    u8 master_int;
++    int i;
++    int ret;
++    unsigned int rtc_int_sts = 0;
++
++    /* printk("PMU: %s: irq=%d\n", __func__, irq); */
++    /* disable_irq_nosync(irq); */
++    /* Clear the status */
++    for (i = 0; i < MAX_INTERRUPT_MASKS; i++)
++        int_sts[i] = 0;
++
++    ret = ricoh61x_read(ricoh619->dev, RICOH619_INTMON,
++            &master_int);
++    //printk(KERN_DEBUG "PMU1: %s: master_int=0x%x\n", __func__, master_int);
++    if (ret < 0) {
++        dev_err(ricoh619->dev, "Error in reading reg 0x%02x "
++                "error: %d\n", RICOH619_INTMON, ret);
++        return IRQ_HANDLED;
++    }
++
++    for (i = 0; i < MAX_INTERRUPT_MASKS; ++i) {
++        /* Even if INTC_INTMON register = 1, INT signal might not
++         * output because INTC_INTMON register indicates only interrupt
++         * facter level.
++         * So remove the following procedure
++         */
++        if (!(master_int & main_int_type[i]))
++            continue;
++
++        ret = ricoh61x_read(ricoh619->dev,
++                irq_mon_add[i], &int_sts[i]);
++        //printk(KERN_DEBUG "PMU2: %s: int_sts[%d]=0x%x\n",
++        //               __func__, i, int_sts[i]);
++        if (ret < 0) {
++            dev_err(ricoh619->dev, "Error in reading reg 0x%02x "
++                    "error: %d\n", irq_mon_add[i], ret);
++            int_sts[i] = 0;
++            continue;
++        }
++        if (!int_sts[i])
++            continue;
++
++        if (main_int_type[i] & RTC_INT) {
++            /* Changes status bit position
++               from RTCCNT2 to RTCCNT1 */
++            rtc_int_sts = 0;
++            if (int_sts[i] & 0x1)
++                rtc_int_sts |= BIT(6);
++            if (int_sts[i] & 0x4)
++                rtc_int_sts |= BIT(0);
++        }
++
++        if(irq_clr_add[i] == RICOH619_RTCCNT2)
++        {
++            int_sts[i] &= ~0x85;
++            ret = ricoh61x_write(ricoh619->dev,
++                    irq_clr_add[i], int_sts[i]);
++            if (ret < 0) {
++                dev_err(ricoh619->dev, "Error in writing reg 0x%02x "
++                        "error: %d\n", irq_clr_add[i], ret);
++            }
++        }
++        else
++        {
++            ret = ricoh61x_write(ricoh619->dev,
++                    irq_clr_add[i], ~int_sts[i]);
++            if (ret < 0) {
++                dev_err(ricoh619->dev, "Error in writing reg 0x%02x "
++                        "error: %d\n", irq_clr_add[i], ret);
++            }
++        }
++
++        /* Mask Charger Interrupt */
++        if (main_int_type[i] & CHG_INT) {
++            if (int_sts[i])
++                ret = ricoh61x_write(ricoh619->dev,
++                        irq_en_add[i], 0xff);
++            if (ret < 0) {
++                dev_err(ricoh619->dev,
++                        "Error in write reg 0x%02x error: %d\n",
++                        irq_en_add[i], ret);
++            }
++        }
++        /* Mask ADC Interrupt */
++        if (main_int_type[i] & ADC_INT) {
++            if (int_sts[i])
++                ret = ricoh61x_write(ricoh619->dev,
++                        irq_en_add[i], 0);
++            if (ret < 0) {
++                dev_err(ricoh619->dev,
++                        "Error in write reg 0x%02x error: %d\n",
++                        irq_en_add[i], ret);
++            }
++        }
++
++        if (main_int_type[i] & RTC_INT)
++            int_sts[i] = rtc_int_sts;
++
++    }
++
++    /* Merge gpio interrupts  for rising and falling case*/
++    int_sts[6] |= int_sts[7];
++
++    /* Call interrupt handler if enabled */
++    for (i = 0; i < RICOH619_NR_IRQS; ++i) {
++        const struct ricoh619_irq_data *data = &ricoh619_irqs[i];
++        if ((int_sts[data->mask_reg_index] & (1 << data->int_en_bit)) &&
++                (ricoh619->group_irq_en[data->master_bit] &
++                 (1 << data->grp_index)))
++            handle_nested_irq(ricoh619->irq_base + i);
++    }
++
++    //printk(KERN_DEBUG "PMU: %s: out\n", __func__);
++    return IRQ_HANDLED;
++
++
++	return IRQ_HANDLED;
++}
++
++static void ricoh619_irq_lock(struct irq_data *irq_data)
++{
++	struct ricoh619_irq_st *ricoh619 = irq_data_get_irq_chip_data(irq_data);
++
++	mutex_lock(&ricoh619->irq_lock);
++}
++
++static void ricoh619_irq_unmask(struct irq_data *irq_data)
++{
++	struct ricoh619_irq_st *ricoh619 = irq_data_get_irq_chip_data(irq_data);
++	unsigned int __irq = irq_data->irq - ricoh619->irq_base;
++	const struct ricoh619_irq_data *data = &ricoh619_irqs[__irq];
++
++	ricoh619->group_irq_en[data->master_bit] |= (1 << data->grp_index);
++	if (ricoh619->group_irq_en[data->master_bit])
++		ricoh619->intc_inten_reg |= 1 << data->master_bit;
++
++	if (data->master_bit == 6)	/* if Charger */
++		ricoh619->irq_en_reg[data->mask_reg_index]
++						&= ~(1 << data->int_en_bit);
++	else
++		ricoh619->irq_en_reg[data->mask_reg_index]
++						|= 1 << data->int_en_bit;
++}
++
++static void ricoh619_irq_mask(struct irq_data *irq_data)
++{
++	struct ricoh619_irq_st *ricoh619 = irq_data_get_irq_chip_data(irq_data);
++	unsigned int __irq = irq_data->irq - ricoh619->irq_base;
++	const struct ricoh619_irq_data *data = &ricoh619_irqs[__irq];
++
++	ricoh619->group_irq_en[data->master_bit] &= ~(1 << data->grp_index);
++	if (!ricoh619->group_irq_en[data->master_bit])
++		ricoh619->intc_inten_reg &= ~(1 << data->master_bit);
++
++	if (data->master_bit == 6)	/* if Charger */
++		ricoh619->irq_en_reg[data->mask_reg_index]
++						|= 1 << data->int_en_bit;
++	else
++		ricoh619->irq_en_reg[data->mask_reg_index]
++						&= ~(1 << data->int_en_bit);
++}
++
++static void ricoh619_irq_sync_unlock(struct irq_data *irq_data)
++{
++	struct ricoh619_irq_st *ricoh619 = irq_data_get_irq_chip_data(irq_data);
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(ricoh619->gpedge_reg); i++) {
++		if (ricoh619->gpedge_reg[i] != ricoh619->gpedge_cache[i]) {
++			if (!WARN_ON(ricoh61x_write(ricoh619->dev,
++						    gpedge_add[i],
++						    ricoh619->gpedge_reg[i])))
++				ricoh619->gpedge_cache[i] =
++						ricoh619->gpedge_reg[i];
++		}
++	}
++
++	for (i = 0; i < ARRAY_SIZE(ricoh619->irq_en_reg); i++) {
++		if (ricoh619->irq_en_reg[i] != ricoh619->irq_en_cache[i]) {
++			if (!WARN_ON(ricoh61x_write(ricoh619->dev,
++						irq_en_add[i],
++						ricoh619->irq_en_reg[i])))
++				ricoh619->irq_en_cache[i] =
++						ricoh619->irq_en_reg[i];
++		}
++	}
++
++	if (ricoh619->intc_inten_reg != ricoh619->intc_inten_cache) {
++		if (!WARN_ON(ricoh61x_write(ricoh619->dev,
++				RICOH619_INTEN, ricoh619->intc_inten_reg)))
++			ricoh619->intc_inten_cache = ricoh619->intc_inten_reg;
++	}
++
++	mutex_unlock(&ricoh619->irq_lock);
++}
++
++static int ricoh619_irq_set_type(struct irq_data *irq_data, unsigned int type)
++{
++	struct ricoh619_irq_st *ricoh619 = irq_data_get_irq_chip_data(irq_data);
++	unsigned int __irq = irq_data->irq - ricoh619->irq_base;
++	const struct ricoh619_irq_data *data = &ricoh619_irqs[__irq];
++	int val = 0;
++	int gpedge_index;
++	int gpedge_bit_pos;
++
++	if (data->int_type & GPIO_INT) {
++		gpedge_index = data->int_en_bit / 4;
++		gpedge_bit_pos = data->int_en_bit % 4;
++
++		if (type & IRQ_TYPE_EDGE_FALLING)
++			val |= 0x2;
++
++		if (type & IRQ_TYPE_EDGE_RISING)
++			val |= 0x1;
++
++		ricoh619->gpedge_reg[gpedge_index] &= ~(3 << gpedge_bit_pos);
++		ricoh619->gpedge_reg[gpedge_index] |= (val << gpedge_bit_pos);
++		ricoh619_irq_unmask(irq_data);
++	}
++	return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int ricoh619_irq_set_wake(struct irq_data *irq_data, unsigned int on)
++{
++	struct ricoh619_irq_st *ricoh619 = irq_data_get_irq_chip_data(irq_data);
++	return irq_set_irq_wake(ricoh619->chip_irq, on);	/* i2c->irq */
++}
++#else
++#define ricoh619_irq_set_wake NULL
++#endif
++
++static struct irq_chip ricoh619_irq_chip = {
++	.name = "ricoh619",
++	.irq_mask = ricoh619_irq_mask,
++	.irq_unmask = ricoh619_irq_unmask,
++	.irq_bus_lock = ricoh619_irq_lock,
++	.irq_bus_sync_unlock = ricoh619_irq_sync_unlock,
++	.irq_set_type = ricoh619_irq_set_type,
++	.irq_set_wake = ricoh619_irq_set_wake,
++};
++
++
++int ricoh619_irq_init(struct i2c_client *i2c, struct regmap *regmap)
++{
++	int ret, i;
++    unsigned int flags;
++    unsigned int irq_gpio_num;
++    unsigned int irq_base = IRQ_RESERVED_BASE;
++    unsigned char reg_data = 0;
++
++
++    printk("%s: %d\n", __func__, __LINE__);
++	//i2c->irq = irq_of_parse_and_map(i2c->dev.of_node, 0);
++	irq_gpio_num = of_get_named_gpio_flags(i2c->dev.of_node, "ingenic,irq-gpio", 0, &flags);
++	if (!irq_gpio_num)
++		return 0;
++
++    i2c->irq = gpio_to_irq(irq_gpio_num);
++
++	ricoh619 = devm_kzalloc(&i2c->dev, sizeof(struct ricoh619_irq_st), GFP_KERNEL);
++	if (!ricoh619)
++		return -ENOMEM;
++
++	mutex_init(&ricoh619->irq_lock);
++	ricoh619->regmap = regmap;
++
++	regmap_write(ricoh619->regmap, RICOH619_INTEN, 0);
++	regmap_write(ricoh619->regmap, RICOH619_INTPOL, 0);
++
++
++	for (i = 0; i < MAX_INTERRUPT_MASKS; i++)  {
++		if (irq_clr_add[i] != RICOH619_RTCCNT2) {
++			ret = ricoh61x_write(&i2c->dev,
++						irq_clr_add[i], 0);
++			if (ret < 0)
++				dev_err(&i2c->dev, "Error in writing reg 0x%02x "
++					"error: %d\n", irq_clr_add[i], ret);
++		} else {
++			ret = ricoh61x_read(&i2c->dev,
++					RICOH619_RTCCNT2, &reg_data);
++			if (ret < 0)
++				dev_err(&i2c->dev, "Error in reading reg 0x%02x "
++					"error: %d\n", RICOH619_RTCCNT2, ret);
++			reg_data &= 0xf0;
++			ret = ricoh61x_write(&i2c->dev,
++					RICOH619_RTCCNT2, reg_data);
++			if (ret < 0)
++				dev_err(&i2c->dev, "Error in writing reg 0x%02x "
++					"error: %d\n", RICOH619_RTCCNT2, ret);
++		}
++	}
++
++
++
++	for (i = 0; i < RICOH619_NR_IRQS; i++) {
++		int __irq = i + irq_base;
++		irq_set_chip_data(__irq, ricoh619);
++		irq_set_chip_and_handler(__irq, &ricoh619_irq_chip,
++					 handle_simple_irq);
++		irq_set_nested_thread(__irq, 1);
++#ifdef CONFIG_ARM
++		set_irq_flags(__irq, IRQF_VALID);
++#endif
++	}
++
++	ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, ricoh619_irq_thread_handler, IRQ_TYPE_EDGE_FALLING|IRQF_ONESHOT, 
++            i2c->name, ricoh619);
++	if (ret) {
++		dev_err(&i2c->dev, "irq request failed: %d\n", ret);
++		return ret;
++	}
++
++    ricoh619->chip_irq = i2c->irq;
++    ricoh619->irq_base = irq_base;
++	ricoh619->dev = &i2c->dev;
++
++	return 0;
++}
++
++void ricoh619_irq_deinit(void)
++{
++	regmap_write(ricoh619->regmap, RICOH619_INTEN, 0);
++    disable_irq(ricoh619->chip_irq);
++}
+diff --git a/module_drivers/drivers/mfd/ricoh619.c b/module_drivers/drivers/mfd/ricoh619.c
+new file mode 100644
+index 000000000..28e1a8a2d
+--- /dev/null
++++ b/module_drivers/drivers/mfd/ricoh619.c
+@@ -0,0 +1,727 @@
++/*
++ * Core driver access RICOH619 power management chip.
++ *
++ * Copyright (C) 2020 Ingenic Semiconductor Co., Ltd.
++ * Author: cljiang <conglong.jiang@ingenic.com>
++ *
++ * Based on code
++ *	drivers/mfd/ricoh619.c
++ *	Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
++ *	Author: Laxman dewangan <ldewangan@nvidia.com>
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/err.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/mfd/core.h>
++#include <linux/mfd/ricoh619.h>
++#include <linux/regmap.h>
++#include <linux/regulator/consumer.h>
++#include <asm/delay.h>
++
++
++typedef struct{
++    int temp;    
++    unsigned int R;
++}R_T;
++
++static R_T sheet[] ={
++    {-40, 188500},
++    {-39, 178600},
++    {-38, 169200},
++    {-37, 160400},
++    {-36, 152100},
++    {-35, 144300},
++    {-34, 136900},
++    {-33, 130000},
++    {-32, 123400},
++    {-31, 117200},
++    {-30, 111300},
++    {-29, 105800},
++    {-28, 100600},
++    {-27, 95640},
++    {-26, 90970},
++    {-25, 86560},
++    {-24, 82380},
++    {-23, 78430},
++    {-22, 74690},
++    {-21, 71140},
++    {-20, 67790},
++    {-19, 64610},
++    {-18, 61600},
++    {-17, 58740},
++    {-16, 56030},
++    {-15, 53460},
++    {-14, 51030},
++    {-13, 48710},
++    {-12, 46520},
++    {-11, 44430},
++    {-10, 42450},
++    {-9, 40570},
++    {-8, 38780},
++    {-7, 37080},
++    {-6, 35460},
++    {-5, 33930},
++    {-4, 32460},
++    {-3, 31070},
++    {-2, 29750},
++    {-1, 28490},
++    {0, 27280},
++    {1, 26140},
++    {2, 25050},
++    {3, 24010},
++    {4, 23020},
++    {5, 22070},
++    {6, 21170},
++    {7, 20310},
++    {8, 19490},
++    {9, 18710},
++    {10, 17960},
++    {11, 17250},
++    {12, 16570},
++    {13, 15910},
++    {14, 15290},
++    {15, 14700},
++    {16, 14130},
++    {17, 13590},
++    {18, 13070},
++    {19, 12570},
++    {20, 12090},
++    {21, 11640},
++    {22, 11200},
++    {23, 10780},
++    {24, 10380},
++    {25, 10000},
++    {26, 9633},
++    {27, 9282},
++    {28, 8945},
++    {29, 8622},
++    {30, 8312},
++    {31, 8015},
++    {32, 7730},
++    {33, 7456},
++    {34, 7194},
++    {35, 6942},
++    {36, 6700},
++    {37, 6468},
++    {38, 6245},
++    {39, 6031},
++    {40, 5826},
++    {41, 5628},
++    {42, 5438},
++    {43, 5255},
++    {44, 5080},
++    {45, 4911},
++    {46, 4749},
++    {47, 4592},
++    {48, 4442},
++    {49, 4297},
++    {50, 4158},
++    {51, 4024},
++    {52, 3895},
++    {53, 3771},
++    {54, 3651},
++    {55, 3536},
++    {56, 3425},
++    {57, 3318},
++    {58, 3215},
++    {59, 3115},
++    {60, 3019},
++    {61, 2927},
++    {62, 2837},
++    {63, 2751},
++    {64, 2668},
++    {65, 2588},
++    {66, 2511},
++    {67, 2436},
++    {68, 2364},
++    {69, 2295},
++    {70, 2227},
++    {71, 2163},
++    {72, 2100},
++    {73, 2039},
++    {74, 1981},
++    {75, 1924},
++    {76, 1869},
++    {77, 1817},
++    {78, 1765},
++    {79, 1716},
++    {80, 1668},
++    {81, 1622},
++    {82, 1577},
++    {83, 1534},
++    {84, 1492},
++    {85, 1451},
++    {86, 1412},
++    {87, 1374},
++    {88, 1337},
++    {89, 1302},
++    {90, 1267},
++    {91, 1234},
++    {92, 1201},
++    {93, 1170},
++    {94, 1139},
++    {95, 1110},
++    {96, 1081},
++    {97, 1054},
++    {98, 1027},
++    {99, 1001},
++    {100, 975},
++    {101, 951},
++    {102, 927},
++    {103, 904},
++    {104, 881},
++    {105, 860},
++    {106, 838},
++    {107, 818},
++    {108, 798},
++    {109, 779},
++    {110, 760},
++};
++
++static unsigned int abs_subtract_val(int val_1, int val_2)
++{
++    if(val_1 > val_2)
++        return (val_1 - val_2);
++    else
++        return (val_2 - val_1);
++}
++
++static int temp_foreach_sheet(unsigned int R)
++{
++    int index = 0;
++    int i = 0;
++    int num = sizeof(sheet) / sizeof(R_T);
++    unsigned int abs = abs_subtract_val(R , sheet[0].R);
++    int tmp;
++    for(i = 1;i < num;i++){
++        tmp = abs_subtract_val(R , sheet[i].R);
++        if(tmp < abs){
++            index = i; 
++            abs = tmp;
++            if(tmp < 10)
++                break;
++        }
++    }
++    return (int)sheet[index].temp;
++}
++
++
++static struct i2c_client *ricoh619_i2c = NULL;
++static struct mutex ricoh61x_io_lock;
++
++static const struct mfd_cell ricoh619_cells[] = {
++	{ .name = "ricoh619-regulator" },
++    { .name = "ricoh619-battery"},
++	/*{ .name = "ricoh619-wdt" },
++	  { .name = "ricoh619-pinctrl" },
++	  { .name = "ricoh619-pm" }, */
++};
++
++static bool ricoh619_reg_hole(unsigned int reg)
++{
++#define RICOH619_REG_SINGLE_HOLE_NUM 16
++	unsigned char single_hole[RICOH619_REG_SINGLE_HOLE_NUM] = {
++		0x4, 0x8, 0x2b, 0x43, 0x49, 0x4b, 0x62, 0x63, 0x67, 0x8b,
++            0x8f, 0x99, 0x9a, 0x9b, 0x9f, 0xb2, };
++	int i;
++
++	for (i = 0; i < RICOH619_REG_SINGLE_HOLE_NUM; i++)
++		if ((unsigned char)reg == single_hole[i])
++			return true;
++	if (reg > RICOH619_MAX_REG)
++		return true;
++#undef RICOH619_REG_SINGLE_HOLE_NUM
++	return false;
++}
++
++static bool ricoh619_opable_reg(struct device *dev, unsigned int reg)
++{
++	return !ricoh619_reg_hole(reg);
++}
++
++static bool ricoh619_volatile_reg(struct device *dev, unsigned int reg)
++{
++	switch (reg) {
++	case RICOH619_WATCHDOGCNT:
++	case RICOH619_DCIRQ:
++	case RICOH619_IR_GPR:
++	case RICOH619_IR_GPF:
++	case RICOH619_MON_IOIN:
++	case RICOH619_INTMON:
++		return true;
++	default:
++		return false;
++	}
++}
++
++static struct reg_default ricoh619_reg_default[RICOH619_REG_NUM];
++static const struct regmap_config ricoh619_regmap_config = {
++	.reg_bits	= 8,
++	.val_bits	= 8,
++	.volatile_reg	= ricoh619_volatile_reg,
++	.writeable_reg  = ricoh619_opable_reg,
++	.readable_reg	= ricoh619_opable_reg,
++	.max_register	= RICOH619_MAX_REG,
++	.reg_defaults	= ricoh619_reg_default,
++	.num_reg_defaults = ARRAY_SIZE(ricoh619_reg_default),
++	.cache_type	= REGCACHE_RBTREE,
++};
++static inline int set_bank_ricoh61x(struct device *dev, int bank)
++{
++    int ret = 0;
++
++    /*if (bank != (bank & 1))*/
++        /*return -EINVAL;*/
++    /*if (bank == ricoh61x->bank_num)*/
++        /*return 0;*/
++    /*ret = __ricoh61x_write(to_i2c_client(dev), RICOH61x_REG_BANKSEL, bank);*/
++    /*if (!ret)*/
++        /*ricoh61x->bank_num = bank;*/
++    return ret;
++}
++
++static int __ricoh619_reg_read(struct i2c_client *i2c, u8 reg)
++{
++	return i2c_smbus_read_byte_data(i2c, reg);
++}
++
++static inline int __ricoh61x_bulk_reads(struct i2c_client *client, u8 reg,
++        int len, uint8_t *val)
++{
++    int ret;
++    int i;
++
++    ret = i2c_smbus_read_i2c_block_data(client, reg, len, val);
++    if (ret < 0) {
++        dev_err(&client->dev, "failed reading from 0x%02x\n", reg);
++        return ret;
++    }
++    for (i = 0; i < len; ++i) {
++        dev_dbg(&client->dev, "ricoh61x: reg read  reg=%x, val=%x\n",
++                reg + i, *(val + i));
++    }
++    return 0;
++}
++
++int ricoh61x_read(struct device* dev, u8 reg, uint8_t* val)
++{
++    int ret;
++    mutex_lock(&ricoh61x_io_lock);
++    if(ricoh619_i2c){
++        *val =  __ricoh619_reg_read(ricoh619_i2c, reg);
++        ret = 0;
++    }else{
++        ret = -1;
++    }
++    mutex_unlock(&ricoh61x_io_lock);
++    return ret;
++}
++EXPORT_SYMBOL(ricoh61x_read);
++
++int ricoh61x_bulk_reads(struct device *dev, u8 reg, u8 len, uint8_t *val)
++{
++    int ret = 0;
++    mutex_lock(&ricoh61x_io_lock);
++    ret = set_bank_ricoh61x(dev, 0);
++    if (!ret)
++        ret = __ricoh61x_bulk_reads(ricoh619_i2c, reg, len, val);
++    mutex_unlock(&ricoh61x_io_lock);
++    return ret;
++}
++EXPORT_SYMBOL_GPL(ricoh61x_bulk_reads);
++int ricoh61x_bulk_reads_bank1(struct device *dev, u8 reg, u8 len, uint8_t *val)
++{
++    int ret = 0;
++
++    mutex_lock(&ricoh61x_io_lock);
++    ret = set_bank_ricoh61x(dev, 1);
++    if (!ret)
++        ret = __ricoh61x_bulk_reads(ricoh619_i2c, reg, len, val);
++    mutex_unlock(&ricoh61x_io_lock);
++
++    return ret;
++}
++EXPORT_SYMBOL_GPL(ricoh61x_bulk_reads_bank1);
++static inline int __ricoh61x_bulk_writes(struct i2c_client *client, u8 reg,
++        int len, uint8_t *val)
++{
++    int ret;
++    int i;
++
++    for (i = 0; i < len; ++i) {
++        dev_dbg(&client->dev, "ricoh61x: reg write  reg=%x, val=%x\n",
++                reg + i, *(val + i));
++    }
++    ret = i2c_smbus_write_i2c_block_data(client, reg, len, val);
++    if (ret < 0) {
++        dev_err(&client->dev, "failed writings to 0x%02x\n", reg);
++        return ret;
++    }
++    return 0;
++}
++
++int ricoh61x_bulk_writes_bank1(struct device *dev, u8 reg, u8 len, uint8_t *val)
++{
++    int ret = 0;
++
++    mutex_lock(&ricoh61x_io_lock);
++    ret = set_bank_ricoh61x(dev, 1);
++    if (!ret)
++        ret = __ricoh61x_bulk_writes(to_i2c_client(dev), reg, len, val);
++    mutex_unlock(&ricoh61x_io_lock);
++
++    return ret;
++}
++EXPORT_SYMBOL_GPL(ricoh61x_bulk_writes_bank1);
++static int __ricoh619_reg_write(struct i2c_client *i2c, u8 reg, u8 val)
++{
++	return i2c_smbus_write_byte_data(i2c, reg, val);
++}
++
++int ricoh61x_write(struct device* dev, u8 reg, uint8_t val)
++{
++    int ret;
++    mutex_lock(&ricoh61x_io_lock);
++    if(ricoh619_i2c)
++        ret =  __ricoh619_reg_write(ricoh619_i2c, reg, val);
++    else 
++        ret = -1;
++    mutex_unlock(&ricoh61x_io_lock);
++    return ret;
++}
++EXPORT_SYMBOL(ricoh61x_write);
++static inline int __ricoh61x_read(struct i2c_client *client,
++        u8 reg, uint8_t *val)
++{
++    int ret;
++
++    ret = i2c_smbus_read_byte_data(client, reg);
++    if (ret < 0) {
++        dev_err(&client->dev, "failed reading at 0x%02x\n", reg);
++        return ret;
++    }
++
++    *val = (uint8_t)ret;
++    dev_dbg(&client->dev, "ricoh61x: reg read  reg=%x, val=%x\n",
++            reg, *val);
++    return 0;
++}
++
++int ricoh61x_read_bank1(struct device *dev, u8 reg, uint8_t *val)
++{
++    int ret = 0;
++
++    mutex_lock(&ricoh61x_io_lock);
++    ret = set_bank_ricoh61x(dev, 1);
++    if (!ret)
++        ret =  __ricoh61x_read(to_i2c_client(dev), reg, val);
++    mutex_unlock(&ricoh61x_io_lock);
++
++    return ret;
++}
++EXPORT_SYMBOL_GPL(ricoh61x_read_bank1);
++int ricoh61x_bulk_writes(struct device *dev, u8 reg, u8 len, uint8_t *val)
++{
++    int ret = 0;
++
++    mutex_lock(&ricoh61x_io_lock);
++    ret = set_bank_ricoh61x(dev, 0);
++    if (!ret)
++        ret = __ricoh61x_bulk_writes(to_i2c_client(dev), reg, len, val);
++    mutex_unlock(&ricoh61x_io_lock);
++
++    return ret;
++}
++EXPORT_SYMBOL_GPL(ricoh61x_bulk_writes);
++
++int ricoh61x_set_bits(struct device *dev, u8 reg, uint8_t bit_mask)
++{
++    uint8_t reg_val;
++    int ret = 0;
++
++    mutex_lock(&ricoh61x_io_lock);
++    if(ricoh619_i2c){
++        reg_val = __ricoh619_reg_read(ricoh619_i2c, reg);
++
++        if ((reg_val & bit_mask) != bit_mask) {
++            reg_val |= bit_mask;
++            ret = __ricoh619_reg_write(ricoh619_i2c, reg,
++                    reg_val);
++        }
++    }
++    mutex_unlock(&ricoh61x_io_lock);
++    return ret;
++}
++EXPORT_SYMBOL_GPL(ricoh61x_set_bits);
++
++int ricoh61x_clr_bits(struct device *dev, u8 reg, uint8_t bit_mask)
++{
++    uint8_t reg_val;
++    int ret = 0;
++
++    mutex_lock(&ricoh61x_io_lock);
++    if(ricoh619_i2c){
++        reg_val = __ricoh619_reg_read(ricoh619_i2c, reg);
++        if (reg_val & bit_mask) {
++            reg_val &= ~bit_mask;
++            ret = __ricoh619_reg_write(ricoh619_i2c, reg,
++                    reg_val);
++        }
++    }
++    mutex_unlock(&ricoh61x_io_lock);
++    return ret;
++}
++EXPORT_SYMBOL_GPL(ricoh61x_clr_bits);
++
++int ricoh61x_write_bank1(struct device *dev, u8 reg, uint8_t val)
++{
++    int ret = 0;
++
++    mutex_lock(&ricoh61x_io_lock);
++    ret =  __ricoh619_reg_write(ricoh619_i2c, reg, val);
++    mutex_unlock(&ricoh61x_io_lock);
++
++    return ret;
++}
++EXPORT_SYMBOL_GPL(ricoh61x_write_bank1);
++
++
++static void ricoh619_reg_default_init(struct i2c_client *i2c)
++{
++	unsigned int reg, def;
++	int i;
++
++	for (i = 0, reg = 0; i < RICOH619_REG_NUM &&
++			reg <= RICOH619_MAX_REG; reg++) {
++		if (ricoh619_reg_hole(reg) ||
++				ricoh619_volatile_reg(NULL, reg))
++			continue;
++		ricoh619_reg_default[i].reg = reg;
++		def = __ricoh619_reg_read(i2c, (u8)reg);
++		if (def < 0) {
++			dev_warn(&i2c->dev, "register %x read failed: %d\n", reg, def);
++			ricoh619_reg_default[i++].def = 0;
++		} else{
++			ricoh619_reg_default[i++].def = def;
++//            printk("ricoh619: reg: 0x%x , val: 0x%x\n", ricoh619_reg_default[i-1].reg, ricoh619_reg_default[i-1].def);
++        }
++	}
++}
++
++static int battery_ntc_R_val(int thermbat_val)
++{
++    thermbat_val *= 10;
++#define R493 10000 
++#define VCHGREGA 2500
++    if(thermbat_val > 0)
++        return thermbat_val * R493 / (VCHGREGA - thermbat_val);
++    else
++        return 0;
++}
++
++static void config_xxzA926_info(struct i2c_client *i2c)
++{
++    unsigned int reg_val;
++    struct regulator *reg = devm_regulator_get(&i2c->dev, "ldo3_2v8");
++    regulator_set_voltage(reg, 2800000, 2800000);
++    regulator_enable(reg);
++
++
++    reg = devm_regulator_get(&i2c->dev, "DC1_0v9");
++    regulator_set_voltage(reg, 900000, 900000);
++    regulator_enable(reg);
++
++    /*regulator_enable(reg);*/
++    reg = devm_regulator_get(&i2c->dev, "DC5_1v2");
++    regulator_set_voltage(reg, 1200000, 1200000);
++    regulator_enable(reg);
++    printk("cljiang======================RICOH619_DC5CTL = 0x%x\n", __ricoh619_reg_read(i2c, RICOH619_DC5CTL));
++    printk("cljiang======================RICOH619_DC5DAC = 0x%x\n", __ricoh619_reg_read(i2c, RICOH619_DC5DAC));
++
++    reg = devm_regulator_get(&i2c->dev, "ldortc2_0v9");
++    regulator_set_voltage(reg, 900000, 900000);
++    regulator_enable(reg);
++
++    /*Full-charging Voltage*/
++    reg_val = __ricoh619_reg_read(i2c, RICOH619_BATSET2);
++    printk("cljiang======================RICOH619_BATSET2 = 0x%x\n", reg_val);
++    reg_val &= 0x84;
++    reg_val |= 0x44; /*full-Charging volt 4.35v, Re-Charging volt 4.1v*/
++    __ricoh619_reg_write(i2c, RICOH619_BATSET2, reg_val);
++    printk("cljiang======================set RICOH619_BATSET2 = 0x%x\n", __ricoh619_reg_read(i2c, RICOH619_BATSET2));
++
++    /*Over Voltage*/
++    reg_val = __ricoh619_reg_read(i2c, RICOH619_BATSET1);
++    reg_val &= 0xEF;
++    reg_val |= 0x10;
++    __ricoh619_reg_write(i2c, RICOH619_BATSET1, reg_val);
++    printk("cljiang======================set RICOH619_BATSET1 = 0x%x\n", __ricoh619_reg_read(i2c, RICOH619_BATSET1));
++
++
++    /*Charging current*/
++        /*limited ADP*/
++    __ricoh619_reg_write(i2c, RICOH619_REGISET1, 0x13); /* 2000ma*/ 
++    printk("cljiang======================RICOH619_REGISET1 = 0x%x\n", __ricoh619_reg_read(i2c, RICOH619_REGISET1));
++
++        /*limited USB */
++    printk("cljiang======================RICOH619_REGISET1 = 0x%x\n", __ricoh619_reg_read(i2c, RICOH619_REGISET1));
++    reg_val = __ricoh619_reg_read(i2c, RICOH619_REGISET2);
++    reg_val &= 0xE0;
++    reg_val |= 0x0E;/*1500ma*/
++    __ricoh619_reg_write(i2c, RICOH619_REGISET2, reg_val);
++    printk("cljiang======================RICOH619_REGISET2 = 0x%x\n", __ricoh619_reg_read(i2c, RICOH619_REGISET2));
++
++        /*Charge Current Setting*/
++    reg_val = __ricoh619_reg_read(i2c, RICOH619_CHGISET); 
++    printk("cljiang======================RICOH619_CHGISET = 0x%x\n", reg_val);
++    reg_val &= 0xE0;
++    reg_val |= 0x0B;/*1200ma*/
++    __ricoh619_reg_write(i2c, RICOH619_CHGISET, reg_val);
++    printk("cljiang======================RICOH619_CHGISET = 0x%x\n", __ricoh619_reg_read(i2c, RICOH619_CHGISET));
++
++
++    /*power off press timer*/
++    reg_val = __ricoh619_reg_read(i2c, RICOH619_PWRONTIMSET); 
++    reg_val &= 0x8F;
++    reg_val |= 0x50; /*8 sec*/
++    __ricoh619_reg_write(i2c, RICOH619_PWRONTIMSET, reg_val);
++
++
++    /*battery temperature measure*/
++        /*enable VTHMSEL bit*/
++    reg_val = __ricoh619_reg_read(i2c, RICOH619_ADCCNT1); 
++    reg_val &= 0xDF;
++    reg_val |= 0x20;
++    __ricoh619_reg_write(i2c, RICOH619_ADCCNT1, reg_val);
++
++        /*set ADRQ auto-mode*/
++    reg_val = __ricoh619_reg_read(i2c, RICOH619_ADCCNT3); 
++    reg_val &= 0xCF;
++    reg_val |= 0x20; /*auto-mode*/
++    __ricoh619_reg_write(i2c, RICOH619_ADCCNT3, reg_val);
++
++     
++    
++    udelay(100000);
++        /*read voltage*/
++    printk("cljiang======================VTHMDATAH: %d, VTHMDATAL: %d\n", __ricoh619_reg_read(i2c, RICOH619_VTHMDATAH), 
++                                                __ricoh619_reg_read(i2c, RICOH619_VTHMDATAL));
++    printk("cljiang======================Resistance = %d\n", battery_ntc_R_val(__ricoh619_reg_read(i2c, RICOH619_VTHMDATAH)));
++    printk("cljiang======================temperature = %d\n", temp_foreach_sheet(188600));
++
++    /*charger insertion logic*/
++    reg_val = __ricoh619_reg_read(i2c, RICOH619_PONHIS);
++    printk("cljiang======================RICOH619_PONHIS = 0x%x\n", reg_val);
++#if 0
++    if(reg_val & 0x4){
++        /*power off*/
++        __ricoh619_reg_write(i2c, RICOH619_SLPCNT, 0x1);
++    }
++#endif
++
++}
++static int ricoh619_i2c_probe(struct i2c_client *i2c,
++		const struct i2c_device_id *id)
++{
++	struct regmap *regmap = NULL;
++	int ret;
++printk("jimgao test ricoh619_i2c_probe=======IIIIIIIIIIIIIII=====\n");
++    ricoh619_i2c = i2c;
++    mutex_init(&ricoh61x_io_lock);
++
++	ricoh619_reg_default_init(i2c);
++
++	regmap = devm_regmap_init_i2c(i2c, &ricoh619_regmap_config);
++	if (IS_ERR(regmap)) {
++		ret = PTR_ERR(regmap);
++		dev_err(&i2c->dev, "regmap init failed: %d\n", ret);
++		return ret;
++	}
++	i2c_set_clientdata(i2c, regmap);
++
++	ret = ricoh619_irq_init(i2c, regmap);
++	if (ret)
++		return ret;
++
++
++	ret = mfd_add_devices(&i2c->dev, -1, ricoh619_cells,
++			ARRAY_SIZE(ricoh619_cells), NULL, 0, NULL);
++	if (ret) {
++		dev_err(&i2c->dev, "failed to add sub-devices: %d\n", ret);
++		goto out_irq_domain_remove;
++	}
++
++	dev_info(&i2c->dev, "%s success\n", __func__);
++
++    config_xxzA926_info(i2c);
++
++
++	return 0;
++
++out_irq_domain_remove:
++	ricoh619_irq_deinit();
++	return ret;
++}
++
++static int ricoh619_i2c_remove(struct i2c_client *i2c)
++{
++	mfd_remove_devices(&i2c->dev);
++	return 0;
++}
++
++static const struct of_device_id ricoh619_of_match[] = {
++	{ .compatible = "ricoh,rn5t619" },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, ricoh619_of_match);
++
++static const struct i2c_device_id rc5t619_i2c_id[] = {
++	{.name = "rc5t619", .driver_data = 0},
++	{}
++};
++
++
++static struct i2c_driver ricoh619_i2c_driver = {
++	.driver = {
++		.name = "ricoh619",
++		.of_match_table = of_match_ptr(ricoh619_of_match),
++	},
++	.probe = ricoh619_i2c_probe,
++	.remove = ricoh619_i2c_remove,
++	.id_table = rc5t619_i2c_id,
++};
++
++static int __init ricoh619_i2c_init(void)
++{
++	int ret = -ENODEV;
++
++	ret = i2c_add_driver(&ricoh619_i2c_driver);
++	if (ret != 0)
++		pr_err("Failed to register I2C driver: %d\n", ret);
++	return ret;
++}
++subsys_initcall(ricoh619_i2c_init);
++
++static void __exit ricoh619_i2c_exit(void)
++{
++	i2c_del_driver(&ricoh619_i2c_driver);
++}
++
++module_exit(ricoh619_i2c_exit);
++
++MODULE_DESCRIPTION("Ricoh RICOH619 MFD driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/module_drivers/drivers/misc/Kconfig b/module_drivers/drivers/misc/Kconfig
+new file mode 100644
+index 000000000..9f3238273
+--- /dev/null
++++ b/module_drivers/drivers/misc/Kconfig
+@@ -0,0 +1,41 @@
++config INGENIC_RSA
++        bool "[RSA] JZ RSA Driver"
++        depends on SOC_X2000 || SOC_X2100 || SOC_M300 || SOC_X2500
++        help
++                this driver is used to Encrypt/Decrypt by RSA.
++        default n
++
++config LINUX_PMEM
++        bool "Linux pmem allocator"
++        default n
++
++config PMEM_RESERVE_SIZE
++        string "reserve size"
++        depends on LINUX_PMEM
++        default 0M
++        help
++                set this like 16M, 4096K, 100000[B], 0x5000(B).
++
++config INGENIC_EFUSE_V2
++          bool "[Efuse] Ingenic Efuse v2 Driver"
++          depends on SOC_X1600
++          default n
++
++config INGENIC_EFUSE_V2_WRITABLE
++        bool "[Efuse] Ingenic Efuse V2 Writable"
++	depends on INGENIC_EFUSE_V2
++        default n
++
++
++config INGENIC_EFUSE_X2000
++          bool "[Efuse] Ingenic Efuse X2000 Driver"
++	  	  depends on SOC_X2000 || SOC_X2100 || SOC_M300
++          default n
++
++config BCM_4345C5_RFKILL
++	tristate "Bluetooth power control driver for BCM-4345C5 module"
++	depends on RFKILL && (MMC_SDHCI_INGENIC || INGENIC_MMC_MMC0 || INGENIC_MMC_MMC1)
++	default n
++	help
++	Creates an rfkill entry in sysfs for power control of Bluetooth
++	bcm-xxxx chips.
+diff --git a/module_drivers/drivers/misc/Makefile b/module_drivers/drivers/misc/Makefile
+new file mode 100644
+index 000000000..0b4f89c27
+--- /dev/null
++++ b/module_drivers/drivers/misc/Makefile
+@@ -0,0 +1,6 @@
++obj-$(CONFIG_LINUX_PMEM)        += linux_pmem.o
++obj-$(CONFIG_INGENIC_RSA)       += ingenic_rsa.o
++obj-$(CONFIG_INGENIC_EFUSE_X2000)       += ingenic_efuse_x2000.o
++obj-$(CONFIG_INGENIC_EFUSE_V2)  += ingenic_efuse_v2.o
++obj-$(CONFIG_RMEM)      += rmem.o
++obj-$(CONFIG_BCM_4345C5_RFKILL) += bt_power_bluesleep.o
+diff --git a/module_drivers/drivers/misc/bt_power_bluesleep.c b/module_drivers/drivers/misc/bt_power_bluesleep.c
+new file mode 100644
+index 000000000..eee7a4c54
+--- /dev/null
++++ b/module_drivers/drivers/misc/bt_power_bluesleep.c
+@@ -0,0 +1,311 @@
++/*
++ * Description:
++ * Bluetooth power driver with rfkill interface ,work in with bluesleep.c , version of running consume.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/kernel.h>
++#include <linux/spinlock.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/input.h>
++#include <linux/rfkill.h>
++#include <linux/gpio.h>
++#include <linux/of_gpio.h>
++#include <asm/atomic.h>
++/*#include <linux/wakelock.h>*/
++/*#include <linux/bt-rfkill.h>*/
++#include <linux/delay.h>
++#include <linux/regulator/consumer.h>
++
++#define DEV_NAME		"bt_power"
++
++struct bt_rfkill_platform_data {
++	struct rfkill *rfkill;  /* for driver only */
++	void (*restore_pin_status)(int);
++	void (*set_pin_status)(int);
++};
++
++static struct bt_rfkill_platform_data pdata;
++#if 1
++#define	DBG_MSG(fmt, ...)	printk(fmt, ##__VA_ARGS__)
++#else
++#define DBG_MSG(fmt, ...)
++#endif
++
++int bt_power_state = 0;
++static int bt_power_control(int enable);
++static int bt_rst_n ;
++static int bt_reg_on;
++static int bt_wake;
++unsigned bt_wake_irq;
++static DEFINE_MUTEX(bt_power_lock);
++#if defined CONFIG_KP_AXP
++static struct regulator *bt_regulator = NULL;
++#endif
++
++extern void rtc32k_enable(void);
++extern void rtc32k_disable(void);
++
++/* For compile only, remove later */
++#define RFKILL_STATE_SOFT_BLOCKED	0
++#define RFKILL_STATE_UNBLOCKED		1
++
++static void bt_enable_power(void)
++{
++	gpio_set_value(bt_reg_on, 1);
++}
++
++static void bt_disable_power(void)
++{
++	gpio_set_value(bt_reg_on, 0);
++}
++
++static int bt_power_control(int enable)
++{
++	if (enable == bt_power_state)// == 0
++		return 0;
++
++#if defined CONFIG_KP_AXP
++	if(bt_regulator == NULL) {
++		bt_regulator = regulator_get(NULL, "wlreg_on");
++		if (bt_regulator == NULL) {
++			printk(("%s regulator is null\n", __FUNCTION__));
++			return -1;
++		}
++	}
++#endif
++
++	switch (enable)	{
++	case RFKILL_STATE_SOFT_BLOCKED://0
++		rtc32k_disable();
++		bt_disable_power();
++		mdelay(1000);
++		if (pdata.set_pin_status != NULL){
++			(*pdata.set_pin_status)(enable);
++			printk("set_pin_status is defined\n");
++		}else{
++			printk("set_pin_status is not defined\n");
++		}
++#if defined CONFIG_KP_AXP
++		if(regulator_disable(bt_regulator) < 0)
++			return -1;
++#endif
++		break;
++	case RFKILL_STATE_UNBLOCKED://1
++#if defined CONFIG_KP_AXP
++		if(regulator_enable(bt_regulator) < 0)
++			return -1;
++#endif
++		if (pdata.restore_pin_status != NULL){
++			(*pdata.restore_pin_status)(enable);
++		}else{
++		rtc32k_enable();
++			printk("restore_pin_status is not defined\n");
++		}
++		rtc32k_enable();
++		if (bt_rst_n > 0){
++			gpio_direction_output(bt_rst_n,0);
++		}
++		bt_enable_power();
++		mdelay(300);
++		if(bt_rst_n > 0){
++			gpio_set_value(bt_rst_n,1);
++		}
++		break;
++	default:
++		break;
++	}
++
++	bt_power_state = enable;
++
++	return 0;
++}
++
++static bool first_called = true;
++
++static int bt_rfkill_set_block(void *data, bool blocked)
++{
++	int ret;
++
++	if (!first_called) {
++		mutex_lock(&bt_power_lock);
++		ret = bt_power_control(blocked ? 0 : 1);
++		mutex_unlock(&bt_power_lock);
++	} else {
++		first_called = false;
++		return 0;
++	}
++
++	return ret;
++}
++
++static const struct rfkill_ops bt_rfkill_ops = {
++	.set_block = bt_rfkill_set_block,
++};
++
++static int bt_power_rfkill_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	enum of_gpio_flags flags;
++	int ret = -ENOMEM;
++
++	bt_rst_n = of_get_named_gpio_flags(np, "ingenic,rst-n-gpio", 0, &flags);
++	if(!gpio_is_valid(bt_rst_n)) {
++		bt_rst_n = -1;
++	}
++	bt_reg_on = of_get_named_gpio_flags(np, "ingenic,reg-on-gpio", 0, &flags);
++	if(!gpio_is_valid(bt_reg_on)) {
++		bt_reg_on = -1;
++	}
++	bt_wake = of_get_named_gpio_flags(np, "ingenic,wake-gpio", 0, &flags);
++	if(!gpio_is_valid(bt_wake)) {
++		bt_wake = -1;
++	}
++
++	pdata.restore_pin_status = NULL;
++	pdata.set_pin_status = NULL;
++	pdata.rfkill = rfkill_alloc("bluetooth", &pdev->dev, RFKILL_TYPE_BLUETOOTH,
++                            &bt_rfkill_ops, NULL);
++
++	if (!pdata.rfkill) {
++		goto exit;
++	}
++
++	ret = rfkill_register(pdata.rfkill);
++	if (ret) {
++		rfkill_destroy(pdata.rfkill);
++		return ret;
++	} else {
++		platform_set_drvdata(pdev, pdata.rfkill);
++	}
++exit:
++	return ret;
++}
++
++static void bt_power_rfkill_remove(struct platform_device *pdev)
++{
++	pdata.rfkill = platform_get_drvdata(pdev);
++	if (pdata.rfkill)
++		rfkill_unregister(pdata.rfkill);
++
++	platform_set_drvdata(pdev, NULL);
++}
++
++static irqreturn_t bt_wake_host_cb(int i, void *data)
++{
++	return IRQ_HANDLED;
++}
++
++static int bluesleep_suspend(struct platform_device *pdev, pm_message_t state)
++{
++
++	if(bt_wake >= 0)
++		enable_irq_wake(bt_wake_irq);
++
++	return 0;
++}
++
++static int bluesleep_resume(struct platform_device *pdev)
++{
++	if(bt_wake >= 0)
++		disable_irq_wake(bt_wake_irq);
++
++	return 0;
++}
++static int __init_or_module bt_power_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	ret = bt_power_rfkill_probe(pdev);
++	if (ret) {
++		return ret;
++	}
++
++	if(bt_rst_n > 0){
++		ret = gpio_request(bt_rst_n,"bt_rst_n");
++		if(unlikely(ret)){
++			return ret;
++		}
++	}
++
++	if (bt_reg_on > 0){
++		ret = gpio_request(bt_reg_on,"bt_reg_on");
++		if(unlikely(ret)){
++			gpio_free(bt_rst_n);
++			return ret;
++		}
++		gpio_direction_output(bt_reg_on, 0);
++	}
++
++	if(bt_wake >= 0){
++		ret = gpio_request(bt_wake,"bt_wake");
++		if(unlikely(ret)){
++			printk("bt_wake request failed\n");
++			return ret;
++		}
++	}
++
++	ret = gpio_direction_input(bt_wake);
++	if (ret < 0) {
++		pr_err("gpio-keys: failed to configure input"
++				" direction for GPIO %d, error %d\n",
++				bt_wake, ret);
++		return ret;
++	}
++
++	bt_wake_irq = gpio_to_irq(bt_wake);
++	if (bt_wake_irq < 0) {
++		printk("couldn't find host_wake irq\n");
++		return -1;
++	}
++	ret = request_irq(bt_wake_irq, bt_wake_host_cb,
++			/*IRQF_DISABLED |*/ IRQF_TRIGGER_RISING,
++			"bluetooth bthostwake", NULL);
++	if (ret < 0) {
++		printk("Couldn't acquire BT_HOST_WAKE IRQ err (%d)\n", ret);
++		return -1;
++	}
++
++	if(bt_rst_n > 0){
++		gpio_direction_output(bt_rst_n,1);
++	}
++	return 0;
++}
++
++static int bt_power_remove(struct platform_device *pdev)
++{
++	int ret;
++
++	bt_power_rfkill_remove(pdev);
++
++	mutex_lock(&bt_power_lock);
++	bt_power_state = 0;
++	ret = bt_power_control(bt_power_state);
++	mutex_unlock(&bt_power_lock);
++
++	return ret;
++}
++
++static const struct of_device_id bt_power_match[] = {
++	{.compatible = "ingenic,bt_power",},
++	{},
++};
++MODULE_DEVICE_TABLE(of, bt_power_match);
++static struct platform_driver bt_power_driver = {
++	.probe = bt_power_probe,
++	.remove = bt_power_remove,
++	.suspend = bluesleep_suspend,
++	.resume = bluesleep_resume,
++	.driver = {
++		.name = DEV_NAME,
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(bt_power_match),
++	},
++};
++
++module_platform_driver(bt_power_driver);
++MODULE_LICENSE("GPL v2");
++MODULE_DESCRIPTION("Bluetooth power control driver");
++MODULE_VERSION("1.0");
+diff --git a/module_drivers/drivers/misc/hamming.c b/module_drivers/drivers/misc/hamming.c
+new file mode 100644
+index 000000000..b2ef71f6d
+--- /dev/null
++++ b/module_drivers/drivers/misc/hamming.c
+@@ -0,0 +1,374 @@
++
++static int checkbit(unsigned int *s,unsigned int *d,int ss,int ds,int bsz)
++{
++	int sg32,sb32,dg32,db32;
++
++	while(bsz > 0){
++		sg32 = ss / 32;
++		sb32 = ss % 32;
++		dg32 = ds / 32;
++		db32 = ds % 32;
++		if(
++			((s[sg32] >> sb32) & 1) !=
++			((d[dg32] >> db32) & 1)
++		)
++			break;
++		ss++;
++		ds++;
++		bsz--;
++	}
++	return bsz;
++}
++
++static int dump(unsigned int *s,int st,int en)
++{
++	int i;
++
++	for(i = st;i < en;i++){
++
++		if((i - st) % 32 == 0){
++			printk("\n");
++		}else if((i - st) % 8 == 0){
++			printk(" ");
++		}
++
++		if(s[i / 32] & (1 << (i % 32)))
++			printk("1");
++		else
++			printk("0");
++
++	}
++	printk("\n");
++	return 0;
++}
++
++static int dumphex(unsigned int *s,int sz)
++{
++	int i;
++
++	for(i = 0;i < sz;i++){
++		printk("%08x\n",s[i]);
++	}
++	return 0;
++}
++
++
++// bits + k = 2^k - 1.
++// result k.
++static int cal_k(int bits)
++{
++	int k = 0;
++	unsigned int cur = 1;
++	while(cur - 1 < bits + k){
++		cur <<= 1;
++		k++;
++	}
++	return k;
++}
++
++/**
++ *  @brief bitcpy
++ *
++ *  copy bit from *s buffer to *d buffer.
++ *
++ *  @param s  source buffer.
++ *  @param d  target buffer.
++ *  @param ss start position of source buffer.
++ *  @param ds start position of target buffer.
++ *  @param bsz bit count of copy.
++ */
++static void bitcpy(const unsigned int *s,unsigned int *d,
++	const int ss,const int ds,int bsz)
++{
++	int ss_int = ss / 32;
++	int ss_bit = ss % 32;
++
++	int ds_int = ds / 32;
++	int ds_bit = ds % 32;
++#define MMIN(a,b) (a) > (b) ? (b) : (a)
++	while(bsz != 0){
++		unsigned int src,dst,bmsk;
++		int min = MMIN(32 - ss_bit,32 - ds_bit);
++		min = MMIN(min,bsz);
++		bmsk = 0xffffffff >> (32 - min);
++		src = s[ss_int] >> ss_bit;
++		src &= bmsk;
++
++		dst = d[ds_int];
++		dst &= ~(bmsk << ds_bit);
++		dst |= src << ds_bit;
++
++		d[ds_int] = dst;
++		ds_bit += min;
++		if(ds_bit >= 32){
++			ds_int++;
++			ds_bit = 0;
++		}
++		ss_bit += min;
++		if(ss_bit >= 32){
++			ss_int++;
++			ss_bit = 0;
++		}
++//		printk("bsz = %d min = %d\n",bsz,min);
++		bsz -= min;
++	}
++}
++
++/**
++ *  @brief bit32_cal_xor
++ *
++ *  The data is xor to 64bit by 32bit unit.
++ *
++ *  @param s The Data buffer.
++ *  @param bitsz  The data's bit count.
++ *  @return length Remained data bit count.
++ */
++static int bit32_cal_xor(const unsigned int *s,int bitsz,unsigned int *d)
++{
++	int j;
++	if(bitsz > 64){
++		unsigned int bit32 = s[0];
++		for(j = 32;j < bitsz / 32 * 32;j+=32){
++			bit32 ^= s[j / 32];
++		}
++		d[0] = bit32;
++		if(bitsz % 32)
++			d[1] = s[j/32];
++
++		return 32 + (bitsz % 32);
++	}else if(bitsz > 32){
++		d[0] = s[0];
++		d[1] = s[1];
++	}else
++		d[0] = s[0];
++	return bitsz;
++}
++/**
++ *  @brief bit_index_cal_xor
++ *
++ *  Calibrate general data hamming and Maximin size is 32bit.
++ *
++ *  @param d  32bit data buffer.
++ *  @param bitsz  bit size.
++ *  @param index  k value.
++ *  @param xor    head result.
++ *  @return xor result.
++ */
++static int bit_index_cal_xor(const unsigned int *d,int bitsz,int index,unsigned int xor)
++{
++	int sz = bitsz;
++	int gap = (1 << index);
++	int j,i;
++	int pre_g = 0;
++	unsigned int bit32;
++	j = gap - 1;
++	bit32 = d[pre_g];
++	while(j < sz){
++		for(i = 0;i < (1 << index);i++){
++			int g = (j + i) / 32;
++			int b = (j + i) % 32;
++			if(g != pre_g){
++				pre_g = g;
++				bit32 = d[pre_g];
++			}
++			xor ^= (bit32 >> b) & 1;
++		}
++		gap += 2 * (1 << index);
++		j += 2 * (1 << index);
++	}
++	return xor;
++}
++
++/**
++ *  @brief bit_cal_xor_first
++ *
++ *  Get the highest position of the POS location.
++ *
++ *  @param s  data buffer.
++ *  @param pos bit position.
++ *  @return 31'b bit
++ */
++static unsigned int get_highest_bit(const unsigned int *s,int pos)
++{
++	unsigned int xor;
++	unsigned int bit32 = s[pos / 32];
++	xor = bit32 >> 31;
++	return xor;
++}
++
++/**
++ *  @brief bit_cal_xor
++ *
++ *  XOR value of calculated data.
++ *
++ *  @param s data buffer.
++ *  @param s calculated bit width.
++ *  @param pos bit position.
++ *  @param xor previous xor value.
++ *  @return XOR value.
++ */
++static unsigned int bit_cal_xor(const unsigned int *s,int bitsz,int pos,unsigned int xor)
++{
++	unsigned int bit32 = s[pos / 32];
++	int bitpos = pos % 32;
++	int i;
++//	printk("--bitsz = %d pos = %d\n",bitsz,pos);
++	if(bitpos){
++		int endpos = bitsz > (32 - bitpos) ? 32 : bitsz + bitpos;
++		int sz = endpos - bitpos;
++		for(i = bitpos;i < endpos;i++){
++			xor ^= (bit32 >> i) & 1;
++		}
++		bitsz -= sz;
++		pos += sz;
++	}
++	if(bitsz > 32){
++		for(i = 32;i < bitsz / 32 * 32;i += 32){
++			bit32 ^= s[(pos + i)/32];
++		}
++		pos += i;
++		for(i = 0;i < 32;i++){
++			xor ^= (bit32 >> i) & 1;
++		}
++		bitsz = bitsz % 32;
++	}
++	if(bitsz)
++		bit32 = s[pos/32];
++
++	for(i = 0;i < bitsz;i++){
++		xor ^= (bit32 >> i) & 1;
++	}
++	return xor;
++}
++
++/**
++ *  @brief cal_xor_ge32
++ *
++ *  Calculate XOR values of segments larger than or equal to 32bit data.
++ *
++ *  @param d data buffer.
++ *  @param dsz bit width of data buffer.
++ *  @param segments interval.
++ *  @return Xor value.
++ */
++static int cal_xor_ge32(const unsigned int *d,int dsz,int index,int xor)
++{
++	int i;
++	int step = 1 << index;
++	int min;
++	for(i = step - 1;i < dsz;i += step * 2){
++		xor ^= get_highest_bit(d,i);
++		min = dsz - i - 1  > step - 1 ? step - 1 : dsz - i - 1;
++		if(min > 0)
++			xor = bit_cal_xor(d, min, i + 1, xor);
++	}
++	return xor;
++}
++
++int encode(unsigned int *s,int bits,unsigned int *d)
++{
++	int k = cal_k(bits);
++	int i,j,p;
++	int bitsz;
++	unsigned int xor = 0;
++	i = 0;
++	p = 0;
++	j = 0;
++	bits += k;
++
++	while(j < bits){
++		int curindex,bsz;
++		curindex = (1 << p);
++		if(j + 1 != curindex){
++			bsz = (curindex - j - 1);
++			if((bits - j) < bsz){
++				bsz = bits - j;
++			}
++			bitcpy(s,d,i,j,bsz);
++			i += bsz;
++			j += bsz;
++		}else{
++			unsigned int dst;
++			unsigned int msk = 1 << (j % 32);
++			dst = d[j / 32];
++			dst &= ~msk;
++			d[j / 32] = dst;
++			j++;
++			p++;
++		}
++	}
++//	dump(d,0,bits);
++
++	// cal xor.
++	bitsz = bit32_cal_xor(d,bits,s);
++//	dump(s,0,bits);
++//	dump(d,0,bits);
++
++	i = 0;
++	while((1 << i) < bits){
++		if(i < 5){
++			xor = bit_index_cal_xor(s,bitsz,i,0);
++//			dump(d,0,bits);
++		}else{
++			xor = cal_xor_ge32(d,bits,i,0);
++//			dump(d,0,bits);
++		}
++		p = (1 << i) - 1;
++		i++;
++		d[p / 32] &= ~(1 << (p % 32));
++		d[p / 32] |= (xor << (p % 32));
++	}
++	return bits;
++}
++
++int decode(unsigned int *s,int bits,unsigned int *d)
++{
++	int i,p,j;
++	int xor = 0;
++	int errbit = 0;
++	int bitsz;
++
++	bitsz = bit32_cal_xor(s,bits,d);
++
++	i = 0;
++	while((1 << i) < bits)
++	{
++		if(i < 5){
++			xor = bit_index_cal_xor(d,bitsz,i,0);
++		}else
++			xor = cal_xor_ge32(s,bits,i,0);
++		errbit |= xor << i;
++		i++;
++	}
++
++	if(errbit > 0){
++		errbit = errbit - 1;
++		xor = 1 << (errbit % 32);
++		s[errbit / 32] ^= xor;
++		s[errbit / 32] ^= 0;
++	}
++
++	i = 0;
++	p = 0;
++	j = 0;
++	while(j < bits){
++		int curindex,bsz;
++		curindex = (1 << p);
++		if(j + 1 != curindex){
++			bsz = (curindex - j - 1);
++			if((bits - j) < bsz){
++				bsz = bits - j;
++			}
++			bitcpy(s,d,j,i,bsz);
++			i += bsz;
++			j += bsz;
++		}else{
++			j++;
++			p++;
++		}
++	}
++
++//	dump(d,0,bits);
++	return i;
++}
++
+diff --git a/module_drivers/drivers/misc/ingenic_efuse_v2.c b/module_drivers/drivers/misc/ingenic_efuse_v2.c
+new file mode 100644
+index 000000000..911dfdfca
+--- /dev/null
++++ b/module_drivers/drivers/misc/ingenic_efuse_v2.c
+@@ -0,0 +1,745 @@
++/*
++ * linux/drivers/misc/ingenic_efuse_v2.c - Ingenic efuse driver
++ *
++ * Copyright (C) 2012 Ingenic Semiconductor Co., Ltd.
++ * Author: <zhihao.xiao@ingenic.com>.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#define	DEBUG
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/kernel.h>
++#include <linux/gpio.h>
++#include <linux/init.h>
++#include <linux/miscdevice.h>
++#include <linux/sched.h>
++#include <linux/ctype.h>
++#include <linux/fs.h>
++#include <linux/timer.h>
++#include <linux/jiffies.h>
++#include <linux/clk.h>
++#include <linux/proc_fs.h>
++#include <linux/seq_file.h>
++#include <linux/regulator/consumer.h>
++#include <linux/of_gpio.h>
++#include <linux/of_platform.h>
++#include <soc/base.h>
++#include <soc/efuse.h>
++#include <ingenic_proc.h>
++#include <linux/delay.h>
++
++
++
++#define DRV_NAME	"ingenic-efuse"
++
++#define CMD_WRITE	 _IOR('E', 100, unsigned int)
++#define CMD_READ	 _IOR('E', 101, unsigned int)
++
++struct efuse_wr_info {
++	uint32_t seg_id;
++	uint8_t *data;
++};
++
++struct board_gpio {
++	short gpio;
++	short level;
++};
++
++struct jz_efuse {
++	struct device *dev;
++	struct miscdevice mdev;
++	struct efuse_wr_info *wr_info;
++	struct mutex lock;
++	void __iomem *iomem;
++#ifdef CONFIG_INGENIC_EFUSE_V2_WRITABLE
++	struct timer_list vddq_protect_timer;
++	struct board_gpio avd_efuse_en;
++#endif
++};
++
++static struct jz_efuse *efuse;
++static struct seg_info info;
++
++static uint32_t efuse_readl(uint32_t reg_off)
++{
++	return readl(efuse->iomem + reg_off);
++}
++
++static void efuse_writel(uint32_t val, uint32_t reg_off)
++{
++	writel(val, efuse->iomem + reg_off);
++}
++
++#ifdef CONFIG_INGENIC_EFUSE_V2_WRITABLE
++static void efuse_vddq_set_timer(struct timer_list *t)
++{
++	struct jz_efuse *efuse_test = from_timer(efuse, t, vddq_protect_timer);
++	gpio_direction_output(efuse->avd_efuse_en.gpio, !efuse->avd_efuse_en.level);
++}
++
++static void efuse_vddq_set(unsigned long on)
++{
++	if(on){
++		mod_timer(&efuse->vddq_protect_timer, jiffies + msecs_to_jiffies(800));
++	}
++	gpio_direction_output(efuse->avd_efuse_en.gpio, on);
++}
++#else
++static void efuse_vddq_set(unsigned long on) {}
++#endif
++
++static int efuse_open(struct inode *inode, struct file *filp)
++{
++	return 0;
++}
++
++static int efuse_release(struct inode *inode, struct file *filp)
++{
++	return 0;
++}
++
++static void otp_r(uint32_t addr, uint32_t blen)
++{
++	unsigned int val;
++	int n;
++
++	efuse_writel(0, EFUSE_CTRL);
++
++	for(n = 0; n < 8; n++)
++		efuse_writel(0, EFUSE_DATA(n));
++
++	/* set read address and data length */
++	val =  addr << EFUSE_CTRL_ADDR | (blen - 1) << EFUSE_CTRL_LEN;
++	efuse_writel(val, EFUSE_CTRL);
++
++	/* enable read */
++	val = efuse_readl(EFUSE_CTRL);
++	val |= EFUSE_CTRL_RDEN;
++	efuse_writel(val, EFUSE_CTRL);
++
++	dev_dbg(efuse->dev,"efuse ctrl regval=0x%x\n",val);
++	/* wait read done status */
++	while(!(efuse_readl(EFUSE_STATE) & EFUSE_STA_RD_DONE));
++}
++
++static int jz_efuse_read(struct seg_info *info, uint8_t *buf)
++{
++	int i;
++	unsigned int *data = (volatile unsigned int *)(efuse->iomem + EFUSE_DATA(0));
++	unsigned byte_len = (info->bit_num >> 3);
++
++	dev_dbg(efuse->dev,"segment name: %s\nsegment addr: 0x%02x\nbyte num: %d\nbit num: %d\n",
++			info->seg_name, info->offset_address, byte_len, info->bit_num);
++
++	otp_r(info->offset_address, byte_len);
++
++	dev_dbg(efuse->dev, "efuse read data:\n");
++	for(i = 0; i < 8; i++ )
++		dev_dbg(efuse->dev,"0x%08x\n", data[i]);
++
++	memcpy(buf, data, 32);
++
++	/* clear read done status */
++	efuse_writel(0, EFUSE_STATE);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(jz_efuse_read);
++
++static void otp_w(uint32_t addr, uint32_t blen)
++{
++	unsigned int val;
++
++	efuse_writel(0, EFUSE_CTRL);
++
++	/* set write Programming address and data length */
++	val =  addr << EFUSE_CTRL_ADDR | (blen - 1) << EFUSE_CTRL_LEN;
++	efuse_writel(val, EFUSE_CTRL);
++
++	/* Programming EFUSE enable */
++	val = efuse_readl(EFUSE_CTRL);
++	val |= EFUSE_CTRL_PGEN;
++	efuse_writel(val, EFUSE_CTRL);
++
++	/* Connect VDDQ pin from 2.5V */
++	efuse_vddq_set(1);
++	mdelay(1);
++
++	/* enable write */
++	val = efuse_readl(EFUSE_CTRL);
++	val |= EFUSE_CTRL_WREN;
++	efuse_writel(val, EFUSE_CTRL);
++
++	/* wait write done status */
++	while(!(efuse_readl(EFUSE_STATE) & EFUSE_STA_WR_DONE));
++
++	/* Disconnect VDDQ pin from 2.5V. */
++	efuse_vddq_set(0);
++	mdelay(1);
++
++	val = efuse_readl(EFUSE_CTRL);
++	val &= ~(EFUSE_CTRL_PGEN);
++	efuse_writel(val, EFUSE_CTRL);
++}
++
++static int jz_efuse_write(struct seg_info *info, uint8_t *buf)
++{
++	int i;
++	unsigned int *data = (volatile unsigned int *)(efuse->iomem + EFUSE_DATA(0));
++	unsigned int byte_len = (info->bit_num >> 3);
++	unsigned int regval = 0;
++
++	dev_dbg(efuse->dev,"segment name: %s\nsegment addr: 0x%02x\nbyte num: %d\nbit num: %d\n",
++			info->seg_name, info->offset_address, byte_len, info->bit_num);
++
++	if(info->seg_id != PRT) {
++		regval = efuse_readl(EFUSE_STATE);
++		if(info->prt_bit & regval) {
++			dev_err(efuse->dev, "segment[%s] has been protected!\n", info->seg_name);
++			return -1;
++		}
++	}
++
++	memset(data, 0, 4 * 8);
++	memcpy(data, buf, 32);
++	dev_dbg(efuse->dev, "efuse write data:\n");
++	for(i = 0; i < 8; i++)
++		dev_dbg(efuse->dev,"%08x\n", data[i]);
++
++	otp_w(info->offset_address, byte_len);
++
++	return 0;
++}
++
++
++static long efuse_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
++{
++	struct miscdevice *dev = filp->private_data;
++	struct jz_efuse *efuse = container_of(dev, struct jz_efuse, mdev);
++	int ret = 0;
++
++	mutex_lock(&efuse->lock);
++	efuse->wr_info = (struct efuse_wr_info *)arg;
++
++	if(efuse->wr_info->seg_id > ARRAY_SIZE(seg_info_array)) {
++		dev_err(efuse->dev, "unknow segment id!\n");
++		goto exit;
++	}
++
++	info = seg_info_array[efuse->wr_info->seg_id];
++	switch (cmd) {
++		case CMD_READ:
++			ret = jz_efuse_read(&info, efuse->wr_info->data);
++			break;
++		case CMD_WRITE:
++			ret = jz_efuse_write(&info, efuse->wr_info->data);
++			break;
++		default:
++			dev_err(efuse->dev, "unknow cmd!\n");
++			break;
++	}
++exit:
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static struct file_operations efuse_misc_fops = {
++	.open		= efuse_open,
++	.release	= efuse_release,
++	.unlocked_ioctl	= efuse_ioctl,
++};
++
++
++static int set_efuse_timing(struct device *dev)
++{
++	struct clk *h2clk;
++	struct clk *devclk;
++	unsigned long rate;
++	uint32_t val, ns;
++	int i, rd_strobe, wr_strobe;
++	uint32_t rd_adj, wr_adj;
++	int flag = 0;
++
++	h2clk = devm_clk_get(dev, "div_ahb2");
++	if (IS_ERR(h2clk)) {
++		dev_err(efuse->dev, "get h2clk rate fail!\n");
++		return -1;
++	}
++
++	devclk = devm_clk_get(dev, "gate_efuse");
++	if (IS_ERR(devclk)) {
++		dev_err(efuse->dev, "get efuse clk rate fail!\n");
++		return -1;
++	}
++	clk_prepare_enable(devclk);
++
++	rate = clk_get_rate(h2clk);
++	ns = 1000000000 / rate;
++	printk("rate = %lu, ns = %d\n", rate, ns);
++
++
++	for(i = 0; i < 0x4; i++)
++		if((( i + 1) * ns ) > 7)
++			break;
++	if(i == 0x4) {
++		dev_err(efuse->dev, "get efuse cfg rd_adj fail!\n");
++		return -1;
++	}
++	rd_adj = wr_adj = i;
++
++	for(i = 0; i < 0x8; i++)
++		if(((rd_adj + i + 5) * ns ) > 35)
++			break;
++	if(i == 0x8) {
++		dev_err(efuse->dev, "get efuse cfg rd_strobe fail!\n");
++		return -1;
++	}
++	rd_strobe = i;
++
++	for(i = 0; i < 0x7ff; i++) {
++		val = (wr_adj + i + 1666) * ns;
++		if(val > 11 * 1000) {
++			val = (wr_adj - i + 1666) * ns;
++			flag = 1;
++		}
++		if(val > 9 * 1000 && val < 11 * 1000)
++			break;
++	}
++	if(i >= 0x7ff) {
++		dev_err(efuse->dev, "get efuse cfg wd_strobe fail!\n");
++		return -1;
++	}
++
++	if(flag)
++		i |= 1 << 11;
++
++	wr_strobe = i;
++
++	dev_info(efuse->dev, "rd_adj = %d | rd_strobe = %d | "
++		 "wr_adj = %d | wr_strobe = %d\n", rd_adj, rd_strobe,
++		 wr_adj, wr_strobe);
++
++	/*set configer register*/
++	val = rd_adj << EFUSE_CFG_RD_ADJ | rd_strobe << EFUSE_CFG_RD_STROBE;
++	val |= wr_adj << EFUSE_CFG_WR_ADJ | wr_strobe;
++	efuse_writel(val, EFUSE_CFG);
++
++	clk_put(h2clk);
++
++	return 0;
++}
++
++static int show_segment(uint32_t seg_id,  char *buf)
++{
++	int ret = 0;
++	int i = 0;
++	unsigned char val[32] = {0};
++	char *last = NULL;
++	info = seg_info_array[seg_id];
++	last = (char *)val + info.bit_num / 8 - 1;
++
++	jz_efuse_read(&info, val);
++	for(i = 0; i < info.bit_num / 8; i++)
++		ret += snprintf(buf + (i * 2), 3, "%02x", *((uint8_t *)last - i));
++	strcat(buf, "\n");
++
++	return ret + 1;
++}
++
++static ssize_t chipid_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(CHIPID, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static ssize_t cutid_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(CUTID, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static ssize_t trim0_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(TRIM0, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static ssize_t trim1_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(TRIM1, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static ssize_t trim2_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(TRIM2, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static ssize_t trim3_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(TRIM3, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static ssize_t socinfo_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(SOCINFO, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static ssize_t hideblk_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(HIDEBLK, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static ssize_t prt_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(PRT, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static void store_segment(uint32_t seg_id, const char *buf, int len)
++{
++	int i = 0;
++	unsigned char val[32] = {0};
++	char tmp[9] = {'\0'};
++	char *last = (char *)buf + (len - 1);
++	int bit_num = (len - 1) * 4;
++	int byte_len = (len - 1) / 2;
++	info = seg_info_array[seg_id];
++
++	memset(val, 0, 32);
++
++	if (bit_num == info.bit_num) {
++		for (i = 0; i < byte_len; i++) {
++			memcpy(tmp, last - ((i + 1) * 2), 2);
++			sscanf(tmp, "%02hhx", &val[i]);
++			printk("%02x\n", val[i]);
++		}
++
++		jz_efuse_write(&info, val);
++	} else {
++		printk("%s segment size is %d bits!\n", info.seg_name, info.bit_num);
++	}
++}
++
++static ssize_t chipid_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(CHIPID, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++static ssize_t cutid_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(CUTID, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++static ssize_t trim0_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(TRIM0, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++static ssize_t trim1_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(TRIM1, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++static ssize_t trim2_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(TRIM2, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++static ssize_t trim3_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(TRIM3, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++static ssize_t socinfo_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(SOCINFO, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++static ssize_t hideblk_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(HIDEBLK, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++static ssize_t prt_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(PRT, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++
++static DEVICE_ATTR(chipid,  S_IRUGO|S_IWUSR, chipid_show,  chipid_store);
++static DEVICE_ATTR(cutid,   S_IRUGO|S_IWUSR, cutid_show,   cutid_store);
++static DEVICE_ATTR(trim0,   S_IRUGO|S_IWUSR, trim0_show,   trim0_store);
++static DEVICE_ATTR(trim1,   S_IRUGO|S_IWUSR, trim1_show,   trim1_store);
++static DEVICE_ATTR(trim2,   S_IRUGO|S_IWUSR, trim2_show,   trim2_store);
++static DEVICE_ATTR(trim3,   S_IRUGO|S_IWUSR, trim3_show,   trim3_store);
++static DEVICE_ATTR(socinfo, S_IRUGO|S_IWUSR, socinfo_show, socinfo_store);
++static DEVICE_ATTR(hideblk, S_IRUGO|S_IWUSR, hideblk_show, hideblk_store);
++static DEVICE_ATTR(prt,     S_IRUGO|S_IWUSR, prt_show,     prt_store);
++static DEVICE_ATTR(chipkey, S_IRUGO|S_IWUSR, NULL, NULL);
++static DEVICE_ATTR(userkey, S_IRUGO|S_IWUSR, NULL, NULL);
++static DEVICE_ATTR(nku,     S_IRUGO|S_IWUSR, NULL, NULL);
++
++static struct attribute *efuse_rw_attrs[] = {
++	&dev_attr_chipid.attr,
++	&dev_attr_cutid.attr,
++	&dev_attr_trim0.attr,
++	&dev_attr_trim1.attr,
++	&dev_attr_trim2.attr,
++	&dev_attr_trim3.attr,
++	&dev_attr_socinfo.attr,
++	&dev_attr_hideblk.attr,
++	&dev_attr_prt.attr,
++	&dev_attr_chipkey.attr,
++	&dev_attr_userkey.attr,
++	&dev_attr_nku.attr,
++	NULL,
++};
++
++const char efuse_group_name[] = "efuse_rw";
++static struct attribute_group efuse_rw_attr_group = {
++	.name   = efuse_group_name,
++	.attrs  = efuse_rw_attrs,
++};
++
++
++#ifdef CONFIG_INGENIC_EFUSE_V2_WRITABLE
++static int of_avd_efuse(struct device *dev)
++{
++	struct jz_efuse *efuse = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++#if 1
++	efuse->avd_efuse_en.gpio = of_get_named_gpio_flags(np, "ingenic,efuse-en-gpio", 0, &flags);
++	if(!gpio_is_valid(efuse->avd_efuse_en.gpio)) {
++		ret = efuse->avd_efuse_en.gpio;
++		dev_err(dev, "efuse_en gpio invalid! %d\n", ret);
++		return ret;
++	}
++
++	ret = devm_gpio_request(dev, efuse->avd_efuse_en.gpio, "efuse-en");
++	if(ret < 0) {
++		dev_err(dev, "efuse_en gpio request failed! %d\n", ret);
++		return ret;
++	}
++	efuse->avd_efuse_en.level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++#else
++	efuse->pmu_efuse_en = regulator_get(NULL, "LDO2_1V8");
++	if(!efuse->pmu_efuse_en) {
++		dev_err(dev, "get efuse regulator failed\n");
++		return -1;
++	}
++#endif
++	return 0;
++}
++#endif
++
++static int jz_efuse_probe(struct platform_device *pdev)
++{
++	struct resource *res = NULL;
++	int ret = 0;
++
++	efuse = devm_kzalloc(&pdev->dev, sizeof(struct jz_efuse), GFP_KERNEL);
++	if (!efuse) {
++		printk("efuse malloc failed!\n");
++		return -ENOMEM;
++	}
++
++	mutex_init(&efuse->lock);
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (IS_ERR_OR_NULL(res)) {
++		dev_err(&pdev->dev, "get efuse resource failed!\n");
++		ret = -ENXIO;
++		goto err_free_efuse;
++	}
++
++	efuse->iomem = devm_ioremap(&pdev->dev, res->start, resource_size(res));
++	if (IS_ERR_OR_NULL(efuse->iomem)) {
++		dev_err(&pdev->dev, "efuse ioremap failed!\n");
++		ret = -EBUSY;
++		goto err_free_efuse;
++	}
++
++	efuse->dev = &pdev->dev;
++	efuse->wr_info = NULL;
++	efuse->mdev.minor = MISC_DYNAMIC_MINOR;
++	efuse->mdev.name =  DRV_NAME;
++	efuse->mdev.fops = &efuse_misc_fops;
++
++	ret = misc_register(&efuse->mdev);
++	if (ret < 0) {
++		dev_err(efuse->dev, "efuse misc_register failed\n");
++		ret = -EINVAL;
++		goto err_free_efuse_io;
++	}
++	platform_set_drvdata(pdev, efuse);
++#ifdef CONFIG_INGENIC_EFUSE_V2_WRITABLE
++	ret = of_avd_efuse(efuse->dev);
++	if (ret < 0) {
++		goto err_free_efuse_io;
++	}
++
++	dev_info(efuse->dev, "setup vddq_protect_timer!\n");
++	timer_setup(&efuse->vddq_protect_timer, efuse_vddq_set_timer, 0);
++	add_timer(&efuse->vddq_protect_timer);
++
++#endif
++	ret = set_efuse_timing(efuse->dev);
++	if(ret) {
++		dev_err(efuse->dev, "efuse timing setting failed!\n");
++		ret = -EINVAL;
++		goto err_free_efuse_io;
++	}
++
++	ret = sysfs_create_group(&pdev->dev.kobj, &efuse_rw_attr_group);
++	if (ret) {
++		dev_err(efuse->dev, "device create sysfs group failed\n");
++		ret = -EINVAL;
++		goto err_free_efuse_io;
++	}
++
++
++	dev_info(efuse->dev, "efuse probe success.\n");
++	return 0;
++
++
++err_free_efuse_io:
++	iounmap(efuse->iomem);
++err_free_efuse:
++	kfree(efuse);
++
++	return ret;
++}
++
++
++static int jz_efuse_remove(struct platform_device *dev)
++{
++	struct jz_efuse *efuse = platform_get_drvdata(dev);
++
++	misc_deregister(&efuse->mdev);
++#ifdef CONFIG_INGENIC_EFUSE_V2_WRITABLE
++	dev_info(efuse->dev, "del vddq_protect_timer!\n");
++	del_timer(&efuse->vddq_protect_timer);
++#endif
++	iounmap(efuse->iomem);
++	kfree(efuse);
++
++	return 0;
++}
++
++static const struct of_device_id efuse_of_match[] = {
++	{ .compatible = "ingenic,x1600-efuse"},
++	{},
++};
++
++static struct platform_driver jz_efuse_driver = {
++	.driver = {
++		.name = DRV_NAME,
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(efuse_of_match),
++	},
++	.probe		= jz_efuse_probe,
++	.remove		= jz_efuse_remove,
++};
++
++static int __init jz_efuse_init(void)
++{
++	return platform_driver_register(&jz_efuse_driver);
++}
++
++static void __exit jz_efuse_exit(void)
++{
++	platform_driver_unregister(&jz_efuse_driver);
++}
++
++
++module_init(jz_efuse_init);
++module_exit(jz_efuse_exit);
++
++MODULE_DESCRIPTION("efuse v2 driver");
++MODULE_AUTHOR("zhxiao <zhihao.xiao@ingenic.com>");
++MODULE_LICENSE("GPL v2");
++MODULE_VERSION("20210823");
+diff --git a/module_drivers/drivers/misc/ingenic_efuse_x2000.c b/module_drivers/drivers/misc/ingenic_efuse_x2000.c
+new file mode 100644
+index 000000000..1ec9e467e
+--- /dev/null
++++ b/module_drivers/drivers/misc/ingenic_efuse_x2000.c
+@@ -0,0 +1,1128 @@
++/*
++ * linux/drivers/misc/ingenic_efuse_x2000.c - Ingenic efuse driver
++ *
++ * Copyright (C) 2012 Ingenic Semiconductor Co., Ltd.
++ * Author: <chongji.wang@ingenic.com>.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#define	DEBUG
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/kernel.h>
++#include <linux/gpio.h>
++#include <linux/init.h>
++#include <linux/miscdevice.h>
++#include <linux/sched.h>
++#include <linux/ctype.h>
++#include <linux/fs.h>
++#include <linux/timer.h>
++#include <linux/jiffies.h>
++#include <linux/clk.h>
++#include <linux/proc_fs.h>
++#include <linux/seq_file.h>
++#include <linux/regulator/consumer.h>
++#include <linux/of_gpio.h>
++#include <linux/of_platform.h>
++#include <soc/base.h>
++#include <soc/efuse.h>
++#include <ingenic_proc.h>
++
++#include "hamming.c"
++
++
++#define DRV_NAME	"ingenic-efuse"
++
++#define CMD_WRITE	 _IOR('E', 100, unsigned int)
++#define CMD_READ	 _IOR('E', 101, unsigned int)
++
++struct efuse_wr_info {
++	uint32_t seg_id;
++	uint32_t *data;
++};
++
++struct board_gpio {
++	short gpio;
++	short level;
++};
++
++struct jz_efuse {
++	struct device *dev;
++	struct miscdevice mdev;
++	struct efuse_wr_info *wr_info;
++	struct mutex lock;
++	void __iomem *iomem;
++#ifdef CONFIG_INGENIC_EFUSE_WRITABLE
++	struct timer_list vddq_protect_timer;
++//	struct regulator *pmu_efuse_en;
++	struct board_gpio avd_efuse_en;
++#endif
++};
++
++static struct jz_efuse *efuse;
++static struct seg_info info;
++
++static uint32_t efuse_readl(uint32_t reg_off)
++{
++	return readl(efuse->iomem + reg_off);
++}
++
++static void efuse_writel(uint32_t val, uint32_t reg_off)
++{
++	writel(val, efuse->iomem + reg_off);
++}
++
++#ifdef CONFIG_INGENIC_EFUSE_WRITABLE
++static void efuse_vddq_set(unsigned long on)
++{
++	if(on){
++		mod_timer(&efuse->vddq_protect_timer, jiffies + HZ);
++	}
++	gpio_direction_output(efuse->avd_efuse_en.gpio, !on);
++}
++#else
++static void efuse_vddq_set(unsigned long on) {}
++#endif
++
++static int efuse_open(struct inode *inode, struct file *filp)
++{
++	return 0;
++}
++
++static int efuse_release(struct inode *inode, struct file *filp)
++{
++	return 0;
++}
++
++static void otp_r(uint32_t addr, uint32_t wlen)
++{
++	unsigned int val;
++	int n;
++
++	efuse_writel(0, EFUSE_CTRL);
++
++	for(n = 0; n < 8; n++)
++		efuse_writel(0, EFUSE_DATA(n));
++
++	/* set read address and data length */
++	val =  addr << EFUSE_CTRL_ADDR | (wlen - 1) << EFUSE_CTRL_LEN;
++	efuse_writel(val, EFUSE_CTRL);
++
++	val = efuse_readl(EFUSE_CTRL);
++	val &= ~EFUSE_CTRL_PD;
++	efuse_writel(val, EFUSE_CTRL);
++
++	/* enable read */
++	val = efuse_readl(EFUSE_CTRL);
++	val |= EFUSE_CTRL_RDEN;
++	efuse_writel(val, EFUSE_CTRL);
++
++	dev_dbg(efuse->dev,"efuse ctrl regval=0x%x\n",val);
++	/* wait read done status */
++	while(!(efuse_readl(EFUSE_STATE) & EFUSE_STA_RD_DONE));
++
++	efuse_writel(0, EFUSE_CTRL);
++	efuse_writel(EFUSE_CTRL_PD, EFUSE_CTRL);
++}
++
++void rir_w(uint32_t addr, uint32_t value)
++{
++	unsigned int val;
++
++	efuse_writel(value, EFUSE_DATA(0));
++	efuse_writel(0, EFUSE_CTRL);
++
++	val =  addr << EFUSE_CTRL_ADDR | 0 << EFUSE_CTRL_LEN;
++	efuse_writel(val, EFUSE_CTRL);
++
++	val = efuse_readl(EFUSE_CTRL);
++	val &= ~EFUSE_CTRL_PD;
++	efuse_writel(val, EFUSE_CTRL);
++
++	val = efuse_readl(EFUSE_CTRL);
++	val |= EFUSE_CTRL_PS | EFUSE_CTRL_RWL;
++	efuse_writel(val, EFUSE_CTRL);
++
++	val = efuse_readl(EFUSE_CTRL);
++	val |= EFUSE_CTRL_PGEN;
++	efuse_writel(val, EFUSE_CTRL);
++
++	efuse_vddq_set(1);
++
++	val = efuse_readl(EFUSE_CTRL);
++	val |= EFUSE_CTRL_WREN;
++	efuse_writel(val, EFUSE_CTRL);
++
++	/* wait write done status */
++	while(!(efuse_readl(EFUSE_STATE) & EFUSE_STA_WR_DONE));
++
++	efuse_vddq_set(0);
++
++	efuse_writel(0, EFUSE_CTRL);
++	efuse_writel(EFUSE_CTRL_PD, EFUSE_CTRL);
++}
++
++static void rir_r(void)
++{
++	unsigned int val;
++
++	efuse_writel(0, EFUSE_CTRL);
++	efuse_writel(0, EFUSE_DATA(0));
++	efuse_writel(0, EFUSE_DATA(1));
++
++	/* set rir read address and data length */
++	val =  0x1f << EFUSE_CTRL_ADDR | 0x1 << EFUSE_CTRL_LEN;
++	efuse_writel(val, EFUSE_CTRL);
++
++	val = efuse_readl(EFUSE_CTRL);
++	val &= ~EFUSE_CTRL_PD;
++	efuse_writel(val, EFUSE_CTRL);
++
++	val = efuse_readl(EFUSE_CTRL);
++	val &= ~EFUSE_CTRL_PS;
++	efuse_writel(val, EFUSE_CTRL);
++
++	val = efuse_readl(EFUSE_CTRL);
++	val |= EFUSE_CTRL_RWL;
++	efuse_writel(val, EFUSE_CTRL);
++
++	val = efuse_readl(EFUSE_CTRL);
++	val |= EFUSE_CTRL_RDEN;
++	efuse_writel(val, EFUSE_CTRL);
++
++	/* wait read done status */
++	while(!(efuse_readl(EFUSE_STATE) & EFUSE_STA_RD_DONE));
++
++	efuse_writel(0, EFUSE_CTRL);
++	efuse_writel(EFUSE_CTRL_PD, EFUSE_CTRL);
++
++	dev_dbg(efuse->dev, "RIR0=0x%08x\n", efuse_readl(EFUSE_DATA(0)));
++	dev_dbg(efuse->dev, "RIR1=0x%08x\n", efuse_readl(EFUSE_DATA(1)));
++}
++
++static int rir_op(uint32_t value, uint32_t flag)
++{
++	unsigned int addr = 0, rf_addr = 0;
++	unsigned int fb_disable = 0;
++	unsigned int ret1, ret2;
++	int rir_num = 0;
++
++	if(value == 0)
++		return -1;
++
++	rir_r();
++	ret1 = efuse_readl(EFUSE_DATA(0));
++	ret2 = efuse_readl(EFUSE_DATA(1));
++
++	if((ret1 & 0xFFFF) && (ret1 & (0xFFFF << 16)) &&
++			(ret2 & 0xFFFF) && (ret2 & (0xFFFF << 16))) {
++		if(flag == 1) {
++			fb_disable = 0x1 << 31;
++			rf_addr = 0x20;
++			rir_w(rf_addr, fb_disable);
++		}
++		dev_err(efuse->dev, "not redundancy bits!\n");
++		return -1;
++	}
++
++	if(((ret1 & (0xFFFF)) && (ret1 & (0xFFFF << 16)))) {
++		addr = 0x20;
++		if(ret2 & 0xFFFF) {
++			value = value << 16;
++			rir_num = 4;
++		} else {
++			rir_num = 3;
++		}
++	} else {
++		addr = 0;
++		if(ret1 & 0xFFFF) {
++			value = value << 16;
++			rir_num = 2;
++		} else {
++			rir_num = 1;
++		}
++	}
++
++	if(flag == 1) {
++		switch(rir_num) {
++			case 2:
++				fb_disable = 0x1 << 15;
++				rf_addr = 0x0;
++				break;
++			case 3:
++				fb_disable = 0x1 << 31;
++				rf_addr = 0x0;
++				break;
++			case 4:
++				fb_disable = 0x1 << 15;
++				rf_addr = 0x20;
++				break;
++			default:
++				dev_err(efuse->dev, "not rir %d!\n", rir_num);
++				return -1;
++		}
++
++		rir_w(rf_addr, fb_disable);
++	}
++
++	rir_w(addr, value);
++
++	return 0;
++}
++
++static int rir_check(struct seg_info *info, uint32_t woffs, uint32_t val)
++{
++	unsigned int rval, errbits;
++
++	rir_r();
++	otp_r(info->word_address + woffs, 1);
++
++	rval = efuse_readl(EFUSE_DATA(0));
++	if(woffs == 0)
++		rval &= 0xffffffff << info->begin_align * 8;
++	else if(woffs == info->word_num - 1)
++		rval &= 0xffffffff >> info->end_align* 8;
++
++	dev_info(efuse->dev, "%08x ^ %08x\n", rval, val);
++	errbits = rval ^ val;
++
++	return errbits;
++}
++
++static int rir_repair(struct seg_info *info, uint32_t *buf)
++{
++	unsigned int errbits, rir_data, repair_result, repair_fail;
++	int ret, n, ebit;
++
++	for(n = 0; n < info->word_num; n++) {
++		errbits = rir_check(info, n, buf[n]);
++		dev_dbg(efuse->dev, "addr=%x, errbits=0x%08x\n", info->word_address + n, errbits);
++
++		while((ebit = ffs(errbits)) > 0) {
++			rir_data = 0x1 << EFUSE_RIR_RF;
++			rir_data |= (buf[n] & ebit) << EFUSE_RIR_DATA;
++			rir_data |= (info->word_address + n + ((ebit + info->begin_align * 8) << 6)) << EFUSE_RIR_ADDR;
++//			rir_data &= 0 << EFUSE_RIR_DISABLE;
++
++			ret = rir_op(rir_data, 0);
++			if(ret) {
++				dev_err(efuse->dev, "rir repair failed!\n");
++				return -1;
++			}
++
++			do {
++				repair_result = rir_check(info, n, buf[n]);
++				repair_fail = repair_result & (0x1 << ebit);
++				if(repair_fail) {
++					ret = rir_op(rir_data, 1);
++					if(ret) {
++						dev_err(efuse->dev, "rir repair failed!\n");
++						return -1;
++					}
++				}
++			} while(repair_fail);
++			errbits &= 0 << ebit;
++		}
++	}
++
++	return 0;
++}
++
++static void rir_disable_all(void)
++{
++	rir_r();
++	rir_w(0x0, (1 << 15));
++	rir_w(0x0, (1 << 31));
++	rir_w(0x20, (1 << 15));
++	rir_w(0x20, (1 << 31));
++}
++
++static int jz_efuse_read(struct seg_info *info, uint32_t *buf)
++{
++	uint32_t val;
++	uint32_t rbuf[8] = {0};
++	uint32_t hamming_buf[8] = {0};
++	uint32_t byte_num = 0;
++	uint32_t half_bit_num = 0;
++	uint32_t half_byte_num = 0;
++	uint32_t half_bit_align = 0;
++	uint32_t hamming_bit_num = 0;
++	int n, ret;
++
++	dev_dbg(efuse->dev,"segment name: %s\nsegment addr: 0x%02x\nbegin align: %d\nend align: %d\n"
++			"word num: %d\nbit num: %d\nverify mode: %d\n",
++			info->seg_name, info->word_address, info->begin_align, info->end_align,
++			info->word_num, info->bit_num, info->verify_mode);
++
++	rir_r();
++	otp_r(info->word_address, info->word_num);
++
++	dev_dbg(efuse->dev, "efuse read data:\n");
++	for(n = 0; n < info->word_num; n++) {
++		val = efuse_readl(EFUSE_DATA(n));
++		dev_dbg(efuse->dev, "%08x\n", val);
++		if(n == 0)
++			rbuf[n] = val & (0xffffffff << info->begin_align * 8);
++		if(n == info->word_num - 1)
++			rbuf[n] = val & (0xffffffff >> info->end_align * 8);
++		else
++			rbuf[n] = val;
++	}
++
++	byte_num = info->bit_num / 8;
++	byte_num += info->bit_num % 8 ? 1 : 0;
++
++	switch(info->verify_mode) {
++		case HAMMING:
++			hamming_bit_num = info->bit_num + cal_k(info->bit_num);
++//			dump(rbuf, 0, hamming_bit_num);
++			decode((unsigned int *)((char *)rbuf + info->begin_align),
++					hamming_bit_num, hamming_buf);
++			memcpy((char *)buf, (char *)hamming_buf, byte_num);
++			break;
++		case DOUBLE:
++			half_bit_num = info->bit_num / 2;
++			half_byte_num = half_bit_num / 8;
++			half_bit_align = half_bit_num % 8;
++//			dump((unsigned int *)((char *)rbuf + info->begin_align), 0, half_bit_num);
++//			dump((unsigned int *)((char *)rbuf + info->begin_align + half_byte_num), half_bit_align, half_bit_num + half_bit_align);
++			ret = checkbit((unsigned int *)((char *)rbuf + info->begin_align),
++					(unsigned int *)((char *)rbuf + info->begin_align + half_byte_num),
++					0, half_bit_align, half_bit_num);
++			if(ret){
++				dev_err(efuse->dev, "double verify failed!\n");
++				return -1;
++			}
++			memcpy((char *)buf, ((char *)rbuf + info->begin_align), byte_num);
++			break;
++		case NONE:
++		default:
++			memcpy((char *)buf, ((char *)rbuf + info->begin_align), byte_num);
++			break;
++	}
++
++	/* clear read done status */
++	efuse_writel(0, EFUSE_STATE);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(jz_efuse_read);
++
++
++static void otp_w(uint32_t addr, uint32_t wlen)
++{
++	unsigned int val;
++
++	efuse_writel(0, EFUSE_CTRL);
++
++	/* set write Programming address and data length */
++	val =  addr << EFUSE_CTRL_ADDR | (wlen - 1) << EFUSE_CTRL_LEN;
++	efuse_writel(val, EFUSE_CTRL);
++
++	val = efuse_readl(EFUSE_CTRL);
++	val &= ~EFUSE_CTRL_PD;
++	efuse_writel(val, EFUSE_CTRL);
++
++	val = efuse_readl(EFUSE_CTRL);
++	val |= EFUSE_CTRL_PS;
++	efuse_writel(val, EFUSE_CTRL);
++
++	/* Programming EFUSE enable */
++	val = efuse_readl(EFUSE_CTRL);
++	val |= EFUSE_CTRL_PGEN;
++	efuse_writel(val, EFUSE_CTRL);
++
++	/* Connect VDDQ pin from 1.8V */
++	efuse_vddq_set(1);
++
++	/* enable write */
++	val = efuse_readl(EFUSE_CTRL);
++	val |= EFUSE_CTRL_WREN;
++	efuse_writel(val, EFUSE_CTRL);
++
++	/* wait write done status */
++	while(!(efuse_readl(EFUSE_STATE) & EFUSE_STA_WR_DONE));
++
++	/* Disconnect VDDQ pin from 1.8V. */
++	efuse_vddq_set(0);
++
++	efuse_writel(0, EFUSE_CTRL);
++	efuse_writel(EFUSE_CTRL_PD, EFUSE_CTRL);
++}
++
++static int jz_efuse_write(struct seg_info *info, uint32_t *buf)
++{
++	unsigned int val[8] = {0};
++	unsigned char *pbuf = (unsigned char *)val;
++	unsigned char *sbuf = (unsigned char *)buf;
++	uint32_t regval = 0;
++	uint32_t byte_num = 0;
++	uint32_t half_bit_num = 0;
++	uint32_t half_byte_num = 0;
++	uint32_t half_bit_align = 0;
++	uint32_t hamming_bit_num = 0;
++	int ret = 0;
++	int n = 0;
++
++
++	dev_dbg(efuse->dev,"segment name: %s\nsegment addr: 0x%02x\nbegin align: %d\nend align: %d\n"
++			"word num: %d\nbit num: %d\nverify mode: %d\n",
++			info->seg_name, info->word_address, info->begin_align, info->end_align,
++			info->word_num, info->bit_num, info->verify_mode);
++
++	if(info->seg_id != PRT) {
++		regval = efuse_readl(EFUSE_STATE);
++		if(info->prt_bit & regval) {
++			dev_err(efuse->dev, "segment[%s] has been protected!\n", info->seg_name);
++			return -1;
++		}
++	}
++
++	byte_num = info->bit_num / 8;
++	byte_num += info->bit_num % 8 ? 1 : 0;
++
++	switch(info->verify_mode) {
++		case HAMMING:
++			hamming_bit_num = info->bit_num + cal_k(info->bit_num);
++//			dumphex(buf, info->word_num);
++			encode(buf, info->bit_num, (unsigned int *)(pbuf + info->begin_align));
++//			dump((unsigned int *)pbuf, 0, hamming_bit_num + info->begin_align * 8);
++//			dumphex((unsigned int *)(pbuf + info->begin_align), info->word_num);
++			break;
++		case DOUBLE:
++			half_bit_num = info->bit_num / 2;
++			half_byte_num = half_bit_num / 8;
++			half_bit_align = half_bit_num % 8;
++			dump(buf, 0, half_bit_num);
++			dump((unsigned int *)(sbuf + half_byte_num), half_bit_align, half_bit_num + half_bit_align);
++			ret = checkbit(buf,(unsigned int *)(sbuf + half_byte_num), 0, half_bit_align, half_bit_num);
++			if(ret){
++				dev_err(efuse->dev, "double verify failed!\n");
++				return -1;
++			}
++			memcpy(pbuf + info->begin_align, (char *)buf, byte_num);
++			break;
++		case NONE:
++		default:
++			memcpy(pbuf + info->begin_align, (char *)buf, byte_num);
++			break;
++	}
++
++	dev_dbg(efuse->dev, "efuse write data:\n");
++	for(n = 0; n < info->word_num; n++) {
++		dev_dbg(efuse->dev,"%08x\n", val[n]);
++		efuse_writel(val[n], EFUSE_DATA(n));
++	}
++
++	otp_w(info->word_address, info->word_num);
++
++	if(info->verify_mode == HAMMING) {
++		ret = rir_repair(info, val);
++		if(ret < 0){
++			dev_err(efuse->dev, "hamming verify failed!\n");
++			return -1;
++		}
++	}
++
++	return 0;
++}
++
++
++static long efuse_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
++{
++	struct miscdevice *dev = filp->private_data;
++	struct jz_efuse *efuse = container_of(dev, struct jz_efuse, mdev);
++	int ret = 0;
++
++
++	mutex_lock(&efuse->lock);
++	efuse->wr_info = (struct efuse_wr_info *)arg;
++
++	if(efuse->wr_info->seg_id > ARRAY_SIZE(seg_info_array)) {
++		dev_err(efuse->dev, "unknow segment id!\n");
++		goto exit;
++	}
++
++
++	info = seg_info_array[efuse->wr_info->seg_id];
++	switch (cmd) {
++		case CMD_READ:
++			ret = jz_efuse_read(&info, efuse->wr_info->data);
++			break;
++		case CMD_WRITE:
++			ret = jz_efuse_write(&info, efuse->wr_info->data);
++			break;
++		default:
++			dev_err(efuse->dev, "unknow cmd!\n");
++			break;
++	}
++exit:
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static struct file_operations efuse_misc_fops = {
++	.open		= efuse_open,
++	.release	= efuse_release,
++	.unlocked_ioctl	= efuse_ioctl,
++};
++
++
++static int set_efuse_timing(struct device *dev)
++{
++	struct clk *h2clk;
++	struct clk *devclk;
++	unsigned long rate;
++	uint32_t val, ns;
++	int i, rd_strobe, wr_strobe;
++	uint32_t rd_adj, wr_adj;
++	int flag = 0;
++
++	h2clk = devm_clk_get(dev, "div_ahb2");
++	if (IS_ERR(h2clk)) {
++		dev_err(efuse->dev, "get h2clk rate fail!\n");
++		return -1;
++	}
++
++	devclk = devm_clk_get(dev, "gate_efuse");
++	if (IS_ERR(devclk)) {
++		dev_err(efuse->dev, "get efuse clk rate fail!\n");
++		return -1;
++	}
++	clk_prepare_enable(devclk);
++
++	rate = clk_get_rate(h2clk);
++	ns = 1000000000 / rate;
++	printk("rate = %lu, ns = %d\n", rate, ns);
++
++
++	for(i = 0; i < 0x4; i++)
++		if((( i + 1) * ns ) > 2)
++			break;
++	if(i == 0x4) {
++		dev_err(efuse->dev, "get efuse cfg rd_adj fail!\n");
++		return -1;
++	}
++	rd_adj = wr_adj = i;
++
++	for(i = 0; i < 0x8; i++)
++		if(((rd_adj + i + 30) * ns ) > 100)
++			break;
++	if(i == 0x8) {
++		dev_err(efuse->dev, "get efuse cfg rd_strobe fail!\n");
++		return -1;
++	}
++	rd_strobe = i;
++
++	for(i = 0; i < 0x3ff; i++) {
++		val = (wr_adj + i + 3000) * ns;
++		if(val > 13 * 1000) {
++			val = (wr_adj - i + 3000) * ns;
++			flag = 1;
++		}
++		if(val > 11 * 1000 && val < 13 * 1000)
++			break;
++	}
++	if(i >= 0x3ff) {
++		dev_err(efuse->dev, "get efuse cfg wd_strobe fail!\n");
++		return -1;
++	}
++
++	if(flag)
++		i |= 1 << 10;
++
++	wr_strobe = i;
++
++	dev_info(efuse->dev, "rd_adj = %d | rd_strobe = %d | "
++		 "wr_adj = %d | wr_strobe = %d\n", rd_adj, rd_strobe,
++		 wr_adj, wr_strobe);
++
++	/*set configer register*/
++	val = rd_adj << EFUSE_CFG_RD_ADJ | rd_strobe << EFUSE_CFG_RD_STROBE;
++	val |= wr_adj << EFUSE_CFG_WR_ADJ | wr_strobe;
++	efuse_writel(val, EFUSE_CFG);
++
++	clk_put(h2clk);
++
++	return 0;
++}
++
++int jz_efuse_read_chipd(uint32_t *chipid){
++	int ret = 0,i;
++	uint32_t val[8] = {0};
++
++	mutex_init(&efuse->lock);
++	info = seg_info_array[CHIPID];
++    for(i = (info.bit_num / 8/4 -1); i >=0 ; i--){
++        chipid[(info.bit_num / 8/4 -1) - i] = val[i];
++    }
++    printk("chipid :%08X %08X %08X %08X\n",chipid[3],chipid[2],chipid[1],chipid[0]);
++    ret = info.bit_num / 8/4;
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++EXPORT_SYMBOL(jz_efuse_read_chipd);
++
++static int show_segment(uint32_t seg_id,  char *buf)
++{
++	int ret = 0;
++	int i = 0;
++	uint32_t val[8] = {0};
++    char *ptr;
++	char *last = NULL;
++	info = seg_info_array[seg_id];
++	last = (char *)val + info.bit_num / 8 - 1;
++
++	jz_efuse_read(&info, val);
++    if(seg_id == CHIPID){
++        ptr = buf;
++        *ptr=0;
++        for(i = (info.bit_num / 8/4 -1); i >=0 ; i--) {
++            sprintf(ptr,"%08x", val[i]);
++            if(i>0){
++                strcat(buf, " ");
++                ptr = buf + strlen(buf);
++            }
++        }
++        strcat(buf, "\n");
++        ret = strlen(buf);
++        printk("chipid :%s\n",buf);
++    }else {
++        for(i = 0; i < info.bit_num / 8; i++)
++            ret += snprintf(buf + (i * 2), 3, "%02x", *((uint8_t *)last - i));
++        strcat(buf, "\n");
++    }
++
++	return ret + 1;
++}
++
++static ssize_t chipid_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(CHIPID, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static ssize_t custid0_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(CUSTID0, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static ssize_t custid1_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(CUSTID1, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static ssize_t custid2_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(CUSTID2, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static ssize_t trim0_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(TRIM0, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static ssize_t trim1_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(TRIM1, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static ssize_t trim2_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(TRIM2, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static ssize_t socinfo_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(SOCINFO, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static ssize_t prt_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(PRT, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static ssize_t hideblk_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	int ret = 0;
++	mutex_init(&efuse->lock);
++	ret = show_segment(HIDEBLK, buf);
++	mutex_unlock(&efuse->lock);
++	return ret;
++}
++
++static void store_segment(uint32_t seg_id, const char *buf, int len)
++{
++	int i = 0;
++	uint32_t val[8] = {0};
++	uint32_t tmpval = 0;
++	char tmp[9] = {'\0'};
++	char *last = (char *)buf + (len - 1);
++	int bit_num = (len - 1) * 4;
++	int word_num =(len - 1) / 8;
++	int remain_num = (len - 1) % 8;
++	info = seg_info_array[seg_id];
++
++	if (bit_num == info.bit_num) {
++		for (i = 0; i < word_num; i++) {
++			memcpy(tmp, last - ((i + 1) * 8), 8);
++			sscanf(tmp, "%08x", &val[i]);
++			printk("%08x\n", val[i]);
++
++		}
++
++		if (remain_num > 0)  {
++			memcpy(tmp, buf, remain_num);
++			sscanf(tmp, "%08x", &tmpval);
++			tmpval &= (0xffffffff << (8 - remain_num) * 4);
++			tmpval >>= ((8 - remain_num) * 4);
++			val[word_num] = tmpval;
++			printk("%08x\n", val[word_num]);
++
++		}
++		jz_efuse_write(&info, val);
++	} else {
++		printk("%s segment size is %d bits!\n", info.seg_name, info.bit_num);
++	}
++}
++
++static ssize_t chipid_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(CHIPID, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++static ssize_t custid0_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(CUSTID0, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++static ssize_t custid1_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(CUSTID1, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++static ssize_t custid2_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(CUSTID2, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++static ssize_t trim0_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(TRIM0, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++static ssize_t trim1_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(TRIM1, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++static ssize_t trim2_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(TRIM2, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++static ssize_t socinfo_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(SOCINFO, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++static ssize_t prt_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(PRT, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++static ssize_t hideblk_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	mutex_init(&efuse->lock);
++	store_segment(HIDEBLK, buf, n);
++	mutex_unlock(&efuse->lock);
++	return n;
++}
++
++
++static DEVICE_ATTR(chipid,  S_IRUGO|S_IWUSR, chipid_show,  chipid_store);
++static DEVICE_ATTR(custid0, S_IRUGO|S_IWUSR, custid0_show, custid0_store);
++static DEVICE_ATTR(custid1, S_IRUGO|S_IWUSR, custid1_show, custid1_store);
++static DEVICE_ATTR(custid2, S_IRUGO|S_IWUSR, custid2_show, custid2_store);
++static DEVICE_ATTR(trim0,   S_IRUGO|S_IWUSR, trim0_show,   trim0_store);
++static DEVICE_ATTR(trim1,   S_IRUGO|S_IWUSR, trim1_show,   trim1_store);
++static DEVICE_ATTR(trim2,   S_IRUGO|S_IWUSR, trim2_show,   trim2_store);
++static DEVICE_ATTR(socinfo, S_IRUGO|S_IWUSR, socinfo_show, socinfo_store);
++static DEVICE_ATTR(prt,     S_IRUGO|S_IWUSR, prt_show,     prt_store);
++static DEVICE_ATTR(hideblk, S_IRUGO|S_IWUSR, hideblk_show, hideblk_store);
++static DEVICE_ATTR(chipkey, S_IRUGO|S_IWUSR, NULL, NULL);
++static DEVICE_ATTR(userkey0,S_IRUGO|S_IWUSR, NULL, NULL);
++static DEVICE_ATTR(userkey1,S_IRUGO|S_IWUSR, NULL, NULL);
++static DEVICE_ATTR(nku,     S_IRUGO|S_IWUSR, NULL, NULL);
++
++static struct attribute *efuse_rw_attrs[] = {
++	&dev_attr_chipid.attr,
++	&dev_attr_custid0.attr,
++	&dev_attr_custid1.attr,
++	&dev_attr_custid2.attr,
++	&dev_attr_trim0.attr,
++	&dev_attr_trim1.attr,
++	&dev_attr_trim2.attr,
++	&dev_attr_socinfo.attr,
++	&dev_attr_prt.attr,
++	&dev_attr_hideblk.attr,
++	&dev_attr_chipkey.attr,
++	&dev_attr_userkey0.attr,
++	&dev_attr_userkey1.attr,
++	&dev_attr_nku.attr,
++	NULL,
++};
++
++const char efuse_group_name[] = "efuse_rw";
++static struct attribute_group efuse_rw_attr_group = {
++	.name   = efuse_group_name,
++	.attrs  = efuse_rw_attrs,
++};
++
++
++#ifdef CONFIG_INGENIC_EFUSE_WRITABLE
++static int of_avd_efuse(struct device *dev)
++{
++	struct jz_efuse *efuse = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++#if 1
++	efuse->avd_efuse_en.gpio = of_get_named_gpio_flags(np, "ingenic,efuse-en-gpio", 0, &flags);
++	if(!gpio_is_valid(efuse->avd_efuse_en.gpio)) {
++		ret = efuse->avd_efuse_en.gpio;
++		dev_err(dev, "efuse_en gpio invalid! %d\n", ret);
++		return ret;
++	}
++
++	ret = devm_gpio_request(dev, efuse->avd_efuse_en.gpio, "efuse-en");
++	if(ret < 0) {
++		dev_err(dev, "efuse_en gpio request failed! %d\n", ret);
++		return ret;
++	}
++	efuse->avd_efuse_en.level = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++#else
++	efuse->pmu_efuse_en = regulator_get(NULL, "LDO2_1V8");
++	if(!efuse->pmu_efuse_en) {
++		dev_err(dev, "get efuse regulator failed\n");
++		return -1;
++	}
++#endif
++	return 0;
++}
++#endif
++
++static int jz_efuse_probe(struct platform_device *pdev)
++{
++	struct resource *res = NULL;
++	int ret = 0;
++
++	efuse = devm_kzalloc(&pdev->dev, sizeof(struct jz_efuse), GFP_KERNEL);
++	if (!efuse) {
++		printk("efuse malloc failed!\n");
++		return -ENOMEM;
++	}
++
++	mutex_init(&efuse->lock);
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (IS_ERR_OR_NULL(res)) {
++		dev_err(&pdev->dev, "get efuse resource failed!\n");
++		ret = -ENXIO;
++		goto err_free_efuse;
++	}
++
++	efuse->iomem = devm_ioremap(&pdev->dev, res->start, resource_size(res));
++	if (IS_ERR_OR_NULL(efuse->iomem)) {
++		dev_err(&pdev->dev, "efuse ioremap failed!\n");
++		ret = -EBUSY;
++		goto err_free_efuse;
++	}
++
++	efuse->dev = &pdev->dev;
++	efuse->wr_info = NULL;
++	efuse->mdev.minor = MISC_DYNAMIC_MINOR;
++	efuse->mdev.name =  DRV_NAME;
++	efuse->mdev.fops = &efuse_misc_fops;
++
++	ret = misc_register(&efuse->mdev);
++	if (ret < 0) {
++		dev_err(efuse->dev, "efuse misc_register failed\n");
++		ret = -EINVAL;
++		goto err_free_efuse_io;
++	}
++	platform_set_drvdata(pdev, efuse);
++
++#ifdef CONFIG_INGENIC_EFUSE_WRITABLE
++	dev_info(efuse->dev, "setup vddq_protect_timer!\n");
++	setup_timer(&efuse->vddq_protect_timer, efuse_vddq_set, 0);
++	add_timer(&efuse->vddq_protect_timer);
++
++	ret = of_avd_efuse(efuse->dev);
++	if (ret < 0) {
++		goto err_free_efuse_io;
++	}
++#endif
++	ret = set_efuse_timing(efuse->dev);
++	if(ret) {
++		dev_err(efuse->dev, "efuse timing setting failed!\n");
++		ret = -EINVAL;
++		goto err_free_efuse_io;
++	}
++
++	ret = sysfs_create_group(&pdev->dev.kobj, &efuse_rw_attr_group);
++	if (ret) {
++		dev_err(efuse->dev, "device create sysfs group failed\n");
++		ret = -EINVAL;
++		goto err_free_efuse_io;
++	}
++
++
++	dev_info(efuse->dev, "efuse probe success.\n");
++	return 0;
++
++
++err_free_efuse_io:
++	iounmap(efuse->iomem);
++err_free_efuse:
++	kfree(efuse);
++
++	return ret;
++}
++
++
++static int jz_efuse_remove(struct platform_device *dev)
++{
++	struct jz_efuse *efuse = platform_get_drvdata(dev);
++
++	misc_deregister(&efuse->mdev);
++#ifdef CONFIG_INGENIC_EFUSE_WRITABLE
++	dev_info(efuse->dev, "del vddq_protect_timer!\n");
++	del_timer(&efuse->vddq_protect_timer);
++#endif
++	iounmap(efuse->iomem);
++	kfree(efuse);
++
++	return 0;
++}
++
++static const struct of_device_id efuse_of_match[] = {
++	{ .compatible = "ingenic,x2000-efuse"},
++	{ .compatible = "ingenic,m300-efuse"},
++	{},
++};
++
++static struct platform_driver jz_efuse_driver = {
++	.driver = {
++		.name = DRV_NAME,
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(efuse_of_match),
++	},
++	.probe		= jz_efuse_probe,
++	.remove		= jz_efuse_remove,
++};
++
++static int __init jz_efuse_init(void)
++{
++	return platform_driver_register(&jz_efuse_driver);
++}
++
++static void __exit jz_efuse_exit(void)
++{
++	platform_driver_unregister(&jz_efuse_driver);
++}
++
++
++module_init(jz_efuse_init);
++module_exit(jz_efuse_exit);
++
++MODULE_DESCRIPTION("X2000_v12 efuse driver");
++MODULE_AUTHOR("cjwang <chongji.wang@ingenic.com>");
++MODULE_LICENSE("GPL v2");
++MODULE_VERSION("20200312");
+diff --git a/module_drivers/drivers/misc/ingenic_rsa.c b/module_drivers/drivers/misc/ingenic_rsa.c
+new file mode 100644
+index 000000000..c9d6ac7c8
+--- /dev/null
++++ b/module_drivers/drivers/misc/ingenic_rsa.c
+@@ -0,0 +1,487 @@
++/*
++ * drivers/misc/ingenic_rsa.c - Ingenic rsa driver
++ *
++ * Copyright (C) 2012 Ingenic Semiconductor Co., Ltd.
++ * Author: mayuanjun <yuanjun.ma@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/miscdevice.h>
++#include <linux/fs.h>
++#include <linux/interrupt.h>
++#include <linux/spinlock.h>
++#include <linux/dma-mapping.h>
++#include <linux/wait.h>
++#include <linux/sched.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++
++#define MAX_KEY_LEN_WORD 64
++#define DEV_NAME  "rsa"
++
++#define MCU_BOOT_DDR 0xb3422000
++
++#define DRV_NAME "jz-rsa"
++#define MAX_KEY_LEN_WORD 64
++
++struct jz_rsa {
++    struct miscdevice mdev;
++    struct device *dev;
++
++    struct clk		*clk_gate;
++    void __iomem *iomem;
++    unsigned int irq;
++
++    bool busy;
++
++    struct mutex mutex;
++
++    wait_queue_head_t wq;
++
++    unsigned int n_len;
++    unsigned int per_done;
++    unsigned int rsa_done;
++};
++
++struct rsa_key {
++    unsigned int *e;
++    unsigned int *n;
++    unsigned int rsa_mode;
++};
++
++struct rsa_data {
++    unsigned int *input;
++    unsigned int inlen;
++    unsigned int *output;
++};
++
++#define RSA_PERPARE_KEY	0x1
++#define RSA_DO_CRYPT	0x2
++
++#define RSAC		0x0
++#define RSAE		0x4
++#define RSAN		0x8
++#define RSAM		0xc
++#define RSAP		0x10
++
++#define RSAC_RSA_INT_M	(1 << 17)
++#define RSAC_PER_INT_M	(1 << 16)
++#define RSAC_RSA_2048	(1 << 7)
++#define RSAC_RSAC	(1 << 6)
++#define RSAC_RSAD	(1 << 5)
++#define RSAC_RSAS	(1 << 4)
++#define RSAC_PERC	(1 << 3)
++#define RSAC_PERD	(1 << 2)
++#define RSAC_PERS	(1 << 1)
++#define RSAC_EN		(1 << 0)
++
++#define mcu_boot()	\
++	do {			\
++	*(volatile unsigned int *)0xb3421030 &= ~1; \
++	} while(0)
++
++#define mcu_reset()		\
++	do {			\
++	*(volatile unsigned int *)0xb3421030 |= 1; \
++	} while(0)
++
++static int inline rsa_readl(struct jz_rsa *rsa, unsigned int offset)
++{
++    return readl(rsa->iomem + offset);
++}
++
++static void inline rsa_writel(struct jz_rsa *rsa, unsigned int offset, unsigned int val)
++{
++    writel(val, rsa->iomem + offset);
++}
++
++static int rsa_perpare_key(struct jz_rsa *rsa, struct rsa_key *rsa_key)
++{
++    unsigned int n[MAX_KEY_LEN_WORD];
++    unsigned int e[MAX_KEY_LEN_WORD];
++    unsigned int keylen = rsa_key->rsa_mode/32;
++
++    unsigned int tmp;
++    unsigned int i;
++    int ret = 0;
++
++    mutex_lock(&rsa->mutex);
++
++    rsa->per_done = 0;
++    rsa->n_len = keylen;
++
++    if(copy_from_user(e, rsa_key->e, keylen * 4)) {
++        dev_err(rsa->dev, "Failed to copy rsa_key->e form user!\n");
++        ret = -EFAULT;
++        goto err;
++    }
++    if(copy_from_user(n, rsa_key->n, keylen * 4)) {
++        dev_err(rsa->dev, "Failed to copy rsa_key->n form user!\n");
++        ret = -EFAULT;
++        goto err;
++    }
++
++    tmp = rsa_readl(rsa, RSAC);
++    if(rsa_key->rsa_mode == 2048)
++        tmp |= RSAC_RSA_2048;
++    else if (rsa_key->rsa_mode == 1024)
++        tmp &= ~RSAC_RSA_2048;
++    tmp &= ~RSAC_PER_INT_M;
++    rsa_writel(rsa, RSAC, tmp);
++
++    for(i = 0; i < keylen; i++) {
++        rsa_writel(rsa, RSAE, e[i]);
++    }
++    for(i = 0; i < keylen; i++){
++        rsa_writel(rsa, RSAN, n[i]);
++    }
++    rsa_writel(rsa, RSAC, RSAC_PERS | rsa_readl(rsa, RSAC));
++
++    ret = wait_event_interruptible(rsa->wq, rsa->per_done == 1);
++    if(ret < 0) {
++        dev_err(rsa->dev, "key perpare can't wait irq\n");
++        ret = -EFAULT;
++        goto err;
++    }
++
++    rsa_writel(rsa, RSAC, RSAC_PERC | rsa_readl(rsa, RSAC));
++    rsa_writel(rsa, RSAC, ~RSAC_PERC & rsa_readl(rsa, RSAC));
++
++    mutex_unlock(&rsa->mutex);
++    return 0;
++
++err:
++    mutex_unlock(&rsa->mutex);
++    return ret;
++}
++
++static int rsa_do_crypt(struct jz_rsa *rsa, struct rsa_data *rsa_data)
++{
++    unsigned int input[MAX_KEY_LEN_WORD];
++    unsigned int output[MAX_KEY_LEN_WORD];
++    unsigned int *id = rsa_data->input;
++    unsigned int *od = rsa_data->output;
++    unsigned int keylen = rsa->n_len;
++    unsigned int len = rsa_data->inlen;
++
++    unsigned int i;
++    int ret = 0;
++
++    mutex_lock(&rsa->mutex);
++
++    if(len % keylen) {
++        pr_err("Data len err \n");
++        ret = -EINVAL;
++        goto err;
++    }
++
++    while(len > 0) {
++
++        rsa->rsa_done = 0;
++
++        if(copy_from_user(input, id, keylen * 4)) {
++            dev_err(rsa->dev, "Failed to copy rsa_data->input form user!\n");
++            ret = -EFAULT;
++            goto err;
++        }
++
++        for(i = 0; i < keylen; i++) {
++            rsa_writel(rsa, RSAM, input[i]);
++        }
++
++        rsa_writel(rsa, RSAC, ~RSAC_RSA_INT_M & rsa_readl(rsa, RSAC));
++        rsa_writel(rsa, RSAC, RSAC_RSAS | rsa_readl(rsa, RSAC));
++
++        ret = wait_event_interruptible(rsa->wq, rsa->rsa_done == 1);
++        if(ret < 0) {
++            dev_err(rsa->dev, "rsa crypt can't wait irq\n");
++            ret = -EFAULT;
++            goto err;
++        }
++
++        for(i = 0; i < keylen; i++) {
++            output[keylen -1 - i] = rsa_readl(rsa, RSAP);
++        }
++
++        rsa_writel(rsa, RSAC, rsa_readl(rsa, RSAC) | RSAC_RSAC);
++        rsa_writel(rsa, RSAC, rsa_readl(rsa, RSAC) & ~RSAC_RSAC);
++
++        if(copy_to_user(od, output, keylen * 4)) {
++            dev_err(rsa->dev, "Failed to copy rsa_data->input form user!\n");
++            ret = -EFAULT;
++            goto err;
++        }
++
++        len -= keylen;
++        id += keylen;
++        od += keylen;
++
++    }
++
++    mutex_unlock(&rsa->mutex);
++    return 0;
++
++err:
++    mutex_unlock(&rsa->mutex);
++    return ret;
++
++}
++
++static int rsa_open(struct inode *inode, struct file *flip)
++{
++    struct miscdevice *mdev = flip->private_data;
++    struct jz_rsa *rsa = container_of(mdev, struct jz_rsa, mdev);
++    int tmp;
++
++    mutex_lock(&rsa->mutex);
++    if(rsa->busy) {
++        dev_err(rsa->dev, "Device is busy!\n");
++        mutex_unlock(&rsa->mutex);
++        return -EBUSY;
++    }
++
++    rsa->busy = 1;
++
++    rsa_writel(rsa, RSAC, RSAC_EN | rsa_readl(rsa, RSAC));
++
++    mutex_unlock(&rsa->mutex);
++
++    return 0;
++}
++
++static int rsa_release(struct inode *inode, struct file *flip)
++{
++    struct miscdevice *mdev = flip->private_data;
++    struct jz_rsa *rsa = container_of(mdev, struct jz_rsa, mdev);
++
++    mutex_lock(&rsa->mutex);
++
++    rsa->busy = 0;
++
++    rsa_writel(rsa, RSAC, ~RSAC_EN & rsa_readl(rsa, RSAC));
++
++    mutex_unlock(&rsa->mutex);
++
++    return 0;
++}
++
++static long rsa_ioctl(struct file *flip, unsigned int cmd, unsigned long args)
++{
++    struct miscdevice *mdev = flip->private_data;
++    struct jz_rsa *rsa = container_of(mdev, struct jz_rsa, mdev);
++    struct rsa_key rsa_key;
++    struct rsa_data rsa_data;
++    int ret = 0;
++
++    switch (cmd) {
++        case RSA_PERPARE_KEY:
++
++            if(copy_from_user(&rsa_key, (void *)args, sizeof(struct rsa_key))) {
++                dev_err(rsa->dev, "Failed to copy rsa_key form user!\n");
++                ret = -EFAULT;
++                goto err;
++            }
++
++            ret = rsa_perpare_key(rsa, &rsa_key);
++
++            break;
++        case RSA_DO_CRYPT:
++            if(rsa->n_len != 32 && rsa->n_len != 64) {
++                dev_err(rsa->dev, "RSA key len err!\n");
++                ret = -EINVAL;
++                goto err;
++            }
++            if(copy_from_user(&rsa_data, (void *)args, sizeof(struct rsa_data))) {
++                dev_err(rsa->dev, "Could not copy data from user!\n");
++                ret = -EFAULT;
++                goto err;
++            }
++
++            ret = rsa_do_crypt(rsa, &rsa_data);
++            if(ret < 0) {
++                dev_err(rsa->dev, "Failed to crypt data!\n");
++                goto err;
++            }
++
++            break;
++        default:
++            dev_err(rsa->dev, "Unsupport IO cmd: %x\n", cmd);
++
++    }
++
++    return 0;
++err:
++    return ret;
++}
++
++static struct file_operations rsa_misc_fops = {
++    .owner = THIS_MODULE,
++    .open = rsa_open,
++    .release = rsa_release,
++    .unlocked_ioctl = rsa_ioctl,
++};
++
++static irqreturn_t rsa_irq(int irq, void *data)
++{
++    struct jz_rsa *rsa = (struct jz_rsa *)data;
++
++    if (rsa_readl(rsa, RSAC) & RSAC_RSAD) {
++        rsa_writel(rsa, RSAC, ~RSAC_RSAS & rsa_readl(rsa, RSAC));
++        rsa_writel(rsa, RSAC, RSAC_RSA_INT_M | rsa_readl(rsa, RSAC));
++        rsa->rsa_done = 1;
++    } else if (rsa_readl(rsa, RSAC) & RSAC_PERD) {
++        rsa_writel(rsa, RSAC, ~RSAC_PERS & rsa_readl(rsa, RSAC));
++        rsa_writel(rsa, RSAC, RSAC_PER_INT_M | rsa_readl(rsa, RSAC));
++        rsa->per_done = 1;
++    }
++
++    wake_up(&rsa->wq);
++
++    return IRQ_HANDLED;
++}
++
++#define cpm_readl(o)         (*(volatile unsigned int *)(o))
++#define cpm_writel(b, o)    (*(volatile unsigned int *)(o)) = (b)
++#ifdef CONFIG_SOC_X2500
++#define CPM_RSACDR      (0xb000004C)
++#else
++#define CPM_RSACDR      (0xb0000050)
++#endif
++#define CPM_CLKGR0      (0xb0000020)
++static int jz_rsa_probe(struct platform_device * pdev)
++{
++    int ret = 0;
++    struct jz_rsa *rsa;
++    struct resource *res;
++    unsigned int tmp;
++
++    rsa = kzalloc(sizeof(struct jz_rsa), GFP_KERNEL);
++    if(IS_ERR_OR_NULL(rsa)) {
++        pr_err("Failed to alloc mem fir jz_rsa!\n");
++        ret = -ENOMEM;
++        goto err;
++    }
++
++    rsa->dev = &pdev->dev;
++
++    rsa->clk_gate = devm_clk_get(&pdev->dev, "gate_rsa");
++    if (IS_ERR(rsa->clk_gate)) {
++        dev_err(&pdev->dev, "cannot find rsa clock\n");
++        ret = PTR_ERR(rsa->clk_gate);
++        goto err1;
++    }
++    clk_prepare_enable(rsa->clk_gate);
++
++    /* rsa cguclk SACLK/2 */
++    tmp = cpm_readl(CPM_RSACDR);
++    tmp &= ~(2<<30 | 0xf | 1 << 27);
++    tmp |= 1 << 29;
++    tmp |= 2 << 0;
++
++    cpm_writel(tmp, CPM_RSACDR);
++    while(cpm_readl(CPM_RSACDR) & (1<<28));
++    tmp &= ~(1<<29);
++    cpm_writel(tmp, CPM_RSACDR);
++    cpm_writel(0, CPM_CLKGR0);
++
++    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++    if(IS_ERR_OR_NULL(res)) {
++        dev_err(rsa->dev, "No iomem resource!\n");
++        ret = -ENOMEM;
++        goto err1;
++    }
++
++    rsa->irq = platform_get_irq(pdev, 0);
++    if(rsa->irq < 0) {
++        dev_err(&pdev->dev, "No irq resource!\n");
++        ret = -ENOMEM;
++        goto err1;
++    }
++
++    rsa->iomem = devm_ioremap(rsa->dev, res->start, resource_size(res));
++    if(IS_ERR_OR_NULL(rsa->iomem)) {
++        dev_err(&pdev->dev, "Failed to remap io resources!\n");
++        ret = -ENOMEM;
++        goto err1;
++    }
++
++    ret = devm_request_irq(&pdev->dev, rsa->irq, rsa_irq, IRQF_ONESHOT, dev_name(&pdev->dev), rsa);
++    if(ret < 0) {
++        dev_err(&pdev->dev, "Failed to request irq!\n");
++        goto err_request_irq;
++    }
++
++    init_waitqueue_head(&rsa->wq);
++
++    platform_set_drvdata(pdev, rsa);
++
++    mutex_init(&rsa->mutex);
++
++    rsa->mdev.minor = MISC_DYNAMIC_MINOR;
++    rsa->mdev.name = DEV_NAME;
++    rsa->mdev.fops = &rsa_misc_fops;
++    ret = misc_register(&rsa->mdev);
++    if(ret < 0) {
++        dev_err(&pdev->dev, "Failed to register misc driver!\n");
++        goto err_misc_register;
++    }
++
++    dev_info(&pdev->dev, "rsa driver probe ok!\n");
++
++    return 0;
++
++err_misc_register:
++    mutex_destroy(&rsa->mutex);
++err_request_irq:
++    devm_iounmap(rsa->dev, rsa->iomem);
++err1:
++    kfree(rsa);
++err:
++    dev_err(rsa->dev, "initialization failed.\n");
++    return ret;
++
++}
++
++static int jz_rsa_remove(struct platform_device *pdev)
++{
++    struct jz_rsa *rsa = platform_get_drvdata(pdev);
++
++    misc_deregister(&rsa->mdev);
++    devm_iounmap(rsa->dev, rsa->iomem);
++    kfree(rsa);
++
++    return 0;
++}
++
++static const struct of_device_id ingenic_rsa_dt_match[] = {
++    { .compatible = "ingenic,rsa", .data = NULL },
++    {},
++};
++MODULE_DEVICE_TABLE(of, aic_dt_match);
++
++static struct platform_driver ingenic_rsa_driver = {
++    .probe	= jz_rsa_probe,
++    .remove	= jz_rsa_remove,
++    .driver	= {
++        .name	= "rsa",
++        .owner	= THIS_MODULE,
++        .of_match_table = of_match_ptr(ingenic_rsa_dt_match),
++    },
++};
++
++module_platform_driver(ingenic_rsa_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("mayuanjun <yuanjun.ma@ingenic.com>");
++MODULE_DESCRIPTION("ingenic rsa driver");
+diff --git a/module_drivers/drivers/mmc/Makefile b/module_drivers/drivers/mmc/Makefile
+new file mode 100644
+index 000000000..4ed51fb9a
+--- /dev/null
++++ b/module_drivers/drivers/mmc/Makefile
+@@ -0,0 +1 @@
++obj-y += host/
+diff --git a/module_drivers/drivers/mmc/host/Kconfig b/module_drivers/drivers/mmc/host/Kconfig
+new file mode 100644
+index 000000000..a174c55a2
+--- /dev/null
++++ b/module_drivers/drivers/mmc/host/Kconfig
+@@ -0,0 +1,40 @@
++
++config MMC_SDHCI_INGENIC
++        tristate "Ingenic(XBurst2)  MMC/SD Card Controller(MSC) support"
++	depends on SOC_X2000 || SOC_X2000_V12 || SOC_M300 || SOC_X2500 || SOC_X2100
++        select MMC_SDHCI
++        help
++          This selects the Ingenic XBurst2 SD/MMC Card Controller MSC.
++          If you have platform with a SD/Multimedia Card slot and compact
++          with this version, say Y or M here.
++          If unsure, say N.
++
++config MMC_INDEX_MATCH_CONTROLLER
++        tristate "MMC Index match Controller support."
++        depends on MMC_SDHCI_INGENIC || INGENIC_MMC
++        default n
++        help
++          This selects the MMC Index match Controller support.This option
++          will enable MMC index to match the controller number. If you want
++          mmcblk to correspond to the controller number,say Y or M here.
++
++          If unsure, say N.
++
++
++ config INGENIC_MMC
++         tristate "Ingenic(XBurst)  MMC/SD Card Controller(MSC) support"
++         depends on SOC_X1600 || SOC_X1000 || SOC_X1800 || SOC_X1021 || SOC_X1520 || SOC_X1630
++         help
++           This selects the Ingenic XBurst SD/MMC Card Controller.
++           If you have platform with a SD/Multimedia Card slot and compact
++           with this version, say Y or M here.
++           If unsure, say N.
++
++ config INGENIC_MMC_MMC0
++         bool "INGENIC_MMC MMC0"
++         depends on INGENIC_MMC
++
++ config INGENIC_MMC_MMC1
++         bool "INGENIC_MMC MMC1"
++         depends on INGENIC_MMC
++
+diff --git a/module_drivers/drivers/mmc/host/Makefile b/module_drivers/drivers/mmc/host/Makefile
+new file mode 100644
+index 000000000..1d7c567d1
+--- /dev/null
++++ b/module_drivers/drivers/mmc/host/Makefile
+@@ -0,0 +1,5 @@
++ccflags-y += -I$(srctree)/drivers/mmc/host/
++
++obj-$(CONFIG_MMC_SDHCI_INGENIC)         += sdhci-ingenic.o ingenic_sdio.o
++obj-$(CONFIG_INGENIC_MMC_MMC0)  	+= ingenic_mmc.o ingenic_sdio.o
++obj-$(CONFIG_INGENIC_MMC_MMC1)  	+= ingenic_mmc.o ingenic_sdio.o
+diff --git a/module_drivers/drivers/mmc/host/ingenic_mmc.c b/module_drivers/drivers/mmc/host/ingenic_mmc.c
+new file mode 100644
+index 000000000..86a58b456
+--- /dev/null
++++ b/module_drivers/drivers/mmc/host/ingenic_mmc.c
+@@ -0,0 +1,1815 @@
++/*
++ * Ingenic MMC/SD Controller driver
++ *
++ * Copyright (C) 2012 Ingenic Semiconductor Co., Ltd.
++ * Written by Large Dipper <ykli@ingenic.com>.
++ *
++ * Modified by qipengzhen <aric.pzqi@ingenic.com> 2016-04-21
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/platform_device.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/card.h>
++#include <linux/mmc/mmc.h>
++#include <linux/mmc/sd.h>
++#include <linux/mmc/sdio.h>
++#include <linux/scatterlist.h>
++#include <linux/dma-mapping.h>
++#include <linux/gpio.h>
++#include <linux/clk.h>
++#include <linux/regulator/consumer.h>
++#include <asm-generic/delay.h>
++
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/stat.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_gpio.h>
++#include <linux/of_device.h>
++#include <linux/clk-provider.h>
++
++#include "ingenic_mmc.h"
++
++/**
++ * MMC driver parameters
++ */
++#define TIMEOUT_PERIOD		3000	/* msc operation timeout detect period */
++#define PIO_THRESHOLD		64	/* use pio mode if data length < PIO_THRESHOLD */
++#define CLK_RATE (CONFIG_EXTAL_CLOCK * 1000000)
++#define CLK_CTRL
++
++#define ERROR_IFLG (							\
++		IFLG_CRC_RES_ERR	|					\
++		IFLG_CRC_READ_ERR	|					\
++		IFLG_CRC_WRITE_ERR	|					\
++		IFLG_TIMEOUT_RES	|					\
++		IFLG_TIMEOUT_READ)
++
++/*
++ * Error status including CRC_READ_ERROR, CRC_WRITE_ERROR,
++ * CRC_RES_ERR, TIME_OUT_RES, TIME_OUT_READ
++ */
++#define ERROR_STAT		0x3f
++
++#define ingenic_mmc_check_pending(host, event)		\
++	test_and_clear_bit(event, &host->pending_events)
++#define ingenic_mmc_set_pending(host, event)			\
++	set_bit(event, &host->pending_events)
++#define is_pio_mode(host)						\
++	(host->flags & (1 << INGENIC_MMC_USE_PIO))
++#define enable_pio_mode(host)					\
++	(host->flags |= (1 << INGENIC_MMC_USE_PIO))
++#define disable_pio_mode(host)					\
++	(host->flags &= ~(1 << INGENIC_MMC_USE_PIO))
++
++static LIST_HEAD(manual_list);
++
++/*-------------------End structure and macro define------------------------*/
++
++#ifndef IT_IS_USED_FOR_DEBUG
++static void ingenic_mmc_dump_reg(struct ingenic_mmc_host *host)
++{
++	dev_info(host->dev,"\nREG dump:\n"
++			 "\tCTRL2\t= 0x%08X\n"
++			 "\tSTAT\t= 0x%08X\n"
++			 "\tCLKRT\t= 0x%08X\n"
++			 "\tCMDAT\t= 0x%08X\n"
++			 "\tRESTO\t= 0x%08X\n"
++			 "\tRDTO\t= 0x%08X\n"
++			 "\tBLKLEN\t= 0x%08X\n"
++			 "\tNOB\t= 0x%08X\n"
++			 "\tSNOB\t= 0x%08X\n"
++			 "\tIMASK\t= 0x%08X\n"
++			 "\tIFLG\t= 0x%08X\n"
++			 "\tCMD\t= 0x%08X\n"
++			 "\tARG\t= 0x%08X\n"
++			 "\tRES\t= 0x%08X\n"
++			 "\tLPM\t= 0x%08X\n"
++			 "\tDMAC\t= 0x%08X\n"
++			 "\tDMANDA\t= 0x%08X\n"
++			 "\tDMADA\t= 0x%08X\n"
++			 "\tDMALEN\t= 0x%08X\n"
++			 "\tDMACMD\t= 0x%08X\n"
++			 "\tRTCNT\t= 0x%08X\n"
++			 "\tDEBUG\t= 0x%08X\n",
++
++			 msc_readl(host, CTRL2),
++			 msc_readl(host, STAT),
++			 msc_readl(host, CLKRT),
++			 msc_readl(host, CMDAT),
++			 msc_readl(host, RESTO),
++			 msc_readl(host, RDTO),
++			 msc_readl(host, BLKLEN),
++			 msc_readl(host, NOB),
++			 msc_readl(host, SNOB),
++			 msc_readl(host, IMASK),
++			 msc_readl(host, IFLG),
++			 msc_readl(host, CMD),
++			 msc_readl(host, ARG),
++			 msc_readl(host, RES),
++			 msc_readl(host, LPM),
++			 msc_readl(host, DMAC),
++			 msc_readl(host, DMANDA),
++			 msc_readl(host, DMADA),
++			 msc_readl(host, DMALEN),
++			 msc_readl(host, DMACMD),
++			 msc_readl(host, RTCNT),
++			 msc_readl(host, DEBUG));
++}
++#endif
++
++/*
++ * Functional functions.
++ *
++ * These small function will be called frequently.
++ */
++static inline void enable_msc_irq(struct ingenic_mmc_host *host, unsigned long bits)
++{
++	unsigned long imsk;
++
++	spin_lock_bh(&host->lock);
++	imsk = msc_readl(host, IMASK);
++	imsk &= ~bits;
++	msc_writel(host, IMASK, imsk);
++	spin_unlock_bh(&host->lock);
++}
++
++static inline void clear_msc_irq(struct ingenic_mmc_host *host, unsigned long bits)
++{
++	msc_writel(host, IFLG, bits);
++}
++
++static inline void disable_msc_irq(struct ingenic_mmc_host *host, unsigned long bits)
++{
++	unsigned long imsk;
++
++	spin_lock_bh(&host->lock);
++	imsk = msc_readl(host, IMASK);
++	imsk |= bits;
++	msc_writel(host, IMASK, imsk);
++	spin_unlock_bh(&host->lock);
++}
++
++static inline void ingenic_mmc_reset(struct ingenic_mmc_host *host)
++{
++	unsigned int clkrt = msc_readl(host, CLKRT);
++	unsigned int cnt = 100 * 1000 * 1000;
++	int vl;
++
++	msc_writel(host, CTRL, CTRL_RESET);
++	vl = msc_readl(host,CTRL);
++	vl &= ~CTRL_RESET;
++	msc_writel(host, CTRL, vl);
++
++	while ((msc_readl(host, STAT) & STAT_IS_RESETTING) && (--cnt));
++	WARN_ON(!cnt);
++
++	if(host->pdata->sdio_clk)
++		msc_writel(host, CTRL, CTRL_CLOCK_START);
++	else
++		msc_writel(host, LPM, LPM_LPM);
++
++	msc_writel(host, IMASK, 0xffffffff);
++	msc_writel(host, IFLG, 0xffffffff);
++
++	msc_writel(host, CLKRT, clkrt);
++}
++
++static inline void ingenic_mmc_stop_dma(struct ingenic_mmc_host *host)
++{
++	dev_warn(host->dev, "%s\n", __func__);
++
++	/*
++	 * Theoretically, DMA can't be stopped when transfering, so we can only
++	 * diable it when it is out of DMA request.
++	 */
++	msc_writel(host, DMAC, 0);
++}
++
++static inline int request_need_stop(struct mmc_request *mrq)
++{
++	return mrq->stop ? 1 : 0;
++}
++static inline void ingenic_mmc_clk_onoff(struct ingenic_mmc_host *host, unsigned int on)
++{
++	if(on) {
++		clk_prepare_enable(host->clk_cgu);
++		clk_prepare_enable(host->clk_gate);
++	} else {
++		clk_disable_unprepare(host->clk_cgu);
++		clk_disable_unprepare(host->clk_gate);
++	}
++}
++static inline int check_error_status(struct ingenic_mmc_host *host, unsigned int status)
++{
++	if (status & ERROR_STAT) {
++		dev_err(host->dev, "Error status->0x%08X: cmd=%d, state=%d\n",
++				status, host->cmd->opcode, host->state);
++		return -1;
++	}
++	return 0;
++}
++
++static int ingenic_mmc_polling_status(struct ingenic_mmc_host *host, unsigned int status)
++{
++	unsigned int cnt = 100 * 1000 * 1000;
++	while(!(msc_readl(host, STAT) & (status | ERROR_STAT))				\
++	      && test_bit(INGENIC_MMC_CARD_PRESENT, &host->flags) && (--cnt));
++
++	if (unlikely(!cnt)) {
++		dev_err(host->dev, "polling status(0x%08X) time out, "
++				"op=%d, status=0x%08X\n", status,
++				host->cmd->opcode, msc_readl(host, STAT));
++		return -1;
++	}
++	if (unlikely(!test_bit(INGENIC_MMC_CARD_PRESENT, &host->flags))) {
++		dev_err(host->dev, "card remove while polling"
++				"status(0x%08X), op=%d\n", status, host->cmd->opcode);
++		return -1;
++	}
++	if (msc_readl(host, STAT) & ERROR_STAT) {
++		dev_err(host->dev, "polling status(0x%08X) error, "
++				"op=%d, status=0x%08X\n", status,
++				host->cmd->opcode, msc_readl(host, STAT));
++		return -1;
++	}
++
++	return 0;
++}
++
++static void send_stop_command(struct ingenic_mmc_host *host)
++{
++	struct mmc_command *stop_cmd = host->mrq->stop;
++
++	msc_writel(host, CMD, stop_cmd->opcode);
++	msc_writel(host, ARG, stop_cmd->arg);
++	msc_writel(host, CMDAT, CMDAT_BUSY | CMDAT_RESPONSE_R1);
++	msc_writel(host, RESTO, 0xff);
++	msc_writel(host, CTRL, CTRL_START_OP);
++
++	if (ingenic_mmc_polling_status(host, STAT_END_CMD_RES))
++		stop_cmd->error = -EIO;
++}
++static void ingenic_mmc_command_done(struct ingenic_mmc_host *host, struct mmc_command *cmd)
++{
++	unsigned long res;
++
++	if ((host->cmdat & CMDAT_RESPONSE_MASK) == CMDAT_RESPONSE_R2) {
++		int i;
++		res = msc_readl(host, RES);
++		for (i = 0 ; i < 4 ; i++) {
++			cmd->resp[i] = res << 24;
++			res = msc_readl(host, RES);
++			cmd->resp[i] |= res << 8;
++			res = msc_readl(host, RES);
++			cmd->resp[i] |= res >> 8;
++		}
++	} else {
++		res = msc_readl(host, RES);
++		cmd->resp[0] = res << 24;
++		res = msc_readl(host, RES);
++		cmd->resp[0] |= res << 8;
++		res = msc_readl(host, RES);
++		cmd->resp[0] |= res & 0xff;
++	}
++
++	clear_msc_irq(host, IFLG_END_CMD_RES);
++}
++
++static void ingenic_mmc_data_done(struct ingenic_mmc_host *host)
++{
++	struct mmc_data *data = host->data;
++
++	if (data->error == 0)
++		data->bytes_xfered = (data->blocks * data->blksz);
++	else {
++		ingenic_mmc_stop_dma(host);
++		data->bytes_xfered = 0;
++		dev_err(host->dev, "error when request done\n");
++	}
++
++	del_timer_sync(&host->request_timer);
++	mmc_request_done(host->mmc, host->mrq);
++}
++
++/*------------------------End functional functions-------------------------*/
++
++/*
++ * State machine.
++ *
++ * The state machine is the manager of the mmc_request. It's triggered by
++ * MSC interrupt and work in interrupt context.
++ */
++static void ingenic_mmc_state_machine(struct ingenic_mmc_host *host, unsigned int status)
++{
++	struct mmc_request *mrq = host->mrq;
++	struct mmc_data *data = host->data;
++
++	WARN_ON(host->double_enter++);
++start:
++	dev_dbg(host->dev, "enter state: %d\n", host->state);
++
++	switch (host->state) {
++	case STATE_IDLE:
++		dev_warn(host->dev, "WARN: enter state machine with IDLE\n");
++		break;
++
++	case STATE_WAITING_RESP:
++		if (!ingenic_mmc_check_pending(host, EVENT_CMD_COMPLETE))
++			break;
++		if (unlikely(check_error_status(host, status) != 0)) {
++			host->state = STATE_ERROR;
++			clear_msc_irq(host, IFLG_CRC_RES_ERR
++						  | IFLG_TIMEOUT_RES
++						  | IFLG_END_CMD_RES);
++			goto start;
++		}
++		ingenic_mmc_command_done(host, mrq->cmd);
++		if (!data) {
++			host->state = STATE_IDLE;
++			del_timer_sync(&host->request_timer);
++			mmc_request_done(host->mmc, host->mrq);
++			break;
++		}
++		host->state = STATE_WAITING_DATA;
++		break;
++
++	case STATE_WAITING_DATA:
++		if (!ingenic_mmc_check_pending(host, EVENT_DATA_COMPLETE))
++			break;
++		if (unlikely(check_error_status(host, status) != 0)) {
++			clear_msc_irq(host, IFLG_DATA_TRAN_DONE
++						  | IFLG_CRC_READ_ERR
++						  | IFLG_CRC_WRITE_ERR
++						  | IFLG_TIMEOUT_READ);
++			if (request_need_stop(host->mrq))
++				send_stop_command(host);
++			host->state = STATE_ERROR;
++			goto start;
++		}
++
++		if (request_need_stop(host->mrq)) {
++			if (likely(msc_readl(host, STAT) & STAT_AUTO_CMD12_DONE)) {
++				disable_msc_irq(host, IMASK_AUTO_CMD12_DONE);
++				clear_msc_irq(host, IFLG_AUTO_CMD12_DONE);
++				host->state = STATE_IDLE;
++				ingenic_mmc_data_done(host);
++			} else {
++				enable_msc_irq(host, IMASK_AUTO_CMD12_DONE);
++				if (msc_readl(host, STAT) & STAT_AUTO_CMD12_DONE) {
++					disable_msc_irq(host, IMASK_AUTO_CMD12_DONE);
++					clear_msc_irq(host, IFLG_AUTO_CMD12_DONE);
++					host->state = STATE_IDLE;
++					ingenic_mmc_data_done(host);
++				} else
++					host->state = STATE_SENDING_STOP;
++			}
++		} else {
++			host->state = STATE_IDLE;
++			ingenic_mmc_data_done(host);
++		}
++		break;
++
++	case STATE_SENDING_STOP:
++		if (!ingenic_mmc_check_pending(host, EVENT_STOP_COMPLETE))
++			break;
++		host->state = STATE_IDLE;
++		ingenic_mmc_data_done(host);
++		break;
++
++	case STATE_ERROR:
++		if (host->state == STATE_WAITING_DATA)
++			host->data->error = -1;
++		host->cmd->error = -1;
++
++		if (data) {
++			data->bytes_xfered = 0;
++			/* Whether should we stop DMA here? */
++		}
++		del_timer_sync(&host->request_timer);
++		host->state = STATE_IDLE;
++		mmc_request_done(host->mmc, host->mrq);
++		break;
++	}
++
++	dev_dbg(host->dev, "exit state: %d\n", host->state);
++	host->double_enter--;
++}
++
++static irqreturn_t ingenic_mmc_thread_handle(int irq, void *dev_id)
++{
++	struct ingenic_mmc_host *host = (struct ingenic_mmc_host *)dev_id;
++	unsigned int iflg, imask, pending, status;
++
++start:
++	iflg = msc_readl(host, IFLG);
++	imask = msc_readl(host, IMASK);
++	pending = iflg & ~imask;
++	status = msc_readl(host, STAT);
++	dev_dbg(host->dev, "%s: iflg-0x%08X imask-0x%08X status-0x%08X\n",
++			__func__, iflg, imask, status);
++
++	if (!pending) {
++		goto out;
++	} else if (pending & IFLG_SDIO) {
++		mmc_signal_sdio_irq(host->mmc);
++		goto out;
++	} else if (pending & ERROR_IFLG) {
++		unsigned int mask = ERROR_IFLG;
++
++		dev_dbg(host->dev, "%s: iflg-0x%08X imask-0x%08X status-0x%08X\n",
++				__func__, iflg, imask, status);
++
++		dev_dbg(host->dev, "err%d cmd%d iflg%08X status%08X\n",
++				host->state, host->cmd ? host->cmd->opcode : -1, iflg, status);
++
++		if (host->state == STATE_WAITING_RESP)
++			mask |= IMASK_END_CMD_RES;
++		else if (host->state == STATE_WAITING_DATA)
++			mask |= IMASK_WR_ALL_DONE | IMASK_DMA_DATA_DONE;
++
++		clear_msc_irq(host, mask);
++		disable_msc_irq(host, mask);
++
++		/*
++		 * It seems that cmd53 CRC error occurs frequently
++		 * at 50mHz clk, but it disappear at 40mHz. In case of
++		 * it happens, we add retry here to try to fix the error.
++		 */
++		if ((host->cmd->opcode == 53)
++		    && (status & STAT_CRC_READ_ERROR)) {
++			dev_err(host->dev, "cmd53 crc error, retry.\n");
++			host->cmd->error = -1;
++			host->cmd->retries = 1;
++			host->data->bytes_xfered = 0;
++			del_timer_sync(&host->request_timer);
++			host->state = STATE_IDLE;
++			mmc_request_done(host->mmc, host->mrq);
++			goto out;
++		}
++		host->state = STATE_ERROR;
++		ingenic_mmc_state_machine(host, status);
++		goto out;
++
++	} else if (pending & IFLG_END_CMD_RES) {
++		ingenic_mmc_set_pending(host, EVENT_CMD_COMPLETE);
++		disable_msc_irq(host, IMASK_END_CMD_RES |		\
++						IMASK_CRC_RES_ERR | IMASK_TIME_OUT_RES);
++		ingenic_mmc_state_machine(host, status);
++	} else if (pending & IFLG_WR_ALL_DONE) {
++		ingenic_mmc_set_pending(host, EVENT_DATA_COMPLETE);
++		clear_msc_irq(host, IFLG_WR_ALL_DONE
++					  | IFLG_DMAEND
++					  | IFLG_DATA_TRAN_DONE
++					  | IFLG_PRG_DONE);
++		disable_msc_irq(host, IMASK_WR_ALL_DONE | IMASK_CRC_WRITE_ERR);
++		ingenic_mmc_state_machine(host, status);
++
++	} else if (pending & IFLG_DMA_DATA_DONE) {
++		ingenic_mmc_set_pending(host, EVENT_DATA_COMPLETE);
++		clear_msc_irq(host, IFLG_DATA_TRAN_DONE | IFLG_DMAEND |
++					  IFLG_DMA_DATA_DONE);
++		disable_msc_irq(host, IMASK_DMA_DATA_DONE | IMASK_CRC_READ_ERR);
++		ingenic_mmc_state_machine(host, status);
++	} else if (pending & IFLG_AUTO_CMD12_DONE) {
++		ingenic_mmc_set_pending(host, EVENT_STOP_COMPLETE);
++		clear_msc_irq(host, IFLG_AUTO_CMD12_DONE);
++		disable_msc_irq(host, IMASK_AUTO_CMD12_DONE);
++		ingenic_mmc_state_machine(host, status);
++
++	} else
++		dev_warn(host->dev, "state-%d: Nothing happens?!\n", host->state);
++
++	/*
++	 * Check if the status has already changed. If so, goto start so that
++	 * we can avoid an interrupt.
++	 */
++	if (status != msc_readl(host, STAT)) {
++		goto start;
++	}
++
++out:
++	return IRQ_HANDLED;
++}
++/*--------------------------End state machine------------------------------*/
++
++/*
++ * DMA handler.
++ *
++ * Descriptor DMA transfer that can handle scatter gather list directly
++ * without bounce buffer which may cause a big deal of memcpy.
++ */
++static inline void sg_to_desc(struct scatterlist *sgentry, struct desc_hd *dhd)
++{
++	dhd->dma_desc->da = sg_phys(sgentry);
++	dhd->dma_desc->len = sg_dma_len(sgentry);
++	dhd->dma_desc->dcmd = DMACMD_LINK;
++}
++
++static void ingenic_mmc_submit_dma(struct ingenic_mmc_host *host, struct mmc_data *data)
++{
++	int i = 0;
++	struct scatterlist *sgentry;
++	struct desc_hd *dhd = &(host->decshds[0]);
++
++	dma_map_sg(host->dev, data->sg, data->sg_len,
++			   data->flags & MMC_DATA_WRITE
++			   ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
++
++	for_each_sg(data->sg, sgentry, data->sg_len, i) {
++		sg_to_desc(sgentry, dhd);
++		if ((data->sg_len - i) > 1) {
++			if (unlikely(dhd->next == NULL))
++				dev_err(host->dev, "dhd->next == NULL\n");
++			else {
++				dhd->dma_desc->nda = dhd->next->dma_desc_phys_addr;
++				dhd = dhd->next;
++			}
++		}
++	}
++
++	dma_unmap_sg(host->dev, data->sg, data->sg_len,
++				 data->flags & MMC_DATA_WRITE
++				 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
++
++	dhd->dma_desc->dcmd |= DMACMD_ENDI;
++	dhd->dma_desc->dcmd &= ~DMACMD_LINK;
++}
++
++static inline unsigned int get_incr(unsigned int dma_len)
++{
++	unsigned int incr = 0;
++
++	BUG_ON(!dma_len);
++#if 0
++	/*
++	 * BUG here!
++	 */
++	switch (dma_len) {
++#define _CASE(S,D) case S: incr = D; break
++		_CASE(1 ... 31, 0);
++		_CASE(32 ... 63, 1);
++	default:
++		incr = 2;
++		break;
++#undef _CASE
++	}
++#else
++	incr = 2;
++#endif
++	return incr;
++}
++
++/* #define PERFORMANCE_DMA */
++static inline void ingenic_mmc_dma_start(struct ingenic_mmc_host *host, struct mmc_data *data)
++{
++	dma_addr_t dma_addr = sg_phys(data->sg);
++	unsigned int dma_len = sg_dma_len(data->sg);
++	unsigned int dmac;
++
++#ifdef PERFORMANCE_DMA
++	dmac = (get_incr(dma_len) << DMAC_INCR_SHF) | DMAC_DMAEN | DMAC_MODE_SEL;
++#else
++	dmac = (get_incr(dma_len) << DMAC_INCR_SHF) | DMAC_DMAEN;
++#endif
++
++	if ((dma_addr & 0x3) || (dma_len & 0x3)) {
++		dmac |= DMAC_ALIGNEN;
++		if (dma_addr & 0x3)
++			dmac |= (dma_addr % 4) << DMAC_AOFST_SHF;
++	}
++	msc_writel(host, DMANDA, host->decshds[0].dma_desc_phys_addr);
++	msc_writel(host, DMAC, dmac);
++}
++
++/*----------------------------End DMA handler------------------------------*/
++
++/*
++ * PIO transfer mode.
++ *
++ * Functions of PIO read/write mode that can handle 1, 2 or 3 bytes transfer
++ * even though the FIFO register is 32-bits width.
++ * It's better just used for test.
++ */
++static int wait_cmd_response(struct ingenic_mmc_host *host)
++{
++	if (ingenic_mmc_polling_status(host, STAT_END_CMD_RES) < 0) {
++		dev_err(host->dev, "PIO mode: command response error\n");
++		return -1;
++	}
++	msc_writel(host, IFLG, IFLG_END_CMD_RES);
++	return 0;
++}
++
++static void do_pio_read(struct ingenic_mmc_host *host,
++						unsigned int *addr, unsigned int cnt)
++{
++	int i = 0;
++	unsigned int status = 0;
++
++	for (i = 0; i < cnt / 4; i++) {
++		while (((status = msc_readl(host, STAT))
++				& STAT_DATA_FIFO_EMPTY)
++		       && test_bit(INGENIC_MMC_CARD_PRESENT, &host->flags));
++
++		if (!test_bit(INGENIC_MMC_CARD_PRESENT, &host->flags)) {
++			host->data->error = -ENOMEDIUM;
++			dev_err(host->dev,
++					"PIO mode: card remove while reading\n");
++			return;
++		}
++		if (check_error_status(host, status)) {
++			host->data->error = -1;
++			return;
++		}
++		*addr++ = msc_readl(host, RXFIFO);
++	}
++
++	/*
++	 * These codes handle the last 1, 2 or 3 bytes transfer.
++	 */
++	if (cnt & 3) {
++		u32 n = cnt & 3;
++		u32 data = msc_readl(host, RXFIFO);
++		u8 *p = (u8 *)addr;
++
++		while (n--) {
++			*p++ = data;
++			data >>= 8;
++		}
++	}
++}
++
++static void do_pio_write(struct ingenic_mmc_host *host,
++						 unsigned int *addr, unsigned int cnt)
++{
++	int i = 0;
++	unsigned int status = 0;
++
++	for (i = 0; i < (cnt / 4); i++) {
++		while (((status = msc_readl(host, STAT))
++				& STAT_DATA_FIFO_FULL)
++		       && test_bit(INGENIC_MMC_CARD_PRESENT, &host->flags));
++
++		if(!test_bit(INGENIC_MMC_CARD_PRESENT, &host->flags)) {
++			host->data->error = -ENOMEDIUM;
++			dev_err(host->dev,
++					"PIO mode: card remove while writing\n");
++			break;
++		}
++		if (check_error_status(host, status)) {
++			host->data->error = -1;
++			return;
++		}
++		msc_writel(host, TXFIFO, *addr++);
++	}
++
++	/*
++	 * These codes handle the last 1, 2 or 3 bytes transfer.
++	 */
++	if (cnt & 3) {
++		u32 data = 0;
++		u8 *p = (u8 *)addr;
++
++		for (i = 0; i < (cnt & 3); i++)
++			data |= *p++ << (8 * i);
++
++		msc_writel(host, TXFIFO, data);
++	}
++}
++
++static inline void pio_trans_start(struct ingenic_mmc_host *host, struct mmc_data *data)
++{
++	unsigned int *addr = sg_virt(data->sg);
++	unsigned int cnt = sg_dma_len(data->sg);
++
++	if (data->flags & MMC_DATA_WRITE)
++		do_pio_write(host, addr, cnt);
++	else
++		do_pio_read(host, addr, cnt);
++}
++
++static void pio_trans_done(struct ingenic_mmc_host *host, struct mmc_data *data)
++{
++	if (data->error == 0)
++		data->bytes_xfered = data->blocks * data->blksz;
++	else
++		data->bytes_xfered = 0;
++
++	if (host->mrq->stop) {
++		if (ingenic_mmc_polling_status(host, STAT_AUTO_CMD12_DONE) < 0)
++			data->error = -EIO;
++	}
++
++	if (data->flags & MMC_DATA_WRITE) {
++		if (ingenic_mmc_polling_status(host, STAT_PRG_DONE) < 0) {
++			data->error = -EIO;
++		}
++		clear_msc_irq(host, IFLG_PRG_DONE);
++	} else {
++		if (ingenic_mmc_polling_status(host, STAT_DATA_TRAN_DONE) < 0) {
++			data->error = -EIO;
++		}
++		clear_msc_irq(host, IFLG_DATA_TRAN_DONE);
++	}
++}
++
++/*-------------------------End PIO transfer mode---------------------------*/
++
++/*
++ * Achieve mmc_request here.
++ */
++static void ingenic_mmc_data_pre(struct ingenic_mmc_host *host, struct mmc_data *data)
++{
++	unsigned int nob = data->blocks;
++	unsigned long cmdat,imsk;
++
++	msc_writel(host, RDTO, 0xffffff);
++	msc_writel(host, NOB, nob);
++	msc_writel(host, BLKLEN, data->blksz);
++	cmdat = CMDAT_DATA_EN;
++
++	msc_writel(host, CMDAT, CMDAT_DATA_EN);
++
++
++	if (data->flags & MMC_DATA_WRITE) {
++		cmdat |= CMDAT_WRITE_READ;
++		imsk = IMASK_WR_ALL_DONE | IMASK_CRC_WRITE_ERR;
++	} else if (data->flags & MMC_DATA_READ) {
++		cmdat &= ~CMDAT_WRITE_READ;
++		imsk = IMASK_DMA_DATA_DONE
++			| IMASK_TIME_OUT_READ
++			| IMASK_CRC_READ_ERR;
++	} else {
++		dev_err(host->dev, "data direction confused\n");
++		BUG_ON(1);
++	}
++	host->cmdat |= cmdat;
++
++	if (!is_pio_mode(host)) {
++		ingenic_mmc_submit_dma(host, data);
++		clear_msc_irq(host, IFLG_PRG_DONE);
++		enable_msc_irq(host, imsk);
++	}
++}
++
++static void ingenic_mmc_data_start(struct ingenic_mmc_host *host, struct mmc_data *data)
++{
++	if (is_pio_mode(host)) {
++		pio_trans_start(host, data);
++		pio_trans_done(host, data);
++		del_timer_sync(&host->request_timer);
++		if (!(host->pdata->pio_mode))
++			disable_pio_mode(host);
++		mmc_request_done(host->mmc, host->mrq);
++	} else {
++		ingenic_mmc_dma_start(host, data);
++	}
++}
++
++static void ingenic_mmc_command_start(struct ingenic_mmc_host *host, struct mmc_command *cmd)
++{
++	unsigned long cmdat = 0;
++	unsigned long imsk;
++
++	if (cmd->flags & MMC_RSP_BUSY)
++		cmdat |= CMDAT_BUSY;
++	if (request_need_stop(host->mrq))
++		cmdat |= CMDAT_AUTO_CMD12;
++
++
++	switch (mmc_resp_type(cmd)) {
++#define _CASE(S,D) case MMC_RSP_##S: cmdat |= CMDAT_RESPONSE_##D; break
++		_CASE(R1, R1); 	/* r1 = r5,r6,r7 */
++		_CASE(R1B, R1);
++		_CASE(R2, R2);
++		_CASE(R3, R3); 	/* r3 = r4 */
++	default:
++		break;
++#undef _CASE
++	}
++	host->cmdat |= cmdat;
++	if (!is_pio_mode(host)) {
++		imsk = IMASK_TIME_OUT_RES | IMASK_END_CMD_RES;
++		enable_msc_irq(host, imsk);
++		host->state = STATE_WAITING_RESP;
++	}
++	msc_writel(host, CMD, cmd->opcode);
++	msc_writel(host, ARG, cmd->arg);
++	msc_writel(host, CMDAT, host->cmdat);
++	msc_writel(host, CTRL, CTRL_START_OP);
++	if (is_pio_mode(host)) {
++		if (wait_cmd_response(host) < 0) {
++			cmd->error = -ETIMEDOUT;
++			del_timer_sync(&host->request_timer);
++			mmc_request_done(host->mmc, host->mrq);
++			return;
++		}
++		ingenic_mmc_command_done(host, host->cmd);
++		if (!host->data) {
++			del_timer_sync(&host->request_timer);
++			mmc_request_done(host->mmc, host->mrq);
++		}
++	}
++}
++
++static void ingenic_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
++{
++	struct ingenic_mmc_host *host = mmc_priv(mmc);
++	if (!test_bit(INGENIC_MMC_CARD_PRESENT, &host->flags)) {
++		dev_vdbg(host->dev, "No card present\n");
++		mrq->cmd->error = -ENOMEDIUM;
++		mmc_request_done(mmc, mrq);
++		return;
++	}
++
++	/*
++	 * It means that this request may flush cache in interrupt context.
++	 * It never happens in design, but we add BUG_ON here to prevent it.
++	 */
++	if ((host->state != STATE_IDLE) && (mrq->data != NULL)) {
++		dev_warn(host->dev, "operate in non-idle state\n");
++		WARN_ON(1);
++	}
++
++	host->mrq = mrq;
++	host->data = mrq->data;
++	host->cmd = mrq->cmd;
++	if (host->data)
++		dev_dbg(host->dev, "op:%d arg:0x%08X sz:%uk\n",
++				host->cmd->opcode, host->cmd->arg,
++				host->data->blocks >> 1);
++	else
++		dev_dbg(host->dev, "op:%d\n", host->cmd->opcode);
++
++	host->cmdat = host->cmdat_def;
++	if(host->data) {
++		if ((host->data->sg_len == 1)
++		    && (sg_dma_len(host->data->sg)) < PIO_THRESHOLD) {
++			enable_pio_mode(host);
++		}
++
++		ingenic_mmc_data_pre(host, host->data);
++	}
++	/*
++	 * We would get mmc_request_done at last, unless some terrible error
++	 * occurs such as intensity rebounding of VDD, that maybe result in
++	 * no action to complete the request.
++	 */
++	host->timeout_cnt = 0;
++	mod_timer(&host->request_timer, jiffies +
++			  msecs_to_jiffies(TIMEOUT_PERIOD));
++	ingenic_mmc_command_start(host, host->cmd);
++	if (host->data) {
++		ingenic_mmc_data_start(host, host->data);
++
++	}
++	if (unlikely(test_and_clear_bit(INGENIC_MMC_CARD_NEED_INIT, &host->flags)))
++		host->cmdat_def &= ~CMDAT_INIT;
++}
++
++static void ingenic_mmc_request_timeout(struct timer_list *t)
++{
++	struct ingenic_mmc_host *host = from_timer(host, t, request_timer);
++	unsigned int status = msc_readl(host, STAT);
++	if (host->timeout_cnt++ < (3000 / TIMEOUT_PERIOD)) {
++		dev_warn(host->dev, "timeout %dms op:%d %s sz:%d state:%d "
++				 "STAT:0x%08X DMALEN:0x%08X blks:%d/%d clk:%s\n",
++				 host->timeout_cnt * TIMEOUT_PERIOD,
++				 host->cmd->opcode,
++				 host->data
++				 ? (host->data->flags & MMC_DATA_WRITE ? "w" : "r")
++				 : "",
++				 host->data ? host->data->blocks << 9 : 0,
++				 host->state,
++				 status,
++				 msc_readl(host, DMALEN),
++				 msc_readl(host, SNOB),
++				 msc_readl(host, NOB),
++				 __clk_is_enabled(host->clk_cgu) ? "enable" : "disable");
++		mod_timer(&host->request_timer, jiffies +
++				  msecs_to_jiffies(TIMEOUT_PERIOD));
++		return;
++
++	} else if (host->timeout_cnt++ < (60000 / TIMEOUT_PERIOD)) {
++		mod_timer(&host->request_timer, jiffies +
++				  msecs_to_jiffies(TIMEOUT_PERIOD));
++		return;
++	}
++
++	dev_err(host->dev, "request time out, op=%d arg=0x%08X, "
++			"sz:%dB state=%d, status=0x%08X, pending=0x%08X, nr_desc=%d\n",
++			host->cmd->opcode, host->cmd->arg,
++			host->data ? host->data->blocks << 9 : -1,
++			host->state, status, (u32)host->pending_events,
++			host->data ? host->data->sg_len : 0);
++	ingenic_mmc_dump_reg(host);
++
++	if (host->data) {
++		int i;
++		dev_err(host->dev, "Descriptor dump:\n");
++		for (i = 0; i < MAX_SEGS; i++) {
++			unsigned int *desc = (unsigned int *)host->decshds[i].dma_desc;
++			dev_err(host->dev, "\t%03d\t nda=%08X da=%08X len=%08X dcmd=%08X\n",
++					i, *desc, *(desc+1), *(desc+2), *(desc+3));
++		}
++		dev_err(host->dev, "\n");
++	}
++
++	if (host->mrq) {
++		if (request_need_stop(host->mrq)) {
++			send_stop_command(host);
++		}
++		host->cmd->error = -ENOMEDIUM;
++		host->state = STATE_IDLE;
++		mmc_request_done(host->mmc, host->mrq);
++	}
++}
++
++/*---------------------------End mmc_request-------------------------------*/
++
++/*
++ * Card insert and remove handler.
++ */
++static irqreturn_t ingenic_mmc_detect_handler(int irq, void *dev_id)
++{
++	struct ingenic_mmc_host *host = (struct ingenic_mmc_host *)dev_id;
++
++	disable_irq_nosync(irq);
++	mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(200));
++
++	return IRQ_HANDLED;
++}
++
++static int get_pin_status(struct ingenic_mmc_pin *pin)
++{
++	int val;
++
++	if(!gpio_is_valid(pin->num)) {
++		return -1;
++	}
++	val = gpio_get_value(pin->num);
++
++	if (pin->enable_level == LOW_ENABLE)
++		return !val;
++	return val;
++}
++
++static void set_pin_status(struct ingenic_mmc_pin *pin, int enable)
++{
++	if(gpio_is_valid(pin->num)) {
++		return;
++	}
++
++	if (pin->enable_level == LOW_ENABLE)
++		enable = !enable;
++	gpio_set_value(pin->num, enable);
++}
++
++static void ingenic_mmc_detect(struct timer_list *t)
++{
++	struct ingenic_mmc_host *host = from_timer(host, t, detect_timer);
++	bool present;
++	bool present_old;
++	static int irq_disable_count;
++
++	present = get_pin_status(&host->pdata->gpio->cd);
++	present_old = test_bit(INGENIC_MMC_CARD_PRESENT, &host->flags);
++
++	if ((present != present_old) || (present_old && host->mmc->card)) {
++		if (present && present_old)
++			dev_warn(host->dev, "rapidly remove\n");
++		else
++			dev_notice(host->dev, "card %s, state=%d\n",
++					   present ? "inserted" : "removed", host->state);
++
++		if (!present || present_old) {
++			clear_bit(INGENIC_MMC_CARD_PRESENT, &host->flags);
++			if(!irq_disable_count) {
++				disable_irq_nosync(host->irq);
++				irq_disable_count = 1;
++			}
++			ingenic_mmc_reset(host);
++
++			if (host->mrq && (host->state > STATE_IDLE)) {
++				host->cmd->error = -ENOMEDIUM;
++				if (host->data) {
++					host->data->bytes_xfered = 0;
++					ingenic_mmc_stop_dma(host);
++				}
++				del_timer_sync(&host->request_timer);
++				mmc_request_done(host->mmc, host->mrq);
++				host->state = STATE_IDLE;
++			}
++			mmc_detect_change(host->mmc, 0);
++		} else {
++			if(irq_disable_count) {
++				enable_irq(host->irq);
++				irq_disable_count = 0;
++			}
++			set_bit(INGENIC_MMC_CARD_PRESENT, &host->flags);
++			/*
++			 * spin_lock() here may case recursion,
++			 * so discard the clk operation.
++			 */
++			ingenic_mmc_clk_onoff(host, 1);
++			mmc_detect_change(host->mmc, msecs_to_jiffies(1000));
++		}
++
++		if (!test_bit(INGENIC_MMC_CARD_PRESENT, &host->flags)) {
++			ingenic_mmc_clk_onoff(host, 0);
++		}
++	}
++
++	enable_irq(gpio_to_irq(host->pdata->gpio->cd.num));
++}
++
++/**
++ *	ingenic_mmc_manual_detect - insert or remove card manually
++ *	@index: host->index, namely the index of the controller.
++ *	@on: 1 means insert card, 0 means remove card.
++ *
++ *	This functions will be called by manually card-detect driver such as
++ *	wifi. To enable this mode you can set value pdata.removal = MANUAL.
++ */
++int ingenic_mmc_manual_detect(int index, int on)
++{
++	struct ingenic_mmc_host *host;
++	struct list_head *pos;
++
++	list_for_each(pos, &manual_list) {
++		host = list_entry(pos, struct ingenic_mmc_host, list);
++		if (host->index == index)
++			break;
++		else
++			host = NULL;
++	}
++
++	if(!host) {
++		printk("no manual card detect\n");
++		return -1;
++	}
++
++	if (on) {
++		dev_vdbg(host->dev, "card insert manually\n");
++		set_bit(INGENIC_MMC_CARD_PRESENT, &host->flags);
++#ifdef CLK_CTRL
++		ingenic_mmc_clk_onoff(host, 1);
++#endif
++		mmc_detect_change(host->mmc, 0);
++	} else {
++		dev_vdbg(host->dev, "card remove manually\n");
++		clear_bit(INGENIC_MMC_CARD_PRESENT, &host->flags);
++		mmc_detect_change(host->mmc, 0);
++#ifdef CLK_CTRL
++		ingenic_mmc_clk_onoff(host, 0);
++#endif
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL(ingenic_mmc_manual_detect);
++
++/**
++ *	ingenic_mmc_clk_ctrl - enable or disable msc clock gate
++ *	@index: host->index, namely the index of the controller.
++ *	@on: 1-enable msc clock gate, 0-disable msc clock gate.
++ */
++int ingenic_mmc_clk_ctrl(int index, int on)
++{
++	struct ingenic_mmc_host *host;
++	struct list_head *pos;
++
++#ifdef CLK_CTRL
++	list_for_each(pos, &manual_list) {
++		host = list_entry(pos, struct ingenic_mmc_host, list);
++		if (host->index == index)
++			break;
++		else
++			host = NULL;
++	}
++
++	if (!host) {
++		printk("no manual card detect\n");
++		return -1;
++	}
++	ingenic_mmc_clk_onoff(host, on);
++#endif
++	return 0;
++}
++EXPORT_SYMBOL(ingenic_mmc_clk_ctrl);
++
++/*
++ * for module driver
++ */
++int jzmmc_manual_detect(int index, int on)
++{
++    return ingenic_mmc_manual_detect(index, on);
++}
++EXPORT_SYMBOL(jzmmc_manual_detect);
++
++int jzmmc_clk_ctrl(int index, int on)
++{
++    return ingenic_mmc_clk_ctrl(index, on);
++}
++EXPORT_SYMBOL(jzmmc_clk_ctrl);
++/*-------------------End card insert and remove handler--------------------*/
++
++/*
++ * Other mmc_ops except request.
++ */
++static inline void ingenic_mmc_power_on(struct ingenic_mmc_host *host)
++{
++	dev_vdbg(host->dev, "power_on\n");
++
++	if (!IS_ERR(host->power)) {
++		/* if(!regulator_is_enabled(host->power)) */
++		/* 	regulator_enable(host->power); */
++
++	} else if (host->pdata->gpio) {
++		set_pin_status(&host->pdata->gpio->pwr, 1);
++	}
++}
++
++static inline void ingenic_mmc_power_off(struct ingenic_mmc_host *host)
++{
++	dev_vdbg(host->dev, "power_off\n");
++
++	if (!IS_ERR(host->power)) {
++		/* if(regulator_is_enabled(host->power)) */
++		/* 	regulator_disable(host->power); */
++
++	} else if (host->pdata->gpio) {
++		set_pin_status(&host->pdata->gpio->pwr, 0);
++	}
++}
++
++static int ingenic_mmc_get_read_only(struct mmc_host *mmc)
++{
++	struct ingenic_mmc_host *host = mmc_priv(mmc);
++	int ret = 0;
++
++	dev_vdbg(host->dev, "get card ro\n");
++	if (host->pdata->gpio != NULL)
++		ret = get_pin_status(&host->pdata->gpio->wp);
++
++	return ret < 0? 0 : ret;
++}
++
++static int ingenic_mmc_get_card_detect(struct mmc_host *mmc)
++{
++	struct ingenic_mmc_host *host = mmc_priv(mmc);
++	int ret = -1;
++
++	dev_vdbg(host->dev, "get card present\n");
++	if ((host->pdata->removal == NONREMOVABLE)
++	    || (host->pdata->removal == MANUAL)) {
++		return test_bit(INGENIC_MMC_CARD_PRESENT, &host->flags);
++	}
++
++	if (host->pdata->gpio != NULL)
++		ret = get_pin_status(&host->pdata->gpio->cd);
++
++	return ret < 0? 1 : ret;
++}
++
++static void ingenic_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
++{
++	struct ingenic_mmc_host *host = mmc_priv(mmc);
++
++	/*
++	 * The max bus width is set in the platformdata->capacity,
++	 * MMC_CAP_4_BIT_DATA: Can the host do 4 bit transfers
++	 * MMC_CAP_8_BIT_DATA: Can the host do 8 bit transfers
++	 */
++
++	switch (ios->bus_width) {
++	case MMC_BUS_WIDTH_1:
++		host->cmdat_def &= ~CMDAT_BUS_WIDTH_MASK;
++		host->cmdat_def |= CMDAT_BUS_WIDTH_1BIT;
++		break;
++	case MMC_BUS_WIDTH_4:
++		host->cmdat_def &= ~CMDAT_BUS_WIDTH_MASK;
++		host->cmdat_def |= CMDAT_BUS_WIDTH_4BIT;
++		break;
++	case MMC_BUS_WIDTH_8:
++		host->cmdat_def &= ~CMDAT_BUS_WIDTH_MASK;
++		host->cmdat_def |= CMDAT_BUS_WIDTH_8BIT;
++		break;
++	}
++
++	if (ios->clock) {
++		unsigned int clk_set = 0, clkrt = 0;
++		unsigned int clk_want = ios->clock;
++		unsigned int lpm = 0;
++
++		ingenic_mmc_clk_onoff(host, 0);
++		if (clk_want > 3000000) {
++			clk_set_rate(host->clk_cgu, ios->clock);
++		} else {
++			clk_set_rate(host->clk_cgu, CLK_RATE);
++		}
++		/*clk_get_rate is permanently 24000000 on board_4785_fpga*/
++		clk_set = clk_get_rate(host->clk_cgu);
++
++		while (clk_want < clk_set) {
++			clkrt++;
++			clk_set >>= 1;
++		}
++		/* discard this warning on board 4785 fpga */
++		if ((clk_want > 3000000) && clkrt) {
++			dev_err(host->dev, "CLKRT must be set to 0 "
++					"when MSC works during normal r/w: "
++					"ios->clock=%d clk_want=%d "
++					"clk_set=%d clkrt=%X,\n",
++					ios->clock, clk_want, clk_set, clkrt);
++			WARN_ON(1);
++		}
++
++		if (clkrt > 7) {
++			dev_err(host->dev, "invalid value of CLKRT: "
++					"ios->clock=%d clk_want=%d "
++					"clk_set=%d clkrt=%X,\n",
++					ios->clock, clk_want, clk_set, clkrt);
++			WARN_ON(1);
++			return;
++		}
++		if (!clkrt)
++			dev_vdbg(host->dev, "clk_want: %u, clk_set: %luHz\n",
++					 ios->clock, clk_get_rate(host->clk_cgu));
++
++		ingenic_mmc_clk_onoff(host, 1);
++		msc_writel(host, CLKRT, clkrt);
++
++        /* sample immediately at clk rising edge */
++		if (clk_set > 25000000)
++			lpm = (0x2 << LPM_DRV_SEL_SHF);
++
++		if(host->pdata->sdio_clk) {
++			msc_writel(host, LPM, lpm);
++			msc_writel(host, CTRL, CTRL_CLOCK_START);
++		} else {
++			lpm |= LPM_LPM;
++			msc_writel(host, LPM, lpm);
++		}
++	}
++
++	switch (ios->power_mode) {
++	case MMC_POWER_ON:
++	case MMC_POWER_UP:
++		host->cmdat_def |= CMDAT_INIT;
++		set_bit(INGENIC_MMC_CARD_NEED_INIT, &host->flags);
++		ingenic_mmc_power_on(host);
++		break;
++	case MMC_POWER_OFF:
++		ingenic_mmc_power_off(host);
++		break;
++	default:
++		break;
++	}
++}
++
++static void ingenic_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
++{
++	struct ingenic_mmc_host *host = mmc_priv(mmc);
++
++	if (enable) {
++		enable_msc_irq(host, IMASK_SDIO);
++	} else {
++		clear_msc_irq(host, IFLG_SDIO);
++		disable_msc_irq(host, IMASK_SDIO);
++	}
++}
++
++static const struct mmc_host_ops ingenic_mmc_ops = {
++	.request		= ingenic_mmc_request,
++	.set_ios		= ingenic_mmc_set_ios,
++	.get_ro			= ingenic_mmc_get_read_only,
++	.get_cd			= ingenic_mmc_get_card_detect,
++	.enable_sdio_irq	= ingenic_mmc_enable_sdio_irq,
++};
++
++/*--------------------------End other mmc_ops------------------------------*/
++static ssize_t ingenic_mmc_present_show(struct device *dev,
++										struct device_attribute *attr,
++										char *buf)
++{
++	struct ingenic_mmc_host *host = dev_get_drvdata(dev);
++	ssize_t count = 0;
++
++	if (test_bit(INGENIC_MMC_CARD_PRESENT, &host->flags))
++		count = sprintf(buf, "Y\n");
++	else
++		count = sprintf(buf, "N\n");
++
++	return count;
++}
++
++static ssize_t ingenic_mmc_present_store(struct device *dev,
++										 struct device_attribute *attr,
++										 const char *buf, size_t count)
++{
++	struct ingenic_mmc_pdata *pdata = dev->platform_data;
++	struct ingenic_mmc_host *host = dev_get_drvdata(dev);
++
++	if ((buf == NULL) || (pdata->removal != NONREMOVABLE)) {
++		dev_err(host->dev, "can't set present\n");
++		return count;
++	}
++
++	if (strncmp(buf, "INSERT", 6) == 0) {
++		dev_info(host->dev, "card insert via sysfs\n");
++		set_bit(INGENIC_MMC_CARD_PRESENT, &host->flags);
++		mmc_detect_change(host->mmc, 0);
++
++	} else if (strncmp(buf, "REMOVE", 6) == 0) {
++		dev_info(host->dev, "card remove via sysfs\n");
++		clear_bit(INGENIC_MMC_CARD_PRESENT, &host->flags);
++		mmc_detect_change(host->mmc, 0);
++		ingenic_mmc_reset(host);
++
++	} else {
++		dev_err(host->dev, "set present error, "
++				"the argument can't be recognised\n");
++	}
++
++	return count;
++}
++
++static DEVICE_ATTR(present, S_IWUSR | S_IRUSR,
++				   ingenic_mmc_present_show, ingenic_mmc_present_store);
++
++static struct attribute *ingenic_mmc_attributes[] = {
++	&dev_attr_present.attr,
++	NULL
++};
++
++static const struct attribute_group ingenic_mmc_attr_group = {
++	.attrs = ingenic_mmc_attributes,
++};
++
++/*-------------------------End Sysfs interface-----------------------------*/
++
++/*
++ * Platform driver and initialization.
++ */
++static void __init ingenic_mmc_host_init(struct ingenic_mmc_host *host, struct mmc_host *mmc)
++{
++	struct ingenic_mmc_pdata *pdata = host->pdata;
++
++	mmc->ops = &ingenic_mmc_ops;
++	mmc->f_min = 200000;
++	mmc->ocr_avail = pdata->ocr_avail;
++	mmc->pm_flags |= pdata->pm_flags;
++#ifdef CONFIG_MMC_BLOCK_BOUNCE
++	mmc->max_blk_count = 65535;
++	mmc->max_req_size = PAGE_SIZE * 16;
++#else
++	mmc->max_segs = MAX_SEGS;
++	mmc->max_blk_count = 4096;
++	mmc->max_req_size = 4096 * 512;
++#endif
++	mmc->max_blk_size = 512;
++	mmc->max_seg_size = mmc->max_req_size;
++
++	host->mmc = mmc;
++	timer_setup(&host->request_timer, ingenic_mmc_request_timeout,0);
++
++	mmc_of_parse(mmc);
++
++	mmc_add_host(mmc);
++}
++
++static int __init ingenic_mmc_dma_init(struct ingenic_mmc_host *host)
++{
++	struct sdma_desc *next_desc;
++	unsigned char i = 0;
++	void *desc_mem;
++	void __iomem *desc;
++
++	desc_mem = (struct sdma_desc *)get_zeroed_page(GFP_KERNEL);
++	if (desc_mem == NULL) {
++		dev_err(host->dev, "get DMA descriptor memory error\n");
++		return -ENODEV;
++	}
++
++	desc = devm_ioremap(host->dev, virt_to_phys(desc_mem), PAGE_SIZE);
++	if (desc == NULL) {
++		dev_err(host->dev, "remap descriptor memory error\n");
++		kfree(desc_mem);
++		return -ENODEV;
++	}
++
++	host->decshds[0].dma_desc = (struct sdma_desc*)desc;
++	next_desc = host->decshds[0].dma_desc;
++
++	for (i = 0; i < MAX_SEGS; ++i) {
++		struct desc_hd *dhd = &host->decshds[i];
++		dhd->dma_desc = next_desc;
++		dhd->dma_desc_phys_addr = CPHYSADDR((unsigned long)dhd->dma_desc);
++		next_desc += 1;
++		dhd->next = dhd + 1;
++	}
++	host->decshds[MAX_SEGS - 1].next = NULL;
++	return 0;
++}
++
++static int __init ingenic_mmc_msc_init(struct ingenic_mmc_host *host)
++{
++	ingenic_mmc_reset(host);
++	host->cmdat_def = CMDAT_RTRG_EQUALT_16 | CMDAT_TTRG_LESS_16 |	\
++		CMDAT_BUS_WIDTH_1BIT;
++
++	return devm_request_threaded_irq(host->dev, host->irq, NULL,
++									ingenic_mmc_thread_handle, IRQF_ONESHOT, dev_name(host->dev), host);
++}
++static void ingenic_mmc_get_gpio(struct device_node *np,
++								 struct ingenic_mmc_pin *pin, char *gpioname)
++{
++	int gpio;
++	enum of_gpio_flags flags;
++
++	pin->num = -EBUSY;
++	gpio = of_get_named_gpio_flags(np, gpioname, 0, &flags);
++	if(gpio_is_valid(gpio)) {
++		pin->num = gpio;
++		pin->enable_level =
++			(flags == OF_GPIO_ACTIVE_LOW ? LOW_ENABLE : HIGH_ENABLE);
++	}
++	printk("mmc gpio %s num:%d en-level: %d\n",
++		   gpioname, pin->num, pin->enable_level);
++}
++static void ingenic_mmc_init_gpio(struct ingenic_mmc_pin *pin, char *gpioname, int dir)
++{
++	if(gpio_is_valid(pin->num)) {
++		if (gpio_request_one(pin->num, dir, gpioname)) {
++			pr_info("%s no detect pin available\n", gpioname);
++			pin->num = -EBUSY;
++		}
++	}
++}
++
++static int __init ingenic_mmc_gpio_init(struct ingenic_mmc_host *host)
++{
++	struct card_gpio *card_gpio = host->pdata->gpio;
++	int ret = 0, dir;
++
++	ingenic_mmc_init_gpio(&card_gpio->cd, "mmc_detect", GPIOF_DIR_IN);
++	ingenic_mmc_init_gpio(&card_gpio->wp, "mmc_wp", GPIOF_DIR_IN);
++	ingenic_mmc_init_gpio(&card_gpio->rst, "mmc_rst", GPIOF_DIR_OUT);
++	dir = card_gpio->pwr.enable_level ? GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH;
++	ingenic_mmc_init_gpio(&card_gpio->pwr, "mmc_pwr", dir);
++
++	switch (host->pdata->removal) {
++	case NONREMOVABLE:
++		break;
++	case REMOVABLE:
++		if (gpio_is_valid(card_gpio->cd.num)) {
++			timer_setup(&host->detect_timer, ingenic_mmc_detect,0);
++			ret = devm_request_irq(host->dev, gpio_to_irq(card_gpio->cd.num),
++								   ingenic_mmc_detect_handler,
++								   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
++								   "mmc-insert-detect", host);
++			if (ret) {
++				dev_err(host->dev, "request detect irq-%d fail\n",
++						gpio_to_irq(card_gpio->cd.num));
++				break;
++			}
++
++			if(!timer_pending(&host->detect_timer)){
++				disable_irq_nosync(gpio_to_irq(card_gpio->cd.num));
++				mod_timer(&host->detect_timer, jiffies);
++			}
++		} else {
++			dev_err(host->dev, "card-detect pin must be valid "
++					"when host->pdata->removal = 1, errno=%d\n",
++					card_gpio->cd.num);
++		}
++
++		break;
++	case MANUAL:
++		list_add(&(host->list), &manual_list);
++		break;
++	default:
++		set_bit(INGENIC_MMC_CARD_PRESENT, &host->flags);
++		break;
++	}
++
++	return ret;
++}
++
++static void ingenic_mmc_gpio_deinit(struct ingenic_mmc_host *host)
++{
++	struct card_gpio *card_gpio = host->pdata->gpio;
++
++	if (card_gpio) {
++		if(gpio_is_valid(card_gpio->cd.num)) {
++			gpio_free(card_gpio->cd.num);
++		}
++		if(gpio_is_valid(card_gpio->wp.num)) {
++			gpio_free(card_gpio->wp.num);
++		}
++		if(gpio_is_valid(card_gpio->pwr.num)) {
++			gpio_free(card_gpio->pwr.num);
++		}
++		if(gpio_is_valid(card_gpio->rst.num)) {
++			gpio_free(card_gpio->rst.num);
++		}
++	}
++}
++
++static void mmc_get_clk_name_v1(int id, char *cgu_name, char *gate_name)
++{
++	sprintf(cgu_name, "cgu_msc%d", id);
++	sprintf(gate_name, "gate_msc%d", id);
++}
++
++static void mmc_get_clk_name_v2(int id, char *cgu_name, char *gate_name)
++{
++	sprintf(cgu_name, "div_msc%d", id);
++	sprintf(gate_name, "gate_msc%d", id);
++}
++
++static struct ingenic_mmc_priv ingenic_mmc_priv = {
++	.get_clk_name = mmc_get_clk_name_v1,
++};
++
++static struct ingenic_mmc_priv x1600_mmc_priv = {
++	.get_clk_name = mmc_get_clk_name_v2,
++};
++
++static const struct of_device_id mmc_ingenic_of_match[] = {
++	{.compatible = "ingenic,mmc", .data = &ingenic_mmc_priv},
++	{.compatible = "ingenic,x1600-mmc", .data = &x1600_mmc_priv},
++	{},
++};
++MODULE_DEVICE_TABLE(of, mmc_ingenic_of_match);
++
++static struct ingenic_mmc_pdata *of_get_mmc_ingenic_pdata(struct device *dev)
++{
++	struct ingenic_mmc_pdata *pdata;
++	struct device_node *np = dev->of_node;
++	struct card_gpio *card_gpio;
++
++	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
++	if (!pdata)
++		return NULL; /* out of memory */
++
++	card_gpio = devm_kzalloc(dev, sizeof(struct card_gpio), GFP_KERNEL);
++	if(!card_gpio)
++		return NULL;
++	ingenic_mmc_get_gpio(np, &card_gpio->rst, "ingneic,rst-gpios");
++	ingenic_mmc_get_gpio(np, &card_gpio->wp, "ingneic,wp-gpios");
++	ingenic_mmc_get_gpio(np, &card_gpio->pwr, "ingneic,pwr-gpios");
++	ingenic_mmc_get_gpio(np, &card_gpio->cd, "ingneic,cd-gpios");
++	pdata->gpio = card_gpio;
++
++	if(of_property_read_bool(np, "pio-mode")) {
++		pdata->pio_mode = 1;
++	}
++
++	{
++		unsigned int val;
++		if(!(of_property_read_u32(np, "ingenic,sdio_clk", &val)))
++			pdata->sdio_clk = val;
++	}
++
++	if(of_property_read_bool(np, "ingenic,removal-dontcare")) {
++		pdata->removal = DONTCARE;
++	} else if(of_property_read_bool(np, "ingenic,removal-nonremovable")) {
++		pdata->removal = NONREMOVABLE;
++	} else if(of_property_read_bool(np, "ingenic,removal-removable")) {
++		pdata->removal = REMOVABLE;
++	} else if(of_property_read_bool(np, "ingenic,removal-manual")) {
++		pdata->removal = MANUAL;
++	};
++
++	mmc_of_parse_voltage(np, &pdata->ocr_avail);
++
++	return pdata;
++}
++
++static int mmc_ingenic_probe(struct platform_device *pdev)
++{
++	struct ingenic_mmc_pdata *pdata;
++	struct resource	*regs;
++	struct ingenic_mmc_host *host = NULL;
++	struct mmc_host *mmc;
++	struct ingenic_mmc_priv *priv;
++	struct of_device_id *of_device_id;
++	int ret = 0;
++	char clk_cgu_name[16];
++	char clk_gate_name[16];
++
++	pdata = of_get_mmc_ingenic_pdata(&pdev->dev);
++	if(IS_ERR(pdata)) {
++		dev_err(&pdev->dev, "Platform Data is missing!\n");
++		return PTR_ERR(pdata);
++	}
++	mmc = mmc_alloc_host(sizeof(struct ingenic_mmc_host), &pdev->dev);
++	if (!mmc)
++		return -ENOMEM;
++
++	host = mmc_priv(mmc);
++
++	of_device_id = of_match_node(mmc_ingenic_of_match, pdev->dev.of_node);
++	priv = of_device_id->data;
++
++
++	pdev->id = of_alias_get_id(pdev->dev.of_node, "mmc");
++	host->index = pdev->id;
++	priv->get_clk_name(host->index, clk_cgu_name, clk_gate_name);
++	host->clk_cgu = devm_clk_get(&pdev->dev, clk_cgu_name);
++	if(!host->clk_cgu) {
++		dev_err(&pdev->dev, "Failed to Get MSC clk!\n");
++		return PTR_ERR(host->clk_cgu);
++	}
++	host->clk_gate = devm_clk_get(&pdev->dev, clk_gate_name);
++	if(!host->clk_gate) {
++		dev_err(&pdev->dev, "Failed to Get PWC MSC clk!\n");
++		return PTR_ERR(host->clk_gate);
++	}
++
++	clk_set_rate(host->clk_cgu, CLK_RATE);
++	if(clk_get_rate(host->clk_cgu) > CLK_RATE) {
++		dev_err(&pdev->dev, "Failed to Set MSC clk %ld!\n", clk_get_rate(host->clk_cgu));
++		goto err_clk_get_rate;
++	}
++	ingenic_mmc_clk_onoff(host, 1);
++
++	host->dev = &pdev->dev;
++	host->pdata = pdata;
++
++	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!regs) {
++		dev_err(&pdev->dev, "No iomem resource\n");
++		return -ENXIO;
++	}
++	host->iomem = devm_ioremap_resource(&pdev->dev, regs);
++	if (!host->iomem)
++		goto err_ioremap;
++
++	host->irq = platform_get_irq(pdev, 0);
++	if (host->irq < 0) {
++		dev_err(&pdev->dev, "No irq resource\n");
++		return host->irq;
++	}
++
++	/* host->power = regulator_get(host->dev, "cpu_mem12"); */
++	/* if (IS_ERR(host->power)) { */
++	/* 	dev_warn(host->dev, "vmmc regulator missing\n"); */
++	/* } */
++	if (host->pdata->pio_mode)
++		set_bit(INGENIC_MMC_USE_PIO, &host->flags);
++
++	if (!test_bit(INGENIC_MMC_USE_PIO, &host->flags)) {
++		ret = ingenic_mmc_dma_init(host);
++		if (ret < 0)
++			goto err_dma_init;
++	}
++
++	spin_lock_init(&host->lock);
++	if (pdata->sdio_clk) {
++		ingenic_sdio_wlan_init(&pdev->dev, host->index);
++	}
++
++	ret = ingenic_mmc_msc_init(host);
++	if (ret < 0)
++		goto err_msc_init;
++
++	ingenic_mmc_host_init(host, mmc);
++
++	ret = ingenic_mmc_gpio_init(host);
++	if (ret < 0)
++		goto err_gpio_init;
++
++	ret = sysfs_create_group(&pdev->dev.kobj, &ingenic_mmc_attr_group);
++	if (ret < 0)
++		goto err_sysfs_create;
++
++	platform_set_drvdata(pdev, host);
++
++	dev_info(host->dev, "register success!\n");
++	return 0;
++
++err_sysfs_create:
++	ingenic_mmc_gpio_deinit(host);
++err_gpio_init:
++	free_irq(host->irq, host);
++err_msc_init:
++	devm_iounmap(&pdev->dev, (void __iomem *)host->decshds[0].dma_desc);
++err_dma_init:
++	devm_iounmap(&pdev->dev, host->iomem);
++err_ioremap:
++	mmc_free_host(mmc);
++	clk_disable_unprepare(host->clk_cgu);
++err_clk_get_rate:
++	clk_put(host->clk_cgu);
++	clk_put(host->clk_gate);
++	dev_err(host->dev, "mmc probe error\n");
++	return ret;
++}
++
++static int __exit mmc_ingenic_remove(struct platform_device *pdev)
++{
++	struct ingenic_mmc_host *host = platform_get_drvdata(pdev);
++
++	platform_set_drvdata(pdev, NULL);
++	mmc_remove_host(host->mmc);
++	mmc_free_host(host->mmc);
++	sysfs_remove_group(&pdev->dev.kobj, &ingenic_mmc_attr_group);
++
++	ingenic_mmc_power_off(host);
++	if (host->pdata->removal == REMOVABLE)
++		free_irq(gpio_to_irq(host->pdata->gpio->cd.num), host);
++
++	free_irq(host->irq, host);
++	ingenic_mmc_gpio_deinit(host);
++	devm_iounmap(&pdev->dev, (void __iomem *)host->decshds[0].dma_desc);
++	/* regulator_put(host->power); */
++	ingenic_mmc_clk_onoff(host, 0);
++
++	clk_put(host->clk_cgu);
++	clk_put(host->clk_gate);
++	iounmap(host->iomem);
++	kfree(host);
++
++	return 0;
++}
++
++static void mmc_ingenic_shutdown(struct platform_device *pdev)
++{
++	struct ingenic_mmc_host *host = platform_get_drvdata(pdev);
++	struct card_gpio *card_gpio = host->pdata->gpio;
++
++	/*
++	 * Remove host when shutdown to avoid illegal request,
++	 * but don't remove sdio_host in case of the SDIO device driver
++	 * can't handle bus remove correctly.
++	 */
++	dev_vdbg(host->dev, "shutdown\n");
++	if(host->mmc->card && !mmc_card_sdio(host->mmc->card)) {
++		if(gpio_is_valid(card_gpio->rst.num)) {
++			gpio_direction_output(card_gpio->rst.num, 0);
++		} else {
++			mmc_remove_host(host->mmc);
++		}
++	}
++
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int mmc_ingenic_suspend(struct device *dev)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	struct ingenic_mmc_host *host = platform_get_drvdata(pdev);
++	int ret = 0;
++
++	ingenic_mmc_clk_onoff(host, 0);
++	/* if (host->mmc->card && host->mmc->card->type != MMC_TYPE_SDIO) { */
++	/* 	ret = mmc_suspend_host(host->mmc); */
++	/* } */
++	return ret;
++}
++
++static int mmc_ingenic_resume(struct device *dev)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	struct ingenic_mmc_host *host = platform_get_drvdata(pdev);
++	int ret = 0;
++	ingenic_mmc_clk_onoff(host, 1);
++	/* if (host->mmc->card && host->mmc->card->type != MMC_TYPE_SDIO) { */
++	/* 	ret = mmc_resume_host(host->mmc); */
++	/* } */
++	return ret;
++}
++#else
++#define mmc_ingenic_suspend NULL
++#define mmc_ingenic_resume NULL
++#endif
++static SIMPLE_DEV_PM_OPS(mmc_ingenic_pm_ops, mmc_ingenic_suspend,
++						 mmc_ingenic_resume);
++
++static struct platform_driver mmc_ingenic_driver = {
++	.driver	= {
++		.name	= "ingenic,mmc",
++		.owner	= THIS_MODULE,
++		.pm	= &mmc_ingenic_pm_ops,
++		.of_match_table = of_match_ptr(mmc_ingenic_of_match),
++	},
++	.probe = mmc_ingenic_probe,
++	.remove = mmc_ingenic_remove,
++	.shutdown	= mmc_ingenic_shutdown,
++};
++
++module_platform_driver(mmc_ingenic_driver);
++
++MODULE_DESCRIPTION("Multimedia Card Interface driver, MMC version 1.2");
++MODULE_AUTHOR("bo.liu <bo.liu@ingenic.cn>");
++MODULE_LICENSE("GPL v2");
++MODULE_VERSION("20170222");
+diff --git a/module_drivers/drivers/mmc/host/ingenic_mmc.h b/module_drivers/drivers/mmc/host/ingenic_mmc.h
+new file mode 100644
+index 000000000..b8d0748f7
+--- /dev/null
++++ b/module_drivers/drivers/mmc/host/ingenic_mmc.h
+@@ -0,0 +1,158 @@
++#ifndef __INGENIC_MMC_H__
++#define __INGENIC_MMC_H__
++
++#include "ingenic_mmc_reg.h"
++#include <linux/interrupt.h>
++enum {
++	DONTCARE = 0,
++	NONREMOVABLE,
++	REMOVABLE,
++	MANUAL,
++};
++
++enum {
++	EVENT_CMD_COMPLETE = 0,
++	EVENT_TRANS_COMPLETE,
++	EVENT_DMA_COMPLETE,
++	EVENT_DATA_COMPLETE,
++	EVENT_STOP_COMPLETE,
++	EVENT_ERROR,
++};
++
++enum ingenic_mmc_state {
++	STATE_IDLE = 0,
++	STATE_WAITING_RESP,
++	STATE_WAITING_DATA,
++	STATE_SENDING_STOP,
++	STATE_ERROR,
++};
++
++struct sdma_desc {
++	volatile u32 nda;
++	volatile u32 da;
++	volatile u32 len;
++	volatile u32 dcmd;
++};
++
++struct desc_hd {
++	struct sdma_desc *dma_desc;
++	dma_addr_t dma_desc_phys_addr;
++	struct desc_hd *next;
++};
++
++#define LOW_ENABLE			0
++#define HIGH_ENABLE			1
++struct ingenic_mmc_pin {
++	short				num;
++	short 				enable_level;
++};
++
++struct card_gpio {
++	struct ingenic_mmc_pin 		wp;
++	struct ingenic_mmc_pin 		cd;
++	struct ingenic_mmc_pin 		pwr;
++	struct ingenic_mmc_pin 		rst;
++};
++
++/**
++ * struct ingenic_mmc_platform_data is a struct which defines board MSC informations
++ * @removal: This shows the card slot's type:
++ *	REMOVABLE/IRREMOVABLE/MANUAL (Tablet card/Phone card/build-in SDIO).
++ * @sdio_clk: SDIO device's clock can't use Low-Power-Mode.
++ * @ocr_mask: This one shows the voltage that host provide.
++ * @capacity: Shows the host's speed capacity and bus width.
++ * @max_freq: The max freqency of mmc host.
++ *
++ * @recovery_info: Informations that Android recovery mode uses.
++ * @gpio: Slot's gpio information including pins of write-protect, card-detect and power.
++ * @pio_mode: Indicate that whether the MSC host use PIO mode.
++ * @private_init: Board private initial function, mostly for SDIO devices.
++ */
++struct ingenic_mmc_pdata {
++	unsigned short			removal;
++	unsigned short			sdio_clk;
++	unsigned int			ocr_avail;
++	unsigned int			capacity;
++	unsigned int			pm_flags;
++	struct card_gpio		*gpio;
++	unsigned int			pio_mode;
++	int				(*private_init)(void);
++};
++
++/**
++ * struct ingenic_mmc_host - Ingenic MMC/SD Controller host structure
++ * @pdata: The platform data.
++ * @dev: The mmc device pointer.
++ * @irq: Interrupt of MSC.
++ * @clk: Main Clk of MSC, including cgu and clk gate.
++ * @pwc_clk: Power of MSC module, MSC register can be access when pwc_clk on.
++ * @power: Power regulator of SD/MMC attached to SD slot.
++ * @mrq: mmc_request pointer which includes all the information
++ *	of the current request, or NULL when the host is idle.
++ * @cmd: Command information of mmc_request.
++ * @data: Data information of mmc_request, or NULL when mrq without
++ *	data request.
++ * @mmc: The mmc_host representing this slot.
++ * @pending_events: Bitmask of events flagged by the interrupt handler
++ *	to be processed by the state machine.
++ * @iomem: Pointer to MSC registers.
++ * @detect_timer: Timer used for debouncing card insert interrupts.
++ * @request_timer: Timer used for preventing request time out.
++ * @flags: Random state bits associated with the slot.
++ * @cmdat: Variable for MSC_CMDAT register.
++ * @cmdat_def: Defalt CMDAT register value for every request.
++ * @gpio: Information of gpio including cd, wp and pwr.
++ * @index: Number of each MSC host.
++ * @decshds[]: Descriptor DMA information structure.
++ * @state: It's the state for request.
++ * @list: List head for manually detect card such as wifi.
++ * @lock: Lock the registers operation.
++ * @double_enter: Prevent state machine reenter.
++ * @timeout_cnt: The count of timeout second.
++ */
++#define MAX_SEGS		128	/* max count of sg */
++#define INGENIC_MMC_CARD_PRESENT	0
++#define INGENIC_MMC_CARD_NEED_INIT	1
++#define INGENIC_MMC_USE_PIO		2
++
++struct ingenic_mmc_host {
++	void __iomem				*iomem;
++	struct device				*dev;
++	struct clk					*clk_cgu;
++	struct clk					*clk_gate;
++	struct regulator			*power;
++	struct mmc_request			*mrq;
++	struct mmc_command			*cmd;
++	struct mmc_data				*data;
++	struct mmc_host				*mmc;
++	struct timer_list			 detect_timer;
++	struct timer_list			 request_timer;
++	struct tasklet_struct		 tasklet;
++	struct list_head			 list;
++	struct ingenic_mmc_pdata	*pdata;
++	struct desc_hd				 decshds[MAX_SEGS];
++	enum ingenic_mmc_state		 state;
++	spinlock_t					 lock;
++	unsigned long				 pending_events;
++	unsigned long				 flags;
++	unsigned int				 cmdat;
++	unsigned int				 cmdat_def;
++	unsigned int				 index;
++	unsigned int				 double_enter;
++	int							 timeout_cnt;
++	int							 irq;
++};
++
++struct ingenic_mmc_priv {
++	void (*get_clk_name)(int id, char *cgu_name, char *gate_name);
++};
++
++/* Register access macros */
++#define msc_readl(port,reg)						\
++	__raw_readl((port)->iomem + MSC_##reg)
++#define msc_writel(port,reg,value)				\
++	__raw_writel((value), (port)->iomem + MSC_##reg)
++int ingenic_sdio_wlan_init(struct device *dev, int index);
++int ingenic_mmc_clk_ctrl(int index, int on);
++int ingenic_mmc_manual_detect(int index, int on);
++#endif /* __INGENIC_MMC_H__ */
+diff --git a/module_drivers/drivers/mmc/host/ingenic_mmc_reg.h b/module_drivers/drivers/mmc/host/ingenic_mmc_reg.h
+new file mode 100644
+index 000000000..5068fb431
+--- /dev/null
++++ b/module_drivers/drivers/mmc/host/ingenic_mmc_reg.h
+@@ -0,0 +1,232 @@
++#ifndef __INGENIC_MMC_REG_H__
++#define __INGENIC_MMC_REG_H__
++#define MMC_BOOT_AREA_PROTECTED		(0x1234)	/* Can not modified the area protected */
++#define MMC_BOOT_AREA_OPENED		(0x4321)	/* Can modified the area protected */
++
++#define	MSC_CTRL			0x000
++#define	MSC_STAT			0x004
++#define	MSC_CLKRT			0x008
++#define	MSC_CMDAT			0x00C
++#define	MSC_RESTO			0x010
++#define	MSC_RDTO			0x014
++#define	MSC_BLKLEN			0x018
++#define	MSC_NOB				0x01C
++#define	MSC_SNOB			0x020
++#define	MSC_IMASK			0x024
++#define	MSC_IFLG			0x028
++#define	MSC_CMD				0x02C
++#define	MSC_ARG				0x030
++#define	MSC_RES				0x034
++#define	MSC_RXFIFO			0x038
++#define	MSC_TXFIFO			0x03C
++#define	MSC_LPM				0x040
++#define	MSC_DMAC			0x044
++#define	MSC_DMANDA			0x048
++#define	MSC_DMADA			0x04C
++#define	MSC_DMALEN			0x050
++#define	MSC_DMACMD			0x054
++#define	MSC_CTRL2			0x058
++#define	MSC_RTCNT			0x05C
++#define	MSC_DEBUG			0x0FC
++
++/* MSC Clock and Control Register (MSC_CTRL) */
++#define CTRL_SEND_CCSD			(1 << 15)		/*send command completion signal disable to ceata */
++#define CTRL_SEND_AS_CCSD		(1 << 14)		/*send internally generated stop after sending ccsd */
++#define CTRL_EXIT_MULTIPLE		(1 << 7)
++#define CTRL_EXIT_TRANSFER		(1 << 6)
++#define CTRL_START_READWAIT		(1 << 5)
++#define CTRL_STOP_READWAIT		(1 << 4)
++#define CTRL_RESET				(1 << 3)
++#define CTRL_START_OP			(1 << 2)
++#define CTRL_CLOCK_SHF			0
++#define CTRL_CLOCK_MASK			(0x3 << CTRL_CLOCK_SHF)
++#define CTRL_CLOCK_STOP			(0x1 << CTRL_CLOCK_SHF)	/* Stop MMC/SD clock */
++#define CTRL_CLOCK_START		(0x2 << CTRL_CLOCK_SHF)	/* Start MMC/SD clock */
++
++/* MSC Control 2 Register (MSC_CTRL2) */
++#define	CTRL2_PIP_SHF			24
++#define	CTRL2_PIP_MASK			(0x1f << CTRL2_PIP_SHF)
++#define	CTRL2_RST_EN			(1 << 23)
++#define	CTRL2_STPRM				(1 << 4)
++#define	CTRL2_SVC				(1 << 3)
++#define	CTRL2_SMS_SHF			0
++#define	CTRL2_SMS_MASK			(0x7 << CTRL2_SMS_SHF)
++#define	CTRL2_SMS_DEFSPD		(0x0 << CTRL2_SMS_SHF)
++#define	CTRL2_SMS_HISPD			(0x1 << CTRL2_SMS_SHF)
++#define	CTRL2_SMS_SDR12			(0x2 << CTRL2_SMS_SHF)
++#define	CTRL2_SMS_SDR25			(0x3 << CTRL2_SMS_SHF)
++#define	CTRL2_SMS_SDR50			(0x4 << CTRL2_SMS_SHF)
++
++/* MSC Status Register (MSC_STAT) */
++#define STAT_AUTO_CMD12_DONE			(1 << 31)
++#define STAT_AUTO_CMD23_DONE			(1 << 30)
++#define STAT_SVS						(1 << 29)
++#define STAT_PIN_LEVEL_SHF				24
++#define STAT_PIN_LEVEL_MASK				(0x1f << STAT_PIN_LEVEL_SHF)
++#define STAT_BCE						(1 << 20)
++#define STAT_BDE						(1 << 19)
++#define STAT_BAE						(1 << 18)
++#define STAT_BAR						(1 << 17)
++#define STAT_IS_RESETTING				(1 << 15)
++#define STAT_SDIO_INT_ACTIVE			(1 << 14)
++#define STAT_PRG_DONE					(1 << 13)
++#define STAT_DATA_TRAN_DONE				(1 << 12)
++#define STAT_END_CMD_RES				(1 << 11)
++#define STAT_DATA_FIFO_AFULL			(1 << 10)
++#define STAT_IS_READWAIT				(1 << 9)
++#define STAT_CLK_EN						(1 << 8)
++#define STAT_DATA_FIFO_FULL				(1 << 7)
++#define STAT_DATA_FIFO_EMPTY			(1 << 6)
++#define STAT_CRC_RES_ERR				(1 << 5)
++#define STAT_CRC_READ_ERROR				(1 << 4)
++#define STAT_CRC_WRITE_ERROR_SHF		2
++#define STAT_CRC_WRITE_ERROR_MASK		(0x3 << STAT_CRC_WRITE_ERROR_SHF)
++#define STAT_CRC_WRITE_ERROR_NO			(0 << STAT_CRC_WRITE_ERROR_SHF)
++#define STAT_CRC_WRITE_ERROR			(1 << STAT_CRC_WRITE_ERROR_SHF)
++#define STAT_CRC_WRITE_ERROR_NOSTS		(2 << STAT_CRC_WRITE_ERROR_SHF)
++#define STAT_TIME_OUT_RES				(1 << 1)
++#define STAT_TIME_OUT_READ				(1 << 0)
++
++/* MSC Bus Clock Control Register (MSC_CLKRT) */
++#define	CLKRT_CLK_RATE_SHF		0
++#define	CLKRT_CLK_RATE_MASK		(0x7 << CLKRT_CLK_RATE_SHF)
++#define CLKRT_CLK_RATE_DIV_1	(0x0 << CLKRT_CLK_RATE_SHF)		/* CLK_SRC */
++#define CLKRT_CLK_RATE_DIV_2	(0x1 << CLKRT_CLK_RATE_SHF)		/* 1/2 of CLK_SRC */
++#define CLKRT_CLK_RATE_DIV_4	(0x2 << CLKRT_CLK_RATE_SHF)		/* 1/4 of CLK_SRC */
++#define CLKRT_CLK_RATE_DIV_8	(0x3 << CLKRT_CLK_RATE_SHF)		/* 1/8 of CLK_SRC */
++#define CLKRT_CLK_RATE_DIV_16	(0x4 << CLKRT_CLK_RATE_SHF)		/* 1/16 of CLK_SRC */
++#define CLKRT_CLK_RATE_DIV_32	(0x5 << CLKRT_CLK_RATE_SHF)		/* 1/32 of CLK_SRC */
++#define CLKRT_CLK_RATE_DIV_64	(0x6 << CLKRT_CLK_RATE_SHF)		/* 1/64 of CLK_SRC */
++#define CLKRT_CLK_RATE_DIV_128	(0x7 << CLKRT_CLK_RATE_SHF)		/* 1/128 of CLK_SRC */
++
++/* MSC Command Sequence Control Register (MSC_CMDAT) */
++#define	CMDAT_CCS_EXPECTED		(1 << 31)		/* interrupts are enabled in ce-ata */
++#define	CMDAT_READ_CEATA		(1 << 30)
++#define	CMDAT_DIS_BOOT			(1 << 27)
++#define	CMDAT_ENB_BOOT			(1 << 26)
++#define	CMDAT_EXP_BOOT_ACK		(1 << 25)
++#define	CMDAT_BOOT_MODE			(1 << 24)
++#define	CMDAT_AUTO_CMD23		(1 << 18)
++#define	CMDAT_SDIO_PRDT			(1 << 17)		/* exact 2 cycle */
++#define	CMDAT_AUTO_CMD12		(1 << 16)
++#define	CMDAT_RTRG_SHF			14
++#define CMDAT_RTRG_EQUALT_16	(0x0 << CMDAT_RTRG_SHF)	/*reset value*/
++#define CMDAT_RTRG_EQUALT_32	(0x1 << CMDAT_RTRG_SHF)
++#define CMDAT_RTRG_EQUALT_64	(0x2 << CMDAT_RTRG_SHF)
++#define CMDAT_RTRG_EQUALT_96	(0x3 << CMDAT_RTRG_SHF)
++#define	CMDAT_TTRG_SHF			12
++#define CMDAT_TTRG_LESS_16		(0x0 << CMDAT_TTRG_SHF)	/*reset value*/
++#define CMDAT_TTRG_LESS_32		(0x1 << CMDAT_TTRG_SHF)
++#define CMDAT_TTRG_LESS_64		(0x2 << CMDAT_TTRG_SHF)
++#define CMDAT_TTRG_LESS_96		(0x3 << CMDAT_TTRG_SHF)
++#define	CMDAT_IO_ABORT			(1 << 11)
++#define	CMDAT_BUS_WIDTH_SHF		9
++#define	CMDAT_BUS_WIDTH_MASK	(0x3 << CMDAT_BUS_WIDTH_SHF)
++#define CMDAT_BUS_WIDTH_1BIT	(0x0 << CMDAT_BUS_WIDTH_SHF)	/* 1-bit data bus */
++#define CMDAT_BUS_WIDTH_4BIT	(0x2 << CMDAT_BUS_WIDTH_SHF)	/* 4-bit data bus */
++#define CMDAT_BUS_WIDTH_8BIT	(0x3 << CMDAT_BUS_WIDTH_SHF)	/* 8-bit data bus */
++#define	CMDAT_INIT				(1 << 7)
++#define	CMDAT_BUSY				(1 << 6)
++#define	CMDAT_STREAM_BLOCK		(1 << 5)
++#define	CMDAT_WRITE_READ		(1 << 4)
++#define	CMDAT_DATA_EN			(1 << 3)
++#define	CMDAT_RESPONSE_SHF		0
++#define	CMDAT_RESPONSE_MASK		(0x7 << CMDAT_RESPONSE_SHF)
++#define CMDAT_RESPONSE_NONE 	(0x0 << CMDAT_RESPONSE_SHF)		/* No response */
++#define CMDAT_RESPONSE_R1		(0x1 << CMDAT_RESPONSE_SHF)		/* Format R1 and R1b */
++#define CMDAT_RESPONSE_R2	  	(0x2 << CMDAT_RESPONSE_SHF)		/* Format R2 */
++#define CMDAT_RESPONSE_R3	  	(0x3 << CMDAT_RESPONSE_SHF)		/* Format R3 */
++#define CMDAT_RESPONSE_R4	  	(0x4 << CMDAT_RESPONSE_SHF)		/* Format R4 */
++#define CMDAT_RESPONSE_R5	  	(0x5 << CMDAT_RESPONSE_SHF)		/* Format R5 */
++#define CMDAT_RESPONSE_R6	  	(0x6 << CMDAT_RESPONSE_SHF)		/* Format R6 */
++#define CMDAT_RESRONSE_R7		(0x7 << CMDAT_RESPONSE_SHF)		/* Format R7 */
++
++/* MSC Interrupts Mask Register (MSC_IMASK) */
++#define	IMASK_DMA_DATA_DONE		(1 << 31)
++#define	IMASK_WR_ALL_DONE		(1 << 23)
++#define	IMASK_AUTO_CMD23_DONE	(1 << 30)
++#define	IMASK_SVS				(1 << 29)
++#define	IMASK_PIN_LEVEL_SHF		24
++#define	IMASK_PIN_LEVEL_MASK	(0x1f << IMASK_PIN_LEVEL_SHF)
++#define	IMASK_BCE				(1 << 20)
++#define	IMASK_BDE				(1 << 19)
++#define	IMASK_BAE				(1 << 18)
++#define	IMASK_BAR				(1 << 17)
++#define	IMASK_DMAEND			(1 << 16)
++#define	IMASK_AUTO_CMD12_DONE	(1 << 15)
++#define	IMASK_DATA_FIFO_FULL	(1 << 14)
++#define	IMASK_DATA_FIFO_EMP		(1 << 13)
++#define	IMASK_CRC_RES_ERR		(1 << 12)
++#define	IMASK_CRC_READ_ERR		(1 << 11)
++#define	IMASK_CRC_WRITE_ERR		(1 << 10)
++#define	IMASK_TIME_OUT_RES		(1 << 9)
++#define	IMASK_TIME_OUT_READ		(1 << 8)
++#define	IMASK_SDIO				(1 << 7)
++#define	IMASK_TXFIFO_WR_REQ		(1 << 6)
++#define	IMASK_RXFIFO_RD_REQ		(1 << 5)
++#define	IMASK_END_CMD_RES		(1 << 2)
++#define	IMASK_PRG_DONE			(1 << 1)
++#define	IMASK_DATA_TRAN_DONE	(1 << 0)
++
++/* MSC Interrupts Status Register (MSC_IREG) */
++#define	IFLG_DMA_DATA_DONE		(1 << 31)
++#define	IFLG_WR_ALL_DONE		(1 << 23)
++#define	IFLG_AUTO_CMD23_DONE	(1 << 30)
++#define	IFLG_SVS				(1 << 29)
++#define	IFLG_PIN_LEVEL_SHF		24
++#define	IFLG_PIN_LEVEL_MASK		(0x1f << IFLG_PIN_LEVEL_SHF)
++#define	IFLG_BCE				(1 << 20)
++#define	IFLG_BDE				(1 << 19)
++#define	IFLG_BAE				(1 << 18)
++#define	IFLG_BAR				(1 << 17)
++#define	IFLG_DMAEND				(1 << 16)
++#define	IFLG_AUTO_CMD12_DONE	(1 << 15)
++#define	IFLG_DATA_FIFO_FULL		(1 << 14)
++#define	IFLG_DATA_FIFO_EMP		(1 << 13)
++#define	IFLG_CRC_RES_ERR		(1 << 12)
++#define	IFLG_CRC_READ_ERR		(1 << 11)
++#define	IFLG_CRC_WRITE_ERR		(1 << 10)
++#define	IFLG_TIMEOUT_RES		(1 << 9)
++#define	IFLG_TIMEOUT_READ		(1 << 8)
++#define	IFLG_SDIO				(1 << 7)
++#define	IFLG_TXFIFO_WR_REQ		(1 << 6)
++#define	IFLG_RXFIFO_RD_REQ		(1 << 5)
++#define	IFLG_END_CMD_RES		(1 << 2)
++#define	IFLG_PRG_DONE			(1 << 1)
++#define	IFLG_DATA_TRAN_DONE		(1 << 0)
++
++/* MSC Low Power Mode Register (MSC_LPM) */
++#define	LPM_DRV_SEL_SHF			30
++#define	LPM_DRV_SEL_MASK		(0x3 << LPM_DRV_SEL_SHF)
++#define	LPM_SMP_SEL				(1 << 29)
++#define	LPM_LPM					(1 << 0)
++
++/* MSC DMA Control Register (MSC_DMAC) */
++#define	DMAC_MODE_SEL	(1 << 7)
++#define	DMAC_AOFST_SHF	5
++#define	DMAC_AOFST_MASK	(0x3 << DMAC_AOFST_SHF)
++#define	DMAC_AOFST_0	(0 << DMAC_AOFST_SHF)
++#define	DMAC_AOFST_1	(1 << DMAC_AOFST_SHF)
++#define	DMAC_AOFST_2	(2 << DMAC_AOFST_SHF)
++#define	DMAC_AOFST_3	(3 << DMAC_AOFST_SHF)
++#define	DMAC_ALIGNEN	(1 << 4)
++#define	DMAC_INCR_SHF	2
++#define	DMAC_INCR_MASK	(0x3 << DMAC_INCR_SHF)
++#define	DMAC_INCR_16	(0 << DMAC_INCR_SHF)
++#define	DMAC_INCR_32	(1 << DMAC_INCR_SHF)
++#define	DMAC_INCR_64	(2 << DMAC_INCR_SHF)
++#define	DMAC_DMASEL		(1 << 1)
++#define	DMAC_DMAEN		(1 << 0)
++
++/* MSC DMA Command Register (MSC_DMACMD) */
++#define	DMACMD_IDI_SHF			24
++#define	DMACMD_IDI_MASK			(0xff << DMACMD_IDI_SHF)
++#define	DMACMD_ID_SHF			16
++#define	DMACMD_ID_MASK			(0xff << DMACMD_ID_SHF)
++#define	DMACMD_OFFSET_SHF		9
++#define	DMACMD_OFFSET_MASK		(0x3 << DMACMD_OFFSET_SHF)
++#define	DMACMD_ALIGN_EN			(1 << 8)
++#define	DMACMD_ENDI				(1 << 1)
++#define	DMACMD_LINK				(1 << 0)
++
++#endif	/* __INGENIC_MMC_REG_H__ */
+diff --git a/module_drivers/drivers/mmc/host/ingenic_sdio.c b/module_drivers/drivers/mmc/host/ingenic_sdio.c
+new file mode 100644
+index 000000000..c60d6d6b8
+--- /dev/null
++++ b/module_drivers/drivers/mmc/host/ingenic_sdio.c
+@@ -0,0 +1,275 @@
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/kernel.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/card.h>
++#include <linux/mmc/mmc.h>
++#include <linux/mmc/sd.h>
++#include <linux/mmc/sdio.h>
++#include <linux/scatterlist.h>
++#include <linux/dma-mapping.h>
++
++#include <linux/fs.h>
++#include <asm/uaccess.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/err.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/stat.h>
++
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/of_platform.h>
++#include <linux/of_gpio.h>
++#include<linux/regulator/consumer.h>
++
++#if (defined(CONFIG_INGENIC_MMC_MMC0) || defined(CONFIG_INGENIC_MMC_MMC1))
++#include "ingenic_mmc.h"
++#else
++#include "sdhci-ingenic.h"
++#endif
++
++struct wifi_data {
++	int sdio_index;
++	/* struct wake_lock                wifi_wake_lock; */
++	/* struct regulator                *wifi_vbat; */
++	/* struct regulator                *wifi_vddio; */
++	uint         wifi_reset;
++	uint         wifi_reset_flags;
++	uint         wifi_irq;
++	uint         wifi_irq_flags;
++	struct pinctrl *pctrl;
++	atomic_t rtc32k_ref;
++	struct regulator *wlreg_on;
++	struct regulator *wl_vccio;
++	struct clk *clk;
++};
++
++#define RESET  0
++#define NORMAL 1
++
++struct wifi_data wifi_data;
++static void rtc32k_init(struct device *dev, struct wifi_data *wdata)
++{
++	atomic_set(&wdata->rtc32k_ref, 0);
++	wdata->pctrl = NULL;
++	wdata->clk = NULL;
++#ifdef CONFIG_RTC_DRV_PCF8563
++	{
++		struct of_phandle_args phandle;
++		phandle.np = of_find_compatible_node(NULL, NULL, "nxp,pcf8563");
++		if (phandle.np) {
++			wdata->clk = of_clk_get_from_provider(&phandle);
++		}
++	}
++#else
++	wdata->pctrl = devm_pinctrl_get(dev);
++#endif
++}
++void rtc32k_enable(void)
++{
++
++	if (atomic_inc_return(&wifi_data.rtc32k_ref) == 1) {
++		if(wifi_data.clk)
++		{
++			printk("@@ rtc.pcf8563 %s @@\n", __func__);
++			clk_prepare_enable(wifi_data.clk);
++		}
++		if(wifi_data.pctrl)
++		{
++			struct pinctrl_state *state = NULL;
++			struct pinctrl *p = wifi_data.pctrl;
++			state = pinctrl_lookup_state(p, "enable");
++			if (!IS_ERR_OR_NULL(state)) {
++				pinctrl_select_state(p, state);
++			}
++		}
++	}
++}
++EXPORT_SYMBOL(rtc32k_enable);
++void rtc32k_disable(void)
++{
++	if (atomic_dec_return(&wifi_data.rtc32k_ref) == 0) {
++		if(wifi_data.clk){
++			printk("@@ rtc.pcf8563 %s @@\n", __func__);
++			clk_disable_unprepare(wifi_data.clk);
++		}
++		if(wifi_data.pctrl) {
++			struct pinctrl_state *state = NULL;
++			struct pinctrl *p = wifi_data.pctrl;
++			state = pinctrl_lookup_state(p, "disable");
++			if (!IS_ERR_OR_NULL(state)) {
++				pinctrl_select_state(p, state);
++			}
++		}
++	}
++}
++EXPORT_SYMBOL(rtc32k_disable);
++static const struct of_device_id wlan_ingenic_of_match[] = {
++	{.compatible = "android,bcmdhd_wlan"},
++	{.compatible = "rtk,rtl8723ds_wlan"},
++	{},
++};
++
++int wlan_regulator_get(struct device *dev)
++{
++	int ret;
++
++	wifi_data.wlreg_on= devm_regulator_get(dev, "wlreg_on");
++
++	if (IS_ERR(wifi_data.wlreg_on)) {
++	printk("wlreg_on is error %s, %s, %d\n", __FILE__, __func__, __LINE__);
++		if (PTR_ERR(wifi_data.wlreg_on) == -EPROBE_DEFER) {
++			return -EPROBE_DEFER;
++		}
++	}
++
++	if (!IS_ERR(wifi_data.wlreg_on)) {
++		ret = regulator_enable(wifi_data.wlreg_on);
++		if (ret) {
++			dev_err(dev, "wlreg_on enable failed\n");
++			return ret;
++		}
++	} else {
++		dev_err(dev, "wlreg_on is invalid\n");
++	}
++
++	wifi_data.wl_vccio = devm_regulator_get(dev, "wl_vccio");
++
++	if (IS_ERR(wifi_data.wl_vccio)) {
++		printk("wl_vccio is error %s, %s, %d\n", __FILE__, __func__, __LINE__);
++		if (PTR_ERR(wifi_data.wl_vccio) == -EPROBE_DEFER) {
++			return -EPROBE_DEFER;
++		}
++	}
++
++	if (!IS_ERR(wifi_data.wl_vccio)) {
++		ret = regulator_enable(wifi_data.wl_vccio);
++		if (ret) {
++			dev_err(dev, "wl_vccio enable failed\n");
++			return ret;
++		}
++	} else {
++		dev_err(dev, "wl_vccio is invalid\n");
++	}
++
++	return 0;
++}
++
++int ingenic_sdio_wlan_init(struct device *dev, int index)
++{
++	struct device_node *np = dev->of_node, *cnp;
++	unsigned int flags, gpio;
++
++	for_each_child_of_node(np, cnp) {
++		if(of_device_is_compatible(cnp, "android,bcmdhd_wlan")) {
++			printk("----android,bcmdhd_wlan!\n");
++			wifi_data.wifi_reset = of_get_named_gpio_flags(cnp, "ingenic,sdio-reset", 0, &flags);
++			wifi_data.wifi_reset_flags = flags;
++			wifi_data.wifi_irq = of_get_named_gpio_flags(cnp, "ingenic,sdio-irq", 0, &flags);
++			wifi_data.wifi_irq_flags = flags;
++		}
++		if(of_device_is_compatible(cnp, "rtk,rtl8723ds_wlan")) {
++			printk("----rtk,rtl8723ds_wlan\n");
++			wifi_data.wifi_reset = of_get_named_gpio_flags(cnp, "ingenic,sdio-reset", 0, &flags);
++			wifi_data.wifi_reset_flags = flags;
++			wifi_data.wifi_irq = of_get_named_gpio_flags(cnp, "ingenic,sdio-irq", 0, &flags);
++			wifi_data.wifi_irq_flags = flags;
++		}
++	}
++
++  wlan_regulator_get(dev);
++
++	rtc32k_init(dev, &wifi_data);
++
++	gpio = wifi_data.wifi_reset;
++	if (devm_gpio_request(dev, gpio, "wifi_reset")) {
++		printk("ERROR: no wifi_reset pin available !!\n");
++		return -EINVAL;
++	} else {
++		gpio_direction_output(gpio, !wifi_data.wifi_reset_flags);
++	}
++	wifi_data.wifi_reset = gpio;
++	wifi_data.sdio_index = index;
++
++	return 0;
++}
++EXPORT_SYMBOL(ingenic_sdio_wlan_init);
++
++int ingenic_sdio_wlan_get_irq(unsigned long *flag)
++{
++	*flag = wifi_data.wifi_irq_flags;
++	return wifi_data.wifi_irq;
++}
++EXPORT_SYMBOL(ingenic_sdio_wlan_get_irq);
++int ingenic_sdio_wlan_power_onoff(int onoff, int flag)
++{
++	int err = 0;
++	int reset = wifi_data.wifi_reset;
++	if(!reset)
++		return -EINVAL;
++	if(onoff) {
++		printk("reset %d wlan power on:%d\n", reset, flag);
++		if (!IS_ERR(wifi_data.wlreg_on)) {
++			err = regulator_enable(wifi_data.wlreg_on);
++			if (err) {
++				printk("wifi_data.wlreg_on enable failed\n");
++				return err;
++			}
++		}
++		if (!IS_ERR(wifi_data.wl_vccio)) {
++			err = regulator_enable(wifi_data.wl_vccio);
++			if (err) {
++				printk("wifi_data.wl_vccio enable failed\n");
++				return err;
++			}
++		}
++		rtc32k_enable();
++		switch(flag) {
++		case RESET:
++			ingenic_mmc_clk_ctrl(wifi_data.sdio_index, 1);
++			gpio_set_value(reset, 0);
++			msleep(10);
++			gpio_set_value(reset, 1);
++			break;
++		case NORMAL:
++			gpio_set_value(reset, 1);
++			ingenic_mmc_manual_detect(wifi_data.sdio_index, 1);
++			break;
++		}
++	} else {
++		printk("wlan power off:%d\n", flag);
++		switch(flag) {
++		case RESET:
++			gpio_set_value(reset, 0);
++			break;
++		case NORMAL:
++			gpio_set_value(reset, 0);
++			break;
++		}
++		rtc32k_disable();
++		if (!IS_ERR(wifi_data.wlreg_on)) {
++			err = regulator_disable(wifi_data.wlreg_on);
++			if (err) {
++				printk("wifi_data.wlreg_on disable failed\n");
++				return err;
++			}
++		}
++		if (!IS_ERR(wifi_data.wl_vccio)) {
++			err = regulator_disable(wifi_data.wl_vccio);
++			if (err) {
++				printk("wifi_data.wl_vccio disable failed\n");
++				return err;
++			}
++		}
++	}
++	if (err < 0) {
++		printk("%s: regulator enable/disable failed", __FUNCTION__);
++		return -1;
++	}
++	return 0;
++
++}
++EXPORT_SYMBOL(ingenic_sdio_wlan_power_onoff);
+diff --git a/module_drivers/drivers/mmc/host/sdhci-ingenic.c b/module_drivers/drivers/mmc/host/sdhci-ingenic.c
+new file mode 100644
+index 000000000..b917ea769
+--- /dev/null
++++ b/module_drivers/drivers/mmc/host/sdhci-ingenic.c
+@@ -0,0 +1,741 @@
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/gpio.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_gpio.h>
++#include <linux/of_address.h>
++#include <linux/pm.h>
++#include <linux/pm_runtime.h>
++
++#include <linux/mmc/host.h>
++#include <soc/cpm.h>
++#include <linux/mmc/core.h>
++#include <linux/mmc/slot-gpio.h>
++#include "sdhci.h"
++#include "sdhci-ingenic.h"
++
++#define CLK_CTRL
++/* Software redefinition caps */
++#define CAPABILITIES1_SW	0x276dc898
++#define CAPABILITIES2_SW	0
++
++static LIST_HEAD(manual_list);
++
++#ifdef CONFIG_SOC_X2500
++#define CPM_MSC0_CLK_R		(0xB0000068)
++#define CPM_MSC1_CLK_R		(0xB000006c)
++#else
++#define CPM_MSC0_CLK_R		(0xB0000068)
++#define CPM_MSC1_CLK_R		(0xB00000a4)
++#define CPM_MSC2_CLK_R		(0xB00000a8)
++#endif
++
++#ifdef CONFIG_FPGA_TEST
++#define MSC_CLK_H_FREQ		(0x1 << 20)
++
++static void sdhci_ingenic_fpga_clk(unsigned int clock)
++{
++#define CPM_MSC_CLK_R CPM_MSC0_CLK_R
++//#define CPM_MSC_CLK_R CPM_MSC1_CLK_R
++	unsigned int val;
++
++	if(500000 <= clock){
++		val = readl((const volatile void*)CPM_MSC_CLK_R);
++		val |= MSC_CLK_H_FREQ;
++		writel(val, (void*)CPM_MSC_CLK_R);
++	} else {
++		val = readl((const volatile void*)CPM_MSC_CLK_R);
++		val &= ~MSC_CLK_H_FREQ;
++		writel(val, (void*)CPM_MSC_CLK_R);
++	}
++	printk("\tclk=%d, CPM_MSC0_CLK_R: %08x\n\n", clock, readl((const volatile void*)CPM_MSC0_CLK_R));
++}
++#endif
++
++static unsigned int sdhci_ingenic_get_cpm_msc(struct sdhci_host *host)
++{
++	char msc_ioaddr[16];
++	unsigned int cpm_msc;
++	sprintf(msc_ioaddr, "0x%x", (unsigned int)host->ioaddr);
++#ifdef CONFIG_SOC_X2500
++	if (!strcmp(msc_ioaddr ,"0xb3450000"))
++		cpm_msc = CPM_MSC0_CLK_R;
++	if (!strcmp(msc_ioaddr ,"0xb3070000"))
++		cpm_msc = CPM_MSC1_CLK_R;
++#else
++	if (!strcmp(msc_ioaddr ,"0xb3450000"))
++		cpm_msc = CPM_MSC0_CLK_R;
++	if (!strcmp(msc_ioaddr ,"0xb3460000"))
++		cpm_msc = CPM_MSC1_CLK_R;
++	if (!strcmp(msc_ioaddr ,"0xb3490000"))
++		cpm_msc = CPM_MSC2_CLK_R;
++#endif
++	return cpm_msc;
++
++}
++
++/**
++ * sdhci_ingenic_msc_tuning  Enable msc controller tuning
++ *
++ * Tuning rx phase
++ * */
++static void sdhci_ingenic_en_msc_tuning(struct sdhci_host *host, unsigned int cpm_msc)
++{
++	if (host->mmc->ios.timing & MMC_TIMING_UHS_SDR50 ||
++		host->mmc->ios.timing & MMC_TIMING_UHS_SDR104 ||
++		host->mmc->ios.timing & MMC_TIMING_MMC_HS400) {
++		*(volatile unsigned int*)cpm_msc &= ~(0x1 << 20);
++	}
++}
++
++static void sdhci_ingenic_sel_rx_phase(unsigned int cpm_msc)
++{
++	*(volatile unsigned int*)cpm_msc |= (0x1 << 20); // default
++
++	*(volatile unsigned int*)cpm_msc &= ~(0x7 << 17);
++	*(volatile unsigned int*)cpm_msc |= (0x7 << 17); // OK  RX 90 TX 270
++}
++
++static void sdhci_ingenic_sel_tx_phase(unsigned int cpm_msc)
++{
++	*(volatile unsigned int*)cpm_msc &= ~(0x3 << 15);
++/*	*(volatile unsigned int*)cpm_msc |= (0x2 << 15); // 180  100M OK*/
++	*(volatile unsigned int*)cpm_msc |= (0x3 << 15);
++}
++
++/**
++ * sdhci_ingenic_set_clock - callback on clock change
++ * @host: The SDHCI host being changed
++ * @clock: The clock rate being requested.
++ *
++ * When the card's clock is going to be changed, look at the new frequency
++ * and find the best clock source to go with it.
++*/
++static void sdhci_ingenic_set_clock(struct sdhci_host *host, unsigned int clock)
++{
++#ifndef CONFIG_FPGA_TEST
++	struct sdhci_ingenic *sdhci_ing = sdhci_priv(host);
++	unsigned int cpm_msc = sdhci_ingenic_get_cpm_msc(host);
++	char clkname[16];
++
++	if (clock == 0){
++		return ;
++	}
++
++	sdhci_set_clock(host, clock);
++	sprintf(clkname, "mux_msc%d", sdhci_ing->pdev->id);
++	sdhci_ing->clk_mux = clk_get(NULL, clkname);
++
++	if (clock > 400000) {
++		clk_set_parent(sdhci_ing->clk_mux, sdhci_ing->clk_mpll);
++	} else {
++		clk_set_parent(sdhci_ing->clk_mux, sdhci_ing->clk_ext);
++		*(volatile unsigned int *)0xB0000068 |= 1 << 21;
++	}
++
++	clk_set_rate(sdhci_ing->clk_cgu, clock);
++
++//	printk("%s, set clk: %d, get_clk_rate=%ld\n", __func__, clock, clk_get_rate(sdhci_ing->clk_cgu));
++
++	if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
++		host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) {
++
++		/* RX phase selecte */
++		if (sdhci_ing->pdata->enable_cpm_rx_tuning == 1)
++			sdhci_ingenic_sel_rx_phase(cpm_msc);
++		else
++			sdhci_ingenic_en_msc_tuning(host, cpm_msc);
++		/* TX phase selecte */
++		if (sdhci_ing->pdata->enable_cpm_tx_tuning == 1)
++			sdhci_ingenic_sel_tx_phase(cpm_msc);
++	}
++#else //CONFIG_FPGA_TEST
++	sdhci_ingenic_fpga_clk(clock);
++#endif
++}
++
++
++/* I/O Driver Strength Types */
++#define INGENIC_TYPE_0  0x0		//30
++#define INGENIC_TYPE_1  0x1		//50
++#define INGENIC_TYPE_2  0x2		//66
++#define INGENIC_TYPE_3  0x3		//100
++
++
++#ifndef CONFIG_SOC_X2500
++void sdhci_ingenic_voltage_switch(struct sdhci_host *host,int voltage)
++{
++	struct sdhci_ingenic *sdhci_ing = sdhci_priv(host);
++	struct sdhci_ingenic_pdata *pdata = sdhci_ing->pdata;
++	unsigned int val;
++
++	if (pdata->sdr_v18 < 0)
++		return;
++
++	switch(voltage){
++		case MMC_SIGNAL_VOLTAGE_330:
++			val = cpm_inl(CPM_EXCLK_DS) & ~(1 << 31);
++			cpm_outl(val, CPM_EXCLK_DS);
++			/*Set up hardware circuit 3V*/
++			gpio_direction_output(sdhci_ing->pdata->sdr_v18, 0);
++			break;
++		case MMC_SIGNAL_VOLTAGE_180:
++			/*controlled SD voltage to 1.8V*/
++			val = cpm_inl(CPM_EXCLK_DS) | (1 << 31);
++			cpm_outl(val, CPM_EXCLK_DS);
++			/*Set up hardware circuit 1.8V*/
++			gpio_direction_output(pdata->sdr_v18, 1);
++			break;
++		default:
++			return ;
++	}
++
++}
++#endif
++
++void sdhci_ingenic_power_set(struct sdhci_host *host,int onoff)
++{
++	struct sdhci_ingenic *sdhci_ing = sdhci_priv(host);
++	struct sdhci_ingenic_pdata *pdata = sdhci_ing->pdata;
++
++	if(pdata->gpio->pwr.num >= 0){
++		if(onoff)
++			gpio_direction_output(pdata->gpio->pwr.num,pdata->gpio->pwr.enable_level);
++		else
++			gpio_direction_output(pdata->gpio->pwr.num,!pdata->gpio->pwr.enable_level);
++	} else {
++		return ;
++	}
++}
++
++void ingenic_sdhci_hwreset(struct sdhci_host *host)
++{
++	struct sdhci_ingenic *sdhci_ing = sdhci_priv(host);
++	struct sdhci_ingenic_pdata *pdata = sdhci_ing->pdata;
++
++	if(pdata->gpio->rst.num >= 0){
++			gpio_direction_output(pdata->gpio->rst.num,pdata->gpio->rst.enable_level);
++			udelay(10);
++			gpio_direction_output(pdata->gpio->rst.num,!pdata->gpio->rst.enable_level);
++			usleep_range(300,500);
++	} else {
++		return ;
++	}
++
++}
++
++
++#define BOUNDARY_OK(addr, len) \
++	((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
++
++
++/*
++ * If DMA addr spans 128MB boundary, we split the DMA transfer into two
++ * so that each DMA transfer doesn't exceed the boundary.
++ */
++static void ingenic_sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
++				    dma_addr_t addr, int len, unsigned int cmd)
++{
++	int tmplen, offset;
++
++	if (likely(!len || BOUNDARY_OK(addr, len))) {
++		sdhci_adma_write_desc(host, desc, addr, len, cmd);
++		return;
++	}
++
++	offset = addr & (SZ_128M - 1);
++	tmplen = SZ_128M - offset;
++	sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
++
++	addr += tmplen;
++	len -= tmplen;
++	sdhci_adma_write_desc(host, desc, addr, len, cmd);
++}
++
++static struct sdhci_ops sdhci_ingenic_ops = {
++	.set_clock			= sdhci_ingenic_set_clock,
++	.set_bus_width			= sdhci_set_bus_width,
++	.reset				= sdhci_reset,
++	.set_uhs_signaling		= sdhci_set_uhs_signaling,
++	.power_set			= sdhci_ingenic_power_set,
++	.hw_reset			= ingenic_sdhci_hwreset,
++	.adma_write_desc		= ingenic_sdhci_adma_write_desc,
++#ifndef CONFIG_SOC_X2500
++	.voltage_switch			= sdhci_ingenic_voltage_switch,
++#endif
++};
++
++
++#ifdef CONFIG_OF
++static void ingenic_mmc_get_gpio(struct device_node *np, struct ingenic_mmc_pin *pin, char *gpioname)
++{
++       int gpio;
++       enum of_gpio_flags flags;
++
++       pin->num = -EBUSY;
++       gpio = of_get_named_gpio_flags(np, gpioname, 0, &flags);
++       if(gpio_is_valid(gpio)) {
++              pin->num = gpio;
++              pin->enable_level = (flags == OF_GPIO_ACTIVE_LOW ? LOW_ENABLE : HIGH_ENABLE);
++       }
++       printk("mmc gpio %s num:%d en-level: %d\n",gpioname, pin->num, pin->enable_level);
++}
++
++static inline void ingenic_mmc_clk_onoff(struct sdhci_ingenic *ingenic_ing, unsigned int on)
++{
++	if(on) {
++		clk_prepare_enable(ingenic_ing->clk_cgu);
++		clk_prepare_enable(ingenic_ing->clk_gate);
++	} else {
++		clk_disable_unprepare(ingenic_ing->clk_cgu);
++		clk_disable_unprepare(ingenic_ing->clk_gate);
++	}
++}
++
++/**
++ *	ingenic_mmc_manual_detect - insert or remove card manually
++ *	@index: host->index, namely the index of the controller.
++ *	@on: 1 means insert card, 0 means remove card.
++ *
++ *	This functions will be called by manually card-detect driver such as
++ *	wifi. To enable this mode you can set value pdata.removal = MANUAL.
++ */
++int ingenic_mmc_manual_detect(int index, int on)
++{
++	struct sdhci_ingenic *sdhci_ing;
++	struct sdhci_host *host;
++	struct list_head *pos;
++
++	list_for_each(pos, &manual_list) {
++		sdhci_ing = list_entry(pos, struct sdhci_ingenic, list);
++		if (sdhci_ing->pdev->id == index) {
++			break;
++		} else
++			sdhci_ing = NULL;
++	}
++
++	if(!sdhci_ing) {
++		printk("no manual card detect\n");
++		return -1;
++	}
++
++	host = sdhci_ing->host;
++
++	if (on) {
++		dev_err(&sdhci_ing->pdev->dev, "card insert manually\n");
++		set_bit(INGENIC_MMC_CARD_PRESENT, &sdhci_ing->flags);
++#ifdef CLK_CTRL
++		ingenic_mmc_clk_onoff(sdhci_ing, 1);
++#endif
++		host->flags &= ~SDHCI_DEVICE_DEAD;
++		host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
++		mmc_detect_change(sdhci_ing->host->mmc, 0);
++	} else {
++		dev_err(&sdhci_ing->pdev->dev, "card remove manually\n");
++		clear_bit(INGENIC_MMC_CARD_PRESENT, &sdhci_ing->flags);
++
++		host->flags |= SDHCI_DEVICE_DEAD;
++		host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
++		mmc_detect_change(sdhci_ing->host->mmc, 0);
++#ifdef CLK_CTRL
++		ingenic_mmc_clk_onoff(sdhci_ing, 0);
++#endif
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL(ingenic_mmc_manual_detect);
++
++/**
++ *	ingenic_mmc_clk_ctrl - enable or disable msc clock gate
++ *	@index: host->index, namely the index of the controller.
++ *	@on: 1-enable msc clock gate, 0-disable msc clock gate.
++ */
++int ingenic_mmc_clk_ctrl(int index, int on)
++{
++	struct sdhci_ingenic *sdhci_ing;
++	struct list_head *pos;
++
++#ifdef CLK_CTRL
++	list_for_each(pos, &manual_list) {
++		sdhci_ing = list_entry(pos, struct sdhci_ingenic, list);
++		if (sdhci_ing->pdev->id == index)
++			break;
++		else
++			sdhci_ing = NULL;
++	}
++
++	if (!sdhci_ing) {
++		printk("no manual card detect\n");
++		return -1;
++	}
++	ingenic_mmc_clk_onoff(sdhci_ing, on);
++#endif
++	return 0;
++}
++EXPORT_SYMBOL(ingenic_mmc_clk_ctrl);
++
++static int sdhci_ingenic_parse_dt(struct device *dev,
++								  struct sdhci_host *host,
++								  struct sdhci_ingenic_pdata *pdata)
++{
++	struct device_node *np = dev->of_node;
++	struct card_gpio *card_gpio;
++	unsigned int val;
++
++	card_gpio = devm_kzalloc(dev, sizeof(struct card_gpio), GFP_KERNEL);
++	if(!card_gpio)
++		return 0;
++	pdata->gpio = card_gpio;
++
++	pdata->sdr_v18 = of_get_named_gpio(np, "ingenic,sdr-gpios", 0);
++	ingenic_mmc_get_gpio(np,&pdata->gpio->pwr,"ingenic,pwr-gpios");
++	ingenic_mmc_get_gpio(np,&pdata->gpio->rst,"ingenic,rst-gpios");
++
++	/* assuming internal card detect that will be configured by pinctrl */
++	pdata->cd_type = SDHCI_INGENIC_CD_INTERNAL;
++
++	if(of_property_read_bool(np, "pio-mode")) {
++		pdata->pio_mode = 1;
++	}
++	if(of_property_read_bool(np, "enable_autocmd12")) {
++		pdata->enable_autocmd12 = 1;
++	}
++	if(of_property_read_bool(np, "enable_cpm_rx_tuning")) {
++		pdata->enable_cpm_rx_tuning = 1;
++	}
++	if(of_property_read_bool(np, "enable_cpm_tx_tuning")) {
++		pdata->enable_cpm_tx_tuning = 1;
++	}
++
++	/* get the card detection method */
++	if (of_get_property(np, "broken-cd", NULL)) {
++		pdata->cd_type = SDHCI_INGENIC_CD_NONE;
++	}
++
++	if (of_get_property(np, "non-removable", NULL)) {
++		pdata->cd_type = SDHCI_INGENIC_CD_PERMANENT;
++	}
++
++	if (of_get_property(np, "cd-inverted", NULL)) {
++		pdata->cd_type = SDHCI_INGENIC_CD_GPIO;
++	}
++
++	if(!(of_property_read_u32(np, "ingenic,sdio_clk", &val)))
++		pdata->sdio_clk = val;
++
++	/*set Power-On-Control Select of GPIO PE group*/
++	if(of_property_read_bool(np, "ingenic,poc-v1.8")) {
++		pdata->poc_v18 = 1;
++	}
++
++	/* if(of_property_read_bool(np, "ingenic,removal-dontcare")) { */
++	/* 	pdata->removal = DONTCARE; */
++	/* } else if(of_property_read_bool(np, "ingenic,removal-nonremovable")) { */
++	/* 	pdata->removal = NONREMOVABLE; */
++	/* } else if(of_property_read_bool(np, "ingenic,removal-removable")) { */
++	/* 	pdata->removal = REMOVABLE; */
++	/* } else if(of_property_read_bool(np, "ingenic,removal-manual")) { */
++	/* 	pdata->removal = MANUAL; */
++	/* }; */
++
++	/* mmc_of_parse_voltage(np, &pdata->ocr_avail); */
++
++	return 0;
++}
++#else
++static int sdhci_ingenic_parse_dt(struct device *dev,
++								  struct sdhci_host *host,
++								  struct sdhci_ingenic_pdata *pdata)
++{
++	return -EINVAL;
++}
++#endif
++
++static int sdhci_ingenic_probe(struct platform_device *pdev)
++{
++	struct sdhci_ingenic_pdata *pdata;
++	struct device *dev = &pdev->dev;
++	struct sdhci_host *host;
++	struct sdhci_ingenic *sdhci_ing;
++	char clkname[16];
++	int ret, irq;
++
++	if (!pdev->dev.platform_data && !pdev->dev.of_node) {
++		dev_err(dev, "no device data specified\n");
++		return -ENOENT;
++	}
++
++	irq = platform_get_irq(pdev, 0);
++	if (irq < 0) {
++		dev_err(dev, "no irq specified\n");
++		return irq;
++	}
++
++	host = sdhci_alloc_host(dev, sizeof(struct sdhci_ingenic));
++	if (IS_ERR(host)) {
++		dev_err(dev, "sdhci_alloc_host() failed\n");
++		return PTR_ERR(host);
++	}
++	sdhci_ing = sdhci_priv(host);
++
++	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
++	if (!pdata) {
++		ret = -ENOMEM;
++		return ret;
++	}
++
++	if (pdev->dev.of_node) {
++		ret = sdhci_ingenic_parse_dt(&pdev->dev, host, pdata);
++		if (ret)
++			return ret;
++	} else {
++		memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
++	}
++
++	pdev->id = of_alias_get_id(pdev->dev.of_node, "mmc");
++
++	sprintf(clkname, "div_msc%d", pdev->id);
++	sdhci_ing->clk_cgu = devm_clk_get(&pdev->dev, clkname);
++	if(!sdhci_ing->clk_cgu) {
++		dev_err(&pdev->dev, "Failed to Get MSC clk!\n");
++		return PTR_ERR(sdhci_ing->clk_cgu);
++	}
++	sprintf(clkname, "gate_msc%d", pdev->id);
++	sdhci_ing->clk_gate = devm_clk_get(&pdev->dev, clkname);
++	if(!sdhci_ing->clk_gate) {
++		dev_err(&pdev->dev, "Failed to Get PWC MSC clk!\n");
++		return PTR_ERR(sdhci_ing->clk_gate);
++	}
++	sdhci_ing->clk_ext = clk_get(NULL, "ext");
++	sdhci_ing->clk_mpll = clk_get(NULL, "mpll");
++
++	ingenic_mmc_clk_onoff(sdhci_ing, 1);
++
++	sdhci_ing->host = host;
++	sdhci_ing->dev  = &pdev->dev;
++	sdhci_ing->pdev = pdev;
++	sdhci_ing->pdata = pdata;
++
++	host->ioaddr= of_iomap(pdev->dev.of_node, 0);
++	if (IS_ERR(host->ioaddr)) {
++		return PTR_ERR(host->ioaddr);
++	}
++
++	platform_set_drvdata(pdev, host);
++
++	/* sdio for WIFI init*/
++	if (pdata->sdio_clk) {
++		ingenic_sdio_wlan_init(&pdev->dev, pdev->id);
++		list_add(&(sdhci_ing->list), &manual_list);
++	}
++
++	if (pdata->sdr_v18 > 0 && \
++			devm_gpio_request(dev, pdata->sdr_v18, "sdr-v18")) {
++		printk("ERROR: no sdr-v18 pin available !!\n");
++	}
++
++	host->hw_name = "ingenic-sdhci";
++	host->ops = &sdhci_ingenic_ops;
++	host->quirks = 0;
++	host->irq = irq;
++
++	/* Software redefinition caps */
++	host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
++	host->caps  = CAPABILITIES1_SW;
++	host->caps1 = CAPABILITIES2_SW;
++
++	/* not check wp */
++	host->quirks |= SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
++
++	/* Setup quirks for the controller */
++	host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
++	host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
++
++	/* Data Timeout Counter Value */
++	//host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
++	host->timeout_clk = 24000; //TMCLK = 24MHz
++
++	/* This host supports the Auto CMD12 */
++	if(pdata->enable_autocmd12)
++		host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
++
++	/* PIO transfer mode */
++	if(pdata->pio_mode){
++		host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
++		host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
++	}
++	/* TODO:SoCs need BROKEN_ADMA_ZEROLEN_DESC */
++/*	host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;*/
++
++	if (pdata->cd_type == SDHCI_INGENIC_CD_NONE ||
++	    pdata->cd_type == SDHCI_INGENIC_CD_PERMANENT)
++		host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
++
++	if (pdata->cd_type == SDHCI_INGENIC_CD_PERMANENT)
++		host->mmc->caps = MMC_CAP_NONREMOVABLE;
++
++	if (pdata->pm_caps)
++		host->mmc->pm_caps |= pdata->pm_caps;
++
++	host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
++					 SDHCI_QUIRK_32BIT_DMA_SIZE);
++
++	/* It supports additional host capabilities if needed */
++	if (pdata->host_caps)
++		host->mmc->caps |= pdata->host_caps;
++
++	if (pdata->host_caps2)
++		host->mmc->caps2 |= pdata->host_caps2;
++
++#ifdef CONFIG_PM_RUNTIME
++	pm_runtime_enable(&pdev->dev);
++	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
++	pm_runtime_use_autosuspend(&pdev->dev);
++	pm_suspend_ignore_children(&pdev->dev, 1);
++#endif
++
++	ret = mmc_of_parse(host->mmc);
++	if (ret) {
++		dev_err(dev, "mmc_of_parse() failed\n");
++		pm_runtime_forbid(&pdev->dev);
++		pm_runtime_get_noresume(&pdev->dev);
++		return ret;
++	}
++
++	sdhci_enable_v4_mode(host);
++	ret = sdhci_add_host(host);
++	if (ret) {
++		dev_err(dev, "sdhci_add_host() failed\n");
++		pm_runtime_forbid(&pdev->dev);
++		pm_runtime_get_noresume(&pdev->dev);
++		return ret;
++	}
++
++	/*   enable card  inserted and unplug wake-up system */
++	if(host->mmc->slot.cd_irq > 0)
++		enable_irq_wake(host->mmc->slot.cd_irq);
++#ifdef CONFIG_PM_RUNTIME
++	if (pdata->cd_type != SDHCI_INGENIC_CD_INTERNAL) {
++		clk_disable_unprepare(sdhci_ing->clk_cgu);
++		/* clk_disable_unprepare(sdhci_ing->clk_gate); */
++	}
++#endif
++
++	return 0;
++}
++
++static int sdhci_ingenic_remove(struct platform_device *pdev)
++{
++	struct sdhci_host *host =  platform_get_drvdata(pdev);
++	struct sdhci_ingenic *sdhci_ing = sdhci_priv(host);
++
++	if (sdhci_ing->ext_cd_irq)
++		free_irq(sdhci_ing->ext_cd_irq, sdhci_ing);
++
++#ifdef CONFIG_PM_RUNTIME
++	if (pdata->cd_type != SDHCI_INGENIC_CD_INTERNAL){
++		/* clk_prepare_enable(sdhci_ing->clk_gate); */
++		clk_prepare_enable(sdhci_ing->clk_cgu);
++	}
++#endif
++	sdhci_remove_host(host, 1);
++
++	pm_runtime_dont_use_autosuspend(&pdev->dev);
++	pm_runtime_disable(&pdev->dev);
++
++	clk_disable_unprepare(sdhci_ing->clk_cgu);
++	/* clk_disable_unprepare(sdhci_ing->clk_gate); */
++
++	sdhci_free_host(host);
++	platform_set_drvdata(pdev, NULL);
++
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int sdhci_ingenic_suspend(struct device *dev)
++{
++	struct sdhci_host *host = dev_get_drvdata(dev);
++	struct sdhci_ingenic *sdhci_ing = sdhci_priv(host) ;
++	clk_disable_unprepare(sdhci_ing->clk_gate);
++	return sdhci_suspend_host(host);
++}
++
++static int sdhci_ingenic_resume(struct device *dev)
++{
++	struct sdhci_host *host = dev_get_drvdata(dev);
++	struct sdhci_ingenic *sdhci_ing = sdhci_priv(host) ;
++	clk_prepare_enable(sdhci_ing->clk_gate);
++	return sdhci_resume_host(host);
++}
++#endif
++
++#ifdef CONFIG_PM
++static int sdhci_ingenic_runtime_suspend(struct device *dev)
++{
++	return 0;
++}
++
++
++static int sdhci_ingenic_runtime_resume(struct device *dev)
++{
++	return 0;
++}
++#endif
++
++#ifdef CONFIG_PM
++static const struct dev_pm_ops sdhci_ingenic_pmops = {
++	SET_SYSTEM_SLEEP_PM_OPS(sdhci_ingenic_suspend, sdhci_ingenic_resume)
++	SET_RUNTIME_PM_OPS(sdhci_ingenic_runtime_suspend, sdhci_ingenic_runtime_resume,
++			   NULL)
++};
++
++#define SDHCI_INGENIC_PMOPS (&sdhci_ingenic_pmops)
++
++#else
++#define SDHCI_INGENIC_PMOPS NULL
++#endif
++
++
++static struct platform_device_id sdhci_ingenic_driver_ids[] = {
++	{
++		.name		= "ingenic,sdhci",
++		.driver_data	= (kernel_ulong_t)NULL,
++	},
++	{ }
++};
++MODULE_DEVICE_TABLE(platform, sdhci_ingenic_driver_ids);
++
++#ifdef CONFIG_OF
++static const struct of_device_id sdhci_ingenic_dt_match[] = {
++	{.compatible = "ingenic,sdhci",},
++	{},
++};
++MODULE_DEVICE_TABLE(of, sdhci_ingenic_dt_match);
++#endif
++
++static struct platform_driver sdhci_ingenic_driver = {
++	.probe		= sdhci_ingenic_probe,
++	.remove		= sdhci_ingenic_remove,
++	.id_table	= sdhci_ingenic_driver_ids,
++	.driver		= {
++		.owner	= THIS_MODULE,
++		.name	= "ingenic,sdhci",
++		.pm	= SDHCI_INGENIC_PMOPS,
++		.of_match_table = of_match_ptr(sdhci_ingenic_dt_match),
++	},
++};
++
++module_platform_driver(sdhci_ingenic_driver);
++
++
++MODULE_DESCRIPTION("Ingenic SDHCI (MSC) driver");
++MODULE_AUTHOR("Large Dipper <wangquan.shao@ingenic.cn>");
++MODULE_LICENSE("GPL v2");
++MODULE_VERSION("20160808");
+diff --git a/module_drivers/drivers/mmc/host/sdhci-ingenic.h b/module_drivers/drivers/mmc/host/sdhci-ingenic.h
+new file mode 100644
+index 000000000..70dde7bdc
+--- /dev/null
++++ b/module_drivers/drivers/mmc/host/sdhci-ingenic.h
+@@ -0,0 +1,97 @@
++#ifndef __SDHCI_INGENIC_H__
++#define __SDHCI_INGENIC_H__
++
++#include "ingenic_mmc_reg.h"
++enum cd_types {
++	SDHCI_INGENIC_CD_INTERNAL,	/* use mmc internal CD line */
++	SDHCI_INGENIC_CD_GPIO,		/* use external gpio pin for CD line */
++	SDHCI_INGENIC_CD_NONE,		/* no CD line, use polling to detect card */
++	SDHCI_INGENIC_CD_PERMANENT,	/* no CD line, card permanently wired to host */
++};
++
++
++#define LOW_ENABLE			0
++#define HIGH_ENABLE			1
++struct ingenic_mmc_pin {
++	short				num;
++	short 				enable_level;
++};
++
++struct card_gpio {
++	struct ingenic_mmc_pin 		wp;
++	struct ingenic_mmc_pin 		cd;
++	struct ingenic_mmc_pin 		pwr;
++	struct ingenic_mmc_pin 		rst;
++};
++
++/**
++ * struct sdhci_ingenic_platdata() - Platform device data for ingenic SDHCI
++ * @max_width: The maximum number of data bits supported.
++ * @host_caps: Standard MMC host capabilities bit field.
++ * @host_caps2: The second standard MMC host capabilities bit field.
++ * @sdr_v18: External gpio pin switch voltage from 3.3V to 1.8V
++ * @cd_type: Type of Card Detection method (see cd_types enum above)
++ * @enable_cpm_rx_tunning: Manual adjustment cpm rx tunting
++ * @enable_cpm_tx_tunning: Manual adjustment cpm tx tunting
++ * @ext_cd_gpio_invert: invert values for external CD gpio line
++ * @cfg_gpio: Configure the GPIO for a specific card bit-width
++ *
++ * Initialisation data specific to either the machine or the platform
++ * for the device driver to use or call-back when configuring gpio or
++ * card speed information.
++ */
++struct sdhci_ingenic_pdata {
++	unsigned int    host_caps;
++	unsigned int    host_caps2;
++	unsigned short	sdio_clk;
++	int		sdr_v18;
++	unsigned int	poc_v18;
++	unsigned int    pm_caps;
++	enum cd_types   cd_type;
++
++	unsigned int	pio_mode;
++	unsigned int	enable_autocmd12;
++
++	struct card_gpio *gpio;
++	int	enable_cpm_rx_tuning;
++	int	enable_cpm_tx_tuning;
++	bool        ext_cd_gpio_invert;
++
++	void    (*cfg_gpio)(struct platform_device *dev, int width);
++	int     (*private_init)(void);
++};
++
++
++#define INGENIC_MMC_CARD_PRESENT	0
++#define INGENIC_MMC_CARD_NEED_INIT	1
++#define INGENIC_MMC_USE_PIO		2
++/**
++ * struct sdhci_ingenic - INGENIC SDHCI instance
++ * @host: The SDHCI host created
++ * @pdev: The platform device we where created from.
++ * @ioarea: The resource created when we claimed the IO area.
++ * @pdata: The platform data for this controller.
++ */
++struct sdhci_ingenic {
++	struct device			*dev;
++	struct sdhci_host		*host;
++	struct platform_device		*pdev;
++	struct device_node		*node;
++	struct sdhci_ingenic_pdata	*pdata;
++	struct list_head		list;
++	struct clk			*clk_cgu;
++	struct clk			*clk_gate;
++	struct clk			*clk_ext;
++	struct clk			*clk_mux;
++	struct clk			*clk_mpll;
++	int				cur_clk;
++	int				ext_cd_irq;
++	int				ext_cd_gpio;
++	unsigned long			clk_rates;
++	unsigned long			flags;
++};
++
++int ingenic_sdio_wlan_init(struct device *dev, int index);
++int ingenic_mmc_clk_ctrl(int index, int on);
++int ingenic_mmc_manual_detect(int index, int on);
++#endif	/* __SDHCI_INGENIC_H__ */
+diff --git a/module_drivers/drivers/mtd/Makefile b/module_drivers/drivers/mtd/Makefile
+new file mode 100644
+index 000000000..6f2dc17a3
+--- /dev/null
++++ b/module_drivers/drivers/mtd/Makefile
+@@ -0,0 +1 @@
++obj-y += devices/
+diff --git a/module_drivers/drivers/mtd/devices/Kconfig b/module_drivers/drivers/mtd/devices/Kconfig
+new file mode 100644
+index 000000000..b5fb65696
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/Kconfig
+@@ -0,0 +1,90 @@
++config INGENIC_SFC
++	tristate "Ingenic series SFC driver"
++	depends on MACH_XBURST || MACH_XBURST2
++	help
++		SFC driver for Ingenic series SoCs
++
++if INGENIC_SFC
++
++
++choice
++	prompt "Select Ingenic series SFC driver version"
++	default MTD_INGENIC_SFC_V1
++	help
++	  Select the SFC driver version
++
++config MTD_INGENIC_SFC_V1
++	bool "Use ingenic sfc driver version 1"
++	depends on INGENIC_SFC
++
++config MTD_INGENIC_SFC_V2
++	bool "Use ingenic sfc driver version 2"
++	depends on INGENIC_SFC
++
++endchoice
++
++
++choice
++	prompt "the SFC external memory (nor or nand)"
++	help
++	  Select the SFC external memory
++
++config MTD_INGENIC_SFC_NORFLASH
++	bool "Support ingenic sfc-nor"
++	depends on INGENIC_SFC
++
++config MTD_INGENIC_SFC_NANDFLASH
++	bool "Support ingenic sfc-nand"
++	depends on INGENIC_SFC
++	select MTD_NAND
++
++endchoice
++
++
++config INGENIC_SFCNAND_FMW
++	bool "ingenic SN and MAC read write support."
++	default n
++	depends on INGENIC_SFC && MTD_INGENIC_SFC_NANDFLASH
++	help
++		Say Y here if you want to use sn read write function. when in doubt , Say N here.
++
++config SN_SIZE
++	int "SN space size (MB)"
++	range 1 5
++	default 1
++	depends on INGENIC_SFCNAND_FMW
++
++config MAC_SIZE
++	int "MAC space size (MB)"
++	range 1 5
++	default 1
++	depends on INGENIC_SFCNAND_FMW
++
++config LICENSE_SIZE
++	int "LICENSE space size (MB)"
++	range 1 5
++	default 1
++	depends on INGENIC_SFCNAND_FMW
++
++
++menuconfig INGENIC_BUILTIN_PARAMS
++	bool "Use SPI Nor Flash params built in kernel"
++	depends on MTD_INGENIC_SFC_NORFLASH
++	default n
++	help
++		Say Y here to SPI Nor Flash params built in kernel.
++
++config INGENIC_GD25Q127C
++	bool "GD25Q127C 0xc84018"
++	depends on INGENIC_BUILTIN_PARAMS
++
++config INGENIC_GD25Q256C
++	bool "GD25Q256C 0xc84019"
++	depends on INGENIC_BUILTIN_PARAMS
++
++config INGENIC_GD25S512MD
++	bool "GD25S512MD 0xc84019"
++	depends on INGENIC_BUILTIN_PARAMS
++
++
++endif
+diff --git a/module_drivers/drivers/mtd/devices/Makefile b/module_drivers/drivers/mtd/devices/Makefile
+new file mode 100644
+index 000000000..29c6aed7a
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/Makefile
+@@ -0,0 +1,2 @@
++#obj-$(CONFIG_MTD_INGENIC_SFC_V1) += ingenic_sfc_v1/
++obj-$(CONFIG_MTD_INGENIC_SFC_V2) += ingenic_sfc_v2/
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/Makefile b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/Makefile
+new file mode 100644
+index 000000000..52e8f6ea5
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/Makefile
+@@ -0,0 +1,8 @@
++#
++# linux/drivers/mtd/devices/ingenic_sfc_v2/Makefile
++#
++
++obj-$(CONFIG_INGENIC_BUILTIN_PARAMS) += nor_device/
++
++ccflags-y += -I$(srctree)/drivers/mtd/nand/raw
++obj-y	+= ingenic_sfc_common.o ingenic_sfc_nand.o nand_device/ ingenic_sfc_nor.o ingenic_sfc_ops.o ingenic_sfc_drv.o
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/fmw.h b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/fmw.h
+new file mode 100644
+index 000000000..00d29fa56
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/fmw.h
+@@ -0,0 +1,72 @@
++#ifndef __FMW_H__
++#define __FMW_H__
++
++#define FMW_BUF_LEN	512
++
++#define CONFIG_SN_FLASH_SIZE        (CONFIG_SN_SIZE * 1024 * 1024)
++#define CONFIG_MAC_FLASH_SIZE       (CONFIG_MAC_SIZE * 1024 * 1024)
++#define CONFIG_LICENSE_FLASH_SIZE   (CONFIG_LICENSE_SIZE * 1024 * 1024)
++
++struct fmw_config {
++	uint32_t data_len;
++	uint32_t crc_val;
++};
++
++static const uint32_t crc_table[] = {
++	/* CRC polynomial 0xedb88320 */
++	0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
++	0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
++	0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
++	0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
++	0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
++	0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
++	0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
++	0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
++	0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
++	0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
++	0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
++	0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
++	0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
++	0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
++	0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
++	0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
++	0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
++	0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
++	0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
++	0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
++	0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
++	0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
++	0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
++	0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
++	0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
++	0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
++	0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
++	0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
++	0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
++	0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
++	0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
++	0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
++	0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
++	0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
++	0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
++	0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
++	0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
++	0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
++	0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
++	0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
++	0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
++	0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
++	0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
++};
++
++static inline uint32_t local_crc32(uint32_t crc,unsigned char *buffer, uint32_t size)
++{
++	uint32_t i;
++	for (i = 0; i < size; i++) {
++		crc = crc_table[(crc ^ buffer[i]) & 0xff] ^ (crc >> 8);
++	}
++	return crc ;
++}
++
++#endif
++
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_common.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_common.c
+new file mode 100644
+index 000000000..2cbb15451
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_common.c
+@@ -0,0 +1,957 @@
++/*
++ * SFC controller for SPI protocol, use FIFO and DMA;
++ *
++ * Copyright (c) 2015 Ingenic
++ * Author: <xiaoyang.fu@ingenic.com>
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++*/
++
++#include <linux/init.h>
++#include <linux/spinlock.h>
++#include <linux/workqueue.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/sched.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/gpio.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++
++#include <asm/uaccess.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++
++#include "ingenic_sfc_common.h"
++#include "spinor.h"
++
++
++#define SFC_REG_DEBUG
++
++#define SFC_ASSERT(sfc, cond) do {				\
++    if (!(cond)) {						\
++        __assert(__FILE__, __LINE__, sfc, #cond);		\
++    }								\
++} while (0)
++
++#define GET_PHYADDR(a)  \
++({						\
++	unsigned int v;        \
++	if (unlikely((unsigned int)(a) & 0x40000000)) {    \
++	v = page_to_phys(vmalloc_to_page((const void *)(a))) | ((unsigned int)(a) & ~PAGE_MASK); \
++	} else     \
++	v = ((unsigned int)(a) & 0x1fffffff);                   \
++	v;                                             \
++ })
++
++static inline void sfc_writel(struct sfc *sfc, unsigned short offset, u32 value)
++{
++	writel(value, sfc->iomem + offset);
++}
++
++static inline unsigned int sfc_readl(struct sfc *sfc, unsigned short offset)
++{
++	return readl(sfc->iomem + offset);
++}
++
++#ifdef SFC_REG_DEBUG
++void dump_sfc_reg(struct sfc *sfc)
++{
++	int i = 0;
++
++	printk("\nSFC_GLB0	 = %08x\n", sfc_readl(sfc, SFC_GLB0));
++	printk("SFC_DEV_CONF	 = %08x\n", sfc_readl(sfc, SFC_DEV_CONF));
++	printk("SFC_DEV_STA_EXP	 = %08x\n", sfc_readl(sfc, SFC_DEV_STA_EXP));
++	printk("SFC_DEV0_STA_RT	 = %08x\n", sfc_readl(sfc, SFC_DEV0_STA_RT));
++	printk("SFC_DEV_STA_MASK = %08x\n", sfc_readl(sfc, SFC_DEV_STA_MSK));
++	for(i = 0; i < 6; i++){
++		printk("SFC_TRAN_CONF0(%d) = %08x\n", i, sfc_readl(sfc, SFC_TRAN_CONF0(i)));
++	}
++	printk("SFC_TRAN_LEN	 = %08x\n", sfc_readl(sfc, SFC_TRAN_LEN));
++	for(i = 0; i < 6; i++){
++		printk("SFC_DEV_ADDR%d		= %08x\n",	i, sfc_readl(sfc, SFC_DEV_ADDR(i)));
++		printk("SFC_DEV_ADDR_PLUS%d	= %08x\n",	i, sfc_readl(sfc, SFC_DEV_ADDR_PLUS(i)));
++	}
++
++	printk("SFC_MEM_ADDR	= %08x\n", sfc_readl(sfc, SFC_MEM_ADDR));
++	printk("SFC_TRIG	= %08x\n", sfc_readl(sfc, SFC_TRIG));
++	printk("SFC_SR		= %08x\n", sfc_readl(sfc, SFC_SR));
++	printk("SFC_SCR		= %08x\n", sfc_readl(sfc, SFC_SCR));
++	printk("SFC_INTC	= %08x\n", sfc_readl(sfc, SFC_INTC));
++	printk("SFC_FSM		= %08x\n", sfc_readl(sfc, SFC_FSM));
++	printk("SFC_CGE		= %08x\n", sfc_readl(sfc, SFC_CGE));
++	printk("SFC_CMD_IDX	= %08x\n", sfc_readl(sfc, SFC_CMD_IDX));
++	printk("SFC_COL_ADDR	= %08x\n", sfc_readl(sfc, SFC_COL_ADDR));
++	printk("SFC_ROW_ADDR	= %08x\n", sfc_readl(sfc, SFC_ROW_ADDR));
++	printk("SFC_STA_ADDR0	= %08x\n", sfc_readl(sfc, SFC_STA_ADDR0));
++	printk("SFC_STA_ADDR1	= %08x\n", sfc_readl(sfc, SFC_STA_ADDR1));
++	printk("SFC_DES_ADDR	= %08x\n", sfc_readl(sfc, SFC_DES_ADDR));
++	printk("SFC_GLB1	= %08x\n", sfc_readl(sfc, SFC_GLB1));
++	printk("SFC_DEV1_STA_RT = %08x\n", sfc_readl(sfc, SFC_DEV1_STA_RT));
++	for(i = 0; i < 6; i++) {
++		printk("SFC_TRAN_CONF1(%d)	= %08x\n", i, sfc_readl(sfc, SFC_TRAN_CONF1(i)));
++	}
++	//printk("SFC_CDT	= %08x\n", sfc_readl(sfc, SFC_CDT));
++	//printk("SFC_DR	= %08x\n", sfc_readl(sfc, SFC_RM_DR));
++}
++
++void dump_cdt(struct sfc *sfc)
++{
++	struct sfc_cdt *cdt;
++	int i;
++
++	if(sfc->iomem == NULL){
++		printk("%s error: sfc res not init !\n", __func__);
++		return;
++	}
++
++	cdt = sfc->iomem + 0x800;
++
++	for(i = 0; i < 32; i++){
++		printk("\nnum------->%d\n", i);
++		printk("link:%02x, ENDIAN:%02x, WORD_UINT:%02x, TRAN_MODE:%02x, ADDR_KIND:%02x\n",
++				(cdt[i].link >> 31) & 0x1, (cdt[i].link >> 18) & 0x1,
++				(cdt[i].link >> 16) & 0x3, (cdt[i].link >> 4) & 0xf,
++				(cdt[i].link >> 0) & 0x3
++				);
++		printk("CLK_MODE:%02x, ADDR_WIDTH:%02x, POLL_EN:%02x, CMD_EN:%02x,PHASE_FORMAT:%02x, DMY_BITS:%02x, DATA_EN:%02x, TRAN_CMD:%04x\n",
++				(cdt[i].xfer >> 29) & 0x7, (cdt[i].xfer >> 26) & 0x7,
++				(cdt[i].xfer >> 25) & 0x1, (cdt[i].xfer >> 24) & 0x1,
++				(cdt[i].xfer >> 23) & 0x1, (cdt[i].xfer >> 17) & 0x3f,
++				(cdt[i].xfer >> 16) & 0x1, (cdt[i].xfer >> 0) & 0xffff
++				);
++		printk("DEV_STA_EXP:%08x\n", cdt[i].staExp);
++		printk("DEV_STA_MSK:%08x\n", cdt[i].staMsk);
++	}
++}
++
++void dump_desc(struct sfc *sfc, uint32_t desc_num)
++{
++	struct sfc_desc *desc = sfc->desc;
++	int i = 0;
++
++	for(; i < desc_num; i++){
++		printk("\nDMA Descriptor ---->num: %d, addr: 0x%08x\n", i, (unsigned int)virt_to_phys(&desc[i]));
++		printk("next_desc_addr: 0x%08x\n", desc[i].next_des_addr);
++		printk("mem_addr: 0x%08x\n", desc[i].mem_addr);
++		printk("tran_len: %d\n", desc[i].tran_len);
++		printk("link: %d\n\n", desc[i].link);
++	}
++}
++
++void dump_sfc_debug(struct sfc *sfc)
++{
++	pr_err("\n######################### sfc dump ###########################\n");
++	pr_err("\nsfc reg: \n");
++	dump_sfc_reg(sfc);
++	pr_err("\nsfc DMA Descriptor chain: \n");
++	dump_desc(sfc, sfc->desc_max_num);
++	pr_err("\nsfc CDT table: \n");
++	dump_cdt(sfc);
++	pr_err("\n######################### sfc dump end ###########################\n");
++}
++
++#endif
++
++void __assert(const char *file, int line, struct sfc *sfc, const char *cond)
++{
++    printk("assert %s failed in %s %d\n", cond, file, line);
++#ifdef SFC_REG_DEBUG
++	dump_sfc_debug(sfc);
++#endif
++	while(1);
++}
++
++static int32_t sfc_stop(struct sfc *sfc)
++{
++	int32_t timeout = 0xffff;
++	sfc_writel(sfc, SFC_TRIG, TRIG_STOP);
++
++	while((sfc_readl(sfc, SFC_SR) & SFC_BUSY) && timeout--);
++	if(timeout < 0)
++		return -EIO;
++	return 0;
++}
++
++static inline void sfc_init(struct sfc *sfc)
++{
++	sfc_writel(sfc, SFC_TRIG, TRIG_STOP);
++	sfc_writel(sfc, SFC_DEV_CONF, 0);
++
++	/* X1000 need set to 0,but X2000 can be set to 1*/
++	sfc_writel(sfc, SFC_CGE, 0);
++
++}
++
++static inline void sfc_start(struct sfc *sfc)
++{
++	uint32_t tmp;
++	tmp = sfc_readl(sfc, SFC_TRIG);
++	tmp |= TRIG_START;
++	sfc_writel(sfc, SFC_TRIG, tmp);
++}
++
++static inline void sfc_flush_fifo(struct sfc *sfc)
++{
++	unsigned int tmp;
++	tmp = sfc_readl(sfc, SFC_TRIG);
++	tmp |= TRIG_FLUSH;
++	sfc_writel(sfc, SFC_TRIG, tmp);
++}
++static inline void  sfc_clear_end_intc(struct sfc *sfc)
++{
++	sfc_writel(sfc, SFC_SCR, CLR_END);
++}
++
++static inline void sfc_clear_treq_intc(struct sfc *sfc)
++{
++	sfc_writel(sfc, SFC_SCR, CLR_TREQ);
++}
++
++static inline void sfc_clear_rreq_intc(struct sfc *sfc)
++{
++	sfc_writel(sfc, SFC_SCR, CLR_RREQ);
++}
++
++static inline void sfc_clear_over_intc(struct sfc *sfc)
++{
++	sfc_writel(sfc, SFC_SCR, CLR_OVER);
++}
++
++static inline void sfc_clear_under_intc(struct sfc *sfc)
++{
++	sfc_writel(sfc, SFC_SCR, CLR_UNDER);
++}
++
++static inline void sfc_clear_all_intc(struct sfc *sfc)
++{
++	sfc_writel(sfc, SFC_SCR, 0x1f);
++}
++
++static inline void sfc_mask_all_intc(struct sfc *sfc)
++{
++	sfc_writel(sfc, SFC_INTC, 0x1f);
++}
++
++static void sfc_dev_hw_init(struct sfc *sfc)
++{
++	uint32_t tmp;
++	tmp = sfc_readl(sfc, SFC_DEV_CONF);
++
++	/*cpha bit:0 , cpol bit:0 */
++	tmp &= ~(DEV_CONF_CPHA | DEV_CONF_CPOL);
++	/*ce_dl bit:1, hold bit:1,wp bit:1*/
++	tmp |= (DEV_CONF_CEDL | DEV_CONF_HOLDDL | DEV_CONF_WPDL);
++	sfc_writel(sfc, SFC_DEV_CONF, tmp);
++
++	/* use CDT mode */
++	printk("Enter 'CDT' mode.\n");
++	tmp = sfc_readl(sfc, SFC_GLB0);
++	tmp |= GLB0_CDT_EN;
++	sfc_writel(sfc, SFC_GLB0, tmp);
++
++	/* use DMA Descriptor chain mode */
++	printk("Enter 'DMA Descriptor chain' mode.\n");
++	tmp = sfc_readl(sfc, SFC_GLB0);
++	tmp |= GLB0_DES_EN;
++	sfc_writel(sfc, SFC_GLB0, tmp);
++}
++
++static void sfc_threshold(struct sfc *sfc, uint32_t value)
++{
++	uint32_t tmp = sfc_readl(sfc, SFC_GLB0);
++	tmp &= ~GLB0_THRESHOLD_MSK;
++	tmp |= value << GLB0_THRESHOLD_OFFSET;
++	sfc_writel(sfc, SFC_GLB0, tmp);
++}
++
++static void sfc_smp_delay(struct sfc *sfc, uint32_t value)
++{
++	uint32_t tmp;
++	tmp = sfc_readl(sfc, SFC_DEV_CONF);
++	tmp &= ~DEV_CONF_SMP_DELAY_MSK;
++	tmp |= value << DEV_CONF_SMP_DELAY_OFFSET;
++	sfc_writel(sfc, SFC_DEV_CONF, tmp);
++}
++
++static int timing_is_valid(uint32_t *p_thold, uint32_t *p_tsetup, uint32_t *p_tsh)
++{
++	int ret = 0;
++
++#define THOLD_LO_VAL 0x0
++#define THOLD_HI_VAL 0x3
++#define TSETUP_LO_VAL 0x0
++#define TSETUP_HI_VAL 0x3
++#define TSH_LO_VAL 0x0
++#define TSH_HI_VAL 0xf
++
++	if ((*p_thold > THOLD_HI_VAL) || (*p_thold < THOLD_LO_VAL)) {
++		pr_err("ERROR: Check that the SFC timing parameter is invalid, thold:%d !\n", *p_thold);
++		*p_thold = clamp((uint32_t)*p_thold, (uint32_t)THOLD_LO_VAL, (uint32_t)THOLD_HI_VAL);
++		ret = -EINVAL;
++	}
++
++	if ((*p_tsetup > TSETUP_HI_VAL) || (p_thold < TSETUP_LO_VAL)) {
++		pr_err("ERROR: Check that the SFC timing parameter is invalid, tsetup:%d !\n", *p_tsetup);
++		*p_tsetup = clamp((uint32_t)*p_tsetup, (uint32_t)TSETUP_LO_VAL, (uint32_t)TSETUP_HI_VAL);
++		ret = -EINVAL;
++	}
++
++	if ((*p_tsh > TSH_HI_VAL) || (*p_tsh < TSH_LO_VAL)){
++		pr_err("ERROR: Check that the SFC timing parameter is invalid, tsh:%d !\n", *p_tsh);
++		*p_tsh = clamp((uint32_t)*p_tsh, (uint32_t)TSH_LO_VAL, (uint32_t)TSH_HI_VAL);
++		ret = -EINVAL;
++	}
++
++	return ret;
++}
++
++
++int32_t set_flash_timing(struct sfc *sfc, uint32_t t_hold, uint32_t t_setup, uint32_t t_shslrd, uint32_t t_shslwr)
++{
++	uint32_t c_hold, c_setup, t_in, c_in;
++	uint32_t c_half_hold, c_half_setup, c_half_in;
++	uint32_t thold, tsetup, tsh;
++	uint32_t tmp;
++	unsigned long cycle;
++	unsigned long half_cycle;
++	unsigned long long ns;
++
++	/* NOTE: 4 frequency division. */
++	sfc->src_clk /= 4;
++
++	ns = 1000000000ULL;
++	do_div(ns, sfc->src_clk);
++	cycle = ns;
++	half_cycle = cycle / 2;
++
++
++	/* Calculate the number of cycle */
++	c_hold = t_hold / cycle;
++	c_half_hold = t_hold % cycle;
++	if(c_half_hold > half_cycle) {
++		c_half_hold = 0;
++		c_hold += 1;
++	}
++
++	c_setup = t_setup / cycle;
++	c_half_setup = t_setup % cycle;
++	if(c_half_setup > half_cycle) {
++		c_half_setup = 0;
++		c_setup += 1;
++	}
++
++	t_in = max(t_shslrd, t_shslwr);
++	c_in = t_in / cycle;
++	c_half_in = t_in % cycle;
++	if(c_half_in > half_cycle) {
++		c_half_in = 0;
++		c_in += 1;
++	}
++
++	/* Calculate timing parameters */
++	if(!c_hold && !c_half_hold)
++		thold = 0;
++	else
++		thold = (2 * c_hold) - 1 + (!!c_half_hold);
++
++	if(!c_setup && !c_half_setup)
++		tsetup = 0;
++	else
++		tsetup = (2 * c_setup) - 1 + (!!c_half_setup);
++
++	if(!c_in && !c_half_in)
++		tsh = 0;
++	else
++		tsh = (2 * c_in) - 1 + (!!c_half_in);
++
++	/* Verify parameters validity */
++	timing_is_valid(&thold, &tsetup, &tsh);
++
++	tmp = sfc_readl(sfc, SFC_DEV_CONF);
++	tmp &= ~(DEV_CONF_THOLD_MSK | DEV_CONF_TSETUP_MSK | DEV_CONF_TSH_MSK);
++	tmp |= (thold << DEV_CONF_THOLD_OFFSET) | \
++		  (tsetup << DEV_CONF_TSETUP_OFFSET) | \
++		  (tsh << DEV_CONF_TSH_OFFSET);
++
++	sfc_writel(sfc, SFC_DEV_CONF, tmp);
++	return 0;
++}
++
++static void sfc_set_length(struct sfc *sfc, uint32_t value)
++{
++	sfc_writel(sfc, SFC_TRAN_LEN, value);
++}
++
++static inline void sfc_transfer_mode(struct sfc *sfc, uint32_t value)
++{
++	uint32_t tmp;
++	tmp = sfc_readl(sfc, SFC_GLB0);
++	if(value == 0)
++		tmp &= ~GLB0_OP_MODE;
++	else
++		tmp |= GLB0_OP_MODE;
++	sfc_writel(sfc, SFC_GLB0, tmp);
++}
++
++static void sfc_read_data(struct sfc *sfc, uint32_t *value)
++{
++	*value = sfc_readl(sfc, SFC_RM_DR);
++}
++
++static void sfc_write_data(struct sfc *sfc, uint32_t value)
++{
++	sfc_writel(sfc, SFC_RM_DR, value);
++}
++
++static void cpu_read_rxfifo(struct sfc *sfc, struct sfc_cdt_xfer *xfer)
++{
++	int32_t i = 0;
++	uint32_t align_len = 0;
++	uint32_t fifo_num = 0;
++	uint32_t last_word = 0;
++	uint32_t unalign_data;
++	uint8_t *c;
++
++	align_len = ALIGN(xfer->config.datalen, 4);
++
++	if(((align_len - xfer->config.cur_len) / 4) > sfc->threshold) {
++		fifo_num = sfc->threshold;
++		last_word = 0;
++	} else {
++		/* last aligned THRESHOLD data*/
++		if(xfer->config.datalen % 4) {
++			fifo_num = (align_len - xfer->config.cur_len) / 4 - 1;
++			last_word = 1;
++		} else {
++			fifo_num = (align_len - xfer->config.cur_len) / 4;
++			last_word = 0;
++		}
++	}
++
++	if ((uint32_t)xfer->config.buf & 0x3) {
++		/* addr not align */
++		for (i = 0; i < fifo_num; i++) {
++			sfc_read_data(sfc, &unalign_data);
++			c = xfer->config.buf;
++			c[0] = (unalign_data >> 0) & 0xff;
++			c[1] = (unalign_data >> 8) & 0xff;
++			c[2] = (unalign_data >> 16) & 0xff;
++			c[3] = (unalign_data >> 24) & 0xff;
++
++			xfer->config.buf += 4;
++			xfer->config.cur_len += 4;
++		}
++	} else {
++		/* addr align */
++		for (i = 0; i < fifo_num; i++) {
++			sfc_read_data(sfc, (uint32_t *)xfer->config.buf);
++			xfer->config.buf += 4;
++			xfer->config.cur_len += 4;
++		}
++	}
++
++	/* last word */
++	if(last_word == 1) {
++		sfc_read_data(sfc, &unalign_data);
++		c = (uint8_t *)xfer->config.buf;
++
++		for(i = 0; i < xfer->config.datalen % 4; i++) {
++			c[i] = (unalign_data >> (i * 8)) & 0xff;
++		}
++
++		xfer->config.buf += xfer->config.datalen % 4;
++		xfer->config.cur_len += xfer->config.datalen % 4;
++	}
++
++}
++
++static void cpu_write_txfifo(struct sfc *sfc, struct sfc_cdt_xfer *xfer)
++{
++	uint32_t align_len = 0;
++	uint32_t fifo_num = 0;
++	uint32_t data = 0;
++	uint32_t i;
++	uint32_t nbytes = xfer->config.datalen % 4;
++
++	align_len = xfer->config.datalen / 4 * 4;
++
++	if (((align_len - xfer->config.cur_len) / 4) >= sfc->threshold) {
++		fifo_num = sfc->threshold;
++		nbytes = 0;
++	} else {
++		fifo_num = (align_len - xfer->config.cur_len) / 4;
++	}
++
++	if ((uint32_t)xfer->config.buf & 0x3) {
++		/* addr not align */
++		for(i = 0; i < fifo_num; i++) {
++			data = xfer->config.buf[3] << 24 | xfer->config.buf[2] << 16 | xfer->config.buf[1] << 8 | xfer->config.buf[0];
++			sfc_write_data(sfc, data);
++			xfer->config.buf += 4;
++			xfer->config.cur_len += 4;
++		}
++	} else {
++		/* addr align */
++		for(i = 0; i < fifo_num; i++) {
++			sfc_write_data(sfc, *(uint32_t *)xfer->config.buf);
++			xfer->config.buf += 4;
++			xfer->config.cur_len += 4;
++		}
++	}
++
++	if(nbytes) {
++		data = 0;
++		for(i = 0; i < nbytes; i++)
++			data |= xfer->config.buf[i] << i * 8;
++		sfc_write_data(sfc, data);
++		xfer->config.cur_len += nbytes;
++	}
++
++}
++
++uint32_t sfc_get_sta_rt0(struct sfc *sfc)
++{
++	return sfc_readl(sfc, SFC_DEV0_STA_RT);
++}
++
++
++static void sfc_enable_all_intc(struct sfc *sfc)
++{
++	sfc_writel(sfc, SFC_INTC, 0);
++}
++
++static void sfc_set_mem_addr(struct sfc *sfc, unsigned int addr)
++{
++	sfc_writel(sfc, SFC_MEM_ADDR, addr);
++}
++
++static void sfc_set_desc_addr(struct sfc *sfc, unsigned int addr)
++{
++	sfc_writel(sfc, SFC_DES_ADDR, addr);
++}
++
++void *sfc_get_paddr(void *vaddr)
++{
++	unsigned long paddr;
++	unsigned int pfn = 0;
++	unsigned int page_offset = 0;
++
++	if (is_vmalloc_addr(vaddr)) {
++		pfn = vmalloc_to_pfn(vaddr);
++		page_offset = (unsigned int)vaddr & (PAGE_SIZE - 1);
++		paddr = (pfn << 12) + page_offset;
++	} else {
++		paddr = virt_to_phys(vaddr);
++	}
++
++	return (void *)paddr;
++}
++
++int32_t create_sfc_desc(struct sfc *sfc, unsigned char *vaddr, size_t len)
++{
++	struct sfc_desc *desc = sfc->desc;
++	uint32_t ualign_size, off_len, last_len, step_len, page_num;
++	int current_pfn = 0, next_pfn = 0;
++	int32_t i = 0, j = 0;
++
++	ualign_size = (unsigned int)vaddr & (PAGE_SIZE - 1);
++	off_len = PAGE_SIZE - ualign_size;
++
++	if(is_vmalloc_addr(vaddr) && (len > off_len)){
++		page_num = (len - off_len) >> (ffs(PAGE_SIZE) - 1);
++		last_len = (len - off_len) & (PAGE_SIZE - 1);
++		current_pfn = vmalloc_to_pfn(vaddr);
++
++		desc[i].next_des_addr = 0;
++		desc[i].mem_addr = (unsigned int)sfc_get_paddr((void *)vaddr);
++		desc[i].tran_len = off_len;
++		desc[i].link = 1;
++
++		vaddr += off_len;
++		step_len = PAGE_SIZE;
++
++		/* case 1. Handle physical address discontinuity */
++		do{
++			if(!page_num){
++				if(last_len)
++					step_len = last_len;
++				else{
++					break;
++				}
++			}
++
++			next_pfn = vmalloc_to_pfn(vaddr);
++			if((current_pfn + 1) != next_pfn){
++				if(++i > (sfc->desc_max_num - 1)){
++					dev_err(sfc->dev, "%s The number of descriptors exceeds the maximum limit.\n", __func__);
++					return -ENOMEM;
++				}
++
++				desc[i-1].next_des_addr = (unsigned int)sfc_get_paddr((void *)&desc[i]);
++
++				desc[i].next_des_addr = 0;
++				desc[i].mem_addr = (unsigned int)sfc_get_paddr((void *)vaddr);
++				desc[i].tran_len = step_len;
++				desc[i].link = 1;
++			}else{
++				desc[i].tran_len += step_len;
++			}
++
++
++			if(page_num){
++				current_pfn = next_pfn;
++				vaddr += step_len;
++			}
++		}while(page_num--);
++	}else{
++		/* case 2. Physical Address Continuity and only need one descriptor */
++		desc[i].next_des_addr = 0;
++		desc[i].mem_addr = (unsigned int)sfc_get_paddr((void *)vaddr);
++		desc[i].tran_len = len;
++	}
++
++	/* last descriptor is not link */
++	desc[i].link = 0;
++
++	return i;
++}
++
++int request_sfc_desc(struct sfc *sfc, int desc_max_num)
++{
++	sfc->desc = (struct sfc_desc *)dma_alloc_coherent(sfc->dev,
++			sizeof(struct sfc_desc) * desc_max_num, &sfc->desc_pyaddr, GFP_KERNEL);
++	if (IS_ERR_OR_NULL(sfc->desc)) {
++		return -ENOMEM;
++	}
++	sfc->desc_max_num = desc_max_num;
++
++	return 0;
++}
++
++void free_sfc_desc(struct sfc *sfc)
++{
++	return dma_free_coherent(sfc->dev, sizeof(struct sfc_desc) * sfc->desc_max_num, sfc->desc, sfc->desc_pyaddr);
++}
++
++#define SFC_TRANSFER_TIMEOUT	3000	//3000ms for timeout
++static int32_t sfc_start_transfer(struct sfc *sfc)
++{
++	int32_t err;
++	sfc_clear_all_intc(sfc);
++	sfc_enable_all_intc(sfc);
++	sfc_start(sfc);
++	err = wait_for_completion_timeout(&sfc->done, msecs_to_jiffies(SFC_TRANSFER_TIMEOUT));
++	if (!err) {
++#ifdef SFC_REG_DEBUG
++		dump_sfc_debug(sfc);
++#endif
++		sfc_mask_all_intc(sfc);
++		sfc_clear_all_intc(sfc);
++
++		sfc_stop(sfc);
++		sfc_flush_fifo(sfc);
++
++		printk("line:%d Timeout for ACK from SFC device\n",__LINE__);
++		return -ETIMEDOUT;
++	}
++	return 0;
++}
++
++void write_cdt(struct sfc *sfc, struct sfc_cdt *cdt, uint16_t start_index, uint16_t end_index)
++{
++	uint32_t cdt_num, cdt_size;
++
++	cdt_num = end_index - start_index + 1;
++	cdt_size = sizeof(struct sfc_cdt);
++
++	memcpy((void *)sfc->iomem + SFC_CDT + (start_index * cdt_size), (void *)cdt + (start_index * cdt_size), cdt_num * cdt_size);
++	printk("create CDT index: %d ~ %d,  index number:%d.\n", start_index, end_index, cdt_num);
++}
++
++static void sfc_set_index(struct sfc *sfc, unsigned short index)
++{
++
++	uint32_t tmp = sfc_readl(sfc, SFC_CMD_IDX);
++	tmp &= ~CMD_IDX_MSK;
++	tmp |= index;
++	sfc_writel(sfc, SFC_CMD_IDX, tmp);
++}
++
++static void sfc_set_dataen(struct sfc *sfc, uint8_t dataen)
++{
++
++	uint32_t tmp = sfc_readl(sfc, SFC_CMD_IDX);
++	tmp &= ~CDT_DATAEN_MSK;
++	tmp |= (dataen << CDT_DATAEN_OFF);
++	sfc_writel(sfc, SFC_CMD_IDX, tmp);
++}
++
++static void sfc_set_datadir(struct sfc *sfc, uint8_t datadir)
++{
++
++	uint32_t tmp = sfc_readl(sfc, SFC_CMD_IDX);
++	tmp &= ~CDT_DIR_MSK;
++	tmp |= (datadir << CDT_DIR_OFF);
++	sfc_writel(sfc, SFC_CMD_IDX, tmp);
++}
++
++
++int sfc_sync_cdt(struct sfc *sfc, struct sfc_cdt_xfer *xfer)
++{
++	/*0.reset transfer length*/
++	sfc_set_length(sfc, 0);
++
++	/*1. set index*/
++	sfc_set_index(sfc, xfer->cmd_index);
++
++	/*2. set addr*/
++	sfc_writel(sfc, SFC_COL_ADDR, xfer->columnaddr);
++	sfc_writel(sfc, SFC_ROW_ADDR, xfer->rowaddr);
++	sfc_writel(sfc, SFC_STA_ADDR0, xfer->staaddr0);
++	sfc_writel(sfc, SFC_STA_ADDR1, xfer->staaddr1);
++
++	/*3. config data*/
++	sfc_set_dataen(sfc, xfer->dataen);
++	if(xfer->dataen){
++		sfc_set_datadir(sfc, xfer->config.data_dir);
++		sfc_transfer_mode(sfc, xfer->config.ops_mode);
++		sfc_set_length(sfc, xfer->config.datalen);
++
++		/* Memory address for DMA when do not use DMA descriptor */
++		sfc_set_mem_addr(sfc, 0);
++
++		if(xfer->config.ops_mode == DMA_OPS){
++			if(xfer->config.data_dir == GLB0_TRAN_DIR_READ){
++				dma_sync_single_for_device(sfc->dev, (dma_addr_t)(sfc_get_paddr((void *)xfer->config.buf)), xfer->config.datalen, DMA_FROM_DEVICE);
++			}else{
++				dma_sync_single_for_device(sfc->dev, (dma_addr_t)(sfc_get_paddr((void *)xfer->config.buf)), xfer->config.datalen, DMA_TO_DEVICE);
++			}
++			/* Set Descriptor address for DMA */
++			sfc_set_desc_addr(sfc, virt_to_phys(sfc->desc));
++		}
++		sfc->xfer = xfer;
++	}
++
++	return sfc_start_transfer(sfc);
++
++}
++
++static irqreturn_t ingenic_sfc_pio_irq_callback(int32_t irq, void *dev)
++{
++	struct sfc *sfc = dev;
++	uint32_t val;
++	uint8_t err_flag = 0;
++
++	val = sfc_readl(sfc, SFC_SR) & 0x1f;
++
++	spin_lock(&sfc->spin_lock);
++
++	if(val & CLR_RREQ) {
++		sfc_clear_rreq_intc(sfc);
++		cpu_read_rxfifo(sfc, sfc->xfer);
++	} else if(val & CLR_TREQ) {
++		sfc_clear_treq_intc(sfc);
++		cpu_write_txfifo(sfc, sfc->xfer);
++	} else if(val & CLR_OVER) {
++		sfc_clear_over_intc(sfc);
++		pr_err("sfc OVER !\n");
++		err_flag = 1;
++	} else if(val & CLR_UNDER) {
++		sfc_clear_under_intc(sfc);
++		pr_err("sfc UNDR !\n");
++		err_flag = 1;
++	} else if(val & CLR_END) {
++		sfc_mask_all_intc(sfc);
++		sfc_clear_end_intc(sfc);
++		sfc->retry_count = 0;
++		complete(&sfc->done);
++	}
++
++	if (err_flag) {
++#ifdef SFC_REG_DEBUG
++		dump_sfc_debug(sfc);
++#endif
++		if (sfc->retry_count > 0) {
++			sfc->retry_count--;
++		} else if (sfc->retry_count == 0){
++			sfc->retry_count = RETRY_COUNT;
++		}
++
++		sfc_clear_all_intc(sfc);
++		sfc_mask_all_intc(sfc);
++		complete(&sfc->done);
++	}
++
++	spin_unlock(&sfc->spin_lock);
++	return IRQ_HANDLED;
++}
++
++static void ingenic_sfc_init_setup(struct sfc *sfc)
++{
++	sfc_init(sfc);
++	sfc_threshold(sfc, sfc->threshold);
++	sfc_dev_hw_init(sfc);
++
++	sfc_transfer_mode(sfc, SLAVE_MODE);
++}
++
++int32_t sfc_clk_set_init(struct sfc *sfc)
++{
++	struct sfc_flash *flash = dev_get_drvdata(sfc->dev);
++	if(flash->sfc_init_frequency)
++		sfc->src_clk = flash->sfc_init_frequency;
++	else
++		sfc->src_clk = 200000000;
++
++
++	/* set clock rate */
++	clk_set_rate(sfc->clk, sfc->src_clk);
++
++	/* sample delay */
++	if(sfc->src_clk >= 200000000){
++		sfc_smp_delay(sfc, DEV_CONF_SMP_DELAY_180);
++	}
++
++	return 0;
++}
++
++int32_t sfc_clk_set_highspeed(struct sfc *sfc)
++{
++	struct sfc_flash *flash = dev_get_drvdata(sfc->dev);
++	struct spinor_flashinfo *nor_info = flash->flash_info;
++
++	if(nor_info->quad_succeed)
++		sfc->src_clk = flash->sfc_max_frequency;
++	else {
++		sfc->src_clk = flash->sfc_max_frequency;
++		if (sfc->src_clk > 200000000) {
++			printk("clk freq too hight! set to 200M\n");
++			sfc->src_clk = 200000000;
++		}
++	}
++
++	/* set clock rate */
++	clk_set_rate(sfc->clk, sfc->src_clk);
++
++	/* sample delay */
++	if(sfc->src_clk >= 200000000){
++		sfc_smp_delay(sfc, DEV_CONF_SMP_DELAY_180);
++	}
++
++	return 0;
++}
++
++
++struct sfc *sfc_res_init(struct platform_device *pdev)
++{
++	struct device_node* np = pdev->dev.of_node;
++	struct ingenic_sfc_info *pdata_params;
++	struct sfc *sfc;
++	struct resource *res;
++	int32_t err = 0;
++
++	pdata_params = devm_kzalloc(&pdev->dev, sizeof(struct ingenic_sfc_info), GFP_KERNEL);
++	if(!pdata_params){
++		printk("ERROR: %s %d devm_kzalloc() error !\n",__func__,__LINE__);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	sfc = devm_kzalloc(&pdev->dev, sizeof(struct sfc), GFP_KERNEL);
++	if (!sfc) {
++		printk("ERROR: %s %d devm_kzalloc() error !\n",__func__,__LINE__);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	sfc->dev = &pdev->dev;
++
++	err = of_property_read_u32(np, "ingenic,spiflash_param_offset", (unsigned int *)&pdata_params->param_offset);
++	if (err < 0) {
++		dev_err(&pdev->dev, "No dts param_offset, use default.\n");
++		pdata_params->param_offset = -EINVAL;
++	}
++
++	err = of_property_read_u8(np, "ingenic,use_ofpart_info", &pdata_params->use_ofpart_info);
++	if (err < 0) {
++		dev_err(&pdev->dev, "Cannot get sfc use_ofpart_info\n");
++		return ERR_PTR(-ENOENT);
++	}
++
++	err = platform_device_add_data(pdev, pdata_params, sizeof(struct ingenic_sfc_info));
++	if(err){
++		printk("ERROR: %s %d error !\n",__func__,__LINE__);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	/* find and map our resources */
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (res == NULL) {
++		dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
++		return ERR_PTR(-ENOENT);
++	}
++
++	sfc->iomem = devm_ioremap_resource(&pdev->dev, res);
++	if (sfc->iomem == NULL) {
++		dev_err(&pdev->dev, "Cannot map IO\n");
++		return ERR_PTR(-ENXIO);
++	}
++
++	sfc->clk = devm_clk_get(&pdev->dev, "div_sfc");
++	if (IS_ERR(sfc->clk)) {
++		dev_err(&pdev->dev, "Cannot get div_sfc clock\n");
++		return ERR_PTR(-ENOENT);
++	}
++
++	sfc->clk_gate = devm_clk_get(&pdev->dev, "gate_sfc");
++	if (IS_ERR(sfc->clk_gate)) {
++		dev_err(&pdev->dev, "Cannot get sfc clock\n");
++		return ERR_PTR(-ENOENT);
++	}
++
++	err = sfc_clk_set_init(sfc);
++	if (err) {
++		return ERR_PTR(-ENOENT);
++	}
++
++	if(clk_prepare_enable(sfc->clk)) {
++		dev_err(&pdev->dev, "cgu clk error\n");
++		return ERR_PTR(-ENOENT);
++	}
++	if(clk_prepare_enable(sfc->clk_gate)) {
++		dev_err(&pdev->dev, "gate clk error\n");
++		return ERR_PTR(-ENOENT);
++	}
++
++	/* SFC parameter initialization */
++	sfc->threshold = THRESHOLD;
++	sfc->retry_count = 0;
++
++	/* request SFC irq */
++	sfc->irq = platform_get_irq(pdev, 0);
++	if (sfc->irq < 0) {
++		dev_err(&pdev->dev, "No IRQ specified\n");
++		return ERR_PTR(-ENOENT);
++	}
++
++	err = devm_request_irq(&pdev->dev, sfc->irq, ingenic_sfc_pio_irq_callback, 0, pdev->name, sfc);
++	if (err) {
++		dev_err(&pdev->dev, "Cannot claim IRQ\n");
++		return ERR_PTR(-EINVAL);
++	}
++
++	/* SFC controller initializations for SFC */
++	ingenic_sfc_init_setup(sfc);
++	spin_lock_init(&sfc->spin_lock);
++	init_completion(&sfc->done);
++	return sfc;
++}
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_common.h b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_common.h
+new file mode 100644
+index 000000000..05d2921a3
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_common.h
+@@ -0,0 +1,36 @@
++#ifndef ingenic_SFC_COMMON_H
++#define ingenic_SFC_COMMON_H
++#include <linux/platform_device.h>
++#include <linux/kernel.h>
++#include <linux/of.h>
++#include <linux/of_gpio.h>
++#include <linux/of_device.h>
++#include "sfc.h"
++#include "sfc_flash.h"
++
++
++void dump_sfc_reg(struct sfc *sfc);
++void dump_cdt(struct sfc *sfc);
++void dump_desc(struct sfc *sfc, uint32_t desc_num);
++
++void *sfc_get_paddr(void *);
++int request_sfc_desc(struct sfc *sfc, int desc_max_num);
++void free_sfc_desc(struct sfc *sfc);
++int32_t create_sfc_desc(struct sfc *, unsigned char *, size_t);
++int sfc_sync_cdt(struct sfc *sfc, struct sfc_cdt_xfer *xfer);
++struct sfc *sfc_res_init(struct platform_device *);
++void sfc_res_deinit(struct sfc *sfc);
++uint32_t sfc_get_sta_rt(struct sfc *);
++void write_cdt(struct sfc *sfc, struct sfc_cdt *cdt, uint16_t start_index, uint16_t end_index);
++
++int32_t set_flash_timing(struct sfc *, uint32_t, uint32_t, uint32_t, uint32_t);
++int32_t sfc_clk_set_highspeed(struct sfc *);
++
++void __assert(const char *file, int line, struct sfc *sfc, const char *cond)
++	    __attribute__ ((__noreturn__));
++
++
++#define RETRY_COUNT 3
++
++#endif
++
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_drv.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_drv.c
+new file mode 100644
+index 000000000..22c827265
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_drv.c
+@@ -0,0 +1,280 @@
++/*
++ * SFC controller for SPI protocol, use FIFO and DMA;
++ *
++ * Copyright (c) 2015 Ingenic
++ * Author: <xiaoyang.fu@ingenic.com>
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++#include <linux/init.h>
++#include <linux/spinlock.h>
++#include <linux/workqueue.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/sched.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/gpio.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++#include <linux/mtd/nand.h>
++#include <asm/uaccess.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++#include "ingenic_sfc_drv.h"
++#include "sfc.h"
++#include "sfc_flash.h"
++#include "ingenic_sfc_common.h"
++
++
++#define is_nor_type(a)          ((a[0]==0x55) && (a[1]==0xaa) && (a[2]==0x55) && (a[3]==0xaa))
++#define is_nand_type(a)         ((a[0]==0x55) && (a[1]==0xaa) && (a[2]==0x55) && (a[3]==0x00))
++
++unsigned int flash_type = -1;
++static int __init flash_type_get(char *str)
++{
++	if(!strcmp(str,"nand"))
++		flash_type = NAND;
++	if(!strcmp(str,"nor"))
++		flash_type = NOR;
++	return 0;
++}
++early_param("flashtype", flash_type_get);
++
++static const struct of_device_id ingenic_sfc_match[];
++
++static int __init ingenic_sfc_probe(struct platform_device *pdev)
++{
++	struct sfc_flash *flash;
++	int ret = 0;
++	const struct of_device_id *of_match;
++	struct sfc_data *data = NULL;
++
++	flash = kzalloc(sizeof(struct sfc_flash), GFP_KERNEL);
++	if (IS_ERR_OR_NULL(flash))
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, flash);
++	flash->dev = &pdev->dev;
++
++	of_match = of_match_node( ingenic_sfc_match, pdev->dev.of_node);
++	if(IS_ERR_OR_NULL(of_match))
++	{
++		kfree(flash);
++		return -ENODEV;
++	}
++
++	data = (struct sfc_data *)of_match->data;
++
++	ret = of_property_read_u32(pdev->dev.of_node, "ingenic,sfc-init-frequency", (unsigned int *)&flash->sfc_init_frequency);
++	if (ret < 0) {
++		dev_err(flash->dev, "Cannot get sfc init frequency\n");
++	}
++
++	ret = of_property_read_u32(pdev->dev.of_node, "ingenic,sfc-max-frequency", (unsigned int *)&flash->sfc_max_frequency);
++	if (ret < 0) {
++		dev_err(flash->dev, "Cannot get sfc max frequency\n");
++		kfree(flash);
++		return -ENOENT;
++	}
++
++	flash->sfc = sfc_res_init(pdev);
++	if(IS_ERR(flash->sfc)) {
++		dev_err(flash->dev, "sfc control init error!\n");
++		kfree(flash);
++		return PTR_ERR(flash->sfc);
++	}
++
++	flash->pdata_params = pdev->dev.platform_data;
++
++	mutex_init(&flash->lock);
++
++	if(flash_type == -1){						/*flash type is not declared in bootargs */
++		flash_type = data->flash_type_auto_detect(pdev);
++	}
++
++	switch(flash_type)
++	{
++		case NAND:
++			ret = ingenic_sfc_nand_probe(flash);
++			break;
++		case NOR:
++			ret = ingenic_sfc_nor_probe(flash);
++			break;
++		default:
++			dev_err(&pdev->dev, "unknown flash type");
++			ret = -EINVAL;
++	}
++	if(ret){
++		kfree(flash);
++		return ret;
++	}
++
++	return 0;
++}
++
++static int __exit ingenic_sfc_remove(struct platform_device *pdev)
++{
++	struct sfc_flash *flash = platform_get_drvdata(pdev);
++	struct sfc *sfc = flash->sfc;
++
++	clk_disable_unprepare(sfc->clk_gate);
++	clk_put(sfc->clk_gate);
++	clk_disable_unprepare(sfc->clk);
++	clk_put(sfc->clk);
++	free_irq(sfc->irq, flash);
++	iounmap(sfc->iomem);
++	release_mem_region(sfc->ioarea->start, resource_size(sfc->ioarea));
++	platform_set_drvdata(pdev, NULL);
++	free_sfc_desc(sfc);
++
++	if(flash_type == NAND){
++		dma_free_coherent(flash->dev, flash->mtd.writesize, flash->sfc->tmp_buffer, flash->sfc->tbuff_pyaddr);
++#ifdef CONFIG_INGENIC_SFCNAND_FMW
++		sysfs_remove_group(&pdev->dev.kobj, flash->attr_group);
++#endif
++	} else if(flash_type == NOR)
++		sysfs_remove_group(&pdev->dev.kobj, flash->attr_group);
++	else{
++		dev_err(&pdev->dev, "unknown flash type!\n");
++		return -EINVAL;
++	}
++	return 0;
++}
++
++
++static int ingenic_sfc_suspend(struct platform_device *pdev, pm_message_t msg)
++{
++	struct sfc_flash *flash = platform_get_drvdata(pdev);
++	struct sfc *sfc = flash->sfc;
++
++	/* 1.Memory power OFF */
++	/*(*(volatile unsigned int *)0xb00000f8) |= (1 << 26);*/
++
++	/* 2.Irq OFF */
++	disable_irq(sfc->irq);
++
++	/* 3.Clk OFF */
++	clk_disable_unprepare(sfc->clk_gate);
++	clk_disable_unprepare(sfc->clk);
++
++	return 0;
++}
++
++static int ingenic_sfc_resume(struct platform_device *pdev)
++{
++	struct sfc_flash *flash = platform_get_drvdata(pdev);
++	struct sfc *sfc = flash->sfc;
++
++	/* 1.Clk ON */
++	clk_prepare_enable(sfc->clk);
++	clk_prepare_enable(sfc->clk_gate);
++
++	/* 2.Irq ON */
++	enable_irq(sfc->irq);
++
++	/* 3.Memory power ON */
++	/*(*(volatile unsigned int *)0xb00000f8) &= ~(1 << 26);*/
++
++	flash->create_cdt_table(flash->sfc, flash->flash_info, DEFAULT_CDT | UPDATE_CDT);
++
++	return 0;
++}
++
++void ingenic_sfc_shutdown(struct platform_device *pdev)
++{
++	struct sfc_flash *flash = platform_get_drvdata(pdev);
++	struct sfc *sfc = flash->sfc;
++
++	disable_irq(sfc->irq);
++	clk_disable_unprepare(sfc->clk_gate);
++	clk_disable_unprepare(sfc->clk);
++	return ;
++}
++
++int flash_type_auto_detect_from_tcsm(struct platform_device *pdev)
++{
++	volatile unsigned char *t;
++	int ret;
++
++	t = (volatile unsigned char *)(0xb2401005);
++
++	if (is_nand_type(t))
++		ret = NAND;
++	else if (is_nor_type(t))
++		ret = NOR;
++	else
++		ret = -EINVAL;
++
++	return ret;
++}
++
++int flash_type_auto_detect_from_ddr(struct platform_device *pdev)
++{
++	volatile unsigned char *t;
++	int ret;
++
++	t = (volatile unsigned char *)(0x80001005);
++
++	if (is_nand_type(t))
++		ret = NAND;
++	else if (is_nor_type(t))
++		ret = NOR;
++	else
++		ret = -EINVAL;
++
++	return ret;
++}
++
++struct sfc_data x2000_sfc_priv = {
++	.flash_type_auto_detect = flash_type_auto_detect_from_tcsm,
++};
++
++struct sfc_data m300_sfc_priv = {
++	.flash_type_auto_detect = flash_type_auto_detect_from_tcsm,
++};
++
++struct sfc_data x2500_sfc_priv = {
++	.flash_type_auto_detect = flash_type_auto_detect_from_ddr,
++};
++
++struct sfc_data x1600_sfc_priv = {
++	.flash_type_auto_detect = flash_type_auto_detect_from_ddr,
++};
++
++static const struct of_device_id ingenic_sfc_match[] = {
++	{ .compatible = "ingenic,x2000-sfc",
++	  .data = &x2000_sfc_priv, },
++	{ .compatible = "ingenic,m300-sfc",
++	  .data = &m300_sfc_priv, },
++	{ .compatible = "ingenic,x2500-sfc",
++	  .data = &x2500_sfc_priv, },
++	{ .compatible = "ingenic,x1600-sfc",
++	  .data = &x1600_sfc_priv, },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ingenic_sfc_match);
++
++static struct platform_driver ingenic_sfc_drv = {
++	.driver		= {
++		.name	= "ingenic-sfc",
++		.owner	= THIS_MODULE,
++		.of_match_table = ingenic_sfc_match,
++	},
++	.remove		= __exit_p(ingenic_sfc_remove),
++	.suspend	= ingenic_sfc_suspend,
++	.resume		= ingenic_sfc_resume,
++	.shutdown	= ingenic_sfc_shutdown,
++};
++module_platform_driver_probe(ingenic_sfc_drv, ingenic_sfc_probe);
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("INGENIC SFC Driver");
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_drv.h b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_drv.h
+new file mode 100644
+index 000000000..30c02f515
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_drv.h
+@@ -0,0 +1,18 @@
++#ifndef __INGENIC_SFC_H
++#define __INGENIC_SFC_H
++
++#include "sfc_flash.h"
++
++enum flash_type {
++	NAND,
++	NOR,
++};
++
++struct sfc_data {
++	int (*flash_type_auto_detect)(struct platform_device *pdev);
++};
++
++int ingenic_sfc_nand_probe(struct sfc_flash *flash);
++int ingenic_sfc_nor_probe(struct sfc_flash *flash);
++
++#endif
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_nand.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_nand.c
+new file mode 100644
+index 000000000..0f366dcd5
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_nand.c
+@@ -0,0 +1,1433 @@
++/*
++ * SFC controller for SPI protocol, use FIFO and DMA;
++ *
++ * Copyright (c) 2015 Ingenic
++ * Author: <xiaoyang.fu@ingenic.com>
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++#include <linux/init.h>
++#include <linux/spinlock.h>
++#include <linux/workqueue.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/sched.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/gpio.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++#include <linux/mtd/rawnand.h>
++#include <linux/mtd/nand.h>
++#include <asm/uaccess.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++#include "sfc_flash.h"
++#include "spinand.h"
++#include "ingenic_sfc_common.h"
++#include "./nand_device/nand_common.h"
++#include "internals.h"
++#include "ingenic_sfc_drv.h"
++
++
++#ifdef CONFIG_INGENIC_SFCNAND_FMW
++#include "fmw.h"
++
++struct sfc_flash *fmw_flash = NULL;
++EXPORT_SYMBOL_GPL(fmw_flash);
++#endif
++
++#define STATUS_SUSPND	(1<<0)
++#define to_ingenic_spi_nand(mtd_info) container_of(mtd_info, struct sfc_flash, mtd)
++
++/*
++ * below is the informtion about nand
++ * that user should modify according to nand spec
++ * */
++
++static LIST_HEAD(nand_list);
++
++void dump_flash_info(struct sfc_flash *flash)
++{
++	struct ingenic_sfcnand_flashinfo *nand_info = flash->flash_info;
++	struct ingenic_sfcnand_base_param *param = &nand_info->param;
++	struct mtd_partition *partition = nand_info->partition.partition;
++	uint8_t num_partition = nand_info->partition.num_partition;
++
++	printk("id_manufactory = 0x%02x\n", nand_info->id_manufactory);
++	printk("id_device = 0x%02x\n", nand_info->id_device);
++
++	printk("pagesize = %d\n", param->pagesize);
++	printk("blocksize = %d\n", param->blocksize);
++	printk("oobsize = %d\n", param->oobsize);
++	printk("flashsize = %d\n", param->flashsize);
++
++	printk("tHOLD = %d\n", param->tHOLD);
++	printk("tSETUP = %d\n", param->tSETUP);
++	printk("tSHSL_R = %d\n", param->tSHSL_R);
++	printk("tSHSL_W = %d\n", param->tSHSL_W);
++
++	printk("ecc_max = %d\n", param->ecc_max);
++	printk("need_quad = %d\n", param->need_quad);
++
++	while(num_partition--) {
++		printk("partition(%d) name=%s\n", num_partition, partition[num_partition].name);
++		printk("partition(%d) size = 0x%llx\n", num_partition, partition[num_partition].size);
++		printk("partition(%d) offset = 0x%llx\n", num_partition, partition[num_partition].offset);
++		printk("partition(%d) mask_flags = 0x%x\n", num_partition, partition[num_partition].mask_flags);
++	}
++	return;
++}
++
++static int badblk_check(int len, unsigned char *buf)
++{
++	int  j;
++	unsigned char *check_buf = buf;
++
++	for(j = 0; j < len; j++){
++		if(check_buf[j] != 0xff){
++			return 1;
++		}
++	}
++	return 0;
++}
++
++static int32_t sfcnand_do_read(struct sfc_flash *flash, struct flash_address *flash_address, u_char *buffer, size_t len)
++{
++	struct ingenic_sfcnand_flashinfo *nand_info = flash->flash_info;
++	struct ingenic_sfcnand_ops *ops = nand_info->ops;
++	struct sfc_cdt_xfer xfer;
++	int32_t ret = 0;
++
++	memset(&xfer, 0, sizeof(xfer));
++
++	/* set Index */
++	if(nand_info->param.need_quad){
++		xfer.cmd_index = NAND_QUAD_READ_TO_CACHE;
++	}else{
++		xfer.cmd_index = NAND_STANDARD_READ_TO_CACHE;
++	}
++
++	/* set addr */
++	xfer.rowaddr = flash_address->pageaddr;
++
++	if(nand_info->param.plane_select){
++		xfer.columnaddr = CONVERT_COL_ADDR(flash_address->pageaddr, flash_address->columnaddr);
++	}else{
++		xfer.columnaddr = flash_address->columnaddr;
++	}
++
++	xfer.staaddr0 = SPINAND_ADDR_STATUS;
++
++	/* set transfer config */
++	xfer.dataen = ENABLE;
++	xfer.config.datalen = len;
++	xfer.config.data_dir = GLB0_TRAN_DIR_READ;
++	xfer.config.ops_mode = flash_address->ops_mode;
++	xfer.config.buf = buffer;
++
++retry:
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		dev_err(flash->dev,"sfc_sync_cdt error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++		return -EIO;
++	}
++
++	/* if underrun, retry read */
++	if (flash->sfc->retry_count > 0) {
++		dev_warn(flash->dev,"SFC retry transfer! %s %s %d\n",__FILE__,__func__,__LINE__);
++		goto retry;
++	}
++
++	/* get status to check nand ecc status */
++	ret = ops->get_feature(flash, GET_ECC_STATUS);
++
++	if(xfer.config.ops_mode == DMA_OPS) {
++		dma_sync_single_for_device(flash->dev, (dma_addr_t)(sfc_get_paddr((void *)xfer.config.buf)), xfer.config.datalen, DMA_FROM_DEVICE);
++	}
++
++	return ret;
++}
++
++static int32_t sfcnand_do_write(struct sfc_flash *flash, u_char *buffer, struct flash_address *flash_address, size_t len)
++{
++	struct ingenic_sfcnand_flashinfo *nand_info = flash->flash_info;
++	struct ingenic_sfcnand_ops *ops = nand_info->ops;
++	struct sfc_cdt_xfer xfer;
++	int32_t ret = 0;
++
++	memset(&xfer, 0, sizeof(xfer));
++
++	/* set Index */
++	if(nand_info->param.need_quad){
++		xfer.cmd_index = NAND_QUAD_WRITE_ENABLE;
++	}else{
++		xfer.cmd_index = NAND_STANDARD_WRITE_ENABLE;
++	}
++
++	/* set addr */
++	xfer.rowaddr = flash_address->pageaddr;
++
++	if(nand_info->param.plane_select){
++		xfer.columnaddr = CONVERT_COL_ADDR(flash_address->pageaddr, flash_address->columnaddr);
++	}else{
++		xfer.columnaddr = flash_address->columnaddr;
++	}
++
++	xfer.staaddr0 = SPINAND_ADDR_STATUS;
++
++	/* set transfer config */
++	xfer.dataen = ENABLE;
++	xfer.config.datalen = len;
++	xfer.config.data_dir = GLB0_TRAN_DIR_WRITE;
++	xfer.config.ops_mode = flash_address->ops_mode;
++	xfer.config.buf = buffer;
++
++retry:
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		dev_err(flash->dev,"sfc_sync_cdt error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++		return -EIO;
++	}
++
++	/* if overrun, retry write */
++	if (flash->sfc->retry_count > 0) {
++		dev_warn(flash->dev,"SFC retry transfer! %s %s %d\n",__FILE__,__func__,__LINE__);
++		goto retry;
++	}
++
++	/* get status to be sure nand write completed */
++	ret = ops->get_feature(flash, GET_WRITE_STATUS);
++
++	return  ret;
++}
++
++static int32_t sfcnand_do_erase(struct sfc_flash *flash, uint32_t pageaddr)
++{
++	struct ingenic_sfcnand_flashinfo *nand_info = flash->flash_info;
++	struct ingenic_sfcnand_ops *ops = nand_info->ops;
++	struct sfc_cdt_xfer xfer;
++	int32_t ret = 0;
++
++	memset(&xfer, 0, sizeof(xfer));
++
++	/* set index */
++	xfer.cmd_index = NAND_ERASE_WRITE_ENABLE;
++
++	/* set addr */
++	xfer.rowaddr = pageaddr;
++	xfer.staaddr0 = SPINAND_ADDR_STATUS;
++
++	/* set transfer config */
++	xfer.dataen = DISABLE;
++
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		dev_err(flash->dev,"sfc_sync_cdt error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++		return -EIO;
++	}
++
++	/* get status to be sure nand write completed */
++	ret = ops->get_feature(flash, GET_ERASE_STATUS);
++	if(ret){
++		dev_err(flash->dev, "Erase error, get state error ! %s %s %d \n",__FILE__,__func__,__LINE__);
++	}
++
++	return ret;
++}
++
++
++static int ingenic_sfcnand_erase(struct mtd_info *mtd, struct erase_info *instr)
++{
++	struct sfc_flash *flash = to_ingenic_spi_nand(mtd);
++	uint32_t addr = (uint32_t)instr->addr;
++	uint32_t end;
++	int32_t ret;
++
++	if(addr % mtd->erasesize) {
++		dev_err(flash->dev, "ERROR:%s line %d eraseaddr no align\n", __func__,__LINE__);
++		return -EINVAL;
++	}
++	end = addr + instr->len;
++	mutex_lock(&flash->lock);
++	while (addr < end) {
++		if((ret = sfcnand_do_erase(flash, addr / mtd->writesize))) {
++			dev_err(flash->dev, "spi nand erase error blk id  %d !\n",addr / mtd->erasesize);
++			goto erase_exit;
++		}
++		addr += mtd->erasesize;
++	}
++
++erase_exit:
++	mutex_unlock(&flash->lock);
++	return ret;
++}
++
++static int ingenic_sfcnand_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
++{
++	struct sfc_flash *flash = to_ingenic_spi_nand(mtd);
++	uint32_t pagesize = mtd->writesize;
++	uint32_t pageaddr;
++	uint32_t columnaddr;
++	uint32_t rlen;
++	size_t align_len;
++	u_char* pbuf;
++	struct flash_address flash_address;
++	int32_t ret = 0, reterr = 0, ret_eccvalue = 0;
++
++	while(len) {
++		pageaddr = (uint32_t)from / pagesize;
++		columnaddr = (uint32_t)from % pagesize;
++		rlen = min_t(uint32_t, len, pagesize - columnaddr);
++
++		/* align length */
++		align_len = ALIGN(rlen, 4);
++
++		/* create DMA Descriptors */
++		if (align_len != rlen) {
++			align_len -= 4;
++			pbuf = flash->sfc->tmp_buffer;
++		} else {
++			pbuf = buf;
++		}
++
++		if (align_len > 0) {
++			flash_address.pageaddr = pageaddr;
++			flash_address.columnaddr = columnaddr;
++			flash_address.ops_mode = DMA_OPS;
++
++			ret = create_sfc_desc(flash->sfc, pbuf, align_len);
++			if(ret < 0){
++				dev_err(flash->dev, "%s create descriptors error. -%d\n", __func__, ret);
++				reterr = ret;
++				goto read_exit;
++			}
++
++		/* DMA Descriptors read */
++			ret = sfcnand_do_read(flash, &flash_address, buf, align_len);
++			if(ret < 0) {
++				dev_err(flash->dev, "%s %s %d: sfcnand_do_read error, ret = %d, \
++						pageaddr = %u, columnaddr = %u, rlen = %u\n",
++						__FILE__, __func__, __LINE__,
++						ret, pageaddr, columnaddr, align_len);
++				reterr = ret;
++				if(ret == -EIO)
++					break;
++			} else if (ret > 0) {
++				dev_dbg(flash->dev, "%s %s %d: sfcnand_do_read, ecc value = %d, \
++						pageaddr = %u, columnaddr = %u, rlen = %u\n",
++						__FILE__, __func__, __LINE__,
++						ret, pageaddr, columnaddr, align_len);
++				ret_eccvalue = ret;
++			}
++		}
++
++		if (align_len != rlen) {
++
++			if (align_len > 0) {
++				memcpy(buf, pbuf, align_len);
++			}
++
++			flash_address.pageaddr = pageaddr;
++			flash_address.columnaddr = columnaddr + align_len;
++			flash_address.ops_mode = CPU_OPS;
++
++			ret = sfcnand_do_read(flash, &flash_address, (u_char *)buf + align_len, rlen - align_len);
++			if(ret < 0) {
++				dev_err(flash->dev, "%s %s %d: sfcnand_do_read error, ret = %d, \
++						pageaddr = %u, columnaddr = %u, rlen = %u\n",
++						__FILE__, __func__, __LINE__,
++						ret, flash_address.pageaddr, flash_address.columnaddr, rlen - align_len);
++				reterr = ret;
++				if(ret == -EIO)
++					break;
++			} else if (ret > 0) {
++				dev_dbg(flash->dev, "%s %s %d: sfcnand_do_read, ecc value = %d, \
++						pageaddr = %u, columnaddr = %u, rlen = %u\n",
++						__FILE__, __func__, __LINE__,
++						ret, flash_address.pageaddr, flash_address.columnaddr, rlen - align_len);
++				ret_eccvalue = ret;
++			}
++
++		}
++
++		len -= rlen;
++		from += rlen;
++		buf += rlen;
++		*retlen += rlen;
++	}
++
++read_exit:
++	return reterr ? reterr : (ret_eccvalue ? ret_eccvalue : ret);
++}
++
++static int ingenic_sfcnand_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf)
++{
++	struct sfc_flash *flash = to_ingenic_spi_nand(mtd);
++	uint32_t pagesize = mtd->writesize;
++	uint32_t pageaddr;
++	uint32_t columnaddr;
++	uint32_t wlen;
++	struct flash_address flash_address;
++	int32_t ret;
++
++	while(len) {
++		pageaddr = (uint32_t)to / pagesize;
++		columnaddr = (uint32_t)to % pagesize;
++		wlen = min_t(uint32_t, pagesize - columnaddr, len);
++
++		flash_address.pageaddr = pageaddr;
++		flash_address.columnaddr = columnaddr;
++		flash_address.ops_mode = DMA_OPS;
++
++		/* create DMA Descriptors */
++		ret = create_sfc_desc(flash->sfc, (unsigned char *)buf, wlen);
++		if(ret < 0){
++			dev_err(flash->dev, "%s create descriptors error. -%d\n", __func__, ret);
++			goto write_exit;
++		}
++
++		/* DMA Descriptors write */
++		if((ret = sfcnand_do_write(flash, (u_char *)buf, &flash_address, wlen))) {
++			dev_err(flash->dev, "%s %s %d : spi nand write fail, ret = %d, \
++				pageaddr = %u, columnaddr = %u, wlen = %u\n",
++				__FILE__, __func__, __LINE__, ret,
++				pageaddr, columnaddr, wlen);
++			break;
++		}
++		*retlen += wlen;
++		len -= wlen;
++		to += wlen;
++		buf += wlen;
++	}
++
++write_exit:
++	return ret;
++}
++
++static int ingenic_sfcnand_write_oob(struct mtd_info *mtd, loff_t addr, struct mtd_oob_ops *ops)
++{
++	struct sfc_flash *flash = to_ingenic_spi_nand(mtd);
++	uint32_t oob_addr = (uint32_t)addr;
++	struct flash_address flash_address;
++	int32_t ret;
++
++	mutex_lock(&flash->lock);
++
++	if(ops->datbuf) {
++		ret = ingenic_sfcnand_write(mtd, addr, ops->len, &ops->retlen, ops->datbuf);
++	}
++	if (ops->oobbuf) {
++		flash_address.pageaddr = oob_addr / mtd->writesize;
++		flash_address.columnaddr =  mtd->writesize;
++		flash_address.ops_mode = DMA_OPS;
++
++		/* create DMA Descriptors */
++		ret = create_sfc_desc(flash->sfc, (unsigned char *)ops->oobbuf, ops->ooblen);
++		if(ret < 0){
++			dev_err(flash->dev, "%s create descriptors error. -%d\n", __func__, ret);
++			goto write_oob_exit;
++		}
++
++		if((ret = sfcnand_do_write(flash, ops->oobbuf, &flash_address, ops->ooblen))) {
++			dev_err(flash->dev, "spi nand write oob error %s %s %d \n",__FILE__,__func__,__LINE__);
++			goto write_oob_exit;
++		}
++		ops->oobretlen = ops->ooblen;
++	}
++
++write_oob_exit:
++	mutex_unlock(&flash->lock);
++	return ret;
++}
++
++static int32_t ingenic_sfcnand_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops)
++{
++	struct sfc_flash *flash = to_ingenic_spi_nand(mtd);
++	uint32_t addr = (uint32_t)from;
++	int32_t ret = 0, ret_eccvalue = 0;
++	struct flash_address flash_address;
++
++	mutex_lock(&flash->lock);
++	if(ops->datbuf) {
++		ret = ingenic_sfcnand_read(mtd, from, ops->len, &ops->retlen, ops->datbuf);
++	}
++
++	if(ops->oobbuf) {
++		flash_address.pageaddr = addr / mtd->writesize;
++		flash_address.columnaddr = mtd->writesize + ops->ooboffs;
++		flash_address.ops_mode = DMA_OPS;
++
++		/* create DMA Descriptors */
++		ret = create_sfc_desc(flash->sfc, (unsigned char *)ops->oobbuf, ops->ooblen);
++		if(ret < 0){
++			dev_err(flash->dev, "%s create descriptors error. -%d\n", __func__, ret);
++			goto read_oob_exit;
++		}
++
++		ret = sfcnand_do_read(flash, &flash_address, ops->oobbuf, ops->ooblen);
++		if(ret < 0)
++			dev_err(flash->dev, "%s %s %d : spi nand read oob error ,ret= %d\n", __FILE__, __func__, __LINE__, ret);
++
++		if(ret != -EIO)
++			ops->oobretlen = ops->ooblen;
++
++	}
++
++read_oob_exit:
++	mutex_unlock(&flash->lock);
++
++	return ret ? ret : ret_eccvalue;
++}
++
++static int ingenic_sfcnand_chip_block_markbad(struct mtd_info *mtd, loff_t ofs)
++{
++	struct nand_chip *chip = mtd->priv;
++	uint8_t buf[2] = { 0, 0 };
++	int  ret = 0, i = 0;
++	int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
++
++	/* Write bad block marker to OOB */
++	if (write_oob) {
++		struct mtd_oob_ops ops;
++		loff_t wr_ofs = ofs;
++		ops.datbuf = NULL;
++		ops.oobbuf = buf;
++		ops.ooboffs = chip->badblockpos;
++		if (chip->options & NAND_BUSWIDTH_16) {
++			ops.ooboffs &= ~0x01;
++			ops.len = ops.ooblen = 2;
++		} else {
++			ops.len = ops.ooblen = 1;
++		}
++		ops.mode = MTD_OPS_PLACE_OOB;
++
++		/* Write to first/last page(s) if necessary */
++		if (chip->bbt_options & NAND_BBM_LASTPAGE)
++			wr_ofs += mtd->erasesize - mtd->writesize;
++		do {
++			ret = ingenic_sfcnand_write_oob(mtd, wr_ofs, &ops);
++			if (ret)
++				return ret;
++			wr_ofs += mtd->writesize;
++			i++;
++		} while ((chip->bbt_options & (NAND_BBM_FIRSTPAGE || NAND_BBM_SECONDPAGE)) && i < 2);
++	}
++	/* Update flash-based bad block table */
++	if (chip->bbt_options & NAND_BBT_USE_FLASH) {
++		ret = nand_markbad_bbt(chip, ofs);
++	}
++
++	return ret;
++}
++
++static int ingenic_sfcnand_block_bad_check(struct mtd_info *mtd, loff_t ofs)
++{
++	int check_len = 1;
++	unsigned char check_buf[2] = {0x0};
++	struct nand_chip *chip = (struct nand_chip *)mtd->priv;
++	struct mtd_oob_ops ops;
++
++	memset(&ops, 0, sizeof(ops));
++	if (chip->options & NAND_BUSWIDTH_16)
++		check_len = 2;
++
++	ops.oobbuf = check_buf;
++	ops.ooblen = check_len;
++	ingenic_sfcnand_read_oob(mtd, ofs, &ops);
++	if(badblk_check(check_len, check_buf))
++		return 1;
++	return 0;
++}
++
++static int ingenic_sfcnand_block_isbab(struct mtd_info *mtd, loff_t ofs)
++{
++	struct nand_chip *chip = mtd->priv;
++	if(!chip->bbt) {
++		return ingenic_sfcnand_block_bad_check(mtd, ofs);
++	}
++	return nand_isbad_bbt(chip, ofs, 0);
++}
++
++static int ingenic_sfcnand_block_markbad(struct mtd_info *mtd, loff_t ofs)
++{
++	int ret = ingenic_sfcnand_block_isbab(mtd, ofs);
++	if(ret > 0) {
++		/* If it was bad already, return success and do nothing */
++			return 0;
++	}
++	return ingenic_sfcnand_chip_block_markbad(mtd, ofs);
++}
++
++static int ingenic_sfc_nand_set_feature(struct sfc_flash *flash, uint8_t addr, uint32_t val)
++{
++	struct sfc_cdt_xfer xfer;
++	memset(&xfer, 0, sizeof(xfer));
++
++	/* set index */
++	xfer.cmd_index = NAND_SET_FEATURE;
++
++	/* set addr */
++	xfer.staaddr0 = addr;
++
++	/* set transfer config */
++	xfer.dataen = ENABLE;
++	xfer.config.datalen = 1;
++	xfer.config.data_dir = GLB0_TRAN_DIR_WRITE;
++	xfer.config.ops_mode = CPU_OPS;
++	xfer.config.buf = (uint8_t *)&val;
++
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		dev_err(flash->dev,"sfc_sync_cdt error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++		return -EIO;
++	}
++
++	return 0;
++}
++
++static int ingenic_sfc_nand_get_feature(struct sfc_flash *flash, uint8_t addr, uint8_t *val)
++{
++	struct sfc_cdt_xfer xfer;
++	memset(&xfer, 0, sizeof(xfer));
++
++	/* set index */
++	xfer.cmd_index = NAND_GET_FEATURE;
++
++	/* set addr */
++	xfer.staaddr0 = addr;
++
++	/* set transfer config */
++	xfer.dataen = ENABLE;
++	xfer.config.datalen = 1;
++	xfer.config.data_dir = GLB0_TRAN_DIR_READ;
++	xfer.config.ops_mode = CPU_OPS;
++	xfer.config.buf = (uint8_t *)val;
++
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		dev_err(flash->dev,"sfc_sync_cdt error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++		return -EIO;
++	}
++
++	return 0;
++}
++
++static int32_t __init ingenic_sfc_nand_dev_init(struct sfc_flash *flash)
++{
++	int32_t ret;
++	/*release protect*/
++	uint8_t feature = 0;
++	if((ret = ingenic_sfc_nand_set_feature(flash, SPINAND_ADDR_PROTECT, feature)))
++		goto exit;
++
++	if((ret = ingenic_sfc_nand_get_feature(flash, SPINAND_ADDR_FEATURE, &feature)))
++		goto exit;
++
++	feature |= (1 << 4) | (1 << 3) | (1 << 0);
++	if((ret = ingenic_sfc_nand_set_feature(flash, SPINAND_ADDR_FEATURE, feature)))
++		goto exit;
++
++	return 0;
++exit:
++	return ret;
++}
++
++static int32_t __init ingenic_sfc_nand_try_id(struct sfc_flash *flash)
++{
++	struct ingenic_sfcnand_flashinfo *nand_info = flash->flash_info;
++	struct ingenic_sfcnand_device *nand_device;
++	struct sfc_cdt_xfer xfer;
++	uint8_t id_buf[2] = {0};
++	unsigned short index[2] = {NAND_TRY_ID, NAND_TRY_ID_DMY};
++	uint8_t i = 0;
++	struct device_id_struct *device_id = NULL;
++	int32_t id_count = 0;
++
++	for(i = 0; i < 2; i++){
++		memset(&xfer, 0, sizeof(xfer));
++
++		/* set index */
++		xfer.cmd_index = index[i];
++
++		/* set addr */
++		xfer.rowaddr = 0;
++
++		/* set transfer config */
++		xfer.dataen = ENABLE;
++		xfer.config.datalen = sizeof(id_buf);
++		xfer.config.data_dir = GLB0_TRAN_DIR_READ;
++		xfer.config.ops_mode = CPU_OPS;
++		xfer.config.buf = id_buf;
++
++		if(sfc_sync_cdt(flash->sfc, &xfer)) {
++			dev_err(flash->dev,"sfc_sync_cdt error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++			return -EIO;
++		}
++
++		dev_info(flash->dev, "id_manufactory = %x, id_device %x\n", id_buf[0], id_buf[1]);
++		list_for_each_entry(nand_device, &nand_list, list) {
++			if(nand_device->id_manufactory == id_buf[0]) {
++				device_id = nand_device->id_device_list;
++				id_count = nand_device->id_device_count;
++				while(id_count--) {
++					if(device_id->id_device == id_buf[1]) {
++						nand_info->id_manufactory = id_buf[0];
++						nand_info->id_device = id_buf[1];
++						nand_info->param = *device_id->param;
++						goto found_param;
++					}
++					device_id++;
++				}
++			}
++		}
++	}
++
++	if(!nand_info->id_manufactory && !nand_info->id_device) {
++		dev_err(flash->dev, " ERROR!: don`t support this nand manufactory, please add nand driver.\n");
++		return -ENODEV;
++	}
++
++found_param:
++	dev_info(flash->dev, "Found Supported device, id_manufactory = 0x%02x, id_device = 0x%02x\n", nand_info->id_manufactory, nand_info->id_device);
++
++	/* fill manufactory special operation and cdt params */
++	nand_info->ops = &nand_device->ops;
++	nand_info->cdt_params = nand_info->ops->get_cdt_params(flash, nand_info->id_device);
++
++	if (!nand_info->ops->get_feature) {
++		if (!nand_info->ops->deal_ecc_status) {
++			dev_err(flash->dev,"ERROR:xxx_nand.c \"get_feature()\" and \"deal_ecc_status()\" not define.\n");
++			return -ENODEV;
++		} else {
++			nand_info->ops->get_feature = nand_common_get_feature;
++			printk("use nand common get feature interface!\n");
++		}
++	} else {
++		printk("use nand private get feature interface!\n");
++	}
++
++	return 0;
++}
++
++static int32_t __init nand_partition_param_copy(struct sfc_flash *flash, struct ingenic_sfcnand_burner_param *burn_param) {
++	struct ingenic_sfcnand_flashinfo *nand_info = flash->flash_info;
++	int i = 0, count = 5, ret;
++	size_t retlen = 0;
++
++	/* partition param copy */
++	nand_info->partition.num_partition = burn_param->partition_num;
++
++	burn_param->partition = kzalloc(nand_info->partition.num_partition * sizeof(struct ingenic_sfcnand_partition), GFP_KERNEL);
++	if (IS_ERR_OR_NULL(burn_param->partition)) {
++	    	dev_err(flash->dev, "alloc partition space failed!\n");
++			return -ENOMEM;
++	}
++
++	nand_info->partition.partition = kzalloc(nand_info->partition.num_partition * sizeof(struct mtd_partition), GFP_KERNEL);
++	if (IS_ERR_OR_NULL(nand_info->partition.partition)) {
++	    	dev_err(flash->dev, "alloc partition space failed!\n");
++		kfree(burn_param->partition);
++		return -ENOMEM;
++	}
++
++partition_retry_read:
++	ret = ingenic_sfcnand_read(&flash->mtd, flash->param_offset + sizeof(*burn_param) - sizeof(burn_param->partition),
++		nand_info->partition.num_partition * sizeof(struct ingenic_sfcnand_partition),
++		&retlen, (u_char *)burn_param->partition);
++
++	if((ret < 0) && count--)
++		goto partition_retry_read;
++	if(count < 0) {
++		dev_err(flash->dev, "read nand partition failed!\n");
++		kfree(burn_param->partition);
++		kfree(nand_info->partition.partition);
++		return -EIO;
++	}
++
++	for(i = 0; i < burn_param->partition_num; i++) {
++		nand_info->partition.partition[i].name = burn_param->partition[i].name;
++		nand_info->partition.partition[i].size = burn_param->partition[i].size;
++		nand_info->partition.partition[i].offset = burn_param->partition[i].offset;
++		nand_info->partition.partition[i].mask_flags = burn_param->partition[i].mask_flags;
++	}
++	return 0;
++}
++
++static struct ingenic_sfcnand_burner_param *burn_param;
++static int32_t __init flash_part_from_chip(struct sfc_flash *flash) {
++
++	int32_t ret = 0, retlen = 0, count = 5;
++
++	burn_param = kzalloc(sizeof(struct ingenic_sfcnand_burner_param), GFP_KERNEL);
++	if(IS_ERR_OR_NULL(burn_param)) {
++		dev_err(flash->dev, "alloc burn_param space error!\n");
++		return -ENOMEM;
++	}
++
++	count = 5;
++param_retry_read:
++	ret = ingenic_sfcnand_read(&flash->mtd, flash->param_offset,
++		sizeof(struct ingenic_sfcnand_burner_param), &retlen, (u_char *)burn_param);
++	if((ret < 0) && count--)
++		goto param_retry_read;
++	if(count < 0) {
++		dev_err(flash->dev, "read nand base param failed!\n");
++		ret = -EIO;
++		goto failed;
++	}
++
++	if(burn_param->magic_num != SPINAND_MAGIC_NUM) {
++		dev_info(flash->dev, "NOTICE: this flash haven`t param, magic_num:%x\n", burn_param->magic_num);
++		ret = -EINVAL;
++		goto failed;
++	}
++
++	if(nand_partition_param_copy(flash, burn_param)) {
++		ret = -ENOMEM;
++		goto failed;
++	}
++
++	return 0;
++failed:
++	kfree(burn_param);
++	return ret;
++
++}
++
++
++static int32_t __init ingenic_sfcnand_partition(struct sfc_flash *flash) {
++	int32_t ret = 0;
++	if((ret = flash_part_from_chip(flash))) {
++		dev_err(flash->dev, "read partition from flash failed!\n");
++	}
++	return ret;
++}
++
++int ingenic_sfcnand_register(struct ingenic_sfcnand_device *flash) {
++	list_add_tail(&flash->list, &nand_list);
++	return 0;
++}
++EXPORT_SYMBOL_GPL(ingenic_sfcnand_register);
++
++/*
++ *MK_CMD(cdt, cmd, LINK, ADDRMODE, DATA_EN)
++ *MK_ST(cdt, st, LINK, ADDRMODE, ADDR_WIDTH, POLL_EN, DATA_EN, TRAN_MODE)
++ */
++static void params_to_cdt(cdt_params_t *params, struct sfc_cdt *cdt)
++{
++	/* 6. nand standard read */
++	MK_CMD(cdt[NAND_STANDARD_READ_TO_CACHE], params->r_to_cache, 1, ROW_ADDR, DISABLE);
++	MK_ST(cdt[NAND_STANDARD_READ_GET_FEATURE], params->oip, 1, STA_ADDR0, 1, ENABLE, DISABLE, TM_STD_SPI);
++	MK_CMD(cdt[NAND_STANDARD_READ_FROM_CACHE], params->standard_r, 0, COL_ADDR, ENABLE);
++
++	/* 7. nand quad read */
++	MK_CMD(cdt[NAND_QUAD_READ_TO_CACHE], params->r_to_cache, 1, ROW_ADDR, DISABLE);
++	MK_ST(cdt[NAND_QUAD_READ_GET_FEATURE], params->oip, 1, STA_ADDR0, 1, ENABLE, DISABLE, TM_STD_SPI);
++	MK_CMD(cdt[NAND_QUAD_READ_FROM_CACHE], params->quad_r, 0, COL_ADDR, ENABLE);
++
++	/* 8. nand standard write */
++	MK_CMD(cdt[NAND_STANDARD_WRITE_ENABLE], params->w_en, 1, DEFAULT_ADDRMODE, DISABLE);
++	MK_CMD(cdt[NAND_STANDARD_WRITE_TO_CACHE], params->standard_w_cache, 1, COL_ADDR, ENABLE);
++	MK_CMD(cdt[NAND_STANDARD_WRITE_EXEC], params->w_exec, 1, ROW_ADDR, DISABLE);
++	MK_ST(cdt[NAND_STANDARD_WRITE_GET_FEATURE], params->oip, 0, STA_ADDR0, 1, ENABLE, DISABLE, TM_STD_SPI);
++
++	/* 9. nand quad write */
++	MK_CMD(cdt[NAND_QUAD_WRITE_ENABLE], params->w_en, 1, DEFAULT_ADDRMODE, DISABLE);
++	MK_CMD(cdt[NAND_QUAD_WRITE_TO_CACHE], params->quad_w_cache, 1, COL_ADDR, ENABLE);
++	MK_CMD(cdt[NAND_QUAD_WRITE_EXEC], params->w_exec, 1, ROW_ADDR, DISABLE);
++	MK_ST(cdt[NAND_QUAD_WRITE_GET_FEATURE], params->oip, 0, STA_ADDR0, 1, ENABLE, DISABLE, TM_STD_SPI);
++
++	/* 10. block erase */
++	MK_CMD(cdt[NAND_ERASE_WRITE_ENABLE], params->w_en, 1, DEFAULT_ADDRMODE, DISABLE);
++	MK_CMD(cdt[NAND_BLOCK_ERASE], params->b_erase, 1, ROW_ADDR, DISABLE);
++	MK_ST(cdt[NAND_ERASE_GET_FEATURE], params->oip, 0, STA_ADDR0, 1, ENABLE, DISABLE, TM_STD_SPI);
++
++	/* 11. ecc status read */
++	MK_CMD(cdt[NAND_ECC_STATUS_READ], params->ecc_r, 0, DEFAULT_ADDRMODE, ENABLE);
++
++}
++
++static void nand_create_cdt_table(struct sfc *sfc, void *flash_info, uint32_t flag)
++{
++	struct ingenic_sfcnand_flashinfo *nand_info = flash_info;
++	cdt_params_t *cdt_params;
++	struct sfc_cdt sfc_cdt[INDEX_MAX_NUM];
++
++	memset(sfc_cdt, 0, sizeof(sfc_cdt));
++	if(flag & DEFAULT_CDT){
++
++		/* 1. reset */
++		sfc_cdt[NAND_RESET].link = CMD_LINK(0, DEFAULT_ADDRMODE, TM_STD_SPI);
++		sfc_cdt[NAND_RESET].xfer = CMD_XFER(0, DISABLE, 0, DISABLE, SPINAND_CMD_RESET);
++		sfc_cdt[NAND_RESET].staExp = 0;
++		sfc_cdt[NAND_RESET].staMsk = 0;
++
++		/* 2. try id */
++		sfc_cdt[NAND_TRY_ID].link = CMD_LINK(0, DEFAULT_ADDRMODE, TM_STD_SPI);
++		sfc_cdt[NAND_TRY_ID].xfer = CMD_XFER(0, DISABLE, 0, ENABLE, SPINAND_CMD_RDID);
++		sfc_cdt[NAND_TRY_ID].staExp = 0;
++		sfc_cdt[NAND_TRY_ID].staMsk = 0;
++
++		/* 3. try id with dummy */
++		/*
++		 * There are some NAND flash, try ID operation requires 8-bit dummy value to be all 0,
++		 * so use 1 byte address instead of dummy here.
++		 */
++		sfc_cdt[NAND_TRY_ID_DMY].link = CMD_LINK(0, ROW_ADDR, TM_STD_SPI);
++		sfc_cdt[NAND_TRY_ID_DMY].xfer = CMD_XFER(1, DISABLE, 0, ENABLE, SPINAND_CMD_RDID);
++		sfc_cdt[NAND_TRY_ID_DMY].staExp = 0;
++		sfc_cdt[NAND_TRY_ID_DMY].staMsk = 0;
++
++		/* 4. set feature */
++		sfc_cdt[NAND_SET_FEATURE].link = CMD_LINK(0, STA_ADDR0, TM_STD_SPI);
++		sfc_cdt[NAND_SET_FEATURE].xfer = CMD_XFER(1, DISABLE, 0, ENABLE, SPINAND_CMD_SET_FEATURE);
++		sfc_cdt[NAND_SET_FEATURE].staExp = 0;
++		sfc_cdt[NAND_SET_FEATURE].staMsk = 0;
++
++		/* 5. get feature */
++		sfc_cdt[NAND_GET_FEATURE].link = CMD_LINK(0, STA_ADDR0, TM_STD_SPI);
++		sfc_cdt[NAND_GET_FEATURE].xfer = CMD_XFER(1, DISABLE, 0, ENABLE, SPINAND_CMD_GET_FEATURE);
++		sfc_cdt[NAND_GET_FEATURE].staExp = 0;
++		sfc_cdt[NAND_GET_FEATURE].staMsk = 0;
++
++		if (!(flag & UPDATE_CDT)){
++			/* first create cdt table (default)*/
++			write_cdt(sfc, sfc_cdt, NAND_RESET, NAND_GET_FEATURE);
++			return;
++		}
++	}
++
++	if(flag & UPDATE_CDT){
++		cdt_params = nand_info->cdt_params;
++		params_to_cdt(cdt_params, sfc_cdt);
++
++		/* second create cdt table */
++		if (!(flag & DEFAULT_CDT)) {
++			/* second create cdt table (update)*/
++			write_cdt(sfc, sfc_cdt, NAND_STANDARD_READ_TO_CACHE, NAND_ECC_STATUS_READ);
++		} else {
++			/* create full cdt table (default && update)*/
++			write_cdt(sfc, sfc_cdt, NAND_RESET, NAND_ECC_STATUS_READ);
++		}
++	}
++	//dump_cdt(sfc);
++}
++
++
++static int request_sfc_buffer(struct sfc_flash *flash)
++{
++	struct sfc *sfc = flash->sfc;
++	sfc->tmp_buffer = (uint8_t *)dma_alloc_coherent(flash->dev,
++			sizeof(uint8_t) * flash->mtd.writesize, &sfc->tbuff_pyaddr, GFP_KERNEL);
++	if (IS_ERR_OR_NULL(sfc->tmp_buffer)) {
++		return -ENOMEM;
++	}
++
++	return 0;
++}
++
++#ifdef CONFIG_INGENIC_SFCNAND_FMW
++
++static int32_t read_fmw_config(struct mtd_info *mtd, 
++		struct fmw_config *fmw_config, loff_t offset, size_t len, size_t part_size)
++{
++	loff_t flash_off = offset;
++	int i, ret, retlen;
++
++	for (i = 0; i < part_size / mtd->erasesize; i++) {
++		ret = ingenic_sfcnand_read(mtd, offset, len, &retlen, (uint8_t *)fmw_config);
++		if(ret >= 0 && fmw_config->data_len != 0 && fmw_config->crc_val != -1)
++			break;
++
++		flash_off += mtd->erasesize;
++	}
++
++	if(fmw_config->data_len == -1 ||
++		fmw_config->crc_val == -1 ||
++		fmw_config->data_len >= FMW_BUF_LEN) {
++		printk("%s %s %d: flash don`t save mac value!\n",
++			__FILE__, __func__, __LINE__);
++		return -ENODATA;
++	}
++
++	if(i == part_size / mtd->erasesize) {
++		printk("%s %s %d:flash all blocks ecc error!\n",
++			__FILE__, __func__, __LINE__);
++	    	return -EIO;
++	}
++
++	return 0;
++}
++
++static int32_t read_fmw(struct mtd_info *mtd, 
++		uint8_t *buf, loff_t offset, size_t part_size)
++{
++	size_t config_len = sizeof(struct fmw_config);
++	struct fmw_config fmw_config;
++	int32_t i, retlen;
++	int32_t ret = 0;
++
++	ret = read_fmw_config(mtd, &fmw_config, offset, config_len, part_size);
++	if(ret) {
++		printk("%s %s %d:read sn config failed!\n",
++			__FILE__, __func__, __LINE__);
++		return -EIO;
++	}
++
++	offset += sizeof(struct fmw_config);
++
++	for (i = 0; i < part_size / mtd->erasesize; i++) {
++		ret = ingenic_sfcnand_read(mtd, offset, fmw_config.data_len, &retlen, buf);
++		if(ret < 0) {
++			offset += mtd->erasesize;
++			continue;
++		}
++
++		if(local_crc32(0xffffffff, buf, fmw_config.data_len) == fmw_config.crc_val)
++			break;
++		offset += mtd->erasesize;
++	}
++
++	if(i == part_size / mtd->erasesize) {
++		printk("%s %s %d: sn flash all blocks ecc error!\n",
++			__FILE__, __func__, __LINE__);
++	    	return -EIO;
++	}
++
++	return ret;
++}
++
++static int32_t buf_compare(const uint8_t *wbuf, uint8_t *rbuf, uint32_t len) {
++
++	int32_t i = 0;
++	for(i = 0; i < len; i++) {
++		if(wbuf[i] != rbuf[i]) {
++			printk("compare err:wbuf = 0x%02x, rbuf= 0x%02x\n",
++				wbuf[i], rbuf[i]);
++			return -EIO;
++		}
++	}
++	return 0;
++}
++
++static int32_t write_fmw_to_flash(struct mtd_info *mtd, 
++		const uint8_t *wbuf, loff_t offset, size_t len, size_t part_size)
++{
++	uint8_t *rbuf;
++	int32_t retry_count = 5;
++	int32_t ret, retlen;
++
++w_retry:
++	ret = ingenic_sfcnand_write(mtd, offset, len, &retlen, wbuf);
++	if(ret < 0) {
++		if(retry_count--)
++			goto w_retry;
++		if(retry_count < 0) {
++			printk("%s %s %d:write flash failed! ret = %d\n",
++					__FILE__, __func__, __LINE__, ret);
++			return -EIO;
++		}
++	}
++
++	retry_count = 5;
++	retlen = 0;
++	rbuf = kzalloc(len, GFP_KERNEL);
++	if(!rbuf) {
++		printk("alloc mem failed!\n");
++		return -ENOMEM;
++	}
++
++r_retry:
++	ret = ingenic_sfcnand_read(mtd, offset, len, &retlen, (uint8_t *)rbuf);
++	if(ret < 0) {
++	    if(retry_count--)
++		    goto r_retry;
++	    if(retry_count < 0) {
++		    printk("%s %s %d:read flash failed! ret = %d\n",
++		    __FILE__, __func__, __LINE__, ret);
++		    goto failed;
++	    }
++	}
++
++	if(buf_compare(wbuf, rbuf, len)) {
++		printk("%s %s %d: buf compare err!\n",
++			__FILE__, __func__, __LINE__);
++		ret = -EIO;
++		goto failed;
++	}
++	kfree(rbuf);
++	return 0;
++
++failed:
++	kfree(rbuf);
++	return ret;
++}
++
++static int32_t write_fmw(struct mtd_info *mtd, 
++		const uint8_t *buf, loff_t offset, size_t len, size_t part_size)
++{
++	uint8_t i;
++	uint8_t errcount = 0;
++	int32_t ret = 0;
++
++	struct erase_info instr = {
++		.addr = offset,
++		.len = mtd->erasesize,
++	};
++
++	for(i = 0; i < part_size / mtd->erasesize; i++) {
++		ingenic_sfcnand_erase(mtd, &instr);
++		instr.addr += instr.len;
++	}
++
++	for(i = 0; i < part_size / mtd->erasesize; i++) {
++		ret = write_fmw_to_flash(mtd, buf, offset, len, CONFIG_SN_FLASH_SIZE / 2);
++		if(ret) {
++			printk("%s %s %d:write data failed! errcount = %d\n",
++					__FILE__, __func__, __LINE__, errcount++);
++		}
++		offset += mtd->erasesize;
++	}
++
++	if(errcount == part_size / mtd->erasesize) {
++		printk("all blk write failed!\n");
++		return -EIO;
++	}
++
++	return ret;
++}
++
++static ssize_t nand_sn_show(struct device *dev, 
++		struct device_attribute *attr, char *buf)
++{
++	struct mtd_info *mtd = &fmw_flash->mtd;
++	uint8_t *rbuf;
++	int32_t ret;
++	size_t part_size = CONFIG_SN_FLASH_SIZE;
++	loff_t offset = mtd->size + CONFIG_MAC_FLASH_SIZE;
++
++	rbuf = kzalloc(FMW_BUF_LEN, GFP_KERNEL);
++	if(!rbuf) {
++		printk("%s %s %d: alloc fmw buf error.\n", __FILE__,__func__,__LINE__);
++		return -ENOMEM;
++	}
++
++	ret = read_fmw(mtd, rbuf, offset, part_size);
++	if(ret) {
++		printk("%s %s %d: sn_read failed, ret = %d\n",
++				__FILE__, __func__, __LINE__, ret);
++		return ret;
++	}
++
++	ret = sprintf(buf, "%s\n", rbuf);
++
++	kfree(rbuf);
++	return ret;
++}
++
++static ssize_t nand_sn_store(struct device *dev, 
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++#if 0
++	struct mtd_info *mtd = &fmw_flash->mtd;
++	loff_t offset = mtd->size + CONFIG_MAC_FLASH_SIZE;
++	int32_t ret;
++
++	ret = write_fmw(mtd, buf, offset, n, CONFIG_SN_FLASH_SIZE);
++	if (ret) {
++		printk("sn firmware write failed!\n");
++		ret = -EIO;
++	}
++#endif
++	printk("The write firmware function is disabled.\n");
++
++	return n;
++}
++
++static ssize_t nand_mac_show(struct device *dev, 
++		struct device_attribute *attr, char *buf)
++{
++	struct mtd_info *mtd = &fmw_flash->mtd;
++	uint8_t *rbuf;
++	size_t part_size = CONFIG_MAC_FLASH_SIZE;
++	loff_t offset = mtd->size;
++	int32_t ret;
++
++	rbuf = kzalloc(FMW_BUF_LEN, GFP_KERNEL);
++	if(!rbuf) {
++		printk("%s %s %d: alloc fmw buf error.\n", __FILE__,__func__,__LINE__);
++		return -ENOMEM;
++	}
++
++
++	ret = read_fmw(mtd, rbuf, offset, part_size);
++	if(ret) {
++		printk("%s %s %d: sn_read failed, ret = %d\n",
++				__FILE__, __func__, __LINE__, ret);
++		return ret;
++	}
++
++	ret = sprintf(buf, "%s\n", rbuf);
++
++	kfree(rbuf);
++	return ret;
++}
++
++static ssize_t nand_mac_store(struct device *dev, 
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++#if 0
++	struct mtd_info *mtd = &fmw_flash->mtd;
++	loff_t offset = mtd->size;
++	int32_t ret;
++
++	ret = write_fmw(mtd, buf, offset, n, CONFIG_MAC_FLASH_SIZE);
++	if (ret) {
++		printk("sn firmware write failed!\n");
++		ret = -EIO;
++	}
++#endif
++	printk("The write firmware function is disabled.\n");
++
++	return n;
++}
++
++static ssize_t nand_license_show(struct device *dev,
++	struct device_attribute *attr, char *buf)
++{
++	struct mtd_info *mtd = &fmw_flash->mtd;
++	uint8_t *rbuf;
++	size_t part_size = CONFIG_LICENSE_FLASH_SIZE;
++	loff_t offset = mtd->size + CONFIG_SN_FLASH_SIZE + CONFIG_MAC_FLASH_SIZE;
++	int32_t ret;
++
++	rbuf = kzalloc(FMW_BUF_LEN, GFP_KERNEL);
++	if(!rbuf) {
++		printk("%s %s %d: alloc fmw buf error.\n", __FILE__,__func__,__LINE__);
++		return -ENOMEM;
++	}
++
++	ret = read_fmw(mtd, rbuf, offset, part_size);
++	if(ret) {
++		printk("%s %s %d: sn_read failed, ret = %d\n",
++				__FILE__, __func__, __LINE__, ret);
++		return ret;
++	}
++
++	ret = sprintf(buf, "%s\n", rbuf);
++
++	kfree(rbuf);
++	return ret;
++}
++
++static ssize_t nand_license_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++#if 0
++	struct mtd_info *mtd = &fmw_flash->mtd;
++	loff_t offset = mtd->size + CONFIG_MAC_FLASH_SIZE + CONFIG_SN_FLASH_SIZE;
++	int32_t ret;
++
++	ret = write_fmw(mtd, buf, offset, n, CONFIG_LICENSE_FLASH_SIZE);
++	if (ret) {
++		printk("sn firmware write failed!\n");
++		ret = -EIO;
++	}
++#endif
++	printk(KERN_ERR "The write firmware function is disabled.\n");
++
++	return n;
++}
++
++static DEVICE_ATTR(nand_sn, S_IRUGO|S_IWUSR, nand_sn_show, nand_sn_store);
++static DEVICE_ATTR(nand_mac, S_IRUGO|S_IWUSR, nand_mac_show, nand_mac_store);
++static DEVICE_ATTR(nand_license, S_IRUGO|S_IWUSR, nand_license_show, nand_license_store);
++
++static struct attribute *nand_fmw_attrs[] = {
++	&dev_attr_nand_sn.attr,
++	&dev_attr_nand_mac.attr,
++	&dev_attr_nand_license.attr,
++	NULL,
++};
++
++const char nand_group_name[] = "nand_fmw";
++static struct attribute_group nand_fmw_attr_group = {
++	.name	= nand_group_name,
++	.attrs	= nand_fmw_attrs,
++};
++#endif
++
++
++
++int ingenic_sfc_nand_probe(struct sfc_flash *flash)
++{
++	const char *ingenic_probe_types[] = {"cmdlinepart", "ofpart", NULL};
++	struct nand_chip *chip;
++	struct ingenic_sfcnand_flashinfo *nand_info;
++	int32_t ret;
++
++	chip = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
++	if (IS_ERR_OR_NULL(chip)) {
++		return -ENOMEM;
++	}
++	nand_info = kzalloc(sizeof(struct ingenic_sfcnand_flashinfo), GFP_KERNEL);
++	if(IS_ERR_OR_NULL(nand_info)) {
++	    	kfree(chip);
++		return -ENOMEM;
++	}
++
++	flash->flash_info = nand_info;
++
++	if(flash->pdata_params->param_offset > 0) {
++		flash->param_offset = flash->pdata_params->param_offset;
++	} else {
++		flash->param_offset = SPIFLASH_PARAMER_OFFSET;
++	}
++
++#define THOLD	5
++#define TSETUP	5
++#define TSHSL_R	    100
++#define TSHSL_W	    100
++
++	set_flash_timing(flash->sfc, THOLD, TSETUP, TSHSL_R, TSHSL_W);
++
++	/* request DMA Descriptor space */
++	ret = request_sfc_desc(flash->sfc, DESC_MAX_NUM);
++	if(ret){
++		dev_err(flash->dev, "Failure to request DMA descriptor space!\n");
++		ret = -ENOMEM;
++		goto free_base;
++	}
++
++	/* Try creating default CDT table */
++	flash->create_cdt_table = nand_create_cdt_table;
++	flash->create_cdt_table(flash->sfc, flash->flash_info ,DEFAULT_CDT);
++
++	if((ret = ingenic_sfc_nand_dev_init(flash))) {
++		dev_err(flash->dev, "nand device init failed!\n");
++		goto free_dma_desc;
++	}
++
++	if((ret = ingenic_sfc_nand_try_id(flash))) {
++		dev_err(flash->dev, "try device id failed\n");
++		goto free_dma_desc;
++	}
++
++	/* Update to private CDT table */
++	flash->create_cdt_table(flash->sfc, flash->flash_info, UPDATE_CDT);
++
++	/* Update sfc rate */
++	if((ret = sfc_clk_set_highspeed(flash->sfc))) {
++		dev_err(flash->dev, "set sfc rate failed\n");
++		goto free_dma_desc;
++	}
++
++	set_flash_timing(flash->sfc, nand_info->param.tHOLD,
++			nand_info->param.tSETUP, nand_info->param.tSHSL_R, nand_info->param.tSHSL_W);
++	flash->mtd.name = "sfc_nand";
++	flash->mtd.owner = THIS_MODULE;
++	flash->mtd.type = MTD_NANDFLASH;
++	flash->mtd.flags |= MTD_CAP_NANDFLASH;
++	flash->mtd.erasesize = nand_info->param.blocksize;
++	flash->mtd.writesize = nand_info->param.pagesize;
++#ifndef CONFIG_INGENIC_SFCNAND_FMW
++	flash->mtd.size = nand_info->param.flashsize;
++#else
++	flash->mtd.size = nand_info->param.flashsize - CONFIG_SN_FLASH_SIZE - CONFIG_MAC_FLASH_SIZE - CONFIG_LICENSE_FLASH_SIZE;
++#endif
++	flash->mtd.oobsize = nand_info->param.oobsize;
++	flash->mtd.writebufsize = flash->mtd.writesize;
++	flash->mtd.bitflip_threshold = flash->mtd.ecc_strength = nand_info->param.ecc_max - 1;
++
++	chip->badblockbits = 8;
++	chip->bbt_erase_shift = chip->phys_erase_shift = ffs(flash->mtd.erasesize) - 1;
++	chip->data_buf = kzalloc(nand_info->param.pagesize + nand_info->param.oobsize, GFP_KERNEL);
++	if(IS_ERR_OR_NULL(chip->data_buf)) {
++		dev_err(flash->dev, "alloc nand buffer->databuf failed\n");
++		ret = -ENOMEM;
++		kfree(chip->data_buf);
++		goto free_dma_desc;
++	}
++
++	flash->chip = chip;
++	flash->mtd.priv = chip;
++	flash->mtd._erase = ingenic_sfcnand_erase;
++	flash->mtd._read_oob = ingenic_sfcnand_read_oob;
++	flash->mtd._write_oob = ingenic_sfcnand_write_oob;
++	flash->mtd._block_isbad = ingenic_sfcnand_block_isbab;
++	flash->mtd._block_markbad = ingenic_sfcnand_block_markbad;
++
++	/* request Temporary buffer space */
++	ret = request_sfc_buffer(flash);
++	if(ret){
++		dev_err(flash->dev, "Failure to request Temporary Buffer space!\n");
++		ret = -ENOMEM;
++		goto free_chip_buffers;
++	}
++
++	flash->dev->of_node = NULL;
++	if (!flash->pdata_params->use_ofpart_info) {
++		/* use burner partitions */
++		if((ret = ingenic_sfcnand_partition(flash))) {
++			if(ret == -EINVAL)
++				return 0;
++			dev_err(flash->dev, "read flash partition failed!\n");
++			goto free_all;
++		}
++		ret = mtd_device_parse_register(&flash->mtd, ingenic_probe_types, NULL,
++				nand_info->partition.partition, nand_info->partition.num_partition);
++	} else {
++
++		/* use ofpart partitions */
++		flash->dev->of_node = of_get_child_by_name(flash->dev->of_node, "nandflash");
++		if (flash->dev->of_node < 0) {
++			dev_err(flash->dev, "Cannot get 'nandflash' node from dtb!\n");
++			flash->dev->of_node = NULL;
++		}
++		ret = mtd_device_parse_register(&flash->mtd, ingenic_probe_types, &flash->ppdata, NULL, 0);
++	}
++
++	if (ret) {
++		kfree(nand_info->partition.partition);
++		if(!flash->pdata_params->use_ofpart_info) {
++			kfree(burn_param->partition);
++			kfree(burn_param);
++		}
++		ret = -ENODEV;
++		goto free_all;
++	}
++
++#ifdef CONFIG_INGENIC_SFCNAND_FMW
++	fmw_flash = flash;
++
++	flash->attr_group = &nand_fmw_attr_group;
++	ret = sysfs_create_group(&flash->dev->kobj, flash->attr_group);
++	if (ret) {
++		dev_err(flash->dev, "device create sysfs group failed\n");
++		ret = -EINVAL;
++		goto free_all;
++	}
++#endif
++
++	return 0;
++
++free_all:
++	dma_free_coherent(flash->dev, flash->mtd.writesize, flash->sfc->tmp_buffer, flash->sfc->tbuff_pyaddr);
++
++free_chip_buffers:
++	kfree(chip->data_buf);
++
++free_dma_desc:
++	free_sfc_desc(flash->sfc);
++
++free_base:
++	kfree(chip);
++	kfree(nand_info);
++	return ret;
++}
++
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_nor.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_nor.c
+new file mode 100644
+index 000000000..57065c5c0
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_nor.c
+@@ -0,0 +1,1000 @@
++/*
++ * SFC controller for SPI protocol, use FIFO and DMA;
++ *
++ * Copyright (c) 2015 Ingenic
++ * Author: <xiaoyang.fu@ingenic.com>
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++*/
++
++#include <linux/init.h>
++#include <linux/spinlock.h>
++#include <linux/workqueue.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/sched.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/gpio.h>
++#include <linux/platform_device.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <asm/uaccess.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++#include <asm/page.h>
++#include "sfc_flash.h"
++#include "spinor.h"
++#include "ingenic_sfc_common.h"
++#include "ingenic_sfc_drv.h"
++
++//#define DEBUG_CLONER_PARAMS
++
++#define STATUS_SUSPND	(1<<0)
++
++#define MULTI_DIE_FLASH_NUM 1
++
++static LIST_HEAD(nor_list);
++
++struct sfc_flash *to_ingenic_spi_norflash(struct mtd_info *mtd_info)
++{
++	return container_of(mtd_info, struct sfc_flash, mtd);
++}
++
++#define ACTIVE_DIE(flash, addr)					\
++({								\
++	uint8_t die_id = addr >> nor_info->die_shift;		\
++	if (die_id != nor_info->current_die_id) {			\
++		sfc_active_die(flash, die_id);				\
++		nor_info->current_die_id = die_id;			\
++	}							\
++	if (die_id)						\
++		addr = addr & ((1 << nor_info->die_shift) - 1);	\
++	addr;							\
++})								\
++
++static int sfc_die_select(struct sfc_flash *flash, uint8_t die_id)
++{
++	struct sfc_cdt_xfer xfer;
++	memset(&xfer, 0, sizeof(xfer));
++
++	/* set Index */
++	xfer.cmd_index = NOR_DIE_SELECT;
++
++	/* set addr */
++	xfer.rowaddr = 0;
++	xfer.columnaddr = 0;
++
++	/* set transfer config */
++	xfer.dataen = ENABLE;
++	xfer.config.datalen = 1;
++	xfer.config.data_dir = GLB0_TRAN_DIR_WRITE;
++	xfer.config.ops_mode = CPU_OPS;
++	xfer.config.buf = &die_id;
++
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		dev_err(flash->dev,"sfc_sync_cdt error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++		return -EIO;
++	}
++
++	return 0;
++}
++
++static int sfc_read_active_die_id(struct sfc_flash *flash, uint8_t *value)
++{
++	struct sfc_cdt_xfer xfer;
++	memset(&xfer, 0, sizeof(xfer));
++
++	/* set Index */
++	xfer.cmd_index = NOR_READ_ACTIVE_DIE_ID;
++
++	/* set addr */
++	xfer.rowaddr = 0;
++	xfer.columnaddr = 0;
++
++	/* set transfer config */
++	xfer.dataen = ENABLE;
++	xfer.config.datalen = 1;
++	xfer.config.data_dir = GLB0_TRAN_DIR_READ;
++	xfer.config.ops_mode = CPU_OPS;
++	xfer.config.buf = value;
++
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		dev_err(flash->dev,"sfc_sync_cdt error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++		return -EIO;
++	}
++
++	return 0;
++}
++
++static int sfc_active_die(struct sfc_flash *flash, uint8_t die_id)
++{
++	uint8_t die_id_read;
++
++	sfc_die_select(flash, die_id);
++	do {
++		sfc_read_active_die_id(flash, &die_id_read);
++	}while(die_id != die_id_read);
++
++	return 0;
++}
++
++int32_t sfc_nor_reset(struct sfc_flash *flash)
++{
++	struct sfc_cdt_xfer xfer;
++	memset(&xfer, 0, sizeof(xfer));
++
++	/* set Index */
++	xfer.cmd_index = NOR_RESET_ENABLE;
++
++	/* set addr */
++	xfer.rowaddr = 0;
++	xfer.columnaddr = 0;
++
++	/* set transfer config */
++	xfer.dataen = DISABLE;
++
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		dev_err(flash->dev,"sfc_sync_cdt error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++		return -EIO;
++	}
++
++	udelay(100);
++	return 0;
++}
++
++int sfc_nor_read_id(struct sfc_flash *flash)
++{
++	struct sfc_cdt_xfer xfer;
++	unsigned char buf[3];
++	unsigned int chip_id = 0;
++	memset(&xfer, 0, sizeof(xfer));
++
++	/* set Index */
++	xfer.cmd_index = NOR_READ_ID;
++
++	/* set addr */
++	xfer.rowaddr = 0;
++	xfer.columnaddr = 0;
++
++	/* set transfer config */
++	xfer.dataen = ENABLE;
++	xfer.config.datalen = 3;
++	xfer.config.data_dir = GLB0_TRAN_DIR_READ;
++	xfer.config.ops_mode = CPU_OPS;
++	xfer.config.buf = buf;
++
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		dev_err(flash->dev,"sfc_sync_cdt error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++		return -EIO;
++	}
++
++	chip_id = ((buf[0] & 0xff) << 16) | ((buf[1] & 0xff) << 8) | (buf[2] & 0xff);
++
++	return chip_id;
++}
++
++static unsigned int sfc_do_read(struct sfc_flash *flash, unsigned int addr, unsigned char *buf, size_t len)
++{
++	struct spinor_flashinfo *nor_info = flash->flash_info;
++	struct sfc_cdt_xfer xfer;
++	memset(&xfer, 0, sizeof(xfer));
++
++	/* set Index */
++	if (nor_info->quad_succeed) {
++		xfer.cmd_index = NOR_READ_QUAD;
++	} else {
++		xfer.cmd_index = NOR_READ_STANDARD;
++	}
++
++	/* active die */
++	if (nor_info->die_num > 1)
++		addr = ACTIVE_DIE(flash, addr);
++
++	/* set addr */
++	xfer.columnaddr = 0;
++	xfer.rowaddr = addr;
++
++	/* set transfer config */
++	xfer.dataen = ENABLE;
++	xfer.config.datalen = len;
++	xfer.config.data_dir = GLB0_TRAN_DIR_READ;
++	xfer.config.ops_mode = DMA_OPS;
++	xfer.config.buf = buf;
++
++retry:
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		dev_err(flash->dev,"sfc_sync_cdt error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++		return -EIO;
++	}
++
++	/* if underrun, retry read */
++	if (flash->sfc->retry_count > 0) {
++		dev_warn(flash->dev,"SFC retry transfer! %s %s %d\n",__FILE__,__func__,__LINE__);
++		goto retry;
++	}
++
++	if(xfer.config.ops_mode == DMA_OPS) {
++		dma_sync_single_for_device(flash->dev, (dma_addr_t)(sfc_get_paddr((void *)buf)), len, DMA_FROM_DEVICE);
++	}
++
++	return len;
++}
++
++static unsigned  int sfc_do_write(struct sfc_flash *flash, unsigned int addr, const unsigned char *buf, size_t len)
++{
++	struct spinor_flashinfo *nor_info = flash->flash_info;
++	struct sfc_cdt_xfer xfer;
++	memset(&xfer, 0, sizeof(xfer));
++
++	/* set Index */
++	if (nor_info->quad_succeed) {
++		xfer.cmd_index = NOR_WRITE_QUAD_ENABLE;
++	} else {
++		xfer.cmd_index = NOR_WRITE_STANDARD_ENABLE;
++	}
++
++	/* active die */
++	if (nor_info->die_num > 1)
++		addr = ACTIVE_DIE(flash, addr);
++
++	/* set addr */
++	xfer.columnaddr = 0;
++	xfer.rowaddr = addr;
++
++	/* set transfer config */
++	xfer.dataen = ENABLE;
++	xfer.config.datalen = len;
++	xfer.config.data_dir = GLB0_TRAN_DIR_WRITE;
++	xfer.config.ops_mode = DMA_OPS;
++	xfer.config.buf = (uint8_t *)buf;
++
++retry:
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		dev_err(flash->dev,"sfc_sync_cdt error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++		return -EIO;
++	}
++
++	/* if overrun, retry write */
++	if (flash->sfc->retry_count > 0) {
++		dev_warn(flash->dev,"SFC retry transfer! %s %s %d\n",__FILE__,__func__,__LINE__);
++		goto retry;
++	}
++
++	return len;
++}
++
++static int sfc_do_erase(struct sfc_flash *flash, uint32_t addr)
++{
++	struct spinor_flashinfo *nor_info = flash->flash_info;
++	struct sfc_cdt_xfer xfer;
++
++	memset(&xfer, 0, sizeof(xfer));
++
++	/* set Index */
++	xfer.cmd_index = NOR_ERASE_WRITE_ENABLE;
++
++	/* active die */
++	if (nor_info->die_num > 1)
++		addr = ACTIVE_DIE(flash, addr);
++
++	/* set addr */
++	xfer.rowaddr = addr;
++
++	/* set transfer config */
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		dev_err(flash->dev,"sfc_sync_cdt error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++		return -EIO;
++	}
++
++	return 0;
++}
++
++static int sfc_read(struct sfc_flash *flash, loff_t from, size_t len, unsigned char *buf)
++{
++	int32_t ret;
++
++	/* create DMA Descriptors */
++	ret = create_sfc_desc(flash->sfc, buf, len);
++	if(ret < 0){
++		dev_err(flash->dev, "%s create descriptors error. -%d\n", __func__, ret);
++		return ret;
++	}
++
++	//dump_desc(flash->sfc, ret);
++
++	/* DMA Descriptors read */
++	ret = sfc_do_read(flash, (unsigned int)from, buf, len);
++
++	return ret;
++}
++
++static int sfc_write(struct sfc_flash *flash, loff_t to, size_t len, const unsigned char *buf)
++{
++	int32_t ret;
++
++	/* create DMA Descriptors */
++	ret = create_sfc_desc(flash->sfc, (unsigned char *)buf, len);
++	if(ret < 0){
++		dev_err(flash->dev, "%s create descriptors error. -%d\n", __func__, ret);
++		return ret;
++	}
++
++	//dump_desc(flash->sfc, ret);
++
++	/* DMA Descriptors write */
++	ret = sfc_do_write(flash, (unsigned int)to, buf, len);
++
++	return ret;
++}
++
++static int ingenic_spi_norflash_read(struct mtd_info *mtd, loff_t from, size_t len,size_t *retlen, unsigned char *buf)
++{
++	struct sfc_flash *flash = to_ingenic_spi_norflash(mtd);
++
++	mutex_lock(&flash->lock);
++	*retlen = sfc_read(flash, from, len, buf);
++	mutex_unlock(&flash->lock);
++
++	return 0;
++}
++
++static int ingenic_spi_norflash_write(struct mtd_info *mtd, loff_t to, size_t len,
++		size_t *retlen, const unsigned char *buf)
++{
++	u32 page_offset, actual_len;
++	struct sfc_flash *flash = to_ingenic_spi_norflash(mtd);
++	struct spinor_flashinfo *nor_info = flash->flash_info;
++	struct spi_nor_info *spi_nor_info = nor_info->nor_flash_info;
++	int ret;
++
++	mutex_lock(&flash->lock);
++
++	page_offset = to & (spi_nor_info->page_size - 1);
++	/* do all the bytes fit onto one page? */
++	if (page_offset + len <= spi_nor_info->page_size) {
++		ret = sfc_write(flash, (unsigned int)to, len, buf);
++		*retlen = ret;
++	} else {
++		u32 i;
++
++		/* the size of data remaining on the first page */
++		actual_len = spi_nor_info->page_size - page_offset;
++		ret = sfc_write(flash, (unsigned int)to, actual_len, buf);
++		*retlen += ret;
++
++		/* write everything in flash->page_size chunks */
++		for (i = actual_len; i < len; i += mtd->writesize) {
++			actual_len = len - i;
++			if (actual_len >= mtd->writesize)
++				actual_len = mtd->writesize;
++
++			ret = sfc_write(flash, (unsigned int)to + i, actual_len, buf + i);
++			*retlen += ret;
++		}
++	}
++	mutex_unlock(&flash->lock);
++	return 0;
++}
++
++static int ingenic_spi_norflash_erase(struct mtd_info *mtd, struct erase_info *instr)
++{
++	struct sfc_flash *flash = to_ingenic_spi_norflash(mtd);
++	struct spinor_flashinfo *nor_info = flash->flash_info;
++	struct spi_nor_info *spi_nor_info = nor_info->nor_flash_info;
++	uint32_t addr, end;
++	int ret;
++
++	mutex_lock(&flash->lock);
++
++	addr = (instr->addr & (mtd->erasesize - 1));
++	if (addr) {
++		dev_err(flash->dev, "%s eraseaddr no align\n", __func__);
++		mutex_unlock(&flash->lock);
++		return -EINVAL;
++	}
++	end = (instr->len & (mtd->erasesize - 1));
++	if (end) {
++		dev_err(flash->dev,"%s erasesize no align\n", __func__);
++		mutex_unlock(&flash->lock);
++		return -EINVAL;
++	}
++	addr = (uint32_t)instr->addr;
++	end = addr + (uint32_t)instr->len;
++
++	while (addr < end) {
++		ret = sfc_do_erase(flash, addr);
++		if (ret) {
++			dev_err(flash->dev,"erase error !\n");
++			mutex_unlock(&flash->lock);
++			return ret;
++		}
++		addr += spi_nor_info->erase_size;
++	}
++	mutex_unlock(&flash->lock);
++
++	return 0;
++}
++
++#ifndef CONFIG_INGENIC_BUILTIN_PARAMS
++static int32_t ingenic_spi_norflash_read_params(struct sfc_flash *flash, loff_t from, size_t len, uint8_t *buf)
++{
++	struct sfc_cdt_xfer xfer;
++	memset(&xfer, 0, sizeof(xfer));
++
++	xfer.cmd_index = NOR_READ_STANDARD;
++
++	xfer.columnaddr = 0;
++	xfer.rowaddr = from;
++
++	xfer.dataen =  ENABLE;
++	xfer.config.datalen = len;
++	xfer.config.data_dir = GLB0_TRAN_DIR_READ;
++	xfer.config.ops_mode = CPU_OPS;
++	xfer.config.buf = buf;
++
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		dev_err(flash->dev,"sfc_sync_cdt error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++		return -EIO;
++	}
++
++	return 0;
++}
++#endif
++
++#ifdef DEBUG_CLONER_PARAMS
++static void dump_cloner_params(struct burner_params *params)
++{
++	struct spi_nor_info *spi_nor_info;
++
++	spi_nor_info = &params->spi_nor_info;
++
++	printk("name=%s\n", spi_nor_info->name);
++	printk("id=0x%x\n", spi_nor_info->id);
++
++	printk("read_standard->cmd=0x%x\n",		spi_nor_info->read_standard.cmd);
++	printk("read_standard->dummy=0x%x\n",		spi_nor_info->read_standard.dummy_byte);
++	printk("read_standard->addr_nbyte=0x%x\n",	spi_nor_info->read_standard.addr_nbyte);
++	printk("read_standard->transfer_mode=0x%x\n",	spi_nor_info->read_standard.transfer_mode);
++
++	printk("read_quad->cmd=0x%x\n",			spi_nor_info->read_quad.cmd);
++	printk("read_quad->dummy=0x%x\n",		spi_nor_info->read_quad.dummy_byte);
++	printk("read_quad->addr_nbyte=0x%x\n",		spi_nor_info->read_quad.addr_nbyte);
++	printk("read_quad->transfer_mode=0x%x\n",	spi_nor_info->read_quad.transfer_mode);
++
++	printk("write_standard->cmd=0x%x\n",		spi_nor_info->write_standard.cmd);
++	printk("write_standard->dummy=0x%x\n",		spi_nor_info->write_standard.dummy_byte);
++	printk("write_standard->addr_nbyte=0x%x\n",	spi_nor_info->write_standard.addr_nbyte);
++	printk("write_standard->transfer_mode=0x%x\n",	spi_nor_info->write_standard.transfer_mode);
++
++	printk("write_quad->cmd=0x%x\n",		spi_nor_info->write_quad.cmd);
++	printk("write_quad->dummy=0x%x\n",		spi_nor_info->write_quad.dummy_byte);
++	printk("write_quad->addr_nbyte=0x%x\n",		spi_nor_info->write_quad.addr_nbyte);
++	printk("write_quad->transfer_mode=0x%x\n",	spi_nor_info->write_quad.transfer_mode);
++
++	printk("sector_erase->cmd=0x%x\n",		spi_nor_info->sector_erase.cmd);
++	printk("sector_erase->dummy=0x%x\n",		spi_nor_info->sector_erase.dummy_byte);
++	printk("sector_erase->addr_nbyte=0x%x\n",	spi_nor_info->sector_erase.addr_nbyte);
++	printk("sector_erase->transfer_mode=0x%x\n",	spi_nor_info->sector_erase.transfer_mode);
++
++	printk("wr_en->cmd=0x%x\n",		spi_nor_info->wr_en.cmd);
++	printk("wr_en->dummy=0x%x\n",		spi_nor_info->wr_en.dummy_byte);
++	printk("wr_en->addr_nbyte=0x%x\n",	spi_nor_info->wr_en.addr_nbyte);
++	printk("wr_en->transfer_mode=0x%x\n",	spi_nor_info->wr_en.transfer_mode);
++
++	printk("en4byte->cmd=0x%x\n",		spi_nor_info->en4byte.cmd);
++	printk("en4byte->dummy=0x%x\n",		spi_nor_info->en4byte.dummy_byte);
++	printk("en4byte->addr_nbyte=0x%x\n",	spi_nor_info->en4byte.addr_nbyte);
++	printk("en4byte->transfer_mode=0x%x\n",	spi_nor_info->en4byte.transfer_mode);
++
++	printk("quad_set->cmd=0x%x\n",		spi_nor_info->quad_set.cmd);
++	printk("quad_set->bit_shift=0x%x\n",		spi_nor_info->quad_set.bit_shift);
++	printk("quad_set->mask=0x%x\n",		spi_nor_info->quad_set.mask);
++	printk("quad_set->val=0x%x\n",		spi_nor_info->quad_set.val);
++	printk("quad_set->len=0x%x\n",		spi_nor_info->quad_set.len);
++	printk("quad_set->dummy=0x%x\n",	spi_nor_info->quad_set.dummy);
++
++	printk("quad_get->cmd=0x%x\n",		spi_nor_info->quad_get.cmd);
++	printk("quad_get->bit_shift=0x%x\n",		spi_nor_info->quad_get.bit_shift);
++	printk("quad_get->mask=0x%x\n",		spi_nor_info->quad_get.mask);
++	printk("quad_get->val=0x%x\n",		spi_nor_info->quad_get.val);
++	printk("quad_get->len=0x%x\n",		spi_nor_info->quad_get.len);
++	printk("quad_get->dummy=0x%x\n",	spi_nor_info->quad_get.dummy);
++
++	printk("busy->cmd=0x%x\n",		spi_nor_info->busy.cmd);
++	printk("busy->bit_shift=0x%x\n",		spi_nor_info->busy.bit_shift);
++	printk("busy->mask=0x%x\n",		spi_nor_info->busy.mask);
++	printk("busy->val=0x%x\n",		spi_nor_info->busy.val);
++	printk("busy->len=0x%x\n",		spi_nor_info->busy.len);
++	printk("busy->dummy=0x%x\n",		spi_nor_info->busy.dummy);
++
++	printk("quad_ops_mode=%d\n",	spi_nor_info->quad_ops_mode);
++	printk("addr_ops_mode=%d\n",	spi_nor_info->addr_ops_mode);
++
++	printk("tCHSH=%d\n",	spi_nor_info->tCHSH);
++	printk("tSLCH=%d\n",	spi_nor_info->tSLCH);
++	printk("tSHSL_RD=%d\n", spi_nor_info->tSHSL_RD);
++	printk("tSHSL_WR=%d\n", spi_nor_info->tSHSL_WR);
++
++	printk("chip_size=%d\n",	spi_nor_info->chip_size);
++	printk("page_size=%d\n",	spi_nor_info->page_size);
++	printk("erase_size=%d\n",	spi_nor_info->erase_size);
++
++	printk("chip_erase_cmd=0x%x\n",	spi_nor_info->chip_erase_cmd);
++}
++#endif
++
++#ifndef CONFIG_INGENIC_BUILTIN_PARAMS
++static struct burner_params *burner_params = NULL;
++#endif
++
++static int ingenic_spi_norflash_get_params(struct sfc_flash *flash)
++{
++	struct spinor_flashinfo *nor_info = flash->flash_info;
++
++#ifndef CONFIG_INGENIC_BUILTIN_PARAMS
++	int32_t ret, err = 0;
++#else
++	int chip_id;
++	struct builtin_params builtin_params;
++	struct nor_params_node *nor_device;
++#endif
++
++
++#ifndef CONFIG_INGENIC_BUILTIN_PARAMS
++	dev_info(flash->dev, "Use burner params.\n");
++	burner_params = kzalloc(sizeof(struct burner_params), GFP_KERNEL);
++	if (!burner_params) {
++		dev_err(flash->dev, "Failed to alloc mem for params\n");
++		err = -ENOMEM;
++		goto err_params;
++	}
++
++	ret = ingenic_spi_norflash_read_params(flash, SPIFLASH_PARAMER_OFFSET, sizeof(struct burner_params), (uint8_t *)burner_params);
++	if (ret) {
++		dev_err(flash->dev, "Failed to read params (burned by Burner)\n");
++		err = -EINVAL;
++		goto err_read_params;
++	}
++	//add crc check for params
++	dev_info(flash->dev, "magic is 0x%x  version is 0x%x\n", burner_params->magic, burner_params->version);
++	nor_info->nor_flash_info = NULL;
++	if (burner_params->magic == NOR_MAGIC) {
++		if (burner_params->version == NOR_VERSION) {
++			nor_info->nor_flash_info = &burner_params->spi_nor_info;
++			nor_info->norflash_partitions = &burner_params->norflash_partitions;
++			nor_info->nor_pri_data = &burner_params->nor_pri_data;
++		}
++	}
++
++#else
++
++	dev_info(flash->dev, "Use builtin params.\n");
++	chip_id = sfc_nor_read_id(flash);
++	if (chip_id < 0) {
++		dev_err(flash->dev, "Failed to read chip id !\n");
++		return -EINVAL;
++	}
++	dev_info(flash->dev, "chip_id: 0x%x\n", chip_id);
++
++	list_for_each_entry(nor_device, &nor_list, list) {
++		if(nor_device->nor_device_info.id == chip_id) {
++			builtin_params.spi_nor_info = &nor_device->nor_device_info;
++			break;
++		}
++	}
++
++	if (!builtin_params.spi_nor_info) {
++		dev_err(flash->dev, "ERROR: do support this device, id = 0x%x\n", chip_id);
++		return -ENODEV;
++	}
++
++	get_nor_builtin_params(flash, &builtin_params);
++
++	dev_info(flash->dev, "magic is 0x%x  version is 0x%x\n", builtin_params.magic, builtin_params.version);
++	nor_info->nor_flash_info = NULL;
++	if (builtin_params.magic == NOR_MAGIC) {
++		if (builtin_params.version == NOR_VERSION) {
++			nor_info->nor_flash_info = builtin_params.spi_nor_info;
++			nor_info->nor_pri_data = builtin_params.nor_pri_data;
++		}
++	}
++#endif
++
++
++#ifndef CONFIG_INGENIC_BUILTIN_PARAMS
++	if ((!nor_info->nor_flash_info) || (!nor_info->norflash_partitions)) {
++		printk("WARNING : cannot get nor flash params or partitions !!!\n");
++		err = -EINVAL;
++		goto err_read_params;
++	}
++
++#ifdef DEBUG_CLONER_PARAMS
++	dump_cloner_params(burner_params);
++#endif
++	return 0;
++
++err_read_params:
++	kfree(burner_params);
++err_params:
++	return err;
++#else
++
++	if (!nor_info->nor_flash_info) {
++		printk("WARNING : cannot get nor flash params !!!\n");
++		return -EINVAL;
++	}
++
++	return 0;
++#endif
++}
++static ssize_t sfc_nor_partition_offset_show(struct device *dev,
++		struct device_attribute *attr,
++		char *buf)
++{
++	return sprintf(buf,"0x%x\n", SPIFLASH_PARAMER_OFFSET + sizeof(int) * 2 + sizeof(struct spi_nor_info));
++}
++
++static DEVICE_ATTR(sfc_nor_partition_offset, S_IRUGO | S_IWUSR,
++		sfc_nor_partition_offset_show,
++		NULL);
++
++static ssize_t sfc_nor_params_offset_show(struct device *dev,
++		struct device_attribute *attr,
++		char *buf)
++{
++	return sprintf(buf,"0x%x\n",SPIFLASH_PARAMER_OFFSET);
++}
++
++static DEVICE_ATTR(sfc_nor_params_offset, S_IRUGO | S_IWUSR,
++		sfc_nor_params_offset_show,
++		NULL);
++
++/*add your attr in here*/
++static struct attribute *sfc_norflash_info_attributes[] = {
++	&dev_attr_sfc_nor_partition_offset.attr,
++	&dev_attr_sfc_nor_params_offset.attr,
++	NULL
++};
++
++static struct attribute_group sfc_norflash_info_attr_group = {
++	.attrs = sfc_norflash_info_attributes
++};
++
++int ingenic_sfcnor_register(struct nor_params_node *flash) {
++	list_add_tail(&flash->list, &nor_list);
++	return 0;
++}
++EXPORT_SYMBOL_GPL(ingenic_sfcnor_register);
++
++/*
++ *MK_CMD(cdt, cmd, LINK, ADDRMODE, DATA_EN)
++ *MK_ST(cdt, st, LINK, ADDRMODE, ADDR_WIDTH, POLL_EN, DATA_EN, TRAN_MODE)
++ */
++static void params_to_cdt(struct spi_nor_info *params, struct sfc_cdt *cdt)
++{
++
++	/* 4.nor singleRead */
++	MK_CMD(cdt[NOR_READ_STANDARD], params->read_standard, 0, ROW_ADDR, ENABLE);
++
++	/* 5.nor quadRead */
++	MK_CMD(cdt[NOR_READ_QUAD], params->read_quad, 0, ROW_ADDR, ENABLE);
++
++	/* 6. nor writeStandard */
++	MK_CMD(cdt[NOR_WRITE_STANDARD_ENABLE], params->wr_en, 1, DEFAULT_ADDRMODE, DISABLE);
++	MK_CMD(cdt[NOR_WRITE_STANDARD], params->write_standard, 1, ROW_ADDR, ENABLE);
++	MK_ST(cdt[NOR_WRITE_STANDARD_FINISH], params->busy, 0, DEFAULT_ADDRMODE, 0, ENABLE, DISABLE, TM_STD_SPI);
++
++	/* 7. nor writeQuad */
++	MK_CMD(cdt[NOR_WRITE_QUAD_ENABLE], params->wr_en, 1, DEFAULT_ADDRMODE, DISABLE);
++	MK_CMD(cdt[NOR_WRITE_QUAD], params->write_quad, 1, ROW_ADDR, ENABLE);
++	MK_ST(cdt[NOR_WRITE_QUAD_FINISH], params->busy, 0, DEFAULT_ADDRMODE, 0, ENABLE, DISABLE, TM_STD_SPI);
++
++	/* 8. nor erase */
++	MK_CMD(cdt[NOR_ERASE_WRITE_ENABLE], params->wr_en, 1, DEFAULT_ADDRMODE, DISABLE);
++	MK_CMD(cdt[NOR_ERASE], params->sector_erase, 1, ROW_ADDR, DISABLE);
++	MK_ST(cdt[NOR_ERASE_FINISH], params->busy, 0, DEFAULT_ADDRMODE, 0, ENABLE, DISABLE, TM_STD_SPI);
++
++	/* 9. quad mode */
++	if(params->quad_ops_mode){
++		MK_CMD(cdt[NOR_QUAD_SET_ENABLE], params->wr_en, 1, DEFAULT_ADDRMODE, DISABLE);
++		MK_ST(cdt[NOR_QUAD_SET], params->quad_set, 1, DEFAULT_ADDRMODE, 0, DISABLE, ENABLE, TM_STD_SPI);  //disable poll, enable data
++
++		MK_ST(cdt[NOR_QUAD_FINISH], params->busy, 1, DEFAULT_ADDRMODE, 0, ENABLE, DISABLE, TM_STD_SPI);
++
++		MK_ST(cdt[NOR_QUAD_GET], params->quad_get, 0, DEFAULT_ADDRMODE, 0, ENABLE, DISABLE, TM_STD_SPI);
++	}
++
++	/* 10. nor write ENABLE */
++	MK_CMD(cdt[NOR_WRITE_ENABLE], params->wr_en, 0, DEFAULT_ADDRMODE, DISABLE);
++
++	/* 11. entry 4byte mode */
++	MK_CMD(cdt[NOR_EN_4BYTE], params->en4byte, 0, DEFAULT_ADDRMODE, DISABLE);
++
++	/* 12. die select */
++	cdt[NOR_DIE_SELECT].link = CMD_LINK(0, DEFAULT_ADDRMODE, TM_STD_SPI);
++	cdt[NOR_DIE_SELECT].xfer = CMD_XFER(0, DISABLE, 0, ENABLE, SPINOR_OP_DIE_SEL);
++	cdt[NOR_DIE_SELECT].staExp = 0;
++	cdt[NOR_DIE_SELECT].staMsk = 0;
++
++	/* 13. read active die ID */
++	cdt[NOR_READ_ACTIVE_DIE_ID].link = CMD_LINK(0, DEFAULT_ADDRMODE, TM_STD_SPI);
++	cdt[NOR_READ_ACTIVE_DIE_ID].xfer = CMD_XFER(0, DISABLE, 0, ENABLE, SPINOR_OP_READ_DIE_ID);
++	cdt[NOR_READ_ACTIVE_DIE_ID].staExp = 0;
++	cdt[NOR_READ_ACTIVE_DIE_ID].staMsk = 0;
++
++
++}
++
++static void nor_create_cdt_table(struct sfc *sfc, void *flash_info, uint32_t flag)
++{
++	struct spinor_flashinfo *nor_info = flash_info;
++	struct sfc_cdt sfc_cdt[INDEX_MAX_NUM];
++
++	memset(sfc_cdt, 0, sizeof(sfc_cdt));
++
++	if(flag & DEFAULT_CDT){
++
++		/* 1.nor reset */
++		sfc_cdt[NOR_RESET_ENABLE].link = CMD_LINK(1, DEFAULT_ADDRMODE, TM_STD_SPI);
++		sfc_cdt[NOR_RESET_ENABLE].xfer = CMD_XFER(0, DISABLE, 0, DISABLE, SPINOR_OP_RSTEN);
++		sfc_cdt[NOR_RESET_ENABLE].staExp = 0;
++		sfc_cdt[NOR_RESET_ENABLE].staMsk = 0;
++
++		sfc_cdt[NOR_RESET].link = CMD_LINK(0, DEFAULT_ADDRMODE, TM_STD_SPI);
++		sfc_cdt[NOR_RESET].xfer = CMD_XFER(0, DISABLE, 0, DISABLE, SPINOR_OP_RST);
++		sfc_cdt[NOR_RESET].staExp = 0;
++		sfc_cdt[NOR_RESET].staMsk = 0;
++
++
++		/* 2.nor read id */
++		sfc_cdt[NOR_READ_ID].link = CMD_LINK(0, DEFAULT_ADDRMODE, TM_STD_SPI);
++		sfc_cdt[NOR_READ_ID].xfer = CMD_XFER(0, DISABLE, 0, ENABLE, SPINOR_OP_RDID);
++		sfc_cdt[NOR_READ_ID].staExp = 0;
++		sfc_cdt[NOR_READ_ID].staMsk = 0;
++
++
++		/* 3. nor get status */
++		sfc_cdt[NOR_GET_STATUS].link = CMD_LINK(0, DEFAULT_ADDRMODE, TM_STD_SPI);
++		sfc_cdt[NOR_GET_STATUS].xfer = CMD_XFER(0, DISABLE, 0, ENABLE, SPINOR_OP_RDSR);
++		sfc_cdt[NOR_GET_STATUS].staExp = 0;
++		sfc_cdt[NOR_GET_STATUS].staMsk = 0;
++
++		sfc_cdt[NOR_GET_STATUS_1].link = CMD_LINK(0, DEFAULT_ADDRMODE, TM_STD_SPI);
++		sfc_cdt[NOR_GET_STATUS_1].xfer = CMD_XFER(0, DISABLE, 0, ENABLE, SPINOR_OP_RDSR_1);
++		sfc_cdt[NOR_GET_STATUS_1].staExp = 0;
++		sfc_cdt[NOR_GET_STATUS_1].staMsk = 0;
++
++		sfc_cdt[NOR_GET_STATUS_2].link = CMD_LINK(0, DEFAULT_ADDRMODE, TM_STD_SPI);
++		sfc_cdt[NOR_GET_STATUS_2].xfer = CMD_XFER(0, DISABLE, 0, ENABLE, SPINOR_OP_RDSR_2);
++		sfc_cdt[NOR_GET_STATUS_2].staExp = 0;
++		sfc_cdt[NOR_GET_STATUS_2].staMsk = 0;
++
++		if (!(flag & UPDATE_CDT)) {
++			/* 4.nor singleRead */
++			sfc_cdt[NOR_READ_STANDARD].link = CMD_LINK(0, ROW_ADDR, TM_STD_SPI);
++			sfc_cdt[NOR_READ_STANDARD].xfer = CMD_XFER(DEFAULT_ADDRSIZE, DISABLE, 0, ENABLE, SPINOR_OP_READ);
++			sfc_cdt[NOR_READ_STANDARD].staExp = 0;
++			sfc_cdt[NOR_READ_STANDARD].staMsk = 0;
++
++			/* first create cdt table (default)*/
++			write_cdt(sfc, sfc_cdt, NOR_RESET_ENABLE, NOR_READ_STANDARD);
++			return;
++		}
++	}
++
++
++	if(flag & UPDATE_CDT){
++
++		params_to_cdt(nor_info->nor_flash_info, sfc_cdt);
++
++		if (!(flag & DEFAULT_CDT)) {
++			/* second create cdt table (update)*/
++			write_cdt(sfc, sfc_cdt, NOR_READ_STANDARD, NOR_READ_ACTIVE_DIE_ID);
++		} else {
++			/* create full cdt table (default && update)*/
++			write_cdt(sfc, sfc_cdt, NOR_RESET_ENABLE, NOR_READ_ACTIVE_DIE_ID);
++		}
++	}
++	//dump_cdt(sfc);
++	return;
++}
++
++
++static struct multi_die_flash die_flash[MULTI_DIE_FLASH_NUM] = {
++	[0] = {0xc84019, 2, "GD25S512MD"},
++};
++
++int ingenic_sfc_nor_probe(struct sfc_flash *flash)
++{
++	struct mtd_partition *ingenic_mtd_partition;
++	const char *ingenic_probe_types[] = {"cmdlinepart", "ofpart", NULL};
++	int num_partition_info = 0;
++	int err = 0,ret = 0;
++	struct spinor_flashinfo *nor_info;
++	int i;
++	int tchsh;
++	int tslch;
++	int tshsl_rd;
++	int tshsl_wr;
++	uint32_t die_size;
++
++	nor_info = kzalloc(sizeof(*nor_info), GFP_KERNEL);
++	if(!nor_info) {
++		dev_err(flash->dev, "alloc nor_info failed!\n");
++		return -ENOMEM;
++	}
++	flash->flash_info = nor_info;
++
++	set_flash_timing(flash->sfc, DEF_TCHSH, DEF_TSLCH, DEF_TSHSL_R, DEF_TSHSL_W);
++
++	/* request DMA Descriptor space */
++	ret = request_sfc_desc(flash->sfc, DESC_MAX_NUM);
++	if(ret){
++		dev_err(flash->dev, "Failure to request DMA descriptor space!\n");
++		ret = -ENOMEM;
++		goto err_sfc_desc_request;
++	}
++
++	/* try creating default CDT table */
++	flash->create_cdt_table = nor_create_cdt_table;
++	flash->create_cdt_table(flash->sfc, flash->flash_info, DEFAULT_CDT);
++
++	ret = sfc_nor_reset(flash);
++	if(ret) {
++		dev_warn(flash->dev, "Failed to reset nor flash, Try to go on\n");
++	}
++
++	ret = ingenic_spi_norflash_get_params(flash);
++	if (ret) {
++		ret = -ENODEV;
++		dev_err(flash->dev, "Failed to match correct nor flash device!\n");
++		goto err_match_device;
++	}
++
++	/* Update to private CDT table */
++	flash->create_cdt_table(flash->sfc, flash->flash_info, UPDATE_CDT);
++
++	/* Update sfc rate */
++	if((ret = sfc_clk_set_highspeed(flash->sfc))) {
++		dev_err(flash->dev, "set sfc rate failed\n");
++		goto err_match_device;
++	}
++
++#ifndef CONFIG_INGENIC_BUILTIN_PARAMS
++	num_partition_info = nor_info->norflash_partitions->num_partition_info;
++	ingenic_mtd_partition = (struct mtd_partition*)kzalloc(sizeof(struct mtd_partition) * num_partition_info, GFP_KERNEL);
++	if (!ingenic_mtd_partition) {
++		ret = -ENOMEM;
++		dev_err(flash->dev, "Failed to alloc mem for ingenic_mtd_partition\n");
++		goto err_alloc_partition;
++	}
++
++	for (i = 0; i < num_partition_info; i++) {
++		ingenic_mtd_partition[i].name = nor_info->norflash_partitions->nor_partition[i].name;
++		ingenic_mtd_partition[i].offset = nor_info->norflash_partitions->nor_partition[i].offset;
++
++		if (nor_info->norflash_partitions->nor_partition[i].size == -1) {
++			ingenic_mtd_partition[i].size = MTDPART_SIZ_FULL;
++		} else {
++			ingenic_mtd_partition[i].size = nor_info->norflash_partitions->nor_partition[i].size;
++		}
++
++		if (nor_info->norflash_partitions->nor_partition[i].mask_flags & NORFLASH_PART_RO) {    //have problem!!!
++			ingenic_mtd_partition[i].mask_flags = MTD_CAP_RAM;
++		} else {
++			ingenic_mtd_partition[i].mask_flags = MTD_CAP_ROM;
++		}
++
++	}
++#endif
++
++	flash->mtd.name     = "sfc_mtd";
++	flash->mtd.owner    = THIS_MODULE;
++	flash->mtd.type     = MTD_NORFLASH;
++	flash->mtd.flags    = MTD_CAP_NORFLASH;
++	flash->mtd.erasesize    = nor_info->nor_pri_data->fs_erase_size;
++	flash->mtd.writesize    = nor_info->nor_flash_info->page_size;
++	flash->mtd.size     = nor_info->nor_flash_info->chip_size;
++	flash->mtd._erase   = ingenic_spi_norflash_erase;
++	flash->mtd._read    = ingenic_spi_norflash_read;
++	flash->mtd._write   = ingenic_spi_norflash_write;
++
++	tchsh = nor_info->nor_flash_info->tCHSH;
++	tslch = nor_info->nor_flash_info->tSLCH;
++	tshsl_rd = nor_info->nor_flash_info->tSHSL_RD;
++	tshsl_wr = nor_info->nor_flash_info->tSHSL_WR;
++	set_flash_timing(flash->sfc, tchsh, tslch, tshsl_rd, tshsl_wr);
++
++	sfc_nor_get_special_ops(flash);
++
++	if (nor_info->nor_pri_data->uk_quad) {
++		if (nor_info->nor_flash_ops->set_quad_mode) {
++			ret = nor_info->nor_flash_ops->set_quad_mode(flash);
++			if (ret < 0) {
++				nor_info->quad_succeed = 0;
++				dev_info(flash->dev, "set quad mode error !\n");
++			} else {
++				nor_info->quad_succeed = 1;
++				dev_info(flash->dev, "nor flash quad mode is set, now use quad mode!\n");
++			}
++		}
++	}
++
++	/* Multi Die support */
++	nor_info->die_num = 1;
++	for (i = 0; i < MULTI_DIE_FLASH_NUM; i++) {
++		if(!(strcmp(die_flash[i].flash_name, nor_info->nor_flash_info->name))) {
++			nor_info->die_num = die_flash[i].die_num;
++			die_size = nor_info->nor_flash_info->chip_size / nor_info->die_num;
++			nor_info->die_shift = ffs(die_size) - 1;
++			nor_info->current_die_id = 0;
++
++			printk("Flash :%s support multi die, die number:%d\n", die_flash[i].flash_name, die_flash[i].die_num);
++			break;
++		}
++	}
++
++
++	/* if nor flash size is greater than 16M, use 4byte mode */
++	if(flash->mtd.size > NOR_SIZE_16M) {
++		if (nor_info->nor_flash_ops->set_4byte_mode) {
++			nor_info->nor_flash_ops->set_4byte_mode(flash);
++		}
++	}
++
++	/*
++	 * partiton parser:  1.cmdlinepart  2.device tree  3.flash burner
++	 */
++	flash->dev->of_node = NULL;
++	if (flash->pdata_params->use_ofpart_info) {
++		flash->dev->of_node = of_get_child_by_name(flash->dev->of_node, "norflash");
++		if (flash->dev->of_node < 0) {
++			dev_err(flash->dev, "Cannot get 'norflash' node from dtb!\n");
++			flash->dev->of_node = NULL;
++		}
++	}
++
++	ret = mtd_device_parse_register(&flash->mtd, ingenic_probe_types, &flash->ppdata, ingenic_mtd_partition, num_partition_info);
++	if (ret) {
++		ret = -ENODEV;
++		dev_err(flash->dev, "Failed to parse register!\n");
++		goto err_parse_register;
++	}
++
++	flash->attr_group = &sfc_norflash_info_attr_group;
++	ret = sysfs_create_group(&flash->dev->kobj, flash->attr_group);
++	if (err) {
++		dev_err(flash->dev, "failed to register sysfs\n");
++		ret = -EIO;
++		goto err_create_group;
++	}
++
++	dev_info(flash->dev,"SPI NOR MTD LOAD OK\n");
++	return 0;
++
++err_create_group:
++	mtd_device_unregister(&flash->mtd);
++err_parse_register:
++	kfree(ingenic_mtd_partition);
++#ifndef CONFIG_INGENIC_BUILTIN_PARAMS
++err_alloc_partition:
++	kfree(burner_params);
++#endif
++err_match_device:
++err_sfc_desc_request:
++	free_sfc_desc(flash->sfc);
++	kfree(nor_info);
++	return ret;
++
++}
++
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_ops.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_ops.c
+new file mode 100644
+index 000000000..63dc8babf
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/ingenic_sfc_ops.c
+@@ -0,0 +1,225 @@
++#include <linux/mtd/mtd.h>
++#include <linux/spinlock.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <asm/uaccess.h>
++#include "spinor.h"
++#include "ingenic_sfc_common.h"
++
++int get_status(struct sfc_flash *flash, int command, int len)
++{
++	struct spinor_flashinfo *nor_info = flash->flash_info;
++	struct spi_nor_info *spi_nor_info = nor_info->nor_flash_info;
++	struct spi_nor_st_info *quad_get;
++	struct spi_nor_st_info *busy;
++	struct sfc_cdt_xfer xfer;
++	static unsigned char buf[32];
++	unsigned int val = 0, i = 0, ret = 0;
++
++	busy = &spi_nor_info->busy;
++	quad_get = &spi_nor_info->quad_get;
++
++	memset(&xfer, 0, sizeof(xfer));
++	memset(buf, 0, sizeof(buf));
++
++	/* set index */
++	if(command == busy->cmd)
++		xfer.cmd_index = NOR_GET_STATUS;
++	else if(command == quad_get->cmd)
++		xfer.cmd_index = NOR_GET_STATUS_1;
++	else
++		xfer.cmd_index = NOR_GET_STATUS_2;
++
++	/* set addr */
++	xfer.rowaddr = 0;
++	xfer.columnaddr = 0;
++
++	/* set transfer config */
++	xfer.dataen = ENABLE;
++	xfer.config.datalen = len;
++	xfer.config.data_dir = GLB0_TRAN_DIR_READ;
++	xfer.config.ops_mode = CPU_OPS;
++	xfer.config.buf = buf;
++
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		printk("sfc_sync error! %s %s %d\n", __FILE__, __func__, __LINE__);
++		ret = -EIO;
++	}
++
++	for(i = 0; i < len; i++) {
++		val |= buf[i] << (i * 8);
++	}
++
++	return val;
++}
++
++/* do nothing to set quad mode, use cmd directly */
++static int set_quad_mode_cmd(struct sfc_flash *flash)
++{
++	return 0;
++}
++
++/* write nor flash status register QE bit to set quad mode */
++static int set_quad_mode_reg(struct sfc_flash *flash)
++{
++	struct spinor_flashinfo *nor_info = flash->flash_info;
++	struct spi_nor_info *spi_nor_info = nor_info->nor_flash_info;
++	struct spi_nor_st_info *quad_set;
++	struct spi_nor_st_info *quad_get;
++	struct spi_nor_st_info *busy;
++	unsigned int data;
++	struct sfc_cdt_xfer xfer;
++	int ret = 0;
++
++	busy = &spi_nor_info->busy;
++	quad_set = &spi_nor_info->quad_set;
++	quad_get = &spi_nor_info->quad_get;
++	data = (quad_set->val & quad_set->mask) << quad_set->bit_shift;
++
++	memset(&xfer, 0, sizeof(xfer));
++
++	/* set index */
++	xfer.cmd_index = NOR_QUAD_SET_ENABLE;
++
++	/* set addr */
++	xfer.columnaddr = 0;
++	xfer.rowaddr = 0;
++
++	/* set transfer config */
++	xfer.dataen = ENABLE;
++	xfer.config.datalen = quad_set->len;
++	xfer.config.data_dir = GLB0_TRAN_DIR_WRITE;
++	xfer.config.ops_mode = CPU_OPS;
++	xfer.config.buf = (uint8_t *)&data;
++
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		printk("sfc_sync error! %s %s %d\n", __FILE__, __func__, __LINE__);
++		ret = -EIO;
++	}
++
++	return ret;
++}
++
++static int write_enable(struct sfc_flash *flash)
++{
++	struct sfc_cdt_xfer xfer;
++	int32_t ret = 0;
++
++	memset(&xfer, 0, sizeof(xfer));
++
++	/* set index */
++	xfer.cmd_index = NOR_WRITE_ENABLE;
++
++	/* set addr */
++	xfer.columnaddr = 0;
++
++	/* set transfer config */
++	xfer.dataen = DISABLE;
++
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		printk("sfc_sync error! %s %s %d\n", __FILE__, __func__, __LINE__);
++		ret = -EIO;
++	}
++
++	return ret;
++}
++
++static int enter_4byte(struct sfc_flash *flash)
++{
++	struct sfc_cdt_xfer xfer;
++	int32_t ret = 0;
++
++	memset(&xfer, 0, sizeof(xfer));
++
++	/* set index */
++	xfer.cmd_index = NOR_EN_4BYTE;
++
++	/* set addr */
++	xfer.columnaddr = 0;
++
++	/* set transfer config */
++	xfer.dataen = DISABLE;
++
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		printk("sfc_sync error! %s %s %d\n", __FILE__, __func__, __LINE__);
++		ret = -EIO;
++	}
++
++	return ret;
++}
++
++/* send 4byte command to enter 4byte mode */
++static int set_4byte_mode_normal(struct sfc_flash *flash)
++{
++	int ret;
++	ret = enter_4byte(flash);
++	if (ret) {
++		dev_err(flash->dev, "enter 4byte mode failed\n");
++	}
++	return ret;
++}
++
++/**
++ * 1.send write enable command
++ * 2.send 4byte command to enter 4byte mode
++ **/
++static int set_4byte_mode_wren(struct sfc_flash *flash)
++{
++	int ret;
++	ret = write_enable(flash);
++	if (ret) {
++		dev_err(flash->dev, "enter 4byte mode failed\n");
++		return ret;
++	}
++
++	ret = enter_4byte(flash);
++	if (ret) {
++		dev_err(flash->dev, "enter 4byte mode failed\n");
++	}
++	return ret;
++}
++
++
++static struct spi_nor_flash_ops nor_flash_ops;
++
++static int noop(struct sfc_flash *flash)
++{
++	return 0;
++}
++
++int sfc_nor_get_special_ops(struct sfc_flash *flash)
++{
++	struct spinor_flashinfo *nor_info = flash->flash_info;
++	struct spi_nor_info *spi_nor_info = nor_info->nor_flash_info;
++
++	switch (spi_nor_info->quad_ops_mode) {
++	case 0:
++		nor_flash_ops.set_quad_mode = set_quad_mode_cmd;
++		break;
++	case 1:
++		nor_flash_ops.set_quad_mode = set_quad_mode_reg;
++		break;
++	default:
++		nor_flash_ops.set_quad_mode = noop;
++		break;
++	}
++
++	switch (spi_nor_info->addr_ops_mode) {
++	case 0:
++		nor_flash_ops.set_4byte_mode = set_4byte_mode_normal;
++		break;
++	case 1:
++		nor_flash_ops.set_4byte_mode = set_4byte_mode_wren;
++		break;
++	default:
++		nor_flash_ops.set_4byte_mode = noop;
++		break;
++	}
++
++	nor_info->nor_flash_ops = &nor_flash_ops;
++
++	return 0;
++}
++
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/Makefile b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/Makefile
+new file mode 100644
+index 000000000..1c8209140
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/Makefile
+@@ -0,0 +1,2 @@
++obj-y += ato_nand.o gd_nand.o mxic_nand.o xtx_nand.o dosilicon_nand.o foresee_nand.o xtx_mid0b_nand.o zetta_nand.o xtx_mid2c_nand.o fm_nand.o yhy_nand.o toshiba_nand.o issi_nand.o xcsp_nand.o
++obj-y += nand_common.o
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/ato_nand.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/ato_nand.c
+new file mode 100644
+index 000000000..8962155cb
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/ato_nand.c
+@@ -0,0 +1,101 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/mtd/partitions.h>
++#include "../spinand.h"
++#include "../ingenic_sfc_common.h"
++#include "nand_common.h"
++
++#define ATO_DEVICES_NUM         1
++#define TSETUP		5
++#define THOLD		5
++#define	TSHSL_R		30
++#define	TSHSL_W		30
++
++#define TRD		25
++#define TPP		500
++#define TBE		3
++
++static struct ingenic_sfcnand_device *ato_nand;
++
++static struct ingenic_sfcnand_base_param ato25d1ga_param = {
++
++	.pagesize = 2 * 1024,
++	.oobsize = 64,
++	.blocksize = 2 * 1024 * 64,
++	.flashsize = 2 * 1024 * 64 * 1024,
++
++	.tSETUP = TSETUP,
++	.tHOLD  = THOLD,
++	.tSHSL_R = TSHSL_R,
++	.tSHSL_W = TSHSL_W,
++
++	.tRD = TRD,
++	.tPP = TPP,
++	.tBE = TBE,
++
++	.plane_select = 0,
++	.ecc_max = 0,//0x3,
++	.need_quad = 1,
++
++};
++
++static struct device_id_struct device_id[ATO_DEVICES_NUM] = {
++	DEVICE_ID_STRUCT(0x12, "ATO25D1GA", &ato25d1ga_param),
++};
++
++
++static cdt_params_t *ato_get_cdt_params(struct sfc_flash *flash, uint8_t device_id)
++{
++	CDT_PARAMS_INIT(ato_nand->cdt_params);
++
++	switch(device_id) {
++		case 0x12:
++		    break;
++		default:
++		    dev_err(flash->dev, "device_id err, please check your  device id: device_id = 0x%02x\n", device_id);
++		    return NULL;
++	}
++
++	return &ato_nand->cdt_params;
++}
++
++
++static inline int deal_ecc_status(struct sfc_flash *flash, uint8_t device_id, uint8_t ecc_status)
++{
++	int ret = 0;
++	switch(device_id) {
++		case 0x12:
++			return 0;
++		default:
++			dev_err(flash->dev, "device_id err,it maybe don`t support this device, please check your device id: device_id = 0x%02x\n", device_id);
++			return -EIO;   //notice!!!
++	}
++	return ret;
++}
++
++
++static int __init ato_nand_init(void) {
++
++	ato_nand = kzalloc(sizeof(*ato_nand), GFP_KERNEL);
++	if(!ato_nand) {
++		pr_err("alloc ato_nand struct fail\n");
++		return -ENOMEM;
++	}
++
++	ato_nand->id_manufactory = 0x9B;
++	ato_nand->id_device_list = device_id;
++	ato_nand->id_device_count = ATO_DEVICES_NUM;
++
++	ato_nand->ops.get_cdt_params = ato_get_cdt_params;
++	ato_nand->ops.deal_ecc_status = deal_ecc_status;
++
++	/* use private get feature interface, please define it in this document */
++	ato_nand->ops.get_feature = NULL;
++
++	return ingenic_sfcnand_register(ato_nand);
++}
++
++fs_initcall(ato_nand_init);
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/dosilicon_nand.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/dosilicon_nand.c
+new file mode 100644
+index 000000000..ff1cdaadc
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/dosilicon_nand.c
+@@ -0,0 +1,217 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/mtd/partitions.h>
++#include "../spinand.h"
++#include "../ingenic_sfc_common.h"
++#include "nand_common.h"
++
++#define DOSILICON_DEVICES_NUM         5
++#define THOLD	    5
++#define TSETUP	    5
++#define TSHSL_R	    100
++#define TSHSL_W	    100
++
++#define TRD	    90
++#define TPP	    700
++#define TBE	    10
++
++struct ingenic_sfcnand_device *dosilicon_nand;
++
++static struct ingenic_sfcnand_base_param dosilicon_param[DOSILICON_DEVICES_NUM] = {
++	[0] = {
++	/*DS35Q1GAXXX*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tHOLD  = THOLD,
++		.tSETUP = TSETUP,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = 70,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x4,
++		.need_quad = 1,
++	},
++	[1] = {
++	/*DS35Q2GAXXX*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 2048,
++
++		.tHOLD  = THOLD,
++		.tSETUP = TSETUP,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = 90,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 1,
++		.ecc_max = 0x4,
++		.need_quad = 1,
++	},
++	[2] = {
++	/*DS35Q2GBXXX*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 128,
++		.flashsize = 2 * 1024 * 64 * 2048,
++
++		.tHOLD  = THOLD,
++		.tSETUP = TSETUP,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = 120,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 1,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++	[3] = {
++	/*DS35M1GAXXX*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tHOLD  = THOLD,
++		.tSETUP = TSETUP,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = 80,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x4,
++		.need_quad = 1,
++	},
++	[4] = {
++	/*DS35Q2GAXXX-1V8*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 2048,
++
++		.tHOLD  = THOLD,
++		.tSETUP = TSETUP,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = 90,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 1,
++		.ecc_max = 0x4,
++		.need_quad = 1,
++	},
++};
++
++static struct device_id_struct device_id[DOSILICON_DEVICES_NUM] = {
++	DEVICE_ID_STRUCT(0x71, "DS35Q1GAXXX", &dosilicon_param[0]),
++	DEVICE_ID_STRUCT(0x72, "DS35Q2GAXXX", &dosilicon_param[1]),
++	DEVICE_ID_STRUCT(0xF2, "DS35Q2GBXXX", &dosilicon_param[2]),
++	DEVICE_ID_STRUCT(0x21, "DS35M1GAXXX", &dosilicon_param[3]),
++	DEVICE_ID_STRUCT(0x22, "DS35Q2GAXXX-1V8", &dosilicon_param[4]),
++};
++
++
++static cdt_params_t *dosilicon_get_cdt_params(struct sfc_flash *flash, uint8_t device_id)
++{
++	CDT_PARAMS_INIT(dosilicon_nand->cdt_params);
++
++	switch(device_id) {
++	    case 0x71:
++	    case 0x72:
++	    case 0xF2:
++	    case 0x21:
++	    case 0x22:
++		    break;
++	    default:
++		    dev_err(flash->dev, "device_id err, please check your  device id: device_id = 0x%02x\n", device_id);
++		    return NULL;
++	}
++
++	return &dosilicon_nand->cdt_params;
++}
++
++
++static inline int deal_ecc_status(struct sfc_flash *flash, uint8_t device_id, uint8_t ecc_status)
++{
++	int ret = 0;
++
++	switch(device_id) {
++		case 0x71:
++		case 0x72:
++		case 0x21:
++		case 0x22:
++			switch((ecc_status >> 0x4) & 0x3) {
++			    case 0x0:
++			    case 0x1:
++				    ret = 0;
++				    break;
++			    case 0x2:
++				    ret = -EBADMSG;
++				    break;
++			    default:
++				   printk("it is flash Unknown state, device_id: 0x%02x\n", device_id);
++				    ret = -EIO;
++			}
++			break;
++		case 0xF2:
++			switch((ecc_status >> 4) & 0x7) {
++				case 0x2:
++					ret = -EBADMSG;
++					break;
++				default:
++					ret = 0;
++					break;
++			}
++			break;
++
++		default:
++			dev_err(flash->dev, "device_id err,it maybe don`t support this device, please check your device id: device_id = 0x%02x\n", device_id);
++		ret = -EIO;
++	}
++	return ret;
++}
++
++
++static int dosilicon_nand_init(void) {
++
++	dosilicon_nand = kzalloc(sizeof(*dosilicon_nand), GFP_KERNEL);
++	if(!dosilicon_nand) {
++		pr_err("alloc dosilicon_nand struct fail\n");
++		return -ENOMEM;
++	}
++
++	dosilicon_nand->id_manufactory = 0xE5;
++	dosilicon_nand->id_device_list = device_id;
++	dosilicon_nand->id_device_count = DOSILICON_DEVICES_NUM;
++
++	dosilicon_nand->ops.get_cdt_params = dosilicon_get_cdt_params;
++	dosilicon_nand->ops.deal_ecc_status = deal_ecc_status;
++
++	/* use private get feature interface, please define it in this document */
++	dosilicon_nand->ops.get_feature = NULL;
++
++	return ingenic_sfcnand_register(dosilicon_nand);
++}
++
++fs_initcall(dosilicon_nand_init);
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/fm_nand.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/fm_nand.c
+new file mode 100644
+index 000000000..62c98a7a6
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/fm_nand.c
+@@ -0,0 +1,126 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/mtd/partitions.h>
++#include "../spinand.h"
++#include "../ingenic_sfc_common.h"
++#include "nand_common.h"
++
++#define FM_DEVICES_NUM         2
++#define TSETUP		5
++#define THOLD		5
++#define	TSHSL_R		80
++#define	TSHSL_W		80
++
++#define TRD		100
++#define TPP		900
++#define TBE		10
++
++static struct ingenic_sfcnand_device *fm_nand;
++static struct ingenic_sfcnand_base_param fm_param[FM_DEVICES_NUM] = {
++	[0] = {
++		/*FM25S01A*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 1024,
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x1,
++		.need_quad = 1,
++	},
++	[1] = {
++		/*FM25S02A*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 1024 * 2,
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x1,
++		.need_quad = 1,
++	},
++};
++
++static struct device_id_struct device_id[FM_DEVICES_NUM] = {
++	DEVICE_ID_STRUCT(0xE4, "FM25S01A", &fm_param[0]),
++	DEVICE_ID_STRUCT(0xE5, "FM25S02A", &fm_param[1]),
++};
++
++static cdt_params_t *fm_get_cdt_params(struct sfc_flash *flash, uint8_t device_id)
++{
++	CDT_PARAMS_INIT(fm_nand->cdt_params);
++
++	switch(device_id) {
++	    case 0xE4:
++	    case 0xE5:
++		    break;
++	    default:
++		    dev_err(flash->dev, "device_id err, please check your  device id: device_id = 0x%02x\n", device_id);
++		    return NULL;
++	}
++
++	return &fm_nand->cdt_params;
++}
++
++static inline int deal_ecc_status(struct sfc_flash *flash, uint8_t device_id, uint8_t ecc_status)
++{
++	int ret = 0;
++
++	switch(device_id) {
++		case 0xE4:
++		case 0xE5:
++			switch((ret = ((ecc_status >> 4) & 0x3))) {
++				case 0x0 ... 0x1:
++					ret = 0;
++					break;
++				default:
++					ret = -EBADMSG;
++			}
++			break;
++		default:
++			dev_err(flash->dev, "device_id err, it maybe don`t support this device, check your device id: device_id = 0x%02x\n", device_id);
++			ret = -EIO;   //notice!!!
++
++	}
++	return ret;
++}
++
++static int __init fm_nand_init(void) {
++	fm_nand = kzalloc(sizeof(*fm_nand), GFP_KERNEL);
++	if(!fm_nand) {
++		pr_err("alloc fm_nand struct fail\n");
++		return -ENOMEM;
++	}
++
++	fm_nand->id_manufactory = 0xA1;
++	fm_nand->id_device_list = device_id;
++	fm_nand->id_device_count = FM_DEVICES_NUM;
++
++	fm_nand->ops.get_cdt_params = fm_get_cdt_params;
++	fm_nand->ops.deal_ecc_status = deal_ecc_status;
++
++	/* use private get feature interface, please define it in this document */
++	fm_nand->ops.get_feature = NULL;
++
++	return ingenic_sfcnand_register(fm_nand);
++}
++fs_initcall(fm_nand_init);
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/foresee_nand.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/foresee_nand.c
+new file mode 100644
+index 000000000..470d485cf
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/foresee_nand.c
+@@ -0,0 +1,145 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/mtd/partitions.h>
++#include "../spinand.h"
++#include "../ingenic_sfc_common.h"
++#include "nand_common.h"
++
++#define FS_DEVICES_NUM         2
++#define TSETUP		5
++#define THOLD		5
++#define	TSHSL_R		20
++#define	TSHSL_W		20
++
++#define TRD		180
++#define TPP		400
++#define TBE		3
++
++static struct ingenic_sfcnand_device *fs_nand;
++
++static struct ingenic_sfcnand_base_param fs_param[FS_DEVICES_NUM] = {
++
++	[0] = {
++		/*FS35ND01G*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x4,
++		.need_quad = 1,
++	},
++	[1] = {
++		/*FS35SQA001G*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = 60,
++		.tPP = 700,
++		.tBE = 10,
++
++		.plane_select = 0,
++		.ecc_max = 0x1,
++		.need_quad = 1,
++	},
++
++};
++
++static struct device_id_struct device_id[FS_DEVICES_NUM] = {
++	DEVICE_ID_STRUCT(0xA1, "FS35ND01G", &fs_param[0]),
++	DEVICE_ID_STRUCT(0x71, "F35SQA001G",&fs_param[1]),
++};
++
++
++static cdt_params_t *fs_get_cdt_params(struct sfc_flash *flash, uint8_t device_id)
++{
++	CDT_PARAMS_INIT(fs_nand->cdt_params);
++
++	switch(device_id) {
++		case 0xA1:
++			break;
++		case 0x71:
++			break;
++		default:
++			dev_err(flash->dev, "device_id err, please check your  device id: device_id = 0x%02x\n", device_id);
++			return NULL;
++	}
++
++	return &fs_nand->cdt_params;
++}
++
++
++static inline int deal_ecc_status(struct sfc_flash *flash, uint8_t device_id, uint8_t ecc_status)
++{
++	int ret = 0;
++
++	switch(device_id) {
++		case 0xA1:
++			switch((ret = ((ecc_status >> 4) & 0x7))) {
++				case 0x0 ... 0x4:
++					break;
++				default:
++					ret = -EBADMSG;
++			}
++			break;
++		case 0x71:
++			switch((ret = ((ecc_status >> 4) & 0x3))) {
++				case 0x0 ... 0x1:
++					break;
++				default:
++					ret = -EBADMSG;
++			}
++			break;
++
++		default:
++			dev_warn(flash->dev, "device_id err, it maybe don`t support this device, check your device id: device_id = 0x%02x\n", device_id);
++			ret = -EIO;   //notice!!!
++
++	}
++	return ret;
++
++}
++
++
++static int fs_nand_init(void) {
++
++	fs_nand = kzalloc(sizeof(*fs_nand), GFP_KERNEL);
++	if(!fs_nand) {
++		pr_err("alloc fs_nand struct fail\n");
++		return -ENOMEM;
++	}
++
++	fs_nand->id_manufactory = 0xCD;
++	fs_nand->id_device_list = device_id;
++	fs_nand->id_device_count = FS_DEVICES_NUM;
++
++	fs_nand->ops.get_cdt_params = fs_get_cdt_params;
++	fs_nand->ops.deal_ecc_status = deal_ecc_status;
++
++	/* use private get feature interface, please define it in this document */
++	fs_nand->ops.get_feature = NULL;
++
++	return ingenic_sfcnand_register(fs_nand);
++}
++
++fs_initcall(fs_nand_init);
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/gd_nand.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/gd_nand.c
+new file mode 100644
+index 000000000..4d920036b
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/gd_nand.c
+@@ -0,0 +1,435 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/mtd/partitions.h>
++#include "../spinand.h"
++#include "../ingenic_sfc_common.h"
++#include "nand_common.h"
++
++#define GD_DEVICES_NUM          11
++#define TSETUP		5
++#define THOLD		5
++#define	TSHSL_R		20
++#define	TSHSL_W		20
++
++#define TRD		80
++#define TRD_4G		120
++#define TPP		700
++#define TBE		5
++
++#define TRD_Q5	        50
++#define TPP_Q5	        600
++
++static struct ingenic_sfcnand_device *gd_nand;
++
++static struct ingenic_sfcnand_base_param gd_param[GD_DEVICES_NUM] = {
++
++	[0] = {
++		/*GD5F1GQ4UB*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 128,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++	[1] = {
++		 /*GD5F2GQ4UB*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 128,
++		.flashsize = 2 * 1024 * 64 * 2048,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++	[2] = {
++		/*GD5F4GQ4UB*/
++		.pagesize = 4 * 1024,
++		.blocksize = 4 * 1024 * 64,
++		.oobsize = 256,
++		.flashsize = 4 * 1024 * 64 * 2048,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD_4G,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++	[3] = {
++		/*GD5F1GQ4UC*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 128,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++	[4] = {
++		/*GD5F2GQ4UC*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 128,
++		.flashsize = 2 * 1024 * 64 * 2048,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++	[5] = {
++		/*GD5F4GQ4UC*/
++		.pagesize = 4 * 1024,
++		.blocksize = 4 * 1024 * 64,
++		.oobsize = 256,
++		.flashsize = 4 * 1024 * 64 * 2048,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD_4G,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++
++	[6] = {
++		/*GD5F1GQ4RF9IG*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++
++	[7] = {
++		/*GD5F4GQ6UE*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 4096,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x4,
++		.need_quad = 1,
++	},
++	[8] = {
++		/*GD5F2GQ5UE*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 2048,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD_Q5,
++		.tPP = TPP_Q5,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x4,
++		.need_quad = 1,
++	},
++	[9] = {
++		/*GD5F1GQ5UE*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD_Q5,
++		.tPP = TPP_Q5,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x4,
++		.need_quad = 1,
++	},
++
++	[10] = {
++		/*GD5F2GM7UE*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 2048,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = 120,
++		.tPP = TPP_Q5,
++		.tBE = 10,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++
++};
++
++static struct device_id_struct device_id[GD_DEVICES_NUM] = {
++	DEVICE_ID_STRUCT(0xD1, "GD5F1GQ4UB",&gd_param[0]),
++	DEVICE_ID_STRUCT(0xD2, "GD5F2GQ4UB",&gd_param[1]),
++	DEVICE_ID_STRUCT(0xD4, "GD5F4GQ4UB",&gd_param[2]),
++	DEVICE_ID_STRUCT(0xB1, "GD5F1GQ4UC",&gd_param[3]),
++	DEVICE_ID_STRUCT(0xB2, "GD5F2GQ4UC",&gd_param[4]),
++	DEVICE_ID_STRUCT(0xB4, "GD5F4GQ4UC",&gd_param[5]),
++	DEVICE_ID_STRUCT(0xA1, "GD5F1GQ4RF",&gd_param[6]),
++	DEVICE_ID_STRUCT(0x55, "GD5F4GQ6UE",&gd_param[7]),
++	DEVICE_ID_STRUCT(0x52, "GD5F2GQ5UE",&gd_param[8]),
++	DEVICE_ID_STRUCT(0x51, "GD5F1GQ5UE",&gd_param[9]),
++	DEVICE_ID_STRUCT(0x92, "GD5F2GM7UE",&gd_param[10]),
++};
++
++
++static cdt_params_t *gd_get_cdt_params(struct sfc_flash *flash, uint8_t device_id)
++{
++	CDT_PARAMS_INIT(gd_nand->cdt_params);
++
++	switch(device_id) {
++	    case 0xB1 ... 0xB4:
++	    case 0xA1:
++		    gd_nand->cdt_params.standard_r.addr_nbyte = 3;
++		    gd_nand->cdt_params.quad_r.addr_nbyte = 3;
++		    break;
++		case 0x92:
++	    case 0xD1 ... 0xD4:
++	    case 0x51 ... 0x55:
++		    break;
++	    default:
++		    dev_err(flash->dev, "device_id err, please check your  device id: device_id = 0x%02x\n", device_id);
++		    return NULL;
++	}
++
++	return &gd_nand->cdt_params;
++}
++
++
++static int32_t gd_get_f0_register_value(struct sfc_flash *flash)
++{
++	struct sfc_cdt_xfer xfer;
++	uint32_t buf = 0;
++
++	memset(&xfer, 0, sizeof(xfer));
++
++	/*set index*/
++	xfer.cmd_index = NAND_GET_FEATURE;
++
++	/* set addr */
++	xfer.staaddr0 = 0xf0;
++
++	/* set transfer config */
++	xfer.dataen = ENABLE;
++	xfer.config.datalen = 1;
++	xfer.config.data_dir = GLB0_TRAN_DIR_READ;
++	xfer.config.ops_mode = CPU_OPS;
++	xfer.config.buf = (uint8_t *)&buf;
++
++	if(sfc_sync_cdt(flash->sfc, &xfer)){
++	        dev_err(flash->dev,"sfc_sync_cdt error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++		return -EIO;
++	}
++	return buf;
++}
++
++
++static inline int deal_ecc_status(struct sfc_flash *flash, uint8_t device_id, uint8_t ecc_status)
++{
++	int ret = 0;
++
++	switch(device_id) {
++		case 0xA1:
++		case 0xB1 ... 0xB4:
++			switch((ecc_status >> 4) & 0x7) {
++				case 0x7:
++					ret = -EBADMSG;
++					break;
++				case 0x6:
++					ret = 0x8;
++					break;
++				case 0x5:
++					ret = 0x7;
++					break;
++				default:
++					ret = 0;
++			}
++			break;
++		case 0xD1 ... 0xD4:
++			switch((ecc_status >> 4) & 0x3) {
++				case 0x3:
++					ret = 0x8;
++					break;
++				case 0x2:
++					ret = -EBADMSG;
++					break;
++				case 0x1:
++					if((ret = gd_get_f0_register_value(flash)) < 0)
++						return ret;
++					if(((ret >> 4) & 0x3) == 0x3)
++						ret = 0x7;
++					break;
++				default:
++					ret = 0;
++					break;
++			}
++			break;
++		case 0x51:
++		case 0x55:
++			switch((ecc_status >> 4) & 0x3) {
++				case 0x3:
++				case 0x0:
++					ret = 0x0;
++					break;
++				case 0x1:
++					ret = 0x4;
++					break;
++				default:
++					ret = -EBADMSG;
++			}
++			break;
++		case 0x52:
++		case 0x92:
++			switch((ecc_status >> 4) & 0x3) {
++				case 0x1:
++					if((ret = gd_get_f0_register_value(flash)) < 0)
++						return ret;
++					switch((ecc_status >> 4) & 0x3) {
++						case 0x0:
++							ret = 0x1;
++							break;
++						case 0x1:
++							ret = 0x2;
++							break;
++						case 0x2:
++							ret = 0x3;
++							break;
++						case 0x3:
++							ret = 0x4;
++							break;
++						default:
++							break;
++					}
++					break;
++				case 0x2:
++					ret = -EBADMSG;
++					break;
++				default:
++					ret = 0x0;
++					break;
++			}
++			break;
++		default:
++			dev_err(flash->dev, "device_id err,it maybe don`t support this device, please check your device id: device_id = 0x%02x\n", device_id);
++			ret = -EIO;   //notice!!!
++	}
++	return ret;
++}
++
++
++static int __init gd_nand_init(void) {
++
++	gd_nand = kzalloc(sizeof(*gd_nand), GFP_KERNEL);
++	if(!gd_nand) {
++		pr_err("alloc gd_nand struct fail\n");
++		return -ENOMEM;
++	}
++
++	gd_nand->id_manufactory = 0xC8;
++	gd_nand->id_device_list = device_id;
++	gd_nand->id_device_count = GD_DEVICES_NUM;
++
++	gd_nand->ops.get_cdt_params = gd_get_cdt_params;
++	gd_nand->ops.deal_ecc_status = deal_ecc_status;
++
++	/* use private get feature interface, please define it in this document */
++	gd_nand->ops.get_feature = NULL;
++
++	return ingenic_sfcnand_register(gd_nand);
++}
++
++fs_initcall(gd_nand_init);
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/issi_nand.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/issi_nand.c
+new file mode 100644
+index 000000000..8b040093e
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/issi_nand.c
+@@ -0,0 +1,104 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/mtd/partitions.h>
++#include "../spinand.h"
++#include "../ingenic_sfc_common.h"
++#include "nand_common.h"
++
++#define ISSI_DEVICES_NUM         1
++#define THOLD	    5
++#define TSETUP	    5
++#define TSHSL_R	    100
++#define TSHSL_W	    100
++
++#define TRD	    100
++#define TPP	    400
++#define TBE	    10
++
++static struct ingenic_sfcnand_device *issi_nand;
++static struct ingenic_sfcnand_base_param issi_param[ISSI_DEVICES_NUM] = {
++	[0] = {
++		/*IS37SML01G1*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x1,
++		.need_quad = 1,
++	},
++};
++
++static struct device_id_struct device_id[ISSI_DEVICES_NUM] = {
++	DEVICE_ID_STRUCT(0x21, "IS37SML01G1", &issi_param[0]),
++};
++static cdt_params_t *issi_get_cdt_params(struct sfc_flash *flash, uint8_t device_id)
++{
++	CDT_PARAMS_INIT(issi_nand->cdt_params);
++	switch(device_id) {
++	    case 0x21:
++		    break;
++	    default:
++		    dev_err(flash->dev,"device_id err, please check your  device id: device_id = 0x%02x\n", device_id);
++		    return NULL;
++	}
++	return &issi_nand->cdt_params;
++}
++
++static inline int deal_ecc_status(struct sfc_flash *flash, uint8_t device_id, uint8_t ecc_status)
++{
++	int ret = 0;
++	switch(device_id) {
++		case 0x21:
++			switch((ecc_status >> 0x4) & 0x3) {
++			    case 0x0:
++			    case 0x1:
++				    ret = 0;
++				    break;
++			    case 0x2:
++				    ret = -EBADMSG;
++				    break;
++			    default:
++				    ret = -EIO;
++			            break;
++			}
++			break;
++		default:
++			dev_warn(flash->dev,"device_id err, it maybe don`t support this device, check your device id: device_id = 0x%02x\n", device_id);
++			ret = -EIO;
++	}
++	return ret;
++}
++
++static int __init issi_nand_init(void) {
++
++	issi_nand = kzalloc(sizeof(*issi_nand), GFP_KERNEL);
++	if(!issi_nand) {
++		pr_err("alloc issi_nand struct fail\n");
++		return -ENOMEM;
++	}
++	issi_nand->id_manufactory = 0xc8;
++	issi_nand->id_device_list = device_id;
++	issi_nand->id_device_count = ISSI_DEVICES_NUM;
++	issi_nand->ops.get_cdt_params = issi_get_cdt_params;
++	issi_nand->ops.deal_ecc_status = deal_ecc_status;
++	/* use private get feature interface, please define it in this document */
++	issi_nand->ops.get_feature = NULL;
++
++	return ingenic_sfcnand_register(issi_nand);
++}
++
++fs_initcall(issi_nand_init);
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/mxic_nand.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/mxic_nand.c
+new file mode 100644
+index 000000000..3dce024b6
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/mxic_nand.c
+@@ -0,0 +1,239 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/mtd/partitions.h>
++#include "../spinand.h"
++#include "../ingenic_sfc_common.h"
++#include "nand_common.h"
++
++#define MXIC_DEVICES_NUM         4
++#define MXIC_CMD_GET_ECC	0x7c
++#define THOLD	    4
++#define TSETUP	    4
++#define TSHSL_R	    100
++#define TSHSL_W	    100
++
++#define TRD	    70
++#define TPP	    600
++#define TBE	    4
++
++static struct ingenic_sfcnand_device *mxic_nand;
++
++static struct ingenic_sfcnand_base_param mxic_param[MXIC_DEVICES_NUM] = {
++	[0] = {
++	/*MX35LF1GE4AB*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tHOLD  = THOLD,
++		.tSETUP = TSETUP,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x4,
++		.need_quad = 1,
++	},
++	[1] = {
++	/*MX35LF2GE4AB*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 2048,
++
++		.tHOLD  = THOLD,
++		.tSETUP = TSETUP,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 1,
++		.ecc_max = 0x4,
++		.need_quad = 1,
++	},
++	[2] = {
++	/*MX35LF2GE4AD*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 2048,
++
++		.tHOLD  = THOLD,
++		.tSETUP = TSETUP,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = 70,
++		.tPP = 760,
++		.tBE = 6,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++	[3] = {
++	/*MX35LF4GE4AD*/
++		.pagesize = 4 * 1024,
++		.blocksize = 4 * 1024 * 64,
++		.oobsize = 128,
++		.flashsize = 4 * 1024 * 64 * 2048,
++
++		.tHOLD  = THOLD,
++		.tSETUP = TSETUP,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = 110,
++		.tPP = 800,
++		.tBE = 6,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++};
++
++static struct device_id_struct device_id[MXIC_DEVICES_NUM] = {
++	DEVICE_ID_STRUCT(0x12, "MX35LF1GE4AB", &mxic_param[0]),
++	DEVICE_ID_STRUCT(0x22, "MX35LF2GE4AB", &mxic_param[1]),
++	DEVICE_ID_STRUCT(0x26, "MX35LF2GE4AD", &mxic_param[2]),
++	DEVICE_ID_STRUCT(0x37, "MX35LF4GE4AD", &mxic_param[3]),
++};
++
++
++static cdt_params_t *mxic_get_cdt_params(struct sfc_flash *flash, uint8_t device_id)
++{
++	CDT_PARAMS_INIT(mxic_nand->cdt_params);
++
++	/* ecc status read */
++	CMD_INFO(mxic_nand->cdt_params.ecc_r, MXIC_CMD_GET_ECC, 8, 0, TM_STD_SPI);
++
++	switch(device_id) {
++	    case 0x12:
++	    case 0x22:
++	    case 0x26:
++	    case 0x37:
++		    break;
++	    default:
++		    dev_err(flash->dev, "device_id err, please check your  device id: device_id = 0x%02x\n", device_id);
++		    return NULL;
++	}
++
++	return &mxic_nand->cdt_params;
++}
++
++
++static int32_t get_ecc_value(struct sfc_flash *flash)
++{
++	struct sfc_cdt_xfer xfer;
++	uint32_t buf = 0;
++	int8_t count = 5;
++
++try_read_again:
++	memset(&xfer, 0, sizeof(xfer));
++
++	/*set index*/
++	xfer.cmd_index = NAND_ECC_STATUS_READ;
++
++	/* set addr */
++	xfer.columnaddr = 0;
++
++	/* set transfer config */
++	xfer.dataen = ENABLE;
++	xfer.config.datalen = 1;
++	xfer.config.data_dir = GLB0_TRAN_DIR_READ;
++	xfer.config.ops_mode = CPU_OPS;
++	xfer.config.buf = (uint8_t *)&buf;
++
++	if(sfc_sync_cdt(flash->sfc, &xfer) && count--){
++		goto try_read_again;
++	}
++
++	if(count < 0)
++		return -EIO;
++
++	return buf & 0xf;
++}
++
++
++static inline int deal_ecc_status(struct sfc_flash *flash, uint8_t device_id, uint8_t ecc_status)
++{
++	int ret = 0;
++
++	switch(device_id) {
++		case 0x12:
++		case 0x22:
++			switch((ecc_status >> 0x4) & 0x3) {
++				case 0x2:
++					ret = -EBADMSG;
++					break;
++				case 0x1:
++					if((ret = get_ecc_value(flash)) > 0x4)
++						ret = -EBADMSG;
++					break;
++				case 0x0:
++					ret = 0;
++					break;
++				default:
++					dev_err(flash->dev, "it is flash Unknown state, device_id: 0x%02x\n", device_id);
++					ret = -EIO;
++			}
++			break;
++		case 0x26:
++		case 0x37:
++			switch((ecc_status >> 0x4) & 0x3) {
++			    case 0x0:
++				    ret = 0;
++				    break;
++			    case 0x1:
++				    if((ret = get_ecc_value(flash)) > 0x8)
++					    ret = -EBADMSG;
++				    break;
++			    case 0x2:
++				    ret = -EBADMSG;
++				    break;
++			    default:
++				    dev_err(flash->dev, "it is flash Unknown state, device_id: 0x%02x\n", device_id);
++				    ret = -EIO;
++			}
++			break;
++		default:
++			dev_warn(flash->dev, "device_id err, it maybe don`t support this device, check your device id: device_id = 0x%02x\n", device_id);
++			ret = -EIO;
++	}
++	return ret;
++}
++
++static int __init mxic_nand_init(void) {
++
++	mxic_nand = kzalloc(sizeof(*mxic_nand), GFP_KERNEL);
++	if(!mxic_nand) {
++		pr_err("alloc mxic_nand struct fail\n");
++		return -ENOMEM;
++	}
++
++	mxic_nand->id_manufactory = 0xC2;
++	mxic_nand->id_device_list = device_id;
++	mxic_nand->id_device_count = MXIC_DEVICES_NUM;
++
++	mxic_nand->ops.get_cdt_params = mxic_get_cdt_params;
++	mxic_nand->ops.deal_ecc_status = deal_ecc_status;
++
++	/* use private get feature interface, please define it in this document */
++	mxic_nand->ops.get_feature = NULL;
++
++	return ingenic_sfcnand_register(mxic_nand);
++}
++
++fs_initcall(mxic_nand_init);
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/nand_common.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/nand_common.c
+new file mode 100644
+index 000000000..0708128b8
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/nand_common.c
+@@ -0,0 +1,66 @@
++#include <linux/types.h>
++#include <linux/export.h>
++#include "../sfc.h"
++#include "../spinand.h"
++#include "../spinand_cmd.h"
++#include "../ingenic_sfc_common.h"
++#include "nand_common.h"
++
++/*
++ * Note: the deal_ecc_status() function needs to be defined in xxx_nand.c
++ */
++int32_t nand_common_get_feature(struct sfc_flash *flash, uint8_t flag)
++{
++	struct ingenic_sfcnand_flashinfo *nand_info = flash->flash_info;
++	struct ingenic_sfcnand_ops *ops = nand_info->ops;
++	uint8_t device_id = nand_info->id_device;
++	struct sfc_cdt_xfer xfer;
++	uint8_t ecc_status = 0;
++	int32_t ret = 0;
++
++retry:
++	ecc_status = 0;
++
++	memset(&xfer, 0, sizeof(xfer));
++
++	/*set index*/
++	xfer.cmd_index = NAND_GET_FEATURE;
++
++	/* set addr */
++	xfer.staaddr0 = SPINAND_ADDR_STATUS;
++
++	/* set transfer config */
++	xfer.dataen = ENABLE;
++	xfer.config.datalen = 1;
++	xfer.config.data_dir = GLB0_TRAN_DIR_READ;
++	xfer.config.ops_mode = CPU_OPS;
++	xfer.config.buf = &ecc_status;
++
++	if(sfc_sync_cdt(flash->sfc, &xfer)) {
++		dev_err(flash->dev,"sfc_sync_cdt error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++		return -EIO;
++	}
++
++	if(ecc_status & SPINAND_IS_BUSY)
++		goto retry;
++
++	switch(flag) {
++		case GET_WRITE_STATUS:
++			if(ecc_status & (0x1 << 3))
++				ret = -EIO;
++			break;
++
++		case GET_ERASE_STATUS:
++			if(ecc_status & (0x1 << 2))
++				ret = -EIO;
++			break;
++
++		case GET_ECC_STATUS:
++			ret = ops->deal_ecc_status(flash, device_id, ecc_status);
++			break;
++		default:
++			dev_err(flash->dev,"flag value is error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++	}
++	return ret;
++}
++EXPORT_SYMBOL_GPL(nand_common_get_feature);
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/nand_common.h b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/nand_common.h
+new file mode 100644
+index 000000000..f0a143aef
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/nand_common.h
+@@ -0,0 +1,74 @@
++#ifndef __NAND_COMMON_H
++#define __NAND_COMMON_H
++#include <linux/types.h>
++#include "../sfc.h"
++#include "../sfc_flash.h"
++#include "../spinand.h"
++
++#define GET_WRITE_STATUS	1
++#define GET_ECC_STATUS		2
++#define GET_ERASE_STATUS	3
++
++/* page number of convert plane */
++#define NAND_PLANE_PAGES	64
++
++/* select plane to convert columnaddr */
++#define CONVERT_COL_ADDR(pageaddr, columnaddr) ({					\
++	uint32_t plane_flag = (pageaddr >> (ffs(NAND_PLANE_PAGES) - 1)) & 0x1;		\
++	if (plane_flag)	{								\
++		columnaddr = columnaddr | ( plane_flag << 12);				\
++	}										\
++	columnaddr;									\
++})
++
++#define DEVICE_ID_STRUCT(id, name_string, parameter) {	\
++                .id_device = id,			\
++                .name = name_string,                    \
++		.param = parameter,			\
++}
++
++#define CMD_INFO(_CMD, COMMAND, DUMMY_BIT, ADDR_LEN, TRANSFER_MODE) {	\
++	_CMD.cmd = COMMAND;			\
++	_CMD.dummy_byte = DUMMY_BIT;		\
++	_CMD.addr_nbyte = ADDR_LEN;		\
++	_CMD.transfer_mode = TRANSFER_MODE;	\
++}
++
++#define ST_INFO(_ST, COMMAND, BIT_SHIFT, MASK, VAL, LEN, DUMMY_BIT) {	\
++	_ST.cmd = COMMAND;		\
++	_ST.bit_shift = BIT_SHIFT;	\
++	_ST.mask = MASK;		\
++	_ST.val = VAL;			\
++	_ST.len = LEN;			\
++	_ST.dummy = DUMMY_BIT;		\
++}
++
++/*
++ * cdt params
++ */
++#define CDT_PARAMS_INIT(cdt_params) {	\
++	/* read to cache */							\
++	CMD_INFO(cdt_params.r_to_cache, SPINAND_CMD_PARD, 0, 3, TM_STD_SPI);	\
++	/* standard read from cache */						\
++	CMD_INFO(cdt_params.standard_r, SPINAND_CMD_FRCH, 8, 2, TM_STD_SPI);	\
++	/* quad read from cache*/						\
++	CMD_INFO(cdt_params.quad_r, SPINAND_CMD_RDCH_X4, 8, 2, TM_QI_QO_SPI);	\
++	/* standard write to cache*/						\
++	CMD_INFO(cdt_params.standard_w_cache, SPINAND_CMD_PRO_LOAD, 0, 2, TM_STD_SPI);	\
++	/* quad write to cache*/						\
++	CMD_INFO(cdt_params.quad_w_cache, SPINAND_CMD_PRO_LOAD_X4, 0, 2, TM_QI_QO_SPI);	\
++	/* write exec */							\
++	CMD_INFO(cdt_params.w_exec, SPINAND_CMD_PRO_EN, 0, 3, TM_STD_SPI);	\
++	/* block erase */							\
++	CMD_INFO(cdt_params.b_erase, SPINAND_CMD_ERASE_128K, 0, 3, TM_STD_SPI);	\
++	/* write enable */							\
++	CMD_INFO(cdt_params.w_en, SPINAND_CMD_WREN, 0, 0, TM_STD_SPI);		\
++	\
++	/* get frature wait oip not busy */					\
++	ST_INFO(cdt_params.oip, SPINAND_CMD_GET_FEATURE, 0, 0x1, 0x0, 1, 0);	\
++}
++
++
++int32_t nand_common_get_feature(struct sfc_flash *flash, uint8_t flag);
++
++#endif
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/toshiba_nand.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/toshiba_nand.c
+new file mode 100644
+index 000000000..797c90842
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/toshiba_nand.c
+@@ -0,0 +1,102 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/mtd/partitions.h>
++#include "../spinand.h"
++#include "../ingenic_sfc_common.h"
++#include "nand_common.h"
++
++#define	TOSHIBA_DEVICES_NUM         1
++#define TSETUP		3
++#define THOLD		3
++#define	TSHSL_R		100
++#define	TSHSL_W		100
++
++#define TRD		300
++#define TPP		600
++#define TBE		7
++
++static struct ingenic_sfcnand_device *toshiba_nand;
++static struct ingenic_sfcnand_base_param toshiba_param[TOSHIBA_DEVICES_NUM] = {
++
++	[0] = {
++		/*TC58CVG2S0HRAIJ */
++		.pagesize = 4 * 1024,
++		.blocksize = 4 * 1024 * 64,
++		.oobsize = 128,
++		.flashsize = 4 * 1024 * 64 * 2048,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++};
++
++static struct device_id_struct device_id[TOSHIBA_DEVICES_NUM] = {
++	DEVICE_ID_STRUCT(0xed, "TC58CVG2S0HRAIJ", &toshiba_param[0]),
++};
++static cdt_params_t *toshiba_get_cdt_params(struct sfc_flash *flash, uint8_t device_id)
++{
++	CDT_PARAMS_INIT(toshiba_nand->cdt_params);
++	switch(device_id) {
++		case 0xed:
++			break;
++		default:
++			dev_err(flash->dev,"device_id err, please check your  device id: device_id = 0x%02x\n", device_id);
++			return NULL;
++	}
++	return &toshiba_nand->cdt_params;
++}
++
++static inline int deal_ecc_status(struct sfc_flash *flash, uint8_t device_id, uint8_t ecc_status)
++{
++	int ret = 0;
++	switch(device_id) {
++		case 0xed:
++			switch((ecc_status >> 4) & 0x3) {
++				case 0x00:
++					ret = 0;
++					break;
++				case 0x01:
++					ret = 0x1;
++					break;
++				case 0x11:
++					ret = 0x11;
++					break;
++				default:
++					ret = -EBADMSG;
++					break;
++			}
++			break;
++		default:
++			dev_warn(flash->dev,"device_id err, it maybe don`t support this device, check your device id: device_id = 0x%02x\n", device_id);
++			ret = -EIO;
++	}
++	return ret;
++}
++
++static int toshiba_nand_init(void) {
++	toshiba_nand = kzalloc(sizeof(*toshiba_nand), GFP_KERNEL);
++	if(!toshiba_nand) {
++		pr_err("alloc toshiba_nand struct fail\n");
++		return -ENOMEM;
++	}
++	toshiba_nand->id_manufactory = 0x98;
++	toshiba_nand->id_device_list = device_id;
++	toshiba_nand->id_device_count = TOSHIBA_DEVICES_NUM;
++	toshiba_nand->ops.get_cdt_params = toshiba_get_cdt_params;
++	toshiba_nand->ops.deal_ecc_status = deal_ecc_status;
++	toshiba_nand->ops.get_feature = NULL;
++	return ingenic_sfcnand_register(toshiba_nand);
++}
++fs_initcall(toshiba_nand_init);
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/xcsp_nand.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/xcsp_nand.c
+new file mode 100644
+index 000000000..561a192cf
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/xcsp_nand.c
+@@ -0,0 +1,197 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/mtd/partitions.h>
++#include "../spinand.h"
++#include "../ingenic_sfc_common.h"
++#include "nand_common.h"
++
++#define XCSP_DEVICES_NUM         3
++#define TSETUP		5
++#define THOLD		5
++#define	TSHSL_R		20
++#define	TSHSL_W		20
++
++#define TRD		120
++#define TPP		600
++#define TBE		8
++
++static struct ingenic_sfcnand_device *xcsp_nand;
++
++static struct ingenic_sfcnand_base_param xcsp_param[XCSP_DEVICES_NUM] = {
++
++	[0] = {
++		/*XCSP1AAWH */
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++	[1] = {
++		/*XCSP2AAWH */
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 2048,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++	[2] = {
++		/*XCSP4AAWH */
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 4096,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++};
++
++static struct device_id_struct device_id[XCSP_DEVICES_NUM] = {
++	DEVICE_ID_STRUCT(0x01, "XCSP1AAWH ", &xcsp_param[0]),
++	DEVICE_ID_STRUCT(0xa1, "XCSP2AAWH ", &xcsp_param[1]),
++	DEVICE_ID_STRUCT(0xb1, "XCSP4AAWH ", &xcsp_param[2]),
++};
++
++
++static cdt_params_t *xcsp_nand_get_cdt_params(struct sfc_flash *flash, uint8_t device_id)
++{
++	CDT_PARAMS_INIT(xcsp_nand->cdt_params);
++
++	switch(device_id) {
++		case 0x01:
++		case 0xa1:
++		case 0xb1:
++			break;
++		default:
++			dev_err(flash->dev, "device_id err, please check your  device id: device_id = 0x%02x\n", device_id);
++			return NULL;
++	}
++	return &xcsp_nand->cdt_params;
++}
++
++static int32_t xcsp_get_f0_register_value(struct sfc_flash *flash)
++{
++	struct sfc_cdt_xfer xfer;
++	uint32_t buf = 0;
++
++	memset(&xfer, 0, sizeof(xfer));
++
++	/*set index*/
++	xfer.cmd_index = NAND_GET_FEATURE;
++
++	/* set addr */
++	xfer.staaddr0 = 0xf0;
++
++	/* set transfer config */
++	xfer.dataen = ENABLE;
++	xfer.config.datalen = 1;
++	xfer.config.data_dir = GLB0_TRAN_DIR_READ;
++	xfer.config.ops_mode = CPU_OPS;
++	xfer.config.buf = (uint8_t *)&buf;
++
++	if(sfc_sync_cdt(flash->sfc, &xfer)){
++		dev_err(flash->dev,"sfc_sync_cdt error ! %s %s %d\n",__FILE__,__func__,__LINE__);
++		return -EIO;
++	}
++	return buf;
++}
++
++
++static inline int deal_ecc_status(struct sfc_flash *flash, uint8_t device_id, uint8_t ecc_status)
++{
++	int ret = 0;
++
++	switch(device_id) {
++		case 0x01:
++		case 0xa1:
++		case 0xb1:
++			switch((ecc_status >> 4) & 0x3) {
++				case 0x0:
++					if((ret = xcsp_get_f0_register_value(flash)) < 0)
++						return ret;
++					ret = (ret >> 4) & 0x3;
++					break;
++				case 0x1:
++					if((ret = xcsp_get_f0_register_value(flash)) < 0)
++						return ret;
++					ret = ((ret >> 4) & 0x3) + 0x4;
++					break;
++				case 0x2:
++					if((ret = xcsp_get_f0_register_value(flash)) < 0)
++						return ret;
++					if(((ret >> 4) & 0x3) == 0)
++						ret = 0x8;
++					else
++						ret = -EBADMSG;
++					break;
++				case 0x3:
++					ret = -EBADMSG;
++					break;
++				default:
++					ret = 0;
++					break;
++			}
++			break;
++		default:
++			dev_warn(flash->dev, "device_id err, it maybe don`t support this device, check your device id: device_id = 0x%02x\n", device_id);
++			ret = -EIO;
++	}
++	return ret;
++}
++
++
++static int xcsp_nand_init(void) {
++
++	xcsp_nand = kzalloc(sizeof(*xcsp_nand), GFP_KERNEL);
++	if(!xcsp_nand) {
++		pr_err("alloc xcsp_nand struct fail\n");
++		return -ENOMEM;
++	}
++	xcsp_nand->id_manufactory = 0x9c;
++	xcsp_nand->id_device_list = device_id;
++	xcsp_nand->id_device_count = XCSP_DEVICES_NUM;
++	xcsp_nand->ops.get_cdt_params = xcsp_nand_get_cdt_params;
++	xcsp_nand->ops.deal_ecc_status = deal_ecc_status;
++	xcsp_nand->ops.get_feature = NULL;
++	return ingenic_sfcnand_register(xcsp_nand);
++}
++
++fs_initcall(xcsp_nand_init);
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/xtx_mid0b_nand.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/xtx_mid0b_nand.c
+new file mode 100644
+index 000000000..faaeebb75
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/xtx_mid0b_nand.c
+@@ -0,0 +1,234 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/mtd/partitions.h>
++#include "../spinand.h"
++#include "../ingenic_sfc_common.h"
++#include "nand_common.h"
++
++#define XTX_MID0B_DEVICES_NUM         4
++#define TSETUP		5
++#define THOLD		5
++#define	TSHSL_R		20
++#define	TSHSL_W		20
++
++#define TRD		260
++#define TPP		350
++#define TBE		3
++
++static struct ingenic_sfcnand_device *xtx_mid0b_nand;
++
++static struct ingenic_sfcnand_base_param xtx_mid0b_param[XTX_MID0B_DEVICES_NUM] = {
++
++	[0] = {
++		/*XT26G01A */
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++
++	[1] = {
++		/*XT26G02B */
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 2048,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x4,
++		.need_quad = 1,
++	},
++
++	[2] = {
++		/*XT26G01C */
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 128,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = 150,
++		.tPP = 450,
++		.tBE = 4,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++
++	[3] = {
++		/*XT26G02C */
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 128,
++		.flashsize = 2 * 1024 * 64 * 2048,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = 125,
++		.tPP = 350,
++		.tBE = 3,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++};
++
++static struct device_id_struct device_id[XTX_MID0B_DEVICES_NUM] = {
++	DEVICE_ID_STRUCT(0xE1, "XT26G01A ", &xtx_mid0b_param[0]),
++	DEVICE_ID_STRUCT(0xF2, "XT26G02B ", &xtx_mid0b_param[1]),
++	DEVICE_ID_STRUCT(0x11, "XT26G01C ", &xtx_mid0b_param[2]),
++	DEVICE_ID_STRUCT(0x12, "XT26G02C ", &xtx_mid0b_param[3]),
++};
++
++
++static cdt_params_t *xtx_mid0b_get_cdt_params(struct sfc_flash *flash, uint8_t device_id)
++{
++	CDT_PARAMS_INIT(xtx_mid0b_nand->cdt_params);
++
++	switch(device_id) {
++	    case 0xE1:
++	    case 0xF2:
++	    case 0x11:
++	    case 0x12:
++		    break;
++	    default:
++		    dev_err(flash->dev, "device_id err, please check your  device id: device_id = 0x%02x\n", device_id);
++		    return NULL;
++	}
++
++	return &xtx_mid0b_nand->cdt_params;
++}
++
++
++static inline int deal_ecc_status(struct sfc_flash *flash, uint8_t device_id, uint8_t ecc_status)
++{
++	int ret = 0;
++
++	switch(device_id) {
++		case 0xE1:
++			switch((ecc_status >> 2) & 0xf) {
++			    case 0x12:
++			    case 0x8:
++				ret = -EBADMSG;
++				break;
++			    case 0x0 ... 0x7:
++			    default:
++				ret = 0;
++				break;
++			}
++			break;
++
++		case 0xF2:
++			switch((ecc_status >> 4) & 0x3) {
++			    case 0x02:
++				    ret = -EBADMSG;
++				    break;
++			    case 0x03:
++				    ret = 0x8;
++				    break;
++			    default:
++				    ret = 0;
++			}
++			break;
++
++		case 0x11:
++		case 0x12:
++			switch((ecc_status >> 4) & 0xf) {
++				case 0x01:
++					ret = 0x1;
++					break;
++				case 0x02:
++					ret = 0x2;
++					break;
++				case 0x03:
++					ret = 0x3;
++					break;
++				case 0x04:
++					ret = 0x4;
++					break;
++				case 0x05:
++					ret = 0x5;
++					break;
++				case 0x06:
++					ret = 0x6;
++					break;
++				case 0x07:
++					ret = 0x7;
++					break;
++				case 0x08:
++					ret = 0x8;
++					break;
++				case 0x0f:
++					ret = -EBADMSG;
++					break;
++				default:
++					ret = 0;
++					break;
++			}
++			break;
++
++		default:
++			dev_warn(flash->dev, "device_id err, it maybe don`t support this device, check your device id: device_id = 0x%02x\n", device_id);
++			ret = -EIO;
++
++	}
++	return ret;
++}
++
++
++static int xtx_mid0b_nand_init(void) {
++
++	xtx_mid0b_nand = kzalloc(sizeof(*xtx_mid0b_nand), GFP_KERNEL);
++	if(!xtx_mid0b_nand) {
++		pr_err("alloc xtx_mid0b_nand struct fail\n");
++		return -ENOMEM;
++	}
++
++	xtx_mid0b_nand->id_manufactory = 0x0B;
++	xtx_mid0b_nand->id_device_list = device_id;
++	xtx_mid0b_nand->id_device_count = XTX_MID0B_DEVICES_NUM;
++
++	xtx_mid0b_nand->ops.get_cdt_params = xtx_mid0b_get_cdt_params;
++	xtx_mid0b_nand->ops.deal_ecc_status = deal_ecc_status;
++
++	/* use private get feature interface, please define it in this document */
++	xtx_mid0b_nand->ops.get_feature = NULL;
++
++	return ingenic_sfcnand_register(xtx_mid0b_nand);
++}
++
++fs_initcall(xtx_mid0b_nand_init);
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/xtx_mid2c_nand.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/xtx_mid2c_nand.c
+new file mode 100644
+index 000000000..9faffa3ae
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/xtx_mid2c_nand.c
+@@ -0,0 +1,124 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/mtd/partitions.h>
++#include "../spinand.h"
++#include "../ingenic_sfc_common.h"
++#include "nand_common.h"
++
++#define XTX_MID2C_DEVICES_NUM         1
++#define TSETUP		4
++#define THOLD		4
++#define	TSHSL_R		30
++#define	TSHSL_W		30
++
++#define TRD		70
++#define TPP		600
++#define TBE		10
++
++static struct ingenic_sfcnand_device *xtx_mid2c_nand;
++
++static struct ingenic_sfcnand_base_param xtx_mid2c_param[XTX_MID2C_DEVICES_NUM] = {
++
++	[0] = {
++		/*XT26G02E */
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 2048,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 1,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++
++};
++
++static struct device_id_struct device_id[XTX_MID2C_DEVICES_NUM] = {
++	DEVICE_ID_STRUCT(0x24, "XT26G02E ", &xtx_mid2c_param[0]),
++};
++
++
++static cdt_params_t *xtx_mid2c_get_cdt_params(struct sfc_flash *flash, uint8_t device_id)
++{
++	CDT_PARAMS_INIT(xtx_mid2c_nand->cdt_params);
++
++	switch(device_id) {
++	    case 0x24:
++		    break;
++	    default:
++		    dev_err(flash->dev, "device_id err, please check your  device id: device_id = 0x%02x\n", device_id);
++		    return NULL;
++	}
++
++	return &xtx_mid2c_nand->cdt_params;
++}
++
++
++static inline int deal_ecc_status(struct sfc_flash *flash, uint8_t device_id, uint8_t ecc_status)
++{
++	int ret = 0;
++
++	switch(device_id) {
++		case 0x24:
++			switch((ecc_status >> 4) & 0x7) {
++				case 0x5:
++					ret = 8;
++					break;
++				case 0x3:
++					ret = 6;
++					break;
++				case 0x2:
++					ret = -EBADMSG;
++					break;
++				case 0x1:
++					ret = 3;
++					break;
++				default:
++					ret = 0;
++					break;
++			}
++			break;
++
++		default:
++			dev_warn(flash->dev, "device_id err, it maybe don`t support this device, check your device id: device_id = 0x%02x\n", device_id);
++			ret = -EIO;
++
++	}
++	return ret;
++}
++
++
++static int xtx_mid2c_nand_init(void) {
++
++	xtx_mid2c_nand = kzalloc(sizeof(*xtx_mid2c_nand), GFP_KERNEL);
++	if(!xtx_mid2c_nand) {
++		pr_err("alloc xtx_mid2c_nand struct fail\n");
++		return -ENOMEM;
++	}
++
++	xtx_mid2c_nand->id_manufactory = 0x2C;
++	xtx_mid2c_nand->id_device_list = device_id;
++	xtx_mid2c_nand->id_device_count = XTX_MID2C_DEVICES_NUM;
++
++	xtx_mid2c_nand->ops.get_cdt_params = xtx_mid2c_get_cdt_params;
++	xtx_mid2c_nand->ops.deal_ecc_status = deal_ecc_status;
++
++	/* use private get feature interface, please define it in this document */
++	xtx_mid2c_nand->ops.get_feature = NULL;
++
++	return ingenic_sfcnand_register(xtx_mid2c_nand);
++}
++
++fs_initcall(xtx_mid2c_nand_init);
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/xtx_nand.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/xtx_nand.c
+new file mode 100644
+index 000000000..0343145e0
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/xtx_nand.c
+@@ -0,0 +1,161 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/mtd/partitions.h>
++#include "../spinand.h"
++#include "../ingenic_sfc_common.h"
++#include "nand_common.h"
++
++#define XTX_DEVICES_NUM         3
++#define TSETUP		5
++#define THOLD		5
++#define	TSHSL_R		20
++#define	TSHSL_W		20
++
++#define TRD		240
++#define TPP		1400
++#define TBE		10
++
++static struct ingenic_sfcnand_device *xtx_nand;
++
++static struct ingenic_sfcnand_base_param xtx_param[XTX_DEVICES_NUM] = {
++
++	[0] = {
++		/*PN26G01AW*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 128,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++	[1] = {
++		/*PN26G02AW */
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 128,
++		.flashsize = 2 * 1024 * 64 * 2048,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++	[2] = {
++		/*PN26Q01AW */
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 128,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x8,
++		.need_quad = 1,
++	},
++
++};
++
++static struct device_id_struct device_id[XTX_DEVICES_NUM] = {
++	DEVICE_ID_STRUCT(0xE1, "PN26G01AW", &xtx_param[0]),
++	DEVICE_ID_STRUCT(0xE2, "PN26G02AW", &xtx_param[1]),
++	DEVICE_ID_STRUCT(0xC1, "PN26Q01AW", &xtx_param[2]),
++};
++
++
++static cdt_params_t *xtx_get_cdt_params(struct sfc_flash *flash, uint8_t device_id)
++{
++	CDT_PARAMS_INIT(xtx_nand->cdt_params);
++
++	switch(device_id) {
++	    case 0xE1:
++	    case 0xE2:
++	    case 0xC1:
++		    break;
++	    default:
++		    dev_err(flash->dev, "device_id err, please check your  device id: device_id = 0x%02x\n", device_id);
++		    return NULL;
++	}
++
++	return &xtx_nand->cdt_params;
++}
++
++
++static inline int deal_ecc_status(struct sfc_flash *flash, uint8_t device_id, uint8_t ecc_status)
++{
++	int ret = 0;
++
++	switch(device_id) {
++		case 0xE1 ... 0xE2:
++		case 0xC1:
++			switch((ecc_status >> 4) & 0x3) {
++			    case 0x02:
++				    ret = -EBADMSG;
++				    break;
++			    case 0x03:
++				    ret = 0x8;
++				    break;
++			    default:
++				    ret = 0;
++			}
++			break;
++		default:
++			dev_err(flash->dev, "device_id err, it maybe don`t support this device, check your device id: device_id = 0x%02x\n", device_id);
++			ret = -EIO;   //notice!!!
++
++	}
++	return ret;
++}
++
++
++static int __init xtx_nand_init(void) {
++
++	xtx_nand = kzalloc(sizeof(*xtx_nand), GFP_KERNEL);
++	if(!xtx_nand) {
++		pr_err("alloc xtx_nand struct fail\n");
++		return -ENOMEM;
++	}
++
++	xtx_nand->id_manufactory = 0xA1;
++	xtx_nand->id_device_list = device_id;
++	xtx_nand->id_device_count = XTX_DEVICES_NUM;
++
++	xtx_nand->ops.get_cdt_params = xtx_get_cdt_params;
++	xtx_nand->ops.deal_ecc_status = deal_ecc_status;
++
++	/* use private get feature interface, please define it in this document */
++	xtx_nand->ops.get_feature = NULL;
++
++	return ingenic_sfcnand_register(xtx_nand);
++}
++
++fs_initcall(xtx_nand_init);
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/yhy_nand.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/yhy_nand.c
+new file mode 100644
+index 000000000..ab580dadd
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/yhy_nand.c
+@@ -0,0 +1,122 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/mtd/partitions.h>
++#include "../spinand.h"
++#include "../ingenic_sfc_common.h"
++#include "nand_common.h"
++
++#define	YHY_MIDC9_DEVICES_NUM         2
++#define TSETUP		5
++#define THOLD		5
++#define	TSHSL_R		20
++#define	TSHSL_W		50
++
++#define TRD		200
++#define TPP		800
++#define TBE		10
++
++static struct ingenic_sfcnand_device *yhy_midc9_nand;
++static struct ingenic_sfcnand_base_param yhy_midc9_param[YHY_MIDC9_DEVICES_NUM] = {
++
++	[0] = {
++		/*HYF1GQ4U */
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.ecc_max = 0x1,
++		.need_quad = 1,
++	},
++
++	[1] = {
++		/*HYF2GQ4U */
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 128,
++		.flashsize = 2 * 1024 * 64 * 2048,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.ecc_max = 0x1,
++		.need_quad = 1,
++	},
++
++};
++
++static struct device_id_struct device_id[YHY_MIDC9_DEVICES_NUM] = {
++	DEVICE_ID_STRUCT(0x21, "HYF1GQ4U", &yhy_midc9_param[0]),
++	DEVICE_ID_STRUCT(0x52, "HYF2GQ4U", &yhy_midc9_param[1]),
++};
++static cdt_params_t *yhy_midc9_get_cdt_params(struct sfc_flash *flash, uint8_t device_id)
++{
++	CDT_PARAMS_INIT(yhy_midc9_nand->cdt_params);
++	switch(device_id) {
++		case 0x21:
++		case 0x52:
++			break;
++		default:
++			dev_err(flash->dev,"device_id err, please check your  device id: device_id = 0x%02x\n", device_id);
++			return NULL;
++	}
++	return &yhy_midc9_nand->cdt_params;
++}
++
++static inline int deal_ecc_status(struct sfc_flash *flash, uint8_t device_id, uint8_t ecc_status)
++{
++	int ret = 0;
++	switch(device_id) {
++		case 0x21:
++		case 0x52:
++			switch((ecc_status >> 4) & 0x3) {
++				case 0x00:
++					ret = 0;
++					break;
++				case 0x01:
++					ret = 0x1;
++					break;
++				default:
++					ret = -EBADMSG;
++			}
++			break;
++		default:
++			dev_warn(flash->dev,"device_id err, it maybe don`t support this device, check your device id: device_id = 0x%02x\n", device_id);
++			ret = -EIO;
++	}
++	return ret;
++}
++
++static int yhy_midc9_nand_init(void) {
++	yhy_midc9_nand = kzalloc(sizeof(*yhy_midc9_nand), GFP_KERNEL);
++	if(!yhy_midc9_nand) {
++		pr_err("alloc yhy_nand struct fail\n");
++		return -ENOMEM;
++	}
++	yhy_midc9_nand->id_manufactory = 0xC9;
++	yhy_midc9_nand->id_device_list = device_id;
++	yhy_midc9_nand->id_device_count = YHY_MIDC9_DEVICES_NUM;
++	yhy_midc9_nand->ops.get_cdt_params = yhy_midc9_get_cdt_params;
++	yhy_midc9_nand->ops.deal_ecc_status = deal_ecc_status;
++	yhy_midc9_nand->ops.get_feature = NULL;
++	return ingenic_sfcnand_register(yhy_midc9_nand);
++}
++fs_initcall(yhy_midc9_nand_init);
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/zetta_nand.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/zetta_nand.c
+new file mode 100644
+index 000000000..d4f067b5e
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nand_device/zetta_nand.c
+@@ -0,0 +1,139 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/mtd/partitions.h>
++#include "../spinand.h"
++#include "../ingenic_sfc_common.h"
++#include "nand_common.h"
++
++#define ZETTA_DEVICES_NUM         2
++#define TSETUP		5
++#define THOLD		5
++#define	TSHSL_R		100
++#define	TSHSL_W		100
++
++#define TRD		70
++#define TPP		320
++#define TBE		2
++
++static struct ingenic_sfcnand_device *zetta_nand;
++
++static struct ingenic_sfcnand_base_param zetta_param[ZETTA_DEVICES_NUM] = {
++
++	[0] = {
++		/*ZD35Q1GA*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 0,
++		.ecc_max = 0x4,
++		.need_quad = 1,
++	},
++	[1] = {
++		/*ZD35Q1GA*/
++		.pagesize = 2 * 1024,
++		.blocksize = 2 * 1024 * 64,
++		.oobsize = 64,
++		.flashsize = 2 * 1024 * 64 * 1024,
++
++		.tSETUP  = TSETUP,
++		.tHOLD   = THOLD,
++		.tSHSL_R = TSHSL_R,
++		.tSHSL_W = TSHSL_W,
++
++		.tRD = TRD,
++		.tPP = TPP,
++		.tBE = TBE,
++
++		.plane_select = 1,
++		.ecc_max = 0x4,
++		.need_quad = 1,
++	},
++
++};
++
++static struct device_id_struct device_id[ZETTA_DEVICES_NUM] = {
++	DEVICE_ID_STRUCT(0x71, "ZD35Q1GA", &zetta_param[0]),
++	DEVICE_ID_STRUCT(0x72, "ZD35Q2GA", &zetta_param[1]),
++};
++
++
++static cdt_params_t *zetta_get_cdt_params(struct sfc_flash *flash, uint8_t device_id)
++{
++	CDT_PARAMS_INIT(zetta_nand->cdt_params);
++
++	switch(device_id) {
++	    case 0x71:
++	    case 0x72:
++		    break;
++	    default:
++		    dev_err(flash->dev, "device_id err, please check your  device id: device_id = 0x%02x\n", device_id);
++		    return NULL;
++	}
++
++	return &zetta_nand->cdt_params;
++}
++
++
++static inline int deal_ecc_status(struct sfc_flash *flash, uint8_t device_id, uint8_t ecc_status)
++{
++	int ret = 0;
++
++	switch(device_id) {
++		case 0x71:
++		case 0x72:
++			switch((ecc_status >> 4) & 0x3) {
++			    case 0x01:
++				    ret = 0x4;
++				    break;
++			    case 0x02:
++				    ret = -EBADMSG;
++				    break;
++			    default:
++				    ret = 0;
++			}
++			break;
++
++		default:
++			dev_warn(flash->dev, "device_id err, it maybe don`t support this device, check your device id: device_id = 0x%02x\n", device_id);
++			ret = -EIO;   //notice!!!
++	}
++	return ret;
++}
++
++
++static int zetta_nand_init(void)
++{
++	zetta_nand = kzalloc(sizeof(*zetta_nand), GFP_KERNEL);
++	if(!zetta_nand) {
++		pr_err("alloc zetta_nand struct fail\n");
++		return -ENOMEM;
++	}
++
++	zetta_nand->id_manufactory = 0xBA;
++	zetta_nand->id_device_list = device_id;
++	zetta_nand->id_device_count = ZETTA_DEVICES_NUM;
++
++	zetta_nand->ops.get_cdt_params = zetta_get_cdt_params;
++	zetta_nand->ops.deal_ecc_status = deal_ecc_status;
++
++	/* use private get feature interface, please define it in this document */
++	zetta_nand->ops.get_feature = NULL;
++
++	return ingenic_sfcnand_register(zetta_nand);
++}
++
++fs_initcall(zetta_nand_init);
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nor_device/Makefile b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nor_device/Makefile
+new file mode 100644
+index 000000000..1a6683390
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nor_device/Makefile
+@@ -0,0 +1 @@
++obj-y += nor_device.o
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nor_device/nor_device.c b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nor_device/nor_device.c
+new file mode 100644
+index 000000000..88e283104
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nor_device/nor_device.c
+@@ -0,0 +1,157 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/mtd/partitions.h>
++#include "../spinor.h"
++#include "../ingenic_sfc_common.h"
++#include "nor_device.h"
++
++
++#define NOR_DEVICES_NUM         3
++
++/* base params */
++static struct nor_params_node nor_params_node[NOR_DEVICES_NUM] = {
++
++#ifdef CONFIG_INGENIC_GD25Q127C
++	/*GD25Q128C*/
++	[0] = {
++		.nor_device_info.name = "GD25Q127C",
++		.nor_device_info.id = 0xc84018,
++
++		.nor_device_info.tCHSH = 5,
++		.nor_device_info.tSLCH = 5,
++		.nor_device_info.tSHSL_RD = 20,
++		.nor_device_info.tSHSL_WR = 50,
++
++		.nor_device_info.chip_size = 16777216,
++		.nor_device_info.page_size = 256,
++		.nor_device_info.erase_size = 32768,
++
++		.nor_device_info.quad_ops_mode = 1,
++		.nor_device_info.addr_ops_mode = 0,
++	},
++#endif
++
++#ifdef CONFIG_INGENIC_GD25Q256C
++	/*GD25Q256C*/
++	[1] = {
++		.nor_device_info.name = "GD25Q256C",
++		.nor_device_info.id = 0xc84019,
++
++		.nor_device_info.tCHSH = 5,
++		.nor_device_info.tSLCH = 5,
++		.nor_device_info.tSHSL_RD = 20,
++		.nor_device_info.tSHSL_WR = 50,
++
++		.nor_device_info.chip_size = 33554432,
++		.nor_device_info.page_size = 256,
++		.nor_device_info.erase_size = 32768,
++
++		.nor_device_info.quad_ops_mode = 1,
++		.nor_device_info.addr_ops_mode = 0,
++	},
++#endif
++
++#ifdef CONFIG_INGENIC_GD25S512MD
++	/*GD25S512MD*/
++	[2] = {
++		.nor_device_info.name = "GD25S512MD",
++		.nor_device_info.id = 0xc84019,
++
++		.nor_device_info.tCHSH = 5,
++		.nor_device_info.tSLCH = 8,
++		.nor_device_info.tSHSL_RD = 20,
++		.nor_device_info.tSHSL_WR = 20,
++
++		.nor_device_info.chip_size = 67108864,
++		.nor_device_info.page_size = 256,
++		.nor_device_info.erase_size = 32768,
++
++		.nor_device_info.quad_ops_mode = 1,
++		.nor_device_info.addr_ops_mode = 0,
++	},
++#endif
++
++};
++
++/* cdt params */
++static struct spi_nor_info *get_cdt_params(struct sfc_flash *flash, struct spi_nor_info *nor_device_info)
++{
++	switch(nor_device_info->id) {
++	    case 0xc84018:
++		if(!(strcmp(nor_device_info->name, "GD25Q127C"))) {
++			CDT_PARAMS_INIT_COMMON(nor_device_info, 3);
++			/* quad set		0x31 1 1 1 1 0 */
++			ST_INFO(nor_device_info->quad_set, SPINOR_OP_WRSR_1, 1, 1, 1, 1, TM_STD_SPI);
++			/* quad get		0x35 1 1 1 1 0 */
++			ST_INFO(nor_device_info->quad_get, SPINOR_OP_RDSR_1, 1, 1, 1, 1, TM_STD_SPI);
++			break;
++		    }
++	    case 0xc84019:
++		if(!(strcmp(nor_device_info->name, "GD25Q256C"))) {
++			CDT_PARAMS_INIT_COMMON(nor_device_info, 4);
++			/* entry 4byte		0xb7 0 0 0 */
++			CMD_INFO(nor_device_info->en4byte, SPINOR_OP_EN4B, 0, 0, TM_STD_SPI);
++			/* quad set		0x01 6 1 1 1 0 */
++			ST_INFO(nor_device_info->quad_set, SPINOR_OP_WRSR, 6, 1, 1, 1, TM_STD_SPI);
++			/* quad get		0x05 6 1 1 1 0 */
++			ST_INFO(nor_device_info->quad_get, SPINOR_OP_RDSR, 6, 1, 1, 1, TM_STD_SPI);
++			break;
++		}
++		if(!(strcmp(nor_device_info->name, "GD25S512MD"))) {
++			CDT_PARAMS_INIT_SPECIAL(nor_device_info);
++			/* quad set		0x31 1 1 1 1 0 */
++			ST_INFO(nor_device_info->quad_set, SPINOR_OP_WRSR_1, 1, 1, 1, 1, TM_STD_SPI);
++			/* quad get		0x35 1 1 1 1 0 */
++			ST_INFO(nor_device_info->quad_get, SPINOR_OP_RDSR_1, 1, 1, 1, 1, TM_STD_SPI);
++			break;
++		}
++	    default:
++		    dev_err(flash->dev, "device_id err, please check your  device id: device_id = 0x%02x\n", nor_device_info->id);
++		    return NULL;
++	}
++
++	return nor_device_info;
++}
++
++
++static struct nor_private_data private_data = {
++	.fs_erase_size = 32768,
++	.uk_quad = 1,
++};
++
++struct builtin_params *get_nor_builtin_params(struct sfc_flash *flash, struct builtin_params *params)
++{
++	/* private params */
++	params->magic = NOR_MAGIC;
++	params->version = NOR_VERSION;
++	params->nor_pri_data = &private_data;
++
++	/* cdt params */
++	params->spi_nor_info = get_cdt_params(flash, params->spi_nor_info);
++
++	return params;
++}
++
++
++static int __init nor_device_init(void) {
++
++	int  i, count = 0;
++	for(i = 0; i < NOR_DEVICES_NUM; i++) {
++		if (nor_params_node[i].nor_device_info.id) {
++			ingenic_sfcnor_register(&nor_params_node[i]);
++			count++;
++		}
++	}
++
++	if (!count) {
++		pr_err("Register SPI Nor Flash params fail !\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++fs_initcall(nor_device_init);
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nor_device/nor_device.h b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nor_device/nor_device.h
+new file mode 100644
+index 000000000..ce6c884c2
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/nor_device/nor_device.h
+@@ -0,0 +1,66 @@
++#ifndef __NOR_DEVICE_H
++#define __NOR_DEVICE_H
++#include <linux/types.h>
++#include "../sfc.h"
++#include "../sfc_flash.h"
++#include "../spinor.h"
++
++
++#define CMD_INFO(_CMD, COMMAND, DUMMY_BIT, ADDR_LEN, TRANSFER_MODE) {	\
++	_CMD.cmd = COMMAND;			\
++	_CMD.dummy_byte = DUMMY_BIT;		\
++	_CMD.addr_nbyte = ADDR_LEN;		\
++	_CMD.transfer_mode = TRANSFER_MODE;	\
++}
++
++#define ST_INFO(_ST, COMMAND, BIT_SHIFT, MASK, VAL, LEN, DUMMY_BIT) {	\
++	_ST.cmd = COMMAND;		\
++	_ST.bit_shift = BIT_SHIFT;	\
++	_ST.mask = MASK;		\
++	_ST.val = VAL;			\
++	_ST.len = LEN;			\
++	_ST.dummy = DUMMY_BIT;		\
++}
++
++/*
++ * create default cdt params
++ */
++#define CDT_PARAMS_INIT_COMMON(cdt_params, addr_bytes) {	\
++	/* read standard	0x03 0 3/4 0 */						\
++	CMD_INFO(cdt_params->read_standard, SPINOR_OP_READ, 0, addr_bytes, TM_STD_SPI);		\
++	/* read quad		0x6b 8 3/4 5 */						\
++	CMD_INFO(cdt_params->read_quad, SPINOR_OP_READ_1_1_4, 8, addr_bytes, TM_QI_QO_SPI);	\
++	/* write standard	0x02 0 3/4 0 */						\
++	CMD_INFO(cdt_params->write_standard, SPINOR_OP_PP, 0, addr_bytes, TM_STD_SPI);		\
++	/* write quad		0x32 0 3/4 5 */						\
++	CMD_INFO(cdt_params->write_quad, SPINOR_OP_QPP, 0, addr_bytes, TM_QI_QO_SPI);		\
++	/* erase sector		0x52 0 3/4 0 */						\
++	CMD_INFO(cdt_params->sector_erase, SPINOR_OP_BE_32K, 0, addr_bytes, TM_STD_SPI);		\
++	/* write enable		0x06 0 0 0 */						\
++	CMD_INFO(cdt_params->wr_en, SPINOR_OP_WREN, 0, 0, TM_STD_SPI);			\
++	\
++	/* wait oip not busy	0x05 0 1 0 1 0 */					\
++	ST_INFO(cdt_params->busy, SPINOR_OP_RDSR, 0, 1, 0, 1, 0);			\
++}
++
++#define CDT_PARAMS_INIT_SPECIAL(cdt_params) {	\
++	/* read standard	0x13 0 4 0 */						\
++	CMD_INFO(cdt_params->read_standard, SPINOR_OP_READ4, 0, 4, TM_STD_SPI);		\
++	/* read quad		0x6c 8 4 5 */						\
++	CMD_INFO(cdt_params->read_quad, SPINOR_OP_READ4_1_1_4, 8, 4, TM_QI_QO_SPI);	\
++	/* write standard	0x12 0 4 0 */						\
++	CMD_INFO(cdt_params->write_standard, SPINOR_OP_PP_4B, 0, 4, TM_STD_SPI);		\
++	/* write quad		0x34 0 4 5 */						\
++	CMD_INFO(cdt_params->write_quad, SPINOR_OP_QPP_4B, 0, 4, TM_QI_QO_SPI);		\
++	/* erase sector		0x5c 0 4 0 */						\
++	CMD_INFO(cdt_params->sector_erase, SPINOR_OP_BE_32K_4B, 0, 4, TM_STD_SPI);	\
++	/* entry 4byte		0xb7 0 0 0 */						\
++	CMD_INFO(cdt_params->en4byte, SPINOR_OP_EN4B, 0, 0, TM_STD_SPI);		\
++	/* write enable		0x06 0 0 0 */						\
++	CMD_INFO(cdt_params->wr_en, SPINOR_OP_WREN, 0, 0, TM_STD_SPI);			\
++	\
++	/* wait oip not busy	0x05 0 1 0 1 0 */					\
++	ST_INFO(cdt_params->busy, SPINOR_OP_RDSR, 0, 1, 0, 1, 0);			\
++}
++
++#endif
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/sfc.h b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/sfc.h
+new file mode 100644
+index 000000000..3528eb3bd
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/sfc.h
+@@ -0,0 +1,116 @@
++#ifndef __SFC_H
++#define __SFC_H
++
++#include <linux/list.h>
++#include <linux/mtd/mtd.h>
++#include <linux/irqreturn.h>
++#include <soc/sfc.h>
++
++
++struct sfc{
++	struct device *dev;
++	void __iomem	*iomem;
++	struct resource *ioarea;
++	int			irq;
++	struct clk		*clk;
++	struct clk		*clk_gate;
++	unsigned long src_clk;
++	struct completion	done;
++	spinlock_t		spin_lock;
++	uint32_t		threshold;
++	irqreturn_t (*irq_callback)(struct sfc *);
++	unsigned long		phys;
++
++	struct sfc_cdt_xfer *xfer;
++
++	struct sfc_desc	*desc;
++	dma_addr_t desc_pyaddr;
++	uint32_t desc_max_num;
++
++	uint8_t *tmp_buffer;
++	dma_addr_t tbuff_pyaddr;
++
++	uint32_t retry_count;
++};
++
++struct data_config {
++
++	uint32_t datalen;
++	uint32_t cur_len;
++	uint8_t data_dir;
++	uint8_t ops_mode;
++	uint8_t *buf;
++};
++
++struct sfc_cdt_xfer {
++
++	unsigned short cmd_index;
++	uint8_t dataen;
++	struct data_config config;
++
++	struct {
++		uint32_t columnaddr;
++		uint32_t rowaddr;
++		uint32_t staaddr0;
++		uint32_t staaddr1;
++	};
++
++};
++
++struct sfc_desc {
++	unsigned int next_des_addr;
++	unsigned int mem_addr;
++	unsigned int tran_len;
++	unsigned int link;
++};
++
++enum{
++	COL_ADDR,
++	ROW_ADDR,
++	STA_ADDR0,
++	STA_ADDR1,
++};
++
++
++/*
++ * create cdt table
++ */
++struct sfc_cdt{
++	uint32_t link;
++	uint32_t xfer;
++	uint32_t staExp;
++	uint32_t staMsk;
++};
++
++#define CMD_XFER(ADDR_WIDTH, POLL_EN, DMY_BITS, DATA_EN, CMD) (			\
++	(ADDR_WIDTH << TRAN_CONF0_ADDR_WIDTH_OFFSET)				\
++	| (POLL_EN << TRAN_CONF0_POLL_OFFSET)					\
++	| (TRAN_CONF0_CMDEN)							\
++	| (0 << TRAN_CONF0_FMAT_OFFSET)						\
++	| (DMY_BITS << TRAN_CONF0_DMYBITS_OFFSET)				\
++	| (DATA_EN << TRAN_CONF0_DATEEN_OFFSET)					\
++	| CMD									\
++	)
++
++#define CMD_LINK(LINK, ADDRMODE, TRAN_MODE) (					\
++	(LINK << 31) | (TRAN_MODE << TRAN_CONF1_TRAN_MODE_OFFSET) | (ADDRMODE)	\
++	)
++
++#define MK_CMD(cdt, cmd_info, LINK, ADDRMODE, DATA_EN)  {						\
++	cdt.link = CMD_LINK(LINK, ADDRMODE, cmd_info.transfer_mode);					\
++	cdt.xfer = CMD_XFER(cmd_info.addr_nbyte, DISABLE, cmd_info.dummy_byte, DATA_EN, cmd_info.cmd);	\
++	cdt.staExp = 0;											\
++	cdt.staMsk = 0;											\
++}
++
++#define MK_ST(cdt, st_info, LINK, ADDRMODE, ADDR_WIDTH, POLL_EN, DATA_EN, TRAN_MODE)  {			\
++	cdt.link = CMD_LINK(LINK, ADDRMODE, TRAN_MODE);							\
++	cdt.xfer = CMD_XFER(ADDR_WIDTH, POLL_EN, st_info.dummy, DATA_EN, st_info.cmd);			\
++	cdt.staExp = (st_info.val << st_info.bit_shift);						\
++	cdt.staMsk = (st_info.mask << st_info.bit_shift);						\
++}
++
++
++#endif
++
++
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/sfc_flash.h b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/sfc_flash.h
+new file mode 100644
+index 000000000..7da74297d
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/sfc_flash.h
+@@ -0,0 +1,33 @@
++#ifndef __SFC_FLASH_H
++#define __SFC_FLASH_H
++#include <linux/device.h>
++#include <linux/mutex.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++#include "sfc.h"
++
++struct sfc_flash {
++
++	struct sfc *sfc;
++	void *flash_info;
++	struct device* dev;
++	struct mtd_info mtd;
++	struct mtd_part_parser_data ppdata;
++	struct mutex	lock;
++	unsigned long sfc_init_frequency;
++	unsigned long sfc_max_frequency;
++	int param_offset;	//param_offset.
++	struct nand_chip *chip;
++	struct ingenic_sfc_info *pdata_params;
++	void (*create_cdt_table)(struct sfc *,void *, uint32_t);
++	struct attribute_group *attr_group;
++};
++
++struct ingenic_sfc_info {
++
++	uint8_t use_ofpart_info;	/* use device tree partiton flag */
++	int param_offset;		/* param_offset */
++	struct device_node *part_node;  /* flash node */
++};
++
++#endif
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/spinand.h b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/spinand.h
+new file mode 100644
+index 000000000..01a29a93a
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/spinand.h
+@@ -0,0 +1,187 @@
++#ifndef __SPINAND_H
++#define __SPINAND_H
++#include <linux/types.h>
++#include "sfc_flash.h"
++#include "spinand_cmd.h"
++
++#define SPIFLASH_PARAMER_OFFSET	0x5800
++#define SPINAND_MAGIC_NUM	0x646e616e
++
++/* the max number of DMA Descriptor */
++#define DESC_MAX_NUM		2
++
++struct ingenic_sfcnand_base_param {
++	uint32_t pagesize;
++	uint32_t blocksize;
++	uint32_t oobsize;
++	uint32_t flashsize;
++
++	uint16_t tHOLD;
++	uint16_t tSETUP;
++	uint16_t tSHSL_R;
++	uint16_t tSHSL_W;
++
++	uint16_t tRD;
++	uint16_t tPP;
++	uint16_t tBE;
++
++	/*
++	 * Indicates that NAND flash has a serial plane structure,
++	 * needs to convert the plane by changing the column address
++	 */
++	uint8_t plane_select;
++
++	uint8_t ecc_max;
++	uint8_t need_quad;
++};
++
++struct flash_address {
++	uint32_t pageaddr;
++	uint32_t columnaddr;
++	uint8_t ops_mode;
++};
++
++struct ingenic_sfcnand_partition_param {
++	struct mtd_partition *partition;
++	uint8_t num_partition;
++};
++
++struct device_id_struct {
++	uint8_t id_device;
++	char *name;
++	struct ingenic_sfcnand_base_param *param;
++};
++
++struct spi_nand_cmd_info {
++	unsigned short cmd;
++	unsigned char dummy_byte;
++	unsigned char addr_nbyte;
++	unsigned char transfer_mode;
++
++};
++
++struct spi_nand_st_info {
++	unsigned short cmd;
++	unsigned char bit_shift;
++	unsigned char mask;
++	unsigned char val;
++	unsigned char len; //length of byte to operate from register
++	unsigned char dummy;
++};
++
++struct ingenic_sfcnand_cdt_params {
++	/* general cmd info */
++	struct spi_nand_cmd_info r_to_cache;
++	struct spi_nand_cmd_info standard_r;
++	struct spi_nand_cmd_info quad_r;
++	struct spi_nand_cmd_info standard_w_cache;
++	struct spi_nand_cmd_info quad_w_cache;
++	struct spi_nand_cmd_info w_exec;
++	struct spi_nand_cmd_info b_erase;
++	struct spi_nand_cmd_info w_en;
++	struct spi_nand_cmd_info ecc_r;
++
++	/* status polling cmd info */
++	struct spi_nand_st_info oip;
++};
++typedef struct ingenic_sfcnand_cdt_params cdt_params_t;
++
++struct ingenic_sfcnand_ops {
++	cdt_params_t *(*get_cdt_params)(struct sfc_flash *, uint8_t);
++	int (*deal_ecc_status)(struct sfc_flash *, uint8_t, uint8_t);
++	int32_t (*get_feature)(struct sfc_flash *, uint8_t);
++};
++
++struct ingenic_sfcnand_device {
++	uint8_t id_manufactory;
++	struct device_id_struct *id_device_list;
++	uint8_t id_device_count;
++
++	struct ingenic_sfcnand_ops ops;
++	cdt_params_t cdt_params;
++
++	struct list_head list;
++};
++
++struct ingenic_sfcnand_flashinfo {
++	uint8_t id_manufactory;
++	uint8_t id_device;
++
++	struct ingenic_sfcnand_base_param param;
++	struct ingenic_sfcnand_partition_param partition;
++	struct ingenic_sfcnand_ops *ops;
++	cdt_params_t *cdt_params;
++};
++
++struct ingenic_sfcnand_partition {
++	char name[32];         /* identifier string */
++	uint32_t size;          /* partition size */
++	uint32_t offset;        /* offset within the master MTD space */
++	uint32_t mask_flags;       /* master MTD flags to mask out for this partition */
++	uint32_t manager_mode;     /* manager_mode mtd or ubi */
++};
++
++struct ingenic_sfcnand_burner_param {
++	uint32_t magic_num;
++	int32_t partition_num;
++	struct ingenic_sfcnand_partition *partition;
++};
++
++int32_t ingenic_sfcnand_register(struct ingenic_sfcnand_device *flash);
++
++
++/* SFC CDT Maximum INDEX number */
++#define INDEX_MAX_NUM 32
++
++/* SFC CDT INDEX */
++enum {
++	/* 1. reset */
++	NAND_RESET,
++
++	/* 2. try id */
++	NAND_TRY_ID,
++
++	/* 3. try id with dummy */
++	NAND_TRY_ID_DMY,
++
++	/* 4. set feature */
++	NAND_SET_FEATURE,
++
++	/* 5. get feature */
++	NAND_GET_FEATURE,
++
++	/* 6. nand standard read */
++	NAND_STANDARD_READ_TO_CACHE,
++	NAND_STANDARD_READ_GET_FEATURE,
++	NAND_STANDARD_READ_FROM_CACHE,
++
++	/* 7. nand quad read */
++	NAND_QUAD_READ_TO_CACHE,
++	NAND_QUAD_READ_GET_FEATURE,
++	NAND_QUAD_READ_FROM_CACHE,
++
++	/* 8. nand standard write */
++	NAND_STANDARD_WRITE_ENABLE,
++	NAND_STANDARD_WRITE_TO_CACHE,
++	NAND_STANDARD_WRITE_EXEC,
++	NAND_STANDARD_WRITE_GET_FEATURE,
++
++	/* 9. nand quad write */
++	NAND_QUAD_WRITE_ENABLE,
++	NAND_QUAD_WRITE_TO_CACHE,
++	NAND_QUAD_WRITE_EXEC,
++	NAND_QUAD_WRITE_GET_FEATURE,
++
++	/* 10. block erase */
++	NAND_ERASE_WRITE_ENABLE,
++	NAND_BLOCK_ERASE,
++	NAND_ERASE_GET_FEATURE,
++
++	/* 11. ecc status read */
++	NAND_ECC_STATUS_READ,
++
++	/* index count */
++	NAND_MAX_INDEX,
++};
++
++#endif
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/spinand_cmd.h b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/spinand_cmd.h
+new file mode 100644
+index 000000000..f0b31f27d
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/spinand_cmd.h
+@@ -0,0 +1,30 @@
++#ifndef __SPINAND_CMD_H
++#define __SPINAND_CMD_H
++
++#define SPINAND_CMD_RDID                0x9f    /* read spi nand id */
++#define SPINAND_CMD_WREN                0x06    /* spi nand write enable */
++#define SPINAND_CMD_PRO_LOAD                    0x02    /* program load */
++#define SPINAND_CMD_PRO_LOAD_X4                 0x32    /* program load fast*/
++#define SPINAND_CMD_PRO_EN              0x10    /* program load execute */
++#define SPINAND_CMD_PARD                0x13    /* read page data to spi nand cache */
++#define SPINAND_CMD_PLRd                0x84    /* program load random data */
++#define SPINAND_CMD_PLRd_X4             0xc4    /* program load random data x4*/
++#define SPINAND_CMD_RDCH                0x03    /* read from spi nand cache */
++#define SPINAND_CMD_RDCH_X4             0x6b    /* read from spi nand cache */
++#define SPINAND_CMD_FRCH                0x0b    /* fast read from spi nand cache */
++#define SPINAND_CMD_FRCH_IO             0xeb    /* for Quad I/O SPI mode */
++#define SPINAND_CMD_ERASE_128K                  0xd8    /* erase spi nand block 128K */
++#define SPINAND_CMD_GET_FEATURE                 0x0f    /* get spi nand feature */
++#define SPINAND_CMD_SET_FEATURE                 0x1f    /* set spi nand feature */
++#define SPINAND_CMD_RESET               0xff    /* reset nand flash device */
++
++
++#define SPINAND_ADDR_PROTECT    0xa0    /* protect addr */
++#define SPINAND_ADDR_STATUS     0xc0    /* get feature status addr */
++#define SPINAND_ADDR_FEATURE    0xb0    /* set feature addr */
++
++#define SPINAND_IS_BUSY                 (1 << 0)                /* PROGRAM EXECUTE, PAGE READ, BLOCK ERASE, or RESET command executing */
++#define SPINAND_OP_BL_128K      (128 * 1024)
++
++
++#endif
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/spinor.h b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/spinor.h
+new file mode 100644
+index 000000000..e2f397e6b
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/spinor.h
+@@ -0,0 +1,205 @@
++#ifndef __SPINOR_H
++#define __SPINOR_H
++#include "sfc_flash.h"
++#include "spinor_cmd.h"
++
++#define SPIFLASH_PARAMER_OFFSET 0x5800
++#define NOR_MAJOR_VERSION_NUMBER	2
++#define NOR_MINOR_VERSION_NUMBER	0
++#define NOR_REVERSION_NUMBER	0
++#define NOR_VERSION		(NOR_MAJOR_VERSION_NUMBER | (NOR_MINOR_VERSION_NUMBER << 8) | (NOR_REVERSION_NUMBER << 16))
++
++
++#define SIZEOF_NAME			32
++
++#define NOR_MAGIC	0x726f6e	//ascii "nor"
++#define NOR_PART_NUM	10
++#define NORFLASH_PART_RW	0
++#define NORFLASH_PART_WO	1
++#define NORFLASH_PART_RO	2
++
++/* the max number of DMA Descriptor */
++#define DESC_MAX_NUM	64
++
++
++struct spi_nor_cmd_info {
++	unsigned short cmd;
++	unsigned char dummy_byte;
++	unsigned char addr_nbyte;
++	unsigned char transfer_mode;
++
++};
++
++struct spi_nor_st_info {
++	unsigned short cmd;
++	unsigned char bit_shift;
++	unsigned char mask;
++	unsigned char val;
++	unsigned char len; //length of byte to operate from register
++	unsigned char dummy;
++};
++
++struct spi_nor_info {
++	unsigned char name[32];
++	unsigned int id;
++
++	struct spi_nor_cmd_info read_standard;
++	struct spi_nor_cmd_info read_quad;
++
++	struct spi_nor_cmd_info write_standard;
++	struct spi_nor_cmd_info write_quad;
++
++	struct spi_nor_cmd_info sector_erase;
++
++	struct spi_nor_cmd_info wr_en;
++	struct spi_nor_cmd_info en4byte;
++	struct spi_nor_st_info	quad_set;
++	struct spi_nor_st_info	quad_get;
++	struct spi_nor_st_info	busy;
++
++	unsigned short quad_ops_mode;
++	unsigned short addr_ops_mode;
++
++	unsigned int tCHSH;      //hold
++	unsigned int tSLCH;      //setup
++	unsigned int tSHSL_RD;   //interval
++	unsigned int tSHSL_WR;
++
++	unsigned int chip_size;
++	unsigned int page_size;
++	unsigned int erase_size;
++
++	unsigned char chip_erase_cmd;
++};
++
++struct nor_partition {
++	char name[32];
++	uint32_t size;
++	uint32_t offset;
++	uint32_t mask_flags;//bit 0-1 mask the partiton RW mode, 0:RW  1:W  2:R
++	uint32_t manager_mode;
++};
++
++struct norflash_partitions {
++	struct nor_partition nor_partition[NOR_PART_NUM];
++	uint32_t num_partition_info;
++};
++
++struct nor_private_data {
++	unsigned int fs_erase_size;
++	unsigned char uk_quad;
++};
++
++
++struct burner_params {
++	uint32_t magic;
++	uint32_t version;
++	struct spi_nor_info spi_nor_info;
++	struct norflash_partitions norflash_partitions;
++	struct nor_private_data nor_pri_data;
++};
++
++struct nor_params_node {
++	struct spi_nor_info nor_device_info;
++	struct list_head list;
++};
++
++struct builtin_params {
++	uint32_t magic;
++	uint32_t version;
++	struct spi_nor_info *spi_nor_info;
++	struct nor_private_data *nor_pri_data;
++};
++
++struct spi_nor_flash_ops {
++	int (*set_4byte_mode)(struct sfc_flash *flash);
++	int (*set_quad_mode)(struct sfc_flash *flash);
++};
++
++struct spinor_flashinfo {
++
++	uint8_t	current_die_id;
++	uint32_t die_shift;
++	uint32_t die_num;
++	int quad_succeed;
++	struct spi_nor_flash_ops *nor_flash_ops;
++	struct spi_nor_info *nor_flash_info;
++	struct spi_nor_cmd_info *cur_r_cmd;
++	struct spi_nor_cmd_info *cur_w_cmd;
++	struct norflash_partitions *norflash_partitions;
++	struct nor_private_data *nor_pri_data;
++
++};
++
++struct multi_die_flash {
++	uint32_t flash_id;
++	uint32_t die_num;
++	char* flash_name;
++};
++
++int ingenic_sfcnor_register(struct nor_params_node *);
++struct builtin_params *get_nor_builtin_params(struct sfc_flash *, struct builtin_params *);
++int32_t sfc_nor_get_special_ops(struct sfc_flash *);
++
++/* SFC CDT Maximum INDEX number */
++#define INDEX_MAX_NUM 32
++
++enum {
++	/* 1. nor reset */
++	NOR_RESET_ENABLE,
++	NOR_RESET,
++
++	/* 2. nor read id */
++	NOR_READ_ID,
++
++	/* 3. nor get status */
++	NOR_GET_STATUS,
++	NOR_GET_STATUS_1,
++	NOR_GET_STATUS_2,
++
++	/* 4. nor singleRead */
++	NOR_READ_STANDARD,
++
++	/* 5. nor quadRead */
++	NOR_READ_QUAD,
++
++	/* 6. nor writeStandard */
++	NOR_WRITE_STANDARD_ENABLE,
++	NOR_WRITE_STANDARD,
++	NOR_WRITE_STANDARD_FINISH,
++
++	/* 7. nor writeQuad */
++	NOR_WRITE_QUAD_ENABLE,
++	NOR_WRITE_QUAD,
++	NOR_WRITE_QUAD_FINISH,
++
++	/* 8. nor erase */
++	NOR_ERASE_WRITE_ENABLE,
++	NOR_ERASE,
++	NOR_ERASE_FINISH,
++
++	/* 9. quad mode */
++	NOR_QUAD_SET_ENABLE,
++	NOR_QUAD_SET,
++	NOR_QUAD_FINISH,
++	NOR_QUAD_GET,
++
++	/* 10. nor write ENABLE */
++	NOR_WRITE_ENABLE,
++
++	/* 11. entry 4byte mode */
++	NOR_EN_4BYTE,
++
++	/* 13. active die */
++	NOR_DIE_SELECT,
++
++	/* 14. read die id */
++	NOR_READ_ACTIVE_DIE_ID,
++
++	/* index count */
++	NOR_MAX_INDEX,
++};
++
++
++#endif
++
+diff --git a/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/spinor_cmd.h b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/spinor_cmd.h
+new file mode 100644
+index 000000000..d6063f1a4
+--- /dev/null
++++ b/module_drivers/drivers/mtd/devices/ingenic_sfc_v2/spinor_cmd.h
+@@ -0,0 +1,84 @@
++#ifndef __SPINOR_CMD_H
++#define __SPINOR_CMD_H
++
++/* Flash opcodes. */
++#define SPINOR_OP_RSTEN		0x66	/* reset enable */
++#define SPINOR_OP_RST		0x99	/* reset */
++#define SPINOR_OP_WREN		0x06	/* Write enable */
++#define SPINOR_OP_RDSR		0x05	/* Read status register */
++#define SPINOR_OP_RDSR_1	0x35	/* Read status1 register */
++#define SPINOR_OP_RDSR_2	0x15	/* Read status2 register */
++#define SPINOR_OP_WRSR		0x01	/* Write status register 1 byte */
++#define SPINOR_OP_WRSR_1	0x31	/* Write status1 register 1 byte */
++#define SPINOR_OP_WRSR_2	0x11	/* Write status2 register 1 byte */
++#define SPINOR_OP_READ		0x03	/* Read data bytes (low frequency) */
++#define SPINOR_OP_READ_FAST	0x0b	/* Read data bytes (high frequency) */
++#define SPINOR_OP_READ_1_1_2	0x3b	/* Read data bytes (Dual SPI) */
++#define SPINOR_OP_READ_1_1_4	0x6b	/* Read data bytes (Quad SPI) */
++#define SPINOR_OP_PP		0x02	/* Page program (up to 256 bytes) */
++#define SPINOR_OP_QPP		0x32	/* Page program (up to 256 bytes) */
++#define SPINOR_OP_BE_4K		0x20	/* Erase 4KiB block */
++#define SPINOR_OP_BE_4K_PMC	0xd7	/* Erase 4KiB block on PMC chips */
++#define SPINOR_OP_BE_32K	0x52	/* Erase 32KiB block */
++#define SPINOR_OP_CHIP_ERASE	0xc7	/* Erase whole flash chip */
++#define SPINOR_OP_SE		0xd8	/* Sector erase (usually 64KiB) */
++#define SPINOR_OP_RDID		0x9f	/* Read JEDEC ID */
++#define SPINOR_OP_RDCR		0x35	/* Read configuration register */
++#define SPINOR_OP_RDFSR		0x70	/* Read flag status register */
++#define SPINOR_OP_DIE_SEL	0xc2    /* Software Die Select */
++#define SPINOR_OP_READ_DIE_ID	0xf8    /* Read Active Die ID */
++
++/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
++#define SPINOR_OP_READ4		0x13	/* Read data bytes (low frequency) */
++#define SPINOR_OP_READ4_FAST	0x0c	/* Read data bytes (high frequency) */
++#define SPINOR_OP_READ4_1_1_2	0x3c	/* Read data bytes (Dual SPI) */
++#define SPINOR_OP_READ4_1_1_4	0x6c	/* Read data bytes (Quad SPI) */
++#define SPINOR_OP_PP_4B		0x12	/* Page program (up to 256 bytes) */
++#define SPINOR_OP_QPP_4B	0x34	/* Page program (up to 256 bytes) */
++#define SPINOR_OP_SE_4B		0xdc	/* Sector erase (usually 64KiB) */
++#define SPINOR_OP_BE_32K_4B	0x5c	/* Erase 32KiB block */
++
++/* Used for SST flashes only. */
++#define SPINOR_OP_BP		0x02	/* Byte program */
++#define SPINOR_OP_WRDI		0x04	/* Write disable */
++#define SPINOR_OP_AAI_WP	0xad	/* Auto address increment word program */
++
++/* Used for Macronix and Winbond flashes. */
++#define SPINOR_OP_EN4B		0xb7	/* Enter 4-byte mode */
++#define SPINOR_OP_EX4B		0xe9	/* Exit 4-byte mode */
++
++/* Used for Spansion flashes only. */
++#define SPINOR_OP_BRWR		0x17	/* Bank register write */
++
++/* Status Register bits. */
++#define SR_WIP			1	/* Write in progress */
++#define SR_WEL			2	/* Write enable latch */
++#define SR_SQE			(1 << 1)	/* QUAD MODE enable */
++/* meaning of other SR_* bits may differ between vendors */
++#define SR_BP0			4	/* Block protect 0 */
++#define SR_BP1			8	/* Block protect 1 */
++#define SR_BP2			0x10	/* Block protect 2 */
++#define SR_SRWD			0x80	/* SR write protect */
++
++#define SR_QUAD_EN_MX		0x40	/* Macronix Quad I/O */
++
++/* Flag Status Register bits */
++#define FSR_READY		0x80
++
++/* Configuration Register bits. */
++#define CR_QUAD_EN_SPAN		0x2	/* Spansion Quad I/O */
++
++
++#define CMD_WREN 	0x06	/* Write Enable */
++#define CMD_EN4B				0xB7
++#define CMD_EX4B				0xE9
++/* nor cmd entry deep power down and Release from Deep Power-Down and Read Device ID */
++#define CMD_DP (0xB9)
++#define CMD_RDP (0xAB)
++
++
++#define BUFFER_SIZE PAGE_SIZE
++
++#define NOR_SIZE_16M	0x1000000
++
++#endif
+diff --git a/module_drivers/drivers/net/Makefile b/module_drivers/drivers/net/Makefile
+new file mode 100644
+index 000000000..94ab82927
+--- /dev/null
++++ b/module_drivers/drivers/net/Makefile
+@@ -0,0 +1,3 @@
++obj-y += ethernet/
++obj-y += wireless/
++#obj-y += can/
+diff --git a/module_drivers/drivers/net/ethernet/Makefile b/module_drivers/drivers/net/ethernet/Makefile
+new file mode 100644
+index 000000000..10e2febc6
+--- /dev/null
++++ b/module_drivers/drivers/net/ethernet/Makefile
+@@ -0,0 +1 @@
++obj-y += ingenic/
+diff --git a/module_drivers/drivers/net/ethernet/ingenic/Kconfig b/module_drivers/drivers/net/ethernet/ingenic/Kconfig
+new file mode 100644
+index 000000000..10fc5cbed
+--- /dev/null
++++ b/module_drivers/drivers/net/ethernet/ingenic/Kconfig
+@@ -0,0 +1,46 @@
++config INGENIC_MAC
++	tristate "ingenic on-chip MAC support"
++	select CRC32
++	select MII
++	help
++	  This is the driver for INGENIC on-chip mac device.
++
++config INGENIC_MAC_DMA_INTERFACES
++	bool "Ingenic mac dma interfaces"
++	depends on INGENIC_MAC
++	help
++	  This is for MAC Dma interfaces selection
++choice
++	prompt "Ingenic mac dma bus interfaces"
++	depends on INGENIC_MAC_DMA_INTERFACES
++
++config INGENIC_MAC_AXI_BUS
++	bool "MAC_AXI_BUS"
++	help
++	  Select for mac dma AXI bus
++
++config INGENIC_MAC_AHB_BUS
++	bool "MAC_AHB_BUS"
++	help
++	  Select for mac dma AHB bus
++endchoice
++
++config INGENIC_GMAC_USE_HWSTAMP
++    bool "Use IEEE 1588 hwstamp"
++	depends on INGENIC_MAC
++	select PTP_1588_CLOCK
++	help
++	  To support the IEEE 1588 Precision Time Protocol (PTP)
++
++config INGENIC_GMAC_MUTUAL_TRANS
++    bool "Dual core mutex transmission"
++	depends on INGENIC_MAC
++	help
++	  Dual core mutex transmission for cache bumps
++
++config INGENIC_GMAC_RX_DESC_COUNT
++    int "Ingenic gmac receive descriptor number[80..10240]"
++	depends on INGENIC_MAC
++        default 512
++	help
++	  Ingenic gmac receive descriptor number
+diff --git a/module_drivers/drivers/net/ethernet/ingenic/Makefile b/module_drivers/drivers/net/ethernet/ingenic/Makefile
+new file mode 100644
+index 000000000..d72badfeb
+--- /dev/null
++++ b/module_drivers/drivers/net/ethernet/ingenic/Makefile
+@@ -0,0 +1,31 @@
++
++####################################################
++# Explanation for EXTRA_FLAGS
++# -DDEBUG		     => Enable the debug trace for driver
++# -DIPC_OFFLOAD		     => Enables the IP and TCP checksum offloading feature in HW (IPV4 only)
++# -DENH_DESC		     => Enables Enhanced Descriptors
++# -DENH_DESC_8W              => Enable Enhanced Descriptors of 8words or else Descriptor will be of 4words.
++####################################################
++
++
++#with the below flags enables Debug messages
++
++#EXTRA_CFLAGS += -DDEBUG
++#EXTRA_CFLAGS +=-DDEBUG -DIPC_OFFLOAD
++#EXTRA_CFLAGS += -DDEBUG -DIPC_OFFLOAD
++#EXTRA_CFLAGS += -DIPC_OFFLOAD
++
++
++#Enhanced Descriptor
++#EXTRA_CFLAGS += -DENH_DESC
++#EXTRA_CFLAGS += -DENH_DESC -DIPC_OFFLOAD
++EXTRA_CFLAGS += -DENH_DESC -DENH_DESC_8W
++#EXTRA_CFLAGS += -DDEBUG -DENH_DESC -DENH_DESC_8W
++#EXTRA_CFLAGS += -DDEBUG -DENH_DESC -DENH_DESC_8W -DIPC_OFFLOAD
++#EXTRA_CFLAGS += -DENH_DESC -DENH_DESC_8W -DIPC_OFFLOAD
++#EXTRA_CFLAGS += -DENH_DESC -DENH_DESC_8W -DAVB_SUPPORT  -DDEBUG
++#EXTRA_CFLAGS += -DENH_DESC -DENH_DESC_8W -DAVB_SUPPORT
++#EXTRA_CFLAGS += -DENH_DESC -DENH_DESC_8W
++
++obj-$(CONFIG_INGENIC_MAC) += mac.o
++mac-objs := synopGMAC_plat.o synopGMAC_Dev.o ethtool.o ingenic_mac.o
+diff --git a/module_drivers/drivers/net/ethernet/ingenic/ethtool.c b/module_drivers/drivers/net/ethernet/ingenic/ethtool.c
+new file mode 100644
+index 000000000..fc76b9526
+--- /dev/null
++++ b/module_drivers/drivers/net/ethernet/ingenic/ethtool.c
+@@ -0,0 +1,284 @@
++/* Intel PRO/1000 Linux driver
++ * Copyright(c) 1999 - 2015 Intel Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in
++ * the file called "COPYING".
++ *
++ */
++
++/* ethtool support for ingenic_mac */
++
++#include <linux/netdevice.h>
++#include <linux/interrupt.h>
++#include <linux/ethtool.h>
++#include <linux/pci.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/vmalloc.h>
++#include <linux/pm_runtime.h>
++#include <linux/phy.h>
++
++#include "ingenic_mac.h"
++
++struct ingenic_mac_reg
++{
++	u32    addr;
++	char   * name;
++};
++
++static struct ingenic_mac_reg mac[] =
++{
++	{ 0x0000, "                  Config" },
++	{ 0x0004, "            Frame Filter" },
++	{ 0x0008, "             MAC HT High" },
++	{ 0x000C, "              MAC HT Low" },
++	{ 0x0010, "               GMII Addr" },
++	{ 0x0014, "               GMII Data" },
++	{ 0x0018, "            Flow Control" },
++	{ 0x001C, "                VLAN Tag" },
++	{ 0x0020, "            GMAC Version" },
++	{ 0x0024, "            GMAC Debug  " },
++	{ 0x0028, "Remote Wake-Up Frame Filter" },
++	{ 0x002C, "  PMT Control and Status" },
++	{ 0x0030, "  LPI Control and status" },
++	{ 0x0034, "      LPI Timers Control" },
++	{ 0x0038, "        Interrupt Status" },
++	{ 0x003c, "        Interrupt Mask" },
++	{ 0x0040, "          MAC Addr0 High" },
++	{ 0x0044, "           MAC Addr0 Low" },
++	{ 0x0048, "          MAC Addr1 High" },
++	{ 0x004c, "           MAC Addr1 Low" },
++	{ 0x0100, "           MMC Ctrl Reg " },
++	{ 0x010c, "        MMC Intr Msk(rx)" },
++	{ 0x0110, "        MMC Intr Msk(tx)" },
++	{ 0x0200, "    MMC Intr Msk(rx ipc)" },
++	{ 0x0700, "       Timestamp control" },
++	{ 0x0704, "    Sub-Second Increment" },
++	{ 0x0708, "                 Seconds" },
++	{ 0x070c, "             Nanoseconds" },
++	{ 0x0710, "          Update seconds" },
++	{ 0x0714, "      Update Nanoseconds" },
++	{ 0x0718, "        Adjust frequency" },
++	{ 0x0738, "          AVMAC Ctrl Reg" },
++	{ 0x00D8, "           RGMII C/S Reg" },
++	{ 0, 0 }
++};
++static struct ingenic_mac_reg dma0[] =
++{
++	{ 0x0000, "[CH0] CSR0   Bus Mode" },
++	{ 0x0004, "[CH0] CSR1   TxPlDmnd" },
++	{ 0x0008, "[CH0] CSR2   RxPlDmnd" },
++	{ 0x000C, "[CH0] CSR3    Rx Base" },
++	{ 0x0010, "[CH0] CSR4    Tx Base" },
++	{ 0x0014, "[CH0] CSR5     Status" },
++	{ 0x0018, "[CH0] CSR6    Control" },
++	{ 0x001C, "[CH0] CSR7 Int Enable" },
++	{ 0x0020, "[CH0] CSR8 Missed Fr." },
++	{ 0x0028, "[CH0] CSR10 AXI Mode." },
++	{ 0x0024, "[CH0] Recv Intr Wd.Tm." },
++	{ 0x0028, "[CH0] AXI Bus Mode   " },
++	{ 0x002c, "[CH0] AHB or AXI Status" },
++	{ 0x0048, "[CH0] CSR18 Tx Desc  " },
++	{ 0x004C, "[CH0] CSR19 Rx Desc  " },
++	{ 0x0050, "[CH0] CSR20 Tx Buffer" },
++	{ 0x0054, "[CH0] CSR21 Rx Buffer" },
++	{ 0x0058, "CSR22 HWCFG          " },
++	{ 0, 0 }
++};
++
++__attribute__((__unused__)) static void ingenic_mac_dump_dma_regs(synopGMACdevice *gmacdev)
++{
++	struct ingenic_mac_reg *reg = dma0;
++
++	printk("======================DMA Regs start===================\n");
++	while(reg->name) {
++		printk("===>%s:\t0x%08x\n", reg->name, synopGMACReadReg((u32 *)gmacdev->DmaBase,reg->addr));
++		reg++;
++	}
++	printk("======================DMA Regs end===================\n");
++}
++
++__attribute__((__unused__)) static void ingenic_mac_dump_mac_regs(synopGMACdevice *gmacdev)
++{
++	struct ingenic_mac_reg *reg = mac;
++
++	printk("======================MAC Regs start===================\n");
++	while(reg->name) {
++		printk("===>%s:\t0x%08x\n", reg->name, synopGMACReadReg((u32 *)gmacdev->MacBase,reg->addr));
++		reg++;
++	}
++	printk("======================MAC Regs end===================\n");
++}
++
++__attribute__((__unused__)) static void ingenic_mac_dump_phy_regs(struct ingenic_mac_local *lp) {
++	u16 phy[] = {0, 1, 4, 5, 6, 9, 10, 15, 16, 17, 18, 20, 21, 24, 0x1c};
++
++	u16 data[sizeof(phy) / sizeof(u16)];
++	int i;
++
++	printk("======================PHY Regs start===================\n");
++	printk("\n-------->PHY dump: %08x\n", lp->phydev->phy_id);
++	for (i = 0; i < sizeof(phy) / sizeof(u16); i++)
++		data[i] = lp->mii_bus->read(lp->mii_bus, lp->phydev->mdio.addr, phy[i]);
++
++	for (i = 0; i < sizeof(phy) / sizeof(u16); i++)
++		printk("PHY reg%d, value %04x\n", phy[i], data[i]);
++	printk("======================PHY Regs end===================\n");
++
++}
++
++__attribute__((__unused__)) static void ingenic_mac_dump_all_regs(struct net_device *netdev) {
++
++	struct ingenic_mac_local *lp = netdev_priv(netdev);
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	ingenic_mac_dump_phy_regs(lp);
++	ingenic_mac_dump_dma_regs(gmacdev);
++	ingenic_mac_dump_mac_regs(gmacdev);
++
++}
++
++static void ingenic_get_drvinfo(struct net_device *netdev,
++			      struct ethtool_drvinfo *drvinfo)
++{
++	struct ingenic_mac_local *lp = netdev_priv(netdev);
++	strlcpy(drvinfo->driver, INGENIC_MAC_DRV_NAME,sizeof(drvinfo->driver));
++	strlcpy(drvinfo->version, INGENIC_MAC_DRV_VERSION,sizeof(drvinfo->version));
++}
++
++static int ingenic_get_regs_len(struct net_device __always_unused *netdev)
++{
++	return 0;
++}
++
++static void ingenic_get_regs(struct net_device *netdev,
++			   struct ethtool_regs *regs, void *p)
++{
++	pm_runtime_get_sync(netdev->dev.parent);
++	ingenic_mac_dump_all_regs(netdev);
++	pm_runtime_put_sync(netdev->dev.parent);
++}
++
++static void ingenic_get_pauseparam(struct net_device *ndev,
++		struct ethtool_pauseparam *pp)
++{
++	const struct ingenic_mac_local *lp = netdev_priv(ndev);
++
++	pp->autoneg = lp->flowcontrol.autoneg;
++	pp->tx_pause = lp->flowcontrol.tx;
++	pp->rx_pause = lp->flowcontrol.rx;
++}
++
++static int ingenic_set_pauseparam(struct net_device *ndev,
++		struct ethtool_pauseparam *pp)
++{
++	struct ingenic_mac_local *lp = netdev_priv(ndev);
++	int ret = 0;
++
++	lp->flowcontrol.autoneg = pp->autoneg;
++	if (pp->autoneg) {
++		linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, lp->phydev->advertising);
++		linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, lp->phydev->advertising);
++	} else {
++		linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, lp->phydev->advertising);
++		linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, lp->phydev->advertising);
++		lp->flowcontrol.rx = pp->rx_pause;
++		lp->flowcontrol.tx = pp->tx_pause;
++	}
++
++	if (netif_running(ndev))
++		ret = phy_start_aneg(lp->phydev);
++
++	return ret;
++}
++
++
++static int ingenic_set_coalesce(struct net_device *netdev,
++			      struct ethtool_coalesce *ec)
++{
++	struct ingenic_mac_local *lp = netdev_priv(netdev);
++
++	/* Check not supported parameters  */
++	if ((ec->rx_max_coalesced_frames) || (ec->rx_coalesce_usecs_irq) ||
++	    (ec->rx_max_coalesced_frames_irq) || (ec->tx_coalesce_usecs_irq) ||
++	    (ec->use_adaptive_rx_coalesce) || (ec->use_adaptive_tx_coalesce) ||
++	    (ec->pkt_rate_low) || (ec->rx_coalesce_usecs_low) ||
++	    (ec->rx_max_coalesced_frames_low) || (ec->tx_coalesce_usecs_high) ||
++	    (ec->tx_max_coalesced_frames_low) || (ec->pkt_rate_high) ||
++	    (ec->tx_coalesce_usecs_low) || (ec->rx_coalesce_usecs_high) ||
++	    (ec->rx_max_coalesced_frames_high) ||
++	    (ec->tx_max_coalesced_frames_irq) ||
++	    (ec->stats_block_coalesce_usecs) ||
++	    (ec->tx_max_coalesced_frames) ||
++	    (ec->tx_max_coalesced_frames_high) || (ec->rate_sample_interval))
++		return -EOPNOTSUPP;
++
++	if (ec->tx_coalesce_usecs > INGENIC_TX_MAX_COALESCE_USECS ||
++		ec->tx_coalesce_usecs < INGENIC_TX_MIN_COALESCE_USECS)
++		return -EINVAL;
++	if (ec->rx_coalesce_usecs > INGENIC_RX_MAX_COALESCE_USECS ||
++		ec->rx_coalesce_usecs < INGENIC_RX_MIN_COALESCE_USECS)
++		return -EINVAL;
++
++	lp->tx_coalesce_usecs = ec->tx_coalesce_usecs;
++	lp->rx_coalesce_usecs = ec->rx_coalesce_usecs;
++
++	return 0;
++}
++
++static int ingenic_get_coalesce(struct net_device *netdev,
++			      struct ethtool_coalesce *ec)
++{
++	struct ingenic_mac_local *lp = netdev_priv(netdev);
++
++	ec->tx_coalesce_usecs = lp->tx_coalesce_usecs;
++	ec->rx_coalesce_usecs = lp->rx_coalesce_usecs;
++
++	return 0;
++}
++static u32 ingenic_get_msglevel(struct net_device *ndev)
++{
++	const struct ingenic_mac_local *lp = netdev_priv(ndev);
++
++	return lp->msg_enable;
++}
++
++static void ingenic_set_msglevel(struct net_device *ndev, u32 msglevel)
++{
++	struct ingenic_mac_local *lp = netdev_priv(ndev);
++
++	lp->msg_enable = msglevel;
++}
++
++static const struct ethtool_ops ingenic_mac_ethtool_ops = {
++
++	.set_link_ksettings	= phy_ethtool_set_link_ksettings,
++	.get_link_ksettings	= phy_ethtool_get_link_ksettings,
++	.get_drvinfo		= ingenic_get_drvinfo,
++	.get_regs_len		= ingenic_get_regs_len,
++	.get_regs		= ingenic_get_regs,
++	.get_link		= ethtool_op_get_link,
++	.get_pauseparam		= ingenic_get_pauseparam,
++	.set_pauseparam		= ingenic_set_pauseparam,
++	.get_coalesce		= ingenic_get_coalesce,
++	.set_coalesce		= ingenic_set_coalesce,
++	.get_msglevel		= ingenic_get_msglevel,
++	.set_msglevel		= ingenic_set_msglevel,
++	.supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS
++				| ETHTOOL_COALESCE_RX_MAX_FRAMES
++				| ETHTOOL_COALESCE_TX_USECS
++				| ETHTOOL_COALESCE_TX_MAX_FRAMES,
++};
++
++void ingenic_mac_set_ethtool_ops(struct net_device *netdev)
++{
++	netdev->ethtool_ops = &ingenic_mac_ethtool_ops;
++}
+diff --git a/module_drivers/drivers/net/ethernet/ingenic/ingenic_mac.c b/module_drivers/drivers/net/ethernet/ingenic/ingenic_mac.c
+new file mode 100644
+index 000000000..f7eddcbcb
+--- /dev/null
++++ b/module_drivers/drivers/net/ethernet/ingenic/ingenic_mac.c
+@@ -0,0 +1,3424 @@
++/*
++ *  ingenic On-Chip MAC Driver
++ *
++ *  Copyright (C) 2010 - 2011  Ingenic Semiconductor Inc.
++ *
++ *  Licensed under the GPL-2 or later.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/timer.h>
++#include <linux/slab.h>
++#include <linux/vmalloc.h>
++#include <linux/errno.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/crc32.h>
++#include <linux/device.h>
++#include <linux/spinlock.h>
++#include <linux/mii.h>
++#include <linux/phy.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool.h>
++#include <linux/skbuff.h>
++#include <linux/platform_device.h>
++#include <linux/of_gpio.h>
++#include <linux/of_platform.h>
++#include <linux/dma-mapping.h>
++#include <linux/interrupt.h>
++#include <linux/clk.h>
++#include "ingenic_mac.h"
++#include <dt-bindings/net/ingenic_gmac.h>
++
++MODULE_AUTHOR("Lutts Wolf <slcao@ingenic.cn>");
++MODULE_VERSION(INGENIC_MAC_DRV_VERSION);
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION(INGENIC_MAC_DRV_DESC);
++MODULE_ALIAS("platform:"INGENIC_MAC_DRV_NAME);
++
++#define COPYBREAK_DEFAULT 256
++static unsigned int copybreak __read_mostly = COPYBREAK_DEFAULT;
++module_param(copybreak, uint, 0644);
++MODULE_PARM_DESC(copybreak, "Maximum size of packet that is copied to a new buffer on receive");
++
++int debug_enable = 0;
++module_param(debug_enable, int, 0644);
++MODULE_PARM_DESC(debug_enable, "ingenic mac TR(x) debug level (0=none,...,16=all)");
++
++int msg_level = 0;
++module_param(msg_level, int, 0644);
++MODULE_PARM_DESC(msg_level, "ingenic mac msg debug level (0=none,...,15=all)");
++
++#define INGENIC_MAC_RX_BUFFER_WRITE	16	/* Must be power of 2 */
++#define MAX_TIMEOUT_CNT 5000
++
++/* Generate the bit field mask from msb to lsb */
++#define BITS_H2L(msb, lsb)  ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))
++
++static int inline ingenic_mac_clean_tx_irq(struct ingenic_mac_local *lp);
++static const struct of_device_id ingenic_mac_dt_match[];
++
++static int ingenic_mac_phy_hwrst(struct platform_device *pdev, bool init)
++{
++	struct net_device *ndev = platform_get_drvdata(pdev);
++	struct ingenic_mac_local *lp = netdev_priv(ndev);
++	struct device *dev = &pdev->dev;
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++	struct pinctrl *p = pinctrl_get(dev);
++	struct pinctrl_state *state = NULL;
++
++	if (IS_ERR_OR_NULL(p)) {
++		dev_warn(&pdev->dev, "can not get pinctrl\n");
++		return 0;
++	}
++
++	if (init)
++		lp->reset_gpio = -ENODEV;
++
++	if (!(lp->reset_gpio < 0))
++		goto hw_reset;
++
++	lp->reset_gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if (lp->reset_gpio < 0)
++		goto out;
++	ret = devm_gpio_request(dev, lp->reset_gpio, "mac-hw-rst");
++	if (ret) {
++		lp->reset_gpio = ret;
++		dev_err(dev, "ingenic mac-hw-rst gpio request failed errno(%d)\n", ret);
++		goto out;
++	}
++	lp->reset_lvl = flags & OF_GPIO_ACTIVE_LOW ? 0 : 1;
++
++#define DEFAULT_RESET_DELAY_MS 10
++	ret = of_property_read_u32(np, "ingenic,rst-delay-ms", &lp->reset_delay_ms);
++	if (ret < 0)
++		lp->reset_delay_ms = DEFAULT_RESET_DELAY_MS;
++#undef DEFAULT_RESET_DELAY_MS
++
++
++#define DEFAULT_RESET_MS 10
++	ret = of_property_read_u32(np, "ingenic,rst-ms", &lp->reset_ms);
++	if (ret < 0)
++		lp->reset_ms = DEFAULT_RESET_MS;
++#undef DEFAULT_RESET_MS
++
++hw_reset:
++	state = pinctrl_lookup_state(p, "reset");
++	if (!IS_ERR_OR_NULL(state))
++		pinctrl_select_state(p, state);
++
++	gpio_direction_output(lp->reset_gpio, lp->reset_lvl);
++	if (in_atomic())
++		mdelay(lp->reset_ms);
++	else
++		msleep(lp->reset_ms);
++	gpio_direction_output(lp->reset_gpio, !lp->reset_lvl);
++
++	state = pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT);
++	if (!IS_ERR_OR_NULL(state))
++		pinctrl_select_state(p, state);
++
++	if (in_atomic())
++		mdelay(lp->reset_delay_ms);
++	else
++		msleep(lp->reset_delay_ms);
++out:
++	pinctrl_put(p);
++	return ret;
++}
++
++
++static void ingenic_set_mdc_rate(struct ingenic_mac_local *lp)
++{
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	unsigned int rate;
++	unsigned int div_val;
++
++	rate = clk_get_rate(lp->clk_gate)/1000000;
++	if(rate > 250)
++		div_val = GmiiCsrClk5;
++	else if(rate > 150)
++		div_val = GmiiCsrClk4;
++	else if(rate > 100)
++		div_val = GmiiCsrClk1;
++	else if(rate > 60)
++		div_val = GmiiCsrClk0;
++	else if(rate > 35)
++		div_val = GmiiCsrClk3;
++	else if(rate > 20)
++		div_val = GmiiCsrClk2;
++	else
++		div_val = GmiiCsrClk5;
++
++	synopGMAC_set_mdc_clk_div(gmacdev, div_val);
++	gmacdev->ClockDivMdc = synopGMAC_get_mdc_clk_div(gmacdev);
++}
++
++static inline unsigned char str2hexnum(unsigned char c)
++{
++	if (c >= '0' && c <= '9')
++		return c - '0';
++	if (c >= 'a' && c <= 'f')
++		return c - 'a' + 10;
++	if (c >= 'A' && c <= 'F')
++		return c - 'A' + 10;
++
++	return 0; /* foo */
++}
++
++static inline void str2eaddr(unsigned char *ea, unsigned char *str)
++{
++	int i;
++
++	for (i = 0; i < 6; i++) {
++		unsigned char num;
++
++		if ((*str == '.') || (*str == ':'))
++			str++;
++		num  = str2hexnum(*str++) << 4;
++		num |= str2hexnum(*str++);
++		ea[i] = num;
++	}
++}
++
++static int bootargs_ethaddr[2] = {0,};
++static unsigned char ethaddr_hex[2][6];
++
++static int __init ethernet_mac0_addr_setup(char *str)
++{
++	if (!str) {
++		printk("ethaddr not set in command line\n");
++		return -1;
++	}
++	bootargs_ethaddr[0] = 1;
++	str2eaddr(ethaddr_hex[0], str);
++
++	return 0;
++}
++
++static int __init ethernet_mac1_addr_setup(char *str)
++{
++	if (!str) {
++		printk("ethaddr not set in command line\n");
++		return -1;
++	}
++	bootargs_ethaddr[1] = 1;
++	str2eaddr(ethaddr_hex[1], str);
++
++	return 0;
++}
++
++__setup("ethaddr=", ethernet_mac0_addr_setup);
++__setup("ethaddr1=", ethernet_mac1_addr_setup);
++
++
++/* debug routines */
++__attribute__((__unused__)) static void ingenic_mac_dump_pkt_data(unsigned char *data, int len) {
++	int i = 0;
++	printk("\t0x0000: ");
++	for (i = 0; i < len; i++) {
++		printk("%02x", data[i]);
++
++		if (i % 2)
++			printk(" ");
++
++		if ( (i != 0) && ((i % 16) == 15) )
++			printk("\n\t0x%04x: ", i+1);
++	}
++	printk("\n");
++}
++
++__attribute__((__unused__)) static void ingenic_mac_dump_skb_data(struct sk_buff *skb) {
++	printk("\n\n===================================\n");
++	printk("head = 0x%08x, data = 0x%08x, tail = 0x%08x, end = 0x%08x\n",
++			(unsigned int)(skb->head), (unsigned int)(skb->data),
++			(unsigned int)(skb->tail), (unsigned int)(skb->end));
++	printk("len = %d\n", skb->len);
++	ingenic_mac_dump_pkt_data(skb->data, skb->len);
++	printk("\n=====================================\n");
++}
++
++struct ingenic_mac_reg
++{
++	u32    addr;
++	char   * name;
++};
++
++static struct ingenic_mac_reg mac[] =
++{
++	{ 0x0000, "                  Config" },
++	{ 0x0004, "            Frame Filter" },
++	{ 0x0008, "             MAC HT High" },
++	{ 0x000C, "              MAC HT Low" },
++	{ 0x0010, "               GMII Addr" },
++	{ 0x0014, "               GMII Data" },
++	{ 0x0018, "            Flow Control" },
++	{ 0x001C, "                VLAN Tag" },
++	{ 0x0020, "            GMAC Version" },
++	{ 0x0024, "            GMAC Debug  " },
++	{ 0x0028, "Remote Wake-Up Frame Filter" },
++	{ 0x002C, "  PMT Control and Status" },
++	{ 0x0030, "  LPI Control and status" },
++	{ 0x0034, "      LPI Timers Control" },
++	{ 0x0038, "        Interrupt Status" },
++	{ 0x003c, "        Interrupt Mask" },
++	{ 0x0040, "          MAC Addr0 High" },
++	{ 0x0044, "           MAC Addr0 Low" },
++	{ 0x0048, "          MAC Addr1 High" },
++	{ 0x004c, "           MAC Addr1 Low" },
++	{ 0x0100, "           MMC Ctrl Reg " },
++	{ 0x010c, "        MMC Intr Msk(rx)" },
++	{ 0x0110, "        MMC Intr Msk(tx)" },
++	{ 0x0200, "    MMC Intr Msk(rx ipc)" },
++	{ 0x0700, "       Timestamp control" },
++	{ 0x0704, "    Sub-Second Increment" },
++	{ 0x0708, "                 Seconds" },
++	{ 0x070c, "             Nanoseconds" },
++	{ 0x0710, "          Update seconds" },
++	{ 0x0714, "      Update Nanoseconds" },
++	{ 0x0718, "        Adjust frequency" },
++	{ 0x0738, "          AVMAC Ctrl Reg" },
++	{ 0x00D8, "           RGMII C/S Reg" },
++	{ 0, 0 }
++};
++static struct ingenic_mac_reg dma0[] =
++{
++	{ 0x0000, "[CH0] CSR0   Bus Mode" },
++	{ 0x0004, "[CH0] CSR1   TxPlDmnd" },
++	{ 0x0008, "[CH0] CSR2   RxPlDmnd" },
++	{ 0x000C, "[CH0] CSR3    Rx Base" },
++	{ 0x0010, "[CH0] CSR4    Tx Base" },
++	{ 0x0014, "[CH0] CSR5     Status" },
++	{ 0x0018, "[CH0] CSR6    Control" },
++	{ 0x001C, "[CH0] CSR7 Int Enable" },
++	{ 0x0020, "[CH0] CSR8 Missed Fr." },
++	{ 0x0028, "[CH0] CSR10 AXI Mode." },
++	{ 0x0024, "[CH0] Recv Intr Wd.Tm." },
++	{ 0x0028, "[CH0] AXI Bus Mode   " },
++	{ 0x002c, "[CH0] AHB or AXI Status" },
++	{ 0x0048, "[CH0] CSR18 Tx Desc  " },
++	{ 0x004C, "[CH0] CSR19 Rx Desc  " },
++	{ 0x0050, "[CH0] CSR20 Tx Buffer" },
++	{ 0x0054, "[CH0] CSR21 Rx Buffer" },
++	{ 0x0058, "CSR22 HWCFG          " },
++	{ 0, 0 }
++};
++
++__attribute__((__unused__)) static void ingenic_mac_dump_dma_regs(synopGMACdevice *gmacdev, const char *func, int line)
++{
++	struct ingenic_mac_reg *reg = dma0;
++
++	printk("======================DMA Regs start===================\n");
++	while(reg->name) {
++		printk("===>%s:\t0x%08x\n", reg->name, synopGMACReadReg((u32 *)gmacdev->DmaBase,reg->addr));
++		reg++;
++	}
++	printk("======================DMA Regs end===================\n");
++}
++
++__attribute__((__unused__)) static void ingenic_mac_dump_mac_regs(synopGMACdevice *gmacdev, const char *func, int line)
++{
++	struct ingenic_mac_reg *reg = mac;
++
++	printk("======================MAC Regs start===================\n");
++	while(reg->name) {
++		printk("===>%s:\t0x%08x\n", reg->name, synopGMACReadReg((u32 *)gmacdev->MacBase,reg->addr));
++		reg++;
++	}
++	printk("======================MAC Regs end===================\n");
++}
++
++__attribute__((__unused__)) static void ingenic_mac_dump_all_regs(synopGMACdevice *gmacdev, const char *func, int line) {
++	ingenic_mac_dump_dma_regs(gmacdev, func, line);
++	ingenic_mac_dump_mac_regs(gmacdev, func, line);
++}
++
++__attribute__((__unused__)) static void ingenic_mac_dump_dma_buffer_info(struct ingenic_mac_buffer *buffer_info) {
++	printk("\tbuffer_info(%p):\n", buffer_info);
++	printk("\t\tskb = %p\n", buffer_info->skb);
++	printk("\t\tdma = 0x%08x\n", buffer_info->dma);
++	printk("\t\tlen = %u\n", buffer_info->length);
++	printk("\t\ttrans = %d\n", buffer_info->transfering);
++	printk("\t\tinvalid = %d\n", buffer_info->invalid);
++}
++
++__attribute__((__unused__)) static void ingenic_mac_dump_dma_desc(DmaDesc *desc) {
++	printk("\tdma desc(%p):\n", desc);
++	printk("\t\tstatus = 0x%08x\n", desc->status);
++	printk("\t\tbuffer1 = 0x%08x\n", desc->buffer1);
++	printk("\t\tlength = %u\n", desc->length);
++}
++
++__attribute__((__unused__)) static void ingenic_mac_dump_dma_desc2(DmaDesc *desc, struct ingenic_mac_buffer *buffer_info) {
++	printk("desc: %p, status: 0x%08x buf1: 0x%08x dma: 0x%08x len: %u bi: %p skb: %p trans: %d inv: %d\n",
++			desc, desc->status, desc->buffer1, buffer_info->dma, desc->length,
++			buffer_info, buffer_info->skb, buffer_info->transfering, buffer_info->invalid);
++}
++
++__attribute__((__unused__)) static void ingenic_mac_dump_rx_desc(struct ingenic_mac_local *lp) {
++	int i = 0;
++	printk("\n===================rx====================\n");
++	printk("count = %d, next_to_use = %d next_to_clean = %d\n",
++			lp->rx_ring.count, lp->rx_ring.next_to_use, lp->rx_ring.next_to_clean);
++	for (i = 0; i < INGENIC_MAC_RX_DESC_COUNT; i++) {
++		DmaDesc *desc = lp->rx_ring.desc + i;
++		struct ingenic_mac_buffer *b = lp->rx_ring.buffer_info + i;
++
++#if 0
++		printk("desc %d:\n", i);
++		ingenic_mac_dump_dma_desc(desc);
++		ingenic_mac_dump_dma_buffer_info(b);
++#endif
++		ingenic_mac_dump_dma_desc2(desc, b);
++	}
++	printk("\n=========================================\n");
++}
++
++__attribute__((__unused__)) static void ingenic_mac_dump_tx_desc(struct ingenic_mac_local *lp) {
++	int i = 0;
++	printk("\n===================tx====================\n");
++	printk("count = %d, next_to_use = %d next_to_clean = %d\n",
++			lp->tx_ring.count, lp->tx_ring.next_to_use, lp->tx_ring.next_to_clean);
++	for (i = 0; i < INGENIC_MAC_TX_DESC_COUNT; i++) {
++		DmaDesc *desc = lp->tx_ring.desc + i;
++		struct ingenic_mac_buffer *b = lp->tx_ring.buffer_info + i;
++
++#if 0
++		printk("desc %d:\n", i);
++		ingenic_mac_dump_dma_desc(desc);
++		ingenic_mac_dump_dma_buffer_info(b);
++#endif
++		ingenic_mac_dump_dma_desc2(desc, b);
++	}
++	printk("\n=========================================\n");
++}
++
++__attribute__((__unused__)) static void ingenic_mac_dump_all_desc(struct ingenic_mac_local *lp) {
++	ingenic_mac_dump_rx_desc(lp);
++	ingenic_mac_dump_tx_desc(lp);
++}
++
++__attribute__((__unused__)) static int get_rx_index_by_desc(struct ingenic_mac_local *lp, DmaDesc *desc) {
++	int i = 0;
++
++	for (i = 0; i < INGENIC_MAC_RX_DESC_COUNT; i++) {
++		if ( (lp->rx_ring.desc + i) == desc)
++			return i;
++	}
++
++	BUG_ON(i == INGENIC_MAC_RX_DESC_COUNT);
++	return -1;
++}
++
++__attribute__((__unused__)) static void ingenic_mac_phy_dump(struct ingenic_mac_local *lp) {
++	u16 phy[] = {0, 1, 4, 5, 6, 9, 10, 15, 16, 17, 18, 20, 21, 24, 0x1c};
++
++	u16 data[sizeof(phy) / sizeof(u16)];
++	int i;
++
++	printk("\n-------->PHY dump: %08X\n", lp->phydev->phy_id);
++	for (i = 0; i < sizeof(phy) / sizeof(u16); i++)
++		data[i] = lp->mii_bus->read(lp->mii_bus, lp->phydev->mdio.addr, phy[i]);
++
++	for (i = 0; i < sizeof(phy) / sizeof(u16); i++)
++		printk("PHY reg%d, value %04X\n", phy[i], data[i]);
++}
++
++#ifdef CONFIG_INGENIC_GMAC_USE_HWSTAMP
++#define PTP_REF_FREQUENCY (50000000)
++#define PTP_CURRENT_FREQUENCY (75000000)
++#define ingenic_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE)
++static int ingenic_mac_hwtstamp_ioctl(struct net_device *netdev,
++		struct ifreq *ifr, int cmd)
++{
++	struct hwtstamp_config config;
++	struct timespec64 curr_t;
++	struct ingenic_mac_local *lp = netdev_priv(netdev);
++	synopGMACdevice *gmacdev = lp->gmacdev;
++
++	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
++		return -EFAULT;
++
++
++	/* reserved for future extensions */
++	if (config.flags)
++		return -EINVAL;
++
++	if ((config.tx_type != HWTSTAMP_TX_OFF) &&
++			(config.tx_type != HWTSTAMP_TX_ON))
++		return -ERANGE;
++
++	switch (config.rx_filter) {
++	case HWTSTAMP_FILTER_NONE:
++		/*
++		 * Dont allow any timestamping
++		 */
++		synopGMAC_TS_mac_addr_filt_enable(gmacdev);
++		synopGMAC_TS_all_frames_disable(gmacdev);
++		break;
++	case HWTSTAMP_FILTER_ALL:
++		/*
++		 * time stamp any incoming packet
++		 */
++		synopGMAC_TS_mac_addr_filt_disable(gmacdev);
++		synopGMAC_TS_all_frames_enable(gmacdev);
++		break;
++	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
++	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
++	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
++		synopGMAC_TS_pkt_snoop_ver1(gmacdev);
++		synopGMAC_TS_set_clk_type(gmacdev, GmacTSEtoEClk);
++		synopGMAC_TS_all_frames_disable(gmacdev);
++		config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
++		break;
++	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
++	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
++	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
++		synopGMAC_TS_IPV4_enable(gmacdev);
++		synopGMAC_TS_pkt_snoop_ver2(gmacdev);
++		synopGMAC_TS_set_clk_type(gmacdev, GmacTSBouClk);
++		synopGMAC_TS_all_frames_disable(gmacdev);
++//		synopGMAC_TS_ptp_over_ethernet_enable(gmacdev);
++		config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
++		break;
++	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
++	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
++	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
++		synopGMAC_TS_all_frames_enable(gmacdev);
++		config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
++		break;
++	default:
++		return -ERANGE;
++	}
++
++	if (config.tx_type == HWTSTAMP_TX_OFF &&
++		ingenic_mac_hwtstamp_is_none(config.rx_filter)) {
++		synopGMAC_TS_disable(lp->gmacdev);
++	} else {
++		synopGMAC_multicast_enable(gmacdev);
++		synopGMAC_TS_disable(lp->gmacdev);
++		synopGMAC_TS_digital_rollover_enable(lp->gmacdev);
++		synopGMAC_TS_subsecond_init(lp->gmacdev, (1000000000ULL)/PTP_REF_FREQUENCY);
++		synopGMAC_TS_addend_update(lp->gmacdev, lp->ptp_addend);
++		synopGMAC_TS_enable(lp->gmacdev);
++		ktime_get_coarse_real_ts64(&curr_t);
++		synopGMAC_TS_timestamp_init(lp->gmacdev, curr_t.tv_sec, curr_t.tv_nsec);
++	}
++
++	lp->stamp_cfg = config;
++	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
++		-EFAULT : 0;
++}
++
++void ingenic_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb, int index)
++{
++	struct ingenic_mac_local *lp = netdev_priv(netdev);
++	struct ingenic_mac_tx_ring *tx_ring = &lp->tx_ring;
++	DmaDesc *desc;
++
++	desc = INGENIC_MAC_TX_DESC(*tx_ring, index);
++
++	if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
++		int timeout_cnt = MAX_TIMEOUT_CNT;
++
++		/* When doing time stamping, keep the connection to the socket
++		 * a while longer
++		 */
++		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
++
++		/*
++		 * The timestamping is done at the EMAC module's MII/RMII interface
++		 * when the module sees the Start of Frame of an event message packet. This
++		 * interface is the closest possible place to the physical Ethernet transmission
++		 * medium, providing the best timing accuracy.
++		 */
++		while ((synopGMAC_is_desc_owned_by_dma(desc)) && (--timeout_cnt))
++			udelay(1);
++		if (timeout_cnt == 0)
++			netdev_err(netdev, "timestamp the TX packet failed\n");
++		else {
++			struct skb_shared_hwtstamps shhwtstamps;
++			u32 nsec, sec;
++			nsec = desc->timestamplow;
++			sec = desc->timestamphigh;
++			memset(&shhwtstamps, 0, sizeof(shhwtstamps));
++			shhwtstamps.hwtstamp = ktime_set(sec, nsec);
++			skb_tstamp_tx(skb, &shhwtstamps);
++		}
++	}
++}
++
++static void ingenic_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb, int index)
++{
++	struct ingenic_mac_local *lp = netdev_priv(netdev);
++	struct ingenic_mac_rx_ring *rx_ring = &lp->rx_ring;
++	struct skb_shared_hwtstamps *shhwtstamps;
++	DmaDesc *desc;
++	unsigned int nsec, sec;
++
++
++	if (ingenic_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter))
++		return;
++
++	desc = INGENIC_MAC_RX_DESC(*rx_ring, index);
++	if((desc->extstatus >> 8) & 0xf) {
++		shhwtstamps = skb_hwtstamps(skb);
++		nsec = desc->timestamplow;
++		sec = desc->timestamphigh;
++		memset(shhwtstamps, 0, sizeof(shhwtstamps));
++		shhwtstamps->hwtstamp = ktime_set(sec, nsec);
++	}
++}
++
++static int ingenic_mac_hwtstamp_init(struct net_device *netdev)
++{
++	struct ingenic_mac_local *lp = netdev_priv(netdev);
++	struct platform_device *pdev = lp->pdev;
++	u64 addend;
++	int err;
++
++	lp->cgu_ptp = devm_clk_get(&pdev->dev, "div_macptp");
++	if (IS_ERR(lp->cgu_ptp)) {
++		err = PTR_ERR(lp->cgu_ptp);
++		dev_err(&pdev->dev, "%s:can't get clk %s\n", __func__,"cgu_ptp");
++		return err;
++	}
++
++	if ((err = clk_prepare_enable(lp->cgu_ptp)) < 0) {
++		dev_err(&pdev->dev, "Enable gmac ptp clk failed\n");
++		return err;
++	}
++	if((err = clk_set_rate(lp->cgu_ptp, PTP_CURRENT_FREQUENCY)) < 0) {
++		dev_err(&pdev->dev, "Set cgu_ptp clk rate faild\n");
++		return err;
++	}
++
++	lp->ptp_freq = clk_get_rate(lp->cgu_ptp);
++	dev_info(&pdev->dev, "ptp clock frequency = %d\n", lp->ptp_freq);
++
++	addend = (1ULL << 32) * (PTP_REF_FREQUENCY);
++	lp->ptp_addend = div_u64(addend, lp->ptp_freq);
++
++
++	/* Initialize hwstamp config */
++	lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
++	lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
++
++	return 0;
++}
++
++/* PTP Hardware Clock operations */
++static int ingenic_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
++{
++	u64 adj, mult;
++	u64 addend;
++	u32 diff;
++	int neg_adj = 0;
++	unsigned long flags;
++	int ret = 0;
++	struct ingenic_mac_local *lp =
++		container_of(ptp, struct ingenic_mac_local, caps);
++
++	if (ppb < 0) {
++		neg_adj = 1;
++		ppb = -ppb;
++	}
++	mult = lp->ptp_addend;
++	adj = mult;
++	adj *= ppb;
++	diff = div_u64(adj, 1000000000ULL);
++	addend = neg_adj ? mult - diff : mult + diff;
++	if(addend > 0xffffffff) {
++		printk("gmac ptp addend out of range\n");
++		return 0;
++	}
++	spin_lock_irqsave(&lp->phc_lock, flags);
++	synopGMAC_TS_fine_update(lp->gmacdev);
++	ret = synopGMAC_TS_addend_update(lp->gmacdev, addend);
++	spin_unlock_irqrestore(&lp->phc_lock, flags);
++
++	return ret;
++}
++
++static int ingenic_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
++{
++	unsigned long flags;
++	struct ingenic_mac_local *lp =
++		container_of(ptp, struct ingenic_mac_local, caps);
++	u32 nsec, sec;
++	u16 hsec;
++
++	spin_lock_irqsave(&lp->phc_lock, flags);
++	synopGMAC_TS_read_timestamp(lp->gmacdev, &hsec, &sec, &nsec);
++	ts->tv_sec = sec;
++	ts->tv_nsec = nsec;
++	spin_unlock_irqrestore(&lp->phc_lock, flags);
++
++	return 0;
++}
++
++static int ingenic_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
++{
++	unsigned long flags;
++	unsigned long fine;
++	struct ingenic_mac_local *lp =
++		container_of(ptp, struct ingenic_mac_local, caps);
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	int ret;
++
++	struct timespec64 ts = ns_to_timespec64(delta);
++
++	spin_lock_irqsave(&lp->phc_lock, flags);
++	fine = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacTSControl) & GmacTSCFUPDT;
++	synopGMAC_TS_coarse_update(gmacdev);
++	if(ts.tv_sec < 0) {
++		ret = synopGMAC_TS_timestamp_update(gmacdev, ts.tv_sec*(-1), 0x80000000);
++		ret = synopGMAC_TS_timestamp_update(gmacdev, 0, ts.tv_nsec);
++	} else
++		ret = synopGMAC_TS_timestamp_update(gmacdev, ts.tv_sec, ts.tv_nsec);
++	if(fine)
++		synopGMAC_TS_fine_update(gmacdev);
++	spin_unlock_irqrestore(&lp->phc_lock, flags);
++
++	return ret;
++}
++
++
++static int ingenic_ptp_settime(struct ptp_clock_info *ptp,
++			   const struct timespec64 *ts)
++{
++	unsigned long flags;
++	u32 nsec = ts->tv_nsec;
++	u32 sec = (u32)ts->tv_sec;
++	int ret;
++	struct ingenic_mac_local *lp =
++		container_of(ptp, struct ingenic_mac_local, caps);
++
++	spin_lock_irqsave(&lp->phc_lock, flags);
++	ret = synopGMAC_TS_timestamp_init(lp->gmacdev, sec, nsec);
++	spin_unlock_irqrestore(&lp->phc_lock, flags);
++
++	return ret;
++}
++
++static int ingenic_ptp_enable(struct ptp_clock_info *ptp,
++			  struct ptp_clock_request *rq, int on)
++{
++	return -EOPNOTSUPP;
++}
++
++static struct ptp_clock_info ingenic_ptp_caps = {
++	.owner		= THIS_MODULE,
++	.name		= "ingenic ptp",
++	.max_adj	= 500000000,
++	.n_alarm	= 0,
++	.n_ext_ts	= 0,
++	.n_per_out	= 0,
++	.pps		= 0,
++	.adjfreq	= ingenic_ptp_adjfreq,
++	.adjtime	= ingenic_ptp_adjtime,
++	.gettime64	= ingenic_ptp_gettime,
++	.settime64	= ingenic_ptp_settime,
++	.enable		= ingenic_ptp_enable,
++};
++
++static int ingenic_phc_init(struct net_device *netdev, struct device *dev)
++{
++	struct ingenic_mac_local *lp = netdev_priv(netdev);
++	int ret;
++
++	lp->caps = ingenic_ptp_caps;
++	ret = ingenic_mac_hwtstamp_init(netdev);
++	if(ret)
++		return ret;
++
++	lp->clock = ptp_clock_register(&lp->caps, dev);
++	if (IS_ERR(lp->clock))
++		return PTR_ERR(lp->clock);
++
++	lp->phc_index = ptp_clock_index(lp->clock);
++	spin_lock_init(&lp->phc_lock);
++
++	return 0;
++}
++
++static void ingenic_phc_release(struct ingenic_mac_local *lp)
++{
++	struct platform_device *pdev = lp->pdev;
++	devm_clk_put(&pdev->dev, lp->cgu_ptp);
++	ptp_clock_unregister(lp->clock);
++}
++
++static int ingenic_mac_get_ts_info(struct net_device *netdev, struct ethtool_ts_info *info)
++{
++	struct ingenic_mac_local *lp = netdev_priv(netdev);
++
++	if(lp->clock) {
++		info->phc_index = ptp_clock_index(lp->clock);
++	} else {
++		info->phc_index = -1;
++	}
++
++	info->so_timestamping =
++			SOF_TIMESTAMPING_TX_HARDWARE |
++			SOF_TIMESTAMPING_RX_HARDWARE |
++			SOF_TIMESTAMPING_RAW_HARDWARE;
++
++	info->tx_types =
++		(1 << HWTSTAMP_TX_OFF) |
++		(1 << HWTSTAMP_TX_ON);
++
++	info->rx_filters =
++		(1 << HWTSTAMP_FILTER_NONE) |
++		(1 << HWTSTAMP_FILTER_ALL) |
++		(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
++		(1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
++		(1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
++
++
++	return 0;
++}
++
++#else
++# define ingenic_mac_hwtstamp_is_none(cfg) 0
++# define ingenic_mac_hwtstamp_init(ndev)
++# define ingenic_mac_hwtstamp_ioctl(netdev, ifr, cmd) (-EOPNOTSUPP)
++# define ingenic_rx_hwtstamp(netdev, skb, rx_desc_i)
++# define ingenic_tx_hwtstamp(netdev, skb, first)
++# define ingenic_phc_init(ndev, dev)
++# define ingenic_phc_release(lp)
++#endif
++
++#if 0
++static void ingenic_start_rx_coalesce_timer(struct ingenic_mac_local *lp)
++{
++	unsigned long ns = lp->rx_coalesce_usecs * NSEC_PER_USEC / 2;
++
++	/* allow timer to fire after half the time at the earliest */
++	hrtimer_start_range_ns(&lp->rx_coalesce_timer, ns_to_ktime(ns),
++			       ns, HRTIMER_MODE_PINNED);
++}
++
++enum hrtimer_restart ingenic_rx_coalesce_timer_done(struct hrtimer *hrtimer)
++{
++	struct ingenic_mac_local *lp;
++	synopGMACdevice *gmacdev;
++	u32 data;
++
++	lp = container_of(hrtimer, struct ingenic_mac_local, rx_coalesce_timer);
++	gmacdev = lp->gmacdev;
++
++	data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaStatus);
++	data &= DmaIntRxNormMask;
++	if(data && napi_schedule_prep(&lp->napi)) {
++		synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaStatus, data);
++		__napi_schedule(&lp->napi);
++	} else {
++		synopGMAC_enable_interrupt(gmacdev, DmaIntEnable);
++	}
++
++	return HRTIMER_NORESTART;
++}
++#endif
++
++static void ingenic_start_tx_coalesce_timer(struct ingenic_mac_local *lp)
++{
++	unsigned long ns = lp->tx_coalesce_usecs * NSEC_PER_USEC / 2;
++
++	/* allow timer to fire after half the time at the earliest */
++	hrtimer_start_range_ns(&lp->tx_coalesce_timer, ns_to_ktime(ns),
++			       ns, HRTIMER_MODE_REL);
++}
++
++enum hrtimer_restart ingenic_tx_coalesce_timer_done(struct hrtimer *hrtimer)
++{
++	struct ingenic_mac_tx_ring *tx_ring;
++	struct ingenic_mac_local *lp;
++	unsigned long ns;
++	int tx_num;
++
++	lp = container_of(hrtimer, struct ingenic_mac_local, tx_coalesce_timer);
++	ns = lp->tx_coalesce_usecs * NSEC_PER_USEC / 2;
++	tx_ring = &lp->tx_ring;
++
++	tx_num = ingenic_mac_clean_tx_irq(lp);
++
++	if(unlikely(INGENIC_MAC_DESC_UNUSED(tx_ring) < (tx_ring->count-1))) {
++		hrtimer_start_range_ns(&lp->tx_coalesce_timer, ns_to_ktime(ns),
++				       ns, HRTIMER_MODE_REL);
++	}
++	return HRTIMER_NORESTART;
++}
++
++static void ingenic_mac_restart_rx_dma(struct ingenic_mac_local *lp) {
++	synopGMAC_enable_dma_rx(lp->gmacdev);
++}
++
++static void ingenic_mac_alloc_rx_buffers(struct ingenic_mac_local *lp, int cleaned_count,
++		int restart_dma) {
++	int i = 0;
++	struct ingenic_mac_buffer *buffer_info;
++	struct sk_buff *skb;
++	struct ingenic_mac_rx_ring *rx_ring = &lp->rx_ring;
++	DmaDesc *rx_desc;
++
++	i = rx_ring->next_to_use;
++	rx_desc = INGENIC_MAC_RX_DESC(*rx_ring, i);
++	buffer_info = &rx_ring->buffer_info[i];
++
++	while (cleaned_count--) {
++		skb = buffer_info->skb;
++		if (skb) {
++			skb_trim(skb, 0);
++			goto map_skb;
++		}
++
++		if(lp->id == 0)
++			skb = napi_alloc_skb(&lp->napi, lp->netdev->mtu + ETHERNET_HEADER + ETHERNET_CRC);
++		else
++			skb = netdev_alloc_skb_ip_align(lp->netdev, lp->netdev->mtu + ETHERNET_HEADER + ETHERNET_CRC);
++		if (unlikely(!skb)) {
++			/* Better luck next round */
++			lp->alloc_rx_buff_failed++;
++			break;
++		}
++
++		buffer_info->skb = skb;
++		buffer_info->length = skb_tailroom(skb);
++map_skb:
++		buffer_info->dma = dma_map_single(&lp->netdev->dev,
++				skb->data, skb_tailroom(skb),
++				DMA_FROM_DEVICE);
++		if (dma_mapping_error(&lp->netdev->dev, buffer_info->dma)) {
++			dev_err(&lp->netdev->dev, "Rx DMA map failed\n");
++			lp->alloc_rx_buff_failed++;
++			break;
++		}
++
++		rx_desc->length |= ((skb_tailroom(skb) <<DescSize1Shift) & DescSize1Mask) |
++			((0 << DescSize2Shift) & DescSize2Mask);
++		rx_desc->buffer1 = cpu_to_le32(buffer_info->dma);
++
++		/* clr invalid first, then start transfer */
++		buffer_info->invalid = 0;
++
++		/* start transfer */
++		rx_desc->status = DescOwnByDma | DescRxEXTsts;
++
++		/* next */
++		if (unlikely(++i == rx_ring->count))
++			i = 0;
++
++		wmb();
++
++		rx_desc = INGENIC_MAC_RX_DESC(*rx_ring, i);
++		buffer_info = &rx_ring->buffer_info[i];
++	}
++
++	if (likely(rx_ring->next_to_use != i)) {
++		rx_ring->next_to_use = i;
++		/* sanity check: ensure next_to_use is not used */
++		rx_desc->status &= ~DescOwnByDma;
++		buffer_info->invalid = 1;
++		wmb();
++
++		/* assure that if there's any buffer space, dma is enabled */
++		if (likely(restart_dma))
++			ingenic_mac_restart_rx_dma(lp);
++	}
++}
++
++static int desc_list_init_rx(struct ingenic_mac_local *lp) {
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	int i;
++	int size;
++
++	/* rx init */
++	lp->rx_ring.count = INGENIC_MAC_RX_DESC_COUNT;
++
++	size = lp->rx_ring.count * sizeof(struct ingenic_mac_buffer);
++	lp->rx_ring.buffer_info = vmalloc(size);
++	if (!lp->rx_ring.buffer_info) {
++		printk(KERN_ERR "Unable to allocate memory for the receive descriptor ring\n");
++		return -ENOMEM;
++	}
++	memset(lp->rx_ring.buffer_info, 0, size);
++
++	lp->rx_ring.desc = dma_alloc_noncoherent(&lp->netdev->dev,
++			lp->rx_ring.count * sizeof(DmaDesc),
++			&lp->rx_ring.dma, DMA_BIDIRECTIONAL, GFP_KERNEL);
++
++	if (lp->rx_ring.desc == NULL) {
++		vfree(lp->rx_ring.buffer_info);
++		lp->rx_ring.buffer_info = NULL;
++		return -ENOMEM;
++	}
++
++	dma_cache_wback_inv((unsigned long)lp->rx_ring.desc,
++			lp->rx_ring.count * sizeof(DmaDesc));
++
++	/* we always use uncached address for descriptors */
++	lp->rx_ring.desc = (DmaDesc *)CKSEG1ADDR(lp->rx_ring.desc);
++
++	for (i = 0; i < INGENIC_MAC_RX_DESC_COUNT; i++) {
++		DmaDesc *desc = lp->rx_ring.desc + i;
++
++		synopGMAC_rx_desc_init_ring(desc, i == (INGENIC_MAC_RX_DESC_COUNT - 1));
++	}
++
++	lp->rx_ring.next_to_use = lp->rx_ring.next_to_clean = 0;
++	ingenic_mac_alloc_rx_buffers(lp, INGENIC_MAC_DESC_UNUSED(&lp->rx_ring), 0);
++
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase,DmaRxBaseAddr, lp->rx_ring.dma);
++
++	return 0;
++}
++
++static void desc_list_free_rx(struct ingenic_mac_local *lp) {
++	struct ingenic_mac_buffer *b;
++	int i = 0;
++
++	if (lp->rx_ring.desc)
++		dma_free_noncoherent(&lp->netdev->dev,
++				lp->rx_ring.count * sizeof(DmaDesc),
++				(void *)CKSEG0ADDR(lp->rx_ring.desc),
++				lp->rx_ring.dma, DMA_BIDIRECTIONAL);
++
++	if (lp->rx_ring.buffer_info) {
++		b = lp->rx_ring.buffer_info;
++
++		for(i = 0; i < INGENIC_MAC_RX_DESC_COUNT; i++) {
++			if (b[i].skb) {
++				if (b[i].dma) {
++					dma_unmap_single(&lp->netdev->dev, b[i].dma,
++							b[i].length, DMA_FROM_DEVICE);
++					b[i].dma = 0;
++				}
++
++				dev_kfree_skb_any(b[i].skb);
++				b[i].skb = NULL;
++				b[i].time_stamp = 0;
++			}
++		}
++	}
++	vfree(lp->rx_ring.buffer_info);
++	lp->rx_ring.buffer_info = NULL;
++	lp->rx_ring.next_to_use = lp->rx_ring.next_to_clean = 0;
++}
++
++/* must be called from interrupt handler */
++static void ingenic_mac_take_desc_ownership_rx(struct ingenic_mac_local *lp) {
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	int i = 0;
++
++	/* must called with interrupts disabled */
++	BUG_ON(synopGMAC_get_interrupt_mask(gmacdev));
++
++	for (i = 0; i < INGENIC_MAC_RX_DESC_COUNT; i++) {
++		DmaDesc *desc = lp->rx_ring.desc + i;
++		struct ingenic_mac_buffer *b = lp->rx_ring.buffer_info + i;
++
++		if (!b->invalid) {
++			synopGMAC_take_desc_ownership(desc);
++		}
++	}
++
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase,DmaRxBaseAddr, lp->rx_ring.dma);
++}
++
++/* MUST ensure that rx is stopped ans rx_dma is disabled */
++static void desc_list_reinit_rx(struct ingenic_mac_local *lp) {
++	DmaDesc *desc;
++	int i = 0;
++
++	//TODO: BUG_ON(!ingenic_mac_rx_dma_stopped());
++
++	for (i = 0; i < INGENIC_MAC_RX_DESC_COUNT; i++) {
++		desc = lp->rx_ring.desc + i;
++
++		/* owned by DMA, can fill data */
++		synopGMAC_rx_desc_init_ring(desc, i == (INGENIC_MAC_RX_DESC_COUNT - 1));
++	}
++
++	lp->rx_ring.next_to_use = lp->rx_ring.next_to_clean = 0;
++	ingenic_mac_alloc_rx_buffers(lp, INGENIC_MAC_DESC_UNUSED(&lp->rx_ring), 0);
++
++	synopGMACWriteReg((u32 *)lp->gmacdev->DmaBase,DmaRxBaseAddr, lp->rx_ring.dma);
++}
++
++static int desc_list_init_tx(struct ingenic_mac_local *lp) {
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	int i;
++	int size;
++
++	/* tx init */
++	lp->tx_ring.count = INGENIC_MAC_TX_DESC_COUNT;
++
++	size = lp->tx_ring.count * sizeof(struct ingenic_mac_buffer);
++	lp->tx_ring.buffer_info = vmalloc(size);
++	if (!lp->tx_ring.buffer_info) {
++		printk(KERN_ERR"Unable to allocate memory for the receive descriptor ring\n");
++		return -ENOMEM;
++	}
++	memset(lp->tx_ring.buffer_info, 0, size);
++
++	lp->tx_ring.desc = dma_alloc_noncoherent(&lp->netdev->dev,
++			lp->tx_ring.count * sizeof(DmaDesc),
++			&lp->tx_ring.dma, DMA_BIDIRECTIONAL, GFP_KERNEL);
++
++	if (lp->tx_ring.desc == NULL) {
++		vfree(lp->tx_ring.buffer_info);
++		lp->tx_ring.buffer_info = NULL;
++		return -ENOMEM;
++	}
++
++	dma_cache_wback_inv((unsigned long)lp->tx_ring.desc,
++			lp->tx_ring.count * sizeof(DmaDesc));
++
++	/* we always use uncached address for descriptors */
++	lp->tx_ring.desc = (DmaDesc *)CKSEG1ADDR(lp->tx_ring.desc);
++
++	for (i = 0; i < INGENIC_MAC_TX_DESC_COUNT; i++) {
++		DmaDesc *desc = lp->tx_ring.desc + i;
++
++		synopGMAC_tx_desc_init_ring(desc, i == (INGENIC_MAC_TX_DESC_COUNT - 1));
++	}
++
++	lp->tx_ring.next_to_use = lp->tx_ring.next_to_clean = 0;
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase,DmaTxBaseAddr,(u32)lp->tx_ring.dma);
++	return 0;
++}
++
++__attribute__((__unused__)) static int get_tx_index_by_desc(struct ingenic_mac_local *lp, DmaDesc *desc) {
++	int i = 0;
++
++	for (i = 0; i < INGENIC_MAC_TX_DESC_COUNT; i++) {
++		if ( (lp->tx_ring.desc + i) == desc)
++			return i;
++	}
++
++	BUG_ON(i == INGENIC_MAC_TX_DESC_COUNT);
++	return -1;
++}
++
++static void ingenic_mac_unmap_and_free_tx_resource(struct ingenic_mac_local *lp,
++		struct ingenic_mac_buffer *buffer_info)
++{
++	buffer_info->transfering = 0;
++
++	if (buffer_info->skb) {
++		if (buffer_info->dma) {
++			if (buffer_info->mapped_as_page)
++				dma_unmap_page(&lp->netdev->dev, buffer_info->dma,
++						buffer_info->length, DMA_TO_DEVICE);
++			else
++				dma_unmap_single(&lp->netdev->dev, buffer_info->dma,
++						buffer_info->length, DMA_TO_DEVICE);
++			buffer_info->dma = 0;
++		}
++		dev_kfree_skb_any(buffer_info->skb);
++		buffer_info->skb = NULL;
++	}
++	buffer_info->time_stamp = 0;
++}
++
++static void desc_list_free_tx(struct ingenic_mac_local *lp) {
++	struct ingenic_mac_buffer *b;
++	int i = 0;
++
++	if (lp->tx_ring.desc)
++		dma_free_noncoherent(&lp->netdev->dev,
++				lp->tx_ring.count * sizeof(DmaDesc),
++				(void *)CKSEG0ADDR(lp->tx_ring.desc),
++				lp->tx_ring.dma, DMA_BIDIRECTIONAL);
++
++	if (lp->tx_ring.buffer_info) {
++		b = lp->tx_ring.buffer_info;
++
++		for (i = 0; i < INGENIC_MAC_TX_DESC_COUNT; i++) {
++			// panic("===>ahha, testing! please do not goes here(%s:%d)!!!\n", __func__, __LINE__);
++			ingenic_mac_unmap_and_free_tx_resource(lp, b + i);
++		}
++
++	}
++	vfree(lp->tx_ring.buffer_info);
++	lp->tx_ring.buffer_info = NULL;
++	lp->tx_ring.next_to_use = lp->tx_ring.next_to_clean = 0;
++}
++
++/* must called in interrupt handler */
++static void ingenic_mac_take_desc_ownership_tx(struct ingenic_mac_local *lp) {
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	int i = 0;
++
++	/* must called with interrupts disabled */
++	BUG_ON(synopGMAC_get_interrupt_mask(gmacdev));
++
++	for (i = 0; i < INGENIC_MAC_TX_DESC_COUNT; i++) {
++		DmaDesc *desc = lp->tx_ring.desc + i;
++		struct ingenic_mac_buffer *b = lp->tx_ring.buffer_info + i;
++
++		if (!b->invalid) {
++			synopGMAC_take_desc_ownership(desc);
++		}
++	}
++}
++
++/* must assure that tx transfer are stopped and tx_dma is disabled */
++static void desc_list_reinit_tx(struct ingenic_mac_local *lp) {
++	int i = 0;
++	DmaDesc *desc;
++	struct ingenic_mac_buffer *b;
++
++	//TODO: BUG_ON(!ingenic_mac_tx_dma_stopped());
++
++	for (i = 0; i < INGENIC_MAC_TX_DESC_COUNT; i++) {
++		desc = lp->tx_ring.desc + i;
++		b = lp->tx_ring.buffer_info + i;
++
++		/* owned by CPU, no valid data */
++		synopGMAC_tx_desc_init_ring(desc, i == (INGENIC_MAC_TX_DESC_COUNT - 1));
++
++		ingenic_mac_unmap_and_free_tx_resource(lp, b);
++	}
++
++	lp->tx_ring.next_to_use = lp->tx_ring.next_to_clean = 0;
++}
++
++static void desc_list_free(struct ingenic_mac_local *lp)
++{
++	desc_list_free_rx(lp);
++	desc_list_free_tx(lp);
++}
++
++static void desc_list_reinit(struct ingenic_mac_local *lp) {
++	desc_list_reinit_rx(lp);
++	desc_list_reinit_tx(lp);
++}
++
++static int desc_list_init(struct ingenic_mac_local *lp)
++{
++	if (desc_list_init_rx(lp) < 0)
++		goto init_error;
++
++	if (desc_list_init_tx(lp) < 0)
++		goto init_error;
++
++	return 0;
++
++init_error:
++	desc_list_free(lp);
++	printk(KERN_ERR INGENIC_MAC_DRV_NAME ": kmalloc failed\n");
++	return -ENOMEM;
++}
++
++static int ingenic_gmac_clk_set_rate(struct ingenic_mac_local *lp, unsigned int rate)
++{
++	struct clk *clk = lp->clk_tx;
++	struct clk *parent = NULL;
++	unsigned int prate = 0;
++
++
++	if(rate <= 2500000) {
++		/*set parent to EPLL*/
++		parent = clk_get(NULL, "epll");
++		prate = clk_get_rate(parent);
++
++		if((prate % rate) || ((prate / rate) > 256)) {
++			if(netif_msg_link(lp)){
++				printk("WARNING, can not set rate:%d epll rate is:%d\n", rate, prate);
++				printk("set macphy parent rate epll 300M \n");
++			}
++			clk_set_rate(parent, 300000000);
++		}
++
++		clk_set_parent(clk_get_parent(clk), parent);
++		clk_set_rate(clk, rate);
++	} else {
++		parent = clk_get_parent(clk);
++		prate = clk_get_rate(parent);
++
++		if((prate % rate) || ((prate / rate) > 256)) {
++			if(netif_msg_link(lp)){
++				printk("WARNING, can not set rate:%d parent rate is:%d\n", rate, prate);
++				printk("set macphy parent is mpll\n");
++			}
++			parent = clk_get(NULL, "mpll");
++			prate = clk_get_rate(parent);
++			clk_set_parent(clk_get_parent(clk), parent);
++			if((prate % rate) || ((prate / rate) > 256)) {
++				printk("### ERROR, %s %s %d\n", __FILE__, __func__, __LINE__);
++				printk("### ERROR, mpll rate is:%d can not set rate:%d\n", prate, rate);
++				printk("### ERROR, please check out mpll, then set an appropriate value\n");
++			}
++		}
++
++		clk_set_rate(clk, rate);
++	}
++
++	return 0;
++}
++
++static void ingenic_mac_set_rx_flowcontrol(struct ingenic_mac_local *lp, bool enable)
++{
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	unsigned long flags;
++
++	spin_lock_irqsave(&lp->hw_lock, flags);
++
++	if (enable){
++		synopGMAC_rx_flow_control_enable(gmacdev);
++	}else{
++		synopGMAC_rx_flow_control_disable(gmacdev);
++	}
++	spin_unlock_irqrestore(&lp->hw_lock, flags);
++}
++
++static void ingenic_mac_set_tx_flowcontrol(struct ingenic_mac_local *lp, bool enable)
++{
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	unsigned long flags;
++
++	spin_lock_irqsave(&lp->hw_lock, flags);
++
++	if (enable){
++		synopGMAC_tx_flow_control_enable(gmacdev);
++	}else{
++		synopGMAC_tx_flow_control_disable(gmacdev);
++	}
++	spin_unlock_irqrestore(&lp->hw_lock, flags);
++}
++
++/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
++static void ingenic_mac_adjust_link(struct net_device *dev)
++{
++	struct ingenic_mac_local *lp = netdev_priv(dev);
++	struct phy_device *phydev = lp->phydev;
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	unsigned long flags;
++	int new_state = 0;
++
++	if (netif_msg_link(lp)){
++		printk("===>ajust link, new_duplex = %d, new_speed = %d, new_link = %d phydev->link = %d phydev->state = %d\n",\
++				lp->old_duplex, lp->old_speed, lp->old_link, phydev->link, phydev->state);
++	}
++
++	spin_lock_irqsave(&lp->link_lock, flags);
++
++	if (phydev->link) {
++		/* Now we make sure that we can be in full duplex mode.
++		 * If not, we operate in half-duplex mode. */
++		if (phydev->duplex != lp->old_duplex) {
++			new_state = 1;
++			lp->old_duplex = phydev->duplex;
++		}
++
++		if (phydev->speed != lp->old_speed) {
++			new_state = 1;
++			lp->old_speed = phydev->speed;
++		}
++
++		if (phydev->duplex) {
++			synopGMAC_set_full_duplex(gmacdev);
++			//synopGMAC_rx_own_enable(gmacdev);
++			//synopGMAC_set_Inter_Frame_Gap(gmacdev, GmacInterFrameGap7);
++		} else {
++			synopGMAC_set_half_duplex(gmacdev);
++			//synopGMAC_rx_own_disable(gmacdev);
++			//synopGMAC_set_Inter_Frame_Gap(gmacdev, GmacInterFrameGap4);
++		}
++
++		switch (phydev->speed) {
++			case 1000:
++				synopGMAC_select_speed1000(gmacdev);
++				if(lp->interface == RGMII)
++					ingenic_gmac_clk_set_rate(lp, 125000000);
++				break;
++			case 100:
++				synopGMAC_select_speed100(gmacdev);
++				if(lp->interface == RGMII)
++					ingenic_gmac_clk_set_rate(lp, 25000000);
++				break;
++			case 10:
++				synopGMAC_select_speed10(gmacdev);
++				if(lp->interface == RGMII)
++					ingenic_gmac_clk_set_rate(lp, 2500000);
++				break;
++			default:
++				printk(KERN_ERR "GMAC PHY speed NOT match!\n");
++				synopGMAC_select_speed100(gmacdev);
++		}
++
++		if (lp->flowcontrol.autoneg) {
++			lp->flowcontrol.rx = phydev->pause ||
++				phydev->asym_pause;
++			lp->flowcontrol.tx = phydev->pause ||
++				phydev->asym_pause;
++		}
++
++		if(lp->flowcontrol.rx || lp->flowcontrol.tx){
++			phydev->pause = 1;
++		}else{
++			phydev->pause = 0;
++		}
++
++		if (lp->flowcontrol.rx != lp->flowcontrol.rx_current) {
++			if (netif_msg_link(lp))
++				printk("set rx flow to %d\n",lp->flowcontrol.rx);
++			ingenic_mac_set_rx_flowcontrol(lp, lp->flowcontrol.rx);
++			lp->flowcontrol.rx_current = lp->flowcontrol.rx;
++		}
++		if (lp->flowcontrol.tx != lp->flowcontrol.tx_current) {
++			if (netif_msg_link(lp))
++				printk("set tx flow to %d\n",lp->flowcontrol.tx);
++			ingenic_mac_set_tx_flowcontrol(lp, lp->flowcontrol.tx);
++			lp->flowcontrol.tx_current = lp->flowcontrol.tx;
++		}
++
++
++		if (!lp->old_link) {
++			new_state = 1;
++			lp->old_link = 1;
++			netif_carrier_on(dev);
++		}
++	} else if (lp->old_link) {
++		new_state = 1;
++		lp->old_link = 0;
++		lp->old_speed = 0;
++		lp->old_duplex = -1;
++		netif_carrier_off(dev);
++	}
++
++	if (new_state)
++		phy_print_status(phydev);
++
++	if (netif_msg_link(lp)){
++		printk("===>ajust link, new_duplex = %d, new_speed = %d, new_link = %d phydev->link = %d phydev->state = %d\n",\
++				lp->old_duplex, lp->old_speed, lp->old_link, phydev->link, phydev->state);
++	}
++
++	spin_unlock_irqrestore(&lp->link_lock, flags);
++
++}
++
++/*half speed features*/
++static const int half_speed_features_array[] = {
++
++	ETHTOOL_LINK_MODE_10baseT_Half_BIT,
++	ETHTOOL_LINK_MODE_100baseT_Half_BIT,
++	ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
++};
++/*full speed features*/
++static const int full_speed_features_array[] = {
++
++	ETHTOOL_LINK_MODE_10baseT_Full_BIT,
++	ETHTOOL_LINK_MODE_100baseT_Full_BIT,
++	ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
++};
++/*autoneg features*/
++static const int autoneg_features_array[] = {
++
++	ETHTOOL_LINK_MODE_Autoneg_BIT,
++};
++/*pause features*/
++static const int pause_features_array[] = {
++
++	ETHTOOL_LINK_MODE_Pause_BIT,
++	ETHTOOL_LINK_MODE_Asym_Pause_BIT,
++};
++/*physics interface features*/
++static const int physics_interface_features_array[] = {
++
++	ETHTOOL_LINK_MODE_TP_BIT,
++	//ETHTOOL_LINK_MODE_AUI_BIT,
++	ETHTOOL_LINK_MODE_MII_BIT,
++	//ETHTOOL_LINK_MODE_FIBRE_BIT,
++	//ETHTOOL_LINK_MODE_BNC_BIT,
++};
++
++__ETHTOOL_DECLARE_LINK_MODE_MASK(local_supported) __ro_after_init;
++__ETHTOOL_DECLARE_LINK_MODE_MASK(local_advertising) __ro_after_init;
++
++static inline void linkmode_clear_bit_array(const int *array, int array_size, unsigned long *addr)
++{
++	int i;
++	for (i = 0; i < array_size; i++)
++		linkmode_clear_bit(array[i], addr);
++}
++
++static int mii_probe(struct net_device *dev)
++{
++	struct ingenic_mac_local *lp = netdev_priv(dev);
++	struct phy_device *phydev = NULL;
++	int phy_interface;
++
++ 	phydev = phy_find_first(lp->mii_bus);
++	if (!phydev) {
++		printk(KERN_ERR "%s: no PHY found\n", dev->name);
++		return -ENXIO;
++	}
++
++	if(lp->interface == RMII)
++		phy_interface = PHY_INTERFACE_MODE_RMII;
++	else if(lp->interface == RGMII)
++		phy_interface = PHY_INTERFACE_MODE_RGMII;
++	else if(lp->interface == GMII)
++		phy_interface = PHY_INTERFACE_MODE_GMII;
++	else
++		phy_interface = PHY_INTERFACE_MODE_MII;
++
++	phydev = phy_connect(dev, dev_name(&phydev->mdio.dev), &ingenic_mac_adjust_link,
++			phy_interface);
++	if (IS_ERR(phydev)) {
++		printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
++		return PTR_ERR(phydev);
++	}
++
++
++	/* Add features not supported by driver*/
++	linkmode_zero(local_supported);
++	linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, local_supported);
++	linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, local_supported);
++	linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, local_supported);
++	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, local_supported);
++	linkmode_or(phydev->supported, phydev->supported, local_supported);
++
++	/* Mask with MAC supported features */
++	linkmode_zero(local_supported);
++	linkmode_set_bit_array(half_speed_features_array, ARRAY_SIZE(half_speed_features_array), local_supported);
++	linkmode_set_bit_array(full_speed_features_array, ARRAY_SIZE(full_speed_features_array), local_supported);
++	linkmode_set_bit_array(autoneg_features_array, ARRAY_SIZE(autoneg_features_array), local_supported);
++	linkmode_set_bit_array(pause_features_array, ARRAY_SIZE(pause_features_array), local_supported);
++	linkmode_set_bit_array(physics_interface_features_array, ARRAY_SIZE(physics_interface_features_array), local_supported);
++	linkmode_and(phydev->supported, phydev->supported, local_supported);
++
++	/* Configure the advertising feature according to the supported feature*/
++	linkmode_copy(phydev->advertising, phydev->supported);
++
++	/* Remove any features not supported by the controller */
++	phy_set_max_speed(phydev, SPEED_1000);
++	phy_support_asym_pause(phydev);
++
++	phy_attached_info(phydev);
++
++	/*setting dts force gmac configure*/
++	if(lp->dts_ctl.force){
++
++		/*1.dts autoneg configuration*/
++		if(lp->dts_ctl.autoneg == 0){  //autoneg off
++
++			phydev->autoneg = AUTONEG_DISABLE;
++			linkmode_clear_bit_array(half_speed_features_array, ARRAY_SIZE(half_speed_features_array), phydev->advertising);
++			linkmode_clear_bit_array(full_speed_features_array, ARRAY_SIZE(full_speed_features_array), phydev->advertising);
++			linkmode_clear_bit_array(autoneg_features_array, ARRAY_SIZE(autoneg_features_array), phydev->advertising);
++
++		}else if(lp->dts_ctl.autoneg == 1){ //autoneg on
++
++			phydev->autoneg = AUTONEG_ENABLE;
++			linkmode_clear_bit_array(half_speed_features_array, ARRAY_SIZE(half_speed_features_array), phydev->advertising);
++			linkmode_clear_bit_array(full_speed_features_array, ARRAY_SIZE(full_speed_features_array), phydev->advertising);
++		}
++
++		/*2.dts duplex and speed configuration*/
++		phydev->speed = lp->dts_ctl.speed;
++		if(lp->dts_ctl.duplex == 1){
++
++			phydev->duplex = DUPLEX_FULL;
++			switch (phydev->speed) {
++				case 1000:
++					linkmode_set_bit(SUPPORTED_1000baseT_Full, phydev->advertising);
++					break;
++				case 100:
++					linkmode_set_bit(SUPPORTED_100baseT_Full, phydev->advertising);
++					break;
++				case 10:
++					linkmode_set_bit(SUPPORTED_10baseT_Full, phydev->advertising);
++					break;
++				default:
++					break;
++			}
++
++		}else if(lp->dts_ctl.duplex == 2){
++
++			phydev->duplex = DUPLEX_HALF;
++			switch (phydev->speed) {
++				case 1000:
++					linkmode_set_bit(SUPPORTED_1000baseT_Full, phydev->advertising);
++					break;
++				case 100:
++					linkmode_set_bit(SUPPORTED_100baseT_Full, phydev->advertising);
++					break;
++				case 10:
++					linkmode_set_bit(SUPPORTED_10baseT_Full, phydev->advertising);
++					break;
++				default:
++					break;
++			}
++		}
++	}
++
++	lp->old_link = 0;
++	lp->old_speed = 0;
++	lp->old_duplex = -1;
++	lp->phydev = phydev;
++
++	//ingenic_mac_phy_dump(lp);
++
++	return 0;
++}
++
++/**
++ * ingenic_mac_update_stats - Update the board statistics counters
++ * @lp: board private structure
++ **/
++
++void ingenic_mac_update_stats(struct ingenic_mac_local *lp)
++{
++	if ((lp->old_link == 0) || (lp->old_speed == 0) || (lp->old_duplex == -1))
++		return;
++
++#if 0
++	//spin_lock_irqsave(&lp->stats_lock, flags);
++	//spin_lock(&lp->stats_lock);
++
++	/* Fill out the OS statistics structure */
++	lp->net_stats.multicast = REG32(MAC_STAT_RMCA);
++	lp->net_stats.collisions = REG32(MAC_STAT_RBCA);
++
++	/* Rx Errors */
++
++	/* RLEC on some newer hardware can be incorrect so build
++	 * our own version based on RUC and ROC */
++	lp->net_stats.rx_errors = lp->stats.rxerrc +
++		lp->stats.crcerrs + lp->stats.algnerrc +
++		lp->stats.ruc + lp->stats.roc +
++		lp->stats.cexterr;
++	lp->net_stats.rx_length_errors = REG32(MAC_STAT_RFLR);
++	lp->net_stats.rx_crc_errors = REG32(MAC_STAT_RFCS);
++	lp->net_stats.rx_frame_errors = REG32(MAC_STAT_RALN);
++	lp->net_stats.rx_missed_errors = lp->stats.mpc;
++
++	/* Tx Errors */
++	lp->stats.txerrc = lp->stats.ecol + lp->stats.latecol;
++	lp->net_stats.tx_errors = lp->stats.txerrc;
++	lp->net_stats.tx_aborted_errors = lp->stats.ecol;
++	lp->net_stats.tx_window_errors = lp->stats.latecol;
++	lp->net_stats.tx_carrier_errors = lp->stats.tncrs;
++	if (hw->bad_tx_carr_stats_fd &&
++		lp->link_duplex == FULL_DUPLEX) {
++		lp->net_stats.tx_carrier_errors = 0;
++		lp->stats.tncrs = 0;
++	}
++
++	/* Tx Dropped needs to be maintained elsewhere */
++
++	/* Phy Stats */
++	if (hw->media_type == e1000_media_type_copper) {
++		if ((lp->link_speed == SPEED_1000) &&
++			(!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
++			phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
++			lp->phy_stats.idle_errors += phy_tmp;
++		}
++
++		if ((hw->mac_type <= e1000_82546) &&
++			(hw->phy_type == e1000_phy_m88) &&
++			!e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
++			lp->phy_stats.receive_errors += phy_tmp;
++	}
++
++	/* Management Stats */
++	if (hw->has_smbus) {
++		lp->stats.mgptc += er32(MGTPTC);
++		lp->stats.mgprc += er32(MGTPRC);
++		lp->stats.mgpdc += er32(MGTPDC);
++	}
++
++	//spin_unlock_irqrestore(&lp->stats_lock, flags);
++	//spin_unlock(&lp->stats_lock);
++#endif
++}
++
++/**
++ * ingenic_mac_watchdog - Timer Call-back
++ * @data: pointer to lp cast into an unsigned long
++ **/
++static void ingenic_mac_watchdog(struct timer_list *t) {
++	struct ingenic_mac_local *lp = from_timer(lp, t, watchdog_timer);
++
++	ingenic_mac_update_stats(lp);
++
++	mod_timer(&lp->watchdog_timer, round_jiffies(jiffies + 5 * HZ));
++}
++
++static int __ingenic_mac_maybe_stop_tx(struct net_device *netdev, int size)
++{
++	struct ingenic_mac_local *lp = netdev_priv(netdev);
++	struct ingenic_mac_tx_ring *tx_ring = &lp->tx_ring;
++
++	netif_stop_queue(netdev);
++	smp_mb();
++
++	/* We need to check again in a case another CPU has just
++	 * made room available. */
++	if (likely(INGENIC_MAC_DESC_UNUSED(tx_ring) < size))
++		return -EBUSY;
++
++	/* A reprieve! */
++	netif_start_queue(netdev);
++	++lp->restart_queue;
++	return 0;
++}
++
++static int ingenic_mac_maybe_stop_tx(struct net_device *netdev,
++		struct ingenic_mac_tx_ring *tx_ring, int size)
++{
++	if (likely(INGENIC_MAC_DESC_UNUSED(tx_ring) >= size))
++		return 0;
++	return __ingenic_mac_maybe_stop_tx(netdev, size);
++}
++
++static int ingenic_mac_tx_map(struct ingenic_mac_local *lp,
++		struct ingenic_mac_tx_ring *tx_ring,
++		struct sk_buff *skb)
++{
++	struct net_device *pdev = lp->netdev;
++	struct ingenic_mac_buffer *buffer_info;
++	unsigned int len = skb_headlen(skb);
++	unsigned int offset = 0, count = 0, i;
++	unsigned int f, segs;
++	unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
++
++	i = tx_ring->next_to_use;
++
++	buffer_info = &tx_ring->buffer_info[i];
++	buffer_info->length = len;
++	buffer_info->time_stamp = jiffies;
++	buffer_info->dma = dma_map_single(&pdev->dev,
++			skb->data + offset,
++			len, DMA_TO_DEVICE);
++	buffer_info->mapped_as_page = false;
++	if (dma_mapping_error(&pdev->dev, buffer_info->dma))
++		goto dma_error;
++	segs = skb_shinfo(skb)->gso_segs ? : 1;
++	tx_ring->buffer_info[i].skb = skb;
++	tx_ring->buffer_info[i].segs = segs;
++	count++;
++
++	for (f = 0; f < nr_frags; f++) {
++		const skb_frag_t *frag;
++
++//		struct page *p;
++		frag = &skb_shinfo(skb)->frags[f];
++		len = frag->bv_len;
++		offset = frag->bv_offset;
++		i++;
++		if (i == tx_ring->count)
++			i = 0;
++		buffer_info = &tx_ring->buffer_info[i];
++		buffer_info->length = len;
++		buffer_info->time_stamp = jiffies;
++		buffer_info->dma = dma_map_page(&pdev->dev, (struct page *)frag, offset, len, DMA_TO_DEVICE);
++
++		buffer_info->mapped_as_page = true;
++		if (dma_mapping_error(&pdev->dev, buffer_info->dma))
++			goto dma_unwind;
++		segs = skb_shinfo(skb)->gso_segs ? : 1;
++		tx_ring->buffer_info[i].skb = skb;
++		tx_ring->buffer_info[i].segs = segs;
++		tx_ring->buffer_info[i].transfering = 1;
++
++		count++;
++	}
++
++
++	return count;
++dma_unwind:
++	dev_err(&pdev->dev, "Tx DMA map failed at dma_unwind\n");
++	while(count-- > 0) {
++		i--;
++		if (i == 0) {
++			i = tx_ring->count;
++		}
++		buffer_info = &tx_ring->buffer_info[i];
++		if (buffer_info->dma) {
++			if (buffer_info->mapped_as_page)
++				dma_unmap_page(&pdev->dev, buffer_info->dma,
++						buffer_info->length, DMA_TO_DEVICE);
++			else
++				dma_unmap_single(&pdev->dev, buffer_info->dma,
++						buffer_info->length, DMA_TO_DEVICE);
++			buffer_info->dma = 0;
++		}
++		if (buffer_info->skb) {
++			dev_kfree_skb_any(buffer_info->skb);
++			buffer_info->skb = NULL;
++		}
++		buffer_info->time_stamp = 0;
++	}
++
++dma_error:
++	dev_err(&pdev->dev, "Tx DMA map failed at dma_error\n");
++	buffer_info->dma = 0;
++	return -ENOMEM;
++}
++
++static void ingenic_mac_restart_tx_dma(struct ingenic_mac_local *lp) {
++	/* TODO: clear error status bits if any */
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	u32 data;
++
++	data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaControl);
++	if (data & DmaTxStart) {
++		synopGMAC_resume_dma_tx(gmacdev);
++	} else {
++		synopGMAC_enable_dma_tx(gmacdev);
++	}
++
++	/* ensure irq is enabled */
++//	synopGMAC_enable_interrupt(gmacdev,DmaIntEnable);
++}
++
++static void ingenic_mac_tx_queue(struct ingenic_mac_local *lp,
++		struct ingenic_mac_tx_ring *tx_ring)
++{
++	DmaDesc *tx_desc = NULL;
++	struct ingenic_mac_buffer *buffer_info;
++	unsigned int i;
++
++	i = tx_ring->next_to_use;
++
++	buffer_info = &tx_ring->buffer_info[i];
++	tx_desc = INGENIC_MAC_TX_DESC(*tx_ring, i);
++
++	tx_desc->length |= (((cpu_to_le32(buffer_info->length) <<DescSize1Shift) & DescSize1Mask)
++			| ((0 <<DescSize2Shift) & DescSize2Mask));  // buffer2 is not used
++	tx_desc->buffer1 = cpu_to_le32(buffer_info->dma);
++	tx_desc->buffer2 = 0;
++	tx_desc->status |=  (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC
++	tx_desc->status |= DescOwnByDma;//ENH_DESC
++	if (unlikely(skb_shinfo(buffer_info->skb)->tx_flags & SKBTX_HW_TSTAMP)) {
++		tx_desc->status |= DescTxEnableTimestamp;
++		tx_desc->timestamphigh = 0;
++		tx_desc->timestamplow = 0;
++	}
++
++	wmb();
++
++	buffer_info->transfering = 1;
++
++	if (unlikely(++i == tx_ring->count)) i = 0;
++	tx_ring->next_to_use = i;
++
++	wmb();
++	ingenic_mac_restart_tx_dma(lp);
++}
++
++static int ingenic_mac_hard_start_xmit(struct sk_buff *skb,
++		struct net_device *netdev)
++{
++	struct ingenic_mac_local *lp = netdev_priv(netdev);
++	struct ingenic_mac_tx_ring *tx_ring;
++	unsigned int first;
++	int count = 1;
++	int tx_num;
++
++	tx_ring = &lp->tx_ring;
++
++#if 0
++	/* this can be cacelled for we should support it */
++	if (unlikely(skb->len <= 0)) {
++		printk(JZMAC_DRV_NAME ": WARNING: skb->len < 0\n");
++		dev_kfree_skb_any(skb);
++		return NETDEV_TX_OK;
++	}
++#endif
++
++	/* this can be cacelled for we should support it*/
++	/*
++	   if (skb_shinfo(skb)->nr_frags) {
++	   printk(JZMAC_DRV_NAME ": WARNING: fragment packet do not handled!!!\n");
++	   dev_kfree_skb_any(skb);
++	   return NETDEV_TX_OK;
++	   }
++	   */
++
++	/* need: count + 2 desc gap to keep tail from touching
++	 * head, otherwise try next time */
++	if (unlikely(ingenic_mac_maybe_stop_tx(netdev, tx_ring, count + 2)))
++		return NETDEV_TX_BUSY;
++
++	first = tx_ring->next_to_use;
++	count = ingenic_mac_tx_map(lp, tx_ring, skb);
++
++	if (likely(count)) {
++		ingenic_mac_tx_queue(lp, tx_ring);
++		/* Make sure there is space in the ring for the next send.*/
++		ingenic_mac_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 2);
++#ifdef CONFIG_INGENIC_GMAC_USE_HWSTAMP
++		ingenic_tx_hwtstamp(netdev, skb, first);
++#endif
++	} else {
++		dev_kfree_skb_any(skb);
++		tx_ring->buffer_info[first].time_stamp = 0;
++		tx_ring->next_to_use = first;
++	}
++
++	if(INGENIC_MAC_DESC_USED(tx_ring) > 16) {
++		hrtimer_cancel(&lp->tx_coalesce_timer);
++		tx_num = ingenic_mac_clean_tx_irq(lp);
++
++		if(INGENIC_MAC_DESC_UNUSED(tx_ring) < (tx_ring->count-1)) {
++			ingenic_start_tx_coalesce_timer(lp);
++		}
++	} else if(!hrtimer_is_queued(&lp->tx_coalesce_timer)){
++		ingenic_start_tx_coalesce_timer(lp);
++	}
++
++	return NETDEV_TX_OK;
++}
++
++static int ingenic_mac_clean_tx_irq(struct ingenic_mac_local *lp) {
++	struct net_device *netdev = lp->netdev;
++	struct ingenic_mac_buffer *buffer_info;
++	struct ingenic_mac_tx_ring *tx_ring = &lp->tx_ring;
++	DmaDesc *desc;
++	unsigned int i;
++	unsigned int count = 0;
++	unsigned int total_tx_bytes=0, total_tx_packets=0;
++
++	i = tx_ring->next_to_clean;
++	desc = INGENIC_MAC_TX_DESC(*tx_ring, i);
++	buffer_info = &tx_ring->buffer_info[i];
++
++	while (buffer_info->transfering &&
++			!synopGMAC_is_desc_owned_by_dma(desc) &&
++			(count < tx_ring->count)) {
++
++		buffer_info->transfering = 0;
++		count++;
++
++		if(synopGMAC_is_desc_valid(desc->status)){
++			total_tx_packets ++;
++			total_tx_bytes += buffer_info->length;
++		}
++
++		ingenic_mac_unmap_and_free_tx_resource(lp, buffer_info);
++		synopGMAC_tx_desc_init_ring(desc, i == (tx_ring->count - 1));
++
++		i++;
++		if (unlikely(i == tx_ring->count)) i = 0;
++
++		desc = INGENIC_MAC_TX_DESC(*tx_ring, i);
++		buffer_info = &tx_ring->buffer_info[i];
++	}
++
++	tx_ring->next_to_clean = i;
++
++#define TX_WAKE_THRESHOLD 16
++	if (unlikely(count && netif_carrier_ok(netdev) &&
++				INGENIC_MAC_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD)) {
++		/* Make sure that anybody stopping the queue after this
++		 * sees the new next_to_clean.
++		 */
++		smp_mb();
++		if (netif_queue_stopped(netdev)) {
++			netif_wake_queue(netdev);
++			++lp->restart_queue;
++		}
++	}
++
++	lp->net_stats.tx_bytes += total_tx_bytes;
++	lp->net_stats.tx_packets += total_tx_packets;
++
++	return count;
++}
++
++static bool inline ingenic_mac_clean_rx_irq(struct ingenic_mac_local *lp,
++		int *work_done, int work_to_do) {
++
++	struct net_device *netdev = lp->netdev;
++	struct ingenic_mac_rx_ring *rx_ring = &lp->rx_ring;
++	DmaDesc *rx_desc;
++	struct ingenic_mac_buffer *buffer_info;
++	u32 length;
++	unsigned int i;
++	int cleaned_count = 0;
++	unsigned int total_rx_bytes=0, total_rx_packets=0;
++
++	i = rx_ring->next_to_clean;
++	rx_desc = INGENIC_MAC_RX_DESC(*rx_ring, i);
++	buffer_info = &rx_ring->buffer_info[i];
++
++	/* except the slot not used, if transfer done, buffer_info->invalid is always 0 */
++	while ((!synopGMAC_is_desc_owned_by_dma(rx_desc)) && (!buffer_info->invalid)) {
++		struct sk_buff *skb;
++
++		if (*work_done >= work_to_do)
++			break;
++		(*work_done)++;
++		rmb();  /* read descriptor and rx_buffer_info after status DD */
++
++		buffer_info->invalid = 1;
++		skb = buffer_info->skb;
++		buffer_info->skb = NULL; /* cleaned */
++
++		cleaned_count++;
++
++		dma_unmap_single(&lp->netdev->dev,
++				buffer_info->dma, buffer_info->length,
++				DMA_FROM_DEVICE);
++		buffer_info->dma = 0;
++
++		if(!synopGMAC_is_rx_desc_valid(rx_desc->status)) {
++			/* save the skb in buffer_info as good */
++			dev_kfree_skb_any(skb);
++//			printk("====>invalid pkt 0x%x\n",rx_desc->status);
++			goto invalid_pkt;
++		}
++
++		length = synopGMAC_get_rx_desc_frame_length(rx_desc->status);
++//		synopGMAC_rx_desc_init_ring(rx_desc, rx_desc_i == (rx_ring->count - 1));
++#if 0
++		printk("============================================\n");
++		ingenic_mac_dump_pkt_data((unsigned char *)CKSEG1ADDR(buffer_info->dma),
++				length - 4);
++		printk("============================================\n");
++#endif
++
++
++		/* adjust length to remove Ethernet CRC, this must be
++		 * done after the TBI_ACCEPT workaround above */
++		length -= 4;
++
++		/* probably a little skewed due to removing CRC */
++		total_rx_bytes += length;
++		total_rx_packets++;
++
++		/* code added for copybreak, this should improve
++		 * performance for small packets with large amounts
++		 * of reassembly being done in the stack */
++
++#ifdef CONFIG_INGENIC_GMAC_USE_HWSTAMP
++		ingenic_rx_hwtstamp(netdev, skb, i);
++#endif
++
++		prefetch(skb->data - NET_IP_ALIGN);
++		skb_put(skb, length);
++		skb->protocol = eth_type_trans(skb, netdev);
++
++		//ingenic_mac_dump_skb_data(skb);
++//		netif_receive_skb(skb);
++		napi_gro_receive(&lp->napi, skb);
++
++invalid_pkt:
++		rx_desc->status = 0;
++		/* return some buffers to hardware, one at a time is too slow */
++		if (unlikely(cleaned_count >= INGENIC_MAC_RX_BUFFER_WRITE)) {
++			ingenic_mac_alloc_rx_buffers(lp, cleaned_count, 1);
++			cleaned_count = 0;
++		}
++		/* use prefetched values */
++		if (++i == rx_ring->count) i = 0;
++
++		rx_desc = INGENIC_MAC_RX_DESC(*rx_ring, i);
++		buffer_info = &rx_ring->buffer_info[i];
++		prefetch(rx_desc);
++	}
++
++	rx_ring->next_to_clean = i;
++
++	cleaned_count = INGENIC_MAC_DESC_UNUSED(rx_ring);
++	if (cleaned_count)
++		ingenic_mac_alloc_rx_buffers(lp, cleaned_count, 1);
++
++	lp->net_stats.rx_bytes += total_rx_bytes;
++	lp->net_stats.rx_packets += total_rx_packets;
++
++	return 0;
++}
++
++
++#ifdef CONFIG_INGENIC_GMAC_MUTUAL_TRANS
++static spinlock_t napi_poll_lock;
++static spinlock_t record_lock;
++static struct ingenic_mac_local *lp_record[2];
++static atomic_t record[2] = {0};
++static atomic_t enter;
++#endif
++/**
++ * ingenic_mac_clean - NAPI Rx polling callback
++ **/
++static int ingenic_mac_clean(struct napi_struct *napi, int budget) {
++	struct ingenic_mac_local *lp = container_of(napi, struct ingenic_mac_local, napi);
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	int rx_num = 0;
++
++#ifdef CONFIG_INGENIC_GMAC_MUTUAL_TRANS
++	int id;
++	if(!spin_trylock(&napi_poll_lock)){
++		spin_lock(&record_lock);
++		if(atomic_read(&enter)) {
++			spin_unlock(&record_lock);
++			spin_lock(&napi_poll_lock);
++		} else {
++			atomic_set(&record[lp->id], 1);
++			napi_complete(napi);
++			spin_unlock(&record_lock);
++			return rx_num;
++		}
++	}
++	atomic_set(&enter, 0);
++#else
++	spin_lock(&lp->napi_poll_lock);
++#endif
++
++	ingenic_mac_clean_rx_irq(lp, &rx_num, budget);
++
++#ifdef CONFIG_INGENIC_GMAC_MUTUAL_TRANS
++	spin_lock(&record_lock);
++	atomic_set(&enter, 1);
++	id = (lp->id+1)%2;
++	if(atomic_read(&record[id]) == 1) {
++		atomic_set(&record[id], 0);
++		if (likely(napi_schedule_prep(&lp_record[id]->napi))) {
++			__napi_schedule(&lp_record[id]->napi);
++		}
++	}
++	spin_unlock(&record_lock);
++#endif
++
++	if((lp->wake_irq_num < lp->net_stats.rx_packets)) {
++		lp->wake_irq_num = lp->net_stats.rx_packets + INGENIC_WAKE_IRQ_NUM;
++		napi_complete(napi);
++		synopGMAC_enable_interrupt(gmacdev,DmaIntEnable);
++		rx_num = (rx_num == budget) ? (rx_num-1) : rx_num;
++		goto end;
++	}
++
++	if (rx_num < budget) {
++		napi_complete(napi);
++		synopGMAC_enable_interrupt(gmacdev,DmaIntEnable);
++		//ingenic_start_rx_coalesce_timer(lp);
++	}
++
++end:
++#ifdef CONFIG_INGENIC_GMAC_MUTUAL_TRANS
++	spin_unlock(&napi_poll_lock);
++#else
++	spin_unlock(&lp->napi_poll_lock);
++#endif
++	return rx_num;
++}
++
++/* interrupt routine to handle rx and error signal */
++static irqreturn_t ingenic_mac_interrupt(int irq, void *data)
++{
++	struct net_device *netdev = data;
++	struct ingenic_mac_local *lp = netdev_priv(netdev);
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	u32 interrupt,dma_status_reg;
++	u32 mac_interrupt_status;
++	u32 rgmii_interrupt_status;
++	u32 lpi_interrupt_status;
++
++	/* Read the Dma interrupt status to know whether the interrupt got generated by our device or not*/
++	dma_status_reg = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaStatus);
++	mac_interrupt_status = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacInterruptStatus);
++
++	//printk("===>enter %s:%d DmaStatus = 0x%08x\n", __func__, __LINE__, dma_status_reg);
++	if(dma_status_reg == 0)
++		return IRQ_NONE;
++
++	synopGMAC_disable_interrupt_all(gmacdev);
++
++
++	if(dma_status_reg & GmacPmtIntr){
++		dev_err(&netdev->dev, "%s:: Interrupt due to PMT module\n",__FUNCTION__);
++		//synopGMAC_linux_powerup_mac(gmacdev);
++	}
++
++	if(dma_status_reg & GmacMmcIntr){
++		dev_err(&netdev->dev, "%s:: Interrupt due to MMC module\n",__FUNCTION__);
++		dev_err(&netdev->dev, "%s:: synopGMAC_rx_int_status = %08x\n",
++				__FUNCTION__,synopGMAC_read_mmc_rx_int_status(gmacdev));
++		dev_err(&netdev->dev, "%s:: synopGMAC_tx_int_status = %08x\n",
++				__FUNCTION__,synopGMAC_read_mmc_tx_int_status(gmacdev));
++	}
++
++	if(dma_status_reg & GmacLineIntfIntr){
++		if (mac_interrupt_status & GmacRgmiiIntSts) {
++			rgmii_interrupt_status = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacRGMIIControl);
++			dev_dbg(&netdev->dev, "%s:Interrupts to RGMII/SGMII: 0x%08x\n",__FUNCTION__,rgmii_interrupt_status);
++		} else
++			dev_err(&netdev->dev, "%s:: Interrupt due to GMAC LINE module\n",__FUNCTION__);
++	}
++
++	if(dma_status_reg & GmacLPIIntr){
++		if (mac_interrupt_status & GmacLPIIS) {
++			lpi_interrupt_status = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacLPICtrlSts);
++			dev_dbg(&netdev->dev, "%s:Interrupts to LPI: 0x%08x\n",__FUNCTION__,lpi_interrupt_status);
++		} else
++			dev_err(&netdev->dev, "%s:: Interrupt due to GMAC LPI module\n",__FUNCTION__);
++	}
++
++	/* Now lets handle the DMA interrupts*/
++	interrupt = synopGMAC_get_interrupt_type(gmacdev);
++	dev_dbg(&netdev->dev, "%s:Interrupts to be handled: 0x%08x\n",__FUNCTION__,interrupt);
++
++
++	if(interrupt & synopGMACDmaError){
++		dev_err(&netdev->dev, "%s::Fatal Bus Error Inetrrupt Seen\n",__FUNCTION__);
++		/* do nothing here, let tx_timeout to handle it */
++	}
++
++	if(interrupt & synopGMACDmaRxAbnormal){
++		dev_dbg(&netdev->dev, "%s::Abnormal Rx Interrupt Seen\n",__FUNCTION__);
++		synopGMAC_resume_dma_rx(gmacdev);
++	}
++
++	if(interrupt & synopGMACDmaRxStopped){
++		// Receiver gone in to stopped state
++		// why Rx Stopped? no enough descriptor? but why no enough descriptor need cause an interrupt?
++		// we have no enough descriptor because we can't handle packets that fast, isn't it?
++		// So I think if DmaRxStopped Interrupt can disabled
++		dev_info(&netdev->dev, "%s::Receiver stopped seeing Rx interrupts\n",__FUNCTION__);
++
++//		synopGMAC_enable_dma_rx(gmacdev);
++	}
++
++	if(interrupt & synopGMACDmaTxAbnormal){
++		dev_dbg(&netdev->dev, "%s::Abnormal Tx Interrupt Seen\n",__FUNCTION__);
++	}
++
++	if(interrupt & synopGMACDmaTxStopped){
++		dev_info(&netdev->dev, "%s::Transmitter stopped sending the packets\n",__FUNCTION__);
++//		synopGMAC_disable_dma_tx(gmacdev);
++//		ingenic_mac_dump_all_desc(lp);
++//		ingenic_mac_take_desc_ownership_tx(lp);
++//		synopGMAC_enable_dma_tx(gmacdev);
++	}
++
++	if (likely(napi_schedule_prep(&lp->napi))) {
++		dev_dbg(&netdev->dev, "enter %s:%d, call __napi_schedule\n", __func__, __LINE__);
++		//hrtimer_cancel(&lp->rx_coalesce_timer);
++		__napi_schedule(&lp->napi);
++	} else {
++		/* this really should not happen! if it does it is basically a
++		 * bug, but not a hard error, so enable ints and continue */
++		synopGMAC_enable_interrupt(gmacdev,DmaIntEnable);
++	}
++
++	return IRQ_HANDLED;
++}
++
++/* MAC control and configuration */
++
++static void ingenic_mac_stop_activity(struct ingenic_mac_local *lp) {
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	synopGMAC_disable_interrupt_all(gmacdev);
++
++	// Disable the Dma in rx path
++	synopGMAC_disable_dma_rx(gmacdev);
++	ingenic_mac_take_desc_ownership_rx(lp);
++	//msleep(100);	      // Allow any pending buffer to be read by host
++	//synopGMAC_rx_disable(gmacdev);
++
++	synopGMAC_disable_dma_tx(gmacdev);
++	ingenic_mac_take_desc_ownership_tx(lp);
++	//msleep(100);	      // allow any pending transmission to complete
++	// Disable the Mac for both tx and rx
++	//synopGMAC_tx_disable(gmacdev);
++}
++
++static void ingenic_mac_disable(struct ingenic_mac_local *lp) {
++	/* First ensure that the upper network stack is stopped */
++	/* can be netif_tx_disable when NETIF_F_LLTX is removed */
++	netif_stop_queue(lp->netdev); /* tx */
++	napi_disable(&lp->napi); /* rx */
++
++	ingenic_mac_stop_activity(lp);
++
++	spin_lock(&lp->napi_poll_lock);
++	desc_list_reinit(lp);
++	spin_unlock(&lp->napi_poll_lock);
++}
++
++static void ingenic_mac_init(struct ingenic_mac_local *lp) {
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	/*
++	 * disable the watchdog and gab to receive frames up to 16384 bytes
++	 * to adjust IP protocol
++	 */
++	synopGMAC_wd_disable(gmacdev);
++	synopGMAC_jab_disable(gmacdev);
++
++	/* cancel to set Frame Burst Enable for now we use duplex mode */
++	//synopGMAC_frame_burst_enable(gmacdev);
++
++	/* set jumbo to allow to receive Jumbo frames of 9,018 bytes */
++	//synopGMAC_jumbo_frame_disable(gmacdev);
++	synopGMAC_jumbo_frame_enable(gmacdev);
++
++	/* for we try to use duplex */
++	synopGMAC_rx_own_disable(gmacdev);
++	synopGMAC_loopback_off(gmacdev);
++	/* default to full duplex, I think this will be the common case */
++	synopGMAC_set_full_duplex(gmacdev);
++	/* here retry enabe may useless */
++	synopGMAC_retry_enable(gmacdev);
++	synopGMAC_pad_crc_strip_disable(gmacdev);
++	synopGMAC_back_off_limit(gmacdev,GmacBackoffLimit0);
++	synopGMAC_deferral_check_disable(gmacdev);
++	synopGMAC_tx_enable(gmacdev);
++	synopGMAC_rx_enable(gmacdev);
++
++	/* default to 100M, I think this will be the common case */
++	synopGMAC_select_mii(gmacdev);
++	synopGMAC_select_speed100(gmacdev);
++
++	/* Frame Filter Configuration */
++	synopGMAC_frame_filter_enable(gmacdev);
++	synopGMAC_set_pass_control(gmacdev,GmacPassControl0);
++	synopGMAC_broadcast_enable(gmacdev);
++	synopGMAC_src_addr_filter_disable(gmacdev);
++	synopGMAC_multicast_enable(gmacdev);
++	synopGMAC_dst_addr_filter_normal(gmacdev);
++	synopGMAC_multicast_hash_filter_disable(gmacdev);
++	synopGMAC_promisc_disable(gmacdev);
++	synopGMAC_unicast_hash_filter_disable(gmacdev);
++
++	/*Flow Control Configuration*/
++	synopGMAC_unicast_pause_frame_detect_disable(gmacdev);
++	synopGMAC_pause_control(gmacdev); // This enables the pause control in Full duplex mode of operation
++	lp->flowcontrol.tx = 0;
++	lp->flowcontrol.rx = 1;
++	lp->flowcontrol.autoneg = 0;
++}
++
++static void ingenic_mac_configure(struct ingenic_mac_local *lp) {
++	synopGMACdevice *gmacdev = lp->gmacdev;
++#ifdef ENH_DESC_8W
++#ifndef CONFIG_INGENIC_MAC_AXI_BUS
++	synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength32 | DmaDescriptorSkip2 | DmaDescriptor8Words | DmaFixedBurstEnable | 0x02000000); //pbl32 incr with rxthreshold 128 and Desc is 8 Words
++#else
++	synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength32 | DmaDescriptorSkip1 | DmaDescriptor8Words);
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaAxiMode, synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaAxiMode) | (0x1 << 31));
++#endif
++#else
++	/* pbl32 incr with rxthreshold 128 */
++	synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength32 | DmaDescriptorSkip2);
++#endif
++	/* DmaRxThreshCtrl128 is ok for the RX FIFO is configured to 256 Bytes */
++	synopGMAC_dma_control_init(gmacdev,DmaStoreAndForward |DmaTxSecondFrame|DmaRxThreshCtrl128);
++
++	/*Initialize the mac interface*/
++
++	ingenic_mac_init(lp);
++
++#ifdef IPC_OFFLOAD
++	/*IPC Checksum offloading is enabled for this driver. Should only be used if Full Ip checksumm offload engine is configured in the hardware*/
++	synopGMAC_enable_rx_chksum_offload(gmacdev);  	//Enable the offload engine in the receive path
++	synopGMAC_rx_tcpip_chksum_drop_enable(gmacdev); // This is default configuration, DMA drops the packets if error in encapsulated ethernet payload
++	// The FEF bit in DMA control register is configured to 0 indicating DMA to drop the errored frames.
++	/*Inform the Linux Networking stack about the hardware capability of checksum offloading*/
++	netdev->features = NETIF_F_HW_CSUM;
++#endif
++
++	synopGMAC_clear_interrupt(gmacdev);
++	/*
++	   Disable the interrupts generated by MMC and IPC counters.
++	   If these are not disabled ISR should be modified accordingly to handle these interrupts.
++	   */
++	synopGMAC_disable_mmc_tx_interrupt(gmacdev, 0xFFFFFFFF);
++	synopGMAC_disable_mmc_rx_interrupt(gmacdev, 0xFFFFFFFF);
++	synopGMAC_disable_mmc_ipc_rx_interrupt(gmacdev, 0xFFFFFFFF);
++}
++
++/*
++ * Enable Interrupts, Receive, and Transmit(The same sequence as ingenic_mac_open, only a bit different)
++ */
++static void ingenic_mac_enable(struct ingenic_mac_local *lp) {
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	ingenic_mac_configure(lp);
++
++	napi_enable(&lp->napi);
++	synopGMAC_enable_interrupt(gmacdev,DmaIntEnable);
++	/* we only enable rx here */
++	synopGMAC_enable_dma_rx(gmacdev);
++	/* We can accept TX packets again */
++	lp->netdev->_tx->trans_start = jiffies;
++	netif_wake_queue(lp->netdev);
++}
++
++static void ingenic_mac_reinit_locked(struct ingenic_mac_local *lp)
++{
++	WARN_ON(in_interrupt());
++	ingenic_mac_disable(lp);
++	ingenic_mac_enable(lp);
++}
++
++/* Our watchdog timed out. Called by the networking layer */
++static void ingenic_mac_tx_timeout(struct net_device *dev, unsigned int txqueue)
++{
++	struct ingenic_mac_local *lp = netdev_priv(dev);
++
++	/* Do the reset outside of interrupt context */
++	lp->tx_timeout_count++;
++	schedule_work(&lp->reset_task);
++}
++
++static void ingenic_mac_reset_task(struct work_struct *work)
++{
++	struct ingenic_mac_local *lp =
++		container_of(work, struct ingenic_mac_local, reset_task);
++
++	ingenic_mac_reinit_locked(lp);
++}
++
++static void setup_mac_addr(synopGMACdevice *gmacdev, u8 *mac_addr) {
++	synopGMAC_set_mac_addr(gmacdev,
++			       GmacAddr0High,GmacAddr0Low,
++			       mac_addr);
++}
++
++static int ingenic_mac_set_mac_address(struct net_device *dev, void *p) {
++	struct ingenic_mac_local *lp = netdev_priv(dev);
++	synopGMACdevice *gmacdev = lp->gmacdev;
++
++	struct sockaddr *addr = p;
++	if (netif_running(dev))
++		return -EBUSY;
++	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
++	setup_mac_addr(gmacdev, dev->dev_addr);
++	return 0;
++}
++
++/*
++ * Open and Initialize the interface
++ *
++ * Set up everything, reset the card, etc..
++ */
++static int ingenic_mac_open(struct net_device *dev)
++{
++	struct ingenic_mac_local *lp = netdev_priv(dev);
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	int retval;
++
++	pr_debug("%s: %s\n", dev->name, __func__);
++	if (ingenic_mac_phy_hwrst(lp->pdev, false)) {
++		return -ENODEV;
++	}
++
++	retval = phy_read(lp->phydev, MII_BMCR);
++	retval &= ~(1 << 11);
++	phy_write(lp->phydev, MII_BMCR, retval);
++
++	/*
++	 * Check that the address is valid.  If its not, refuse
++	 * to bring the device up.  The user must specify an
++	 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
++	 */
++	if (!is_valid_ether_addr(dev->dev_addr)) {
++		printk(KERN_WARNING INGENIC_MAC_DRV_NAME ": no valid ethernet hw addr\n");
++		return -EINVAL;
++	}
++
++	phy_write(lp->phydev, MII_BMCR, BMCR_RESET | phy_read(lp->phydev, MII_BMCR));
++	while(phy_read(lp->phydev, MII_BMCR) & BMCR_RESET);
++	phy_start(lp->phydev);
++
++	if (synopGMAC_reset(gmacdev) < 0) {
++		printk("func:%s, synopGMAC_reset failed\n", __func__);
++		phy_stop(lp->phydev);
++		return -1;
++	}
++
++	/* init MDC CLK */
++	ingenic_set_mdc_rate(lp);
++
++	/* initial rx and tx list */
++	retval = desc_list_init(lp);
++
++	if (retval)
++		return retval;
++
++	setup_mac_addr(gmacdev, dev->dev_addr);
++	ingenic_mac_configure(lp);
++
++	//ingenic_mac_dump_all_regs(gmacdev, __func__, __LINE__);
++
++	napi_enable(&lp->napi);
++
++	/* we are ready, reset GMAC and enable interrupts */
++	synopGMAC_enable_interrupt(gmacdev,DmaIntEnable);
++	/* we only enable rx here */
++	synopGMAC_enable_dma_rx(gmacdev);
++
++	lp->wake_irq_num = lp->net_stats.rx_packets + INGENIC_WAKE_IRQ_NUM;
++
++	/* We can accept TX packets again */
++	lp->netdev->_tx->trans_start = jiffies;
++	netif_start_queue(dev);
++
++	return 0;
++}
++
++/*
++ * this makes the board clean up everything that it can
++ * and not talk to the outside world.   Caused by
++ * an 'ifconfig ethX down'
++ */
++static int ingenic_mac_close(struct net_device *dev)
++{
++	struct ingenic_mac_local *lp = netdev_priv(dev);
++	synopGMACdevice *gmacdev = lp->gmacdev;
++
++	synopGMAC_clear_interrupt(gmacdev);
++	synopGMAC_disable_interrupt_all(gmacdev);
++	ingenic_mac_disable(lp);
++
++	netif_carrier_off(dev);
++
++	phy_stop(lp->phydev);
++	phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
++
++	/* free the rx/tx buffers */
++	desc_list_free(lp);
++	return 0;
++}
++
++static void ingenic_mac_change_rx_flags(struct net_device *dev, int flags)
++{
++	struct ingenic_mac_local *lp = netdev_priv(dev);
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	if (dev->flags & IFF_PROMISC) {
++		/* Accept any kinds of packets */
++		synopGMAC_promisc_enable(gmacdev);
++		//	synopGMAC_frame_filter_disable(gmacdev);
++		printk("%s: Enter promisc mode!\n",dev->name);
++	}else{
++		synopGMAC_promisc_disable(gmacdev);
++	}
++}
++
++static struct net_device_stats *ingenic_mac_get_stats(struct net_device *netdev)
++{
++	struct ingenic_mac_local *lp = netdev_priv(netdev);
++
++	/* only return the current stats */
++	return &lp->net_stats;
++}
++
++static int ingenic_mac_change_mtu(struct net_device *netdev, int new_mtu) {
++	int running = netif_running(netdev);
++	int err;
++
++	if (new_mtu < MIN_ETHERNET_PAYLOAD || new_mtu > JUMBO_FRAME_PAYLOAD)
++		return -EINVAL;
++
++	if (running)
++		ingenic_mac_close(netdev);
++
++	netdev_info(netdev, "MTU change from %d to %d\n", netdev->mtu, new_mtu);
++	netdev->mtu = new_mtu;
++
++	if (running)
++		err = ingenic_mac_open(netdev);
++
++	return err;
++}
++
++static int ingenic_mac_do_ioctl(struct net_device *netdev, struct ifreq *ifr, s32 cmd) {
++	struct ingenic_mac_local *lp = netdev_priv(netdev);
++
++	if (!netif_running(netdev)) {
++		printk("error : it is not in netif_running\n");
++		return -EINVAL;
++	}
++
++	if(!(lp->phydev->link))
++		return 0;
++
++	switch (cmd) {
++	case SIOCSHWTSTAMP:
++		return ingenic_mac_hwtstamp_ioctl(netdev, ifr, cmd);
++	default:
++		return generic_mii_ioctl(&lp->mii, if_mii(ifr), cmd, NULL);
++	}
++}
++
++static const struct net_device_ops ingenic_mac_netdev_ops = {
++	.ndo_open		= ingenic_mac_open,
++	.ndo_stop		= ingenic_mac_close,
++	.ndo_start_xmit		= ingenic_mac_hard_start_xmit,
++	.ndo_change_rx_flags	= ingenic_mac_change_rx_flags,
++	.ndo_get_stats		= ingenic_mac_get_stats,
++	.ndo_set_mac_address	= ingenic_mac_set_mac_address,
++	.ndo_tx_timeout		= ingenic_mac_tx_timeout,
++	.ndo_validate_addr	= eth_validate_addr,
++	.ndo_change_mtu		= ingenic_mac_change_mtu,
++	.ndo_do_ioctl		= ingenic_mac_do_ioctl,
++};
++
++/* Read an off-chip register in a PHY through the MDC/MDIO port */
++static int ingenic_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
++{
++	u16 data = 0;
++	struct ingenic_mac_local *lp = bus->priv;
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	s32 status;
++	if(lp->no_phy_connect){
++		return (int)lp->virt_phy.reg[regnum];
++	} else {
++		status = synopGMAC_read_phy_reg(gmacdev, phy_addr, regnum, &data);
++		if (status)
++			data = 0;
++		return (int)data;
++	}
++}
++/* Write an off-chip register in a PHY through the MDC/MDIO port */
++static int ingenic_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
++{
++	struct ingenic_mac_local *lp = bus->priv;
++	synopGMACdevice *gmacdev = lp->gmacdev;
++	u16 tmp,force_op,autoneg_op;
++	if(lp->no_phy_connect){
++		/* 0x0 Basic mode control reg*/
++		if(regnum == MII_BMCR){
++
++			tmp = lp->virt_phy.reg[MII_BMCR];
++			/*down_op :maintain the register value when ifconfig ethx down operation*/
++			if(!(value & BMCR_PDOWN)){
++				tmp &= ~(BMCR_SPEED1000 | BMCR_SPEED100 | BMCR_FULLDPLX);
++				tmp |= value;
++
++				/*force_op :configure other registers according to BCMR register after forced operation*/
++				force_op = (value & (BMCR_SPEED1000 | BMCR_SPEED100));
++				switch(force_op){
++					case BMCR_SPEED1000:
++						lp->virt_phy.reg[MII_ADVERTISE] &= ~(ADVERTISE_ALL);
++						lp->virt_phy.reg[MII_LPA] &= ~(ADVERTISE_ALL);
++						lp->virt_phy.reg[MII_BMSR] |= BMSR_ESTATEN;
++
++						if(value & BMCR_FULLDPLX){
++							lp->virt_phy.reg[MII_CTRL1000] = ADVERTISE_1000FULL;
++							lp->virt_phy.reg[MII_STAT1000] = LPA_1000FULL;
++						} else {
++							lp->virt_phy.reg[MII_CTRL1000] = ADVERTISE_1000HALF;
++							lp->virt_phy.reg[MII_STAT1000] = LPA_1000HALF;
++						}
++						break;
++
++					case BMCR_SPEED100:
++						lp->virt_phy.reg[MII_BMSR] &= ~(BMSR_ESTATEN);
++						lp->virt_phy.reg[MII_CTRL1000] &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
++						lp->virt_phy.reg[MII_STAT1000] &= ~(LPA_1000FULL | LPA_1000HALF);
++
++						if(value & BMCR_FULLDPLX){
++							lp->virt_phy.reg[MII_ADVERTISE] &= ~(ADVERTISE_ALL);
++							lp->virt_phy.reg[MII_ADVERTISE] |= ADVERTISE_100FULL;
++							lp->virt_phy.reg[MII_LPA] &= ~(ADVERTISE_ALL);
++							lp->virt_phy.reg[MII_LPA] |= LPA_100FULL;
++						} else {
++
++							lp->virt_phy.reg[MII_ADVERTISE] &= ~(ADVERTISE_ALL);
++							lp->virt_phy.reg[MII_ADVERTISE] |= ADVERTISE_100HALF;
++							lp->virt_phy.reg[MII_LPA] &= ~(ADVERTISE_ALL);
++							lp->virt_phy.reg[MII_LPA] |= LPA_100HALF;
++						}
++						break;
++
++					case 0x0:
++						lp->virt_phy.reg[MII_BMSR] &= ~(BMSR_ESTATEN);
++						lp->virt_phy.reg[MII_CTRL1000] &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
++						lp->virt_phy.reg[MII_STAT1000] &= ~(LPA_1000FULL | LPA_1000HALF);
++
++						if(value & BMCR_FULLDPLX){
++							lp->virt_phy.reg[MII_ADVERTISE] &= ~(ADVERTISE_ALL);
++							lp->virt_phy.reg[MII_ADVERTISE] |= ADVERTISE_10FULL;
++							lp->virt_phy.reg[MII_LPA] &= ~(ADVERTISE_ALL);
++							lp->virt_phy.reg[MII_LPA] |= LPA_10FULL;
++						} else {
++							lp->virt_phy.reg[MII_ADVERTISE] &= ~(ADVERTISE_ALL);
++							lp->virt_phy.reg[MII_ADVERTISE] |= ADVERTISE_10HALF;
++							lp->virt_phy.reg[MII_LPA] &= ~(ADVERTISE_ALL);
++							lp->virt_phy.reg[MII_LPA] |= LPA_10HALF;
++						}
++
++					default:
++						break;
++
++				}
++			}
++			tmp &= ~(BMCR_RESET | BMCR_PDOWN);/*clean reset bit*/
++			lp->virt_phy.reg[MII_BMCR] = tmp;
++		}
++
++		/* 0x4 Advertisement control reg*/
++		if((regnum == MII_ADVERTISE))
++		{
++			tmp = lp->virt_phy.reg[MII_ADVERTISE];
++			tmp &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
++			tmp |= value;
++			lp->virt_phy.reg[MII_ADVERTISE] = tmp;
++
++			tmp = lp->virt_phy.reg[MII_LPA];
++			tmp &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
++			tmp |= value;
++			lp->virt_phy.reg[MII_LPA] = tmp;
++
++			/* 0x1 Basic mode status reg*/
++			tmp = lp->virt_phy.reg[MII_BMSR];
++			tmp |= BMSR_ESTATEN;
++			if(lp->virt_phy.reg[MII_ADVERTISE] & ADVERTISE_ALL){
++				tmp &= ~(BMSR_ESTATEN);  /*1000M need extended*/
++			}
++			lp->virt_phy.reg[MII_BMSR] = tmp;
++
++			/* 0x9 1000BASE-T control reg*/
++			if(lp->virt_phy.reg[MII_ADVERTISE] & ADVERTISE_ALL){
++				lp->virt_phy.reg[MII_CTRL1000] &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
++			}
++
++			/* 0xa 1000BASE-T status reg*/
++			if(lp->virt_phy.reg[MII_LPA] & ADVERTISE_ALL){
++				lp->virt_phy.reg[MII_STAT1000] &= ~(LPA_1000FULL | LPA_1000HALF);
++			}
++
++			/*autoneg_op :update BMCR register since negotiation operation*/
++			autoneg_op = (value & ADVERTISE_ALL);
++			if(autoneg_op){
++				tmp = lp->virt_phy.reg[MII_BMCR];
++				tmp &= ~(BMCR_SPEED1000 | BMCR_SPEED100 | BMCR_FULLDPLX);
++				switch(autoneg_op){
++					case ADVERTISE_100FULL:
++						tmp |= (BMCR_SPEED100 | BMCR_FULLDPLX);
++						break;
++					case ADVERTISE_100HALF:
++						tmp |= BMCR_SPEED100;
++						break;
++					case ADVERTISE_10FULL:
++						tmp |= BMCR_FULLDPLX;
++						break;
++					case ADVERTISE_10HALF:
++						tmp |= 0;
++						break;
++					default:
++						break;
++
++				}
++				lp->virt_phy.reg[MII_BMCR] = tmp;
++			}
++		}
++		/* 0x9 1000BASE-T control reg*/
++		if(regnum == MII_CTRL1000){
++			lp->virt_phy.reg[MII_CTRL1000] = value;
++			/* 0xa 1000BASE-T status reg*/
++			lp->virt_phy.reg[MII_STAT1000] = value << 2;
++
++			/*autoneg_op :update BMCR register since negotiation operation*/
++			autoneg_op = (value & (ADVERTISE_1000FULL | ADVERTISE_1000HALF));
++			if(autoneg_op){
++				tmp = lp->virt_phy.reg[MII_BMCR];
++				tmp &= ~(BMCR_SPEED1000 | BMCR_SPEED100 | BMCR_FULLDPLX);
++				switch(autoneg_op){
++					case ADVERTISE_1000FULL:
++						tmp |= (BMCR_SPEED1000 | BMCR_FULLDPLX);
++						break;
++					case ADVERTISE_1000HALF:
++						tmp |= BMCR_SPEED1000;
++						break;
++					default:
++						break;
++
++				}
++				lp->virt_phy.reg[MII_BMCR] = tmp;
++			}
++		}
++
++		return 0;
++	} else {
++		return synopGMAC_write_phy_reg(gmacdev, phy_addr, regnum, value);
++	}
++}
++
++static int ingenic_mdiobus_reset(struct mii_bus *bus)
++{
++	return 0;
++}
++
++static int ingenic_mdio_phy_read(struct net_device *dev, int phy_id, int location)
++{
++	struct ingenic_mac_local *lp = netdev_priv(dev);
++	return ingenic_mdiobus_read(lp->mii_bus, phy_id, location);
++}
++
++static void ingenic_mdio_phy_write(struct net_device *dev, int phy_id, int location, int value)
++{
++	struct ingenic_mac_local *lp = netdev_priv(dev);
++
++	ingenic_mdiobus_write(lp->mii_bus, phy_id, location, value);
++}
++
++static int ingenic_mac_interface_init(struct ingenic_mac_local *lp)
++{
++	struct platform_device *pdev = lp->pdev;
++	struct device *dev = &pdev->dev;
++	struct device_node *np = dev->of_node;
++	unsigned int rx_clk_delay = 0;
++	unsigned int tx_clk_delay = 0;
++	unsigned int cpm_mphyc;
++	unsigned int data;
++	unsigned int val;
++	int err;
++
++	switch(lp->interface) {
++		case RMII:
++		case MII:
++		case GMII:
++			break;
++		case RGMII:
++			break;
++		default:
++			dev_err(dev, "Gmac interface mode err!\n");
++			return -EINVAL;
++	}
++
++	err = of_property_read_u32(np, "ingenic,mode-reg", &cpm_mphyc);
++	if (err < 0) {
++		dev_err(dev, "Gmac get interface mode register failed!\n");
++		return err;
++	}
++
++	if(lp->interface==RGMII) {
++		err = of_property_read_u32(np, "ingenic,rx-clk-delay", &rx_clk_delay);
++		if (err < 0) {
++			dev_info(dev, "Gmac rgmii set origin rx-clk\n");
++		}
++
++		err = of_property_read_u32(np, "ingenic,tx-clk-delay", &tx_clk_delay);
++		if (err < 0) {
++			dev_info(dev, "Gmac rgmii set origin tx-clk\n");
++		}
++	}
++
++	/* Set gmac interface mode */
++	if(lp->interface==RMII || lp->interface==RGMII)
++		val = lp->interface;
++	else
++		val = 0;
++
++	data = *(volatile unsigned int *)cpm_mphyc;
++	if(tx_clk_delay > 0 && tx_clk_delay <= 128)
++		data = (data & ~(0x7f << 12)) | ((tx_clk_delay-1) << 12) | (0x1 << 19);
++	if(rx_clk_delay > 0 && rx_clk_delay <= 128)
++		data = (data & ~(0x7f << 4)) | ((rx_clk_delay-1) << 4) | (0x1 << 11);
++	*(volatile unsigned int *)cpm_mphyc = (data & ~0x7) | val;
++
++	return 0;
++}
++
++static int ingenic_mac_virtual_phy_init(struct ingenic_mac_local *lp)
++{
++	u16 tmp = 0;
++	/* 0x0 Basic mode control reg*/
++	tmp = (lp->interface == RMII)?(BMCR_SPEED100 | BMCR_FULLDPLX):(BMCR_SPEED1000 | BMCR_FULLDPLX);
++
++	if(lp->dts_ctl.duplex == 1){
++		tmp |= BMCR_FULLDPLX;
++	}else if(lp->dts_ctl.duplex == 2){
++		tmp &= ~BMCR_FULLDPLX;
++	}
++
++	if(lp->dts_ctl.speed == 1000){
++		tmp |= BMCR_SPEED1000;
++	}else if(lp->dts_ctl.speed == 100){
++		tmp |= BMCR_SPEED100;
++	}else if(lp->dts_ctl.speed == 10){
++		tmp &= ~(BMCR_SPEED1000 | BMCR_SPEED100);
++	}
++	lp->virt_phy.reg[MII_BMCR] = tmp;
++
++	/* 0x1 Basic mode status reg*/
++	lp->virt_phy.reg[MII_BMSR] = BMSR_LSTATUS | BMSR_ANEGCAPABLE | BMSR_ANEGCOMPLETE | BMSR_100FULL |\
++			             BMSR_100HALF | BMSR_10FULL | BMSR_10HALF | BMSR_ESTATEN;
++
++	/* 0x2 PHYS ID 1 reg*/
++	lp->virt_phy.reg[MII_PHYSID1] = 0x5555;
++
++	/* 0x3 PHYS ID 2 reg*/
++	lp->virt_phy.reg[MII_PHYSID2] = (lp->id & 0xffff);
++
++	/* 0x4 Advertisement control reg*/
++	tmp = ADVERTISE_LPACK | ADVERTISE_PAUSE_CAP;
++	if(lp->dts_ctl.duplex == 1){
++		if(lp->dts_ctl.speed == 100){
++			tmp |= ADVERTISE_100FULL;
++		}else if(lp->dts_ctl.speed == 10){
++			tmp |= ADVERTISE_10FULL;
++		}
++	}else if(lp->dts_ctl.duplex == 2){
++		if(lp->dts_ctl.speed == 100){
++			tmp |= ADVERTISE_100HALF;
++		}else if(lp->dts_ctl.speed == 10){
++			tmp |= ADVERTISE_10HALF;
++		}
++	}
++	lp->virt_phy.reg[MII_ADVERTISE] = tmp;
++
++	/* 0x5 Link partner ability reg*/
++	tmp = LPA_LPACK | LPA_PAUSE_CAP;
++	if(lp->dts_ctl.duplex == 1){
++		if(lp->dts_ctl.speed == 100){
++			tmp |= LPA_100FULL;
++		}else if(lp->dts_ctl.speed == 10){
++			tmp |= LPA_10FULL;
++		}
++	}else if(lp->dts_ctl.duplex == 2){
++		if(lp->dts_ctl.speed == 100){
++			tmp |= LPA_100HALF;
++		}else if(lp->dts_ctl.speed == 10){
++			tmp |= LPA_10HALF;
++		}
++	}
++	lp->virt_phy.reg[MII_LPA] = tmp;
++
++	/* 0x9 1000BASE-T control reg*/
++	if(lp->dts_ctl.speed == 1000){
++		if(lp->dts_ctl.duplex == 1){
++			tmp = ADVERTISE_1000FULL;
++		}else if(lp->dts_ctl.duplex == 2){
++			tmp = ADVERTISE_1000HALF;
++		}
++	}
++	lp->virt_phy.reg[MII_CTRL1000] = tmp;
++
++	/* 0xa 1000BASE-T status reg*/
++	if(lp->dts_ctl.speed == 1000){
++		if(lp->dts_ctl.duplex == 1){
++			tmp = LPA_1000FULL;
++		}else if(lp->dts_ctl.duplex == 2){
++			tmp = LPA_1000HALF;
++		}
++	}
++	lp->virt_phy.reg[MII_STAT1000] = tmp;
++
++	/* 0xf Extended status reg*/
++	lp->virt_phy.reg[MII_ESTATUS] = ESTATUS_1000_TFULL | ESTATUS_1000_THALF;
++
++	return 0;
++}
++
++static ssize_t mac_reg_dump(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct net_device *net_dev = dev_get_drvdata(dev);
++	struct ingenic_mac_local *lp = netdev_priv(net_dev);
++
++	ingenic_mac_dump_all_regs(lp->gmacdev, __func__, __LINE__);
++
++	return 0;
++}
++
++static DEVICE_ATTR(mac_reg_dump, S_IRUGO|S_IWUSR, mac_reg_dump, NULL);
++static struct attribute *mac_debug_attrs[] = {
++	&dev_attr_mac_reg_dump.attr,
++	NULL,
++};
++
++const char mac_group_name[] = "debug";
++static struct attribute_group mac_debug_attr_group = {
++	.name	= mac_group_name,
++	.attrs	= mac_debug_attrs,
++};
++
++static int get_param_from_dts(struct ingenic_mac_local *lp)
++{
++	struct platform_device *pdev = lp->pdev;
++	struct device *dev = &pdev->dev;
++	struct device_node *np = dev->of_node;
++	unsigned int mode;
++	unsigned int force;
++	unsigned int autoneg;
++	unsigned int speed;
++	unsigned int duplex;
++	int rc;
++
++	rc = of_property_read_u32(np, "ingenic,mac-mode", &mode);
++	if (rc < 0) {
++		dev_err(&pdev->dev, "Get mac-mode value failed\n");
++		return rc;
++	}else{
++		lp->interface = mode;
++	}
++
++	rc = of_property_read_u32(np, "ingenic,mac-force", &force);
++	if (rc < 0)
++		lp->dts_ctl.force = 0;
++	else
++		lp->dts_ctl.force = force;
++
++	rc = of_property_read_u32(np, "ingenic,mac-autoneg", &autoneg);
++	if (rc < 0)
++		lp->dts_ctl.autoneg = 0;
++	else
++		lp->dts_ctl.autoneg = autoneg;
++
++	rc = of_property_read_u32(np, "ingenic,mac-speed", &speed);
++	if (rc < 0)
++		lp->dts_ctl.speed = 0;
++	else
++		lp->dts_ctl.speed = speed;
++
++	rc = of_property_read_u32(np, "ingenic,mac-duplex", &duplex);
++	if (rc < 0)
++		lp->dts_ctl.duplex = 0;
++	else
++		lp->dts_ctl.duplex = duplex;
++
++	if (of_property_read_bool(pdev->dev.of_node, "ingenic,no_phy_connect"))
++		lp->no_phy_connect = true;
++	else
++		lp->no_phy_connect = false;
++
++	return 0;
++}
++
++static int ingenic_mac_probe(struct platform_device *pdev)
++{
++	synopGMACdevice *gmacdev;
++	struct resource *r_mem = NULL;
++	struct net_device *ndev = NULL;
++	struct device_node *child = NULL;
++	struct ingenic_mac_local *lp;
++	const struct of_device_id *match;
++	const struct ingenic_gmac_priv *priv;
++	struct mii_bus *miibus;
++	char clk_gate_name[16];
++	char clk_cgu_name[16];
++	unsigned int phy_clk_freq;
++	int rc = 0, i;
++
++	r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!r_mem) {
++		dev_err(&pdev->dev, "no IO resource defined.\n");
++		return -ENXIO;
++	}
++
++	gmacdev = devm_kzalloc(&pdev->dev, sizeof (synopGMACdevice), GFP_KERNEL);
++	if(!gmacdev)
++		return -ENOMEM;
++
++	ndev = alloc_etherdev(sizeof(struct ingenic_mac_local));
++	if (!ndev) {
++		dev_err(&pdev->dev, "Cannot allocate net device!\n");
++		return -ENOMEM;
++	}
++	pdev->id = of_alias_get_id(pdev->dev.of_node, "mac");
++	SET_NETDEV_DEV(ndev, &pdev->dev);
++	platform_set_drvdata(pdev, ndev);
++	lp = netdev_priv(ndev);
++	lp->netdev = ndev;
++	lp->pdev = pdev;
++	lp->gmacdev = gmacdev;
++	lp->id = pdev->id;
++	lp->interface = RMII;
++	lp->netdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
++	lp->netdev->dev.dma_mask = &lp->netdev->dev.coherent_dma_mask;
++	lp->msg_enable = netif_msg_init(msg_level, INGENIC_MAC_MSG_DEFAULT);
++
++	match = of_match_node(ingenic_mac_dt_match, pdev->dev.of_node);
++	if (!match) {
++		rc = -ENODEV;
++		goto err_out_free_netdev;
++	}
++	priv = match->data;
++
++	lp->baseaddr = devm_ioremap_resource(&pdev->dev, r_mem);
++	if (IS_ERR(lp->baseaddr)) {
++		dev_err(&pdev->dev, "failed to map baseaddress.\n");
++		rc = PTR_ERR(lp->baseaddr);
++		goto err_out_free_netdev;
++	}
++
++	gmacdev->DmaBase = (u32)lp->baseaddr + DMABASE;
++	gmacdev->MacBase = (u32)lp->baseaddr + MACBASE;
++
++	rc = get_param_from_dts(lp);
++	if(rc < 0){
++		goto err_out_free_netdev;
++	}
++
++	if(lp->no_phy_connect){
++		rc = ingenic_mac_virtual_phy_init(lp);
++		if (rc < 0) {
++			dev_err(&pdev->dev, "virtual phy init failed\n");
++			goto err_out_free_netdev;
++		}
++	}
++
++	if(priv->support_multi_if) {
++		rc = ingenic_mac_interface_init(lp);
++		if (rc < 0) {
++			dev_err(&pdev->dev, "Interface init failed\n");
++			goto err_out_free_netdev;
++		}
++	}
++
++	priv->get_clk_name(lp, clk_gate_name, clk_cgu_name);
++	lp->clk_gate = devm_clk_get(&pdev->dev, clk_gate_name);
++	if (IS_ERR(lp->clk_gate)) {
++		rc = PTR_ERR(lp->clk_gate);
++		dev_err(&pdev->dev, "%s:can't get clk %s\n", __func__,clk_gate_name);
++		goto err_out_free_netdev;
++	}
++	lp->clk_cgu = devm_clk_get(&pdev->dev, clk_cgu_name);
++	if (IS_ERR(lp->clk_cgu)) {
++		rc = PTR_ERR(lp->clk_cgu);
++		dev_err(&pdev->dev, "%s:can't get clk %s\n", __func__,clk_cgu_name);
++		goto err_out_clk_gate_put;
++	}
++
++	if ((rc = clk_prepare_enable(lp->clk_gate)) < 0) {
++		dev_err(&pdev->dev, "Enable gmac gate clk failed\n");
++		goto err_out_clk_cgu_put;
++	}
++
++	rc = of_property_read_u32(pdev->dev.of_node, "ingenic,phy-clk-freq", &phy_clk_freq);
++	if (rc < 0) {
++		phy_clk_freq = 50000000;
++	}
++
++	if (clk_set_rate(lp->clk_cgu, phy_clk_freq) || (clk_prepare_enable(lp->clk_cgu))) {
++		dev_err(&pdev->dev, "Set cgu_mac clk rate faild\n");
++		rc = -ENODEV;
++		goto err_out_clk_gate_disable;
++	}
++
++	if(lp->interface == RGMII) {
++		char clk_name[16];
++		sprintf(clk_name, "div_mactxphy%d", pdev->id);
++		lp->clk_tx = devm_clk_get(&pdev->dev, clk_name);
++		if (IS_ERR(lp->clk_tx)) {
++			rc = PTR_ERR(lp->clk_tx);
++			dev_err(&pdev->dev, "%s:can't get clk %s\n", __func__,clk_name);
++			goto err_out_clk_cgu_disable;
++		}
++		if (clk_set_rate(lp->clk_tx, 125000000) || (clk_prepare_enable(lp->clk_tx))) {
++			dev_err(&pdev->dev, "Set tx clk rate faild\n");
++			rc = -ENODEV;
++			goto err_out_clk_tx_put;
++		}
++	}
++
++	if (ingenic_mac_phy_hwrst(pdev, true)) {
++		rc = -ENODEV;
++		goto err_out_clk_tx_disable;
++	}
++
++	synopGMAC_disable_interrupt_all(gmacdev);
++
++	if (!!(child = of_get_child_by_name(pdev->dev.of_node, "mdio-gpio")) &&
++			of_device_is_available(child)) {
++		if (!(lp->mii_pdev = of_platform_device_create(child, NULL, &pdev->dev))) {
++			rc = -ENODEV;
++			goto err_out_clk_cgu_disable;
++		}
++		lp->use_mdio_goio = true;
++		lp->mii_bus = platform_get_drvdata(lp->mii_pdev);
++	} else {
++		lp->use_mdio_goio = false;
++		if (!(miibus = devm_mdiobus_alloc(&pdev->dev))) {
++			rc = -ENOMEM;
++			goto err_out_clk_cgu_disable;
++		}
++		miibus->priv = lp;
++		miibus->read = ingenic_mdiobus_read;
++		miibus->write = ingenic_mdiobus_write;
++		miibus->reset = ingenic_mdiobus_reset;
++		miibus->parent = &pdev->dev;
++		miibus->name = "ingenic_mii_bus";
++		snprintf(miibus->id, MII_BUS_ID_SIZE, "%d", lp->id);
++		for (i = 0; i < PHY_MAX_ADDR; ++i)
++			miibus->irq[i] = PHY_POLL;
++
++		/* init MDC CLK */
++		ingenic_set_mdc_rate(lp);
++
++		rc = mdiobus_register(miibus);
++		if (rc) {
++			dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
++			goto err_out_clk_cgu_disable;
++		}
++		lp->mii_bus = miibus;
++	}
++
++	/*Lets read the version of ip in to device structure*/
++	synopGMAC_read_version(gmacdev);
++
++	/* configure MAC address */
++	if (bootargs_ethaddr[pdev->id]) {
++		for (i=0; i<6; i++) {
++			ndev->dev_addr[i] = ethaddr_hex[pdev->id][i];
++		}
++	} else {
++		random_ether_addr(ndev->dev_addr);
++	}
++	setup_mac_addr(gmacdev, ndev->dev_addr);
++
++	rc = mii_probe(ndev);
++	if (rc) {
++		dev_err(&pdev->dev, "MII Probe failed!\n");
++		goto err_out_miibus_unregister;
++	}
++
++	/* Fill in the fields of the device structure with ethernet values. */
++	ether_setup(ndev);
++
++	ndev->netdev_ops = &ingenic_mac_netdev_ops;
++	ingenic_mac_set_ethtool_ops(ndev);
++
++	ndev->watchdog_timeo = 2 * HZ;
++
++	lp->mii.phy_id	= lp->phydev->mdio.addr;
++	lp->mii.phy_id_mask  = 0x1f;
++	lp->mii.reg_num_mask = 0x1f;
++	lp->mii.dev	= ndev;
++	lp->mii.mdio_read    = ingenic_mdio_phy_read;
++	lp->mii.mdio_write   = ingenic_mdio_phy_write;
++	lp->mii.supports_gmii	= mii_check_gmii_support(&lp->mii);
++
++	timer_setup(&lp->watchdog_timer, ingenic_mac_watchdog, 0);
++
++	netif_napi_add(ndev, &lp->napi, ingenic_mac_clean, 32);
++
++#if 0
++	hrtimer_init(&lp->rx_coalesce_timer, CLOCK_MONOTONIC, HRTIMER_MODE_PINNED);
++	lp->rx_coalesce_usecs = 200;
++	lp->rx_coalesce_timer.function = ingenic_rx_coalesce_timer_done;
++#endif
++
++	hrtimer_init(&lp->tx_coalesce_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
++	lp->tx_coalesce_usecs = 300;
++	lp->tx_coalesce_timer.function = ingenic_tx_coalesce_timer_done;
++
++	spin_lock_init(&lp->link_lock);
++	spin_lock_init(&lp->napi_poll_lock);
++	spin_lock_init(&lp->hw_lock);
++#ifdef CONFIG_INGENIC_GMAC_MUTUAL_TRANS
++	spin_lock_init(&napi_poll_lock);
++	spin_lock_init(&record_lock);
++	lp_record[lp->id] = lp;
++#endif
++
++	INIT_WORK(&lp->reset_task, ingenic_mac_reset_task);
++
++	/* register irq handler */
++	rc = platform_get_irq(pdev, 0);
++	if (rc < 0)
++		goto err_out_miibus_unregister;
++
++	rc = devm_request_irq(&pdev->dev, rc, ingenic_mac_interrupt, 0, dev_name(&pdev->dev), ndev);
++	if (rc) {
++		dev_err(&pdev->dev, "Cannot request ingenic MAC IRQ!\n");
++		rc = -EBUSY;
++		goto err_out_miibus_unregister;
++	}
++
++#ifdef CONFIG_INGENIC_GMAC_USE_HWSTAMP
++	rc = ingenic_phc_init(ndev, &pdev->dev);
++	if (rc) {
++		dev_err(&pdev->dev, "Cannot register PHC device!\n");
++		goto err_out_miibus_unregister;
++	}
++#endif
++
++	sprintf(ndev->name, "eth%d", lp->id);
++	rc = register_netdev(ndev);
++	if (rc) {
++		dev_err(&pdev->dev, "Cannot register net device!\n");
++		goto err_out_miibus_unregister;
++	}
++
++	sysfs_create_group(&(pdev->dev.kobj), &mac_debug_attr_group);
++
++	dev_info(&pdev->dev, "%s, Version %s\n", INGENIC_MAC_DRV_DESC, INGENIC_MAC_DRV_VERSION);
++	return 0;
++
++err_out_miibus_unregister:
++	if (lp->use_mdio_goio)
++		platform_device_unregister(lp->mii_pdev);
++	else
++		mdiobus_unregister(lp->mii_bus);
++err_out_clk_tx_disable:
++	if(lp->interface == RGMII)
++		clk_disable_unprepare(lp->clk_tx);
++err_out_clk_tx_put:
++	if(lp->interface == RGMII)
++		devm_clk_put(&pdev->dev, lp->clk_tx);
++err_out_clk_cgu_disable:
++	clk_disable_unprepare(lp->clk_cgu);
++err_out_clk_gate_disable:
++	clk_disable_unprepare(lp->clk_gate);
++err_out_clk_cgu_put:
++		devm_clk_put(&pdev->dev, lp->clk_cgu);
++err_out_clk_gate_put:
++		devm_clk_put(&pdev->dev, lp->clk_gate);
++err_out_free_netdev:
++	platform_set_drvdata(pdev, NULL);
++	free_netdev(ndev);
++	return rc;
++}
++
++static int  ingenic_mac_remove(struct platform_device *pdev)
++{
++	struct net_device *ndev = platform_get_drvdata(pdev);
++	struct ingenic_mac_local *lp = netdev_priv(ndev);
++
++	unregister_netdev(ndev);
++
++	if (lp->use_mdio_goio)
++		platform_device_unregister(lp->mii_pdev);
++	else
++		mdiobus_unregister(lp->mii_bus);
++
++	clk_disable_unprepare(lp->clk_cgu);
++
++	clk_disable_unprepare(lp->clk_gate);
++
++#ifdef CONFIG_INGENIC_GMAC_USE_HWSTAMP
++	ingenic_phc_release(lp);
++#endif
++
++	platform_set_drvdata(pdev, NULL);
++
++	free_netdev(ndev);
++
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int ingenic_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
++{
++	struct net_device *net_dev = platform_get_drvdata(pdev);
++	struct ingenic_mac_local *lp = netdev_priv(net_dev);
++
++	if (netif_running(net_dev))
++		ingenic_mac_close(net_dev);
++
++	clk_disable_unprepare(lp->clk_cgu);
++
++	clk_disable_unprepare(lp->clk_gate);
++
++	if(lp->interface == RGMII)
++		clk_disable_unprepare(lp->clk_tx);
++
++	return 0;
++}
++
++static int ingenic_mac_resume(struct platform_device *pdev)
++{
++	struct net_device *net_dev = platform_get_drvdata(pdev);
++	struct ingenic_mac_local *lp = netdev_priv(net_dev);
++
++	clk_prepare_enable(lp->clk_gate);
++	clk_prepare_enable(lp->clk_cgu);
++	if(lp->interface == RGMII)
++		clk_prepare_enable(lp->clk_tx);
++
++	if (netif_running(net_dev))
++		ingenic_mac_open(net_dev);
++
++	return 0;
++}
++#else
++#define ingenic_mac_suspend NULL
++#define ingenic_mac_resume NULL
++#endif	/* CONFIG_PM */
++
++void get_clk_name_v1(struct ingenic_mac_local *lp, char *gate_name, char *cgu_name)
++{
++	sprintf(gate_name, "gate_mac");
++	sprintf(cgu_name, "cgu_mac");
++}
++
++void get_clk_name_v2(struct ingenic_mac_local *lp, char *gate_name, char *cgu_name)
++{
++	struct platform_device *pdev = lp->pdev;
++	sprintf(gate_name, "gate_gmac%d", pdev->id);
++	sprintf(cgu_name, "div_macphy");
++}
++
++void get_clk_name_v3(struct ingenic_mac_local *lp, char *gate_name, char *cgu_name)
++{
++	sprintf(gate_name, "gate_gmac");
++	sprintf(cgu_name, "div_macphy");
++}
++struct ingenic_gmac_priv x1000_priv = {
++	.support_multi_if = 0,
++	.get_clk_name = get_clk_name_v1,
++};
++
++struct ingenic_gmac_priv x1021_priv = {
++	.support_multi_if = 0,
++	.get_clk_name = get_clk_name_v1,
++};
++
++struct ingenic_gmac_priv x1630_priv = {
++	.support_multi_if = 0,
++	.get_clk_name = get_clk_name_v1,
++};
++
++struct ingenic_gmac_priv x2000_priv = {
++	.support_multi_if = 1,
++	.get_clk_name = get_clk_name_v2,
++};
++
++struct ingenic_gmac_priv x2500_priv = {
++	.support_multi_if = 0,
++	.get_clk_name = get_clk_name_v3,
++};
++
++struct ingenic_gmac_priv m300_priv = {
++	.support_multi_if = 1,
++	.get_clk_name = get_clk_name_v2,
++};
++
++struct ingenic_gmac_priv x1600_priv = {
++	.support_multi_if = 0,
++	.get_clk_name = get_clk_name_v2,
++};
++
++static const struct of_device_id ingenic_mac_dt_match[] = {
++	{ .compatible = "ingenic,x1000-mac", .data = &x1000_priv },
++	{ .compatible = "ingenic,x1021-mac", .data = &x1021_priv },
++	{ .compatible = "ingenic,x1630-mac", .data = &x1630_priv },
++	{ .compatible = "ingenic,x2000-mac", .data = &x2000_priv },
++	{ .compatible = "ingenic,x2500-mac", .data = &x2500_priv },
++	{ .compatible = "ingenic,m300-mac", .data = &m300_priv },
++	{ .compatible = "ingenic,x1600-mac", .data = &x1600_priv },
++	{},
++};
++
++MODULE_DEVICE_TABLE(of, ingenic_mac_dt_match);
++
++static struct platform_driver ingenic_mac_driver = {
++	.driver = {
++		.name = INGENIC_MAC_DRV_NAME,
++		.owner	= THIS_MODULE,
++		.of_match_table = of_match_ptr(ingenic_mac_dt_match),
++	},
++	.probe = ingenic_mac_probe,
++	.remove = ingenic_mac_remove,
++	.resume = ingenic_mac_resume,
++	.suspend = ingenic_mac_suspend,
++};
++module_platform_driver(ingenic_mac_driver)
+diff --git a/module_drivers/drivers/net/ethernet/ingenic/ingenic_mac.h b/module_drivers/drivers/net/ethernet/ingenic/ingenic_mac.h
+new file mode 100644
+index 000000000..405f81ec0
+--- /dev/null
++++ b/module_drivers/drivers/net/ethernet/ingenic/ingenic_mac.h
+@@ -0,0 +1,194 @@
++#ifndef __INGENIC_MAC_H__
++#define __INGENIC_MAC_H__
++
++
++#include <linux/net_tstamp.h>
++#include <linux/ptp_clock_kernel.h>
++#include <linux/timer.h>
++#include <linux/mii.h>
++#include "synopGMAC_Dev.h"
++
++/* wrapper around a pointer to a socket buffer,
++ * so a DMA handle can be stored along with the buffer */
++struct ingenic_mac_buffer {
++	struct sk_buff *skb;
++	dma_addr_t dma;
++	unsigned long time_stamp;
++	u16 length;
++	volatile u8 transfering; /* used by tx */
++	volatile u8 invalid;	 /* used by rx */
++	u16 mapped_as_page;
++	unsigned int segs;
++};
++
++#define INGENIC_MAC_DRV_NAME		"dwc-mac"
++#define INGENIC_MAC_DRV_VERSION		"1.0"
++#define INGENIC_MAC_DRV_DESC		"Ingenic on-chip Ethernet MAC driver"
++
++#define INGENIC_MAC_MSG_DEFAULT     (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
++
++
++/* TX/RX descriptor defines */
++#define INGENIC_MAC_TX_DESC_COUNT                128
++#define INGENIC_MAC_MAX_TXD                      256
++#define INGENIC_MAC_MIN_TXD                       80
++
++#define INGENIC_MAC_RX_DESC_COUNT                CONFIG_INGENIC_GMAC_RX_DESC_COUNT
++#define INGENIC_MAC_MAX_RXD                      10240
++#define INGENIC_MAC_MIN_RXD                       80
++
++#define INGENIC_RX_MAX_COALESCE_USECS	200
++#define INGENIC_RX_MIN_COALESCE_USECS	100
++#define INGENIC_TX_MAX_COALESCE_USECS	2000
++#define INGENIC_TX_MIN_COALESCE_USECS	200
++
++#define INGENIC_WAKE_IRQ_NUM		20000
++
++struct ingenic_mac_tx_ring {
++	/* pointer to the descriptor ring memory */
++	DmaDesc *desc;
++	/* physical address of the descriptor ring */
++	dma_addr_t dma;
++	/* number of descriptors in the ring */
++	unsigned int count;
++	/* next descriptor to associate a buffer with */
++	unsigned int next_to_use;
++	/* next descriptor to check for trans done status */
++	unsigned int next_to_clean;
++	/* array of buffer information structs */
++	struct ingenic_mac_buffer *buffer_info;
++};
++
++struct ingenic_mac_rx_ring {
++	/* pointer to the descriptor ring memory */
++	DmaDesc *desc;
++	/* physical address of the descriptor ring */
++	dma_addr_t dma;
++	/* number of descriptors in the ring */
++	unsigned int count;
++	/* next descriptor to associate a buffer with */
++	unsigned int next_to_use;
++	/* next descriptor to check for DD status bit */
++	unsigned int next_to_clean;
++	/* array of buffer information structs */
++	struct ingenic_mac_buffer *buffer_info;
++};
++
++#define INGENIC_MAC_DESC_UNUSED(R)						\
++	((((R)->next_to_clean > (R)->next_to_use)			\
++	  ? 0 : (R)->count) + (R)->next_to_clean - (R)->next_to_use - 1)
++
++#define INGENIC_MAC_DESC_USED(R)  (((R)->count - 1) - INGENIC_MAC_DESC_UNUSED(R))
++
++#define INGENIC_MAC_GET_DESC(R, i)	(&(((DmaDesc *)((R).desc))[i]))
++#define INGENIC_MAC_RX_DESC(R, i)		INGENIC_MAC_GET_DESC(R, i)
++#define INGENIC_MAC_TX_DESC(R, i)		INGENIC_MAC_GET_DESC(R, i)
++
++struct ingenic_mac_flowcontrol {
++	int autoneg;
++	int rx;
++	int rx_current;
++	int tx;
++	int tx_current;
++};
++
++struct ingenic_mac_dts_control {
++	unsigned int force;
++	unsigned int autoneg;
++	unsigned int speed;
++	unsigned int duplex;
++};
++
++struct virtual_phy{
++	u16 reg[MII_NCONFIG + 1];
++};
++
++struct ingenic_mac_local {
++	struct clk *clk_gate;
++	struct clk *clk_cgu;
++	struct clk *clk_tx;
++	void __iomem *baseaddr;
++
++	struct ingenic_mac_tx_ring tx_ring;
++	unsigned int restart_queue;
++	u32 tx_timeout_count;
++
++	struct timer_list watchdog_timer;
++	struct ingenic_mac_rx_ring rx_ring;
++
++	struct napi_struct napi;
++	spinlock_t napi_poll_lock;
++
++	struct net_device *netdev;
++	struct platform_device *pdev;
++	struct net_device_stats net_stats;
++
++	spinlock_t stats_lock;
++
++	atomic_t tx_fifo_used;
++
++	unsigned char Mac[6];	/* MAC address of the board */
++	spinlock_t link_lock;
++
++	/* MII and PHY stuffs */
++	int old_link;
++	int old_speed;
++	int old_duplex;
++
++	bool no_phy_connect;
++	struct phy_device *phydev;
++	struct mii_bus *mii_bus;
++	bool use_mdio_goio;
++	struct platform_device *mii_pdev;
++
++	u32 alloc_rx_buff_failed;
++
++	struct work_struct reset_task;
++	struct mii_if_info mii;
++
++	u32 msg_enable;
++	struct ingenic_mac_flowcontrol flowcontrol;
++	/* Spinlock for register read-modify-writes. */
++	spinlock_t hw_lock;
++
++	/*power*/
++	int pwr_gpio;
++	u32 pwr_lvl;
++
++	/*hw reset*/
++	u32 reset_ms;
++	u32 reset_delay_ms;
++	int reset_gpio;
++	u32 reset_lvl;
++	int id;
++
++	synopGMACdevice *gmacdev;
++	unsigned int interface;
++	struct ingenic_mac_dts_control dts_ctl;
++	struct virtual_phy virt_phy;
++
++	int rx_coalesce_usecs;
++	struct hrtimer rx_coalesce_timer;
++	int tx_coalesce_usecs;
++	struct hrtimer tx_coalesce_timer;
++	unsigned long wake_irq_num;
++
++#ifdef CONFIG_INGENIC_GMAC_USE_HWSTAMP
++	struct hwtstamp_config stamp_cfg;
++	struct ptp_clock_info caps;
++	struct ptp_clock *clock;
++	struct clk *cgu_ptp;
++	int phc_index;
++	u32 ptp_addend;
++	u32 ptp_freq;
++	spinlock_t phc_lock;
++#endif
++};
++
++struct ingenic_gmac_priv {
++	unsigned int support_multi_if;
++	void (*get_clk_name)(struct ingenic_mac_local *lp, char *gate_name, char *cgu_name);
++};
++
++void ingenic_mac_set_ethtool_ops(struct net_device *netdev);
++#endif	/* __INGENIC_MAC_H__ */
+diff --git a/module_drivers/drivers/net/ethernet/ingenic/readme b/module_drivers/drivers/net/ethernet/ingenic/readme
+new file mode 100644
+index 000000000..a9228c7f5
+--- /dev/null
++++ b/module_drivers/drivers/net/ethernet/ingenic/readme
+@@ -0,0 +1,26 @@
++*************************************README***************************************
++
++
++**********************************************************************************
++
++This is a README file for the sample device driver software for Synopsys Universal
++GMAC IP. The files listed below are available in this directory.
++
++./README (this file)
++./synopGMAC_banner.h
++./synopGMAC_plat.c
++./synopGMAC_plat.h
++./synopGMAC_Dev.c
++./synopGMAC_Dev.h
++./synopGMAC_network_interface.c
++./synopGMAC_network_interface.h
++./synopGMAC_Host.c
++./synopGMAC_Host.h
++./Makefile
++./synopGMAC_Debug.c
++./synopGMAC_driver_ug.pdf
++
++The User Guide (synopGMAC_driver_ug.pdf) provides details about driver architecture, flow
++diagrams and driver APIs. Please refer to compilation subsection of chapter 1 to compile
++the driver and the debug utility. The same section explains how to use the kernel module
++in Linux platform.
+diff --git a/module_drivers/drivers/net/ethernet/ingenic/synopGMAC_Dev.c b/module_drivers/drivers/net/ethernet/ingenic/synopGMAC_Dev.c
+new file mode 100644
+index 000000000..4a951391f
+--- /dev/null
++++ b/module_drivers/drivers/net/ethernet/ingenic/synopGMAC_Dev.c
+@@ -0,0 +1,3839 @@
++/* ===================================================================================
++ * Copyright (c) <2009> Synopsys, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a copy of
++ * this software annotated with this license and associated documentation files
++ * (the "Software"), to deal in the Software without restriction, including without
++ * limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the Software is
++ * furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in all
++ * copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * =================================================================================== */
++
++/** \file
++ * This file defines the synopsys GMAC device dependent functions.
++ * Most of the operations on the GMAC device are available in this file.
++ * Functions for initiliasing and accessing MAC/DMA/PHY registers and the DMA descriptors
++ * are encapsulated in this file. The functions are platform/host/OS independent.
++ * These functions in turn use the low level device dependent (HAL) functions to
++ * access the register space.
++ * \internal
++ * ------------------------REVISION HISTORY---------------------------------
++ * Synopsys                 01/Aug/2007                              Created
++ */
++#include "synopGMAC_Dev.h"
++
++/**
++ * Function to set the MDC clock for mdio transactiona
++ *
++ * @param[in] pointer to device structure.
++ * @param[in] clk divider value.
++ * \return Reuturns 0 on success else return the error value.
++ */
++s32 synopGMAC_set_mdc_clk_div(synopGMACdevice *gmacdev,u32 clk_div_val)
++{
++	u32 orig_data;
++	int times = 100;
++	while(((orig_data = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacGmiiAddr)) & GmiiBusy) && (times-- > 0)) {
++		printk("===>PHY busy!\n");
++	}
++	orig_data &= (~ GmiiCsrClkMask);
++	orig_data |= clk_div_val;
++	synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacGmiiAddr ,orig_data);
++	return 0;
++}
++
++/**
++ * Returns the current MDC divider value programmed in the ip.
++ *
++ * @param[in] pointer to device structure.
++ * @param[in] clk divider value.
++ * \return Returns the MDC divider value read.
++ */
++u32 synopGMAC_get_mdc_clk_div(synopGMACdevice *gmacdev)
++{
++	u32 data;
++	data = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacGmiiAddr);
++	data &= GmiiCsrClkMask;
++	return data;
++}
++
++/**
++ * struct GmiiCsrDiv
++ */
++typedef struct GmiiCisrDivStruct {
++	u32 CsrClkDiv;
++	u32 CsrRegValue;
++} GmiiCsrDiv;
++
++/**
++ * GmacCsrDivArray
++ *
++ * Note:
++ *	GmacCsrDivArray is descending order baseed on
++ *	GmacCsrDivArray.CsrClkDiv.
++ */
++static GmiiCsrDiv GmacCsrDivArray[] = {
++	{ 124, GmiiCsrClk5 }, /* sysclk is 250-300 MHz */
++	{ 102, GmiiCsrClk4 }, /* sysclk is 150-250 MHz */
++	{ 62, GmiiCsrClk1 }, /* sysclk is 100-150 MHz */
++	{ 42, GmiiCsrClk0 }, /* sysclk is 60-100 MHz */
++	{ 26, GmiiCsrClk3 }, /* sysclk is 35-60 MHz */
++	{ 16, GmiiCsrClk2 }, /* sysclk is 20-35 MHz */
++	{ 14, 0x00000034 },
++	{ 12, 0x00000030 },
++	{ 10, 0x0000002C },
++	{ 8, 0x00000028 },
++	{ 6, 0x00000024 },
++	{ 4, 0x00000020 },
++};
++
++/**
++ * Function to Calculate the GMIIAddressRegister.CR[5:2] right value
++ * @sysclk[in]
++ * @max_mdcclk[in]
++ * \return Returns 0xFFFFFFFF on out of band else return a rigth value.
++ */
++u32 synopGMAC_calculate_mdc_clk_csr(u32 sysclk, u32 max_mdcclk)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(GmacCsrDivArray); i++) {
++		if (sysclk > max_mdcclk * GmacCsrDivArray[i].CsrClkDiv)
++			return i ? GmacCsrDivArray[i - 1].CsrRegValue : ~(u32)0;
++	}
++
++	return GmacCsrDivArray[i - 1].CsrRegValue;
++}
++
++
++/**
++ * Function to read the Phy register. The access to phy register
++ * is a slow process as the data is moved accross MDI/MDO interface
++ * @param[in] pointer to Register Base (It is the mac base in our case) .
++ * @param[in] PhyBase register is the index of one of supported 32 PHY devices.
++ * @param[in] Register offset is the index of one of the 32 phy register.
++ * @param[out] u16 data read from the respective phy register (only valid iff return value is 0).
++ * \return Returns 0 on success else return the error status.
++ */
++s32 synopGMAC_read_phy_reg(synopGMACdevice *gmacdev, u32 PhyBase, u32 RegOffset, u16 * data)
++{
++	u32 addr = 0;
++	u32 loop_variable = 0;
++	u32 *RegBase = (u32 *)gmacdev->MacBase;
++	int times = 100;
++
++	while((synopGMACReadReg(RegBase,GmacGmiiAddr) & GmiiBusy) && (times-- > 0)) {
++		printk("===>PHY busy!\n");
++	}
++
++	addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask);
++	addr = addr | (gmacdev->ClockDivMdc) | GmiiBusy; //Gmii busy bit
++
++	// printk("====>PHY: addr = 0x%08x\n", addr);
++
++	synopGMACWriteReg(RegBase,GmacGmiiAddr,addr); //write the address from where the data to be read in GmiiGmiiAddr register of synopGMAC ip
++
++	for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
++		if (!(synopGMACReadReg(RegBase,GmacGmiiAddr) & GmiiBusy)){
++			break;
++		}
++		plat_delay(DEFAULT_DELAY_VARIABLE);
++	}
++	if(loop_variable < DEFAULT_LOOP_VARIABLE) {
++		*data = (u16)(synopGMACReadReg(RegBase,GmacGmiiData) & 0xFFFF);
++		// printk("======>PHY: data = 0x%04x\n", *data);
++	} else{
++		printk("====>Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n");
++		return -ESYNOPGMACPHYERR;
++	}
++	return -ESYNOPGMACNOERR;
++}
++
++/**
++ * Function to write to the Phy register. The access to phy register
++ * is a slow process as the data is moved accross MDI/MDO interface
++ * @param[in] pointer to Register Base (It is the mac base in our case) .
++ * @param[in] PhyBase register is the index of one of supported 32 PHY devices.
++ * @param[in] Register offset is the index of one of the 32 phy register.
++ * @param[in] data to be written to the respective phy register.
++ * \return Returns 0 on success else return the error status.
++ */
++s32 synopGMAC_write_phy_reg(synopGMACdevice *gmacdev, u32 PhyBase, u32 RegOffset, u16 data)
++{
++	u32 addr;
++	u32 loop_variable;
++	u32 *RegBase = (u32 *)gmacdev->MacBase;
++	int times = 100;
++
++	while((synopGMACReadReg(RegBase,GmacGmiiAddr) & GmiiBusy) && (times-- > 0)) {
++		printk("===>PHY busy!\n");
++	}
++	synopGMACWriteReg(RegBase,GmacGmiiData,data); // write the data in to GmacGmiiData register of synopGMAC ip
++	addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask) | GmiiWrite;
++
++	addr = addr | (gmacdev->ClockDivMdc) | GmiiBusy ; //set Gmii clk to 20-35 Mhz and Gmii busy bit
++
++	times = 100;
++	while((synopGMACReadReg(RegBase,GmacGmiiAddr) & GmiiBusy) && (times-- > 0)) {
++		printk("===>PHY busy!\n");
++	}
++	synopGMACWriteReg(RegBase,GmacGmiiAddr,addr);
++	for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){
++		if (!(synopGMACReadReg(RegBase,GmacGmiiAddr) & GmiiBusy)){
++			break;
++		}
++		plat_delay(DEFAULT_DELAY_VARIABLE);
++	}
++
++	if(loop_variable < DEFAULT_LOOP_VARIABLE){
++		return -ESYNOPGMACNOERR;
++	}
++	else{
++		TR("Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n");
++		return -ESYNOPGMACPHYERR;
++	}
++}
++
++/**
++ * Function to configure the phy in loopback mode.
++ *
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] enable or disable the loopback.
++ * \return 0 on success else return the error status.
++ * \note Don't get confused with mac loop-back synopGMAC_loopback_on(synopGMACdevice *)
++ * and synopGMAC_loopback_off(synopGMACdevice *) functions.
++ */
++s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev, bool loopback)
++{
++	s32 status = -ESYNOPGMACNOERR;
++	if(loopback)
++		status = synopGMAC_write_phy_reg(gmacdev, gmacdev->PhyBase, PHY_CONTROL_REG, Mii_Loopback);
++	else
++		status = synopGMAC_write_phy_reg(gmacdev, gmacdev->PhyBase, PHY_CONTROL_REG, Mii_NoLoopback);
++
++	return status;
++}
++
++
++
++/**
++ * Function to read the GMAC IP Version and populates the same in device data structure.
++ * @param[in] pointer to synopGMACdevice.
++ * \return Always return 0.
++ */
++
++s32 synopGMAC_read_version (synopGMACdevice * gmacdev)
++{
++	u32 data = 0;
++	data = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacVersion );
++	gmacdev->Version = data;
++	TR("The data read from %08x is %08x\n",(gmacdev->MacBase+GmacVersion),data);
++	return 0;
++}
++
++#include <linux/delay.h>
++
++/**
++ * Function to reset the GMAC core.
++ * This reests the DMA and GMAC core. After reset all the registers holds their respective reset value
++ * @param[in] pointer to synopGMACdevice.
++ * \return 0 on success else return the error status.
++ */
++s32 synopGMAC_reset (synopGMACdevice * gmacdev)
++{
++	u32 data = 0;
++	int cnt = 0;
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaBusMode ,DmaResetOn);
++	plat_delay(DEFAULT_LOOP_VARIABLE);
++
++	while (1) {
++		data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaBusMode);
++		TR("DATA after Reset = %08x\n",data);
++		if (data & DmaResetOn) {
++			if (cnt > 500) {
++				return -1;
++			}
++			if (cnt%100 == 0) {
++				printk("Bus Mode Reg after reset: 0x%08x, cnt=%d\n", data, cnt);
++			}
++
++			msleep(10);
++			cnt ++;
++		} else {
++			break;
++		}
++	}
++
++	return 0;
++}
++
++
++/**
++ * Function to program DMA bus mode register.
++ *
++ * The Bus Mode register is programmed with the value given. The bits to be set are
++ * bit wise or'ed and sent as the second argument to this function.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] the data to be programmed.
++ * \return 0 on success else return the error status.
++ */
++s32 synopGMAC_dma_bus_mode_init(synopGMACdevice * gmacdev, u32 init_value )
++{
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaBusMode ,init_value);
++	TR("bus_mode after init: 0x%08x\n", synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaBusMode));
++	return 0;
++
++}
++
++/**
++ * Function to program DMA Control register.
++ *
++ * The Dma Control register is programmed with the value given. The bits to be set are
++ * bit wise or'ed and sent as the second argument to this function.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] the data to be programmed.
++ * \return 0 on success else return the error status.
++ */
++s32 synopGMAC_dma_control_init(synopGMACdevice * gmacdev, u32 init_value)
++{
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaControl, init_value);
++	return 0;
++}
++
++
++/*Gmac configuration functions*/
++
++/**
++ * Enable the watchdog timer on the receiver.
++ * When enabled, Gmac enables Watchdog timer, and GMAC allows no more than
++ * 2048 bytes of data (10,240 if Jumbo frame enabled).
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_wd_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacWatchdog);
++	return;
++}
++/**
++ * Disable the watchdog timer on the receiver.
++ * When disabled, Gmac disabled watchdog timer, and can receive frames up to
++ * 16,384 bytes.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_wd_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacWatchdog);
++	return;
++}
++
++/**
++ * Enables the Jabber frame support.
++ * When cleared, GMAC enables jabber timer. It cuts of transmitter if application
++ * sends more than 2048 bytes of data (10240 if Jumbo frame enabled).
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_jab_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacJabber);
++	return;
++}
++/*
++ * Disables the Jabber frame support.
++ * When set, GMAC disabled the jabber timer, and can transfer 16,384 byte frames.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_jab_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacJabber);
++	return;
++}
++
++/**
++ * Enables Frame bursting (Only in Half Duplex Mode).
++ * When enabled, GMAC allows frame bursting in GMII Half Duplex mode.
++ * Reserved in 10/100 and Full-Duplex configurations.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_frame_burst_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacFrameBurst);
++	return;
++}
++/**
++ * Disables Frame bursting.
++ * When Disabled, frame bursting is not supported.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_frame_burst_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacFrameBurst);
++	return;
++}
++
++/**
++ * Enable Jumbo frame support.
++ * When Enabled GMAC supports jumbo frames of 9018/9022(VLAN tagged).
++ * Giant frame error is not reported in receive frame status.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_jumbo_frame_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacJumboFrame);
++	return;
++}
++
++/**
++ * Disable Jumbo frame support.
++ * When Disabled GMAC does not supports jumbo frames.
++ * Giant frame error is reported in receive frame status.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_jumbo_frame_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacJumboFrame);
++	return;
++}
++
++/**
++ *
++ */
++void synopGMAC_set_Inter_Frame_Gap(synopGMACdevice * gmacdev, u32 value)
++{
++	u32 data;
++	data = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacConfig);
++	data &= (~GmacInterFrameGap);
++	data |= value;
++	synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacConfig, data);
++	return;
++}
++
++/**
++ * Disable Carrier sense.
++ * When Disabled GMAC ignores CRS signal during frame transmission
++ * in half duplex mode.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++
++void synopGMAC_disable_crs(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacDisableCrs);
++	return;
++}
++
++
++
++/**
++ * Selects the GMII port.
++ * When called GMII (1000Mbps) port is selected (programmable only in 10/100/1000 Mbps configuration).
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_select_gmii(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacMiiGmii);
++	return;
++}
++/**
++ * Selects the MII port.
++ * When called MII (10/100Mbps) port is selected (programmable only in 10/100/1000 Mbps configuration).
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_select_mii(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacSelectMii);
++	return;
++}
++
++/**
++ * Select the Speed 1000 Mbps
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_select_speed1000(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacMiiGmii);
++	return;
++}
++
++
++/**
++ * Select the Speed 100 Mbps
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_select_speed100(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacFESpeed100 | GmacSelectMii);
++	return;
++}
++
++/**
++ * Select the Speed 10 Mbps
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_select_speed10(synopGMACdevice * gmacdev)
++{
++	u32 regVal;
++	regVal = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacConfig);
++	regVal |= GmacSelectMii;
++	regVal &= (~GmacFESpeed100);
++	synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacConfig, regVal);
++	return;
++}
++
++/**
++ * Enables Receive Own bit (Only in Half Duplex Mode).
++ * When enaled GMAC receives all the packets given by phy while transmitting.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_rx_own_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacRxOwn);
++	return;
++}
++/**
++ * Disables Receive Own bit (Only in Half Duplex Mode).
++ * When enaled GMAC disables the reception of frames when gmii_txen_o is asserted.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_rx_own_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacRxOwn);
++	return;
++}
++
++/**
++ * Sets the GMAC in loopback mode.
++ * When on GMAC operates in loop-back mode at GMII/MII.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ * \note (G)MII Receive clock is required for loopback to work properly, as transmit clock is
++ * not looped back internally.
++ */
++void synopGMAC_loopback_on(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacLoopback);
++	return;
++}
++/**
++ * Sets the GMAC in Normal mode.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_loopback_off(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacLoopback);
++	return;
++}
++
++/**
++ * Sets the GMAC core in Full-Duplex mode.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_set_full_duplex(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacDuplex);
++	return;
++}
++/**
++ * Sets the GMAC core in Half-Duplex mode.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_set_half_duplex(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacDuplex);
++	return;
++}
++
++/**
++ * GMAC tries retransmission (Only in Half Duplex mode).
++ * If collision occurs on the GMII/MII, GMAC attempt retries based on the
++ * back off limit configured.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ * \note This function is tightly coupled with synopGMAC_back_off_limit(synopGMACdev *, u32).
++ */
++void synopGMAC_retry_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacRetry);
++	return;
++}
++/**
++ * GMAC tries only one transmission (Only in Half Duplex mode).
++ * If collision occurs on the GMII/MII, GMAC will ignore the current frami
++ * transmission and report a frame abort with excessive collision in tranmit frame status.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_retry_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacRetry);
++	return;
++}
++
++/**
++ * GMAC strips the Pad/FCS field of incoming frames.
++ * This is true only if the length field value is less than or equal to
++ * 1500 bytes. All received frames with length field greater than or equal to
++ * 1501 bytes are passed to the application without stripping the Pad/FCS field.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_pad_crc_strip_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacPadCrcStrip);
++	return;
++}
++/**
++ * GMAC doesnot strips the Pad/FCS field of incoming frames.
++ * GMAC will pass all the incoming frames to Host unmodified.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_pad_crc_strip_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacPadCrcStrip);
++	return;
++}
++/**
++ * GMAC programmed with the back off limit value.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ * \note This function is tightly coupled with synopGMAC_retry_enable(synopGMACdevice * gmacdev)
++ */
++void synopGMAC_back_off_limit(synopGMACdevice * gmacdev, u32 value)
++{
++	u32 data;
++	data = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacConfig);
++	data &= (~GmacBackoffLimit);
++	data |= value;
++	synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacConfig,data);
++	return;
++}
++
++/**
++ * Enables the Deferral check in GMAC (Only in Half Duplex mode)
++ * GMAC issues a Frame Abort Status, along with the excessive deferral error bit set in the
++ * transmit frame status when transmit state machine is deferred for more than
++ * 	- 24,288 bit times in 10/100Mbps mode
++ * 	- 155,680 bit times in 1000Mbps mode or Jumbo frame mode in 10/100Mbps operation.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ * \note Deferral begins when transmitter is ready to transmit, but is prevented because  of
++ * an active CRS (carrier sense)
++ */
++void synopGMAC_deferral_check_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacDeferralCheck);
++	return;
++}
++/**
++ * Disables the Deferral check in GMAC (Only in Half Duplex mode).
++ * GMAC defers until the CRS signal goes inactive.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_deferral_check_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacDeferralCheck);
++	return;
++}
++/**
++ * Enable the reception of frames on GMII/MII.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_rx_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacRx);
++	return;
++}
++/**
++ * Disable the reception of frames on GMII/MII.
++ * GMAC receive state machine is disabled after completion of reception of current frame.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_rx_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacRx);
++	return;
++}
++/**
++ * Enable the transmission of frames on GMII/MII.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_tx_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacTx);
++	return;
++}
++/**
++ * Disable the transmission of frames on GMII/MII.
++ * GMAC transmit state machine is disabled after completion of transmission of current frame.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_tx_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacTx);
++	return;
++}
++
++
++/*Receive frame filter configuration functions*/
++
++/**
++ * Enables reception of all the frames to application.
++ * GMAC passes all the frames received to application irrespective of whether they
++ * pass SA/DA address filtering or not.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_frame_filter_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacFilter);
++	return;
++}
++/**
++ * Disables reception of all the frames to application.
++ * GMAC passes only those received frames to application which
++ * pass SA/DA address filtering.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_frame_filter_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacFilter);
++	return;
++}
++
++/**
++ * Populates the Hash High register with the data supplied.
++ * This function is called when the Hash filtering is to be enabled.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] data to be written to hash table high register.
++ * \return void.
++ */
++void synopGMAC_write_hash_table_high(synopGMACdevice * gmacdev, u32 data)
++{
++	synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacHashHigh,data);
++	return;
++}
++
++/**
++ * Populates the Hash Low register with the data supplied.
++ * This function is called when the Hash filtering is to be enabled.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] data to be written to hash table low register.
++ * \return void.
++ */
++void synopGMAC_write_hash_table_low(synopGMACdevice * gmacdev, u32 data)
++{
++	synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacHashLow,data);
++	return;
++}
++
++/**
++ * Enables Hash or Perfect filter (only if Hash filter is enabled in H/W).
++ * Only frames matching either perfect filtering or Hash Filtering as per HMC and HUC
++ * configuration are sent to application.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_hash_perfect_filter_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacHashPerfectFilter);
++	return;
++}
++
++/**
++ * Enables only Hash(only if Hash filter is enabled in H/W).
++ * Only frames matching Hash Filtering as per HMC and HUC
++ * configuration are sent to application.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_Hash_filter_only_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacHashPerfectFilter);
++	return;
++}
++
++/**
++ * Enables Source address filtering.
++ * When enabled source address filtering is performed. Only frames matching SA filtering are passed  to application with
++ * SAMatch bit of RxStatus is set. GMAC drops failed frames.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ * \note This function is overriden by synopGMAC_frame_filter_disable(synopGMACdevice *)
++ */
++void synopGMAC_src_addr_filter_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacSrcAddrFilter);
++	return;
++}
++/**
++ * Disables Source address filtering.
++ * When disabled GMAC forwards the received frames with updated SAMatch bit in RxStatus.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_src_addr_filter_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacSrcAddrFilter);
++	return;
++}
++/**
++ * Enables Inverse Destination address filtering.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_dst_addr_filter_inverse(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacDestAddrFilterNor);
++	return;
++}
++/**
++ * Enables the normal Destination address filtering.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_dst_addr_filter_normal(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacDestAddrFilterNor);
++	return;
++}
++
++/**
++ * Enables forwarding of control frames.
++ * When set forwards all the control frames (incl. unicast and multicast PAUSE frames).
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ * \note Depends on RFE of FlowControlRegister[2]
++ */
++void synopGMAC_set_pass_control(synopGMACdevice * gmacdev,u32 passcontrol)
++{
++	u32 data;
++	data = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacFrameFilter);
++	data &= (~GmacPassControl);
++	data |= passcontrol;
++	synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacFrameFilter,data);
++	return;
++}
++
++/**
++ * Enables Broadcast frames.
++ * When enabled Address filtering module passes all incoming broadcast frames.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_broadcast_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacBroadcast);
++	return;
++}
++/**
++ * Disable Broadcast frames.
++ * When disabled Address filtering module filters all incoming broadcast frames.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_broadcast_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacBroadcast);
++	return;
++}
++
++/**
++ * Enables Multicast frames.
++ * When enabled all multicast frames are passed.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_multicast_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacMulticastFilter);
++	return;
++}
++/**
++ * Disable Multicast frames.
++ * When disabled multicast frame filtering depends on HMC bit.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_multicast_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacMulticastFilter);
++	return;
++}
++
++/**
++ * Enables multicast hash filtering.
++ * When enabled GMAC performs teh destination address filtering according to the hash table.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_multicast_hash_filter_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacMcastHashFilter);
++	return;
++}
++/**
++ * Disables multicast hash filtering.
++ * When disabled GMAC performs perfect destination address filtering for multicast frames, it compares
++ * DA field with the value programmed in DA register.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_multicast_hash_filter_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacMcastHashFilter);
++	return;
++}
++
++/**
++ * Enables promiscous mode.
++ * When enabled Address filter modules pass all incoming frames regardless of their Destination
++ * and source addresses.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_promisc_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacPromiscuousMode);
++	return;
++}
++/**
++ * Clears promiscous mode.
++ * When called the GMAC falls back to normal operation from promiscous mode.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_promisc_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacPromiscuousMode);
++	return;
++}
++
++
++/**
++ * Enables unicast hash filtering.
++ * When enabled GMAC performs the destination address filtering of unicast frames according to the hash table.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_unicast_hash_filter_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacUcastHashFilter);
++	return;
++}
++/**
++ * Disables multicast hash filtering.
++ * When disabled GMAC performs perfect destination address filtering for unicast frames, it compares
++ * DA field with the value programmed in DA register.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_unicast_hash_filter_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacUcastHashFilter);
++	return;
++}
++
++/*Flow control configuration functions*/
++
++/**
++ * Enables detection of pause frames with stations unicast address.
++ * When enabled GMAC detects the pause frames with stations unicast address in addition to the
++ * detection of pause frames with unique multicast address.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_unicast_pause_frame_detect_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacUnicastPauseFrame);
++	return;
++}
++/**
++ * Disables detection of pause frames with stations unicast address.
++ * When disabled GMAC only detects with the unique multicast address (802.3x).
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_unicast_pause_frame_detect_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacUnicastPauseFrame);
++	return;
++}
++/**
++ * Rx flow control enable.
++ * When Enabled GMAC will decode the rx pause frame and disable the tx for a specified time.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_rx_flow_control_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacRxFlowControl);
++	return;
++}
++/**
++ * Rx flow control disable.
++ * When disabled GMAC will not decode pause frame.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_rx_flow_control_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacRxFlowControl);
++	return;
++}
++/**
++ * Tx flow control enable.
++ * When Enabled
++ * 	- In full duplex GMAC enables flow control operation to transmit pause frames.
++ *	- In Half duplex GMAC enables the back pressure operation
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_tx_flow_control_enable(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacTxFlowControl);
++	return;
++}
++
++/**
++ * Tx flow control disable.
++ * When Disabled
++ * 	- In full duplex GMAC will not transmit any pause frames.
++ *	- In Half duplex GMAC disables the back pressure feature.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_tx_flow_control_disable(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacTxFlowControl);
++	return;
++}
++
++/**
++ * Initiate Flowcontrol operation.
++ * When Set
++ * 	- In full duplex GMAC initiates pause control frame.
++ *	- In Half duplex GMAC initiates back pressure function.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_tx_activate_flow_control(synopGMACdevice * gmacdev)
++{
++	//In case of full duplex check for this bit to b'0. if it is read as b'1 indicates that
++	//control frame transmission is in progress.
++	if(gmacdev->Speed == FULLDUPLEX){
++		if(!synopGMACCheckBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure))
++			synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure);
++	}
++	else{ //if half duplex mode
++
++		synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure);
++	}
++
++	return;
++}
++
++/**
++ * stops Flowcontrol operation.
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_tx_deactivate_flow_control(synopGMACdevice * gmacdev)
++{
++	//In full duplex this bit is automatically cleared after transmitting a pause control frame.
++	if(gmacdev->Speed == HALFDUPLEX){
++		synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure);
++	}
++	return;
++}
++
++/**
++ * This enables the pause frame generation after programming the appropriate registers.
++ * presently activation is set at 3k and deactivation set at 4k. These may have to tweaked
++ * if found any issues
++ * @param[in] pointer to synopGMACdevice.
++ * \return void.
++ */
++void synopGMAC_pause_control(synopGMACdevice *gmacdev)
++{
++	u32 omr_reg;
++	u32 mac_flow_control_reg;
++	omr_reg = synopGMACReadReg((u32 *)gmacdev->DmaBase,DmaControl);
++	omr_reg |= DmaRxFlowCtrlAct3K | DmaRxFlowCtrlDeact4K |DmaEnHwFlowCtrl;
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaControl, omr_reg);
++
++	mac_flow_control_reg = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacFlowControl);
++	mac_flow_control_reg |= GmacRxFlowControl | GmacTxFlowControl | 0xFFFF0000;
++	synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacFlowControl,mac_flow_control_reg);
++
++	return;
++
++}
++
++/**
++ * Example mac initialization sequence.
++ * This function calls the initialization routines to initialize the GMAC register.
++ * One can change the functions invoked here to have different configuration as per the requirement
++ * @param[in] pointer to synopGMACdevice.
++ * \return Returns 0 on success.
++ */
++s32 synopGMAC_mac_init(synopGMACdevice * gmacdev)
++{
++	u32 PHYreg;
++
++	printk("=====>enter %s:%d\n", __func__, __LINE__);
++
++	if(gmacdev->DuplexMode == FULLDUPLEX){
++		printk("=====>full duplex\n");
++
++		synopGMAC_wd_enable(gmacdev);
++		//synopGMAC_jab_enable(gmacdev);
++		synopGMAC_frame_burst_enable(gmacdev);
++		synopGMAC_jumbo_frame_disable(gmacdev);
++		synopGMAC_rx_own_enable(gmacdev);
++		synopGMAC_loopback_off(gmacdev);
++		synopGMAC_set_full_duplex(gmacdev);
++		synopGMAC_retry_enable(gmacdev);
++		synopGMAC_pad_crc_strip_disable(gmacdev);
++		synopGMAC_back_off_limit(gmacdev,GmacBackoffLimit0);
++		synopGMAC_deferral_check_disable(gmacdev);
++		synopGMAC_tx_enable(gmacdev);
++		synopGMAC_rx_enable(gmacdev);
++
++		if(gmacdev->Speed == SPEED1000) {
++			printk("=====>1000M\n");
++			synopGMAC_select_gmii(gmacdev);
++		} else {
++			printk("=====>100M\n");
++			synopGMAC_select_mii(gmacdev);
++		}
++
++		/*Frame Filter Configuration*/
++		synopGMAC_frame_filter_enable(gmacdev);
++		synopGMAC_set_pass_control(gmacdev,GmacPassControl0);
++		synopGMAC_broadcast_enable(gmacdev);
++		synopGMAC_src_addr_filter_disable(gmacdev);
++		synopGMAC_multicast_disable(gmacdev);
++		synopGMAC_dst_addr_filter_normal(gmacdev);
++		synopGMAC_multicast_hash_filter_disable(gmacdev);
++		synopGMAC_promisc_disable(gmacdev);
++		synopGMAC_unicast_hash_filter_disable(gmacdev);
++
++		/*Flow Control Configuration*/
++		synopGMAC_unicast_pause_frame_detect_disable(gmacdev);
++#if 0
++		synopGMAC_rx_flow_control_enable(gmacdev);
++		synopGMAC_tx_flow_control_enable(gmacdev);
++#else
++		synopGMAC_rx_flow_control_disable(gmacdev);
++		synopGMAC_tx_flow_control_disable(gmacdev);
++#endif
++	}
++	else{//for Half Duplex configuration
++		printk("====>half duplex\n");
++
++		synopGMAC_wd_enable(gmacdev);
++		synopGMAC_jab_enable(gmacdev);
++		synopGMAC_frame_burst_enable(gmacdev);
++		synopGMAC_jumbo_frame_disable(gmacdev);
++		synopGMAC_rx_own_enable(gmacdev);
++		synopGMAC_loopback_off(gmacdev);
++		synopGMAC_set_half_duplex(gmacdev);
++		synopGMAC_retry_enable(gmacdev);
++		synopGMAC_pad_crc_strip_disable(gmacdev);
++		synopGMAC_back_off_limit(gmacdev,GmacBackoffLimit0);
++		synopGMAC_deferral_check_disable(gmacdev);
++		synopGMAC_tx_enable(gmacdev);
++		synopGMAC_rx_enable(gmacdev);
++
++		if(gmacdev->Speed == SPEED1000)
++			synopGMAC_select_gmii(gmacdev);
++		else
++			synopGMAC_select_mii(gmacdev);
++
++		/*Frame Filter Configuration*/
++		synopGMAC_frame_filter_enable(gmacdev);
++		synopGMAC_set_pass_control(gmacdev,GmacPassControl0);
++		synopGMAC_broadcast_enable(gmacdev);
++		synopGMAC_src_addr_filter_disable(gmacdev);
++		synopGMAC_multicast_disable(gmacdev);
++		synopGMAC_dst_addr_filter_normal(gmacdev);
++		synopGMAC_multicast_hash_filter_disable(gmacdev);
++		synopGMAC_promisc_disable(gmacdev);
++		synopGMAC_unicast_hash_filter_disable(gmacdev);
++
++		/*Flow Control Configuration*/
++		synopGMAC_unicast_pause_frame_detect_disable(gmacdev);
++		synopGMAC_rx_flow_control_disable(gmacdev);
++		synopGMAC_tx_flow_control_disable(gmacdev);
++
++		/*To set PHY register to enable CRS on Transmit*/
++		synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacGmiiAddr, GmiiBusy | 0x00000408);
++		PHYreg = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacGmiiData);
++		synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacGmiiData, PHYreg   | 0x00000800);
++		synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacGmiiAddr, GmiiBusy | 0x0000040a);
++	}
++	return 0;
++}
++
++s32 synopGMAC_search_phy (synopGMACdevice * gmacdev) {
++	int phy_id = 0;
++	u16 data;
++	s32 status = -ESYNOPGMACNOERR;
++
++	for (phy_id = 0; phy_id < 32; phy_id++) {
++		status = synopGMAC_read_phy_reg(gmacdev, phy_id, PHY_STATUS_REG, &data);
++		if ( (!status) && (data != 0xffff)) {
++			if((data & Mii_AutoNegCmplt) != 0){
++				printk("====>phy %d Autonegotiation Complete\n", phy_id);
++				break;
++			}
++		}
++	}
++
++	return (phy_id < 32) ? phy_id : -ESYNOPGMACPHYERR;
++}
++
++/**
++ * Checks and initialze phy.
++ * This function checks whether the phy initialization is complete.
++ * @param[in] pointer to synopGMACdevice.
++ * \return 0 if success else returns the error number.
++ */
++#if 0
++s32 synopGMAC_check_phy_init (synopGMACdevice * gmacdev)
++{
++	//u32 addr;
++	u16 data;
++	s32 status = -ESYNOPGMACNOERR;
++	s32 loop_count;
++
++	loop_count = DEFAULT_LOOP_VARIABLE;
++	while(loop_count-- > 0)
++	{
++
++		status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase,PHY_STATUS_REG, &data);
++		if(status)
++			return status;
++
++		if((data & Mii_AutoNegCmplt) != 0){
++			TR("Autonegotiation Complete\n");
++			break;
++		}
++	}
++
++	status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase,PHY_SPECIFIC_STATUS_REG, &data);
++	if(status)
++		return status;
++
++	if((data & Mii_phy_status_link_up) == 0){
++		TR("No Link\n");
++		gmacdev->LinkState = LINKDOWN;
++		return -ESYNOPGMACPHYERR;
++	}
++	else{
++		gmacdev->LinkState = LINKUP;
++		TR("Link UP\n");
++	}
++
++	status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase,PHY_SPECIFIC_STATUS_REG, &data);
++	if(status)
++		return status;
++
++
++
++	gmacdev->DuplexMode = (data & Mii_phy_status_full_duplex)  ? FULLDUPLEX: HALFDUPLEX ;
++	TR("Link is up in %s mode\n",(gmacdev->DuplexMode == FULLDUPLEX) ? "FULL DUPLEX": "HALF DUPLEX");
++
++	/*if not set to Master configuration in case of Half duplex mode set it manually as Master*/
++	if(gmacdev->DuplexMode == HALFDUPLEX){
++		printk("=========>enter %s:%d\n", __func__, __LINE__);
++		status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase,PHY_CONTROL_REG, &data);
++		if(status)
++			return status;
++
++		status = synopGMAC_write_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase,PHY_CONTROL_REG, data | Mii_Manual_Master_Config );
++		if(status)
++			return status;
++	}
++
++	status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase,PHY_SPECIFIC_STATUS_REG, &data);
++	if(status)
++		return status;
++	if(data & Mii_phy_status_speed_1000)
++		gmacdev->Speed      =   SPEED1000;
++	else if(data & Mii_phy_status_speed_100)
++		gmacdev->Speed      =   SPEED100;
++	else
++		gmacdev->Speed      =   SPEED10;
++
++	if(gmacdev->Speed == SPEED1000)
++		TR("Link is with 1000M Speed \n");
++	if(gmacdev->Speed == SPEED100)
++		TR("Link is with 100M Speed \n");
++	if(gmacdev->Speed == SPEED10)
++		TR("Link is with 10M Speed \n");
++
++	return -ESYNOPGMACNOERR;
++}
++#else
++s32 synopGMAC_check_phy_init (synopGMACdevice * gmacdev) {
++	gmacdev->LinkState = LINKUP;
++	gmacdev->DuplexMode = FULLDUPLEX;
++	gmacdev->Speed      =   SPEED100;
++
++	return -ESYNOPGMACNOERR;
++}
++#endif
++
++/**
++ * Sets the Mac address in to GMAC register.
++ * This function sets the MAC address to the MAC register in question.
++ * @param[in] pointer to synopGMACdevice to populate mac dma and phy addresses.
++ * @param[in] Register offset for Mac address high
++ * @param[in] Register offset for Mac address low
++ * @param[in] buffer containing mac address to be programmed.
++ * \return 0 upon success. Error code upon failure.
++ */
++s32 synopGMAC_set_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr)
++{
++	u32 data;
++
++	data = (MacAddr[5] << 8) | MacAddr[4];
++	synopGMACWriteReg((u32 *)gmacdev->MacBase,MacHigh,data);
++	data = (MacAddr[3] << 24) | (MacAddr[2] << 16) | (MacAddr[1] << 8) | MacAddr[0] ;
++	synopGMACWriteReg((u32 *)gmacdev->MacBase,MacLow,data);
++	return 0;
++}
++
++
++/**
++ * Get the Mac address in to the address specified.
++ * The mac register contents are read and written to buffer passed.
++ * @param[in] pointer to synopGMACdevice to populate mac dma and phy addresses.
++ * @param[in] Register offset for Mac address high
++ * @param[in] Register offset for Mac address low
++ * @param[out] buffer containing the device mac address.
++ * \return 0 upon success. Error code upon failure.
++ */
++s32 synopGMAC_get_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr)
++{
++	u32 data;
++
++	data = synopGMACReadReg((u32 *)gmacdev->MacBase,MacHigh);
++	MacAddr[5] = (data >> 8) & 0xff;
++	MacAddr[4] = (data)        & 0xff;
++
++	data = synopGMACReadReg((u32 *)gmacdev->MacBase,MacLow);
++	MacAddr[3] = (data >> 24) & 0xff;
++	MacAddr[2] = (data >> 16) & 0xff;
++	MacAddr[1] = (data >> 8 ) & 0xff;
++	MacAddr[0] = (data )      & 0xff;
++
++	return 0;
++}
++
++
++/**
++ * Attaches the synopGMAC device structure to the hardware.
++ * Device structure is populated with MAC/DMA and PHY base addresses.
++ * @param[in] pointer to synopGMACdevice to populate mac dma and phy addresses.
++ * @param[in] GMAC IP mac base address.
++ * @param[in] GMAC IP dma base address.
++ * @param[in] GMAC IP phy base address.
++ * \return 0 upon success. Error code upon failure.
++ * \note This is important function. No kernel api provided by Synopsys
++ */
++
++s32 synopGMAC_attach (synopGMACdevice * gmacdev, u32 macBase, u32 dmaBase, u32 phyBase)
++{
++	u8 mac_addr0[6] = DEFAULT_MAC_ADDRESS;
++	/*Make sure the Device data strucure is cleared before we proceed further*/
++	memset((void *) gmacdev,0,sizeof(synopGMACdevice));
++	/*Populate the mac and dma base addresses*/
++	gmacdev->MacBase = macBase;
++	gmacdev->DmaBase = dmaBase;
++	gmacdev->PhyBase = phyBase;
++
++	printk("=======>MacBase = 0x%08x, DmaBase = 0x%08x PhyBase = 0x%08x\n",
++			gmacdev->MacBase, gmacdev->DmaBase, gmacdev->PhyBase);
++
++	/* Program/flash in the station/IP's Mac address */
++	synopGMAC_set_mac_addr(gmacdev,GmacAddr0High,GmacAddr0Low, mac_addr0);
++
++	return 0;
++}
++
++
++
++/**
++ * Initialize the rx descriptors for ring or chain mode operation.
++ * 	- Status field is initialized to 0.
++ *	- EndOfRing set for the last descriptor.
++ *	- buffer1 and buffer2 set to 0 for ring mode of operation. (note)
++ *	- data1 and data2 set to 0. (note)
++ * @param[in] pointer to DmaDesc structure.
++ * @param[in] whether end of ring
++ * \return void.
++ * \note Initialization of the buffer1, buffer2, data1,data2 and status are not done here. This only initializes whether one wants to use this descriptor
++ * in chain mode or ring mode. For chain mode of operation the buffer2 and data2 are programmed before calling this function.
++ */
++void synopGMAC_rx_desc_init_ring(DmaDesc *desc, bool last_ring_desc)
++{
++	desc->status = 0;
++	desc->length = last_ring_desc ? RxDescEndOfRing : 0;
++	desc->buffer1 = 0;
++	desc->buffer2 = 0;
++	desc->data1 = 0;
++	desc->data2 = 0;
++	return;
++}
++/**
++ * Initialize the tx descriptors for ring or chain mode operation.
++ * 	- Status field is initialized to 0.
++ *	- EndOfRing set for the last descriptor.
++ *	- buffer1 and buffer2 set to 0 for ring mode of operation. (note)
++ *	- data1 and data2 set to 0. (note)
++ * @param[in] pointer to DmaDesc structure.
++ * @param[in] whether end of ring
++ * \return void.
++ * \note Initialization of the buffer1, buffer2, data1,data2 and status are not done here. This only initializes whether one wants to use this descriptor
++ * in chain mode or ring mode. For chain mode of operation the buffer2 and data2 are programmed before calling this function.
++ */
++void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc)
++{
++#ifdef ENH_DESC
++	desc->status = last_ring_desc? TxDescEndOfRing : 0;
++	desc->length = 0;
++#else
++	desc->length = last_ring_desc? TxDescEndOfRing : 0;
++#endif
++	desc->buffer1 = 0;
++	desc->buffer2 = 0;
++	desc->data1 = 0;
++	desc->data2 = 0;
++	return;
++}
++
++
++
++/**
++ * Initialize the rx descriptors for chain mode of operation.
++ * 	- Status field is initialized to 0.
++ *	- EndOfRing set for the last descriptor.
++ *	- buffer1 and buffer2 set to 0.
++ *	- data1 and data2 set to 0.
++ * @param[in] pointer to DmaDesc structure.
++ * @param[in] whether end of ring
++ * \return void.
++ */
++
++void synopGMAC_rx_desc_init_chain(DmaDesc * desc)
++{
++	desc->status = 0;
++	desc->length = RxDescChain;
++	desc->buffer1 = 0;
++	desc->data1 = 0;
++	return;
++}
++/**
++ * Initialize the rx descriptors for chain mode of operation.
++ * 	- Status field is initialized to 0.
++ *	- EndOfRing set for the last descriptor.
++ *	- buffer1 and buffer2 set to 0.
++ *	- data1 and data2 set to 0.
++ * @param[in] pointer to DmaDesc structure.
++ * @param[in] whether end of ring
++ * \return void.
++ */
++void synopGMAC_tx_desc_init_chain(DmaDesc * desc)
++{
++#ifdef ENH_DESC
++	desc->status = TxDescChain;
++	desc->length = 0;
++#else
++	desc->length = TxDescChain;
++#endif
++	desc->buffer1 = 0;
++	desc->data1 = 0;
++	return;
++}
++
++
++s32 synopGMAC_init_tx_rx_desc_queue(synopGMACdevice *gmacdev)
++{
++	s32 i;
++	for(i =0; i < gmacdev -> TxDescCount; i++){
++		synopGMAC_tx_desc_init_ring(gmacdev->TxDesc + i, i == gmacdev->TxDescCount-1);
++	}
++	TR("At line %d\n",__LINE__);
++	for(i =0; i < gmacdev -> RxDescCount; i++){
++		synopGMAC_rx_desc_init_ring(gmacdev->RxDesc + i, i == gmacdev->RxDescCount-1);
++	}
++
++	gmacdev->TxNext = 0;
++	gmacdev->TxBusy = 0;
++	gmacdev->RxNext = 0;
++	gmacdev->RxBusy = 0;
++
++	return -ESYNOPGMACNOERR;
++}
++/**
++ * Programs the DmaRxBaseAddress with the Rx descriptor base address.
++ * Rx Descriptor's base address is available in the gmacdev structure. This function progrms the
++ * Dma Rx Base address with the starting address of the descriptor ring or chain.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_init_rx_desc_base(synopGMACdevice *gmacdev)
++{
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase,DmaRxBaseAddr,(u32)gmacdev->RxDescDma);
++	return;
++}
++
++/**
++ * Programs the DmaTxBaseAddress with the Tx descriptor base address.
++ * Tx Descriptor's base address is available in the gmacdev structure. This function progrms the
++ * Dma Tx Base address with the starting address of the descriptor ring or chain.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_init_tx_desc_base(synopGMACdevice *gmacdev)
++{
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase,DmaTxBaseAddr,(u32)gmacdev->TxDescDma);
++	return;
++}
++
++
++/**
++ * Makes the Dma as owner for this descriptor.
++ * This function sets the own bit of status field of the DMA descriptor,
++ * indicating the DMA is the owner for this descriptor.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns void.
++ */
++void synopGMAC_set_owner_dma(DmaDesc *desc)
++{
++	desc->status |=  DescOwnByDma;
++}
++
++/**
++ * set tx descriptor to indicate SOF.
++ * This Descriptor contains the start of ethernet frame.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns void.
++ */
++void synopGMAC_set_desc_sof(DmaDesc *desc)
++{
++#ifdef ENH_DESC
++	desc->status |= DescTxFirst;//ENH_DESC
++#else
++	desc->length |= DescTxFirst;
++#endif
++
++}
++
++/**
++ * set tx descriptor to indicate EOF.
++ * This descriptor contains the End of ethernet frame.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns void.
++ */
++void synopGMAC_set_desc_eof(DmaDesc *desc)
++{
++#ifdef ENH_DESC
++	desc->status |= DescTxLast;//ENH_DESC
++#else
++	desc->length |= DescTxLast;
++#endif
++}
++
++
++/**
++ * checks whether this descriptor contains start of frame.
++ * This function is to check whether the descriptor's data buffer
++ * contains a fresh ethernet frame?
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if SOF in current descriptor, else returns fail.
++ */
++bool synopGMAC_is_sof_in_rx_desc(DmaDesc *desc)
++{
++	return ((desc->status & DescRxFirst) == DescRxFirst);
++}
++
++/**
++ * checks whether this descriptor contains end of frame.
++ * This function is to check whether the descriptor's data buffer
++ * contains end of ethernet frame?
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if SOF in current descriptor, else returns fail.
++ */
++bool synopGMAC_is_eof_in_rx_desc(DmaDesc *desc)
++{
++	return ((desc->status & DescRxLast) == DescRxLast);
++}
++
++/**
++ * checks whether destination address filter failed in the rx frame.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if Failed, false if not.
++ */
++bool synopGMAC_is_da_filter_failed(DmaDesc *desc)
++{
++	return ((desc->status & DescDAFilterFail) == DescDAFilterFail);
++}
++
++/**
++ * checks whether source address filter failed in the rx frame.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if Failed, false if not.
++ */
++bool synopGMAC_is_sa_filter_failed(DmaDesc *desc)
++{
++	return ((desc->status & DescSAFilterFail) == DescSAFilterFail);
++}
++
++/**
++ * Checks whether the descriptor is owned by DMA.
++ * If descriptor is owned by DMA then the OWN bit is set to 1. This API is same for both ring and chain mode.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if Dma owns descriptor and false if not.
++ */
++bool synopGMAC_is_desc_owned_by_dma(DmaDesc *desc)
++{
++	return ((desc->status & DescOwnByDma) == DescOwnByDma );
++}
++
++/**
++ * returns the byte length of received frame including CRC.
++ * This returns the no of bytes received in the received ethernet frame including CRC(FCS).
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns the length of received frame lengths in bytes.
++ */
++u32 synopGMAC_get_rx_desc_frame_length(u32 status)
++{
++	return ((status & DescFrameLengthMask) >> DescFrameLengthShift);
++}
++
++/**
++ * Checks whether the descriptor is valid
++ * if no errors such as CRC/Receive Error/Watchdog Timeout/Late collision/Giant Frame/Overflow/Descriptor
++ * error the descritpor is said to be a valid descriptor.
++ * @param[in] pointer to DmaDesc structure.
++ * \return True if desc valid. false if error.
++ */
++bool synopGMAC_is_desc_valid(u32 status)
++{
++	return ((status & DescError) == 0);
++}
++
++/**
++ * Checks whether the descriptor is empty.
++ * If the buffer1 and buffer2 lengths are zero in ring mode descriptor is empty.
++ * In chain mode buffer2 length is 0 but buffer2 itself contains the next descriptor address.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if descriptor is empty, false if not empty.
++ */
++bool synopGMAC_is_desc_empty(DmaDesc *desc)
++{
++	//if both the buffer1 length and buffer2 length are zero desc is empty
++	return(((desc->length  & DescSize1Mask) == 0) && ((desc->length  & DescSize2Mask) == 0) );
++}
++
++
++/**
++ * Checks whether the rx descriptor is valid.
++ * if rx descripor is not in error and complete frame is available in the same descriptor
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if no error and first and last desc bits are set, otherwise it returns false.
++ */
++bool synopGMAC_is_rx_desc_valid(u32 status)
++{
++	return ((status & DescError) == 0) && ((status & DescRxFirst) == DescRxFirst) && ((status & DescRxLast) == DescRxLast);
++}
++
++/**
++ * Checks whether the tx is aborted due to collisions.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if collisions, else returns false.
++ */
++bool synopGMAC_is_tx_aborted(u32 status)
++{
++	return (((status & DescTxLateCollision) == DescTxLateCollision) | ((status & DescTxExcCollisions) == DescTxExcCollisions));
++
++}
++
++/**
++ * Checks whether the tx carrier error.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if carrier error occured, else returns falser.
++ */
++bool synopGMAC_is_tx_carrier_error(u32 status)
++{
++	return (((status & DescTxLostCarrier) == DescTxLostCarrier)  | ((status & DescTxNoCarrier) == DescTxNoCarrier));
++}
++
++
++/**
++ * Gives the transmission collision count.
++ * returns the transmission collision count indicating number of collisions occured before the frame was transmitted.
++ * Make sure to check excessive collision didnot happen to ensure the count is valid.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns the count value of collision.
++ */
++u32 synopGMAC_get_tx_collision_count(u32 status)
++{
++	return ((status & DescTxCollMask) >> DescTxCollShift);
++}
++u32 synopGMAC_is_exc_tx_collisions(u32 status)
++{
++	return ((status & DescTxExcCollisions) == DescTxExcCollisions);
++}
++
++
++/**
++ * Check for damaged frame due to overflow or collision.
++ * Retruns true if rx frame was damaged due to buffer overflow in MTL or late collision in half duplex mode.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if error else returns false.
++ */
++bool synopGMAC_is_rx_frame_damaged(u32 status)
++{
++	//bool synopGMAC_dma_rx_collisions(u32 status)
++	return (((status & DescRxDamaged) == DescRxDamaged) | ((status & DescRxCollision) == DescRxCollision));
++}
++
++/**
++ * Check for damaged frame due to collision.
++ * Retruns true if rx frame was damaged due to late collision in half duplex mode.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if error else returns false.
++ */
++bool synopGMAC_is_rx_frame_collision(u32 status)
++{
++	//bool synopGMAC_dma_rx_collisions(u32 status)
++	return ((status & DescRxCollision) == DescRxCollision);
++}
++
++/**
++ * Check for receive CRC error.
++ * Retruns true if rx frame CRC error occured.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if error else returns false.
++ */
++bool synopGMAC_is_rx_crc(u32 status)
++{
++	//u32 synopGMAC_dma_rx_crc(u32 status)
++	return ((status & DescRxCrc) == DescRxCrc);
++}
++
++/**
++ * Indicates rx frame has non integer multiple of bytes. (odd nibbles).
++ * Retruns true if dribbling error in rx frame.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if error else returns false.
++ */
++bool synopGMAC_is_frame_dribbling_errors(u32 status)
++{
++	//u32 synopGMAC_dma_rx_frame_errors(u32 status)
++	return ((status & DescRxDribbling) == DescRxDribbling);
++}
++
++/**
++ * Indicates error in rx frame length.
++ * Retruns true if received frame length doesnot match with the length field
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if error else returns false.
++ */
++bool synopGMAC_is_rx_frame_length_errors(u32 status)
++{
++	//u32 synopGMAC_dma_rx_length_errors(u32 status)
++	return((status & DescRxLengthError) == DescRxLengthError);
++}
++
++/**
++ * Checks whether this rx descriptor is last rx descriptor.
++ * This returns true if it is last descriptor either in ring mode or in chain mode.
++ * @param[in] pointer to devic structure.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if it is last descriptor, false if not.
++ * \note This function should not be called before initializing the descriptor using synopGMAC_desc_init().
++ */
++bool synopGMAC_is_last_rx_desc(synopGMACdevice * gmacdev,DmaDesc *desc)
++{
++	//bool synopGMAC_is_last_desc(DmaDesc *desc)
++	return (((desc->length & RxDescEndOfRing) == RxDescEndOfRing) || ((u32)gmacdev->RxDesc == desc->data2));
++}
++
++/**
++ * Checks whether this tx descriptor is last tx descriptor.
++ * This returns true if it is last descriptor either in ring mode or in chain mode.
++ * @param[in] pointer to devic structure.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if it is last descriptor, false if not.
++ * \note This function should not be called before initializing the descriptor using synopGMAC_desc_init().
++ */
++bool synopGMAC_is_last_tx_desc(synopGMACdevice * gmacdev,DmaDesc *desc)
++{
++	//bool synopGMAC_is_last_desc(DmaDesc *desc)
++#ifdef ENH_DESC
++	return (((desc->status & TxDescEndOfRing) == TxDescEndOfRing) || ((u32)gmacdev->TxDesc == desc->data2));
++#else
++	return (((desc->length & TxDescEndOfRing) == TxDescEndOfRing) || ((u32)gmacdev->TxDesc == desc->data2));
++#endif
++}
++
++/**
++ * Checks whether this rx descriptor is in chain mode.
++ * This returns true if it is this descriptor is in chain mode.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if chain mode is set, false if not.
++ */
++bool synopGMAC_is_rx_desc_chained(DmaDesc * desc)
++{
++	return((desc->length & RxDescChain) == RxDescChain);
++}
++
++/**
++ * Checks whether this tx descriptor is in chain mode.
++ * This returns true if it is this descriptor is in chain mode.
++ * @param[in] pointer to DmaDesc structure.
++ * \return returns true if chain mode is set, false if not.
++ */
++bool synopGMAC_is_tx_desc_chained(DmaDesc * desc)
++{
++#ifdef ENH_DESC
++	return((desc->status & TxDescChain) == TxDescChain);
++#else
++	return((desc->length & TxDescChain) == TxDescChain);
++#endif
++}
++
++/**
++ * Driver Api to get the descriptor field information.
++ * This returns the status, dma-able address of buffer1, the length of buffer1, virtual address of buffer1
++ * dma-able address of buffer2, length of buffer2, virtural adddress of buffer2.
++ * @param[in]  pointer to DmaDesc structure.
++ * @param[out] pointer to status field fo descriptor.
++ * @param[out] dma-able address of buffer1.
++ * @param[out] length of buffer1.
++ * @param[out] virtual address of buffer1.
++ * @param[out] dma-able address of buffer2.
++ * @param[out] length of buffer2.
++ * @param[out] virtual address of buffer2.
++ * \return returns void.
++ */
++void synopGMAC_get_desc_data(DmaDesc * desc, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2)
++{
++
++	if(Status != 0)
++		*Status = desc->status;
++
++	if(Buffer1 != 0)
++		*Buffer1 = desc->buffer1;
++	if(Length1 != 0)
++		*Length1 = (desc->length & DescSize1Mask) >> DescSize1Shift;
++	if(Data1 != 0)
++		*Data1 = desc->data1;
++
++	if(Buffer2 != 0)
++		*Buffer2 = desc->buffer2;
++	if(Length2 != 0)
++		*Length2 = (desc->length & DescSize2Mask) >> DescSize2Shift;
++	if(Data1 != 0)
++		*Data2 = desc->data2;
++
++	return;
++
++}
++#ifdef AVB_SUPPORT
++void synopGMAC_set_desc_data(DmaDesc *txdesc, u32 Status, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2)
++{
++	TR("s:%08x B1:%08x L1:%08x D1: %08x B2: %08x L2: %08x D2: %08x\n",Status,Buffer1,Length1,Data1,Buffer2,Length2,Data2);
++
++	txdesc->length = (((Length1 <<DescSize1Shift) & DescSize1Mask) | ((Length2 <<DescSize2Shift) & DescSize2Mask));
++#ifdef ENH_DESC
++	txdesc->status |=  (DescTxFirst | DescTxLast | DescTxIntEnable | Status ); //ENH_DESC
++#else
++	txdesc->length |=  (DescTxFirst | DescTxLast | DescTxIntEnable ); //Its always assumed that complete data will fit in to one descriptor
++#endif
++
++	txdesc->buffer1 = Buffer1;
++	txdesc->data1 = Data1;
++
++	txdesc->buffer2 = Buffer2;
++	txdesc->data2 = Data2;
++
++#ifdef ENH_DESC
++	txdesc->status |= DescOwnByDma;//ENH_DESC
++#else
++	txdesc->status = DescOwnByDma;
++#endif
++}
++#endif
++
++#ifdef ENH_DESC_8W
++/**
++ * This function is defined two times. Once when the code is compiled for ENHANCED DESCRIPTOR SUPPORT and Once for Normal descriptor
++ * Get the index and address of Tx desc.
++ * This api is same for both ring mode and chain mode.
++ * This function tracks the tx descriptor the DMA just closed after the transmission of data from this descriptor is
++ * over. This returns the descriptor fields to the caller.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[out] status field of the descriptor.
++ * @param[out] Dma-able buffer1 pointer.
++ * @param[out] length of buffer1 (Max is 2048).
++ * @param[out] virtual pointer for buffer1.
++ * @param[out] Dma-able buffer2 pointer.
++ * @param[out] length of buffer2 (Max is 2048).
++ * @param[out] virtual pointer for buffer2.
++ * @param[out] u32 data indicating whether the descriptor is in ring mode or chain mode.
++ * \return returns present tx descriptor index on success. Negative value if error.
++ */
++s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2,
++		u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_Low)
++{
++	u32  txover      = gmacdev->TxBusy;
++	DmaDesc * txdesc = gmacdev->TxBusyDesc;
++
++	if(synopGMAC_is_desc_owned_by_dma(txdesc))
++		return -1;
++	if(synopGMAC_is_desc_empty(txdesc))
++		return -1;
++
++	(gmacdev->BusyTxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now
++
++	if(Status != 0)
++		*Status = txdesc->status;
++
++	if(Ext_Status != 0)
++		*Ext_Status = txdesc->extstatus;
++	if(Time_Stamp_High != 0)
++		*Time_Stamp_High = txdesc->timestamphigh;
++	if(Time_Stamp_Low != 0)
++		*Time_Stamp_High = txdesc->timestamplow;
++
++	if(Buffer1 != 0)
++		*Buffer1 = txdesc->buffer1;
++	if(Length1 != 0)
++		*Length1 = (txdesc->length & DescSize1Mask) >> DescSize1Shift;
++	if(Data1 != 0)
++		*Data1 = txdesc->data1;
++
++	if(Buffer2 != 0)
++		*Buffer2 = txdesc->buffer2;
++	if(Length2 != 0)
++		*Length2 = (txdesc->length & DescSize2Mask) >> DescSize2Shift;
++	if(Data1 != 0)
++		*Data2 = txdesc->data2;
++
++	gmacdev->TxBusy     = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1;
++
++	if(synopGMAC_is_tx_desc_chained(txdesc)){
++		gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2;
++		synopGMAC_tx_desc_init_chain(txdesc);
++	}
++	else{
++		gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1);
++		synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev,txdesc));
++	}
++	TR("(get)%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2);
++
++	return txover;
++}
++#else
++
++/**
++ * Get the index and address of Tx desc.
++ * This api is same for both ring mode and chain mode.
++ * This function tracks the tx descriptor the DMA just closed after the transmission of data from this descriptor is
++ * over. This returns the descriptor fields to the caller.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[out] status field of the descriptor.
++ * @param[out] Dma-able buffer1 pointer.
++ * @param[out] length of buffer1 (Max is 2048).
++ * @param[out] virtual pointer for buffer1.
++ * @param[out] Dma-able buffer2 pointer.
++ * @param[out] length of buffer2 (Max is 2048).
++ * @param[out] virtual pointer for buffer2.
++ * @param[out] u32 data indicating whether the descriptor is in ring mode or chain mode.
++ * \return returns present tx descriptor index on success. Negative value if error.
++ */
++s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2 )
++{
++	u32  txover      = gmacdev->TxBusy;
++	DmaDesc * txdesc = gmacdev->TxBusyDesc;
++
++	if(synopGMAC_is_desc_owned_by_dma(txdesc))
++		return -1;
++	if(synopGMAC_is_desc_empty(txdesc))
++		return -1;
++
++	(gmacdev->BusyTxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now
++
++	if(Status != 0)
++		*Status = txdesc->status;
++
++	if(Buffer1 != 0)
++		*Buffer1 = txdesc->buffer1;
++	if(Length1 != 0)
++		*Length1 = (txdesc->length & DescSize1Mask) >> DescSize1Shift;
++	if(Data1 != 0)
++		*Data1 = txdesc->data1;
++
++	if(Buffer2 != 0)
++		*Buffer2 = txdesc->buffer2;
++	if(Length2 != 0)
++		*Length2 = (txdesc->length & DescSize2Mask) >> DescSize2Shift;
++	if(Data1 != 0)
++		*Data2 = txdesc->data2;
++
++	gmacdev->TxBusy     = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1;
++
++	if(synopGMAC_is_tx_desc_chained(txdesc)){
++		gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2;
++		synopGMAC_tx_desc_init_chain(txdesc);
++	}
++	else{
++		gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1);
++		synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev,txdesc));
++	}
++	TR("(get)%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2);
++
++	return txover;
++}
++
++#endif
++/**
++ * Populate the tx desc structure with the buffer address.
++ * Once the driver has a packet ready to be transmitted, this function is called with the
++ * valid dma-able buffer addresses and their lengths. This function populates the descriptor
++ * and make the DMA the owner for the descriptor. This function also controls whetther Checksum
++ * offloading to be done in hardware or not.
++ * This api is same for both ring mode and chain mode.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] Dma-able buffer1 pointer.
++ * @param[in] length of buffer1 (Max is 2048).
++ * @param[in] virtual pointer for buffer1.
++ * @param[in] Dma-able buffer2 pointer.
++ * @param[in] length of buffer2 (Max is 2048).
++ * @param[in] virtual pointer for buffer2.
++ * @param[in] u32 data indicating whether the descriptor is in ring mode or chain mode.
++ * @param[in] u32 indicating whether the checksum offloading in HW/SW.
++ * \return returns present tx descriptor index on success. Negative value if error.
++ */
++s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2,u32 offload_needed)
++{
++	u32  txnext      = gmacdev->TxNext;
++	DmaDesc * txdesc = gmacdev->TxNextDesc;
++	if(!synopGMAC_is_desc_empty(txdesc))
++		return -1;
++
++	(gmacdev->BusyTxDesc)++; //busy tx descriptor is incremented by one as it will be handed over to DMA
++
++	if(synopGMAC_is_tx_desc_chained(txdesc)){
++		txdesc->length |= ((Length1 <<DescSize1Shift) & DescSize1Mask);
++#ifdef ENH_DESC
++		txdesc->status |=  (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC
++#else
++		txdesc->length |=  (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor
++#endif
++
++		txdesc->buffer1 = Buffer1;
++		txdesc->data1 = Data1;
++
++		if(offload_needed){
++			/*
++			   Make sure that the OS you are running supports the IP and TCP checkusm offloaidng,
++			   before calling any of the functions given below.
++			   */
++			synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc);
++			synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc);
++			//		synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc);
++		}
++#ifdef ENH_DESC
++		txdesc->status |= DescOwnByDma;//ENH_DESC
++#else
++		txdesc->status = DescOwnByDma;
++#endif
++
++		gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1;
++		gmacdev->TxNextDesc = (DmaDesc *)txdesc->data2;
++	}
++	else{
++		txdesc->length |= (((Length1 <<DescSize1Shift) & DescSize1Mask) | ((Length2 <<DescSize2Shift) & DescSize2Mask));
++#ifdef ENH_DESC
++		txdesc->status |=  (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC
++#else
++		txdesc->length |=  (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor
++#endif
++
++		txdesc->buffer1 = Buffer1;
++		txdesc->data1 = Data1;
++
++		txdesc->buffer2 = Buffer2;
++		txdesc->data2 = Data2;
++
++		if(offload_needed){
++			/*
++			   Make sure that the OS you are running supports the IP and TCP checkusm offloaidng,
++			   before calling any of the functions given below.
++			   */
++			synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc);
++			synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc);
++			//		synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc);
++		}
++#ifdef ENH_DESC
++		txdesc->status |= DescOwnByDma;//ENH_DESC
++#else
++		txdesc->status = DescOwnByDma;
++#endif
++
++		gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1;
++		gmacdev->TxNextDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1);
++	}
++
++
++	TR("(set)%02d %08x %08x %08x %08x %08x %08x %08x\n",txnext,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2);
++	return txnext;
++}
++#ifdef ENH_DESC_8W
++/**
++ * Prepares the descriptor to receive packets.
++ * The descriptor is allocated with the valid buffer addresses (sk_buff address) and the length fields
++ * and handed over to DMA by setting the ownership. After successful return from this function the
++ * descriptor is added to the receive descriptor pool/queue.
++ * This api is same for both ring mode and chain mode.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] Dma-able buffer1 pointer.
++ * @param[in] length of buffer1 (Max is 2048).
++ * @param[in] Dma-able buffer2 pointer.
++ * @param[in] length of buffer2 (Max is 2048).
++ * @param[in] u32 data indicating whether the descriptor is in ring mode or chain mode.
++ * \return returns present rx descriptor index on success. Negative value if error.
++ */
++s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2)
++{
++	u32  rxnext      = gmacdev->RxNext;
++	DmaDesc * rxdesc = gmacdev->RxNextDesc;
++
++	if(!synopGMAC_is_desc_empty(rxdesc))
++		return -1;
++
++
++	if(synopGMAC_is_rx_desc_chained(rxdesc)){
++		rxdesc->length |= ((Length1 <<DescSize1Shift) & DescSize1Mask);
++
++		rxdesc->buffer1 = Buffer1;
++		rxdesc->data1 = Data1;
++
++		rxdesc->extstatus = 0;
++		rxdesc->reserved1 = 0;
++		rxdesc->timestamplow = 0;
++		rxdesc->timestamphigh = 0;
++
++		if((rxnext % MODULO_INTERRUPT) !=0)
++			rxdesc->length |= RxDisIntCompl;
++
++		rxdesc->status = DescOwnByDma;
++
++		gmacdev->RxNext     = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1;
++		gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2;
++	}
++	else{
++		rxdesc->length |= (((Length1 <<DescSize1Shift) & DescSize1Mask) | ((Length2 << DescSize2Shift) & DescSize2Mask));
++
++		rxdesc->buffer1 = Buffer1;
++		rxdesc->data1 = Data1;
++
++		rxdesc->extstatus = 0;
++		rxdesc->reserved1 = 0;
++		rxdesc->timestamplow = 0;
++		rxdesc->timestamphigh = 0;
++
++		rxdesc->buffer2 = Buffer2;
++		rxdesc->data2 = Data2;
++
++		if((rxnext % MODULO_INTERRUPT) !=0)
++			rxdesc->length |= RxDisIntCompl;
++
++		rxdesc->status = DescOwnByDma;
++
++		gmacdev->RxNext     = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1;
++		gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1);
++	}
++	TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2);
++
++	(gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one
++	return rxnext;
++}
++
++#else
++/**
++ * Prepares the descriptor to receive packets.
++ * The descriptor is allocated with the valid buffer addresses (sk_buff address) and the length fields
++ * and handed over to DMA by setting the ownership. After successful return from this function the
++ * descriptor is added to the receive descriptor pool/queue.
++ * This api is same for both ring mode and chain mode.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] Dma-able buffer1 pointer.
++ * @param[in] length of buffer1 (Max is 2048).
++ * @param[in] Dma-able buffer2 pointer.
++ * @param[in] length of buffer2 (Max is 2048).
++ * @param[in] u32 data indicating whether the descriptor is in ring mode or chain mode.
++ * \return returns present rx descriptor index on success. Negative value if error.
++ */
++s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2)
++{
++	u32  rxnext      = gmacdev->RxNext;
++	DmaDesc * rxdesc = gmacdev->RxNextDesc;
++
++	if(!synopGMAC_is_desc_empty(rxdesc))
++		return -1;
++
++	if(synopGMAC_is_rx_desc_chained(rxdesc)){
++		rxdesc->length |= ((Length1 <<DescSize1Shift) & DescSize1Mask);
++
++		rxdesc->buffer1 = Buffer1;
++		rxdesc->data1 = Data1;
++
++		if((rxnext % MODULO_INTERRUPT) !=0)
++			rxdesc->length |= RxDisIntCompl;
++
++		rxdesc->status = DescOwnByDma;
++
++		gmacdev->RxNext     = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1;
++		gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2;
++	}
++	else{
++		rxdesc->length |= (((Length1 <<DescSize1Shift) & DescSize1Mask) | ((Length2 << DescSize2Shift) & DescSize2Mask));
++
++		rxdesc->buffer1 = Buffer1;
++		rxdesc->data1 = Data1;
++
++		rxdesc->buffer2 = Buffer2;
++		rxdesc->data2 = Data2;
++
++		if((rxnext % MODULO_INTERRUPT) !=0)
++			rxdesc->length |= RxDisIntCompl;
++
++		rxdesc->status = DescOwnByDma;
++
++		gmacdev->RxNext     = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1;
++		gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1);
++	}
++	TR("%s: %02d %08x %08x %08x %08x %08x %08x %08x\n",
++			__func__, rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2);
++	(gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one
++	return rxnext;
++}
++
++#endif
++#ifdef ENH_DESC_8W
++/**
++ * This function is defined two times. Once when the code is compiled for ENHANCED DESCRIPTOR SUPPORT and Once for Normal descriptor
++ * Get back the descriptor from DMA after data has been received.
++ * When the DMA indicates that the data is received (interrupt is generated), this function should be
++ * called to get the descriptor and hence the data buffers received. With successful return from this
++ * function caller gets the descriptor fields for processing. check the parameters to understand the
++ * fields returned.`
++ * @param[in] pointer to synopGMACdevice.
++ * @param[out] pointer to hold the status of DMA.
++ * @param[out] Dma-able buffer1 pointer.
++ * @param[out] pointer to hold length of buffer1 (Max is 2048).
++ * @param[out] virtual pointer for buffer1.
++ * @param[out] Dma-able buffer2 pointer.
++ * @param[out] pointer to hold length of buffer2 (Max is 2048).
++ * @param[out] virtual pointer for buffer2.
++ * \return returns present rx descriptor index on success. Negative value if error.
++ */
++s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2,
++		u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_Low)
++{
++	u32 rxnext       = gmacdev->RxBusy;	// index of descriptor the DMA just completed. May be useful when data
++	//is spread over multiple buffers/descriptors
++	DmaDesc * rxdesc = gmacdev->RxBusyDesc;
++	if(synopGMAC_is_desc_owned_by_dma(rxdesc))
++		return -1;
++	if(synopGMAC_is_desc_empty(rxdesc))
++		return -1;
++
++
++	if(Status != 0)
++		*Status = rxdesc->status;// send the status of this descriptor
++
++	if(Ext_Status != 0)
++		*Ext_Status = rxdesc->extstatus;
++	if(Time_Stamp_High != 0)
++		*Time_Stamp_High = rxdesc->timestamphigh;
++	if(Time_Stamp_Low != 0)
++		*Time_Stamp_Low = rxdesc->timestamplow;
++
++	if(Length1 != 0)
++		*Length1 = (rxdesc->length & DescSize1Mask) >> DescSize1Shift;
++	if(Buffer1 != 0)
++		*Buffer1 = rxdesc->buffer1;
++	if(Data1 != 0)
++		*Data1 = rxdesc->data1;
++
++	if(Length2 != 0)
++		*Length2 = (rxdesc->length & DescSize2Mask) >> DescSize2Shift;
++	if(Buffer2 != 0)
++		*Buffer2 = rxdesc->buffer2;
++	if(Data1 != 0)
++		*Data2 = rxdesc->data2;
++
++	gmacdev->RxBusy     = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1;
++
++	if(synopGMAC_is_rx_desc_chained(rxdesc)){
++		gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2;
++		synopGMAC_rx_desc_init_chain(rxdesc);
++		//synopGMAC_desc_init_chain(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc),0,0);
++	}
++	else{
++		gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1);
++		synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc));
++	}
++	TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2);
++	(gmacdev->BusyRxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now
++	return(rxnext);
++
++}
++#else
++
++/**
++ * Get back the descriptor from DMA after data has been received.
++ * When the DMA indicates that the data is received (interrupt is generated), this function should be
++ * called to get the descriptor and hence the data buffers received. With successful return from this
++ * function caller gets the descriptor fields for processing. check the parameters to understand the
++ * fields returned.`
++ * @param[in] pointer to synopGMACdevice.
++ * @param[out] pointer to hold the status of DMA.
++ * @param[out] Dma-able buffer1 pointer.
++ * @param[out] pointer to hold length of buffer1 (Max is 2048).
++ * @param[out] virtual pointer for buffer1.
++ * @param[out] Dma-able buffer2 pointer.
++ * @param[out] pointer to hold length of buffer2 (Max is 2048).
++ * @param[out] virtual pointer for buffer2.
++ * \return returns present rx descriptor index on success. Negative value if error.
++ */
++s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2)
++{
++	u32 rxnext       = gmacdev->RxBusy;	// index of descriptor the DMA just completed. May be useful when data
++	//is spread over multiple buffers/descriptors
++	DmaDesc * rxdesc = gmacdev->RxBusyDesc;
++	if(synopGMAC_is_desc_owned_by_dma(rxdesc))
++		return -1;
++	if(synopGMAC_is_desc_empty(rxdesc))
++		return -1;
++
++
++	if(Status != 0)
++		*Status = rxdesc->status;// send the status of this descriptor
++
++	if(Length1 != 0)
++		*Length1 = (rxdesc->length & DescSize1Mask) >> DescSize1Shift;
++	if(Buffer1 != 0)
++		*Buffer1 = rxdesc->buffer1;
++	if(Data1 != 0)
++		*Data1 = rxdesc->data1;
++
++	if(Length2 != 0)
++		*Length2 = (rxdesc->length & DescSize2Mask) >> DescSize2Shift;
++	if(Buffer2 != 0)
++		*Buffer2 = rxdesc->buffer2;
++	if(Data1 != 0)
++		*Data2 = rxdesc->data2;
++
++	gmacdev->RxBusy     = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1;
++
++	if(synopGMAC_is_rx_desc_chained(rxdesc)){
++		gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2;
++		synopGMAC_rx_desc_init_chain(rxdesc);
++		//synopGMAC_desc_init_chain(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc),0,0);
++	}
++	else{
++		gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1);
++		synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc));
++	}
++	TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2);
++	(gmacdev->BusyRxDesc)--; //This returns one descriptor to processor. So busy count will be decremented by one
++
++	return(rxnext);
++
++}
++
++#endif
++
++/**
++ * Clears all the pending interrupts.
++ * If the Dma status register is read then all the interrupts gets cleared
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_clear_interrupt(synopGMACdevice *gmacdev)
++{
++	u32 data;
++	data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaStatus);
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaStatus ,data);
++}
++
++/**
++ * Returns the all unmasked interrupt status after reading the DmaStatus register.
++ * @param[in] pointer to synopGMACdevice.
++ * \return 0 upon success. Error code upon failure.
++ */
++u32 synopGMAC_get_interrupt_type(synopGMACdevice *gmacdev)
++{
++	u32 data;
++	u32 interrupts = 0;
++	data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaStatus);
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaStatus ,data); //This is the appropriate location to clear the interrupts
++	TR("DMA status reg is  %08x\n",data);
++	if(data & DmaIntErrorMask)	interrupts     |= synopGMACDmaError;
++	if(data & DmaIntRxNormMask)	interrupts     |= synopGMACDmaRxNormal;
++	if(data & DmaIntRxAbnMask)	interrupts     |= synopGMACDmaRxAbnormal;
++	if(data & DmaIntRxStoppedMask)	interrupts |= synopGMACDmaRxStopped;
++	if(data & DmaIntTxNormMask)	interrupts     |= synopGMACDmaTxNormal;
++	if(data & DmaIntTxAbnMask)	interrupts     |= synopGMACDmaTxAbnormal;
++	if(data & DmaIntTxStoppedMask)	interrupts |= synopGMACDmaTxStopped;
++#ifdef AVB_SUPPORT
++	if(data & DmaSlotCounterIntr)   interrupts |= synopGMADmaSlotCounter;
++#endif
++
++	return interrupts;
++}
++
++/**
++ * Returns the interrupt mask.
++ * @param[in] pointer to synopGMACdevice.
++ * \return 0 upon success. Error code upon failure.
++ */
++u32 synopGMAC_get_interrupt_mask(synopGMACdevice *gmacdev)
++{
++	return(synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaInterrupt));
++}
++
++/**
++ * Enable all the interrupts.
++ * Enables the DMA interrupt as specified by the bit mask.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] bit mask of interrupts to be enabled.
++ * \return returns void.
++ */
++void synopGMAC_enable_interrupt(synopGMACdevice *gmacdev, u32 interrupts)
++{
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaInterrupt, interrupts);
++	return;
++}
++
++
++/**
++ * Disable all the interrupts.
++ * Disables all DMA interrupts.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ * \note This function disabled all the interrupts, if you want to disable a particular interrupt then
++ *  use synopGMAC_disable_interrupt().
++ */
++void synopGMAC_disable_interrupt_all(synopGMACdevice *gmacdev)
++{
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaInterrupt, DmaIntDisable);
++	return;
++}
++
++/**
++ * Disable interrupt according to the bitfield supplied.
++ * Disables only those interrupts specified in the bit mask in second argument.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] bit mask for interrupts to be disabled.
++ * \return returns void.
++ */
++void synopGMAC_disable_interrupt(synopGMACdevice *gmacdev, u32 interrupts)
++{
++	synopGMACClearBits((u32 *)gmacdev->DmaBase, DmaInterrupt, interrupts);
++	return;
++}
++/**
++ * Enable the DMA Reception.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_enable_dma_rx(synopGMACdevice * gmacdev)
++{
++	//	synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaControl, DmaRxStart);
++	u32 data;
++	data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaControl);
++	data |= DmaRxStart;
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaControl ,data);
++
++}
++
++/**
++ * Enable the DMA Transmission.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_enable_dma_tx(synopGMACdevice * gmacdev)
++{
++	//	synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaControl, DmaTxStart);
++	u32 data;
++	data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaControl);
++	data |= DmaTxStart;
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaControl ,data);
++
++}
++
++/**
++ * Resumes the DMA Transmission.
++ * the DmaTxPollDemand is written. (the data writeen could be anything).
++ * This forces the DMA to resume transmission.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_resume_dma_tx(synopGMACdevice * gmacdev)
++{
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaTxPollDemand, 0);
++
++}
++/**
++ * Resumes the DMA Reception.
++ * the DmaRxPollDemand is written. (the data writeen could be anything).
++ * This forces the DMA to resume reception.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_resume_dma_rx(synopGMACdevice * gmacdev)
++{
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaRxPollDemand, 0);
++
++}
++/**
++ * Take ownership of this Descriptor.
++ * The function is same for both the ring mode and the chain mode DMA structures.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_take_desc_ownership(DmaDesc * desc)
++{
++	if(desc){
++		desc->status &= ~DescOwnByDma;  //Clear the DMA own bit
++		//		desc->status |= DescError;	// Set the error to indicate this descriptor is bad
++	}
++}
++
++/**
++ * Take ownership of all the rx Descriptors.
++ * This function is called when there is fatal error in DMA transmission.
++ * When called it takes the ownership of all the rx descriptor in rx descriptor pool/queue from DMA.
++ * The function is same for both the ring mode and the chain mode DMA structures.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ * \note Make sure to disable the transmission before calling this function, otherwise may result in racing situation.
++ */
++void synopGMAC_take_desc_ownership_rx(synopGMACdevice * gmacdev)
++{
++	s32 i;
++	DmaDesc *desc;
++	desc = gmacdev->RxDesc;
++	for(i = 0; i < gmacdev->RxDescCount; i++){
++		if(synopGMAC_is_rx_desc_chained(desc)){	//This descriptor is in chain mode
++
++			synopGMAC_take_desc_ownership(desc);
++			desc = (DmaDesc *)desc->data2;
++		}
++		else{
++			synopGMAC_take_desc_ownership(desc + i);
++		}
++	}
++}
++
++/**
++ * Take ownership of all the rx Descriptors.
++ * This function is called when there is fatal error in DMA transmission.
++ * When called it takes the ownership of all the tx descriptor in tx descriptor pool/queue from DMA.
++ * The function is same for both the ring mode and the chain mode DMA structures.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ * \note Make sure to disable the transmission before calling this function, otherwise may result in racing situation.
++ */
++void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev)
++{
++	s32 i;
++	DmaDesc *desc;
++	desc = gmacdev->TxDesc;
++	for(i = 0; i < gmacdev->TxDescCount; i++){
++		if(synopGMAC_is_tx_desc_chained(desc)){	//This descriptor is in chain mode
++			synopGMAC_take_desc_ownership(desc);
++			desc = (DmaDesc *)desc->data2;
++		}
++		else{
++			synopGMAC_take_desc_ownership(desc + i);
++		}
++	}
++
++}
++
++/**
++ * Disable the DMA for Transmission.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++
++void synopGMAC_disable_dma_tx(synopGMACdevice * gmacdev)
++{
++	//	synopGMACClearBits((u32 *)gmacdev->DmaBase, DmaControl, DmaTxStart);
++	u32 data;
++	data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaControl);
++	data &= (~DmaTxStart);
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaControl ,data);
++}
++/**
++ * Disable the DMA for Reception.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev)
++{
++	//	synopGMACClearBits((u32 *)gmacdev->DmaBase, DmaControl, DmaRxStart);
++	u32 data;
++	data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaControl);
++	data &= (~DmaRxStart);
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaControl ,data);
++}
++
++
++
++/*******************PMT APIs***************************************/
++
++
++
++
++/**
++ * Enables the assertion of PMT interrupt.
++ * This enables the assertion of PMT interrupt due to Magic Pkt or Wakeup frame
++ * reception.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_pmt_int_enable(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask);
++	return;
++}
++/**
++ * Disables the assertion of PMT interrupt.
++ * This disables the assertion of PMT interrupt due to Magic Pkt or Wakeup frame
++ * reception.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_pmt_int_disable(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask);
++	return;
++}
++/**
++ * Enables the power down mode of GMAC.
++ * This function puts the Gmac in power down mode.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_power_down_enable(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtPowerDown);
++	return;
++}
++/**
++ * Disables the powerd down setting of GMAC.
++ * If the driver wants to bring up the GMAC from powerdown mode, even though the magic packet or the
++ * wake up frames received from the network, this function should be called.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_power_down_disable(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtPowerDown);
++	return;
++}
++/**
++ * Enables the pmt interrupt generation in powerdown mode.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_enable_pmt_interrupt(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask);
++}
++/**
++ * Disables the pmt interrupt generation in powerdown mode.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_disable_pmt_interrupt(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask);
++}
++/**
++ * Enables GMAC to look for Magic packet.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_magic_packet_enable(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtMagicPktEnable);
++	return;
++}
++
++/**
++ * Enables GMAC to look for wake up frame.
++ * Wake up frame is defined by the user.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_wakeup_frame_enable(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtWakeupFrameEnable);
++	return;
++}
++
++/**
++ * Enables wake-up frame filter to handle unicast packets.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_pmt_unicast_enable(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtGlobalUnicast);
++	return;
++}
++/**
++ * Checks whether the packet received is a magic packet?.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns True if magic packet received else returns false.
++ */
++bool synopGMAC_is_magic_packet_received(synopGMACdevice *gmacdev)
++{
++	u32 data;
++	data = 	synopGMACReadReg((u32 *)gmacdev->MacBase,GmacPmtCtrlStatus);
++	return((data & GmacPmtMagicPktReceived) == GmacPmtMagicPktReceived);
++}
++/**
++ * Checks whether the packet received is a wakeup frame?.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns true if wakeup frame received else returns false.
++ */
++bool synopGMAC_is_wakeup_frame_received(synopGMACdevice *gmacdev)
++{
++	u32 data;
++	data = 	synopGMACReadReg((u32 *)gmacdev->MacBase,GmacPmtCtrlStatus);
++	return((data & GmacPmtWakeupFrameReceived) == GmacPmtWakeupFrameReceived);
++}
++
++/**
++ * Populates the remote wakeup frame registers.
++ * Consecutive 8 writes to GmacWakeupAddr writes the wakeup frame filter registers.
++ * Before commensing a new write, frame filter pointer is reset to 0x0000.
++ * A small delay is introduced to allow frame filter pointer reset operation.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] pointer to frame filter contents array.
++ * \return returns void.
++ */
++void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 * filter_contents)
++{
++	s32 i;
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtFrmFilterPtrReset);
++	plat_delay(10);
++	for(i =0; i<WAKEUP_REG_LENGTH; i++)
++		synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacWakeupAddr,  *(filter_contents + i));
++	return;
++
++}
++/*******************PMT APIs***************************************/
++/*******************MMC APIs***************************************/
++
++/**
++ * Freezes the MMC counters.
++ * This function call freezes the MMC counters. None of the MMC counters are updated
++ * due to any tx or rx frames until synopGMAC_mmc_counters_resume is called.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_mmc_counters_stop(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterFreeze);
++	return;
++}
++/**
++ * Resumes the MMC counter updation.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_mmc_counters_resume(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterFreeze);
++	return;
++}
++/**
++ * Configures the MMC in Self clearing mode.
++ * Programs MMC interface so that counters are cleared when the counters are read.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_mmc_counters_set_selfclear(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterResetOnRead);
++	return;
++}
++/**
++ * Configures the MMC in non-Self clearing mode.
++ * Programs MMC interface so that counters are cleared when the counters are read.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_mmc_counters_reset_selfclear(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterResetOnRead);
++	return;
++}
++/**
++ * Configures the MMC to stop rollover.
++ * Programs MMC interface so that counters will not rollover after reaching maximum value.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_mmc_counters_disable_rollover(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterStopRollover);
++	return;
++}
++/**
++ * Configures the MMC to rollover.
++ * Programs MMC interface so that counters will rollover after reaching maximum value.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_mmc_counters_enable_rollover(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterStopRollover);
++	return;
++}
++
++/**
++ * Read the MMC Counter.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] the counter to be read.
++ * \return returns the read count value.
++ */
++u32 synopGMAC_read_mmc_counter(synopGMACdevice *gmacdev, u32 counter)
++{
++	return(	synopGMACReadReg((u32 *)gmacdev->MacBase,counter));
++}
++/**
++ * Read the MMC Rx interrupt status.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns the Rx interrupt status.
++ */
++u32 synopGMAC_read_mmc_rx_int_status(synopGMACdevice *gmacdev)
++{
++	return(	synopGMACReadReg((u32 *)gmacdev->MacBase,GmacMmcIntrRx));
++}
++/**
++ * Read the MMC Tx interrupt status.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns the Tx interrupt status.
++ */
++u32 synopGMAC_read_mmc_tx_int_status(synopGMACdevice *gmacdev)
++{
++	return(	synopGMACReadReg((u32 *)gmacdev->MacBase,GmacMmcIntrTx));
++}
++/**
++ * Disable the MMC Tx interrupt.
++ * The MMC tx interrupts are masked out as per the mask specified.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] tx interrupt bit mask for which interrupts needs to be disabled.
++ * \return returns void.
++ */
++void synopGMAC_disable_mmc_tx_interrupt(synopGMACdevice *gmacdev, u32 mask)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacMmcIntrMaskTx,mask);
++	return;
++}
++/**
++ * Enable the MMC Tx interrupt.
++ * The MMC tx interrupts are enabled as per the mask specified.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] tx interrupt bit mask for which interrupts needs to be enabled.
++ * \return returns void.
++ */
++void synopGMAC_enable_mmc_tx_interrupt(synopGMACdevice *gmacdev, u32 mask)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacMmcIntrMaskTx,mask);
++}
++/**
++ * Disable the MMC Rx interrupt.
++ * The MMC rx interrupts are masked out as per the mask specified.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] rx interrupt bit mask for which interrupts needs to be disabled.
++ * \return returns void.
++ */
++void synopGMAC_disable_mmc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacMmcIntrMaskRx,mask);
++	return;
++}
++/**
++ * Enable the MMC Rx interrupt.
++ * The MMC rx interrupts are enabled as per the mask specified.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] rx interrupt bit mask for which interrupts needs to be enabled.
++ * \return returns void.
++ */
++void synopGMAC_enable_mmc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacMmcIntrMaskRx,mask);
++	return;
++}
++/**
++ * Disable the MMC ipc rx checksum offload interrupt.
++ * The MMC ipc rx checksum offload interrupts are masked out as per the mask specified.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] rx interrupt bit mask for which interrupts needs to be disabled.
++ * \return returns void.
++ */
++void synopGMAC_disable_mmc_ipc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacMmcRxIpcIntrMask,mask);
++	return;
++}
++/**
++ * Enable the MMC ipc rx checksum offload interrupt.
++ * The MMC ipc rx checksum offload interrupts are enabled as per the mask specified.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] rx interrupt bit mask for which interrupts needs to be enabled.
++ * \return returns void.
++ */
++void synopGMAC_enable_mmc_ipc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacMmcRxIpcIntrMask,mask);
++	return;
++}
++/*******************MMC APIs***************************************/
++/*******************Ip checksum offloading APIs***************************************/
++
++/**
++ * Enables the ip checksum offloading in receive path.
++ * When set GMAC calculates 16 bit 1's complement of all received ethernet frame payload.
++ * It also checks IPv4 Header checksum is correct. GMAC core appends the 16 bit checksum calculated
++ * for payload of IP datagram and appends it to Ethernet frame transferred to the application.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_enable_rx_chksum_offload(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacConfig,GmacRxIpcOffload);
++	return;
++}
++/**
++ * Disable the ip checksum offloading in receive path.
++ * Ip checksum offloading is disabled in the receive path.
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_disable_rx_Ipchecksum_offload(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacConfig,GmacRxIpcOffload);
++}
++/**
++ * Instruct the DMA to drop the packets fails tcp ip checksum.
++ * This is to instruct the receive DMA engine to drop the recevied packet if they
++ * fails the tcp/ip checksum in hardware. Valid only when full checksum offloading is enabled(type-2).
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_rx_tcpip_chksum_drop_enable(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->DmaBase,DmaControl,DmaDisableDropTcpCs);
++	return;
++}
++/**
++ * Instruct the DMA not to drop the packets even if it fails tcp ip checksum.
++ * This is to instruct the receive DMA engine to allow the packets even if recevied packet
++ * fails the tcp/ip checksum in hardware. Valid only when full checksum offloading is enabled(type-2).
++ * @param[in] pointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->DmaBase,DmaControl,DmaDisableDropTcpCs);
++	return;
++}
++
++/**
++ * When the Enhanced Descriptor is enabled then the bit 0 of RDES0 indicates whether the
++ * Extended Status is available (RDES4). Time Stamp feature and the Checksum Offload Engine2
++ * makes use of this extended status to provide the status of the received packet.
++ * @param[in] pointer to synopGMACdevice
++ * \return returns TRUE or FALSE
++ */
++#ifdef ENH_DESC_8W
++
++/**
++ * This function indicates whether extended status is available in the RDES0.
++ * Any function which accesses the fields of extended status register must ensure a check on this has been made
++ * This is valid only for Enhanced Descriptor.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] u32 status field of the corresponding descriptor.
++ * \return returns TRUE or FALSE.
++ */
++bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status) 		      // extended status present indicates that the RDES4 need to be probed
++{
++	return((status & DescRxEXTsts ) != 0 ); // if extstatus set then it returns 1
++}
++/**
++ * This function returns true if the IP header checksum bit is set in the extended status.
++ * Valid only when enhaced status available is set in RDES0 bit 0.
++ * This is valid only for Enhanced Descriptor.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] u32 status field of the corresponding descriptor.
++ * \return returns TRUE or FALSE.
++ */
++bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status)          // IP header (IPV4) checksum error
++{
++	return((ext_status & DescRxIpHeaderError) != 0 ); // if IPV4 header error return 1
++}
++/**
++ * This function returns true if the Checksum is bypassed in the hardware.
++ * Valid only when enhaced status available is set in RDES0 bit 0.
++ * This is valid only for Enhanced Descriptor.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] u32 status field of the corresponding descriptor.
++ * \return returns TRUE or FALSE.
++ */
++bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev,u32 ext_status)     // Hardware engine bypassed the checksum computation/checking
++{
++	return((ext_status & DescRxChkSumBypass ) != 0 ); // if checksum offloading bypassed return 1
++}
++/**
++ * This function returns true if payload checksum error is set in the extended status.
++ * Valid only when enhaced status available is set in RDES0 bit 0.
++ * This is valid only for Enhanced Descriptor.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] u32 status field of the corresponding descriptor.
++ * \return returns TRUE or FALSE.
++ */
++bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status)         // IP payload checksum is in error (UDP/TCP/ICMP checksum error)
++{
++	return((ext_status & DescRxIpPayloadError) != 0 ); // if IP payload error return 1
++}
++#endif
++
++
++
++/**
++ * Decodes the Rx Descriptor status to various checksum error conditions.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] u32 status field of the corresponding descriptor.
++ * \return returns decoded enum (u32) indicating the status.
++ */
++u32 synopGMAC_is_rx_checksum_error(synopGMACdevice *gmacdev, u32 status)
++{
++	if     (((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0))
++		return RxLenLT600;
++	else if(((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0))
++		return RxIpHdrPayLoadChkBypass;
++	else if(((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0))
++		return RxChkBypass;
++	else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0))
++		return RxNoChkError;
++	else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0))
++		return RxPayLoadChkError;
++	else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) == 0))
++		return RxIpHdrChkError;
++	else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0))
++		return RxIpHdrPayLoadChkError;
++	else
++		return RxIpHdrPayLoadRes;
++}
++/**
++ * Checks if any Ipv4 header checksum error in the frame just transmitted.
++ * This serves as indication that error occureed in the IPv4 header checksum insertion.
++ * The sent out frame doesnot carry any ipv4 header checksum inserted by the hardware.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] u32 status field of the corresponding descriptor.
++ * \return returns true if error in ipv4 header checksum, else returns false.
++ */
++bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 status)
++{
++	return((status & DescTxIpv4ChkError) == DescTxIpv4ChkError);
++}
++
++
++/**
++ * Checks if any payload checksum error in the frame just transmitted.
++ * This serves as indication that error occureed in the payload checksum insertion.
++ * The sent out frame doesnot carry any payload checksum inserted by the hardware.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] u32 status field of the corresponding descriptor.
++ * \return returns true if error in ipv4 header checksum, else returns false.
++ */
++bool synopGMAC_is_tx_payload_checksum_error(synopGMACdevice *gmacdev, u32 status)
++{
++	return((status & DescTxPayChkError) == DescTxPayChkError);
++}
++/**
++ * The check summ offload engine is bypassed in the tx path.
++ * Checksum is not computed in the Hardware.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] Pointer to tx descriptor for which  ointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *desc)
++{
++#ifdef ENH_DESC
++	desc->status = (desc->length & (~DescTxCisMask));//ENH_DESC
++#else
++	desc->length = (desc->length & (~DescTxCisMask));
++#endif
++
++}
++/**
++ * The check summ offload engine is enabled to do only IPV4 header checksum.
++ * IPV4 header Checksum is computed in the Hardware.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] Pointer to tx descriptor for which  ointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *desc)
++{
++#ifdef ENH_DESC
++	desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisIpv4HdrCs);//ENH_DESC
++#else
++	desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisIpv4HdrCs);
++#endif
++
++}
++
++/**
++ * The check summ offload engine is enabled to do TCPIP checsum assuming Pseudo header is available.
++ * Hardware computes the tcp ip checksum assuming pseudo header checksum is computed in software.
++ * Ipv4 header checksum is also inserted.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] Pointer to tx descriptor for which  ointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *desc)
++{
++#ifdef ENH_DESC
++	desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisTcpOnlyCs);//ENH_DESC
++#else
++	desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpOnlyCs);
++#endif
++
++}
++/**
++ * The check summ offload engine is enabled to do complete checksum computation.
++ * Hardware computes the tcp ip checksum including the pseudo header checksum.
++ * Here the tcp payload checksum field should be set to 0000.
++ * Ipv4 header checksum is also inserted.
++ * @param[in] pointer to synopGMACdevice.
++ * @param[in] Pointer to tx descriptor for which  ointer to synopGMACdevice.
++ * \return returns void.
++ */
++void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc *desc)
++{
++#ifdef ENH_DESC
++	desc->status = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpPseudoCs);
++#else
++	desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpPseudoCs);
++#endif
++
++}
++/*******************Ip checksum offloading APIs***************************************/
++
++
++
++
++
++/*******************IEEE 1588 Timestamping API***************************************/
++
++
++/*
++ * At this time the driver supports the IEEE time stamping feature when the Enhanced Descriptors are enabled.
++ * For normal descriptor and the IEEE time stamp (version 1), driver support is not proviced
++ * Please make sure you have enabled the Advanced timestamp feature in the hardware and the driver should
++ * be compiled with the ADV_TME_STAMP feature.
++ * Some of the APIs provided here may not be valid for all configurations. Please make sure you call the
++ * API with due care.
++ */
++
++/**
++ * This function enables the timestamping. This enables the timestamping for transmit and receive frames.
++ * When disabled timestamp is not added to tx and receive frames and timestamp generator is suspended.
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_enable(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSENA);
++	return;
++}
++/**
++ * This function disables the timestamping.
++ * When disabled timestamp is not added to tx and receive frames and timestamp generator is suspended.
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_disable(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl, GmacTSENA);
++	return;
++}
++
++
++/**
++ * Enable the interrupt to get timestamping interrupt.
++ * This enables the host to get the interrupt when (1) system time is greater or equal to the
++ * target time high and low register or (2) there is a overflow in th esecond register.
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_int_enable(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask);
++	return;
++}
++
++/**
++ * Disable the interrupt to get timestamping interrupt.
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_int_disable(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask);
++	return;
++}
++
++/**
++ * Enable MAC address for PTP frame filtering.
++ * When enabled, uses MAC address (apart from MAC address 0) to filter the PTP frames when
++ * PTP is sent directly over Ethernet.
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_mac_addr_filt_enable(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSENMACADDR);
++	return;
++}
++
++/**
++ * Disables MAC address for PTP frame filtering.
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSENMACADDR);
++	return;
++}
++
++
++/**
++ * Selet the type of clock mode for PTP.
++ * Please note to use one of the follwoing as the clk_type argument.
++ * GmacTSOrdClk		  = 0x00000000,	     00=> Ordinary clock
++ * GmacTSBouClk		  = 0x00010000,	     01=> Boundary clock
++ * GmacTSEtoEClk		  = 0x00020000,	     10=> End-to-End transparent clock
++ * GmacTSPtoPClk		  = 0x00030000,	     11=> P-to-P transparent clock
++ * @param[in] pointer to synopGMACdevice
++ * @param[in] u32 value representing one of the above clk value
++ * \return returns void
++ */
++void synopGMAC_TS_set_clk_type(synopGMACdevice *gmacdev, u32 clk_type)
++{
++	u32 clkval;
++	clkval = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSControl); //set the mdc clock to the user defined value
++	clkval = clkval | clk_type;
++	synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSControl,clkval);
++	return;
++}
++
++/**
++ * Enable Snapshot for messages relevant to Master.
++ * When enabled, snapshot is taken for messages relevant to master mode only, else snapshot is taken for messages relevant
++ * to slave node.
++ * Valid only for Ordinary clock and Boundary clock
++ * Reserved when "Advanced Time Stamp" is not selected
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSMSTRENA);
++	return;
++}
++/**
++ * Disable Snapshot for messages relevant to Master.
++ * When disabled, snapshot is taken for messages relevant
++ * to slave node.
++ * Valid only for Ordinary clock and Boundary clock
++ * Reserved when "Advanced Time Stamp" is not selected
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSMSTRENA);
++	return;
++}
++/**
++ * Enable Snapshot for Event messages.
++ * When enabled, snapshot is taken for event messages only (SYNC, Delay_Req, Pdelay_Req or Pdelay_Resp)
++ * When disabled, snapshot is taken for all messages except Announce, Management and Signaling.
++ * Reserved when "Advanced Time Stamp" is not selected
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSEVNTENA);
++	return;
++}
++/**
++ * Disable Snapshot for Event messages.
++ * When disabled, snapshot is taken for all messages except Announce, Management and Signaling.
++ * Reserved when "Advanced Time Stamp" is not selected
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_event_disable(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSEVNTENA);
++	return;
++}
++
++/**
++ * Enable time stamp snapshot for IPV4 frames.
++ * When enabled, time stamp snapshot is taken for IPV4 frames
++ * Reserved when "Advanced Time Stamp" is not selected
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_IPV4_enable(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSIPV4ENA);
++	return;
++}
++/**
++ * Disable time stamp snapshot for IPV4 frames.
++ * When disabled, time stamp snapshot is not taken for IPV4 frames
++ * Reserved when "Advanced Time Stamp" is not selected
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_IPV4_disable(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSIPV4ENA);
++	return;
++}                    // Only for "Advanced Time Stamp"
++/**
++ * Enable time stamp snapshot for IPV6 frames.
++ * When enabled, time stamp snapshot is taken for IPV6 frames
++ * Reserved when "Advanced Time Stamp" is not selected
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_IPV6_enable(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSIPV6ENA);
++	return;
++}
++/**
++ * Disable time stamp snapshot for IPV6 frames.
++ * When disabled, time stamp snapshot is not taken for IPV6 frames
++ * Reserved when "Advanced Time Stamp" is not selected
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_IPV6_disable(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSIPV6ENA);
++	return;
++}
++
++/**
++ * Enable time stamp snapshot for PTP over Ethernet frames.
++ * When enabled, time stamp snapshot is taken for PTP over Ethernet frames
++ * Reserved when "Advanced Time Stamp" is not selected
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_ptp_over_ethernet_enable(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSIPENA);
++	return;
++}
++/**
++ * Disable time stamp snapshot for PTP over Ethernet frames.
++ * When disabled, time stamp snapshot is not taken for PTP over Ethernet frames
++ * Reserved when "Advanced Time Stamp" is not selected
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSIPENA);
++	return;
++}
++
++
++/**
++ * Snoop PTP packet for version 2 format
++ * When set the PTP packets are snooped using the version 2 format.
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_pkt_snoop_ver2(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSVER2ENA);
++	return;
++}
++/**
++ * Snoop PTP packet for version 2 format
++ * When set the PTP packets are snooped using the version 2 format.
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_pkt_snoop_ver1(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSVER2ENA);
++	return;
++}
++
++/**
++ * Timestamp digital rollover
++ * When set the timestamp low register rolls over after 0x3B9A_C9FF value.
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSCTRLSSR);
++	return;
++}
++/**
++ * Timestamp binary rollover
++ * When set the timestamp low register rolls over after 0x7FFF_FFFF value.
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSCTRLSSR);
++	return;
++}
++/**
++ * Enable Time Stamp for All frames
++ * When set the timestamp snap shot is enabled for all frames received by the core.
++ * Reserved when "Advanced Time Stamp" is not selected
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSENALL);
++	return;
++}
++/**
++ * Disable Time Stamp for All frames
++ * When reset the timestamp snap shot is not enabled for all frames received by the core.
++ * Reserved when "Advanced Time Stamp" is not selected
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSENALL);
++	return;
++}
++/**
++ * Addend Register Update
++ * This function loads the contents of Time stamp addend register with the supplied 32 value.
++ * This is reserved function when only coarse correction option is selected
++ * @param[in] pointer to synopGMACdevice
++ * @param[in] 32 bit addend value
++ * \return returns 0 for Success or else Failure
++ */
++s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value)
++{
++	u32 loop_variable;
++	synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSAddend,addend_value);// Load the addend_value in to Addend register
++	for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
++		if(!((synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSControl)) & GmacTSADDREG)){ // if it is cleared then break
++			break;
++		}
++		plat_delay(DEFAULT_DELAY_VARIABLE);
++	}
++	if(loop_variable < DEFAULT_LOOP_VARIABLE)
++		synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSADDREG);
++	else{
++		TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
++		return -ESYNOPGMACPHYERR;
++	}
++	return -ESYNOPGMACNOERR;
++
++}
++/**
++ * time stamp Update
++ * This function updates (adds/subtracts) with the value specified in the Timestamp High Update and
++ * Timestamp Low Update register.
++ * @param[in] pointer to synopGMACdevice
++ * @param[in] Timestamp High Update value
++ * @param[in] Timestamp Low Update value
++ * \return returns 0 for Success or else Failure
++ */
++s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 low_value)
++{
++	u32 loop_variable;
++	synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register
++	synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register
++	for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
++		if(!((synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSControl)) & GmacTSUPDT)){ // if it is cleared then break
++			break;
++		}
++		plat_delay(DEFAULT_DELAY_VARIABLE);
++	}
++	if(loop_variable < DEFAULT_LOOP_VARIABLE)
++		synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSUPDT);
++	else{
++		TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
++		return -ESYNOPGMACPHYERR;
++	}
++	return -ESYNOPGMACNOERR;
++}
++
++/**
++ * time stamp Initialize
++ * This function Loads/Initializes h the value specified in the Timestamp High Update and
++ * Timestamp Low Update register.
++ * @param[in] pointer to synopGMACdevice
++ * @param[in] Timestamp High Load value
++ * @param[in] Timestamp Low Load value
++ * \return returns 0 for Success or else Failure
++ */
++s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 low_value)
++{
++	u32 loop_variable;
++	synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register
++	synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register
++	for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
++		if(!((synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSControl)) & GmacTSINT)){ // if it is cleared then break
++			break;
++		}
++		plat_delay(DEFAULT_DELAY_VARIABLE);
++	}
++	if(loop_variable < DEFAULT_LOOP_VARIABLE)
++		synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSINT);
++	else{
++		TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
++		return -ESYNOPGMACPHYERR;
++	}
++	return -ESYNOPGMACNOERR;
++}
++
++/**
++ * Time Stamp Update Coarse
++ * When reset the timestamp update is done using coarse method.
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSCFUPDT);
++	return;
++}
++/**
++ * Time Stamp Update Fine
++ * When reset the timestamp update is done using Fine method.
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSCFUPDT);
++	return;
++}
++
++/**
++ * Load the Sub Second Increment value in to Sub Second increment register
++ * @param[in] pointer to synopGMACdevice
++ * \return returns void
++ */
++void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_value)
++{
++	synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSSubSecIncr,(sub_sec_inc_value & GmacSSINCMsk));
++	return;
++}
++/**
++ * Reads the time stamp contents in to the respective pointers
++ * These registers are readonly.
++ * This function returns the 48 bit time stamp assuming Version 2 timestamp with higher word is selected.
++ * @param[in] pointer to synopGMACdevice
++ * @param[in] pointer to hold 16 higher bit second register contents
++ * @param[in] pointer to hold 32 bit second register contents
++ * @param[in] pointer to hold 32 bit subnanosecond register contents
++ * \return returns void
++ * \note Please note that since the atomic access to the timestamp registers is not possible,
++ *  the contents read may be different from the actual time stamp.
++ */
++void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, u32 * sec_val, u32 *  sub_sec_val)
++{
++	* higher_sec_val = (u16)(synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask);
++	* sec_val        = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSHigh);
++	* sub_sec_val    = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSLow);
++	return;
++}
++/**
++ * Loads the time stamp higher sec value from the value supplied
++ * @param[in] pointer to synopGMACdevice
++ * @param[in] 16 higher bit second register contents passed as 32 bit value
++ * \return returns void
++ */
++void synopGMAC_TS_load_timestamp_higher_val(synopGMACdevice *gmacdev, u32 higher_sec_val)
++{
++	synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSHighWord, (higher_sec_val & GmacTSHighWordMask));
++	return;
++}
++/**
++ * Reads the time stamp higher sec value to respective pointers
++ * @param[in] pointer to synopGMACdevice
++ * @param[in] pointer to hold 16 higher bit second register contents
++ * \return returns void
++ */
++void synopGMAC_TS_read_timestamp_higher_val(synopGMACdevice *gmacdev, u16 * higher_sec_val)
++{
++	* higher_sec_val = (u16)(synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask);
++	return;
++}
++/**
++ * Load the Target time stamp registers
++ * This function Loads the target time stamp registers with the values proviced
++ * @param[in] pointer to synopGMACdevice
++ * @param[in] target Timestamp High value
++ * @param[in] target Timestamp Low  value
++ * \return returns 0 for Success or else Failure
++ */
++void synopGMAC_TS_load_target_timestamp(synopGMACdevice *gmacdev, u32 sec_val, u32 sub_sec_val)
++{
++	synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSTargetTimeHigh,sec_val);
++	synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSTargetTimeLow,sub_sec_val);
++	return;
++}
++/**
++ * Reads the Target time stamp registers
++ * This function Loads the target time stamp registers with the values proviced
++ * @param[in] pointer to synopGMACdevice
++ * @param[in] pointer to hold target Timestamp High value
++ * @param[in] pointer to hold target Timestamp Low  value
++ * \return returns 0 for Success or else Failure
++ */
++void synopGMAC_TS_read_target_timestamp(synopGMACdevice *gmacdev, u32 * sec_val, u32 * sub_sec_val)
++{
++	* sec_val     = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSTargetTimeHigh);
++	* sub_sec_val = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSTargetTimeLow);
++	return;
++}
++
++#ifdef AVB_SUPPORT
++void  synopGMACsetAvType(synopGMACdevice *gmacdev, u32 avtype)
++{
++	u32 orig_data;
++	orig_data = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacAvMacCtrl);
++	orig_data &= (~ GmacAvTypeMask);
++	orig_data |= avtype;
++	synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacAvMacCtrl ,orig_data);
++}
++
++void synopGMACsetAvPrio(synopGMACdevice * gmacdev,u8 priority){ //set the Avpriority tag
++	u32 orig_data;
++	orig_data = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacAvMacCtrl);
++	orig_data &= (~ GmacAvPrio);
++	orig_data |= (priority << 16);
++	synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacAvMacCtrl ,orig_data);
++
++}
++void synopGMACsetAvCtrlCh(synopGMACdevice * gmacdev,u8 channel)
++{//set the Av control Channel
++	u32 orig_data;
++	orig_data = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacAvMacCtrl);
++	orig_data &= (~ GmacAvCtrlCh);
++	orig_data |= (channel << 24);
++	synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacAvMacCtrl ,orig_data);
++
++}
++void synopGMACsetAvPTPCh (synopGMACdevice * gmacdev,u8 channel)
++{//set the Av control Channel
++	u32 orig_data;
++	orig_data = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacAvMacCtrl);
++	orig_data &= (~ GmacPtpCh);
++	orig_data |= (channel << 24);
++	synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacAvMacCtrl ,orig_data);
++
++}
++
++void synopGMACsetTxRxPrioPolicy(synopGMACdevice * gmacdev,u8 policy)
++{ //0=>RR 1=>Strict priority
++	if(policy)
++		synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaBusMode , DmaArbitrationStrict);
++	else
++		synopGMACClearBits((u32 *)gmacdev->DmaBase, DmaBusMode , DmaArbitrationStrict);
++}
++void synopGMACsetTxRxPrio(synopGMACdevice * gmacdev,u8 tx_has_high_prio)
++{ //0=>RR 1=>Strict priority
++	if(tx_has_high_prio)
++		synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaBusMode , DmaTxRxPrio );
++	else
++		synopGMACClearBits((u32 *)gmacdev->DmaBase, DmaBusMode , DmaTxRxPrio  );
++}
++void synopGMACsetTxRxPrioRatio(synopGMACdevice * gmacdev,u8 tx_rx_prio_ratio)
++{ //0=>RR 1=>Strict prioriyt
++
++	synopGMACClearBits((u32 *)gmacdev->DmaBase, DmaBusMode , DmaPriorityRatio41);
++	if(tx_rx_prio_ratio == 0)
++		synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaBusMode , DmaPriorityRatio11);
++	if(tx_rx_prio_ratio == 1)
++		synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaBusMode , DmaPriorityRatio21);
++	if(tx_rx_prio_ratio == 2)
++		synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaBusMode , DmaPriorityRatio31);
++	if(tx_rx_prio_ratio == 3)
++		synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaBusMode , DmaPriorityRatio41);
++}
++void synopGMACsetChPrioWts(synopGMACdevice * gmacdev,u8 weights)
++{
++	synopGMACClearBits((u32 *)gmacdev->DmaBase, DmaBusMode , DmaChannelPrioWt);
++	if(weights == 1)
++		synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaBusMode,  DmaChannelPrio1);
++	if(weights == 2)
++		synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaBusMode,  DmaChannelPrio2);
++	if(weights == 3)
++		synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaBusMode,  DmaChannelPrio3);
++	if(weights == 4)
++		synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaBusMode,  DmaChannelPrio4);
++}
++
++void synopGMACAvbEnSlot(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaSlotFnCtrlSts , EnaSlot);
++}
++void synopGMACAvbDisSlot (synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->DmaBase, DmaSlotFnCtrlSts , EnaSlot);
++}
++void synopGMACAvbEnAdvSlotInt(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaSlotFnCtrlSts , AdvSlotInt );
++}
++void synopGMACAvbDisAdvSlotInt(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->DmaBase, DmaSlotFnCtrlSts , AdvSlotInt );
++}
++void synopGMACAvbSetSlotCount(synopGMACdevice * gmacdev, u8 slotcount)
++{
++	u32 orig_data;
++	orig_data = synopGMACReadReg((u32 *)gmacdev->DmaBase,DmaChannelCtrl);
++	orig_data &= (~ ChannelSlotCount);
++	if(slotcount == 1 )
++		orig_data |= 0x00000000;
++	if(slotcount == 2 )
++		orig_data |= 0x00000010;
++	if(slotcount == 4 )
++		orig_data |= 0x00000020;
++	if(slotcount == 8 )
++		orig_data |= 0x00000030;
++	if(slotcount == 16 )
++		orig_data |= 0x00000040;
++
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaChannelCtrl,orig_data);
++
++	TR("CH1 SLOT COUNT = %08x\n",synopGMACReadReg((u32 *)gmacdev->DmaBase,DmaChannelCtrl));
++
++}
++
++void synopGMACAvbEnSlotInterrupt(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaChannelCtrl, ChannelSlotIntEn);
++}
++void synopGMACAvbDisSlotInterrupt(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->DmaBase, DmaChannelCtrl, ChannelSlotIntEn);
++}
++void synopGMACAvbEnableCrSh(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->DmaBase, DmaChannelCtrl, ChannelCreditShDis);
++}
++void synopGMACAvbDisableCrSh(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaChannelCtrl, ChannelCreditShDis);
++}
++void synopGMACAvbEnableCrControl(synopGMACdevice * gmacdev)
++{
++	synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaChannelCtrl, ChannelCreditCtrl);
++}
++void synopGMACAvbDisableCrControl(synopGMACdevice * gmacdev)
++{
++	synopGMACClearBits((u32 *)gmacdev->DmaBase, DmaChannelCtrl, ChannelCreditCtrl);
++}
++
++void synopGMACsetAvbSendSlope(synopGMACdevice * gmacdev,u32 sendslope_val)
++{
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, SendSlopeCredit,(ChannelSendSlCr & sendslope_val ));
++}
++void synopGMACsetAvbIdleSlope(synopGMACdevice * gmacdev,u32 idleslope_val)
++{
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, IdleSlopeCredit,(ChannelIdleSlCr & idleslope_val ));
++}
++void synopGMACsetAvbHiCredit(synopGMACdevice * gmacdev,u32 hicredit_val)
++{
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, HighCredit ,(ChannelHiCr  & hicredit_val));
++}
++void synopGMACsetAvbLoCredit(synopGMACdevice * gmacdev,u32 locredit_val)
++{
++	synopGMACWriteReg((u32 *)gmacdev->DmaBase, LoCredit ,(ChannelLoCr  & locredit_val));
++}
++#endif
+diff --git a/module_drivers/drivers/net/ethernet/ingenic/synopGMAC_Dev.h b/module_drivers/drivers/net/ethernet/ingenic/synopGMAC_Dev.h
+new file mode 100644
+index 000000000..08f7c1238
+--- /dev/null
++++ b/module_drivers/drivers/net/ethernet/ingenic/synopGMAC_Dev.h
+@@ -0,0 +1,2011 @@
++/* ===================================================================================
++ * Copyright (c) <2009> Synopsys, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a copy of
++ * this software annotated with this license and associated documentation files
++ * (the "Software"), to deal in the Software without restriction, including without
++ * limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the Software is
++ * furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in all
++ * copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * =================================================================================== */
++
++/**\file
++ * This file defines the function prototypes for the Synopsys GMAC device and the
++ * Marvell 88E1011/88E1011S integrated 10/100/1000 Gigabit Ethernet Transceiver.
++ * Since the phy register mapping are standardised, the phy register map and the
++ * bit definitions remain the same for other phy as well.
++ * This also defines some of the Ethernet related parmeters.
++ * \internal
++ *  -----------------------------REVISION HISTORY------------------------------------
++ * Synopsys			   01/Aug/2007				Created
++ */
++
++
++#ifndef SYNOP_GMAC_DEV_H
++#define SYNOP_GMAC_DEV_H 1
++
++#include "synopGMAC_plat.h"
++
++/*SynopGMAC can support up to 32 phys*/
++
++enum GMACPhyBase
++{
++	PHY0  = 0,			//The device can support 32 phys, but we use first phy only
++	PHY31 = 31,
++};
++
++#define DEFAULT_PHY_BASE (PHY0 + 16)		//We use First Phy
++#define MACBASE 0x0000			// The Mac Base address offset is 0x0000
++#define DMABASE 0x1000			// Dma base address starts with an offset 0x1000
++
++#ifdef AVB_SUPPORT
++#define DMABASE_CH0 DMABASE     // DMA base address for Channel 0
++#define DMABASE_CH1 0x1100      // DMA base address for Channel 1
++#define DMABASE_CH2 0x1200      // DMA base address for Channel 2
++
++#define ETHERNET_HEADER_AVB     18	//6 byte Dest addr, 6 byte Src addr, 2 byte length/type
++
++#endif
++
++
++//#define TRANSMIT_DESC_SIZE  256		//Tx Descriptors needed in the Descriptor pool/queue
++//#define RECEIVE_DESC_SIZE   256 	//Rx Descriptors needed in the Descriptor pool/queue
++#define TRANSMIT_DESC_SIZE  12//256	//Tx Descriptors needed in the Descriptor pool/queue
++#define RECEIVE_DESC_SIZE   12//256	//Rx Descriptors needed in the Descriptor pool/queue
++
++#define ETHERNET_HEADER             14	//6 byte Dest addr, 6 byte Src addr, 2 byte length/type
++#define ETHERNET_CRC                 4	//Ethernet CRC
++#define ETHERNET_EXTRA		     2  //Only God knows about this?????
++#define ETHERNET_PACKET_COPY	   250  // Maximum length when received data is copied on to a new skb
++#define ETHERNET_PACKET_EXTRA	    18  // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA
++#define VLAN_TAG		     4  //optional 802.1q VLAN Tag
++#define MIN_ETHERNET_PAYLOAD        46  //Minimum Ethernet payload size
++#define MAX_ETHERNET_PAYLOAD      1500  //Maximum Ethernet payload size
++#define JUMBO_FRAME_PAYLOAD       9000  //Jumbo frame payload size
++
++#define TX_BUF_SIZE        ETHERNET_HEADER + ETHERNET_CRC + MAX_ETHERNET_PAYLOAD + VLAN_TAG
++
++
++// This is the IP's phy address. This is unique address for every MAC in the universe
++#define DEFAULT_MAC_ADDRESS {0x00, 0x55, 0x7B, 0xB5, 0x7D, 0xF7}
++
++/*
++   DMA Descriptor Structure
++   The structure is common for both receive and transmit descriptors
++   The descriptor is of 4 words, but our structrue contains 6 words where
++   last two words are to hold the virtual address of the network buffer pointers
++   for driver's use
++   From the GMAC core release 3.50a onwards, the Enhanced Descriptor structure got changed.
++   The descriptor (both transmit and receive) are of 8 words each rather the 4 words of normal
++   descriptor structure.
++   Whenever IEEE 1588 Timestamping is enabled TX/RX DESC6 provides the lower 32 bits of Timestamp value and
++   TX/RX DESC7 provides the upper 32 bits of Timestamp value
++   In addition to this whenever extended status bit is set (RX DESC0 bit 0), RX DESC4 contains the extended status information
++   */
++
++#define MODULO_INTERRUPT   1 // if it is set to 1, interrupt is available for all the descriptors or else interrupt is available only for
++// descriptor whose index%MODULO_INTERRUPT is zero
++#ifdef ENH_DESC_8W
++typedef struct DmaDescStruct
++{
++	u32   status;         /* Status 									*/
++	u32   length;         /* Buffer 1  and Buffer 2 length 						*/
++	u32   buffer1;        /* Network Buffer 1 pointer (Dma-able) 							*/
++	u32   buffer2;        /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure 	*/
++	/* This data below is used only by driver					*/
++	u32   extstatus;      /* Extended status of a Rx Descriptor                                           */
++	u32   reserved1;      /* Reserved word                                                                */
++	u32   timestamplow;   /* Lower 32 bits of the 64 bit timestamp value                                  */
++	u32   timestamphigh;  /* Higher 32 bits of the 64 bit timestamp value                                  */
++	u32   data1;          /* This holds virtual address of buffer1, not used by DMA  			*/
++	u32   data2;          /* This holds virtual address of buffer2, not used by DMA  			*/
++}__packed __aligned(8) DmaDesc;
++#else
++typedef struct DmaDescStruct
++{
++	u32   status;         /* Status 									*/
++	u32   length;         /* Buffer 1  and Buffer 2 length 						*/
++	u32   buffer1;        /* Network Buffer 1 pointer (Dma-able) 							*/
++	u32   buffer2;        /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure 	*/
++	/* This data below is used only by driver					*/
++	u32   data1;          /* This holds virtual address of buffer1, not used by DMA  			*/
++	u32   data2;          /* This holds virtual address of buffer2, not used by DMA  			*/
++}__packed __aligned(8) DmaDesc;
++#endif
++
++enum DescMode
++{
++	RINGMODE	= 0x00000001,
++	CHAINMODE	= 0x00000002,
++};
++
++enum BufferMode
++{
++	SINGLEBUF	= 0x00000001,
++	DUALBUF		= 0x00000002,
++};
++
++/* synopGMAC device data */
++
++typedef struct synopGMACDeviceStruct
++{
++	u32 MacBase; 		         /* base address of MAC registers           */
++	u32 DmaBase;         		 /* base address of DMA registers           */
++	u32 PhyBase;          	 /* PHY device address on MII interface     */
++	u32 Version;	                 /* Gmac Revision version	                */
++
++
++	dma_addr_t TxDescDma;		 /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/
++	dma_addr_t RxDescDma; 	 /* Dma-albe address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/
++	DmaDesc *TxDesc;               /* start address of TX descriptors ring or chain, this is used by the driver  */
++	DmaDesc *RxDesc;               /* start address of RX descriptors ring or chain, this is used by the driver  */
++
++	u32 BusyTxDesc;	         /* Number of Tx Descriptors owned by DMA at any given time*/
++	u32 BusyRxDesc;		 /* Number of Rx Descriptors owned by DMA at any given time*/
++
++	u32  RxDescCount;              /* number of rx descriptors in the tx descriptor queue/pool */
++	u32  TxDescCount;              /* number of tx descriptors in the rx descriptor queue/pool */
++
++	u32  TxBusy;                   /* index of the tx descriptor owned by DMA, is obtained by synopGMAC_get_tx_qptr()                */
++	u32  TxNext;                   /* index of the tx descriptor next available with driver, given to DMA by synopGMAC_set_tx_qptr() */
++	u32  RxBusy;                   /* index of the rx descriptor owned by DMA, obtained by synopGMAC_get_rx_qptr()                   */
++	u32  RxNext;                   /* index of the rx descriptor next available with driver, given to DMA by synopGMAC_set_rx_qptr() */
++
++	DmaDesc * TxBusyDesc;          /* Tx Descriptor address corresponding to the index TxBusy */
++	DmaDesc * TxNextDesc;          /* Tx Descriptor address corresponding to the index TxNext */
++	DmaDesc * RxBusyDesc;          /* Rx Descriptor address corresponding to the index TxBusy */
++	DmaDesc * RxNextDesc;          /* Rx Descriptor address corresponding to the index RxNext */
++
++
++	/*Phy related stuff*/
++	u32 ClockDivMdc;		 /* Clock divider value programmed in the hardware           */
++	/* The status of the link */
++	u32 LinkState;		 /* Link status as reported by the Marvel Phy                */
++	u32 DuplexMode;                /* Duplex mode of the Phy				    */
++	u32 Speed;			 /* Speed of the Phy					    */
++	u32 LoopBackMode; 		 /* Loopback status of the Phy				    */
++
++} synopGMACdevice;
++
++#ifdef AVB_SUPPORT
++typedef struct AVBStruct
++{
++	u8 ChSelMask;             /* This gives which DMA channel is enabled and which is disabled
++								 Bit0 for Ch0
++								 Bit1 for Ch1
++								 Bit2 for Ch2
++								 */
++	u8 DurationOfExp;         /* Duration for which experiment should be conducted in minutes - Default 2 Minutes */
++
++	u8 AvControlCh;           /* channel on which AV control channel must be received (Not used)*/
++	u8 PTPCh;                 /* Channel on which PTP packets must be received (Not Used)*/
++	u8 PrioTagForAV;          /* Used when more than One channel enabled in Rx path (Not Used)
++								 for only CH1 Enabled:
++								 Frames sith Priority > Value programmed, frames sent to CH1
++								 Frames with priority < Value programmed are sent to CH0
++								 For both CH1 and CH2 Enabled:
++								 Frames sith Priority > Value programmed, frames sent to CH2
++								 Frames with priority < Value programmed are sent to CH1
++								 */
++
++	u16 AvType;                /* AV Ethernet Type to be programmed for Core to identify AV type */
++
++	u8 Ch1PrioWts;
++	u8 Ch1Bw;
++	u32 Ch1_frame_size;
++	u8 Ch1_EnableSlotCheck;    /* Enable checking of slot numbers programmed in the Tx Desc*/
++	u8 Ch1_AdvSlotInterval;    /* When Set Data fetched for current slot and for next 2 slots in advance
++								  When reset data fetched for current slot and in advance for next slot*/
++
++	u8  Ch1CrSh;        /* When set Enables the credit based traffic shaping. Now works with Strict priority style*/
++	u8  Ch1SlotCount;          /* Over which transmiteed bits per slot needs to be computed (Only for Credit based shaping) */
++	u32 Ch1AvgBitsPerSlot;     /* Average bits per slot reported by core once in Ch1SlotCount * 125 micro seconds */
++	u32 Ch1AvgBitsPerSlotAccL;  /* No of Avg Bits per slot on Channel1*/
++	u32 Ch1AvgBitsPerSlotAccH;  /* No of Avg Bits per slot on Channel1*/
++	u32 Ch1AvgBitsNoOfInterrupts;  /* Total Number of interrupts over which AvbBits are accumulated*/
++
++	u8  Ch1CreditControl;      /* Will be zero (Not used) */
++
++	u8 Ch1_tx_rx_prio_policy;   // Should Ch1 use Strict or RR policy
++	u8 Ch1_use_tx_high_prio;    // Should Ch1 Tx have High priority over Rx
++	u8 Ch1_tx_rx_prio_ratio;    // For Round Robin what is the ratio between tx-rx or rx-tx
++
++	u8 Ch1_tx_desc_slot_no_start;
++	u8 Ch1_tx_desc_slot_no_skip;
++
++	u32 Ch1SendSlope;
++	u32 Ch1IdleSlope;
++	u32 Ch1HiCredit;
++	u32 Ch1LoCredit;
++
++	u32 Ch1FramecountTx;         /* No of Frames Transmitted on Channel 1 */
++	u32 Ch1FramecountRx;         /* No of Frames Received on Channel 1 */
++
++	u8 Ch2PrioWts;
++	u8 Ch2Bw;
++	u32 Ch2_frame_size;
++	u8 Ch2_EnableSlotCheck;    /* Enable checking of slot numbers programmed in the Tx Desc*/
++	u8 Ch2_AdvSlotInterval;    /* When Set Data fetched for current slot and for next 2 slots in advance
++								  When reset data fetched for current slot and in advance for next slot*/
++	u8  Ch2CrSh;        /* When set Enables the credit based traffic shaping. Now works with Strict priority style*/
++	u8  Ch2SlotCount;          /* Over which transmiteed bits per slot needs to be computed (Only for Credit based shaping) */
++	u32 Ch2AvgBitsPerSlot;     /* Average bits per slot reported by core once in Ch2SlotCount * 125 micro seconds */
++	u32 Ch2AvgBitsPerSlotAccL;  /* No of Avg Bits per slot on Channel2*/
++	u32 Ch2AvgBitsPerSlotAccH;  /* No of Avg Bits per slot on Channel2*/
++	u32 Ch2AvgBitsNoOfInterrupts; /* Total Number of interrupts over which AvbBits are accumulated*/
++
++	u8  Ch2CreditControl;      /* Will be zero at present*/
++
++	u8 Ch2_tx_rx_prio_policy;   // Should Ch1 use Strict or RR policy
++	u8 Ch2_use_tx_high_prio;    // Should Ch1 Tx have High priority over Rx
++	u8 Ch2_tx_rx_prio_ratio;    // For Round Robin what is the ratio between tx-rx or rx-tx
++
++
++	u8 Ch2_tx_desc_slot_no_start;
++	u8 Ch2_tx_desc_slot_no_skip;
++
++	u32 Ch2SendSlope;
++	u32 Ch2IdleSlope;
++	u32 Ch2HiCredit;
++	u32 Ch2LoCredit;
++
++	u32 Ch2FramecountTx;         /* No of Frames Transmitted on Channel 2 */
++	u32 Ch2FramecountRx;         /* No of Frames Received on Channel 2 */
++
++	u8 Ch0PrioWts;
++	u8 Ch0_tx_rx_prio_policy;   // Should Ch1 use Strict or RR policy
++	u8 Ch0_use_tx_high_prio;    // Should Ch1 Tx have High priority over Rx
++	u8 Ch0_tx_rx_prio_ratio;    // For Round Robin what is the ratio between tx-rx or rx-tx
++
++	u32 Ch0_frame_size;
++	u32 Ch0FramecountTx;         /* No of Frames Transmitted on Channel 0 */
++	u32 Ch0FramecountRx;         /* No of Frames Received on Channel 0 */
++
++} synopGMACavbStruct;
++#endif
++
++/* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver"
++ * Register and their layouts. This Phy has been used in the Dot Aster GMAC Phy daughter.
++ * Since the Phy register map is standard, this map hardly changes to a different Ppy
++ */
++
++enum MiiRegisters
++{
++	PHY_CONTROL_REG           = 0x0000,		/*Control Register*/
++	PHY_STATUS_REG            = 0x0001,		/*Status Register */
++	PHY_ID_HI_REG             = 0x0002,		/*PHY Identifier High Register*/
++	PHY_ID_LOW_REG            = 0x0003,		/*PHY Identifier High Register*/
++	PHY_AN_ADV_REG            = 0x0004,		/*Auto-Negotiation Advertisement Register*/
++	PHY_LNK_PART_ABl_REG      = 0x0005,		/*Link Partner Ability Register (Base Page)*/
++	PHY_AN_EXP_REG            = 0x0006,		/*Auto-Negotiation Expansion Register*/
++	PHY_AN_NXT_PAGE_TX_REG    = 0x0007,		/*Next Page Transmit Register*/
++	PHY_LNK_PART_NXT_PAGE_REG = 0x0008,		/*Link Partner Next Page Register*/
++	PHY_1000BT_CTRL_REG       = 0x0009,		/*1000BASE-T Control Register*/
++	PHY_1000BT_STATUS_REG     = 0x000a,		/*1000BASE-T Status Register*/
++	PHY_SPECIFIC_CTRL_REG     = 0x0010,		/*Phy specific control register*/
++	PHY_SPECIFIC_STATUS_REG   = 0x0011,		/*Phy specific status register*/
++	PHY_INTERRUPT_ENABLE_REG  = 0x0012,		/*Phy interrupt enable register*/
++	PHY_INTERRUPT_STATUS_REG  = 0x0013,		/*Phy interrupt status register*/
++	PHY_EXT_PHY_SPC_CTRL	    = 0x0014,		/*Extended Phy specific control*/
++	PHY_RX_ERR_COUNTER	    = 0x0015,		/*Receive Error Counter*/
++	PHY_EXT_ADDR_CBL_DIAG     = 0x0016,		/*Extended address for cable diagnostic register*/
++	PHY_LED_CONTROL	    = 0x0018,		/*LED Control*/
++	PHY_MAN_LED_OVERIDE       = 0x0019,		/*Manual LED override register*/
++	PHY_EXT_PHY_SPC_CTRL2     = 0x001a,		/*Extended Phy specific control 2*/
++	PHY_EXT_PHY_SPC_STATUS    = 0x001b,		/*Extended Phy specific status*/
++	PHY_CBL_DIAG_REG	    = 0x001c,		/*Cable diagnostic registers*/
++};
++
++
++/* This is Control register layout. Control register is of 16 bit wide.
++*/
++
++enum Mii_GEN_CTRL
++{		                      /*	Description	               bits	       R/W	default value  */
++	Mii_reset		 = 0x8000,
++	Mii_Speed_10   		 = 0x0000,   /* 10   Mbps                    6:13         	RW                      */
++	Mii_Speed_100   	 = 0x2000,   /* 100  Mbps                    6:13         	RW                      */
++	Mii_Speed_1000 		 = 0x0040,   /* 1000 Mbit/s                  6:13         	RW                      */
++
++	Mii_Duplex     		 = 0x0100,   /* Full Duplex mode             8               	RW                      */
++
++	Mii_Manual_Master_Config = 0x0800,   /* Manual Master Config         11              	RW			*/
++
++	Mii_Loopback   		 = 0x4000,   /* Enable Loop back             14              	RW                      */
++	Mii_NoLoopback 		 = 0x0000,   /* Enable Loop back             14              	RW                      */
++};
++
++enum Mii_Phy_Status
++{
++	Mii_phy_status_speed_10	 	= 0x0000,
++	Mii_phy_status_speed_100  	= 0x4000,
++	Mii_phy_status_speed_1000	= 0x8000,
++
++	Mii_phy_status_full_duplex	= 0x2000,
++	Mii_phy_status_half_duplex	= 0x0000,
++
++	Mii_phy_status_link_up		= 0x0400,
++};
++/* This is Status register layout. Status register is of 16 bit wide.
++*/
++enum Mii_GEN_STATUS
++{
++	Mii_AutoNegCmplt     = 0x0020,   /* Autonegotiation completed      5              RW                   */
++	Mii_Link             = 0x0004,   /* Link status                    2              RW                   */
++};
++
++enum Mii_Link_Status
++{
++	LINKDOWN	= 0,
++	LINKUP		= 1,
++};
++
++enum Mii_Duplex_Mode
++{
++	HALFDUPLEX = 1,
++	FULLDUPLEX = 2,
++};
++enum Mii_Link_Speed
++{
++	SPEED10     = 1,
++	SPEED100    = 2,
++	SPEED1000   = 3,
++};
++
++enum Mii_Loop_Back
++{
++	NOLOOPBACK  = 0,
++	LOOPBACK    = 1,
++};
++
++
++
++/**********************************************************
++ * GMAC registers Map
++ * For Pci based system address is BARx + GmacRegisterBase
++ * For any other system translation is done accordingly
++ **********************************************************/
++enum GmacRegisters
++{
++	GmacConfig     	  = 0x0000,    /* Mac config Register                       */
++	GmacFrameFilter  	  = 0x0004,    /* Mac frame filtering controls              */
++	GmacHashHigh     	  = 0x0008,    /* Multi-cast hash table high                */
++	GmacHashLow      	  = 0x000C,    /* Multi-cast hash table low                 */
++	GmacGmiiAddr     	  = 0x0010,    /* GMII address Register(ext. Phy)           */
++	GmacGmiiData     	  = 0x0014,    /* GMII data Register(ext. Phy)              */
++	GmacFlowControl  	  = 0x0018,    /* Flow control Register                     */
++	GmacVlan         	  = 0x001C,    /* VLAN tag Register (IEEE 802.1Q)           */
++
++	GmacVersion     	  = 0x0020,    /* GMAC Core Version Register                */
++	GmacWakeupAddr  	  = 0x0028,    /* GMAC wake-up frame filter adrress reg     */
++	GmacPmtCtrlStatus  	  = 0x002C,    /* PMT control and status register           */
++
++#ifdef LPI_SUPPORT
++	GmacLPICtrlSts      = 0x0030,    /* LPI (low power idle) Control and Status Register          */
++	GmacLPITimerCtrl    = 0x0034,    /* LPI timer control register               */
++#endif
++
++	GmacInterruptStatus	  = 0x0038,    /* Mac Interrupt ststus register	       */
++	GmacInterruptMask       = 0x003C,    /* Mac Interrupt Mask register	       */
++
++	GmacAddr0High    	  = 0x0040,    /* Mac address0 high Register                */
++	GmacAddr0Low    	  = 0x0044,    /* Mac address0 low Register                 */
++	GmacAddr1High    	  = 0x0048,    /* Mac address1 high Register                */
++	GmacAddr1Low     	  = 0x004C,    /* Mac address1 low Register                 */
++	GmacAddr2High   	  = 0x0050,    /* Mac address2 high Register                */
++	GmacAddr2Low     	  = 0x0054,    /* Mac address2 low Register                 */
++	GmacAddr3High    	  = 0x0058,    /* Mac address3 high Register                */
++	GmacAddr3Low     	  = 0x005C,    /* Mac address3 low Register                 */
++	GmacAddr4High    	  = 0x0060,    /* Mac address4 high Register                */
++	GmacAddr4Low     	  = 0x0064,    /* Mac address4 low Register                 */
++	GmacAddr5High    	  = 0x0068,    /* Mac address5 high Register                */
++	GmacAddr5Low     	  = 0x006C,    /* Mac address5 low Register                 */
++	GmacAddr6High    	  = 0x0070,    /* Mac address6 high Register                */
++	GmacAddr6Low     	  = 0x0074,    /* Mac address6 low Register                 */
++	GmacAddr7High    	  = 0x0078,    /* Mac address7 high Register                */
++	GmacAddr7Low     	  = 0x007C,    /* Mac address7 low Register                 */
++	GmacAddr8High    	  = 0x0080,    /* Mac address8 high Register                */
++	GmacAddr8Low     	  = 0x0084,    /* Mac address8 low Register                 */
++	GmacAddr9High    	  = 0x0088,    /* Mac address9 high Register                */
++	GmacAddr9Low      	  = 0x008C,    /* Mac address9 low Register                 */
++	GmacAddr10High          = 0x0090,    /* Mac address10 high Register               */
++	GmacAddr10Low    	  = 0x0094,    /* Mac address10 low Register                */
++	GmacAddr11High   	  = 0x0098,    /* Mac address11 high Register               */
++	GmacAddr11Low    	  = 0x009C,    /* Mac address11 low Register                */
++	GmacAddr12High   	  = 0x00A0,    /* Mac address12 high Register               */
++	GmacAddr12Low     	  = 0x00A4,    /* Mac address12 low Register                */
++	GmacAddr13High   	  = 0x00A8,    /* Mac address13 high Register               */
++	GmacAddr13Low   	  = 0x00AC,    /* Mac address13 low Register                */
++	GmacAddr14High   	  = 0x00B0,    /* Mac address14 high Register               */
++	GmacAddr14Low        	  = 0x00B4,    /* Mac address14 low Register                */
++	GmacAddr15High     	  = 0x00B8,    /* Mac address15 high Register               */
++	GmacAddr15Low  	  = 0x00BC,    /* Mac address15 low Register                */
++
++	GmacRGMIIControl        = 0x00D8,    /* SGMII/RGMII/SMII Control and Status Register */
++
++	/*Time Stamp Register Map*/
++	GmacTSControl	          = 0x0700,  /* Controls the Timestamp update logic                         : only when IEEE 1588 time stamping is enabled in corekit            */
++
++	GmacTSSubSecIncr     	  = 0x0704,  /* 8 bit value by which sub second register is incremented     : only when IEEE 1588 time stamping without external timestamp input */
++
++	GmacTSHigh  	          = 0x0708,  /* 32 bit seconds(MS)                                          : only when IEEE 1588 time stamping without external timestamp input */
++	GmacTSLow   	          = 0x070C,  /* 32 bit nano seconds(MS)                                     : only when IEEE 1588 time stamping without external timestamp input */
++
++	GmacTSHighUpdate        = 0x0710,  /* 32 bit seconds(MS) to be written/added/subtracted           : only when IEEE 1588 time stamping without external timestamp input */
++	GmacTSLowUpdate         = 0x0714,  /* 32 bit nano seconds(MS) to be writeen/added/subtracted      : only when IEEE 1588 time stamping without external timestamp input */
++
++	GmacTSAddend            = 0x0718,  /* Used by Software to readjust the clock frequency linearly   : only when IEEE 1588 time stamping without external timestamp input */
++
++	GmacTSTargetTimeHigh 	  = 0x071C,  /* 32 bit seconds(MS) to be compared with system time          : only when IEEE 1588 time stamping without external timestamp input */
++	GmacTSTargetTimeLow     = 0x0720,  /* 32 bit nano seconds(MS) to be compared with system time     : only when IEEE 1588 time stamping without external timestamp input */
++
++	GmacTSHighWord          = 0x0724,  /* Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid                                                   */
++	//GmacTSHighWordUpdate    = 0x072C,  /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid                                            */
++
++	GmacTSStatus            = 0x0728,  /* Time Stamp Status Register                                                                                                       */
++#ifdef AVB_SUPPORT
++	GmacAvMacCtrl            = 0x0738,  /* AV mac control Register  */
++#endif
++
++};
++
++/**********************************************************
++ * GMAC Network interface registers
++ * This explains the Register's Layout
++
++ * FES is Read only by default and is enabled only when Tx
++ * Config Parameter is enabled for RGMII/SGMII interface
++ * during CoreKit Config.
++
++ * DM is Read only with value 1'b1 in Full duplex only Config
++ **********************************************************/
++
++/* GmacConfig              = 0x0000,    Mac config Register  Layout */
++enum GmacConfigReg
++{
++	/* Bit description                      Bits         R/W   Reset value  */
++	GmacWatchdog		   = 0x00800000,
++	GmacWatchdogDisable      = 0x00800000,     /* (WD)Disable watchdog timer on Rx      23           RW                */
++	GmacWatchdogEnable       = 0x00000000,     /* Enable watchdog timer                                        0       */
++
++	GmacJabber		   = 0x00400000,
++	GmacJabberDisable        = 0x00400000,     /* (JD)Disable jabber timer on Tx        22           RW                */
++	GmacJabberEnable         = 0x00000000,     /* Enable jabber timer                                          0       */
++
++	GmacFrameBurst           = 0x00200000,
++	GmacFrameBurstEnable     = 0x00200000,     /* (BE)Enable frame bursting during Tx   21           RW                */
++	GmacFrameBurstDisable    = 0x00000000,     /* Disable frame bursting                                       0       */
++
++	GmacJumboFrame           = 0x00100000,
++	GmacJumboFrameEnable     = 0x00100000,     /* (JE)Enable jumbo frame for Tx         20           RW                */
++	GmacJumboFrameDisable    = 0x00000000,     /* Disable jumbo frame                                          0       */
++
++	GmacInterFrameGap        = 0x000E0000,
++	GmacInterFrameGap7       = 0x000E0000,     /* (IFG) Config7 - 40 bit times          19:17        RW                */
++	GmacInterFrameGap6       = 0x000C0000,     /* (IFG) Config6 - 48 bit times                                         */
++	GmacInterFrameGap5       = 0x000A0000,     /* (IFG) Config5 - 56 bit times                                         */
++	GmacInterFrameGap4       = 0x00080000,     /* (IFG) Config4 - 64 bit times                                         */
++	GmacInterFrameGap3       = 0x00040000,     /* (IFG) Config3 - 72 bit times                                         */
++	GmacInterFrameGap2       = 0x00020000,     /* (IFG) Config2 - 80 bit times                                         */
++	GmacInterFrameGap1       = 0x00010000,     /* (IFG) Config1 - 88 bit times                                         */
++	GmacInterFrameGap0       = 0x00000000,     /* (IFG) Config0 - 96 bit times                                 000     */
++
++	GmacDisableCrs	   = 0x00010000,
++	GmacMiiGmii		   = 0x00008000,
++	GmacSelectMii            = 0x00008000,     /* (PS)Port Select-MII mode              15           RW                */
++	GmacSelectGmii           = 0x00000000,     /* GMII mode                                                    0       */
++
++	GmacFESpeed100           = 0x00004000,     /*(FES)Fast Ethernet speed 100Mbps       14           RW                */
++	GmacFESpeed10            = 0x00000000,     /* 10Mbps                                                       0       */
++
++	GmacRxOwn		   = 0x00002000,
++	GmacDisableRxOwn         = 0x00002000,     /* (DO)Disable receive own packets       13           RW                */
++	GmacEnableRxOwn          = 0x00000000,     /* Enable receive own packets                                   0       */
++
++	GmacLoopback		   = 0x00001000,
++	GmacLoopbackOn           = 0x00001000,     /* (LM)Loopback mode for GMII/MII        12           RW                */
++	GmacLoopbackOff          = 0x00000000,     /* Normal mode                                                  0       */
++
++	GmacDuplex		   = 0x00000800,
++	GmacFullDuplex           = 0x00000800,     /* (DM)Full duplex mode                  11           RW                */
++	GmacHalfDuplex           = 0x00000000,     /* Half duplex mode                                             0       */
++
++	GmacRxIpcOffload	   = 0x00000400,     /*IPC checksum offload		      10           RW        0       */
++
++	GmacRetry		   = 0x00000200,
++	GmacRetryDisable         = 0x00000200,     /* (DR)Disable Retry                      9           RW                */
++	GmacRetryEnable          = 0x00000000,     /* Enable retransmission as per BL                              0       */
++
++	GmacLinkUp               = 0x00000100,     /* (LUD)Link UP                           8           RW                */
++	GmacLinkDown             = 0x00000100,     /* Link Down                                                    0       */
++
++	GmacPadCrcStrip	   = 0x00000080,
++	GmacPadCrcStripEnable    = 0x00000080,     /* (ACS) Automatic Pad/Crc strip enable   7           RW                */
++	GmacPadCrcStripDisable   = 0x00000000,     /* Automatic Pad/Crc stripping disable                          0       */
++
++	GmacBackoffLimit	   = 0x00000060,
++	GmacBackoffLimit3        = 0x00000060,     /* (BL)Back-off limit in HD mode          6:5         RW                */
++	GmacBackoffLimit2        = 0x00000040,     /*                                                                      */
++	GmacBackoffLimit1        = 0x00000020,     /*                                                                      */
++	GmacBackoffLimit0        = 0x00000000,     /*                                                              00      */
++
++	GmacDeferralCheck	   = 0x00000010,
++	GmacDeferralCheckEnable  = 0x00000010,     /* (DC)Deferral check enable in HD mode   4           RW                */
++	GmacDeferralCheckDisable = 0x00000000,     /* Deferral check disable                                       0       */
++
++	GmacTx		   = 0x00000008,
++	GmacTxEnable             = 0x00000008,     /* (TE)Transmitter enable                 3           RW                */
++	GmacTxDisable            = 0x00000000,     /* Transmitter disable                                          0       */
++
++	GmacRx		   = 0x00000004,
++	GmacRxEnable             = 0x00000004,     /* (RE)Receiver enable                    2           RW                */
++	GmacRxDisable            = 0x00000000,     /* Receiver disable                                             0       */
++};
++
++/* GmacFrameFilter    = 0x0004,     Mac frame filtering controls Register Layout*/
++enum GmacFrameFilterReg
++{
++	GmacFilter		   = 0x80000000,
++	GmacFilterOff            = 0x80000000,     /* (RA)Receive all incoming packets       31         RW                 */
++	GmacFilterOn             = 0x00000000,     /* Receive filtered packets only                                0       */
++
++	GmacHashPerfectFilter	   = 0x00000400,     /*Hash or Perfect Filter enable           10         RW         0       */
++
++	GmacSrcAddrFilter	   = 0x00000200,
++	GmacSrcAddrFilterEnable  = 0x00000200,     /* (SAF)Source Address Filter enable       9         RW                 */
++	GmacSrcAddrFilterDisable = 0x00000000,     /*                                                              0       */
++
++	GmacSrcInvaAddrFilter    = 0x00000100,
++	GmacSrcInvAddrFilterEn   = 0x00000100,     /* (SAIF)Inv Src Addr Filter enable        8         RW                 */
++	GmacSrcInvAddrFilterDis  = 0x00000000,     /*                                                              0       */
++
++	GmacPassControl	   = 0x000000C0,
++	GmacPassControl3         = 0x000000C0,     /* (PCS)Forwards ctrl frms that pass AF    7:6       RW                 */
++	GmacPassControl2         = 0x00000080,     /* Forwards all control frames                                          */
++	GmacPassControl1         = 0x00000040,     /* Does not pass control frames                                         */
++	GmacPassControl0         = 0x00000000,     /* Does not pass control frames                                 00      */
++
++	GmacBroadcast		   = 0x00000020,
++	GmacBroadcastDisable     = 0x00000020,     /* (DBF)Disable Rx of broadcast frames     5         RW                 */
++	GmacBroadcastEnable      = 0x00000000,     /* Enable broadcast frames                                      0       */
++
++	GmacMulticastFilter      = 0x00000010,
++	GmacMulticastFilterOff   = 0x00000010,     /* (PM) Pass all multicast packets         4         RW                 */
++	GmacMulticastFilterOn    = 0x00000000,     /* Pass filtered multicast packets                              0       */
++
++	GmacDestAddrFilter       = 0x00000008,
++	GmacDestAddrFilterInv    = 0x00000008,     /* (DAIF)Inverse filtering for DA          3         RW                 */
++	GmacDestAddrFilterNor    = 0x00000000,     /* Normal filtering for DA                                      0       */
++
++	GmacMcastHashFilter      = 0x00000004,
++	GmacMcastHashFilterOn    = 0x00000004,     /* (HMC)perfom multicast hash filtering    2         RW                 */
++	GmacMcastHashFilterOff   = 0x00000000,     /* perfect filtering only                                       0       */
++
++	GmacUcastHashFilter      = 0x00000002,
++	GmacUcastHashFilterOn    = 0x00000002,     /* (HUC)Unicast Hash filtering only        1         RW                 */
++	GmacUcastHashFilterOff   = 0x00000000,     /* perfect filtering only                                       0       */
++
++	GmacPromiscuousMode      = 0x00000001,
++	GmacPromiscuousModeOn    = 0x00000001,     /* Receive all frames                      0         RW                 */
++	GmacPromiscuousModeOff   = 0x00000000,     /* Receive filtered packets only                                0       */
++};
++
++
++/*GmacGmiiAddr             = 0x0010,    GMII address Register(ext. Phy) Layout          */
++enum GmacGmiiAddrReg
++{
++	GmiiDevMask              = 0x0000F800,     /* (PA)GMII device address                 15:11     RW         0x00    */
++	GmiiDevShift             = 11,
++
++	GmiiRegMask              = 0x000007C0,     /* (GR)GMII register in selected Phy       10:6      RW         0x00    */
++	GmiiRegShift             = 6,
++
++	GmiiCsrClkMask	   = 0x0000001C,     /*CSR Clock bit Mask			 4:2			     */
++	GmiiCsrClk5              = 0x00000014,     /* (CR)CSR Clock Range     250-300 MHz      4:2      RW         000     */
++	GmiiCsrClk4              = 0x00000010,     /*                         150-250 MHz                                  */
++	GmiiCsrClk3              = 0x0000000C,     /*                         35-60 MHz                                    */
++	GmiiCsrClk2              = 0x00000008,     /*                         20-35 MHz                                    */
++	GmiiCsrClk1              = 0x00000004,     /*                         100-150 MHz                                  */
++	GmiiCsrClk0              = 0x00000000,     /*                         60-100 MHz                                   */
++
++	GmiiWrite                = 0x00000002,     /* (GW)Write to register                      1      RW                 */
++	GmiiRead                 = 0x00000000,     /* Read from register                                            0      */
++
++	GmiiBusy                 = 0x00000001,     /* (GB)GMII interface is busy                 0      RW          0      */
++};
++
++/* GmacGmiiData            = 0x0014,    GMII data Register(ext. Phy) Layout             */
++enum GmacGmiiDataReg
++{
++	GmiiDataMask             = 0x0000FFFF,     /* (GD)GMII Data                             15:0    RW         0x0000  */
++};
++
++
++/*GmacFlowControl    = 0x0018,    Flow control Register   Layout                  */
++enum GmacFlowControlReg
++{
++	GmacPauseTimeMask        = 0xFFFF0000,     /* (PT) PAUSE TIME field in the control frame  31:16   RW       0x0000  */
++	GmacPauseTimeShift       = 16,
++
++	GmacPauseLowThresh	   = 0x00000030,
++	GmacPauseLowThresh3      = 0x00000030,     /* (PLT)thresh for pause tmr 256 slot time      5:4    RW               */
++	GmacPauseLowThresh2      = 0x00000020,     /*                           144 slot time                              */
++	GmacPauseLowThresh1      = 0x00000010,     /*                            28 slot time                              */
++	GmacPauseLowThresh0      = 0x00000000,     /*                             4 slot time                       000    */
++
++	GmacUnicastPauseFrame    = 0x00000008,
++	GmacUnicastPauseFrameOn  = 0x00000008,     /* (UP)Detect pause frame with unicast addr.     3    RW                */
++	GmacUnicastPauseFrameOff = 0x00000000,     /* Detect only pause frame with multicast addr.                   0     */
++
++	GmacRxFlowControl	   = 0x00000004,
++	GmacRxFlowControlEnable  = 0x00000004,     /* (RFE)Enable Rx flow control                   2    RW                */
++	GmacRxFlowControlDisable = 0x00000000,     /* Disable Rx flow control                                        0     */
++
++	GmacTxFlowControl   	   = 0x00000002,
++	GmacTxFlowControlEnable  = 0x00000002,     /* (TFE)Enable Tx flow control                   1    RW                */
++	GmacTxFlowControlDisable = 0x00000000,     /* Disable flow control                                           0     */
++
++	GmacFlowControlBackPressure= 0x00000001,
++	GmacSendPauseFrame       = 0x00000001,     /* (FCB/PBA)send pause frm/Apply back pressure   0    RW          0     */
++};
++
++/*  GmacInterruptStatus	  = 0x0038,     Mac Interrupt ststus register	       */
++enum GmacInterruptStatusBitDefinition
++{
++	GmacLPIIS		   = 0x00000400,    /* set if int generated in LPI Interrupt Status	*/
++	GmacTSIntSts		   = 0x00000200,    /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/
++	GmacMmcRxChksumOffload   = 0x00000080,    /* set if int generated in MMC RX CHECKSUM OFFLOAD int register	                  */
++	GmacMmcTxIntSts	   = 0x00000040,    /* set if int generated in MMC TX Int register			   */
++	GmacMmcRxIntSts	   = 0x00000020,    /* set if int generated in MMC RX Int register 			   */
++	GmacMmcIntSts		   = 0x00000010,    /* set if any of the above bit [7:5] is set			   */
++	GmacPmtIntSts		   = 0x00000008,    /* set whenver magic pkt/wake-on-lan frame is received		   */
++	GmacPcsAnComplete	   = 0x00000004,    /* set when AN is complete in TBI/RTBI/SGMIII phy interface        */
++	GmacPcsLnkStsChange	   = 0x00000002,    /* set if any lnk status change in TBI/RTBI/SGMII interface        */
++	GmacRgmiiIntSts	   = 0x00000001,    /* set if any change in lnk status of RGMII interface		   */
++
++};
++
++/*  GmacInterruptMask       = 0x003C,     Mac Interrupt Mask register	       */
++enum GmacInterruptMaskBitDefinition
++{
++	GmacTSIntMask		   = 0x00000200,    /* when set disables the time stamp interrupt generation            */
++	GmacPmtIntMask	   = 0x00000008,    /* when set Disables the assertion of PMT interrupt     	    	*/
++	GmacPcsAnIntMask	   = 0x00000004,    /* When set disables the assertion of PCS AN complete interrupt	      	*/
++	GmacPcsLnkStsIntMask	   = 0x00000002,    /* when set disables the assertion of PCS lnk status change interrupt	*/
++	GmacRgmiiIntMask	   = 0x00000001,    /* when set disables the assertion of RGMII int 			*/
++};
++
++/**********************************************************
++ * GMAC DMA registers
++ * For Pci based system address is BARx + GmaDmaBase
++ * For any other system translation is done accordingly
++ **********************************************************/
++
++enum DmaRegisters
++{
++	DmaBusMode        = 0x0000,    /* CSR0 - Bus Mode Register                          */
++	DmaTxPollDemand   = 0x0004,    /* CSR1 - Transmit Poll Demand Register              */
++	DmaRxPollDemand   = 0x0008,    /* CSR2 - Receive Poll Demand Register               */
++	DmaRxBaseAddr     = 0x000C,    /* CSR3 - Receive Descriptor list base address       */
++	DmaTxBaseAddr     = 0x0010,    /* CSR4 - Transmit Descriptor list base address      */
++	DmaStatus         = 0x0014,    /* CSR5 - Dma status Register                        */
++	DmaControl        = 0x0018,    /* CSR6 - Dma Operation Mode Register                */
++	DmaInterrupt      = 0x001C,    /* CSR7 - Interrupt enable                           */
++	DmaMissedFr       = 0x0020,    /* CSR8 - Missed Frame & Buffer overflow Counter     */
++	DmaAxiMode	  = 0x0028,    /* CSR10 -AXI Bus Mode Register			    */
++	DmaTxCurrDesc     = 0x0048,    /*      - Current host Tx Desc Register              */
++	DmaRxCurrDesc     = 0x004C,    /*      - Current host Rx Desc Register              */
++	DmaTxCurrAddr     = 0x0050,    /* CSR20 - Current host transmit buffer address      */
++	DmaRxCurrAddr     = 0x0054,    /* CSR21 - Current host receive buffer address       */
++
++#ifdef AVB_SUPPORT
++	HwFeature         = 0x0058,    /* Hardware Feature Register                         */
++
++	DmaSlotFnCtrlSts  = 0x0030,    /* Slot function control and status register         */
++
++	DmaChannelCtrl    = 0x0060,    /* Channel Control register only for Channel1 and Channel2 */
++	DmaChannelAvSts   = 0x0064,    /* Channel Status register only for Channel1 and  Channel2 */
++	IdleSlopeCredit   = 0x0068,    /* Idle slope credit register                              */
++	SendSlopeCredit   = 0x006C,    /* Send slope credit register                              */
++	HighCredit        = 0x0070,    /* High Credit register                                    */
++	LoCredit          = 0x0074,    /* Lo Credit Register                                      */
++#endif
++
++};
++
++/**********************************************************
++ * DMA Engine registers Layout
++ **********************************************************/
++
++/*DmaBusMode               = 0x0000,    CSR0 - Bus Mode */
++enum DmaBusModeReg
++{
++	/* Bit description                                Bits     R/W   Reset value */
++#ifdef AVB_SUPPORT
++	DmaChannelPrioWt       = 0x30000000,    /* Channel priority weight mask                     29:28    RW       0       */
++	DmaChannelPrio1        = 0x00000000,    /* Channel priority weight 1                        29:28    RW       0       */
++	DmaChannelPrio2        = 0x10000000,    /* Channel priority weight 2                        29:28    RW       0       */
++	DmaChannelPrio3        = 0x20000000,    /* Channel priority weight 3                        29:28    RW       0       */
++	DmaChannelPrio4        = 0x30000000,    /* Channel priority weight 4                        29:28    RW       0       */
++
++	DmaTxRxPrio            = 0x08000000,    /* When set indicates Tx Dma has more priority       27      RW        0       */
++
++	DmaPriorityRatio11     = 0x00000000,   /* (PR)TX:RX DMA priority ratio 1:1                15:14   RW        00      */
++	DmaPriorityRatio21     = 0x00004000,   /* (PR)TX:RX DMA priority ratio 2:1                                          */
++	DmaPriorityRatio31     = 0x00008000,   /* (PR)TX:RX DMA priority ratio 3:1                                          */
++	DmaPriorityRatio41     = 0x0000C000,   /* (PR)TX:RX DMA priority ratio 4:1                                          */
++
++	DmaArbitration         = 0x00000002,    /* Dma Arbitration decides whether strict prio or RR  1      RW       0       */
++	DmaArbitrationStrict   = 0x00000002,    /* Dma Arbitration decides whether strict prio or RR  1      RW       0       */
++	DmaArbitrationRR       = 0x00000000,    /* Dma Arbitration decides whether strict prio or RR  0      RW       0       */
++#endif
++
++
++	DmaFixedBurstEnable     = 0x00010000,   /* (FB)Fixed Burst SINGLE, INCR4, INCR8 or INCR16   16     RW                */
++	DmaFixedBurstDisable    = 0x00000000,   /*             SINGLE, INCR                                          0       */
++
++	DmaTxPriorityRatio11    = 0x00000000,   /* (PR)TX:RX DMA priority ratio 1:1                15:14   RW        00      */
++	DmaTxPriorityRatio21    = 0x00004000,   /* (PR)TX:RX DMA priority ratio 2:1                                          */
++	DmaTxPriorityRatio31    = 0x00008000,   /* (PR)TX:RX DMA priority ratio 3:1                                          */
++	DmaTxPriorityRatio41    = 0x0000C000,   /* (PR)TX:RX DMA priority ratio 4:1                                          */
++
++	DmaBurstLengthx8        = 0x01000000,   /* When set mutiplies the PBL by 8                  24      RW        0      */
++
++	DmaBurstLength256       = 0x01002000,   /*(DmaBurstLengthx8 | DmaBurstLength32) = 256      [24]:13:8                 */
++	DmaBurstLength128       = 0x01001000,   /*(DmaBurstLengthx8 | DmaBurstLength16) = 128      [24]:13:8                 */
++	DmaBurstLength64        = 0x01000800,   /*(DmaBurstLengthx8 | DmaBurstLength8) = 64        [24]:13:8                 */
++	DmaBurstLength32        = 0x00002000,   /* (PBL) programmable Dma burst length = 32        13:8    RW                */
++	DmaBurstLength16        = 0x00001000,   /* Dma burst length = 16                                                     */
++	DmaBurstLength8         = 0x00000800,   /* Dma burst length = 8                                                      */
++	DmaBurstLength4         = 0x00000400,   /* Dma burst length = 4                                                      */
++	DmaBurstLength2         = 0x00000200,   /* Dma burst length = 2                                                      */
++	DmaBurstLength1         = 0x00000100,   /* Dma burst length = 1                                                      */
++	DmaBurstLength0         = 0x00000000,   /* Dma burst length = 0                                               0x00   */
++
++	DmaDescriptor8Words     = 0x00000080,   /* Enh Descriptor works  1=> 8 word descriptor      7                  0    */
++	DmaDescriptor4Words     = 0x00000000,   /* Enh Descriptor works  0=> 4 word descriptor      7                  0    */
++
++	DmaDescriptorSkip16     = 0x00000040,   /* (DSL)Descriptor skip length (no.of dwords)       6:2     RW               */
++	DmaDescriptorSkip8      = 0x00000020,   /* between two unchained descriptors                                         */
++	DmaDescriptorSkip4      = 0x00000010,   /*                                                                           */
++	DmaDescriptorSkip2      = 0x00000008,   /*                                                                           */
++	DmaDescriptorSkip1      = 0x00000004,   /*                                                                           */
++	DmaDescriptorSkip0      = 0x00000000,   /*                                                                    0x00   */
++
++	DmaArbitRr              = 0x00000000,   /* (DA) DMA RR arbitration                            1     RW         0     */
++	DmaArbitPr              = 0x00000002,   /* Rx has priority over Tx                                                   */
++
++	DmaResetOn              = 0x00000001,   /* (SWR)Software Reset DMA engine                     0     RW               */
++	DmaResetOff             = 0x00000000,   /*                                                                      0    */
++};
++
++
++/*DmaStatus         = 0x0014,    CSR5 - Dma status Register                        */
++enum DmaStatusReg
++{
++	/*Bit 28 27 and 26 indicate whether the interrupt due to PMT GMACMMC or GMAC LINE Remaining bits are DMA interrupts*/
++
++#ifdef AVB_SUPPORT
++	DmaSlotCounterIntr      = 0x40000000,   /* For Ch1 and Ch2 AVB slot interrupt status          31     RW       0       */
++#endif
++#ifdef LPI_SUPPORT
++	GmacLPIIntr             = 0x40000000,   /* GMC LPI interrupt                                  31     RO       0       */
++#endif
++
++	GmacPmtIntr             = 0x10000000,   /* (GPI)Gmac subsystem interrupt                      28     RO       0       */
++	GmacMmcIntr             = 0x08000000,   /* (GMI)Gmac MMC subsystem interrupt                  27     RO       0       */
++	GmacLineIntfIntr        = 0x04000000,   /* Line interface interrupt                           26     RO       0       */
++
++	DmaErrorBit2            = 0x02000000,   /* (EB)Error bits 0-data buffer, 1-desc. access       25     RO       0       */
++	DmaErrorBit1            = 0x01000000,   /* (EB)Error bits 0-write trnsf, 1-read transfr       24     RO       0       */
++	DmaErrorBit0            = 0x00800000,   /* (EB)Error bits 0-Rx DMA, 1-Tx DMA                  23     RO       0       */
++
++	DmaTxState              = 0x00700000,   /* (TS)Transmit process state                         22:20  RO               */
++	DmaTxStopped            = 0x00000000,   /* Stopped - Reset or Stop Tx Command issued                         000      */
++	DmaTxFetching           = 0x00100000,   /* Running - fetching the Tx descriptor                                       */
++	DmaTxWaiting            = 0x00200000,   /* Running - waiting for status                                               */
++	DmaTxReading            = 0x00300000,   /* Running - reading the data from host memory                                */
++	DmaTxSuspended          = 0x00600000,   /* Suspended - Tx Descriptor unavailabe                                       */
++	DmaTxClosing            = 0x00700000,   /* Running - closing Rx descriptor                                            */
++
++	DmaRxState              = 0x000E0000,   /* (RS)Receive process state                         19:17  RO                */
++	DmaRxStopped            = 0x00000000,   /* Stopped - Reset or Stop Rx Command issued                         000      */
++	DmaRxFetching           = 0x00020000,   /* Running - fetching the Rx descriptor                                       */
++	DmaRxWaiting            = 0x00060000,   /* Running - waiting for packet                                               */
++	DmaRxSuspended          = 0x00080000,   /* Suspended - Rx Descriptor unavailable                                      */
++	DmaRxClosing            = 0x000A0000,   /* Running - closing descriptor                                               */
++	DmaRxQueuing            = 0x000E0000,   /* Running - queuing the recieve frame into host memory                       */
++
++	DmaIntNormal            = 0x00010000,   /* (NIS)Normal interrupt summary                     16     RW        0       */
++	DmaIntAbnormal          = 0x00008000,   /* (AIS)Abnormal interrupt summary                   15     RW        0       */
++
++	DmaIntEarlyRx           = 0x00004000,   /* Early receive interrupt (Normal)       RW        0       */
++	DmaIntBusError          = 0x00002000,   /* Fatal bus error (Abnormal)             RW        0       */
++	DmaIntEarlyTx           = 0x00000400,   /* Early transmit interrupt (Abnormal)    RW        0       */
++	DmaIntRxWdogTO          = 0x00000200,   /* Receive Watchdog Timeout (Abnormal)    RW        0       */
++	DmaIntRxStopped         = 0x00000100,   /* Receive process stopped (Abnormal)     RW        0       */
++	DmaIntRxNoBuffer        = 0x00000080,   /* Receive buffer unavailable (Abnormal)  RW        0       */
++	DmaIntRxCompleted       = 0x00000040,   /* Completion of frame reception (Normal) RW        0       */
++	DmaIntTxUnderflow       = 0x00000020,   /* Transmit underflow (Abnormal)          RW        0       */
++	DmaIntRcvOverflow       = 0x00000010,   /* Receive Buffer overflow interrupt      RW        0       */
++	DmaIntTxJabberTO        = 0x00000008,   /* Transmit Jabber Timeout (Abnormal)     RW        0       */
++	DmaIntTxNoBuffer        = 0x00000004,   /* Transmit buffer unavailable (Normal)   RW        0       */
++	DmaIntTxStopped         = 0x00000002,   /* Transmit process stopped (Abnormal)    RW        0       */
++	DmaIntTxCompleted       = 0x00000001,   /* Transmit completed (Normal)            RW        0       */
++};
++
++/*DmaControl        = 0x0018,     CSR6 - Dma Operation Mode Register                */
++enum DmaControlReg
++{
++	DmaDisableDropTcpCs	  = 0x04000000,   /* (DT) Dis. drop. of tcp/ip CS error frames        26      RW        0       */
++
++	DmaStoreAndForward      = 0x00200000,   /* (SF)Store and forward                            21      RW        0       */
++	DmaFlushTxFifo          = 0x00100000,   /* (FTF)Tx FIFO controller is reset to default      20      RW        0       */
++
++	DmaTxThreshCtrl         = 0x0001C000,   /* (TTC)Controls thre Threh of MTL tx Fifo          16:14   RW                */
++	DmaTxThreshCtrl16       = 0x0001C000,   /* (TTC)Controls thre Threh of MTL tx Fifo 16       16:14   RW                */
++	DmaTxThreshCtrl24       = 0x00018000,   /* (TTC)Controls thre Threh of MTL tx Fifo 24       16:14   RW                */
++	DmaTxThreshCtrl32       = 0x00014000,   /* (TTC)Controls thre Threh of MTL tx Fifo 32       16:14   RW                */
++	DmaTxThreshCtrl40       = 0x00010000,   /* (TTC)Controls thre Threh of MTL tx Fifo 40       16:14   RW                */
++	DmaTxThreshCtrl256      = 0x0000c000,   /* (TTC)Controls thre Threh of MTL tx Fifo 256      16:14   RW                */
++	DmaTxThreshCtrl192      = 0x00008000,   /* (TTC)Controls thre Threh of MTL tx Fifo 192      16:14   RW                */
++	DmaTxThreshCtrl128      = 0x00004000,   /* (TTC)Controls thre Threh of MTL tx Fifo 128      16:14   RW                */
++	DmaTxThreshCtrl64       = 0x00000000,   /* (TTC)Controls thre Threh of MTL tx Fifo 64       16:14   RW        000     */
++
++	DmaTxStart              = 0x00002000,   /* (ST)Start/Stop transmission                      13      RW        0       */
++
++	DmaRxFlowCtrlDeact      = 0x00401800,   /* (RFD)Rx flow control deact. threhold             [22]:12:11   RW                 */
++	DmaRxFlowCtrlDeact1K    = 0x00000000,   /* (RFD)Rx flow control deact. threhold (1kbytes)   [22]:12:11   RW        00       */
++	DmaRxFlowCtrlDeact2K    = 0x00000800,   /* (RFD)Rx flow control deact. threhold (2kbytes)   [22]:12:11   RW                 */
++	DmaRxFlowCtrlDeact3K    = 0x00001000,   /* (RFD)Rx flow control deact. threhold (3kbytes)   [22]:12:11   RW                 */
++	DmaRxFlowCtrlDeact4K    = 0x00001800,   /* (RFD)Rx flow control deact. threhold (4kbytes)   [22]:12:11   RW                 */
++	DmaRxFlowCtrlDeact5K    = 0x00400000,   /* (RFD)Rx flow control deact. threhold (4kbytes)   [22]:12:11   RW                 */
++	DmaRxFlowCtrlDeact6K    = 0x00400800,   /* (RFD)Rx flow control deact. threhold (4kbytes)   [22]:12:11   RW                 */
++	DmaRxFlowCtrlDeact7K    = 0x00401000,   /* (RFD)Rx flow control deact. threhold (4kbytes)   [22]:12:11   RW                 */
++
++	DmaRxFlowCtrlAct        = 0x00800600,   /* (RFA)Rx flow control Act. threhold              [23]:10:09   RW                 */
++	DmaRxFlowCtrlAct1K      = 0x00000000,   /* (RFA)Rx flow control Act. threhold (1kbytes)    [23]:10:09   RW        00       */
++	DmaRxFlowCtrlAct2K      = 0x00000200,   /* (RFA)Rx flow control Act. threhold (2kbytes)    [23]:10:09   RW                 */
++	DmaRxFlowCtrlAct3K      = 0x00000400,   /* (RFA)Rx flow control Act. threhold (3kbytes)    [23]:10:09   RW                 */
++	DmaRxFlowCtrlAct4K      = 0x00000600,   /* (RFA)Rx flow control Act. threhold (4kbytes)    [23]:10:09   RW                 */
++	DmaRxFlowCtrlAct5K      = 0x00800000,   /* (RFA)Rx flow control Act. threhold (5kbytes)    [23]:10:09   RW                 */
++	DmaRxFlowCtrlAct6K      = 0x00800200,   /* (RFA)Rx flow control Act. threhold (6kbytes)    [23]:10:09   RW                 */
++	DmaRxFlowCtrlAct7K      = 0x00800400,   /* (RFA)Rx flow control Act. threhold (7kbytes)    [23]:10:09   RW                 */
++
++	DmaRxThreshCtrl         = 0x00000018,   /* (RTC)Controls thre Threh of MTL rx Fifo          4:3   RW                */
++	DmaRxThreshCtrl64       = 0x00000000,   /* (RTC)Controls thre Threh of MTL tx Fifo 64       4:3   RW                */
++	DmaRxThreshCtrl32       = 0x00000008,   /* (RTC)Controls thre Threh of MTL tx Fifo 32       4:3   RW                */
++	DmaRxThreshCtrl96       = 0x00000010,   /* (RTC)Controls thre Threh of MTL tx Fifo 96       4:3   RW                */
++	DmaRxThreshCtrl128      = 0x00000018,   /* (RTC)Controls thre Threh of MTL tx Fifo 128      4:3   RW                */
++
++	DmaEnHwFlowCtrl         = 0x00000100,   /* (EFC)Enable HW flow control                      8       RW                 */
++	DmaDisHwFlowCtrl        = 0x00000000,   /* Disable HW flow control                                            0        */
++
++	DmaFwdErrorFrames       = 0x00000080,   /* (FEF)Forward error frames                        7       RW        0       */
++	DmaFwdUnderSzFrames     = 0x00000040,   /* (FUF)Forward undersize frames                    6       RW        0       */
++	DmaTxSecondFrame        = 0x00000004,   /* (OSF)Operate on second frame                     4       RW        0       */
++	DmaRxStart              = 0x00000002,   /* (SR)Start/Stop reception                         1       RW        0       */
++};
++
++
++/*DmaInterrupt      = 0x001C,    CSR7 - Interrupt enable Register Layout     */
++enum  DmaInterruptReg
++{
++	DmaIeNormal            = DmaIntNormal     ,   /* Normal interrupt enable                 RW        0       */
++	DmaIeAbnormal          = DmaIntAbnormal   ,   /* Abnormal interrupt enable               RW        0       */
++
++	DmaIeEarlyRx           = DmaIntEarlyRx    ,   /* Early receive interrupt enable          RW        0       */
++	DmaIeBusError          = DmaIntBusError   ,   /* Fatal bus error enable                  RW        0       */
++	DmaIeEarlyTx           = DmaIntEarlyTx    ,   /* Early transmit interrupt enable         RW        0       */
++	DmaIeRxWdogTO          = DmaIntRxWdogTO   ,   /* Receive Watchdog Timeout enable         RW        0       */
++	DmaIeRxStopped         = DmaIntRxStopped  ,   /* Receive process stopped enable          RW        0       */
++	DmaIeRxNoBuffer        = DmaIntRxNoBuffer ,   /* Receive buffer unavailable enable       RW        0       */
++	DmaIeRxCompleted       = DmaIntRxCompleted,   /* Completion of frame reception enable    RW        0       */
++	DmaIeTxUnderflow       = DmaIntTxUnderflow,   /* Transmit underflow enable               RW        0       */
++
++	DmaIeRxOverflow        = DmaIntRcvOverflow,   /* Receive Buffer overflow interrupt       RW        0       */
++	DmaIeTxJabberTO        = DmaIntTxJabberTO ,   /* Transmit Jabber Timeout enable          RW        0       */
++	DmaIeTxNoBuffer        = DmaIntTxNoBuffer ,   /* Transmit buffer unavailable enable      RW        0       */
++	DmaIeTxStopped         = DmaIntTxStopped  ,   /* Transmit process stopped enable         RW        0       */
++	DmaIeTxCompleted       = DmaIntTxCompleted,   /* Transmit completed enable               RW        0       */
++};
++
++#ifdef AVB_SUPPORT
++/*DmaSlotFnCtrlSts  = 0x0030,     Slot function control and status register         */
++enum DmaSlotFnCtrlStsReg
++{
++	SlotNum                = 0x000F0000,   /* Current Slot Number                            19:16     R0         0      */
++	AdvSlotInt             = 0x00000002,   /* Advance the slot interval for data fetch       1         RW         0      */
++	EnaSlot                = 0x00000001,   /* Enable checking of Slot number                 0         RW         0      */
++};
++
++/*  DmaChannelCtrl    = 0x0060,     Channel Control register only for Channel1 and Channel2 */
++enum DmaChannelCtrlReg
++{
++	ChannelSlotIntEn       = 0x00020000,   /* Channel Slot Interrupt Enable                  16         RW         0      */
++	ChannelSlotCount       = 0x00000070,   /* Channel Slot Count                             6:4        RW         0      */
++	ChannelCreditCtrl      = 0x00000002,   /* Channel Credit Control                         1          RW         0      */
++	ChannelCreditShDis     = 0x00000001,   /* Channel Credit based shaping disable           0          RW         0      */
++};
++
++/*  DmaChannelSts     = 0x0064,     Channel Status register only for Channel1 and  Channel2 */
++enum DmaChannelStsReg
++{
++	ChannelAvBitsPerSlot   = 0x0000FFFF,   /* Channel Average Bits per slot                  16:0       RO         0      */
++};
++
++/*  IdleSlopeCredit   = 0x0068,     Idle slope credit register                              */
++enum IdleSlopeCreditReg
++{
++	ChannelIdleSlCr       = 0x00003FFF,   /*Channel Idle Slope Credit                       13:0       RW         0     */
++};
++
++/*SendSlopeCredit   = 0x006C,     Send slope credit register                              */
++enum SendSlopeCreditReg
++{
++	ChannelSendSlCr       = 0x00003FFF,   /*Channel Send Slope Credit                       13:0       RW         0     */
++};
++
++/*  HighCredit        = 0x0070,     High Credit register                                    */
++enum HighCreditReg
++{
++	ChannelHiCr           = 0x1FFFFFFF,   /*Channel Hi Credit                               28:0       RW         0     */
++};
++
++/*  LoCredit          = 0x0074,     Lo Credit Register                                      */
++enum LoCreditReg
++{
++	ChannelLoCr           = 0x1FFFFFFF,   /* Channel Lo Credit                               28:0      RW         0    */
++};
++/*DmaChannelAvSts   */
++enum DmaChannelAvStsReg
++{
++	ChannelAvgBitsPerSlotMsk = 0x0001FFFF,
++};
++#endif
++
++/**********************************************************
++ * DMA Engine descriptors
++ **********************************************************/
++#ifdef ENH_DESC
++/*
++ **********Enhanced Descritpor structure to support 8K buffer per buffer ****************************
++
++ DmaRxBaseAddr     = 0x000C,   CSR3 - Receive Descriptor list base address
++ DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a
++ 32 bit Data bus is as shown below
++
++ Similarly
++ DmaTxBaseAddr     = 0x0010,  CSR4 - Transmit Descriptor list base address
++ DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a
++ 32 bit Data bus is as shown below
++ --------------------------------------------------------------------------
++ RDES0	  |OWN (31)| Status                                                        |
++ --------------------------------------------------------------------------
++ RDES1	  | Ctrl | Res | Byte Count Buffer 2 | Ctrl | Res | Byte Count Buffer 1    |
++ --------------------------------------------------------------------------
++ RDES2	  |  Buffer 1 Address                                                      |
++ --------------------------------------------------------------------------
++ RDES3	  |  Buffer 2 Address / Next Descriptor Address                            |
++ --------------------------------------------------------------------------
++
++ --------------------------------------------------------------------------
++ TDES0	  |OWN (31)| Ctrl | Res | Ctrl | Res | Status                              |
++ --------------------------------------------------------------------------
++ TDES1	  | Res | Byte Count Buffer 2 | Res |         Byte Count Buffer 1          |
++ --------------------------------------------------------------------------
++ TDES2	  |  Buffer 1 Address                                                      |
++ --------------------------------------------------------------------------
++ TDES3         |  Buffer 2 Address / Next Descriptor Address                            |
++ --------------------------------------------------------------------------
++
++*/
++
++enum DmaDescriptorStatus    /* status word of DMA descriptor */
++{
++
++	DescOwnByDma          = 0x80000000,   /* (OWN)Descriptor is owned by DMA engine              31      RW                  */
++
++	DescDAFilterFail      = 0x40000000,   /* (AFM)Rx - DA Filter Fail for the rx frame           30                          */
++
++	DescFrameLengthMask   = 0x3FFF0000,   /* (FL)Receive descriptor frame length                 29:16                       */
++	DescFrameLengthShift  = 16,
++
++	DescError             = 0x00008000,   /* (ES)Error summary bit  - OR of the follo. bits:     15                          */
++	/*  DE || OE || IPC || LC || RWT || RE || CE */
++	DescRxTruncated       = 0x00004000,   /* (DE)Rx - no more descriptors for receive frame      14                          */
++	DescSAFilterFail      = 0x00002000,   /* (SAF)Rx - SA Filter Fail for the received frame     13                          */
++	DescRxLengthError	    = 0x00001000,   /* (LE)Rx - frm size not matching with len field       12                          */
++	DescRxDamaged         = 0x00000800,   /* (OE)Rx - frm was damaged due to buffer overflow     11                          */
++	DescRxVLANTag         = 0x00000400,   /* (VLAN)Rx - received frame is a VLAN frame           10                          */
++	DescRxFirst           = 0x00000200,   /* (FS)Rx - first descriptor of the frame              9                          */
++	DescRxLast            = 0x00000100,   /* (LS)Rx - last descriptor of the frame               8                          */
++	DescRxLongFrame       = 0x00000080,   /* (Giant Frame)Rx - frame is longer than 1518/1522    7                          */
++	DescRxCollision       = 0x00000040,   /* (LC)Rx - late collision occurred during reception   6                          */
++	DescRxFrameEther      = 0x00000020,   /* (FT)Rx - Frame type - Ethernet, otherwise 802.3     5                          */
++	DescRxWatchdog        = 0x00000010,   /* (RWT)Rx - watchdog timer expired during reception   4                          */
++	DescRxMiiError        = 0x00000008,   /* (RE)Rx - error reported by MII interface            3                          */
++	DescRxDribbling       = 0x00000004,   /* (DE)Rx - frame contains non int multiple of 8 bits  2                          */
++	DescRxCrc             = 0x00000002,   /* (CE)Rx - CRC error                                  1                          */
++	//  DescRxMacMatch        = 0x00000001,   /* (RX MAC Address) Rx mac address reg(1 to 15)match   0                          */
++
++	DescRxEXTsts          = 0x00000001,   /* Extended Status Available (RDES4)                           0                          */
++
++	DescTxIntEnable       = 0x40000000,   /* (IC)Tx - interrupt on completion                    30                       */
++	DescTxLast            = 0x20000000,   /* (LS)Tx - Last segment of the frame                  29                       */
++	DescTxFirst           = 0x10000000,   /* (FS)Tx - First segment of the frame                 28                       */
++	DescTxDisableCrc      = 0x08000000,   /* (DC)Tx - Add CRC disabled (first segment only)      27                       */
++	DescTxDisablePadd   	= 0x04000000,   /* (DP)disable padding, added by - reyaz               26                       */
++	DescTxEnableTimestamp = 0x02000000,   /* (TTSE) Transmit Timestamp Enable               25                       */
++
++	DescTxCisMask     	= 0x00c00000,   /* Tx checksum offloading control mask		       23:22			*/
++	DescTxCisBypass   	= 0x00000000,   /* Checksum bypass								*/
++	DescTxCisIpv4HdrCs	= 0x00400000,	/* IPv4 header checksum								*/
++	DescTxCisTcpOnlyCs    = 0x00800000,	/* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present	*/
++	DescTxCisTcpPseudoCs  = 0x00c00000,	/* TCP/UDP/ICMP checksum fully in hardware including pseudo header		*/
++
++	TxDescEndOfRing       = 0x00200000,   /* (TER)End of descriptors ring                        21                       */
++	TxDescChain           = 0x00100000,   /* (TCH)Second buffer address is chain address         20                       */
++
++	DescRxChkBit0		    = 0x00000001,   /*()  Rx - Rx Payload Checksum Error                   0                          */
++	DescRxChkBit7	    	= 0x00000080,   /* (IPC CS ERROR)Rx - Ipv4 header checksum error       7                          */
++	DescRxChkBit5 		= 0x00000020,   /* (FT)Rx - Frame type - Ethernet, otherwise 802.3     5                          */
++
++	DescRxTSavail         = 0x00000080,   /* Time stamp available                                7                          */
++	DescRxFrameType   	= 0x00000020,   /* (FT)Rx - Frame type - Ethernet, otherwise 802.3     5                          */
++
++	DescTxIpv4ChkError    = 0x00010000,   /* (IHE) Tx Ip header error                            16                         */
++	DescTxTimeout         = 0x00004000,   /* (JT)Tx - Transmit jabber timeout                    14                         */
++	DescTxFrameFlushed    = 0x00002000,   /* (FF)Tx - DMA/MTL flushed the frame due to SW flush  13                         */
++	DescTxPayChkError     = 0x00001000,   /* (PCE) Tx Payload checksum Error                     12                         */
++	DescTxLostCarrier     = 0x00000800,   /* (LC)Tx - carrier lost during tramsmission           11                         */
++	DescTxNoCarrier       = 0x00000400,   /* (NC)Tx - no carrier signal from the tranceiver      10                         */
++	DescTxLateCollision   = 0x00000200,   /* (LC)Tx - transmission aborted due to collision      9                         */
++	DescTxExcCollisions   = 0x00000100,   /* (EC)Tx - transmission aborted after 16 collisions   8                         */
++	DescTxVLANFrame       = 0x00000080,   /* (VF)Tx - VLAN-type frame                            7                         */
++
++	DescTxCollMask        = 0x00000078,   /* (CC)Tx - Collision count                            6:3                        */
++	DescTxCollShift       = 3,
++
++	DescTxExcDeferral     = 0x00000004,   /* (ED)Tx - excessive deferral                         2                        */
++	DescTxUnderflow       = 0x00000002,   /* (UF)Tx - late data arrival from the memory          1                        */
++	DescTxDeferred        = 0x00000001,   /* (DB)Tx - frame transmision deferred                 0                        */
++
++	/*
++	   This explains the RDES1/TDES1 bits layout
++	   --------------------------------------------------------------------
++	   RDES1/TDES1  | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1          |
++	   --------------------------------------------------------------------
++
++*/
++	// DmaDescriptorLength     length word of DMA descriptor
++
++
++	RxDisIntCompl		= 0x80000000,	/* (Disable Rx int on completion) 			31			*/
++	RxDescEndOfRing       = 0x00008000,   /* (TER)End of descriptors ring                         15                       */
++	RxDescChain           = 0x00004000,   /* (TCH)Second buffer address is chain address          14                       */
++
++
++	DescSize2Mask         = 0x1FFF0000,   /* (TBS2) Buffer 2 size                                28:16                    */
++	DescSize2Shift        = 16,
++	DescSize1Mask         = 0x00001FFF,   /* (TBS1) Buffer 1 size                                12:0                     */
++	DescSize1Shift        = 0,
++
++
++	/*
++	   This explains the RDES4 Extended Status bits layout
++	   --------------------------------------------------------------------
++	   RDES4   |                             Extended Status                        |
++	   --------------------------------------------------------------------
++	   */
++
++#ifdef AVB_SUPPORT
++	DescRxVlanPrioVal     = 0x001C0000,    /* Gives the VLAN Priority Value                      20:18                     */
++	DescRxVlanPrioShVal   = 18,            /* Gives the shift value to get priority value in LS bits                       */
++
++	DescRxAvTagPktRx      = 0x00020000,    /* Indicates AV tagged Packet is received              17                       */
++	DescRxAvPktRx         = 0x00010000,    /* Indicates AV Packet received                        16                       */
++
++#endif
++
++	DescRxPtpAvail        = 0x00004000,    /* PTP snapshot available                              14                        */
++	DescRxPtpVer          = 0x00002000,    /* When set indicates IEEE1584 Version 2 (else Ver1)   13                        */
++	DescRxPtpFrameType    = 0x00001000,    /* PTP frame type Indicates PTP sent over ethernet     12                        */
++	DescRxPtpMessageType  = 0x00000F00,    /* Message Type                                        11:8                      */
++	DescRxPtpNo           = 0x00000000,    /* 0000 => No PTP message received                                               */
++	DescRxPtpSync         = 0x00000100,    /* 0001 => Sync (all clock types) received                                       */
++	DescRxPtpFollowUp     = 0x00000200,    /* 0010 => Follow_Up (all clock types) received                                  */
++	DescRxPtpDelayReq     = 0x00000300,    /* 0011 => Delay_Req (all clock types) received                                  */
++	DescRxPtpDelayResp    = 0x00000400,    /* 0100 => Delay_Resp (all clock types) received                                 */
++	DescRxPtpPdelayReq    = 0x00000500,    /* 0101 => Pdelay_Req (in P to P tras clk)  or Announce in Ord and Bound clk     */
++	DescRxPtpPdelayResp   = 0x00000600,    /* 0110 => Pdealy_Resp(in P to P trans clk) or Management in Ord and Bound clk   */
++	DescRxPtpPdelayRespFP = 0x00000700,    /* 0111 => Pdealy_Resp_Follow_Up (in P to P trans clk) or Signaling in Ord and Bound clk   */
++	DescRxPtpIPV6         = 0x00000080,    /* Received Packet is  in IPV6 Packet                  7                         */
++	DescRxPtpIPV4         = 0x00000040,    /* Received Packet is  in IPV4 Packet                  6                         */
++
++	DescRxChkSumBypass    = 0x00000020,    /* When set indicates checksum offload engine          5
++											  is bypassed                                                                   */
++	DescRxIpPayloadError  = 0x00000010,    /* When set indicates 16bit IP payload CS is in error  4                         */
++	DescRxIpHeaderError   = 0x00000008,    /* When set indicates 16bit IPV4 header CS is in       3
++											  error or IP datagram version is not consistent
++											  with Ethernet type value                                                      */
++	DescRxIpPayloadType   = 0x00000007,     /* Indicate the type of payload encapsulated          2:0
++											   in IPdatagram processed by COE (Rx)                                          */
++	DescRxIpPayloadUnknown= 0x00000000,     /* Unknown or didnot process IP payload                                         */
++	DescRxIpPayloadUDP    = 0x00000001,     /* UDP                                                                          */
++	DescRxIpPayloadTCP    = 0x00000002,     /* TCP                                                                          */
++	DescRxIpPayloadICMP   = 0x00000003,     /* ICMP                                                                         */
++
++};
++
++#else
++/*
++
++ ********** Default Descritpor structure  ****************************
++ DmaRxBaseAddr     = 0x000C,   CSR3 - Receive Descriptor list base address
++ DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a
++ 32 bit Data bus is as shown below
++
++ Similarly
++ DmaTxBaseAddr     = 0x0010,  CSR4 - Transmit Descriptor list base address
++ DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a
++ 32 bit Data bus is as shown below
++ --------------------------------------------------------------------
++ RDES0/TDES0  |OWN (31)| Status                                                   |
++ --------------------------------------------------------------------
++ RDES1/TDES1  | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1          |
++ --------------------------------------------------------------------
++ RDES2/TDES2  |  Buffer 1 Address                                                 |
++ --------------------------------------------------------------------
++ RDES3/TDES3  |  Buffer 2 Address / Next Descriptor Address                       |
++ --------------------------------------------------------------------
++ */
++enum DmaDescriptorStatus    /* status word of DMA descriptor */
++{
++	DescOwnByDma          = 0x80000000,   /* (OWN)Descriptor is owned by DMA engine            31      RW                  */
++
++	DescDAFilterFail      = 0x40000000,   /* (AFM)Rx - DA Filter Fail for the rx frame         30                          */
++
++	DescFrameLengthMask   = 0x3FFF0000,   /* (FL)Receive descriptor frame length               29:16                       */
++	DescFrameLengthShift  = 16,
++
++	DescError             = 0x00008000,   /* (ES)Error summary bit  - OR of the follo. bits:   15                          */
++	/*  DE || OE || IPC || LC || RWT || RE || CE */
++	DescRxTruncated       = 0x00004000,   /* (DE)Rx - no more descriptors for receive frame    14                          */
++	DescSAFilterFail      = 0x00002000,   /* (SAF)Rx - SA Filter Fail for the received frame   13                          */
++	DescRxLengthError	= 0x00001000,   /* (LE)Rx - frm size not matching with len field     12                          */
++	DescRxDamaged         = 0x00000800,   /* (OE)Rx - frm was damaged due to buffer overflow   11                          */
++	DescRxVLANTag         = 0x00000400,   /* (VLAN)Rx - received frame is a VLAN frame         10                          */
++	DescRxFirst           = 0x00000200,   /* (FS)Rx - first descriptor of the frame             9                          */
++	DescRxLast            = 0x00000100,   /* (LS)Rx - last descriptor of the frame              8                          */
++	DescRxLongFrame       = 0x00000080,   /* (Giant Frame)Rx - frame is longer than 1518/1522   7                          */
++	DescRxCollision       = 0x00000040,   /* (LC)Rx - late collision occurred during reception  6                          */
++	DescRxFrameEther      = 0x00000020,   /* (FT)Rx - Frame type - Ethernet, otherwise 802.3    5                          */
++	DescRxWatchdog        = 0x00000010,   /* (RWT)Rx - watchdog timer expired during reception  4                          */
++	DescRxMiiError        = 0x00000008,   /* (RE)Rx - error reported by MII interface           3                          */
++	DescRxDribbling       = 0x00000004,   /* (DE)Rx - frame contains non int multiple of 8 bits 2                          */
++	DescRxCrc             = 0x00000002,   /* (CE)Rx - CRC error                                 1                          */
++	DescRxMacMatch        = 0x00000001,   /* (RX MAC Address) Rx mac address reg(1 to 15)match  0                          */
++
++	//Rx Descriptor Checksum Offload engine (type 2) encoding
++	//DescRxPayChkError     = 0x00000001,   /* ()  Rx - Rx Payload Checksum Error                 0                          */
++	//DescRxIpv4ChkError    = 0x00000080,   /* (IPC CS ERROR)Rx - Ipv4 header checksum error      7                          */
++
++	DescRxChkBit0		= 0x00000001,   /*()  Rx - Rx Payload Checksum Error                  0                          */
++	DescRxChkBit7		= 0x00000080,   /* (IPC CS ERROR)Rx - Ipv4 header checksum error      7                          */
++	DescRxChkBit5		= 0x00000020,   /* (FT)Rx - Frame type - Ethernet, otherwise 802.3    5                          */
++
++	DescTxIpv4ChkError    = 0x00010000,   /* (IHE) Tx Ip header error                           16                         */
++	DescTxTimeout         = 0x00004000,   /* (JT)Tx - Transmit jabber timeout                   14                         */
++	DescTxFrameFlushed    = 0x00002000,   /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13                         */
++	DescTxPayChkError     = 0x00001000,   /* (PCE) Tx Payload checksum Error                    12                         */
++	DescTxLostCarrier     = 0x00000800,   /* (LC)Tx - carrier lost during tramsmission          11                         */
++	DescTxNoCarrier       = 0x00000400,   /* (NC)Tx - no carrier signal from the tranceiver     10                         */
++	DescTxLateCollision   = 0x00000200,   /* (LC)Tx - transmission aborted due to collision      9                         */
++	DescTxExcCollisions   = 0x00000100,   /* (EC)Tx - transmission aborted after 16 collisions   8                         */
++	DescTxVLANFrame       = 0x00000080,   /* (VF)Tx - VLAN-type frame                            7                         */
++
++	DescTxCollMask        = 0x00000078,   /* (CC)Tx - Collision count                           6:3                        */
++	DescTxCollShift       = 3,
++
++	DescTxExcDeferral     = 0x00000004,   /* (ED)Tx - excessive deferral                          2                        */
++	DescTxUnderflow       = 0x00000002,   /* (UF)Tx - late data arrival from the memory           1                        */
++	DescTxDeferred        = 0x00000001,   /* (DB)Tx - frame transmision deferred                  0                        */
++
++	/*
++	   This explains the RDES1/TDES1 bits layout
++	   --------------------------------------------------------------------
++	   RDES1/TDES1  | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1          |
++	   --------------------------------------------------------------------
++
++*/
++	//DmaDescriptorLength     length word of DMA descriptor
++
++	DescTxIntEnable       = 0x80000000,   /* (IC)Tx - interrupt on completion                    31                       */
++	DescTxLast            = 0x40000000,   /* (LS)Tx - Last segment of the frame                  30                       */
++	DescTxFirst           = 0x20000000,   /* (FS)Tx - First segment of the frame                 29                       */
++	DescTxDisableCrc      = 0x04000000,   /* (DC)Tx - Add CRC disabled (first segment only)      26                       */
++
++	RxDisIntCompl		= 0x80000000,	/* (Disable Rx int on completion) 			31			*/
++	RxDescEndOfRing       = 0x02000000,   /* (TER)End of descriptors ring                                                 */
++	RxDescChain           = 0x01000000,   /* (TCH)Second buffer address is chain address         24                       */
++
++	DescTxDisablePadd	= 0x00800000,   /* (DP)disable padding, added by - reyaz               23                       */
++
++	TxDescEndOfRing       = 0x02000000,   /* (TER)End of descriptors ring                                                 */
++	TxDescChain           = 0x01000000,   /* (TCH)Second buffer address is chain address         24                       */
++
++	DescSize2Mask         = 0x003FF800,   /* (TBS2) Buffer 2 size                                21:11                    */
++	DescSize2Shift        = 11,
++	DescSize1Mask         = 0x000007FF,   /* (TBS1) Buffer 1 size                                10:0                     */
++	DescSize1Shift        = 0,
++
++
++	DescTxCisMask  	= 0x18000000,   /* Tx checksum offloading control mask			28:27			*/
++	DescTxCisBypass	= 0x00000000,   /* Checksum bypass								*/
++	DescTxCisIpv4HdrCs	= 0x08000000,	/* IPv4 header checksum								*/
++	DescTxCisTcpOnlyCs    = 0x10000000,	/* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present	*/
++	DescTxCisTcpPseudoCs  = 0x18000000,	/* TCP/UDP/ICMP checksum fully in hardware including pseudo header		*/
++};
++#endif
++
++// Rx Descriptor COE type2 encoding
++enum RxDescCOEEncode
++{
++	RxLenLT600			= 0,	/* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600			*/
++	RxIpHdrPayLoadChkBypass	= 1,	/* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload) 		*/
++	RxIpHdrPayLoadRes		= 2,	/* Bit(5:7:0)=>2 Reserved						 		*/
++	RxChkBypass			= 3,	/* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed 		 		*/
++	RxNoChkError			= 4,	/* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected					*/
++	RxPayLoadChkError		= 5,	/* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames			*/
++	RxIpHdrChkError		= 6,	/* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames			*/
++	RxIpHdrPayLoadChkError	= 7,	/* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames	*/
++};
++
++/**********************************************************
++ * DMA engine interrupt handling functions
++ **********************************************************/
++
++enum synopGMACDmaIntEnum  /* Intrerrupt types */
++{
++	synopGMACDmaRxNormal   = 0x01,   /* normal receiver interrupt */
++	synopGMACDmaRxAbnormal = 0x02,   /* abnormal receiver interrupt */
++	synopGMACDmaRxStopped  = 0x04,   /* receiver stopped */
++	synopGMACDmaTxNormal   = 0x08,   /* normal transmitter interrupt */
++	synopGMACDmaTxAbnormal = 0x10,   /* abnormal transmitter interrupt */
++	synopGMACDmaTxStopped  = 0x20,   /* transmitter stopped */
++	synopGMACDmaError      = 0x80,   /* Dma engine error */
++
++#ifdef AVB_SUPPORT
++	synopGMADmaSlotCounter  = 0x40,  /* Dma SlotCounter interrupt mask for Channel1 and Channel2*/
++#endif
++};
++
++
++/**********************************************************
++ * Initial register values
++ **********************************************************/
++enum InitialRegisters
++{
++	/* Full-duplex mode with perfect filter on */
++	GmacConfigInitFdx1000   = GmacWatchdogEnable | GmacJabberEnable         | GmacFrameBurstEnable | GmacJumboFrameDisable
++		| GmacSelectGmii     | GmacEnableRxOwn          | GmacLoopbackOff
++		| GmacFullDuplex     | GmacRetryEnable          | GmacPadCrcStripDisable
++		| GmacBackoffLimit0  | GmacDeferralCheckDisable | GmacTxEnable          | GmacRxEnable,
++
++	/* Full-duplex mode with perfect filter on */
++	GmacConfigInitFdx110    = GmacWatchdogEnable | GmacJabberEnable         | GmacFrameBurstEnable  | GmacJumboFrameDisable
++		| GmacSelectMii      | GmacEnableRxOwn          | GmacLoopbackOff
++		| GmacFullDuplex     | GmacRetryEnable          | GmacPadCrcStripDisable
++		| GmacBackoffLimit0  | GmacDeferralCheckDisable | GmacTxEnable          | GmacRxEnable,
++
++	/* Full-duplex mode */
++	// CHANGED: Pass control config, dest addr filter normal, added source address filter, multicast & unicast
++	// Hash filter.
++	/*                        = GmacFilterOff         | GmacPassControlOff | GmacBroadcastEnable */
++	GmacFrameFilterInitFdx = GmacFilterOn          | GmacPassControl0   | GmacBroadcastEnable |  GmacSrcAddrFilterDisable
++		| GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff
++		| GmacPromiscuousModeOff | GmacUcastHashFilterOff,
++
++	/* Full-duplex mode */
++	GmacFlowControlInitFdx = GmacUnicastPauseFrameOff | GmacRxFlowControlEnable | GmacTxFlowControlEnable,
++
++	/* Full-duplex mode */
++	GmacGmiiAddrInitFdx    = GmiiCsrClk2,
++
++
++	/* Half-duplex mode with perfect filter on */
++	// CHANGED: Removed Endian configuration, added single bit config for PAD/CRC strip,
++	/*| GmacSelectMii      | GmacLittleEndian         | GmacDisableRxOwn      | GmacLoopbackOff*/
++	GmacConfigInitHdx1000  = GmacWatchdogEnable | GmacJabberEnable         | GmacFrameBurstEnable  | GmacJumboFrameDisable
++		| GmacSelectGmii     | GmacDisableRxOwn         | GmacLoopbackOff
++		| GmacHalfDuplex     | GmacRetryEnable          | GmacPadCrcStripDisable
++		| GmacBackoffLimit0  | GmacDeferralCheckDisable | GmacTxEnable          | GmacRxEnable,
++
++	/* Half-duplex mode with perfect filter on */
++	GmacConfigInitHdx110   = GmacWatchdogEnable | GmacJabberEnable         | GmacFrameBurstEnable  | GmacJumboFrameDisable
++		| GmacSelectMii      | GmacDisableRxOwn         | GmacLoopbackOff
++		| GmacHalfDuplex     | GmacRetryEnable          | GmacPadCrcStripDisable
++		| GmacBackoffLimit0  | GmacDeferralCheckDisable | GmacTxEnable          | GmacRxEnable,
++
++	/* Half-duplex mode */
++	GmacFrameFilterInitHdx = GmacFilterOn          | GmacPassControl0        | GmacBroadcastEnable | GmacSrcAddrFilterDisable
++		| GmacMulticastFilterOn | GmacDestAddrFilterNor   | GmacMcastHashFilterOff
++		| GmacUcastHashFilterOff| GmacPromiscuousModeOff,
++
++	/* Half-duplex mode */
++	GmacFlowControlInitHdx = GmacUnicastPauseFrameOff | GmacRxFlowControlDisable | GmacTxFlowControlDisable,
++
++	/* Half-duplex mode */
++	GmacGmiiAddrInitHdx    = GmiiCsrClk2,
++
++
++
++	/**********************************************
++	 *DMA configurations
++	 **********************************************/
++
++	DmaBusModeInit         = DmaFixedBurstEnable |   DmaBurstLength8   | DmaDescriptorSkip2       | DmaResetOff | 0x02000000,
++	//   DmaBusModeInit         = DmaFixedBurstEnable |   DmaBurstLength8   | DmaDescriptorSkip4       | DmaResetOff,
++
++	/* 1000 Mb/s mode */
++	DmaControlInit1000     = DmaStoreAndForward,//       | DmaTxSecondFrame ,
++
++	/* 100 Mb/s mode */
++	DmaControlInit100      = DmaStoreAndForward,
++
++	/* 10 Mb/s mode */
++	DmaControlInit10       = DmaStoreAndForward,
++
++	/* Interrupt groups */
++	DmaIntErrorMask         = DmaIntBusError,           /* Error */
++	DmaIntRxAbnMask         = DmaIntRxNoBuffer,         /* receiver abnormal interrupt */
++	DmaIntRxNormMask        = DmaIntRxCompleted,        /* receiver normal interrupt   */
++	DmaIntRxStoppedMask     = DmaIntRxStopped,          /* receiver stopped */
++	DmaIntTxAbnMask         = DmaIntTxUnderflow,        /* transmitter abnormal interrupt */
++	DmaIntTxNormMask        = DmaIntTxCompleted,        /* transmitter normal interrupt */
++	DmaIntTxStoppedMask     = DmaIntTxStopped,          /* transmitter stopped */
++
++#if 0
++	DmaIntEnable            = DmaIeNormal     | DmaIeAbnormal    | DmaIntErrorMask
++		| DmaIntRxAbnMask | DmaIntRxNormMask | DmaIntRxStoppedMask
++		| DmaIntTxAbnMask | DmaIntTxNormMask | DmaIntTxStoppedMask,
++#else
++	DmaIntEnable            = DmaIeNormal    | DmaIntErrorMask
++		| DmaIntRxNormMask | DmaIntRxStoppedMask
++//		| DmaIntTxNormMask | DmaIntTxStoppedMask,
++		| DmaIntTxStoppedMask,
++#endif
++	DmaIntDisable           = 0,
++};
++
++
++/**********************************************************
++ * Mac Management Counters (MMC)
++ **********************************************************/
++
++enum MMC_ENABLE
++{
++	GmacMmcCntrl			= 0x0100,	/* mmc control for operating mode of MMC						*/
++	GmacMmcIntrRx			= 0x0104,	/* maintains interrupts generated by rx counters					*/
++	GmacMmcIntrTx			= 0x0108,	/* maintains interrupts generated by tx counters					*/
++	GmacMmcIntrMaskRx		= 0x010C,	/* mask for interrupts generated from rx counters					*/
++	GmacMmcIntrMaskTx		= 0x0110,	/* mask for interrupts generated from tx counters					*/
++};
++enum MMC_TX
++{
++	GmacMmcTxOctetCountGb		= 0x0114,	/*Bytes Tx excl. of preamble and retried bytes     (Good or Bad)			*/
++	GmacMmcTxFrameCountGb		= 0x0118,	/*Frames Tx excl. of retried frames	           (Good or Bad)			*/
++	GmacMmcTxBcFramesG		= 0x011C,	/*Broadcast Frames Tx 				   (Good)				*/
++	GmacMmcTxMcFramesG		= 0x0120,	/*Multicast Frames Tx				   (Good)				*/
++
++	GmacMmcTx64OctetsGb		= 0x0124,	/*Tx with len 64 bytes excl. of pre and retried    (Good or Bad)			*/
++	GmacMmcTx65To127OctetsGb	= 0x0128,	/*Tx with len >64 bytes <=127 excl. of pre and retried    (Good or Bad)			*/
++	GmacMmcTx128To255OctetsGb	= 0x012C,	/*Tx with len >128 bytes <=255 excl. of pre and retried   (Good or Bad)			*/
++	GmacMmcTx256To511OctetsGb	= 0x0130,	/*Tx with len >256 bytes <=511 excl. of pre and retried   (Good or Bad)			*/
++	GmacMmcTx512To1023OctetsGb	= 0x0134,	/*Tx with len >512 bytes <=1023 excl. of pre and retried  (Good or Bad)			*/
++	GmacMmcTx1024ToMaxOctetsGb	= 0x0138,	/*Tx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad)		*/
++
++	GmacMmcTxUcFramesGb		= 0x013C,	/*Unicast Frames Tx 					 (Good or Bad)			*/
++	GmacMmcTxMcFramesGb		= 0x0140,	/*Multicast Frames Tx				   (Good and Bad)			*/
++	GmacMmcTxBcFramesGb		= 0x0144,	/*Broadcast Frames Tx 				   (Good and Bad)			*/
++	GmacMmcTxUnderFlowError		= 0x0148,	/*Frames aborted due to Underflow error							*/
++	GmacMmcTxSingleColG		= 0x014C,	/*Successfully Tx Frames after singel collision in Half duplex mode			*/
++	GmacMmcTxMultiColG		= 0x0150,	/*Successfully Tx Frames after more than singel collision in Half duplex mode		*/
++	GmacMmcTxDeferred		= 0x0154,	/*Successfully Tx Frames after a deferral in Half duplex mode				*/
++	GmacMmcTxLateCol		= 0x0158,	/*Frames aborted due to late collision error						*/
++	GmacMmcTxExessCol		= 0x015C,	/*Frames aborted due to excessive (16) collision errors					*/
++	GmacMmcTxCarrierError		= 0x0160,	/*Frames aborted due to carrier sense error (No carrier or Loss of carrier)		*/
++	GmacMmcTxOctetCountG		= 0x0164,	/*Bytes Tx excl. of preamble and retried bytes     (Good) 				*/
++	GmacMmcTxFrameCountG		= 0x0168,	/*Frames Tx 				           (Good)				*/
++	GmacMmcTxExessDef		= 0x016C,	/*Frames aborted due to excessive deferral errors (deferred for more than 2 max-sized frame times)*/
++
++	GmacMmcTxPauseFrames		= 0x0170,	/*Number of good pause frames Tx.							*/
++	GmacMmcTxVlanFramesG		= 0x0174,	/*Number of good Vlan frames Tx excl. retried frames					*/
++};
++enum MMC_RX
++{
++	GmacMmcRxFrameCountGb		= 0x0180,	/*Frames Rx 				           (Good or Bad)			*/
++	GmacMmcRxOctetCountGb		= 0x0184,	/*Bytes Rx excl. of preamble and retried bytes     (Good or Bad)			*/
++	GmacMmcRxOctetCountG		= 0x0188,	/*Bytes Rx excl. of preamble and retried bytes     (Good) 				*/
++	GmacMmcRxBcFramesG		= 0x018C,	/*Broadcast Frames Rx 				   (Good)				*/
++	GmacMmcRxMcFramesG		= 0x0190,	/*Multicast Frames Rx				   (Good)				*/
++
++	GmacMmcRxCrcError		= 0x0194,	/*Number of frames received with CRC error						*/
++	GmacMmcRxAlignError		= 0x0198,	/*Number of frames received with alignment (dribble) error. Only in 10/100mode		*/
++	GmacMmcRxRuntError		= 0x019C,	/*Number of frames received with runt (<64 bytes and CRC error) error			*/
++	GmacMmcRxJabberError		= 0x01A0,	/*Number of frames rx with jabber (>1518/1522 or >9018/9022 and CRC) 			*/
++	GmacMmcRxUnderSizeG		= 0x01A4,	/*Number of frames received with <64 bytes without any error				*/
++	GmacMmcRxOverSizeG		= 0x01A8,	/*Number of frames received with >1518/1522 bytes without any error			*/
++
++	GmacMmcRx64OctetsGb		= 0x01AC,	/*Rx with len 64 bytes excl. of pre and retried    (Good or Bad)			*/
++	GmacMmcRx65To127OctetsGb	= 0x01B0,	/*Rx with len >64 bytes <=127 excl. of pre and retried    (Good or Bad)			*/
++	GmacMmcRx128To255OctetsGb	= 0x01B4,	/*Rx with len >128 bytes <=255 excl. of pre and retried   (Good or Bad)			*/
++	GmacMmcRx256To511OctetsGb	= 0x01B8,	/*Rx with len >256 bytes <=511 excl. of pre and retried   (Good or Bad)			*/
++	GmacMmcRx512To1023OctetsGb	= 0x01BC,	/*Rx with len >512 bytes <=1023 excl. of pre and retried  (Good or Bad)			*/
++	GmacMmcRx1024ToMaxOctetsGb	= 0x01C0,	/*Rx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad)		*/
++
++	GmacMmcRxUcFramesG		= 0x01C4,	/*Unicast Frames Rx 					 (Good)				*/
++	GmacMmcRxLengthError		= 0x01C8,	/*Number of frames received with Length type field != frame size			*/
++	GmacMmcRxOutOfRangeType		= 0x01CC,	/*Number of frames received with length field != valid frame size			*/
++
++	GmacMmcRxPauseFrames		= 0x01D0,	/*Number of good pause frames Rx.							*/
++	GmacMmcRxFifoOverFlow		= 0x01D4,	/*Number of missed rx frames due to FIFO overflow					*/
++	GmacMmcRxVlanFramesGb		= 0x01D8,	/*Number of good Vlan frames Rx 							*/
++
++	GmacMmcRxWatchdobError		= 0x01DC,	/*Number of frames rx with error due to watchdog timeout error				*/
++};
++enum MMC_IP_RELATED
++{
++	GmacMmcRxIpcIntrMask		= 0x0200,	/*Maintains the mask for interrupt generated from rx IPC statistic counters 		*/
++	GmacMmcRxIpcIntr		= 0x0208,	/*Maintains the interrupt that rx IPC statistic counters generate			*/
++
++	GmacMmcRxIpV4FramesG		= 0x0210,	/*Good IPV4 datagrams received								*/
++	GmacMmcRxIpV4HdrErrFrames	= 0x0214,	/*Number of IPV4 datagrams received with header errors					*/
++	GmacMmcRxIpV4NoPayFrames	= 0x0218,	/*Number of IPV4 datagrams received which didnot have TCP/UDP/ICMP payload		*/
++	GmacMmcRxIpV4FragFrames		= 0x021C,	/*Number of IPV4 datagrams received with fragmentation					*/
++	GmacMmcRxIpV4UdpChkDsblFrames	= 0x0220,	/*Number of IPV4 datagrams received that had a UDP payload checksum disabled		*/
++
++	GmacMmcRxIpV6FramesG		= 0x0224,	/*Good IPV6 datagrams received								*/
++	GmacMmcRxIpV6HdrErrFrames	= 0x0228,	/*Number of IPV6 datagrams received with header errors					*/
++	GmacMmcRxIpV6NoPayFrames	= 0x022C,	/*Number of IPV6 datagrams received which didnot have TCP/UDP/ICMP payload		*/
++
++	GmacMmcRxUdpFramesG		= 0x0230,	/*Number of good IP datagrams with good UDP payload					*/
++	GmacMmcRxUdpErrorFrames		= 0x0234,	/*Number of good IP datagrams with UDP payload having checksum error			*/
++
++	GmacMmcRxTcpFramesG		= 0x0238,	/*Number of good IP datagrams with good TDP payload					*/
++	GmacMmcRxTcpErrorFrames		= 0x023C,	/*Number of good IP datagrams with TCP payload having checksum error			*/
++
++	GmacMmcRxIcmpFramesG		= 0x0240,	/*Number of good IP datagrams with good Icmp payload					*/
++	GmacMmcRxIcmpErrorFrames	= 0x0244,	/*Number of good IP datagrams with Icmp payload having checksum error			*/
++
++	GmacMmcRxIpV4OctetsG		= 0x0250,	/*Good IPV4 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes			*/
++	GmacMmcRxIpV4HdrErrorOctets	= 0x0254,	/*Number of bytes in IPV4 datagram with header errors					*/
++	GmacMmcRxIpV4NoPayOctets	= 0x0258,	/*Number of bytes in IPV4 datagram with no TCP/UDP/ICMP payload				*/
++	GmacMmcRxIpV4FragOctets		= 0x025C,	/*Number of bytes received in fragmented IPV4 datagrams 				*/
++	GmacMmcRxIpV4UdpChkDsblOctets	= 0x0260,	/*Number of bytes received in UDP segment that had UDP checksum disabled		*/
++
++	GmacMmcRxIpV6OctetsG		= 0x0264,	/*Good IPV6 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes			*/
++	GmacMmcRxIpV6HdrErrorOctets	= 0x0268,	/*Number of bytes in IPV6 datagram with header errors					*/
++	GmacMmcRxIpV6NoPayOctets	= 0x026C,	/*Number of bytes in IPV6 datagram with no TCP/UDP/ICMP payload				*/
++
++	GmacMmcRxUdpOctetsG		= 0x0270,	/*Number of bytes in IP datagrams with good UDP payload					*/
++	GmacMmcRxUdpErrorOctets		= 0x0274,	/*Number of bytes in IP datagrams with UDP payload having checksum error		*/
++
++	GmacMmcRxTcpOctetsG		= 0x0278,	/*Number of bytes in IP datagrams with good TDP payload					*/
++	GmacMmcRxTcpErrorOctets		= 0x027C,	/*Number of bytes in IP datagrams with TCP payload having checksum error		*/
++
++	GmacMmcRxIcmpOctetsG		= 0x0280,	/*Number of bytes in IP datagrams with good Icmp payload				*/
++	GmacMmcRxIcmpErrorOctets	= 0x0284,	/*Number of bytes in IP datagrams with Icmp payload having checksum error		*/
++};
++
++
++enum MMC_CNTRL_REG_BIT_DESCRIPTIONS
++{
++	GmacMmcCounterFreeze		= 0x00000008,		/* when set MMC counters freeze to current value				*/
++	GmacMmcCounterResetOnRead	= 0x00000004,		/* when set MMC counters will be reset to 0 after read				*/
++	GmacMmcCounterStopRollover	= 0x00000002,		/* when set counters will not rollover after max value				*/
++	GmacMmcCounterReset		= 0x00000001,		/* when set all counters wil be reset (automatically cleared after 1 clk)	*/
++
++};
++
++enum MMC_RX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS
++{
++	GmacMmcRxWDInt			= 0x00800000,		/* set when rxwatchdog error reaches half of max value				*/
++	GmacMmcRxVlanInt		= 0x00400000,		/* set when GmacMmcRxVlanFramesGb counter reaches half of max value		*/
++	GmacMmcRxFifoOverFlowInt	= 0x00200000,		/* set when GmacMmcRxFifoOverFlow counter reaches half of max value		*/
++	GmacMmcRxPauseFrameInt		= 0x00100000,		/* set when GmacMmcRxPauseFrames counter reaches half of max value		*/
++	GmacMmcRxOutOfRangeInt		= 0x00080000,		/* set when GmacMmcRxOutOfRangeType counter reaches half of max value		*/
++	GmacMmcRxLengthErrorInt		= 0x00040000,		/* set when GmacMmcRxLengthError counter reaches half of max value		*/
++	GmacMmcRxUcFramesInt		= 0x00020000,		/* set when GmacMmcRxUcFramesG counter reaches half of max value		*/
++	GmacMmcRx1024OctInt		= 0x00010000,		/* set when GmacMmcRx1024ToMaxOctetsGb counter reaches half of max value	*/
++	GmacMmcRx512OctInt		= 0x00008000,		/* set when GmacMmcRx512To1023OctetsGb counter reaches half of max value	*/
++	GmacMmcRx256OctInt		= 0x00004000,		/* set when GmacMmcRx256To511OctetsGb counter reaches half of max value		*/
++	GmacMmcRx128OctInt		= 0x00002000,		/* set when GmacMmcRx128To255OctetsGb counter reaches half of max value		*/
++	GmacMmcRx65OctInt		= 0x00001000,		/* set when GmacMmcRx65To127OctetsG counter reaches half of max value		*/
++	GmacMmcRx64OctInt		= 0x00000800,		/* set when GmacMmcRx64OctetsGb counter reaches half of max value		*/
++	GmacMmcRxOverSizeInt		= 0x00000400,		/* set when GmacMmcRxOverSizeG counter reaches half of max value		*/
++	GmacMmcRxUnderSizeInt		= 0x00000200,		/* set when GmacMmcRxUnderSizeG counter reaches half of max value		*/
++	GmacMmcRxJabberErrorInt		= 0x00000100,		/* set when GmacMmcRxJabberError counter reaches half of max value		*/
++	GmacMmcRxRuntErrorInt		= 0x00000080,		/* set when GmacMmcRxRuntError counter reaches half of max value		*/
++	GmacMmcRxAlignErrorInt		= 0x00000040,		/* set when GmacMmcRxAlignError counter reaches half of max value		*/
++	GmacMmcRxCrcErrorInt		= 0x00000020,		/* set when GmacMmcRxCrcError counter reaches half of max value			*/
++	GmacMmcRxMcFramesInt		= 0x00000010,		/* set when GmacMmcRxMcFramesG counter reaches half of max value		*/
++	GmacMmcRxBcFramesInt		= 0x00000008,		/* set when GmacMmcRxBcFramesG counter reaches half of max value		*/
++	GmacMmcRxOctetGInt		= 0x00000004,		/* set when GmacMmcRxOctetCountG counter reaches half of max value		*/
++	GmacMmcRxOctetGbInt		= 0x00000002,		/* set when GmacMmcRxOctetCountGb counter reaches half of max value		*/
++	GmacMmcRxFrameInt		= 0x00000001,		/* set when GmacMmcRxFrameCountGb counter reaches half of max value		*/
++};
++
++enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS
++{
++
++	GmacMmcTxVlanInt		= 0x01000000,		/* set when GmacMmcTxVlanFramesG counter reaches half of max value		*/
++	GmacMmcTxPauseFrameInt		= 0x00800000,		/* set when GmacMmcTxPauseFrames counter reaches half of max value		*/
++	GmacMmcTxExessDefInt		= 0x00400000,		/* set when GmacMmcTxExessDef counter reaches half of max value			*/
++	GmacMmcTxFrameInt		= 0x00200000,		/* set when GmacMmcTxFrameCount counter reaches half of max value		*/
++	GmacMmcTxOctetInt		= 0x00100000,		/* set when GmacMmcTxOctetCountG counter reaches half of max value		*/
++	GmacMmcTxCarrierErrorInt	= 0x00080000,		/* set when GmacMmcTxCarrierError counter reaches half of max value		*/
++	GmacMmcTxExessColInt		= 0x00040000,		/* set when GmacMmcTxExessCol counter reaches half of max value			*/
++	GmacMmcTxLateColInt		= 0x00020000,		/* set when GmacMmcTxLateCol counter reaches half of max value			*/
++	GmacMmcTxDeferredInt		= 0x00010000,		/* set when GmacMmcTxDeferred counter reaches half of max value			*/
++	GmacMmcTxMultiColInt		= 0x00008000,		/* set when GmacMmcTxMultiColG counter reaches half of max value		*/
++	GmacMmcTxSingleCol		= 0x00004000,		/* set when GmacMmcTxSingleColG	counter reaches half of max value		*/
++	GmacMmcTxUnderFlowErrorInt	= 0x00002000,		/* set when GmacMmcTxUnderFlowError counter reaches half of max value		*/
++	GmacMmcTxBcFramesGbInt 		= 0x00001000,		/* set when GmacMmcTxBcFramesGb	counter reaches half of max value		*/
++	GmacMmcTxMcFramesGbInt 		= 0x00000800,		/* set when GmacMmcTxMcFramesGb	counter reaches half of max value		*/
++	GmacMmcTxUcFramesInt 		= 0x00000400,		/* set when GmacMmcTxUcFramesGb counter reaches half of max value		*/
++	GmacMmcTx1024OctInt 		= 0x00000200,		/* set when GmacMmcTx1024ToMaxOctetsGb counter reaches half of max value	*/
++	GmacMmcTx512OctInt 		= 0x00000100,		/* set when GmacMmcTx512To1023OctetsGb counter reaches half of max value	*/
++	GmacMmcTx256OctInt 		= 0x00000080,		/* set when GmacMmcTx256To511OctetsGb counter reaches half of max value		*/
++	GmacMmcTx128OctInt 		= 0x00000040,		/* set when GmacMmcTx128To255OctetsGb counter reaches half of max value		*/
++	GmacMmcTx65OctInt 		= 0x00000020,		/* set when GmacMmcTx65To127OctetsGb counter reaches half of max value		*/
++	GmacMmcTx64OctInt 		= 0x00000010,		/* set when GmacMmcTx64OctetsGb	counter reaches half of max value		*/
++	GmacMmcTxMcFramesInt 		= 0x00000008,		/* set when GmacMmcTxMcFramesG counter reaches half of max value		*/
++	GmacMmcTxBcFramesInt 		= 0x00000004,		/* set when GmacMmcTxBcFramesG counter reaches half of max value		*/
++	GmacMmcTxFrameGbInt 		= 0x00000002,		/* set when GmacMmcTxFrameCountGb counter reaches half of max value		*/
++	GmacMmcTxOctetGbInt 		= 0x00000001,		/* set when GmacMmcTxOctetCountGb counter reaches half of max value		*/
++
++};
++
++
++/**********************************************************
++ * Power Management (PMT) Block
++ **********************************************************/
++
++/**
++ * PMT supports the reception of network (remote) wake-up frames and Magic packet frames.
++ * It generates interrupts for wake-up frames and Magic packets received by GMAC.
++ * PMT sits in Rx path and is enabled with remote wake-up frame enable and Magic packet enable.
++ * These enable are in PMT control and Status register and are programmed by apllication.
++ *
++ * When power down mode is enabled in PMT, all rx frames are dropped by the core. Core comes
++ * out of power down mode only when either Magic packe tor a Remote wake-up frame is received
++ * and the corresponding detection is enabled.
++ *
++ * Driver need not be modified to support this feature. Only Api to put the device in to power
++ * down mode is sufficient
++ */
++
++#define WAKEUP_REG_LENGTH	8 				/*This is the reg length for wake up register configuration*/
++
++enum GmacPmtCtrlStatusBitDefinition
++{
++	GmacPmtFrmFilterPtrReset	= 0x80000000,		/* when set remote wake-up frame filter register pointer to 3'b000 */
++	GmacPmtGlobalUnicast		= 0x00000200,		/* When set enables any unicast packet to be a wake-up frame       */
++	GmacPmtWakeupFrameReceived	= 0x00000040,		/* Wake up frame received					   */
++	GmacPmtMagicPktReceived		= 0x00000020,		/* Magic Packet received					   */
++	GmacPmtWakeupFrameEnable	= 0x00000004,		/* Wake-up frame enable						   */
++	GmacPmtMagicPktEnable		= 0x00000002,		/* Magic packet enable						   */
++	GmacPmtPowerDown		= 0x00000001,		/* Power Down							   */
++};
++
++
++
++
++/**********************************************************
++ * IEEE 1588-2008 Precision Time Protocol (PTP) Support
++ **********************************************************/
++enum PTPMessageType
++{
++	SYNC        	   = 0x0,
++	Delay_Req    	   = 0x1,
++	Pdelay_Req             = 0x2,
++	Pdelay_Resp            = 0x3,
++	Follow_up              = 0x8,
++	Delay_Resp             = 0x9,
++	Pdelay_Resp_Follow_Up  = 0xA,
++	Announce               = 0xB,
++	Signaling              = 0xC,
++	Management             = 0xD,
++};
++
++
++
++typedef struct TimeStampStruct
++{
++	u32   TSversion;      /* PTP Version 1 or PTP version2                                                                          */
++	u32   TSmessagetype;  /* Message type associated with this time stamp                                                           */
++
++	u16   TShighest16;    /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit		  */
++	u32   TSupper32;      /* Most significant 32 bit time stamp value								  */
++	u32   TSlower32;      /* Least Significat 32 bit time stamp value								  */
++
++} TimeStamp;
++
++
++/**
++ * IEEE 1588-2008 is the optional module to support Ethernet frame time stamping.
++ * Sixty four (+16) bit time stamps are given in each frames transmit and receive status.
++ * The driver assumes the following
++ *  1. "IEEE 1588 Time Stamping" "TIME_STAMPING"is ENABLED in corekit
++ *  2. "IEEE 1588 External Time Stamp Input Enable" "EXT_TIME_STAMPING" is DISABLED in corekit
++ *  3. "IEEE 1588 Advanced Time Stamp support" "ADV_TIME_STAMPING" is ENABLED in corekit
++ *  4. "IEEE 1588 Higher Word Register Enable" "ADV_TIME_HIGH_WORD" is ENABLED in corekit
++ */
++
++/* GmacTSControl  = 0x0700,   Controls the Timestamp update logic  : only when IEEE 1588 time stamping is enabled in corekit         */
++enum GmacTSControlReg
++{
++	GmacTSENMACADDR	  = 0x00040000,     /* Enable Mac Addr for PTP filtering     18            RW         0     */
++
++	GmacTSCLKTYPE		  = 0x00030000,     /* Select the type of clock node         17:16         RW         00    */
++	/*
++	   TSCLKTYPE        TSMSTRENA      TSEVNTENA         Messages for wihich TS snapshot is taken
++	   00/01                X             0              SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP
++	   00/01                1             0              DELAY_REQ
++	   00/01                0             1              SYNC
++	   10                  NA            0              SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP
++	   10                  NA            1              SYNC, FOLLOW_UP
++	   11                  NA            0              SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP, PDELAY_REQ, PDELAY_RESP
++	   11                  NA            1              SYNC, PDELAY_REQ, PDELAY_RESP
++	   */
++	GmacTSOrdClk		  = 0x00000000,	    /* 00=> Ordinary clock*/
++	GmacTSBouClk		  = 0x00010000,	    /* 01=> Boundary clock*/
++	GmacTSEtoEClk		  = 0x00020000,	    /* 10=> End-to-End transparent clock*/
++	GmacTSPtoPClk		  = 0x00030000,	    /* 11=> P-to-P transparent clock*/
++
++	GmacTSMSTRENA		  = 0x00008000,	    /* Ena TS Snapshot for Master Messages   15            RW         0     */
++	GmacTSEVNTENA		  = 0x00004000,	    /* Ena TS Snapshot for Event Messages    14            RW         0     */
++	GmacTSIPV4ENA		  = 0x00002000,	    /* Ena TS snapshot for IPv4              13            RW         1     */
++	GmacTSIPV6ENA		  = 0x00001000,	    /* Ena TS snapshot for IPv6              12            RW         0     */
++	GmacTSIPENA		  = 0x00000800,	    /* Ena TS snapshot for PTP over E'net    11            RW         0     */
++	GmacTSVER2ENA		  = 0x00000400,	    /* Ena PTP snooping for version 2        10            RW         0     */
++
++	GmacTSCTRLSSR           = 0x00000200,      /* Digital or Binary Rollover           9             RW         0     */
++
++	GmacTSENALL             = 0x00000100,      /* Enable TS fro all frames (Ver2 only) 8             RW         0     */
++
++	GmacTSADDREG		  = 0x00000020,	     /* Addend Register Update		     5             RW_SC      0     */
++	GmacTSUPDT		  = 0x00000008,	     /* Time Stamp Update		     3             RW_SC      0     */
++	GmacTSINT		  = 0x00000004,	     /* Time Atamp Initialize		     2             RW_SC      0     */
++
++	GmacTSTRIG		  = 0x00000010,	     /* Time stamp interrupt Trigger Enable  4             RW_SC      0     */
++
++	GmacTSCFUPDT		  = 0x00000002,	     /* Time Stamp Fine/Coarse		     1             RW         0     */
++	GmacTSCUPDTCoarse	  = 0x00000000,	     /* 0=> Time Stamp update method is coarse			            */
++	GmacTSCUPDTFine	  = 0x00000002,	     /* 1=> Time Stamp update method is fine				    */
++
++	GmacTSENA		  = 0x00000001,      /* Time Stamp Enable                    0             RW         0     */
++};
++
++
++/*  GmacTSSubSecIncr     	  = 0x0704,   8 bit value by which sub second register is incremented     : only when IEEE 1588 time stamping without external timestamp input */
++enum GmacTSSubSecIncrReg
++{
++	GmacSSINCMsk            = 0x000000FF,       /* Only Lower 8 bits are valid bits     7:0           RW         00    */
++};
++
++/*  GmacTSLow   	  = 0x070C,   Indicates whether the timestamp low count is positive or negative; for Adv timestamp it is always zero */
++enum GmacTSSign
++{
++	GmacTSSign              = 0x80000000,      /* PSNT                                  31            RW          0    */
++	GmacTSPositive          = 0x00000000,
++	GmacTSNegative          = 0x80000000,
++};
++
++/*GmacTargetTimeLow   	  = 0x0718,   32 bit nano seconds(MS) to be compared with system time     : only when IEEE 1588 time stamping without external timestamp input */
++enum GmacTSLowReg
++{
++	GmacTSDecThr            = 0x3B9AC9FF,      /*when TSCTRLSSR is set the max value for GmacTargetTimeLowReg and GmacTimeStampLow register is 0x3B9AC9FF at 1ns precision       */
++};
++
++/* GmacTSHighWord          = 0x0724,   Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid                                                   */
++enum GmacTSHighWordReg
++{
++	GmacTSHighWordMask      = 0x0000FFFF,     /* Time Stamp Higher work register has only lower 16 bits valid			*/
++};
++/*GmacTSStatus            = 0x0728,   Time Stamp Status Register                                                                                                       */
++enum GmacTSStatusReg
++{
++	GmacTSTargTimeReached   = 0x00000002,     /* Time Stamp Target Time Reached          1             RO          0    */
++	GmacTSSecondsOverflow   = 0x00000001,     /* Time Stamp Seconds Overflow             0             RO          0    */
++};
++
++/* GmacAvMacCtrl            = 0x0738,   AV mac control Register  */
++#ifdef AVB_SUPPORT
++enum GmacAvMacCtrlReg
++{
++	GmacAvCtrlCh            = 0x03000000,      /* Channel on which AV control packets to be received                   25:24  RW   0    */
++	GmacPtpCh               = 0x00180000,      /* Channel on which PTP packets to be received                          20:19  RW   0    */
++	GmacAvPrio              = 0x00070000,      /* Priority tag value for AV Packets                                    18:16  RW   4    */
++	GmacAvTypeMask          = 0x0000FFFF,      /* Ethernet Type value to be used for comparing and detecting AV packet 15:0   RW   0    */
++};
++#endif
++
++/**********************************************************
++ * Time stamp related functions
++ **********************************************************/
++void synopGMAC_TS_enable(synopGMACdevice *gmacdev);
++void synopGMAC_TS_disable(synopGMACdevice *gmacdev);
++
++void synopGMAC_TS_int_enable(synopGMACdevice *gmacdev);
++void synopGMAC_TS_int_disable(synopGMACdevice *gmacdev);
++
++void synopGMAC_TS_mac_addr_filt_enable(synopGMACdevice *gmacdev);
++void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev);
++void synopGMAC_TS_set_clk_type(synopGMACdevice *gmacdev, u32 clk_type);
++void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev);			// Only for Ordinary clock and Boundary clock and "Advanced Time Stamp"
++void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev);			// Only for Ordinary clock and Boundary clock and "Advanced Time Stamp"
++void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev);			// Only for "Advanced Time Stamp"
++void synopGMAC_TS_event_disable(synopGMACdevice *gmacdev);                   // Only for "Advanced Time Stamp"
++void synopGMAC_TS_IPV4_enable(synopGMACdevice *gmacdev);                     // Only for "Advanced Time Stamp"
++void synopGMAC_TS_IPV4_disable(synopGMACdevice *gmacdev);                    // Only for "Advanced Time Stamp"
++void synopGMAC_TS_IPV6_enable(synopGMACdevice *gmacdev);                     // Only for "Advanced Time Stamp"
++void synopGMAC_TS_IPV6_disable(synopGMACdevice *gmacdev);                    // Only for "Advanced Time Stamp"
++void synopGMAC_TS_ptp_over_ethernet_enable(synopGMACdevice *gmacdev);        // Only for "Advanced Time Stamp"
++void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev);       // Only for "Advanced Time Stamp"
++void synopGMAC_TS_pkt_snoop_ver2(synopGMACdevice *gmacdev);                  // Only for "Advanced Time Stamp"
++void synopGMAC_TS_pkt_snoop_ver1(synopGMACdevice *gmacdev);                  // Only for "Advanced Time Stamp"
++
++void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev);
++void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev);
++void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev);               // Only for "Advanced Time Stamp"
++void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev);              // Only for "Advanced Time Stamp"
++
++s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value);
++s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 low_value);
++s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 low_value);
++
++void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev);			// Only if "fine correction" enabled
++void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev);			// Only if "fine correction" enabled
++
++void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_val); // Update should happen making use of subsecond mask
++void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val,
++		u32 * sec_val, u32 *  sub_sec_val);                   // Reads the timestamp low,high and higher(Ver2) registers in the the struct pointer; readonly contents
++void synopGMAC_TS_load_target_timestamp(synopGMACdevice *gmacdev, u32 sec_val, u32 sub_sec_val); //Loads the timestamp target register with the values provided
++
++void synopGMAC_TS_load_timestamp_higher_val(synopGMACdevice *gmacdev, u32 higher_sec_val);
++void synopGMAC_TS_read_timestamp_higher_val(synopGMACdevice *gmacdev, u16 * higher_sec_val);
++void synopGMAC_TS_read_target_timestamp(synopGMACdevice *gmacdev, u32 * sec_val, u32 * sub_sec_val); //Read the target time stamp register contents
++
++
++/**********************************************************
++ * Common functions
++ **********************************************************/
++s32 synopGMAC_set_mdc_clk_div(synopGMACdevice *gmacdev,u32 clk_div_val);
++u32 synopGMAC_get_mdc_clk_div(synopGMACdevice *gmacdev);
++u32 synopGMAC_calculate_mdc_clk_csr(u32 sysclk, u32 max_mdcclk);
++s32 synopGMAC_read_phy_reg(synopGMACdevice *gmacdev, u32 PhyBase, u32 RegOffset, u16 * data);
++s32 synopGMAC_write_phy_reg(synopGMACdevice *gmacdev, u32 PhyBase, u32 RegOffset, u16 data);
++s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev, bool loopback);
++s32 synopGMAC_read_version (synopGMACdevice * gmacdev) ;
++s32 synopGMAC_reset (synopGMACdevice * gmacdev );
++s32 synopGMAC_dma_bus_mode_init(synopGMACdevice * gmacdev, u32 init_value );
++s32 synopGMAC_dma_control_init(synopGMACdevice * gmacdev, u32 init_value);
++void synopGMAC_wd_enable(synopGMACdevice * gmacdev);
++void synopGMAC_wd_disable(synopGMACdevice * gmacdev);
++void synopGMAC_jab_enable(synopGMACdevice * gmacdev);
++void synopGMAC_jab_disable(synopGMACdevice * gmacdev);
++void synopGMAC_frame_burst_enable(synopGMACdevice * gmacdev);
++void synopGMAC_frame_burst_disable(synopGMACdevice * gmacdev);
++void synopGMAC_jumbo_frame_enable(synopGMACdevice * gmacdev);
++void synopGMAC_jumbo_frame_disable(synopGMACdevice * gmacdev);
++void synopGMAC_set_Inter_Frame_Gap(synopGMACdevice * gmacdev, u32 value);
++void synopGMAC_select_gmii(synopGMACdevice * gmacdev);
++void synopGMAC_select_mii(synopGMACdevice * gmacdev);
++void synopGMAC_select_speed1000(synopGMACdevice * gmacdev);
++void synopGMAC_select_speed100(synopGMACdevice * gmacdev);
++void synopGMAC_select_speed10(synopGMACdevice * gmacdev);
++void synopGMAC_rx_own_enable(synopGMACdevice * gmacdev);
++void synopGMAC_rx_own_disable(synopGMACdevice * gmacdev);
++void synopGMAC_loopback_on(synopGMACdevice * gmacdev);
++void synopGMAC_loopback_off(synopGMACdevice * gmacdev);
++void synopGMAC_set_full_duplex(synopGMACdevice * gmacdev);
++void synopGMAC_set_half_duplex(synopGMACdevice * gmacdev);
++void synopGMAC_retry_enable(synopGMACdevice * gmacdev);
++void synopGMAC_retry_disable(synopGMACdevice * gmacdev);
++void synopGMAC_pad_crc_strip_enable(synopGMACdevice * gmacdev);
++void synopGMAC_pad_crc_strip_disable(synopGMACdevice * gmacdev);
++void synopGMAC_back_off_limit(synopGMACdevice * gmacdev, u32 value);
++void synopGMAC_deferral_check_enable(synopGMACdevice * gmacdev);
++void synopGMAC_deferral_check_disable(synopGMACdevice * gmacdev);
++void synopGMAC_rx_enable(synopGMACdevice * gmacdev);
++void synopGMAC_rx_disable(synopGMACdevice * gmacdev);
++void synopGMAC_tx_enable(synopGMACdevice * gmacdev);
++void synopGMAC_tx_disable(synopGMACdevice * gmacdev);
++void synopGMAC_frame_filter_enable(synopGMACdevice * gmacdev);
++void synopGMAC_frame_filter_disable(synopGMACdevice * gmacdev);
++void synopGMAC_write_hash_table_high(synopGMACdevice * gmacdev, u32 data);
++void synopGMAC_write_hash_table_low(synopGMACdevice * gmacdev, u32 data);
++void synopGMAC_hash_perfect_filter_enable(synopGMACdevice * gmacdev);
++void synopGMAC_Hash_filter_only_enable(synopGMACdevice * gmacdev);
++void synopGMAC_src_addr_filter_enable(synopGMACdevice * gmacdev);
++void synopGMAC_src_addr_filter_disable(synopGMACdevice * gmacdev);
++void synopGMAC_dst_addr_filter_inverse(synopGMACdevice * gmacdev);
++void synopGMAC_dst_addr_filter_normal(synopGMACdevice * gmacdev);
++void synopGMAC_set_pass_control(synopGMACdevice * gmacdev,u32 passcontrol);
++void synopGMAC_broadcast_enable(synopGMACdevice * gmacdev);
++void synopGMAC_broadcast_disable(synopGMACdevice * gmacdev);
++void synopGMAC_multicast_enable(synopGMACdevice * gmacdev);
++void synopGMAC_multicast_disable(synopGMACdevice * gmacdev);
++void synopGMAC_multicast_hash_filter_enable(synopGMACdevice * gmacdev);
++void synopGMAC_multicast_hash_filter_disable(synopGMACdevice * gmacdev);
++void synopGMAC_promisc_enable(synopGMACdevice * gmacdev);
++void synopGMAC_promisc_disable(synopGMACdevice * gmacdev);
++void synopGMAC_unicast_hash_filter_enable(synopGMACdevice * gmacdev);
++void synopGMAC_unicast_hash_filter_disable(synopGMACdevice * gmacdev);
++void synopGMAC_unicast_pause_frame_detect_enable(synopGMACdevice * gmacdev);
++void synopGMAC_unicast_pause_frame_detect_disable(synopGMACdevice * gmacdev);
++void synopGMAC_rx_flow_control_enable(synopGMACdevice * gmacdev);
++void synopGMAC_rx_flow_control_disable(synopGMACdevice * gmacdev);
++void synopGMAC_tx_flow_control_enable(synopGMACdevice * gmacdev);
++void synopGMAC_tx_flow_control_disable(synopGMACdevice * gmacdev);
++void synopGMAC_tx_activate_flow_control(synopGMACdevice * gmacdev);
++void synopGMAC_tx_deactivate_flow_control(synopGMACdevice * gmacdev);
++void synopGMAC_pause_control(synopGMACdevice *gmacdev);
++s32 synopGMAC_mac_init(synopGMACdevice * gmacdev);
++s32 synopGMAC_search_phy (synopGMACdevice * gmacdev);
++s32 synopGMAC_check_phy_init (synopGMACdevice * gmacdev);
++s32 synopGMAC_set_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr);
++s32 synopGMAC_get_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr);
++s32 synopGMAC_attach (synopGMACdevice * gmacdev, u32 macBase, u32 dmaBase, u32 phyBase);
++void synopGMAC_rx_desc_init_ring(DmaDesc *desc, bool last_ring_desc);
++void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc);
++void synopGMAC_rx_desc_init_chain(DmaDesc * desc);
++void synopGMAC_tx_desc_init_chain(DmaDesc * desc);
++s32 synopGMAC_init_tx_rx_desc_queue(synopGMACdevice *gmacdev);
++void synopGMAC_init_rx_desc_base(synopGMACdevice *gmacdev);
++void synopGMAC_init_tx_desc_base(synopGMACdevice *gmacdev);
++void synopGMAC_set_owner_dma(DmaDesc *desc);
++void synopGMAC_set_desc_sof(DmaDesc *desc);
++void synopGMAC_set_desc_eof(DmaDesc *desc);
++bool synopGMAC_is_sof_in_rx_desc(DmaDesc *desc);
++bool synopGMAC_is_eof_in_rx_desc(DmaDesc *desc);
++bool synopGMAC_is_da_filter_failed(DmaDesc *desc);
++bool synopGMAC_is_sa_filter_failed(DmaDesc *desc);
++bool synopGMAC_is_desc_owned_by_dma(DmaDesc *desc);
++u32 synopGMAC_get_rx_desc_frame_length(u32 status);
++bool synopGMAC_is_desc_valid(u32 status);
++bool synopGMAC_is_desc_empty(DmaDesc *desc);
++bool synopGMAC_is_rx_desc_valid(u32 status);
++bool synopGMAC_is_tx_aborted(u32 status);
++bool synopGMAC_is_tx_carrier_error(u32 status);
++u32 synopGMAC_get_tx_collision_count(u32 status);
++u32 synopGMAC_is_exc_tx_collisions(u32 status);
++bool synopGMAC_is_rx_frame_damaged(u32 status);
++bool synopGMAC_is_rx_frame_collision(u32 status);
++bool synopGMAC_is_rx_crc(u32 status);
++bool synopGMAC_is_frame_dribbling_errors(u32 status);
++bool synopGMAC_is_rx_frame_length_errors(u32 status);
++bool synopGMAC_is_last_rx_desc(synopGMACdevice * gmacdev,DmaDesc *desc);
++bool synopGMAC_is_last_tx_desc(synopGMACdevice * gmacdev,DmaDesc *desc);
++bool synopGMAC_is_rx_desc_chained(DmaDesc * desc);
++bool synopGMAC_is_tx_desc_chained(DmaDesc * desc);
++void synopGMAC_get_desc_data(DmaDesc * desc, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2);
++#ifdef ENH_DESC_8W
++s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2,
++		u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low);
++#else
++s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2 );
++#endif
++s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2,u32 offload_needed);
++s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2);
++#ifdef ENH_DESC_8W
++s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2,
++		u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low);
++#else
++s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2);
++#endif
++void synopGMAC_clear_interrupt(synopGMACdevice *gmacdev);
++u32 synopGMAC_get_interrupt_type(synopGMACdevice *gmacdev);
++u32 synopGMAC_get_interrupt_mask(synopGMACdevice *gmacdev);
++void synopGMAC_enable_interrupt(synopGMACdevice *gmacdev, u32 interrupts);
++void synopGMAC_disable_interrupt_all(synopGMACdevice *gmacdev);
++void synopGMAC_disable_interrupt(synopGMACdevice *gmacdev, u32 interrupts);
++void synopGMAC_enable_dma_rx(synopGMACdevice * gmacdev);
++void synopGMAC_enable_dma_tx(synopGMACdevice * gmacdev);
++void synopGMAC_resume_dma_tx(synopGMACdevice * gmacdev);
++void synopGMAC_resume_dma_rx(synopGMACdevice * gmacdev);
++void synopGMAC_take_desc_ownership(DmaDesc * desc);
++void synopGMAC_take_desc_ownership_rx(synopGMACdevice * gmacdev);
++void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev);
++void synopGMAC_disable_dma_tx(synopGMACdevice * gmacdev);
++void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev);
++/******Following APIs are valid only for Enhanced Descriptor from 3.50a release onwards*******/
++bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status);
++bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status);
++bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev,u32 ext_status);
++bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status);
++/*******************PMT APIs***************************************/
++void synopGMAC_pmt_int_enable(synopGMACdevice *gmacdev);
++void synopGMAC_pmt_int_disable(synopGMACdevice *gmacdev);
++void synopGMAC_power_down_enable(synopGMACdevice *gmacdev);
++void synopGMAC_power_down_disable(synopGMACdevice *gmacdev);
++void synopGMAC_enable_pmt_interrupt(synopGMACdevice *gmacdev);
++void synopGMAC_disable_pmt_interrupt(synopGMACdevice *gmacdev);
++void synopGMAC_magic_packet_enable(synopGMACdevice *gmacdev);
++void synopGMAC_wakeup_frame_enable(synopGMACdevice *gmacdev);
++void synopGMAC_pmt_unicast_enable(synopGMACdevice *gmacdev);
++bool synopGMAC_is_magic_packet_received(synopGMACdevice *gmacdev);
++bool synopGMAC_is_wakeup_frame_received(synopGMACdevice *gmacdev);
++void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 * filter_contents);
++/*******************MMC APIs***************************************/
++void synopGMAC_mmc_counters_stop(synopGMACdevice *gmacdev);
++void synopGMAC_mmc_counters_resume(synopGMACdevice *gmacdev);
++void synopGMAC_mmc_counters_set_selfclear(synopGMACdevice *gmacdev);
++void synopGMAC_mmc_counters_reset_selfclear(synopGMACdevice *gmacdev);
++void synopGMAC_mmc_counters_disable_rollover(synopGMACdevice *gmacdev);
++void synopGMAC_mmc_counters_enable_rollover(synopGMACdevice *gmacdev);
++u32 synopGMAC_read_mmc_counter(synopGMACdevice *gmacdev, u32 counter);
++u32 synopGMAC_read_mmc_rx_int_status(synopGMACdevice *gmacdev);
++u32 synopGMAC_read_mmc_tx_int_status(synopGMACdevice *gmacdev);
++void synopGMAC_disable_mmc_tx_interrupt(synopGMACdevice *gmacdev, u32 mask);
++void synopGMAC_enable_mmc_tx_interrupt(synopGMACdevice *gmacdev, u32 mask);
++void synopGMAC_disable_mmc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask);
++void synopGMAC_enable_mmc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask);
++void synopGMAC_enable_mmc_ipc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask);
++void synopGMAC_disable_mmc_ipc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask);
++/*******************Ip checksum offloading APIs***************************************/
++void synopGMAC_enable_rx_chksum_offload(synopGMACdevice *gmacdev);
++void synopGMAC_disable_rx_Ipchecksum_offload(synopGMACdevice *gmacdev);
++void synopGMAC_rx_tcpip_chksum_drop_enable(synopGMACdevice *gmacdev);
++void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev);
++u32  synopGMAC_is_rx_checksum_error(synopGMACdevice *gmacdev, u32 status);
++bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 status);
++bool synopGMAC_is_tx_payload_checksum_error(synopGMACdevice *gmacdev, u32 status);
++void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *desc);
++void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *desc);
++void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *desc);
++void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc *desc);
++#ifdef AVB_SUPPORT
++void  synopGMACsetAvType(synopGMACdevice *gmacdev, u32 avtype);
++void synopGMACsetAvPrio(synopGMACdevice * gmacdev,u8 priority);
++void synopGMACsetAvCtrlCh(synopGMACdevice * gmacdev,u8 channel);
++void synopGMACsetAvPTPCh (synopGMACdevice * gmacdev,u8 channel);
++void synopGMACsetTxRxPrioPolicy(synopGMACdevice * gmacdev,u8 policy);
++void synopGMACsetTxRxPrio(synopGMACdevice * gmacdev,u8 tx_has_high_prio);
++void synopGMACsetTxRxPrioRatio(synopGMACdevice * gmacdev,u8 tx_rx_prio_ratio);
++void synopGMACsetChPrioWts(synopGMACdevice * gmacdev,u8 weights);
++void synopGMACAvbEnSlot(synopGMACdevice * gmacdev);
++void synopGMACAvbDisSlot (synopGMACdevice * gmacdev);
++void synopGMACAvbEnAdvSlotInt(synopGMACdevice * gmacdev);
++void synopGMACAvbDisAdvSlotInt(synopGMACdevice * gmacdev);
++void synopGMACAvbSetSlotCount(synopGMACdevice * gmacdev, u8 slotcount);
++void synopGMACAvbEnSlotInterrupt(synopGMACdevice * gmacdev);
++void synopGMACAvbDisSlotInterrupt(synopGMACdevice * gmacdev);
++void synopGMACAvbEnableCrSh(synopGMACdevice * gmacdev);
++void synopGMACAvbDisableCrSh(synopGMACdevice * gmacdev);
++void synopGMACAvbEnableCrControl(synopGMACdevice * gmacdev);
++void synopGMACAvbDisableCrControl(synopGMACdevice * gmacdev);
++void synopGMACsetAvbSendSlope(synopGMACdevice * gmacdev,u32 sendslope_val);
++void synopGMACsetAvbIdleSlope(synopGMACdevice * gmacdev,u32 idleslope_val);
++void synopGMACsetAvbHiCredit(synopGMACdevice * gmacdev,u32 hicredit_val);
++void synopGMACsetAvbLoCredit(synopGMACdevice * gmacdev,u32 locredit_val);
++
++void synopGMAC_set_desc_data(DmaDesc *txdesc, u32 Status, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2);
++#endif
++
++
++#endif /* End of file */
+diff --git a/module_drivers/drivers/net/ethernet/ingenic/synopGMAC_plat.c b/module_drivers/drivers/net/ethernet/ingenic/synopGMAC_plat.c
+new file mode 100644
+index 000000000..d46736f8c
+--- /dev/null
++++ b/module_drivers/drivers/net/ethernet/ingenic/synopGMAC_plat.c
+@@ -0,0 +1,94 @@
++/* ===================================================================================
++ * Copyright (c) <2009> Synopsys, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a copy of
++ * this software annotated with this license and associated documentation files
++ * (the "Software"), to deal in the Software without restriction, including without
++ * limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the Software is
++ * furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in all
++ * copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * =================================================================================== */
++
++/**\file
++ *  This file defines the wrapper for the platform/OS related functions
++ *  The function definitions needs to be modified according to the platform
++ *  and the Operating system used.
++ *  This file should be handled with greatest care while porting the driver
++ *  to a different platform running different operating system other than
++ *  Linux 2.6.xx.
++ * \internal
++ * ----------------------------REVISION HISTORY-----------------------------
++ * Synopsys			01/Aug/2007			Created
++ */
++
++#include "synopGMAC_plat.h"
++
++/**
++  * This is a wrapper function for Memory allocation routine. In linux Kernel
++  * it it kmalloc function
++  * @param[in] bytes in bytes to allocate
++  */
++
++void *plat_alloc_memory(u32 bytes)
++{
++	return kmalloc((size_t)bytes, GFP_KERNEL);
++}
++
++/**
++  * This is a wrapper function for consistent dma-able Memory allocation routine.
++  * @param[in] bytes in bytes to allocate
++  */
++
++void *plat_alloc_consistent_dmaable_memory(struct device *dev, u32 size, u32 *addr)
++{
++	return dma_alloc_coherent(dev, size, addr, GFP_ATOMIC);
++}
++
++/**
++  * This is a wrapper function for freeing consistent dma-able Memory.
++  * @param[in] bytes in bytes to allocate
++  */
++
++void plat_free_consistent_dmaable_memory(struct device *dev, u32 size, void * addr,u32 dma_addr)
++{
++	dma_free_coherent(dev, size, addr, dma_addr);
++}
++
++
++
++/**
++  * This is a wrapper function for Memory free routine. In linux Kernel
++  * it it kfree function
++  * @param[in] buffer pointer to be freed
++  */
++void plat_free_memory(void *buffer)
++{
++	kfree(buffer);
++	return ;
++}
++
++
++/**
++  * This is a wrapper function for platform dependent delay
++  * Take care while passing the argument to this function
++  * @param[in] buffer pointer to be freed
++  */
++void plat_delay(u32 delay)
++{
++	while (delay--);
++	return;
++}
++
++
++
+diff --git a/module_drivers/drivers/net/ethernet/ingenic/synopGMAC_plat.h b/module_drivers/drivers/net/ethernet/ingenic/synopGMAC_plat.h
+new file mode 100644
+index 000000000..a69319e80
+--- /dev/null
++++ b/module_drivers/drivers/net/ethernet/ingenic/synopGMAC_plat.h
+@@ -0,0 +1,211 @@
++/* ===================================================================================
++ * Copyright (c) <2009> Synopsys, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a copy of
++ * this software annotated with this license and associated documentation files
++ * (the "Software"), to deal in the Software without restriction, including without
++ * limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the Software is
++ * furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in all
++ * copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * =================================================================================== */
++
++/**\file
++ *  This file serves as the wrapper for the platform/OS dependent functions
++ *  It is needed to modify these functions accordingly based on the platform and the
++ *  OS. Whenever the synopsys GMAC driver ported on to different platform, this file
++ *  should be handled at most care.
++ *  The corresponding function definitions for non-inline functions are available in
++ *  synopGMAC_plat.c file.
++ * \internal
++ * -------------------------------------REVISION HISTORY---------------------------
++ * Synopsys 				01/Aug/2007		 	   Created
++ */
++
++
++#ifndef SYNOP_GMAC_PLAT_H
++#define SYNOP_GMAC_PLAT_H 1
++
++
++#include <linux/kernel.h>
++#include <asm/io.h>
++#include <linux/device.h>
++#include <linux/gfp.h>
++#include <linux/slab.h>
++#include <linux/dma-mapping.h>
++
++#define TR0(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args)
++
++extern int debug_enable;
++
++#if 0
++#ifdef DEBUG
++#undef TR
++# define TR(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args)
++#else
++# define TR(fmt, args...) /* not debugging: nothing */
++#endif
++#endif
++
++#define TR(fmt, args...)						\
++	do {								\
++		if (debug_enable) {					\
++			printk(KERN_CRIT "SynopGMAC: " fmt, ##args);	\
++		}							\
++	} while(0)
++
++#if 0
++typedef int bool;
++enum synopGMAC_boolean
++ {
++    false = 0,
++    true = 1
++ };
++#endif
++
++#if (defined(CONFIG_SOC_X2000) || defined(CONFIG_SOC_M300) || defined(CONFIG_SOC_X2100) || defined(CONFIG_SOC_X2500) || defined(CONFIG_SOC_X1600))
++#define LPI_SUPPORT
++#endif
++
++#define DEFAULT_DELAY_VARIABLE  10
++#define DEFAULT_LOOP_VARIABLE   10000
++
++/* There are platform related endian conversions
++ *
++ */
++
++#define LE32_TO_CPU	__le32_to_cpu
++#define BE32_TO_CPU	__be32_to_cpu
++#define CPU_TO_LE32	__cpu_to_le32
++
++/* Error Codes */
++#define ESYNOPGMACNOERR   0
++#define ESYNOPGMACNOMEM   1
++#define ESYNOPGMACPHYERR  2
++#define ESYNOPGMACBUSY    3
++
++struct Network_interface_data
++{
++	u32 unit;
++	u32 addr;
++	u32 data;
++};
++
++
++/**
++  * These are the wrapper function prototypes for OS/platform related routines
++  */
++
++void * plat_alloc_memory(u32 );
++void   plat_free_memory(void *);
++
++void * plat_alloc_consistent_dmaable_memory(struct device *, u32, u32 *);
++void   plat_free_consistent_dmaable_memory (struct device *, u32, void *, u32);
++
++void   plat_delay(u32);
++
++
++/**
++ * The Low level function to read register contents from Hardware.
++ *
++ * @param[in] pointer to the base of register map
++ * @param[in] Offset from the base
++ * \return  Returns the register contents
++ */
++static u32 __inline__ synopGMACReadReg(u32 *RegBase, u32 RegOffset)
++{
++
++  u32 addr = (u32)RegBase + RegOffset;
++  u32 data = readl((void *)addr);
++  //printk("=====>%s: RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, (u32)RegBase, RegOffset, data );
++  return data;
++}
++
++/**
++ * The Low level function to write to a register in Hardware.
++ *
++ * @param[in] pointer to the base of register map
++ * @param[in] Offset from the base
++ * @param[in] Data to be written
++ * \return  void
++ */
++static void  __inline__ synopGMACWriteReg(u32 *RegBase, u32 RegOffset, u32 RegData)
++{
++
++  u32 addr = (u32)RegBase + RegOffset;
++  //printk("=====>%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__,(u32) RegBase, RegOffset, RegData );
++  writel(RegData,(void *)addr);
++  //*((volatile unsigned int *)addr) = RegData;
++  return;
++}
++
++/**
++ * The Low level function to set bits of a register in Hardware.
++ *
++ * @param[in] pointer to the base of register map
++ * @param[in] Offset from the base
++ * @param[in] Bit mask to set bits to logical 1
++ * \return  void
++ */
++static void __inline__ synopGMACSetBits(u32 *RegBase, u32 RegOffset, u32 BitPos)
++{
++  u32 addr = (u32)RegBase + RegOffset;
++  u32 data = readl((void *)addr);
++  data |= BitPos;
++//  TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data );
++  writel(data,(void *)addr);
++//  TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data );
++  return;
++}
++
++
++/**
++ * The Low level function to clear bits of a register in Hardware.
++ *
++ * @param[in] pointer to the base of register map
++ * @param[in] Offset from the base
++ * @param[in] Bit mask to clear bits to logical 0
++ * \return  void
++ */
++static void __inline__ synopGMACClearBits(u32 *RegBase, u32 RegOffset, u32 BitPos)
++{
++  u32 addr = (u32)RegBase + RegOffset;
++  u32 data = readl((void *)addr);
++  data &= (~BitPos);
++//  TR("%s !!!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data );
++  writel(data,(void *)addr);
++//  TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data );
++  return;
++}
++
++/**
++ * The Low level function to Check the setting of the bits.
++ *
++ * @param[in] pointer to the base of register map
++ * @param[in] Offset from the base
++ * @param[in] Bit mask to set bits to logical 1
++ * \return  returns TRUE if set to '1' returns FALSE if set to '0'. Result undefined there are no bit set in the BitPos argument.
++ *
++ */
++static bool __inline__ synopGMACCheckBits(u32 *RegBase, u32 RegOffset, u32 BitPos)
++{
++  u32 addr = (u32)RegBase + RegOffset;
++  u32 data = readl((void *)addr);
++  data &= BitPos;
++  if(data)  return true;
++  else	    return false;
++
++}
++
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/Kconfig b/module_drivers/drivers/net/wireless/Kconfig
+new file mode 100644
+index 000000000..fe6b1103b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/Kconfig
+@@ -0,0 +1,2 @@
++source "module_drivers/drivers/net/wireless/bcmdhd/Kconfig"
++source "module_drivers/drivers/net/wireless/realtek/rtl8723ds/Kconfig"
+diff --git a/module_drivers/drivers/net/wireless/Makefile b/module_drivers/drivers/net/wireless/Makefile
+new file mode 100644
+index 000000000..65455a54f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/Makefile
+@@ -0,0 +1,4 @@
++obj-$(CONFIG_BCMDHD) += bcmdhd/
++obj-y	      += realtek/
++
++
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/Kconfig b/module_drivers/drivers/net/wireless/bcmdhd/Kconfig
+new file mode 100644
+index 000000000..fffcee200
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/Kconfig
+@@ -0,0 +1,60 @@
++config BCMDHD
++	tristate "Broadcom FullMAC wireless cards support"
++	help
++	  This module adds support for wireless adapters based on
++	  Broadcom FullMAC chipset.
++
++config BCMDHD_FW_PATH
++	depends on BCMDHD
++	string "Firmware path"
++	default "/system/etc/firmware/fw_bcmdhd.bin"
++	help
++	  Path to the firmware file.
++
++config BCMDHD_NVRAM_PATH
++	depends on BCMDHD
++	string "NVRAM path"
++	default "/system/etc/firmware/nvram.txt"
++	help
++	  Path to the calibration file.
++
++config BCMDHD_WEXT
++	bool "Enable WEXT support"
++	depends on BCMDHD && CFG80211 = n
++	select WIRELESS_EXT
++	select WEXT_PRIV
++	help
++	  Enables WEXT support
++
++choice
++	prompt "Enable Chip Interface"
++	depends on BCMDHD
++	help
++		Enable Chip Interface.
++config BCMDHD_SDIO
++		bool "SDIO bus interface support"
++		depends on BCMDHD && MMC
++config BCMDHD_PCIE
++		bool "PCIe bus interface support"
++		depends on BCMDHD && PCI
++config BCMDHD_USB
++		bool "USB bus interface support"
++		depends on BCMDHD && USB
++endchoice
++
++choice
++	depends on BCMDHD && BCMDHD_SDIO
++	prompt "Interrupt type"
++	help
++		Interrupt type
++config BCMDHD_OOB
++	depends on BCMDHD && BCMDHD_SDIO
++	bool "Out-of-Band Interrupt"
++	help
++		Interrupt from WL_HOST_WAKE.
++config BCMDHD_SDIO_IRQ
++	depends on BCMDHD && BCMDHD_SDIO
++	bool "In-Band Interrupt"
++	help
++	  Interrupt from SDIO DAT[1]
++endchoice
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/Makefile b/module_drivers/drivers/net/wireless/bcmdhd/Makefile
+new file mode 100644
+index 000000000..31c21657c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/Makefile
+@@ -0,0 +1,169 @@
++# bcmdhd
++
++MODULE_NAME := bcmdhd
++#CONFIG_BCMDHD := m
++#CONFIG_BCMDHD_SDIO := y
++#CONFIG_BCMDHD_PCIE := y
++#CONFIG_BCMDHD_USB := y
++
++#CONFIG_BCMDHD_OOB := y
++#CONFIG_BCMDHD_CUSB := y
++CONFIG_BCMDHD_PROPTXSTATUS := y
++#CONFIG_DHD_USE_STATIC_BUF := y
++#CONFIG_VTS_SUPPORT := y
++
++CONFIG_MACH_PLATFORM := y
++#CONFIG_BCMDHD_DTS := y
++
++DHDCFLAGS = -Wall -Wstrict-prototypes -Dlinux -DBCMDRIVER                 \
++	-DBCMDONGLEHOST -DUNRELEASEDCHIP -DBCMDMA32 -DBCMFILEIMAGE            \
++	-DDHDTHREAD -DDHD_DEBUG -DSHOW_EVENTS -DBCMDBG -DGET_OTP_MAC_ENABLE   \
++	-DWIFI_ACT_FRAME -DARP_OFFLOAD_SUPPORT -DSUPPORT_PM2_ONLY             \
++	-DKEEP_ALIVE -DPKT_FILTER_SUPPORT -DDHDTCPACK_SUPPRESS                \
++	-DDHD_DONOT_FORWARD_BCMEVENT_AS_NETWORK_PKT                           \
++	-DMULTIPLE_SUPPLICANT -DTSQ_MULTIPLIER -DMFP -DDHD_8021X_DUMP         \
++	-DWL_EXT_IAPSTA -DWL_ESCAN -DCCODE_LIST                               \
++	-DENABLE_INSMOD_NO_FW_LOAD                                            \
++	-I$(srctree)/$(src) -I$(srctree)/$(src)/include
++
++DHDOFILES = aiutils.o siutils.o sbutils.o bcmutils.o bcmwifi_channels.o   \
++	dhd_linux.o dhd_linux_platdev.o dhd_linux_sched.o dhd_pno.o           \
++	dhd_common.o dhd_ip.o dhd_linux_wq.o dhd_custom_gpio.o                \
++	bcmevent.o hndpmu.o linux_osl.o wldev_common.o wl_android.o bcmxtlv.o \
++	dhd_debug_linux.o dhd_debug.o dhd_mschdbg.o hnd_pktq.o hnd_pktpool.o  \
++	dhd_config.o dhd_ccode.o wl_event.o wl_android_ext.o wl_escan.o
++
++ifneq ($(CONFIG_WIRELESS_EXT),)
++	DHDOFILES += wl_iw.o
++	DHDCFLAGS += -DSOFTAP -DWL_WIRELESS_EXT -DUSE_IW
++endif
++ifneq ($(CONFIG_CFG80211),)
++	DHDOFILES += wl_cfg80211.o wl_cfgp2p.o wl_linux_mon.o wl_cfg_btcoex.o wl_cfgvendor.o
++	DHDOFILES += dhd_cfg80211.o
++	DHDCFLAGS += -DWL_CFG80211 -DWLP2P -DWL_CFG80211_STA_EVENT -DWL_ENABLE_P2P_IF
++	DHDCFLAGS += -DWL_IFACE_COMB_NUM_CHANNELS
++	DHDCFLAGS += -DCUSTOM_PNO_EVENT_LOCK_xTIME=7
++	DHDCFLAGS += -DWL_SUPPORT_AUTO_CHANNEL
++	DHDCFLAGS += -DWL_SUPPORT_BACKPORTED_KPATCHES
++	DHDCFLAGS += -DESCAN_RESULT_PATCH -DESCAN_BUF_OVERFLOW_MGMT
++	DHDCFLAGS += -DVSDB -DWL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++	DHDCFLAGS += -DWLTDLS -DMIRACAST_AMPDU_SIZE=8
++	DHDCFLAGS += -DWL_VIRTUAL_APSTA
++	DHDCFLAGS += -DPNO_SUPPORT -DEXPLICIT_DISCIF_CLEANUP
++#	DHDCFLAGS += -DWL_SAE
++endif
++
++#BCMDHD_SDIO
++ifneq ($(CONFIG_BCMDHD_SDIO),)
++DHDCFLAGS += -DBCMSDIO -DMMC_SDIO_ABORT -DBCMLXSDMMC -DUSE_SDIOFIFO_IOVAR \
++	-DSDTEST -DBDC -DDHD_USE_IDLECOUNT -DCUSTOM_SDIO_F2_BLKSIZE=256       \
++	-DBCMSDIOH_TXGLOM -DBCMSDIOH_TXGLOM_EXT -DRXFRAME_THREAD              \
++	-DDHDENABLE_TAILPAD -DSUPPORT_P2P_GO_PS                               \
++	-DBCMSDIO_RXLIM_POST -DCONSOLE_DPC
++ifeq ($(CONFIG_BCMDHD_OOB),y)
++	DHDCFLAGS += -DOOB_INTR_ONLY -DCUSTOMER_OOB -DHW_OOB
++ifeq ($(CONFIG_BCMDHD_DISABLE_WOWLAN),y)
++	DHDCFLAGS += -DDISABLE_WOWLAN
++endif
++else
++	DHDCFLAGS += -DSDIO_ISR_THREAD
++endif
++DHDOFILES += bcmsdh.o bcmsdh_linux.o bcmsdh_sdmmc.o bcmsdh_sdmmc_linux.o  \
++	dhd_sdio.o dhd_cdc.o dhd_wlfc.o
++endif
++
++#BCMDHD_PCIE
++ifneq ($(CONFIG_BCMDHD_PCIE),)
++DHDCFLAGS += -DPCIE_FULL_DONGLE -DBCMPCIE -DCUSTOM_DPC_PRIO_SETTING=-1    \
++	-DDONGLE_ENABLE_ISOLATION
++DHDCFLAGS += -DDHD_LB -DDHD_LB_RXP -DDHD_LB_STATS #-DDHD_LB_TXP
++ifeq ($(CONFIG_BCMDHD_OOB),y)
++	DHDCFLAGS += -DCUSTOMER_OOB -DBCMPCIE_OOB_HOST_WAKE
++endif
++ifneq ($(CONFIG_PCI_MSI),)
++	DHDCFLAGS += -DDHD_USE_MSI
++endif
++DHDOFILES += dhd_pcie.o dhd_pcie_linux.o pcie_core.o dhd_flowring.o       \
++	dhd_msgbuf.o
++endif
++
++#BCMDHD_USB
++ifneq ($(CONFIG_BCMDHD_USB),)
++DHDCFLAGS += -DUSBOS_TX_THREAD -DBCMDBUS -DBCMTRXV2 -DDBUS_USB_LOOPBACK   \
++	-DBDC
++DHDCFLAGS += -DBCM_REQUEST_FW -DEXTERNAL_FW_PATH
++#DHDCFLAGS :=$(filter-out -DENABLE_INSMOD_NO_FW_LOAD,$(DHDCFLAGS))
++ifneq ($(CONFIG_BCMDHD_CUSB),)
++	DHDCFLAGS += -DBCMUSBDEV_COMPOSITE
++	DHDCFLAGS :=$(filter-out -DENABLE_INSMOD_NO_FW_LOAD,$(DHDCFLAGS))
++endif
++DHDOFILES += dbus.o dbus_usb.o dbus_usb_linux.o dhd_cdc.o dhd_wlfc.o
++endif
++
++#PROPTXSTATUS
++ifeq ($(CONFIG_BCMDHD_PROPTXSTATUS),y)
++ifneq ($(CONFIG_BCMDHD_USB),)
++	DHDCFLAGS += -DPROP_TXSTATUS
++endif
++ifneq ($(CONFIG_BCMDHD_SDIO),)
++	DHDCFLAGS += -DPROP_TXSTATUS
++endif
++ifneq ($(CONFIG_CFG80211),)
++	DHDCFLAGS += -DPROP_TXSTATUS_VSDB
++endif
++endif
++
++#VTS_SUPPORT
++ifeq ($(CONFIG_VTS_SUPPORT),y)
++ifneq ($(CONFIG_CFG80211),)
++DHDCFLAGS += -DGSCAN_SUPPORT -DRTT_SUPPORT -DLINKSTAT_SUPPORT             \
++	-DCUSTOM_COUNTRY_CODE                                                 \
++	-DDEBUGABILITY -DDBG_PKT_MON -DDHD_FW_COREDUMP                        \
++	-DAPF -DNDO_CONFIG_SUPPORT -DRSSI_MONITOR_SUPPORT -DDHD_WAKE_STATUS
++DHDOFILES += dhd_rtt.o bcm_app_utils.o
++endif
++endif
++
++# MESH support for kernel 3.10 later
++ifeq ($(CONFIG_WL_MESH),y)
++	DHDCFLAGS += -DWLMESH
++ifneq ($(CONFIG_CFG80211),)
++	DHDCFLAGS += -DWLMESH_CFG80211
++endif
++ifneq ($(CONFIG_BCMDHD_PCIE),)
++	DHDCFLAGS += -DBCM_HOST_BUF -DDMA_HOST_BUFFER_LEN=0x80000
++endif
++	DHDCFLAGS += -DDHD_UPDATE_INTF_MAC
++	DHDCFLAGS :=$(filter-out -DDHD_FW_COREDUMP,$(DHDCFLAGS))
++	DHDCFLAGS :=$(filter-out -DSET_RANDOM_MAC_SOFTAP,$(DHDCFLAGS))
++endif
++
++obj-$(CONFIG_BCMDHD) += $(MODULE_NAME).o
++$(MODULE_NAME)-objs += $(DHDOFILES)
++
++ifeq ($(CONFIG_MACH_PLATFORM),y)
++	DHDOFILES += dhd_gpio.o
++ifeq ($(CONFIG_BCMDHD_DTS),y)
++	DHDCFLAGS += -DCONFIG_DTS
++else
++	DHDCFLAGS += -DCUSTOMER_HW -DDHD_OF_SUPPORT
++endif
++	DHDCFLAGS += -DCUSTOMER_HW_INGENIC
++#	DHDCFLAGS += -DBCMWAPI_WPI -DBCMWAPI_WAI
++endif
++
++ifeq ($(CONFIG_BCMDHD_AG),y)
++	DHDCFLAGS += -DBAND_AG
++endif
++
++ifeq ($(CONFIG_DHD_USE_STATIC_BUF),y)
++	obj-m += dhd_static_buf.o
++	DHDCFLAGS += -DSTATIC_WL_PRIV_STRUCT -DENHANCED_STATIC_BUF
++	DHDCFLAGS += -DCONFIG_DHD_USE_STATIC_BUF
++	DHDCFLAGS += -DDHD_USE_STATIC_MEMDUMP
++endif
++
++EXTRA_CFLAGS = $(DHDCFLAGS)
++ifeq ($(CONFIG_BCMDHD),m)
++EXTRA_LDFLAGS += --strip-debug
++endif
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/README b/module_drivers/drivers/net/wireless/bcmdhd/README
+new file mode 100644
+index 000000000..4b292ae0f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/README
+@@ -0,0 +1,2 @@
++版本更新:
++当�版本 bcmdhd.1.579.77.41.x
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/aiutils.c b/module_drivers/drivers/net/wireless/bcmdhd/aiutils.c
+new file mode 100644
+index 000000000..f88b12336
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/aiutils.c
+@@ -0,0 +1,1810 @@
++/*
++ * Misc utility routines for accessing chip-specific features
++ * of the SiliconBackplane-based Broadcom chips.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: aiutils.c 625027 2016-03-15 08:20:18Z $
++ */
++#include <bcm_cfg.h>
++#include <typedefs.h>
++#include <bcmdefs.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <siutils.h>
++#include <hndsoc.h>
++#include <sbchipc.h>
++#include <pcicfg.h>
++
++#include "siutils_priv.h"
++#include <bcmdevs.h>
++
++#define BCM5357_DMP() (0)
++#define BCM53573_DMP() (0)
++#define BCM4707_DMP() (0)
++#define PMU_DMP() (0)
++#define GCI_DMP() (0)
++#define remap_coreid(sih, coreid)	(coreid)
++#define remap_corerev(sih, corerev)	(corerev)
++
++/* EROM parsing */
++
++static uint32
++get_erom_ent(si_t *sih, uint32 **eromptr, uint32 mask, uint32 match)
++{
++	uint32 ent;
++	uint inv = 0, nom = 0;
++	uint32 size = 0;
++
++	while (TRUE) {
++		ent = R_REG(si_osh(sih), *eromptr);
++		(*eromptr)++;
++
++		if (mask == 0)
++			break;
++
++		if ((ent & ER_VALID) == 0) {
++			inv++;
++			continue;
++		}
++
++		if (ent == (ER_END | ER_VALID))
++			break;
++
++		if ((ent & mask) == match)
++			break;
++
++		/* escape condition related EROM size if it has invalid values */
++		size += sizeof(*eromptr);
++		if (size >= ER_SZ_MAX) {
++			SI_ERROR(("Failed to find end of EROM marker\n"));
++			break;
++		}
++
++		nom++;
++	}
++
++	SI_VMSG(("%s: Returning ent 0x%08x\n", __FUNCTION__, ent));
++	if (inv + nom) {
++		SI_VMSG(("  after %d invalid and %d non-matching entries\n", inv, nom));
++	}
++	return ent;
++}
++
++static uint32
++get_asd(si_t *sih, uint32 **eromptr, uint sp, uint ad, uint st, uint32 *addrl, uint32 *addrh,
++	uint32 *sizel, uint32 *sizeh)
++{
++	uint32 asd, sz, szd;
++
++	BCM_REFERENCE(ad);
++
++	asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
++	if (((asd & ER_TAG1) != ER_ADD) ||
++	    (((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
++	    ((asd & AD_ST_MASK) != st)) {
++		/* This is not what we want, "push" it back */
++		(*eromptr)--;
++		return 0;
++	}
++	*addrl = asd & AD_ADDR_MASK;
++	if (asd & AD_AG32)
++		*addrh = get_erom_ent(sih, eromptr, 0, 0);
++	else
++		*addrh = 0;
++	*sizeh = 0;
++	sz = asd & AD_SZ_MASK;
++	if (sz == AD_SZ_SZD) {
++		szd = get_erom_ent(sih, eromptr, 0, 0);
++		*sizel = szd & SD_SZ_MASK;
++		if (szd & SD_SG32)
++			*sizeh = get_erom_ent(sih, eromptr, 0, 0);
++	} else
++		*sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
++
++	SI_VMSG(("  SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
++	        sp, ad, st, *sizeh, *sizel, *addrh, *addrl));
++
++	return asd;
++}
++
++
++/* parse the enumeration rom to identify all cores */
++void
++ai_scan(si_t *sih, void *regs, uint devid)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	chipcregs_t *cc = (chipcregs_t *)regs;
++	uint32 erombase, *eromptr, *eromlim;
++	axi_wrapper_t * axi_wrapper = sii->axi_wrapper;
++
++	BCM_REFERENCE(devid);
++
++	erombase = R_REG(sii->osh, &cc->eromptr);
++
++	switch (BUSTYPE(sih->bustype)) {
++	case SI_BUS:
++		eromptr = (uint32 *)REG_MAP(erombase, SI_CORE_SIZE);
++		break;
++
++	case PCI_BUS:
++		/* Set wrappers address */
++		sii->curwrap = (void *)((uintptr)regs + SI_CORE_SIZE);
++
++		/* Now point the window at the erom */
++		OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, erombase);
++		eromptr = regs;
++		break;
++
++#ifdef BCMSDIO
++	case SPI_BUS:
++	case SDIO_BUS:
++		eromptr = (uint32 *)(uintptr)erombase;
++		break;
++#endif	/* BCMSDIO */
++
++	case PCMCIA_BUS:
++	default:
++		SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n", sih->bustype));
++		ASSERT(0);
++		return;
++	}
++	eromlim = eromptr + (ER_REMAPCONTROL / sizeof(uint32));
++	sii->axi_num_wrappers = 0;
++
++	SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n",
++	         OSL_OBFUSCATE_BUF(regs), erombase,
++		OSL_OBFUSCATE_BUF(eromptr), OSL_OBFUSATE_BUF(eromlim)));
++	while (eromptr < eromlim) {
++		uint32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
++		uint32 mpd, asd, addrl, addrh, sizel, sizeh;
++		uint i, j, idx;
++		bool br;
++
++		br = FALSE;
++
++		/* Grok a component */
++		cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
++		if (cia == (ER_END | ER_VALID)) {
++			SI_VMSG(("Found END of erom after %d cores\n", sii->numcores));
++			return;
++		}
++
++		cib = get_erom_ent(sih, &eromptr, 0, 0);
++
++		if ((cib & ER_TAG) != ER_CI) {
++			SI_ERROR(("CIA not followed by CIB\n"));
++			goto error;
++		}
++
++		cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
++		mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
++		crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
++		nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
++		nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
++		nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
++		nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
++
++#ifdef BCMDBG_SI
++		SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, "
++		         "nsw = %d, nmp = %d & nsp = %d\n",
++		         mfg, cid, crev, OSL_OBFUSCATE_BUF(eromptr - 1), nmw, nsw, nmp, nsp));
++#else
++		BCM_REFERENCE(crev);
++#endif
++
++		if (CHIPID(sih->chip) == BCM4347_CHIP_ID) {
++			/* 4347 has more entries for ARM core
++			 * This should apply to all chips but crashes on router
++			 * This is a temp fix to be further analyze
++			 */
++			if (nsp == 0)
++				continue;
++		} else {
++			/* Include Default slave wrapper for timeout monitoring */
++			if ((nsp == 0) ||
++#if !defined(AXI_TIMEOUTS) && !defined(BCM_BACKPLANE_TIMEOUT)
++				((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) ||
++#endif /* !defined(AXI_TIMEOUTS) && !defined(BCM_BACKPLANE_TIMEOUT) */
++				FALSE) {
++				continue;
++			}
++		}
++
++		if ((nmw + nsw == 0)) {
++			/* A component which is not a core */
++			if (cid == OOB_ROUTER_CORE_ID) {
++				asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
++					&addrl, &addrh, &sizel, &sizeh);
++				if (asd != 0) {
++					sii->oob_router = addrl;
++				}
++			}
++			if (cid != GMAC_COMMON_4706_CORE_ID && cid != NS_CCB_CORE_ID &&
++				cid != PMU_CORE_ID && cid != GCI_CORE_ID)
++				continue;
++		}
++
++		idx = sii->numcores;
++
++		cores_info->cia[idx] = cia;
++		cores_info->cib[idx] = cib;
++		cores_info->coreid[idx] = remap_coreid(sih, cid);
++
++		for (i = 0; i < nmp; i++) {
++			mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
++			if ((mpd & ER_TAG) != ER_MP) {
++				SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
++				goto error;
++			}
++			SI_VMSG(("  Master port %d, mp: %d id: %d\n", i,
++			         (mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
++			         (mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
++		}
++
++		/* First Slave Address Descriptor should be port 0:
++		 * the main register space for the core
++		 */
++		asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh, &sizel, &sizeh);
++		if (asd == 0) {
++			do {
++			/* Try again to see if it is a bridge */
++			asd = get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl, &addrh,
++			              &sizel, &sizeh);
++			if (asd != 0)
++				br = TRUE;
++			else {
++					if (br == TRUE) {
++						break;
++					}
++					else if ((addrh != 0) || (sizeh != 0) ||
++						(sizel != SI_CORE_SIZE)) {
++						SI_ERROR(("addrh = 0x%x\t sizeh = 0x%x\t size1 ="
++							"0x%x\n", addrh, sizeh, sizel));
++						SI_ERROR(("First Slave ASD for"
++							"core 0x%04x malformed "
++							"(0x%08x)\n", cid, asd));
++						goto error;
++					}
++				}
++			} while (1);
++		}
++		cores_info->coresba[idx] = addrl;
++		cores_info->coresba_size[idx] = sizel;
++		/* Get any more ASDs in port 0 */
++		j = 1;
++		do {
++			asd = get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl, &addrh,
++			              &sizel, &sizeh);
++			if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
++				cores_info->coresba2[idx] = addrl;
++				cores_info->coresba2_size[idx] = sizel;
++			}
++			j++;
++		} while (asd != 0);
++
++		/* Go through the ASDs for other slave ports */
++		for (i = 1; i < nsp; i++) {
++			j = 0;
++			do {
++				asd = get_asd(sih, &eromptr, i, j, AD_ST_SLAVE, &addrl, &addrh,
++				              &sizel, &sizeh);
++
++				if (asd == 0)
++					break;
++				j++;
++			} while (1);
++			if (j == 0) {
++				SI_ERROR((" SP %d has no address descriptors\n", i));
++				goto error;
++			}
++		}
++
++		/* Now get master wrappers */
++		for (i = 0; i < nmw; i++) {
++			asd = get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl, &addrh,
++			              &sizel, &sizeh);
++			if (asd == 0) {
++				SI_ERROR(("Missing descriptor for MW %d\n", i));
++				goto error;
++			}
++			if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
++				SI_ERROR(("Master wrapper %d is not 4KB\n", i));
++				goto error;
++			}
++			if (i == 0)
++				cores_info->wrapba[idx] = addrl;
++			else if (i == 1)
++				cores_info->wrapba2[idx] = addrl;
++
++
++			ASSERT(sii->axi_num_wrappers < SI_MAX_AXI_WRAPPERS);
++			axi_wrapper[sii->axi_num_wrappers].mfg = mfg;
++			axi_wrapper[sii->axi_num_wrappers].cid = cid;
++			axi_wrapper[sii->axi_num_wrappers].rev = crev;
++			axi_wrapper[sii->axi_num_wrappers].wrapper_type = AI_MASTER_WRAPPER;
++			axi_wrapper[sii->axi_num_wrappers].wrapper_addr = addrl;
++			sii->axi_num_wrappers++;
++			SI_VMSG(("MASTER WRAPPER: %d, mfg:%x, cid:%x, rev:%x, addr:%x, size:%x\n",
++					sii->axi_num_wrappers, mfg, cid, crev, addrl, sizel));
++		}
++
++		/* And finally slave wrappers */
++		for (i = 0; i < nsw; i++) {
++			uint fwp = (nsp == 1) ? 0 : 1;
++			asd = get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP, &addrl, &addrh,
++			              &sizel, &sizeh);
++
++			/* cache APB bridge wrapper address for set/clear timeout */
++			if ((mfg == MFGID_ARM) && (cid == APB_BRIDGE_ID)) {
++				ASSERT(sii->num_br < SI_MAXBR);
++				sii->br_wrapba[sii->num_br++] = addrl;
++			}
++
++			if (asd == 0) {
++				SI_ERROR(("Missing descriptor for SW %d\n", i));
++				goto error;
++			}
++			if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
++				SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
++				goto error;
++			}
++			if ((nmw == 0) && (i == 0))
++				cores_info->wrapba[idx] = addrl;
++			else if ((nmw == 0) && (i == 1))
++				cores_info->wrapba2[idx] = addrl;
++
++			/* Include all slave wrappers to the list to
++			 * enable and monitor watchdog timeouts
++			 */
++
++			ASSERT(sii->axi_num_wrappers < SI_MAX_AXI_WRAPPERS);
++			axi_wrapper[sii->axi_num_wrappers].mfg = mfg;
++			axi_wrapper[sii->axi_num_wrappers].cid = cid;
++			axi_wrapper[sii->axi_num_wrappers].rev = crev;
++			axi_wrapper[sii->axi_num_wrappers].wrapper_type = AI_SLAVE_WRAPPER;
++			axi_wrapper[sii->axi_num_wrappers].wrapper_addr = addrl;
++			sii->axi_num_wrappers++;
++
++			SI_VMSG(("SLAVE WRAPPER: %d,  mfg:%x, cid:%x, rev:%x, addr:%x, size:%x\n",
++				sii->axi_num_wrappers,  mfg, cid, crev, addrl, sizel));
++		}
++
++
++#ifndef BCM_BACKPLANE_TIMEOUT
++		/* Don't record bridges */
++		if (br)
++			continue;
++#endif
++
++		/* Done with core */
++		sii->numcores++;
++	}
++
++	SI_ERROR(("Reached end of erom without finding END\n"));
++
++error:
++	sii->numcores = 0;
++	return;
++}
++
++#define AI_SETCOREIDX_MAPSIZE(coreid) \
++	(((coreid) == NS_CCB_CORE_ID) ? 15 * SI_CORE_SIZE : SI_CORE_SIZE)
++
++/* This function changes the logical "focus" to the indicated core.
++ * Return the current core's virtual address.
++ */
++static volatile void *
++_ai_setcoreidx(si_t *sih, uint coreidx, uint use_wrap2)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint32 addr, wrap, wrap2;
++	volatile void *regs;
++
++	if (coreidx >= MIN(sii->numcores, SI_MAXCORES))
++		return (NULL);
++
++	addr = cores_info->coresba[coreidx];
++	wrap = cores_info->wrapba[coreidx];
++	wrap2 = cores_info->wrapba2[coreidx];
++
++#ifdef BCM_BACKPLANE_TIMEOUT
++	/* No need to disable interrupts while entering/exiting APB bridge core */
++	if ((cores_info->coreid[coreidx] != APB_BRIDGE_CORE_ID) &&
++		(cores_info->coreid[sii->curidx] != APB_BRIDGE_CORE_ID))
++#endif /* BCM_BACKPLANE_TIMEOUT */
++	{
++		/*
++		 * If the user has provided an interrupt mask enabled function,
++		 * then assert interrupts are disabled before switching the core.
++		 */
++		ASSERT((sii->intrsenabled_fn == NULL) ||
++			!(*(sii)->intrsenabled_fn)((sii)->intr_arg));
++	}
++
++	switch (BUSTYPE(sih->bustype)) {
++	case SI_BUS:
++		/* map new one */
++		if (!cores_info->regs[coreidx]) {
++			cores_info->regs[coreidx] = REG_MAP(addr,
++				AI_SETCOREIDX_MAPSIZE(cores_info->coreid[coreidx]));
++			ASSERT(GOODREGS(cores_info->regs[coreidx]));
++		}
++		sii->curmap = regs = cores_info->regs[coreidx];
++		if (!cores_info->wrappers[coreidx] && (wrap != 0)) {
++			cores_info->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
++			ASSERT(GOODREGS(cores_info->wrappers[coreidx]));
++		}
++		if (!cores_info->wrappers2[coreidx] && (wrap2 != 0)) {
++			cores_info->wrappers2[coreidx] = REG_MAP(wrap2, SI_CORE_SIZE);
++			ASSERT(GOODREGS(cores_info->wrappers2[coreidx]));
++		}
++		if (use_wrap2)
++			sii->curwrap = cores_info->wrappers2[coreidx];
++		else
++			sii->curwrap = cores_info->wrappers[coreidx];
++		break;
++
++	case PCI_BUS:
++#ifdef BCM_BACKPLANE_TIMEOUT
++		/* No need to set the BAR0 if core is APB Bridge.
++		 * This is to reduce 2 PCI writes while checkng for errlog
++		 */
++		if (cores_info->coreid[coreidx] != APB_BRIDGE_CORE_ID)
++#endif /* BCM_BACKPLANE_TIMEOUT */
++		{
++			/* point bar0 window */
++			OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, addr);
++		}
++
++		regs = sii->curmap;
++		/* point bar0 2nd 4KB window to the primary wrapper */
++		if (use_wrap2)
++			wrap = wrap2;
++		if (PCIE_GEN2(sii))
++			OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_WIN2, 4, wrap);
++		else
++			OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, wrap);
++		break;
++
++#ifdef BCMSDIO
++	case SPI_BUS:
++	case SDIO_BUS:
++		sii->curmap = regs = (void *)((uintptr)addr);
++		if (use_wrap2)
++			sii->curwrap = (void *)((uintptr)wrap2);
++		else
++			sii->curwrap = (void *)((uintptr)wrap);
++		break;
++#endif	/* BCMSDIO */
++
++	case PCMCIA_BUS:
++	default:
++		ASSERT(0);
++		regs = NULL;
++		break;
++	}
++
++	sii->curmap = regs;
++	sii->curidx = coreidx;
++
++	return regs;
++}
++
++volatile void *
++ai_setcoreidx(si_t *sih, uint coreidx)
++{
++	return _ai_setcoreidx(sih, coreidx, 0);
++}
++
++volatile void *
++ai_setcoreidx_2ndwrap(si_t *sih, uint coreidx)
++{
++	return _ai_setcoreidx(sih, coreidx, 1);
++}
++
++void
++ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	chipcregs_t *cc = NULL;
++	uint32 erombase, *eromptr, *eromlim;
++	uint i, j, cidx;
++	uint32 cia, cib, nmp, nsp;
++	uint32 asd, addrl, addrh, sizel, sizeh;
++
++	for (i = 0; i < sii->numcores; i++) {
++		if (cores_info->coreid[i] == CC_CORE_ID) {
++			cc = (chipcregs_t *)cores_info->regs[i];
++			break;
++		}
++	}
++	if (cc == NULL)
++		goto error;
++
++	erombase = R_REG(sii->osh, &cc->eromptr);
++	eromptr = (uint32 *)REG_MAP(erombase, SI_CORE_SIZE);
++	eromlim = eromptr + (ER_REMAPCONTROL / sizeof(uint32));
++
++	cidx = sii->curidx;
++	cia = cores_info->cia[cidx];
++	cib = cores_info->cib[cidx];
++
++	nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
++	nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
++
++	/* scan for cores */
++	while (eromptr < eromlim) {
++		if ((get_erom_ent(sih, &eromptr, ER_TAG, ER_CI) == cia) &&
++			(get_erom_ent(sih, &eromptr, 0, 0) == cib)) {
++			break;
++		}
++	}
++
++	/* skip master ports */
++	for (i = 0; i < nmp; i++)
++		get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
++
++	/* Skip ASDs in port 0 */
++	asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh, &sizel, &sizeh);
++	if (asd == 0) {
++		/* Try again to see if it is a bridge */
++		asd = get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl, &addrh,
++		              &sizel, &sizeh);
++	}
++
++	j = 1;
++	do {
++		asd = get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl, &addrh,
++		              &sizel, &sizeh);
++		j++;
++	} while (asd != 0);
++
++	/* Go through the ASDs for other slave ports */
++	for (i = 1; i < nsp; i++) {
++		j = 0;
++		do {
++			asd = get_asd(sih, &eromptr, i, j, AD_ST_SLAVE, &addrl, &addrh,
++				&sizel, &sizeh);
++			if (asd == 0)
++				break;
++
++			if (!asidx--) {
++				*addr = addrl;
++				*size = sizel;
++				return;
++			}
++			j++;
++		} while (1);
++
++		if (j == 0) {
++			SI_ERROR((" SP %d has no address descriptors\n", i));
++			break;
++		}
++	}
++
++error:
++	*size = 0;
++	return;
++}
++
++/* Return the number of address spaces in current core */
++int
++ai_numaddrspaces(si_t *sih)
++{
++
++	BCM_REFERENCE(sih);
++
++	return 2;
++}
++
++/* Return the address of the nth address space in the current core */
++uint32
++ai_addrspace(si_t *sih, uint asidx)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint cidx;
++
++	cidx = sii->curidx;
++
++	if (asidx == 0)
++		return cores_info->coresba[cidx];
++	else if (asidx == 1)
++		return cores_info->coresba2[cidx];
++	else {
++		SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n",
++		          __FUNCTION__, asidx));
++		return 0;
++	}
++}
++
++/* Return the size of the nth address space in the current core */
++uint32
++ai_addrspacesize(si_t *sih, uint asidx)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint cidx;
++
++	cidx = sii->curidx;
++
++	if (asidx == 0)
++		return cores_info->coresba_size[cidx];
++	else if (asidx == 1)
++		return cores_info->coresba2_size[cidx];
++	else {
++		SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n",
++		          __FUNCTION__, asidx));
++		return 0;
++	}
++}
++
++uint
++ai_flag(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++
++	if (BCM5357_DMP()) {
++		SI_ERROR(("%s: Attempting to read USB20H DMP registers on 5357b0\n", __FUNCTION__));
++		return sii->curidx;
++	}
++	if (BCM4707_DMP()) {
++		SI_ERROR(("%s: Attempting to read CHIPCOMMONB DMP registers on 4707\n",
++			__FUNCTION__));
++		return sii->curidx;
++	}
++	if (BCM53573_DMP()) {
++		SI_ERROR(("%s: Attempting to read DMP registers on 53573\n", __FUNCTION__));
++		return sii->curidx;
++	}
++#ifdef REROUTE_OOBINT
++	if (PMU_DMP()) {
++		SI_ERROR(("%s: Attempting to read PMU DMP registers\n",
++			__FUNCTION__));
++		return PMU_OOB_BIT;
++	}
++#else
++	if (PMU_DMP()) {
++		uint idx, flag;
++		idx = sii->curidx;
++		ai_setcoreidx(sih, SI_CC_IDX);
++		flag = ai_flag_alt(sih);
++		ai_setcoreidx(sih, idx);
++		return flag;
++	}
++#endif /* REROUTE_OOBINT */
++
++	ai = sii->curwrap;
++	ASSERT(ai != NULL);
++
++	return (R_REG(sii->osh, &ai->oobselouta30) & 0x1f);
++}
++
++uint
++ai_flag_alt(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++
++	if (BCM5357_DMP()) {
++		SI_ERROR(("%s: Attempting to read USB20H DMP registers on 5357b0\n", __FUNCTION__));
++		return sii->curidx;
++	}
++	if (BCM4707_DMP()) {
++		SI_ERROR(("%s: Attempting to read CHIPCOMMONB DMP registers on 4707\n",
++			__FUNCTION__));
++		return sii->curidx;
++	}
++#ifdef REROUTE_OOBINT
++	if (PMU_DMP()) {
++		SI_ERROR(("%s: Attempting to read PMU DMP registers\n",
++			__FUNCTION__));
++		return PMU_OOB_BIT;
++	}
++#endif /* REROUTE_OOBINT */
++
++	ai = sii->curwrap;
++
++	return ((R_REG(sii->osh, &ai->oobselouta30) >> AI_OOBSEL_1_SHIFT) & AI_OOBSEL_MASK);
++}
++
++void
++ai_setint(si_t *sih, int siflag)
++{
++	BCM_REFERENCE(sih);
++	BCM_REFERENCE(siflag);
++
++}
++
++uint
++ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint32 *map = (uint32 *) sii->curwrap;
++
++	if (mask || val) {
++		uint32 w = R_REG(sii->osh, map+(offset/4));
++		w &= ~mask;
++		w |= val;
++		W_REG(sii->osh, map+(offset/4), w);
++	}
++
++	return (R_REG(sii->osh, map+(offset/4)));
++}
++
++uint
++ai_corevendor(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint32 cia;
++
++	cia = cores_info->cia[sii->curidx];
++	return ((cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT);
++}
++
++uint
++ai_corerev(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint32 cib;
++
++
++	cib = cores_info->cib[sii->curidx];
++	return remap_corerev(sih, (cib & CIB_REV_MASK) >> CIB_REV_SHIFT);
++}
++
++bool
++ai_iscoreup(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++
++	ai = sii->curwrap;
++
++	return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) == SICF_CLOCK_EN) &&
++	        ((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
++}
++
++/*
++ * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
++ * switch back to the original core, and return the new value.
++ *
++ * When using the silicon backplane, no fiddling with interrupts or core switches is needed.
++ *
++ * Also, when using pci/pcie, we can optimize away the core switching for pci registers
++ * and (on newer pci cores) chipcommon registers.
++ */
++uint
++ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
++{
++	uint origidx = 0;
++	volatile uint32 *r = NULL;
++	uint w;
++	uint intr_val = 0;
++	bool fast = FALSE;
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++
++	ASSERT(GOODIDX(coreidx));
++	ASSERT(regoff < SI_CORE_SIZE);
++	ASSERT((val & ~mask) == 0);
++
++	if (coreidx >= SI_MAXCORES)
++		return 0;
++
++	if (BUSTYPE(sih->bustype) == SI_BUS) {
++		/* If internal bus, we can always get at everything */
++		fast = TRUE;
++		/* map if does not exist */
++		if (!cores_info->regs[coreidx]) {
++			cores_info->regs[coreidx] = REG_MAP(cores_info->coresba[coreidx],
++			                            SI_CORE_SIZE);
++			ASSERT(GOODREGS(cores_info->regs[coreidx]));
++		}
++		r = (volatile uint32 *)((volatile uchar *)cores_info->regs[coreidx] + regoff);
++	} else if (BUSTYPE(sih->bustype) == PCI_BUS) {
++		/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
++
++		if ((cores_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
++			/* Chipc registers are mapped at 12KB */
++
++			fast = TRUE;
++			r = (volatile uint32 *)((volatile char *)sii->curmap +
++			               PCI_16KB0_CCREGS_OFFSET + regoff);
++		} else if (sii->pub.buscoreidx == coreidx) {
++			/* pci registers are at either in the last 2KB of an 8KB window
++			 * or, in pcie and pci rev 13 at 8KB
++			 */
++			fast = TRUE;
++			if (SI_FAST(sii))
++				r = (volatile uint32 *)((volatile char *)sii->curmap +
++				               PCI_16KB0_PCIREGS_OFFSET + regoff);
++			else
++				r = (volatile uint32 *)((volatile char *)sii->curmap +
++				               ((regoff >= SBCONFIGOFF) ?
++				                PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
++				               regoff);
++		}
++	}
++
++	if (!fast) {
++		INTR_OFF(sii, intr_val);
++
++		/* save current core index */
++		origidx = si_coreidx(&sii->pub);
++
++		/* switch core */
++		r = (volatile uint32*) ((volatile uchar*) ai_setcoreidx(&sii->pub, coreidx) +
++		               regoff);
++	}
++	ASSERT(r != NULL);
++
++	/* mask and set */
++	if (mask || val) {
++		w = (R_REG(sii->osh, r) & ~mask) | val;
++		W_REG(sii->osh, r, w);
++	}
++
++	/* readback */
++	w = R_REG(sii->osh, r);
++
++	if (!fast) {
++		/* restore core index */
++		if (origidx != coreidx)
++			ai_setcoreidx(&sii->pub, origidx);
++
++		INTR_RESTORE(sii, intr_val);
++	}
++
++	return (w);
++}
++
++/*
++ * If there is no need for fiddling with interrupts or core switches (typically silicon
++ * back plane registers, pci registers and chipcommon registers), this function
++ * returns the register offset on this core to a mapped address. This address can
++ * be used for W_REG/R_REG directly.
++ *
++ * For accessing registers that would need a core switch, this function will return
++ * NULL.
++ */
++volatile uint32 *
++ai_corereg_addr(si_t *sih, uint coreidx, uint regoff)
++{
++	volatile uint32 *r = NULL;
++	bool fast = FALSE;
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++
++	ASSERT(GOODIDX(coreidx));
++	ASSERT(regoff < SI_CORE_SIZE);
++
++	if (coreidx >= SI_MAXCORES)
++		return 0;
++
++	if (BUSTYPE(sih->bustype) == SI_BUS) {
++		/* If internal bus, we can always get at everything */
++		fast = TRUE;
++		/* map if does not exist */
++		if (!cores_info->regs[coreidx]) {
++			cores_info->regs[coreidx] = REG_MAP(cores_info->coresba[coreidx],
++			                            SI_CORE_SIZE);
++			ASSERT(GOODREGS(cores_info->regs[coreidx]));
++		}
++		r = (volatile uint32 *)((volatile uchar *)cores_info->regs[coreidx] + regoff);
++	} else if (BUSTYPE(sih->bustype) == PCI_BUS) {
++		/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
++
++		if ((cores_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
++			/* Chipc registers are mapped at 12KB */
++
++			fast = TRUE;
++			r = (volatile uint32 *)((volatile char *)sii->curmap +
++			               PCI_16KB0_CCREGS_OFFSET + regoff);
++		} else if (sii->pub.buscoreidx == coreidx) {
++			/* pci registers are at either in the last 2KB of an 8KB window
++			 * or, in pcie and pci rev 13 at 8KB
++			 */
++			fast = TRUE;
++			if (SI_FAST(sii))
++				r = (volatile uint32 *)((volatile char *)sii->curmap +
++				               PCI_16KB0_PCIREGS_OFFSET + regoff);
++			else
++				r = (volatile uint32 *)((volatile char *)sii->curmap +
++				               ((regoff >= SBCONFIGOFF) ?
++				                PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
++				               regoff);
++		}
++	}
++
++	if (!fast) {
++		ASSERT(sii->curidx == coreidx);
++		r = (volatile uint32*) ((volatile uchar*)sii->curmap + regoff);
++	}
++
++	return (r);
++}
++
++void
++ai_core_disable(si_t *sih, uint32 bits)
++{
++	si_info_t *sii = SI_INFO(sih);
++	volatile uint32 dummy;
++	uint32 status;
++	aidmp_t *ai;
++
++
++	ASSERT(GOODREGS(sii->curwrap));
++	ai = sii->curwrap;
++
++	/* if core is already in reset, just return */
++	if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) {
++		return;
++	}
++
++	/* ensure there are no pending backplane operations */
++	SPINWAIT(((status = R_REG(sii->osh, &ai->resetstatus)) != 0), 300);
++
++	/* if pending backplane ops still, try waiting longer */
++	if (status != 0) {
++		/* 300usecs was sufficient to allow backplane ops to clear for big hammer */
++		/* during driver load we may need more time */
++		SPINWAIT(((status = R_REG(sii->osh, &ai->resetstatus)) != 0), 10000);
++		/* if still pending ops, continue on and try disable anyway */
++		/* this is in big hammer path, so don't call wl_reinit in this case... */
++	}
++
++	W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
++	dummy = R_REG(sii->osh, &ai->resetctrl);
++	BCM_REFERENCE(dummy);
++	OSL_DELAY(1);
++
++	W_REG(sii->osh, &ai->ioctrl, bits);
++	dummy = R_REG(sii->osh, &ai->ioctrl);
++	BCM_REFERENCE(dummy);
++	OSL_DELAY(10);
++}
++
++/* reset and re-enable a core
++ * inputs:
++ * bits - core specific bits that are set during and after reset sequence
++ * resetbits - core specific bits that are set only during reset sequence
++ */
++static void
++_ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
++{
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++	volatile uint32 dummy;
++	uint loop_counter = 10;
++
++	ASSERT(GOODREGS(sii->curwrap));
++	ai = sii->curwrap;
++
++	/* if core is already out of reset, just return */
++
++	/* ensure there are no pending backplane operations */
++	SPINWAIT(((dummy = R_REG(sii->osh, &ai->resetstatus)) != 0), 300);
++
++
++	/* put core into reset state */
++	W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
++	OSL_DELAY(10);
++
++	/* ensure there are no pending backplane operations */
++	SPINWAIT((R_REG(sii->osh, &ai->resetstatus) != 0), 300);
++
++	W_REG(sii->osh, &ai->ioctrl, (bits | resetbits | SICF_FGC | SICF_CLOCK_EN));
++	dummy = R_REG(sii->osh, &ai->ioctrl);
++	BCM_REFERENCE(dummy);
++
++	/* ensure there are no pending backplane operations */
++	SPINWAIT(((dummy = R_REG(sii->osh, &ai->resetstatus)) != 0), 300);
++
++
++	while (R_REG(sii->osh, &ai->resetctrl) != 0 && --loop_counter != 0) {
++		/* ensure there are no pending backplane operations */
++		SPINWAIT(((dummy = R_REG(sii->osh, &ai->resetstatus)) != 0), 300);
++
++
++		/* take core out of reset */
++		W_REG(sii->osh, &ai->resetctrl, 0);
++
++		/* ensure there are no pending backplane operations */
++		SPINWAIT((R_REG(sii->osh, &ai->resetstatus) != 0), 300);
++	}
++
++
++	W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN));
++	dummy = R_REG(sii->osh, &ai->ioctrl);
++	BCM_REFERENCE(dummy);
++	OSL_DELAY(1);
++}
++
++void
++ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint idx = sii->curidx;
++
++	if (cores_info->wrapba2[idx] != 0) {
++		ai_setcoreidx_2ndwrap(sih, idx);
++		_ai_core_reset(sih, bits, resetbits);
++		ai_setcoreidx(sih, idx);
++	}
++
++	_ai_core_reset(sih, bits, resetbits);
++}
++
++void
++ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)
++{
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++	uint32 w;
++
++	if (BCM5357_DMP()) {
++		SI_ERROR(("%s: Accessing USB20H DMP register (ioctrl) on 5357\n",
++		          __FUNCTION__));
++		return;
++	}
++	if (BCM4707_DMP()) {
++		SI_ERROR(("%s: Accessing CHIPCOMMONB DMP register (ioctrl) on 4707\n",
++			__FUNCTION__));
++		return;
++	}
++	if (PMU_DMP()) {
++		SI_ERROR(("%s: Accessing PMU DMP register (ioctrl)\n",
++			__FUNCTION__));
++		return;
++	}
++
++	ASSERT(GOODREGS(sii->curwrap));
++	ai = sii->curwrap;
++
++	ASSERT((val & ~mask) == 0);
++
++	if (mask || val) {
++		w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
++		W_REG(sii->osh, &ai->ioctrl, w);
++	}
++}
++
++uint32
++ai_core_cflags(si_t *sih, uint32 mask, uint32 val)
++{
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++	uint32 w;
++
++	if (BCM5357_DMP()) {
++		SI_ERROR(("%s: Accessing USB20H DMP register (ioctrl) on 5357\n",
++		          __FUNCTION__));
++		return 0;
++	}
++	if (BCM4707_DMP()) {
++		SI_ERROR(("%s: Accessing CHIPCOMMONB DMP register (ioctrl) on 4707\n",
++			__FUNCTION__));
++		return 0;
++	}
++
++	if (PMU_DMP()) {
++		SI_ERROR(("%s: Accessing PMU DMP register (ioctrl)\n",
++			__FUNCTION__));
++		return 0;
++	}
++	ASSERT(GOODREGS(sii->curwrap));
++	ai = sii->curwrap;
++
++	ASSERT((val & ~mask) == 0);
++
++	if (mask || val) {
++		w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
++		W_REG(sii->osh, &ai->ioctrl, w);
++	}
++
++	return R_REG(sii->osh, &ai->ioctrl);
++}
++
++uint32
++ai_core_sflags(si_t *sih, uint32 mask, uint32 val)
++{
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++	uint32 w;
++
++	if (BCM5357_DMP()) {
++		SI_ERROR(("%s: Accessing USB20H DMP register (iostatus) on 5357\n",
++		          __FUNCTION__));
++		return 0;
++	}
++	if (BCM4707_DMP()) {
++		SI_ERROR(("%s: Accessing CHIPCOMMONB DMP register (ioctrl) on 4707\n",
++			__FUNCTION__));
++		return 0;
++	}
++	if (PMU_DMP()) {
++		SI_ERROR(("%s: Accessing PMU DMP register (ioctrl)\n",
++			__FUNCTION__));
++		return 0;
++	}
++
++	ASSERT(GOODREGS(sii->curwrap));
++	ai = sii->curwrap;
++
++	ASSERT((val & ~mask) == 0);
++	ASSERT((mask & ~SISF_CORE_BITS) == 0);
++
++	if (mask || val) {
++		w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) | val);
++		W_REG(sii->osh, &ai->iostatus, w);
++	}
++
++	return R_REG(sii->osh, &ai->iostatus);
++}
++
++#if defined(BCMDBG_PHYDUMP)
++/* print interesting aidmp registers */
++void
++ai_dumpregs(si_t *sih, struct bcmstrbuf *b)
++{
++	si_info_t *sii = SI_INFO(sih);
++	osl_t *osh;
++	aidmp_t *ai;
++	uint i;
++	uint32 prev_value = 0;
++	axi_wrapper_t * axi_wrapper = sii->axi_wrapper;
++	uint32 cfg_reg = 0;
++	uint bar0_win_offset = 0;
++
++	osh = sii->osh;
++
++
++	/* Save and restore wrapper access window */
++	if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
++		if (PCIE_GEN2(sii)) {
++			cfg_reg = PCIE2_BAR0_CORE2_WIN2;
++			bar0_win_offset = PCIE2_BAR0_CORE2_WIN2_OFFSET;
++		} else {
++			cfg_reg = PCI_BAR0_WIN2;
++			bar0_win_offset = PCI_BAR0_WIN2_OFFSET;
++		}
++
++		prev_value = OSL_PCI_READ_CONFIG(osh, cfg_reg, 4);
++
++		if (prev_value == ID32_INVALID) {
++			SI_PRINT(("%s, PCI_BAR0_WIN2 - %x\n", __FUNCTION__, prev_value));
++			return;
++		}
++	}
++
++	bcm_bprintf(b, "ChipNum:%x, ChipRev;%x, BusType:%x, BoardType:%x, BoardVendor:%x\n\n",
++		sih->chip, sih->chiprev, sih->bustype, sih->boardtype, sih->boardvendor);
++
++	for (i = 0; i < sii->axi_num_wrappers; i++) {
++
++		if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
++			/* Set BAR0 window to bridge wapper base address */
++			OSL_PCI_WRITE_CONFIG(osh,
++				cfg_reg, 4, axi_wrapper[i].wrapper_addr);
++
++			ai = (aidmp_t *) ((volatile uint8*)sii->curmap + bar0_win_offset);
++		} else {
++			ai = (aidmp_t *)(uintptr) axi_wrapper[i].wrapper_addr;
++		}
++
++		bcm_bprintf(b, "core 0x%x: core_rev:%d, %s_WR ADDR:%x \n", axi_wrapper[i].cid,
++			axi_wrapper[i].rev,
++			axi_wrapper[i].wrapper_type == AI_SLAVE_WRAPPER ? "SLAVE" : "MASTER",
++			axi_wrapper[i].wrapper_addr);
++
++		/* BCM5357_DMP() */
++		if (((CHIPID(sih->chip) == BCM5357_CHIP_ID) ||
++			(CHIPID(sih->chip) == BCM4749_CHIP_ID)) &&
++			(sih->chippkg == BCM5357_PKG_ID) &&
++			(axi_wrapper[i].cid == USB20H_CORE_ID)) {
++			bcm_bprintf(b, "Skipping usb20h in 5357\n");
++			continue;
++		}
++
++		/* BCM4707_DMP() */
++		if (BCM4707_CHIP(CHIPID(sih->chip)) &&
++			(axi_wrapper[i].cid == NS_CCB_CORE_ID)) {
++			bcm_bprintf(b, "Skipping chipcommonb in 4707\n");
++			continue;
++		}
++
++		bcm_bprintf(b, "ioctrlset 0x%x ioctrlclear 0x%x ioctrl 0x%x iostatus 0x%x "
++			    "ioctrlwidth 0x%x iostatuswidth 0x%x\n"
++			    "resetctrl 0x%x resetstatus 0x%x resetreadid 0x%x resetwriteid 0x%x\n"
++			    "errlogctrl 0x%x errlogdone 0x%x errlogstatus 0x%x "
++			    "errlogaddrlo 0x%x errlogaddrhi 0x%x\n"
++			    "errlogid 0x%x errloguser 0x%x errlogflags 0x%x\n"
++			    "intstatus 0x%x config 0x%x itcr 0x%x\n\n",
++			    R_REG(osh, &ai->ioctrlset),
++			    R_REG(osh, &ai->ioctrlclear),
++			    R_REG(osh, &ai->ioctrl),
++			    R_REG(osh, &ai->iostatus),
++			    R_REG(osh, &ai->ioctrlwidth),
++			    R_REG(osh, &ai->iostatuswidth),
++			    R_REG(osh, &ai->resetctrl),
++			    R_REG(osh, &ai->resetstatus),
++			    R_REG(osh, &ai->resetreadid),
++			    R_REG(osh, &ai->resetwriteid),
++			    R_REG(osh, &ai->errlogctrl),
++			    R_REG(osh, &ai->errlogdone),
++			    R_REG(osh, &ai->errlogstatus),
++			    R_REG(osh, &ai->errlogaddrlo),
++			    R_REG(osh, &ai->errlogaddrhi),
++			    R_REG(osh, &ai->errlogid),
++			    R_REG(osh, &ai->errloguser),
++			    R_REG(osh, &ai->errlogflags),
++			    R_REG(osh, &ai->intstatus),
++			    R_REG(osh, &ai->config),
++			    R_REG(osh, &ai->itcr));
++	}
++
++	/* Restore the initial wrapper space */
++	if (prev_value && cfg_reg) {
++		OSL_PCI_WRITE_CONFIG(osh, cfg_reg, 4, prev_value);
++	}
++
++}
++#endif	
++
++
++void
++ai_enable_backplane_timeouts(si_t *sih)
++{
++#if defined(AXI_TIMEOUTS) || defined(BCM_BACKPLANE_TIMEOUT)
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++	uint32 i;
++	axi_wrapper_t * axi_wrapper = sii->axi_wrapper;
++
++#ifdef BCM_BACKPLANE_TIMEOUT
++	uint32 prev_value = 0;
++	osl_t *osh = sii->osh;
++	uint32 cfg_reg = 0;
++	uint32 offset = 0;
++#endif /* BCM_BACKPLANE_TIMEOUT */
++
++	if ((sii->axi_num_wrappers == 0) ||
++#ifdef BCM_BACKPLANE_TIMEOUT
++		(!PCIE(sii)) ||
++#endif /* BCM_BACKPLANE_TIMEOUT */
++		FALSE) {
++		SI_VMSG((" %s, axi_num_wrappers:%d, Is_PCIE:%d, BUS_TYPE:%d, ID:%x\n",
++			__FUNCTION__, sii->axi_num_wrappers, PCIE(sii),
++			BUSTYPE(sii->pub.bustype), sii->pub.buscoretype));
++		return;
++	}
++
++#ifdef BCM_BACKPLANE_TIMEOUT
++	/* Save and restore the wrapper access window */
++	if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
++		if (PCIE_GEN1(sii)) {
++			cfg_reg = PCI_BAR0_WIN2;
++			offset = PCI_BAR0_WIN2_OFFSET;
++		} else if (PCIE_GEN2(sii)) {
++			cfg_reg = PCIE2_BAR0_CORE2_WIN2;
++			offset = PCIE2_BAR0_CORE2_WIN2_OFFSET;
++		}
++		else {
++			osl_panic("!PCIE_GEN1 && !PCIE_GEN2\n");
++		}
++
++		prev_value = OSL_PCI_READ_CONFIG(osh, cfg_reg, 4);
++		if (prev_value == ID32_INVALID) {
++			SI_PRINT(("%s, PCI_BAR0_WIN2 - %x\n", __FUNCTION__, prev_value));
++			return;
++		}
++	}
++
++#endif /* BCM_BACKPLANE_TIMEOUT */
++
++	for (i = 0; i < sii->axi_num_wrappers; ++i) {
++
++		if (axi_wrapper[i].wrapper_type != AI_SLAVE_WRAPPER) {
++			SI_VMSG(("SKIP ENABLE BPT: MFG:%x, CID:%x, ADDR:%x\n",
++				axi_wrapper[i].mfg,
++				axi_wrapper[i].cid,
++				axi_wrapper[i].wrapper_addr));
++			continue;
++		}
++
++#ifdef BCM_BACKPLANE_TIMEOUT
++		if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
++			/* Set BAR0_CORE2_WIN2 to wapper base address */
++			OSL_PCI_WRITE_CONFIG(osh,
++				cfg_reg, 4, axi_wrapper[i].wrapper_addr);
++
++			/* set AI to BAR0 + Offset corresponding to Gen1 or gen2 */
++			ai = (aidmp_t *) ((uint8*)sii->curmap + offset);
++		}
++		else
++#endif /* BCM_BACKPLANE_TIMEOUT */
++		{
++			ai = (aidmp_t *)(uintptr) axi_wrapper[i].wrapper_addr;
++		}
++
++		W_REG(sii->osh, &ai->errlogctrl, (1 << AIELC_TO_ENAB_SHIFT) |
++		      ((AXI_TO_VAL << AIELC_TO_EXP_SHIFT) & AIELC_TO_EXP_MASK));
++
++		SI_VMSG(("ENABLED BPT: MFG:%x, CID:%x, ADDR:%x, ERR_CTRL:%x\n",
++			axi_wrapper[i].mfg,
++			axi_wrapper[i].cid,
++			axi_wrapper[i].wrapper_addr,
++			R_REG(sii->osh, &ai->errlogctrl)));
++	}
++
++#ifdef BCM_BACKPLANE_TIMEOUT
++	/* Restore the initial wrapper space */
++	if (prev_value) {
++		OSL_PCI_WRITE_CONFIG(osh, cfg_reg, 4, prev_value);
++	}
++#endif /* BCM_BACKPLANE_TIMEOUT */
++
++#endif /* AXI_TIMEOUTS || BCM_BACKPLANE_TIMEOUT */
++}
++
++#if defined(AXI_TIMEOUTS) || defined(BCM_BACKPLANE_TIMEOUT)
++
++/* slave error is ignored, so account for those cases */
++static uint32 si_ignore_errlog_cnt = 0;
++
++static bool
++ai_ignore_errlog(si_info_t *sii, uint32 lo_addr, uint32 hi_addr, uint32 err_axi_id, uint32 errsts)
++{
++	uint32 axi_id;
++
++	/* ignore the BT slave errors if the errlog is to chipcommon addr 0x190 */
++	switch (CHIPID(sii->pub.chip)) {
++		case BCM4350_CHIP_ID:
++			axi_id = BCM4350_BT_AXI_ID;
++			break;
++		case BCM4345_CHIP_ID:
++			axi_id = BCM4345_BT_AXI_ID;
++			break;
++		default:
++			return FALSE;
++	}
++
++	/* AXI ID check */
++	if ((err_axi_id & AI_ERRLOGID_AXI_ID_MASK) != axi_id)
++		return FALSE;
++
++	/* slave errors */
++	if ((errsts & AIELS_TIMEOUT_MASK) != AIELS_SLAVE_ERR)
++		return FALSE;
++
++	/* chipc reg 0x190 */
++	if ((hi_addr != BT_CC_SPROM_BADREG_HI) || (lo_addr != BT_CC_SPROM_BADREG_LO))
++		return FALSE;
++
++	return TRUE;
++}
++#endif /* defined (AXI_TIMEOUTS) || defined (BCM_BACKPLANE_TIMEOUT) */
++
++#ifdef BCM_BACKPLANE_TIMEOUT
++
++/* Function to return the APB bridge details corresponding to the core */
++bool
++ai_get_apb_bridge(si_t * sih, uint32 coreidx, uint32 *apb_id, uint32 * apb_coreuinit)
++{
++	uint i;
++	uint32 core_base, core_end;
++	si_info_t *sii = SI_INFO(sih);
++	static uint32 coreidx_cached = 0, apb_id_cached = 0, apb_coreunit_cached = 0;
++	uint32 tmp_coreunit = 0;
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	if (coreidx >= MIN(sii->numcores, SI_MAXCORES))
++		return FALSE;
++
++	/* Most of the time apb bridge query will be for d11 core.
++	 * Maintain the last cache and return if found rather than iterating the table
++	 */
++	if (coreidx_cached == coreidx) {
++		*apb_id = apb_id_cached;
++		*apb_coreuinit = apb_coreunit_cached;
++		return TRUE;
++	}
++
++	core_base = cores_info->coresba[coreidx];
++	core_end = core_base + cores_info->coresba_size[coreidx];
++
++	for (i = 0; i < sii->numcores; i++) {
++		if (cores_info->coreid[i] == APB_BRIDGE_ID) {
++			uint32 apb_base;
++			uint32 apb_end;
++
++			apb_base = cores_info->coresba[i];
++			apb_end = apb_base + cores_info->coresba_size[i];
++
++			if ((core_base >= apb_base) &&
++				(core_end <= apb_end)) {
++				/* Current core is attached to this APB bridge */
++				*apb_id = apb_id_cached = APB_BRIDGE_ID;
++				*apb_coreuinit = apb_coreunit_cached = tmp_coreunit;
++				coreidx_cached = coreidx;
++				return TRUE;
++			}
++			/* Increment the coreunit */
++			tmp_coreunit++;
++		}
++	}
++
++	return FALSE;
++}
++
++uint32
++ai_clear_backplane_to_fast(si_t *sih, void * addr)
++{
++	si_info_t *sii = SI_INFO(sih);
++	void * curmap = sii->curmap;
++	bool core_reg = FALSE;
++
++	/* Use fast path only for core register access */
++	if ((addr >= curmap) && (addr < (curmap + SI_CORE_SIZE))) {
++		/* address being accessed is within current core reg map */
++		core_reg = TRUE;
++	}
++
++	if (core_reg) {
++		uint32 apb_id, apb_coreuinit;
++
++		if (ai_get_apb_bridge(sih, si_coreidx(&sii->pub),
++			&apb_id, &apb_coreuinit) == TRUE) {
++			/* Found the APB bridge corresponding to current core,
++			 * Check for bus errors in APB wrapper
++			 */
++			return ai_clear_backplane_to_per_core(sih,
++				apb_id, apb_coreuinit, NULL);
++		}
++	}
++
++	/* Default is to poll for errors on all slave wrappers */
++	return si_clear_backplane_to(sih);
++}
++#endif /* BCM_BACKPLANE_TIMEOUT */
++
++#if defined(AXI_TIMEOUTS) || defined(BCM_BACKPLANE_TIMEOUT)
++/*
++ * API to clear the back plane timeout per core.
++ * Caller may passs optional wrapper address. If present this will be used as
++ * the wrapper base address. If wrapper base address is provided then caller
++ * must provide the coreid also.
++ * If both coreid and wrapper is zero, then err status of current bridge
++ * will be verified.
++ */
++uint32
++ai_clear_backplane_to_per_core(si_t *sih, uint coreid, uint coreunit, void * wrap)
++{
++	int ret = AXI_WRAP_STS_NONE;
++	aidmp_t *ai = NULL;
++	uint32 errlog_status = 0;
++	si_info_t *sii = SI_INFO(sih);
++	uint32 errlog_lo = 0, errlog_hi = 0, errlog_id = 0, errlog_flags = 0;
++	uint32 current_coreidx = si_coreidx(sih);
++	uint32 target_coreidx = si_findcoreidx(sih, coreid, coreunit);
++
++#if defined(BCM_BACKPLANE_TIMEOUT)
++	si_axi_error_t * axi_error = &sih->err_info->axi_error[sih->err_info->count];
++#endif /* BCM_BACKPLANE_TIMEOUT */
++	bool restore_core = FALSE;
++
++	if ((sii->axi_num_wrappers == 0) ||
++#ifdef BCM_BACKPLANE_TIMEOUT
++		(!PCIE(sii)) ||
++#endif /* BCM_BACKPLANE_TIMEOUT */
++		FALSE) {
++		SI_VMSG((" %s, axi_num_wrappers:%d, Is_PCIE:%d, BUS_TYPE:%d, ID:%x\n",
++			__FUNCTION__, sii->axi_num_wrappers, PCIE(sii),
++			BUSTYPE(sii->pub.bustype), sii->pub.buscoretype));
++		return AXI_WRAP_STS_NONE;
++	}
++
++	if (wrap != NULL) {
++		ai = (aidmp_t *)wrap;
++	} else if (coreid && (target_coreidx != current_coreidx)) {
++
++		if (ai_setcoreidx(sih, target_coreidx) == NULL) {
++			/* Unable to set the core */
++			SI_PRINT(("Set Code Failed: coreid:%x, unit:%d, target_coreidx:%d\n",
++				coreid, coreunit, target_coreidx));
++			errlog_lo = target_coreidx;
++			ret = AXI_WRAP_STS_SET_CORE_FAIL;
++			goto end;
++		}
++
++		restore_core = TRUE;
++		ai = (aidmp_t *)si_wrapperregs(sih);
++	} else {
++		/* Read error status of current wrapper */
++		ai = (aidmp_t *)si_wrapperregs(sih);
++
++		/* Update CoreID to current Code ID */
++		coreid = si_coreid(sih);
++	}
++
++	/* read error log status */
++	errlog_status = R_REG(sii->osh, &ai->errlogstatus);
++
++	if (errlog_status == ID32_INVALID) {
++		/* Do not try to peek further */
++		SI_PRINT(("%s, errlogstatus:%x - Slave Wrapper:%x\n",
++			__FUNCTION__, errlog_status, coreid));
++		ret = AXI_WRAP_STS_WRAP_RD_ERR;
++		errlog_lo = (uint32)&ai->errlogstatus;
++		goto end;
++	}
++
++	if ((errlog_status & AIELS_TIMEOUT_MASK) != 0) {
++		uint32 tmp;
++		uint32 count = 0;
++		/* set ErrDone to clear the condition */
++		W_REG(sii->osh, &ai->errlogdone, AIELD_ERRDONE_MASK);
++
++		/* SPINWAIT on errlogstatus timeout status bits */
++		while ((tmp = R_REG(sii->osh, &ai->errlogstatus)) & AIELS_TIMEOUT_MASK) {
++
++			if (tmp == ID32_INVALID) {
++				SI_PRINT(("%s: prev errlogstatus:%x, errlogstatus:%x\n",
++					__FUNCTION__, errlog_status, tmp));
++				ret = AXI_WRAP_STS_WRAP_RD_ERR;
++				errlog_lo = (uint32)&ai->errlogstatus;
++				goto end;
++			}
++			/*
++			 * Clear again, to avoid getting stuck in the loop, if a new error
++			 * is logged after we cleared the first timeout
++			 */
++			W_REG(sii->osh, &ai->errlogdone, AIELD_ERRDONE_MASK);
++
++			count++;
++			OSL_DELAY(10);
++			if ((10 * count) > AI_REG_READ_TIMEOUT) {
++				errlog_status = tmp;
++				break;
++			}
++		}
++
++		errlog_lo = R_REG(sii->osh, &ai->errlogaddrlo);
++		errlog_hi = R_REG(sii->osh, &ai->errlogaddrhi);
++		errlog_id = R_REG(sii->osh, &ai->errlogid);
++		errlog_flags = R_REG(sii->osh, &ai->errlogflags);
++
++		/* we are already in the error path, so OK to check for the  slave error */
++		if (ai_ignore_errlog(sii, errlog_lo, errlog_hi, errlog_id,
++			errlog_status)) {
++			si_ignore_errlog_cnt++;
++			goto end;
++		}
++
++		/* only reset APB Bridge on timeout (not slave error, or dec error) */
++		switch (errlog_status & AIELS_TIMEOUT_MASK) {
++			case AIELS_SLAVE_ERR:
++				SI_PRINT(("AXI slave error"));
++				ret = AXI_WRAP_STS_SLAVE_ERR;
++				break;
++
++			case AIELS_TIMEOUT:
++				/* reset APB Bridge */
++				OR_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
++				/* sync write */
++				(void)R_REG(sii->osh, &ai->resetctrl);
++				/* clear Reset bit */
++				AND_REG(sii->osh, &ai->resetctrl, ~(AIRC_RESET));
++				/* sync write */
++				(void)R_REG(sii->osh, &ai->resetctrl);
++				SI_PRINT(("AXI timeout"));
++				ret = AXI_WRAP_STS_TIMEOUT;
++				break;
++
++			case AIELS_DECODE:
++				SI_PRINT(("AXI decode error"));
++				ret = AXI_WRAP_STS_DECODE_ERR;
++				break;
++			default:
++				ASSERT(0);	/* should be impossible */
++		}
++
++		SI_PRINT(("\tCoreID: %x\n", coreid));
++		SI_PRINT(("\t errlog: lo 0x%08x, hi 0x%08x, id 0x%08x, flags 0x%08x"
++			", status 0x%08x\n",
++			errlog_lo, errlog_hi, errlog_id, errlog_flags,
++			errlog_status));
++	}
++
++end:
++
++#if defined(BCM_BACKPLANE_TIMEOUT)
++	if (axi_error && (ret != AXI_WRAP_STS_NONE)) {
++		axi_error->error = ret;
++		axi_error->coreid = coreid;
++		axi_error->errlog_lo = errlog_lo;
++		axi_error->errlog_hi = errlog_hi;
++		axi_error->errlog_id = errlog_id;
++		axi_error->errlog_flags = errlog_flags;
++		axi_error->errlog_status = errlog_status;
++		sih->err_info->count++;
++
++		if (sih->err_info->count == SI_MAX_ERRLOG_SIZE) {
++			sih->err_info->count = SI_MAX_ERRLOG_SIZE - 1;
++			SI_PRINT(("AXI Error log overflow\n"));
++		}
++	}
++#endif /* BCM_BACKPLANE_TIMEOUT */
++
++	if (restore_core) {
++		if (ai_setcoreidx(sih, current_coreidx) == NULL) {
++			/* Unable to set the core */
++			return ID32_INVALID;
++		}
++	}
++
++	return ret;
++}
++#endif /* AXI_TIMEOUTS || BCM_BACKPLANE_TIMEOUT */
++
++/*
++ * This API polls all slave wrappers for errors and returns bit map of
++ * all reported errors.
++ * return - bit map of
++ *	AXI_WRAP_STS_NONE
++ *	AXI_WRAP_STS_TIMEOUT
++ *	AXI_WRAP_STS_SLAVE_ERR
++ *	AXI_WRAP_STS_DECODE_ERR
++ *	AXI_WRAP_STS_PCI_RD_ERR
++ *	AXI_WRAP_STS_WRAP_RD_ERR
++ *	AXI_WRAP_STS_SET_CORE_FAIL
++ * On timeout detection, correspondign bridge will be reset to
++ * unblock the bus.
++ * Error reported in each wrapper can be retrieved using the API
++ * si_get_axi_errlog_info()
++ */
++uint32
++ai_clear_backplane_to(si_t *sih)
++{
++	uint32 ret = 0;
++#if defined(AXI_TIMEOUTS) || defined(BCM_BACKPLANE_TIMEOUT)
++
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++	uint32 i;
++	axi_wrapper_t * axi_wrapper = sii->axi_wrapper;
++
++#ifdef BCM_BACKPLANE_TIMEOUT
++	uint32 prev_value = 0;
++	osl_t *osh = sii->osh;
++	uint32 cfg_reg = 0;
++	uint32 offset = 0;
++
++	if ((sii->axi_num_wrappers == 0) || (!PCIE(sii)))
++#else
++	if (sii->axi_num_wrappers == 0)
++#endif
++	{
++		SI_VMSG((" %s, axi_num_wrappers:%d, Is_PCIE:%d, BUS_TYPE:%d, ID:%x\n",
++			__FUNCTION__, sii->axi_num_wrappers, PCIE(sii),
++			BUSTYPE(sii->pub.bustype), sii->pub.buscoretype));
++		return AXI_WRAP_STS_NONE;
++	}
++
++#ifdef BCM_BACKPLANE_TIMEOUT
++	/* Save and restore wrapper access window */
++	if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
++		if (PCIE_GEN1(sii)) {
++			cfg_reg = PCI_BAR0_WIN2;
++			offset = PCI_BAR0_WIN2_OFFSET;
++		} else if (PCIE_GEN2(sii)) {
++			cfg_reg = PCIE2_BAR0_CORE2_WIN2;
++			offset = PCIE2_BAR0_CORE2_WIN2_OFFSET;
++		}
++		else {
++			osl_panic("!PCIE_GEN1 && !PCIE_GEN2\n");
++		}
++
++		prev_value = OSL_PCI_READ_CONFIG(osh, cfg_reg, 4);
++
++		if (prev_value == ID32_INVALID) {
++			si_axi_error_t * axi_error =
++				&sih->err_info->axi_error[sih->err_info->count];
++			SI_PRINT(("%s, PCI_BAR0_WIN2 - %x\n", __FUNCTION__, prev_value));
++
++			axi_error->error = ret = AXI_WRAP_STS_PCI_RD_ERR;
++			axi_error->errlog_lo = cfg_reg;
++			sih->err_info->count++;
++
++			if (sih->err_info->count == SI_MAX_ERRLOG_SIZE) {
++				sih->err_info->count = SI_MAX_ERRLOG_SIZE - 1;
++				SI_PRINT(("AXI Error log overflow\n"));
++			}
++
++			return ret;
++		}
++	}
++#endif /* BCM_BACKPLANE_TIMEOUT */
++
++	for (i = 0; i < sii->axi_num_wrappers; ++i) {
++		uint32 tmp;
++
++		if (axi_wrapper[i].wrapper_type != AI_SLAVE_WRAPPER) {
++			continue;
++		}
++
++#ifdef BCM_BACKPLANE_TIMEOUT
++
++		if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
++			/* Set BAR0_CORE2_WIN2 to bridge wapper base address */
++			OSL_PCI_WRITE_CONFIG(osh,
++				cfg_reg, 4, axi_wrapper[i].wrapper_addr);
++
++			/* set AI to BAR0 + Offset corresponding to Gen1 or gen2 */
++			ai = (aidmp_t *) ((uint8*)sii->curmap + offset);
++		}
++		else
++#endif /* BCM_BACKPLANE_TIMEOUT */
++		{
++			ai = (aidmp_t *)(uintptr) axi_wrapper[i].wrapper_addr;
++		}
++
++		tmp = ai_clear_backplane_to_per_core(sih, axi_wrapper[i].cid, 0, (void*)ai);
++
++		ret |= tmp;
++	}
++
++#ifdef BCM_BACKPLANE_TIMEOUT
++	/* Restore the initial wrapper space */
++	if (prev_value) {
++		OSL_PCI_WRITE_CONFIG(osh, cfg_reg, 4, prev_value);
++	}
++#endif /* BCM_BACKPLANE_TIMEOUT */
++
++#endif /* AXI_TIMEOUTS || BCM_BACKPLANE_TIMEOUT */
++
++	return ret;
++}
++
++uint
++ai_num_slaveports(si_t *sih, uint coreidx)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint32 cib;
++
++	cib = cores_info->cib[coreidx];
++	return ((cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT);
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/bcm_app_utils.c b/module_drivers/drivers/net/wireless/bcmdhd/bcm_app_utils.c
+new file mode 100644
+index 000000000..a5a7a5b23
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/bcm_app_utils.c
+@@ -0,0 +1,1015 @@
++/*
++ * Misc utility routines used by kernel or app-level.
++ * Contents are wifi-specific, used by any kernel or app-level
++ * software that might want wifi things as it grows.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcm_app_utils.c 623866 2016-03-09 11:58:34Z $
++ */
++
++#include <typedefs.h>
++
++#ifdef BCMDRIVER
++#include <osl.h>
++#define strtoul(nptr, endptr, base) bcm_strtoul((nptr), (endptr), (base))
++#define tolower(c) (bcm_isupper((c)) ? ((c) + 'a' - 'A') : (c))
++#else /* BCMDRIVER */
++#include <stdio.h>
++#include <string.h>
++#include <stdlib.h>
++#include <ctype.h>
++#ifndef ASSERT
++#define ASSERT(exp)
++#endif
++#endif /* BCMDRIVER */
++#include <bcmwifi_channels.h>
++
++#if defined(WIN32) && (defined(BCMDLL) || defined(WLMDLL))
++#include <bcmstdlib.h>	/* For wl/exe/GNUmakefile.brcm_wlu and GNUmakefile.wlm_dll */
++#endif
++
++#include <bcmutils.h>
++#include <wlioctl.h>
++#include <wlioctl_utils.h>
++
++#ifndef BCMDRIVER
++/*	Take an array of measurments representing a single channel over time and return
++	a summary. Currently implemented as a simple average but could easily evolve
++	into more cpomplex alogrithms.
++*/
++cca_congest_channel_req_t *
++cca_per_chan_summary(cca_congest_channel_req_t *input, cca_congest_channel_req_t *avg, bool percent)
++{
++	int sec;
++	cca_congest_t totals;
++
++	totals.duration  = 0;
++	totals.congest_ibss  = 0;
++	totals.congest_obss  = 0;
++	totals.interference  = 0;
++	avg->num_secs = 0;
++
++	for (sec = 0; sec < input->num_secs; sec++) {
++		if (input->secs[sec].duration) {
++			totals.duration += input->secs[sec].duration;
++			totals.congest_ibss += input->secs[sec].congest_ibss;
++			totals.congest_obss += input->secs[sec].congest_obss;
++			totals.interference += input->secs[sec].interference;
++			avg->num_secs++;
++		}
++	}
++	avg->chanspec = input->chanspec;
++
++	if (!avg->num_secs || !totals.duration)
++		return (avg);
++
++	if (percent) {
++		avg->secs[0].duration = totals.duration / avg->num_secs;
++		avg->secs[0].congest_ibss = totals.congest_ibss * 100/totals.duration;
++		avg->secs[0].congest_obss = totals.congest_obss * 100/totals.duration;
++		avg->secs[0].interference = totals.interference * 100/totals.duration;
++	} else {
++		avg->secs[0].duration = totals.duration / avg->num_secs;
++		avg->secs[0].congest_ibss = totals.congest_ibss / avg->num_secs;
++		avg->secs[0].congest_obss = totals.congest_obss / avg->num_secs;
++		avg->secs[0].interference = totals.interference / avg->num_secs;
++	}
++
++	return (avg);
++}
++
++static void
++cca_info(uint8 *bitmap, int num_bits, int *left, int *bit_pos)
++{
++	int i;
++	for (*left = 0, i = 0; i < num_bits; i++) {
++		if (isset(bitmap, i)) {
++			(*left)++;
++			*bit_pos = i;
++		}
++	}
++}
++
++static uint8
++spec_to_chan(chanspec_t chspec)
++{
++	uint8 center_ch, edge, primary, sb;
++
++	center_ch = CHSPEC_CHANNEL(chspec);
++
++	if (CHSPEC_BW_LE20(chspec)) {
++		return center_ch;
++	} else {
++		/* the lower edge of the wide channel is half the bw from
++		 * the center channel.
++		 */
++		if (CHSPEC_IS40(chspec)) {
++			edge = center_ch - CH_20MHZ_APART;
++		} else {
++			/* must be 80MHz (until we support more) */
++			ASSERT(CHSPEC_IS80(chspec));
++			edge = center_ch - CH_40MHZ_APART;
++		}
++
++		/* find the channel number of the lowest 20MHz primary channel */
++		primary = edge + CH_10MHZ_APART;
++
++		/* select the actual subband */
++		sb = (chspec & WL_CHANSPEC_CTL_SB_MASK) >> WL_CHANSPEC_CTL_SB_SHIFT;
++		primary = primary + sb * CH_20MHZ_APART;
++
++		return primary;
++	}
++}
++
++/*
++	Take an array of measumrements representing summaries of different channels.
++	Return a recomended channel.
++	Interference is evil, get rid of that first.
++	Then hunt for lowest Other bss traffic.
++	Don't forget that channels with low duration times may not have accurate readings.
++	For the moment, do not overwrite input array.
++*/
++int
++cca_analyze(cca_congest_channel_req_t *input[], int num_chans, uint flags, chanspec_t *answer)
++{
++	uint8 *bitmap = NULL;	/* 38 Max channels needs 5 bytes  = 40 */
++	int i, left, winner, ret_val = 0;
++	uint32 min_obss = 1 << 30;
++	uint bitmap_sz;
++
++	bitmap_sz = CEIL(num_chans, NBBY);
++	bitmap = (uint8 *)malloc(bitmap_sz);
++	if (bitmap == NULL) {
++		printf("unable to allocate memory\n");
++		return BCME_NOMEM;
++	}
++
++	memset(bitmap, 0, bitmap_sz);
++	/* Initially, all channels are up for consideration */
++	for (i = 0; i < num_chans; i++) {
++		if (input[i]->chanspec)
++			setbit(bitmap, i);
++	}
++	cca_info(bitmap, num_chans, &left, &i);
++	if (!left) {
++		ret_val = CCA_ERRNO_TOO_FEW;
++		goto f_exit;
++	}
++
++	/* Filter for 2.4 GHz Band */
++	if (flags & CCA_FLAG_2G_ONLY) {
++		for (i = 0; i < num_chans; i++) {
++			if (!CHSPEC_IS2G(input[i]->chanspec))
++				clrbit(bitmap, i);
++		}
++	}
++	cca_info(bitmap, num_chans, &left, &i);
++	if (!left) {
++		ret_val = CCA_ERRNO_BAND;
++		goto f_exit;
++	}
++
++	/* Filter for 5 GHz Band */
++	if (flags & CCA_FLAG_5G_ONLY) {
++		for (i = 0; i < num_chans; i++) {
++			if (!CHSPEC_IS5G(input[i]->chanspec))
++				clrbit(bitmap, i);
++		}
++	}
++	cca_info(bitmap, num_chans, &left, &i);
++	if (!left) {
++		ret_val = CCA_ERRNO_BAND;
++		goto f_exit;
++	}
++
++	/* Filter for Duration */
++	if (!(flags & CCA_FLAG_IGNORE_DURATION)) {
++		for (i = 0; i < num_chans; i++) {
++			if (input[i]->secs[0].duration < CCA_THRESH_MILLI)
++				clrbit(bitmap, i);
++		}
++	}
++	cca_info(bitmap, num_chans, &left, &i);
++	if (!left) {
++		ret_val = CCA_ERRNO_DURATION;
++		goto f_exit;
++	}
++
++	/* Filter for 1 6 11 on 2.4 Band */
++	if (flags &  CCA_FLAGS_PREFER_1_6_11) {
++		int tmp_channel = spec_to_chan(input[i]->chanspec);
++		int is2g = CHSPEC_IS2G(input[i]->chanspec);
++		for (i = 0; i < num_chans; i++) {
++			if (is2g && tmp_channel != 1 && tmp_channel != 6 && tmp_channel != 11)
++				clrbit(bitmap, i);
++		}
++	}
++	cca_info(bitmap, num_chans, &left, &i);
++	if (!left) {
++		ret_val = CCA_ERRNO_PREF_CHAN;
++		goto f_exit;
++	}
++
++	/* Toss high interference interference */
++	if (!(flags & CCA_FLAG_IGNORE_INTERFER)) {
++		for (i = 0; i < num_chans; i++) {
++			if (input[i]->secs[0].interference > CCA_THRESH_INTERFERE)
++				clrbit(bitmap, i);
++		}
++		cca_info(bitmap, num_chans, &left, &i);
++		if (!left) {
++			ret_val = CCA_ERRNO_INTERFER;
++			goto f_exit;
++		}
++	}
++
++	/* Now find lowest obss */
++	winner = 0;
++	for (i = 0; i < num_chans; i++) {
++		if (isset(bitmap, i) && input[i]->secs[0].congest_obss < min_obss) {
++			winner = i;
++			min_obss = input[i]->secs[0].congest_obss;
++		}
++	}
++	*answer = input[winner]->chanspec;
++	f_exit:
++	free(bitmap);	/* free the allocated memory for bitmap */
++	return ret_val;
++}
++#endif /* !BCMDRIVER */
++
++/* offset of cntmember by sizeof(uint32) from the first cnt variable, txframe. */
++#define IDX_IN_WL_CNT_VER_6_T(cntmember)		\
++	((OFFSETOF(wl_cnt_ver_6_t, cntmember) - OFFSETOF(wl_cnt_ver_6_t, txframe)) / sizeof(uint32))
++
++#define IDX_IN_WL_CNT_VER_11_T(cntmember)		\
++	((OFFSETOF(wl_cnt_ver_11_t, cntmember) - OFFSETOF(wl_cnt_ver_11_t, txframe))	\
++	/ sizeof(uint32))
++
++/* Exclude version and length fields */
++#define NUM_OF_CNT_IN_WL_CNT_VER_6_T	\
++	((sizeof(wl_cnt_ver_6_t) - 2 * sizeof(uint16)) / sizeof(uint32))
++/* Exclude macstat cnt variables. wl_cnt_ver_6_t only has 62 macstat cnt variables. */
++#define NUM_OF_WLCCNT_IN_WL_CNT_VER_6_T			\
++	(NUM_OF_CNT_IN_WL_CNT_VER_6_T - (WL_CNT_MCST_VAR_NUM - 2))
++
++/* Exclude version and length fields */
++#define NUM_OF_CNT_IN_WL_CNT_VER_11_T	\
++	((sizeof(wl_cnt_ver_11_t) - 2 * sizeof(uint16)) / sizeof(uint32))
++/* Exclude 64 macstat cnt variables. */
++#define NUM_OF_WLCCNT_IN_WL_CNT_VER_11_T		\
++	(NUM_OF_CNT_IN_WL_CNT_VER_11_T - WL_CNT_MCST_VAR_NUM)
++
++/* Index conversion table from wl_cnt_ver_6_t to wl_cnt_wlc_t */
++static const uint8 wlcntver6t_to_wlcntwlct[NUM_OF_WLCCNT_IN_WL_CNT_VER_6_T] = {
++	IDX_IN_WL_CNT_VER_6_T(txframe),
++	IDX_IN_WL_CNT_VER_6_T(txbyte),
++	IDX_IN_WL_CNT_VER_6_T(txretrans),
++	IDX_IN_WL_CNT_VER_6_T(txerror),
++	IDX_IN_WL_CNT_VER_6_T(txctl),
++	IDX_IN_WL_CNT_VER_6_T(txprshort),
++	IDX_IN_WL_CNT_VER_6_T(txserr),
++	IDX_IN_WL_CNT_VER_6_T(txnobuf),
++	IDX_IN_WL_CNT_VER_6_T(txnoassoc),
++	IDX_IN_WL_CNT_VER_6_T(txrunt),
++	IDX_IN_WL_CNT_VER_6_T(txchit),
++	IDX_IN_WL_CNT_VER_6_T(txcmiss),
++	IDX_IN_WL_CNT_VER_6_T(txuflo),
++	IDX_IN_WL_CNT_VER_6_T(txphyerr),
++	IDX_IN_WL_CNT_VER_6_T(txphycrs),
++	IDX_IN_WL_CNT_VER_6_T(rxframe),
++	IDX_IN_WL_CNT_VER_6_T(rxbyte),
++	IDX_IN_WL_CNT_VER_6_T(rxerror),
++	IDX_IN_WL_CNT_VER_6_T(rxctl),
++	IDX_IN_WL_CNT_VER_6_T(rxnobuf),
++	IDX_IN_WL_CNT_VER_6_T(rxnondata),
++	IDX_IN_WL_CNT_VER_6_T(rxbadds),
++	IDX_IN_WL_CNT_VER_6_T(rxbadcm),
++	IDX_IN_WL_CNT_VER_6_T(rxfragerr),
++	IDX_IN_WL_CNT_VER_6_T(rxrunt),
++	IDX_IN_WL_CNT_VER_6_T(rxgiant),
++	IDX_IN_WL_CNT_VER_6_T(rxnoscb),
++	IDX_IN_WL_CNT_VER_6_T(rxbadproto),
++	IDX_IN_WL_CNT_VER_6_T(rxbadsrcmac),
++	IDX_IN_WL_CNT_VER_6_T(rxbadda),
++	IDX_IN_WL_CNT_VER_6_T(rxfilter),
++	IDX_IN_WL_CNT_VER_6_T(rxoflo),
++	IDX_IN_WL_CNT_VER_6_T(rxuflo),
++	IDX_IN_WL_CNT_VER_6_T(rxuflo) + 1,
++	IDX_IN_WL_CNT_VER_6_T(rxuflo) + 2,
++	IDX_IN_WL_CNT_VER_6_T(rxuflo) + 3,
++	IDX_IN_WL_CNT_VER_6_T(rxuflo) + 4,
++	IDX_IN_WL_CNT_VER_6_T(rxuflo) + 5,
++	IDX_IN_WL_CNT_VER_6_T(d11cnt_txrts_off),
++	IDX_IN_WL_CNT_VER_6_T(d11cnt_rxcrc_off),
++	IDX_IN_WL_CNT_VER_6_T(d11cnt_txnocts_off),
++	IDX_IN_WL_CNT_VER_6_T(dmade),
++	IDX_IN_WL_CNT_VER_6_T(dmada),
++	IDX_IN_WL_CNT_VER_6_T(dmape),
++	IDX_IN_WL_CNT_VER_6_T(reset),
++	IDX_IN_WL_CNT_VER_6_T(tbtt),
++	IDX_IN_WL_CNT_VER_6_T(txdmawar),
++	IDX_IN_WL_CNT_VER_6_T(pkt_callback_reg_fail),
++	IDX_IN_WL_CNT_VER_6_T(txfrag),
++	IDX_IN_WL_CNT_VER_6_T(txmulti),
++	IDX_IN_WL_CNT_VER_6_T(txfail),
++	IDX_IN_WL_CNT_VER_6_T(txretry),
++	IDX_IN_WL_CNT_VER_6_T(txretrie),
++	IDX_IN_WL_CNT_VER_6_T(rxdup),
++	IDX_IN_WL_CNT_VER_6_T(txrts),
++	IDX_IN_WL_CNT_VER_6_T(txnocts),
++	IDX_IN_WL_CNT_VER_6_T(txnoack),
++	IDX_IN_WL_CNT_VER_6_T(rxfrag),
++	IDX_IN_WL_CNT_VER_6_T(rxmulti),
++	IDX_IN_WL_CNT_VER_6_T(rxcrc),
++	IDX_IN_WL_CNT_VER_6_T(txfrmsnt),
++	IDX_IN_WL_CNT_VER_6_T(rxundec),
++	IDX_IN_WL_CNT_VER_6_T(tkipmicfaill),
++	IDX_IN_WL_CNT_VER_6_T(tkipcntrmsr),
++	IDX_IN_WL_CNT_VER_6_T(tkipreplay),
++	IDX_IN_WL_CNT_VER_6_T(ccmpfmterr),
++	IDX_IN_WL_CNT_VER_6_T(ccmpreplay),
++	IDX_IN_WL_CNT_VER_6_T(ccmpundec),
++	IDX_IN_WL_CNT_VER_6_T(fourwayfail),
++	IDX_IN_WL_CNT_VER_6_T(wepundec),
++	IDX_IN_WL_CNT_VER_6_T(wepicverr),
++	IDX_IN_WL_CNT_VER_6_T(decsuccess),
++	IDX_IN_WL_CNT_VER_6_T(tkipicverr),
++	IDX_IN_WL_CNT_VER_6_T(wepexcluded),
++	IDX_IN_WL_CNT_VER_6_T(txchanrej),
++	IDX_IN_WL_CNT_VER_6_T(psmwds),
++	IDX_IN_WL_CNT_VER_6_T(phywatchdog),
++	IDX_IN_WL_CNT_VER_6_T(prq_entries_handled),
++	IDX_IN_WL_CNT_VER_6_T(prq_undirected_entries),
++	IDX_IN_WL_CNT_VER_6_T(prq_bad_entries),
++	IDX_IN_WL_CNT_VER_6_T(atim_suppress_count),
++	IDX_IN_WL_CNT_VER_6_T(bcn_template_not_ready),
++	IDX_IN_WL_CNT_VER_6_T(bcn_template_not_ready_done),
++	IDX_IN_WL_CNT_VER_6_T(late_tbtt_dpc),
++	IDX_IN_WL_CNT_VER_6_T(rx1mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx2mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx5mbps5),
++	IDX_IN_WL_CNT_VER_6_T(rx6mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx9mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx11mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx12mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx18mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx24mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx36mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx48mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx54mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx108mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx162mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx216mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx270mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx324mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx378mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx432mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx486mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx540mbps),
++	IDX_IN_WL_CNT_VER_6_T(rfdisable),
++	IDX_IN_WL_CNT_VER_6_T(txexptime),
++	IDX_IN_WL_CNT_VER_6_T(txmpdu_sgi),
++	IDX_IN_WL_CNT_VER_6_T(rxmpdu_sgi),
++	IDX_IN_WL_CNT_VER_6_T(txmpdu_stbc),
++	IDX_IN_WL_CNT_VER_6_T(rxmpdu_stbc),
++	IDX_IN_WL_CNT_VER_6_T(rxundec_mcst),
++	IDX_IN_WL_CNT_VER_6_T(tkipmicfaill_mcst),
++	IDX_IN_WL_CNT_VER_6_T(tkipcntrmsr_mcst),
++	IDX_IN_WL_CNT_VER_6_T(tkipreplay_mcst),
++	IDX_IN_WL_CNT_VER_6_T(ccmpfmterr_mcst),
++	IDX_IN_WL_CNT_VER_6_T(ccmpreplay_mcst),
++	IDX_IN_WL_CNT_VER_6_T(ccmpundec_mcst),
++	IDX_IN_WL_CNT_VER_6_T(fourwayfail_mcst),
++	IDX_IN_WL_CNT_VER_6_T(wepundec_mcst),
++	IDX_IN_WL_CNT_VER_6_T(wepicverr_mcst),
++	IDX_IN_WL_CNT_VER_6_T(decsuccess_mcst),
++	IDX_IN_WL_CNT_VER_6_T(tkipicverr_mcst),
++	IDX_IN_WL_CNT_VER_6_T(wepexcluded_mcst)
++};
++
++/* Index conversion table from wl_cnt_ver_11_t to wl_cnt_wlc_t */
++static const uint8 wlcntver11t_to_wlcntwlct[NUM_OF_WLCCNT_IN_WL_CNT_VER_11_T] = {
++	IDX_IN_WL_CNT_VER_11_T(txframe),
++	IDX_IN_WL_CNT_VER_11_T(txbyte),
++	IDX_IN_WL_CNT_VER_11_T(txretrans),
++	IDX_IN_WL_CNT_VER_11_T(txerror),
++	IDX_IN_WL_CNT_VER_11_T(txctl),
++	IDX_IN_WL_CNT_VER_11_T(txprshort),
++	IDX_IN_WL_CNT_VER_11_T(txserr),
++	IDX_IN_WL_CNT_VER_11_T(txnobuf),
++	IDX_IN_WL_CNT_VER_11_T(txnoassoc),
++	IDX_IN_WL_CNT_VER_11_T(txrunt),
++	IDX_IN_WL_CNT_VER_11_T(txchit),
++	IDX_IN_WL_CNT_VER_11_T(txcmiss),
++	IDX_IN_WL_CNT_VER_11_T(txuflo),
++	IDX_IN_WL_CNT_VER_11_T(txphyerr),
++	IDX_IN_WL_CNT_VER_11_T(txphycrs),
++	IDX_IN_WL_CNT_VER_11_T(rxframe),
++	IDX_IN_WL_CNT_VER_11_T(rxbyte),
++	IDX_IN_WL_CNT_VER_11_T(rxerror),
++	IDX_IN_WL_CNT_VER_11_T(rxctl),
++	IDX_IN_WL_CNT_VER_11_T(rxnobuf),
++	IDX_IN_WL_CNT_VER_11_T(rxnondata),
++	IDX_IN_WL_CNT_VER_11_T(rxbadds),
++	IDX_IN_WL_CNT_VER_11_T(rxbadcm),
++	IDX_IN_WL_CNT_VER_11_T(rxfragerr),
++	IDX_IN_WL_CNT_VER_11_T(rxrunt),
++	IDX_IN_WL_CNT_VER_11_T(rxgiant),
++	IDX_IN_WL_CNT_VER_11_T(rxnoscb),
++	IDX_IN_WL_CNT_VER_11_T(rxbadproto),
++	IDX_IN_WL_CNT_VER_11_T(rxbadsrcmac),
++	IDX_IN_WL_CNT_VER_11_T(rxbadda),
++	IDX_IN_WL_CNT_VER_11_T(rxfilter),
++	IDX_IN_WL_CNT_VER_11_T(rxoflo),
++	IDX_IN_WL_CNT_VER_11_T(rxuflo),
++	IDX_IN_WL_CNT_VER_11_T(rxuflo) + 1,
++	IDX_IN_WL_CNT_VER_11_T(rxuflo) + 2,
++	IDX_IN_WL_CNT_VER_11_T(rxuflo) + 3,
++	IDX_IN_WL_CNT_VER_11_T(rxuflo) + 4,
++	IDX_IN_WL_CNT_VER_11_T(rxuflo) + 5,
++	IDX_IN_WL_CNT_VER_11_T(d11cnt_txrts_off),
++	IDX_IN_WL_CNT_VER_11_T(d11cnt_rxcrc_off),
++	IDX_IN_WL_CNT_VER_11_T(d11cnt_txnocts_off),
++	IDX_IN_WL_CNT_VER_11_T(dmade),
++	IDX_IN_WL_CNT_VER_11_T(dmada),
++	IDX_IN_WL_CNT_VER_11_T(dmape),
++	IDX_IN_WL_CNT_VER_11_T(reset),
++	IDX_IN_WL_CNT_VER_11_T(tbtt),
++	IDX_IN_WL_CNT_VER_11_T(txdmawar),
++	IDX_IN_WL_CNT_VER_11_T(pkt_callback_reg_fail),
++	IDX_IN_WL_CNT_VER_11_T(txfrag),
++	IDX_IN_WL_CNT_VER_11_T(txmulti),
++	IDX_IN_WL_CNT_VER_11_T(txfail),
++	IDX_IN_WL_CNT_VER_11_T(txretry),
++	IDX_IN_WL_CNT_VER_11_T(txretrie),
++	IDX_IN_WL_CNT_VER_11_T(rxdup),
++	IDX_IN_WL_CNT_VER_11_T(txrts),
++	IDX_IN_WL_CNT_VER_11_T(txnocts),
++	IDX_IN_WL_CNT_VER_11_T(txnoack),
++	IDX_IN_WL_CNT_VER_11_T(rxfrag),
++	IDX_IN_WL_CNT_VER_11_T(rxmulti),
++	IDX_IN_WL_CNT_VER_11_T(rxcrc),
++	IDX_IN_WL_CNT_VER_11_T(txfrmsnt),
++	IDX_IN_WL_CNT_VER_11_T(rxundec),
++	IDX_IN_WL_CNT_VER_11_T(tkipmicfaill),
++	IDX_IN_WL_CNT_VER_11_T(tkipcntrmsr),
++	IDX_IN_WL_CNT_VER_11_T(tkipreplay),
++	IDX_IN_WL_CNT_VER_11_T(ccmpfmterr),
++	IDX_IN_WL_CNT_VER_11_T(ccmpreplay),
++	IDX_IN_WL_CNT_VER_11_T(ccmpundec),
++	IDX_IN_WL_CNT_VER_11_T(fourwayfail),
++	IDX_IN_WL_CNT_VER_11_T(wepundec),
++	IDX_IN_WL_CNT_VER_11_T(wepicverr),
++	IDX_IN_WL_CNT_VER_11_T(decsuccess),
++	IDX_IN_WL_CNT_VER_11_T(tkipicverr),
++	IDX_IN_WL_CNT_VER_11_T(wepexcluded),
++	IDX_IN_WL_CNT_VER_11_T(txchanrej),
++	IDX_IN_WL_CNT_VER_11_T(psmwds),
++	IDX_IN_WL_CNT_VER_11_T(phywatchdog),
++	IDX_IN_WL_CNT_VER_11_T(prq_entries_handled),
++	IDX_IN_WL_CNT_VER_11_T(prq_undirected_entries),
++	IDX_IN_WL_CNT_VER_11_T(prq_bad_entries),
++	IDX_IN_WL_CNT_VER_11_T(atim_suppress_count),
++	IDX_IN_WL_CNT_VER_11_T(bcn_template_not_ready),
++	IDX_IN_WL_CNT_VER_11_T(bcn_template_not_ready_done),
++	IDX_IN_WL_CNT_VER_11_T(late_tbtt_dpc),
++	IDX_IN_WL_CNT_VER_11_T(rx1mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx2mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx5mbps5),
++	IDX_IN_WL_CNT_VER_11_T(rx6mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx9mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx11mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx12mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx18mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx24mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx36mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx48mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx54mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx108mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx162mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx216mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx270mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx324mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx378mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx432mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx486mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx540mbps),
++	IDX_IN_WL_CNT_VER_11_T(rfdisable),
++	IDX_IN_WL_CNT_VER_11_T(txexptime),
++	IDX_IN_WL_CNT_VER_11_T(txmpdu_sgi),
++	IDX_IN_WL_CNT_VER_11_T(rxmpdu_sgi),
++	IDX_IN_WL_CNT_VER_11_T(txmpdu_stbc),
++	IDX_IN_WL_CNT_VER_11_T(rxmpdu_stbc),
++	IDX_IN_WL_CNT_VER_11_T(rxundec_mcst),
++	IDX_IN_WL_CNT_VER_11_T(tkipmicfaill_mcst),
++	IDX_IN_WL_CNT_VER_11_T(tkipcntrmsr_mcst),
++	IDX_IN_WL_CNT_VER_11_T(tkipreplay_mcst),
++	IDX_IN_WL_CNT_VER_11_T(ccmpfmterr_mcst),
++	IDX_IN_WL_CNT_VER_11_T(ccmpreplay_mcst),
++	IDX_IN_WL_CNT_VER_11_T(ccmpundec_mcst),
++	IDX_IN_WL_CNT_VER_11_T(fourwayfail_mcst),
++	IDX_IN_WL_CNT_VER_11_T(wepundec_mcst),
++	IDX_IN_WL_CNT_VER_11_T(wepicverr_mcst),
++	IDX_IN_WL_CNT_VER_11_T(decsuccess_mcst),
++	IDX_IN_WL_CNT_VER_11_T(tkipicverr_mcst),
++	IDX_IN_WL_CNT_VER_11_T(wepexcluded_mcst),
++	IDX_IN_WL_CNT_VER_11_T(dma_hang),
++	IDX_IN_WL_CNT_VER_11_T(reinit),
++	IDX_IN_WL_CNT_VER_11_T(pstatxucast),
++	IDX_IN_WL_CNT_VER_11_T(pstatxnoassoc),
++	IDX_IN_WL_CNT_VER_11_T(pstarxucast),
++	IDX_IN_WL_CNT_VER_11_T(pstarxbcmc),
++	IDX_IN_WL_CNT_VER_11_T(pstatxbcmc),
++	IDX_IN_WL_CNT_VER_11_T(cso_passthrough),
++	IDX_IN_WL_CNT_VER_11_T(cso_normal),
++	IDX_IN_WL_CNT_VER_11_T(chained),
++	IDX_IN_WL_CNT_VER_11_T(chainedsz1),
++	IDX_IN_WL_CNT_VER_11_T(unchained),
++	IDX_IN_WL_CNT_VER_11_T(maxchainsz),
++	IDX_IN_WL_CNT_VER_11_T(currchainsz),
++	IDX_IN_WL_CNT_VER_11_T(pciereset),
++	IDX_IN_WL_CNT_VER_11_T(cfgrestore),
++	IDX_IN_WL_CNT_VER_11_T(reinitreason),
++	IDX_IN_WL_CNT_VER_11_T(reinitreason) + 1,
++	IDX_IN_WL_CNT_VER_11_T(reinitreason) + 2,
++	IDX_IN_WL_CNT_VER_11_T(reinitreason) + 3,
++	IDX_IN_WL_CNT_VER_11_T(reinitreason) + 4,
++	IDX_IN_WL_CNT_VER_11_T(reinitreason) + 5,
++	IDX_IN_WL_CNT_VER_11_T(reinitreason) + 6,
++	IDX_IN_WL_CNT_VER_11_T(reinitreason) + 7,
++	IDX_IN_WL_CNT_VER_11_T(rxrtry),
++	IDX_IN_WL_CNT_VER_11_T(rxmpdu_mu),
++	IDX_IN_WL_CNT_VER_11_T(txbar),
++	IDX_IN_WL_CNT_VER_11_T(rxbar),
++	IDX_IN_WL_CNT_VER_11_T(txpspoll),
++	IDX_IN_WL_CNT_VER_11_T(rxpspoll),
++	IDX_IN_WL_CNT_VER_11_T(txnull),
++	IDX_IN_WL_CNT_VER_11_T(rxnull),
++	IDX_IN_WL_CNT_VER_11_T(txqosnull),
++	IDX_IN_WL_CNT_VER_11_T(rxqosnull),
++	IDX_IN_WL_CNT_VER_11_T(txassocreq),
++	IDX_IN_WL_CNT_VER_11_T(rxassocreq),
++	IDX_IN_WL_CNT_VER_11_T(txreassocreq),
++	IDX_IN_WL_CNT_VER_11_T(rxreassocreq),
++	IDX_IN_WL_CNT_VER_11_T(txdisassoc),
++	IDX_IN_WL_CNT_VER_11_T(rxdisassoc),
++	IDX_IN_WL_CNT_VER_11_T(txassocrsp),
++	IDX_IN_WL_CNT_VER_11_T(rxassocrsp),
++	IDX_IN_WL_CNT_VER_11_T(txreassocrsp),
++	IDX_IN_WL_CNT_VER_11_T(rxreassocrsp),
++	IDX_IN_WL_CNT_VER_11_T(txauth),
++	IDX_IN_WL_CNT_VER_11_T(rxauth),
++	IDX_IN_WL_CNT_VER_11_T(txdeauth),
++	IDX_IN_WL_CNT_VER_11_T(rxdeauth),
++	IDX_IN_WL_CNT_VER_11_T(txprobereq),
++	IDX_IN_WL_CNT_VER_11_T(rxprobereq),
++	IDX_IN_WL_CNT_VER_11_T(txprobersp),
++	IDX_IN_WL_CNT_VER_11_T(rxprobersp),
++	IDX_IN_WL_CNT_VER_11_T(txaction),
++	IDX_IN_WL_CNT_VER_11_T(rxaction),
++	IDX_IN_WL_CNT_VER_11_T(ampdu_wds),
++	IDX_IN_WL_CNT_VER_11_T(txlost),
++	IDX_IN_WL_CNT_VER_11_T(txdatamcast),
++	IDX_IN_WL_CNT_VER_11_T(txdatabcast)
++};
++
++/* Index conversion table from wl_cnt_ver_11_t to
++ * either wl_cnt_ge40mcst_v1_t or wl_cnt_lt40mcst_v1_t
++ */
++static const uint8 wlcntver11t_to_wlcntXX40mcstv1t[WL_CNT_MCST_VAR_NUM] = {
++	IDX_IN_WL_CNT_VER_11_T(txallfrm),
++	IDX_IN_WL_CNT_VER_11_T(txrtsfrm),
++	IDX_IN_WL_CNT_VER_11_T(txctsfrm),
++	IDX_IN_WL_CNT_VER_11_T(txackfrm),
++	IDX_IN_WL_CNT_VER_11_T(txdnlfrm),
++	IDX_IN_WL_CNT_VER_11_T(txbcnfrm),
++	IDX_IN_WL_CNT_VER_11_T(txfunfl),
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 1,
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 2,
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 3,
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 4,
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 5,
++	IDX_IN_WL_CNT_VER_11_T(txfbw),
++	IDX_IN_WL_CNT_VER_11_T(txmpdu),
++	IDX_IN_WL_CNT_VER_11_T(txtplunfl),
++	IDX_IN_WL_CNT_VER_11_T(txphyerror),
++	IDX_IN_WL_CNT_VER_11_T(pktengrxducast),
++	IDX_IN_WL_CNT_VER_11_T(pktengrxdmcast),
++	IDX_IN_WL_CNT_VER_11_T(rxfrmtoolong),
++	IDX_IN_WL_CNT_VER_11_T(rxfrmtooshrt),
++	IDX_IN_WL_CNT_VER_11_T(rxinvmachdr),
++	IDX_IN_WL_CNT_VER_11_T(rxbadfcs),
++	IDX_IN_WL_CNT_VER_11_T(rxbadplcp),
++	IDX_IN_WL_CNT_VER_11_T(rxcrsglitch),
++	IDX_IN_WL_CNT_VER_11_T(rxstrt),
++	IDX_IN_WL_CNT_VER_11_T(rxdfrmucastmbss),
++	IDX_IN_WL_CNT_VER_11_T(rxmfrmucastmbss),
++	IDX_IN_WL_CNT_VER_11_T(rxcfrmucast),
++	IDX_IN_WL_CNT_VER_11_T(rxrtsucast),
++	IDX_IN_WL_CNT_VER_11_T(rxctsucast),
++	IDX_IN_WL_CNT_VER_11_T(rxackucast),
++	IDX_IN_WL_CNT_VER_11_T(rxdfrmocast),
++	IDX_IN_WL_CNT_VER_11_T(rxmfrmocast),
++	IDX_IN_WL_CNT_VER_11_T(rxcfrmocast),
++	IDX_IN_WL_CNT_VER_11_T(rxrtsocast),
++	IDX_IN_WL_CNT_VER_11_T(rxctsocast),
++	IDX_IN_WL_CNT_VER_11_T(rxdfrmmcast),
++	IDX_IN_WL_CNT_VER_11_T(rxmfrmmcast),
++	IDX_IN_WL_CNT_VER_11_T(rxcfrmmcast),
++	IDX_IN_WL_CNT_VER_11_T(rxbeaconmbss),
++	IDX_IN_WL_CNT_VER_11_T(rxdfrmucastobss),
++	IDX_IN_WL_CNT_VER_11_T(rxbeaconobss),
++	IDX_IN_WL_CNT_VER_11_T(rxrsptmout),
++	IDX_IN_WL_CNT_VER_11_T(bcntxcancl),
++	IDX_IN_WL_CNT_VER_11_T(rxnodelim),
++	IDX_IN_WL_CNT_VER_11_T(rxf0ovfl),
++	IDX_IN_WL_CNT_VER_11_T(rxf1ovfl),
++	IDX_IN_WL_CNT_VER_11_T(rxf2ovfl),
++	IDX_IN_WL_CNT_VER_11_T(txsfovfl),
++	IDX_IN_WL_CNT_VER_11_T(pmqovfl),
++	IDX_IN_WL_CNT_VER_11_T(rxcgprqfrm),
++	IDX_IN_WL_CNT_VER_11_T(rxcgprsqovfl),
++	IDX_IN_WL_CNT_VER_11_T(txcgprsfail),
++	IDX_IN_WL_CNT_VER_11_T(txcgprssuc),
++	IDX_IN_WL_CNT_VER_11_T(prs_timeout),
++	IDX_IN_WL_CNT_VER_11_T(rxnack),
++	IDX_IN_WL_CNT_VER_11_T(frmscons),
++	IDX_IN_WL_CNT_VER_11_T(txnack),
++	IDX_IN_WL_CNT_VER_11_T(rxback),
++	IDX_IN_WL_CNT_VER_11_T(txback),
++	IDX_IN_WL_CNT_VER_11_T(bphy_rxcrsglitch),
++	IDX_IN_WL_CNT_VER_11_T(rxdrop20s),
++	IDX_IN_WL_CNT_VER_11_T(rxtoolate),
++	IDX_IN_WL_CNT_VER_11_T(bphy_badplcp)
++};
++
++/* For mcst offsets that were not used. (2 Pads) */
++#define INVALID_MCST_IDX ((uint8)(-1))
++/* Index conversion table from wl_cnt_ver_11_t to wl_cnt_v_le10_mcst_t */
++static const uint8 wlcntver11t_to_wlcntvle10mcstt[WL_CNT_MCST_VAR_NUM] = {
++	IDX_IN_WL_CNT_VER_11_T(txallfrm),
++	IDX_IN_WL_CNT_VER_11_T(txrtsfrm),
++	IDX_IN_WL_CNT_VER_11_T(txctsfrm),
++	IDX_IN_WL_CNT_VER_11_T(txackfrm),
++	IDX_IN_WL_CNT_VER_11_T(txdnlfrm),
++	IDX_IN_WL_CNT_VER_11_T(txbcnfrm),
++	IDX_IN_WL_CNT_VER_11_T(txfunfl),
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 1,
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 2,
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 3,
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 4,
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 5,
++	IDX_IN_WL_CNT_VER_11_T(txfbw),
++	INVALID_MCST_IDX,
++	IDX_IN_WL_CNT_VER_11_T(txtplunfl),
++	IDX_IN_WL_CNT_VER_11_T(txphyerror),
++	IDX_IN_WL_CNT_VER_11_T(pktengrxducast),
++	IDX_IN_WL_CNT_VER_11_T(pktengrxdmcast),
++	IDX_IN_WL_CNT_VER_11_T(rxfrmtoolong),
++	IDX_IN_WL_CNT_VER_11_T(rxfrmtooshrt),
++	IDX_IN_WL_CNT_VER_11_T(rxinvmachdr),
++	IDX_IN_WL_CNT_VER_11_T(rxbadfcs),
++	IDX_IN_WL_CNT_VER_11_T(rxbadplcp),
++	IDX_IN_WL_CNT_VER_11_T(rxcrsglitch),
++	IDX_IN_WL_CNT_VER_11_T(rxstrt),
++	IDX_IN_WL_CNT_VER_11_T(rxdfrmucastmbss),
++	IDX_IN_WL_CNT_VER_11_T(rxmfrmucastmbss),
++	IDX_IN_WL_CNT_VER_11_T(rxcfrmucast),
++	IDX_IN_WL_CNT_VER_11_T(rxrtsucast),
++	IDX_IN_WL_CNT_VER_11_T(rxctsucast),
++	IDX_IN_WL_CNT_VER_11_T(rxackucast),
++	IDX_IN_WL_CNT_VER_11_T(rxdfrmocast),
++	IDX_IN_WL_CNT_VER_11_T(rxmfrmocast),
++	IDX_IN_WL_CNT_VER_11_T(rxcfrmocast),
++	IDX_IN_WL_CNT_VER_11_T(rxrtsocast),
++	IDX_IN_WL_CNT_VER_11_T(rxctsocast),
++	IDX_IN_WL_CNT_VER_11_T(rxdfrmmcast),
++	IDX_IN_WL_CNT_VER_11_T(rxmfrmmcast),
++	IDX_IN_WL_CNT_VER_11_T(rxcfrmmcast),
++	IDX_IN_WL_CNT_VER_11_T(rxbeaconmbss),
++	IDX_IN_WL_CNT_VER_11_T(rxdfrmucastobss),
++	IDX_IN_WL_CNT_VER_11_T(rxbeaconobss),
++	IDX_IN_WL_CNT_VER_11_T(rxrsptmout),
++	IDX_IN_WL_CNT_VER_11_T(bcntxcancl),
++	INVALID_MCST_IDX,
++	IDX_IN_WL_CNT_VER_11_T(rxf0ovfl),
++	IDX_IN_WL_CNT_VER_11_T(rxf1ovfl),
++	IDX_IN_WL_CNT_VER_11_T(rxf2ovfl),
++	IDX_IN_WL_CNT_VER_11_T(txsfovfl),
++	IDX_IN_WL_CNT_VER_11_T(pmqovfl),
++	IDX_IN_WL_CNT_VER_11_T(rxcgprqfrm),
++	IDX_IN_WL_CNT_VER_11_T(rxcgprsqovfl),
++	IDX_IN_WL_CNT_VER_11_T(txcgprsfail),
++	IDX_IN_WL_CNT_VER_11_T(txcgprssuc),
++	IDX_IN_WL_CNT_VER_11_T(prs_timeout),
++	IDX_IN_WL_CNT_VER_11_T(rxnack),
++	IDX_IN_WL_CNT_VER_11_T(frmscons),
++	IDX_IN_WL_CNT_VER_11_T(txnack),
++	IDX_IN_WL_CNT_VER_11_T(rxback),
++	IDX_IN_WL_CNT_VER_11_T(txback),
++	IDX_IN_WL_CNT_VER_11_T(bphy_rxcrsglitch),
++	IDX_IN_WL_CNT_VER_11_T(rxdrop20s),
++	IDX_IN_WL_CNT_VER_11_T(rxtoolate),
++	IDX_IN_WL_CNT_VER_11_T(bphy_badplcp)
++};
++
++
++/* Index conversion table from wl_cnt_ver_6_t to wl_cnt_v_le10_mcst_t */
++static const uint8 wlcntver6t_to_wlcntvle10mcstt[WL_CNT_MCST_VAR_NUM] = {
++	IDX_IN_WL_CNT_VER_6_T(txallfrm),
++	IDX_IN_WL_CNT_VER_6_T(txrtsfrm),
++	IDX_IN_WL_CNT_VER_6_T(txctsfrm),
++	IDX_IN_WL_CNT_VER_6_T(txackfrm),
++	IDX_IN_WL_CNT_VER_6_T(txdnlfrm),
++	IDX_IN_WL_CNT_VER_6_T(txbcnfrm),
++	IDX_IN_WL_CNT_VER_6_T(txfunfl),
++	IDX_IN_WL_CNT_VER_6_T(txfunfl) + 1,
++	IDX_IN_WL_CNT_VER_6_T(txfunfl) + 2,
++	IDX_IN_WL_CNT_VER_6_T(txfunfl) + 3,
++	IDX_IN_WL_CNT_VER_6_T(txfunfl) + 4,
++	IDX_IN_WL_CNT_VER_6_T(txfunfl) + 5,
++	IDX_IN_WL_CNT_VER_6_T(txfbw),
++	INVALID_MCST_IDX,
++	IDX_IN_WL_CNT_VER_6_T(txtplunfl),
++	IDX_IN_WL_CNT_VER_6_T(txphyerror),
++	IDX_IN_WL_CNT_VER_6_T(pktengrxducast),
++	IDX_IN_WL_CNT_VER_6_T(pktengrxdmcast),
++	IDX_IN_WL_CNT_VER_6_T(rxfrmtoolong),
++	IDX_IN_WL_CNT_VER_6_T(rxfrmtooshrt),
++	IDX_IN_WL_CNT_VER_6_T(rxinvmachdr),
++	IDX_IN_WL_CNT_VER_6_T(rxbadfcs),
++	IDX_IN_WL_CNT_VER_6_T(rxbadplcp),
++	IDX_IN_WL_CNT_VER_6_T(rxcrsglitch),
++	IDX_IN_WL_CNT_VER_6_T(rxstrt),
++	IDX_IN_WL_CNT_VER_6_T(rxdfrmucastmbss),
++	IDX_IN_WL_CNT_VER_6_T(rxmfrmucastmbss),
++	IDX_IN_WL_CNT_VER_6_T(rxcfrmucast),
++	IDX_IN_WL_CNT_VER_6_T(rxrtsucast),
++	IDX_IN_WL_CNT_VER_6_T(rxctsucast),
++	IDX_IN_WL_CNT_VER_6_T(rxackucast),
++	IDX_IN_WL_CNT_VER_6_T(rxdfrmocast),
++	IDX_IN_WL_CNT_VER_6_T(rxmfrmocast),
++	IDX_IN_WL_CNT_VER_6_T(rxcfrmocast),
++	IDX_IN_WL_CNT_VER_6_T(rxrtsocast),
++	IDX_IN_WL_CNT_VER_6_T(rxctsocast),
++	IDX_IN_WL_CNT_VER_6_T(rxdfrmmcast),
++	IDX_IN_WL_CNT_VER_6_T(rxmfrmmcast),
++	IDX_IN_WL_CNT_VER_6_T(rxcfrmmcast),
++	IDX_IN_WL_CNT_VER_6_T(rxbeaconmbss),
++	IDX_IN_WL_CNT_VER_6_T(rxdfrmucastobss),
++	IDX_IN_WL_CNT_VER_6_T(rxbeaconobss),
++	IDX_IN_WL_CNT_VER_6_T(rxrsptmout),
++	IDX_IN_WL_CNT_VER_6_T(bcntxcancl),
++	INVALID_MCST_IDX,
++	IDX_IN_WL_CNT_VER_6_T(rxf0ovfl),
++	IDX_IN_WL_CNT_VER_6_T(rxf1ovfl),
++	IDX_IN_WL_CNT_VER_6_T(rxf2ovfl),
++	IDX_IN_WL_CNT_VER_6_T(txsfovfl),
++	IDX_IN_WL_CNT_VER_6_T(pmqovfl),
++	IDX_IN_WL_CNT_VER_6_T(rxcgprqfrm),
++	IDX_IN_WL_CNT_VER_6_T(rxcgprsqovfl),
++	IDX_IN_WL_CNT_VER_6_T(txcgprsfail),
++	IDX_IN_WL_CNT_VER_6_T(txcgprssuc),
++	IDX_IN_WL_CNT_VER_6_T(prs_timeout),
++	IDX_IN_WL_CNT_VER_6_T(rxnack),
++	IDX_IN_WL_CNT_VER_6_T(frmscons),
++	IDX_IN_WL_CNT_VER_6_T(txnack),
++	IDX_IN_WL_CNT_VER_6_T(rxback),
++	IDX_IN_WL_CNT_VER_6_T(txback),
++	IDX_IN_WL_CNT_VER_6_T(bphy_rxcrsglitch),
++	IDX_IN_WL_CNT_VER_6_T(rxdrop20s),
++	IDX_IN_WL_CNT_VER_6_T(rxtoolate),
++	IDX_IN_WL_CNT_VER_6_T(bphy_badplcp)
++};
++
++/* copy wlc layer counters from old type cntbuf to wl_cnt_wlc_t type. */
++static int
++wl_copy_wlccnt(uint16 cntver, uint32 *dst, uint32 *src, uint8 src_max_idx)
++{
++	uint i;
++	if (dst == NULL || src == NULL) {
++		return BCME_ERROR;
++	}
++
++	/* Init wlccnt with invalid value. Unchanged value will not be printed out */
++	for (i = 0; i < (sizeof(wl_cnt_wlc_t) / sizeof(uint32)); i++) {
++		dst[i] = INVALID_CNT_VAL;
++	}
++
++	if (cntver == WL_CNT_VERSION_6) {
++		for (i = 0; i < NUM_OF_WLCCNT_IN_WL_CNT_VER_6_T; i++) {
++			if (wlcntver6t_to_wlcntwlct[i] >= src_max_idx) {
++				/* src buffer does not have counters from here */
++				break;
++			}
++			dst[i] = src[wlcntver6t_to_wlcntwlct[i]];
++		}
++	} else {
++		for (i = 0; i < NUM_OF_WLCCNT_IN_WL_CNT_VER_11_T; i++) {
++			if (wlcntver11t_to_wlcntwlct[i] >= src_max_idx) {
++				/* src buffer does not have counters from here */
++				break;
++			}
++			dst[i] = src[wlcntver11t_to_wlcntwlct[i]];
++		}
++	}
++	return BCME_OK;
++}
++
++/* copy macstat counters from old type cntbuf to wl_cnt_v_le10_mcst_t type. */
++static int
++wl_copy_macstat_upto_ver10(uint16 cntver, uint32 *dst, uint32 *src)
++{
++	uint i;
++
++	if (dst == NULL || src == NULL) {
++		return BCME_ERROR;
++	}
++
++	if (cntver == WL_CNT_VERSION_6) {
++		for (i = 0; i < WL_CNT_MCST_VAR_NUM; i++) {
++			if (wlcntver6t_to_wlcntvle10mcstt[i] == INVALID_MCST_IDX) {
++				/* This mcst counter does not exist in wl_cnt_ver_6_t */
++				dst[i] = INVALID_CNT_VAL;
++			} else {
++				dst[i] = src[wlcntver6t_to_wlcntvle10mcstt[i]];
++			}
++		}
++	} else {
++		for (i = 0; i < WL_CNT_MCST_VAR_NUM; i++) {
++			if (wlcntver11t_to_wlcntvle10mcstt[i] == INVALID_MCST_IDX) {
++				/* This mcst counter does not exist in wl_cnt_ver_11_t */
++				dst[i] = INVALID_CNT_VAL;
++			} else {
++				dst[i] = src[wlcntver11t_to_wlcntvle10mcstt[i]];
++			}
++		}
++	}
++	return BCME_OK;
++}
++
++static int
++wl_copy_macstat_ver11(uint32 *dst, uint32 *src)
++{
++	uint i;
++
++	if (dst == NULL || src == NULL) {
++		return BCME_ERROR;
++	}
++
++	for (i = 0; i < WL_CNT_MCST_VAR_NUM; i++) {
++		dst[i] = src[wlcntver11t_to_wlcntXX40mcstv1t[i]];
++	}
++	return BCME_OK;
++}
++
++/**
++ * Translate non-xtlv 'wl counters' IOVar buffer received by old driver/FW to xtlv format.
++ * Parameters:
++ *	cntbuf: pointer to non-xtlv 'wl counters' IOVar buffer received by old driver/FW.
++ *		Newly translated xtlv format is written to this pointer.
++ *	buflen: length of the "cntbuf" without any padding.
++ *	corerev: chip core revision of the driver/FW.
++ */
++int
++wl_cntbuf_to_xtlv_format(void *ctx, void *cntbuf, int buflen, uint32 corerev)
++{
++	wl_cnt_wlc_t *wlccnt = NULL;
++	uint32 *macstat = NULL;
++	xtlv_desc_t xtlv_desc[3];
++	uint16 mcst_xtlv_id;
++	int res = BCME_OK;
++	wl_cnt_info_t *cntinfo = cntbuf;
++	void *xtlvbuf_p = cntinfo->data;
++	uint16 ver = cntinfo->version;
++	uint16 xtlvbuflen = (uint16)buflen;
++	uint16 src_max_idx;
++#ifdef BCMDRIVER
++	osl_t *osh = ctx;
++#else
++	BCM_REFERENCE(ctx);
++#endif
++
++	if (ver >= WL_CNT_VERSION_XTLV) {
++		/* Already in xtlv format. */
++		goto exit;
++	}
++
++#ifdef BCMDRIVER
++	wlccnt = MALLOC(osh, sizeof(*wlccnt));
++	macstat = MALLOC(osh, WL_CNT_MCST_STRUCT_SZ);
++#else
++	wlccnt = (wl_cnt_wlc_t *)malloc(sizeof(*wlccnt));
++	macstat = (uint32 *)malloc(WL_CNT_MCST_STRUCT_SZ);
++#endif
++	if (!wlccnt || !macstat) {
++		printf("%s: malloc fail!\n", __FUNCTION__);
++		res = BCME_NOMEM;
++		goto exit;
++	}
++
++	/* Check if the max idx in the struct exceeds the boundary of uint8 */
++	if (NUM_OF_CNT_IN_WL_CNT_VER_6_T > ((uint8)(-1) + 1) ||
++		NUM_OF_CNT_IN_WL_CNT_VER_11_T > ((uint8)(-1) + 1)) {
++		printf("wlcntverXXt_to_wlcntwlct and src_max_idx need"
++			" to be of uint16 instead of uint8\n");
++		res = BCME_ERROR;
++		goto exit;
++	}
++
++	/* Exclude version and length fields in either wlc_cnt_ver_6_t or wlc_cnt_ver_11_t */
++	src_max_idx = (cntinfo->datalen - OFFSETOF(wl_cnt_info_t, data)) / sizeof(uint32);
++	if (src_max_idx > (uint8)(-1)) {
++		printf("wlcntverXXt_to_wlcntwlct and src_max_idx need"
++			" to be of uint16 instead of uint8\n"
++			"Try updating wl utility to the latest.\n");
++		src_max_idx = (uint8)(-1);
++	}
++
++	/* Copy wlc layer counters to wl_cnt_wlc_t */
++	res = wl_copy_wlccnt(ver, (uint32 *)wlccnt, (uint32 *)cntinfo->data, (uint8)src_max_idx);
++	if (res != BCME_OK) {
++		printf("wl_copy_wlccnt fail!\n");
++		goto exit;
++	}
++
++	/* Copy macstat counters to wl_cnt_wlc_t */
++	if (ver == WL_CNT_VERSION_11) {
++		res = wl_copy_macstat_ver11(macstat, (uint32 *)cntinfo->data);
++		if (res != BCME_OK) {
++			printf("wl_copy_macstat_ver11 fail!\n");
++			goto exit;
++		}
++		if (corerev >= 40) {
++			mcst_xtlv_id = WL_CNT_XTLV_GE40_UCODE_V1;
++		} else {
++			mcst_xtlv_id = WL_CNT_XTLV_LT40_UCODE_V1;
++		}
++	} else {
++		res = wl_copy_macstat_upto_ver10(ver, macstat, (uint32 *)cntinfo->data);
++		if (res != BCME_OK) {
++			printf("wl_copy_macstat_upto_ver10 fail!\n");
++			goto exit;
++		}
++		mcst_xtlv_id = WL_CNT_XTLV_CNTV_LE10_UCODE;
++	}
++
++	xtlv_desc[0].type = WL_CNT_XTLV_WLC;
++	xtlv_desc[0].len = sizeof(*wlccnt);
++	xtlv_desc[0].ptr = wlccnt;
++
++	xtlv_desc[1].type = mcst_xtlv_id;
++	xtlv_desc[1].len = WL_CNT_MCST_STRUCT_SZ;
++	xtlv_desc[1].ptr = macstat;
++
++	xtlv_desc[2].type = 0;
++	xtlv_desc[2].len = 0;
++	xtlv_desc[2].ptr = NULL;
++
++	memset(cntbuf, 0, buflen);
++
++	res = bcm_pack_xtlv_buf_from_mem(&xtlvbuf_p, &xtlvbuflen,
++		xtlv_desc, BCM_XTLV_OPTION_ALIGN32);
++	cntinfo->datalen = (buflen - xtlvbuflen);
++exit:
++#ifdef BCMDRIVER
++	if (wlccnt) {
++		MFREE(osh, wlccnt, sizeof(*wlccnt));
++	}
++	if (macstat) {
++		MFREE(osh, macstat, WL_CNT_MCST_STRUCT_SZ);
++	}
++#else
++	if (wlccnt) {
++		free(wlccnt);
++	}
++	if (macstat) {
++		free(macstat);
++	}
++#endif
++	return res;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/bcmevent.c b/module_drivers/drivers/net/wireless/bcmdhd/bcmevent.c
+new file mode 100644
+index 000000000..1e44ad7d4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/bcmevent.c
+@@ -0,0 +1,385 @@
++/*
++ * bcmevent read-only data shared by kernel or app layers
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmevent.c 707287 2017-06-27 06:44:29Z $
++ */
++
++#include <typedefs.h>
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <ethernet.h>
++#include <bcmeth.h>
++#include <bcmevent.h>
++#include <802.11.h>
++
++/* Table of event name strings for UIs and debugging dumps */
++typedef struct {
++	uint event;
++	const char *name;
++} bcmevent_name_str_t;
++
++/* Use the actual name for event tracing */
++#define BCMEVENT_NAME(_event) {(_event), #_event}
++
++static const bcmevent_name_str_t bcmevent_names[] = {
++	BCMEVENT_NAME(WLC_E_SET_SSID),
++	BCMEVENT_NAME(WLC_E_JOIN),
++	BCMEVENT_NAME(WLC_E_START),
++	BCMEVENT_NAME(WLC_E_AUTH),
++	BCMEVENT_NAME(WLC_E_AUTH_IND),
++	BCMEVENT_NAME(WLC_E_DEAUTH),
++	BCMEVENT_NAME(WLC_E_DEAUTH_IND),
++	BCMEVENT_NAME(WLC_E_ASSOC),
++	BCMEVENT_NAME(WLC_E_ASSOC_IND),
++	BCMEVENT_NAME(WLC_E_REASSOC),
++	BCMEVENT_NAME(WLC_E_REASSOC_IND),
++	BCMEVENT_NAME(WLC_E_DISASSOC),
++	BCMEVENT_NAME(WLC_E_DISASSOC_IND),
++	BCMEVENT_NAME(WLC_E_QUIET_START),
++	BCMEVENT_NAME(WLC_E_QUIET_END),
++	BCMEVENT_NAME(WLC_E_BEACON_RX),
++	BCMEVENT_NAME(WLC_E_LINK),
++	BCMEVENT_NAME(WLC_E_MIC_ERROR),
++	BCMEVENT_NAME(WLC_E_NDIS_LINK),
++	BCMEVENT_NAME(WLC_E_ROAM),
++	BCMEVENT_NAME(WLC_E_TXFAIL),
++	BCMEVENT_NAME(WLC_E_PMKID_CACHE),
++	BCMEVENT_NAME(WLC_E_RETROGRADE_TSF),
++	BCMEVENT_NAME(WLC_E_PRUNE),
++	BCMEVENT_NAME(WLC_E_AUTOAUTH),
++	BCMEVENT_NAME(WLC_E_EAPOL_MSG),
++	BCMEVENT_NAME(WLC_E_SCAN_COMPLETE),
++	BCMEVENT_NAME(WLC_E_ADDTS_IND),
++	BCMEVENT_NAME(WLC_E_DELTS_IND),
++	BCMEVENT_NAME(WLC_E_BCNSENT_IND),
++	BCMEVENT_NAME(WLC_E_BCNRX_MSG),
++	BCMEVENT_NAME(WLC_E_BCNLOST_MSG),
++	BCMEVENT_NAME(WLC_E_ROAM_PREP),
++	BCMEVENT_NAME(WLC_E_PFN_NET_FOUND),
++	BCMEVENT_NAME(WLC_E_PFN_SCAN_ALLGONE),
++	BCMEVENT_NAME(WLC_E_PFN_NET_LOST),
++	BCMEVENT_NAME(WLC_E_JOIN_START),
++	BCMEVENT_NAME(WLC_E_ROAM_START),
++	BCMEVENT_NAME(WLC_E_ASSOC_START),
++#if defined(IBSS_PEER_DISCOVERY_EVENT)
++	BCMEVENT_NAME(WLC_E_IBSS_ASSOC),
++#endif /* defined(IBSS_PEER_DISCOVERY_EVENT) */
++	BCMEVENT_NAME(WLC_E_RADIO),
++	BCMEVENT_NAME(WLC_E_PSM_WATCHDOG),
++	BCMEVENT_NAME(WLC_E_PROBREQ_MSG),
++	BCMEVENT_NAME(WLC_E_SCAN_CONFIRM_IND),
++	BCMEVENT_NAME(WLC_E_PSK_SUP),
++	BCMEVENT_NAME(WLC_E_COUNTRY_CODE_CHANGED),
++	BCMEVENT_NAME(WLC_E_EXCEEDED_MEDIUM_TIME),
++	BCMEVENT_NAME(WLC_E_ICV_ERROR),
++	BCMEVENT_NAME(WLC_E_UNICAST_DECODE_ERROR),
++	BCMEVENT_NAME(WLC_E_MULTICAST_DECODE_ERROR),
++	BCMEVENT_NAME(WLC_E_TRACE),
++	BCMEVENT_NAME(WLC_E_IF),
++#ifdef WLP2P
++	BCMEVENT_NAME(WLC_E_P2P_DISC_LISTEN_COMPLETE),
++#endif
++	BCMEVENT_NAME(WLC_E_RSSI),
++	BCMEVENT_NAME(WLC_E_PFN_SCAN_COMPLETE),
++	BCMEVENT_NAME(WLC_E_EXTLOG_MSG),
++	BCMEVENT_NAME(WLC_E_ACTION_FRAME),
++	BCMEVENT_NAME(WLC_E_ACTION_FRAME_RX),
++	BCMEVENT_NAME(WLC_E_ACTION_FRAME_COMPLETE),
++#ifdef BCMWAPI_WAI
++	BCMEVENT_NAME(WLC_E_WAI_STA_EVENT),
++	BCMEVENT_NAME(WLC_E_WAI_MSG),
++#endif /* BCMWAPI_WAI */
++	BCMEVENT_NAME(WLC_E_ESCAN_RESULT),
++	BCMEVENT_NAME(WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE),
++#ifdef WLP2P
++	BCMEVENT_NAME(WLC_E_PROBRESP_MSG),
++	BCMEVENT_NAME(WLC_E_P2P_PROBREQ_MSG),
++#endif
++#ifdef PROP_TXSTATUS
++	BCMEVENT_NAME(WLC_E_FIFO_CREDIT_MAP),
++#endif
++	BCMEVENT_NAME(WLC_E_WAKE_EVENT),
++	BCMEVENT_NAME(WLC_E_DCS_REQUEST),
++	BCMEVENT_NAME(WLC_E_RM_COMPLETE),
++#ifdef WLMEDIA_HTSF
++	BCMEVENT_NAME(WLC_E_HTSFSYNC),
++#endif
++	BCMEVENT_NAME(WLC_E_OVERLAY_REQ),
++	BCMEVENT_NAME(WLC_E_CSA_COMPLETE_IND),
++	BCMEVENT_NAME(WLC_E_EXCESS_PM_WAKE_EVENT),
++	BCMEVENT_NAME(WLC_E_PFN_SCAN_NONE),
++	BCMEVENT_NAME(WLC_E_PFN_SCAN_ALLGONE),
++#ifdef SOFTAP
++	BCMEVENT_NAME(WLC_E_GTK_PLUMBED),
++#endif
++	BCMEVENT_NAME(WLC_E_ASSOC_REQ_IE),
++	BCMEVENT_NAME(WLC_E_ASSOC_RESP_IE),
++	BCMEVENT_NAME(WLC_E_BEACON_FRAME_RX),
++#ifdef WLTDLS
++	BCMEVENT_NAME(WLC_E_TDLS_PEER_EVENT),
++#endif /* WLTDLS */
++	BCMEVENT_NAME(WLC_E_NATIVE),
++#ifdef WLPKTDLYSTAT
++	BCMEVENT_NAME(WLC_E_PKTDELAY_IND),
++#endif /* WLPKTDLYSTAT */
++	BCMEVENT_NAME(WLC_E_SERVICE_FOUND),
++	BCMEVENT_NAME(WLC_E_GAS_FRAGMENT_RX),
++	BCMEVENT_NAME(WLC_E_GAS_COMPLETE),
++	BCMEVENT_NAME(WLC_E_P2PO_ADD_DEVICE),
++	BCMEVENT_NAME(WLC_E_P2PO_DEL_DEVICE),
++#ifdef WLWNM
++	BCMEVENT_NAME(WLC_E_WNM_STA_SLEEP),
++#endif /* WLWNM */
++#if defined(WL_PROXDETECT)
++	BCMEVENT_NAME(WLC_E_PROXD),
++#endif
++	BCMEVENT_NAME(WLC_E_CCA_CHAN_QUAL),
++	BCMEVENT_NAME(WLC_E_BSSID),
++#ifdef PROP_TXSTATUS
++	BCMEVENT_NAME(WLC_E_BCMC_CREDIT_SUPPORT),
++#endif
++	BCMEVENT_NAME(WLC_E_PSTA_PRIMARY_INTF_IND),
++	BCMEVENT_NAME(WLC_E_TXFAIL_THRESH),
++#ifdef GSCAN_SUPPORT
++	BCMEVENT_NAME(WLC_E_PFN_GSCAN_FULL_RESULT),
++	BCMEVENT_NAME(WLC_E_PFN_SSID_EXT),
++#endif /* GSCAN_SUPPORT */
++#ifdef WLBSSLOAD_REPORT
++	BCMEVENT_NAME(WLC_E_BSS_LOAD),
++#endif
++#if defined(BT_WIFI_HANDOVER) || defined(WL_TBOW)
++	BCMEVENT_NAME(WLC_E_BT_WIFI_HANDOVER_REQ),
++#endif
++#ifdef WLFBT
++	BCMEVENT_NAME(WLC_E_FBT_AUTH_REQ_IND),
++#endif /* WLFBT */
++	BCMEVENT_NAME(WLC_E_AUTHORIZED),
++	BCMEVENT_NAME(WLC_E_PROBREQ_MSG_RX),
++	BCMEVENT_NAME(WLC_E_CSA_START_IND),
++	BCMEVENT_NAME(WLC_E_CSA_DONE_IND),
++	BCMEVENT_NAME(WLC_E_CSA_FAILURE_IND),
++	BCMEVENT_NAME(WLC_E_RMC_EVENT),
++	BCMEVENT_NAME(WLC_E_DPSTA_INTF_IND),
++	BCMEVENT_NAME(WLC_E_ALLOW_CREDIT_BORROW),
++	BCMEVENT_NAME(WLC_E_MSCH),
++	BCMEVENT_NAME(WLC_E_ULP),
++	BCMEVENT_NAME(WLC_E_PSK_AUTH),
++	BCMEVENT_NAME(WLC_E_SDB_TRANSITION),
++};
++
++
++const char *bcmevent_get_name(uint event_type)
++{
++	/* note:  first coded this as a static const but some
++	 * ROMs already have something called event_name so
++	 * changed it so we don't have a variable for the
++	 * 'unknown string
++	 */
++	const char *event_name = NULL;
++
++	uint idx;
++	for (idx = 0; idx < (uint)ARRAYSIZE(bcmevent_names); idx++) {
++
++		if (bcmevent_names[idx].event == event_type) {
++			event_name = bcmevent_names[idx].name;
++			break;
++		}
++	}
++
++	/* if we find an event name in the array, return it.
++	 * otherwise return unknown string.
++	 */
++	return ((event_name) ? event_name : "Unknown Event");
++}
++
++void
++wl_event_to_host_order(wl_event_msg_t * evt)
++{
++	/* Event struct members passed from dongle to host are stored in network
++	* byte order. Convert all members to host-order.
++	*/
++	evt->event_type = ntoh32(evt->event_type);
++	evt->flags = ntoh16(evt->flags);
++	evt->status = ntoh32(evt->status);
++	evt->reason = ntoh32(evt->reason);
++	evt->auth_type = ntoh32(evt->auth_type);
++	evt->datalen = ntoh32(evt->datalen);
++	evt->version = ntoh16(evt->version);
++}
++
++void
++wl_event_to_network_order(wl_event_msg_t * evt)
++{
++	/* Event struct members passed from dongle to host are stored in network
++	* byte order. Convert all members to host-order.
++	*/
++	evt->event_type = hton32(evt->event_type);
++	evt->flags = hton16(evt->flags);
++	evt->status = hton32(evt->status);
++	evt->reason = hton32(evt->reason);
++	evt->auth_type = hton32(evt->auth_type);
++	evt->datalen = hton32(evt->datalen);
++	evt->version = hton16(evt->version);
++}
++
++/*
++ * Validate if the event is proper and if valid copy event header to event.
++ * If proper event pointer is passed, to just validate, pass NULL to event.
++ *
++ * Return values are
++ *	BCME_OK - It is a BRCM event or BRCM dongle event
++ *	BCME_NOTFOUND - Not BRCM, not an event, may be okay
++ *	BCME_BADLEN - Bad length, should not process, just drop
++ */
++int
++is_wlc_event_frame(void *pktdata, uint pktlen, uint16 exp_usr_subtype,
++	bcm_event_msg_u_t *out_event)
++{
++	uint16 evlen = 0;	/* length in bcmeth_hdr */
++	uint16 subtype;
++	uint16 usr_subtype;
++	bcm_event_t *bcm_event;
++	uint8 *pktend;
++	uint8 *evend;
++	int err = BCME_OK;
++	uint32 data_len = 0; /* data length in bcm_event */
++
++	pktend = (uint8 *)pktdata + pktlen;
++	bcm_event = (bcm_event_t *)pktdata;
++
++	/* only care about 16-bit subtype / length versions */
++	if ((uint8 *)&bcm_event->bcm_hdr < pktend) {
++		uint8 short_subtype = *(uint8 *)&bcm_event->bcm_hdr;
++		if (!(short_subtype & 0x80)) {
++			err = BCME_NOTFOUND;
++			goto done;
++		}
++	}
++
++	/* must have both ether_header and bcmeth_hdr */
++	if (pktlen < OFFSETOF(bcm_event_t, event)) {
++		err = BCME_BADLEN;
++		goto done;
++	}
++
++	/* check length in bcmeth_hdr */
++
++	/* temporary - header length not always set properly. When the below
++	 * !BCMDONGLEHOST is in all branches that use trunk DHD, the code
++	 * under BCMDONGLEHOST can be removed.
++	 */
++	evlen = (uint16)(pktend - (uint8 *)&bcm_event->bcm_hdr.version);
++	evend = (uint8 *)&bcm_event->bcm_hdr.version + evlen;
++	if (evend != pktend) {
++		err = BCME_BADLEN;
++		goto done;
++	}
++
++	/* match on subtype, oui and usr subtype for BRCM events */
++	subtype = ntoh16_ua((void *)&bcm_event->bcm_hdr.subtype);
++	if (subtype != BCMILCP_SUBTYPE_VENDOR_LONG) {
++		err = BCME_NOTFOUND;
++		goto done;
++	}
++
++	if (bcmp(BRCM_OUI, &bcm_event->bcm_hdr.oui[0], DOT11_OUI_LEN)) {
++		err = BCME_NOTFOUND;
++		goto done;
++	}
++
++	/* if it is a bcm_event or bcm_dngl_event_t, validate it */
++	usr_subtype = ntoh16_ua((void *)&bcm_event->bcm_hdr.usr_subtype);
++	switch (usr_subtype) {
++	case BCMILCP_BCM_SUBTYPE_EVENT:
++		/* check that header length and pkt length are sufficient */
++		if ((pktlen < sizeof(bcm_event_t)) ||
++			(evend < ((uint8 *)bcm_event + sizeof(bcm_event_t)))) {
++			err = BCME_BADLEN;
++			goto done;
++		}
++
++		/* ensure data length in event is not beyond the packet. */
++		data_len = ntoh32_ua((void *)&bcm_event->event.datalen);
++		if ((sizeof(bcm_event_t) + data_len +
++			BCMILCP_BCM_SUBTYPE_EVENT_DATA_PAD) != pktlen) {
++			err = BCME_BADLEN;
++			goto done;
++		}
++
++		if (exp_usr_subtype && (exp_usr_subtype != usr_subtype)) {
++			err = BCME_NOTFOUND;
++			goto done;
++		}
++
++		if (out_event) {
++			/* ensure BRCM event pkt aligned */
++			memcpy(&out_event->event, &bcm_event->event, sizeof(wl_event_msg_t));
++		}
++
++		break;
++
++	case BCMILCP_BCM_SUBTYPE_DNGLEVENT:
++#if defined(DNGL_EVENT_SUPPORT)
++		if ((pktlen < sizeof(bcm_dngl_event_t)) ||
++			(evend < ((uint8 *)bcm_event + sizeof(bcm_dngl_event_t)))) {
++			err = BCME_BADLEN;
++			goto done;
++		}
++
++		/* ensure data length in event is not beyond the packet. */
++		data_len = ntoh16_ua((void *)&((bcm_dngl_event_t *)pktdata)->dngl_event.datalen);
++		if ((sizeof(bcm_dngl_event_t) + data_len +
++			BCMILCP_BCM_SUBTYPE_EVENT_DATA_PAD) != pktlen) {
++			err = BCME_BADLEN;
++			goto done;
++		}
++
++		if (exp_usr_subtype && (exp_usr_subtype != usr_subtype)) {
++			err = BCME_NOTFOUND;
++			goto done;
++		}
++
++		if (out_event) {
++			/* ensure BRCM dngl event pkt aligned */
++			memcpy(&out_event->dngl_event, &((bcm_dngl_event_t *)pktdata)->dngl_event,
++				sizeof(bcm_dngl_event_msg_t));
++		}
++
++		break;
++#else
++		err = BCME_UNSUPPORTED;
++		break;
++#endif 
++
++	default:
++		err = BCME_NOTFOUND;
++		goto done;
++	}
++
++	BCM_REFERENCE(data_len);
++done:
++	return err;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/bcmsdh.c b/module_drivers/drivers/net/wireless/bcmdhd/bcmsdh.c
+new file mode 100644
+index 000000000..a4144efe3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/bcmsdh.c
+@@ -0,0 +1,847 @@
++/*
++ *  BCMSDH interface glue
++ *  implement bcmsdh API for SDIOH driver
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmsdh.c 671319 2016-11-21 14:27:29Z $
++ */
++
++/**
++ * @file bcmsdh.c
++ */
++
++/* ****************** BCMSDH Interface Functions *************************** */
++
++#include <typedefs.h>
++#include <bcmdevs.h>
++#include <bcmendian.h>
++#include <bcmutils.h>
++#include <hndsoc.h>
++#include <siutils.h>
++#include <osl.h>
++
++#include <bcmsdh.h>	/* BRCM API for SDIO clients (such as wl, dhd) */
++#include <bcmsdbus.h>	/* common SDIO/controller interface */
++#include <sbsdio.h>	/* SDIO device core hardware definitions. */
++#include <sdio.h>	/* SDIO Device and Protocol Specs */
++
++#if defined(BT_OVER_SDIO)
++#include <dhd_bt_interface.h>
++#endif /* defined (BT_OVER_SDIO) */
++
++#define SDIOH_API_ACCESS_RETRY_LIMIT	2
++const uint bcmsdh_msglevel = BCMSDH_ERROR_VAL;
++
++/* local copy of bcm sd handler */
++bcmsdh_info_t * l_bcmsdh = NULL;
++
++#if defined(BT_OVER_SDIO)
++struct sdio_func *func_f3 = NULL;
++static f3intr_handler processf3intr = NULL;
++static dhd_hang_notification process_dhd_hang_notification = NULL;
++static dhd_hang_state_t g_dhd_hang_state = NO_HANG_STATE;
++#endif /* defined (BT_OVER_SDIO) */
++
++
++#if defined(OOB_INTR_ONLY) && defined(HW_OOB) || defined(FORCE_WOWLAN)
++extern int
++sdioh_enable_hw_oob_intr(void *sdioh, bool enable);
++
++void
++bcmsdh_enable_hw_oob_intr(bcmsdh_info_t *sdh, bool enable)
++{
++	sdioh_enable_hw_oob_intr(sdh->sdioh, enable);
++}
++#endif
++
++#if defined(BT_OVER_SDIO)
++void bcmsdh_btsdio_process_hang_state(dhd_hang_state_t new_state)
++{
++	bool state_change = false;
++
++	BCMSDH_ERROR(("%s: DHD hang state changed - [%d] -> [%d]\n",
++		__FUNCTION__, g_dhd_hang_state, new_state));
++
++	if (g_dhd_hang_state == new_state)
++		return;
++
++	switch (g_dhd_hang_state) {
++		case NO_HANG_STATE:
++			if (HANG_START_STATE == new_state)
++				state_change = true;
++		break;
++
++		case HANG_START_STATE:
++			if (HANG_RECOVERY_STATE == new_state ||
++				NO_HANG_STATE == new_state)
++				state_change = true;
++		break;
++
++		case HANG_RECOVERY_STATE:
++			if (NO_HANG_STATE == new_state)
++				state_change = true;
++		break;
++
++		default:
++			BCMSDH_ERROR(("%s: Unhandled Hang state\n", __FUNCTION__));
++		break;
++	}
++
++	if (!state_change) {
++		BCMSDH_ERROR(("%s: Hang state cannot be changed\n", __FUNCTION__));
++		return;
++	}
++
++	g_dhd_hang_state = new_state;
++}
++
++void bcmsdh_btsdio_process_f3_intr(void)
++{
++	if (processf3intr && (g_dhd_hang_state == NO_HANG_STATE))
++		processf3intr(func_f3);
++}
++
++void bcmsdh_btsdio_process_dhd_hang_notification(bool wifi_recovery_completed)
++{
++	bcmsdh_btsdio_process_hang_state(HANG_START_STATE);
++
++	if (process_dhd_hang_notification)
++		process_dhd_hang_notification(func_f3, wifi_recovery_completed);
++
++	/* WiFi was off, so HANG_RECOVERY_STATE is not needed */
++	if (wifi_recovery_completed)
++		bcmsdh_btsdio_process_hang_state(NO_HANG_STATE);
++	else {
++		bcmsdh_btsdio_process_hang_state(HANG_RECOVERY_STATE);
++	}
++}
++
++void bcmsdh_btsdio_interface_init(struct sdio_func *func,
++	f3intr_handler f3intr_fun, dhd_hang_notification hang_notification)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)l_bcmsdh;
++	BCMSDH_INFO(("%s: func %p \n", __FUNCTION__, func));
++	func_f3 = func;
++	processf3intr = f3intr_fun;
++	sdioh_sdmmc_card_enable_func_f3(bcmsdh->sdioh, func);
++	process_dhd_hang_notification = hang_notification;
++
++} EXPORT_SYMBOL(bcmsdh_btsdio_interface_init);
++#endif /* defined (BT_OVER_SDIO) */
++
++/* Attach BCMSDH layer to SDIO Host Controller Driver
++ *
++ * @param osh OSL Handle.
++ * @param cfghdl Configuration Handle.
++ * @param regsva Virtual address of controller registers.
++ * @param irq Interrupt number of SDIO controller.
++ *
++ * @return bcmsdh_info_t Handle to BCMSDH context.
++ */
++bcmsdh_info_t *
++bcmsdh_attach(osl_t *osh, void *sdioh, ulong *regsva)
++{
++	bcmsdh_info_t *bcmsdh;
++
++	if ((bcmsdh = (bcmsdh_info_t *)MALLOC(osh, sizeof(bcmsdh_info_t))) == NULL) {
++		BCMSDH_ERROR(("bcmsdh_attach: out of memory, malloced %d bytes\n", MALLOCED(osh)));
++		return NULL;
++	}
++	bzero((char *)bcmsdh, sizeof(bcmsdh_info_t));
++	bcmsdh->sdioh = sdioh;
++	bcmsdh->osh = osh;
++	bcmsdh->init_success = TRUE;
++	*regsva = SI_ENUM_BASE;
++
++	bcmsdh_force_sbwad_calc(bcmsdh, FALSE);
++
++	/* Report the BAR, to fix if needed */
++	bcmsdh->sbwad = SI_ENUM_BASE;
++
++	/* save the handler locally */
++	l_bcmsdh = bcmsdh;
++
++	return bcmsdh;
++}
++
++int
++bcmsdh_detach(osl_t *osh, void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	if (bcmsdh != NULL) {
++		MFREE(osh, bcmsdh, sizeof(bcmsdh_info_t));
++	}
++
++	l_bcmsdh = NULL;
++
++	return 0;
++}
++
++int
++bcmsdh_iovar_op(void *sdh, const char *name,
++                void *params, int plen, void *arg, int len, bool set)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	return sdioh_iovar_op(bcmsdh->sdioh, name, params, plen, arg, len, set);
++}
++
++bool
++bcmsdh_intr_query(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	bool on;
++
++	ASSERT(bcmsdh);
++	status = sdioh_interrupt_query(bcmsdh->sdioh, &on);
++	if (SDIOH_API_SUCCESS(status))
++		return FALSE;
++	else
++		return on;
++}
++
++int
++bcmsdh_intr_enable(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	ASSERT(bcmsdh);
++
++	status = sdioh_interrupt_set(bcmsdh->sdioh, TRUE);
++	return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
++}
++
++int
++bcmsdh_intr_disable(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	ASSERT(bcmsdh);
++
++	status = sdioh_interrupt_set(bcmsdh->sdioh, FALSE);
++	return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
++}
++
++int
++bcmsdh_intr_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	ASSERT(bcmsdh);
++
++	status = sdioh_interrupt_register(bcmsdh->sdioh, fn, argh);
++	return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
++}
++
++int
++bcmsdh_intr_dereg(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	ASSERT(bcmsdh);
++
++	status = sdioh_interrupt_deregister(bcmsdh->sdioh);
++	return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
++}
++
++#if defined(DHD_DEBUG)
++bool
++bcmsdh_intr_pending(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	ASSERT(sdh);
++	return sdioh_interrupt_pending(bcmsdh->sdioh);
++}
++#endif
++
++
++int
++bcmsdh_devremove_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh)
++{
++	ASSERT(sdh);
++
++	/* don't support yet */
++	return BCME_UNSUPPORTED;
++}
++
++/**
++ * Read from SDIO Configuration Space
++ * @param sdh SDIO Host context.
++ * @param func_num Function number to read from.
++ * @param addr Address to read from.
++ * @param err Error return.
++ * @return value read from SDIO configuration space.
++ */
++uint8
++bcmsdh_cfg_read(void *sdh, uint fnc_num, uint32 addr, int *err)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
++	int32 retry = 0;
++#endif
++	uint8 data = 0;
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	ASSERT(bcmsdh->init_success);
++
++#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
++	do {
++		if (retry)	/* wait for 1 ms till bus get settled down */
++			OSL_DELAY(1000);
++#endif
++	status = sdioh_cfg_read(bcmsdh->sdioh, fnc_num, addr, (uint8 *)&data);
++#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
++	} while (!SDIOH_API_SUCCESS(status) && (retry++ < SDIOH_API_ACCESS_RETRY_LIMIT));
++#endif
++	if (err)
++		*err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
++
++	BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, uint8data = 0x%x\n", __FUNCTION__,
++	            fnc_num, addr, data));
++
++	return data;
++} EXPORT_SYMBOL(bcmsdh_cfg_read);
++
++void
++bcmsdh_cfg_write(void *sdh, uint fnc_num, uint32 addr, uint8 data, int *err)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
++	int32 retry = 0;
++#endif
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	ASSERT(bcmsdh->init_success);
++
++#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
++	do {
++		if (retry)	/* wait for 1 ms till bus get settled down */
++			OSL_DELAY(1000);
++#endif
++	status = sdioh_cfg_write(bcmsdh->sdioh, fnc_num, addr, (uint8 *)&data);
++#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
++	} while (!SDIOH_API_SUCCESS(status) && (retry++ < SDIOH_API_ACCESS_RETRY_LIMIT));
++#endif
++	if (err)
++		*err = SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR;
++
++	BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, uint8data = 0x%x\n", __FUNCTION__,
++	            fnc_num, addr, data));
++} EXPORT_SYMBOL(bcmsdh_cfg_write);
++
++uint32
++bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr, int *err)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	uint32 data = 0;
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	ASSERT(bcmsdh->init_success);
++
++	status = sdioh_request_word(bcmsdh->sdioh, SDIOH_CMD_TYPE_NORMAL, SDIOH_READ, fnc_num,
++	                            addr, &data, 4);
++
++	if (err)
++		*err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
++
++	BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, uint32data = 0x%x\n", __FUNCTION__,
++	            fnc_num, addr, data));
++
++	return data;
++}
++
++void
++bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr, uint32 data, int *err)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	ASSERT(bcmsdh->init_success);
++
++	status = sdioh_request_word(bcmsdh->sdioh, SDIOH_CMD_TYPE_NORMAL, SDIOH_WRITE, fnc_num,
++	                            addr, &data, 4);
++
++	if (err)
++		*err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
++
++	BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, uint32data = 0x%x\n", __FUNCTION__, fnc_num,
++	             addr, data));
++}
++
++
++int
++bcmsdh_cis_read(void *sdh, uint func, uint8 *cis, uint length)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++
++	uint8 *tmp_buf, *tmp_ptr;
++	uint8 *ptr;
++	bool ascii = func & ~0xf;
++	func &= 0x7;
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	ASSERT(bcmsdh->init_success);
++	ASSERT(cis);
++	ASSERT(length <= SBSDIO_CIS_SIZE_LIMIT);
++
++	status = sdioh_cis_read(bcmsdh->sdioh, func, cis, length);
++
++	if (ascii) {
++		/* Move binary bits to tmp and format them into the provided buffer. */
++		if ((tmp_buf = (uint8 *)MALLOC(bcmsdh->osh, length)) == NULL) {
++			BCMSDH_ERROR(("%s: out of memory\n", __FUNCTION__));
++			return BCME_NOMEM;
++		}
++		bcopy(cis, tmp_buf, length);
++		for (tmp_ptr = tmp_buf, ptr = cis; ptr < (cis + length - 4); tmp_ptr++) {
++			ptr += snprintf((char*)ptr, (cis + length - ptr - 4),
++				"%.2x ", *tmp_ptr & 0xff);
++			if ((((tmp_ptr - tmp_buf) + 1) & 0xf) == 0)
++				ptr += snprintf((char *)ptr, (cis + length - ptr -4), "\n");
++		}
++		MFREE(bcmsdh->osh, tmp_buf, length);
++	}
++
++	return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
++}
++
++int
++bcmsdh_cisaddr_read(void *sdh, uint func, uint8 *cisd, uint32 offset)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++
++	func &= 0x7;
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	ASSERT(bcmsdh->init_success);
++	ASSERT(cisd);
++
++	status = sdioh_cisaddr_read(bcmsdh->sdioh, func, cisd, offset);
++
++	return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
++}
++
++
++int
++bcmsdhsdio_set_sbaddr_window(void *sdh, uint32 address, bool force_set)
++{
++	int err = 0;
++	uint bar0 = address & ~SBSDIO_SB_OFT_ADDR_MASK;
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	if (bar0 != bcmsdh->sbwad || force_set) {
++		bcmsdh_cfg_write(bcmsdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
++			(address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
++		if (!err)
++			bcmsdh_cfg_write(bcmsdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
++				(address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
++		if (!err)
++			bcmsdh_cfg_write(bcmsdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
++				(address >> 24) & SBSDIO_SBADDRHIGH_MASK, &err);
++
++		if (!err)
++			bcmsdh->sbwad = bar0;
++		else
++			/* invalidate cached window var */
++			bcmsdh->sbwad = 0;
++
++	}
++
++	return err;
++}
++
++uint32
++bcmsdh_reg_read(void *sdh, uintptr addr, uint size)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	uint32 word = 0;
++
++	BCMSDH_INFO(("%s:fun = 1, addr = 0x%x\n", __FUNCTION__, (unsigned int)addr));
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	ASSERT(bcmsdh->init_success);
++
++	if (bcmsdhsdio_set_sbaddr_window(bcmsdh, addr, FALSE)) {
++		bcmsdh->regfail = TRUE; // terence 20130621: prevent dhd_dpc in dead lock
++		return 0xFFFFFFFF;
++	}
++
++	addr &= SBSDIO_SB_OFT_ADDR_MASK;
++	if (size == 4)
++		addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
++
++	status = sdioh_request_word(bcmsdh->sdioh, SDIOH_CMD_TYPE_NORMAL,
++		SDIOH_READ, SDIO_FUNC_1, addr, &word, size);
++
++	bcmsdh->regfail = !(SDIOH_API_SUCCESS(status));
++
++	BCMSDH_INFO(("uint32data = 0x%x\n", word));
++
++	/* if ok, return appropriately masked word */
++	if (SDIOH_API_SUCCESS(status)) {
++		switch (size) {
++			case sizeof(uint8):
++				return (word & 0xff);
++			case sizeof(uint16):
++				return (word & 0xffff);
++			case sizeof(uint32):
++				return word;
++			default:
++				bcmsdh->regfail = TRUE;
++
++		}
++	}
++
++	/* otherwise, bad sdio access or invalid size */
++	BCMSDH_ERROR(("%s: error reading addr 0x%x size %d\n",
++		__FUNCTION__, (unsigned int)addr, size));
++	return 0xFFFFFFFF;
++}
++
++uint32
++bcmsdh_reg_write(void *sdh, uintptr addr, uint size, uint32 data)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	int err = 0;
++
++	BCMSDH_INFO(("%s:fun = 1, addr = 0x%x, uint%ddata = 0x%x\n",
++	             __FUNCTION__, (unsigned int)addr, size*8, data));
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	ASSERT(bcmsdh->init_success);
++
++	if ((err = bcmsdhsdio_set_sbaddr_window(bcmsdh, addr, bcmsdh->force_sbwad_calc))) {
++		bcmsdh->regfail = TRUE; // terence 20130621:
++		return err;
++	}
++
++	addr &= SBSDIO_SB_OFT_ADDR_MASK;
++	if (size == 4)
++		addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
++	status = sdioh_request_word(bcmsdh->sdioh, SDIOH_CMD_TYPE_NORMAL, SDIOH_WRITE, SDIO_FUNC_1,
++	                            addr, &data, size);
++	bcmsdh->regfail = !(SDIOH_API_SUCCESS(status));
++
++	if (SDIOH_API_SUCCESS(status))
++		return 0;
++
++	BCMSDH_ERROR(("%s: error writing 0x%08x to addr 0x%04x size %d\n",
++	              __FUNCTION__, data, (unsigned int)addr, size));
++	return 0xFFFFFFFF;
++}
++
++bool
++bcmsdh_regfail(void *sdh)
++{
++	return ((bcmsdh_info_t *)sdh)->regfail;
++}
++
++int
++bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags,
++                uint8 *buf, uint nbytes, void *pkt,
++                bcmsdh_cmplt_fn_t complete_fn, void *handle)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	uint incr_fix;
++	uint width;
++	int err = 0;
++
++	ASSERT(bcmsdh);
++	ASSERT(bcmsdh->init_success);
++
++	BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, size = %d\n",
++	             __FUNCTION__, fn, addr, nbytes));
++
++	/* Async not implemented yet */
++	ASSERT(!(flags & SDIO_REQ_ASYNC));
++	if (flags & SDIO_REQ_ASYNC)
++		return BCME_UNSUPPORTED;
++
++	if ((err = bcmsdhsdio_set_sbaddr_window(bcmsdh, addr, FALSE)))
++		return err;
++
++	addr &= SBSDIO_SB_OFT_ADDR_MASK;
++
++	incr_fix = (flags & SDIO_REQ_FIXED) ? SDIOH_DATA_FIX : SDIOH_DATA_INC;
++	width = (flags & SDIO_REQ_4BYTE) ? 4 : 2;
++	if (width == 4)
++		addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
++
++	status = sdioh_request_buffer(bcmsdh->sdioh, SDIOH_DATA_PIO, incr_fix,
++	                              SDIOH_READ, fn, addr, width, nbytes, buf, pkt);
++
++	return (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
++}
++
++int
++bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags,
++                uint8 *buf, uint nbytes, void *pkt,
++                bcmsdh_cmplt_fn_t complete_fn, void *handle)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	uint incr_fix;
++	uint width;
++	int err = 0;
++
++	ASSERT(bcmsdh);
++	ASSERT(bcmsdh->init_success);
++
++	BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, size = %d\n",
++	            __FUNCTION__, fn, addr, nbytes));
++
++	/* Async not implemented yet */
++	ASSERT(!(flags & SDIO_REQ_ASYNC));
++	if (flags & SDIO_REQ_ASYNC)
++		return BCME_UNSUPPORTED;
++
++	if ((err = bcmsdhsdio_set_sbaddr_window(bcmsdh, addr, FALSE)))
++		return err;
++
++	addr &= SBSDIO_SB_OFT_ADDR_MASK;
++
++	incr_fix = (flags & SDIO_REQ_FIXED) ? SDIOH_DATA_FIX : SDIOH_DATA_INC;
++	width = (flags & SDIO_REQ_4BYTE) ? 4 : 2;
++	if (width == 4)
++		addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
++
++	status = sdioh_request_buffer(bcmsdh->sdioh, SDIOH_DATA_PIO, incr_fix,
++	                              SDIOH_WRITE, fn, addr, width, nbytes, buf, pkt);
++
++	return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
++}
++
++int
++bcmsdh_rwdata(void *sdh, uint rw, uint32 addr, uint8 *buf, uint nbytes)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++
++	ASSERT(bcmsdh);
++	ASSERT(bcmsdh->init_success);
++	ASSERT((addr & SBSDIO_SBWINDOW_MASK) == 0);
++
++	addr &= SBSDIO_SB_OFT_ADDR_MASK;
++	addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
++
++	status = sdioh_request_buffer(bcmsdh->sdioh, SDIOH_DATA_PIO, SDIOH_DATA_INC,
++	                              (rw ? SDIOH_WRITE : SDIOH_READ), SDIO_FUNC_1,
++	                              addr, 4, nbytes, buf, NULL);
++
++	return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
++}
++
++int
++bcmsdh_abort(void *sdh, uint fn)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	return sdioh_abort(bcmsdh->sdioh, fn);
++}
++
++int
++bcmsdh_start(void *sdh, int stage)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	return sdioh_start(bcmsdh->sdioh, stage);
++}
++
++int
++bcmsdh_stop(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	return sdioh_stop(bcmsdh->sdioh);
++}
++
++int
++bcmsdh_waitlockfree(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	return sdioh_waitlockfree(bcmsdh->sdioh);
++}
++
++int
++bcmsdh_query_device(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	bcmsdh->vendevid = (VENDOR_BROADCOM << 16) | 0;
++	return (bcmsdh->vendevid);
++}
++
++uint
++bcmsdh_query_iofnum(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	return (sdioh_query_iofnum(bcmsdh->sdioh));
++}
++
++int
++bcmsdh_reset(bcmsdh_info_t *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	return sdioh_sdio_reset(bcmsdh->sdioh);
++}
++
++void *bcmsdh_get_sdioh(bcmsdh_info_t *sdh)
++{
++	ASSERT(sdh);
++	return sdh->sdioh;
++}
++
++/* Function to pass device-status bits to DHD. */
++uint32
++bcmsdh_get_dstatus(void *sdh)
++{
++	return 0;
++}
++uint32
++bcmsdh_cur_sbwad(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	return (bcmsdh->sbwad);
++}
++
++/* example usage: if force is TRUE, forces the bcmsdhsdio_set_sbaddr_window to
++ * calculate sbwad always instead of caching.
++ */
++void
++bcmsdh_force_sbwad_calc(void *sdh, bool force)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++	bcmsdh->force_sbwad_calc = force;
++}
++
++void
++bcmsdh_chipinfo(void *sdh, uint32 chip, uint32 chiprev)
++{
++	return;
++}
++
++
++int
++bcmsdh_sleep(void *sdh, bool enab)
++{
++#ifdef SDIOH_SLEEP_ENABLED
++	bcmsdh_info_t *p = (bcmsdh_info_t *)sdh;
++	sdioh_info_t *sd = (sdioh_info_t *)(p->sdioh);
++
++	return sdioh_sleep(sd, enab);
++#else
++	return BCME_UNSUPPORTED;
++#endif
++}
++
++int
++bcmsdh_gpio_init(void *sdh)
++{
++	bcmsdh_info_t *p = (bcmsdh_info_t *)sdh;
++	sdioh_info_t *sd = (sdioh_info_t *)(p->sdioh);
++
++	return sdioh_gpio_init(sd);
++}
++
++bool
++bcmsdh_gpioin(void *sdh, uint32 gpio)
++{
++	bcmsdh_info_t *p = (bcmsdh_info_t *)sdh;
++	sdioh_info_t *sd = (sdioh_info_t *)(p->sdioh);
++
++	return sdioh_gpioin(sd, gpio);
++}
++
++int
++bcmsdh_gpioouten(void *sdh, uint32 gpio)
++{
++	bcmsdh_info_t *p = (bcmsdh_info_t *)sdh;
++	sdioh_info_t *sd = (sdioh_info_t *)(p->sdioh);
++
++	return sdioh_gpioouten(sd, gpio);
++}
++
++int
++bcmsdh_gpioout(void *sdh, uint32 gpio, bool enab)
++{
++	bcmsdh_info_t *p = (bcmsdh_info_t *)sdh;
++	sdioh_info_t *sd = (sdioh_info_t *)(p->sdioh);
++
++	return sdioh_gpioout(sd, gpio, enab);
++}
++
++uint
++bcmsdh_set_mode(void *sdh, uint mode) 
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	return (sdioh_set_mode(bcmsdh->sdioh, mode));
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/bcmsdh_linux.c b/module_drivers/drivers/net/wireless/bcmdhd/bcmsdh_linux.c
+new file mode 100644
+index 000000000..fd6b757cd
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/bcmsdh_linux.c
+@@ -0,0 +1,517 @@
++/*
++ * SDIO access interface for drivers - linux specific (pci only)
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmsdh_linux.c 672609 2016-11-29 07:00:46Z $
++ */
++
++/**
++ * @file bcmsdh_linux.c
++ */
++
++#define __UNDEF_NO_VERSION__
++
++#include <typedefs.h>
++#include <linuxver.h>
++#include <linux/pci.h>
++#include <linux/completion.h>
++
++#include <osl.h>
++#include <pcicfg.h>
++#include <bcmdefs.h>
++#include <bcmdevs.h>
++#include <linux/irq.h>
++extern void dhdsdio_isr(void * args);
++#include <bcmutils.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#if defined(CONFIG_ARCH_ODIN)
++#include <linux/platform_data/gpio-odin.h>
++#endif /* defined(CONFIG_ARCH_ODIN) */
++#include <dhd_linux.h>
++
++/* driver info, initialized when bcmsdh_register is called */
++static bcmsdh_driver_t drvinfo = {NULL, NULL, NULL, NULL};
++
++typedef enum {
++	DHD_INTR_INVALID = 0,
++	DHD_INTR_INBAND,
++	DHD_INTR_HWOOB,
++	DHD_INTR_SWOOB
++} DHD_HOST_INTR_TYPE;
++
++/* the BCMSDH module comprises the generic part (bcmsdh.c) and OS specific layer (e.g.
++ * bcmsdh_linux.c). Put all OS specific variables (e.g. irq number and flags) here rather
++ * than in the common structure bcmsdh_info. bcmsdh_info only keeps a handle (os_ctx) to this
++ * structure.
++ */
++typedef struct bcmsdh_os_info {
++	DHD_HOST_INTR_TYPE	intr_type;
++	int			oob_irq_num;	/* valid when hardware or software oob in use */
++	unsigned long		oob_irq_flags;	/* valid when hardware or software oob in use */
++	bool			oob_irq_registered;
++	bool			oob_irq_enabled;
++	bool			oob_irq_wake_enabled;
++	spinlock_t		oob_irq_spinlock;
++	bcmsdh_cb_fn_t		oob_irq_handler;
++	void			*oob_irq_handler_context;
++	void			*context;	/* context returned from upper layer */
++	void			*sdioh;		/* handle to lower layer (sdioh) */
++	void			*dev;		/* handle to the underlying device */
++	bool			dev_wake_enabled;
++} bcmsdh_os_info_t;
++
++/* debugging macros */
++#define SDLX_ERR(x) printf x
++#define SDLX_MSG(x) printf x
++
++/**
++ * Checks to see if vendor and device IDs match a supported SDIO Host Controller.
++ */
++bool
++bcmsdh_chipmatch(uint16 vendor, uint16 device)
++{
++	/* Add other vendors and devices as required */
++
++#ifdef BCMSDIOH_STD
++	/* Check for Arasan host controller */
++	if (vendor == VENDOR_SI_IMAGE) {
++		return (TRUE);
++	}
++	/* Check for BRCM 27XX Standard host controller */
++	if (device == BCM27XX_SDIOH_ID && vendor == VENDOR_BROADCOM) {
++		return (TRUE);
++	}
++	/* Check for BRCM Standard host controller */
++	if (device == SDIOH_FPGA_ID && vendor == VENDOR_BROADCOM) {
++		return (TRUE);
++	}
++	/* Check for TI PCIxx21 Standard host controller */
++	if (device == PCIXX21_SDIOH_ID && vendor == VENDOR_TI) {
++		return (TRUE);
++	}
++	if (device == PCIXX21_SDIOH0_ID && vendor == VENDOR_TI) {
++		return (TRUE);
++	}
++	/* Ricoh R5C822 Standard SDIO Host */
++	if (device == R5C822_SDIOH_ID && vendor == VENDOR_RICOH) {
++		return (TRUE);
++	}
++	/* JMicron Standard SDIO Host */
++	if (device == JMICRON_SDIOH_ID && vendor == VENDOR_JMICRON) {
++		return (TRUE);
++	}
++
++#endif /* BCMSDIOH_STD */
++#ifdef BCMSDIOH_SPI
++	/* This is the PciSpiHost. */
++	if (device == SPIH_FPGA_ID && vendor == VENDOR_BROADCOM) {
++		printf("Found PCI SPI Host Controller\n");
++		return (TRUE);
++	}
++
++#endif /* BCMSDIOH_SPI */
++
++	return (FALSE);
++}
++
++void* bcmsdh_probe(osl_t *osh, void *dev, void *sdioh, void *adapter_info, uint bus_type,
++	uint bus_num, uint slot_num)
++{
++	ulong regs;
++	bcmsdh_info_t *bcmsdh;
++	uint32 vendevid;
++	bcmsdh_os_info_t *bcmsdh_osinfo = NULL;
++
++	bcmsdh = bcmsdh_attach(osh, sdioh, &regs);
++	if (bcmsdh == NULL) {
++		SDLX_ERR(("%s: bcmsdh_attach failed\n", __FUNCTION__));
++		goto err;
++	}
++	bcmsdh_osinfo = MALLOC(osh, sizeof(bcmsdh_os_info_t));
++	if (bcmsdh_osinfo == NULL) {
++		SDLX_ERR(("%s: failed to allocate bcmsdh_os_info_t\n", __FUNCTION__));
++		goto err;
++	}
++	bzero((char *)bcmsdh_osinfo, sizeof(bcmsdh_os_info_t));
++	bcmsdh->os_cxt = bcmsdh_osinfo;
++	bcmsdh_osinfo->sdioh = sdioh;
++	bcmsdh_osinfo->dev = dev;
++	osl_set_bus_handle(osh, bcmsdh);
++
++#if !defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++	if (dev && device_init_wakeup(dev, true) == 0)
++		bcmsdh_osinfo->dev_wake_enabled = TRUE;
++#endif /* !defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36)) */
++
++#if defined(OOB_INTR_ONLY)
++	spin_lock_init(&bcmsdh_osinfo->oob_irq_spinlock);
++	/* Get customer specific OOB IRQ parametres: IRQ number as IRQ type */
++	bcmsdh_osinfo->oob_irq_num = wifi_platform_get_irq_number(adapter_info,
++		&bcmsdh_osinfo->oob_irq_flags);
++	if  (bcmsdh_osinfo->oob_irq_num < 0) {
++		SDLX_ERR(("%s: Host OOB irq is not defined\n", __FUNCTION__));
++		goto err;
++	}
++#endif /* defined(BCMLXSDMMC) */
++
++	/* Read the vendor/device ID from the CIS */
++	vendevid = bcmsdh_query_device(bcmsdh);
++	/* try to attach to the target device */
++	bcmsdh_osinfo->context = drvinfo.probe((vendevid >> 16), (vendevid & 0xFFFF), bus_num,
++		slot_num, 0, bus_type, (void *)regs, osh, bcmsdh);
++	if (bcmsdh_osinfo->context == NULL) {
++		SDLX_ERR(("%s: device attach failed\n", __FUNCTION__));
++		goto err;
++	}
++
++	return bcmsdh;
++
++	/* error handling */
++err:
++	if (bcmsdh != NULL)
++		bcmsdh_detach(osh, bcmsdh);
++	if (bcmsdh_osinfo != NULL)
++		MFREE(osh, bcmsdh_osinfo, sizeof(bcmsdh_os_info_t));
++	return NULL;
++}
++
++int bcmsdh_remove(bcmsdh_info_t *bcmsdh)
++{
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++
++#if !defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++	if (bcmsdh_osinfo->dev)
++		device_init_wakeup(bcmsdh_osinfo->dev, false);
++	bcmsdh_osinfo->dev_wake_enabled = FALSE;
++#endif /* !defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36)) */
++
++	drvinfo.remove(bcmsdh_osinfo->context);
++	MFREE(bcmsdh->osh, bcmsdh->os_cxt, sizeof(bcmsdh_os_info_t));
++	bcmsdh_detach(bcmsdh->osh, bcmsdh);
++
++	return 0;
++}
++
++#ifdef DHD_WAKE_STATUS
++int bcmsdh_get_total_wake(bcmsdh_info_t *bcmsdh)
++{
++	return bcmsdh->total_wake_count;
++}
++
++int bcmsdh_set_get_wake(bcmsdh_info_t *bcmsdh, int flag)
++{
++#if defined(OOB_INTR_ONLY)
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++	unsigned long flags;
++#endif
++	int ret = 0;
++
++#if defined(OOB_INTR_ONLY)
++	spin_lock_irqsave(&bcmsdh_osinfo->oob_irq_spinlock, flags);
++
++	ret = bcmsdh->pkt_wake;
++	bcmsdh->total_wake_count += flag;
++	bcmsdh->pkt_wake = flag;
++
++	spin_unlock_irqrestore(&bcmsdh_osinfo->oob_irq_spinlock, flags);
++#endif
++	return ret;
++}
++#endif /* DHD_WAKE_STATUS */
++
++int bcmsdh_suspend(bcmsdh_info_t *bcmsdh)
++{
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++
++	if (drvinfo.suspend && drvinfo.suspend(bcmsdh_osinfo->context))
++		return -EBUSY;
++	return 0;
++}
++
++int bcmsdh_resume(bcmsdh_info_t *bcmsdh)
++{
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++
++	if (drvinfo.resume)
++		return drvinfo.resume(bcmsdh_osinfo->context);
++	return 0;
++}
++
++extern int bcmsdh_register_client_driver(void);
++extern void bcmsdh_unregister_client_driver(void);
++extern int sdio_func_reg_notify(void* semaphore);
++extern void sdio_func_unreg_notify(void);
++
++#if defined(BCMLXSDMMC)
++int bcmsdh_reg_sdio_notify(void* semaphore)
++{
++	return sdio_func_reg_notify(semaphore);
++}
++
++void bcmsdh_unreg_sdio_notify(void)
++{
++	sdio_func_unreg_notify();
++}
++#endif /* defined(BCMLXSDMMC) */
++
++int
++bcmsdh_register(bcmsdh_driver_t *driver)
++{
++	int error = 0;
++
++	drvinfo = *driver;
++	SDLX_MSG(("%s: register client driver\n", __FUNCTION__));
++	error = bcmsdh_register_client_driver();
++	if (error)
++		SDLX_ERR(("%s: failed %d\n", __FUNCTION__, error));
++
++	return error;
++}
++
++void
++bcmsdh_unregister(void)
++{
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
++		if (bcmsdh_pci_driver.node.next == NULL)
++			return;
++#endif
++
++	bcmsdh_unregister_client_driver();
++}
++
++void bcmsdh_dev_pm_stay_awake(bcmsdh_info_t *bcmsdh)
++{
++#if !defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++	pm_stay_awake(bcmsdh_osinfo->dev);
++#endif /* !defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36)) */
++}
++
++void bcmsdh_dev_relax(bcmsdh_info_t *bcmsdh)
++{
++#if !defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++	pm_relax(bcmsdh_osinfo->dev);
++#endif /* !defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36)) */
++}
++
++bool bcmsdh_dev_pm_enabled(bcmsdh_info_t *bcmsdh)
++{
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++
++	return bcmsdh_osinfo->dev_wake_enabled;
++}
++
++#if defined(OOB_INTR_ONLY)
++void bcmsdh_oob_intr_set(bcmsdh_info_t *bcmsdh, bool enable)
++{
++	unsigned long flags;
++	bcmsdh_os_info_t *bcmsdh_osinfo;
++
++	if (!bcmsdh)
++		return;
++
++	bcmsdh_osinfo = bcmsdh->os_cxt;
++	spin_lock_irqsave(&bcmsdh_osinfo->oob_irq_spinlock, flags);
++	if (bcmsdh_osinfo->oob_irq_enabled != enable) {
++		if (enable)
++			enable_irq(bcmsdh_osinfo->oob_irq_num);
++		else
++			disable_irq_nosync(bcmsdh_osinfo->oob_irq_num);
++		bcmsdh_osinfo->oob_irq_enabled = enable;
++	}
++	spin_unlock_irqrestore(&bcmsdh_osinfo->oob_irq_spinlock, flags);
++}
++
++static irqreturn_t wlan_oob_irq(int irq, void *dev_id)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)dev_id;
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++
++	bcmsdh_oob_intr_set(bcmsdh, FALSE);
++	bcmsdh_osinfo->oob_irq_handler(bcmsdh_osinfo->oob_irq_handler_context);
++
++	return IRQ_HANDLED;
++}
++
++int bcmsdh_oob_intr_register(bcmsdh_info_t *bcmsdh, bcmsdh_cb_fn_t oob_irq_handler,
++	void* oob_irq_handler_context)
++{
++	int err = 0;
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++
++	if (bcmsdh_osinfo->oob_irq_registered) {
++		SDLX_ERR(("%s: irq is already registered\n", __FUNCTION__));
++		return -EBUSY;
++	}
++#ifdef HW_OOB
++	SDLX_MSG(("%s: HW_OOB irq=%d flags=0x%X\n", __FUNCTION__,
++		(int)bcmsdh_osinfo->oob_irq_num, (int)bcmsdh_osinfo->oob_irq_flags));
++#else
++	SDLX_MSG(("%s: SW_OOB irq=%d flags=0x%X\n", __FUNCTION__,
++		(int)bcmsdh_osinfo->oob_irq_num, (int)bcmsdh_osinfo->oob_irq_flags));
++#endif
++	bcmsdh_osinfo->oob_irq_handler = oob_irq_handler;
++	bcmsdh_osinfo->oob_irq_handler_context = oob_irq_handler_context;
++	bcmsdh_osinfo->oob_irq_enabled = TRUE;
++	bcmsdh_osinfo->oob_irq_registered = TRUE;
++#if defined(CONFIG_ARCH_ODIN)
++	err = odin_gpio_sms_request_irq(bcmsdh_osinfo->oob_irq_num, wlan_oob_irq,
++		bcmsdh_osinfo->oob_irq_flags, "bcmsdh_sdmmc", bcmsdh);
++#else
++	err = request_irq(bcmsdh_osinfo->oob_irq_num, wlan_oob_irq,
++		bcmsdh_osinfo->oob_irq_flags, "bcmsdh_sdmmc", bcmsdh);
++#endif /* defined(CONFIG_ARCH_ODIN) */
++	if (err) {
++		SDLX_ERR(("%s: request_irq failed with %d\n", __FUNCTION__, err));
++		bcmsdh_osinfo->oob_irq_enabled = FALSE;
++		bcmsdh_osinfo->oob_irq_registered = FALSE;
++		return err;
++	}
++
++#if defined(DISABLE_WOWLAN)
++	SDLX_MSG(("%s: disable_irq_wake\n", __FUNCTION__));
++	bcmsdh_osinfo->oob_irq_wake_enabled = FALSE;
++#else
++	err = enable_irq_wake(bcmsdh_osinfo->oob_irq_num);
++	if (err)
++		SDLX_ERR(("%s: enable_irq_wake failed with %d\n", __FUNCTION__, err));
++	else
++		bcmsdh_osinfo->oob_irq_wake_enabled = TRUE;
++#endif
++
++	return 0;
++}
++
++void bcmsdh_oob_intr_unregister(bcmsdh_info_t *bcmsdh)
++{
++	int err = 0;
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++
++	SDLX_MSG(("%s: Enter\n", __FUNCTION__));
++	if (!bcmsdh_osinfo->oob_irq_registered) {
++		SDLX_MSG(("%s: irq is not registered\n", __FUNCTION__));
++		return;
++	}
++	if (bcmsdh_osinfo->oob_irq_wake_enabled) {
++		err = disable_irq_wake(bcmsdh_osinfo->oob_irq_num);
++		if (!err)
++			bcmsdh_osinfo->oob_irq_wake_enabled = FALSE;
++	}
++	if (bcmsdh_osinfo->oob_irq_enabled) {
++		disable_irq(bcmsdh_osinfo->oob_irq_num);
++		bcmsdh_osinfo->oob_irq_enabled = FALSE;
++	}
++	free_irq(bcmsdh_osinfo->oob_irq_num, bcmsdh);
++	bcmsdh_osinfo->oob_irq_registered = FALSE;
++}
++#endif
++
++/* Module parameters specific to each host-controller driver */
++
++extern uint sd_msglevel;	/* Debug message level */
++module_param(sd_msglevel, uint, 0);
++
++extern uint sd_power;	/* 0 = SD Power OFF, 1 = SD Power ON. */
++module_param(sd_power, uint, 0);
++
++extern uint sd_clock;	/* SD Clock Control, 0 = SD Clock OFF, 1 = SD Clock ON */
++module_param(sd_clock, uint, 0);
++
++extern uint sd_divisor;	/* Divisor (-1 means external clock) */
++module_param(sd_divisor, uint, 0);
++
++extern uint sd_sdmode;	/* Default is SD4, 0=SPI, 1=SD1, 2=SD4 */
++module_param(sd_sdmode, uint, 0);
++
++extern uint sd_hiok;	/* Ok to use hi-speed mode */
++module_param(sd_hiok, uint, 0);
++
++extern uint sd_f2_blocksize;
++module_param(sd_f2_blocksize, int, 0);
++
++extern uint sd_f1_blocksize;
++module_param(sd_f1_blocksize, int, 0);
++
++#ifdef BCMSDIOH_STD
++extern int sd_uhsimode;
++module_param(sd_uhsimode, int, 0);
++extern uint sd_tuning_period;
++module_param(sd_tuning_period, uint, 0);
++extern int sd_delay_value;
++module_param(sd_delay_value, uint, 0);
++
++/* SDIO Drive Strength for UHSI mode specific to SDIO3.0 */
++extern char dhd_sdiod_uhsi_ds_override[2];
++module_param_string(dhd_sdiod_uhsi_ds_override, dhd_sdiod_uhsi_ds_override, 2, 0);
++
++#endif
++
++#ifdef BCMSDH_MODULE
++EXPORT_SYMBOL(bcmsdh_attach);
++EXPORT_SYMBOL(bcmsdh_detach);
++EXPORT_SYMBOL(bcmsdh_intr_query);
++EXPORT_SYMBOL(bcmsdh_intr_enable);
++EXPORT_SYMBOL(bcmsdh_intr_disable);
++EXPORT_SYMBOL(bcmsdh_intr_reg);
++EXPORT_SYMBOL(bcmsdh_intr_dereg);
++
++#if defined(DHD_DEBUG)
++EXPORT_SYMBOL(bcmsdh_intr_pending);
++#endif
++
++#if defined(BT_OVER_SDIO)
++EXPORT_SYMBOL(bcmsdh_btsdio_interface_init);
++#endif /* defined (BT_OVER_SDIO) */
++
++EXPORT_SYMBOL(bcmsdh_devremove_reg);
++EXPORT_SYMBOL(bcmsdh_cfg_read);
++EXPORT_SYMBOL(bcmsdh_cfg_write);
++EXPORT_SYMBOL(bcmsdh_cis_read);
++EXPORT_SYMBOL(bcmsdh_reg_read);
++EXPORT_SYMBOL(bcmsdh_reg_write);
++EXPORT_SYMBOL(bcmsdh_regfail);
++EXPORT_SYMBOL(bcmsdh_send_buf);
++EXPORT_SYMBOL(bcmsdh_recv_buf);
++
++EXPORT_SYMBOL(bcmsdh_rwdata);
++EXPORT_SYMBOL(bcmsdh_abort);
++EXPORT_SYMBOL(bcmsdh_query_device);
++EXPORT_SYMBOL(bcmsdh_query_iofnum);
++EXPORT_SYMBOL(bcmsdh_iovar_op);
++EXPORT_SYMBOL(bcmsdh_register);
++EXPORT_SYMBOL(bcmsdh_unregister);
++EXPORT_SYMBOL(bcmsdh_chipmatch);
++EXPORT_SYMBOL(bcmsdh_reset);
++EXPORT_SYMBOL(bcmsdh_waitlockfree);
++
++EXPORT_SYMBOL(bcmsdh_get_dstatus);
++EXPORT_SYMBOL(bcmsdh_cfg_read_word);
++EXPORT_SYMBOL(bcmsdh_cfg_write_word);
++EXPORT_SYMBOL(bcmsdh_cur_sbwad);
++EXPORT_SYMBOL(bcmsdh_chipinfo);
++
++#endif /* BCMSDH_MODULE */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc.c b/module_drivers/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc.c
+new file mode 100644
+index 000000000..0aa5d960c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc.c
+@@ -0,0 +1,1774 @@
++/*
++ * BCMSDH Function Driver for the native SDIO/MMC driver in the Linux Kernel
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Proprietary,Open:>>
++ *
++ * $Id: bcmsdh_sdmmc.c 710913 2017-07-14 10:17:51Z $
++ */
++#include <typedefs.h>
++
++#include <bcmdevs.h>
++#include <bcmendian.h>
++#include <bcmutils.h>
++#include <osl.h>
++#include <sdio.h>	/* SDIO Device and Protocol Specs */
++#include <sdioh.h>	/* Standard SDIO Host Controller Specification */
++#include <bcmsdbus.h>	/* bcmsdh to/from specific controller APIs */
++#include <sdiovar.h>	/* ioctl/iovars */
++
++#include <linux/mmc/core.h>
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 0, 0))
++#include <drivers/mmc/core/host.h>
++void
++mmc_host_clk_hold(struct mmc_host *host)
++{
++	BCM_REFERENCE(host);
++	return;
++}
++
++void
++mmc_host_clk_release(struct mmc_host *host)
++{
++	BCM_REFERENCE(host);
++	return;
++}
++#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 0, 8))
++#include <drivers/mmc/core/host.h>
++#else
++#include <linux/mmc/host.h>
++#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 0, 0)) */
++#include <linux/mmc/card.h>
++#include <linux/mmc/sdio_func.h>
++#include <linux/mmc/sdio_ids.h>
++
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_dbg.h>
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_PM_SLEEP)
++#include <linux/suspend.h>
++extern volatile bool dhd_mmc_suspend;
++#endif
++#include "bcmsdh_sdmmc.h"
++
++#ifndef BCMSDH_MODULE
++extern int sdio_function_init(void);
++extern void sdio_function_cleanup(void);
++#endif /* BCMSDH_MODULE */
++
++#if !defined(OOB_INTR_ONLY)
++static void IRQHandler(struct sdio_func *func);
++static void IRQHandlerF2(struct sdio_func *func);
++#endif /* !defined(OOB_INTR_ONLY) */
++static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, uint32 regaddr);
++#if defined(ENABLE_INSMOD_NO_FW_LOAD) && !defined(BUS_POWER_RESTORE)
++extern int sdio_reset_comm(struct mmc_card *card);
++#endif
++#ifdef GLOBAL_SDMMC_INSTANCE
++extern PBCMSDH_SDMMC_INSTANCE gInstance;
++#endif
++
++#define DEFAULT_SDIO_F2_BLKSIZE		512
++#ifndef CUSTOM_SDIO_F2_BLKSIZE
++#define CUSTOM_SDIO_F2_BLKSIZE		DEFAULT_SDIO_F2_BLKSIZE
++#endif
++
++#define DEFAULT_SDIO_F1_BLKSIZE		64
++#ifndef CUSTOM_SDIO_F1_BLKSIZE
++#define CUSTOM_SDIO_F1_BLKSIZE		DEFAULT_SDIO_F1_BLKSIZE
++#endif
++
++#define MAX_IO_RW_EXTENDED_BLK		511
++
++uint sd_sdmode = SDIOH_MODE_SD4;	/* Use SD4 mode by default */
++uint sd_f2_blocksize = CUSTOM_SDIO_F2_BLKSIZE;
++uint sd_f1_blocksize = CUSTOM_SDIO_F1_BLKSIZE;
++
++#if defined(BT_OVER_SDIO)
++uint sd_f3_blocksize = 64;
++#endif /* defined (BT_OVER_SDIO) */
++
++uint sd_divisor = 2;			/* Default 48MHz/2 = 24MHz */
++
++uint sd_power = 1;		/* Default to SD Slot powered ON */
++uint sd_clock = 1;		/* Default to SD Clock turned ON */
++uint sd_hiok = FALSE;	/* Don't use hi-speed mode by default */
++uint sd_msglevel = 0x01;
++uint sd_use_dma = TRUE;
++
++#ifndef CUSTOM_RXCHAIN
++#define CUSTOM_RXCHAIN 0
++#endif
++
++DHD_PM_RESUME_WAIT_INIT(sdioh_request_byte_wait);
++DHD_PM_RESUME_WAIT_INIT(sdioh_request_word_wait);
++DHD_PM_RESUME_WAIT_INIT(sdioh_request_packet_wait);
++DHD_PM_RESUME_WAIT_INIT(sdioh_request_buffer_wait);
++
++#define DMA_ALIGN_MASK	0x03
++#define MMC_SDIO_ABORT_RETRY_LIMIT 5
++
++int sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data);
++
++void  sdmmc_set_clock_rate(sdioh_info_t *sd, uint hz);
++uint  sdmmc_get_clock_rate(sdioh_info_t *sd);
++void  sdmmc_set_clock_divisor(sdioh_info_t *sd, uint sd_div);
++#if defined(BT_OVER_SDIO)
++extern
++void sdioh_sdmmc_card_enable_func_f3(sdioh_info_t *sd, struct sdio_func *func)
++{
++	sd->func[3] = func;
++	sd_info(("%s sd->func[3] %p\n", __FUNCTION__, sd->func[3]));
++}
++#endif /* defined (BT_OVER_SDIO) */
++
++static int
++sdioh_sdmmc_card_enablefuncs(sdioh_info_t *sd)
++{
++	int err_ret;
++	uint32 fbraddr;
++	uint8 func;
++
++	sd_trace(("%s\n", __FUNCTION__));
++
++	/* Get the Card's common CIS address */
++	sd->com_cis_ptr = sdioh_sdmmc_get_cisaddr(sd, SDIOD_CCCR_CISPTR_0);
++	sd->func_cis_ptr[0] = sd->com_cis_ptr;
++	sd_info(("%s: Card's Common CIS Ptr = 0x%x\n", __FUNCTION__, sd->com_cis_ptr));
++
++	/* Get the Card's function CIS (for each function) */
++	for (fbraddr = SDIOD_FBR_STARTADDR, func = 1;
++	     func <= sd->num_funcs; func++, fbraddr += SDIOD_FBR_SIZE) {
++		sd->func_cis_ptr[func] = sdioh_sdmmc_get_cisaddr(sd, SDIOD_FBR_CISPTR_0 + fbraddr);
++		sd_info(("%s: Function %d CIS Ptr = 0x%x\n",
++		         __FUNCTION__, func, sd->func_cis_ptr[func]));
++	}
++
++	sd->func_cis_ptr[0] = sd->com_cis_ptr;
++	sd_info(("%s: Card's Common CIS Ptr = 0x%x\n", __FUNCTION__, sd->com_cis_ptr));
++
++	/* Enable Function 1 */
++	sdio_claim_host(sd->func[1]);
++	err_ret = sdio_enable_func(sd->func[1]);
++	sdio_release_host(sd->func[1]);
++	if (err_ret) {
++		sd_err(("bcmsdh_sdmmc: Failed to enable F1 Err: 0x%08x\n", err_ret));
++	}
++
++	return FALSE;
++}
++
++/*
++ *	Public entry points & extern's
++ */
++extern sdioh_info_t *
++sdioh_attach(osl_t *osh, struct sdio_func *func)
++{
++	sdioh_info_t *sd = NULL;
++	int err_ret;
++
++	sd_trace(("%s\n", __FUNCTION__));
++
++	if (func == NULL) {
++		sd_err(("%s: sdio function device is NULL\n", __FUNCTION__));
++		return NULL;
++	}
++
++	if ((sd = (sdioh_info_t *)MALLOC(osh, sizeof(sdioh_info_t))) == NULL) {
++		sd_err(("sdioh_attach: out of memory, malloced %d bytes\n", MALLOCED(osh)));
++		return NULL;
++	}
++	bzero((char *)sd, sizeof(sdioh_info_t));
++	sd->osh = osh;
++	sd->fake_func0.num = 0;
++	sd->fake_func0.card = func->card;
++	sd->func[0] = &sd->fake_func0;
++#ifdef GLOBAL_SDMMC_INSTANCE
++	if (func->num == 2)
++		sd->func[1] = gInstance->func[1];
++#else
++	sd->func[1] = func->card->sdio_func[0];
++#endif
++	sd->func[2] = func->card->sdio_func[1];
++#ifdef GLOBAL_SDMMC_INSTANCE
++	sd->func[func->num] = func;
++#endif
++
++#if defined(BT_OVER_SDIO)
++	sd->func[3] = NULL;
++#endif /* defined (BT_OVER_SDIO) */
++
++	sd->num_funcs = 2;
++	sd->sd_blockmode = TRUE;
++	sd->use_client_ints = TRUE;
++	sd->client_block_size[0] = 64;
++	sd->use_rxchain = CUSTOM_RXCHAIN;
++	if (sd->func[1] == NULL || sd->func[2] == NULL) {
++		sd_err(("%s: func 1 or 2 is null \n", __FUNCTION__));
++		goto fail;
++	}
++	sdio_set_drvdata(sd->func[1], sd);
++
++	sdio_claim_host(sd->func[1]);
++	sd->client_block_size[1] = sd_f1_blocksize;
++	err_ret = sdio_set_block_size(sd->func[1], sd_f1_blocksize);
++	sdio_release_host(sd->func[1]);
++	if (err_ret) {
++		sd_err(("bcmsdh_sdmmc: Failed to set F1 blocksize(%d)\n", err_ret));
++		goto fail;
++	}
++
++	sdio_claim_host(sd->func[2]);
++	sd->client_block_size[2] = sd_f2_blocksize;
++	printf("%s: set sd_f2_blocksize %d\n", __FUNCTION__, sd_f2_blocksize);
++	err_ret = sdio_set_block_size(sd->func[2], sd_f2_blocksize);
++	sdio_release_host(sd->func[2]);
++	if (err_ret) {
++		sd_err(("bcmsdh_sdmmc: Failed to set F2 blocksize to %d(%d)\n",
++			sd_f2_blocksize, err_ret));
++		goto fail;
++	}
++
++	sd->sd_clk_rate = sdmmc_get_clock_rate(sd);
++	printf("%s: sd clock rate = %u\n", __FUNCTION__, sd->sd_clk_rate);
++	sdioh_sdmmc_card_enablefuncs(sd);
++
++	sd_trace(("%s: Done\n", __FUNCTION__));
++	return sd;
++
++fail:
++	MFREE(sd->osh, sd, sizeof(sdioh_info_t));
++	return NULL;
++}
++
++
++extern SDIOH_API_RC
++sdioh_detach(osl_t *osh, sdioh_info_t *sd)
++{
++	sd_trace(("%s\n", __FUNCTION__));
++
++	if (sd) {
++
++		/* Disable Function 2 */
++		if (sd->func[2]) {
++			sdio_claim_host(sd->func[2]);
++			sdio_disable_func(sd->func[2]);
++			sdio_release_host(sd->func[2]);
++		}
++
++		/* Disable Function 1 */
++		if (sd->func[1]) {
++			sdio_claim_host(sd->func[1]);
++			sdio_disable_func(sd->func[1]);
++			sdio_release_host(sd->func[1]);
++		}
++
++		sd->func[1] = NULL;
++		sd->func[2] = NULL;
++
++		MFREE(sd->osh, sd, sizeof(sdioh_info_t));
++	}
++	return SDIOH_API_RC_SUCCESS;
++}
++
++#if defined(OOB_INTR_ONLY) && defined(HW_OOB)
++
++extern SDIOH_API_RC
++sdioh_enable_func_intr(sdioh_info_t *sd)
++{
++	uint8 reg;
++	int err;
++
++	if (sd->func[0] == NULL) {
++		sd_err(("%s: function 0 pointer is NULL\n", __FUNCTION__));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	sdio_claim_host(sd->func[0]);
++	reg = sdio_readb(sd->func[0], SDIOD_CCCR_INTEN, &err);
++	if (err) {
++		sd_err(("%s: error for read SDIO_CCCR_IENx : 0x%x\n", __FUNCTION__, err));
++		sdio_release_host(sd->func[0]);
++		return SDIOH_API_RC_FAIL;
++	}
++	/* Enable F1 and F2 interrupts, clear master enable */
++	reg &= ~INTR_CTL_MASTER_EN;
++	reg |= (INTR_CTL_FUNC1_EN | INTR_CTL_FUNC2_EN);
++#if defined(BT_OVER_SDIO)
++	reg |= (INTR_CTL_FUNC3_EN);
++#endif /* defined (BT_OVER_SDIO) */
++	sdio_writeb(sd->func[0], reg, SDIOD_CCCR_INTEN, &err);
++	sdio_release_host(sd->func[0]);
++
++	if (err) {
++		sd_err(("%s: error for write SDIO_CCCR_IENx : 0x%x\n", __FUNCTION__, err));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	return SDIOH_API_RC_SUCCESS;
++}
++
++extern SDIOH_API_RC
++sdioh_disable_func_intr(sdioh_info_t *sd)
++{
++	uint8 reg;
++	int err;
++
++	if (sd->func[0] == NULL) {
++		sd_err(("%s: function 0 pointer is NULL\n", __FUNCTION__));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	sdio_claim_host(sd->func[0]);
++	reg = sdio_readb(sd->func[0], SDIOD_CCCR_INTEN, &err);
++	if (err) {
++		sd_err(("%s: error for read SDIO_CCCR_IENx : 0x%x\n", __FUNCTION__, err));
++		sdio_release_host(sd->func[0]);
++		return SDIOH_API_RC_FAIL;
++	}
++	reg &= ~(INTR_CTL_FUNC1_EN | INTR_CTL_FUNC2_EN);
++#if defined(BT_OVER_SDIO)
++	reg &= ~INTR_CTL_FUNC3_EN;
++#endif
++	/* Disable master interrupt with the last function interrupt */
++	if (!(reg & 0xFE))
++		reg = 0;
++	sdio_writeb(sd->func[0], reg, SDIOD_CCCR_INTEN, &err);
++	sdio_release_host(sd->func[0]);
++
++	if (err) {
++		sd_err(("%s: error for write SDIO_CCCR_IENx : 0x%x\n", __FUNCTION__, err));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	return SDIOH_API_RC_SUCCESS;
++}
++#endif /* defined(OOB_INTR_ONLY) && defined(HW_OOB) */
++
++/* Configure callback to client when we recieve client interrupt */
++extern SDIOH_API_RC
++sdioh_interrupt_register(sdioh_info_t *sd, sdioh_cb_fn_t fn, void *argh)
++{
++	sd_trace(("%s: Entering\n", __FUNCTION__));
++	if (fn == NULL) {
++		sd_err(("%s: interrupt handler is NULL, not registering\n", __FUNCTION__));
++		return SDIOH_API_RC_FAIL;
++	}
++#if !defined(OOB_INTR_ONLY)
++	sd->intr_handler = fn;
++	sd->intr_handler_arg = argh;
++	sd->intr_handler_valid = TRUE;
++
++	/* register and unmask irq */
++	if (sd->func[2]) {
++		sdio_claim_host(sd->func[2]);
++		sdio_claim_irq(sd->func[2], IRQHandlerF2);
++		sdio_release_host(sd->func[2]);
++	}
++
++	if (sd->func[1]) {
++		sdio_claim_host(sd->func[1]);
++		sdio_claim_irq(sd->func[1], IRQHandler);
++		sdio_release_host(sd->func[1]);
++	}
++#elif defined(HW_OOB)
++	sdioh_enable_func_intr(sd);
++#endif /* !defined(OOB_INTR_ONLY) */
++
++	return SDIOH_API_RC_SUCCESS;
++}
++
++extern SDIOH_API_RC
++sdioh_interrupt_deregister(sdioh_info_t *sd)
++{
++	sd_trace(("%s: Entering\n", __FUNCTION__));
++
++#if !defined(OOB_INTR_ONLY)
++	if (sd->func[1]) {
++		/* register and unmask irq */
++		sdio_claim_host(sd->func[1]);
++		sdio_release_irq(sd->func[1]);
++		sdio_release_host(sd->func[1]);
++	}
++
++	if (sd->func[2]) {
++		/* Claim host controller F2 */
++		sdio_claim_host(sd->func[2]);
++		sdio_release_irq(sd->func[2]);
++		/* Release host controller F2 */
++		sdio_release_host(sd->func[2]);
++	}
++
++	sd->intr_handler_valid = FALSE;
++	sd->intr_handler = NULL;
++	sd->intr_handler_arg = NULL;
++#elif defined(HW_OOB)
++	if (dhd_download_fw_on_driverload)
++		sdioh_disable_func_intr(sd);
++#endif /* !defined(OOB_INTR_ONLY) */
++	return SDIOH_API_RC_SUCCESS;
++}
++
++extern SDIOH_API_RC
++sdioh_interrupt_query(sdioh_info_t *sd, bool *onoff)
++{
++	sd_trace(("%s: Entering\n", __FUNCTION__));
++	*onoff = sd->client_intr_enabled;
++	return SDIOH_API_RC_SUCCESS;
++}
++
++#if defined(DHD_DEBUG)
++extern bool
++sdioh_interrupt_pending(sdioh_info_t *sd)
++{
++	return (0);
++}
++#endif
++
++uint
++sdioh_query_iofnum(sdioh_info_t *sd)
++{
++	return sd->num_funcs;
++}
++
++/* IOVar table */
++enum {
++	IOV_MSGLEVEL = 1,
++	IOV_BLOCKMODE,
++	IOV_BLOCKSIZE,
++	IOV_DMA,
++	IOV_USEINTS,
++	IOV_NUMINTS,
++	IOV_NUMLOCALINTS,
++	IOV_HOSTREG,
++	IOV_DEVREG,
++	IOV_DIVISOR,
++	IOV_SDMODE,
++	IOV_HISPEED,
++	IOV_HCIREGS,
++	IOV_POWER,
++	IOV_CLOCK,
++	IOV_RXCHAIN
++};
++
++const bcm_iovar_t sdioh_iovars[] = {
++	{"sd_msglevel", IOV_MSGLEVEL,	0, 0,	IOVT_UINT32,	0 },
++	{"sd_blockmode", IOV_BLOCKMODE, 0, 0,	IOVT_BOOL,	0 },
++	{"sd_blocksize", IOV_BLOCKSIZE, 0, 0,	IOVT_UINT32,	0 }, /* ((fn << 16) | size) */
++	{"sd_dma",	IOV_DMA,	0, 0,	IOVT_BOOL,	0 },
++	{"sd_ints",	IOV_USEINTS,	0, 0,	IOVT_BOOL,	0 },
++	{"sd_numints",	IOV_NUMINTS,	0, 0,	IOVT_UINT32,	0 },
++	{"sd_numlocalints", IOV_NUMLOCALINTS, 0, 0, IOVT_UINT32,	0 },
++	{"sd_divisor",	IOV_DIVISOR,	0, 0,	IOVT_UINT32,	0 },
++	{"sd_power",	IOV_POWER,	0, 0,	IOVT_UINT32,	0 },
++	{"sd_clock",	IOV_CLOCK,	0, 0,	IOVT_UINT32,	0 },
++	{"sd_mode",	IOV_SDMODE,	0, 0,	IOVT_UINT32,	100},
++	{"sd_highspeed", IOV_HISPEED,	0, 0,	IOVT_UINT32,	0 },
++	{"sd_rxchain",  IOV_RXCHAIN,    0, 0, 	IOVT_BOOL,	0 },
++	{NULL, 0, 0, 0, 0, 0 }
++};
++
++int
++sdioh_iovar_op(sdioh_info_t *si, const char *name,
++                           void *params, int plen, void *arg, int len, bool set)
++{
++	const bcm_iovar_t *vi = NULL;
++	int bcmerror = 0;
++	int val_size;
++	int32 int_val = 0;
++	bool bool_val;
++	uint32 actionid;
++
++	ASSERT(name);
++	ASSERT(len >= 0);
++
++	/* Get must have return space; Set does not take qualifiers */
++	ASSERT(set || (arg && len));
++	ASSERT(!set || (!params && !plen));
++
++	sd_trace(("%s: Enter (%s %s)\n", __FUNCTION__, (set ? "set" : "get"), name));
++
++	if ((vi = bcm_iovar_lookup(sdioh_iovars, name)) == NULL) {
++		bcmerror = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++	if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, set)) != 0)
++		goto exit;
++
++	/* Set up params so get and set can share the convenience variables */
++	if (params == NULL) {
++		params = arg;
++		plen = len;
++	}
++
++	if (vi->type == IOVT_VOID)
++		val_size = 0;
++	else if (vi->type == IOVT_BUFFER)
++		val_size = len;
++	else
++		val_size = sizeof(int);
++
++	if (plen >= (int)sizeof(int_val))
++		bcopy(params, &int_val, sizeof(int_val));
++
++	bool_val = (int_val != 0) ? TRUE : FALSE;
++	BCM_REFERENCE(bool_val);
++
++	actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
++	switch (actionid) {
++	case IOV_GVAL(IOV_MSGLEVEL):
++		int_val = (int32)sd_msglevel;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_MSGLEVEL):
++		sd_msglevel = int_val;
++		break;
++
++	case IOV_GVAL(IOV_BLOCKMODE):
++		int_val = (int32)si->sd_blockmode;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_BLOCKMODE):
++		si->sd_blockmode = (bool)int_val;
++		/* Haven't figured out how to make non-block mode with DMA */
++		break;
++
++	case IOV_GVAL(IOV_BLOCKSIZE):
++		if ((uint32)int_val > si->num_funcs) {
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		int_val = (int32)si->client_block_size[int_val];
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_BLOCKSIZE):
++	{
++		uint func = ((uint32)int_val >> 16);
++		uint blksize = (uint16)int_val;
++		uint maxsize;
++
++		if (func > si->num_funcs) {
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		switch (func) {
++		case 0: maxsize = 32; break;
++		case 1: maxsize = BLOCK_SIZE_4318; break;
++		case 2: maxsize = BLOCK_SIZE_4328; break;
++		default: maxsize = 0;
++		}
++		if (blksize > maxsize) {
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		if (!blksize) {
++			blksize = maxsize;
++		}
++
++		/* Now set it */
++		si->client_block_size[func] = blksize;
++
++#ifdef USE_DYNAMIC_F2_BLKSIZE
++		if (si->func[func] == NULL) {
++			sd_err(("%s: SDIO Device not present\n", __FUNCTION__));
++			bcmerror = BCME_NORESOURCE;
++			break;
++		}
++		sdio_claim_host(si->func[func]);
++		bcmerror = sdio_set_block_size(si->func[func], blksize);
++		if (bcmerror)
++			sd_err(("%s: Failed to set F%d blocksize to %d(%d)\n",
++				__FUNCTION__, func, blksize, bcmerror));
++		sdio_release_host(si->func[func]);
++#endif /* USE_DYNAMIC_F2_BLKSIZE */
++		break;
++	}
++
++	case IOV_GVAL(IOV_RXCHAIN):
++		int_val = (int32)si->use_rxchain;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_DMA):
++		int_val = (int32)si->sd_use_dma;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DMA):
++		si->sd_use_dma = (bool)int_val;
++		break;
++
++	case IOV_GVAL(IOV_USEINTS):
++		int_val = (int32)si->use_client_ints;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_USEINTS):
++		si->use_client_ints = (bool)int_val;
++		if (si->use_client_ints)
++			si->intmask |= CLIENT_INTR;
++		else
++			si->intmask &= ~CLIENT_INTR;
++
++		break;
++
++	case IOV_GVAL(IOV_DIVISOR):
++		int_val = (uint32)sd_divisor;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DIVISOR):
++		/* set the clock to divisor, if value is non-zero & power of 2 */
++		if (int_val && !(int_val & (int_val - 1))) {
++			sd_divisor = int_val;
++			sdmmc_set_clock_divisor(si, sd_divisor);
++		} else {
++			DHD_ERROR(("%s: Invalid sd_divisor value, should be power of 2!\n",
++				__FUNCTION__));
++		}
++		break;
++
++	case IOV_GVAL(IOV_POWER):
++		int_val = (uint32)sd_power;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_POWER):
++		sd_power = int_val;
++		break;
++
++	case IOV_GVAL(IOV_CLOCK):
++		int_val = (uint32)sd_clock;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_CLOCK):
++		sd_clock = int_val;
++		break;
++
++	case IOV_GVAL(IOV_SDMODE):
++		int_val = (uint32)sd_sdmode;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_SDMODE):
++		sd_sdmode = int_val;
++		break;
++
++	case IOV_GVAL(IOV_HISPEED):
++		int_val = (uint32)sd_hiok;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_HISPEED):
++		sd_hiok = int_val;
++		break;
++
++	case IOV_GVAL(IOV_NUMINTS):
++		int_val = (int32)si->intrcount;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_NUMLOCALINTS):
++		int_val = (int32)0;
++		bcopy(&int_val, arg, val_size);
++		break;
++	default:
++		bcmerror = BCME_UNSUPPORTED;
++		break;
++	}
++exit:
++
++	return bcmerror;
++}
++
++#if (defined(OOB_INTR_ONLY) && defined(HW_OOB)) || defined(FORCE_WOWLAN)
++
++SDIOH_API_RC
++sdioh_enable_hw_oob_intr(sdioh_info_t *sd, bool enable)
++{
++	SDIOH_API_RC status;
++	uint8 data;
++
++	if (enable)
++#ifdef HW_OOB_LOW_LEVEL
++		data = SDIO_SEPINT_MASK | SDIO_SEPINT_OE;
++#else
++		data = SDIO_SEPINT_MASK | SDIO_SEPINT_OE | SDIO_SEPINT_ACT_HI;
++#endif
++	else
++		data = SDIO_SEPINT_ACT_HI;	/* disable hw oob interrupt */
++
++	status = sdioh_request_byte(sd, SDIOH_WRITE, 0, SDIOD_CCCR_BRCM_SEPINT, &data);
++	return status;
++}
++#endif /* defined(OOB_INTR_ONLY) && defined(HW_OOB) */
++
++extern SDIOH_API_RC
++sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
++{
++	SDIOH_API_RC status;
++	/* No lock needed since sdioh_request_byte does locking */
++	status = sdioh_request_byte(sd, SDIOH_READ, fnc_num, addr, data);
++	return status;
++}
++
++extern SDIOH_API_RC
++sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
++{
++	/* No lock needed since sdioh_request_byte does locking */
++	SDIOH_API_RC status;
++	status = sdioh_request_byte(sd, SDIOH_WRITE, fnc_num, addr, data);
++	return status;
++}
++
++static int
++sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, uint32 regaddr)
++{
++	/* read 24 bits and return valid 17 bit addr */
++	int i;
++	uint32 scratch, regdata;
++	uint8 *ptr = (uint8 *)&scratch;
++	for (i = 0; i < 3; i++) {
++		if ((sdioh_sdmmc_card_regread (sd, 0, regaddr, 1, &regdata)) != SUCCESS)
++			sd_err(("%s: Can't read!\n", __FUNCTION__));
++
++		*ptr++ = (uint8) regdata;
++		regaddr++;
++	}
++
++	/* Only the lower 17-bits are valid */
++	scratch = ltoh32(scratch);
++	scratch &= 0x0001FFFF;
++	return (scratch);
++}
++
++extern SDIOH_API_RC
++sdioh_cis_read(sdioh_info_t *sd, uint func, uint8 *cisd, uint32 length)
++{
++	uint32 count;
++	int offset;
++	uint32 foo;
++	uint8 *cis = cisd;
++
++	sd_trace(("%s: Func = %d\n", __FUNCTION__, func));
++
++	if (!sd->func_cis_ptr[func]) {
++		bzero(cis, length);
++		sd_err(("%s: no func_cis_ptr[%d]\n", __FUNCTION__, func));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	sd_err(("%s: func_cis_ptr[%d]=0x%04x\n", __FUNCTION__, func, sd->func_cis_ptr[func]));
++
++	for (count = 0; count < length; count++) {
++		offset =  sd->func_cis_ptr[func] + count;
++		if (sdioh_sdmmc_card_regread (sd, 0, offset, 1, &foo) < 0) {
++			sd_err(("%s: regread failed: Can't read CIS\n", __FUNCTION__));
++			return SDIOH_API_RC_FAIL;
++		}
++
++		*cis = (uint8)(foo & 0xff);
++		cis++;
++	}
++
++	return SDIOH_API_RC_SUCCESS;
++}
++
++extern SDIOH_API_RC
++sdioh_cisaddr_read(sdioh_info_t *sd, uint func, uint8 *cisd, uint32 offset)
++{
++	uint32 foo;
++
++	sd_trace(("%s: Func = %d\n", __FUNCTION__, func));
++
++	if (!sd->func_cis_ptr[func]) {
++		sd_err(("%s: no func_cis_ptr[%d]\n", __FUNCTION__, func));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	sd_err(("%s: func_cis_ptr[%d]=0x%04x\n", __FUNCTION__, func, sd->func_cis_ptr[func]));
++
++	if (sdioh_sdmmc_card_regread (sd, 0, sd->func_cis_ptr[func]+offset, 1, &foo) < 0) {
++		sd_err(("%s: regread failed: Can't read CIS\n", __FUNCTION__));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	*cisd = (uint8)(foo & 0xff);
++
++	return SDIOH_API_RC_SUCCESS;
++}
++
++extern SDIOH_API_RC
++sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr, uint8 *byte)
++{
++	int err_ret = 0;
++#if defined(MMC_SDIO_ABORT)
++	int sdio_abort_retry = MMC_SDIO_ABORT_RETRY_LIMIT;
++#endif
++	struct osl_timespec now, before;
++
++	if (sd_msglevel & SDH_COST_VAL)
++		osl_do_gettimeofday(&before);
++
++	sd_info(("%s: rw=%d, func=%d, addr=0x%05x\n", __FUNCTION__, rw, func, regaddr));
++
++	DHD_PM_RESUME_WAIT(sdioh_request_byte_wait);
++	DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
++	if(rw) { /* CMD52 Write */
++		if (func == 0) {
++			/* Can only directly write to some F0 registers.  Handle F2 enable
++			 * as a special case.
++			 */
++			if (regaddr == SDIOD_CCCR_IOEN) {
++#if defined(BT_OVER_SDIO)
++				do {
++				if (sd->func[3]) {
++					sd_info(("bcmsdh_sdmmc F3: *byte 0x%x\n", *byte));
++
++					if (*byte & SDIO_FUNC_ENABLE_3) {
++						sdio_claim_host(sd->func[3]);
++
++						/* Set Function 3 Block Size */
++						err_ret = sdio_set_block_size(sd->func[3],
++						sd_f3_blocksize);
++						if (err_ret) {
++							sd_err(("F3 blocksize set err%d\n",
++								err_ret));
++						}
++
++						/* Enable Function 3 */
++						sd_info(("bcmsdh_sdmmc F3: enable F3 fn %p\n",
++						sd->func[3]));
++						err_ret = sdio_enable_func(sd->func[3]);
++						if (err_ret) {
++							sd_err(("bcmsdh_sdmmc: enable F3 err:%d\n",
++								err_ret));
++						}
++
++						sdio_release_host(sd->func[3]);
++
++						break;
++					} else if (*byte & SDIO_FUNC_DISABLE_3) {
++						sdio_claim_host(sd->func[3]);
++
++						/* Disable Function 3 */
++						sd_info(("bcmsdh_sdmmc F3: disable F3 fn %p\n",
++						sd->func[3]));
++						err_ret = sdio_disable_func(sd->func[3]);
++						if (err_ret) {
++							sd_err(("bcmsdh_sdmmc: Disable F3 err:%d\n",
++								err_ret));
++						}
++						sdio_release_host(sd->func[3]);
++						sd->func[3] = NULL;
++
++						break;
++					}
++				}
++#endif /* defined (BT_OVER_SDIO) */
++				if (sd->func[2]) {
++					sdio_claim_host(sd->func[2]);
++					if (*byte & SDIO_FUNC_ENABLE_2) {
++						/* Enable Function 2 */
++						err_ret = sdio_enable_func(sd->func[2]);
++						if (err_ret) {
++							sd_err(("bcmsdh_sdmmc: enable F2 failed:%d\n",
++								err_ret));
++						}
++					} else {
++						/* Disable Function 2 */
++						err_ret = sdio_disable_func(sd->func[2]);
++						if (err_ret) {
++							sd_err(("bcmsdh_sdmmc: Disab F2 failed:%d\n",
++								err_ret));
++						}
++					}
++					sdio_release_host(sd->func[2]);
++				}
++#if defined(BT_OVER_SDIO)
++			} while (0);
++#endif /* defined (BT_OVER_SDIO) */
++		}
++#if defined(MMC_SDIO_ABORT)
++			/* to allow abort command through F1 */
++			else if (regaddr == SDIOD_CCCR_IOABORT) {
++				while (sdio_abort_retry--) {
++					if (sd->func[func]) {
++						sdio_claim_host(sd->func[func]);
++						/*
++						 * this sdio_f0_writeb() can be replaced with
++						 * another api depending upon MMC driver change.
++						 * As of this time, this is temporaray one
++						 */
++						sdio_writeb(sd->func[func],
++							*byte, regaddr, &err_ret);
++						sdio_release_host(sd->func[func]);
++					}
++					if (!err_ret)
++						break;
++				}
++			}
++#endif /* MMC_SDIO_ABORT */
++			/* to allow abort command through F1 */
++#if defined(SDIO_ISR_THREAD)
++			else if (regaddr == SDIOD_CCCR_INTR_EXTN) {
++				while (sdio_abort_retry--) {
++					if (sd->func[func]) {
++						sdio_claim_host(sd->func[func]);
++						/*
++						 * this sdio_f0_writeb() can be replaced with
++						 * another api depending upon MMC driver change.
++						 * As of this time, this is temporaray one
++						 */
++						sdio_writeb(sd->func[func],
++							*byte, regaddr, &err_ret);
++						sdio_release_host(sd->func[func]);
++					}
++					if (!err_ret)
++						break;
++				}
++			}
++#endif
++			else if (regaddr < 0xF0) {
++				sd_err(("bcmsdh_sdmmc: F0 Wr:0x%02x: write disallowed\n", regaddr));
++			} else {
++				/* Claim host controller, perform F0 write, and release */
++				if (sd->func[func]) {
++					sdio_claim_host(sd->func[func]);
++					sdio_f0_writeb(sd->func[func],
++						*byte, regaddr, &err_ret);
++					sdio_release_host(sd->func[func]);
++				}
++			}
++		} else {
++			/* Claim host controller, perform Fn write, and release */
++			if (sd->func[func]) {
++				sdio_claim_host(sd->func[func]);
++				sdio_writeb(sd->func[func], *byte, regaddr, &err_ret);
++				sdio_release_host(sd->func[func]);
++			}
++		}
++	} else { /* CMD52 Read */
++		/* Claim host controller, perform Fn read, and release */
++		if (sd->func[func]) {
++			sdio_claim_host(sd->func[func]);
++			if (func == 0) {
++				*byte = sdio_f0_readb(sd->func[func], regaddr, &err_ret);
++			} else {
++				*byte = sdio_readb(sd->func[func], regaddr, &err_ret);
++			}
++			sdio_release_host(sd->func[func]);
++		}
++	}
++
++	if (err_ret) {
++		if ((regaddr == 0x1001F) && ((err_ret == -ETIMEDOUT) || (err_ret == -EILSEQ))) {
++		} else {
++			sd_err(("bcmsdh_sdmmc: Failed to %s byte F%d:@0x%05x=%02x, Err: %d\n",
++				rw ? "Write" : "Read", func, regaddr, *byte, err_ret));
++		}
++	}
++
++	if (sd_msglevel & SDH_COST_VAL) {
++		osl_do_gettimeofday(&now);
++		sd_cost(("%s: rw=%d len=1 cost=%lds %luus\n", __FUNCTION__,
++			rw, now.tv_sec-before.tv_sec, now.tv_nsec/1000-before.tv_nsec/1000));
++	}
++
++	return ((err_ret == 0) ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
++}
++
++uint
++sdioh_set_mode(sdioh_info_t *sd, uint mode)
++{
++	if (mode == SDPCM_TXGLOM_CPY)
++		sd->txglom_mode = mode;
++	else if (mode == SDPCM_TXGLOM_MDESC)
++		sd->txglom_mode = mode;
++
++	return (sd->txglom_mode);
++}
++
++extern SDIOH_API_RC
++sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func, uint addr,
++                                   uint32 *word, uint nbytes)
++{
++	int err_ret = SDIOH_API_RC_FAIL;
++	int err_ret2 = SDIOH_API_RC_SUCCESS; // terence 20130621: prevent dhd_dpc in dead lock
++#if defined(MMC_SDIO_ABORT)
++	int sdio_abort_retry = MMC_SDIO_ABORT_RETRY_LIMIT;
++#endif
++	struct osl_timespec now, before;
++
++	if (sd_msglevel & SDH_COST_VAL)
++		osl_do_gettimeofday(&before);
++
++	if (func == 0) {
++		sd_err(("%s: Only CMD52 allowed to F0.\n", __FUNCTION__));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	sd_info(("%s: cmd_type=%d, rw=%d, func=%d, addr=0x%05x, nbytes=%d\n",
++	         __FUNCTION__, cmd_type, rw, func, addr, nbytes));
++
++	DHD_PM_RESUME_WAIT(sdioh_request_word_wait);
++	DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
++	/* Claim host controller */
++	sdio_claim_host(sd->func[func]);
++
++	if(rw) { /* CMD52 Write */
++		if (nbytes == 4) {
++			sdio_writel(sd->func[func], *word, addr, &err_ret);
++		} else if (nbytes == 2) {
++			sdio_writew(sd->func[func], (*word & 0xFFFF), addr, &err_ret);
++		} else {
++			sd_err(("%s: Invalid nbytes: %d\n", __FUNCTION__, nbytes));
++		}
++	} else { /* CMD52 Read */
++		if (nbytes == 4) {
++			*word = sdio_readl(sd->func[func], addr, &err_ret);
++		} else if (nbytes == 2) {
++			*word = sdio_readw(sd->func[func], addr, &err_ret) & 0xFFFF;
++		} else {
++			sd_err(("%s: Invalid nbytes: %d\n", __FUNCTION__, nbytes));
++		}
++	}
++
++	/* Release host controller */
++	sdio_release_host(sd->func[func]);
++
++	if (err_ret) {
++#if defined(MMC_SDIO_ABORT)
++		/* Any error on CMD53 transaction should abort that function using function 0. */
++		while (sdio_abort_retry--) {
++			if (sd->func[0]) {
++				sdio_claim_host(sd->func[0]);
++				/*
++				 * this sdio_f0_writeb() can be replaced with another api
++				 * depending upon MMC driver change.
++				 * As of this time, this is temporaray one
++				 */
++				sdio_writeb(sd->func[0],
++					func, SDIOD_CCCR_IOABORT, &err_ret2);
++				sdio_release_host(sd->func[0]);
++			}
++			if (!err_ret2)
++				break;
++		}
++		if (err_ret)
++#endif /* MMC_SDIO_ABORT */
++		{
++			sd_err(("bcmsdh_sdmmc: Failed to %s word F%d:@0x%05x=%02x, Err: 0x%08x\n",
++				rw ? "Write" : "Read", func, addr, *word, err_ret));
++		}
++	}
++
++	if (sd_msglevel & SDH_COST_VAL) {
++		osl_do_gettimeofday(&now);
++		sd_cost(("%s: rw=%d, len=%d cost=%lds %luus\n", __FUNCTION__,
++			rw, nbytes, now.tv_sec-before.tv_sec, now.tv_nsec/1000 - before.tv_nsec/1000));
++	}
++
++	return (((err_ret == 0)&&(err_ret2 == 0)) ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
++}
++
++#ifdef BCMSDIOH_TXGLOM
++static SDIOH_API_RC
++sdioh_request_packet_chain(sdioh_info_t *sd, uint fix_inc, uint write, uint func,
++                     uint addr, void *pkt)
++{
++	bool fifo = (fix_inc == SDIOH_DATA_FIX);
++	int err_ret = 0;
++	void *pnext;
++	uint ttl_len, pkt_offset;
++	uint blk_num;
++	uint blk_size;
++	uint max_blk_count;
++	uint max_req_size;
++	struct mmc_request mmc_req;
++	struct mmc_command mmc_cmd;
++	struct mmc_data mmc_dat;
++	uint32 sg_count;
++	struct sdio_func *sdio_func = sd->func[func];
++	struct mmc_host *host = sdio_func->card->host;
++	uint8 *localbuf = NULL;
++	uint local_plen = 0;
++	uint pkt_len = 0;
++	struct osl_timespec now, before;
++
++	sd_trace(("%s: Enter\n", __FUNCTION__));
++	ASSERT(pkt);
++	DHD_PM_RESUME_WAIT(sdioh_request_packet_wait);
++	DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
++
++	if (sd_msglevel & SDH_COST_VAL)
++		osl_do_gettimeofday(&before);
++
++	blk_size = sd->client_block_size[func];
++	max_blk_count = min(host->max_blk_count, (uint)MAX_IO_RW_EXTENDED_BLK);
++	max_req_size = min(max_blk_count * blk_size, host->max_req_size);
++
++	pkt_offset = 0;
++	pnext = pkt;
++
++	ttl_len = 0;
++	sg_count = 0;
++	if(sd->txglom_mode == SDPCM_TXGLOM_MDESC) {
++	while (pnext != NULL) {
++		ttl_len = 0;
++		sg_count = 0;
++		memset(&mmc_req, 0, sizeof(struct mmc_request));
++		memset(&mmc_cmd, 0, sizeof(struct mmc_command));
++		memset(&mmc_dat, 0, sizeof(struct mmc_data));
++		sg_init_table(sd->sg_list, ARRAYSIZE(sd->sg_list));
++
++		/* Set up scatter-gather DMA descriptors. this loop is to find out the max
++		 * data we can transfer with one command 53. blocks per command is limited by
++		 * host max_req_size and 9-bit max block number. when the total length of this
++		 * packet chain is bigger than max_req_size, use multiple SD_IO_RW_EXTENDED
++		 * commands (each transfer is still block aligned)
++		 */
++		while (pnext != NULL && ttl_len < max_req_size) {
++			int pkt_len;
++			int sg_data_size;
++			uint8 *pdata = (uint8*)PKTDATA(sd->osh, pnext);
++
++			ASSERT(pdata != NULL);
++			pkt_len = PKTLEN(sd->osh, pnext);
++			sd_trace(("%s[%d] data=%p, len=%d\n", __FUNCTION__, write, pdata, pkt_len));
++			/* sg_count is unlikely larger than the array size, and this is
++			 * NOT something we can handle here, but in case it happens, PLEASE put
++			 * a restriction on max tx/glom count (based on host->max_segs).
++			 */
++			if (sg_count >= ARRAYSIZE(sd->sg_list)) {
++				sd_err(("%s: sg list entries exceed limit %d\n", __FUNCTION__, sg_count));
++				return (SDIOH_API_RC_FAIL);
++			}
++			pdata += pkt_offset;
++
++			sg_data_size = pkt_len - pkt_offset;
++			if (sg_data_size > max_req_size - ttl_len)
++				sg_data_size = max_req_size - ttl_len;
++			/* some platforms put a restriction on the data size of each scatter-gather
++			 * DMA descriptor, use multiple sg buffers when xfer_size is bigger than
++			 * max_seg_size
++			 */
++			if (sg_data_size > host->max_seg_size)
++				sg_data_size = host->max_seg_size;
++			sg_set_buf(&sd->sg_list[sg_count++], pdata, sg_data_size);
++
++			ttl_len += sg_data_size;
++			pkt_offset += sg_data_size;
++			if (pkt_offset == pkt_len) {
++				pnext = PKTNEXT(sd->osh, pnext);
++				pkt_offset = 0;
++			}
++		}
++
++		if (ttl_len % blk_size != 0) {
++			sd_err(("%s, data length %d not aligned to block size %d\n",
++				__FUNCTION__,  ttl_len, blk_size));
++			return SDIOH_API_RC_FAIL;
++		}
++		blk_num = ttl_len / blk_size;
++		mmc_dat.sg = sd->sg_list;
++		mmc_dat.sg_len = sg_count;
++		mmc_dat.blksz = blk_size;
++		mmc_dat.blocks = blk_num;
++		mmc_dat.flags = write ? MMC_DATA_WRITE : MMC_DATA_READ;
++		mmc_cmd.opcode = 53; /* SD_IO_RW_EXTENDED */
++		mmc_cmd.arg = write ? 1<<31 : 0;
++		mmc_cmd.arg |= (func & 0x7) << 28;
++		mmc_cmd.arg |= 1<<27;
++		mmc_cmd.arg |= fifo ? 0 : 1<<26;
++		mmc_cmd.arg |= (addr & 0x1FFFF) << 9;
++		mmc_cmd.arg |= blk_num & 0x1FF;
++		mmc_cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
++		mmc_req.cmd = &mmc_cmd;
++		mmc_req.data = &mmc_dat;
++		if (!fifo)
++			addr += ttl_len;
++
++		sdio_claim_host(sdio_func);
++		mmc_set_data_timeout(&mmc_dat, sdio_func->card);
++		mmc_wait_for_req(host, &mmc_req);
++		sdio_release_host(sdio_func);
++
++		err_ret = mmc_cmd.error? mmc_cmd.error : mmc_dat.error;
++		if (0 != err_ret) {
++			sd_err(("%s:CMD53 %s failed with code %d\n",
++				__FUNCTION__, write ? "write" : "read", err_ret));
++			return SDIOH_API_RC_FAIL;
++		}
++	}
++	} else if(sd->txglom_mode == SDPCM_TXGLOM_CPY) {
++		for (pnext = pkt; pnext; pnext = PKTNEXT(sd->osh, pnext)) {
++			ttl_len += PKTLEN(sd->osh, pnext);
++		}
++		/* Claim host controller */
++		sdio_claim_host(sd->func[func]);
++		for (pnext = pkt; pnext; pnext = PKTNEXT(sd->osh, pnext)) {
++			uint8 *buf = (uint8*)PKTDATA(sd->osh, pnext);
++			pkt_len = PKTLEN(sd->osh, pnext);
++
++			if (!localbuf) {
++				localbuf = (uint8 *)MALLOC(sd->osh, ttl_len);
++				if (localbuf == NULL) {
++					sd_err(("%s: %s TXGLOM: localbuf malloc FAILED\n",
++						__FUNCTION__, (write) ? "TX" : "RX"));
++					goto txglomfail;
++				}
++			}
++
++			bcopy(buf, (localbuf + local_plen), pkt_len);
++			local_plen += pkt_len;
++			if (PKTNEXT(sd->osh, pnext))
++				continue;
++
++			buf = localbuf;
++			pkt_len = local_plen;
++txglomfail:
++			/* Align Patch */
++			if (!write || pkt_len < 32)
++				pkt_len = (pkt_len + 3) & 0xFFFFFFFC;
++			else if (pkt_len % blk_size)
++				pkt_len += blk_size - (pkt_len % blk_size);
++
++			if ((write) && (!fifo))
++				err_ret = sdio_memcpy_toio(sd->func[func], addr, buf, pkt_len);
++			else if (write)
++				err_ret = sdio_memcpy_toio(sd->func[func], addr, buf, pkt_len);
++			else if (fifo)
++				err_ret = sdio_readsb(sd->func[func], buf, addr, pkt_len);
++			else
++				err_ret = sdio_memcpy_fromio(sd->func[func], buf, addr, pkt_len);
++
++			if (err_ret)
++				sd_err(("%s: %s FAILED %p[%d], addr=0x%05x, pkt_len=%d, ERR=%d\n",
++				       __FUNCTION__,
++				       (write) ? "TX" : "RX",
++				       pnext, sg_count, addr, pkt_len, err_ret));
++			else
++				sd_trace(("%s: %s xfr'd %p[%d], addr=0x%05x, len=%d\n",
++					__FUNCTION__,
++					(write) ? "TX" : "RX",
++					pnext, sg_count, addr, pkt_len));
++
++			if (!fifo)
++				addr += pkt_len;
++			sg_count ++;
++		}
++		sdio_release_host(sd->func[func]);
++	} else {
++		sd_err(("%s: set to wrong glom mode %d\n", __FUNCTION__, sd->txglom_mode));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	if (localbuf)
++		MFREE(sd->osh, localbuf, ttl_len);
++
++	if (sd_msglevel & SDH_COST_VAL) {
++		osl_do_gettimeofday(&now);
++		sd_cost(("%s: rw=%d, ttl_len=%d, cost=%lds %luus\n", __FUNCTION__,
++			write, ttl_len, now.tv_sec-before.tv_sec, now.tv_nsec/1000-before.tv_nsec/1000));
++	}
++
++	sd_trace(("%s: Exit\n", __FUNCTION__));
++	return SDIOH_API_RC_SUCCESS;
++}
++#endif /* BCMSDIOH_TXGLOM */
++
++static SDIOH_API_RC
++sdioh_buffer_tofrom_bus(sdioh_info_t *sd, uint fix_inc, uint write, uint func,
++                     uint addr, uint8 *buf, uint len)
++{
++	bool fifo = (fix_inc == SDIOH_DATA_FIX);
++	int err_ret = 0;
++	struct osl_timespec now, before;
++
++	sd_trace(("%s: Enter\n", __FUNCTION__));
++	ASSERT(buf);
++
++	if (sd_msglevel & SDH_COST_VAL)
++		osl_do_gettimeofday(&before);
++
++	/* NOTE:
++	 * For all writes, each packet length is aligned to 32 (or 4)
++	 * bytes in dhdsdio_txpkt_preprocess, and for glom the last packet length
++	 * is aligned to block boundary. If you want to align each packet to
++	 * a custom size, please do it in dhdsdio_txpkt_preprocess, NOT here
++	 *
++	 * For reads, the alignment is doen in sdioh_request_buffer.
++	 *
++	 */
++	sdio_claim_host(sd->func[func]);
++
++	if ((write) && (!fifo))
++		err_ret = sdio_memcpy_toio(sd->func[func], addr, buf, len);
++	else if (write)
++		err_ret = sdio_memcpy_toio(sd->func[func], addr, buf, len);
++	else if (fifo)
++		err_ret = sdio_readsb(sd->func[func], buf, addr, len);
++	else
++		err_ret = sdio_memcpy_fromio(sd->func[func], buf, addr, len);
++
++	sdio_release_host(sd->func[func]);
++
++	if (err_ret)
++		sd_err(("%s: %s FAILED %p, addr=0x%05x, pkt_len=%d, ERR=%d\n", __FUNCTION__,
++		       (write) ? "TX" : "RX", buf, addr, len, err_ret));
++	else
++		sd_trace(("%s: %s xfr'd %p, addr=0x%05x, len=%d\n", __FUNCTION__,
++			(write) ? "TX" : "RX", buf, addr, len));
++
++	sd_trace(("%s: Exit\n", __FUNCTION__));
++
++	if (sd_msglevel & SDH_COST_VAL) {
++		osl_do_gettimeofday(&now);
++		sd_cost(("%s: rw=%d, len=%d cost=%lds %luus\n", __FUNCTION__,
++			write, len, now.tv_sec-before.tv_sec, now.tv_nsec/1000 - before.tv_nsec/1000));
++	}
++
++	return ((err_ret == 0) ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
++}
++
++
++/*
++ * This function takes a buffer or packet, and fixes everything up so that in the
++ * end, a DMA-able packet is created.
++ *
++ * A buffer does not have an associated packet pointer, and may or may not be aligned.
++ * A packet may consist of a single packet, or a packet chain.  If it is a packet chain,
++ * then all the packets in the chain must be properly aligned.  If the packet data is not
++ * aligned, then there may only be one packet, and in this case, it is copied to a new
++ * aligned packet.
++ *
++ */
++extern SDIOH_API_RC
++sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint write, uint func,
++	uint addr, uint reg_width, uint buf_len, uint8 *buffer, void *pkt)
++{
++	SDIOH_API_RC status;
++	void *tmppkt;
++	struct osl_timespec now, before;
++
++	sd_trace(("%s: Enter\n", __FUNCTION__));
++	DHD_PM_RESUME_WAIT(sdioh_request_buffer_wait);
++	DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
++
++	if (sd_msglevel & SDH_COST_VAL)
++		osl_do_gettimeofday(&before);
++
++	if (pkt) {
++#ifdef BCMSDIOH_TXGLOM
++		/* packet chain, only used for tx/rx glom, all packets length
++		 * are aligned, total length is a block multiple
++		 */
++		if (PKTNEXT(sd->osh, pkt))
++			return sdioh_request_packet_chain(sd, fix_inc, write, func, addr, pkt);
++#endif /* BCMSDIOH_TXGLOM */
++		/* non-glom mode, ignore the buffer parameter and use the packet pointer
++		 * (this shouldn't happen)
++		 */
++		buffer = PKTDATA(sd->osh, pkt);
++		buf_len = PKTLEN(sd->osh, pkt);
++	}
++
++	ASSERT(buffer);
++
++	/* buffer and length are aligned, use it directly so we can avoid memory copy */
++	if (((ulong)buffer & DMA_ALIGN_MASK) == 0 && (buf_len & DMA_ALIGN_MASK) == 0)
++		return sdioh_buffer_tofrom_bus(sd, fix_inc, write, func, addr, buffer, buf_len);
++
++	sd_trace(("%s: [%d] doing memory copy buf=%p, len=%d\n",
++		__FUNCTION__, write, buffer, buf_len));
++
++	/* otherwise, a memory copy is needed as the input buffer is not aligned */
++	tmppkt = PKTGET_STATIC(sd->osh, buf_len + DEFAULT_SDIO_F2_BLKSIZE, write ? TRUE : FALSE);
++	if (tmppkt == NULL) {
++		sd_err(("%s: PKTGET failed: len %d\n", __FUNCTION__, buf_len));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	if (write)
++		bcopy(buffer, PKTDATA(sd->osh, tmppkt), buf_len);
++
++	status = sdioh_buffer_tofrom_bus(sd, fix_inc, write, func, addr,
++		PKTDATA(sd->osh, tmppkt), ROUNDUP(buf_len, (DMA_ALIGN_MASK+1)));
++
++	if (!write)
++		bcopy(PKTDATA(sd->osh, tmppkt), buffer, buf_len);
++
++	PKTFREE_STATIC(sd->osh, tmppkt, write ? TRUE : FALSE);
++
++	if (sd_msglevel & SDH_COST_VAL) {
++		osl_do_gettimeofday(&now);
++		sd_cost(("%s: len=%d cost=%lds %luus\n", __FUNCTION__,
++			buf_len, now.tv_sec-before.tv_sec, now.tv_nsec/1000 - before.tv_nsec/1000));
++	}
++
++	return status;
++}
++
++/* this function performs "abort" for both of host & device */
++extern int
++sdioh_abort(sdioh_info_t *sd, uint func)
++{
++#if defined(MMC_SDIO_ABORT)
++	char t_func = (char) func;
++#endif /* defined(MMC_SDIO_ABORT) */
++	sd_trace(("%s: Enter\n", __FUNCTION__));
++
++#if defined(MMC_SDIO_ABORT)
++	/* issue abort cmd52 command through F1 */
++	sdioh_request_byte(sd, SD_IO_OP_WRITE, SDIO_FUNC_0, SDIOD_CCCR_IOABORT, &t_func);
++#endif /* defined(MMC_SDIO_ABORT) */
++
++	sd_trace(("%s: Exit\n", __FUNCTION__));
++	return SDIOH_API_RC_SUCCESS;
++}
++
++/* Reset and re-initialize the device */
++int sdioh_sdio_reset(sdioh_info_t *si)
++{
++	sd_trace(("%s: Enter\n", __FUNCTION__));
++	sd_trace(("%s: Exit\n", __FUNCTION__));
++	return SDIOH_API_RC_SUCCESS;
++}
++
++/* Disable device interrupt */
++void
++sdioh_sdmmc_devintr_off(sdioh_info_t *sd)
++{
++	sd_trace(("%s: %d\n", __FUNCTION__, sd->use_client_ints));
++	sd->intmask &= ~CLIENT_INTR;
++}
++
++/* Enable device interrupt */
++void
++sdioh_sdmmc_devintr_on(sdioh_info_t *sd)
++{
++	sd_trace(("%s: %d\n", __FUNCTION__, sd->use_client_ints));
++	sd->intmask |= CLIENT_INTR;
++}
++
++/* Read client card reg */
++int
++sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data)
++{
++
++	if ((func == 0) || (regsize == 1)) {
++		uint8 temp = 0;
++
++		sdioh_request_byte(sd, SDIOH_READ, func, regaddr, &temp);
++		*data = temp;
++		*data &= 0xff;
++		sd_data(("%s: byte read data=0x%02x\n",
++		         __FUNCTION__, *data));
++	} else {
++		if (sdioh_request_word(sd, 0, SDIOH_READ, func, regaddr, data, regsize)) {
++			return BCME_SDIO_ERROR;
++		}
++
++		if (regsize == 2)
++			*data &= 0xffff;
++
++		sd_data(("%s: word read data=0x%08x\n",
++		         __FUNCTION__, *data));
++	}
++
++	return SUCCESS;
++}
++
++#if !defined(OOB_INTR_ONLY)
++/* bcmsdh_sdmmc interrupt handler */
++static void IRQHandler(struct sdio_func *func)
++{
++	sdioh_info_t *sd;
++
++	sd = sdio_get_drvdata(func);
++
++	ASSERT(sd != NULL);
++	sdio_release_host(sd->func[0]);
++
++	if (sd->use_client_ints) {
++		sd->intrcount++;
++		ASSERT(sd->intr_handler);
++		ASSERT(sd->intr_handler_arg);
++		(sd->intr_handler)(sd->intr_handler_arg);
++	} else {
++		sd_err(("bcmsdh_sdmmc: ***IRQHandler\n"));
++
++		sd_err(("%s: Not ready for intr: enabled %d, handler %p\n",
++		        __FUNCTION__, sd->client_intr_enabled, sd->intr_handler));
++	}
++
++	sdio_claim_host(sd->func[0]);
++}
++
++/* bcmsdh_sdmmc interrupt handler for F2 (dummy handler) */
++static void IRQHandlerF2(struct sdio_func *func)
++{
++	sd_trace(("bcmsdh_sdmmc: ***IRQHandlerF2\n"));
++}
++#endif /* !defined(OOB_INTR_ONLY) */
++
++#ifdef NOTUSED
++/* Write client card reg */
++static int
++sdioh_sdmmc_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 data)
++{
++
++	if ((func == 0) || (regsize == 1)) {
++		uint8 temp;
++
++		temp = data & 0xff;
++		sdioh_request_byte(sd, SDIOH_READ, func, regaddr, &temp);
++		sd_data(("%s: byte write data=0x%02x\n",
++		         __FUNCTION__, data));
++	} else {
++		if (regsize == 2)
++			data &= 0xffff;
++
++		sdioh_request_word(sd, 0, SDIOH_READ, func, regaddr, &data, regsize);
++
++		sd_data(("%s: word write data=0x%08x\n",
++		         __FUNCTION__, data));
++	}
++
++	return SUCCESS;
++}
++#endif /* NOTUSED */
++
++int
++sdioh_start(sdioh_info_t *sd, int stage)
++{
++	int ret;
++
++	if (!sd) {
++		sd_err(("%s Failed, sd is NULL\n", __FUNCTION__));
++		return (0);
++	}
++
++	/* Need to do this stages as we can't enable the interrupt till
++		downloading of the firmware is complete, other wise polling
++		sdio access will come in way
++	*/
++	if (sd->func[0]) {
++			if (stage == 0) {
++		/* Since the power to the chip is killed, we will have
++			re enumerate the device again. Set the block size
++			and enable the fucntion 1 for in preparation for
++			downloading the code
++		*/
++		/* sdio_reset_comm() - has been fixed in latest kernel/msm.git for Linux
++		   2.6.27. The implementation prior to that is buggy, and needs broadcom's
++		   patch for it
++		*/
++#if defined(ENABLE_INSMOD_NO_FW_LOAD) && !defined(BUS_POWER_RESTORE)
++		if ((ret = sdio_reset_comm(sd->func[0]->card))) {
++			sd_err(("%s Failed, error = %d\n", __FUNCTION__, ret));
++			return ret;
++		} else
++#endif
++		{
++			sd->num_funcs = 2;
++			sd->sd_blockmode = TRUE;
++			sd->use_client_ints = TRUE;
++			sd->client_block_size[0] = 64;
++
++			if (sd->func[1]) {
++				/* Claim host controller */
++				sdio_claim_host(sd->func[1]);
++
++				sd->client_block_size[1] = 64;
++				ret = sdio_set_block_size(sd->func[1], 64);
++				if (ret) {
++					sd_err(("bcmsdh_sdmmc: Failed to set F1 "
++						"blocksize(%d)\n", ret));
++				}
++
++				/* Release host controller F1 */
++				sdio_release_host(sd->func[1]);
++			}
++
++			if (sd->func[2]) {
++				/* Claim host controller F2 */
++				sdio_claim_host(sd->func[2]);
++
++				sd->client_block_size[2] = sd_f2_blocksize;
++				printf("%s: set sd_f2_blocksize %d\n", __FUNCTION__, sd_f2_blocksize);
++				ret = sdio_set_block_size(sd->func[2], sd_f2_blocksize);
++				if (ret) {
++					sd_err(("bcmsdh_sdmmc: Failed to set F2 "
++						"blocksize to %d(%d)\n", sd_f2_blocksize, ret));
++				}
++
++				/* Release host controller F2 */
++				sdio_release_host(sd->func[2]);
++			}
++
++			sdioh_sdmmc_card_enablefuncs(sd);
++			}
++		} else {
++#if !defined(OOB_INTR_ONLY)
++			sdio_claim_host(sd->func[0]);
++			if (sd->func[2])
++				sdio_claim_irq(sd->func[2], IRQHandlerF2);
++			if (sd->func[1])
++				sdio_claim_irq(sd->func[1], IRQHandler);
++			sdio_release_host(sd->func[0]);
++#else /* defined(OOB_INTR_ONLY) */
++#if defined(HW_OOB)
++			sdioh_enable_func_intr(sd);
++#endif
++			bcmsdh_oob_intr_set(sd->bcmsdh, TRUE);
++#endif /* !defined(OOB_INTR_ONLY) */
++		}
++	}
++	else
++		sd_err(("%s Failed\n", __FUNCTION__));
++
++	return (0);
++}
++
++int
++sdioh_stop(sdioh_info_t *sd)
++{
++	/* MSM7201A Android sdio stack has bug with interrupt
++		So internaly within SDIO stack they are polling
++		which cause issue when device is turned off. So
++		unregister interrupt with SDIO stack to stop the
++		polling
++	*/
++	if (sd->func[0]) {
++#if !defined(OOB_INTR_ONLY)
++		sdio_claim_host(sd->func[0]);
++		if (sd->func[1])
++			sdio_release_irq(sd->func[1]);
++		if (sd->func[2])
++			sdio_release_irq(sd->func[2]);
++		sdio_release_host(sd->func[0]);
++#else /* defined(OOB_INTR_ONLY) */
++#if defined(HW_OOB)
++		sdioh_disable_func_intr(sd);
++#endif
++		bcmsdh_oob_intr_set(sd->bcmsdh, FALSE);
++#endif /* !defined(OOB_INTR_ONLY) */
++	}
++	else
++		sd_err(("%s Failed\n", __FUNCTION__));
++	return (0);
++}
++
++int
++sdioh_waitlockfree(sdioh_info_t *sd)
++{
++	return (1);
++}
++
++
++SDIOH_API_RC
++sdioh_gpioouten(sdioh_info_t *sd, uint32 gpio)
++{
++	return SDIOH_API_RC_FAIL;
++}
++
++SDIOH_API_RC
++sdioh_gpioout(sdioh_info_t *sd, uint32 gpio, bool enab)
++{
++	return SDIOH_API_RC_FAIL;
++}
++
++bool
++sdioh_gpioin(sdioh_info_t *sd, uint32 gpio)
++{
++	return FALSE;
++}
++
++SDIOH_API_RC
++sdioh_gpio_init(sdioh_info_t *sd)
++{
++	return SDIOH_API_RC_FAIL;
++}
++
++uint
++sdmmc_get_clock_rate(sdioh_info_t *sd)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) || (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0))
++	return 0;
++#else
++	struct sdio_func *sdio_func = sd->func[0];
++	struct mmc_host *host = sdio_func->card->host;
++	return mmc_host_clk_rate(host);
++#endif
++}
++
++
++void
++sdmmc_set_clock_rate(sdioh_info_t *sd, uint hz)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) || (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0))
++	return;
++#else
++	struct sdio_func *sdio_func = sd->func[0];
++	struct mmc_host *host = sdio_func->card->host;
++	struct mmc_ios *ios = &host->ios;
++
++	mmc_host_clk_hold(host);
++	DHD_INFO(("%s: Before change: sd clock rate is %u\n", __FUNCTION__, ios->clock));
++	if (hz < host->f_min) {
++		DHD_ERROR(("%s: Intended rate is below min rate, setting to min\n", __FUNCTION__));
++		hz = host->f_min;
++	}
++
++	if (hz > host->f_max) {
++		DHD_ERROR(("%s: Intended rate exceeds max rate, setting to max\n", __FUNCTION__));
++		hz = host->f_max;
++	}
++	ios->clock = hz;
++	host->ops->set_ios(host, ios);
++	DHD_ERROR(("%s: After change: sd clock rate is %u\n", __FUNCTION__, ios->clock));
++	mmc_host_clk_release(host);
++#endif
++}
++
++void
++sdmmc_set_clock_divisor(sdioh_info_t *sd, uint sd_div)
++{
++	uint hz;
++	uint old_div = sdmmc_get_clock_rate(sd);
++	if (old_div == sd_div) {
++		return;
++	}
++
++	hz = sd->sd_clk_rate / sd_div;
++	sdmmc_set_clock_rate(sd, hz);
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc_linux.c b/module_drivers/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc_linux.c
+new file mode 100644
+index 000000000..dd5d3bab5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc_linux.c
+@@ -0,0 +1,405 @@
++/*
++ * BCMSDH Function Driver for the native SDIO/MMC driver in the Linux Kernel
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Proprietary,Open:>>
++ *
++ * $Id: bcmsdh_sdmmc_linux.c 644124 2016-06-17 07:59:34Z $
++ */
++
++#include <typedefs.h>
++#include <bcmutils.h>
++#include <sdio.h>	/* SDIO Device and Protocol Specs */
++#include <bcmsdbus.h>	/* bcmsdh to/from specific controller APIs */
++#include <sdiovar.h>	/* to get msglevel bit values */
++
++#include <linux/sched.h>	/* request_irq() */
++
++#include <linux/mmc/core.h>
++#include <linux/mmc/card.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/sdio_func.h>
++#include <linux/mmc/sdio_ids.h>
++#include <dhd_linux.h>
++#include <bcmsdh_sdmmc.h>
++#include <dhd_dbg.h>
++
++#if !defined(SDIO_VENDOR_ID_BROADCOM)
++#define SDIO_VENDOR_ID_BROADCOM		0x02d0
++#endif /* !defined(SDIO_VENDOR_ID_BROADCOM) */
++
++#define SDIO_DEVICE_ID_BROADCOM_DEFAULT	0x0000
++
++#if !defined(SDIO_DEVICE_ID_BROADCOM_4325_SDGWB)
++#define SDIO_DEVICE_ID_BROADCOM_4325_SDGWB	0x0492	/* BCM94325SDGWB */
++#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_4325_SDGWB) */
++#if !defined(SDIO_DEVICE_ID_BROADCOM_4325)
++#define SDIO_DEVICE_ID_BROADCOM_4325	0x0493
++#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_4325) */
++#if !defined(SDIO_DEVICE_ID_BROADCOM_4329)
++#define SDIO_DEVICE_ID_BROADCOM_4329	0x4329
++#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_4329) */
++#if !defined(SDIO_DEVICE_ID_BROADCOM_4319)
++#define SDIO_DEVICE_ID_BROADCOM_4319	0x4319
++#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_4319) */
++#if !defined(SDIO_DEVICE_ID_BROADCOM_4330)
++#define SDIO_DEVICE_ID_BROADCOM_4330	0x4330
++#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_4330) */
++#if !defined(SDIO_DEVICE_ID_BROADCOM_4334)
++#define SDIO_DEVICE_ID_BROADCOM_4334    0x4334
++#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_4334) */
++#if !defined(SDIO_DEVICE_ID_BROADCOM_4324)
++#define SDIO_DEVICE_ID_BROADCOM_4324    0x4324
++#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_4324) */
++#if !defined(SDIO_DEVICE_ID_BROADCOM_43239)
++#define SDIO_DEVICE_ID_BROADCOM_43239    43239
++#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_43239) */
++
++extern void wl_cfg80211_set_parent_dev(void *dev);
++extern void sdioh_sdmmc_devintr_off(sdioh_info_t *sd);
++extern void sdioh_sdmmc_devintr_on(sdioh_info_t *sd);
++extern void* bcmsdh_probe(osl_t *osh, void *dev, void *sdioh, void *adapter_info, uint bus_type,
++	uint bus_num, uint slot_num);
++extern int bcmsdh_remove(bcmsdh_info_t *bcmsdh);
++
++int sdio_function_init(void);
++void sdio_function_cleanup(void);
++
++#define DESCRIPTION "bcmsdh_sdmmc Driver"
++#define AUTHOR "Broadcom Corporation"
++
++/* module param defaults */
++static int clockoverride = 0;
++
++module_param(clockoverride, int, 0644);
++MODULE_PARM_DESC(clockoverride, "SDIO card clock override");
++
++#ifdef GLOBAL_SDMMC_INSTANCE
++PBCMSDH_SDMMC_INSTANCE gInstance;
++#endif
++
++/* Maximum number of bcmsdh_sdmmc devices supported by driver */
++#define BCMSDH_SDMMC_MAX_DEVICES 1
++
++extern volatile bool dhd_mmc_suspend;
++
++static int sdioh_probe(struct sdio_func *func)
++{
++	int host_idx = func->card->host->index;
++	uint32 rca = func->card->rca;
++	wifi_adapter_info_t *adapter;
++	osl_t *osh = NULL;
++	sdioh_info_t *sdioh = NULL;
++
++	sd_err(("bus num (host idx)=%d, slot num (rca)=%d\n", host_idx, rca));
++	adapter = dhd_wifi_platform_get_adapter(SDIO_BUS, host_idx, rca);
++	if (adapter != NULL) {
++		sd_err(("found adapter info '%s'\n", adapter->name));
++#ifdef BUS_POWER_RESTORE
++		adapter->sdio_func = func;
++#endif
++	} else
++		sd_err(("can't find adapter info for this chip\n"));
++
++#ifdef WL_CFG80211
++	wl_cfg80211_set_parent_dev(&func->dev);
++#endif
++
++	 /* allocate SDIO Host Controller state info */
++	 osh = osl_attach(&func->dev, SDIO_BUS, TRUE);
++	 if (osh == NULL) {
++		 sd_err(("%s: osl_attach failed\n", __FUNCTION__));
++		 goto fail;
++	 }
++	 osl_static_mem_init(osh, adapter);
++	 sdioh = sdioh_attach(osh, func);
++	 if (sdioh == NULL) {
++		 sd_err(("%s: sdioh_attach failed\n", __FUNCTION__));
++		 goto fail;
++	 }
++	 sdioh->bcmsdh = bcmsdh_probe(osh, &func->dev, sdioh, adapter, SDIO_BUS, host_idx, rca);
++	 if (sdioh->bcmsdh == NULL) {
++		 sd_err(("%s: bcmsdh_probe failed\n", __FUNCTION__));
++		 goto fail;
++	 }
++
++	sdio_set_drvdata(func, sdioh);
++	return 0;
++
++fail:
++	if (sdioh != NULL)
++		sdioh_detach(osh, sdioh);
++	if (osh != NULL)
++		osl_detach(osh);
++	return -ENOMEM;
++}
++
++static void sdioh_remove(struct sdio_func *func)
++{
++	sdioh_info_t *sdioh;
++	osl_t *osh;
++
++	sdioh = sdio_get_drvdata(func);
++	if (sdioh == NULL) {
++		sd_err(("%s: error, no sdioh handler found\n", __FUNCTION__));
++		return;
++	}
++	sd_err(("%s: Enter\n", __FUNCTION__));
++
++	osh = sdioh->osh;
++	bcmsdh_remove(sdioh->bcmsdh);
++	sdioh_detach(osh, sdioh);
++	osl_detach(osh);
++}
++
++static int bcmsdh_sdmmc_probe(struct sdio_func *func,
++                              const struct sdio_device_id *id)
++{
++	int ret = 0;
++
++	if (func == NULL)
++		return -EINVAL;
++
++	sd_err(("%s: Enter num=%d\n", __FUNCTION__, func->num));
++	sd_info(("sdio_bcmsdh: func->class=%x\n", func->class));
++	sd_info(("sdio_vendor: 0x%04x\n", func->vendor));
++	sd_info(("sdio_device: 0x%04x\n", func->device));
++	sd_info(("Function#: 0x%04x\n", func->num));
++
++#ifdef GLOBAL_SDMMC_INSTANCE
++	gInstance->func[func->num] = func;
++#endif
++
++	/* 4318 doesn't have function 2 */
++	if ((func->num == 2) || (func->num == 1 && func->device == 0x4))
++		ret = sdioh_probe(func);
++
++	return ret;
++}
++
++static void bcmsdh_sdmmc_remove(struct sdio_func *func)
++{
++	if (func == NULL) {
++		sd_err(("%s is called with NULL SDIO function pointer\n", __FUNCTION__));
++		return;
++	}
++
++	sd_trace(("bcmsdh_sdmmc: %s Enter\n", __FUNCTION__));
++	sd_info(("sdio_bcmsdh: func->class=%x\n", func->class));
++	sd_info(("sdio_vendor: 0x%04x\n", func->vendor));
++	sd_info(("sdio_device: 0x%04x\n", func->device));
++	sd_info(("Function#: 0x%04x\n", func->num));
++
++	if ((func->num == 2) || (func->num == 1 && func->device == 0x4))
++		sdioh_remove(func);
++}
++
++/* devices we support, null terminated */
++static const struct sdio_device_id bcmsdh_sdmmc_ids[] = {
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_DEFAULT) },
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4325_SDGWB) },
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4325) },
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4329) },
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4319) },
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4330) },
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4334) },
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4324) },
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_43239) },
++	{ SDIO_DEVICE_CLASS(SDIO_CLASS_NONE)		},
++	{ 0, 0, 0, 0 /* end: all zeroes */
++	},
++};
++
++MODULE_DEVICE_TABLE(sdio, bcmsdh_sdmmc_ids);
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39)) && defined(CONFIG_PM)
++static int bcmsdh_sdmmc_suspend(struct device *pdev)
++{
++	int err;
++	sdioh_info_t *sdioh;
++	struct sdio_func *func = dev_to_sdio_func(pdev);
++	mmc_pm_flag_t sdio_flags;
++
++	printf("%s Enter func->num=%d\n", __FUNCTION__, func->num);
++	if (func->num != 2)
++		return 0;
++
++	dhd_mmc_suspend = TRUE;
++	sdioh = sdio_get_drvdata(func);
++	err = bcmsdh_suspend(sdioh->bcmsdh);
++	if (err) {
++		printf("%s bcmsdh_suspend err=%d\n", __FUNCTION__, err);
++		dhd_mmc_suspend = FALSE;
++		return err;
++	}
++
++	sdio_flags = sdio_get_host_pm_caps(func);
++	if (!(sdio_flags & MMC_PM_KEEP_POWER)) {
++		sd_err(("%s: can't keep power while host is suspended\n", __FUNCTION__));
++		dhd_mmc_suspend = FALSE;
++		return  -EINVAL;
++	}
++
++	/* keep power while host suspended */
++	err = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
++	if (err) {
++		sd_err(("%s: error while trying to keep power\n", __FUNCTION__));
++		dhd_mmc_suspend = FALSE;
++		return err;
++	}
++	smp_mb();
++
++	printf("%s Exit\n", __FUNCTION__);
++	return 0;
++}
++
++static int bcmsdh_sdmmc_resume(struct device *pdev)
++{
++	sdioh_info_t *sdioh;
++	struct sdio_func *func = dev_to_sdio_func(pdev);
++
++	printf("%s Enter func->num=%d\n", __FUNCTION__, func->num);
++	if (func->num != 2)
++		return 0;
++
++	dhd_mmc_suspend = FALSE;
++	sdioh = sdio_get_drvdata(func);
++	bcmsdh_resume(sdioh->bcmsdh);
++
++	smp_mb();
++	printf("%s Exit\n", __FUNCTION__);
++	return 0;
++}
++
++static const struct dev_pm_ops bcmsdh_sdmmc_pm_ops = {
++	.suspend	= bcmsdh_sdmmc_suspend,
++	.resume		= bcmsdh_sdmmc_resume,
++};
++#endif  /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39)) && defined(CONFIG_PM) */
++
++#if defined(BCMLXSDMMC)
++static struct semaphore *notify_semaphore = NULL;
++
++static int dummy_probe(struct sdio_func *func,
++                              const struct sdio_device_id *id)
++{
++	if (func && (func->num != 2)) {
++		return 0;
++	}
++
++	if (notify_semaphore)
++		up(notify_semaphore);
++	return 0;
++}
++
++static void dummy_remove(struct sdio_func *func)
++{
++}
++
++static struct sdio_driver dummy_sdmmc_driver = {
++	.probe		= dummy_probe,
++	.remove		= dummy_remove,
++	.name		= "dummy_sdmmc",
++	.id_table	= bcmsdh_sdmmc_ids,
++	};
++
++int sdio_func_reg_notify(void* semaphore)
++{
++	notify_semaphore = semaphore;
++	return sdio_register_driver(&dummy_sdmmc_driver);
++}
++
++void sdio_func_unreg_notify(void)
++{
++	OSL_SLEEP(15);
++	sdio_unregister_driver(&dummy_sdmmc_driver);
++}
++
++#endif /* defined(BCMLXSDMMC) */
++
++static struct sdio_driver bcmsdh_sdmmc_driver = {
++	.probe		= bcmsdh_sdmmc_probe,
++	.remove		= bcmsdh_sdmmc_remove,
++	.name		= "bcmsdh_sdmmc",
++	.id_table	= bcmsdh_sdmmc_ids,
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39)) && defined(CONFIG_PM)
++	.drv = {
++	.pm	= &bcmsdh_sdmmc_pm_ops,
++	},
++#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39)) && defined(CONFIG_PM) */
++	};
++
++struct sdos_info {
++	sdioh_info_t *sd;
++	spinlock_t lock;
++};
++
++/* Interrupt enable/disable */
++SDIOH_API_RC
++sdioh_interrupt_set(sdioh_info_t *sd, bool enable)
++{
++	if (!sd)
++		return BCME_BADARG;
++
++	sd_trace(("%s: %s\n", __FUNCTION__, enable ? "Enabling" : "Disabling"));
++	return SDIOH_API_RC_SUCCESS;
++}
++
++#ifdef BCMSDH_MODULE
++static int __init
++bcmsdh_module_init(void)
++{
++	int error = 0;
++	error = sdio_function_init();
++	return error;
++}
++
++static void __exit
++bcmsdh_module_cleanup(void)
++{
++	sdio_function_cleanup();
++}
++
++module_init(bcmsdh_module_init);
++module_exit(bcmsdh_module_cleanup);
++
++MODULE_LICENSE("GPL v2");
++MODULE_DESCRIPTION(DESCRIPTION);
++MODULE_AUTHOR(AUTHOR);
++
++#endif /* BCMSDH_MODULE */
++/*
++ * module init
++*/
++int bcmsdh_register_client_driver(void)
++{
++	return sdio_register_driver(&bcmsdh_sdmmc_driver);
++}
++
++/*
++ * module cleanup
++*/
++void bcmsdh_unregister_client_driver(void)
++{
++	sdio_unregister_driver(&bcmsdh_sdmmc_driver);
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/bcmsdspi_linux.c b/module_drivers/drivers/net/wireless/bcmdhd/bcmsdspi_linux.c
+new file mode 100644
+index 000000000..b7091e598
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/bcmsdspi_linux.c
+@@ -0,0 +1,252 @@
++/*
++ * Broadcom SPI Host Controller Driver - Linux Per-port
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmsdspi_linux.c 514727 2014-11-12 03:02:48Z $
++ */
++
++#include <typedefs.h>
++#include <bcmutils.h>
++
++#include <bcmsdbus.h>		/* bcmsdh to/from specific controller APIs */
++#include <sdiovar.h>		/* to get msglevel bit values */
++
++#include <pcicfg.h>
++#include <sdio.h>		/* SDIO Device and Protocol Specs */
++#include <linux/sched.h>	/* request_irq(), free_irq() */
++#include <bcmsdspi.h>
++#include <bcmspi.h>
++
++extern uint sd_crc;
++module_param(sd_crc, uint, 0);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++#define KERNEL26
++#endif
++
++struct sdos_info {
++	sdioh_info_t *sd;
++	spinlock_t lock;
++	wait_queue_head_t intr_wait_queue;
++};
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++#define BLOCKABLE()	(!in_atomic())
++#else
++#define BLOCKABLE()	(!in_interrupt())
++#endif
++
++/* Interrupt handler */
++static irqreturn_t
++sdspi_isr(int irq, void *dev_id
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20)
++, struct pt_regs *ptregs
++#endif
++)
++{
++	sdioh_info_t *sd;
++	struct sdos_info *sdos;
++	bool ours;
++
++	sd = (sdioh_info_t *)dev_id;
++	sd->local_intrcount++;
++
++	if (!sd->card_init_done) {
++		sd_err(("%s: Hey Bogus intr...not even initted: irq %d\n", __FUNCTION__, irq));
++		return IRQ_RETVAL(FALSE);
++	} else {
++		ours = spi_check_client_intr(sd, NULL);
++
++		/* For local interrupts, wake the waiting process */
++		if (ours && sd->got_hcint) {
++			sdos = (struct sdos_info *)sd->sdos_info;
++			wake_up_interruptible(&sdos->intr_wait_queue);
++		}
++
++		return IRQ_RETVAL(ours);
++	}
++}
++
++
++/* Register with Linux for interrupts */
++int
++spi_register_irq(sdioh_info_t *sd, uint irq)
++{
++	sd_trace(("Entering %s: irq == %d\n", __FUNCTION__, irq));
++	if (request_irq(irq, sdspi_isr, IRQF_SHARED, "bcmsdspi", sd) < 0) {
++		sd_err(("%s: request_irq() failed\n", __FUNCTION__));
++		return ERROR;
++	}
++	return SUCCESS;
++}
++
++/* Free Linux irq */
++void
++spi_free_irq(uint irq, sdioh_info_t *sd)
++{
++	free_irq(irq, sd);
++}
++
++/* Map Host controller registers */
++uint32 *
++spi_reg_map(osl_t *osh, uintptr addr, int size)
++{
++	return (uint32 *)REG_MAP(addr, size);
++}
++
++void
++spi_reg_unmap(osl_t *osh, uintptr addr, int size)
++{
++	REG_UNMAP((void*)(uintptr)addr);
++}
++
++int
++spi_osinit(sdioh_info_t *sd)
++{
++	struct sdos_info *sdos;
++
++	sdos = (struct sdos_info*)MALLOC(sd->osh, sizeof(struct sdos_info));
++	sd->sdos_info = (void*)sdos;
++	if (sdos == NULL)
++		return BCME_NOMEM;
++
++	sdos->sd = sd;
++	spin_lock_init(&sdos->lock);
++	init_waitqueue_head(&sdos->intr_wait_queue);
++	return BCME_OK;
++}
++
++void
++spi_osfree(sdioh_info_t *sd)
++{
++	struct sdos_info *sdos;
++	ASSERT(sd && sd->sdos_info);
++
++	sdos = (struct sdos_info *)sd->sdos_info;
++	MFREE(sd->osh, sdos, sizeof(struct sdos_info));
++}
++
++/* Interrupt enable/disable */
++SDIOH_API_RC
++sdioh_interrupt_set(sdioh_info_t *sd, bool enable)
++{
++	ulong flags;
++	struct sdos_info *sdos;
++
++	sd_trace(("%s: %s\n", __FUNCTION__, enable ? "Enabling" : "Disabling"));
++
++	sdos = (struct sdos_info *)sd->sdos_info;
++	ASSERT(sdos);
++
++	if (!(sd->host_init_done && sd->card_init_done)) {
++		sd_err(("%s: Card & Host are not initted - bailing\n", __FUNCTION__));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	if (enable && !(sd->intr_handler && sd->intr_handler_arg)) {
++		sd_err(("%s: no handler registered, will not enable\n", __FUNCTION__));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	/* Ensure atomicity for enable/disable calls */
++	spin_lock_irqsave(&sdos->lock, flags);
++
++	sd->client_intr_enabled = enable;
++	if (enable && !sd->lockcount)
++		spi_devintr_on(sd);
++	else
++		spi_devintr_off(sd);
++
++	spin_unlock_irqrestore(&sdos->lock, flags);
++
++	return SDIOH_API_RC_SUCCESS;
++}
++
++/* Protect against reentrancy (disable device interrupts while executing) */
++void
++spi_lock(sdioh_info_t *sd)
++{
++	ulong flags;
++	struct sdos_info *sdos;
++
++	sdos = (struct sdos_info *)sd->sdos_info;
++	ASSERT(sdos);
++
++	sd_trace(("%s: %d\n", __FUNCTION__, sd->lockcount));
++
++	spin_lock_irqsave(&sdos->lock, flags);
++	if (sd->lockcount) {
++		sd_err(("%s: Already locked!\n", __FUNCTION__));
++		ASSERT(sd->lockcount == 0);
++	}
++	spi_devintr_off(sd);
++	sd->lockcount++;
++	spin_unlock_irqrestore(&sdos->lock, flags);
++}
++
++/* Enable client interrupt */
++void
++spi_unlock(sdioh_info_t *sd)
++{
++	ulong flags;
++	struct sdos_info *sdos;
++
++	sd_trace(("%s: %d, %d\n", __FUNCTION__, sd->lockcount, sd->client_intr_enabled));
++	ASSERT(sd->lockcount > 0);
++
++	sdos = (struct sdos_info *)sd->sdos_info;
++	ASSERT(sdos);
++
++	spin_lock_irqsave(&sdos->lock, flags);
++	if (--sd->lockcount == 0 && sd->client_intr_enabled) {
++		spi_devintr_on(sd);
++	}
++	spin_unlock_irqrestore(&sdos->lock, flags);
++}
++
++void spi_waitbits(sdioh_info_t *sd, bool yield)
++{
++#ifndef BCMSDYIELD
++	ASSERT(!yield);
++#endif
++	sd_trace(("%s: yield %d canblock %d\n",
++	          __FUNCTION__, yield, BLOCKABLE()));
++
++	/* Clear the "interrupt happened" flag and last intrstatus */
++	sd->got_hcint = FALSE;
++
++#ifdef BCMSDYIELD
++	if (yield && BLOCKABLE()) {
++		struct sdos_info *sdos;
++		sdos = (struct sdos_info *)sd->sdos_info;
++		/* Wait for the indication, the interrupt will be masked when the ISR fires. */
++		wait_event_interruptible(sdos->intr_wait_queue, (sd->got_hcint));
++	} else
++#endif /* BCMSDYIELD */
++	{
++		spi_spinbits(sd);
++	}
++
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/bcmspibrcm.c b/module_drivers/drivers/net/wireless/bcmdhd/bcmspibrcm.c
+new file mode 100644
+index 000000000..1bbff169f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/bcmspibrcm.c
+@@ -0,0 +1,1764 @@
++/*
++ * Broadcom BCMSDH to gSPI Protocol Conversion Layer
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmspibrcm.c 611787 2016-01-12 06:07:27Z $
++ */
++
++#define HSMODE
++
++#include <typedefs.h>
++
++#include <bcmdevs.h>
++#include <bcmendian.h>
++#include <bcmutils.h>
++#include <osl.h>
++#include <hndsoc.h>
++#include <siutils.h>
++#include <sbchipc.h>
++#include <sbsdio.h>	/* SDIO device core hardware definitions. */
++#include <spid.h>
++
++#include <bcmsdbus.h>	/* bcmsdh to/from specific controller APIs */
++#include <sdiovar.h>	/* ioctl/iovars */
++#include <sdio.h>	/* SDIO Device and Protocol Specs */
++
++#include <pcicfg.h>
++
++
++#include <bcmspibrcm.h>
++#include <bcmspi.h>
++
++/* these are for the older cores... for newer cores we have control for each of them */
++#define F0_RESPONSE_DELAY	16
++#define F1_RESPONSE_DELAY	16
++#define F2_RESPONSE_DELAY	F0_RESPONSE_DELAY
++
++
++#define GSPI_F0_RESP_DELAY		0
++#define GSPI_F1_RESP_DELAY		F1_RESPONSE_DELAY
++#define GSPI_F2_RESP_DELAY		0
++#define GSPI_F3_RESP_DELAY		0
++
++#define CMDLEN		4
++
++/* Globals */
++#if defined(DHD_DEBUG)
++uint sd_msglevel = SDH_ERROR_VAL;
++#else
++uint sd_msglevel = 0;
++#endif 
++
++uint sd_hiok = FALSE;		/* Use hi-speed mode if available? */
++uint sd_sdmode = SDIOH_MODE_SPI;		/* Use SD4 mode by default */
++uint sd_f2_blocksize = 64;		/* Default blocksize */
++
++
++uint sd_divisor = 2;
++uint sd_power = 1;		/* Default to SD Slot powered ON */
++uint sd_clock = 1;		/* Default to SD Clock turned ON */
++uint sd_crc = 0;		/* Default to SPI CRC Check turned OFF */
++uint sd_pci_slot = 0xFFFFffff; /* Used to force selection of a particular PCI slot */
++
++uint8	spi_outbuf[SPI_MAX_PKT_LEN];
++uint8	spi_inbuf[SPI_MAX_PKT_LEN];
++
++/* 128bytes buffer is enough to clear data-not-available and program response-delay F0 bits
++ * assuming we will not exceed F0 response delay > 100 bytes at 48MHz.
++ */
++#define BUF2_PKT_LEN	128
++uint8	spi_outbuf2[BUF2_PKT_LEN];
++uint8	spi_inbuf2[BUF2_PKT_LEN];
++
++#define SPISWAP_WD4(x) bcmswap32(x);
++#define SPISWAP_WD2(x) (bcmswap16(x & 0xffff)) | \
++						(bcmswap16((x & 0xffff0000) >> 16) << 16);
++
++/* Prototypes */
++static bool bcmspi_test_card(sdioh_info_t *sd);
++static bool bcmspi_host_device_init_adapt(sdioh_info_t *sd);
++static int bcmspi_set_highspeed_mode(sdioh_info_t *sd, bool hsmode);
++static int bcmspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd_arg,
++                           uint32 *data, uint32 datalen);
++static int bcmspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr,
++                              int regsize, uint32 *data);
++static int bcmspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr,
++                               int regsize, uint32 data);
++static int bcmspi_card_bytewrite(sdioh_info_t *sd, int func, uint32 regaddr,
++                               uint8 *data);
++static int bcmspi_driver_init(sdioh_info_t *sd);
++static int bcmspi_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo,
++                          uint32 addr, int nbytes, uint32 *data);
++static int bcmspi_card_regread_fixedaddr(sdioh_info_t *sd, int func, uint32 regaddr, int regsize,
++                                 uint32 *data);
++static void bcmspi_cmd_getdstatus(sdioh_info_t *sd, uint32 *dstatus_buffer);
++static int bcmspi_update_stats(sdioh_info_t *sd, uint32 cmd_arg);
++
++/*
++ *  Public entry points & extern's
++ */
++extern sdioh_info_t *
++sdioh_attach(osl_t *osh, void *bar0, uint irq)
++{
++	sdioh_info_t *sd;
++
++	sd_trace(("%s\n", __FUNCTION__));
++	if ((sd = (sdioh_info_t *)MALLOC(osh, sizeof(sdioh_info_t))) == NULL) {
++		sd_err(("%s: out of memory, malloced %d bytes\n", __FUNCTION__, MALLOCED(osh)));
++		return NULL;
++	}
++	bzero((char *)sd, sizeof(sdioh_info_t));
++	sd->osh = osh;
++	if (spi_osinit(sd) != 0) {
++		sd_err(("%s: spi_osinit() failed\n", __FUNCTION__));
++		MFREE(sd->osh, sd, sizeof(sdioh_info_t));
++		return NULL;
++	}
++
++	sd->bar0 = bar0;
++	sd->irq = irq;
++	sd->intr_handler = NULL;
++	sd->intr_handler_arg = NULL;
++	sd->intr_handler_valid = FALSE;
++
++	/* Set defaults */
++	sd->use_client_ints = TRUE;
++	sd->sd_use_dma = FALSE;	/* DMA Not supported */
++
++	/* Spi device default is 16bit mode, change to 4 when device is changed to 32bit
++	 * mode
++	 */
++	sd->wordlen = 2;
++
++
++	if (!spi_hw_attach(sd)) {
++		sd_err(("%s: spi_hw_attach() failed\n", __FUNCTION__));
++		spi_osfree(sd);
++		MFREE(sd->osh, sd, sizeof(sdioh_info_t));
++		return (NULL);
++	}
++
++	if (bcmspi_driver_init(sd) != SUCCESS) {
++		sd_err(("%s: bcmspi_driver_init() failed()\n", __FUNCTION__));
++		spi_hw_detach(sd);
++		spi_osfree(sd);
++		MFREE(sd->osh, sd, sizeof(sdioh_info_t));
++		return (NULL);
++	}
++
++	if (spi_register_irq(sd, irq) != SUCCESS) {
++		sd_err(("%s: spi_register_irq() failed for irq = %d\n", __FUNCTION__, irq));
++		spi_hw_detach(sd);
++		spi_osfree(sd);
++		MFREE(sd->osh, sd, sizeof(sdioh_info_t));
++		return (NULL);
++	}
++
++	sd_trace(("%s: Done\n", __FUNCTION__));
++
++	return sd;
++}
++
++extern SDIOH_API_RC
++sdioh_detach(osl_t *osh, sdioh_info_t *sd)
++{
++	sd_trace(("%s\n", __FUNCTION__));
++	if (sd) {
++		sd_err(("%s: detaching from hardware\n", __FUNCTION__));
++		spi_free_irq(sd->irq, sd);
++		spi_hw_detach(sd);
++		spi_osfree(sd);
++		MFREE(sd->osh, sd, sizeof(sdioh_info_t));
++	}
++	return SDIOH_API_RC_SUCCESS;
++}
++
++/* Configure callback to client when we recieve client interrupt */
++extern SDIOH_API_RC
++sdioh_interrupt_register(sdioh_info_t *sd, sdioh_cb_fn_t fn, void *argh)
++{
++	sd_trace(("%s: Entering\n", __FUNCTION__));
++#if !defined(OOB_INTR_ONLY)
++	sd->intr_handler = fn;
++	sd->intr_handler_arg = argh;
++	sd->intr_handler_valid = TRUE;
++#endif /* !defined(OOB_INTR_ONLY) */
++	return SDIOH_API_RC_SUCCESS;
++}
++
++extern SDIOH_API_RC
++sdioh_interrupt_deregister(sdioh_info_t *sd)
++{
++	sd_trace(("%s: Entering\n", __FUNCTION__));
++#if !defined(OOB_INTR_ONLY)
++	sd->intr_handler_valid = FALSE;
++	sd->intr_handler = NULL;
++	sd->intr_handler_arg = NULL;
++#endif /* !defined(OOB_INTR_ONLY) */
++	return SDIOH_API_RC_SUCCESS;
++}
++
++extern SDIOH_API_RC
++sdioh_interrupt_query(sdioh_info_t *sd, bool *onoff)
++{
++	sd_trace(("%s: Entering\n", __FUNCTION__));
++	*onoff = sd->client_intr_enabled;
++	return SDIOH_API_RC_SUCCESS;
++}
++
++#if defined(DHD_DEBUG)
++extern bool
++sdioh_interrupt_pending(sdioh_info_t *sd)
++{
++	return 0;
++}
++#endif
++
++/* Provide dstatus bits of spi-transaction for dhd layers. */
++extern uint32
++sdioh_get_dstatus(sdioh_info_t *sd)
++{
++	return sd->card_dstatus;
++}
++
++extern void
++sdioh_chipinfo(sdioh_info_t *sd, uint32 chip, uint32 chiprev)
++{
++	sd->chip = chip;
++	sd->chiprev = chiprev;
++}
++
++extern void
++sdioh_dwordmode(sdioh_info_t *sd, bool set)
++{
++	uint8 reg = 0;
++	int status;
++
++	if ((status = sdioh_request_byte(sd, SDIOH_READ, SPI_FUNC_0, SPID_STATUS_ENABLE, &reg)) !=
++	     SUCCESS) {
++		sd_err(("%s: Failed to set dwordmode in gSPI\n", __FUNCTION__));
++		return;
++	}
++
++	if (set) {
++		reg |= DWORD_PKT_LEN_EN;
++		sd->dwordmode = TRUE;
++		sd->client_block_size[SPI_FUNC_2] = 4096; /* h2spi's limit is 4KB, we support 8KB */
++	} else {
++		reg &= ~DWORD_PKT_LEN_EN;
++		sd->dwordmode = FALSE;
++		sd->client_block_size[SPI_FUNC_2] = 2048;
++	}
++
++	if ((status = sdioh_request_byte(sd, SDIOH_WRITE, SPI_FUNC_0, SPID_STATUS_ENABLE, &reg)) !=
++	     SUCCESS) {
++		sd_err(("%s: Failed to set dwordmode in gSPI\n", __FUNCTION__));
++		return;
++	}
++}
++
++
++uint
++sdioh_query_iofnum(sdioh_info_t *sd)
++{
++	return sd->num_funcs;
++}
++
++/* IOVar table */
++enum {
++	IOV_MSGLEVEL = 1,
++	IOV_BLOCKMODE,
++	IOV_BLOCKSIZE,
++	IOV_DMA,
++	IOV_USEINTS,
++	IOV_NUMINTS,
++	IOV_NUMLOCALINTS,
++	IOV_HOSTREG,
++	IOV_DEVREG,
++	IOV_DIVISOR,
++	IOV_SDMODE,
++	IOV_HISPEED,
++	IOV_HCIREGS,
++	IOV_POWER,
++	IOV_CLOCK,
++	IOV_SPIERRSTATS,
++	IOV_RESP_DELAY_ALL
++};
++
++const bcm_iovar_t sdioh_iovars[] = {
++	{"sd_msglevel",	IOV_MSGLEVEL, 	0,	IOVT_UINT32,	0 },
++	{"sd_blocksize", IOV_BLOCKSIZE, 0,	IOVT_UINT32,	0 }, /* ((fn << 16) | size) */
++	{"sd_dma",	IOV_DMA,	0,	IOVT_BOOL,	0 },
++	{"sd_ints",	IOV_USEINTS,	0,	IOVT_BOOL,	0 },
++	{"sd_numints",	IOV_NUMINTS,	0,	IOVT_UINT32,	0 },
++	{"sd_numlocalints", IOV_NUMLOCALINTS, 0, IOVT_UINT32,	0 },
++	{"sd_hostreg",	IOV_HOSTREG,	0,	IOVT_BUFFER,	sizeof(sdreg_t) },
++	{"sd_devreg",	IOV_DEVREG,	0,	IOVT_BUFFER,	sizeof(sdreg_t)	},
++	{"sd_divisor",	IOV_DIVISOR,	0,	IOVT_UINT32,	0 },
++	{"sd_power",	IOV_POWER,	0,	IOVT_UINT32,	0 },
++	{"sd_clock",	IOV_CLOCK,	0,	IOVT_UINT32,	0 },
++	{"sd_mode",	IOV_SDMODE,	0,	IOVT_UINT32,	100},
++	{"sd_highspeed",	IOV_HISPEED,	0,	IOVT_UINT32,	0},
++	{"spi_errstats", IOV_SPIERRSTATS, 0, IOVT_BUFFER, sizeof(struct spierrstats_t) },
++	{"spi_respdelay",	IOV_RESP_DELAY_ALL,	0,	IOVT_BOOL,	0 },
++	{NULL, 0, 0, 0, 0 }
++};
++
++int
++sdioh_iovar_op(sdioh_info_t *si, const char *name,
++               void *params, int plen, void *arg, int len, bool set)
++{
++	const bcm_iovar_t *vi = NULL;
++	int bcmerror = 0;
++	int val_size;
++	int32 int_val = 0;
++	bool bool_val;
++	uint32 actionid;
++/*
++	sdioh_regs_t *regs;
++*/
++
++	ASSERT(name);
++	ASSERT(len >= 0);
++
++	/* Get must have return space; Set does not take qualifiers */
++	ASSERT(set || (arg && len));
++	ASSERT(!set || (!params && !plen));
++
++	sd_trace(("%s: Enter (%s %s)\n", __FUNCTION__, (set ? "set" : "get"), name));
++
++	if ((vi = bcm_iovar_lookup(sdioh_iovars, name)) == NULL) {
++		bcmerror = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++	if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, set)) != 0)
++		goto exit;
++
++	/* Set up params so get and set can share the convenience variables */
++	if (params == NULL) {
++		params = arg;
++		plen = len;
++	}
++
++	if (vi->type == IOVT_VOID)
++		val_size = 0;
++	else if (vi->type == IOVT_BUFFER)
++		val_size = len;
++	else
++		val_size = sizeof(int);
++
++	if (plen >= (int)sizeof(int_val))
++		bcopy(params, &int_val, sizeof(int_val));
++
++	bool_val = (int_val != 0) ? TRUE : FALSE;
++
++	actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
++	switch (actionid) {
++	case IOV_GVAL(IOV_MSGLEVEL):
++		int_val = (int32)sd_msglevel;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_MSGLEVEL):
++		sd_msglevel = int_val;
++		break;
++
++	case IOV_GVAL(IOV_BLOCKSIZE):
++		if ((uint32)int_val > si->num_funcs) {
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		int_val = (int32)si->client_block_size[int_val];
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_DMA):
++		int_val = (int32)si->sd_use_dma;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DMA):
++		si->sd_use_dma = (bool)int_val;
++		break;
++
++	case IOV_GVAL(IOV_USEINTS):
++		int_val = (int32)si->use_client_ints;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_USEINTS):
++		break;
++
++	case IOV_GVAL(IOV_DIVISOR):
++		int_val = (uint32)sd_divisor;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DIVISOR):
++		sd_divisor = int_val;
++		if (!spi_start_clock(si, (uint16)sd_divisor)) {
++			sd_err(("%s: set clock failed\n", __FUNCTION__));
++			bcmerror = BCME_ERROR;
++		}
++		break;
++
++	case IOV_GVAL(IOV_POWER):
++		int_val = (uint32)sd_power;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_POWER):
++		sd_power = int_val;
++		break;
++
++	case IOV_GVAL(IOV_CLOCK):
++		int_val = (uint32)sd_clock;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_CLOCK):
++		sd_clock = int_val;
++		break;
++
++	case IOV_GVAL(IOV_SDMODE):
++		int_val = (uint32)sd_sdmode;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_SDMODE):
++		sd_sdmode = int_val;
++		break;
++
++	case IOV_GVAL(IOV_HISPEED):
++		int_val = (uint32)sd_hiok;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_HISPEED):
++		sd_hiok = int_val;
++
++		if (!bcmspi_set_highspeed_mode(si, (bool)sd_hiok)) {
++			sd_err(("%s: Failed changing highspeed mode to %d.\n",
++			        __FUNCTION__, sd_hiok));
++			bcmerror = BCME_ERROR;
++			return ERROR;
++		}
++		break;
++
++	case IOV_GVAL(IOV_NUMINTS):
++		int_val = (int32)si->intrcount;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_NUMLOCALINTS):
++		int_val = (int32)si->local_intrcount;
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_GVAL(IOV_DEVREG):
++	{
++		sdreg_t *sd_ptr = (sdreg_t *)params;
++		uint8 data;
++
++		if (sdioh_cfg_read(si, sd_ptr->func, sd_ptr->offset, &data)) {
++			bcmerror = BCME_SDIO_ERROR;
++			break;
++		}
++
++		int_val = (int)data;
++		bcopy(&int_val, arg, sizeof(int_val));
++		break;
++	}
++
++	case IOV_SVAL(IOV_DEVREG):
++	{
++		sdreg_t *sd_ptr = (sdreg_t *)params;
++		uint8 data = (uint8)sd_ptr->value;
++
++		if (sdioh_cfg_write(si, sd_ptr->func, sd_ptr->offset, &data)) {
++			bcmerror = BCME_SDIO_ERROR;
++			break;
++		}
++		break;
++	}
++
++
++	case IOV_GVAL(IOV_SPIERRSTATS):
++	{
++		bcopy(&si->spierrstats, arg, sizeof(struct spierrstats_t));
++		break;
++	}
++
++	case IOV_SVAL(IOV_SPIERRSTATS):
++	{
++		bzero(&si->spierrstats, sizeof(struct spierrstats_t));
++		break;
++	}
++
++	case IOV_GVAL(IOV_RESP_DELAY_ALL):
++		int_val = (int32)si->resp_delay_all;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_RESP_DELAY_ALL):
++		si->resp_delay_all = (bool)int_val;
++		int_val = STATUS_ENABLE|INTR_WITH_STATUS;
++		if (si->resp_delay_all)
++			int_val |= RESP_DELAY_ALL;
++		else {
++			if (bcmspi_card_regwrite(si, SPI_FUNC_0, SPID_RESPONSE_DELAY, 1,
++			     F1_RESPONSE_DELAY) != SUCCESS) {
++				sd_err(("%s: Unable to set response delay.\n", __FUNCTION__));
++				bcmerror = BCME_SDIO_ERROR;
++				break;
++			}
++		}
++
++		if (bcmspi_card_regwrite(si, SPI_FUNC_0, SPID_STATUS_ENABLE, 1, int_val)
++		     != SUCCESS) {
++			sd_err(("%s: Unable to set response delay.\n", __FUNCTION__));
++			bcmerror = BCME_SDIO_ERROR;
++			break;
++		}
++		break;
++
++	default:
++		bcmerror = BCME_UNSUPPORTED;
++		break;
++	}
++exit:
++
++	return bcmerror;
++}
++
++extern SDIOH_API_RC
++sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
++{
++	SDIOH_API_RC status;
++	/* No lock needed since sdioh_request_byte does locking */
++	status = sdioh_request_byte(sd, SDIOH_READ, fnc_num, addr, data);
++	return status;
++}
++
++extern SDIOH_API_RC
++sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
++{
++	/* No lock needed since sdioh_request_byte does locking */
++	SDIOH_API_RC status;
++
++	if ((fnc_num == SPI_FUNC_1) && (addr == SBSDIO_FUNC1_FRAMECTRL)) {
++		uint8 dummy_data;
++		status = sdioh_cfg_read(sd, fnc_num, addr, &dummy_data);
++		if (status) {
++			sd_err(("sdioh_cfg_read() failed.\n"));
++			return status;
++		}
++	}
++
++	status = sdioh_request_byte(sd, SDIOH_WRITE, fnc_num, addr, data);
++	return status;
++}
++
++extern SDIOH_API_RC
++sdioh_cis_read(sdioh_info_t *sd, uint func, uint8 *cisd, uint32 length)
++{
++	uint32 count;
++	int offset;
++	uint32 cis_byte;
++	uint16 *cis = (uint16 *)cisd;
++	uint bar0 = SI_ENUM_BASE;
++	int status;
++	uint8 data;
++
++	sd_trace(("%s: Func %d\n", __FUNCTION__, func));
++
++	spi_lock(sd);
++
++	/* Set sb window address to 0x18000000 */
++	data = (bar0 >> 8) & SBSDIO_SBADDRLOW_MASK;
++	status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW, &data);
++	if (status == SUCCESS) {
++		data = (bar0 >> 16) & SBSDIO_SBADDRMID_MASK;
++		status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID, &data);
++	} else {
++		sd_err(("%s: Unable to set sb-addr-windows\n", __FUNCTION__));
++		spi_unlock(sd);
++		return (BCME_ERROR);
++	}
++	if (status == SUCCESS) {
++		data = (bar0 >> 24) & SBSDIO_SBADDRHIGH_MASK;
++		status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH, &data);
++	} else {
++		sd_err(("%s: Unable to set sb-addr-windows\n", __FUNCTION__));
++		spi_unlock(sd);
++		return (BCME_ERROR);
++	}
++
++	offset =  CC_SROM_OTP; /* OTP offset in chipcommon. */
++	for (count = 0; count < length/2; count++) {
++		if (bcmspi_card_regread (sd, SDIO_FUNC_1, offset, 2, &cis_byte) < 0) {
++			sd_err(("%s: regread failed: Can't read CIS\n", __FUNCTION__));
++			spi_unlock(sd);
++			return (BCME_ERROR);
++		}
++
++		*cis = (uint16)cis_byte;
++		cis++;
++		offset += 2;
++	}
++
++	spi_unlock(sd);
++
++	return (BCME_OK);
++}
++
++extern SDIOH_API_RC
++sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr, uint8 *byte)
++{
++	int status;
++	uint32 cmd_arg;
++	uint32 dstatus;
++	uint32 data = (uint32)(*byte);
++
++	spi_lock(sd);
++
++	cmd_arg = 0;
++	cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
++	cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1);	/* Incremental access */
++	cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
++	cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, rw == SDIOH_READ ? 0 : 1);
++	cmd_arg = SFIELD(cmd_arg, SPI_LEN, 1);
++
++	if (rw == SDIOH_READ) {
++		sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x\n",
++		          __FUNCTION__, cmd_arg, func, regaddr));
++	} else {
++		sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x data=0x%x\n",
++		          __FUNCTION__, cmd_arg, func, regaddr, data));
++	}
++
++	if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, 1)) != SUCCESS) {
++		spi_unlock(sd);
++		return status;
++	}
++
++	if (rw == SDIOH_READ) {
++		*byte = (uint8)data;
++		sd_trace(("%s: RD result=0x%x\n", __FUNCTION__, *byte));
++	}
++
++	bcmspi_cmd_getdstatus(sd, &dstatus);
++	if (dstatus)
++		sd_trace(("dstatus=0x%x\n", dstatus));
++
++	spi_unlock(sd);
++	return SDIOH_API_RC_SUCCESS;
++}
++
++extern SDIOH_API_RC
++sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func, uint addr,
++                   uint32 *word, uint nbytes)
++{
++	int status;
++
++	spi_lock(sd);
++
++	if (rw == SDIOH_READ)
++		status = bcmspi_card_regread(sd, func, addr, nbytes, word);
++	else
++		status = bcmspi_card_regwrite(sd, func, addr, nbytes, *word);
++
++	spi_unlock(sd);
++	return (status == SUCCESS ?  SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
++}
++
++extern SDIOH_API_RC
++sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint rw, uint func,
++                     uint addr, uint reg_width, uint buflen_u, uint8 *buffer, void *pkt)
++{
++	int len;
++	int buflen = (int)buflen_u;
++	bool fifo = (fix_inc == SDIOH_DATA_FIX);
++
++	spi_lock(sd);
++
++	ASSERT(reg_width == 4);
++	ASSERT(buflen_u < (1 << 30));
++	ASSERT(sd->client_block_size[func]);
++
++	sd_data(("%s: %c len %d r_cnt %d t_cnt %d, pkt @0x%p\n",
++	         __FUNCTION__, rw == SDIOH_READ ? 'R' : 'W',
++	         buflen_u, sd->r_cnt, sd->t_cnt, pkt));
++
++	/* Break buffer down into blocksize chunks. */
++	while (buflen > 0) {
++		len = MIN(sd->client_block_size[func], buflen);
++		if (bcmspi_card_buf(sd, rw, func, fifo, addr, len, (uint32 *)buffer) != SUCCESS) {
++			sd_err(("%s: bcmspi_card_buf %s failed\n",
++				__FUNCTION__, rw == SDIOH_READ ? "Read" : "Write"));
++			spi_unlock(sd);
++			return SDIOH_API_RC_FAIL;
++		}
++		buffer += len;
++		buflen -= len;
++		if (!fifo)
++			addr += len;
++	}
++	spi_unlock(sd);
++	return SDIOH_API_RC_SUCCESS;
++}
++
++/* This function allows write to gspi bus when another rd/wr function is deep down the call stack.
++ * Its main aim is to have simpler spi writes rather than recursive writes.
++ * e.g. When there is a need to program response delay on the fly after detecting the SPI-func
++ * this call will allow to program the response delay.
++ */
++static int
++bcmspi_card_byterewrite(sdioh_info_t *sd, int func, uint32 regaddr, uint8 byte)
++{
++	uint32 cmd_arg;
++	uint32 datalen = 1;
++	uint32 hostlen;
++
++	cmd_arg = 0;
++
++	cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
++	cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1);	/* Incremental access */
++	cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
++	cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
++	cmd_arg = SFIELD(cmd_arg, SPI_LEN, datalen);
++
++	sd_trace(("%s cmd_arg = 0x%x\n", __FUNCTION__, cmd_arg));
++
++
++	/* Set up and issue the SPI command.  MSByte goes out on bus first.  Increase datalen
++	 * according to the wordlen mode(16/32bit) the device is in.
++	 */
++	ASSERT(sd->wordlen == 4 || sd->wordlen == 2);
++	datalen = ROUNDUP(datalen, sd->wordlen);
++
++	/* Start by copying command in the spi-outbuffer */
++	if (sd->wordlen == 4) { /* 32bit spid */
++		*(uint32 *)spi_outbuf2 = SPISWAP_WD4(cmd_arg);
++		if (datalen & 0x3)
++			datalen += (4 - (datalen & 0x3));
++	} else if (sd->wordlen == 2) { /* 16bit spid */
++		*(uint32 *)spi_outbuf2 = SPISWAP_WD2(cmd_arg);
++		if (datalen & 0x1)
++			datalen++;
++	} else {
++		sd_err(("%s: Host is %d bit spid, could not create SPI command.\n",
++		        __FUNCTION__, 8 * sd->wordlen));
++		return ERROR;
++	}
++
++	/* for Write, put the data into the output buffer  */
++	if (datalen != 0) {
++			if (sd->wordlen == 4) { /* 32bit spid */
++				*(uint32 *)&spi_outbuf2[CMDLEN] = SPISWAP_WD4(byte);
++			} else if (sd->wordlen == 2) { /* 16bit spid */
++				*(uint32 *)&spi_outbuf2[CMDLEN] = SPISWAP_WD2(byte);
++			}
++	}
++
++	/* +4 for cmd, +4 for dstatus */
++	hostlen = datalen + 8;
++	hostlen += (4 - (hostlen & 0x3));
++	spi_sendrecv(sd, spi_outbuf2, spi_inbuf2, hostlen);
++
++	/* Last 4bytes are dstatus.  Device is configured to return status bits. */
++	if (sd->wordlen == 4) { /* 32bit spid */
++		sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
++	} else if (sd->wordlen == 2) { /* 16bit spid */
++		sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
++	} else {
++		sd_err(("%s: Host is %d bit machine, could not read SPI dstatus.\n",
++		        __FUNCTION__, 8 * sd->wordlen));
++		return ERROR;
++	}
++
++	if (sd->card_dstatus)
++		sd_trace(("dstatus after byte rewrite = 0x%x\n", sd->card_dstatus));
++
++	return (BCME_OK);
++}
++
++/* Program the response delay corresponding to the spi function */
++static int
++bcmspi_prog_resp_delay(sdioh_info_t *sd, int func, uint8 resp_delay)
++{
++	if (sd->resp_delay_all == FALSE)
++		return (BCME_OK);
++
++	if (sd->prev_fun == func)
++		return (BCME_OK);
++
++	if (F0_RESPONSE_DELAY == F1_RESPONSE_DELAY)
++		return (BCME_OK);
++
++	bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_RESPONSE_DELAY, resp_delay);
++
++	/* Remember function for which to avoid reprogramming resp-delay in next iteration */
++	sd->prev_fun = func;
++
++	return (BCME_OK);
++
++}
++
++#define GSPI_RESYNC_PATTERN	0x0
++
++/* A resync pattern is a 32bit MOSI line with all zeros. Its a special command in gSPI.
++ * It resets the spi-bkplane logic so that all F1 related ping-pong buffer logic is
++ * synchronised and all queued resuests are cancelled.
++ */
++static int
++bcmspi_resync_f1(sdioh_info_t *sd)
++{
++	uint32 cmd_arg = GSPI_RESYNC_PATTERN, data = 0, datalen = 0;
++
++
++	/* Set up and issue the SPI command.  MSByte goes out on bus first.  Increase datalen
++	 * according to the wordlen mode(16/32bit) the device is in.
++	 */
++	ASSERT(sd->wordlen == 4 || sd->wordlen == 2);
++	datalen = ROUNDUP(datalen, sd->wordlen);
++
++	/* Start by copying command in the spi-outbuffer */
++	*(uint32 *)spi_outbuf2 = cmd_arg;
++
++	/* for Write, put the data into the output buffer  */
++	*(uint32 *)&spi_outbuf2[CMDLEN] = data;
++
++	/* +4 for cmd, +4 for dstatus */
++	spi_sendrecv(sd, spi_outbuf2, spi_inbuf2, datalen + 8);
++
++	/* Last 4bytes are dstatus.  Device is configured to return status bits. */
++	if (sd->wordlen == 4) { /* 32bit spid */
++		sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
++	} else if (sd->wordlen == 2) { /* 16bit spid */
++		sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
++	} else {
++		sd_err(("%s: Host is %d bit machine, could not read SPI dstatus.\n",
++		        __FUNCTION__, 8 * sd->wordlen));
++		return ERROR;
++	}
++
++	if (sd->card_dstatus)
++		sd_trace(("dstatus after resync pattern write = 0x%x\n", sd->card_dstatus));
++
++	return (BCME_OK);
++}
++
++uint32 dstatus_count = 0;
++
++static int
++bcmspi_update_stats(sdioh_info_t *sd, uint32 cmd_arg)
++{
++	uint32 dstatus = sd->card_dstatus;
++	struct spierrstats_t *spierrstats = &sd->spierrstats;
++	int err = SUCCESS;
++
++	sd_trace(("cmd = 0x%x, dstatus = 0x%x\n", cmd_arg, dstatus));
++
++	/* Store dstatus of last few gSPI transactions */
++	spierrstats->dstatus[dstatus_count % NUM_PREV_TRANSACTIONS] = dstatus;
++	spierrstats->spicmd[dstatus_count % NUM_PREV_TRANSACTIONS] = cmd_arg;
++	dstatus_count++;
++
++	if (sd->card_init_done == FALSE)
++		return err;
++
++	if (dstatus & STATUS_DATA_NOT_AVAILABLE) {
++		spierrstats->dna++;
++		sd_trace(("Read data not available on F1 addr = 0x%x\n",
++		        GFIELD(cmd_arg, SPI_REG_ADDR)));
++		/* Clear dna bit */
++		bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_INTR_REG, DATA_UNAVAILABLE);
++	}
++
++	if (dstatus & STATUS_UNDERFLOW) {
++		spierrstats->rdunderflow++;
++		sd_err(("FIFO underflow happened due to current F2 read command.\n"));
++	}
++
++	if (dstatus & STATUS_OVERFLOW) {
++		spierrstats->wroverflow++;
++		sd_err(("FIFO overflow happened due to current (F1/F2) write command.\n"));
++		bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_INTR_REG, F1_OVERFLOW);
++		bcmspi_resync_f1(sd);
++		sd_err(("Recovering from F1 FIFO overflow.\n"));
++	}
++
++	if (dstatus & STATUS_F2_INTR) {
++		spierrstats->f2interrupt++;
++		sd_trace(("Interrupt from F2.  SW should clear corresponding IntStatus bits\n"));
++	}
++
++	if (dstatus & STATUS_F3_INTR) {
++		spierrstats->f3interrupt++;
++		sd_err(("Interrupt from F3.  SW should clear corresponding IntStatus bits\n"));
++	}
++
++	if (dstatus & STATUS_HOST_CMD_DATA_ERR) {
++		spierrstats->hostcmddataerr++;
++		sd_err(("Error in CMD or Host data, detected by CRC/Checksum (optional)\n"));
++	}
++
++	if (dstatus & STATUS_F2_PKT_AVAILABLE) {
++		spierrstats->f2pktavailable++;
++		sd_trace(("Packet is available/ready in F2 TX FIFO\n"));
++		sd_trace(("Packet length = %d\n", sd->dwordmode ?
++		         ((dstatus & STATUS_F2_PKT_LEN_MASK) >> (STATUS_F2_PKT_LEN_SHIFT - 2)) :
++		         ((dstatus & STATUS_F2_PKT_LEN_MASK) >> STATUS_F2_PKT_LEN_SHIFT)));
++	}
++
++	if (dstatus & STATUS_F3_PKT_AVAILABLE) {
++		spierrstats->f3pktavailable++;
++		sd_err(("Packet is available/ready in F3 TX FIFO\n"));
++		sd_err(("Packet length = %d\n",
++		        (dstatus & STATUS_F3_PKT_LEN_MASK) >> STATUS_F3_PKT_LEN_SHIFT));
++	}
++
++	return err;
++}
++
++extern int
++sdioh_abort(sdioh_info_t *sd, uint func)
++{
++	return 0;
++}
++
++int
++sdioh_start(sdioh_info_t *sd, int stage)
++{
++	return SUCCESS;
++}
++
++int
++sdioh_stop(sdioh_info_t *sd)
++{
++	return SUCCESS;
++}
++
++int
++sdioh_waitlockfree(sdioh_info_t *sd)
++{
++	return SUCCESS;
++}
++
++
++/*
++ * Private/Static work routines
++ */
++static int
++bcmspi_host_init(sdioh_info_t *sd)
++{
++
++	/* Default power on mode */
++	sd->sd_mode = SDIOH_MODE_SPI;
++	sd->polled_mode = TRUE;
++	sd->host_init_done = TRUE;
++	sd->card_init_done = FALSE;
++	sd->adapter_slot = 1;
++
++	return (SUCCESS);
++}
++
++static int
++get_client_blocksize(sdioh_info_t *sd)
++{
++	uint32 regdata[2];
++	int status;
++
++	/* Find F1/F2/F3 max packet size */
++	if ((status = bcmspi_card_regread(sd, 0, SPID_F1_INFO_REG,
++	                                 8, regdata)) != SUCCESS) {
++		return status;
++	}
++
++	sd_trace(("pkt_size regdata[0] = 0x%x, regdata[1] = 0x%x\n",
++	        regdata[0], regdata[1]));
++
++	sd->client_block_size[1] = (regdata[0] & F1_MAX_PKT_SIZE) >> 2;
++	sd_trace(("Func1 blocksize = %d\n", sd->client_block_size[1]));
++	ASSERT(sd->client_block_size[1] == BLOCK_SIZE_F1);
++
++	sd->client_block_size[2] = ((regdata[0] >> 16) & F2_MAX_PKT_SIZE) >> 2;
++	sd_trace(("Func2 blocksize = %d\n", sd->client_block_size[2]));
++	ASSERT(sd->client_block_size[2] == BLOCK_SIZE_F2);
++
++	sd->client_block_size[3] = (regdata[1] & F3_MAX_PKT_SIZE) >> 2;
++	sd_trace(("Func3 blocksize = %d\n", sd->client_block_size[3]));
++	ASSERT(sd->client_block_size[3] == BLOCK_SIZE_F3);
++
++	return 0;
++}
++
++static int
++bcmspi_client_init(sdioh_info_t *sd)
++{
++	uint32	status_en_reg = 0;
++	sd_trace(("%s: Powering up slot %d\n", __FUNCTION__, sd->adapter_slot));
++
++#ifdef HSMODE
++	if (!spi_start_clock(sd, (uint16)sd_divisor)) {
++		sd_err(("spi_start_clock failed\n"));
++		return ERROR;
++	}
++#else
++	/* Start at ~400KHz clock rate for initialization */
++	if (!spi_start_clock(sd, 128)) {
++		sd_err(("spi_start_clock failed\n"));
++		return ERROR;
++	}
++#endif /* HSMODE */
++
++	if (!bcmspi_host_device_init_adapt(sd)) {
++		sd_err(("bcmspi_host_device_init_adapt failed\n"));
++		return ERROR;
++	}
++
++	if (!bcmspi_test_card(sd)) {
++		sd_err(("bcmspi_test_card failed\n"));
++		return ERROR;
++	}
++
++	sd->num_funcs = SPI_MAX_IOFUNCS;
++
++	get_client_blocksize(sd);
++
++	/* Apply resync pattern cmd with all zeros to reset spi-bkplane F1 logic */
++	bcmspi_resync_f1(sd);
++
++	sd->dwordmode = FALSE;
++
++	bcmspi_card_regread(sd, 0, SPID_STATUS_ENABLE, 1, &status_en_reg);
++
++	sd_trace(("%s: Enabling interrupt with dstatus \n", __FUNCTION__));
++	status_en_reg |= INTR_WITH_STATUS;
++
++	if (bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_STATUS_ENABLE, 1,
++	    status_en_reg & 0xff) != SUCCESS) {
++		sd_err(("%s: Unable to set response delay for all fun's.\n", __FUNCTION__));
++		return ERROR;
++	}
++
++#ifndef HSMODE
++	/* After configuring for High-Speed mode, set the desired clock rate. */
++	if (!spi_start_clock(sd, 4)) {
++		sd_err(("spi_start_clock failed\n"));
++		return ERROR;
++	}
++#endif /* HSMODE */
++
++	/* check to see if the response delay needs to be programmed properly */
++	{
++		uint32 f1_respdelay = 0;
++		bcmspi_card_regread(sd, 0, SPID_RESP_DELAY_F1, 1, &f1_respdelay);
++		if ((f1_respdelay == 0) || (f1_respdelay == 0xFF)) {
++			/* older sdiodevice core and has no separte resp delay for each of */
++			sd_err(("older corerev < 4 so use the same resp delay for all funcs\n"));
++			sd->resp_delay_new = FALSE;
++		}
++		else {
++			/* older sdiodevice core and has no separte resp delay for each of */
++			int ret_val;
++			sd->resp_delay_new = TRUE;
++			sd_err(("new corerev >= 4 so set the resp delay for each of the funcs\n"));
++			sd_trace(("resp delay for funcs f0(%d), f1(%d), f2(%d), f3(%d)\n",
++				GSPI_F0_RESP_DELAY, GSPI_F1_RESP_DELAY,
++				GSPI_F2_RESP_DELAY, GSPI_F3_RESP_DELAY));
++			ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F0, 1,
++				GSPI_F0_RESP_DELAY);
++			if (ret_val != SUCCESS) {
++				sd_err(("%s: Unable to set response delay for F0\n", __FUNCTION__));
++				return ERROR;
++			}
++			ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F1, 1,
++				GSPI_F1_RESP_DELAY);
++			if (ret_val != SUCCESS) {
++				sd_err(("%s: Unable to set response delay for F1\n", __FUNCTION__));
++				return ERROR;
++			}
++			ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F2, 1,
++				GSPI_F2_RESP_DELAY);
++			if (ret_val != SUCCESS) {
++				sd_err(("%s: Unable to set response delay for F2\n", __FUNCTION__));
++				return ERROR;
++			}
++			ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F3, 1,
++				GSPI_F3_RESP_DELAY);
++			if (ret_val != SUCCESS) {
++				sd_err(("%s: Unable to set response delay for F2\n", __FUNCTION__));
++				return ERROR;
++			}
++		}
++	}
++
++
++	sd->card_init_done = TRUE;
++
++	/* get the device rev to program the prop respdelays */
++
++	return SUCCESS;
++}
++
++static int
++bcmspi_set_highspeed_mode(sdioh_info_t *sd, bool hsmode)
++{
++	uint32 regdata;
++	int status;
++
++	if ((status = bcmspi_card_regread(sd, 0, SPID_CONFIG,
++	                                 4, &regdata)) != SUCCESS)
++		return status;
++
++	sd_trace(("In %s spih-ctrl = 0x%x \n", __FUNCTION__, regdata));
++
++
++	if (hsmode == TRUE) {
++		sd_trace(("Attempting to enable High-Speed mode.\n"));
++
++		if (regdata & HIGH_SPEED_MODE) {
++			sd_trace(("Device is already in High-Speed mode.\n"));
++			return status;
++		} else {
++			regdata |= HIGH_SPEED_MODE;
++			sd_trace(("Writing %08x to device at %08x\n", regdata, SPID_CONFIG));
++			if ((status = bcmspi_card_regwrite(sd, 0, SPID_CONFIG,
++			                                  4, regdata)) != SUCCESS) {
++				return status;
++			}
++		}
++	} else {
++		sd_trace(("Attempting to disable High-Speed mode.\n"));
++
++		if (regdata & HIGH_SPEED_MODE) {
++			regdata &= ~HIGH_SPEED_MODE;
++			sd_trace(("Writing %08x to device at %08x\n", regdata, SPID_CONFIG));
++			if ((status = bcmspi_card_regwrite(sd, 0, SPID_CONFIG,
++			                                  4, regdata)) != SUCCESS)
++				return status;
++		}
++		 else {
++			sd_trace(("Device is already in Low-Speed mode.\n"));
++			return status;
++		}
++	}
++	spi_controller_highspeed_mode(sd, hsmode);
++
++	return TRUE;
++}
++
++#define bcmspi_find_curr_mode(sd) { \
++	sd->wordlen = 2; \
++	status = bcmspi_card_regread_fixedaddr(sd, 0, SPID_TEST_READ, 4, &regdata); \
++	regdata &= 0xff; \
++	if ((regdata == 0xad) || (regdata == 0x5b) || \
++	    (regdata == 0x5d) || (regdata == 0x5a)) \
++		break; \
++	sd->wordlen = 4; \
++	status = bcmspi_card_regread_fixedaddr(sd, 0, SPID_TEST_READ, 4, &regdata); \
++	regdata &= 0xff; \
++	if ((regdata == 0xad) || (regdata == 0x5b) || \
++	    (regdata == 0x5d) || (regdata == 0x5a)) \
++		break; \
++	sd_trace(("Silicon testability issue: regdata = 0x%x." \
++		" Expected 0xad, 0x5a, 0x5b or 0x5d.\n", regdata)); \
++	OSL_DELAY(100000); \
++}
++
++#define INIT_ADAPT_LOOP		100
++
++/* Adapt clock-phase-speed-bitwidth between host and device */
++static bool
++bcmspi_host_device_init_adapt(sdioh_info_t *sd)
++{
++	uint32 wrregdata, regdata = 0;
++	int status;
++	int i;
++
++	/* Due to a silicon testability issue, the first command from the Host
++	 * to the device will get corrupted (first bit will be lost). So the
++	 * Host should poll the device with a safe read request. ie: The Host
++	 * should try to read F0 addr 0x14 using the Fixed address mode
++	 * (This will prevent a unintended write command to be detected by device)
++	 */
++	for (i = 0; i < INIT_ADAPT_LOOP; i++) {
++	/* If device was not power-cycled it will stay in 32bit mode with
++	 * response-delay-all bit set.  Alternate the iteration so that
++	 * read either with or without response-delay for F0 to succeed.
++	 */
++		bcmspi_find_curr_mode(sd);
++		sd->resp_delay_all = (i & 0x1) ? TRUE : FALSE;
++
++		bcmspi_find_curr_mode(sd);
++		sd->dwordmode = TRUE;
++
++		bcmspi_find_curr_mode(sd);
++		sd->dwordmode = FALSE;
++	}
++
++	/* Bail out, device not detected */
++	if (i == INIT_ADAPT_LOOP)
++		return FALSE;
++
++	/* Softreset the spid logic */
++	if ((sd->dwordmode) || (sd->wordlen == 4)) {
++		bcmspi_card_regwrite(sd, 0, SPID_RESET_BP, 1, RESET_ON_WLAN_BP_RESET|RESET_SPI);
++		bcmspi_card_regread(sd, 0, SPID_RESET_BP, 1, &regdata);
++		sd_trace(("reset reg read = 0x%x\n", regdata));
++		sd_trace(("dwordmode = %d, wordlen = %d, resp_delay_all = %d\n", sd->dwordmode,
++		       sd->wordlen, sd->resp_delay_all));
++		/* Restore default state after softreset */
++		sd->wordlen = 2;
++		sd->dwordmode = FALSE;
++	}
++
++	if (sd->wordlen == 4) {
++		if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, &regdata)) !=
++		     SUCCESS)
++				return FALSE;
++		if (regdata == TEST_RO_DATA_32BIT_LE) {
++			sd_trace(("Spid is already in 32bit LE mode. Value read = 0x%x\n",
++			          regdata));
++			sd_trace(("Spid power was left on.\n"));
++		} else {
++			sd_err(("Spid power was left on but signature read failed."
++			        " Value read = 0x%x\n", regdata));
++			return FALSE;
++		}
++	} else {
++		sd->wordlen = 2;
++
++#define CTRL_REG_DEFAULT	0x00010430 /* according to the host m/c */
++
++		wrregdata = (CTRL_REG_DEFAULT);
++
++		if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, &regdata)) != SUCCESS)
++			return FALSE;
++		sd_trace(("(we are still in 16bit mode) 32bit READ LE regdata = 0x%x\n", regdata));
++
++#ifndef HSMODE
++		wrregdata |= (CLOCK_PHASE | CLOCK_POLARITY);
++		wrregdata &= ~HIGH_SPEED_MODE;
++		bcmspi_card_regwrite(sd, 0, SPID_CONFIG, 4, wrregdata);
++#endif /* HSMODE */
++
++		for (i = 0; i < INIT_ADAPT_LOOP; i++) {
++			if ((regdata == 0xfdda7d5b) || (regdata == 0xfdda7d5a)) {
++				sd_trace(("0xfeedbead was leftshifted by 1-bit.\n"));
++				if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4,
++				     &regdata)) != SUCCESS)
++					return FALSE;
++			}
++			OSL_DELAY(1000);
++		}
++
++#if defined(CHANGE_SPI_INTR_POLARITY_ACTIVE_HIGH)
++		/* Change to host controller intr-polarity of active-high */
++		wrregdata |= INTR_POLARITY;
++#else
++		/* Change to host controller intr-polarity of active-low */
++		wrregdata &= ~INTR_POLARITY;
++#endif /* CHANGE_SPI_INTR_POLARITY_ACTIVE_HIGH */
++
++		sd_trace(("(we are still in 16bit mode) 32bit Write LE reg-ctrl-data = 0x%x\n",
++		        wrregdata));
++		/* Change to 32bit mode */
++		wrregdata |= WORD_LENGTH_32;
++		bcmspi_card_regwrite(sd, 0, SPID_CONFIG, 4, wrregdata);
++
++		/* Change command/data packaging in 32bit LE mode */
++		sd->wordlen = 4;
++
++		if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, &regdata)) != SUCCESS)
++			return FALSE;
++
++		if (regdata == TEST_RO_DATA_32BIT_LE) {
++			sd_trace(("Read spid passed. Value read = 0x%x\n", regdata));
++			sd_trace(("Spid had power-on cycle OR spi was soft-resetted \n"));
++		} else {
++			sd_err(("Stale spid reg values read as it was kept powered. Value read ="
++			  "0x%x\n", regdata));
++			return FALSE;
++		}
++	}
++
++
++	return TRUE;
++}
++
++static bool
++bcmspi_test_card(sdioh_info_t *sd)
++{
++	uint32 regdata;
++	int status;
++
++	if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, &regdata)) != SUCCESS)
++		return FALSE;
++
++	if (regdata == (TEST_RO_DATA_32BIT_LE))
++		sd_trace(("32bit LE regdata = 0x%x\n", regdata));
++	else {
++		sd_trace(("Incorrect 32bit LE regdata = 0x%x\n", regdata));
++		return FALSE;
++	}
++
++
++#define RW_PATTERN1	0xA0A1A2A3
++#define RW_PATTERN2	0x4B5B6B7B
++
++	regdata = RW_PATTERN1;
++	if ((status = bcmspi_card_regwrite(sd, 0, SPID_TEST_RW, 4, regdata)) != SUCCESS)
++		return FALSE;
++	regdata = 0;
++	if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_RW, 4, &regdata)) != SUCCESS)
++		return FALSE;
++	if (regdata != RW_PATTERN1) {
++		sd_err(("Write-Read spid failed. Value wrote = 0x%x, Value read = 0x%x\n",
++			RW_PATTERN1, regdata));
++		return FALSE;
++	} else
++		sd_trace(("R/W spid passed. Value read = 0x%x\n", regdata));
++
++	regdata = RW_PATTERN2;
++	if ((status = bcmspi_card_regwrite(sd, 0, SPID_TEST_RW, 4, regdata)) != SUCCESS)
++		return FALSE;
++	regdata = 0;
++	if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_RW, 4, &regdata)) != SUCCESS)
++		return FALSE;
++	if (regdata != RW_PATTERN2) {
++		sd_err(("Write-Read spid failed. Value wrote = 0x%x, Value read = 0x%x\n",
++			RW_PATTERN2, regdata));
++		return FALSE;
++	} else
++		sd_trace(("R/W spid passed. Value read = 0x%x\n", regdata));
++
++	return TRUE;
++}
++
++static int
++bcmspi_driver_init(sdioh_info_t *sd)
++{
++	sd_trace(("%s\n", __FUNCTION__));
++	if ((bcmspi_host_init(sd)) != SUCCESS) {
++		return ERROR;
++	}
++
++	if (bcmspi_client_init(sd) != SUCCESS) {
++		return ERROR;
++	}
++
++	return SUCCESS;
++}
++
++/* Read device reg */
++static int
++bcmspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data)
++{
++	int status;
++	uint32 cmd_arg, dstatus;
++
++	ASSERT(regsize);
++
++	if (func == 2)
++		sd_trace(("Reg access on F2 will generate error indication in dstatus bits.\n"));
++
++	cmd_arg = 0;
++	cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 0);
++	cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1);	/* Incremental access */
++	cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
++	cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
++	cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize == BLOCK_SIZE_F2 ? 0 : regsize);
++
++	sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d\n",
++	          __FUNCTION__, cmd_arg, func, regaddr, regsize));
++
++	if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, regsize)) != SUCCESS)
++		return status;
++
++	bcmspi_cmd_getdstatus(sd, &dstatus);
++	if (dstatus)
++		sd_trace(("dstatus =0x%x\n", dstatus));
++
++	return SUCCESS;
++}
++
++static int
++bcmspi_card_regread_fixedaddr(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data)
++{
++
++	int status;
++	uint32 cmd_arg;
++	uint32 dstatus;
++
++	ASSERT(regsize);
++
++	if (func == 2)
++		sd_trace(("Reg access on F2 will generate error indication in dstatus bits.\n"));
++
++	cmd_arg = 0;
++	cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 0);
++	cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 0);	/* Fixed access */
++	cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
++	cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
++	cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize);
++
++	sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d\n",
++	          __FUNCTION__, cmd_arg, func, regaddr, regsize));
++
++	if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, regsize)) != SUCCESS)
++		return status;
++
++	sd_trace(("%s: RD result=0x%x\n", __FUNCTION__, *data));
++
++	bcmspi_cmd_getdstatus(sd, &dstatus);
++	sd_trace(("dstatus =0x%x\n", dstatus));
++	return SUCCESS;
++}
++
++/* write a device register */
++static int
++bcmspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 data)
++{
++	int status;
++	uint32 cmd_arg, dstatus;
++
++	ASSERT(regsize);
++
++	cmd_arg = 0;
++
++	cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
++	cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1);	/* Incremental access */
++	cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
++	cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
++	cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize == BLOCK_SIZE_F2 ? 0 : regsize);
++
++	sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d data=0x%x\n",
++	          __FUNCTION__, cmd_arg, func, regaddr, regsize, data));
++
++	if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, regsize)) != SUCCESS)
++		return status;
++
++	bcmspi_cmd_getdstatus(sd, &dstatus);
++	if (dstatus)
++		sd_trace(("dstatus=0x%x\n", dstatus));
++
++	return SUCCESS;
++}
++
++/* write a device register - 1 byte */
++static int
++bcmspi_card_bytewrite(sdioh_info_t *sd, int func, uint32 regaddr, uint8 *byte)
++{
++	int status;
++	uint32 cmd_arg;
++	uint32 dstatus;
++	uint32 data = (uint32)(*byte);
++
++	cmd_arg = 0;
++	cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
++	cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1);	/* Incremental access */
++	cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
++	cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
++	cmd_arg = SFIELD(cmd_arg, SPI_LEN, 1);
++
++	sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x data=0x%x\n",
++	          __FUNCTION__, cmd_arg, func, regaddr, data));
++
++	if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, 1)) != SUCCESS)
++		return status;
++
++	bcmspi_cmd_getdstatus(sd, &dstatus);
++	if (dstatus)
++		sd_trace(("dstatus =0x%x\n", dstatus));
++
++	return SUCCESS;
++}
++
++void
++bcmspi_cmd_getdstatus(sdioh_info_t *sd, uint32 *dstatus_buffer)
++{
++	*dstatus_buffer = sd->card_dstatus;
++}
++
++/* 'data' is of type uint32 whereas other buffers are of type uint8 */
++static int
++bcmspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd_arg,
++                uint32 *data, uint32 datalen)
++{
++	uint32	i, j;
++	uint8	resp_delay = 0;
++	int	err = SUCCESS;
++	uint32	hostlen;
++	uint32 spilen = 0;
++	uint32 dstatus_idx = 0;
++	uint16 templen, buslen, len, *ptr = NULL;
++
++	sd_trace(("spi cmd = 0x%x\n", cmd_arg));
++
++	/* Set up and issue the SPI command.  MSByte goes out on bus first.  Increase datalen
++	 * according to the wordlen mode(16/32bit) the device is in.
++	 */
++	if (sd->wordlen == 4) { /* 32bit spid */
++		*(uint32 *)spi_outbuf = SPISWAP_WD4(cmd_arg);
++		if (datalen & 0x3)
++			datalen += (4 - (datalen & 0x3));
++	} else if (sd->wordlen == 2) { /* 16bit spid */
++		*(uint32 *)spi_outbuf = SPISWAP_WD2(cmd_arg);
++		if (datalen & 0x1)
++			datalen++;
++		if (datalen < 4)
++			datalen = ROUNDUP(datalen, 4);
++	} else {
++		sd_err(("Host is %d bit spid, could not create SPI command.\n",
++			8 * sd->wordlen));
++		return ERROR;
++	}
++
++	/* for Write, put the data into the output buffer */
++	if (GFIELD(cmd_arg, SPI_RW_FLAG) == 1) {
++		/* We send len field of hw-header always a mod16 size, both from host and dongle */
++		if (datalen != 0) {
++			for (i = 0; i < datalen/4; i++) {
++				if (sd->wordlen == 4) { /* 32bit spid */
++					*(uint32 *)&spi_outbuf[i * 4 + CMDLEN] =
++						SPISWAP_WD4(data[i]);
++				} else if (sd->wordlen == 2) { /* 16bit spid */
++					*(uint32 *)&spi_outbuf[i * 4 + CMDLEN] =
++						SPISWAP_WD2(data[i]);
++				}
++			}
++		}
++	}
++
++	/* Append resp-delay number of bytes and clock them out for F0/1/2 reads. */
++	if ((GFIELD(cmd_arg, SPI_RW_FLAG) == 0)) {
++		int func = GFIELD(cmd_arg, SPI_FUNCTION);
++		switch (func) {
++			case 0:
++				if (sd->resp_delay_new)
++					resp_delay = GSPI_F0_RESP_DELAY;
++				else
++					resp_delay = sd->resp_delay_all ? F0_RESPONSE_DELAY : 0;
++				break;
++			case 1:
++				if (sd->resp_delay_new)
++					resp_delay = GSPI_F1_RESP_DELAY;
++				else
++					resp_delay = F1_RESPONSE_DELAY;
++				break;
++			case 2:
++				if (sd->resp_delay_new)
++					resp_delay = GSPI_F2_RESP_DELAY;
++				else
++					resp_delay = sd->resp_delay_all ? F2_RESPONSE_DELAY : 0;
++				break;
++			default:
++				ASSERT(0);
++				break;
++		}
++		/* Program response delay */
++		if (sd->resp_delay_new == FALSE)
++			bcmspi_prog_resp_delay(sd, func, resp_delay);
++	}
++
++	/* +4 for cmd and +4 for dstatus */
++	hostlen = datalen + 8 + resp_delay;
++	hostlen += dstatus_idx;
++	hostlen += (4 - (hostlen & 0x3));
++	spi_sendrecv(sd, spi_outbuf, spi_inbuf, hostlen);
++
++	/* for Read, get the data into the input buffer */
++	if (datalen != 0) {
++		if (GFIELD(cmd_arg, SPI_RW_FLAG) == 0) { /* if read cmd */
++			for (j = 0; j < datalen/4; j++) {
++				if (sd->wordlen == 4) { /* 32bit spid */
++					data[j] = SPISWAP_WD4(*(uint32 *)&spi_inbuf[j * 4 +
++					            CMDLEN + resp_delay]);
++				} else if (sd->wordlen == 2) { /* 16bit spid */
++					data[j] = SPISWAP_WD2(*(uint32 *)&spi_inbuf[j * 4 +
++					            CMDLEN + resp_delay]);
++				}
++			}
++		}
++	}
++
++	dstatus_idx += (datalen + CMDLEN + resp_delay);
++	/* Last 4bytes are dstatus.  Device is configured to return status bits. */
++	if (sd->wordlen == 4) { /* 32bit spid */
++		sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf[dstatus_idx]);
++	} else if (sd->wordlen == 2) { /* 16bit spid */
++		sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf[dstatus_idx]);
++	} else {
++		sd_err(("Host is %d bit machine, could not read SPI dstatus.\n",
++			8 * sd->wordlen));
++		return ERROR;
++	}
++	if (sd->card_dstatus == 0xffffffff) {
++		sd_err(("looks like not a GSPI device or device is not powered.\n"));
++	}
++
++	err = bcmspi_update_stats(sd, cmd_arg);
++
++	return err;
++
++}
++
++static int
++bcmspi_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo,
++                uint32 addr, int nbytes, uint32 *data)
++{
++	int status;
++	uint32 cmd_arg;
++	bool write = rw == SDIOH_READ ? 0 : 1;
++	uint retries = 0;
++
++	bool enable;
++	uint32	spilen;
++
++	cmd_arg = 0;
++
++	ASSERT(nbytes);
++	ASSERT(nbytes <= sd->client_block_size[func]);
++
++	if (write) sd->t_cnt++; else sd->r_cnt++;
++
++	if (func == 2) {
++		/* Frame len check limited by gSPI. */
++		if ((nbytes > 2000) && write) {
++			sd_trace((">2KB write: F2 wr of %d bytes\n", nbytes));
++		}
++		/* ASSERT(nbytes <= 2048); Fix bigger len gspi issue and uncomment. */
++		/* If F2 fifo on device is not ready to receive data, don't do F2 transfer */
++		if (write) {
++			uint32 dstatus;
++			/* check F2 ready with cached one */
++			bcmspi_cmd_getdstatus(sd, &dstatus);
++			if ((dstatus & STATUS_F2_RX_READY) == 0) {
++				retries = WAIT_F2RXFIFORDY;
++				enable = 0;
++				while (retries-- && !enable) {
++					OSL_DELAY(WAIT_F2RXFIFORDY_DELAY * 1000);
++					bcmspi_card_regread(sd, SPI_FUNC_0, SPID_STATUS_REG, 4,
++					                   &dstatus);
++					if (dstatus & STATUS_F2_RX_READY)
++						enable = TRUE;
++				}
++				if (!enable) {
++					struct spierrstats_t *spierrstats = &sd->spierrstats;
++					spierrstats->f2rxnotready++;
++					sd_err(("F2 FIFO is not ready to receive data.\n"));
++					return ERROR;
++				}
++				sd_trace(("No of retries on F2 ready %d\n",
++					(WAIT_F2RXFIFORDY - retries)));
++			}
++		}
++	}
++
++	/* F2 transfers happen on 0 addr */
++	addr = (func == 2) ? 0 : addr;
++
++	/* In pio mode buffer is read using fixed address fifo in func 1 */
++	if ((func == 1) && (fifo))
++		cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 0);
++	else
++		cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1);
++
++	cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
++	cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, addr);
++	cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, write);
++	spilen = sd->data_xfer_count = MIN(sd->client_block_size[func], nbytes);
++	if ((sd->dwordmode == TRUE) && (GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_2)) {
++		/* convert len to mod4 size */
++		spilen = spilen + ((spilen & 0x3) ? (4 - (spilen & 0x3)): 0);
++		cmd_arg = SFIELD(cmd_arg, SPI_LEN, (spilen >> 2));
++	} else
++		cmd_arg = SFIELD(cmd_arg, SPI_LEN, spilen);
++
++	if ((func == 2) && (fifo == 1)) {
++		sd_data(("%s: %s func %d, %s, addr 0x%x, len %d bytes, r_cnt %d t_cnt %d\n",
++		          __FUNCTION__, write ? "Wr" : "Rd", func, "INCR",
++		          addr, nbytes, sd->r_cnt, sd->t_cnt));
++	}
++
++	sd_trace(("%s cmd_arg = 0x%x\n", __FUNCTION__, cmd_arg));
++	sd_data(("%s: %s func %d, %s, addr 0x%x, len %d bytes, r_cnt %d t_cnt %d\n",
++	         __FUNCTION__, write ? "Wd" : "Rd", func, "INCR",
++	         addr, nbytes, sd->r_cnt, sd->t_cnt));
++
++
++	if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, nbytes)) != SUCCESS) {
++		sd_err(("%s: cmd_issue failed for %s\n", __FUNCTION__,
++			(write ? "write" : "read")));
++		return status;
++	}
++
++	/* gSPI expects that hw-header-len is equal to spi-command-len */
++	if ((func == 2) && (rw == SDIOH_WRITE) && (sd->dwordmode == FALSE)) {
++		ASSERT((uint16)sd->data_xfer_count == (uint16)(*data & 0xffff));
++		ASSERT((uint16)sd->data_xfer_count == (uint16)(~((*data & 0xffff0000) >> 16)));
++	}
++
++	if ((nbytes > 2000) && !write) {
++		sd_trace((">2KB read: F2 rd of %d bytes\n", nbytes));
++	}
++
++	return SUCCESS;
++}
++
++/* Reset and re-initialize the device */
++int
++sdioh_sdio_reset(sdioh_info_t *si)
++{
++	si->card_init_done = FALSE;
++	return bcmspi_client_init(si);
++}
++
++SDIOH_API_RC
++sdioh_gpioouten(sdioh_info_t *sd, uint32 gpio)
++{
++	return SDIOH_API_RC_FAIL;
++}
++
++SDIOH_API_RC
++sdioh_gpioout(sdioh_info_t *sd, uint32 gpio, bool enab)
++{
++	return SDIOH_API_RC_FAIL;
++}
++
++bool
++sdioh_gpioin(sdioh_info_t *sd, uint32 gpio)
++{
++	return FALSE;
++}
++
++SDIOH_API_RC
++sdioh_gpio_init(sdioh_info_t *sd)
++{
++	return SDIOH_API_RC_FAIL;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/bcmutils.c b/module_drivers/drivers/net/wireless/bcmdhd/bcmutils.c
+new file mode 100644
+index 000000000..1ba8481c5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/bcmutils.c
+@@ -0,0 +1,4106 @@
++/*
++ * Driver O/S-independent utility routines
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmutils.c 699163 2017-05-12 05:18:23Z $
++ */
++
++#include <bcm_cfg.h>
++#include <typedefs.h>
++#include <bcmdefs.h>
++#include <stdarg.h>
++#ifdef BCMDRIVER
++
++#include <osl.h>
++#include <bcmutils.h>
++
++#else /* !BCMDRIVER */
++
++#include <stdio.h>
++#include <string.h>
++#include <bcmutils.h>
++
++#if defined(BCMEXTSUP)
++#include <bcm_osl.h>
++#endif
++
++#ifndef ASSERT
++#define ASSERT(exp)
++#endif
++
++#endif /* !BCMDRIVER */
++
++#include <bcmendian.h>
++#include <bcmdevs.h>
++#include <ethernet.h>
++#include <vlan.h>
++#include <bcmip.h>
++#include <802.1d.h>
++#include <802.11.h>
++#include <bcmip.h>
++#include <bcmipv6.h>
++#include <bcmtcp.h>
++
++/* Look-up table to calculate head room present in a number */
++static const uint8 msb_table[] = {
++	0, 1, 2, 2, 3, 3, 3, 3,
++	4, 4, 4, 4, 4, 4, 4, 4,
++	5, 5, 5, 5, 5, 5, 5, 5,
++	5, 5, 5, 5, 5, 5, 5, 5,
++	6, 6, 6, 6, 6, 6, 6, 6,
++	6, 6, 6, 6, 6, 6, 6, 6,
++	6, 6, 6, 6, 6, 6, 6, 6,
++	6, 6, 6, 6, 6, 6, 6, 6,
++	7, 7, 7, 7, 7, 7, 7, 7,
++	7, 7, 7, 7, 7, 7, 7, 7,
++	7, 7, 7, 7, 7, 7, 7, 7,
++	7, 7, 7, 7, 7, 7, 7, 7,
++	7, 7, 7, 7, 7, 7, 7, 7,
++	7, 7, 7, 7, 7, 7, 7, 7,
++	7, 7, 7, 7, 7, 7, 7, 7,
++	7, 7, 7, 7, 7, 7, 7, 7,
++	8, 8, 8, 8, 8, 8, 8, 8,
++	8, 8, 8, 8, 8, 8, 8, 8,
++	8, 8, 8, 8, 8, 8, 8, 8,
++	8, 8, 8, 8, 8, 8, 8, 8,
++	8, 8, 8, 8, 8, 8, 8, 8,
++	8, 8, 8, 8, 8, 8, 8, 8,
++	8, 8, 8, 8, 8, 8, 8, 8,
++	8, 8, 8, 8, 8, 8, 8, 8,
++	8, 8, 8, 8, 8, 8, 8, 8,
++	8, 8, 8, 8, 8, 8, 8, 8,
++	8, 8, 8, 8, 8, 8, 8, 8,
++	8, 8, 8, 8, 8, 8, 8, 8,
++	8, 8, 8, 8, 8, 8, 8, 8,
++	8, 8, 8, 8, 8, 8, 8, 8,
++	8, 8, 8, 8, 8, 8, 8, 8,
++	8, 8, 8, 8, 8, 8, 8, 8,
++};
++
++void *_bcmutils_dummy_fn = NULL;
++
++
++
++
++#ifdef BCMDRIVER
++
++
++/* copy a pkt buffer chain into a buffer */
++uint
++pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf)
++{
++	uint n, ret = 0;
++
++	if (len < 0)
++		len = 4096;	/* "infinite" */
++
++	/* skip 'offset' bytes */
++	for (; p && offset; p = PKTNEXT(osh, p)) {
++		if (offset < (uint)PKTLEN(osh, p))
++			break;
++		offset -= PKTLEN(osh, p);
++	}
++
++	if (!p)
++		return 0;
++
++	/* copy the data */
++	for (; p && len; p = PKTNEXT(osh, p)) {
++		n = MIN((uint)PKTLEN(osh, p) - offset, (uint)len);
++		bcopy(PKTDATA(osh, p) + offset, buf, n);
++		buf += n;
++		len -= n;
++		ret += n;
++		offset = 0;
++	}
++
++	return ret;
++}
++
++/* copy a buffer into a pkt buffer chain */
++uint
++pktfrombuf(osl_t *osh, void *p, uint offset, int len, uchar *buf)
++{
++	uint n, ret = 0;
++
++
++	/* skip 'offset' bytes */
++	for (; p && offset; p = PKTNEXT(osh, p)) {
++		if (offset < (uint)PKTLEN(osh, p))
++			break;
++		offset -= PKTLEN(osh, p);
++	}
++
++	if (!p)
++		return 0;
++
++	/* copy the data */
++	for (; p && len; p = PKTNEXT(osh, p)) {
++		n = MIN((uint)PKTLEN(osh, p) - offset, (uint)len);
++		bcopy(buf, PKTDATA(osh, p) + offset, n);
++		buf += n;
++		len -= n;
++		ret += n;
++		offset = 0;
++	}
++
++	return ret;
++}
++
++
++
++/* return total length of buffer chain */
++uint BCMFASTPATH
++pkttotlen(osl_t *osh, void *p)
++{
++	uint total;
++	int len;
++
++	total = 0;
++	for (; p; p = PKTNEXT(osh, p)) {
++		len = PKTLEN(osh, p);
++		total += len;
++#ifdef BCMLFRAG
++		if (BCMLFRAG_ENAB()) {
++			if (PKTISFRAG(osh, p)) {
++				total += PKTFRAGTOTLEN(osh, p);
++			}
++		}
++#endif
++	}
++
++	return (total);
++}
++
++/* return the last buffer of chained pkt */
++void *
++pktlast(osl_t *osh, void *p)
++{
++	for (; PKTNEXT(osh, p); p = PKTNEXT(osh, p))
++		;
++
++	return (p);
++}
++
++/* count segments of a chained packet */
++uint BCMFASTPATH
++pktsegcnt(osl_t *osh, void *p)
++{
++	uint cnt;
++
++	for (cnt = 0; p; p = PKTNEXT(osh, p)) {
++		cnt++;
++#ifdef BCMLFRAG
++		if (BCMLFRAG_ENAB()) {
++			if (PKTISFRAG(osh, p)) {
++				cnt += PKTFRAGTOTNUM(osh, p);
++			}
++		}
++#endif
++	}
++
++	return cnt;
++}
++
++
++/* count segments of a chained packet */
++uint BCMFASTPATH
++pktsegcnt_war(osl_t *osh, void *p)
++{
++	uint cnt;
++	uint8 *pktdata;
++	uint len, remain, align64;
++
++	for (cnt = 0; p; p = PKTNEXT(osh, p)) {
++		cnt++;
++		len = PKTLEN(osh, p);
++		if (len > 128) {
++			pktdata = (uint8 *)PKTDATA(osh, p);	/* starting address of data */
++			/* Check for page boundary straddle (2048B) */
++			if (((uintptr)pktdata & ~0x7ff) != ((uintptr)(pktdata+len) & ~0x7ff))
++				cnt++;
++
++			align64 = (uint)((uintptr)pktdata & 0x3f);	/* aligned to 64B */
++			align64 = (64 - align64) & 0x3f;
++			len -= align64;		/* bytes from aligned 64B to end */
++			/* if aligned to 128B, check for MOD 128 between 1 to 4B */
++			remain = len % 128;
++			if (remain > 0 && remain <= 4)
++				cnt++;		/* add extra seg */
++		}
++	}
++
++	return cnt;
++}
++
++uint8 * BCMFASTPATH
++pktdataoffset(osl_t *osh, void *p,  uint offset)
++{
++	uint total = pkttotlen(osh, p);
++	uint pkt_off = 0, len = 0;
++	uint8 *pdata = (uint8 *) PKTDATA(osh, p);
++
++	if (offset > total)
++		return NULL;
++
++	for (; p; p = PKTNEXT(osh, p)) {
++		pdata = (uint8 *) PKTDATA(osh, p);
++		pkt_off = offset - len;
++		len += PKTLEN(osh, p);
++		if (len > offset)
++			break;
++	}
++	return (uint8*) (pdata+pkt_off);
++}
++
++
++/* given a offset in pdata, find the pkt seg hdr */
++void *
++pktoffset(osl_t *osh, void *p,  uint offset)
++{
++	uint total = pkttotlen(osh, p);
++	uint len = 0;
++
++	if (offset > total)
++		return NULL;
++
++	for (; p; p = PKTNEXT(osh, p)) {
++		len += PKTLEN(osh, p);
++		if (len > offset)
++			break;
++	}
++	return p;
++}
++
++#endif /* BCMDRIVER */
++
++#if !defined(BCMROMOFFLOAD_EXCLUDE_BCMUTILS_FUNCS)
++const unsigned char bcm_ctype[] = {
++
++	_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,			/* 0-7 */
++	_BCM_C, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C,
++	_BCM_C,	/* 8-15 */
++	_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,			/* 16-23 */
++	_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,			/* 24-31 */
++	_BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,		/* 32-39 */
++	_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,			/* 40-47 */
++	_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,			/* 48-55 */
++	_BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,			/* 56-63 */
++	_BCM_P, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X,
++	_BCM_U|_BCM_X, _BCM_U, /* 64-71 */
++	_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,			/* 72-79 */
++	_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,			/* 80-87 */
++	_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,			/* 88-95 */
++	_BCM_P, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X,
++	_BCM_L|_BCM_X, _BCM_L, /* 96-103 */
++	_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
++	_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
++	_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
++	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,		/* 128-143 */
++	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,		/* 144-159 */
++	_BCM_S|_BCM_SP, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
++	_BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,	/* 160-175 */
++	_BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
++	_BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,	/* 176-191 */
++	_BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U,
++	_BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U,	/* 192-207 */
++	_BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_P, _BCM_U, _BCM_U, _BCM_U,
++	_BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_L,	/* 208-223 */
++	_BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L,
++	_BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L,	/* 224-239 */
++	_BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_P, _BCM_L, _BCM_L, _BCM_L,
++	_BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L /* 240-255 */
++};
++
++ulong
++bcm_strtoul(const char *cp, char **endp, uint base)
++{
++	ulong result, last_result = 0, value;
++	bool minus;
++
++	minus = FALSE;
++
++	while (bcm_isspace(*cp))
++		cp++;
++
++	if (cp[0] == '+')
++		cp++;
++	else if (cp[0] == '-') {
++		minus = TRUE;
++		cp++;
++	}
++
++	if (base == 0) {
++		if (cp[0] == '0') {
++			if ((cp[1] == 'x') || (cp[1] == 'X')) {
++				base = 16;
++				cp = &cp[2];
++			} else {
++				base = 8;
++				cp = &cp[1];
++			}
++		} else
++			base = 10;
++	} else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
++		cp = &cp[2];
++	}
++
++	result = 0;
++
++	while (bcm_isxdigit(*cp) &&
++	       (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
++		result = result*base + value;
++		/* Detected overflow */
++		if (result < last_result && !minus) {
++			if (endp) {
++				/* Go to the end of current number */
++				while (bcm_isxdigit(*cp)) {
++					cp++;
++				}
++				*endp = DISCARD_QUAL(cp, char);
++			}
++			return (ulong)-1;
++		}
++		last_result = result;
++		cp++;
++	}
++
++	if (minus)
++		result = (ulong)(-(long)result);
++
++	if (endp)
++		*endp = DISCARD_QUAL(cp, char);
++
++	return (result);
++}
++
++int
++bcm_atoi(const char *s)
++{
++	return (int)bcm_strtoul(s, NULL, 10);
++}
++
++/* return pointer to location of substring 'needle' in 'haystack' */
++char *
++bcmstrstr(const char *haystack, const char *needle)
++{
++	int len, nlen;
++	int i;
++
++	if ((haystack == NULL) || (needle == NULL))
++		return DISCARD_QUAL(haystack, char);
++
++	nlen = (int)strlen(needle);
++	len = (int)strlen(haystack) - nlen + 1;
++
++	for (i = 0; i < len; i++)
++		if (memcmp(needle, &haystack[i], nlen) == 0)
++			return DISCARD_QUAL(&haystack[i], char);
++	return (NULL);
++}
++
++char *
++bcmstrnstr(const char *s, uint s_len, const char *substr, uint substr_len)
++{
++	for (; s_len >= substr_len; s++, s_len--)
++		if (strncmp(s, substr, substr_len) == 0)
++			return DISCARD_QUAL(s, char);
++
++	return NULL;
++}
++
++char *
++bcmstrcat(char *dest, const char *src)
++{
++	char *p;
++
++	p = dest + strlen(dest);
++
++	while ((*p++ = *src++) != '\0')
++		;
++
++	return (dest);
++}
++
++char *
++bcmstrncat(char *dest, const char *src, uint size)
++{
++	char *endp;
++	char *p;
++
++	p = dest + strlen(dest);
++	endp = p + size;
++
++	while (p != endp && (*p++ = *src++) != '\0')
++		;
++
++	return (dest);
++}
++
++
++/****************************************************************************
++* Function:   bcmstrtok
++*
++* Purpose:
++*  Tokenizes a string. This function is conceptually similiar to ANSI C strtok(),
++*  but allows strToken() to be used by different strings or callers at the same
++*  time. Each call modifies '*string' by substituting a NULL character for the
++*  first delimiter that is encountered, and updates 'string' to point to the char
++*  after the delimiter. Leading delimiters are skipped.
++*
++* Parameters:
++*  string      (mod) Ptr to string ptr, updated by token.
++*  delimiters  (in)  Set of delimiter characters.
++*  tokdelim    (out) Character that delimits the returned token. (May
++*                    be set to NULL if token delimiter is not required).
++*
++* Returns:  Pointer to the next token found. NULL when no more tokens are found.
++*****************************************************************************
++*/
++char *
++bcmstrtok(char **string, const char *delimiters, char *tokdelim)
++{
++	unsigned char *str;
++	unsigned long map[8];
++	int count;
++	char *nextoken;
++
++	if (tokdelim != NULL) {
++		/* Prime the token delimiter */
++		*tokdelim = '\0';
++	}
++
++	/* Clear control map */
++	for (count = 0; count < 8; count++) {
++		map[count] = 0;
++	}
++
++	/* Set bits in delimiter table */
++	do {
++		map[*delimiters >> 5] |= (1 << (*delimiters & 31));
++	}
++	while (*delimiters++);
++
++	str = (unsigned char*)*string;
++
++	/* Find beginning of token (skip over leading delimiters). Note that
++	 * there is no token iff this loop sets str to point to the terminal
++	 * null (*str == '\0')
++	 */
++	while (((map[*str >> 5] & (1 << (*str & 31))) && *str) || (*str == ' ')) {
++		str++;
++	}
++
++	nextoken = (char*)str;
++
++	/* Find the end of the token. If it is not the end of the string,
++	 * put a null there.
++	 */
++	for (; *str; str++) {
++		if (map[*str >> 5] & (1 << (*str & 31))) {
++			if (tokdelim != NULL) {
++				*tokdelim = *str;
++			}
++
++			*str++ = '\0';
++			break;
++		}
++	}
++
++	*string = (char*)str;
++
++	/* Determine if a token has been found. */
++	if (nextoken == (char *) str) {
++		return NULL;
++	}
++	else {
++		return nextoken;
++	}
++}
++
++
++#define xToLower(C) \
++	((C >= 'A' && C <= 'Z') ? (char)((int)C - (int)'A' + (int)'a') : C)
++
++
++/****************************************************************************
++* Function:   bcmstricmp
++*
++* Purpose:    Compare to strings case insensitively.
++*
++* Parameters: s1 (in) First string to compare.
++*             s2 (in) Second string to compare.
++*
++* Returns:    Return 0 if the two strings are equal, -1 if t1 < t2 and 1 if
++*             t1 > t2, when ignoring case sensitivity.
++*****************************************************************************
++*/
++int
++bcmstricmp(const char *s1, const char *s2)
++{
++	char dc, sc;
++
++	while (*s2 && *s1) {
++		dc = xToLower(*s1);
++		sc = xToLower(*s2);
++		if (dc < sc) return -1;
++		if (dc > sc) return 1;
++		s1++;
++		s2++;
++	}
++
++	if (*s1 && !*s2) return 1;
++	if (!*s1 && *s2) return -1;
++	return 0;
++}
++
++
++/****************************************************************************
++* Function:   bcmstrnicmp
++*
++* Purpose:    Compare to strings case insensitively, upto a max of 'cnt'
++*             characters.
++*
++* Parameters: s1  (in) First string to compare.
++*             s2  (in) Second string to compare.
++*             cnt (in) Max characters to compare.
++*
++* Returns:    Return 0 if the two strings are equal, -1 if t1 < t2 and 1 if
++*             t1 > t2, when ignoring case sensitivity.
++*****************************************************************************
++*/
++int
++bcmstrnicmp(const char* s1, const char* s2, int cnt)
++{
++	char dc, sc;
++
++	while (*s2 && *s1 && cnt) {
++		dc = xToLower(*s1);
++		sc = xToLower(*s2);
++		if (dc < sc) return -1;
++		if (dc > sc) return 1;
++		s1++;
++		s2++;
++		cnt--;
++	}
++
++	if (!cnt) return 0;
++	if (*s1 && !*s2) return 1;
++	if (!*s1 && *s2) return -1;
++	return 0;
++}
++
++/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
++int
++bcm_ether_atoe(const char *p, struct ether_addr *ea)
++{
++	int i = 0;
++	char *ep;
++
++	for (;;) {
++		ea->octet[i++] = (char) bcm_strtoul(p, &ep, 16);
++		p = ep;
++		if (!*p++ || i == 6)
++			break;
++	}
++
++	return (i == 6);
++}
++
++int
++bcm_atoipv4(const char *p, struct ipv4_addr *ip)
++{
++
++	int i = 0;
++	char *c;
++	for (;;) {
++		ip->addr[i++] = (uint8)bcm_strtoul(p, &c, 0);
++		if (*c++ != '.' || i == IPV4_ADDR_LEN)
++			break;
++		p = c;
++	}
++	return (i == IPV4_ADDR_LEN);
++}
++#endif	/* !BCMROMOFFLOAD_EXCLUDE_BCMUTILS_FUNCS */
++
++
++#if defined(CONFIG_USBRNDIS_RETAIL) || defined(NDIS_MINIPORT_DRIVER)
++/* registry routine buffer preparation utility functions:
++ * parameter order is like strncpy, but returns count
++ * of bytes copied. Minimum bytes copied is null char(1)/wchar(2)
++ */
++ulong
++wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen)
++{
++	ulong copyct = 1;
++	ushort i;
++
++	if (abuflen == 0)
++		return 0;
++
++	/* wbuflen is in bytes */
++	wbuflen /= sizeof(ushort);
++
++	for (i = 0; i < wbuflen; ++i) {
++		if (--abuflen == 0)
++			break;
++		*abuf++ = (char) *wbuf++;
++		++copyct;
++	}
++	*abuf = '\0';
++
++	return copyct;
++}
++#endif /* CONFIG_USBRNDIS_RETAIL || NDIS_MINIPORT_DRIVER */
++
++char *
++bcm_ether_ntoa(const struct ether_addr *ea, char *buf)
++{
++	static const char hex[] =
++	  {
++		  '0', '1', '2', '3', '4', '5', '6', '7',
++		  '8', '9', 'a', 'b', 'c', 'd', 'e', 'f'
++	  };
++	const uint8 *octet = ea->octet;
++	char *p = buf;
++	int i;
++
++	for (i = 0; i < 6; i++, octet++) {
++		*p++ = hex[(*octet >> 4) & 0xf];
++		*p++ = hex[*octet & 0xf];
++		*p++ = ':';
++	}
++
++	*(p-1) = '\0';
++
++	return (buf);
++}
++
++char *
++bcm_ip_ntoa(struct ipv4_addr *ia, char *buf)
++{
++	snprintf(buf, 16, "%d.%d.%d.%d",
++	         ia->addr[0], ia->addr[1], ia->addr[2], ia->addr[3]);
++	return (buf);
++}
++
++char *
++bcm_ipv6_ntoa(void *ipv6, char *buf)
++{
++	/* Implementing RFC 5952 Sections 4 + 5 */
++	/* Not thoroughly tested */
++	uint16 tmp[8];
++	uint16 *a = &tmp[0];
++	char *p = buf;
++	int i, i_max = -1, cnt = 0, cnt_max = 1;
++	uint8 *a4 = NULL;
++	memcpy((uint8 *)&tmp[0], (uint8 *)ipv6, IPV6_ADDR_LEN);
++
++	for (i = 0; i < IPV6_ADDR_LEN/2; i++) {
++		if (a[i]) {
++			if (cnt > cnt_max) {
++				cnt_max = cnt;
++				i_max = i - cnt;
++			}
++			cnt = 0;
++		} else
++			cnt++;
++	}
++	if (cnt > cnt_max) {
++		cnt_max = cnt;
++		i_max = i - cnt;
++	}
++	if (i_max == 0 &&
++		/* IPv4-translated: ::ffff:0:a.b.c.d */
++		((cnt_max == 4 && a[4] == 0xffff && a[5] == 0) ||
++		/* IPv4-mapped: ::ffff:a.b.c.d */
++		(cnt_max == 5 && a[5] == 0xffff)))
++		a4 = (uint8*) (a + 6);
++
++	for (i = 0; i < IPV6_ADDR_LEN/2; i++) {
++		if ((uint8*) (a + i) == a4) {
++			snprintf(p, 16, ":%u.%u.%u.%u", a4[0], a4[1], a4[2], a4[3]);
++			break;
++		} else if (i == i_max) {
++			*p++ = ':';
++			i += cnt_max - 1;
++			p[0] = ':';
++			p[1] = '\0';
++		} else {
++			if (i)
++				*p++ = ':';
++			p += snprintf(p, 8, "%x", ntoh16(a[i]));
++		}
++	}
++
++	return buf;
++}
++#ifdef BCMDRIVER
++
++void
++bcm_mdelay(uint ms)
++{
++	uint i;
++
++	for (i = 0; i < ms; i++) {
++		OSL_DELAY(1000);
++	}
++}
++
++
++
++
++
++#if defined(DHD_DEBUG)
++/* pretty hex print a pkt buffer chain */
++void
++prpkt(const char *msg, osl_t *osh, void *p0)
++{
++	void *p;
++
++	if (msg && (msg[0] != '\0'))
++		printf("%s:\n", msg);
++
++	for (p = p0; p; p = PKTNEXT(osh, p))
++		prhex(NULL, PKTDATA(osh, p), PKTLEN(osh, p));
++}
++#endif	
++
++/* Takes an Ethernet frame and sets out-of-bound PKTPRIO.
++ * Also updates the inplace vlan tag if requested.
++ * For debugging, it returns an indication of what it did.
++ */
++uint BCMFASTPATH
++pktsetprio(void *pkt, bool update_vtag)
++{
++	struct ether_header *eh;
++	struct ethervlan_header *evh;
++	uint8 *pktdata;
++	int priority = 0;
++	int rc = 0;
++
++	pktdata = (uint8 *)PKTDATA(OSH_NULL, pkt);
++	ASSERT(ISALIGNED((uintptr)pktdata, sizeof(uint16)));
++
++	eh = (struct ether_header *) pktdata;
++
++	if (eh->ether_type == hton16(ETHER_TYPE_8021Q)) {
++		uint16 vlan_tag;
++		int vlan_prio, dscp_prio = 0;
++
++		evh = (struct ethervlan_header *)eh;
++
++		vlan_tag = ntoh16(evh->vlan_tag);
++		vlan_prio = (int) (vlan_tag >> VLAN_PRI_SHIFT) & VLAN_PRI_MASK;
++
++		if ((evh->ether_type == hton16(ETHER_TYPE_IP)) ||
++			(evh->ether_type == hton16(ETHER_TYPE_IPV6))) {
++			uint8 *ip_body = pktdata + sizeof(struct ethervlan_header);
++			uint8 tos_tc = IP_TOS46(ip_body);
++			dscp_prio = (int)(tos_tc >> IPV4_TOS_PREC_SHIFT);
++		}
++
++		/* DSCP priority gets precedence over 802.1P (vlan tag) */
++		if (dscp_prio != 0) {
++			priority = dscp_prio;
++			rc |= PKTPRIO_VDSCP;
++		} else {
++			priority = vlan_prio;
++			rc |= PKTPRIO_VLAN;
++		}
++		/*
++		 * If the DSCP priority is not the same as the VLAN priority,
++		 * then overwrite the priority field in the vlan tag, with the
++		 * DSCP priority value. This is required for Linux APs because
++		 * the VLAN driver on Linux, overwrites the skb->priority field
++		 * with the priority value in the vlan tag
++		 */
++		if (update_vtag && (priority != vlan_prio)) {
++			vlan_tag &= ~(VLAN_PRI_MASK << VLAN_PRI_SHIFT);
++			vlan_tag |= (uint16)priority << VLAN_PRI_SHIFT;
++			evh->vlan_tag = hton16(vlan_tag);
++			rc |= PKTPRIO_UPD;
++		}
++#if defined(EAPOL_PKT_PRIO) || defined(DHD_LOSSLESS_ROAMING)
++	} else if (eh->ether_type == hton16(ETHER_TYPE_802_1X)) {
++		priority = PRIO_8021D_NC;
++		rc = PKTPRIO_DSCP;
++#endif /* EAPOL_PKT_PRIO || DHD_LOSSLESS_ROAMING */
++	} else if ((eh->ether_type == hton16(ETHER_TYPE_IP)) ||
++		(eh->ether_type == hton16(ETHER_TYPE_IPV6))) {
++		uint8 *ip_body = pktdata + sizeof(struct ether_header);
++		uint8 tos_tc = IP_TOS46(ip_body);
++		uint8 dscp = tos_tc >> IPV4_TOS_DSCP_SHIFT;
++		switch (dscp) {
++		case DSCP_EF:
++			priority = PRIO_8021D_VO;
++			break;
++		case DSCP_AF31:
++		case DSCP_AF32:
++		case DSCP_AF33:
++			priority = PRIO_8021D_CL;
++			break;
++		case DSCP_AF21:
++		case DSCP_AF22:
++		case DSCP_AF23:
++		case DSCP_AF11:
++		case DSCP_AF12:
++		case DSCP_AF13:
++			priority = PRIO_8021D_EE;
++			break;
++		default:
++			priority = (int)(tos_tc >> IPV4_TOS_PREC_SHIFT);
++			break;
++		}
++
++		rc |= PKTPRIO_DSCP;
++	}
++
++	ASSERT(priority >= 0 && priority <= MAXPRIO);
++	PKTSETPRIO(pkt, priority);
++	return (rc | priority);
++}
++
++/* lookup user priority for specified DSCP */
++static uint8
++dscp2up(uint8 *up_table, uint8 dscp)
++{
++	uint8 user_priority = 255;
++
++	/* lookup up from table if parameters valid */
++	if (up_table != NULL && dscp < UP_TABLE_MAX) {
++		user_priority = up_table[dscp];
++	}
++
++	/* 255 is unused value so return up from dscp */
++	if (user_priority == 255) {
++		user_priority = dscp >> (IPV4_TOS_PREC_SHIFT - IPV4_TOS_DSCP_SHIFT);
++	}
++
++	return user_priority;
++}
++
++/* set user priority by QoS Map Set table (UP table), table size is UP_TABLE_MAX */
++uint BCMFASTPATH
++pktsetprio_qms(void *pkt, uint8* up_table, bool update_vtag)
++{
++	if (up_table) {
++		uint8 *pktdata;
++		uint pktlen;
++		uint8 dscp;
++		uint user_priority = 0;
++		uint rc = 0;
++
++		pktdata = (uint8 *)PKTDATA(OSH_NULL, pkt);
++		pktlen = PKTLEN(OSH_NULL, pkt);
++
++		if (pktgetdscp(pktdata, pktlen, &dscp)) {
++			rc = PKTPRIO_DSCP;
++			user_priority = dscp2up(up_table, dscp);
++			PKTSETPRIO(pkt, user_priority);
++		}
++
++		return (rc | user_priority);
++	} else {
++		return pktsetprio(pkt, update_vtag);
++	}
++}
++
++/* Returns TRUE and DSCP if IP header found, FALSE otherwise.
++ */
++bool BCMFASTPATH
++pktgetdscp(uint8 *pktdata, uint pktlen, uint8 *dscp)
++{
++	struct ether_header *eh;
++	struct ethervlan_header *evh;
++	uint8 *ip_body;
++	bool rc = FALSE;
++
++	/* minimum length is ether header and IP header */
++	if (pktlen < sizeof(struct ether_header) + IPV4_MIN_HEADER_LEN)
++		return FALSE;
++
++	eh = (struct ether_header *) pktdata;
++
++	if (eh->ether_type == HTON16(ETHER_TYPE_IP)) {
++		ip_body = pktdata + sizeof(struct ether_header);
++		*dscp = IP_DSCP46(ip_body);
++		rc = TRUE;
++	}
++	else if (eh->ether_type == HTON16(ETHER_TYPE_8021Q)) {
++		evh = (struct ethervlan_header *)eh;
++
++		/* minimum length is ethervlan header and IP header */
++		if (pktlen >= sizeof(struct ethervlan_header) + IPV4_MIN_HEADER_LEN &&
++			evh->ether_type == HTON16(ETHER_TYPE_IP)) {
++			ip_body = pktdata + sizeof(struct ethervlan_header);
++			*dscp = IP_DSCP46(ip_body);
++			rc = TRUE;
++		}
++	}
++
++	return rc;
++}
++
++/* Add to adjust the 802.1x priority */
++void
++pktset8021xprio(void *pkt, int prio)
++{
++	struct ether_header *eh;
++	uint8 *pktdata;
++	if(prio == PKTPRIO(pkt))
++		return;
++	pktdata = (uint8 *)PKTDATA(OSH_NULL, pkt);
++	ASSERT(ISALIGNED((uintptr)pktdata, sizeof(uint16)));
++	eh = (struct ether_header *) pktdata;
++	if (eh->ether_type == hton16(ETHER_TYPE_802_1X)) {
++		ASSERT(prio >= 0 && prio <= MAXPRIO);
++		PKTSETPRIO(pkt, prio);
++	}
++}
++
++/* usr_prio range from low to high with usr_prio value */
++static bool
++up_table_set(uint8 *up_table, uint8 usr_prio, uint8 low, uint8 high)
++{
++	int i;
++
++	if (usr_prio > 7 || low > high || low >= UP_TABLE_MAX || high >= UP_TABLE_MAX) {
++		return FALSE;
++	}
++
++	for (i = low; i <= high; i++) {
++		up_table[i] = usr_prio;
++	}
++
++	return TRUE;
++}
++
++/* set user priority table */
++int BCMFASTPATH
++wl_set_up_table(uint8 *up_table, bcm_tlv_t *qos_map_ie)
++{
++	uint8 len;
++
++	if (up_table == NULL || qos_map_ie == NULL) {
++		return BCME_ERROR;
++	}
++
++	/* clear table to check table was set or not */
++	memset(up_table, 0xff, UP_TABLE_MAX);
++
++	/* length of QoS Map IE must be 16+n*2, n is number of exceptions */
++	if (qos_map_ie != NULL && qos_map_ie->id == DOT11_MNG_QOS_MAP_ID &&
++			(len = qos_map_ie->len) >= QOS_MAP_FIXED_LENGTH &&
++			(len % 2) == 0) {
++		uint8 *except_ptr = (uint8 *)qos_map_ie->data;
++		uint8 except_len = len - QOS_MAP_FIXED_LENGTH;
++		uint8 *range_ptr = except_ptr + except_len;
++		int i;
++
++		/* fill in ranges */
++		for (i = 0; i < QOS_MAP_FIXED_LENGTH; i += 2) {
++			uint8 low = range_ptr[i];
++			uint8 high = range_ptr[i + 1];
++			if (low == 255 && high == 255) {
++				continue;
++			}
++
++			if (!up_table_set(up_table, i / 2, low, high)) {
++				/* clear the table on failure */
++				memset(up_table, 0xff, UP_TABLE_MAX);
++				return BCME_ERROR;
++			}
++		}
++
++		/* update exceptions */
++		for (i = 0; i < except_len; i += 2) {
++			uint8 dscp = except_ptr[i];
++			uint8 usr_prio = except_ptr[i+1];
++
++			/* exceptions with invalid dscp/usr_prio are ignored */
++			up_table_set(up_table, usr_prio, dscp, dscp);
++		}
++	}
++
++	return BCME_OK;
++}
++
++/* The 0.5KB string table is not removed by compiler even though it's unused */
++
++static char bcm_undeferrstr[32];
++static const char *bcmerrorstrtable[] = BCMERRSTRINGTABLE;
++
++/* Convert the error codes into related error strings  */
++const char *
++bcmerrorstr(int bcmerror)
++{
++	/* check if someone added a bcmerror code but forgot to add errorstring */
++	ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(bcmerrorstrtable) - 1));
++
++	if (bcmerror > 0 || bcmerror < BCME_LAST) {
++		snprintf(bcm_undeferrstr, sizeof(bcm_undeferrstr), "Undefined error %d", bcmerror);
++		return bcm_undeferrstr;
++	}
++
++	ASSERT(strlen(bcmerrorstrtable[-bcmerror]) < BCME_STRLEN);
++
++	return bcmerrorstrtable[-bcmerror];
++}
++
++
++/* iovar table lookup */
++/* could mandate sorted tables and do a binary search */
++const bcm_iovar_t*
++bcm_iovar_lookup(const bcm_iovar_t *table, const char *name)
++{
++	const bcm_iovar_t *vi;
++	const char *lookup_name;
++
++	/* skip any ':' delimited option prefixes */
++	lookup_name = strrchr(name, ':');
++	if (lookup_name != NULL)
++		lookup_name++;
++	else
++		lookup_name = name;
++
++	ASSERT(table != NULL);
++
++	for (vi = table; vi->name; vi++) {
++		if (!strcmp(vi->name, lookup_name))
++			return vi;
++	}
++	/* ran to end of table */
++
++	return NULL; /* var name not found */
++}
++
++int
++bcm_iovar_lencheck(const bcm_iovar_t *vi, void *arg, int len, bool set)
++{
++	int bcmerror = 0;
++	BCM_REFERENCE(arg);
++
++	/* length check on io buf */
++	switch (vi->type) {
++	case IOVT_BOOL:
++	case IOVT_INT8:
++	case IOVT_INT16:
++	case IOVT_INT32:
++	case IOVT_UINT8:
++	case IOVT_UINT16:
++	case IOVT_UINT32:
++		/* all integers are int32 sized args at the ioctl interface */
++		if (len < (int)sizeof(int)) {
++			bcmerror = BCME_BUFTOOSHORT;
++		}
++		break;
++
++	case IOVT_BUFFER:
++		/* buffer must meet minimum length requirement */
++		if (len < vi->minlen) {
++			bcmerror = BCME_BUFTOOSHORT;
++		}
++		break;
++
++	case IOVT_VOID:
++		if (!set) {
++			/* Cannot return nil... */
++			bcmerror = BCME_UNSUPPORTED;
++		} else if (len) {
++			/* Set is an action w/o parameters */
++			bcmerror = BCME_BUFTOOLONG;
++		}
++		break;
++
++	default:
++		/* unknown type for length check in iovar info */
++		ASSERT(0);
++		bcmerror = BCME_UNSUPPORTED;
++	}
++
++	return bcmerror;
++}
++
++#endif	/* BCMDRIVER */
++
++#ifdef BCM_OBJECT_TRACE
++
++#define BCM_OBJECT_MERGE_SAME_OBJ	0
++
++/* some place may add / remove the object to trace list for Linux: */
++/* add:    osl_alloc_skb dev_alloc_skb skb_realloc_headroom dhd_start_xmit */
++/* remove: osl_pktfree dev_kfree_skb netif_rx */
++
++#define BCM_OBJDBG_COUNT          (1024 * 100)
++static spinlock_t dbgobj_lock;
++#define	BCM_OBJDBG_LOCK_INIT()    spin_lock_init(&dbgobj_lock)
++#define	BCM_OBJDBG_LOCK_DESTROY()
++#define	BCM_OBJDBG_LOCK           spin_lock_irqsave
++#define	BCM_OBJDBG_UNLOCK         spin_unlock_irqrestore
++
++#define BCM_OBJDBG_ADDTOHEAD      0
++#define BCM_OBJDBG_ADDTOTAIL      1
++
++#define BCM_OBJDBG_CALLER_LEN     32
++struct bcm_dbgobj {
++	struct bcm_dbgobj *prior;
++	struct bcm_dbgobj *next;
++	uint32 flag;
++	void   *obj;
++	uint32 obj_sn;
++	uint32 obj_state;
++	uint32 line;
++	char   caller[BCM_OBJDBG_CALLER_LEN];
++};
++
++static struct bcm_dbgobj *dbgobj_freehead = NULL;
++static struct bcm_dbgobj *dbgobj_freetail = NULL;
++static struct bcm_dbgobj *dbgobj_objhead = NULL;
++static struct bcm_dbgobj *dbgobj_objtail = NULL;
++
++static uint32 dbgobj_sn = 0;
++static int dbgobj_count = 0;
++static struct bcm_dbgobj bcm_dbg_objs[BCM_OBJDBG_COUNT];
++
++void
++bcm_object_trace_init(void)
++{
++	int i = 0;
++	BCM_OBJDBG_LOCK_INIT();
++	memset(&bcm_dbg_objs, 0x00, sizeof(struct bcm_dbgobj) * BCM_OBJDBG_COUNT);
++	dbgobj_freehead = &bcm_dbg_objs[0];
++	dbgobj_freetail = &bcm_dbg_objs[BCM_OBJDBG_COUNT - 1];
++
++	for (i = 0; i < BCM_OBJDBG_COUNT; ++i) {
++		bcm_dbg_objs[i].next = (i == (BCM_OBJDBG_COUNT - 1)) ?
++			dbgobj_freehead : &bcm_dbg_objs[i + 1];
++		bcm_dbg_objs[i].prior = (i == 0) ?
++			dbgobj_freetail : &bcm_dbg_objs[i - 1];
++	}
++}
++
++void
++bcm_object_trace_deinit(void)
++{
++	if (dbgobj_objhead || dbgobj_objtail) {
++		printf("%s: not all objects are released\n", __FUNCTION__);
++		ASSERT(0);
++	}
++	BCM_OBJDBG_LOCK_DESTROY();
++}
++
++static void
++bcm_object_rm_list(struct bcm_dbgobj **head, struct bcm_dbgobj **tail,
++	struct bcm_dbgobj *dbgobj)
++{
++	if ((dbgobj == *head) && (dbgobj == *tail)) {
++		*head = NULL;
++		*tail = NULL;
++	} else if (dbgobj == *head) {
++		*head = (*head)->next;
++	} else if (dbgobj == *tail) {
++		*tail = (*tail)->prior;
++	}
++	dbgobj->next->prior = dbgobj->prior;
++	dbgobj->prior->next = dbgobj->next;
++}
++
++static void
++bcm_object_add_list(struct bcm_dbgobj **head, struct bcm_dbgobj **tail,
++	struct bcm_dbgobj *dbgobj, int addtotail)
++{
++	if (!(*head) && !(*tail)) {
++		*head = dbgobj;
++		*tail = dbgobj;
++		dbgobj->next = dbgobj;
++		dbgobj->prior = dbgobj;
++	} else if ((*head) && (*tail)) {
++		(*tail)->next = dbgobj;
++		(*head)->prior = dbgobj;
++		dbgobj->next = *head;
++		dbgobj->prior = *tail;
++		if (addtotail == BCM_OBJDBG_ADDTOTAIL)
++			*tail = dbgobj;
++		else
++			*head = dbgobj;
++	} else {
++		ASSERT(0); /* can't be this case */
++	}
++}
++
++static INLINE void
++bcm_object_movetoend(struct bcm_dbgobj **head, struct bcm_dbgobj **tail,
++	struct bcm_dbgobj *dbgobj, int movetotail)
++{
++	if ((*head) && (*tail)) {
++		if (movetotail == BCM_OBJDBG_ADDTOTAIL) {
++			if (dbgobj != (*tail)) {
++				bcm_object_rm_list(head, tail, dbgobj);
++				bcm_object_add_list(head, tail, dbgobj, movetotail);
++			}
++		} else {
++			if (dbgobj != (*head)) {
++				bcm_object_rm_list(head, tail, dbgobj);
++				bcm_object_add_list(head, tail, dbgobj, movetotail);
++			}
++		}
++	} else {
++		ASSERT(0); /* can't be this case */
++	}
++}
++
++void
++bcm_object_trace_opr(void *obj, uint32 opt, const char *caller, int line)
++{
++	struct bcm_dbgobj *dbgobj;
++	unsigned long flags;
++
++	BCM_REFERENCE(flags);
++	BCM_OBJDBG_LOCK(&dbgobj_lock, flags);
++
++	if (opt == BCM_OBJDBG_ADD_PKT ||
++		opt == BCM_OBJDBG_ADD) {
++		dbgobj = dbgobj_objtail;
++		while (dbgobj) {
++			if (dbgobj->obj == obj) {
++				printf("%s: obj %p allocated from %s(%d),"
++					" allocate again from %s(%d)\n",
++					__FUNCTION__, dbgobj->obj,
++					dbgobj->caller, dbgobj->line,
++					caller, line);
++				ASSERT(0);
++				goto EXIT;
++			}
++			dbgobj = dbgobj->prior;
++			if (dbgobj == dbgobj_objtail)
++				break;
++		}
++
++#if BCM_OBJECT_MERGE_SAME_OBJ
++		dbgobj = dbgobj_freetail;
++		while (dbgobj) {
++			if (dbgobj->obj == obj) {
++				goto FREED_ENTRY_FOUND;
++			}
++			dbgobj = dbgobj->prior;
++			if (dbgobj == dbgobj_freetail)
++				break;
++		}
++#endif /* BCM_OBJECT_MERGE_SAME_OBJ */
++
++		dbgobj = dbgobj_freehead;
++#if BCM_OBJECT_MERGE_SAME_OBJ
++FREED_ENTRY_FOUND:
++#endif /* BCM_OBJECT_MERGE_SAME_OBJ */
++		if (!dbgobj) {
++			printf("%s: already got %d objects ?????????????????????\n",
++				__FUNCTION__, BCM_OBJDBG_COUNT);
++			ASSERT(0);
++			goto EXIT;
++		}
++
++		bcm_object_rm_list(&dbgobj_freehead, &dbgobj_freetail, dbgobj);
++		dbgobj->obj = obj;
++		strncpy(dbgobj->caller, caller, BCM_OBJDBG_CALLER_LEN);
++		dbgobj->caller[BCM_OBJDBG_CALLER_LEN-1] = '\0';
++		dbgobj->line = line;
++		dbgobj->flag = 0;
++		if (opt == BCM_OBJDBG_ADD_PKT) {
++			dbgobj->obj_sn = dbgobj_sn++;
++			dbgobj->obj_state = 0;
++			/* first 4 bytes is pkt sn */
++			if (((unsigned long)PKTTAG(obj)) & 0x3)
++				printf("pkt tag address not aligned by 4: %p\n", PKTTAG(obj));
++			*(uint32*)PKTTAG(obj) = dbgobj->obj_sn;
++		}
++		bcm_object_add_list(&dbgobj_objhead, &dbgobj_objtail, dbgobj,
++			BCM_OBJDBG_ADDTOTAIL);
++
++		dbgobj_count++;
++
++	} else if (opt == BCM_OBJDBG_REMOVE) {
++		dbgobj = dbgobj_objtail;
++		while (dbgobj) {
++			if (dbgobj->obj == obj) {
++				if (dbgobj->flag) {
++					printf("%s: rm flagged obj %p flag 0x%08x from %s(%d)\n",
++						__FUNCTION__, obj, dbgobj->flag, caller, line);
++				}
++				bcm_object_rm_list(&dbgobj_objhead, &dbgobj_objtail, dbgobj);
++				memset(dbgobj->caller, 0x00, BCM_OBJDBG_CALLER_LEN);
++				strncpy(dbgobj->caller, caller, BCM_OBJDBG_CALLER_LEN);
++				dbgobj->caller[BCM_OBJDBG_CALLER_LEN-1] = '\0';
++				dbgobj->line = line;
++				bcm_object_add_list(&dbgobj_freehead, &dbgobj_freetail, dbgobj,
++					BCM_OBJDBG_ADDTOTAIL);
++				dbgobj_count--;
++				goto EXIT;
++			}
++			dbgobj = dbgobj->prior;
++			if (dbgobj == dbgobj_objtail)
++				break;
++		}
++
++		dbgobj = dbgobj_freetail;
++		while (dbgobj && dbgobj->obj) {
++			if (dbgobj->obj == obj) {
++				printf("%s: obj %p already freed from from %s(%d),"
++					" try free again from %s(%d)\n",
++					__FUNCTION__, obj,
++					dbgobj->caller, dbgobj->line,
++					caller, line);
++				//ASSERT(0); /* release same obj more than one time? */
++				goto EXIT;
++			}
++			dbgobj = dbgobj->prior;
++			if (dbgobj == dbgobj_freetail)
++				break;
++		}
++
++		printf("%s: ################### release none-existing obj %p from %s(%d)\n",
++			__FUNCTION__, obj, caller, line);
++		//ASSERT(0); /* release same obj more than one time? */
++
++	}
++
++EXIT:
++	BCM_OBJDBG_UNLOCK(&dbgobj_lock, flags);
++	return;
++}
++
++void
++bcm_object_trace_upd(void *obj, void *obj_new)
++{
++	struct bcm_dbgobj *dbgobj;
++	unsigned long flags;
++
++	BCM_REFERENCE(flags);
++	BCM_OBJDBG_LOCK(&dbgobj_lock, flags);
++
++	dbgobj = dbgobj_objtail;
++	while (dbgobj) {
++		if (dbgobj->obj == obj) {
++			dbgobj->obj = obj_new;
++			if (dbgobj != dbgobj_objtail) {
++				bcm_object_movetoend(&dbgobj_objhead, &dbgobj_objtail,
++					dbgobj, BCM_OBJDBG_ADDTOTAIL);
++			}
++			goto EXIT;
++		}
++		dbgobj = dbgobj->prior;
++		if (dbgobj == dbgobj_objtail)
++			break;
++	}
++
++EXIT:
++	BCM_OBJDBG_UNLOCK(&dbgobj_lock, flags);
++	return;
++}
++
++void
++bcm_object_trace_chk(void *obj, uint32 chksn, uint32 sn,
++	const char *caller, int line)
++{
++	struct bcm_dbgobj *dbgobj;
++	unsigned long flags;
++
++	BCM_REFERENCE(flags);
++	BCM_OBJDBG_LOCK(&dbgobj_lock, flags);
++
++	dbgobj = dbgobj_objtail;
++	while (dbgobj) {
++		if ((dbgobj->obj == obj) &&
++			((!chksn) || (dbgobj->obj_sn == sn))) {
++			if (dbgobj != dbgobj_objtail) {
++				bcm_object_movetoend(&dbgobj_objhead, &dbgobj_objtail,
++					dbgobj, BCM_OBJDBG_ADDTOTAIL);
++			}
++			goto EXIT;
++		}
++		dbgobj = dbgobj->prior;
++		if (dbgobj == dbgobj_objtail)
++			break;
++	}
++
++	dbgobj = dbgobj_freetail;
++	while (dbgobj) {
++		if ((dbgobj->obj == obj) &&
++			((!chksn) || (dbgobj->obj_sn == sn))) {
++			printf("%s: (%s:%d) obj %p (sn %d state %d) was freed from %s(%d)\n",
++				__FUNCTION__, caller, line,
++				dbgobj->obj, dbgobj->obj_sn, dbgobj->obj_state,
++				dbgobj->caller, dbgobj->line);
++			goto EXIT;
++		}
++		else if (dbgobj->obj == NULL) {
++			break;
++		}
++		dbgobj = dbgobj->prior;
++		if (dbgobj == dbgobj_freetail)
++			break;
++	}
++
++	printf("%s: obj %p not found, check from %s(%d), chksn %s, sn %d\n",
++		__FUNCTION__, obj, caller, line, chksn ? "yes" : "no", sn);
++	dbgobj = dbgobj_objtail;
++	while (dbgobj) {
++		printf("%s: (%s:%d) obj %p sn %d was allocated from %s(%d)\n",
++				__FUNCTION__, caller, line,
++				dbgobj->obj, dbgobj->obj_sn, dbgobj->caller, dbgobj->line);
++		dbgobj = dbgobj->prior;
++		if (dbgobj == dbgobj_objtail)
++			break;
++	}
++
++EXIT:
++	BCM_OBJDBG_UNLOCK(&dbgobj_lock, flags);
++	return;
++}
++
++void
++bcm_object_feature_set(void *obj, uint32 type, uint32 value)
++{
++	struct bcm_dbgobj *dbgobj;
++	unsigned long flags;
++
++	BCM_REFERENCE(flags);
++	BCM_OBJDBG_LOCK(&dbgobj_lock, flags);
++
++	dbgobj = dbgobj_objtail;
++	while (dbgobj) {
++		if (dbgobj->obj == obj) {
++			if (type == BCM_OBJECT_FEATURE_FLAG) {
++				if (value & BCM_OBJECT_FEATURE_CLEAR)
++					dbgobj->flag &= ~(value);
++				else
++					dbgobj->flag |= (value);
++			} else if (type == BCM_OBJECT_FEATURE_PKT_STATE) {
++				dbgobj->obj_state = value;
++			}
++			if (dbgobj != dbgobj_objtail) {
++				bcm_object_movetoend(&dbgobj_objhead, &dbgobj_objtail,
++					dbgobj, BCM_OBJDBG_ADDTOTAIL);
++			}
++			goto EXIT;
++		}
++		dbgobj = dbgobj->prior;
++		if (dbgobj == dbgobj_objtail)
++			break;
++	}
++
++	printf("%s: obj %p not found in active list\n", __FUNCTION__, obj);
++	ASSERT(0);
++
++EXIT:
++	BCM_OBJDBG_UNLOCK(&dbgobj_lock, flags);
++	return;
++}
++
++int
++bcm_object_feature_get(void *obj, uint32 type, uint32 value)
++{
++	int rtn = 0;
++	struct bcm_dbgobj *dbgobj;
++	unsigned long flags;
++
++	BCM_REFERENCE(flags);
++	BCM_OBJDBG_LOCK(&dbgobj_lock, flags);
++
++	dbgobj = dbgobj_objtail;
++	while (dbgobj) {
++		if (dbgobj->obj == obj) {
++			if (type == BCM_OBJECT_FEATURE_FLAG) {
++				rtn = (dbgobj->flag & value) & (~BCM_OBJECT_FEATURE_CLEAR);
++			}
++			if (dbgobj != dbgobj_objtail) {
++				bcm_object_movetoend(&dbgobj_objhead, &dbgobj_objtail,
++					dbgobj, BCM_OBJDBG_ADDTOTAIL);
++			}
++			goto EXIT;
++		}
++		dbgobj = dbgobj->prior;
++		if (dbgobj == dbgobj_objtail)
++			break;
++	}
++
++	printf("%s: obj %p not found in active list\n", __FUNCTION__, obj);
++	ASSERT(0);
++
++EXIT:
++	BCM_OBJDBG_UNLOCK(&dbgobj_lock, flags);
++	return rtn;
++}
++
++#endif /* BCM_OBJECT_TRACE */
++
++uint8 *
++bcm_write_tlv(int type, const void *data, int datalen, uint8 *dst)
++{
++	uint8 *new_dst = dst;
++	bcm_tlv_t *dst_tlv = (bcm_tlv_t *)dst;
++
++	/* dst buffer should always be valid */
++	ASSERT(dst);
++
++	/* data len must be within valid range */
++	ASSERT((datalen >= 0) && (datalen <= BCM_TLV_MAX_DATA_SIZE));
++
++	/* source data buffer pointer should be valid, unless datalen is 0
++	 * meaning no data with this TLV
++	 */
++	ASSERT((data != NULL) || (datalen == 0));
++
++	/* only do work if the inputs are valid
++	 * - must have a dst to write to AND
++	 * - datalen must be within range AND
++	 * - the source data pointer must be non-NULL if datalen is non-zero
++	 * (this last condition detects datalen > 0 with a NULL data pointer)
++	 */
++	if ((dst != NULL) &&
++	    ((datalen >= 0) && (datalen <= BCM_TLV_MAX_DATA_SIZE)) &&
++	    ((data != NULL) || (datalen == 0))) {
++
++	        /* write type, len fields */
++		dst_tlv->id = (uint8)type;
++	        dst_tlv->len = (uint8)datalen;
++
++		/* if data is present, copy to the output buffer and update
++		 * pointer to output buffer
++		 */
++		if (datalen > 0) {
++
++			memcpy(dst_tlv->data, data, datalen);
++		}
++
++		/* update the output destination poitner to point past
++		 * the TLV written
++		 */
++		new_dst = dst + BCM_TLV_HDR_SIZE + datalen;
++	}
++
++	return (new_dst);
++}
++
++uint8 *
++bcm_write_tlv_safe(int type, const void *data, int datalen, uint8 *dst, int dst_maxlen)
++{
++	uint8 *new_dst = dst;
++
++	if ((datalen >= 0) && (datalen <= BCM_TLV_MAX_DATA_SIZE)) {
++
++		/* if len + tlv hdr len is more than destlen, don't do anything
++		 * just return the buffer untouched
++		 */
++		if ((int)(datalen + BCM_TLV_HDR_SIZE) <= dst_maxlen) {
++
++			new_dst = bcm_write_tlv(type, data, datalen, dst);
++		}
++	}
++
++	return (new_dst);
++}
++
++uint8 *
++bcm_copy_tlv(const void *src, uint8 *dst)
++{
++	uint8 *new_dst = dst;
++	const bcm_tlv_t *src_tlv = (const bcm_tlv_t *)src;
++	uint totlen;
++
++	ASSERT(dst && src);
++	if (dst && src) {
++
++		totlen = BCM_TLV_HDR_SIZE + src_tlv->len;
++		memcpy(dst, src_tlv, totlen);
++		new_dst = dst + totlen;
++	}
++
++	return (new_dst);
++}
++
++
++uint8 *bcm_copy_tlv_safe(const void *src, uint8 *dst, int dst_maxlen)
++{
++	uint8 *new_dst = dst;
++	const bcm_tlv_t *src_tlv = (const bcm_tlv_t *)src;
++
++	ASSERT(src);
++	if (src) {
++		if (bcm_valid_tlv(src_tlv, dst_maxlen)) {
++			new_dst = bcm_copy_tlv(src, dst);
++		}
++	}
++
++	return (new_dst);
++}
++
++
++#if !defined(BCMROMOFFLOAD_EXCLUDE_BCMUTILS_FUNCS)
++/*******************************************************************************
++ * crc8
++ *
++ * Computes a crc8 over the input data using the polynomial:
++ *
++ *       x^8 + x^7 +x^6 + x^4 + x^2 + 1
++ *
++ * The caller provides the initial value (either CRC8_INIT_VALUE
++ * or the previous returned value) to allow for processing of
++ * discontiguous blocks of data.  When generating the CRC the
++ * caller is responsible for complementing the final return value
++ * and inserting it into the byte stream.  When checking, a final
++ * return value of CRC8_GOOD_VALUE indicates a valid CRC.
++ *
++ * Reference: Dallas Semiconductor Application Note 27
++ *   Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
++ *     ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
++ *     ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
++ *
++ * ****************************************************************************
++ */
++
++static const uint8 crc8_table[256] = {
++    0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
++    0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
++    0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
++    0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
++    0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
++    0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
++    0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
++    0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
++    0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
++    0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
++    0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
++    0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
++    0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
++    0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
++    0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
++    0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
++    0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
++    0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
++    0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
++    0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
++    0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
++    0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
++    0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
++    0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
++    0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
++    0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
++    0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
++    0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
++    0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
++    0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
++    0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
++    0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
++};
++
++#define CRC_INNER_LOOP(n, c, x) \
++	(c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
++
++uint8
++hndcrc8(
++	uint8 *pdata,	/* pointer to array of data to process */
++	uint  nbytes,	/* number of input data bytes to process */
++	uint8 crc	/* either CRC8_INIT_VALUE or previous return value */
++)
++{
++	/* hard code the crc loop instead of using CRC_INNER_LOOP macro
++	 * to avoid the undefined and unnecessary (uint8 >> 8) operation.
++	 */
++	while (nbytes-- > 0)
++		crc = crc8_table[(crc ^ *pdata++) & 0xff];
++
++	return crc;
++}
++
++/*******************************************************************************
++ * crc16
++ *
++ * Computes a crc16 over the input data using the polynomial:
++ *
++ *       x^16 + x^12 +x^5 + 1
++ *
++ * The caller provides the initial value (either CRC16_INIT_VALUE
++ * or the previous returned value) to allow for processing of
++ * discontiguous blocks of data.  When generating the CRC the
++ * caller is responsible for complementing the final return value
++ * and inserting it into the byte stream.  When checking, a final
++ * return value of CRC16_GOOD_VALUE indicates a valid CRC.
++ *
++ * Reference: Dallas Semiconductor Application Note 27
++ *   Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
++ *     ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
++ *     ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
++ *
++ * ****************************************************************************
++ */
++
++static const uint16 crc16_table[256] = {
++    0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF,
++    0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7,
++    0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E,
++    0x9CC9, 0x8D40, 0xBFDB, 0xAE52, 0xDAED, 0xCB64, 0xF9FF, 0xE876,
++    0x2102, 0x308B, 0x0210, 0x1399, 0x6726, 0x76AF, 0x4434, 0x55BD,
++    0xAD4A, 0xBCC3, 0x8E58, 0x9FD1, 0xEB6E, 0xFAE7, 0xC87C, 0xD9F5,
++    0x3183, 0x200A, 0x1291, 0x0318, 0x77A7, 0x662E, 0x54B5, 0x453C,
++    0xBDCB, 0xAC42, 0x9ED9, 0x8F50, 0xFBEF, 0xEA66, 0xD8FD, 0xC974,
++    0x4204, 0x538D, 0x6116, 0x709F, 0x0420, 0x15A9, 0x2732, 0x36BB,
++    0xCE4C, 0xDFC5, 0xED5E, 0xFCD7, 0x8868, 0x99E1, 0xAB7A, 0xBAF3,
++    0x5285, 0x430C, 0x7197, 0x601E, 0x14A1, 0x0528, 0x37B3, 0x263A,
++    0xDECD, 0xCF44, 0xFDDF, 0xEC56, 0x98E9, 0x8960, 0xBBFB, 0xAA72,
++    0x6306, 0x728F, 0x4014, 0x519D, 0x2522, 0x34AB, 0x0630, 0x17B9,
++    0xEF4E, 0xFEC7, 0xCC5C, 0xDDD5, 0xA96A, 0xB8E3, 0x8A78, 0x9BF1,
++    0x7387, 0x620E, 0x5095, 0x411C, 0x35A3, 0x242A, 0x16B1, 0x0738,
++    0xFFCF, 0xEE46, 0xDCDD, 0xCD54, 0xB9EB, 0xA862, 0x9AF9, 0x8B70,
++    0x8408, 0x9581, 0xA71A, 0xB693, 0xC22C, 0xD3A5, 0xE13E, 0xF0B7,
++    0x0840, 0x19C9, 0x2B52, 0x3ADB, 0x4E64, 0x5FED, 0x6D76, 0x7CFF,
++    0x9489, 0x8500, 0xB79B, 0xA612, 0xD2AD, 0xC324, 0xF1BF, 0xE036,
++    0x18C1, 0x0948, 0x3BD3, 0x2A5A, 0x5EE5, 0x4F6C, 0x7DF7, 0x6C7E,
++    0xA50A, 0xB483, 0x8618, 0x9791, 0xE32E, 0xF2A7, 0xC03C, 0xD1B5,
++    0x2942, 0x38CB, 0x0A50, 0x1BD9, 0x6F66, 0x7EEF, 0x4C74, 0x5DFD,
++    0xB58B, 0xA402, 0x9699, 0x8710, 0xF3AF, 0xE226, 0xD0BD, 0xC134,
++    0x39C3, 0x284A, 0x1AD1, 0x0B58, 0x7FE7, 0x6E6E, 0x5CF5, 0x4D7C,
++    0xC60C, 0xD785, 0xE51E, 0xF497, 0x8028, 0x91A1, 0xA33A, 0xB2B3,
++    0x4A44, 0x5BCD, 0x6956, 0x78DF, 0x0C60, 0x1DE9, 0x2F72, 0x3EFB,
++    0xD68D, 0xC704, 0xF59F, 0xE416, 0x90A9, 0x8120, 0xB3BB, 0xA232,
++    0x5AC5, 0x4B4C, 0x79D7, 0x685E, 0x1CE1, 0x0D68, 0x3FF3, 0x2E7A,
++    0xE70E, 0xF687, 0xC41C, 0xD595, 0xA12A, 0xB0A3, 0x8238, 0x93B1,
++    0x6B46, 0x7ACF, 0x4854, 0x59DD, 0x2D62, 0x3CEB, 0x0E70, 0x1FF9,
++    0xF78F, 0xE606, 0xD49D, 0xC514, 0xB1AB, 0xA022, 0x92B9, 0x8330,
++    0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78
++};
++
++uint16
++hndcrc16(
++    uint8 *pdata,  /* pointer to array of data to process */
++    uint nbytes, /* number of input data bytes to process */
++    uint16 crc     /* either CRC16_INIT_VALUE or previous return value */
++)
++{
++	while (nbytes-- > 0)
++		CRC_INNER_LOOP(16, crc, *pdata++);
++	return crc;
++}
++
++static const uint32 crc32_table[256] = {
++    0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
++    0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
++    0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
++    0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
++    0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
++    0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
++    0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
++    0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
++    0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
++    0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
++    0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
++    0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
++    0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
++    0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
++    0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
++    0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
++    0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
++    0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
++    0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
++    0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
++    0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
++    0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
++    0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
++    0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
++    0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
++    0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
++    0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
++    0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
++    0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
++    0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
++    0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
++    0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
++    0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
++    0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
++    0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
++    0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
++    0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
++    0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
++    0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
++    0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
++    0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
++    0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
++    0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
++    0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
++    0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
++    0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
++    0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
++    0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
++    0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
++    0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
++    0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
++    0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
++    0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
++    0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
++    0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
++    0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
++    0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
++    0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
++    0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
++    0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
++    0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
++    0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
++    0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
++    0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
++};
++
++/*
++ * crc input is CRC32_INIT_VALUE for a fresh start, or previous return value if
++ * accumulating over multiple pieces.
++ */
++uint32
++hndcrc32(uint8 *pdata, uint nbytes, uint32 crc)
++{
++	uint8 *pend;
++	pend = pdata + nbytes;
++	while (pdata < pend)
++		CRC_INNER_LOOP(32, crc, *pdata++);
++
++	return crc;
++}
++
++#ifdef notdef
++#define CLEN 	1499 	/*  CRC Length */
++#define CBUFSIZ 	(CLEN+4)
++#define CNBUFS		5 /* # of bufs */
++
++void
++testcrc32(void)
++{
++	uint j, k, l;
++	uint8 *buf;
++	uint len[CNBUFS];
++	uint32 crcr;
++	uint32 crc32tv[CNBUFS] =
++		{0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110};
++
++	ASSERT((buf = MALLOC(CBUFSIZ*CNBUFS)) != NULL);
++
++	/* step through all possible alignments */
++	for (l = 0; l <= 4; l++) {
++		for (j = 0; j < CNBUFS; j++) {
++			len[j] = CLEN;
++			for (k = 0; k < len[j]; k++)
++				*(buf + j*CBUFSIZ + (k+l)) = (j+k) & 0xff;
++		}
++
++		for (j = 0; j < CNBUFS; j++) {
++			crcr = crc32(buf + j*CBUFSIZ + l, len[j], CRC32_INIT_VALUE);
++			ASSERT(crcr == crc32tv[j]);
++		}
++	}
++
++	MFREE(buf, CBUFSIZ*CNBUFS);
++	return;
++}
++#endif /* notdef */
++
++/*
++ * Advance from the current 1-byte tag/1-byte length/variable-length value
++ * triple, to the next, returning a pointer to the next.
++ * If the current or next TLV is invalid (does not fit in given buffer length),
++ * NULL is returned.
++ * *buflen is not modified if the TLV elt parameter is invalid, or is decremented
++ * by the TLV parameter's length if it is valid.
++ */
++bcm_tlv_t *
++bcm_next_tlv(bcm_tlv_t *elt, int *buflen)
++{
++	int len;
++
++	/* validate current elt */
++	if (!bcm_valid_tlv(elt, *buflen)) {
++		return NULL;
++	}
++
++	/* advance to next elt */
++	len = elt->len;
++	elt = (bcm_tlv_t*)(elt->data + len);
++	*buflen -= (TLV_HDR_LEN + len);
++
++	/* validate next elt */
++	if (!bcm_valid_tlv(elt, *buflen)) {
++		return NULL;
++	}
++
++	return elt;
++}
++
++/*
++ * Traverse a string of 1-byte tag/1-byte length/variable-length value
++ * triples, returning a pointer to the substring whose first element
++ * matches tag
++ */
++bcm_tlv_t *
++bcm_parse_tlvs(void *buf, int buflen, uint key)
++{
++	bcm_tlv_t *elt;
++	int totlen;
++
++	if ((elt = (bcm_tlv_t*)buf) == NULL) {
++		return NULL;
++	}
++	totlen = buflen;
++
++	/* find tagged parameter */
++	while (totlen >= TLV_HDR_LEN) {
++		int len = elt->len;
++
++		/* validate remaining totlen */
++		if ((elt->id == key) && (totlen >= (int)(len + TLV_HDR_LEN))) {
++
++			return (elt);
++		}
++
++		elt = (bcm_tlv_t*)((uint8*)elt + (len + TLV_HDR_LEN));
++		totlen -= (len + TLV_HDR_LEN);
++	}
++
++	return NULL;
++}
++
++bcm_tlv_t *
++bcm_parse_tlvs_dot11(void *buf, int buflen, uint key, bool id_ext)
++{
++	bcm_tlv_t *elt;
++	int totlen;
++
++	elt = (bcm_tlv_t*)buf;
++	totlen = buflen;
++
++	/* find tagged parameter */
++	while (totlen >= TLV_HDR_LEN) {
++		int len = elt->len;
++
++		do {
++			/* validate remaining totlen */
++			if (totlen <  (int)(len + TLV_HDR_LEN))
++				break;
++
++			if (id_ext) {
++				if (!DOT11_MNG_IE_ID_EXT_MATCH(elt, key))
++					break;
++			} else if (elt->id != key) {
++				break;
++			}
++
++			return (elt);
++		} while (0);
++
++		elt = (bcm_tlv_t*)((uint8*)elt + (len + TLV_HDR_LEN));
++		totlen -= (len + TLV_HDR_LEN);
++	}
++
++	return NULL;
++}
++
++/*
++ * Traverse a string of 1-byte tag/1-byte length/variable-length value
++ * triples, returning a pointer to the substring whose first element
++ * matches tag
++ * return NULL if not found or length field < min_varlen
++ */
++bcm_tlv_t *
++bcm_parse_tlvs_min_bodylen(void *buf, int buflen, uint key, int min_bodylen)
++{
++	bcm_tlv_t * ret;
++	ret = bcm_parse_tlvs(buf, buflen, key);
++	if (ret == NULL || ret->len < min_bodylen) {
++		return NULL;
++	}
++	return ret;
++}
++
++/*
++ * Traverse a string of 1-byte tag/1-byte length/variable-length value
++ * triples, returning a pointer to the substring whose first element
++ * matches tag.  Stop parsing when we see an element whose ID is greater
++ * than the target key.
++ */
++bcm_tlv_t *
++bcm_parse_ordered_tlvs(void *buf, int buflen, uint key)
++{
++	bcm_tlv_t *elt;
++	int totlen;
++
++	elt = (bcm_tlv_t*)buf;
++	totlen = buflen;
++
++	/* find tagged parameter */
++	while (totlen >= TLV_HDR_LEN) {
++		uint id = elt->id;
++		int len = elt->len;
++
++		/* Punt if we start seeing IDs > than target key */
++		if (id > key) {
++			return (NULL);
++		}
++
++		/* validate remaining totlen */
++		if ((id == key) && (totlen >= (int)(len + TLV_HDR_LEN))) {
++			return (elt);
++		}
++
++		elt = (bcm_tlv_t*)((uint8*)elt + (len + TLV_HDR_LEN));
++		totlen -= (len + TLV_HDR_LEN);
++	}
++	return NULL;
++}
++#endif	/* !BCMROMOFFLOAD_EXCLUDE_BCMUTILS_FUNCS */
++
++#if defined(WLMSG_PRHDRS) || defined(WLMSG_PRPKT) || defined(WLMSG_ASSOC) || \
++	defined(DHD_DEBUG)
++int
++bcm_format_field(const bcm_bit_desc_ex_t *bd, uint32 flags, char* buf, int len)
++{
++	int i, slen = 0;
++	uint32 bit, mask;
++	const char *name;
++	mask = bd->mask;
++	if (len < 2 || !buf)
++		return 0;
++
++	buf[0] = '\0';
++
++	for (i = 0;  (name = bd->bitfield[i].name) != NULL; i++) {
++		bit = bd->bitfield[i].bit;
++		if ((flags & mask) == bit) {
++			if (len > (int)strlen(name)) {
++				slen = strlen(name);
++				strncpy(buf, name, slen+1);
++			}
++			break;
++		}
++	}
++	return slen;
++}
++
++int
++bcm_format_flags(const bcm_bit_desc_t *bd, uint32 flags, char* buf, int len)
++{
++	int i;
++	char* p = buf;
++	char hexstr[16];
++	int slen = 0, nlen = 0;
++	uint32 bit;
++	const char* name;
++
++	if (len < 2 || !buf)
++		return 0;
++
++	buf[0] = '\0';
++
++	for (i = 0; flags != 0; i++) {
++		bit = bd[i].bit;
++		name = bd[i].name;
++		if (bit == 0 && flags != 0) {
++			/* print any unnamed bits */
++			snprintf(hexstr, 16, "0x%X", flags);
++			name = hexstr;
++			flags = 0;	/* exit loop */
++		} else if ((flags & bit) == 0)
++			continue;
++		flags &= ~bit;
++		nlen = strlen(name);
++		slen += nlen;
++		/* count btwn flag space */
++		if (flags != 0)
++			slen += 1;
++		/* need NULL char as well */
++		if (len <= slen)
++			break;
++		/* copy NULL char but don't count it */
++		strncpy(p, name, nlen + 1);
++		p += nlen;
++		/* copy btwn flag space and NULL char */
++		if (flags != 0)
++			p += snprintf(p, 2, " ");
++	}
++
++	/* indicate the str was too short */
++	if (flags != 0) {
++		p += snprintf(p, 2, ">");
++	}
++
++	return (int)(p - buf);
++}
++#endif 
++
++/* print bytes formatted as hex to a string. return the resulting string length */
++int
++bcm_format_hex(char *str, const void *bytes, int len)
++{
++	int i;
++	char *p = str;
++	const uint8 *src = (const uint8*)bytes;
++
++	for (i = 0; i < len; i++) {
++		p += snprintf(p, 3, "%02X", *src);
++		src++;
++	}
++	return (int)(p - str);
++}
++
++/* pretty hex print a contiguous buffer */
++void
++prhex(const char *msg, volatile uchar *buf, uint nbytes)
++{
++	char line[128], *p;
++	int len = sizeof(line);
++	int nchar;
++	uint i;
++
++	if (msg && (msg[0] != '\0'))
++		printf("%s:\n", msg);
++
++	p = line;
++	for (i = 0; i < nbytes; i++) {
++		if (i % 16 == 0) {
++			nchar = snprintf(p, len, "  %04x: ", i);	/* line prefix */
++			p += nchar;
++			len -= nchar;
++		}
++		if (len > 0) {
++			nchar = snprintf(p, len, "%02x ", buf[i]);
++			p += nchar;
++			len -= nchar;
++		}
++
++		if (i % 16 == 15) {
++			printf("%s\n", line);		/* flush line */
++			p = line;
++			len = sizeof(line);
++		}
++	}
++
++	/* flush last partial line */
++	if (p != line)
++		printf("%s\n", line);
++}
++
++static const char *crypto_algo_names[] = {
++	"NONE",
++	"WEP1",
++	"TKIP",
++	"WEP128",
++	"AES_CCM",
++	"AES_OCB_MSDU",
++	"AES_OCB_MPDU",
++	"NALG",
++	"UNDEF",
++	"UNDEF",
++	"UNDEF",
++	"UNDEF"
++	"PMK",
++	"BIP",
++	"AES_GCM",
++	"AES_CCM256",
++	"AES_GCM256",
++	"BIP_CMAC256",
++	"BIP_GMAC",
++	"BIP_GMAC256",
++	"UNDEF"
++};
++
++const char *
++bcm_crypto_algo_name(uint algo)
++{
++	return (algo < ARRAYSIZE(crypto_algo_names)) ? crypto_algo_names[algo] : "ERR";
++}
++
++
++char *
++bcm_chipname(uint chipid, char *buf, uint len)
++{
++	const char *fmt;
++
++	fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
++	snprintf(buf, len, fmt, chipid);
++	return buf;
++}
++
++/* Produce a human-readable string for boardrev */
++char *
++bcm_brev_str(uint32 brev, char *buf)
++{
++	if (brev < 0x100)
++		snprintf(buf, 8, "%d.%d", (brev & 0xf0) >> 4, brev & 0xf);
++	else
++		snprintf(buf, 8, "%c%03x", ((brev & 0xf000) == 0x1000) ? 'P' : 'A', brev & 0xfff);
++
++	return (buf);
++}
++
++#define BUFSIZE_TODUMP_ATONCE 512 /* Buffer size */
++
++/* dump large strings to console */
++void
++printbig(char *buf)
++{
++	uint len, max_len;
++	char c;
++
++	len = (uint)strlen(buf);
++
++	max_len = BUFSIZE_TODUMP_ATONCE;
++
++	while (len > max_len) {
++		c = buf[max_len];
++		buf[max_len] = '\0';
++		printf("%s", buf);
++		buf[max_len] = c;
++
++		buf += max_len;
++		len -= max_len;
++	}
++	/* print the remaining string */
++	printf("%s\n", buf);
++	return;
++}
++
++/* routine to dump fields in a fileddesc structure */
++uint
++bcmdumpfields(bcmutl_rdreg_rtn read_rtn, void *arg0, uint arg1, struct fielddesc *fielddesc_array,
++	char *buf, uint32 bufsize)
++{
++	uint  filled_len;
++	int len;
++	struct fielddesc *cur_ptr;
++
++	filled_len = 0;
++	cur_ptr = fielddesc_array;
++
++	while (bufsize > 1) {
++		if (cur_ptr->nameandfmt == NULL)
++			break;
++		len = snprintf(buf, bufsize, cur_ptr->nameandfmt,
++		               read_rtn(arg0, arg1, cur_ptr->offset));
++		/* check for snprintf overflow or error */
++		if (len < 0 || (uint32)len >= bufsize)
++			len = bufsize - 1;
++		buf += len;
++		bufsize -= len;
++		filled_len += len;
++		cur_ptr++;
++	}
++	return filled_len;
++}
++
++uint
++bcm_mkiovar(const char *name, const char *data, uint datalen, char *buf, uint buflen)
++{
++	uint len;
++
++	len = (uint)strlen(name) + 1;
++
++	if ((len + datalen) > buflen)
++		return 0;
++
++	strncpy(buf, name, buflen);
++
++	/* append data onto the end of the name string */
++	if (data && datalen != 0) {
++		memcpy(&buf[len], data, datalen);
++		len += datalen;
++	}
++
++	return len;
++}
++
++/* Quarter dBm units to mW
++ * Table starts at QDBM_OFFSET, so the first entry is mW for qdBm=153
++ * Table is offset so the last entry is largest mW value that fits in
++ * a uint16.
++ */
++
++#define QDBM_OFFSET 153		/* Offset for first entry */
++#define QDBM_TABLE_LEN 40	/* Table size */
++
++/* Smallest mW value that will round up to the first table entry, QDBM_OFFSET.
++ * Value is ( mW(QDBM_OFFSET - 1) + mW(QDBM_OFFSET) ) / 2
++ */
++#define QDBM_TABLE_LOW_BOUND 6493 /* Low bound */
++
++/* Largest mW value that will round down to the last table entry,
++ * QDBM_OFFSET + QDBM_TABLE_LEN-1.
++ * Value is ( mW(QDBM_OFFSET + QDBM_TABLE_LEN - 1) + mW(QDBM_OFFSET + QDBM_TABLE_LEN) ) / 2.
++ */
++#define QDBM_TABLE_HIGH_BOUND 64938 /* High bound */
++
++static const uint16 nqdBm_to_mW_map[QDBM_TABLE_LEN] = {
++/* qdBm: 	+0 	+1 	+2 	+3 	+4 	+5 	+6 	+7 */
++/* 153: */      6683,	7079,	7499,	7943,	8414,	8913,	9441,	10000,
++/* 161: */      10593,	11220,	11885,	12589,	13335,	14125,	14962,	15849,
++/* 169: */      16788,	17783,	18836,	19953,	21135,	22387,	23714,	25119,
++/* 177: */      26607,	28184,	29854,	31623,	33497,	35481,	37584,	39811,
++/* 185: */      42170,	44668,	47315,	50119,	53088,	56234,	59566,	63096
++};
++
++uint16
++bcm_qdbm_to_mw(uint8 qdbm)
++{
++	uint factor = 1;
++	int idx = qdbm - QDBM_OFFSET;
++
++	if (idx >= QDBM_TABLE_LEN) {
++		/* clamp to max uint16 mW value */
++		return 0xFFFF;
++	}
++
++	/* scale the qdBm index up to the range of the table 0-40
++	 * where an offset of 40 qdBm equals a factor of 10 mW.
++	 */
++	while (idx < 0) {
++		idx += 40;
++		factor *= 10;
++	}
++
++	/* return the mW value scaled down to the correct factor of 10,
++	 * adding in factor/2 to get proper rounding.
++	 */
++	return ((nqdBm_to_mW_map[idx] + factor/2) / factor);
++}
++
++uint8
++bcm_mw_to_qdbm(uint16 mw)
++{
++	uint8 qdbm;
++	int offset;
++	uint mw_uint = mw;
++	uint boundary;
++
++	/* handle boundary case */
++	if (mw_uint <= 1)
++		return 0;
++
++	offset = QDBM_OFFSET;
++
++	/* move mw into the range of the table */
++	while (mw_uint < QDBM_TABLE_LOW_BOUND) {
++		mw_uint *= 10;
++		offset -= 40;
++	}
++
++	for (qdbm = 0; qdbm < QDBM_TABLE_LEN-1; qdbm++) {
++		boundary = nqdBm_to_mW_map[qdbm] + (nqdBm_to_mW_map[qdbm+1] -
++		                                    nqdBm_to_mW_map[qdbm])/2;
++		if (mw_uint < boundary) break;
++	}
++
++	qdbm += (uint8)offset;
++
++	return (qdbm);
++}
++
++
++uint
++bcm_bitcount(uint8 *bitmap, uint length)
++{
++	uint bitcount = 0, i;
++	uint8 tmp;
++	for (i = 0; i < length; i++) {
++		tmp = bitmap[i];
++		while (tmp) {
++			bitcount++;
++			tmp &= (tmp - 1);
++		}
++	}
++	return bitcount;
++}
++
++#if defined(BCMDRIVER) || defined(WL_UNITTEST)
++
++/* triggers bcm_bprintf to print to kernel log */
++bool bcm_bprintf_bypass = FALSE;
++
++/* Initialization of bcmstrbuf structure */
++void
++bcm_binit(struct bcmstrbuf *b, char *buf, uint size)
++{
++	b->origsize = b->size = size;
++	b->origbuf = b->buf = buf;
++}
++
++/* Buffer sprintf wrapper to guard against buffer overflow */
++int
++bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...)
++{
++	va_list ap;
++	int r;
++
++	va_start(ap, fmt);
++
++	r = vsnprintf(b->buf, b->size, fmt, ap);
++	if (bcm_bprintf_bypass == TRUE) {
++		printf("%s", b->buf);
++		goto exit;
++	}
++
++	/* Non Ansi C99 compliant returns -1,
++	 * Ansi compliant return r >= b->size,
++	 * bcmstdlib returns 0, handle all
++	 */
++	/* r == 0 is also the case when strlen(fmt) is zero.
++	 * typically the case when "" is passed as argument.
++	 */
++	if ((r == -1) || (r >= (int)b->size)) {
++		b->size = 0;
++	} else {
++		b->size -= r;
++		b->buf += r;
++	}
++
++exit:
++	va_end(ap);
++
++	return r;
++}
++
++void
++bcm_bprhex(struct bcmstrbuf *b, const char *msg, bool newline, const uint8 *buf, int len)
++{
++	int i;
++
++	if (msg != NULL && msg[0] != '\0')
++		bcm_bprintf(b, "%s", msg);
++	for (i = 0; i < len; i ++)
++		bcm_bprintf(b, "%02X", buf[i]);
++	if (newline)
++		bcm_bprintf(b, "\n");
++}
++
++void
++bcm_inc_bytes(uchar *num, int num_bytes, uint8 amount)
++{
++	int i;
++
++	for (i = 0; i < num_bytes; i++) {
++		num[i] += amount;
++		if (num[i] >= amount)
++			break;
++		amount = 1;
++	}
++}
++
++int
++bcm_cmp_bytes(const uchar *arg1, const uchar *arg2, uint8 nbytes)
++{
++	int i;
++
++	for (i = nbytes - 1; i >= 0; i--) {
++		if (arg1[i] != arg2[i])
++			return (arg1[i] - arg2[i]);
++	}
++	return 0;
++}
++
++void
++bcm_print_bytes(const char *name, const uchar *data, int len)
++{
++	int i;
++	int per_line = 0;
++
++	printf("%s: %d \n", name ? name : "", len);
++	for (i = 0; i < len; i++) {
++		printf("%02x ", *data++);
++		per_line++;
++		if (per_line == 16) {
++			per_line = 0;
++			printf("\n");
++		}
++	}
++	printf("\n");
++}
++
++/* Look for vendor-specific IE with specified OUI and optional type */
++bcm_tlv_t *
++bcm_find_vendor_ie(void *tlvs, int tlvs_len, const char *voui, uint8 *type, int type_len)
++{
++	bcm_tlv_t *ie;
++	uint8 ie_len;
++
++	ie = (bcm_tlv_t*)tlvs;
++
++	/* make sure we are looking at a valid IE */
++	if (ie == NULL || !bcm_valid_tlv(ie, tlvs_len)) {
++		return NULL;
++	}
++
++	/* Walk through the IEs looking for an OUI match */
++	do {
++		ie_len = ie->len;
++		if ((ie->id == DOT11_MNG_PROPR_ID) &&
++		    (ie_len >= (DOT11_OUI_LEN + type_len)) &&
++		    !bcmp(ie->data, voui, DOT11_OUI_LEN))
++		{
++			/* compare optional type */
++			if (type_len == 0 ||
++			    !bcmp(&ie->data[DOT11_OUI_LEN], type, type_len)) {
++				return (ie);		/* a match */
++			}
++		}
++	} while ((ie = bcm_next_tlv(ie, &tlvs_len)) != NULL);
++
++	return NULL;
++}
++
++#if defined(WLTINYDUMP) || defined(WLMSG_INFORM) || defined(WLMSG_ASSOC) || \
++	defined(WLMSG_PRPKT) || defined(WLMSG_WSEC)
++#define SSID_FMT_BUF_LEN	((4 * DOT11_MAX_SSID_LEN) + 1)
++
++int
++bcm_format_ssid(char* buf, const uchar ssid[], uint ssid_len)
++{
++	uint i, c;
++	char *p = buf;
++	char *endp = buf + SSID_FMT_BUF_LEN;
++
++	if (ssid_len > DOT11_MAX_SSID_LEN) ssid_len = DOT11_MAX_SSID_LEN;
++
++	for (i = 0; i < ssid_len; i++) {
++		c = (uint)ssid[i];
++		if (c == '\\') {
++			*p++ = '\\';
++			*p++ = '\\';
++		} else if (bcm_isprint((uchar)c)) {
++			*p++ = (char)c;
++		} else {
++			p += snprintf(p, (endp - p), "\\x%02X", c);
++		}
++	}
++	*p = '\0';
++	ASSERT(p < endp);
++
++	return (int)(p - buf);
++}
++#endif 
++
++#endif /* BCMDRIVER || WL_UNITTEST */
++
++/*
++ * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file and ending in a NUL.
++ * also accepts nvram files which are already in the format of <var1>=<value>\0\<var2>=<value2>\0
++ * Removes carriage returns, empty lines, comment lines, and converts newlines to NULs.
++ * Shortens buffer as needed and pads with NULs.  End of buffer is marked by two NULs.
++*/
++
++unsigned int
++process_nvram_vars(char *varbuf, unsigned int len)
++{
++	char *dp;
++	bool findNewline;
++	int column;
++	unsigned int buf_len, n;
++	unsigned int pad = 0;
++	char nv_ver[128];
++
++	dp = varbuf;
++
++	findNewline = FALSE;
++	column = 0;
++
++	// terence 20130914: print out NVRAM version
++	if (varbuf[0] == '#') {
++		memset(nv_ver, 0x00, sizeof(nv_ver));
++		for (n=1; n<len && n<(sizeof(nv_ver)-1); n++) {
++			if (varbuf[n] == '\n')
++				break;
++			nv_ver[n-1] = varbuf[n];
++		}
++		printf("NVRAM version: %s\n", nv_ver);
++	}
++
++	for (n = 0; n < len; n++) {
++		if (varbuf[n] == '\r')
++			continue;
++		if (findNewline && varbuf[n] != '\n')
++			continue;
++		findNewline = FALSE;
++		if (varbuf[n] == '#') {
++			findNewline = TRUE;
++			continue;
++		}
++		if (varbuf[n] == '\n') {
++			if (column == 0)
++				continue;
++			*dp++ = 0;
++			column = 0;
++			continue;
++		}
++		*dp++ = varbuf[n];
++		column++;
++	}
++	buf_len = (unsigned int)(dp - varbuf);
++	if (buf_len % 4) {
++		pad = 4 - buf_len % 4;
++		if (pad && (buf_len + pad <= len)) {
++			buf_len += pad;
++		}
++	}
++
++	while (dp < varbuf + n)
++		*dp++ = 0;
++
++	return buf_len;
++}
++
++/* calculate a * b + c */
++void
++bcm_uint64_multiple_add(uint32* r_high, uint32* r_low, uint32 a, uint32 b, uint32 c)
++{
++#define FORMALIZE(var) {cc += (var & 0x80000000) ? 1 : 0; var &= 0x7fffffff;}
++	uint32 r1, r0;
++	uint32 a1, a0, b1, b0, t, cc = 0;
++
++	a1 = a >> 16;
++	a0 = a & 0xffff;
++	b1 = b >> 16;
++	b0 = b & 0xffff;
++
++	r0 = a0 * b0;
++	FORMALIZE(r0);
++
++	t = (a1 * b0) << 16;
++	FORMALIZE(t);
++
++	r0 += t;
++	FORMALIZE(r0);
++
++	t = (a0 * b1) << 16;
++	FORMALIZE(t);
++
++	r0 += t;
++	FORMALIZE(r0);
++
++	FORMALIZE(c);
++
++	r0 += c;
++	FORMALIZE(r0);
++
++	r0 |= (cc % 2) ? 0x80000000 : 0;
++	r1 = a1 * b1 + ((a1 * b0) >> 16) + ((b1 * a0) >> 16) + (cc / 2);
++
++	*r_high = r1;
++	*r_low = r0;
++}
++
++/* calculate a / b */
++void
++bcm_uint64_divide(uint32* r, uint32 a_high, uint32 a_low, uint32 b)
++{
++	uint32 a1 = a_high, a0 = a_low, r0 = 0;
++
++	if (b < 2)
++		return;
++
++	while (a1 != 0) {
++		r0 += (0xffffffff / b) * a1;
++		bcm_uint64_multiple_add(&a1, &a0, ((0xffffffff % b) + 1) % b, a1, a0);
++	}
++
++	r0 += a0 / b;
++	*r = r0;
++}
++
++#ifndef setbit /* As in the header file */
++#ifdef BCMUTILS_BIT_MACROS_USE_FUNCS
++/* Set bit in byte array. */
++void
++setbit(void *array, uint bit)
++{
++	((uint8 *)array)[bit / NBBY] |= 1 << (bit % NBBY);
++}
++
++/* Clear bit in byte array. */
++void
++clrbit(void *array, uint bit)
++{
++	((uint8 *)array)[bit / NBBY] &= ~(1 << (bit % NBBY));
++}
++
++/* Test if bit is set in byte array. */
++bool
++isset(const void *array, uint bit)
++{
++	return (((const uint8 *)array)[bit / NBBY] & (1 << (bit % NBBY)));
++}
++
++/* Test if bit is clear in byte array. */
++bool
++isclr(const void *array, uint bit)
++{
++	return ((((const uint8 *)array)[bit / NBBY] & (1 << (bit % NBBY))) == 0);
++}
++#endif /* BCMUTILS_BIT_MACROS_USE_FUNCS */
++#endif /* setbit */
++
++void
++set_bitrange(void *array, uint start, uint end, uint maxbit)
++{
++	uint startbyte = start/NBBY;
++	uint endbyte = end/NBBY;
++	uint i, startbytelastbit, endbytestartbit;
++
++	if (end >= start) {
++		if (endbyte - startbyte > 1)
++		{
++			startbytelastbit = (startbyte+1)*NBBY - 1;
++			endbytestartbit = endbyte*NBBY;
++			for (i = startbyte+1; i < endbyte; i++)
++				((uint8 *)array)[i] = 0xFF;
++			for (i = start; i <= startbytelastbit; i++)
++				setbit(array, i);
++			for (i = endbytestartbit; i <= end; i++)
++				setbit(array, i);
++		} else {
++			for (i = start; i <= end; i++)
++				setbit(array, i);
++		}
++	}
++	else {
++		set_bitrange(array, start, maxbit, maxbit);
++		set_bitrange(array, 0, end, maxbit);
++	}
++}
++
++void
++bcm_bitprint32(const uint32 u32arg)
++{
++	int i;
++	for (i = NBITS(uint32) - 1; i >= 0; i--) {
++		if (isbitset(u32arg, i)) {
++			printf("1");
++		} else {
++			printf("0");
++		}
++
++		if ((i % NBBY) == 0) printf(" ");
++	}
++	printf("\n");
++}
++
++/* calculate checksum for ip header, tcp / udp header / data */
++uint16
++bcm_ip_cksum(uint8 *buf, uint32 len, uint32 sum)
++{
++	while (len > 1) {
++		sum += (buf[0] << 8) | buf[1];
++		buf += 2;
++		len -= 2;
++	}
++
++	if (len > 0) {
++		sum += (*buf) << 8;
++	}
++
++	while (sum >> 16) {
++		sum = (sum & 0xffff) + (sum >> 16);
++	}
++
++	return ((uint16)~sum);
++}
++#if defined(BCMDRIVER) && !defined(_CFEZ_)
++/*
++ * Hierarchical Multiword bitmap based small id allocator.
++ *
++ * Multilevel hierarchy bitmap. (maximum 2 levels)
++ * First hierarchy uses a multiword bitmap to identify 32bit words in the
++ * second hierarchy that have at least a single bit set. Each bit in a word of
++ * the second hierarchy represents a unique ID that may be allocated.
++ *
++ * BCM_MWBMAP_ITEMS_MAX: Maximum number of IDs managed.
++ * BCM_MWBMAP_BITS_WORD: Number of bits in a bitmap word word
++ * BCM_MWBMAP_WORDS_MAX: Maximum number of bitmap words needed for free IDs.
++ * BCM_MWBMAP_WDMAP_MAX: Maximum number of bitmap wordss identifying first non
++ *                       non-zero bitmap word carrying at least one free ID.
++ * BCM_MWBMAP_SHIFT_OP:  Used in MOD, DIV and MUL operations.
++ * BCM_MWBMAP_INVALID_IDX: Value ~0U is treated as an invalid ID
++ *
++ * Design Notes:
++ * BCM_MWBMAP_USE_CNTSETBITS trades CPU for memory. A runtime count of how many
++ * bits are computed each time on allocation and deallocation, requiring 4
++ * array indexed access and 3 arithmetic operations. When not defined, a runtime
++ * count of set bits state is maintained. Upto 32 Bytes per 1024 IDs is needed.
++ * In a 4K max ID allocator, up to 128Bytes are hence used per instantiation.
++ * In a memory limited system e.g. dongle builds, a CPU for memory tradeoff may
++ * be used by defining BCM_MWBMAP_USE_CNTSETBITS.
++ *
++ * Note: wd_bitmap[] is statically declared and is not ROM friendly ... array
++ * size is fixed. No intention to support larger than 4K indice allocation. ID
++ * allocators for ranges smaller than 4K will have a wastage of only 12Bytes
++ * with savings in not having to use an indirect access, had it been dynamically
++ * allocated.
++ */
++#define BCM_MWBMAP_ITEMS_MAX    (64 * 1024)  /* May increase to 64K */
++
++#define BCM_MWBMAP_BITS_WORD    (NBITS(uint32))
++#define BCM_MWBMAP_WORDS_MAX    (BCM_MWBMAP_ITEMS_MAX / BCM_MWBMAP_BITS_WORD)
++#define BCM_MWBMAP_WDMAP_MAX    (BCM_MWBMAP_WORDS_MAX / BCM_MWBMAP_BITS_WORD)
++#define BCM_MWBMAP_SHIFT_OP     (5)
++#define BCM_MWBMAP_MODOP(ix)    ((ix) & (BCM_MWBMAP_BITS_WORD - 1))
++#define BCM_MWBMAP_DIVOP(ix)    ((ix) >> BCM_MWBMAP_SHIFT_OP)
++#define BCM_MWBMAP_MULOP(ix)    ((ix) << BCM_MWBMAP_SHIFT_OP)
++
++/* Redefine PTR() and/or HDL() conversion to invoke audit for debugging */
++#define BCM_MWBMAP_PTR(hdl)		((struct bcm_mwbmap *)(hdl))
++#define BCM_MWBMAP_HDL(ptr)		((void *)(ptr))
++
++#if defined(BCM_MWBMAP_DEBUG)
++#define BCM_MWBMAP_AUDIT(mwb) \
++	do { \
++		ASSERT((mwb != NULL) && \
++		       (((struct bcm_mwbmap *)(mwb))->magic == (void *)(mwb))); \
++		bcm_mwbmap_audit(mwb); \
++	} while (0)
++#define MWBMAP_ASSERT(exp)		ASSERT(exp)
++#define MWBMAP_DBG(x)           printf x
++#else   /* !BCM_MWBMAP_DEBUG */
++#define BCM_MWBMAP_AUDIT(mwb)   do {} while (0)
++#define MWBMAP_ASSERT(exp)		do {} while (0)
++#define MWBMAP_DBG(x)
++#endif  /* !BCM_MWBMAP_DEBUG */
++
++
++typedef struct bcm_mwbmap {     /* Hierarchical multiword bitmap allocator    */
++	uint16 wmaps;               /* Total number of words in free wd bitmap    */
++	uint16 imaps;               /* Total number of words in free id bitmap    */
++	int32  ifree;               /* Count of free indices. Used only in audits */
++	uint16 total;               /* Total indices managed by multiword bitmap  */
++
++	void * magic;               /* Audit handle parameter from user           */
++
++	uint32 wd_bitmap[BCM_MWBMAP_WDMAP_MAX]; /* 1st level bitmap of            */
++#if !defined(BCM_MWBMAP_USE_CNTSETBITS)
++	int8   wd_count[BCM_MWBMAP_WORDS_MAX];  /* free id running count, 1st lvl */
++#endif /*  ! BCM_MWBMAP_USE_CNTSETBITS */
++
++	uint32 id_bitmap[0];        /* Second level bitmap                        */
++} bcm_mwbmap_t;
++
++/* Incarnate a hierarchical multiword bitmap based small index allocator. */
++struct bcm_mwbmap *
++bcm_mwbmap_init(osl_t *osh, uint32 items_max)
++{
++	struct bcm_mwbmap * mwbmap_p;
++	uint32 wordix, size, words, extra;
++
++	/* Implementation Constraint: Uses 32bit word bitmap */
++	MWBMAP_ASSERT(BCM_MWBMAP_BITS_WORD == 32U);
++	MWBMAP_ASSERT(BCM_MWBMAP_SHIFT_OP == 5U);
++	MWBMAP_ASSERT(ISPOWEROF2(BCM_MWBMAP_ITEMS_MAX));
++	MWBMAP_ASSERT((BCM_MWBMAP_ITEMS_MAX % BCM_MWBMAP_BITS_WORD) == 0U);
++
++	ASSERT(items_max <= BCM_MWBMAP_ITEMS_MAX);
++
++	/* Determine the number of words needed in the multiword bitmap */
++	extra = BCM_MWBMAP_MODOP(items_max);
++	words = BCM_MWBMAP_DIVOP(items_max) + ((extra != 0U) ? 1U : 0U);
++
++	/* Allocate runtime state of multiword bitmap */
++	/* Note: wd_count[] or wd_bitmap[] are not dynamically allocated */
++	size = sizeof(bcm_mwbmap_t) + (sizeof(uint32) * words);
++	mwbmap_p = (bcm_mwbmap_t *)MALLOC(osh, size);
++	if (mwbmap_p == (bcm_mwbmap_t *)NULL) {
++		ASSERT(0);
++		goto error1;
++	}
++	memset(mwbmap_p, 0, size);
++
++	/* Initialize runtime multiword bitmap state */
++	mwbmap_p->imaps = (uint16)words;
++	mwbmap_p->ifree = (int32)items_max;
++	mwbmap_p->total = (uint16)items_max;
++
++	/* Setup magic, for use in audit of handle */
++	mwbmap_p->magic = BCM_MWBMAP_HDL(mwbmap_p);
++
++	/* Setup the second level bitmap of free indices */
++	/* Mark all indices as available */
++	for (wordix = 0U; wordix < mwbmap_p->imaps; wordix++) {
++		mwbmap_p->id_bitmap[wordix] = (uint32)(~0U);
++#if !defined(BCM_MWBMAP_USE_CNTSETBITS)
++		mwbmap_p->wd_count[wordix] = BCM_MWBMAP_BITS_WORD;
++#endif /*  ! BCM_MWBMAP_USE_CNTSETBITS */
++	}
++
++	/* Ensure that extra indices are tagged as un-available */
++	if (extra) { /* fixup the free ids in last bitmap and wd_count */
++		uint32 * bmap_p = &mwbmap_p->id_bitmap[mwbmap_p->imaps - 1];
++		*bmap_p ^= (uint32)(~0U << extra); /* fixup bitmap */
++#if !defined(BCM_MWBMAP_USE_CNTSETBITS)
++		mwbmap_p->wd_count[mwbmap_p->imaps - 1] = (int8)extra; /* fixup count */
++#endif /*  ! BCM_MWBMAP_USE_CNTSETBITS */
++	}
++
++	/* Setup the first level bitmap hierarchy */
++	extra = BCM_MWBMAP_MODOP(mwbmap_p->imaps);
++	words = BCM_MWBMAP_DIVOP(mwbmap_p->imaps) + ((extra != 0U) ? 1U : 0U);
++
++	mwbmap_p->wmaps = (uint16)words;
++
++	for (wordix = 0U; wordix < mwbmap_p->wmaps; wordix++)
++		mwbmap_p->wd_bitmap[wordix] = (uint32)(~0U);
++	if (extra) {
++		uint32 * bmap_p = &mwbmap_p->wd_bitmap[mwbmap_p->wmaps - 1];
++		*bmap_p ^= (uint32)(~0U << extra); /* fixup bitmap */
++	}
++
++	return mwbmap_p;
++
++error1:
++	return BCM_MWBMAP_INVALID_HDL;
++}
++
++/* Release resources used by multiword bitmap based small index allocator. */
++void
++bcm_mwbmap_fini(osl_t * osh, struct bcm_mwbmap * mwbmap_hdl)
++{
++	bcm_mwbmap_t * mwbmap_p;
++
++	BCM_MWBMAP_AUDIT(mwbmap_hdl);
++	mwbmap_p = BCM_MWBMAP_PTR(mwbmap_hdl);
++
++	MFREE(osh, mwbmap_p, sizeof(struct bcm_mwbmap)
++	                     + (sizeof(uint32) * mwbmap_p->imaps));
++	return;
++}
++
++/* Allocate a unique small index using a multiword bitmap index allocator.    */
++uint32 BCMFASTPATH
++bcm_mwbmap_alloc(struct bcm_mwbmap * mwbmap_hdl)
++{
++	bcm_mwbmap_t * mwbmap_p;
++	uint32 wordix, bitmap;
++
++	BCM_MWBMAP_AUDIT(mwbmap_hdl);
++	mwbmap_p = BCM_MWBMAP_PTR(mwbmap_hdl);
++
++	/* Start with the first hierarchy */
++	for (wordix = 0; wordix < mwbmap_p->wmaps; ++wordix) {
++
++		bitmap = mwbmap_p->wd_bitmap[wordix]; /* get the word bitmap */
++
++		if (bitmap != 0U) {
++
++			uint32 count, bitix, *bitmap_p;
++
++			bitmap_p = &mwbmap_p->wd_bitmap[wordix];
++
++			/* clear all except trailing 1 */
++			bitmap   = (uint32)(((int)(bitmap)) & (-((int)(bitmap))));
++			MWBMAP_ASSERT(C_bcm_count_leading_zeros(bitmap) ==
++			              bcm_count_leading_zeros(bitmap));
++			bitix    = (BCM_MWBMAP_BITS_WORD - 1)
++			         - bcm_count_leading_zeros(bitmap); /* use asm clz */
++			wordix   = BCM_MWBMAP_MULOP(wordix) + bitix;
++
++			/* Clear bit if wd count is 0, without conditional branch */
++#if defined(BCM_MWBMAP_USE_CNTSETBITS)
++			count = bcm_cntsetbits(mwbmap_p->id_bitmap[wordix]) - 1;
++#else  /* ! BCM_MWBMAP_USE_CNTSETBITS */
++			mwbmap_p->wd_count[wordix]--;
++			count = mwbmap_p->wd_count[wordix];
++			MWBMAP_ASSERT(count ==
++			              (bcm_cntsetbits(mwbmap_p->id_bitmap[wordix]) - 1));
++#endif /* ! BCM_MWBMAP_USE_CNTSETBITS */
++			MWBMAP_ASSERT(count >= 0);
++
++			/* clear wd_bitmap bit if id_map count is 0 */
++			bitmap = (count == 0) << bitix;
++
++			MWBMAP_DBG((
++			    "Lvl1: bitix<%02u> wordix<%02u>: %08x ^ %08x = %08x wfree %d",
++			    bitix, wordix, *bitmap_p, bitmap, (*bitmap_p) ^ bitmap, count));
++
++			*bitmap_p ^= bitmap;
++
++			/* Use bitix in the second hierarchy */
++			bitmap_p = &mwbmap_p->id_bitmap[wordix];
++
++			bitmap = mwbmap_p->id_bitmap[wordix]; /* get the id bitmap */
++			MWBMAP_ASSERT(bitmap != 0U);
++
++			/* clear all except trailing 1 */
++			bitmap   = (uint32)(((int)(bitmap)) & (-((int)(bitmap))));
++			MWBMAP_ASSERT(C_bcm_count_leading_zeros(bitmap) ==
++			              bcm_count_leading_zeros(bitmap));
++			bitix    = BCM_MWBMAP_MULOP(wordix)
++			         + (BCM_MWBMAP_BITS_WORD - 1)
++			         - bcm_count_leading_zeros(bitmap); /* use asm clz */
++
++			mwbmap_p->ifree--; /* decrement system wide free count */
++			MWBMAP_ASSERT(mwbmap_p->ifree >= 0);
++
++			MWBMAP_DBG((
++			    "Lvl2: bitix<%02u> wordix<%02u>: %08x ^ %08x = %08x ifree %d",
++			    bitix, wordix, *bitmap_p, bitmap, (*bitmap_p) ^ bitmap,
++			    mwbmap_p->ifree));
++
++			*bitmap_p ^= bitmap; /* mark as allocated = 1b0 */
++
++			return bitix;
++		}
++	}
++
++	ASSERT(mwbmap_p->ifree == 0);
++
++	return BCM_MWBMAP_INVALID_IDX;
++}
++
++/* Force an index at a specified position to be in use */
++void
++bcm_mwbmap_force(struct bcm_mwbmap * mwbmap_hdl, uint32 bitix)
++{
++	bcm_mwbmap_t * mwbmap_p;
++	uint32 count, wordix, bitmap, *bitmap_p;
++
++	BCM_MWBMAP_AUDIT(mwbmap_hdl);
++	mwbmap_p = BCM_MWBMAP_PTR(mwbmap_hdl);
++
++	ASSERT(bitix < mwbmap_p->total);
++
++	/* Start with second hierarchy */
++	wordix   = BCM_MWBMAP_DIVOP(bitix);
++	bitmap   = (uint32)(1U << BCM_MWBMAP_MODOP(bitix));
++	bitmap_p = &mwbmap_p->id_bitmap[wordix];
++
++	ASSERT((*bitmap_p & bitmap) == bitmap);
++
++	mwbmap_p->ifree--; /* update free count */
++	ASSERT(mwbmap_p->ifree >= 0);
++
++	MWBMAP_DBG(("Lvl2: bitix<%u> wordix<%u>: %08x ^ %08x = %08x ifree %d",
++	           bitix, wordix, *bitmap_p, bitmap, (*bitmap_p) ^ bitmap,
++	           mwbmap_p->ifree));
++
++	*bitmap_p ^= bitmap; /* mark as in use */
++
++	/* Update first hierarchy */
++	bitix    = wordix;
++
++	wordix   = BCM_MWBMAP_DIVOP(bitix);
++	bitmap_p = &mwbmap_p->wd_bitmap[wordix];
++
++#if defined(BCM_MWBMAP_USE_CNTSETBITS)
++	count = bcm_cntsetbits(mwbmap_p->id_bitmap[bitix]);
++#else  /* ! BCM_MWBMAP_USE_CNTSETBITS */
++	mwbmap_p->wd_count[bitix]--;
++	count = mwbmap_p->wd_count[bitix];
++	MWBMAP_ASSERT(count == bcm_cntsetbits(mwbmap_p->id_bitmap[bitix]));
++#endif /* ! BCM_MWBMAP_USE_CNTSETBITS */
++	MWBMAP_ASSERT(count >= 0);
++
++	bitmap   = (count == 0) << BCM_MWBMAP_MODOP(bitix);
++
++	MWBMAP_DBG(("Lvl1: bitix<%02lu> wordix<%02u>: %08x ^ %08x = %08x wfree %d",
++	           BCM_MWBMAP_MODOP(bitix), wordix, *bitmap_p, bitmap,
++	           (*bitmap_p) ^ bitmap, count));
++
++	*bitmap_p ^= bitmap; /* mark as in use */
++
++	return;
++}
++
++/* Free a previously allocated index back into the multiword bitmap allocator */
++void BCMFASTPATH
++bcm_mwbmap_free(struct bcm_mwbmap * mwbmap_hdl, uint32 bitix)
++{
++	bcm_mwbmap_t * mwbmap_p;
++	uint32 wordix, bitmap, *bitmap_p;
++
++	BCM_MWBMAP_AUDIT(mwbmap_hdl);
++	mwbmap_p = BCM_MWBMAP_PTR(mwbmap_hdl);
++
++	ASSERT(bitix < mwbmap_p->total);
++
++	/* Start with second level hierarchy */
++	wordix   = BCM_MWBMAP_DIVOP(bitix);
++	bitmap   = (1U << BCM_MWBMAP_MODOP(bitix));
++	bitmap_p = &mwbmap_p->id_bitmap[wordix];
++
++	ASSERT((*bitmap_p & bitmap) == 0U);	/* ASSERT not a double free */
++
++	mwbmap_p->ifree++; /* update free count */
++	ASSERT(mwbmap_p->ifree <= mwbmap_p->total);
++
++	MWBMAP_DBG(("Lvl2: bitix<%02u> wordix<%02u>: %08x | %08x = %08x ifree %d",
++	           bitix, wordix, *bitmap_p, bitmap, (*bitmap_p) | bitmap,
++	           mwbmap_p->ifree));
++
++	*bitmap_p |= bitmap; /* mark as available */
++
++	/* Now update first level hierarchy */
++
++	bitix    = wordix;
++
++	wordix   = BCM_MWBMAP_DIVOP(bitix); /* first level's word index */
++	bitmap   = (1U << BCM_MWBMAP_MODOP(bitix));
++	bitmap_p = &mwbmap_p->wd_bitmap[wordix];
++
++#if !defined(BCM_MWBMAP_USE_CNTSETBITS)
++	mwbmap_p->wd_count[bitix]++;
++#endif
++
++#if defined(BCM_MWBMAP_DEBUG)
++	{
++		uint32 count;
++#if defined(BCM_MWBMAP_USE_CNTSETBITS)
++		count = bcm_cntsetbits(mwbmap_p->id_bitmap[bitix]);
++#else  /*  ! BCM_MWBMAP_USE_CNTSETBITS */
++		count = mwbmap_p->wd_count[bitix];
++		MWBMAP_ASSERT(count == bcm_cntsetbits(mwbmap_p->id_bitmap[bitix]));
++#endif /*  ! BCM_MWBMAP_USE_CNTSETBITS */
++
++		MWBMAP_ASSERT(count <= BCM_MWBMAP_BITS_WORD);
++
++		MWBMAP_DBG(("Lvl1: bitix<%02u> wordix<%02u>: %08x | %08x = %08x wfree %d",
++		            bitix, wordix, *bitmap_p, bitmap, (*bitmap_p) | bitmap, count));
++	}
++#endif /* BCM_MWBMAP_DEBUG */
++
++	*bitmap_p |= bitmap;
++
++	return;
++}
++
++/* Fetch the toal number of free indices in the multiword bitmap allocator */
++uint32
++bcm_mwbmap_free_cnt(struct bcm_mwbmap * mwbmap_hdl)
++{
++	bcm_mwbmap_t * mwbmap_p;
++
++	BCM_MWBMAP_AUDIT(mwbmap_hdl);
++	mwbmap_p = BCM_MWBMAP_PTR(mwbmap_hdl);
++
++	ASSERT(mwbmap_p->ifree >= 0);
++
++	return mwbmap_p->ifree;
++}
++
++/* Determine whether an index is inuse or free */
++bool
++bcm_mwbmap_isfree(struct bcm_mwbmap * mwbmap_hdl, uint32 bitix)
++{
++	bcm_mwbmap_t * mwbmap_p;
++	uint32 wordix, bitmap;
++
++	BCM_MWBMAP_AUDIT(mwbmap_hdl);
++	mwbmap_p = BCM_MWBMAP_PTR(mwbmap_hdl);
++
++	ASSERT(bitix < mwbmap_p->total);
++
++	wordix   = BCM_MWBMAP_DIVOP(bitix);
++	bitmap   = (1U << BCM_MWBMAP_MODOP(bitix));
++
++	return ((mwbmap_p->id_bitmap[wordix] & bitmap) != 0U);
++}
++
++/* Debug dump a multiword bitmap allocator */
++void
++bcm_mwbmap_show(struct bcm_mwbmap * mwbmap_hdl)
++{
++	uint32 ix, count;
++	bcm_mwbmap_t * mwbmap_p;
++
++	BCM_MWBMAP_AUDIT(mwbmap_hdl);
++	mwbmap_p = BCM_MWBMAP_PTR(mwbmap_hdl);
++
++	printf("mwbmap_p %p wmaps %u imaps %u ifree %d total %u\n", mwbmap_p,
++	       mwbmap_p->wmaps, mwbmap_p->imaps, mwbmap_p->ifree, mwbmap_p->total);
++	for (ix = 0U; ix < mwbmap_p->wmaps; ix++) {
++		printf("\tWDMAP:%2u. 0x%08x\t", ix, mwbmap_p->wd_bitmap[ix]);
++		bcm_bitprint32(mwbmap_p->wd_bitmap[ix]);
++		printf("\n");
++	}
++	for (ix = 0U; ix < mwbmap_p->imaps; ix++) {
++#if defined(BCM_MWBMAP_USE_CNTSETBITS)
++		count = bcm_cntsetbits(mwbmap_p->id_bitmap[ix]);
++#else  /* ! BCM_MWBMAP_USE_CNTSETBITS */
++		count = mwbmap_p->wd_count[ix];
++		MWBMAP_ASSERT(count == bcm_cntsetbits(mwbmap_p->id_bitmap[ix]));
++#endif /* ! BCM_MWBMAP_USE_CNTSETBITS */
++		printf("\tIDMAP:%2u. 0x%08x %02u\t", ix, mwbmap_p->id_bitmap[ix], count);
++		bcm_bitprint32(mwbmap_p->id_bitmap[ix]);
++		printf("\n");
++	}
++
++	return;
++}
++
++/* Audit a hierarchical multiword bitmap */
++void
++bcm_mwbmap_audit(struct bcm_mwbmap * mwbmap_hdl)
++{
++	bcm_mwbmap_t * mwbmap_p;
++	uint32 count, free_cnt = 0U, wordix, idmap_ix, bitix, *bitmap_p;
++
++	mwbmap_p = BCM_MWBMAP_PTR(mwbmap_hdl);
++
++	for (wordix = 0U; wordix < mwbmap_p->wmaps; ++wordix) {
++
++		bitmap_p = &mwbmap_p->wd_bitmap[wordix];
++
++		for (bitix = 0U; bitix < BCM_MWBMAP_BITS_WORD; bitix++) {
++			if ((*bitmap_p) & (1 << bitix)) {
++				idmap_ix = BCM_MWBMAP_MULOP(wordix) + bitix;
++#if defined(BCM_MWBMAP_USE_CNTSETBITS)
++				count = bcm_cntsetbits(mwbmap_p->id_bitmap[idmap_ix]);
++#else  /* ! BCM_MWBMAP_USE_CNTSETBITS */
++				count = mwbmap_p->wd_count[idmap_ix];
++				ASSERT(count == bcm_cntsetbits(mwbmap_p->id_bitmap[idmap_ix]));
++#endif /* ! BCM_MWBMAP_USE_CNTSETBITS */
++				ASSERT(count != 0U);
++				free_cnt += count;
++			}
++		}
++	}
++
++	ASSERT((int)free_cnt == mwbmap_p->ifree);
++}
++/* END : Multiword bitmap based 64bit to Unique 32bit Id allocator. */
++
++/* Simple 16bit Id allocator using a stack implementation. */
++typedef struct id16_map {
++	uint32  failures;  /* count of failures */
++	void    *dbg;      /* debug placeholder */
++	uint16  total;     /* total number of ids managed by allocator */
++	uint16  start;     /* start value of 16bit ids to be managed */
++	int     stack_idx; /* index into stack of available ids */
++	uint16  stack[0];  /* stack of 16 bit ids */
++} id16_map_t;
++
++#define ID16_MAP_SZ(items)      (sizeof(id16_map_t) + \
++	                             (sizeof(uint16) * (items)))
++
++#if defined(BCM_DBG)
++
++/* Uncomment BCM_DBG_ID16 to debug double free */
++/* #define BCM_DBG_ID16 */
++
++typedef struct id16_map_dbg {
++	uint16  total;
++	bool    avail[0];
++} id16_map_dbg_t;
++#define ID16_MAP_DBG_SZ(items)  (sizeof(id16_map_dbg_t) + \
++	                             (sizeof(bool) * (items)))
++#define ID16_MAP_MSG(x)         print x
++#else
++#define ID16_MAP_MSG(x)
++#endif /* BCM_DBG */
++
++void * /* Construct an id16 allocator: [start_val16 .. start_val16+total_ids) */
++id16_map_init(osl_t *osh, uint16 total_ids, uint16 start_val16)
++{
++	uint16 idx, val16;
++	id16_map_t * id16_map;
++
++	ASSERT(total_ids > 0);
++
++	/* A start_val16 of ID16_UNDEFINED, allows the caller to fill the id16 map
++	 * with random values.
++	 */
++	ASSERT((start_val16 == ID16_UNDEFINED) ||
++	       (start_val16 + total_ids) < ID16_INVALID);
++
++	id16_map = (id16_map_t *) MALLOC(osh, ID16_MAP_SZ(total_ids));
++	if (id16_map == NULL) {
++		return NULL;
++	}
++
++	id16_map->total = total_ids;
++	id16_map->start = start_val16;
++	id16_map->failures = 0;
++	id16_map->dbg = NULL;
++
++	/*
++	 * Populate stack with 16bit id values, commencing with start_val16.
++	 * if start_val16 is ID16_UNDEFINED, then do not populate the id16 map.
++	 */
++	id16_map->stack_idx = -1;
++
++	if (id16_map->start != ID16_UNDEFINED) {
++		val16 = start_val16;
++
++		for (idx = 0; idx < total_ids; idx++, val16++) {
++			id16_map->stack_idx = idx;
++			id16_map->stack[id16_map->stack_idx] = val16;
++		}
++	}
++
++#if defined(BCM_DBG) && defined(BCM_DBG_ID16)
++	if (id16_map->start != ID16_UNDEFINED) {
++		id16_map->dbg = MALLOC(osh, ID16_MAP_DBG_SZ(total_ids));
++
++		if (id16_map->dbg) {
++			id16_map_dbg_t *id16_map_dbg = (id16_map_dbg_t *)id16_map->dbg;
++
++			id16_map_dbg->total = total_ids;
++			for (idx = 0; idx < total_ids; idx++) {
++				id16_map_dbg->avail[idx] = TRUE;
++			}
++		}
++	}
++#endif /* BCM_DBG && BCM_DBG_ID16 */
++
++	return (void *)id16_map;
++}
++
++void * /* Destruct an id16 allocator instance */
++id16_map_fini(osl_t *osh, void * id16_map_hndl)
++{
++	uint16 total_ids;
++	id16_map_t * id16_map;
++
++	if (id16_map_hndl == NULL)
++		return NULL;
++
++	id16_map = (id16_map_t *)id16_map_hndl;
++
++	total_ids = id16_map->total;
++	ASSERT(total_ids > 0);
++
++#if defined(BCM_DBG) && defined(BCM_DBG_ID16)
++	if (id16_map->dbg) {
++		MFREE(osh, id16_map->dbg, ID16_MAP_DBG_SZ(total_ids));
++		id16_map->dbg = NULL;
++	}
++#endif /* BCM_DBG && BCM_DBG_ID16 */
++
++	id16_map->total = 0;
++	MFREE(osh, id16_map, ID16_MAP_SZ(total_ids));
++
++	return NULL;
++}
++
++void
++id16_map_clear(void * id16_map_hndl, uint16 total_ids, uint16 start_val16)
++{
++	uint16 idx, val16;
++	id16_map_t * id16_map;
++
++	ASSERT(total_ids > 0);
++	/* A start_val16 of ID16_UNDEFINED, allows the caller to fill the id16 map
++	 * with random values.
++	 */
++	ASSERT((start_val16 == ID16_UNDEFINED) ||
++	       (start_val16 + total_ids) < ID16_INVALID);
++
++	id16_map = (id16_map_t *)id16_map_hndl;
++	if (id16_map == NULL) {
++		return;
++	}
++
++	id16_map->total = total_ids;
++	id16_map->start = start_val16;
++	id16_map->failures = 0;
++
++	/* Populate stack with 16bit id values, commencing with start_val16 */
++	id16_map->stack_idx = -1;
++
++	if (id16_map->start != ID16_UNDEFINED) {
++		val16 = start_val16;
++
++		for (idx = 0; idx < total_ids; idx++, val16++) {
++			id16_map->stack_idx = idx;
++			id16_map->stack[id16_map->stack_idx] = val16;
++		}
++	}
++
++#if defined(BCM_DBG) && defined(BCM_DBG_ID16)
++	if (id16_map->start != ID16_UNDEFINED) {
++		if (id16_map->dbg) {
++			id16_map_dbg_t *id16_map_dbg = (id16_map_dbg_t *)id16_map->dbg;
++
++			id16_map_dbg->total = total_ids;
++			for (idx = 0; idx < total_ids; idx++) {
++				id16_map_dbg->avail[idx] = TRUE;
++			}
++		}
++	}
++#endif /* BCM_DBG && BCM_DBG_ID16 */
++}
++
++uint16 BCMFASTPATH /* Allocate a unique 16bit id */
++id16_map_alloc(void * id16_map_hndl)
++{
++	uint16 val16;
++	id16_map_t * id16_map;
++
++	ASSERT(id16_map_hndl != NULL);
++
++	id16_map = (id16_map_t *)id16_map_hndl;
++
++	ASSERT(id16_map->total > 0);
++
++	if (id16_map->stack_idx < 0) {
++		id16_map->failures++;
++		return ID16_INVALID;
++	}
++
++	val16 = id16_map->stack[id16_map->stack_idx];
++	id16_map->stack_idx--;
++
++#if defined(BCM_DBG) && defined(BCM_DBG_ID16)
++	ASSERT((id16_map->start == ID16_UNDEFINED) ||
++	       (val16 < (id16_map->start + id16_map->total)));
++
++	if (id16_map->dbg) { /* Validate val16 */
++		id16_map_dbg_t *id16_map_dbg = (id16_map_dbg_t *)id16_map->dbg;
++
++		ASSERT(id16_map_dbg->avail[val16 - id16_map->start] == TRUE);
++		id16_map_dbg->avail[val16 - id16_map->start] = FALSE;
++	}
++#endif /* BCM_DBG && BCM_DBG_ID16 */
++
++	return val16;
++}
++
++
++void BCMFASTPATH /* Free a 16bit id value into the id16 allocator */
++id16_map_free(void * id16_map_hndl, uint16 val16)
++{
++	id16_map_t * id16_map;
++
++	ASSERT(id16_map_hndl != NULL);
++
++	id16_map = (id16_map_t *)id16_map_hndl;
++
++#if defined(BCM_DBG) && defined(BCM_DBG_ID16)
++	ASSERT((id16_map->start == ID16_UNDEFINED) ||
++	       (val16 < (id16_map->start + id16_map->total)));
++
++	if (id16_map->dbg) { /* Validate val16 */
++		id16_map_dbg_t *id16_map_dbg = (id16_map_dbg_t *)id16_map->dbg;
++
++		ASSERT(id16_map_dbg->avail[val16 - id16_map->start] == FALSE);
++		id16_map_dbg->avail[val16 - id16_map->start] = TRUE;
++	}
++#endif /* BCM_DBG && BCM_DBG_ID16 */
++
++	id16_map->stack_idx++;
++	id16_map->stack[id16_map->stack_idx] = val16;
++}
++
++uint32 /* Returns number of failures to allocate an unique id16 */
++id16_map_failures(void * id16_map_hndl)
++{
++	ASSERT(id16_map_hndl != NULL);
++	return ((id16_map_t *)id16_map_hndl)->failures;
++}
++
++bool
++id16_map_audit(void * id16_map_hndl)
++{
++	int idx;
++	int insane = 0;
++	id16_map_t * id16_map;
++
++	ASSERT(id16_map_hndl != NULL);
++
++	id16_map = (id16_map_t *)id16_map_hndl;
++
++	ASSERT(id16_map->stack_idx >= -1);
++	ASSERT(id16_map->stack_idx < (int)id16_map->total);
++
++	if (id16_map->start == ID16_UNDEFINED)
++		goto done;
++
++	for (idx = 0; idx <= id16_map->stack_idx; idx++) {
++		ASSERT(id16_map->stack[idx] >= id16_map->start);
++		ASSERT(id16_map->stack[idx] < (id16_map->start + id16_map->total));
++
++#if defined(BCM_DBG) && defined(BCM_DBG_ID16)
++		if (id16_map->dbg) {
++			uint16 val16 = id16_map->stack[idx];
++			if (((id16_map_dbg_t *)(id16_map->dbg))->avail[val16] != TRUE) {
++				insane |= 1;
++				ID16_MAP_MSG(("id16_map<%p>: stack_idx %u invalid val16 %u\n",
++					id16_map_hndl, idx, val16));
++			}
++		}
++#endif /* BCM_DBG && BCM_DBG_ID16 */
++	}
++
++#if defined(BCM_DBG) && defined(BCM_DBG_ID16)
++	if (id16_map->dbg) {
++		uint16 avail = 0; /* Audit available ids counts */
++		for (idx = 0; idx < id16_map_dbg->total; idx++) {
++			if (((id16_map_dbg_t *)(id16_map->dbg))->avail[idx16] == TRUE)
++				avail++;
++		}
++		if (avail && (avail != (id16_map->stack_idx + 1))) {
++			insane |= 1;
++			ID16_MAP_MSG(("id16_map<%p>: avail %u stack_idx %u\n",
++				id16_map_hndl, avail, id16_map->stack_idx));
++		}
++	}
++#endif /* BCM_DBG && BCM_DBG_ID16 */
++
++done:
++	/* invoke any other system audits */
++	return (!!insane);
++}
++/* END: Simple id16 allocator */
++
++
++#endif 
++
++/* calculate a >> b; and returns only lower 32 bits */
++void
++bcm_uint64_right_shift(uint32* r, uint32 a_high, uint32 a_low, uint32 b)
++{
++	uint32 a1 = a_high, a0 = a_low, r0 = 0;
++
++	if (b == 0) {
++		r0 = a_low;
++		*r = r0;
++		return;
++	}
++
++	if (b < 32) {
++		a0 = a0 >> b;
++		a1 = a1 & ((1 << b) - 1);
++		a1 = a1 << (32 - b);
++		r0 = a0 | a1;
++		*r = r0;
++		return;
++	} else {
++		r0 = a1 >> (b - 32);
++		*r = r0;
++		return;
++	}
++
++}
++
++/* calculate a + b where a is a 64 bit number and b is a 32 bit number */
++void
++bcm_add_64(uint32* r_hi, uint32* r_lo, uint32 offset)
++{
++	uint32 r1_lo = *r_lo;
++	(*r_lo) += offset;
++	if (*r_lo < r1_lo)
++		(*r_hi) ++;
++}
++
++/* calculate a - b where a is a 64 bit number and b is a 32 bit number */
++void
++bcm_sub_64(uint32* r_hi, uint32* r_lo, uint32 offset)
++{
++	uint32 r1_lo = *r_lo;
++	(*r_lo) -= offset;
++	if (*r_lo > r1_lo)
++		(*r_hi) --;
++}
++
++/* Does unsigned 64 bit fixed point multiplication */
++uint64
++fp_mult_64(uint64 val1, uint64 val2, uint8 nf1, uint8 nf2, uint8 nf_res)
++{
++	uint64 mult_out_tmp, mult_out, rnd_val;
++	uint8 shift_amt;
++
++	shift_amt = nf1 + nf2 - nf_res;
++	/* 0.5 in 1.0.shift_amt */
++	rnd_val = bcm_shl_64(1, (shift_amt - 1));
++	rnd_val = (shift_amt == 0) ? 0 : rnd_val;
++	mult_out_tmp = (uint64)((uint64)val1 * (uint64)val2) + (uint64)rnd_val;
++	mult_out = bcm_shr_64(mult_out_tmp, shift_amt);
++
++	return mult_out;
++}
++
++
++/* Does unsigned 64 bit by 32 bit fixed point division */
++uint8
++fp_div_64(uint64 num, uint32 den, uint8 nf_num, uint8 nf_den, uint32 *div_out)
++{
++	uint8 shift_amt1, shift_amt2, shift_amt, nf_res, hd_rm_nr, hd_rm_dr;
++	uint32 num_hi, num_lo;
++	uint64 num_scale;
++
++	/* Worst case shift possible */
++	hd_rm_nr = fp_calc_head_room_64(num);
++	hd_rm_dr = fp_calc_head_room_32(den);
++
++	/* (Nr / Dr) <= 2^32 */
++	shift_amt1 = hd_rm_nr - hd_rm_dr - 1;
++	/* Shift <= 32 + N2 - N1 */
++	shift_amt2 = 31 + nf_den - nf_num;
++	shift_amt = MINIMUM(shift_amt1, shift_amt2);
++
++	/* Scale numerator */
++	num_scale = bcm_shl_64(num, shift_amt);
++
++	/* Do division */
++	num_hi = (uint32)((uint64)num_scale >> 32) & MASK_32_BITS;
++	num_lo = (uint32)(num_scale & MASK_32_BITS);
++	bcm_uint64_divide(div_out, num_hi, num_lo, den);
++
++	/* Result format */
++	nf_res = nf_num - nf_den + shift_amt;
++	return nf_res;
++}
++
++/* Finds the number of bits available for shifting in unsigned 64 bit number */
++uint8
++fp_calc_head_room_64(uint64 num)
++{
++	uint8 n_room_bits = 0, msb_pos;
++	uint32 num_hi, num_lo, x;
++
++	num_hi = (uint32)((uint64)num >> 32) & MASK_32_BITS;
++	num_lo = (uint32)(num & MASK_32_BITS);
++
++	if (num_hi > 0) {
++		x = num_hi;
++		n_room_bits = 0;
++	} else {
++		x = num_lo;
++		n_room_bits = 32;
++	}
++
++	msb_pos = (x >> 16) ? ((x >> 24) ? (24 + msb_table[(x >> 24) & MASK_8_BITS])
++			: (16 + msb_table[(x >> 16) & MASK_8_BITS]))
++			: ((x >> 8) ? (8 + msb_table[(x >> 8) & MASK_8_BITS])
++			: msb_table[x & MASK_8_BITS]);
++
++	return (n_room_bits + 32 - msb_pos);
++}
++
++/* Finds the number of bits available for shifting in unsigned 32 bit number */
++uint8
++fp_calc_head_room_32(uint32 x)
++{
++	uint8 msb_pos;
++
++	msb_pos = (x >> 16) ? ((x >> 24) ? (24 + msb_table[(x >> 24) & MASK_8_BITS])
++			: (16 + msb_table[(x >> 16) & MASK_8_BITS]))
++			: ((x >> 8) ? (8 + msb_table[(x >> 8) & MASK_8_BITS])
++			: msb_table[x & MASK_8_BITS]);
++
++	return (32 - msb_pos);
++}
++
++/* Does unsigned 64 bit fixed point floor */
++uint32
++fp_floor_64(uint64 num, uint8 floor_pos)
++{
++	uint32 floor_out;
++
++	floor_out = (uint32)bcm_shr_64(num, floor_pos);
++
++	return floor_out;
++}
++
++/* Does unsigned 32 bit fixed point floor */
++uint32
++fp_floor_32(uint32 num, uint8 floor_pos)
++{
++	return num >> floor_pos;
++}
++
++/* Does unsigned 64 bit fixed point rounding */
++uint32
++fp_round_64(uint64 num, uint8 rnd_pos)
++{
++	uint64 rnd_val, rnd_out_tmp;
++	uint32 rnd_out;
++
++	/* 0.5 in 1.0.rnd_pos */
++	rnd_val = bcm_shl_64(1, (rnd_pos - 1));
++	rnd_val = (rnd_pos == 0) ? 0 : rnd_val;
++	rnd_out_tmp = num + rnd_val;
++	rnd_out = (uint32)bcm_shr_64(rnd_out_tmp, rnd_pos);
++
++	return rnd_out;
++}
++
++/* Does unsigned 32 bit fixed point rounding */
++uint32
++fp_round_32(uint32 num, uint8 rnd_pos)
++{
++	uint32 rnd_val, rnd_out_tmp;
++
++	/* 0.5 in 1.0.rnd_pos */
++	rnd_val = 1 << (rnd_pos - 1);
++	rnd_val = (rnd_pos == 0) ? 0 : rnd_val;
++	rnd_out_tmp = num + rnd_val;
++	return (rnd_out_tmp >> rnd_pos);
++}
++
++/* Does unsigned fixed point ceiling */
++uint32
++fp_ceil_64(uint64 num, uint8 ceil_pos)
++{
++	uint64 ceil_val, ceil_out_tmp;
++	uint32 ceil_out;
++
++	/* 0.999 in 1.0.rnd_pos */
++	ceil_val = bcm_shl_64(1, ceil_pos) - 1;
++	ceil_out_tmp = num + ceil_val;
++	ceil_out = (uint32)bcm_shr_64(ceil_out_tmp, ceil_pos);
++
++	return ceil_out;
++}
++
++/* Does left shift of unsigned 64 bit number */
++uint64
++bcm_shl_64(uint64 input, uint8 shift_amt)
++{
++	uint32 in_hi, in_lo;
++	uint32 masked_lo = 0;
++	uint32 mask;
++	uint64 shl_out;
++
++	if (shift_amt == 0) {
++		return input;
++	}
++
++	/* Get hi and lo part */
++	in_hi = (uint32)((uint64)input >> 32) & MASK_32_BITS;
++	in_lo = (uint32)(input & MASK_32_BITS);
++
++	if (shift_amt < 32) {
++		/* Extract bit which belongs to hi part after shifting */
++		mask = ((uint32)~0) << (32 - shift_amt);
++		masked_lo = (in_lo & mask) >> (32 - shift_amt);
++
++		/* Shift hi and lo and prepare output */
++		in_hi = (in_hi << shift_amt) | masked_lo;
++		in_lo = in_lo << shift_amt;
++	} else {
++		/* Extract bit which belongs to hi part after shifting */
++		shift_amt = shift_amt - 32;
++
++		/* Shift hi and lo and prepare output */
++		in_hi = in_lo << shift_amt;
++		in_lo = 0;
++	}
++
++	shl_out = (((uint64)in_hi << 32) | in_lo);
++	return shl_out;
++}
++
++/* Does right shift of unsigned 64 bit number */
++uint64
++bcm_shr_64(uint64 input, uint8 shift_amt)
++{
++	uint32 in_hi, in_lo;
++	uint32 masked_hi = 0;
++	uint32 mask;
++	uint64 shr_out;
++
++	if (shift_amt == 0) {
++		return input;
++	}
++
++	/* Get hi and lo part */
++	in_hi = (uint32)((uint64)input >> 32) & MASK_32_BITS;
++	in_lo = (uint32)(input & MASK_32_BITS);
++
++	if (shift_amt < 32) {
++		/* Extract bit which belongs to lo part after shifting */
++		mask = (1 << shift_amt) - 1;
++		masked_hi = in_hi & mask;
++
++		/* Shift hi and lo and prepare output */
++		in_hi = (uint32)in_hi >> shift_amt;
++		in_lo = ((uint32)in_lo >> shift_amt) | (masked_hi << (32 - shift_amt));
++	} else {
++		shift_amt = shift_amt - 32;
++		in_lo = in_hi >> shift_amt;
++		in_hi = 0;
++	}
++
++	shr_out = (((uint64)in_hi << 32) | in_lo);
++	return shr_out;
++}
++
++#ifdef DEBUG_COUNTER
++#if (OSL_SYSUPTIME_SUPPORT == TRUE)
++void counter_printlog(counter_tbl_t *ctr_tbl)
++{
++	uint32 now;
++
++	if (!ctr_tbl->enabled)
++		return;
++
++	now = OSL_SYSUPTIME();
++
++	if (now - ctr_tbl->prev_log_print > ctr_tbl->log_print_interval) {
++		uint8 i = 0;
++		printf("counter_print(%s %d):", ctr_tbl->name, now - ctr_tbl->prev_log_print);
++
++		for (i = 0; i < ctr_tbl->needed_cnt; i++) {
++			printf(" %u", ctr_tbl->cnt[i]);
++		}
++		printf("\n");
++
++		ctr_tbl->prev_log_print = now;
++		bzero(ctr_tbl->cnt, CNTR_TBL_MAX * sizeof(uint));
++	}
++}
++#else
++/* OSL_SYSUPTIME is not supported so no way to get time */
++#define counter_printlog(a) do {} while (0)
++#endif /* OSL_SYSUPTIME_SUPPORT == TRUE */
++#endif /* DEBUG_COUNTER */
++
++#if defined(BCMDRIVER) && !defined(_CFEZ_)
++void
++dll_pool_detach(void * osh, dll_pool_t * pool, uint16 elems_max, uint16 elem_size)
++{
++	uint32 mem_size;
++	mem_size = sizeof(dll_pool_t) + (elems_max * elem_size);
++	if (pool)
++		MFREE(osh, pool, mem_size);
++}
++dll_pool_t *
++dll_pool_init(void * osh, uint16 elems_max, uint16 elem_size)
++{
++	uint32 mem_size, i;
++	dll_pool_t * dll_pool_p;
++	dll_t * elem_p;
++
++	ASSERT(elem_size > sizeof(dll_t));
++
++	mem_size = sizeof(dll_pool_t) + (elems_max * elem_size);
++
++	if ((dll_pool_p = (dll_pool_t *)MALLOCZ(osh, mem_size)) == NULL) {
++		printf("dll_pool_init: elems_max<%u> elem_size<%u> malloc failure\n",
++			elems_max, elem_size);
++		ASSERT(0);
++		return dll_pool_p;
++	}
++
++	dll_init(&dll_pool_p->free_list);
++	dll_pool_p->elems_max = elems_max;
++	dll_pool_p->elem_size = elem_size;
++
++	elem_p = dll_pool_p->elements;
++	for (i = 0; i < elems_max; i++) {
++		dll_append(&dll_pool_p->free_list, elem_p);
++		elem_p = (dll_t *)((uintptr)elem_p + elem_size);
++	}
++
++	dll_pool_p->free_count = elems_max;
++
++	return dll_pool_p;
++}
++
++
++void *
++dll_pool_alloc(dll_pool_t * dll_pool_p)
++{
++	dll_t * elem_p;
++
++	if (dll_pool_p->free_count == 0) {
++		ASSERT(dll_empty(&dll_pool_p->free_list));
++		return NULL;
++	}
++
++	elem_p = dll_head_p(&dll_pool_p->free_list);
++	dll_delete(elem_p);
++	dll_pool_p->free_count -= 1;
++
++	return (void *)elem_p;
++}
++
++void
++dll_pool_free(dll_pool_t * dll_pool_p, void * elem_p)
++{
++	dll_t * node_p = (dll_t *)elem_p;
++	dll_prepend(&dll_pool_p->free_list, node_p);
++	dll_pool_p->free_count += 1;
++}
++
++
++void
++dll_pool_free_tail(dll_pool_t * dll_pool_p, void * elem_p)
++{
++	dll_t * node_p = (dll_t *)elem_p;
++	dll_append(&dll_pool_p->free_list, node_p);
++	dll_pool_p->free_count += 1;
++}
++
++#endif 
++
++/* calculate partial checksum */
++static uint32
++ip_cksum_partial(uint32 sum, uint8 *val8, uint32 count)
++{
++	uint32 i;
++	uint16 *val16 = (uint16 *)val8;
++
++	ASSERT(val8 != NULL);
++	/* partial chksum calculated on 16-bit values */
++	ASSERT((count % 2) == 0);
++
++	count /= 2;
++
++	for (i = 0; i < count; i++) {
++		sum += *val16++;
++	}
++	return sum;
++}
++
++/* calculate IP checksum */
++static uint16
++ip_cksum(uint32 sum, uint8 *val8, uint32 count)
++{
++	uint16 *val16 = (uint16 *)val8;
++
++	ASSERT(val8 != NULL);
++
++	while (count > 1) {
++		sum += *val16++;
++		count -= 2;
++	}
++	/*  add left-over byte, if any */
++	if (count > 0) {
++		sum += (*(uint8 *)val16);
++	}
++
++	/*  fold 32-bit sum to 16 bits */
++	sum = (sum >> 16) + (sum & 0xffff);
++	sum += (sum >> 16);
++	return ((uint16)~sum);
++}
++
++/* calculate IPv4 header checksum
++ * - input ip points to IP header in network order
++ * - output cksum is in network order
++ */
++uint16
++ipv4_hdr_cksum(uint8 *ip, int ip_len)
++{
++	uint32 sum = 0;
++	uint8 *ptr = ip;
++
++	ASSERT(ip != NULL);
++	ASSERT(ip_len >= IPV4_MIN_HEADER_LEN);
++
++	/* partial cksum skipping the hdr_chksum field */
++	sum = ip_cksum_partial(sum, ptr, OFFSETOF(struct ipv4_hdr, hdr_chksum));
++	ptr += OFFSETOF(struct ipv4_hdr, hdr_chksum) + 2;
++
++	/* return calculated chksum */
++	return ip_cksum(sum, ptr, ip_len - OFFSETOF(struct ipv4_hdr, src_ip));
++}
++
++/* calculate TCP header checksum using partial sum */
++static uint16
++tcp_hdr_chksum(uint32 sum, uint8 *tcp_hdr, uint16 tcp_len)
++{
++	uint8 *ptr = tcp_hdr;
++
++	ASSERT(tcp_hdr != NULL);
++	ASSERT(tcp_len >= TCP_MIN_HEADER_LEN);
++
++	/* partial TCP cksum skipping the chksum field */
++	sum = ip_cksum_partial(sum, ptr, OFFSETOF(struct bcmtcp_hdr, chksum));
++	ptr += OFFSETOF(struct bcmtcp_hdr, chksum) + 2;
++
++	/* return calculated chksum */
++	return ip_cksum(sum, ptr, tcp_len - OFFSETOF(struct bcmtcp_hdr, urg_ptr));
++}
++
++struct tcp_pseudo_hdr {
++	uint8   src_ip[IPV4_ADDR_LEN];  /* Source IP Address */
++	uint8   dst_ip[IPV4_ADDR_LEN];  /* Destination IP Address */
++	uint8	zero;
++	uint8	prot;
++	uint16	tcp_size;
++};
++
++/* calculate IPv4 TCP header checksum
++ * - input ip and tcp points to IP and TCP header in network order
++ * - output cksum is in network order
++ */
++uint16
++ipv4_tcp_hdr_cksum(uint8 *ip, uint8 *tcp, uint16 tcp_len)
++{
++	struct ipv4_hdr *ip_hdr = (struct ipv4_hdr *)ip;
++	struct tcp_pseudo_hdr tcp_ps;
++	uint32 sum = 0;
++
++	ASSERT(ip != NULL);
++	ASSERT(tcp != NULL);
++	ASSERT(tcp_len >= TCP_MIN_HEADER_LEN);
++
++	/* pseudo header cksum */
++	memset(&tcp_ps, 0, sizeof(tcp_ps));
++	memcpy(&tcp_ps.dst_ip, ip_hdr->dst_ip, IPV4_ADDR_LEN);
++	memcpy(&tcp_ps.src_ip, ip_hdr->src_ip, IPV4_ADDR_LEN);
++	tcp_ps.zero = 0;
++	tcp_ps.prot = ip_hdr->prot;
++	tcp_ps.tcp_size = hton16(tcp_len);
++	sum = ip_cksum_partial(sum, (uint8 *)&tcp_ps, sizeof(tcp_ps));
++
++	/* return calculated TCP header chksum */
++	return tcp_hdr_chksum(sum, tcp, tcp_len);
++}
++
++struct ipv6_pseudo_hdr {
++	uint8  saddr[IPV6_ADDR_LEN];
++	uint8  daddr[IPV6_ADDR_LEN];
++	uint16 payload_len;
++	uint8  zero;
++	uint8  next_hdr;
++};
++
++/* calculate IPv6 TCP header checksum
++ * - input ipv6 and tcp points to IPv6 and TCP header in network order
++ * - output cksum is in network order
++ */
++uint16
++ipv6_tcp_hdr_cksum(uint8 *ipv6, uint8 *tcp, uint16 tcp_len)
++{
++	struct ipv6_hdr *ipv6_hdr = (struct ipv6_hdr *)ipv6;
++	struct ipv6_pseudo_hdr ipv6_pseudo;
++	uint32 sum = 0;
++
++	ASSERT(ipv6 != NULL);
++	ASSERT(tcp != NULL);
++	ASSERT(tcp_len >= TCP_MIN_HEADER_LEN);
++
++	/* pseudo header cksum */
++	memset((char *)&ipv6_pseudo, 0, sizeof(ipv6_pseudo));
++	memcpy((char *)ipv6_pseudo.saddr, (char *)ipv6_hdr->saddr.addr,
++		sizeof(ipv6_pseudo.saddr));
++	memcpy((char *)ipv6_pseudo.daddr, (char *)ipv6_hdr->daddr.addr,
++		sizeof(ipv6_pseudo.daddr));
++	ipv6_pseudo.payload_len = ipv6_hdr->payload_len;
++	ipv6_pseudo.next_hdr = ipv6_hdr->nexthdr;
++	sum = ip_cksum_partial(sum, (uint8 *)&ipv6_pseudo, sizeof(ipv6_pseudo));
++
++	/* return calculated TCP header chksum */
++	return tcp_hdr_chksum(sum, tcp, tcp_len);
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/bcmwifi_channels.c b/module_drivers/drivers/net/wireless/bcmdhd/bcmwifi_channels.c
+new file mode 100644
+index 000000000..40fc3f757
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/bcmwifi_channels.c
+@@ -0,0 +1,1349 @@
++/*
++ * Misc utility routines used by kernel or app-level.
++ * Contents are wifi-specific, used by any kernel or app-level
++ * software that might want wifi things as it grows.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmwifi_channels.c 612483 2016-01-14 03:44:27Z $
++ */
++
++#include <bcm_cfg.h>
++#include <typedefs.h>
++#include <bcmutils.h>
++
++#ifdef BCMDRIVER
++#include <osl.h>
++#define strtoul(nptr, endptr, base) bcm_strtoul((nptr), (endptr), (base))
++#define tolower(c) (bcm_isupper((c)) ? ((c) + 'a' - 'A') : (c))
++#else
++#include <stdio.h>
++#include <stdlib.h>
++#include <ctype.h>
++#ifndef ASSERT
++#define ASSERT(exp)
++#endif
++#endif /* BCMDRIVER */
++
++#include <bcmwifi_channels.h>
++
++#if defined(WIN32) && (defined(BCMDLL) || defined(WLMDLL))
++#include <bcmstdlib.h> 	/* For wl/exe/GNUmakefile.brcm_wlu and GNUmakefile.wlm_dll */
++#endif
++
++/* Definitions for D11AC capable Chanspec type */
++
++/* Chanspec ASCII representation with 802.11ac capability:
++ * [<band> 'g'] <channel> ['/'<bandwidth> [<ctl-sideband>]['/'<1st80channel>'-'<2nd80channel>]]
++ *
++ * <band>:
++ *      (optional) 2, 3, 4, 5 for 2.4GHz, 3GHz, 4GHz, and 5GHz respectively.
++ *      Default value is 2g if channel <= 14, otherwise 5g.
++ * <channel>:
++ *      channel number of the 5MHz, 10MHz, 20MHz channel,
++ *      or primary channel of 40MHz, 80MHz, 160MHz, or 80+80MHz channel.
++ * <bandwidth>:
++ *      (optional) 5, 10, 20, 40, 80, 160, or 80+80. Default value is 20.
++ * <primary-sideband>:
++ *      (only for 2.4GHz band 40MHz) U for upper sideband primary, L for lower.
++ *
++ *      For 2.4GHz band 40MHz channels, the same primary channel may be the
++ *      upper sideband for one 40MHz channel, and the lower sideband for an
++ *      overlapping 40MHz channel.  The U/L disambiguates which 40MHz channel
++ *      is being specified.
++ *
++ *      For 40MHz in the 5GHz band and all channel bandwidths greater than
++ *      40MHz, the U/L specificaion is not allowed since the channels are
++ *      non-overlapping and the primary sub-band is derived from its
++ *      position in the wide bandwidth channel.
++ *
++ * <1st80Channel>:
++ * <2nd80Channel>:
++ *      Required for 80+80, otherwise not allowed.
++ *      Specifies the center channel of the first and second 80MHz band.
++ *
++ * In its simplest form, it is a 20MHz channel number, with the implied band
++ * of 2.4GHz if channel number <= 14, and 5GHz otherwise.
++ *
++ * To allow for backward compatibility with scripts, the old form for
++ * 40MHz channels is also allowed: <channel><ctl-sideband>
++ *
++ * <channel>:
++ *	primary channel of 40MHz, channel <= 14 is 2GHz, otherwise 5GHz
++ * <ctl-sideband>:
++ * 	"U" for upper, "L" for lower (or lower case "u" "l")
++ *
++ * 5 GHz Examples:
++ *      Chanspec        BW        Center Ch  Channel Range  Primary Ch
++ *      5g8             20MHz     8          -              -
++ *      52              20MHz     52         -              -
++ *      52/40           40MHz     54         52-56          52
++ *      56/40           40MHz     54         52-56          56
++ *      52/80           80MHz     58         52-64          52
++ *      56/80           80MHz     58         52-64          56
++ *      60/80           80MHz     58         52-64          60
++ *      64/80           80MHz     58         52-64          64
++ *      52/160          160MHz    50         36-64          52
++ *      36/160          160MGz    50         36-64          36
++ *      36/80+80/42-106 80+80MHz  42,106     36-48,100-112  36
++ *
++ * 2 GHz Examples:
++ *      Chanspec        BW        Center Ch  Channel Range  Primary Ch
++ *      2g8             20MHz     8          -              -
++ *      8               20MHz     8          -              -
++ *      6               20MHz     6          -              -
++ *      6/40l           40MHz     8          6-10           6
++ *      6l              40MHz     8          6-10           6
++ *      6/40u           40MHz     4          2-6            6
++ *      6u              40MHz     4          2-6            6
++ */
++
++/* bandwidth ASCII string */
++static const char *wf_chspec_bw_str[] =
++{
++	"5",
++	"10",
++	"20",
++	"40",
++	"80",
++	"160",
++	"80+80",
++#ifdef WL11ULB
++	"2.5"
++#else /* WL11ULB */
++	"na"
++#endif /* WL11ULB */
++};
++
++static const uint8 wf_chspec_bw_mhz[] =
++{5, 10, 20, 40, 80, 160, 160};
++
++#define WF_NUM_BW \
++	(sizeof(wf_chspec_bw_mhz)/sizeof(uint8))
++
++/* 40MHz channels in 5GHz band */
++static const uint8 wf_5g_40m_chans[] =
++{38, 46, 54, 62, 102, 110, 118, 126, 134, 142, 151, 159};
++#define WF_NUM_5G_40M_CHANS \
++	(sizeof(wf_5g_40m_chans)/sizeof(uint8))
++
++/* 80MHz channels in 5GHz band */
++static const uint8 wf_5g_80m_chans[] =
++{42, 58, 106, 122, 138, 155};
++#define WF_NUM_5G_80M_CHANS \
++	(sizeof(wf_5g_80m_chans)/sizeof(uint8))
++
++/* 160MHz channels in 5GHz band */
++static const uint8 wf_5g_160m_chans[] =
++{50, 114};
++#define WF_NUM_5G_160M_CHANS \
++	(sizeof(wf_5g_160m_chans)/sizeof(uint8))
++
++/* opclass and channel information for US. Table E-1 */
++static const uint16 opclass_data[] = {
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_20)&WL_CHANSPEC_BW_MASK)),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_20)&WL_CHANSPEC_BW_MASK)),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_20)&WL_CHANSPEC_BW_MASK)),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_20)&WL_CHANSPEC_BW_MASK)),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_20)&WL_CHANSPEC_BW_MASK)),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_5)&WL_CHANSPEC_BW_MASK)),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_5)&WL_CHANSPEC_BW_MASK)),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_10)&WL_CHANSPEC_BW_MASK)),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_10)&WL_CHANSPEC_BW_MASK)),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_20)&WL_CHANSPEC_BW_MASK)),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_20)&WL_CHANSPEC_BW_MASK)),
++	(WL_CHANSPEC_BAND_2G |((WL_CHANSPEC_BW_20)&WL_CHANSPEC_BW_MASK)),
++	(WL_CHANSPEC_BAND_3G |((WL_CHANSPEC_BW_20)&WL_CHANSPEC_BW_MASK)),
++	(WL_CHANSPEC_BAND_3G |((WL_CHANSPEC_BW_10)&WL_CHANSPEC_BW_MASK)),
++	(WL_CHANSPEC_BAND_3G |((WL_CHANSPEC_BW_5)&WL_CHANSPEC_BW_MASK)),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_5)&WL_CHANSPEC_BW_MASK)),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_10)&WL_CHANSPEC_BW_MASK)),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_20)&WL_CHANSPEC_BW_MASK)),
++	0,
++	0,
++	0,
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_40)&WL_CHANSPEC_BW_MASK)|WL_CHANSPEC_CTL_SB_LOWER),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_40)&WL_CHANSPEC_BW_MASK)|WL_CHANSPEC_CTL_SB_LOWER),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_40)&WL_CHANSPEC_BW_MASK)|WL_CHANSPEC_CTL_SB_LOWER),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_40)&WL_CHANSPEC_BW_MASK)|WL_CHANSPEC_CTL_SB_LOWER),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_40)&WL_CHANSPEC_BW_MASK)|WL_CHANSPEC_CTL_SB_LOWER),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_40)&WL_CHANSPEC_BW_MASK)|WL_CHANSPEC_CTL_SB_UPPER),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_40)&WL_CHANSPEC_BW_MASK)|WL_CHANSPEC_CTL_SB_UPPER),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_40)&WL_CHANSPEC_BW_MASK)|WL_CHANSPEC_CTL_SB_UPPER),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_40)&WL_CHANSPEC_BW_MASK)|WL_CHANSPEC_CTL_SB_UPPER),
++	(WL_CHANSPEC_BAND_5G |((WL_CHANSPEC_BW_40)&WL_CHANSPEC_BW_MASK)|WL_CHANSPEC_CTL_SB_UPPER),
++	(WL_CHANSPEC_BAND_2G |((WL_CHANSPEC_BW_40)&WL_CHANSPEC_BW_MASK)|WL_CHANSPEC_CTL_SB_LOWER),
++	(WL_CHANSPEC_BAND_2G |((WL_CHANSPEC_BW_40)&WL_CHANSPEC_BW_MASK)|WL_CHANSPEC_CTL_SB_UPPER),
++};
++
++/* convert bandwidth from chanspec to MHz */
++static uint
++bw_chspec_to_mhz(chanspec_t chspec)
++{
++	uint bw;
++
++	bw = (chspec & WL_CHANSPEC_BW_MASK) >> WL_CHANSPEC_BW_SHIFT;
++	return (bw >= WF_NUM_BW ? 0 : wf_chspec_bw_mhz[bw]);
++}
++
++/* bw in MHz, return the channel count from the center channel to the
++ * the channel at the edge of the band
++ */
++static uint8
++center_chan_to_edge(uint bw)
++{
++	/* edge channels separated by BW - 10MHz on each side
++	 * delta from cf to edge is half of that,
++	 * MHz to channel num conversion is 5MHz/channel
++	 */
++	return (uint8)(((bw - 20) / 2) / 5);
++}
++
++/* return channel number of the low edge of the band
++ * given the center channel and BW
++ */
++static uint8
++channel_low_edge(uint center_ch, uint bw)
++{
++	return (uint8)(center_ch - center_chan_to_edge(bw));
++}
++
++/* return side band number given center channel and control channel
++ * return -1 on error
++ */
++static int
++channel_to_sb(uint center_ch, uint ctl_ch, uint bw)
++{
++	uint lowest = channel_low_edge(center_ch, bw);
++	uint sb;
++
++	if ((ctl_ch - lowest) % 4) {
++		/* bad ctl channel, not mult 4 */
++		return -1;
++	}
++
++	sb = ((ctl_ch - lowest) / 4);
++
++	/* sb must be a index to a 20MHz channel in range */
++	if (sb >= (bw / 20)) {
++		/* ctl_ch must have been too high for the center_ch */
++		return -1;
++	}
++
++	return sb;
++}
++
++/* return control channel given center channel and side band */
++static uint8
++channel_to_ctl_chan(uint center_ch, uint bw, uint sb)
++{
++	return (uint8)(channel_low_edge(center_ch, bw) + sb * 4);
++}
++
++/* return index of 80MHz channel from channel number
++ * return -1 on error
++ */
++static int
++channel_80mhz_to_id(uint ch)
++{
++	uint i;
++	for (i = 0; i < WF_NUM_5G_80M_CHANS; i ++) {
++		if (ch == wf_5g_80m_chans[i])
++			return i;
++	}
++
++	return -1;
++}
++
++/* wrapper function for wf_chspec_ntoa. In case of an error it puts
++ * the original chanspec in the output buffer, prepended with "invalid".
++ * Can be directly used in print routines as it takes care of null
++ */
++char *
++wf_chspec_ntoa_ex(chanspec_t chspec, char *buf)
++{
++	if (wf_chspec_ntoa(chspec, buf) == NULL)
++		snprintf(buf, CHANSPEC_STR_LEN, "invalid 0x%04x", chspec);
++	return buf;
++}
++
++/* given a chanspec and a string buffer, format the chanspec as a
++ * string, and return the original pointer a.
++ * Min buffer length must be CHANSPEC_STR_LEN.
++ * On error return NULL
++ */
++char *
++wf_chspec_ntoa(chanspec_t chspec, char *buf)
++{
++	const char *band;
++	uint ctl_chan;
++
++	if (wf_chspec_malformed(chspec))
++		return NULL;
++
++	band = "";
++
++	/* check for non-default band spec */
++	if ((CHSPEC_IS2G(chspec) && CHSPEC_CHANNEL(chspec) > CH_MAX_2G_CHANNEL) ||
++	    (CHSPEC_IS5G(chspec) && CHSPEC_CHANNEL(chspec) <= CH_MAX_2G_CHANNEL))
++		band = (CHSPEC_IS2G(chspec)) ? "2g" : "5g";
++
++	/* ctl channel */
++	ctl_chan = wf_chspec_ctlchan(chspec);
++
++	/* bandwidth and ctl sideband */
++	if (CHSPEC_IS20(chspec)) {
++		snprintf(buf, CHANSPEC_STR_LEN, "%s%d", band, ctl_chan);
++	} else if (!CHSPEC_IS8080(chspec)) {
++		const char *bw;
++		const char *sb = "";
++
++		bw = wf_chspec_bw_str[(chspec & WL_CHANSPEC_BW_MASK) >> WL_CHANSPEC_BW_SHIFT];
++
++#ifdef CHANSPEC_NEW_40MHZ_FORMAT
++		/* ctl sideband string if needed for 2g 40MHz */
++		if (CHSPEC_IS40(chspec) && CHSPEC_IS2G(chspec)) {
++			sb = CHSPEC_SB_UPPER(chspec) ? "u" : "l";
++		}
++
++		snprintf(buf, CHANSPEC_STR_LEN, "%s%d/%s%s", band, ctl_chan, bw, sb);
++#else
++		/* ctl sideband string instead of BW for 40MHz */
++		if (CHSPEC_IS40(chspec)) {
++			sb = CHSPEC_SB_UPPER(chspec) ? "u" : "l";
++			snprintf(buf, CHANSPEC_STR_LEN, "%s%d%s", band, ctl_chan, sb);
++		} else {
++			snprintf(buf, CHANSPEC_STR_LEN, "%s%d/%s", band, ctl_chan, bw);
++		}
++#endif /* CHANSPEC_NEW_40MHZ_FORMAT */
++
++	} else {
++		/* 80+80 */
++		uint chan1 = (chspec & WL_CHANSPEC_CHAN1_MASK) >> WL_CHANSPEC_CHAN1_SHIFT;
++		uint chan2 = (chspec & WL_CHANSPEC_CHAN2_MASK) >> WL_CHANSPEC_CHAN2_SHIFT;
++
++		/* convert to channel number */
++		chan1 = (chan1 < WF_NUM_5G_80M_CHANS) ? wf_5g_80m_chans[chan1] : 0;
++		chan2 = (chan2 < WF_NUM_5G_80M_CHANS) ? wf_5g_80m_chans[chan2] : 0;
++
++		/* Outputs a max of CHANSPEC_STR_LEN chars including '\0'  */
++		snprintf(buf, CHANSPEC_STR_LEN, "%d/80+80/%d-%d", ctl_chan, chan1, chan2);
++	}
++
++	return (buf);
++}
++
++static int
++read_uint(const char **p, unsigned int *num)
++{
++	unsigned long val;
++	char *endp = NULL;
++
++	val = strtoul(*p, &endp, 10);
++	/* if endp is the initial pointer value, then a number was not read */
++	if (endp == *p)
++		return 0;
++
++	/* advance the buffer pointer to the end of the integer string */
++	*p = endp;
++	/* return the parsed integer */
++	*num = (unsigned int)val;
++
++	return 1;
++}
++
++/* given a chanspec string, convert to a chanspec.
++ * On error return 0
++ */
++chanspec_t
++wf_chspec_aton(const char *a)
++{
++	chanspec_t chspec;
++	uint chspec_ch, chspec_band, bw, chspec_bw, chspec_sb;
++	uint num, ctl_ch;
++	uint ch1, ch2;
++	char c, sb_ul = '\0';
++	int i;
++
++	bw = 20;
++	chspec_sb = 0;
++	chspec_ch = ch1 = ch2 = 0;
++
++	/* parse channel num or band */
++	if (!read_uint(&a, &num))
++		return 0;
++	/* if we are looking at a 'g', then the first number was a band */
++	c = tolower((int)a[0]);
++	if (c == 'g') {
++		a++; /* consume the char */
++
++		/* band must be "2" or "5" */
++		if (num == 2)
++			chspec_band = WL_CHANSPEC_BAND_2G;
++		else if (num == 5)
++			chspec_band = WL_CHANSPEC_BAND_5G;
++		else
++			return 0;
++
++		/* read the channel number */
++		if (!read_uint(&a, &ctl_ch))
++			return 0;
++
++		c = tolower((int)a[0]);
++	}
++	else {
++		/* first number is channel, use default for band */
++		ctl_ch = num;
++		chspec_band = ((ctl_ch <= CH_MAX_2G_CHANNEL) ?
++		               WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G);
++	}
++
++	if (c == '\0') {
++		/* default BW of 20MHz */
++		chspec_bw = WL_CHANSPEC_BW_20;
++		goto done_read;
++	}
++
++	a ++; /* consume the 'u','l', or '/' */
++
++	/* check 'u'/'l' */
++	if (c == 'u' || c == 'l') {
++		sb_ul = c;
++		chspec_bw = WL_CHANSPEC_BW_40;
++		goto done_read;
++	}
++
++	/* next letter must be '/' */
++	if (c != '/')
++		return 0;
++
++	/* read bandwidth */
++	if (!read_uint(&a, &bw))
++		return 0;
++
++	/* convert to chspec value */
++	if (bw == 2) {
++		chspec_bw = WL_CHANSPEC_BW_2P5;
++	} else if (bw == 5) {
++		chspec_bw = WL_CHANSPEC_BW_5;
++	} else if (bw == 10) {
++		chspec_bw = WL_CHANSPEC_BW_10;
++	} else if (bw == 20) {
++		chspec_bw = WL_CHANSPEC_BW_20;
++	} else if (bw == 40) {
++		chspec_bw = WL_CHANSPEC_BW_40;
++	} else if (bw == 80) {
++		chspec_bw = WL_CHANSPEC_BW_80;
++	} else if (bw == 160) {
++		chspec_bw = WL_CHANSPEC_BW_160;
++	} else {
++		return 0;
++	}
++
++	/* So far we have <band>g<chan>/<bw>
++	 * Can now be followed by u/l if bw = 40,
++	 * or '+80' if bw = 80, to make '80+80' bw,
++	 * or '.5' if bw = 2.5 to make '2.5' bw .
++	 */
++
++	c = tolower((int)a[0]);
++
++	/* if we have a 2g/40 channel, we should have a l/u spec now */
++	if (chspec_band == WL_CHANSPEC_BAND_2G && bw == 40) {
++		if (c == 'u' || c == 'l') {
++			a ++; /* consume the u/l char */
++			sb_ul = c;
++			goto done_read;
++		}
++	}
++
++	/* check for 80+80 */
++	if (c == '+') {
++		/* 80+80 */
++		const char plus80[] = "80/";
++
++		/* must be looking at '+80/'
++		 * check and consume this string.
++		 */
++		chspec_bw = WL_CHANSPEC_BW_8080;
++
++		a ++; /* consume the char '+' */
++
++		/* consume the '80/' string */
++		for (i = 0; i < 3; i++) {
++			if (*a++ != plus80[i]) {
++				return 0;
++			}
++		}
++
++		/* read primary 80MHz channel */
++		if (!read_uint(&a, &ch1))
++			return 0;
++
++		/* must followed by '-' */
++		if (a[0] != '-')
++			return 0;
++		a ++; /* consume the char */
++
++		/* read secondary 80MHz channel */
++		if (!read_uint(&a, &ch2))
++			return 0;
++	} else if (c == '.') {
++		/* 2.5 */
++		/* must be looking at '.5'
++		 * check and consume this string.
++		 */
++		chspec_bw = WL_CHANSPEC_BW_2P5;
++
++		a ++; /* consume the char '.' */
++
++		/* consume the '5' string */
++		if (*a++ != '5') {
++			return 0;
++		}
++	}
++
++done_read:
++	/* skip trailing white space */
++	while (a[0] == ' ') {
++		a ++;
++	}
++
++	/* must be end of string */
++	if (a[0] != '\0')
++		return 0;
++
++	/* Now have all the chanspec string parts read;
++	 * chspec_band, ctl_ch, chspec_bw, sb_ul, ch1, ch2.
++	 * chspec_band and chspec_bw are chanspec values.
++	 * Need to convert ctl_ch, sb_ul, and ch1,ch2 into
++	 * a center channel (or two) and sideband.
++	 */
++
++	/* if a sb u/l string was given, just use that,
++	 * guaranteed to be bw = 40 by sting parse.
++	 */
++	if (sb_ul != '\0') {
++		if (sb_ul == 'l') {
++			chspec_ch = UPPER_20_SB(ctl_ch);
++			chspec_sb = WL_CHANSPEC_CTL_SB_LLL;
++		} else if (sb_ul == 'u') {
++			chspec_ch = LOWER_20_SB(ctl_ch);
++			chspec_sb = WL_CHANSPEC_CTL_SB_LLU;
++		}
++	}
++	/* if the bw is 20, center and sideband are trivial */
++	else if (BW_LE20(chspec_bw)) {
++		chspec_ch = ctl_ch;
++		chspec_sb = WL_CHANSPEC_CTL_SB_NONE;
++	}
++	/* if the bw is 40/80/160, not 80+80, a single method
++	 * can be used to to find the center and sideband
++	 */
++	else if (chspec_bw != WL_CHANSPEC_BW_8080) {
++		/* figure out ctl sideband based on ctl channel and bandwidth */
++		const uint8 *center_ch = NULL;
++		int num_ch = 0;
++		int sb = -1;
++
++		if (chspec_bw == WL_CHANSPEC_BW_40) {
++			center_ch = wf_5g_40m_chans;
++			num_ch = WF_NUM_5G_40M_CHANS;
++		} else if (chspec_bw == WL_CHANSPEC_BW_80) {
++			center_ch = wf_5g_80m_chans;
++			num_ch = WF_NUM_5G_80M_CHANS;
++		} else if (chspec_bw == WL_CHANSPEC_BW_160) {
++			center_ch = wf_5g_160m_chans;
++			num_ch = WF_NUM_5G_160M_CHANS;
++		} else {
++			return 0;
++		}
++
++		for (i = 0; i < num_ch; i ++) {
++			sb = channel_to_sb(center_ch[i], ctl_ch, bw);
++			if (sb >= 0) {
++				chspec_ch = center_ch[i];
++				chspec_sb = sb << WL_CHANSPEC_CTL_SB_SHIFT;
++				break;
++			}
++		}
++
++		/* check for no matching sb/center */
++		if (sb < 0) {
++			return 0;
++		}
++	}
++	/* Otherwise, bw is 80+80. Figure out channel pair and sb */
++	else {
++		int ch1_id = 0, ch2_id = 0;
++		int sb;
++
++		/* look up the channel ID for the specified channel numbers */
++		ch1_id = channel_80mhz_to_id(ch1);
++		ch2_id = channel_80mhz_to_id(ch2);
++
++		/* validate channels */
++		if (ch1_id < 0 || ch2_id < 0)
++			return 0;
++
++		/* combine 2 channel IDs in channel field of chspec */
++		chspec_ch = (((uint)ch1_id << WL_CHANSPEC_CHAN1_SHIFT) |
++		             ((uint)ch2_id << WL_CHANSPEC_CHAN2_SHIFT));
++
++		/* figure out primary 20 MHz sideband */
++
++		/* is the primary channel contained in the 1st 80MHz channel? */
++		sb = channel_to_sb(ch1, ctl_ch, bw);
++		if (sb < 0) {
++			/* no match for primary channel 'ctl_ch' in segment0 80MHz channel */
++			return 0;
++		}
++
++		chspec_sb = sb << WL_CHANSPEC_CTL_SB_SHIFT;
++	}
++
++	chspec = (chspec_ch | chspec_band | chspec_bw | chspec_sb);
++
++	if (wf_chspec_malformed(chspec))
++		return 0;
++
++	return chspec;
++}
++
++/*
++ * Verify the chanspec is using a legal set of parameters, i.e. that the
++ * chanspec specified a band, bw, ctl_sb and channel and that the
++ * combination could be legal given any set of circumstances.
++ * RETURNS: TRUE is the chanspec is malformed, false if it looks good.
++ */
++bool
++wf_chspec_malformed(chanspec_t chanspec)
++{
++	uint chspec_bw = CHSPEC_BW(chanspec);
++	uint chspec_ch = CHSPEC_CHANNEL(chanspec);
++
++	/* must be 2G or 5G band */
++	if (CHSPEC_IS2G(chanspec)) {
++		/* must be valid bandwidth */
++		if (!BW_LE40(chspec_bw)) {
++			return TRUE;
++		}
++	} else if (CHSPEC_IS5G(chanspec)) {
++		if (chspec_bw == WL_CHANSPEC_BW_8080) {
++			uint ch1_id, ch2_id;
++
++			/* channel IDs in 80+80 must be in range */
++			ch1_id = CHSPEC_CHAN1(chanspec);
++			ch2_id = CHSPEC_CHAN2(chanspec);
++			if (ch1_id >= WF_NUM_5G_80M_CHANS || ch2_id >= WF_NUM_5G_80M_CHANS)
++				return TRUE;
++
++		} else if (BW_LE160(chspec_bw)) {
++			if (chspec_ch > MAXCHANNEL) {
++				return TRUE;
++			}
++		} else {
++			/* invalid bandwidth */
++			return TRUE;
++		}
++	} else {
++		/* must be 2G or 5G band */
++		return TRUE;
++	}
++
++	/* side band needs to be consistent with bandwidth */
++	if (BW_LE20(chspec_bw)) {
++		if (CHSPEC_CTL_SB(chanspec) != WL_CHANSPEC_CTL_SB_LLL)
++			return TRUE;
++	} else if (chspec_bw == WL_CHANSPEC_BW_40) {
++		if (CHSPEC_CTL_SB(chanspec) > WL_CHANSPEC_CTL_SB_LLU)
++			return TRUE;
++	} else if (chspec_bw == WL_CHANSPEC_BW_80 ||
++	           chspec_bw == WL_CHANSPEC_BW_8080) {
++		if (CHSPEC_CTL_SB(chanspec) > WL_CHANSPEC_CTL_SB_LUU)
++			return TRUE;
++	}
++	else if (chspec_bw == WL_CHANSPEC_BW_160) {
++		ASSERT(CHSPEC_CTL_SB(chanspec) <= WL_CHANSPEC_CTL_SB_UUU);
++	}
++	return FALSE;
++}
++
++/*
++ * Verify the chanspec specifies a valid channel according to 802.11.
++ * RETURNS: TRUE if the chanspec is a valid 802.11 channel
++ */
++bool
++wf_chspec_valid(chanspec_t chanspec)
++{
++	uint chspec_bw = CHSPEC_BW(chanspec);
++	uint chspec_ch = CHSPEC_CHANNEL(chanspec);
++
++	if (wf_chspec_malformed(chanspec))
++		return FALSE;
++
++	if (CHSPEC_IS2G(chanspec)) {
++		/* must be valid bandwidth and channel range */
++		if (BW_LE20(chspec_bw)) {
++			if (chspec_ch >= 1 && chspec_ch <= 14)
++				return TRUE;
++		} else if (chspec_bw == WL_CHANSPEC_BW_40) {
++			if (chspec_ch >= 3 && chspec_ch <= 11)
++				return TRUE;
++		}
++	} else if (CHSPEC_IS5G(chanspec)) {
++		if (chspec_bw == WL_CHANSPEC_BW_8080) {
++			uint16 ch1, ch2;
++
++			ch1 = wf_5g_80m_chans[CHSPEC_CHAN1(chanspec)];
++			ch2 = wf_5g_80m_chans[CHSPEC_CHAN2(chanspec)];
++
++			/* the two channels must be separated by more than 80MHz by VHT req */
++			if ((ch2 > ch1 + CH_80MHZ_APART) ||
++			    (ch1 > ch2 + CH_80MHZ_APART))
++				return TRUE;
++		} else {
++			const uint8 *center_ch;
++			uint num_ch, i;
++
++			if (BW_LE40(chspec_bw)) {
++				center_ch = wf_5g_40m_chans;
++				num_ch = WF_NUM_5G_40M_CHANS;
++			} else if (chspec_bw == WL_CHANSPEC_BW_80) {
++				center_ch = wf_5g_80m_chans;
++				num_ch = WF_NUM_5G_80M_CHANS;
++			} else if (chspec_bw == WL_CHANSPEC_BW_160) {
++				center_ch = wf_5g_160m_chans;
++				num_ch = WF_NUM_5G_160M_CHANS;
++			} else {
++				/* invalid bandwidth */
++				return FALSE;
++			}
++
++			/* check for a valid center channel */
++			if (BW_LE20(chspec_bw)) {
++				/* We don't have an array of legal 20MHz 5G channels, but they are
++				 * each side of the legal 40MHz channels.  Check the chanspec
++				 * channel against either side of the 40MHz channels.
++				 */
++				for (i = 0; i < num_ch; i ++) {
++					if (chspec_ch == (uint)LOWER_20_SB(center_ch[i]) ||
++					    chspec_ch == (uint)UPPER_20_SB(center_ch[i]))
++						break; /* match found */
++				}
++
++				if (i == num_ch) {
++					/* check for channel 165 which is not the side band
++					 * of 40MHz 5G channel
++					 */
++					if (chspec_ch == 165)
++						i = 0;
++
++					/* check for legacy JP channels on failure */
++					if (chspec_ch == 34 || chspec_ch == 38 ||
++					    chspec_ch == 42 || chspec_ch == 46)
++						i = 0;
++				}
++			} else {
++				/* check the chanspec channel to each legal channel */
++				for (i = 0; i < num_ch; i ++) {
++					if (chspec_ch == center_ch[i])
++						break; /* match found */
++				}
++			}
++
++			if (i < num_ch) {
++				/* match found */
++				return TRUE;
++			}
++		}
++	}
++
++	return FALSE;
++}
++
++/*
++ * This function returns the channel number that control traffic is being sent on, for 20MHz
++ * channels this is just the channel number, for 40MHZ, 80MHz, 160MHz channels it is the 20MHZ
++ * sideband depending on the chanspec selected
++ */
++uint8
++wf_chspec_ctlchan(chanspec_t chspec)
++{
++	uint center_chan;
++	uint bw_mhz;
++	uint sb;
++
++	ASSERT(!wf_chspec_malformed(chspec));
++
++	/* Is there a sideband ? */
++	if (CHSPEC_BW_LE20(chspec)) {
++		return CHSPEC_CHANNEL(chspec);
++	} else {
++		sb = CHSPEC_CTL_SB(chspec) >> WL_CHANSPEC_CTL_SB_SHIFT;
++
++		if (CHSPEC_IS8080(chspec)) {
++			/* For an 80+80 MHz channel, the sideband 'sb' field is an 80 MHz sideband
++			 * (LL, LU, UL, LU) for the 80 MHz frequency segment 0.
++			 */
++			uint chan_id = CHSPEC_CHAN1(chspec);
++
++			bw_mhz = 80;
++
++			/* convert from channel index to channel number */
++			center_chan = wf_5g_80m_chans[chan_id];
++		}
++		else {
++			bw_mhz = bw_chspec_to_mhz(chspec);
++			center_chan = CHSPEC_CHANNEL(chspec) >> WL_CHANSPEC_CHAN_SHIFT;
++		}
++
++		return (channel_to_ctl_chan(center_chan, bw_mhz, sb));
++	}
++}
++
++/* given a chanspec, return the bandwidth string */
++const char *
++wf_chspec_to_bw_str(chanspec_t chspec)
++{
++	return wf_chspec_bw_str[(CHSPEC_BW(chspec) >> WL_CHANSPEC_BW_SHIFT)];
++}
++
++/*
++ * This function returns the chanspec of the control channel of a given chanspec
++ */
++chanspec_t
++wf_chspec_ctlchspec(chanspec_t chspec)
++{
++	chanspec_t ctl_chspec = chspec;
++	uint8 ctl_chan;
++
++	ASSERT(!wf_chspec_malformed(chspec));
++
++	/* Is there a sideband ? */
++	if (!CHSPEC_BW_LE20(chspec)) {
++		ctl_chan = wf_chspec_ctlchan(chspec);
++		ctl_chspec = ctl_chan | WL_CHANSPEC_BW_20;
++		ctl_chspec |= CHSPEC_BAND(chspec);
++	}
++	return ctl_chspec;
++}
++
++/* return chanspec given control channel and bandwidth
++ * return 0 on error
++ */
++uint16
++wf_channel2chspec(uint ctl_ch, uint bw)
++{
++	uint16 chspec;
++	const uint8 *center_ch = NULL;
++	int num_ch = 0;
++	int sb = -1;
++	int i = 0;
++
++	chspec = ((ctl_ch <= CH_MAX_2G_CHANNEL) ? WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G);
++
++	chspec |= bw;
++
++	if (bw == WL_CHANSPEC_BW_40) {
++		center_ch = wf_5g_40m_chans;
++		num_ch = WF_NUM_5G_40M_CHANS;
++		bw = 40;
++	} else if (bw == WL_CHANSPEC_BW_80) {
++		center_ch = wf_5g_80m_chans;
++		num_ch = WF_NUM_5G_80M_CHANS;
++		bw = 80;
++	} else if (bw == WL_CHANSPEC_BW_160) {
++		center_ch = wf_5g_160m_chans;
++		num_ch = WF_NUM_5G_160M_CHANS;
++		bw = 160;
++	} else if (BW_LE20(bw)) {
++		chspec |= ctl_ch;
++		return chspec;
++	} else {
++		return 0;
++	}
++
++	for (i = 0; i < num_ch; i ++) {
++		sb = channel_to_sb(center_ch[i], ctl_ch, bw);
++		if (sb >= 0) {
++			chspec |= center_ch[i];
++			chspec |= (sb << WL_CHANSPEC_CTL_SB_SHIFT);
++			break;
++		}
++	}
++
++	/* check for no matching sb/center */
++	if (sb < 0) {
++		return 0;
++	}
++
++	return chspec;
++}
++
++/*
++ * This function returns the chanspec for the primary 40MHz of an 80MHz channel.
++ * The control sideband specifies the same 20MHz channel that the 80MHz channel is using
++ * as the primary 20MHz channel.
++ */
++extern chanspec_t wf_chspec_primary40_chspec(chanspec_t chspec)
++{
++	chanspec_t chspec40 = chspec;
++	uint center_chan;
++	uint sb;
++
++	ASSERT(!wf_chspec_malformed(chspec));
++
++	/* if the chanspec is > 80MHz, use the helper routine to find the primary 80 MHz channel */
++	if (CHSPEC_IS8080(chspec) || CHSPEC_IS160(chspec)) {
++		chspec = wf_chspec_primary80_chspec(chspec);
++	}
++
++	/* determine primary 40 MHz sub-channel of an 80 MHz chanspec */
++	if (CHSPEC_IS80(chspec)) {
++		center_chan = CHSPEC_CHANNEL(chspec);
++		sb = CHSPEC_CTL_SB(chspec);
++
++		if (sb < WL_CHANSPEC_CTL_SB_UL) {
++			/* Primary 40MHz is on lower side */
++			center_chan -= CH_20MHZ_APART;
++			/* sideband bits are the same for LL/LU and L/U */
++		} else {
++			/* Primary 40MHz is on upper side */
++			center_chan += CH_20MHZ_APART;
++			/* sideband bits need to be adjusted by UL offset */
++			sb -= WL_CHANSPEC_CTL_SB_UL;
++		}
++
++		/* Create primary 40MHz chanspec */
++		chspec40 = (WL_CHANSPEC_BAND_5G | WL_CHANSPEC_BW_40 |
++		            sb | center_chan);
++	}
++
++	return chspec40;
++}
++
++/*
++ * Return the channel number for a given frequency and base frequency.
++ * The returned channel number is relative to the given base frequency.
++ * If the given base frequency is zero, a base frequency of 5 GHz is assumed for
++ * frequencies from 5 - 6 GHz, and 2.407 GHz is assumed for 2.4 - 2.5 GHz.
++ *
++ * Frequency is specified in MHz.
++ * The base frequency is specified as (start_factor * 500 kHz).
++ * Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_5_G are defined for
++ * 2.4 GHz and 5 GHz bands.
++ *
++ * The returned channel will be in the range [1, 14] in the 2.4 GHz band
++ * and [0, 200] otherwise.
++ * -1 is returned if the start_factor is WF_CHAN_FACTOR_2_4_G and the
++ * frequency is not a 2.4 GHz channel, or if the frequency is not and even
++ * multiple of 5 MHz from the base frequency to the base plus 1 GHz.
++ *
++ * Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
++ */
++int
++wf_mhz2channel(uint freq, uint start_factor)
++{
++	int ch = -1;
++	uint base;
++	int offset;
++
++	/* take the default channel start frequency */
++	if (start_factor == 0) {
++		if (freq >= 2400 && freq <= 2500)
++			start_factor = WF_CHAN_FACTOR_2_4_G;
++		else if (freq >= 5000 && freq <= 6000)
++			start_factor = WF_CHAN_FACTOR_5_G;
++	}
++
++	if (freq == 2484 && start_factor == WF_CHAN_FACTOR_2_4_G)
++		return 14;
++
++	base = start_factor / 2;
++
++	/* check that the frequency is in 1GHz range of the base */
++	if ((freq < base) || (freq > base + 1000))
++		return -1;
++
++	offset = freq - base;
++	ch = offset / 5;
++
++	/* check that frequency is a 5MHz multiple from the base */
++	if (offset != (ch * 5))
++		return -1;
++
++	/* restricted channel range check for 2.4G */
++	if (start_factor == WF_CHAN_FACTOR_2_4_G && (ch < 1 || ch > 13))
++		return -1;
++
++	return ch;
++}
++
++/*
++ * Return the center frequency in MHz of the given channel and base frequency.
++ * The channel number is interpreted relative to the given base frequency.
++ *
++ * The valid channel range is [1, 14] in the 2.4 GHz band and [0, 200] otherwise.
++ * The base frequency is specified as (start_factor * 500 kHz).
++ * Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_4_G, and WF_CHAN_FACTOR_5_G
++ * are defined for 2.4 GHz, 4 GHz, and 5 GHz bands.
++ * The channel range of [1, 14] is only checked for a start_factor of
++ * WF_CHAN_FACTOR_2_4_G (4814 = 2407 * 2).
++ * Odd start_factors produce channels on .5 MHz boundaries, in which case
++ * the answer is rounded down to an integral MHz.
++ * -1 is returned for an out of range channel.
++ *
++ * Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
++ */
++int
++wf_channel2mhz(uint ch, uint start_factor)
++{
++	int freq;
++
++	if ((start_factor == WF_CHAN_FACTOR_2_4_G && (ch < 1 || ch > 14)) ||
++	    (ch > 200))
++		freq = -1;
++	else if ((start_factor == WF_CHAN_FACTOR_2_4_G) && (ch == 14))
++		freq = 2484;
++	else
++		freq = ch * 5 + start_factor / 2;
++
++	return freq;
++}
++
++static const uint16 sidebands[] = {
++	WL_CHANSPEC_CTL_SB_LLL, WL_CHANSPEC_CTL_SB_LLU,
++	WL_CHANSPEC_CTL_SB_LUL, WL_CHANSPEC_CTL_SB_LUU,
++	WL_CHANSPEC_CTL_SB_ULL, WL_CHANSPEC_CTL_SB_ULU,
++	WL_CHANSPEC_CTL_SB_UUL, WL_CHANSPEC_CTL_SB_UUU
++};
++
++/*
++ * Returns the chanspec 80Mhz channel corresponding to the following input
++ * parameters
++ *
++ *	primary_channel - primary 20Mhz channel
++ *	center_channel   - center frequecny of the 80Mhz channel
++ *
++ * The center_channel can be one of {42, 58, 106, 122, 138, 155}
++ *
++ * returns INVCHANSPEC in case of error
++ */
++chanspec_t
++wf_chspec_80(uint8 center_channel, uint8 primary_channel)
++{
++
++	chanspec_t chanspec = INVCHANSPEC;
++	chanspec_t chanspec_cur;
++	uint i;
++
++	for (i = 0; i < WF_NUM_SIDEBANDS_80MHZ; i++) {
++		chanspec_cur = CH80MHZ_CHSPEC(center_channel, sidebands[i]);
++		if (primary_channel == wf_chspec_ctlchan(chanspec_cur)) {
++			chanspec = chanspec_cur;
++			break;
++		}
++	}
++	/* If the loop ended early, we are good, otherwise we did not
++	* find a 80MHz chanspec with the given center_channel that had a primary channel
++	*matching the given primary_channel.
++	*/
++	return chanspec;
++}
++
++/*
++ * Returns the 80+80 chanspec corresponding to the following input parameters
++ *
++ *    primary_20mhz - Primary 20 MHz channel
++ *    chan0 - center channel number of one frequency segment
++ *    chan1 - center channel number of the other frequency segment
++ *
++ * Parameters chan0 and chan1 are channel numbers in {42, 58, 106, 122, 138, 155}.
++ * The primary channel must be contained in one of the 80MHz channels. This routine
++ * will determine which frequency segment is the primary 80 MHz segment.
++ *
++ * Returns INVCHANSPEC in case of error.
++ *
++ * Refer to IEEE802.11ac section 22.3.14 "Channelization".
++ */
++chanspec_t
++wf_chspec_get8080_chspec(uint8 primary_20mhz, uint8 chan0, uint8 chan1)
++{
++	int sb = 0;
++	uint16 chanspec = 0;
++	int chan0_id = 0, chan1_id = 0;
++	int seg0, seg1;
++
++	chan0_id = channel_80mhz_to_id(chan0);
++	chan1_id = channel_80mhz_to_id(chan1);
++
++	/* make sure the channel numbers were valid */
++	if (chan0_id == -1 || chan1_id == -1)
++		return INVCHANSPEC;
++
++	/* does the primary channel fit with the 1st 80MHz channel ? */
++	sb = channel_to_sb(chan0, primary_20mhz, 80);
++	if (sb >= 0) {
++		/* yes, so chan0 is frequency segment 0, and chan1 is seg 1 */
++		seg0 = chan0_id;
++		seg1 = chan1_id;
++	} else {
++		/* no, so does the primary channel fit with the 2nd 80MHz channel ? */
++		sb = channel_to_sb(chan1, primary_20mhz, 80);
++		if (sb < 0) {
++			/* no match for ctl_ch to either 80MHz center channel */
++			return INVCHANSPEC;
++		}
++		/* swapped, so chan1 is frequency segment 0, and chan0 is seg 1 */
++		seg0 = chan1_id;
++		seg1 = chan0_id;
++	}
++
++	chanspec = ((seg0 << WL_CHANSPEC_CHAN1_SHIFT) |
++	            (seg1 << WL_CHANSPEC_CHAN2_SHIFT) |
++	            (sb << WL_CHANSPEC_CTL_SB_SHIFT) |
++	            WL_CHANSPEC_BW_8080 |
++	            WL_CHANSPEC_BAND_5G);
++
++	return chanspec;
++}
++
++/*
++ * This function returns the 80Mhz channel for the given id.
++ */
++static uint8
++wf_chspec_get80Mhz_ch(uint8 chan_80Mhz_id)
++{
++	if (chan_80Mhz_id < WF_NUM_5G_80M_CHANS)
++		return wf_5g_80m_chans[chan_80Mhz_id];
++
++	return 0;
++}
++
++/*
++ * Returns the primary 80 Mhz channel for the provided chanspec
++ *
++ *    chanspec - Input chanspec for which the 80MHz primary channel has to be retrieved
++ *
++ *  returns -1 in case the provided channel is 20/40 Mhz chanspec
++ */
++
++uint8
++wf_chspec_primary80_channel(chanspec_t chanspec)
++{
++	uint8 primary80_chan;
++
++	if (CHSPEC_IS80(chanspec))	{
++		primary80_chan = CHSPEC_CHANNEL(chanspec);
++	}
++	else if (CHSPEC_IS8080(chanspec)) {
++		/* Channel ID 1 corresponds to frequency segment 0, the primary 80 MHz segment */
++		primary80_chan = wf_chspec_get80Mhz_ch(CHSPEC_CHAN1(chanspec));
++	}
++	else if (CHSPEC_IS160(chanspec)) {
++		uint8 center_chan = CHSPEC_CHANNEL(chanspec);
++		uint sb = CHSPEC_CTL_SB(chanspec) >> WL_CHANSPEC_CTL_SB_SHIFT;
++
++		/* based on the sb value primary 80 channel can be retrieved
++		 * if sb is in range 0 to 3 the lower band is the 80Mhz primary band
++		 */
++		if (sb < 4) {
++			primary80_chan = center_chan - CH_40MHZ_APART;
++		}
++		/* if sb is in range 4 to 7 the upper band is the 80Mhz primary band */
++		else
++		{
++			primary80_chan = center_chan + CH_40MHZ_APART;
++		}
++	}
++	else {
++		/* for 20 and 40 Mhz */
++		primary80_chan = -1;
++	}
++	return primary80_chan;
++}
++
++/*
++ * Returns the secondary 80 Mhz channel for the provided chanspec
++ *
++ *    chanspec - Input chanspec for which the 80MHz secondary channel has to be retrieved
++ *
++ *  returns -1 in case the provided channel is 20/40/80 Mhz chanspec
++ */
++uint8
++wf_chspec_secondary80_channel(chanspec_t chanspec)
++{
++	uint8 secondary80_chan;
++
++	if (CHSPEC_IS8080(chanspec)) {
++		secondary80_chan = wf_chspec_get80Mhz_ch(CHSPEC_CHAN2(chanspec));
++	}
++	else if (CHSPEC_IS160(chanspec)) {
++		uint8 center_chan = CHSPEC_CHANNEL(chanspec);
++		uint sb = CHSPEC_CTL_SB(chanspec) >> WL_CHANSPEC_CTL_SB_SHIFT;
++
++		/* based on the sb value  secondary 80 channel can be retrieved
++		 * if sb is in range 0 to 3 upper band is the secondary 80Mhz band
++		 */
++		if (sb < 4) {
++			secondary80_chan = center_chan + CH_40MHZ_APART;
++		}
++		/* if sb is in range 4 to 7 the lower band is the secondary 80Mhz band */
++		else
++		{
++			secondary80_chan = center_chan - CH_40MHZ_APART;
++		}
++	}
++	else {
++		/* for 20, 40, and 80 Mhz */
++		secondary80_chan = -1;
++	}
++	return secondary80_chan;
++}
++
++/*
++ * This function returns the chanspec for the primary 80MHz of an 160MHz or 80+80 channel.
++ *
++ *    chanspec - Input chanspec for which the primary 80Mhz chanspec has to be retreived
++ *
++ *  returns the input chanspec in case the provided chanspec is an 80 MHz chanspec
++ *  returns INVCHANSPEC in case the provided channel is 20/40 MHz chanspec
++ */
++chanspec_t
++wf_chspec_primary80_chspec(chanspec_t chspec)
++{
++	chanspec_t chspec80;
++	uint center_chan;
++	uint sb;
++
++	ASSERT(!wf_chspec_malformed(chspec));
++	if (CHSPEC_IS80(chspec)) {
++		chspec80 = chspec;
++	}
++	else if (CHSPEC_IS8080(chspec)) {
++
++		/* Channel ID 1 corresponds to frequency segment 0, the primary 80 MHz segment */
++		center_chan = wf_chspec_get80Mhz_ch(CHSPEC_CHAN1(chspec));
++
++		sb = CHSPEC_CTL_SB(chspec);
++
++		/* Create primary 80MHz chanspec */
++		chspec80 = (WL_CHANSPEC_BAND_5G | WL_CHANSPEC_BW_80 | sb | center_chan);
++	}
++	else if (CHSPEC_IS160(chspec)) {
++		center_chan = CHSPEC_CHANNEL(chspec);
++		sb = CHSPEC_CTL_SB(chspec);
++
++		if (sb < WL_CHANSPEC_CTL_SB_ULL) {
++			/* Primary 80MHz is on lower side */
++			center_chan -= CH_40MHZ_APART;
++		}
++		else {
++			/* Primary 80MHz is on upper side */
++			center_chan += CH_40MHZ_APART;
++			sb -= WL_CHANSPEC_CTL_SB_ULL;
++		}
++		/* Create primary 80MHz chanspec */
++		chspec80 = (WL_CHANSPEC_BAND_5G | WL_CHANSPEC_BW_80 | sb | center_chan);
++	}
++	else {
++		chspec80 = INVCHANSPEC;
++	}
++
++	return chspec80;
++}
++
++#ifdef WL11AC_80P80
++uint8
++wf_chspec_channel(chanspec_t chspec)
++{
++	if (CHSPEC_IS8080(chspec)) {
++		return wf_chspec_primary80_channel(chspec);
++	}
++	else {
++		return ((uint8)((chspec) & WL_CHANSPEC_CHAN_MASK));
++	}
++}
++#endif /* WL11AC_80P80 */
++
++/* This routine returns the chanspec for a given operating class and
++ * channel number
++ */
++chanspec_t
++wf_channel_create_chspec_frm_opclass(uint8 opclass, uint8 channel)
++{
++	chanspec_t chanspec = 0;
++	uint16 opclass_info = 0;
++	uint16 lookupindex = 0;
++	switch (opclass) {
++		case 115:
++			lookupindex = 1;
++			break;
++		case 124:
++			lookupindex = 3;
++			break;
++		case 125:
++			lookupindex = 5;
++			break;
++		case 81:
++			lookupindex = 12;
++			break;
++		case 116:
++			lookupindex = 22;
++			break;
++		case 119:
++			lookupindex = 23;
++			break;
++		case 126:
++			lookupindex = 25;
++			break;
++		case 83:
++			lookupindex = 32;
++			break;
++		case 84:
++			lookupindex = 33;
++			break;
++		default:
++			lookupindex = 12;
++	}
++
++	if (lookupindex < 33) {
++		opclass_info = opclass_data[lookupindex-1];
++	}
++	else {
++		opclass_info = opclass_data[11];
++	}
++	chanspec = opclass_info | (uint16)channel;
++	return chanspec;
++}
++
++/* This routine returns the opclass for a given chanspec */
++int
++wf_channel_create_opclass_frm_chspec(chanspec_t chspec)
++{
++	BCM_REFERENCE(chspec);
++	/* TODO: Implement this function ! */
++	return 12; /* opclass 12 for basic 2G channels */
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/bcmwifi_channels.h b/module_drivers/drivers/net/wireless/bcmdhd/bcmwifi_channels.h
+new file mode 100644
+index 000000000..28c6e2739
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/bcmwifi_channels.h
+@@ -0,0 +1,645 @@
++/*
++ * Misc utility routines for WL and Apps
++ * This header file housing the define and function prototype use by
++ * both the wl driver, tools & Apps.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmwifi_channels.h 612483 2016-01-14 03:44:27Z $
++ */
++
++#ifndef	_bcmwifi_channels_h_
++#define	_bcmwifi_channels_h_
++
++
++/* A chanspec holds the channel number, band, bandwidth and control sideband */
++typedef uint16 chanspec_t;
++
++/* channel defines */
++#define CH_UPPER_SB			0x01
++#define CH_LOWER_SB			0x02
++#define CH_EWA_VALID			0x04
++#define CH_80MHZ_APART			16
++#define CH_40MHZ_APART			8
++#define CH_20MHZ_APART			4
++#define CH_10MHZ_APART			2
++#define CH_5MHZ_APART			1	/* 2G band channels are 5 Mhz apart */
++#define CH_MAX_2G_CHANNEL		14	/* Max channel in 2G band */
++
++/* maximum # channels the s/w supports */
++#define MAXCHANNEL		224	/* max # supported channels. The max channel no is above,
++					 * this is that + 1 rounded up to a multiple of NBBY (8).
++					 * DO NOT MAKE it > 255: channels are uint8's all over
++					 */
++#define MAXCHANNEL_NUM	(MAXCHANNEL - 1)	/* max channel number */
++
++/* channel bitvec */
++typedef struct {
++	uint8   vec[MAXCHANNEL/8];   /* bitvec of channels */
++} chanvec_t;
++
++/* make sure channel num is within valid range */
++#define CH_NUM_VALID_RANGE(ch_num) ((ch_num) > 0 && (ch_num) <= MAXCHANNEL_NUM)
++
++#define CHSPEC_CTLOVLP(sp1, sp2, sep)	\
++	(ABS(wf_chspec_ctlchan(sp1) - wf_chspec_ctlchan(sp2)) < (sep))
++
++/* All builds use the new 11ac ratespec/chanspec */
++#undef  D11AC_IOTYPES
++#define D11AC_IOTYPES
++
++#define WL_CHANSPEC_CHAN_MASK		0x00ff
++#define WL_CHANSPEC_CHAN_SHIFT		0
++#define WL_CHANSPEC_CHAN1_MASK		0x000f
++#define WL_CHANSPEC_CHAN1_SHIFT		0
++#define WL_CHANSPEC_CHAN2_MASK		0x00f0
++#define WL_CHANSPEC_CHAN2_SHIFT		4
++
++#define WL_CHANSPEC_CTL_SB_MASK		0x0700
++#define WL_CHANSPEC_CTL_SB_SHIFT	8
++#define WL_CHANSPEC_CTL_SB_LLL		0x0000
++#define WL_CHANSPEC_CTL_SB_LLU		0x0100
++#define WL_CHANSPEC_CTL_SB_LUL		0x0200
++#define WL_CHANSPEC_CTL_SB_LUU		0x0300
++#define WL_CHANSPEC_CTL_SB_ULL		0x0400
++#define WL_CHANSPEC_CTL_SB_ULU		0x0500
++#define WL_CHANSPEC_CTL_SB_UUL		0x0600
++#define WL_CHANSPEC_CTL_SB_UUU		0x0700
++#define WL_CHANSPEC_CTL_SB_LL		WL_CHANSPEC_CTL_SB_LLL
++#define WL_CHANSPEC_CTL_SB_LU		WL_CHANSPEC_CTL_SB_LLU
++#define WL_CHANSPEC_CTL_SB_UL		WL_CHANSPEC_CTL_SB_LUL
++#define WL_CHANSPEC_CTL_SB_UU		WL_CHANSPEC_CTL_SB_LUU
++#define WL_CHANSPEC_CTL_SB_L		WL_CHANSPEC_CTL_SB_LLL
++#define WL_CHANSPEC_CTL_SB_U		WL_CHANSPEC_CTL_SB_LLU
++#define WL_CHANSPEC_CTL_SB_LOWER	WL_CHANSPEC_CTL_SB_LLL
++#define WL_CHANSPEC_CTL_SB_UPPER	WL_CHANSPEC_CTL_SB_LLU
++#define WL_CHANSPEC_CTL_SB_NONE		WL_CHANSPEC_CTL_SB_LLL
++
++#define WL_CHANSPEC_BW_MASK		0x3800
++#define WL_CHANSPEC_BW_SHIFT		11
++#define WL_CHANSPEC_BW_5		0x0000
++#define WL_CHANSPEC_BW_10		0x0800
++#define WL_CHANSPEC_BW_20		0x1000
++#define WL_CHANSPEC_BW_40		0x1800
++#define WL_CHANSPEC_BW_80		0x2000
++#define WL_CHANSPEC_BW_160		0x2800
++#define WL_CHANSPEC_BW_8080		0x3000
++#define WL_CHANSPEC_BW_2P5		0x3800
++
++#define WL_CHANSPEC_BAND_MASK		0xc000
++#define WL_CHANSPEC_BAND_SHIFT		14
++#define WL_CHANSPEC_BAND_2G		0x0000
++#define WL_CHANSPEC_BAND_3G		0x4000
++#define WL_CHANSPEC_BAND_4G		0x8000
++#define WL_CHANSPEC_BAND_5G		0xc000
++#define INVCHANSPEC			255
++#define MAX_CHANSPEC				0xFFFF
++
++#define WL_CHANNEL_BAND(ch) (((ch) <= CH_MAX_2G_CHANNEL) ? \
++	WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G)
++
++/* channel defines */
++#define LOWER_20_SB(channel)		(((channel) > CH_10MHZ_APART) ? \
++					((channel) - CH_10MHZ_APART) : 0)
++#define UPPER_20_SB(channel)		(((channel) < (MAXCHANNEL - CH_10MHZ_APART)) ? \
++					((channel) + CH_10MHZ_APART) : 0)
++
++#define LL_20_SB(channel) (((channel) > 3 * CH_10MHZ_APART) ? ((channel) - 3 * CH_10MHZ_APART) : 0)
++#define UU_20_SB(channel) 	(((channel) < (MAXCHANNEL - 3 * CH_10MHZ_APART)) ? \
++				((channel) + 3 * CH_10MHZ_APART) : 0)
++#define LU_20_SB(channel) LOWER_20_SB(channel)
++#define UL_20_SB(channel) UPPER_20_SB(channel)
++
++#define LOWER_40_SB(channel)		((channel) - CH_20MHZ_APART)
++#define UPPER_40_SB(channel)		((channel) + CH_20MHZ_APART)
++#define CHSPEC_WLCBANDUNIT(chspec)	(CHSPEC_IS5G(chspec) ? BAND_5G_INDEX : BAND_2G_INDEX)
++#define CH20MHZ_CHSPEC(channel)		(chanspec_t)((chanspec_t)(channel) | WL_CHANSPEC_BW_20 | \
++					(((channel) <= CH_MAX_2G_CHANNEL) ? \
++					WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
++#define CH2P5MHZ_CHSPEC(channel)	(chanspec_t)((chanspec_t)(channel) | WL_CHANSPEC_BW_2P5 | \
++						(((channel) <= CH_MAX_2G_CHANNEL) ? \
++						WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
++#define CH5MHZ_CHSPEC(channel)		(chanspec_t)((chanspec_t)(channel) | WL_CHANSPEC_BW_5 | \
++						(((channel) <= CH_MAX_2G_CHANNEL) ? \
++						WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
++#define CH10MHZ_CHSPEC(channel)		(chanspec_t)((chanspec_t)(channel) | WL_CHANSPEC_BW_10 | \
++						(((channel) <= CH_MAX_2G_CHANNEL) ? \
++						WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
++#define NEXT_20MHZ_CHAN(channel)	(((channel) < (MAXCHANNEL - CH_20MHZ_APART)) ? \
++					((channel) + CH_20MHZ_APART) : 0)
++#define CH40MHZ_CHSPEC(channel, ctlsb)	(chanspec_t) \
++					((channel) | (ctlsb) | WL_CHANSPEC_BW_40 | \
++					((channel) <= CH_MAX_2G_CHANNEL ? WL_CHANSPEC_BAND_2G : \
++					WL_CHANSPEC_BAND_5G))
++#define CH80MHZ_CHSPEC(channel, ctlsb)	(chanspec_t) \
++					((channel) | (ctlsb) | \
++					 WL_CHANSPEC_BW_80 | WL_CHANSPEC_BAND_5G)
++#define CH160MHZ_CHSPEC(channel, ctlsb)	(chanspec_t) \
++					((channel) | (ctlsb) | \
++					 WL_CHANSPEC_BW_160 | WL_CHANSPEC_BAND_5G)
++#define CHBW_CHSPEC(bw, channel)	(chanspec_t)((chanspec_t)(channel) | (bw) | \
++							(((channel) <= CH_MAX_2G_CHANNEL) ? \
++							WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
++
++/* simple MACROs to get different fields of chanspec */
++#ifdef WL11AC_80P80
++#define CHSPEC_CHANNEL(chspec)	wf_chspec_channel(chspec)
++#else
++#define CHSPEC_CHANNEL(chspec)	((uint8)((chspec) & WL_CHANSPEC_CHAN_MASK))
++#endif
++#define CHSPEC_CHAN1(chspec)	((chspec) & WL_CHANSPEC_CHAN1_MASK) >> WL_CHANSPEC_CHAN1_SHIFT
++#define CHSPEC_CHAN2(chspec)	((chspec) & WL_CHANSPEC_CHAN2_MASK) >> WL_CHANSPEC_CHAN2_SHIFT
++#define CHSPEC_BAND(chspec)		((chspec) & WL_CHANSPEC_BAND_MASK)
++#define CHSPEC_CTL_SB(chspec)	((chspec) & WL_CHANSPEC_CTL_SB_MASK)
++#define CHSPEC_BW(chspec)		((chspec) & WL_CHANSPEC_BW_MASK)
++
++#ifdef WL11N_20MHZONLY
++#ifdef WL11ULB
++#define CHSPEC_IS2P5(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_2P5)
++#define CHSPEC_IS5(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_5)
++#define CHSPEC_IS10(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_10)
++#else
++#define CHSPEC_IS2P5(chspec)	0
++#define CHSPEC_IS5(chspec)	0
++#define CHSPEC_IS10(chspec)	0
++#endif
++#define CHSPEC_IS20(chspec)	1
++#define CHSPEC_IS20_2G(chspec)	((((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_20) && \
++								CHSPEC_IS2G(chspec))
++#ifndef CHSPEC_IS40
++#define CHSPEC_IS40(chspec)	0
++#endif
++#ifndef CHSPEC_IS80
++#define CHSPEC_IS80(chspec)	0
++#endif
++#ifndef CHSPEC_IS160
++#define CHSPEC_IS160(chspec)	0
++#endif
++#ifndef CHSPEC_IS8080
++#define CHSPEC_IS8080(chspec)	0
++#endif
++#define BW_LE20(bw)		TRUE
++#define CHSPEC_ISLE20(chspec)	TRUE
++#else /* !WL11N_20MHZONLY */
++
++#define CHSPEC_IS2P5(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_2P5)
++#define CHSPEC_IS5(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_5)
++#define CHSPEC_IS10(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_10)
++#define CHSPEC_IS20(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_20)
++#define CHSPEC_IS20_5G(chspec)	((((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_20) && \
++								CHSPEC_IS5G(chspec))
++#ifndef CHSPEC_IS40
++#define CHSPEC_IS40(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40)
++#endif
++#ifndef CHSPEC_IS80
++#define CHSPEC_IS80(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_80)
++#endif
++#ifndef CHSPEC_IS160
++#define CHSPEC_IS160(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_160)
++#endif
++#ifndef CHSPEC_IS8080
++#define CHSPEC_IS8080(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_8080)
++#endif
++
++#ifdef WL11ULB
++#define BW_LT20(bw)		(((bw) == WL_CHANSPEC_BW_2P5) || \
++				((bw) == WL_CHANSPEC_BW_5) || \
++				((bw) == WL_CHANSPEC_BW_10))
++#define CHSPEC_BW_LT20(chspec)	(BW_LT20(CHSPEC_BW(chspec)))
++/* This MACRO is strictly to avoid abandons in existing code with ULB feature and is in no way
++ * optimial to use. Should be replaced with CHSPEC_BW_LE() instead
++ */
++#define BW_LE20(bw)		(((bw) == WL_CHANSPEC_BW_2P5) || \
++				((bw) == WL_CHANSPEC_BW_5) || \
++				((bw) == WL_CHANSPEC_BW_10) || \
++				((bw) == WL_CHANSPEC_BW_20))
++#define CHSPEC_ISLE20(chspec)	(BW_LE20(CHSPEC_BW(chspec)))
++
++#else /* WL11ULB */
++#define BW_LE20(bw)		((bw) == WL_CHANSPEC_BW_20)
++#define CHSPEC_ISLE20(chspec)	(CHSPEC_IS20(chspec))
++#endif /* WL11ULB */
++#endif /* !WL11N_20MHZONLY */
++
++#define BW_LE40(bw)		(BW_LE20(bw) || ((bw) == WL_CHANSPEC_BW_40))
++#define BW_LE80(bw)		(BW_LE40(bw) || ((bw) == WL_CHANSPEC_BW_80))
++#define BW_LE160(bw)		(BW_LE80(bw) || ((bw) == WL_CHANSPEC_BW_160))
++#define CHSPEC_BW_LE20(chspec)	(BW_LE20(CHSPEC_BW(chspec)))
++#define CHSPEC_IS5G(chspec)	(((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_5G)
++#define CHSPEC_IS2G(chspec)	(((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_2G)
++#define CHSPEC_SB_UPPER(chspec)	\
++	((((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_UPPER) && \
++	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40))
++#define CHSPEC_SB_LOWER(chspec)	\
++	((((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_LOWER) && \
++	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40))
++#define CHSPEC2WLC_BAND(chspec) (CHSPEC_IS5G(chspec) ? WLC_BAND_5G : WLC_BAND_2G)
++
++/**
++ * Number of chars needed for wf_chspec_ntoa() destination character buffer.
++ */
++#define CHANSPEC_STR_LEN    20
++
++
++#define CHSPEC_IS_BW_160_WIDE(chspec) (CHSPEC_BW(chspec) == WL_CHANSPEC_BW_160 ||\
++	CHSPEC_BW(chspec) == WL_CHANSPEC_BW_8080)
++
++/* BW inequality comparisons, LE (<=), GE (>=), LT (<), GT (>), comparisons can be made
++* as simple numeric comparisons, with the exception that 160 is the same BW as 80+80,
++* but have different numeric values; (WL_CHANSPEC_BW_160 < WL_CHANSPEC_BW_8080).
++*
++* The LT/LE/GT/GE macros check first checks whether both chspec bandwidth and bw are 160 wide.
++* If both chspec bandwidth and bw is not 160 wide, then the comparison is made.
++*/
++#ifdef WL11ULB
++#define CHSPEC_BW_GE(chspec, bw) \
++	(((CHSPEC_IS_BW_160_WIDE(chspec) &&\
++	((bw) == WL_CHANSPEC_BW_160 || (bw) == WL_CHANSPEC_BW_8080)) ||\
++	(CHSPEC_BW(chspec) >= (bw))) && \
++	(!(CHSPEC_BW(chspec) == WL_CHANSPEC_BW_2P5 && (bw) != WL_CHANSPEC_BW_2P5)))
++#else /* WL11ULB */
++#define CHSPEC_BW_GE(chspec, bw) \
++		((CHSPEC_IS_BW_160_WIDE(chspec) &&\
++		((bw) == WL_CHANSPEC_BW_160 || (bw) == WL_CHANSPEC_BW_8080)) ||\
++		(CHSPEC_BW(chspec) >= (bw)))
++#endif /* WL11ULB */
++
++#ifdef WL11ULB
++#define CHSPEC_BW_LE(chspec, bw) \
++	(((CHSPEC_IS_BW_160_WIDE(chspec) &&\
++	((bw) == WL_CHANSPEC_BW_160 || (bw) == WL_CHANSPEC_BW_8080)) ||\
++	(CHSPEC_BW(chspec) <= (bw))) || \
++	(CHSPEC_BW(chspec) == WL_CHANSPEC_BW_2P5))
++#else /* WL11ULB */
++#define CHSPEC_BW_LE(chspec, bw) \
++		((CHSPEC_IS_BW_160_WIDE(chspec) &&\
++		((bw) == WL_CHANSPEC_BW_160 || (bw) == WL_CHANSPEC_BW_8080)) ||\
++		(CHSPEC_BW(chspec) <= (bw)))
++#endif /* WL11ULB */
++
++#ifdef WL11ULB
++#define CHSPEC_BW_GT(chspec, bw) \
++	((!(CHSPEC_IS_BW_160_WIDE(chspec) &&\
++	((bw) == WL_CHANSPEC_BW_160 || (bw) == WL_CHANSPEC_BW_8080)) &&\
++	(CHSPEC_BW(chspec) > (bw))) && \
++	(CHSPEC_BW(chspec) != WL_CHANSPEC_BW_2P5))
++#else /* WL11ULB */
++#define CHSPEC_BW_GT(chspec, bw) \
++		(!(CHSPEC_IS_BW_160_WIDE(chspec) &&\
++		((bw) == WL_CHANSPEC_BW_160 || (bw) == WL_CHANSPEC_BW_8080)) &&\
++		(CHSPEC_BW(chspec) > (bw)))
++#endif /* WL11ULB */
++
++#ifdef WL11ULB
++#define CHSPEC_BW_LT(chspec, bw) \
++	((!(CHSPEC_IS_BW_160_WIDE(chspec) &&\
++	((bw) == WL_CHANSPEC_BW_160 || (bw) == WL_CHANSPEC_BW_8080)) &&\
++	(CHSPEC_BW(chspec) < (bw))) || \
++	((CHSPEC_BW(chspec) == WL_CHANSPEC_BW_2P5 && (bw) != WL_CHANSPEC_BW_2P5)))
++#else /* WL11ULB */
++#define CHSPEC_BW_LT(chspec, bw) \
++		(!(CHSPEC_IS_BW_160_WIDE(chspec) &&\
++		((bw) == WL_CHANSPEC_BW_160 || (bw) == WL_CHANSPEC_BW_8080)) &&\
++		(CHSPEC_BW(chspec) < (bw)))
++#endif /* WL11ULB */
++
++/* Legacy Chanspec defines
++ * These are the defines for the previous format of the chanspec_t
++ */
++#define WL_LCHANSPEC_CHAN_MASK		0x00ff
++#define WL_LCHANSPEC_CHAN_SHIFT		     0
++
++#define WL_LCHANSPEC_CTL_SB_MASK	0x0300
++#define WL_LCHANSPEC_CTL_SB_SHIFT	     8
++#define WL_LCHANSPEC_CTL_SB_LOWER	0x0100
++#define WL_LCHANSPEC_CTL_SB_UPPER	0x0200
++#define WL_LCHANSPEC_CTL_SB_NONE	0x0300
++
++#define WL_LCHANSPEC_BW_MASK		0x0C00
++#define WL_LCHANSPEC_BW_SHIFT		    10
++#define WL_LCHANSPEC_BW_10		0x0400
++#define WL_LCHANSPEC_BW_20		0x0800
++#define WL_LCHANSPEC_BW_40		0x0C00
++
++#define WL_LCHANSPEC_BAND_MASK		0xf000
++#define WL_LCHANSPEC_BAND_SHIFT		    12
++#define WL_LCHANSPEC_BAND_5G		0x1000
++#define WL_LCHANSPEC_BAND_2G		0x2000
++
++#define LCHSPEC_CHANNEL(chspec)	((uint8)((chspec) & WL_LCHANSPEC_CHAN_MASK))
++#define LCHSPEC_BAND(chspec)	((chspec) & WL_LCHANSPEC_BAND_MASK)
++#define LCHSPEC_CTL_SB(chspec)	((chspec) & WL_LCHANSPEC_CTL_SB_MASK)
++#define LCHSPEC_BW(chspec)	((chspec) & WL_LCHANSPEC_BW_MASK)
++#define LCHSPEC_IS10(chspec)	(((chspec) & WL_LCHANSPEC_BW_MASK) == WL_LCHANSPEC_BW_10)
++#define LCHSPEC_IS20(chspec)	(((chspec) & WL_LCHANSPEC_BW_MASK) == WL_LCHANSPEC_BW_20)
++#define LCHSPEC_IS40(chspec)	(((chspec) & WL_LCHANSPEC_BW_MASK) == WL_LCHANSPEC_BW_40)
++#define LCHSPEC_IS5G(chspec)	(((chspec) & WL_LCHANSPEC_BAND_MASK) == WL_LCHANSPEC_BAND_5G)
++#define LCHSPEC_IS2G(chspec)	(((chspec) & WL_LCHANSPEC_BAND_MASK) == WL_LCHANSPEC_BAND_2G)
++
++#define LCHSPEC_SB_UPPER(chspec)	\
++	((((chspec) & WL_LCHANSPEC_CTL_SB_MASK) == WL_LCHANSPEC_CTL_SB_UPPER) && \
++	(((chspec) & WL_LCHANSPEC_BW_MASK) == WL_LCHANSPEC_BW_40))
++#define LCHSPEC_SB_LOWER(chspec)	\
++	((((chspec) & WL_LCHANSPEC_CTL_SB_MASK) == WL_LCHANSPEC_CTL_SB_LOWER) && \
++	(((chspec) & WL_LCHANSPEC_BW_MASK) == WL_LCHANSPEC_BW_40))
++
++#define LCHSPEC_CREATE(chan, band, bw, sb)  ((uint16)((chan) | (sb) | (bw) | (band)))
++
++#define CH20MHZ_LCHSPEC(channel) \
++	(chanspec_t)((chanspec_t)(channel) | WL_LCHANSPEC_BW_20 | \
++	WL_LCHANSPEC_CTL_SB_NONE | (((channel) <= CH_MAX_2G_CHANNEL) ? \
++	WL_LCHANSPEC_BAND_2G : WL_LCHANSPEC_BAND_5G))
++
++/*
++ * WF_CHAN_FACTOR_* constants are used to calculate channel frequency
++ * given a channel number.
++ * chan_freq = chan_factor * 500Mhz + chan_number * 5
++ */
++
++/**
++ * Channel Factor for the starting frequence of 2.4 GHz channels.
++ * The value corresponds to 2407 MHz.
++ */
++#define WF_CHAN_FACTOR_2_4_G		4814	/* 2.4 GHz band, 2407 MHz */
++
++/**
++ * Channel Factor for the starting frequence of 5 GHz channels.
++ * The value corresponds to 5000 MHz.
++ */
++#define WF_CHAN_FACTOR_5_G		10000	/* 5   GHz band, 5000 MHz */
++
++/**
++ * Channel Factor for the starting frequence of 4.9 GHz channels.
++ * The value corresponds to 4000 MHz.
++ */
++#define WF_CHAN_FACTOR_4_G		8000	/* 4.9 GHz band for Japan */
++
++#define WLC_2G_25MHZ_OFFSET		5	/* 2.4GHz band channel offset */
++
++/**
++ *  No of sub-band vlaue of the specified Mhz chanspec
++ */
++#define WF_NUM_SIDEBANDS_40MHZ   2
++#define WF_NUM_SIDEBANDS_80MHZ   4
++#define WF_NUM_SIDEBANDS_8080MHZ 4
++#define WF_NUM_SIDEBANDS_160MHZ  8
++
++/**
++ * Convert chanspec to ascii string
++ *
++ * @param	chspec		chanspec format
++ * @param	buf		ascii string of chanspec
++ *
++ * @return	pointer to buf with room for at least CHANSPEC_STR_LEN bytes
++ *		Original chanspec in case of error
++ *
++ * @see		CHANSPEC_STR_LEN
++ */
++extern char * wf_chspec_ntoa_ex(chanspec_t chspec, char *buf);
++
++/**
++ * Convert chanspec to ascii string
++ *
++ * @param	chspec		chanspec format
++ * @param	buf		ascii string of chanspec
++ *
++ * @return	pointer to buf with room for at least CHANSPEC_STR_LEN bytes
++ *		NULL in case of error
++ *
++ * @see		CHANSPEC_STR_LEN
++ */
++extern char * wf_chspec_ntoa(chanspec_t chspec, char *buf);
++
++/**
++ * Convert ascii string to chanspec
++ *
++ * @param	a     pointer to input string
++ *
++ * @return	>= 0 if successful or 0 otherwise
++ */
++extern chanspec_t wf_chspec_aton(const char *a);
++
++/**
++ * Verify the chanspec fields are valid.
++ *
++ * Verify the chanspec is using a legal set field values, i.e. that the chanspec
++ * specified a band, bw, ctl_sb and channel and that the combination could be
++ * legal given some set of circumstances.
++ *
++ * @param	chanspec   input chanspec to verify
++ *
++ * @return TRUE if the chanspec is malformed, FALSE if it looks good.
++ */
++extern bool wf_chspec_malformed(chanspec_t chanspec);
++
++/**
++ * Verify the chanspec specifies a valid channel according to 802.11.
++ *
++ * @param	chanspec   input chanspec to verify
++ *
++ * @return TRUE if the chanspec is a valid 802.11 channel
++ */
++extern bool wf_chspec_valid(chanspec_t chanspec);
++
++/**
++ * Return the primary (control) channel.
++ *
++ * This function returns the channel number of the primary 20MHz channel. For
++ * 20MHz channels this is just the channel number. For 40MHz or wider channels
++ * it is the primary 20MHz channel specified by the chanspec.
++ *
++ * @param	chspec    input chanspec
++ *
++ * @return Returns the channel number of the primary 20MHz channel
++ */
++extern uint8 wf_chspec_ctlchan(chanspec_t chspec);
++
++/*
++ * Return the bandwidth string.
++ *
++ * This function returns the bandwidth string for the passed chanspec.
++ *
++ * @param	chspec    input chanspec
++ *
++ * @return Returns the bandwidth string
++ */
++extern const char *wf_chspec_to_bw_str(chanspec_t chspec);
++
++/**
++ * Return the primary (control) chanspec.
++ *
++ * This function returns the chanspec of the primary 20MHz channel. For 20MHz
++ * channels this is just the chanspec. For 40MHz or wider channels it is the
++ * chanspec of the primary 20MHZ channel specified by the chanspec.
++ *
++ * @param	chspec    input chanspec
++ *
++ * @return Returns the chanspec of the primary 20MHz channel
++ */
++extern chanspec_t wf_chspec_ctlchspec(chanspec_t chspec);
++
++/**
++ * Return a channel number corresponding to a frequency.
++ *
++ * This function returns the chanspec for the primary 40MHz of an 80MHz channel.
++ * The control sideband specifies the same 20MHz channel that the 80MHz channel is using
++ * as the primary 20MHz channel.
++ */
++extern chanspec_t wf_chspec_primary40_chspec(chanspec_t chspec);
++
++/*
++ * Return the channel number for a given frequency and base frequency.
++ * The returned channel number is relative to the given base frequency.
++ * If the given base frequency is zero, a base frequency of 5 GHz is assumed for
++ * frequencies from 5 - 6 GHz, and 2.407 GHz is assumed for 2.4 - 2.5 GHz.
++ *
++ * Frequency is specified in MHz.
++ * The base frequency is specified as (start_factor * 500 kHz).
++ * Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_5_G are defined for
++ * 2.4 GHz and 5 GHz bands.
++ *
++ * The returned channel will be in the range [1, 14] in the 2.4 GHz band
++ * and [0, 200] otherwise.
++ * -1 is returned if the start_factor is WF_CHAN_FACTOR_2_4_G and the
++ * frequency is not a 2.4 GHz channel, or if the frequency is not and even
++ * multiple of 5 MHz from the base frequency to the base plus 1 GHz.
++ *
++ * Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
++ *
++ * @param	freq          frequency in MHz
++ * @param	start_factor  base frequency in 500 kHz units, e.g. 10000 for 5 GHz
++ *
++ * @return Returns a channel number
++ *
++ * @see  WF_CHAN_FACTOR_2_4_G
++ * @see  WF_CHAN_FACTOR_5_G
++ */
++extern int wf_mhz2channel(uint freq, uint start_factor);
++
++/**
++ * Return the center frequency in MHz of the given channel and base frequency.
++ *
++ * Return the center frequency in MHz of the given channel and base frequency.
++ * The channel number is interpreted relative to the given base frequency.
++ *
++ * The valid channel range is [1, 14] in the 2.4 GHz band and [0, 200] otherwise.
++ * The base frequency is specified as (start_factor * 500 kHz).
++ * Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_5_G are defined for
++ * 2.4 GHz and 5 GHz bands.
++ * The channel range of [1, 14] is only checked for a start_factor of
++ * WF_CHAN_FACTOR_2_4_G (4814).
++ * Odd start_factors produce channels on .5 MHz boundaries, in which case
++ * the answer is rounded down to an integral MHz.
++ * -1 is returned for an out of range channel.
++ *
++ * Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
++ *
++ * @param	channel       input channel number
++ * @param	start_factor  base frequency in 500 kHz units, e.g. 10000 for 5 GHz
++ *
++ * @return Returns a frequency in MHz
++ *
++ * @see  WF_CHAN_FACTOR_2_4_G
++ * @see  WF_CHAN_FACTOR_5_G
++ */
++extern int wf_channel2mhz(uint channel, uint start_factor);
++
++/**
++ * Returns the chanspec 80Mhz channel corresponding to the following input
++ * parameters
++ *
++ *	primary_channel - primary 20Mhz channel
++ *	center_channel   - center frequecny of the 80Mhz channel
++ *
++ * The center_channel can be one of {42, 58, 106, 122, 138, 155}
++ *
++ * returns INVCHANSPEC in case of error
++ */
++extern chanspec_t wf_chspec_80(uint8 center_channel, uint8 primary_channel);
++
++/**
++ * Convert ctl chan and bw to chanspec
++ *
++ * @param	ctl_ch		channel
++ * @param	bw	        bandwidth
++ *
++ * @return	> 0 if successful or 0 otherwise
++ *
++ */
++extern uint16 wf_channel2chspec(uint ctl_ch, uint bw);
++
++extern uint wf_channel2freq(uint channel);
++extern uint wf_freq2channel(uint freq);
++
++/*
++ * Returns the 80+80 MHz chanspec corresponding to the following input parameters
++ *
++ *    primary_20mhz - Primary 20 MHz channel
++ *    chan0_80MHz - center channel number of one frequency segment
++ *    chan1_80MHz - center channel number of the other frequency segment
++ *
++ * Parameters chan0_80MHz and chan1_80MHz are channel numbers in {42, 58, 106, 122, 138, 155}.
++ * The primary channel must be contained in one of the 80MHz channels. This routine
++ * will determine which frequency segment is the primary 80 MHz segment.
++ *
++ * Returns INVCHANSPEC in case of error.
++ *
++ * Refer to IEEE802.11ac section 22.3.14 "Channelization".
++ */
++extern chanspec_t wf_chspec_get8080_chspec(uint8 primary_20mhz,
++	uint8 chan0_80Mhz, uint8 chan1_80Mhz);
++
++/*
++ * Returns the primary 80 Mhz channel for the provided chanspec
++ *
++ *    chanspec - Input chanspec for which the 80MHz primary channel has to be retrieved
++ *
++ *  returns -1 in case the provided channel is 20/40 Mhz chanspec
++ */
++extern uint8 wf_chspec_primary80_channel(chanspec_t chanspec);
++
++/*
++ * Returns the secondary 80 Mhz channel for the provided chanspec
++ *
++ *    chanspec - Input chanspec for which the 80MHz secondary channel has to be retrieved
++ *
++ *  returns -1 in case the provided channel is 20/40 Mhz chanspec
++ */
++extern uint8 wf_chspec_secondary80_channel(chanspec_t chanspec);
++
++/*
++ * This function returns the chanspec for the primary 80MHz of an 160MHz or 80+80 channel.
++ */
++extern chanspec_t wf_chspec_primary80_chspec(chanspec_t chspec);
++
++#ifdef WL11AC_80P80
++/*
++ * This function returns the centre chanel for the given chanspec.
++ * In case of 80+80 chanspec it returns the primary 80 Mhz centre channel
++ */
++extern uint8 wf_chspec_channel(chanspec_t chspec);
++#endif
++extern chanspec_t wf_channel_create_chspec_frm_opclass(uint8 opclass, uint8 channel);
++extern int wf_channel_create_opclass_frm_chspec(chanspec_t chspec);
++#endif	/* _bcmwifi_channels_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/bcmwifi_rates.h b/module_drivers/drivers/net/wireless/bcmdhd/bcmwifi_rates.h
+new file mode 100644
+index 000000000..542055df3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/bcmwifi_rates.h
+@@ -0,0 +1,793 @@
++/*
++ * Indices for 802.11 a/b/g/n/ac 1-3 chain symmetric transmit rates
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmwifi_rates.h 612483 2016-01-14 03:44:27Z $
++ */
++
++#ifndef _bcmwifi_rates_h_
++#define _bcmwifi_rates_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif /* __cplusplus */
++
++
++#define WL_RATESET_SZ_DSSS		4
++#define WL_RATESET_SZ_OFDM		8
++#define WL_RATESET_SZ_VHT_MCS	10
++#define WL_RATESET_SZ_VHT_MCS_P	12
++
++#if defined(WLPROPRIETARY_11N_RATES)
++#define WL_RATESET_SZ_HT_MCS	WL_RATESET_SZ_VHT_MCS
++#else
++#define WL_RATESET_SZ_HT_MCS	8
++#endif
++
++#define WL_RATESET_SZ_HT_IOCTL	8	/* MAC histogram, compatibility with wl utility */
++
++#define WL_TX_CHAINS_MAX		4
++
++#define WL_RATE_DISABLED		(-128) /* Power value corresponding to unsupported rate */
++
++/* Transmit channel bandwidths */
++typedef enum wl_tx_bw {
++	WL_TX_BW_20,
++	WL_TX_BW_40,
++	WL_TX_BW_80,
++	WL_TX_BW_20IN40,
++	WL_TX_BW_20IN80,
++	WL_TX_BW_40IN80,
++	WL_TX_BW_160,
++	WL_TX_BW_20IN160,
++	WL_TX_BW_40IN160,
++	WL_TX_BW_80IN160,
++	WL_TX_BW_ALL,
++	WL_TX_BW_8080,
++	WL_TX_BW_8080CHAN2,
++	WL_TX_BW_20IN8080,
++	WL_TX_BW_40IN8080,
++	WL_TX_BW_80IN8080,
++	WL_TX_BW_2P5,
++	WL_TX_BW_5,
++	WL_TX_BW_10
++} wl_tx_bw_t;
++
++
++/*
++ * Transmit modes.
++ * Not all modes are listed here, only those required for disambiguation. e.g. SPEXP is not listed
++ */
++typedef enum wl_tx_mode {
++	WL_TX_MODE_NONE,
++	WL_TX_MODE_STBC,
++	WL_TX_MODE_CDD,
++	WL_TX_MODE_TXBF,
++	WL_NUM_TX_MODES
++} wl_tx_mode_t;
++
++
++/* Number of transmit chains */
++typedef enum wl_tx_chains {
++	WL_TX_CHAINS_1 = 1,
++	WL_TX_CHAINS_2,
++	WL_TX_CHAINS_3,
++	WL_TX_CHAINS_4
++} wl_tx_chains_t;
++
++
++/* Number of transmit streams */
++typedef enum wl_tx_nss {
++	WL_TX_NSS_1 = 1,
++	WL_TX_NSS_2,
++	WL_TX_NSS_3,
++	WL_TX_NSS_4
++} wl_tx_nss_t;
++
++
++/* This enum maps each rate to a CLM index */
++
++typedef enum clm_rates {
++	/************
++	* 1 chain  *
++	************
++	*/
++
++	/* 1 Stream */
++	WL_RATE_1X1_DSSS_1            = 0,
++	WL_RATE_1X1_DSSS_2            = 1,
++	WL_RATE_1X1_DSSS_5_5          = 2,
++	WL_RATE_1X1_DSSS_11           = 3,
++
++	WL_RATE_1X1_OFDM_6            = 4,
++	WL_RATE_1X1_OFDM_9            = 5,
++	WL_RATE_1X1_OFDM_12           = 6,
++	WL_RATE_1X1_OFDM_18           = 7,
++	WL_RATE_1X1_OFDM_24           = 8,
++	WL_RATE_1X1_OFDM_36           = 9,
++	WL_RATE_1X1_OFDM_48           = 10,
++	WL_RATE_1X1_OFDM_54           = 11,
++
++	WL_RATE_1X1_MCS0              = 12,
++	WL_RATE_1X1_MCS1              = 13,
++	WL_RATE_1X1_MCS2              = 14,
++	WL_RATE_1X1_MCS3              = 15,
++	WL_RATE_1X1_MCS4              = 16,
++	WL_RATE_1X1_MCS5              = 17,
++	WL_RATE_1X1_MCS6              = 18,
++	WL_RATE_1X1_MCS7              = 19,
++	WL_RATE_P_1X1_MCS87           = 20,
++	WL_RATE_P_1X1_MCS88           = 21,
++
++	WL_RATE_1X1_VHT0SS1           = 12,
++	WL_RATE_1X1_VHT1SS1           = 13,
++	WL_RATE_1X1_VHT2SS1           = 14,
++	WL_RATE_1X1_VHT3SS1           = 15,
++	WL_RATE_1X1_VHT4SS1           = 16,
++	WL_RATE_1X1_VHT5SS1           = 17,
++	WL_RATE_1X1_VHT6SS1           = 18,
++	WL_RATE_1X1_VHT7SS1           = 19,
++	WL_RATE_1X1_VHT8SS1           = 20,
++	WL_RATE_1X1_VHT9SS1           = 21,
++	WL_RATE_P_1X1_VHT10SS1        = 22,
++	WL_RATE_P_1X1_VHT11SS1        = 23,
++
++
++	/************
++	* 2 chains *
++	************
++	*/
++
++	/* 1 Stream expanded + 1 */
++	WL_RATE_1X2_DSSS_1            = 24,
++	WL_RATE_1X2_DSSS_2            = 25,
++	WL_RATE_1X2_DSSS_5_5          = 26,
++	WL_RATE_1X2_DSSS_11           = 27,
++
++	WL_RATE_1X2_CDD_OFDM_6        = 28,
++	WL_RATE_1X2_CDD_OFDM_9        = 29,
++	WL_RATE_1X2_CDD_OFDM_12       = 30,
++	WL_RATE_1X2_CDD_OFDM_18       = 31,
++	WL_RATE_1X2_CDD_OFDM_24       = 32,
++	WL_RATE_1X2_CDD_OFDM_36       = 33,
++	WL_RATE_1X2_CDD_OFDM_48       = 34,
++	WL_RATE_1X2_CDD_OFDM_54       = 35,
++
++	WL_RATE_1X2_CDD_MCS0          = 36,
++	WL_RATE_1X2_CDD_MCS1          = 37,
++	WL_RATE_1X2_CDD_MCS2          = 38,
++	WL_RATE_1X2_CDD_MCS3          = 39,
++	WL_RATE_1X2_CDD_MCS4          = 40,
++	WL_RATE_1X2_CDD_MCS5          = 41,
++	WL_RATE_1X2_CDD_MCS6          = 42,
++	WL_RATE_1X2_CDD_MCS7          = 43,
++	WL_RATE_P_1X2_CDD_MCS87       = 44,
++	WL_RATE_P_1X2_CDD_MCS88       = 45,
++
++	WL_RATE_1X2_VHT0SS1           = 36,
++	WL_RATE_1X2_VHT1SS1           = 37,
++	WL_RATE_1X2_VHT2SS1           = 38,
++	WL_RATE_1X2_VHT3SS1           = 39,
++	WL_RATE_1X2_VHT4SS1           = 40,
++	WL_RATE_1X2_VHT5SS1           = 41,
++	WL_RATE_1X2_VHT6SS1           = 42,
++	WL_RATE_1X2_VHT7SS1           = 43,
++	WL_RATE_1X2_VHT8SS1           = 44,
++	WL_RATE_1X2_VHT9SS1           = 45,
++	WL_RATE_P_1X2_VHT10SS1        = 46,
++	WL_RATE_P_1X2_VHT11SS1        = 47,
++
++	/* 2 Streams */
++	WL_RATE_2X2_STBC_MCS0         = 48,
++	WL_RATE_2X2_STBC_MCS1         = 49,
++	WL_RATE_2X2_STBC_MCS2         = 50,
++	WL_RATE_2X2_STBC_MCS3         = 51,
++	WL_RATE_2X2_STBC_MCS4         = 52,
++	WL_RATE_2X2_STBC_MCS5         = 53,
++	WL_RATE_2X2_STBC_MCS6         = 54,
++	WL_RATE_2X2_STBC_MCS7         = 55,
++	WL_RATE_P_2X2_STBC_MCS87      = 56,
++	WL_RATE_P_2X2_STBC_MCS88      = 57,
++
++	WL_RATE_2X2_STBC_VHT0SS1      = 48,
++	WL_RATE_2X2_STBC_VHT1SS1      = 49,
++	WL_RATE_2X2_STBC_VHT2SS1      = 50,
++	WL_RATE_2X2_STBC_VHT3SS1      = 51,
++	WL_RATE_2X2_STBC_VHT4SS1      = 52,
++	WL_RATE_2X2_STBC_VHT5SS1      = 53,
++	WL_RATE_2X2_STBC_VHT6SS1      = 54,
++	WL_RATE_2X2_STBC_VHT7SS1      = 55,
++	WL_RATE_2X2_STBC_VHT8SS1      = 56,
++	WL_RATE_2X2_STBC_VHT9SS1      = 57,
++	WL_RATE_P_2X2_STBC_VHT10SS1   = 58,
++	WL_RATE_P_2X2_STBC_VHT11SS1   = 59,
++
++	WL_RATE_2X2_SDM_MCS8          = 60,
++	WL_RATE_2X2_SDM_MCS9          = 61,
++	WL_RATE_2X2_SDM_MCS10         = 62,
++	WL_RATE_2X2_SDM_MCS11         = 63,
++	WL_RATE_2X2_SDM_MCS12         = 64,
++	WL_RATE_2X2_SDM_MCS13         = 65,
++	WL_RATE_2X2_SDM_MCS14         = 66,
++	WL_RATE_2X2_SDM_MCS15         = 67,
++	WL_RATE_P_2X2_SDM_MCS99       = 68,
++	WL_RATE_P_2X2_SDM_MCS100      = 69,
++
++	WL_RATE_2X2_VHT0SS2           = 60,
++	WL_RATE_2X2_VHT1SS2           = 61,
++	WL_RATE_2X2_VHT2SS2           = 62,
++	WL_RATE_2X2_VHT3SS2           = 63,
++	WL_RATE_2X2_VHT4SS2           = 64,
++	WL_RATE_2X2_VHT5SS2           = 65,
++	WL_RATE_2X2_VHT6SS2           = 66,
++	WL_RATE_2X2_VHT7SS2           = 67,
++	WL_RATE_2X2_VHT8SS2           = 68,
++	WL_RATE_2X2_VHT9SS2           = 69,
++	WL_RATE_P_2X2_VHT10SS2        = 70,
++	WL_RATE_P_2X2_VHT11SS2        = 71,
++
++	/****************************
++	 * TX Beamforming, 2 chains *
++	 ****************************
++	 */
++
++	/* 1 Stream expanded + 1 */
++	WL_RATE_1X2_TXBF_OFDM_6       = 72,
++	WL_RATE_1X2_TXBF_OFDM_9       = 73,
++	WL_RATE_1X2_TXBF_OFDM_12      = 74,
++	WL_RATE_1X2_TXBF_OFDM_18      = 75,
++	WL_RATE_1X2_TXBF_OFDM_24      = 76,
++	WL_RATE_1X2_TXBF_OFDM_36      = 77,
++	WL_RATE_1X2_TXBF_OFDM_48      = 78,
++	WL_RATE_1X2_TXBF_OFDM_54      = 79,
++
++	WL_RATE_1X2_TXBF_MCS0         = 80,
++	WL_RATE_1X2_TXBF_MCS1         = 81,
++	WL_RATE_1X2_TXBF_MCS2         = 82,
++	WL_RATE_1X2_TXBF_MCS3         = 83,
++	WL_RATE_1X2_TXBF_MCS4         = 84,
++	WL_RATE_1X2_TXBF_MCS5         = 85,
++	WL_RATE_1X2_TXBF_MCS6         = 86,
++	WL_RATE_1X2_TXBF_MCS7         = 87,
++	WL_RATE_P_1X2_TXBF_MCS87      = 88,
++	WL_RATE_P_1X2_TXBF_MCS88      = 89,
++
++	WL_RATE_1X2_TXBF_VHT0SS1      = 80,
++	WL_RATE_1X2_TXBF_VHT1SS1      = 81,
++	WL_RATE_1X2_TXBF_VHT2SS1      = 82,
++	WL_RATE_1X2_TXBF_VHT3SS1      = 83,
++	WL_RATE_1X2_TXBF_VHT4SS1      = 84,
++	WL_RATE_1X2_TXBF_VHT5SS1      = 85,
++	WL_RATE_1X2_TXBF_VHT6SS1      = 86,
++	WL_RATE_1X2_TXBF_VHT7SS1      = 87,
++	WL_RATE_1X2_TXBF_VHT8SS1      = 88,
++	WL_RATE_1X2_TXBF_VHT9SS1      = 89,
++	WL_RATE_P_1X2_TXBF_VHT10SS1   = 90,
++	WL_RATE_P_1X2_TXBF_VHT11SS1   = 91,
++
++	/* 2 Streams */
++	WL_RATE_2X2_TXBF_SDM_MCS8     = 92,
++	WL_RATE_2X2_TXBF_SDM_MCS9     = 93,
++	WL_RATE_2X2_TXBF_SDM_MCS10    = 94,
++	WL_RATE_2X2_TXBF_SDM_MCS11    = 95,
++	WL_RATE_2X2_TXBF_SDM_MCS12    = 96,
++	WL_RATE_2X2_TXBF_SDM_MCS13    = 97,
++	WL_RATE_2X2_TXBF_SDM_MCS14    = 98,
++	WL_RATE_2X2_TXBF_SDM_MCS15    = 99,
++	WL_RATE_P_2X2_TXBF_SDM_MCS99  = 100,
++	WL_RATE_P_2X2_TXBF_SDM_MCS100 = 101,
++
++	WL_RATE_2X2_TXBF_VHT0SS2      = 92,
++	WL_RATE_2X2_TXBF_VHT1SS2      = 93,
++	WL_RATE_2X2_TXBF_VHT2SS2      = 94,
++	WL_RATE_2X2_TXBF_VHT3SS2      = 95,
++	WL_RATE_2X2_TXBF_VHT4SS2      = 96,
++	WL_RATE_2X2_TXBF_VHT5SS2      = 97,
++	WL_RATE_2X2_TXBF_VHT6SS2      = 98,
++	WL_RATE_2X2_TXBF_VHT7SS2      = 99,
++	WL_RATE_2X2_TXBF_VHT8SS2      = 100,
++	WL_RATE_2X2_TXBF_VHT9SS2      = 101,
++	WL_RATE_P_2X2_TXBF_VHT10SS2   = 102,
++	WL_RATE_P_2X2_TXBF_VHT11SS2   = 103,
++
++
++	/************
++	* 3 chains *
++	************
++	*/
++
++	/* 1 Stream expanded + 2 */
++	WL_RATE_1X3_DSSS_1            = 104,
++	WL_RATE_1X3_DSSS_2            = 105,
++	WL_RATE_1X3_DSSS_5_5          = 106,
++	WL_RATE_1X3_DSSS_11           = 107,
++
++	WL_RATE_1X3_CDD_OFDM_6        = 108,
++	WL_RATE_1X3_CDD_OFDM_9        = 109,
++	WL_RATE_1X3_CDD_OFDM_12       = 110,
++	WL_RATE_1X3_CDD_OFDM_18       = 111,
++	WL_RATE_1X3_CDD_OFDM_24       = 112,
++	WL_RATE_1X3_CDD_OFDM_36       = 113,
++	WL_RATE_1X3_CDD_OFDM_48       = 114,
++	WL_RATE_1X3_CDD_OFDM_54       = 115,
++
++	WL_RATE_1X3_CDD_MCS0          = 116,
++	WL_RATE_1X3_CDD_MCS1          = 117,
++	WL_RATE_1X3_CDD_MCS2          = 118,
++	WL_RATE_1X3_CDD_MCS3          = 119,
++	WL_RATE_1X3_CDD_MCS4          = 120,
++	WL_RATE_1X3_CDD_MCS5          = 121,
++	WL_RATE_1X3_CDD_MCS6          = 122,
++	WL_RATE_1X3_CDD_MCS7          = 123,
++	WL_RATE_P_1X3_CDD_MCS87       = 124,
++	WL_RATE_P_1X3_CDD_MCS88       = 125,
++
++	WL_RATE_1X3_VHT0SS1           = 116,
++	WL_RATE_1X3_VHT1SS1           = 117,
++	WL_RATE_1X3_VHT2SS1           = 118,
++	WL_RATE_1X3_VHT3SS1           = 119,
++	WL_RATE_1X3_VHT4SS1           = 120,
++	WL_RATE_1X3_VHT5SS1           = 121,
++	WL_RATE_1X3_VHT6SS1           = 122,
++	WL_RATE_1X3_VHT7SS1           = 123,
++	WL_RATE_1X3_VHT8SS1           = 124,
++	WL_RATE_1X3_VHT9SS1           = 125,
++	WL_RATE_P_1X3_VHT10SS1        = 126,
++	WL_RATE_P_1X3_VHT11SS1        = 127,
++
++	/* 2 Streams expanded + 1 */
++	WL_RATE_2X3_STBC_MCS0         = 128,
++	WL_RATE_2X3_STBC_MCS1         = 129,
++	WL_RATE_2X3_STBC_MCS2         = 130,
++	WL_RATE_2X3_STBC_MCS3         = 131,
++	WL_RATE_2X3_STBC_MCS4         = 132,
++	WL_RATE_2X3_STBC_MCS5         = 133,
++	WL_RATE_2X3_STBC_MCS6         = 134,
++	WL_RATE_2X3_STBC_MCS7         = 135,
++	WL_RATE_P_2X3_STBC_MCS87      = 136,
++	WL_RATE_P_2X3_STBC_MCS88      = 137,
++
++	WL_RATE_2X3_STBC_VHT0SS1      = 128,
++	WL_RATE_2X3_STBC_VHT1SS1      = 129,
++	WL_RATE_2X3_STBC_VHT2SS1      = 130,
++	WL_RATE_2X3_STBC_VHT3SS1      = 131,
++	WL_RATE_2X3_STBC_VHT4SS1      = 132,
++	WL_RATE_2X3_STBC_VHT5SS1      = 133,
++	WL_RATE_2X3_STBC_VHT6SS1      = 134,
++	WL_RATE_2X3_STBC_VHT7SS1      = 135,
++	WL_RATE_2X3_STBC_VHT8SS1      = 136,
++	WL_RATE_2X3_STBC_VHT9SS1      = 137,
++	WL_RATE_P_2X3_STBC_VHT10SS1   = 138,
++	WL_RATE_P_2X3_STBC_VHT11SS1   = 139,
++
++	WL_RATE_2X3_SDM_MCS8          = 140,
++	WL_RATE_2X3_SDM_MCS9          = 141,
++	WL_RATE_2X3_SDM_MCS10         = 142,
++	WL_RATE_2X3_SDM_MCS11         = 143,
++	WL_RATE_2X3_SDM_MCS12         = 144,
++	WL_RATE_2X3_SDM_MCS13         = 145,
++	WL_RATE_2X3_SDM_MCS14         = 146,
++	WL_RATE_2X3_SDM_MCS15         = 147,
++	WL_RATE_P_2X3_SDM_MCS99       = 148,
++	WL_RATE_P_2X3_SDM_MCS100      = 149,
++
++	WL_RATE_2X3_VHT0SS2           = 140,
++	WL_RATE_2X3_VHT1SS2           = 141,
++	WL_RATE_2X3_VHT2SS2           = 142,
++	WL_RATE_2X3_VHT3SS2           = 143,
++	WL_RATE_2X3_VHT4SS2           = 144,
++	WL_RATE_2X3_VHT5SS2           = 145,
++	WL_RATE_2X3_VHT6SS2           = 146,
++	WL_RATE_2X3_VHT7SS2           = 147,
++	WL_RATE_2X3_VHT8SS2           = 148,
++	WL_RATE_2X3_VHT9SS2           = 149,
++	WL_RATE_P_2X3_VHT10SS2        = 150,
++	WL_RATE_P_2X3_VHT11SS2        = 151,
++
++	/* 3 Streams */
++	WL_RATE_3X3_SDM_MCS16         = 152,
++	WL_RATE_3X3_SDM_MCS17         = 153,
++	WL_RATE_3X3_SDM_MCS18         = 154,
++	WL_RATE_3X3_SDM_MCS19         = 155,
++	WL_RATE_3X3_SDM_MCS20         = 156,
++	WL_RATE_3X3_SDM_MCS21         = 157,
++	WL_RATE_3X3_SDM_MCS22         = 158,
++	WL_RATE_3X3_SDM_MCS23         = 159,
++	WL_RATE_P_3X3_SDM_MCS101      = 160,
++	WL_RATE_P_3X3_SDM_MCS102      = 161,
++
++	WL_RATE_3X3_VHT0SS3           = 152,
++	WL_RATE_3X3_VHT1SS3           = 153,
++	WL_RATE_3X3_VHT2SS3           = 154,
++	WL_RATE_3X3_VHT3SS3           = 155,
++	WL_RATE_3X3_VHT4SS3           = 156,
++	WL_RATE_3X3_VHT5SS3           = 157,
++	WL_RATE_3X3_VHT6SS3           = 158,
++	WL_RATE_3X3_VHT7SS3           = 159,
++	WL_RATE_3X3_VHT8SS3           = 160,
++	WL_RATE_3X3_VHT9SS3           = 161,
++	WL_RATE_P_3X3_VHT10SS3        = 162,
++	WL_RATE_P_3X3_VHT11SS3        = 163,
++
++
++	/****************************
++	 * TX Beamforming, 3 chains *
++	 ****************************
++	 */
++
++	/* 1 Stream expanded + 2 */
++	WL_RATE_1X3_TXBF_OFDM_6       = 164,
++	WL_RATE_1X3_TXBF_OFDM_9       = 165,
++	WL_RATE_1X3_TXBF_OFDM_12      = 166,
++	WL_RATE_1X3_TXBF_OFDM_18      = 167,
++	WL_RATE_1X3_TXBF_OFDM_24      = 168,
++	WL_RATE_1X3_TXBF_OFDM_36      = 169,
++	WL_RATE_1X3_TXBF_OFDM_48      = 170,
++	WL_RATE_1X3_TXBF_OFDM_54      = 171,
++
++	WL_RATE_1X3_TXBF_MCS0         = 172,
++	WL_RATE_1X3_TXBF_MCS1         = 173,
++	WL_RATE_1X3_TXBF_MCS2         = 174,
++	WL_RATE_1X3_TXBF_MCS3         = 175,
++	WL_RATE_1X3_TXBF_MCS4         = 176,
++	WL_RATE_1X3_TXBF_MCS5         = 177,
++	WL_RATE_1X3_TXBF_MCS6         = 178,
++	WL_RATE_1X3_TXBF_MCS7         = 179,
++	WL_RATE_P_1X3_TXBF_MCS87      = 180,
++	WL_RATE_P_1X3_TXBF_MCS88      = 181,
++
++	WL_RATE_1X3_TXBF_VHT0SS1      = 172,
++	WL_RATE_1X3_TXBF_VHT1SS1      = 173,
++	WL_RATE_1X3_TXBF_VHT2SS1      = 174,
++	WL_RATE_1X3_TXBF_VHT3SS1      = 175,
++	WL_RATE_1X3_TXBF_VHT4SS1      = 176,
++	WL_RATE_1X3_TXBF_VHT5SS1      = 177,
++	WL_RATE_1X3_TXBF_VHT6SS1      = 178,
++	WL_RATE_1X3_TXBF_VHT7SS1      = 179,
++	WL_RATE_1X3_TXBF_VHT8SS1      = 180,
++	WL_RATE_1X3_TXBF_VHT9SS1      = 181,
++	WL_RATE_P_1X3_TXBF_VHT10SS1   = 182,
++	WL_RATE_P_1X3_TXBF_VHT11SS1   = 183,
++
++	/* 2 Streams expanded + 1 */
++	WL_RATE_2X3_TXBF_SDM_MCS8     = 184,
++	WL_RATE_2X3_TXBF_SDM_MCS9     = 185,
++	WL_RATE_2X3_TXBF_SDM_MCS10    = 186,
++	WL_RATE_2X3_TXBF_SDM_MCS11    = 187,
++	WL_RATE_2X3_TXBF_SDM_MCS12    = 188,
++	WL_RATE_2X3_TXBF_SDM_MCS13    = 189,
++	WL_RATE_2X3_TXBF_SDM_MCS14    = 190,
++	WL_RATE_2X3_TXBF_SDM_MCS15    = 191,
++	WL_RATE_P_2X3_TXBF_SDM_MCS99  = 192,
++	WL_RATE_P_2X3_TXBF_SDM_MCS100 = 193,
++
++	WL_RATE_2X3_TXBF_VHT0SS2      = 184,
++	WL_RATE_2X3_TXBF_VHT1SS2      = 185,
++	WL_RATE_2X3_TXBF_VHT2SS2      = 186,
++	WL_RATE_2X3_TXBF_VHT3SS2      = 187,
++	WL_RATE_2X3_TXBF_VHT4SS2      = 188,
++	WL_RATE_2X3_TXBF_VHT5SS2      = 189,
++	WL_RATE_2X3_TXBF_VHT6SS2      = 190,
++	WL_RATE_2X3_TXBF_VHT7SS2      = 191,
++	WL_RATE_2X3_TXBF_VHT8SS2      = 192,
++	WL_RATE_2X3_TXBF_VHT9SS2      = 193,
++	WL_RATE_P_2X3_TXBF_VHT10SS2   = 194,
++	WL_RATE_P_2X3_TXBF_VHT11SS2   = 195,
++
++	/* 3 Streams */
++	WL_RATE_3X3_TXBF_SDM_MCS16    = 196,
++	WL_RATE_3X3_TXBF_SDM_MCS17    = 197,
++	WL_RATE_3X3_TXBF_SDM_MCS18    = 198,
++	WL_RATE_3X3_TXBF_SDM_MCS19    = 199,
++	WL_RATE_3X3_TXBF_SDM_MCS20    = 200,
++	WL_RATE_3X3_TXBF_SDM_MCS21    = 201,
++	WL_RATE_3X3_TXBF_SDM_MCS22    = 202,
++	WL_RATE_3X3_TXBF_SDM_MCS23    = 203,
++	WL_RATE_P_3X3_TXBF_SDM_MCS101 = 204,
++	WL_RATE_P_3X3_TXBF_SDM_MCS102 = 205,
++
++	WL_RATE_3X3_TXBF_VHT0SS3      = 196,
++	WL_RATE_3X3_TXBF_VHT1SS3      = 197,
++	WL_RATE_3X3_TXBF_VHT2SS3      = 198,
++	WL_RATE_3X3_TXBF_VHT3SS3      = 199,
++	WL_RATE_3X3_TXBF_VHT4SS3      = 200,
++	WL_RATE_3X3_TXBF_VHT5SS3      = 201,
++	WL_RATE_3X3_TXBF_VHT6SS3      = 202,
++	WL_RATE_3X3_TXBF_VHT7SS3      = 203,
++	WL_RATE_3X3_TXBF_VHT8SS3      = 204,
++	WL_RATE_3X3_TXBF_VHT9SS3      = 205,
++	WL_RATE_P_3X3_TXBF_VHT10SS3   = 206,
++	WL_RATE_P_3X3_TXBF_VHT11SS3   = 207,
++
++
++	/************
++	* 4 chains *
++	************
++	*/
++
++	/* 1 Stream expanded + 3 */
++	WL_RATE_1X4_DSSS_1            = 208,
++	WL_RATE_1X4_DSSS_2            = 209,
++	WL_RATE_1X4_DSSS_5_5          = 210,
++	WL_RATE_1X4_DSSS_11           = 211,
++
++	WL_RATE_1X4_CDD_OFDM_6        = 212,
++	WL_RATE_1X4_CDD_OFDM_9        = 213,
++	WL_RATE_1X4_CDD_OFDM_12       = 214,
++	WL_RATE_1X4_CDD_OFDM_18       = 215,
++	WL_RATE_1X4_CDD_OFDM_24       = 216,
++	WL_RATE_1X4_CDD_OFDM_36       = 217,
++	WL_RATE_1X4_CDD_OFDM_48       = 218,
++	WL_RATE_1X4_CDD_OFDM_54       = 219,
++
++	WL_RATE_1X4_CDD_MCS0          = 220,
++	WL_RATE_1X4_CDD_MCS1          = 221,
++	WL_RATE_1X4_CDD_MCS2          = 222,
++	WL_RATE_1X4_CDD_MCS3          = 223,
++	WL_RATE_1X4_CDD_MCS4          = 224,
++	WL_RATE_1X4_CDD_MCS5          = 225,
++	WL_RATE_1X4_CDD_MCS6          = 226,
++	WL_RATE_1X4_CDD_MCS7          = 227,
++	WL_RATE_P_1X4_CDD_MCS87       = 228,
++	WL_RATE_P_1X4_CDD_MCS88       = 229,
++
++	WL_RATE_1X4_VHT0SS1           = 220,
++	WL_RATE_1X4_VHT1SS1           = 221,
++	WL_RATE_1X4_VHT2SS1           = 222,
++	WL_RATE_1X4_VHT3SS1           = 223,
++	WL_RATE_1X4_VHT4SS1           = 224,
++	WL_RATE_1X4_VHT5SS1           = 225,
++	WL_RATE_1X4_VHT6SS1           = 226,
++	WL_RATE_1X4_VHT7SS1           = 227,
++	WL_RATE_1X4_VHT8SS1           = 228,
++	WL_RATE_1X4_VHT9SS1           = 229,
++	WL_RATE_P_1X4_VHT10SS1        = 230,
++	WL_RATE_P_1X4_VHT11SS1        = 231,
++
++	/* 2 Streams expanded + 2 */
++	WL_RATE_2X4_STBC_MCS0         = 232,
++	WL_RATE_2X4_STBC_MCS1         = 233,
++	WL_RATE_2X4_STBC_MCS2         = 234,
++	WL_RATE_2X4_STBC_MCS3         = 235,
++	WL_RATE_2X4_STBC_MCS4         = 236,
++	WL_RATE_2X4_STBC_MCS5         = 237,
++	WL_RATE_2X4_STBC_MCS6         = 238,
++	WL_RATE_2X4_STBC_MCS7         = 239,
++	WL_RATE_P_2X4_STBC_MCS87      = 240,
++	WL_RATE_P_2X4_STBC_MCS88      = 241,
++
++	WL_RATE_2X4_STBC_VHT0SS1      = 232,
++	WL_RATE_2X4_STBC_VHT1SS1      = 233,
++	WL_RATE_2X4_STBC_VHT2SS1      = 234,
++	WL_RATE_2X4_STBC_VHT3SS1      = 235,
++	WL_RATE_2X4_STBC_VHT4SS1      = 236,
++	WL_RATE_2X4_STBC_VHT5SS1      = 237,
++	WL_RATE_2X4_STBC_VHT6SS1      = 238,
++	WL_RATE_2X4_STBC_VHT7SS1      = 239,
++	WL_RATE_2X4_STBC_VHT8SS1      = 240,
++	WL_RATE_2X4_STBC_VHT9SS1      = 241,
++	WL_RATE_P_2X4_STBC_VHT10SS1   = 242,
++	WL_RATE_P_2X4_STBC_VHT11SS1   = 243,
++
++	WL_RATE_2X4_SDM_MCS8          = 244,
++	WL_RATE_2X4_SDM_MCS9          = 245,
++	WL_RATE_2X4_SDM_MCS10         = 246,
++	WL_RATE_2X4_SDM_MCS11         = 247,
++	WL_RATE_2X4_SDM_MCS12         = 248,
++	WL_RATE_2X4_SDM_MCS13         = 249,
++	WL_RATE_2X4_SDM_MCS14         = 250,
++	WL_RATE_2X4_SDM_MCS15         = 251,
++	WL_RATE_P_2X4_SDM_MCS99       = 252,
++	WL_RATE_P_2X4_SDM_MCS100      = 253,
++
++	WL_RATE_2X4_VHT0SS2           = 244,
++	WL_RATE_2X4_VHT1SS2           = 245,
++	WL_RATE_2X4_VHT2SS2           = 246,
++	WL_RATE_2X4_VHT3SS2           = 247,
++	WL_RATE_2X4_VHT4SS2           = 248,
++	WL_RATE_2X4_VHT5SS2           = 249,
++	WL_RATE_2X4_VHT6SS2           = 250,
++	WL_RATE_2X4_VHT7SS2           = 251,
++	WL_RATE_2X4_VHT8SS2           = 252,
++	WL_RATE_2X4_VHT9SS2           = 253,
++	WL_RATE_P_2X4_VHT10SS2        = 254,
++	WL_RATE_P_2X4_VHT11SS2        = 255,
++
++	/* 3 Streams expanded + 1 */
++	WL_RATE_3X4_SDM_MCS16         = 256,
++	WL_RATE_3X4_SDM_MCS17         = 257,
++	WL_RATE_3X4_SDM_MCS18         = 258,
++	WL_RATE_3X4_SDM_MCS19         = 259,
++	WL_RATE_3X4_SDM_MCS20         = 260,
++	WL_RATE_3X4_SDM_MCS21         = 261,
++	WL_RATE_3X4_SDM_MCS22         = 262,
++	WL_RATE_3X4_SDM_MCS23         = 263,
++	WL_RATE_P_3X4_SDM_MCS101      = 264,
++	WL_RATE_P_3X4_SDM_MCS102      = 265,
++
++	WL_RATE_3X4_VHT0SS3           = 256,
++	WL_RATE_3X4_VHT1SS3           = 257,
++	WL_RATE_3X4_VHT2SS3           = 258,
++	WL_RATE_3X4_VHT3SS3           = 259,
++	WL_RATE_3X4_VHT4SS3           = 260,
++	WL_RATE_3X4_VHT5SS3           = 261,
++	WL_RATE_3X4_VHT6SS3           = 262,
++	WL_RATE_3X4_VHT7SS3           = 263,
++	WL_RATE_3X4_VHT8SS3           = 264,
++	WL_RATE_3X4_VHT9SS3           = 265,
++	WL_RATE_P_3X4_VHT10SS3        = 266,
++	WL_RATE_P_3X4_VHT11SS3        = 267,
++
++
++	/* 4 Streams */
++	WL_RATE_4X4_SDM_MCS24         = 268,
++	WL_RATE_4X4_SDM_MCS25         = 269,
++	WL_RATE_4X4_SDM_MCS26         = 270,
++	WL_RATE_4X4_SDM_MCS27         = 271,
++	WL_RATE_4X4_SDM_MCS28         = 272,
++	WL_RATE_4X4_SDM_MCS29         = 273,
++	WL_RATE_4X4_SDM_MCS30         = 274,
++	WL_RATE_4X4_SDM_MCS31         = 275,
++	WL_RATE_P_4X4_SDM_MCS103      = 276,
++	WL_RATE_P_4X4_SDM_MCS104      = 277,
++
++	WL_RATE_4X4_VHT0SS4           = 268,
++	WL_RATE_4X4_VHT1SS4           = 269,
++	WL_RATE_4X4_VHT2SS4           = 270,
++	WL_RATE_4X4_VHT3SS4           = 271,
++	WL_RATE_4X4_VHT4SS4           = 272,
++	WL_RATE_4X4_VHT5SS4           = 273,
++	WL_RATE_4X4_VHT6SS4           = 274,
++	WL_RATE_4X4_VHT7SS4           = 275,
++	WL_RATE_4X4_VHT8SS4           = 276,
++	WL_RATE_4X4_VHT9SS4           = 277,
++	WL_RATE_P_4X4_VHT10SS4        = 278,
++	WL_RATE_P_4X4_VHT11SS4        = 279,
++
++
++	/****************************
++	 * TX Beamforming, 4 chains *
++	 ****************************
++	 */
++
++	/* 1 Stream expanded + 3 */
++	WL_RATE_1X4_TXBF_OFDM_6       = 280,
++	WL_RATE_1X4_TXBF_OFDM_9       = 281,
++	WL_RATE_1X4_TXBF_OFDM_12      = 282,
++	WL_RATE_1X4_TXBF_OFDM_18      = 283,
++	WL_RATE_1X4_TXBF_OFDM_24      = 284,
++	WL_RATE_1X4_TXBF_OFDM_36      = 285,
++	WL_RATE_1X4_TXBF_OFDM_48      = 286,
++	WL_RATE_1X4_TXBF_OFDM_54      = 287,
++
++	WL_RATE_1X4_TXBF_MCS0         = 288,
++	WL_RATE_1X4_TXBF_MCS1         = 289,
++	WL_RATE_1X4_TXBF_MCS2         = 290,
++	WL_RATE_1X4_TXBF_MCS3         = 291,
++	WL_RATE_1X4_TXBF_MCS4         = 292,
++	WL_RATE_1X4_TXBF_MCS5         = 293,
++	WL_RATE_1X4_TXBF_MCS6         = 294,
++	WL_RATE_1X4_TXBF_MCS7         = 295,
++	WL_RATE_P_1X4_TXBF_MCS87      = 296,
++	WL_RATE_P_1X4_TXBF_MCS88      = 297,
++
++	WL_RATE_1X4_TXBF_VHT0SS1      = 288,
++	WL_RATE_1X4_TXBF_VHT1SS1      = 289,
++	WL_RATE_1X4_TXBF_VHT2SS1      = 290,
++	WL_RATE_1X4_TXBF_VHT3SS1      = 291,
++	WL_RATE_1X4_TXBF_VHT4SS1      = 292,
++	WL_RATE_1X4_TXBF_VHT5SS1      = 293,
++	WL_RATE_1X4_TXBF_VHT6SS1      = 294,
++	WL_RATE_1X4_TXBF_VHT7SS1      = 295,
++	WL_RATE_1X4_TXBF_VHT8SS1      = 296,
++	WL_RATE_1X4_TXBF_VHT9SS1      = 297,
++	WL_RATE_P_1X4_TXBF_VHT10SS1   = 298,
++	WL_RATE_P_1X4_TXBF_VHT11SS1   = 299,
++
++	/* 2 Streams expanded + 2 */
++	WL_RATE_2X4_TXBF_SDM_MCS8     = 300,
++	WL_RATE_2X4_TXBF_SDM_MCS9     = 301,
++	WL_RATE_2X4_TXBF_SDM_MCS10    = 302,
++	WL_RATE_2X4_TXBF_SDM_MCS11    = 303,
++	WL_RATE_2X4_TXBF_SDM_MCS12    = 304,
++	WL_RATE_2X4_TXBF_SDM_MCS13    = 305,
++	WL_RATE_2X4_TXBF_SDM_MCS14    = 306,
++	WL_RATE_2X4_TXBF_SDM_MCS15    = 307,
++	WL_RATE_P_2X4_TXBF_SDM_MCS99  = 308,
++	WL_RATE_P_2X4_TXBF_SDM_MCS100 = 309,
++
++	WL_RATE_2X4_TXBF_VHT0SS2      = 300,
++	WL_RATE_2X4_TXBF_VHT1SS2      = 301,
++	WL_RATE_2X4_TXBF_VHT2SS2      = 302,
++	WL_RATE_2X4_TXBF_VHT3SS2      = 303,
++	WL_RATE_2X4_TXBF_VHT4SS2      = 304,
++	WL_RATE_2X4_TXBF_VHT5SS2      = 305,
++	WL_RATE_2X4_TXBF_VHT6SS2      = 306,
++	WL_RATE_2X4_TXBF_VHT7SS2      = 307,
++	WL_RATE_2X4_TXBF_VHT8SS2      = 308,
++	WL_RATE_2X4_TXBF_VHT9SS2      = 309,
++	WL_RATE_P_2X4_TXBF_VHT10SS2   = 310,
++	WL_RATE_P_2X4_TXBF_VHT11SS2   = 311,
++
++	/* 3 Streams expanded + 1 */
++	WL_RATE_3X4_TXBF_SDM_MCS16    = 312,
++	WL_RATE_3X4_TXBF_SDM_MCS17    = 313,
++	WL_RATE_3X4_TXBF_SDM_MCS18    = 314,
++	WL_RATE_3X4_TXBF_SDM_MCS19    = 315,
++	WL_RATE_3X4_TXBF_SDM_MCS20    = 316,
++	WL_RATE_3X4_TXBF_SDM_MCS21    = 317,
++	WL_RATE_3X4_TXBF_SDM_MCS22    = 318,
++	WL_RATE_3X4_TXBF_SDM_MCS23    = 319,
++	WL_RATE_P_3X4_TXBF_SDM_MCS101 = 320,
++	WL_RATE_P_3X4_TXBF_SDM_MCS102 = 321,
++
++	WL_RATE_3X4_TXBF_VHT0SS3      = 312,
++	WL_RATE_3X4_TXBF_VHT1SS3      = 313,
++	WL_RATE_3X4_TXBF_VHT2SS3      = 314,
++	WL_RATE_3X4_TXBF_VHT3SS3      = 315,
++	WL_RATE_3X4_TXBF_VHT4SS3      = 316,
++	WL_RATE_3X4_TXBF_VHT5SS3      = 317,
++	WL_RATE_3X4_TXBF_VHT6SS3      = 318,
++	WL_RATE_3X4_TXBF_VHT7SS3      = 319,
++	WL_RATE_P_3X4_TXBF_VHT8SS3    = 320,
++	WL_RATE_P_3X4_TXBF_VHT9SS3    = 321,
++	WL_RATE_P_3X4_TXBF_VHT10SS3   = 322,
++	WL_RATE_P_3X4_TXBF_VHT11SS3   = 323,
++
++	/* 4 Streams */
++	WL_RATE_4X4_TXBF_SDM_MCS24    = 324,
++	WL_RATE_4X4_TXBF_SDM_MCS25    = 325,
++	WL_RATE_4X4_TXBF_SDM_MCS26    = 326,
++	WL_RATE_4X4_TXBF_SDM_MCS27    = 327,
++	WL_RATE_4X4_TXBF_SDM_MCS28    = 328,
++	WL_RATE_4X4_TXBF_SDM_MCS29    = 329,
++	WL_RATE_4X4_TXBF_SDM_MCS30    = 330,
++	WL_RATE_4X4_TXBF_SDM_MCS31    = 331,
++	WL_RATE_P_4X4_TXBF_SDM_MCS103 = 332,
++	WL_RATE_P_4X4_TXBF_SDM_MCS104 = 333,
++
++	WL_RATE_4X4_TXBF_VHT0SS4      = 324,
++	WL_RATE_4X4_TXBF_VHT1SS4      = 325,
++	WL_RATE_4X4_TXBF_VHT2SS4      = 326,
++	WL_RATE_4X4_TXBF_VHT3SS4      = 327,
++	WL_RATE_4X4_TXBF_VHT4SS4      = 328,
++	WL_RATE_4X4_TXBF_VHT5SS4      = 329,
++	WL_RATE_4X4_TXBF_VHT6SS4      = 330,
++	WL_RATE_4X4_TXBF_VHT7SS4      = 331,
++	WL_RATE_P_4X4_TXBF_VHT8SS4    = 332,
++	WL_RATE_P_4X4_TXBF_VHT9SS4    = 333,
++	WL_RATE_P_4X4_TXBF_VHT10SS4   = 334,
++	WL_RATE_P_4X4_TXBF_VHT11SS4   = 335
++
++} clm_rates_t;
++
++/* Number of rate codes */
++#define WL_NUMRATES 336
++
++#ifdef __cplusplus
++}
++#endif /* __cplusplus */
++
++#endif /* _bcmwifi_rates_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/bcmxtlv.c b/module_drivers/drivers/net/wireless/bcmdhd/bcmxtlv.c
+new file mode 100644
+index 000000000..d6bef6fa2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/bcmxtlv.c
+@@ -0,0 +1,457 @@
++/*
++ * Driver O/S-independent utility routines
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmxtlv.c 628611 2016-03-31 17:53:25Z $
++ */
++
++#include <bcm_cfg.h>
++
++#include <typedefs.h>
++#include <bcmdefs.h>
++
++#include <stdarg.h>
++
++#ifdef BCMDRIVER
++#include <osl.h>
++#else /* !BCMDRIVER */
++	#include <stdlib.h> /* AS!!! */
++#include <stdio.h>
++#include <string.h>
++#include <stdlib.h>
++#ifndef ASSERT
++#define ASSERT(exp)
++#endif
++INLINE void* MALLOCZ(void *o, size_t s) { BCM_REFERENCE(o); return calloc(1, s); }
++INLINE void MFREE(void *o, void *p, size_t s) { BCM_REFERENCE(o); BCM_REFERENCE(s); free(p); }
++#endif /* !BCMDRIVER */
++
++#include <bcmendian.h>
++#include <bcmutils.h>
++
++static INLINE int bcm_xtlv_size_for_data(int dlen, bcm_xtlv_opts_t opts)
++{
++	return ((opts & BCM_XTLV_OPTION_ALIGN32) ? ALIGN_SIZE(dlen + BCM_XTLV_HDR_SIZE, 4)
++		: (dlen + BCM_XTLV_HDR_SIZE));
++}
++
++bcm_xtlv_t *
++bcm_next_xtlv(bcm_xtlv_t *elt, int *buflen, bcm_xtlv_opts_t opts)
++{
++	int sz;
++	/* advance to next elt */
++	sz = BCM_XTLV_SIZE(elt, opts);
++	elt = (bcm_xtlv_t*)((uint8 *)elt + sz);
++	*buflen -= sz;
++
++	/* validate next elt */
++	if (!bcm_valid_xtlv(elt, *buflen, opts))
++		return NULL;
++
++	return elt;
++}
++
++int
++bcm_xtlv_buf_init(bcm_xtlvbuf_t *tlv_buf, uint8 *buf, uint16 len, bcm_xtlv_opts_t opts)
++{
++	if (!tlv_buf || !buf || !len)
++		return BCME_BADARG;
++
++	tlv_buf->opts = opts;
++	tlv_buf->size = len;
++	tlv_buf->head = buf;
++	tlv_buf->buf  = buf;
++	return BCME_OK;
++}
++
++uint16
++bcm_xtlv_buf_len(bcm_xtlvbuf_t *tbuf)
++{
++	if (tbuf == NULL) return 0;
++	return (uint16)(tbuf->buf - tbuf->head);
++}
++uint16
++bcm_xtlv_buf_rlen(bcm_xtlvbuf_t *tbuf)
++{
++	if (tbuf == NULL) return 0;
++	return tbuf->size - bcm_xtlv_buf_len(tbuf);
++}
++uint8 *
++bcm_xtlv_buf(bcm_xtlvbuf_t *tbuf)
++{
++	if (tbuf == NULL) return NULL;
++	return tbuf->buf;
++}
++uint8 *
++bcm_xtlv_head(bcm_xtlvbuf_t *tbuf)
++{
++	if (tbuf == NULL) return NULL;
++	return tbuf->head;
++}
++int
++bcm_xtlv_put_data(bcm_xtlvbuf_t *tbuf, uint16 type, const void *data, uint16 dlen)
++{
++	bcm_xtlv_t *xtlv;
++	int size;
++
++	if (tbuf == NULL)
++		return BCME_BADARG;
++	size = bcm_xtlv_size_for_data(dlen, tbuf->opts);
++	if (bcm_xtlv_buf_rlen(tbuf) < size)
++		return BCME_NOMEM;
++	xtlv = (bcm_xtlv_t *)bcm_xtlv_buf(tbuf);
++	xtlv->id = htol16(type);
++	xtlv->len = htol16(dlen);
++	memcpy(xtlv->data, data, dlen);
++	tbuf->buf += size;
++	return BCME_OK;
++}
++int
++bcm_xtlv_put_8(bcm_xtlvbuf_t *tbuf, uint16 type, const int8 data)
++{
++	bcm_xtlv_t *xtlv;
++	int size;
++
++	if (tbuf == NULL)
++		return BCME_BADARG;
++	size = bcm_xtlv_size_for_data(1, tbuf->opts);
++	if (bcm_xtlv_buf_rlen(tbuf) < size)
++		return BCME_NOMEM;
++	xtlv = (bcm_xtlv_t *)bcm_xtlv_buf(tbuf);
++	xtlv->id = htol16(type);
++	xtlv->len = htol16(sizeof(data));
++	xtlv->data[0] = data;
++	tbuf->buf += size;
++	return BCME_OK;
++}
++int
++bcm_xtlv_put_16(bcm_xtlvbuf_t *tbuf, uint16 type, const int16 data)
++{
++	bcm_xtlv_t *xtlv;
++	int size;
++
++	if (tbuf == NULL)
++		return BCME_BADARG;
++	size = bcm_xtlv_size_for_data(2, tbuf->opts);
++	if (bcm_xtlv_buf_rlen(tbuf) < size)
++		return BCME_NOMEM;
++
++	xtlv = (bcm_xtlv_t *)bcm_xtlv_buf(tbuf);
++	xtlv->id = htol16(type);
++	xtlv->len = htol16(sizeof(data));
++	htol16_ua_store(data, xtlv->data);
++	tbuf->buf += size;
++	return BCME_OK;
++}
++int
++bcm_xtlv_put_32(bcm_xtlvbuf_t *tbuf, uint16 type, const int32 data)
++{
++	bcm_xtlv_t *xtlv;
++	int size;
++
++	if (tbuf == NULL)
++		return BCME_BADARG;
++	size = bcm_xtlv_size_for_data(4, tbuf->opts);
++	if (bcm_xtlv_buf_rlen(tbuf) < size)
++		return BCME_NOMEM;
++	xtlv = (bcm_xtlv_t *)bcm_xtlv_buf(tbuf);
++	xtlv->id = htol16(type);
++	xtlv->len = htol16(sizeof(data));
++	htol32_ua_store(data, xtlv->data);
++	tbuf->buf += size;
++	return BCME_OK;
++}
++
++/*
++ *  upacks xtlv record from buf checks the type
++ *  copies data to callers buffer
++ *  advances tlv pointer to next record
++ *  caller's resposible for dst space check
++ */
++int
++bcm_unpack_xtlv_entry(uint8 **tlv_buf, uint16 xpct_type, uint16 xpct_len, void *dst,
++	bcm_xtlv_opts_t opts)
++{
++	bcm_xtlv_t *ptlv = (bcm_xtlv_t *)*tlv_buf;
++	uint16 len;
++	uint16 type;
++
++	ASSERT(ptlv);
++	/* tlv headr is always packed in LE order */
++	len = ltoh16(ptlv->len);
++	type = ltoh16(ptlv->id);
++	if	(len == 0) {
++		/* z-len tlv headers: allow, but don't process */
++		printf("z-len, skip unpack\n");
++	} else  {
++		if ((type != xpct_type) ||
++			(len > xpct_len)) {
++			printf("xtlv_unpack Error: found[type:%d,len:%d] != xpct[type:%d,len:%d]\n",
++				type, len, xpct_type, xpct_len);
++			return BCME_BADARG;
++		}
++		/* copy tlv record to caller's buffer */
++		memcpy(dst, ptlv->data, ptlv->len);
++	}
++	*tlv_buf = (uint8*)(*tlv_buf) + BCM_XTLV_SIZE(ptlv, opts);
++	return BCME_OK;
++}
++
++/*
++ *  packs user data into tlv record
++ *  advances tlv pointer to next xtlv slot
++ *  buflen is used for tlv_buf space check
++ */
++int
++bcm_pack_xtlv_entry(uint8 **tlv_buf, uint16 *buflen, uint16 type, uint16 len, void *src,
++	bcm_xtlv_opts_t opts)
++{
++	bcm_xtlv_t *ptlv = (bcm_xtlv_t *)*tlv_buf;
++	int size;
++
++	ASSERT(ptlv);
++	ASSERT(src);
++
++	size = bcm_xtlv_size_for_data(len, opts);
++
++	/* copy data from tlv buffer to dst provided by user */
++	if (size > *buflen) {
++		printf("bcm_pack_xtlv_entry: no space tlv_buf: requested:%d, available:%d\n",
++			size, *buflen);
++		return BCME_BADLEN;
++	}
++	ptlv->id = htol16(type);
++	ptlv->len = htol16(len);
++
++	/* copy callers data */
++	memcpy(ptlv->data, src, len);
++
++	/* advance callers pointer to tlv buff */
++	*tlv_buf = (uint8*)(*tlv_buf) + size;
++	/* decrement the len */
++	*buflen -= (uint16)size;
++	return BCME_OK;
++}
++
++/*
++ *  unpack all xtlv records from the issue a callback
++ *  to set function one call per found tlv record
++ */
++int
++bcm_unpack_xtlv_buf(void *ctx, uint8 *tlv_buf, uint16 buflen, bcm_xtlv_opts_t opts,
++	bcm_xtlv_unpack_cbfn_t *cbfn)
++{
++	uint16 len;
++	uint16 type;
++	int res = BCME_OK;
++	int size;
++	bcm_xtlv_t *ptlv;
++	int sbuflen = buflen;
++
++	ASSERT(!buflen || tlv_buf);
++	ASSERT(!buflen || cbfn);
++
++	while (sbuflen >= (int)BCM_XTLV_HDR_SIZE) {
++		ptlv = (bcm_xtlv_t *)tlv_buf;
++
++		/* tlv header is always packed in LE order */
++		len = ltoh16(ptlv->len);
++		type = ltoh16(ptlv->id);
++
++		size = bcm_xtlv_size_for_data(len, opts);
++
++		sbuflen -= size;
++		/* check for possible buffer overrun */
++		if (sbuflen < 0)
++			break;
++
++		if ((res = cbfn(ctx, ptlv->data, type, len)) != BCME_OK)
++			break;
++		tlv_buf = (uint8*)tlv_buf + size;
++	}
++	return res;
++}
++
++int
++bcm_pack_xtlv_buf(void *ctx, void *tlv_buf, uint16 buflen, bcm_xtlv_opts_t opts,
++	bcm_pack_xtlv_next_info_cbfn_t get_next, bcm_pack_xtlv_pack_next_cbfn_t pack_next,
++	int *outlen)
++{
++	int res = BCME_OK;
++	uint16 tlv_id;
++	uint16 tlv_len;
++	uint8 *startp;
++	uint8 *endp;
++	uint8 *buf;
++	bool more;
++	int size;
++
++	ASSERT(get_next && pack_next);
++
++	buf = (uint8 *)tlv_buf;
++	startp = buf;
++	endp = (uint8 *)buf + buflen;
++	more = TRUE;
++	while (more && (buf < endp)) {
++		more = get_next(ctx, &tlv_id, &tlv_len);
++		size = bcm_xtlv_size_for_data(tlv_len, opts);
++		if ((buf + size) > endp) {
++			res = BCME_BUFTOOSHORT;
++			goto done;
++		}
++
++		htol16_ua_store(tlv_id, buf);
++		htol16_ua_store(tlv_len, buf + sizeof(tlv_id));
++		pack_next(ctx, tlv_id, tlv_len, buf + BCM_XTLV_HDR_SIZE);
++		buf += size;
++	}
++
++	if (more)
++		res = BCME_BUFTOOSHORT;
++
++done:
++	if (outlen) {
++		*outlen = (int)(buf - startp);
++	}
++	return res;
++}
++
++/*
++ *  pack xtlv buffer from memory according to xtlv_desc_t
++ */
++int
++bcm_pack_xtlv_buf_from_mem(void **tlv_buf, uint16 *buflen, xtlv_desc_t *items,
++	bcm_xtlv_opts_t opts)
++{
++	int res = BCME_OK;
++	uint8 *ptlv = (uint8 *)*tlv_buf;
++
++	while (items->type != 0) {
++		if ((items->len > 0) && (res = bcm_pack_xtlv_entry(&ptlv,
++			buflen, items->type,
++			items->len, items->ptr, opts) != BCME_OK)) {
++			break;
++		}
++		items++;
++	}
++	*tlv_buf = ptlv; /* update the external pointer */
++	return res;
++}
++
++/*
++ *  unpack xtlv buffer to memory according to xtlv_desc_t
++ *
++ */
++int
++bcm_unpack_xtlv_buf_to_mem(void *tlv_buf, int *buflen, xtlv_desc_t *items, bcm_xtlv_opts_t opts)
++{
++	int res = BCME_OK;
++	bcm_xtlv_t *elt;
++
++	elt =  bcm_valid_xtlv((bcm_xtlv_t *)tlv_buf, *buflen, opts) ? (bcm_xtlv_t *)tlv_buf : NULL;
++	if (!elt || !items) {
++		res = BCME_BADARG;
++		return res;
++	}
++
++	for (; elt != NULL && res == BCME_OK; elt = bcm_next_xtlv(elt, buflen, opts)) {
++		/*  find matches in desc_t items  */
++		xtlv_desc_t *dst_desc = items;
++		uint16 len = ltoh16(elt->len);
++
++		while (dst_desc->type != 0) {
++			if (ltoh16(elt->id) == dst_desc->type) {
++				if (len != dst_desc->len) {
++					res = BCME_BADLEN;
++				} else {
++					memcpy(dst_desc->ptr, elt->data, len);
++				}
++				break;
++			}
++			dst_desc++;
++		}
++	}
++
++	if (res == BCME_OK && *buflen != 0)
++		res =  BCME_BUFTOOSHORT;
++
++	return res;
++}
++
++/*
++ * return data pointer of a given ID from xtlv buffer.
++ * If the specified xTLV ID is found, on return *data_len_out will contain
++ * the the data length of the xTLV ID.
++ */
++void *
++bcm_get_data_from_xtlv_buf(uint8 *tlv_buf, uint16 buflen, uint16 id,
++	uint16 *datalen_out, bcm_xtlv_opts_t opts)
++{
++	void *retptr = NULL;
++	uint16 type, len;
++	int size;
++	bcm_xtlv_t *ptlv;
++	int sbuflen = buflen;
++
++	while (sbuflen >= (int)BCM_XTLV_HDR_SIZE) {
++		ptlv = (bcm_xtlv_t *)tlv_buf;
++
++		/* tlv header is always packed in LE order */
++		type = ltoh16(ptlv->id);
++		len = ltoh16(ptlv->len);
++		size = bcm_xtlv_size_for_data(len, opts);
++
++		sbuflen -= size;
++		/* check for possible buffer overrun */
++		if (sbuflen < 0) {
++			printf("%s %d: Invalid sbuflen %d\n",
++				__FUNCTION__, __LINE__, sbuflen);
++			break;
++		}
++
++		if (id == type) {
++			retptr = ptlv->data;
++			if (datalen_out) {
++				*datalen_out = len;
++			}
++			break;
++		}
++		tlv_buf += size;
++	}
++
++	return retptr;
++}
++
++int bcm_xtlv_size(const bcm_xtlv_t *elt, bcm_xtlv_opts_t opts)
++{
++	int size; /* entire size of the XTLV including header, data, and optional padding */
++	int len; /* XTLV's value real length wthout padding */
++
++	len = BCM_XTLV_LEN(elt);
++
++	size = bcm_xtlv_size_for_data(len, opts);
++
++	return size;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dbus.c b/module_drivers/drivers/net/wireless/bcmdhd/dbus.c
+new file mode 100644
+index 000000000..8e2102fe1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dbus.c
+@@ -0,0 +1,2904 @@
++/** @file dbus.c
++ *
++ * Hides details of USB / SDIO / SPI interfaces and OS details. It is intended to shield details and
++ * provide the caller with one common bus interface for all dongle devices. In practice, it is only
++ * used for USB interfaces. DBUS is not a protocol, but an abstraction layer.
++ *
++ * Copyright (C) 1999-2016, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dbus.c 553311 2015-04-29 10:23:08Z $
++ */
++
++
++#include "osl.h"
++#include "dbus.h"
++#include <bcmutils.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_proto.h>
++#ifdef PROP_TXSTATUS /* a form of flow control between host and dongle */
++#include <dhd_wlfc.h>
++#endif
++#include <dhd_config.h>
++
++#if defined(BCM_REQUEST_FW)
++#include <bcmsrom_fmt.h>
++#include <trxhdr.h>
++#include <usbrdl.h>
++#include <bcmendian.h>
++#include <sbpcmcia.h>
++#include <bcmnvram.h>
++#include <bcmdevs.h>
++#endif 
++
++
++
++#if defined(BCM_REQUEST_FW)
++#ifndef VARS_MAX
++#define VARS_MAX            8192
++#endif
++#endif 
++
++#ifdef DBUS_USB_LOOPBACK
++extern bool is_loopback_pkt(void *buf);
++extern int matches_loopback_pkt(void *buf);
++#endif
++
++/** General info for all BUS types */
++typedef struct dbus_irbq {
++	dbus_irb_t *head;
++	dbus_irb_t *tail;
++	int cnt;
++} dbus_irbq_t;
++
++/**
++ * This private structure dhd_bus_t is also declared in dbus_usb_linux.c.
++ * All the fields must be consistent in both declarations.
++ */
++typedef struct dhd_bus {
++	dbus_pub_t   pub; /* MUST BE FIRST */
++	dhd_pub_t *dhd;
++
++	void        *cbarg;
++	dbus_callbacks_t *cbs; /* callbacks to higher level, e.g. dhd_linux.c */
++	void        *bus_info;
++	dbus_intf_t *drvintf;  /* callbacks to lower level, e.g. dbus_usb.c or dbus_usb_linux.c */
++	uint8       *fw;
++	int         fwlen;
++	uint32      errmask;
++	int         rx_low_watermark;  /* avoid rx overflow by filling rx with free IRBs */
++	int         tx_low_watermark;
++	bool        txoff;
++	bool        txoverride;   /* flow control related */
++	bool        rxoff;
++	bool        tx_timer_ticking;
++
++
++	dbus_irbq_t *rx_q;
++	dbus_irbq_t *tx_q;
++
++	uint8        *nvram;
++	int          nvram_len;
++	uint8        *image;  /* buffer for combine fw and nvram */
++	int          image_len;
++	uint8        *orig_fw;
++	int          origfw_len;
++	int          decomp_memsize;
++	dbus_extdl_t extdl;
++	int          nvram_nontxt;
++#if defined(BCM_REQUEST_FW)
++	void         *firmware;
++	void         *nvfile;
++#endif
++	char		*fw_path;		/* module_param: path to firmware image */
++	char		*nv_path;		/* module_param: path to nvram vars file */
++} dhd_bus_t;
++
++struct exec_parms {
++	union {
++		/* Can consolidate same params, if need be, but this shows
++		 * group of parameters per function
++		 */
++		struct {
++			dbus_irbq_t  *q;
++			dbus_irb_t   *b;
++		} qenq;
++
++		struct {
++			dbus_irbq_t  *q;
++		} qdeq;
++	};
++};
++
++#define EXEC_RXLOCK(info, fn, a) \
++	info->drvintf->exec_rxlock(dhd_bus->bus_info, ((exec_cb_t)fn), ((struct exec_parms *) a))
++
++#define EXEC_TXLOCK(info, fn, a) \
++	info->drvintf->exec_txlock(dhd_bus->bus_info, ((exec_cb_t)fn), ((struct exec_parms *) a))
++
++/*
++ * Callbacks common for all BUS
++ */
++static void dbus_if_send_irb_timeout(void *handle, dbus_irb_tx_t *txirb);
++static void dbus_if_send_irb_complete(void *handle, dbus_irb_tx_t *txirb, int status);
++static void dbus_if_recv_irb_complete(void *handle, dbus_irb_rx_t *rxirb, int status);
++static void dbus_if_errhandler(void *handle, int err);
++static void dbus_if_ctl_complete(void *handle, int type, int status);
++static void dbus_if_state_change(void *handle, int state);
++static void *dbus_if_pktget(void *handle, uint len, bool send);
++static void dbus_if_pktfree(void *handle, void *p, bool send);
++static struct dbus_irb *dbus_if_getirb(void *cbarg, bool send);
++static void dbus_if_rxerr_indicate(void *handle, bool on);
++
++void * dhd_dbus_probe_cb(void *arg, const char *desc, uint32 bustype,
++	uint16 bus_no, uint16 slot, uint32 hdrlen);
++void dhd_dbus_disconnect_cb(void *arg);
++void dbus_detach(dhd_bus_t *pub);
++
++/** functions in this file that are called by lower DBUS levels, e.g. dbus_usb.c */
++static dbus_intf_callbacks_t dbus_intf_cbs = {
++	dbus_if_send_irb_timeout,
++	dbus_if_send_irb_complete,
++	dbus_if_recv_irb_complete,
++	dbus_if_errhandler,
++	dbus_if_ctl_complete,
++	dbus_if_state_change,
++	NULL,			/* isr */
++	NULL,			/* dpc */
++	NULL,			/* watchdog */
++	dbus_if_pktget,
++	dbus_if_pktfree,
++	dbus_if_getirb,
++	dbus_if_rxerr_indicate
++};
++
++/*
++ * Need global for probe() and disconnect() since
++ * attach() is not called at probe and detach()
++ * can be called inside disconnect()
++ */
++static dbus_intf_t     *g_busintf = NULL;
++static probe_cb_t      probe_cb = NULL;
++static disconnect_cb_t disconnect_cb = NULL;
++static void            *probe_arg = NULL;
++static void            *disc_arg = NULL;
++
++#if defined(BCM_REQUEST_FW)
++int8 *nonfwnvram = NULL; /* stand-alone multi-nvram given with driver load */
++int nonfwnvramlen = 0;
++#endif /* #if defined(BCM_REQUEST_FW) */
++
++static void* q_enq(dbus_irbq_t *q, dbus_irb_t *b);
++static void* q_enq_exec(struct exec_parms *args);
++static dbus_irb_t*q_deq(dbus_irbq_t *q);
++static void* q_deq_exec(struct exec_parms *args);
++static int   dbus_tx_timer_init(dhd_bus_t *dhd_bus);
++static int   dbus_tx_timer_start(dhd_bus_t *dhd_bus, uint timeout);
++static int   dbus_tx_timer_stop(dhd_bus_t *dhd_bus);
++static int   dbus_irbq_init(dhd_bus_t *dhd_bus, dbus_irbq_t *q, int nq, int size_irb);
++static int   dbus_irbq_deinit(dhd_bus_t *dhd_bus, dbus_irbq_t *q, int size_irb);
++static int   dbus_rxirbs_fill(dhd_bus_t *dhd_bus);
++static int   dbus_send_irb(dbus_pub_t *pub, uint8 *buf, int len, void *pkt, void *info);
++static void  dbus_disconnect(void *handle);
++static void *dbus_probe(void *arg, const char *desc, uint32 bustype,
++	uint16 bus_no, uint16 slot, uint32 hdrlen);
++
++#if defined(BCM_REQUEST_FW)
++extern char * dngl_firmware;
++extern unsigned int dngl_fwlen;
++#ifndef EXTERNAL_FW_PATH
++static int dbus_get_nvram(dhd_bus_t *dhd_bus);
++static int dbus_jumbo_nvram(dhd_bus_t *dhd_bus);
++static int dbus_otp(dhd_bus_t *dhd_bus, uint16 *boardtype, uint16 *boardrev);
++static int dbus_select_nvram(dhd_bus_t *dhd_bus, int8 *jumbonvram, int jumbolen,
++uint16 boardtype, uint16 boardrev, int8 **nvram, int *nvram_len);
++#endif /* !EXTERNAL_FW_PATH */
++extern int dbus_zlib_decomp(dhd_bus_t *dhd_bus);
++extern void *dbus_zlib_calloc(int num, int size);
++extern void dbus_zlib_free(void *ptr);
++#endif
++
++/* function */
++void
++dbus_flowctrl_tx(void *dbi, bool on)
++{
++	dhd_bus_t *dhd_bus = dbi;
++
++	if (dhd_bus == NULL)
++		return;
++
++	DBUSTRACE(("%s on %d\n", __FUNCTION__, on));
++
++	if (dhd_bus->txoff == on)
++		return;
++
++	dhd_bus->txoff = on;
++
++	if (dhd_bus->cbs && dhd_bus->cbs->txflowcontrol)
++		dhd_bus->cbs->txflowcontrol(dhd_bus->cbarg, on);
++}
++
++/**
++ * if lower level DBUS signaled a rx error, more free rx IRBs should be allocated or flow control
++ * should kick in to make more free rx IRBs available.
++ */
++static void
++dbus_if_rxerr_indicate(void *handle, bool on)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) handle;
++
++	DBUSTRACE(("%s, on %d\n", __FUNCTION__, on));
++
++	if (dhd_bus == NULL)
++		return;
++
++	if (dhd_bus->txoverride == on)
++		return;
++
++	dhd_bus->txoverride = on;	/* flow control */
++
++	if (!on)
++		dbus_rxirbs_fill(dhd_bus);
++
++}
++
++/** q_enq()/q_deq() are executed with protection via exec_rxlock()/exec_txlock() */
++static void*
++q_enq(dbus_irbq_t *q, dbus_irb_t *b)
++{
++	ASSERT(q->tail != b);
++	ASSERT(b->next == NULL);
++	b->next = NULL;
++	if (q->tail) {
++		q->tail->next = b;
++		q->tail = b;
++	} else
++		q->head = q->tail = b;
++
++	q->cnt++;
++
++	return b;
++}
++
++static void*
++q_enq_exec(struct exec_parms *args)
++{
++	return q_enq(args->qenq.q, args->qenq.b);
++}
++
++static dbus_irb_t*
++q_deq(dbus_irbq_t *q)
++{
++	dbus_irb_t *b;
++
++	b = q->head;
++	if (b) {
++		q->head = q->head->next;
++		b->next = NULL;
++
++		if (q->head == NULL)
++			q->tail = q->head;
++
++		q->cnt--;
++	}
++	return b;
++}
++
++static void*
++q_deq_exec(struct exec_parms *args)
++{
++	return q_deq(args->qdeq.q);
++}
++
++/**
++ * called during attach phase. Status @ Dec 2012: this function does nothing since for all of the
++ * lower DBUS levels dhd_bus->drvintf->tx_timer_init is NULL.
++ */
++static int
++dbus_tx_timer_init(dhd_bus_t *dhd_bus)
++{
++	if (dhd_bus && dhd_bus->drvintf && dhd_bus->drvintf->tx_timer_init)
++		return dhd_bus->drvintf->tx_timer_init(dhd_bus->bus_info);
++	else
++		return DBUS_ERR;
++}
++
++static int
++dbus_tx_timer_start(dhd_bus_t *dhd_bus, uint timeout)
++{
++	if (dhd_bus == NULL)
++		return DBUS_ERR;
++
++	if (dhd_bus->tx_timer_ticking)
++		return DBUS_OK;
++
++	if (dhd_bus->drvintf && dhd_bus->drvintf->tx_timer_start) {
++		if (dhd_bus->drvintf->tx_timer_start(dhd_bus->bus_info, timeout) == DBUS_OK) {
++			dhd_bus->tx_timer_ticking = TRUE;
++			return DBUS_OK;
++		}
++	}
++
++	return DBUS_ERR;
++}
++
++static int
++dbus_tx_timer_stop(dhd_bus_t *dhd_bus)
++{
++	if (dhd_bus == NULL)
++		return DBUS_ERR;
++
++	if (!dhd_bus->tx_timer_ticking)
++		return DBUS_OK;
++
++	if (dhd_bus->drvintf && dhd_bus->drvintf->tx_timer_stop) {
++		if (dhd_bus->drvintf->tx_timer_stop(dhd_bus->bus_info) == DBUS_OK) {
++			dhd_bus->tx_timer_ticking = FALSE;
++			return DBUS_OK;
++		}
++	}
++
++	return DBUS_ERR;
++}
++
++/** called during attach phase. */
++static int
++dbus_irbq_init(dhd_bus_t *dhd_bus, dbus_irbq_t *q, int nq, int size_irb)
++{
++	int i;
++	dbus_irb_t *irb;
++
++	ASSERT(q);
++	ASSERT(dhd_bus);
++
++	for (i = 0; i < nq; i++) {
++		/* MALLOC dbus_irb_tx or dbus_irb_rx, but cast to simple dbus_irb_t linkedlist */
++		irb = (dbus_irb_t *) MALLOC(dhd_bus->pub.osh, size_irb);
++		if (irb == NULL) {
++			ASSERT(irb);
++			return DBUS_ERR;
++		}
++		bzero(irb, size_irb);
++
++		/* q_enq() does not need to go through EXEC_xxLOCK() during init() */
++		q_enq(q, irb);
++	}
++
++	return DBUS_OK;
++}
++
++/** called during detach phase or when attach failed */
++static int
++dbus_irbq_deinit(dhd_bus_t *dhd_bus, dbus_irbq_t *q, int size_irb)
++{
++	dbus_irb_t *irb;
++
++	ASSERT(q);
++	ASSERT(dhd_bus);
++
++	/* q_deq() does not need to go through EXEC_xxLOCK()
++	 * during deinit(); all callbacks are stopped by this time
++	 */
++	while ((irb = q_deq(q)) != NULL) {
++		MFREE(dhd_bus->pub.osh, irb, size_irb);
++	}
++
++	if (q->cnt)
++		DBUSERR(("deinit: q->cnt=%d > 0\n", q->cnt));
++	return DBUS_OK;
++}
++
++/** multiple code paths require the rx queue to be filled with more free IRBs */
++static int
++dbus_rxirbs_fill(dhd_bus_t *dhd_bus)
++{
++	int err = DBUS_OK;
++
++
++	dbus_irb_rx_t *rxirb;
++	struct exec_parms args;
++
++	ASSERT(dhd_bus);
++	if (dhd_bus->pub.busstate != DBUS_STATE_UP) {
++		DBUSERR(("dbus_rxirbs_fill: DBUS not up \n"));
++		return DBUS_ERR;
++	} else if (!dhd_bus->drvintf || (dhd_bus->drvintf->recv_irb == NULL)) {
++		/* Lower edge bus interface does not support recv_irb().
++		 * No need to pre-submit IRBs in this case.
++		 */
++		return DBUS_ERR;
++	}
++
++	/* The dongle recv callback is freerunning without lock. So multiple callbacks(and this
++	 *  refill) can run in parallel. While the rxoff condition is triggered outside,
++	 *  below while loop has to check and abort posting more to avoid RPC rxq overflow.
++	 */
++	args.qdeq.q = dhd_bus->rx_q;
++	while ((!dhd_bus->rxoff) &&
++	       (rxirb = (EXEC_RXLOCK(dhd_bus, q_deq_exec, &args))) != NULL) {
++		err = dhd_bus->drvintf->recv_irb(dhd_bus->bus_info, rxirb);
++		if (err == DBUS_ERR_RXDROP || err == DBUS_ERR_RXFAIL) {
++			/* Add the the free rxirb back to the queue
++			 * and wait till later
++			 */
++			bzero(rxirb, sizeof(dbus_irb_rx_t));
++			args.qenq.q = dhd_bus->rx_q;
++			args.qenq.b = (dbus_irb_t *) rxirb;
++			EXEC_RXLOCK(dhd_bus, q_enq_exec, &args);
++			break;
++		} else if (err != DBUS_OK) {
++			int i = 0;
++			while (i++ < 100) {
++				DBUSERR(("%s :: memory leak for rxirb note?\n", __FUNCTION__));
++			}
++		}
++	}
++	return err;
++} /* dbus_rxirbs_fill */
++
++/** called when the DBUS interface state changed. */
++void
++dbus_flowctrl_rx(dbus_pub_t *pub, bool on)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++
++	if (dhd_bus == NULL)
++		return;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dhd_bus->rxoff == on)
++		return;
++
++	dhd_bus->rxoff = on;
++
++	if (dhd_bus->pub.busstate == DBUS_STATE_UP) {
++		if (!on) {
++			/* post more irbs, resume rx if necessary */
++			dbus_rxirbs_fill(dhd_bus);
++			if (dhd_bus && dhd_bus->drvintf->recv_resume) {
++				dhd_bus->drvintf->recv_resume(dhd_bus->bus_info);
++			}
++		} else {
++			/* ??? cancell posted irbs first */
++
++			if (dhd_bus && dhd_bus->drvintf->recv_stop) {
++				dhd_bus->drvintf->recv_stop(dhd_bus->bus_info);
++			}
++		}
++	}
++}
++
++/**
++ * Several code paths in this file want to send a buffer to the dongle. This function handles both
++ * sending of a buffer or a pkt.
++ */
++static int
++dbus_send_irb(dbus_pub_t *pub, uint8 *buf, int len, void *pkt, void *info)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++	int err = DBUS_OK;
++	dbus_irb_tx_t *txirb = NULL;
++	int txirb_pending;
++	struct exec_parms args;
++
++	if (dhd_bus == NULL)
++		return DBUS_ERR;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dhd_bus->pub.busstate == DBUS_STATE_UP ||
++		dhd_bus->pub.busstate == DBUS_STATE_SLEEP) {
++		args.qdeq.q = dhd_bus->tx_q;
++		if (dhd_bus->drvintf)
++			txirb = EXEC_TXLOCK(dhd_bus, q_deq_exec, &args);
++
++		if (txirb == NULL) {
++			DBUSERR(("Out of tx dbus_bufs\n"));
++			return DBUS_ERR;
++		}
++
++		if (pkt != NULL) {
++			txirb->pkt = pkt;
++			txirb->buf = NULL;
++			txirb->len = 0;
++		} else if (buf != NULL) {
++			txirb->pkt = NULL;
++			txirb->buf = buf;
++			txirb->len = len;
++		} else {
++			ASSERT(0); /* Should not happen */
++		}
++		txirb->info = info;
++		txirb->arg = NULL;
++		txirb->retry_count = 0;
++
++		if (dhd_bus->drvintf && dhd_bus->drvintf->send_irb) {
++			/* call lower DBUS level send_irb function */
++			err = dhd_bus->drvintf->send_irb(dhd_bus->bus_info, txirb);
++			if (err == DBUS_ERR_TXDROP) {
++				/* tx fail and no completion routine to clean up, reclaim irb NOW */
++				DBUSERR(("%s: send_irb failed, status = %d\n", __FUNCTION__, err));
++				bzero(txirb, sizeof(dbus_irb_tx_t));
++				args.qenq.q = dhd_bus->tx_q;
++				args.qenq.b = (dbus_irb_t *) txirb;
++				EXEC_TXLOCK(dhd_bus, q_enq_exec, &args);
++			} else {
++				dbus_tx_timer_start(dhd_bus, DBUS_TX_TIMEOUT_INTERVAL);
++				txirb_pending = dhd_bus->pub.ntxq - dhd_bus->tx_q->cnt;
++				if (txirb_pending > (dhd_bus->tx_low_watermark * 3)) {
++					dbus_flowctrl_tx(dhd_bus, TRUE);
++				}
++			}
++		}
++	} else {
++		err = DBUS_ERR_TXFAIL;
++		DBUSTRACE(("%s: bus down, send_irb failed\n", __FUNCTION__));
++	}
++
++	return err;
++} /* dbus_send_irb */
++
++#if defined(BCM_REQUEST_FW)
++
++/**
++ * Before downloading a firmware image into the dongle, the validity of the image must be checked.
++ */
++static int
++check_file(osl_t *osh, unsigned char *headers)
++{
++	struct trx_header *trx;
++	int actual_len = -1;
++
++	/* Extract trx header */
++	trx = (struct trx_header *)headers;
++	if (ltoh32(trx->magic) != TRX_MAGIC) {
++		printf("Error: trx bad hdr %x\n", ltoh32(trx->magic));
++		return -1;
++	}
++
++	headers += SIZEOF_TRX(trx);
++
++	/* TRX V1: get firmware len */
++	/* TRX V2: get firmware len and DSG/CFG lengths */
++	if (ltoh32(trx->flag_version) & TRX_UNCOMP_IMAGE) {
++		actual_len = ltoh32(trx->offsets[TRX_OFFSETS_DLFWLEN_IDX]) +
++		                     SIZEOF_TRX(trx);
++#ifdef BCMTRXV2
++		if (ISTRX_V2(trx)) {
++			actual_len += ltoh32(trx->offsets[TRX_OFFSETS_DSG_LEN_IDX]) +
++				ltoh32(trx->offsets[TRX_OFFSETS_CFG_LEN_IDX]);
++		}
++#endif
++		return actual_len;
++	}  else {
++		printf("compressed image\n");
++	}
++
++	return -1;
++}
++
++#ifdef EXTERNAL_FW_PATH
++static int
++dbus_get_fw_nvram(dhd_bus_t *dhd_bus, char *pfw_path, char *pnv_path)
++{
++	int bcmerror = -1, i;
++	uint len, total_len;
++	void *nv_image = NULL, *fw_image = NULL;
++	char *nv_memblock = NULL, *fw_memblock = NULL;
++	char *bufp;
++	bool file_exists;
++	uint8 nvram_words_pad = 0;
++	uint memblock_size = 2048;
++	uint8 *memptr;
++	int	actual_fwlen;
++	struct trx_header *hdr;
++	uint32 img_offset = 0;
++	int offset = 0;
++
++	/* For Get nvram */
++	file_exists = ((pnv_path != NULL) && (pnv_path[0] != '\0'));
++	if (file_exists) {
++		nv_image = dhd_os_open_image(pnv_path);
++		if (nv_image == NULL) {
++			printf("%s: Open nvram file failed %s\n", __FUNCTION__, pnv_path);
++			goto err;
++		}
++	}
++	nv_memblock = MALLOC(dhd_bus->pub.osh, MAX_NVRAMBUF_SIZE);
++	if (nv_memblock == NULL) {
++		DBUSERR(("%s: Failed to allocate memory %d bytes\n",
++		           __FUNCTION__, MAX_NVRAMBUF_SIZE));
++		goto err;
++	}
++	len = dhd_os_get_image_block(nv_memblock, MAX_NVRAMBUF_SIZE, nv_image);
++	if (len > 0 && len < MAX_NVRAMBUF_SIZE) {
++		bufp = (char *)nv_memblock;
++		bufp[len] = 0;
++		dhd_bus->nvram_len = process_nvram_vars(bufp, len);
++		if (dhd_bus->nvram_len % 4)
++			nvram_words_pad = 4 - dhd_bus->nvram_len % 4;
++	} else {
++		DBUSERR(("%s: error reading nvram file: %d\n", __FUNCTION__, len));
++		bcmerror = DBUS_ERR_NVRAM;
++		goto err;
++	}
++	if (nv_image) {
++		dhd_os_close_image(nv_image);
++		nv_image = NULL;
++	}
++
++	/* For Get first block of fw to calculate total_len */
++	file_exists = ((pfw_path != NULL) && (pfw_path[0] != '\0'));
++	if (file_exists) {
++		fw_image = dhd_os_open_image(pfw_path);
++		if (fw_image == NULL) {
++			printf("%s: Open fw file failed %s\n", __FUNCTION__, pfw_path);
++			goto err;
++		}
++	}
++	memptr = fw_memblock = MALLOC(dhd_bus->pub.osh, memblock_size);
++	if (fw_memblock == NULL) {
++		DBUSERR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__,
++			memblock_size));
++		goto err;
++	}
++	len = dhd_os_get_image_block((char*)memptr, memblock_size, fw_image);
++	if ((actual_fwlen = check_file(dhd_bus->pub.osh, memptr)) <= 0) {
++		DBUSERR(("%s: bad firmware format!\n", __FUNCTION__));
++		goto err;
++	}
++
++	total_len = actual_fwlen + dhd_bus->nvram_len + nvram_words_pad;
++	dhd_bus->image = MALLOC(dhd_bus->pub.osh, total_len);
++	dhd_bus->image_len = total_len;
++	if (dhd_bus->image == NULL) {
++		DBUSERR(("%s: malloc failed!\n", __FUNCTION__));
++		goto err;
++	}
++
++	/* Step1: Copy trx header + firmwre */
++	memptr = fw_memblock;
++	do {
++		if (len < 0) {
++			DBUSERR(("%s: dhd_os_get_image_block failed (%d)\n", __FUNCTION__, len));
++			bcmerror = BCME_ERROR;
++			goto err;
++		}
++		bcopy(memptr, dhd_bus->image+offset, len);
++		offset += len;
++	} while ((len = dhd_os_get_image_block((char*)memptr, memblock_size, fw_image)));
++	/* Step2: Copy NVRAM + pad */
++	hdr = (struct trx_header *)dhd_bus->image;
++	img_offset = SIZEOF_TRX(hdr) + hdr->offsets[TRX_OFFSETS_DLFWLEN_IDX];
++	bcopy(nv_memblock, (uint8 *)(dhd_bus->image + img_offset),
++		dhd_bus->nvram_len);
++	img_offset += dhd_bus->nvram_len;
++	if (nvram_words_pad) {
++		bzero(&dhd_bus->image[img_offset], nvram_words_pad);
++		img_offset += nvram_words_pad;
++	}
++#ifdef BCMTRXV2
++	/* Step3: Copy DSG/CFG for V2 */
++	if (ISTRX_V2(hdr) &&
++		(hdr->offsets[TRX_OFFSETS_DSG_LEN_IDX] ||
++		hdr->offsets[TRX_OFFSETS_CFG_LEN_IDX])) {
++		DBUSERR(("%s: fix me\n", __FUNCTION__));
++	}
++#endif /* BCMTRXV2 */
++	/* Step4: update TRX header for nvram size */
++	hdr = (struct trx_header *)dhd_bus->image;
++	hdr->len = htol32(total_len);
++	/* Pass the actual fw len */
++	hdr->offsets[TRX_OFFSETS_NVM_LEN_IDX] =
++		htol32(dhd_bus->nvram_len + nvram_words_pad);
++	/* Calculate CRC over header */
++	hdr->crc32 = hndcrc32((uint8 *)&hdr->flag_version,
++		SIZEOF_TRX(hdr) - OFFSETOF(struct trx_header, flag_version),
++		CRC32_INIT_VALUE);
++
++	/* Calculate CRC over data */
++	for (i = SIZEOF_TRX(hdr); i < total_len; ++i)
++			hdr->crc32 = hndcrc32((uint8 *)&dhd_bus->image[i], 1, hdr->crc32);
++	hdr->crc32 = htol32(hdr->crc32);
++
++	bcmerror = DBUS_OK;
++
++err:
++	if (fw_memblock)
++		MFREE(dhd_bus->pub.osh, fw_memblock, MAX_NVRAMBUF_SIZE);
++	if (fw_image)
++		dhd_os_close_image(fw_image);
++	if (nv_memblock)
++		MFREE(dhd_bus->pub.osh, nv_memblock, MAX_NVRAMBUF_SIZE);
++	if (nv_image)
++		dhd_os_close_image(nv_image);
++
++	return bcmerror;
++}
++
++/**
++ * during driver initialization ('attach') or after PnP 'resume', firmware needs to be loaded into
++ * the dongle
++ */
++static int
++dbus_do_download(dhd_bus_t *dhd_bus, char *pfw_path, char *pnv_path)
++{
++	int err = DBUS_OK;
++
++	err = dbus_get_fw_nvram(dhd_bus, pfw_path, pnv_path);
++	if (err) {
++		DBUSERR(("dbus_do_download: fail to get nvram %d\n", err));
++		return err;
++	}
++
++	if (dhd_bus->drvintf->dlstart && dhd_bus->drvintf->dlrun) {
++		err = dhd_bus->drvintf->dlstart(dhd_bus->bus_info,
++			dhd_bus->image, dhd_bus->image_len);
++		if (err == DBUS_OK) {
++			err = dhd_bus->drvintf->dlrun(dhd_bus->bus_info);
++		}
++	} else
++		err = DBUS_ERR;
++
++	if (dhd_bus->image) {
++		MFREE(dhd_bus->pub.osh, dhd_bus->image, dhd_bus->image_len);
++		dhd_bus->image = NULL;
++		dhd_bus->image_len = 0;
++	}
++
++	return err;
++} /* dbus_do_download */
++#else
++
++/**
++ * It is easy for the user to pass one jumbo nvram file to the driver than a set of smaller files.
++ * The 'jumbo nvram' file format is essentially a set of nvram files. Before commencing firmware
++ * download, the dongle needs to be probed so that the correct nvram contents within the jumbo nvram
++ * file is selected.
++ */
++static int
++dbus_jumbo_nvram(dhd_bus_t *dhd_bus)
++{
++	int8 *nvram = NULL;
++	int nvram_len = 0;
++	int ret = DBUS_OK;
++	uint16 boardrev = 0xFFFF;
++	uint16 boardtype = 0xFFFF;
++
++	/* read the otp for boardrev & boardtype
++	* if boardtype/rev are present in otp
++	* select nvram data for that boardtype/rev
++	*/
++	dbus_otp(dhd_bus, &boardtype, &boardrev);
++
++	ret = dbus_select_nvram(dhd_bus, dhd_bus->extdl.vars, dhd_bus->extdl.varslen,
++		boardtype, boardrev, &nvram, &nvram_len);
++
++	if (ret == DBUS_JUMBO_BAD_FORMAT)
++			return DBUS_ERR_NVRAM;
++	else if (ret == DBUS_JUMBO_NOMATCH &&
++		(boardtype != 0xFFFF || boardrev  != 0xFFFF)) {
++			DBUSERR(("No matching NVRAM for boardtype 0x%02x boardrev 0x%02x\n",
++				boardtype, boardrev));
++			return DBUS_ERR_NVRAM;
++	}
++	dhd_bus->nvram = nvram;
++	dhd_bus->nvram_len =  nvram_len;
++
++	return DBUS_OK;
++}
++
++/** before commencing fw download, the correct NVRAM image to download has to be picked */
++static int
++dbus_get_nvram(dhd_bus_t *dhd_bus)
++{
++	int len, i;
++	struct trx_header *hdr;
++	int	actual_fwlen;
++	uint32 img_offset = 0;
++
++	dhd_bus->nvram_len = 0;
++	if (dhd_bus->extdl.varslen) {
++		if (DBUS_OK != dbus_jumbo_nvram(dhd_bus))
++			return DBUS_ERR_NVRAM;
++		DBUSERR(("NVRAM %d bytes downloaded\n", dhd_bus->nvram_len));
++	}
++#if defined(BCM_REQUEST_FW)
++	else if (nonfwnvram) {
++		dhd_bus->nvram = nonfwnvram;
++		dhd_bus->nvram_len = nonfwnvramlen;
++		DBUSERR(("NVRAM %d bytes downloaded\n", dhd_bus->nvram_len));
++	}
++#endif
++	if (dhd_bus->nvram) {
++		uint8 nvram_words_pad = 0;
++		/* Validate the format/length etc of the file */
++		if ((actual_fwlen = check_file(dhd_bus->pub.osh, dhd_bus->fw)) <= 0) {
++			DBUSERR(("%s: bad firmware format!\n", __FUNCTION__));
++			return DBUS_ERR_NVRAM;
++		}
++
++		if (!dhd_bus->nvram_nontxt) {
++			/* host supplied nvram could be in .txt format
++			* with all the comments etc...
++			*/
++			dhd_bus->nvram_len = process_nvram_vars(dhd_bus->nvram,
++				dhd_bus->nvram_len);
++		}
++		if (dhd_bus->nvram_len % 4)
++			nvram_words_pad = 4 - dhd_bus->nvram_len % 4;
++
++		len = actual_fwlen + dhd_bus->nvram_len + nvram_words_pad;
++		dhd_bus->image = MALLOC(dhd_bus->pub.osh, len);
++		dhd_bus->image_len = len;
++		if (dhd_bus->image == NULL) {
++			DBUSERR(("%s: malloc failed!\n", __FUNCTION__));
++			return DBUS_ERR_NVRAM;
++		}
++		hdr = (struct trx_header *)dhd_bus->fw;
++		/* Step1: Copy trx header + firmwre */
++		img_offset = SIZEOF_TRX(hdr) + hdr->offsets[TRX_OFFSETS_DLFWLEN_IDX];
++		bcopy(dhd_bus->fw, dhd_bus->image, img_offset);
++		/* Step2: Copy NVRAM + pad */
++		bcopy(dhd_bus->nvram, (uint8 *)(dhd_bus->image + img_offset),
++			dhd_bus->nvram_len);
++		img_offset += dhd_bus->nvram_len;
++		if (nvram_words_pad) {
++			bzero(&dhd_bus->image[img_offset],
++				nvram_words_pad);
++			img_offset += nvram_words_pad;
++		}
++#ifdef BCMTRXV2
++		/* Step3: Copy DSG/CFG for V2 */
++		if (ISTRX_V2(hdr) &&
++			(hdr->offsets[TRX_OFFSETS_DSG_LEN_IDX] ||
++			hdr->offsets[TRX_OFFSETS_CFG_LEN_IDX])) {
++
++			bcopy(dhd_bus->fw + SIZEOF_TRX(hdr) +
++				hdr->offsets[TRX_OFFSETS_DLFWLEN_IDX] +
++				hdr->offsets[TRX_OFFSETS_NVM_LEN_IDX],
++				dhd_bus->image + img_offset,
++				hdr->offsets[TRX_OFFSETS_DSG_LEN_IDX] +
++				hdr->offsets[TRX_OFFSETS_CFG_LEN_IDX]);
++
++			img_offset += hdr->offsets[TRX_OFFSETS_DSG_LEN_IDX] +
++				hdr->offsets[TRX_OFFSETS_CFG_LEN_IDX];
++		}
++#endif /* BCMTRXV2 */
++		/* Step4: update TRX header for nvram size */
++		hdr = (struct trx_header *)dhd_bus->image;
++		hdr->len = htol32(len);
++		/* Pass the actual fw len */
++		hdr->offsets[TRX_OFFSETS_NVM_LEN_IDX] =
++			htol32(dhd_bus->nvram_len + nvram_words_pad);
++		/* Calculate CRC over header */
++		hdr->crc32 = hndcrc32((uint8 *)&hdr->flag_version,
++			SIZEOF_TRX(hdr) - OFFSETOF(struct trx_header, flag_version),
++			CRC32_INIT_VALUE);
++
++		/* Calculate CRC over data */
++		for (i = SIZEOF_TRX(hdr); i < len; ++i)
++				hdr->crc32 = hndcrc32((uint8 *)&dhd_bus->image[i], 1, hdr->crc32);
++		hdr->crc32 = htol32(hdr->crc32);
++	} else {
++		dhd_bus->image = dhd_bus->fw;
++		dhd_bus->image_len = (uint32)dhd_bus->fwlen;
++	}
++
++	return DBUS_OK;
++} /* dbus_get_nvram */
++
++/**
++ * during driver initialization ('attach') or after PnP 'resume', firmware needs to be loaded into
++ * the dongle
++ */
++static int
++dbus_do_download(dhd_bus_t *dhd_bus)
++{
++	int err = DBUS_OK;
++#ifndef BCM_REQUEST_FW
++	int decomp_override = 0;
++#endif
++#ifdef BCM_REQUEST_FW
++	uint16 boardrev = 0xFFFF, boardtype = 0xFFFF;
++	int8 *temp_nvram;
++	int temp_len;
++#endif
++
++#if defined(BCM_REQUEST_FW)
++	dhd_bus->firmware = dbus_get_fw_nvfile(dhd_bus->pub.attrib.devid,
++		dhd_bus->pub.attrib.chiprev, &dhd_bus->fw, &dhd_bus->fwlen,
++		DBUS_FIRMWARE, 0, 0);
++	if (!dhd_bus->firmware)
++		return DBUS_ERR;
++#endif 
++
++	dhd_bus->image = dhd_bus->fw;
++	dhd_bus->image_len = (uint32)dhd_bus->fwlen;
++
++#ifndef BCM_REQUEST_FW
++	if (UNZIP_ENAB(dhd_bus) && !decomp_override) {
++		err = dbus_zlib_decomp(dhd_bus);
++		if (err) {
++			DBUSERR(("dbus_attach: fw decompress fail %d\n", err));
++			return err;
++		}
++	}
++#endif
++
++#if defined(BCM_REQUEST_FW)
++	/* check if firmware is appended with nvram file */
++	err = dbus_otp(dhd_bus, &boardtype, &boardrev);
++	/* check if nvram is provided as separte file */
++	nonfwnvram = NULL;
++	nonfwnvramlen = 0;
++	dhd_bus->nvfile = dbus_get_fw_nvfile(dhd_bus->pub.attrib.devid,
++		dhd_bus->pub.attrib.chiprev, (void *)&temp_nvram, &temp_len,
++		DBUS_NVFILE, boardtype, boardrev);
++	if (dhd_bus->nvfile) {
++		int8 *tmp = MALLOC(dhd_bus->pub.osh, temp_len);
++		if (tmp) {
++			bcopy(temp_nvram, tmp, temp_len);
++			nonfwnvram = tmp;
++			nonfwnvramlen = temp_len;
++		} else {
++			err = DBUS_ERR;
++			goto fail;
++		}
++	}
++#endif /* defined(BCM_REQUEST_FW) */
++
++	err = dbus_get_nvram(dhd_bus);
++	if (err) {
++		DBUSERR(("dbus_do_download: fail to get nvram %d\n", err));
++		return err;
++	}
++
++
++	if (dhd_bus->drvintf->dlstart && dhd_bus->drvintf->dlrun) {
++		err = dhd_bus->drvintf->dlstart(dhd_bus->bus_info,
++			dhd_bus->image, dhd_bus->image_len);
++
++		if (err == DBUS_OK)
++			err = dhd_bus->drvintf->dlrun(dhd_bus->bus_info);
++	} else
++		err = DBUS_ERR;
++
++	if (dhd_bus->nvram) {
++		MFREE(dhd_bus->pub.osh, dhd_bus->image, dhd_bus->image_len);
++		dhd_bus->image = dhd_bus->fw;
++		dhd_bus->image_len = (uint32)dhd_bus->fwlen;
++	}
++
++#ifndef BCM_REQUEST_FW
++	if (UNZIP_ENAB(dhd_bus) && (!decomp_override) && dhd_bus->orig_fw) {
++		MFREE(dhd_bus->pub.osh, dhd_bus->fw, dhd_bus->decomp_memsize);
++		dhd_bus->image = dhd_bus->fw = dhd_bus->orig_fw;
++		dhd_bus->image_len = dhd_bus->fwlen = dhd_bus->origfw_len;
++	}
++#endif
++
++#if defined(BCM_REQUEST_FW)
++fail:
++	if (dhd_bus->firmware) {
++		dbus_release_fw_nvfile(dhd_bus->firmware);
++		dhd_bus->firmware = NULL;
++	}
++	if (dhd_bus->nvfile) {
++		dbus_release_fw_nvfile(dhd_bus->nvfile);
++		dhd_bus->nvfile = NULL;
++	}
++	if (nonfwnvram) {
++		MFREE(dhd_bus->pub.osh, nonfwnvram, nonfwnvramlen);
++		nonfwnvram = NULL;
++		nonfwnvramlen = 0;
++	}
++#endif
++	return err;
++} /* dbus_do_download */
++#endif /* EXTERNAL_FW_PATH */
++#endif
++
++/** required for DBUS deregistration */
++static void
++dbus_disconnect(void *handle)
++{
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (disconnect_cb)
++		disconnect_cb(disc_arg);
++}
++
++/**
++ * This function is called when the sent irb times out without a tx response status.
++ * DBUS adds reliability by resending timed out IRBs DBUS_TX_RETRY_LIMIT times.
++ */
++static void
++dbus_if_send_irb_timeout(void *handle, dbus_irb_tx_t *txirb)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) handle;
++
++	if ((dhd_bus == NULL) || (dhd_bus->drvintf == NULL) || (txirb == NULL)) {
++		return;
++	}
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	return;
++
++} /* dbus_if_send_irb_timeout */
++
++/**
++ * When lower DBUS level signals that a send IRB completed, either successful or not, the higher
++ * level (e.g. dhd_linux.c) has to be notified, and transmit flow control has to be evaluated.
++ */
++static void BCMFASTPATH
++dbus_if_send_irb_complete(void *handle, dbus_irb_tx_t *txirb, int status)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) handle;
++	int txirb_pending;
++	struct exec_parms args;
++	void *pktinfo;
++
++	if ((dhd_bus == NULL) || (txirb == NULL)) {
++		return;
++	}
++
++	DBUSTRACE(("%s: status = %d\n", __FUNCTION__, status));
++
++	dbus_tx_timer_stop(dhd_bus);
++
++	/* re-queue BEFORE calling send_complete which will assume that this irb
++	   is now available.
++	 */
++	pktinfo = txirb->info;
++	bzero(txirb, sizeof(dbus_irb_tx_t));
++	args.qenq.q = dhd_bus->tx_q;
++	args.qenq.b = (dbus_irb_t *) txirb;
++	EXEC_TXLOCK(dhd_bus, q_enq_exec, &args);
++
++	if (dhd_bus->pub.busstate != DBUS_STATE_DOWN) {
++		if ((status == DBUS_OK) || (status == DBUS_ERR_NODEVICE)) {
++			if (dhd_bus->cbs && dhd_bus->cbs->send_complete)
++				dhd_bus->cbs->send_complete(dhd_bus->cbarg, pktinfo,
++					status);
++
++			if (status == DBUS_OK) {
++				txirb_pending = dhd_bus->pub.ntxq - dhd_bus->tx_q->cnt;
++				if (txirb_pending)
++					dbus_tx_timer_start(dhd_bus, DBUS_TX_TIMEOUT_INTERVAL);
++				if ((txirb_pending < dhd_bus->tx_low_watermark) &&
++					dhd_bus->txoff && !dhd_bus->txoverride) {
++					dbus_flowctrl_tx(dhd_bus, OFF);
++				}
++			}
++		} else {
++			DBUSERR(("%s: %d WARNING freeing orphan pkt %p\n", __FUNCTION__, __LINE__,
++				pktinfo));
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_TXNOCOPY) || defined(BCM_RPC_TOC)
++			if (pktinfo)
++				if (dhd_bus->cbs && dhd_bus->cbs->send_complete)
++					dhd_bus->cbs->send_complete(dhd_bus->cbarg, pktinfo,
++						status);
++#else
++			dbus_if_pktfree(dhd_bus, (void*)pktinfo, TRUE);
++#endif /* defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_TXNOCOPY) || defined(BCM_RPC_TOC) */
++		}
++	} else {
++		DBUSERR(("%s: %d WARNING freeing orphan pkt %p\n", __FUNCTION__, __LINE__,
++			pktinfo));
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_TXNOCOPY) || defined(BCM_RPC_TOC)
++		if (pktinfo)
++			if (dhd_bus->cbs && dhd_bus->cbs->send_complete)
++				dhd_bus->cbs->send_complete(dhd_bus->cbarg, pktinfo,
++					status);
++#else
++		dbus_if_pktfree(dhd_bus, (void*)pktinfo, TRUE);
++#endif /* defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_TXNOCOPY) defined(BCM_RPC_TOC) */
++	}
++} /* dbus_if_send_irb_complete */
++
++/**
++ * When lower DBUS level signals that a receive IRB completed, either successful or not, the higher
++ * level (e.g. dhd_linux.c) has to be notified, and fresh free receive IRBs may have to be given
++ * to lower levels.
++ */
++static void BCMFASTPATH
++dbus_if_recv_irb_complete(void *handle, dbus_irb_rx_t *rxirb, int status)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) handle;
++	int rxirb_pending;
++	struct exec_parms args;
++
++	if ((dhd_bus == NULL) || (rxirb == NULL)) {
++		return;
++	}
++	DBUSTRACE(("%s\n", __FUNCTION__));
++	if (dhd_bus->pub.busstate != DBUS_STATE_DOWN &&
++		dhd_bus->pub.busstate != DBUS_STATE_SLEEP) {
++		if (status == DBUS_OK) {
++			if ((rxirb->buf != NULL) && (rxirb->actual_len > 0)) {
++#ifdef DBUS_USB_LOOPBACK
++				if (is_loopback_pkt(rxirb->buf)) {
++					matches_loopback_pkt(rxirb->buf);
++				} else
++#endif
++				if (dhd_bus->cbs && dhd_bus->cbs->recv_buf) {
++					dhd_bus->cbs->recv_buf(dhd_bus->cbarg, rxirb->buf,
++					rxirb->actual_len);
++				}
++			} else if (rxirb->pkt != NULL) {
++				if (dhd_bus->cbs && dhd_bus->cbs->recv_pkt)
++					dhd_bus->cbs->recv_pkt(dhd_bus->cbarg, rxirb->pkt);
++			} else {
++				ASSERT(0); /* Should not happen */
++			}
++
++			rxirb_pending = dhd_bus->pub.nrxq - dhd_bus->rx_q->cnt - 1;
++			if ((rxirb_pending <= dhd_bus->rx_low_watermark) &&
++				!dhd_bus->rxoff) {
++				DBUSTRACE(("Low watermark so submit more %d <= %d \n",
++					dhd_bus->rx_low_watermark, rxirb_pending));
++				dbus_rxirbs_fill(dhd_bus);
++			} else if (dhd_bus->rxoff)
++				DBUSTRACE(("rx flow controlled. not filling more. cut_rxq=%d\n",
++					dhd_bus->rx_q->cnt));
++		} else if (status == DBUS_ERR_NODEVICE) {
++			DBUSERR(("%s: %d status = %d, buf %p\n", __FUNCTION__, __LINE__, status,
++				rxirb->buf));
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++			if (rxirb->buf) {
++				PKTFRMNATIVE(dhd_bus->pub.osh, rxirb->buf);
++				PKTFREE(dhd_bus->pub.osh, rxirb->buf, FALSE);
++			}
++#endif /* BCM_RPC_NOCOPY || BCM_RPC_TXNOCOPY || BCM_RPC_TOC */
++		} else {
++			if (status != DBUS_ERR_RXZLP)
++				DBUSERR(("%s: %d status = %d, buf %p\n", __FUNCTION__, __LINE__,
++					status, rxirb->buf));
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++			if (rxirb->buf) {
++				PKTFRMNATIVE(dhd_bus->pub.osh, rxirb->buf);
++				PKTFREE(dhd_bus->pub.osh, rxirb->buf, FALSE);
++			}
++#endif /* BCM_RPC_NOCOPY || BCM_RPC_TXNOCOPY || BCM_RPC_TOC */
++		}
++	} else {
++		DBUSTRACE(("%s: DBUS down, ignoring recv callback. buf %p\n", __FUNCTION__,
++			rxirb->buf));
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++		if (rxirb->buf) {
++			PKTFRMNATIVE(dhd_bus->pub.osh, rxirb->buf);
++			PKTFREE(dhd_bus->pub.osh, rxirb->buf, FALSE);
++		}
++#endif /* BCM_RPC_NOCOPY || BCM_RPC_TXNOCOPY || BCM_RPC_TOC */
++	}
++	if (dhd_bus->rx_q != NULL) {
++		bzero(rxirb, sizeof(dbus_irb_rx_t));
++		args.qenq.q = dhd_bus->rx_q;
++		args.qenq.b = (dbus_irb_t *) rxirb;
++		EXEC_RXLOCK(dhd_bus, q_enq_exec, &args);
++	} else
++		MFREE(dhd_bus->pub.osh, rxirb, sizeof(dbus_irb_tx_t));
++} /* dbus_if_recv_irb_complete */
++
++/**
++ *  Accumulate errors signaled by lower DBUS levels and signal them to higher (e.g. dhd_linux.c)
++ *  level.
++ */
++static void
++dbus_if_errhandler(void *handle, int err)
++{
++	dhd_bus_t *dhd_bus = handle;
++	uint32 mask = 0;
++
++	if (dhd_bus == NULL)
++		return;
++
++	switch (err) {
++		case DBUS_ERR_TXFAIL:
++			dhd_bus->pub.stats.tx_errors++;
++			mask |= ERR_CBMASK_TXFAIL;
++			break;
++		case DBUS_ERR_TXDROP:
++			dhd_bus->pub.stats.tx_dropped++;
++			mask |= ERR_CBMASK_TXFAIL;
++			break;
++		case DBUS_ERR_RXFAIL:
++			dhd_bus->pub.stats.rx_errors++;
++			mask |= ERR_CBMASK_RXFAIL;
++			break;
++		case DBUS_ERR_RXDROP:
++			dhd_bus->pub.stats.rx_dropped++;
++			mask |= ERR_CBMASK_RXFAIL;
++			break;
++		default:
++			break;
++	}
++
++	if (dhd_bus->cbs && dhd_bus->cbs->errhandler && (dhd_bus->errmask & mask))
++		dhd_bus->cbs->errhandler(dhd_bus->cbarg, err);
++}
++
++/**
++ * When lower DBUS level signals control IRB completed, higher level (e.g. dhd_linux.c) has to be
++ * notified.
++ */
++static void
++dbus_if_ctl_complete(void *handle, int type, int status)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) handle;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dhd_bus == NULL) {
++		DBUSERR(("%s: dhd_bus is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (dhd_bus->pub.busstate != DBUS_STATE_DOWN) {
++		if (dhd_bus->cbs && dhd_bus->cbs->ctl_complete)
++			dhd_bus->cbs->ctl_complete(dhd_bus->cbarg, type, status);
++	}
++}
++
++/**
++ * Rx related functionality (flow control, posting of free IRBs to rx queue) is dependent upon the
++ * bus state. When lower DBUS level signals a change in the interface state, take appropriate action
++ * and forward the signaling to the higher (e.g. dhd_linux.c) level.
++ */
++static void
++dbus_if_state_change(void *handle, int state)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) handle;
++	int old_state;
++
++	if (dhd_bus == NULL)
++		return;
++
++	if (dhd_bus->pub.busstate == state)
++		return;
++	old_state = dhd_bus->pub.busstate;
++	if (state == DBUS_STATE_DISCONNECT) {
++		DBUSERR(("DBUS disconnected\n"));
++	}
++
++	/* Ignore USB SUSPEND while not up yet */
++	if (state == DBUS_STATE_SLEEP && old_state != DBUS_STATE_UP)
++		return;
++
++	DBUSTRACE(("dbus state change from %d to to %d\n", old_state, state));
++
++	/* Don't update state if it's PnP firmware re-download */
++	if (state != DBUS_STATE_PNP_FWDL)
++		dhd_bus->pub.busstate = state;
++	else
++		dbus_flowctrl_rx(handle, FALSE);
++	if (state == DBUS_STATE_SLEEP)
++		dbus_flowctrl_rx(handle, TRUE);
++	if (state == DBUS_STATE_UP) {
++		dbus_rxirbs_fill(dhd_bus);
++		dbus_flowctrl_rx(handle, FALSE);
++	}
++
++	if (dhd_bus->cbs && dhd_bus->cbs->state_change)
++		dhd_bus->cbs->state_change(dhd_bus->cbarg, state);
++}
++
++/** Forward request for packet from lower DBUS layer to higher layer (e.g. dhd_linux.c) */
++static void *
++dbus_if_pktget(void *handle, uint len, bool send)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) handle;
++	void *p = NULL;
++
++	if (dhd_bus == NULL)
++		return NULL;
++
++	if (dhd_bus->cbs && dhd_bus->cbs->pktget)
++		p = dhd_bus->cbs->pktget(dhd_bus->cbarg, len, send);
++	else
++		ASSERT(0);
++
++	return p;
++}
++
++/** Forward request to free packet from lower DBUS layer to higher layer (e.g. dhd_linux.c) */
++static void
++dbus_if_pktfree(void *handle, void *p, bool send)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) handle;
++
++	if (dhd_bus == NULL)
++		return;
++
++	if (dhd_bus->cbs && dhd_bus->cbs->pktfree)
++		dhd_bus->cbs->pktfree(dhd_bus->cbarg, p, send);
++	else
++		ASSERT(0);
++}
++
++/** Lower DBUS level requests either a send or receive IRB */
++static struct dbus_irb*
++dbus_if_getirb(void *cbarg, bool send)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) cbarg;
++	struct exec_parms args;
++	struct dbus_irb *irb;
++
++	if ((dhd_bus == NULL) || (dhd_bus->pub.busstate != DBUS_STATE_UP))
++		return NULL;
++
++	if (send == TRUE) {
++		args.qdeq.q = dhd_bus->tx_q;
++		irb = EXEC_TXLOCK(dhd_bus, q_deq_exec, &args);
++	} else {
++		args.qdeq.q = dhd_bus->rx_q;
++		irb = EXEC_RXLOCK(dhd_bus, q_deq_exec, &args);
++	}
++
++	return irb;
++}
++
++/**
++ * Called as part of DBUS bus registration. Calls back into higher level (e.g. dhd_linux.c) probe
++ * function.
++ */
++static void *
++dbus_probe(void *arg, const char *desc, uint32 bustype, uint16 bus_no,
++	uint16 slot, uint32 hdrlen)
++{
++	DBUSTRACE(("%s\n", __FUNCTION__));
++	if (probe_cb) {
++		disc_arg = probe_cb(probe_arg, desc, bustype, bus_no, slot, hdrlen);
++		return disc_arg;
++	}
++
++	return (void *)DBUS_ERR;
++}
++
++/**
++ * As part of initialization, higher level (e.g. dhd_linux.c) requests DBUS to prepare for
++ * action.
++ */
++int
++dhd_bus_register(void)
++{
++	int err;
++
++	DBUSTRACE(("%s: Enter\n", __FUNCTION__));
++
++	probe_cb = dhd_dbus_probe_cb;
++	disconnect_cb = dhd_dbus_disconnect_cb;
++	probe_arg = NULL;
++
++	err = dbus_bus_register(0xa5c, 0x48f, dbus_probe, /* call lower DBUS level register function */
++		dbus_disconnect, NULL, &g_busintf, NULL, NULL);
++
++	/* Device not detected */
++	if (err == DBUS_ERR_NODEVICE)
++		err = DBUS_OK;
++
++	return err;
++}
++
++dhd_pub_t *g_pub = NULL;
++void
++dhd_bus_unregister(void)
++{
++	int ret;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	DHD_MUTEX_LOCK();
++	if (g_pub) {
++		g_pub->dhd_remove = TRUE;
++		if (!g_pub->bus) {
++			dhd_dbus_disconnect_cb(g_pub->bus);
++		}
++	}
++	probe_cb = NULL;
++	DHD_MUTEX_UNLOCK();
++	ret = dbus_bus_deregister();
++	disconnect_cb = NULL;
++	probe_arg = NULL;
++}
++
++/** As part of initialization, data structures have to be allocated and initialized */
++dhd_bus_t *
++dbus_attach(osl_t *osh, int rxsize, int nrxq, int ntxq, dhd_pub_t *pub,
++	dbus_callbacks_t *cbs, dbus_extdl_t *extdl, struct shared_info *sh)
++{
++	dhd_bus_t *dhd_bus;
++	int err;
++
++	if ((g_busintf == NULL) || (g_busintf->attach == NULL) || (cbs == NULL))
++		return NULL;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if ((nrxq <= 0) || (ntxq <= 0))
++		return NULL;
++
++	dhd_bus = MALLOC(osh, sizeof(dhd_bus_t));
++	if (dhd_bus == NULL) {
++		DBUSERR(("%s: malloc failed %zu\n", __FUNCTION__, sizeof(dhd_bus_t)));
++		return NULL;
++	}
++
++	bzero(dhd_bus, sizeof(dhd_bus_t));
++
++	/* BUS-specific driver interface (at a lower DBUS level) */
++	dhd_bus->drvintf = g_busintf;
++	dhd_bus->cbarg = pub;
++	dhd_bus->cbs = cbs;
++
++	dhd_bus->pub.sh = sh;
++	dhd_bus->pub.osh = osh;
++	dhd_bus->pub.rxsize = rxsize;
++
++	dhd_bus->pub.nrxq = nrxq;
++	dhd_bus->rx_low_watermark = nrxq / 2;	/* keep enough posted rx urbs */
++	dhd_bus->pub.ntxq = ntxq;
++	dhd_bus->tx_low_watermark = ntxq / 4;	/* flow control when too many tx urbs posted */
++
++	dhd_bus->tx_q = MALLOC(osh, sizeof(dbus_irbq_t));
++	if (dhd_bus->tx_q == NULL)
++		goto error;
++	else {
++		bzero(dhd_bus->tx_q, sizeof(dbus_irbq_t));
++		err = dbus_irbq_init(dhd_bus, dhd_bus->tx_q, ntxq, sizeof(dbus_irb_tx_t));
++		if (err != DBUS_OK)
++			goto error;
++	}
++
++	dhd_bus->rx_q = MALLOC(osh, sizeof(dbus_irbq_t));
++	if (dhd_bus->rx_q == NULL)
++		goto error;
++	else {
++		bzero(dhd_bus->rx_q, sizeof(dbus_irbq_t));
++		err = dbus_irbq_init(dhd_bus, dhd_bus->rx_q, nrxq, sizeof(dbus_irb_rx_t));
++		if (err != DBUS_OK)
++			goto error;
++	}
++
++
++	dhd_bus->bus_info = (void *)g_busintf->attach(&dhd_bus->pub,
++		dhd_bus, &dbus_intf_cbs);
++	if (dhd_bus->bus_info == NULL)
++		goto error;
++
++	dbus_tx_timer_init(dhd_bus);
++
++#if defined(BCM_REQUEST_FW)
++	/* Need to copy external image for re-download */
++	if (extdl && extdl->fw && (extdl->fwlen > 0)) {
++		dhd_bus->extdl.fw = MALLOC(osh, extdl->fwlen);
++		if (dhd_bus->extdl.fw) {
++			bcopy(extdl->fw, dhd_bus->extdl.fw, extdl->fwlen);
++			dhd_bus->extdl.fwlen = extdl->fwlen;
++		}
++	}
++
++	if (extdl && extdl->vars && (extdl->varslen > 0)) {
++		dhd_bus->extdl.vars = MALLOC(osh, extdl->varslen);
++		if (dhd_bus->extdl.vars) {
++			bcopy(extdl->vars, dhd_bus->extdl.vars, extdl->varslen);
++			dhd_bus->extdl.varslen = extdl->varslen;
++		}
++	}
++#endif 
++
++	return (dhd_bus_t *)dhd_bus;
++
++error:
++	DBUSERR(("%s: Failed\n", __FUNCTION__));
++	dbus_detach(dhd_bus);
++	return NULL;
++} /* dbus_attach */
++
++void
++dbus_detach(dhd_bus_t *pub)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++	osl_t *osh;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dhd_bus == NULL)
++		return;
++
++	dbus_tx_timer_stop(dhd_bus);
++
++	osh = pub->pub.osh;
++
++	if (dhd_bus->drvintf && dhd_bus->drvintf->detach)
++		 dhd_bus->drvintf->detach((dbus_pub_t *)dhd_bus, dhd_bus->bus_info);
++
++	if (dhd_bus->tx_q) {
++		dbus_irbq_deinit(dhd_bus, dhd_bus->tx_q, sizeof(dbus_irb_tx_t));
++		MFREE(osh, dhd_bus->tx_q, sizeof(dbus_irbq_t));
++		dhd_bus->tx_q = NULL;
++	}
++
++	if (dhd_bus->rx_q) {
++		dbus_irbq_deinit(dhd_bus, dhd_bus->rx_q, sizeof(dbus_irb_rx_t));
++		MFREE(osh, dhd_bus->rx_q, sizeof(dbus_irbq_t));
++		dhd_bus->rx_q = NULL;
++	}
++
++
++	if (dhd_bus->extdl.fw && (dhd_bus->extdl.fwlen > 0)) {
++		MFREE(osh, dhd_bus->extdl.fw, dhd_bus->extdl.fwlen);
++		dhd_bus->extdl.fw = NULL;
++		dhd_bus->extdl.fwlen = 0;
++	}
++
++	if (dhd_bus->extdl.vars && (dhd_bus->extdl.varslen > 0)) {
++		MFREE(osh, dhd_bus->extdl.vars, dhd_bus->extdl.varslen);
++		dhd_bus->extdl.vars = NULL;
++		dhd_bus->extdl.varslen = 0;
++	}
++
++	MFREE(osh, dhd_bus, sizeof(dhd_bus_t));
++} /* dbus_detach */
++
++int dbus_dlneeded(dhd_bus_t *pub)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++	int dlneeded = DBUS_ERR;
++
++	if (!dhd_bus) {
++		DBUSERR(("%s: dhd_bus is NULL\n", __FUNCTION__));
++		return DBUS_ERR;
++	}
++
++	DBUSTRACE(("%s: state %d\n", __FUNCTION__, dhd_bus->pub.busstate));
++
++	if (dhd_bus->drvintf->dlneeded) {
++		dlneeded = dhd_bus->drvintf->dlneeded(dhd_bus->bus_info);
++	}
++	printf("%s: dlneeded=%d\n", __FUNCTION__, dlneeded);
++
++	/* dlneeded > 0: need to download
++	  * dlneeded = 0: downloaded
++	  * dlneeded < 0: bus error*/
++	return dlneeded;
++}
++
++#if defined(BCM_REQUEST_FW)
++int dbus_download_firmware(dhd_bus_t *pub, char *pfw_path, char *pnv_path)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++	int err = DBUS_OK;
++
++	if (!dhd_bus) {
++		DBUSERR(("%s: dhd_bus is NULL\n", __FUNCTION__));
++		return DBUS_ERR;
++	}
++
++	DBUSTRACE(("%s: state %d\n", __FUNCTION__, dhd_bus->pub.busstate));
++
++	dhd_bus->pub.busstate = DBUS_STATE_DL_PENDING;
++#ifdef EXTERNAL_FW_PATH
++	err = dbus_do_download(dhd_bus, pfw_path, pnv_path);
++#else
++	err = dbus_do_download(dhd_bus);
++#endif /* EXTERNAL_FW_PATH */
++	if (err == DBUS_OK) {
++		dhd_bus->pub.busstate = DBUS_STATE_DL_DONE;
++	} else {
++		DBUSERR(("%s: download failed (%d)\n", __FUNCTION__, err));
++	}
++
++	return err;
++}
++#endif 
++
++/**
++ * higher layer requests us to 'up' the interface to the dongle. Prerequisite is that firmware (not
++ * bootloader) must be active in the dongle.
++ */
++int
++dbus_up(struct dhd_bus *pub)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++	int err = DBUS_OK;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dhd_bus == NULL) {
++		DBUSERR(("%s: dhd_bus is NULL\n", __FUNCTION__));
++		return DBUS_ERR;
++	}
++
++	if ((dhd_bus->pub.busstate == DBUS_STATE_DL_DONE) ||
++		(dhd_bus->pub.busstate == DBUS_STATE_DOWN) ||
++		(dhd_bus->pub.busstate == DBUS_STATE_SLEEP)) {
++		if (dhd_bus->drvintf && dhd_bus->drvintf->up) {
++			err = dhd_bus->drvintf->up(dhd_bus->bus_info);
++
++			if (err == DBUS_OK) {
++				dbus_rxirbs_fill(dhd_bus);
++			}
++		}
++	} else
++		err = DBUS_ERR;
++
++	return err;
++}
++
++/** higher layer requests us to 'down' the interface to the dongle. */
++int
++dbus_down(dbus_pub_t *pub)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dhd_bus == NULL)
++		return DBUS_ERR;
++
++	dbus_tx_timer_stop(dhd_bus);
++
++	if (dhd_bus->pub.busstate == DBUS_STATE_UP ||
++		dhd_bus->pub.busstate == DBUS_STATE_SLEEP) {
++		if (dhd_bus->drvintf && dhd_bus->drvintf->down)
++			return dhd_bus->drvintf->down(dhd_bus->bus_info);
++	}
++
++	return DBUS_ERR;
++}
++
++int
++dbus_shutdown(dbus_pub_t *pub)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dhd_bus == NULL)
++		return DBUS_ERR;
++
++	if (dhd_bus->drvintf && dhd_bus->drvintf->shutdown)
++		return dhd_bus->drvintf->shutdown(dhd_bus->bus_info);
++
++	return DBUS_OK;
++}
++
++int
++dbus_stop(struct dhd_bus *pub)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dhd_bus == NULL)
++		return DBUS_ERR;
++
++	if (dhd_bus->pub.busstate == DBUS_STATE_UP ||
++		dhd_bus->pub.busstate == DBUS_STATE_SLEEP) {
++		if (dhd_bus->drvintf && dhd_bus->drvintf->stop)
++			return dhd_bus->drvintf->stop(dhd_bus->bus_info);
++	}
++
++	return DBUS_ERR;
++}
++
++int dbus_send_txdata(dbus_pub_t *dbus, void *pktbuf)
++{
++	return dbus_send_pkt(dbus, pktbuf, pktbuf /* pktinfo */);
++}
++
++int
++dbus_send_buf(dbus_pub_t *pub, uint8 *buf, int len, void *info)
++{
++	return dbus_send_irb(pub, buf, len, NULL, info);
++}
++
++int
++dbus_send_pkt(dbus_pub_t *pub, void *pkt, void *info)
++{
++	return dbus_send_irb(pub, NULL, 0, pkt, info);
++}
++
++int
++dbus_send_ctl(struct dhd_bus *pub, uint8 *buf, int len)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++
++	if (dhd_bus == NULL) {
++		DBUSERR(("%s: dhd_bus is NULL\n", __FUNCTION__));
++		return DBUS_ERR;
++	}
++
++	if (dhd_bus->pub.busstate == DBUS_STATE_UP ||
++		dhd_bus->pub.busstate == DBUS_STATE_SLEEP) {
++		if (dhd_bus->drvintf && dhd_bus->drvintf->send_ctl)
++			return dhd_bus->drvintf->send_ctl(dhd_bus->bus_info, buf, len);
++	} else {
++		DBUSERR(("%s: bustate=%d\n", __FUNCTION__, dhd_bus->pub.busstate));
++	}
++
++	return DBUS_ERR;
++}
++
++int
++dbus_recv_ctl(struct dhd_bus *pub, uint8 *buf, int len)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++
++	if ((dhd_bus == NULL) || (buf == NULL))
++		return DBUS_ERR;
++
++	if (dhd_bus->pub.busstate == DBUS_STATE_UP ||
++		dhd_bus->pub.busstate == DBUS_STATE_SLEEP) {
++		if (dhd_bus->drvintf && dhd_bus->drvintf->recv_ctl)
++			return dhd_bus->drvintf->recv_ctl(dhd_bus->bus_info, buf, len);
++	}
++
++	return DBUS_ERR;
++}
++
++/** Only called via RPC (Dec 2012) */
++int
++dbus_recv_bulk(dbus_pub_t *pub, uint32 ep_idx)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++
++	dbus_irb_rx_t *rxirb;
++	struct exec_parms args;
++	int status;
++
++
++	if (dhd_bus == NULL)
++		return DBUS_ERR;
++
++	args.qdeq.q = dhd_bus->rx_q;
++	if (dhd_bus->pub.busstate == DBUS_STATE_UP) {
++		if (dhd_bus->drvintf && dhd_bus->drvintf->recv_irb_from_ep) {
++			if ((rxirb = (EXEC_RXLOCK(dhd_bus, q_deq_exec, &args))) != NULL) {
++				status = dhd_bus->drvintf->recv_irb_from_ep(dhd_bus->bus_info,
++					rxirb, ep_idx);
++				if (status == DBUS_ERR_RXDROP) {
++					bzero(rxirb, sizeof(dbus_irb_rx_t));
++					args.qenq.q = dhd_bus->rx_q;
++					args.qenq.b = (dbus_irb_t *) rxirb;
++					EXEC_RXLOCK(dhd_bus, q_enq_exec, &args);
++				}
++			}
++		}
++	}
++
++	return DBUS_ERR;
++}
++
++/** only called by dhd_cdc.c (Dec 2012) */
++int
++dbus_poll_intr(dbus_pub_t *pub)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++
++	int status = DBUS_ERR;
++
++	if (dhd_bus == NULL)
++		return DBUS_ERR;
++
++	if (dhd_bus->pub.busstate == DBUS_STATE_UP) {
++		if (dhd_bus->drvintf && dhd_bus->drvintf->recv_irb_from_ep) {
++			status = dhd_bus->drvintf->recv_irb_from_ep(dhd_bus->bus_info,
++				NULL, 0xff);
++		}
++	}
++	return status;
++}
++
++/** called by nobody (Dec 2012) */
++void *
++dbus_pktget(dbus_pub_t *pub, int len)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++
++	if ((dhd_bus == NULL) || (len < 0))
++		return NULL;
++
++	return PKTGET(dhd_bus->pub.osh, len, TRUE);
++}
++
++/** called by nobody (Dec 2012) */
++void
++dbus_pktfree(dbus_pub_t *pub, void* pkt)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++
++	if ((dhd_bus == NULL) || (pkt == NULL))
++		return;
++
++	PKTFREE(dhd_bus->pub.osh, pkt, TRUE);
++}
++
++/** called by nobody (Dec 2012) */
++int
++dbus_get_stats(dbus_pub_t *pub, dbus_stats_t *stats)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++
++	if ((dhd_bus == NULL) || (stats == NULL))
++		return DBUS_ERR;
++
++	bcopy(&dhd_bus->pub.stats, stats, sizeof(dbus_stats_t));
++
++	return DBUS_OK;
++}
++
++int
++dbus_get_attrib(dhd_bus_t *pub, dbus_attrib_t *attrib)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++	int err = DBUS_ERR;
++
++	if ((dhd_bus == NULL) || (attrib == NULL))
++		return DBUS_ERR;
++
++	if (dhd_bus->drvintf && dhd_bus->drvintf->get_attrib) {
++		err = dhd_bus->drvintf->get_attrib(dhd_bus->bus_info,
++		&dhd_bus->pub.attrib);
++	}
++
++	bcopy(&dhd_bus->pub.attrib, attrib, sizeof(dbus_attrib_t));
++	return err;
++}
++
++int
++dbus_get_device_speed(dbus_pub_t *pub)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++
++	if (dhd_bus == NULL)
++		return INVALID_SPEED;
++
++	return (dhd_bus->pub.device_speed);
++}
++
++int
++dbus_set_config(dbus_pub_t *pub, dbus_config_t *config)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++	int err = DBUS_ERR;
++
++	if ((dhd_bus == NULL) || (config == NULL))
++		return DBUS_ERR;
++
++	if (dhd_bus->drvintf && dhd_bus->drvintf->set_config) {
++		err = dhd_bus->drvintf->set_config(dhd_bus->bus_info,
++			config);
++
++		if ((config->config_id == DBUS_CONFIG_ID_AGGR_LIMIT) &&
++			(!err) &&
++			(dhd_bus->pub.busstate == DBUS_STATE_UP)) {
++			dbus_rxirbs_fill(dhd_bus);
++		}
++	}
++
++	return err;
++}
++
++int
++dbus_get_config(dbus_pub_t *pub, dbus_config_t *config)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++	int err = DBUS_ERR;
++
++	if ((dhd_bus == NULL) || (config == NULL))
++		return DBUS_ERR;
++
++	if (dhd_bus->drvintf && dhd_bus->drvintf->get_config) {
++		err = dhd_bus->drvintf->get_config(dhd_bus->bus_info,
++		config);
++	}
++
++	return err;
++}
++
++int
++dbus_set_errmask(dbus_pub_t *pub, uint32 mask)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++	int err = DBUS_OK;
++
++	if (dhd_bus == NULL)
++		return DBUS_ERR;
++
++	dhd_bus->errmask = mask;
++	return err;
++}
++
++int
++dbus_pnp_resume(dbus_pub_t *pub, int *fw_reload)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++	int err = DBUS_ERR;
++	bool fwdl = FALSE;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dhd_bus == NULL)
++		return DBUS_ERR;
++
++	if (dhd_bus->pub.busstate == DBUS_STATE_UP) {
++		return DBUS_OK;
++	}
++
++
++
++	if (dhd_bus->drvintf->pnp) {
++		err = dhd_bus->drvintf->pnp(dhd_bus->bus_info,
++			DBUS_PNP_RESUME);
++	}
++
++	if (dhd_bus->drvintf->recv_needed) {
++		if (dhd_bus->drvintf->recv_needed(dhd_bus->bus_info)) {
++			/* Refill after sleep/hibernate */
++			dbus_rxirbs_fill(dhd_bus);
++		}
++	}
++
++
++	if (fw_reload)
++		*fw_reload = fwdl;
++
++	return err;
++} /* dbus_pnp_resume */
++
++int
++dbus_pnp_sleep(dbus_pub_t *pub)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++	int err = DBUS_ERR;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dhd_bus == NULL)
++		return DBUS_ERR;
++
++	dbus_tx_timer_stop(dhd_bus);
++
++	if (dhd_bus->drvintf && dhd_bus->drvintf->pnp) {
++		err = dhd_bus->drvintf->pnp(dhd_bus->bus_info,
++			DBUS_PNP_SLEEP);
++	}
++
++	return err;
++}
++
++int
++dbus_pnp_disconnect(dbus_pub_t *pub)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) pub;
++	int err = DBUS_ERR;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dhd_bus == NULL)
++		return DBUS_ERR;
++
++	dbus_tx_timer_stop(dhd_bus);
++
++	if (dhd_bus->drvintf && dhd_bus->drvintf->pnp) {
++		err = dhd_bus->drvintf->pnp(dhd_bus->bus_info,
++			DBUS_PNP_DISCONNECT);
++	}
++
++	return err;
++}
++
++int
++dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
++	void *params, int plen, void *arg, int len, bool set)
++{
++	dhd_bus_t *dhd_bus = (dhd_bus_t *) dhdp->bus;
++	int err = DBUS_ERR;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dhd_bus == NULL)
++		return DBUS_ERR;
++
++	if (dhd_bus->drvintf && dhd_bus->drvintf->iovar_op) {
++		err = dhd_bus->drvintf->iovar_op(dhd_bus->bus_info,
++			name, params, plen, arg, len, set);
++	}
++
++	return err;
++}
++
++
++void *
++dhd_dbus_txq(const dbus_pub_t *pub)
++{
++	return NULL;
++}
++
++uint
++dhd_dbus_hdrlen(const dbus_pub_t *pub)
++{
++	return 0;
++}
++
++void *
++dbus_get_devinfo(dbus_pub_t *pub)
++{
++	return pub->dev_info;
++}
++
++#if defined(BCM_REQUEST_FW) && !defined(EXTERNAL_FW_PATH)
++static int
++dbus_otp(dhd_bus_t *dhd_bus, uint16 *boardtype, uint16 *boardrev)
++{
++	uint32 value = 0;
++	uint8 *cis;
++	uint16 *otpinfo;
++	uint32 i;
++	bool standard_cis = TRUE;
++	uint8 tup, tlen;
++	bool btype_present = FALSE;
++	bool brev_present = FALSE;
++	int ret;
++	int devid;
++	uint16 btype = 0;
++	uint16 brev = 0;
++	uint32 otp_size = 0, otp_addr = 0, otp_sw_rgn = 0;
++
++	if (dhd_bus == NULL || dhd_bus->drvintf == NULL ||
++		dhd_bus->drvintf->readreg == NULL)
++		return DBUS_ERR;
++
++	devid = dhd_bus->pub.attrib.devid;
++
++	if ((devid == BCM43234_CHIP_ID) || (devid == BCM43235_CHIP_ID) ||
++		(devid == BCM43236_CHIP_ID)) {
++
++		otp_size = BCM_OTP_SIZE_43236;
++		otp_sw_rgn = BCM_OTP_SW_RGN_43236;
++		otp_addr = BCM_OTP_ADDR_43236;
++
++	} else {
++		return DBUS_ERR_NVRAM;
++	}
++
++	cis = MALLOC(dhd_bus->pub.osh, otp_size * 2);
++	if (cis == NULL)
++		return DBUS_ERR;
++
++	otpinfo = (uint16 *) cis;
++
++	for (i = 0; i < otp_size; i++) {
++
++		ret = dhd_bus->drvintf->readreg(dhd_bus->bus_info,
++			otp_addr + ((otp_sw_rgn + i) << 1), 2, &value);
++
++		if (ret != DBUS_OK) {
++			MFREE(dhd_bus->pub.osh, cis, otp_size * 2);
++			return ret;
++		}
++		otpinfo[i] = (uint16) value;
++	}
++
++	for (i = 0; i < (otp_size << 1); ) {
++
++		if (standard_cis) {
++			tup = cis[i++];
++			if (tup == CISTPL_NULL || tup == CISTPL_END)
++				tlen = 0;
++			else
++				tlen = cis[i++];
++		} else {
++			if (cis[i] == CISTPL_NULL || cis[i] == CISTPL_END) {
++				tlen = 0;
++				tup = cis[i];
++			} else {
++				tlen = cis[i];
++				tup = CISTPL_BRCM_HNBU;
++			}
++			++i;
++		}
++
++		if (tup == CISTPL_END || (i + tlen) >= (otp_size << 1)) {
++			break;
++		}
++
++		switch (tup) {
++
++		case CISTPL_BRCM_HNBU:
++
++			switch (cis[i]) {
++
++			case HNBU_BOARDTYPE:
++
++				btype = (uint16) ((cis[i + 2] << 8) + cis[i + 1]);
++				btype_present = TRUE;
++				DBUSTRACE(("%s: HNBU_BOARDTYPE = 0x%2x\n", __FUNCTION__,
++					(uint32)btype));
++				break;
++
++			case HNBU_BOARDREV:
++
++				if (tlen == 2)
++					brev = (uint16) cis[i + 1];
++				else
++					brev = (uint16) ((cis[i + 2] << 8) + cis[i + 1]);
++				brev_present = TRUE;
++				DBUSTRACE(("%s: HNBU_BOARDREV =  0x%2x\n", __FUNCTION__,
++					(uint32)*boardrev));
++				break;
++
++			case HNBU_HNBUCIS:
++				DBUSTRACE(("%s: HNBU_HNBUCIS\n", __FUNCTION__));
++				tlen++;
++				standard_cis = FALSE;
++				break;
++			}
++			break;
++		}
++
++		i += tlen;
++	}
++
++	MFREE(dhd_bus->pub.osh, cis, otp_size * 2);
++
++	if (btype_present == TRUE && brev_present == TRUE) {
++		*boardtype = btype;
++		*boardrev = brev;
++		DBUSERR(("otp boardtype = 0x%2x boardrev = 0x%2x\n",
++			*boardtype, *boardrev));
++
++		return DBUS_OK;
++	}
++	else
++		return DBUS_ERR;
++} /* dbus_otp */
++
++static int
++dbus_select_nvram(dhd_bus_t *dhd_bus, int8 *jumbonvram, int jumbolen,
++uint16 boardtype, uint16 boardrev, int8 **nvram, int *nvram_len)
++{
++	/* Multi board nvram file format is contenation of nvram info with \r
++	*  The file format for two contatenated set is
++	*  \nBroadcom Jumbo Nvram file\nfirst_set\nsecond_set\nthird_set\n
++	*/
++	uint8 *nvram_start = NULL, *nvram_end = NULL;
++	uint8 *nvram_start_prev = NULL, *nvram_end_prev = NULL;
++	uint16 btype = 0, brev = 0;
++	int len  = 0;
++	char *field;
++
++	*nvram = NULL;
++	*nvram_len = 0;
++
++	if (strncmp(BCM_JUMBO_START, jumbonvram, strlen(BCM_JUMBO_START))) {
++		/* single nvram file in the native format */
++		DBUSTRACE(("%s: Non-Jumbo NVRAM File \n", __FUNCTION__));
++		*nvram = jumbonvram;
++		*nvram_len = jumbolen;
++		return DBUS_OK;
++	} else {
++		DBUSTRACE(("%s: Jumbo NVRAM File \n", __FUNCTION__));
++	}
++
++	/* sanity test the end of the config sets for proper ending */
++	if (jumbonvram[jumbolen - 1] != BCM_JUMBO_NVRAM_DELIMIT ||
++		jumbonvram[jumbolen - 2] != '\0') {
++		DBUSERR(("%s: Bad Jumbo NVRAM file format\n", __FUNCTION__));
++		return DBUS_JUMBO_BAD_FORMAT;
++	}
++
++	dhd_bus->nvram_nontxt = DBUS_NVRAM_NONTXT;
++
++	nvram_start = jumbonvram;
++
++	while (*nvram_start != BCM_JUMBO_NVRAM_DELIMIT && len < jumbolen) {
++
++		/* consume the  first file info line
++		* \nBroadcom Jumbo Nvram file\nfile1\n ...
++		*/
++		len ++;
++		nvram_start ++;
++	}
++
++	nvram_end = nvram_start;
++
++	/* search for "boardrev=0xabcd" and "boardtype=0x1234" information in
++	* the concatenated nvram config files /sets
++	*/
++
++	while (len < jumbolen) {
++
++		if (*nvram_end == '\0') {
++			/* end of a config set is marked by multiple null characters */
++			len ++;
++			nvram_end ++;
++			DBUSTRACE(("%s: NULL chr len = %d char = 0x%x\n", __FUNCTION__,
++				len, *nvram_end));
++			continue;
++
++		} else if (*nvram_end == BCM_JUMBO_NVRAM_DELIMIT) {
++
++			/* config set delimiter is reached */
++			/* check if next config set is present or not
++			*  return  if next config is not present
++			*/
++
++			/* start search the next config set */
++			nvram_start_prev = nvram_start;
++			nvram_end_prev = nvram_end;
++
++			nvram_end ++;
++			nvram_start = nvram_end;
++			btype = brev = 0;
++			DBUSTRACE(("%s: going to next record len = %d "
++					"char = 0x%x \n", __FUNCTION__, len, *nvram_end));
++			len ++;
++			if (len >= jumbolen) {
++
++				*nvram = nvram_start_prev;
++				*nvram_len = (int)(nvram_end_prev - nvram_start_prev);
++
++				DBUSTRACE(("%s: no more len = %d nvram_end = 0x%p",
++					__FUNCTION__, len, nvram_end));
++
++				return DBUS_JUMBO_NOMATCH;
++
++			} else {
++				continue;
++			}
++
++		} else {
++
++			DBUSTRACE(("%s: config str = %s\n", __FUNCTION__, nvram_end));
++
++			if (bcmp(nvram_end, "boardtype", strlen("boardtype")) == 0) {
++
++				field = strchr(nvram_end, '=');
++				field++;
++				btype = (uint16)bcm_strtoul(field, NULL, 0);
++
++				DBUSTRACE(("%s: btype = 0x%x boardtype = 0x%x \n", __FUNCTION__,
++					btype, boardtype));
++			}
++
++			if (bcmp(nvram_end, "boardrev", strlen("boardrev")) == 0) {
++
++				field = strchr(nvram_end, '=');
++				field++;
++				brev = (uint16)bcm_strtoul(field, NULL, 0);
++
++				DBUSTRACE(("%s: brev = 0x%x boardrev = 0x%x \n", __FUNCTION__,
++					brev, boardrev));
++			}
++			if (btype == boardtype && brev == boardrev) {
++				/* locate nvram config set end - ie.find '\r' char */
++				while (*nvram_end != BCM_JUMBO_NVRAM_DELIMIT)
++					nvram_end ++;
++				*nvram = nvram_start;
++				*nvram_len = (int) (nvram_end - nvram_start);
++				DBUSTRACE(("found len = %d nvram_start = 0x%p "
++					"nvram_end = 0x%p\n", *nvram_len, nvram_start, nvram_end));
++				return DBUS_OK;
++			}
++
++			len += (strlen(nvram_end) + 1);
++			nvram_end += (strlen(nvram_end) + 1);
++		}
++	}
++	return DBUS_JUMBO_NOMATCH;
++} /* dbus_select_nvram */
++
++#endif 
++
++#define DBUS_NRXQ	50
++#define DBUS_NTXQ	100
++
++static void
++dhd_dbus_send_complete(void *handle, void *info, int status)
++{
++	dhd_pub_t *dhd = (dhd_pub_t *)handle;
++	void *pkt = info;
++
++	if ((dhd == NULL) || (pkt == NULL)) {
++		DBUSERR(("dhd or pkt is NULL\n"));
++		return;
++	}
++
++	if (status == DBUS_OK) {
++		dhd->dstats.tx_packets++;
++	} else {
++		DBUSERR(("TX error=%d\n", status));
++		dhd->dstats.tx_errors++;
++	}
++#ifdef PROP_TXSTATUS
++	if (DHD_PKTTAG_WLFCPKT(PKTTAG(pkt)) &&
++		(dhd_wlfc_txcomplete(dhd, pkt, status == 0) != WLFC_UNSUPPORTED)) {
++		return;
++	}
++#endif /* PROP_TXSTATUS */
++	PKTFREE(dhd->osh, pkt, TRUE);
++}
++
++static void
++dhd_dbus_recv_pkt(void *handle, void *pkt)
++{
++	uchar reorder_info_buf[WLHOST_REORDERDATA_TOTLEN];
++	uint reorder_info_len;
++	uint pkt_count;
++	dhd_pub_t *dhd = (dhd_pub_t *)handle;
++	int ifidx = 0;
++
++	if (dhd == NULL) {
++		DBUSERR(("%s: dhd is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	/* If the protocol uses a data header, check and remove it */
++	if (dhd_prot_hdrpull(dhd, &ifidx, pkt, reorder_info_buf,
++		&reorder_info_len) != 0) {
++		DBUSERR(("rx protocol error\n"));
++		PKTFREE(dhd->osh, pkt, FALSE);
++		dhd->rx_errors++;
++		return;
++	}
++
++	if (reorder_info_len) {
++		/* Reordering info from the firmware */
++		dhd_process_pkt_reorder_info(dhd, reorder_info_buf, reorder_info_len,
++			&pkt, &pkt_count);
++		if (pkt_count == 0)
++			return;
++	}
++	else {
++		pkt_count = 1;
++	}
++	dhd_rx_frame(dhd, ifidx, pkt, pkt_count, 0);
++}
++
++static void
++dhd_dbus_recv_buf(void *handle, uint8 *buf, int len)
++{
++	dhd_pub_t *dhd = (dhd_pub_t *)handle;
++	void *pkt;
++
++	if (dhd == NULL) {
++		DBUSERR(("%s: dhd is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if ((pkt = PKTGET(dhd->osh, len, FALSE)) == NULL) {
++		DBUSERR(("PKTGET (rx) failed=%d\n", len));
++		return;
++	}
++
++	bcopy(buf, PKTDATA(dhd->osh, pkt), len);
++	dhd_dbus_recv_pkt(dhd, pkt);
++}
++
++static void
++dhd_dbus_txflowcontrol(void *handle, bool onoff)
++{
++	dhd_pub_t *dhd = (dhd_pub_t *)handle;
++	bool wlfc_enabled = FALSE;
++
++	if (dhd == NULL) {
++		DBUSERR(("%s: dhd is NULL\n", __FUNCTION__));
++		return;
++	}
++
++#ifdef PROP_TXSTATUS
++	wlfc_enabled = (dhd_wlfc_flowcontrol(dhd, onoff, !onoff) != WLFC_UNSUPPORTED);
++#endif
++
++	if (!wlfc_enabled) {
++		dhd_txflowcontrol(dhd, ALL_INTERFACES, onoff);
++	}
++}
++
++static void
++dhd_dbus_errhandler(void *handle, int err)
++{
++}
++
++static void
++dhd_dbus_ctl_complete(void *handle, int type, int status)
++{
++	dhd_pub_t *dhd = (dhd_pub_t *)handle;
++
++	if (dhd == NULL) {
++		DBUSERR(("%s: dhd is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (type == DBUS_CBCTL_READ) {
++		if (status == DBUS_OK)
++			dhd->rx_ctlpkts++;
++		else
++			dhd->rx_ctlerrs++;
++	} else if (type == DBUS_CBCTL_WRITE) {
++		if (status == DBUS_OK)
++			dhd->tx_ctlpkts++;
++		else
++			dhd->tx_ctlerrs++;
++	}
++
++	dhd_prot_ctl_complete(dhd);
++}
++
++static void
++dhd_dbus_state_change(void *handle, int state)
++{
++	dhd_pub_t *dhd = (dhd_pub_t *)handle;
++
++	if (dhd == NULL) {
++		DBUSERR(("%s: dhd is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	switch (state) {
++
++		case DBUS_STATE_DL_NEEDED:
++			DBUSERR(("%s: firmware request cannot be handled\n", __FUNCTION__));
++			break;
++		case DBUS_STATE_DOWN:
++			DBUSTRACE(("%s: DBUS is down\n", __FUNCTION__));
++			dhd->busstate = DHD_BUS_DOWN;
++			break;
++		case DBUS_STATE_UP:
++			DBUSTRACE(("%s: DBUS is up\n", __FUNCTION__));
++			dhd->busstate = DHD_BUS_DATA;
++			break;
++		default:
++			break;
++	}
++
++	DBUSERR(("%s: DBUS current state=%d\n", __FUNCTION__, state));
++}
++
++static void *
++dhd_dbus_pktget(void *handle, uint len, bool send)
++{
++	dhd_pub_t *dhd = (dhd_pub_t *)handle;
++	void *p = NULL;
++
++	if (dhd == NULL) {
++		DBUSERR(("%s: dhd is NULL\n", __FUNCTION__));
++		return NULL;
++	}
++
++	if (send == TRUE) {
++		dhd_os_sdlock_txq(dhd);
++		p = PKTGET(dhd->osh, len, TRUE);
++		dhd_os_sdunlock_txq(dhd);
++	} else {
++		dhd_os_sdlock_rxq(dhd);
++		p = PKTGET(dhd->osh, len, FALSE);
++		dhd_os_sdunlock_rxq(dhd);
++	}
++
++	return p;
++}
++
++static void
++dhd_dbus_pktfree(void *handle, void *p, bool send)
++{
++	dhd_pub_t *dhd = (dhd_pub_t *)handle;
++
++	if (dhd == NULL) {
++		DBUSERR(("%s: dhd is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (send == TRUE) {
++#ifdef PROP_TXSTATUS
++		if (DHD_PKTTAG_WLFCPKT(PKTTAG(p)) &&
++			(dhd_wlfc_txcomplete(dhd, p, FALSE) != WLFC_UNSUPPORTED)) {
++			return;
++		}
++#endif /* PROP_TXSTATUS */
++
++		dhd_os_sdlock_txq(dhd);
++		PKTFREE(dhd->osh, p, TRUE);
++		dhd_os_sdunlock_txq(dhd);
++	} else {
++		dhd_os_sdlock_rxq(dhd);
++		PKTFREE(dhd->osh, p, FALSE);
++		dhd_os_sdunlock_rxq(dhd);
++	}
++}
++
++
++static dbus_callbacks_t dhd_dbus_cbs = {
++	dhd_dbus_send_complete,
++	dhd_dbus_recv_buf,
++	dhd_dbus_recv_pkt,
++	dhd_dbus_txflowcontrol,
++	dhd_dbus_errhandler,
++	dhd_dbus_ctl_complete,
++	dhd_dbus_state_change,
++	dhd_dbus_pktget,
++	dhd_dbus_pktfree
++};
++
++uint
++dhd_bus_chip(struct dhd_bus *bus)
++{
++	ASSERT(bus != NULL);
++	return bus->pub.attrib.devid;
++}
++
++uint
++dhd_bus_chiprev(struct dhd_bus *bus)
++{
++	ASSERT(bus);
++	ASSERT(bus != NULL);
++	return bus->pub.attrib.chiprev;
++}
++
++void
++dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
++{
++	bcm_bprintf(strbuf, "Bus USB\n");
++}
++
++void
++dhd_bus_clearcounts(dhd_pub_t *dhdp)
++{
++}
++
++int
++dhd_bus_txdata(struct dhd_bus *bus, void *pktbuf)
++{
++	DBUSTRACE(("%s\n", __FUNCTION__));
++	if (bus->txoff) {
++		DBUSTRACE(("txoff\n"));
++		return BCME_EPERM;
++	}
++	return dbus_send_txdata(&bus->pub, pktbuf);
++}
++
++static void
++dhd_dbus_advertise_bus_cleanup(dhd_pub_t *dhdp)
++{
++	unsigned long flags;
++	int timeleft;
++
++	DHD_LINUX_GENERAL_LOCK(dhdp, flags);
++	dhdp->busstate = DHD_BUS_DOWN_IN_PROGRESS;
++	DHD_LINUX_GENERAL_UNLOCK(dhdp, flags);
++
++	timeleft = dhd_os_busbusy_wait_negation(dhdp, &dhdp->dhd_bus_busy_state);
++	if ((timeleft == 0) || (timeleft == 1)) {
++		DBUSERR(("%s : Timeout due to dhd_bus_busy_state=0x%x\n",
++				__FUNCTION__, dhdp->dhd_bus_busy_state));
++		ASSERT(0);
++	}
++
++	return;
++}
++
++static void
++dhd_dbus_advertise_bus_remove(dhd_pub_t *dhdp)
++{
++	unsigned long flags;
++	int timeleft;
++
++	DHD_LINUX_GENERAL_LOCK(dhdp, flags);
++	dhdp->busstate = DHD_BUS_REMOVE;
++	DHD_LINUX_GENERAL_UNLOCK(dhdp, flags);
++
++	timeleft = dhd_os_busbusy_wait_negation(dhdp, &dhdp->dhd_bus_busy_state);
++	if ((timeleft == 0) || (timeleft == 1)) {
++		DBUSERR(("%s : Timeout due to dhd_bus_busy_state=0x%x\n",
++				__FUNCTION__, dhdp->dhd_bus_busy_state));
++		ASSERT(0);
++	}
++
++	return;
++}
++
++int
++dhd_bus_devreset(dhd_pub_t *dhdp, uint8 flag)
++{
++	int bcmerror = 0;
++	unsigned long flags;
++	wifi_adapter_info_t *adapter = (wifi_adapter_info_t *)dhdp->adapter;
++
++	if (flag == TRUE) {
++		if (!dhdp->dongle_reset) {
++			DBUSERR(("%s: == Power OFF ==\n", __FUNCTION__));
++			dhd_dbus_advertise_bus_cleanup(dhdp);
++			dhd_os_wd_timer(dhdp, 0);
++#if !defined(IGNORE_ETH0_DOWN)
++			/* Force flow control as protection when stop come before ifconfig_down */
++			dhd_txflowcontrol(dhdp, ALL_INTERFACES, ON);
++#endif /* !defined(IGNORE_ETH0_DOWN) */
++			dbus_stop(dhdp->bus);
++
++			dhdp->dongle_reset = TRUE;
++			dhdp->up = FALSE;
++
++			DHD_LINUX_GENERAL_LOCK(dhdp, flags);
++			dhdp->busstate = DHD_BUS_DOWN;
++			DHD_LINUX_GENERAL_UNLOCK(dhdp, flags);
++			wifi_clr_adapter_status(adapter, WIFI_STATUS_FW_READY);
++
++			printf("%s:  WLAN OFF DONE\n", __FUNCTION__);
++			/* App can now remove power from device */
++		} else
++			bcmerror = BCME_ERROR;
++	} else {
++		/* App must have restored power to device before calling */
++		printf("\n\n%s: == WLAN ON ==\n", __FUNCTION__);
++		if (dhdp->dongle_reset) {
++			/* Turn on WLAN */
++			DHD_MUTEX_UNLOCK();
++			wait_event_interruptible_timeout(adapter->status_event,
++				wifi_get_adapter_status(adapter, WIFI_STATUS_FW_READY),
++				msecs_to_jiffies(DHD_FW_READY_TIMEOUT));
++			DHD_MUTEX_LOCK();
++			bcmerror = dbus_up(dhdp->bus);
++			if (bcmerror == BCME_OK) {
++				dhdp->dongle_reset = FALSE;
++				dhdp->up = TRUE;
++#if !defined(IGNORE_ETH0_DOWN)
++				/* Restore flow control  */
++				dhd_txflowcontrol(dhdp, ALL_INTERFACES, OFF);
++#endif 
++				dhd_os_wd_timer(dhdp, dhd_watchdog_ms);
++
++				DBUSTRACE(("%s: WLAN ON DONE\n", __FUNCTION__));
++			} else {
++				DBUSERR(("%s: failed to dbus_up with code %d\n", __FUNCTION__, bcmerror));
++			}
++		}
++	}
++
++#ifdef PKT_STATICS
++	memset((uint8*) &tx_statics, 0, sizeof(pkt_statics_t));
++#endif
++	return bcmerror;
++}
++
++void
++dhd_bus_update_fw_nv_path(struct dhd_bus *bus, char *pfw_path,
++	char *pnv_path, char *pclm_path, char *pconf_path)
++{
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (bus == NULL) {
++		DBUSERR(("%s: bus is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	bus->fw_path = pfw_path;
++	bus->nv_path = pnv_path;
++	bus->dhd->clm_path = pclm_path;
++	bus->dhd->conf_path = pconf_path;
++
++	dhd_conf_set_path_params(bus->dhd, bus->fw_path, bus->nv_path);
++
++}
++
++/*
++ * hdrlen is space to reserve in pkt headroom for DBUS
++ */
++void *
++dhd_dbus_probe_cb(void *arg, const char *desc, uint32 bustype,
++	uint16 bus_no, uint16 slot, uint32 hdrlen)
++{
++	osl_t *osh = NULL;
++	dhd_bus_t *bus = NULL;
++	dhd_pub_t *pub = NULL;
++	uint rxsz;
++	int dlneeded = 0;
++	wifi_adapter_info_t *adapter = NULL;
++
++	DBUSTRACE(("%s: Enter\n", __FUNCTION__));
++
++	adapter = dhd_wifi_platform_get_adapter(bustype, bus_no, slot);
++
++	if (!g_pub) {
++		/* Ask the OS interface part for an OSL handle */
++		if (!(osh = osl_attach(NULL, bustype, TRUE))) {
++			DBUSERR(("%s: OSL attach failed\n", __FUNCTION__));
++			goto fail;
++		}
++
++		/* Attach to the dhd/OS interface */
++		if (!(pub = dhd_attach(osh, bus, hdrlen, adapter))) {
++			DBUSERR(("%s: dhd_attach failed\n", __FUNCTION__));
++			goto fail;
++		}
++	} else {
++		pub = g_pub;
++		osh = pub->osh;
++	}
++
++	if (pub->bus) {
++		DBUSERR(("%s: wrong probe\n", __FUNCTION__));
++		goto fail;
++	}
++
++	rxsz = dhd_get_rxsz(pub);
++	bus = dbus_attach(osh, rxsz, DBUS_NRXQ, DBUS_NTXQ, pub, &dhd_dbus_cbs, NULL, NULL);
++	if (bus) {
++		pub->bus = bus;
++		bus->dhd = pub;
++
++		dlneeded = dbus_dlneeded(bus);
++		if (dlneeded >= 0) {
++			if (!g_pub) {
++				dhd_conf_reset(pub);
++				dhd_conf_set_chiprev(pub, bus->pub.attrib.devid, bus->pub.attrib.chiprev);
++				dhd_conf_preinit(pub);
++			}
++		}
++
++		if (g_pub || dhd_download_fw_on_driverload) {
++			if (dlneeded == 0) {
++				wifi_set_adapter_status(adapter, WIFI_STATUS_FW_READY);
++#ifdef BCM_REQUEST_FW
++			} else if (dlneeded > 0) {
++				dhd_set_path(bus->dhd);
++				if (dbus_download_firmware(bus, bus->fw_path, bus->nv_path) != DBUS_OK)
++					goto fail;
++#endif
++			} else {
++				goto fail;
++			}
++		}
++	} else {
++		DBUSERR(("%s: dbus_attach failed\n", __FUNCTION__));
++	}
++
++	if (!g_pub) {
++		/* Ok, finish the attach to the OS network interface */
++		if (dhd_register_if(pub, 0, TRUE) != 0) {
++			DBUSERR(("%s: dhd_register_if failed\n", __FUNCTION__));
++			goto fail;
++		}
++		pub->hang_report  = TRUE;
++#if defined(MULTIPLE_SUPPLICANT)
++		wl_android_post_init(); // terence 20120530: fix critical section in dhd_open and dhdsdio_probe
++#endif
++		g_pub = pub;
++	}
++
++	DBUSTRACE(("%s: Exit\n", __FUNCTION__));
++	wifi_clr_adapter_status(adapter, WIFI_STATUS_DETTACH);
++	wifi_set_adapter_status(adapter, WIFI_STATUS_ATTACH);
++	wake_up_interruptible(&adapter->status_event);
++	/* This is passed to dhd_dbus_disconnect_cb */
++	return bus;
++
++fail:
++	if (pub && pub->bus) {
++		dbus_detach(pub->bus);
++		pub->bus = NULL;
++	}
++	/* Release resources in reverse order */
++	if (!g_pub) {
++		if (pub) {
++			dhd_detach(pub);
++			dhd_free(pub);
++		}
++		if (osh) {
++			osl_detach(osh);
++		}
++	}
++
++	printf("%s: Failed\n", __FUNCTION__);
++	return NULL;
++}
++
++void
++dhd_dbus_disconnect_cb(void *arg)
++{
++	dhd_bus_t *bus = (dhd_bus_t *)arg;
++	dhd_pub_t *pub = g_pub;
++	osl_t *osh;
++	wifi_adapter_info_t *adapter = NULL;
++
++	adapter = (wifi_adapter_info_t *)pub->adapter;
++
++	if (pub && !pub->dhd_remove && bus == NULL) {
++		DBUSERR(("%s: bus is NULL\n", __FUNCTION__));
++		return;
++	}
++	if (!adapter) {
++		DBUSERR(("%s: adapter is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	printf("%s: Enter dhd_remove=%d on %s\n", __FUNCTION__,
++		pub->dhd_remove, adapter->name);
++	if (!pub->dhd_remove) {
++		/* Advertise bus remove during rmmod */
++		dhd_dbus_advertise_bus_remove(bus->dhd);
++		dbus_detach(pub->bus);
++		pub->bus = NULL;
++		wifi_clr_adapter_status(adapter, WIFI_STATUS_ATTACH);
++		wifi_set_adapter_status(adapter, WIFI_STATUS_DETTACH);
++		wake_up_interruptible(&adapter->status_event);
++	} else {
++		osh = pub->osh;
++		dhd_detach(pub);
++		if (pub->bus) {
++			dbus_detach(pub->bus);
++			pub->bus = NULL;
++		}
++		dhd_free(pub);
++		g_pub = NULL;
++		if (MALLOCED(osh)) {
++			DBUSERR(("%s: MEMORY LEAK %d bytes\n", __FUNCTION__, MALLOCED(osh)));
++		}
++		osl_detach(osh);
++	}
++
++	DBUSTRACE(("%s: Exit\n", __FUNCTION__));
++}
++
++#ifdef LINUX_EXTERNAL_MODULE_DBUS
++
++static int __init
++bcm_dbus_module_init(void)
++{
++	printf("Inserting bcm_dbus module \n");
++	return 0;
++}
++
++static void __exit
++bcm_dbus_module_exit(void)
++{
++	printf("Removing bcm_dbus module \n");
++	return;
++}
++
++EXPORT_SYMBOL(dbus_pnp_sleep);
++EXPORT_SYMBOL(dbus_get_devinfo);
++EXPORT_SYMBOL(dbus_detach);
++EXPORT_SYMBOL(dbus_get_attrib);
++EXPORT_SYMBOL(dbus_down);
++EXPORT_SYMBOL(dbus_pnp_resume);
++EXPORT_SYMBOL(dbus_set_config);
++EXPORT_SYMBOL(dbus_flowctrl_rx);
++EXPORT_SYMBOL(dbus_up);
++EXPORT_SYMBOL(dbus_get_device_speed);
++EXPORT_SYMBOL(dbus_send_pkt);
++EXPORT_SYMBOL(dbus_recv_ctl);
++EXPORT_SYMBOL(dbus_attach);
++
++MODULE_LICENSE("GPL");
++
++module_init(bcm_dbus_module_init);
++module_exit(bcm_dbus_module_exit);
++
++#endif  /* #ifdef LINUX_EXTERNAL_MODULE_DBUS */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dbus_usb.c b/module_drivers/drivers/net/wireless/bcmdhd/dbus_usb.c
+new file mode 100644
+index 000000000..8a496dd1e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dbus_usb.c
+@@ -0,0 +1,1172 @@
++/*
++ * Dongle BUS interface for USB, OS independent
++ *
++ * Copyright (C) 1999-2016, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dbus_usb.c 565557 2015-06-22 19:29:44Z $
++ */
++
++/**
++ * @file @brief
++ * This file contains DBUS code that is USB, but not OS specific. DBUS is a Broadcom proprietary
++ * host specific abstraction layer.
++ */
++
++#include <osl.h>
++#include <bcmdefs.h>
++#include <bcmutils.h>
++#include <dbus.h>
++#include <usbrdl.h>
++#include <bcmdevs.h>
++#include <bcmendian.h>
++
++uint dbus_msglevel = DBUS_ERROR_VAL;
++module_param(dbus_msglevel, int, 0);
++
++
++#define USB_DLIMAGE_RETRY_TIMEOUT    3000    /* retry Timeout */
++#define USB_SFLASH_DLIMAGE_SPINWAIT  150     /* in unit of ms */
++#define USB_SFLASH_DLIMAGE_LIMIT     2000    /* spinwait limit (ms) */
++#define POSTBOOT_ID                  0xA123  /* ID to detect if dongle has boot up */
++#define USB_RESETCFG_SPINWAIT        1       /* wait after resetcfg (ms) */
++#define USB_DEV_ISBAD(u)             (u->pub->attrib.devid == 0xDEAD)
++#define USB_DLGO_SPINWAIT            100     /* wait after DL_GO (ms) */
++#define TEST_CHIP                    0x4328
++
++typedef struct {
++	dbus_pub_t  *pub;
++
++	void        *cbarg;
++	dbus_intf_callbacks_t *cbs;  /** callbacks into higher DBUS level (dbus.c) */
++	dbus_intf_t *drvintf;
++	void        *usbosl_info;
++	uint32      rdlram_base_addr;
++	uint32      rdlram_size;
++} usb_info_t;
++
++/*
++ * Callbacks common to all USB
++ */
++static void dbus_usb_disconnect(void *handle);
++static void dbus_usb_send_irb_timeout(void *handle, dbus_irb_tx_t *txirb);
++static void dbus_usb_send_irb_complete(void *handle, dbus_irb_tx_t *txirb, int status);
++static void dbus_usb_recv_irb_complete(void *handle, dbus_irb_rx_t *rxirb, int status);
++static void dbus_usb_errhandler(void *handle, int err);
++static void dbus_usb_ctl_complete(void *handle, int type, int status);
++static void dbus_usb_state_change(void *handle, int state);
++static struct dbus_irb* dbus_usb_getirb(void *handle, bool send);
++static void dbus_usb_rxerr_indicate(void *handle, bool on);
++#if !defined(BCM_REQUEST_FW)
++static int dbus_usb_resetcfg(usb_info_t *usbinfo);
++#endif
++static int dbus_usb_iovar_op(void *bus, const char *name,
++	void *params, int plen, void *arg, int len, bool set);
++static int dbus_iovar_process(usb_info_t* usbinfo, const char *name,
++                 void *params, int plen, void *arg, int len, bool set);
++static int dbus_usb_doiovar(usb_info_t *bus, const bcm_iovar_t *vi, uint32 actionid,
++	const char *name, void *params, int plen, void *arg, int len, int val_size);
++static int dhdusb_downloadvars(usb_info_t *bus, void *arg, int len);
++
++static int dbus_usb_dl_writeimage(usb_info_t *usbinfo, uint8 *fw, int fwlen);
++static int dbus_usb_dlstart(void *bus, uint8 *fw, int len);
++static int dbus_usb_dlneeded(void *bus);
++static int dbus_usb_dlrun(void *bus);
++static int dbus_usb_rdl_dwnld_state(usb_info_t *usbinfo);
++
++
++/* OS specific */
++extern bool dbus_usbos_dl_cmd(void *info, uint8 cmd, void *buffer, int buflen);
++extern int dbus_usbos_wait(void *info, uint16 ms);
++extern int dbus_write_membytes(usb_info_t *usbinfo, bool set, uint32 address,
++	uint8 *data, uint size);
++extern bool dbus_usbos_dl_send_bulk(void *info, void *buffer, int len);
++extern int dbus_usbos_loopback_tx(void *usbos_info_ptr, int cnt, int size);
++
++/**
++ * These functions are called by the lower DBUS level (dbus_usb_os.c) to notify this DBUS level
++ * (dbus_usb.c) of an event.
++ */
++static dbus_intf_callbacks_t dbus_usb_intf_cbs = {
++	dbus_usb_send_irb_timeout,
++	dbus_usb_send_irb_complete,
++	dbus_usb_recv_irb_complete,
++	dbus_usb_errhandler,
++	dbus_usb_ctl_complete,
++	dbus_usb_state_change,
++	NULL,			/* isr */
++	NULL,			/* dpc */
++	NULL,			/* watchdog */
++	NULL,			/* dbus_if_pktget */
++	NULL, 			/* dbus_if_pktfree */
++	dbus_usb_getirb,
++	dbus_usb_rxerr_indicate
++};
++
++/* IOVar table */
++enum {
++	IOV_SET_DOWNLOAD_STATE = 1,
++	IOV_DBUS_MSGLEVEL,
++	IOV_MEMBYTES,
++	IOV_VARS,
++	IOV_LOOPBACK_TX
++};
++
++const bcm_iovar_t dhdusb_iovars[] = {
++	{"vars",	IOV_VARS,	0,	IOVT_BUFFER,	0 },
++	{"dbus_msglevel",	IOV_DBUS_MSGLEVEL,	0,	IOVT_UINT32,	0 },
++	{"dwnldstate",	IOV_SET_DOWNLOAD_STATE,	0,	IOVT_BOOL,	0 },
++	{"membytes",	IOV_MEMBYTES,	0,	IOVT_BUFFER,	2 * sizeof(int) },
++	{"usb_lb_txfer", IOV_LOOPBACK_TX, 0,    IOVT_BUFFER,    2 * sizeof(int) },
++	{NULL, 0, 0, 0, 0 }
++};
++
++/*
++ * Need global for probe() and disconnect() since
++ * attach() is not called at probe and detach()
++ * can be called inside disconnect()
++ */
++static probe_cb_t	probe_cb = NULL;
++static disconnect_cb_t	disconnect_cb = NULL;
++static void		*probe_arg = NULL;
++static void		*disc_arg = NULL;
++static dbus_intf_t	*g_dbusintf = NULL;
++static dbus_intf_t	dbus_usb_intf; /** functions called by higher layer DBUS into lower layer */
++
++/*
++ * dbus_intf_t common to all USB
++ * These functions override dbus_usb_<os>.c.
++ */
++static void *dbus_usb_attach(dbus_pub_t *pub, void *cbarg, dbus_intf_callbacks_t *cbs);
++static void dbus_usb_detach(dbus_pub_t *pub, void *info);
++static void * dbus_usb_probe(void *arg, const char *desc, uint32 bustype,
++	uint16 bus_no, uint16 slot, uint32 hdrlen);
++
++/* functions */
++
++/**
++ * As part of DBUS initialization/registration, the higher level DBUS (dbus.c) needs to know what
++ * lower level DBUS functions to call (in both dbus_usb.c and dbus_usb_os.c).
++ */
++static void *
++dbus_usb_probe(void *arg, const char *desc, uint32 bustype, uint16 bus_no,
++	uint16 slot, uint32 hdrlen)
++{
++	DBUSTRACE(("%s(): \n", __FUNCTION__));
++	if (probe_cb) {
++
++		if (g_dbusintf != NULL) {
++			/* First, initialize all lower-level functions as default
++			 * so that dbus.c simply calls directly to dbus_usb_os.c.
++			 */
++			bcopy(g_dbusintf, &dbus_usb_intf, sizeof(dbus_intf_t));
++
++			/* Second, selectively override functions we need, if any. */
++			dbus_usb_intf.attach = dbus_usb_attach;
++			dbus_usb_intf.detach = dbus_usb_detach;
++			dbus_usb_intf.iovar_op = dbus_usb_iovar_op;
++			dbus_usb_intf.dlstart = dbus_usb_dlstart;
++			dbus_usb_intf.dlneeded = dbus_usb_dlneeded;
++			dbus_usb_intf.dlrun = dbus_usb_dlrun;
++		}
++
++		disc_arg = probe_cb(probe_arg, "DBUS USB", USB_BUS, bus_no, slot, hdrlen);
++		return disc_arg;
++	}
++
++	return NULL;
++}
++
++/**
++ * On return, *intf contains this or lower-level DBUS functions to be called by higher
++ * level (dbus.c)
++ */
++int
++dbus_bus_register(int vid, int pid, probe_cb_t prcb,
++	disconnect_cb_t discb, void *prarg, dbus_intf_t **intf, void *param1, void *param2)
++{
++	int err;
++
++	DBUSTRACE(("%s(): \n", __FUNCTION__));
++	probe_cb = prcb;
++	disconnect_cb = discb;
++	probe_arg = prarg;
++
++	*intf = &dbus_usb_intf;
++
++	err = dbus_bus_osl_register(vid, pid, dbus_usb_probe,
++		dbus_usb_disconnect, NULL, &g_dbusintf, param1, param2);
++
++	ASSERT(g_dbusintf);
++	return err;
++}
++
++int
++dbus_bus_deregister()
++{
++	DBUSTRACE(("%s(): \n", __FUNCTION__));
++	return dbus_bus_osl_deregister();
++}
++
++/** initialization consists of registration followed by 'attach'. */
++void *
++dbus_usb_attach(dbus_pub_t *pub, void *cbarg, dbus_intf_callbacks_t *cbs)
++{
++	usb_info_t *usb_info;
++
++	DBUSTRACE(("%s(): \n", __FUNCTION__));
++
++	if ((g_dbusintf == NULL) || (g_dbusintf->attach == NULL))
++		return NULL;
++
++	/* Sanity check for BUS_INFO() */
++	ASSERT(OFFSETOF(usb_info_t, pub) == 0);
++
++	usb_info = MALLOC(pub->osh, sizeof(usb_info_t));
++	if (usb_info == NULL)
++		return NULL;
++
++	bzero(usb_info, sizeof(usb_info_t));
++
++	usb_info->pub = pub;
++	usb_info->cbarg = cbarg;
++	usb_info->cbs = cbs;
++
++	usb_info->usbosl_info = (dbus_pub_t *)g_dbusintf->attach(pub,
++		usb_info, &dbus_usb_intf_cbs);
++	if (usb_info->usbosl_info == NULL) {
++		MFREE(pub->osh, usb_info, sizeof(usb_info_t));
++		return NULL;
++	}
++
++	/* Save USB OS-specific driver entry points */
++	usb_info->drvintf = g_dbusintf;
++
++	pub->bus = usb_info;
++#if !defined(BCM_REQUEST_FW)
++	if (!dbus_usb_resetcfg(usb_info)) {
++		usb_info->pub->busstate = DBUS_STATE_DL_DONE;
++	}
++#endif
++	/* Return Lower layer info */
++	return (void *) usb_info->usbosl_info;
++}
++
++void
++dbus_usb_detach(dbus_pub_t *pub, void *info)
++{
++	usb_info_t *usb_info = (usb_info_t *) pub->bus;
++	osl_t *osh = pub->osh;
++
++	if (usb_info == NULL)
++		return;
++
++	if (usb_info->drvintf && usb_info->drvintf->detach)
++		usb_info->drvintf->detach(pub, usb_info->usbosl_info);
++
++	MFREE(osh, usb_info, sizeof(usb_info_t));
++}
++
++void
++dbus_usb_disconnect(void *handle)
++{
++	DBUSTRACE(("%s(): \n", __FUNCTION__));
++	if (disconnect_cb)
++		disconnect_cb(disc_arg);
++}
++
++/**
++ * When the lower DBUS level (dbus_usb_os.c) signals this event, the higher DBUS level has to be
++ * notified.
++ */
++static void
++dbus_usb_send_irb_timeout(void *handle, dbus_irb_tx_t *txirb)
++{
++	usb_info_t *usb_info = (usb_info_t *) handle;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (usb_info == NULL)
++		return;
++
++	if (usb_info->cbs && usb_info->cbs->send_irb_timeout)
++		usb_info->cbs->send_irb_timeout(usb_info->cbarg, txirb);
++}
++
++/**
++ * When the lower DBUS level (dbus_usb_os.c) signals this event, the higher DBUS level has to be
++ * notified.
++ */
++static void
++dbus_usb_send_irb_complete(void *handle, dbus_irb_tx_t *txirb, int status)
++{
++	usb_info_t *usb_info = (usb_info_t *) handle;
++
++	if (usb_info == NULL)
++		return;
++
++	if (usb_info->cbs && usb_info->cbs->send_irb_complete)
++		usb_info->cbs->send_irb_complete(usb_info->cbarg, txirb, status);
++}
++
++/**
++ * When the lower DBUS level (dbus_usb_os.c) signals this event, the higher DBUS level has to be
++ * notified.
++ */
++static void
++dbus_usb_recv_irb_complete(void *handle, dbus_irb_rx_t *rxirb, int status)
++{
++	usb_info_t *usb_info = (usb_info_t *) handle;
++
++	if (usb_info == NULL)
++		return;
++
++	if (usb_info->cbs && usb_info->cbs->recv_irb_complete)
++		usb_info->cbs->recv_irb_complete(usb_info->cbarg, rxirb, status);
++}
++
++/** Lower DBUS level (dbus_usb_os.c) requests a free IRB. Pass this on to the higher DBUS level. */
++static struct dbus_irb*
++dbus_usb_getirb(void *handle, bool send)
++{
++	usb_info_t *usb_info = (usb_info_t *) handle;
++
++	if (usb_info == NULL)
++		return NULL;
++
++	if (usb_info->cbs && usb_info->cbs->getirb)
++		return usb_info->cbs->getirb(usb_info->cbarg, send);
++
++	return NULL;
++}
++
++/**
++ * When the lower DBUS level (dbus_usb_os.c) signals this event, the higher DBUS level has to be
++ * notified.
++ */
++static void
++dbus_usb_rxerr_indicate(void *handle, bool on)
++{
++	usb_info_t *usb_info = (usb_info_t *) handle;
++
++	if (usb_info == NULL)
++		return;
++
++	if (usb_info->cbs && usb_info->cbs->rxerr_indicate)
++		usb_info->cbs->rxerr_indicate(usb_info->cbarg, on);
++}
++
++/**
++ * When the lower DBUS level (dbus_usb_os.c) signals this event, the higher DBUS level has to be
++ * notified.
++ */
++static void
++dbus_usb_errhandler(void *handle, int err)
++{
++	usb_info_t *usb_info = (usb_info_t *) handle;
++
++	if (usb_info == NULL)
++		return;
++
++	if (usb_info->cbs && usb_info->cbs->errhandler)
++		usb_info->cbs->errhandler(usb_info->cbarg, err);
++}
++
++/**
++ * When the lower DBUS level (dbus_usb_os.c) signals this event, the higher DBUS level has to be
++ * notified.
++ */
++static void
++dbus_usb_ctl_complete(void *handle, int type, int status)
++{
++	usb_info_t *usb_info = (usb_info_t *) handle;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (usb_info == NULL) {
++		DBUSERR(("%s: usb_info is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (usb_info->cbs && usb_info->cbs->ctl_complete)
++		usb_info->cbs->ctl_complete(usb_info->cbarg, type, status);
++}
++
++/**
++ * When the lower DBUS level (dbus_usb_os.c) signals this event, the higher DBUS level has to be
++ * notified.
++ */
++static void
++dbus_usb_state_change(void *handle, int state)
++{
++	usb_info_t *usb_info = (usb_info_t *) handle;
++
++	if (usb_info == NULL)
++		return;
++
++	if (usb_info->cbs && usb_info->cbs->state_change)
++		usb_info->cbs->state_change(usb_info->cbarg, state);
++}
++
++/** called by higher DBUS level (dbus.c) */
++static int
++dbus_usb_iovar_op(void *bus, const char *name,
++	void *params, int plen, void *arg, int len, bool set)
++{
++	int err = DBUS_OK;
++
++	err = dbus_iovar_process((usb_info_t*)bus, name, params, plen, arg, len, set);
++	return err;
++}
++
++/** process iovar request from higher DBUS level */
++static int
++dbus_iovar_process(usb_info_t* usbinfo, const char *name,
++                 void *params, int plen, void *arg, int len, bool set)
++{
++	const bcm_iovar_t *vi = NULL;
++	int bcmerror = 0;
++	int val_size;
++	uint32 actionid;
++
++	DBUSTRACE(("%s: Enter\n", __FUNCTION__));
++
++	ASSERT(name);
++	ASSERT(len >= 0);
++
++	/* Get MUST have return space */
++	ASSERT(set || (arg && len));
++
++	/* Set does NOT take qualifiers */
++	ASSERT(!set || (!params && !plen));
++
++	/* Look up var locally; if not found pass to host driver */
++	if ((vi = bcm_iovar_lookup(dhdusb_iovars, name)) == NULL) {
++		/* Not Supported */
++		bcmerror = BCME_UNSUPPORTED;
++		DBUSTRACE(("%s: IOVAR %s is not supported\n", name, __FUNCTION__));
++		goto exit;
++
++	}
++
++	DBUSTRACE(("%s: %s %s, len %d plen %d\n", __FUNCTION__,
++	         name, (set ? "set" : "get"), len, plen));
++
++	/* set up 'params' pointer in case this is a set command so that
++	 * the convenience int and bool code can be common to set and get
++	 */
++	if (params == NULL) {
++		params = arg;
++		plen = len;
++	}
++
++	if (vi->type == IOVT_VOID)
++		val_size = 0;
++	else if (vi->type == IOVT_BUFFER)
++		val_size = len;
++	else
++		/* all other types are integer sized */
++		val_size = sizeof(int);
++
++	actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
++	bcmerror = dbus_usb_doiovar(usbinfo, vi, actionid,
++		name, params, plen, arg, len, val_size);
++
++exit:
++	return bcmerror;
++} /* dbus_iovar_process */
++
++static int
++dbus_usb_doiovar(usb_info_t *bus, const bcm_iovar_t *vi, uint32 actionid, const char *name,
++                void *params, int plen, void *arg, int len, int val_size)
++{
++	int bcmerror = 0;
++	int32 int_val = 0;
++	int32 int_val2 = 0;
++	bool bool_val = 0;
++
++	DBUSTRACE(("%s: Enter, action %d name %s params %p plen %d arg %p len %d val_size %d\n",
++	           __FUNCTION__, actionid, name, params, plen, arg, len, val_size));
++
++	if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid))) != 0)
++		goto exit;
++
++	if (plen >= (int)sizeof(int_val))
++		bcopy(params, &int_val, sizeof(int_val));
++
++	if (plen >= (int)sizeof(int_val) * 2)
++		bcopy((void*)((uintptr)params + sizeof(int_val)), &int_val2, sizeof(int_val2));
++
++	bool_val = (int_val != 0) ? TRUE : FALSE;
++
++	switch (actionid) {
++
++	case IOV_SVAL(IOV_MEMBYTES):
++	case IOV_GVAL(IOV_MEMBYTES):
++	{
++		uint32 address;
++		uint size, dsize;
++		uint8 *data;
++
++		bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
++
++		ASSERT(plen >= 2*sizeof(int));
++
++		address = (uint32)int_val;
++		BCM_REFERENCE(address);
++		bcopy((char *)params + sizeof(int_val), &int_val, sizeof(int_val));
++		size = (uint)int_val;
++
++		/* Do some validation */
++		dsize = set ? plen - (2 * sizeof(int)) : len;
++		if (dsize < size) {
++			DBUSTRACE(("%s: error on %s membytes, addr 0x%08x size %d dsize %d\n",
++			           __FUNCTION__, (set ? "set" : "get"), address, size, dsize));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		DBUSTRACE(("%s: Request to %s %d bytes at address 0x%08x\n", __FUNCTION__,
++		          (set ? "write" : "read"), size, address));
++
++		/* Generate the actual data pointer */
++		data = set ? (uint8*)params + 2 * sizeof(int): (uint8*)arg;
++
++		/* Call to do the transfer */
++		bcmerror = dbus_usb_dl_writeimage(BUS_INFO(bus, usb_info_t), data, size);
++	}
++		break;
++
++
++	case IOV_SVAL(IOV_SET_DOWNLOAD_STATE):
++
++		if (bool_val == TRUE) {
++			bcmerror = dbus_usb_dlneeded(bus);
++			dbus_usb_rdl_dwnld_state(BUS_INFO(bus, usb_info_t));
++		} else {
++			usb_info_t *usbinfo = BUS_INFO(bus, usb_info_t);
++			bcmerror = dbus_usb_dlrun(bus);
++			usbinfo->pub->busstate = DBUS_STATE_DL_DONE;
++		}
++		break;
++
++	case IOV_SVAL(IOV_VARS):
++		bcmerror = dhdusb_downloadvars(BUS_INFO(bus, usb_info_t), arg, len);
++		break;
++
++	case IOV_GVAL(IOV_DBUS_MSGLEVEL):
++		int_val = (int32)dbus_msglevel;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DBUS_MSGLEVEL):
++		dbus_msglevel = int_val;
++		break;
++
++#ifdef DBUS_USB_LOOPBACK
++	case IOV_SVAL(IOV_LOOPBACK_TX):
++			bcmerror = dbus_usbos_loopback_tx(BUS_INFO(bus, usb_info_t), int_val,
++			  int_val2);
++			break;
++#endif
++	default:
++		bcmerror = BCME_UNSUPPORTED;
++		break;
++	}
++
++exit:
++	return bcmerror;
++} /* dbus_usb_doiovar */
++
++/** higher DBUS level (dbus.c) wants to set NVRAM variables in dongle */
++static int
++dhdusb_downloadvars(usb_info_t *bus, void *arg, int len)
++{
++	int bcmerror = 0;
++	uint32 varsize;
++	uint32 varaddr;
++	uint32 varsizew;
++
++	if (!len) {
++		bcmerror = BCME_BUFTOOSHORT;
++		goto err;
++	}
++
++	/* RAM size is not set. Set it at dbus_usb_dlneeded */
++	if (!bus->rdlram_size)
++		bcmerror = BCME_ERROR;
++
++	/* Even if there are no vars are to be written, we still need to set the ramsize. */
++	varsize = len ? ROUNDUP(len, 4) : 0;
++	varaddr = (bus->rdlram_size - 4) - varsize;
++
++	/* Write the vars list */
++	DBUSTRACE(("WriteVars: @%x varsize=%d\n", varaddr, varsize));
++	bcmerror = dbus_write_membytes(bus->usbosl_info, TRUE, (varaddr + bus->rdlram_base_addr),
++		arg, varsize);
++
++	/* adjust to the user specified RAM */
++	DBUSTRACE(("Usable memory size: %d\n", bus->rdlram_size));
++	DBUSTRACE(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
++
++	varsize = ((bus->rdlram_size - 4) - varaddr);
++
++	/*
++	 * Determine the length token:
++	 * Varsize, converted to words, in lower 16-bits, checksum in upper 16-bits.
++	 */
++	if (bcmerror) {
++		varsizew = 0;
++	} else {
++		varsizew = varsize / 4;
++		varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
++		varsizew = htol32(varsizew);
++	}
++
++	DBUSTRACE(("New varsize is %d, length token=0x%08x\n", varsize, varsizew));
++
++	/* Write the length token to the last word */
++	bcmerror = dbus_write_membytes(bus->usbosl_info, TRUE, ((bus->rdlram_size - 4) +
++		bus->rdlram_base_addr), (uint8*)&varsizew, 4);
++err:
++	return bcmerror;
++} /* dbus_usb_doiovar */
++
++#if !defined(BCM_REQUEST_FW)
++/**
++ * After downloading firmware into dongle and starting it, we need to know if the firmware is
++ * indeed up and running.
++ */
++static int
++dbus_usb_resetcfg(usb_info_t *usbinfo)
++{
++	void *osinfo;
++	bootrom_id_t id;
++	uint16 waittime = 0;
++
++	uint32 starttime = 0;
++	uint32 endtime = 0;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (usbinfo == NULL)
++		return DBUS_ERR;
++
++	osinfo = usbinfo->usbosl_info;
++	ASSERT(osinfo);
++
++	/* Give dongle chance to boot */
++	dbus_usbos_wait(osinfo, USB_SFLASH_DLIMAGE_SPINWAIT);
++	waittime = USB_SFLASH_DLIMAGE_SPINWAIT;
++	while (waittime < USB_DLIMAGE_RETRY_TIMEOUT) {
++
++		starttime = OSL_SYSUPTIME();
++
++		id.chip = 0xDEAD;       /* Get the ID */
++		dbus_usbos_dl_cmd(osinfo, DL_GETVER, &id, sizeof(bootrom_id_t));
++		id.chip = ltoh32(id.chip);
++
++		endtime = OSL_SYSUPTIME();
++		waittime += (endtime - starttime);
++
++		if (id.chip == POSTBOOT_ID)
++			break;
++	}
++
++	if (id.chip == POSTBOOT_ID) {
++		DBUSERR(("%s: download done. Bootup time = %d ms postboot chip 0x%x/rev 0x%x\n",
++			__FUNCTION__, waittime, id.chip, id.chiprev));
++
++		dbus_usbos_dl_cmd(osinfo, DL_RESETCFG, &id, sizeof(bootrom_id_t));
++
++		dbus_usbos_wait(osinfo, USB_RESETCFG_SPINWAIT);
++		return DBUS_OK;
++	} else {
++		DBUSERR(("%s: Cannot talk to Dongle. Wait time = %d ms. Firmware is not UP \n",
++			__FUNCTION__, waittime));
++		return DBUS_ERR;
++	}
++
++	return DBUS_OK;
++}
++#endif
++
++/** before firmware download, the dongle has to be prepared to receive the fw image */
++static int
++dbus_usb_rdl_dwnld_state(usb_info_t *usbinfo)
++{
++	void *osinfo = usbinfo->usbosl_info;
++	rdl_state_t state;
++	int err = DBUS_OK;
++
++	/* 1) Prepare USB boot loader for runtime image */
++	dbus_usbos_dl_cmd(osinfo, DL_START, &state, sizeof(rdl_state_t));
++
++	state.state = ltoh32(state.state);
++	state.bytes = ltoh32(state.bytes);
++
++	/* 2) Check we are in the Waiting state */
++	if (state.state != DL_WAITING) {
++		DBUSERR(("%s: Failed to DL_START\n", __FUNCTION__));
++		err = DBUS_ERR;
++		goto fail;
++	}
++
++fail:
++	return err;
++}
++
++/**
++ * Dongle contains bootcode in ROM but firmware is (partially) contained in dongle RAM. Therefore,
++ * firmware has to be downloaded into dongle RAM.
++ */
++static int
++dbus_usb_dl_writeimage(usb_info_t *usbinfo, uint8 *fw, int fwlen)
++{
++	osl_t *osh = usbinfo->pub->osh;
++	void *osinfo = usbinfo->usbosl_info;
++	unsigned int sendlen, sent, dllen;
++	char *bulkchunk = NULL, *dlpos;
++	rdl_state_t state;
++	int err = DBUS_OK;
++	bootrom_id_t id;
++	uint16 wait, wait_time;
++	uint32 dl_trunk_size = RDL_CHUNK;
++
++	if (BCM4350_CHIP(usbinfo->pub->attrib.devid))
++		dl_trunk_size = RDL_CHUNK_MAX;
++
++	while (!bulkchunk) {
++		bulkchunk = MALLOC(osh, dl_trunk_size);
++		if (dl_trunk_size == RDL_CHUNK)
++			break;
++		if (!bulkchunk) {
++			dl_trunk_size /= 2;
++			if (dl_trunk_size < RDL_CHUNK)
++				dl_trunk_size = RDL_CHUNK;
++		}
++	}
++
++	if (bulkchunk == NULL) {
++		err = DBUS_ERR;
++		goto fail;
++	}
++
++	sent = 0;
++	dlpos = fw;
++	dllen = fwlen;
++
++	/* Get chip id and rev */
++	id.chip = usbinfo->pub->attrib.devid;
++	id.chiprev = usbinfo->pub->attrib.chiprev;
++
++	DBUSTRACE(("enter %s: fwlen=%d\n", __FUNCTION__, fwlen));
++
++	dbus_usbos_dl_cmd(osinfo, DL_GETSTATE, &state, sizeof(rdl_state_t));
++
++	/* 3) Load the image */
++	while ((sent < dllen)) {
++		/* Wait until the usb device reports it received all the bytes we sent */
++
++		if (sent < dllen) {
++			if ((dllen-sent) < dl_trunk_size)
++				sendlen = dllen-sent;
++			else
++				sendlen = dl_trunk_size;
++
++			/* simply avoid having to send a ZLP by ensuring we never have an even
++			 * multiple of 64
++			 */
++			if (!(sendlen % 64))
++				sendlen -= 4;
++
++			/* send data */
++			memcpy(bulkchunk, dlpos, sendlen);
++			if (!dbus_usbos_dl_send_bulk(osinfo, bulkchunk, sendlen)) {
++				err = DBUS_ERR;
++				goto fail;
++			}
++
++			dlpos += sendlen;
++			sent += sendlen;
++			DBUSTRACE(("%s: sendlen %d\n", __FUNCTION__, sendlen));
++		}
++
++		wait = 0;
++		wait_time = USB_SFLASH_DLIMAGE_SPINWAIT;
++		while (!dbus_usbos_dl_cmd(osinfo, DL_GETSTATE, &state,
++			sizeof(rdl_state_t))) {
++			if ((id.chip == 43236) && (id.chiprev == 0)) {
++				DBUSERR(("%s: 43236a0 SFlash delay, waiting for dongle crc check "
++					 "completion!!!\n", __FUNCTION__));
++				dbus_usbos_wait(osinfo, wait_time);
++				wait += wait_time;
++				if (wait >= USB_SFLASH_DLIMAGE_LIMIT) {
++					DBUSERR(("%s: DL_GETSTATE Failed xxxx\n", __FUNCTION__));
++					err = DBUS_ERR;
++					goto fail;
++					break;
++				}
++			} else {
++				DBUSERR(("%s: DL_GETSTATE Failed xxxx\n", __FUNCTION__));
++				err = DBUS_ERR;
++				goto fail;
++			}
++		}
++
++		state.state = ltoh32(state.state);
++		state.bytes = ltoh32(state.bytes);
++
++		/* restart if an error is reported */
++		if ((state.state == DL_BAD_HDR) || (state.state == DL_BAD_CRC)) {
++			DBUSERR(("%s: Bad Hdr or Bad CRC\n", __FUNCTION__));
++			err = DBUS_ERR;
++			goto fail;
++		}
++
++	}
++fail:
++	if (bulkchunk)
++		MFREE(osh, bulkchunk, dl_trunk_size);
++
++	return err;
++} /* dbus_usb_dl_writeimage */
++
++/** Higher level DBUS layer (dbus.c) requests this layer to download image into dongle */
++static int
++dbus_usb_dlstart(void *bus, uint8 *fw, int len)
++{
++	usb_info_t *usbinfo = BUS_INFO(bus, usb_info_t);
++	int err;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (usbinfo == NULL)
++		return DBUS_ERR;
++
++	if (USB_DEV_ISBAD(usbinfo))
++		return DBUS_ERR;
++
++	err = dbus_usb_rdl_dwnld_state(usbinfo);
++
++	if (DBUS_OK == err) {
++		err = dbus_usb_dl_writeimage(usbinfo, fw, len);
++		if (err == DBUS_OK)
++			usbinfo->pub->busstate = DBUS_STATE_DL_DONE;
++		else
++			usbinfo->pub->busstate = DBUS_STATE_DL_PENDING;
++	} else
++		usbinfo->pub->busstate = DBUS_STATE_DL_PENDING;
++
++	return err;
++}
++
++static bool
++dbus_usb_update_chipinfo(usb_info_t *usbinfo, uint32 chip)
++{
++	bool retval = TRUE;
++	/* based on the CHIP Id, store the ram size which is needed for NVRAM download. */
++	switch (chip) {
++
++		case 0x4319:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_4319;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_4319;
++			break;
++
++		case 0x4329:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_4329;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_4329;
++			break;
++
++		case 43234:
++		case 43235:
++		case 43236:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_43236;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_43236;
++			break;
++
++		case 0x4328:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_4328;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_4328;
++			break;
++
++		case 0x4322:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_4322;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_4322;
++			break;
++
++		case 0x4360:
++		case 0xAA06:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_4360;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_4360;
++			break;
++
++		case 43242:
++		case 43243:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_43242;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_43242;
++			break;
++
++		case 43143:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_43143;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_43143;
++			break;
++
++		case 0x4350:
++		case 43556:
++		case 43558:
++		case 43569:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_4350;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_4350;
++			break;
++
++		case POSTBOOT_ID:
++			break;
++
++		default:
++			DBUSERR(("%s: Chip 0x%x Ram size is not known\n", __FUNCTION__, chip));
++			retval = FALSE;
++			break;
++
++	}
++
++	return retval;
++} /* dbus_usb_update_chipinfo */
++
++/** higher DBUS level (dbus.c) wants to know if firmware download is required. */
++static int
++dbus_usb_dlneeded(void *bus)
++{
++	usb_info_t *usbinfo = BUS_INFO(bus, usb_info_t);
++	void *osinfo;
++	bootrom_id_t id;
++	int dl_needed = 1;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (usbinfo == NULL)
++		return DBUS_ERR;
++
++	osinfo = usbinfo->usbosl_info;
++	ASSERT(osinfo);
++
++	/* Check if firmware downloaded already by querying runtime ID */
++	id.chip = 0xDEAD;
++	dbus_usbos_dl_cmd(osinfo, DL_GETVER, &id, sizeof(bootrom_id_t));
++
++	id.chip = ltoh32(id.chip);
++	id.chiprev = ltoh32(id.chiprev);
++
++	if (FALSE == dbus_usb_update_chipinfo(usbinfo, id.chip)) {
++		dl_needed = DBUS_ERR;
++		goto exit;
++	}
++
++	DBUSERR(("%s: chip 0x%x rev 0x%x\n", __FUNCTION__, id.chip, id.chiprev));
++	if (id.chip == POSTBOOT_ID) {
++		/* This code is  needed to support two enumerations on USB1.1 scenario */
++		DBUSERR(("%s: Firmware already downloaded\n", __FUNCTION__));
++
++		dbus_usbos_dl_cmd(osinfo, DL_RESETCFG, &id, sizeof(bootrom_id_t));
++		dl_needed = DBUS_OK;
++		if (usbinfo->pub->busstate == DBUS_STATE_DL_PENDING)
++			usbinfo->pub->busstate = DBUS_STATE_DL_DONE;
++	} else {
++		usbinfo->pub->attrib.devid = id.chip;
++		usbinfo->pub->attrib.chiprev = id.chiprev;
++	}
++
++exit:
++	return dl_needed;
++}
++
++/** After issuing firmware download, higher DBUS level (dbus.c) wants to start the firmware. */
++static int
++dbus_usb_dlrun(void *bus)
++{
++	usb_info_t *usbinfo = BUS_INFO(bus, usb_info_t);
++	void *osinfo;
++	rdl_state_t state;
++	int err = DBUS_OK;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (usbinfo == NULL)
++		return DBUS_ERR;
++
++	if (USB_DEV_ISBAD(usbinfo))
++		return DBUS_ERR;
++
++	osinfo = usbinfo->usbosl_info;
++	ASSERT(osinfo);
++
++	/* Check we are runnable */
++	dbus_usbos_dl_cmd(osinfo, DL_GETSTATE, &state, sizeof(rdl_state_t));
++
++	state.state = ltoh32(state.state);
++	state.bytes = ltoh32(state.bytes);
++
++	/* Start the image */
++	if (state.state == DL_RUNNABLE) {
++		DBUSTRACE(("%s: Issue DL_GO\n", __FUNCTION__));
++		dbus_usbos_dl_cmd(osinfo, DL_GO, &state, sizeof(rdl_state_t));
++
++		if (usbinfo->pub->attrib.devid == TEST_CHIP)
++			dbus_usbos_wait(osinfo, USB_DLGO_SPINWAIT);
++
++//		dbus_usb_resetcfg(usbinfo);
++		/* The Donlge may go for re-enumeration. */
++	} else {
++		DBUSERR(("%s: Dongle not runnable\n", __FUNCTION__));
++		err = DBUS_ERR;
++	}
++
++	return err;
++}
++
++/**
++ * As preparation for firmware download, higher DBUS level (dbus.c) requests the firmware image
++ * to be used for the type of dongle detected. Directly called by dbus.c (so not via a callback
++ * construction)
++ */
++void
++dbus_bus_fw_get(void *bus, uint8 **fw, int *fwlen, int *decomp)
++{
++	usb_info_t *usbinfo = BUS_INFO(bus, usb_info_t);
++	unsigned int devid;
++	unsigned int crev;
++
++	devid = usbinfo->pub->attrib.devid;
++	crev = usbinfo->pub->attrib.chiprev;
++
++	*fw = NULL;
++	*fwlen = 0;
++
++	switch (devid) {
++	case BCM43236_CHIP_ID:
++	case BCM43235_CHIP_ID:
++	case BCM43234_CHIP_ID:
++	case BCM43238_CHIP_ID: {
++		if (crev == 3 || crev == 2 || crev == 1) {
++#ifdef EMBED_IMAGE_43236b
++			*fw = (uint8 *)dlarray_43236b;
++			*fwlen = sizeof(dlarray_43236b);
++
++#endif
++		}
++		} break;
++	case BCM4360_CHIP_ID:
++	case BCM4352_CHIP_ID:
++	case BCM43526_CHIP_ID:
++#ifdef EMBED_IMAGE_43526a
++		if (crev <= 2) {
++			*fw = (uint8 *)dlarray_43526a;
++			*fwlen = sizeof(dlarray_43526a);
++		}
++#endif
++#ifdef EMBED_IMAGE_43526b
++		if (crev > 2) {
++			*fw = (uint8 *)dlarray_43526b;
++			*fwlen = sizeof(dlarray_43526b);
++		}
++#endif
++		break;
++
++	case BCM43242_CHIP_ID:
++#ifdef EMBED_IMAGE_43242a0
++		*fw = (uint8 *)dlarray_43242a0;
++		*fwlen = sizeof(dlarray_43242a0);
++#endif
++		break;
++
++	case BCM43143_CHIP_ID:
++#ifdef EMBED_IMAGE_43143a0
++		*fw = (uint8 *)dlarray_43143a0;
++		*fwlen = sizeof(dlarray_43143a0);
++#endif
++#ifdef EMBED_IMAGE_43143b0
++		*fw = (uint8 *)dlarray_43143b0;
++		*fwlen = sizeof(dlarray_43143b0);
++#endif
++		break;
++
++	case BCM4350_CHIP_ID:
++	case BCM4354_CHIP_ID:
++	case BCM43556_CHIP_ID:
++	case BCM43558_CHIP_ID:
++	case BCM43566_CHIP_ID:
++	case BCM43568_CHIP_ID:
++	case BCM43570_CHIP_ID:
++	case BCM4358_CHIP_ID:
++#ifdef EMBED_IMAGE_4350a0
++		if (crev == 0) {
++			*fw = (uint8 *)dlarray_4350a0;
++			*fwlen = sizeof(dlarray_4350a0);
++		}
++#endif
++#ifdef EMBED_IMAGE_4350b0
++		if (crev == 1) {
++			*fw = (uint8 *)dlarray_4350b0;
++			*fwlen = sizeof(dlarray_4350b0);
++		}
++#endif
++#ifdef EMBED_IMAGE_4350b1
++		if (crev == 2) {
++			*fw = (uint8 *)dlarray_4350b1;
++			*fwlen = sizeof(dlarray_4350b1);
++		}
++#endif
++#ifdef EMBED_IMAGE_43556b1
++		if (crev == 2) {
++			*fw = (uint8 *)dlarray_43556b1;
++			*fwlen = sizeof(dlarray_43556b1);
++		}
++#endif
++#ifdef EMBED_IMAGE_4350c0
++		if (crev == 3) {
++			*fw = (uint8 *)dlarray_4350c0;
++			*fwlen = sizeof(dlarray_4350c0);
++		}
++#endif /* EMBED_IMAGE_4350c0 */
++#ifdef EMBED_IMAGE_4350c1
++		if (crev == 4) {
++			*fw = (uint8 *)dlarray_4350c1;
++			*fwlen = sizeof(dlarray_4350c1);
++		}
++#endif /* EMBED_IMAGE_4350c1 */
++		break;
++	case BCM43569_CHIP_ID:
++#ifdef EMBED_IMAGE_43569a0
++		if (crev == 0) {
++			*fw = (uint8 *)dlarray_43569a0;
++			*fwlen = sizeof(dlarray_43569a0);
++		}
++#endif /* EMBED_IMAGE_43569a0 */
++		break;
++	default:
++#ifdef EMBED_IMAGE_GENERIC
++		*fw = (uint8 *)dlarray;
++		*fwlen = sizeof(dlarray);
++#endif
++		break;
++	}
++} /* dbus_bus_fw_get */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dbus_usb_linux.c b/module_drivers/drivers/net/wireless/bcmdhd/dbus_usb_linux.c
+new file mode 100644
+index 000000000..10927d894
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dbus_usb_linux.c
+@@ -0,0 +1,3403 @@
++/*
++ * Dongle BUS interface
++ * USB Linux Implementation
++ *
++ * Copyright (C) 1999-2016, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dbus_usb_linux.c 564663 2015-06-18 02:34:42Z $
++ */
++
++/**
++ * @file @brief
++ * This file contains DBUS code that is USB *and* OS (Linux) specific. DBUS is a Broadcom
++ * proprietary host specific abstraction layer.
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++
++/**
++ * DBUS_LINUX_RXDPC is created for router platform performance tuning. A separate thread is created
++ * to handle USB RX and avoid the call chain getting too long and enhance cache hit rate.
++ *
++ * DBUS_LINUX_RXDPC setting is in wlconfig file.
++ */
++
++/*
++ * If DBUS_LINUX_RXDPC is off, spin_lock_bh() for CTFPOOL in
++ * linux_osl.c has to be changed to spin_lock_irqsave() because
++ * PKTGET/PKTFREE are no longer in bottom half.
++ *
++ * Right now we have another queue rpcq in wl_linux.c. Maybe we
++ * can eliminate that one to reduce the overhead.
++ *
++ * Enabling 2nd EP and DBUS_LINUX_RXDPC causing traffic from
++ * both EP's to be queued in the same rx queue. If we want
++ * RXDPC to work with 2nd EP. The EP for RPC call return
++ * should bypass the dpc and go directly up.
++ */
++
++/* #define DBUS_LINUX_RXDPC */
++
++/* Dbus histogram for ntxq, nrxq, dpc parameter tuning */
++/* #define DBUS_LINUX_HIST */
++
++#include <usbrdl.h>
++#include <bcmendian.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/usb.h>
++#include <linux/skbuff.h>
++#include <linux/netdevice.h>
++#include <linux/random.h>
++#include <linux/spinlock.h>
++#include <linux/list.h>
++#include <asm/uaccess.h>
++#include <asm/unaligned.h>
++#include <dbus.h>
++#include <bcmutils.h>
++#include <bcmdevs.h>
++#include <linux/usb.h>
++#include <usbrdl.h>
++#include <linux/firmware.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++
++#if defined(USBOS_THREAD) || defined(USBOS_TX_THREAD)
++
++/**
++ * The usb-thread is designed to provide currency on multiprocessors and SMP linux kernels. On the
++ * dual cores platform, the WLAN driver, without threads, executed only on CPU0. The driver consumed
++ * almost of 100% on CPU0, while CPU1 remained idle. The behavior was observed on Broadcom's STB.
++ *
++ * The WLAN driver consumed most of CPU0 and not CPU1 because tasklets/queues, software irq, and
++ * hardware irq are executing from CPU0, only. CPU0 became the system's bottle-neck. TPUT is lower
++ * and system's responsiveness is slower.
++ *
++ * To improve system responsiveness and TPUT usb-thread was implemented. The system's threads could
++ * be scheduled to run on any core. One core could be processing data in the usb-layer and the other
++ * core could be processing data in the wl-layer.
++ *
++ * For further info see [WlThreadAndUsbThread] Twiki.
++ */
++
++#include <linux/kthread.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <asm/hardirq.h>
++#include <linux/list.h>
++#include <linux_osl.h>
++#endif /* USBOS_THREAD || USBOS_TX_THREAD */
++
++
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++#define KERNEL26
++#endif
++
++/**
++ * Starting with the 3.10 kernel release, dynamic PM support for USB is present whenever
++ * the kernel was built with CONFIG_PM_RUNTIME enabled. The CONFIG_USB_SUSPEND option has
++ * been eliminated.
++ */
++#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) && defined(CONFIG_USB_SUSPEND)) \
++	|| ((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) && defined(CONFIG_PM_RUNTIME))
++/* For USB power management support, see Linux kernel: Documentation/usb/power-management.txt */
++#define USB_SUSPEND_AVAILABLE
++#endif
++
++/* Define alternate fw/nvram paths used in Android */
++#ifdef OEM_ANDROID
++#define CONFIG_ANDROID_BCMDHD_FW_PATH "broadcom/dhd/firmware/fw.bin.trx"
++#define CONFIG_ANDROID_BCMDHD_NVRAM_PATH "broadcom/dhd/nvrams/nvm.txt"
++#endif /* OEM_ANDROID */
++
++static inline int usb_submit_urb_linux(struct urb *urb)
++{
++
++#ifdef BCM_MAX_URB_LEN
++	if (urb && (urb->transfer_buffer_length > BCM_MAX_URB_LEN)) {
++		DBUSERR(("URB transfer length=%d exceeded %d ra=%p\n", urb->transfer_buffer_length,
++		BCM_MAX_URB_LEN, __builtin_return_address(0)));
++		return DBUS_ERR;
++	}
++#endif
++
++#ifdef KERNEL26
++	return usb_submit_urb(urb, GFP_ATOMIC);
++#else
++	return usb_submit_urb(urb);
++#endif
++
++}
++
++#define USB_SUBMIT_URB(urb) usb_submit_urb_linux(urb)
++
++#ifdef KERNEL26
++
++#define USB_ALLOC_URB()				usb_alloc_urb(0, GFP_ATOMIC)
++#define USB_UNLINK_URB(urb)			(usb_kill_urb(urb))
++#define USB_FREE_URB(urb)			(usb_free_urb(urb))
++#define USB_REGISTER()				usb_register(&dbus_usbdev)
++#define USB_DEREGISTER()			usb_deregister(&dbus_usbdev)
++
++#ifdef USB_SUSPEND_AVAILABLE
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33))
++#define USB_AUTOPM_SET_INTERFACE(intf)		usb_autopm_set_interface(intf)
++#else
++#define USB_ENABLE_AUTOSUSPEND(udev)		usb_enable_autosuspend(udev)
++#define USB_DISABLE_AUTOSUSPEND(udev)       usb_disable_autosuspend(udev)
++#endif  /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33))  */
++
++#define USB_AUTOPM_GET_INTERFACE(intf)		usb_autopm_get_interface(intf)
++#define USB_AUTOPM_PUT_INTERFACE(intf)		usb_autopm_put_interface(intf)
++#define USB_AUTOPM_GET_INTERFACE_ASYNC(intf)	usb_autopm_get_interface_async(intf)
++#define USB_AUTOPM_PUT_INTERFACE_ASYNC(intf)	usb_autopm_put_interface_async(intf)
++#define USB_MARK_LAST_BUSY(dev)			usb_mark_last_busy(dev)
++
++#else /* USB_SUSPEND_AVAILABLE */
++
++#define USB_AUTOPM_GET_INTERFACE(intf)		do {} while (0)
++#define USB_AUTOPM_PUT_INTERFACE(intf)		do {} while (0)
++#define USB_AUTOPM_GET_INTERFACE_ASYNC(intf)	do {} while (0)
++#define USB_AUTOPM_PUT_INTERFACE_ASYNC(intf)	do {} while (0)
++#define USB_MARK_LAST_BUSY(dev)			do {} while (0)
++#endif /* USB_SUSPEND_AVAILABLE */
++
++#define USB_CONTROL_MSG(dev, pipe, request, requesttype, value, index, data, size, timeout) \
++	usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), \
++	(data), (size), (timeout))
++#define USB_BULK_MSG(dev, pipe, data, len, actual_length, timeout) \
++	usb_bulk_msg((dev), (pipe), (data), (len), (actual_length), (timeout))
++#define USB_BUFFER_ALLOC(dev, size, mem, dma)	usb_buffer_alloc(dev, size, mem, dma)
++#define USB_BUFFER_FREE(dev, size, data, dma)	usb_buffer_free(dev, size, data, dma)
++
++#ifdef WL_URB_ZPKT
++#define URB_QUEUE_BULK   URB_ZERO_PACKET
++#else
++#define URB_QUEUE_BULK   0
++#endif /* WL_URB_ZPKT */
++
++#define CALLBACK_ARGS		struct urb *urb, struct pt_regs *regs
++#define CALLBACK_ARGS_DATA	urb, regs
++#define CONFIGDESC(usb)		(&((usb)->actconfig)->desc)
++#define IFPTR(usb, idx)		((usb)->actconfig->interface[idx])
++#define IFALTS(usb, idx)	(IFPTR((usb), (idx))->altsetting[0])
++#define IFDESC(usb, idx)	IFALTS((usb), (idx)).desc
++#define IFEPDESC(usb, idx, ep)	(IFALTS((usb), (idx)).endpoint[ep]).desc
++
++#else /* KERNEL26 */
++
++#define USB_ALLOC_URB()				usb_alloc_urb(0)
++#define USB_UNLINK_URB(urb)			usb_unlink_urb(urb)
++#define USB_FREE_URB(urb)			(usb_free_urb(urb))
++#define USB_REGISTER()				usb_register(&dbus_usbdev)
++#define USB_DEREGISTER()			usb_deregister(&dbus_usbdev)
++#define USB_AUTOPM_GET_INTERFACE(intf)		do {} while (0)
++#define USB_AUTOPM_GET_INTERFACE_ASYNC(intf)	do {} while (0)
++#define USB_AUTOPM_PUT_INTERFACE_ASYNC(intf)	do {} while (0)
++#define USB_MARK_LAST_BUSY(dev)			do {} while (0)
++
++#define USB_CONTROL_MSG(dev, pipe, request, requesttype, value, index, data, size, timeout) \
++	usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), \
++	(data), (size), (timeout))
++#define USB_BUFFER_ALLOC(dev, size, mem, dma)  kmalloc(size, mem)
++#define USB_BUFFER_FREE(dev, size, data, dma)  kfree(data)
++
++#ifdef WL_URB_ZPKT
++#define URB_QUEUE_BULK   USB_QUEUE_BULK|URB_ZERO_PACKET
++#else
++#define URB_QUEUE_BULK   0
++#endif /*  WL_URB_ZPKT */
++
++#define CALLBACK_ARGS		struct urb *urb
++#define CALLBACK_ARGS_DATA	urb
++#define CONFIGDESC(usb)		((usb)->actconfig)
++#define IFPTR(usb, idx)		(&(usb)->actconfig->interface[idx])
++#define IFALTS(usb, idx)	((usb)->actconfig->interface[idx].altsetting[0])
++#define IFDESC(usb, idx)	IFALTS((usb), (idx))
++#define IFEPDESC(usb, idx, ep)	(IFALTS((usb), (idx)).endpoint[ep])
++
++
++#endif /* KERNEL26 */
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31))
++#define USB_SPEED_SUPER		5
++#endif  /* #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31)) */
++
++#define CONTROL_IF   0
++#define BULK_IF      0
++
++#ifdef BCMUSBDEV_COMPOSITE
++#define USB_COMPIF_MAX       4
++
++#define USB_CLASS_WIRELESS	0xe0
++#define USB_CLASS_MISC		0xef
++#define USB_SUBCLASS_COMMON	0x02
++#define USB_PROTO_IAD		0x01
++#define USB_PROTO_VENDOR	0xff
++
++#define USB_QUIRK_NO_SET_INTF   0x04 /* device does not support set_interface */
++#endif /* BCMUSBDEV_COMPOSITE */
++
++#define USB_SYNC_WAIT_TIMEOUT  300  /* ms */
++
++/* Private data kept in skb */
++#define SKB_PRIV(skb, idx)  (&((void **)skb->cb)[idx])
++#define SKB_PRIV_URB(skb)   (*(struct urb **)SKB_PRIV(skb, 0))
++
++#ifndef DBUS_USB_RXQUEUE_BATCH_ADD
++/* items to add each time within limit */
++#define DBUS_USB_RXQUEUE_BATCH_ADD            8
++#endif
++
++#ifndef DBUS_USB_RXQUEUE_LOWER_WATERMARK
++/* add a new batch req to rx queue when waiting item count reduce to this number */
++#define DBUS_USB_RXQUEUE_LOWER_WATERMARK      4
++#endif
++
++enum usbos_suspend_state {
++	USBOS_SUSPEND_STATE_DEVICE_ACTIVE = 0, /* Device is busy, won't allow suspend */
++	USBOS_SUSPEND_STATE_SUSPEND_PENDING,   /* Device is idle, can be suspended */
++	                                       /* Wating PM to suspend */
++	USBOS_SUSPEND_STATE_SUSPENDED          /* Device suspended */
++};
++
++enum usbos_request_state {
++	USBOS_REQUEST_STATE_UNSCHEDULED = 0,	/* USB TX request not scheduled */
++	USBOS_REQUEST_STATE_SCHEDULED,		/* USB TX request given to TX thread */
++	USBOS_REQUEST_STATE_SUBMITTED		/* USB TX request submitted */
++};
++
++typedef struct {
++	uint32 notification;
++	uint32 reserved;
++} intr_t;
++
++typedef struct {
++	dbus_pub_t *pub;
++
++	void *cbarg;
++	dbus_intf_callbacks_t *cbs;
++
++	/* Imported */
++	struct usb_device *usb;	/* USB device pointer from OS */
++	struct urb *intr_urb; /* URB for interrupt endpoint */
++	struct list_head req_rxfreeq;
++	struct list_head req_txfreeq;
++	struct list_head req_rxpostedq;	/* Posted down to USB driver for RX */
++	struct list_head req_txpostedq;	/* Posted down to USB driver for TX */
++	spinlock_t rxfree_lock; /* Lock for rx free list */
++	spinlock_t txfree_lock; /* Lock for tx free list */
++	spinlock_t rxposted_lock; /* Lock for rx posted list */
++	spinlock_t txposted_lock; /* Lock for tx posted list */
++	uint rx_pipe, tx_pipe, intr_pipe, rx_pipe2; /* Pipe numbers for USB I/O */
++	uint rxbuf_len;
++
++	struct list_head req_rxpendingq; /* RXDPC: Pending for dpc to send up */
++	spinlock_t rxpending_lock;	/* RXDPC: Lock for rx pending list */
++	long dpc_pid;
++	struct semaphore dpc_sem;
++	struct completion dpc_exited;
++	int rxpending;
++
++	struct urb               *ctl_urb;
++	int                      ctl_in_pipe, ctl_out_pipe;
++	struct usb_ctrlrequest   ctl_write;
++	struct usb_ctrlrequest   ctl_read;
++	struct semaphore         ctl_lock;     /* Lock for CTRL transfers via tx_thread */
++#ifdef USBOS_TX_THREAD
++	enum usbos_request_state ctl_state;
++#endif /* USBOS_TX_THREAD */
++
++	spinlock_t rxlock;      /* Lock for rxq management */
++	spinlock_t txlock;      /* Lock for txq management */
++
++	int intr_size;          /* Size of interrupt message */
++	int interval;           /* Interrupt polling interval */
++	intr_t intr;            /* Data buffer for interrupt endpoint */
++
++	int maxps;
++	atomic_t txposted;
++	atomic_t rxposted;
++	atomic_t txallocated;
++	atomic_t rxallocated;
++	bool rxctl_deferrespok;	/* Get a response for setup from dongle */
++
++	wait_queue_head_t wait;
++	bool waitdone;
++	int sync_urb_status;
++
++	struct urb *blk_urb; /* Used for downloading embedded image */
++
++#ifdef USBOS_THREAD
++	spinlock_t              ctrl_lock;
++	spinlock_t              usbos_list_lock;
++	struct list_head        usbos_list;
++	struct list_head        usbos_free_list;
++	atomic_t                usbos_list_cnt;
++	wait_queue_head_t       usbos_queue_head;
++	struct task_struct      *usbos_kt;
++#endif /* USBOS_THREAD */
++
++#ifdef USBOS_TX_THREAD
++	spinlock_t              usbos_tx_list_lock;
++	struct list_head	usbos_tx_list;
++	wait_queue_head_t	usbos_tx_queue_head;
++	struct task_struct      *usbos_tx_kt;
++#endif /* USBOS_TX_THREAD */
++
++	struct dma_pool *qtd_pool; /* QTD pool for USB optimization only */
++	int tx_ep, rx_ep, rx2_ep;  /* EPs for USB optimization */
++	struct usb_device *usb_device; /* USB device for optimization */
++} usbos_info_t;
++
++typedef struct urb_req {
++	void         *pkt;
++	int          buf_len;
++	struct urb   *urb;
++	void         *arg;
++	usbos_info_t *usbinfo;
++	struct list_head urb_list;
++} urb_req_t;
++
++#ifdef USBOS_THREAD
++typedef struct usbos_list_entry {
++	struct list_head    list;   /* must be first */
++	void               *urb_context;
++	int                 urb_length;
++	int                 urb_status;
++} usbos_list_entry_t;
++
++static void* dbus_usbos_thread_init(usbos_info_t *usbos_info);
++static void  dbus_usbos_thread_deinit(usbos_info_t *usbos_info);
++static void  dbus_usbos_dispatch_schedule(CALLBACK_ARGS);
++static int   dbus_usbos_thread_func(void *data);
++#endif /* USBOS_THREAD */
++
++#ifdef USBOS_TX_THREAD
++void* dbus_usbos_tx_thread_init(usbos_info_t *usbos_info);
++void  dbus_usbos_tx_thread_deinit(usbos_info_t *usbos_info);
++int   dbus_usbos_tx_thread_func(void *data);
++#endif /* USBOS_TX_THREAD */
++
++/* Shared Function prototypes */
++bool dbus_usbos_dl_cmd(usbos_info_t *usbinfo, uint8 cmd, void *buffer, int buflen);
++int dbus_usbos_wait(usbos_info_t *usbinfo, uint16 ms);
++bool dbus_usbos_dl_send_bulk(usbos_info_t *usbinfo, void *buffer, int len);
++int dbus_write_membytes(usbos_info_t *usbinfo, bool set, uint32 address, uint8 *data, uint size);
++
++/* Local function prototypes */
++static void dbus_usbos_send_complete(CALLBACK_ARGS);
++static void dbus_usbos_recv_complete(CALLBACK_ARGS);
++static int  dbus_usbos_errhandler(void *bus, int err);
++static int  dbus_usbos_state_change(void *bus, int state);
++static void dbusos_stop(usbos_info_t *usbos_info);
++
++#ifdef KERNEL26
++static int dbus_usbos_probe(struct usb_interface *intf, const struct usb_device_id *id);
++static void dbus_usbos_disconnect(struct usb_interface *intf);
++#if defined(USB_SUSPEND_AVAILABLE)
++static int dbus_usbos_resume(struct usb_interface *intf);
++static int dbus_usbos_suspend(struct usb_interface *intf, pm_message_t message);
++/* at the moment, used for full dongle host driver only */
++static int dbus_usbos_reset_resume(struct usb_interface *intf);
++#endif /* USB_SUSPEND_AVAILABLE */
++#else /* KERNEL26 */
++static void *dbus_usbos_probe(struct usb_device *usb, unsigned int ifnum,
++	const struct usb_device_id *id);
++static void dbus_usbos_disconnect(struct usb_device *usb, void *ptr);
++#endif /* KERNEL26 */
++
++
++/**
++ * have to disable missing-field-initializers warning as last element {} triggers it
++ * and different versions of kernel have different number of members so it is impossible
++ * to specify the initializer. BTW issuing the warning here is bug og GCC as  universal
++ * zero {0} specified in C99 standard as correct way of initialization of struct to all zeros
++ */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
++#endif
++
++static struct usb_device_id devid_table[] = {
++	{ USB_DEVICE(BCM_DNGL_VID, 0x0000) }, /* Configurable via register() */
++#if defined(BCM_REQUEST_FW)
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_4328) },
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_4322) },
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_4319) },
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_43236) },
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_43143) },
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_43242) },
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_4360) },
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_4350) },
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_43569) },
++#endif
++#ifdef EXTENDED_VID_PID
++	EXTENDED_VID_PID,
++#endif /* EXTENDED_VID_PID */
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BDC_PID) }, /* Default BDC */
++	{ }
++};
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++#pragma GCC diagnostic pop
++#endif
++
++MODULE_DEVICE_TABLE(usb, devid_table);
++
++/** functions called by the Linux kernel USB subsystem */
++static struct usb_driver dbus_usbdev = {
++	name:           "dbus_usbdev",
++	probe:          dbus_usbos_probe,
++	disconnect:     dbus_usbos_disconnect,
++	id_table:       devid_table,
++#if defined(USB_SUSPEND_AVAILABLE)
++	suspend:        dbus_usbos_suspend,
++	resume:         dbus_usbos_resume,
++	reset_resume:	dbus_usbos_reset_resume,
++	/* Linux USB core will allow autosuspend for devices bound to this driver */
++	supports_autosuspend: 1
++#endif /* USB_SUSPEND_AVAILABLE */
++};
++
++/**
++ * This stores USB info during Linux probe callback since attach() is not called yet at this point
++ */
++typedef struct {
++	void    *usbos_info;
++	struct usb_device *usb; /* USB device pointer from OS */
++	uint    rx_pipe;   /* Pipe numbers for USB I/O */
++	uint    tx_pipe;   /* Pipe numbers for USB I/O */
++	uint    intr_pipe; /* Pipe numbers for USB I/O */
++	uint    rx_pipe2;  /* Pipe numbers for USB I/O */
++	int     intr_size; /* Size of interrupt message */
++	int     interval;  /* Interrupt polling interval */
++	bool    dldone;
++	int     vid;
++	int     pid;
++	bool    dereged;
++	bool    disc_cb_done;
++	DEVICE_SPEED    device_speed;
++	enum usbos_suspend_state suspend_state;
++	struct usb_interface     *intf;
++} probe_info_t;
++
++/*
++ * USB Linux dbus_intf_t
++ */
++static void *dbus_usbos_intf_attach(dbus_pub_t *pub, void *cbarg, dbus_intf_callbacks_t *cbs);
++static void dbus_usbos_intf_detach(dbus_pub_t *pub, void *info);
++static int  dbus_usbos_intf_send_irb(void *bus, dbus_irb_tx_t *txirb);
++static int  dbus_usbos_intf_recv_irb(void *bus, dbus_irb_rx_t *rxirb);
++static int  dbus_usbos_intf_recv_irb_from_ep(void *bus, dbus_irb_rx_t *rxirb, uint32 ep_idx);
++static int  dbus_usbos_intf_cancel_irb(void *bus, dbus_irb_tx_t *txirb);
++static int  dbus_usbos_intf_send_ctl(void *bus, uint8 *buf, int len);
++static int  dbus_usbos_intf_recv_ctl(void *bus, uint8 *buf, int len);
++static int  dbus_usbos_intf_get_attrib(void *bus, dbus_attrib_t *attrib);
++static int  dbus_usbos_intf_up(void *bus);
++static int  dbus_usbos_intf_down(void *bus);
++static int  dbus_usbos_intf_stop(void *bus);
++static int  dbus_usbos_readreg(void *bus, uint32 regaddr, int datalen, uint32 *value);
++extern int dbus_usbos_loopback_tx(void *usbos_info_ptr, int cnt, int size);
++int dbus_usbos_writereg(void *bus, uint32 regaddr, int datalen, uint32 data);
++static int  dbus_usbos_intf_set_config(void *bus, dbus_config_t *config);
++static bool dbus_usbos_intf_recv_needed(void *bus);
++static void *dbus_usbos_intf_exec_rxlock(void *bus, exec_cb_t cb, struct exec_parms *args);
++static void *dbus_usbos_intf_exec_txlock(void *bus, exec_cb_t cb, struct exec_parms *args);
++#ifdef BCMUSBDEV_COMPOSITE
++static int dbus_usbos_intf_wlan(struct usb_device *usb);
++#endif /* BCMUSBDEV_COMPOSITE */
++
++/** functions called by dbus_usb.c */
++static dbus_intf_t dbus_usbos_intf = {
++	.attach = dbus_usbos_intf_attach,
++	.detach = dbus_usbos_intf_detach,
++	.up = dbus_usbos_intf_up,
++	.down = dbus_usbos_intf_down,
++	.send_irb = dbus_usbos_intf_send_irb,
++	.recv_irb = dbus_usbos_intf_recv_irb,
++	.cancel_irb = dbus_usbos_intf_cancel_irb,
++	.send_ctl = dbus_usbos_intf_send_ctl,
++	.recv_ctl = dbus_usbos_intf_recv_ctl,
++	.get_stats = NULL,
++	.get_attrib = dbus_usbos_intf_get_attrib,
++	.remove = NULL,
++	.resume = NULL,
++	.suspend = NULL,
++	.stop = dbus_usbos_intf_stop,
++	.reset = NULL,
++	.pktget = NULL,
++	.pktfree = NULL,
++	.iovar_op = NULL,
++	.dump = NULL,
++	.set_config = dbus_usbos_intf_set_config,
++	.get_config = NULL,
++	.device_exists = NULL,
++	.dlneeded = NULL,
++	.dlstart = NULL,
++	.dlrun = NULL,
++	.recv_needed = dbus_usbos_intf_recv_needed,
++	.exec_rxlock = dbus_usbos_intf_exec_rxlock,
++	.exec_txlock = dbus_usbos_intf_exec_txlock,
++
++	.tx_timer_init = NULL,
++	.tx_timer_start = NULL,
++	.tx_timer_stop = NULL,
++
++	.sched_dpc = NULL,
++	.lock = NULL,
++	.unlock = NULL,
++	.sched_probe_cb = NULL,
++
++	.shutdown = NULL,
++
++	.recv_stop = NULL,
++	.recv_resume = NULL,
++
++	.recv_irb_from_ep = dbus_usbos_intf_recv_irb_from_ep,
++	.readreg = dbus_usbos_readreg
++};
++
++static probe_info_t    g_probe_info;
++static probe_cb_t      probe_cb = NULL;
++static disconnect_cb_t disconnect_cb = NULL;
++static void            *probe_arg = NULL;
++static void            *disc_arg = NULL;
++
++
++
++static volatile int loopback_rx_cnt, loopback_tx_cnt;
++int loopback_size;
++bool is_loopback_pkt(void *buf);
++int matches_loopback_pkt(void *buf);
++
++/**
++ * multiple code paths in this file dequeue a URB request, this function makes sure that it happens
++ * in a concurrency save manner. Don't call this from a sleepable process context.
++ */
++static urb_req_t * BCMFASTPATH
++dbus_usbos_qdeq(struct list_head *urbreq_q, spinlock_t *lock)
++{
++	unsigned long flags;
++	urb_req_t *req;
++
++	ASSERT(urbreq_q != NULL);
++
++	spin_lock_irqsave(lock, flags);
++
++	if (list_empty(urbreq_q)) {
++		req = NULL;
++	} else {
++		ASSERT(urbreq_q->next != NULL);
++		ASSERT(urbreq_q->next != urbreq_q);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++		req = list_entry(urbreq_q->next, urb_req_t, urb_list);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++		list_del_init(&req->urb_list);
++	}
++
++	spin_unlock_irqrestore(lock, flags);
++
++	return req;
++}
++
++static void BCMFASTPATH
++dbus_usbos_qenq(struct list_head *urbreq_q, urb_req_t *req, spinlock_t *lock)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(lock, flags);
++
++	list_add_tail(&req->urb_list, urbreq_q);
++
++	spin_unlock_irqrestore(lock, flags);
++}
++
++/**
++ * multiple code paths in this file remove a URB request from a list, this function makes sure that
++ * it happens in a concurrency save manner. Don't call this from a sleepable process context.
++ * Is quite similar to dbus_usbos_qdeq(), I wonder why this function is needed.
++ */
++static void
++dbus_usbos_req_del(urb_req_t *req, spinlock_t *lock)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(lock, flags);
++
++	list_del_init(&req->urb_list);
++
++	spin_unlock_irqrestore(lock, flags);
++}
++
++
++/**
++ * Driver requires a pool of URBs to operate. This function is called during
++ * initialization (attach phase), allocates a number of URBs, and puts them
++ * on the free (req_rxfreeq and req_txfreeq) queue
++ */
++static int
++dbus_usbos_urbreqs_alloc(usbos_info_t *usbos_info, uint32 count, bool is_rx)
++{
++	int i;
++	int allocated = 0;
++	int err = DBUS_OK;
++
++	for (i = 0; i < count; i++) {
++		urb_req_t *req;
++
++		req = MALLOC(usbos_info->pub->osh, sizeof(urb_req_t));
++		if (req == NULL) {
++			DBUSERR(("%s: MALLOC req failed\n", __FUNCTION__));
++			err = DBUS_ERR_NOMEM;
++			goto fail;
++		}
++		bzero(req, sizeof(urb_req_t));
++
++		req->urb = USB_ALLOC_URB();
++		if (req->urb == NULL) {
++			DBUSERR(("%s: USB_ALLOC_URB req->urb failed\n", __FUNCTION__));
++			err = DBUS_ERR_NOMEM;
++			goto fail;
++		}
++
++		INIT_LIST_HEAD(&req->urb_list);
++
++		if (is_rx) {
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++			/* don't allocate now. Do it on demand */
++			req->pkt = NULL;
++#else
++			/* pre-allocate  buffers never to be released */
++			req->pkt = MALLOC(usbos_info->pub->osh, usbos_info->rxbuf_len);
++			if (req->pkt == NULL) {
++				DBUSERR(("%s: MALLOC req->pkt failed\n", __FUNCTION__));
++				err = DBUS_ERR_NOMEM;
++				goto fail;
++			}
++#endif
++			req->buf_len = usbos_info->rxbuf_len;
++			dbus_usbos_qenq(&usbos_info->req_rxfreeq, req, &usbos_info->rxfree_lock);
++		} else {
++			req->buf_len = 0;
++			dbus_usbos_qenq(&usbos_info->req_txfreeq, req, &usbos_info->txfree_lock);
++		}
++		allocated++;
++		continue;
++
++fail:
++		if (req) {
++			if (is_rx && req->pkt) {
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++				/* req->pkt is NULL in "NOCOPY" mode */
++#else
++				MFREE(usbos_info->pub->osh, req->pkt, req->buf_len);
++#endif
++			}
++			if (req->urb) {
++				USB_FREE_URB(req->urb);
++			}
++			MFREE(usbos_info->pub->osh, req, sizeof(urb_req_t));
++		}
++		break;
++	}
++
++	atomic_add(allocated, is_rx ? &usbos_info->rxallocated : &usbos_info->txallocated);
++
++	if (is_rx) {
++		DBUSTRACE(("%s: add %d (total %d) rx buf, each has %d bytes\n", __FUNCTION__,
++			allocated, atomic_read(&usbos_info->rxallocated), usbos_info->rxbuf_len));
++	} else {
++		DBUSTRACE(("%s: add %d (total %d) tx req\n", __FUNCTION__,
++			allocated, atomic_read(&usbos_info->txallocated)));
++	}
++
++	return err;
++} /* dbus_usbos_urbreqs_alloc */
++
++/** Typically called during detach or when attach failed. Don't call until all URBs unlinked */
++static int
++dbus_usbos_urbreqs_free(usbos_info_t *usbos_info, bool is_rx)
++{
++	int rtn = 0;
++	urb_req_t *req;
++	struct list_head *req_q;
++	spinlock_t *lock;
++
++	if (is_rx) {
++		req_q = &usbos_info->req_rxfreeq;
++		lock = &usbos_info->rxfree_lock;
++	} else {
++		req_q = &usbos_info->req_txfreeq;
++		lock = &usbos_info->txfree_lock;
++	}
++	while ((req = dbus_usbos_qdeq(req_q, lock)) != NULL) {
++
++		if (is_rx) {
++			if (req->pkt) {
++				/* We do MFREE instead of PKTFREE because the pkt has been
++				 * converted to native already
++				 */
++				MFREE(usbos_info->pub->osh, req->pkt, req->buf_len);
++				req->pkt = NULL;
++				req->buf_len = 0;
++			}
++		} else {
++			/* sending req should not be assigned pkt buffer */
++			ASSERT(req->pkt == NULL);
++		}
++
++		if (req->urb) {
++			USB_FREE_URB(req->urb);
++			req->urb = NULL;
++		}
++		MFREE(usbos_info->pub->osh, req, sizeof(urb_req_t));
++
++		rtn++;
++	}
++	return rtn;
++} /* dbus_usbos_urbreqs_free */
++
++/**
++ * called by Linux kernel on URB completion. Upper DBUS layer (dbus_usb.c) has to be notified of
++ * send completion.
++ */
++void
++dbus_usbos_send_complete(CALLBACK_ARGS)
++{
++	urb_req_t *req = urb->context;
++	dbus_irb_tx_t *txirb = req->arg;
++	usbos_info_t *usbos_info = req->usbinfo;
++	unsigned long flags;
++	int status = DBUS_OK;
++	int txposted;
++
++	USB_AUTOPM_PUT_INTERFACE_ASYNC(g_probe_info.intf);
++
++	spin_lock_irqsave(&usbos_info->txlock, flags);
++
++	dbus_usbos_req_del(req, &usbos_info->txposted_lock);
++	txposted = atomic_dec_return(&usbos_info->txposted);
++	if (unlikely (txposted < 0)) {
++		DBUSERR(("%s ERROR: txposted is negative (%d)!!\n", __FUNCTION__, txposted));
++	}
++	spin_unlock_irqrestore(&usbos_info->txlock, flags);
++
++	if (unlikely (urb->status)) {
++		status = DBUS_ERR_TXFAIL;
++		DBUSTRACE(("txfail status %d\n", urb->status));
++	}
++
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++	/* sending req should not be assigned pkt buffer */
++	ASSERT(req->pkt == NULL);
++#endif
++	/*  txirb should always be set, except for ZLP. ZLP is reusing this callback function. */
++	if (txirb != NULL) {
++		if (txirb->send_buf != NULL) {
++			MFREE(usbos_info->pub->osh, txirb->send_buf, req->buf_len);
++			txirb->send_buf = NULL;
++			req->buf_len = 0;
++		}
++		if (likely (usbos_info->cbarg && usbos_info->cbs)) {
++			if (likely (usbos_info->cbs->send_irb_complete != NULL))
++			    usbos_info->cbs->send_irb_complete(usbos_info->cbarg, txirb, status);
++		}
++	}
++
++	dbus_usbos_qenq(&usbos_info->req_txfreeq, req, &usbos_info->txfree_lock);
++} /* dbus_usbos_send_complete */
++
++/**
++ * In order to receive USB traffic from the dongle, we need to supply the Linux kernel with a free
++ * URB that is going to contain received data.
++ */
++static int BCMFASTPATH
++dbus_usbos_recv_urb_submit(usbos_info_t *usbos_info, dbus_irb_rx_t *rxirb, uint32 ep_idx)
++{
++	urb_req_t *req;
++	int ret = DBUS_OK;
++	unsigned long flags;
++	void *p;
++	uint rx_pipe;
++	int rxposted;
++
++	BCM_REFERENCE(rxposted);
++
++	if (!(req = dbus_usbos_qdeq(&usbos_info->req_rxfreeq, &usbos_info->rxfree_lock))) {
++		DBUSTRACE(("%s No free URB!\n", __FUNCTION__));
++		return DBUS_ERR_RXDROP;
++	}
++
++	spin_lock_irqsave(&usbos_info->rxlock, flags);
++
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++	req->pkt = rxirb->pkt = PKTGET(usbos_info->pub->osh, req->buf_len, FALSE);
++	if (!rxirb->pkt) {
++		DBUSERR(("%s: PKTGET failed\n", __FUNCTION__));
++		dbus_usbos_qenq(&usbos_info->req_rxfreeq, req, &usbos_info->rxfree_lock);
++		ret = DBUS_ERR_RXDROP;
++		goto fail;
++	}
++	/* consider the packet "native" so we don't count it as MALLOCED in the osl */
++	PKTTONATIVE(usbos_info->pub->osh, req->pkt);
++	rxirb->buf = NULL;
++	p = PKTDATA(usbos_info->pub->osh, req->pkt);
++#else
++	if (req->buf_len != usbos_info->rxbuf_len) {
++		ASSERT(req->pkt);
++		MFREE(usbos_info->pub->osh, req->pkt, req->buf_len);
++		DBUSTRACE(("%s: replace rx buff: old len %d, new len %d\n", __FUNCTION__,
++			req->buf_len, usbos_info->rxbuf_len));
++		req->buf_len = 0;
++		req->pkt = MALLOC(usbos_info->pub->osh, usbos_info->rxbuf_len);
++		if (req->pkt == NULL) {
++			DBUSERR(("%s: MALLOC req->pkt failed\n", __FUNCTION__));
++			ret = DBUS_ERR_NOMEM;
++			goto fail;
++		}
++		req->buf_len = usbos_info->rxbuf_len;
++	}
++	rxirb->buf = req->pkt;
++	p = rxirb->buf;
++#endif /* defined(BCM_RPC_NOCOPY) */
++	rxirb->buf_len = req->buf_len;
++	req->usbinfo = usbos_info;
++	req->arg = rxirb;
++	if (ep_idx == 0) {
++		rx_pipe = usbos_info->rx_pipe;
++	} else {
++		rx_pipe = usbos_info->rx_pipe2;
++		ASSERT(usbos_info->rx_pipe2);
++	}
++	/* Prepare the URB */
++	usb_fill_bulk_urb(req->urb, usbos_info->usb, rx_pipe,
++		p,
++		rxirb->buf_len,
++		(usb_complete_t)dbus_usbos_recv_complete, req);
++		req->urb->transfer_flags |= URB_QUEUE_BULK;
++
++	if ((ret = USB_SUBMIT_URB(req->urb))) {
++		DBUSERR(("%s USB_SUBMIT_URB failed. status %d\n", __FUNCTION__, ret));
++		dbus_usbos_qenq(&usbos_info->req_rxfreeq, req, &usbos_info->rxfree_lock);
++		ret = DBUS_ERR_RXFAIL;
++		goto fail;
++	}
++	rxposted = atomic_inc_return(&usbos_info->rxposted);
++
++	dbus_usbos_qenq(&usbos_info->req_rxpostedq, req, &usbos_info->rxposted_lock);
++fail:
++	spin_unlock_irqrestore(&usbos_info->rxlock, flags);
++	return ret;
++} /* dbus_usbos_recv_urb_submit */
++
++
++/**
++ * Called by worked thread when a 'receive URB' completed or Linux kernel when it returns a URB to
++ * this driver.
++ */
++static void BCMFASTPATH
++dbus_usbos_recv_complete_handle(urb_req_t *req, int len, int status)
++{
++	dbus_irb_rx_t *rxirb = req->arg;
++	usbos_info_t *usbos_info = req->usbinfo;
++	unsigned long flags;
++	int rxallocated, rxposted;
++	int dbus_status = DBUS_OK;
++	bool killed = (g_probe_info.suspend_state == USBOS_SUSPEND_STATE_SUSPEND_PENDING) ? 1 : 0;
++
++	spin_lock_irqsave(&usbos_info->rxlock, flags);
++	dbus_usbos_req_del(req, &usbos_info->rxposted_lock);
++	rxposted = atomic_dec_return(&usbos_info->rxposted);
++	rxallocated = atomic_read(&usbos_info->rxallocated);
++	spin_unlock_irqrestore(&usbos_info->rxlock, flags);
++
++	if ((rxallocated < usbos_info->pub->nrxq) && (!status) &&
++		(rxposted == DBUS_USB_RXQUEUE_LOWER_WATERMARK)) {
++			DBUSTRACE(("%s: need more rx buf: rxallocated %d rxposted %d!\n",
++				__FUNCTION__, rxallocated, rxposted));
++			dbus_usbos_urbreqs_alloc(usbos_info,
++				MIN(DBUS_USB_RXQUEUE_BATCH_ADD,
++				usbos_info->pub->nrxq - rxallocated), TRUE);
++	}
++
++	/* Handle errors */
++	if (status) {
++		/*
++		 * Linux 2.4 disconnect: -ENOENT or -EILSEQ for CRC error; rmmod: -ENOENT
++		 * Linux 2.6 disconnect: -EPROTO, rmmod: -ESHUTDOWN
++		 */
++		if ((status == -ENOENT && (!killed))|| status == -ESHUTDOWN) {
++			/* NOTE: unlink() can not be called from URB callback().
++			 * Do not call dbusos_stop() here.
++			 */
++			DBUSTRACE(("%s rx error %d\n", __FUNCTION__, status));
++			dbus_usbos_state_change(usbos_info, DBUS_STATE_DOWN);
++		} else if (status == -EPROTO) {
++			DBUSTRACE(("%s rx error %d\n", __FUNCTION__, status));
++		} else if (killed && (status == -EHOSTUNREACH || status == -ENOENT)) {
++			/* Device is suspended */
++		} else {
++			DBUSTRACE(("%s rx error %d\n", __FUNCTION__, status));
++			dbus_usbos_errhandler(usbos_info, DBUS_ERR_RXFAIL);
++		}
++
++		/* On error, don't submit more URBs yet */
++		rxirb->buf = NULL;
++		rxirb->actual_len = 0;
++		dbus_status = DBUS_ERR_RXFAIL;
++		goto fail;
++	}
++
++	/* Make the skb represent the received urb */
++	rxirb->actual_len = len;
++
++	if (rxirb->actual_len < sizeof(uint32)) {
++		DBUSTRACE(("small pkt len %d, process as ZLP\n", rxirb->actual_len));
++		dbus_status = DBUS_ERR_RXZLP;
++	}
++
++fail:
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++	/* detach the packet from the queue */
++	req->pkt = NULL;
++#endif /* BCM_RPC_NOCOPY || BCM_RPC_RXNOCOPY */
++
++	if (usbos_info->cbarg && usbos_info->cbs) {
++		if (usbos_info->cbs->recv_irb_complete) {
++			usbos_info->cbs->recv_irb_complete(usbos_info->cbarg, rxirb, dbus_status);
++		}
++	}
++
++	dbus_usbos_qenq(&usbos_info->req_rxfreeq, req, &usbos_info->rxfree_lock);
++
++	/* Mark the interface as busy to reset USB autosuspend timer */
++	USB_MARK_LAST_BUSY(usbos_info->usb);
++} /* dbus_usbos_recv_complete_handle */
++
++/** called by Linux kernel when it returns a URB to this driver */
++static void
++dbus_usbos_recv_complete(CALLBACK_ARGS)
++{
++#ifdef USBOS_THREAD
++	dbus_usbos_dispatch_schedule(CALLBACK_ARGS_DATA);
++#else /*  !USBOS_THREAD */
++	dbus_usbos_recv_complete_handle(urb->context, urb->actual_length, urb->status);
++#endif /*  USBOS_THREAD */
++}
++
++
++/**
++ * If Linux notifies our driver that a control read or write URB has completed, we should notify
++ * the DBUS layer above us (dbus_usb.c in this case).
++ */
++static void
++dbus_usbos_ctl_complete(usbos_info_t *usbos_info, int type, int urbstatus)
++{
++	int status = DBUS_ERR;
++
++	if (usbos_info == NULL)
++		return;
++
++	switch (urbstatus) {
++		case 0:
++			status = DBUS_OK;
++		break;
++		case -EINPROGRESS:
++		case -ENOENT:
++		default:
++#ifdef INTR_EP_ENABLE
++			DBUSERR(("%s:%d fail status %d bus:%d susp:%d intr:%d ctli:%d ctlo:%d\n",
++				__FUNCTION__, type, urbstatus,
++				usbos_info->pub->busstate, g_probe_info.suspend_state,
++				usbos_info->intr_urb_submitted, usbos_info->ctlin_urb_submitted,
++				usbos_info->ctlout_urb_submitted));
++#else
++			DBUSERR(("%s: failed with status %d\n", __FUNCTION__, urbstatus));
++			status = DBUS_ERR;
++		break;
++#endif /* INTR_EP_ENABLE */
++	}
++
++	if (usbos_info->cbarg && usbos_info->cbs) {
++		if (usbos_info->cbs->ctl_complete)
++			usbos_info->cbs->ctl_complete(usbos_info->cbarg, type, status);
++	}
++}
++
++/** called by Linux */
++static void
++dbus_usbos_ctlread_complete(CALLBACK_ARGS)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *)urb->context;
++
++	ASSERT(urb);
++	usbos_info = (usbos_info_t *)urb->context;
++
++	dbus_usbos_ctl_complete(usbos_info, DBUS_CBCTL_READ, urb->status);
++
++#ifdef USBOS_THREAD
++	if (usbos_info->rxctl_deferrespok) {
++		usbos_info->ctl_read.bRequestType = USB_DIR_IN | USB_TYPE_CLASS |
++		USB_RECIP_INTERFACE;
++		usbos_info->ctl_read.bRequest = 1;
++	}
++#endif
++
++	up(&usbos_info->ctl_lock);
++
++	USB_AUTOPM_PUT_INTERFACE_ASYNC(g_probe_info.intf);
++}
++
++/** called by Linux */
++static void
++dbus_usbos_ctlwrite_complete(CALLBACK_ARGS)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *)urb->context;
++
++	ASSERT(urb);
++	usbos_info = (usbos_info_t *)urb->context;
++
++	dbus_usbos_ctl_complete(usbos_info, DBUS_CBCTL_WRITE, urb->status);
++
++#ifdef USBOS_TX_THREAD
++	usbos_info->ctl_state = USBOS_REQUEST_STATE_UNSCHEDULED;
++#endif /* USBOS_TX_THREAD */
++
++	up(&usbos_info->ctl_lock);
++
++	USB_AUTOPM_PUT_INTERFACE_ASYNC(g_probe_info.intf);
++}
++
++#ifdef INTR_EP_ENABLE
++/** called by Linux */
++static void
++dbus_usbos_intr_complete(CALLBACK_ARGS)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *)urb->context;
++	bool killed = (g_probe_info.suspend_state == USBOS_SUSPEND_STATE_SUSPEND_PENDING) ? 1 : 0;
++
++	if (usbos_info == NULL || usbos_info->pub == NULL)
++		return;
++	if ((urb->status == -ENOENT && (!killed)) || urb->status == -ESHUTDOWN ||
++		urb->status == -ENODEV) {
++		dbus_usbos_state_change(usbos_info, DBUS_STATE_DOWN);
++	}
++
++	if (usbos_info->pub->busstate == DBUS_STATE_DOWN) {
++		DBUSERR(("%s: intr cb when DBUS down, ignoring\n", __FUNCTION__));
++		return;
++	}
++	dbus_usbos_ctl_complete(usbos_info, DBUS_CBINTR_POLL, urb->status);
++}
++#endif	/* INTR_EP_ENABLE */
++
++/**
++ * when the bus is going to sleep or halt, the Linux kernel requires us to take ownership of our
++ * URBs again. Multiple code paths in this file require a list of URBs to be cancelled in a
++ * concurrency save manner.
++ */
++static void
++dbus_usbos_unlink(struct list_head *urbreq_q, spinlock_t *lock)
++{
++	urb_req_t *req;
++
++	/* dbus_usbos_recv_complete() adds req back to req_freeq */
++	while ((req = dbus_usbos_qdeq(urbreq_q, lock)) != NULL) {
++		ASSERT(req->urb != NULL);
++		USB_UNLINK_URB(req->urb);
++	}
++}
++
++/** multiple code paths in this file require the bus to stop */
++static void
++dbus_usbos_cancel_all_urbs(usbos_info_t *usbos_info)
++{
++	int rxposted, txposted;
++
++	DBUSTRACE(("%s: unlink all URBs\n", __FUNCTION__));
++
++#ifdef USBOS_TX_THREAD
++	usbos_info->ctl_state = USBOS_REQUEST_STATE_UNSCHEDULED;
++
++	/* Yield the CPU to TX thread so all pending requests are submitted */
++	while (!list_empty(&usbos_info->usbos_tx_list)) {
++		wake_up_interruptible(&usbos_info->usbos_tx_queue_head);
++		OSL_SLEEP(10);
++	}
++#endif /* USBOS_TX_THREAD */
++
++	/* tell Linux kernel to cancel a single intr, ctl and blk URB */
++	if (usbos_info->intr_urb)
++		USB_UNLINK_URB(usbos_info->intr_urb);
++	if (usbos_info->ctl_urb)
++		USB_UNLINK_URB(usbos_info->ctl_urb);
++	if (usbos_info->blk_urb)
++		USB_UNLINK_URB(usbos_info->blk_urb);
++
++	dbus_usbos_unlink(&usbos_info->req_txpostedq, &usbos_info->txposted_lock);
++	dbus_usbos_unlink(&usbos_info->req_rxpostedq, &usbos_info->rxposted_lock);
++
++	/* Wait until the callbacks for all submitted URBs have been called, because the
++	 * handler needs to know is an USB suspend is in progress.
++	 */
++	SPINWAIT((atomic_read(&usbos_info->txposted) != 0 ||
++		atomic_read(&usbos_info->rxposted) != 0), 10000);
++
++	txposted = atomic_read(&usbos_info->txposted);
++	rxposted = atomic_read(&usbos_info->rxposted);
++	if (txposted != 0 || rxposted != 0) {
++		DBUSERR(("%s ERROR: REQs posted, rx=%d tx=%d!\n",
++			__FUNCTION__, rxposted, txposted));
++	}
++} /* dbus_usbos_cancel_all_urbs */
++
++/** multiple code paths require the bus to stop */
++static void
++dbusos_stop(usbos_info_t *usbos_info)
++{
++	urb_req_t *req;
++	int rxposted;
++	req = NULL;
++	BCM_REFERENCE(req);
++
++	ASSERT(usbos_info);
++
++	dbus_usbos_state_change(usbos_info, DBUS_STATE_DOWN);
++
++	dbus_usbos_cancel_all_urbs(usbos_info);
++
++#ifdef USBOS_THREAD
++	/* yield the CPU to rx packet thread */
++	while (1) {
++		if (atomic_read(&usbos_info->usbos_list_cnt) <= 0)	break;
++		wake_up_interruptible(&usbos_info->usbos_queue_head);
++		OSL_SLEEP(3);
++	}
++#endif /* USBOS_THREAD */
++
++	rxposted = atomic_read(&usbos_info->rxposted);
++	if (rxposted > 0) {
++		DBUSERR(("%s ERROR: rx REQs posted=%d in stop!\n", __FUNCTION__,
++			rxposted));
++	}
++
++	ASSERT(atomic_read(&usbos_info->txposted) == 0 && rxposted == 0);
++
++} /* dbusos_stop */
++
++#if defined(USB_SUSPEND_AVAILABLE)
++
++/**
++ * Linux kernel sports a 'USB auto suspend' feature. See: http://lwn.net/Articles/373550/
++ * The suspend method is called by the Linux kernel to warn the driver that the device is going to
++ * be suspended.  If the driver returns a negative error code, the suspend will be aborted. If the
++ * driver returns 0, it must cancel all outstanding URBs (usb_kill_urb()) and not submit any more.
++ */
++static int
++dbus_usbos_suspend(struct usb_interface *intf,
++            pm_message_t message)
++{
++	DBUSERR(("%s suspend state: %d\n", __FUNCTION__, g_probe_info.suspend_state));
++	/* DHD for full dongle model */
++	g_probe_info.suspend_state = USBOS_SUSPEND_STATE_SUSPEND_PENDING;
++	dbus_usbos_state_change((usbos_info_t*)g_probe_info.usbos_info, DBUS_STATE_SLEEP);
++	dbus_usbos_cancel_all_urbs((usbos_info_t*)g_probe_info.usbos_info);
++	g_probe_info.suspend_state = USBOS_SUSPEND_STATE_SUSPENDED;
++
++	return 0;
++}
++
++/**
++ * The resume method is called to tell the driver that the device has been resumed and the driver
++ * can return to normal operation.  URBs may once more be submitted.
++ */
++static int dbus_usbos_resume(struct usb_interface *intf)
++{
++	DBUSERR(("%s Device resumed\n", __FUNCTION__));
++
++	dbus_usbos_state_change((usbos_info_t*)g_probe_info.usbos_info, DBUS_STATE_UP);
++	g_probe_info.suspend_state = USBOS_SUSPEND_STATE_DEVICE_ACTIVE;
++	return 0;
++}
++
++/**
++* This function is directly called by the Linux kernel, when the suspended device has been reset
++* instead of being resumed
++*/
++static int dbus_usbos_reset_resume(struct usb_interface *intf)
++{
++	DBUSERR(("%s Device reset resumed\n", __FUNCTION__));
++
++	/* The device may have lost power, so a firmware download may be required */
++	dbus_usbos_state_change((usbos_info_t*)g_probe_info.usbos_info, DBUS_STATE_DL_NEEDED);
++	g_probe_info.suspend_state = USBOS_SUSPEND_STATE_DEVICE_ACTIVE;
++	return 0;
++}
++
++#endif /* USB_SUSPEND_AVAILABLE */
++
++/**
++ * Called by Linux kernel at initialization time, kernel wants to know if our driver will accept the
++ * caller supplied USB interface. Note that USB drivers are bound to interfaces, and not to USB
++ * devices.
++ */
++#ifdef KERNEL26
++#define DBUS_USBOS_PROBE() static int dbus_usbos_probe(struct usb_interface *intf, const struct usb_device_id *id)
++#define DBUS_USBOS_DISCONNECT() static void dbus_usbos_disconnect(struct usb_interface *intf)
++#else
++#define DBUS_USBOS_PROBE() static void * dbus_usbos_probe(struct usb_device *usb, unsigned int ifnum, const struct usb_device_id *id)
++#define DBUS_USBOS_DISCONNECT() static void dbus_usbos_disconnect(struct usb_device *usb, void *ptr)
++#endif /* KERNEL26 */
++
++DBUS_USBOS_PROBE()
++{
++	int ep;
++	struct usb_endpoint_descriptor *endpoint;
++	int ret = 0;
++#ifdef KERNEL26
++	struct usb_device *usb = interface_to_usbdev(intf);
++#else
++	int claimed = 0;
++#endif
++	int num_of_eps;
++#ifdef BCMUSBDEV_COMPOSITE
++	int wlan_if = -1;
++	bool intr_ep = FALSE;
++#endif /* BCMUSBDEV_COMPOSITE */
++	wifi_adapter_info_t *adapter;
++
++	DHD_MUTEX_LOCK();
++
++	DBUSERR(("%s: bus num(busnum)=%d, slot num (portnum)=%d\n", __FUNCTION__,
++		usb->bus->busnum, usb->portnum));
++	adapter = dhd_wifi_platform_attach_adapter(USB_BUS, usb->bus->busnum,
++		usb->portnum, WIFI_STATUS_POWER_ON);
++	if (adapter == NULL) {
++		DBUSERR(("%s: can't find adapter info for this chip\n", __FUNCTION__));
++		goto fail;
++	}
++
++#ifdef BCMUSBDEV_COMPOSITE
++	wlan_if = dbus_usbos_intf_wlan(usb);
++#ifdef KERNEL26
++	if ((wlan_if >= 0) && (IFPTR(usb, wlan_if) == intf))
++#else
++	if (wlan_if == ifnum)
++#endif /* KERNEL26 */
++	{
++#endif /* BCMUSBDEV_COMPOSITE */
++		g_probe_info.usb = usb;
++		g_probe_info.dldone = TRUE;
++#ifdef BCMUSBDEV_COMPOSITE
++	} else {
++		DBUSTRACE(("dbus_usbos_probe: skip probe for non WLAN interface\n"));
++		ret = BCME_UNSUPPORTED;
++		goto fail;
++	}
++#endif /* BCMUSBDEV_COMPOSITE */
++
++#ifdef KERNEL26
++	g_probe_info.intf = intf;
++#endif /* KERNEL26 */
++
++#ifdef BCMUSBDEV_COMPOSITE
++	if (IFDESC(usb, wlan_if).bInterfaceNumber > USB_COMPIF_MAX)
++#else
++	if (IFDESC(usb, CONTROL_IF).bInterfaceNumber)
++#endif /* BCMUSBDEV_COMPOSITE */
++	{
++		ret = -1;
++		goto fail;
++	}
++	if (id != NULL) {
++		g_probe_info.vid = id->idVendor;
++		g_probe_info.pid = id->idProduct;
++	}
++
++#ifdef KERNEL26
++	usb_set_intfdata(intf, &g_probe_info);
++#endif
++
++	/* Check that the device supports only one configuration */
++	if (usb->descriptor.bNumConfigurations != 1) {
++		ret = -1;
++		goto fail;
++	}
++
++	if (usb->descriptor.bDeviceClass != USB_CLASS_VENDOR_SPEC) {
++#ifdef BCMUSBDEV_COMPOSITE
++		if ((usb->descriptor.bDeviceClass != USB_CLASS_MISC) &&
++			(usb->descriptor.bDeviceClass != USB_CLASS_WIRELESS)) {
++#endif /* BCMUSBDEV_COMPOSITE */
++			ret = -1;
++			goto fail;
++#ifdef BCMUSBDEV_COMPOSITE
++		}
++#endif /* BCMUSBDEV_COMPOSITE */
++	}
++
++	/*
++	 * Only the BDC interface configuration is supported:
++	 *	Device class: USB_CLASS_VENDOR_SPEC
++	 *	if0 class: USB_CLASS_VENDOR_SPEC
++	 *	if0/ep0: control
++	 *	if0/ep1: bulk in
++	 *	if0/ep2: bulk out (ok if swapped with bulk in)
++	 */
++	if (CONFIGDESC(usb)->bNumInterfaces != 1) {
++#ifdef BCMUSBDEV_COMPOSITE
++		if (CONFIGDESC(usb)->bNumInterfaces > USB_COMPIF_MAX) {
++#endif /* BCMUSBDEV_COMPOSITE */
++			ret = -1;
++			goto fail;
++#ifdef BCMUSBDEV_COMPOSITE
++		}
++#endif /* BCMUSBDEV_COMPOSITE */
++	}
++
++	/* Check interface */
++#ifndef KERNEL26
++#ifdef BCMUSBDEV_COMPOSITE
++	if (usb_interface_claimed(IFPTR(usb, wlan_if)))
++#else
++	if (usb_interface_claimed(IFPTR(usb, CONTROL_IF)))
++#endif /* BCMUSBDEV_COMPOSITE */
++	{
++		ret = -1;
++		goto fail;
++	}
++#endif /* !KERNEL26 */
++
++#ifdef BCMUSBDEV_COMPOSITE
++	if ((IFDESC(usb, wlan_if).bInterfaceClass != USB_CLASS_VENDOR_SPEC ||
++		IFDESC(usb, wlan_if).bInterfaceSubClass != 2 ||
++		IFDESC(usb, wlan_if).bInterfaceProtocol != 0xff) &&
++		(IFDESC(usb, wlan_if).bInterfaceClass != USB_CLASS_MISC ||
++		IFDESC(usb, wlan_if).bInterfaceSubClass != USB_SUBCLASS_COMMON ||
++		IFDESC(usb, wlan_if).bInterfaceProtocol != USB_PROTO_IAD))
++#else
++	if (IFDESC(usb, CONTROL_IF).bInterfaceClass != USB_CLASS_VENDOR_SPEC ||
++		IFDESC(usb, CONTROL_IF).bInterfaceSubClass != 2 ||
++		IFDESC(usb, CONTROL_IF).bInterfaceProtocol != 0xff)
++#endif /* BCMUSBDEV_COMPOSITE */
++	{
++#ifdef BCMUSBDEV_COMPOSITE
++			DBUSERR(("%s: invalid control interface: class %d, subclass %d, proto %d\n",
++				__FUNCTION__,
++				IFDESC(usb, wlan_if).bInterfaceClass,
++				IFDESC(usb, wlan_if).bInterfaceSubClass,
++				IFDESC(usb, wlan_if).bInterfaceProtocol));
++#else
++			DBUSERR(("%s: invalid control interface: class %d, subclass %d, proto %d\n",
++				__FUNCTION__,
++				IFDESC(usb, CONTROL_IF).bInterfaceClass,
++				IFDESC(usb, CONTROL_IF).bInterfaceSubClass,
++				IFDESC(usb, CONTROL_IF).bInterfaceProtocol));
++#endif /* BCMUSBDEV_COMPOSITE */
++			ret = -1;
++			goto fail;
++	}
++
++	/* Check control endpoint */
++#ifdef BCMUSBDEV_COMPOSITE
++	endpoint = &IFEPDESC(usb, wlan_if, 0);
++#else
++	endpoint = &IFEPDESC(usb, CONTROL_IF, 0);
++#endif /* BCMUSBDEV_COMPOSITE */
++	if ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) != USB_ENDPOINT_XFER_INT) {
++#ifdef BCMUSBDEV_COMPOSITE
++		if ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) !=
++			USB_ENDPOINT_XFER_BULK) {
++#endif /* BCMUSBDEV_COMPOSITE */
++			DBUSERR(("%s: invalid control endpoint %d\n",
++				__FUNCTION__, endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK));
++			ret = -1;
++			goto fail;
++#ifdef BCMUSBDEV_COMPOSITE
++		}
++#endif /* BCMUSBDEV_COMPOSITE */
++	}
++
++#ifdef BCMUSBDEV_COMPOSITE
++	if ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
++#endif /* BCMUSBDEV_COMPOSITE */
++		g_probe_info.intr_pipe =
++			usb_rcvintpipe(usb, endpoint->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK);
++#ifdef BCMUSBDEV_COMPOSITE
++		intr_ep = TRUE;
++	}
++#endif /* BCMUSBDEV_COMPOSITE */
++
++#ifndef KERNEL26
++	/* Claim interface */
++#ifdef BCMUSBDEV_COMPOSITE
++	usb_driver_claim_interface(&dbus_usbdev, IFPTR(usb, wlan_if), &g_probe_info);
++#else
++	usb_driver_claim_interface(&dbus_usbdev, IFPTR(usb, CONTROL_IF), &g_probe_info);
++#endif /* BCMUSBDEV_COMPOSITE */
++	claimed = 1;
++#endif /* !KERNEL26 */
++	g_probe_info.rx_pipe = 0;
++	g_probe_info.rx_pipe2 = 0;
++	g_probe_info.tx_pipe = 0;
++#ifdef BCMUSBDEV_COMPOSITE
++	if (intr_ep)
++		ep = 1;
++	else
++		ep = 0;
++	num_of_eps = IFDESC(usb, wlan_if).bNumEndpoints - 1;
++#else
++	num_of_eps = IFDESC(usb, BULK_IF).bNumEndpoints - 1;
++#endif /* BCMUSBDEV_COMPOSITE */
++
++	if ((num_of_eps != 2) && (num_of_eps != 3)) {
++#ifdef BCMUSBDEV_COMPOSITE
++		if (num_of_eps > 7)
++#endif /* BCMUSBDEV_COMPOSITE */
++			ASSERT(0);
++	}
++	/* Check data endpoints and get pipes */
++#ifdef BCMUSBDEV_COMPOSITE
++	for (; ep <= num_of_eps; ep++)
++#else
++	for (ep = 1; ep <= num_of_eps; ep++)
++#endif /* BCMUSBDEV_COMPOSITE */
++	{
++#ifdef BCMUSBDEV_COMPOSITE
++		endpoint = &IFEPDESC(usb, wlan_if, ep);
++#else
++		endpoint = &IFEPDESC(usb, BULK_IF, ep);
++#endif /* BCMUSBDEV_COMPOSITE */
++		if ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) !=
++		    USB_ENDPOINT_XFER_BULK) {
++			DBUSERR(("%s: invalid data endpoint %d\n",
++			           __FUNCTION__, ep));
++			ret = -1;
++			goto fail;
++		}
++
++		if ((endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
++			/* direction: dongle->host */
++			if (!g_probe_info.rx_pipe) {
++				g_probe_info.rx_pipe = usb_rcvbulkpipe(usb,
++					(endpoint->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK));
++			} else {
++				g_probe_info.rx_pipe2 = usb_rcvbulkpipe(usb,
++					(endpoint->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK));
++			}
++
++		} else
++			g_probe_info.tx_pipe = usb_sndbulkpipe(usb, (endpoint->bEndpointAddress &
++			     USB_ENDPOINT_NUMBER_MASK));
++	}
++
++	/* Allocate interrupt URB and data buffer */
++	/* RNDIS says 8-byte intr, our old drivers used 4-byte */
++#ifdef BCMUSBDEV_COMPOSITE
++	g_probe_info.intr_size = (IFEPDESC(usb, wlan_if, 0).wMaxPacketSize == 16) ? 8 : 4;
++	g_probe_info.interval = IFEPDESC(usb, wlan_if, 0).bInterval;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21))
++	usb->quirks |= USB_QUIRK_NO_SET_INTF;
++#endif
++#else
++	g_probe_info.intr_size = (IFEPDESC(usb, CONTROL_IF, 0).wMaxPacketSize == 16) ? 8 : 4;
++	g_probe_info.interval = IFEPDESC(usb, CONTROL_IF, 0).bInterval;
++#endif /* BCMUSBDEV_COMPOSITE */
++
++#ifndef KERNEL26
++	/* usb_fill_int_urb does the interval decoding in 2.6 */
++	if (usb->speed == USB_SPEED_HIGH)
++		g_probe_info.interval = 1 << (g_probe_info.interval - 1);
++#endif
++	if (usb->speed == USB_SPEED_SUPER) {
++		g_probe_info.device_speed = SUPER_SPEED;
++		DBUSERR(("super speed device detected\n"));
++	} else if (usb->speed == USB_SPEED_HIGH) {
++		g_probe_info.device_speed = HIGH_SPEED;
++		DBUSERR(("high speed device detected\n"));
++	} else {
++		g_probe_info.device_speed = FULL_SPEED;
++		DBUSERR(("full speed device detected\n"));
++	}
++	if (g_probe_info.dereged == FALSE && probe_cb) {
++		disc_arg = probe_cb(probe_arg, "", USB_BUS, usb->bus->busnum, usb->portnum, 0);
++	}
++
++	g_probe_info.disc_cb_done = FALSE;
++
++#ifdef KERNEL26
++	intf->needs_remote_wakeup = 1;
++#endif /* KERNEL26 */
++	DHD_MUTEX_UNLOCK();
++
++	/* Success */
++#ifdef KERNEL26
++	return DBUS_OK;
++#else
++	usb_inc_dev_use(usb);
++	return &g_probe_info;
++#endif
++
++fail:
++	printf("%s: Exit ret=%d\n", __FUNCTION__, ret);
++#ifdef BCMUSBDEV_COMPOSITE
++	if (ret != BCME_UNSUPPORTED)
++#endif /* BCMUSBDEV_COMPOSITE */
++		DBUSERR(("%s: failed with errno %d\n", __FUNCTION__, ret));
++#ifndef KERNEL26
++	if (claimed)
++#ifdef BCMUSBDEV_COMPOSITE
++		usb_driver_release_interface(&dbus_usbdev, IFPTR(usb, wlan_if));
++#else
++		usb_driver_release_interface(&dbus_usbdev, IFPTR(usb, CONTROL_IF));
++#endif /* BCMUSBDEV_COMPOSITE */
++#endif /* !KERNEL26 */
++
++	DHD_MUTEX_UNLOCK();
++#ifdef KERNEL26
++	usb_set_intfdata(intf, NULL);
++	return ret;
++#else
++	return NULL;
++#endif
++} /* dbus_usbos_probe */
++
++/** Called by Linux kernel, is the counter part of dbus_usbos_probe() */
++DBUS_USBOS_DISCONNECT()
++{
++#ifdef KERNEL26
++	struct usb_device *usb = interface_to_usbdev(intf);
++	probe_info_t *probe_usb_init_data = usb_get_intfdata(intf);
++#else
++	probe_info_t *probe_usb_init_data = (probe_info_t *) ptr;
++#endif
++	usbos_info_t *usbos_info;
++
++	DHD_MUTEX_LOCK();
++
++	DBUSERR(("%s: bus num(busnum)=%d, slot num (portnum)=%d\n", __FUNCTION__,
++		usb->bus->busnum, usb->portnum));
++
++	if (probe_usb_init_data) {
++		usbos_info = (usbos_info_t *) probe_usb_init_data->usbos_info;
++		if (usbos_info) {
++			if ((probe_usb_init_data->dereged == FALSE) && disconnect_cb && disc_arg) {
++				disconnect_cb(disc_arg);
++				disc_arg = NULL;
++				probe_usb_init_data->disc_cb_done = TRUE;
++			}
++		}
++	}
++
++	if (usb) {
++#ifndef KERNEL26
++#ifdef BCMUSBDEV_COMPOSITE
++		usb_driver_release_interface(&dbus_usbdev, IFPTR(usb, wlan_if));
++#else
++		usb_driver_release_interface(&dbus_usbdev, IFPTR(usb, CONTROL_IF));
++#endif /* BCMUSBDEV_COMPOSITE */
++		usb_dec_dev_use(usb);
++#endif /* !KERNEL26 */
++	}
++	DHD_MUTEX_UNLOCK();
++} /* dbus_usbos_disconnect */
++
++#define LOOPBACK_PKT_START 0xBABE1234
++
++bool is_loopback_pkt(void *buf)
++{
++
++	uint32 *buf_ptr = (uint32 *) buf;
++
++	if (*buf_ptr == LOOPBACK_PKT_START)
++		return TRUE;
++	return FALSE;
++
++}
++
++int matches_loopback_pkt(void *buf)
++{
++	int i, j;
++	unsigned char *cbuf = (unsigned char *) buf;
++
++	for (i = 4; i < loopback_size; i++) {
++		if (cbuf[i] != (i % 256)) {
++			printf("%s: mismatch at i=%d %d : ", __FUNCTION__, i, cbuf[i]);
++			for (j = i; ((j < i+ 16) && (j < loopback_size)); j++) {
++				printf("%d ", cbuf[j]);
++			}
++			printf("\n");
++			return 0;
++		}
++	}
++	loopback_rx_cnt++;
++	return 1;
++}
++
++int dbus_usbos_loopback_tx(void *usbos_info_ptr, int cnt, int size)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) usbos_info_ptr;
++	unsigned char *buf;
++	int j;
++	void* p = NULL;
++	int rc, last_rx_cnt;
++	int tx_failed_cnt;
++	int max_size = 1650;
++	int usb_packet_size = 512;
++	int min_packet_size = 10;
++
++	if (size % usb_packet_size == 0) {
++		size = size - 1;
++		DBUSERR(("%s: overriding size=%d \n", __FUNCTION__, size));
++	}
++
++	if (size < min_packet_size) {
++		size = min_packet_size;
++		DBUSERR(("%s: overriding size=%d\n", __FUNCTION__, min_packet_size));
++	}
++	if (size > max_size) {
++		size = max_size;
++		DBUSERR(("%s: overriding size=%d\n", __FUNCTION__, max_size));
++	}
++
++	loopback_tx_cnt = 0;
++	loopback_rx_cnt = 0;
++	tx_failed_cnt = 0;
++	loopback_size   = size;
++
++	while (loopback_tx_cnt < cnt) {
++		uint32 *x;
++		int pkt_size = loopback_size;
++
++		p = PKTGET(usbos_info->pub->osh, pkt_size, TRUE);
++		if (p == NULL) {
++			DBUSERR(("%s:%d Failed to allocate packet sz=%d\n",
++			       __FUNCTION__, __LINE__, pkt_size));
++			return BCME_ERROR;
++		}
++		x = (uint32*) PKTDATA(usbos_info->pub->osh, p);
++		*x = LOOPBACK_PKT_START;
++		buf = (unsigned char*) x;
++		for (j = 4; j < pkt_size; j++) {
++			buf[j] = j % 256;
++		}
++		rc = dbus_send_buf(usbos_info->pub, buf, pkt_size, p);
++		if (rc != BCME_OK) {
++			DBUSERR(("%s:%d Freeing packet \n", __FUNCTION__, __LINE__));
++			PKTFREE(usbos_info->pub->osh, p, TRUE);
++			dbus_usbos_wait(usbos_info, 1);
++			tx_failed_cnt++;
++		} else {
++			loopback_tx_cnt++;
++			tx_failed_cnt = 0;
++		}
++		if (tx_failed_cnt == 5) {
++			DBUSERR(("%s : Failed to send loopback packets cnt=%d loopback_tx_cnt=%d\n",
++			 __FUNCTION__, cnt, loopback_tx_cnt));
++			break;
++		}
++	}
++	printf("Transmitted %d loopback packets of size %d\n", loopback_tx_cnt, loopback_size);
++
++	last_rx_cnt = loopback_rx_cnt;
++	while (loopback_rx_cnt < loopback_tx_cnt) {
++		dbus_usbos_wait(usbos_info, 1);
++		if (loopback_rx_cnt <= last_rx_cnt) {
++			DBUSERR(("%s: Matched rx cnt stuck at %d \n", __FUNCTION__, last_rx_cnt));
++			return BCME_ERROR;
++		}
++		last_rx_cnt = loopback_rx_cnt;
++	}
++	printf("Received %d loopback packets of size %d\n", loopback_tx_cnt, loopback_size);
++
++	return BCME_OK;
++} /* dbus_usbos_loopback_tx */
++
++/**
++ * Higher layer (dbus_usb.c) wants to transmit an I/O Request Block
++ *     @param[in] txirb txirb->pkt, if non-zero, contains a single or a chain of packets
++ */
++static int
++dbus_usbos_intf_send_irb(void *bus, dbus_irb_tx_t *txirb)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++	urb_req_t *req, *req_zlp = NULL;
++	int ret = DBUS_OK;
++	unsigned long flags;
++	void *pkt;
++	uint32 buffer_length;
++	uint8 *buf;
++
++	if ((usbos_info == NULL) || !usbos_info->tx_pipe) {
++		return DBUS_ERR;
++	}
++
++	if (txirb->pkt != NULL) {
++		buffer_length = pkttotlen(usbos_info->pub->osh, txirb->pkt);
++		/* In case of multiple packets the values below may be overwritten */
++		txirb->send_buf = NULL;
++		buf = PKTDATA(usbos_info->pub->osh, txirb->pkt);
++	} else { /* txirb->buf != NULL */
++		ASSERT(txirb->buf != NULL);
++		ASSERT(txirb->send_buf == NULL);
++		buffer_length = txirb->len;
++		buf = txirb->buf;
++	}
++
++	if (!(req = dbus_usbos_qdeq(&usbos_info->req_txfreeq, &usbos_info->txfree_lock))) {
++		DBUSERR(("%s No free URB!\n", __FUNCTION__));
++		return DBUS_ERR_TXDROP;
++	}
++
++	/* If not using standard Linux kernel functionality for handling Zero Length Packet(ZLP),
++	 * the dbus needs to generate ZLP when length is multiple of MaxPacketSize.
++	 */
++#ifndef WL_URB_ZPKT
++	if (!(buffer_length % usbos_info->maxps)) {
++		if (!(req_zlp =
++			dbus_usbos_qdeq(&usbos_info->req_txfreeq, &usbos_info->txfree_lock))) {
++			DBUSERR(("%s No free URB for ZLP!\n", __FUNCTION__));
++			dbus_usbos_qenq(&usbos_info->req_txfreeq, req, &usbos_info->txfree_lock);
++			return DBUS_ERR_TXDROP;
++		}
++
++		/* No txirb, so that dbus_usbos_send_complete can differentiate between
++		 * DATA and ZLP.
++		 */
++		req_zlp->arg = NULL;
++		req_zlp->usbinfo = usbos_info;
++		req_zlp->buf_len = 0;
++
++		usb_fill_bulk_urb(req_zlp->urb, usbos_info->usb, usbos_info->tx_pipe, NULL,
++			0, (usb_complete_t)dbus_usbos_send_complete, req_zlp);
++
++		req_zlp->urb->transfer_flags |= URB_QUEUE_BULK;
++	}
++#endif /* !WL_URB_ZPKT */
++
++#ifndef USBOS_TX_THREAD
++	/* Disable USB autosuspend until this request completes, request USB resume if needed.
++	 * Because this call runs asynchronously, there is no guarantee the bus is resumed before
++	 * the URB is submitted, and the URB might be dropped. Use USBOS_TX_THREAD to avoid
++	 * this.
++	 */
++	USB_AUTOPM_GET_INTERFACE_ASYNC(g_probe_info.intf);
++#endif /* !USBOS_TX_THREAD */
++
++	spin_lock_irqsave(&usbos_info->txlock, flags);
++
++	req->arg = txirb;
++	req->usbinfo = usbos_info;
++	req->buf_len = 0;
++
++	/* Prepare the URB */
++	if (txirb->pkt != NULL) {
++		uint32 pktlen;
++		uint8 *transfer_buf;
++
++		/* For multiple packets, allocate contiguous buffer and copy packet data to it */
++		if (PKTNEXT(usbos_info->pub->osh, txirb->pkt)) {
++			transfer_buf = MALLOC(usbos_info->pub->osh, buffer_length);
++			if (!transfer_buf) {
++				ret = DBUS_ERR_TXDROP;
++				DBUSERR(("fail to alloc to usb buffer\n"));
++				goto fail;
++			}
++
++			pkt = txirb->pkt;
++			txirb->send_buf = transfer_buf;
++			req->buf_len = buffer_length;
++
++			while (pkt) {
++				pktlen = PKTLEN(usbos_info->pub->osh, pkt);
++				bcopy(PKTDATA(usbos_info->pub->osh, pkt), transfer_buf, pktlen);
++				transfer_buf += pktlen;
++				pkt = PKTNEXT(usbos_info->pub->osh, pkt);
++			}
++
++			ASSERT(((uint8 *) txirb->send_buf + buffer_length) == transfer_buf);
++
++			/* Overwrite buf pointer with pointer to allocated contiguous transfer_buf
++			 */
++			buf = txirb->send_buf;
++		}
++	}
++
++	usb_fill_bulk_urb(req->urb, usbos_info->usb, usbos_info->tx_pipe, buf,
++		buffer_length, (usb_complete_t)dbus_usbos_send_complete, req);
++
++	req->urb->transfer_flags |= URB_QUEUE_BULK;
++
++#ifdef USBOS_TX_THREAD
++	/* Enqueue TX request, the TX thread will resume the bus if needed and submit
++	 * it asynchronously
++	 */
++	dbus_usbos_qenq(&usbos_info->usbos_tx_list, req, &usbos_info->usbos_tx_list_lock);
++	if (req_zlp != NULL) {
++		dbus_usbos_qenq(&usbos_info->usbos_tx_list, req_zlp,
++			&usbos_info->usbos_tx_list_lock);
++	}
++	spin_unlock_irqrestore(&usbos_info->txlock, flags);
++
++	wake_up_interruptible(&usbos_info->usbos_tx_queue_head);
++	return DBUS_OK;
++#else
++	if ((ret = USB_SUBMIT_URB(req->urb))) {
++		ret = DBUS_ERR_TXDROP;
++		goto fail;
++	}
++
++	dbus_usbos_qenq(&usbos_info->req_txpostedq, req, &usbos_info->txposted_lock);
++	atomic_inc(&usbos_info->txposted);
++
++	if (req_zlp != NULL) {
++		if ((ret = USB_SUBMIT_URB(req_zlp->urb))) {
++			DBUSERR(("failed to submit ZLP URB!\n"));
++			ASSERT(0);
++			ret = DBUS_ERR_TXDROP;
++			goto fail2;
++		}
++
++		dbus_usbos_qenq(&usbos_info->req_txpostedq, req_zlp, &usbos_info->txposted_lock);
++		/* Also increment txposted for zlp packet, as it will be decremented in
++		 * dbus_usbos_send_complete()
++		 */
++		atomic_inc(&usbos_info->txposted);
++	}
++
++	spin_unlock_irqrestore(&usbos_info->txlock, flags);
++	return DBUS_OK;
++#endif /* USBOS_TX_THREAD */
++
++fail:
++	if (txirb->send_buf != NULL) {
++		MFREE(usbos_info->pub->osh, txirb->send_buf, req->buf_len);
++		txirb->send_buf = NULL;
++		req->buf_len = 0;
++	}
++	dbus_usbos_qenq(&usbos_info->req_txfreeq, req, &usbos_info->txfree_lock);
++#ifndef USBOS_TX_THREAD
++fail2:
++#endif
++	if (req_zlp != NULL) {
++		dbus_usbos_qenq(&usbos_info->req_txfreeq, req_zlp, &usbos_info->txfree_lock);
++	}
++
++	spin_unlock_irqrestore(&usbos_info->txlock, flags);
++
++#ifndef USBOS_TX_THREAD
++	USB_AUTOPM_PUT_INTERFACE_ASYNC(g_probe_info.intf);
++#endif /* !USBOS_TX_THREAD */
++
++	return ret;
++} /* dbus_usbos_intf_send_irb */
++
++/** Higher layer (dbus_usb.c) recycles a received (and used) packet. */
++static int
++dbus_usbos_intf_recv_irb(void *bus, dbus_irb_rx_t *rxirb)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++	int ret = DBUS_OK;
++
++	if (usbos_info == NULL)
++		return DBUS_ERR;
++
++	ret = dbus_usbos_recv_urb_submit(usbos_info, rxirb, 0);
++	return ret;
++}
++
++static int
++dbus_usbos_intf_recv_irb_from_ep(void *bus, dbus_irb_rx_t *rxirb, uint32 ep_idx)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++	int ret = DBUS_OK;
++
++	if (usbos_info == NULL)
++		return DBUS_ERR;
++
++#ifdef INTR_EP_ENABLE
++		/* By specifying the ep_idx value of 0xff, the cdc layer is asking to
++		* submit an interrupt URB
++		*/
++		if (rxirb == NULL && ep_idx == 0xff) {
++			/* submit intr URB */
++			if ((ret = USB_SUBMIT_URB(usbos_info->intr_urb)) < 0) {
++				DBUSERR(("%s intr USB_SUBMIT_URB failed, status %d\n",
++					__FUNCTION__, ret));
++			}
++			return ret;
++		}
++#else
++		if (rxirb == NULL) {
++			return DBUS_ERR;
++		}
++#endif /* INTR_EP_ENABLE */
++
++	ret = dbus_usbos_recv_urb_submit(usbos_info, rxirb, ep_idx);
++	return ret;
++}
++
++/** Higher layer (dbus_usb.c) want to cancel an IRB */
++static int
++dbus_usbos_intf_cancel_irb(void *bus, dbus_irb_tx_t *txirb)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++
++	if (usbos_info == NULL)
++		return DBUS_ERR;
++
++	return DBUS_ERR;
++}
++
++/** Only one CTL transfer can be pending at any time. This function may block. */
++static int
++dbus_usbos_intf_send_ctl(void *bus, uint8 *buf, int len)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++	uint16 size;
++#ifndef USBOS_TX_THREAD
++	int status;
++#endif /* USBOS_TX_THREAD */
++
++	if ((usbos_info == NULL) || (buf == NULL) || (len == 0))
++		return DBUS_ERR;
++
++	if (usbos_info->ctl_urb == NULL)
++		return DBUS_ERR;
++
++	/* Block until a pending CTL transfer has completed */
++	if (down_interruptible(&usbos_info->ctl_lock) != 0) {
++		return DBUS_ERR_TXCTLFAIL;
++	}
++
++#ifdef USBOS_TX_THREAD
++	ASSERT(usbos_info->ctl_state == USBOS_REQUEST_STATE_UNSCHEDULED);
++#else
++	/* Disable USB autosuspend until this request completes, request USB resume if needed.
++	 * Because this call runs asynchronously, there is no guarantee the bus is resumed before
++	 * the URB is submitted, and the URB might be dropped. Use USBOS_TX_THREAD to avoid
++	 * this.
++	 */
++	USB_AUTOPM_GET_INTERFACE_ASYNC(g_probe_info.intf);
++#endif /* USBOS_TX_THREAD */
++
++	size = len;
++	usbos_info->ctl_write.wLength = cpu_to_le16p(&size);
++	usbos_info->ctl_urb->transfer_buffer_length = size;
++
++	usb_fill_control_urb(usbos_info->ctl_urb,
++		usbos_info->usb,
++		usb_sndctrlpipe(usbos_info->usb, 0),
++		(unsigned char *) &usbos_info->ctl_write,
++		buf, size, (usb_complete_t)dbus_usbos_ctlwrite_complete, usbos_info);
++
++#ifdef USBOS_TX_THREAD
++	/* Enqueue CTRL request for transmission by the TX thread. The
++	 * USB bus will first be resumed if needed.
++	 */
++	usbos_info->ctl_state = USBOS_REQUEST_STATE_SCHEDULED;
++	wake_up_interruptible(&usbos_info->usbos_tx_queue_head);
++#else
++	status = USB_SUBMIT_URB(usbos_info->ctl_urb);
++	if (status < 0) {
++		DBUSERR(("%s: usb_submit_urb failed %d\n", __FUNCTION__, status));
++		up(&usbos_info->ctl_lock);
++
++		USB_AUTOPM_PUT_INTERFACE_ASYNC(g_probe_info.intf);
++
++		return DBUS_ERR_TXCTLFAIL;
++	}
++#endif /* USBOS_TX_THREAD */
++
++	return DBUS_OK;
++} /* dbus_usbos_intf_send_ctl */
++
++/** This function does not seem to be called by anyone, including dbus_usb.c */
++static int
++dbus_usbos_intf_recv_ctl(void *bus, uint8 *buf, int len)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++	int status;
++	uint16 size;
++
++	if ((usbos_info == NULL) || (buf == NULL) || (len == 0))
++		return DBUS_ERR;
++
++	if (usbos_info->ctl_urb == NULL)
++		return DBUS_ERR;
++
++	/* Block until a pending CTRL transfer has completed */
++	if (down_interruptible(&usbos_info->ctl_lock) != 0) {
++		return DBUS_ERR_TXCTLFAIL;
++	}
++
++	/* Disable USB autosuspend until this request completes, request USB resume if needed. */
++	USB_AUTOPM_GET_INTERFACE_ASYNC(g_probe_info.intf);
++
++	size = len;
++	usbos_info->ctl_read.wLength = cpu_to_le16p(&size);
++	usbos_info->ctl_urb->transfer_buffer_length = size;
++
++	if (usbos_info->rxctl_deferrespok) {
++		/* BMAC model */
++		usbos_info->ctl_read.bRequestType = USB_DIR_IN | USB_TYPE_VENDOR |
++			USB_RECIP_INTERFACE;
++		usbos_info->ctl_read.bRequest = DL_DEFER_RESP_OK;
++	} else {
++		/* full dongle model */
++		usbos_info->ctl_read.bRequestType = USB_DIR_IN | USB_TYPE_CLASS |
++			USB_RECIP_INTERFACE;
++		usbos_info->ctl_read.bRequest = 1;
++	}
++
++	usb_fill_control_urb(usbos_info->ctl_urb,
++		usbos_info->usb,
++		usb_rcvctrlpipe(usbos_info->usb, 0),
++		(unsigned char *) &usbos_info->ctl_read,
++		buf, size, (usb_complete_t)dbus_usbos_ctlread_complete, usbos_info);
++
++	status = USB_SUBMIT_URB(usbos_info->ctl_urb);
++	if (status < 0) {
++		DBUSERR(("%s: usb_submit_urb failed %d\n", __FUNCTION__, status));
++		up(&usbos_info->ctl_lock);
++
++		USB_AUTOPM_PUT_INTERFACE_ASYNC(g_probe_info.intf);
++
++		return DBUS_ERR_RXCTLFAIL;
++	}
++
++	return DBUS_OK;
++}
++
++static int
++dbus_usbos_intf_get_attrib(void *bus, dbus_attrib_t *attrib)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++
++	if ((usbos_info == NULL) || (attrib == NULL))
++		return DBUS_ERR;
++
++	attrib->bustype = DBUS_USB;
++	attrib->vid = g_probe_info.vid;
++	attrib->pid = g_probe_info.pid;
++	attrib->devid = 0x4322;
++
++	attrib->nchan = 1;
++
++	/* MaxPacketSize for USB hi-speed bulk out is 512 bytes
++	 * and 64-bytes for full-speed.
++	 * When sending pkt > MaxPacketSize, Host SW breaks it
++	 * up into multiple packets.
++	 */
++	attrib->mtu = usbos_info->maxps;
++
++	return DBUS_OK;
++}
++
++/** Called by higher layer (dbus_usb.c) when it wants to 'up' the USB interface to the dongle */
++static int
++dbus_usbos_intf_up(void *bus)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++	uint16 ifnum;
++#ifdef BCMUSBDEV_COMPOSITE
++	int wlan_if = 0;
++#endif
++	if (usbos_info == NULL)
++		return DBUS_ERR;
++
++	if (usbos_info->usb == NULL)
++		return DBUS_ERR;
++
++#if defined(INTR_EP_ENABLE)
++	/* full dongle use intr EP, bmac doesn't use it */
++	if (usbos_info->intr_urb) {
++		int ret;
++
++		usb_fill_int_urb(usbos_info->intr_urb, usbos_info->usb,
++			usbos_info->intr_pipe, &usbos_info->intr,
++			usbos_info->intr_size, (usb_complete_t)dbus_usbos_intr_complete,
++			usbos_info, usbos_info->interval);
++
++		if ((ret = USB_SUBMIT_URB(usbos_info->intr_urb))) {
++			DBUSERR(("%s USB_SUBMIT_URB failed with status %d\n", __FUNCTION__, ret));
++			return DBUS_ERR;
++		}
++	}
++#endif	
++
++	if (usbos_info->ctl_urb) {
++		usbos_info->ctl_in_pipe = usb_rcvctrlpipe(usbos_info->usb, 0);
++		usbos_info->ctl_out_pipe = usb_sndctrlpipe(usbos_info->usb, 0);
++
++#ifdef BCMUSBDEV_COMPOSITE
++		wlan_if = dbus_usbos_intf_wlan(usbos_info->usb);
++		ifnum = cpu_to_le16(IFDESC(usbos_info->usb, wlan_if).bInterfaceNumber);
++#else
++		ifnum = cpu_to_le16(IFDESC(usbos_info->usb, CONTROL_IF).bInterfaceNumber);
++#endif /* BCMUSBDEV_COMPOSITE */
++		/* CTL Write */
++		usbos_info->ctl_write.bRequestType =
++			USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE;
++		usbos_info->ctl_write.bRequest = 0;
++		usbos_info->ctl_write.wValue = cpu_to_le16(0);
++		usbos_info->ctl_write.wIndex = cpu_to_le16p(&ifnum);
++
++		/* CTL Read */
++		usbos_info->ctl_read.bRequestType =
++			USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE;
++		usbos_info->ctl_read.bRequest = 1;
++		usbos_info->ctl_read.wValue = cpu_to_le16(0);
++		usbos_info->ctl_read.wIndex = cpu_to_le16p(&ifnum);
++	}
++
++	/* Success, indicate usbos_info is fully up */
++	dbus_usbos_state_change(usbos_info, DBUS_STATE_UP);
++
++	return DBUS_OK;
++} /* dbus_usbos_intf_up */
++
++static int
++dbus_usbos_intf_down(void *bus)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++
++	if (usbos_info == NULL)
++		return DBUS_ERR;
++
++	dbusos_stop(usbos_info);
++	return DBUS_OK;
++}
++
++static int
++dbus_usbos_intf_stop(void *bus)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++
++	if (usbos_info == NULL)
++		return DBUS_ERR;
++
++	dbusos_stop(usbos_info);
++	return DBUS_OK;
++}
++
++
++/** Called by higher layer (dbus_usb.c) */
++static int
++dbus_usbos_intf_set_config(void *bus, dbus_config_t *config)
++{
++	int err = DBUS_ERR;
++	usbos_info_t* usbos_info = bus;
++
++	if (config->config_id == DBUS_CONFIG_ID_RXCTL_DEFERRES) {
++		usbos_info->rxctl_deferrespok = config->rxctl_deferrespok;
++		err = DBUS_OK;
++	} else if (config->config_id == DBUS_CONFIG_ID_AGGR_LIMIT) {
++		/* DBUS_CONFIG_ID_AGGR_LIMIT shouldn't be called after probe stage */
++		ASSERT(disc_arg == NULL);
++		ASSERT(config->aggr_param.maxrxsf > 0);
++		ASSERT(config->aggr_param.maxrxsize > 0);
++		if (config->aggr_param.maxrxsize > usbos_info->rxbuf_len) {
++			int state = usbos_info->pub->busstate;
++			dbus_usbos_unlink(&usbos_info->req_rxpostedq, &usbos_info->rxposted_lock);
++			while (atomic_read(&usbos_info->rxposted)) {
++				DBUSTRACE(("%s rxposted is %d, delay 1 ms\n", __FUNCTION__,
++					atomic_read(&usbos_info->rxposted)));
++				dbus_usbos_wait(usbos_info, 1);
++			}
++			usbos_info->rxbuf_len = config->aggr_param.maxrxsize;
++			dbus_usbos_state_change(usbos_info, state);
++		}
++		err = DBUS_OK;
++	}
++
++	return err;
++}
++
++
++/** Called by dbus_usb.c when it wants to download firmware into the dongle */
++bool
++dbus_usbos_dl_cmd(usbos_info_t *usbinfo, uint8 cmd, void *buffer, int buflen)
++{
++	int transferred;
++	int index = 0;
++	char *tmpbuf;
++
++	if ((usbinfo == NULL) || (buffer == NULL) || (buflen == 0))
++		return FALSE;
++
++	tmpbuf = (char *) MALLOC(usbinfo->pub->osh, buflen);
++	if (!tmpbuf) {
++		DBUSERR(("%s: Unable to allocate memory \n", __FUNCTION__));
++		return FALSE;
++	}
++
++#ifdef BCM_REQUEST_FW
++	if (cmd == DL_GO) {
++		index = 1;
++	}
++#endif
++
++	/* Disable USB autosuspend until this request completes, request USB resume if needed. */
++	USB_AUTOPM_GET_INTERFACE(g_probe_info.intf);
++
++	transferred = USB_CONTROL_MSG(usbinfo->usb, usb_rcvctrlpipe(usbinfo->usb, 0),
++		cmd, (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_INTERFACE),
++		0, index,
++		(void*) tmpbuf, buflen, USB_CTRL_EP_TIMEOUT);
++	if (transferred == buflen) {
++		memcpy(buffer, tmpbuf, buflen);
++	} else {
++		DBUSERR(("%s: usb_control_msg failed %d\n", __FUNCTION__, transferred));
++	}
++
++	USB_AUTOPM_PUT_INTERFACE(g_probe_info.intf);
++
++	MFREE(usbinfo->pub->osh, tmpbuf, buflen);
++	return (transferred == buflen);
++}
++
++/**
++ * Called by dbus_usb.c when it wants to download a buffer into the dongle (e.g. as part of the
++ * download process, when writing nvram variables).
++ */
++int
++dbus_write_membytes(usbos_info_t* usbinfo, bool set, uint32 address, uint8 *data, uint size)
++{
++	hwacc_t hwacc;
++	int write_bytes = 4;
++	int status;
++	int retval = 0;
++
++	DBUSTRACE(("Enter:%s\n", __FUNCTION__));
++
++	/* Read is not supported */
++	if (set == 0) {
++		DBUSERR(("Currently read is not supported!!\n"));
++		return -1;
++	}
++
++	USB_AUTOPM_GET_INTERFACE(g_probe_info.intf);
++
++	hwacc.cmd = DL_CMD_WRHW;
++	hwacc.addr = address;
++
++	DBUSTRACE(("Address:%x size:%d", hwacc.addr, size));
++	do {
++		if (size >= 4) {
++			write_bytes = 4;
++		} else if (size >= 2) {
++			write_bytes = 2;
++		} else {
++			write_bytes = 1;
++		}
++
++		hwacc.len = write_bytes;
++
++		while (size >= write_bytes) {
++			hwacc.data = *((unsigned int*)data);
++
++			status = USB_CONTROL_MSG(usbinfo->usb, usb_sndctrlpipe(usbinfo->usb, 0),
++				DL_WRHW, (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_INTERFACE),
++				1, 0, (char *)&hwacc, sizeof(hwacc_t), USB_CTRL_EP_TIMEOUT);
++
++			if (status < 0) {
++				retval = -1;
++				DBUSERR((" Ctrl write hwacc failed w/status %d @ address:%x \n",
++					status, hwacc.addr));
++				goto err;
++			}
++
++			hwacc.addr += write_bytes;
++			data += write_bytes;
++			size -= write_bytes;
++		}
++	} while (size > 0);
++
++err:
++	USB_AUTOPM_PUT_INTERFACE(g_probe_info.intf);
++
++	return retval;
++}
++
++int
++dbus_usbos_readreg(void *bus, uint32 regaddr, int datalen, uint32 *value)
++{
++	usbos_info_t *usbinfo = (usbos_info_t *) bus;
++	int ret = DBUS_OK;
++	int transferred;
++	uint32 cmd;
++	hwacc_t	hwacc;
++
++	if (usbinfo == NULL)
++		return DBUS_ERR;
++
++	if (datalen == 1)
++		cmd = DL_RDHW8;
++	else if (datalen == 2)
++		cmd = DL_RDHW16;
++	else
++		cmd = DL_RDHW32;
++
++	USB_AUTOPM_GET_INTERFACE(g_probe_info.intf);
++
++	transferred = USB_CONTROL_MSG(usbinfo->usb, usb_rcvctrlpipe(usbinfo->usb, 0),
++		cmd, (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_INTERFACE),
++		(uint16)(regaddr), (uint16)(regaddr >> 16),
++		(void *) &hwacc, sizeof(hwacc_t), USB_CTRL_EP_TIMEOUT);
++
++	if (transferred >= sizeof(hwacc_t)) {
++		*value = hwacc.data;
++	} else {
++		DBUSERR(("%s: usb_control_msg failed %d\n", __FUNCTION__, transferred));
++		ret = DBUS_ERR;
++	}
++
++	USB_AUTOPM_PUT_INTERFACE(g_probe_info.intf);
++
++	return ret;
++}
++
++int
++dbus_usbos_writereg(void *bus, uint32 regaddr, int datalen, uint32 data)
++{
++	usbos_info_t *usbinfo = (usbos_info_t *) bus;
++	int ret = DBUS_OK;
++	int transferred;
++	uint32 cmd = DL_WRHW;
++	hwacc_t	hwacc;
++
++	if (usbinfo == NULL)
++		return DBUS_ERR;
++
++	USB_AUTOPM_GET_INTERFACE(g_probe_info.intf);
++
++	hwacc.cmd = DL_WRHW;
++	hwacc.addr = regaddr;
++	hwacc.data = data;
++	hwacc.len = datalen;
++
++	transferred = USB_CONTROL_MSG(usbinfo->usb, usb_sndctrlpipe(usbinfo->usb, 0),
++		cmd, (USB_DIR_OUT| USB_TYPE_VENDOR | USB_RECIP_INTERFACE),
++		1, 0,
++		(void *) &hwacc, sizeof(hwacc_t), USB_CTRL_EP_TIMEOUT);
++
++	if (transferred != sizeof(hwacc_t)) {
++		DBUSERR(("%s: usb_control_msg failed %d\n", __FUNCTION__, transferred));
++		ret = DBUS_ERR;
++	}
++
++	USB_AUTOPM_PUT_INTERFACE(g_probe_info.intf);
++
++	return ret;
++}
++
++int
++dbus_usbos_wait(usbos_info_t *usbinfo, uint16 ms)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++	if (in_interrupt())
++		mdelay(ms);
++	else
++		msleep_interruptible(ms);
++#else
++	wait_ms(ms);
++#endif
++	return DBUS_OK;
++}
++
++/** Called by dbus_usb.c as part of the firmware download process */
++bool
++dbus_usbos_dl_send_bulk(usbos_info_t *usbinfo, void *buffer, int len)
++{
++	bool ret = TRUE;
++	int status;
++	int transferred = 0;
++
++	if (usbinfo == NULL)
++		return DBUS_ERR;
++
++	USB_AUTOPM_GET_INTERFACE(g_probe_info.intf);
++
++	status = USB_BULK_MSG(usbinfo->usb, usbinfo->tx_pipe,
++		buffer, len,
++		&transferred, USB_BULK_EP_TIMEOUT);
++
++	if (status < 0) {
++		DBUSERR(("%s: usb_bulk_msg failed %d\n", __FUNCTION__, status));
++		ret = FALSE;
++	}
++
++	USB_AUTOPM_PUT_INTERFACE(g_probe_info.intf);
++
++	return ret;
++}
++
++static bool
++dbus_usbos_intf_recv_needed(void *bus)
++{
++	return FALSE;
++}
++
++/**
++ * Higher layer (dbus_usb.c) wants to execute a function on the condition that the rx spin lock has
++ * been acquired.
++ */
++static void*
++dbus_usbos_intf_exec_rxlock(void *bus, exec_cb_t cb, struct exec_parms *args)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++	void *ret;
++	unsigned long flags;
++
++	if (usbos_info == NULL)
++		return NULL;
++
++	spin_lock_irqsave(&usbos_info->rxlock, flags);
++	ret = cb(args);
++	spin_unlock_irqrestore(&usbos_info->rxlock, flags);
++
++	return ret;
++}
++
++static void*
++dbus_usbos_intf_exec_txlock(void *bus, exec_cb_t cb, struct exec_parms *args)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++	void *ret;
++	unsigned long flags;
++
++	if (usbos_info == NULL)
++		return NULL;
++
++	spin_lock_irqsave(&usbos_info->txlock, flags);
++	ret = cb(args);
++	spin_unlock_irqrestore(&usbos_info->txlock, flags);
++
++	return ret;
++}
++
++/**
++ * if an error condition was detected in this module, the higher DBUS layer (dbus_usb.c) has to
++ * be notified.
++ */
++int
++dbus_usbos_errhandler(void *bus, int err)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++
++	if (usbos_info == NULL)
++		return DBUS_ERR;
++
++	if (usbos_info->cbarg && usbos_info->cbs) {
++		if (usbos_info->cbs->errhandler)
++			usbos_info->cbs->errhandler(usbos_info->cbarg, err);
++	}
++
++	return DBUS_OK;
++}
++
++/**
++ * if a change in bus state was detected in this module, the higher DBUS layer (dbus_usb.c) has to
++ * be notified.
++ */
++int
++dbus_usbos_state_change(void *bus, int state)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++
++	if (usbos_info == NULL)
++		return DBUS_ERR;
++
++	if (usbos_info->cbarg && usbos_info->cbs) {
++		if (usbos_info->cbs->state_change)
++			usbos_info->cbs->state_change(usbos_info->cbarg, state);
++	}
++
++	usbos_info->pub->busstate = state;
++	return DBUS_OK;
++}
++
++int
++dbus_bus_osl_register(int vid, int pid, probe_cb_t prcb,
++	disconnect_cb_t discb, void *prarg, dbus_intf_t **intf, void *param1, void *param2)
++{
++	bzero(&g_probe_info, sizeof(probe_info_t));
++
++	probe_cb = prcb;
++	disconnect_cb = discb;
++	probe_arg = prarg;
++
++	devid_table[0].idVendor = vid;
++	devid_table[0].idProduct = pid;
++
++	*intf = &dbus_usbos_intf;
++
++	USB_REGISTER();
++
++	return DBUS_ERR_NODEVICE;
++}
++
++int
++dbus_bus_osl_deregister()
++{
++	g_probe_info.dereged = TRUE;
++
++	DHD_MUTEX_LOCK();
++	if (disconnect_cb && disc_arg && (g_probe_info.disc_cb_done == FALSE)) {
++		disconnect_cb(disc_arg);
++		disc_arg = NULL;
++	}
++	DHD_MUTEX_UNLOCK();
++
++	USB_DEREGISTER();
++
++	return DBUS_OK;
++}
++
++void *
++dbus_usbos_intf_attach(dbus_pub_t *pub, void *cbarg, dbus_intf_callbacks_t *cbs)
++{
++	usbos_info_t *usbos_info;
++
++	if (g_probe_info.dldone == FALSE) {
++		DBUSERR(("%s: err device not downloaded!\n", __FUNCTION__));
++		return NULL;
++	}
++
++	/* Sanity check for BUS_INFO() */
++	ASSERT(OFFSETOF(usbos_info_t, pub) == 0);
++
++	usbos_info = MALLOC(pub->osh, sizeof(usbos_info_t));
++	if (usbos_info == NULL)
++		return NULL;
++
++	bzero(usbos_info, sizeof(usbos_info_t));
++
++	usbos_info->pub = pub;
++	usbos_info->cbarg = cbarg;
++	usbos_info->cbs = cbs;
++
++	/* Needed for disconnect() */
++	g_probe_info.usbos_info = usbos_info;
++
++	/* Update USB Info */
++	usbos_info->usb = g_probe_info.usb;
++	usbos_info->rx_pipe = g_probe_info.rx_pipe;
++	usbos_info->rx_pipe2 = g_probe_info.rx_pipe2;
++	usbos_info->tx_pipe = g_probe_info.tx_pipe;
++	usbos_info->intr_pipe = g_probe_info.intr_pipe;
++	usbos_info->intr_size = g_probe_info.intr_size;
++	usbos_info->interval = g_probe_info.interval;
++	usbos_info->pub->device_speed = g_probe_info.device_speed;
++	if (usbos_info->rx_pipe2) {
++		usbos_info->pub->attrib.has_2nd_bulk_in_ep = 1;
++	} else {
++		usbos_info->pub->attrib.has_2nd_bulk_in_ep = 0;
++	}
++
++	if (usbos_info->tx_pipe)
++		usbos_info->maxps = usb_maxpacket(usbos_info->usb,
++			usbos_info->tx_pipe, usb_pipeout(usbos_info->tx_pipe));
++
++	INIT_LIST_HEAD(&usbos_info->req_rxfreeq);
++	INIT_LIST_HEAD(&usbos_info->req_txfreeq);
++	INIT_LIST_HEAD(&usbos_info->req_rxpostedq);
++	INIT_LIST_HEAD(&usbos_info->req_txpostedq);
++	spin_lock_init(&usbos_info->rxfree_lock);
++	spin_lock_init(&usbos_info->txfree_lock);
++	spin_lock_init(&usbos_info->rxposted_lock);
++	spin_lock_init(&usbos_info->txposted_lock);
++	spin_lock_init(&usbos_info->rxlock);
++	spin_lock_init(&usbos_info->txlock);
++
++	atomic_set(&usbos_info->rxposted, 0);
++	atomic_set(&usbos_info->txposted, 0);
++
++
++#ifdef USB_DISABLE_INT_EP
++	usbos_info->intr_urb = NULL;
++#else
++	if (!(usbos_info->intr_urb = USB_ALLOC_URB())) {
++		DBUSERR(("%s: usb_alloc_urb (tx) failed\n", __FUNCTION__));
++		goto fail;
++	}
++#endif
++
++	if (!(usbos_info->ctl_urb = USB_ALLOC_URB())) {
++		DBUSERR(("%s: usb_alloc_urb (tx) failed\n", __FUNCTION__));
++		goto fail;
++	}
++
++	init_waitqueue_head(&usbos_info->wait);
++
++	if (!(usbos_info->blk_urb = USB_ALLOC_URB())) {	/* for embedded image downloading */
++		DBUSERR(("%s: usb_alloc_urb (tx) failed\n", __FUNCTION__));
++		goto fail;
++	}
++
++	usbos_info->rxbuf_len = (uint)usbos_info->pub->rxsize;
++
++
++
++	atomic_set(&usbos_info->txallocated, 0);
++	if (DBUS_OK != dbus_usbos_urbreqs_alloc(usbos_info,
++		usbos_info->pub->ntxq, FALSE)) {
++		goto fail;
++	}
++
++	atomic_set(&usbos_info->rxallocated, 0);
++	if (DBUS_OK != dbus_usbos_urbreqs_alloc(usbos_info,
++		MIN(DBUS_USB_RXQUEUE_BATCH_ADD, usbos_info->pub->nrxq),
++		TRUE)) {
++		goto fail;
++	}
++
++	sema_init(&usbos_info->ctl_lock, 1);
++
++#ifdef USBOS_THREAD
++	if (dbus_usbos_thread_init(usbos_info) == NULL)
++		goto fail;
++#endif /* USBOS_THREAD */
++
++#ifdef USBOS_TX_THREAD
++	if (dbus_usbos_tx_thread_init(usbos_info) == NULL)
++		goto fail;
++#endif /* USBOS_TX_THREAD */
++
++	pub->dev_info = g_probe_info.usb;
++
++
++	return (void *) usbos_info;
++fail:
++	if (usbos_info->intr_urb) {
++		USB_FREE_URB(usbos_info->intr_urb);
++		usbos_info->intr_urb = NULL;
++	}
++
++	if (usbos_info->ctl_urb) {
++		USB_FREE_URB(usbos_info->ctl_urb);
++		usbos_info->ctl_urb = NULL;
++	}
++
++#if defined(BCM_REQUEST_FW)
++	if (usbos_info->blk_urb) {
++		USB_FREE_URB(usbos_info->blk_urb);
++		usbos_info->blk_urb = NULL;
++	}
++#endif
++
++	dbus_usbos_urbreqs_free(usbos_info, TRUE);
++	atomic_set(&usbos_info->rxallocated, 0);
++	dbus_usbos_urbreqs_free(usbos_info, FALSE);
++	atomic_set(&usbos_info->txallocated, 0);
++
++	g_probe_info.usbos_info = NULL;
++
++	MFREE(pub->osh, usbos_info, sizeof(usbos_info_t));
++	return NULL;
++} /* dbus_usbos_intf_attach */
++
++void
++dbus_usbos_intf_detach(dbus_pub_t *pub, void *info)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) info;
++	osl_t *osh = pub->osh;
++
++	if (usbos_info == NULL) {
++		return;
++	}
++
++#ifdef USBOS_TX_THREAD
++	dbus_usbos_tx_thread_deinit(usbos_info);
++#endif /* USBOS_TX_THREAD */
++
++	/* Must unlink all URBs prior to driver unload;
++	 * otherwise an URB callback can occur after driver
++	 * has been de-allocated and rmmod'd
++	 */
++	dbusos_stop(usbos_info);
++
++	if (usbos_info->intr_urb) {
++		USB_FREE_URB(usbos_info->intr_urb);
++		usbos_info->intr_urb = NULL;
++	}
++
++	if (usbos_info->ctl_urb) {
++		USB_FREE_URB(usbos_info->ctl_urb);
++		usbos_info->ctl_urb = NULL;
++	}
++
++	if (usbos_info->blk_urb) {
++		USB_FREE_URB(usbos_info->blk_urb);
++		usbos_info->blk_urb = NULL;
++	}
++
++	dbus_usbos_urbreqs_free(usbos_info, TRUE);
++	atomic_set(&usbos_info->rxallocated, 0);
++	dbus_usbos_urbreqs_free(usbos_info, FALSE);
++	atomic_set(&usbos_info->txallocated, 0);
++
++#ifdef USBOS_THREAD
++	dbus_usbos_thread_deinit(usbos_info);
++#endif /* USBOS_THREAD */
++
++	g_probe_info.usbos_info = NULL;
++	MFREE(osh, usbos_info, sizeof(usbos_info_t));
++} /* dbus_usbos_intf_detach */
++
++
++#ifdef USBOS_TX_THREAD
++
++void*
++dbus_usbos_tx_thread_init(usbos_info_t *usbos_info)
++{
++	spin_lock_init(&usbos_info->usbos_tx_list_lock);
++	INIT_LIST_HEAD(&usbos_info->usbos_tx_list);
++	init_waitqueue_head(&usbos_info->usbos_tx_queue_head);
++
++	usbos_info->usbos_tx_kt = kthread_create(dbus_usbos_tx_thread_func,
++		usbos_info, "usb-tx-thread");
++
++	if (IS_ERR(usbos_info->usbos_tx_kt)) {
++		DBUSERR(("Thread Creation failed\n"));
++		return (NULL);
++	}
++
++	usbos_info->ctl_state = USBOS_REQUEST_STATE_UNSCHEDULED;
++	wake_up_process(usbos_info->usbos_tx_kt);
++
++	return (usbos_info->usbos_tx_kt);
++}
++
++void
++dbus_usbos_tx_thread_deinit(usbos_info_t *usbos_info)
++{
++	urb_req_t *req;
++
++	if (usbos_info->usbos_tx_kt) {
++		wake_up_interruptible(&usbos_info->usbos_tx_queue_head);
++		kthread_stop(usbos_info->usbos_tx_kt);
++	}
++
++	/* Move pending requests to free queue so they can be freed */
++	while ((req = dbus_usbos_qdeq(
++		&usbos_info->usbos_tx_list, &usbos_info->usbos_tx_list_lock)) != NULL) {
++		dbus_usbos_qenq(&usbos_info->req_txfreeq, req, &usbos_info->txfree_lock);
++	}
++}
++
++/**
++ * Allow USB in-band resume to block by submitting CTRL and DATA URBs on a separate thread.
++ */
++int
++dbus_usbos_tx_thread_func(void *data)
++{
++	usbos_info_t  *usbos_info = (usbos_info_t *)data;
++	urb_req_t     *req;
++	dbus_irb_tx_t *txirb;
++	int           ret;
++	unsigned long flags;
++
++#ifdef WL_THREADNICE
++	set_user_nice(current, WL_THREADNICE);
++#endif
++
++	while (1) {
++		/* Wait until there are URBs to submit */
++		wait_event_interruptible_timeout(
++			usbos_info->usbos_tx_queue_head,
++			!list_empty(&usbos_info->usbos_tx_list) ||
++			usbos_info->ctl_state == USBOS_REQUEST_STATE_SCHEDULED,
++			100);
++
++		if (kthread_should_stop())
++			break;
++
++		/* Submit CTRL URB if needed */
++		if (usbos_info->ctl_state == USBOS_REQUEST_STATE_SCHEDULED) {
++
++			/* Disable USB autosuspend until this request completes. If the
++			 * interface was suspended, this call blocks until it has been resumed.
++			 */
++			USB_AUTOPM_GET_INTERFACE(g_probe_info.intf);
++
++			usbos_info->ctl_state = USBOS_REQUEST_STATE_SUBMITTED;
++
++			ret = USB_SUBMIT_URB(usbos_info->ctl_urb);
++			if (ret != 0) {
++				DBUSERR(("%s CTRL USB_SUBMIT_URB failed, status %d\n",
++					__FUNCTION__, ret));
++
++				usbos_info->ctl_state = USBOS_REQUEST_STATE_UNSCHEDULED;
++				up(&usbos_info->ctl_lock);
++
++				USB_AUTOPM_PUT_INTERFACE_ASYNC(g_probe_info.intf);
++			}
++		}
++
++		/* Submit all available TX URBs */
++		while ((req = dbus_usbos_qdeq(&usbos_info->usbos_tx_list,
++			&usbos_info->usbos_tx_list_lock)) != NULL) {
++
++			/* Disable USB autosuspend until this request completes. If the
++			 * interface was suspended, this call blocks until it has been resumed.
++			 */
++			USB_AUTOPM_GET_INTERFACE(g_probe_info.intf);
++
++			spin_lock_irqsave(&usbos_info->txlock, flags);
++
++			ret = USB_SUBMIT_URB(req->urb);
++			if (ret == 0) {
++				/* URB submitted successfully */
++				dbus_usbos_qenq(&usbos_info->req_txpostedq, req,
++					&usbos_info->txposted_lock);
++				atomic_inc(&usbos_info->txposted);
++			} else {
++				/* Submitting the URB failed. */
++				DBUSERR(("%s TX USB_SUBMIT_URB failed, status %d\n",
++					__FUNCTION__, ret));
++
++				USB_AUTOPM_PUT_INTERFACE_ASYNC(g_probe_info.intf);
++			}
++
++			spin_unlock_irqrestore(&usbos_info->txlock, flags);
++
++			if (ret != 0) {
++				/* Cleanup and notify higher layers */
++				dbus_usbos_qenq(&usbos_info->req_txfreeq, req,
++					&usbos_info->txfree_lock);
++
++				txirb = req->arg;
++				if (txirb->send_buf) {
++					MFREE(usbos_info->pub->osh, txirb->send_buf, req->buf_len);
++					txirb->send_buf = NULL;
++					req->buf_len = 0;
++				}
++
++				if (likely (usbos_info->cbarg && usbos_info->cbs)) {
++					if (likely (usbos_info->cbs->send_irb_complete != NULL))
++						usbos_info->cbs->send_irb_complete(
++							usbos_info->cbarg, txirb, DBUS_ERR_TXDROP);
++				}
++			}
++		}
++	}
++
++	return 0;
++} /* dbus_usbos_tx_thread_func */
++
++#endif /* USBOS_TX_THREAD */
++
++#ifdef USBOS_THREAD
++
++/**
++ * Increase system performance by creating a USB thread that runs parallel to other system
++ * activity.
++ */
++static void*
++dbus_usbos_thread_init(usbos_info_t *usbos_info)
++{
++	usbos_list_entry_t  *entry;
++	unsigned long       flags, ii;
++
++	spin_lock_init(&usbos_info->usbos_list_lock);
++	spin_lock_init(&usbos_info->ctrl_lock);
++	INIT_LIST_HEAD(&usbos_info->usbos_list);
++	INIT_LIST_HEAD(&usbos_info->usbos_free_list);
++	init_waitqueue_head(&usbos_info->usbos_queue_head);
++	atomic_set(&usbos_info->usbos_list_cnt, 0);
++
++
++	for (ii = 0; ii < (usbos_info->pub->nrxq + usbos_info->pub->ntxq); ii++) {
++		entry = MALLOC(usbos_info->pub->osh, sizeof(usbos_list_entry_t));
++		if (entry) {
++			spin_lock_irqsave(&usbos_info->usbos_list_lock, flags);
++			list_add_tail((struct list_head*) entry, &usbos_info->usbos_free_list);
++			spin_unlock_irqrestore(&usbos_info->usbos_list_lock, flags);
++		} else {
++			DBUSERR(("Failed to create list\n"));
++		}
++	}
++
++	usbos_info->usbos_kt = kthread_create(dbus_usbos_thread_func,
++		usbos_info, "usb-thread");
++
++	if (IS_ERR(usbos_info->usbos_kt)) {
++		DBUSERR(("Thread Creation failed\n"));
++		return (NULL);
++	}
++
++	wake_up_process(usbos_info->usbos_kt);
++
++	return (usbos_info->usbos_kt);
++}
++
++static void
++dbus_usbos_thread_deinit(usbos_info_t *usbos_info)
++{
++	struct list_head    *cur, *next;
++	usbos_list_entry_t  *entry;
++	unsigned long       flags;
++
++	if (usbos_info->usbos_kt) {
++		wake_up_interruptible(&usbos_info->usbos_queue_head);
++		kthread_stop(usbos_info->usbos_kt);
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	list_for_each_safe(cur, next, &usbos_info->usbos_list)
++	{
++		entry = list_entry(cur, struct usbos_list_entry, list);
++		/* detach this entry from the list and then free the entry */
++		spin_lock_irqsave(&usbos_info->usbos_list_lock, flags);
++		list_del(cur);
++		MFREE(usbos_info->pub->osh, entry, sizeof(usbos_list_entry_t));
++		spin_unlock_irqrestore(&usbos_info->usbos_list_lock, flags);
++	}
++
++	list_for_each_safe(cur, next, &usbos_info->usbos_free_list)
++	{
++		entry = list_entry(cur, struct usbos_list_entry, list);
++		/* detach this entry from the list and then free the entry */
++		spin_lock_irqsave(&usbos_info->usbos_list_lock, flags);
++		list_del(cur);
++		MFREE(usbos_info->pub->osh, entry, sizeof(usbos_list_entry_t));
++		spin_unlock_irqrestore(&usbos_info->usbos_list_lock, flags);
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++}
++
++/** Process completed URBs in a worker thread */
++static int
++dbus_usbos_thread_func(void *data)
++{
++	usbos_info_t        *usbos_info = (usbos_info_t *)data;
++	usbos_list_entry_t  *entry;
++	struct list_head    *cur, *next;
++	unsigned long       flags;
++
++#ifdef WL_THREADNICE
++	set_user_nice(current, WL_THREADNICE);
++#endif
++
++	while (1) {
++		/* If the list is empty, then go to sleep */
++		wait_event_interruptible_timeout
++		(usbos_info->usbos_queue_head,
++			atomic_read(&usbos_info->usbos_list_cnt) > 0,
++			100);
++
++		if (kthread_should_stop())
++			break;
++
++		spin_lock_irqsave(&usbos_info->usbos_list_lock, flags);
++
++		/* For each entry on the list, process it.  Remove the entry from
++		* the list when done.
++		*/
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++		list_for_each_safe(cur, next, &usbos_info->usbos_list)
++		{
++			urb_req_t           *req;
++			int                 len;
++			int                 stat;
++			usbos_info_t        *usbos_info_local;
++
++			entry = list_entry(cur, struct usbos_list_entry, list);
++			if (entry == NULL)
++				break;
++
++			req = entry->urb_context;
++			len = entry->urb_length;
++			stat = entry->urb_status;
++			usbos_info_local = req->usbinfo;
++
++			/* detach this entry from the list and attach it to the free list */
++			list_del_init(cur);
++			spin_unlock_irqrestore(&usbos_info_local->usbos_list_lock, flags);
++
++			dbus_usbos_recv_complete_handle(req, len, stat);
++
++			spin_lock_irqsave(&usbos_info_local->usbos_list_lock, flags);
++
++			list_add_tail(cur, &usbos_info_local->usbos_free_list);
++
++			atomic_dec(&usbos_info_local->usbos_list_cnt);
++		}
++
++		spin_unlock_irqrestore(&usbos_info->usbos_list_lock, flags);
++
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++	return 0;
++} /* dbus_usbos_thread_func */
++
++/** Called on Linux calling URB callback, see dbus_usbos_recv_complete() */
++static void
++dbus_usbos_dispatch_schedule(CALLBACK_ARGS)
++{
++	urb_req_t           *req = urb->context;
++	usbos_info_t        *usbos_info = req->usbinfo;
++	usbos_list_entry_t  *entry;
++	unsigned long       flags;
++	struct list_head    *cur;
++
++	spin_lock_irqsave(&usbos_info->usbos_list_lock, flags);
++
++	cur   = usbos_info->usbos_free_list.next;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	entry = list_entry(cur, struct usbos_list_entry, list);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++	/* detach this entry from the free list and prepare it insert it to use list */
++	list_del_init(cur);
++
++	if (entry) {
++		entry->urb_context = urb->context;
++		entry->urb_length  = urb->actual_length;
++		entry->urb_status  = urb->status;
++
++		atomic_inc(&usbos_info->usbos_list_cnt);
++		list_add_tail(cur, &usbos_info->usbos_list);
++	} else {
++		DBUSERR(("!!!!!!OUT OF MEMORY!!!!!!!\n"));
++	}
++
++	spin_unlock_irqrestore(&usbos_info->usbos_list_lock, flags);
++
++	/* thread */
++	wake_up_interruptible(&usbos_info->usbos_queue_head);
++} /* dbus_usbos_dispatch_schedule */
++
++#endif /* USBOS_THREAD */
++
++
++
++
++#ifdef BCM_REQUEST_FW
++
++struct request_fw_context {
++	const struct firmware *firmware;
++	struct semaphore lock;
++};
++
++/*
++ * Callback for dbus_request_firmware().
++ */
++static void
++dbus_request_firmware_done(const struct firmware *firmware, void *ctx)
++{
++	struct request_fw_context *context = (struct request_fw_context*)ctx;
++
++	/* Store the received firmware handle in the context and wake requester */
++	context->firmware = firmware;
++	up(&context->lock);
++}
++
++/*
++ * Send a firmware request and wait for completion.
++ *
++ * The use of the asynchronous version of request_firmware() is needed to avoid
++ * kernel oopses when we just come out of system hibernate.
++ */
++static int
++dbus_request_firmware(const char *name, const struct firmware **firmware)
++{
++	struct request_fw_context *context;
++	int ret;
++
++	context = kzalloc(sizeof(*context), GFP_KERNEL);
++	if (!context)
++		return -ENOMEM;
++
++	sema_init(&context->lock, 0);
++
++	ret = request_firmware_nowait(THIS_MODULE, true, name, &g_probe_info.usb->dev,
++	                              GFP_KERNEL, context, dbus_request_firmware_done);
++	if (ret) {
++		kfree(context);
++		return ret;
++	}
++
++	/* Wait for completion */
++	if (down_interruptible(&context->lock) != 0) {
++		kfree(context);
++		return -ERESTARTSYS;
++	}
++
++	*firmware = context->firmware;
++	kfree(context);
++
++	return *firmware != NULL ? 0 : -ENOENT;
++}
++
++static void *
++dbus_get_fwfile(int devid, int chiprev, uint8 **fw, int *fwlen, uint16 boardtype, uint16 boardrev)
++{
++	const struct firmware *firmware = NULL;
++#ifndef OEM_ANDROID
++	s8 *device_id = NULL;
++	s8 *chip_rev = "";
++#endif /* OEM_ANDROID */
++	s8 file_name[64];
++	int ret;
++
++#ifndef OEM_ANDROID
++	switch (devid) {
++		case BCM4350_CHIP_ID:
++		case BCM4354_CHIP_ID:
++		case BCM43556_CHIP_ID:
++		case BCM43558_CHIP_ID:
++		case BCM43566_CHIP_ID:
++		case BCM43568_CHIP_ID:
++		case BCM43570_CHIP_ID:
++		case BCM4358_CHIP_ID:
++			device_id = "4350";
++			break;
++		case BCM43143_CHIP_ID:
++			device_id = "43143";
++			break;
++		case BCM43234_CHIP_ID:
++		case BCM43235_CHIP_ID:
++		case BCM43236_CHIP_ID:
++			device_id = "43236";
++			break;
++		case BCM43242_CHIP_ID:
++			device_id = "43242";
++			break;
++		case BCM43238_CHIP_ID:
++			device_id = "43238";
++			break;
++		case BCM43526_CHIP_ID:
++			device_id = "43526";
++			break;
++		case BCM43569_CHIP_ID:
++			device_id = "43569";
++			switch (chiprev) {
++				case 0:
++					chip_rev = "a0";
++					break;
++				case 2:
++					chip_rev = "a2";
++					break;
++				default:
++					break;
++			}
++			break;
++		default:
++			DBUSERR(("unsupported device %x\n", devid));
++			return NULL;
++	}
++
++	/* Load firmware */
++	snprintf(file_name, sizeof(file_name), "brcm/bcm%s%s-firmware.bin", device_id, chip_rev);
++#else
++	snprintf(file_name, sizeof(file_name), "%s", CONFIG_ANDROID_BCMDHD_FW_PATH);
++#endif /* OEM_ANDROID */
++
++	ret = dbus_request_firmware(file_name, &firmware);
++	if (ret) {
++		DBUSERR(("fail to request firmware %s\n", file_name));
++		return NULL;
++	}
++
++	*fwlen = firmware->size;
++	*fw = (uint8 *)firmware->data;
++	return (void *)firmware;
++
++}
++
++static void *
++dbus_get_nvfile(int devid, int chiprev, uint8 **fw, int *fwlen, uint16 boardtype, uint16 boardrev)
++{
++	const struct firmware *firmware = NULL;
++#ifndef OEM_ANDROID
++	s8 *device_id = NULL;
++	s8 *chip_rev = "";
++#endif /* OEM_ANDROID */
++	s8 file_name[64];
++	int ret;
++
++#ifndef OEM_ANDROID
++	switch (devid) {
++		case BCM4350_CHIP_ID:
++		case BCM4354_CHIP_ID:
++		case BCM43556_CHIP_ID:
++		case BCM43558_CHIP_ID:
++		case BCM43566_CHIP_ID:
++		case BCM43568_CHIP_ID:
++		case BCM43570_CHIP_ID:
++		case BCM4358_CHIP_ID:
++			device_id = "4350";
++			break;
++		case BCM43143_CHIP_ID:
++			device_id = "43143";
++			break;
++		case BCM43234_CHIP_ID:
++			device_id = "43234";
++			break;
++		case BCM43235_CHIP_ID:
++			device_id = "43235";
++			break;
++		case BCM43236_CHIP_ID:
++			device_id = "43236";
++			break;
++		case BCM43238_CHIP_ID:
++			device_id = "43238";
++			break;
++		case BCM43242_CHIP_ID:
++			device_id = "43242";
++			break;
++		case BCM43526_CHIP_ID:
++			device_id = "43526";
++			break;
++		case BCM43569_CHIP_ID:
++			device_id = "43569";
++			switch (chiprev) {
++				case 0:
++					chip_rev = "a0";
++					break;
++				case 2:
++					chip_rev = "a2";
++					break;
++				default:
++					break;
++			}
++			break;
++		default:
++			DBUSERR(("unsupported device %x\n", devid));
++			return NULL;
++	}
++
++	/* Load board specific nvram file */
++	snprintf(file_name, sizeof(file_name), "brcm/bcm%s%s-%2x-%2x.nvm",
++	         device_id, chip_rev, boardtype, boardrev);
++#else
++	snprintf(file_name, sizeof(file_name), "%s", CONFIG_ANDROID_BCMDHD_NVRAM_PATH);
++#endif /* OEM_ANDROID */
++
++	ret = dbus_request_firmware(file_name, &firmware);
++	if (ret) {
++		DBUSERR(("fail to request nvram %s\n", file_name));
++
++#ifndef OEM_ANDROID
++		/* Load generic nvram file */
++		snprintf(file_name, sizeof(file_name), "brcm/bcm%s%s.nvm",
++		         device_id, chip_rev);
++
++		ret = dbus_request_firmware(file_name, &firmware);
++#endif /* OEM_ANDROID */
++
++		if (ret) {
++			DBUSERR(("fail to request nvram %s\n", file_name));
++			return NULL;
++		}
++	}
++
++	*fwlen = firmware->size;
++	*fw = (uint8 *)firmware->data;
++	return (void *)firmware;
++}
++
++void *
++dbus_get_fw_nvfile(int devid, int chiprev, uint8 **fw, int *fwlen, int type, uint16 boardtype,
++	uint16 boardrev)
++{
++	switch (type) {
++		case DBUS_FIRMWARE:
++			return dbus_get_fwfile(devid, chiprev, fw, fwlen, boardtype, boardrev);
++		case DBUS_NVFILE:
++			return dbus_get_nvfile(devid, chiprev, fw, fwlen, boardtype, boardrev);
++		default:
++			return NULL;
++	}
++}
++
++void
++dbus_release_fw_nvfile(void *firmware)
++{
++	release_firmware((struct firmware *)firmware);
++}
++#endif /* BCM_REQUEST_FW */
++
++#ifdef BCMUSBDEV_COMPOSITE
++/**
++ * For a composite device the interface order is not guaranteed, scan the device struct for the WLAN
++ * interface.
++ */
++static int
++dbus_usbos_intf_wlan(struct usb_device *usb)
++{
++	int i, num_of_eps, ep, intf_wlan = -1;
++	int num_intf = CONFIGDESC(usb)->bNumInterfaces;
++	struct usb_endpoint_descriptor *endpoint;
++
++	for (i = 0; i < num_intf; i++) {
++		if (IFDESC(usb, i).bInterfaceClass != USB_CLASS_VENDOR_SPEC)
++			continue;
++		num_of_eps = IFDESC(usb, i).bNumEndpoints;
++
++		for (ep = 0; ep < num_of_eps; ep++) {
++			endpoint = &IFEPDESC(usb, i, ep);
++			if ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
++				USB_ENDPOINT_XFER_BULK) {
++				intf_wlan = i;
++				break;
++			}
++		}
++		if (ep < num_of_eps)
++			break;
++	}
++
++	return intf_wlan;
++}
++#endif /* BCMUSBDEV_COMPOSITE */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd.h b/module_drivers/drivers/net/wireless/bcmdhd/dhd.h
+new file mode 100644
+index 000000000..c434ab4e0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd.h
+@@ -0,0 +1,2594 @@
++/*
++ * Header file describing the internal (inter-module) DHD interfaces.
++ *
++ * Provides type definitions and function prototypes used to link the
++ * DHD OS, bus, and protocol modules.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd.h 711448 2017-07-18 08:27:03Z $
++ */
++
++/****************
++ * Common types *
++ */
++
++#ifndef _dhd_h_
++#define _dhd_h_
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/skbuff.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/random.h>
++#include <linux/spinlock.h>
++#include <linux/ethtool.h>
++#include <asm/uaccess.h>
++#include <asm/unaligned.h>
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_HAS_WAKELOCK)
++#include <linux/wakelock.h>
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined (CONFIG_HAS_WAKELOCK) */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)
++#include <linux/sched/types.h>
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0) */
++/* The kernel threading is sdio-specific */
++struct task_struct;
++struct sched_param;
++#if defined(BT_OVER_SDIO)
++#include <dhd_bt_interface.h>
++#endif /* defined (BT_OVER_SDIO) */
++int setScheduler(struct task_struct *p, int policy, struct sched_param *param);
++int get_scheduler_policy(struct task_struct *p);
++#define MAX_EVENT	16
++
++#define ALL_INTERFACES	0xff
++
++#include <wlioctl.h>
++#include <wlfc_proto.h>
++#include <hnd_armtrap.h>
++#if defined(DUMP_IOCTL_IOV_LIST) || defined(DHD_DEBUG)
++#include <bcmutils.h>
++#endif /* DUMP_IOCTL_IOV_LIST || DHD_DEBUG */
++#include <hnd_pktq.h>
++
++#if defined(BCMWDF)
++#include <wdf.h>
++#include <WdfMiniport.h>
++#endif /* (BCMWDF)  */
++
++#ifdef DEBUG_DPC_THREAD_WATCHDOG
++#define MAX_RESCHED_CNT 600
++#endif /* DEBUG_DPC_THREAD_WATCHDOG */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) && LINUX_VERSION_CODE < \
++	KERNEL_VERSION(3, 18, 0) || defined(CONFIG_BCMDHD_VENDOR_EXT))
++#define WL_VENDOR_EXT_SUPPORT
++#endif /* 3.18 > KERNEL_VER >= 3.14 || defined(CONFIG_BCMDHD_VENDOR_EXT) */
++
++#if defined(KEEP_ALIVE)
++/* Default KEEP_ALIVE Period is 55 sec to prevent AP from sending Keep Alive probe frame */
++#define KEEP_ALIVE_PERIOD 55000
++#define NULL_PKT_STR	"null_pkt"
++#endif /* KEEP_ALIVE */
++
++/* Forward decls */
++struct dhd_bus;
++struct dhd_prot;
++struct dhd_info;
++struct dhd_ioctl;
++struct dhd_dbg;
++struct dhd_ts;
++
++/* The level of bus communication with the dongle */
++enum dhd_bus_state {
++	DHD_BUS_DOWN,		/* Not ready for frame transfers */
++	DHD_BUS_LOAD,		/* Download access only (CPU reset) */
++	DHD_BUS_DATA,		/* Ready for frame transfers */
++	DHD_BUS_SUSPEND,	/* Bus has been suspended */
++	DHD_BUS_DOWN_IN_PROGRESS,	/* Bus going Down */
++	DHD_BUS_REMOVE,	/* Bus has been removed */
++};
++
++/*
++ * Bit fields to Indicate clean up process that wait till they are finished.
++ * Future synchronizable processes can add their bit filed below and update
++ * their functionalities accordingly
++ */
++#define DHD_BUS_BUSY_IN_TX                   0x01
++#define DHD_BUS_BUSY_IN_SEND_PKT             0x02
++#define DHD_BUS_BUSY_IN_DPC                  0x04
++#define DHD_BUS_BUSY_IN_WD                   0x08
++#define DHD_BUS_BUSY_IN_IOVAR                0x10
++#define DHD_BUS_BUSY_IN_DHD_IOVAR            0x20
++#define DHD_BUS_BUSY_SUSPEND_IN_PROGRESS     0x40
++#define DHD_BUS_BUSY_RESUME_IN_PROGRESS      0x80
++#define DHD_BUS_BUSY_RPM_SUSPEND_IN_PROGRESS 0x100
++#define DHD_BUS_BUSY_RPM_SUSPEND_DONE        0x200
++#define DHD_BUS_BUSY_RPM_RESUME_IN_PROGRESS  0x400
++#define DHD_BUS_BUSY_RPM_ALL                 (DHD_BUS_BUSY_RPM_SUSPEND_DONE | \
++		DHD_BUS_BUSY_RPM_SUSPEND_IN_PROGRESS | \
++		DHD_BUS_BUSY_RPM_RESUME_IN_PROGRESS)
++#define DHD_BUS_BUSY_IN_CHECKDIED            0x800
++
++#define DHD_BUS_BUSY_SET_IN_TX(dhdp) \
++	(dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_TX
++#define DHD_BUS_BUSY_SET_IN_SEND_PKT(dhdp) \
++	(dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_SEND_PKT
++#define DHD_BUS_BUSY_SET_IN_DPC(dhdp) \
++	(dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_DPC
++#define DHD_BUS_BUSY_SET_IN_WD(dhdp) \
++	(dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_WD
++#define DHD_BUS_BUSY_SET_IN_IOVAR(dhdp) \
++	(dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_IOVAR
++#define DHD_BUS_BUSY_SET_IN_DHD_IOVAR(dhdp) \
++	(dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_DHD_IOVAR
++#define DHD_BUS_BUSY_SET_SUSPEND_IN_PROGRESS(dhdp) \
++	(dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_SUSPEND_IN_PROGRESS
++#define DHD_BUS_BUSY_SET_RESUME_IN_PROGRESS(dhdp) \
++	(dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_RESUME_IN_PROGRESS
++#define DHD_BUS_BUSY_SET_RPM_SUSPEND_IN_PROGRESS(dhdp) \
++	(dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_RPM_SUSPEND_IN_PROGRESS
++#define DHD_BUS_BUSY_SET_RPM_SUSPEND_DONE(dhdp) \
++	(dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_RPM_SUSPEND_DONE
++#define DHD_BUS_BUSY_SET_RPM_RESUME_IN_PROGRESS(dhdp) \
++	(dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_RPM_RESUME_IN_PROGRESS
++#define DHD_BUS_BUSY_SET_IN_CHECKDIED(dhdp) \
++	(dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_CHECKDIED
++
++#define DHD_BUS_BUSY_CLEAR_IN_TX(dhdp) \
++	(dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_TX
++#define DHD_BUS_BUSY_CLEAR_IN_SEND_PKT(dhdp) \
++	(dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_SEND_PKT
++#define DHD_BUS_BUSY_CLEAR_IN_DPC(dhdp) \
++	(dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_DPC
++#define DHD_BUS_BUSY_CLEAR_IN_WD(dhdp) \
++	(dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_WD
++#define DHD_BUS_BUSY_CLEAR_IN_IOVAR(dhdp) \
++	(dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_IOVAR
++#define DHD_BUS_BUSY_CLEAR_IN_DHD_IOVAR(dhdp) \
++	(dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_DHD_IOVAR
++#define DHD_BUS_BUSY_CLEAR_SUSPEND_IN_PROGRESS(dhdp) \
++	(dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_SUSPEND_IN_PROGRESS
++#define DHD_BUS_BUSY_CLEAR_RESUME_IN_PROGRESS(dhdp) \
++	(dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_RESUME_IN_PROGRESS
++#define DHD_BUS_BUSY_CLEAR_RPM_SUSPEND_IN_PROGRESS(dhdp) \
++	(dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_RPM_SUSPEND_IN_PROGRESS
++#define DHD_BUS_BUSY_CLEAR_RPM_SUSPEND_DONE(dhdp) \
++	(dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_RPM_SUSPEND_DONE
++#define DHD_BUS_BUSY_CLEAR_RPM_RESUME_IN_PROGRESS(dhdp) \
++	(dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_RPM_RESUME_IN_PROGRESS
++#define DHD_BUS_BUSY_CLEAR_IN_CHECKDIED(dhdp) \
++	(dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_CHECKDIED
++
++#define DHD_BUS_BUSY_CHECK_IN_TX(dhdp) \
++	((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_TX)
++#define DHD_BUS_BUSY_CHECK_IN_SEND_PKT(dhdp) \
++	((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_SEND_PKT)
++#define DHD_BUS_BUSY_CHECK_IN_DPC(dhdp) \
++	((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_DPC)
++#define DHD_BUS_BUSY_CHECK_IN_WD(dhdp) \
++	((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_WD)
++#define DHD_BUS_BUSY_CHECK_IN_IOVAR(dhdp) \
++	((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_IOVAR)
++#define DHD_BUS_BUSY_CHECK_IN_DHD_IOVAR(dhdp) \
++	((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_DHD_IOVAR)
++#define DHD_BUS_BUSY_CHECK_SUSPEND_IN_PROGRESS(dhdp) \
++	((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_SUSPEND_IN_PROGRESS)
++#define DHD_BUS_BUSY_CHECK_RESUME_IN_PROGRESS(dhdp) \
++	((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_RESUME_IN_PROGRESS)
++#define DHD_BUS_BUSY_CHECK_RPM_SUSPEND_IN_PROGRESS(dhdp) \
++	((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_RPM_SUSPEND_IN_PROGRESS)
++#define DHD_BUS_BUSY_CHECK_RPM_SUSPEND_DONE(dhdp) \
++	((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_RPM_SUSPEND_DONE)
++#define DHD_BUS_BUSY_CHECK_RPM_RESUME_IN_PROGRESS(dhdp) \
++	((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_RPM_RESUME_IN_PROGRESS)
++#define DHD_BUS_BUSY_CHECK_RPM_ALL(dhdp) \
++	((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_RPM_ALL)
++#define DHD_BUS_BUSY_CHECK_IN_CHECKDIED(dhdp) \
++	((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_CHECKDIED)
++#define DHD_BUS_BUSY_CHECK_IDLE(dhdp) \
++		((dhdp)->dhd_bus_busy_state == 0)
++
++#define DHD_BUS_CHECK_SUSPEND_OR_SUSPEND_IN_PROGRESS(dhdp) \
++	((dhdp)->busstate == DHD_BUS_SUSPEND || DHD_BUS_BUSY_CHECK_SUSPEND_IN_PROGRESS(dhdp) || \
++	 DHD_BUS_BUSY_CHECK_RPM_SUSPEND_IN_PROGRESS(dhdp))
++
++#define DHD_BUS_CHECK_ANY_SUSPEND_IN_PROGRESS(dhdp) \
++		(DHD_BUS_BUSY_CHECK_SUSPEND_IN_PROGRESS(dhdp) || \
++		 DHD_BUS_BUSY_CHECK_RPM_SUSPEND_IN_PROGRESS(dhdp))
++
++#define DHD_BUS_CHECK_DOWN_OR_DOWN_IN_PROGRESS(dhdp) \
++		((dhdp)->busstate == DHD_BUS_DOWN || (dhdp)->busstate == DHD_BUS_DOWN_IN_PROGRESS || \
++		(dhdp)->busstate == DHD_BUS_REMOVE)
++
++#define DHD_BUS_CHECK_REMOVE(dhdp) \
++		((dhdp)->busstate == DHD_BUS_REMOVE)
++
++/* Macro to print Ethernet Address as String
++ * expects both arguements as (char *)
++ */
++#define DHD_MAC_TO_STR(mac, str) (snprintf(str, ETHER_ADDR_STR_LEN, \
++					"%02x:%02x:%02x:%02x:%02x:%02x\n", \
++					(uchar)mac[0]&0xff, \
++					(uchar)mac[1]&0xff, \
++					(uchar)mac[2]&0xff, \
++					(uchar)mac[3]&0xff, \
++					(uchar)mac[4]&0xff, \
++					(uchar)mac[5]&0xff))
++
++
++/* Download Types */
++typedef enum download_type {
++	FW,
++	NVRAM,
++	CLM_BLOB
++} download_type_t;
++
++
++/* For supporting multiple interfaces */
++#define DHD_MAX_IFS	16
++#define DHD_DEL_IF	-0xE
++#define DHD_BAD_IF	-0xF
++#define DHD_EVENT_IF	0xFFFF	/* Hack i/f to handle events from INFO Ring */
++
++enum dhd_op_flags {
++/* Firmware requested operation mode */
++	DHD_FLAG_STA_MODE				= (1 << (0)), /* STA only */
++	DHD_FLAG_HOSTAP_MODE				= (1 << (1)), /* SOFTAP only */
++	DHD_FLAG_P2P_MODE				= (1 << (2)), /* P2P Only */
++	/* STA + P2P */
++	DHD_FLAG_CONCURR_SINGLE_CHAN_MODE = (DHD_FLAG_STA_MODE | DHD_FLAG_P2P_MODE),
++	/* STA + SoftAP */
++	DHD_FLAG_CONCURR_STA_HOSTAP_MODE = (DHD_FLAG_STA_MODE | DHD_FLAG_HOSTAP_MODE),
++	DHD_FLAG_CONCURR_MULTI_CHAN_MODE		= (1 << (4)), /* STA + P2P */
++	/* Current P2P mode for P2P connection */
++	DHD_FLAG_P2P_GC_MODE				= (1 << (5)),
++	DHD_FLAG_P2P_GO_MODE				= (1 << (6)),
++	DHD_FLAG_MBSS_MODE				= (1 << (7)), /* MBSS in future */
++	DHD_FLAG_IBSS_MODE				= (1 << (8)),
++	DHD_FLAG_MFG_MODE				= (1 << (9)),
++	DHD_FLAG_RSDB_MODE				= (1 << (10)),
++	DHD_FLAG_MP2P_MODE				= (1 << (11))
++};
++
++#define DHD_OPMODE_SUPPORTED(dhd, opmode_flag) \
++	(dhd ? ((((dhd_pub_t *)dhd)->op_mode)  &  opmode_flag) : -1)
++
++/* Max sequential TX/RX Control timeouts to set HANG event */
++#ifndef MAX_CNTL_TX_TIMEOUT
++#define MAX_CNTL_TX_TIMEOUT 2
++#endif /* MAX_CNTL_TX_TIMEOUT */
++#ifndef MAX_CNTL_RX_TIMEOUT
++#define MAX_CNTL_RX_TIMEOUT 1
++#endif /* MAX_CNTL_RX_TIMEOUT */
++
++#define DHD_SCAN_ASSOC_ACTIVE_TIME	40 /* ms: Embedded default Active setting from DHD */
++#define DHD_SCAN_UNASSOC_ACTIVE_TIME 80 /* ms: Embedded def. Unassoc Active setting from DHD */
++#define DHD_SCAN_PASSIVE_TIME		130 /* ms: Embedded default Passive setting from DHD */
++#define DHD_SCAN_HOME_TIME		45 /* ms: Embedded default Home time setting from DHD */
++#define DHD_SCAN_HOME_AWAY_TIME	100 /* ms: Embedded default Home Away time setting from DHD */
++
++#ifndef POWERUP_MAX_RETRY
++#define POWERUP_MAX_RETRY	3 /* how many times we retry to power up the chip */
++#endif
++#ifndef POWERUP_WAIT_MS
++#define POWERUP_WAIT_MS		2000 /* ms: time out in waiting wifi to come up */
++#endif
++/*
++ * MAX_NVRAMBUF_SIZE determines the size of the Buffer in the DHD that holds
++ * the NVRAM data. That is the size of the buffer pointed by bus->vars
++ * This also needs to be increased to 16K to support NVRAM size higher than 8K
++ */
++#define MAX_NVRAMBUF_SIZE	(16 * 1024) /* max nvram buf size */
++#define MAX_CLM_BUF_SIZE	(48 * 1024) /* max clm blob size */
++#ifdef DHD_DEBUG
++#define DHD_JOIN_MAX_TIME_DEFAULT 10000 /* ms: Max time out for joining AP */
++#define DHD_SCAN_DEF_TIMEOUT 10000 /* ms: Max time out for scan in progress */
++#endif
++
++#ifndef CONFIG_BCMDHD_CLM_PATH
++#define CONFIG_BCMDHD_CLM_PATH "/system/etc/wifi/bcmdhd_clm.blob"
++#endif /* CONFIG_BCMDHD_CLM_PATH */
++#define WL_CCODE_NULL_COUNTRY  "#n"
++
++#define FW_VER_STR_LEN	128
++#define CLM_VER_STR_LEN 128
++#define BUS_API_REV_STR_LEN	128
++extern char bus_api_revision[];
++
++enum dhd_bus_wake_state {
++	WAKE_LOCK_OFF,
++	WAKE_LOCK_PRIV,
++	WAKE_LOCK_DPC,
++	WAKE_LOCK_IOCTL,
++	WAKE_LOCK_DOWNLOAD,
++	WAKE_LOCK_TMOUT,
++	WAKE_LOCK_WATCHDOG,
++	WAKE_LOCK_LINK_DOWN_TMOUT,
++	WAKE_LOCK_PNO_FIND_TMOUT,
++	WAKE_LOCK_SOFTAP_SET,
++	WAKE_LOCK_SOFTAP_STOP,
++	WAKE_LOCK_SOFTAP_START,
++	WAKE_LOCK_SOFTAP_THREAD
++};
++
++#ifdef PCIE_INB_DW
++enum dhd_bus_ds_state {
++	DW_DEVICE_DS_INVALID = -1,
++	DW_DEVICE_DS_DEV_SLEEP = 0,
++	DW_DEVICE_DS_DEV_SLEEP_PEND,
++	DW_DEVICE_DS_DISABLED_WAIT,
++	DW_DEVICE_DS_DEV_WAKE,
++	DW_DEVICE_DS_ACTIVE,
++	DW_DEVICE_HOST_SLEEP_WAIT,
++	DW_DEVICE_HOST_SLEEP,
++	DW_DEVICE_HOST_WAKE_WAIT,
++	DW_DEVICE_DS_D3_INFORM_WAIT
++};
++#endif /* PCIE_INB_DW */
++
++enum dhd_prealloc_index {
++	DHD_PREALLOC_PROT = 0,
++	DHD_PREALLOC_RXBUF = 1,
++	DHD_PREALLOC_DATABUF = 2,
++	DHD_PREALLOC_OSL_BUF = 3,
++	DHD_PREALLOC_SKB_BUF = 4,
++#if defined(STATIC_WL_PRIV_STRUCT)
++	DHD_PREALLOC_WIPHY_ESCAN0 = 5,
++#endif /* STATIC_WL_PRIV_STRUCT */
++	DHD_PREALLOC_DHD_INFO = 7,
++	DHD_PREALLOC_DHD_WLFC_INFO = 8,
++	DHD_PREALLOC_IF_FLOW_LKUP = 9,
++	/* 10 */
++	DHD_PREALLOC_MEMDUMP_RAM = 11,
++	DHD_PREALLOC_DHD_WLFC_HANGER = 12,
++	DHD_PREALLOC_PKTID_MAP = 13,
++	DHD_PREALLOC_PKTID_MAP_IOCTL = 14,
++	DHD_PREALLOC_DHD_LOG_DUMP_BUF = 15,
++	DHD_PREALLOC_DHD_LOG_DUMP_BUF_EX = 16,
++	DHD_PREALLOC_DHD_PKTLOG_DUMP_BUF = 17,
++	DHD_PREALLOC_STAT_REPORT_BUF = 18,
++	DHD_PREALLOC_WL_ESCAN = 19,
++	DHD_PREALLOC_FW_VERBOSE_RING = 20,
++	DHD_PREALLOC_FW_EVENT_RING = 21,
++	DHD_PREALLOC_DHD_EVENT_RING = 22,
++	DHD_PREALLOC_NAN_EVENT_RING = 23
++};
++
++enum dhd_dongledump_mode {
++	DUMP_DISABLED = 0,
++	DUMP_MEMONLY,
++	DUMP_MEMFILE,
++	DUMP_MEMFILE_BUGON,
++	DUMP_MEMFILE_MAX
++};
++
++enum dhd_dongledump_type {
++	DUMP_TYPE_RESUMED_ON_TIMEOUT = 1,
++	DUMP_TYPE_D3_ACK_TIMEOUT,
++	DUMP_TYPE_DONGLE_TRAP,
++	DUMP_TYPE_MEMORY_CORRUPTION,
++	DUMP_TYPE_PKTID_AUDIT_FAILURE,
++	DUMP_TYPE_PKTID_INVALID,
++	DUMP_TYPE_SCAN_TIMEOUT,
++	DUMP_TYPE_JOIN_TIMEOUT,
++	DUMP_TYPE_SCAN_BUSY,
++	DUMP_TYPE_BY_SYSDUMP,
++	DUMP_TYPE_BY_LIVELOCK,
++	DUMP_TYPE_AP_LINKUP_FAILURE,
++	DUMP_TYPE_AP_ABNORMAL_ACCESS,
++	DUMP_TYPE_CFG_VENDOR_TRIGGERED,
++	DUMP_TYPE_RESUMED_ON_TIMEOUT_TX,
++	DUMP_TYPE_RESUMED_ON_TIMEOUT_RX,
++	DUMP_TYPE_RESUMED_ON_INVALID_RING_RDWR,
++	DUMP_TYPE_DONGLE_HOST_EVENT,
++	DUMP_TYPE_RESUMED_UNKNOWN,
++	DUMP_TYPE_TRANS_ID_MISMATCH,
++	DUMP_TYPE_HANG_ON_IFACE_OP_FAIL,
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++	DUMP_TYPE_READ_SHM_FAIL
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++};
++
++enum dhd_hang_reason {
++	HANG_REASON_MASK = 0x8000,
++	HANG_REASON_IOCTL_RESP_TIMEOUT = 0x8001,
++	HANG_REASON_DONGLE_TRAP = 0x8002,
++	HANG_REASON_D3_ACK_TIMEOUT = 0x8003,
++	HANG_REASON_BUS_DOWN = 0x8004,
++	HANG_REASON_MSGBUF_LIVELOCK = 0x8006,
++	HANG_REASON_IFACE_OP_FAILURE = 0x8007,
++	HANG_REASON_HT_AVAIL_ERROR = 0x8008,
++	HANG_REASON_PCIE_RC_LINK_UP_FAIL = 0x8009,
++	HANG_REASON_PCIE_PKTID_ERROR = 0x800A,
++	HANG_REASON_PCIE_LINK_DOWN = 0x8805,
++	HANG_REASON_INVALID_EVENT_OR_DATA = 0x8806,
++	HANG_REASON_UNKNOWN = 0x8807,
++	HANG_REASON_MAX = 0x8808
++};
++
++enum dhd_rsdb_scan_features {
++	/* Downgraded scan feature for AP active */
++	RSDB_SCAN_DOWNGRADED_AP_SCAN = 0x01,
++	/* Downgraded scan feature for P2P Discovery */
++	RSDB_SCAN_DOWNGRADED_P2P_DISC_SCAN = 0x02,
++	/* Enable channel pruning for ROAM SCAN */
++	RSDB_SCAN_DOWNGRADED_CH_PRUNE_ROAM = 0x10,
++	/* Enable channel pruning for any SCAN */
++	RSDB_SCAN_DOWNGRADED_CH_PRUNE_ALL  = 0x20
++};
++
++/* Packet alignment for most efficient SDIO (can change based on platform) */
++#ifndef DHD_SDALIGN
++#define DHD_SDALIGN	32
++#endif
++
++/**
++ * DMA-able buffer parameters
++ * - dmaaddr_t is 32bits on a 32bit host.
++ *   dhd_dma_buf::pa may not be used as a sh_addr_t, bcm_addr64_t or uintptr
++ * - dhd_dma_buf::_alloced is ONLY for freeing a DMA-able buffer.
++ */
++typedef struct dhd_dma_buf {
++	void      *va;      /* virtual address of buffer */
++	uint32    len;      /* user requested buffer length */
++	dmaaddr_t pa;       /* physical address of buffer */
++	void      *dmah;    /* dma mapper handle */
++	void      *secdma;  /* secure dma sec_cma_info handle */
++	uint32    _alloced; /* actual size of buffer allocated with align and pad */
++} dhd_dma_buf_t;
++
++/* host reordering packts logic */
++/* followed the structure to hold the reorder buffers (void **p) */
++typedef struct reorder_info {
++	void **p;
++	uint8 flow_id;
++	uint8 cur_idx;
++	uint8 exp_idx;
++	uint8 max_idx;
++	uint8 pend_pkts;
++} reorder_info_t;
++
++#ifdef DHDTCPACK_SUPPRESS
++
++enum {
++	/* TCPACK suppress off */
++	TCPACK_SUP_OFF,
++	/* Replace TCPACK in txq when new coming one has higher ACK number. */
++	TCPACK_SUP_REPLACE,
++	/* TCPACK_SUP_REPLACE + delayed TCPACK TX unless ACK to PSH DATA.
++	 * This will give benefits to Half-Duplex bus interface(e.g. SDIO) that
++	 * 1. we are able to read TCP DATA packets first from the bus
++	 * 2. TCPACKs that don't need to hurry delivered remains longer in TXQ so can be suppressed.
++	 */
++	TCPACK_SUP_DELAYTX,
++	TCPACK_SUP_HOLD,
++	TCPACK_SUP_LAST_MODE
++};
++
++#ifdef BCMSDIO
++#define TCPACK_SUP_DEFAULT	TCPACK_SUP_DELAYTX
++#elif defined(BCMPCIE)
++#define TCPACK_SUP_DEFAULT	TCPACK_SUP_HOLD
++#else
++#define TCPACK_SUP_DEFAULT	TCPACK_SUP_OFF
++#endif /* BCMSDIO */
++#endif /* DHDTCPACK_SUPPRESS */
++
++#if defined(TRAFFIC_MGMT_DWM)
++#define DHD_DWM_TBL_SIZE           57
++/* DSCP WMM AC Mapping macros and structures */
++#define DHD_TRF_MGMT_DWM_FILTER_BIT                 0x8
++#define DHD_TRF_MGMT_DWM_PRIO_BITS                  0x7
++#define DHD_TRF_MGMT_DWM_FAVORED_BIT                0x10
++#define DHD_TRF_MGMT_DWM_PRIO(dwm_tbl_entry) ((dwm_tbl_entry) & DHD_TRF_MGMT_DWM_PRIO_BITS)
++#define DHD_TRF_MGMT_DWM_IS_FAVORED_SET(dwm_tbl_entry) \
++	((dwm_tbl_entry) & DHD_TRF_MGMT_DWM_FAVORED_BIT)
++#define DHD_TRF_MGMT_DWM_SET_FAVORED(dwm_tbl_entry) \
++	((dwm_tbl_entry) |= DHD_TRF_MGMT_DWM_FAVORED_BIT)
++#define DHD_TRF_MGMT_DWM_IS_FILTER_SET(dwm_tbl_entry) \
++	((dwm_tbl_entry) & DHD_TRF_MGMT_DWM_FILTER_BIT)
++#define DHD_TRF_MGMT_DWM_SET_FILTER(dwm_tbl_entry) \
++	((dwm_tbl_entry) |= DHD_TRF_MGMT_DWM_FILTER_BIT)
++
++typedef struct {
++	uint8 dhd_dwm_enabled;
++	uint8 dhd_dwm_tbl[DHD_DWM_TBL_SIZE];
++} dhd_trf_mgmt_dwm_tbl_t;
++#endif 
++
++#define DHD_NULL_CHK_AND_RET(cond) \
++	if (!cond) { \
++		DHD_ERROR(("%s " #cond " is NULL\n", __FUNCTION__)); \
++		return; \
++	}
++
++#define DHD_NULL_CHK_AND_RET_VAL(cond, value) \
++	if (!cond) { \
++		DHD_ERROR(("%s " #cond " is NULL\n", __FUNCTION__)); \
++		return value; \
++	}
++
++#define DHD_NULL_CHK_AND_GOTO(cond, label) \
++	if (!cond) { \
++		DHD_ERROR(("%s " #cond " is NULL\n", __FUNCTION__)); \
++		goto label; \
++	}
++
++/*
++ * Accumulating the queue lengths of all flowring queues in a parent object,
++ * to assert flow control, when the cummulative queue length crosses an upper
++ * threshold defined on a parent object. Upper threshold may be maintained
++ * at a station level, at an interface level, or at a dhd instance.
++ *
++ * cumm_ctr_t abstraction:
++ * cumm_ctr_t abstraction may be enhanced to use an object with a hysterisis
++ * pause on/off threshold callback.
++ * All macros use the address of the cummulative length in the parent objects.
++ *
++ * BCM_GMAC3 builds use a single perimeter lock, as opposed to a per queue lock.
++ * Cummulative counters in parent objects may be updated without spinlocks.
++ *
++ * In non BCM_GMAC3, if a cummulative queue length is desired across all flows
++ * belonging to either of (a station, or an interface or a dhd instance), then
++ * an atomic operation is required using an atomic_t cummulative counters or
++ * using a spinlock. BCM_ROUTER_DHD uses the Linux atomic_t construct.
++ */
++
++/* Cummulative length not supported. */
++typedef uint32 cumm_ctr_t;
++#define DHD_CUMM_CTR_PTR(clen)     ((cumm_ctr_t*)(clen))
++#define DHD_CUMM_CTR(clen)         *(DHD_CUMM_CTR_PTR(clen)) /* accessor */
++#define DHD_CUMM_CTR_READ(clen)    DHD_CUMM_CTR(clen) /* read access */
++#define DHD_CUMM_CTR_INIT(clen)                                                \
++	ASSERT(DHD_CUMM_CTR_PTR(clen) != DHD_CUMM_CTR_PTR(NULL));
++#define DHD_CUMM_CTR_INCR(clen)                                                \
++	ASSERT(DHD_CUMM_CTR_PTR(clen) != DHD_CUMM_CTR_PTR(NULL));
++#define DHD_CUMM_CTR_DECR(clen)                                                \
++	ASSERT(DHD_CUMM_CTR_PTR(clen) != DHD_CUMM_CTR_PTR(NULL));
++
++#if defined(WLTDLS) && defined(PCIE_FULL_DONGLE)
++struct tdls_peer_node {
++	uint8 addr[ETHER_ADDR_LEN];
++	struct tdls_peer_node *next;
++};
++typedef struct tdls_peer_node tdls_peer_node_t;
++typedef struct {
++	tdls_peer_node_t *node;
++	uint8 tdls_peer_count;
++} tdls_peer_tbl_t;
++#endif /* defined(WLTDLS) && defined(PCIE_FULL_DONGLE) */
++
++#ifdef DHD_LOG_DUMP
++/* below structure describe ring buffer. */
++struct dhd_log_dump_buf
++{
++	spinlock_t lock;
++	unsigned int enable;
++	unsigned int wraparound;
++	unsigned long max;
++	unsigned int remain;
++	char* present;
++	char* front;
++	char* buffer;
++};
++
++#define DHD_LOG_DUMP_MAX_TEMP_BUFFER_SIZE	256
++extern void dhd_log_dump_write(int type, const char *fmt, ...);
++extern char *dhd_log_dump_get_timestamp(void);
++#endif /* DHD_LOG_DUMP */
++
++#if defined(CUSTOMER_HW2)
++#define DHD_COMMON_DUMP_PATH	"/data/misc/wifi/"
++#else
++#define DHD_COMMON_DUMP_PATH	"/installmedia/"
++#endif 
++
++struct cntry_locales_custom {
++	char iso_abbrev[WLC_CNTRY_BUF_SZ];      /* ISO 3166-1 country abbreviation */
++	char custom_locale[WLC_CNTRY_BUF_SZ];   /* Custom firmware locale */
++	int32 custom_locale_rev;                /* Custom local revisin default -1 */
++};
++
++#ifdef REPORT_FATAL_TIMEOUTS
++typedef struct timeout_info {
++	void	*scan_timer_lock;
++	void	*join_timer_lock;
++	void	*cmd_timer_lock;
++	void	*bus_timer_lock;
++	uint32 scan_timeout_val;
++	uint32 join_timeout_val;
++	uint32 cmd_timeout_val;
++	uint32 bus_timeout_val;
++	bool scan_timer_active;
++	bool join_timer_active;
++	bool cmd_timer_active;
++	bool bus_timer_active;
++	osl_timer_t *scan_timer;
++	osl_timer_t *join_timer;
++	osl_timer_t *cmd_timer;
++	osl_timer_t *bus_timer;
++	uint16 cmd_request_id;
++	uint32 cmd;
++	uint32 cmd_join_error;
++} timeout_info_t;
++#endif /* REPORT_FATAL_TIMEOUTS */
++
++#ifdef HOFFLOAD_MODULES
++/* Metadata structure containing module information */
++struct module_metadata {
++	void *data;	/* module data */
++	uint32_t size;	/* module size */
++	u64 data_addr;	/* address of module data in host */
++};
++#endif
++
++#ifdef DMAMAP_STATS
++typedef struct dmamap_stats {
++	uint64 txdata;
++	uint64 txdata_sz;
++	uint64 rxdata;
++	uint64 rxdata_sz;
++	uint64 ioctl_rx;
++	uint64 ioctl_rx_sz;
++	uint64 event_rx;
++	uint64 event_rx_sz;
++	uint64 info_rx;
++	uint64 info_rx_sz;
++	uint64 tsbuf_rx;
++	uint64 tsbuf_rx_sz;
++} dma_stats_t;
++#endif /* DMAMAP_STATS */
++
++/* Common structure for module and instance linkage */
++typedef struct dhd_pub {
++	/* Linkage ponters */
++	osl_t *osh;		/* OSL handle */
++	struct dhd_bus *bus;	/* Bus module handle */
++	struct dhd_prot *prot;	/* Protocol module handle */
++	struct dhd_info  *info; /* Info module handle */
++	struct dhd_dbg *dbg;	/* Debugability module handle */
++
++	/* to NDIS developer, the structure dhd_common is redundant,
++	 * please do NOT merge it back from other branches !!!
++	 */
++
++#ifdef BCMDBUS
++	struct dbus_pub *dbus;
++#endif /* BCMDBUS */
++
++	/* Internal dhd items */
++	bool up;		/* Driver up/down (to OS) */
++#ifdef WL_CFG80211
++	spinlock_t up_lock;	/* Synchronization with CFG80211 down */
++#endif /* WL_CFG80211 */
++	bool txoff;		/* Transmit flow-controlled */
++	bool dongle_reset;  /* TRUE = DEVRESET put dongle into reset */
++	enum dhd_bus_state busstate;
++	uint dhd_bus_busy_state;	/* Bus busy state */
++	uint hdrlen;		/* Total DHD header length (proto + bus) */
++	uint maxctl;		/* Max size rxctl request from proto to bus */
++	uint rxsz;		/* Rx buffer size bus module should use */
++	uint8 wme_dp;	/* wme discard priority */
++
++	/* Dongle media info */
++	bool iswl;		/* Dongle-resident driver is wl */
++	ulong drv_version;	/* Version of dongle-resident driver */
++	struct ether_addr mac;	/* MAC address obtained from dongle */
++	dngl_stats_t dstats;	/* Stats for dongle-based data */
++
++	/* Additional stats for the bus level */
++	ulong tx_packets;	/* Data packets sent to dongle */
++	ulong tx_dropped;	/* Data packets dropped in dhd */
++	ulong tx_multicast;	/* Multicast data packets sent to dongle */
++	ulong tx_errors;	/* Errors in sending data to dongle */
++	ulong tx_ctlpkts;	/* Control packets sent to dongle */
++	ulong tx_ctlerrs;	/* Errors sending control frames to dongle */
++	ulong rx_packets;	/* Packets sent up the network interface */
++	ulong rx_multicast;	/* Multicast packets sent up the network interface */
++	ulong rx_errors;	/* Errors processing rx data packets */
++	ulong rx_ctlpkts;	/* Control frames processed from dongle */
++	ulong rx_ctlerrs;	/* Errors in processing rx control frames */
++	ulong rx_dropped;	/* Packets dropped locally (no memory) */
++	ulong rx_flushed;  /* Packets flushed due to unscheduled sendup thread */
++	ulong wd_dpc_sched;   /* Number of times dhd dpc scheduled by watchdog timer */
++	ulong rx_pktgetfail; /* Number of PKTGET failures in DHD on RX */
++	ulong tx_pktgetfail; /* Number of PKTGET failures in DHD on TX */
++	ulong rx_readahead_cnt;	/* Number of packets where header read-ahead was used. */
++	ulong tx_realloc;	/* Number of tx packets we had to realloc for headroom */
++	ulong fc_packets;       /* Number of flow control pkts recvd */
++
++#ifdef DMAMAP_STATS
++	/* DMA Mapping statistics */
++	dma_stats_t dma_stats;
++#endif /* DMAMAP_STATS */
++
++	/* Last error return */
++	int bcmerror;
++	uint tickcnt;
++
++	/* Last error from dongle */
++	int dongle_error;
++
++	uint8 country_code[WLC_CNTRY_BUF_SZ];
++
++	/* Suspend disable flag and "in suspend" flag */
++	int suspend_disable_flag; /* "1" to disable all extra powersaving during suspend */
++	int in_suspend;			/* flag set to 1 when early suspend called */
++#ifdef PNO_SUPPORT
++	int pno_enable;			/* pno status : "1" is pno enable */
++	int pno_suspend;		/* pno suspend status : "1" is pno suspended */
++#endif /* PNO_SUPPORT */
++	/* DTIM skip value, default 0(or 1) means wake each DTIM
++	 * 3 means skip 2 DTIMs and wake up 3rd DTIM(9th beacon when AP DTIM is 3)
++	 */
++	int suspend_bcn_li_dtim;         /* bcn_li_dtim value in suspend mode */
++#ifdef PKT_FILTER_SUPPORT
++	int early_suspended;	/* Early suspend status */
++	int dhcp_in_progress;	/* DHCP period */
++#endif
++
++	/* Pkt filter defination */
++	char * pktfilter[100];
++	int pktfilter_count;
++
++	wl_country_t dhd_cspec;		/* Current Locale info */
++#ifdef CUSTOM_COUNTRY_CODE
++	uint dhd_cflags;
++#endif /* CUSTOM_COUNTRY_CODE */
++#if defined(DHD_BLOB_EXISTENCE_CHECK)
++	bool is_blob;			/* Checking for existance of Blob file */
++#endif /* DHD_BLOB_EXISTENCE_CHECK */
++	bool force_country_change;
++	char eventmask[WL_EVENTING_MASK_LEN];
++	int	op_mode;				/* STA, HostAPD, WFD, SoftAP */
++
++/* Set this to 1 to use a seperate interface (p2p0) for p2p operations.
++ *  For ICS MR1 releases it should be disable to be compatable with ICS MR1 Framework
++ *  see target dhd-cdc-sdmmc-panda-cfg80211-icsmr1-gpl-debug in Makefile
++ */
++/* #define WL_ENABLE_P2P_IF		1 */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	struct mutex 	wl_start_stop_lock; /* lock/unlock for Android start/stop */
++	struct mutex 	wl_softap_lock;		 /* lock/unlock for any SoftAP/STA settings */
++#endif 
++
++#ifdef PROP_TXSTATUS
++	bool	wlfc_enabled;
++	int	wlfc_mode;
++	void*	wlfc_state;
++	/*
++	Mode in which the dhd flow control shall operate. Must be set before
++	traffic starts to the device.
++	0 - Do not do any proptxtstatus flow control
++	1 - Use implied credit from a packet status
++	2 - Use explicit credit
++	3 - Only AMPDU hostreorder used. no wlfc.
++	*/
++	uint8	proptxstatus_mode;
++	bool	proptxstatus_txoff;
++	bool	proptxstatus_module_ignore;
++	bool	proptxstatus_credit_ignore;
++	bool	proptxstatus_txstatus_ignore;
++
++	bool	wlfc_rxpkt_chk;
++#ifdef LIMIT_BORROW
++	bool wlfc_borrow_allowed;
++#endif /* LIMIT_BORROW */
++	/*
++	 * implement below functions in each platform if needed.
++	 */
++	/* platform specific function whether to skip flow control */
++	bool (*skip_fc)(void * dhdp, uint8 ifx);
++	/* platform specific function for wlfc_enable and wlfc_deinit */
++	void (*plat_init)(void *dhd);
++	void (*plat_deinit)(void *dhd);
++#ifdef DHD_WLFC_THREAD
++	bool                wlfc_thread_go;
++	struct task_struct* wlfc_thread;
++	wait_queue_head_t   wlfc_wqhead;
++#endif /* DHD_WLFC_THREAD */
++#endif /* PROP_TXSTATUS */
++#ifdef PNO_SUPPORT
++	void *pno_state;
++#endif
++#ifdef RTT_SUPPORT
++	void *rtt_state;
++	bool rtt_supported;
++#endif
++	bool	dongle_isolation;
++	bool	is_pcie_watchdog_reset;
++	bool	dongle_trap_occured;	/* flag for sending HANG event to upper layer */
++	bool	iovar_timeout_occured;	/* flag to indicate iovar resumed on timeout */
++#ifdef PCIE_FULL_DONGLE
++	bool	d3ack_timeout_occured;	/* flag to indicate d3ack resumed on timeout */
++#endif /* PCIE_FULL_DONGLE */
++#ifdef BT_OVER_SDIO
++	bool	is_bt_recovery_required;
++#endif
++	int   hang_was_sent;
++	int   rxcnt_timeout;		/* counter rxcnt timeout to send HANG */
++	int   txcnt_timeout;		/* counter txcnt timeout to send HANG */
++#ifdef BCMPCIE
++	int   d3ackcnt_timeout;		/* counter d3ack timeout to send HANG */
++#endif /* BCMPCIE */
++	bool hang_report;		/* enable hang report by default */
++	uint16 hang_reason;		/* reason codes for HANG event */
++#if defined(DHD_HANG_SEND_UP_TEST)
++	uint req_hang_type;
++#endif /* DHD_HANG_SEND_UP_TEST */
++#if defined(CONFIG_BCM_DETECT_CONSECUTIVE_HANG)
++	uint hang_counts;
++#endif /* CONFIG_BCM_DETECT_CONSECUTIVE_HANG */
++#ifdef WLMEDIA_HTSF
++	uint8 htsfdlystat_sz; /* Size of delay stats, max 255B */
++#endif
++#ifdef WLTDLS
++	bool tdls_enable;
++#endif
++	struct reorder_info *reorder_bufs[WLHOST_REORDERDATA_MAXFLOWS];
++	#define WLC_IOCTL_MAXBUF_FWCAP	512
++	char  fw_capabilities[WLC_IOCTL_MAXBUF_FWCAP];
++	#define MAXSKBPEND 1024
++	void *skbbuf[MAXSKBPEND];
++	uint32 store_idx;
++	uint32 sent_idx;
++#ifdef DHDTCPACK_SUPPRESS
++	uint8 tcpack_sup_mode;		/* TCPACK suppress mode */
++	void *tcpack_sup_module;	/* TCPACK suppress module */
++	uint32 tcpack_sup_ratio;
++	uint32 tcpack_sup_delay;
++#endif /* DHDTCPACK_SUPPRESS */
++#if defined(ARP_OFFLOAD_SUPPORT)
++	uint32 arp_version;
++#endif
++#ifdef DEBUG_DPC_THREAD_WATCHDOG
++	bool dhd_bug_on;
++#endif /* DEBUG_DPC_THREAD_WATCHDOG */
++#ifdef CUSTOM_SET_CPUCORE
++	struct task_struct * current_dpc;
++	struct task_struct * current_rxf;
++	int chan_isvht80;
++#endif /* CUSTOM_SET_CPUCORE */
++
++
++	void    *sta_pool;          /* pre-allocated pool of sta objects */
++	void    *staid_allocator;   /* allocator of sta indexes */
++#ifdef PCIE_FULL_DONGLE
++	bool	flow_rings_inited;	/* set this flag after initializing flow rings */
++#endif /* PCIE_FULL_DONGLE */
++	void    *flowid_allocator;  /* unique flowid allocator */
++	void	*flow_ring_table;   /* flow ring table, include prot and bus info */
++	void	*if_flow_lkup;      /* per interface flowid lkup hash table */
++	void    *flowid_lock;       /* per os lock for flowid info protection */
++	void    *flowring_list_lock;       /* per os lock for flowring list protection */
++	uint32  num_flow_rings;
++	cumm_ctr_t cumm_ctr;        /* cumm queue length placeholder  */
++	cumm_ctr_t l2cumm_ctr;      /* level 2 cumm queue length placeholder */
++	uint32 d2h_sync_mode;       /* D2H DMA completion sync mode */
++	uint8  flow_prio_map[NUMPRIO];
++	uint8	flow_prio_map_type;
++	char enable_log[MAX_EVENT];
++	bool dma_d2h_ring_upd_support;
++	bool dma_h2d_ring_upd_support;
++	bool dma_ring_upd_overwrite;	/* host overwrites support setting */
++
++	bool idma_enable;
++	uint idma_inited;
++	bool idma_retention_ds;		/* Implicit DMA memory retention */
++
++	bool ifrm_enable;			/* implicit frm enable */
++	uint ifrm_inited;			/* implicit frm init */
++
++#ifdef DHD_WMF
++	bool wmf_ucast_igmp;
++#ifdef DHD_IGMP_UCQUERY
++	bool wmf_ucast_igmp_query;
++#endif
++#ifdef DHD_UCAST_UPNP
++	bool wmf_ucast_upnp;
++#endif
++#endif /* DHD_WMF */
++#if defined(TRAFFIC_MGMT_DWM)
++	dhd_trf_mgmt_dwm_tbl_t dhd_tm_dwm_tbl;
++#endif 
++#ifdef DHD_L2_FILTER
++	unsigned long l2_filter_cnt;	/* for L2_FILTER ARP table timeout */
++#endif /* DHD_L2_FILTER */
++#ifdef DHD_SSSR_DUMP
++	bool sssr_inited;
++	sssr_reg_info_t sssr_reg_info;
++	uint8 *sssr_mempool;
++	uint *sssr_d11_before[MAX_NUM_D11CORES];
++	uint *sssr_d11_after[MAX_NUM_D11CORES];
++	bool sssr_d11_outofreset[MAX_NUM_D11CORES];
++	uint *sssr_vasip_buf_before;
++	uint *sssr_vasip_buf_after;
++#endif /* DHD_SSSR_DUMP */
++	uint8 *soc_ram;
++	uint32 soc_ram_length;
++	uint32 memdump_type;
++#ifdef DHD_FW_COREDUMP
++	uint32 memdump_enabled;
++	bool memdump_success;
++#endif /* DHD_FW_COREDUMP */
++#ifdef PCIE_FULL_DONGLE
++#ifdef WLTDLS
++	tdls_peer_tbl_t peer_tbl;
++#endif /* WLTDLS */
++	uint8 tx_in_progress;
++#endif /* PCIE_FULL_DONGLE */
++#ifdef DHD_ULP
++	void *dhd_ulp;
++#endif
++#ifdef CACHE_FW_IMAGES
++	char	*cached_fw;
++	int	cached_fw_length;
++	char	*cached_nvram;
++	int	cached_nvram_length;
++	char	*cached_clm;
++	int	cached_clm_length;
++#endif
++#ifdef WLTDLS
++	uint32 tdls_mode;
++#endif
++#ifdef GSCAN_SUPPORT
++	bool lazy_roam_enable;
++#endif
++#if defined(PKT_FILTER_SUPPORT) && defined(APF)
++	bool apf_set;
++#endif /* PKT_FILTER_SUPPORT && APF */
++#ifdef DHD_WET
++	void *wet_info;
++#endif
++	bool	h2d_phase_supported;
++	bool	force_dongletrap_on_bad_h2d_phase;
++	uint32	dongle_trap_data;
++	bool	cto_enable;		/* enable PCIE CTO Prevention and recovery */
++	uint32	cto_threshold;	/* PCIE CTO timeout threshold */
++	bool	fw_download_done;
++	trap_t	last_trap_info; /* trap info from the last trap */
++	uint8 rand_mac_oui[DOT11_OUI_LEN];
++#ifdef DHD_LOSSLESS_ROAMING
++	uint8 dequeue_prec_map;
++	uint8 prio_8021x;
++#endif
++#ifdef REPORT_FATAL_TIMEOUTS
++	timeout_info_t *timeout_info;
++#endif /* REPORT_FATAL_TIMEOUTS */
++	/* timesync link */
++	struct dhd_ts *ts;
++	bool	d2h_hostrdy_supported;
++#if defined(DBG_PKT_MON) || defined(DHD_PKT_LOGGING)
++	bool d11_tx_status;
++#endif /* DBG_PKT_MON || DHD_PKT_LOGGING */
++	uint16 ndo_version;		/* ND offload version supported */
++#ifdef NDO_CONFIG_SUPPORT
++	bool ndo_enable;		/* ND offload feature enable */
++	bool ndo_host_ip_overflow;	/* # of host ip addr exceed FW capacity */
++	uint32 ndo_max_host_ip;		/* # of host ip addr supported by FW */
++#endif /* NDO_CONFIG_SUPPORT */
++#if defined(DHD_EFI) && defined(DHD_LOG_DUMP)
++	uint8 log_capture_enable;
++#endif /* DHD_EFI && DHD_LOG_DUMP */
++	bool max_dtim_enable;         /* use MAX bcn_li_dtim value in suspend mode */
++#ifdef PCIE_OOB
++	bool	d2h_no_oob_dw;
++#endif /* PCIE_OOB */
++#ifdef PCIE_INB_DW
++	bool	d2h_inband_dw;
++	enum dhd_bus_ds_state	ds_state;
++#endif /* PCIE_INB_DW */
++#ifdef CUSTOM_SET_ANTNPM
++	uint32 mimo_ant_set;
++#endif /* CUSTOM_SET_ANTNPM */
++#ifdef CUSTOM_SET_OCLOFF
++	bool ocl_off;
++#endif /* CUSTOM_SET_OCLOFF */
++#ifdef HOFFLOAD_MODULES
++	struct module_metadata hmem;
++#endif
++	bool wbtext_support;
++#ifdef DUMP_IOCTL_IOV_LIST
++	/* dump iovar list */
++	dll_t dump_iovlist_head;
++	uint8 dump_iovlist_len;
++#endif /* DUMP_IOCTL_IOV_LIST */
++#ifdef DHD_DEBUG
++/* memwaste feature */
++	dll_t mw_list_head; /* memwaste list head */
++	uint32 mw_id; /* memwaste list unique id */
++#endif /* DHD_DEBUG */
++#ifdef WLTDLS
++	spinlock_t tdls_lock;
++#endif /* WLTDLS */
++#ifdef WLADPS_SEAK_AP_WAR
++	uint32 disabled_adps;
++#endif /* WLADPS_SEAK_AP_WAR */
++	bool ext_trap_data_supported;
++	uint32 *extended_trap_data;
++#ifdef DHD_PKT_LOGGING
++	struct dhd_pktlog *pktlog;
++#endif /* DHD_PKT_LOGGING */
++#if defined(STAT_REPORT)
++	void *stat_report_info;
++#endif
++	char *clm_path;		/* module_param: path to clm vars file */
++	char *conf_path;		/* module_param: path to config vars file */
++	struct dhd_conf *conf;	/* Bus module handle */
++	void *adapter;			/* adapter information, interrupt, fw path etc. */
++	void *event_params;
++#ifdef BCMDBUS
++	bool dhd_remove;
++#endif /* BCMDBUS */
++#ifdef WL_ESCAN
++	struct wl_escan_info *escan;
++#endif
++#if defined(WL_WIRELESS_EXT)
++	void *wext_info;
++#endif
++#ifdef WL_EXT_IAPSTA
++	void *iapsta_params;
++#endif
++	int hostsleep;
++#ifdef SENDPROB
++	bool recv_probereq;
++#endif
++} dhd_pub_t;
++
++typedef struct {
++	uint rxwake;
++	uint rcwake;
++#ifdef DHD_WAKE_RX_STATUS
++	uint rx_bcast;
++	uint rx_arp;
++	uint rx_mcast;
++	uint rx_multi_ipv6;
++	uint rx_icmpv6;
++	uint rx_icmpv6_ra;
++	uint rx_icmpv6_na;
++	uint rx_icmpv6_ns;
++	uint rx_multi_ipv4;
++	uint rx_multi_other;
++	uint rx_ucast;
++#endif /* DHD_WAKE_RX_STATUS */
++#ifdef DHD_WAKE_EVENT_STATUS
++	uint rc_event[WLC_E_LAST];
++#endif /* DHD_WAKE_EVENT_STATUS */
++} wake_counts_t;
++
++#if defined(PCIE_FULL_DONGLE)
++
++/* Packet Tag for PCIE Full Dongle DHD */
++typedef struct dhd_pkttag_fd {
++	uint16    flowid;   /* Flowring Id */
++	uint16    dataoff;  /* start of packet */
++	uint16    dma_len;  /* pkt len for DMA_MAP/UNMAP */
++	dmaaddr_t pa;       /* physical address */
++	void      *dmah;    /* dma mapper handle */
++	void      *secdma; /* secure dma sec_cma_info handle */
++} dhd_pkttag_fd_t;
++
++/* Packet Tag for DHD PCIE Full Dongle */
++#define DHD_PKTTAG_FD(pkt)          ((dhd_pkttag_fd_t *)(PKTTAG(pkt)))
++
++#define DHD_PKT_GET_FLOWID(pkt)     ((DHD_PKTTAG_FD(pkt))->flowid)
++#define DHD_PKT_SET_FLOWID(pkt, pkt_flowid) \
++	DHD_PKTTAG_FD(pkt)->flowid = (uint16)(pkt_flowid)
++
++#define DHD_PKT_GET_DATAOFF(pkt)    ((DHD_PKTTAG_FD(pkt))->dataoff)
++#define DHD_PKT_SET_DATAOFF(pkt, pkt_dataoff) \
++	DHD_PKTTAG_FD(pkt)->dataoff = (uint16)(pkt_dataoff)
++
++#define DHD_PKT_GET_DMA_LEN(pkt)    ((DHD_PKTTAG_FD(pkt))->dma_len)
++#define DHD_PKT_SET_DMA_LEN(pkt, pkt_dma_len) \
++	DHD_PKTTAG_FD(pkt)->dma_len = (uint16)(pkt_dma_len)
++
++#define DHD_PKT_GET_PA(pkt)         ((DHD_PKTTAG_FD(pkt))->pa)
++#define DHD_PKT_SET_PA(pkt, pkt_pa) \
++	DHD_PKTTAG_FD(pkt)->pa = (dmaaddr_t)(pkt_pa)
++
++#define DHD_PKT_GET_DMAH(pkt)       ((DHD_PKTTAG_FD(pkt))->dmah)
++#define DHD_PKT_SET_DMAH(pkt, pkt_dmah) \
++	DHD_PKTTAG_FD(pkt)->dmah = (void *)(pkt_dmah)
++
++#define DHD_PKT_GET_SECDMA(pkt)    ((DHD_PKTTAG_FD(pkt))->secdma)
++#define DHD_PKT_SET_SECDMA(pkt, pkt_secdma) \
++	DHD_PKTTAG_FD(pkt)->secdma = (void *)(pkt_secdma)
++#endif /* PCIE_FULL_DONGLE */
++
++#if defined(BCMWDF)
++typedef struct {
++	dhd_pub_t *dhd_pub;
++} dhd_workitem_context_t;
++
++WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(dhd_workitem_context_t, dhd_get_dhd_workitem_context)
++#endif /* (BCMWDF)  */
++
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_PM_SLEEP)
++
++	#define DHD_PM_RESUME_WAIT_INIT(a) DECLARE_WAIT_QUEUE_HEAD(a);
++	#define _DHD_PM_RESUME_WAIT(a, b) do {\
++			int retry = 0; \
++			SMP_RD_BARRIER_DEPENDS(); \
++			while (dhd_mmc_suspend && retry++ != b) { \
++				SMP_RD_BARRIER_DEPENDS(); \
++				wait_event_interruptible_timeout(a, !dhd_mmc_suspend, 1); \
++			} \
++		} 	while (0)
++	#define DHD_PM_RESUME_WAIT(a) 		_DHD_PM_RESUME_WAIT(a, 200)
++	#define DHD_PM_RESUME_WAIT_FOREVER(a) 	_DHD_PM_RESUME_WAIT(a, ~0)
++	#define DHD_PM_RESUME_RETURN_ERROR(a)   do { \
++			if (dhd_mmc_suspend) { \
++				printf("%s[%d]: mmc is still in suspend state!!!\n", \
++					__FUNCTION__, __LINE__); \
++				return a; \
++			} \
++		} while (0)
++	#define DHD_PM_RESUME_RETURN		do { if (dhd_mmc_suspend) return; } while (0)
++
++	#define DHD_SPINWAIT_SLEEP_INIT(a) DECLARE_WAIT_QUEUE_HEAD(a);
++	#define SPINWAIT_SLEEP(a, exp, us) do { \
++		uint countdown = (us) + 9999; \
++		while ((exp) && (countdown >= 10000)) { \
++			wait_event_interruptible_timeout(a, FALSE, 1); \
++			countdown -= 10000; \
++		} \
++	} while (0)
++
++	#else
++
++	#define DHD_PM_RESUME_WAIT_INIT(a)
++	#define DHD_PM_RESUME_WAIT(a)
++	#define DHD_PM_RESUME_WAIT_FOREVER(a)
++	#define DHD_PM_RESUME_RETURN_ERROR(a)
++	#define DHD_PM_RESUME_RETURN
++
++	#define DHD_SPINWAIT_SLEEP_INIT(a)
++	#define SPINWAIT_SLEEP(a, exp, us)  do { \
++		uint countdown = (us) + 9; \
++		while ((exp) && (countdown >= 10)) { \
++			OSL_DELAY(10);  \
++			countdown -= 10;  \
++		} \
++	} while (0)
++
++	#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_PM_SLEEP) */
++
++#ifndef OSL_SLEEP
++#define OSL_SLEEP(ms)		OSL_DELAY(ms*1000)
++#endif /* OSL_SLEEP */
++
++#define DHD_IF_VIF	0x01	/* Virtual IF (Hidden from user) */
++
++#ifdef PNO_SUPPORT
++int dhd_pno_clean(dhd_pub_t *dhd);
++#endif /* PNO_SUPPORT */
++
++#ifdef HOFFLOAD_MODULES
++void dhd_linux_get_modfw_address(dhd_pub_t *dhd);
++#endif
++
++/*
++ *  Wake locks are an Android power management concept. They are used by applications and services
++ *  to request CPU resources.
++ */
++extern int dhd_os_wake_lock(dhd_pub_t *pub);
++extern int dhd_os_wake_unlock(dhd_pub_t *pub);
++extern int dhd_os_wake_lock_waive(dhd_pub_t *pub);
++extern int dhd_os_wake_lock_restore(dhd_pub_t *pub);
++extern void dhd_event_wake_lock(dhd_pub_t *pub);
++extern void dhd_event_wake_unlock(dhd_pub_t *pub);
++extern void dhd_pm_wake_lock_timeout(dhd_pub_t *pub, int val);
++extern void dhd_pm_wake_unlock(dhd_pub_t *pub);
++extern void dhd_txfl_wake_lock_timeout(dhd_pub_t *pub, int val);
++extern void dhd_txfl_wake_unlock(dhd_pub_t *pub);
++extern int dhd_os_wake_lock_timeout(dhd_pub_t *pub);
++extern int dhd_os_wake_lock_rx_timeout_enable(dhd_pub_t *pub, int val);
++extern int dhd_os_wake_lock_ctrl_timeout_enable(dhd_pub_t *pub, int val);
++extern int dhd_os_wake_lock_ctrl_timeout_cancel(dhd_pub_t *pub);
++extern int dhd_os_wd_wake_lock(dhd_pub_t *pub);
++extern int dhd_os_wd_wake_unlock(dhd_pub_t *pub);
++extern void dhd_os_wake_lock_init(struct dhd_info *dhd);
++extern void dhd_os_wake_lock_destroy(struct dhd_info *dhd);
++#ifdef DHD_USE_SCAN_WAKELOCK
++extern void dhd_os_scan_wake_lock_timeout(dhd_pub_t *pub, int val);
++extern void dhd_os_scan_wake_unlock(dhd_pub_t *pub);
++#endif /* BCMPCIE_SCAN_WAKELOCK */
++
++inline static void MUTEX_LOCK_SOFTAP_SET_INIT(dhd_pub_t * dhdp)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	mutex_init(&dhdp->wl_softap_lock);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
++}
++
++inline static void MUTEX_LOCK_SOFTAP_SET(dhd_pub_t * dhdp)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	mutex_lock(&dhdp->wl_softap_lock);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
++}
++
++inline static void MUTEX_UNLOCK_SOFTAP_SET(dhd_pub_t * dhdp)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	mutex_unlock(&dhdp->wl_softap_lock);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
++}
++
++#define PRINT_CALL_INFO(str)
++#define PRINT_CALL_INFO_TIMEOUT(str, val)
++#define DHD_OS_WAKE_LOCK(pub) \
++	do { \
++		PRINT_CALL_INFO("call wakelock"); \
++		dhd_os_wake_lock(pub); \
++	} while (0)
++#define DHD_OS_WAKE_UNLOCK(pub) \
++	do { \
++		PRINT_CALL_INFO("call wake_unlock"); \
++		dhd_os_wake_unlock(pub); \
++	} while (0)
++#define DHD_EVENT_WAKE_LOCK(pub) \
++	do { \
++		PRINT_CALL_INFO("call event_wake lock"); \
++	dhd_event_wake_lock(pub); \
++	} while (0)
++#define DHD_EVENT_WAKE_UNLOCK(pub) \
++	do { \
++		PRINT_CALL_INFO("call event_wake unlock"); \
++	dhd_event_wake_unlock(pub); \
++	} while (0)
++#define DHD_PM_WAKE_LOCK_TIMEOUT(pub, val) \
++	do { \
++		PRINT_CALL_INFO("call pm_wake_timeout enable"); \
++	dhd_pm_wake_lock_timeout(pub, val); \
++	} while (0)
++#define DHD_PM_WAKE_UNLOCK(pub) \
++	do { \
++		PRINT_CALL_INFO("call pm_wake unlock"); \
++	dhd_pm_wake_unlock(pub); \
++	} while (0)
++#define DHD_TXFL_WAKE_LOCK_TIMEOUT(pub, val) \
++	do { \
++		PRINT_CALL_INFO("call pm_wake_timeout enable"); \
++		dhd_txfl_wake_lock_timeout(pub, val); \
++	} while (0)
++#define DHD_TXFL_WAKE_UNLOCK(pub) \
++	do { \
++		PRINT_CALL_INFO("call pm_wake unlock"); \
++		dhd_txfl_wake_unlock(pub); \
++	} while (0)
++#define DHD_OS_WAKE_LOCK_TIMEOUT(pub) \
++	do { \
++		PRINT_CALL_INFO("call wake_lock_timeout"); \
++		dhd_os_wake_lock_timeout(pub); \
++	} while (0)
++#define DHD_OS_WAKE_LOCK_RX_TIMEOUT_ENABLE(pub, val) \
++	do { \
++		PRINT_CALL_INFO_TIMEOUT("call wake_lock_rx_timeout_enable", val); \
++		dhd_os_wake_lock_rx_timeout_enable(pub, val); \
++	} while (0)
++#define DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_ENABLE(pub, val) \
++	do { \
++		PRINT_CALL_INFO_TIMEOUT("call wake_lock_ctrl_timeout_enable", val); \
++		dhd_os_wake_lock_ctrl_timeout_enable(pub, val); \
++	} while (0)
++#define DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_CANCEL(pub) \
++	do { \
++		PRINT_CALL_INFO("call wake_lock_ctrl_timeout_cancel"); \
++		dhd_os_wake_lock_ctrl_timeout_cancel(pub); \
++	} while (0)
++#define DHD_OS_WAKE_LOCK_WAIVE(pub) \
++	do { \
++		PRINT_CALL_INFO("call wake_lock_waive"); \
++		dhd_os_wake_lock_waive(pub); \
++	} while (0)
++#define DHD_OS_WAKE_LOCK_RESTORE(pub) \
++	do { \
++		PRINT_CALL_INFO("call wake_lock_restore"); \
++		dhd_os_wake_lock_restore(pub); \
++	} while (0)
++#define DHD_OS_WAKE_LOCK_INIT(dhd) \
++	do { \
++		PRINT_CALL_INFO("call wake_lock_init"); \
++		dhd_os_wake_lock_init(dhd); \
++	} while (0)
++#define DHD_OS_WAKE_LOCK_DESTROY(dhd) \
++	do { \
++		PRINT_CALL_INFO("call wake_lock_destroy"); \
++		dhd_os_wake_lock_destroy(dhd); \
++	} while (0)
++
++#define DHD_OS_WD_WAKE_LOCK(pub)		dhd_os_wd_wake_lock(pub)
++#define DHD_OS_WD_WAKE_UNLOCK(pub)		dhd_os_wd_wake_unlock(pub)
++
++#ifdef DHD_USE_SCAN_WAKELOCK
++#ifdef DHD_DEBUG_SCAN_WAKELOCK
++#define PRINT_SCAN_CALL(str) printf("%s: %s %d\n", \
++		str, __FUNCTION__, __LINE__)
++#else
++#define PRINT_SCAN_CALL(str)
++#endif /* DHD_DEBUG_SCAN_WAKELOCK */
++#define DHD_OS_SCAN_WAKE_LOCK_TIMEOUT(pub, val) \
++	do { \
++		PRINT_SCAN_CALL("call wake_lock_scan"); \
++		dhd_os_scan_wake_lock_timeout(pub, val); \
++	} while (0)
++#define DHD_OS_SCAN_WAKE_UNLOCK(pub) \
++	do { \
++		PRINT_SCAN_CALL("call wake_unlock_scan"); \
++		dhd_os_scan_wake_unlock(pub); \
++	} while (0)
++#else
++#define DHD_OS_SCAN_WAKE_LOCK_TIMEOUT(pub, val)
++#define DHD_OS_SCAN_WAKE_UNLOCK(pub)
++#endif /* DHD_USE_SCAN_WAKELOCK */
++
++#ifdef BCMPCIE_OOB_HOST_WAKE
++#define OOB_WAKE_LOCK_TIMEOUT 500
++extern void dhd_os_oob_irq_wake_lock_timeout(dhd_pub_t *pub, int val);
++extern void dhd_os_oob_irq_wake_unlock(dhd_pub_t *pub);
++#define DHD_OS_OOB_IRQ_WAKE_LOCK_TIMEOUT(pub, val)	dhd_os_oob_irq_wake_lock_timeout(pub, val)
++#define DHD_OS_OOB_IRQ_WAKE_UNLOCK(pub)			dhd_os_oob_irq_wake_unlock(pub)
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++
++#define DHD_PACKET_TIMEOUT_MS	500
++#define DHD_EVENT_TIMEOUT_MS	1500
++#define SCAN_WAKE_LOCK_TIMEOUT	10000
++#define MAX_TX_TIMEOUT			500
++
++/* Enum for IOCTL recieved status */
++typedef enum dhd_ioctl_recieved_status
++{
++	IOCTL_WAIT = 0,
++	IOCTL_RETURN_ON_SUCCESS,
++	IOCTL_RETURN_ON_TRAP,
++	IOCTL_RETURN_ON_BUS_STOP,
++	IOCTL_RETURN_ON_ERROR
++} dhd_ioctl_recieved_status_t;
++
++/* interface operations (register, remove) should be atomic, use this lock to prevent race
++ * condition among wifi on/off and interface operation functions
++ */
++void dhd_net_if_lock(struct net_device *dev);
++void dhd_net_if_unlock(struct net_device *dev);
++#if defined(MULTIPLE_SUPPLICANT)
++extern void wl_android_post_init(void); // terence 20120530: fix critical section in dhd_open and dhdsdio_probe
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25)) && defined(MULTIPLE_SUPPLICANT)
++extern struct mutex _dhd_mutex_lock_;
++#define DHD_MUTEX_IS_LOCK_RETURN() \
++	if (mutex_is_locked(&_dhd_mutex_lock_) != 0) { \
++		printf("%s : probe is already running! return.\n", __FUNCTION__); \
++		return 0; \
++	}
++#define DHD_MUTEX_LOCK() \
++	do { \
++		if (mutex_is_locked(&_dhd_mutex_lock_) == 0) { \
++			printf("%s : no mutex held. set lock\n", __FUNCTION__); \
++		} else { \
++			printf("%s : mutex is locked!. wait for unlocking\n", __FUNCTION__); \
++		} \
++		mutex_lock(&_dhd_mutex_lock_); \
++	} while (0)
++#define DHD_MUTEX_UNLOCK() \
++	do { \
++		mutex_unlock(&_dhd_mutex_lock_); \
++		printf("%s : the lock is released.\n", __FUNCTION__); \
++	} while (0)
++#else
++#define DHD_MUTEX_IS_LOCK_RETURN(a)	do {} while (0)
++#define DHD_MUTEX_LOCK(a)	do {} while (0)
++#define DHD_MUTEX_UNLOCK(a)	do {} while (0)
++#endif
++
++typedef enum dhd_attach_states
++{
++	DHD_ATTACH_STATE_INIT = 0x0,
++	DHD_ATTACH_STATE_NET_ALLOC = 0x1,
++	DHD_ATTACH_STATE_DHD_ALLOC = 0x2,
++	DHD_ATTACH_STATE_ADD_IF = 0x4,
++	DHD_ATTACH_STATE_PROT_ATTACH = 0x8,
++	DHD_ATTACH_STATE_WL_ATTACH = 0x10,
++	DHD_ATTACH_STATE_THREADS_CREATED = 0x20,
++	DHD_ATTACH_STATE_WAKELOCKS_INIT = 0x40,
++	DHD_ATTACH_STATE_CFG80211 = 0x80,
++	DHD_ATTACH_STATE_EARLYSUSPEND_DONE = 0x100,
++	DHD_ATTACH_TIMESYNC_ATTACH_DONE = 0x200,
++	DHD_ATTACH_LOGTRACE_INIT = 0x400,
++	DHD_ATTACH_STATE_LB_ATTACH_DONE = 0x800,
++	DHD_ATTACH_STATE_DONE = 0x1000
++} dhd_attach_states_t;
++
++/* Value -1 means we are unsuccessful in creating the kthread. */
++#define DHD_PID_KT_INVALID 	-1
++/* Value -2 means we are unsuccessful in both creating the kthread and tasklet */
++#define DHD_PID_KT_TL_INVALID	-2
++
++/*
++ * Exported from dhd OS modules (dhd_linux/dhd_ndis)
++ */
++
++/* Indication from bus module regarding presence/insertion of dongle.
++ * Return dhd_pub_t pointer, used as handle to OS module in later calls.
++ * Returned structure should have bus and prot pointers filled in.
++ * bus_hdrlen specifies required headroom for bus module header.
++ */
++extern dhd_pub_t *dhd_attach(osl_t *osh, struct dhd_bus *bus, uint bus_hdrlen
++#ifdef BCMDBUS
++	, void *adapter
++#endif
++);
++#if defined(WLP2P) && defined(WL_CFG80211)
++/* To allow attach/detach calls corresponding to p2p0 interface  */
++extern int dhd_attach_p2p(dhd_pub_t *);
++extern int dhd_detach_p2p(dhd_pub_t *);
++#endif /* WLP2P && WL_CFG80211 */
++extern int dhd_register_if(dhd_pub_t *dhdp, int idx, bool need_rtnl_lock);
++
++/* Indication from bus module regarding removal/absence of dongle */
++extern void dhd_detach(dhd_pub_t *dhdp);
++extern void dhd_free(dhd_pub_t *dhdp);
++extern void dhd_clear(dhd_pub_t *dhdp);
++
++/* Indication from bus module to change flow-control state */
++extern void dhd_txflowcontrol(dhd_pub_t *dhdp, int ifidx, bool on);
++
++/* Store the status of a connection attempt for later retrieval by an iovar */
++extern void dhd_store_conn_status(uint32 event, uint32 status, uint32 reason);
++
++extern bool dhd_prec_enq(dhd_pub_t *dhdp, struct pktq *q, void *pkt, int prec);
++
++extern void dhd_rx_frame(dhd_pub_t *dhdp, int ifidx, void *rxp, int numpkt, uint8 chan);
++
++/* Return pointer to interface name */
++extern char *dhd_ifname(dhd_pub_t *dhdp, int idx);
++
++#ifdef DHD_UCODE_DOWNLOAD
++/* Returns the ucode path */
++extern char *dhd_get_ucode_path(dhd_pub_t *dhdp);
++#endif /* DHD_UCODE_DOWNLOAD */
++
++/* Request scheduling of the bus dpc */
++extern void dhd_sched_dpc(dhd_pub_t *dhdp);
++
++/* Notify tx completion */
++extern void dhd_txcomplete(dhd_pub_t *dhdp, void *txp, bool success);
++
++#define WIFI_FEATURE_INFRA              0x0001      /* Basic infrastructure mode        */
++#define WIFI_FEATURE_INFRA_5G           0x0002      /* Support for 5 GHz Band           */
++#define WIFI_FEATURE_HOTSPOT            0x0004      /* Support for GAS/ANQP             */
++#define WIFI_FEATURE_P2P                0x0008      /* Wifi-Direct                      */
++#define WIFI_FEATURE_SOFT_AP            0x0010      /* Soft AP                          */
++#define WIFI_FEATURE_GSCAN              0x0020      /* Google-Scan APIs                 */
++#define WIFI_FEATURE_NAN                0x0040      /* Neighbor Awareness Networking    */
++#define WIFI_FEATURE_D2D_RTT            0x0080      /* Device-to-device RTT             */
++#define WIFI_FEATURE_D2AP_RTT           0x0100      /* Device-to-AP RTT                 */
++#define WIFI_FEATURE_BATCH_SCAN         0x0200      /* Batched Scan (legacy)            */
++#define WIFI_FEATURE_PNO                0x0400      /* Preferred network offload        */
++#define WIFI_FEATURE_ADDITIONAL_STA     0x0800      /* Support for two STAs             */
++#define WIFI_FEATURE_TDLS               0x1000      /* Tunnel directed link setup       */
++#define WIFI_FEATURE_TDLS_OFFCHANNEL    0x2000      /* Support for TDLS off channel     */
++#define WIFI_FEATURE_EPR                0x4000      /* Enhanced power reporting         */
++#define WIFI_FEATURE_AP_STA             0x8000      /* Support for AP STA Concurrency   */
++#define WIFI_FEATURE_LINKSTAT           0x10000     /* Support for Linkstats            */
++#define WIFI_FEATURE_LOGGER             0x20000     /* WiFi Logger			*/
++#define WIFI_FEATURE_HAL_EPNO           0x40000     /* WiFi PNO enhanced                */
++#define WIFI_FEATURE_RSSI_MONITOR       0x80000     /* RSSI Monitor                     */
++#define WIFI_FEATURE_MKEEP_ALIVE        0x100000    /* WiFi mkeep_alive			*/
++#define WIFI_FEATURE_CONFIG_NDO         0x200000    /* ND offload configure             */
++#define WIFI_FEATURE_TX_TRANSMIT_POWER  0x400000    /* Capture Tx transmit power levels	*/
++#define WIFI_FEATURE_INVALID            0xFFFFFFFF  /* Invalid Feature                  */
++
++#define MAX_FEATURE_SET_CONCURRRENT_GROUPS  3
++
++extern int dhd_dev_get_feature_set(struct net_device *dev);
++extern int dhd_dev_get_feature_set_matrix(struct net_device *dev, int num);
++extern int dhd_dev_cfg_rand_mac_oui(struct net_device *dev, uint8 *oui);
++#ifdef CUSTOM_FORCE_NODFS_FLAG
++extern int dhd_dev_set_nodfs(struct net_device *dev, uint nodfs);
++#endif /* CUSTOM_FORCE_NODFS_FLAG */
++
++#ifdef NDO_CONFIG_SUPPORT
++#ifndef NDO_MAX_HOST_IP_ENTRIES
++#define NDO_MAX_HOST_IP_ENTRIES	10
++#endif /* NDO_MAX_HOST_IP_ENTRIES */
++extern int dhd_dev_ndo_cfg(struct net_device *dev, u8 enable);
++extern int dhd_dev_ndo_update_inet6addr(struct net_device * dev);
++#endif /* NDO_CONFIG_SUPPORT */
++extern int dhd_set_rand_mac_oui(dhd_pub_t *dhd);
++#ifdef GSCAN_SUPPORT
++extern int dhd_dev_set_lazy_roam_cfg(struct net_device *dev,
++             wlc_roam_exp_params_t *roam_param);
++extern int dhd_dev_lazy_roam_enable(struct net_device *dev, uint32 enable);
++extern int dhd_dev_set_lazy_roam_bssid_pref(struct net_device *dev,
++       wl_bssid_pref_cfg_t *bssid_pref, uint32 flush);
++extern int dhd_dev_set_blacklist_bssid(struct net_device *dev, maclist_t *blacklist,
++    uint32 len, uint32 flush);
++extern int dhd_dev_set_whitelist_ssid(struct net_device *dev, wl_ssid_whitelist_t *whitelist,
++    uint32 len, uint32 flush);
++#endif /* GSCAN_SUPPORT */
++
++/* OS independent layer functions */
++extern void dhd_os_dhdiovar_lock(dhd_pub_t *pub);
++extern void dhd_os_dhdiovar_unlock(dhd_pub_t *pub);
++extern int dhd_os_proto_block(dhd_pub_t * pub);
++extern int dhd_os_proto_unblock(dhd_pub_t * pub);
++extern int dhd_os_ioctl_resp_wait(dhd_pub_t * pub, uint * condition);
++extern int dhd_os_ioctl_resp_wake(dhd_pub_t * pub);
++extern unsigned int dhd_os_get_ioctl_resp_timeout(void);
++extern void dhd_os_set_ioctl_resp_timeout(unsigned int timeout_msec);
++extern void dhd_os_ioctl_resp_lock(dhd_pub_t * pub);
++extern void dhd_os_ioctl_resp_unlock(dhd_pub_t * pub);
++#ifdef PCIE_FULL_DONGLE
++extern void dhd_wakeup_ioctl_event(dhd_pub_t *pub, dhd_ioctl_recieved_status_t reason);
++#else
++static INLINE void dhd_wakeup_ioctl_event(dhd_pub_t *pub, dhd_ioctl_recieved_status_t reason)
++{ printf("%s is NOT implemented for SDIO", __FUNCTION__); return; }
++#endif
++#ifdef SHOW_LOGTRACE
++extern int dhd_os_read_file(void *file, char *buf, uint32 size);
++extern int dhd_os_seek_file(void *file, int64 offset);
++#endif /* SHOW_LOGTRACE */
++
++extern void
++dhd_pcie_dump_core_regs(dhd_pub_t * pub, uint32 index, uint32 first_addr, uint32 last_addr);
++extern void wl_dhdpcie_dump_regs(void * context);
++
++#define DHD_OS_IOCTL_RESP_LOCK(x)
++#define DHD_OS_IOCTL_RESP_UNLOCK(x)
++
++
++extern int dhd_os_get_image_block(char * buf, int len, void * image);
++extern int dhd_os_get_image_size(void * image);
++#if defined(BT_OVER_SDIO)
++extern int dhd_os_gets_image(dhd_pub_t *pub, char *str, int len, void *image);
++extern void dhdsdio_bus_usr_cnt_inc(dhd_pub_t *pub);
++extern void dhdsdio_bus_usr_cnt_dec(dhd_pub_t *pub);
++#endif /* (BT_OVER_SDIO) */
++extern void * dhd_os_open_image(char * filename);
++extern void dhd_os_close_image(void * image);
++extern void dhd_os_wd_timer(void *bus, uint wdtick);
++#ifdef DHD_PCIE_RUNTIMEPM
++extern void dhd_os_runtimepm_timer(void *bus, uint tick);
++#endif /* DHD_PCIE_RUNTIMEPM */
++extern void dhd_os_sdlock(dhd_pub_t * pub);
++extern void dhd_os_sdunlock(dhd_pub_t * pub);
++extern void dhd_os_sdlock_txq(dhd_pub_t * pub);
++extern void dhd_os_sdunlock_txq(dhd_pub_t * pub);
++extern void dhd_os_sdlock_rxq(dhd_pub_t * pub);
++extern void dhd_os_sdunlock_rxq(dhd_pub_t * pub);
++extern void dhd_os_sdlock_sndup_rxq(dhd_pub_t * pub);
++extern void dhd_os_tracelog(const char *format, ...);
++#ifdef DHDTCPACK_SUPPRESS
++extern unsigned long dhd_os_tcpacklock(dhd_pub_t *pub);
++extern void dhd_os_tcpackunlock(dhd_pub_t *pub, unsigned long flags);
++#endif /* DHDTCPACK_SUPPRESS */
++
++extern int dhd_customer_oob_irq_map(void *adapter, unsigned long *irq_flags_ptr);
++extern int dhd_customer_gpio_wlan_ctrl(void *adapter, int onoff);
++extern int dhd_custom_get_mac_address(void *adapter, unsigned char *buf);
++#if defined(CUSTOM_COUNTRY_CODE)
++extern void get_customized_country_code(void *adapter, char *country_iso_code,
++	wl_country_t *cspec, u32 flags);
++#else
++extern void get_customized_country_code(void *adapter, char *country_iso_code, wl_country_t *cspec);
++#endif /* CUSTOM_COUNTRY_CODE */
++extern void dhd_os_sdunlock_sndup_rxq(dhd_pub_t * pub);
++extern void dhd_os_sdlock_eventq(dhd_pub_t * pub);
++extern void dhd_os_sdunlock_eventq(dhd_pub_t * pub);
++extern bool dhd_os_check_hang(dhd_pub_t *dhdp, int ifidx, int ret);
++extern int dhd_os_send_hang_message(dhd_pub_t *dhdp);
++extern void dhd_set_version_info(dhd_pub_t *pub, char *fw);
++extern bool dhd_os_check_if_up(dhd_pub_t *pub);
++extern int dhd_os_check_wakelock(dhd_pub_t *pub);
++extern int dhd_os_check_wakelock_all(dhd_pub_t *pub);
++extern int dhd_get_instance(dhd_pub_t *pub);
++#ifdef CUSTOM_SET_CPUCORE
++extern void dhd_set_cpucore(dhd_pub_t *dhd, int set);
++#endif /* CUSTOM_SET_CPUCORE */
++
++#if defined(KEEP_ALIVE)
++extern int dhd_keep_alive_onoff(dhd_pub_t *dhd);
++#endif /* KEEP_ALIVE */
++
++#if defined(DHD_FW_COREDUMP)
++void dhd_schedule_memdump(dhd_pub_t *dhdp, uint8 *buf, uint32 size);
++#endif /* DHD_FW_COREDUMP */
++
++void dhd_schedule_sssr_dump(dhd_pub_t *dhdp);
++
++#ifdef SUPPORT_AP_POWERSAVE
++extern int dhd_set_ap_powersave(dhd_pub_t *dhdp, int ifidx, int enable);
++#endif /* SUPPORT_AP_POWERSAVE */
++
++#ifdef PKT_FILTER_SUPPORT
++#define DHD_UNICAST_FILTER_NUM		0
++#define DHD_BROADCAST_FILTER_NUM	1
++#define DHD_MULTICAST4_FILTER_NUM	2
++#define DHD_MULTICAST6_FILTER_NUM	3
++#define DHD_MDNS_FILTER_NUM		4
++#define DHD_ARP_FILTER_NUM		5
++#define DHD_BROADCAST_ARP_FILTER_NUM	6
++#define DHD_IP4BCAST_DROP_FILTER_NUM	7
++#define DISCARD_IPV4_MCAST	"102 1 6 IP4_H:16 0xf0 0xe0"
++#define DISCARD_IPV6_MCAST	"103 1 6 IP6_H:24 0xff 0xff"
++extern int dhd_os_enable_packet_filter(dhd_pub_t *dhdp, int val);
++extern void dhd_enable_packet_filter(int value, dhd_pub_t *dhd);
++extern int dhd_packet_filter_add_remove(dhd_pub_t *dhdp, int add_remove, int num);
++extern int net_os_enable_packet_filter(struct net_device *dev, int val);
++extern int net_os_rxfilter_add_remove(struct net_device *dev, int val, int num);
++extern int net_os_set_suspend_bcn_li_dtim(struct net_device *dev, int val);
++#endif /* PKT_FILTER_SUPPORT */
++
++
++#if defined(BCMPCIE)
++extern int dhd_get_suspend_bcn_li_dtim(dhd_pub_t *dhd, int *dtim_period, int *bcn_interval);
++#else
++extern int dhd_get_suspend_bcn_li_dtim(dhd_pub_t *dhd);
++#endif /* OEM_ANDROID && BCMPCIE */
++
++extern bool dhd_support_sta_mode(dhd_pub_t *dhd);
++extern int write_to_file(dhd_pub_t *dhd, uint8 *buf, int size);
++
++#ifdef RSSI_MONITOR_SUPPORT
++extern int dhd_dev_set_rssi_monitor_cfg(struct net_device *dev, int start,
++             int8 max_rssi, int8 min_rssi);
++#endif /* RSSI_MONITOR_SUPPORT */
++
++#ifdef DHDTCPACK_SUPPRESS
++extern int dhd_dev_set_tcpack_sup_mode_cfg(struct net_device *dev, uint8 enable);
++#endif /* DHDTCPACK_SUPPRESS */
++
++#define DHD_RSSI_MONITOR_EVT_VERSION   1
++typedef struct {
++	uint8 version;
++	int8 cur_rssi;
++	struct ether_addr BSSID;
++} dhd_rssi_monitor_evt_t;
++
++typedef struct {
++	uint32 limit;		/* Expiration time (usec) */
++	uint32 increment;	/* Current expiration increment (usec) */
++	uint32 elapsed;		/* Current elapsed time (usec) */
++	uint32 tick;		/* O/S tick time (usec) */
++} dhd_timeout_t;
++
++#ifdef SHOW_LOGTRACE
++typedef struct {
++	int  num_fmts;
++	char **fmts;
++	char *raw_fmts;
++	char *raw_sstr;
++	uint32 fmts_size;
++	uint32 raw_fmts_size;
++	uint32 raw_sstr_size;
++	uint32 ramstart;
++	uint32 rodata_start;
++	uint32 rodata_end;
++	char *rom_raw_sstr;
++	uint32 rom_raw_sstr_size;
++	uint32 rom_ramstart;
++	uint32 rom_rodata_start;
++	uint32 rom_rodata_end;
++} dhd_event_log_t;
++#endif /* SHOW_LOGTRACE */
++
++#ifdef KEEP_ALIVE
++extern int dhd_dev_start_mkeep_alive(dhd_pub_t *dhd_pub, uint8 mkeep_alive_id, uint8 *ip_pkt,
++	uint16 ip_pkt_len, uint8* src_mac_addr, uint8* dst_mac_addr, uint32 period_msec);
++extern int dhd_dev_stop_mkeep_alive(dhd_pub_t *dhd_pub, uint8 mkeep_alive_id);
++#endif /* KEEP_ALIVE */
++
++#if defined(PKT_FILTER_SUPPORT) && defined(APF)
++/*
++ * As per Google's current implementation, there will be only one APF filter.
++ * Therefore, userspace doesn't bother about filter id and because of that
++ * DHD has to manage the filter id.
++ */
++#define PKT_FILTER_APF_ID		200
++#define DHD_APF_LOCK(ndev)		dhd_apf_lock(ndev)
++#define DHD_APF_UNLOCK(ndev)	dhd_apf_unlock(ndev)
++
++extern void dhd_apf_lock(struct net_device *dev);
++extern void dhd_apf_unlock(struct net_device *dev);
++extern int dhd_dev_apf_get_version(struct net_device *ndev, uint32 *version);
++extern int dhd_dev_apf_get_max_len(struct net_device *ndev, uint32 *max_len);
++extern int dhd_dev_apf_add_filter(struct net_device *ndev, u8* program,
++	uint32 program_len);
++extern int dhd_dev_apf_enable_filter(struct net_device *ndev);
++extern int dhd_dev_apf_disable_filter(struct net_device *ndev);
++extern int dhd_dev_apf_delete_filter(struct net_device *ndev);
++#endif /* PKT_FILTER_SUPPORT && APF */
++
++extern void dhd_timeout_start(dhd_timeout_t *tmo, uint usec);
++extern int dhd_timeout_expired(dhd_timeout_t *tmo);
++
++extern int dhd_ifname2idx(struct dhd_info *dhd, char *name);
++extern int dhd_net2idx(struct dhd_info *dhd, struct net_device *net);
++extern struct net_device * dhd_idx2net(void *pub, int ifidx);
++extern int net_os_send_hang_message(struct net_device *dev);
++extern int net_os_send_hang_message_reason(struct net_device *dev, const char *string_num);
++extern bool dhd_wowl_cap(void *bus);
++extern int wl_host_event(dhd_pub_t *dhd_pub, int *idx, void *pktdata, uint pktlen,
++	wl_event_msg_t *, void **data_ptr,  void *);
++extern int wl_process_host_event(dhd_pub_t *dhd_pub, int *idx, void *pktdata, uint pktlen,
++	wl_event_msg_t *, void **data_ptr,  void *);
++extern void wl_event_to_host_order(wl_event_msg_t * evt);
++extern int wl_host_event_get_data(void *pktdata, uint pktlen, bcm_event_msg_u_t *evu);
++extern int dhd_wl_ioctl(dhd_pub_t *dhd_pub, int ifindex, wl_ioctl_t *ioc, void *buf, int len);
++extern int dhd_wl_ioctl_cmd(dhd_pub_t *dhd_pub, int cmd, void *arg, int len, uint8 set,
++                            int ifindex);
++extern int dhd_wl_ioctl_get_intiovar(dhd_pub_t *dhd_pub, char *name, uint *pval,
++	int cmd, uint8 set, int ifidx);
++extern int dhd_wl_ioctl_set_intiovar(dhd_pub_t *dhd_pub, char *name, uint val,
++	int cmd, uint8 set, int ifidx);
++extern void dhd_common_init(osl_t *osh);
++
++extern int dhd_do_driver_init(struct net_device *net);
++extern int dhd_event_ifadd(struct dhd_info *dhd, struct wl_event_data_if *ifevent,
++	char *name, uint8 *mac);
++extern int dhd_event_ifdel(struct dhd_info *dhd, struct wl_event_data_if *ifevent,
++	char *name, uint8 *mac);
++extern int dhd_event_ifchange(struct dhd_info *dhd, struct wl_event_data_if *ifevent,
++       char *name, uint8 *mac);
++#ifdef DHD_UPDATE_INTF_MAC
++extern int dhd_op_if_update(dhd_pub_t *dhdpub, int ifidx);
++#endif /* DHD_UPDATE_INTF_MAC */
++extern struct net_device* dhd_allocate_if(dhd_pub_t *dhdpub, int ifidx, const char *name,
++	uint8 *mac, uint8 bssidx, bool need_rtnl_lock, const char *dngl_name);
++extern int dhd_remove_if(dhd_pub_t *dhdpub, int ifidx, bool need_rtnl_lock);
++extern void dhd_vif_add(struct dhd_info *dhd, int ifidx, char * name);
++extern void dhd_vif_del(struct dhd_info *dhd, int ifidx);
++extern void dhd_event(struct dhd_info *dhd, char *evpkt, int evlen, int ifidx);
++extern void dhd_vif_sendup(struct dhd_info *dhd, int ifidx, uchar *cp, int len);
++
++/* Send packet to dongle via data channel */
++extern int dhd_sendpkt(dhd_pub_t *dhdp, int ifidx, void *pkt);
++
++/* send up locally generated event */
++extern void dhd_sendup_event_common(dhd_pub_t *dhdp, wl_event_msg_t *event, void *data);
++/* Send event to host */
++extern void dhd_sendup_event(dhd_pub_t *dhdp, wl_event_msg_t *event, void *data);
++#ifdef LOG_INTO_TCPDUMP
++extern void dhd_sendup_log(dhd_pub_t *dhdp, void *data, int len);
++#endif /* LOG_INTO_TCPDUMP */
++extern int dhd_bus_devreset(dhd_pub_t *dhdp, uint8 flag);
++extern uint dhd_bus_status(dhd_pub_t *dhdp);
++extern int  dhd_bus_start(dhd_pub_t *dhdp);
++extern int dhd_bus_suspend(dhd_pub_t *dhdpub);
++extern int dhd_bus_resume(dhd_pub_t *dhdpub, int stage);
++extern int dhd_bus_membytes(dhd_pub_t *dhdp, bool set, uint32 address, uint8 *data, uint size);
++extern void dhd_print_buf(void *pbuf, int len, int bytes_per_line);
++extern bool dhd_is_associated(dhd_pub_t *dhd, uint8 ifidx, int *retval);
++#if defined(BCMSDIO) || defined(BCMPCIE)
++extern uint dhd_bus_chip_id(dhd_pub_t *dhdp);
++extern uint dhd_bus_chiprev_id(dhd_pub_t *dhdp);
++extern uint dhd_bus_chippkg_id(dhd_pub_t *dhdp);
++#endif /* defined(BCMSDIO) || defined(BCMPCIE) */
++int dhd_bus_get_fw_mode(dhd_pub_t *dhdp);
++
++#if defined(KEEP_ALIVE)
++extern int dhd_keep_alive_onoff(dhd_pub_t *dhd);
++#endif /* KEEP_ALIVE */
++
++/* OS spin lock API */
++extern void *dhd_os_spin_lock_init(osl_t *osh);
++extern void dhd_os_spin_lock_deinit(osl_t *osh, void *lock);
++extern unsigned long dhd_os_spin_lock(void *lock);
++void dhd_os_spin_unlock(void *lock, unsigned long flags);
++
++#ifdef DHD_EFI
++extern int dhd_os_ds_enter_wait(dhd_pub_t * pub, uint * condition);
++extern int dhd_os_ds_enter_wake(dhd_pub_t * pub);
++#else
++static INLINE int dhd_os_ds_enter_wait(dhd_pub_t * pub, uint * condition)
++{ printf("%s is Not supported for this platform", __FUNCTION__); return 0; }
++static INLINE int dhd_os_ds_enter_wake(dhd_pub_t * pub)
++{ return 0; }
++#endif /* DHD_EFI */
++
++#ifdef PCIE_INB_DW
++extern int dhd_os_ds_exit_wait(dhd_pub_t * pub, uint * condition);
++extern int dhd_os_ds_exit_wake(dhd_pub_t * pub);
++#endif /* PCIE_INB_DW */
++extern int dhd_os_busbusy_wake(dhd_pub_t * pub);
++extern int dhd_os_busbusy_wait_condition(dhd_pub_t *pub, uint *var, uint condition);
++extern int dhd_os_busbusy_wait_negation(dhd_pub_t * pub, uint * condition);
++extern int dhd_os_d3ack_wait(dhd_pub_t * pub, uint * condition);
++extern int dhd_os_d3ack_wake(dhd_pub_t * pub);
++
++/*
++ * Manage sta objects in an interface. Interface is identified by an ifindex and
++ * sta(s) within an interfaces are managed using a MacAddress of the sta.
++ */
++struct dhd_sta;
++extern bool dhd_sta_associated(dhd_pub_t *dhdp, uint32 bssidx, uint8 *mac);
++extern struct dhd_sta *dhd_find_sta(void *pub, int ifidx, void *ea);
++extern struct dhd_sta *dhd_findadd_sta(void *pub, int ifidx, void *ea);
++extern void dhd_del_all_sta(void *pub, int ifidx);
++extern void dhd_del_sta(void *pub, int ifidx, void *ea);
++extern int dhd_get_ap_isolate(dhd_pub_t *dhdp, uint32 idx);
++extern int dhd_set_ap_isolate(dhd_pub_t *dhdp, uint32 idx, int val);
++#if defined(BCM_GMAC3)
++extern int dhd_set_dev_def(dhd_pub_t *dhdp, uint32 idx, int val);
++#endif
++extern int dhd_bssidx2idx(dhd_pub_t *dhdp, uint32 bssidx);
++extern struct net_device *dhd_linux_get_primary_netdev(dhd_pub_t *dhdp);
++
++extern bool dhd_is_concurrent_mode(dhd_pub_t *dhd);
++int dhd_iovar(dhd_pub_t *pub, int ifidx, char *name, char *param_buf, uint param_len,
++		char *res_buf, uint res_len, int set);
++extern int dhd_getiovar(dhd_pub_t *pub, int ifidx, char *name, char *cmd_buf,
++		uint cmd_len, char **resptr, uint resp_len);
++
++#ifdef DHD_MCAST_REGEN
++extern int dhd_get_mcast_regen_bss_enable(dhd_pub_t *dhdp, uint32 idx);
++extern int dhd_set_mcast_regen_bss_enable(dhd_pub_t *dhdp, uint32 idx, int val);
++#endif
++typedef enum cust_gpio_modes {
++	WLAN_RESET_ON,
++	WLAN_RESET_OFF,
++	WLAN_POWER_ON,
++	WLAN_POWER_OFF
++} cust_gpio_modes_t;
++
++typedef struct dmaxref_mem_map {
++	dhd_dma_buf_t *srcmem;
++	dhd_dma_buf_t *dstmem;
++} dmaxref_mem_map_t;
++
++extern int wl_iw_iscan_set_scan_broadcast_prep(struct net_device *dev, uint flag);
++extern int wl_iw_send_priv_event(struct net_device *dev, char *flag);
++/*
++ * Insmod parameters for debug/test
++ */
++
++/* Watchdog timer interval */
++extern uint dhd_watchdog_ms;
++extern bool dhd_os_wd_timer_enabled(void *bus);
++#ifdef DHD_PCIE_RUNTIMEPM
++extern uint dhd_runtimepm_ms;
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++/* Console output poll interval */
++extern uint dhd_console_ms;
++extern uint android_msg_level;
++extern uint config_msg_level;
++extern uint sd_msglevel;
++extern uint dump_msg_level;
++#ifdef BCMDBUS
++extern uint dbus_msglevel;
++#endif /* BCMDBUS */
++#ifdef WL_WIRELESS_EXT
++extern uint iw_msg_level;
++#endif
++#ifdef WL_CFG80211
++extern uint wl_dbg_level;
++#endif
++
++extern uint dhd_slpauto;
++
++/* Use interrupts */
++extern uint dhd_intr;
++
++/* Use polling */
++extern uint dhd_poll;
++
++/* ARP offload agent mode */
++extern uint dhd_arp_mode;
++
++/* ARP offload enable */
++extern uint dhd_arp_enable;
++
++/* Pkt filte enable control */
++extern uint dhd_pkt_filter_enable;
++
++/*  Pkt filter init setup */
++extern uint dhd_pkt_filter_init;
++
++/* Pkt filter mode control */
++extern uint dhd_master_mode;
++
++/* Roaming mode control */
++extern uint dhd_roam_disable;
++
++/* Roaming mode control */
++extern uint dhd_radio_up;
++
++/* Initial idletime ticks (may be -1 for immediate idle, 0 for no idle) */
++extern int dhd_idletime;
++#ifdef DHD_USE_IDLECOUNT
++#define DHD_IDLETIME_TICKS 5
++#else
++#define DHD_IDLETIME_TICKS 1
++#endif /* DHD_USE_IDLECOUNT */
++
++/* SDIO Drive Strength */
++extern uint dhd_sdiod_drive_strength;
++
++/* triggers bcm_bprintf to print to kernel log */
++extern bool bcm_bprintf_bypass;
++
++/* Override to force tx queueing all the time */
++extern uint dhd_force_tx_queueing;
++
++/* Default bcn_timeout value is 4 */
++#define DEFAULT_BCN_TIMEOUT_VALUE	4
++#ifndef CUSTOM_BCN_TIMEOUT_SETTING
++#define CUSTOM_BCN_TIMEOUT_SETTING	DEFAULT_BCN_TIMEOUT_VALUE
++#endif
++
++/* Default KEEP_ALIVE Period is 55 sec to prevent AP from sending Keep Alive probe frame */
++#define DEFAULT_KEEP_ALIVE_VALUE 	55000 /* msec */
++#ifndef CUSTOM_KEEP_ALIVE_SETTING
++#define CUSTOM_KEEP_ALIVE_SETTING 	DEFAULT_KEEP_ALIVE_VALUE
++#endif /* DEFAULT_KEEP_ALIVE_VALUE */
++
++#define NULL_PKT_STR	"null_pkt"
++
++/* hooks for custom glom setting option via Makefile */
++#define DEFAULT_GLOM_VALUE 	-1
++#ifndef CUSTOM_GLOM_SETTING
++#define CUSTOM_GLOM_SETTING 	DEFAULT_GLOM_VALUE
++#endif
++#define WL_AUTO_ROAM_TRIGGER -75
++/* hooks for custom Roaming Trigger  setting via Makefile */
++#define DEFAULT_ROAM_TRIGGER_VALUE -75 /* dBm default roam trigger all band */
++#define DEFAULT_ROAM_TRIGGER_SETTING 	-1
++#ifndef CUSTOM_ROAM_TRIGGER_SETTING
++#define CUSTOM_ROAM_TRIGGER_SETTING 	DEFAULT_ROAM_TRIGGER_VALUE
++#endif
++
++/* hooks for custom Roaming Romaing  setting via Makefile */
++#define DEFAULT_ROAM_DELTA_VALUE  10 /* dBm default roam delta all band */
++#define DEFAULT_ROAM_DELTA_SETTING 	-1
++#ifndef CUSTOM_ROAM_DELTA_SETTING
++#define CUSTOM_ROAM_DELTA_SETTING 	DEFAULT_ROAM_DELTA_VALUE
++#endif
++
++/* hooks for custom PNO Event wake lock to guarantee enough time
++	for the Platform to detect Event before system suspended
++*/
++#define DEFAULT_PNO_EVENT_LOCK_xTIME 	2 	/* multiplay of DHD_PACKET_TIMEOUT_MS */
++#ifndef CUSTOM_PNO_EVENT_LOCK_xTIME
++#define CUSTOM_PNO_EVENT_LOCK_xTIME	 DEFAULT_PNO_EVENT_LOCK_xTIME
++#endif
++/* hooks for custom dhd_dpc_prio setting option via Makefile */
++#define DEFAULT_DHP_DPC_PRIO  1
++#ifndef CUSTOM_DPC_PRIO_SETTING
++#define CUSTOM_DPC_PRIO_SETTING 	DEFAULT_DHP_DPC_PRIO
++#endif
++
++#ifndef CUSTOM_LISTEN_INTERVAL
++#define CUSTOM_LISTEN_INTERVAL 		LISTEN_INTERVAL
++#endif /* CUSTOM_LISTEN_INTERVAL */
++
++#define DEFAULT_SUSPEND_BCN_LI_DTIM		3
++#ifndef CUSTOM_SUSPEND_BCN_LI_DTIM
++#define CUSTOM_SUSPEND_BCN_LI_DTIM		DEFAULT_SUSPEND_BCN_LI_DTIM
++#endif
++
++#ifndef BCN_TIMEOUT_IN_SUSPEND
++#define BCN_TIMEOUT_IN_SUSPEND			6 /* bcn timeout value in suspend mode */
++#endif
++
++#ifndef CUSTOM_RXF_PRIO_SETTING
++#define CUSTOM_RXF_PRIO_SETTING		MAX((CUSTOM_DPC_PRIO_SETTING - 1), 1)
++#endif
++
++#define DEFAULT_WIFI_TURNOFF_DELAY		0
++#define WIFI_TURNOFF_DELAY		DEFAULT_WIFI_TURNOFF_DELAY
++
++#define DEFAULT_WIFI_TURNON_DELAY		200
++#ifndef WIFI_TURNON_DELAY
++#define WIFI_TURNON_DELAY		DEFAULT_WIFI_TURNON_DELAY
++#endif /* WIFI_TURNON_DELAY */
++
++#ifdef BCMSDIO
++#define DEFAULT_DHD_WATCHDOG_INTERVAL_MS	10 /* msec */
++#else
++#define DEFAULT_DHD_WATCHDOG_INTERVAL_MS	0 /* msec */
++#endif
++#ifndef CUSTOM_DHD_WATCHDOG_MS
++#define CUSTOM_DHD_WATCHDOG_MS			DEFAULT_DHD_WATCHDOG_INTERVAL_MS
++#endif /* DEFAULT_DHD_WATCHDOG_INTERVAL_MS */
++
++#define DEFAULT_ASSOC_RETRY_MAX			3
++#ifndef CUSTOM_ASSOC_RETRY_MAX
++#define CUSTOM_ASSOC_RETRY_MAX			DEFAULT_ASSOC_RETRY_MAX
++#endif /* DEFAULT_ASSOC_RETRY_MAX */
++
++#if defined(BCMSDIO) || defined(DISABLE_FRAMEBURST)
++#define DEFAULT_FRAMEBURST_SET			0
++#else
++#define DEFAULT_FRAMEBURST_SET			1
++#endif /* BCMSDIO */
++
++#ifndef CUSTOM_FRAMEBURST_SET
++#define CUSTOM_FRAMEBURST_SET			DEFAULT_FRAMEBURST_SET
++#endif /* CUSTOM_FRAMEBURST_SET */
++
++#ifdef WLTDLS
++#ifndef CUSTOM_TDLS_IDLE_MODE_SETTING
++#define CUSTOM_TDLS_IDLE_MODE_SETTING  60000 /* 60sec to tear down TDLS of not active */
++#endif
++#ifndef CUSTOM_TDLS_RSSI_THRESHOLD_HIGH
++#define CUSTOM_TDLS_RSSI_THRESHOLD_HIGH -70 /* rssi threshold for establishing TDLS link */
++#endif
++#ifndef CUSTOM_TDLS_RSSI_THRESHOLD_LOW
++#define CUSTOM_TDLS_RSSI_THRESHOLD_LOW -80 /* rssi threshold for tearing down TDLS link */
++#endif
++#endif /* WLTDLS */
++
++#if defined(VSDB) || defined(ROAM_ENABLE)
++#define DEFAULT_BCN_TIMEOUT            8
++#else
++#define DEFAULT_BCN_TIMEOUT            4
++#endif 
++
++#ifndef CUSTOM_BCN_TIMEOUT
++#define CUSTOM_BCN_TIMEOUT             DEFAULT_BCN_TIMEOUT
++#endif
++
++#define MAX_DTIM_SKIP_BEACON_INTERVAL	100 /* max allowed associated AP beacon for DTIM skip */
++#ifndef MAX_DTIM_ALLOWED_INTERVAL
++#define MAX_DTIM_ALLOWED_INTERVAL 600 /* max allowed total beacon interval for DTIM skip */
++#endif
++
++#ifndef MIN_DTIM_FOR_ROAM_THRES_EXTEND
++#define MIN_DTIM_FOR_ROAM_THRES_EXTEND	600 /* minimum dtim interval to extend roam threshold */
++#endif
++
++#define NO_DTIM_SKIP 1
++#ifdef SDTEST
++/* Echo packet generator (SDIO), pkts/s */
++extern uint dhd_pktgen;
++
++/* Echo packet len (0 => sawtooth, max 1800) */
++extern uint dhd_pktgen_len;
++#define MAX_PKTGEN_LEN 1800
++#endif
++
++
++/* optionally set by a module_param_string() */
++#define MOD_PARAM_PATHLEN	2048
++#define MOD_PARAM_INFOLEN	512
++#define MOD_PARAM_SRLEN	64
++
++#ifdef SOFTAP
++extern char fw_path2[MOD_PARAM_PATHLEN];
++#endif
++
++#ifdef DHD_LEGACY_FILE_PATH
++#define PLATFORM_PATH	"/data/"
++#elif defined(PLATFORM_SLP)
++#define PLATFORM_PATH	"/opt/etc/"
++#else
++#define PLATFORM_PATH	"/data/misc/conn/"
++#endif /* DHD_LEGACY_FILE_PATH */
++
++/* Flag to indicate if we should download firmware on driver load */
++extern uint dhd_download_fw_on_driverload;
++#ifndef BCMDBUS
++extern int allow_delay_fwdl;
++#endif /* !BCMDBUS */
++
++extern int dhd_process_cid_mac(dhd_pub_t *dhdp, bool prepost);
++extern int dhd_write_file(const char *filepath, char *buf, int buf_len);
++extern int dhd_read_file(const char *filepath, char *buf, int buf_len);
++extern int dhd_write_file_and_check(const char *filepath, char *buf, int buf_len);
++
++#ifdef READ_MACADDR
++extern int dhd_set_macaddr_from_file(dhd_pub_t *dhdp);
++#else
++static INLINE int dhd_set_macaddr_from_file(dhd_pub_t *dhdp) { return 0; }
++#endif /* READ_MACADDR */
++#ifdef WRITE_MACADDR
++extern int dhd_write_macaddr(struct ether_addr *mac);
++#else
++static INLINE int dhd_write_macaddr(struct ether_addr *mac) { return 0; }
++#endif /* WRITE_MACADDR */
++static INLINE int dhd_check_module_cid(dhd_pub_t *dhdp) { return 0; }
++#ifdef GET_MAC_FROM_OTP
++extern int dhd_check_module_mac(dhd_pub_t *dhdp);
++#else
++static INLINE int dhd_check_module_mac(dhd_pub_t *dhdp) { return 0; }
++#endif /* GET_MAC_FROM_OTP */
++
++#if defined(READ_MACADDR) || defined(WRITE_MACADDR) || defined(GET_MAC_FROM_OTP)
++#define DHD_USE_CISINFO
++#endif 
++
++#ifdef DHD_USE_CISINFO
++int dhd_read_cis(dhd_pub_t *dhdp);
++void dhd_clear_cis(dhd_pub_t *dhdp);
++#else
++static INLINE int dhd_read_cis(dhd_pub_t *dhdp) { return 0; }
++static INLINE void dhd_clear_cis(dhd_pub_t *dhdp) { }
++#endif /* DHD_USE_CISINFO */
++
++#define IBSS_COALESCE_DEFAULT 1
++#define IBSS_INITIAL_SCAN_ALLOWED_DEFAULT 1
++
++
++extern void dhd_wait_for_event(dhd_pub_t *dhd, bool *lockvar);
++extern void dhd_wait_event_wakeup(dhd_pub_t*dhd);
++
++#define IFLOCK_INIT(lock)       *lock = 0
++#define IFLOCK(lock)    while (InterlockedCompareExchange((lock), 1, 0))	\
++	NdisStallExecution(1);
++#define IFUNLOCK(lock)  InterlockedExchange((lock), 0)
++#define IFLOCK_FREE(lock)
++#define FW_SUPPORTED(dhd, capa) ((strstr(dhd->fw_capabilities, " " #capa " ") != NULL))
++#ifdef ARP_OFFLOAD_SUPPORT
++#define MAX_IPV4_ENTRIES	8
++void dhd_arp_offload_set(dhd_pub_t * dhd, int arp_mode);
++void dhd_arp_offload_enable(dhd_pub_t * dhd, int arp_enable);
++
++/* dhd_commn arp offload wrapers */
++void dhd_aoe_hostip_clr(dhd_pub_t *dhd, int idx);
++void dhd_aoe_arp_clr(dhd_pub_t *dhd, int idx);
++int dhd_arp_get_arp_hostip_table(dhd_pub_t *dhd, void *buf, int buflen, int idx);
++void dhd_arp_offload_add_ip(dhd_pub_t *dhd, uint32 ipaddr, int idx);
++#endif /* ARP_OFFLOAD_SUPPORT */
++#ifdef WLTDLS
++int dhd_tdls_enable(struct net_device *dev, bool tdls_on, bool auto_on, struct ether_addr *mac);
++int dhd_tdls_set_mode(dhd_pub_t *dhd, bool wfd_mode);
++#ifdef PCIE_FULL_DONGLE
++int dhd_tdls_update_peer_info(dhd_pub_t *dhdp, wl_event_msg_t *event);
++int dhd_tdls_event_handler(dhd_pub_t *dhd_pub, wl_event_msg_t *event);
++int dhd_free_tdls_peer_list(dhd_pub_t *dhd_pub);
++#endif /* PCIE_FULL_DONGLE */
++#endif /* WLTDLS */
++
++/* Neighbor Discovery Offload Support */
++extern int dhd_ndo_enable(dhd_pub_t * dhd, int ndo_enable);
++int dhd_ndo_add_ip(dhd_pub_t *dhd, char* ipaddr, int idx);
++int dhd_ndo_remove_ip(dhd_pub_t *dhd, int idx);
++
++/* Enhanced ND offload support */
++uint16 dhd_ndo_get_version(dhd_pub_t *dhdp);
++int dhd_ndo_add_ip_with_type(dhd_pub_t *dhdp, char *ipv6addr, uint8 type, int idx);
++int dhd_ndo_remove_ip_by_addr(dhd_pub_t *dhdp, char *ipv6addr, int idx);
++int dhd_ndo_remove_ip_by_type(dhd_pub_t *dhdp, uint8 type, int idx);
++int dhd_ndo_unsolicited_na_filter_enable(dhd_pub_t *dhdp, int enable);
++
++/* ioctl processing for nl80211 */
++int dhd_ioctl_process(dhd_pub_t *pub, int ifidx, struct dhd_ioctl *ioc, void *data_buf);
++
++void dhd_bus_update_fw_nv_path(struct dhd_bus *bus, char *pfw_path, char *pnv_path,
++											char *pclm_path, char *pconf_path);
++void dhd_set_bus_state(void *bus, uint32 state);
++
++/* Remove proper pkts(either one no-frag pkt or whole fragmented pkts) */
++typedef int (*f_droppkt_t)(dhd_pub_t *dhdp, int prec, void* p, bool bPktInQ);
++extern bool dhd_prec_drop_pkts(dhd_pub_t *dhdp, struct pktq *pq, int prec, f_droppkt_t fn);
++
++#ifdef PROP_TXSTATUS
++int dhd_os_wlfc_block(dhd_pub_t *pub);
++int dhd_os_wlfc_unblock(dhd_pub_t *pub);
++extern const uint8 prio2fifo[];
++#endif /* PROP_TXSTATUS */
++
++int dhd_os_socram_dump(struct net_device *dev, uint32 *dump_size);
++int dhd_os_get_socram_dump(struct net_device *dev, char **buf, uint32 *size);
++int dhd_common_socram_dump(dhd_pub_t *dhdp);
++
++int dhd_os_get_version(struct net_device *dev, bool dhd_ver, char **buf, uint32 size);
++
++uint8* dhd_os_prealloc(dhd_pub_t *dhdpub, int section, uint size, bool kmalloc_if_fail);
++void dhd_os_prefree(dhd_pub_t *dhdpub, void *addr, uint size);
++
++#if defined(CONFIG_DHD_USE_STATIC_BUF)
++#define DHD_OS_PREALLOC(dhdpub, section, size) dhd_os_prealloc(dhdpub, section, size, FALSE)
++#define DHD_OS_PREFREE(dhdpub, addr, size) dhd_os_prefree(dhdpub, addr, size)
++#else
++#define DHD_OS_PREALLOC(dhdpub, section, size) MALLOC(dhdpub->osh, size)
++#define DHD_OS_PREFREE(dhdpub, addr, size) MFREE(dhdpub->osh, addr, size)
++#endif /* defined(CONFIG_DHD_USE_STATIC_BUF) */
++
++#ifdef USE_WFA_CERT_CONF
++enum {
++	SET_PARAM_BUS_TXGLOM_MODE,
++	SET_PARAM_ROAMOFF,
++#ifdef USE_WL_FRAMEBURST
++	SET_PARAM_FRAMEBURST,
++#endif /* USE_WL_FRAMEBURST */
++#ifdef USE_WL_TXBF
++	SET_PARAM_TXBF,
++#endif /* USE_WL_TXBF */
++#ifdef PROP_TXSTATUS
++	SET_PARAM_PROPTX,
++	SET_PARAM_PROPTXMODE,
++#endif /* PROP_TXSTATUS */
++	PARAM_LAST_VALUE
++};
++extern int sec_get_param_wfa_cert(dhd_pub_t *dhd, int mode, uint* read_val);
++#endif /* USE_WFA_CERT_CONF */
++
++#define dhd_add_flowid(pub, ifidx, ac_prio, ea, flowid)  do {} while (0)
++#define dhd_del_flowid(pub, ifidx, flowid)               do {} while (0)
++bool dhd_wet_chainable(dhd_pub_t *dhdp);
++
++extern unsigned long dhd_os_general_spin_lock(dhd_pub_t *pub);
++extern void dhd_os_general_spin_unlock(dhd_pub_t *pub, unsigned long flags);
++
++/** Miscellaenous DHD Spin Locks */
++
++/* Disable router 3GMAC bypass path perimeter lock */
++#define DHD_PERIM_LOCK(dhdp)              do {} while (0)
++#define DHD_PERIM_UNLOCK(dhdp)            do {} while (0)
++#define DHD_PERIM_LOCK_ALL(processor_id)    do {} while (0)
++#define DHD_PERIM_UNLOCK_ALL(processor_id)  do {} while (0)
++
++/* Enable DHD general spin lock/unlock */
++#define DHD_GENERAL_LOCK(dhdp, flags) \
++	(flags) = dhd_os_general_spin_lock(dhdp)
++#define DHD_GENERAL_UNLOCK(dhdp, flags) \
++	dhd_os_general_spin_unlock((dhdp), (flags))
++
++/* Enable DHD timer spin lock/unlock */
++#define DHD_TIMER_LOCK(lock, flags)     (flags) = dhd_os_spin_lock(lock)
++#define DHD_TIMER_UNLOCK(lock, flags)   dhd_os_spin_unlock(lock, (flags))
++
++/* Enable DHD flowring spin lock/unlock */
++#define DHD_FLOWRING_LOCK(lock, flags)     (flags) = dhd_os_spin_lock(lock)
++#define DHD_FLOWRING_UNLOCK(lock, flags)   dhd_os_spin_unlock((lock), (flags))
++
++/* Enable DHD common flowring info spin lock/unlock */
++#define DHD_FLOWID_LOCK(lock, flags)       (flags) = dhd_os_spin_lock(lock)
++#define DHD_FLOWID_UNLOCK(lock, flags)     dhd_os_spin_unlock((lock), (flags))
++
++/* Enable DHD common flowring list spin lock/unlock */
++#define DHD_FLOWRING_LIST_LOCK(lock, flags)       (flags) = dhd_os_spin_lock(lock)
++#define DHD_FLOWRING_LIST_UNLOCK(lock, flags)     dhd_os_spin_unlock((lock), (flags))
++
++#define DHD_SPIN_LOCK(lock, flags)	(flags) = dhd_os_spin_lock(lock)
++#define DHD_SPIN_UNLOCK(lock, flags)	dhd_os_spin_unlock((lock), (flags))
++
++#define DHD_BUS_INB_DW_LOCK(lock, flags)	(flags) = dhd_os_spin_lock(lock)
++#define DHD_BUS_INB_DW_UNLOCK(lock, flags)	dhd_os_spin_unlock((lock), (flags))
++
++/* Enable DHD TDLS peer list spin lock/unlock */
++#ifdef WLTDLS
++#define DHD_TDLS_LOCK(lock, flags)       (flags) = dhd_os_spin_lock(lock)
++#define DHD_TDLS_UNLOCK(lock, flags)     dhd_os_spin_unlock((lock), (flags))
++#endif /* WLTDLS */
++
++#ifdef DBG_PKT_MON
++/* Enable DHD PKT MON spin lock/unlock */
++#define DHD_PKT_MON_LOCK(lock, flags)     (flags) = dhd_os_spin_lock(lock)
++#define DHD_PKT_MON_UNLOCK(lock, flags)   dhd_os_spin_unlock(lock, (flags))
++#endif /* DBG_PKT_MON */
++
++#define DHD_LINUX_GENERAL_LOCK(dhdp, flags)	DHD_GENERAL_LOCK(dhdp, flags)
++#define DHD_LINUX_GENERAL_UNLOCK(dhdp, flags)	DHD_GENERAL_UNLOCK(dhdp, flags)
++
++extern void dhd_dump_to_kernelog(dhd_pub_t *dhdp);
++
++#ifdef BCMDBUS
++extern uint dhd_get_rxsz(dhd_pub_t *pub);
++extern void dhd_set_path(dhd_pub_t *pub);
++extern void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf);
++extern void dhd_bus_clearcounts(dhd_pub_t *dhdp);
++#endif /* BCMDBUS */
++
++#ifdef DHD_L2_FILTER
++extern int dhd_get_parp_status(dhd_pub_t *dhdp, uint32 idx);
++extern int dhd_set_parp_status(dhd_pub_t *dhdp, uint32 idx, int val);
++extern int dhd_get_dhcp_unicast_status(dhd_pub_t *dhdp, uint32 idx);
++extern int dhd_set_dhcp_unicast_status(dhd_pub_t *dhdp, uint32 idx, int val);
++extern int dhd_get_block_ping_status(dhd_pub_t *dhdp, uint32 idx);
++extern int dhd_set_block_ping_status(dhd_pub_t *dhdp, uint32 idx, int val);
++extern int dhd_get_grat_arp_status(dhd_pub_t *dhdp, uint32 idx);
++extern int dhd_set_grat_arp_status(dhd_pub_t *dhdp, uint32 idx, int val);
++#endif /* DHD_L2_FILTER */
++
++
++typedef struct wl_io_pport {
++	dhd_pub_t *dhd_pub;
++	uint ifidx;
++} wl_io_pport_t;
++
++typedef struct wl_evt_pport {
++	dhd_pub_t *dhd_pub;
++	int *ifidx;
++	void *pktdata;
++	uint data_len;
++	void **data_ptr;
++	void *raw_event;
++} wl_evt_pport_t;
++
++extern void *dhd_pub_shim(dhd_pub_t *dhd_pub);
++#ifdef DHD_FW_COREDUMP
++void* dhd_get_fwdump_buf(dhd_pub_t *dhd_pub, uint32 length);
++#endif /* DHD_FW_COREDUMP */
++
++#if defined(SET_RPS_CPUS)
++int dhd_rps_cpus_enable(struct net_device *net, int enable);
++int custom_rps_map_set(struct netdev_rx_queue *queue, char *buf, size_t len);
++void custom_rps_map_clear(struct netdev_rx_queue *queue);
++#define PRIMARY_INF 0
++#define VIRTUAL_INF 1
++#if defined(CONFIG_MACH_UNIVERSAL5433) || defined(CONFIG_MACH_UNIVERSAL7420) || \
++	defined(CONFIG_SOC_EXYNOS8890)
++#define RPS_CPUS_MASK "10"
++#define RPS_CPUS_MASK_P2P "10"
++#define RPS_CPUS_MASK_IBSS "10"
++#define RPS_CPUS_WLAN_CORE_ID 4
++#else
++#define RPS_CPUS_MASK "6"
++#define RPS_CPUS_MASK_P2P "6"
++#define RPS_CPUS_MASK_IBSS "6"
++#endif /* CONFIG_MACH_UNIVERSAL5433 || CONFIG_MACH_UNIVERSAL7420 || CONFIG_SOC_EXYNOS8890 */
++#endif 
++
++int dhd_get_download_buffer(dhd_pub_t	*dhd, char *file_path, download_type_t component,
++	char ** buffer, int *length);
++
++void dhd_free_download_buffer(dhd_pub_t	*dhd, void *buffer, int length);
++
++int dhd_download_blob(dhd_pub_t *dhd, unsigned char *image,
++		uint32 len, char *iovar);
++
++int dhd_apply_default_clm(dhd_pub_t *dhd, char *clm_path);
++
++#ifdef SHOW_LOGTRACE
++int dhd_parse_logstrs_file(osl_t *osh, char *raw_fmts, int logstrs_size,
++		dhd_event_log_t *event_log);
++int dhd_parse_map_file(osl_t *osh, void *file, uint32 *ramstart,
++		uint32 *rodata_start, uint32 *rodata_end);
++#ifdef PCIE_FULL_DONGLE
++int dhd_event_logtrace_infobuf_pkt_process(dhd_pub_t *dhdp, void *pktbuf,
++		dhd_event_log_t *event_data);
++#endif /* PCIE_FULL_DONGLE */
++#endif /* SHOW_LOGTRACE */
++
++#define dhd_is_device_removed(x) FALSE
++#define dhd_os_ind_firmware_stall(x)
++
++#if defined(DHD_FW_COREDUMP)
++extern void dhd_get_memdump_info(dhd_pub_t *dhd);
++#endif /* defined(DHD_FW_COREDUMP) */
++#ifdef BCMASSERT_LOG
++extern void dhd_get_assert_info(dhd_pub_t *dhd);
++#else
++static INLINE void dhd_get_assert_info(dhd_pub_t *dhd) { }
++#endif /* BCMASSERT_LOG */
++
++#define DMAXFER_FREE(dhdp, dmap) dhd_schedule_dmaxfer_free(dhdp, dmap);
++
++#if defined(PCIE_FULL_DONGLE)
++extern void dmaxfer_free_prev_dmaaddr(dhd_pub_t *dhdp, dmaxref_mem_map_t *dmmap);
++void dhd_schedule_dmaxfer_free(dhd_pub_t *dhdp, dmaxref_mem_map_t *dmmap);
++#endif  /* PCIE_FULL_DONGLE */
++
++#define DHD_LB_STATS_NOOP	do { /* noop */ } while (0)
++#if defined(DHD_LB_STATS)
++#include <bcmutils.h>
++extern void dhd_lb_stats_init(dhd_pub_t *dhd);
++extern void dhd_lb_stats_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf);
++extern void dhd_lb_stats_update_napi_histo(dhd_pub_t *dhdp, uint32 count);
++extern void dhd_lb_stats_update_txc_histo(dhd_pub_t *dhdp, uint32 count);
++extern void dhd_lb_stats_update_rxc_histo(dhd_pub_t *dhdp, uint32 count);
++extern void dhd_lb_stats_txc_percpu_cnt_incr(dhd_pub_t *dhdp);
++extern void dhd_lb_stats_rxc_percpu_cnt_incr(dhd_pub_t *dhdp);
++#define DHD_LB_STATS_INIT(dhdp)	dhd_lb_stats_init(dhdp)
++#define DHD_LB_STATS_DEINIT(dhdp) dhd_lb_stats_deinit(dhdp)
++/* Reset is called from common layer so it takes dhd_pub_t as argument */
++#define DHD_LB_STATS_RESET(dhdp) dhd_lb_stats_init(dhdp)
++#define DHD_LB_STATS_CLR(x)	(x) = 0U
++#define DHD_LB_STATS_INCR(x)	(x) = (x) + 1
++#define DHD_LB_STATS_ADD(x, c)	(x) = (x) + (c)
++#define DHD_LB_STATS_PERCPU_ARR_INCR(x) \
++	{ \
++		int cpu = get_cpu(); put_cpu(); \
++		DHD_LB_STATS_INCR(x[cpu]); \
++	}
++#define DHD_LB_STATS_UPDATE_NAPI_HISTO(dhdp, x)	dhd_lb_stats_update_napi_histo(dhdp, x)
++#define DHD_LB_STATS_UPDATE_TXC_HISTO(dhdp, x)	dhd_lb_stats_update_txc_histo(dhdp, x)
++#define DHD_LB_STATS_UPDATE_RXC_HISTO(dhdp, x)	dhd_lb_stats_update_rxc_histo(dhdp, x)
++#define DHD_LB_STATS_TXC_PERCPU_CNT_INCR(dhdp)	dhd_lb_stats_txc_percpu_cnt_incr(dhdp)
++#define DHD_LB_STATS_RXC_PERCPU_CNT_INCR(dhdp)	dhd_lb_stats_rxc_percpu_cnt_incr(dhdp)
++#else /* !DHD_LB_STATS */
++#define DHD_LB_STATS_INIT(dhdp)	 DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_DEINIT(dhdp) DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_RESET(dhdp) DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_CLR(x)	 DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_INCR(x)	 DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_ADD(x, c)	 DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_PERCPU_ARR_INCR(x)	 DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_UPDATE_NAPI_HISTO(dhd, x) DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_UPDATE_TXC_HISTO(dhd, x) DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_UPDATE_RXC_HISTO(dhd, x) DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_TXC_PERCPU_CNT_INCR(dhdp) DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_RXC_PERCPU_CNT_INCR(dhdp) DHD_LB_STATS_NOOP
++#endif /* !DHD_LB_STATS */
++
++#ifdef DHD_SSSR_DUMP
++#define DHD_SSSR_MEMPOOL_SIZE	(1024 * 1024) /* 1MB size */
++extern int dhd_sssr_mempool_init(dhd_pub_t *dhd);
++extern void dhd_sssr_mempool_deinit(dhd_pub_t *dhd);
++extern int dhd_sssr_dump_init(dhd_pub_t *dhd);
++extern void dhd_sssr_dump_deinit(dhd_pub_t *dhd);
++#define DHD_SSSR_MEMPOOL_INIT(dhdp)	dhd_sssr_mempool_init(dhdp)
++#define DHD_SSSR_MEMPOOL_DEINIT(dhdp) dhd_sssr_mempool_deinit(dhdp)
++#define DHD_SSSR_DUMP_INIT(dhdp)	dhd_sssr_dump_init(dhdp)
++#define DHD_SSSR_DUMP_DEINIT(dhdp) dhd_sssr_dump_deinit(dhdp)
++#else
++#define DHD_SSSR_MEMPOOL_INIT(dhdp)	do { /* noop */ } while (0)
++#define DHD_SSSR_MEMPOOL_DEINIT(dhdp)	do { /* noop */ } while (0)
++#define DHD_SSSR_DUMP_INIT(dhdp)	do { /* noop */ } while (0)
++#define DHD_SSSR_DUMP_DEINIT(dhdp)	do { /* noop */ } while (0)
++#endif /* DHD_SSSR_DUMP */
++
++#ifdef SHOW_LOGTRACE
++void dhd_get_read_buf_ptr(dhd_pub_t *dhd_pub, trace_buf_info_t *read_buf_info);
++#endif /* SHOW_LOGTRACE */
++
++#ifdef BCMPCIE
++extern int dhd_prot_debug_info_print(dhd_pub_t *dhd);
++#else
++#define dhd_prot_debug_info_print(x)
++#endif /* BCMPCIE */
++
++extern bool dhd_prot_is_cmpl_ring_empty(dhd_pub_t *dhd, void *prot_info);
++
++bool dhd_fw_download_status(dhd_pub_t * dhd_pub);
++
++/* Bitmask used for Join Timeout */
++#define WLC_SSID_MASK          0x01
++#define WLC_WPA_MASK           0x02
++
++extern int dhd_start_join_timer(dhd_pub_t *pub);
++extern int dhd_stop_join_timer(dhd_pub_t *pub);
++extern int dhd_start_scan_timer(dhd_pub_t *pub);
++extern int dhd_stop_scan_timer(dhd_pub_t *pub);
++extern int dhd_start_cmd_timer(dhd_pub_t *pub);
++extern int dhd_stop_cmd_timer(dhd_pub_t *pub);
++extern int dhd_start_bus_timer(dhd_pub_t *pub);
++extern int dhd_stop_bus_timer(dhd_pub_t *pub);
++extern uint16 dhd_get_request_id(dhd_pub_t *pub);
++extern int dhd_set_request_id(dhd_pub_t *pub, uint16 id, uint32 cmd);
++extern void dhd_set_join_error(dhd_pub_t *pub, uint32 mask);
++extern void dhd_clear_join_error(dhd_pub_t *pub, uint32 mask);
++extern void dhd_get_scan_to_val(dhd_pub_t *pub, uint32 *to_val);
++extern void dhd_set_scan_to_val(dhd_pub_t *pub, uint32 to_val);
++extern void dhd_get_join_to_val(dhd_pub_t *pub, uint32 *to_val);
++extern void dhd_set_join_to_val(dhd_pub_t *pub, uint32 to_val);
++extern void dhd_get_cmd_to_val(dhd_pub_t *pub, uint32 *to_val);
++extern void dhd_set_cmd_to_val(dhd_pub_t *pub, uint32 to_val);
++extern void dhd_get_bus_to_val(dhd_pub_t *pub, uint32 *to_val);
++extern void dhd_set_bus_to_val(dhd_pub_t *pub, uint32 to_val);
++extern int dhd_start_timesync_timer(dhd_pub_t *pub);
++extern int dhd_stop_timesync_timer(dhd_pub_t *pub);
++
++#ifdef DHD_PKTID_AUDIT_ENABLED
++void dhd_pktid_error_handler(dhd_pub_t *dhdp);
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++#ifdef DHD_PCIE_RUNTIMEPM
++extern bool dhd_runtimepm_state(dhd_pub_t *dhd);
++extern bool dhd_runtime_bus_wake(struct dhd_bus *bus, bool wait, void *func_addr);
++extern bool dhdpcie_runtime_bus_wake(dhd_pub_t *dhdp, bool wait, void *func_addr);
++extern void dhdpcie_block_runtime_pm(dhd_pub_t *dhdp);
++extern bool dhdpcie_is_resume_done(dhd_pub_t *dhdp);
++extern void dhd_runtime_pm_disable(dhd_pub_t *dhdp);
++extern void dhd_runtime_pm_enable(dhd_pub_t *dhdp);
++/* Disable the Runtime PM and wake up if the bus is already in suspend */
++#define DHD_DISABLE_RUNTIME_PM(dhdp) \
++do { \
++	dhd_runtime_pm_disable(dhdp); \
++} while (0);
++
++/* Enable the Runtime PM */
++#define DHD_ENABLE_RUNTIME_PM(dhdp) \
++do { \
++	dhd_runtime_pm_enable(dhdp); \
++} while (0);
++#else
++#define DHD_DISABLE_RUNTIME_PM(dhdp)
++#define DHD_ENABLE_RUNTIME_PM(dhdp)
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++/*
++ * Enable this macro if you want to track the calls to wake lock
++ * This records can be printed using the following command
++ * cat /sys/bcm-dhd/wklock_trace
++ * DHD_TRACE_WAKE_LOCK supports over linux 2.6.0 version
++ */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
++#undef DHD_TRACE_WAKE_LOCK
++#endif /* KERNEL_VER < KERNEL_VERSION(2, 6, 0) */
++
++#if defined(DHD_TRACE_WAKE_LOCK)
++void dhd_wk_lock_stats_dump(dhd_pub_t *dhdp);
++#endif
++
++extern bool dhd_query_bus_erros(dhd_pub_t *dhdp);
++
++extern void init_dhd_timeouts(dhd_pub_t *pub);
++extern void deinit_dhd_timeouts(dhd_pub_t *pub);
++
++typedef enum timeout_resons {
++	DHD_REASON_COMMAND_TO,
++	DHD_REASON_JOIN_TO,
++	DHD_REASON_SCAN_TO,
++	DHD_REASON_OQS_TO
++} timeout_reasons_t;
++
++#if defined(PCIE_OOB) || defined(PCIE_INB_DW)
++extern int dhd_bus_set_device_wake(struct dhd_bus *bus, bool val);
++#endif /* defined(PCIE_OOB) || defined(PCIE_INB_DW) */
++
++#ifdef DHD_EFI
++extern void dhd_schedule_reset(dhd_pub_t *dhdp);
++#else
++static INLINE void dhd_schedule_reset(dhd_pub_t *dhdp) {;}
++#endif
++
++#ifdef ENABLE_TEMP_THROTTLING
++#ifndef TEMP_THROTTLE_CONTROL_BIT
++#define TEMP_THROTTLE_CONTROL_BIT 0xd
++#endif
++#endif /* ENABLE_TEMP_THROTTLING */
++
++int dhd_send_msg_to_daemon(struct sk_buff *skb, void *data, int size);
++#ifdef REPORT_FATAL_TIMEOUTS
++void dhd_send_trap_to_fw_for_timeout(dhd_pub_t * pub, timeout_reasons_t reason);
++#endif
++
++#if defined(CONFIG_64BIT)
++#define DHD_SUPPORT_64BIT
++#elif defined(DHD_EFI)
++#define DHD_SUPPORT_64BIT
++/* by default disabled for other platforms, can enable appropriate macro to enable 64 bit support */
++#endif /* (linux || LINUX) && CONFIG_64BIT */
++
++#ifdef SET_PCIE_IRQ_CPU_CORE
++extern void dhd_set_irq_cpucore(dhd_pub_t *dhdp, int set);
++extern void set_irq_cpucore(unsigned int irq, int set);
++#endif /* SET_PCIE_IRQ_CPU_CORE */
++#if defined(DHD_HANG_SEND_UP_TEST)
++extern void dhd_make_hang_with_reason(struct net_device *dev, const char *string_num);
++#endif /* DHD_HANG_SEND_UP_TEST */
++
++#if defined(DHD_BLOB_EXISTENCE_CHECK)
++extern void dhd_set_blob_support(dhd_pub_t *dhdp, char *fw_path);
++#endif /* DHD_BLOB_EXISTENCE_CHECK */
++
++#ifdef DHD_WAKE_STATUS
++wake_counts_t* dhd_get_wakecount(dhd_pub_t *dhdp);
++#endif /* DHD_WAKE_STATUS */
++
++#ifdef BCM_ASLR_HEAP
++extern uint32 dhd_get_random_number(void);
++#endif /* BCM_ASLR_HEAP */
++#endif /* _dhd_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_bus.h b/module_drivers/drivers/net/wireless/bcmdhd/dhd_bus.h
+new file mode 100644
+index 000000000..aa5ba6c14
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_bus.h
+@@ -0,0 +1,298 @@
++/*
++ * Header file describing the internal (inter-module) DHD interfaces.
++ *
++ * Provides type definitions and function prototypes used to link the
++ * DHD OS, bus, and protocol modules.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_bus.h 698895 2017-05-11 02:55:17Z $
++ */
++
++#ifndef _dhd_bus_h_
++#define _dhd_bus_h_
++
++extern int dbus_up(struct dhd_bus *pub);
++extern int dbus_stop(struct dhd_bus *pub);
++extern int dbus_send_ctl(struct dhd_bus *pub, uint8 *buf, int len);
++extern int dbus_recv_ctl(struct dhd_bus *pub, uint8 *buf, int len);
++/*
++ * Exported from dhd bus module (dhd_usb, dhd_sdio)
++ */
++
++/* Indicate (dis)interest in finding dongles. */
++extern int dhd_bus_register(void);
++extern void dhd_bus_unregister(void);
++
++/* Download firmware image and nvram image */
++extern int dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh,
++	char *fw_path, char *nv_path, char *clm_path, char *conf_path);
++#if defined(BT_OVER_SDIO)
++extern int dhd_bus_download_btfw(struct dhd_bus *bus, osl_t *osh, char *btfw_path);
++#endif /* defined (BT_OVER_SDIO) */
++
++/* Stop bus module: clear pending frames, disable data flow */
++extern void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex);
++
++/* Initialize bus module: prepare for communication w/dongle */
++extern int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex);
++
++/* Get the Bus Idle Time */
++extern void dhd_bus_getidletime(dhd_pub_t *dhdp, int *idletime);
++
++/* Set the Bus Idle Time */
++extern void dhd_bus_setidletime(dhd_pub_t *dhdp, int idle_time);
++
++/* Size of Extended Trap data Buffer */
++#ifdef BCMPCIE
++#define BCMPCIE_EXT_TRAP_DATA_MAXLEN  4096
++#endif
++
++/* Send a data frame to the dongle.  Callee disposes of txp. */
++#ifdef BCMPCIE
++extern int dhd_bus_txdata(struct dhd_bus *bus, void *txp, uint8 ifidx);
++#else
++extern int dhd_bus_txdata(struct dhd_bus *bus, void *txp);
++#endif
++
++extern struct device * dhd_bus_to_dev(struct dhd_bus *bus);
++
++/* Send/receive a control message to/from the dongle.
++ * Expects caller to enforce a single outstanding transaction.
++ */
++extern int dhd_bus_txctl(struct dhd_bus *bus, uchar *msg, uint msglen);
++extern int dhd_bus_rxctl(struct dhd_bus *bus, uchar *msg, uint msglen);
++
++/* Watchdog timer function */
++extern bool dhd_bus_watchdog(dhd_pub_t *dhd);
++
++extern int dhd_bus_oob_intr_register(dhd_pub_t *dhdp);
++extern void dhd_bus_oob_intr_unregister(dhd_pub_t *dhdp);
++extern void dhd_bus_oob_intr_set(dhd_pub_t *dhdp, bool enable);
++extern void dhd_bus_dev_pm_stay_awake(dhd_pub_t *dhdpub);
++extern void dhd_bus_dev_pm_relax(dhd_pub_t *dhdpub);
++extern bool dhd_bus_dev_pm_enabled(dhd_pub_t *dhdpub);
++
++/* Device console input function */
++extern int dhd_bus_console_in(dhd_pub_t *dhd, uchar *msg, uint msglen);
++#ifdef CONSOLE_DPC
++extern int dhd_bus_txcons(dhd_pub_t *dhd, uchar *msg, uint msglen);
++#endif
++
++/* Deferred processing for the bus, return TRUE requests reschedule */
++extern bool dhd_bus_dpc(struct dhd_bus *bus);
++extern void dhd_bus_isr(bool * InterruptRecognized, bool * QueueMiniportHandleInterrupt, void *arg);
++
++
++/* Check for and handle local prot-specific iovar commands */
++extern int dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
++                            void *params, int plen, void *arg, int len, bool set);
++
++/* Add bus dump output to a buffer */
++extern void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf);
++
++/* Clear any bus counters */
++extern void dhd_bus_clearcounts(dhd_pub_t *dhdp);
++
++/* return the dongle chipid */
++extern uint dhd_bus_chip(struct dhd_bus *bus);
++
++/* return the dongle chiprev */
++extern uint dhd_bus_chiprev(struct dhd_bus *bus);
++
++/* Set user-specified nvram parameters. */
++extern void dhd_bus_set_nvram_params(struct dhd_bus * bus, const char *nvram_params);
++
++extern void *dhd_bus_pub(struct dhd_bus *bus);
++extern void *dhd_bus_txq(struct dhd_bus *bus);
++extern const void *dhd_bus_sih(struct dhd_bus *bus);
++extern uint dhd_bus_hdrlen(struct dhd_bus *bus);
++#ifdef BCMSDIO
++extern void dhd_bus_set_dotxinrx(struct dhd_bus *bus, bool val);
++/* return sdio io status */
++extern uint8 dhd_bus_is_ioready(struct dhd_bus *bus);
++#else
++#define dhd_bus_set_dotxinrx(a, b) do {} while (0)
++#endif
++
++#define DHD_SET_BUS_STATE_DOWN(_bus)  do { \
++	(_bus)->dhd->busstate = DHD_BUS_DOWN; \
++} while (0)
++
++/* Register a dummy SDIO client driver in order to be notified of new SDIO device */
++extern int dhd_bus_reg_sdio_notify(void* semaphore);
++extern void dhd_bus_unreg_sdio_notify(void);
++extern void dhd_txglom_enable(dhd_pub_t *dhdp, bool enable);
++extern int dhd_bus_get_ids(struct dhd_bus *bus, uint32 *bus_type, uint32 *bus_num,
++	uint32 *slot_num);
++
++#if defined(DHD_FW_COREDUMP) && (defined(BCMPCIE) || defined(BCMSDIO))
++extern int dhd_bus_mem_dump(dhd_pub_t *dhd);
++#else
++#define dhd_bus_mem_dump(x)
++#endif /* DHD_FW_COREDUMP && (BCMPCIE || BCMSDIO) */
++
++#ifdef BCMPCIE
++enum {
++	/* Scratch buffer confiuguration update */
++	D2H_DMA_SCRATCH_BUF,
++	D2H_DMA_SCRATCH_BUF_LEN,
++
++	/* DMA Indices array buffers for: H2D WR and RD, and D2H WR and RD */
++	H2D_DMA_INDX_WR_BUF, /* update H2D WR dma indices buf base addr to dongle */
++	H2D_DMA_INDX_RD_BUF, /* update H2D RD dma indices buf base addr to dongle */
++	D2H_DMA_INDX_WR_BUF, /* update D2H WR dma indices buf base addr to dongle */
++	D2H_DMA_INDX_RD_BUF, /* update D2H RD dma indices buf base addr to dongle */
++
++	/* DHD sets/gets WR or RD index, in host's H2D and D2H DMA indices buffer */
++	H2D_DMA_INDX_WR_UPD, /* update H2D WR index in H2D WR dma indices buf */
++	H2D_DMA_INDX_RD_UPD, /* update H2D RD index in H2D RD dma indices buf */
++	D2H_DMA_INDX_WR_UPD, /* update D2H WR index in D2H WR dma indices buf */
++	D2H_DMA_INDX_RD_UPD, /* update D2H RD index in D2H RD dma indices buf */
++
++	/* DHD Indices array buffers and update for: H2D flow ring WR */
++	H2D_IFRM_INDX_WR_BUF, /* update H2D WR dma indices buf base addr to dongle */
++	H2D_IFRM_INDX_WR_UPD, /* update H2D WR dma indices buf base addr to dongle */
++
++	/* H2D and D2H Mailbox data update */
++	H2D_MB_DATA,
++	D2H_MB_DATA,
++
++	/* (Common) MsgBuf Ring configuration update */
++	RING_BUF_ADDR,       /* update ring base address to dongle */
++	RING_ITEM_LEN,       /* update ring item size to dongle */
++	RING_MAX_ITEMS,      /* update ring max items to dongle */
++
++	/* Update of WR or RD index, for a MsgBuf Ring */
++	RING_RD_UPD,         /* update ring read index from/to dongle */
++	RING_WR_UPD,         /* update ring write index from/to dongle */
++
++	TOTAL_LFRAG_PACKET_CNT,
++	MAX_HOST_RXBUFS,
++	HOST_API_VERSION,
++	DNGL_TO_HOST_TRAP_ADDR,
++#ifdef HOFFLOAD_MODULES
++	WRT_HOST_MODULE_ADDR
++#endif
++};
++
++typedef void (*dhd_mb_ring_t) (struct dhd_bus *, uint32);
++typedef void (*dhd_mb_ring_2_t) (struct dhd_bus *, uint32, bool);
++extern void dhd_bus_cmn_writeshared(struct dhd_bus *bus, void * data, uint32 len, uint8 type,
++	uint16 ringid);
++extern void dhd_bus_ringbell(struct dhd_bus *bus, uint32 value);
++extern void dhd_bus_ringbell_2(struct dhd_bus *bus, uint32 value, bool devwake);
++extern void dhd_bus_cmn_readshared(struct dhd_bus *bus, void* data, uint8 type, uint16 ringid);
++extern uint32 dhd_bus_get_sharedflags(struct dhd_bus *bus);
++extern void dhd_bus_rx_frame(struct dhd_bus *bus, void* pkt, int ifidx, uint pkt_count);
++extern void dhd_bus_start_queue(struct dhd_bus *bus);
++extern void dhd_bus_stop_queue(struct dhd_bus *bus);
++extern dhd_mb_ring_t dhd_bus_get_mbintr_fn(struct dhd_bus *bus);
++extern dhd_mb_ring_2_t dhd_bus_get_mbintr_2_fn(struct dhd_bus *bus);
++extern void dhd_bus_write_flow_ring_states(struct dhd_bus *bus,
++	void * data, uint16 flowid);
++extern void dhd_bus_read_flow_ring_states(struct dhd_bus *bus,
++	void * data, uint8 flowid);
++extern int dhd_bus_flow_ring_create_request(struct dhd_bus *bus, void *flow_ring_node);
++extern void dhd_bus_clean_flow_ring(struct dhd_bus *bus, void *flow_ring_node);
++extern void dhd_bus_flow_ring_create_response(struct dhd_bus *bus, uint16 flow_id, int32 status);
++extern int dhd_bus_flow_ring_delete_request(struct dhd_bus *bus, void *flow_ring_node);
++extern void dhd_bus_flow_ring_delete_response(struct dhd_bus *bus, uint16 flowid, uint32 status);
++extern int dhd_bus_flow_ring_flush_request(struct dhd_bus *bus, void *flow_ring_node);
++extern void dhd_bus_flow_ring_flush_response(struct dhd_bus *bus, uint16 flowid, uint32 status);
++extern uint32 dhd_bus_max_h2d_queues(struct dhd_bus *bus);
++extern int dhd_bus_schedule_queue(struct dhd_bus *bus, uint16 flow_id, bool txs);
++extern void dhd_bus_set_linkdown(dhd_pub_t *dhdp, bool val);
++
++#ifdef IDLE_TX_FLOW_MGMT
++extern void dhd_bus_flow_ring_resume_response(struct dhd_bus *bus, uint16 flowid, int32 status);
++#endif /* IDLE_TX_FLOW_MGMT */
++
++
++extern int dhdpcie_bus_clock_start(struct dhd_bus *bus);
++extern int dhdpcie_bus_clock_stop(struct dhd_bus *bus);
++extern int dhdpcie_bus_enable_device(struct dhd_bus *bus);
++extern int dhdpcie_bus_disable_device(struct dhd_bus *bus);
++extern int dhdpcie_bus_alloc_resource(struct dhd_bus *bus);
++extern void dhdpcie_bus_free_resource(struct dhd_bus *bus);
++extern bool dhdpcie_bus_dongle_attach(struct dhd_bus *bus);
++extern int dhd_bus_release_dongle(struct dhd_bus *bus);
++extern int dhd_bus_request_irq(struct dhd_bus *bus);
++extern int dhdpcie_get_pcieirq(struct dhd_bus *bus, unsigned int *irq);
++
++extern void dhdpcie_cto_init(struct dhd_bus *bus, bool enable);
++
++
++#ifdef DHD_FW_COREDUMP
++extern struct dhd_bus *g_dhd_bus;
++extern int dhd_dongle_mem_dump(void);
++#endif /* DHD_FW_COREDUMP */
++
++#ifdef IDLE_TX_FLOW_MGMT
++extern void dhd_bus_idle_tx_ring_suspend(dhd_pub_t *dhd, uint16 flow_ring_id);
++#endif /* IDLE_TX_FLOW_MGMT */
++extern void dhd_bus_handle_mb_data(struct dhd_bus *bus, uint32 d2h_mb_data);
++#endif /* BCMPCIE */
++
++/* dump the device trap informtation  */
++extern void dhd_bus_dump_trap_info(struct dhd_bus *bus, struct bcmstrbuf *b);
++
++/* Function to set default min res mask */
++extern bool dhd_bus_set_default_min_res_mask(struct dhd_bus *bus);
++
++/* Function to reset PMU registers */
++extern void dhd_bus_pmu_reg_reset(dhd_pub_t *dhdp);
++
++#ifdef DHD_ULP
++extern void dhd_bus_ulp_disable_console(dhd_pub_t *dhdp);
++extern void dhd_bus_ucode_download(struct dhd_bus *bus);
++#endif /* DHD_ULP */
++extern int dhd_bus_readwrite_bp_addr(dhd_pub_t *dhdp, uint addr, uint size, uint* data, bool read);
++
++#ifdef BT_OVER_SDIO
++/*
++ * SDIO layer clock control functions exposed to be called from other layers.
++ * This is required especially in the case where the BUS is shared between
++ * BT and SDIO and we have to control the clock. The callers of this function
++ * are expected to hold the sdlock
++ */
++int __dhdsdio_clk_enable(struct dhd_bus *bus, bus_owner_t owner, int can_wait);
++int __dhdsdio_clk_disable(struct dhd_bus *bus, bus_owner_t owner, int can_wait);
++void dhdsdio_reset_bt_use_count(struct dhd_bus *bus);
++#endif /* BT_OVER_SDIO */
++#ifdef BCMPCIE
++extern void dhd_bus_dump_console_buffer(struct dhd_bus *bus);
++#else
++#define dhd_bus_dump_console_buffer(x)
++#endif /* BCMPCIE */
++
++extern uint16 dhd_get_chipid(dhd_pub_t *dhd);
++
++extern int dhd_get_idletime(dhd_pub_t *dhd);
++
++#ifdef DHD_WAKE_STATUS
++extern wake_counts_t* dhd_bus_get_wakecount(dhd_pub_t *dhd);
++extern int dhd_bus_get_bus_wake(dhd_pub_t * dhd);
++#endif /* DHD_WAKE_STATUS */
++#endif /* _dhd_bus_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_buzzz.h b/module_drivers/drivers/net/wireless/bcmdhd/dhd_buzzz.h
+new file mode 100644
+index 000000000..e349a3f45
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_buzzz.h
+@@ -0,0 +1,37 @@
++#ifndef _DHD_BUZZZ_H_INCLUDED_
++#define _DHD_BUZZZ_H_INCLUDED_
++
++/*
++ * Broadcom logging system - Empty implementaiton
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id$
++ */
++
++#define dhd_buzzz_attach()              do { /* noop */ } while (0)
++#define dhd_buzzz_detach()              do { /* noop */ } while (0)
++#define dhd_buzzz_panic(x)              do { /* noop */ } while (0)
++#define BUZZZ_LOG(ID, N, ARG...)    do { /* noop */ } while (0)
++
++#endif /* _DHD_BUZZZ_H_INCLUDED_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_ccode.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_ccode.c
+new file mode 100644
+index 000000000..abf71ccd7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_ccode.c
+@@ -0,0 +1,234 @@
++
++#ifdef CCODE_LIST
++#ifdef CONFIG_COMPAT
++#include <linux/compat.h>
++#endif /* COMFIG_COMPAT */
++#include <typedefs.h>
++#include <dhd_config.h>
++
++#ifdef BCMSDIO
++#define CCODE_43438
++#define CCODE_43455C0
++#define CCODE_43456C5
++#endif
++#if defined(BCMSDIO) || defined(BCMPCIE)
++#define CCODE_4356A2
++#define CCODE_4359C0
++#endif
++#ifdef BCMDBUS
++#define CCODE_4358U
++#endif
++
++#ifdef BCMSDIO
++#ifdef CCODE_43438
++const char ccode_43438[] = "RU/13";
++#else
++const char ccode_43438 = "";
++#endif
++
++#ifdef CCODE_43455C0
++const char ccode_43455c0[] = \
++"AE/6 AG/2 AI/1 AL/2 AS/12 AT/4 AU/6 AW/2 AZ/2 "\
++"BA/2 BD/1 BE/4 BG/4 BH/4 BM/12 BN/4 BR/2 BS/2 BY/3 "\
++"CA/2 CA/31 CH/4 CN/38 CO/17 CR/17 CY/4 CZ/4 "\
++"DE/3 DE/7 DK/4 "\
++"EC/21 EE/4 EG/13 ES/4 ET/2 "\
++"FI/4 FR/5 "\
++"GB/1 GB/6 GD/2 GF/2 GP/2 GR/4 GT/1 GU/30 "\
++"HK/2 HR/4 HU/4 "\
++"ID/1 IE/5 IL/14 IN/3 IS/4 IT/4 "\
++"JO/3 JP/45 JP/58 "\
++"KH/2 KR/45 KR/48 KR/49 KR/70 KR/71 KR/96 KW/5 KY/3 "\
++"LA/2 LB/5 LI/4 LK/1 LS/2 LT/4 LU/3 LV/4 "\
++"MA/2 MC/1 MD/2 ME/2 MK/2 MN/1 MQ/2 MR/2 MT/4 MU/2 MV/3 MW/1 MX/44 MY/3 "\
++"NI/2 NL/4 NO/4 NZ/4 "\
++"OM/4 "\
++"PA/17 PE/20 PH/5 PL/4 PR/38 PT/4 PY/2 "\
++"Q2/993 "\
++"RE/2 RO/4 RS/2 RU/13 "\
++"SE/4 SI/4 SK/4 SV/25 "\
++"TH/5 TN/1 TR/7 TT/3 TW/1 "\
++"UA/8 US/988 "\
++"VA/2 VE/3 VG/2 VN/4 "\
++"XZ/11 "\
++"YT/2 "\
++"ZA/6";
++#else
++const char ccode_43455c0[] = "";
++#endif
++
++#ifdef CCODE_43456C5
++const char ccode_43456c5[] = \
++"AE/6 AG/2 AI/1 AL/2 AS/12 AT/4 AU/6 AW/2 AZ/2 "\
++"BA/2 BD/1 BE/4 BG/4 BH/4 BM/12 BN/4 BR/4 BS/2 BY/3 "\
++"CA/2 CH/4 CN/38 CO/17 CR/17 CY/4 CZ/4 "\
++"DE/7 DK/4 "\
++"EC/21 EE/4 EG/13 ES/4 ET/2 "\
++"FI/4 FR/5 "\
++"GB/6 GD/2 GF/2 GP/2 GR/4 GT/1 GU/30 "\
++"HK/2 HR/4 HU/4 "\
++"ID/1 IE/5 IL/14 IN/3 IS/4 IT/4 "\
++"JO/3 JP/58 "\
++"KH/2 KR/96 KW/5 KY/3 "\
++"LA/2 LB/5 LI/4 LK/1 LS/2 LT/4 LU/3 LV/4 "\
++"MA/2 MC/1 MD/2 ME/2 MK/2 MN/1 MQ/2 MR/2 MT/4 MU/2 MV/3 MW/1 MX/44 MY/3 "\
++"NI/2 NL/4 NO/4 NZ/4 "\
++"OM/4 "\
++"PA/17 PE/20 PH/5 PL/4 PR/38 PT/4 PY/2 "\
++"Q2/993 "\
++"RE/2 RO/4 RS/2 RU/13 "\
++"SE/4 SI/4 SK/4 SV/25 "\
++"TH/5 TN/1 TR/7 TT/3 TW/65 "\
++"UA/8 US/988 "\
++"VA/2 VE/3 VG/2 VN/4 "\
++"XZ/11 "\
++"YT/2 "\
++"ZA/6";
++#else
++const char ccode_43456c5[] = "";
++#endif
++#endif
++
++#ifdef CCODE_4356A2
++const char ccode_4356a2[] = \
++"AE/6 AG/2 AI/1 AL/2 AN/2 AR/21 AS/12 AT/4 AU/6 AW/2 AZ/2 "\
++"BA/2 BD/2 BE/4 BG/4 BH/4 BM/12 BN/4 BR/4 BS/2 BY/3 "\
++"CA/31 CH/4 CN/38 CO/17 CR/17 CY/4 CZ/4 "\
++"DE/7 DK/4 DZ/1 "\
++"EC/21 EE/4 ES/4 ET/2 "\
++"FI/4 FR/5 "\
++"GB/6 GD/2 GF/2 GP/2 GR/4 GT/1 GU/12 "\
++"HK/2 HR/4 HU/4 "\
++"ID/13 IE/5 IL/7 IN/28 IS/4 IT/4 "\
++"JO/3 JP/58 "\
++"KH/2 KR/57 KW/5 KY/3 "\
++"LA/2 LB/5 LI/4 LK/1 LS/2 LT/4 LU/3 LV/4 "\
++"MA/2 MC/1 MD/2 ME/2 MK/2 MN/1 MO/2 MR/2 MT/4 MQ/2 MU/2 MV/3 MW/1 MX/20 MY/16 "\
++"NI/2 NL/4 NO/4 NP/3 NZ/4 "\
++"OM/4 "\
++"PA/17 PE/20 PG/2 PH/5 PL/4 PR/20 PT/4 PY/2 "\
++"RE/2 RO/4 RS/2 RU/986 "\
++"SE/4 SG/4 SG/19 SI/4 SK/4 SN/2 SV/19 "\
++"TH/9 TN/1 TR/7 TT/3 TW/1 "\
++"UA/8 UG/2 US/1 UY/1 "\
++"VA/2 UA/16 VE/3 VG/2 VI/13 VN/4 "\
++"XZ/11 "\
++"YT/2 "\
++"ZM/2 "\
++"E0/32";
++#else
++const char ccode_4356a2[] = "";
++#endif
++
++#ifdef CCODE_4359C0
++const char ccode_4359c0[] = \
++"AD/1 AE/6 AG/2 AI/1 AL/3 AS/12 AT/21 AU/6 AW/2 AZ/8 "\
++"BA/4 BD/1 BE/19 BG/18 BH/4 BM/12 BN/4 BR/2 BS/2 BY/3 "\
++"CN/38 CO/17 CR/17 CY/18 CZ/18 "\
++"DE/30 DK/19 "\
++"E0/32 EC/21 EE/18 EG/13 ES/21 ET/2 "\
++"FI/19 FR/21 "\
++"GB/996 GD/2 GE/1 GF/2 GP/2 GR/18 GT/1 GU/30 "\
++"HK/2 HR/18 HU/18 "\
++"ID/1 IE/21 IL/14 IN/3 IS/17 IT/20 "\
++"JO/3 JP/967 "\
++"KH/2 KR/70 KW/5 KY/3 "\
++"LA/2 LB/5 LI/17 LI/4 LK/1 LS/2 LT/18 LU/18 LV/18 "\
++"MA/2 MC/2 MD/3 ME/5 MK/4 MN/1 MQ/2 MR/2 MT/18 MU/2 MV/3 MW/1 MX/44 MY/3 "\
++"NI/2 NL/19 NO/18 NZ/4 "\
++"OM/4 "\
++"PA/17 PE/20 PH/5 PL/18 PR/38 PT/20 PY/2 "\
++"Q1/947 Q2/993 "\
++"RE/2 RO/18 RS/4 RU/986 "\
++"SE/19 SI/18 SK/18 SM/1 SV/25 "\
++"TH/5 TN/1 TR/18 TT/3 TW/1 "\
++"UA/16 US/988 "\
++"VA/3 VE/3 VG/2 VN/4 "\
++"XZ/11 "\
++"YT/2 "\
++"ZA/6";
++#else
++const char ccode_4359c0[] = "";
++#endif
++
++#ifdef CCODE_4358U
++const char ccode_4358u[] = \
++"BE/4 BR/4 CA/2 CH/4 CN/38 CY/4 DE/7 DK/4 ES/4 "\
++"FI/4 FR/5 GB/6 GR/4 HK/2 HU/4 IE/5 IL/7 IS/4 "\
++"IT/4 JP/72 KE/0 MY/3 NL/4 PT/4 SA/5 SE/4 SG/0 "\
++"SZ/0 TH/5 TR/7 TW/230 US/0 VN/4";
++#else
++const char ccode_4358u[] = "";
++#endif
++
++typedef struct ccode_list_map_t {
++	uint chip;
++	uint chiprev;
++	const char *ccode_list;
++	const char *ccode_ww;
++} ccode_list_map_t;
++
++extern const char ccode_43438[];
++extern const char ccode_43455c0[];
++extern const char ccode_43456c5[];
++extern const char ccode_4356a2[];
++extern const char ccode_4359c0[];
++extern const char ccode_4358u[];
++
++const ccode_list_map_t ccode_list_map[] = {
++	/* ChipID		Chiprev		ccode  */
++#ifdef BCMSDIO
++	{BCM43430_CHIP_ID,	0,	ccode_43438, ""},
++	{BCM43430_CHIP_ID,	1,	ccode_43438, ""},
++	{BCM4345_CHIP_ID,	6,	ccode_43455c0, "XZ/11"},
++	{BCM43454_CHIP_ID,	6,	ccode_43455c0, "XZ/11"},
++	{BCM4345_CHIP_ID,	9,	ccode_43456c5, "XZ/11"},
++	{BCM43454_CHIP_ID,	9,	ccode_43456c5, "XZ/11"},
++	{BCM4354_CHIP_ID,	2,	ccode_4356a2, "XZ/11"},
++	{BCM4356_CHIP_ID,	2,	ccode_4356a2, "XZ/11"},
++	{BCM4371_CHIP_ID,	2,	ccode_4356a2, "XZ/11"},
++	{BCM4359_CHIP_ID,	9,	ccode_4359c0, "XZ/11"},
++#endif
++#ifdef BCMPCIE
++	{BCM4354_CHIP_ID,	2,	ccode_4356a2, "XZ/11"},
++	{BCM4356_CHIP_ID,	2,	ccode_4356a2, "XZ/11"},
++	{BCM4359_CHIP_ID,	9,	ccode_4359c0, "XZ/11"},
++#endif
++#ifdef BCMDBUS
++	{BCM43569_CHIP_ID,	2,	ccode_4358u, "XW/0"},
++#endif
++};
++
++int
++dhd_ccode_map_country_list(dhd_pub_t *dhd, wl_country_t *cspec)
++{
++	int bcmerror = -1, i;
++	uint chip = dhd->conf->chip, chiprev = dhd->conf->chiprev; 
++	const char *ccode_list = NULL, *ccode_ww = NULL;
++	char *pch;
++
++	for (i=0;  i<sizeof(ccode_list_map)/sizeof(ccode_list_map[0]);  i++) {
++		const ccode_list_map_t* row = &ccode_list_map[i];
++		if (row->chip == chip && row->chiprev == chiprev) {
++			ccode_list = row->ccode_list;
++			ccode_ww = row->ccode_ww;
++			break;
++		}
++	}
++
++	if (ccode_list) {
++		pch = strstr(ccode_list, cspec->ccode);
++		if (pch) {
++			cspec->rev = (int)simple_strtol(pch+strlen(cspec->ccode)+1, NULL, 0);
++			bcmerror = 0;
++		}
++	}
++
++	if (bcmerror && ccode_ww && strlen(ccode_ww)>=4) {
++		memcpy(cspec->ccode, ccode_ww, 2);
++		cspec->rev = (int)simple_strtol(ccode_ww+3, NULL, 0);
++	}
++
++	return bcmerror;
++}
++#endif
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_cdc.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_cdc.c
+new file mode 100644
+index 000000000..21286dded
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_cdc.c
+@@ -0,0 +1,962 @@
++/*
++ * DHD Protocol Module for CDC and BDC.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_cdc.c 699163 2017-05-12 05:18:23Z $
++ *
++ * BDC is like CDC, except it includes a header for data packets to convey
++ * packet priority over the bus, and flags (e.g. to indicate checksum status
++ * for dongle offload.)
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++
++#include <bcmutils.h>
++#include <bcmcdc.h>
++#include <bcmendian.h>
++
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_proto.h>
++#include <dhd_bus.h>
++#include <dhd_dbg.h>
++
++
++#ifdef PROP_TXSTATUS
++#include <wlfc_proto.h>
++#include <dhd_wlfc.h>
++#endif
++#ifdef BCMDBUS
++#include <dhd_config.h>
++#endif /* BCMDBUS */
++
++#ifdef DHD_ULP
++#include <dhd_ulp.h>
++#endif /* DHD_ULP */
++
++
++#define RETRIES 2		/* # of retries to retrieve matching ioctl response */
++#define BUS_HEADER_LEN	(24+DHD_SDALIGN)	/* Must be at least SDPCM_RESERVE
++				 * defined in dhd_sdio.c (amount of header tha might be added)
++				 * plus any space that might be needed for alignment padding.
++				 */
++#define ROUND_UP_MARGIN	2048	/* Biggest SDIO block size possible for
++				 * round off at the end of buffer
++				 */
++
++typedef struct dhd_prot {
++	uint16 reqid;
++	uint8 pending;
++	uint32 lastcmd;
++#ifdef BCMDBUS
++	uint ctl_completed;
++#endif /* BCMDBUS */
++	uint8 bus_header[BUS_HEADER_LEN];
++	cdc_ioctl_t msg;
++	unsigned char buf[WLC_IOCTL_MAXLEN + ROUND_UP_MARGIN];
++} dhd_prot_t;
++
++static int
++dhdcdc_msg(dhd_pub_t *dhd)
++{
++#ifdef BCMDBUS
++	int timeout = 0;
++#endif /* BCMDBUS */
++	int err = 0;
++	dhd_prot_t *prot = dhd->prot;
++	int len = ltoh32(prot->msg.len) + sizeof(cdc_ioctl_t);
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	DHD_OS_WAKE_LOCK(dhd);
++
++	/* NOTE : cdc->msg.len holds the desired length of the buffer to be
++	 *        returned. Only up to CDC_MAX_MSG_SIZE of this buffer area
++	 *	  is actually sent to the dongle
++	 */
++	if (len > CDC_MAX_MSG_SIZE)
++		len = CDC_MAX_MSG_SIZE;
++
++	/* Send request */
++#ifdef BCMDBUS
++	DHD_OS_IOCTL_RESP_LOCK(dhd);
++	prot->ctl_completed = FALSE;
++	err = dbus_send_ctl(dhd->bus, (void *)&prot->msg, len);
++	if (err) {
++		DHD_ERROR(("dbus_send_ctl error=%d\n", err));
++		DHD_OS_IOCTL_RESP_UNLOCK(dhd);
++		DHD_OS_WAKE_UNLOCK(dhd);
++		return err;
++	}
++#else
++	err = dhd_bus_txctl(dhd->bus, (uchar*)&prot->msg, len);
++#endif /* BCMDBUS */
++
++#ifdef BCMDBUS
++	timeout = dhd_os_ioctl_resp_wait(dhd, &prot->ctl_completed);
++	if ((!timeout) || (!prot->ctl_completed)) {
++		DHD_ERROR(("Txctl timeout %d ctl_completed %d\n",
++			timeout, prot->ctl_completed));
++		DHD_ERROR(("Txctl wait timed out\n"));
++		err = -1;
++	}
++	DHD_OS_IOCTL_RESP_UNLOCK(dhd);
++#endif /* BCMDBUS */
++#if defined(BCMDBUS) && defined(INTR_EP_ENABLE)
++	/* If the ctl write is successfully completed, wait for an acknowledgement
++	* that indicates that it is now ok to do ctl read from the dongle
++	*/
++	if (err != -1) {
++		DHD_OS_IOCTL_RESP_LOCK(dhd);
++		prot->ctl_completed = FALSE;
++		if (dbus_poll_intr(dhd->dbus)) {
++			DHD_ERROR(("dbus_poll_intr not submitted\n"));
++		} else {
++			/* interrupt polling is sucessfully submitted. Wait for dongle to send
++			* interrupt
++			*/
++			timeout = dhd_os_ioctl_resp_wait(dhd, &prot->ctl_completed);
++			if (!timeout) {
++				DHD_ERROR(("intr poll wait timed out\n"));
++			}
++		}
++		DHD_OS_IOCTL_RESP_UNLOCK(dhd);
++	}
++#endif /* defined(BCMDBUS) && defined(INTR_EP_ENABLE) */
++	DHD_OS_WAKE_UNLOCK(dhd);
++	return err;
++}
++
++static int
++dhdcdc_cmplt(dhd_pub_t *dhd, uint32 id, uint32 len)
++{
++#ifdef BCMDBUS
++	int timeout = 0;
++#endif /* BCMDBUS */
++	int ret;
++	int cdc_len = len + sizeof(cdc_ioctl_t);
++	dhd_prot_t *prot = dhd->prot;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	do {
++#ifdef BCMDBUS
++		DHD_OS_IOCTL_RESP_LOCK(dhd);
++		prot->ctl_completed = FALSE;
++		ret = dbus_recv_ctl(dhd->bus, (uchar*)&prot->msg, cdc_len);
++		if (ret) {
++			DHD_ERROR(("dbus_recv_ctl error=0x%x(%d)\n", ret, ret));
++			DHD_OS_IOCTL_RESP_UNLOCK(dhd);
++			goto done;
++		}
++		timeout = dhd_os_ioctl_resp_wait(dhd, &prot->ctl_completed);
++		if ((!timeout) || (!prot->ctl_completed)) {
++			DHD_ERROR(("Rxctl timeout %d ctl_completed %d\n",
++				timeout, prot->ctl_completed));
++			ret = -1;
++			DHD_OS_IOCTL_RESP_UNLOCK(dhd);
++
++			goto done;
++		}
++		DHD_OS_IOCTL_RESP_UNLOCK(dhd);
++
++		ret = cdc_len;
++#else
++		ret = dhd_bus_rxctl(dhd->bus, (uchar*)&prot->msg, cdc_len);
++#endif /* BCMDBUS */
++		if (ret < 0)
++			break;
++	} while (CDC_IOC_ID(ltoh32(prot->msg.flags)) != id);
++
++#ifdef BCMDBUS
++done:
++#endif /* BCMDBUS */
++	return ret;
++}
++
++static int
++dhdcdc_query_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len, uint8 action)
++{
++	dhd_prot_t *prot = dhd->prot;
++	cdc_ioctl_t *msg = &prot->msg;
++	int ret = 0, retries = 0;
++	uint32 id, flags = 0;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++	DHD_CTL(("%s: cmd %d len %d\n", __FUNCTION__, cmd, len));
++
++
++	/* Respond "bcmerror" and "bcmerrorstr" with local cache */
++	if (cmd == WLC_GET_VAR && buf)
++	{
++		if (!strcmp((char *)buf, "bcmerrorstr"))
++		{
++			strncpy((char *)buf, bcmerrorstr(dhd->dongle_error), BCME_STRLEN);
++			goto done;
++		}
++		else if (!strcmp((char *)buf, "bcmerror"))
++		{
++			*(int *)buf = dhd->dongle_error;
++			goto done;
++		}
++	}
++
++	memset(msg, 0, sizeof(cdc_ioctl_t));
++
++	msg->cmd = htol32(cmd);
++	msg->len = htol32(len);
++	msg->flags = (++prot->reqid << CDCF_IOC_ID_SHIFT);
++	CDC_SET_IF_IDX(msg, ifidx);
++	/* add additional action bits */
++	action &= WL_IOCTL_ACTION_MASK;
++	msg->flags |= (action << CDCF_IOC_ACTION_SHIFT);
++	msg->flags = htol32(msg->flags);
++
++	if (buf)
++		memcpy(prot->buf, buf, len);
++
++	if ((ret = dhdcdc_msg(dhd)) < 0) {
++		if (!dhd->hang_was_sent)
++		DHD_ERROR(("dhdcdc_query_ioctl: dhdcdc_msg failed w/status %d\n", ret));
++		goto done;
++	}
++
++retry:
++	/* wait for interrupt and get first fragment */
++	if ((ret = dhdcdc_cmplt(dhd, prot->reqid, len)) < 0)
++		goto done;
++
++	flags = ltoh32(msg->flags);
++	id = (flags & CDCF_IOC_ID_MASK) >> CDCF_IOC_ID_SHIFT;
++
++	if ((id < prot->reqid) && (++retries < RETRIES))
++		goto retry;
++	if (id != prot->reqid) {
++		DHD_ERROR(("%s: %s: unexpected request id %d (expected %d)\n",
++		           dhd_ifname(dhd, ifidx), __FUNCTION__, id, prot->reqid));
++		ret = -EINVAL;
++		goto done;
++	}
++
++	/* Copy info buffer */
++	if (buf)
++	{
++		if (ret < (int)len)
++			len = ret;
++		memcpy(buf, (void*) prot->buf, len);
++	}
++
++	/* Check the ERROR flag */
++	if (flags & CDCF_IOC_ERROR)
++	{
++		ret = ltoh32(msg->status);
++		/* Cache error from dongle */
++		dhd->dongle_error = ret;
++	}
++
++done:
++	return ret;
++}
++
++
++static int
++dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len, uint8 action)
++{
++	dhd_prot_t *prot = dhd->prot;
++	cdc_ioctl_t *msg = &prot->msg;
++	int ret = 0;
++	uint32 flags, id;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++	DHD_CTL(("%s: cmd %d len %d\n", __FUNCTION__, cmd, len));
++
++	if (dhd->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s : bus is down. we have nothing to do\n", __FUNCTION__));
++		return -EIO;
++	}
++
++	/* don't talk to the dongle if fw is about to be reloaded */
++	if (dhd->hang_was_sent) {
++		DHD_ERROR(("%s: HANG was sent up earlier. Not talking to the chip\n",
++			__FUNCTION__));
++		return -EIO;
++	}
++
++	if (cmd == WLC_SET_PM) {
++		DHD_TRACE_HW4(("%s: SET PM to %d\n", __FUNCTION__, buf ? *(char *)buf : 0));
++	}
++
++	memset(msg, 0, sizeof(cdc_ioctl_t));
++
++	msg->cmd = htol32(cmd);
++	msg->len = htol32(len);
++	msg->flags = (++prot->reqid << CDCF_IOC_ID_SHIFT);
++	CDC_SET_IF_IDX(msg, ifidx);
++	/* add additional action bits */
++	action &= WL_IOCTL_ACTION_MASK;
++	msg->flags |= (action << CDCF_IOC_ACTION_SHIFT) | CDCF_IOC_SET;
++	msg->flags = htol32(msg->flags);
++
++	if (buf)
++		memcpy(prot->buf, buf, len);
++
++#ifdef DHD_ULP
++	if (buf && (!strncmp(buf, "ulp", sizeof("ulp")))) {
++		/* force all the writes after this point to NOT to use cached sbwad value */
++		dhd_ulp_disable_cached_sbwad(dhd);
++	}
++#endif /* DHD_ULP */
++
++	if ((ret = dhdcdc_msg(dhd)) < 0) {
++		DHD_ERROR(("%s: dhdcdc_msg failed w/status %d\n", __FUNCTION__, ret));
++		goto done;
++	}
++
++	if ((ret = dhdcdc_cmplt(dhd, prot->reqid, len)) < 0)
++		goto done;
++
++	flags = ltoh32(msg->flags);
++	id = (flags & CDCF_IOC_ID_MASK) >> CDCF_IOC_ID_SHIFT;
++
++	if (id != prot->reqid) {
++		DHD_ERROR(("%s: %s: unexpected request id %d (expected %d)\n",
++		           dhd_ifname(dhd, ifidx), __FUNCTION__, id, prot->reqid));
++		ret = -EINVAL;
++		goto done;
++	}
++
++#ifdef DHD_ULP
++	/* For ulp prototyping temporary */
++	if ((ret = dhd_ulp_check_ulp_request(dhd, buf)) < 0)
++		goto done;
++#endif /* DHD_ULP */
++
++	/* Check the ERROR flag */
++	if (flags & CDCF_IOC_ERROR)
++	{
++		ret = ltoh32(msg->status);
++		/* Cache error from dongle */
++		dhd->dongle_error = ret;
++	}
++
++done:
++	return ret;
++}
++
++#ifdef BCMDBUS
++int
++dhd_prot_ctl_complete(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot;
++
++	if (dhd == NULL)
++		return BCME_ERROR;
++
++	prot = dhd->prot;
++
++	ASSERT(prot);
++	DHD_OS_IOCTL_RESP_LOCK(dhd);
++	prot->ctl_completed = TRUE;
++	dhd_os_ioctl_resp_wake(dhd);
++	DHD_OS_IOCTL_RESP_UNLOCK(dhd);
++	return 0;
++}
++#endif /* BCMDBUS */
++
++int
++dhd_prot_ioctl(dhd_pub_t *dhd, int ifidx, wl_ioctl_t * ioc, void * buf, int len)
++{
++	dhd_prot_t *prot = dhd->prot;
++	int ret = -1;
++	uint8 action;
++	static int error_cnt = 0;
++
++	if ((dhd->busstate == DHD_BUS_DOWN) || dhd->hang_was_sent) {
++		DHD_ERROR(("%s : bus is down. we have nothing to do - bs: %d, has: %d\n",
++				__FUNCTION__, dhd->busstate, dhd->hang_was_sent));
++		goto done;
++	}
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	ASSERT(len <= WLC_IOCTL_MAXLEN);
++
++	if (len > WLC_IOCTL_MAXLEN)
++		goto done;
++
++	if (prot->pending == TRUE) {
++		DHD_ERROR(("CDC packet is pending!!!! cmd=0x%x (%lu) lastcmd=0x%x (%lu)\n",
++			ioc->cmd, (unsigned long)ioc->cmd, prot->lastcmd,
++			(unsigned long)prot->lastcmd));
++		if ((ioc->cmd == WLC_SET_VAR) || (ioc->cmd == WLC_GET_VAR)) {
++			DHD_TRACE(("iovar cmd=%s\n", buf ? (char*)buf : "\0"));
++		}
++		goto done;
++	}
++
++	prot->pending = TRUE;
++	prot->lastcmd = ioc->cmd;
++	action = ioc->set;
++	if (action & WL_IOCTL_ACTION_SET)
++		ret = dhdcdc_set_ioctl(dhd, ifidx, ioc->cmd, buf, len, action);
++	else {
++		ret = dhdcdc_query_ioctl(dhd, ifidx, ioc->cmd, buf, len, action);
++		if (ret > 0)
++			ioc->used = ret - sizeof(cdc_ioctl_t);
++	}
++	// terence 20130805: send hang event to wpa_supplicant
++	if (ret == -EIO) {
++		error_cnt++;
++		if (error_cnt > 2)
++			ret = -ETIMEDOUT;
++	} else
++		error_cnt = 0;
++
++	/* Too many programs assume ioctl() returns 0 on success */
++	if (ret >= 0)
++		ret = 0;
++	else {
++		cdc_ioctl_t *msg = &prot->msg;
++		ioc->needed = ltoh32(msg->len); /* len == needed when set/query fails from dongle */
++	}
++
++	/* Intercept the wme_dp ioctl here */
++	if ((!ret) && (ioc->cmd == WLC_SET_VAR) && (!strcmp(buf, "wme_dp"))) {
++		int slen, val = 0;
++
++		slen = strlen("wme_dp") + 1;
++		if (len >= (int)(slen + sizeof(int)))
++			bcopy(((char *)buf + slen), &val, sizeof(int));
++		dhd->wme_dp = (uint8) ltoh32(val);
++	}
++
++	prot->pending = FALSE;
++
++done:
++
++	return ret;
++}
++
++int
++dhd_prot_iovar_op(dhd_pub_t *dhdp, const char *name,
++                  void *params, int plen, void *arg, int len, bool set)
++{
++	return BCME_UNSUPPORTED;
++}
++
++void
++dhd_prot_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
++{
++	if (!dhdp || !dhdp->prot) {
++		return;
++	}
++
++	bcm_bprintf(strbuf, "Protocol CDC: reqid %d\n", dhdp->prot->reqid);
++#ifdef PROP_TXSTATUS
++	dhd_wlfc_dump(dhdp, strbuf);
++#endif
++}
++
++/*	The FreeBSD PKTPUSH could change the packet buf pinter
++	so we need to make it changable
++*/
++#define PKTBUF pktbuf
++void
++dhd_prot_hdrpush(dhd_pub_t *dhd, int ifidx, void *PKTBUF)
++{
++#ifdef BDC
++	struct bdc_header *h;
++#endif /* BDC */
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++#ifdef BDC
++	/* Push BDC header used to convey priority for buses that don't */
++
++	PKTPUSH(dhd->osh, PKTBUF, BDC_HEADER_LEN);
++
++	h = (struct bdc_header *)PKTDATA(dhd->osh, PKTBUF);
++
++	h->flags = (BDC_PROTO_VER << BDC_FLAG_VER_SHIFT);
++	if (PKTSUMNEEDED(PKTBUF))
++		h->flags |= BDC_FLAG_SUM_NEEDED;
++
++
++	h->priority = (PKTPRIO(PKTBUF) & BDC_PRIORITY_MASK);
++	h->flags2 = 0;
++	h->dataOffset = 0;
++#endif /* BDC */
++	BDC_SET_IF_IDX(h, ifidx);
++}
++#undef PKTBUF	/* Only defined in the above routine */
++
++uint
++dhd_prot_hdrlen(dhd_pub_t *dhd, void *PKTBUF)
++{
++	uint hdrlen = 0;
++#ifdef BDC
++	/* Length of BDC(+WLFC) headers pushed */
++	hdrlen = BDC_HEADER_LEN + (((struct bdc_header *)PKTBUF)->dataOffset * 4);
++#endif
++	return hdrlen;
++}
++
++int
++dhd_prot_hdrpull(dhd_pub_t *dhd, int *ifidx, void *pktbuf, uchar *reorder_buf_info,
++	uint *reorder_info_len)
++{
++#ifdef BDC
++	struct bdc_header *h;
++#endif
++	uint8 data_offset = 0;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++#ifdef BDC
++	if (reorder_info_len)
++		*reorder_info_len = 0;
++	/* Pop BDC header used to convey priority for buses that don't */
++
++	if (PKTLEN(dhd->osh, pktbuf) < BDC_HEADER_LEN) {
++		DHD_ERROR(("%s: rx data too short (%d < %d)\n", __FUNCTION__,
++		           PKTLEN(dhd->osh, pktbuf), BDC_HEADER_LEN));
++		return BCME_ERROR;
++	}
++
++	h = (struct bdc_header *)PKTDATA(dhd->osh, pktbuf);
++
++	if (!ifidx) {
++		/* for tx packet, skip the analysis */
++		data_offset = h->dataOffset;
++		PKTPULL(dhd->osh, pktbuf, BDC_HEADER_LEN);
++		goto exit;
++	}
++
++	*ifidx = BDC_GET_IF_IDX(h);
++
++	if (((h->flags & BDC_FLAG_VER_MASK) >> BDC_FLAG_VER_SHIFT) != BDC_PROTO_VER) {
++		DHD_ERROR(("%s: non-BDC packet received, flags = 0x%x\n",
++		           dhd_ifname(dhd, *ifidx), h->flags));
++		if (((h->flags & BDC_FLAG_VER_MASK) >> BDC_FLAG_VER_SHIFT) == BDC_PROTO_VER_1)
++			h->dataOffset = 0;
++		else
++		return BCME_ERROR;
++	}
++
++	if (h->flags & BDC_FLAG_SUM_GOOD) {
++		DHD_INFO(("%s: BDC packet received with good rx-csum, flags 0x%x\n",
++		          dhd_ifname(dhd, *ifidx), h->flags));
++		PKTSETSUMGOOD(pktbuf, TRUE);
++	}
++
++	PKTSETPRIO(pktbuf, (h->priority & BDC_PRIORITY_MASK));
++	data_offset = h->dataOffset;
++	PKTPULL(dhd->osh, pktbuf, BDC_HEADER_LEN);
++#endif /* BDC */
++
++
++#ifdef PROP_TXSTATUS
++	if (!DHD_PKTTAG_PKTDIR(PKTTAG(pktbuf))) {
++		/*
++		- parse txstatus only for packets that came from the firmware
++		*/
++		dhd_wlfc_parse_header_info(dhd, pktbuf, (data_offset << 2),
++			reorder_buf_info, reorder_info_len);
++
++#ifdef BCMDBUS
++#ifndef DHD_WLFC_THREAD
++		dhd_wlfc_commit_packets(dhd,
++			(f_commitpkt_t)dhd_bus_txdata, dhd->bus, NULL, FALSE);
++#endif /* DHD_WLFC_THREAD */
++#endif /* BCMDBUS */
++	}
++#endif /* PROP_TXSTATUS */
++
++exit:
++	PKTPULL(dhd->osh, pktbuf, (data_offset << 2));
++	return 0;
++}
++
++
++int
++dhd_prot_attach(dhd_pub_t *dhd)
++{
++	dhd_prot_t *cdc;
++
++	if (!(cdc = (dhd_prot_t *)DHD_OS_PREALLOC(dhd, DHD_PREALLOC_PROT, sizeof(dhd_prot_t)))) {
++		DHD_ERROR(("%s: kmalloc failed\n", __FUNCTION__));
++		goto fail;
++	}
++	memset(cdc, 0, sizeof(dhd_prot_t));
++
++	/* ensure that the msg buf directly follows the cdc msg struct */
++	if ((uintptr)(&cdc->msg + 1) != (uintptr)cdc->buf) {
++		DHD_ERROR(("dhd_prot_t is not correctly defined\n"));
++		goto fail;
++	}
++
++	dhd->prot = cdc;
++#ifdef BDC
++	dhd->hdrlen += BDC_HEADER_LEN;
++#endif
++	dhd->maxctl = WLC_IOCTL_MAXLEN + sizeof(cdc_ioctl_t) + ROUND_UP_MARGIN;
++	return 0;
++
++fail:
++	if (cdc != NULL)
++		DHD_OS_PREFREE(dhd, cdc, sizeof(dhd_prot_t));
++	return BCME_NOMEM;
++}
++
++/* ~NOTE~ What if another thread is waiting on the semaphore?  Holding it? */
++void
++dhd_prot_detach(dhd_pub_t *dhd)
++{
++#ifdef PROP_TXSTATUS
++	dhd_wlfc_deinit(dhd);
++#endif
++	DHD_OS_PREFREE(dhd, dhd->prot, sizeof(dhd_prot_t));
++	dhd->prot = NULL;
++}
++
++void
++dhd_prot_dstats(dhd_pub_t *dhd)
++{
++	/*  copy bus stats */
++
++	dhd->dstats.tx_packets = dhd->tx_packets;
++	dhd->dstats.tx_errors = dhd->tx_errors;
++	dhd->dstats.rx_packets = dhd->rx_packets;
++	dhd->dstats.rx_errors = dhd->rx_errors;
++	dhd->dstats.rx_dropped = dhd->rx_dropped;
++	dhd->dstats.multicast = dhd->rx_multicast;
++	return;
++}
++
++int
++dhd_sync_with_dongle(dhd_pub_t *dhd)
++{
++	int ret = 0;
++	wlc_rev_info_t revinfo;
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++#ifdef DHD_FW_COREDUMP
++	/* Check the memdump capability */
++	dhd_get_memdump_info(dhd);
++#endif /* DHD_FW_COREDUMP */
++
++#ifdef BCMASSERT_LOG
++	dhd_get_assert_info(dhd);
++#endif /* BCMASSERT_LOG */
++
++	/* Get the device rev info */
++	memset(&revinfo, 0, sizeof(revinfo));
++	ret = dhd_wl_ioctl_cmd(dhd, WLC_GET_REVINFO, &revinfo, sizeof(revinfo), FALSE, 0);
++	if (ret < 0)
++		goto done;
++#if defined(BCMDBUS)
++	if (dhd_download_fw_on_driverload) {
++		dhd_conf_reset(dhd);
++		dhd_conf_set_chiprev(dhd, revinfo.chipnum, revinfo.chiprev);
++		dhd_conf_preinit(dhd);
++		dhd_conf_read_config(dhd, dhd->conf_path);
++	}
++#endif /* BCMDBUS */
++
++
++	DHD_SSSR_DUMP_INIT(dhd);
++
++	dhd_process_cid_mac(dhd, TRUE);
++	ret = dhd_preinit_ioctls(dhd);
++	dhd_process_cid_mac(dhd, FALSE);
++
++	/* Always assumes wl for now */
++	dhd->iswl = TRUE;
++
++done:
++	return ret;
++}
++
++int dhd_prot_init(dhd_pub_t *dhd)
++{
++	return BCME_OK;
++}
++
++void
++dhd_prot_stop(dhd_pub_t *dhd)
++{
++/* Nothing to do for CDC */
++}
++
++
++static void
++dhd_get_hostreorder_pkts(void *osh, struct reorder_info *ptr, void **pkt,
++	uint32 *pkt_count, void **pplast, uint8 start, uint8 end)
++{
++	void *plast = NULL, *p;
++	uint32 pkt_cnt = 0;
++
++	if (ptr->pend_pkts == 0) {
++		DHD_REORDER(("%s: no packets in reorder queue \n", __FUNCTION__));
++		*pplast = NULL;
++		*pkt_count = 0;
++		*pkt = NULL;
++		return;
++	}
++	do {
++		p = (void *)(ptr->p[start]);
++		ptr->p[start] = NULL;
++
++		if (p != NULL) {
++			if (plast == NULL)
++				*pkt = p;
++			else
++				PKTSETNEXT(osh, plast, p);
++
++			plast = p;
++			pkt_cnt++;
++		}
++		start++;
++		if (start > ptr->max_idx)
++			start = 0;
++	} while (start != end);
++	*pplast = plast;
++	*pkt_count = pkt_cnt;
++	ptr->pend_pkts -= (uint8)pkt_cnt;
++}
++
++int
++dhd_process_pkt_reorder_info(dhd_pub_t *dhd, uchar *reorder_info_buf, uint reorder_info_len,
++	void **pkt, uint32 *pkt_count)
++{
++	uint8 flow_id, max_idx, cur_idx, exp_idx;
++	struct reorder_info *ptr;
++	uint8 flags;
++	void *cur_pkt, *plast = NULL;
++	uint32 cnt = 0;
++
++	if (pkt == NULL) {
++		if (pkt_count != NULL)
++			*pkt_count = 0;
++		return 0;
++	}
++
++	flow_id = reorder_info_buf[WLHOST_REORDERDATA_FLOWID_OFFSET];
++	flags = reorder_info_buf[WLHOST_REORDERDATA_FLAGS_OFFSET];
++
++	DHD_REORDER(("flow_id %d, flags 0x%02x, idx(%d, %d, %d)\n", flow_id, flags,
++		reorder_info_buf[WLHOST_REORDERDATA_CURIDX_OFFSET],
++		reorder_info_buf[WLHOST_REORDERDATA_EXPIDX_OFFSET],
++		reorder_info_buf[WLHOST_REORDERDATA_MAXIDX_OFFSET]));
++
++	/* validate flags and flow id */
++	if (flags == 0xFF) {
++		DHD_ERROR(("%s: invalid flags...so ignore this packet\n", __FUNCTION__));
++		*pkt_count = 1;
++		return 0;
++	}
++
++	cur_pkt = *pkt;
++	*pkt = NULL;
++
++	ptr = dhd->reorder_bufs[flow_id];
++	if (flags & WLHOST_REORDERDATA_DEL_FLOW) {
++		uint32 buf_size = sizeof(struct reorder_info);
++
++		DHD_REORDER(("%s: Flags indicating to delete a flow id %d\n",
++			__FUNCTION__, flow_id));
++
++		if (ptr == NULL) {
++			DHD_REORDER(("%s: received flags to cleanup, but no flow (%d) yet\n",
++				__FUNCTION__, flow_id));
++			*pkt_count = 1;
++			*pkt = cur_pkt;
++			return 0;
++		}
++
++		dhd_get_hostreorder_pkts(dhd->osh, ptr, pkt, &cnt, &plast,
++			ptr->exp_idx, ptr->exp_idx);
++		/* set it to the last packet */
++		if (plast) {
++			PKTSETNEXT(dhd->osh, plast, cur_pkt);
++			cnt++;
++		}
++		else {
++			if (cnt != 0) {
++				DHD_ERROR(("%s: del flow: something fishy, pending packets %d\n",
++					__FUNCTION__, cnt));
++			}
++			*pkt = cur_pkt;
++			cnt = 1;
++		}
++		buf_size += ((ptr->max_idx + 1) * sizeof(void *));
++		MFREE(dhd->osh, ptr, buf_size);
++		dhd->reorder_bufs[flow_id] = NULL;
++		*pkt_count = cnt;
++		return 0;
++	}
++	/* all the other cases depend on the existance of the reorder struct for that flow id */
++	if (ptr == NULL) {
++		uint32 buf_size_alloc = sizeof(reorder_info_t);
++		max_idx = reorder_info_buf[WLHOST_REORDERDATA_MAXIDX_OFFSET];
++
++		buf_size_alloc += ((max_idx + 1) * sizeof(void*));
++		/* allocate space to hold the buffers, index etc */
++
++		DHD_REORDER(("%s: alloc buffer of size %d size, reorder info id %d, maxidx %d\n",
++			__FUNCTION__, buf_size_alloc, flow_id, max_idx));
++		ptr = (struct reorder_info *)MALLOC(dhd->osh, buf_size_alloc);
++		if (ptr == NULL) {
++			DHD_ERROR(("%s: Malloc failed to alloc buffer\n", __FUNCTION__));
++			*pkt_count = 1;
++			return 0;
++		}
++		bzero(ptr, buf_size_alloc);
++		dhd->reorder_bufs[flow_id] = ptr;
++		ptr->p = (void *)(ptr+1);
++		ptr->max_idx = max_idx;
++	}
++	if (flags & WLHOST_REORDERDATA_NEW_HOLE)  {
++		DHD_REORDER(("%s: new hole, so cleanup pending buffers\n", __FUNCTION__));
++		if (ptr->pend_pkts) {
++			dhd_get_hostreorder_pkts(dhd->osh, ptr, pkt, &cnt, &plast,
++				ptr->exp_idx, ptr->exp_idx);
++			ptr->pend_pkts = 0;
++		}
++		ptr->cur_idx = reorder_info_buf[WLHOST_REORDERDATA_CURIDX_OFFSET];
++		ptr->exp_idx = reorder_info_buf[WLHOST_REORDERDATA_EXPIDX_OFFSET];
++		ptr->max_idx = reorder_info_buf[WLHOST_REORDERDATA_MAXIDX_OFFSET];
++		ptr->p[ptr->cur_idx] = cur_pkt;
++		ptr->pend_pkts++;
++		*pkt_count = cnt;
++	}
++	else if (flags & WLHOST_REORDERDATA_CURIDX_VALID) {
++		cur_idx = reorder_info_buf[WLHOST_REORDERDATA_CURIDX_OFFSET];
++		exp_idx = reorder_info_buf[WLHOST_REORDERDATA_EXPIDX_OFFSET];
++
++
++		if ((exp_idx == ptr->exp_idx) && (cur_idx != ptr->exp_idx)) {
++			/* still in the current hole */
++			/* enqueue the current on the buffer chain */
++			if (ptr->p[cur_idx] != NULL) {
++				DHD_REORDER(("%s: HOLE: ERROR buffer pending..free it\n",
++					__FUNCTION__));
++				PKTFREE(dhd->osh, ptr->p[cur_idx], TRUE);
++				ptr->p[cur_idx] = NULL;
++			}
++			ptr->p[cur_idx] = cur_pkt;
++			ptr->pend_pkts++;
++			ptr->cur_idx = cur_idx;
++			DHD_REORDER(("%s: fill up a hole..pending packets is %d\n",
++				__FUNCTION__, ptr->pend_pkts));
++			*pkt_count = 0;
++			*pkt = NULL;
++		}
++		else if (ptr->exp_idx == cur_idx) {
++			/* got the right one ..flush from cur to exp and update exp */
++			DHD_REORDER(("%s: got the right one now, cur_idx is %d\n",
++				__FUNCTION__, cur_idx));
++			if (ptr->p[cur_idx] != NULL) {
++				DHD_REORDER(("%s: Error buffer pending..free it\n",
++					__FUNCTION__));
++				PKTFREE(dhd->osh, ptr->p[cur_idx], TRUE);
++				ptr->p[cur_idx] = NULL;
++			}
++			ptr->p[cur_idx] = cur_pkt;
++			ptr->pend_pkts++;
++
++			ptr->cur_idx = cur_idx;
++			ptr->exp_idx = exp_idx;
++
++			dhd_get_hostreorder_pkts(dhd->osh, ptr, pkt, &cnt, &plast,
++				cur_idx, exp_idx);
++			*pkt_count = cnt;
++			DHD_REORDER(("%s: freeing up buffers %d, still pending %d\n",
++				__FUNCTION__, cnt, ptr->pend_pkts));
++		}
++		else {
++			uint8 end_idx;
++			bool flush_current = FALSE;
++			/* both cur and exp are moved now .. */
++			DHD_REORDER(("%s:, flow %d, both moved, cur %d(%d), exp %d(%d)\n",
++				__FUNCTION__, flow_id, ptr->cur_idx, cur_idx,
++				ptr->exp_idx, exp_idx));
++			if (flags & WLHOST_REORDERDATA_FLUSH_ALL)
++				end_idx = ptr->exp_idx;
++			else
++				end_idx = exp_idx;
++
++			/* flush pkts first */
++			dhd_get_hostreorder_pkts(dhd->osh, ptr, pkt, &cnt, &plast,
++				ptr->exp_idx, end_idx);
++
++			if (cur_idx == ptr->max_idx) {
++				if (exp_idx == 0)
++					flush_current = TRUE;
++			} else {
++				if (exp_idx == cur_idx + 1)
++					flush_current = TRUE;
++			}
++			if (flush_current) {
++				if (plast)
++					PKTSETNEXT(dhd->osh, plast, cur_pkt);
++				else
++					*pkt = cur_pkt;
++				cnt++;
++			}
++			else {
++				ptr->p[cur_idx] = cur_pkt;
++				ptr->pend_pkts++;
++			}
++			ptr->exp_idx = exp_idx;
++			ptr->cur_idx = cur_idx;
++			*pkt_count = cnt;
++		}
++	}
++	else {
++		uint8 end_idx;
++		/* no real packet but update to exp_seq...that means explicit window move */
++		exp_idx = reorder_info_buf[WLHOST_REORDERDATA_EXPIDX_OFFSET];
++
++		DHD_REORDER(("%s: move the window, cur_idx is %d, exp is %d, new exp is %d\n",
++			__FUNCTION__, ptr->cur_idx, ptr->exp_idx, exp_idx));
++		if (flags & WLHOST_REORDERDATA_FLUSH_ALL)
++			end_idx =  ptr->exp_idx;
++		else
++			end_idx =  exp_idx;
++
++		dhd_get_hostreorder_pkts(dhd->osh, ptr, pkt, &cnt, &plast, ptr->exp_idx, end_idx);
++		if (plast)
++			PKTSETNEXT(dhd->osh, plast, cur_pkt);
++		else
++			*pkt = cur_pkt;
++		cnt++;
++		*pkt_count = cnt;
++		/* set the new expected idx */
++		ptr->exp_idx = exp_idx;
++	}
++	return 0;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_cfg80211.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_cfg80211.c
+new file mode 100644
+index 000000000..d01e76801
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_cfg80211.c
+@@ -0,0 +1,269 @@
++/*
++ * Linux cfg80211 driver - Dongle Host Driver (DHD) related
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_cfg80211.c 699163 2017-05-12 05:18:23Z $
++ */
++
++#include <linux/vmalloc.h>
++#include <net/rtnetlink.h>
++
++#include <bcmutils.h>
++#include <wldev_common.h>
++#include <wl_cfg80211.h>
++#include <dhd_cfg80211.h>
++
++#ifdef PKT_FILTER_SUPPORT
++#include <dngl_stats.h>
++#include <dhd.h>
++#endif
++
++#ifdef PKT_FILTER_SUPPORT
++extern uint dhd_pkt_filter_enable;
++extern uint dhd_master_mode;
++extern void dhd_pktfilter_offload_enable(dhd_pub_t * dhd, char *arg, int enable, int master_mode);
++#endif
++
++static int dhd_dongle_up = FALSE;
++
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhdioctl.h>
++#include <wlioctl.h>
++#include <brcm_nl80211.h>
++#include <dhd_cfg80211.h>
++
++static s32 wl_dongle_up(struct net_device *ndev);
++static s32 wl_dongle_down(struct net_device *ndev);
++
++/**
++ * Function implementations
++ */
++
++s32 dhd_cfg80211_init(struct bcm_cfg80211 *cfg)
++{
++	dhd_dongle_up = FALSE;
++	return 0;
++}
++
++s32 dhd_cfg80211_deinit(struct bcm_cfg80211 *cfg)
++{
++	dhd_dongle_up = FALSE;
++	return 0;
++}
++
++s32 dhd_cfg80211_down(struct bcm_cfg80211 *cfg)
++{
++	struct net_device *ndev;
++	s32 err = 0;
++
++	WL_TRACE(("In\n"));
++	if (!dhd_dongle_up) {
++		WL_ERR(("Dongle is already down\n"));
++		return err;
++	}
++
++	ndev = bcmcfg_to_prmry_ndev(cfg);
++	wl_dongle_down(ndev);
++	dhd_dongle_up = FALSE;
++	return 0;
++}
++
++s32 dhd_cfg80211_set_p2p_info(struct bcm_cfg80211 *cfg, int val)
++{
++	dhd_pub_t *dhd =  (dhd_pub_t *)(cfg->pub);
++	dhd->op_mode |= val;
++	WL_ERR(("Set : op_mode=0x%04x\n", dhd->op_mode));
++#ifdef ARP_OFFLOAD_SUPPORT
++	if (dhd->arp_version == 1) {
++		/* IF P2P is enabled, disable arpoe */
++		dhd_arp_offload_set(dhd, 0);
++		dhd_arp_offload_enable(dhd, false);
++	}
++#endif /* ARP_OFFLOAD_SUPPORT */
++
++	return 0;
++}
++
++s32 dhd_cfg80211_clean_p2p_info(struct bcm_cfg80211 *cfg)
++{
++	dhd_pub_t *dhd =  (dhd_pub_t *)(cfg->pub);
++	dhd->op_mode &= ~(DHD_FLAG_P2P_GC_MODE | DHD_FLAG_P2P_GO_MODE);
++	WL_ERR(("Clean : op_mode=0x%04x\n", dhd->op_mode));
++
++#ifdef ARP_OFFLOAD_SUPPORT
++	if (dhd->arp_version == 1) {
++		/* IF P2P is disabled, enable arpoe back for STA mode. */
++		dhd_arp_offload_set(dhd, dhd_arp_mode);
++		dhd_arp_offload_enable(dhd, true);
++	}
++#endif /* ARP_OFFLOAD_SUPPORT */
++
++	return 0;
++}
++
++struct net_device* wl_cfg80211_allocate_if(struct bcm_cfg80211 *cfg, int ifidx, const char *name,
++	uint8 *mac, uint8 bssidx, const char *dngl_name)
++{
++	return dhd_allocate_if(cfg->pub, ifidx, name, mac, bssidx, FALSE, dngl_name);
++}
++
++int wl_cfg80211_register_if(struct bcm_cfg80211 *cfg,
++	int ifidx, struct net_device* ndev, bool rtnl_lock_reqd)
++{
++	return dhd_register_if(cfg->pub, ifidx, rtnl_lock_reqd);
++}
++
++int wl_cfg80211_remove_if(struct bcm_cfg80211 *cfg,
++	int ifidx, struct net_device* ndev, bool rtnl_lock_reqd)
++{
++	return dhd_remove_if(cfg->pub, ifidx, rtnl_lock_reqd);
++}
++
++struct net_device * dhd_cfg80211_netdev_free(struct net_device *ndev)
++{
++	if (ndev) {
++		if (ndev->ieee80211_ptr) {
++			kfree(ndev->ieee80211_ptr);
++			ndev->ieee80211_ptr = NULL;
++		}
++		free_netdev(ndev);
++		return NULL;
++	}
++
++	return ndev;
++}
++
++void dhd_netdev_free(struct net_device *ndev)
++{
++#ifdef WL_CFG80211
++	ndev = dhd_cfg80211_netdev_free(ndev);
++#endif
++	if (ndev)
++		free_netdev(ndev);
++}
++
++static s32
++wl_dongle_up(struct net_device *ndev)
++{
++	s32 err = 0;
++	u32 local_up = 0;
++
++	err = wldev_ioctl_set(ndev, WLC_UP, &local_up, sizeof(local_up));
++	if (unlikely(err)) {
++		WL_ERR(("WLC_UP error (%d)\n", err));
++	}
++	return err;
++}
++
++static s32
++wl_dongle_down(struct net_device *ndev)
++{
++	s32 err = 0;
++	u32 local_down = 0;
++
++	err = wldev_ioctl_set(ndev, WLC_DOWN, &local_down, sizeof(local_down));
++	if (unlikely(err)) {
++		WL_ERR(("WLC_DOWN error (%d)\n", err));
++	}
++	return err;
++}
++
++
++s32 dhd_config_dongle(struct bcm_cfg80211 *cfg)
++{
++#ifndef DHD_SDALIGN
++#define DHD_SDALIGN	32
++#endif
++	struct net_device *ndev;
++	s32 err = 0;
++
++	WL_TRACE(("In\n"));
++	if (dhd_dongle_up) {
++		WL_ERR(("Dongle is already up\n"));
++		return err;
++	}
++
++	ndev = bcmcfg_to_prmry_ndev(cfg);
++
++	err = wl_dongle_up(ndev);
++	if (unlikely(err)) {
++		WL_ERR(("wl_dongle_up failed\n"));
++		goto default_conf_out;
++	}
++	dhd_dongle_up = true;
++
++default_conf_out:
++
++	return err;
++
++}
++
++int dhd_cfgvendor_priv_string_handler(struct bcm_cfg80211 *cfg, struct wireless_dev *wdev,
++	const struct bcm_nlmsg_hdr *nlioc, void *buf)
++{
++	struct net_device *ndev = NULL;
++	dhd_pub_t *dhd;
++	dhd_ioctl_t ioc = { 0, NULL, 0, 0, 0, 0, 0};
++	int ret = 0;
++	int8 index;
++
++	WL_TRACE(("entry: cmd = %d\n", nlioc->cmd));
++
++	dhd = cfg->pub;
++	DHD_OS_WAKE_LOCK(dhd);
++
++	/* send to dongle only if we are not waiting for reload already */
++	if (dhd->hang_was_sent) {
++		WL_ERR(("HANG was sent up earlier\n"));
++		DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_ENABLE(dhd, DHD_EVENT_TIMEOUT_MS);
++		DHD_OS_WAKE_UNLOCK(dhd);
++		return OSL_ERROR(BCME_DONGLE_DOWN);
++	}
++
++	ndev = wdev_to_wlc_ndev(wdev, cfg);
++	index = dhd_net2idx(dhd->info, ndev);
++	if (index == DHD_BAD_IF) {
++		WL_ERR(("Bad ifidx from wdev:%p\n", wdev));
++		ret = BCME_ERROR;
++		goto done;
++	}
++
++	ioc.cmd = nlioc->cmd;
++	ioc.len = nlioc->len;
++	ioc.set = nlioc->set;
++	ioc.driver = nlioc->magic;
++	ioc.buf = buf;
++	ret = dhd_ioctl_process(dhd, index, &ioc, buf);
++	if (ret) {
++		WL_TRACE(("dhd_ioctl_process return err %d\n", ret));
++		ret = OSL_ERROR(ret);
++		goto done;
++	}
++
++done:
++	DHD_OS_WAKE_UNLOCK(dhd);
++	return ret;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_cfg80211.h b/module_drivers/drivers/net/wireless/bcmdhd/dhd_cfg80211.h
+new file mode 100644
+index 000000000..20923ce5f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_cfg80211.h
+@@ -0,0 +1,54 @@
++/*
++ * Linux cfg80211 driver - Dongle Host Driver (DHD) related
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_cfg80211.h 612483 2016-01-14 03:44:27Z $
++ */
++
++
++#ifndef __DHD_CFG80211__
++#define __DHD_CFG80211__
++
++#include <wl_cfg80211.h>
++#include <wl_cfgp2p.h>
++#include <brcm_nl80211.h>
++
++#ifndef WL_ERR
++#define WL_ERR CFG80211_ERR
++#endif
++#ifndef WL_TRACE
++#define WL_TRACE CFG80211_TRACE
++#endif
++
++s32 dhd_cfg80211_init(struct bcm_cfg80211 *cfg);
++s32 dhd_cfg80211_deinit(struct bcm_cfg80211 *cfg);
++s32 dhd_cfg80211_down(struct bcm_cfg80211 *cfg);
++s32 dhd_cfg80211_set_p2p_info(struct bcm_cfg80211 *cfg, int val);
++s32 dhd_cfg80211_clean_p2p_info(struct bcm_cfg80211 *cfg);
++s32 dhd_config_dongle(struct bcm_cfg80211 *cfg);
++int dhd_cfgvendor_priv_string_handler(struct bcm_cfg80211 *cfg,
++	struct wireless_dev *wdev, const struct bcm_nlmsg_hdr *nlioc, void  *data);
++
++#endif /* __DHD_CFG80211__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_common.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_common.c
+new file mode 100644
+index 000000000..c2ddbf1ab
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_common.c
+@@ -0,0 +1,6076 @@
++/*
++ * Broadcom Dongle Host Driver (DHD), common DHD core.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_common.c 710862 2017-07-14 07:43:59Z $
++ */
++#include <typedefs.h>
++#include <osl.h>
++
++#include <epivers.h>
++#include <bcmutils.h>
++
++#include <bcmendian.h>
++#include <dngl_stats.h>
++#include <wlioctl.h>
++#include <dhd.h>
++#include <dhd_ip.h>
++#include <bcmevent.h>
++
++#ifdef PCIE_FULL_DONGLE
++#include <bcmmsgbuf.h>
++#endif /* PCIE_FULL_DONGLE */
++
++#ifdef SHOW_LOGTRACE
++#include <event_log.h>
++#endif /* SHOW_LOGTRACE */
++
++#ifdef BCMPCIE
++#include <dhd_flowring.h>
++#endif
++
++#include <dhd_bus.h>
++#include <dhd_proto.h>
++#include <bcmsdbus.h>
++#include <dhd_dbg.h>
++#include <dhd_debug.h>
++#include <dhd_mschdbg.h>
++#include <msgtrace.h>
++#include <dhd_config.h>
++#include <wl_android.h>
++
++#ifdef WL_CFG80211
++#include <wl_cfg80211.h>
++#endif
++#ifdef PNO_SUPPORT
++#include <dhd_pno.h>
++#elif defined(WL_WIRELESS_EXT)
++#include <wl_iw.h>
++#endif
++#ifdef RTT_SUPPORT
++#include <dhd_rtt.h>
++#endif
++
++#ifdef DNGL_EVENT_SUPPORT
++#include <dnglevent.h>
++#endif
++
++#define htod32(i) (i)
++#define htod16(i) (i)
++#define dtoh32(i) (i)
++#define dtoh16(i) (i)
++#define htodchanspec(i) (i)
++#define dtohchanspec(i) (i)
++
++#ifdef PROP_TXSTATUS
++#include <wlfc_proto.h>
++#include <dhd_wlfc.h>
++#endif
++
++#ifdef DHD_WMF
++#include <dhd_linux.h>
++#include <dhd_wmf_linux.h>
++#endif /* DHD_WMF */
++
++#ifdef DHD_L2_FILTER
++#include <dhd_l2_filter.h>
++#endif /* DHD_L2_FILTER */
++
++#ifdef DHD_PSTA
++#include <dhd_psta.h>
++#endif /* DHD_PSTA */
++#ifdef DHD_TIMESYNC
++#include <dhd_timesync.h>
++#endif /* DHD_TIMESYNC */
++
++#ifdef DHD_WET
++#include <dhd_wet.h>
++#endif /* DHD_WET */
++
++#if defined(BCMEMBEDIMAGE) && defined(DHD_EFI)
++#include <nvram_4364.h>
++#endif
++
++#ifdef WLMEDIA_HTSF
++extern void htsf_update(struct dhd_info *dhd, void *data);
++#endif
++
++extern int is_wlc_event_frame(void *pktdata, uint pktlen, uint16 exp_usr_subtype,
++	bcm_event_msg_u_t *out_event);
++
++/* By default all logs are enabled */
++int dhd_msg_level = DHD_ERROR_VAL | DHD_MSGTRACE_VAL | DHD_FWLOG_VAL;
++
++
++#if defined(WL_WLC_SHIM)
++#include <wl_shim.h>
++#else
++#endif /* WL_WLC_SHIM */
++
++#ifdef DHD_ULP
++#include <dhd_ulp.h>
++#endif /* DHD_ULP */
++
++#ifdef DHD_DEBUG
++#include <sdiovar.h>
++#endif /* DHD_DEBUG */
++
++#ifdef SOFTAP
++char fw_path2[MOD_PARAM_PATHLEN];
++extern bool softap_enabled;
++#endif
++
++#ifdef REPORT_FATAL_TIMEOUTS
++/* Default timeout value in ms */
++#define SCAN_TIMEOUT_DEFAULT    1
++#define JOIN_TIMEOUT_DEFAULT    7500
++#ifdef DHD_EFI
++#define BUS_TIMEOUT_DEFAULT     8000000  /* 800ms, in units of 100ns */
++#define CMD_TIMEOUT_DEFAULT     15000000 /* 1.5sec, in units of 100ns */
++#else
++#define BUS_TIMEOUT_DEFAULT     800
++#define CMD_TIMEOUT_DEFAULT     1200
++#endif /* DHD_EFI */
++#endif /* REPORT_FATAL_TIMEOUTS */
++
++#ifdef SHOW_LOGTRACE
++#define BYTES_AHEAD_NUM		11	/* address in map file is before these many bytes */
++#define READ_NUM_BYTES		1000 /* read map file each time this No. of bytes */
++#define GO_BACK_FILE_POS_NUM_BYTES	100 /* set file pos back to cur pos */
++static char *ramstart_str = "text_start"; /* string in mapfile has addr ramstart */
++static char *rodata_start_str = "rodata_start"; /* string in mapfile has addr rodata start */
++static char *rodata_end_str = "rodata_end"; /* string in mapfile has addr rodata end */
++#define RAMSTART_BIT	0x01
++#define RDSTART_BIT		0x02
++#define RDEND_BIT		0x04
++#define ALL_MAP_VAL		(RAMSTART_BIT | RDSTART_BIT | RDEND_BIT)
++#endif /* SHOW_LOGTRACE */
++
++/* Last connection success/failure status */
++uint32 dhd_conn_event;
++uint32 dhd_conn_status;
++uint32 dhd_conn_reason;
++
++extern int dhd_iscan_request(void * dhdp, uint16 action);
++extern void dhd_ind_scan_confirm(void *h, bool status);
++extern int dhd_iscan_in_progress(void *h);
++void dhd_iscan_lock(void);
++void dhd_iscan_unlock(void);
++extern int dhd_change_mtu(dhd_pub_t *dhd, int new_mtu, int ifidx);
++#if !defined(AP) && defined(WLP2P)
++extern int dhd_get_concurrent_capabilites(dhd_pub_t *dhd);
++#endif
++
++extern int dhd_socram_dump(struct dhd_bus *bus);
++
++#ifdef DNGL_EVENT_SUPPORT
++static void dngl_host_event_process(dhd_pub_t *dhdp, bcm_dngl_event_t *event,
++	bcm_dngl_event_msg_t *dngl_event, size_t pktlen);
++static int dngl_host_event(dhd_pub_t *dhdp, void *pktdata, bcm_dngl_event_msg_t *dngl_event,
++	size_t pktlen);
++#endif /* DNGL_EVENT_SUPPORT */
++
++#define MAX_CHUNK_LEN 1408 /* 8 * 8 * 22 */
++
++bool ap_cfg_running = FALSE;
++bool ap_fw_loaded = FALSE;
++
++/* Version string to report */
++#ifdef DHD_DEBUG
++#ifndef SRCBASE
++#define SRCBASE        "drivers/net/wireless/bcmdhd"
++#endif
++#define DHD_COMPILED "\nCompiled in " SRCBASE
++#endif /* DHD_DEBUG */
++
++#define CHIPID_MISMATCH	8
++
++#if defined(DHD_DEBUG)
++const char dhd_version[] = "Dongle Host Driver, version " EPI_VERSION_STR;
++#else
++const char dhd_version[] = "\nDongle Host Driver, version " EPI_VERSION_STR;
++#endif 
++char fw_version[FW_VER_STR_LEN] = "\0";
++char clm_version[CLM_VER_STR_LEN] = "\0";
++
++char bus_api_revision[BUS_API_REV_STR_LEN] = "\0";
++
++void dhd_set_timer(void *bus, uint wdtick);
++
++#if defined(TRAFFIC_MGMT_DWM)
++static int traffic_mgmt_add_dwm_filter(dhd_pub_t *dhd,
++	trf_mgmt_filter_list_t * trf_mgmt_filter_list, int len);
++#endif
++
++/* IOVar table */
++enum {
++	IOV_VERSION = 1,
++	IOV_WLMSGLEVEL,
++	IOV_MSGLEVEL,
++	IOV_BCMERRORSTR,
++	IOV_BCMERROR,
++	IOV_WDTICK,
++	IOV_DUMP,
++	IOV_CLEARCOUNTS,
++	IOV_LOGDUMP,
++	IOV_LOGCAL,
++	IOV_LOGSTAMP,
++	IOV_GPIOOB,
++	IOV_IOCTLTIMEOUT,
++	IOV_CONS,
++	IOV_DCONSOLE_POLL,
++#if defined(DHD_DEBUG)
++	IOV_DHD_JOIN_TIMEOUT_DBG,
++	IOV_SCAN_TIMEOUT,
++	IOV_MEM_DEBUG,
++#endif /* defined(DHD_DEBUG) */
++#ifdef PROP_TXSTATUS
++	IOV_PROPTXSTATUS_ENABLE,
++	IOV_PROPTXSTATUS_MODE,
++	IOV_PROPTXSTATUS_OPT,
++	IOV_PROPTXSTATUS_MODULE_IGNORE,
++	IOV_PROPTXSTATUS_CREDIT_IGNORE,
++	IOV_PROPTXSTATUS_TXSTATUS_IGNORE,
++	IOV_PROPTXSTATUS_RXPKT_CHK,
++#endif /* PROP_TXSTATUS */
++	IOV_BUS_TYPE,
++#ifdef WLMEDIA_HTSF
++	IOV_WLPKTDLYSTAT_SZ,
++#endif
++	IOV_CHANGEMTU,
++	IOV_HOSTREORDER_FLOWS,
++#ifdef DHDTCPACK_SUPPRESS
++	IOV_TCPACK_SUPPRESS,
++#endif /* DHDTCPACK_SUPPRESS */
++#ifdef DHD_WMF
++	IOV_WMF_BSS_ENAB,
++	IOV_WMF_UCAST_IGMP,
++	IOV_WMF_MCAST_DATA_SENDUP,
++#ifdef WL_IGMP_UCQUERY
++	IOV_WMF_UCAST_IGMP_QUERY,
++#endif /* WL_IGMP_UCQUERY */
++#ifdef DHD_UCAST_UPNP
++	IOV_WMF_UCAST_UPNP,
++#endif /* DHD_UCAST_UPNP */
++	IOV_WMF_PSTA_DISABLE,
++#endif /* DHD_WMF */
++#if defined(TRAFFIC_MGMT_DWM)
++	IOV_TRAFFIC_MGMT_DWM,
++#endif 
++	IOV_AP_ISOLATE,
++#ifdef DHD_L2_FILTER
++	IOV_DHCP_UNICAST,
++	IOV_BLOCK_PING,
++	IOV_PROXY_ARP,
++	IOV_GRAT_ARP,
++#endif /* DHD_L2_FILTER */
++	IOV_DHD_IE,
++#ifdef DHD_PSTA
++	IOV_PSTA,
++#endif /* DHD_PSTA */
++#ifdef DHD_WET
++	IOV_WET,
++	IOV_WET_HOST_IPV4,
++	IOV_WET_HOST_MAC,
++#endif /* DHD_WET */
++	IOV_CFG80211_OPMODE,
++	IOV_ASSERT_TYPE,
++	IOV_LMTEST,
++#ifdef DHD_MCAST_REGEN
++	IOV_MCAST_REGEN_BSS_ENABLE,
++#endif
++#ifdef SHOW_LOGTRACE
++	IOV_DUMP_TRACE_LOG,
++#endif /* SHOW_LOGTRACE */
++#ifdef REPORT_FATAL_TIMEOUTS
++	IOV_SCAN_TO,
++	IOV_JOIN_TO,
++	IOV_CMD_TO,
++	IOV_OQS_TO,
++#endif /* REPORT_FATAL_TIMEOUTS */
++	IOV_DONGLE_TRAP_TYPE,
++	IOV_DONGLE_TRAP_INFO,
++	IOV_BPADDR,
++	IOV_LAST,
++#if defined(DHD_EFI) && defined(DHD_LOG_DUMP)
++	IOV_LOG_CAPTURE_ENABLE,
++	IOV_LOG_DUMP
++#endif /* DHD_EFI && DHD_LOG_DUMP */
++};
++
++const bcm_iovar_t dhd_iovars[] = {
++	{"version",	IOV_VERSION,	0,	0,	IOVT_BUFFER,	sizeof(dhd_version) },
++	{"wlmsglevel",	IOV_WLMSGLEVEL,	0,	0,	IOVT_UINT32,	0 },
++#ifdef DHD_DEBUG
++	{"msglevel",	IOV_MSGLEVEL,	0,	0,	IOVT_UINT32,	0 },
++	{"mem_debug",   IOV_MEM_DEBUG,  0,      0,      IOVT_BUFFER,    0 },
++#endif /* DHD_DEBUG */
++	{"bcmerrorstr", IOV_BCMERRORSTR, 0, 0,	IOVT_BUFFER,	BCME_STRLEN },
++	{"bcmerror",	IOV_BCMERROR,	0,	0,	IOVT_INT8,	0 },
++	{"wdtick",	IOV_WDTICK, 0,	0,	IOVT_UINT32,	0 },
++	{"dump",	IOV_DUMP,	0,	0,	IOVT_BUFFER,	DHD_IOCTL_MAXLEN },
++	{"cons",	IOV_CONS,	0,	0,	IOVT_BUFFER,	0 },
++	{"dconpoll",	IOV_DCONSOLE_POLL, 0,	0,	IOVT_UINT32,	0 },
++	{"clearcounts", IOV_CLEARCOUNTS, 0, 0,	IOVT_VOID,	0 },
++	{"gpioob",	IOV_GPIOOB,	0,	0,	IOVT_UINT32,	0 },
++	{"ioctl_timeout",	IOV_IOCTLTIMEOUT,	0,	0,	IOVT_UINT32,	0 },
++#ifdef PROP_TXSTATUS
++	{"proptx",	IOV_PROPTXSTATUS_ENABLE,	0,	0,	IOVT_BOOL,	0 },
++	/*
++	set the proptxtstatus operation mode:
++	0 - Do not do any proptxtstatus flow control
++	1 - Use implied credit from a packet status
++	2 - Use explicit credit
++	*/
++	{"ptxmode",	IOV_PROPTXSTATUS_MODE,	0,	0, IOVT_UINT32,	0 },
++	{"proptx_opt", IOV_PROPTXSTATUS_OPT,	0,	0, IOVT_UINT32,	0 },
++	{"pmodule_ignore", IOV_PROPTXSTATUS_MODULE_IGNORE, 0, 0, IOVT_BOOL, 0 },
++	{"pcredit_ignore", IOV_PROPTXSTATUS_CREDIT_IGNORE, 0, 0, IOVT_BOOL, 0 },
++	{"ptxstatus_ignore", IOV_PROPTXSTATUS_TXSTATUS_IGNORE, 0, 0, IOVT_BOOL, 0 },
++	{"rxpkt_chk", IOV_PROPTXSTATUS_RXPKT_CHK, 0, 0, IOVT_BOOL, 0 },
++#endif /* PROP_TXSTATUS */
++	{"bustype", IOV_BUS_TYPE, 0, 0, IOVT_UINT32, 0},
++#ifdef WLMEDIA_HTSF
++	{"pktdlystatsz", IOV_WLPKTDLYSTAT_SZ, 0, 0, IOVT_UINT8, 0 },
++#endif
++	{"changemtu", IOV_CHANGEMTU, 0, 0, IOVT_UINT32, 0 },
++	{"host_reorder_flows", IOV_HOSTREORDER_FLOWS, 0, 0, IOVT_BUFFER,
++	(WLHOST_REORDERDATA_MAXFLOWS + 1) },
++#ifdef DHDTCPACK_SUPPRESS
++	{"tcpack_suppress",	IOV_TCPACK_SUPPRESS,	0,	0, IOVT_UINT8,	0 },
++#endif /* DHDTCPACK_SUPPRESS */
++#ifdef DHD_WMF
++	{"wmf_bss_enable", IOV_WMF_BSS_ENAB,	0,	0, IOVT_BOOL,	0 },
++	{"wmf_ucast_igmp", IOV_WMF_UCAST_IGMP,	0,	0, IOVT_BOOL,	0 },
++	{"wmf_mcast_data_sendup", IOV_WMF_MCAST_DATA_SENDUP,	0,	0, IOVT_BOOL,	0 },
++#ifdef WL_IGMP_UCQUERY
++	{"wmf_ucast_igmp_query", IOV_WMF_UCAST_IGMP_QUERY, (0), 0, IOVT_BOOL, 0 },
++#endif /* WL_IGMP_UCQUERY */
++#ifdef DHD_UCAST_UPNP
++	{"wmf_ucast_upnp", IOV_WMF_UCAST_UPNP, (0), 0, IOVT_BOOL, 0 },
++#endif /* DHD_UCAST_UPNP */
++	{"wmf_psta_disable", IOV_WMF_PSTA_DISABLE, (0), 0, IOVT_BOOL, 0 },
++#endif /* DHD_WMF */
++#if defined(TRAFFIC_MGMT_DWM)
++	{"trf_mgmt_filters_add", IOV_TRAFFIC_MGMT_DWM, (0), 0, IOVT_BUFFER, 0},
++#endif 
++#ifdef DHD_L2_FILTER
++	{"dhcp_unicast", IOV_DHCP_UNICAST, (0), 0, IOVT_BOOL, 0 },
++#endif /* DHD_L2_FILTER */
++	{"ap_isolate", IOV_AP_ISOLATE, (0), 0, IOVT_BOOL, 0},
++#ifdef DHD_L2_FILTER
++	{"block_ping", IOV_BLOCK_PING, (0), 0, IOVT_BOOL, 0},
++	{"proxy_arp", IOV_PROXY_ARP, (0), 0, IOVT_BOOL, 0},
++	{"grat_arp", IOV_GRAT_ARP, (0), 0, IOVT_BOOL, 0},
++#endif /* DHD_L2_FILTER */
++	{"dhd_ie", IOV_DHD_IE, (0), 0, IOVT_BUFFER, 0},
++#ifdef DHD_PSTA
++	/* PSTA/PSR Mode configuration. 0: DIABLED 1: PSTA 2: PSR */
++	{"psta", IOV_PSTA, 0, 0, IOVT_UINT32, 0},
++#endif /* DHD PSTA */
++#ifdef DHD_WET
++	/* WET Mode configuration. 0: DIABLED 1: WET */
++	{"wet", IOV_WET, 0, 0, IOVT_UINT32, 0},
++	{"wet_host_ipv4", IOV_WET_HOST_IPV4, 0, 0, IOVT_UINT32, 0},
++	{"wet_host_mac", IOV_WET_HOST_MAC, 0, 0, IOVT_BUFFER, 0},
++#endif /* DHD WET */
++	{"op_mode",	IOV_CFG80211_OPMODE,	0,	0, IOVT_UINT32,	0 },
++	{"assert_type", IOV_ASSERT_TYPE, (0), 0, IOVT_UINT32, 0},
++	{"lmtest", IOV_LMTEST,	0,	0, IOVT_UINT32,	0 },
++#ifdef DHD_MCAST_REGEN
++	{"mcast_regen_bss_enable", IOV_MCAST_REGEN_BSS_ENABLE, 0, 0, IOVT_BOOL, 0},
++#endif
++#ifdef SHOW_LOGTRACE
++	{"dump_trace_buf", IOV_DUMP_TRACE_LOG,	0, 0, IOVT_BUFFER,	sizeof(trace_buf_info_t) },
++#endif /* SHOW_LOGTRACE */
++#ifdef REPORT_FATAL_TIMEOUTS
++	{"scan_timeout", IOV_SCAN_TO, 0, 0, IOVT_UINT32, 0 },
++	{"join_timeout", IOV_JOIN_TO, 0, 0, IOVT_UINT32, 0 },
++	{"cmd_timeout", IOV_CMD_TO, 0, 0, IOVT_UINT32, 0 },
++	{"oqs_timeout", IOV_OQS_TO, 0, 0, IOVT_UINT32, 0 },
++#endif /* REPORT_FATAL_TIMEOUTS */
++	{"trap_type", IOV_DONGLE_TRAP_TYPE, 0, 0, IOVT_UINT32, 0 },
++	{"trap_info", IOV_DONGLE_TRAP_INFO, 0, 0, IOVT_BUFFER, sizeof(trap_t) },
++#ifdef DHD_DEBUG
++	{"bpaddr", IOV_BPADDR,	0, 0, IOVT_BUFFER,	sizeof(sdreg_t) },
++#endif /* DHD_DEBUG */
++#if defined(DHD_EFI) && defined(DHD_LOG_DUMP)
++	{"log_capture_enable", IOV_LOG_CAPTURE_ENABLE, 0, 0, IOVT_UINT8, 0},
++	{"log_dump", IOV_LOG_DUMP,	0, 0, IOVT_UINT8, 0},
++#endif /* DHD_EFI && DHD_LOG_DUMP */
++	{NULL, 0, 0, 0, 0, 0 }
++};
++
++#define DHD_IOVAR_BUF_SIZE	128
++
++bool
++dhd_query_bus_erros(dhd_pub_t *dhdp)
++{
++	bool ret = FALSE;
++
++	if (dhdp->dongle_reset) {
++		DHD_ERROR(("%s: Dongle Reset occurred, cannot proceed\n",
++			__FUNCTION__));
++		ret = TRUE;
++	}
++
++	if (dhdp->dongle_trap_occured) {
++		DHD_ERROR(("%s: FW TRAP has occurred, cannot proceed\n",
++			__FUNCTION__));
++		ret = TRUE;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++		dhdp->hang_reason = HANG_REASON_DONGLE_TRAP;
++		dhd_os_send_hang_message(dhdp);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27) */
++	}
++
++	if (dhdp->iovar_timeout_occured) {
++		DHD_ERROR(("%s: Resumed on timeout for previous IOVAR, cannot proceed\n",
++			__FUNCTION__));
++		ret = TRUE;
++	}
++
++#ifdef PCIE_FULL_DONGLE
++	if (dhdp->d3ack_timeout_occured) {
++		DHD_ERROR(("%s: Resumed on timeout for previous D3ACK, cannot proceed\n",
++			__FUNCTION__));
++		ret = TRUE;
++	}
++#endif /* PCIE_FULL_DONGLE */
++
++	return ret;
++}
++
++#ifdef DHD_SSSR_DUMP
++int
++dhd_sssr_mempool_init(dhd_pub_t *dhd)
++{
++	dhd->sssr_mempool = (uint8 *) MALLOCZ(dhd->osh, DHD_SSSR_MEMPOOL_SIZE);
++	if (dhd->sssr_mempool == NULL) {
++		DHD_ERROR(("%s: MALLOC of sssr_mempool failed\n",
++			__FUNCTION__));
++		return BCME_ERROR;
++	}
++	return BCME_OK;
++}
++
++void
++dhd_sssr_mempool_deinit(dhd_pub_t *dhd)
++{
++	if (dhd->sssr_mempool) {
++		MFREE(dhd->osh, dhd->sssr_mempool, DHD_SSSR_MEMPOOL_SIZE);
++		dhd->sssr_mempool = NULL;
++	}
++}
++
++int
++dhd_get_sssr_reg_info(dhd_pub_t *dhd)
++{
++	int ret = BCME_ERROR;
++
++	DHD_ERROR(("%s: get sssr_reg_info\n", __FUNCTION__));
++	/* get sssr_reg_info from firmware */
++	memset((void *)&dhd->sssr_reg_info, 0, sizeof(dhd->sssr_reg_info));
++	if (bcm_mkiovar("sssr_reg_info", 0, 0, (char *)&dhd->sssr_reg_info,
++		sizeof(dhd->sssr_reg_info))) {
++		if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_GET_VAR, &dhd->sssr_reg_info,
++			sizeof(dhd->sssr_reg_info), FALSE, 0)) < 0) {
++			DHD_ERROR(("%s: dhd_wl_ioctl_cmd failed (error=%d)\n", __FUNCTION__, ret));
++		}
++	} else {
++			DHD_ERROR(("%s: bcm_mkiovar failed\n", __FUNCTION__));
++	}
++
++	return ret;
++}
++
++uint32
++dhd_get_sssr_bufsize(dhd_pub_t *dhd)
++{
++	int i;
++	uint32 sssr_bufsize = 0;
++	/* Init all pointers to NULL */
++	for (i = 0; i < MAX_NUM_D11CORES; i++) {
++		sssr_bufsize += dhd->sssr_reg_info.mac_regs[i].sr_size;
++	}
++	sssr_bufsize += dhd->sssr_reg_info.vasip_regs.vasip_sr_size;
++
++	/* Double the size as different dumps will be saved before and after SR */
++	sssr_bufsize = 2 * sssr_bufsize;
++
++	return sssr_bufsize;
++}
++
++int
++dhd_sssr_dump_init(dhd_pub_t *dhd)
++{
++	int i;
++	uint32 sssr_bufsize;
++	uint32 mempool_used = 0;
++
++	dhd->sssr_inited = FALSE;
++
++	/* check if sssr mempool is allocated */
++	if (dhd->sssr_mempool == NULL) {
++		DHD_ERROR(("%s: sssr_mempool is not allocated\n",
++			__FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	/* Get SSSR reg info */
++	if (dhd_get_sssr_reg_info(dhd) != BCME_OK) {
++		DHD_ERROR(("%s: dhd_get_sssr_reg_info failed\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	/* Validate structure version */
++	if (dhd->sssr_reg_info.version != SSSR_REG_INFO_VER) {
++		DHD_ERROR(("%s: dhd->sssr_reg_info.version (%d : %d) mismatch\n",
++			__FUNCTION__, (int)dhd->sssr_reg_info.version, SSSR_REG_INFO_VER));
++		return BCME_ERROR;
++	}
++
++	/* Validate structure length */
++	if (dhd->sssr_reg_info.length != sizeof(dhd->sssr_reg_info)) {
++		DHD_ERROR(("%s: dhd->sssr_reg_info.length (%d : %d) mismatch\n",
++			__FUNCTION__, (int)dhd->sssr_reg_info.length,
++			(int)sizeof(dhd->sssr_reg_info)));
++		return BCME_ERROR;
++	}
++
++	/* validate fifo size */
++	sssr_bufsize = dhd_get_sssr_bufsize(dhd);
++	if (sssr_bufsize > DHD_SSSR_MEMPOOL_SIZE) {
++		DHD_ERROR(("%s: sssr_bufsize(%d) is greater than sssr_mempool(%d)\n",
++			__FUNCTION__, (int)sssr_bufsize, DHD_SSSR_MEMPOOL_SIZE));
++		return BCME_ERROR;
++	}
++
++	/* init all pointers to NULL */
++	for (i = 0; i < MAX_NUM_D11CORES; i++) {
++		dhd->sssr_d11_before[i] = NULL;
++		dhd->sssr_d11_after[i] = NULL;
++	}
++	dhd->sssr_vasip_buf_before = NULL;
++	dhd->sssr_vasip_buf_after = NULL;
++
++	/* Allocate memory */
++	for (i = 0; i < MAX_NUM_D11CORES; i++) {
++		if (dhd->sssr_reg_info.mac_regs[i].sr_size) {
++			dhd->sssr_d11_before[i] = (uint32 *)(dhd->sssr_mempool + mempool_used);
++			mempool_used += dhd->sssr_reg_info.mac_regs[i].sr_size;
++
++			dhd->sssr_d11_after[i] = (uint32 *)(dhd->sssr_mempool + mempool_used);
++			mempool_used += dhd->sssr_reg_info.mac_regs[i].sr_size;
++		}
++	}
++
++	if (dhd->sssr_reg_info.vasip_regs.vasip_sr_size) {
++		dhd->sssr_vasip_buf_before = (uint32 *)(dhd->sssr_mempool + mempool_used);
++		mempool_used += dhd->sssr_reg_info.vasip_regs.vasip_sr_size;
++
++		dhd->sssr_vasip_buf_after = (uint32 *)(dhd->sssr_mempool + mempool_used);
++		mempool_used += dhd->sssr_reg_info.vasip_regs.vasip_sr_size;
++	}
++
++	dhd->sssr_inited = TRUE;
++
++	return BCME_OK;
++
++}
++
++void
++dhd_sssr_dump_deinit(dhd_pub_t *dhd)
++{
++	int i;
++
++	dhd->sssr_inited = FALSE;
++	/* init all pointers to NULL */
++	for (i = 0; i < MAX_NUM_D11CORES; i++) {
++		dhd->sssr_d11_before[i] = NULL;
++		dhd->sssr_d11_after[i] = NULL;
++	}
++	dhd->sssr_vasip_buf_before = NULL;
++	dhd->sssr_vasip_buf_after = NULL;
++
++	return;
++}
++
++#endif /* DHD_SSSR_DUMP */
++
++#ifdef DHD_FW_COREDUMP
++void* dhd_get_fwdump_buf(dhd_pub_t *dhd_pub, uint32 length)
++{
++	if (!dhd_pub->soc_ram) {
++#if defined(CONFIG_DHD_USE_STATIC_BUF) && defined(DHD_USE_STATIC_MEMDUMP)
++		dhd_pub->soc_ram = (uint8*)DHD_OS_PREALLOC(dhd_pub,
++			DHD_PREALLOC_MEMDUMP_RAM, length);
++#else
++		dhd_pub->soc_ram = (uint8*) MALLOC(dhd_pub->osh, length);
++#endif /* CONFIG_DHD_USE_STATIC_BUF && DHD_USE_STATIC_MEMDUMP */
++	}
++
++	if (dhd_pub->soc_ram == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory for fw crash snap shot.\n",
++			__FUNCTION__));
++		dhd_pub->soc_ram_length = 0;
++	} else {
++		memset(dhd_pub->soc_ram, 0, length);
++		dhd_pub->soc_ram_length = length;
++	}
++
++	/* soc_ram free handled in dhd_{free,clear} */
++	return dhd_pub->soc_ram;
++}
++#endif /* DHD_FW_COREDUMP */
++
++/* to NDIS developer, the structure dhd_common is redundant,
++ * please do NOT merge it back from other branches !!!
++ */
++
++int
++dhd_common_socram_dump(dhd_pub_t *dhdp)
++{
++#ifdef BCMDBUS
++	return 0;
++#else
++	return dhd_socram_dump(dhdp->bus);
++#endif /* BCMDBUS */
++}
++
++static int
++dhd_dump(dhd_pub_t *dhdp, char *buf, int buflen)
++{
++	char eabuf[ETHER_ADDR_STR_LEN];
++
++	struct bcmstrbuf b;
++	struct bcmstrbuf *strbuf = &b;
++
++	if (!dhdp || !dhdp->prot || !buf) {
++		return BCME_ERROR;
++	}
++
++	bcm_binit(strbuf, buf, buflen);
++
++	/* Base DHD info */
++	bcm_bprintf(strbuf, "%s\n", dhd_version);
++	bcm_bprintf(strbuf, "\n");
++	bcm_bprintf(strbuf, "pub.up %d pub.txoff %d pub.busstate %d\n",
++	            dhdp->up, dhdp->txoff, dhdp->busstate);
++	bcm_bprintf(strbuf, "pub.hdrlen %u pub.maxctl %u pub.rxsz %u\n",
++	            dhdp->hdrlen, dhdp->maxctl, dhdp->rxsz);
++	bcm_bprintf(strbuf, "pub.iswl %d pub.drv_version %ld pub.mac %s\n",
++	            dhdp->iswl, dhdp->drv_version, bcm_ether_ntoa(&dhdp->mac, eabuf));
++	bcm_bprintf(strbuf, "pub.bcmerror %d tickcnt %u\n", dhdp->bcmerror, dhdp->tickcnt);
++
++	bcm_bprintf(strbuf, "dongle stats:\n");
++	bcm_bprintf(strbuf, "tx_packets %lu tx_bytes %lu tx_errors %lu tx_dropped %lu\n",
++	            dhdp->dstats.tx_packets, dhdp->dstats.tx_bytes,
++	            dhdp->dstats.tx_errors, dhdp->dstats.tx_dropped);
++	bcm_bprintf(strbuf, "rx_packets %lu rx_bytes %lu rx_errors %lu rx_dropped %lu\n",
++	            dhdp->dstats.rx_packets, dhdp->dstats.rx_bytes,
++	            dhdp->dstats.rx_errors, dhdp->dstats.rx_dropped);
++	bcm_bprintf(strbuf, "multicast %lu\n", dhdp->dstats.multicast);
++
++	bcm_bprintf(strbuf, "bus stats:\n");
++	bcm_bprintf(strbuf, "tx_packets %lu  tx_dropped %lu tx_multicast %lu tx_errors %lu\n",
++	            dhdp->tx_packets, dhdp->tx_dropped, dhdp->tx_multicast, dhdp->tx_errors);
++	bcm_bprintf(strbuf, "tx_ctlpkts %lu tx_ctlerrs %lu\n",
++	            dhdp->tx_ctlpkts, dhdp->tx_ctlerrs);
++	bcm_bprintf(strbuf, "rx_packets %lu rx_multicast %lu rx_errors %lu \n",
++	            dhdp->rx_packets, dhdp->rx_multicast, dhdp->rx_errors);
++	bcm_bprintf(strbuf, "rx_ctlpkts %lu rx_ctlerrs %lu rx_dropped %lu\n",
++	            dhdp->rx_ctlpkts, dhdp->rx_ctlerrs, dhdp->rx_dropped);
++	bcm_bprintf(strbuf, "rx_readahead_cnt %lu tx_realloc %lu\n",
++	            dhdp->rx_readahead_cnt, dhdp->tx_realloc);
++	bcm_bprintf(strbuf, "tx_pktgetfail %lu rx_pktgetfail %lu\n",
++	            dhdp->tx_pktgetfail, dhdp->rx_pktgetfail);
++	bcm_bprintf(strbuf, "\n");
++
++#ifdef DMAMAP_STATS
++	/* Add DMA MAP info */
++	bcm_bprintf(strbuf, "DMA MAP stats: \n");
++	bcm_bprintf(strbuf, "txdata: %lu size: %luK, rxdata: %lu size: %luK\n",
++			dhdp->dma_stats.txdata, KB(dhdp->dma_stats.txdata_sz),
++			dhdp->dma_stats.rxdata, KB(dhdp->dma_stats.rxdata_sz));
++#ifndef IOCTLRESP_USE_CONSTMEM
++	bcm_bprintf(strbuf, "IOCTL RX: %lu size: %luK ,",
++			dhdp->dma_stats.ioctl_rx, KB(dhdp->dma_stats.ioctl_rx_sz));
++#endif /* !IOCTLRESP_USE_CONSTMEM */
++	bcm_bprintf(strbuf, "EVENT RX: %lu size: %luK, INFO RX: %lu size: %luK, "
++			"TSBUF RX: %lu size %luK\n",
++			dhdp->dma_stats.event_rx, KB(dhdp->dma_stats.event_rx_sz),
++			dhdp->dma_stats.info_rx, KB(dhdp->dma_stats.info_rx_sz),
++			dhdp->dma_stats.tsbuf_rx, KB(dhdp->dma_stats.tsbuf_rx_sz));
++	bcm_bprintf(strbuf, "Total : %luK \n",
++			KB(dhdp->dma_stats.txdata_sz + dhdp->dma_stats.rxdata_sz +
++			dhdp->dma_stats.ioctl_rx_sz + dhdp->dma_stats.event_rx_sz +
++			dhdp->dma_stats.tsbuf_rx_sz));
++#endif /* DMAMAP_STATS */
++
++	/* Add any prot info */
++	dhd_prot_dump(dhdp, strbuf);
++	bcm_bprintf(strbuf, "\n");
++
++	/* Add any bus info */
++	dhd_bus_dump(dhdp, strbuf);
++
++
++#if defined(DHD_LB_STATS)
++	dhd_lb_stats_dump(dhdp, strbuf);
++#endif /* DHD_LB_STATS */
++#ifdef DHD_WET
++	if (dhd_get_wet_mode(dhdp)) {
++		bcm_bprintf(strbuf, "Wet Dump:\n");
++		dhd_wet_dump(dhdp, strbuf);
++		}
++#endif /* DHD_WET */
++	return (!strbuf->size ? BCME_BUFTOOSHORT : 0);
++}
++
++void
++dhd_dump_to_kernelog(dhd_pub_t *dhdp)
++{
++	char buf[512];
++
++	DHD_ERROR(("F/W version: %s\n", fw_version));
++	bcm_bprintf_bypass = TRUE;
++	dhd_dump(dhdp, buf, sizeof(buf));
++	bcm_bprintf_bypass = FALSE;
++}
++
++int
++dhd_wl_ioctl_cmd(dhd_pub_t *dhd_pub, int cmd, void *arg, int len, uint8 set, int ifidx)
++{
++	wl_ioctl_t ioc;
++
++	ioc.cmd = cmd;
++	ioc.buf = arg;
++	ioc.len = len;
++	ioc.set = set;
++
++	return dhd_wl_ioctl(dhd_pub, ifidx, &ioc, arg, len);
++}
++
++int
++dhd_wl_ioctl_get_intiovar(dhd_pub_t *dhd_pub, char *name, uint *pval,
++	int cmd, uint8 set, int ifidx)
++{
++	char iovbuf[WLC_IOCTL_SMLEN];
++	int ret = -1;
++
++	memset(iovbuf, 0, sizeof(iovbuf));
++	if (bcm_mkiovar(name, NULL, 0, iovbuf, sizeof(iovbuf))) {
++		ret = dhd_wl_ioctl_cmd(dhd_pub, cmd, iovbuf, sizeof(iovbuf), set, ifidx);
++		if (!ret) {
++			*pval = ltoh32(*((uint*)iovbuf));
++		} else {
++			DHD_ERROR(("%s: get int iovar %s failed, ERR %d\n",
++				__FUNCTION__, name, ret));
++		}
++	} else {
++		DHD_ERROR(("%s: mkiovar %s failed\n",
++			__FUNCTION__, name));
++	}
++
++	return ret;
++}
++
++int
++dhd_wl_ioctl_set_intiovar(dhd_pub_t *dhd_pub, char *name, uint val,
++	int cmd, uint8 set, int ifidx)
++{
++	char iovbuf[WLC_IOCTL_SMLEN] = {0};
++	int ret = -1;
++	int lval = htol32(val);
++	uint len;
++
++	len = bcm_mkiovar(name, (char*)&lval, sizeof(lval), iovbuf, sizeof(iovbuf));
++
++	if (len) {
++		ret = dhd_wl_ioctl_cmd(dhd_pub, cmd, iovbuf, len, set, ifidx);
++		if (ret) {
++			DHD_ERROR(("%s: set int iovar %s failed, ERR %d\n",
++				__FUNCTION__, name, ret));
++		}
++	} else {
++		DHD_ERROR(("%s: mkiovar %s failed\n",
++			__FUNCTION__, name));
++	}
++
++	return ret;
++}
++
++int
++dhd_wl_ioctl(dhd_pub_t *dhd_pub, int ifidx, wl_ioctl_t *ioc, void *buf, int len)
++{
++	int ret = BCME_ERROR;
++	unsigned long flags;
++#ifdef DUMP_IOCTL_IOV_LIST
++	dhd_iov_li_t *iov_li;
++#endif /* DUMP_IOCTL_IOV_LIST */
++	int hostsleep_set = 0;
++	int hostsleep_val = 0;
++
++#ifdef KEEPIF_ON_DEVICE_RESET
++		if (ioc->cmd == WLC_GET_VAR) {
++			dbus_config_t config;
++			config.general_param = 0;
++			if (!strcmp(buf, "wowl_activate")) {
++				config.general_param = 2; /* 1 (TRUE) after decreased by 1 */
++			} else if (!strcmp(buf, "wowl_clear")) {
++				config.general_param = 1; /* 0 (FALSE) after decreased by 1 */
++			}
++			if (config.general_param) {
++				config.config_id = DBUS_CONFIG_ID_KEEPIF_ON_DEVRESET;
++				config.general_param--;
++				dbus_set_config(dhd_pub->dbus, &config);
++			}
++		}
++#endif /* KEEPIF_ON_DEVICE_RESET */
++
++	if (dhd_os_proto_block(dhd_pub))
++	{
++#ifdef DHD_LOG_DUMP
++		int slen, i, val, rem, lval, min_len;
++		char *pval, *pos, *msg;
++		char tmp[64];
++
++		/* WLC_GET_VAR */
++		if (ioc->cmd == WLC_GET_VAR) {
++			min_len = MIN(sizeof(tmp) - 1, strlen(buf));
++			memset(tmp, 0, sizeof(tmp));
++			bcopy(buf, tmp, min_len);
++			tmp[min_len] = '\0';
++		}
++#endif /* DHD_LOG_DUMP */
++		DHD_LINUX_GENERAL_LOCK(dhd_pub, flags);
++		if (DHD_BUS_CHECK_DOWN_OR_DOWN_IN_PROGRESS(dhd_pub)) {
++#ifdef DHD_EFI
++			DHD_INFO(("%s: returning as busstate=%d\n",
++				__FUNCTION__, dhd_pub->busstate));
++#else
++			DHD_ERROR(("%s: returning as busstate=%d\n",
++				__FUNCTION__, dhd_pub->busstate));
++#endif /* DHD_EFI */
++			DHD_LINUX_GENERAL_UNLOCK(dhd_pub, flags);
++			dhd_os_proto_unblock(dhd_pub);
++			return -ENODEV;
++		}
++		DHD_BUS_BUSY_SET_IN_IOVAR(dhd_pub);
++		DHD_LINUX_GENERAL_UNLOCK(dhd_pub, flags);
++
++#ifdef DHD_PCIE_RUNTIMEPM
++		dhdpcie_runtime_bus_wake(dhd_pub, TRUE, dhd_wl_ioctl);
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++		DHD_LINUX_GENERAL_LOCK(dhd_pub, flags);
++		if (DHD_BUS_CHECK_SUSPEND_OR_SUSPEND_IN_PROGRESS(dhd_pub)) {
++			DHD_ERROR(("%s: bus is in suspend(%d) or suspending(0x%x) state!!\n",
++				__FUNCTION__, dhd_pub->busstate, dhd_pub->dhd_bus_busy_state));
++			DHD_BUS_BUSY_CLEAR_IN_IOVAR(dhd_pub);
++			dhd_os_busbusy_wake(dhd_pub);
++			DHD_LINUX_GENERAL_UNLOCK(dhd_pub, flags);
++			dhd_os_proto_unblock(dhd_pub);
++			return -ENODEV;
++		}
++		DHD_LINUX_GENERAL_UNLOCK(dhd_pub, flags);
++
++#if defined(WL_WLC_SHIM)
++		{
++			struct wl_shim_node *shim = dhd_pub_shim(dhd_pub);
++
++			wl_io_pport_t io_pport;
++			io_pport.dhd_pub = dhd_pub;
++			io_pport.ifidx = ifidx;
++
++			ret = wl_shim_ioctl(shim, ioc, len, &io_pport);
++			if (ret != BCME_OK) {
++				DHD_TRACE(("%s: wl_shim_ioctl(%d) ERR %d\n",
++					__FUNCTION__, ioc->cmd, ret));
++			}
++		}
++#else
++#ifdef DUMP_IOCTL_IOV_LIST
++		if (ioc->cmd != WLC_GET_MAGIC && ioc->cmd != WLC_GET_VERSION && buf) {
++			if (!(iov_li = MALLOC(dhd_pub->osh, sizeof(*iov_li)))) {
++				DHD_ERROR(("iovar dump list item allocation Failed\n"));
++			} else {
++				iov_li->cmd = ioc->cmd;
++				bcopy((char *)buf, iov_li->buff, strlen((char *)buf)+1);
++				dhd_iov_li_append(dhd_pub, &dhd_pub->dump_iovlist_head,
++					&iov_li->list);
++			}
++		}
++#endif /* DUMP_IOCTL_IOV_LIST */
++		if (dhd_conf_check_hostsleep(dhd_pub, ioc->cmd, ioc->buf, len,
++				&hostsleep_set, &hostsleep_val, &ret))
++			goto exit;
++		ret = dhd_prot_ioctl(dhd_pub, ifidx, ioc, buf, len);
++		dhd_conf_get_hostsleep(dhd_pub, hostsleep_set, hostsleep_val, ret);
++#ifdef DUMP_IOCTL_IOV_LIST
++		if (ret == -ETIMEDOUT) {
++			DHD_ERROR(("Last %d issued commands: Latest one is at bottom.\n",
++				IOV_LIST_MAX_LEN));
++			dhd_iov_li_print(&dhd_pub->dump_iovlist_head);
++		}
++#endif /* DUMP_IOCTL_IOV_LIST */
++#endif /* defined(WL_WLC_SHIM) */
++#ifdef DHD_LOG_DUMP
++		if (ioc->cmd == WLC_GET_VAR || ioc->cmd == WLC_SET_VAR) {
++			lval = 0;
++			slen = strlen(buf) + 1;
++			msg = (char*)buf;
++			if (len >= slen + sizeof(lval)) {
++				if (ioc->cmd == WLC_GET_VAR) {
++					msg = tmp;
++					lval = *(int*)buf;
++				} else {
++					min_len = MIN(ioc->len - slen, sizeof(int));
++					bcopy((msg + slen), &lval, min_len);
++				}
++			}
++			DHD_ERROR_MEM(("%s: cmd: %d, msg: %s, val: 0x%x, len: %d, set: %d\n",
++				ioc->cmd == WLC_GET_VAR ? "WLC_GET_VAR" : "WLC_SET_VAR",
++				ioc->cmd, msg, lval, ioc->len, ioc->set));
++		} else {
++			slen = ioc->len;
++			if (buf != NULL) {
++				val = *(int*)buf;
++				pval = (char*)buf;
++				pos = tmp;
++				rem = sizeof(tmp);
++				memset(tmp, 0, sizeof(tmp));
++				for (i = 0; i < slen; i++) {
++					if (rem <= 3) {
++						/* At least 2 byte required + 1 byte(NULL) */
++						break;
++					}
++					pos += snprintf(pos, rem, "%02x ", pval[i]);
++					rem = sizeof(tmp) - (int)(pos - tmp);
++				}
++				/* Do not dump for WLC_GET_MAGIC and WLC_GET_VERSION */
++				if (ioc->cmd != WLC_GET_MAGIC && ioc->cmd != WLC_GET_VERSION)
++					DHD_ERROR_MEM(("WLC_IOCTL: cmd: %d, val: %d(%s), "
++						"len: %d, set: %d\n",
++						ioc->cmd, val, tmp, ioc->len, ioc->set));
++			} else {
++				DHD_ERROR_MEM(("WLC_IOCTL: cmd: %d, buf is NULL\n", ioc->cmd));
++			}
++		}
++#endif /* DHD_LOG_DUMP */
++		if (ret && dhd_pub->up) {
++			/* Send hang event only if dhd_open() was success */
++			dhd_os_check_hang(dhd_pub, ifidx, ret);
++		}
++
++		if (ret == -ETIMEDOUT && !dhd_pub->up) {
++			DHD_ERROR(("%s: 'resumed on timeout' error is "
++				"occurred before the interface does not"
++				" bring up\n", __FUNCTION__));
++			dhd_pub->busstate = DHD_BUS_DOWN;
++		}
++
++exit:
++		DHD_LINUX_GENERAL_LOCK(dhd_pub, flags);
++		DHD_BUS_BUSY_CLEAR_IN_IOVAR(dhd_pub);
++		dhd_os_busbusy_wake(dhd_pub);
++		DHD_LINUX_GENERAL_UNLOCK(dhd_pub, flags);
++
++		dhd_os_proto_unblock(dhd_pub);
++
++	}
++
++	return ret;
++}
++
++uint wl_get_port_num(wl_io_pport_t *io_pport)
++{
++	return 0;
++}
++
++/* Get bssidx from iovar params
++ * Input:   dhd_pub - pointer to dhd_pub_t
++ *	    params  - IOVAR params
++ * Output:  idx	    - BSS index
++ *	    val	    - ponter to the IOVAR arguments
++ */
++static int
++dhd_iovar_parse_bssidx(dhd_pub_t *dhd_pub, const char *params, uint32 *idx, const char **val)
++{
++	char *prefix = "bsscfg:";
++	uint32	bssidx;
++
++	if (!(strncmp(params, prefix, strlen(prefix)))) {
++		/* per bss setting should be prefixed with 'bsscfg:' */
++		const char *p = params + strlen(prefix);
++
++		/* Skip Name */
++		while (*p != '\0')
++			p++;
++		/* consider null */
++		p = p + 1;
++		bcopy(p, &bssidx, sizeof(uint32));
++		/* Get corresponding dhd index */
++		bssidx = dhd_bssidx2idx(dhd_pub, htod32(bssidx));
++
++		if (bssidx >= DHD_MAX_IFS) {
++			DHD_ERROR(("%s Wrong bssidx provided\n", __FUNCTION__));
++			return BCME_ERROR;
++		}
++
++		/* skip bss idx */
++		p += sizeof(uint32);
++		*val = p;
++		*idx = bssidx;
++	} else {
++		DHD_ERROR(("%s: bad parameter for per bss iovar\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	return BCME_OK;
++}
++
++#if defined(DHD_DEBUG) && defined(BCMDBUS)
++/* USB Device console input function */
++int dhd_bus_console_in(dhd_pub_t *dhd, uchar *msg, uint msglen)
++{
++	DHD_TRACE(("%s \n", __FUNCTION__));
++
++	return dhd_iovar(dhd, 0, "cons", msg, msglen, NULL, 0, TRUE);
++
++}
++#endif /* DHD_DEBUG && BCMDBUS  */
++
++#ifdef DHD_DEBUG
++int
++dhd_mem_debug(dhd_pub_t *dhd, char *msg, uint msglen)
++{
++	unsigned long int_arg = 0;
++	char *p;
++	char *end_ptr = NULL;
++	dhd_dbg_mwli_t *mw_li;
++	dll_t *item, *next;
++	/* check if mwalloc, mwquery or mwfree was supplied arguement with space */
++	p = bcmstrstr(msg, " ");
++	if (p != NULL) {
++		/* space should be converted to null as separation flag for firmware */
++		*p = '\0';
++		/* store the argument in int_arg */
++		int_arg = bcm_strtoul(p+1, &end_ptr, 10);
++	}
++
++	if (!p && !strcmp(msg, "query")) {
++		/* lets query the list inetrnally */
++		if (dll_empty(dll_head_p(&dhd->mw_list_head))) {
++			DHD_ERROR(("memwaste list is empty, call mwalloc < size > to allocate\n"));
++			/* reset the id */
++			dhd->mw_id = 0;
++		} else {
++			for (item = dll_head_p(&dhd->mw_list_head);
++					!dll_end(&dhd->mw_list_head, item); item = next) {
++				next = dll_next_p(item);
++				mw_li = (dhd_dbg_mwli_t *)CONTAINEROF(item, dhd_dbg_mwli_t, list);
++				DHD_ERROR(("item: <id=%d, size=%d>\n", mw_li->id, mw_li->size));
++			}
++		}
++	} else if (p && end_ptr && (*end_ptr == '\0') && !strcmp(msg, "alloc")) {
++		int32 alloc_handle;
++		/* convert size into KB and append as integer */
++		*((int32 *)(p+1)) = int_arg*1024;
++		*(p+1+sizeof(int32)) = '\0';
++
++		/* recalculated length -> 5 bytes for "alloc" + 4 bytes for size +
++		 *1 bytes for null caracter
++		 */
++		msglen = strlen(msg) + sizeof(int32) + 1;
++		if (dhd_wl_ioctl_cmd(dhd, WLC_GET_VAR, msg, msglen, FALSE, 0) < 0) {
++			DHD_ERROR(("IOCTL failed for memdebug alloc\n"));
++		}
++
++		/* returned allocated handle from dongle, basically address of the allocated unit */
++		alloc_handle = *((int32 *)msg);
++
++		/* add a node in the list with tuple <id, handle, size> */
++		if (alloc_handle == 0) {
++			DHD_ERROR(("Reuqested size could not be allocated\n"));
++		} else if (!(mw_li = MALLOC(dhd->osh, sizeof(*mw_li)))) {
++			DHD_ERROR(("mw list item allocation Failed\n"));
++		} else {
++			mw_li->id = dhd->mw_id++;
++			mw_li->handle = alloc_handle;
++			mw_li->size = int_arg;
++			/* append the node in the list */
++			dll_append(&dhd->mw_list_head, &mw_li->list);
++		}
++	} else if (p && end_ptr && (*end_ptr == '\0') && !strcmp(msg, "free")) {
++		/* inform dongle to free wasted chunk */
++		int handle = 0;
++		int size = 0;
++		for (item = dll_head_p(&dhd->mw_list_head);
++				!dll_end(&dhd->mw_list_head, item); item = next) {
++			next = dll_next_p(item);
++			mw_li = (dhd_dbg_mwli_t *)CONTAINEROF(item, dhd_dbg_mwli_t, list);
++
++			if (mw_li->id == (int)int_arg) {
++				handle = mw_li->handle;
++				size = mw_li->size;
++				dll_delete(item);
++				MFREE(dhd->osh, mw_li, sizeof(*mw_li));
++			}
++		}
++		if (handle) {
++			int len;
++			/* append the free handle and the chunk size in first 8 bytes
++			 * after the command and null character
++			 */
++			*((int32 *)(p+1)) = handle;
++			*((int32 *)((p+1)+sizeof(int32))) = size;
++			/* append null as terminator */
++			*(p+1+2*sizeof(int32)) = '\0';
++			/* recalculated length -> 4 bytes for "free" + 8 bytes for hadnle and size
++			 * + 1 bytes for null caracter
++			 */
++			len = strlen(msg) + 2*sizeof(int32) + 1;
++			/* send iovar to free the chunk */
++			if (dhd_wl_ioctl_cmd(dhd, WLC_GET_VAR, msg, len, FALSE, 0) < 0) {
++				DHD_ERROR(("IOCTL failed for memdebug free\n"));
++			}
++		} else {
++			DHD_ERROR(("specified id does not exist\n"));
++		}
++	} else {
++		/* for all the wrong argument formats */
++		return BCME_BADARG;
++	}
++	return 0;
++}
++
++extern void
++dhd_mw_list_delete(dhd_pub_t *dhd, dll_t *list_head)
++{
++	dll_t *item;
++	dhd_dbg_mwli_t *mw_li;
++	while (!(dll_empty(list_head))) {
++		item = dll_head_p(list_head);
++		mw_li = (dhd_dbg_mwli_t *)CONTAINEROF(item, dhd_dbg_mwli_t, list);
++		dll_delete(item);
++		MFREE(dhd->osh, mw_li, sizeof(*mw_li));
++	}
++}
++#endif /* DHD_DEBUG */
++
++#ifdef PKT_STATICS
++extern pkt_statics_t tx_statics;
++extern void dhdsdio_txpktstatics(void);
++#endif
++
++static int
++dhd_doiovar(dhd_pub_t *dhd_pub, const bcm_iovar_t *vi, uint32 actionid, const char *name,
++            void *params, int plen, void *arg, int len, int val_size)
++{
++	int bcmerror = 0;
++	int32 int_val = 0;
++	uint32 dhd_ver_len, bus_api_rev_len;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++	DHD_TRACE(("%s: actionid = %d; name %s\n", __FUNCTION__, actionid, name));
++
++	if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid))) != 0)
++		goto exit;
++
++	if (plen >= (int)sizeof(int_val))
++		bcopy(params, &int_val, sizeof(int_val));
++
++	switch (actionid) {
++	case IOV_GVAL(IOV_VERSION):
++		/* Need to have checked buffer length */
++		dhd_ver_len = strlen(dhd_version);
++		bus_api_rev_len = strlen(bus_api_revision);
++		if (dhd_ver_len)
++			bcm_strncpy_s((char*)arg, dhd_ver_len, dhd_version, dhd_ver_len);
++		if (bus_api_rev_len)
++			bcm_strncat_s((char*)arg + dhd_ver_len, bus_api_rev_len, bus_api_revision,
++				bus_api_rev_len);
++#ifdef PKT_STATICS
++		memset((uint8*) &tx_statics, 0, sizeof(pkt_statics_t));
++#endif
++		break;
++
++	case IOV_GVAL(IOV_WLMSGLEVEL):
++		printf("android_msg_level=0x%x\n", android_msg_level);
++		printf("config_msg_level=0x%x\n", config_msg_level);
++#if defined(WL_WIRELESS_EXT)
++		int_val = (int32)iw_msg_level;
++		bcopy(&int_val, arg, val_size);
++		printf("iw_msg_level=0x%x\n", iw_msg_level);
++#endif
++#ifdef WL_CFG80211
++		int_val = (int32)wl_dbg_level;
++		bcopy(&int_val, arg, val_size);
++		printf("cfg_msg_level=0x%x\n", wl_dbg_level);
++#endif
++		break;
++
++	case IOV_SVAL(IOV_WLMSGLEVEL):
++		if (int_val & DHD_ANDROID_VAL) {
++			android_msg_level = (uint)(int_val & 0xFFFF);
++			printf("android_msg_level=0x%x\n", android_msg_level);
++		}
++		if (int_val & DHD_CONFIG_VAL) {
++			config_msg_level = (uint)(int_val & 0xFFFF);
++			printf("config_msg_level=0x%x\n", config_msg_level);
++		}
++#if defined(WL_WIRELESS_EXT)
++		if (int_val & DHD_IW_VAL) {
++			iw_msg_level = (uint)(int_val & 0xFFFF);
++			printf("iw_msg_level=0x%x\n", iw_msg_level);
++		}
++#endif
++#ifdef WL_CFG80211
++		if (int_val & DHD_CFG_VAL) {
++			wl_cfg80211_enable_trace((u32)(int_val & 0xFFFF));
++		}
++#endif
++		break;
++
++	case IOV_GVAL(IOV_MSGLEVEL):
++		int_val = (int32)dhd_msg_level;
++		bcopy(&int_val, arg, val_size);
++#ifdef PKT_STATICS
++		dhdsdio_txpktstatics();
++#endif
++		break;
++
++	case IOV_SVAL(IOV_MSGLEVEL):
++		dhd_msg_level = int_val;
++		break;
++
++	case IOV_GVAL(IOV_BCMERRORSTR):
++		bcm_strncpy_s((char *)arg, len, bcmerrorstr(dhd_pub->bcmerror), BCME_STRLEN);
++		((char *)arg)[BCME_STRLEN - 1] = 0x00;
++		break;
++
++	case IOV_GVAL(IOV_BCMERROR):
++		int_val = (int32)dhd_pub->bcmerror;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++#ifndef BCMDBUS
++	case IOV_GVAL(IOV_WDTICK):
++		int_val = (int32)dhd_watchdog_ms;
++		bcopy(&int_val, arg, val_size);
++		break;
++#endif /* !BCMDBUS */
++
++	case IOV_SVAL(IOV_WDTICK):
++		if (!dhd_pub->up) {
++			bcmerror = BCME_NOTUP;
++			break;
++		}
++
++		if (CUSTOM_DHD_WATCHDOG_MS == 0 && int_val == 0) {
++			dhd_watchdog_ms = (uint)int_val;
++		}
++
++		dhd_os_wd_timer(dhd_pub, (uint)int_val);
++		break;
++
++	case IOV_GVAL(IOV_DUMP):
++		bcmerror = dhd_dump(dhd_pub, arg, len);
++		break;
++
++#ifndef BCMDBUS
++	case IOV_GVAL(IOV_DCONSOLE_POLL):
++		int_val = (int32)dhd_console_ms;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DCONSOLE_POLL):
++		dhd_console_ms = (uint)int_val;
++		break;
++
++	case IOV_SVAL(IOV_CONS):
++		if (len > 0) {
++#ifdef CONSOLE_DPC
++			bcmerror = dhd_bus_txcons(dhd_pub, arg, len - 1);
++#else
++			bcmerror = dhd_bus_console_in(dhd_pub, arg, len - 1);
++#endif
++		}
++		break;
++#endif /* !BCMDBUS */
++
++	case IOV_SVAL(IOV_CLEARCOUNTS):
++		dhd_pub->tx_packets = dhd_pub->rx_packets = 0;
++		dhd_pub->tx_errors = dhd_pub->rx_errors = 0;
++		dhd_pub->tx_ctlpkts = dhd_pub->rx_ctlpkts = 0;
++		dhd_pub->tx_ctlerrs = dhd_pub->rx_ctlerrs = 0;
++		dhd_pub->tx_dropped = 0;
++		dhd_pub->rx_dropped = 0;
++		dhd_pub->tx_pktgetfail = 0;
++		dhd_pub->rx_pktgetfail = 0;
++		dhd_pub->rx_readahead_cnt = 0;
++		dhd_pub->tx_realloc = 0;
++		dhd_pub->wd_dpc_sched = 0;
++		memset(&dhd_pub->dstats, 0, sizeof(dhd_pub->dstats));
++		dhd_bus_clearcounts(dhd_pub);
++#ifdef PROP_TXSTATUS
++		/* clear proptxstatus related counters */
++		dhd_wlfc_clear_counts(dhd_pub);
++#endif /* PROP_TXSTATUS */
++#if defined(DHD_LB_STATS)
++		DHD_LB_STATS_RESET(dhd_pub);
++#endif /* DHD_LB_STATS */
++		break;
++
++
++	case IOV_GVAL(IOV_IOCTLTIMEOUT): {
++		int_val = (int32)dhd_os_get_ioctl_resp_timeout();
++		bcopy(&int_val, arg, sizeof(int_val));
++		break;
++	}
++
++	case IOV_SVAL(IOV_IOCTLTIMEOUT): {
++		if (int_val <= 0)
++			bcmerror = BCME_BADARG;
++		else
++			dhd_os_set_ioctl_resp_timeout((unsigned int)int_val);
++		break;
++	}
++
++#ifdef PROP_TXSTATUS
++	case IOV_GVAL(IOV_PROPTXSTATUS_ENABLE): {
++		bool wlfc_enab = FALSE;
++		bcmerror = dhd_wlfc_get_enable(dhd_pub, &wlfc_enab);
++		if (bcmerror != BCME_OK)
++			goto exit;
++		int_val = wlfc_enab ? 1 : 0;
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_PROPTXSTATUS_ENABLE): {
++		bool wlfc_enab = FALSE;
++		bcmerror = dhd_wlfc_get_enable(dhd_pub, &wlfc_enab);
++		if (bcmerror != BCME_OK)
++			goto exit;
++
++		/* wlfc is already set as desired */
++		if (wlfc_enab == (int_val == 0 ? FALSE : TRUE))
++			goto exit;
++
++		if (int_val == TRUE)
++			bcmerror = dhd_wlfc_init(dhd_pub);
++		else
++			bcmerror = dhd_wlfc_deinit(dhd_pub);
++
++		break;
++	}
++	case IOV_GVAL(IOV_PROPTXSTATUS_MODE):
++		bcmerror = dhd_wlfc_get_mode(dhd_pub, &int_val);
++		if (bcmerror != BCME_OK)
++			goto exit;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_PROPTXSTATUS_MODE):
++		dhd_wlfc_set_mode(dhd_pub, int_val);
++		break;
++
++	case IOV_GVAL(IOV_PROPTXSTATUS_MODULE_IGNORE):
++		bcmerror = dhd_wlfc_get_module_ignore(dhd_pub, &int_val);
++		if (bcmerror != BCME_OK)
++			goto exit;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_PROPTXSTATUS_MODULE_IGNORE):
++		dhd_wlfc_set_module_ignore(dhd_pub, int_val);
++		break;
++
++	case IOV_GVAL(IOV_PROPTXSTATUS_CREDIT_IGNORE):
++		bcmerror = dhd_wlfc_get_credit_ignore(dhd_pub, &int_val);
++		if (bcmerror != BCME_OK)
++			goto exit;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_PROPTXSTATUS_CREDIT_IGNORE):
++		dhd_wlfc_set_credit_ignore(dhd_pub, int_val);
++		break;
++
++	case IOV_GVAL(IOV_PROPTXSTATUS_TXSTATUS_IGNORE):
++		bcmerror = dhd_wlfc_get_txstatus_ignore(dhd_pub, &int_val);
++		if (bcmerror != BCME_OK)
++			goto exit;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_PROPTXSTATUS_TXSTATUS_IGNORE):
++		dhd_wlfc_set_txstatus_ignore(dhd_pub, int_val);
++		break;
++
++	case IOV_GVAL(IOV_PROPTXSTATUS_RXPKT_CHK):
++		bcmerror = dhd_wlfc_get_rxpkt_chk(dhd_pub, &int_val);
++		if (bcmerror != BCME_OK)
++			goto exit;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_PROPTXSTATUS_RXPKT_CHK):
++		dhd_wlfc_set_rxpkt_chk(dhd_pub, int_val);
++		break;
++
++#endif /* PROP_TXSTATUS */
++
++	case IOV_GVAL(IOV_BUS_TYPE):
++		/* The dhd application queries the driver to check if its usb or sdio.  */
++#ifdef BCMDBUS
++		int_val = BUS_TYPE_USB;
++#endif /* BCMDBUS */
++#ifdef BCMSDIO
++		int_val = BUS_TYPE_SDIO;
++#endif
++#ifdef PCIE_FULL_DONGLE
++		int_val = BUS_TYPE_PCIE;
++#endif
++		bcopy(&int_val, arg, val_size);
++		break;
++
++
++#ifdef WLMEDIA_HTSF
++	case IOV_GVAL(IOV_WLPKTDLYSTAT_SZ):
++		int_val = dhd_pub->htsfdlystat_sz;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_WLPKTDLYSTAT_SZ):
++		dhd_pub->htsfdlystat_sz = int_val & 0xff;
++		printf("Setting tsfdlystat_sz:%d\n", dhd_pub->htsfdlystat_sz);
++		break;
++#endif
++	case IOV_SVAL(IOV_CHANGEMTU):
++		int_val &= 0xffff;
++		bcmerror = dhd_change_mtu(dhd_pub, int_val, 0);
++		break;
++
++	case IOV_GVAL(IOV_HOSTREORDER_FLOWS):
++	{
++		uint i = 0;
++		uint8 *ptr = (uint8 *)arg;
++		uint8 count = 0;
++
++		ptr++;
++		for (i = 0; i < WLHOST_REORDERDATA_MAXFLOWS; i++) {
++			if (dhd_pub->reorder_bufs[i] != NULL) {
++				*ptr = dhd_pub->reorder_bufs[i]->flow_id;
++				ptr++;
++				count++;
++			}
++		}
++		ptr = (uint8 *)arg;
++		*ptr = count;
++		break;
++	}
++#ifdef DHDTCPACK_SUPPRESS
++	case IOV_GVAL(IOV_TCPACK_SUPPRESS): {
++		int_val = (uint32)dhd_pub->tcpack_sup_mode;
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_TCPACK_SUPPRESS): {
++		bcmerror = dhd_tcpack_suppress_set(dhd_pub, (uint8)int_val);
++		break;
++	}
++#endif /* DHDTCPACK_SUPPRESS */
++#ifdef DHD_WMF
++	case IOV_GVAL(IOV_WMF_BSS_ENAB): {
++		uint32	bssidx;
++		dhd_wmf_t *wmf;
++		const char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: wmf_bss_enable: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		wmf = dhd_wmf_conf(dhd_pub, bssidx);
++		int_val = wmf->wmf_enable ? 1 :0;
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_WMF_BSS_ENAB): {
++		/* Enable/Disable WMF */
++		uint32	bssidx;
++		dhd_wmf_t *wmf;
++		const char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: wmf_bss_enable: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		ASSERT(val);
++		bcopy(val, &int_val, sizeof(uint32));
++		wmf = dhd_wmf_conf(dhd_pub, bssidx);
++		if (wmf->wmf_enable == int_val)
++			break;
++		if (int_val) {
++			/* Enable WMF */
++			if (dhd_wmf_instance_add(dhd_pub, bssidx) != BCME_OK) {
++				DHD_ERROR(("%s: Error in creating WMF instance\n",
++				__FUNCTION__));
++				break;
++			}
++			if (dhd_wmf_start(dhd_pub, bssidx) != BCME_OK) {
++				DHD_ERROR(("%s: Failed to start WMF\n", __FUNCTION__));
++				break;
++			}
++			wmf->wmf_enable = TRUE;
++		} else {
++			/* Disable WMF */
++			wmf->wmf_enable = FALSE;
++			dhd_wmf_stop(dhd_pub, bssidx);
++			dhd_wmf_instance_del(dhd_pub, bssidx);
++		}
++		break;
++	}
++	case IOV_GVAL(IOV_WMF_UCAST_IGMP):
++		int_val = dhd_pub->wmf_ucast_igmp ? 1 : 0;
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_SVAL(IOV_WMF_UCAST_IGMP):
++		if (dhd_pub->wmf_ucast_igmp == int_val)
++			break;
++
++		if (int_val >= OFF && int_val <= ON)
++			dhd_pub->wmf_ucast_igmp = int_val;
++		else
++			bcmerror = BCME_RANGE;
++		break;
++	case IOV_GVAL(IOV_WMF_MCAST_DATA_SENDUP):
++		int_val = dhd_wmf_mcast_data_sendup(dhd_pub, 0, FALSE, FALSE);
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_SVAL(IOV_WMF_MCAST_DATA_SENDUP):
++		dhd_wmf_mcast_data_sendup(dhd_pub, 0, TRUE, int_val);
++		break;
++
++#ifdef WL_IGMP_UCQUERY
++	case IOV_GVAL(IOV_WMF_UCAST_IGMP_QUERY):
++		int_val = dhd_pub->wmf_ucast_igmp_query ? 1 : 0;
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_SVAL(IOV_WMF_UCAST_IGMP_QUERY):
++		if (dhd_pub->wmf_ucast_igmp_query == int_val)
++			break;
++
++		if (int_val >= OFF && int_val <= ON)
++			dhd_pub->wmf_ucast_igmp_query = int_val;
++		else
++			bcmerror = BCME_RANGE;
++		break;
++#endif /* WL_IGMP_UCQUERY */
++#ifdef DHD_UCAST_UPNP
++	case IOV_GVAL(IOV_WMF_UCAST_UPNP):
++		int_val = dhd_pub->wmf_ucast_upnp ? 1 : 0;
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_SVAL(IOV_WMF_UCAST_UPNP):
++		if (dhd_pub->wmf_ucast_upnp == int_val)
++			break;
++
++		if (int_val >= OFF && int_val <= ON)
++			dhd_pub->wmf_ucast_upnp = int_val;
++		else
++			bcmerror = BCME_RANGE;
++		break;
++#endif /* DHD_UCAST_UPNP */
++
++	case IOV_GVAL(IOV_WMF_PSTA_DISABLE): {
++		uint32	bssidx;
++		const char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: ap isoalate: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		int_val = dhd_get_wmf_psta_disable(dhd_pub, bssidx);
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++
++	case IOV_SVAL(IOV_WMF_PSTA_DISABLE): {
++		uint32	bssidx;
++		const char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: ap isolate: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		ASSERT(val);
++		bcopy(val, &int_val, sizeof(uint32));
++		dhd_set_wmf_psta_disable(dhd_pub, bssidx, int_val);
++		break;
++	}
++#endif /* DHD_WMF */
++
++#if defined(TRAFFIC_MGMT_DWM)
++	case IOV_SVAL(IOV_TRAFFIC_MGMT_DWM): {
++			trf_mgmt_filter_list_t   *trf_mgmt_filter_list =
++				(trf_mgmt_filter_list_t *)(arg);
++			bcmerror = traffic_mgmt_add_dwm_filter(dhd_pub, trf_mgmt_filter_list, len);
++		}
++		break;
++#endif 
++
++#ifdef DHD_L2_FILTER
++	case IOV_GVAL(IOV_DHCP_UNICAST): {
++		uint32 bssidx;
++		const char *val;
++		if (dhd_iovar_parse_bssidx(dhd_pub, name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: IOV_DHCP_UNICAST: bad parameterand name = %s\n",
++				__FUNCTION__, name));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		int_val = dhd_get_dhcp_unicast_status(dhd_pub, bssidx);
++		memcpy(arg, &int_val, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_DHCP_UNICAST): {
++		uint32	bssidx;
++		const char *val;
++		if (dhd_iovar_parse_bssidx(dhd_pub, name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: IOV_DHCP_UNICAST: bad parameterand name = %s\n",
++				__FUNCTION__, name));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		memcpy(&int_val, val, sizeof(int_val));
++		bcmerror = dhd_set_dhcp_unicast_status(dhd_pub, bssidx, int_val ? 1 : 0);
++		break;
++	}
++	case IOV_GVAL(IOV_BLOCK_PING): {
++		uint32 bssidx;
++		const char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: IOV_BLOCK_PING: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		int_val = dhd_get_block_ping_status(dhd_pub, bssidx);
++		memcpy(arg, &int_val, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_BLOCK_PING): {
++		uint32	bssidx;
++		const char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: IOV_BLOCK_PING: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		memcpy(&int_val, val, sizeof(int_val));
++		bcmerror = dhd_set_block_ping_status(dhd_pub, bssidx, int_val ? 1 : 0);
++		break;
++	}
++	case IOV_GVAL(IOV_PROXY_ARP): {
++		uint32	bssidx;
++		const char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: IOV_PROXY_ARP: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		int_val = dhd_get_parp_status(dhd_pub, bssidx);
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_PROXY_ARP): {
++		uint32	bssidx;
++		const char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: IOV_PROXY_ARP: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		bcopy(val, &int_val, sizeof(int_val));
++
++		/* Issue a iovar request to WL to update the proxy arp capability bit
++		 * in the Extended Capability IE of beacons/probe responses.
++		 */
++		bcmerror = dhd_iovar(dhd_pub, bssidx, "proxy_arp_advertise", val, sizeof(int_val),
++				NULL, 0, TRUE);
++		if (bcmerror == BCME_OK) {
++			dhd_set_parp_status(dhd_pub, bssidx, int_val ? 1 : 0);
++		}
++		break;
++	}
++	case IOV_GVAL(IOV_GRAT_ARP): {
++		uint32 bssidx;
++		const char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: IOV_GRAT_ARP: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		int_val = dhd_get_grat_arp_status(dhd_pub, bssidx);
++		memcpy(arg, &int_val, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_GRAT_ARP): {
++		uint32	bssidx;
++		const char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: IOV_GRAT_ARP: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		memcpy(&int_val, val, sizeof(int_val));
++		bcmerror = dhd_set_grat_arp_status(dhd_pub, bssidx, int_val ? 1 : 0);
++		break;
++	}
++#endif /* DHD_L2_FILTER */
++	case IOV_SVAL(IOV_DHD_IE): {
++		uint32	bssidx;
++		const char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: dhd ie: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		break;
++	}
++	case IOV_GVAL(IOV_AP_ISOLATE): {
++		uint32	bssidx;
++		const char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: ap isoalate: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		int_val = dhd_get_ap_isolate(dhd_pub, bssidx);
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_AP_ISOLATE): {
++		uint32	bssidx;
++		const char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: ap isolate: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		ASSERT(val);
++		bcopy(val, &int_val, sizeof(uint32));
++		dhd_set_ap_isolate(dhd_pub, bssidx, int_val);
++		break;
++	}
++#ifdef DHD_PSTA
++	case IOV_GVAL(IOV_PSTA): {
++		int_val = dhd_get_psta_mode(dhd_pub);
++		bcopy(&int_val, arg, val_size);
++		break;
++		}
++	case IOV_SVAL(IOV_PSTA): {
++		if (int_val >= DHD_MODE_PSTA_DISABLED && int_val <= DHD_MODE_PSR) {
++			dhd_set_psta_mode(dhd_pub, int_val);
++		} else {
++			bcmerror = BCME_RANGE;
++		}
++		break;
++		}
++#endif /* DHD_PSTA */
++#ifdef DHD_WET
++	case IOV_GVAL(IOV_WET):
++		 int_val = dhd_get_wet_mode(dhd_pub);
++		 bcopy(&int_val, arg, val_size);
++		 break;
++
++	case IOV_SVAL(IOV_WET):
++		 if (int_val == 0 || int_val == 1) {
++			 dhd_set_wet_mode(dhd_pub, int_val);
++			 /* Delete the WET DB when disabled */
++			 if (!int_val) {
++				 dhd_wet_sta_delete_list(dhd_pub);
++			 }
++		 } else {
++			 bcmerror = BCME_RANGE;
++		 }
++				 break;
++	case IOV_SVAL(IOV_WET_HOST_IPV4):
++			dhd_set_wet_host_ipv4(dhd_pub, params, plen);
++			break;
++	case IOV_SVAL(IOV_WET_HOST_MAC):
++			dhd_set_wet_host_mac(dhd_pub, params, plen);
++		break;
++#endif /* DHD_WET */
++#ifdef DHD_MCAST_REGEN
++	case IOV_GVAL(IOV_MCAST_REGEN_BSS_ENABLE): {
++		uint32	bssidx;
++		const char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: mcast_regen_bss_enable: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		int_val = dhd_get_mcast_regen_bss_enable(dhd_pub, bssidx);
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++
++	case IOV_SVAL(IOV_MCAST_REGEN_BSS_ENABLE): {
++		uint32	bssidx;
++		const char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: mcast_regen_bss_enable: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		ASSERT(val);
++		bcopy(val, &int_val, sizeof(uint32));
++		dhd_set_mcast_regen_bss_enable(dhd_pub, bssidx, int_val);
++		break;
++	}
++#endif /* DHD_MCAST_REGEN */
++
++	case IOV_GVAL(IOV_CFG80211_OPMODE): {
++		int_val = (int32)dhd_pub->op_mode;
++		bcopy(&int_val, arg, sizeof(int_val));
++		break;
++		}
++	case IOV_SVAL(IOV_CFG80211_OPMODE): {
++		if (int_val <= 0)
++			bcmerror = BCME_BADARG;
++		else
++			dhd_pub->op_mode = int_val;
++		break;
++	}
++
++	case IOV_GVAL(IOV_ASSERT_TYPE):
++		int_val = g_assert_type;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_ASSERT_TYPE):
++		g_assert_type = (uint32)int_val;
++		break;
++
++
++#if !defined(MACOSX_DHD)
++	case IOV_GVAL(IOV_LMTEST): {
++		*(uint32 *)arg = (uint32)lmtest;
++		break;
++	}
++
++	case IOV_SVAL(IOV_LMTEST): {
++		uint32 val = *(uint32 *)arg;
++		if (val > 50)
++			bcmerror = BCME_BADARG;
++		else {
++			lmtest = (uint)val;
++			DHD_ERROR(("%s: lmtest %s\n",
++				__FUNCTION__, (lmtest == FALSE)? "OFF" : "ON"));
++		}
++		break;
++	}
++#endif 
++
++#ifdef SHOW_LOGTRACE
++	case IOV_GVAL(IOV_DUMP_TRACE_LOG): {
++		trace_buf_info_t *trace_buf_info;
++
++		trace_buf_info = (trace_buf_info_t *)MALLOC(dhd_pub->osh,
++				sizeof(trace_buf_info_t));
++		if (trace_buf_info != NULL) {
++			dhd_get_read_buf_ptr(dhd_pub, trace_buf_info);
++			memcpy((void*)arg, (void*)trace_buf_info, sizeof(trace_buf_info_t));
++			MFREE(dhd_pub->osh, trace_buf_info, sizeof(trace_buf_info_t));
++		} else {
++			DHD_ERROR(("Memory allocation Failed\n"));
++			bcmerror = BCME_NOMEM;
++		}
++		break;
++	}
++#endif /* SHOW_LOGTRACE */
++#ifdef REPORT_FATAL_TIMEOUTS
++	case IOV_GVAL(IOV_SCAN_TO): {
++		dhd_get_scan_to_val(dhd_pub, (uint32 *)&int_val);
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_SCAN_TO): {
++		dhd_set_scan_to_val(dhd_pub, (uint32)int_val);
++		break;
++	}
++	case IOV_GVAL(IOV_JOIN_TO): {
++		dhd_get_join_to_val(dhd_pub, (uint32 *)&int_val);
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_JOIN_TO): {
++		dhd_set_join_to_val(dhd_pub, (uint32)int_val);
++		break;
++	}
++	case IOV_GVAL(IOV_CMD_TO): {
++		dhd_get_cmd_to_val(dhd_pub, (uint32 *)&int_val);
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_CMD_TO): {
++		dhd_set_cmd_to_val(dhd_pub, (uint32)int_val);
++		break;
++	}
++	case IOV_GVAL(IOV_OQS_TO): {
++		dhd_get_bus_to_val(dhd_pub, (uint32 *)&int_val);
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_OQS_TO): {
++		dhd_set_bus_to_val(dhd_pub, (uint32)int_val);
++		break;
++	}
++#endif /* REPORT_FATAL_TIMEOUTS */
++#ifdef DHD_DEBUG
++#if defined(BCMSDIO) || defined(BCMPCIE)
++	case IOV_GVAL(IOV_DONGLE_TRAP_TYPE):
++		if (dhd_pub->dongle_trap_occured)
++			int_val = ltoh32(dhd_pub->last_trap_info.type);
++		else
++			int_val = 0;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_DONGLE_TRAP_INFO):
++	{
++		struct bcmstrbuf strbuf;
++		bcm_binit(&strbuf, arg, len);
++		if (dhd_pub->dongle_trap_occured == FALSE) {
++			bcm_bprintf(&strbuf, "no trap recorded\n");
++			break;
++		}
++		dhd_bus_dump_trap_info(dhd_pub->bus, &strbuf);
++		break;
++	}
++
++	case IOV_GVAL(IOV_BPADDR):
++		{
++			sdreg_t sdreg;
++			uint32 addr, size;
++
++			memcpy(&sdreg, params, sizeof(sdreg));
++
++			addr = sdreg.offset;
++			size = sdreg.func;
++
++			bcmerror = dhd_bus_readwrite_bp_addr(dhd_pub, addr, size,
++				(uint *)&int_val, TRUE);
++
++			memcpy(arg, &int_val, sizeof(int32));
++
++			break;
++		}
++
++	case IOV_SVAL(IOV_BPADDR):
++		{
++			sdreg_t sdreg;
++			uint32 addr, size;
++
++			memcpy(&sdreg, params, sizeof(sdreg));
++
++			addr = sdreg.offset;
++			size = sdreg.func;
++
++			bcmerror = dhd_bus_readwrite_bp_addr(dhd_pub, addr, size,
++				(uint *)&sdreg.value,
++				FALSE);
++
++			break;
++		}
++#endif /* BCMSDIO || BCMPCIE */
++	case IOV_SVAL(IOV_MEM_DEBUG):
++		if (len > 0) {
++			bcmerror = dhd_mem_debug(dhd_pub, arg, len - 1);
++		}
++		break;
++#endif /* DHD_DEBUG */
++#if defined(DHD_EFI) && defined(DHD_LOG_DUMP)
++	case IOV_GVAL(IOV_LOG_CAPTURE_ENABLE):
++		{
++			int_val = dhd_pub->log_capture_enable;
++			bcopy(&int_val, arg, val_size);
++			break;
++		}
++
++	case IOV_SVAL(IOV_LOG_CAPTURE_ENABLE):
++		{
++			dhd_pub->log_capture_enable = (uint8)int_val;
++			break;
++		}
++
++	case IOV_GVAL(IOV_LOG_DUMP):
++		{
++			dhd_prot_debug_info_print(dhd_pub);
++			dhd_bus_mem_dump(dhd_pub);
++			break;
++		}
++#endif /* DHD_EFI && DHD_LOG_DUMP */
++	default:
++		bcmerror = BCME_UNSUPPORTED;
++		break;
++	}
++
++exit:
++	DHD_TRACE(("%s: actionid %d, bcmerror %d\n", __FUNCTION__, actionid, bcmerror));
++	return bcmerror;
++}
++
++/* Store the status of a connection attempt for later retrieval by an iovar */
++void
++dhd_store_conn_status(uint32 event, uint32 status, uint32 reason)
++{
++	/* Do not overwrite a WLC_E_PRUNE with a WLC_E_SET_SSID
++	 * because an encryption/rsn mismatch results in both events, and
++	 * the important information is in the WLC_E_PRUNE.
++	 */
++	if (!(event == WLC_E_SET_SSID && status == WLC_E_STATUS_FAIL &&
++	      dhd_conn_event == WLC_E_PRUNE)) {
++		dhd_conn_event = event;
++		dhd_conn_status = status;
++		dhd_conn_reason = reason;
++	}
++}
++
++bool
++dhd_prec_enq(dhd_pub_t *dhdp, struct pktq *q, void *pkt, int prec)
++{
++	void *p;
++	int eprec = -1;		/* precedence to evict from */
++	bool discard_oldest;
++
++	/* Fast case, precedence queue is not full and we are also not
++	 * exceeding total queue length
++	 */
++	if (!pktq_pfull(q, prec) && !pktq_full(q)) {
++		pktq_penq(q, prec, pkt);
++		return TRUE;
++	}
++
++	/* Determine precedence from which to evict packet, if any */
++	if (pktq_pfull(q, prec))
++		eprec = prec;
++	else if (pktq_full(q)) {
++		p = pktq_peek_tail(q, &eprec);
++		ASSERT(p);
++		if (eprec > prec || eprec < 0)
++			return FALSE;
++	}
++
++	/* Evict if needed */
++	if (eprec >= 0) {
++		/* Detect queueing to unconfigured precedence */
++		ASSERT(!pktq_pempty(q, eprec));
++		discard_oldest = AC_BITMAP_TST(dhdp->wme_dp, eprec);
++		if (eprec == prec && !discard_oldest)
++			return FALSE;		/* refuse newer (incoming) packet */
++		/* Evict packet according to discard policy */
++		p = discard_oldest ? pktq_pdeq(q, eprec) : pktq_pdeq_tail(q, eprec);
++		ASSERT(p);
++#ifdef DHDTCPACK_SUPPRESS
++		if (dhd_tcpack_check_xmit(dhdp, p) == BCME_ERROR) {
++			DHD_ERROR(("%s %d: tcpack_suppress ERROR!!! Stop using it\n",
++				__FUNCTION__, __LINE__));
++			dhd_tcpack_suppress_set(dhdp, TCPACK_SUP_OFF);
++		}
++#endif /* DHDTCPACK_SUPPRESS */
++		PKTFREE(dhdp->osh, p, TRUE);
++	}
++
++	/* Enqueue */
++	p = pktq_penq(q, prec, pkt);
++	ASSERT(p);
++
++	return TRUE;
++}
++
++/*
++ * Functions to drop proper pkts from queue:
++ *	If one pkt in queue is non-fragmented, drop first non-fragmented pkt only
++ *	If all pkts in queue are all fragmented, find and drop one whole set fragmented pkts
++ *	If can't find pkts matching upper 2 cases, drop first pkt anyway
++ */
++bool
++dhd_prec_drop_pkts(dhd_pub_t *dhdp, struct pktq *pq, int prec, f_droppkt_t fn)
++{
++	struct pktq_prec *q = NULL;
++	void *p, *prev = NULL, *next = NULL, *first = NULL, *last = NULL, *prev_first = NULL;
++	pkt_frag_t frag_info;
++
++	ASSERT(dhdp && pq);
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	q = &pq->q[prec];
++	p = q->head;
++
++	if (p == NULL)
++		return FALSE;
++
++	while (p) {
++		frag_info = pkt_frag_info(dhdp->osh, p);
++		if (frag_info == DHD_PKT_FRAG_NONE) {
++			break;
++		} else if (frag_info == DHD_PKT_FRAG_FIRST) {
++			if (first) {
++				/* No last frag pkt, use prev as last */
++				last = prev;
++				break;
++			} else {
++				first = p;
++				prev_first = prev;
++			}
++		} else if (frag_info == DHD_PKT_FRAG_LAST) {
++			if (first) {
++				last = p;
++				break;
++			}
++		}
++
++		prev = p;
++		p = PKTLINK(p);
++	}
++
++	if ((p == NULL) || ((frag_info != DHD_PKT_FRAG_NONE) && !(first && last))) {
++		/* Not found matching pkts, use oldest */
++		prev = NULL;
++		p = q->head;
++		frag_info = 0;
++	}
++
++	if (frag_info == DHD_PKT_FRAG_NONE) {
++		first = last = p;
++		prev_first = prev;
++	}
++
++	p = first;
++	while (p) {
++		next = PKTLINK(p);
++		q->len--;
++		pq->len--;
++
++		PKTSETLINK(p, NULL);
++
++		if (fn)
++			fn(dhdp, prec, p, TRUE);
++
++		if (p == last)
++			break;
++
++		p = next;
++	}
++
++	if (prev_first == NULL) {
++		if ((q->head = next) == NULL)
++			q->tail = NULL;
++	} else {
++		PKTSETLINK(prev_first, next);
++		if (!next)
++			q->tail = prev_first;
++	}
++
++	return TRUE;
++}
++
++static int
++dhd_iovar_op(dhd_pub_t *dhd_pub, const char *name,
++	void *params, int plen, void *arg, int len, bool set)
++{
++	int bcmerror = 0;
++	int val_size;
++	const bcm_iovar_t *vi = NULL;
++	uint32 actionid;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	ASSERT(name);
++	ASSERT(len >= 0);
++
++	/* Get MUST have return space */
++	ASSERT(set || (arg && len));
++
++	/* Set does NOT take qualifiers */
++	ASSERT(!set || (!params && !plen));
++
++	if ((vi = bcm_iovar_lookup(dhd_iovars, name)) == NULL) {
++		bcmerror = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++	DHD_CTL(("%s: %s %s, len %d plen %d\n", __FUNCTION__,
++		name, (set ? "set" : "get"), len, plen));
++
++	/* set up 'params' pointer in case this is a set command so that
++	 * the convenience int and bool code can be common to set and get
++	 */
++	if (params == NULL) {
++		params = arg;
++		plen = len;
++	}
++
++	if (vi->type == IOVT_VOID)
++		val_size = 0;
++	else if (vi->type == IOVT_BUFFER)
++		val_size = len;
++	else
++		/* all other types are integer sized */
++		val_size = sizeof(int);
++
++	actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
++
++	bcmerror = dhd_doiovar(dhd_pub, vi, actionid, name, params, plen, arg, len, val_size);
++
++exit:
++	return bcmerror;
++}
++
++int
++dhd_ioctl(dhd_pub_t * dhd_pub, dhd_ioctl_t *ioc, void *buf, uint buflen)
++{
++	int bcmerror = 0;
++	unsigned long flags;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (!buf) {
++		return BCME_BADARG;
++	}
++
++	dhd_os_dhdiovar_lock(dhd_pub);
++	switch (ioc->cmd) {
++		case DHD_GET_MAGIC:
++			if (buflen < sizeof(int))
++				bcmerror = BCME_BUFTOOSHORT;
++			else
++				*(int*)buf = DHD_IOCTL_MAGIC;
++			break;
++
++		case DHD_GET_VERSION:
++			if (buflen < sizeof(int))
++				bcmerror = BCME_BUFTOOSHORT;
++			else
++				*(int*)buf = DHD_IOCTL_VERSION;
++			break;
++
++		case DHD_GET_VAR:
++		case DHD_SET_VAR:
++			{
++				char *arg;
++				uint arglen;
++
++				DHD_LINUX_GENERAL_LOCK(dhd_pub, flags);
++				if (DHD_BUS_CHECK_DOWN_OR_DOWN_IN_PROGRESS(dhd_pub)) {
++					/* In platforms like FC19, the FW download is done via IOCTL
++					 * and should not return error for IOCTLs fired before FW
++					 * Download is done
++					 */
++					if (dhd_fw_download_status(dhd_pub)) {
++						DHD_ERROR(("%s: returning as busstate=%d\n",
++								__FUNCTION__, dhd_pub->busstate));
++						DHD_LINUX_GENERAL_UNLOCK(dhd_pub, flags);
++						dhd_os_dhdiovar_unlock(dhd_pub);
++						return -ENODEV;
++					}
++				}
++				DHD_BUS_BUSY_SET_IN_DHD_IOVAR(dhd_pub);
++				DHD_LINUX_GENERAL_UNLOCK(dhd_pub, flags);
++
++#ifdef DHD_PCIE_RUNTIMEPM
++				dhdpcie_runtime_bus_wake(dhd_pub, TRUE, dhd_ioctl);
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++				DHD_LINUX_GENERAL_LOCK(dhd_pub, flags);
++				if (DHD_BUS_CHECK_SUSPEND_OR_SUSPEND_IN_PROGRESS(dhd_pub)) {
++					/* If Suspend/Resume is tested via pcie_suspend IOVAR
++					 * then continue to execute the IOVAR, return from here for
++					 * other IOVARs, also include pciecfgreg and devreset to go
++					 * through.
++					 */
++#ifdef DHD_EFI
++					if (bcmstricmp((char *)buf, "pcie_suspend") &&
++						bcmstricmp((char *)buf, "pciecfgreg") &&
++						bcmstricmp((char *)buf, "devreset") &&
++						bcmstricmp((char *)buf, "sdio_suspend") &&
++						bcmstricmp((char *)buf, "control_signal"))
++#else
++					if (bcmstricmp((char *)buf, "pcie_suspend") &&
++					    bcmstricmp((char *)buf, "pciecfgreg") &&
++					    bcmstricmp((char *)buf, "devreset") &&
++					    bcmstricmp((char *)buf, "sdio_suspend"))
++#endif /* DHD_EFI */
++					{
++						DHD_ERROR(("%s: bus is in suspend(%d)"
++							"or suspending(0x%x) state\n",
++							__FUNCTION__, dhd_pub->busstate,
++							dhd_pub->dhd_bus_busy_state));
++						DHD_BUS_BUSY_CLEAR_IN_DHD_IOVAR(dhd_pub);
++						dhd_os_busbusy_wake(dhd_pub);
++						DHD_LINUX_GENERAL_UNLOCK(dhd_pub, flags);
++						dhd_os_dhdiovar_unlock(dhd_pub);
++						return -ENODEV;
++					}
++				}
++				/* During devreset ioctl, we call dhdpcie_advertise_bus_cleanup,
++				 * which will wait for all the busy contexts to get over for
++				 * particular time and call ASSERT if timeout happens. As during
++				 * devreset ioctal, we made DHD_BUS_BUSY_SET_IN_DHD_IOVAR,
++				 * to avoid ASSERT, clear the IOCTL busy state. "devreset" ioctl is
++				 * not used in Production platforms but only used in FC19 setups.
++				 */
++				if (!bcmstricmp((char *)buf, "devreset")) {
++					DHD_BUS_BUSY_CLEAR_IN_DHD_IOVAR(dhd_pub);
++				}
++				DHD_LINUX_GENERAL_UNLOCK(dhd_pub, flags);
++
++				/* scan past the name to any arguments */
++				for (arg = buf, arglen = buflen; *arg && arglen; arg++, arglen--)
++					;
++
++				if (*arg) {
++					bcmerror = BCME_BUFTOOSHORT;
++					goto unlock_exit;
++				}
++
++				/* account for the NUL terminator */
++				arg++, arglen--;
++				/* call with the appropriate arguments */
++				if (ioc->cmd == DHD_GET_VAR) {
++					bcmerror = dhd_iovar_op(dhd_pub, buf, arg, arglen,
++							buf, buflen, IOV_GET);
++				} else {
++					bcmerror = dhd_iovar_op(dhd_pub, buf, NULL, 0,
++							arg, arglen, IOV_SET);
++				}
++				if (bcmerror != BCME_UNSUPPORTED) {
++					goto unlock_exit;
++				}
++
++				/* not in generic table, try protocol module */
++				if (ioc->cmd == DHD_GET_VAR) {
++					bcmerror = dhd_prot_iovar_op(dhd_pub, buf, arg,
++							arglen, buf, buflen, IOV_GET);
++				} else {
++					bcmerror = dhd_prot_iovar_op(dhd_pub, buf,
++							NULL, 0, arg, arglen, IOV_SET);
++				}
++				if (bcmerror != BCME_UNSUPPORTED) {
++					goto unlock_exit;
++				}
++
++				/* if still not found, try bus module */
++				if (ioc->cmd == DHD_GET_VAR) {
++					bcmerror = dhd_bus_iovar_op(dhd_pub, buf,
++							arg, arglen, buf, buflen, IOV_GET);
++				} else {
++					bcmerror = dhd_bus_iovar_op(dhd_pub, buf,
++							NULL, 0, arg, arglen, IOV_SET);
++				}
++				if (bcmerror != BCME_UNSUPPORTED) {
++					goto unlock_exit;
++				}
++
++#ifdef DHD_TIMESYNC
++				/* check TS module */
++				if (ioc->cmd == DHD_GET_VAR)
++					bcmerror = dhd_timesync_iovar_op(dhd_pub->ts, buf, arg,
++						arglen, buf, buflen, IOV_GET);
++				else
++					bcmerror = dhd_timesync_iovar_op(dhd_pub->ts, buf,
++						NULL, 0, arg, arglen, IOV_SET);
++#endif /* DHD_TIMESYNC */
++			}
++			goto unlock_exit;
++
++		default:
++			bcmerror = BCME_UNSUPPORTED;
++	}
++	dhd_os_dhdiovar_unlock(dhd_pub);
++	return bcmerror;
++
++unlock_exit:
++	DHD_LINUX_GENERAL_LOCK(dhd_pub, flags);
++	DHD_BUS_BUSY_CLEAR_IN_DHD_IOVAR(dhd_pub);
++	dhd_os_busbusy_wake(dhd_pub);
++	DHD_LINUX_GENERAL_UNLOCK(dhd_pub, flags);
++	dhd_os_dhdiovar_unlock(dhd_pub);
++	return bcmerror;
++}
++
++#ifdef SHOW_EVENTS
++static void
++wl_show_host_event(dhd_pub_t *dhd_pub, wl_event_msg_t *event, void *event_data,
++	void *raw_event_ptr, char *eventmask)
++{
++	uint i, status, reason;
++	bool group = FALSE, flush_txq = FALSE, link = FALSE;
++	bool host_data = FALSE; /* prints  event data after the case  when set */
++	const char *auth_str;
++	const char *event_name;
++	uchar *buf;
++	char err_msg[256], eabuf[ETHER_ADDR_STR_LEN];
++	uint event_type, flags, auth_type, datalen;
++
++	event_type = ntoh32(event->event_type);
++	flags = ntoh16(event->flags);
++	status = ntoh32(event->status);
++	reason = ntoh32(event->reason);
++	BCM_REFERENCE(reason);
++	auth_type = ntoh32(event->auth_type);
++	datalen = ntoh32(event->datalen);
++
++	/* debug dump of event messages */
++	snprintf(eabuf, sizeof(eabuf), "%02x:%02x:%02x:%02x:%02x:%02x",
++	        (uchar)event->addr.octet[0]&0xff,
++	        (uchar)event->addr.octet[1]&0xff,
++	        (uchar)event->addr.octet[2]&0xff,
++	        (uchar)event->addr.octet[3]&0xff,
++	        (uchar)event->addr.octet[4]&0xff,
++	        (uchar)event->addr.octet[5]&0xff);
++
++	event_name = bcmevent_get_name(event_type);
++	BCM_REFERENCE(event_name);
++
++	if (flags & WLC_EVENT_MSG_LINK)
++		link = TRUE;
++	if (flags & WLC_EVENT_MSG_GROUP)
++		group = TRUE;
++	if (flags & WLC_EVENT_MSG_FLUSHTXQ)
++		flush_txq = TRUE;
++
++	switch (event_type) {
++	case WLC_E_START:
++	case WLC_E_DEAUTH:
++	case WLC_E_DISASSOC:
++		DHD_EVENT(("MACEVENT: %s, MAC %s\n", event_name, eabuf));
++		break;
++
++	case WLC_E_ASSOC_IND:
++	case WLC_E_REASSOC_IND:
++
++		DHD_EVENT(("MACEVENT: %s, MAC %s\n", event_name, eabuf));
++		break;
++
++	case WLC_E_ASSOC:
++	case WLC_E_REASSOC:
++		if (status == WLC_E_STATUS_SUCCESS) {
++			DHD_EVENT(("MACEVENT: %s, MAC %s, SUCCESS\n", event_name, eabuf));
++		} else if (status == WLC_E_STATUS_TIMEOUT) {
++			DHD_EVENT(("MACEVENT: %s, MAC %s, TIMEOUT\n", event_name, eabuf));
++		} else if (status == WLC_E_STATUS_FAIL) {
++			DHD_EVENT(("MACEVENT: %s, MAC %s, FAILURE, reason %d\n",
++			       event_name, eabuf, (int)reason));
++		} else {
++			DHD_EVENT(("MACEVENT: %s, MAC %s, unexpected status %d\n",
++			       event_name, eabuf, (int)status));
++		}
++		break;
++
++	case WLC_E_DEAUTH_IND:
++	case WLC_E_DISASSOC_IND:
++		DHD_EVENT(("MACEVENT: %s, MAC %s, reason %d\n", event_name, eabuf, (int)reason));
++		break;
++
++	case WLC_E_AUTH:
++	case WLC_E_AUTH_IND:
++		if (auth_type == DOT11_OPEN_SYSTEM)
++			auth_str = "Open System";
++		else if (auth_type == DOT11_SHARED_KEY)
++			auth_str = "Shared Key";
++		else {
++			snprintf(err_msg, sizeof(err_msg), "AUTH unknown: %d", (int)auth_type);
++			auth_str = err_msg;
++		}
++
++	if (event_type == WLC_E_AUTH_IND) {
++			DHD_EVENT(("MACEVENT: %s, MAC %s, %s\n", event_name, eabuf, auth_str));
++		} else if (status == WLC_E_STATUS_SUCCESS) {
++			DHD_EVENT(("MACEVENT: %s, MAC %s, %s, SUCCESS\n",
++				event_name, eabuf, auth_str));
++		} else if (status == WLC_E_STATUS_TIMEOUT) {
++			DHD_EVENT(("MACEVENT: %s, MAC %s, %s, TIMEOUT\n",
++				event_name, eabuf, auth_str));
++		} else if (status == WLC_E_STATUS_FAIL) {
++			DHD_EVENT(("MACEVENT: %s, MAC %s, %s, FAILURE, reason %d\n",
++			       event_name, eabuf, auth_str, (int)reason));
++		}
++		BCM_REFERENCE(auth_str);
++
++		break;
++
++	case WLC_E_JOIN:
++	case WLC_E_ROAM:
++	case WLC_E_SET_SSID:
++		if (status == WLC_E_STATUS_SUCCESS) {
++			DHD_EVENT(("MACEVENT: %s, MAC %s\n", event_name, eabuf));
++#ifdef REPORT_FATAL_TIMEOUTS
++			dhd_clear_join_error(dhd_pub, WLC_SSID_MASK);
++#endif /* REPORT_FATAL_TIMEOUTS */
++		} else {
++#ifdef REPORT_FATAL_TIMEOUTS
++			dhd_set_join_error(dhd_pub, WLC_SSID_MASK);
++#endif /* REPORT_FATAL_TIMEOUTS */
++			if (status == WLC_E_STATUS_FAIL) {
++				DHD_EVENT(("MACEVENT: %s, failed\n", event_name));
++			} else if (status == WLC_E_STATUS_NO_NETWORKS) {
++				DHD_EVENT(("MACEVENT: %s, no networks found\n", event_name));
++			} else {
++				DHD_EVENT(("MACEVENT: %s, unexpected status %d\n",
++					event_name, (int)status));
++			}
++		}
++		break;
++
++	case WLC_E_BEACON_RX:
++		if (status == WLC_E_STATUS_SUCCESS) {
++			DHD_EVENT(("MACEVENT: %s, SUCCESS\n", event_name));
++		} else if (status == WLC_E_STATUS_FAIL) {
++			DHD_EVENT(("MACEVENT: %s, FAIL\n", event_name));
++		} else {
++			DHD_EVENT(("MACEVENT: %s, status %d\n", event_name, status));
++		}
++		break;
++
++	case WLC_E_LINK:
++		DHD_EVENT(("MACEVENT: %s %s\n", event_name, link?"UP":"DOWN"));
++		BCM_REFERENCE(link);
++		break;
++
++	case WLC_E_MIC_ERROR:
++		DHD_EVENT(("MACEVENT: %s, MAC %s, Group %d, Flush %d\n",
++		       event_name, eabuf, group, flush_txq));
++		BCM_REFERENCE(group);
++		BCM_REFERENCE(flush_txq);
++		break;
++
++	case WLC_E_ICV_ERROR:
++	case WLC_E_UNICAST_DECODE_ERROR:
++	case WLC_E_MULTICAST_DECODE_ERROR:
++		DHD_EVENT(("MACEVENT: %s, MAC %s\n",
++		       event_name, eabuf));
++		break;
++
++	case WLC_E_TXFAIL:
++		DHD_EVENT(("MACEVENT: %s, RA %s status %d\n", event_name, eabuf, status));
++		break;
++
++	case WLC_E_ASSOC_REQ_IE:
++	case WLC_E_ASSOC_RESP_IE:
++	case WLC_E_PMKID_CACHE:
++		DHD_EVENT(("MACEVENT: %s\n", event_name));
++		break;
++
++	case WLC_E_SCAN_COMPLETE:
++		DHD_EVENT(("MACEVENT: %s\n", event_name));
++#ifdef REPORT_FATAL_TIMEOUTS
++		dhd_stop_scan_timer(dhd_pub);
++#endif /* REPORT_FATAL_TIMEOUTS */
++		break;
++	case WLC_E_RSSI_LQM:
++	case WLC_E_PFN_NET_FOUND:
++	case WLC_E_PFN_NET_LOST:
++	case WLC_E_PFN_SCAN_COMPLETE:
++	case WLC_E_PFN_SCAN_NONE:
++	case WLC_E_PFN_SCAN_ALLGONE:
++	case WLC_E_PFN_GSCAN_FULL_RESULT:
++	case WLC_E_PFN_SSID_EXT:
++		DHD_EVENT(("PNOEVENT: %s\n", event_name));
++		break;
++
++	case WLC_E_PSK_SUP:
++	case WLC_E_PRUNE:
++		DHD_EVENT(("MACEVENT: %s, status %d, reason %d\n",
++		           event_name, (int)status, (int)reason));
++#ifdef REPORT_FATAL_TIMEOUTS
++		if ((status == WLC_E_STATUS_SUCCESS || status == WLC_E_STATUS_UNSOLICITED) &&
++				(reason == WLC_E_SUP_OTHER)) {
++			dhd_clear_join_error(dhd_pub, WLC_WPA_MASK);
++		} else {
++			dhd_set_join_error(dhd_pub, WLC_WPA_MASK);
++		}
++#endif /* REPORT_FATAL_TIMEOUTS */
++		break;
++
++#ifdef WIFI_ACT_FRAME
++	case WLC_E_ACTION_FRAME:
++		DHD_TRACE(("MACEVENT: %s Bssid %s\n", event_name, eabuf));
++		break;
++#endif /* WIFI_ACT_FRAME */
++
++#ifdef SHOW_LOGTRACE
++	case WLC_E_TRACE:
++		DHD_EVENT(("MACEVENT: %s Logtrace\n", event_name));
++		dhd_dbg_trace_evnt_handler(dhd_pub, event_data, raw_event_ptr, datalen);
++		break;
++#endif /* SHOW_LOGTRACE */
++
++	case WLC_E_RSSI:
++		DHD_EVENT(("MACEVENT: %s %d\n", event_name, ntoh32(*((int *)event_data))));
++		break;
++
++	case WLC_E_SERVICE_FOUND:
++	case WLC_E_P2PO_ADD_DEVICE:
++	case WLC_E_P2PO_DEL_DEVICE:
++		DHD_EVENT(("MACEVENT: %s, MAC %s\n", event_name, eabuf));
++		break;
++
++#ifdef BT_WIFI_HANDOBER
++	case WLC_E_BT_WIFI_HANDOVER_REQ:
++		DHD_EVENT(("MACEVENT: %s, MAC %s\n", event_name, eabuf));
++		break;
++#endif
++
++	case WLC_E_CCA_CHAN_QUAL:
++		if (datalen) {
++			buf = (uchar *) event_data;
++			DHD_EVENT(("MACEVENT: %s %d, MAC %s, status %d, reason %d, auth %d, "
++				"channel 0x%02x \n", event_name, event_type, eabuf, (int)status,
++				(int)reason, (int)auth_type, *(buf + 4)));
++		}
++		break;
++	case WLC_E_ESCAN_RESULT:
++	{
++		DHD_EVENT(("MACEVENT: %s %d, MAC %s, status %d \n",
++		       event_name, event_type, eabuf, (int)status));
++	}
++		break;
++	case WLC_E_PSK_AUTH:
++		DHD_EVENT(("MACEVENT: %s, RA %s status %d Reason:%d\n",
++		event_name, eabuf, status, reason));
++		break;
++	case WLC_E_IF:
++	{
++		struct wl_event_data_if *ifevent = (struct wl_event_data_if *)event_data;
++		BCM_REFERENCE(ifevent);
++
++		DHD_EVENT(("MACEVENT: %s, opcode:0x%d  ifidx:%d\n",
++		event_name, ifevent->opcode, ifevent->ifidx));
++		break;
++	}
++
++#ifdef SHOW_LOGTRACE
++	case WLC_E_MSCH:
++	{
++		wl_mschdbg_event_handler(dhd_pub, raw_event_ptr, reason, event_data, datalen);
++		break;
++	}
++#endif /* SHOW_LOGTRACE */
++
++	default:
++		DHD_EVENT(("MACEVENT: %s %d, MAC %s, status %d, reason %d, auth %d\n",
++		       event_name, event_type, eabuf, (int)status, (int)reason,
++		       (int)auth_type));
++		break;
++	}
++
++	/* show any appended data if message level is set to bytes or host_data is set */
++	if ((DHD_BYTES_ON() || (host_data == TRUE)) && DHD_EVENT_ON() && datalen) {
++		buf = (uchar *) event_data;
++		BCM_REFERENCE(buf);
++		DHD_EVENT((" data (%d) : ", datalen));
++		for (i = 0; i < datalen; i++) {
++			DHD_EVENT((" 0x%02x ", buf[i]));
++		}
++		DHD_EVENT(("\n"));
++	}
++}
++#endif /* SHOW_EVENTS */
++
++#ifdef DNGL_EVENT_SUPPORT
++/* Check whether packet is a BRCM dngl event pkt. If it is, process event data. */
++int
++dngl_host_event(dhd_pub_t *dhdp, void *pktdata, bcm_dngl_event_msg_t *dngl_event, size_t pktlen)
++{
++	bcm_dngl_event_t *pvt_data = (bcm_dngl_event_t *)pktdata;
++
++	dngl_host_event_process(dhdp, pvt_data, dngl_event, pktlen);
++	return BCME_OK;
++}
++
++void
++dngl_host_event_process(dhd_pub_t *dhdp, bcm_dngl_event_t *event,
++	bcm_dngl_event_msg_t *dngl_event, size_t pktlen)
++{
++	uint8 *p = (uint8 *)(event + 1);
++	uint16 type = ntoh16_ua((void *)&dngl_event->event_type);
++	uint16 datalen = ntoh16_ua((void *)&dngl_event->datalen);
++	uint16 version = ntoh16_ua((void *)&dngl_event->version);
++
++	DHD_EVENT(("VERSION:%d, EVENT TYPE:%d, DATALEN:%d\n", version, type, datalen));
++	if (datalen > (pktlen - sizeof(bcm_dngl_event_t) + ETHER_TYPE_LEN)) {
++		return;
++	}
++	if (version != BCM_DNGL_EVENT_MSG_VERSION) {
++		DHD_ERROR(("%s:version mismatch:%d:%d\n", __FUNCTION__,
++			version, BCM_DNGL_EVENT_MSG_VERSION));
++		return;
++	}
++	switch (type) {
++	   case DNGL_E_SOCRAM_IND:
++		{
++		   bcm_dngl_socramind_t *socramind_ptr = (bcm_dngl_socramind_t *)p;
++		   uint16 tag = ltoh32(socramind_ptr->tag);
++		   uint16 taglen = ltoh32(socramind_ptr->length);
++		   p = (uint8 *)socramind_ptr->value;
++		   DHD_EVENT(("Tag:%d Len:%d Datalen:%d\n", tag, taglen, datalen));
++		   switch (tag) {
++			case SOCRAM_IND_ASSERT_TAG:
++			    {
++				/*
++				* The payload consists of -
++				* null terminated function name padded till 32 bit boundary +
++				* Line number - (32 bits)
++				* Caller address (32 bits)
++				*/
++				char *fnname = (char *)p;
++				if (datalen < (ROUNDUP(strlen(fnname) + 1, sizeof(uint32)) +
++					sizeof(uint32) * 2)) {
++					DHD_ERROR(("Wrong length:%d\n", datalen));
++					return;
++				}
++				DHD_EVENT(("ASSRT Function:%s ", p));
++				p += ROUNDUP(strlen(p) + 1, sizeof(uint32));
++				DHD_EVENT(("Line:%d ", *(uint32 *)p));
++				p += sizeof(uint32);
++				DHD_EVENT(("Caller Addr:0x%x\n", *(uint32 *)p));
++				break;
++			    }
++			case SOCRAM_IND_TAG_HEALTH_CHECK:
++			   {
++				bcm_dngl_healthcheck_t *dngl_hc = (bcm_dngl_healthcheck_t *)p;
++				DHD_EVENT(("SOCRAM_IND_HEALTHCHECK_TAG:%d Len:%d\n",
++				ltoh32(dngl_hc->top_module_tag), ltoh32(dngl_hc->top_module_len)));
++				if (DHD_EVENT_ON()) {
++					prhex("HEALTHCHECK", p, ltoh32(dngl_hc->top_module_len));
++				}
++				p = (uint8 *)dngl_hc->value;
++
++				switch (ltoh32(dngl_hc->top_module_tag)) {
++					case HEALTH_CHECK_TOP_LEVEL_MODULE_PCIEDEV_RTE:
++					   {
++						bcm_dngl_pcie_hc_t *pcie_hc;
++						pcie_hc = (bcm_dngl_pcie_hc_t *)p;
++						BCM_REFERENCE(pcie_hc);
++						if (ltoh32(dngl_hc->top_module_len) <
++								sizeof(bcm_dngl_pcie_hc_t)) {
++							DHD_ERROR(("Wrong length:%d\n",
++								ltoh32(dngl_hc->top_module_len)));
++							return;
++						}
++						DHD_EVENT(("%d:PCIE HC error:%d flag:0x%x,"
++							" control:0x%x\n",
++							ltoh32(pcie_hc->version),
++							ltoh32(pcie_hc->pcie_err_ind_type),
++							ltoh32(pcie_hc->pcie_flag),
++							ltoh32(pcie_hc->pcie_control_reg)));
++						break;
++					   }
++					default:
++						DHD_ERROR(("%s:Unknown module TAG:%d\n",
++						  __FUNCTION__,
++						  ltoh32(dngl_hc->top_module_tag)));
++						break;
++				}
++				break;
++			   }
++			default:
++			   DHD_ERROR(("%s:Unknown TAG", __FUNCTION__));
++			   if (p && DHD_EVENT_ON()) {
++				   prhex("SOCRAMIND", p, taglen);
++			   }
++			   break;
++		   }
++		   break;
++		}
++	   default:
++		DHD_ERROR(("%s:Unknown DNGL Event Type:%d", __FUNCTION__, type));
++		if (p && DHD_EVENT_ON()) {
++			prhex("SOCRAMIND", p, datalen);
++		}
++		break;
++	}
++#ifdef DHD_FW_COREDUMP
++	dhdp->memdump_type = DUMP_TYPE_DONGLE_HOST_EVENT;
++#endif /* DHD_FW_COREDUMP */
++#ifndef BCMDBUS
++	if (dhd_socram_dump(dhdp->bus)) {
++		DHD_ERROR(("%s: socram dump failed\n", __FUNCTION__));
++	} else {
++		/* Notify framework */
++		dhd_dbg_send_urgent_evt(dhdp, p, datalen);
++	}
++#endif /* !BCMDBUS */
++}
++#endif /* DNGL_EVENT_SUPPORT */
++
++/* Stub for now. Will become real function as soon as shim
++ * is being integrated to Android, Linux etc.
++ */
++int
++wl_event_process_default(wl_event_msg_t *event, struct wl_evt_pport *evt_pport)
++{
++	return BCME_OK;
++}
++
++int
++wl_event_process(dhd_pub_t *dhd_pub, int *ifidx, void *pktdata,
++	uint pktlen, void **data_ptr, void *raw_event)
++{
++	wl_evt_pport_t evt_pport;
++	wl_event_msg_t event;
++	bcm_event_msg_u_t evu;
++	int ret;
++
++	/* make sure it is a BRCM event pkt and record event data */
++	ret = wl_host_event_get_data(pktdata, pktlen, &evu);
++	if (ret != BCME_OK) {
++		return ret;
++	}
++
++	memcpy(&event, &evu.event, sizeof(wl_event_msg_t));
++
++	/* convert event from network order to host order */
++	wl_event_to_host_order(&event);
++
++	/* record event params to evt_pport */
++	evt_pport.dhd_pub = dhd_pub;
++	evt_pport.ifidx = ifidx;
++	evt_pport.pktdata = pktdata;
++	evt_pport.data_ptr = data_ptr;
++	evt_pport.raw_event = raw_event;
++	evt_pport.data_len = pktlen;
++
++#if defined(WL_WLC_SHIM) && defined(WL_WLC_SHIM_EVENTS)
++	{
++		struct wl_shim_node *shim = dhd_pub_shim(dhd_pub);
++		if (shim) {
++			ret = wl_shim_event_process(shim, &event, &evt_pport);
++		} else {
++			/* events can come even before shim is initialized
++			 (when waiting for "wlc_ver" response)
++			 * handle them in a non-shim way.
++			 */
++			DHD_ERROR(("%s: Events coming before shim initialization!\n",
++				__FUNCTION__));
++			ret = wl_event_process_default(&event, &evt_pport);
++		}
++	}
++#else
++	ret = wl_event_process_default(&event, &evt_pport);
++#endif /* WL_WLC_SHIM && WL_WLC_SHIM_EVENTS */
++
++	return ret;
++}
++
++/* Check whether packet is a BRCM event pkt. If it is, record event data. */
++int
++wl_host_event_get_data(void *pktdata, uint pktlen, bcm_event_msg_u_t *evu)
++{
++	int ret;
++
++	ret = is_wlc_event_frame(pktdata, pktlen, 0, evu);
++	if (ret != BCME_OK) {
++		DHD_ERROR(("%s: Invalid event frame, err = %d\n",
++			__FUNCTION__, ret));
++	}
++
++	return ret;
++}
++
++int
++wl_process_host_event(dhd_pub_t *dhd_pub, int *ifidx, void *pktdata, uint pktlen,
++	wl_event_msg_t *event, void **data_ptr, void *raw_event)
++{
++	bcm_event_t *pvt_data = (bcm_event_t *)pktdata;
++	bcm_event_msg_u_t evu;
++	uint8 *event_data;
++	uint32 type, status, datalen;
++	uint16 flags;
++	uint evlen;
++	int ret;
++	uint16 usr_subtype;
++	char macstr[ETHER_ADDR_STR_LEN];
++
++	BCM_REFERENCE(macstr);
++
++	ret = wl_host_event_get_data(pktdata, pktlen, &evu);
++	if (ret != BCME_OK) {
++		return ret;
++	}
++
++	usr_subtype = ntoh16_ua((void *)&pvt_data->bcm_hdr.usr_subtype);
++	switch (usr_subtype) {
++	case BCMILCP_BCM_SUBTYPE_EVENT:
++		memcpy(event, &evu.event, sizeof(wl_event_msg_t));
++		*data_ptr = &pvt_data[1];
++		break;
++	case BCMILCP_BCM_SUBTYPE_DNGLEVENT:
++#ifdef DNGL_EVENT_SUPPORT
++		/* If it is a DNGL event process it first */
++		if (dngl_host_event(dhd_pub, pktdata, &evu.dngl_event, pktlen) == BCME_OK) {
++			/*
++			 * Return error purposely to prevent DNGL event being processed
++			 * as BRCM event
++			 */
++			return BCME_ERROR;
++		}
++#endif /* DNGL_EVENT_SUPPORT */
++		return BCME_NOTFOUND;
++	default:
++		return BCME_NOTFOUND;
++	}
++
++	/* start wl_event_msg process */
++	event_data = *data_ptr;
++	type = ntoh32_ua((void *)&event->event_type);
++	flags = ntoh16_ua((void *)&event->flags);
++	status = ntoh32_ua((void *)&event->status);
++	datalen = ntoh32_ua((void *)&event->datalen);
++	evlen = datalen + sizeof(bcm_event_t);
++
++	switch (type) {
++#ifdef PROP_TXSTATUS
++	case WLC_E_FIFO_CREDIT_MAP:
++		dhd_wlfc_enable(dhd_pub);
++		dhd_wlfc_FIFOcreditmap_event(dhd_pub, event_data);
++		WLFC_DBGMESG(("WLC_E_FIFO_CREDIT_MAP:(AC0,AC1,AC2,AC3),(BC_MC),(OTHER): "
++			"(%d,%d,%d,%d),(%d),(%d)\n", event_data[0], event_data[1],
++			event_data[2],
++			event_data[3], event_data[4], event_data[5]));
++		break;
++
++	case WLC_E_BCMC_CREDIT_SUPPORT:
++		dhd_wlfc_BCMCCredit_support_event(dhd_pub);
++		break;
++#ifdef LIMIT_BORROW
++	case WLC_E_ALLOW_CREDIT_BORROW:
++		dhd_wlfc_disable_credit_borrow_event(dhd_pub, event_data);
++		break;
++#endif /* LIMIT_BORROW */
++#endif /* PROP_TXSTATUS */
++
++
++	case WLC_E_ULP:
++#ifdef DHD_ULP
++	{
++		wl_ulp_event_t *ulp_evt = (wl_ulp_event_t *)event_data;
++
++		/* Flush and disable console messages */
++		if (ulp_evt->ulp_dongle_action == WL_ULP_DISABLE_CONSOLE) {
++#ifdef DHD_ULP_NOT_USED
++			dhd_bus_ulp_disable_console(dhd_pub);
++#endif /* DHD_ULP_NOT_USED */
++		}
++		if (ulp_evt->ulp_dongle_action == WL_ULP_UCODE_DOWNLOAD) {
++			dhd_bus_ucode_download(dhd_pub->bus);
++		}
++	}
++#endif /* DHD_ULP */
++		break;
++	case WLC_E_TDLS_PEER_EVENT:
++#if defined(WLTDLS) && defined(PCIE_FULL_DONGLE)
++		{
++			dhd_tdls_event_handler(dhd_pub, event);
++		}
++#endif
++		break;
++
++	case WLC_E_IF:
++		{
++		struct wl_event_data_if *ifevent = (struct wl_event_data_if *)event_data;
++
++		/* Ignore the event if NOIF is set */
++		if (ifevent->reserved & WLC_E_IF_FLAGS_BSSCFG_NOIF) {
++			DHD_ERROR(("WLC_E_IF: NO_IF set, event Ignored\r\n"));
++			return (BCME_UNSUPPORTED);
++		}
++#ifdef PCIE_FULL_DONGLE
++		dhd_update_interface_flow_info(dhd_pub, ifevent->ifidx,
++			ifevent->opcode, ifevent->role);
++#endif
++#ifdef PROP_TXSTATUS
++		{
++			uint8* ea = pvt_data->eth.ether_dhost;
++			WLFC_DBGMESG(("WLC_E_IF: idx:%d, action:%s, iftype:%s, "
++						  "[%02x:%02x:%02x:%02x:%02x:%02x]\n",
++						  ifevent->ifidx,
++						  ((ifevent->opcode == WLC_E_IF_ADD) ? "ADD":"DEL"),
++						  ((ifevent->role == 0) ? "STA":"AP "),
++						  ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]));
++			(void)ea;
++
++			if (ifevent->opcode == WLC_E_IF_CHANGE)
++				dhd_wlfc_interface_event(dhd_pub,
++					eWLFC_MAC_ENTRY_ACTION_UPDATE,
++					ifevent->ifidx, ifevent->role, ea);
++			else
++				dhd_wlfc_interface_event(dhd_pub,
++					((ifevent->opcode == WLC_E_IF_ADD) ?
++					eWLFC_MAC_ENTRY_ACTION_ADD : eWLFC_MAC_ENTRY_ACTION_DEL),
++					ifevent->ifidx, ifevent->role, ea);
++
++			/* dhd already has created an interface by default, for 0 */
++			if (ifevent->ifidx == 0)
++				break;
++		}
++#endif /* PROP_TXSTATUS */
++
++		if (ifevent->ifidx > 0 && ifevent->ifidx < DHD_MAX_IFS) {
++			if (ifevent->opcode == WLC_E_IF_ADD) {
++				if (dhd_event_ifadd(dhd_pub->info, ifevent, event->ifname,
++					event->addr.octet)) {
++
++					DHD_ERROR(("%s: dhd_event_ifadd failed ifidx: %d  %s\n",
++						__FUNCTION__, ifevent->ifidx, event->ifname));
++					return (BCME_ERROR);
++				}
++			} else if (ifevent->opcode == WLC_E_IF_DEL) {
++#ifdef PCIE_FULL_DONGLE
++				/* Delete flowrings unconditionally for i/f delete */
++				dhd_flow_rings_delete(dhd_pub, (uint8)dhd_ifname2idx(dhd_pub->info,
++					event->ifname));
++#endif /* PCIE_FULL_DONGLE */
++				dhd_event_ifdel(dhd_pub->info, ifevent, event->ifname,
++					event->addr.octet);
++				/* Return ifidx (for vitual i/f, it will be > 0)
++				 * so that no other operations on deleted interface
++				 * are carried out
++				 */
++				ret = ifevent->ifidx;
++				goto exit;
++			} else if (ifevent->opcode == WLC_E_IF_CHANGE) {
++#ifdef WL_CFG80211
++				dhd_event_ifchange(dhd_pub->info, ifevent, event->ifname,
++					event->addr.octet);
++#endif /* WL_CFG80211 */
++			}
++		} else {
++#if !defined(PROP_TXSTATUS) && !defined(PCIE_FULL_DONGLE) && defined(WL_CFG80211)
++			DHD_INFO(("%s: Invalid ifidx %d for %s\n",
++			   __FUNCTION__, ifevent->ifidx, event->ifname));
++#endif /* !PROP_TXSTATUS && !PCIE_FULL_DONGLE && WL_CFG80211 */
++		}
++			/* send up the if event: btamp user needs it */
++			*ifidx = dhd_ifname2idx(dhd_pub->info, event->ifname);
++			/* push up to external supp/auth */
++			dhd_event(dhd_pub->info, (char *)pvt_data, evlen, *ifidx);
++		break;
++	}
++
++#ifdef WLMEDIA_HTSF
++	case WLC_E_HTSFSYNC:
++		htsf_update(dhd_pub->info, event_data);
++		break;
++#endif /* WLMEDIA_HTSF */
++	case WLC_E_NDIS_LINK:
++		break;
++	case WLC_E_PFN_NET_FOUND:
++	case WLC_E_PFN_SCAN_ALLGONE: /* share with WLC_E_PFN_BSSID_NET_LOST */
++	case WLC_E_PFN_NET_LOST:
++		break;
++#if defined(PNO_SUPPORT)
++	case WLC_E_PFN_BSSID_NET_FOUND:
++	case WLC_E_PFN_BEST_BATCHING:
++		dhd_pno_event_handler(dhd_pub, event, (void *)event_data);
++		break;
++#endif 
++#if defined(RTT_SUPPORT)
++	case WLC_E_PROXD:
++		dhd_rtt_event_handler(dhd_pub, event, (void *)event_data);
++		break;
++#endif /* RTT_SUPPORT */
++		/* These are what external supplicant/authenticator wants */
++	case WLC_E_ASSOC_IND:
++	case WLC_E_AUTH_IND:
++	case WLC_E_REASSOC_IND:
++		dhd_findadd_sta(dhd_pub,
++			dhd_ifname2idx(dhd_pub->info, event->ifname),
++			&event->addr.octet);
++		break;
++#ifndef BCMDBUS
++#if defined(DHD_FW_COREDUMP)
++	case WLC_E_PSM_WATCHDOG:
++		DHD_ERROR(("%s: WLC_E_PSM_WATCHDOG event received : \n", __FUNCTION__));
++		if (dhd_socram_dump(dhd_pub->bus) != BCME_OK) {
++			DHD_ERROR(("%s: socram dump ERROR : \n", __FUNCTION__));
++		}
++	break;
++#endif
++#endif /* !BCMDBUS */
++#ifdef DHD_WMF
++	case WLC_E_PSTA_PRIMARY_INTF_IND:
++		dhd_update_psta_interface_for_sta(dhd_pub, event->ifname,
++			(void *)(event->addr.octet), (void*) event_data);
++		break;
++#endif
++	case WLC_E_LINK:
++#ifdef PCIE_FULL_DONGLE
++		DHD_EVENT(("%s: Link event %d, flags %x, status %x\n",
++			__FUNCTION__, type, flags, status));
++		if (dhd_update_interface_link_status(dhd_pub, (uint8)dhd_ifname2idx(dhd_pub->info,
++			event->ifname), (uint8)flags) != BCME_OK) {
++			DHD_ERROR(("%s: dhd_update_interface_link_status Failed.\n",
++				__FUNCTION__));
++			break;
++		}
++		if (!flags) {
++			DHD_ERROR(("%s: Deleting all STA from assoc list and flowrings.\n",
++				__FUNCTION__));
++			/* Delete all sta and flowrings */
++			dhd_del_all_sta(dhd_pub, dhd_ifname2idx(dhd_pub->info, event->ifname));
++			dhd_flow_rings_delete(dhd_pub, (uint8)dhd_ifname2idx(dhd_pub->info,
++				event->ifname));
++		}
++		/* fall through */
++#endif /* PCIE_FULL_DONGLE */
++	case WLC_E_DEAUTH:
++	case WLC_E_DEAUTH_IND:
++	case WLC_E_DISASSOC:
++	case WLC_E_DISASSOC_IND:
++#ifdef PCIE_FULL_DONGLE
++		if (type != WLC_E_LINK) {
++			uint8 ifindex = (uint8)dhd_ifname2idx(dhd_pub->info, event->ifname);
++			uint8 role = dhd_flow_rings_ifindex2role(dhd_pub, ifindex);
++			uint8 del_sta = TRUE;
++#ifdef WL_CFG80211
++			if (role == WLC_E_IF_ROLE_STA &&
++				!wl_cfg80211_is_roam_offload(dhd_idx2net(dhd_pub, ifindex)) &&
++					!wl_cfg80211_is_event_from_connected_bssid(
++						dhd_idx2net(dhd_pub, ifindex), event, *ifidx)) {
++				del_sta = FALSE;
++			}
++#endif /* WL_CFG80211 */
++			DHD_EVENT(("%s: Link event %d, flags %x, status %x, role %d, del_sta %d\n",
++				__FUNCTION__, type, flags, status, role, del_sta));
++
++			if (del_sta) {
++				DHD_MAC_TO_STR((event->addr.octet), macstr);
++				DHD_EVENT(("%s: Deleting STA %s\n", __FUNCTION__, macstr));
++
++				dhd_del_sta(dhd_pub, dhd_ifname2idx(dhd_pub->info,
++					event->ifname), &event->addr.octet);
++				/* Delete all flowrings for STA and P2P Client */
++				if (role == WLC_E_IF_ROLE_STA || role == WLC_E_IF_ROLE_P2P_CLIENT) {
++					dhd_flow_rings_delete(dhd_pub, ifindex);
++				} else {
++					dhd_flow_rings_delete_for_peer(dhd_pub, ifindex,
++						(char *)&event->addr.octet[0]);
++				}
++			}
++		}
++#endif /* PCIE_FULL_DONGLE */
++		/* fall through */
++
++	default:
++		*ifidx = dhd_ifname2idx(dhd_pub->info, event->ifname);
++#ifdef DHD_UPDATE_INTF_MAC
++		if ((WLC_E_LINK==type)&&(WLC_EVENT_MSG_LINK&flags)) {
++			dhd_event_ifchange(dhd_pub->info,
++			(struct wl_event_data_if *)event,
++			event->ifname,
++			event->addr.octet);
++		}
++#endif /* DHD_UPDATE_INTF_MAC */
++		/* push up to external supp/auth */
++		dhd_event(dhd_pub->info, (char *)pvt_data, evlen, *ifidx);
++		DHD_TRACE(("%s: MAC event %d, flags %x, status %x\n",
++			__FUNCTION__, type, flags, status));
++		BCM_REFERENCE(flags);
++		BCM_REFERENCE(status);
++
++		break;
++	}
++#if defined(STBAP)
++	/* For routers, EAPD will be working on these events.
++	 * Overwrite interface name to that event is pushed
++	 * to host with its registered interface name
++	 */
++	memcpy(pvt_data->event.ifname, dhd_ifname(dhd_pub, *ifidx), IFNAMSIZ);
++#endif
++
++exit:
++
++#ifdef SHOW_EVENTS
++	if (DHD_FWLOG_ON() || DHD_EVENT_ON()) {
++		wl_show_host_event(dhd_pub, event,
++			(void *)event_data, raw_event, dhd_pub->enable_log);
++	}
++#endif /* SHOW_EVENTS */
++
++	return ret;
++}
++
++int
++wl_host_event(dhd_pub_t *dhd_pub, int *ifidx, void *pktdata, uint pktlen,
++	wl_event_msg_t *event, void **data_ptr, void *raw_event)
++{
++	return wl_process_host_event(dhd_pub, ifidx, pktdata, pktlen, event, data_ptr,
++			raw_event);
++}
++
++void
++dhd_print_buf(void *pbuf, int len, int bytes_per_line)
++{
++#ifdef DHD_DEBUG
++	int i, j = 0;
++	unsigned char *buf = pbuf;
++
++	if (bytes_per_line == 0) {
++		bytes_per_line = len;
++	}
++
++	for (i = 0; i < len; i++) {
++		printf("%2.2x", *buf++);
++		j++;
++		if (j == bytes_per_line) {
++			printf("\n");
++			j = 0;
++		} else {
++			printf(":");
++		}
++	}
++	printf("\n");
++#endif /* DHD_DEBUG */
++}
++#ifndef strtoul
++#define strtoul(nptr, endptr, base) bcm_strtoul((nptr), (endptr), (base))
++#endif
++
++/* Convert user's input in hex pattern to byte-size mask */
++int
++wl_pattern_atoh(char *src, char *dst)
++{
++	int i;
++	if (strncmp(src, "0x", 2) != 0 &&
++	    strncmp(src, "0X", 2) != 0) {
++		DHD_ERROR(("Mask invalid format. Needs to start with 0x\n"));
++		return -1;
++	}
++	src = src + 2; /* Skip past 0x */
++	if (strlen(src) % 2 != 0) {
++		DHD_ERROR(("Mask invalid format. Needs to be of even length\n"));
++		return -1;
++	}
++	for (i = 0; *src != '\0'; i++) {
++		char num[3];
++		bcm_strncpy_s(num, sizeof(num), src, 2);
++		num[2] = '\0';
++		dst[i] = (uint8)strtoul(num, NULL, 16);
++		src += 2;
++	}
++	return i;
++}
++
++#ifdef PKT_FILTER_SUPPORT
++void
++dhd_pktfilter_offload_enable(dhd_pub_t * dhd, char *arg, int enable, int master_mode)
++{
++	char				*argv[8];
++	int					i = 0;
++	const char			*str;
++	int					buf_len;
++	int					str_len;
++	char				*arg_save = 0, *arg_org = 0;
++	int					rc;
++	char				buf[32] = {0};
++	wl_pkt_filter_enable_t	enable_parm;
++	wl_pkt_filter_enable_t	* pkt_filterp;
++
++	if (!arg)
++		return;
++
++	if (!(arg_save = MALLOC(dhd->osh, strlen(arg) + 1))) {
++		DHD_ERROR(("%s: malloc failed\n", __FUNCTION__));
++		goto fail;
++	}
++	arg_org = arg_save;
++	memcpy(arg_save, arg, strlen(arg) + 1);
++
++	argv[i] = bcmstrtok(&arg_save, " ", 0);
++
++	i = 0;
++	if (argv[i] == NULL) {
++		DHD_ERROR(("No args provided\n"));
++		goto fail;
++	}
++
++	str = "pkt_filter_enable";
++	str_len = strlen(str);
++	bcm_strncpy_s(buf, sizeof(buf) - 1, str, sizeof(buf) - 1);
++	buf[ sizeof(buf) - 1 ] = '\0';
++	buf_len = str_len + 1;
++
++	pkt_filterp = (wl_pkt_filter_enable_t *)(buf + str_len + 1);
++
++	/* Parse packet filter id. */
++	enable_parm.id = htod32(strtoul(argv[i], NULL, 0));
++	if (dhd_conf_del_pkt_filter(dhd, enable_parm.id))
++		goto fail;
++
++	/* Parse enable/disable value. */
++	enable_parm.enable = htod32(enable);
++
++	buf_len += sizeof(enable_parm);
++	memcpy((char *)pkt_filterp,
++	       &enable_parm,
++	       sizeof(enable_parm));
++
++	/* Enable/disable the specified filter. */
++	rc = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, buf, buf_len, TRUE, 0);
++	rc = rc >= 0 ? 0 : rc;
++	if (rc)
++		DHD_ERROR(("%s: failed to %s pktfilter %s, retcode = %d\n",
++		__FUNCTION__, enable?"enable":"disable", arg, rc));
++	else
++		DHD_TRACE(("%s: successfully %s pktfilter %s\n",
++		__FUNCTION__, enable?"enable":"disable", arg));
++
++	/* Contorl the master mode */
++	rc = dhd_wl_ioctl_set_intiovar(dhd, "pkt_filter_mode",
++		master_mode, WLC_SET_VAR, TRUE, 0);
++	rc = rc >= 0 ? 0 : rc;
++	if (rc)
++		DHD_TRACE(("%s: failed to set pkt_filter_mode %d, retcode = %d\n",
++			__FUNCTION__, master_mode, rc));
++
++fail:
++	if (arg_org)
++		MFREE(dhd->osh, arg_org, strlen(arg) + 1);
++}
++
++/* Packet filter section: extended filters have named offsets, add table here */
++typedef struct {
++	char *name;
++	uint16 base;
++} wl_pfbase_t;
++
++static wl_pfbase_t basenames[] = { WL_PKT_FILTER_BASE_NAMES };
++
++static int
++wl_pkt_filter_base_parse(char *name)
++{
++	uint i;
++	char *bname, *uname;
++
++	for (i = 0; i < ARRAYSIZE(basenames); i++) {
++		bname = basenames[i].name;
++		for (uname = name; *uname; bname++, uname++) {
++			if (*bname != bcm_toupper(*uname)) {
++				break;
++			}
++		}
++		if (!*uname && !*bname) {
++			break;
++		}
++	}
++
++	if (i < ARRAYSIZE(basenames)) {
++		return basenames[i].base;
++	} else {
++		return -1;
++	}
++}
++
++void
++dhd_pktfilter_offload_set(dhd_pub_t * dhd, char *arg)
++{
++	const char 			*str;
++	wl_pkt_filter_t		pkt_filter;
++	wl_pkt_filter_t		*pkt_filterp;
++	int					buf_len;
++	int					str_len;
++	int 				rc;
++	uint32				mask_size;
++	uint32				pattern_size;
++	char				*argv[16], * buf = 0;
++	int					i = 0;
++	char				*arg_save = 0, *arg_org = 0;
++#define BUF_SIZE		2048
++
++	if (!arg)
++		return;
++
++	if (!(arg_save = MALLOC(dhd->osh, strlen(arg) + 1))) {
++		DHD_ERROR(("%s: malloc failed\n", __FUNCTION__));
++		goto fail;
++	}
++
++	arg_org = arg_save;
++
++	if (!(buf = MALLOC(dhd->osh, BUF_SIZE))) {
++		DHD_ERROR(("%s: malloc failed\n", __FUNCTION__));
++		goto fail;
++	}
++	memset(buf, 0, BUF_SIZE);
++	memcpy(arg_save, arg, strlen(arg) + 1);
++
++	if (strlen(arg) > BUF_SIZE) {
++		DHD_ERROR(("Not enough buffer %d < %d\n", (int)strlen(arg), (int)sizeof(buf)));
++		goto fail;
++	}
++
++	argv[i] = bcmstrtok(&arg_save, " ", 0);
++	while (argv[i++])
++		argv[i] = bcmstrtok(&arg_save, " ", 0);
++
++	i = 0;
++	if (argv[i] == NULL) {
++		DHD_ERROR(("No args provided\n"));
++		goto fail;
++	}
++
++	str = "pkt_filter_add";
++	str_len = strlen(str);
++	bcm_strncpy_s(buf, BUF_SIZE, str, str_len);
++	buf[ str_len ] = '\0';
++	buf_len = str_len + 1;
++
++	pkt_filterp = (wl_pkt_filter_t *) (buf + str_len + 1);
++
++	/* Parse packet filter id. */
++	pkt_filter.id = htod32(strtoul(argv[i], NULL, 0));
++	if (dhd_conf_del_pkt_filter(dhd, pkt_filter.id))
++		goto fail;
++
++	if (argv[++i] == NULL) {
++		DHD_ERROR(("Polarity not provided\n"));
++		goto fail;
++	}
++
++	/* Parse filter polarity. */
++	pkt_filter.negate_match = htod32(strtoul(argv[i], NULL, 0));
++
++	if (argv[++i] == NULL) {
++		DHD_ERROR(("Filter type not provided\n"));
++		goto fail;
++	}
++
++	/* Parse filter type. */
++	pkt_filter.type = htod32(strtoul(argv[i], NULL, 0));
++
++	if ((pkt_filter.type == 0) || (pkt_filter.type == 1)) {
++		if (argv[++i] == NULL) {
++			DHD_ERROR(("Offset not provided\n"));
++			goto fail;
++		}
++
++		/* Parse pattern filter offset. */
++		pkt_filter.u.pattern.offset = htod32(strtoul(argv[i], NULL, 0));
++
++		if (argv[++i] == NULL) {
++			DHD_ERROR(("Bitmask not provided\n"));
++			goto fail;
++		}
++
++		/* Parse pattern filter mask. */
++		mask_size =
++			htod32(wl_pattern_atoh(argv[i],
++			(char *) pkt_filterp->u.pattern.mask_and_pattern));
++
++		if (argv[++i] == NULL) {
++			DHD_ERROR(("Pattern not provided\n"));
++			goto fail;
++		}
++
++		/* Parse pattern filter pattern. */
++		pattern_size =
++			htod32(wl_pattern_atoh(argv[i],
++			(char *) &pkt_filterp->u.pattern.mask_and_pattern[mask_size]));
++
++		if (mask_size != pattern_size) {
++			DHD_ERROR(("Mask and pattern not the same size\n"));
++			goto fail;
++		}
++
++		pkt_filter.u.pattern.size_bytes = mask_size;
++		buf_len += WL_PKT_FILTER_FIXED_LEN;
++		buf_len += (WL_PKT_FILTER_PATTERN_FIXED_LEN + 2 * mask_size);
++
++		/* Keep-alive attributes are set in local	variable (keep_alive_pkt), and
++		 * then memcpy'ed into buffer (keep_alive_pktp) since there is no
++		 * guarantee that the buffer is properly aligned.
++		 */
++		memcpy((char *)pkt_filterp,
++			&pkt_filter,
++			WL_PKT_FILTER_FIXED_LEN + WL_PKT_FILTER_PATTERN_FIXED_LEN);
++	} else if ((pkt_filter.type == 2) || (pkt_filter.type == 6)) {
++		int list_cnt = 0;
++		char *endptr = '\0';
++		wl_pkt_filter_pattern_listel_t *pf_el = &pkt_filterp->u.patlist.patterns[0];
++
++		while (argv[++i] != NULL) {
++			/* Parse pattern filter base and offset. */
++			if (bcm_isdigit(*argv[i])) {
++				/* Numeric base */
++				rc = strtoul(argv[i], &endptr, 0);
++			} else {
++				endptr = strchr(argv[i], ':');
++				if (endptr) {
++					*endptr = '\0';
++					rc = wl_pkt_filter_base_parse(argv[i]);
++					if (rc == -1) {
++						 printf("Invalid base %s\n", argv[i]);
++						goto fail;
++					}
++					*endptr = ':';
++				} else {
++					printf("Invalid [base:]offset format: %s\n", argv[i]);
++					goto fail;
++				}
++			}
++
++			if (*endptr == ':') {
++				pkt_filter.u.patlist.patterns[0].base_offs = htod16(rc);
++				rc = strtoul(endptr + 1, &endptr, 0);
++			} else {
++				/* Must have had a numeric offset only */
++				pkt_filter.u.patlist.patterns[0].base_offs = htod16(0);
++			}
++
++			if (*endptr) {
++				printf("Invalid [base:]offset format: %s\n", argv[i]);
++				goto fail;
++			}
++			if (rc > 0x0000FFFF) {
++				printf("Offset too large\n");
++				goto fail;
++			}
++			pkt_filter.u.patlist.patterns[0].rel_offs = htod16(rc);
++
++			/* Clear match_flag (may be set in parsing which follows) */
++			pkt_filter.u.patlist.patterns[0].match_flags = htod16(0);
++
++			/* Parse pattern filter mask and pattern directly into ioctl buffer */
++			if (argv[++i] == NULL) {
++				printf("Bitmask not provided\n");
++				goto fail;
++			}
++			rc = wl_pattern_atoh(argv[i], (char*)pf_el->mask_and_data);
++			if (rc == -1) {
++				printf("Rejecting: %s\n", argv[i]);
++				goto fail;
++			}
++			mask_size = htod16(rc);
++
++			if (argv[++i] == NULL) {
++				printf("Pattern not provided\n");
++				goto fail;
++			}
++
++			if (*argv[i] == '!') {
++				pkt_filter.u.patlist.patterns[0].match_flags =
++					htod16(WL_PKT_FILTER_MFLAG_NEG);
++				(argv[i])++;
++			}
++			if (*argv[i] == '\0') {
++				printf("Pattern not provided\n");
++				goto fail;
++			}
++			rc = wl_pattern_atoh(argv[i], (char*)&pf_el->mask_and_data[rc]);
++			if (rc == -1) {
++				printf("Rejecting: %s\n", argv[i]);
++				goto fail;
++			}
++			pattern_size = htod16(rc);
++
++			if (mask_size != pattern_size) {
++				printf("Mask and pattern not the same size\n");
++				goto fail;
++			}
++
++			pkt_filter.u.patlist.patterns[0].size_bytes = mask_size;
++
++			/* Account for the size of this pattern element */
++			buf_len += WL_PKT_FILTER_PATTERN_LISTEL_FIXED_LEN + 2 * rc;
++
++			/* And the pattern element fields that were put in a local for
++			 * alignment purposes now get copied to the ioctl buffer.
++			 */
++			memcpy((char*)pf_el, &pkt_filter.u.patlist.patterns[0],
++				WL_PKT_FILTER_PATTERN_FIXED_LEN);
++
++			/* Move to next element location in ioctl buffer */
++			pf_el = (wl_pkt_filter_pattern_listel_t*)
++				((uint8*)pf_el + WL_PKT_FILTER_PATTERN_LISTEL_FIXED_LEN + 2 * rc);
++
++			/* Count list element */
++			list_cnt++;
++		}
++
++		/* Account for initial fixed size, and copy initial fixed fields */
++		buf_len += WL_PKT_FILTER_FIXED_LEN + WL_PKT_FILTER_PATTERN_LIST_FIXED_LEN;
++
++		/* Update list count and total size */
++		pkt_filter.u.patlist.list_cnt = list_cnt;
++		pkt_filter.u.patlist.PAD1[0] = 0;
++		pkt_filter.u.patlist.totsize = buf + buf_len - (char*)pkt_filterp;
++		pkt_filter.u.patlist.totsize -= WL_PKT_FILTER_FIXED_LEN;
++
++		memcpy((char *)pkt_filterp, &pkt_filter,
++			WL_PKT_FILTER_FIXED_LEN + WL_PKT_FILTER_PATTERN_LIST_FIXED_LEN);
++	} else {
++		DHD_ERROR(("Invalid filter type %d\n", pkt_filter.type));
++		goto fail;
++	}
++
++	rc = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, buf, buf_len, TRUE, 0);
++	rc = rc >= 0 ? 0 : rc;
++
++	if (rc)
++		DHD_ERROR(("%s: failed to add pktfilter %s, retcode = %d\n",
++		__FUNCTION__, arg, rc));
++	else
++		DHD_TRACE(("%s: successfully added pktfilter %s\n",
++		__FUNCTION__, arg));
++
++fail:
++	if (arg_org)
++		MFREE(dhd->osh, arg_org, strlen(arg) + 1);
++
++	if (buf)
++		MFREE(dhd->osh, buf, BUF_SIZE);
++}
++
++void
++dhd_pktfilter_offload_delete(dhd_pub_t *dhd, int id)
++{
++	int ret;
++
++	ret = dhd_wl_ioctl_set_intiovar(dhd, "pkt_filter_delete",
++		id, WLC_SET_VAR, TRUE, 0);
++	if (ret < 0) {
++		DHD_ERROR(("%s: Failed to delete filter ID:%d, ret=%d\n",
++			__FUNCTION__, id, ret));
++	}
++	else
++		DHD_TRACE(("%s: successfully deleted pktfilter %d\n",
++		__FUNCTION__, id));
++}
++#endif /* PKT_FILTER_SUPPORT */
++
++/* ========================== */
++/* ==== ARP OFFLOAD SUPPORT = */
++/* ========================== */
++#ifdef ARP_OFFLOAD_SUPPORT
++void
++dhd_arp_offload_set(dhd_pub_t * dhd, int arp_mode)
++{
++	int retcode;
++
++	retcode = dhd_wl_ioctl_set_intiovar(dhd, "arp_ol",
++		arp_mode, WLC_SET_VAR, TRUE, 0);
++
++	retcode = retcode >= 0 ? 0 : retcode;
++	if (retcode)
++		DHD_ERROR(("%s: failed to set ARP offload mode to 0x%x, retcode = %d\n",
++			__FUNCTION__, arp_mode, retcode));
++	else
++		DHD_ARPOE(("%s: successfully set ARP offload mode to 0x%x\n",
++			__FUNCTION__, arp_mode));
++}
++
++void
++dhd_arp_offload_enable(dhd_pub_t * dhd, int arp_enable)
++{
++	int retcode;
++
++	retcode = dhd_wl_ioctl_set_intiovar(dhd, "arpoe",
++		arp_enable, WLC_SET_VAR, TRUE, 0);
++
++	retcode = retcode >= 0 ? 0 : retcode;
++	if (retcode)
++		DHD_ERROR(("%s: failed to enabe ARP offload to %d, retcode = %d\n",
++			__FUNCTION__, arp_enable, retcode));
++	else
++		DHD_ARPOE(("%s: successfully enabed ARP offload to %d\n",
++			__FUNCTION__, arp_enable));
++	if (arp_enable) {
++		uint32 version;
++		retcode = dhd_wl_ioctl_get_intiovar(dhd, "arp_version",
++			&version, WLC_GET_VAR, FALSE, 0);
++		if (retcode) {
++			DHD_INFO(("%s: fail to get version (maybe version 1:retcode = %d\n",
++				__FUNCTION__, retcode));
++			dhd->arp_version = 1;
++		}
++		else {
++			DHD_INFO(("%s: ARP Version= %x\n", __FUNCTION__, version));
++			dhd->arp_version = version;
++		}
++	}
++}
++
++void
++dhd_aoe_arp_clr(dhd_pub_t *dhd, int idx)
++{
++	int ret = 0;
++
++	if (dhd == NULL) return;
++	if (dhd->arp_version == 1)
++		idx = 0;
++
++	ret = dhd_iovar(dhd, idx, "arp_table_clear", NULL, 0, NULL, 0, TRUE);
++	if (ret < 0)
++		DHD_ERROR(("%s failed code %d\n", __FUNCTION__, ret));
++}
++
++void
++dhd_aoe_hostip_clr(dhd_pub_t *dhd, int idx)
++{
++	int ret = 0;
++
++	if (dhd == NULL) return;
++	if (dhd->arp_version == 1)
++		idx = 0;
++
++	ret = dhd_iovar(dhd, idx, "arp_hostip_clear", NULL, 0, NULL, 0, TRUE);
++	if (ret < 0)
++		DHD_ERROR(("%s failed code %d\n", __FUNCTION__, ret));
++}
++
++void
++dhd_arp_offload_add_ip(dhd_pub_t *dhd, uint32 ipaddr, int idx)
++{
++	int ret;
++
++	if (dhd == NULL) return;
++	if (dhd->arp_version == 1)
++		idx = 0;
++
++	ret = dhd_iovar(dhd, idx, "arp_hostip", (char *)&ipaddr, sizeof(ipaddr),
++			NULL, 0, TRUE);
++	if (ret)
++		DHD_ERROR(("%s: ARP ip addr add failed, ret = %d\n", __FUNCTION__, ret));
++	else
++		DHD_ARPOE(("%s: sARP H ipaddr entry added \n",
++			__FUNCTION__));
++}
++
++int
++dhd_arp_get_arp_hostip_table(dhd_pub_t *dhd, void *buf, int buflen, int idx)
++{
++	int ret, i;
++	uint32 *ptr32 = buf;
++	bool clr_bottom = FALSE;
++
++	if (!buf)
++		return -1;
++	if (dhd == NULL) return -1;
++	if (dhd->arp_version == 1)
++		idx = 0;
++
++	ret = dhd_iovar(dhd, idx, "arp_hostip", NULL, 0, (char *)buf, buflen,
++			FALSE);
++	if (ret) {
++		DHD_ERROR(("%s: ioctl WLC_GET_VAR error %d\n",
++		__FUNCTION__, ret));
++
++		return -1;
++	}
++
++	/* clean up the buf, ascii reminder */
++	for (i = 0; i < MAX_IPV4_ENTRIES; i++) {
++		if (!clr_bottom) {
++			if (*ptr32 == 0)
++				clr_bottom = TRUE;
++		} else {
++			*ptr32 = 0;
++		}
++		ptr32++;
++	}
++
++	return 0;
++}
++#endif /* ARP_OFFLOAD_SUPPORT  */
++
++/*
++ * Neighbor Discovery Offload: enable NDO feature
++ * Called  by ipv6 event handler when interface comes up/goes down
++ */
++int
++dhd_ndo_enable(dhd_pub_t * dhd, int ndo_enable)
++{
++	int retcode;
++
++	if (dhd == NULL)
++		return -1;
++
++	retcode = dhd_wl_ioctl_set_intiovar(dhd, "ndoe",
++		ndo_enable, WLC_SET_VAR, TRUE, 0);
++	if (retcode)
++		DHD_ERROR(("%s: failed to enabe ndo to %d, retcode = %d\n",
++			__FUNCTION__, ndo_enable, retcode));
++	else
++		DHD_TRACE(("%s: successfully enabed ndo offload to %d\n",
++			__FUNCTION__, ndo_enable));
++
++	return retcode;
++}
++
++/*
++ * Neighbor Discover Offload: enable NDO feature
++ * Called  by ipv6 event handler when interface comes up
++ */
++int
++dhd_ndo_add_ip(dhd_pub_t *dhd, char* ipv6addr, int idx)
++{
++	int iov_len = 0;
++	char iovbuf[DHD_IOVAR_BUF_SIZE] = {0};
++	int retcode;
++
++	if (dhd == NULL)
++		return -1;
++
++	iov_len = bcm_mkiovar("nd_hostip", (char *)ipv6addr,
++		IPV6_ADDR_LEN, iovbuf, sizeof(iovbuf));
++	if (!iov_len) {
++		DHD_ERROR(("%s: Insufficient iovar buffer size %zu \n",
++			__FUNCTION__, sizeof(iovbuf)));
++		return -1;
++	}
++	retcode = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, iovbuf, iov_len, TRUE, idx);
++
++	if (retcode)
++		DHD_ERROR(("%s: ndo ip addr add failed, retcode = %d\n",
++		__FUNCTION__, retcode));
++	else
++		DHD_TRACE(("%s: ndo ipaddr entry added \n",
++		__FUNCTION__));
++
++	return retcode;
++}
++
++/*
++ * Neighbor Discover Offload: enable NDO feature
++ * Called  by ipv6 event handler when interface goes down
++ */
++int
++dhd_ndo_remove_ip(dhd_pub_t *dhd, int idx)
++{
++	int iov_len = 0;
++	char iovbuf[DHD_IOVAR_BUF_SIZE] = {0};
++	int retcode;
++
++	if (dhd == NULL)
++		return -1;
++
++	iov_len = bcm_mkiovar("nd_hostip_clear", NULL,
++		0, iovbuf, sizeof(iovbuf));
++	if (!iov_len) {
++		DHD_ERROR(("%s: Insufficient iovar buffer size %zu \n",
++			__FUNCTION__, sizeof(iovbuf)));
++		return -1;
++	}
++	retcode = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, iovbuf, iov_len, TRUE, idx);
++
++	if (retcode)
++		DHD_ERROR(("%s: ndo ip addr remove failed, retcode = %d\n",
++		__FUNCTION__, retcode));
++	else
++		DHD_TRACE(("%s: ndo ipaddr entry removed \n",
++		__FUNCTION__));
++
++	return retcode;
++}
++
++/* Enhanced ND offload */
++uint16
++dhd_ndo_get_version(dhd_pub_t *dhdp)
++{
++	char iovbuf[DHD_IOVAR_BUF_SIZE];
++	wl_nd_hostip_t ndo_get_ver;
++	int iov_len;
++	int retcode;
++	uint16 ver = 0;
++
++	if (dhdp == NULL) {
++		return BCME_ERROR;
++	}
++
++	memset(&iovbuf, 0, sizeof(iovbuf));
++	ndo_get_ver.version = htod16(WL_ND_HOSTIP_IOV_VER);
++	ndo_get_ver.op_type = htod16(WL_ND_HOSTIP_OP_VER);
++	ndo_get_ver.length = htod32(WL_ND_HOSTIP_FIXED_LEN + sizeof(uint16));
++	ndo_get_ver.u.version = 0;
++	iov_len = bcm_mkiovar("nd_hostip", (char *)&ndo_get_ver,
++			WL_ND_HOSTIP_FIXED_LEN + sizeof(uint16), iovbuf, sizeof(iovbuf));
++	if (!iov_len) {
++		DHD_ERROR(("%s: Insufficient iovar buffer size %zu \n",
++			__FUNCTION__, sizeof(iovbuf)));
++		return BCME_ERROR;
++	}
++
++	retcode = dhd_wl_ioctl_cmd(dhdp, WLC_GET_VAR, iovbuf, iov_len, FALSE, 0);
++	if (retcode) {
++		DHD_ERROR(("%s: failed, retcode = %d\n", __FUNCTION__, retcode));
++		/* ver iovar not supported. NDO version is 0 */
++		ver = 0;
++	} else {
++		wl_nd_hostip_t *ndo_ver_ret = (wl_nd_hostip_t *)iovbuf;
++
++		if ((dtoh16(ndo_ver_ret->version) == WL_ND_HOSTIP_IOV_VER) &&
++				(dtoh16(ndo_ver_ret->op_type) == WL_ND_HOSTIP_OP_VER) &&
++				(dtoh32(ndo_ver_ret->length) == WL_ND_HOSTIP_FIXED_LEN
++					+ sizeof(uint16))) {
++			/* nd_hostip iovar version */
++			ver = dtoh16(ndo_ver_ret->u.version);
++		}
++
++		DHD_TRACE(("%s: successfully get version: %d\n", __FUNCTION__, ver));
++	}
++
++	return ver;
++}
++
++int
++dhd_ndo_add_ip_with_type(dhd_pub_t *dhdp, char *ipv6addr, uint8 type, int idx)
++{
++	char iovbuf[DHD_IOVAR_BUF_SIZE];
++	wl_nd_hostip_t ndo_add_addr;
++	int iov_len;
++	int retcode;
++
++	if (dhdp == NULL || ipv6addr == 0) {
++		return BCME_ERROR;
++	}
++
++	/* wl_nd_hostip_t fixed param */
++	ndo_add_addr.version = htod16(WL_ND_HOSTIP_IOV_VER);
++	ndo_add_addr.op_type = htod16(WL_ND_HOSTIP_OP_ADD);
++	ndo_add_addr.length = htod32(WL_ND_HOSTIP_WITH_ADDR_LEN);
++	/* wl_nd_host_ip_addr_t param for add */
++	memcpy(&ndo_add_addr.u.host_ip.ip_addr, ipv6addr, IPV6_ADDR_LEN);
++	ndo_add_addr.u.host_ip.type = type;
++
++	iov_len = bcm_mkiovar("nd_hostip", (char *)&ndo_add_addr,
++		WL_ND_HOSTIP_WITH_ADDR_LEN, iovbuf, sizeof(iovbuf));
++	if (!iov_len) {
++		DHD_ERROR(("%s: Insufficient iovar buffer size %zu \n",
++			__FUNCTION__, sizeof(iovbuf)));
++		return BCME_ERROR;
++	}
++
++	retcode = dhd_wl_ioctl_cmd(dhdp, WLC_SET_VAR, iovbuf, iov_len, TRUE, idx);
++	if (retcode) {
++		DHD_ERROR(("%s: failed, retcode = %d\n", __FUNCTION__, retcode));
++#ifdef NDO_CONFIG_SUPPORT
++		if (retcode == BCME_NORESOURCE) {
++			/* number of host ip addr exceeds FW capacity, Deactivate ND offload */
++			DHD_INFO(("%s: Host IP count exceed device capacity,"
++				"ND offload deactivated\n", __FUNCTION__));
++			dhdp->ndo_host_ip_overflow = TRUE;
++			dhd_ndo_enable(dhdp, 0);
++		}
++#endif /* NDO_CONFIG_SUPPORT */
++	} else {
++		DHD_TRACE(("%s: successfully added: %d\n", __FUNCTION__, retcode));
++	}
++
++	return retcode;
++}
++
++int
++dhd_ndo_remove_ip_by_addr(dhd_pub_t *dhdp, char *ipv6addr, int idx)
++{
++	char iovbuf[DHD_IOVAR_BUF_SIZE];
++	wl_nd_hostip_t ndo_del_addr;
++	int iov_len;
++	int retcode;
++
++	if (dhdp == NULL || ipv6addr == 0) {
++		return BCME_ERROR;
++	}
++
++	/* wl_nd_hostip_t fixed param */
++	ndo_del_addr.version = htod16(WL_ND_HOSTIP_IOV_VER);
++	ndo_del_addr.op_type = htod16(WL_ND_HOSTIP_OP_DEL);
++	ndo_del_addr.length = htod32(WL_ND_HOSTIP_WITH_ADDR_LEN);
++	/* wl_nd_host_ip_addr_t param for del */
++	memcpy(&ndo_del_addr.u.host_ip.ip_addr, ipv6addr, IPV6_ADDR_LEN);
++	ndo_del_addr.u.host_ip.type = 0;	/* don't care */
++
++	iov_len = bcm_mkiovar("nd_hostip", (char *)&ndo_del_addr,
++		WL_ND_HOSTIP_WITH_ADDR_LEN, iovbuf, sizeof(iovbuf));
++	if (!iov_len) {
++		DHD_ERROR(("%s: Insufficient iovar buffer size %zu \n",
++			__FUNCTION__, sizeof(iovbuf)));
++		return BCME_ERROR;
++	}
++
++	retcode = dhd_wl_ioctl_cmd(dhdp, WLC_SET_VAR, iovbuf, iov_len, TRUE, idx);
++	if (retcode) {
++		DHD_ERROR(("%s: failed, retcode = %d\n", __FUNCTION__, retcode));
++	} else {
++		DHD_TRACE(("%s: successfully removed: %d\n", __FUNCTION__, retcode));
++	}
++
++	return retcode;
++}
++
++int
++dhd_ndo_remove_ip_by_type(dhd_pub_t *dhdp, uint8 type, int idx)
++{
++	char iovbuf[DHD_IOVAR_BUF_SIZE];
++	wl_nd_hostip_t ndo_del_addr;
++	int iov_len;
++	int retcode;
++
++	if (dhdp == NULL) {
++		return BCME_ERROR;
++	}
++
++	/* wl_nd_hostip_t fixed param */
++	ndo_del_addr.version = htod16(WL_ND_HOSTIP_IOV_VER);
++	if (type == WL_ND_IPV6_ADDR_TYPE_UNICAST) {
++		ndo_del_addr.op_type = htod16(WL_ND_HOSTIP_OP_DEL_UC);
++	} else if (type == WL_ND_IPV6_ADDR_TYPE_ANYCAST) {
++		ndo_del_addr.op_type = htod16(WL_ND_HOSTIP_OP_DEL_AC);
++	} else {
++		return BCME_BADARG;
++	}
++	ndo_del_addr.length = htod32(WL_ND_HOSTIP_FIXED_LEN);
++
++	iov_len = bcm_mkiovar("nd_hostip", (char *)&ndo_del_addr, WL_ND_HOSTIP_FIXED_LEN,
++			iovbuf, sizeof(iovbuf));
++	if (!iov_len) {
++		DHD_ERROR(("%s: Insufficient iovar buffer size %zu \n",
++			__FUNCTION__, sizeof(iovbuf)));
++		return BCME_ERROR;
++	}
++
++	retcode = dhd_wl_ioctl_cmd(dhdp, WLC_SET_VAR, iovbuf, iov_len, TRUE, idx);
++	if (retcode) {
++		DHD_ERROR(("%s: failed, retcode = %d\n", __FUNCTION__, retcode));
++	} else {
++		DHD_TRACE(("%s: successfully removed: %d\n", __FUNCTION__, retcode));
++	}
++
++	return retcode;
++}
++
++int
++dhd_ndo_unsolicited_na_filter_enable(dhd_pub_t *dhdp, int enable)
++{
++	char iovbuf[DHD_IOVAR_BUF_SIZE];
++	int iov_len;
++	int retcode;
++
++	if (dhdp == NULL) {
++		return BCME_ERROR;
++	}
++
++	iov_len = bcm_mkiovar("nd_unsolicited_na_filter", (char *)&enable, sizeof(int),
++			iovbuf, sizeof(iovbuf));
++	if (!iov_len) {
++		DHD_ERROR(("%s: Insufficient iovar buffer size %zu \n",
++			__FUNCTION__, sizeof(iovbuf)));
++		return BCME_ERROR;
++	}
++	retcode = dhd_wl_ioctl_cmd(dhdp, WLC_SET_VAR, iovbuf, iov_len, TRUE, 0);
++	if (retcode)
++		DHD_ERROR(("%s: failed to enable Unsolicited NA filter to %d, retcode = %d\n",
++			__FUNCTION__, enable, retcode));
++	else {
++		DHD_TRACE(("%s: successfully enabled Unsolicited NA filter to %d\n",
++			__FUNCTION__, enable));
++	}
++
++	return retcode;
++}
++
++
++/*
++ * returns = TRUE if associated, FALSE if not associated
++ */
++bool dhd_is_associated(dhd_pub_t *dhd, uint8 ifidx, int *retval)
++{
++	char bssid[6], zbuf[6];
++	int ret = -1;
++
++	bzero(bssid, 6);
++	bzero(zbuf, 6);
++
++	ret  = dhd_wl_ioctl_cmd(dhd, WLC_GET_BSSID, (char *)&bssid,
++		ETHER_ADDR_LEN, FALSE, ifidx);
++	DHD_TRACE((" %s WLC_GET_BSSID ioctl res = %d\n", __FUNCTION__, ret));
++
++	if (ret == BCME_NOTASSOCIATED) {
++		DHD_TRACE(("%s: not associated! res:%d\n", __FUNCTION__, ret));
++	}
++
++	if (retval)
++		*retval = ret;
++
++	if (ret < 0)
++		return FALSE;
++
++	if ((memcmp(bssid, zbuf, ETHER_ADDR_LEN) == 0)) {
++		DHD_TRACE(("%s: WLC_GET_BSSID ioctl returned zero bssid\n", __FUNCTION__));
++		return FALSE;
++	}
++	return TRUE;
++}
++
++/* Function to estimate possible DTIM_SKIP value */
++#if defined(BCMPCIE)
++int
++dhd_get_suspend_bcn_li_dtim(dhd_pub_t *dhd, int *dtim_period, int *bcn_interval)
++{
++	int bcn_li_dtim = 1; /* deafult no dtim skip setting */
++	int ret = -1;
++	int allowed_skip_dtim_cnt = 0;
++
++	/* Check if associated */
++	if (dhd_is_associated(dhd, 0, NULL) == FALSE) {
++		DHD_TRACE(("%s NOT assoc ret %d\n", __FUNCTION__, ret));
++		return bcn_li_dtim;
++	}
++
++	if (dtim_period == NULL || bcn_interval == NULL)
++		return bcn_li_dtim;
++
++	/* read associated AP beacon interval */
++	if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_GET_BCNPRD,
++		bcn_interval, sizeof(*bcn_interval), FALSE, 0)) < 0) {
++		DHD_ERROR(("%s get beacon failed code %d\n", __FUNCTION__, ret));
++		return bcn_li_dtim;
++	}
++
++	/* read associated AP dtim setup */
++	if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_GET_DTIMPRD,
++		dtim_period, sizeof(*dtim_period), FALSE, 0)) < 0) {
++		DHD_ERROR(("%s failed code %d\n", __FUNCTION__, ret));
++		return bcn_li_dtim;
++	}
++
++	/* if not assocated just return */
++	if (*dtim_period == 0) {
++		return bcn_li_dtim;
++	}
++
++	if (dhd->max_dtim_enable) {
++		bcn_li_dtim =
++			(int) (MAX_DTIM_ALLOWED_INTERVAL / ((*dtim_period) * (*bcn_interval)));
++		if (bcn_li_dtim == 0) {
++			bcn_li_dtim = 1;
++		}
++	} else {
++		/* attemp to use platform defined dtim skip interval */
++		bcn_li_dtim = dhd->suspend_bcn_li_dtim;
++
++		/* check if sta listen interval fits into AP dtim */
++		if (*dtim_period > CUSTOM_LISTEN_INTERVAL) {
++			/* AP DTIM to big for our Listen Interval : no dtim skiping */
++			bcn_li_dtim = NO_DTIM_SKIP;
++			DHD_ERROR(("%s DTIM=%d > Listen=%d : too big ...\n",
++				__FUNCTION__, *dtim_period, CUSTOM_LISTEN_INTERVAL));
++			return bcn_li_dtim;
++		}
++
++		if (((*dtim_period) * (*bcn_interval) * bcn_li_dtim) > MAX_DTIM_ALLOWED_INTERVAL) {
++			allowed_skip_dtim_cnt =
++				MAX_DTIM_ALLOWED_INTERVAL / ((*dtim_period) * (*bcn_interval));
++			bcn_li_dtim =
++				(allowed_skip_dtim_cnt != 0) ? allowed_skip_dtim_cnt : NO_DTIM_SKIP;
++		}
++
++		if ((bcn_li_dtim * (*dtim_period)) > CUSTOM_LISTEN_INTERVAL) {
++			/* Round up dtim_skip to fit into STAs Listen Interval */
++			bcn_li_dtim = (int)(CUSTOM_LISTEN_INTERVAL / *dtim_period);
++			DHD_TRACE(("%s agjust dtim_skip as %d\n", __FUNCTION__, bcn_li_dtim));
++		}
++	}
++
++	if (dhd->conf->suspend_bcn_li_dtim >= 0)
++		bcn_li_dtim = dhd->conf->suspend_bcn_li_dtim;
++	DHD_ERROR(("%s beacon=%d bcn_li_dtim=%d DTIM=%d Listen=%d\n",
++		__FUNCTION__, *bcn_interval, bcn_li_dtim, *dtim_period, CUSTOM_LISTEN_INTERVAL));
++
++	return bcn_li_dtim;
++}
++#else /* OEM_ANDROID && BCMPCIE */
++int
++dhd_get_suspend_bcn_li_dtim(dhd_pub_t *dhd)
++{
++	int bcn_li_dtim = 1; /* deafult no dtim skip setting */
++	int ret = -1;
++	int dtim_period = 0;
++	int ap_beacon = 0;
++	int allowed_skip_dtim_cnt = 0;
++	/* Check if associated */
++	if (dhd_is_associated(dhd, 0, NULL) == FALSE) {
++		DHD_TRACE(("%s NOT assoc ret %d\n", __FUNCTION__, ret));
++		goto exit;
++	}
++
++	/* read associated AP beacon interval */
++	if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_GET_BCNPRD,
++		&ap_beacon, sizeof(ap_beacon), FALSE, 0)) < 0) {
++		DHD_ERROR(("%s get beacon failed code %d\n", __FUNCTION__, ret));
++		goto exit;
++	}
++
++	/* read associated ap's dtim setup */
++	if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_GET_DTIMPRD,
++		&dtim_period, sizeof(dtim_period), FALSE, 0)) < 0) {
++		DHD_ERROR(("%s failed code %d\n", __FUNCTION__, ret));
++		goto exit;
++	}
++
++	/* if not assocated just exit */
++	if (dtim_period == 0) {
++		goto exit;
++	}
++
++	if (dhd->max_dtim_enable) {
++		bcn_li_dtim = (int) (MAX_DTIM_ALLOWED_INTERVAL / (ap_beacon * dtim_period));
++		if (bcn_li_dtim == 0) {
++			bcn_li_dtim = 1;
++		}
++	} else {
++		/* attemp to use platform defined dtim skip interval */
++		bcn_li_dtim = dhd->suspend_bcn_li_dtim;
++
++		/* check if sta listen interval fits into AP dtim */
++		if (dtim_period > CUSTOM_LISTEN_INTERVAL) {
++			/* AP DTIM to big for our Listen Interval : no dtim skiping */
++			bcn_li_dtim = NO_DTIM_SKIP;
++			DHD_ERROR(("%s DTIM=%d > Listen=%d : too big ...\n",
++				__FUNCTION__, dtim_period, CUSTOM_LISTEN_INTERVAL));
++			goto exit;
++		}
++
++		if ((dtim_period * ap_beacon * bcn_li_dtim) > MAX_DTIM_ALLOWED_INTERVAL) {
++			allowed_skip_dtim_cnt =
++				MAX_DTIM_ALLOWED_INTERVAL / (dtim_period * ap_beacon);
++			bcn_li_dtim =
++				(allowed_skip_dtim_cnt != 0) ? allowed_skip_dtim_cnt : NO_DTIM_SKIP;
++		}
++
++		if ((bcn_li_dtim * dtim_period) > CUSTOM_LISTEN_INTERVAL) {
++			/* Round up dtim_skip to fit into STAs Listen Interval */
++			bcn_li_dtim = (int)(CUSTOM_LISTEN_INTERVAL / dtim_period);
++			DHD_TRACE(("%s agjust dtim_skip as %d\n", __FUNCTION__, bcn_li_dtim));
++		}
++	}
++
++	if (dhd->conf->suspend_bcn_li_dtim >= 0)
++		bcn_li_dtim = dhd->conf->suspend_bcn_li_dtim;
++	DHD_ERROR(("%s beacon=%d bcn_li_dtim=%d DTIM=%d Listen=%d\n",
++		__FUNCTION__, ap_beacon, bcn_li_dtim, dtim_period, CUSTOM_LISTEN_INTERVAL));
++
++exit:
++	return bcn_li_dtim;
++}
++#endif /* OEM_ANDROID && BCMPCIE */
++
++/* Check if the mode supports STA MODE */
++bool dhd_support_sta_mode(dhd_pub_t *dhd)
++{
++
++#ifdef  WL_CFG80211
++	if (!(dhd->op_mode & DHD_FLAG_STA_MODE))
++		return FALSE;
++	else
++#endif /* WL_CFG80211 */
++		return TRUE;
++}
++
++#if defined(KEEP_ALIVE)
++int dhd_keep_alive_onoff(dhd_pub_t *dhd)
++{
++	char				buf[32] = {0};
++	const char			*str;
++	wl_mkeep_alive_pkt_t	mkeep_alive_pkt = {0, 0, 0, 0, 0, {0}};
++	wl_mkeep_alive_pkt_t	*mkeep_alive_pktp;
++	int					buf_len;
++	int					str_len;
++	int res					= -1;
++
++	if (!dhd_support_sta_mode(dhd))
++		return res;
++
++	DHD_TRACE(("%s execution\n", __FUNCTION__));
++
++	str = "mkeep_alive";
++	str_len = strlen(str);
++	strncpy(buf, str, sizeof(buf) - 1);
++	buf[ sizeof(buf) - 1 ] = '\0';
++	mkeep_alive_pktp = (wl_mkeep_alive_pkt_t *) (buf + str_len + 1);
++	mkeep_alive_pkt.period_msec = dhd->conf->keep_alive_period;
++	buf_len = str_len + 1;
++	mkeep_alive_pkt.version = htod16(WL_MKEEP_ALIVE_VERSION);
++	mkeep_alive_pkt.length = htod16(WL_MKEEP_ALIVE_FIXED_LEN);
++	/* Setup keep alive zero for null packet generation */
++	mkeep_alive_pkt.keep_alive_id = 0;
++	mkeep_alive_pkt.len_bytes = 0;
++	buf_len += WL_MKEEP_ALIVE_FIXED_LEN;
++	bzero(mkeep_alive_pkt.data, sizeof(mkeep_alive_pkt.data));
++	/* Keep-alive attributes are set in local	variable (mkeep_alive_pkt), and
++	 * then memcpy'ed into buffer (mkeep_alive_pktp) since there is no
++	 * guarantee that the buffer is properly aligned.
++	 */
++	memcpy((char *)mkeep_alive_pktp, &mkeep_alive_pkt, WL_MKEEP_ALIVE_FIXED_LEN);
++
++	res = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, buf, buf_len, TRUE, 0);
++
++	return res;
++}
++#endif /* defined(KEEP_ALIVE) */
++
++#define CSCAN_TLV_TYPE_SSID_IE	'S'
++/*
++ *  SSIDs list parsing from cscan tlv list
++ */
++int
++wl_parse_ssid_list_tlv(char** list_str, wlc_ssid_ext_t* ssid, int max, int *bytes_left)
++{
++	char* str;
++	int idx = 0;
++
++	if ((list_str == NULL) || (*list_str == NULL) || (*bytes_left < 0)) {
++		DHD_ERROR(("%s error paramters\n", __FUNCTION__));
++		return -1;
++	}
++	str = *list_str;
++	while (*bytes_left > 0) {
++
++		if (str[0] != CSCAN_TLV_TYPE_SSID_IE) {
++			*list_str = str;
++			DHD_TRACE(("nssid=%d left_parse=%d %d\n", idx, *bytes_left, str[0]));
++			return idx;
++		}
++
++		/* Get proper CSCAN_TLV_TYPE_SSID_IE */
++		*bytes_left -= 1;
++		str += 1;
++		ssid[idx].rssi_thresh = 0;
++		ssid[idx].flags = 0;
++		if (str[0] == 0) {
++			/* Broadcast SSID */
++			ssid[idx].SSID_len = 0;
++			memset((char*)ssid[idx].SSID, 0x0, DOT11_MAX_SSID_LEN);
++			*bytes_left -= 1;
++			str += 1;
++
++			DHD_TRACE(("BROADCAST SCAN  left=%d\n", *bytes_left));
++		}
++		else if (str[0] <= DOT11_MAX_SSID_LEN) {
++			/* Get proper SSID size */
++			ssid[idx].SSID_len = str[0];
++			*bytes_left -= 1;
++			str += 1;
++
++			/* Get SSID */
++			if (ssid[idx].SSID_len > *bytes_left) {
++				DHD_ERROR(("%s out of memory range len=%d but left=%d\n",
++				__FUNCTION__, ssid[idx].SSID_len, *bytes_left));
++				return -1;
++			}
++
++			memcpy((char*)ssid[idx].SSID, str, ssid[idx].SSID_len);
++
++			*bytes_left -= ssid[idx].SSID_len;
++			str += ssid[idx].SSID_len;
++			ssid[idx].hidden = TRUE;
++
++			DHD_TRACE(("%s :size=%d left=%d\n",
++				(char*)ssid[idx].SSID, ssid[idx].SSID_len, *bytes_left));
++		}
++		else {
++			DHD_ERROR(("### SSID size more that %d\n", str[0]));
++			return -1;
++		}
++
++		if (idx++ >  max) {
++			DHD_ERROR(("%s number of SSIDs more that %d\n", __FUNCTION__, idx));
++			return -1;
++		}
++	}
++
++	*list_str = str;
++	return idx;
++}
++
++#if defined(WL_WIRELESS_EXT)
++/* Android ComboSCAN support */
++
++/*
++ *  data parsing from ComboScan tlv list
++*/
++int
++wl_iw_parse_data_tlv(char** list_str, void *dst, int dst_size, const char token,
++                     int input_size, int *bytes_left)
++{
++	char* str;
++	uint16 short_temp;
++	uint32 int_temp;
++
++	if ((list_str == NULL) || (*list_str == NULL) ||(bytes_left == NULL) || (*bytes_left < 0)) {
++		DHD_ERROR(("%s error paramters\n", __FUNCTION__));
++		return -1;
++	}
++	str = *list_str;
++
++	/* Clean all dest bytes */
++	memset(dst, 0, dst_size);
++	while (*bytes_left > 0) {
++
++		if (str[0] != token) {
++			DHD_TRACE(("%s NOT Type=%d get=%d left_parse=%d \n",
++				__FUNCTION__, token, str[0], *bytes_left));
++			return -1;
++		}
++
++		*bytes_left -= 1;
++		str += 1;
++
++		if (input_size == 1) {
++			memcpy(dst, str, input_size);
++		}
++		else if (input_size == 2) {
++			memcpy(dst, (char *)htod16(memcpy(&short_temp, str, input_size)),
++				input_size);
++		}
++		else if (input_size == 4) {
++			memcpy(dst, (char *)htod32(memcpy(&int_temp, str, input_size)),
++				input_size);
++		}
++
++		*bytes_left -= input_size;
++		str += input_size;
++		*list_str = str;
++		return 1;
++	}
++	return 1;
++}
++
++/*
++ *  channel list parsing from cscan tlv list
++*/
++int
++wl_iw_parse_channel_list_tlv(char** list_str, uint16* channel_list,
++                             int channel_num, int *bytes_left)
++{
++	char* str;
++	int idx = 0;
++
++	if ((list_str == NULL) || (*list_str == NULL) ||(bytes_left == NULL) || (*bytes_left < 0)) {
++		DHD_ERROR(("%s error paramters\n", __FUNCTION__));
++		return -1;
++	}
++	str = *list_str;
++
++	while (*bytes_left > 0) {
++
++		if (str[0] != CSCAN_TLV_TYPE_CHANNEL_IE) {
++			*list_str = str;
++			DHD_TRACE(("End channel=%d left_parse=%d %d\n", idx, *bytes_left, str[0]));
++			return idx;
++		}
++		/* Get proper CSCAN_TLV_TYPE_CHANNEL_IE */
++		*bytes_left -= 1;
++		str += 1;
++
++		if (str[0] == 0) {
++			/* All channels */
++			channel_list[idx] = 0x0;
++		}
++		else {
++			channel_list[idx] = (uint16)str[0];
++			DHD_TRACE(("%s channel=%d \n", __FUNCTION__,  channel_list[idx]));
++		}
++		*bytes_left -= 1;
++		str += 1;
++
++		if (idx++ > 255) {
++			DHD_ERROR(("%s Too many channels \n", __FUNCTION__));
++			return -1;
++		}
++	}
++
++	*list_str = str;
++	return idx;
++}
++
++/* Parse a comma-separated list from list_str into ssid array, starting
++ * at index idx.  Max specifies size of the ssid array.  Parses ssids
++ * and returns updated idx; if idx >= max not all fit, the excess have
++ * not been copied.  Returns -1 on empty string, or on ssid too long.
++ */
++int
++wl_iw_parse_ssid_list(char** list_str, wlc_ssid_t* ssid, int idx, int max)
++{
++	char* str, *ptr;
++
++	if ((list_str == NULL) || (*list_str == NULL))
++		return -1;
++
++	for (str = *list_str; str != NULL; str = ptr) {
++
++		/* check for next TAG */
++		if (!strncmp(str, GET_CHANNEL, strlen(GET_CHANNEL))) {
++			*list_str	 = str + strlen(GET_CHANNEL);
++			return idx;
++		}
++
++		if ((ptr = strchr(str, ',')) != NULL) {
++			*ptr++ = '\0';
++		}
++
++		if (strlen(str) > DOT11_MAX_SSID_LEN) {
++			DHD_ERROR(("ssid <%s> exceeds %d\n", str, DOT11_MAX_SSID_LEN));
++			return -1;
++		}
++
++		if (strlen(str) == 0)
++			ssid[idx].SSID_len = 0;
++
++		if (idx < max) {
++			bzero(ssid[idx].SSID, sizeof(ssid[idx].SSID));
++			strncpy((char*)ssid[idx].SSID, str, sizeof(ssid[idx].SSID) - 1);
++			ssid[idx].SSID_len = strlen(str);
++		}
++		idx++;
++	}
++	return idx;
++}
++
++/*
++ * Parse channel list from iwpriv CSCAN
++ */
++int
++wl_iw_parse_channel_list(char** list_str, uint16* channel_list, int channel_num)
++{
++	int num;
++	int val;
++	char* str;
++	char* endptr = NULL;
++
++	if ((list_str == NULL)||(*list_str == NULL))
++		return -1;
++
++	str = *list_str;
++	num = 0;
++	while (strncmp(str, GET_NPROBE, strlen(GET_NPROBE))) {
++		val = (int)strtoul(str, &endptr, 0);
++		if (endptr == str) {
++			printf("could not parse channel number starting at"
++				" substring \"%s\" in list:\n%s\n",
++				str, *list_str);
++			return -1;
++		}
++		str = endptr + strspn(endptr, " ,");
++
++		if (num == channel_num) {
++			DHD_ERROR(("too many channels (more than %d) in channel list:\n%s\n",
++				channel_num, *list_str));
++			return -1;
++		}
++
++		channel_list[num++] = (uint16)val;
++	}
++	*list_str = str;
++	return num;
++}
++
++#endif 
++
++#if defined(TRAFFIC_MGMT_DWM)
++static int traffic_mgmt_add_dwm_filter(dhd_pub_t *dhd,
++	trf_mgmt_filter_list_t * trf_mgmt_filter_list, int len)
++{
++	int ret = 0;
++	uint32              i;
++	trf_mgmt_filter_t   *trf_mgmt_filter;
++	uint8               dwm_tbl_entry;
++	uint32              dscp = 0;
++	uint16              dwm_filter_enabled = 0;
++
++
++	/* Check parameter length is adequate */
++	if (len < (OFFSETOF(trf_mgmt_filter_list_t, filter) +
++		trf_mgmt_filter_list->num_filters * sizeof(trf_mgmt_filter_t))) {
++		ret = BCME_BUFTOOSHORT;
++		return ret;
++	}
++
++	bzero(&dhd->dhd_tm_dwm_tbl, sizeof(dhd_trf_mgmt_dwm_tbl_t));
++
++	for (i = 0; i < trf_mgmt_filter_list->num_filters; i++) {
++		trf_mgmt_filter = &trf_mgmt_filter_list->filter[i];
++
++		dwm_filter_enabled = (trf_mgmt_filter->flags & TRF_FILTER_DWM);
++
++		if (dwm_filter_enabled) {
++			dscp = trf_mgmt_filter->dscp;
++			if (dscp >= DHD_DWM_TBL_SIZE) {
++				ret = BCME_BADARG;
++			return ret;
++			}
++		}
++
++		dhd->dhd_tm_dwm_tbl.dhd_dwm_enabled = 1;
++		/* set WMM AC bits */
++		dwm_tbl_entry = (uint8) trf_mgmt_filter->priority;
++		DHD_TRF_MGMT_DWM_SET_FILTER(dwm_tbl_entry);
++
++		/* set favored bits */
++		if (trf_mgmt_filter->flags & TRF_FILTER_FAVORED)
++			DHD_TRF_MGMT_DWM_SET_FAVORED(dwm_tbl_entry);
++
++		dhd->dhd_tm_dwm_tbl.dhd_dwm_tbl[dscp] =  dwm_tbl_entry;
++	}
++	return ret;
++}
++#endif 
++
++/* Given filename and download type,  returns a buffer pointer and length
++ * for download to f/w. Type can be FW or NVRAM.
++ *
++ */
++int dhd_get_download_buffer(dhd_pub_t	*dhd, char *file_path, download_type_t component,
++	char ** buffer, int *length)
++
++{
++	int ret = BCME_ERROR;
++	int len = 0;
++	int file_len;
++	void *image = NULL;
++	uint8 *buf = NULL;
++
++	/* Point to cache if available. */
++#ifdef CACHE_FW_IMAGES
++	if (component == FW) {
++		if (dhd->cached_fw_length) {
++			len = dhd->cached_fw_length;
++			buf = dhd->cached_fw;
++		}
++	}
++	else if (component == NVRAM) {
++		if (dhd->cached_nvram_length) {
++			len = dhd->cached_nvram_length;
++			buf = dhd->cached_nvram;
++		}
++	}
++	else if (component == CLM_BLOB) {
++		if (dhd->cached_clm_length) {
++			len = dhd->cached_clm_length;
++			buf = dhd->cached_clm;
++		}
++	} else {
++		return ret;
++	}
++#endif /* CACHE_FW_IMAGES */
++	/* No Valid cache found on this call */
++	if (!len) {
++		file_len = *length;
++		*length = 0;
++
++		if (file_path) {
++			image = dhd_os_open_image(file_path);
++			if (image == NULL) {
++				printf("%s: Open image file failed %s\n", __FUNCTION__, file_path);
++				goto err;
++			}
++		}
++
++		buf = MALLOCZ(dhd->osh, file_len);
++		if (buf == NULL) {
++			DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
++				__FUNCTION__, file_len));
++			goto err;
++		}
++
++		/* Download image */
++#if defined(BCMEMBEDIMAGE) && defined(DHD_EFI)
++		if (!image) {
++			memcpy(buf, nvram_arr, sizeof(nvram_arr));
++			len = sizeof(nvram_arr);
++		} else {
++			len = dhd_os_get_image_block((char *)buf, file_len, image);
++			if ((len <= 0 || len > file_len)) {
++				MFREE(dhd->osh, buf, file_len);
++				goto err;
++			}
++		}
++#else
++		len = dhd_os_get_image_block((char *)buf, file_len, image);
++		if ((len <= 0 || len > file_len)) {
++			MFREE(dhd->osh, buf, file_len);
++			goto err;
++		}
++#endif /* DHD_EFI */
++	}
++
++	ret = BCME_OK;
++	*length = len;
++	*buffer = (char *)buf;
++
++	/* Cache if first call. */
++#ifdef CACHE_FW_IMAGES
++	if (component == FW) {
++		if (!dhd->cached_fw_length) {
++			dhd->cached_fw = buf;
++			dhd->cached_fw_length = len;
++		}
++	}
++	else if (component == NVRAM) {
++		if (!dhd->cached_nvram_length) {
++			dhd->cached_nvram = buf;
++			dhd->cached_nvram_length = len;
++		}
++	}
++	else if (component == CLM_BLOB) {
++		if (!dhd->cached_clm_length) {
++			 dhd->cached_clm = buf;
++			 dhd->cached_clm_length = len;
++		}
++	}
++#endif /* CACHE_FW_IMAGES */
++
++err:
++	if (image)
++		dhd_os_close_image(image);
++
++	return ret;
++}
++
++int
++dhd_download_2_dongle(dhd_pub_t	*dhd, char *iovar, uint16 flag, uint16 dload_type,
++	unsigned char *dload_buf, int len)
++{
++	struct wl_dload_data *dload_ptr = (struct wl_dload_data *)dload_buf;
++	int err = 0;
++	int dload_data_offset;
++	static char iovar_buf[WLC_IOCTL_MEDLEN];
++	int iovar_len;
++
++	memset(iovar_buf, 0, sizeof(iovar_buf));
++
++	dload_data_offset = OFFSETOF(wl_dload_data_t, data);
++	dload_ptr->flag = (DLOAD_HANDLER_VER << DLOAD_FLAG_VER_SHIFT) | flag;
++	dload_ptr->dload_type = dload_type;
++	dload_ptr->len = htod32(len - dload_data_offset);
++	dload_ptr->crc = 0;
++	len = ROUNDUP(len, 8);
++
++	iovar_len = bcm_mkiovar(iovar, (char *)dload_buf,
++		(uint)len, iovar_buf, sizeof(iovar_buf));
++	if (iovar_len == 0) {
++		DHD_ERROR(("%s: insufficient buffer space passed to bcm_mkiovar for '%s' \n",
++		           __FUNCTION__, iovar));
++		return BCME_BUFTOOSHORT;
++	}
++
++	err = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, iovar_buf,
++			iovar_len, IOV_SET, 0);
++
++	return err;
++}
++
++int
++dhd_download_blob(dhd_pub_t	*dhd, unsigned char *image,
++		uint32 len, char *iovar)
++{
++	int chunk_len;
++	int size2alloc;
++	unsigned char *new_buf;
++	int err = 0, data_offset;
++	uint16 dl_flag = DL_BEGIN;
++
++	data_offset = OFFSETOF(wl_dload_data_t, data);
++	size2alloc = data_offset + MAX_CHUNK_LEN;
++	size2alloc = ROUNDUP(size2alloc, 8);
++
++	if ((new_buf = (unsigned char *)MALLOCZ(dhd->osh, size2alloc)) != NULL) {
++		do {
++			chunk_len = dhd_os_get_image_block((char *)(new_buf + data_offset),
++				MAX_CHUNK_LEN, image);
++			if (chunk_len < 0) {
++				DHD_ERROR(("%s: dhd_os_get_image_block failed (%d)\n",
++					__FUNCTION__, chunk_len));
++				err = BCME_ERROR;
++				goto exit;
++			}
++
++			if (len - chunk_len == 0)
++				dl_flag |= DL_END;
++
++			err = dhd_download_2_dongle(dhd, iovar, dl_flag, DL_TYPE_CLM,
++				new_buf, data_offset + chunk_len);
++
++			dl_flag &= ~DL_BEGIN;
++
++			len = len - chunk_len;
++		} while ((len > 0) && (err == 0));
++	} else {
++		err = BCME_NOMEM;
++	}
++exit:
++	if (new_buf) {
++		MFREE(dhd->osh, new_buf, size2alloc);
++	}
++
++	return err;
++}
++
++int
++dhd_check_current_clm_data(dhd_pub_t *dhd)
++{
++	char iovbuf[WLC_IOCTL_SMLEN] = {0};
++	wl_country_t *cspec;
++	int err = BCME_OK;
++
++	bcm_mkiovar("country", NULL, 0, iovbuf, sizeof(iovbuf));
++	err = dhd_wl_ioctl_cmd(dhd, WLC_GET_VAR, iovbuf, sizeof(iovbuf), FALSE, 0);
++	if (err) {
++		DHD_ERROR(("%s: country code get failed\n", __FUNCTION__));
++		return err;
++	}
++
++	cspec = (wl_country_t *)iovbuf;
++	if ((strncmp(cspec->ccode, WL_CCODE_NULL_COUNTRY, WLC_CNTRY_BUF_SZ)) == 0) {
++		DHD_ERROR(("%s: ----- This FW is not included CLM data -----\n",
++			__FUNCTION__));
++		return FALSE;
++	}
++	DHD_ERROR(("%s: ----- This FW is included CLM data -----\n",
++		__FUNCTION__));
++	return TRUE;
++}
++
++int
++dhd_apply_default_clm(dhd_pub_t *dhd, char *clm_path)
++{
++	char *clm_blob_path;
++	int len;
++	unsigned char *imgbuf = NULL;
++	int err = BCME_OK;
++	char iovbuf[WLC_IOCTL_SMLEN] = {0};
++	int status = FALSE;
++
++	if (clm_path && clm_path[0] != '\0') {
++		if (strlen(clm_path) > MOD_PARAM_PATHLEN) {
++			DHD_ERROR(("clm path exceeds max len\n"));
++			return BCME_ERROR;
++		}
++		clm_blob_path = clm_path;
++		DHD_TRACE(("clm path from module param:%s\n", clm_path));
++	} else {
++		clm_blob_path = CONFIG_BCMDHD_CLM_PATH;
++	}
++
++	/* If CLM blob file is found on the filesystem, download the file.
++	 * After CLM file download or If the blob file is not present,
++	 * validate the country code before proceeding with the initialization.
++	 * If country code is not valid, fail the initialization.
++	 */
++
++	imgbuf = dhd_os_open_image((char *)clm_blob_path);
++	if (imgbuf == NULL) {
++		printf("%s: Ignore clm file %s\n", __FUNCTION__, clm_path);
++#if defined(DHD_BLOB_EXISTENCE_CHECK)
++		if (dhd->is_blob) {
++			err = BCME_ERROR;
++		} else {
++			status = dhd_check_current_clm_data(dhd);
++			if (status == TRUE) {
++				err = BCME_OK;
++			} else {
++				err = BCME_ERROR;
++			}
++		}
++#endif /* DHD_BLOB_EXISTENCE_CHECK */
++		goto exit;
++	}
++
++	len = dhd_os_get_image_size(imgbuf);
++
++	if ((len > 0) && (len < MAX_CLM_BUF_SIZE) && imgbuf) {
++		status = dhd_check_current_clm_data(dhd);
++		if (status == TRUE) {
++#if defined(DHD_BLOB_EXISTENCE_CHECK)
++			if (dhd->op_mode != DHD_FLAG_MFG_MODE) {
++				if (dhd->is_blob) {
++					err = BCME_ERROR;
++				}
++				goto exit;
++			}
++#else
++			DHD_ERROR(("%s: CLM already exist in F/W, "
++				"new CLM data will be added to the end of existing CLM data!\n",
++				__FUNCTION__));
++#endif /* DHD_BLOB_EXISTENCE_CHECK */
++		}
++
++		/* Found blob file. Download the file */
++		DHD_ERROR(("clm file download from %s \n", clm_blob_path));
++		err = dhd_download_blob(dhd, imgbuf, len, "clmload");
++		if (err) {
++			DHD_ERROR(("%s: CLM download failed err=%d\n", __FUNCTION__, err));
++			/* Retrieve clmload_status and print */
++			bcm_mkiovar("clmload_status", NULL, 0, iovbuf, sizeof(iovbuf));
++			err = dhd_wl_ioctl_cmd(dhd, WLC_GET_VAR, iovbuf, sizeof(iovbuf), FALSE, 0);
++			if (err) {
++				DHD_ERROR(("%s: clmload_status get failed err=%d \n",
++					__FUNCTION__, err));
++			} else {
++				DHD_ERROR(("%s: clmload_status: %d \n",
++					__FUNCTION__, *((int *)iovbuf)));
++				if (*((int *)iovbuf) == CHIPID_MISMATCH) {
++					DHD_ERROR(("Chip ID mismatch error \n"));
++				}
++			}
++			err = BCME_ERROR;
++			goto exit;
++		} else {
++			DHD_INFO(("%s: CLM download succeeded \n", __FUNCTION__));
++		}
++	} else {
++		DHD_INFO(("Skipping the clm download. len:%d memblk:%p \n", len, imgbuf));
++	}
++
++	/* Verify country code */
++	status = dhd_check_current_clm_data(dhd);
++
++	if (status != TRUE) {
++		/* Country code not initialized or CLM download not proper */
++		DHD_ERROR(("country code not initialized\n"));
++		err = BCME_ERROR;
++	}
++exit:
++
++	if (imgbuf) {
++		dhd_os_close_image(imgbuf);
++	}
++
++	return err;
++}
++
++void dhd_free_download_buffer(dhd_pub_t	*dhd, void *buffer, int length)
++{
++#ifdef CACHE_FW_IMAGES
++	return;
++#endif
++	MFREE(dhd->osh, buffer, length);
++}
++
++#if defined(DHD_8021X_DUMP)
++#define EAP_PRINT(x, args...) \
++	do { \
++		if (dump_msg_level & DUMP_EAPOL_VAL) { \
++			printk("[dhd-%s] 802_1X " x " [%s] : (%s) %s (%s)\n", ifname, ## args, \
++			tx?"TX":"RX", tx?seabuf:deabuf, tx?"->":"<-", tx?deabuf:seabuf); \
++		} \
++	} while (0)
++#else
++#define EAP_PRINT(x, args...)
++#endif /* DHD_8021X_DUMP */
++/* Parse EAPOL 4 way handshake messages */
++void
++dhd_dump_eapol_4way_message(dhd_pub_t *dhd, char *ifname,
++	char *dump_data, bool tx)
++{
++	unsigned char type;
++	int pair, ack, mic, kerr, req, sec, install;
++	unsigned short us_tmp, key_len;
++	char seabuf[ETHER_ADDR_STR_LEN]="";
++	char deabuf[ETHER_ADDR_STR_LEN]="";
++
++	bcm_ether_ntoa((struct ether_addr *)dump_data, deabuf);
++	bcm_ether_ntoa((struct ether_addr *)(dump_data+6), seabuf);
++
++	type = dump_data[15];
++	if (type == 0) {
++		if ((dump_data[22] == 1) && (dump_data[18] == 1)) {
++			dhd->conf->eapol_status = EAPOL_STATUS_REQID;
++			EAP_PRINT("Request, Identity");
++		} else if ((dump_data[22] == 1) && (dump_data[18] == 2)) {
++			dhd->conf->eapol_status = EAPOL_STATUS_RSPID;
++			EAP_PRINT("Response, Identity");
++		} else if (dump_data[22] == 254) {
++			if (dump_data[30] == 1) {
++				dhd->conf->eapol_status = EAPOL_STATUS_WSC_START;
++				EAP_PRINT("WSC Start");
++			} else if (dump_data[30] == 4) {
++				if (dump_data[41] == 4) {
++					dhd->conf->eapol_status = EAPOL_STATUS_WPS_M1;
++					EAP_PRINT("WPS M1");
++				} else if (dump_data[41] == 5) {
++					dhd->conf->eapol_status = EAPOL_STATUS_WPS_M2;
++					EAP_PRINT("WPS M2");
++				} else if (dump_data[41] == 7) {
++					dhd->conf->eapol_status = EAPOL_STATUS_WPS_M3;
++					EAP_PRINT("WPS M3");
++				} else if (dump_data[41] == 8) {
++					dhd->conf->eapol_status = EAPOL_STATUS_WPS_M4;
++					EAP_PRINT("WPS M4");
++				} else if (dump_data[41] == 9) {
++					dhd->conf->eapol_status = EAPOL_STATUS_WPS_M5;
++					EAP_PRINT("WPS M5");
++				} else if (dump_data[41] == 10) {
++					dhd->conf->eapol_status = EAPOL_STATUS_WPS_M6;
++					EAP_PRINT("WPS M6");
++				} else if (dump_data[41] == 11) {
++					dhd->conf->eapol_status = EAPOL_STATUS_WPS_M7;
++					EAP_PRINT("WPS M7");
++				} else if (dump_data[41] == 12) {
++					dhd->conf->eapol_status = EAPOL_STATUS_WPS_M8;
++					EAP_PRINT("WPS M8");
++				}
++			} else if (dump_data[30] == 5) {
++				dhd->conf->eapol_status = EAPOL_STATUS_WSC_DONE;
++				EAP_PRINT("WSC Done");
++			}
++		} else {
++			EAP_PRINT("ver %d, type %d, replay %d",
++				dump_data[14], dump_data[15], dump_data[30]);
++		}
++	}
++	else if (type == 3 && dump_data[18] == 2) {
++		us_tmp = (dump_data[19] << 8) | dump_data[20];
++		pair =  0 != (us_tmp & 0x08);
++		ack = 0  != (us_tmp & 0x80);
++		mic = 0  != (us_tmp & 0x100);
++		kerr =  0 != (us_tmp & 0x400);
++		req = 0  != (us_tmp & 0x800);
++		sec = 0  != (us_tmp & 0x200);
++		install  = 0 != (us_tmp & 0x40);
++
++		if (!req && !kerr && !sec && !mic && ack && !install && pair) {
++			dhd->conf->eapol_status = EAPOL_STATUS_4WAY_M1;
++			EAP_PRINT("WPA2 4-way M1(0x%04x)", us_tmp);
++		} else if (!req && !kerr && !sec && mic && !ack && !install && pair) {
++			dhd->conf->eapol_status = EAPOL_STATUS_4WAY_M2;
++			EAP_PRINT("WPA2 4-way M2(0x%04x)", us_tmp);
++		} else if (!req && !kerr && sec && mic && ack && pair) {
++			dhd->conf->eapol_status = EAPOL_STATUS_4WAY_M3;
++			EAP_PRINT("WPA2 4-way M3(0x%04x)", us_tmp);
++		} else if (!req && !kerr && sec && mic && !ack && !install && pair) {
++			dhd->conf->eapol_status = EAPOL_STATUS_4WAY_M4;
++			EAP_PRINT("WPA2 4-way M4(0x%04x)", us_tmp);
++		} else {
++			EAP_PRINT("ver %d, type %d, key_info 0x%x, replay %d",
++				dump_data[14], dump_data[15], us_tmp, dump_data[30]);
++		}
++	}
++	else if (type == 3 && dump_data[18] == 254) {
++		us_tmp = (dump_data[19] << 8) | dump_data[20];
++		req = 0  != (us_tmp & 0x800);
++		kerr = 0 != (us_tmp & 0x400);
++		sec = 0  != (us_tmp & 0x200);
++		mic = 0  != (us_tmp & 0x100);
++		ack = 0  != (us_tmp & 0x80);
++		install = 0 != (us_tmp & 0x40);
++		pair = 0 != (us_tmp & 0x08);
++		key_len = (dump_data[111] << 8) | dump_data[112];
++
++		if (!req && !kerr && !sec && !mic && ack && !install && pair) {
++			dhd->conf->eapol_status = EAPOL_STATUS_4WAY_M1;
++			EAP_PRINT("WPA 4-way M1(0x%04x)", us_tmp);
++		} else if (!req && !kerr && !sec && mic && !ack && !install && pair && key_len) {
++			dhd->conf->eapol_status = EAPOL_STATUS_4WAY_M2;
++			EAP_PRINT("WPA 4-way M2(0x%04x)", us_tmp);
++		} else if (!req && !kerr && !sec && mic && ack && install && pair) {
++			dhd->conf->eapol_status = EAPOL_STATUS_4WAY_M3;
++			EAP_PRINT("WPA 4-way M3(0x%04x)", us_tmp);
++		} else if (!req && !kerr && !sec && mic && !ack && !install && pair) {
++			dhd->conf->eapol_status = EAPOL_STATUS_4WAY_M4;
++			EAP_PRINT("WPA 4-way M4(0x%04x)", us_tmp);
++		} else if (!req && !kerr && sec && mic && ack && !install && !pair) {
++			dhd->conf->eapol_status = EAPOL_STATUS_GROUPKEY_M1;
++			EAP_PRINT("GROUP Key M1(0x%04x)", us_tmp);
++		} else if (!req && !kerr && sec && mic && !ack && !install && !pair) {
++			dhd->conf->eapol_status = EAPOL_STATUS_GROUPKEY_M2;
++			EAP_PRINT("GROUP Key M2(0x%04x)", us_tmp);
++		} else {
++			EAP_PRINT("ver %d, type %d, key_type %d, key_info 0x%x, replay %d",
++				dump_data[14], dump_data[15], dump_data[18], us_tmp, dump_data[30]);
++		}
++	} else {
++		EAP_PRINT("ver %d, type %d, replay %d",
++			dump_data[14], dump_data[15], dump_data[30]);
++	}
++}
++
++#ifdef REPORT_FATAL_TIMEOUTS
++void init_dhd_timeouts(dhd_pub_t *pub)
++{
++	pub->timeout_info = MALLOC(pub->osh, sizeof(timeout_info_t));
++	if (pub->timeout_info == NULL) {
++		DHD_ERROR(("%s: Failed to alloc timeout_info\n", __FUNCTION__));
++	} else {
++		DHD_INFO(("Initializing dhd_timeouts\n"));
++		pub->timeout_info->scan_timer_lock = dhd_os_spin_lock_init(pub->osh);
++		pub->timeout_info->join_timer_lock = dhd_os_spin_lock_init(pub->osh);
++		pub->timeout_info->bus_timer_lock = dhd_os_spin_lock_init(pub->osh);
++		pub->timeout_info->cmd_timer_lock = dhd_os_spin_lock_init(pub->osh);
++		pub->timeout_info->scan_timeout_val = SCAN_TIMEOUT_DEFAULT;
++		pub->timeout_info->join_timeout_val = JOIN_TIMEOUT_DEFAULT;
++		pub->timeout_info->cmd_timeout_val = CMD_TIMEOUT_DEFAULT;
++		pub->timeout_info->bus_timeout_val = BUS_TIMEOUT_DEFAULT;
++		pub->timeout_info->scan_timer_active = FALSE;
++		pub->timeout_info->join_timer_active = FALSE;
++		pub->timeout_info->cmd_timer_active = FALSE;
++		pub->timeout_info->bus_timer_active = FALSE;
++		pub->timeout_info->cmd_join_error = WLC_SSID_MASK;
++		pub->timeout_info->cmd_request_id = 0;
++	}
++}
++
++void
++deinit_dhd_timeouts(dhd_pub_t *pub)
++{
++	/* stop the join, scan bus, cmd timers
++	* as failing to do so may cause a kernel panic if
++	* an rmmod is done
++	*/
++	if (!pub->timeout_info) {
++		DHD_ERROR(("timeout_info pointer is NULL\n"));
++		ASSERT(0);
++		return;
++	}
++	if (dhd_stop_scan_timer(pub)) {
++		DHD_ERROR(("dhd_stop_scan_timer failed\n"));
++		ASSERT(0);
++	}
++	if (dhd_stop_bus_timer(pub)) {
++		DHD_ERROR(("dhd_stop_bus_timer failed\n"));
++		ASSERT(0);
++	}
++	if (dhd_stop_cmd_timer(pub)) {
++		DHD_ERROR(("dhd_stop_cmd_timer failed\n"));
++		ASSERT(0);
++	}
++	if (dhd_stop_join_timer(pub)) {
++		DHD_ERROR(("dhd_stop_join_timer failed\n"));
++		ASSERT(0);
++	}
++
++	dhd_os_spin_lock_deinit(pub->osh, pub->timeout_info->scan_timer_lock);
++	dhd_os_spin_lock_deinit(pub->osh, pub->timeout_info->join_timer_lock);
++	dhd_os_spin_lock_deinit(pub->osh, pub->timeout_info->bus_timer_lock);
++	dhd_os_spin_lock_deinit(pub->osh, pub->timeout_info->cmd_timer_lock);
++	MFREE(pub->osh, pub->timeout_info, sizeof(timeout_info_t));
++	pub->timeout_info = NULL;
++}
++
++static void
++dhd_cmd_timeout(void *ctx)
++{
++	dhd_pub_t *pub = (dhd_pub_t *)ctx;
++	unsigned long flags;
++
++	if (!pub->timeout_info) {
++		DHD_ERROR(("DHD: timeout_info NULL\n"));
++		ASSERT(0);
++		return;
++	}
++
++	DHD_TIMER_LOCK(pub->timeout_info->cmd_timer_lock, flags);
++	if (pub->timeout_info && pub->timeout_info->cmd_timer_active) {
++		DHD_ERROR(("\nERROR COMMAND TIMEOUT TO:%d\n", pub->timeout_info->cmd_timeout_val));
++		DHD_TIMER_UNLOCK(pub->timeout_info->cmd_timer_lock, flags);
++#ifdef PCIE_OOB
++		/* Assert device_wake so that UART_Rx is available */
++		if (dhd_bus_set_device_wake(pub->bus, TRUE)) {
++			DHD_ERROR(("%s: dhd_bus_set_device_wake() failed\n", __FUNCTION__));
++			ASSERT(0);
++		}
++#endif /* PCIE_OOB */
++		if (dhd_stop_cmd_timer(pub)) {
++			DHD_ERROR(("%s: dhd_stop_cmd_timer() failed\n", __FUNCTION__));
++			ASSERT(0);
++		}
++		dhd_wakeup_ioctl_event(pub, IOCTL_RETURN_ON_ERROR);
++		if (!dhd_query_bus_erros(pub))
++			dhd_send_trap_to_fw_for_timeout(pub, DHD_REASON_COMMAND_TO);
++	} else {
++		DHD_TIMER_UNLOCK(pub->timeout_info->cmd_timer_lock, flags);
++	}
++}
++
++int
++dhd_start_cmd_timer(dhd_pub_t *pub)
++{
++	int ret = BCME_OK;
++	unsigned long flags = 0;
++	uint32 cmd_to_ms;
++
++	if (!pub->timeout_info) {
++		DHD_ERROR(("DHD: timeout_info NULL\n"));
++		ret = BCME_ERROR;
++		ASSERT(0);
++		goto exit_null;
++	}
++	DHD_TIMER_LOCK(pub->timeout_info->cmd_timer_lock, flags);
++	cmd_to_ms = pub->timeout_info->cmd_timeout_val;
++
++	if (pub->timeout_info->cmd_timeout_val == 0) {
++		/* Disable Command timer timeout */
++		DHD_INFO(("DHD: Command Timeout Disabled\n"));
++		goto exit;
++	}
++	if (pub->timeout_info->cmd_timer_active) {
++		DHD_ERROR(("%s:Timer already active\n", __FUNCTION__));
++		ret = BCME_ERROR;
++		ASSERT(0);
++	} else {
++		pub->timeout_info->cmd_timer = osl_timer_init(pub->osh,
++			"cmd_timer", dhd_cmd_timeout, pub);
++		osl_timer_update(pub->osh, pub->timeout_info->cmd_timer,
++			cmd_to_ms, 0);
++		pub->timeout_info->cmd_timer_active = TRUE;
++	}
++	if (ret == BCME_OK) {
++		DHD_INFO(("%s Cmd Timer started\n", __FUNCTION__));
++	}
++exit:
++	DHD_TIMER_UNLOCK(pub->timeout_info->cmd_timer_lock, flags);
++exit_null:
++	return ret;
++}
++
++int
++dhd_stop_cmd_timer(dhd_pub_t *pub)
++{
++	int ret = BCME_OK;
++	unsigned long flags = 0;
++
++	if (!pub->timeout_info) {
++		DHD_ERROR(("DHD: timeout_info NULL\n"));
++		ret = BCME_ERROR;
++		ASSERT(0);
++		goto exit;
++	}
++	DHD_TIMER_LOCK(pub->timeout_info->cmd_timer_lock, flags);
++
++	if (pub->timeout_info->cmd_timer_active) {
++		osl_timer_del(pub->osh, pub->timeout_info->cmd_timer);
++		pub->timeout_info->cmd_timer_active = FALSE;
++	}
++	else {
++		DHD_INFO(("DHD: CMD timer is not active\n"));
++	}
++	if (ret == BCME_OK) {
++		DHD_INFO(("%s Cmd Timer Stopped\n", __FUNCTION__));
++	}
++	DHD_TIMER_UNLOCK(pub->timeout_info->cmd_timer_lock, flags);
++exit:
++	return ret;
++}
++
++static int
++__dhd_stop_join_timer(dhd_pub_t *pub)
++{
++	int ret = BCME_OK;
++	if (!pub->timeout_info) {
++		DHD_ERROR(("DHD: timeout_info NULL\n"));
++		ASSERT(0);
++		return BCME_ERROR;
++	}
++
++	if (pub->timeout_info->join_timer_active) {
++		osl_timer_del(pub->osh, pub->timeout_info->join_timer);
++		pub->timeout_info->join_timer_active = FALSE;
++	} else {
++		DHD_INFO(("DHD: JOIN timer is not active\n"));
++	}
++	if (ret == BCME_OK) {
++		DHD_INFO(("%s: Join Timer Stopped\n", __FUNCTION__));
++	}
++	return ret;
++}
++
++static void
++dhd_join_timeout(void *ctx)
++{
++	dhd_pub_t *pub = (dhd_pub_t *)ctx;
++	unsigned long flags;
++
++	if (!pub->timeout_info) {
++		DHD_ERROR(("DHD: timeout_info NULL\n"));
++		ASSERT(0);
++		return;
++	}
++
++	DHD_TIMER_LOCK(pub->timeout_info->join_timer_lock, flags);
++	if (pub->timeout_info->join_timer_active) {
++		DHD_TIMER_UNLOCK(pub->timeout_info->join_timer_lock, flags);
++		if (dhd_stop_join_timer(pub)) {
++			DHD_ERROR(("%s: dhd_stop_join_timer() failed\n", __FUNCTION__));
++			ASSERT(0);
++		}
++		if (pub->timeout_info->cmd_join_error) {
++			DHD_ERROR(("\nERROR JOIN TIMEOUT TO:%d:0x%x\n",
++				pub->timeout_info->join_timeout_val,
++				pub->timeout_info->cmd_join_error));
++#ifdef DHD_FW_COREDUMP
++				/* collect core dump and crash */
++				pub->memdump_enabled = DUMP_MEMFILE_BUGON;
++				pub->memdump_type = DUMP_TYPE_JOIN_TIMEOUT;
++				dhd_bus_mem_dump(pub);
++#endif /* DHD_FW_COREDUMP */
++
++		}
++	} else {
++		DHD_TIMER_UNLOCK(pub->timeout_info->join_timer_lock, flags);
++	}
++}
++
++int
++dhd_start_join_timer(dhd_pub_t *pub)
++{
++	int ret = BCME_OK;
++	unsigned long flags = 0;
++	uint32 join_to_ms;
++
++	if (!pub->timeout_info) {
++		DHD_ERROR(("DHD: timeout_info NULL\n"));
++		ret = BCME_ERROR;
++		ASSERT(0);
++		goto exit;
++	}
++
++	join_to_ms = pub->timeout_info->join_timeout_val;
++	DHD_TIMER_LOCK(pub->timeout_info->join_timer_lock, flags);
++	if (pub->timeout_info->join_timer_active) {
++		DHD_ERROR(("%s:Stoping active timer\n", __FUNCTION__));
++		__dhd_stop_join_timer(pub);
++	}
++	if (pub->timeout_info->join_timeout_val == 0) {
++		/* Disable Join timer timeout */
++		DHD_INFO(("DHD: Join Timeout Disabled\n"));
++	} else {
++		pub->timeout_info->join_timer = osl_timer_init(pub->osh,
++			"join_timer", dhd_join_timeout, pub);
++		osl_timer_update(pub->osh, pub->timeout_info->join_timer, join_to_ms, 0);
++		pub->timeout_info->join_timer_active = TRUE;
++		pub->timeout_info->cmd_join_error |= WLC_SSID_MASK;
++	}
++	if (ret == BCME_OK) {
++		DHD_INFO(("%s:Join Timer started 0x%x\n", __FUNCTION__,
++			pub->timeout_info->cmd_join_error));
++	}
++	DHD_TIMER_UNLOCK(pub->timeout_info->join_timer_lock, flags);
++exit:
++	return ret;
++}
++
++int
++dhd_stop_join_timer(dhd_pub_t *pub)
++{
++	int ret = BCME_OK;
++	unsigned long flags;
++
++	DHD_TIMER_LOCK(pub->timeout_info->join_timer_lock, flags);
++	ret = __dhd_stop_join_timer(pub);
++	DHD_TIMER_UNLOCK(pub->timeout_info->join_timer_lock, flags);
++	return ret;
++}
++
++static void
++dhd_scan_timeout(void *ctx)
++{
++	dhd_pub_t *pub = (dhd_pub_t *)ctx;
++	unsigned long flags;
++
++	 if (pub->timeout_info == NULL) {
++		DHD_ERROR(("timeout_info pointer is NULL\n"));
++		ASSERT(0);
++		return;
++	 }
++
++	DHD_TIMER_LOCK(pub->timeout_info->scan_timer_lock, flags);
++	if (pub->timeout_info && pub->timeout_info->scan_timer_active) {
++		DHD_ERROR(("\nERROR SCAN TIMEOUT TO:%d\n", pub->timeout_info->scan_timeout_val));
++		DHD_TIMER_UNLOCK(pub->timeout_info->scan_timer_lock, flags);
++		dhd_stop_scan_timer(pub);
++		if (!dhd_query_bus_erros(pub))
++			dhd_send_trap_to_fw_for_timeout(pub, DHD_REASON_SCAN_TO);
++	} else {
++		DHD_TIMER_UNLOCK(pub->timeout_info->scan_timer_lock, flags);
++	}
++}
++
++int
++dhd_start_scan_timer(dhd_pub_t *pub)
++{
++	int ret = BCME_OK;
++	unsigned long flags = 0;
++	uint32 scan_to_ms;
++
++	if (!pub->timeout_info) {
++		DHD_ERROR(("DHD: timeout_info NULL\n"));
++		ret = BCME_ERROR;
++		ASSERT(0);
++		goto exit_null;
++	}
++	DHD_TIMER_LOCK(pub->timeout_info->scan_timer_lock, flags);
++	scan_to_ms = pub->timeout_info->scan_timeout_val;
++
++	if (pub->timeout_info->scan_timer_active) {
++		/* NOTE : New scan timeout value will be effective
++		 * only once current scan is completed.
++		 */
++		DHD_ERROR(("%s:Timer already active\n", __FUNCTION__));
++		ret = BCME_ERROR;
++		goto exit;
++	}
++
++	if (pub->timeout_info->scan_timeout_val == 0) {
++		/* Disable Scan timer timeout */
++		DHD_INFO(("DHD: Scan Timeout Disabled\n"));
++	} else {
++		pub->timeout_info->scan_timer = osl_timer_init(pub->osh, "scan_timer",
++			dhd_scan_timeout, pub);
++		pub->timeout_info->scan_timer_active = TRUE;
++		osl_timer_update(pub->osh, pub->timeout_info->scan_timer, scan_to_ms, 0);
++	}
++	if (ret == BCME_OK) {
++		DHD_INFO(("%s Scan Timer started\n", __FUNCTION__));
++	}
++exit:
++	DHD_TIMER_UNLOCK(pub->timeout_info->scan_timer_lock, flags);
++exit_null:
++	return ret;
++}
++
++int
++dhd_stop_scan_timer(dhd_pub_t *pub)
++{
++	int ret = BCME_OK;
++	unsigned long flags = 0;
++
++	if (!pub->timeout_info) {
++		DHD_ERROR(("DHD: timeout_info NULL\n"));
++		ret = BCME_ERROR;
++		ASSERT(0);
++		goto exit;
++	}
++	DHD_TIMER_LOCK(pub->timeout_info->scan_timer_lock, flags);
++
++	if (pub->timeout_info->scan_timer_active) {
++		osl_timer_del(pub->osh, pub->timeout_info->scan_timer);
++		pub->timeout_info->scan_timer_active = FALSE;
++	}
++	else {
++		DHD_INFO(("DHD: SCAN timer is not active\n"));
++	}
++
++	if (ret == BCME_OK) {
++		DHD_INFO(("%s Scan Timer Stopped\n", __FUNCTION__));
++	}
++	DHD_TIMER_UNLOCK(pub->timeout_info->scan_timer_lock, flags);
++exit:
++	return ret;
++}
++
++static void
++dhd_bus_timeout(void *ctx)
++{
++	dhd_pub_t *pub = (dhd_pub_t *)ctx;
++	unsigned long flags;
++
++	if (pub->timeout_info == NULL) {
++		DHD_ERROR(("timeout_info pointer is NULL\n"));
++		ASSERT(0);
++		return;
++	}
++
++	DHD_TIMER_LOCK(pub->timeout_info->bus_timer_lock, flags);
++	if (pub->timeout_info->bus_timer_active) {
++		DHD_ERROR(("\nERROR BUS TIMEOUT TO:%d\n", pub->timeout_info->bus_timeout_val));
++		DHD_TIMER_UNLOCK(pub->timeout_info->bus_timer_lock, flags);
++#ifdef PCIE_OOB
++		/* Assert device_wake so that UART_Rx is available */
++		if (dhd_bus_set_device_wake(pub->bus, TRUE)) {
++			DHD_ERROR(("%s: dhd_bus_set_device_wake() failed\n", __FUNCTION__));
++			ASSERT(0);
++		}
++#endif /* PCIE_OOB */
++		if (dhd_stop_bus_timer(pub)) {
++			DHD_ERROR(("%s: dhd_stop_bus_timer() failed\n", __FUNCTION__));
++			ASSERT(0);
++		}
++		if (!dhd_query_bus_erros(pub))
++			dhd_send_trap_to_fw_for_timeout(pub, DHD_REASON_OQS_TO);
++	} else {
++		DHD_TIMER_UNLOCK(pub->timeout_info->bus_timer_lock, flags);
++	}
++}
++
++int
++dhd_start_bus_timer(dhd_pub_t *pub)
++{
++	int ret = BCME_OK;
++	unsigned long flags = 0;
++	uint32 bus_to_ms;
++
++	if (!pub->timeout_info) {
++		DHD_ERROR(("DHD: timeout_info NULL\n"));
++		ret = BCME_ERROR;
++		ASSERT(0);
++		goto exit_null;
++	}
++	DHD_TIMER_LOCK(pub->timeout_info->bus_timer_lock, flags);
++	bus_to_ms = pub->timeout_info->bus_timeout_val;
++
++	if (pub->timeout_info->bus_timeout_val == 0) {
++		/* Disable Bus timer timeout */
++		DHD_INFO(("DHD: Bus Timeout Disabled\n"));
++		goto exit;
++	}
++	if (pub->timeout_info->bus_timer_active) {
++		DHD_ERROR(("%s:Timer already active\n", __FUNCTION__));
++		ret = BCME_ERROR;
++		ASSERT(0);
++	} else {
++		pub->timeout_info->bus_timer = osl_timer_init(pub->osh,
++			"bus_timer", dhd_bus_timeout, pub);
++		pub->timeout_info->bus_timer_active = TRUE;
++		osl_timer_update(pub->osh, pub->timeout_info->bus_timer, bus_to_ms, 0);
++	}
++	if (ret == BCME_OK) {
++		DHD_INFO(("%s: BUS Timer started\n", __FUNCTION__));
++	}
++exit:
++	DHD_TIMER_UNLOCK(pub->timeout_info->bus_timer_lock, flags);
++exit_null:
++	return ret;
++}
++
++int
++dhd_stop_bus_timer(dhd_pub_t *pub)
++{
++	int ret = BCME_OK;
++	unsigned long flags = 0;
++
++	if (!pub->timeout_info) {
++		DHD_ERROR(("DHD: timeout_info NULL\n"));
++		ret = BCME_ERROR;
++		ASSERT(0);
++		goto exit;
++	}
++	DHD_TIMER_LOCK(pub->timeout_info->bus_timer_lock, flags);
++
++	if (pub->timeout_info->bus_timer_active) {
++		osl_timer_del(pub->osh, pub->timeout_info->bus_timer);
++		pub->timeout_info->bus_timer_active = FALSE;
++	}
++	else {
++		DHD_INFO(("DHD: BUS timer is not active\n"));
++	}
++	if (ret == BCME_OK) {
++		DHD_INFO(("%s: Bus Timer Stopped\n", __FUNCTION__));
++	}
++	DHD_TIMER_UNLOCK(pub->timeout_info->bus_timer_lock, flags);
++exit:
++	return ret;
++}
++
++int
++dhd_set_request_id(dhd_pub_t *pub, uint16 id, uint32 cmd)
++{
++	DHD_INFO(("%s: id:%d\n", __FUNCTION__, id));
++	if (pub->timeout_info) {
++		pub->timeout_info->cmd_request_id = id;
++		pub->timeout_info->cmd = cmd;
++		return BCME_OK;
++	} else {
++		return BCME_ERROR;
++	}
++}
++
++uint16
++dhd_get_request_id(dhd_pub_t *pub)
++{
++	if (pub->timeout_info) {
++		return (pub->timeout_info->cmd_request_id);
++	} else {
++		return 0;
++	}
++}
++
++void
++dhd_set_join_error(dhd_pub_t *pub, uint32 mask)
++{
++	DHD_INFO(("Setting join Error %d\n", mask));
++	if (pub->timeout_info) {
++		pub->timeout_info->cmd_join_error |= mask;
++	}
++}
++
++void
++dhd_clear_join_error(dhd_pub_t *pub, uint32 mask)
++{
++	DHD_INFO(("clear join Error %d\n", mask));
++	if (pub->timeout_info) {
++		pub->timeout_info->cmd_join_error &= ~mask;
++	}
++}
++
++void
++dhd_get_scan_to_val(dhd_pub_t *pub, uint32 *to_val)
++{
++	if (pub->timeout_info) {
++		*to_val = pub->timeout_info->scan_timeout_val;
++	} else {
++		*to_val = 0;
++	}
++}
++
++void
++dhd_set_scan_to_val(dhd_pub_t *pub, uint32 to_val)
++{
++	if (pub->timeout_info) {
++		DHD_INFO(("Setting TO val:%d\n", to_val));
++		pub->timeout_info->scan_timeout_val = to_val;
++	}
++}
++
++void
++dhd_get_join_to_val(dhd_pub_t *pub, uint32 *to_val)
++{
++	if (pub->timeout_info) {
++		*to_val = pub->timeout_info->join_timeout_val;
++	} else {
++		*to_val = 0;
++	}
++}
++
++void
++dhd_set_join_to_val(dhd_pub_t *pub, uint32 to_val)
++{
++	if (pub->timeout_info) {
++		DHD_INFO(("Setting TO val:%d\n", to_val));
++		pub->timeout_info->join_timeout_val = to_val;
++	}
++}
++
++void
++dhd_get_cmd_to_val(dhd_pub_t *pub, uint32 *to_val)
++{
++	if (pub->timeout_info) {
++		*to_val = pub->timeout_info->cmd_timeout_val;
++	} else {
++		*to_val = 0;
++	}
++}
++
++void
++dhd_set_cmd_to_val(dhd_pub_t *pub, uint32 to_val)
++{
++	if (pub->timeout_info) {
++		DHD_INFO(("Setting TO val:%d\n", to_val));
++		pub->timeout_info->cmd_timeout_val = to_val;
++	}
++}
++
++void
++dhd_get_bus_to_val(dhd_pub_t *pub, uint32 *to_val)
++{
++	if (pub->timeout_info) {
++		*to_val = pub->timeout_info->bus_timeout_val;
++	} else {
++		*to_val = 0;
++	}
++}
++
++void
++dhd_set_bus_to_val(dhd_pub_t *pub, uint32 to_val)
++{
++	if (pub->timeout_info) {
++		DHD_INFO(("Setting TO val:%d\n", to_val));
++		pub->timeout_info->bus_timeout_val = to_val;
++	}
++}
++#endif /* REPORT_FATAL_TIMEOUTS */
++
++#ifdef SHOW_LOGTRACE
++int
++dhd_parse_logstrs_file(osl_t *osh, char *raw_fmts, int logstrs_size,
++		dhd_event_log_t *event_log)
++{
++	logstr_header_t *hdr = NULL;
++	uint32 *lognums = NULL;
++	char *logstrs = NULL;
++	int ram_index = 0;
++	char **fmts;
++	int num_fmts = 0;
++	int32 i = 0;
++
++	/* Remember header from the logstrs.bin file */
++	hdr = (logstr_header_t *) (raw_fmts + logstrs_size -
++		sizeof(logstr_header_t));
++
++	if (hdr->log_magic == LOGSTRS_MAGIC) {
++		/*
++		* logstrs.bin start with header.
++		*/
++		num_fmts =	hdr->rom_logstrs_offset / sizeof(uint32);
++		ram_index = (hdr->ram_lognums_offset -
++			hdr->rom_lognums_offset) / sizeof(uint32);
++		lognums = (uint32 *) &raw_fmts[hdr->rom_lognums_offset];
++		logstrs = (char *)	 &raw_fmts[hdr->rom_logstrs_offset];
++	} else {
++		/*
++		 * Legacy logstrs.bin format without header.
++		 */
++		num_fmts = *((uint32 *) (raw_fmts)) / sizeof(uint32);
++		if (num_fmts == 0) {
++			/* Legacy ROM/RAM logstrs.bin format:
++			  *  - ROM 'lognums' section
++			  *   - RAM 'lognums' section
++			  *   - ROM 'logstrs' section.
++			  *   - RAM 'logstrs' section.
++			  *
++			  * 'lognums' is an array of indexes for the strings in the
++			  * 'logstrs' section. The first uint32 is 0 (index of first
++			  * string in ROM 'logstrs' section).
++			  *
++			  * The 4324b5 is the only ROM that uses this legacy format. Use the
++			  * fixed number of ROM fmtnums to find the start of the RAM
++			  * 'lognums' section. Use the fixed first ROM string ("Con\n") to
++			  * find the ROM 'logstrs' section.
++			  */
++			#define NUM_4324B5_ROM_FMTS	186
++			#define FIRST_4324B5_ROM_LOGSTR "Con\n"
++			ram_index = NUM_4324B5_ROM_FMTS;
++			lognums = (uint32 *) raw_fmts;
++			num_fmts =	ram_index;
++			logstrs = (char *) &raw_fmts[num_fmts << 2];
++			while (strncmp(FIRST_4324B5_ROM_LOGSTR, logstrs, 4)) {
++				num_fmts++;
++				logstrs = (char *) &raw_fmts[num_fmts << 2];
++			}
++		} else {
++				/* Legacy RAM-only logstrs.bin format:
++				 *	  - RAM 'lognums' section
++				 *	  - RAM 'logstrs' section.
++				 *
++				 * 'lognums' is an array of indexes for the strings in the
++				 * 'logstrs' section. The first uint32 is an index to the
++				 * start of 'logstrs'. Therefore, if this index is divided
++				 * by 'sizeof(uint32)' it provides the number of logstr
++				 *	entries.
++				 */
++				ram_index = 0;
++				lognums = (uint32 *) raw_fmts;
++				logstrs = (char *)	&raw_fmts[num_fmts << 2];
++			}
++	}
++	fmts = MALLOC(osh, num_fmts  * sizeof(char *));
++	if (fmts == NULL) {
++		DHD_ERROR(("%s: Failed to allocate fmts memory\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++	event_log->fmts_size = num_fmts  * sizeof(char *);
++
++	for (i = 0; i < num_fmts; i++) {
++		/* ROM lognums index into logstrs using 'rom_logstrs_offset' as a base
++		* (they are 0-indexed relative to 'rom_logstrs_offset').
++		*
++		* RAM lognums are already indexed to point to the correct RAM logstrs (they
++		* are 0-indexed relative to the start of the logstrs.bin file).
++		*/
++		if (i == ram_index) {
++			logstrs = raw_fmts;
++		}
++		fmts[i] = &logstrs[lognums[i]];
++	}
++	event_log->fmts = fmts;
++	event_log->raw_fmts_size = logstrs_size;
++	event_log->raw_fmts = raw_fmts;
++	event_log->num_fmts = num_fmts;
++
++	return BCME_OK;
++}
++
++int dhd_parse_map_file(osl_t *osh, void *file, uint32 *ramstart, uint32 *rodata_start,
++		uint32 *rodata_end)
++{
++	char *raw_fmts =  NULL;
++	uint32 read_size = READ_NUM_BYTES;
++	int error = 0;
++	char * cptr = NULL;
++	char c;
++	uint8 count = 0;
++
++	*ramstart = 0;
++	*rodata_start = 0;
++	*rodata_end = 0;
++
++	/* Allocate 1 byte more than read_size to terminate it with NULL */
++	raw_fmts = MALLOC(osh, read_size + 1);
++	if (raw_fmts == NULL) {
++		DHD_ERROR(("%s: Failed to allocate raw_fmts memory \n", __FUNCTION__));
++		goto fail;
++	}
++
++	/* read ram start, rodata_start and rodata_end values from map  file */
++	while (count != ALL_MAP_VAL)
++	{
++		error = dhd_os_read_file(file, raw_fmts, read_size);
++		if (error < 0) {
++			DHD_ERROR(("%s: map file read failed err:%d \n", __FUNCTION__,
++					error));
++			goto fail;
++		}
++
++		/* End raw_fmts with NULL as strstr expects NULL terminated strings */
++		raw_fmts[read_size] = '\0';
++
++		/* Get ramstart address */
++		if ((cptr = strstr(raw_fmts, ramstart_str))) {
++			cptr = cptr - BYTES_AHEAD_NUM;
++			sscanf(cptr, "%x %c text_start", ramstart, &c);
++			count |= RAMSTART_BIT;
++		}
++
++		/* Get ram rodata start address */
++		if ((cptr = strstr(raw_fmts, rodata_start_str))) {
++			cptr = cptr - BYTES_AHEAD_NUM;
++			sscanf(cptr, "%x %c rodata_start", rodata_start, &c);
++			count |= RDSTART_BIT;
++		}
++
++		/* Get ram rodata end address */
++		if ((cptr = strstr(raw_fmts, rodata_end_str))) {
++			cptr = cptr - BYTES_AHEAD_NUM;
++			sscanf(cptr, "%x %c rodata_end", rodata_end, &c);
++			count |= RDEND_BIT;
++		}
++
++		if (error < (int)read_size) {
++			/*
++			* since we reset file pos back to earlier pos by
++			* GO_BACK_FILE_POS_NUM_BYTES bytes we won't reach EOF.
++			* The reason for this is if string is spreaded across
++			* bytes, the read function should not miss it.
++			* So if ret value is less than read_size, reached EOF don't read further
++			*/
++			break;
++		}
++		memset(raw_fmts, 0, read_size);
++		/*
++		* go back to predefined NUM of bytes so that we won't miss
++		* the string and  addr even if it comes as splited in next read.
++		*/
++		dhd_os_seek_file(file, -GO_BACK_FILE_POS_NUM_BYTES);
++	}
++
++
++fail:
++	if (raw_fmts) {
++		MFREE(osh, raw_fmts, read_size + 1);
++		raw_fmts = NULL;
++	}
++	if (count == ALL_MAP_VAL)
++		return BCME_OK;
++	else {
++		DHD_ERROR(("%s: readmap error 0X%x \n", __FUNCTION__,
++				count));
++		return BCME_ERROR;
++	}
++
++}
++
++#ifdef PCIE_FULL_DONGLE
++int
++dhd_event_logtrace_infobuf_pkt_process(dhd_pub_t *dhdp, void *pktbuf,
++		dhd_event_log_t *event_data)
++{
++	uint32 infobuf_version;
++	info_buf_payload_hdr_t *payload_hdr_ptr;
++	uint16 payload_hdr_type;
++	uint16 payload_hdr_length;
++
++	DHD_TRACE(("%s:Enter\n", __FUNCTION__));
++
++	if (PKTLEN(dhdp->osh, pktbuf) < sizeof(uint32)) {
++		DHD_ERROR(("%s: infobuf too small for version field\n",
++			__FUNCTION__));
++		goto exit;
++	}
++	infobuf_version = *((uint32 *)PKTDATA(dhdp->osh, pktbuf));
++	PKTPULL(dhdp->osh, pktbuf, sizeof(uint32));
++	if (infobuf_version != PCIE_INFOBUF_V1) {
++		DHD_ERROR(("%s: infobuf version %d is not PCIE_INFOBUF_V1\n",
++			__FUNCTION__, infobuf_version));
++		goto exit;
++	}
++
++	/* Version 1 infobuf has a single type/length (and then value) field */
++	if (PKTLEN(dhdp->osh, pktbuf) < sizeof(info_buf_payload_hdr_t)) {
++		DHD_ERROR(("%s: infobuf too small for v1 type/length  fields\n",
++			__FUNCTION__));
++		goto exit;
++	}
++	/* Process/parse the common info payload header (type/length) */
++	payload_hdr_ptr = (info_buf_payload_hdr_t *)PKTDATA(dhdp->osh, pktbuf);
++	payload_hdr_type = ltoh16(payload_hdr_ptr->type);
++	payload_hdr_length = ltoh16(payload_hdr_ptr->length);
++	if (payload_hdr_type != PCIE_INFOBUF_V1_TYPE_LOGTRACE) {
++		DHD_ERROR(("%s: payload_hdr_type %d is not V1_TYPE_LOGTRACE\n",
++			__FUNCTION__, payload_hdr_type));
++		goto exit;
++	}
++	PKTPULL(dhdp->osh, pktbuf, sizeof(info_buf_payload_hdr_t));
++
++	/* Validate that the specified length isn't bigger than the
++	 * provided data.
++	 */
++	if (payload_hdr_length > PKTLEN(dhdp->osh, pktbuf)) {
++		DHD_ERROR(("%s: infobuf logtrace length is bigger"
++			" than actual buffer data\n", __FUNCTION__));
++		goto exit;
++	}
++	dhd_dbg_trace_evnt_handler(dhdp, PKTDATA(dhdp->osh, pktbuf),
++		event_data, payload_hdr_length);
++
++	return BCME_OK;
++
++exit:
++	return BCME_ERROR;
++}
++#endif /* PCIE_FULL_DONGLE */
++#endif /* SHOW_LOGTRACE */
++
++#if defined(WLTDLS) && defined(PCIE_FULL_DONGLE)
++
++/* To handle the TDLS event in the dhd_common.c
++ */
++int dhd_tdls_event_handler(dhd_pub_t *dhd_pub, wl_event_msg_t *event)
++{
++	int ret = BCME_OK;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	ret = dhd_tdls_update_peer_info(dhd_pub, event);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	return ret;
++}
++
++int dhd_free_tdls_peer_list(dhd_pub_t *dhd_pub)
++{
++	tdls_peer_node_t *cur = NULL, *prev = NULL;
++	if (!dhd_pub)
++		return BCME_ERROR;
++	cur = dhd_pub->peer_tbl.node;
++
++	if ((dhd_pub->peer_tbl.node == NULL) && !dhd_pub->peer_tbl.tdls_peer_count)
++		return BCME_ERROR;
++
++	while (cur != NULL) {
++		prev = cur;
++		cur = cur->next;
++		MFREE(dhd_pub->osh, prev, sizeof(tdls_peer_node_t));
++	}
++	dhd_pub->peer_tbl.tdls_peer_count = 0;
++	dhd_pub->peer_tbl.node = NULL;
++	return BCME_OK;
++}
++#endif	/* #if defined(WLTDLS) && defined(PCIE_FULL_DONGLE) */
++
++#ifdef DUMP_IOCTL_IOV_LIST
++void
++dhd_iov_li_append(dhd_pub_t *dhd, dll_t *list_head, dll_t *node)
++{
++	dll_t *item;
++	dhd_iov_li_t *iov_li;
++	dhd->dump_iovlist_len++;
++
++	if (dhd->dump_iovlist_len == IOV_LIST_MAX_LEN+1) {
++		item = dll_head_p(list_head);
++		iov_li = (dhd_iov_li_t *)CONTAINEROF(item, dhd_iov_li_t, list);
++		dll_delete(item);
++		MFREE(dhd->osh, iov_li, sizeof(*iov_li));
++		dhd->dump_iovlist_len--;
++	}
++	dll_append(list_head, node);
++}
++
++void
++dhd_iov_li_print(dll_t *list_head)
++{
++	dhd_iov_li_t *iov_li;
++	dll_t *item, *next;
++	uint8 index = 0;
++	for (item = dll_head_p(list_head); !dll_end(list_head, item); item = next) {
++		next = dll_next_p(item);
++		iov_li = (dhd_iov_li_t *)CONTAINEROF(item, dhd_iov_li_t, list);
++		index++;
++		DHD_ERROR(("%d:cmd_name = %s, cmd = %d.\n", index, iov_li->buff, iov_li->cmd));
++	}
++}
++
++void
++dhd_iov_li_delete(dhd_pub_t *dhd, dll_t *list_head)
++{
++	dll_t *item;
++	dhd_iov_li_t *iov_li;
++	while (!(dll_empty(list_head))) {
++		item = dll_head_p(list_head);
++		iov_li = (dhd_iov_li_t *)CONTAINEROF(item, dhd_iov_li_t, list);
++		dll_delete(item);
++		MFREE(dhd->osh, iov_li, sizeof(*iov_li));
++	}
++}
++#endif /* DUMP_IOCTL_IOV_LIST */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_config.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_config.c
+new file mode 100644
+index 000000000..af05a3f6d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_config.c
+@@ -0,0 +1,3851 @@
++
++#include <typedefs.h>
++#include <osl.h>
++
++#include <bcmendian.h>
++#include <bcmutils.h>
++#include <hndsoc.h>
++#include <bcmsdbus.h>
++#if defined(HW_OOB) || defined(FORCE_WOWLAN)
++#include <bcmdefs.h>
++#include <bcmsdh.h>
++#include <sdio.h>
++#include <sbchipc.h>
++#endif
++#ifdef WL_CFG80211
++#include <wl_cfg80211.h>
++#endif
++
++#include <dhd_config.h>
++#include <dhd_dbg.h>
++#include <wl_android.h>
++
++/* message levels */
++#define CONFIG_ERROR_LEVEL	(1 << 0)
++#define CONFIG_TRACE_LEVEL	(1 << 1)
++#define CONFIG_MSG_LEVEL	(1 << 0)
++
++uint config_msg_level = CONFIG_ERROR_LEVEL | CONFIG_MSG_LEVEL;
++uint dump_msg_level = 0;
++
++#define CONFIG_MSG(x, args...) \
++	do { \
++		if (config_msg_level & CONFIG_MSG_LEVEL) { \
++			printk(KERN_ERR "[dhd] %s : " x, __func__, ## args); \
++		} \
++	} while (0)
++#define CONFIG_ERROR(x, args...) \
++	do { \
++		if (config_msg_level & CONFIG_ERROR_LEVEL) { \
++			printk(KERN_ERR "[dhd] CONFIG-ERROR) %s : " x, __func__, ## args); \
++		} \
++	} while (0)
++#define CONFIG_TRACE(x, args...) \
++	do { \
++		if (config_msg_level & CONFIG_TRACE_LEVEL) { \
++			printk(KERN_INFO "[dhd] CONFIG-TRACE) %s : " x, __func__, ## args); \
++		} \
++	} while (0)
++
++#define MAXSZ_BUF		4096
++#define MAXSZ_CONFIG	8192
++
++#ifndef WL_CFG80211
++#define htod32(i) i
++#define htod16(i) i
++#define dtoh32(i) i
++#define dtoh16(i) i
++#define htodchanspec(i) i
++#define dtohchanspec(i) i
++#endif
++
++#if defined(SUSPEND_EVENT) && defined(PROP_TXSTATUS)
++#if defined(BCMSDIO) || defined(BCMDBUS)
++#include <dhd_wlfc.h>
++#endif /* BCMSDIO || BCMDBUS */
++#endif /* SUSPEND_EVENT && PROP_TXSTATUS */
++
++#define MAX_EVENT_BUF_NUM 16
++typedef struct eventmsg_buf {
++	u16 num;
++	struct {
++		u16 type;
++		bool set;
++	} event [MAX_EVENT_BUF_NUM];
++} eventmsg_buf_t;
++
++typedef struct cihp_name_map_t {
++	uint chip;
++	uint chiprev;
++	uint ag_type;
++	char *chip_name;
++	char *module_name;
++} cihp_name_map_t;
++
++/* Map of WLC_E events to connection failure strings */
++#define DONT_CARE	9999
++const cihp_name_map_t chip_name_map[] = {
++	/* ChipID			Chiprev	AG	 	ChipName	ModuleName  */
++#ifdef BCMSDIO
++	{BCM43362_CHIP_ID,	0,	DONT_CARE,	"bcm40181a0",		""},
++	{BCM43362_CHIP_ID,	1,	DONT_CARE,	"bcm40181a2",		""},
++	{BCM4330_CHIP_ID,	4,	FW_TYPE_G,	"bcm40183b2",		""},
++	{BCM4330_CHIP_ID,	4,	FW_TYPE_AG,	"bcm40183b2_ag",	""},
++	{BCM43430_CHIP_ID,	0,	DONT_CARE,	"bcm43438a0",		""},
++	{BCM43430_CHIP_ID,	1,	DONT_CARE,	"bcm43438a1",		""},
++	{BCM43430_CHIP_ID,	2,	DONT_CARE,	"bcm43436b0",		""},
++	{BCM43012_CHIP_ID,	1,	FW_TYPE_G,	"bcm43013b0",		""},
++	{BCM43012_CHIP_ID,	1,	FW_TYPE_AG,	"bcm43013c0_ag",	""},
++	{BCM43012_CHIP_ID,	2,	DONT_CARE,	"bcm43013c1_ag",	""},
++	{BCM4334_CHIP_ID,	3,	DONT_CARE,	"bcm4334b1_ag",		""},
++	{BCM43340_CHIP_ID,	2,	DONT_CARE,	"bcm43341b0_ag",	""},
++	{BCM43341_CHIP_ID,	2,	DONT_CARE,	"bcm43341b0_ag",	""},
++	{BCM4324_CHIP_ID,	5,	DONT_CARE,	"bcm43241b4_ag",	""},
++	{BCM4335_CHIP_ID,	2,	DONT_CARE,	"bcm4339a0_ag",		""},
++	{BCM4339_CHIP_ID,	1,	DONT_CARE,	"bcm4339a0_ag",		""},
++	{BCM4345_CHIP_ID,	6,	DONT_CARE,	"bcm43455c0_ag",	""},
++	{BCM43454_CHIP_ID,	6,	DONT_CARE,	"bcm43455c0_ag",	""},
++	{BCM4345_CHIP_ID,	9,	DONT_CARE,	"bcm43456c5_ag",	""},
++	{BCM43454_CHIP_ID,	9,	DONT_CARE,	"bcm43456c5_ag",	""},
++	{BCM4354_CHIP_ID,	1,	DONT_CARE,	"bcm4354a1_ag",		""},
++	{BCM4354_CHIP_ID,	2,	DONT_CARE,	"bcm4356a2_ag",		""},
++	{BCM4356_CHIP_ID,	2,	DONT_CARE,	"bcm4356a2_ag",		""},
++	{BCM4371_CHIP_ID,	2,	DONT_CARE,	"bcm4356a2_ag",		""},
++	{BCM43569_CHIP_ID,	3,	DONT_CARE,	"bcm4358a3_ag",		""},
++	{BCM4359_CHIP_ID,	5,	DONT_CARE,	"bcm4359b1_ag",		""},
++	{BCM4359_CHIP_ID,	9,	DONT_CARE,	"bcm4359c0_ag",		""},
++#endif
++#ifdef BCMPCIE
++	{BCM4354_CHIP_ID,	2,	DONT_CARE,	"bcm4356a2_pcie_ag",	""},
++	{BCM4356_CHIP_ID,	2,	DONT_CARE,	"bcm4356a2_pcie_ag",	""},
++	{BCM4359_CHIP_ID,	9,	DONT_CARE,	"bcm4359c0_pcie_ag",	""},
++#endif
++#ifdef BCMDBUS
++	{BCM43143_CHIP_ID,	2,	DONT_CARE,	"bcm43143b0",		""},
++	{BCM43242_CHIP_ID,	1,	DONT_CARE,	"bcm43242a1_ag",	""},
++	{BCM43569_CHIP_ID,	2,	DONT_CARE,	"bcm4358u_ag",		""},
++#endif
++};
++
++void
++dhd_conf_free_chip_nv_path_list(wl_chip_nv_path_list_ctrl_t *chip_nv_list)
++{
++	CONFIG_TRACE("called\n");
++
++	if (chip_nv_list->m_chip_nv_path_head) {
++		CONFIG_TRACE("Free %p\n", chip_nv_list->m_chip_nv_path_head);
++		kfree(chip_nv_list->m_chip_nv_path_head);
++	}
++	chip_nv_list->count = 0;
++}
++
++#ifdef BCMSDIO
++void
++dhd_conf_free_mac_list(wl_mac_list_ctrl_t *mac_list)
++{
++	int i;
++
++	CONFIG_TRACE("called\n");
++	if (mac_list->m_mac_list_head) {
++		for (i=0; i<mac_list->count; i++) {
++			if (mac_list->m_mac_list_head[i].mac) {
++				CONFIG_TRACE("Free mac %p\n", mac_list->m_mac_list_head[i].mac);
++				kfree(mac_list->m_mac_list_head[i].mac);
++			}
++		}
++		CONFIG_TRACE("Free m_mac_list_head %p\n", mac_list->m_mac_list_head);
++		kfree(mac_list->m_mac_list_head);
++	}
++	mac_list->count = 0;
++}
++
++#if defined(HW_OOB) || defined(FORCE_WOWLAN)
++void
++dhd_conf_set_hw_oob_intr(bcmsdh_info_t *sdh, uint chip)
++{
++	uint32 gpiocontrol, addr;
++
++	if (CHIPID(chip) == BCM43362_CHIP_ID) {
++		CONFIG_MSG("Enable HW OOB for 43362\n");
++		addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, gpiocontrol);
++		gpiocontrol = bcmsdh_reg_read(sdh, addr, 4);
++		gpiocontrol |= 0x2;
++		bcmsdh_reg_write(sdh, addr, 4, gpiocontrol);
++		bcmsdh_cfg_write(sdh, SDIO_FUNC_1, 0x10005, 0xf, NULL);
++		bcmsdh_cfg_write(sdh, SDIO_FUNC_1, 0x10006, 0x0, NULL);
++		bcmsdh_cfg_write(sdh, SDIO_FUNC_1, 0x10007, 0x2, NULL);
++	}
++}
++#endif
++
++#define SBSDIO_CIS_SIZE_LIMIT		0x200
++#define F0_BLOCK_SIZE 32
++int
++dhd_conf_set_blksize(bcmsdh_info_t *sdh)
++{
++	int err = 0;
++	uint fn, numfn;
++	int32 blksize = 0, cur_blksize = 0;
++	uint8 cisd;
++
++	numfn = bcmsdh_query_iofnum(sdh);
++
++	for (fn = 0; fn <= numfn; fn++) {
++		if (!fn)
++			blksize = F0_BLOCK_SIZE;
++		else {
++			bcmsdh_cisaddr_read(sdh, fn, &cisd, 24);
++			blksize = cisd;
++			bcmsdh_cisaddr_read(sdh, fn, &cisd, 25);
++			blksize |= cisd << 8;
++		}
++#ifdef CUSTOM_SDIO_F2_BLKSIZE
++		if (fn == 2 && blksize > CUSTOM_SDIO_F2_BLKSIZE) {
++			blksize = CUSTOM_SDIO_F2_BLKSIZE;
++		}
++#endif
++		bcmsdh_iovar_op(sdh, "sd_blocksize", &fn, sizeof(int32),
++			&cur_blksize, sizeof(int32), FALSE);
++		if (cur_blksize != blksize) {
++			CONFIG_MSG("fn=%d, blksize=%d, cur_blksize=%d\n",
++				fn, blksize, cur_blksize);
++			blksize |= (fn<<16);
++			if (bcmsdh_iovar_op(sdh, "sd_blocksize", NULL, 0, &blksize,
++				sizeof(blksize), TRUE) != BCME_OK) {
++				CONFIG_ERROR("fail on get sd_blocksize");
++				err = -1;
++			}
++		}
++	}
++
++	return err;
++}
++
++void
++dhd_conf_get_otp(dhd_pub_t *dhd, bcmsdh_info_t *sdh)
++{
++	int i, err = -1;
++	uint8 *ptr = 0, *ptpl_code = NULL;
++	unsigned char tpl_code, tpl_link='\0';
++	uint8 mac_header[3] = {0x80, 0x07, 0x19};
++	uint8 *cis;
++
++	if (!(cis = MALLOC(dhd->osh, SBSDIO_CIS_SIZE_LIMIT))) {
++		CONFIG_ERROR("cis malloc failed\n");
++	}
++	bzero(cis, SBSDIO_CIS_SIZE_LIMIT);
++
++	if ((err = bcmsdh_cis_read(sdh, 0, cis, SBSDIO_CIS_SIZE_LIMIT))) {
++		CONFIG_ERROR("cis read err %d\n", err);
++		MFREE(dhd->osh, cis, SBSDIO_CIS_SIZE_LIMIT);
++		return;
++	}
++	ptr = cis;
++	do {
++		/* 0xff means we're done */
++		tpl_code = *ptr;
++		ptpl_code = ptr;
++		ptr++;
++		if (tpl_code == 0xff)
++			break;
++
++		/* null entries have no link field or data */
++		if (tpl_code == 0x00)
++			continue;
++
++		tpl_link = *ptr;
++		ptr++;
++		/* a size of 0xff also means we're done */
++		if (tpl_link == 0xff)
++			break;
++		if (config_msg_level & CONFIG_TRACE_LEVEL) {
++			prhex("TPL", ptpl_code, tpl_link+2);
++		}
++
++		if (tpl_code == 0x80 && tpl_link == 0x07 && *ptr == 0x19) {
++			memcpy(&dhd->conf->otp_mac, ptr+1, 6);
++		}
++#ifdef GET_OTP_MODULE_NAME
++		else if (tpl_code == 0x8e && *ptr == 0x41) {
++			int len = tpl_link - 1;
++			if (len <= sizeof(dhd->conf->module_name) - 1) {
++				strncpy(dhd->conf->module_name, ptr+1, len);
++				CONFIG_MSG("module_name=%s\n", dhd->conf->module_name);
++			} else {
++				CONFIG_ERROR("len is too long %d >= %d\n",
++					len, (int)sizeof(dhd->conf->module_name) - 1);
++			}
++		}
++#endif
++
++		ptr += tpl_link;
++	} while (1);
++
++	if (!memcmp(&ether_null, &dhd->conf->otp_mac, ETHER_ADDR_LEN)) {
++		ptr = cis;
++		/* Special OTP */
++		if (bcmsdh_reg_read(sdh, SI_ENUM_BASE, 4) == 0x16044330) {
++			for (i=0; i<SBSDIO_CIS_SIZE_LIMIT; i++) {
++				if (!memcmp(mac_header, ptr, 3)) {
++					memcpy(&dhd->conf->otp_mac, ptr+3, 6);
++					break;
++				}
++				ptr++;
++			}
++		}
++	}
++
++	ASSERT(cis);
++	MFREE(dhd->osh, cis, SBSDIO_CIS_SIZE_LIMIT);
++}
++
++void
++dhd_conf_set_fw_name_by_mac(dhd_pub_t *dhd, char *fw_path)
++{
++	int i, j;
++	uint8 *mac = (uint8 *)&dhd->conf->otp_mac;
++	int fw_num=0, mac_num=0;
++	uint32 oui, nic;
++	wl_mac_list_t *mac_list;
++	wl_mac_range_t *mac_range;
++	int fw_type, fw_type_new;
++	char *name_ptr;
++
++	mac_list = dhd->conf->fw_by_mac.m_mac_list_head;
++	fw_num = dhd->conf->fw_by_mac.count;
++	if (!mac_list || !fw_num)
++		return;
++
++	oui = (mac[0] << 16) | (mac[1] << 8) | (mac[2]);
++	nic = (mac[3] << 16) | (mac[4] << 8) | (mac[5]);
++
++	/* find out the last '/' */
++	i = strlen(fw_path);
++	while (i > 0) {
++		if (fw_path[i] == '/') {
++			i++;
++			break;
++		}
++		i--;
++	}
++	name_ptr = &fw_path[i];
++
++	if (strstr(name_ptr, "_apsta"))
++		fw_type = FW_TYPE_APSTA;
++	else if (strstr(name_ptr, "_p2p"))
++		fw_type = FW_TYPE_P2P;
++	else if (strstr(name_ptr, "_mesh"))
++		fw_type = FW_TYPE_MESH;
++	else if (strstr(name_ptr, "_es"))
++		fw_type = FW_TYPE_ES;
++	else if (strstr(name_ptr, "_mfg"))
++		fw_type = FW_TYPE_MFG;
++	else
++		fw_type = FW_TYPE_STA;
++
++	for (i=0; i<fw_num; i++) {
++		mac_num = mac_list[i].count;
++		mac_range = mac_list[i].mac;
++		if (strstr(mac_list[i].name, "_apsta"))
++			fw_type_new = FW_TYPE_APSTA;
++		else if (strstr(mac_list[i].name, "_p2p"))
++			fw_type_new = FW_TYPE_P2P;
++		else if (strstr(mac_list[i].name, "_mesh"))
++			fw_type_new = FW_TYPE_MESH;
++		else if (strstr(mac_list[i].name, "_es"))
++			fw_type_new = FW_TYPE_ES;
++		else if (strstr(mac_list[i].name, "_mfg"))
++			fw_type_new = FW_TYPE_MFG;
++		else
++			fw_type_new = FW_TYPE_STA;
++		if (fw_type != fw_type_new) {
++			CONFIG_MSG("fw_typ=%d != fw_type_new=%d\n", fw_type, fw_type_new);
++			continue;
++		}
++		for (j=0; j<mac_num; j++) {
++			if (oui == mac_range[j].oui) {
++				if (nic >= mac_range[j].nic_start && nic <= mac_range[j].nic_end) {
++					strcpy(name_ptr, mac_list[i].name);
++					CONFIG_MSG("matched oui=0x%06X, nic=0x%06X\n", oui, nic);
++					CONFIG_MSG("fw_path=%s\n", fw_path);
++					return;
++				}
++			}
++		}
++	}
++}
++
++void
++dhd_conf_set_nv_name_by_mac(dhd_pub_t *dhd, char *nv_path)
++{
++	int i, j;
++	uint8 *mac = (uint8 *)&dhd->conf->otp_mac;
++	int nv_num=0, mac_num=0;
++	uint32 oui, nic;
++	wl_mac_list_t *mac_list;
++	wl_mac_range_t *mac_range;
++	char *pnv_name;
++
++	mac_list = dhd->conf->nv_by_mac.m_mac_list_head;
++	nv_num = dhd->conf->nv_by_mac.count;
++	if (!mac_list || !nv_num)
++		return;
++
++	oui = (mac[0] << 16) | (mac[1] << 8) | (mac[2]);
++	nic = (mac[3] << 16) | (mac[4] << 8) | (mac[5]);
++
++	/* find out the last '/' */
++	i = strlen(nv_path);
++	while (i > 0) {
++		if (nv_path[i] == '/') break;
++		i--;
++	}
++	pnv_name = &nv_path[i+1];
++
++	for (i=0; i<nv_num; i++) {
++		mac_num = mac_list[i].count;
++		mac_range = mac_list[i].mac;
++		for (j=0; j<mac_num; j++) {
++			if (oui == mac_range[j].oui) {
++				if (nic >= mac_range[j].nic_start && nic <= mac_range[j].nic_end) {
++					strcpy(pnv_name, mac_list[i].name);
++					CONFIG_MSG("matched oui=0x%06X, nic=0x%06X\n", oui, nic);
++					CONFIG_MSG("nv_path=%s\n", nv_path);
++					return;
++				}
++			}
++		}
++	}
++}
++#endif
++
++void
++dhd_conf_free_country_list(struct dhd_conf *conf)
++{
++	country_list_t *country = conf->country_head;
++	int count = 0;
++
++	CONFIG_TRACE("called\n");
++	while (country) {
++		CONFIG_TRACE("Free cspec %s\n", country->cspec.country_abbrev);
++		conf->country_head = country->next;
++		kfree(country);
++		country = conf->country_head;
++		count++;
++	}
++	CONFIG_TRACE("%d country released\n", count);
++}
++
++void
++dhd_conf_free_mchan_list(struct dhd_conf *conf)
++{
++	mchan_params_t *mchan = conf->mchan;
++	int count = 0;
++
++	CONFIG_TRACE("called\n");
++	while (mchan) {
++		CONFIG_TRACE("Free cspec %p\n", mchan);
++		conf->mchan = mchan->next;
++		kfree(mchan);
++		mchan = conf->mchan;
++		count++;
++	}
++	CONFIG_TRACE("%d mchan released\n", count);
++}
++
++int
++dhd_conf_set_fw_name_by_chip(dhd_pub_t *dhd, char *fw_path)
++{
++	int fw_type, ag_type;
++	uint chip, chiprev;
++	int i;
++	char *name_ptr;
++
++	chip = dhd->conf->chip;
++	chiprev = dhd->conf->chiprev;
++
++	if (fw_path[0] == '\0') {
++#ifdef CONFIG_BCMDHD_FW_PATH
++		bcm_strncpy_s(fw_path, MOD_PARAM_PATHLEN-1, CONFIG_BCMDHD_FW_PATH, MOD_PARAM_PATHLEN-1);
++		if (fw_path[0] == '\0')
++#endif
++		{
++			CONFIG_MSG("firmware path is null\n");
++			return 0;
++		}
++	}
++#ifndef FW_PATH_AUTO_SELECT
++	return DONT_CARE;
++#endif
++
++	/* find out the last '/' */
++	i = strlen(fw_path);
++	while (i > 0) {
++		if (fw_path[i] == '/') {
++			i++;
++			break;
++		}
++		i--;
++	}
++	name_ptr = &fw_path[i];
++#ifdef BAND_AG
++	ag_type = FW_TYPE_AG;
++#else
++	ag_type = strstr(name_ptr, "_ag") ? FW_TYPE_AG : FW_TYPE_G;
++#endif
++	if (strstr(name_ptr, "_apsta"))
++		fw_type = FW_TYPE_APSTA;
++	else if (strstr(name_ptr, "_p2p"))
++		fw_type = FW_TYPE_P2P;
++	else if (strstr(name_ptr, "_mesh"))
++		fw_type = FW_TYPE_MESH;
++	else if (strstr(name_ptr, "_es"))
++		fw_type = FW_TYPE_ES;
++	else if (strstr(name_ptr, "_mfg"))
++		fw_type = FW_TYPE_MFG;
++	else
++		fw_type = FW_TYPE_STA;
++
++	for (i = 0; i < sizeof(chip_name_map)/sizeof(chip_name_map[0]); i++) {
++		const cihp_name_map_t* row = &chip_name_map[i];
++		if (row->chip == chip && row->chiprev == chiprev &&
++				(row->ag_type == ag_type || row->ag_type == DONT_CARE)) {
++			strcpy(name_ptr, "fw_");
++			strcat(fw_path, row->chip_name);
++#ifdef BCMUSBDEV_COMPOSITE
++			strcat(fw_path, "_cusb");
++#endif
++			if (fw_type == FW_TYPE_APSTA)
++				strcat(fw_path, "_apsta.bin");
++			else if (fw_type == FW_TYPE_P2P)
++				strcat(fw_path, "_p2p.bin");
++			else if (fw_type == FW_TYPE_MESH)
++				strcat(fw_path, "_mesh.bin");
++			else if (fw_type == FW_TYPE_ES)
++				strcat(fw_path, "_es.bin");
++			else if (fw_type == FW_TYPE_MFG)
++				strcat(fw_path, "_mfg.bin");
++			else
++				strcat(fw_path, ".bin");
++		}
++	}
++
++	dhd->conf->fw_type = fw_type;
++
++	CONFIG_TRACE("firmware_path=%s\n", fw_path);
++	return ag_type;
++}
++
++void
++dhd_conf_set_clm_name_by_chip(dhd_pub_t *dhd, char *clm_path, int ag_type)
++{
++	uint chip, chiprev;
++	int i;
++	char *name_ptr;
++
++	chip = dhd->conf->chip;
++	chiprev = dhd->conf->chiprev;
++
++	if (clm_path[0] == '\0') {
++		CONFIG_MSG("clm path is null\n");
++		return;
++	}
++
++	/* find out the last '/' */
++	i = strlen(clm_path);
++	while (i > 0) {
++		if (clm_path[i] == '/') {
++			i++;
++			break;
++		}
++		i--;
++	}
++	name_ptr = &clm_path[i];
++
++	for (i = 0; i < sizeof(chip_name_map)/sizeof(chip_name_map[0]); i++) {
++		const cihp_name_map_t* row = &chip_name_map[i];
++		if (row->chip == chip && row->chiprev == chiprev &&
++				(row->ag_type == ag_type || row->ag_type == DONT_CARE)) {
++			strcpy(name_ptr, "clm_");
++			strcat(clm_path, row->chip_name);
++			strcat(clm_path, ".blob");
++		}
++	}
++
++	CONFIG_TRACE("clm_path=%s\n", clm_path);
++}
++
++void
++dhd_conf_set_nv_name_by_chip(dhd_pub_t *dhd, char *nv_path, int ag_type)
++{
++	uint chip, chiprev;
++	int i;
++	char *name_ptr;
++
++	chip = dhd->conf->chip;
++	chiprev = dhd->conf->chiprev;
++
++	if (nv_path[0] == '\0') {
++#ifdef CONFIG_BCMDHD_NVRAM_PATH
++		bcm_strncpy_s(nv_path, MOD_PARAM_PATHLEN-1, CONFIG_BCMDHD_NVRAM_PATH, MOD_PARAM_PATHLEN-1);
++		if (nv_path[0] == '\0')
++#endif
++		{
++			CONFIG_MSG("nvram path is null\n");
++			return;
++		}
++	}
++
++	/* find out the last '/' */
++	i = strlen(nv_path);
++	while (i > 0) {
++		if (nv_path[i] == '/') {
++			i++;
++			break;
++		}
++		i--;
++	}
++	name_ptr = &nv_path[i];
++
++	for (i = 0; i < sizeof(chip_name_map)/sizeof(chip_name_map[0]); i++) {
++		const cihp_name_map_t* row = &chip_name_map[i];
++		if (row->chip == chip && row->chiprev == chiprev &&
++				(row->ag_type == ag_type || row->ag_type == DONT_CARE)) {
++#ifdef GET_OTP_MODULE_NAME
++			if (strlen(dhd->conf->module_name)) {
++				strcpy(name_ptr, "nvram_");
++				strcat(name_ptr, dhd->conf->module_name);
++			} else
++#endif
++			if (strlen(row->module_name)){
++				strcpy(name_ptr, "nvram_");
++				strcat(name_ptr, row->module_name);
++			} else
++				continue;
++#ifdef BCMUSBDEV_COMPOSITE
++			strcat(name_ptr, "_cusb");
++#endif
++			strcat(name_ptr, ".txt");
++		}
++	}
++
++	for (i=0; i<dhd->conf->nv_by_chip.count; i++) {
++		if (chip==dhd->conf->nv_by_chip.m_chip_nv_path_head[i].chip &&
++				chiprev==dhd->conf->nv_by_chip.m_chip_nv_path_head[i].chiprev) {
++			strcpy(name_ptr, dhd->conf->nv_by_chip.m_chip_nv_path_head[i].name);
++			break;
++		}
++	}
++
++	CONFIG_TRACE("nvram_path=%s\n", nv_path);
++}
++
++void
++dhd_conf_copy_path(dhd_pub_t *dhd, char *dst_name, char *dst_path, char *src_path)
++{
++	int i;
++
++	if (src_path[0] == '\0') {
++		CONFIG_MSG("src_path is null\n");
++		return;
++	} else
++		strcpy(dst_path, src_path);
++
++	/* find out the last '/' */
++	i = strlen(dst_path);
++	while (i > 0) {
++		if (dst_path[i] == '/') {
++			i++;
++			break;
++		}
++		i--;
++	}
++	strcpy(&dst_path[i], dst_name);
++
++	CONFIG_TRACE("dst_path=%s\n", dst_path);
++}
++
++#ifdef CONFIG_PATH_AUTO_SELECT
++void
++dhd_conf_set_conf_name_by_chip(dhd_pub_t *dhd, char *conf_path)
++{
++	uint chip, chiprev;
++	int i;
++	char *name_ptr;
++
++	chip = dhd->conf->chip;
++	chiprev = dhd->conf->chiprev;
++
++	if (conf_path[0] == '\0') {
++		CONFIG_MSG("config path is null\n");
++		return;
++	}
++
++	/* find out the last '/' */
++	i = strlen(conf_path);
++	while (i > 0) {
++		if (conf_path[i] == '/') {
++			i++;
++			break;
++		}
++		i--;
++	}
++	name_ptr = &conf_path[i];
++
++	for (i = 0;  i < sizeof(chip_name_map)/sizeof(chip_name_map[0]);  i++) {
++		const cihp_name_map_t* row = &chip_name_map[i];
++		if (row->chip == chip && row->chiprev == chiprev) {
++			strcpy(name_ptr, "config_");
++			strcat(conf_path, row->chip_name);
++			strcat(conf_path, ".txt");
++		}
++	}
++
++	CONFIG_TRACE("config_path=%s\n", conf_path);
++}
++#endif
++
++void
++dhd_conf_set_path_params(dhd_pub_t *dhd, char *fw_path, char *nv_path)
++{
++	int ag_type;
++
++	/* External conf takes precedence if specified */
++	dhd_conf_preinit(dhd);
++
++	if (dhd->conf_path[0] == '\0') {
++		dhd_conf_copy_path(dhd, "config.txt", dhd->conf_path, nv_path);
++	}
++	if (dhd->clm_path[0] == '\0') {
++		dhd_conf_copy_path(dhd, "clm.blob", dhd->clm_path, fw_path);
++	}
++#ifdef CONFIG_PATH_AUTO_SELECT
++	dhd_conf_set_conf_name_by_chip(dhd, dhd->conf_path);
++#endif
++
++	dhd_conf_read_config(dhd, dhd->conf_path);
++
++	ag_type = dhd_conf_set_fw_name_by_chip(dhd, fw_path);
++	dhd_conf_set_nv_name_by_chip(dhd, nv_path, ag_type);
++	dhd_conf_set_clm_name_by_chip(dhd, dhd->clm_path, ag_type);
++#ifdef BCMSDIO
++	dhd_conf_set_fw_name_by_mac(dhd, fw_path);
++	dhd_conf_set_nv_name_by_mac(dhd, nv_path);
++#endif
++
++	CONFIG_MSG("Final fw_path=%s\n", fw_path);
++	CONFIG_MSG("Final nv_path=%s\n", nv_path);
++	CONFIG_MSG("Final clm_path=%s\n", dhd->clm_path);
++	CONFIG_MSG("Final conf_path=%s\n", dhd->conf_path);
++}
++
++int
++dhd_conf_set_intiovar(dhd_pub_t *dhd, uint cmd, char *name, int val,
++	int def, bool down)
++{
++	int ret = -1;
++	char iovbuf[WL_EVENTING_MASK_LEN + 12];	/*  Room for "event_msgs" + '\0' + bitvec  */
++
++	if (val >= def) {
++		if (down) {
++			if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_DOWN, NULL, 0, TRUE, 0)) < 0)
++				CONFIG_ERROR("WLC_DOWN setting failed %d\n", ret);
++		}
++		if (cmd == WLC_SET_VAR) {
++			CONFIG_TRACE("set %s %d\n", name, val);
++			bcm_mkiovar(name, (char *)&val, sizeof(val), iovbuf, sizeof(iovbuf));
++			if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, iovbuf, sizeof(iovbuf), TRUE, 0)) < 0)
++				CONFIG_ERROR("%s setting failed %d\n", name, ret);
++		} else {
++			CONFIG_TRACE("set %s %d %d\n", name, cmd, val);
++			if ((ret = dhd_wl_ioctl_cmd(dhd, cmd, &val, sizeof(val), TRUE, 0)) < 0)
++				CONFIG_ERROR("%s setting failed %d\n", name, ret);
++		}
++	}
++
++	return ret;
++}
++
++int
++dhd_conf_set_bufiovar(dhd_pub_t *dhd, int ifidx, uint cmd, char *name,
++	char *buf, int len, bool down)
++{
++	char iovbuf[WLC_IOCTL_SMLEN];
++	s32 iovar_len;
++	int ret = -1;
++
++	if (down) {
++		if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_DOWN, NULL, 0, TRUE, ifidx)) < 0)
++			CONFIG_ERROR("WLC_DOWN setting failed %d\n", ret);
++	}
++
++	if (cmd == WLC_SET_VAR) {
++		iovar_len = bcm_mkiovar(name, buf, len, iovbuf, sizeof(iovbuf));
++		if (iovar_len > 0)
++			ret = dhd_wl_ioctl_cmd(dhd, cmd, iovbuf, iovar_len, TRUE, ifidx);
++		else
++			ret = BCME_BUFTOOSHORT;
++		if (ret < 0)
++			CONFIG_ERROR("%s setting failed %d, len=%d\n", name, ret, len);
++	} else {
++		if ((ret = dhd_wl_ioctl_cmd(dhd, cmd, buf, len, TRUE, ifidx)) < 0)
++			CONFIG_ERROR("%s setting failed %d\n", name, ret);
++	}
++
++	return ret;
++}
++
++int
++dhd_conf_get_iovar(dhd_pub_t *dhd, int ifidx, int cmd, char *name,
++	char *buf, int len)
++{
++	char iovbuf[WLC_IOCTL_SMLEN];
++	int ret = -1;
++
++	if (cmd == WLC_GET_VAR) {
++		if (bcm_mkiovar(name, NULL, 0, iovbuf, sizeof(iovbuf))) {
++			ret = dhd_wl_ioctl_cmd(dhd, cmd, iovbuf, sizeof(iovbuf), FALSE, ifidx);
++			if (!ret) {
++				memcpy(buf, iovbuf, len);
++			} else {
++				CONFIG_ERROR("get iovar %s failed %d\n", name, ret);
++			}
++		} else {
++			CONFIG_ERROR("mkiovar %s failed\n", name);
++		}
++	} else {
++		ret = dhd_wl_ioctl_cmd(dhd, cmd, buf, len, FALSE, 0);
++		if (ret < 0)
++			CONFIG_ERROR("get iovar %s failed %d\n", name, ret);
++	}
++
++	return ret;
++}
++
++static int
++dhd_conf_rsdb_mode(dhd_pub_t *dhd, char *buf)
++{
++	wl_config_t rsdb_mode_cfg = {1, 0};
++
++	if (buf) {
++		rsdb_mode_cfg.config = (int)simple_strtol(buf, NULL, 0);
++		CONFIG_MSG("rsdb_mode %d\n", rsdb_mode_cfg.config);
++		dhd_conf_set_bufiovar(dhd, 0, WLC_SET_VAR, "rsdb_mode", (char *)&rsdb_mode_cfg,
++			sizeof(rsdb_mode_cfg), TRUE);
++	}
++
++	return 0;
++}
++
++typedef int (tpl_parse_t)(dhd_pub_t *dhd, char *buf);
++
++typedef struct iovar_tpl_t {
++	int cmd;
++	char *name;
++	tpl_parse_t *parse;
++} iovar_tpl_t;
++
++const iovar_tpl_t iovar_tpl_list[] = {
++	{WLC_SET_VAR,	"rsdb_mode",	dhd_conf_rsdb_mode},
++};
++
++static int iovar_tpl_parse(const iovar_tpl_t *tpl, int tpl_count,
++	dhd_pub_t *dhd, int cmd, char *name, char *buf)
++{
++	int i, ret = 0;
++
++	/* look for a matching code in the table */
++	for (i = 0; i < tpl_count; i++, tpl++) {
++		if (tpl->cmd == cmd && !strcmp(tpl->name, name))
++			break;
++	}
++	if (i < tpl_count && tpl->parse) {
++		ret = tpl->parse(dhd, buf);
++	} else {
++		ret = -1;
++	}
++
++	return ret;
++}
++
++bool
++dhd_conf_set_wl_cmd(dhd_pub_t *dhd, char *data, bool down)
++{
++	int cmd, val, ret = 0, len;
++	char name[32], *pch, *pick_tmp, *pick_tmp2, *pdata = NULL;
++
++	/* Process wl_preinit:
++	 * wl_preinit=[cmd]=[val], [cmd]=[val]
++	 * Ex: wl_preinit=86=0, mpc=0
++	 */
++
++	if (data == NULL)
++		return FALSE;
++
++	len = strlen(data);
++	pdata = kmalloc(len+1, GFP_KERNEL);
++	if (pdata == NULL) {
++		CONFIG_ERROR("Failed to allocate buffer of %d bytes\n", len+1);
++		goto exit;
++	}
++	memset(pdata, 0, len+1);
++	strcpy(pdata, data);
++
++	pick_tmp = pdata;
++	while (pick_tmp && (pick_tmp2 = bcmstrtok(&pick_tmp, ",", 0)) != NULL) {
++		pch = bcmstrtok(&pick_tmp2, "=", 0);
++		if (!pch)
++			break;
++		if (*pch == ' ') {
++			pch++;
++		}
++		memset(name, 0 , sizeof (name));
++		cmd = (int)simple_strtol(pch, NULL, 0);
++		if (cmd == 0) {
++			cmd = WLC_SET_VAR;
++			strcpy(name, pch);
++		}
++		pch = bcmstrtok(&pick_tmp2, ",", 0);
++		if (!pch) {
++			break;
++		}
++		ret = iovar_tpl_parse(iovar_tpl_list, ARRAY_SIZE(iovar_tpl_list),
++			dhd, cmd, name, pch);
++		if (ret) {
++			val = (int)simple_strtol(pch, NULL, 0);
++			dhd_conf_set_intiovar(dhd, cmd, name, val, -1, down);
++		}
++	}
++
++exit:
++	if (pdata)
++		kfree(pdata);
++	return true;
++}
++
++int
++dhd_conf_get_band(dhd_pub_t *dhd)
++{
++	int band = -1;
++
++	if (dhd && dhd->conf)
++		band = dhd->conf->band;
++	else
++		CONFIG_ERROR("dhd or conf is NULL\n");
++
++	return band;
++}
++
++int
++dhd_conf_get_country(dhd_pub_t *dhd, wl_country_t *cspec)
++{
++	int bcmerror = -1;
++
++	memset(cspec, 0, sizeof(wl_country_t));
++	bcm_mkiovar("country", NULL, 0, (char*)cspec, sizeof(wl_country_t));
++	if ((bcmerror = dhd_wl_ioctl_cmd(dhd, WLC_GET_VAR, cspec, sizeof(wl_country_t),
++			FALSE, 0)) < 0)
++		CONFIG_ERROR("country code getting failed %d\n", bcmerror);
++
++	return bcmerror;
++}
++
++int
++dhd_conf_map_country_list(dhd_pub_t *dhd, wl_country_t *cspec)
++{
++	int bcmerror = -1;
++	struct dhd_conf *conf = dhd->conf;
++	country_list_t *country = conf->country_head;
++
++#ifdef CCODE_LIST
++	bcmerror = dhd_ccode_map_country_list(dhd, cspec);
++#endif
++
++	while (country != NULL) {
++		if (!strncmp("**", country->cspec.country_abbrev, 2)) {
++			memcpy(cspec->ccode, country->cspec.ccode, WLC_CNTRY_BUF_SZ);
++			cspec->rev = country->cspec.rev;
++			bcmerror = 0;
++			break;
++		} else if (!strncmp(cspec->country_abbrev,
++				country->cspec.country_abbrev, 2)) {
++			memcpy(cspec->ccode, country->cspec.ccode, WLC_CNTRY_BUF_SZ);
++			cspec->rev = country->cspec.rev;
++			bcmerror = 0;
++			break;
++		}
++		country = country->next;
++	}
++
++	if (!bcmerror)
++		CONFIG_MSG("%s/%d\n", cspec->ccode, cspec->rev);
++
++	return bcmerror;
++}
++
++int
++dhd_conf_set_country(dhd_pub_t *dhd, wl_country_t *cspec)
++{
++	int bcmerror = -1;
++
++	memset(&dhd->dhd_cspec, 0, sizeof(wl_country_t));
++
++	CONFIG_MSG("set country %s, revision %d\n", cspec->ccode, cspec->rev);
++	bcmerror = dhd_conf_set_bufiovar(dhd, 0, WLC_SET_VAR, "country", (char *)cspec,
++		sizeof(wl_country_t), FALSE);
++	dhd_conf_get_country(dhd, cspec);
++	CONFIG_MSG("Country code: %s (%s/%d)\n",
++		cspec->country_abbrev, cspec->ccode, cspec->rev);
++
++	return bcmerror;
++}
++
++int
++dhd_conf_fix_country(dhd_pub_t *dhd)
++{
++	int bcmerror = -1;
++	int band;
++	wl_uint32_list_t *list;
++	u8 valid_chan_list[sizeof(u32)*(WL_NUMCHANNELS + 1)];
++	wl_country_t cspec;
++
++	if (!(dhd && dhd->conf)) {
++		return bcmerror;
++	}
++
++	memset(valid_chan_list, 0, sizeof(valid_chan_list));
++	list = (wl_uint32_list_t *)(void *) valid_chan_list;
++	list->count = htod32(WL_NUMCHANNELS);
++	if ((bcmerror = dhd_wl_ioctl_cmd(dhd, WLC_GET_VALID_CHANNELS, valid_chan_list,
++			sizeof(valid_chan_list), FALSE, 0)) < 0) {
++		CONFIG_ERROR("get channels failed with %d\n", bcmerror);
++	}
++
++	band = dhd_conf_get_band(dhd);
++
++	if (bcmerror || ((band==WLC_BAND_AUTO || band==WLC_BAND_2G || band==-1) &&
++			dtoh32(list->count)<11)) {
++		CONFIG_ERROR("bcmerror=%d, # of channels %d\n",
++			bcmerror, dtoh32(list->count));
++		dhd_conf_map_country_list(dhd, &dhd->conf->cspec);
++		if ((bcmerror = dhd_conf_set_country(dhd, &dhd->conf->cspec)) < 0) {
++			strcpy(cspec.country_abbrev, "US");
++			cspec.rev = 0;
++			strcpy(cspec.ccode, "US");
++			dhd_conf_map_country_list(dhd, &cspec);
++			dhd_conf_set_country(dhd, &cspec);
++		}
++	}
++
++	return bcmerror;
++}
++
++bool
++dhd_conf_match_channel(dhd_pub_t *dhd, uint32 channel)
++{
++	int i;
++	bool match = false;
++
++	if (dhd && dhd->conf) {
++		if (dhd->conf->channels.count == 0)
++			return true;
++		for (i=0; i<dhd->conf->channels.count; i++) {
++			if (channel == dhd->conf->channels.channel[i])
++				match = true;
++		}
++	} else {
++		match = true;
++		CONFIG_ERROR("dhd or conf is NULL\n");
++	}
++
++	return match;
++}
++
++int
++dhd_conf_set_roam(dhd_pub_t *dhd)
++{
++	int bcmerror = -1;
++	struct dhd_conf *conf = dhd->conf;
++
++	dhd_roam_disable = conf->roam_off;
++	dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "roam_off", dhd->conf->roam_off, 0, FALSE);
++
++	if (!conf->roam_off || !conf->roam_off_suspend) {
++		CONFIG_MSG("set roam_trigger %d\n", conf->roam_trigger[0]);
++		dhd_conf_set_bufiovar(dhd, 0, WLC_SET_ROAM_TRIGGER, "WLC_SET_ROAM_TRIGGER",
++			(char *)conf->roam_trigger, sizeof(conf->roam_trigger), FALSE);
++
++		CONFIG_MSG("set roam_scan_period %d\n", conf->roam_scan_period[0]);
++		dhd_conf_set_bufiovar(dhd, 0, WLC_SET_ROAM_SCAN_PERIOD, "WLC_SET_ROAM_SCAN_PERIOD",
++			(char *)conf->roam_scan_period, sizeof(conf->roam_scan_period), FALSE);
++
++		CONFIG_MSG("set roam_delta %d\n", conf->roam_delta[0]);
++		dhd_conf_set_bufiovar(dhd, 0, WLC_SET_ROAM_DELTA, "WLC_SET_ROAM_DELTA",
++			(char *)conf->roam_delta, sizeof(conf->roam_delta), FALSE);
++
++		dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "fullroamperiod",
++			dhd->conf->fullroamperiod, 1, FALSE);
++	}
++
++	return bcmerror;
++}
++
++void
++dhd_conf_add_to_eventbuffer(struct eventmsg_buf *ev, u16 event, bool set)
++{
++	if (!ev || (event > WLC_E_LAST))
++		return;
++
++	if (ev->num < MAX_EVENT_BUF_NUM) {
++		ev->event[ev->num].type = event;
++		ev->event[ev->num].set = set;
++		ev->num++;
++	} else {
++		CONFIG_ERROR("evenbuffer doesn't support > %u events. Update"
++			" the define MAX_EVENT_BUF_NUM \n", MAX_EVENT_BUF_NUM);
++		ASSERT(0);
++	}
++}
++
++s32
++dhd_conf_apply_eventbuffer(dhd_pub_t *dhd, eventmsg_buf_t *ev)
++{
++	char eventmask[WL_EVENTING_MASK_LEN];
++	int i, ret = 0;
++
++	if (!ev || (!ev->num))
++		return -EINVAL;
++
++	/* Read event_msgs mask */
++	ret = dhd_conf_get_iovar(dhd, 0, WLC_GET_VAR, "event_msgs", eventmask,
++		sizeof(eventmask));
++	if (unlikely(ret)) {
++		CONFIG_ERROR("Get event_msgs error (%d)\n", ret);
++		goto exit;
++	}
++
++	/* apply the set bits */
++	for (i = 0; i < ev->num; i++) {
++		if (ev->event[i].set)
++			setbit(eventmask, ev->event[i].type);
++		else
++			clrbit(eventmask, ev->event[i].type);
++	}
++
++	/* Write updated Event mask */
++	ret = dhd_conf_set_bufiovar(dhd, 0, WLC_SET_VAR, "event_msgs", eventmask,
++		sizeof(eventmask), FALSE);
++	if (unlikely(ret)) {
++		CONFIG_ERROR("Set event_msgs error (%d)\n", ret);
++	}
++
++exit:
++	return ret;
++}
++
++int
++dhd_conf_enable_roam_offload(dhd_pub_t *dhd, int enable)
++{
++	int err;
++	eventmsg_buf_t ev_buf;
++
++	if (dhd->conf->roam_off_suspend)
++		return 0;
++
++	err = dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "roam_offload", enable, 0, FALSE);
++	if (err)
++		return err;
++
++	bzero(&ev_buf, sizeof(eventmsg_buf_t));
++	dhd_conf_add_to_eventbuffer(&ev_buf, WLC_E_PSK_SUP, !enable);
++	dhd_conf_add_to_eventbuffer(&ev_buf, WLC_E_ASSOC_REQ_IE, !enable);
++	dhd_conf_add_to_eventbuffer(&ev_buf, WLC_E_ASSOC_RESP_IE, !enable);
++	dhd_conf_add_to_eventbuffer(&ev_buf, WLC_E_REASSOC, !enable);
++	dhd_conf_add_to_eventbuffer(&ev_buf, WLC_E_JOIN, !enable);
++	dhd_conf_add_to_eventbuffer(&ev_buf, WLC_E_ROAM, !enable);
++	err = dhd_conf_apply_eventbuffer(dhd, &ev_buf);
++
++	CONFIG_TRACE("roam_offload %d\n", enable);
++
++	return err;
++}
++
++void
++dhd_conf_set_bw_cap(dhd_pub_t *dhd)
++{
++	struct {
++		u32 band;
++		u32 bw_cap;
++	} param = {0, 0};
++
++	if (dhd->conf->bw_cap[0] >= 0) {
++		memset(&param, 0, sizeof(param));
++		param.band = WLC_BAND_2G;
++		param.bw_cap = (uint)dhd->conf->bw_cap[0];
++		CONFIG_MSG("set bw_cap 2g 0x%x\n", param.bw_cap);
++		dhd_conf_set_bufiovar(dhd, 0, WLC_SET_VAR, "bw_cap", (char *)&param,
++			sizeof(param), TRUE);
++	}
++
++	if (dhd->conf->bw_cap[1] >= 0) {
++		memset(&param, 0, sizeof(param));
++		param.band = WLC_BAND_5G;
++		param.bw_cap = (uint)dhd->conf->bw_cap[1];
++		CONFIG_MSG("set bw_cap 5g 0x%x\n", param.bw_cap);
++		dhd_conf_set_bufiovar(dhd, 0, WLC_SET_VAR, "bw_cap", (char *)&param,
++			sizeof(param), TRUE);
++	}
++}
++
++void
++dhd_conf_get_wme(dhd_pub_t *dhd, int ifidx, int mode, edcf_acparam_t *acp)
++{
++	int bcmerror = -1;
++	char iovbuf[WLC_IOCTL_SMLEN];
++	edcf_acparam_t *acparam;
++
++	bzero(iovbuf, sizeof(iovbuf));
++
++	/*
++	 * Get current acparams, using buf as an input buffer.
++	 * Return data is array of 4 ACs of wme params.
++	 */
++	if (mode == 0)
++		bcm_mkiovar("wme_ac_sta", NULL, 0, iovbuf, sizeof(iovbuf));
++	else
++		bcm_mkiovar("wme_ac_ap", NULL, 0, iovbuf, sizeof(iovbuf));
++	if ((bcmerror = dhd_wl_ioctl_cmd(dhd, WLC_GET_VAR, iovbuf, sizeof(iovbuf),
++			FALSE, ifidx)) < 0) {
++		CONFIG_ERROR("wme_ac_sta getting failed %d\n", bcmerror);
++		return;
++	}
++	memcpy((char*)acp, iovbuf, sizeof(edcf_acparam_t)*AC_COUNT);
++
++	acparam = &acp[AC_BK];
++	CONFIG_TRACE("BK: aci %d aifsn %d ecwmin %d ecwmax %d txop 0x%x\n",
++		acparam->ACI, acparam->ACI&EDCF_AIFSN_MASK,
++		acparam->ECW&EDCF_ECWMIN_MASK, (acparam->ECW&EDCF_ECWMAX_MASK)>>EDCF_ECWMAX_SHIFT,
++		acparam->TXOP);
++	acparam = &acp[AC_BE];
++	CONFIG_TRACE("BE: aci %d aifsn %d ecwmin %d ecwmax %d txop 0x%x\n",
++		acparam->ACI, acparam->ACI&EDCF_AIFSN_MASK,
++		acparam->ECW&EDCF_ECWMIN_MASK, (acparam->ECW&EDCF_ECWMAX_MASK)>>EDCF_ECWMAX_SHIFT,
++		acparam->TXOP);
++	acparam = &acp[AC_VI];
++	CONFIG_TRACE("VI: aci %d aifsn %d ecwmin %d ecwmax %d txop 0x%x\n",
++		acparam->ACI, acparam->ACI&EDCF_AIFSN_MASK,
++		acparam->ECW&EDCF_ECWMIN_MASK, (acparam->ECW&EDCF_ECWMAX_MASK)>>EDCF_ECWMAX_SHIFT,
++		acparam->TXOP);
++	acparam = &acp[AC_VO];
++	CONFIG_TRACE("VO: aci %d aifsn %d ecwmin %d ecwmax %d txop 0x%x\n",
++		acparam->ACI, acparam->ACI&EDCF_AIFSN_MASK,
++		acparam->ECW&EDCF_ECWMIN_MASK, (acparam->ECW&EDCF_ECWMAX_MASK)>>EDCF_ECWMAX_SHIFT,
++		acparam->TXOP);
++
++	return;
++}
++
++void
++dhd_conf_update_wme(dhd_pub_t *dhd, int ifidx, int mode,
++	edcf_acparam_t *acparam_cur, int aci)
++{
++	int aifsn, ecwmin, ecwmax, txop;
++	edcf_acparam_t *acp;
++	struct dhd_conf *conf = dhd->conf;
++	wme_param_t *wme;
++
++	if (mode == 0)
++		wme = &conf->wme_sta;
++	else
++		wme = &conf->wme_ap;
++
++	/* Default value */
++	aifsn = acparam_cur->ACI&EDCF_AIFSN_MASK;
++	ecwmin = acparam_cur->ECW&EDCF_ECWMIN_MASK;
++	ecwmax = (acparam_cur->ECW&EDCF_ECWMAX_MASK)>>EDCF_ECWMAX_SHIFT;
++	txop = acparam_cur->TXOP;
++
++	/* Modified value */
++	if (wme->aifsn[aci] > 0)
++		aifsn = wme->aifsn[aci];
++	if (wme->ecwmin[aci] > 0)
++		ecwmin = wme->ecwmin[aci];
++	if (wme->ecwmax[aci] > 0)
++		ecwmax = wme->ecwmax[aci];
++	if (wme->txop[aci] > 0)
++		txop = wme->txop[aci];
++
++	if (!(wme->aifsn[aci] || wme->ecwmin[aci] ||
++			wme->ecwmax[aci] || wme->txop[aci]))
++		return;
++
++	/* Update */
++	acp = acparam_cur;
++	acp->ACI = (acp->ACI & ~EDCF_AIFSN_MASK) | (aifsn & EDCF_AIFSN_MASK);
++	acp->ECW = ((ecwmax << EDCF_ECWMAX_SHIFT) & EDCF_ECWMAX_MASK) | (acp->ECW & EDCF_ECWMIN_MASK);
++	acp->ECW = ((acp->ECW & EDCF_ECWMAX_MASK) | (ecwmin & EDCF_ECWMIN_MASK));
++	acp->TXOP = txop;
++
++	CONFIG_MSG("wme_ac %s aci %d aifsn %d ecwmin %d ecwmax %d txop 0x%x\n",
++		mode?"ap":"sta", acp->ACI, acp->ACI&EDCF_AIFSN_MASK,
++		acp->ECW&EDCF_ECWMIN_MASK, (acp->ECW&EDCF_ECWMAX_MASK)>>EDCF_ECWMAX_SHIFT,
++		acp->TXOP);
++
++	/*
++	* Now use buf as an output buffer.
++	* Put WME acparams after "wme_ac\0" in buf.
++	* NOTE: only one of the four ACs can be set at a time.
++	*/
++	if (mode == 0)
++		dhd_conf_set_bufiovar(dhd, ifidx, WLC_SET_VAR, "wme_ac_sta", (char *)acp,
++			sizeof(edcf_acparam_t), FALSE);
++	else
++		dhd_conf_set_bufiovar(dhd, ifidx, WLC_SET_VAR, "wme_ac_ap", (char *)acp,
++			sizeof(edcf_acparam_t), FALSE);
++
++}
++
++void
++dhd_conf_set_wme(dhd_pub_t *dhd, int ifidx, int mode)
++{
++	edcf_acparam_t acparam_cur[AC_COUNT];
++
++	if (dhd && dhd->conf) {
++		if (!dhd->conf->force_wme_ac) {
++			CONFIG_TRACE("force_wme_ac is not enabled %d\n",
++				dhd->conf->force_wme_ac);
++			return;
++		}
++
++		CONFIG_TRACE("Before change:\n");
++		dhd_conf_get_wme(dhd, ifidx, mode, acparam_cur);
++
++		dhd_conf_update_wme(dhd, ifidx, mode, &acparam_cur[AC_BK], AC_BK);
++		dhd_conf_update_wme(dhd, ifidx, mode, &acparam_cur[AC_BE], AC_BE);
++		dhd_conf_update_wme(dhd, ifidx, mode, &acparam_cur[AC_VI], AC_VI);
++		dhd_conf_update_wme(dhd, ifidx, mode, &acparam_cur[AC_VO], AC_VO);
++
++		CONFIG_TRACE("After change:\n");
++		dhd_conf_get_wme(dhd, ifidx, mode, acparam_cur);
++	} else {
++		CONFIG_ERROR("dhd or conf is NULL\n");
++	}
++
++	return;
++}
++
++void
++dhd_conf_set_mchan_bw(dhd_pub_t *dhd, int p2p_mode, int miracast_mode)
++{
++	struct dhd_conf *conf = dhd->conf;
++	mchan_params_t *mchan = conf->mchan;
++	bool set = true;
++
++	while (mchan != NULL) {
++		set = true;
++		set &= (mchan->bw >= 0);
++		set &= ((mchan->p2p_mode == -1) | (mchan->p2p_mode == p2p_mode));
++		set &= ((mchan->miracast_mode == -1) | (mchan->miracast_mode == miracast_mode));
++		if (set) {
++			dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "mchan_bw", mchan->bw, 0, FALSE);
++		}
++		mchan = mchan->next;
++	}
++
++	return;
++}
++
++#ifdef PKT_FILTER_SUPPORT
++void
++dhd_conf_add_pkt_filter(dhd_pub_t *dhd)
++{
++	int i, j;
++	char str[16];
++#define MACS "%02x%02x%02x%02x%02x%02x"
++
++	/*
++	 * Filter in less pkt: ARP(0x0806, ID is 105), BRCM(0x886C), 802.1X(0x888E)
++	 *   1) dhd_master_mode=1
++	 *   2) pkt_filter_delete=100, 102, 103, 104, 105, 106, 107
++	 *   3) pkt_filter_add=131 0 0 12 0xFFFF 0x886C, 132 0 0 12 0xFFFF 0x888E
++	 *   4) magic_pkt_filter_add=141 0 1 12
++	 */
++	for(i=0; i<dhd->conf->pkt_filter_add.count; i++) {
++		dhd->pktfilter[i+dhd->pktfilter_count] = dhd->conf->pkt_filter_add.filter[i];
++		CONFIG_MSG("%s\n", dhd->pktfilter[i+dhd->pktfilter_count]);
++	}
++	dhd->pktfilter_count += i;
++
++	if (dhd->conf->magic_pkt_filter_add) {
++		strcat(dhd->conf->magic_pkt_filter_add, " 0x");
++		strcat(dhd->conf->magic_pkt_filter_add, "FFFFFFFFFFFF");
++		for (j=0; j<16; j++)
++			strcat(dhd->conf->magic_pkt_filter_add, "FFFFFFFFFFFF");
++		strcat(dhd->conf->magic_pkt_filter_add, " 0x");
++		strcat(dhd->conf->magic_pkt_filter_add, "FFFFFFFFFFFF");
++		sprintf(str, MACS, MAC2STRDBG(dhd->mac.octet));
++		for (j=0; j<16; j++)
++			strncat(dhd->conf->magic_pkt_filter_add, str, 12);
++		dhd->pktfilter[dhd->pktfilter_count] = dhd->conf->magic_pkt_filter_add;
++		dhd->pktfilter_count += 1;
++	}
++}
++
++bool
++dhd_conf_del_pkt_filter(dhd_pub_t *dhd, uint32 id)
++{
++	int i;
++
++	if (dhd && dhd->conf) {
++		for (i=0; i<dhd->conf->pkt_filter_del.count; i++) {
++			if (id == dhd->conf->pkt_filter_del.id[i]) {
++				CONFIG_MSG("%d\n", dhd->conf->pkt_filter_del.id[i]);
++				return true;
++			}
++		}
++		return false;
++	}
++	return false;
++}
++
++void
++dhd_conf_discard_pkt_filter(dhd_pub_t *dhd)
++{
++	dhd->pktfilter_count = 6;
++	dhd->pktfilter[DHD_UNICAST_FILTER_NUM] = NULL;
++	dhd->pktfilter[DHD_BROADCAST_FILTER_NUM] = "101 0 0 0 0xFFFFFFFFFFFF 0xFFFFFFFFFFFF";
++	dhd->pktfilter[DHD_MULTICAST4_FILTER_NUM] = "102 0 0 0 0xFFFFFF 0x01005E";
++	dhd->pktfilter[DHD_MULTICAST6_FILTER_NUM] = "103 0 0 0 0xFFFF 0x3333";
++	dhd->pktfilter[DHD_MDNS_FILTER_NUM] = NULL;
++	/* Do not enable ARP to pkt filter if dhd_master_mode is false.*/
++	dhd->pktfilter[DHD_ARP_FILTER_NUM] = NULL;
++
++	/* IPv4 broadcast address XXX.XXX.XXX.255 */
++	dhd->pktfilter[dhd->pktfilter_count] = "110 0 0 12 0xFFFF00000000000000000000000000000000000000FF 0x080000000000000000000000000000000000000000FF";
++	dhd->pktfilter_count++;
++	/* discard IPv4 multicast address 224.0.0.0/4 */
++	dhd->pktfilter[dhd->pktfilter_count] = "111 0 0 12 0xFFFF00000000000000000000000000000000F0 0x080000000000000000000000000000000000E0";
++	dhd->pktfilter_count++;
++	/* discard IPv6 multicast address FF00::/8 */
++	dhd->pktfilter[dhd->pktfilter_count] = "112 0 0 12 0xFFFF000000000000000000000000000000000000000000000000FF 0x86DD000000000000000000000000000000000000000000000000FF";
++	dhd->pktfilter_count++;
++	/* discard Netbios pkt */
++	dhd->pktfilter[dhd->pktfilter_count] = "121 0 0 12 0xFFFF000000000000000000FF000000000000000000000000FFFF 0x0800000000000000000000110000000000000000000000000089";
++	dhd->pktfilter_count++;
++
++}
++#endif /* PKT_FILTER_SUPPORT */
++
++int
++dhd_conf_get_pm(dhd_pub_t *dhd)
++{
++	if (dhd && dhd->conf) {
++		return dhd->conf->pm;
++	}
++	return -1;
++}
++
++int
++dhd_conf_check_hostsleep(dhd_pub_t *dhd, int cmd, void *buf, int len,
++	int *hostsleep_set, int *hostsleep_val, int *ret)
++{
++	if (dhd->conf->insuspend & (NO_TXCTL_IN_SUSPEND | WOWL_IN_SUSPEND)) {
++		if (cmd == WLC_SET_VAR) {
++			char *psleep = NULL;
++			psleep = strstr(buf, "hostsleep");
++			if (psleep) {
++				*hostsleep_set = 1;
++				memcpy(hostsleep_val, psleep+strlen("hostsleep")+1, sizeof(int));
++			}
++		}
++		if (dhd->hostsleep && (!*hostsleep_set || *hostsleep_val)) {
++			CONFIG_TRACE("block all none hostsleep clr cmd\n");
++			*ret = BCME_EPERM;
++			goto exit;
++		} else if (*hostsleep_set && *hostsleep_val) {
++			CONFIG_TRACE("hostsleep %d => %d\n", dhd->hostsleep, *hostsleep_val);
++			dhd->hostsleep = *hostsleep_val;
++			if (dhd->conf->insuspend & NO_TXDATA_IN_SUSPEND) {
++				dhd_txflowcontrol(dhd, ALL_INTERFACES, ON);
++			}
++			if (dhd->hostsleep == 2) {
++				*ret = 0;
++				goto exit;
++			}
++		} else if (dhd->hostsleep == 2 && !*hostsleep_val) {
++			CONFIG_TRACE("hostsleep %d => %d\n", dhd->hostsleep, *hostsleep_val);
++			dhd->hostsleep = *hostsleep_val;
++			if (dhd->conf->insuspend & NO_TXDATA_IN_SUSPEND) {
++				dhd_txflowcontrol(dhd, ALL_INTERFACES, OFF);
++			}
++			*ret = 0;
++			goto exit;
++		}
++	}
++
++	return 0;
++exit:
++	return -1;
++}
++
++void
++dhd_conf_get_hostsleep(dhd_pub_t *dhd,
++	int hostsleep_set, int hostsleep_val, int ret)
++{
++	if (dhd->conf->insuspend & (NO_TXCTL_IN_SUSPEND | WOWL_IN_SUSPEND)) {
++		if (hostsleep_set) {
++			if (hostsleep_val && ret) {
++				CONFIG_TRACE("reset hostsleep %d => 0\n", dhd->hostsleep);
++				dhd->hostsleep = 0;
++				if (dhd->conf->insuspend & NO_TXDATA_IN_SUSPEND) {
++					dhd_txflowcontrol(dhd, ALL_INTERFACES, OFF);
++				}
++			} else if (!hostsleep_val && !ret) {
++				CONFIG_TRACE("set hostsleep %d => 0\n", dhd->hostsleep);
++				dhd->hostsleep = 0;
++				if (dhd->conf->insuspend & NO_TXDATA_IN_SUSPEND) {
++					dhd_txflowcontrol(dhd, ALL_INTERFACES, OFF);
++				}
++			}
++		}
++	}
++}
++
++#ifdef WL_EXT_WOWL
++#define WL_WOWL_TCPFIN	(1 << 26)
++typedef struct wl_wowl_pattern2 {
++	char cmd[4];
++	wl_wowl_pattern_t wowl_pattern;
++} wl_wowl_pattern2_t;
++static int
++dhd_conf_wowl_pattern(dhd_pub_t *dhd, bool add, char *data)
++{
++	uint buf_len = 0;
++	int	id, type, polarity, offset;
++	char cmd[4]="\0", mask[128]="\0", pattern[128]="\0", mask_tmp[128]="\0", *pmask_tmp;
++	uint32 masksize, patternsize, pad_len = 0;
++	wl_wowl_pattern2_t *wowl_pattern2 = NULL;
++	char *mask_and_pattern;
++	int ret = 0, i, j, v;
++
++	if (data) {
++		if (add)
++			strcpy(cmd, "add");
++		else
++			strcpy(cmd, "clr");
++		if (!strcmp(cmd, "clr")) {
++			CONFIG_TRACE("wowl_pattern clr\n");
++			ret = dhd_conf_set_bufiovar(dhd, 0, WLC_SET_VAR, "wowl_pattern", cmd,
++				sizeof(cmd), FALSE);
++			goto exit;
++		}
++		sscanf(data, "%d %d %d %d %s %s", &id, &type, &polarity, &offset,
++			mask_tmp, pattern);
++		masksize = strlen(mask_tmp) -2;
++		CONFIG_TRACE("0 mask_tmp=%s, masksize=%d\n", mask_tmp, masksize);
++
++		// add pading
++		if (masksize % 16)
++			pad_len = (16 - masksize % 16);
++		for (i=0; i<pad_len; i++)
++			strcat(mask_tmp, "0");
++		masksize += pad_len;
++		CONFIG_TRACE("1 mask_tmp=%s, masksize=%d\n", mask_tmp, masksize);
++
++		// translate 0x00 to 0, others to 1
++		j = 0;
++		pmask_tmp = &mask_tmp[2];
++		for (i=0; i<masksize/2; i++) {
++			if(strncmp(&pmask_tmp[i*2], "00", 2))
++				pmask_tmp[j] = '1';
++			else
++				pmask_tmp[j] = '0';
++			j++;
++		}
++		pmask_tmp[j] = '\0';
++		masksize = masksize / 2;
++		CONFIG_TRACE("2 mask_tmp=%s, masksize=%d\n", mask_tmp, masksize);
++
++		// reorder per 8bits
++		pmask_tmp = &mask_tmp[2];
++		for (i=0; i<masksize/8; i++) {
++			char c;
++			for (j=0; j<4; j++) {
++				c = pmask_tmp[i*8+j];
++				pmask_tmp[i*8+j] = pmask_tmp[(i+1)*8-j-1];
++				pmask_tmp[(i+1)*8-j-1] = c;
++			}
++		}
++		CONFIG_TRACE("3 mask_tmp=%s, masksize=%d\n", mask_tmp, masksize);
++
++		// translate 8bits to 1byte
++		j = 0; v = 0;
++		pmask_tmp = &mask_tmp[2];
++		strcpy(mask, "0x");
++		for (i=0; i<masksize; i++) {
++			v = (v<<1) | (pmask_tmp[i]=='1');
++			if (((i+1)%4) == 0) {
++				if (v < 10)
++					mask[j+2] = v + '0';
++				else
++					mask[j+2] = (v-10) + 'a';
++				j++;
++				v = 0;
++			}
++		}
++		mask[j+2] = '\0';
++		masksize = j/2;
++		CONFIG_TRACE("4 mask=%s, masksize=%d\n", mask, masksize);
++
++		patternsize = (strlen(pattern)-2)/2;
++		buf_len = sizeof(wl_wowl_pattern2_t) + patternsize + masksize;
++		wowl_pattern2 = kmalloc(buf_len, GFP_KERNEL);
++		if (wowl_pattern2 == NULL) {
++			CONFIG_ERROR("Failed to allocate buffer of %d bytes\n", buf_len);
++			goto exit;
++		}
++		memset(wowl_pattern2, 0, sizeof(wl_wowl_pattern2_t));
++
++		strncpy(wowl_pattern2->cmd, cmd, sizeof(cmd));
++		wowl_pattern2->wowl_pattern.id = id;
++		wowl_pattern2->wowl_pattern.type = 0;
++		wowl_pattern2->wowl_pattern.offset = offset;
++		mask_and_pattern = (char*)wowl_pattern2 + sizeof(wl_wowl_pattern2_t);
++
++		wowl_pattern2->wowl_pattern.masksize = masksize;
++		ret = wl_pattern_atoh(mask, mask_and_pattern);
++		if (ret == -1) {
++			CONFIG_ERROR("rejecting mask=%s\n", mask);
++			goto exit;
++		}
++
++		mask_and_pattern += wowl_pattern2->wowl_pattern.masksize;
++		wowl_pattern2->wowl_pattern.patternoffset = sizeof(wl_wowl_pattern_t) +
++			wowl_pattern2->wowl_pattern.masksize;
++
++		wowl_pattern2->wowl_pattern.patternsize = patternsize;
++		ret = wl_pattern_atoh(pattern, mask_and_pattern);
++		if (ret == -1) {
++			CONFIG_ERROR("rejecting pattern=%s\n", pattern);
++			goto exit;
++		}
++
++		CONFIG_TRACE("%s %d %s %s\n", cmd, offset, mask, pattern);
++
++		ret = dhd_conf_set_bufiovar(dhd, 0, WLC_SET_VAR, "wowl_pattern",
++			(char *)wowl_pattern2, buf_len, FALSE);
++	}
++
++exit:
++	if (wowl_pattern2)
++		kfree(wowl_pattern2);
++	return ret;
++}
++
++static int
++dhd_conf_wowl_wakeind(dhd_pub_t *dhd, bool clear)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	wl_wowl_wakeind_t *wake = NULL;
++	int ret = -1;
++	char clr[6]="clear", wakeind_str[32]="\0";
++
++	if (clear) {
++		CONFIG_TRACE("wowl_wakeind clear\n");
++		ret = dhd_conf_set_bufiovar(dhd, 0, WLC_SET_VAR, "wowl_wakeind",
++			clr, sizeof(clr), 0);
++	} else {
++		ret = dhd_conf_get_iovar(dhd, 0, WLC_GET_VAR, "wowl_wakeind",
++			iovar_buf, sizeof(iovar_buf));
++		if (!ret) {
++			wake = (wl_wowl_wakeind_t *) iovar_buf;
++			if (wake->ucode_wakeind & WL_WOWL_MAGIC)
++				strcpy(wakeind_str, "(MAGIC packet)");
++			if (wake->ucode_wakeind & WL_WOWL_NET)
++				strcpy(wakeind_str, "(Netpattern)");
++			if (wake->ucode_wakeind & WL_WOWL_DIS)
++				strcpy(wakeind_str, "(Disassoc/Deauth)");
++			if (wake->ucode_wakeind & WL_WOWL_BCN)
++				strcpy(wakeind_str, "(Loss of beacon)");
++			if (wake->ucode_wakeind & WL_WOWL_TCPKEEP_TIME)
++				strcpy(wakeind_str, "(TCPKA timeout)");
++			if (wake->ucode_wakeind & WL_WOWL_TCPKEEP_DATA)
++				strcpy(wakeind_str, "(TCPKA data)");
++			if (wake->ucode_wakeind & WL_WOWL_TCPFIN)
++				strcpy(wakeind_str, "(TCP FIN)");
++			CONFIG_MSG("wakeind=0x%x %s\n", wake->ucode_wakeind, wakeind_str);
++		}
++	}
++
++	return ret;
++}
++#endif
++
++int
++dhd_conf_mkeep_alive(dhd_pub_t *dhd, int ifidx, int id, int period,
++	char *packet, bool bcast)
++{
++	wl_mkeep_alive_pkt_t *mkeep_alive_pktp;
++	int ret = 0, len_bytes=0, buf_len=0;
++	char *buf = NULL, *iovar_buf = NULL;
++	uint8 *pdata;
++
++	CONFIG_TRACE("id=%d, period=%d, packet=%s\n", id, period, packet);
++	if (period >= 0) {
++		buf = kmalloc(WLC_IOCTL_SMLEN, GFP_KERNEL);
++		if (buf == NULL) {
++			CONFIG_ERROR("Failed to allocate buffer of %d bytes\n", WLC_IOCTL_SMLEN);
++			goto exit;
++		}
++		iovar_buf = kmalloc(WLC_IOCTL_SMLEN, GFP_KERNEL);
++		if (iovar_buf == NULL) {
++			CONFIG_ERROR("Failed to allocate buffer of %d bytes\n", WLC_IOCTL_SMLEN);
++			goto exit;
++		}
++		mkeep_alive_pktp = (wl_mkeep_alive_pkt_t *)buf;
++		mkeep_alive_pktp->version = htod16(WL_MKEEP_ALIVE_VERSION);
++		mkeep_alive_pktp->length = htod16(WL_MKEEP_ALIVE_FIXED_LEN);
++		mkeep_alive_pktp->keep_alive_id = id;
++		buf_len += WL_MKEEP_ALIVE_FIXED_LEN;
++		mkeep_alive_pktp->period_msec = period;
++		if (packet && strlen(packet)) {
++			len_bytes = wl_pattern_atoh(packet, (char *)mkeep_alive_pktp->data);
++			buf_len += len_bytes;
++			if (bcast) {
++				memcpy(mkeep_alive_pktp->data, &ether_bcast, ETHER_ADDR_LEN);
++			}
++			ret = dhd_conf_get_iovar(dhd, ifidx, WLC_GET_VAR, "cur_etheraddr",
++				iovar_buf, WLC_IOCTL_SMLEN);
++			if (!ret) {
++				pdata = mkeep_alive_pktp->data;
++				memcpy(pdata+6, iovar_buf, ETHER_ADDR_LEN);
++			}
++		}
++		mkeep_alive_pktp->len_bytes = htod16(len_bytes);
++		ret = dhd_conf_set_bufiovar(dhd, ifidx, WLC_SET_VAR, "mkeep_alive",
++			buf, buf_len, FALSE);
++	}
++
++exit:
++	if (buf)
++		kfree(buf);
++	if (iovar_buf)
++		kfree(iovar_buf);
++	return ret;
++}
++
++#ifdef ARP_OFFLOAD_SUPPORT
++void
++dhd_conf_set_garp(dhd_pub_t *dhd, int ifidx, uint32 ipa, bool enable)
++{
++	int i, len = 0, total_len = WLC_IOCTL_SMLEN;
++	char *iovar_buf = NULL, *packet = NULL;
++
++	if (!dhd->conf->garp || ifidx != 0 || !(dhd->op_mode & DHD_FLAG_STA_MODE))
++		return;
++
++	CONFIG_TRACE("enable=%d\n", enable);
++
++	if (enable) {
++		iovar_buf = kmalloc(total_len, GFP_KERNEL);
++		if (iovar_buf == NULL) {
++			CONFIG_ERROR("Failed to allocate buffer of %d bytes\n", total_len);
++			goto exit;
++		}
++		packet = kmalloc(total_len, GFP_KERNEL);
++		if (packet == NULL) {
++			CONFIG_ERROR("Failed to allocate buffer of %d bytes\n", total_len);
++			goto exit;
++		}
++		dhd_conf_get_iovar(dhd, ifidx, WLC_GET_VAR, "cur_etheraddr", iovar_buf, total_len);
++
++		len += snprintf(packet+len, total_len, "0xffffffffffff");
++		for (i=0; i<ETHER_ADDR_LEN; i++)
++			len += snprintf(packet+len, total_len, "%02x", iovar_buf[i]);
++		len += snprintf(packet+len, total_len, "08060001080006040001");
++		for (i=0; i<ETHER_ADDR_LEN; i++)
++			len += snprintf(packet+len, total_len, "%02x", iovar_buf[i]);
++		len += snprintf(packet+len, total_len, "%02x%02x%02x%02x",
++			ipa&0xff, (ipa>>8)&0xff, (ipa>>16)&0xff, (ipa>>24)&0xff);
++		len += snprintf(packet+len, total_len, "ffffffffffffc0a80101000000000000000000000000000000000000");
++	}
++
++	dhd_conf_mkeep_alive(dhd, ifidx, 0, dhd->conf->keep_alive_period, packet, TRUE);
++
++exit:
++	if (iovar_buf)
++		kfree(iovar_buf);
++	if (packet)
++		kfree(packet);
++	return;
++}
++#endif
++
++uint
++dhd_conf_get_insuspend(dhd_pub_t *dhd, uint mask)
++{
++	uint insuspend = 0;
++
++	if (dhd->op_mode & DHD_FLAG_STA_MODE) {
++		insuspend = dhd->conf->insuspend &
++			(NO_EVENT_IN_SUSPEND | NO_TXDATA_IN_SUSPEND | NO_TXCTL_IN_SUSPEND |
++			ROAM_OFFLOAD_IN_SUSPEND | WOWL_IN_SUSPEND);
++	} else if (dhd->op_mode & DHD_FLAG_HOSTAP_MODE) {
++		insuspend = dhd->conf->insuspend &
++			(NO_EVENT_IN_SUSPEND | NO_TXDATA_IN_SUSPEND | NO_TXCTL_IN_SUSPEND |
++			AP_DOWN_IN_SUSPEND | AP_FILTER_IN_SUSPEND);
++	}
++
++	return (insuspend & mask);
++}
++
++#ifdef SUSPEND_EVENT
++void
++dhd_conf_set_suspend_event(dhd_pub_t *dhd, int suspend)
++{
++	struct dhd_conf *conf = dhd->conf;
++	struct ether_addr bssid;
++	char suspend_eventmask[WL_EVENTING_MASK_LEN];
++	wl_event_msg_t msg;
++	int pm;
++#ifdef WL_CFG80211
++	struct net_device *net;
++#endif /* defined(WL_CFG80211) */
++
++	CONFIG_TRACE("Enter\n");
++	if (suspend) {
++#ifdef PROP_TXSTATUS
++#if defined(BCMSDIO) || defined(BCMDBUS)
++		if (dhd->wlfc_enabled) {
++			dhd_wlfc_deinit(dhd);
++			conf->wlfc = TRUE;
++		} else {
++			conf->wlfc = FALSE;
++		}
++#endif /* BCMSDIO || BCMDBUS */
++#endif /* PROP_TXSTATUS */
++		dhd_conf_get_iovar(dhd, 0, WLC_GET_VAR, "event_msgs",
++			conf->resume_eventmask, sizeof(conf->resume_eventmask));
++		memset(suspend_eventmask, 0, sizeof(suspend_eventmask));
++		setbit(suspend_eventmask, WLC_E_ESCAN_RESULT);
++		dhd_conf_set_bufiovar(dhd, 0, WLC_SET_VAR, "event_msgs",
++			suspend_eventmask, sizeof(suspend_eventmask), FALSE);
++		if (dhd->op_mode & DHD_FLAG_STA_MODE) {
++			memset(&bssid, 0, ETHER_ADDR_LEN);
++			dhd_wl_ioctl_cmd(dhd, WLC_GET_BSSID, &bssid, ETHER_ADDR_LEN, FALSE, 0);
++			if (memcmp(&ether_null, &bssid, ETHER_ADDR_LEN))
++				memcpy(&conf->bssid_insuspend, &bssid, ETHER_ADDR_LEN);
++			else
++				memset(&conf->bssid_insuspend, 0, ETHER_ADDR_LEN);
++		}
++	}
++	else {
++		dhd_conf_set_bufiovar(dhd, 0, WLC_SET_VAR, "event_msgs",
++			conf->resume_eventmask, sizeof(conf->resume_eventmask), FALSE);
++		if (dhd->op_mode & DHD_FLAG_STA_MODE) {
++			if (memcmp(&ether_null, &conf->bssid_insuspend, ETHER_ADDR_LEN)) {
++				memset(&bssid, 0, ETHER_ADDR_LEN);
++				dhd_wl_ioctl_cmd(dhd, WLC_GET_BSSID, &bssid, ETHER_ADDR_LEN,
++					FALSE, 0);
++				if (memcmp(&ether_null, &bssid, ETHER_ADDR_LEN)) {
++					dhd_conf_set_intiovar(dhd, WLC_SET_PM, "WLC_SET_PM", 0, 0, FALSE);
++					dhd_conf_set_bufiovar(dhd, 0, WLC_SET_VAR, "send_nulldata",
++						(char *)&bssid, ETHER_ADDR_LEN, FALSE);
++					OSL_SLEEP(100);
++					if (conf->pm >= 0)
++						pm = conf->pm;
++					else
++						pm = PM_FAST;
++					dhd_conf_set_intiovar(dhd, WLC_SET_PM, "WLC_SET_PM", pm, 0, FALSE);
++				} else {
++					CONFIG_TRACE("send WLC_E_DEAUTH_IND event\n");
++					bzero(&msg, sizeof(wl_event_msg_t));
++					memcpy(&msg.addr, &conf->bssid_insuspend, ETHER_ADDR_LEN);
++					msg.event_type = hton32(WLC_E_DEAUTH_IND);
++					msg.status = 0;
++					msg.reason = hton32(DOT11_RC_DEAUTH_LEAVING);
++#if defined(WL_EXT_IAPSTA) || defined(USE_IW)
++					wl_ext_event_send(dhd->event_params, &msg, NULL);
++#endif
++#ifdef WL_CFG80211
++					net = dhd_idx2net(dhd, 0);
++					if (net) {
++						wl_cfg80211_event(net, &msg, NULL);
++					}
++#endif /* defined(WL_CFG80211) */
++				}
++			}
++#ifdef PROP_TXSTATUS
++#if defined(BCMSDIO) || defined(BCMDBUS)
++			if (conf->wlfc) {
++				dhd_wlfc_init(dhd);
++				dhd_conf_set_intiovar(dhd, WLC_UP, "WLC_UP", 0, 0, FALSE);
++			}
++#endif
++#endif /* PROP_TXSTATUS */
++		}
++	}
++
++}
++#endif
++
++#if defined(WL_CFG80211) || defined(WL_ESCAN)
++static void
++dhd_conf_wait_event_complete(struct dhd_pub *dhd, int ifidx)
++{
++	s32 timeout = -1;
++
++	timeout = wait_event_interruptible_timeout(dhd->conf->event_complete,
++		wl_ext_event_complete(dhd, ifidx), msecs_to_jiffies(10000));
++	if (timeout <= 0 || !wl_ext_event_complete(dhd, ifidx)) {
++		wl_ext_event_complete(dhd, ifidx);
++		CONFIG_ERROR("timeout\n");
++	}
++}
++#endif
++
++int
++dhd_conf_set_suspend_resume(dhd_pub_t *dhd, int suspend)
++{
++	struct dhd_conf *conf = dhd->conf;
++	uint insuspend = 0;
++	int pm;
++#ifdef BCMSDIO
++	uint32 intstatus = 0;
++	int ret = 0;
++#endif
++#ifdef WL_EXT_WOWL
++	int i;
++#endif
++
++	insuspend = dhd_conf_get_insuspend(dhd, ALL_IN_SUSPEND);
++	if (insuspend)
++		CONFIG_MSG("op_mode %d, suspend %d, suspended %d, insuspend 0x%x, suspend_mode=%d\n",
++			dhd->op_mode, suspend, conf->suspended, insuspend, conf->suspend_mode);
++
++	if (conf->suspended == suspend || !dhd->up) {
++		return 0;
++	}
++
++	if (suspend) {
++		if (dhd->op_mode & DHD_FLAG_STA_MODE) {
++			dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "roam_off",
++				dhd->conf->roam_off_suspend, 0, FALSE);
++			dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "bcn_li_dtim",
++				dhd->conf->suspend_bcn_li_dtim, 0, FALSE);
++			if (insuspend & ROAM_OFFLOAD_IN_SUSPEND)
++				dhd_conf_enable_roam_offload(dhd, 2);
++		} else if (dhd->op_mode & DHD_FLAG_HOSTAP_MODE) {
++			if (insuspend & AP_DOWN_IN_SUSPEND) {
++				dhd_conf_set_intiovar(dhd, WLC_DOWN, "WLC_DOWN", 1, 0, FALSE);
++			}
++		}
++#if defined(WL_CFG80211) || defined(WL_ESCAN)
++		if (insuspend & (NO_EVENT_IN_SUSPEND|NO_TXCTL_IN_SUSPEND|WOWL_IN_SUSPEND)) {
++			if (conf->suspend_mode == PM_NOTIFIER)
++				dhd_conf_wait_event_complete(dhd, 0);
++		}
++#endif
++		if (insuspend & NO_TXDATA_IN_SUSPEND) {
++			dhd_txflowcontrol(dhd, ALL_INTERFACES, ON);
++		}
++#if defined(WL_CFG80211) || defined(WL_ESCAN)
++		if (insuspend & (NO_EVENT_IN_SUSPEND|NO_TXCTL_IN_SUSPEND|WOWL_IN_SUSPEND)) {
++			if (conf->suspend_mode == PM_NOTIFIER)
++				wl_ext_user_sync(dhd, 0, TRUE);
++		}
++#endif
++#ifdef SUSPEND_EVENT
++		if (insuspend & NO_EVENT_IN_SUSPEND) {
++			dhd_conf_set_suspend_event(dhd, suspend);
++		}
++#endif
++		if (dhd->op_mode & DHD_FLAG_STA_MODE) {
++			if (conf->pm_in_suspend >= 0)
++				pm = conf->pm_in_suspend;
++			else if (conf->pm >= 0)
++				pm = conf->pm;
++			else
++				pm = PM_FAST;
++			dhd_conf_set_intiovar(dhd, WLC_SET_PM, "WLC_SET_PM", pm, 0, FALSE);
++		}
++		dhd_conf_set_wl_cmd(dhd, conf->wl_suspend, FALSE);
++#ifdef WL_EXT_WOWL
++		if ((insuspend & WOWL_IN_SUSPEND) && dhd_master_mode) {
++			dhd_conf_wowl_pattern(dhd, FALSE, "clr");
++			for(i=0; i<conf->pkt_filter_add.count; i++) {
++				dhd_conf_wowl_pattern(dhd, TRUE, conf->pkt_filter_add.filter[i]);
++			}
++			dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "wowl", conf->wowl, 0, FALSE);
++			dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "wowl_activate", 1, 0, FALSE);
++			dhd_conf_wowl_wakeind(dhd, TRUE);
++			dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "hostsleep", 1, 0, FALSE);
++#ifdef BCMSDIO
++			ret = dhd_bus_sleep(dhd, TRUE, &intstatus);
++			CONFIG_TRACE("ret = %d, intstatus = 0x%x\n", ret, intstatus);
++#endif
++		} else
++#endif
++		if (insuspend & NO_TXCTL_IN_SUSPEND) {
++			dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "hostsleep", 2, 0, FALSE);
++#ifdef BCMSDIO
++			ret = dhd_bus_sleep(dhd, TRUE, &intstatus);
++			CONFIG_TRACE("ret = %d, intstatus = 0x%x\n", ret, intstatus);
++#endif
++		}
++		conf->suspended = TRUE;
++	} else {
++		if (insuspend & (WOWL_IN_SUSPEND | NO_TXCTL_IN_SUSPEND)) {
++			dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "hostsleep", 0, 0, FALSE);
++		}
++#ifdef WL_EXT_WOWL
++		if (insuspend & WOWL_IN_SUSPEND) {
++			dhd_conf_wowl_wakeind(dhd, FALSE);
++			dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "wowl_activate", 0, 0, FALSE);
++			dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "wowl", 0, 0, FALSE);
++			dhd_conf_wowl_pattern(dhd, FALSE, "clr");
++		}
++#endif
++		dhd_conf_set_wl_cmd(dhd, conf->wl_resume, FALSE);
++		dhd_conf_get_iovar(dhd, 0, WLC_GET_PM, "WLC_GET_PM", (char *)&pm, sizeof(pm));
++		CONFIG_TRACE("PM in suspend = %d\n", pm);
++#ifdef SUSPEND_EVENT
++		if (insuspend & NO_EVENT_IN_SUSPEND) {
++			dhd_conf_set_suspend_event(dhd, suspend);
++		}
++#endif
++#if defined(WL_CFG80211) || defined(WL_ESCAN)
++		if (insuspend & (NO_EVENT_IN_SUSPEND|NO_TXCTL_IN_SUSPEND|WOWL_IN_SUSPEND)) {
++			if (conf->suspend_mode == PM_NOTIFIER)
++				wl_ext_user_sync(dhd, 0, FALSE);
++		}
++#endif
++		if (insuspend & NO_TXDATA_IN_SUSPEND) {
++			dhd_txflowcontrol(dhd, ALL_INTERFACES, OFF);
++		}
++		if (dhd->op_mode & DHD_FLAG_STA_MODE) {
++			if (insuspend & ROAM_OFFLOAD_IN_SUSPEND)
++				dhd_conf_enable_roam_offload(dhd, 0);
++			dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "bcn_li_dtim", 0, 0, FALSE);
++			dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "roam_off",
++				dhd->conf->roam_off, 0, FALSE);
++		} else if (dhd->op_mode & DHD_FLAG_HOSTAP_MODE) {
++			if (insuspend & AP_DOWN_IN_SUSPEND) {
++				dhd_conf_set_intiovar(dhd, WLC_UP, "WLC_UP", 0, 0, FALSE);
++			}
++		}
++		if (dhd->op_mode & DHD_FLAG_STA_MODE) {
++			if (conf->pm >= 0)
++				pm = conf->pm;
++			else
++				pm = PM_FAST;
++			dhd_conf_set_intiovar(dhd, WLC_SET_PM, "WLC_SET_PM", pm, 0, FALSE);
++		}
++		conf->suspended = FALSE;
++	}
++
++	return 0;
++}
++
++#ifdef PROP_TXSTATUS
++int
++dhd_conf_get_disable_proptx(dhd_pub_t *dhd)
++{
++	struct dhd_conf *conf = dhd->conf;
++	int disable_proptx = -1;
++	int fw_proptx = 0;
++
++	/* check fw proptx priority:
++	  * 1st: check fw support by wl cap
++	  * 2nd: 4334/43340/43341/43241 support proptx but not show in wl cap, so enable it by default
++	  * 	   if you would like to disable it, please set disable_proptx=1 in config.txt
++	  * 3th: disable when proptxstatus not support in wl cap
++	  */
++	if (FW_SUPPORTED(dhd, proptxstatus)) {
++		fw_proptx = 1;
++	} else if (conf->chip == BCM4334_CHIP_ID || conf->chip == BCM43340_CHIP_ID ||
++			dhd->conf->chip == BCM43340_CHIP_ID || conf->chip == BCM4324_CHIP_ID) {
++		fw_proptx = 1;
++	} else {
++		fw_proptx = 0;
++	}
++
++	/* returned disable_proptx value:
++	  * -1: disable in STA and enable in P2P(follow original dhd settings when PROP_TXSTATUS_VSDB enabled)
++	  * 0: depend on fw support
++	  * 1: always disable proptx
++	  */
++	if (conf->disable_proptx == 0) {
++		// check fw support as well
++		if (fw_proptx)
++			disable_proptx = 0;
++		else
++			disable_proptx = 1;
++	} else if (conf->disable_proptx >= 1) {
++		disable_proptx = 1;
++	} else {
++		// check fw support as well
++		if (fw_proptx)
++			disable_proptx = -1;
++		else
++			disable_proptx = 1;
++	}
++
++	CONFIG_MSG("fw_proptx=%d, disable_proptx=%d\n", fw_proptx, disable_proptx);
++
++	return disable_proptx;
++}
++#endif
++
++uint
++pick_config_vars(char *varbuf, uint len, uint start_pos, char *pickbuf, int picklen)
++{
++	bool findNewline, changenewline=FALSE, pick=FALSE;
++	int column;
++	uint n, pick_column=0;
++
++	findNewline = FALSE;
++	column = 0;
++
++	if (start_pos >= len) {
++		CONFIG_ERROR("wrong start pos\n");
++		return 0;
++	}
++
++	for (n = start_pos; n < len; n++) {
++		if (varbuf[n] == '\r')
++			continue;
++		if ((findNewline || changenewline) && varbuf[n] != '\n')
++			continue;
++		findNewline = FALSE;
++		if (varbuf[n] == '#') {
++			findNewline = TRUE;
++			continue;
++		}
++		if (varbuf[n] == '\\') {
++			changenewline = TRUE;
++			continue;
++		}
++		if (!changenewline && varbuf[n] == '\n') {
++			if (column == 0)
++				continue;
++			column = 0;
++			continue;
++		}
++		if (changenewline && varbuf[n] == '\n') {
++			changenewline = FALSE;
++			continue;
++		}
++
++		if (column==0 && !pick) { // start to pick
++			pick = TRUE;
++			column++;
++			pick_column = 0;
++		} else {
++			if (pick && column==0) { // stop to pick
++				pick = FALSE;
++				break;
++			} else
++				column++;
++		}
++		if (pick) {
++			if (varbuf[n] == 0x9)
++				continue;
++			if (pick_column >= picklen)
++				break;
++			pickbuf[pick_column] = varbuf[n];
++			pick_column++;
++		}
++	}
++
++	return n; // return current position
++}
++
++bool
++dhd_conf_read_chiprev(dhd_pub_t *dhd, int *chip_match,
++	char *full_param, uint len_param)
++{
++	char *data = full_param+len_param, *pick_tmp, *pch;
++	uint chip = 0, rev = 0;
++
++	/* Process chip, regrev:
++	 * chip=[chipid], rev==[rev]
++	 * Ex: chip=0x4359, rev=9
++	 */
++	if (!strncmp("chip=", full_param, len_param)) {
++		chip = (int)simple_strtol(data, NULL, 0);
++		pick_tmp = data;
++		pch = bcmstrstr(pick_tmp, "rev=");
++		if (pch) {
++			rev = (int)simple_strtol(pch+strlen("rev="), NULL, 0);
++		}
++		if (chip == dhd->conf->chip && rev == dhd->conf->chiprev)
++			*chip_match = 1;
++		else
++			*chip_match = 0;
++		CONFIG_MSG("chip=0x%x, rev=%d, chip_match=%d\n", chip, rev, *chip_match);
++	}
++
++	return TRUE;
++}
++
++bool
++dhd_conf_read_log_level(dhd_pub_t *dhd, char *full_param, uint len_param)
++{
++	char *data = full_param+len_param;
++
++	if (!strncmp("dhd_msg_level=", full_param, len_param)) {
++		dhd_msg_level = (int)simple_strtol(data, NULL, 0);
++		CONFIG_MSG("dhd_msg_level = 0x%X\n", dhd_msg_level);
++	}
++	else if (!strncmp("dump_msg_level=", full_param, len_param)) {
++		dump_msg_level = (int)simple_strtol(data, NULL, 0);
++		CONFIG_MSG("dump_msg_level = 0x%X\n", dump_msg_level);
++	}
++#ifdef BCMSDIO
++	else if (!strncmp("sd_msglevel=", full_param, len_param)) {
++		sd_msglevel = (int)simple_strtol(data, NULL, 0);
++		CONFIG_MSG("sd_msglevel = 0x%X\n", sd_msglevel);
++	}
++#endif
++#ifdef BCMDBUS
++	else if (!strncmp("dbus_msglevel=", full_param, len_param)) {
++		dbus_msglevel = (int)simple_strtol(data, NULL, 0);
++		CONFIG_MSG("dbus_msglevel = 0x%X\n", dbus_msglevel);
++	}
++#endif
++	else if (!strncmp("android_msg_level=", full_param, len_param)) {
++		android_msg_level = (int)simple_strtol(data, NULL, 0);
++		CONFIG_MSG("android_msg_level = 0x%X\n", android_msg_level);
++	}
++	else if (!strncmp("config_msg_level=", full_param, len_param)) {
++		config_msg_level = (int)simple_strtol(data, NULL, 0);
++		CONFIG_MSG("config_msg_level = 0x%X\n", config_msg_level);
++	}
++#ifdef WL_CFG80211
++	else if (!strncmp("wl_dbg_level=", full_param, len_param)) {
++		wl_dbg_level = (int)simple_strtol(data, NULL, 0);
++		CONFIG_MSG("wl_dbg_level = 0x%X\n", wl_dbg_level);
++	}
++#endif
++#if defined(WL_WIRELESS_EXT)
++	else if (!strncmp("iw_msg_level=", full_param, len_param)) {
++		iw_msg_level = (int)simple_strtol(data, NULL, 0);
++		CONFIG_MSG("iw_msg_level = 0x%X\n", iw_msg_level);
++	}
++#endif
++#if defined(DHD_DEBUG)
++	else if (!strncmp("dhd_console_ms=", full_param, len_param)) {
++		dhd_console_ms = (int)simple_strtol(data, NULL, 0);
++		CONFIG_MSG("dhd_console_ms = 0x%X\n", dhd_console_ms);
++	}
++#endif
++	else
++		return false;
++
++	return true;
++}
++
++void
++dhd_conf_read_wme_ac_value(wme_param_t *wme, char *pick, int ac_val)
++{
++	char *pick_tmp, *pch;
++
++	pick_tmp = pick;
++	pch = bcmstrstr(pick_tmp, "aifsn ");
++	if (pch) {
++		wme->aifsn[ac_val] = (int)simple_strtol(pch+strlen("aifsn "), NULL, 0);
++		CONFIG_MSG("ac_val=%d, aifsn=%d\n", ac_val, wme->aifsn[ac_val]);
++	}
++	pick_tmp = pick;
++	pch = bcmstrstr(pick_tmp, "ecwmin ");
++	if (pch) {
++		wme->ecwmin[ac_val] = (int)simple_strtol(pch+strlen("ecwmin "), NULL, 0);
++		CONFIG_MSG("ac_val=%d, ecwmin=%d\n", ac_val, wme->ecwmin[ac_val]);
++	}
++	pick_tmp = pick;
++	pch = bcmstrstr(pick_tmp, "ecwmax ");
++	if (pch) {
++		wme->ecwmax[ac_val] = (int)simple_strtol(pch+strlen("ecwmax "), NULL, 0);
++		CONFIG_MSG("ac_val=%d, ecwmax=%d\n", ac_val, wme->ecwmax[ac_val]);
++	}
++	pick_tmp = pick;
++	pch = bcmstrstr(pick_tmp, "txop ");
++	if (pch) {
++		wme->txop[ac_val] = (int)simple_strtol(pch+strlen("txop "), NULL, 0);
++		CONFIG_MSG("ac_val=%d, txop=0x%x\n", ac_val, wme->txop[ac_val]);
++	}
++
++}
++
++bool
++dhd_conf_read_wme_ac_params(dhd_pub_t *dhd, char *full_param, uint len_param)
++{
++	struct dhd_conf *conf = dhd->conf;
++	char *data = full_param+len_param;
++
++	// wme_ac_sta_be=aifsn 1 ecwmin 2 ecwmax 3 txop 0x5e
++	// wme_ac_sta_vo=aifsn 1 ecwmin 1 ecwmax 1 txop 0x5e
++
++	if (!strncmp("force_wme_ac=", full_param, len_param)) {
++		conf->force_wme_ac = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("force_wme_ac = %d\n", conf->force_wme_ac);
++	}
++	else if (!strncmp("wme_ac_sta_be=", full_param, len_param)) {
++		dhd_conf_read_wme_ac_value(&conf->wme_sta, data, AC_BE);
++	}
++	else if (!strncmp("wme_ac_sta_bk=", full_param, len_param)) {
++		dhd_conf_read_wme_ac_value(&conf->wme_sta, data, AC_BK);
++	}
++	else if (!strncmp("wme_ac_sta_vi=", full_param, len_param)) {
++		dhd_conf_read_wme_ac_value(&conf->wme_sta, data, AC_VI);
++	}
++	else if (!strncmp("wme_ac_sta_vo=", full_param, len_param)) {
++		dhd_conf_read_wme_ac_value(&conf->wme_sta, data, AC_VO);
++	}
++	else if (!strncmp("wme_ac_ap_be=", full_param, len_param)) {
++		dhd_conf_read_wme_ac_value(&conf->wme_ap, data, AC_BE);
++	}
++	else if (!strncmp("wme_ac_ap_bk=", full_param, len_param)) {
++		dhd_conf_read_wme_ac_value(&conf->wme_ap, data, AC_BK);
++	}
++	else if (!strncmp("wme_ac_ap_vi=", full_param, len_param)) {
++		dhd_conf_read_wme_ac_value(&conf->wme_ap, data, AC_VI);
++	}
++	else if (!strncmp("wme_ac_ap_vo=", full_param, len_param)) {
++		dhd_conf_read_wme_ac_value(&conf->wme_ap, data, AC_VO);
++	}
++	else
++		return false;
++
++	return true;
++}
++
++#ifdef BCMSDIO
++bool
++dhd_conf_read_fw_by_mac(dhd_pub_t *dhd, char *full_param, uint len_param)
++{
++	int i, j;
++	char *pch, *pick_tmp;
++	wl_mac_list_t *mac_list;
++	wl_mac_range_t *mac_range;
++	struct dhd_conf *conf = dhd->conf;
++	char *data = full_param+len_param;
++
++	/* Process fw_by_mac:
++	 * fw_by_mac=[fw_mac_num] \
++	 *  [fw_name1] [mac_num1] [oui1-1] [nic_start1-1] [nic_end1-1] \
++	 *                                    [oui1-1] [nic_start1-1] [nic_end1-1]... \
++	 *                                    [oui1-n] [nic_start1-n] [nic_end1-n] \
++	 *  [fw_name2] [mac_num2] [oui2-1] [nic_start2-1] [nic_end2-1] \
++	 *                                    [oui2-1] [nic_start2-1] [nic_end2-1]... \
++	 *                                    [oui2-n] [nic_start2-n] [nic_end2-n] \
++	 * Ex: fw_by_mac=2 \
++	 *  fw_bcmdhd1.bin 2 0x0022F4 0xE85408 0xE8549D 0x983B16 0x3557A9 0x35582A \
++	 *  fw_bcmdhd2.bin 3 0x0022F4 0xE85408 0xE8549D 0x983B16 0x3557A9 0x35582A \
++	 *                           0x983B16 0x916157 0x916487
++	 */
++
++	if (!strncmp("fw_by_mac=", full_param, len_param)) {
++		dhd_conf_free_mac_list(&conf->fw_by_mac);
++		pick_tmp = data;
++		pch = bcmstrtok(&pick_tmp, " ", 0);
++		conf->fw_by_mac.count = (uint32)simple_strtol(pch, NULL, 0);
++		if (!(mac_list = kmalloc(sizeof(wl_mac_list_t)*conf->fw_by_mac.count,
++				GFP_KERNEL))) {
++			conf->fw_by_mac.count = 0;
++			CONFIG_ERROR("kmalloc failed\n");
++		}
++		CONFIG_MSG("fw_count=%d\n", conf->fw_by_mac.count);
++		conf->fw_by_mac.m_mac_list_head = mac_list;
++		for (i=0; i<conf->fw_by_mac.count; i++) {
++			pch = bcmstrtok(&pick_tmp, " ", 0);
++			strcpy(mac_list[i].name, pch);
++			pch = bcmstrtok(&pick_tmp, " ", 0);
++			mac_list[i].count = (uint32)simple_strtol(pch, NULL, 0);
++			CONFIG_MSG("name=%s, mac_count=%d\n",
++				mac_list[i].name, mac_list[i].count);
++			if (!(mac_range = kmalloc(sizeof(wl_mac_range_t)*mac_list[i].count,
++					GFP_KERNEL))) {
++				mac_list[i].count = 0;
++				CONFIG_ERROR("kmalloc failed\n");
++				break;
++			}
++			mac_list[i].mac = mac_range;
++			for (j=0; j<mac_list[i].count; j++) {
++				pch = bcmstrtok(&pick_tmp, " ", 0);
++				mac_range[j].oui = (uint32)simple_strtol(pch, NULL, 0);
++				pch = bcmstrtok(&pick_tmp, " ", 0);
++				mac_range[j].nic_start = (uint32)simple_strtol(pch, NULL, 0);
++				pch = bcmstrtok(&pick_tmp, " ", 0);
++				mac_range[j].nic_end = (uint32)simple_strtol(pch, NULL, 0);
++				CONFIG_MSG("oui=0x%06X, nic_start=0x%06X, nic_end=0x%06X\n",
++					mac_range[j].oui, mac_range[j].nic_start, mac_range[j].nic_end);
++			}
++		}
++	}
++	else
++		return false;
++
++	return true;
++}
++
++bool
++dhd_conf_read_nv_by_mac(dhd_pub_t *dhd, char *full_param, uint len_param)
++{
++	int i, j;
++	char *pch, *pick_tmp;
++	wl_mac_list_t *mac_list;
++	wl_mac_range_t *mac_range;
++	struct dhd_conf *conf = dhd->conf;
++	char *data = full_param+len_param;
++
++	/* Process nv_by_mac:
++	 * [nv_by_mac]: The same format as fw_by_mac
++	 */
++	if (!strncmp("nv_by_mac=", full_param, len_param)) {
++		dhd_conf_free_mac_list(&conf->nv_by_mac);
++		pick_tmp = data;
++		pch = bcmstrtok(&pick_tmp, " ", 0);
++		conf->nv_by_mac.count = (uint32)simple_strtol(pch, NULL, 0);
++		if (!(mac_list = kmalloc(sizeof(wl_mac_list_t)*conf->nv_by_mac.count,
++				GFP_KERNEL))) {
++			conf->nv_by_mac.count = 0;
++			CONFIG_ERROR("kmalloc failed\n");
++		}
++		CONFIG_MSG("nv_count=%d\n", conf->nv_by_mac.count);
++		conf->nv_by_mac.m_mac_list_head = mac_list;
++		for (i=0; i<conf->nv_by_mac.count; i++) {
++			pch = bcmstrtok(&pick_tmp, " ", 0);
++			strcpy(mac_list[i].name, pch);
++			pch = bcmstrtok(&pick_tmp, " ", 0);
++			mac_list[i].count = (uint32)simple_strtol(pch, NULL, 0);
++			CONFIG_MSG("name=%s, mac_count=%d\n",
++				mac_list[i].name, mac_list[i].count);
++			if (!(mac_range = kmalloc(sizeof(wl_mac_range_t)*mac_list[i].count,
++					GFP_KERNEL))) {
++				mac_list[i].count = 0;
++				CONFIG_ERROR("kmalloc failed\n");
++				break;
++			}
++			mac_list[i].mac = mac_range;
++			for (j=0; j<mac_list[i].count; j++) {
++				pch = bcmstrtok(&pick_tmp, " ", 0);
++				mac_range[j].oui = (uint32)simple_strtol(pch, NULL, 0);
++				pch = bcmstrtok(&pick_tmp, " ", 0);
++				mac_range[j].nic_start = (uint32)simple_strtol(pch, NULL, 0);
++				pch = bcmstrtok(&pick_tmp, " ", 0);
++				mac_range[j].nic_end = (uint32)simple_strtol(pch, NULL, 0);
++				CONFIG_MSG("oui=0x%06X, nic_start=0x%06X, nic_end=0x%06X\n",
++					mac_range[j].oui, mac_range[j].nic_start, mac_range[j].nic_end);
++			}
++		}
++	}
++	else
++		return false;
++
++	return true;
++}
++#endif
++
++bool
++dhd_conf_read_nv_by_chip(dhd_pub_t *dhd, char *full_param, uint len_param)
++{
++	int i;
++	char *pch, *pick_tmp;
++	wl_chip_nv_path_t *chip_nv_path;
++	struct dhd_conf *conf = dhd->conf;
++	char *data = full_param+len_param;
++
++	/* Process nv_by_chip:
++	 * nv_by_chip=[nv_chip_num] \
++	 *  [chip1] [chiprev1] [nv_name1] [chip2] [chiprev2] [nv_name2] \
++	 * Ex: nv_by_chip=2 \
++	 *  43430 0 nvram_ap6212.txt 43430 1 nvram_ap6212a.txt \
++	 */
++	if (!strncmp("nv_by_chip=", full_param, len_param)) {
++		dhd_conf_free_chip_nv_path_list(&conf->nv_by_chip);
++		pick_tmp = data;
++		pch = bcmstrtok(&pick_tmp, " ", 0);
++		conf->nv_by_chip.count = (uint32)simple_strtol(pch, NULL, 0);
++		if (!(chip_nv_path = kmalloc(sizeof(wl_mac_list_t)*conf->nv_by_chip.count,
++				GFP_KERNEL))) {
++			conf->nv_by_chip.count = 0;
++			CONFIG_ERROR("kmalloc failed\n");
++		}
++		CONFIG_MSG("nv_by_chip_count=%d\n", conf->nv_by_chip.count);
++		conf->nv_by_chip.m_chip_nv_path_head = chip_nv_path;
++		for (i=0; i<conf->nv_by_chip.count; i++) {
++			pch = bcmstrtok(&pick_tmp, " ", 0);
++			chip_nv_path[i].chip = (uint32)simple_strtol(pch, NULL, 0);
++			pch = bcmstrtok(&pick_tmp, " ", 0);
++			chip_nv_path[i].chiprev = (uint32)simple_strtol(pch, NULL, 0);
++			pch = bcmstrtok(&pick_tmp, " ", 0);
++			strcpy(chip_nv_path[i].name, pch);
++			CONFIG_MSG("chip=0x%x, chiprev=%d, name=%s\n",
++				chip_nv_path[i].chip, chip_nv_path[i].chiprev, chip_nv_path[i].name);
++		}
++	}
++	else
++		return false;
++
++	return true;
++}
++
++bool
++dhd_conf_read_roam_params(dhd_pub_t *dhd, char *full_param, uint len_param)
++{
++	struct dhd_conf *conf = dhd->conf;
++	char *data = full_param+len_param;
++
++	if (!strncmp("roam_off=", full_param, len_param)) {
++		if (!strncmp(data, "0", 1))
++			conf->roam_off = 0;
++		else
++			conf->roam_off = 1;
++		CONFIG_MSG("roam_off = %d\n", conf->roam_off);
++	}
++	else if (!strncmp("roam_off_suspend=", full_param, len_param)) {
++		if (!strncmp(data, "0", 1))
++			conf->roam_off_suspend = 0;
++		else
++			conf->roam_off_suspend = 1;
++		CONFIG_MSG("roam_off_suspend = %d\n", conf->roam_off_suspend);
++	}
++	else if (!strncmp("roam_trigger=", full_param, len_param)) {
++		conf->roam_trigger[0] = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("roam_trigger = %d\n", conf->roam_trigger[0]);
++	}
++	else if (!strncmp("roam_scan_period=", full_param, len_param)) {
++		conf->roam_scan_period[0] = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("roam_scan_period = %d\n", conf->roam_scan_period[0]);
++	}
++	else if (!strncmp("roam_delta=", full_param, len_param)) {
++		conf->roam_delta[0] = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("roam_delta = %d\n", conf->roam_delta[0]);
++	}
++	else if (!strncmp("fullroamperiod=", full_param, len_param)) {
++		conf->fullroamperiod = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("fullroamperiod = %d\n", conf->fullroamperiod);
++	} else
++		return false;
++
++	return true;
++}
++
++bool
++dhd_conf_read_country(dhd_pub_t *dhd, char *full_param, uint len_param)
++{
++	struct dhd_conf *conf = dhd->conf;
++	country_list_t *country_next = NULL, *country;
++	int i, count = 0;
++	char *pch, *pick_tmp, *pick_tmp2;
++	char *data = full_param+len_param;
++	uint len_data = strlen(data);
++
++	/* Process country_list:
++	 * country_list=[country1]:[ccode1]/[regrev1],
++	 * [country2]:[ccode2]/[regrev2] \
++	 * Ex: country_list=US:US/0, TW:TW/1
++	 */
++	if (!strncmp("ccode=", full_param, len_param)) {
++		len_data = min((uint)WLC_CNTRY_BUF_SZ, len_data);
++		memset(&conf->cspec, 0, sizeof(wl_country_t));
++		memcpy(conf->cspec.country_abbrev, data, len_data);
++		memcpy(conf->cspec.ccode, data, len_data);
++		CONFIG_MSG("ccode = %s\n", conf->cspec.ccode);
++	}
++	else if (!strncmp("regrev=", full_param, len_param)) {
++		conf->cspec.rev = (int32)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("regrev = %d\n", conf->cspec.rev);
++	}
++	else if (!strncmp("country_list=", full_param, len_param)) {
++		dhd_conf_free_country_list(conf);
++		pick_tmp = data;
++		for (i=0; i<CONFIG_COUNTRY_LIST_SIZE; i++) {
++			pick_tmp2 = bcmstrtok(&pick_tmp, ", ", 0);
++			if (!pick_tmp2)
++				break;
++			pch = bcmstrtok(&pick_tmp2, ":", 0);
++			if (!pch)
++				break;
++			country = NULL;
++			if (!(country = kmalloc(sizeof(country_list_t), GFP_KERNEL))) {
++				CONFIG_ERROR("kmalloc failed\n");
++				break;
++			}
++			memset(country, 0, sizeof(country_list_t));
++
++			memcpy(country->cspec.country_abbrev, pch, 2);
++			pch = bcmstrtok(&pick_tmp2, "/", 0);
++			if (!pch) {
++				kfree(country);
++				break;
++			}
++			memcpy(country->cspec.ccode, pch, 2);
++			pch = bcmstrtok(&pick_tmp2, "/", 0);
++			if (!pch) {
++				kfree(country);
++				break;
++			}
++			country->cspec.rev = (int32)simple_strtol(pch, NULL, 10);
++			count++;
++			if (!conf->country_head) {
++				conf->country_head = country;
++				country_next = country;
++			} else {
++				country_next->next = country;
++				country_next = country;
++			}
++			CONFIG_TRACE("abbrev=%s, ccode=%s, regrev=%d\n",
++				country->cspec.country_abbrev, country->cspec.ccode, country->cspec.rev);
++		}
++		CONFIG_MSG("%d country in list\n", count);
++	}
++	else
++		return false;
++
++	return true;
++}
++
++bool
++dhd_conf_read_mchan_params(dhd_pub_t *dhd, char *full_param, uint len_param)
++{
++	int i;
++	char *pch, *pick_tmp, *pick_tmp2;
++	struct dhd_conf *conf = dhd->conf;
++	mchan_params_t *mchan_next = NULL, *mchan;
++	char *data = full_param+len_param;
++
++	/* Process mchan_bw:
++	 * mchan_bw=[val]/[any/go/gc]/[any/source/sink]
++	 * Ex: mchan_bw=80/go/source, 30/gc/sink
++	 */
++	if (!strncmp("mchan_bw=", full_param, len_param)) {
++		dhd_conf_free_mchan_list(conf);
++		pick_tmp = data;
++		for (i=0; i<MCHAN_MAX_NUM; i++) {
++			pick_tmp2 = bcmstrtok(&pick_tmp, ", ", 0);
++			if (!pick_tmp2)
++				break;
++			pch = bcmstrtok(&pick_tmp2, "/", 0);
++			if (!pch)
++				break;
++
++			mchan = NULL;
++			if (!(mchan = kmalloc(sizeof(mchan_params_t), GFP_KERNEL))) {
++				CONFIG_ERROR("kmalloc failed\n");
++				break;
++			}
++			memset(mchan, 0, sizeof(mchan_params_t));
++
++			mchan->bw = (int)simple_strtol(pch, NULL, 0);
++			if (mchan->bw < 0 || mchan->bw > 100) {
++				CONFIG_ERROR("wrong bw %d\n", mchan->bw);
++				kfree(mchan);
++				break;
++			}
++
++			pch = bcmstrtok(&pick_tmp2, "/", 0);
++			if (!pch) {
++				kfree(mchan);
++				break;
++			} else {
++				if (bcmstrstr(pch, "any")) {
++					mchan->p2p_mode = -1;
++				} else if (bcmstrstr(pch, "go")) {
++					mchan->p2p_mode = WL_P2P_IF_GO;
++				} else if (bcmstrstr(pch, "gc")) {
++					mchan->p2p_mode = WL_P2P_IF_CLIENT;
++				}
++			}
++			pch = bcmstrtok(&pick_tmp2, "/", 0);
++			if (!pch) {
++				kfree(mchan);
++				break;
++			} else {
++				if (bcmstrstr(pch, "any")) {
++					mchan->miracast_mode = -1;
++				} else if (bcmstrstr(pch, "source")) {
++					mchan->miracast_mode = MIRACAST_SOURCE;
++				} else if (bcmstrstr(pch, "sink")) {
++					mchan->miracast_mode = MIRACAST_SINK;
++				}
++			}
++			if (!conf->mchan) {
++				conf->mchan = mchan;
++				mchan_next = mchan;
++			} else {
++				mchan_next->next = mchan;
++				mchan_next = mchan;
++			}
++			CONFIG_TRACE("mchan_bw=%d/%d/%d\n", mchan->bw,mchan->p2p_mode,
++				mchan->miracast_mode);
++		}
++	}
++	else
++		return false;
++
++	return true;
++}
++
++#ifdef PKT_FILTER_SUPPORT
++bool
++dhd_conf_read_pkt_filter(dhd_pub_t *dhd, char *full_param, uint len_param)
++{
++	struct dhd_conf *conf = dhd->conf;
++	char *data = full_param+len_param;
++	char *pch, *pick_tmp;
++	int i;
++
++	/* Process pkt filter:
++	 * 1) pkt_filter_add=99 0 0 0 0x000000000000 0x000000000000
++	 * 2) pkt_filter_delete=100, 102, 103, 104, 105
++	 * 3) magic_pkt_filter_add=141 0 1 12
++	 */
++	if (!strncmp("dhd_master_mode=", full_param, len_param)) {
++		if (!strncmp(data, "0", 1))
++			dhd_master_mode = FALSE;
++		else
++			dhd_master_mode = TRUE;
++		CONFIG_MSG("dhd_master_mode = %d\n", dhd_master_mode);
++	}
++	else if (!strncmp("pkt_filter_add=", full_param, len_param)) {
++		pick_tmp = data;
++		pch = bcmstrtok(&pick_tmp, ",.-", 0);
++		i=0;
++		while (pch != NULL && i<DHD_CONF_FILTER_MAX) {
++			strcpy(&conf->pkt_filter_add.filter[i][0], pch);
++			CONFIG_MSG("pkt_filter_add[%d][] = %s\n",
++				i, &conf->pkt_filter_add.filter[i][0]);
++			pch = bcmstrtok(&pick_tmp, ",.-", 0);
++			i++;
++		}
++		conf->pkt_filter_add.count = i;
++	}
++	else if (!strncmp("pkt_filter_delete=", full_param, len_param) ||
++			!strncmp("pkt_filter_del=", full_param, len_param)) {
++		pick_tmp = data;
++		pch = bcmstrtok(&pick_tmp, " ,.-", 0);
++		i=0;
++		while (pch != NULL && i<DHD_CONF_FILTER_MAX) {
++			conf->pkt_filter_del.id[i] = (uint32)simple_strtol(pch, NULL, 10);
++			pch = bcmstrtok(&pick_tmp, " ,.-", 0);
++			i++;
++		}
++		conf->pkt_filter_del.count = i;
++		CONFIG_MSG("pkt_filter_del id = ");
++		for (i=0; i<conf->pkt_filter_del.count; i++)
++			printf("%d ", conf->pkt_filter_del.id[i]);
++		printf("\n");
++	}
++	else if (!strncmp("magic_pkt_filter_add=", full_param, len_param)) {
++		if (conf->magic_pkt_filter_add) {
++			kfree(conf->magic_pkt_filter_add);
++			conf->magic_pkt_filter_add = NULL;
++		}
++		if (!(conf->magic_pkt_filter_add = kmalloc(MAGIC_PKT_FILTER_LEN, GFP_KERNEL))) {
++			CONFIG_ERROR("kmalloc failed\n");
++		} else {
++			memset(conf->magic_pkt_filter_add, 0, MAGIC_PKT_FILTER_LEN);
++			strcpy(conf->magic_pkt_filter_add, data);
++			CONFIG_MSG("magic_pkt_filter_add = %s\n", conf->magic_pkt_filter_add);
++		}
++	}
++	else
++		return false;
++
++	return true;
++}
++#endif
++
++#ifdef ISAM_PREINIT
++#if !defined(WL_EXT_IAPSTA)
++#error "WL_EXT_IAPSTA should be defined to enable ISAM_PREINIT"
++#endif /* !WL_EXT_IAPSTA */
++/*
++ * isam_init=mode [sta|ap|apsta|dualap] vifname [wlan1]
++ * isam_config=ifname [wlan0|wlan1] ssid [xxx] chan [x]
++		 hidden [y|n] maxassoc [x]
++		 amode [open|shared|wpapsk|wpa2psk|wpawpa2psk]
++		 emode [none|wep|tkip|aes|tkipaes]
++		 key [xxxxx]
++ * isam_enable=ifname [wlan0|wlan1]
++*/
++bool
++dhd_conf_read_isam(dhd_pub_t *dhd, char *full_param, uint len_param)
++{
++	struct dhd_conf *conf = dhd->conf;
++	char *data = full_param+len_param;
++
++	if (!strncmp("isam_init=", full_param, len_param)) {
++		sprintf(conf->isam_init, "isam_init %s", data);
++		CONFIG_MSG("isam_init=%s\n", conf->isam_init);
++	}
++	else if (!strncmp("isam_config=", full_param, len_param)) {
++		sprintf(conf->isam_config, "isam_config %s", data);
++		CONFIG_MSG("isam_config=%s\n", conf->isam_config);
++	}
++	else if (!strncmp("isam_enable=", full_param, len_param)) {
++		sprintf(conf->isam_enable, "isam_enable %s", data);
++		CONFIG_MSG("isam_enable=%s\n", conf->isam_enable);
++	}
++	else
++		return false;
++
++	return true;
++}
++#endif
++
++#ifdef IDHCP
++bool
++dhd_conf_read_dhcp_params(dhd_pub_t *dhd, char *full_param, uint len_param)
++{
++	struct dhd_conf *conf = dhd->conf;
++	char *data = full_param+len_param;
++	struct ipv4_addr ipa_set;
++
++	if (!strncmp("dhcpc_enable=", full_param, len_param)) {
++		conf->dhcpc_enable = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("dhcpc_enable = %d\n", conf->dhcpc_enable);
++	}
++	else if (!strncmp("dhcpd_enable=", full_param, len_param)) {
++		conf->dhcpd_enable = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("dhcpd_enable = %d\n", conf->dhcpd_enable);
++	}
++	else if (!strncmp("dhcpd_ip_addr=", full_param, len_param)) {
++		if (!bcm_atoipv4(data, &ipa_set)) {
++			CONFIG_ERROR("dhcpd_ip_addr adress setting failed.n");
++			return false;
++		}
++		memcpy(&conf->dhcpd_ip_addr, &ipa_set, sizeof(struct ipv4_addr));
++		CONFIG_MSG("dhcpd_ip_addr = %s\n", data);
++	}
++	else if (!strncmp("dhcpd_ip_mask=", full_param, len_param)) {
++		if (!bcm_atoipv4(data, &ipa_set)) {
++			CONFIG_ERROR("dhcpd_ip_mask adress setting failed\n");
++			return false;
++		}
++		memcpy(&conf->dhcpd_ip_mask, &ipa_set, sizeof(struct ipv4_addr));
++		CONFIG_MSG("dhcpd_ip_mask = %s\n", data);
++	}
++	else if (!strncmp("dhcpd_ip_start=", full_param, len_param)) {
++		if (!bcm_atoipv4(data, &ipa_set)) {
++			CONFIG_ERROR("dhcpd_ip_start adress setting failed\n");
++			return false;
++		}
++		memcpy(&conf->dhcpd_ip_start, &ipa_set, sizeof(struct ipv4_addr));
++		CONFIG_MSG("dhcpd_ip_start = %s\n", data);
++	}
++	else if (!strncmp("dhcpd_ip_end=", full_param, len_param)) {
++		if (!bcm_atoipv4(data, &ipa_set)) {
++			CONFIG_ERROR("dhcpd_ip_end adress setting failed\n");
++			return false;
++		}
++		memcpy(&conf->dhcpd_ip_end, &ipa_set, sizeof(struct ipv4_addr));
++		CONFIG_MSG("dhcpd_ip_end = %s\n", data);
++	}
++	else
++		return false;
++
++	return true;
++}
++#endif
++
++#ifdef BCMSDIO
++bool
++dhd_conf_read_sdio_params(dhd_pub_t *dhd, char *full_param, uint len_param)
++{
++	struct dhd_conf *conf = dhd->conf;
++	char *data = full_param+len_param;
++
++	if (!strncmp("dhd_doflow=", full_param, len_param)) {
++		if (!strncmp(data, "0", 1))
++			dhd_doflow = FALSE;
++		else
++			dhd_doflow = TRUE;
++		CONFIG_MSG("dhd_doflow = %d\n", dhd_doflow);
++	}
++	else if (!strncmp("dhd_slpauto=", full_param, len_param) ||
++			!strncmp("kso_enable=", full_param, len_param)) {
++		if (!strncmp(data, "0", 1))
++			dhd_slpauto = FALSE;
++		else
++			dhd_slpauto = TRUE;
++		CONFIG_MSG("dhd_slpauto = %d\n", dhd_slpauto);
++	}
++	else if (!strncmp("use_rxchain=", full_param, len_param)) {
++		conf->use_rxchain = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("use_rxchain = %d\n", conf->use_rxchain);
++	}
++	else if (!strncmp("dhd_txminmax=", full_param, len_param)) {
++		conf->dhd_txminmax = (uint)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("dhd_txminmax = %d\n", conf->dhd_txminmax);
++	}
++	else if (!strncmp("txinrx_thres=", full_param, len_param)) {
++		conf->txinrx_thres = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("txinrx_thres = %d\n", conf->txinrx_thres);
++	}
++#if defined(HW_OOB)
++	else if (!strncmp("oob_enabled_later=", full_param, len_param)) {
++		if (!strncmp(data, "0", 1))
++			conf->oob_enabled_later = FALSE;
++		else
++			conf->oob_enabled_later = TRUE;
++		CONFIG_MSG("oob_enabled_later = %d\n", conf->oob_enabled_later);
++	}
++#endif
++	else if (!strncmp("dpc_cpucore=", full_param, len_param)) {
++		conf->dpc_cpucore = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("dpc_cpucore = %d\n", conf->dpc_cpucore);
++	}
++	else if (!strncmp("rxf_cpucore=", full_param, len_param)) {
++		conf->rxf_cpucore = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("rxf_cpucore = %d\n", conf->rxf_cpucore);
++	}
++#if defined(BCMSDIOH_TXGLOM)
++	else if (!strncmp("txglomsize=", full_param, len_param)) {
++		conf->txglomsize = (uint)simple_strtol(data, NULL, 10);
++		if (conf->txglomsize > SDPCM_MAXGLOM_SIZE)
++			conf->txglomsize = SDPCM_MAXGLOM_SIZE;
++		CONFIG_MSG("txglomsize = %d\n", conf->txglomsize);
++	}
++	else if (!strncmp("txglom_ext=", full_param, len_param)) {
++		if (!strncmp(data, "0", 1))
++			conf->txglom_ext = FALSE;
++		else
++			conf->txglom_ext = TRUE;
++		CONFIG_MSG("txglom_ext = %d\n", conf->txglom_ext);
++		if (conf->txglom_ext) {
++			if ((conf->chip == BCM43362_CHIP_ID) || (conf->chip == BCM4330_CHIP_ID))
++				conf->txglom_bucket_size = 1680;
++			else if (conf->chip == BCM43340_CHIP_ID || conf->chip == BCM43341_CHIP_ID ||
++					conf->chip == BCM4334_CHIP_ID || conf->chip == BCM4324_CHIP_ID)
++				conf->txglom_bucket_size = 1684;
++		}
++		CONFIG_MSG("txglom_bucket_size = %d\n", conf->txglom_bucket_size);
++	}
++	else if (!strncmp("bus:rxglom=", full_param, len_param)) {
++		if (!strncmp(data, "0", 1))
++			conf->bus_rxglom = FALSE;
++		else
++			conf->bus_rxglom = TRUE;
++		CONFIG_MSG("bus:rxglom = %d\n", conf->bus_rxglom);
++	}
++	else if (!strncmp("deferred_tx_len=", full_param, len_param)) {
++		conf->deferred_tx_len = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("deferred_tx_len = %d\n", conf->deferred_tx_len);
++	}
++	else if (!strncmp("txctl_tmo_fix=", full_param, len_param)) {
++		conf->txctl_tmo_fix = (int)simple_strtol(data, NULL, 0);
++		CONFIG_MSG("txctl_tmo_fix = %d\n", conf->txctl_tmo_fix);
++	}
++	else if (!strncmp("tx_max_offset=", full_param, len_param)) {
++		conf->tx_max_offset = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("tx_max_offset = %d\n", conf->tx_max_offset);
++	}
++	else if (!strncmp("txglom_mode=", full_param, len_param)) {
++		if (!strncmp(data, "0", 1))
++			conf->txglom_mode = FALSE;
++		else
++			conf->txglom_mode = TRUE;
++		CONFIG_MSG("txglom_mode = %d\n", conf->txglom_mode);
++	}
++#if defined(SDIO_ISR_THREAD)
++	else if (!strncmp("intr_extn=", full_param, len_param)) {
++		if (!strncmp(data, "0", 1))
++			conf->intr_extn = FALSE;
++		else
++			conf->intr_extn = TRUE;
++		CONFIG_MSG("intr_extn = %d\n", conf->intr_extn);
++	}
++#endif
++#ifdef BCMSDIO_RXLIM_POST
++	else if (!strncmp("rxlim_en=", full_param, len_param)) {
++		if (!strncmp(data, "0", 1))
++			conf->rxlim_en = FALSE;
++		else
++			conf->rxlim_en = TRUE;
++		CONFIG_MSG("rxlim_en = %d\n", conf->rxlim_en);
++	}
++#endif
++#endif
++	else
++		return false;
++
++	return true;
++}
++#endif
++
++#ifdef BCMPCIE
++bool
++dhd_conf_read_pcie_params(dhd_pub_t *dhd, char *full_param, uint len_param)
++{
++	struct dhd_conf *conf = dhd->conf;
++	char *data = full_param+len_param;
++
++	if (!strncmp("bus:deepsleep_disable=", full_param, len_param)) {
++		if (!strncmp(data, "0", 1))
++			conf->bus_deepsleep_disable = 0;
++		else
++			conf->bus_deepsleep_disable = 1;
++		CONFIG_MSG("bus:deepsleep_disable = %d\n", conf->bus_deepsleep_disable);
++	}
++	else
++		return false;
++
++	return true;
++}
++#endif
++
++bool
++dhd_conf_read_pm_params(dhd_pub_t *dhd, char *full_param, uint len_param)
++{
++	struct dhd_conf *conf = dhd->conf;
++	char *data = full_param+len_param;
++
++	if (!strncmp("deepsleep=", full_param, len_param)) {
++		if (!strncmp(data, "1", 1))
++			conf->deepsleep = TRUE;
++		else
++			conf->deepsleep = FALSE;
++		CONFIG_MSG("deepsleep = %d\n", conf->deepsleep);
++	}
++	else if (!strncmp("PM=", full_param, len_param)) {
++		conf->pm = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("PM = %d\n", conf->pm);
++	}
++	else if (!strncmp("pm_in_suspend=", full_param, len_param)) {
++		conf->pm_in_suspend = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("pm_in_suspend = %d\n", conf->pm_in_suspend);
++	}
++	else if (!strncmp("suspend_mode=", full_param, len_param)) {
++		conf->suspend_mode = (int)simple_strtol(data, NULL, 0);
++		CONFIG_MSG("suspend_mode = %d\n", conf->suspend_mode);
++		if (conf->suspend_mode == PM_NOTIFIER)
++			conf->insuspend |= (NO_TXDATA_IN_SUSPEND | NO_TXCTL_IN_SUSPEND);
++	}
++	else if (!strncmp("suspend_bcn_li_dtim=", full_param, len_param)) {
++		conf->suspend_bcn_li_dtim = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("suspend_bcn_li_dtim = %d\n", conf->suspend_bcn_li_dtim);
++	}
++	else if (!strncmp("xmit_in_suspend=", full_param, len_param)) {
++		if (!strncmp(data, "1", 1))
++			conf->insuspend &= ~NO_TXDATA_IN_SUSPEND;
++		else
++			conf->insuspend |= NO_TXDATA_IN_SUSPEND;
++		CONFIG_MSG("insuspend = 0x%x\n", conf->insuspend);
++	}
++	else if (!strncmp("insuspend=", full_param, len_param)) {
++		conf->insuspend = (int)simple_strtol(data, NULL, 0);
++		CONFIG_MSG("insuspend = 0x%x\n", conf->insuspend);
++	}
++#ifdef WL_EXT_WOWL
++	else if (!strncmp("wowl=", full_param, len_param)) {
++		conf->wowl = (int)simple_strtol(data, NULL, 0);
++		CONFIG_MSG("wowl = 0x%x\n", conf->wowl);
++	}
++#endif
++	else
++		return false;
++
++	return true;
++}
++
++#ifdef GET_CUSTOM_MAC_FROM_CONFIG
++int
++bcm_str2hex(const char *p, char *ea, int size)
++{
++	int i = 0;
++	char *ep;
++
++	for (;;) {
++		ea[i++] = (char) bcm_strtoul(p, &ep, 16);
++		p = ep;
++		if (!*p++ || i == size)
++			break;
++	}
++
++	return (i == size);
++}
++#endif
++
++bool
++dhd_conf_read_others(dhd_pub_t *dhd, char *full_param, uint len_param)
++{
++	struct dhd_conf *conf = dhd->conf;
++	char *data = full_param+len_param;
++	char *pch, *pick_tmp;
++	int i;
++#ifdef GET_CUSTOM_MAC_FROM_CONFIG
++	struct ether_addr ea_addr;
++	char macpad[56];
++#endif
++
++	if (!strncmp("dhd_poll=", full_param, len_param)) {
++		if (!strncmp(data, "0", 1))
++			conf->dhd_poll = 0;
++		else
++			conf->dhd_poll = 1;
++		CONFIG_MSG("dhd_poll = %d\n", conf->dhd_poll);
++	}
++	else if (!strncmp("dhd_watchdog_ms=", full_param, len_param)) {
++		dhd_watchdog_ms = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("dhd_watchdog_ms = %d\n", dhd_watchdog_ms);
++	}
++	else if (!strncmp("band=", full_param, len_param)) {
++		/* Process band:
++		 * band=a for 5GHz only and band=b for 2.4GHz only
++		 */
++		if (!strcmp(data, "b"))
++			conf->band = WLC_BAND_2G;
++		else if (!strcmp(data, "a"))
++			conf->band = WLC_BAND_5G;
++		else
++			conf->band = WLC_BAND_AUTO;
++		CONFIG_MSG("band = %d\n", conf->band);
++	}
++	else if (!strncmp("bw_cap_2g=", full_param, len_param)) {
++		conf->bw_cap[0] = (uint)simple_strtol(data, NULL, 0);
++		CONFIG_MSG("bw_cap_2g = %d\n", conf->bw_cap[0]);
++	}
++	else if (!strncmp("bw_cap_5g=", full_param, len_param)) {
++		conf->bw_cap[1] = (uint)simple_strtol(data, NULL, 0);
++		CONFIG_MSG("bw_cap_5g = %d\n", conf->bw_cap[1]);
++	}
++	else if (!strncmp("bw_cap=", full_param, len_param)) {
++		pick_tmp = data;
++		pch = bcmstrtok(&pick_tmp, " ,.-", 0);
++		if (pch != NULL) {
++			conf->bw_cap[0] = (uint32)simple_strtol(pch, NULL, 0);
++			CONFIG_MSG("bw_cap 2g = %d\n", conf->bw_cap[0]);
++		}
++		pch = bcmstrtok(&pick_tmp, " ,.-", 0);
++		if (pch != NULL) {
++			conf->bw_cap[1] = (uint32)simple_strtol(pch, NULL, 0);
++			CONFIG_MSG("bw_cap 5g = %d\n", conf->bw_cap[1]);
++		}
++	}
++	else if (!strncmp("channels=", full_param, len_param)) {
++		pick_tmp = data;
++		pch = bcmstrtok(&pick_tmp, " ,.-", 0);
++		i=0;
++		while (pch != NULL && i<WL_NUMCHANNELS) {
++			conf->channels.channel[i] = (uint32)simple_strtol(pch, NULL, 10);
++			pch = bcmstrtok(&pick_tmp, " ,.-", 0);
++			i++;
++		}
++		conf->channels.count = i;
++		CONFIG_MSG("channels = ");
++		for (i=0; i<conf->channels.count; i++)
++			printf("%d ", conf->channels.channel[i]);
++		printf("\n");
++	}
++	else if (!strncmp("keep_alive_period=", full_param, len_param)) {
++		conf->keep_alive_period = (uint)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("keep_alive_period = %d\n", conf->keep_alive_period);
++	}
++#ifdef ARP_OFFLOAD_SUPPORT
++	else if (!strncmp("garp=", full_param, len_param)) {
++		if (!strncmp(data, "0", 1))
++			conf->garp = FALSE;
++		else
++			conf->garp = TRUE;
++		CONFIG_MSG("garp = %d\n", conf->garp);
++	}
++#endif
++	else if (!strncmp("srl=", full_param, len_param)) {
++		conf->srl = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("srl = %d\n", conf->srl);
++	}
++	else if (!strncmp("lrl=", full_param, len_param)) {
++		conf->lrl = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("lrl = %d\n", conf->lrl);
++	}
++	else if (!strncmp("bcn_timeout=", full_param, len_param)) {
++		conf->bcn_timeout= (uint)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("bcn_timeout = %d\n", conf->bcn_timeout);
++	}
++	else if (!strncmp("frameburst=", full_param, len_param)) {
++		conf->frameburst = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("frameburst = %d\n", conf->frameburst);
++	}
++	else if (!strncmp("disable_proptx=", full_param, len_param)) {
++		conf->disable_proptx = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("disable_proptx = %d\n", conf->disable_proptx);
++	}
++#ifdef DHDTCPACK_SUPPRESS
++	else if (!strncmp("tcpack_sup_mode=", full_param, len_param)) {
++		conf->tcpack_sup_mode = (uint)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("tcpack_sup_mode = %d\n", conf->tcpack_sup_mode);
++	}
++#endif
++	else if (!strncmp("pktprio8021x=", full_param, len_param)) {
++		conf->pktprio8021x = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("pktprio8021x = %d\n", conf->pktprio8021x);
++	}
++#if defined(BCMSDIO) || defined(BCMPCIE)
++	else if (!strncmp("dhd_txbound=", full_param, len_param)) {
++		dhd_txbound = (uint)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("dhd_txbound = %d\n", dhd_txbound);
++	}
++	else if (!strncmp("dhd_rxbound=", full_param, len_param)) {
++		dhd_rxbound = (uint)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("dhd_rxbound = %d\n", dhd_rxbound);
++	}
++#endif
++	else if (!strncmp("orphan_move=", full_param, len_param)) {
++		conf->orphan_move = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("orphan_move = %d\n", conf->orphan_move);
++	}
++	else if (!strncmp("tsq=", full_param, len_param)) {
++		conf->tsq = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("tsq = %d\n", conf->tsq);
++	}
++	else if (!strncmp("ctrl_resched=", full_param, len_param)) {
++		conf->ctrl_resched = (int)simple_strtol(data, NULL, 10);
++		CONFIG_MSG("ctrl_resched = %d\n", conf->ctrl_resched);
++	}
++	else if (!strncmp("in4way=", full_param, len_param)) {
++		conf->in4way = (int)simple_strtol(data, NULL, 0);
++		CONFIG_MSG("in4way = 0x%x\n", conf->in4way);
++	}
++	else if (!strncmp("wl_preinit=", full_param, len_param)) {
++		if (conf->wl_preinit) {
++			kfree(conf->wl_preinit);
++			conf->wl_preinit = NULL;
++		}
++		if (!(conf->wl_preinit = kmalloc(len_param+1, GFP_KERNEL))) {
++			CONFIG_ERROR("kmalloc failed\n");
++		} else {
++			memset(conf->wl_preinit, 0, len_param+1);
++			strcpy(conf->wl_preinit, data);
++			CONFIG_MSG("wl_preinit = %s\n", conf->wl_preinit);
++		}
++	}
++	else if (!strncmp("wl_suspend=", full_param, len_param)) {
++		if (conf->wl_suspend) {
++			kfree(conf->wl_suspend);
++			conf->wl_suspend = NULL;
++		}
++		if (!(conf->wl_suspend = kmalloc(len_param+1, GFP_KERNEL))) {
++			CONFIG_ERROR("kmalloc failed\n");
++		} else {
++			memset(conf->wl_suspend, 0, len_param+1);
++			strcpy(conf->wl_suspend, data);
++			CONFIG_MSG("wl_suspend = %s\n", conf->wl_suspend);
++		}
++	}
++	else if (!strncmp("wl_resume=", full_param, len_param)) {
++		if (conf->wl_resume) {
++			kfree(conf->wl_resume);
++			conf->wl_resume = NULL;
++		}
++		if (!(conf->wl_resume = kmalloc(len_param+1, GFP_KERNEL))) {
++			CONFIG_ERROR("kmalloc failed\n");
++		} else {
++			memset(conf->wl_resume, 0, len_param+1);
++			strcpy(conf->wl_resume, data);
++			CONFIG_MSG("wl_resume = %s\n", conf->wl_resume);
++		}
++	}
++#ifdef GET_CUSTOM_MAC_FROM_CONFIG
++	else if (!strncmp("mac=", full_param, len_param)) {
++		if (!bcm_ether_atoe(data, &ea_addr)) {
++			CONFIG_ERROR("mac adress read error");
++			return false;
++		}
++		memcpy(&conf->hw_ether, &ea_addr, ETHER_ADDR_LEN);
++		CONFIG_MSG("mac = %s\n", data);
++	}
++	else if (!strncmp("macpad=", full_param, len_param)) {
++		if (!bcm_str2hex(data, macpad, sizeof(macpad))) {
++			CONFIG_ERROR("macpad adress read error");
++			return false;
++		}
++		memcpy(&conf->hw_ether[ETHER_ADDR_LEN], macpad, sizeof(macpad));
++		if (config_msg_level & CONFIG_TRACE_LEVEL) {
++			printf("macpad =\n");
++			for (i=0; i<sizeof(macpad); i++) {
++				printf("0x%02x, ", conf->hw_ether[ETHER_ADDR_LEN+i]);
++				if ((i+1)%8 == 0)
++					printf("\n");
++			}
++		}
++	}
++#endif
++	else
++		return false;
++
++	return true;
++}
++
++int
++dhd_conf_read_config(dhd_pub_t *dhd, char *conf_path)
++{
++	int bcmerror = -1, chip_match = -1;
++	uint len = 0, start_pos=0, end_pos=0;
++	void *image = NULL;
++	char *memblock = NULL;
++	char *bufp, *pick = NULL, *pch;
++	bool conf_file_exists;
++	uint len_param;
++
++	conf_file_exists = ((conf_path != NULL) && (conf_path[0] != '\0'));
++	if (!conf_file_exists) {
++		CONFIG_MSG("config path %s\n", conf_path);
++		return (0);
++	}
++
++	if (conf_file_exists) {
++		image = dhd_os_open_image(conf_path);
++		if (image == NULL) {
++			CONFIG_MSG("Ignore config file %s\n", conf_path);
++			goto err;
++		}
++	}
++
++	memblock = MALLOC(dhd->osh, MAXSZ_CONFIG);
++	if (memblock == NULL) {
++		CONFIG_ERROR("Failed to allocate memory %d bytes\n", MAXSZ_CONFIG);
++		goto err;
++	}
++
++	pick = MALLOC(dhd->osh, MAXSZ_BUF);
++	if (!pick) {
++		CONFIG_ERROR("Failed to allocate memory %d bytes\n", MAXSZ_BUF);
++		goto err;
++	}
++
++	/* Read variables */
++	if (conf_file_exists) {
++		len = dhd_os_get_image_block(memblock, MAXSZ_CONFIG, image);
++	}
++	if (len > 0 && len < MAXSZ_CONFIG) {
++		bufp = (char *)memblock;
++		bufp[len] = 0;
++
++		while (start_pos < len) {
++			memset(pick, 0, MAXSZ_BUF);
++			end_pos = pick_config_vars(bufp, len, start_pos, pick, MAXSZ_BUF);
++			if (end_pos - start_pos >= MAXSZ_BUF)
++				CONFIG_ERROR("out of buf to read MAXSIZ_BUF=%d\n", MAXSZ_BUF);
++			start_pos = end_pos;
++			pch = strchr(pick, '=');
++			if (pch != NULL) {
++				len_param = pch-pick+1;
++				if (len_param == strlen(pick)) {
++					CONFIG_ERROR("not a right parameter %s\n", pick);
++					continue;
++				}
++			} else {
++				CONFIG_ERROR("not a right parameter %s\n", pick);
++				continue;
++			}
++
++			dhd_conf_read_chiprev(dhd, &chip_match, pick, len_param);
++			if (!chip_match)
++				continue;
++
++			if (dhd_conf_read_log_level(dhd, pick, len_param))
++				continue;
++			else if (dhd_conf_read_roam_params(dhd, pick, len_param))
++				continue;
++			else if (dhd_conf_read_wme_ac_params(dhd, pick, len_param))
++				continue;
++#ifdef BCMSDIO
++			else if (dhd_conf_read_fw_by_mac(dhd, pick, len_param))
++				continue;
++			else if (dhd_conf_read_nv_by_mac(dhd, pick, len_param))
++				continue;
++#endif
++			else if (dhd_conf_read_nv_by_chip(dhd, pick, len_param))
++				continue;
++			else if (dhd_conf_read_country(dhd, pick, len_param))
++				continue;
++			else if (dhd_conf_read_mchan_params(dhd, pick, len_param))
++				continue;
++#ifdef PKT_FILTER_SUPPORT
++			else if (dhd_conf_read_pkt_filter(dhd, pick, len_param))
++				continue;
++#endif /* PKT_FILTER_SUPPORT */
++#ifdef ISAM_PREINIT
++			else if (dhd_conf_read_isam(dhd, pick, len_param))
++				continue;
++#endif /* ISAM_PREINIT */
++#ifdef IDHCP
++			else if (dhd_conf_read_dhcp_params(dhd, pick, len_param))
++				continue;
++#endif /* IDHCP */
++#ifdef BCMSDIO
++			else if (dhd_conf_read_sdio_params(dhd, pick, len_param))
++				continue;
++#endif /* BCMSDIO */
++#ifdef BCMPCIE
++			else if (dhd_conf_read_pcie_params(dhd, pick, len_param))
++				continue;
++#endif /* BCMPCIE */
++			else if (dhd_conf_read_pm_params(dhd, pick, len_param))
++				continue;
++			else if (dhd_conf_read_others(dhd, pick, len_param))
++				continue;
++			else
++				continue;
++		}
++
++		bcmerror = 0;
++	} else {
++		CONFIG_ERROR("error reading config file: %d\n", len);
++		bcmerror = BCME_SDIO_ERROR;
++	}
++
++err:
++	if (pick)
++		MFREE(dhd->osh, pick, MAXSZ_BUF);
++
++	if (memblock)
++		MFREE(dhd->osh, memblock, MAXSZ_CONFIG);
++
++	if (image)
++		dhd_os_close_image(image);
++
++	return bcmerror;
++}
++
++int
++dhd_conf_set_chiprev(dhd_pub_t *dhd, uint chip, uint chiprev)
++{
++	CONFIG_MSG("chip=0x%x, chiprev=%d\n", chip, chiprev);
++	dhd->conf->chip = chip;
++	dhd->conf->chiprev = chiprev;
++	return 0;
++}
++
++uint
++dhd_conf_get_chip(void *context)
++{
++	dhd_pub_t *dhd = context;
++
++	if (dhd && dhd->conf)
++		return dhd->conf->chip;
++	return 0;
++}
++
++uint
++dhd_conf_get_chiprev(void *context)
++{
++	dhd_pub_t *dhd = context;
++
++	if (dhd && dhd->conf)
++		return dhd->conf->chiprev;
++	return 0;
++}
++
++#ifdef BCMSDIO
++void
++dhd_conf_set_txglom_params(dhd_pub_t *dhd, bool enable)
++{
++	struct dhd_conf *conf = dhd->conf;
++
++	if (enable) {
++#if defined(BCMSDIOH_TXGLOM_EXT)
++		if (conf->chip == BCM43362_CHIP_ID || conf->chip == BCM4330_CHIP_ID ||
++				conf->chip == BCM43340_CHIP_ID || conf->chip == BCM43341_CHIP_ID ||
++				conf->chip == BCM4334_CHIP_ID || conf->chip == BCM4324_CHIP_ID) {
++			conf->txglom_mode = SDPCM_TXGLOM_CPY;
++		}
++#endif
++		// other parameters set in preinit or config.txt
++		if (conf->txglom_ext)
++			CONFIG_MSG("txglom_ext=%d, txglom_bucket_size=%d\n",
++				conf->txglom_ext, conf->txglom_bucket_size);
++		CONFIG_MSG("txglom_mode=%s\n",
++	 		conf->txglom_mode==SDPCM_TXGLOM_MDESC?"multi-desc":"copy");
++		CONFIG_MSG("txglomsize=%d, deferred_tx_len=%d\n",
++			conf->txglomsize, conf->deferred_tx_len);
++		CONFIG_MSG("txinrx_thres=%d, dhd_txminmax=%d\n",
++			conf->txinrx_thres, conf->dhd_txminmax);
++		CONFIG_MSG("tx_max_offset=%d, txctl_tmo_fix=%d\n",
++			conf->tx_max_offset, conf->txctl_tmo_fix);
++	} else {
++		// clear txglom parameters
++		conf->txglom_ext = FALSE;
++		conf->txglom_bucket_size = 0;
++		conf->txglomsize = 0;
++		conf->deferred_tx_len = 0;
++	}
++
++}
++#endif
++
++void
++dhd_conf_postinit_ioctls(dhd_pub_t *dhd)
++{
++	struct dhd_conf *conf = dhd->conf;
++	char wl_preinit[] = "assoc_retry_max=20";
++
++	dhd_conf_set_intiovar(dhd, WLC_UP, "WLC_UP", 0, 0, FALSE);
++	dhd_conf_map_country_list(dhd, &conf->cspec);
++	dhd_conf_set_country(dhd, &conf->cspec);
++	dhd_conf_fix_country(dhd);
++	dhd_conf_get_country(dhd, &dhd->dhd_cspec);
++
++	dhd_conf_set_intiovar(dhd, WLC_SET_BAND, "WLC_SET_BAND", conf->band, 0, FALSE);
++	dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "bcn_timeout", conf->bcn_timeout, 0, FALSE);
++	dhd_conf_set_intiovar(dhd, WLC_SET_PM, "WLC_SET_PM", conf->pm, 0, FALSE);
++	dhd_conf_set_intiovar(dhd, WLC_SET_SRL, "WLC_SET_SRL", conf->srl, 0, FALSE);
++	dhd_conf_set_intiovar(dhd, WLC_SET_LRL, "WLC_SET_LRL", conf->lrl, 0, FALSE);
++	dhd_conf_set_bw_cap(dhd);
++	dhd_conf_set_roam(dhd);
++
++#if defined(BCMPCIE)
++	dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "bus:deepsleep_disable",
++		conf->bus_deepsleep_disable, 0, FALSE);
++#endif /* defined(BCMPCIE) */
++
++#ifdef IDHCP
++	dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "dhcpc_enable", conf->dhcpc_enable,
++		0, FALSE);
++	if (conf->dhcpd_enable >= 0) {
++		dhd_conf_set_bufiovar(dhd, 0, WLC_SET_VAR, "dhcpd_ip_addr",
++			(char *)&conf->dhcpd_ip_addr, sizeof(conf->dhcpd_ip_addr), FALSE);
++		dhd_conf_set_bufiovar(dhd, 0, WLC_SET_VAR, "dhcpd_ip_mask",
++			(char *)&conf->dhcpd_ip_mask, sizeof(conf->dhcpd_ip_mask), FALSE);
++		dhd_conf_set_bufiovar(dhd, 0, WLC_SET_VAR, "dhcpd_ip_start",
++			(char *)&conf->dhcpd_ip_start, sizeof(conf->dhcpd_ip_start), FALSE);
++		dhd_conf_set_bufiovar(dhd, 0, WLC_SET_VAR, "dhcpd_ip_end",
++			(char *)&conf->dhcpd_ip_end, sizeof(conf->dhcpd_ip_end), FALSE);
++		dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "dhcpd_enable",
++			conf->dhcpd_enable, 0, FALSE);
++	}
++#endif
++	dhd_conf_set_intiovar(dhd, WLC_SET_FAKEFRAG, "WLC_SET_FAKEFRAG",
++		conf->frameburst, 0, FALSE);
++
++	dhd_conf_set_wl_cmd(dhd, wl_preinit, TRUE);
++#if defined(BCMSDIO)
++	{
++		char ampdu_mpdu[] = "ampdu_mpdu=16";
++		dhd_conf_set_wl_cmd(dhd, ampdu_mpdu, TRUE);
++	}
++#endif
++	if (conf->chip == BCM4354_CHIP_ID || conf->chip == BCM4356_CHIP_ID ||
++			conf->chip == BCM4371_CHIP_ID || conf->chip == BCM4359_CHIP_ID ||
++			conf->chip == BCM43569_CHIP_ID) {
++		dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "txbf", 1, 0, FALSE);
++	}
++	dhd_conf_set_wl_cmd(dhd, conf->wl_preinit, TRUE);
++
++#ifndef WL_CFG80211
++	dhd_conf_set_intiovar(dhd, WLC_UP, "WLC_UP", 0, 0, FALSE);
++#endif
++
++}
++
++int
++dhd_conf_preinit(dhd_pub_t *dhd)
++{
++	struct dhd_conf *conf = dhd->conf;
++
++	CONFIG_TRACE("Enter\n");
++
++#ifdef BCMSDIO
++	dhd_conf_free_mac_list(&conf->fw_by_mac);
++	dhd_conf_free_mac_list(&conf->nv_by_mac);
++#endif
++	dhd_conf_free_chip_nv_path_list(&conf->nv_by_chip);
++	dhd_conf_free_country_list(conf);
++	dhd_conf_free_mchan_list(conf);
++	if (conf->magic_pkt_filter_add) {
++		kfree(conf->magic_pkt_filter_add);
++		conf->magic_pkt_filter_add = NULL;
++	}
++	if (conf->wl_preinit) {
++		kfree(conf->wl_preinit);
++		conf->wl_preinit = NULL;
++	}
++	if (conf->wl_suspend) {
++		kfree(conf->wl_suspend);
++		conf->wl_suspend = NULL;
++	}
++	if (conf->wl_resume) {
++		kfree(conf->wl_resume);
++		conf->wl_resume = NULL;
++	}
++	conf->band = -1;
++	memset(&conf->bw_cap, -1, sizeof(conf->bw_cap));
++	if (conf->chip == BCM43362_CHIP_ID || conf->chip == BCM4330_CHIP_ID) {
++		strcpy(conf->cspec.country_abbrev, "ALL");
++		strcpy(conf->cspec.ccode, "ALL");
++		conf->cspec.rev = 0;
++	} else if (conf->chip == BCM4335_CHIP_ID || conf->chip == BCM4339_CHIP_ID ||
++			conf->chip == BCM4354_CHIP_ID || conf->chip == BCM4356_CHIP_ID ||
++			conf->chip == BCM4345_CHIP_ID || conf->chip == BCM4371_CHIP_ID ||
++			conf->chip == BCM43569_CHIP_ID || conf->chip == BCM4359_CHIP_ID) {
++		strcpy(conf->cspec.country_abbrev, "CN");
++		strcpy(conf->cspec.ccode, "CN");
++		conf->cspec.rev = 38;
++	} else {
++		strcpy(conf->cspec.country_abbrev, "CN");
++		strcpy(conf->cspec.ccode, "CN");
++		conf->cspec.rev = 0;
++	}
++	memset(&conf->channels, 0, sizeof(wl_channel_list_t));
++	conf->roam_off = 1;
++	conf->roam_off_suspend = 1;
++	conf->roam_trigger[0] = -65;
++	conf->roam_trigger[1] = WLC_BAND_ALL;
++	conf->roam_scan_period[0] = 10;
++	conf->roam_scan_period[1] = WLC_BAND_ALL;
++	conf->roam_delta[0] = 10;
++	conf->roam_delta[1] = WLC_BAND_ALL;
++	conf->fullroamperiod = 20;
++	conf->keep_alive_period = 30000;
++#ifdef ARP_OFFLOAD_SUPPORT
++	conf->garp = FALSE;
++#endif
++	conf->force_wme_ac = 0;
++	memset(&conf->wme_sta, 0, sizeof(wme_param_t));
++	memset(&conf->wme_ap, 0, sizeof(wme_param_t));
++#ifdef PKT_FILTER_SUPPORT
++	memset(&conf->pkt_filter_add, 0, sizeof(conf_pkt_filter_add_t));
++	memset(&conf->pkt_filter_del, 0, sizeof(conf_pkt_filter_del_t));
++#endif
++	conf->srl = -1;
++	conf->lrl = -1;
++	conf->bcn_timeout = 16;
++	conf->disable_proptx = -1;
++	conf->dhd_poll = -1;
++#ifdef BCMSDIO
++	conf->use_rxchain = 0;
++	conf->bus_rxglom = TRUE;
++	conf->txglom_ext = FALSE;
++	conf->tx_max_offset = 0;
++	conf->txglomsize = SDPCM_DEFGLOM_SIZE;
++	conf->txctl_tmo_fix = 300;
++	conf->txglom_mode = SDPCM_TXGLOM_MDESC;
++	conf->deferred_tx_len = 0;
++	conf->dhd_txminmax = 1;
++	conf->txinrx_thres = -1;
++#if defined(SDIO_ISR_THREAD)
++	conf->intr_extn = FALSE;
++#endif
++#ifdef BCMSDIO_RXLIM_POST
++	conf->rxlim_en = TRUE;
++#endif
++#if defined(HW_OOB)
++	conf->oob_enabled_later = FALSE;
++#endif
++#endif
++#ifdef BCMPCIE
++	conf->bus_deepsleep_disable = 1;
++#endif
++	conf->dpc_cpucore = -1;
++	conf->rxf_cpucore = -1;
++	conf->frameburst = -1;
++	conf->deepsleep = FALSE;
++	conf->pm = -1;
++	conf->pm_in_suspend = -1;
++	conf->insuspend = 0;
++	conf->suspend_mode = EARLY_SUSPEND;
++	conf->suspend_bcn_li_dtim = -1;
++#ifdef WL_EXT_WOWL
++	dhd_master_mode = TRUE;
++	conf->wowl = WL_WOWL_NET|WL_WOWL_DIS|WL_WOWL_BCN;
++	conf->insuspend |= (WOWL_IN_SUSPEND | NO_TXDATA_IN_SUSPEND);
++#endif
++	if (conf->suspend_mode == PM_NOTIFIER)
++		conf->insuspend |= (NO_TXDATA_IN_SUSPEND | NO_TXCTL_IN_SUSPEND);
++	conf->suspended = FALSE;
++#ifdef SUSPEND_EVENT
++	memset(&conf->resume_eventmask, 0, sizeof(conf->resume_eventmask));
++	memset(&conf->bssid_insuspend, 0, ETHER_ADDR_LEN);
++	conf->wlfc = FALSE;
++#endif
++#ifdef GET_CUSTOM_MAC_FROM_CONFIG
++	memset(&conf->hw_ether, 0, sizeof(conf->hw_ether));
++#endif
++#ifdef IDHCP
++	conf->dhcpc_enable = -1;
++	conf->dhcpd_enable = -1;
++#endif
++	conf->orphan_move = 0;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
++	conf->tsq = 10;
++#else
++	conf->tsq = 0;
++#endif
++#ifdef DHDTCPACK_SUPPRESS
++#ifdef BCMPCIE
++	conf->tcpack_sup_mode = TCPACK_SUP_DEFAULT;
++#else
++	conf->tcpack_sup_mode = TCPACK_SUP_OFF;
++#endif
++#endif
++	conf->pktprio8021x = -1;
++	conf->ctrl_resched = 2;
++	conf->in4way = NO_SCAN_IN4WAY | DONT_DELETE_GC_AFTER_WPS | WAIT_DISCONNECTED;
++#ifdef ISAM_PREINIT
++	memset(conf->isam_init, 0, sizeof(conf->isam_init));
++	memset(conf->isam_config, 0, sizeof(conf->isam_config));
++	memset(conf->isam_enable, 0, sizeof(conf->isam_enable));
++#endif
++#if defined(SDIO_ISR_THREAD)
++	if (conf->chip == BCM43012_CHIP_ID ||
++			conf->chip == BCM4335_CHIP_ID || conf->chip == BCM4339_CHIP_ID ||
++			conf->chip == BCM43454_CHIP_ID || conf->chip == BCM4345_CHIP_ID ||
++			conf->chip == BCM4354_CHIP_ID || conf->chip == BCM4356_CHIP_ID ||
++			conf->chip == BCM4345_CHIP_ID || conf->chip == BCM4371_CHIP_ID ||
++			conf->chip == BCM4359_CHIP_ID) {
++		conf->intr_extn = TRUE;
++	}
++#endif
++	if ((conf->chip == BCM43430_CHIP_ID && conf->chiprev == 2) ||
++			conf->chip == BCM43012_CHIP_ID ||
++			conf->chip == BCM4335_CHIP_ID || conf->chip == BCM4339_CHIP_ID ||
++			conf->chip == BCM43454_CHIP_ID || conf->chip == BCM4345_CHIP_ID ||
++			conf->chip == BCM4354_CHIP_ID || conf->chip == BCM4356_CHIP_ID ||
++			conf->chip == BCM4345_CHIP_ID || conf->chip == BCM4371_CHIP_ID ||
++			conf->chip == BCM43569_CHIP_ID || conf->chip == BCM4359_CHIP_ID) {
++#ifdef DHDTCPACK_SUPPRESS
++#ifdef BCMSDIO
++		conf->tcpack_sup_mode = TCPACK_SUP_REPLACE;
++#endif
++#endif
++#if defined(BCMSDIO) || defined(BCMPCIE)
++		dhd_rxbound = 128;
++		dhd_txbound = 64;
++#endif
++		conf->frameburst = 1;
++#ifdef BCMSDIO
++		conf->dhd_txminmax = -1;
++		conf->txinrx_thres = 128;
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
++		conf->orphan_move = 1;
++#else
++		conf->orphan_move = 0;
++#endif
++	}
++
++#ifdef BCMSDIO
++#if defined(BCMSDIOH_TXGLOM_EXT)
++	if (conf->chip == BCM43362_CHIP_ID || conf->chip == BCM4330_CHIP_ID ||
++			conf->chip == BCM43340_CHIP_ID || conf->chip == BCM43341_CHIP_ID ||
++			conf->chip == BCM4334_CHIP_ID || conf->chip == BCM4324_CHIP_ID) {
++		conf->txglom_ext = TRUE;
++	} else {
++		conf->txglom_ext = FALSE;
++	}
++	if (conf->chip == BCM43362_CHIP_ID || conf->chip == BCM4330_CHIP_ID) {
++		conf->txglom_bucket_size = 1680; // fixed value, don't change
++		conf->txglomsize = 6;
++	}
++	if (conf->chip == BCM4334_CHIP_ID || conf->chip == BCM43340_CHIP_ID ||
++			conf->chip == BCM43341_CHIP_ID || conf->chip == BCM4324_CHIP_ID) {
++		conf->txglom_bucket_size = 1684; // fixed value, don't change
++		conf->txglomsize = 16;
++	}
++#endif
++	if (conf->txglomsize > SDPCM_MAXGLOM_SIZE)
++		conf->txglomsize = SDPCM_MAXGLOM_SIZE;
++#endif
++	init_waitqueue_head(&conf->event_complete);
++
++	return 0;
++}
++
++int
++dhd_conf_reset(dhd_pub_t *dhd)
++{
++	struct dhd_conf *conf = dhd->conf;
++
++#ifdef BCMSDIO
++	dhd_conf_free_mac_list(&conf->fw_by_mac);
++	dhd_conf_free_mac_list(&conf->nv_by_mac);
++#endif
++	dhd_conf_free_chip_nv_path_list(&conf->nv_by_chip);
++	dhd_conf_free_country_list(conf);
++	dhd_conf_free_mchan_list(conf);
++	if (conf->magic_pkt_filter_add) {
++		kfree(conf->magic_pkt_filter_add);
++		conf->magic_pkt_filter_add = NULL;
++	}
++	if (conf->wl_preinit) {
++		kfree(conf->wl_preinit);
++		conf->wl_preinit = NULL;
++	}
++	if (conf->wl_suspend) {
++		kfree(conf->wl_suspend);
++		conf->wl_suspend = NULL;
++	}
++	if (conf->wl_resume) {
++		kfree(conf->wl_resume);
++		conf->wl_resume = NULL;
++	}
++	memset(conf, 0, sizeof(dhd_conf_t));
++	return 0;
++}
++
++int
++dhd_conf_attach(dhd_pub_t *dhd)
++{
++	dhd_conf_t *conf;
++
++	CONFIG_TRACE("Enter\n");
++
++	if (dhd->conf != NULL) {
++		CONFIG_MSG("config is attached before!\n");
++		return 0;
++	}
++	/* Allocate private bus interface state */
++	if (!(conf = MALLOC(dhd->osh, sizeof(dhd_conf_t)))) {
++		CONFIG_ERROR("MALLOC failed\n");
++		goto fail;
++	}
++	memset(conf, 0, sizeof(dhd_conf_t));
++
++	dhd->conf = conf;
++
++	return 0;
++
++fail:
++	if (conf != NULL)
++		MFREE(dhd->osh, conf, sizeof(dhd_conf_t));
++	return BCME_NOMEM;
++}
++
++void
++dhd_conf_detach(dhd_pub_t *dhd)
++{
++	struct dhd_conf *conf = dhd->conf;
++
++	CONFIG_TRACE("Enter\n");
++	if (dhd->conf) {
++#ifdef BCMSDIO
++		dhd_conf_free_mac_list(&conf->fw_by_mac);
++		dhd_conf_free_mac_list(&conf->nv_by_mac);
++#endif
++		dhd_conf_free_chip_nv_path_list(&conf->nv_by_chip);
++		dhd_conf_free_country_list(conf);
++		dhd_conf_free_mchan_list(conf);
++		if (conf->magic_pkt_filter_add) {
++			kfree(conf->magic_pkt_filter_add);
++			conf->magic_pkt_filter_add = NULL;
++		}
++		if (conf->wl_preinit) {
++			kfree(conf->wl_preinit);
++			conf->wl_preinit = NULL;
++		}
++		if (conf->wl_suspend) {
++			kfree(conf->wl_suspend);
++			conf->wl_suspend = NULL;
++		}
++		if (conf->wl_resume) {
++			kfree(conf->wl_resume);
++			conf->wl_resume = NULL;
++		}
++		MFREE(dhd->osh, conf, sizeof(dhd_conf_t));
++	}
++	dhd->conf = NULL;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_config.h b/module_drivers/drivers/net/wireless/bcmdhd/dhd_config.h
+new file mode 100644
+index 000000000..045745369
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_config.h
+@@ -0,0 +1,329 @@
++
++#ifndef _dhd_config_
++#define _dhd_config_
++
++#include <bcmdevs.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <wlioctl.h>
++#include <802.11.h>
++
++#define FW_TYPE_STA     0
++#define FW_TYPE_APSTA   1
++#define FW_TYPE_P2P     2
++#define FW_TYPE_MESH    3
++#define FW_TYPE_ES      4
++#define FW_TYPE_MFG     5
++#define FW_TYPE_G       0
++#define FW_TYPE_AG      1
++
++#define FW_PATH_AUTO_SELECT 1
++//#define CONFIG_PATH_AUTO_SELECT
++extern char firmware_path[MOD_PARAM_PATHLEN];
++#if defined(BCMSDIO) || defined(BCMPCIE)
++extern uint dhd_rxbound;
++extern uint dhd_txbound;
++#endif
++#ifdef BCMSDIO
++#define TXGLOM_RECV_OFFSET 8
++extern uint dhd_doflow;
++extern uint dhd_slpauto;
++#endif
++
++typedef struct wl_mac_range {
++	uint32 oui;
++	uint32 nic_start;
++	uint32 nic_end;
++} wl_mac_range_t;
++
++typedef struct wl_mac_list {
++	int count;
++	wl_mac_range_t *mac;
++	char name[MOD_PARAM_PATHLEN];
++} wl_mac_list_t;
++
++typedef struct wl_mac_list_ctrl {
++	int count;
++	struct wl_mac_list *m_mac_list_head;
++} wl_mac_list_ctrl_t;
++
++typedef struct wl_chip_nv_path {
++	uint chip;
++	uint chiprev;
++	char name[MOD_PARAM_PATHLEN];
++} wl_chip_nv_path_t;
++
++typedef struct wl_chip_nv_path_list_ctrl {
++	int count;
++	struct wl_chip_nv_path *m_chip_nv_path_head;
++} wl_chip_nv_path_list_ctrl_t;
++
++typedef struct wl_channel_list {
++	uint32 count;
++	uint32 channel[WL_NUMCHANNELS];
++} wl_channel_list_t;
++
++typedef struct wmes_param {
++	int aifsn[AC_COUNT];
++	int ecwmin[AC_COUNT];
++	int ecwmax[AC_COUNT];
++	int txop[AC_COUNT];
++} wme_param_t;
++
++#ifdef PKT_FILTER_SUPPORT
++#define DHD_CONF_FILTER_MAX	8
++#define PKT_FILTER_LEN 300
++#define MAGIC_PKT_FILTER_LEN 450
++typedef struct conf_pkt_filter_add {
++	uint32 count;
++	char filter[DHD_CONF_FILTER_MAX][PKT_FILTER_LEN];
++} conf_pkt_filter_add_t;
++
++typedef struct conf_pkt_filter_del {
++	uint32 count;
++	uint32 id[DHD_CONF_FILTER_MAX];
++} conf_pkt_filter_del_t;
++#endif
++
++#define CONFIG_COUNTRY_LIST_SIZE 500
++typedef struct country_list {
++	struct country_list *next;
++	wl_country_t cspec;
++} country_list_t;
++
++/* mchan_params */
++#define MCHAN_MAX_NUM 4
++#define MIRACAST_SOURCE	1
++#define MIRACAST_SINK	2
++typedef struct mchan_params {
++	struct mchan_params *next;
++	int bw;
++	int p2p_mode;
++	int miracast_mode;
++} mchan_params_t;
++
++enum in4way_flags {
++	NO_SCAN_IN4WAY	= (1 << (0)),
++	NO_BTC_IN4WAY	= (1 << (1)),
++	DONT_DELETE_GC_AFTER_WPS	= (1 << (2)),
++	WAIT_DISCONNECTED	= (1 << (3)),
++};
++
++enum in_suspend_flags {
++	NO_EVENT_IN_SUSPEND		= (1 << (0)),
++	NO_TXDATA_IN_SUSPEND	= (1 << (1)),
++	NO_TXCTL_IN_SUSPEND		= (1 << (2)),
++	AP_DOWN_IN_SUSPEND		= (1 << (3)),
++	ROAM_OFFLOAD_IN_SUSPEND	= (1 << (4)),
++	AP_FILTER_IN_SUSPEND	= (1 << (5)),
++	WOWL_IN_SUSPEND			= (1 << (6)),
++	ALL_IN_SUSPEND 			= 0xFFFFFFFF,
++};
++
++enum in_suspend_mode {
++	EARLY_SUSPEND = 0,
++	PM_NOTIFIER = 1
++};
++
++enum eapol_status {
++	EAPOL_STATUS_NONE = 0,
++	EAPOL_STATUS_REQID = 1,
++	EAPOL_STATUS_RSPID = 2,
++	EAPOL_STATUS_WSC_START = 3,
++	EAPOL_STATUS_WPS_M1 = 4,
++	EAPOL_STATUS_WPS_M2 = 5,
++	EAPOL_STATUS_WPS_M3 = 6,
++	EAPOL_STATUS_WPS_M4 = 7,
++	EAPOL_STATUS_WPS_M5 = 8,
++	EAPOL_STATUS_WPS_M6 = 9,
++	EAPOL_STATUS_WPS_M7 = 10,
++	EAPOL_STATUS_WPS_M8 = 11,
++	EAPOL_STATUS_WSC_DONE = 12,
++	EAPOL_STATUS_4WAY_START = 13,
++	EAPOL_STATUS_4WAY_M1 = 14,
++	EAPOL_STATUS_4WAY_M2 = 15,
++	EAPOL_STATUS_4WAY_M3 = 16,
++	EAPOL_STATUS_4WAY_M4 = 17,
++	EAPOL_STATUS_GROUPKEY_M1 = 18,
++	EAPOL_STATUS_GROUPKEY_M2 = 19,
++	EAPOL_STATUS_4WAY_DONE = 20
++};
++
++typedef struct dhd_conf {
++	uint chip;
++	uint chiprev;
++#ifdef GET_OTP_MODULE_NAME
++	char module_name[16];
++#endif
++	struct ether_addr otp_mac;
++	int fw_type;
++#ifdef BCMSDIO
++	wl_mac_list_ctrl_t fw_by_mac;
++	wl_mac_list_ctrl_t nv_by_mac;
++#endif
++	wl_chip_nv_path_list_ctrl_t nv_by_chip;
++	country_list_t *country_head;
++	int band;
++	int bw_cap[2];
++	wl_country_t cspec;
++	wl_channel_list_t channels;
++	uint roam_off;
++	uint roam_off_suspend;
++	int roam_trigger[2];
++	int roam_scan_period[2];
++	int roam_delta[2];
++	int fullroamperiod;
++	uint keep_alive_period;
++#ifdef ARP_OFFLOAD_SUPPORT
++	bool garp;
++#endif
++	int force_wme_ac;
++	wme_param_t wme_sta;
++	wme_param_t wme_ap;
++#ifdef PKT_FILTER_SUPPORT
++	conf_pkt_filter_add_t pkt_filter_add;
++	conf_pkt_filter_del_t pkt_filter_del;
++	char *magic_pkt_filter_add;
++#endif
++	int srl;
++	int lrl;
++	uint bcn_timeout;
++	int disable_proptx;
++	int dhd_poll;
++#ifdef BCMSDIO
++	int use_rxchain;
++	bool bus_rxglom;
++	bool txglom_ext; /* Only for 43362/4330/43340/43341/43241 */
++	/* terence 20161011:
++	    1) conf->tx_max_offset = 1 to fix credict issue in adaptivity testing
++	    2) conf->tx_max_offset = 1 will cause to UDP Tx not work in rxglom supported,
++	        but not happened in sw txglom
++	*/
++	int tx_max_offset;
++	uint txglomsize;
++	int txctl_tmo_fix;
++	bool txglom_mode;
++	uint deferred_tx_len;
++	/*txglom_bucket_size:
++	 * 43362/4330: 1680
++	 * 43340/43341/43241: 1684
++	 */
++	int txglom_bucket_size;
++	int txinrx_thres;
++	int dhd_txminmax; // -1=DATABUFCNT(bus)
++	bool oob_enabled_later;
++#if defined(SDIO_ISR_THREAD)
++	bool intr_extn;
++#endif
++#ifdef BCMSDIO_RXLIM_POST
++	bool rxlim_en;
++#endif
++#endif
++#ifdef BCMPCIE
++	int bus_deepsleep_disable;
++#endif
++	int dpc_cpucore;
++	int rxf_cpucore;
++	int frameburst;
++	bool deepsleep;
++	int pm;
++	int pm_in_suspend;
++	int suspend_mode;
++	int suspend_bcn_li_dtim;
++#ifdef DHDTCPACK_SUPPRESS
++	uint8 tcpack_sup_mode;
++#endif
++	int pktprio8021x;
++	uint insuspend;
++	bool suspended;
++#ifdef SUSPEND_EVENT
++	char resume_eventmask[WL_EVENTING_MASK_LEN];
++	struct ether_addr bssid_insuspend;
++	bool wlfc;
++#endif
++#ifdef IDHCP
++	int dhcpc_enable;
++	int dhcpd_enable;
++	struct ipv4_addr dhcpd_ip_addr;
++	struct ipv4_addr dhcpd_ip_mask;
++	struct ipv4_addr dhcpd_ip_start;
++	struct ipv4_addr dhcpd_ip_end;
++#endif
++#ifdef ISAM_PREINIT
++	char isam_init[50];
++	char isam_config[300];
++	char isam_enable[50];
++#endif
++	int ctrl_resched;
++	mchan_params_t *mchan;
++	char *wl_preinit;
++	char *wl_suspend;
++	char *wl_resume;
++	int tsq;
++	int orphan_move;
++	uint eapol_status;
++	uint in4way;
++#ifdef WL_EXT_WOWL
++	uint wowl;
++#endif
++#ifdef GET_CUSTOM_MAC_FROM_CONFIG
++	char hw_ether[62];
++#endif
++	wait_queue_head_t event_complete;
++} dhd_conf_t;
++
++#ifdef BCMSDIO
++void dhd_conf_get_otp(dhd_pub_t *dhd, bcmsdh_info_t *sdh);
++#if defined(HW_OOB) || defined(FORCE_WOWLAN)
++void dhd_conf_set_hw_oob_intr(bcmsdh_info_t *sdh, uint chip);
++#endif
++void dhd_conf_set_txglom_params(dhd_pub_t *dhd, bool enable);
++int dhd_conf_set_blksize(bcmsdh_info_t *sdh);
++#endif
++void dhd_conf_set_path_params(dhd_pub_t *dhd, char *fw_path, char *nv_path);
++int dhd_conf_set_intiovar(dhd_pub_t *dhd, uint cmd, char *name, int val,
++	int def, bool down);
++int dhd_conf_get_band(dhd_pub_t *dhd);
++int dhd_conf_set_country(dhd_pub_t *dhd, wl_country_t *cspec);
++int dhd_conf_get_country(dhd_pub_t *dhd, wl_country_t *cspec);
++int dhd_conf_map_country_list(dhd_pub_t *dhd, wl_country_t *cspec);
++#ifdef CCODE_LIST
++int dhd_ccode_map_country_list(dhd_pub_t *dhd, wl_country_t *cspec);
++#endif
++int dhd_conf_fix_country(dhd_pub_t *dhd);
++bool dhd_conf_match_channel(dhd_pub_t *dhd, uint32 channel);
++void dhd_conf_set_wme(dhd_pub_t *dhd, int ifidx, int mode);
++void dhd_conf_set_mchan_bw(dhd_pub_t *dhd, int go, int source);
++void dhd_conf_add_pkt_filter(dhd_pub_t *dhd);
++bool dhd_conf_del_pkt_filter(dhd_pub_t *dhd, uint32 id);
++void dhd_conf_discard_pkt_filter(dhd_pub_t *dhd);
++int dhd_conf_read_config(dhd_pub_t *dhd, char *conf_path);
++int dhd_conf_set_chiprev(dhd_pub_t *dhd, uint chip, uint chiprev);
++uint dhd_conf_get_chip(void *context);
++uint dhd_conf_get_chiprev(void *context);
++int dhd_conf_get_pm(dhd_pub_t *dhd);
++int dhd_conf_check_hostsleep(dhd_pub_t *dhd, int cmd, void *buf, int len,
++	int *hostsleep_set, int *hostsleep_val, int *ret);
++void dhd_conf_get_hostsleep(dhd_pub_t *dhd,
++	int hostsleep_set, int hostsleep_val, int ret);
++int dhd_conf_mkeep_alive(dhd_pub_t *dhd, int ifidx, int id, int period,
++	char *packet, bool bcast);
++#ifdef ARP_OFFLOAD_SUPPORT
++void dhd_conf_set_garp(dhd_pub_t *dhd, int ifidx, uint32 ipa, bool enable);
++#endif
++#ifdef PROP_TXSTATUS
++int dhd_conf_get_disable_proptx(dhd_pub_t *dhd);
++#endif
++uint dhd_conf_get_insuspend(dhd_pub_t *dhd, uint mask);
++int dhd_conf_set_suspend_resume(dhd_pub_t *dhd, int suspend);
++void dhd_conf_postinit_ioctls(dhd_pub_t *dhd);
++int dhd_conf_preinit(dhd_pub_t *dhd);
++int dhd_conf_reset(dhd_pub_t *dhd);
++int dhd_conf_attach(dhd_pub_t *dhd);
++void dhd_conf_detach(dhd_pub_t *dhd);
++void *dhd_get_pub(struct net_device *dev);
++int wl_pattern_atoh(char *src, char *dst);
++#ifdef BCMSDIO
++extern int dhd_bus_sleep(dhd_pub_t *dhdp, bool sleep, uint32 *intstatus);
++#endif
++#endif /* _dhd_config_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_custom_gpio.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_custom_gpio.c
+new file mode 100644
+index 000000000..0aa51ca97
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_custom_gpio.c
+@@ -0,0 +1,299 @@
++/*
++ * Customer code to add GPIO control during WLAN start/stop
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_custom_gpio.c 664997 2016-10-14 11:56:35Z $
++ */
++
++#include <typedefs.h>
++#include <linuxver.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_linux.h>
++
++#include <wlioctl.h>
++
++#define WL_ERROR(x) printf x
++#define WL_TRACE(x)
++
++#if defined(OOB_INTR_ONLY)
++
++#if defined(BCMLXSDMMC)
++extern int sdioh_mmc_irq(int irq);
++#endif /* (BCMLXSDMMC)  */
++
++/* Customer specific Host GPIO defintion  */
++static int dhd_oob_gpio_num = -1;
++
++module_param(dhd_oob_gpio_num, int, 0644);
++MODULE_PARM_DESC(dhd_oob_gpio_num, "DHD oob gpio number");
++
++/* This function will return:
++ *  1) return :  Host gpio interrupt number per customer platform
++ *  2) irq_flags_ptr : Type of Host interrupt as Level or Edge
++ *
++ *  NOTE :
++ *  Customer should check his platform definitions
++ *  and his Host Interrupt spec
++ *  to figure out the proper setting for his platform.
++ *  Broadcom provides just reference settings as example.
++ *
++ */
++int dhd_customer_oob_irq_map(void *adapter, unsigned long *irq_flags_ptr)
++{
++	int  host_oob_irq = 0;
++
++#if defined(CUSTOMER_HW2)
++	host_oob_irq = wifi_platform_get_irq_number(adapter, irq_flags_ptr);
++
++#else
++#if defined(CUSTOM_OOB_GPIO_NUM)
++	if (dhd_oob_gpio_num < 0) {
++		dhd_oob_gpio_num = CUSTOM_OOB_GPIO_NUM;
++	}
++#endif /* CUSTOMER_OOB_GPIO_NUM */
++
++	if (dhd_oob_gpio_num < 0) {
++		WL_ERROR(("%s: ERROR customer specific Host GPIO is NOT defined \n",
++		__FUNCTION__));
++		return (dhd_oob_gpio_num);
++	}
++
++	WL_ERROR(("%s: customer specific Host GPIO number is (%d)\n",
++	         __FUNCTION__, dhd_oob_gpio_num));
++
++#endif 
++
++	return (host_oob_irq);
++}
++#endif 
++
++/* Customer function to control hw specific wlan gpios */
++int
++dhd_customer_gpio_wlan_ctrl(void *adapter, int onoff)
++{
++	int err = 0;
++
++	return err;
++}
++
++#ifdef GET_CUSTOM_MAC_ENABLE
++/* Function to get custom MAC address */
++int
++dhd_custom_get_mac_address(void *adapter, unsigned char *buf)
++{
++	int ret = 0;
++
++	WL_TRACE(("%s Enter\n", __FUNCTION__));
++	if (!buf)
++		return -EINVAL;
++
++	/* Customer access to MAC address stored outside of DHD driver */
++#if defined(CUSTOMER_HW2) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	ret = wifi_platform_get_mac_addr(adapter, buf);
++#endif
++
++#ifdef EXAMPLE_GET_MAC
++	/* EXAMPLE code */
++	{
++		struct ether_addr ea_example = {{0x00, 0x11, 0x22, 0x33, 0x44, 0xFF}};
++		bcopy((char *)&ea_example, buf, sizeof(struct ether_addr));
++	}
++#endif /* EXAMPLE_GET_MAC */
++
++	return ret;
++}
++#endif /* GET_CUSTOM_MAC_ENABLE */
++
++/* Customized Locale table : OPTIONAL feature */
++const struct cntry_locales_custom translate_custom_table[] = {
++/* Table should be filled out based on custom platform regulatory requirement */
++#ifdef EXAMPLE_TABLE
++	{"",   "XY", 4},  /* Universal if Country code is unknown or empty */
++	{"US", "US", 69}, /* input ISO "US" to : US regrev 69 */
++	{"CA", "US", 69}, /* input ISO "CA" to : US regrev 69 */
++	{"EU", "EU", 5},  /* European union countries to : EU regrev 05 */
++	{"AT", "EU", 5},
++	{"BE", "EU", 5},
++	{"BG", "EU", 5},
++	{"CY", "EU", 5},
++	{"CZ", "EU", 5},
++	{"DK", "EU", 5},
++	{"EE", "EU", 5},
++	{"FI", "EU", 5},
++	{"FR", "EU", 5},
++	{"DE", "EU", 5},
++	{"GR", "EU", 5},
++	{"HU", "EU", 5},
++	{"IE", "EU", 5},
++	{"IT", "EU", 5},
++	{"LV", "EU", 5},
++	{"LI", "EU", 5},
++	{"LT", "EU", 5},
++	{"LU", "EU", 5},
++	{"MT", "EU", 5},
++	{"NL", "EU", 5},
++	{"PL", "EU", 5},
++	{"PT", "EU", 5},
++	{"RO", "EU", 5},
++	{"SK", "EU", 5},
++	{"SI", "EU", 5},
++	{"ES", "EU", 5},
++	{"SE", "EU", 5},
++	{"GB", "EU", 5},
++	{"KR", "XY", 3},
++	{"AU", "XY", 3},
++	{"CN", "XY", 3}, /* input ISO "CN" to : XY regrev 03 */
++	{"TW", "XY", 3},
++	{"AR", "XY", 3},
++	{"MX", "XY", 3},
++	{"IL", "IL", 0},
++	{"CH", "CH", 0},
++	{"TR", "TR", 0},
++	{"NO", "NO", 0},
++#endif /* EXMAPLE_TABLE */
++#if defined(CUSTOMER_HW2)
++#if defined(BCM4335_CHIP)
++	{"",   "XZ", 11},  /* Universal if Country code is unknown or empty */
++#endif
++	{"AE", "AE", 1},
++	{"AR", "AR", 1},
++	{"AT", "AT", 1},
++	{"AU", "AU", 2},
++	{"BE", "BE", 1},
++	{"BG", "BG", 1},
++	{"BN", "BN", 1},
++	{"CA", "CA", 2},
++	{"CH", "CH", 1},
++	{"CY", "CY", 1},
++	{"CZ", "CZ", 1},
++	{"DE", "DE", 3},
++	{"DK", "DK", 1},
++	{"EE", "EE", 1},
++	{"ES", "ES", 1},
++	{"FI", "FI", 1},
++	{"FR", "FR", 1},
++	{"GB", "GB", 1},
++	{"GR", "GR", 1},
++	{"HR", "HR", 1},
++	{"HU", "HU", 1},
++	{"IE", "IE", 1},
++	{"IS", "IS", 1},
++	{"IT", "IT", 1},
++	{"ID", "ID", 1},
++	{"JP", "JP", 8},
++	{"KR", "KR", 24},
++	{"KW", "KW", 1},
++	{"LI", "LI", 1},
++	{"LT", "LT", 1},
++	{"LU", "LU", 1},
++	{"LV", "LV", 1},
++	{"MA", "MA", 1},
++	{"MT", "MT", 1},
++	{"MX", "MX", 1},
++	{"NL", "NL", 1},
++	{"NO", "NO", 1},
++	{"PL", "PL", 1},
++	{"PT", "PT", 1},
++	{"PY", "PY", 1},
++	{"RO", "RO", 1},
++	{"SE", "SE", 1},
++	{"SI", "SI", 1},
++	{"SK", "SK", 1},
++	{"TR", "TR", 7},
++	{"TW", "TW", 1},
++	{"IR", "XZ", 11},	/* Universal if Country code is IRAN, (ISLAMIC REPUBLIC OF) */
++	{"SD", "XZ", 11},	/* Universal if Country code is SUDAN */
++	{"SY", "XZ", 11},	/* Universal if Country code is SYRIAN ARAB REPUBLIC */
++	{"GL", "XZ", 11},	/* Universal if Country code is GREENLAND */
++	{"PS", "XZ", 11},	/* Universal if Country code is PALESTINIAN TERRITORY, OCCUPIED */
++	{"TL", "XZ", 11},	/* Universal if Country code is TIMOR-LESTE (EAST TIMOR) */
++	{"MH", "XZ", 11},	/* Universal if Country code is MARSHALL ISLANDS */
++#ifdef BCM4330_CHIP
++	{"RU", "RU", 1},
++	{"US", "US", 5}
++#endif
++#endif 
++};
++
++
++/* Customized Locale convertor
++*  input : ISO 3166-1 country abbreviation
++*  output: customized cspec
++*/
++void
++#ifdef CUSTOM_COUNTRY_CODE
++get_customized_country_code(void *adapter, char *country_iso_code,
++	wl_country_t *cspec, u32 flags)
++#else
++get_customized_country_code(void *adapter, char *country_iso_code, wl_country_t *cspec)
++#endif /* CUSTOM_COUNTRY_CODE */
++{
++#if (defined(CUSTOMER_HW) || defined(CUSTOMER_HW2)) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39))
++
++	struct cntry_locales_custom *cloc_ptr;
++
++	if (!cspec)
++		return;
++#ifdef CUSTOM_COUNTRY_CODE
++	cloc_ptr = wifi_platform_get_country_code(adapter, country_iso_code, flags);
++#else
++	cloc_ptr = wifi_platform_get_country_code(adapter, country_iso_code);
++#endif /* CUSTOM_COUNTRY_CODE */
++
++	if (cloc_ptr) {
++		strlcpy(cspec->ccode, cloc_ptr->custom_locale, WLC_CNTRY_BUF_SZ);
++		cspec->rev = cloc_ptr->custom_locale_rev;
++	}
++	return;
++#else
++	int size, i;
++
++	size = ARRAYSIZE(translate_custom_table);
++
++	if (cspec == 0)
++		 return;
++
++	if (size == 0)
++		 return;
++
++	for (i = 0; i < size; i++) {
++		if (strcmp(country_iso_code, translate_custom_table[i].iso_abbrev) == 0) {
++			memcpy(cspec->ccode,
++				translate_custom_table[i].custom_locale, WLC_CNTRY_BUF_SZ);
++			cspec->rev = translate_custom_table[i].custom_locale_rev;
++			return;
++		}
++	}
++#ifdef EXAMPLE_TABLE
++	/* if no country code matched return first universal code from translate_custom_table */
++	memcpy(cspec->ccode, translate_custom_table[0].custom_locale, WLC_CNTRY_BUF_SZ);
++	cspec->rev = translate_custom_table[0].custom_locale_rev;
++#endif /* EXMAPLE_TABLE */
++	return;
++#endif /* defined(CUSTOMER_HW2) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) */
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_custom_memprealloc.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_custom_memprealloc.c
+new file mode 100644
+index 000000000..1f593a488
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_custom_memprealloc.c
+@@ -0,0 +1,513 @@
++/*
++ * Platform Dependent file for usage of Preallocted Memory
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_custom_memprealloc.c 707595 2017-06-28 08:28:30Z $
++ */
++
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/miscdevice.h>
++#include <linux/sched.h>
++#include <linux/module.h>
++#include <linux/fs.h>
++#include <linux/list.h>
++#include <linux/io.h>
++#include <linux/workqueue.h>
++#include <linux/unistd.h>
++#include <linux/bug.h>
++#include <linux/skbuff.h>
++#include <linux/init.h>
++
++#ifdef CONFIG_BROADCOM_WIFI_RESERVED_MEM
++
++#define WLAN_STATIC_SCAN_BUF0		5
++#define WLAN_STATIC_SCAN_BUF1		6
++#define WLAN_STATIC_DHD_INFO_BUF	7
++#define WLAN_STATIC_DHD_WLFC_BUF	8
++#define WLAN_STATIC_DHD_IF_FLOW_LKUP	9
++#define WLAN_STATIC_DHD_MEMDUMP_RAM	11
++#define WLAN_STATIC_DHD_WLFC_HANGER	12
++#define WLAN_STATIC_DHD_PKTID_MAP	13
++#define WLAN_STATIC_DHD_PKTID_IOCTL_MAP	14
++#define WLAN_STATIC_DHD_LOG_DUMP_BUF	15
++#define WLAN_STATIC_DHD_LOG_DUMP_BUF_EX	16
++#define WLAN_STATIC_DHD_PKTLOG_DUMP_BUF	17
++#define WLAN_STATIC_STAT_REPORT_BUF		18
++
++#define WLAN_SCAN_BUF_SIZE		(64 * 1024)
++
++#if defined(CONFIG_64BIT)
++#define WLAN_DHD_INFO_BUF_SIZE		(32 * 1024)
++#define WLAN_DHD_WLFC_BUF_SIZE		(64 * 1024)
++#define WLAN_DHD_IF_FLOW_LKUP_SIZE	(64 * 1024)
++#else
++#define WLAN_DHD_INFO_BUF_SIZE		(32 * 1024)
++#define WLAN_DHD_WLFC_BUF_SIZE		(16 * 1024)
++#define WLAN_DHD_IF_FLOW_LKUP_SIZE	(20 * 1024)
++#endif /* CONFIG_64BIT */
++#define WLAN_DHD_MEMDUMP_SIZE		(1536 * 1024)
++
++#define PREALLOC_WLAN_SEC_NUM		4
++#define PREALLOC_WLAN_BUF_NUM		160
++#define PREALLOC_WLAN_SECTION_HEADER	24
++
++#ifdef CONFIG_BCMDHD_PCIE
++#define DHD_SKB_1PAGE_BUFSIZE	(PAGE_SIZE*1)
++#define DHD_SKB_2PAGE_BUFSIZE	(PAGE_SIZE*2)
++#define DHD_SKB_4PAGE_BUFSIZE	(PAGE_SIZE*4)
++
++#define WLAN_SECTION_SIZE_0	(PREALLOC_WLAN_BUF_NUM * 128)
++#define WLAN_SECTION_SIZE_1	0
++#define WLAN_SECTION_SIZE_2	0
++#define WLAN_SECTION_SIZE_3	(PREALLOC_WLAN_BUF_NUM * 1024)
++
++#define DHD_SKB_1PAGE_BUF_NUM	0
++#define DHD_SKB_2PAGE_BUF_NUM	128
++#define DHD_SKB_4PAGE_BUF_NUM	0
++
++#else
++#define DHD_SKB_HDRSIZE		336
++#define DHD_SKB_1PAGE_BUFSIZE	((PAGE_SIZE*1)-DHD_SKB_HDRSIZE)
++#define DHD_SKB_2PAGE_BUFSIZE	((PAGE_SIZE*2)-DHD_SKB_HDRSIZE)
++#define DHD_SKB_4PAGE_BUFSIZE	((PAGE_SIZE*4)-DHD_SKB_HDRSIZE)
++
++#define WLAN_SECTION_SIZE_0	(PREALLOC_WLAN_BUF_NUM * 128)
++#define WLAN_SECTION_SIZE_1	(PREALLOC_WLAN_BUF_NUM * 128)
++#define WLAN_SECTION_SIZE_2	(PREALLOC_WLAN_BUF_NUM * 512)
++#define WLAN_SECTION_SIZE_3	(PREALLOC_WLAN_BUF_NUM * 1024)
++
++#define DHD_SKB_1PAGE_BUF_NUM	8
++#define DHD_SKB_2PAGE_BUF_NUM	8
++#define DHD_SKB_4PAGE_BUF_NUM	1
++#endif /* CONFIG_BCMDHD_PCIE */
++
++#define WLAN_SKB_1_2PAGE_BUF_NUM	((DHD_SKB_1PAGE_BUF_NUM) + \
++		(DHD_SKB_2PAGE_BUF_NUM))
++#define WLAN_SKB_BUF_NUM	((WLAN_SKB_1_2PAGE_BUF_NUM) + \
++		(DHD_SKB_4PAGE_BUF_NUM))
++
++#define WLAN_MAX_PKTID_ITEMS		(8192)
++#define WLAN_DHD_PKTID_MAP_HDR_SIZE	(20 + 4*(WLAN_MAX_PKTID_ITEMS + 1))
++#define WLAN_DHD_PKTID_MAP_ITEM_SIZE	(32)
++#define WLAN_DHD_PKTID_MAP_SIZE		((WLAN_DHD_PKTID_MAP_HDR_SIZE) + \
++		((WLAN_MAX_PKTID_ITEMS+1) * WLAN_DHD_PKTID_MAP_ITEM_SIZE))
++
++#define WLAN_MAX_PKTID_IOCTL_ITEMS	(32)
++#define WLAN_DHD_PKTID_IOCTL_MAP_HDR_SIZE	(20 + 4*(WLAN_MAX_PKTID_IOCTL_ITEMS + 1))
++#define WLAN_DHD_PKTID_IOCTL_MAP_ITEM_SIZE	(32)
++#define WLAN_DHD_PKTID_IOCTL_MAP_SIZE		((WLAN_DHD_PKTID_IOCTL_MAP_HDR_SIZE) + \
++		((WLAN_MAX_PKTID_IOCTL_ITEMS+1) * WLAN_DHD_PKTID_IOCTL_MAP_ITEM_SIZE))
++
++#define DHD_LOG_DUMP_BUF_SIZE	(1024 * 1024)
++#define DHD_LOG_DUMP_BUF_EX_SIZE	(8 * 1024)
++
++#define DHD_PKTLOG_DUMP_BUF_SIZE	(64 * 1024)
++
++#define DHD_STAT_REPORT_BUF_SIZE	(128 * 1024)
++
++#define WLAN_DHD_WLFC_HANGER_MAXITEMS		3072
++#define WLAN_DHD_WLFC_HANGER_ITEM_SIZE		32
++#define WLAN_DHD_WLFC_HANGER_SIZE	((WLAN_DHD_WLFC_HANGER_ITEM_SIZE) + \
++	((WLAN_DHD_WLFC_HANGER_MAXITEMS) * (WLAN_DHD_WLFC_HANGER_ITEM_SIZE)))
++
++static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
++
++struct wlan_mem_prealloc {
++	void *mem_ptr;
++	unsigned long size;
++};
++
++static struct wlan_mem_prealloc wlan_mem_array[PREALLOC_WLAN_SEC_NUM] = {
++	{NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
++	{NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
++	{NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
++	{NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
++};
++
++static void *wlan_static_scan_buf0 = NULL;
++static void *wlan_static_scan_buf1 = NULL;
++static void *wlan_static_dhd_info_buf = NULL;
++static void *wlan_static_dhd_wlfc_buf = NULL;
++static void *wlan_static_if_flow_lkup = NULL;
++static void *wlan_static_dhd_memdump_ram = NULL;
++static void *wlan_static_dhd_wlfc_hanger = NULL;
++static void *wlan_static_dhd_pktid_map = NULL;
++static void *wlan_static_dhd_pktid_ioctl_map = NULL;
++static void *wlan_static_dhd_log_dump_buf = NULL;
++static void *wlan_static_dhd_log_dump_buf_ex = NULL;
++static void *wlan_static_dhd_pktlog_dump_buf = NULL;
++static void *wlan_static_stat_report_buf = NULL;
++
++#define GET_STATIC_BUF(section, config_size, req_size, buf) ({\
++	void *__ret; \
++	if (req_size > config_size) {\
++		pr_err("request " #section " size(%lu) is bigger than" \
++				" static size(%d)\n", \
++				req_size, config_size); \
++		__ret = NULL; \
++	} else { __ret = buf;} \
++	__ret; \
++})
++
++void
++*dhd_wlan_mem_prealloc(int section, unsigned long size)
++{
++	if (section == PREALLOC_WLAN_SEC_NUM) {
++		return wlan_static_skb;
++	}
++
++	if (section == WLAN_STATIC_SCAN_BUF0) {
++		return wlan_static_scan_buf0;
++	}
++
++	if (section == WLAN_STATIC_SCAN_BUF1) {
++		return wlan_static_scan_buf1;
++	}
++
++	if (section == WLAN_STATIC_DHD_INFO_BUF) {
++		if (size > WLAN_DHD_INFO_BUF_SIZE) {
++			pr_err("request DHD_INFO size(%lu) is bigger than"
++				" static size(%d).\n", size,
++				WLAN_DHD_INFO_BUF_SIZE);
++			return NULL;
++		}
++		return wlan_static_dhd_info_buf;
++	}
++
++	if (section == WLAN_STATIC_DHD_WLFC_BUF)  {
++		if (size > WLAN_DHD_WLFC_BUF_SIZE) {
++			pr_err("request DHD_WLFC size(%lu) is bigger than"
++				" static size(%d).\n",
++				size, WLAN_DHD_WLFC_BUF_SIZE);
++			return NULL;
++		}
++		return wlan_static_dhd_wlfc_buf;
++	}
++
++	if (section == WLAN_STATIC_DHD_WLFC_HANGER) {
++		if (size > WLAN_DHD_WLFC_HANGER_SIZE) {
++			pr_err("request DHD_WLFC_HANGER size(%lu) is bigger than"
++				" static size(%d).\n",
++				size, WLAN_DHD_WLFC_HANGER_SIZE);
++			return NULL;
++		}
++		return wlan_static_dhd_wlfc_hanger;
++	}
++
++	if (section == WLAN_STATIC_DHD_IF_FLOW_LKUP)  {
++		if (size > WLAN_DHD_IF_FLOW_LKUP_SIZE) {
++			pr_err("request DHD_WLFC size(%lu) is bigger than"
++				" static size(%d).\n",
++				size, WLAN_DHD_WLFC_BUF_SIZE);
++			return NULL;
++		}
++		return wlan_static_if_flow_lkup;
++	}
++
++	if (section == WLAN_STATIC_DHD_MEMDUMP_RAM) {
++		if (size > WLAN_DHD_MEMDUMP_SIZE) {
++			pr_err("request DHD_MEMDUMP_RAM size(%lu) is bigger"
++				" than static size(%d).\n",
++				size, WLAN_DHD_MEMDUMP_SIZE);
++			return NULL;
++		}
++		return wlan_static_dhd_memdump_ram;
++	}
++
++	if (section == WLAN_STATIC_DHD_PKTID_MAP)  {
++		if (size > WLAN_DHD_PKTID_MAP_SIZE) {
++			pr_err("request DHD_PKTID_MAP size(%lu) is bigger than"
++				" static size(%d).\n",
++				size, WLAN_DHD_PKTID_MAP_SIZE);
++			return NULL;
++		}
++		return wlan_static_dhd_pktid_map;
++	}
++
++
++	if (section == WLAN_STATIC_DHD_PKTID_IOCTL_MAP)  {
++		if (size > WLAN_DHD_PKTID_IOCTL_MAP_SIZE) {
++			pr_err("request DHD_PKTID_IOCTL_MAP size(%lu) is bigger than"
++				" static size(%d).\n",
++				size, WLAN_DHD_PKTID_IOCTL_MAP_SIZE);
++			return NULL;
++		}
++		return wlan_static_dhd_pktid_ioctl_map;
++	}
++
++	if (section == WLAN_STATIC_DHD_LOG_DUMP_BUF) {
++		if (size > DHD_LOG_DUMP_BUF_SIZE) {
++			pr_err("request DHD_LOG_DUMP_BUF size(%lu) is bigger then"
++				" static size(%d).\n",
++				size, DHD_LOG_DUMP_BUF_SIZE);
++			return NULL;
++		}
++		return wlan_static_dhd_log_dump_buf;
++	}
++
++	if (section == WLAN_STATIC_DHD_LOG_DUMP_BUF_EX) {
++		if (size > DHD_LOG_DUMP_BUF_EX_SIZE) {
++			pr_err("request DHD_LOG_DUMP_BUF_EX size(%lu) is bigger then"
++				" static size(%d).\n",
++				size, DHD_LOG_DUMP_BUF_EX_SIZE);
++			return NULL;
++		}
++		return wlan_static_dhd_log_dump_buf_ex;
++	}
++
++	if (section == WLAN_STATIC_DHD_PKTLOG_DUMP_BUF) {
++		if (size > DHD_PKTLOG_DUMP_BUF_SIZE) {
++			pr_err("request DHD_PKTLOG_DUMP_BUF size(%lu) is bigger then"
++					" static size(%d).\n",
++					size, DHD_PKTLOG_DUMP_BUF_SIZE);
++			return NULL;
++		}
++		return wlan_static_dhd_pktlog_dump_buf;
++	}
++
++	if (section == WLAN_STATIC_STAT_REPORT_BUF) {
++		return GET_STATIC_BUF(WLAN_STATIC_STAT_REPORT_BUF,
++			DHD_STAT_REPORT_BUF_SIZE, size, wlan_static_stat_report_buf);
++	}
++
++	if ((section < 0) || (section >= PREALLOC_WLAN_SEC_NUM)) {
++		return NULL;
++	}
++
++	if (wlan_mem_array[section].size < size) {
++		return NULL;
++	}
++
++	return wlan_mem_array[section].mem_ptr;
++}
++EXPORT_SYMBOL(dhd_wlan_mem_prealloc);
++
++int
++dhd_init_wlan_mem(void)
++{
++	int i;
++	int j;
++
++	for (i = 0; i < DHD_SKB_1PAGE_BUF_NUM; i++) {
++		wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_1PAGE_BUFSIZE);
++		if (!wlan_static_skb[i]) {
++			goto err_skb_alloc;
++		}
++	}
++
++	for (i = DHD_SKB_1PAGE_BUF_NUM; i < WLAN_SKB_1_2PAGE_BUF_NUM; i++) {
++		wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_2PAGE_BUFSIZE);
++		if (!wlan_static_skb[i]) {
++			goto err_skb_alloc;
++		}
++	}
++
++#if !defined(CONFIG_BCMDHD_PCIE)
++	wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_4PAGE_BUFSIZE);
++	if (!wlan_static_skb[i]) {
++		goto err_skb_alloc;
++	}
++#endif /* !CONFIG_BCMDHD_PCIE */
++
++	for (i = 0; i < PREALLOC_WLAN_SEC_NUM; i++) {
++		if (wlan_mem_array[i].size > 0) {
++			wlan_mem_array[i].mem_ptr =
++				kmalloc(wlan_mem_array[i].size, GFP_KERNEL);
++
++			if (!wlan_mem_array[i].mem_ptr) {
++				goto err_mem_alloc;
++			}
++		}
++	}
++
++	wlan_static_scan_buf0 = kmalloc(WLAN_SCAN_BUF_SIZE, GFP_KERNEL);
++	if (!wlan_static_scan_buf0) {
++		pr_err("Failed to alloc wlan_static_scan_buf0\n");
++		goto err_mem_alloc;
++	}
++
++	wlan_static_scan_buf1 = kmalloc(WLAN_SCAN_BUF_SIZE, GFP_KERNEL);
++	if (!wlan_static_scan_buf1) {
++		pr_err("Failed to alloc wlan_static_scan_buf1\n");
++		goto err_mem_alloc;
++	}
++
++	wlan_static_dhd_log_dump_buf = kmalloc(DHD_LOG_DUMP_BUF_SIZE, GFP_KERNEL);
++	if (!wlan_static_dhd_log_dump_buf) {
++		pr_err("Failed to alloc wlan_static_dhd_log_dump_buf\n");
++		goto err_mem_alloc;
++	}
++
++	wlan_static_dhd_log_dump_buf_ex = kmalloc(DHD_LOG_DUMP_BUF_EX_SIZE, GFP_KERNEL);
++	if (!wlan_static_dhd_log_dump_buf_ex) {
++		pr_err("Failed to alloc wlan_static_dhd_log_dump_buf_ex\n");
++		goto err_mem_alloc;
++	}
++
++	wlan_static_dhd_info_buf = kmalloc(WLAN_DHD_INFO_BUF_SIZE, GFP_KERNEL);
++	if (!wlan_static_dhd_info_buf) {
++		pr_err("Failed to alloc wlan_static_dhd_info_buf\n");
++		goto err_mem_alloc;
++	}
++
++#ifdef CONFIG_BCMDHD_PCIE
++	wlan_static_if_flow_lkup = kmalloc(WLAN_DHD_IF_FLOW_LKUP_SIZE,
++		GFP_KERNEL);
++	if (!wlan_static_if_flow_lkup) {
++		pr_err("Failed to alloc wlan_static_if_flow_lkup\n");
++		goto err_mem_alloc;
++	}
++
++#ifdef CONFIG_BCMDHD_PREALLOC_PKTIDMAP
++	wlan_static_dhd_pktid_map = kmalloc(WLAN_DHD_PKTID_MAP_SIZE,
++		GFP_KERNEL);
++	if (!wlan_static_dhd_pktid_map) {
++		pr_err("Failed to alloc wlan_static_dhd_pktid_map\n");
++		goto err_mem_alloc;
++	}
++
++	wlan_static_dhd_pktid_ioctl_map = kmalloc(WLAN_DHD_PKTID_IOCTL_MAP_SIZE,
++		GFP_KERNEL);
++	if (!wlan_static_dhd_pktid_ioctl_map) {
++		pr_err("Failed to alloc wlan_static_dhd_pktid_ioctl_map\n");
++		goto err_mem_alloc;
++	}
++#endif /* CONFIG_BCMDHD_PREALLOC_PKTIDMAP */
++#else
++	wlan_static_dhd_wlfc_buf = kmalloc(WLAN_DHD_WLFC_BUF_SIZE,
++		GFP_KERNEL);
++	if (!wlan_static_dhd_wlfc_buf) {
++		pr_err("Failed to alloc wlan_static_dhd_wlfc_buf\n");
++		goto err_mem_alloc;
++	}
++
++	wlan_static_dhd_wlfc_hanger = kmalloc(WLAN_DHD_WLFC_HANGER_SIZE,
++		GFP_KERNEL);
++	if (!wlan_static_dhd_wlfc_hanger) {
++		pr_err("Failed to alloc wlan_static_dhd_wlfc_hanger\n");
++		goto err_mem_alloc;
++	}
++#endif /* CONFIG_BCMDHD_PCIE */
++
++#ifdef CONFIG_BCMDHD_PREALLOC_MEMDUMP
++	wlan_static_dhd_memdump_ram = kmalloc(WLAN_DHD_MEMDUMP_SIZE, GFP_KERNEL);
++	if (!wlan_static_dhd_memdump_ram) {
++		pr_err("Failed to alloc wlan_static_dhd_memdump_ram\n");
++		goto err_mem_alloc;
++	}
++#endif /* CONFIG_BCMDHD_PREALLOC_MEMDUMP */
++
++	wlan_static_dhd_pktlog_dump_buf = kmalloc(DHD_PKTLOG_DUMP_BUF_SIZE, GFP_KERNEL);
++	if (!wlan_static_dhd_pktlog_dump_buf) {
++		pr_err("Failed to alloc wlan_static_dhd_pktlog_dump_buf\n");
++		goto err_mem_alloc;
++	}
++
++	wlan_static_stat_report_buf = kmalloc(DHD_STAT_REPORT_BUF_SIZE, GFP_KERNEL);
++	if (!wlan_static_stat_report_buf) {
++		pr_err("Failed to alloc wlan_static_stat_report_buf\n");
++		goto err_mem_alloc;
++	}
++
++	pr_err("%s: WIFI MEM Allocated\n", __FUNCTION__);
++	return 0;
++
++err_mem_alloc:
++#ifdef CONFIG_BCMDHD_PREALLOC_MEMDUMP
++	if (wlan_static_dhd_memdump_ram) {
++		kfree(wlan_static_dhd_memdump_ram);
++	}
++
++#endif /* CONFIG_BCMDHD_PREALLOC_MEMDUMP */
++
++#ifdef CONFIG_BCMDHD_PCIE
++	if (wlan_static_if_flow_lkup) {
++		kfree(wlan_static_if_flow_lkup);
++	}
++
++#ifdef CONFIG_BCMDHD_PREALLOC_PKTIDMAP
++	if (wlan_static_dhd_pktid_map) {
++		kfree(wlan_static_dhd_pktid_map);
++	}
++
++	if (wlan_static_dhd_pktid_ioctl_map) {
++		kfree(wlan_static_dhd_pktid_ioctl_map);
++	}
++#endif /* CONFIG_BCMDHD_PREALLOC_PKTIDMAP */
++#else
++	if (wlan_static_dhd_wlfc_buf) {
++		kfree(wlan_static_dhd_wlfc_buf);
++	}
++
++	if (wlan_static_dhd_wlfc_hanger) {
++		kfree(wlan_static_dhd_wlfc_hanger);
++	}
++#endif /* CONFIG_BCMDHD_PCIE */
++	if (wlan_static_dhd_info_buf) {
++		kfree(wlan_static_dhd_info_buf);
++	}
++
++	if (wlan_static_dhd_log_dump_buf) {
++		kfree(wlan_static_dhd_log_dump_buf);
++	}
++
++	if (wlan_static_dhd_log_dump_buf_ex) {
++		kfree(wlan_static_dhd_log_dump_buf_ex);
++	}
++
++	if (wlan_static_scan_buf1) {
++		kfree(wlan_static_scan_buf1);
++	}
++
++	if (wlan_static_scan_buf0) {
++		kfree(wlan_static_scan_buf0);
++	}
++
++	if (wlan_static_dhd_pktlog_dump_buf) {
++		kfree(wlan_static_dhd_pktlog_dump_buf);
++	}
++
++	if (wlan_static_stat_report_buf) {
++		kfree(wlan_static_stat_report_buf);
++	}
++
++	pr_err("Failed to mem_alloc for WLAN\n");
++
++	for (j = 0; j < i; j++) {
++		kfree(wlan_mem_array[j].mem_ptr);
++	}
++
++	i = WLAN_SKB_BUF_NUM;
++
++err_skb_alloc:
++	pr_err("Failed to skb_alloc for WLAN\n");
++	for (j = 0; j < i; j++) {
++		dev_kfree_skb(wlan_static_skb[j]);
++	}
++
++	return -ENOMEM;
++}
++EXPORT_SYMBOL(dhd_init_wlan_mem);
++#endif /* CONFIG_BROADCOM_WIFI_RESERVED_MEM */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_custom_msm.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_custom_msm.c
+new file mode 100644
+index 000000000..27399d0d0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_custom_msm.c
+@@ -0,0 +1,253 @@
++/*
++ * Platform Dependent file for Qualcomm MSM/APQ
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_custom_msm.c 674523 2016-12-09 04:05:27Z $
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/gpio.h>
++#include <linux/skbuff.h>
++#include <linux/wlan_plat.h>
++#include <linux/mmc/host.h>
++#include <linux/msm_pcie.h>
++#include <linux/fcntl.h>
++#include <linux/fs.h>
++#include <linux/of_gpio.h>
++#if defined(CONFIG_ARCH_MSM8996) || defined(CONFIG_ARCH_MSM8998)
++#include <linux/msm_pcie.h>
++#endif /* CONFIG_ARCH_MSM8996 || CONFIG_ARCH_MSM8998 */
++
++#ifdef CONFIG_BROADCOM_WIFI_RESERVED_MEM
++extern int dhd_init_wlan_mem(void);
++extern void *dhd_wlan_mem_prealloc(int section, unsigned long size);
++#endif /* CONFIG_BROADCOM_WIFI_RESERVED_MEM */
++
++#define WIFI_TURNON_DELAY       200
++static int wlan_reg_on = -1;
++#define DHD_DT_COMPAT_ENTRY		"android,bcmdhd_wlan"
++#ifdef CUSTOMER_HW2
++#define WIFI_WL_REG_ON_PROPNAME		"wl_reg_on"
++#else
++#define WIFI_WL_REG_ON_PROPNAME		"wlan-en-gpio"
++#endif /* CUSTOMER_HW2 */
++
++#if defined(CONFIG_ARCH_MSM8996) || defined(CONFIG_ARCH_MSM8998)
++#define MSM_PCIE_CH_NUM			0
++#else
++#define MSM_PCIE_CH_NUM			1
++#endif /* CONFIG_ARCH_MSM8996 || CONFIG_ARCH_MSM8998 */
++
++#ifdef CONFIG_BCMDHD_OOB_HOST_WAKE
++static int wlan_host_wake_up = -1;
++static int wlan_host_wake_irq = 0;
++#ifdef CUSTOMER_HW2
++#define WIFI_WLAN_HOST_WAKE_PROPNAME    "wl_host_wake"
++#else
++#define WIFI_WLAN_HOST_WAKE_PROPNAME    "wlan-host-wake-gpio"
++#endif /* CUSTOMER_HW2 */
++#endif /* CONFIG_BCMDHD_OOB_HOST_WAKE */
++
++int __init
++dhd_wifi_init_gpio(void)
++{
++	char *wlan_node = DHD_DT_COMPAT_ENTRY;
++	struct device_node *root_node = NULL;
++
++	root_node = of_find_compatible_node(NULL, NULL, wlan_node);
++	if (!root_node) {
++		WARN(1, "failed to get device node of BRCM WLAN\n");
++		return -ENODEV;
++	}
++
++	/* ========== WLAN_PWR_EN ============ */
++	wlan_reg_on = of_get_named_gpio(root_node, WIFI_WL_REG_ON_PROPNAME, 0);
++	printk(KERN_INFO "%s: gpio_wlan_power : %d\n", __FUNCTION__, wlan_reg_on);
++
++	if (gpio_request_one(wlan_reg_on, GPIOF_OUT_INIT_LOW, "WL_REG_ON")) {
++		printk(KERN_ERR "%s: Faiiled to request gpio %d for WL_REG_ON\n",
++			__FUNCTION__, wlan_reg_on);
++	} else {
++		printk(KERN_ERR "%s: gpio_request WL_REG_ON done - WLAN_EN: GPIO %d\n",
++			__FUNCTION__, wlan_reg_on);
++	}
++
++	if (gpio_direction_output(wlan_reg_on, 1)) {
++		printk(KERN_ERR "%s: WL_REG_ON failed to pull up\n", __FUNCTION__);
++	} else {
++		printk(KERN_ERR "%s: WL_REG_ON is pulled up\n", __FUNCTION__);
++	}
++
++	if (gpio_get_value(wlan_reg_on)) {
++		printk(KERN_INFO "%s: Initial WL_REG_ON: [%d]\n",
++			__FUNCTION__, gpio_get_value(wlan_reg_on));
++	}
++
++	/* Wait for WIFI_TURNON_DELAY due to power stability */
++	msleep(WIFI_TURNON_DELAY);
++
++#ifdef CONFIG_BCMDHD_OOB_HOST_WAKE
++	/* ========== WLAN_HOST_WAKE ============ */
++	wlan_host_wake_up = of_get_named_gpio(root_node, WIFI_WLAN_HOST_WAKE_PROPNAME, 0);
++	printk(KERN_INFO "%s: gpio_wlan_host_wake : %d\n", __FUNCTION__, wlan_host_wake_up);
++
++#ifndef CUSTOMER_HW2
++	if (gpio_request_one(wlan_host_wake_up, GPIOF_IN, "WLAN_HOST_WAKE")) {
++		printk(KERN_ERR "%s: Failed to request gpio %d for WLAN_HOST_WAKE\n",
++			__FUNCTION__, wlan_host_wake_up);
++			return -ENODEV;
++	} else {
++		printk(KERN_ERR "%s: gpio_request WLAN_HOST_WAKE done"
++			" - WLAN_HOST_WAKE: GPIO %d\n",
++			__FUNCTION__, wlan_host_wake_up);
++	}
++#endif /* !CUSTOMER_HW2 */
++
++	gpio_direction_input(wlan_host_wake_up);
++	wlan_host_wake_irq = gpio_to_irq(wlan_host_wake_up);
++#endif /* CONFIG_BCMDHD_OOB_HOST_WAKE */
++
++#if defined(CONFIG_BCM4359) || defined(CONFIG_BCM4361)
++	printk(KERN_INFO "%s: Call msm_pcie_enumerate\n", __FUNCTION__);
++	msm_pcie_enumerate(MSM_PCIE_CH_NUM);
++#endif /* CONFIG_BCM4359 || CONFIG_BCM4361 */
++
++	return 0;
++}
++
++int
++dhd_wlan_power(int onoff)
++{
++	printk(KERN_INFO"------------------------------------------------");
++	printk(KERN_INFO"------------------------------------------------\n");
++	printk(KERN_INFO"%s Enter: power %s\n", __func__, onoff ? "on" : "off");
++
++	if (onoff) {
++		if (gpio_direction_output(wlan_reg_on, 1)) {
++			printk(KERN_ERR "%s: WL_REG_ON is failed to pull up\n", __FUNCTION__);
++			return -EIO;
++		}
++		if (gpio_get_value(wlan_reg_on)) {
++			printk(KERN_INFO"WL_REG_ON on-step-2 : [%d]\n",
++				gpio_get_value(wlan_reg_on));
++		} else {
++			printk("[%s] gpio value is 0. We need reinit.\n", __func__);
++			if (gpio_direction_output(wlan_reg_on, 1)) {
++				printk(KERN_ERR "%s: WL_REG_ON is "
++					"failed to pull up\n", __func__);
++			}
++		}
++	} else {
++		if (gpio_direction_output(wlan_reg_on, 0)) {
++			printk(KERN_ERR "%s: WL_REG_ON is failed to pull up\n", __FUNCTION__);
++			return -EIO;
++		}
++		if (gpio_get_value(wlan_reg_on)) {
++			printk(KERN_INFO"WL_REG_ON on-step-2 : [%d]\n",
++				gpio_get_value(wlan_reg_on));
++		}
++	}
++	return 0;
++}
++EXPORT_SYMBOL(dhd_wlan_power);
++
++static int
++dhd_wlan_reset(int onoff)
++{
++	return 0;
++}
++
++static int
++dhd_wlan_set_carddetect(int val)
++{
++	return 0;
++}
++
++struct resource dhd_wlan_resources = {
++	.name	= "bcmdhd_wlan_irq",
++	.start	= 0, /* Dummy */
++	.end	= 0, /* Dummy */
++	.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE |
++#ifdef CONFIG_BCMDHD_PCIE
++	IORESOURCE_IRQ_HIGHEDGE,
++#else
++	IORESOURCE_IRQ_HIGHLEVEL,
++#endif /* CONFIG_BCMDHD_PCIE */
++};
++EXPORT_SYMBOL(dhd_wlan_resources);
++
++struct wifi_platform_data dhd_wlan_control = {
++	.set_power	= dhd_wlan_power,
++	.set_reset	= dhd_wlan_reset,
++	.set_carddetect	= dhd_wlan_set_carddetect,
++#ifdef CONFIG_BROADCOM_WIFI_RESERVED_MEM
++	.mem_prealloc	= dhd_wlan_mem_prealloc,
++#endif /* CONFIG_BROADCOM_WIFI_RESERVED_MEM */
++};
++EXPORT_SYMBOL(dhd_wlan_control);
++
++int __init
++dhd_wlan_init(void)
++{
++	int ret;
++
++	printk(KERN_INFO"%s: START.......\n", __FUNCTION__);
++	ret = dhd_wifi_init_gpio();
++	if (ret < 0) {
++		printk(KERN_ERR "%s: failed to initiate GPIO, ret=%d\n",
++			__FUNCTION__, ret);
++		goto fail;
++	}
++
++#ifdef CONFIG_BCMDHD_OOB_HOST_WAKE
++	dhd_wlan_resources.start = wlan_host_wake_irq;
++	dhd_wlan_resources.end = wlan_host_wake_irq;
++#endif /* CONFIG_BCMDHD_OOB_HOST_WAKE */
++
++#ifdef CONFIG_BROADCOM_WIFI_RESERVED_MEM
++	ret = dhd_init_wlan_mem();
++	if (ret < 0) {
++		printk(KERN_ERR "%s: failed to alloc reserved memory,"
++			" ret=%d\n", __FUNCTION__, ret);
++	}
++#endif /* CONFIG_BROADCOM_WIFI_RESERVED_MEM */
++
++fail:
++	printk(KERN_INFO"%s: FINISH.......\n", __FUNCTION__);
++	return ret;
++}
++#if defined(CONFIG_ARCH_MSM8996) || defined(CONFIG_ARCH_MSM8998)
++#if defined(CONFIG_DEFERRED_INITCALLS)
++deferred_module_init(dhd_wlan_init);
++#else
++late_initcall(dhd_wlan_init);
++#endif /* CONFIG_DEFERRED_INITCALLS */
++#else
++device_initcall(dhd_wlan_init);
++#endif /* CONFIG_ARCH_MSM8996 || CONFIG_ARCH_MSM8998 */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_dbg.h b/module_drivers/drivers/net/wireless/bcmdhd/dhd_dbg.h
+new file mode 100644
+index 000000000..3f90c5229
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_dbg.h
+@@ -0,0 +1,347 @@
++/*
++ * Debug/trace/assert driver definitions for Dongle Host Driver.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_dbg.h 667145 2016-10-26 04:27:53Z $
++ */
++
++#ifndef _dhd_dbg_
++#define _dhd_dbg_
++
++
++#if defined(DHD_EFI) && defined(DHD_LOG_DUMP)
++extern void dhd_log_dump_print(const char *fmt, ...);
++extern void dhd_log_dump_print_drv(const char *fmt, ...);
++#endif
++
++#if defined(DHD_DEBUG)
++
++#ifdef DHD_LOG_DUMP
++extern void dhd_log_dump_write(int type, const char *fmt, ...);
++extern char *dhd_log_dump_get_timestamp(void);
++#ifndef _DHD_LOG_DUMP_DEFINITIONS_
++#define _DHD_LOG_DUMP_DEFINITIONS_
++#define DLD_BUF_TYPE_GENERAL    0
++#define DLD_BUF_TYPE_SPECIAL    1
++#define DHD_LOG_DUMP_WRITE(fmt, ...)	dhd_log_dump_write(DLD_BUF_TYPE_GENERAL, fmt, ##__VA_ARGS__)
++#define DHD_LOG_DUMP_WRITE_EX(fmt, ...)	dhd_log_dump_write(DLD_BUF_TYPE_SPECIAL, fmt, ##__VA_ARGS__)
++#endif /* !_DHD_LOG_DUMP_DEFINITIONS_ */
++
++#ifdef DHD_EFI
++#define DHD_ERROR(args)	\
++do {	\
++	if (dhd_msg_level & DHD_ERROR_VAL) {	\
++		printf args;	\
++		dhd_log_dump_print_drv("[%s] %s: ", dhd_log_dump_get_timestamp(), __FUNCTION__); \
++		dhd_log_dump_print_drv args; \
++	}	\
++} while (0)
++#define DHD_INFO(args) \
++do {	\
++	if (dhd_msg_level & DHD_INFO_VAL) {	\
++		printf args;	\
++		dhd_log_dump_print_drv("[%s] %s: ", dhd_log_dump_get_timestamp(), __FUNCTION__); \
++		dhd_log_dump_print_drv args; \
++	}	\
++} while (0)
++#else /* DHD_EFI */
++#define DHD_ERROR(args)	\
++do {	\
++	if (dhd_msg_level & DHD_ERROR_VAL) {	\
++		printf args;	\
++		DHD_LOG_DUMP_WRITE("[%s] %s: ", dhd_log_dump_get_timestamp(), __func__);	\
++		DHD_LOG_DUMP_WRITE args;	\
++	}	\
++} while (0)
++#define DHD_INFO(args)		do {if (dhd_msg_level & DHD_INFO_VAL) printf args;} while (0)
++#endif /* DHD_EFI */
++#else /* DHD_LOG_DUMP */
++#define DHD_ERROR(args)		do {if (dhd_msg_level & DHD_ERROR_VAL) printf args;} while (0)
++#define DHD_INFO(args)		do {if (dhd_msg_level & DHD_INFO_VAL) printf args;} while (0)
++#endif /* DHD_LOG_DUMP */
++#define DHD_TRACE(args)		do {if (dhd_msg_level & DHD_TRACE_VAL) printf args;} while (0)
++
++#define DHD_DATA(args)		do {if (dhd_msg_level & DHD_DATA_VAL) printf args;} while (0)
++#define DHD_CTL(args)		do {if (dhd_msg_level & DHD_CTL_VAL) printf args;} while (0)
++#define DHD_TIMER(args)		do {if (dhd_msg_level & DHD_TIMER_VAL) printf args;} while (0)
++#define DHD_HDRS(args)		do {if (dhd_msg_level & DHD_HDRS_VAL) printf args;} while (0)
++#define DHD_BYTES(args)		do {if (dhd_msg_level & DHD_BYTES_VAL) printf args;} while (0)
++#define DHD_INTR(args)		do {if (dhd_msg_level & DHD_INTR_VAL) printf args;} while (0)
++#define DHD_GLOM(args)		do {if (dhd_msg_level & DHD_GLOM_VAL) printf args;} while (0)
++#ifdef DHD_LOG_DUMP
++#ifndef DHD_EFI
++#define DHD_EVENT(args) \
++do {	\
++	if (dhd_msg_level & DHD_EVENT_VAL) {	\
++		printf args;	\
++		DHD_LOG_DUMP_WRITE("[%s] %s: ", dhd_log_dump_get_timestamp(), __func__);	\
++		DHD_LOG_DUMP_WRITE args;	\
++	}	\
++} while (0)
++#else
++#define DHD_EVENT(args) \
++do {	\
++	if (dhd_msg_level & DHD_EVENT_VAL) {	\
++		dhd_log_dump_print("[%s] %s: ", dhd_log_dump_get_timestamp(), __FUNCTION__);	\
++		dhd_log_dump_print args;	\
++	}	\
++} while (0)
++#endif /* !DHD_EFI */
++#else
++#define DHD_EVENT(args)		do {if (dhd_msg_level & DHD_EVENT_VAL) printf args;} while (0)
++#endif /* DHD_LOG_DUMP */
++#define DHD_ISCAN(args)		do {if (dhd_msg_level & DHD_ISCAN_VAL) printf args;} while (0)
++#define DHD_ARPOE(args)		do {if (dhd_msg_level & DHD_ARPOE_VAL) printf args;} while (0)
++#define DHD_REORDER(args)	do {if (dhd_msg_level & DHD_REORDER_VAL) printf args;} while (0)
++#define DHD_PNO(args)		do {if (dhd_msg_level & DHD_PNO_VAL) printf args;} while (0)
++#define DHD_RTT(args)		do {if (dhd_msg_level & DHD_RTT_VAL) printf args;} while (0)
++#define DHD_PKT_MON(args)	do {if (dhd_msg_level & DHD_PKT_MON_VAL) printf args;} while (0)
++#ifdef DHD_LOG_DUMP
++#ifndef DHD_EFI
++#define DHD_MSGTRACE_LOG(args)	\
++do {	\
++	if (dhd_msg_level & DHD_MSGTRACE_VAL) {	\
++		printf args;	\
++		DHD_LOG_DUMP_WRITE("[%s] %s: ", dhd_log_dump_get_timestamp(), __func__);	\
++		DHD_LOG_DUMP_WRITE args;	\
++	}   \
++} while (0)
++#else
++#define DHD_MSGTRACE_LOG(args)	\
++do {	\
++	if (dhd_msg_level & DHD_MSGTRACE_VAL) {	\
++		dhd_log_dump_print("[%s] %s: ", dhd_log_dump_get_timestamp(), __FUNCTION__);	\
++		dhd_log_dump_print args;	\
++	}   \
++} while (0)
++#endif /* !DHD_EFI	*/
++#else
++#define DHD_MSGTRACE_LOG(args)  do {if (dhd_msg_level & DHD_MSGTRACE_VAL) printf args;} while (0)
++#endif /* DHD_LOG_DUMP */
++
++#if defined(DHD_LOG_DUMP) && defined(DHD_EFI)
++#define DHD_FWLOG(args) DHD_MSGTRACE_LOG(args)
++#else
++
++#define DHD_FWLOG(args)		do {if (dhd_msg_level & DHD_FWLOG_VAL) printf args;} while (0)
++#endif /* DHD_LOG_DUMP & DHD_EFI */
++#define DHD_DBGIF(args)		do {if (dhd_msg_level & DHD_DBGIF_VAL) printf args;} while (0)
++
++#ifdef DHD_LOG_DUMP
++#ifdef DHD_EFI
++#define DHD_ERROR_MEM(args)					\
++do {                                        \
++	if (dhd_msg_level & DHD_ERROR_VAL) {    \
++		dhd_log_dump_print_drv("[%s] %s: ", dhd_log_dump_get_timestamp(), __FUNCTION__); \
++		dhd_log_dump_print_drv args;	\
++	}	\
++} while (0)
++#define DHD_ERROR_EX(args)	DHD_ERROR(args)
++#else
++#define DHD_ERROR_MEM(args)					\
++do {                                        \
++	if (dhd_msg_level & DHD_ERROR_VAL) {    \
++			if (dhd_msg_level & DHD_ERROR_MEM_VAL) {	\
++				printf args;	\
++			}	\
++		DHD_LOG_DUMP_WRITE("[%s] %s: ", dhd_log_dump_get_timestamp(), __FUNCTION__);	\
++		DHD_LOG_DUMP_WRITE args;	\
++	}	\
++} while (0)
++#define DHD_ERROR_EX(args)					\
++do {                                        \
++	if (dhd_msg_level & DHD_ERROR_VAL) {    \
++		printf args;	\
++		DHD_LOG_DUMP_WRITE_EX("[%s] %s: ", dhd_log_dump_get_timestamp(), __FUNCTION__);	\
++		DHD_LOG_DUMP_WRITE_EX args;	\
++	}	\
++} while (0)
++#endif /* DHD_EFI */
++#else
++#define DHD_ERROR_MEM(args)	DHD_ERROR(args)
++#define DHD_ERROR_EX(args)	DHD_ERROR(args)
++#endif /* DHD_LOG_DUMP */
++
++#ifdef CUSTOMER_HW4_DEBUG
++#define DHD_TRACE_HW4	DHD_ERROR
++#define DHD_INFO_HW4	DHD_ERROR
++#else
++#define DHD_TRACE_HW4	DHD_TRACE
++#define DHD_INFO_HW4	DHD_INFO
++#endif /* CUSTOMER_HW4_DEBUG */
++
++#define DHD_ERROR_ON()		(dhd_msg_level & DHD_ERROR_VAL)
++#define DHD_TRACE_ON()		(dhd_msg_level & DHD_TRACE_VAL)
++#define DHD_INFO_ON()		(dhd_msg_level & DHD_INFO_VAL)
++#define DHD_DATA_ON()		(dhd_msg_level & DHD_DATA_VAL)
++#define DHD_CTL_ON()		(dhd_msg_level & DHD_CTL_VAL)
++#define DHD_TIMER_ON()		(dhd_msg_level & DHD_TIMER_VAL)
++#define DHD_HDRS_ON()		(dhd_msg_level & DHD_HDRS_VAL)
++#define DHD_BYTES_ON()		(dhd_msg_level & DHD_BYTES_VAL)
++#define DHD_INTR_ON()		(dhd_msg_level & DHD_INTR_VAL)
++#define DHD_GLOM_ON()		(dhd_msg_level & DHD_GLOM_VAL)
++#define DHD_EVENT_ON()		(dhd_msg_level & DHD_EVENT_VAL)
++#define DHD_ISCAN_ON()		(dhd_msg_level & DHD_ISCAN_VAL)
++#define DHD_ARPOE_ON()		(dhd_msg_level & DHD_ARPOE_VAL)
++#define DHD_REORDER_ON()	(dhd_msg_level & DHD_REORDER_VAL)
++#define DHD_NOCHECKDIED_ON()	(dhd_msg_level & DHD_NOCHECKDIED_VAL)
++#define DHD_PNO_ON()		(dhd_msg_level & DHD_PNO_VAL)
++#define DHD_RTT_ON()		(dhd_msg_level & DHD_RTT_VAL)
++#define DHD_MSGTRACE_ON()	(dhd_msg_level & DHD_MSGTRACE_VAL)
++#define DHD_FWLOG_ON()		(dhd_msg_level & DHD_FWLOG_VAL)
++#define DHD_DBGIF_ON()		(dhd_msg_level & DHD_DBGIF_VAL)
++#define DHD_PKT_MON_ON()	(dhd_msg_level & DHD_PKT_MON_VAL)
++#define DHD_PKT_MON_DUMP_ON()	(dhd_msg_level & DHD_PKT_MON_DUMP_VAL)
++
++#else /* defined(BCMDBG) || defined(DHD_DEBUG) */
++
++#if defined(DHD_EFI)
++extern void dhd_log_dump_print_drv(const char *fmt, ...);
++extern char *dhd_log_dump_get_timestamp(void);
++#define DHD_ERROR(args)	\
++do {	\
++	if (dhd_msg_level & DHD_ERROR_VAL) {	\
++		printf args;	\
++		dhd_log_dump_print_drv("[%s] %s: ", dhd_log_dump_get_timestamp(), __FUNCTION__); \
++		dhd_log_dump_print_drv args; \
++	}	\
++} while (0)
++#define DHD_INFO(args) \
++do {	\
++	if (dhd_msg_level & DHD_INFO_VAL) {	\
++		printf args;	\
++		dhd_log_dump_print_drv("[%s] %s: ", dhd_log_dump_get_timestamp(), __FUNCTION__); \
++		dhd_log_dump_print_drv args; \
++	}	\
++} while (0)
++#define DHD_TRACE(args)
++#else /* DHD_EFI */
++
++#define DHD_ERROR(args)		do {if (dhd_msg_level & DHD_ERROR_VAL) \
++								printf args;} while (0)
++#define DHD_TRACE(args)
++#define DHD_INFO(args)
++#endif 
++
++#define DHD_DATA(args)
++#define DHD_CTL(args)
++#define DHD_TIMER(args)
++#define DHD_HDRS(args)
++#define DHD_BYTES(args)
++#define DHD_INTR(args)
++#define DHD_GLOM(args)
++
++#if defined(DHD_EFI) && defined(DHD_LOG_DUMP)
++#define DHD_EVENT(args) \
++do {	\
++	if (dhd_msg_level & DHD_EVENT_VAL) {	\
++		dhd_log_dump_print("[%s] %s: ", dhd_log_dump_get_timestamp(), __FUNCTION__);	\
++		dhd_log_dump_print args;	\
++	}	\
++} while (0)
++#else
++#define DHD_EVENT(args)
++#endif /* DHD_EFI && DHD_LOG_DUMP */
++
++#define DHD_ISCAN(args)
++#define DHD_ARPOE(args)
++#define DHD_REORDER(args)
++#define DHD_PNO(args)
++#define DHD_RTT(args)
++#define DHD_PKT_MON(args)
++
++#if defined(DHD_EFI) && defined(DHD_LOG_DUMP)
++#define DHD_MSGTRACE_LOG(args)	\
++do {	\
++	if (dhd_msg_level & DHD_MSGTRACE_VAL) {	\
++		dhd_log_dump_print("[%s] %s: ", dhd_log_dump_get_timestamp(), __FUNCTION__);	\
++		dhd_log_dump_print args;	\
++	}   \
++} while (0)
++#define DHD_FWLOG(args) DHD_MSGTRACE_LOG(args)
++#else
++#define DHD_MSGTRACE_LOG(args)
++#define DHD_FWLOG(args)
++#endif /* DHD_EFI && DHD_LOG_DUMP */
++
++#define DHD_DBGIF(args)
++
++#if defined(DHD_EFI) && defined(DHD_LOG_DUMP)
++#define DHD_ERROR_MEM(args)                  \
++do {                                        \
++	if (dhd_msg_level & DHD_ERROR_VAL) {    \
++		dhd_log_dump_print("[%s] %s: ", dhd_log_dump_get_timestamp(), __FUNCTION__);	\
++		dhd_log_dump_print args;	\
++	}	\
++} while (0)
++#define DHD_ERROR_EX(args)	DHD_ERROR(args)
++#else
++#define DHD_ERROR_MEM(args) DHD_ERROR(args)
++#define DHD_ERROR_EX(args)	DHD_ERROR(args)
++#endif /* DHD_EFI && DHD_LOG_DUMP */
++
++#ifdef CUSTOMER_HW4_DEBUG
++#define DHD_TRACE_HW4	DHD_ERROR
++#define DHD_INFO_HW4	DHD_ERROR
++#else
++#define DHD_TRACE_HW4	DHD_TRACE
++#define DHD_INFO_HW4	DHD_INFO
++#endif /* CUSTOMER_HW4_DEBUG */
++
++#define DHD_ERROR_ON()		0
++#define DHD_TRACE_ON()		0
++#define DHD_INFO_ON()		0
++#define DHD_DATA_ON()		0
++#define DHD_CTL_ON()		0
++#define DHD_TIMER_ON()		0
++#define DHD_HDRS_ON()		0
++#define DHD_BYTES_ON()		0
++#define DHD_INTR_ON()		0
++#define DHD_GLOM_ON()		0
++#define DHD_EVENT_ON()		0
++#define DHD_ISCAN_ON()		0
++#define DHD_ARPOE_ON()		0
++#define DHD_REORDER_ON()	0
++#define DHD_NOCHECKDIED_ON()	0
++#define DHD_PNO_ON()		0
++#define DHD_RTT_ON()		0
++#define DHD_PKT_MON_ON()	0
++#define DHD_PKT_MON_DUMP_ON()	0
++#define DHD_MSGTRACE_ON()	0
++#define DHD_FWLOG_ON()		0
++#define DHD_DBGIF_ON()		0
++#endif 
++
++#define DHD_LOG(args)
++
++#define DHD_BLOG(cp, size)
++
++#define DHD_NONE(args)
++extern int dhd_msg_level;
++
++/* Defines msg bits */
++#include <dhdioctl.h>
++
++#endif /* _dhd_dbg_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_debug.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_debug.c
+new file mode 100644
+index 000000000..66e96a43c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_debug.c
+@@ -0,0 +1,2335 @@
++/*
++ * DHD debugability support
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * $Id: dhd_debug.c 711908 2017-07-20 10:37:34Z $
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_dbg.h>
++#include <dhd_debug.h>
++#include <dhd_mschdbg.h>
++
++#include <event_log.h>
++#include <event_trace.h>
++#include <msgtrace.h>
++
++#if defined(DHD_EFI)
++#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
++#define container_of(ptr, type, member) \
++		((type *)((char *)(ptr) - offsetof(type, member)))
++#endif 
++
++#define DBGRING_FLUSH_THRESHOLD(ring)		(ring->ring_size / 3)
++#define RING_STAT_TO_STATUS(ring, status) \
++	do {               \
++		strncpy(status.name, ring->name, \
++			sizeof(status.name) - 1);  \
++		status.ring_id = ring->id;     \
++		status.ring_buffer_byte_size = ring->ring_size;  \
++		status.written_bytes = ring->stat.written_bytes; \
++		status.written_records = ring->stat.written_records; \
++		status.read_bytes = ring->stat.read_bytes; \
++		status.verbose_level = ring->log_level; \
++	} while (0)
++
++#define DHD_PKT_INFO DHD_ERROR
++struct map_table {
++	uint16 fw_id;
++	uint16 host_id;
++	char *desc;
++};
++
++struct map_table event_map[] = {
++	{WLC_E_AUTH, WIFI_EVENT_AUTH_COMPLETE, "AUTH_COMPLETE"},
++	{WLC_E_ASSOC, WIFI_EVENT_ASSOC_COMPLETE, "ASSOC_COMPLETE"},
++	{TRACE_FW_AUTH_STARTED, WIFI_EVENT_FW_AUTH_STARTED, "AUTH STARTED"},
++	{TRACE_FW_ASSOC_STARTED, WIFI_EVENT_FW_ASSOC_STARTED, "ASSOC STARTED"},
++	{TRACE_FW_RE_ASSOC_STARTED, WIFI_EVENT_FW_RE_ASSOC_STARTED, "REASSOC STARTED"},
++	{TRACE_G_SCAN_STARTED, WIFI_EVENT_G_SCAN_STARTED, "GSCAN STARTED"},
++	{WLC_E_PFN_SCAN_COMPLETE, WIFI_EVENT_G_SCAN_COMPLETE, "GSCAN COMPLETE"},
++	{WLC_E_DISASSOC, WIFI_EVENT_DISASSOCIATION_REQUESTED, "DIASSOC REQUESTED"},
++	{WLC_E_REASSOC, WIFI_EVENT_RE_ASSOCIATION_REQUESTED, "REASSOC REQUESTED"},
++	{TRACE_ROAM_SCAN_STARTED, WIFI_EVENT_ROAM_REQUESTED, "ROAM REQUESTED"},
++	{WLC_E_BEACON_FRAME_RX, WIFI_EVENT_BEACON_RECEIVED, "BEACON Received"},
++	{TRACE_ROAM_SCAN_STARTED, WIFI_EVENT_ROAM_SCAN_STARTED, "ROAM SCAN STARTED"},
++	{TRACE_ROAM_SCAN_COMPLETE, WIFI_EVENT_ROAM_SCAN_COMPLETE, "ROAM SCAN COMPLETED"},
++	{TRACE_ROAM_AUTH_STARTED, WIFI_EVENT_ROAM_AUTH_STARTED, "ROAM AUTH STARTED"},
++	{WLC_E_AUTH, WIFI_EVENT_ROAM_AUTH_COMPLETE, "ROAM AUTH COMPLETED"},
++	{TRACE_FW_RE_ASSOC_STARTED, WIFI_EVENT_ROAM_ASSOC_STARTED, "ROAM ASSOC STARTED"},
++	{WLC_E_ASSOC, WIFI_EVENT_ROAM_ASSOC_COMPLETE, "ROAM ASSOC COMPLETED"},
++	{TRACE_ROAM_SCAN_COMPLETE, WIFI_EVENT_ROAM_SCAN_COMPLETE, "ROAM SCAN COMPLETED"},
++	{TRACE_BT_COEX_BT_SCO_START, WIFI_EVENT_BT_COEX_BT_SCO_START, "BT SCO START"},
++	{TRACE_BT_COEX_BT_SCO_STOP, WIFI_EVENT_BT_COEX_BT_SCO_STOP, "BT SCO STOP"},
++	{TRACE_BT_COEX_BT_SCAN_START, WIFI_EVENT_BT_COEX_BT_SCAN_START, "BT COEX SCAN START"},
++	{TRACE_BT_COEX_BT_SCAN_STOP, WIFI_EVENT_BT_COEX_BT_SCAN_STOP, "BT COEX SCAN STOP"},
++	{TRACE_BT_COEX_BT_HID_START, WIFI_EVENT_BT_COEX_BT_HID_START, "BT HID START"},
++	{TRACE_BT_COEX_BT_HID_STOP, WIFI_EVENT_BT_COEX_BT_HID_STOP, "BT HID STOP"},
++	{WLC_E_EAPOL_MSG, WIFI_EVENT_FW_EAPOL_FRAME_RECEIVED, "FW EAPOL PKT RECEIVED"},
++	{TRACE_FW_EAPOL_FRAME_TRANSMIT_START, WIFI_EVENT_FW_EAPOL_FRAME_TRANSMIT_START,
++	"FW EAPOL PKT TRANSMITED"},
++	{TRACE_FW_EAPOL_FRAME_TRANSMIT_STOP, WIFI_EVENT_FW_EAPOL_FRAME_TRANSMIT_STOP,
++	"FW EAPOL PKT TX STOPPED"},
++	{TRACE_BLOCK_ACK_NEGOTIATION_COMPLETE, WIFI_EVENT_BLOCK_ACK_NEGOTIATION_COMPLETE,
++	"BLOCK ACK NEGO COMPLETED"},
++};
++
++struct map_table event_tag_map[] = {
++	{TRACE_TAG_VENDOR_SPECIFIC, WIFI_TAG_VENDOR_SPECIFIC, "VENDOR SPECIFIC DATA"},
++	{TRACE_TAG_BSSID, WIFI_TAG_BSSID, "BSSID"},
++	{TRACE_TAG_ADDR, WIFI_TAG_ADDR, "ADDR_0"},
++	{TRACE_TAG_SSID, WIFI_TAG_SSID, "SSID"},
++	{TRACE_TAG_STATUS, WIFI_TAG_STATUS, "STATUS"},
++	{TRACE_TAG_CHANNEL_SPEC, WIFI_TAG_CHANNEL_SPEC, "CHANSPEC"},
++	{TRACE_TAG_WAKE_LOCK_EVENT, WIFI_TAG_WAKE_LOCK_EVENT, "WAKELOCK EVENT"},
++	{TRACE_TAG_ADDR1, WIFI_TAG_ADDR1, "ADDR_1"},
++	{TRACE_TAG_ADDR2, WIFI_TAG_ADDR2, "ADDR_2"},
++	{TRACE_TAG_ADDR3, WIFI_TAG_ADDR3, "ADDR_3"},
++	{TRACE_TAG_ADDR4, WIFI_TAG_ADDR4, "ADDR_4"},
++	{TRACE_TAG_TSF, WIFI_TAG_TSF, "TSF"},
++	{TRACE_TAG_IE, WIFI_TAG_IE, "802.11 IE"},
++	{TRACE_TAG_INTERFACE, WIFI_TAG_INTERFACE, "INTERFACE"},
++	{TRACE_TAG_REASON_CODE, WIFI_TAG_REASON_CODE, "REASON CODE"},
++	{TRACE_TAG_RATE_MBPS, WIFI_TAG_RATE_MBPS, "RATE"},
++};
++
++/* define log level per ring type */
++struct log_level_table fw_verbose_level_map[] = {
++	{1, EVENT_LOG_TAG_PCI_ERROR, EVENT_LOG_SET_BUS, "PCI_ERROR"},
++	{1, EVENT_LOG_TAG_PCI_WARN, EVENT_LOG_SET_BUS, "PCI_WARN"},
++	{2, EVENT_LOG_TAG_PCI_INFO, EVENT_LOG_SET_BUS, "PCI_INFO"},
++	{3, EVENT_LOG_TAG_PCI_DBG, EVENT_LOG_SET_BUS, "PCI_DEBUG"},
++	{3, EVENT_LOG_TAG_BEACON_LOG, EVENT_LOG_SET_WL, "BEACON_LOG"},
++	{2, EVENT_LOG_TAG_WL_ASSOC_LOG, EVENT_LOG_SET_WL, "ASSOC_LOG"},
++	{2, EVENT_LOG_TAG_WL_ROAM_LOG, EVENT_LOG_SET_WL, "ROAM_LOG"},
++	{1, EVENT_LOG_TAG_TRACE_WL_INFO, EVENT_LOG_SET_WL, "WL_INFO"},
++	{1, EVENT_LOG_TAG_TRACE_BTCOEX_INFO, EVENT_LOG_SET_WL, "BTCOEX_INFO"},
++#ifdef CUSTOMER_HW4_DEBUG
++	{3, EVENT_LOG_TAG_SCAN_WARN, EVENT_LOG_SET_WL, "SCAN_WARN"},
++#else
++	{1, EVENT_LOG_TAG_SCAN_WARN, EVENT_LOG_SET_WL, "SCAN_WARN"},
++#endif /* CUSTOMER_HW4_DEBUG */
++	{1, EVENT_LOG_TAG_SCAN_ERROR, EVENT_LOG_SET_WL, "SCAN_ERROR"},
++	{2, EVENT_LOG_TAG_SCAN_TRACE_LOW, EVENT_LOG_SET_WL, "SCAN_TRACE_LOW"},
++	{2, EVENT_LOG_TAG_SCAN_TRACE_HIGH, EVENT_LOG_SET_WL, "SCAN_TRACE_HIGH"}
++};
++
++struct log_level_table fw_event_level_map[] = {
++	{1, EVENT_LOG_TAG_TRACE_WL_INFO, EVENT_LOG_SET_WL, "WL_INFO"},
++	{1, EVENT_LOG_TAG_TRACE_BTCOEX_INFO, EVENT_LOG_SET_WL, "BTCOEX_INFO"},
++#ifdef CUSTOMER_HW4_DEBUG
++	{3, EVENT_LOG_TAG_BEACON_LOG, EVENT_LOG_SET_WL, "BEACON LOG"},
++#else
++	{2, EVENT_LOG_TAG_BEACON_LOG, EVENT_LOG_SET_WL, "BEACON LOG"},
++#endif /* CUSTOMER_HW4_DEBUG */
++};
++
++struct map_table nan_event_map[] = {
++	{TRACE_NAN_CLUSTER_STARTED, NAN_EVENT_CLUSTER_STARTED, "NAN_CLUSTER_STARTED"},
++	{TRACE_NAN_CLUSTER_JOINED, NAN_EVENT_CLUSTER_JOINED, "NAN_CLUSTER_JOINED"},
++	{TRACE_NAN_CLUSTER_MERGED, NAN_EVENT_CLUSTER_MERGED, "NAN_CLUSTER_MERGED"},
++	{TRACE_NAN_ROLE_CHANGED, NAN_EVENT_ROLE_CHANGED, "NAN_ROLE_CHANGED"},
++	{TRACE_NAN_SCAN_COMPLETE, NAN_EVENT_SCAN_COMPLETE, "NAN_SCAN_COMPLETE"},
++	{TRACE_NAN_STATUS_CHNG, NAN_EVENT_STATUS_CHNG, "NAN_STATUS_CHNG"},
++};
++
++struct log_level_table nan_event_level_map[] = {
++	{1, EVENT_LOG_TAG_NAN_ERROR, 0, "NAN_ERROR"},
++	{2, EVENT_LOG_TAG_NAN_INFO, 0, "NAN_INFO"},
++	{3, EVENT_LOG_TAG_NAN_DBG, 0, "NAN_DEBUG"},
++};
++
++struct map_table nan_evt_tag_map[] = {
++	{TRACE_TAG_BSSID, WIFI_TAG_BSSID, "BSSID"},
++	{TRACE_TAG_ADDR, WIFI_TAG_ADDR, "ADDR_0"},
++};
++
++/* reference tab table */
++uint ref_tag_tbl[EVENT_LOG_TAG_MAX + 1] = {0};
++
++typedef struct dhddbg_loglist_item {
++	dll_t list;
++	event_log_hdr_t *hdr;
++} loglist_item_t;
++
++typedef struct dhbdbg_pending_item {
++	dll_t list;
++	dhd_dbg_ring_status_t ring_status;
++	dhd_dbg_ring_entry_t *ring_entry;
++} pending_item_t;
++
++/* trace log entry header user space processing */
++struct tracelog_header {
++	int magic_num;
++	int buf_size;
++	int seq_num;
++};
++#define TRACE_LOG_MAGIC_NUMBER 0xEAE47C06
++
++int
++dhd_dbg_ring_pull_single(dhd_pub_t *dhdp, int ring_id, void *data, uint32 buf_len,
++	bool strip_header)
++{
++	dhd_dbg_ring_t *ring;
++	dhd_dbg_ring_entry_t *r_entry;
++	uint32 rlen;
++	char *buf;
++
++	if (!dhdp || !dhdp->dbg) {
++		return 0;
++	}
++
++	ring = &dhdp->dbg->dbg_rings[ring_id];
++
++	if (ring->state != RING_ACTIVE) {
++		return 0;
++	}
++
++	if (ring->rp == ring->wp) {
++		return 0;
++	}
++
++	r_entry = (dhd_dbg_ring_entry_t *)((uint8 *)ring->ring_buf + ring->rp);
++
++	/* Boundary Check */
++	rlen = ENTRY_LENGTH(r_entry);
++	if ((ring->rp + rlen) > ring->ring_size) {
++		DHD_ERROR(("%s: entry len %d is out of boundary of ring size %d,"
++			" current ring %d[%s] - rp=%d\n", __FUNCTION__, rlen,
++			ring->ring_size, ring->id, ring->name, ring->rp));
++		return 0;
++	}
++
++	if (strip_header) {
++		rlen = r_entry->len;
++		buf = (char *)r_entry + DBG_RING_ENTRY_SIZE;
++	} else {
++		rlen = ENTRY_LENGTH(r_entry);
++		buf = (char *)r_entry;
++	}
++	if (rlen > buf_len) {
++		DHD_ERROR(("%s: buf len %d is too small for entry len %d\n",
++			__FUNCTION__, buf_len, rlen));
++		DHD_ERROR(("%s: ring %d[%s] - ring size=%d, wp=%d, rp=%d\n",
++			__FUNCTION__, ring->id, ring->name, ring->ring_size,
++			ring->wp, ring->rp));
++		ASSERT(0);
++		return 0;
++	}
++
++	memcpy(data, buf, rlen);
++	/* update ring context */
++	ring->rp += ENTRY_LENGTH(r_entry);
++	/* skip padding if there is one */
++	if (ring->tail_padded && ((ring->rp + ring->rem_len) == ring->ring_size)) {
++		DHD_DBGIF(("%s: RING%d[%s] Found padding, rp=%d, wp=%d\n",
++			__FUNCTION__, ring->id, ring->name, ring->rp, ring->wp));
++		ring->rp = 0;
++		ring->tail_padded = FALSE;
++		ring->rem_len = 0;
++	}
++	if (ring->rp >= ring->ring_size) {
++		DHD_ERROR(("%s: RING%d[%s] rp pointed out of ring boundary,"
++			" rp=%d, ring_size=%d\n", __FUNCTION__, ring->id,
++			ring->name, ring->rp, ring->ring_size));
++		ASSERT(0);
++	}
++	ring->stat.read_bytes += ENTRY_LENGTH(r_entry);
++	DHD_DBGIF(("%s RING%d[%s]read_bytes %d, wp=%d, rp=%d\n", __FUNCTION__,
++		ring->id, ring->name, ring->stat.read_bytes, ring->wp, ring->rp));
++
++	return rlen;
++}
++
++int
++dhd_dbg_ring_pull(dhd_pub_t *dhdp, int ring_id, void *data, uint32 buf_len)
++{
++	int32 r_len, total_r_len = 0;
++	dhd_dbg_ring_t *ring;
++
++	if (!dhdp || !dhdp->dbg)
++		return 0;
++	ring = &dhdp->dbg->dbg_rings[ring_id];
++	if (ring->state != RING_ACTIVE)
++		return 0;
++
++	while (buf_len > 0) {
++		r_len = dhd_dbg_ring_pull_single(dhdp, ring_id, data, buf_len, FALSE);
++		if (r_len == 0)
++			break;
++		data = (uint8 *)data + r_len;
++		buf_len -= r_len;
++		total_r_len += r_len;
++	}
++
++	return total_r_len;
++}
++
++int
++dhd_dbg_ring_push(dhd_pub_t *dhdp, int ring_id, dhd_dbg_ring_entry_t *hdr, void *data)
++{
++	unsigned long flags;
++	uint32 pending_len;
++	uint32 w_len;
++	uint32 avail_size;
++	dhd_dbg_ring_t *ring;
++	dhd_dbg_ring_entry_t *w_entry, *r_entry;
++
++	if (!dhdp || !dhdp->dbg) {
++		return BCME_BADADDR;
++	}
++
++	ring = &dhdp->dbg->dbg_rings[ring_id];
++
++	if (ring->state != RING_ACTIVE) {
++		return BCME_OK;
++	}
++
++	flags = dhd_os_spin_lock(ring->lock);
++
++	w_len = ENTRY_LENGTH(hdr);
++
++	if (w_len > ring->ring_size) {
++		dhd_os_spin_unlock(ring->lock, flags);
++		return BCME_ERROR;
++	}
++
++	/* Claim the space */
++	do {
++		avail_size = DBG_RING_CHECK_WRITE_SPACE(ring->rp, ring->wp, ring->ring_size);
++		if (avail_size <= w_len) {
++			/* Prepare the space */
++			if (ring->rp <= ring->wp) {
++				ring->tail_padded = TRUE;
++				ring->rem_len = ring->ring_size - ring->wp;
++				DHD_DBGIF(("%s: RING%d[%s] Insuffient tail space,"
++					" rp=%d, wp=%d, rem_len=%d, ring_size=%d,"
++					" avail_size=%d, w_len=%d\n", __FUNCTION__,
++					ring->id, ring->name, ring->rp, ring->wp,
++					ring->rem_len, ring->ring_size, avail_size,
++					w_len));
++
++				/* 0 pad insufficient tail space */
++				memset((uint8 *)ring->ring_buf + ring->wp, 0, ring->rem_len);
++				if (ring->rp == ring->wp) {
++					ring->rp = 0;
++				}
++				ring->wp = 0;
++			} else {
++				/* Not enough space for new entry, free some up */
++				r_entry = (dhd_dbg_ring_entry_t *)((uint8 *)ring->ring_buf +
++					ring->rp);
++				ring->rp += ENTRY_LENGTH(r_entry);
++				/* skip padding if there is one */
++				if (ring->tail_padded &&
++					((ring->rp + ring->rem_len) == ring->ring_size)) {
++					DHD_DBGIF(("%s: RING%d[%s] Found padding,"
++						" avail_size=%d, w_len=%d\n", __FUNCTION__,
++						ring->id, ring->name, avail_size, w_len));
++					ring->rp = 0;
++					ring->tail_padded = FALSE;
++					ring->rem_len = 0;
++				}
++				if (ring->rp >= ring->ring_size) {
++					DHD_ERROR(("%s: RING%d[%s] rp points out of boundary,"
++						" ring->rp = %d, ring->ring_size=%d\n",
++						__FUNCTION__, ring->id, ring->name, ring->rp,
++						ring->ring_size));
++					ASSERT(0);
++				}
++				ring->stat.read_bytes += ENTRY_LENGTH(r_entry);
++				DHD_DBGIF(("%s: RING%d[%s] read_bytes  %d, wp=%d, rp=%d\n",
++					__FUNCTION__, ring->id, ring->name, ring->stat.read_bytes,
++					ring->wp, ring->rp));
++			}
++		} else {
++			break;
++		}
++	} while (TRUE);
++
++	w_entry = (dhd_dbg_ring_entry_t *)((uint8 *)ring->ring_buf + ring->wp);
++	/* header */
++	memcpy(w_entry, hdr, DBG_RING_ENTRY_SIZE);
++	w_entry->len = hdr->len;
++	/* payload */
++	memcpy((char *)w_entry + DBG_RING_ENTRY_SIZE, data, w_entry->len);
++	/* update write pointer */
++	ring->wp += w_len;
++	if (ring->wp >= ring->ring_size) {
++		DHD_ERROR(("%s: RING%d[%s] wp pointed out of ring boundary, "
++			"wp=%d, ring_size=%d\n", __FUNCTION__, ring->id,
++			ring->name, ring->wp, ring->ring_size));
++		ASSERT(0);
++	}
++	/* update statistics */
++	ring->stat.written_records++;
++	ring->stat.written_bytes += w_len;
++	DHD_DBGIF(("%s : RING%d[%s] written_records %d, written_bytes %d, read_bytes=%d,"
++		" ring->threshold=%d, wp=%d, rp=%d\n", __FUNCTION__, ring->id, ring->name,
++		ring->stat.written_records, ring->stat.written_bytes, ring->stat.read_bytes,
++		ring->threshold, ring->wp, ring->rp));
++
++	/* Calculate current pending size */
++	if (ring->stat.written_bytes > ring->stat.read_bytes) {
++		pending_len = ring->stat.written_bytes - ring->stat.read_bytes;
++	} else if (ring->stat.written_bytes < ring->stat.read_bytes) {
++		pending_len = 0xFFFFFFFF - ring->stat.read_bytes + ring->stat.written_bytes;
++	} else {
++		pending_len = 0;
++	}
++
++	/* if the current pending size is bigger than threshold */
++	if (ring->threshold > 0 &&
++	   (pending_len >= ring->threshold) && ring->sched_pull) {
++		dhdp->dbg->pullreq(dhdp->dbg->private, ring->id);
++		ring->sched_pull = FALSE;
++	}
++	dhd_os_spin_unlock(ring->lock, flags);
++	return BCME_OK;
++}
++
++static int
++dhd_dbg_msgtrace_seqchk(uint32 *prev, uint32 cur)
++{
++	/* normal case including wrap around */
++	if ((cur == 0 && *prev == 0xFFFFFFFF) || ((cur - *prev) == 1)) {
++		goto done;
++	} else if (cur == *prev) {
++		DHD_EVENT(("%s duplicate trace\n", __FUNCTION__));
++		return -1;
++	} else if (cur > *prev) {
++		DHD_EVENT(("%s lost %d packets\n", __FUNCTION__, cur - *prev));
++	} else {
++		DHD_EVENT(("%s seq out of order, dhd %d, dongle %d\n",
++			__FUNCTION__, *prev, cur));
++	}
++done:
++	*prev = cur;
++	return 0;
++}
++
++#ifndef MACOSX_DHD
++static void
++dhd_dbg_msgtrace_msg_parser(void *event_data)
++{
++	msgtrace_hdr_t *hdr;
++	char *data, *s;
++	static uint32 seqnum_prev = 0;
++
++	hdr = (msgtrace_hdr_t *)event_data;
++	data = (char *)event_data + MSGTRACE_HDRLEN;
++
++	/* There are 2 bytes available at the end of data */
++	data[ntoh16(hdr->len)] = '\0';
++
++	if (ntoh32(hdr->discarded_bytes) || ntoh32(hdr->discarded_printf)) {
++		DHD_DBGIF(("WLC_E_TRACE: [Discarded traces in dongle -->"
++			"discarded_bytes %d discarded_printf %d]\n",
++			ntoh32(hdr->discarded_bytes),
++			ntoh32(hdr->discarded_printf)));
++	}
++
++	if (dhd_dbg_msgtrace_seqchk(&seqnum_prev, ntoh32(hdr->seqnum)))
++		return;
++
++	/* Display the trace buffer. Advance from
++	 * \n to \n to avoid display big
++	 * printf (issue with Linux printk )
++	 */
++	while (*data != '\0' && (s = strstr(data, "\n")) != NULL) {
++		*s = '\0';
++		DHD_FWLOG(("[FWLOG] %s\n", data));
++		data = s+1;
++	}
++	if (*data)
++		DHD_FWLOG(("[FWLOG] %s", data));
++}
++#endif /* MACOSX_DHD */
++#ifdef SHOW_LOGTRACE
++static const uint8 *
++event_get_tlv(uint16 id, const char* tlvs, uint tlvs_len)
++{
++	const uint8 *pos = (const uint8 *)tlvs;
++	const uint8 *end = pos + tlvs_len;
++	const tlv_log *tlv;
++	int rest;
++
++	while (pos + 1 < end) {
++		if (pos + 4 + pos[1] > end)
++			break;
++		tlv = (const tlv_log *) pos;
++		if (tlv->tag == id)
++			return pos;
++		rest = tlv->len % 4; /* padding values */
++		pos += 4 + tlv->len + rest;
++	}
++	return NULL;
++}
++
++#define DATA_UNIT_FOR_LOG_CNT 4
++/* #pragma used as a WAR to fix build failure,
++ * ignore dropping of 'const' qualifier in tlv_data assignment
++ * this pragma disables the warning only for the following function
++ */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++static int
++dhd_dbg_nan_event_handler(dhd_pub_t *dhdp, event_log_hdr_t *hdr, uint32 *data)
++{
++	int ret = BCME_OK;
++	wl_event_log_id_ver_t nan_hdr;
++	log_nan_event_t *evt_payload;
++	uint16 evt_payload_len = 0, tot_payload_len = 0;
++	dhd_dbg_ring_entry_t msg_hdr;
++	bool evt_match = FALSE;
++	event_log_hdr_t *ts_hdr;
++	uint32 *ts_data;
++	char *tlvs, *dest_tlvs;
++	tlv_log *tlv_data;
++	int tlv_len = 0;
++	int i = 0, evt_idx = 0;
++	char eaddr_buf[ETHER_ADDR_STR_LEN];
++
++	BCM_REFERENCE(eaddr_buf);
++
++	nan_hdr.t = *data;
++	DHD_DBGIF(("%s: version %u event %x\n", __FUNCTION__, nan_hdr.version,
++		nan_hdr.event));
++
++	if (nan_hdr.version != DIAG_VERSION) {
++		DHD_ERROR(("Event payload version %u mismatch with current version %u\n",
++			nan_hdr.version, DIAG_VERSION));
++		return BCME_VERSION;
++	}
++
++	/* nan event log should at least contain a wl_event_log_id_ver_t
++	 * header and a arm cycle count
++	 */
++	if (hdr->count < NAN_EVENT_LOG_MIN_LENGTH) {
++		return BCME_BADLEN;
++	}
++
++	memset(&msg_hdr, 0, sizeof(dhd_dbg_ring_entry_t));
++	ts_hdr = (event_log_hdr_t *)((uint8 *)data - sizeof(event_log_hdr_t));
++	if (ts_hdr->tag == EVENT_LOG_TAG_TS) {
++		ts_data = (uint32 *)ts_hdr - ts_hdr->count;
++		msg_hdr.timestamp = (uint64)ts_data[0];
++		msg_hdr.flags |= DBG_RING_ENTRY_FLAGS_HAS_TIMESTAMP;
++	}
++	msg_hdr.type = DBG_RING_ENTRY_NAN_EVENT_TYPE;
++	for (i = 0; i < ARRAYSIZE(nan_event_map); i++) {
++		if (nan_event_map[i].fw_id == nan_hdr.event) {
++			evt_match = TRUE;
++			evt_idx = i;
++			break;
++		}
++	}
++	if (evt_match) {
++		DHD_DBGIF(("%s : event (%s)\n", __FUNCTION__, nan_event_map[evt_idx].desc));
++		/* payload length for nan event data */
++		evt_payload_len = sizeof(log_nan_event_t) +
++			(hdr->count - 2) * DATA_UNIT_FOR_LOG_CNT;
++		if ((evt_payload = MALLOC(dhdp->osh, evt_payload_len)) == NULL) {
++			DHD_ERROR(("Memory allocation failed for nan evt log (%u)\n",
++				evt_payload_len));
++			return BCME_NOMEM;
++		}
++		evt_payload->version = NAN_EVENT_VERSION;
++		evt_payload->event = nan_event_map[evt_idx].host_id;
++		dest_tlvs = (char *)evt_payload->tlvs;
++		tot_payload_len = sizeof(log_nan_event_t);
++		tlvs = (char *)(&data[1]);
++		tlv_len = (hdr->count - 2) * DATA_UNIT_FOR_LOG_CNT;
++		for (i = 0; i < ARRAYSIZE(nan_evt_tag_map); i++) {
++			tlv_data = (tlv_log *)event_get_tlv(nan_evt_tag_map[i].fw_id,
++				tlvs, tlv_len);
++			if (tlv_data) {
++				DHD_DBGIF(("NAN evt tlv.tag(%s), tlv.len : %d, tlv.data :  ",
++					nan_evt_tag_map[i].desc, tlv_data->len));
++				memcpy(dest_tlvs, tlv_data, sizeof(tlv_log) + tlv_data->len);
++				tot_payload_len += tlv_data->len + sizeof(tlv_log);
++				switch (tlv_data->tag) {
++					case TRACE_TAG_BSSID:
++					case TRACE_TAG_ADDR:
++						DHD_DBGIF(("%s\n",
++						bcm_ether_ntoa(
++							(const struct ether_addr *)tlv_data->value,
++							eaddr_buf)));
++					break;
++					default:
++						if (DHD_DBGIF_ON()) {
++							prhex(NULL, &tlv_data->value[0],
++								tlv_data->len);
++						}
++					break;
++				}
++				dest_tlvs += tlv_data->len + sizeof(tlv_log);
++			}
++		}
++		msg_hdr.flags |= DBG_RING_ENTRY_FLAGS_HAS_BINARY;
++		msg_hdr.len = tot_payload_len;
++		dhd_dbg_ring_push(dhdp, NAN_EVENT_RING_ID, &msg_hdr, evt_payload);
++		MFREE(dhdp->osh, evt_payload, evt_payload_len);
++	}
++	return ret;
++}
++
++static int
++dhd_dbg_custom_evnt_handler(dhd_pub_t *dhdp, event_log_hdr_t *hdr, uint32 *data)
++{
++	int i = 0, match_idx = 0;
++	int payload_len, tlv_len;
++	uint16 tot_payload_len = 0;
++	int ret = BCME_OK;
++	int log_level;
++	wl_event_log_id_ver_t wl_log_id;
++	dhd_dbg_ring_entry_t msg_hdr;
++	log_conn_event_t *event_data;
++	bool evt_match = FALSE;
++	event_log_hdr_t *ts_hdr;
++	uint32 *ts_data;
++	char *tlvs, *dest_tlvs;
++	tlv_log *tlv_data;
++	static uint64 ts_saved = 0;
++	char eabuf[ETHER_ADDR_STR_LEN];
++	char chanbuf[CHANSPEC_STR_LEN];
++
++	BCM_REFERENCE(eabuf);
++	BCM_REFERENCE(chanbuf);
++	/* get a event type and version */
++	wl_log_id.t = *data;
++	if (wl_log_id.version != DIAG_VERSION)
++		return BCME_VERSION;
++
++	/* custom event log should at least contain a wl_event_log_id_ver_t
++	 * header and a arm cycle count
++	 */
++	if (hdr->count < NAN_EVENT_LOG_MIN_LENGTH) {
++		return BCME_BADLEN;
++	}
++
++	ts_hdr = (event_log_hdr_t *)((uint8 *)data - sizeof(event_log_hdr_t));
++	if (ts_hdr->tag == EVENT_LOG_TAG_TS) {
++		ts_data = (uint32 *)ts_hdr - ts_hdr->count;
++		ts_saved = (uint64)ts_data[0];
++	}
++	memset(&msg_hdr, 0, sizeof(dhd_dbg_ring_entry_t));
++	msg_hdr.timestamp = ts_saved;
++
++	DHD_DBGIF(("Android Event ver %d, payload %d words, ts %llu\n",
++		(*data >> 16), hdr->count - 1, ts_saved));
++
++	/* Perform endian convertion */
++	for (i = 0; i < hdr->count; i++) {
++		/* *(data + i) = ntoh32(*(data + i)); */
++		DHD_DATA(("%08x ", *(data + i)));
++	}
++	DHD_DATA(("\n"));
++	msg_hdr.flags |= DBG_RING_ENTRY_FLAGS_HAS_TIMESTAMP;
++	msg_hdr.flags |= DBG_RING_ENTRY_FLAGS_HAS_BINARY;
++	msg_hdr.type = DBG_RING_ENTRY_EVENT_TYPE;
++
++	/* convert the data to log_conn_event_t format */
++	for (i = 0; i < ARRAYSIZE(event_map); i++) {
++		if (event_map[i].fw_id == wl_log_id.event) {
++			evt_match = TRUE;
++			match_idx = i;
++			break;
++		}
++	}
++	if (evt_match) {
++		log_level = dhdp->dbg->dbg_rings[FW_EVENT_RING_ID].log_level;
++		/* filter the data based on log_level */
++		for (i = 0; i < ARRAYSIZE(fw_event_level_map); i++) {
++			if ((fw_event_level_map[i].tag == hdr->tag) &&
++				(fw_event_level_map[i].log_level > log_level)) {
++				return BCME_OK;
++			}
++		}
++		DHD_DBGIF(("%s : event (%s)\n", __FUNCTION__, event_map[match_idx].desc));
++		/* get the payload length for event data (skip : log header + timestamp) */
++		payload_len = sizeof(log_conn_event_t) + DATA_UNIT_FOR_LOG_CNT * (hdr->count - 2);
++		event_data = MALLOC(dhdp->osh, payload_len);
++		if (!event_data) {
++			DHD_ERROR(("failed to allocate the log_conn_event_t with length(%d)\n",
++				payload_len));
++			return BCME_NOMEM;
++		}
++		event_data->event = event_map[match_idx].host_id;
++		dest_tlvs = (char *)event_data->tlvs;
++		tot_payload_len = sizeof(log_conn_event_t);
++		tlvs = (char *)(&data[1]);
++		tlv_len = (hdr->count - 2) * DATA_UNIT_FOR_LOG_CNT;
++		for (i = 0; i < ARRAYSIZE(event_tag_map); i++) {
++			tlv_data = (tlv_log *)event_get_tlv(event_tag_map[i].fw_id,
++			         tlvs, tlv_len);
++			if (tlv_data) {
++				DHD_DBGIF(("tlv.tag(%s), tlv.len : %d, tlv.data :  ",
++					event_tag_map[i].desc, tlv_data->len));
++				memcpy(dest_tlvs, tlv_data, sizeof(tlv_log) + tlv_data->len);
++				tot_payload_len += tlv_data->len + sizeof(tlv_log);
++				switch (tlv_data->tag) {
++				case TRACE_TAG_BSSID:
++				case TRACE_TAG_ADDR:
++				case TRACE_TAG_ADDR1:
++				case TRACE_TAG_ADDR2:
++				case TRACE_TAG_ADDR3:
++				case TRACE_TAG_ADDR4:
++					DHD_DBGIF(("%s\n",
++					bcm_ether_ntoa((const struct ether_addr *)tlv_data->value,
++							eabuf)));
++					break;
++				case TRACE_TAG_SSID:
++					DHD_DBGIF(("%s\n", tlv_data->value));
++					break;
++				case TRACE_TAG_STATUS:
++					DHD_DBGIF(("%d\n", ltoh32_ua(&tlv_data->value[0])));
++					break;
++				case TRACE_TAG_REASON_CODE:
++					DHD_DBGIF(("%d\n", ltoh16_ua(&tlv_data->value[0])));
++					break;
++				case TRACE_TAG_RATE_MBPS:
++					DHD_DBGIF(("%d Kbps\n",
++						ltoh16_ua(&tlv_data->value[0]) * 500));
++					break;
++				case TRACE_TAG_CHANNEL_SPEC:
++					DHD_DBGIF(("%s\n",
++						wf_chspec_ntoa(
++							ltoh16_ua(&tlv_data->value[0]), chanbuf)));
++					break;
++				default:
++					if (DHD_DBGIF_ON()) {
++						prhex(NULL, &tlv_data->value[0], tlv_data->len);
++					}
++				}
++				dest_tlvs += tlv_data->len + sizeof(tlv_log);
++			}
++		}
++		msg_hdr.len = tot_payload_len;
++		dhd_dbg_ring_push(dhdp, FW_EVENT_RING_ID, &msg_hdr, event_data);
++		MFREE(dhdp->osh, event_data, payload_len);
++	}
++	return ret;
++}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++/* To identify format of types %Ns where N >= 0 is a number */
++bool
++check_valid_string_format(char *curr_ptr)
++{
++	char *next_ptr;
++	if ((next_ptr = bcmstrstr(curr_ptr, "s")) != NULL) {
++		/* Default %s format */
++		if (curr_ptr == next_ptr) {
++			return TRUE;
++		}
++
++		/* Verify each charater between '%' and 's' is a valid number */
++		while (curr_ptr < next_ptr) {
++			if (bcm_isdigit(*curr_ptr) == FALSE) {
++				return FALSE;
++			}
++			curr_ptr++;
++		}
++
++		return TRUE;
++	} else {
++		return FALSE;
++	}
++}
++
++#define MAX_NO_OF_ARG	16
++#define FMTSTR_SIZE	132
++#define ROMSTR_SIZE	200
++#define SIZE_LOC_STR	50
++static uint64 verboselog_ts_saved = 0;
++static void
++dhd_dbg_verboselog_handler(dhd_pub_t *dhdp, event_log_hdr_t *hdr,
++		void *raw_event_ptr)
++{
++	event_log_hdr_t *ts_hdr;
++	uint32 *log_ptr = (uint32 *)hdr - hdr->count;
++	char fmtstr_loc_buf[ROMSTR_SIZE] = { 0 };
++	uint32 rom_str_len = 0;
++	uint32 *ts_data;
++
++	if (!raw_event_ptr) {
++		return;
++	}
++
++	/* Get time stamp if it's updated */
++	ts_hdr = (event_log_hdr_t *)((char *)log_ptr - sizeof(event_log_hdr_t));
++	if (ts_hdr->tag == EVENT_LOG_TAG_TS) {
++		ts_data = (uint32 *)ts_hdr - ts_hdr->count;
++		verboselog_ts_saved = (uint64)ts_data[0];
++		DHD_MSGTRACE_LOG(("EVENT_LOG_TS[0x%08x]: SYS:%08x CPU:%08x\n",
++			ts_data[ts_hdr->count - 1], ts_data[0], ts_data[1]));
++	}
++
++	if (hdr->tag == EVENT_LOG_TAG_ROM_PRINTF) {
++		rom_str_len = (hdr->count - 1) * sizeof(uint32);
++		if (rom_str_len >= (ROMSTR_SIZE -1))
++			rom_str_len = ROMSTR_SIZE - 1;
++
++		/* copy all ascii data for ROM printf to local string */
++		memcpy(fmtstr_loc_buf, log_ptr, rom_str_len);
++		/* add end of line at last */
++		fmtstr_loc_buf[rom_str_len] = '\0';
++
++		DHD_MSGTRACE_LOG(("EVENT_LOG_ROM[0x%08x]: %s",
++				log_ptr[hdr->count - 1], fmtstr_loc_buf));
++
++		/* Add newline if missing */
++		if (fmtstr_loc_buf[strlen(fmtstr_loc_buf) - 1] != '\n')
++			DHD_MSGTRACE_LOG(("\n"));
++
++		return;
++	}
++
++	if (hdr->tag == EVENT_LOG_TAG_MSCHPROFILE || hdr->tag == EVENT_LOG_TAG_MSCHPROFILE_TLV) {
++		wl_mschdbg_verboselog_handler(dhdp, raw_event_ptr, hdr->tag, log_ptr);
++		return;
++	}
++
++	/* print the message out in a logprint  */
++	dhd_dbg_verboselog_printf(dhdp, hdr, raw_event_ptr, log_ptr);
++}
++
++void
++dhd_dbg_verboselog_printf(dhd_pub_t *dhdp, event_log_hdr_t *hdr,
++	void *raw_event_ptr, uint32 *log_ptr)
++{
++	dhd_event_log_t *raw_event = (dhd_event_log_t *)raw_event_ptr;
++	uint16 count;
++	int log_level, id;
++	char fmtstr_loc_buf[ROMSTR_SIZE] = { 0 };
++	char (*str_buf)[SIZE_LOC_STR] = NULL;
++	char *str_tmpptr = NULL;
++	uint32 addr = 0;
++	typedef union {
++		uint32 val;
++		char * addr;
++	} u_arg;
++	u_arg arg[MAX_NO_OF_ARG] = {{0}};
++	char *c_ptr = NULL;
++
++	BCM_REFERENCE(arg);
++
++	if (!raw_event) {
++		return;
++	}
++
++	/* print the message out in a logprint  */
++	if (!(raw_event->fmts) || hdr->fmt_num == 0xffff) {
++		if (dhdp->dbg) {
++			log_level = dhdp->dbg->dbg_rings[FW_VERBOSE_RING_ID].log_level;
++			for (id = 0; id < ARRAYSIZE(fw_verbose_level_map); id++) {
++				if ((fw_verbose_level_map[id].tag == hdr->tag) &&
++					(fw_verbose_level_map[id].log_level > log_level))
++					return;
++			}
++		}
++
++		DHD_EVENT(("%d.%d EL:tag=%d len=%d fmt=0x%x",
++			(uint32)verboselog_ts_saved / 1000,
++			(uint32)verboselog_ts_saved % 1000,
++			hdr->tag,
++			hdr->count,
++			hdr->fmt_num));
++
++		for (count = 0; count < (hdr->count-1); count++) {
++			if (count % 8 == 0)
++				DHD_EVENT(("\n\t%08x", log_ptr[count]));
++			else
++				DHD_EVENT((" %08x", log_ptr[count]));
++		}
++		DHD_EVENT(("\n"));
++
++		return;
++	}
++
++	str_buf = MALLOCZ(dhdp->osh, (MAX_NO_OF_ARG * SIZE_LOC_STR));
++	if (!str_buf) {
++		DHD_ERROR(("%s: malloc failed str_buf\n", __FUNCTION__));
++		return;
++	}
++
++	if ((hdr->fmt_num >> 2) < raw_event->num_fmts) {
++		if (hdr->tag == EVENT_LOG_TAG_MSCHPROFILE) {
++			snprintf(fmtstr_loc_buf, FMTSTR_SIZE, "%s",
++				raw_event->fmts[hdr->fmt_num >> 2]);
++			hdr->count++;
++		} else {
++			snprintf(fmtstr_loc_buf, FMTSTR_SIZE, "CONSOLE_E: %6d.%3d %s",
++				log_ptr[hdr->count-1]/1000, (log_ptr[hdr->count - 1] % 1000),
++				raw_event->fmts[hdr->fmt_num >> 2]);
++		}
++		c_ptr = fmtstr_loc_buf;
++	} else {
++		DHD_ERROR(("%s: fmt number out of range \n", __FUNCTION__));
++		goto exit;
++	}
++
++	for (count = 0; count < (hdr->count - 1); count++) {
++		if (c_ptr != NULL)
++			if ((c_ptr = bcmstrstr(c_ptr, "%")) != NULL)
++				c_ptr++;
++
++		if (c_ptr != NULL) {
++			if (check_valid_string_format(c_ptr)) {
++				if ((raw_event->raw_sstr) &&
++					((log_ptr[count] > raw_event->rodata_start) &&
++					(log_ptr[count] < raw_event->rodata_end))) {
++					/* ram static string */
++					addr = log_ptr[count] - raw_event->rodata_start;
++					str_tmpptr = raw_event->raw_sstr + addr;
++					memcpy(str_buf[count], str_tmpptr,
++						SIZE_LOC_STR);
++					str_buf[count][SIZE_LOC_STR-1] = '\0';
++					arg[count].addr = str_buf[count];
++				} else if ((raw_event->rom_raw_sstr) &&
++						((log_ptr[count] >
++						raw_event->rom_rodata_start) &&
++						(log_ptr[count] <
++						raw_event->rom_rodata_end))) {
++					/* rom static string */
++					addr = log_ptr[count] - raw_event->rom_rodata_start;
++					str_tmpptr = raw_event->rom_raw_sstr + addr;
++					memcpy(str_buf[count], str_tmpptr,
++						SIZE_LOC_STR);
++					str_buf[count][SIZE_LOC_STR-1] = '\0';
++					arg[count].addr = str_buf[count];
++				} else {
++					/*
++					*  Dynamic string OR
++					* No data for static string.
++					* So store all string's address as string.
++					*/
++					snprintf(str_buf[count], SIZE_LOC_STR,
++						"(s)0x%x", log_ptr[count]);
++					arg[count].addr = str_buf[count];
++				}
++			} else {
++				/* Other than string */
++				arg[count].val = log_ptr[count];
++			}
++		}
++	}
++
++	/* Print FW logs */
++	DHD_FWLOG((fmtstr_loc_buf, arg[0], arg[1], arg[2], arg[3],
++		arg[4], arg[5], arg[6], arg[7], arg[8], arg[9], arg[10],
++		arg[11], arg[12], arg[13], arg[14], arg[15]));
++
++exit:
++	MFREE(dhdp->osh, str_buf, (MAX_NO_OF_ARG * SIZE_LOC_STR));
++}
++
++static void
++dhd_dbg_msgtrace_log_parser(dhd_pub_t *dhdp, void *event_data,
++	void *raw_event_ptr, uint datalen)
++{
++	msgtrace_hdr_t *hdr;
++	char *data;
++	int id;
++	uint32 log_hdr_len = sizeof(event_log_hdr_t);
++	uint32 log_pyld_len;
++	static uint32 seqnum_prev = 0;
++	event_log_hdr_t *log_hdr;
++	bool msg_processed = FALSE;
++	uint32 *log_ptr =  NULL;
++	dll_t list_head, *cur;
++	loglist_item_t *log_item;
++	int32 nan_evt_ring_log_level = 0;
++	dhd_dbg_ring_entry_t msg_hdr;
++	char *logbuf;
++	struct tracelog_header *logentry_header;
++
++	/* log trace event consists of:
++	 * msgtrace header
++	 * event log block header
++	 * event log payload
++	 */
++	if (datalen <= MSGTRACE_HDRLEN + EVENT_LOG_BLOCK_HDRLEN) {
++		return;
++	}
++	hdr = (msgtrace_hdr_t *)event_data;
++	data = (char *)event_data + MSGTRACE_HDRLEN;
++	datalen -= MSGTRACE_HDRLEN;
++
++	if (dhd_dbg_msgtrace_seqchk(&seqnum_prev, ntoh32(hdr->seqnum)))
++		return;
++
++	/* Save the whole message to event log ring */
++	memset(&msg_hdr, 0, sizeof(dhd_dbg_ring_entry_t));
++	logbuf = VMALLOC(dhdp->osh, sizeof(*logentry_header) + datalen);
++	if (logbuf == NULL)
++		return;
++	logentry_header = (struct tracelog_header *)logbuf;
++	logentry_header->magic_num = TRACE_LOG_MAGIC_NUMBER;
++	logentry_header->buf_size = datalen;
++	logentry_header->seq_num = hdr->seqnum;
++	msg_hdr.type = DBG_RING_ENTRY_DATA_TYPE;
++
++	if ((sizeof(*logentry_header) + datalen) > PAYLOAD_MAX_LEN) {
++		DHD_ERROR(("%s:Payload len=%u exceeds max len\n", __FUNCTION__,
++			((uint)sizeof(*logentry_header) + datalen)));
++		VMFREE(dhdp->osh, logbuf, sizeof(*logentry_header) + datalen);
++		return;
++	}
++
++	msg_hdr.len = sizeof(*logentry_header) + datalen;
++	memcpy(logbuf + sizeof(*logentry_header), data, datalen);
++	dhd_dbg_ring_push(dhdp, FW_VERBOSE_RING_ID, &msg_hdr, logbuf);
++	VMFREE(dhdp->osh, logbuf, sizeof(*logentry_header) + datalen);
++
++	/* Print sequence number, originating set and length of received
++	 * event log buffer. Refer to event log buffer structure in
++	 * event_log.h
++	 */
++	DHD_MSGTRACE_LOG(("EVENT_LOG_HDR[0x%x]: Set: 0x%08x length = %d\n",
++		ltoh16(*((uint16 *)(data+2))), ltoh32(*((uint32 *)(data + 4))),
++		ltoh16(*((uint16 *)(data)))));
++	data += EVENT_LOG_BLOCK_HDRLEN;
++	datalen -= EVENT_LOG_BLOCK_HDRLEN;
++
++	/* start parsing from the tail of packet
++	 * Sameple format of a meessage
++	 * 001d3c54 00000064 00000064 001d3c54 001dba08 035d6ce1 0c540639
++	 * 001d3c54 00000064 00000064 035d6d89 0c580439
++	 * 0x0c580439 -- 39 is tag, 04 is count, 580c is format number
++	 * all these uint32 values comes in reverse order as group as EL data
++	 * while decoding we can only parse from last to first
++	 * |<-                     datalen                     ->|
++	 * |----(payload and maybe more logs)----|event_log_hdr_t|
++	 * data                                  log_hdr
++	 */
++	dll_init(&list_head);
++	while (datalen > log_hdr_len) {
++		log_hdr = (event_log_hdr_t *)(data + datalen - log_hdr_len);
++		/* skip zero padding at end of frame */
++		if (log_hdr->tag == EVENT_LOG_TAG_NULL) {
++			datalen -= log_hdr_len;
++			continue;
++		}
++		/* Check argument count, any event log should contain at least
++		 * one argument (4 bytes) for arm cycle count and up to 16
++		 * arguments when the format is valid
++		 */
++		if (log_hdr->count == 0) {
++			break;
++		}
++		if ((log_hdr->count > MAX_NO_OF_ARG) && (log_hdr->fmt_num != 0xffff)) {
++			break;
++		}
++
++		log_pyld_len = log_hdr->count * DATA_UNIT_FOR_LOG_CNT;
++		/* log data should not cross the event data boundary */
++		if ((char *)log_hdr - data < log_pyld_len)
++			break;
++		/* skip 4 bytes time stamp packet */
++		if (log_hdr->tag == EVENT_LOG_TAG_TS) {
++			datalen -= log_pyld_len + log_hdr_len;
++			continue;
++		}
++		if (!(log_item = MALLOC(dhdp->osh, sizeof(*log_item)))) {
++			DHD_ERROR(("%s allocating log list item failed\n",
++				__FUNCTION__));
++			break;
++		}
++		log_item->hdr = log_hdr;
++		dll_insert(&log_item->list, &list_head);
++		datalen -= (log_pyld_len + log_hdr_len);
++	}
++
++	while (!dll_empty(&list_head)) {
++		msg_processed = FALSE;
++		cur = dll_head_p(&list_head);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++		log_item = (loglist_item_t *)container_of(cur, loglist_item_t, list);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++		log_hdr = log_item->hdr;
++		log_ptr = (uint32 *)log_hdr - log_hdr->count;
++		dll_delete(cur);
++		MFREE(dhdp->osh, log_item, sizeof(*log_item));
++
++		/* Before DHD debugability is implemented WLC_E_TRACE had been
++		 * used to carry verbose logging from firmware. We need to
++		 * be able to handle those messages even without a initialized
++		 * debug layer.
++		 */
++		if (dhdp->dbg) {
++			/* check the data for NAN event ring; keeping first as small table */
++			/* process only user configured to log */
++			nan_evt_ring_log_level = dhdp->dbg->dbg_rings[NAN_EVENT_RING_ID].log_level;
++			if (dhdp->dbg->dbg_rings[NAN_EVENT_RING_ID].log_level) {
++				for (id = 0; id < ARRAYSIZE(nan_event_level_map); id++) {
++					if (nan_event_level_map[id].tag == log_hdr->tag) {
++						/* dont process if tag log level is greater
++						 * than ring log level
++						 */
++						if (nan_event_level_map[id].log_level >
++							nan_evt_ring_log_level) {
++							msg_processed = TRUE;
++							break;
++						}
++						/* In case of BCME_VERSION error,
++						 * this is not NAN event type data
++						 */
++						if (dhd_dbg_nan_event_handler(dhdp,
++							log_hdr, log_ptr) != BCME_VERSION) {
++							msg_processed = TRUE;
++						}
++						break;
++					}
++				}
++			}
++			if (!msg_processed) {
++				/* check the data for event ring */
++				for (id = 0; id < ARRAYSIZE(fw_event_level_map); id++) {
++					if (fw_event_level_map[id].tag == log_hdr->tag) {
++						/* In case of BCME_VERSION error,
++						 * this is not event type data
++						 */
++						if (dhd_dbg_custom_evnt_handler(dhdp,
++							log_hdr, log_ptr) != BCME_VERSION) {
++							msg_processed = TRUE;
++						}
++						break;
++					}
++				}
++			}
++		}
++		if (!msg_processed)
++			dhd_dbg_verboselog_handler(dhdp, log_hdr, raw_event_ptr);
++
++	}
++}
++#else /* !SHOW_LOGTRACE */
++static INLINE void dhd_dbg_verboselog_handler(dhd_pub_t *dhdp,
++	event_log_hdr_t *hdr, void *raw_event_ptr) {};
++static INLINE void dhd_dbg_msgtrace_log_parser(dhd_pub_t *dhdp,
++	void *event_data, void *raw_event_ptr, uint datalen) {};
++#endif /* SHOW_LOGTRACE */
++#ifndef MACOSX_DHD
++void
++dhd_dbg_trace_evnt_handler(dhd_pub_t *dhdp, void *event_data,
++		void *raw_event_ptr, uint datalen)
++{
++	msgtrace_hdr_t *hdr;
++
++	hdr = (msgtrace_hdr_t *)event_data;
++
++	if (hdr->version != MSGTRACE_VERSION) {
++		DHD_DBGIF(("%s unsupported MSGTRACE version, dhd %d, dongle %d\n",
++			__FUNCTION__, MSGTRACE_VERSION, hdr->version));
++		return;
++	}
++
++	if (hdr->trace_type == MSGTRACE_HDR_TYPE_MSG)
++		dhd_dbg_msgtrace_msg_parser(event_data);
++	else if (hdr->trace_type == MSGTRACE_HDR_TYPE_LOG)
++		dhd_dbg_msgtrace_log_parser(dhdp, event_data, raw_event_ptr, datalen);
++}
++#endif /* MACOSX_DHD */
++static int
++dhd_dbg_ring_init(dhd_pub_t *dhdp, dhd_dbg_ring_t *ring, uint16 id, uint8 *name,
++		uint32 ring_sz, int section)
++{
++	void *buf;
++	unsigned long flags;
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++	buf = DHD_OS_PREALLOC(dhdp, section, ring_sz);
++#else
++	buf = MALLOCZ(dhdp->osh, ring_sz);
++#endif
++	if (!buf)
++		return BCME_NOMEM;
++
++	ring->lock = dhd_os_spin_lock_init(dhdp->osh);
++
++	flags = dhd_os_spin_lock(ring->lock);
++	ring->id = id;
++	strncpy(ring->name, name, DBGRING_NAME_MAX);
++	ring->name[DBGRING_NAME_MAX - 1] = 0;
++	ring->ring_size = ring_sz;
++	ring->wp = ring->rp = 0;
++	ring->ring_buf = buf;
++	ring->threshold = DBGRING_FLUSH_THRESHOLD(ring);
++	ring->state = RING_SUSPEND;
++	ring->sched_pull = TRUE;
++	ring->rem_len = 0;
++	dhd_os_spin_unlock(ring->lock, flags);
++
++	return BCME_OK;
++}
++
++static void
++dhd_dbg_ring_deinit(dhd_pub_t *dhdp, dhd_dbg_ring_t *ring)
++{
++	void *buf;
++	uint32 ring_sz;
++	unsigned long flags;
++
++	if (!ring->ring_buf)
++		return;
++
++	flags = dhd_os_spin_lock(ring->lock);
++	ring->id = 0;
++	ring->name[0] = 0;
++	ring_sz = ring->ring_size;
++	ring->ring_size = 0;
++	ring->wp = ring->rp = 0;
++	buf = ring->ring_buf;
++	ring->ring_buf = NULL;
++	memset(&ring->stat, 0, sizeof(ring->stat));
++	ring->threshold = 0;
++	ring->state = RING_STOP;
++	dhd_os_spin_unlock(ring->lock, flags);
++
++	dhd_os_spin_lock_deinit(dhdp->osh, ring->lock);
++#ifndef CONFIG_DHD_USE_STATIC_BUF
++	MFREE(dhdp->osh, buf, ring_sz);
++#endif
++}
++
++uint8
++dhd_dbg_find_sets_by_tag(uint16 tag)
++{
++	uint i;
++	uint8 sets = 0;
++
++	for (i = 0; i < ARRAYSIZE(fw_verbose_level_map); i++) {
++		if (fw_verbose_level_map[i].tag == tag) {
++			sets |= fw_verbose_level_map[i].sets;
++		}
++	}
++
++	for (i = 0; i < ARRAYSIZE(fw_event_level_map); i++) {
++		if (fw_event_level_map[i].tag == tag) {
++			sets |= fw_event_level_map[i].sets;
++		}
++	}
++
++	return sets;
++}
++
++/*
++ * dhd_dbg_set_event_log_tag : modify the state of an event log tag
++ */
++void
++dhd_dbg_set_event_log_tag(dhd_pub_t *dhdp, uint16 tag, uint8 set)
++{
++	wl_el_tag_params_t pars;
++	char *cmd = "event_log_tag_control";
++	char iovbuf[WLC_IOCTL_SMLEN] = { 0 };
++	int ret;
++
++	memset(&pars, 0, sizeof(pars));
++	pars.tag = tag;
++	pars.set = dhd_dbg_find_sets_by_tag(tag);
++	pars.flags = set ? EVENT_LOG_TAG_FLAG_LOG : EVENT_LOG_TAG_FLAG_NONE;
++
++	if (!bcm_mkiovar(cmd, (char *)&pars, sizeof(pars), iovbuf, sizeof(iovbuf))) {
++		DHD_ERROR(("%s mkiovar failed\n", __FUNCTION__));
++		return;
++	}
++
++	ret = dhd_wl_ioctl_cmd(dhdp, WLC_SET_VAR, iovbuf, sizeof(iovbuf), TRUE, 0);
++	if (ret) {
++		DHD_ERROR(("%s set log tag iovar failed %d\n", __FUNCTION__, ret));
++	}
++}
++
++int
++dhd_dbg_set_configuration(dhd_pub_t *dhdp, int ring_id, int log_level, int flags, uint32 threshold)
++{
++	dhd_dbg_ring_t *ring;
++	uint8 set = 1;
++	unsigned long lock_flags;
++	int i, array_len = 0;
++	struct log_level_table *log_level_tbl = NULL;
++	if (!dhdp || !dhdp->dbg)
++		return BCME_BADADDR;
++
++	ring = &dhdp->dbg->dbg_rings[ring_id];
++
++	if (ring->state == RING_STOP)
++		return BCME_UNSUPPORTED;
++
++	lock_flags = dhd_os_spin_lock(ring->lock);
++	if (log_level == 0)
++		ring->state = RING_SUSPEND;
++	else
++		ring->state = RING_ACTIVE;
++	ring->log_level = log_level;
++
++	ring->threshold = MIN(threshold, DBGRING_FLUSH_THRESHOLD(ring));
++	dhd_os_spin_unlock(ring->lock, lock_flags);
++	if (log_level > 0)
++		set = TRUE;
++
++	if (ring->id == FW_EVENT_RING_ID) {
++		log_level_tbl = fw_event_level_map;
++		array_len = ARRAYSIZE(fw_event_level_map);
++	} else if (ring->id == FW_VERBOSE_RING_ID) {
++		log_level_tbl = fw_verbose_level_map;
++		array_len = ARRAYSIZE(fw_verbose_level_map);
++	} else if (ring->id == NAN_EVENT_RING_ID) {
++		log_level_tbl = nan_event_level_map;
++		array_len = ARRAYSIZE(nan_event_level_map);
++	}
++
++	for (i = 0; i < array_len; i++) {
++		if (log_level == 0 || (log_level_tbl[i].log_level > log_level)) {
++			/* clear the reference per ring */
++			ref_tag_tbl[log_level_tbl[i].tag] &= ~(1 << ring_id);
++		} else {
++			/* set the reference per ring */
++			ref_tag_tbl[log_level_tbl[i].tag] |= (1 << ring_id);
++		}
++		set = (ref_tag_tbl[log_level_tbl[i].tag])? 1 : 0;
++		DHD_DBGIF(("%s TAG(%s) is %s for the ring(%s)\n", __FUNCTION__,
++			log_level_tbl[i].desc, (set)? "SET" : "CLEAR", ring->name));
++		dhd_dbg_set_event_log_tag(dhdp, log_level_tbl[i].tag, set);
++	}
++	return BCME_OK;
++}
++
++/*
++* dhd_dbg_get_ring_status : get the ring status from the coresponding ring buffer
++* Return: An error code or 0 on success.
++*/
++
++int
++dhd_dbg_get_ring_status(dhd_pub_t *dhdp, int ring_id, dhd_dbg_ring_status_t *dbg_ring_status)
++{
++	int ret = BCME_OK;
++	int id = 0;
++	dhd_dbg_t *dbg;
++	dhd_dbg_ring_t *dbg_ring;
++	dhd_dbg_ring_status_t ring_status;
++	if (!dhdp || !dhdp->dbg)
++		return BCME_BADADDR;
++	dbg = dhdp->dbg;
++
++	memset(&ring_status, 0, sizeof(dhd_dbg_ring_status_t));
++	for (id = DEBUG_RING_ID_INVALID + 1; id < DEBUG_RING_ID_MAX; id++) {
++		dbg_ring = &dbg->dbg_rings[id];
++		if (VALID_RING(dbg_ring->id) && (dbg_ring->id == ring_id)) {
++			RING_STAT_TO_STATUS(dbg_ring, ring_status);
++			*dbg_ring_status = ring_status;
++			break;
++		}
++	}
++	if (!VALID_RING(id)) {
++		DHD_ERROR(("%s : cannot find the ring_id : %d\n", __FUNCTION__, ring_id));
++		ret = BCME_NOTFOUND;
++	}
++	return ret;
++}
++
++/*
++* dhd_dbg_find_ring_id : return ring_id based on ring_name
++* Return: An invalid ring id for failure or valid ring id on success.
++*/
++
++int
++dhd_dbg_find_ring_id(dhd_pub_t *dhdp, char *ring_name)
++{
++	int id;
++	dhd_dbg_t *dbg;
++	dhd_dbg_ring_t *ring;
++
++	if (!dhdp || !dhdp->dbg)
++		return BCME_BADADDR;
++
++	dbg = dhdp->dbg;
++	for (id = DEBUG_RING_ID_INVALID + 1; id < DEBUG_RING_ID_MAX; id++) {
++		ring = &dbg->dbg_rings[id];
++		if (!strncmp((char *)ring->name, ring_name, sizeof(ring->name) - 1))
++			break;
++	}
++	return id;
++}
++
++/*
++* dhd_dbg_get_priv : get the private data of dhd dbugability module
++* Return : An NULL on failure or valid data address
++*/
++void *
++dhd_dbg_get_priv(dhd_pub_t *dhdp)
++{
++	if (!dhdp || !dhdp->dbg)
++		return NULL;
++	return dhdp->dbg->private;
++}
++
++/*
++* dhd_dbg_start : start and stop All of Ring buffers
++* Return: An error code or 0 on success.
++*/
++int
++dhd_dbg_start(dhd_pub_t *dhdp, bool start)
++{
++	int ret = BCME_OK;
++	int ring_id;
++	dhd_dbg_t *dbg;
++	dhd_dbg_ring_t *dbg_ring;
++	if (!dhdp)
++		return BCME_BADARG;
++	dbg = dhdp->dbg;
++
++	for (ring_id = DEBUG_RING_ID_INVALID + 1; ring_id < DEBUG_RING_ID_MAX; ring_id++) {
++		dbg_ring = &dbg->dbg_rings[ring_id];
++		if (!start) {
++			if (VALID_RING(dbg_ring->id)) {
++				/* Initialize the information for the ring */
++				dbg_ring->state = RING_SUSPEND;
++				dbg_ring->log_level = 0;
++				dbg_ring->rp = dbg_ring->wp = 0;
++				dbg_ring->threshold = 0;
++				memset(&dbg_ring->stat, 0, sizeof(struct ring_statistics));
++				memset(dbg_ring->ring_buf, 0, dbg_ring->ring_size);
++			}
++		}
++	}
++	return ret;
++}
++
++/*
++ * dhd_dbg_send_urgent_evt: send the health check evt to Upper layer
++ *
++ * Return: An error code or 0 on success.
++ */
++
++int
++dhd_dbg_send_urgent_evt(dhd_pub_t *dhdp, const void *data, const uint32 len)
++{
++	dhd_dbg_t *dbg;
++	int ret = BCME_OK;
++	if (!dhdp || !dhdp->dbg)
++		return BCME_BADADDR;
++
++	dbg = dhdp->dbg;
++	if (dbg->urgent_notifier) {
++		dbg->urgent_notifier(dhdp, data, len);
++	}
++	return ret;
++}
++
++#if defined(DBG_PKT_MON) || defined(DHD_PKT_LOGGING)
++uint32
++__dhd_dbg_pkt_hash(uintptr_t pkt, uint32 pktid)
++{
++	uint32 __pkt;
++	uint32 __pktid;
++
++	__pkt = ((int)pkt) >= 0 ? (2 * pkt) : (-2 * pkt - 1);
++	__pktid = ((int)pktid) >= 0 ? (2 * pktid) : (-2 * pktid - 1);
++
++	return (__pkt >= __pktid ? (__pkt * __pkt + __pkt + __pktid) :
++			(__pkt + __pktid * __pktid));
++}
++
++#define __TIMESPEC_TO_US(ts) \
++	(((uint32)(ts).tv_sec * USEC_PER_SEC) + ((ts).tv_nsec / NSEC_PER_USEC))
++
++uint32
++__dhd_dbg_driver_ts_usec(void)
++{
++	struct osl_timespec ts;
++
++	osl_get_monotonic_boottime(&ts);
++	return ((uint32)(__TIMESPEC_TO_US(ts)));
++}
++
++wifi_tx_packet_fate
++__dhd_dbg_map_tx_status_to_pkt_fate(uint16 status)
++{
++	wifi_tx_packet_fate pkt_fate;
++
++	switch (status) {
++		case WLFC_CTL_PKTFLAG_DISCARD:
++			pkt_fate = TX_PKT_FATE_ACKED;
++			break;
++		case WLFC_CTL_PKTFLAG_D11SUPPRESS:
++			/* intensional fall through */
++		case WLFC_CTL_PKTFLAG_WLSUPPRESS:
++			pkt_fate = TX_PKT_FATE_FW_QUEUED;
++			break;
++		case WLFC_CTL_PKTFLAG_TOSSED_BYWLC:
++			pkt_fate = TX_PKT_FATE_FW_DROP_INVALID;
++			break;
++		case WLFC_CTL_PKTFLAG_DISCARD_NOACK:
++			pkt_fate = TX_PKT_FATE_SENT;
++			break;
++		default:
++			pkt_fate = TX_PKT_FATE_FW_DROP_OTHER;
++			break;
++	}
++
++	return pkt_fate;
++}
++#endif /* DBG_PKT_MON || DHD_PKT_LOGGING */
++
++#ifdef DBG_PKT_MON
++static int
++__dhd_dbg_free_tx_pkts(dhd_pub_t *dhdp, dhd_dbg_tx_info_t *tx_pkts,
++	uint16 pkt_count)
++{
++	uint16 count;
++
++	DHD_PKT_INFO(("%s, %d\n", __FUNCTION__, __LINE__));
++	count = 0;
++	while ((count < pkt_count) && tx_pkts) {
++		if (tx_pkts->info.pkt)
++			PKTFREE(dhdp->osh, tx_pkts->info.pkt, TRUE);
++		tx_pkts++;
++		count++;
++	}
++
++	return BCME_OK;
++}
++
++static int
++__dhd_dbg_free_rx_pkts(dhd_pub_t *dhdp, dhd_dbg_rx_info_t *rx_pkts,
++	uint16 pkt_count)
++{
++	uint16 count;
++
++	DHD_PKT_INFO(("%s, %d\n", __FUNCTION__, __LINE__));
++	count = 0;
++	while ((count < pkt_count) && rx_pkts) {
++		if (rx_pkts->info.pkt)
++			PKTFREE(dhdp->osh, rx_pkts->info.pkt, TRUE);
++		rx_pkts++;
++		count++;
++	}
++
++	return BCME_OK;
++}
++
++void
++__dhd_dbg_dump_pkt_info(dhd_pub_t *dhdp, dhd_dbg_pkt_info_t *info)
++{
++	if (DHD_PKT_MON_DUMP_ON()) {
++		DHD_PKT_MON(("payload type   = %d\n", info->payload_type));
++		DHD_PKT_MON(("driver ts      = %u\n", info->driver_ts));
++		DHD_PKT_MON(("firmware ts    = %u\n", info->firmware_ts));
++		DHD_PKT_MON(("packet hash    = %u\n", info->pkt_hash));
++		DHD_PKT_MON(("packet length  = %zu\n", info->pkt_len));
++		DHD_PKT_MON(("packet address = %p\n", info->pkt));
++		DHD_PKT_MON(("packet data    = \n"));
++		if (DHD_PKT_MON_ON()) {
++			prhex(NULL, PKTDATA(dhdp->osh, info->pkt), info->pkt_len);
++		}
++	}
++}
++
++void
++__dhd_dbg_dump_tx_pkt_info(dhd_pub_t *dhdp, dhd_dbg_tx_info_t *tx_pkt,
++	uint16 count)
++{
++	if (DHD_PKT_MON_DUMP_ON()) {
++		DHD_PKT_MON(("\nTX (count: %d)\n", ++count));
++		DHD_PKT_MON(("packet fate    = %d\n", tx_pkt->fate));
++		__dhd_dbg_dump_pkt_info(dhdp, &tx_pkt->info);
++	}
++}
++
++void
++__dhd_dbg_dump_rx_pkt_info(dhd_pub_t *dhdp, dhd_dbg_rx_info_t *rx_pkt,
++	uint16 count)
++{
++	if (DHD_PKT_MON_DUMP_ON()) {
++		DHD_PKT_MON(("\nRX (count: %d)\n", ++count));
++		DHD_PKT_MON(("packet fate    = %d\n", rx_pkt->fate));
++		__dhd_dbg_dump_pkt_info(dhdp, &rx_pkt->info);
++	}
++}
++
++int
++dhd_dbg_attach_pkt_monitor(dhd_pub_t *dhdp,
++		dbg_mon_tx_pkts_t tx_pkt_mon,
++		dbg_mon_tx_status_t tx_status_mon,
++		dbg_mon_rx_pkts_t rx_pkt_mon)
++{
++
++	dhd_dbg_tx_report_t *tx_report = NULL;
++	dhd_dbg_rx_report_t *rx_report = NULL;
++	dhd_dbg_tx_info_t *tx_pkts = NULL;
++	dhd_dbg_rx_info_t *rx_pkts = NULL;
++	dhd_dbg_pkt_mon_state_t tx_pkt_state;
++	dhd_dbg_pkt_mon_state_t tx_status_state;
++	dhd_dbg_pkt_mon_state_t rx_pkt_state;
++	gfp_t kflags;
++	uint32 alloc_len;
++	int ret = BCME_OK;
++	unsigned long flags;
++
++	DHD_PKT_INFO(("%s, %d\n", __FUNCTION__, __LINE__));
++	if (!dhdp || !dhdp->dbg) {
++		DHD_PKT_MON(("%s(): dhdp=%p, dhdp->dbg=%p\n", __FUNCTION__,
++			dhdp, (dhdp ? dhdp->dbg : NULL)));
++		return -EINVAL;
++	}
++
++	DHD_PKT_MON_LOCK(dhdp->dbg->pkt_mon_lock, flags);
++	tx_pkt_state = dhdp->dbg->pkt_mon.tx_pkt_state;
++	tx_status_state = dhdp->dbg->pkt_mon.tx_pkt_state;
++	rx_pkt_state = dhdp->dbg->pkt_mon.rx_pkt_state;
++
++	if (PKT_MON_ATTACHED(tx_pkt_state) || PKT_MON_ATTACHED(tx_status_state) ||
++			PKT_MON_ATTACHED(rx_pkt_state)) {
++		DHD_PKT_MON(("%s(): packet monitor is already attached, "
++			"tx_pkt_state=%d, tx_status_state=%d, rx_pkt_state=%d\n",
++			__FUNCTION__, tx_pkt_state, tx_status_state, rx_pkt_state));
++		DHD_PKT_MON_UNLOCK(dhdp->dbg->pkt_mon_lock, flags);
++		/* return success as the intention was to initialize packet monitor */
++		return BCME_OK;
++	}
++
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++
++	/* allocate and initialize tx packet monitoring */
++	alloc_len = sizeof(*tx_report);
++	tx_report = (dhd_dbg_tx_report_t *)kzalloc(alloc_len, kflags);
++	if (unlikely(!tx_report)) {
++		DHD_ERROR(("%s(): could not allocate memory for - "
++			"dhd_dbg_tx_report_t\n", __FUNCTION__));
++		ret = -ENOMEM;
++		goto fail;
++	}
++
++	alloc_len = (sizeof(*tx_pkts) * MAX_FATE_LOG_LEN);
++	tx_pkts = (dhd_dbg_tx_info_t *)kzalloc(alloc_len, kflags);
++	if (unlikely(!tx_pkts)) {
++		DHD_ERROR(("%s(): could not allocate memory for - "
++			"dhd_dbg_tx_info_t\n", __FUNCTION__));
++		ret = -ENOMEM;
++		goto fail;
++	}
++	dhdp->dbg->pkt_mon.tx_report = tx_report;
++	dhdp->dbg->pkt_mon.tx_report->tx_pkts = tx_pkts;
++	dhdp->dbg->pkt_mon.tx_pkt_mon = tx_pkt_mon;
++	dhdp->dbg->pkt_mon.tx_status_mon = tx_status_mon;
++	dhdp->dbg->pkt_mon.tx_pkt_state = PKT_MON_ATTACHED;
++	dhdp->dbg->pkt_mon.tx_status_state = PKT_MON_ATTACHED;
++
++	/* allocate and initialze rx packet monitoring */
++	alloc_len = sizeof(*rx_report);
++	rx_report = (dhd_dbg_rx_report_t *)kzalloc(alloc_len, kflags);
++	if (unlikely(!rx_report)) {
++		DHD_ERROR(("%s(): could not allocate memory for - "
++			"dhd_dbg_rx_report_t\n", __FUNCTION__));
++		ret = -ENOMEM;
++		goto fail;
++	}
++
++	alloc_len = (sizeof(*rx_pkts) * MAX_FATE_LOG_LEN);
++	rx_pkts = (dhd_dbg_rx_info_t *)kzalloc(alloc_len, kflags);
++	if (unlikely(!rx_pkts)) {
++		DHD_ERROR(("%s(): could not allocate memory for - "
++			"dhd_dbg_rx_info_t\n", __FUNCTION__));
++		ret = -ENOMEM;
++		goto fail;
++	}
++	dhdp->dbg->pkt_mon.rx_report = rx_report;
++	dhdp->dbg->pkt_mon.rx_report->rx_pkts = rx_pkts;
++	dhdp->dbg->pkt_mon.rx_pkt_mon = rx_pkt_mon;
++	dhdp->dbg->pkt_mon.rx_pkt_state = PKT_MON_ATTACHED;
++
++	DHD_PKT_MON_UNLOCK(dhdp->dbg->pkt_mon_lock, flags);
++	DHD_PKT_MON(("%s(): packet monitor attach succeeded\n", __FUNCTION__));
++	return ret;
++
++fail:
++	/* tx packet monitoring */
++	if (tx_pkts) {
++		kfree(tx_pkts);
++	}
++	if (tx_report) {
++		kfree(tx_report);
++	}
++	dhdp->dbg->pkt_mon.tx_report = NULL;
++	dhdp->dbg->pkt_mon.tx_report->tx_pkts = NULL;
++	dhdp->dbg->pkt_mon.tx_pkt_mon = NULL;
++	dhdp->dbg->pkt_mon.tx_status_mon = NULL;
++	dhdp->dbg->pkt_mon.tx_pkt_state = PKT_MON_DETACHED;
++	dhdp->dbg->pkt_mon.tx_status_state = PKT_MON_DETACHED;
++
++	/* rx packet monitoring */
++	if (rx_pkts) {
++		kfree(rx_pkts);
++	}
++	if (rx_report) {
++		kfree(rx_report);
++	}
++	dhdp->dbg->pkt_mon.rx_report = NULL;
++	dhdp->dbg->pkt_mon.rx_report->rx_pkts = NULL;
++	dhdp->dbg->pkt_mon.rx_pkt_mon = NULL;
++	dhdp->dbg->pkt_mon.rx_pkt_state = PKT_MON_DETACHED;
++
++	DHD_PKT_MON_UNLOCK(dhdp->dbg->pkt_mon_lock, flags);
++	DHD_ERROR(("%s(): packet monitor attach failed\n", __FUNCTION__));
++	return ret;
++}
++
++int
++dhd_dbg_start_pkt_monitor(dhd_pub_t *dhdp)
++{
++	dhd_dbg_tx_report_t *tx_report;
++	dhd_dbg_rx_report_t *rx_report;
++	dhd_dbg_pkt_mon_state_t tx_pkt_state;
++	dhd_dbg_pkt_mon_state_t tx_status_state;
++	dhd_dbg_pkt_mon_state_t rx_pkt_state;
++	unsigned long flags;
++
++	DHD_PKT_INFO(("%s, %d\n", __FUNCTION__, __LINE__));
++	if (!dhdp || !dhdp->dbg) {
++		DHD_PKT_MON(("%s(): dhdp=%p, dhdp->dbg=%p\n", __FUNCTION__,
++			dhdp, (dhdp ? dhdp->dbg : NULL)));
++		return -EINVAL;
++	}
++
++	DHD_PKT_MON_LOCK(dhdp->dbg->pkt_mon_lock, flags);
++	tx_pkt_state = dhdp->dbg->pkt_mon.tx_pkt_state;
++	tx_status_state = dhdp->dbg->pkt_mon.tx_status_state;
++	rx_pkt_state = dhdp->dbg->pkt_mon.rx_pkt_state;
++
++	if (PKT_MON_DETACHED(tx_pkt_state) || PKT_MON_DETACHED(tx_status_state) ||
++			PKT_MON_DETACHED(rx_pkt_state)) {
++		DHD_PKT_MON(("%s(): packet monitor is not yet enabled, "
++			"tx_pkt_state=%d, tx_status_state=%d, rx_pkt_state=%d\n",
++			__FUNCTION__, tx_pkt_state, tx_status_state, rx_pkt_state));
++		DHD_PKT_MON_UNLOCK(dhdp->dbg->pkt_mon_lock, flags);
++		return -EINVAL;
++	}
++
++	dhdp->dbg->pkt_mon.tx_pkt_state = PKT_MON_STARTING;
++	dhdp->dbg->pkt_mon.tx_status_state = PKT_MON_STARTING;
++	dhdp->dbg->pkt_mon.rx_pkt_state = PKT_MON_STARTING;
++
++	tx_report = dhdp->dbg->pkt_mon.tx_report;
++	rx_report = dhdp->dbg->pkt_mon.rx_report;
++	if (!tx_report || !rx_report) {
++		DHD_PKT_MON(("%s(): tx_report=%p, rx_report=%p\n",
++			__FUNCTION__, tx_report, rx_report));
++		DHD_PKT_MON_UNLOCK(dhdp->dbg->pkt_mon_lock, flags);
++		return -EINVAL;
++	}
++
++
++	tx_pkt_state = dhdp->dbg->pkt_mon.tx_pkt_state;
++	tx_status_state = dhdp->dbg->pkt_mon.tx_status_state;
++	rx_pkt_state = dhdp->dbg->pkt_mon.rx_pkt_state;
++
++	/* Safe to free packets as state pkt_state is STARTING */
++	__dhd_dbg_free_tx_pkts(dhdp, tx_report->tx_pkts, tx_report->pkt_pos);
++
++	__dhd_dbg_free_rx_pkts(dhdp, rx_report->rx_pkts, rx_report->pkt_pos);
++
++	/* reset array postion */
++	tx_report->pkt_pos = 0;
++	tx_report->status_pos = 0;
++	dhdp->dbg->pkt_mon.tx_pkt_state = PKT_MON_STARTED;
++	dhdp->dbg->pkt_mon.tx_status_state = PKT_MON_STARTED;
++
++	rx_report->pkt_pos = 0;
++	dhdp->dbg->pkt_mon.rx_pkt_state = PKT_MON_STARTED;
++	DHD_PKT_MON_UNLOCK(dhdp->dbg->pkt_mon_lock, flags);
++
++	DHD_PKT_MON(("%s(): packet monitor started\n", __FUNCTION__));
++	return BCME_OK;
++}
++
++int
++dhd_dbg_monitor_tx_pkts(dhd_pub_t *dhdp, void *pkt, uint32 pktid)
++{
++	dhd_dbg_tx_report_t *tx_report;
++	dhd_dbg_tx_info_t *tx_pkts;
++	dhd_dbg_pkt_mon_state_t tx_pkt_state;
++	uint32 pkt_hash, driver_ts;
++	uint16 pkt_pos;
++	unsigned long flags;
++
++	if (!dhdp || !dhdp->dbg) {
++		DHD_PKT_MON(("%s(): dhdp=%p, dhdp->dbg=%p\n", __FUNCTION__,
++			dhdp, (dhdp ? dhdp->dbg : NULL)));
++		return -EINVAL;
++	}
++
++	DHD_PKT_MON_LOCK(dhdp->dbg->pkt_mon_lock, flags);
++	tx_pkt_state = dhdp->dbg->pkt_mon.tx_pkt_state;
++	if (PKT_MON_STARTED(tx_pkt_state)) {
++		tx_report = dhdp->dbg->pkt_mon.tx_report;
++		pkt_pos = tx_report->pkt_pos;
++
++		if (!PKT_MON_PKT_FULL(pkt_pos)) {
++			tx_pkts = tx_report->tx_pkts;
++			pkt_hash = __dhd_dbg_pkt_hash((uintptr_t)pkt, pktid);
++			driver_ts = __dhd_dbg_driver_ts_usec();
++
++			tx_pkts[pkt_pos].info.pkt = PKTDUP(dhdp->osh, pkt);
++			tx_pkts[pkt_pos].info.pkt_len = PKTLEN(dhdp->osh, pkt);
++			tx_pkts[pkt_pos].info.pkt_hash = pkt_hash;
++			tx_pkts[pkt_pos].info.driver_ts = driver_ts;
++			tx_pkts[pkt_pos].info.firmware_ts = 0U;
++			tx_pkts[pkt_pos].info.payload_type = FRAME_TYPE_ETHERNET_II;
++			tx_pkts[pkt_pos].fate = TX_PKT_FATE_DRV_QUEUED;
++
++			tx_report->pkt_pos++;
++		} else {
++			dhdp->dbg->pkt_mon.tx_pkt_state = PKT_MON_STOPPED;
++			DHD_PKT_MON(("%s(): tx pkt logging stopped, reached "
++				"max limit\n", __FUNCTION__));
++		}
++	}
++
++	DHD_PKT_MON_UNLOCK(dhdp->dbg->pkt_mon_lock, flags);
++	return BCME_OK;
++}
++
++int
++dhd_dbg_monitor_tx_status(dhd_pub_t *dhdp, void *pkt, uint32 pktid,
++		uint16 status)
++{
++	dhd_dbg_tx_report_t *tx_report;
++	dhd_dbg_tx_info_t *tx_pkt;
++	dhd_dbg_pkt_mon_state_t tx_status_state;
++	wifi_tx_packet_fate pkt_fate;
++	uint32 pkt_hash, temp_hash;
++	uint16 pkt_pos, status_pos;
++	int16 count;
++	bool found = FALSE;
++	unsigned long flags;
++
++	if (!dhdp || !dhdp->dbg) {
++		DHD_PKT_MON(("%s(): dhdp=%p, dhdp->dbg=%p\n", __FUNCTION__,
++			dhdp, (dhdp ? dhdp->dbg : NULL)));
++		return -EINVAL;
++	}
++
++	DHD_PKT_MON_LOCK(dhdp->dbg->pkt_mon_lock, flags);
++	tx_status_state = dhdp->dbg->pkt_mon.tx_status_state;
++	if (PKT_MON_STARTED(tx_status_state)) {
++		tx_report = dhdp->dbg->pkt_mon.tx_report;
++		pkt_pos = tx_report->pkt_pos;
++		status_pos = tx_report->status_pos;
++
++		if (!PKT_MON_STATUS_FULL(pkt_pos, status_pos)) {
++			pkt_hash = __dhd_dbg_pkt_hash((uintptr_t)pkt, pktid);
++			pkt_fate = __dhd_dbg_map_tx_status_to_pkt_fate(status);
++
++			/* best bet (in-order tx completion) */
++			count = status_pos;
++			tx_pkt = (((dhd_dbg_tx_info_t *)tx_report->tx_pkts) + status_pos);
++			while ((count < pkt_pos) && tx_pkt) {
++				temp_hash = tx_pkt->info.pkt_hash;
++				if (temp_hash == pkt_hash) {
++					tx_pkt->fate = pkt_fate;
++					tx_report->status_pos++;
++					found = TRUE;
++					break;
++				}
++				tx_pkt++;
++				count++;
++			}
++
++			/* search until beginning (handles out-of-order completion) */
++			if (!found) {
++				count = status_pos - 1;
++				tx_pkt = (((dhd_dbg_tx_info_t *)tx_report->tx_pkts) + count);
++				while ((count >= 0) && tx_pkt) {
++					temp_hash = tx_pkt->info.pkt_hash;
++					if (temp_hash == pkt_hash) {
++						tx_pkt->fate = pkt_fate;
++						tx_report->status_pos++;
++						found = TRUE;
++						break;
++					}
++					tx_pkt--;
++					count--;
++				}
++
++				if (!found) {
++					/* still couldn't match tx_status */
++					DHD_ERROR(("%s(): couldn't match tx_status, pkt_pos=%u, "
++						"status_pos=%u, pkt_fate=%u\n", __FUNCTION__,
++						pkt_pos, status_pos, pkt_fate));
++				}
++			}
++		} else {
++			dhdp->dbg->pkt_mon.tx_status_state = PKT_MON_STOPPED;
++			DHD_PKT_MON(("%s(): tx_status logging stopped, reached "
++				"max limit\n", __FUNCTION__));
++		}
++	}
++
++	DHD_PKT_MON_UNLOCK(dhdp->dbg->pkt_mon_lock, flags);
++	return BCME_OK;
++}
++
++int
++dhd_dbg_monitor_rx_pkts(dhd_pub_t *dhdp, void *pkt)
++{
++	dhd_dbg_rx_report_t *rx_report;
++	dhd_dbg_rx_info_t *rx_pkts;
++	dhd_dbg_pkt_mon_state_t rx_pkt_state;
++	uint32 driver_ts;
++	uint16 pkt_pos;
++	unsigned long flags;
++
++	if (!dhdp || !dhdp->dbg) {
++		DHD_PKT_MON(("%s(): dhdp=%p, dhdp->dbg=%p\n", __FUNCTION__,
++			dhdp, (dhdp ? dhdp->dbg : NULL)));
++		return -EINVAL;
++	}
++
++	DHD_PKT_MON_LOCK(dhdp->dbg->pkt_mon_lock, flags);
++	rx_pkt_state = dhdp->dbg->pkt_mon.rx_pkt_state;
++	if (PKT_MON_STARTED(rx_pkt_state)) {
++		rx_report = dhdp->dbg->pkt_mon.rx_report;
++		pkt_pos = rx_report->pkt_pos;
++
++		if (!PKT_MON_PKT_FULL(pkt_pos)) {
++			rx_pkts = rx_report->rx_pkts;
++			driver_ts = __dhd_dbg_driver_ts_usec();
++
++			rx_pkts[pkt_pos].info.pkt = PKTDUP(dhdp->osh, pkt);
++			rx_pkts[pkt_pos].info.pkt_len = PKTLEN(dhdp->osh, pkt);
++			rx_pkts[pkt_pos].info.pkt_hash = 0U;
++			rx_pkts[pkt_pos].info.driver_ts = driver_ts;
++			rx_pkts[pkt_pos].info.firmware_ts = 0U;
++			rx_pkts[pkt_pos].info.payload_type = FRAME_TYPE_ETHERNET_II;
++			rx_pkts[pkt_pos].fate = RX_PKT_FATE_SUCCESS;
++
++			rx_report->pkt_pos++;
++		} else {
++			dhdp->dbg->pkt_mon.rx_pkt_state = PKT_MON_STOPPED;
++			DHD_PKT_MON(("%s(): rx pkt logging stopped, reached "
++					"max limit\n", __FUNCTION__));
++		}
++	}
++
++	DHD_PKT_MON_UNLOCK(dhdp->dbg->pkt_mon_lock, flags);
++	return BCME_OK;
++}
++
++int
++dhd_dbg_stop_pkt_monitor(dhd_pub_t *dhdp)
++{
++	dhd_dbg_pkt_mon_state_t tx_pkt_state;
++	dhd_dbg_pkt_mon_state_t tx_status_state;
++	dhd_dbg_pkt_mon_state_t rx_pkt_state;
++	unsigned long flags;
++
++	DHD_PKT_INFO(("%s, %d\n", __FUNCTION__, __LINE__));
++	if (!dhdp || !dhdp->dbg) {
++		DHD_PKT_MON(("%s(): dhdp=%p, dhdp->dbg=%p\n", __FUNCTION__,
++			dhdp, (dhdp ? dhdp->dbg : NULL)));
++		return -EINVAL;
++	}
++
++	DHD_PKT_MON_LOCK(dhdp->dbg->pkt_mon_lock, flags);
++	tx_pkt_state = dhdp->dbg->pkt_mon.tx_pkt_state;
++	tx_status_state = dhdp->dbg->pkt_mon.tx_status_state;
++	rx_pkt_state = dhdp->dbg->pkt_mon.rx_pkt_state;
++
++	if (PKT_MON_DETACHED(tx_pkt_state) || PKT_MON_DETACHED(tx_status_state) ||
++			PKT_MON_DETACHED(rx_pkt_state)) {
++		DHD_PKT_MON(("%s(): packet monitor is not yet enabled, "
++			"tx_pkt_state=%d, tx_status_state=%d, rx_pkt_state=%d\n",
++			__FUNCTION__, tx_pkt_state, tx_status_state, rx_pkt_state));
++		DHD_PKT_MON_UNLOCK(dhdp->dbg->pkt_mon_lock, flags);
++		return -EINVAL;
++	}
++	dhdp->dbg->pkt_mon.tx_pkt_state = PKT_MON_STOPPED;
++	dhdp->dbg->pkt_mon.tx_status_state = PKT_MON_STOPPED;
++	dhdp->dbg->pkt_mon.rx_pkt_state = PKT_MON_STOPPED;
++	DHD_PKT_MON_UNLOCK(dhdp->dbg->pkt_mon_lock, flags);
++
++	DHD_PKT_MON(("%s(): packet monitor stopped\n", __FUNCTION__));
++	return BCME_OK;
++}
++
++#define __COPY_TO_USER(to, from, n) \
++	do { \
++		int __ret; \
++		__ret = copy_to_user((void __user *)(to), (void *)(from), \
++				(unsigned long)(n)); \
++		if (unlikely(__ret)) { \
++			DHD_ERROR(("%s():%d: copy_to_user failed, ret=%d\n", \
++				__FUNCTION__, __LINE__, __ret)); \
++			return __ret; \
++		} \
++	} while (0);
++
++int
++dhd_dbg_monitor_get_tx_pkts(dhd_pub_t *dhdp, void __user *user_buf,
++		uint16 req_count, uint16 *resp_count)
++{
++	dhd_dbg_tx_report_t *tx_report;
++	dhd_dbg_tx_info_t *tx_pkt;
++	wifi_tx_report_t *ptr;
++	compat_wifi_tx_report_t *cptr;
++	dhd_dbg_pkt_mon_state_t tx_pkt_state;
++	dhd_dbg_pkt_mon_state_t tx_status_state;
++	uint16 pkt_count, count;
++	unsigned long flags;
++
++	DHD_PKT_INFO(("%s, %d\n", __FUNCTION__, __LINE__));
++	BCM_REFERENCE(ptr);
++	BCM_REFERENCE(cptr);
++
++	if (!dhdp || !dhdp->dbg) {
++		DHD_PKT_MON(("%s(): dhdp=%p, dhdp->dbg=%p\n", __FUNCTION__,
++			dhdp, (dhdp ? dhdp->dbg : NULL)));
++		return -EINVAL;
++	}
++
++	DHD_PKT_MON_LOCK(dhdp->dbg->pkt_mon_lock, flags);
++	tx_pkt_state = dhdp->dbg->pkt_mon.tx_pkt_state;
++	tx_status_state = dhdp->dbg->pkt_mon.tx_status_state;
++	if (PKT_MON_DETACHED(tx_pkt_state) || PKT_MON_DETACHED(tx_status_state)) {
++		DHD_PKT_MON(("%s(): packet monitor is not yet enabled, "
++			"tx_pkt_state=%d, tx_status_state=%d\n", __FUNCTION__,
++			tx_pkt_state, tx_status_state));
++		DHD_PKT_MON_UNLOCK(dhdp->dbg->pkt_mon_lock, flags);
++		return -EINVAL;
++	}
++
++	count = 0;
++	tx_report = dhdp->dbg->pkt_mon.tx_report;
++	tx_pkt = tx_report->tx_pkts;
++	pkt_count = MIN(req_count, tx_report->status_pos);
++
++#ifdef CONFIG_COMPAT
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 6, 0))
++	if (in_compat_syscall())
++#else
++	if (is_compat_task())
++#endif
++	{
++		cptr = (compat_wifi_tx_report_t *)user_buf;
++		while ((count < pkt_count) && tx_pkt && cptr) {
++			compat_wifi_tx_report_t *comp_ptr = compat_ptr((uintptr_t) cptr);
++			compat_dhd_dbg_pkt_info_t compat_tx_pkt;
++			__dhd_dbg_dump_tx_pkt_info(dhdp, tx_pkt, count);
++			__COPY_TO_USER(&comp_ptr->fate, &tx_pkt->fate, sizeof(tx_pkt->fate));
++
++			compat_tx_pkt.payload_type = tx_pkt->info.payload_type;
++			compat_tx_pkt.pkt_len = tx_pkt->info.pkt_len;
++			compat_tx_pkt.driver_ts = tx_pkt->info.driver_ts;
++			compat_tx_pkt.firmware_ts = tx_pkt->info.firmware_ts;
++			compat_tx_pkt.pkt_hash = tx_pkt->info.pkt_hash;
++			__COPY_TO_USER(&comp_ptr->frame_inf.payload_type,
++				&compat_tx_pkt.payload_type,
++				OFFSETOF(compat_dhd_dbg_pkt_info_t, pkt_hash));
++			__COPY_TO_USER(comp_ptr->frame_inf.frame_content.ethernet_ii,
++				PKTDATA(dhdp->osh, tx_pkt->info.pkt), tx_pkt->info.pkt_len);
++
++			cptr++;
++			tx_pkt++;
++			count++;
++		}
++	} else
++#endif /* CONFIG_COMPAT */
++
++	{
++		ptr = (wifi_tx_report_t *)user_buf;
++		while ((count < pkt_count) && tx_pkt && ptr) {
++			__dhd_dbg_dump_tx_pkt_info(dhdp, tx_pkt, count);
++			__COPY_TO_USER(&ptr->fate, &tx_pkt->fate, sizeof(tx_pkt->fate));
++			__COPY_TO_USER(&ptr->frame_inf.payload_type,
++				&tx_pkt->info.payload_type,
++				OFFSETOF(dhd_dbg_pkt_info_t, pkt_hash));
++			__COPY_TO_USER(ptr->frame_inf.frame_content.ethernet_ii,
++				PKTDATA(dhdp->osh, tx_pkt->info.pkt), tx_pkt->info.pkt_len);
++
++			ptr++;
++			tx_pkt++;
++			count++;
++		}
++	}
++	*resp_count = pkt_count;
++
++	DHD_PKT_MON_UNLOCK(dhdp->dbg->pkt_mon_lock, flags);
++	if (!pkt_count) {
++		DHD_ERROR(("%s(): no tx_status in tx completion messages, "
++			"make sure that 'd11status' is enabled in firmware, "
++			"status_pos=%u\n", __FUNCTION__, pkt_count));
++	}
++
++	return BCME_OK;
++}
++
++int
++dhd_dbg_monitor_get_rx_pkts(dhd_pub_t *dhdp, void __user *user_buf,
++		uint16 req_count, uint16 *resp_count)
++{
++	dhd_dbg_rx_report_t *rx_report;
++	dhd_dbg_rx_info_t *rx_pkt;
++	wifi_rx_report_t *ptr;
++	compat_wifi_rx_report_t *cptr;
++	dhd_dbg_pkt_mon_state_t rx_pkt_state;
++	uint16 pkt_count, count;
++	unsigned long flags;
++
++	DHD_PKT_INFO(("%s, %d\n", __FUNCTION__, __LINE__));
++	BCM_REFERENCE(ptr);
++	BCM_REFERENCE(cptr);
++
++	if (!dhdp || !dhdp->dbg) {
++		DHD_PKT_MON(("%s(): dhdp=%p, dhdp->dbg=%p\n", __FUNCTION__,
++			dhdp, (dhdp ? dhdp->dbg : NULL)));
++		return -EINVAL;
++	}
++
++	DHD_PKT_MON_LOCK(dhdp->dbg->pkt_mon_lock, flags);
++	rx_pkt_state = dhdp->dbg->pkt_mon.rx_pkt_state;
++	if (PKT_MON_DETACHED(rx_pkt_state)) {
++		DHD_PKT_MON(("%s(): packet fetch is not allowed , "
++			"rx_pkt_state=%d\n", __FUNCTION__, rx_pkt_state));
++		DHD_PKT_MON_UNLOCK(dhdp->dbg->pkt_mon_lock, flags);
++		return -EINVAL;
++	}
++
++	count = 0;
++	rx_report = dhdp->dbg->pkt_mon.rx_report;
++	rx_pkt = rx_report->rx_pkts;
++	pkt_count = MIN(req_count, rx_report->pkt_pos);
++
++#ifdef CONFIG_COMPAT
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 6, 0))
++	if (in_compat_syscall())
++#else
++	if (is_compat_task())
++#endif
++	{
++		cptr = (compat_wifi_rx_report_t *)user_buf;
++		while ((count < pkt_count) && rx_pkt && cptr) {
++			compat_wifi_rx_report_t *comp_ptr = compat_ptr((uintptr_t) cptr);
++			compat_dhd_dbg_pkt_info_t compat_rx_pkt;
++			__dhd_dbg_dump_rx_pkt_info(dhdp, rx_pkt, count);
++			__COPY_TO_USER(&comp_ptr->fate, &rx_pkt->fate, sizeof(rx_pkt->fate));
++
++			compat_rx_pkt.payload_type = rx_pkt->info.payload_type;
++			compat_rx_pkt.pkt_len = rx_pkt->info.pkt_len;
++			compat_rx_pkt.driver_ts = rx_pkt->info.driver_ts;
++			compat_rx_pkt.firmware_ts = rx_pkt->info.firmware_ts;
++			compat_rx_pkt.pkt_hash = rx_pkt->info.pkt_hash;
++			__COPY_TO_USER(&comp_ptr->frame_inf.payload_type,
++				&compat_rx_pkt.payload_type,
++				OFFSETOF(compat_dhd_dbg_pkt_info_t, pkt_hash));
++			__COPY_TO_USER(comp_ptr->frame_inf.frame_content.ethernet_ii,
++				PKTDATA(dhdp->osh, rx_pkt->info.pkt), rx_pkt->info.pkt_len);
++
++			cptr++;
++			rx_pkt++;
++			count++;
++		}
++	} else
++#endif /* CONFIG_COMPAT */
++	{
++		ptr = (wifi_rx_report_t *)user_buf;
++		while ((count < pkt_count) && rx_pkt && ptr) {
++			__dhd_dbg_dump_rx_pkt_info(dhdp, rx_pkt, count);
++
++			__COPY_TO_USER(&ptr->fate, &rx_pkt->fate, sizeof(rx_pkt->fate));
++			__COPY_TO_USER(&ptr->frame_inf.payload_type,
++				&rx_pkt->info.payload_type,
++				OFFSETOF(dhd_dbg_pkt_info_t, pkt_hash));
++			__COPY_TO_USER(ptr->frame_inf.frame_content.ethernet_ii,
++				PKTDATA(dhdp->osh, rx_pkt->info.pkt), rx_pkt->info.pkt_len);
++
++			ptr++;
++			rx_pkt++;
++			count++;
++		}
++	}
++
++	*resp_count = pkt_count;
++	DHD_PKT_MON_UNLOCK(dhdp->dbg->pkt_mon_lock, flags);
++
++	return BCME_OK;
++}
++
++int
++dhd_dbg_detach_pkt_monitor(dhd_pub_t *dhdp)
++{
++	dhd_dbg_tx_report_t *tx_report;
++	dhd_dbg_rx_report_t *rx_report;
++	dhd_dbg_pkt_mon_state_t tx_pkt_state;
++	dhd_dbg_pkt_mon_state_t tx_status_state;
++	dhd_dbg_pkt_mon_state_t rx_pkt_state;
++	unsigned long flags;
++
++	DHD_PKT_INFO(("%s, %d\n", __FUNCTION__, __LINE__));
++	if (!dhdp || !dhdp->dbg) {
++		DHD_PKT_MON(("%s(): dhdp=%p, dhdp->dbg=%p\n", __FUNCTION__,
++			dhdp, (dhdp ? dhdp->dbg : NULL)));
++		return -EINVAL;
++	}
++
++	DHD_PKT_MON_LOCK(dhdp->dbg->pkt_mon_lock, flags);
++	tx_pkt_state = dhdp->dbg->pkt_mon.tx_pkt_state;
++	tx_status_state = dhdp->dbg->pkt_mon.tx_status_state;
++	rx_pkt_state = dhdp->dbg->pkt_mon.rx_pkt_state;
++
++	if (PKT_MON_DETACHED(tx_pkt_state) || PKT_MON_DETACHED(tx_status_state) ||
++			PKT_MON_DETACHED(rx_pkt_state)) {
++		DHD_PKT_MON(("%s(): packet monitor is already detached, "
++			"tx_pkt_state=%d, tx_status_state=%d, rx_pkt_state=%d\n",
++			__FUNCTION__, tx_pkt_state, tx_status_state, rx_pkt_state));
++		DHD_PKT_MON_UNLOCK(dhdp->dbg->pkt_mon_lock, flags);
++		return -EINVAL;
++	}
++
++	tx_report = dhdp->dbg->pkt_mon.tx_report;
++	rx_report = dhdp->dbg->pkt_mon.rx_report;
++
++	/* free and de-initalize tx packet monitoring */
++	dhdp->dbg->pkt_mon.tx_pkt_state = PKT_MON_DETACHED;
++	dhdp->dbg->pkt_mon.tx_status_state = PKT_MON_DETACHED;
++	if (tx_report) {
++		if (tx_report->tx_pkts) {
++			__dhd_dbg_free_tx_pkts(dhdp, tx_report->tx_pkts,
++				tx_report->pkt_pos);
++			kfree(tx_report->tx_pkts);
++			dhdp->dbg->pkt_mon.tx_report->tx_pkts = NULL;
++		}
++		kfree(tx_report);
++		dhdp->dbg->pkt_mon.tx_report = NULL;
++	}
++	dhdp->dbg->pkt_mon.tx_pkt_mon = NULL;
++	dhdp->dbg->pkt_mon.tx_status_mon = NULL;
++
++	/* free and de-initalize rx packet monitoring */
++	dhdp->dbg->pkt_mon.rx_pkt_state = PKT_MON_DETACHED;
++	if (rx_report) {
++		if (rx_report->rx_pkts) {
++			__dhd_dbg_free_rx_pkts(dhdp, rx_report->rx_pkts,
++				rx_report->pkt_pos);
++			kfree(rx_report->rx_pkts);
++			dhdp->dbg->pkt_mon.rx_report->rx_pkts = NULL;
++		}
++		kfree(rx_report);
++		dhdp->dbg->pkt_mon.rx_report = NULL;
++	}
++	dhdp->dbg->pkt_mon.rx_pkt_mon = NULL;
++
++	DHD_PKT_MON_UNLOCK(dhdp->dbg->pkt_mon_lock, flags);
++	DHD_PKT_MON(("%s(): packet monitor detach succeeded\n", __FUNCTION__));
++	return BCME_OK;
++}
++#endif /* DBG_PKT_MON */
++
++/*
++ * dhd_dbg_attach: initialziation of dhd dbugability module
++ *
++ * Return: An error code or 0 on success.
++ */
++int
++dhd_dbg_attach(dhd_pub_t *dhdp, dbg_pullreq_t os_pullreq,
++	dbg_urgent_noti_t os_urgent_notifier, void *os_priv)
++{
++	dhd_dbg_t *dbg;
++	int ret, ring_id;
++
++	dbg = MALLOCZ(dhdp->osh, sizeof(dhd_dbg_t));
++	if (!dbg)
++		return BCME_NOMEM;
++
++	ret = dhd_dbg_ring_init(dhdp, &dbg->dbg_rings[FW_VERBOSE_RING_ID], FW_VERBOSE_RING_ID,
++			(uint8 *)FW_VERBOSE_RING_NAME, FW_VERBOSE_RING_SIZE, DHD_PREALLOC_FW_VERBOSE_RING);
++	if (ret)
++		goto error;
++
++	ret = dhd_dbg_ring_init(dhdp, &dbg->dbg_rings[FW_EVENT_RING_ID], FW_EVENT_RING_ID,
++			(uint8 *)FW_EVENT_RING_NAME, FW_EVENT_RING_SIZE, DHD_PREALLOC_FW_EVENT_RING);
++	if (ret)
++		goto error;
++
++	ret = dhd_dbg_ring_init(dhdp, &dbg->dbg_rings[DHD_EVENT_RING_ID], DHD_EVENT_RING_ID,
++			(uint8 *)DHD_EVENT_RING_NAME, DHD_EVENT_RING_SIZE, DHD_PREALLOC_DHD_EVENT_RING);
++	if (ret)
++		goto error;
++
++	ret = dhd_dbg_ring_init(dhdp, &dbg->dbg_rings[NAN_EVENT_RING_ID], NAN_EVENT_RING_ID,
++			(uint8 *)NAN_EVENT_RING_NAME, NAN_EVENT_RING_SIZE, DHD_PREALLOC_NAN_EVENT_RING);
++	if (ret)
++		goto error;
++
++	dbg->private = os_priv;
++	dbg->pullreq = os_pullreq;
++	dbg->urgent_notifier = os_urgent_notifier;
++	dhdp->dbg = dbg;
++
++	return BCME_OK;
++
++error:
++	for (ring_id = DEBUG_RING_ID_INVALID + 1; ring_id < DEBUG_RING_ID_MAX; ring_id++) {
++		if (VALID_RING(dbg->dbg_rings[ring_id].id)) {
++			dhd_dbg_ring_deinit(dhdp, &dbg->dbg_rings[ring_id]);
++		}
++	}
++	MFREE(dhdp->osh, dhdp->dbg, sizeof(dhd_dbg_t));
++
++	return ret;
++}
++
++/*
++ * dhd_dbg_detach: clean up dhd dbugability module
++ */
++void
++dhd_dbg_detach(dhd_pub_t *dhdp)
++{
++	int ring_id;
++	dhd_dbg_t *dbg;
++	if (!dhdp->dbg)
++		return;
++	dbg = dhdp->dbg;
++	for (ring_id = DEBUG_RING_ID_INVALID + 1; ring_id < DEBUG_RING_ID_MAX; ring_id++) {
++		if (VALID_RING(dbg->dbg_rings[ring_id].id)) {
++			dhd_dbg_ring_deinit(dhdp, &dbg->dbg_rings[ring_id]);
++		}
++	}
++	MFREE(dhdp->osh, dhdp->dbg, sizeof(dhd_dbg_t));
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_debug.h b/module_drivers/drivers/net/wireless/bcmdhd/dhd_debug.h
+new file mode 100644
+index 000000000..933711371
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_debug.h
+@@ -0,0 +1,868 @@
++/*
++ * DHD debugability header file
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * $Id: dhd_debug.h 705824 2017-06-19 13:58:39Z $
++ */
++
++#ifndef _dhd_debug_h_
++#define _dhd_debug_h_
++#include <event_log.h>
++#include <bcmutils.h>
++
++enum {
++	DEBUG_RING_ID_INVALID	= 0,
++	FW_VERBOSE_RING_ID,
++	FW_EVENT_RING_ID,
++	DHD_EVENT_RING_ID,
++	NAN_EVENT_RING_ID,
++	/* add new id here */
++	DEBUG_RING_ID_MAX
++};
++
++enum {
++	/* Feature set */
++	DBG_MEMORY_DUMP_SUPPORTED = (1 << (0)), /* Memory dump of FW */
++	DBG_PER_PACKET_TX_RX_STATUS_SUPPORTED = (1 << (1)), /* PKT Status */
++	DBG_CONNECT_EVENT_SUPPORTED = (1 << (2)), /* Connectivity Event */
++	DBG_POWER_EVENT_SUPOORTED = (1 << (3)), /* POWER of Driver */
++	DBG_WAKE_LOCK_SUPPORTED = (1 << (4)), /* WAKE LOCK of Driver */
++	DBG_VERBOSE_LOG_SUPPORTED = (1 << (5)), /* verbose log of FW */
++	DBG_HEALTH_CHECK_SUPPORTED = (1 << (6)), /* monitor the health of FW */
++	DBG_DRIVER_DUMP_SUPPORTED = (1 << (7)), /* dumps driver state */
++	DBG_PACKET_FATE_SUPPORTED = (1 << (8)), /* tracks connection packets' fate */
++	DBG_NAN_EVENT_SUPPORTED = (1 << (9)), /* NAN Events */
++};
++
++enum {
++	/* set for binary entries */
++	DBG_RING_ENTRY_FLAGS_HAS_BINARY = (1 << (0)),
++	/* set if 64 bits timestamp is present */
++	DBG_RING_ENTRY_FLAGS_HAS_TIMESTAMP = (1 << (1))
++};
++
++#define DBGRING_NAME_MAX		32
++/* firmware verbose ring, ring id 1 */
++#define FW_VERBOSE_RING_NAME		"fw_verbose"
++#define FW_VERBOSE_RING_SIZE		(64 * 1024)
++/* firmware event ring, ring id 2 */
++#define FW_EVENT_RING_NAME		"fw_event"
++#define FW_EVENT_RING_SIZE		(64 * 1024)
++/* DHD connection event ring, ring id 3 */
++#define DHD_EVENT_RING_NAME		"dhd_event"
++#define DHD_EVENT_RING_SIZE		(64 * 1024)
++
++/* NAN event ring, ring id 4 */
++#define NAN_EVENT_RING_NAME		"nan_event"
++#define NAN_EVENT_RING_SIZE		(64 * 1024)
++
++#define TLV_LOG_SIZE(tlv) ((tlv) ? (sizeof(tlv_log) + (tlv)->len) : 0)
++
++#define TLV_LOG_NEXT(tlv) \
++	((tlv) ? ((tlv_log *)((uint8 *)tlv + TLV_LOG_SIZE(tlv))) : 0)
++
++#define DBG_RING_STATUS_SIZE (sizeof(dhd_dbg_ring_status_t))
++
++#define VALID_RING(id)	\
++	((id > DEBUG_RING_ID_INVALID) && (id < DEBUG_RING_ID_MAX))
++
++#ifdef DEBUGABILITY
++#define DBG_RING_ACTIVE(dhdp, ring_id) \
++	((dhdp)->dbg->dbg_rings[(ring_id)].state == RING_ACTIVE)
++#else
++#define DBG_RING_ACTIVE(dhdp, ring_id) 0
++#endif /* DEBUGABILITY */
++
++#define TXACTIVESZ(r, w, d)			(((r) <= (w)) ? ((w) - (r)) : ((d) - (r) + (w)))
++#define DBG_RING_READ_AVAIL_SPACE(w, r, d)	(((w) >= (r)) ? ((w) - (r)) : ((d) - (r)))
++#define DBG_RING_WRITE_SPACE_AVAIL_CONT(r, w, d)	(((w) >= (r)) ? ((d) - (w)) : ((r) - (w)))
++#define DBG_RING_WRITE_SPACE_AVAIL(r, w, d)	(d - (TXACTIVESZ(r, w, d)))
++#define DBG_RING_CHECK_WRITE_SPACE(r, w, d)	\
++	MIN(DBG_RING_WRITE_SPACE_AVAIL(r, w, d), DBG_RING_WRITE_SPACE_AVAIL_CONT(r, w, d))
++
++enum {
++	/* driver receive association command from kernel */
++	WIFI_EVENT_ASSOCIATION_REQUESTED	= 0,
++	WIFI_EVENT_AUTH_COMPLETE,
++	WIFI_EVENT_ASSOC_COMPLETE,
++	/* received firmware event indicating auth frames are sent */
++	WIFI_EVENT_FW_AUTH_STARTED,
++	/* received firmware event indicating assoc frames are sent */
++	WIFI_EVENT_FW_ASSOC_STARTED,
++	/* received firmware event indicating reassoc frames are sent */
++	WIFI_EVENT_FW_RE_ASSOC_STARTED,
++	WIFI_EVENT_DRIVER_SCAN_REQUESTED,
++	WIFI_EVENT_DRIVER_SCAN_RESULT_FOUND,
++	WIFI_EVENT_DRIVER_SCAN_COMPLETE,
++	WIFI_EVENT_G_SCAN_STARTED,
++	WIFI_EVENT_G_SCAN_COMPLETE,
++	WIFI_EVENT_DISASSOCIATION_REQUESTED,
++	WIFI_EVENT_RE_ASSOCIATION_REQUESTED,
++	WIFI_EVENT_ROAM_REQUESTED,
++	/* received beacon from AP (event enabled only in verbose mode) */
++	WIFI_EVENT_BEACON_RECEIVED,
++	/* firmware has triggered a roam scan (not g-scan) */
++	WIFI_EVENT_ROAM_SCAN_STARTED,
++	/* firmware has completed a roam scan (not g-scan) */
++	WIFI_EVENT_ROAM_SCAN_COMPLETE,
++	/* firmware has started searching for roam candidates (with reason =xx) */
++	WIFI_EVENT_ROAM_SEARCH_STARTED,
++	/* firmware has stopped searching for roam candidates (with reason =xx) */
++	WIFI_EVENT_ROAM_SEARCH_STOPPED,
++	WIFI_EVENT_UNUSED_0,
++	/* received channel switch anouncement from AP */
++	WIFI_EVENT_CHANNEL_SWITCH_ANOUNCEMENT,
++	/* fw start transmit eapol frame, with EAPOL index 1-4 */
++	WIFI_EVENT_FW_EAPOL_FRAME_TRANSMIT_START,
++	/* fw gives up eapol frame, with rate, success/failure and number retries */
++	WIFI_EVENT_FW_EAPOL_FRAME_TRANSMIT_STOP,
++	/* kernel queue EAPOL for transmission in driver with EAPOL index 1-4 */
++	WIFI_EVENT_DRIVER_EAPOL_FRAME_TRANSMIT_REQUESTED,
++	/* with rate, regardless of the fact that EAPOL frame is accepted or
++	 * rejected by firmware
++	 */
++	WIFI_EVENT_FW_EAPOL_FRAME_RECEIVED,
++	WIFI_EVENT_UNUSED_1,
++	/* with rate, and eapol index, driver has received */
++	/* EAPOL frame and will queue it up to wpa_supplicant */
++	WIFI_EVENT_DRIVER_EAPOL_FRAME_RECEIVED,
++	/* with success/failure, parameters */
++	WIFI_EVENT_BLOCK_ACK_NEGOTIATION_COMPLETE,
++	WIFI_EVENT_BT_COEX_BT_SCO_START,
++	WIFI_EVENT_BT_COEX_BT_SCO_STOP,
++	/* for paging/scan etc..., when BT starts transmiting twice per BT slot */
++	WIFI_EVENT_BT_COEX_BT_SCAN_START,
++	WIFI_EVENT_BT_COEX_BT_SCAN_STOP,
++	WIFI_EVENT_BT_COEX_BT_HID_START,
++	WIFI_EVENT_BT_COEX_BT_HID_STOP,
++	/* firmware sends auth frame in roaming to next candidate */
++	WIFI_EVENT_ROAM_AUTH_STARTED,
++	/* firmware receive auth confirm from ap */
++	WIFI_EVENT_ROAM_AUTH_COMPLETE,
++	/* firmware sends assoc/reassoc frame in */
++	WIFI_EVENT_ROAM_ASSOC_STARTED,
++	/* firmware receive assoc/reassoc confirm from ap */
++	WIFI_EVENT_ROAM_ASSOC_COMPLETE,
++	/* firmware sends stop G_SCAN */
++	WIFI_EVENT_G_SCAN_STOP,
++	/* firmware indicates G_SCAN scan cycle started */
++	WIFI_EVENT_G_SCAN_CYCLE_STARTED,
++	/* firmware indicates G_SCAN scan cycle completed */
++	WIFI_EVENT_G_SCAN_CYCLE_COMPLETED,
++	/* firmware indicates G_SCAN scan start for a particular bucket */
++	WIFI_EVENT_G_SCAN_BUCKET_STARTED,
++	/* firmware indicates G_SCAN scan completed for particular bucket */
++	WIFI_EVENT_G_SCAN_BUCKET_COMPLETED,
++	/* Event received from firmware about G_SCAN scan results being available */
++	WIFI_EVENT_G_SCAN_RESULTS_AVAILABLE,
++	/* Event received from firmware with G_SCAN capabilities */
++	WIFI_EVENT_G_SCAN_CAPABILITIES,
++	/* Event received from firmware when eligible candidate is found */
++	WIFI_EVENT_ROAM_CANDIDATE_FOUND,
++	/* Event received from firmware when roam scan configuration gets enabled or disabled */
++	WIFI_EVENT_ROAM_SCAN_CONFIG,
++	/* firmware/driver timed out authentication */
++	WIFI_EVENT_AUTH_TIMEOUT,
++	/* firmware/driver timed out association */
++	WIFI_EVENT_ASSOC_TIMEOUT,
++	/* firmware/driver encountered allocation failure */
++	WIFI_EVENT_MEM_ALLOC_FAILURE,
++	/* driver added a PNO network in firmware */
++	WIFI_EVENT_DRIVER_PNO_ADD,
++	/* driver removed a PNO network in firmware */
++	WIFI_EVENT_DRIVER_PNO_REMOVE,
++	/* driver received PNO networks found indication from firmware */
++	WIFI_EVENT_DRIVER_PNO_NETWORK_FOUND,
++	/* driver triggered a scan for PNO networks */
++	WIFI_EVENT_DRIVER_PNO_SCAN_REQUESTED,
++	/* driver received scan results of PNO networks */
++	WIFI_EVENT_DRIVER_PNO_SCAN_RESULT_FOUND,
++	/* driver updated scan results from PNO candidates to cfg */
++	WIFI_EVENT_DRIVER_PNO_SCAN_COMPLETE
++};
++
++enum {
++	WIFI_TAG_VENDOR_SPECIFIC = 0, /* take a byte stream as parameter */
++	WIFI_TAG_BSSID, /* takes a 6 bytes MAC address as parameter */
++	WIFI_TAG_ADDR, /* takes a 6 bytes MAC address as parameter */
++	WIFI_TAG_SSID, /* takes a 32 bytes SSID address as parameter */
++	WIFI_TAG_STATUS, /* takes an integer as parameter */
++	WIFI_TAG_CHANNEL_SPEC, /* takes one or more wifi_channel_spec as parameter */
++	WIFI_TAG_WAKE_LOCK_EVENT, /* takes a wake_lock_event struct as parameter */
++	WIFI_TAG_ADDR1, /* takes a 6 bytes MAC address as parameter */
++	WIFI_TAG_ADDR2, /* takes a 6 bytes MAC address as parameter */
++	WIFI_TAG_ADDR3, /* takes a 6 bytes MAC address as parameter */
++	WIFI_TAG_ADDR4, /* takes a 6 bytes MAC address as parameter */
++	WIFI_TAG_TSF, /* take a 64 bits TSF value as parameter */
++	WIFI_TAG_IE,
++	/* take one or more specific 802.11 IEs parameter, IEs are in turn
++	 * indicated in TLV format as per 802.11 spec
++	 */
++	WIFI_TAG_INTERFACE,	/* take interface name as parameter */
++	WIFI_TAG_REASON_CODE,	/* take a reason code as per 802.11 as parameter */
++	WIFI_TAG_RATE_MBPS,	/* take a wifi rate in 0.5 mbps */
++	WIFI_TAG_REQUEST_ID,	/* take an integer as parameter */
++	WIFI_TAG_BUCKET_ID,	/* take an integer as parameter */
++	WIFI_TAG_GSCAN_PARAMS,	/* takes a wifi_scan_cmd_params struct as parameter */
++	WIFI_TAG_GSCAN_CAPABILITIES, /* takes a wifi_gscan_capabilities struct as parameter */
++	WIFI_TAG_SCAN_ID,	/* take an integer as parameter */
++	WIFI_TAG_RSSI,		/* takes s16 as parameter */
++	WIFI_TAG_CHANNEL,	/* takes u16 as parameter */
++	WIFI_TAG_LINK_ID,	/* take an integer as parameter */
++	WIFI_TAG_LINK_ROLE,	/* take an integer as parameter */
++	WIFI_TAG_LINK_STATE,	/* take an integer as parameter */
++	WIFI_TAG_LINK_TYPE,	/* take an integer as parameter */
++	WIFI_TAG_TSCO,		/* take an integer as parameter */
++	WIFI_TAG_RSCO,		/* take an integer as parameter */
++	WIFI_TAG_EAPOL_MESSAGE_TYPE /* take an integer as parameter */
++};
++
++/* NAN  events */
++typedef enum {
++	NAN_EVENT_INVALID = 0,
++	NAN_EVENT_CLUSTER_STARTED = 1,
++	NAN_EVENT_CLUSTER_JOINED = 2,
++	NAN_EVENT_CLUSTER_MERGED = 3,
++	NAN_EVENT_ROLE_CHANGED = 4,
++	NAN_EVENT_SCAN_COMPLETE = 5,
++	NAN_EVENT_STATUS_CHNG  = 6,
++	/* ADD new events before this line */
++	NAN_EVENT_MAX
++} nan_event_id_t;
++
++typedef struct {
++    uint16 tag;
++    uint16 len; /* length of value */
++    uint8 value[0];
++} tlv_log;
++
++typedef struct per_packet_status_entry {
++    uint8 flags;
++    uint8 tid; /* transmit or received tid */
++    uint16 MCS; /* modulation and bandwidth */
++	/*
++	* TX: RSSI of ACK for that packet
++	* RX: RSSI of packet
++	*/
++    uint8 rssi;
++    uint8 num_retries; /* number of attempted retries */
++    uint16 last_transmit_rate; /* last transmit rate in .5 mbps */
++	 /* transmit/reeive sequence for that MPDU packet */
++    uint16 link_layer_transmit_sequence;
++	/*
++	* TX: firmware timestamp (us) when packet is queued within firmware buffer
++	* for SDIO/HSIC or into PCIe buffer
++	* RX : firmware receive timestamp
++	*/
++    uint64 firmware_entry_timestamp;
++	/*
++	* firmware timestamp (us) when packet start contending for the
++	* medium for the first time, at head of its AC queue,
++	* or as part of an MPDU or A-MPDU. This timestamp is not updated
++	* for each retry, only the first transmit attempt.
++	*/
++    uint64 start_contention_timestamp;
++	/*
++	* fimrware timestamp (us) when packet is successfully transmitted
++	* or aborted because it has exhausted its maximum number of retries
++	*/
++	uint64 transmit_success_timestamp;
++	/*
++	* packet data. The length of packet data is determined by the entry_size field of
++	* the wifi_ring_buffer_entry structure. It is expected that first bytes of the
++	* packet, or packet headers only (up to TCP or RTP/UDP headers) will be copied into the ring
++	*/
++    uint8 *data;
++} per_packet_status_entry_t;
++
++#define PACKED_STRUCT __attribute__ ((packed))
++typedef struct log_conn_event {
++    uint16 event;
++    tlv_log *tlvs;
++	/*
++	* separate parameter structure per event to be provided and optional data
++	* the event_data is expected to include an official android part, with some
++	* parameter as transmit rate, num retries, num scan result found etc...
++	* as well, event_data can include a vendor proprietary part which is
++	* understood by the developer only.
++	*/
++} PACKED_STRUCT log_conn_event_t;
++
++/*
++ * Ring buffer name for power events ring. note that power event are extremely frequents
++ * and thus should be stored in their own ring/file so as not to clobber connectivity events
++ */
++
++typedef struct wake_lock_event {
++    uint32 status; /* 0 taken, 1 released */
++    uint32 reason; /* reason why this wake lock is taken */
++    char *name; /* null terminated */
++} wake_lock_event_t;
++
++typedef struct wifi_power_event {
++    uint16 event;
++    tlv_log *tlvs;
++} wifi_power_event_t;
++
++#define NAN_EVENT_VERSION 1
++typedef struct log_nan_event {
++    uint8 version;
++    uint8 pad;
++    uint16 event;
++    tlv_log *tlvs;
++} log_nan_event_t;
++
++/* entry type */
++enum {
++	DBG_RING_ENTRY_EVENT_TYPE = 1,
++	DBG_RING_ENTRY_PKT_TYPE,
++	DBG_RING_ENTRY_WAKE_LOCK_EVENT_TYPE,
++	DBG_RING_ENTRY_POWER_EVENT_TYPE,
++	DBG_RING_ENTRY_DATA_TYPE,
++	DBG_RING_ENTRY_NAN_EVENT_TYPE
++};
++
++typedef struct dhd_dbg_ring_entry {
++	uint16 len; /* payload length excluding the header */
++	uint8 flags;
++	uint8 type; /* Per ring specific */
++	uint64 timestamp; /* present if has_timestamp bit is set. */
++} PACKED_STRUCT dhd_dbg_ring_entry_t;
++
++#define DBG_RING_ENTRY_SIZE (sizeof(dhd_dbg_ring_entry_t))
++
++#define ENTRY_LENGTH(hdr) ((hdr)->len + DBG_RING_ENTRY_SIZE)
++
++#define PAYLOAD_MAX_LEN 65535
++
++typedef struct dhd_dbg_ring_status {
++	uint8 name[DBGRING_NAME_MAX];
++	uint32 flags;
++	int ring_id; /* unique integer representing the ring */
++	/* total memory size allocated for the buffer */
++	uint32 ring_buffer_byte_size;
++	uint32 verbose_level;
++	/* number of bytes that was written to the buffer by driver */
++	uint32 written_bytes;
++	/* number of bytes that was read from the buffer by user land */
++	uint32 read_bytes;
++	/* number of records that was read from the buffer by user land */
++	uint32 written_records;
++} dhd_dbg_ring_status_t;
++
++struct log_level_table {
++	int log_level;
++	uint16 tag;
++	uint8 sets;
++	char *desc;
++};
++
++#ifdef DEBUGABILITY
++#define DBG_EVENT_LOG(dhdp, connect_state)					\
++{										\
++	do {									\
++		uint16 state = connect_state;					\
++		if (DBG_RING_ACTIVE(dhdp, DHD_EVENT_RING_ID))			\
++			dhd_os_push_push_ring_data(dhdp, DHD_EVENT_RING_ID,	\
++				&state, sizeof(state));				\
++	} while (0);								\
++}
++#else
++#define DBG_EVENT_LOG(dhdp, connect_state)
++#endif /* DEBUGABILITY */
++
++
++#define MD5_PREFIX_LEN				4
++#define MAX_FATE_LOG_LEN			32
++
++#define MAX_FRAME_LEN_ETHERNET		1518
++#define MAX_FRAME_LEN_80211_MGMT	2352 /* 802.11-2012 Fig. 8-34 */
++
++typedef enum {
++	/* Sent over air and ACKed. */
++	TX_PKT_FATE_ACKED,
++
++	/* Sent over air but not ACKed. (Normal for broadcast/multicast.) */
++	TX_PKT_FATE_SENT,
++
++	/* Queued within firmware, but not yet sent over air. */
++	TX_PKT_FATE_FW_QUEUED,
++
++	/*
++	 * Dropped by firmware as invalid. E.g. bad source address,
++	 * bad checksum, or invalid for current state.
++	 */
++	TX_PKT_FATE_FW_DROP_INVALID,
++
++	/* Dropped by firmware due to lack of buffer space. */
++	TX_PKT_FATE_FW_DROP_NOBUFS,
++
++	/*
++	 * Dropped by firmware for any other reason. Includes
++	 * frames that were sent by driver to firmware, but
++	 * unaccounted for by firmware.
++	 */
++	TX_PKT_FATE_FW_DROP_OTHER,
++
++	/* Queued within driver, not yet sent to firmware. */
++	TX_PKT_FATE_DRV_QUEUED,
++
++	/*
++	 * Dropped by driver as invalid. E.g. bad source address,
++	 * or invalid for current state.
++	 */
++	TX_PKT_FATE_DRV_DROP_INVALID,
++
++	/* Dropped by driver due to lack of buffer space. */
++	TX_PKT_FATE_DRV_DROP_NOBUFS,
++
++	/*  Dropped by driver for any other reason. */
++	TX_PKT_FATE_DRV_DROP_OTHER,
++
++	} wifi_tx_packet_fate;
++
++typedef enum {
++	/* Valid and delivered to network stack (e.g., netif_rx()). */
++	RX_PKT_FATE_SUCCESS,
++
++	/* Queued within firmware, but not yet sent to driver. */
++	RX_PKT_FATE_FW_QUEUED,
++
++	/* Dropped by firmware due to host-programmable filters. */
++	RX_PKT_FATE_FW_DROP_FILTER,
++
++	/*
++	 * Dropped by firmware as invalid. E.g. bad checksum,
++	 * decrypt failed, or invalid for current state.
++	 */
++	RX_PKT_FATE_FW_DROP_INVALID,
++
++	/* Dropped by firmware due to lack of buffer space. */
++	RX_PKT_FATE_FW_DROP_NOBUFS,
++
++	/* Dropped by firmware for any other reason. */
++	RX_PKT_FATE_FW_DROP_OTHER,
++
++	/* Queued within driver, not yet delivered to network stack. */
++	RX_PKT_FATE_DRV_QUEUED,
++
++	/* Dropped by driver due to filter rules. */
++	RX_PKT_FATE_DRV_DROP_FILTER,
++
++	/* Dropped by driver as invalid. E.g. not permitted in current state. */
++	RX_PKT_FATE_DRV_DROP_INVALID,
++
++	/* Dropped by driver due to lack of buffer space. */
++	RX_PKT_FATE_DRV_DROP_NOBUFS,
++
++	/* Dropped by driver for any other reason. */
++	RX_PKT_FATE_DRV_DROP_OTHER,
++
++	} wifi_rx_packet_fate;
++
++typedef enum {
++	FRAME_TYPE_UNKNOWN,
++	FRAME_TYPE_ETHERNET_II,
++	FRAME_TYPE_80211_MGMT,
++	} frame_type;
++
++typedef struct wifi_frame_info {
++	/*
++	 * The type of MAC-layer frame that this frame_info holds.
++	 * - For data frames, use FRAME_TYPE_ETHERNET_II.
++	 * - For management frames, use FRAME_TYPE_80211_MGMT.
++	 * - If the type of the frame is unknown, use FRAME_TYPE_UNKNOWN.
++	 */
++	frame_type payload_type;
++
++	/*
++	 * The number of bytes included in |frame_content|. If the frame
++	 * contents are missing (e.g. RX frame dropped in firmware),
++	 * |frame_len| should be set to 0.
++	 */
++	size_t frame_len;
++
++	/*
++	 * Host clock when this frame was received by the driver (either
++	 *	outbound from the host network stack, or inbound from the
++	 *	firmware).
++	 *	- The timestamp should be taken from a clock which includes time
++	 *	  the host spent suspended (e.g. ktime_get_boottime()).
++	 *	- If no host timestamp is available (e.g. RX frame was dropped in
++	 *	  firmware), this field should be set to 0.
++	 */
++	uint32 driver_timestamp_usec;
++
++	/*
++	 * Firmware clock when this frame was received by the firmware
++	 *	(either outbound from the host, or inbound from a remote
++	 *	station).
++	 *	- The timestamp should be taken from a clock which includes time
++	 *	  firmware spent suspended (if applicable).
++	 *	- If no firmware timestamp is available (e.g. TX frame was
++	 *	  dropped by driver), this field should be set to 0.
++	 *	- Consumers of |frame_info| should _not_ assume any
++	 *	  synchronization between driver and firmware clocks.
++	 */
++	uint32 firmware_timestamp_usec;
++
++	/*
++	 * Actual frame content.
++	 * - Should be provided for TX frames originated by the host.
++	 * - Should be provided for RX frames received by the driver.
++	 * - Optionally provided for TX frames originated by firmware. (At
++	 *   discretion of HAL implementation.)
++	 * - Optionally provided for RX frames dropped in firmware. (At
++	 *   discretion of HAL implementation.)
++	 * - If frame content is not provided, |frame_len| should be set
++	 *   to 0.
++	 */
++	union {
++		char ethernet_ii[MAX_FRAME_LEN_ETHERNET];
++		char ieee_80211_mgmt[MAX_FRAME_LEN_80211_MGMT];
++	} frame_content;
++} wifi_frame_info_t;
++
++typedef struct wifi_tx_report {
++	/*
++	 * Prefix of MD5 hash of |frame_inf.frame_content|. If frame
++	 * content is not provided, prefix of MD5 hash over the same data
++	 * that would be in frame_content, if frame content were provided.
++	 */
++	char md5_prefix[MD5_PREFIX_LEN];
++	wifi_tx_packet_fate fate;
++	wifi_frame_info_t frame_inf;
++} wifi_tx_report_t;
++
++typedef struct wifi_rx_report {
++	/*
++	 * Prefix of MD5 hash of |frame_inf.frame_content|. If frame
++	 * content is not provided, prefix of MD5 hash over the same data
++	 * that would be in frame_content, if frame content were provided.
++	 */
++	char md5_prefix[MD5_PREFIX_LEN];
++	wifi_rx_packet_fate fate;
++	wifi_frame_info_t frame_inf;
++} wifi_rx_report_t;
++
++typedef struct compat_wifi_frame_info {
++	frame_type payload_type;
++
++	uint32 frame_len;
++
++	uint32 driver_timestamp_usec;
++
++	uint32 firmware_timestamp_usec;
++
++	union {
++		char ethernet_ii[MAX_FRAME_LEN_ETHERNET];
++		char ieee_80211_mgmt[MAX_FRAME_LEN_80211_MGMT];
++	} frame_content;
++} compat_wifi_frame_info_t;
++
++
++typedef struct compat_wifi_tx_report {
++	char md5_prefix[MD5_PREFIX_LEN];
++	wifi_tx_packet_fate fate;
++	compat_wifi_frame_info_t frame_inf;
++} compat_wifi_tx_report_t;
++
++typedef struct compat_wifi_rx_report {
++	char md5_prefix[MD5_PREFIX_LEN];
++	wifi_rx_packet_fate fate;
++	compat_wifi_frame_info_t frame_inf;
++} compat_wifi_rx_report_t;
++
++
++/*
++ * Packet logging - internal data
++ */
++
++typedef enum dhd_dbg_pkt_mon_state {
++	PKT_MON_INVALID = 0,
++	PKT_MON_ATTACHED,
++	PKT_MON_STARTING,
++	PKT_MON_STARTED,
++	PKT_MON_STOPPING,
++	PKT_MON_STOPPED,
++	PKT_MON_DETACHED,
++	} dhd_dbg_pkt_mon_state_t;
++
++typedef struct dhd_dbg_pkt_info {
++	frame_type payload_type;
++	size_t pkt_len;
++	uint32 driver_ts;
++	uint32 firmware_ts;
++	uint32 pkt_hash;
++	void *pkt;
++} dhd_dbg_pkt_info_t;
++
++typedef struct compat_dhd_dbg_pkt_info {
++	frame_type payload_type;
++	uint32 pkt_len;
++	uint32 driver_ts;
++	uint32 firmware_ts;
++	uint32 pkt_hash;
++	void *pkt;
++} compat_dhd_dbg_pkt_info_t;
++
++typedef struct dhd_dbg_tx_info
++{
++	wifi_tx_packet_fate fate;
++	dhd_dbg_pkt_info_t info;
++} dhd_dbg_tx_info_t;
++
++typedef struct dhd_dbg_rx_info
++{
++	wifi_rx_packet_fate fate;
++	dhd_dbg_pkt_info_t info;
++} dhd_dbg_rx_info_t;
++
++typedef struct dhd_dbg_tx_report
++{
++	dhd_dbg_tx_info_t *tx_pkts;
++	uint16 pkt_pos;
++	uint16 status_pos;
++} dhd_dbg_tx_report_t;
++
++typedef struct dhd_dbg_rx_report
++{
++	dhd_dbg_rx_info_t *rx_pkts;
++	uint16 pkt_pos;
++} dhd_dbg_rx_report_t;
++
++typedef void (*dbg_pullreq_t)(void *os_priv, const int ring_id);
++typedef void (*dbg_urgent_noti_t) (dhd_pub_t *dhdp, const void *data, const uint32 len);
++typedef int (*dbg_mon_tx_pkts_t) (dhd_pub_t *dhdp, void *pkt, uint32 pktid);
++typedef int (*dbg_mon_tx_status_t) (dhd_pub_t *dhdp, void *pkt,
++	uint32 pktid, uint16 status);
++typedef int (*dbg_mon_rx_pkts_t) (dhd_pub_t *dhdp, void *pkt);
++
++typedef struct dhd_dbg_pkt_mon
++{
++	dhd_dbg_tx_report_t *tx_report;
++	dhd_dbg_rx_report_t *rx_report;
++	dhd_dbg_pkt_mon_state_t tx_pkt_state;
++	dhd_dbg_pkt_mon_state_t tx_status_state;
++	dhd_dbg_pkt_mon_state_t rx_pkt_state;
++
++	/* call backs */
++	dbg_mon_tx_pkts_t tx_pkt_mon;
++	dbg_mon_tx_status_t tx_status_mon;
++	dbg_mon_rx_pkts_t rx_pkt_mon;
++} dhd_dbg_pkt_mon_t;
++
++enum dbg_ring_state {
++	RING_STOP       = 0,    /* ring is not initialized */
++	RING_ACTIVE,    /* ring is live and logging */
++	RING_SUSPEND    /* ring is initialized but not logging */
++};
++
++struct ring_statistics {
++	/* number of bytes that was written to the buffer by driver */
++	uint32 written_bytes;
++	/* number of bytes that was read from the buffer by user land */
++	uint32 read_bytes;
++	/* number of records that was written to the buffer by driver */
++	uint32 written_records;
++};
++
++typedef struct dhd_dbg_ring {
++	int     id;             /* ring id */
++	uint8   name[DBGRING_NAME_MAX]; /* name string */
++	uint32  ring_size;      /* numbers of item in ring */
++	uint32  wp;             /* write pointer */
++	uint32  rp;             /* read pointer */
++	uint32  log_level; /* log_level */
++	uint32  threshold; /* threshold bytes */
++	void *  ring_buf;       /* pointer of actually ring buffer */
++	void *  lock;           /* spin lock for ring access */
++	struct ring_statistics stat; /* statistics */
++	enum dbg_ring_state state;      /* ring state enum */
++	bool tail_padded;		/* writer does not have enough space */
++	uint32 rem_len;		/* number of bytes from wp_pad to end */
++	bool sched_pull;	/* schedule reader immediately */
++} dhd_dbg_ring_t;
++
++typedef struct dhd_dbg {
++	dhd_dbg_ring_t dbg_rings[DEBUG_RING_ID_MAX];
++	void *private;          /* os private_data */
++	dhd_dbg_pkt_mon_t pkt_mon;
++	void *pkt_mon_lock; /* spin lock for packet monitoring */
++	dbg_pullreq_t pullreq;
++	dbg_urgent_noti_t urgent_notifier;
++} dhd_dbg_t;
++
++#define PKT_MON_ATTACHED(state) \
++		(((state) > PKT_MON_INVALID) && ((state) < PKT_MON_DETACHED))
++#define PKT_MON_DETACHED(state) \
++		(((state) == PKT_MON_INVALID) || ((state) == PKT_MON_DETACHED))
++#define PKT_MON_STARTED(state) ((state) == PKT_MON_STARTED)
++#define PKT_MON_STOPPED(state) ((state) == PKT_MON_STOPPED)
++#define PKT_MON_NOT_OPERATIONAL(state) \
++	(((state) != PKT_MON_STARTED) && ((state) != PKT_MON_STOPPED))
++#define PKT_MON_SAFE_TO_FREE(state) \
++	(((state) == PKT_MON_STARTING) || ((state) == PKT_MON_STOPPED))
++#define PKT_MON_PKT_FULL(pkt_count) ((pkt_count) >= MAX_FATE_LOG_LEN)
++#define PKT_MON_STATUS_FULL(pkt_count, status_count) \
++		(((status_count) >= (pkt_count)) || ((status_count) >= MAX_FATE_LOG_LEN))
++
++#ifdef DBG_PKT_MON
++#define DHD_DBG_PKT_MON_TX(dhdp, pkt, pktid) \
++	do { \
++		if ((dhdp) && (dhdp)->dbg && (dhdp)->dbg->pkt_mon.tx_pkt_mon && (pkt)) { \
++			(dhdp)->dbg->pkt_mon.tx_pkt_mon((dhdp), (pkt), (pktid)); \
++		} \
++	} while (0);
++#define DHD_DBG_PKT_MON_TX_STATUS(dhdp, pkt, pktid, status) \
++	do { \
++		if ((dhdp) && (dhdp)->dbg && (dhdp)->dbg->pkt_mon.tx_status_mon && (pkt)) { \
++			(dhdp)->dbg->pkt_mon.tx_status_mon((dhdp), (pkt), (pktid), (status)); \
++		} \
++	} while (0);
++#define DHD_DBG_PKT_MON_RX(dhdp, pkt) \
++	do { \
++		if ((dhdp) && (dhdp)->dbg && (dhdp)->dbg->pkt_mon.rx_pkt_mon && (pkt)) { \
++			if (ntoh16((pkt)->protocol) != ETHER_TYPE_BRCM) { \
++				(dhdp)->dbg->pkt_mon.rx_pkt_mon((dhdp), (pkt)); \
++			} \
++		} \
++	} while (0);
++
++#define DHD_DBG_PKT_MON_START(dhdp) \
++		dhd_os_dbg_start_pkt_monitor((dhdp));
++#define DHD_DBG_PKT_MON_STOP(dhdp) \
++		dhd_os_dbg_stop_pkt_monitor((dhdp));
++#else
++#define DHD_DBG_PKT_MON_TX(dhdp, pkt, pktid)
++#define DHD_DBG_PKT_MON_TX_STATUS(dhdp, pkt, pktid, status)
++#define DHD_DBG_PKT_MON_RX(dhdp, pkt)
++#define DHD_DBG_PKT_MON_START(dhdp)
++#define DHD_DBG_PKT_MON_STOP(dhdp)
++#endif /* DBG_PKT_MON */
++
++#ifdef DUMP_IOCTL_IOV_LIST
++typedef struct dhd_iov_li {
++	dll_t list;
++	uint32 cmd;
++	char buff[100];
++} dhd_iov_li_t;
++
++#define IOV_LIST_MAX_LEN 5
++#endif /* DUMP_IOCTL_IOV_LIST */
++
++#ifdef DHD_DEBUG
++typedef struct {
++	dll_t list;
++	uint32 id; /* wasted chunk id */
++	uint32 handle; /* wasted chunk handle */
++	uint32 size; /* wasted chunk size */
++} dhd_dbg_mwli_t;
++#endif /* DHD_DEBUG */
++
++/* dhd_dbg functions */
++extern void dhd_dbg_trace_evnt_handler(dhd_pub_t *dhdp, void *event_data,
++		void *raw_event_ptr, uint datalen);
++extern int dhd_dbg_attach(dhd_pub_t *dhdp, dbg_pullreq_t os_pullreq,
++	dbg_urgent_noti_t os_urgent_notifier, void *os_priv);
++extern void dhd_dbg_detach(dhd_pub_t *dhdp);
++extern int dhd_dbg_start(dhd_pub_t *dhdp, bool start);
++extern int dhd_dbg_set_configuration(dhd_pub_t *dhdp, int ring_id,
++		int log_level, int flags, uint32 threshold);
++extern int dhd_dbg_get_ring_status(dhd_pub_t *dhdp, int ring_id,
++		dhd_dbg_ring_status_t *dbg_ring_status);
++extern int dhd_dbg_ring_push(dhd_pub_t *dhdp, int ring_id, dhd_dbg_ring_entry_t *hdr, void *data);
++extern int dhd_dbg_ring_pull(dhd_pub_t *dhdp, int ring_id, void *data, uint32 buf_len);
++extern int dhd_dbg_ring_pull_single(dhd_pub_t *dhdp, int ring_id, void *data, uint32 buf_len,
++		bool strip_header);
++extern int dhd_dbg_find_ring_id(dhd_pub_t *dhdp, char *ring_name);
++extern void *dhd_dbg_get_priv(dhd_pub_t *dhdp);
++extern int dhd_dbg_send_urgent_evt(dhd_pub_t *dhdp, const void *data, const uint32 len);
++extern void dhd_dbg_verboselog_printf(dhd_pub_t *dhdp, event_log_hdr_t *hdr,
++	void *raw_event_ptr, uint32 *log_ptr);
++
++#ifdef DBG_PKT_MON
++extern int dhd_dbg_attach_pkt_monitor(dhd_pub_t *dhdp,
++		dbg_mon_tx_pkts_t tx_pkt_mon,
++		dbg_mon_tx_status_t tx_status_mon,
++		dbg_mon_rx_pkts_t rx_pkt_mon);
++extern int dhd_dbg_start_pkt_monitor(dhd_pub_t *dhdp);
++extern int dhd_dbg_monitor_tx_pkts(dhd_pub_t *dhdp, void *pkt, uint32 pktid);
++extern int dhd_dbg_monitor_tx_status(dhd_pub_t *dhdp, void *pkt,
++		uint32 pktid, uint16 status);
++extern int dhd_dbg_monitor_rx_pkts(dhd_pub_t *dhdp, void *pkt);
++extern int dhd_dbg_stop_pkt_monitor(dhd_pub_t *dhdp);
++extern int dhd_dbg_monitor_get_tx_pkts(dhd_pub_t *dhdp, void __user *user_buf,
++		uint16 req_count, uint16 *resp_count);
++extern int dhd_dbg_monitor_get_rx_pkts(dhd_pub_t *dhdp, void __user *user_buf,
++		uint16 req_count, uint16 *resp_count);
++extern int dhd_dbg_detach_pkt_monitor(dhd_pub_t *dhdp);
++#endif /* DBG_PKT_MON */
++
++/* os wrapper function */
++extern int dhd_os_dbg_attach(dhd_pub_t *dhdp);
++extern void dhd_os_dbg_detach(dhd_pub_t *dhdp);
++extern int dhd_os_dbg_register_callback(int ring_id,
++	void (*dbg_ring_sub_cb)(void *ctx, const int ring_id, const void *data,
++		const uint32 len, const dhd_dbg_ring_status_t dbg_ring_status));
++extern int dhd_os_dbg_register_urgent_notifier(dhd_pub_t *dhdp,
++	void (*urgent_noti)(void *ctx, const void *data, const uint32 len, const uint32 fw_len));
++
++extern int dhd_os_start_logging(dhd_pub_t *dhdp, char *ring_name, int log_level,
++		int flags, int time_intval, int threshold);
++extern int dhd_os_reset_logging(dhd_pub_t *dhdp);
++extern int dhd_os_suppress_logging(dhd_pub_t *dhdp, bool suppress);
++
++extern int dhd_os_get_ring_status(dhd_pub_t *dhdp, int ring_id,
++		dhd_dbg_ring_status_t *dbg_ring_status);
++extern int dhd_os_trigger_get_ring_data(dhd_pub_t *dhdp, char *ring_name);
++extern int dhd_os_push_push_ring_data(dhd_pub_t *dhdp, int ring_id, void *data, int32 data_len);
++extern int dhd_os_dbg_get_feature(dhd_pub_t *dhdp, int32 *features);
++
++#ifdef DBG_PKT_MON
++extern int dhd_os_dbg_attach_pkt_monitor(dhd_pub_t *dhdp);
++extern int dhd_os_dbg_start_pkt_monitor(dhd_pub_t *dhdp);
++extern int dhd_os_dbg_monitor_tx_pkts(dhd_pub_t *dhdp, void *pkt,
++	uint32 pktid);
++extern int dhd_os_dbg_monitor_tx_status(dhd_pub_t *dhdp, void *pkt,
++	uint32 pktid, uint16 status);
++extern int dhd_os_dbg_monitor_rx_pkts(dhd_pub_t *dhdp, void *pkt);
++extern int dhd_os_dbg_stop_pkt_monitor(dhd_pub_t *dhdp);
++extern int dhd_os_dbg_monitor_get_tx_pkts(dhd_pub_t *dhdp,
++	void __user *user_buf, uint16 req_count, uint16 *resp_count);
++extern int dhd_os_dbg_monitor_get_rx_pkts(dhd_pub_t *dhdp,
++	void __user *user_buf, uint16 req_count, uint16 *resp_count);
++extern int dhd_os_dbg_detach_pkt_monitor(dhd_pub_t *dhdp);
++#endif /* DBG_PKT_MON */
++
++#ifdef DUMP_IOCTL_IOV_LIST
++extern void dhd_iov_li_append(dhd_pub_t *dhd, dll_t *list_head, dll_t *node);
++extern void dhd_iov_li_print(dll_t *list_head);
++extern void dhd_iov_li_delete(dhd_pub_t *dhd, dll_t *list_head);
++#endif /* DUMP_IOCTL_IOV_LIST */
++
++#ifdef DHD_DEBUG
++extern void dhd_mw_list_delete(dhd_pub_t *dhd, dll_t *list_head);
++#endif /* DHD_DEBUG */
++#endif /* _dhd_debug_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_debug_linux.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_debug_linux.c
+new file mode 100644
+index 000000000..ddd659407
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_debug_linux.c
+@@ -0,0 +1,520 @@
++/*
++ * DHD debugability Linux os layer
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * $Id: dhd_debug_linux.c 710862 2017-07-14 07:43:59Z $
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_dbg.h>
++#include <dhd_debug.h>
++
++#include <net/cfg80211.h>
++#include <wl_cfgvendor.h>
++
++typedef void (*dbg_ring_send_sub_t)(void *ctx, const int ring_id, const void *data,
++	const uint32 len, const dhd_dbg_ring_status_t ring_status);
++typedef void (*dbg_urgent_noti_sub_t)(void *ctx, const void *data,
++	const uint32 len, const uint32 fw_len);
++
++static dbg_ring_send_sub_t ring_send_sub_cb[DEBUG_RING_ID_MAX];
++static dbg_urgent_noti_sub_t urgent_noti_sub_cb;
++typedef struct dhd_dbg_os_ring_info {
++	dhd_pub_t *dhdp;
++	int ring_id;
++	int log_level;
++	unsigned long interval;
++	struct delayed_work work;
++	uint64 tsoffset;
++} linux_dbgring_info_t;
++
++struct log_level_table dhd_event_map[] = {
++	{1, WIFI_EVENT_DRIVER_EAPOL_FRAME_TRANSMIT_REQUESTED, 0, "DRIVER EAPOL TX REQ"},
++	{1, WIFI_EVENT_DRIVER_EAPOL_FRAME_RECEIVED, 0, "DRIVER EAPOL RX"},
++	{2, WIFI_EVENT_DRIVER_SCAN_REQUESTED, 0, "SCAN_REQUESTED"},
++	{2, WIFI_EVENT_DRIVER_SCAN_COMPLETE, 0, "SCAN COMPELETE"},
++	{3, WIFI_EVENT_DRIVER_SCAN_RESULT_FOUND, 0, "SCAN RESULT FOUND"},
++	{2, WIFI_EVENT_DRIVER_PNO_ADD, 0, "PNO ADD"},
++	{2, WIFI_EVENT_DRIVER_PNO_REMOVE, 0, "PNO REMOVE"},
++	{2, WIFI_EVENT_DRIVER_PNO_NETWORK_FOUND, 0, "PNO NETWORK FOUND"},
++	{2, WIFI_EVENT_DRIVER_PNO_SCAN_REQUESTED, 0, "PNO SCAN_REQUESTED"},
++	{1, WIFI_EVENT_DRIVER_PNO_SCAN_RESULT_FOUND, 0, "PNO SCAN RESULT FOUND"},
++	{1, WIFI_EVENT_DRIVER_PNO_SCAN_COMPLETE, 0, "PNO SCAN COMPELETE"}
++};
++
++static void
++debug_data_send(dhd_pub_t *dhdp, int ring_id, const void *data, const uint32 len,
++	const dhd_dbg_ring_status_t ring_status)
++{
++	struct net_device *ndev;
++	dbg_ring_send_sub_t ring_sub_send;
++	ndev = dhd_linux_get_primary_netdev(dhdp);
++	if (!ndev)
++		return;
++	if (ring_send_sub_cb[ring_id]) {
++		ring_sub_send = ring_send_sub_cb[ring_id];
++		ring_sub_send(ndev, ring_id, data, len, ring_status);
++	}
++}
++
++static void
++dhd_os_dbg_urgent_notifier(dhd_pub_t *dhdp, const void *data, const uint32 len)
++{
++	struct net_device *ndev;
++	ndev = dhd_linux_get_primary_netdev(dhdp);
++	if (!ndev)
++		return;
++	if (urgent_noti_sub_cb) {
++		urgent_noti_sub_cb(ndev, data, len, dhdp->soc_ram_length);
++	}
++}
++
++static void
++dbg_ring_poll_worker(struct work_struct *work)
++{
++	struct delayed_work *d_work = to_delayed_work(work);
++	bool sched = TRUE;
++	dhd_dbg_ring_t *ring;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	linux_dbgring_info_t *ring_info =
++		container_of(d_work, linux_dbgring_info_t, work);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	dhd_pub_t *dhdp = ring_info->dhdp;
++	int ringid = ring_info->ring_id;
++	dhd_dbg_ring_status_t ring_status;
++	void *buf;
++	dhd_dbg_ring_entry_t *hdr;
++	uint32 buflen, rlen;
++	unsigned long flags;
++
++	ring = &dhdp->dbg->dbg_rings[ringid];
++	flags = dhd_os_spin_lock(ring->lock);
++	dhd_dbg_get_ring_status(dhdp, ringid, &ring_status);
++
++	if (ring->wp > ring->rp) {
++		buflen = ring->wp - ring->rp;
++	} else if (ring->wp < ring->rp) {
++		buflen = ring->ring_size - ring->rp + ring->wp;
++	} else {
++		goto exit;
++	}
++
++	if (buflen > ring->ring_size) {
++		goto exit;
++	}
++
++	buf = MALLOCZ(dhdp->osh, buflen);
++	if (!buf) {
++		DHD_ERROR(("%s failed to allocate read buf\n", __FUNCTION__));
++		sched = FALSE;
++		goto exit;
++	}
++
++	rlen = dhd_dbg_ring_pull(dhdp, ringid, buf, buflen);
++	if (!ring->sched_pull) {
++		ring->sched_pull = TRUE;
++	}
++
++	hdr = (dhd_dbg_ring_entry_t *)buf;
++	while (rlen > 0) {
++		ring_status.read_bytes += ENTRY_LENGTH(hdr);
++		/* offset fw ts to host ts */
++		hdr->timestamp += ring_info->tsoffset;
++		debug_data_send(dhdp, ringid, hdr, ENTRY_LENGTH(hdr),
++			ring_status);
++		rlen -= ENTRY_LENGTH(hdr);
++		hdr = (dhd_dbg_ring_entry_t *)((char *)hdr + ENTRY_LENGTH(hdr));
++	}
++	MFREE(dhdp->osh, buf, buflen);
++
++exit:
++	if (sched) {
++		/* retrigger the work at same interval */
++		if ((ring_status.written_bytes == ring_status.read_bytes) &&
++				(ring_info->interval)) {
++			schedule_delayed_work(d_work, ring_info->interval);
++		}
++	}
++
++	dhd_os_spin_unlock(ring->lock, flags);
++
++	return;
++}
++
++int
++dhd_os_dbg_register_callback(int ring_id, dbg_ring_send_sub_t callback)
++{
++	if (!VALID_RING(ring_id))
++		return BCME_RANGE;
++
++	ring_send_sub_cb[ring_id] = callback;
++	return BCME_OK;
++}
++
++int
++dhd_os_dbg_register_urgent_notifier(dhd_pub_t *dhdp, dbg_urgent_noti_sub_t urgent_noti_sub)
++{
++	if (!dhdp || !urgent_noti_sub)
++		return BCME_BADARG;
++	urgent_noti_sub_cb = urgent_noti_sub;
++
++	return BCME_OK;
++}
++
++int
++dhd_os_start_logging(dhd_pub_t *dhdp, char *ring_name, int log_level,
++	int flags, int time_intval, int threshold)
++{
++	int ret = BCME_OK;
++	int ring_id;
++	linux_dbgring_info_t *os_priv, *ring_info;
++	uint32 ms;
++
++	ring_id = dhd_dbg_find_ring_id(dhdp, ring_name);
++	if (!VALID_RING(ring_id))
++		return BCME_UNSUPPORTED;
++
++	DHD_DBGIF(("%s , log_level : %d, time_intval : %d, threshod %d Bytes\n",
++		__FUNCTION__, log_level, time_intval, threshold));
++
++	/* change the configuration */
++	ret = dhd_dbg_set_configuration(dhdp, ring_id, log_level, flags, threshold);
++	if (ret) {
++		DHD_ERROR(("dhd_set_configuration is failed : %d\n", ret));
++		return ret;
++	}
++
++	os_priv = dhd_dbg_get_priv(dhdp);
++	if (!os_priv)
++		return BCME_ERROR;
++	ring_info = &os_priv[ring_id];
++	ring_info->log_level = log_level;
++	if (ring_id == FW_VERBOSE_RING_ID || ring_id == FW_EVENT_RING_ID) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))
++		ring_info->tsoffset = local_clock();
++#else
++		ring_info->tsoffset = sched_clock();
++#endif
++		if (dhd_wl_ioctl_get_intiovar(dhdp, "rte_timesync", &ms, WLC_GET_VAR,
++				FALSE, 0))
++			DHD_ERROR(("%s rte_timesync failed\n", __FUNCTION__));
++		do_div(ring_info->tsoffset, 1000000);
++		ring_info->tsoffset -= ms;
++	}
++	if (time_intval == 0 || log_level == 0) {
++		ring_info->interval = 0;
++		cancel_delayed_work_sync(&ring_info->work);
++	} else {
++		ring_info->interval = msecs_to_jiffies(time_intval * MSEC_PER_SEC);
++		cancel_delayed_work_sync(&ring_info->work);
++		schedule_delayed_work(&ring_info->work, ring_info->interval);
++	}
++
++	return ret;
++}
++
++int
++dhd_os_reset_logging(dhd_pub_t *dhdp)
++{
++	int ret = BCME_OK;
++	int ring_id;
++	linux_dbgring_info_t *os_priv, *ring_info;
++
++	os_priv = dhd_dbg_get_priv(dhdp);
++	if (!os_priv)
++		return BCME_ERROR;
++
++	/* Stop all rings */
++	for (ring_id = DEBUG_RING_ID_INVALID + 1; ring_id < DEBUG_RING_ID_MAX; ring_id++) {
++		DHD_DBGIF(("%s: Stop ring buffer %d\n", __FUNCTION__, ring_id));
++
++		ring_info = &os_priv[ring_id];
++		/* cancel any pending work */
++		cancel_delayed_work_sync(&ring_info->work);
++		/* log level zero makes stop logging on that ring */
++		ring_info->log_level = 0;
++		ring_info->interval = 0;
++		/* change the configuration */
++		ret = dhd_dbg_set_configuration(dhdp, ring_id, 0, 0, 0);
++		if (ret) {
++			DHD_ERROR(("dhd_set_configuration is failed : %d\n", ret));
++			return ret;
++		}
++	}
++	return ret;
++}
++
++#define SUPPRESS_LOG_LEVEL 1
++int
++dhd_os_suppress_logging(dhd_pub_t *dhdp, bool suppress)
++{
++	int ret = BCME_OK;
++	int max_log_level;
++	int enable = (suppress) ? 0 : 1;
++	linux_dbgring_info_t *os_priv;
++
++	os_priv = dhd_dbg_get_priv(dhdp);
++	if (!os_priv)
++		return BCME_ERROR;
++
++	max_log_level = MAX(os_priv[FW_VERBOSE_RING_ID].log_level,
++		os_priv[FW_EVENT_RING_ID].log_level);
++	if (max_log_level == SUPPRESS_LOG_LEVEL) {
++		/* suppress the logging in FW not to wake up host while device in suspend mode */
++		ret = dhd_iovar(dhdp, 0, "logtrace", (char *)&enable, sizeof(enable), NULL, 0,
++				TRUE);
++		if (ret < 0 && (ret != BCME_UNSUPPORTED)) {
++			DHD_ERROR(("logtrace is failed : %d\n", ret));
++		}
++	}
++
++	return ret;
++}
++
++int
++dhd_os_get_ring_status(dhd_pub_t *dhdp, int ring_id, dhd_dbg_ring_status_t *dbg_ring_status)
++{
++	return dhd_dbg_get_ring_status(dhdp, ring_id, dbg_ring_status);
++}
++
++int
++dhd_os_trigger_get_ring_data(dhd_pub_t *dhdp, char *ring_name)
++{
++	int ret = BCME_OK;
++	int ring_id;
++	linux_dbgring_info_t *os_priv, *ring_info;
++	ring_id = dhd_dbg_find_ring_id(dhdp, ring_name);
++	if (!VALID_RING(ring_id))
++		return BCME_UNSUPPORTED;
++	os_priv = dhd_dbg_get_priv(dhdp);
++	if (os_priv) {
++		ring_info = &os_priv[ring_id];
++		if (ring_info->interval) {
++			cancel_delayed_work_sync(&ring_info->work);
++		}
++		schedule_delayed_work(&ring_info->work, 0);
++	} else {
++		DHD_ERROR(("%s : os_priv is NULL\n", __FUNCTION__));
++		ret = BCME_ERROR;
++	}
++	return ret;
++}
++
++int
++dhd_os_push_push_ring_data(dhd_pub_t *dhdp, int ring_id, void *data, int32 data_len)
++{
++	int ret = BCME_OK, i;
++	dhd_dbg_ring_entry_t msg_hdr;
++	log_conn_event_t *event_data = (log_conn_event_t *)data;
++	linux_dbgring_info_t *os_priv, *ring_info = NULL;
++
++	if (!VALID_RING(ring_id))
++		return BCME_UNSUPPORTED;
++	os_priv = dhd_dbg_get_priv(dhdp);
++
++	if (os_priv) {
++		ring_info = &os_priv[ring_id];
++	} else
++		return BCME_NORESOURCE;
++
++	memset(&msg_hdr, 0, sizeof(dhd_dbg_ring_entry_t));
++
++	if (ring_id == DHD_EVENT_RING_ID) {
++		msg_hdr.type = DBG_RING_ENTRY_EVENT_TYPE;
++		msg_hdr.flags |= DBG_RING_ENTRY_FLAGS_HAS_TIMESTAMP;
++		msg_hdr.flags |= DBG_RING_ENTRY_FLAGS_HAS_BINARY;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))
++		msg_hdr.timestamp = local_clock();
++#else
++		msg_hdr.timestamp = sched_clock();
++#endif
++		/* convert to ms */
++		do_div(msg_hdr.timestamp, 1000000);
++		msg_hdr.len = data_len;
++		/* filter the event for higher log level with current log level */
++		for (i = 0; i < ARRAYSIZE(dhd_event_map); i++) {
++			if ((dhd_event_map[i].tag == event_data->event) &&
++				dhd_event_map[i].log_level > ring_info->log_level) {
++				return ret;
++			}
++		}
++	}
++	ret = dhd_dbg_ring_push(dhdp, ring_id, &msg_hdr, event_data);
++	if (ret) {
++		DHD_ERROR(("%s : failed to push data into the ring (%d) with ret(%d)\n",
++			__FUNCTION__, ring_id, ret));
++	}
++
++	return ret;
++}
++
++#ifdef DBG_PKT_MON
++int
++dhd_os_dbg_attach_pkt_monitor(dhd_pub_t *dhdp)
++{
++	return dhd_dbg_attach_pkt_monitor(dhdp, dhd_os_dbg_monitor_tx_pkts,
++		dhd_os_dbg_monitor_tx_status, dhd_os_dbg_monitor_rx_pkts);
++}
++
++int
++dhd_os_dbg_start_pkt_monitor(dhd_pub_t *dhdp)
++{
++	return dhd_dbg_start_pkt_monitor(dhdp);
++}
++
++int
++dhd_os_dbg_monitor_tx_pkts(dhd_pub_t *dhdp, void *pkt, uint32 pktid)
++{
++	return dhd_dbg_monitor_tx_pkts(dhdp, pkt, pktid);
++}
++
++int
++dhd_os_dbg_monitor_tx_status(dhd_pub_t *dhdp, void *pkt, uint32 pktid,
++	uint16 status)
++{
++	return dhd_dbg_monitor_tx_status(dhdp, pkt, pktid, status);
++}
++
++int
++dhd_os_dbg_monitor_rx_pkts(dhd_pub_t *dhdp, void *pkt)
++{
++	return dhd_dbg_monitor_rx_pkts(dhdp, pkt);
++}
++
++int
++dhd_os_dbg_stop_pkt_monitor(dhd_pub_t *dhdp)
++{
++	return dhd_dbg_stop_pkt_monitor(dhdp);
++}
++
++int
++dhd_os_dbg_monitor_get_tx_pkts(dhd_pub_t *dhdp, void __user *user_buf,
++	uint16 req_count, uint16 *resp_count)
++{
++	return dhd_dbg_monitor_get_tx_pkts(dhdp, user_buf, req_count, resp_count);
++}
++
++int
++dhd_os_dbg_monitor_get_rx_pkts(dhd_pub_t *dhdp, void __user *user_buf,
++	uint16 req_count, uint16 *resp_count)
++{
++	return dhd_dbg_monitor_get_rx_pkts(dhdp, user_buf, req_count, resp_count);
++}
++
++int
++dhd_os_dbg_detach_pkt_monitor(dhd_pub_t *dhdp)
++{
++	return dhd_dbg_detach_pkt_monitor(dhdp);
++}
++#endif /* DBG_PKT_MON */
++
++int
++dhd_os_dbg_get_feature(dhd_pub_t *dhdp, int32 *features)
++{
++	int ret = BCME_OK;
++	*features = 0;
++	*features |= DBG_MEMORY_DUMP_SUPPORTED;
++	if (FW_SUPPORTED(dhdp, logtrace)) {
++		*features |= DBG_CONNECT_EVENT_SUPPORTED;
++		*features |= DBG_VERBOSE_LOG_SUPPORTED;
++	}
++	if (FW_SUPPORTED(dhdp, hchk)) {
++		*features |= DBG_HEALTH_CHECK_SUPPORTED;
++	}
++#ifdef DBG_PKT_MON
++	if (FW_SUPPORTED(dhdp, d11status)) {
++		*features |= DBG_PACKET_FATE_SUPPORTED;
++	}
++#endif /* DBG_PKT_MON */
++	return ret;
++}
++
++static void
++dhd_os_dbg_pullreq(void *os_priv, int ring_id)
++{
++	linux_dbgring_info_t *ring_info;
++
++	ring_info = &((linux_dbgring_info_t *)os_priv)[ring_id];
++	cancel_delayed_work(&ring_info->work);
++	schedule_delayed_work(&ring_info->work, 0);
++}
++
++int
++dhd_os_dbg_attach(dhd_pub_t *dhdp)
++{
++	int ret = BCME_OK;
++	linux_dbgring_info_t *os_priv, *ring_info;
++	int ring_id;
++
++	/* os_dbg data */
++	os_priv = MALLOCZ(dhdp->osh, sizeof(*os_priv) * DEBUG_RING_ID_MAX);
++	if (!os_priv)
++		return BCME_NOMEM;
++
++	for (ring_id = DEBUG_RING_ID_INVALID + 1; ring_id < DEBUG_RING_ID_MAX;
++	     ring_id++) {
++		ring_info = &os_priv[ring_id];
++		INIT_DELAYED_WORK(&ring_info->work, dbg_ring_poll_worker);
++		ring_info->dhdp = dhdp;
++		ring_info->ring_id = ring_id;
++	}
++
++	ret = dhd_dbg_attach(dhdp, dhd_os_dbg_pullreq, dhd_os_dbg_urgent_notifier, os_priv);
++	if (ret)
++		MFREE(dhdp->osh, os_priv, sizeof(*os_priv) * DEBUG_RING_ID_MAX);
++
++	return ret;
++}
++
++void
++dhd_os_dbg_detach(dhd_pub_t *dhdp)
++{
++	linux_dbgring_info_t *os_priv, *ring_info;
++	int ring_id;
++	/* free os_dbg data */
++	os_priv = dhd_dbg_get_priv(dhdp);
++	if (!os_priv)
++		return;
++	/* abort pending any job */
++	for (ring_id = DEBUG_RING_ID_INVALID + 1; ring_id < DEBUG_RING_ID_MAX; ring_id++) {
++		ring_info = &os_priv[ring_id];
++		if (ring_info->interval) {
++			ring_info->interval = 0;
++			cancel_delayed_work_sync(&ring_info->work);
++		}
++	}
++	MFREE(dhdp->osh, os_priv, sizeof(*os_priv) * DEBUG_RING_ID_MAX);
++
++	return dhd_dbg_detach(dhdp);
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_flowring.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_flowring.c
+new file mode 100644
+index 000000000..17a9dc314
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_flowring.c
+@@ -0,0 +1,1063 @@
++/*
++ * @file Broadcom Dongle Host Driver (DHD), Flow ring specific code at top level
++ *
++ * Flow rings are transmit traffic (=propagating towards antenna) related entities
++ *
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_flowring.c 710862 2017-07-14 07:43:59Z $
++ */
++
++
++#include <typedefs.h>
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <bcmdevs.h>
++
++#include <ethernet.h>
++#include <bcmevent.h>
++#include <dngl_stats.h>
++
++#include <dhd.h>
++
++#include <dhd_flowring.h>
++#include <dhd_bus.h>
++#include <dhd_proto.h>
++#include <dhd_dbg.h>
++#include <802.1d.h>
++#include <pcie_core.h>
++#include <bcmmsgbuf.h>
++#include <dhd_pcie.h>
++
++static INLINE int dhd_flow_queue_throttle(flow_queue_t *queue);
++
++static INLINE uint16 dhd_flowid_find(dhd_pub_t *dhdp, uint8 ifindex,
++                                     uint8 prio, char *sa, char *da);
++
++static INLINE uint16 dhd_flowid_alloc(dhd_pub_t *dhdp, uint8 ifindex,
++                                      uint8 prio, char *sa, char *da);
++
++static INLINE int dhd_flowid_lookup(dhd_pub_t *dhdp, uint8 ifindex,
++                                uint8 prio, char *sa, char *da, uint16 *flowid);
++int BCMFASTPATH dhd_flow_queue_overflow(flow_queue_t *queue, void *pkt);
++
++#define FLOW_QUEUE_PKT_NEXT(p)          PKTLINK(p)
++#define FLOW_QUEUE_PKT_SETNEXT(p, x)    PKTSETLINK((p), (x))
++
++#if defined(EAPOL_PKT_PRIO) || defined(DHD_LOSSLESS_ROAMING)
++const uint8 prio2ac[8] = { 0, 1, 1, 0, 2, 2, 3, 7 };
++#else
++const uint8 prio2ac[8] = { 0, 1, 1, 0, 2, 2, 3, 3 };
++#endif /* EAPOL_PKT_PRIO || DHD_LOSSLESS_ROAMING */
++const uint8 prio2tid[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
++
++/** Queue overflow throttle. Return value: TRUE if throttle needs to be applied */
++static INLINE int
++dhd_flow_queue_throttle(flow_queue_t *queue)
++{
++	return DHD_FLOW_QUEUE_FULL(queue);
++}
++
++int BCMFASTPATH
++dhd_flow_queue_overflow(flow_queue_t *queue, void *pkt)
++{
++	return BCME_NORESOURCE;
++}
++
++/** Returns flow ring given a flowid */
++flow_ring_node_t *
++dhd_flow_ring_node(dhd_pub_t *dhdp, uint16 flowid)
++{
++	flow_ring_node_t * flow_ring_node;
++
++	ASSERT(dhdp != (dhd_pub_t*)NULL);
++	ASSERT(flowid < dhdp->num_flow_rings);
++
++	flow_ring_node = &(((flow_ring_node_t*)(dhdp->flow_ring_table))[flowid]);
++
++	ASSERT(flow_ring_node->flowid == flowid);
++	return flow_ring_node;
++}
++
++/** Returns 'backup' queue given a flowid */
++flow_queue_t *
++dhd_flow_queue(dhd_pub_t *dhdp, uint16 flowid)
++{
++	flow_ring_node_t * flow_ring_node;
++
++	flow_ring_node = dhd_flow_ring_node(dhdp, flowid);
++	return &flow_ring_node->queue;
++}
++
++/* Flow ring's queue management functions */
++
++/** Reinitialize a flow ring's queue. */
++void
++dhd_flow_queue_reinit(dhd_pub_t *dhdp, flow_queue_t *queue, int max)
++{
++	ASSERT((queue != NULL) && (max > 0));
++
++	queue->head = queue->tail = NULL;
++	queue->len = 0;
++
++	/* Set queue's threshold and queue's parent cummulative length counter */
++	ASSERT(max > 1);
++	DHD_FLOW_QUEUE_SET_MAX(queue, max);
++	DHD_FLOW_QUEUE_SET_THRESHOLD(queue, max);
++	DHD_FLOW_QUEUE_SET_CLEN(queue, &dhdp->cumm_ctr);
++	DHD_FLOW_QUEUE_SET_L2CLEN(queue, &dhdp->l2cumm_ctr);
++
++	queue->failures = 0U;
++	queue->cb = &dhd_flow_queue_overflow;
++}
++
++/** Initialize a flow ring's queue, called on driver initialization. */
++void
++dhd_flow_queue_init(dhd_pub_t *dhdp, flow_queue_t *queue, int max)
++{
++	ASSERT((queue != NULL) && (max > 0));
++
++	dll_init(&queue->list);
++	dhd_flow_queue_reinit(dhdp, queue, max);
++}
++
++/** Register an enqueue overflow callback handler */
++void
++dhd_flow_queue_register(flow_queue_t *queue, flow_queue_cb_t cb)
++{
++	ASSERT(queue != NULL);
++	queue->cb = cb;
++}
++
++/**
++ * Enqueue an 802.3 packet at the back of a flow ring's queue. From there, it will travel later on
++ * to the flow ring itself.
++ */
++int BCMFASTPATH
++dhd_flow_queue_enqueue(dhd_pub_t *dhdp, flow_queue_t *queue, void *pkt)
++{
++	int ret = BCME_OK;
++
++	ASSERT(queue != NULL);
++
++	if (dhd_flow_queue_throttle(queue)) {
++		queue->failures++;
++		ret = (*queue->cb)(queue, pkt);
++		goto done;
++	}
++
++	if (queue->head) {
++		FLOW_QUEUE_PKT_SETNEXT(queue->tail, pkt);
++	} else {
++		queue->head = pkt;
++	}
++
++	FLOW_QUEUE_PKT_SETNEXT(pkt, NULL);
++
++	queue->tail = pkt; /* at tail */
++
++	queue->len++;
++	/* increment parent's cummulative length */
++	DHD_CUMM_CTR_INCR(DHD_FLOW_QUEUE_CLEN_PTR(queue));
++	/* increment grandparent's cummulative length */
++	DHD_CUMM_CTR_INCR(DHD_FLOW_QUEUE_L2CLEN_PTR(queue));
++
++done:
++	return ret;
++}
++
++/** Dequeue an 802.3 packet from a flow ring's queue, from head (FIFO) */
++void * BCMFASTPATH
++dhd_flow_queue_dequeue(dhd_pub_t *dhdp, flow_queue_t *queue)
++{
++	void * pkt;
++
++	ASSERT(queue != NULL);
++
++	pkt = queue->head; /* from head */
++
++	if (pkt == NULL) {
++		ASSERT((queue->len == 0) && (queue->tail == NULL));
++		goto done;
++	}
++
++	queue->head = FLOW_QUEUE_PKT_NEXT(pkt);
++	if (queue->head == NULL)
++		queue->tail = NULL;
++
++	queue->len--;
++	/* decrement parent's cummulative length */
++	DHD_CUMM_CTR_DECR(DHD_FLOW_QUEUE_CLEN_PTR(queue));
++	/* decrement grandparent's cummulative length */
++	DHD_CUMM_CTR_DECR(DHD_FLOW_QUEUE_L2CLEN_PTR(queue));
++
++	FLOW_QUEUE_PKT_SETNEXT(pkt, NULL); /* dettach packet from queue */
++
++done:
++	return pkt;
++}
++
++/** Reinsert a dequeued 802.3 packet back at the head */
++void BCMFASTPATH
++dhd_flow_queue_reinsert(dhd_pub_t *dhdp, flow_queue_t *queue, void *pkt)
++{
++	if (queue->head == NULL) {
++		queue->tail = pkt;
++	}
++
++	FLOW_QUEUE_PKT_SETNEXT(pkt, queue->head);
++	queue->head = pkt;
++	queue->len++;
++	/* increment parent's cummulative length */
++	DHD_CUMM_CTR_INCR(DHD_FLOW_QUEUE_CLEN_PTR(queue));
++	/* increment grandparent's cummulative length */
++	DHD_CUMM_CTR_INCR(DHD_FLOW_QUEUE_L2CLEN_PTR(queue));
++}
++
++/** Fetch the backup queue for a flowring, and assign flow control thresholds */
++void
++dhd_flow_ring_config_thresholds(dhd_pub_t *dhdp, uint16 flowid,
++                     int queue_budget, int cumm_threshold, void *cumm_ctr,
++                     int l2cumm_threshold, void *l2cumm_ctr)
++{
++	flow_queue_t * queue;
++
++	ASSERT(dhdp != (dhd_pub_t*)NULL);
++	ASSERT(queue_budget > 1);
++	ASSERT(cumm_threshold > 1);
++	ASSERT(cumm_ctr != (void*)NULL);
++	ASSERT(l2cumm_threshold > 1);
++	ASSERT(l2cumm_ctr != (void*)NULL);
++
++	queue = dhd_flow_queue(dhdp, flowid);
++
++	DHD_FLOW_QUEUE_SET_MAX(queue, queue_budget); /* Max queue length */
++
++	/* Set the queue's parent threshold and cummulative counter */
++	DHD_FLOW_QUEUE_SET_THRESHOLD(queue, cumm_threshold);
++	DHD_FLOW_QUEUE_SET_CLEN(queue, cumm_ctr);
++
++	/* Set the queue's grandparent threshold and cummulative counter */
++	DHD_FLOW_QUEUE_SET_L2THRESHOLD(queue, l2cumm_threshold);
++	DHD_FLOW_QUEUE_SET_L2CLEN(queue, l2cumm_ctr);
++}
++
++/** Initializes data structures of multiple flow rings */
++int
++dhd_flow_rings_init(dhd_pub_t *dhdp, uint32 num_flow_rings)
++{
++	uint32 idx;
++	uint32 flow_ring_table_sz;
++	uint32 if_flow_lkup_sz = 0;
++	void * flowid_allocator;
++	flow_ring_table_t *flow_ring_table = NULL;
++	if_flow_lkup_t *if_flow_lkup = NULL;
++	void *lock = NULL;
++	void *list_lock = NULL;
++	unsigned long flags;
++
++	DHD_INFO(("%s\n", __FUNCTION__));
++
++	/* Construct a 16bit flowid allocator */
++	flowid_allocator = id16_map_init(dhdp->osh,
++	                       num_flow_rings - dhdp->bus->max_cmn_rings, FLOWID_RESERVED);
++	if (flowid_allocator == NULL) {
++		DHD_ERROR(("%s: flowid allocator init failure\n", __FUNCTION__));
++		return BCME_NOMEM;
++	}
++
++	/* Allocate a flow ring table, comprising of requested number of rings */
++	flow_ring_table_sz = (num_flow_rings * sizeof(flow_ring_node_t));
++	flow_ring_table = (flow_ring_table_t *)MALLOCZ(dhdp->osh, flow_ring_table_sz);
++	if (flow_ring_table == NULL) {
++		DHD_ERROR(("%s: flow ring table alloc failure\n", __FUNCTION__));
++		goto fail;
++	}
++
++	/* Initialize flow ring table state */
++	DHD_CUMM_CTR_INIT(&dhdp->cumm_ctr);
++	DHD_CUMM_CTR_INIT(&dhdp->l2cumm_ctr);
++	bzero((uchar *)flow_ring_table, flow_ring_table_sz);
++	for (idx = 0; idx < num_flow_rings; idx++) {
++		flow_ring_table[idx].status = FLOW_RING_STATUS_CLOSED;
++		flow_ring_table[idx].flowid = (uint16)idx;
++		flow_ring_table[idx].lock = dhd_os_spin_lock_init(dhdp->osh);
++#ifdef IDLE_TX_FLOW_MGMT
++		flow_ring_table[idx].last_active_ts = OSL_SYSUPTIME();
++#endif /* IDLE_TX_FLOW_MGMT */
++		if (flow_ring_table[idx].lock == NULL) {
++			DHD_ERROR(("%s: Failed to init spinlock for queue!\n", __FUNCTION__));
++			goto fail;
++		}
++
++		dll_init(&flow_ring_table[idx].list);
++
++		/* Initialize the per flow ring backup queue */
++		dhd_flow_queue_init(dhdp, &flow_ring_table[idx].queue,
++		                    FLOW_RING_QUEUE_THRESHOLD);
++	}
++
++	/* Allocate per interface hash table (for fast lookup from interface to flow ring) */
++	if_flow_lkup_sz = sizeof(if_flow_lkup_t) * DHD_MAX_IFS;
++	if_flow_lkup = (if_flow_lkup_t *)DHD_OS_PREALLOC(dhdp,
++		DHD_PREALLOC_IF_FLOW_LKUP, if_flow_lkup_sz);
++	if (if_flow_lkup == NULL) {
++		DHD_ERROR(("%s: if flow lkup alloc failure\n", __FUNCTION__));
++		goto fail;
++	}
++
++	/* Initialize per interface hash table */
++	for (idx = 0; idx < DHD_MAX_IFS; idx++) {
++		int hash_ix;
++		if_flow_lkup[idx].status = 0;
++		if_flow_lkup[idx].role = 0;
++		for (hash_ix = 0; hash_ix < DHD_FLOWRING_HASH_SIZE; hash_ix++)
++			if_flow_lkup[idx].fl_hash[hash_ix] = NULL;
++	}
++
++	lock = dhd_os_spin_lock_init(dhdp->osh);
++	if (lock == NULL)
++		goto fail;
++
++	list_lock = dhd_os_spin_lock_init(dhdp->osh);
++	if (list_lock == NULL)
++		goto lock_fail;
++
++	dhdp->flow_prio_map_type = DHD_FLOW_PRIO_AC_MAP;
++	bcopy(prio2ac, dhdp->flow_prio_map, sizeof(uint8) * NUMPRIO);
++#ifdef DHD_LOSSLESS_ROAMING
++	dhdp->dequeue_prec_map = ALLPRIO;
++#endif
++	/* Now populate into dhd pub */
++	DHD_FLOWID_LOCK(lock, flags);
++	dhdp->num_flow_rings = num_flow_rings;
++	dhdp->flowid_allocator = (void *)flowid_allocator;
++	dhdp->flow_ring_table = (void *)flow_ring_table;
++	dhdp->if_flow_lkup = (void *)if_flow_lkup;
++	dhdp->flowid_lock = lock;
++	dhdp->flow_rings_inited = TRUE;
++	dhdp->flowring_list_lock = list_lock;
++	DHD_FLOWID_UNLOCK(lock, flags);
++
++	DHD_INFO(("%s done\n", __FUNCTION__));
++	return BCME_OK;
++
++lock_fail:
++	/* deinit the spinlock */
++	dhd_os_spin_lock_deinit(dhdp->osh, lock);
++
++fail:
++	/* Destruct the per interface flow lkup table */
++	if (if_flow_lkup != NULL) {
++		DHD_OS_PREFREE(dhdp, if_flow_lkup, if_flow_lkup_sz);
++	}
++	if (flow_ring_table != NULL) {
++		for (idx = 0; idx < num_flow_rings; idx++) {
++			if (flow_ring_table[idx].lock != NULL)
++				dhd_os_spin_lock_deinit(dhdp->osh, flow_ring_table[idx].lock);
++		}
++		MFREE(dhdp->osh, flow_ring_table, flow_ring_table_sz);
++	}
++	id16_map_fini(dhdp->osh, flowid_allocator);
++
++	return BCME_NOMEM;
++}
++
++/** Deinit Flow Ring specific data structures */
++void dhd_flow_rings_deinit(dhd_pub_t *dhdp)
++{
++	uint16 idx;
++	uint32 flow_ring_table_sz;
++	uint32 if_flow_lkup_sz;
++	flow_ring_table_t *flow_ring_table;
++	unsigned long flags;
++	void *lock;
++
++	DHD_INFO(("dhd_flow_rings_deinit\n"));
++
++	if (!(dhdp->flow_rings_inited)) {
++		DHD_ERROR(("dhd_flow_rings not initialized!\n"));
++		return;
++	}
++
++	if (dhdp->flow_ring_table != NULL) {
++
++		ASSERT(dhdp->num_flow_rings > 0);
++
++		DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++		flow_ring_table = (flow_ring_table_t *)dhdp->flow_ring_table;
++		dhdp->flow_ring_table = NULL;
++		DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++		for (idx = 0; idx < dhdp->num_flow_rings; idx++) {
++			if (flow_ring_table[idx].active) {
++				dhd_bus_clean_flow_ring(dhdp->bus, &flow_ring_table[idx]);
++			}
++			ASSERT(DHD_FLOW_QUEUE_EMPTY(&flow_ring_table[idx].queue));
++
++			/* Deinit flow ring queue locks before destroying flow ring table */
++			if (flow_ring_table[idx].lock != NULL) {
++				dhd_os_spin_lock_deinit(dhdp->osh, flow_ring_table[idx].lock);
++			}
++			flow_ring_table[idx].lock = NULL;
++
++		}
++
++		/* Destruct the flow ring table */
++		flow_ring_table_sz = dhdp->num_flow_rings * sizeof(flow_ring_table_t);
++		MFREE(dhdp->osh, flow_ring_table, flow_ring_table_sz);
++	}
++
++	DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++
++	/* Destruct the per interface flow lkup table */
++	if (dhdp->if_flow_lkup != NULL) {
++		if_flow_lkup_sz = sizeof(if_flow_lkup_t) * DHD_MAX_IFS;
++		bzero((uchar *)dhdp->if_flow_lkup, if_flow_lkup_sz);
++		DHD_OS_PREFREE(dhdp, dhdp->if_flow_lkup, if_flow_lkup_sz);
++		dhdp->if_flow_lkup = NULL;
++	}
++
++	/* Destruct the flowid allocator */
++	if (dhdp->flowid_allocator != NULL)
++		dhdp->flowid_allocator = id16_map_fini(dhdp->osh, dhdp->flowid_allocator);
++
++	dhdp->num_flow_rings = 0U;
++	bzero(dhdp->flow_prio_map, sizeof(uint8) * NUMPRIO);
++
++	lock = dhdp->flowid_lock;
++	dhdp->flowid_lock = NULL;
++
++	if (lock) {
++		DHD_FLOWID_UNLOCK(lock, flags);
++		dhd_os_spin_lock_deinit(dhdp->osh, lock);
++	}
++
++	dhd_os_spin_lock_deinit(dhdp->osh, dhdp->flowring_list_lock);
++	dhdp->flowring_list_lock = NULL;
++
++	ASSERT(dhdp->if_flow_lkup == NULL);
++	ASSERT(dhdp->flowid_allocator == NULL);
++	ASSERT(dhdp->flow_ring_table == NULL);
++	dhdp->flow_rings_inited = FALSE;
++}
++
++/** Uses hash table to quickly map from ifindex to a flow ring 'role' (STA/AP) */
++uint8
++dhd_flow_rings_ifindex2role(dhd_pub_t *dhdp, uint8 ifindex)
++{
++	if_flow_lkup_t *if_flow_lkup = (if_flow_lkup_t *)dhdp->if_flow_lkup;
++	ASSERT(if_flow_lkup);
++	return if_flow_lkup[ifindex].role;
++}
++
++#ifdef WLTDLS
++bool is_tdls_destination(dhd_pub_t *dhdp, uint8 *da)
++{
++	unsigned long flags;
++	tdls_peer_node_t *cur = NULL;
++
++	DHD_TDLS_LOCK(&dhdp->tdls_lock, flags);
++	cur = dhdp->peer_tbl.node;
++
++	while (cur != NULL) {
++		if (!memcmp(da, cur->addr, ETHER_ADDR_LEN)) {
++			DHD_TDLS_UNLOCK(&dhdp->tdls_lock, flags);
++			return TRUE;
++		}
++		cur = cur->next;
++	}
++	DHD_TDLS_UNLOCK(&dhdp->tdls_lock, flags);
++	return FALSE;
++}
++#endif /* WLTDLS */
++
++/** Uses hash table to quickly map from ifindex+prio+da to a flow ring id */
++static INLINE uint16
++dhd_flowid_find(dhd_pub_t *dhdp, uint8 ifindex, uint8 prio, char *sa, char *da)
++{
++	int hash;
++	bool ismcast = FALSE;
++	flow_hash_info_t *cur;
++	if_flow_lkup_t *if_flow_lkup;
++	unsigned long flags;
++
++	DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++	if_flow_lkup = (if_flow_lkup_t *)dhdp->if_flow_lkup;
++
++	ASSERT(if_flow_lkup);
++
++	if ((if_flow_lkup[ifindex].role == WLC_E_IF_ROLE_STA) ||
++			(if_flow_lkup[ifindex].role == WLC_E_IF_ROLE_WDS)) {
++#ifdef WLTDLS
++		if (dhdp->peer_tbl.tdls_peer_count && !(ETHER_ISMULTI(da)) &&
++			is_tdls_destination(dhdp, da)) {
++			hash = DHD_FLOWRING_HASHINDEX(da, prio);
++			cur = if_flow_lkup[ifindex].fl_hash[hash];
++			while (cur != NULL) {
++				if (!memcmp(cur->flow_info.da, da, ETHER_ADDR_LEN)) {
++					DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++					return cur->flowid;
++				}
++				cur = cur->next;
++			}
++			DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++			return FLOWID_INVALID;
++		}
++#endif /* WLTDLS */
++		/* For STA non TDLS dest and WDS dest flow ring id is mapped based on prio only */
++		cur = if_flow_lkup[ifindex].fl_hash[prio];
++		if (cur) {
++			DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++			return cur->flowid;
++		}
++	} else {
++
++		if (ETHER_ISMULTI(da)) {
++			ismcast = TRUE;
++			hash = 0;
++		} else {
++			hash = DHD_FLOWRING_HASHINDEX(da, prio);
++		}
++
++		cur = if_flow_lkup[ifindex].fl_hash[hash];
++
++		while (cur) {
++			if ((ismcast && ETHER_ISMULTI(cur->flow_info.da)) ||
++				(!memcmp(cur->flow_info.da, da, ETHER_ADDR_LEN) &&
++				(cur->flow_info.tid == prio))) {
++				DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++				return cur->flowid;
++			}
++			cur = cur->next;
++		}
++	}
++	DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++
++	DHD_INFO(("%s: cannot find flowid\n", __FUNCTION__));
++	return FLOWID_INVALID;
++} /* dhd_flowid_find */
++
++/** Create unique Flow ID, called when a flow ring is created. */
++static INLINE uint16
++dhd_flowid_alloc(dhd_pub_t *dhdp, uint8 ifindex, uint8 prio, char *sa, char *da)
++{
++	flow_hash_info_t *fl_hash_node, *cur;
++	if_flow_lkup_t *if_flow_lkup;
++	int hash;
++	uint16 flowid;
++	unsigned long flags;
++
++	fl_hash_node = (flow_hash_info_t *) MALLOCZ(dhdp->osh, sizeof(flow_hash_info_t));
++	if (fl_hash_node == NULL) {
++		DHD_ERROR(("%s: flow_hash_info_t memory allocation failed \n", __FUNCTION__));
++		return FLOWID_INVALID;
++	}
++	memcpy(fl_hash_node->flow_info.da, da, sizeof(fl_hash_node->flow_info.da));
++
++	DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++	ASSERT(dhdp->flowid_allocator != NULL);
++	flowid = id16_map_alloc(dhdp->flowid_allocator);
++	DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++
++	if (flowid == FLOWID_INVALID) {
++		MFREE(dhdp->osh, fl_hash_node,  sizeof(flow_hash_info_t));
++		DHD_ERROR(("%s: cannot get free flowid \n", __FUNCTION__));
++		return FLOWID_INVALID;
++	}
++
++	fl_hash_node->flowid = flowid;
++	fl_hash_node->flow_info.tid = prio;
++	fl_hash_node->flow_info.ifindex = ifindex;
++	fl_hash_node->next = NULL;
++
++	DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++	if_flow_lkup = (if_flow_lkup_t *)dhdp->if_flow_lkup;
++
++	if ((if_flow_lkup[ifindex].role == WLC_E_IF_ROLE_STA) ||
++			(if_flow_lkup[ifindex].role == WLC_E_IF_ROLE_WDS)) {
++		/* For STA non TDLS dest and WDS dest we allocate entry based on prio only */
++#ifdef WLTDLS
++		if (dhdp->peer_tbl.tdls_peer_count &&
++			(is_tdls_destination(dhdp, da))) {
++			hash = DHD_FLOWRING_HASHINDEX(da, prio);
++			cur = if_flow_lkup[ifindex].fl_hash[hash];
++			if (cur) {
++				while (cur->next) {
++					cur = cur->next;
++				}
++				cur->next = fl_hash_node;
++			} else {
++				if_flow_lkup[ifindex].fl_hash[hash] = fl_hash_node;
++			}
++		} else
++#endif /* WLTDLS */
++			if_flow_lkup[ifindex].fl_hash[prio] = fl_hash_node;
++	} else {
++
++		/* For bcast/mcast assign first slot in in interface */
++		hash = ETHER_ISMULTI(da) ? 0 : DHD_FLOWRING_HASHINDEX(da, prio);
++		cur = if_flow_lkup[ifindex].fl_hash[hash];
++		if (cur) {
++			while (cur->next) {
++				cur = cur->next;
++			}
++			cur->next = fl_hash_node;
++		} else
++			if_flow_lkup[ifindex].fl_hash[hash] = fl_hash_node;
++	}
++	DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++
++	DHD_INFO(("%s: allocated flowid %d\n", __FUNCTION__, fl_hash_node->flowid));
++
++	return fl_hash_node->flowid;
++} /* dhd_flowid_alloc */
++
++/** Get flow ring ID, if not present try to create one */
++static INLINE int
++dhd_flowid_lookup(dhd_pub_t *dhdp, uint8 ifindex,
++                  uint8 prio, char *sa, char *da, uint16 *flowid)
++{
++	uint16 id;
++	flow_ring_node_t *flow_ring_node;
++	flow_ring_table_t *flow_ring_table;
++	unsigned long flags;
++	int ret;
++	bool is_sta_assoc;
++
++	DHD_INFO(("%s\n", __FUNCTION__));
++	if (!dhdp->flow_ring_table) {
++		return BCME_ERROR;
++	}
++
++	flow_ring_table = (flow_ring_table_t *)dhdp->flow_ring_table;
++
++	id = dhd_flowid_find(dhdp, ifindex, prio, sa, da);
++
++	if (id == FLOWID_INVALID) {
++
++		if_flow_lkup_t *if_flow_lkup;
++		if_flow_lkup = (if_flow_lkup_t *)dhdp->if_flow_lkup;
++
++		if (!if_flow_lkup[ifindex].status)
++			return BCME_ERROR;
++		BCM_REFERENCE(is_sta_assoc);
++#if defined(PCIE_FULL_DONGLE)
++		is_sta_assoc = dhd_sta_associated(dhdp, ifindex, (uint8 *)da);
++		DHD_ERROR(("%s: multi %x ifindex %d role %x assoc %d\n", __FUNCTION__,
++			ETHER_ISMULTI(da), ifindex, if_flow_lkup[ifindex].role,
++			is_sta_assoc));
++		if (!ETHER_ISMULTI(da) &&
++		    ((if_flow_lkup[ifindex].role == WLC_E_IF_ROLE_AP) ||
++		    (if_flow_lkup[ifindex].role == WLC_E_IF_ROLE_P2P_GO)) &&
++		    (!is_sta_assoc))
++			return BCME_ERROR;
++#endif /* (linux || LINUX) && PCIE_FULL_DONGLE */
++
++		id = dhd_flowid_alloc(dhdp, ifindex, prio, sa, da);
++		if (id == FLOWID_INVALID) {
++			DHD_ERROR(("%s: alloc flowid ifindex %u status %u\n",
++			           __FUNCTION__, ifindex, if_flow_lkup[ifindex].status));
++			return BCME_ERROR;
++		}
++
++		ASSERT(id < dhdp->num_flow_rings);
++
++		/* register this flowid in dhd_pub */
++		dhd_add_flowid(dhdp, ifindex, prio, da, id);
++
++		flow_ring_node = (flow_ring_node_t *) &flow_ring_table[id];
++
++		DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++
++		/* Init Flow info */
++		memcpy(flow_ring_node->flow_info.sa, sa, sizeof(flow_ring_node->flow_info.sa));
++		memcpy(flow_ring_node->flow_info.da, da, sizeof(flow_ring_node->flow_info.da));
++		flow_ring_node->flow_info.tid = prio;
++		flow_ring_node->flow_info.ifindex = ifindex;
++		flow_ring_node->active = TRUE;
++		flow_ring_node->status = FLOW_RING_STATUS_CREATE_PENDING;
++
++#ifdef DEVICE_TX_STUCK_DETECT
++		flow_ring_node->tx_cmpl = flow_ring_node->tx_cmpl_prev = OSL_SYSUPTIME();
++		flow_ring_node->stuck_count = 0;
++#endif /* DEVICE_TX_STUCK_DETECT */
++
++		DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++
++		/* Create and inform device about the new flow */
++		if (dhd_bus_flow_ring_create_request(dhdp->bus, (void *)flow_ring_node)
++				!= BCME_OK) {
++			DHD_ERROR(("%s: create error %d\n", __FUNCTION__, id));
++			return BCME_ERROR;
++		}
++
++		*flowid = id;
++		return BCME_OK;
++	} else {
++		/* if the Flow id was found in the hash */
++		ASSERT(id < dhdp->num_flow_rings);
++
++		flow_ring_node = (flow_ring_node_t *) &flow_ring_table[id];
++		DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++
++		/*
++		 * If the flow_ring_node is in Open State or Status pending state then
++		 * we can return the Flow id to the caller.If the flow_ring_node is in
++		 * FLOW_RING_STATUS_PENDING this means the creation is in progress and
++		 * hence the packets should be queued.
++		 *
++		 * If the flow_ring_node is in FLOW_RING_STATUS_DELETE_PENDING Or
++		 * FLOW_RING_STATUS_CLOSED, then we should return Error.
++		 * Note that if the flowing is being deleted we would mark it as
++		 * FLOW_RING_STATUS_DELETE_PENDING.  Now before Dongle could respond and
++		 * before we mark it as FLOW_RING_STATUS_CLOSED we could get tx packets.
++		 * We should drop the packets in that case.
++		 * The decission to return OK should NOT be based on 'active' variable, beause
++		 * active is made TRUE when a flow_ring_node gets allocated and is made
++		 * FALSE when the flow ring gets removed and does not reflect the True state
++		 * of the Flow ring.
++		 * In case if IDLE_TX_FLOW_MGMT is defined, we have to handle two more flowring
++		 * states. If the flow_ring_node's status is FLOW_RING_STATUS_SUSPENDED, the flowid
++		 * is to be returned and from dhd_bus_txdata, the flowring would be resumed again.
++		 * The status FLOW_RING_STATUS_RESUME_PENDING, is equivalent to
++		 * FLOW_RING_STATUS_CREATE_PENDING.
++		 */
++		if (flow_ring_node->status == FLOW_RING_STATUS_DELETE_PENDING ||
++			flow_ring_node->status == FLOW_RING_STATUS_CLOSED) {
++			*flowid = FLOWID_INVALID;
++			ret = BCME_ERROR;
++		} else {
++			*flowid = id;
++			ret = BCME_OK;
++		}
++
++		DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++		return ret;
++	} /* Flow Id found in the hash */
++} /* dhd_flowid_lookup */
++
++/**
++ * Assign existing or newly created flowid to an 802.3 packet. This flowid is later on used to
++ * select the flowring to send the packet to the dongle.
++ */
++int BCMFASTPATH
++dhd_flowid_update(dhd_pub_t *dhdp, uint8 ifindex, uint8 prio, void *pktbuf)
++{
++	uint8 *pktdata = (uint8 *)PKTDATA(dhdp->osh, pktbuf);
++	struct ether_header *eh = (struct ether_header *)pktdata;
++	uint16 flowid;
++
++	ASSERT(ifindex < DHD_MAX_IFS);
++
++	if (ifindex >= DHD_MAX_IFS) {
++		return BCME_BADARG;
++	}
++
++	if (!dhdp->flowid_allocator) {
++		DHD_ERROR(("%s: Flow ring not intited yet  \n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	if (dhd_flowid_lookup(dhdp, ifindex, prio, (char *)eh->ether_shost, (char *)eh->ether_dhost,
++		&flowid) != BCME_OK) {
++		return BCME_ERROR;
++	}
++
++	DHD_INFO(("%s: prio %d flowid %d\n", __FUNCTION__, prio, flowid));
++
++	/* Tag the packet with flowid */
++	DHD_PKT_SET_FLOWID(pktbuf, flowid);
++	return BCME_OK;
++}
++
++void
++dhd_flowid_free(dhd_pub_t *dhdp, uint8 ifindex, uint16 flowid)
++{
++	int hashix;
++	bool found = FALSE;
++	flow_hash_info_t *cur, *prev;
++	if_flow_lkup_t *if_flow_lkup;
++	unsigned long flags;
++
++	DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++	if_flow_lkup = (if_flow_lkup_t *)dhdp->if_flow_lkup;
++
++	for (hashix = 0; hashix < DHD_FLOWRING_HASH_SIZE; hashix++) {
++
++		cur = if_flow_lkup[ifindex].fl_hash[hashix];
++
++		if (cur) {
++			if (cur->flowid == flowid) {
++				found = TRUE;
++			}
++
++			prev = NULL;
++			while (!found && cur) {
++				if (cur->flowid == flowid) {
++					found = TRUE;
++					break;
++				}
++				prev = cur;
++				cur = cur->next;
++			}
++			if (found) {
++				if (!prev) {
++					if_flow_lkup[ifindex].fl_hash[hashix] = cur->next;
++				} else {
++					prev->next = cur->next;
++				}
++
++				/* deregister flowid from dhd_pub. */
++				dhd_del_flowid(dhdp, ifindex, flowid);
++
++				id16_map_free(dhdp->flowid_allocator, flowid);
++				DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++				MFREE(dhdp->osh, cur, sizeof(flow_hash_info_t));
++
++				return;
++			}
++		}
++	}
++
++	DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++	DHD_ERROR(("%s: could not free flow ring hash entry flowid %d\n",
++	           __FUNCTION__, flowid));
++} /* dhd_flowid_free */
++
++/**
++ * Delete all Flow rings associated with the given interface. Is called when eg the dongle
++ * indicates that a wireless link has gone down.
++ */
++void
++dhd_flow_rings_delete(dhd_pub_t *dhdp, uint8 ifindex)
++{
++	uint32 id;
++	flow_ring_table_t *flow_ring_table;
++
++	DHD_ERROR(("%s: ifindex %u\n", __FUNCTION__, ifindex));
++
++	ASSERT(ifindex < DHD_MAX_IFS);
++	if (ifindex >= DHD_MAX_IFS)
++		return;
++
++	if (!dhdp->flow_ring_table)
++		return;
++
++	flow_ring_table = (flow_ring_table_t *)dhdp->flow_ring_table;
++	for (id = 0; id < dhdp->num_flow_rings; id++) {
++		if (flow_ring_table[id].active &&
++			(flow_ring_table[id].flow_info.ifindex == ifindex) &&
++			(flow_ring_table[id].status == FLOW_RING_STATUS_OPEN)) {
++			dhd_bus_flow_ring_delete_request(dhdp->bus,
++			                                 (void *) &flow_ring_table[id]);
++		}
++	}
++}
++
++void
++dhd_flow_rings_flush(dhd_pub_t *dhdp, uint8 ifindex)
++{
++	uint32 id;
++	flow_ring_table_t *flow_ring_table;
++
++	DHD_INFO(("%s: ifindex %u\n", __FUNCTION__, ifindex));
++
++	ASSERT(ifindex < DHD_MAX_IFS);
++	if (ifindex >= DHD_MAX_IFS)
++		return;
++
++	if (!dhdp->flow_ring_table)
++		return;
++	flow_ring_table = (flow_ring_table_t *)dhdp->flow_ring_table;
++
++	for (id = 0; id <= dhdp->num_flow_rings; id++) {
++		if (flow_ring_table[id].active &&
++			(flow_ring_table[id].flow_info.ifindex == ifindex) &&
++			(flow_ring_table[id].status == FLOW_RING_STATUS_OPEN)) {
++			dhd_bus_flow_ring_flush_request(dhdp->bus,
++			                                 (void *) &flow_ring_table[id]);
++		}
++	}
++}
++
++
++/** Delete flow ring(s) for given peer address. Related to AP/AWDL/TDLS functionality. */
++void
++dhd_flow_rings_delete_for_peer(dhd_pub_t *dhdp, uint8 ifindex, char *addr)
++{
++	uint32 id;
++	flow_ring_table_t *flow_ring_table;
++
++	DHD_ERROR(("%s: ifindex %u\n", __FUNCTION__, ifindex));
++
++	ASSERT(ifindex < DHD_MAX_IFS);
++	if (ifindex >= DHD_MAX_IFS)
++		return;
++
++	if (!dhdp->flow_ring_table)
++		return;
++
++	flow_ring_table = (flow_ring_table_t *)dhdp->flow_ring_table;
++	for (id = 0; id < dhdp->num_flow_rings; id++) {
++		if (flow_ring_table[id].active &&
++			(flow_ring_table[id].flow_info.ifindex == ifindex) &&
++			(!memcmp(flow_ring_table[id].flow_info.da, addr, ETHER_ADDR_LEN)) &&
++			(flow_ring_table[id].status == FLOW_RING_STATUS_OPEN)) {
++			DHD_ERROR(("%s: deleting flowid %d\n",
++				__FUNCTION__, flow_ring_table[id].flowid));
++			dhd_bus_flow_ring_delete_request(dhdp->bus,
++				(void *) &flow_ring_table[id]);
++		}
++	}
++}
++
++/** Handles interface ADD, CHANGE, DEL indications from the dongle */
++void
++dhd_update_interface_flow_info(dhd_pub_t *dhdp, uint8 ifindex,
++                               uint8 op, uint8 role)
++{
++	if_flow_lkup_t *if_flow_lkup;
++	unsigned long flags;
++
++	ASSERT(ifindex < DHD_MAX_IFS);
++	if (ifindex >= DHD_MAX_IFS)
++		return;
++
++	DHD_ERROR(("%s: ifindex %u op %u role is %u \n",
++	          __FUNCTION__, ifindex, op, role));
++	if (!dhdp->flowid_allocator) {
++		DHD_ERROR(("%s: Flow ring not intited yet  \n", __FUNCTION__));
++		return;
++	}
++
++	DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++	if_flow_lkup = (if_flow_lkup_t *)dhdp->if_flow_lkup;
++
++	if (op == WLC_E_IF_ADD || op == WLC_E_IF_CHANGE) {
++
++		if_flow_lkup[ifindex].role = role;
++
++		if (role == WLC_E_IF_ROLE_WDS) {
++			/**
++			 * WDS role does not send WLC_E_LINK event after interface is up.
++			 * So to create flowrings for WDS, make status as TRUE in WLC_E_IF itself.
++			 * same is true while making the status as FALSE.
++			 * TODO: Fix FW to send WLC_E_LINK for WDS role aswell. So that all the
++			 * interfaces are handled uniformly.
++			 */
++			if_flow_lkup[ifindex].status = TRUE;
++			DHD_INFO(("%s: Mcast Flow ring for ifindex %d role is %d \n",
++			          __FUNCTION__, ifindex, role));
++		}
++	} else	if ((op == WLC_E_IF_DEL) && (role == WLC_E_IF_ROLE_WDS)) {
++		if_flow_lkup[ifindex].status = FALSE;
++		DHD_INFO(("%s: cleanup all Flow rings for ifindex %d role is %d \n",
++		          __FUNCTION__, ifindex, role));
++	}
++	DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++}
++
++/** Handles a STA 'link' indication from the dongle */
++int
++dhd_update_interface_link_status(dhd_pub_t *dhdp, uint8 ifindex, uint8 status)
++{
++	if_flow_lkup_t *if_flow_lkup;
++	unsigned long flags;
++
++	ASSERT(ifindex < DHD_MAX_IFS);
++	if (ifindex >= DHD_MAX_IFS)
++		return BCME_BADARG;
++
++	DHD_ERROR(("%s: ifindex %d status %d\n", __FUNCTION__, ifindex, status));
++
++	DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++	if_flow_lkup = (if_flow_lkup_t *)dhdp->if_flow_lkup;
++
++	if (status) {
++		if_flow_lkup[ifindex].status = TRUE;
++	} else {
++		if_flow_lkup[ifindex].status = FALSE;
++	}
++
++	DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++
++	return BCME_OK;
++}
++
++/** Update flow priority mapping, called on IOVAR */
++int dhd_update_flow_prio_map(dhd_pub_t *dhdp, uint8 map)
++{
++	uint16 flowid;
++	flow_ring_node_t *flow_ring_node;
++
++	if (map > DHD_FLOW_PRIO_LLR_MAP)
++		return BCME_BADOPTION;
++
++	/* Check if we need to change prio map */
++	if (map == dhdp->flow_prio_map_type)
++		return BCME_OK;
++
++	/* If any ring is active we cannot change priority mapping for flow rings */
++	for (flowid = 0; flowid < dhdp->num_flow_rings; flowid++) {
++		flow_ring_node = DHD_FLOW_RING(dhdp, flowid);
++		if (flow_ring_node->active)
++			return BCME_EPERM;
++	}
++
++	/* Inform firmware about new mapping type */
++	if (BCME_OK != dhd_flow_prio_map(dhdp, &map, TRUE))
++		return BCME_ERROR;
++
++	/* update internal structures */
++	dhdp->flow_prio_map_type = map;
++	if (dhdp->flow_prio_map_type == DHD_FLOW_PRIO_TID_MAP)
++		bcopy(prio2tid, dhdp->flow_prio_map, sizeof(uint8) * NUMPRIO);
++	else
++		bcopy(prio2ac, dhdp->flow_prio_map, sizeof(uint8) * NUMPRIO);
++
++	return BCME_OK;
++}
++
++/** Inform firmware on updated flow priority mapping, called on IOVAR */
++int dhd_flow_prio_map(dhd_pub_t *dhd, uint8 *map, bool set)
++{
++	uint8 iovbuf[24] = {0};
++	if (!set) {
++		bcm_mkiovar("bus:fl_prio_map", NULL, 0, (char*)iovbuf, sizeof(iovbuf));
++		if (dhd_wl_ioctl_cmd(dhd, WLC_GET_VAR, iovbuf, sizeof(iovbuf), FALSE, 0) < 0) {
++			DHD_ERROR(("%s: failed to get fl_prio_map\n", __FUNCTION__));
++			return BCME_ERROR;
++		}
++		*map = iovbuf[0];
++		return BCME_OK;
++	}
++	bcm_mkiovar("bus:fl_prio_map", (char *)map, 4, (char*)iovbuf, sizeof(iovbuf));
++	if (dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, iovbuf, sizeof(iovbuf), TRUE, 0) < 0) {
++		DHD_ERROR(("%s: failed to set fl_prio_map \n",
++			__FUNCTION__));
++		return BCME_ERROR;
++	}
++	return BCME_OK;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_flowring.h b/module_drivers/drivers/net/wireless/bcmdhd/dhd_flowring.h
+new file mode 100644
+index 000000000..d5faf0aa8
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_flowring.h
+@@ -0,0 +1,275 @@
++/*
++ * @file Header file describing the flow rings DHD interfaces.
++ *
++ * Flow rings are transmit traffic (=propagating towards antenna) related entities.
++ *
++ * Provides type definitions and function prototypes used to create, delete and manage flow rings at
++ * high level.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_flowring.h 672438 2016-11-28 12:35:24Z $
++ */
++
++
++/****************
++ * Common types *
++ */
++
++#ifndef _dhd_flowrings_h_
++#define _dhd_flowrings_h_
++
++/* Max pkts held in a flow ring's backup queue */
++#define FLOW_RING_QUEUE_THRESHOLD       (2048)
++
++/* Number of H2D common rings */
++#define FLOW_RING_COMMON                BCMPCIE_H2D_COMMON_MSGRINGS
++
++#define FLOWID_INVALID                  (ID16_INVALID)
++#define FLOWID_RESERVED                 (FLOW_RING_COMMON)
++
++#define FLOW_RING_STATUS_OPEN           0
++#define FLOW_RING_STATUS_CREATE_PENDING	1
++#define FLOW_RING_STATUS_CLOSED         2
++#define FLOW_RING_STATUS_DELETE_PENDING 3
++#define FLOW_RING_STATUS_FLUSH_PENDING  4
++
++#ifdef IDLE_TX_FLOW_MGMT
++#define FLOW_RING_STATUS_SUSPENDED	5
++#define FLOW_RING_STATUS_RESUME_PENDING	6
++#endif /* IDLE_TX_FLOW_MGMT */
++#define FLOW_RING_STATUS_STA_FREEING    7
++
++#ifdef DHD_EFI
++#define DHD_FLOWRING_RX_BUFPOST_PKTSZ	1600
++#else
++#define DHD_FLOWRING_RX_BUFPOST_PKTSZ	2048
++#endif
++
++#define DHD_FLOW_PRIO_AC_MAP		0
++#define DHD_FLOW_PRIO_TID_MAP		1
++/* Flow ring prority map for lossless roaming */
++#define DHD_FLOW_PRIO_LLR_MAP		2
++
++/* Hashing a MacAddress for lkup into a per interface flow hash table */
++#define DHD_FLOWRING_HASH_SIZE    256
++#define	DHD_FLOWRING_HASHINDEX(ea, prio) \
++	       ((((uint8 *)(ea))[3] ^ ((uint8 *)(ea))[4] ^ ((uint8 *)(ea))[5] ^ ((uint8)(prio))) \
++		% DHD_FLOWRING_HASH_SIZE)
++
++#define DHD_IF_ROLE(pub, idx)		(((if_flow_lkup_t *)(pub)->if_flow_lkup)[idx].role)
++#define DHD_IF_ROLE_AP(pub, idx)	(DHD_IF_ROLE(pub, idx) == WLC_E_IF_ROLE_AP)
++#define DHD_IF_ROLE_STA(pub, idx)	(DHD_IF_ROLE(pub, idx) == WLC_E_IF_ROLE_STA)
++#define DHD_IF_ROLE_P2PGO(pub, idx)	(DHD_IF_ROLE(pub, idx) == WLC_E_IF_ROLE_P2P_GO)
++#define DHD_IF_ROLE_WDS(pub, idx)	(DHD_IF_ROLE(pub, idx) == WLC_E_IF_ROLE_WDS)
++#define DHD_FLOW_RING(dhdp, flowid) \
++	(flow_ring_node_t *)&(((flow_ring_node_t *)((dhdp)->flow_ring_table))[flowid])
++
++struct flow_queue;
++
++/* Flow Ring Queue Enqueue overflow callback */
++typedef int (*flow_queue_cb_t)(struct flow_queue * queue, void * pkt);
++
++/**
++ * Each flow ring has an associated (tx flow controlled) queue. 802.3 packets are transferred
++ * between queue and ring. A packet from the host stack is first added to the queue, and in a later
++ * stage transferred to the flow ring. Packets in the queue are dhd owned, whereas packets in the
++ * flow ring are device owned.
++ */
++typedef struct flow_queue {
++	dll_t  list;                /* manage a flowring queue in a double linked list */
++	void * head;                /* first packet in the queue */
++	void * tail;                /* last packet in the queue */
++	uint16 len;                 /* number of packets in the queue */
++	uint16 max;                 /* maximum or min budget (used in cumm) */
++	uint32 threshold;           /* parent's cummulative length threshold */
++	void * clen_ptr;            /* parent's cummulative length counter */
++	uint32 failures;            /* enqueue failures due to queue overflow */
++	flow_queue_cb_t cb;         /* callback invoked on threshold crossing */
++	uint32 l2threshold;         /* grandparent's (level 2) cummulative length threshold */
++	void * l2clen_ptr;          /* grandparent's (level 2) cummulative length counter */
++} flow_queue_t;
++
++#define DHD_FLOW_QUEUE_LEN(queue)       ((int)(queue)->len)
++#define DHD_FLOW_QUEUE_MAX(queue)       ((int)(queue)->max)
++#define DHD_FLOW_QUEUE_THRESHOLD(queue) ((int)(queue)->threshold)
++#define DHD_FLOW_QUEUE_L2THRESHOLD(queue) ((int)(queue)->l2threshold)
++#define DHD_FLOW_QUEUE_EMPTY(queue)     ((queue)->len == 0)
++#define DHD_FLOW_QUEUE_FAILURES(queue)  ((queue)->failures)
++
++#define DHD_FLOW_QUEUE_AVAIL(queue)     ((int)((queue)->max - (queue)->len))
++#define DHD_FLOW_QUEUE_FULL(queue)      ((queue)->len >= (queue)->max)
++
++#define DHD_FLOW_QUEUE_OVFL(queue, budget)  \
++	(((queue)->len) > budget)
++
++#define DHD_FLOW_QUEUE_SET_MAX(queue, budget) \
++	((queue)->max) = ((budget) - 1)
++
++/* Queue's cummulative threshold. */
++#define DHD_FLOW_QUEUE_SET_THRESHOLD(queue, cumm_threshold) \
++	((queue)->threshold) = ((cumm_threshold) - 1)
++
++/* Queue's cummulative length object accessor. */
++#define DHD_FLOW_QUEUE_CLEN_PTR(queue)  ((queue)->clen_ptr)
++
++/* Set a queue's cumm_len point to a parent's cumm_ctr_t cummulative length */
++#define DHD_FLOW_QUEUE_SET_CLEN(queue, parent_clen_ptr)  \
++	((queue)->clen_ptr) = (void *)(parent_clen_ptr)
++
++/* Queue's level 2 cummulative threshold. */
++#define DHD_FLOW_QUEUE_SET_L2THRESHOLD(queue, l2cumm_threshold) \
++	((queue)->l2threshold) = ((l2cumm_threshold) - 1)
++
++/* Queue's level 2 cummulative length object accessor. */
++#define DHD_FLOW_QUEUE_L2CLEN_PTR(queue)  ((queue)->l2clen_ptr)
++
++/* Set a queue's level 2 cumm_len point to a grandparent's cumm_ctr_t cummulative length */
++#define DHD_FLOW_QUEUE_SET_L2CLEN(queue, grandparent_clen_ptr)  \
++	((queue)->l2clen_ptr) = (void *)(grandparent_clen_ptr)
++
++/*  see wlfc_proto.h for tx status details */
++#define DHD_FLOWRING_MAXSTATUS_MSGS	5
++#define DHD_FLOWRING_TXSTATUS_CNT_UPDATE(bus, flowid, txstatus)
++
++/* Pkttag not compatible with PROP_TXSTATUS or WLFC */
++typedef struct dhd_pkttag_fr {
++	uint16  flowid;
++	uint16  ifid;
++	int     dataoff;
++	dmaaddr_t physaddr;
++	uint32 pa_len;
++} dhd_pkttag_fr_t;
++
++#define DHD_PKTTAG_SET_IFID(tag, idx)       ((tag)->ifid = (uint16)(idx))
++#define DHD_PKTTAG_SET_PA(tag, pa)          ((tag)->physaddr = (pa))
++#define DHD_PKTTAG_SET_PA_LEN(tag, palen)   ((tag)->pa_len = (palen))
++#define DHD_PKTTAG_IFID(tag)                ((tag)->ifid)
++#define DHD_PKTTAG_PA(tag)                  ((tag)->physaddr)
++#define DHD_PKTTAG_PA_LEN(tag)              ((tag)->pa_len)
++
++
++/** each flow ring is dedicated to a tid/sa/da combination */
++typedef struct flow_info {
++	uint8		tid;
++	uint8		ifindex;
++	char		sa[ETHER_ADDR_LEN];
++	char		da[ETHER_ADDR_LEN];
++} flow_info_t;
++
++/** a flow ring is used for outbound (towards antenna) 802.3 packets */
++typedef struct flow_ring_node {
++	dll_t		list;  /* manage a constructed flowring in a dll, must be at first place */
++	flow_queue_t	queue; /* queues packets before they enter the flow ring, flow control */
++	bool		active;
++	uint8		status;
++	/*
++	 * flowid: unique ID of a flow ring, which can either be unicast or broadcast/multicast. For
++	 * unicast flow rings, the flow id accelerates ARM 802.3->802.11 header translation.
++	 */
++	uint16		flowid;
++	flow_info_t	flow_info;
++	void		*prot_info;
++	void		*lock; /* lock for flowring access protection */
++
++#ifdef IDLE_TX_FLOW_MGMT
++	uint64		last_active_ts; /* contains last active timestamp */
++#endif /* IDLE_TX_FLOW_MGMT */
++#ifdef DEVICE_TX_STUCK_DETECT
++	/* Time stamp(msec) when last time a Tx packet completion is received on this flow ring */
++	uint32		tx_cmpl;
++	/*
++	 * Holds the tx_cmpl which was read during the previous
++	 * iteration of the stuck detection algo
++	 */
++	uint32		tx_cmpl_prev;
++	/* counter to decide if this particlur flow is stuck or not */
++	uint32		stuck_count;
++#endif /* DEVICE_TX_STUCK_DETECT */
++
++} flow_ring_node_t;
++
++typedef flow_ring_node_t flow_ring_table_t;
++
++typedef struct flow_hash_info {
++	uint16			flowid;
++	flow_info_t		flow_info;
++	struct flow_hash_info	*next;
++} flow_hash_info_t;
++
++typedef struct if_flow_lkup {
++	bool		status;
++	uint8		role; /* Interface role: STA/AP */
++	flow_hash_info_t *fl_hash[DHD_FLOWRING_HASH_SIZE]; /* Lkup Hash table */
++} if_flow_lkup_t;
++
++static INLINE flow_ring_node_t *
++dhd_constlist_to_flowring(dll_t *item)
++{
++	return ((flow_ring_node_t *)item);
++}
++
++/* Exported API */
++
++/* Flow ring's queue management functions */
++extern flow_ring_node_t * dhd_flow_ring_node(dhd_pub_t *dhdp, uint16 flowid);
++extern flow_queue_t * dhd_flow_queue(dhd_pub_t *dhdp, uint16 flowid);
++
++extern void dhd_flow_queue_init(dhd_pub_t *dhdp, flow_queue_t *queue, int max);
++extern void dhd_flow_queue_reinit(dhd_pub_t *dhdp, flow_queue_t *queue, int max);
++extern void dhd_flow_queue_register(flow_queue_t *queue, flow_queue_cb_t cb);
++extern int  dhd_flow_queue_enqueue(dhd_pub_t *dhdp, flow_queue_t *queue, void *pkt);
++extern void * dhd_flow_queue_dequeue(dhd_pub_t *dhdp, flow_queue_t *queue);
++extern void dhd_flow_queue_reinsert(dhd_pub_t *dhdp, flow_queue_t *queue, void *pkt);
++
++extern void dhd_flow_ring_config_thresholds(dhd_pub_t *dhdp, uint16 flowid,
++                          int queue_budget, int cumm_threshold, void *cumm_ctr,
++                          int l2cumm_threshold, void *l2cumm_ctr);
++extern int  dhd_flow_rings_init(dhd_pub_t *dhdp, uint32 num_flow_rings);
++
++extern void dhd_flow_rings_deinit(dhd_pub_t *dhdp);
++
++extern int dhd_flowid_update(dhd_pub_t *dhdp, uint8 ifindex, uint8 prio,
++                void *pktbuf);
++
++extern void dhd_flowid_free(dhd_pub_t *dhdp, uint8 ifindex, uint16 flowid);
++
++extern void dhd_flow_rings_delete(dhd_pub_t *dhdp, uint8 ifindex);
++extern void dhd_flow_rings_flush(dhd_pub_t *dhdp, uint8 ifindex);
++
++extern void dhd_flow_rings_delete_for_peer(dhd_pub_t *dhdp, uint8 ifindex,
++                char *addr);
++
++/* Handle Interface ADD, DEL operations */
++extern void dhd_update_interface_flow_info(dhd_pub_t *dhdp, uint8 ifindex,
++                uint8 op, uint8 role);
++
++/* Handle a STA interface link status update */
++extern int dhd_update_interface_link_status(dhd_pub_t *dhdp, uint8 ifindex,
++                uint8 status);
++extern int dhd_flow_prio_map(dhd_pub_t *dhd, uint8 *map, bool set);
++extern int dhd_update_flow_prio_map(dhd_pub_t *dhdp, uint8 map);
++
++extern uint8 dhd_flow_rings_ifindex2role(dhd_pub_t *dhdp, uint8 ifindex);
++#endif /* _dhd_flowrings_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_gpio.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_gpio.c
+new file mode 100644
+index 000000000..d5d2b9b06
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_gpio.c
+@@ -0,0 +1,360 @@
++
++#include <osl.h>
++#include <dhd_linux.h>
++#include <linux/gpio.h>
++
++#ifdef CUSTOMER_HW_PLATFORM
++#include <plat/sdhci.h>
++#define	sdmmc_channel	sdmmc_device_mmc0
++#endif /* CUSTOMER_HW_PLATFORM */
++
++#if defined(BUS_POWER_RESTORE) && defined(BCMSDIO)
++#include <linux/mmc/core.h>
++#include <linux/mmc/card.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/sdio_func.h>
++#endif /* defined(BUS_POWER_RESTORE) && defined(BCMSDIO) */
++
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++extern void *dhd_wlan_mem_prealloc(int section, unsigned long size);
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++
++static int gpio_wl_reg_on = -1; // WL_REG_ON is input pin of WLAN module
++#ifdef CUSTOMER_OOB
++static int gpio_wl_host_wake = -1; // WL_HOST_WAKE is output pin of WLAN module
++#endif
++
++#ifdef CUSTOMER_HW_INGENIC
++extern int ingenic_sdio_wlan_power_onoff(int onoff, int flag);
++extern int ingenic_sdio_wlan_get_irq(unsigned long *flag);
++#define RESET  0
++#define NORMAL 1
++static int poweroff_num = 0;
++static int poweron_num = 0;
++#endif
++
++static int
++dhd_wlan_set_power(int on
++#ifdef BUS_POWER_RESTORE
++, wifi_adapter_info_t *adapter
++#endif /* BUS_POWER_RESTORE */
++)
++{
++	int err = 0;
++
++	if (on) {
++		printf("======== PULL WL_REG_ON(%d) HIGH! ========\n", gpio_wl_reg_on);
++		if (gpio_wl_reg_on >= 0) {
++			err = gpio_direction_output(gpio_wl_reg_on, 1);
++			if (err) {
++				printf("%s: WL_REG_ON didn't output high\n", __FUNCTION__);
++				return -EIO;
++			}
++		}
++#ifdef CUSTOMER_HW_INGENIC
++		if (poweron_num) {
++			ingenic_sdio_wlan_power_onoff(on, RESET);
++		} else {
++			poweron_num = 1;
++			ingenic_sdio_wlan_power_onoff(on, NORMAL);
++		}
++#endif
++#if defined(BUS_POWER_RESTORE)
++#if defined(BCMSDIO) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0))
++		if (adapter->sdio_func && adapter->sdio_func->card && adapter->sdio_func->card->host) {
++			mdelay(100);
++			printf("======== mmc_power_restore_host! ========\n");
++			mmc_power_restore_host(adapter->sdio_func->card->host);
++		}
++#elif defined(BCMPCIE)
++		if (adapter->pci_dev) {
++			mdelay(100);
++			printf("======== pci_set_power_state PCI_D0! ========\n");
++			pci_set_power_state(adapter->pci_dev, PCI_D0);
++			if (adapter->pci_saved_state)
++				pci_load_and_free_saved_state(adapter->pci_dev, &adapter->pci_saved_state);
++			pci_restore_state(adapter->pci_dev);
++			err = pci_enable_device(adapter->pci_dev);
++			if (err < 0)
++				printf("%s: PCI enable device failed", __FUNCTION__);
++			pci_set_master(adapter->pci_dev);
++		}
++#endif /* BCMPCIE */
++#endif /* BUS_POWER_RESTORE */
++		/* Lets customer power to get stable */
++		mdelay(100);
++	} else {
++#if defined(BUS_POWER_RESTORE)
++#if defined(BCMSDIO) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0))
++		if (adapter->sdio_func && adapter->sdio_func->card && adapter->sdio_func->card->host) {
++			printf("======== mmc_power_save_host! ========\n");
++			mmc_power_save_host(adapter->sdio_func->card->host);
++		}
++#elif defined(BCMPCIE)
++		if (adapter->pci_dev) {
++			printf("======== pci_set_power_state PCI_D3hot! ========\n");
++			pci_save_state(adapter->pci_dev);
++			adapter->pci_saved_state = pci_store_saved_state(adapter->pci_dev);
++			if (pci_is_enabled(adapter->pci_dev))
++				pci_disable_device(adapter->pci_dev);
++			pci_set_power_state(adapter->pci_dev, PCI_D3hot);
++		}
++#endif /* BCMPCIE */
++#endif /* BUS_POWER_RESTORE */
++		printf("======== PULL WL_REG_ON(%d) LOW! ========\n", gpio_wl_reg_on);
++		if (gpio_wl_reg_on >= 0) {
++			err = gpio_direction_output(gpio_wl_reg_on, 0);
++			if (err) {
++				printf("%s: WL_REG_ON didn't output low\n", __FUNCTION__);
++				return -EIO;
++			}
++		}
++#ifdef CUSTOMER_HW_INGENIC
++		if (poweron_num) {
++			ingenic_sdio_wlan_power_onoff(on, RESET);
++		} else {
++			poweroff_num = 1;
++			ingenic_sdio_wlan_power_onoff(on, NORMAL);
++		}
++#endif
++	}
++
++	return err;
++}
++
++static int dhd_wlan_set_reset(int onoff)
++{
++	return 0;
++}
++
++static int dhd_wlan_set_carddetect(int present)
++{
++	int err = 0;
++
++#if !defined(BUS_POWER_RESTORE)
++	if (present) {
++#if defined(BCMSDIO)
++		printf("======== Card detection to detect SDIO card! ========\n");
++#ifdef CUSTOMER_HW_PLATFORM
++		err = sdhci_force_presence_change(&sdmmc_channel, 1);
++#endif /* CUSTOMER_HW_PLATFORM */
++#elif defined(BCMPCIE)
++		printf("======== Card detection to detect PCIE card! ========\n");
++#endif
++	} else {
++#if defined(BCMSDIO)
++		printf("======== Card detection to remove SDIO card! ========\n");
++#ifdef CUSTOMER_HW_PLATFORM
++		err = sdhci_force_presence_change(&sdmmc_channel, 0);
++#endif /* CUSTOMER_HW_PLATFORM */
++#elif defined(BCMPCIE)
++		printf("======== Card detection to remove PCIE card! ========\n");
++#endif
++	}
++#endif /* BUS_POWER_RESTORE */
++
++	return err;
++}
++
++static int dhd_wlan_get_mac_addr(unsigned char *buf)
++{
++	int err = 0;
++
++	printf("======== %s ========\n", __FUNCTION__);
++#ifdef EXAMPLE_GET_MAC
++	/* EXAMPLE code */
++	{
++		struct ether_addr ea_example = {{0x00, 0x11, 0x22, 0x33, 0x44, 0xFF}};
++		bcopy((char *)&ea_example, buf, sizeof(struct ether_addr));
++	}
++#endif /* EXAMPLE_GET_MAC */
++#ifdef EXAMPLE_GET_MAC_VER2
++	/* EXAMPLE code */
++	{
++		char macpad[56]= {
++		0x00,0xaa,0x9c,0x84,0xc7,0xbc,0x9b,0xf6,
++		0x02,0x33,0xa9,0x4d,0x5c,0xb4,0x0a,0x5d,
++		0xa8,0xef,0xb0,0xcf,0x8e,0xbf,0x24,0x8a,
++		0x87,0x0f,0x6f,0x0d,0xeb,0x83,0x6a,0x70,
++		0x4a,0xeb,0xf6,0xe6,0x3c,0xe7,0x5f,0xfc,
++		0x0e,0xa7,0xb3,0x0f,0x00,0xe4,0x4a,0xaf,
++		0x87,0x08,0x16,0x6d,0x3a,0xe3,0xc7,0x80};
++		bcopy(macpad, buf+6, sizeof(macpad));
++	}
++#endif /* EXAMPLE_GET_MAC_VER2 */
++
++	return err;
++}
++
++static struct cntry_locales_custom brcm_wlan_translate_custom_table[] = {
++	/* Table should be filled out based on custom platform regulatory requirement */
++#ifdef EXAMPLE_TABLE
++	{"",   "XT", 49},  /* Universal if Country code is unknown or empty */
++	{"US", "US", 0},
++#endif /* EXMAPLE_TABLE */
++};
++
++#ifdef CUSTOM_FORCE_NODFS_FLAG
++struct cntry_locales_custom brcm_wlan_translate_nodfs_table[] = {
++#ifdef EXAMPLE_TABLE
++	{"",   "XT", 50},  /* Universal if Country code is unknown or empty */
++	{"US", "US", 0},
++#endif /* EXMAPLE_TABLE */
++};
++#endif
++
++static void *dhd_wlan_get_country_code(char *ccode
++#ifdef CUSTOM_FORCE_NODFS_FLAG
++	, u32 flags
++#endif
++)
++{
++	struct cntry_locales_custom *locales;
++	int size;
++	int i;
++
++	if (!ccode)
++		return NULL;
++
++#ifdef CUSTOM_FORCE_NODFS_FLAG
++	if (flags & WLAN_PLAT_NODFS_FLAG) {
++		locales = brcm_wlan_translate_nodfs_table;
++		size = ARRAY_SIZE(brcm_wlan_translate_nodfs_table);
++	} else {
++#endif
++		locales = brcm_wlan_translate_custom_table;
++		size = ARRAY_SIZE(brcm_wlan_translate_custom_table);
++#ifdef CUSTOM_FORCE_NODFS_FLAG
++	}
++#endif
++
++	for (i = 0; i < size; i++)
++		if (strcmp(ccode, locales[i].iso_abbrev) == 0)
++			return &locales[i];
++	return NULL;
++}
++
++struct resource dhd_wlan_resources[] = {
++	[0] = {
++		.name	= "bcmdhd_wlan_irq",
++		.start	= 0, /* Dummy */
++		.end	= 0, /* Dummy */
++		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE
++			| IORESOURCE_IRQ_HIGHLEVEL, /* Dummy */
++	},
++};
++
++struct wifi_platform_data dhd_wlan_control = {
++	.set_power	= dhd_wlan_set_power,
++	.set_reset	= dhd_wlan_set_reset,
++	.set_carddetect	= dhd_wlan_set_carddetect,
++	.get_mac_addr	= dhd_wlan_get_mac_addr,
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++	.mem_prealloc	= dhd_wlan_mem_prealloc,
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++	.get_country_code = dhd_wlan_get_country_code,
++};
++
++int dhd_wlan_init_gpio(void)
++{
++	int err = 0;
++#ifdef CUSTOMER_OOB
++	int host_oob_irq = -1;
++	uint host_oob_irq_flags = 0;
++#endif
++
++	/* Please check your schematic and fill right GPIO number which connected to
++	* WL_REG_ON and WL_HOST_WAKE.
++	*/
++	gpio_wl_reg_on = -1;
++#ifdef CUSTOMER_OOB
++	gpio_wl_host_wake = -1;
++#ifdef CUSTOMER_HW_INGENIC
++	gpio_wl_host_wake = ingenic_sdio_wlan_get_irq((unsigned long *)&host_oob_irq_flags);
++#endif
++#endif
++
++	if (gpio_wl_reg_on >= 0) {
++		err = gpio_request(gpio_wl_reg_on, "WL_REG_ON");
++		if (err < 0) {
++			printf("%s: gpio_request(%d) for WL_REG_ON failed\n",
++				__FUNCTION__, gpio_wl_reg_on);
++			gpio_wl_reg_on = -1;
++		}
++	}
++
++#ifdef CUSTOMER_OOB
++	if (gpio_wl_host_wake >= 0) {
++		err = gpio_request(gpio_wl_host_wake, "bcmdhd");
++		if (err < 0) {
++			printf("%s: gpio_request(%d) for WL_HOST_WAKE failed\n",
++				__FUNCTION__, gpio_wl_host_wake);
++			return -1;
++		}
++		err = gpio_direction_input(gpio_wl_host_wake);
++		if (err < 0) {
++			printf("%s: gpio_direction_input(%d) for WL_HOST_WAKE failed\n",
++				__FUNCTION__, gpio_wl_host_wake);
++			gpio_free(gpio_wl_host_wake);
++			return -1;
++		}
++		host_oob_irq = gpio_to_irq(gpio_wl_host_wake);
++		if (host_oob_irq < 0) {
++			printf("%s: gpio_to_irq(%d) for WL_HOST_WAKE failed\n",
++				__FUNCTION__, gpio_wl_host_wake);
++			gpio_free(gpio_wl_host_wake);
++			return -1;
++		}
++	}
++
++#ifdef HW_OOB
++	if (host_oob_irq_flags & IORESOURCE_IRQ_LOWLEVEL){
++		host_oob_irq_flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL | IORESOURCE_IRQ_SHAREABLE;
++	} else if (host_oob_irq_flags & IORESOURCE_IRQ_HIGHLEVEL){
++		host_oob_irq_flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL | IORESOURCE_IRQ_SHAREABLE;
++	} else if (host_oob_irq_flags & IORESOURCE_IRQ_HIGHEDGE){
++		host_oob_irq_flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_SHAREABLE;
++	}
++#endif
++
++	dhd_wlan_resources[0].start = dhd_wlan_resources[0].end = host_oob_irq;
++	dhd_wlan_resources[0].flags = host_oob_irq_flags;
++	printf("%s: WL_HOST_WAKE=%d, oob_irq=%d, oob_irq_flags=0x%x\n", __FUNCTION__,
++		gpio_wl_host_wake, host_oob_irq, host_oob_irq_flags);
++#endif /* CUSTOMER_OOB */
++	printf("%s: WL_REG_ON=%d\n", __FUNCTION__, gpio_wl_reg_on);
++
++	return 0;
++}
++
++static void dhd_wlan_deinit_gpio(void)
++{
++	if (gpio_wl_reg_on >= 0) {
++		printf("%s: gpio_free(WL_REG_ON %d)\n", __FUNCTION__, gpio_wl_reg_on);
++		gpio_free(gpio_wl_reg_on);
++		gpio_wl_reg_on = -1;
++	}
++#ifdef CUSTOMER_OOB
++	if (gpio_wl_host_wake >= 0) {
++		printf("%s: gpio_free(WL_HOST_WAKE %d)\n", __FUNCTION__, gpio_wl_host_wake);
++		gpio_free(gpio_wl_host_wake);
++		gpio_wl_host_wake = -1;
++	}
++#endif /* CUSTOMER_OOB */
++}
++
++int dhd_wlan_init_plat_data(void)
++{
++	int err = 0;
++
++	printf("======== %s ========\n", __FUNCTION__);
++	err = dhd_wlan_init_gpio();
++	return err;
++}
++
++void dhd_wlan_deinit_plat_data(wifi_adapter_info_t *adapter)
++{
++	printf("======== %s ========\n", __FUNCTION__);
++	dhd_wlan_deinit_gpio();
++}
++
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_ip.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_ip.c
+new file mode 100644
+index 000000000..2089c674f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_ip.c
+@@ -0,0 +1,1318 @@
++/*
++ * IP Packet Parser Module.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_ip.c 700317 2017-05-18 15:13:29Z $
++ */
++#include <typedefs.h>
++#include <osl.h>
++
++#include <ethernet.h>
++#include <vlan.h>
++#include <802.3.h>
++#include <bcmip.h>
++#include <bcmendian.h>
++
++#include <dhd_dbg.h>
++
++#include <dhd_ip.h>
++
++#ifdef DHDTCPACK_SUPPRESS
++#include <dhd_bus.h>
++#include <dhd_proto.h>
++#include <bcmtcp.h>
++#endif /* DHDTCPACK_SUPPRESS */
++
++/* special values */
++/* 802.3 llc/snap header */
++static const uint8 llc_snap_hdr[SNAP_HDR_LEN] = {0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00};
++
++pkt_frag_t pkt_frag_info(osl_t *osh, void *p)
++{
++	uint8 *frame;
++	int length;
++	uint8 *pt;			/* Pointer to type field */
++	uint16 ethertype;
++	struct ipv4_hdr *iph;		/* IP frame pointer */
++	int ipl;			/* IP frame length */
++	uint16 iph_frag;
++
++	ASSERT(osh && p);
++
++	frame = PKTDATA(osh, p);
++	length = PKTLEN(osh, p);
++
++	/* Process Ethernet II or SNAP-encapsulated 802.3 frames */
++	if (length < ETHER_HDR_LEN) {
++		DHD_INFO(("%s: short eth frame (%d)\n", __FUNCTION__, length));
++		return DHD_PKT_FRAG_NONE;
++	} else if (ntoh16(*(uint16 *)(frame + ETHER_TYPE_OFFSET)) >= ETHER_TYPE_MIN) {
++		/* Frame is Ethernet II */
++		pt = frame + ETHER_TYPE_OFFSET;
++	} else if (length >= ETHER_HDR_LEN + SNAP_HDR_LEN + ETHER_TYPE_LEN &&
++	           !bcmp(llc_snap_hdr, frame + ETHER_HDR_LEN, SNAP_HDR_LEN)) {
++		pt = frame + ETHER_HDR_LEN + SNAP_HDR_LEN;
++	} else {
++		DHD_INFO(("%s: non-SNAP 802.3 frame\n", __FUNCTION__));
++		return DHD_PKT_FRAG_NONE;
++	}
++
++	ethertype = ntoh16(*(uint16 *)pt);
++
++	/* Skip VLAN tag, if any */
++	if (ethertype == ETHER_TYPE_8021Q) {
++		pt += VLAN_TAG_LEN;
++
++		if (pt + ETHER_TYPE_LEN > frame + length) {
++			DHD_INFO(("%s: short VLAN frame (%d)\n", __FUNCTION__, length));
++			return DHD_PKT_FRAG_NONE;
++		}
++
++		ethertype = ntoh16(*(uint16 *)pt);
++	}
++
++	if (ethertype != ETHER_TYPE_IP) {
++		DHD_INFO(("%s: non-IP frame (ethertype 0x%x, length %d)\n",
++			__FUNCTION__, ethertype, length));
++		return DHD_PKT_FRAG_NONE;
++	}
++
++	iph = (struct ipv4_hdr *)(pt + ETHER_TYPE_LEN);
++	ipl = (uint)(length - (pt + ETHER_TYPE_LEN - frame));
++
++	/* We support IPv4 only */
++	if ((ipl < IPV4_OPTIONS_OFFSET) || (IP_VER(iph) != IP_VER_4)) {
++		DHD_INFO(("%s: short frame (%d) or non-IPv4\n", __FUNCTION__, ipl));
++		return DHD_PKT_FRAG_NONE;
++	}
++
++	iph_frag = ntoh16(iph->frag);
++
++	if (iph_frag & IPV4_FRAG_DONT) {
++		return DHD_PKT_FRAG_NONE;
++	} else if ((iph_frag & IPV4_FRAG_MORE) == 0) {
++		return DHD_PKT_FRAG_LAST;
++	} else {
++		return (iph_frag & IPV4_FRAG_OFFSET_MASK)? DHD_PKT_FRAG_CONT : DHD_PKT_FRAG_FIRST;
++	}
++}
++
++#ifdef DHDTCPACK_SUPPRESS
++
++typedef struct {
++	void *pkt_in_q;		/* TCP ACK packet that is already in txq or DelayQ */
++	void *pkt_ether_hdr;	/* Ethernet header pointer of pkt_in_q */
++	int ifidx;
++	uint8 supp_cnt;
++	dhd_pub_t *dhdp;
++	timer_list_compat_t timer;
++} tcpack_info_t;
++
++typedef struct _tdata_psh_info_t {
++	uint32 end_seq;			/* end seq# of a received TCP PSH DATA pkt */
++	struct _tdata_psh_info_t *next;	/* next pointer of the link chain */
++} tdata_psh_info_t;
++
++typedef struct {
++	struct {
++		uint8 src[IPV4_ADDR_LEN];	/* SRC ip addrs of this TCP stream */
++		uint8 dst[IPV4_ADDR_LEN];	/* DST ip addrs of this TCP stream */
++	} ip_addr;
++	struct {
++		uint8 src[TCP_PORT_LEN];	/* SRC tcp ports of this TCP stream */
++		uint8 dst[TCP_PORT_LEN];	/* DST tcp ports of this TCP stream */
++	} tcp_port;
++	tdata_psh_info_t *tdata_psh_info_head;	/* Head of received TCP PSH DATA chain */
++	tdata_psh_info_t *tdata_psh_info_tail;	/* Tail of received TCP PSH DATA chain */
++	uint32 last_used_time;	/* The last time this tcpdata_info was used(in ms) */
++} tcpdata_info_t;
++
++/* TCPACK SUPPRESS module */
++typedef struct {
++	int tcpack_info_cnt;
++	tcpack_info_t tcpack_info_tbl[TCPACK_INFO_MAXNUM];	/* Info of TCP ACK to send */
++	int tcpdata_info_cnt;
++	tcpdata_info_t tcpdata_info_tbl[TCPDATA_INFO_MAXNUM];	/* Info of received TCP DATA */
++	tdata_psh_info_t *tdata_psh_info_pool;	/* Pointer to tdata_psh_info elements pool */
++	tdata_psh_info_t *tdata_psh_info_free;	/* free tdata_psh_info elements chain in pool */
++#ifdef DHDTCPACK_SUP_DBG
++	int psh_info_enq_num;	/* Number of free TCP PSH DATA info elements in pool */
++#endif /* DHDTCPACK_SUP_DBG */
++} tcpack_sup_module_t;
++
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++counter_tbl_t tack_tbl = {"tcpACK", 0, 1000, 10, {0, }, 1};
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++
++static void
++_tdata_psh_info_pool_enq(tcpack_sup_module_t *tcpack_sup_mod,
++	tdata_psh_info_t *tdata_psh_info)
++{
++	if ((tcpack_sup_mod == NULL) || (tdata_psh_info == NULL)) {
++		DHD_ERROR(("%s %d: ERROR %p %p\n", __FUNCTION__, __LINE__,
++			tcpack_sup_mod, tdata_psh_info));
++		return;
++	}
++
++	ASSERT(tdata_psh_info->next == NULL);
++	tdata_psh_info->next = tcpack_sup_mod->tdata_psh_info_free;
++	tcpack_sup_mod->tdata_psh_info_free = tdata_psh_info;
++#ifdef DHDTCPACK_SUP_DBG
++	tcpack_sup_mod->psh_info_enq_num++;
++#endif
++}
++
++static tdata_psh_info_t*
++_tdata_psh_info_pool_deq(tcpack_sup_module_t *tcpack_sup_mod)
++{
++	tdata_psh_info_t *tdata_psh_info = NULL;
++
++	if (tcpack_sup_mod == NULL) {
++		DHD_ERROR(("%s %d: ERROR %p\n", __FUNCTION__, __LINE__,
++			tcpack_sup_mod));
++		return NULL;
++	}
++
++	tdata_psh_info = tcpack_sup_mod->tdata_psh_info_free;
++	if (tdata_psh_info == NULL)
++		DHD_ERROR(("%s %d: Out of tdata_disc_grp\n", __FUNCTION__, __LINE__));
++	else {
++		tcpack_sup_mod->tdata_psh_info_free = tdata_psh_info->next;
++		tdata_psh_info->next = NULL;
++#ifdef DHDTCPACK_SUP_DBG
++		tcpack_sup_mod->psh_info_enq_num--;
++#endif /* DHDTCPACK_SUP_DBG */
++	}
++
++	return tdata_psh_info;
++}
++
++static int _tdata_psh_info_pool_init(dhd_pub_t *dhdp,
++	tcpack_sup_module_t *tcpack_sup_mod)
++{
++	tdata_psh_info_t *tdata_psh_info_pool = NULL;
++	uint i;
++
++	DHD_TRACE(("%s %d: Enter\n", __FUNCTION__, __LINE__));
++
++	if (tcpack_sup_mod == NULL)
++		return BCME_ERROR;
++
++	ASSERT(tcpack_sup_mod->tdata_psh_info_pool == NULL);
++	ASSERT(tcpack_sup_mod->tdata_psh_info_free == NULL);
++
++	tdata_psh_info_pool =
++		MALLOC(dhdp->osh, sizeof(tdata_psh_info_t) * TCPDATA_PSH_INFO_MAXNUM);
++
++	if (tdata_psh_info_pool == NULL)
++		return BCME_NOMEM;
++	bzero(tdata_psh_info_pool, sizeof(tdata_psh_info_t) * TCPDATA_PSH_INFO_MAXNUM);
++#ifdef DHDTCPACK_SUP_DBG
++	tcpack_sup_mod->psh_info_enq_num = 0;
++#endif /* DHDTCPACK_SUP_DBG */
++
++	/* Enqueue newly allocated tcpdata psh info elements to the pool */
++	for (i = 0; i < TCPDATA_PSH_INFO_MAXNUM; i++)
++		_tdata_psh_info_pool_enq(tcpack_sup_mod, &tdata_psh_info_pool[i]);
++
++	ASSERT(tcpack_sup_mod->tdata_psh_info_free != NULL);
++	tcpack_sup_mod->tdata_psh_info_pool = tdata_psh_info_pool;
++
++	return BCME_OK;
++}
++
++static void _tdata_psh_info_pool_deinit(dhd_pub_t *dhdp,
++	tcpack_sup_module_t *tcpack_sup_mod)
++{
++	uint i;
++	tdata_psh_info_t *tdata_psh_info;
++
++	DHD_TRACE(("%s %d: Enter\n", __FUNCTION__, __LINE__));
++
++	if (tcpack_sup_mod == NULL) {
++		DHD_ERROR(("%s %d: ERROR tcpack_sup_mod NULL!\n",
++			__FUNCTION__, __LINE__));
++		return;
++	}
++
++	for (i = 0; i < tcpack_sup_mod->tcpdata_info_cnt; i++) {
++		tcpdata_info_t *tcpdata_info = &tcpack_sup_mod->tcpdata_info_tbl[i];
++		/* Return tdata_psh_info elements allocated to each tcpdata_info to the pool */
++		while ((tdata_psh_info = tcpdata_info->tdata_psh_info_head)) {
++			tcpdata_info->tdata_psh_info_head = tdata_psh_info->next;
++			tdata_psh_info->next = NULL;
++			_tdata_psh_info_pool_enq(tcpack_sup_mod, tdata_psh_info);
++		}
++		tcpdata_info->tdata_psh_info_tail = NULL;
++	}
++#ifdef DHDTCPACK_SUP_DBG
++	DHD_ERROR(("%s %d: PSH INFO ENQ %d\n",
++		__FUNCTION__, __LINE__, tcpack_sup_mod->psh_info_enq_num));
++#endif /* DHDTCPACK_SUP_DBG */
++
++	i = 0;
++	/* Be sure we recollected all tdata_psh_info elements */
++	while ((tdata_psh_info = tcpack_sup_mod->tdata_psh_info_free)) {
++		tcpack_sup_mod->tdata_psh_info_free = tdata_psh_info->next;
++		tdata_psh_info->next = NULL;
++		i++;
++	}
++	ASSERT(i == TCPDATA_PSH_INFO_MAXNUM);
++	MFREE(dhdp->osh, tcpack_sup_mod->tdata_psh_info_pool,
++		sizeof(tdata_psh_info_t) * TCPDATA_PSH_INFO_MAXNUM);
++	tcpack_sup_mod->tdata_psh_info_pool = NULL;
++
++	return;
++}
++
++static void dhd_tcpack_send(ulong data)
++{
++	tcpack_sup_module_t *tcpack_sup_mod;
++	tcpack_info_t *cur_tbl = (tcpack_info_t *)data;
++	dhd_pub_t *dhdp;
++	int ifidx;
++	void* pkt;
++	unsigned long flags;
++
++	if (!cur_tbl) {
++		return;
++	}
++
++	dhdp = cur_tbl->dhdp;
++	if (!dhdp) {
++		return;
++	}
++
++	flags = dhd_os_tcpacklock(dhdp);
++
++	tcpack_sup_mod = dhdp->tcpack_sup_module;
++	if (!tcpack_sup_mod) {
++		DHD_ERROR(("%s %d: tcpack suppress module NULL!!\n",
++			__FUNCTION__, __LINE__));
++		dhd_os_tcpackunlock(dhdp, flags);
++		return;
++	}
++	pkt = cur_tbl->pkt_in_q;
++	ifidx = cur_tbl->ifidx;
++	if (!pkt) {
++		dhd_os_tcpackunlock(dhdp, flags);
++		return;
++	}
++	cur_tbl->pkt_in_q = NULL;
++	cur_tbl->pkt_ether_hdr = NULL;
++	cur_tbl->ifidx = 0;
++	cur_tbl->supp_cnt = 0;
++	if (--tcpack_sup_mod->tcpack_info_cnt < 0) {
++		DHD_ERROR(("%s %d: ERROR!!! tcp_ack_info_cnt %d\n",
++			__FUNCTION__, __LINE__, tcpack_sup_mod->tcpack_info_cnt));
++	}
++
++	dhd_os_tcpackunlock(dhdp, flags);
++
++	dhd_sendpkt(dhdp, ifidx, pkt);
++}
++
++int dhd_tcpack_suppress_set(dhd_pub_t *dhdp, uint8 mode)
++{
++	int ret = BCME_OK;
++	unsigned long flags;
++	tcpack_sup_module_t *tcpack_sup_module;
++	uint8 invalid_mode = FALSE;
++	int prev_mode;
++	int i = 0;
++
++	flags = dhd_os_tcpacklock(dhdp);
++	tcpack_sup_module = dhdp->tcpack_sup_module;
++	prev_mode = dhdp->tcpack_sup_mode;
++
++	/* Check a new mode */
++	if (prev_mode == mode) {
++		DHD_ERROR(("%s %d: already set to %d\n", __FUNCTION__, __LINE__, mode));
++		goto exit;
++	}
++
++	invalid_mode |= (mode >= TCPACK_SUP_LAST_MODE);
++#ifdef BCMSDIO
++	invalid_mode |= (mode == TCPACK_SUP_HOLD);
++#endif /* BCMSDIO */
++#ifdef BCMPCIE
++	invalid_mode |= ((mode == TCPACK_SUP_REPLACE) || (mode == TCPACK_SUP_DELAYTX));
++#endif /* BCMPCIE */
++
++	if (invalid_mode) {
++		DHD_ERROR(("%s %d: Invalid TCP ACK Suppress mode %d\n",
++			__FUNCTION__, __LINE__, mode));
++		ret = BCME_BADARG;
++		goto exit;
++	}
++
++	printf("%s: TCP ACK Suppress mode %d -> mode %d\n",
++		__FUNCTION__, dhdp->tcpack_sup_mode, mode);
++
++	/* Pre-process routines to change a new mode as per previous mode */
++	switch (prev_mode) {
++		case TCPACK_SUP_OFF:
++			if (tcpack_sup_module == NULL) {
++				tcpack_sup_module = MALLOC(dhdp->osh, sizeof(tcpack_sup_module_t));
++				if (tcpack_sup_module == NULL) {
++					DHD_ERROR(("%s[%d]: Failed to allocate the new memory for "
++						"tcpack_sup_module\n", __FUNCTION__, __LINE__));
++					dhdp->tcpack_sup_mode = TCPACK_SUP_OFF;
++					ret = BCME_NOMEM;
++					goto exit;
++				}
++				dhdp->tcpack_sup_module = tcpack_sup_module;
++			}
++			bzero(tcpack_sup_module, sizeof(tcpack_sup_module_t));
++			break;
++		case TCPACK_SUP_DELAYTX:
++			if (tcpack_sup_module) {
++				/* We won't need tdata_psh_info pool and
++				 * tcpddata_info_tbl anymore
++				 */
++				_tdata_psh_info_pool_deinit(dhdp, tcpack_sup_module);
++				tcpack_sup_module->tcpdata_info_cnt = 0;
++				bzero(tcpack_sup_module->tcpdata_info_tbl,
++					sizeof(tcpdata_info_t) * TCPDATA_INFO_MAXNUM);
++			}
++
++			/* For half duplex bus interface, tx precedes rx by default */
++			if (dhdp->bus) {
++				dhd_bus_set_dotxinrx(dhdp->bus, TRUE);
++			}
++
++			if (tcpack_sup_module == NULL) {
++				DHD_ERROR(("%s[%d]: tcpack_sup_module should not be NULL\n",
++					__FUNCTION__, __LINE__));
++				dhdp->tcpack_sup_mode = TCPACK_SUP_OFF;
++				goto exit;
++			}
++			break;
++	}
++
++	/* Update a new mode */
++	dhdp->tcpack_sup_mode = mode;
++
++	/* Process for a new mode */
++	switch (mode) {
++		case TCPACK_SUP_OFF:
++			ASSERT(tcpack_sup_module != NULL);
++			/* Clean up timer/data structure for
++			 * any remaining/pending packet or timer.
++			 */
++			if (tcpack_sup_module) {
++				/* Check if previous mode is TCAPACK_SUP_HOLD */
++				if (prev_mode == TCPACK_SUP_HOLD) {
++					for (i = 0; i < TCPACK_INFO_MAXNUM; i++) {
++						tcpack_info_t *tcpack_info_tbl =
++							&tcpack_sup_module->tcpack_info_tbl[i];
++						_del_timer(&tcpack_info_tbl->timer);
++						if (tcpack_info_tbl->pkt_in_q) {
++							PKTFREE(dhdp->osh,
++								tcpack_info_tbl->pkt_in_q, TRUE);
++							tcpack_info_tbl->pkt_in_q = NULL;
++						}
++					}
++				}
++				MFREE(dhdp->osh, tcpack_sup_module, sizeof(tcpack_sup_module_t));
++				dhdp->tcpack_sup_module = NULL;
++			} else {
++				DHD_ERROR(("%s[%d]: tcpack_sup_module should not be NULL\n",
++					__FUNCTION__, __LINE__));
++			}
++			break;
++		case TCPACK_SUP_REPLACE:
++			/* There is nothing to configure for this mode */
++			break;
++		case TCPACK_SUP_DELAYTX:
++			ret = _tdata_psh_info_pool_init(dhdp, tcpack_sup_module);
++			if (ret != BCME_OK) {
++				DHD_ERROR(("%s %d: pool init fail with %d\n",
++					__FUNCTION__, __LINE__, ret));
++				break;
++			}
++			if (dhdp->bus) {
++				dhd_bus_set_dotxinrx(dhdp->bus, FALSE);
++			}
++			break;
++		case TCPACK_SUP_HOLD:
++			dhdp->tcpack_sup_ratio = CUSTOM_TCPACK_SUPP_RATIO;
++			dhdp->tcpack_sup_delay = CUSTOM_TCPACK_DELAY_TIME;
++			for (i = 0; i < TCPACK_INFO_MAXNUM; i++) {
++				tcpack_info_t *tcpack_info_tbl =
++					&tcpack_sup_module->tcpack_info_tbl[i];
++				tcpack_info_tbl->dhdp = dhdp;
++				init_timer_compat(&tcpack_info_tbl->timer, dhd_tcpack_send, tcpack_info_tbl);
++			}
++			break;
++	}
++
++exit:
++	dhd_os_tcpackunlock(dhdp, flags);
++	return ret;
++}
++
++void
++dhd_tcpack_info_tbl_clean(dhd_pub_t *dhdp)
++{
++	tcpack_sup_module_t *tcpack_sup_mod = dhdp->tcpack_sup_module;
++	int i;
++	unsigned long flags;
++
++	if (dhdp->tcpack_sup_mode == TCPACK_SUP_OFF)
++		goto exit;
++
++	flags = dhd_os_tcpacklock(dhdp);
++
++	if (!tcpack_sup_mod) {
++		DHD_ERROR(("%s %d: tcpack suppress module NULL!!\n",
++			__FUNCTION__, __LINE__));
++		dhd_os_tcpackunlock(dhdp, flags);
++		goto exit;
++	}
++
++	if (dhdp->tcpack_sup_mode == TCPACK_SUP_HOLD) {
++		for (i = 0; i < TCPACK_INFO_MAXNUM; i++) {
++			if (tcpack_sup_mod->tcpack_info_tbl[i].pkt_in_q) {
++				PKTFREE(dhdp->osh, tcpack_sup_mod->tcpack_info_tbl[i].pkt_in_q,
++					TRUE);
++				tcpack_sup_mod->tcpack_info_tbl[i].pkt_in_q = NULL;
++				tcpack_sup_mod->tcpack_info_tbl[i].pkt_ether_hdr = NULL;
++				tcpack_sup_mod->tcpack_info_tbl[i].ifidx = 0;
++				tcpack_sup_mod->tcpack_info_tbl[i].supp_cnt = 0;
++			}
++		}
++	} else {
++		tcpack_sup_mod->tcpack_info_cnt = 0;
++		bzero(tcpack_sup_mod->tcpack_info_tbl, sizeof(tcpack_info_t) * TCPACK_INFO_MAXNUM);
++	}
++
++	dhd_os_tcpackunlock(dhdp, flags);
++
++	if (dhdp->tcpack_sup_mode == TCPACK_SUP_HOLD) {
++		for (i = 0; i < TCPACK_INFO_MAXNUM; i++) {
++			_del_timer_sync(&tcpack_sup_mod->tcpack_info_tbl[i].timer);
++		}
++	}
++
++exit:
++	return;
++}
++
++inline int dhd_tcpack_check_xmit(dhd_pub_t *dhdp, void *pkt)
++{
++	uint8 i;
++	tcpack_sup_module_t *tcpack_sup_mod;
++	tcpack_info_t *tcpack_info_tbl;
++	int tbl_cnt;
++	int ret = BCME_OK;
++	void *pdata;
++	uint32 pktlen;
++	unsigned long flags;
++
++	if (dhdp->tcpack_sup_mode == TCPACK_SUP_OFF)
++		goto exit;
++
++	pdata = PKTDATA(dhdp->osh, pkt);
++	pktlen = PKTLEN(dhdp->osh, pkt) - dhd_prot_hdrlen(dhdp, pdata);
++
++	if (pktlen < TCPACKSZMIN || pktlen > TCPACKSZMAX) {
++		DHD_TRACE(("%s %d: Too short or long length %d to be TCP ACK\n",
++			__FUNCTION__, __LINE__, pktlen));
++		goto exit;
++	}
++
++	flags = dhd_os_tcpacklock(dhdp);
++	tcpack_sup_mod = dhdp->tcpack_sup_module;
++
++	if (!tcpack_sup_mod) {
++		DHD_ERROR(("%s %d: tcpack suppress module NULL!!\n", __FUNCTION__, __LINE__));
++		ret = BCME_ERROR;
++		dhd_os_tcpackunlock(dhdp, flags);
++		goto exit;
++	}
++	tbl_cnt = tcpack_sup_mod->tcpack_info_cnt;
++	tcpack_info_tbl = tcpack_sup_mod->tcpack_info_tbl;
++
++	ASSERT(tbl_cnt <= TCPACK_INFO_MAXNUM);
++
++	for (i = 0; i < tbl_cnt; i++) {
++		if (tcpack_info_tbl[i].pkt_in_q == pkt) {
++			DHD_TRACE(("%s %d: pkt %p sent out. idx %d, tbl_cnt %d\n",
++				__FUNCTION__, __LINE__, pkt, i, tbl_cnt));
++			/* This pkt is being transmitted so remove the tcp_ack_info of it. */
++			if (i < tbl_cnt - 1) {
++				bcopy(&tcpack_info_tbl[tbl_cnt - 1],
++					&tcpack_info_tbl[i], sizeof(tcpack_info_t));
++			}
++			bzero(&tcpack_info_tbl[tbl_cnt - 1], sizeof(tcpack_info_t));
++			if (--tcpack_sup_mod->tcpack_info_cnt < 0) {
++				DHD_ERROR(("%s %d: ERROR!!! tcp_ack_info_cnt %d\n",
++					__FUNCTION__, __LINE__, tcpack_sup_mod->tcpack_info_cnt));
++				ret = BCME_ERROR;
++			}
++			break;
++		}
++	}
++	dhd_os_tcpackunlock(dhdp, flags);
++
++exit:
++	return ret;
++}
++
++static INLINE bool dhd_tcpdata_psh_acked(dhd_pub_t *dhdp, uint8 *ip_hdr,
++	uint8 *tcp_hdr, uint32 tcp_ack_num)
++{
++	tcpack_sup_module_t *tcpack_sup_mod;
++	int i;
++	tcpdata_info_t *tcpdata_info = NULL;
++	tdata_psh_info_t *tdata_psh_info = NULL;
++	bool ret = FALSE;
++
++	if (dhdp->tcpack_sup_mode != TCPACK_SUP_DELAYTX)
++		goto exit;
++
++	tcpack_sup_mod = dhdp->tcpack_sup_module;
++
++	if (!tcpack_sup_mod) {
++		DHD_ERROR(("%s %d: tcpack suppress module NULL!!\n", __FUNCTION__, __LINE__));
++		goto exit;
++	}
++
++	DHD_TRACE(("%s %d: IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR
++		" TCP port %d %d, ack %u\n", __FUNCTION__, __LINE__,
++		IPV4_ADDR_TO_STR(ntoh32_ua(&ip_hdr[IPV4_SRC_IP_OFFSET])),
++		IPV4_ADDR_TO_STR(ntoh32_ua(&ip_hdr[IPV4_DEST_IP_OFFSET])),
++		ntoh16_ua(&tcp_hdr[TCP_SRC_PORT_OFFSET]),
++		ntoh16_ua(&tcp_hdr[TCP_DEST_PORT_OFFSET]),
++		tcp_ack_num));
++
++	for (i = 0; i < tcpack_sup_mod->tcpdata_info_cnt; i++) {
++		tcpdata_info_t *tcpdata_info_tmp = &tcpack_sup_mod->tcpdata_info_tbl[i];
++		DHD_TRACE(("%s %d: data info[%d], IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR
++			" TCP port %d %d\n", __FUNCTION__, __LINE__, i,
++			IPV4_ADDR_TO_STR(ntoh32_ua(tcpdata_info_tmp->ip_addr.src)),
++			IPV4_ADDR_TO_STR(ntoh32_ua(tcpdata_info_tmp->ip_addr.dst)),
++			ntoh16_ua(tcpdata_info_tmp->tcp_port.src),
++			ntoh16_ua(tcpdata_info_tmp->tcp_port.dst)));
++
++		/* If either IP address or TCP port number does not match, skip. */
++		if (memcmp(&ip_hdr[IPV4_SRC_IP_OFFSET],
++			tcpdata_info_tmp->ip_addr.dst, IPV4_ADDR_LEN) == 0 &&
++			memcmp(&ip_hdr[IPV4_DEST_IP_OFFSET],
++			tcpdata_info_tmp->ip_addr.src, IPV4_ADDR_LEN) == 0 &&
++			memcmp(&tcp_hdr[TCP_SRC_PORT_OFFSET],
++			tcpdata_info_tmp->tcp_port.dst, TCP_PORT_LEN) == 0 &&
++			memcmp(&tcp_hdr[TCP_DEST_PORT_OFFSET],
++			tcpdata_info_tmp->tcp_port.src, TCP_PORT_LEN) == 0) {
++			tcpdata_info = tcpdata_info_tmp;
++			break;
++		}
++	}
++
++	if (tcpdata_info == NULL) {
++		DHD_TRACE(("%s %d: no tcpdata_info!\n", __FUNCTION__, __LINE__));
++		goto exit;
++	}
++
++	if (tcpdata_info->tdata_psh_info_head == NULL) {
++		DHD_TRACE(("%s %d: No PSH DATA to be acked!\n", __FUNCTION__, __LINE__));
++	}
++
++	while ((tdata_psh_info = tcpdata_info->tdata_psh_info_head)) {
++		if (IS_TCPSEQ_GE(tcp_ack_num, tdata_psh_info->end_seq)) {
++			DHD_TRACE(("%s %d: PSH ACKED! %u >= %u\n",
++				__FUNCTION__, __LINE__, tcp_ack_num, tdata_psh_info->end_seq));
++			tcpdata_info->tdata_psh_info_head = tdata_psh_info->next;
++			tdata_psh_info->next = NULL;
++			_tdata_psh_info_pool_enq(tcpack_sup_mod, tdata_psh_info);
++			ret = TRUE;
++		} else
++			break;
++	}
++	if (tdata_psh_info == NULL)
++		tcpdata_info->tdata_psh_info_tail = NULL;
++
++#ifdef DHDTCPACK_SUP_DBG
++	DHD_TRACE(("%s %d: PSH INFO ENQ %d\n",
++		__FUNCTION__, __LINE__, tcpack_sup_mod->psh_info_enq_num));
++#endif /* DHDTCPACK_SUP_DBG */
++
++exit:
++	return ret;
++}
++
++bool
++dhd_tcpack_suppress(dhd_pub_t *dhdp, void *pkt)
++{
++	uint8 *new_ether_hdr;	/* Ethernet header of the new packet */
++	uint16 new_ether_type;	/* Ethernet type of the new packet */
++	uint8 *new_ip_hdr;		/* IP header of the new packet */
++	uint8 *new_tcp_hdr;		/* TCP header of the new packet */
++	uint32 new_ip_hdr_len;	/* IP header length of the new packet */
++	uint32 cur_framelen;
++	uint32 new_tcp_ack_num;		/* TCP acknowledge number of the new packet */
++	uint16 new_ip_total_len;	/* Total length of IP packet for the new packet */
++	uint32 new_tcp_hdr_len;		/* TCP header length of the new packet */
++	tcpack_sup_module_t *tcpack_sup_mod;
++	tcpack_info_t *tcpack_info_tbl;
++	int i;
++	bool ret = FALSE;
++	bool set_dotxinrx = TRUE;
++	unsigned long flags;
++
++
++	if (dhdp->tcpack_sup_mode == TCPACK_SUP_OFF)
++		goto exit;
++
++	new_ether_hdr = PKTDATA(dhdp->osh, pkt);
++	cur_framelen = PKTLEN(dhdp->osh, pkt);
++
++	if (cur_framelen < TCPACKSZMIN || cur_framelen > TCPACKSZMAX) {
++		DHD_TRACE(("%s %d: Too short or long length %d to be TCP ACK\n",
++			__FUNCTION__, __LINE__, cur_framelen));
++		goto exit;
++	}
++
++	new_ether_type = new_ether_hdr[12] << 8 | new_ether_hdr[13];
++
++	if (new_ether_type != ETHER_TYPE_IP) {
++		DHD_TRACE(("%s %d: Not a IP packet 0x%x\n",
++			__FUNCTION__, __LINE__, new_ether_type));
++		goto exit;
++	}
++
++	DHD_TRACE(("%s %d: IP pkt! 0x%x\n", __FUNCTION__, __LINE__, new_ether_type));
++
++	new_ip_hdr = new_ether_hdr + ETHER_HDR_LEN;
++	cur_framelen -= ETHER_HDR_LEN;
++
++	ASSERT(cur_framelen >= IPV4_MIN_HEADER_LEN);
++
++	new_ip_hdr_len = IPV4_HLEN(new_ip_hdr);
++	if (IP_VER(new_ip_hdr) != IP_VER_4 || IPV4_PROT(new_ip_hdr) != IP_PROT_TCP) {
++		DHD_TRACE(("%s %d: Not IPv4 nor TCP! ip ver %d, prot %d\n",
++			__FUNCTION__, __LINE__, IP_VER(new_ip_hdr), IPV4_PROT(new_ip_hdr)));
++		goto exit;
++	}
++
++	new_tcp_hdr = new_ip_hdr + new_ip_hdr_len;
++	cur_framelen -= new_ip_hdr_len;
++
++	ASSERT(cur_framelen >= TCP_MIN_HEADER_LEN);
++
++	DHD_TRACE(("%s %d: TCP pkt!\n", __FUNCTION__, __LINE__));
++
++	/* is it an ack ? Allow only ACK flag, not to suppress others. */
++	if (new_tcp_hdr[TCP_FLAGS_OFFSET] != TCP_FLAG_ACK) {
++		DHD_TRACE(("%s %d: Do not touch TCP flag 0x%x\n",
++			__FUNCTION__, __LINE__, new_tcp_hdr[TCP_FLAGS_OFFSET]));
++		goto exit;
++	}
++
++	new_ip_total_len = ntoh16_ua(&new_ip_hdr[IPV4_PKTLEN_OFFSET]);
++	new_tcp_hdr_len = 4 * TCP_HDRLEN(new_tcp_hdr[TCP_HLEN_OFFSET]);
++
++	/* This packet has TCP data, so just send */
++	if (new_ip_total_len > new_ip_hdr_len + new_tcp_hdr_len) {
++		DHD_TRACE(("%s %d: Do nothing for TCP DATA\n", __FUNCTION__, __LINE__));
++		goto exit;
++	}
++
++	ASSERT(new_ip_total_len == new_ip_hdr_len + new_tcp_hdr_len);
++
++	new_tcp_ack_num = ntoh32_ua(&new_tcp_hdr[TCP_ACK_NUM_OFFSET]);
++
++	DHD_TRACE(("%s %d: TCP ACK with zero DATA length"
++		" IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR" TCP port %d %d\n",
++		__FUNCTION__, __LINE__,
++		IPV4_ADDR_TO_STR(ntoh32_ua(&new_ip_hdr[IPV4_SRC_IP_OFFSET])),
++		IPV4_ADDR_TO_STR(ntoh32_ua(&new_ip_hdr[IPV4_DEST_IP_OFFSET])),
++		ntoh16_ua(&new_tcp_hdr[TCP_SRC_PORT_OFFSET]),
++		ntoh16_ua(&new_tcp_hdr[TCP_DEST_PORT_OFFSET])));
++
++	/* Look for tcp_ack_info that has the same ip src/dst addrs and tcp src/dst ports */
++	flags = dhd_os_tcpacklock(dhdp);
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++	counter_printlog(&tack_tbl);
++	tack_tbl.cnt[0]++;
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++
++	tcpack_sup_mod = dhdp->tcpack_sup_module;
++	tcpack_info_tbl = tcpack_sup_mod->tcpack_info_tbl;
++
++	if (!tcpack_sup_mod) {
++		DHD_ERROR(("%s %d: tcpack suppress module NULL!!\n", __FUNCTION__, __LINE__));
++		ret = BCME_ERROR;
++		dhd_os_tcpackunlock(dhdp, flags);
++		goto exit;
++	}
++
++	if (dhd_tcpdata_psh_acked(dhdp, new_ip_hdr, new_tcp_hdr, new_tcp_ack_num)) {
++		/* This TCPACK is ACK to TCPDATA PSH pkt, so keep set_dotxinrx TRUE */
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++		tack_tbl.cnt[5]++;
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++	} else
++		set_dotxinrx = FALSE;
++
++	for (i = 0; i < tcpack_sup_mod->tcpack_info_cnt; i++) {
++		void *oldpkt;	/* TCPACK packet that is already in txq or DelayQ */
++		uint8 *old_ether_hdr, *old_ip_hdr, *old_tcp_hdr;
++		uint32 old_ip_hdr_len, old_tcp_hdr_len;
++		uint32 old_tcpack_num;	/* TCP ACK number of old TCPACK packet in Q */
++
++		if ((oldpkt = tcpack_info_tbl[i].pkt_in_q) == NULL) {
++			DHD_ERROR(("%s %d: Unexpected error!! cur idx %d, ttl cnt %d\n",
++				__FUNCTION__, __LINE__, i, tcpack_sup_mod->tcpack_info_cnt));
++			break;
++		}
++
++		if (PKTDATA(dhdp->osh, oldpkt) == NULL) {
++			DHD_ERROR(("%s %d: oldpkt data NULL!! cur idx %d, ttl cnt %d\n",
++				__FUNCTION__, __LINE__, i, tcpack_sup_mod->tcpack_info_cnt));
++			break;
++		}
++
++		old_ether_hdr = tcpack_info_tbl[i].pkt_ether_hdr;
++		old_ip_hdr = old_ether_hdr + ETHER_HDR_LEN;
++		old_ip_hdr_len = IPV4_HLEN(old_ip_hdr);
++		old_tcp_hdr = old_ip_hdr + old_ip_hdr_len;
++		old_tcp_hdr_len = 4 * TCP_HDRLEN(old_tcp_hdr[TCP_HLEN_OFFSET]);
++
++		DHD_TRACE(("%s %d: oldpkt %p[%d], IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR
++			" TCP port %d %d\n", __FUNCTION__, __LINE__, oldpkt, i,
++			IPV4_ADDR_TO_STR(ntoh32_ua(&old_ip_hdr[IPV4_SRC_IP_OFFSET])),
++			IPV4_ADDR_TO_STR(ntoh32_ua(&old_ip_hdr[IPV4_DEST_IP_OFFSET])),
++			ntoh16_ua(&old_tcp_hdr[TCP_SRC_PORT_OFFSET]),
++			ntoh16_ua(&old_tcp_hdr[TCP_DEST_PORT_OFFSET])));
++
++		/* If either of IP address or TCP port number does not match, skip.
++		 * Note that src/dst addr fields in ip header are contiguous being 8 bytes in total.
++		 * Also, src/dst port fields in TCP header are contiguous being 4 bytes in total.
++		 */
++		if (memcmp(&new_ip_hdr[IPV4_SRC_IP_OFFSET],
++			&old_ip_hdr[IPV4_SRC_IP_OFFSET], IPV4_ADDR_LEN * 2) ||
++			memcmp(&new_tcp_hdr[TCP_SRC_PORT_OFFSET],
++			&old_tcp_hdr[TCP_SRC_PORT_OFFSET], TCP_PORT_LEN * 2))
++			continue;
++
++		old_tcpack_num = ntoh32_ua(&old_tcp_hdr[TCP_ACK_NUM_OFFSET]);
++
++		if (IS_TCPSEQ_GT(new_tcp_ack_num, old_tcpack_num)) {
++			/* New packet has higher TCP ACK number, so it replaces the old packet */
++			if (new_ip_hdr_len == old_ip_hdr_len &&
++				new_tcp_hdr_len == old_tcp_hdr_len) {
++				ASSERT(memcmp(new_ether_hdr, old_ether_hdr, ETHER_HDR_LEN) == 0);
++				bcopy(new_ip_hdr, old_ip_hdr, new_ip_total_len);
++				PKTFREE(dhdp->osh, pkt, FALSE);
++				DHD_TRACE(("%s %d: TCP ACK replace %u -> %u\n",
++					__FUNCTION__, __LINE__, old_tcpack_num, new_tcp_ack_num));
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++				tack_tbl.cnt[2]++;
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++				ret = TRUE;
++			} else {
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++				tack_tbl.cnt[6]++;
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++				DHD_TRACE(("%s %d: lenth mismatch %d != %d || %d != %d"
++					" ACK %u -> %u\n", __FUNCTION__, __LINE__,
++					new_ip_hdr_len, old_ip_hdr_len,
++					new_tcp_hdr_len, old_tcp_hdr_len,
++					old_tcpack_num, new_tcp_ack_num));
++			}
++		} else if (new_tcp_ack_num == old_tcpack_num) {
++			set_dotxinrx = TRUE;
++			/* TCPACK retransmission */
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++			tack_tbl.cnt[3]++;
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++		} else {
++			DHD_TRACE(("%s %d: ACK number reverse old %u(0x%p) new %u(0x%p)\n",
++				__FUNCTION__, __LINE__, old_tcpack_num, oldpkt,
++				new_tcp_ack_num, pkt));
++		}
++		dhd_os_tcpackunlock(dhdp, flags);
++		goto exit;
++	}
++
++	if (i == tcpack_sup_mod->tcpack_info_cnt && i < TCPACK_INFO_MAXNUM) {
++		/* No TCPACK packet with the same IP addr and TCP port is found
++		 * in tcp_ack_info_tbl. So add this packet to the table.
++		 */
++		DHD_TRACE(("%s %d: Add pkt 0x%p(ether_hdr 0x%p) to tbl[%d]\n",
++			__FUNCTION__, __LINE__, pkt, new_ether_hdr,
++			tcpack_sup_mod->tcpack_info_cnt));
++
++		tcpack_info_tbl[tcpack_sup_mod->tcpack_info_cnt].pkt_in_q = pkt;
++		tcpack_info_tbl[tcpack_sup_mod->tcpack_info_cnt].pkt_ether_hdr = new_ether_hdr;
++		tcpack_sup_mod->tcpack_info_cnt++;
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++		tack_tbl.cnt[1]++;
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++	} else {
++		ASSERT(i == tcpack_sup_mod->tcpack_info_cnt);
++		DHD_TRACE(("%s %d: No empty tcp ack info tbl\n",
++			__FUNCTION__, __LINE__));
++	}
++	dhd_os_tcpackunlock(dhdp, flags);
++
++exit:
++	/* Unless TCPACK_SUP_DELAYTX, dotxinrx is alwasy TRUE, so no need to set here */
++	if (dhdp->tcpack_sup_mode == TCPACK_SUP_DELAYTX && set_dotxinrx)
++		dhd_bus_set_dotxinrx(dhdp->bus, TRUE);
++
++	return ret;
++}
++
++bool
++dhd_tcpdata_info_get(dhd_pub_t *dhdp, void *pkt)
++{
++	uint8 *ether_hdr;	/* Ethernet header of the new packet */
++	uint16 ether_type;	/* Ethernet type of the new packet */
++	uint8 *ip_hdr;		/* IP header of the new packet */
++	uint8 *tcp_hdr;		/* TCP header of the new packet */
++	uint32 ip_hdr_len;	/* IP header length of the new packet */
++	uint32 cur_framelen;
++	uint16 ip_total_len;	/* Total length of IP packet for the new packet */
++	uint32 tcp_hdr_len;		/* TCP header length of the new packet */
++	uint32 tcp_seq_num;		/* TCP sequence number of the new packet */
++	uint16 tcp_data_len;	/* TCP DATA length that excludes IP and TCP headers */
++	uint32 end_tcp_seq_num;	/* TCP seq number of the last byte in the new packet */
++	tcpack_sup_module_t *tcpack_sup_mod;
++	tcpdata_info_t *tcpdata_info = NULL;
++	tdata_psh_info_t *tdata_psh_info;
++
++	int i;
++	bool ret = FALSE;
++	unsigned long flags;
++
++	if (dhdp->tcpack_sup_mode != TCPACK_SUP_DELAYTX)
++		goto exit;
++
++	ether_hdr = PKTDATA(dhdp->osh, pkt);
++	cur_framelen = PKTLEN(dhdp->osh, pkt);
++
++	ether_type = ether_hdr[12] << 8 | ether_hdr[13];
++
++	if (ether_type != ETHER_TYPE_IP) {
++		DHD_TRACE(("%s %d: Not a IP packet 0x%x\n",
++			__FUNCTION__, __LINE__, ether_type));
++		goto exit;
++	}
++
++	DHD_TRACE(("%s %d: IP pkt! 0x%x\n", __FUNCTION__, __LINE__, ether_type));
++
++	ip_hdr = ether_hdr + ETHER_HDR_LEN;
++	cur_framelen -= ETHER_HDR_LEN;
++
++	ASSERT(cur_framelen >= IPV4_MIN_HEADER_LEN);
++
++	ip_hdr_len = IPV4_HLEN(ip_hdr);
++	if (IP_VER(ip_hdr) != IP_VER_4 || IPV4_PROT(ip_hdr) != IP_PROT_TCP) {
++		DHD_TRACE(("%s %d: Not IPv4 nor TCP! ip ver %d, prot %d\n",
++			__FUNCTION__, __LINE__, IP_VER(ip_hdr), IPV4_PROT(ip_hdr)));
++		goto exit;
++	}
++
++	tcp_hdr = ip_hdr + ip_hdr_len;
++	cur_framelen -= ip_hdr_len;
++
++	ASSERT(cur_framelen >= TCP_MIN_HEADER_LEN);
++
++	DHD_TRACE(("%s %d: TCP pkt!\n", __FUNCTION__, __LINE__));
++
++	ip_total_len = ntoh16_ua(&ip_hdr[IPV4_PKTLEN_OFFSET]);
++	tcp_hdr_len = 4 * TCP_HDRLEN(tcp_hdr[TCP_HLEN_OFFSET]);
++
++	/* This packet is mere TCP ACK, so do nothing */
++	if (ip_total_len == ip_hdr_len + tcp_hdr_len) {
++		DHD_TRACE(("%s %d: Do nothing for no data TCP ACK\n", __FUNCTION__, __LINE__));
++		goto exit;
++	}
++
++	ASSERT(ip_total_len > ip_hdr_len + tcp_hdr_len);
++
++	if ((tcp_hdr[TCP_FLAGS_OFFSET] & TCP_FLAG_PSH) == 0) {
++		DHD_TRACE(("%s %d: Not interested TCP DATA packet\n", __FUNCTION__, __LINE__));
++		goto exit;
++	}
++
++	DHD_TRACE(("%s %d: TCP DATA with nonzero DATA length"
++		" IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR" TCP port %d %d, flag 0x%x\n",
++		__FUNCTION__, __LINE__,
++		IPV4_ADDR_TO_STR(ntoh32_ua(&ip_hdr[IPV4_SRC_IP_OFFSET])),
++		IPV4_ADDR_TO_STR(ntoh32_ua(&ip_hdr[IPV4_DEST_IP_OFFSET])),
++		ntoh16_ua(&tcp_hdr[TCP_SRC_PORT_OFFSET]),
++		ntoh16_ua(&tcp_hdr[TCP_DEST_PORT_OFFSET]),
++		tcp_hdr[TCP_FLAGS_OFFSET]));
++
++	flags = dhd_os_tcpacklock(dhdp);
++	tcpack_sup_mod = dhdp->tcpack_sup_module;
++
++	if (!tcpack_sup_mod) {
++		DHD_ERROR(("%s %d: tcpack suppress module NULL!!\n", __FUNCTION__, __LINE__));
++		ret = BCME_ERROR;
++		dhd_os_tcpackunlock(dhdp, flags);
++		goto exit;
++	}
++
++	/* Look for tcpdata_info that has the same ip src/dst addrs and tcp src/dst ports */
++	i = 0;
++	while (i < tcpack_sup_mod->tcpdata_info_cnt) {
++		tcpdata_info_t *tdata_info_tmp = &tcpack_sup_mod->tcpdata_info_tbl[i];
++		uint32 now_in_ms = OSL_SYSUPTIME();
++		DHD_TRACE(("%s %d: data info[%d], IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR
++			" TCP port %d %d\n", __FUNCTION__, __LINE__, i,
++			IPV4_ADDR_TO_STR(ntoh32_ua(tdata_info_tmp->ip_addr.src)),
++			IPV4_ADDR_TO_STR(ntoh32_ua(tdata_info_tmp->ip_addr.dst)),
++			ntoh16_ua(tdata_info_tmp->tcp_port.src),
++			ntoh16_ua(tdata_info_tmp->tcp_port.dst)));
++
++		/* If both IP address and TCP port number match, we found it so break.
++		 * Note that src/dst addr fields in ip header are contiguous being 8 bytes in total.
++		 * Also, src/dst port fields in TCP header are contiguous being 4 bytes in total.
++		 */
++		if (memcmp(&ip_hdr[IPV4_SRC_IP_OFFSET],
++			(void *)&tdata_info_tmp->ip_addr, IPV4_ADDR_LEN * 2) == 0 &&
++			memcmp(&tcp_hdr[TCP_SRC_PORT_OFFSET],
++			(void *)&tdata_info_tmp->tcp_port, TCP_PORT_LEN * 2) == 0) {
++			tcpdata_info = tdata_info_tmp;
++			tcpdata_info->last_used_time = now_in_ms;
++			break;
++		}
++
++		if (now_in_ms - tdata_info_tmp->last_used_time > TCPDATA_INFO_TIMEOUT) {
++			tdata_psh_info_t *tdata_psh_info_tmp;
++			tcpdata_info_t *last_tdata_info;
++
++			while ((tdata_psh_info_tmp = tdata_info_tmp->tdata_psh_info_head)) {
++				tdata_info_tmp->tdata_psh_info_head = tdata_psh_info_tmp->next;
++				tdata_psh_info_tmp->next = NULL;
++				DHD_TRACE(("%s %d: Clean tdata_psh_info(end_seq %u)!\n",
++					__FUNCTION__, __LINE__, tdata_psh_info_tmp->end_seq));
++				_tdata_psh_info_pool_enq(tcpack_sup_mod, tdata_psh_info_tmp);
++			}
++#ifdef DHDTCPACK_SUP_DBG
++			DHD_ERROR(("%s %d: PSH INFO ENQ %d\n",
++				__FUNCTION__, __LINE__, tcpack_sup_mod->psh_info_enq_num));
++#endif /* DHDTCPACK_SUP_DBG */
++			tcpack_sup_mod->tcpdata_info_cnt--;
++			ASSERT(tcpack_sup_mod->tcpdata_info_cnt >= 0);
++
++			last_tdata_info =
++				&tcpack_sup_mod->tcpdata_info_tbl[tcpack_sup_mod->tcpdata_info_cnt];
++			if (i < tcpack_sup_mod->tcpdata_info_cnt) {
++				ASSERT(last_tdata_info != tdata_info_tmp);
++				bcopy(last_tdata_info, tdata_info_tmp, sizeof(tcpdata_info_t));
++			}
++			bzero(last_tdata_info, sizeof(tcpdata_info_t));
++			DHD_INFO(("%s %d: tcpdata_info(idx %d) is aged out. ttl cnt is now %d\n",
++				__FUNCTION__, __LINE__, i, tcpack_sup_mod->tcpdata_info_cnt));
++			/* Don't increase "i" here, so that the prev last tcpdata_info is checked */
++		} else
++			 i++;
++	}
++
++	tcp_seq_num = ntoh32_ua(&tcp_hdr[TCP_SEQ_NUM_OFFSET]);
++	tcp_data_len = ip_total_len - ip_hdr_len - tcp_hdr_len;
++	end_tcp_seq_num = tcp_seq_num + tcp_data_len;
++
++	if (tcpdata_info == NULL) {
++		ASSERT(i == tcpack_sup_mod->tcpdata_info_cnt);
++		if (i >= TCPDATA_INFO_MAXNUM) {
++			DHD_TRACE(("%s %d: tcp_data_info_tbl FULL! %d %d"
++				" IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR" TCP port %d %d\n",
++				__FUNCTION__, __LINE__, i, tcpack_sup_mod->tcpdata_info_cnt,
++				IPV4_ADDR_TO_STR(ntoh32_ua(&ip_hdr[IPV4_SRC_IP_OFFSET])),
++				IPV4_ADDR_TO_STR(ntoh32_ua(&ip_hdr[IPV4_DEST_IP_OFFSET])),
++				ntoh16_ua(&tcp_hdr[TCP_SRC_PORT_OFFSET]),
++				ntoh16_ua(&tcp_hdr[TCP_DEST_PORT_OFFSET])));
++			dhd_os_tcpackunlock(dhdp, flags);
++			goto exit;
++		}
++		tcpdata_info = &tcpack_sup_mod->tcpdata_info_tbl[i];
++
++		/* No TCP flow with the same IP addr and TCP port is found
++		 * in tcp_data_info_tbl. So add this flow to the table.
++		 */
++		DHD_INFO(("%s %d: Add data info to tbl[%d]: IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR
++			" TCP port %d %d\n",
++			__FUNCTION__, __LINE__, tcpack_sup_mod->tcpdata_info_cnt,
++			IPV4_ADDR_TO_STR(ntoh32_ua(&ip_hdr[IPV4_SRC_IP_OFFSET])),
++			IPV4_ADDR_TO_STR(ntoh32_ua(&ip_hdr[IPV4_DEST_IP_OFFSET])),
++			ntoh16_ua(&tcp_hdr[TCP_SRC_PORT_OFFSET]),
++			ntoh16_ua(&tcp_hdr[TCP_DEST_PORT_OFFSET])));
++		/* Note that src/dst addr fields in ip header are contiguous being 8 bytes in total.
++		 * Also, src/dst port fields in TCP header are contiguous being 4 bytes in total.
++		 */
++		bcopy(&ip_hdr[IPV4_SRC_IP_OFFSET], (void *)&tcpdata_info->ip_addr,
++			IPV4_ADDR_LEN * 2);
++		bcopy(&tcp_hdr[TCP_SRC_PORT_OFFSET], (void *)&tcpdata_info->tcp_port,
++			TCP_PORT_LEN * 2);
++
++		tcpdata_info->last_used_time = OSL_SYSUPTIME();
++		tcpack_sup_mod->tcpdata_info_cnt++;
++	}
++
++	ASSERT(tcpdata_info != NULL);
++
++	tdata_psh_info = _tdata_psh_info_pool_deq(tcpack_sup_mod);
++#ifdef DHDTCPACK_SUP_DBG
++	DHD_TRACE(("%s %d: PSH INFO ENQ %d\n",
++		__FUNCTION__, __LINE__, tcpack_sup_mod->psh_info_enq_num));
++#endif /* DHDTCPACK_SUP_DBG */
++
++	if (tdata_psh_info == NULL) {
++		DHD_ERROR(("%s %d: No more free tdata_psh_info!!\n", __FUNCTION__, __LINE__));
++		ret = BCME_ERROR;
++		dhd_os_tcpackunlock(dhdp, flags);
++		goto exit;
++	}
++	tdata_psh_info->end_seq = end_tcp_seq_num;
++
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++	tack_tbl.cnt[4]++;
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++
++	DHD_TRACE(("%s %d: TCP PSH DATA recvd! end seq %u\n",
++		__FUNCTION__, __LINE__, tdata_psh_info->end_seq));
++
++	ASSERT(tdata_psh_info->next == NULL);
++
++	if (tcpdata_info->tdata_psh_info_head == NULL)
++		tcpdata_info->tdata_psh_info_head = tdata_psh_info;
++	else {
++		ASSERT(tcpdata_info->tdata_psh_info_tail);
++		tcpdata_info->tdata_psh_info_tail->next = tdata_psh_info;
++	}
++	tcpdata_info->tdata_psh_info_tail = tdata_psh_info;
++
++	dhd_os_tcpackunlock(dhdp, flags);
++
++exit:
++	return ret;
++}
++
++bool
++dhd_tcpack_hold(dhd_pub_t *dhdp, void *pkt, int ifidx)
++{
++	uint8 *new_ether_hdr;	/* Ethernet header of the new packet */
++	uint16 new_ether_type;	/* Ethernet type of the new packet */
++	uint8 *new_ip_hdr;		/* IP header of the new packet */
++	uint8 *new_tcp_hdr;		/* TCP header of the new packet */
++	uint32 new_ip_hdr_len;	/* IP header length of the new packet */
++	uint32 cur_framelen;
++	uint32 new_tcp_ack_num;		/* TCP acknowledge number of the new packet */
++	uint16 new_ip_total_len;	/* Total length of IP packet for the new packet */
++	uint32 new_tcp_hdr_len;		/* TCP header length of the new packet */
++	tcpack_sup_module_t *tcpack_sup_mod;
++	tcpack_info_t *tcpack_info_tbl;
++	int i, free_slot = TCPACK_INFO_MAXNUM;
++	bool hold = FALSE;
++	unsigned long flags;
++
++	if (dhdp->tcpack_sup_mode != TCPACK_SUP_HOLD) {
++		goto exit;
++	}
++
++	if (dhdp->tcpack_sup_ratio == 1) {
++		goto exit;
++	}
++
++	new_ether_hdr = PKTDATA(dhdp->osh, pkt);
++	cur_framelen = PKTLEN(dhdp->osh, pkt);
++
++	if (cur_framelen < TCPACKSZMIN || cur_framelen > TCPACKSZMAX) {
++		DHD_TRACE(("%s %d: Too short or long length %d to be TCP ACK\n",
++			__FUNCTION__, __LINE__, cur_framelen));
++		goto exit;
++	}
++
++	new_ether_type = new_ether_hdr[12] << 8 | new_ether_hdr[13];
++
++	if (new_ether_type != ETHER_TYPE_IP) {
++		DHD_TRACE(("%s %d: Not a IP packet 0x%x\n",
++			__FUNCTION__, __LINE__, new_ether_type));
++		goto exit;
++	}
++
++	DHD_TRACE(("%s %d: IP pkt! 0x%x\n", __FUNCTION__, __LINE__, new_ether_type));
++
++	new_ip_hdr = new_ether_hdr + ETHER_HDR_LEN;
++	cur_framelen -= ETHER_HDR_LEN;
++
++	ASSERT(cur_framelen >= IPV4_MIN_HEADER_LEN);
++
++	new_ip_hdr_len = IPV4_HLEN(new_ip_hdr);
++	if (IP_VER(new_ip_hdr) != IP_VER_4 || IPV4_PROT(new_ip_hdr) != IP_PROT_TCP) {
++		DHD_TRACE(("%s %d: Not IPv4 nor TCP! ip ver %d, prot %d\n",
++			__FUNCTION__, __LINE__, IP_VER(new_ip_hdr), IPV4_PROT(new_ip_hdr)));
++		goto exit;
++	}
++
++	new_tcp_hdr = new_ip_hdr + new_ip_hdr_len;
++	cur_framelen -= new_ip_hdr_len;
++
++	ASSERT(cur_framelen >= TCP_MIN_HEADER_LEN);
++
++	DHD_TRACE(("%s %d: TCP pkt!\n", __FUNCTION__, __LINE__));
++
++	/* is it an ack ? Allow only ACK flag, not to suppress others. */
++	if (new_tcp_hdr[TCP_FLAGS_OFFSET] != TCP_FLAG_ACK) {
++		DHD_TRACE(("%s %d: Do not touch TCP flag 0x%x\n",
++			__FUNCTION__, __LINE__, new_tcp_hdr[TCP_FLAGS_OFFSET]));
++		goto exit;
++	}
++
++	new_ip_total_len = ntoh16_ua(&new_ip_hdr[IPV4_PKTLEN_OFFSET]);
++	new_tcp_hdr_len = 4 * TCP_HDRLEN(new_tcp_hdr[TCP_HLEN_OFFSET]);
++
++	/* This packet has TCP data, so just send */
++	if (new_ip_total_len > new_ip_hdr_len + new_tcp_hdr_len) {
++		DHD_TRACE(("%s %d: Do nothing for TCP DATA\n", __FUNCTION__, __LINE__));
++		goto exit;
++	}
++
++	ASSERT(new_ip_total_len == new_ip_hdr_len + new_tcp_hdr_len);
++
++	new_tcp_ack_num = ntoh32_ua(&new_tcp_hdr[TCP_ACK_NUM_OFFSET]);
++
++	DHD_TRACE(("%s %d: TCP ACK with zero DATA length"
++		" IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR" TCP port %d %d\n",
++		__FUNCTION__, __LINE__,
++		IPV4_ADDR_TO_STR(ntoh32_ua(&new_ip_hdr[IPV4_SRC_IP_OFFSET])),
++		IPV4_ADDR_TO_STR(ntoh32_ua(&new_ip_hdr[IPV4_DEST_IP_OFFSET])),
++		ntoh16_ua(&new_tcp_hdr[TCP_SRC_PORT_OFFSET]),
++		ntoh16_ua(&new_tcp_hdr[TCP_DEST_PORT_OFFSET])));
++
++	/* Look for tcp_ack_info that has the same ip src/dst addrs and tcp src/dst ports */
++	flags = dhd_os_tcpacklock(dhdp);
++
++	tcpack_sup_mod = dhdp->tcpack_sup_module;
++	tcpack_info_tbl = tcpack_sup_mod->tcpack_info_tbl;
++
++	if (!tcpack_sup_mod) {
++		DHD_ERROR(("%s %d: tcpack suppress module NULL!!\n", __FUNCTION__, __LINE__));
++		dhd_os_tcpackunlock(dhdp, flags);
++		goto exit;
++	}
++
++	hold = TRUE;
++
++	for (i = 0; i < TCPACK_INFO_MAXNUM; i++) {
++		void *oldpkt;	/* TCPACK packet that is already in txq or DelayQ */
++		uint8 *old_ether_hdr, *old_ip_hdr, *old_tcp_hdr;
++		uint32 old_ip_hdr_len;
++		uint32 old_tcpack_num;	/* TCP ACK number of old TCPACK packet in Q */
++
++		if ((oldpkt = tcpack_info_tbl[i].pkt_in_q) == NULL) {
++			if (free_slot == TCPACK_INFO_MAXNUM) {
++				free_slot = i;
++			}
++			continue;
++		}
++
++		if (PKTDATA(dhdp->osh, oldpkt) == NULL) {
++			DHD_ERROR(("%s %d: oldpkt data NULL!! cur idx %d\n",
++				__FUNCTION__, __LINE__, i));
++			hold = FALSE;
++			dhd_os_tcpackunlock(dhdp, flags);
++			goto exit;
++		}
++
++		old_ether_hdr = tcpack_info_tbl[i].pkt_ether_hdr;
++		old_ip_hdr = old_ether_hdr + ETHER_HDR_LEN;
++		old_ip_hdr_len = IPV4_HLEN(old_ip_hdr);
++		old_tcp_hdr = old_ip_hdr + old_ip_hdr_len;
++
++		DHD_TRACE(("%s %d: oldpkt %p[%d], IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR
++			" TCP port %d %d\n", __FUNCTION__, __LINE__, oldpkt, i,
++			IPV4_ADDR_TO_STR(ntoh32_ua(&old_ip_hdr[IPV4_SRC_IP_OFFSET])),
++			IPV4_ADDR_TO_STR(ntoh32_ua(&old_ip_hdr[IPV4_DEST_IP_OFFSET])),
++			ntoh16_ua(&old_tcp_hdr[TCP_SRC_PORT_OFFSET]),
++			ntoh16_ua(&old_tcp_hdr[TCP_DEST_PORT_OFFSET])));
++
++		/* If either of IP address or TCP port number does not match, skip. */
++		if (memcmp(&new_ip_hdr[IPV4_SRC_IP_OFFSET],
++			&old_ip_hdr[IPV4_SRC_IP_OFFSET], IPV4_ADDR_LEN * 2) ||
++			memcmp(&new_tcp_hdr[TCP_SRC_PORT_OFFSET],
++			&old_tcp_hdr[TCP_SRC_PORT_OFFSET], TCP_PORT_LEN * 2)) {
++			continue;
++		}
++
++		old_tcpack_num = ntoh32_ua(&old_tcp_hdr[TCP_ACK_NUM_OFFSET]);
++
++		if (IS_TCPSEQ_GE(new_tcp_ack_num, old_tcpack_num)) {
++			tcpack_info_tbl[i].supp_cnt++;
++			if (tcpack_info_tbl[i].supp_cnt >= dhdp->tcpack_sup_ratio) {
++				tcpack_info_tbl[i].pkt_in_q = NULL;
++				tcpack_info_tbl[i].pkt_ether_hdr = NULL;
++				tcpack_info_tbl[i].ifidx = 0;
++				tcpack_info_tbl[i].supp_cnt = 0;
++				hold = FALSE;
++			} else {
++				tcpack_info_tbl[i].pkt_in_q = pkt;
++				tcpack_info_tbl[i].pkt_ether_hdr = new_ether_hdr;
++				tcpack_info_tbl[i].ifidx = ifidx;
++			}
++			PKTFREE(dhdp->osh, oldpkt, TRUE);
++		} else {
++			PKTFREE(dhdp->osh, pkt, TRUE);
++		}
++		dhd_os_tcpackunlock(dhdp, flags);
++
++		if (!hold) {
++			_del_timer_sync(&tcpack_info_tbl[i].timer);
++		}
++		goto exit;
++	}
++
++	if (free_slot < TCPACK_INFO_MAXNUM) {
++		/* No TCPACK packet with the same IP addr and TCP port is found
++		 * in tcp_ack_info_tbl. So add this packet to the table.
++		 */
++		DHD_TRACE(("%s %d: Add pkt 0x%p(ether_hdr 0x%p) to tbl[%d]\n",
++			__FUNCTION__, __LINE__, pkt, new_ether_hdr,
++			free_slot));
++
++		tcpack_info_tbl[free_slot].pkt_in_q = pkt;
++		tcpack_info_tbl[free_slot].pkt_ether_hdr = new_ether_hdr;
++		tcpack_info_tbl[free_slot].ifidx = ifidx;
++		tcpack_info_tbl[free_slot].supp_cnt = 1;
++		mod_timer(&tcpack_sup_mod->tcpack_info_tbl[free_slot].timer,
++			jiffies + msecs_to_jiffies(dhdp->tcpack_sup_delay));
++		tcpack_sup_mod->tcpack_info_cnt++;
++	} else {
++		DHD_TRACE(("%s %d: No empty tcp ack info tbl\n",
++			__FUNCTION__, __LINE__));
++	}
++	dhd_os_tcpackunlock(dhdp, flags);
++
++exit:
++	return hold;
++}
++#endif /* DHDTCPACK_SUPPRESS */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_ip.h b/module_drivers/drivers/net/wireless/bcmdhd/dhd_ip.h
+new file mode 100644
+index 000000000..240d85215
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_ip.h
+@@ -0,0 +1,85 @@
++/*
++ * Header file describing the common ip parser function.
++ *
++ * Provides type definitions and function prototypes used to parse ip packet.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_ip.h 536854 2015-02-24 13:17:29Z $
++ */
++
++#ifndef _dhd_ip_h_
++#define _dhd_ip_h_
++
++#ifdef DHDTCPACK_SUPPRESS
++#include <dngl_stats.h>
++#include <bcmutils.h>
++#include <dhd.h>
++#endif /* DHDTCPACK_SUPPRESS */
++
++typedef enum pkt_frag
++{
++	DHD_PKT_FRAG_NONE = 0,
++	DHD_PKT_FRAG_FIRST,
++	DHD_PKT_FRAG_CONT,
++	DHD_PKT_FRAG_LAST
++} pkt_frag_t;
++
++extern pkt_frag_t pkt_frag_info(osl_t *osh, void *p);
++
++#ifdef DHDTCPACK_SUPPRESS
++#define	TCPACKSZMIN	(ETHER_HDR_LEN + IPV4_MIN_HEADER_LEN + TCP_MIN_HEADER_LEN)
++/* Size of MAX possible TCP ACK packet. Extra bytes for IP/TCP option fields */
++#define	TCPACKSZMAX	(TCPACKSZMIN + 100)
++
++/* Max number of TCP streams that have own src/dst IP addrs and TCP ports */
++#define TCPACK_INFO_MAXNUM 4
++#define TCPDATA_INFO_MAXNUM 4
++#define TCPDATA_PSH_INFO_MAXNUM (8 * TCPDATA_INFO_MAXNUM)
++
++#define TCPDATA_INFO_TIMEOUT 5000	/* Remove tcpdata_info if inactive for this time (in ms) */
++
++#define DEFAULT_TCPACK_SUPP_RATIO 3
++#ifndef CUSTOM_TCPACK_SUPP_RATIO
++#define CUSTOM_TCPACK_SUPP_RATIO DEFAULT_TCPACK_SUPP_RATIO
++#endif /* CUSTOM_TCPACK_SUPP_RATIO */
++
++#define DEFAULT_TCPACK_DELAY_TIME 10 /* ms */
++#ifndef CUSTOM_TCPACK_DELAY_TIME
++#define CUSTOM_TCPACK_DELAY_TIME DEFAULT_TCPACK_DELAY_TIME
++#endif /* CUSTOM_TCPACK_DELAY_TIME */
++
++extern int dhd_tcpack_suppress_set(dhd_pub_t *dhdp, uint8 on);
++extern void dhd_tcpack_info_tbl_clean(dhd_pub_t *dhdp);
++extern int dhd_tcpack_check_xmit(dhd_pub_t *dhdp, void *pkt);
++extern bool dhd_tcpack_suppress(dhd_pub_t *dhdp, void *pkt);
++extern bool dhd_tcpdata_info_get(dhd_pub_t *dhdp, void *pkt);
++extern bool dhd_tcpack_hold(dhd_pub_t *dhdp, void *pkt, int ifidx);
++/* #define DHDTCPACK_SUP_DBG */
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++extern counter_tbl_t tack_tbl;
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++#endif /* DHDTCPACK_SUPPRESS */
++
++#endif /* _dhd_ip_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux.c
+new file mode 100644
+index 000000000..c5a5aa87a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux.c
+@@ -0,0 +1,19882 @@
++/*
++ * Broadcom Dongle Host Driver (DHD), Linux-specific network interface
++ * Basically selected code segments from usb-cdc.c and usb-rndis.c
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_linux.c 710862 2017-07-14 07:43:59Z $
++ */
++
++#include <typedefs.h>
++#include <uapi/linux/sched/types.h>
++#include <linuxver.h>
++#include <osl.h>
++#ifdef SHOW_LOGTRACE
++#include <linux/syscalls.h>
++#include <event_log.h>
++#endif /* SHOW_LOGTRACE */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/skbuff.h>
++#include <linux/netdevice.h>
++#include <linux/inetdevice.h>
++#include <linux/rtnetlink.h>
++#include <linux/etherdevice.h>
++#include <linux/random.h>
++#include <linux/spinlock.h>
++#include <linux/ethtool.h>
++#include <linux/fcntl.h>
++#include <linux/fs.h>
++#include <linux/ip.h>
++#include <linux/reboot.h>
++#include <linux/notifier.h>
++#include <net/addrconf.h>
++#ifdef ENABLE_ADAPTIVE_SCHED
++#include <linux/cpufreq.h>
++#endif /* ENABLE_ADAPTIVE_SCHED */
++
++#include <asm/uaccess.h>
++#include <asm/unaligned.h>
++
++#include <epivers.h>
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <bcmdevs.h>
++
++
++#include <ethernet.h>
++#include <bcmevent.h>
++#include <vlan.h>
++#include <802.3.h>
++
++#include <dngl_stats.h>
++#include <dhd_linux_wq.h>
++#include <dhd.h>
++#include <dhd_linux.h>
++#ifdef DHD_WET
++#include <dhd_wet.h>
++#endif /* DHD_WET */
++#ifdef PCIE_FULL_DONGLE
++#include <dhd_flowring.h>
++#endif
++#include <dhd_bus.h>
++#include <dhd_proto.h>
++#include <dhd_config.h>
++#ifdef WL_ESCAN
++#include <wl_escan.h>
++#endif
++#include <dhd_dbg.h>
++#include <dhd_debug.h>
++#ifdef CONFIG_HAS_WAKELOCK
++#include <linux/wakelock.h>
++#endif
++#ifdef WL_CFG80211
++#include <wl_cfg80211.h>
++#endif
++#ifdef PNO_SUPPORT
++#include <dhd_pno.h>
++#endif
++#ifdef RTT_SUPPORT
++#include <dhd_rtt.h>
++#endif
++#ifdef DHD_TIMESYNC
++#include <dhd_timesync.h>
++#endif /* DHD_TIMESYNC */
++
++#ifdef CONFIG_COMPAT
++#include <linux/compat.h>
++#endif
++
++#if defined(CONFIG_SOC_EXYNOS8895)
++#include <linux/exynos-pci-ctrl.h>
++#endif /* CONFIG_SOC_EXYNOS8895 */
++
++#ifdef DHD_WMF
++#include <dhd_wmf_linux.h>
++#endif /* DHD_WMF */
++
++#ifdef DHD_L2_FILTER
++#include <bcmicmp.h>
++#include <bcm_l2_filter.h>
++#include <dhd_l2_filter.h>
++#endif /* DHD_L2_FILTER */
++
++#ifdef DHD_PSTA
++#include <dhd_psta.h>
++#endif /* DHD_PSTA */
++
++
++#ifdef DHDTCPACK_SUPPRESS
++#include <dhd_ip.h>
++#endif /* DHDTCPACK_SUPPRESS */
++#include <dhd_daemon.h>
++#ifdef DHD_PKT_LOGGING
++#include <dhd_pktlog.h>
++#endif /* DHD_PKT_LOGGING */
++#if defined(STAT_REPORT)
++#include <wl_statreport.h>
++#endif /* STAT_REPORT */
++#ifdef DHD_DEBUG_PAGEALLOC
++typedef void (*page_corrupt_cb_t)(void *handle, void *addr_corrupt, size_t len);
++void dhd_page_corrupt_cb(void *handle, void *addr_corrupt, size_t len);
++extern void register_page_corrupt_cb(page_corrupt_cb_t cb, void* handle);
++#endif /* DHD_DEBUG_PAGEALLOC */
++
++
++#if defined(DHD_LB)
++#if !defined(PCIE_FULL_DONGLE)
++#error "DHD Loadbalancing only supported on PCIE_FULL_DONGLE"
++#endif /* !PCIE_FULL_DONGLE */
++#endif /* DHD_LB */
++
++#if defined(DHD_LB_RXP) || defined(DHD_LB_RXC) || defined(DHD_LB_TXC) || \
++	defined(DHD_LB_STATS)
++#if !defined(DHD_LB)
++#error "DHD loadbalance derivatives are supported only if DHD_LB is defined"
++#endif /* !DHD_LB */
++#endif /* DHD_LB_RXP || DHD_LB_RXC || DHD_LB_TXC || DHD_LB_STATS */
++
++#if defined(DHD_LB)
++/* Dynamic CPU selection for load balancing */
++#include <linux/cpu.h>
++#include <linux/cpumask.h>
++#include <linux/notifier.h>
++#include <linux/workqueue.h>
++#include <asm/atomic.h>
++
++#if !defined(DHD_LB_PRIMARY_CPUS)
++#define DHD_LB_PRIMARY_CPUS     0x0 /* Big CPU coreids mask */
++#endif
++#if !defined(DHD_LB_SECONDARY_CPUS)
++#define DHD_LB_SECONDARY_CPUS   0xFE /* Little CPU coreids mask */
++#endif
++
++#define HIST_BIN_SIZE	9
++
++static void dhd_rx_napi_dispatcher_fn(struct work_struct * work);
++
++#if defined(DHD_LB_TXP)
++static void dhd_lb_tx_handler(unsigned long data);
++static void dhd_tx_dispatcher_work(struct work_struct * work);
++static void dhd_tx_dispatcher_fn(dhd_pub_t *dhdp);
++static void dhd_lb_tx_dispatch(dhd_pub_t *dhdp);
++
++/* Pkttag not compatible with PROP_TXSTATUS or WLFC */
++typedef struct dhd_tx_lb_pkttag_fr {
++	struct net_device *net;
++	int ifidx;
++} dhd_tx_lb_pkttag_fr_t;
++
++#define DHD_LB_TX_PKTTAG_SET_NETDEV(tag, netdevp)	((tag)->net = netdevp)
++#define DHD_LB_TX_PKTTAG_NETDEV(tag)			((tag)->net)
++
++#define DHD_LB_TX_PKTTAG_SET_IFIDX(tag, ifidx)	((tag)->ifidx = ifidx)
++#define DHD_LB_TX_PKTTAG_IFIDX(tag)		((tag)->ifidx)
++#endif /* DHD_LB_TXP */
++#endif /* DHD_LB */
++
++#ifdef HOFFLOAD_MODULES
++#include <linux/firmware.h>
++#endif
++
++#ifdef WLMEDIA_HTSF
++#include <linux/time.h>
++#include <htsf.h>
++
++#define HTSF_MINLEN 200    /* min. packet length to timestamp */
++#define HTSF_BUS_DELAY 150 /* assume a fix propagation in us  */
++#define TSMAX  1000        /* max no. of timing record kept   */
++#define NUMBIN 34
++
++static uint32 tsidx = 0;
++static uint32 htsf_seqnum = 0;
++uint32 tsfsync;
++struct timeval tsync;
++static uint32 tsport = 5010;
++
++typedef struct histo_ {
++	uint32 bin[NUMBIN];
++} histo_t;
++
++#if !ISPOWEROF2(DHD_SDALIGN)
++#error DHD_SDALIGN is not a power of 2!
++#endif
++
++static histo_t vi_d1, vi_d2, vi_d3, vi_d4;
++#endif /* WLMEDIA_HTSF */
++
++#ifdef WL_MONITOR
++#include <bcmmsgbuf.h>
++#include <bcmwifi_monitor.h>
++#endif
++
++#define htod32(i) (i)
++#define htod16(i) (i)
++#define dtoh32(i) (i)
++#define dtoh16(i) (i)
++#define htodchanspec(i) (i)
++#define dtohchanspec(i) (i)
++
++#ifdef STBLINUX
++#ifdef quote_str
++#undef quote_str
++#endif /* quote_str */
++#ifdef to_str
++#undef to_str
++#endif /* quote_str */
++#define to_str(s) #s
++#define quote_str(s) to_str(s)
++
++static char *driver_target = "driver_target: "quote_str(BRCM_DRIVER_TARGET);
++#endif /* STBLINUX */
++
++
++
++#if defined(SOFTAP)
++extern bool ap_cfg_running;
++extern bool ap_fw_loaded;
++#endif
++
++extern void dhd_dump_eapol_4way_message(dhd_pub_t *dhd, char *ifname,
++	char *dump_data, bool direction);
++
++#ifdef FIX_CPU_MIN_CLOCK
++#include <linux/pm_qos.h>
++#endif /* FIX_CPU_MIN_CLOCK */
++
++#ifdef SET_RANDOM_MAC_SOFTAP
++#ifndef CONFIG_DHD_SET_RANDOM_MAC_VAL
++#define CONFIG_DHD_SET_RANDOM_MAC_VAL	0x001A11
++#endif
++static u32 vendor_oui = CONFIG_DHD_SET_RANDOM_MAC_VAL;
++#endif /* SET_RANDOM_MAC_SOFTAP */
++
++#ifdef ENABLE_ADAPTIVE_SCHED
++#define DEFAULT_CPUFREQ_THRESH		1000000	/* threshold frequency : 1000000 = 1GHz */
++#ifndef CUSTOM_CPUFREQ_THRESH
++#define CUSTOM_CPUFREQ_THRESH	DEFAULT_CPUFREQ_THRESH
++#endif /* CUSTOM_CPUFREQ_THRESH */
++#endif /* ENABLE_ADAPTIVE_SCHED */
++
++/* enable HOSTIP cache update from the host side when an eth0:N is up */
++#define AOE_IP_ALIAS_SUPPORT 1
++
++#ifdef BCM_FD_AGGR
++#include <bcm_rpc.h>
++#include <bcm_rpc_tp.h>
++#endif
++#ifdef PROP_TXSTATUS
++#include <wlfc_proto.h>
++#include <dhd_wlfc.h>
++#endif
++
++#include <wl_android.h>
++
++/* Maximum STA per radio */
++#define DHD_MAX_STA     32
++
++
++
++const uint8 wme_fifo2ac[] = { 0, 1, 2, 3, 1, 1 };
++const uint8 prio2fifo[8] = { 1, 0, 0, 1, 2, 2, 3, 3 };
++#define WME_PRIO2AC(prio)  wme_fifo2ac[prio2fifo[(prio)]]
++
++#ifdef ARP_OFFLOAD_SUPPORT
++void aoe_update_host_ipv4_table(dhd_pub_t *dhd_pub, u32 ipa, bool add, int idx);
++static int dhd_inetaddr_notifier_call(struct notifier_block *this,
++	unsigned long event, void *ptr);
++static struct notifier_block dhd_inetaddr_notifier = {
++	.notifier_call = dhd_inetaddr_notifier_call
++};
++/* to make sure we won't register the same notifier twice, otherwise a loop is likely to be
++ * created in kernel notifier link list (with 'next' pointing to itself)
++ */
++static bool dhd_inetaddr_notifier_registered = FALSE;
++#endif /* ARP_OFFLOAD_SUPPORT */
++
++#if defined(CONFIG_IPV6) && defined(IPV6_NDO_SUPPORT)
++int dhd_inet6addr_notifier_call(struct notifier_block *this,
++	unsigned long event, void *ptr);
++static struct notifier_block dhd_inet6addr_notifier = {
++	.notifier_call = dhd_inet6addr_notifier_call
++};
++/* to make sure we won't register the same notifier twice, otherwise a loop is likely to be
++ * created in kernel notifier link list (with 'next' pointing to itself)
++ */
++static bool dhd_inet6addr_notifier_registered = FALSE;
++#endif /* CONFIG_IPV6 && IPV6_NDO_SUPPORT */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_PM_SLEEP)
++#include <linux/suspend.h>
++volatile bool dhd_mmc_suspend = FALSE;
++DECLARE_WAIT_QUEUE_HEAD(dhd_dpc_wait);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_PM_SLEEP) */
++
++#if defined(OOB_INTR_ONLY) || defined(FORCE_WOWLAN)
++extern void dhd_enable_oob_intr(struct dhd_bus *bus, bool enable);
++#endif 
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++static void dhd_hang_process(void *dhd_info, void *event_data, u8 event);
++#endif 
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++MODULE_LICENSE("GPL and additional rights");
++#endif /* LinuxVer */
++
++#if defined(MULTIPLE_SUPPLICANT)
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++DEFINE_MUTEX(_dhd_mutex_lock_);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25)) */
++#endif 
++static int dhd_suspend_resume_helper(struct dhd_info *dhd, int val, int force);
++
++#ifdef CONFIG_BCM_DETECT_CONSECUTIVE_HANG
++#define MAX_CONSECUTIVE_HANG_COUNTS 5
++#endif /* CONFIG_BCM_DETECT_CONSECUTIVE_HANG */
++
++#include <dhd_bus.h>
++
++#ifdef DHD_ULP
++#include <dhd_ulp.h>
++#endif /* DHD_ULP */
++
++#ifdef BCM_FD_AGGR
++#define DBUS_RX_BUFFER_SIZE_DHD(net)	(BCM_RPC_TP_DNGL_AGG_MAX_BYTE)
++#else
++#ifndef PROP_TXSTATUS
++#define DBUS_RX_BUFFER_SIZE_DHD(net)	(net->mtu + net->hard_header_len + dhd->pub.hdrlen)
++#else
++#define DBUS_RX_BUFFER_SIZE_DHD(net)	(net->mtu + net->hard_header_len + dhd->pub.hdrlen + 128)
++#endif
++#endif /* BCM_FD_AGGR */
++
++#ifdef PROP_TXSTATUS
++extern bool dhd_wlfc_skip_fc(void * dhdp, uint8 idx);
++extern void dhd_wlfc_plat_init(void *dhd);
++extern void dhd_wlfc_plat_deinit(void *dhd);
++#endif /* PROP_TXSTATUS */
++#ifdef USE_DYNAMIC_F2_BLKSIZE
++extern uint sd_f2_blocksize;
++extern int dhdsdio_func_blocksize(dhd_pub_t *dhd, int function_num, int block_size);
++#endif /* USE_DYNAMIC_F2_BLKSIZE */
++
++#if LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 15)
++const char *
++print_tainted()
++{
++	return "";
++}
++#endif	/* LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 15) */
++
++/* Linux wireless extension support */
++#if defined(WL_WIRELESS_EXT)
++#include <wl_iw.h>
++extern wl_iw_extra_params_t  g_wl_iw_params;
++#endif /* defined(WL_WIRELESS_EXT) */
++
++#ifdef CONFIG_PARTIALSUSPEND_SLP
++#include <linux/partialsuspend_slp.h>
++#define CONFIG_HAS_EARLYSUSPEND
++#define DHD_USE_EARLYSUSPEND
++#define register_early_suspend		register_pre_suspend
++#define unregister_early_suspend	unregister_pre_suspend
++#define early_suspend				pre_suspend
++#define EARLY_SUSPEND_LEVEL_BLANK_SCREEN		50
++#else
++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND)
++#include <linux/earlysuspend.h>
++#endif /* defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND) */
++#endif /* CONFIG_PARTIALSUSPEND_SLP */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++#include <linux/nl80211.h>
++#endif /* OEM_ANDROID && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) */
++
++#if defined(BCMPCIE)
++extern int dhd_get_suspend_bcn_li_dtim(dhd_pub_t *dhd, int *dtim_period, int *bcn_interval);
++#else
++extern int dhd_get_suspend_bcn_li_dtim(dhd_pub_t *dhd);
++#endif /* OEM_ANDROID && BCMPCIE */
++
++#ifdef PKT_FILTER_SUPPORT
++extern void dhd_pktfilter_offload_set(dhd_pub_t * dhd, char *arg);
++extern void dhd_pktfilter_offload_enable(dhd_pub_t * dhd, char *arg, int enable, int master_mode);
++extern void dhd_pktfilter_offload_delete(dhd_pub_t *dhd, int id);
++#endif
++
++#if defined(PKT_FILTER_SUPPORT) && defined(APF)
++static int __dhd_apf_add_filter(struct net_device *ndev, uint32 filter_id,
++	u8* program, uint32 program_len);
++static int __dhd_apf_config_filter(struct net_device *ndev, uint32 filter_id,
++	uint32 mode, uint32 enable);
++static int __dhd_apf_delete_filter(struct net_device *ndev, uint32 filter_id);
++#endif /* PKT_FILTER_SUPPORT && APF */
++
++
++
++static INLINE int argos_register_notifier_init(struct net_device *net) { return 0;}
++static INLINE int argos_register_notifier_deinit(void) { return 0;}
++
++#if defined(BT_OVER_SDIO)
++extern void wl_android_set_wifi_on_flag(bool enable);
++#endif /* BT_OVER_SDIO */
++
++
++#if defined(TRAFFIC_MGMT_DWM)
++void traffic_mgmt_pkt_set_prio(dhd_pub_t *dhdp, void * pktbuf);
++#endif 
++
++#ifdef DHD_FW_COREDUMP
++static void dhd_mem_dump(void *dhd_info, void *event_info, u8 event);
++#endif /* DHD_FW_COREDUMP */
++#ifdef DHD_LOG_DUMP
++#define DLD_BUFFER_NUM  2
++/* [0]: General, [1]: Special */
++struct dhd_log_dump_buf g_dld_buf[DLD_BUFFER_NUM];
++static const int dld_buf_size[] = {
++	(1024 * 1024),	/* DHD_LOG_DUMP_BUFFER_SIZE */
++	(8 * 1024)	/* DHD_LOG_DUMP_BUFFER_EX_SIZE */
++};
++static void dhd_log_dump_init(dhd_pub_t *dhd);
++static void dhd_log_dump_deinit(dhd_pub_t *dhd);
++static void dhd_log_dump(void *handle, void *event_info, u8 event);
++void dhd_schedule_log_dump(dhd_pub_t *dhdp);
++static int do_dhd_log_dump(dhd_pub_t *dhdp);
++#endif /* DHD_LOG_DUMP */
++
++#ifdef DHD_DEBUG_UART
++#include <linux/kmod.h>
++#define DHD_DEBUG_UART_EXEC_PATH	"/system/bin/wldu"
++static void dhd_debug_uart_exec_rd(void *handle, void *event_info, u8 event);
++static void dhd_debug_uart_exec(dhd_pub_t *dhdp, char *cmd);
++#endif	/* DHD_DEBUG_UART */
++
++static int dhd_reboot_callback(struct notifier_block *this, unsigned long code, void *unused);
++static struct notifier_block dhd_reboot_notifier = {
++	.notifier_call = dhd_reboot_callback,
++	.priority = 1,
++};
++
++#ifdef BCMPCIE
++static int is_reboot = 0;
++#endif /* BCMPCIE */
++
++#if defined(BT_OVER_SDIO)
++#include "dhd_bt_interface.h"
++dhd_pub_t	*g_dhd_pub = NULL;
++#endif /* defined (BT_OVER_SDIO) */
++
++atomic_t exit_in_progress = ATOMIC_INIT(0);
++
++typedef struct dhd_if_event {
++	struct list_head	list;
++	wl_event_data_if_t	event;
++	char			name[IFNAMSIZ+1];
++	uint8			mac[ETHER_ADDR_LEN];
++} dhd_if_event_t;
++
++/* Interface control information */
++typedef struct dhd_if {
++	struct dhd_info *info;			/* back pointer to dhd_info */
++	/* OS/stack specifics */
++	struct net_device *net;
++	int				idx;			/* iface idx in dongle */
++	uint			subunit;		/* subunit */
++	uint8			mac_addr[ETHER_ADDR_LEN];	/* assigned MAC address */
++	bool			set_macaddress;
++	bool			set_multicast;
++	uint8			bssidx;			/* bsscfg index for the interface */
++	bool			attached;		/* Delayed attachment when unset */
++	bool			txflowcontrol;	/* Per interface flow control indicator */
++	char			name[IFNAMSIZ+1]; /* linux interface name */
++	char			dngl_name[IFNAMSIZ+1]; /* corresponding dongle interface name */
++	struct net_device_stats stats;
++#ifdef DHD_WMF
++	dhd_wmf_t		wmf;		/* per bsscfg wmf setting */
++	bool	wmf_psta_disable;		/* enable/disable MC pkt to each mac
++						 * of MC group behind PSTA
++						 */
++#endif /* DHD_WMF */
++#ifdef PCIE_FULL_DONGLE
++	struct list_head sta_list;		/* sll of associated stations */
++#if !defined(BCM_GMAC3)
++	spinlock_t	sta_list_lock;		/* lock for manipulating sll */
++#endif /* ! BCM_GMAC3 */
++#endif /* PCIE_FULL_DONGLE */
++	uint32  ap_isolate;			/* ap-isolation settings */
++#ifdef DHD_L2_FILTER
++	bool parp_enable;
++	bool parp_discard;
++	bool parp_allnode;
++	arp_table_t *phnd_arp_table;
++	/* for Per BSS modification */
++	bool dhcp_unicast;
++	bool block_ping;
++	bool grat_arp;
++#endif /* DHD_L2_FILTER */
++#ifdef DHD_MCAST_REGEN
++	bool mcast_regen_bss_enable;
++#endif
++	bool rx_pkt_chainable;		/* set all rx packet to chainable config by default */
++	cumm_ctr_t cumm_ctr;			/* cummulative queue length of child flowrings */
++} dhd_if_t;
++
++#ifdef WLMEDIA_HTSF
++typedef struct {
++	uint32 low;
++	uint32 high;
++} tsf_t;
++
++typedef struct {
++	uint32 last_cycle;
++	uint32 last_sec;
++	uint32 last_tsf;
++	uint32 coef;     /* scaling factor */
++	uint32 coefdec1; /* first decimal  */
++	uint32 coefdec2; /* second decimal */
++} htsf_t;
++
++typedef struct {
++	uint32 t1;
++	uint32 t2;
++	uint32 t3;
++	uint32 t4;
++} tstamp_t;
++
++static tstamp_t ts[TSMAX];
++static tstamp_t maxdelayts;
++static uint32 maxdelay = 0, tspktcnt = 0, maxdelaypktno = 0;
++
++#endif  /* WLMEDIA_HTSF */
++
++struct ipv6_work_info_t {
++	uint8			if_idx;
++	char			ipv6_addr[IPV6_ADDR_LEN];
++	unsigned long		event;
++};
++static void dhd_process_daemon_msg(struct sk_buff *skb);
++static void dhd_destroy_to_notifier_skt(void);
++static int dhd_create_to_notifier_skt(void);
++static struct sock *nl_to_event_sk = NULL;
++int sender_pid = 0;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++struct netlink_kernel_cfg g_cfg = {
++	.groups = 1,
++	.input = dhd_process_daemon_msg,
++};
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0)) */
++
++typedef struct dhd_dump {
++	uint8 *buf;
++	int bufsize;
++} dhd_dump_t;
++
++
++/* When Perimeter locks are deployed, any blocking calls must be preceeded
++ * with a PERIM UNLOCK and followed by a PERIM LOCK.
++ * Examples of blocking calls are: schedule_timeout(), down_interruptible(),
++ * wait_event_timeout().
++ */
++
++/* Local private structure (extension of pub) */
++typedef struct dhd_info {
++#if defined(WL_WIRELESS_EXT)
++	wl_iw_t		iw;		/* wireless extensions state (must be first) */
++#endif /* defined(WL_WIRELESS_EXT) */
++	dhd_pub_t pub;
++	dhd_if_t *iflist[DHD_MAX_IFS]; /* for supporting multiple interfaces */
++
++	wifi_adapter_info_t *adapter;			/* adapter information, interrupt, fw path etc. */
++	char fw_path[PATH_MAX];		/* path to firmware image */
++	char nv_path[PATH_MAX];		/* path to nvram vars file */
++	char clm_path[PATH_MAX];		/* path to clm vars file */
++	char conf_path[PATH_MAX];	/* path to config vars file */
++#ifdef DHD_UCODE_DOWNLOAD
++	char uc_path[PATH_MAX];	/* path to ucode image */
++#endif /* DHD_UCODE_DOWNLOAD */
++
++	/* serialize dhd iovars */
++	struct mutex dhd_iovar_mutex;
++
++	struct semaphore proto_sem;
++#ifdef PROP_TXSTATUS
++	spinlock_t	wlfc_spinlock;
++
++#ifdef BCMDBUS
++	ulong		wlfc_lock_flags;
++	ulong		wlfc_pub_lock_flags;
++#endif /* BCMDBUS */
++#endif /* PROP_TXSTATUS */
++#ifdef WLMEDIA_HTSF
++	htsf_t  htsf;
++#endif
++	wait_queue_head_t ioctl_resp_wait;
++	wait_queue_head_t d3ack_wait;
++	wait_queue_head_t dhd_bus_busy_state_wait;
++	uint32	default_wd_interval;
++
++	timer_list_compat_t timer;
++	bool wd_timer_valid;
++#ifdef DHD_PCIE_RUNTIMEPM
++	timer_list_compat_t rpm_timer;
++	bool rpm_timer_valid;
++	tsk_ctl_t	  thr_rpm_ctl;
++#endif /* DHD_PCIE_RUNTIMEPM */
++	struct tasklet_struct tasklet;
++	spinlock_t	sdlock;
++	spinlock_t	txqlock;
++	spinlock_t	rxqlock;
++	spinlock_t	dhd_lock;
++#ifdef BCMDBUS
++	ulong		txqlock_flags;
++#else
++
++	struct semaphore sdsem;
++	tsk_ctl_t	thr_dpc_ctl;
++	tsk_ctl_t	thr_wdt_ctl;
++#endif /* BCMDBUS */
++
++	tsk_ctl_t	thr_rxf_ctl;
++	spinlock_t	rxf_lock;
++	bool		rxthread_enabled;
++
++	/* Wakelocks */
++#if defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++	struct wake_lock wl_wifi;   /* Wifi wakelock */
++	struct wake_lock wl_rxwake; /* Wifi rx wakelock */
++	struct wake_lock wl_ctrlwake; /* Wifi ctrl wakelock */
++	struct wake_lock wl_wdwake; /* Wifi wd wakelock */
++	struct wake_lock wl_evtwake; /* Wifi event wakelock */
++	struct wake_lock wl_pmwake;   /* Wifi pm handler wakelock */
++	struct wake_lock wl_txflwake; /* Wifi tx flow wakelock */
++#ifdef BCMPCIE_OOB_HOST_WAKE
++	struct wake_lock wl_intrwake; /* Host wakeup wakelock */
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#ifdef DHD_USE_SCAN_WAKELOCK
++	struct wake_lock wl_scanwake;  /* Wifi scan wakelock */
++#endif /* DHD_USE_SCAN_WAKELOCK */
++#endif /* CONFIG_HAS_WAKELOCK && LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	/* net_device interface lock, prevent race conditions among net_dev interface
++	 * calls and wifi_on or wifi_off
++	 */
++	struct mutex dhd_net_if_mutex;
++	struct mutex dhd_suspend_mutex;
++#if defined(PKT_FILTER_SUPPORT) && defined(APF)
++	struct mutex dhd_apf_mutex;
++#endif /* PKT_FILTER_SUPPORT && APF */
++#endif 
++	spinlock_t wakelock_spinlock;
++	spinlock_t wakelock_evt_spinlock;
++	uint32 wakelock_counter;
++	int wakelock_wd_counter;
++	int wakelock_rx_timeout_enable;
++	int wakelock_ctrl_timeout_enable;
++	bool waive_wakelock;
++	uint32 wakelock_before_waive;
++
++	/* Thread to issue ioctl for multicast */
++	wait_queue_head_t ctrl_wait;
++	atomic_t pend_8021x_cnt;
++	dhd_attach_states_t dhd_state;
++#ifdef SHOW_LOGTRACE
++	dhd_event_log_t event_data;
++#endif /* SHOW_LOGTRACE */
++
++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND)
++	struct early_suspend early_suspend;
++#endif /* CONFIG_HAS_EARLYSUSPEND && DHD_USE_EARLYSUSPEND */
++
++#ifdef ARP_OFFLOAD_SUPPORT
++	u32 pend_ipaddr;
++#endif /* ARP_OFFLOAD_SUPPORT */
++#ifdef BCM_FD_AGGR
++	void *rpc_th;
++	void *rpc_osh;
++	timer_list_compat_t rpcth_timer;
++	bool rpcth_timer_active;
++	uint8 fdaggr;
++#endif
++#ifdef DHDTCPACK_SUPPRESS
++	spinlock_t	tcpack_lock;
++#endif /* DHDTCPACK_SUPPRESS */
++#ifdef FIX_CPU_MIN_CLOCK
++	bool cpufreq_fix_status;
++	struct mutex cpufreq_fix;
++	struct pm_qos_request dhd_cpu_qos;
++#ifdef FIX_BUS_MIN_CLOCK
++	struct pm_qos_request dhd_bus_qos;
++#endif /* FIX_BUS_MIN_CLOCK */
++#endif /* FIX_CPU_MIN_CLOCK */
++	void			*dhd_deferred_wq;
++#ifdef DEBUG_CPU_FREQ
++	struct notifier_block freq_trans;
++	int __percpu *new_freq;
++#endif
++	unsigned int unit;
++	struct notifier_block pm_notifier;
++#ifdef DHD_PSTA
++	uint32	psta_mode;	/* PSTA or PSR */
++#endif /* DHD_PSTA */
++#ifdef DHD_WET
++	        uint32  wet_mode;
++#endif /* DHD_WET */
++#ifdef DHD_DEBUG
++	dhd_dump_t *dump;
++	timer_list_compat_t join_timer;
++	u32 join_timeout_val;
++	bool join_timer_active;
++	uint scan_time_count;
++	timer_list_compat_t scan_timer;
++	bool scan_timer_active;
++#endif
++#if defined(DHD_LB)
++	/* CPU Load Balance dynamic CPU selection */
++
++	/* Variable that tracks the currect CPUs available for candidacy */
++	cpumask_var_t cpumask_curr_avail;
++
++	/* Primary and secondary CPU mask */
++	cpumask_var_t cpumask_primary, cpumask_secondary; /* configuration */
++	cpumask_var_t cpumask_primary_new, cpumask_secondary_new; /* temp */
++
++	struct notifier_block cpu_notifier;
++
++	/* Tasklet to handle Tx Completion packet freeing */
++	struct tasklet_struct tx_compl_tasklet;
++	atomic_t                   tx_compl_cpu;
++
++	/* Tasklet to handle RxBuf Post during Rx completion */
++	struct tasklet_struct rx_compl_tasklet;
++	atomic_t                   rx_compl_cpu;
++
++	/* Napi struct for handling rx packet sendup. Packets are removed from
++	 * H2D RxCompl ring and placed into rx_pend_queue. rx_pend_queue is then
++	 * appended to rx_napi_queue (w/ lock) and the rx_napi_struct is scheduled
++	 * to run to rx_napi_cpu.
++	 */
++	struct sk_buff_head   rx_pend_queue  ____cacheline_aligned;
++	struct sk_buff_head   rx_napi_queue  ____cacheline_aligned;
++	struct napi_struct    rx_napi_struct ____cacheline_aligned;
++	atomic_t                   rx_napi_cpu; /* cpu on which the napi is dispatched */
++	struct net_device    *rx_napi_netdev; /* netdev of primary interface */
++
++	struct work_struct    rx_napi_dispatcher_work;
++	struct work_struct	  tx_compl_dispatcher_work;
++	struct work_struct    tx_dispatcher_work;
++
++	/* Number of times DPC Tasklet ran */
++	uint32	dhd_dpc_cnt;
++	/* Number of times NAPI processing got scheduled */
++	uint32	napi_sched_cnt;
++	/* Number of times NAPI processing ran on each available core */
++	uint32	*napi_percpu_run_cnt;
++	/* Number of times RX Completions got scheduled */
++	uint32	rxc_sched_cnt;
++	/* Number of times RX Completion ran on each available core */
++	uint32	*rxc_percpu_run_cnt;
++	/* Number of times TX Completions got scheduled */
++	uint32	txc_sched_cnt;
++	/* Number of times TX Completions ran on each available core */
++	uint32	*txc_percpu_run_cnt;
++	/* CPU status */
++	/* Number of times each CPU came online */
++	uint32	*cpu_online_cnt;
++	/* Number of times each CPU went offline */
++	uint32	*cpu_offline_cnt;
++
++	/* Number of times TX processing run on each core */
++	uint32	*txp_percpu_run_cnt;
++	/* Number of times TX start run on each core */
++	uint32	*tx_start_percpu_run_cnt;
++
++	/* Tx load balancing */
++
++	/* TODO: Need to see if batch processing is really required in case of TX
++	 * processing. In case of RX the Dongle can send a bunch of rx completions,
++	 * hence we took a 3 queue approach
++	 * enque - adds the skbs to rx_pend_queue
++	 * dispatch - uses a lock and adds the list of skbs from pend queue to
++	 *            napi queue
++	 * napi processing - copies the pend_queue into a local queue and works
++	 * on it.
++	 * But for TX its going to be 1 skb at a time, so we are just thinking
++	 * of using only one queue and use the lock supported skb queue functions
++	 * to add and process it. If its in-efficient we'll re-visit the queue
++	 * design.
++	 */
++
++	/* When the NET_TX tries to send a TX packet put it into tx_pend_queue */
++	/* struct sk_buff_head		tx_pend_queue  ____cacheline_aligned;  */
++	/*
++	 * From the Tasklet that actually sends out data
++	 * copy the list tx_pend_queue into tx_active_queue. There by we need
++	 * to spinlock to only perform the copy the rest of the code ie to
++	 * construct the tx_pend_queue and the code to process tx_active_queue
++	 * can be lockless. The concept is borrowed as is from RX processing
++	 */
++	/* struct sk_buff_head		tx_active_queue  ____cacheline_aligned; */
++
++	/* Control TXP in runtime, enable by default */
++	atomic_t                lb_txp_active;
++
++	/*
++	 * When the NET_TX tries to send a TX packet put it into tx_pend_queue
++	 * For now, the processing tasklet will also direcly operate on this
++	 * queue
++	 */
++	struct sk_buff_head	tx_pend_queue  ____cacheline_aligned;
++
++	/* cpu on which the DHD Tx is happenning */
++	atomic_t		tx_cpu;
++
++	/* CPU on which the Network stack is calling the DHD's xmit function */
++	atomic_t		net_tx_cpu;
++
++	/* Tasklet context from which the DHD's TX processing happens */
++	struct tasklet_struct tx_tasklet;
++
++	/*
++	 * Consumer Histogram - NAPI RX Packet processing
++	 * -----------------------------------------------
++	 * On Each CPU, when the NAPI RX Packet processing call back was invoked
++	 * how many packets were processed is captured in this data structure.
++	 * Now its difficult to capture the "exact" number of packets processed.
++	 * So considering the packet counter to be a 32 bit one, we have a
++	 * bucket with 8 bins (2^1, 2^2 ... 2^8). The "number" of packets
++	 * processed is rounded off to the next power of 2 and put in the
++	 * approriate "bin" the value in the bin gets incremented.
++	 * For example, assume that in CPU 1 if NAPI Rx runs 3 times
++	 * and the packet count processed is as follows (assume the bin counters are 0)
++	 * iteration 1 - 10 (the bin counter 2^4 increments to 1)
++	 * iteration 2 - 30 (the bin counter 2^5 increments to 1)
++	 * iteration 3 - 15 (the bin counter 2^4 increments by 1 to become 2)
++	 */
++	uint32 *napi_rx_hist[HIST_BIN_SIZE];
++	uint32 *txc_hist[HIST_BIN_SIZE];
++	uint32 *rxc_hist[HIST_BIN_SIZE];
++#endif /* DHD_LB */
++
++#ifdef SHOW_LOGTRACE
++	struct work_struct	  event_log_dispatcher_work;
++#endif /* SHOW_LOGTRACE */
++
++#if defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW)
++#endif /* defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW) */
++	struct kobject dhd_kobj;
++#ifdef SHOW_LOGTRACE
++	struct sk_buff_head   evt_trace_queue     ____cacheline_aligned;
++#endif
++	timer_list_compat_t timesync_timer;
++#if defined(BT_OVER_SDIO)
++	char btfw_path[PATH_MAX];
++#endif /* defined (BT_OVER_SDIO) */
++
++#ifdef WL_MONITOR
++	struct net_device *monitor_dev; /* monitor pseudo device */
++	struct sk_buff *monitor_skb;
++	uint	monitor_len;
++	uint monitor_type;   /* monitor pseudo device */
++	monitor_info_t *monitor_info;
++#endif /* WL_MONITOR */
++	uint32 shub_enable;
++#if defined(BT_OVER_SDIO)
++	struct mutex bus_user_lock; /* lock for sdio bus apis shared between WLAN & BT */
++	int	bus_user_count; /* User counts of sdio bus shared between WLAN & BT */
++#endif /* BT_OVER_SDIO */
++#ifdef DHD_DEBUG_UART
++	bool duart_execute;
++#endif
++#ifdef PCIE_INB_DW
++	wait_queue_head_t ds_exit_wait;
++#endif /* PCIE_INB_DW */
++} dhd_info_t;
++
++#ifdef WL_MONITOR
++#define MONPKT_EXTRA_LEN	48
++#endif
++
++#define DHDIF_FWDER(dhdif)      FALSE
++
++#if defined(BT_OVER_SDIO)
++/* Flag to indicate if driver is initialized */
++uint dhd_driver_init_done = TRUE;
++#else
++/* Flag to indicate if driver is initialized */
++uint dhd_driver_init_done = FALSE;
++#endif
++/* Flag to indicate if we should download firmware on driver load */
++uint dhd_download_fw_on_driverload = TRUE;
++
++/* Definitions to provide path to the firmware and nvram
++ * example nvram_path[MOD_PARAM_PATHLEN]="/projects/wlan/nvram.txt"
++ */
++char firmware_path[MOD_PARAM_PATHLEN];
++char nvram_path[MOD_PARAM_PATHLEN];
++char clm_path[MOD_PARAM_PATHLEN];
++char config_path[MOD_PARAM_PATHLEN];
++#ifdef DHD_UCODE_DOWNLOAD
++char ucode_path[MOD_PARAM_PATHLEN];
++#endif /* DHD_UCODE_DOWNLOAD */
++
++module_param_string(clm_path, clm_path, MOD_PARAM_PATHLEN, 0660);
++
++
++/* backup buffer for firmware and nvram path */
++char fw_bak_path[MOD_PARAM_PATHLEN];
++char nv_bak_path[MOD_PARAM_PATHLEN];
++
++/* information string to keep firmware, chio, cheip version info visiable from log */
++char info_string[MOD_PARAM_INFOLEN];
++module_param_string(info_string, info_string, MOD_PARAM_INFOLEN, 0444);
++int op_mode = 0;
++int disable_proptx = 0;
++module_param(op_mode, int, 0644);
++extern int wl_control_wl_start(struct net_device *dev);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && (defined(BCMLXSDMMC) || defined(BCMDBUS))
++struct semaphore dhd_registration_sem;
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
++
++/* deferred handlers */
++static void dhd_ifadd_event_handler(void *handle, void *event_info, u8 event);
++static void dhd_ifdel_event_handler(void *handle, void *event_info, u8 event);
++static void dhd_set_mac_addr_handler(void *handle, void *event_info, u8 event);
++static void dhd_set_mcast_list_handler(void *handle, void *event_info, u8 event);
++
++#ifdef DHD_UPDATE_INTF_MAC
++static void dhd_ifupdate_event_handler(void *handle, void *event_info, u8 event);
++#endif /* DHD_UPDATE_INTF_MAC */
++#if defined(CONFIG_IPV6) && defined(IPV6_NDO_SUPPORT)
++static void dhd_inet6_work_handler(void *dhd_info, void *event_data, u8 event);
++#endif /* CONFIG_IPV6 && IPV6_NDO_SUPPORT */
++#ifdef WL_CFG80211
++extern void dhd_netdev_free(struct net_device *ndev);
++#endif /* WL_CFG80211 */
++
++#if (defined(DHD_WET) || defined(DHD_MCAST_REGEN) || defined(DHD_L2_FILTER))
++/* update rx_pkt_chainable state of dhd interface */
++static void dhd_update_rx_pkt_chainable_state(dhd_pub_t* dhdp, uint32 idx);
++#endif /* DHD_WET || DHD_MCAST_REGEN || DHD_L2_FILTER */
++
++#ifdef HOFFLOAD_MODULES
++char dhd_hmem_module_string[MOD_PARAM_SRLEN];
++module_param_string(dhd_hmem_module_string, dhd_hmem_module_string, MOD_PARAM_SRLEN, 0660);
++#endif
++/* Error bits */
++module_param(dhd_msg_level, int, 0);
++#if defined(WL_WIRELESS_EXT)
++module_param(iw_msg_level, int, 0);
++#endif
++#ifdef WL_CFG80211
++module_param(wl_dbg_level, int, 0);
++#endif
++module_param(android_msg_level, int, 0);
++module_param(config_msg_level, int, 0);
++
++#ifdef ARP_OFFLOAD_SUPPORT
++/* ARP offload enable */
++uint dhd_arp_enable = TRUE;
++module_param(dhd_arp_enable, uint, 0);
++
++/* ARP offload agent mode : Enable ARP Host Auto-Reply and ARP Peer Auto-Reply */
++
++#ifdef ENABLE_ARP_SNOOP_MODE
++uint dhd_arp_mode = ARP_OL_AGENT | ARP_OL_PEER_AUTO_REPLY | ARP_OL_SNOOP | ARP_OL_HOST_AUTO_REPLY;
++#else
++uint dhd_arp_mode = ARP_OL_AGENT | ARP_OL_PEER_AUTO_REPLY;
++#endif /* ENABLE_ARP_SNOOP_MODE */
++
++module_param(dhd_arp_mode, uint, 0);
++#endif /* ARP_OFFLOAD_SUPPORT */
++
++/* Disable Prop tx */
++module_param(disable_proptx, int, 0644);
++/* load firmware and/or nvram values from the filesystem */
++module_param_string(firmware_path, firmware_path, MOD_PARAM_PATHLEN, 0660);
++module_param_string(nvram_path, nvram_path, MOD_PARAM_PATHLEN, 0660);
++module_param_string(config_path, config_path, MOD_PARAM_PATHLEN, 0);
++#ifdef DHD_UCODE_DOWNLOAD
++module_param_string(ucode_path, ucode_path, MOD_PARAM_PATHLEN, 0660);
++#endif /* DHD_UCODE_DOWNLOAD */
++
++/* Watchdog interval */
++
++/* extend watchdog expiration to 2 seconds when DPC is running */
++#define WATCHDOG_EXTEND_INTERVAL (2000)
++
++uint dhd_watchdog_ms = CUSTOM_DHD_WATCHDOG_MS;
++module_param(dhd_watchdog_ms, uint, 0);
++
++#ifdef DHD_PCIE_RUNTIMEPM
++uint dhd_runtimepm_ms = CUSTOM_DHD_RUNTIME_MS;
++#endif /* DHD_PCIE_RUNTIMEPMT */
++#if defined(DHD_DEBUG)
++/* Console poll interval */
++uint dhd_console_ms = 0;
++module_param(dhd_console_ms, uint, 0644);
++#else
++uint dhd_console_ms = 0;
++#endif /* DHD_DEBUG */
++
++uint dhd_slpauto = TRUE;
++module_param(dhd_slpauto, uint, 0);
++
++#ifdef PKT_FILTER_SUPPORT
++/* Global Pkt filter enable control */
++uint dhd_pkt_filter_enable = TRUE;
++module_param(dhd_pkt_filter_enable, uint, 0);
++#endif
++
++/* Pkt filter init setup */
++uint dhd_pkt_filter_init = 0;
++module_param(dhd_pkt_filter_init, uint, 0);
++
++/* Pkt filter mode control */
++#ifdef GAN_LITE_NAT_KEEPALIVE_FILTER
++uint dhd_master_mode = FALSE;
++#else
++uint dhd_master_mode = FALSE;
++#endif /* GAN_LITE_NAT_KEEPALIVE_FILTER */
++module_param(dhd_master_mode, uint, 0);
++
++int dhd_watchdog_prio = 0;
++module_param(dhd_watchdog_prio, int, 0);
++
++/* DPC thread priority */
++int dhd_dpc_prio = CUSTOM_DPC_PRIO_SETTING;
++module_param(dhd_dpc_prio, int, 0);
++
++/* RX frame thread priority */
++int dhd_rxf_prio = CUSTOM_RXF_PRIO_SETTING;
++module_param(dhd_rxf_prio, int, 0);
++
++#if !defined(BCMDBUS)
++extern int dhd_dongle_ramsize;
++module_param(dhd_dongle_ramsize, int, 0);
++#endif /* !BCMDBUS */
++
++#ifdef WL_CFG80211
++int passive_channel_skip = 0;
++module_param(passive_channel_skip, int, (S_IRUSR|S_IWUSR));
++#endif /* WL_CFG80211 */
++
++/* Keep track of number of instances */
++static int dhd_found = 0;
++static int instance_base = 0; /* Starting instance number */
++module_param(instance_base, int, 0644);
++
++#if defined(DHD_LB_RXP) && defined(PCIE_FULL_DONGLE)
++static int dhd_napi_weight = 32;
++module_param(dhd_napi_weight, int, 0644);
++#endif /* DHD_LB_RXP && PCIE_FULL_DONGLE */
++
++#ifdef PCIE_FULL_DONGLE
++extern int h2d_max_txpost;
++module_param(h2d_max_txpost, int, 0644);
++#endif /* PCIE_FULL_DONGLE */
++
++#ifdef DHD_ARP_DUMP
++#include <linux/if_arp.h>
++static const char arp_types[][10] = {
++	"NA", "REQUEST", "RESPONSE"
++};
++static void dhd_arp_dump(char *ifname, uint8 *pktdata, bool tx);
++#endif /* DHD_ARP_DUMP */
++
++#ifdef DHD_DHCP_DUMP
++struct bootp_fmt {
++	struct iphdr ip_header;
++	struct udphdr udp_header;
++	uint8 op;
++	uint8 htype;
++	uint8 hlen;
++	uint8 hops;
++	uint32 transaction_id;
++	uint16 secs;
++	uint16 flags;
++	uint32 client_ip;
++	uint32 assigned_ip;
++	uint32 server_ip;
++	uint32 relay_ip;
++	uint8 hw_address[16];
++	uint8 server_name[64];
++	uint8 file_name[128];
++	uint8 options[312];
++};
++
++static const uint8 bootp_magic_cookie[4] = { 99, 130, 83, 99 };
++static const char dhcp_ops[][10] = {
++	"NA", "REQUEST", "REPLY"
++};
++static const char dhcp_types[][10] = {
++	"NA", "DISCOVER", "OFFER", "REQUEST", "DECLINE", "ACK", "NAK", "RELEASE", "INFORM"
++};
++static void dhd_dhcp_dump(char *ifname, uint8 *pktdata, bool tx);
++#endif /* DHD_DHCP_DUMP */
++
++#ifdef DHD_ICMP_DUMP
++#include <net/icmp.h>
++static void dhd_icmp_dump(char *ifname, uint8 *pktdata, bool tx);
++#endif /* DHD_ICMP_DUMP */
++
++/* Functions to manage sysfs interface for dhd */
++static int dhd_sysfs_init(dhd_info_t *dhd);
++static void dhd_sysfs_exit(dhd_info_t *dhd);
++
++#ifdef SHOW_LOGTRACE
++#if defined(CUSTOMER_HW4_DEBUG)
++static char *logstrs_path = PLATFORM_PATH"logstrs.bin";
++static char *st_str_file_path = PLATFORM_PATH"rtecdc.bin";
++static char *map_file_path = PLATFORM_PATH"rtecdc.map";
++static char *rom_st_str_file_path = PLATFORM_PATH"roml.bin";
++static char *rom_map_file_path = PLATFORM_PATH"roml.map";
++#elif defined(CUSTOMER_HW2)
++static char *logstrs_path = "/data/misc/wifi/logstrs.bin";
++static char *st_str_file_path = "/data/misc/wifi/rtecdc.bin";
++static char *map_file_path = "/data/misc/wifi/rtecdc.map";
++static char *rom_st_str_file_path = "/data/misc/wifi/roml.bin";
++static char *rom_map_file_path = "/data/misc/wifi/roml.map";
++#else
++static char *logstrs_path = "/installmedia/logstrs.bin";
++static char *st_str_file_path = "/installmedia/rtecdc.bin";
++static char *map_file_path = "/installmedia/rtecdc.map";
++static char *rom_st_str_file_path = "/installmedia/roml.bin";
++static char *rom_map_file_path = "/installmedia/roml.map";
++#endif /* CUSTOMER_HW4_DEBUG || CUSTOMER_HW2 */
++static char *ram_file_str = "rtecdc";
++static char *rom_file_str = "roml";
++
++module_param(logstrs_path, charp, S_IRUGO);
++module_param(st_str_file_path, charp, S_IRUGO);
++module_param(map_file_path, charp, S_IRUGO);
++module_param(rom_st_str_file_path, charp, S_IRUGO);
++module_param(rom_map_file_path, charp, S_IRUGO);
++
++static int dhd_init_logstrs_array(osl_t *osh, dhd_event_log_t *temp);
++static int dhd_read_map(osl_t *osh, char *fname, uint32 *ramstart, uint32 *rodata_start,
++	uint32 *rodata_end);
++static int dhd_init_static_strs_array(osl_t *osh, dhd_event_log_t *temp, char *str_file,
++	char *map_file);
++#endif /* SHOW_LOGTRACE */
++
++#if defined(DHD_LB)
++
++static void
++dhd_lb_set_default_cpus(dhd_info_t *dhd)
++{
++	/* Default CPU allocation for the jobs */
++	atomic_set(&dhd->rx_napi_cpu, 1);
++	atomic_set(&dhd->rx_compl_cpu, 2);
++	atomic_set(&dhd->tx_compl_cpu, 2);
++	atomic_set(&dhd->tx_cpu, 2);
++	atomic_set(&dhd->net_tx_cpu, 0);
++}
++
++static void
++dhd_cpumasks_deinit(dhd_info_t *dhd)
++{
++	free_cpumask_var(dhd->cpumask_curr_avail);
++	free_cpumask_var(dhd->cpumask_primary);
++	free_cpumask_var(dhd->cpumask_primary_new);
++	free_cpumask_var(dhd->cpumask_secondary);
++	free_cpumask_var(dhd->cpumask_secondary_new);
++}
++
++static int
++dhd_cpumasks_init(dhd_info_t *dhd)
++{
++	int id;
++	uint32 cpus, num_cpus = num_possible_cpus();
++	int ret = 0;
++
++	DHD_ERROR(("%s CPU masks primary(big)=0x%x secondary(little)=0x%x\n", __FUNCTION__,
++		DHD_LB_PRIMARY_CPUS, DHD_LB_SECONDARY_CPUS));
++
++	if (!alloc_cpumask_var(&dhd->cpumask_curr_avail, GFP_KERNEL) ||
++	    !alloc_cpumask_var(&dhd->cpumask_primary, GFP_KERNEL) ||
++	    !alloc_cpumask_var(&dhd->cpumask_primary_new, GFP_KERNEL) ||
++	    !alloc_cpumask_var(&dhd->cpumask_secondary, GFP_KERNEL) ||
++	    !alloc_cpumask_var(&dhd->cpumask_secondary_new, GFP_KERNEL)) {
++		DHD_ERROR(("%s Failed to init cpumasks\n", __FUNCTION__));
++		ret = -ENOMEM;
++		goto fail;
++	}
++
++	cpumask_copy(dhd->cpumask_curr_avail, cpu_online_mask);
++	cpumask_clear(dhd->cpumask_primary);
++	cpumask_clear(dhd->cpumask_secondary);
++
++	if (num_cpus > 32) {
++		DHD_ERROR(("%s max cpus must be 32, %d too big\n", __FUNCTION__, num_cpus));
++		ASSERT(0);
++	}
++
++	cpus = DHD_LB_PRIMARY_CPUS;
++	for (id = 0; id < num_cpus; id++) {
++		if (isset(&cpus, id))
++			cpumask_set_cpu(id, dhd->cpumask_primary);
++	}
++
++	cpus = DHD_LB_SECONDARY_CPUS;
++	for (id = 0; id < num_cpus; id++) {
++		if (isset(&cpus, id))
++			cpumask_set_cpu(id, dhd->cpumask_secondary);
++	}
++
++	return ret;
++fail:
++	dhd_cpumasks_deinit(dhd);
++	return ret;
++}
++
++/*
++ * The CPU Candidacy Algorithm
++ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ * The available CPUs for selection are divided into two groups
++ *  Primary Set - A CPU mask that carries the First Choice CPUs
++ *  Secondary Set - A CPU mask that carries the Second Choice CPUs.
++ *
++ * There are two types of Job, that needs to be assigned to
++ * the CPUs, from one of the above mentioned CPU group. The Jobs are
++ * 1) Rx Packet Processing - napi_cpu
++ * 2) Completion Processiong (Tx, RX) - compl_cpu
++ *
++ * To begin with both napi_cpu and compl_cpu are on CPU0. Whenever a CPU goes
++ * on-line/off-line the CPU candidacy algorithm is triggerd. The candidacy
++ * algo tries to pickup the first available non boot CPU (CPU0) for napi_cpu.
++ * If there are more processors free, it assigns one to compl_cpu.
++ * It also tries to ensure that both napi_cpu and compl_cpu are not on the same
++ * CPU, as much as possible.
++ *
++ * By design, both Tx and Rx completion jobs are run on the same CPU core, as it
++ * would allow Tx completion skb's to be released into a local free pool from
++ * which the rx buffer posts could have been serviced. it is important to note
++ * that a Tx packet may not have a large enough buffer for rx posting.
++ */
++void dhd_select_cpu_candidacy(dhd_info_t *dhd)
++{
++	uint32 primary_available_cpus; /* count of primary available cpus */
++	uint32 secondary_available_cpus; /* count of secondary available cpus */
++	uint32 napi_cpu = 0; /* cpu selected for napi rx processing */
++	uint32 compl_cpu = 0; /* cpu selected for completion jobs */
++	uint32 tx_cpu = 0; /* cpu selected for tx processing job */
++
++	cpumask_clear(dhd->cpumask_primary_new);
++	cpumask_clear(dhd->cpumask_secondary_new);
++
++	/*
++	 * Now select from the primary mask. Even if a Job is
++	 * already running on a CPU in secondary group, we still move
++	 * to primary CPU. So no conditional checks.
++	 */
++	cpumask_and(dhd->cpumask_primary_new, dhd->cpumask_primary,
++		dhd->cpumask_curr_avail);
++
++	cpumask_and(dhd->cpumask_secondary_new, dhd->cpumask_secondary,
++		dhd->cpumask_curr_avail);
++
++	primary_available_cpus = cpumask_weight(dhd->cpumask_primary_new);
++
++	if (primary_available_cpus > 0) {
++		napi_cpu = cpumask_first(dhd->cpumask_primary_new);
++
++		/* If no further CPU is available,
++		 * cpumask_next returns >= nr_cpu_ids
++		 */
++		tx_cpu = cpumask_next(napi_cpu, dhd->cpumask_primary_new);
++		if (tx_cpu >= nr_cpu_ids)
++			tx_cpu = 0;
++
++		/* In case there are no more CPUs, do completions & Tx in same CPU */
++		compl_cpu = cpumask_next(tx_cpu, dhd->cpumask_primary_new);
++		if (compl_cpu >= nr_cpu_ids)
++			compl_cpu = tx_cpu;
++	}
++
++	DHD_INFO(("%s After primary CPU check napi_cpu %d compl_cpu %d tx_cpu %d\n",
++		__FUNCTION__, napi_cpu, compl_cpu, tx_cpu));
++
++	/* -- Now check for the CPUs from the secondary mask -- */
++	secondary_available_cpus = cpumask_weight(dhd->cpumask_secondary_new);
++
++	DHD_INFO(("%s Available secondary cpus %d nr_cpu_ids %d\n",
++		__FUNCTION__, secondary_available_cpus, nr_cpu_ids));
++
++	if (secondary_available_cpus > 0) {
++		/* At this point if napi_cpu is unassigned it means no CPU
++		 * is online from Primary Group
++		 */
++		if (napi_cpu == 0) {
++			napi_cpu = cpumask_first(dhd->cpumask_secondary_new);
++			tx_cpu = cpumask_next(napi_cpu, dhd->cpumask_secondary_new);
++			compl_cpu = cpumask_next(tx_cpu, dhd->cpumask_secondary_new);
++		} else if (tx_cpu == 0) {
++			tx_cpu = cpumask_first(dhd->cpumask_secondary_new);
++			compl_cpu = cpumask_next(tx_cpu, dhd->cpumask_secondary_new);
++		} else if (compl_cpu == 0) {
++			compl_cpu = cpumask_first(dhd->cpumask_secondary_new);
++		}
++
++		/* If no CPU was available for tx processing, choose CPU 0 */
++		if (tx_cpu >= nr_cpu_ids)
++			tx_cpu = 0;
++
++		/* If no CPU was available for completion, choose CPU 0 */
++		if (compl_cpu >= nr_cpu_ids)
++			compl_cpu = 0;
++	}
++	if ((primary_available_cpus == 0) &&
++		(secondary_available_cpus == 0)) {
++		/* No CPUs available from primary or secondary mask */
++		napi_cpu = 1;
++		compl_cpu = 0;
++		tx_cpu = 2;
++	}
++
++	DHD_INFO(("%s After secondary CPU check napi_cpu %d compl_cpu %d tx_cpu %d\n",
++		__FUNCTION__, napi_cpu, compl_cpu, tx_cpu));
++
++	ASSERT(napi_cpu < nr_cpu_ids);
++	ASSERT(compl_cpu < nr_cpu_ids);
++	ASSERT(tx_cpu < nr_cpu_ids);
++
++	atomic_set(&dhd->rx_napi_cpu, napi_cpu);
++	atomic_set(&dhd->tx_compl_cpu, compl_cpu);
++	atomic_set(&dhd->rx_compl_cpu, compl_cpu);
++	atomic_set(&dhd->tx_cpu, tx_cpu);
++
++	return;
++}
++
++/*
++ * Function to handle CPU Hotplug notifications.
++ * One of the task it does is to trigger the CPU Candidacy algorithm
++ * for load balancing.
++ */
++int
++dhd_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
++{
++	unsigned long int cpu = (unsigned long int)hcpu;
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	dhd_info_t *dhd = container_of(nfb, dhd_info_t, cpu_notifier);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++	if (!dhd || !(dhd->dhd_state & DHD_ATTACH_STATE_LB_ATTACH_DONE)) {
++		DHD_INFO(("%s(): LB data is not initialized yet.\n",
++			__FUNCTION__));
++		return NOTIFY_BAD;
++	}
++
++	switch (action)
++	{
++		case CPU_ONLINE:
++		case CPU_ONLINE_FROZEN:
++			DHD_LB_STATS_INCR(dhd->cpu_online_cnt[cpu]);
++			cpumask_set_cpu(cpu, dhd->cpumask_curr_avail);
++			dhd_select_cpu_candidacy(dhd);
++			break;
++
++		case CPU_DOWN_PREPARE:
++		case CPU_DOWN_PREPARE_FROZEN:
++			DHD_LB_STATS_INCR(dhd->cpu_offline_cnt[cpu]);
++			cpumask_clear_cpu(cpu, dhd->cpumask_curr_avail);
++			dhd_select_cpu_candidacy(dhd);
++			break;
++		default:
++			break;
++	}
++
++	return NOTIFY_OK;
++}
++
++#if defined(DHD_LB_STATS)
++void dhd_lb_stats_init(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd;
++	int i, j, num_cpus = num_possible_cpus();
++	int alloc_size = sizeof(uint32) * num_cpus;
++
++	if (dhdp == NULL) {
++		DHD_ERROR(("%s(): Invalid argument dhd pubb pointer is NULL \n",
++			__FUNCTION__));
++		return;
++	}
++
++	dhd = dhdp->info;
++	if (dhd == NULL) {
++		DHD_ERROR(("%s(): DHD pointer is NULL \n", __FUNCTION__));
++		return;
++	}
++
++	DHD_LB_STATS_CLR(dhd->dhd_dpc_cnt);
++	DHD_LB_STATS_CLR(dhd->napi_sched_cnt);
++
++	dhd->napi_percpu_run_cnt = (uint32 *)MALLOC(dhdp->osh, alloc_size);
++	if (!dhd->napi_percpu_run_cnt) {
++		DHD_ERROR(("%s(): napi_percpu_run_cnt malloc failed \n",
++			__FUNCTION__));
++		return;
++	}
++	for (i = 0; i < num_cpus; i++)
++		DHD_LB_STATS_CLR(dhd->napi_percpu_run_cnt[i]);
++
++	DHD_LB_STATS_CLR(dhd->rxc_sched_cnt);
++
++	dhd->rxc_percpu_run_cnt = (uint32 *)MALLOC(dhdp->osh, alloc_size);
++	if (!dhd->rxc_percpu_run_cnt) {
++		DHD_ERROR(("%s(): rxc_percpu_run_cnt malloc failed \n",
++			__FUNCTION__));
++		return;
++	}
++	for (i = 0; i < num_cpus; i++)
++		DHD_LB_STATS_CLR(dhd->rxc_percpu_run_cnt[i]);
++
++	DHD_LB_STATS_CLR(dhd->txc_sched_cnt);
++
++	dhd->txc_percpu_run_cnt = (uint32 *)MALLOC(dhdp->osh, alloc_size);
++	if (!dhd->txc_percpu_run_cnt) {
++		DHD_ERROR(("%s(): txc_percpu_run_cnt malloc failed \n",
++			__FUNCTION__));
++		return;
++	}
++	for (i = 0; i < num_cpus; i++)
++		DHD_LB_STATS_CLR(dhd->txc_percpu_run_cnt[i]);
++
++	dhd->cpu_online_cnt = (uint32 *)MALLOC(dhdp->osh, alloc_size);
++	if (!dhd->cpu_online_cnt) {
++		DHD_ERROR(("%s(): cpu_online_cnt malloc failed \n",
++			__FUNCTION__));
++		return;
++	}
++	for (i = 0; i < num_cpus; i++)
++		DHD_LB_STATS_CLR(dhd->cpu_online_cnt[i]);
++
++	dhd->cpu_offline_cnt = (uint32 *)MALLOC(dhdp->osh, alloc_size);
++	if (!dhd->cpu_offline_cnt) {
++		DHD_ERROR(("%s(): cpu_offline_cnt malloc failed \n",
++			__FUNCTION__));
++		return;
++	}
++	for (i = 0; i < num_cpus; i++)
++		DHD_LB_STATS_CLR(dhd->cpu_offline_cnt[i]);
++
++	dhd->txp_percpu_run_cnt = (uint32 *)MALLOC(dhdp->osh, alloc_size);
++	if (!dhd->txp_percpu_run_cnt) {
++		DHD_ERROR(("%s(): txp_percpu_run_cnt malloc failed \n",
++			__FUNCTION__));
++		return;
++	}
++	for (i = 0; i < num_cpus; i++)
++		DHD_LB_STATS_CLR(dhd->txp_percpu_run_cnt[i]);
++
++	dhd->tx_start_percpu_run_cnt = (uint32 *)MALLOC(dhdp->osh, alloc_size);
++	if (!dhd->tx_start_percpu_run_cnt) {
++		DHD_ERROR(("%s(): tx_start_percpu_run_cnt malloc failed \n",
++			__FUNCTION__));
++		return;
++	}
++	for (i = 0; i < num_cpus; i++)
++		DHD_LB_STATS_CLR(dhd->tx_start_percpu_run_cnt[i]);
++
++	for (j = 0; j < HIST_BIN_SIZE; j++) {
++		dhd->napi_rx_hist[j] = (uint32 *)MALLOC(dhdp->osh, alloc_size);
++		if (!dhd->napi_rx_hist[j]) {
++			DHD_ERROR(("%s(): dhd->napi_rx_hist[%d] malloc failed \n",
++				__FUNCTION__, j));
++			return;
++		}
++		for (i = 0; i < num_cpus; i++) {
++			DHD_LB_STATS_CLR(dhd->napi_rx_hist[j][i]);
++		}
++	}
++#ifdef DHD_LB_TXC
++	for (j = 0; j < HIST_BIN_SIZE; j++) {
++		dhd->txc_hist[j] = (uint32 *)MALLOC(dhdp->osh, alloc_size);
++		if (!dhd->txc_hist[j]) {
++			DHD_ERROR(("%s(): dhd->txc_hist[%d] malloc failed \n",
++			         __FUNCTION__, j));
++			return;
++		}
++		for (i = 0; i < num_cpus; i++) {
++			DHD_LB_STATS_CLR(dhd->txc_hist[j][i]);
++		}
++	}
++#endif /* DHD_LB_TXC */
++#ifdef DHD_LB_RXC
++	for (j = 0; j < HIST_BIN_SIZE; j++) {
++		dhd->rxc_hist[j] = (uint32 *)MALLOC(dhdp->osh, alloc_size);
++		if (!dhd->rxc_hist[j]) {
++			DHD_ERROR(("%s(): dhd->rxc_hist[%d] malloc failed \n",
++				__FUNCTION__, j));
++			return;
++		}
++		for (i = 0; i < num_cpus; i++) {
++			DHD_LB_STATS_CLR(dhd->rxc_hist[j][i]);
++		}
++	}
++#endif /* DHD_LB_RXC */
++	return;
++}
++
++void dhd_lb_stats_deinit(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd;
++	int j, num_cpus = num_possible_cpus();
++	int alloc_size = sizeof(uint32) * num_cpus;
++
++	if (dhdp == NULL) {
++		DHD_ERROR(("%s(): Invalid argument dhd pubb pointer is NULL \n",
++			__FUNCTION__));
++		return;
++	}
++
++	dhd = dhdp->info;
++	if (dhd == NULL) {
++		DHD_ERROR(("%s(): DHD pointer is NULL \n", __FUNCTION__));
++		return;
++	}
++
++	if (dhd->napi_percpu_run_cnt) {
++		MFREE(dhdp->osh, dhd->napi_percpu_run_cnt, alloc_size);
++		dhd->napi_percpu_run_cnt = NULL;
++	}
++	if (dhd->rxc_percpu_run_cnt) {
++		MFREE(dhdp->osh, dhd->rxc_percpu_run_cnt, alloc_size);
++		dhd->rxc_percpu_run_cnt = NULL;
++	}
++	if (dhd->txc_percpu_run_cnt) {
++		MFREE(dhdp->osh, dhd->txc_percpu_run_cnt, alloc_size);
++		dhd->txc_percpu_run_cnt = NULL;
++	}
++	if (dhd->cpu_online_cnt) {
++		MFREE(dhdp->osh, dhd->cpu_online_cnt, alloc_size);
++		dhd->cpu_online_cnt = NULL;
++	}
++	if (dhd->cpu_offline_cnt) {
++		MFREE(dhdp->osh, dhd->cpu_offline_cnt, alloc_size);
++		dhd->cpu_offline_cnt = NULL;
++	}
++
++	if (dhd->txp_percpu_run_cnt) {
++		MFREE(dhdp->osh, dhd->txp_percpu_run_cnt, alloc_size);
++		dhd->txp_percpu_run_cnt = NULL;
++	}
++	if (dhd->tx_start_percpu_run_cnt) {
++		MFREE(dhdp->osh, dhd->tx_start_percpu_run_cnt, alloc_size);
++		dhd->tx_start_percpu_run_cnt = NULL;
++	}
++
++	for (j = 0; j < HIST_BIN_SIZE; j++) {
++		if (dhd->napi_rx_hist[j]) {
++			MFREE(dhdp->osh, dhd->napi_rx_hist[j], alloc_size);
++			dhd->napi_rx_hist[j] = NULL;
++		}
++#ifdef DHD_LB_TXC
++		if (dhd->txc_hist[j]) {
++			MFREE(dhdp->osh, dhd->txc_hist[j], alloc_size);
++			dhd->txc_hist[j] = NULL;
++		}
++#endif /* DHD_LB_TXC */
++#ifdef DHD_LB_RXC
++		if (dhd->rxc_hist[j]) {
++			MFREE(dhdp->osh, dhd->rxc_hist[j], alloc_size);
++			dhd->rxc_hist[j] = NULL;
++		}
++#endif /* DHD_LB_RXC */
++	}
++
++	return;
++}
++
++static void dhd_lb_stats_dump_histo(
++	struct bcmstrbuf *strbuf, uint32 **hist)
++{
++	int i, j;
++	uint32 *per_cpu_total;
++	uint32 total = 0;
++	uint32 num_cpus = num_possible_cpus();
++
++	per_cpu_total = (uint32 *)kmalloc(sizeof(uint32) * num_cpus, GFP_ATOMIC);
++	if (!per_cpu_total) {
++		DHD_ERROR(("%s(): dhd->per_cpu_total malloc failed \n", __FUNCTION__));
++		return;
++	}
++	bzero(per_cpu_total, sizeof(uint32) * num_cpus);
++
++	bcm_bprintf(strbuf, "CPU: \t\t");
++	for (i = 0; i < num_cpus; i++)
++		bcm_bprintf(strbuf, "%d\t", i);
++	bcm_bprintf(strbuf, "\nBin\n");
++
++	for (i = 0; i < HIST_BIN_SIZE; i++) {
++		bcm_bprintf(strbuf, "%d:\t\t", 1<<i);
++		for (j = 0; j < num_cpus; j++) {
++			bcm_bprintf(strbuf, "%d\t", hist[i][j]);
++		}
++		bcm_bprintf(strbuf, "\n");
++	}
++	bcm_bprintf(strbuf, "Per CPU Total \t");
++	total = 0;
++	for (i = 0; i < num_cpus; i++) {
++		for (j = 0; j < HIST_BIN_SIZE; j++) {
++			per_cpu_total[i] += (hist[j][i] * (1<<j));
++		}
++		bcm_bprintf(strbuf, "%d\t", per_cpu_total[i]);
++		total += per_cpu_total[i];
++	}
++	bcm_bprintf(strbuf, "\nTotal\t\t%d \n", total);
++
++	kfree(per_cpu_total);
++	return;
++}
++
++static inline void dhd_lb_stats_dump_cpu_array(struct bcmstrbuf *strbuf, uint32 *p)
++{
++	int i, num_cpus = num_possible_cpus();
++
++	bcm_bprintf(strbuf, "CPU: \t");
++	for (i = 0; i < num_cpus; i++)
++		bcm_bprintf(strbuf, "%d\t", i);
++	bcm_bprintf(strbuf, "\n");
++
++	bcm_bprintf(strbuf, "Val: \t");
++	for (i = 0; i < num_cpus; i++)
++		bcm_bprintf(strbuf, "%u\t", *(p+i));
++	bcm_bprintf(strbuf, "\n");
++	return;
++}
++
++void dhd_lb_stats_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
++{
++	dhd_info_t *dhd;
++
++	if (dhdp == NULL || strbuf == NULL) {
++		DHD_ERROR(("%s(): Invalid argument dhdp %p strbuf %p \n",
++			__FUNCTION__, dhdp, strbuf));
++		return;
++	}
++
++	dhd = dhdp->info;
++	if (dhd == NULL) {
++		DHD_ERROR(("%s(): DHD pointer is NULL \n", __FUNCTION__));
++		return;
++	}
++
++	bcm_bprintf(strbuf, "\ncpu_online_cnt:\n");
++	dhd_lb_stats_dump_cpu_array(strbuf, dhd->cpu_online_cnt);
++
++	bcm_bprintf(strbuf, "\ncpu_offline_cnt:\n");
++	dhd_lb_stats_dump_cpu_array(strbuf, dhd->cpu_offline_cnt);
++
++	bcm_bprintf(strbuf, "\nsched_cnt: dhd_dpc %u napi %u rxc %u txc %u\n",
++		dhd->dhd_dpc_cnt, dhd->napi_sched_cnt, dhd->rxc_sched_cnt,
++		dhd->txc_sched_cnt);
++
++#ifdef DHD_LB_RXP
++	bcm_bprintf(strbuf, "\nnapi_percpu_run_cnt:\n");
++	dhd_lb_stats_dump_cpu_array(strbuf, dhd->napi_percpu_run_cnt);
++	bcm_bprintf(strbuf, "\nNAPI Packets Received Histogram:\n");
++	dhd_lb_stats_dump_histo(strbuf, dhd->napi_rx_hist);
++#endif /* DHD_LB_RXP */
++
++#ifdef DHD_LB_RXC
++	bcm_bprintf(strbuf, "\nrxc_percpu_run_cnt:\n");
++	dhd_lb_stats_dump_cpu_array(strbuf, dhd->rxc_percpu_run_cnt);
++	bcm_bprintf(strbuf, "\nRX Completions (Buffer Post) Histogram:\n");
++	dhd_lb_stats_dump_histo(strbuf, dhd->rxc_hist);
++#endif /* DHD_LB_RXC */
++
++#ifdef DHD_LB_TXC
++	bcm_bprintf(strbuf, "\ntxc_percpu_run_cnt:\n");
++	dhd_lb_stats_dump_cpu_array(strbuf, dhd->txc_percpu_run_cnt);
++	bcm_bprintf(strbuf, "\nTX Completions (Buffer Free) Histogram:\n");
++	dhd_lb_stats_dump_histo(strbuf, dhd->txc_hist);
++#endif /* DHD_LB_TXC */
++
++#ifdef DHD_LB_TXP
++	bcm_bprintf(strbuf, "\ntxp_percpu_run_cnt:\n");
++	dhd_lb_stats_dump_cpu_array(strbuf, dhd->txp_percpu_run_cnt);
++
++	bcm_bprintf(strbuf, "\ntx_start_percpu_run_cnt:\n");
++	dhd_lb_stats_dump_cpu_array(strbuf, dhd->tx_start_percpu_run_cnt);
++#endif /* DHD_LB_TXP */
++
++	bcm_bprintf(strbuf, "\nCPU masks primary(big)=0x%x secondary(little)=0x%x\n",
++		DHD_LB_PRIMARY_CPUS, DHD_LB_SECONDARY_CPUS);
++
++	bcm_bprintf(strbuf, "napi_cpu %x tx_cpu %x\n",
++		atomic_read(&dhd->rx_napi_cpu), atomic_read(&dhd->tx_cpu));
++
++}
++
++/* Given a number 'n' returns 'm' that is next larger power of 2 after n */
++static inline uint32 next_larger_power2(uint32 num)
++{
++	num--;
++	num |= (num >> 1);
++	num |= (num >> 2);
++	num |= (num >> 4);
++	num |= (num >> 8);
++	num |= (num >> 16);
++
++	return (num + 1);
++}
++
++static void dhd_lb_stats_update_histo(uint32 **bin, uint32 count, uint32 cpu)
++{
++	uint32 bin_power;
++	uint32 *p;
++	bin_power = next_larger_power2(count);
++
++	switch (bin_power) {
++		case   1: p = bin[0] + cpu; break;
++		case   2: p = bin[1] + cpu; break;
++		case   4: p = bin[2] + cpu; break;
++		case   8: p = bin[3] + cpu; break;
++		case  16: p = bin[4] + cpu; break;
++		case  32: p = bin[5] + cpu; break;
++		case  64: p = bin[6] + cpu; break;
++		case 128: p = bin[7] + cpu; break;
++		default : p = bin[8] + cpu; break;
++	}
++
++	*p = *p + 1;
++	return;
++}
++
++extern void dhd_lb_stats_update_napi_histo(dhd_pub_t *dhdp, uint32 count)
++{
++	int cpu;
++	dhd_info_t *dhd = dhdp->info;
++
++	cpu = get_cpu();
++	put_cpu();
++	dhd_lb_stats_update_histo(dhd->napi_rx_hist, count, cpu);
++
++	return;
++}
++
++extern void dhd_lb_stats_update_txc_histo(dhd_pub_t *dhdp, uint32 count)
++{
++	int cpu;
++	dhd_info_t *dhd = dhdp->info;
++
++	cpu = get_cpu();
++	put_cpu();
++	dhd_lb_stats_update_histo(dhd->txc_hist, count, cpu);
++
++	return;
++}
++
++extern void dhd_lb_stats_update_rxc_histo(dhd_pub_t *dhdp, uint32 count)
++{
++	int cpu;
++	dhd_info_t *dhd = dhdp->info;
++
++	cpu = get_cpu();
++	put_cpu();
++	dhd_lb_stats_update_histo(dhd->rxc_hist, count, cpu);
++
++	return;
++}
++
++extern void dhd_lb_stats_txc_percpu_cnt_incr(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++	DHD_LB_STATS_PERCPU_ARR_INCR(dhd->txc_percpu_run_cnt);
++}
++
++extern void dhd_lb_stats_rxc_percpu_cnt_incr(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++	DHD_LB_STATS_PERCPU_ARR_INCR(dhd->rxc_percpu_run_cnt);
++}
++#endif /* DHD_LB_STATS */
++
++#endif /* DHD_LB */
++
++#if defined(DISABLE_FRAMEBURST_VSDB) && defined(USE_WFA_CERT_CONF)
++int g_frameburst = 1;
++#endif /* DISABLE_FRAMEBURST_VSDB && USE_WFA_CERT_CONF */
++
++static int dhd_get_pend_8021x_cnt(dhd_info_t *dhd);
++
++/* DHD Perimiter lock only used in router with bypass forwarding. */
++#define DHD_PERIM_RADIO_INIT()              do { /* noop */ } while (0)
++#define DHD_PERIM_LOCK_TRY(unit, flag)      do { /* noop */ } while (0)
++#define DHD_PERIM_UNLOCK_TRY(unit, flag)    do { /* noop */ } while (0)
++
++#ifdef PCIE_FULL_DONGLE
++#if defined(BCM_GMAC3)
++#define DHD_IF_STA_LIST_LOCK_INIT(ifp)      do { /* noop */ } while (0)
++#define DHD_IF_STA_LIST_LOCK(ifp, flags)    ({ BCM_REFERENCE(flags); })
++#define DHD_IF_STA_LIST_UNLOCK(ifp, flags)  ({ BCM_REFERENCE(flags); })
++
++#if defined(DHD_IGMP_UCQUERY) || defined(DHD_UCAST_UPNP)
++#define DHD_IF_WMF_UCFORWARD_LOCK(dhd, ifp, slist) ({ BCM_REFERENCE(slist); &(ifp)->sta_list; })
++#define DHD_IF_WMF_UCFORWARD_UNLOCK(dhd, slist) ({ BCM_REFERENCE(slist); })
++#endif /* DHD_IGMP_UCQUERY || DHD_UCAST_UPNP */
++
++#else /* ! BCM_GMAC3 */
++#define DHD_IF_STA_LIST_LOCK_INIT(ifp) spin_lock_init(&(ifp)->sta_list_lock)
++#define DHD_IF_STA_LIST_LOCK(ifp, flags) \
++	spin_lock_irqsave(&(ifp)->sta_list_lock, (flags))
++#define DHD_IF_STA_LIST_UNLOCK(ifp, flags) \
++	spin_unlock_irqrestore(&(ifp)->sta_list_lock, (flags))
++
++#if defined(DHD_IGMP_UCQUERY) || defined(DHD_UCAST_UPNP)
++static struct list_head * dhd_sta_list_snapshot(dhd_info_t *dhd, dhd_if_t *ifp,
++	struct list_head *snapshot_list);
++static void dhd_sta_list_snapshot_free(dhd_info_t *dhd, struct list_head *snapshot_list);
++#define DHD_IF_WMF_UCFORWARD_LOCK(dhd, ifp, slist) ({ dhd_sta_list_snapshot(dhd, ifp, slist); })
++#define DHD_IF_WMF_UCFORWARD_UNLOCK(dhd, slist) ({ dhd_sta_list_snapshot_free(dhd, slist); })
++#endif /* DHD_IGMP_UCQUERY || DHD_UCAST_UPNP */
++
++#endif /* ! BCM_GMAC3 */
++#endif /* PCIE_FULL_DONGLE */
++
++/* Control fw roaming */
++uint dhd_roam_disable = 0;
++
++#ifdef BCMDBGFS
++extern void dhd_dbgfs_init(dhd_pub_t *dhdp);
++extern void dhd_dbgfs_remove(void);
++#endif
++
++
++/* Control radio state */
++uint dhd_radio_up = 1;
++
++/* Network inteface name */
++char iface_name[IFNAMSIZ] = {'\0'};
++module_param_string(iface_name, iface_name, IFNAMSIZ, 0);
++
++/* The following are specific to the SDIO dongle */
++
++/* IOCTL response timeout */
++int dhd_ioctl_timeout_msec = IOCTL_RESP_TIMEOUT;
++
++/* DS Exit response timeout */
++int ds_exit_timeout_msec = DS_EXIT_TIMEOUT;
++
++/* Idle timeout for backplane clock */
++int dhd_idletime = DHD_IDLETIME_TICKS;
++module_param(dhd_idletime, int, 0);
++
++/* Use polling */
++uint dhd_poll = FALSE;
++module_param(dhd_poll, uint, 0);
++
++/* Use interrupts */
++uint dhd_intr = TRUE;
++module_param(dhd_intr, uint, 0);
++
++/* SDIO Drive Strength (in milliamps) */
++uint dhd_sdiod_drive_strength = 6;
++module_param(dhd_sdiod_drive_strength, uint, 0);
++
++#ifdef BCMSDIO
++/* Tx/Rx bounds */
++extern uint dhd_txbound;
++extern uint dhd_rxbound;
++module_param(dhd_txbound, uint, 0);
++module_param(dhd_rxbound, uint, 0);
++
++/* Deferred transmits */
++extern uint dhd_deferred_tx;
++module_param(dhd_deferred_tx, uint, 0);
++
++#endif /* BCMSDIO */
++
++
++#ifdef SDTEST
++/* Echo packet generator (pkts/s) */
++uint dhd_pktgen = 0;
++module_param(dhd_pktgen, uint, 0);
++
++/* Echo packet len (0 => sawtooth, max 2040) */
++uint dhd_pktgen_len = 0;
++module_param(dhd_pktgen_len, uint, 0);
++#endif /* SDTEST */
++
++
++
++#ifndef BCMDBUS
++/* Allow delayed firmware download for debug purpose */
++int allow_delay_fwdl = FALSE;
++module_param(allow_delay_fwdl, int, 0);
++#endif /* !BCMDBUS */
++
++extern char dhd_version[];
++extern char fw_version[];
++extern char clm_version[];
++
++int dhd_net_bus_devreset(struct net_device *dev, uint8 flag);
++static void dhd_net_if_lock_local(dhd_info_t *dhd);
++static void dhd_net_if_unlock_local(dhd_info_t *dhd);
++static void dhd_suspend_lock(dhd_pub_t *dhdp);
++static void dhd_suspend_unlock(dhd_pub_t *dhdp);
++
++#ifdef WLMEDIA_HTSF
++void htsf_update(dhd_info_t *dhd, void *data);
++tsf_t prev_tsf, cur_tsf;
++
++uint32 dhd_get_htsf(dhd_info_t *dhd, int ifidx);
++static int dhd_ioctl_htsf_get(dhd_info_t *dhd, int ifidx);
++static void dhd_dump_latency(void);
++static void dhd_htsf_addtxts(dhd_pub_t *dhdp, void *pktbuf);
++static void dhd_htsf_addrxts(dhd_pub_t *dhdp, void *pktbuf);
++static void dhd_dump_htsfhisto(histo_t *his, char *s);
++#endif /* WLMEDIA_HTSF */
++
++/* Monitor interface */
++int dhd_monitor_init(void *dhd_pub);
++int dhd_monitor_uninit(void);
++
++
++#if defined(WL_WIRELESS_EXT)
++struct iw_statistics *dhd_get_wireless_stats(struct net_device *dev);
++#endif /* defined(WL_WIRELESS_EXT) */
++
++#ifndef BCMDBUS
++static void dhd_dpc(ulong data);
++#endif /* !BCMDBUS */
++/* forward decl */
++extern int dhd_wait_pend8021x(struct net_device *dev);
++void dhd_os_wd_timer_extend(void *bus, bool extend);
++
++#ifdef TOE
++#ifndef BDC
++#error TOE requires BDC
++#endif /* !BDC */
++static int dhd_toe_get(dhd_info_t *dhd, int idx, uint32 *toe_ol);
++static int dhd_toe_set(dhd_info_t *dhd, int idx, uint32 toe_ol);
++#endif /* TOE */
++
++static int dhd_wl_host_event(dhd_info_t *dhd, int ifidx, void *pktdata, uint16 pktlen,
++		wl_event_msg_t *event_ptr, void **data_ptr);
++
++#if defined(CONFIG_PM_SLEEP)
++static int dhd_pm_callback(struct notifier_block *nfb, unsigned long action, void *ignored)
++{
++	int ret = NOTIFY_DONE;
++	bool suspend = FALSE;
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	dhd_info_t *dhdinfo = (dhd_info_t*)container_of(nfb, struct dhd_info, pm_notifier);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++	BCM_REFERENCE(dhdinfo);
++	BCM_REFERENCE(suspend);
++
++	switch (action) {
++	case PM_HIBERNATION_PREPARE:
++	case PM_SUSPEND_PREPARE:
++		suspend = TRUE;
++		break;
++
++	case PM_POST_HIBERNATION:
++	case PM_POST_SUSPEND:
++		suspend = FALSE;
++		break;
++	}
++
++	printf("%s: action=%ld, suspend=%d, suspend_mode=%d\n",
++		__FUNCTION__, action, suspend, dhdinfo->pub.conf->suspend_mode);
++	if (suspend) {
++		DHD_OS_WAKE_LOCK_WAIVE(&dhdinfo->pub);
++		if (dhdinfo->pub.conf->suspend_mode == PM_NOTIFIER)
++			dhd_suspend_resume_helper(dhdinfo, suspend, 0);
++#if defined(SUPPORT_P2P_GO_PS) && defined(PROP_TXSTATUS)
++		dhd_wlfc_suspend(&dhdinfo->pub);
++#endif /* defined(SUPPORT_P2P_GO_PS) && defined(PROP_TXSTATUS) */
++		if (dhdinfo->pub.conf->suspend_mode == PM_NOTIFIER)
++			dhd_conf_set_suspend_resume(&dhdinfo->pub, suspend);
++		DHD_OS_WAKE_LOCK_RESTORE(&dhdinfo->pub);
++	} else {
++		if (dhdinfo->pub.conf->suspend_mode == PM_NOTIFIER)
++			dhd_conf_set_suspend_resume(&dhdinfo->pub, suspend);
++#if defined(SUPPORT_P2P_GO_PS) && defined(PROP_TXSTATUS)
++		dhd_wlfc_resume(&dhdinfo->pub);
++#endif /* defined(SUPPORT_P2P_GO_PS) && defined(PROP_TXSTATUS) */
++		if (dhdinfo->pub.conf->suspend_mode == PM_NOTIFIER)
++			dhd_suspend_resume_helper(dhdinfo, suspend, 0);
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && (LINUX_VERSION_CODE <= \
++        KERNEL_VERSION(2, 6, 39))
++	dhd_mmc_suspend = suspend;
++	smp_mb();
++#endif
++
++	return ret;
++}
++
++/* to make sure we won't register the same notifier twice, otherwise a loop is likely to be
++ * created in kernel notifier link list (with 'next' pointing to itself)
++ */
++static bool dhd_pm_notifier_registered = FALSE;
++
++extern int register_pm_notifier(struct notifier_block *nb);
++extern int unregister_pm_notifier(struct notifier_block *nb);
++#endif /* CONFIG_PM_SLEEP */
++
++/* Request scheduling of the bus rx frame */
++static void dhd_sched_rxf(dhd_pub_t *dhdp, void *skb);
++static void dhd_os_rxflock(dhd_pub_t *pub);
++static void dhd_os_rxfunlock(dhd_pub_t *pub);
++
++/** priv_link is the link between netdev and the dhdif and dhd_info structs. */
++typedef struct dhd_dev_priv {
++	dhd_info_t * dhd; /* cached pointer to dhd_info in netdevice priv */
++	dhd_if_t   * ifp; /* cached pointer to dhd_if in netdevice priv */
++	int          ifidx; /* interface index */
++	void       * lkup;
++} dhd_dev_priv_t;
++
++#define DHD_DEV_PRIV_SIZE       (sizeof(dhd_dev_priv_t))
++#define DHD_DEV_PRIV(dev)       ((dhd_dev_priv_t *)DEV_PRIV(dev))
++#define DHD_DEV_INFO(dev)       (((dhd_dev_priv_t *)DEV_PRIV(dev))->dhd)
++#define DHD_DEV_IFP(dev)        (((dhd_dev_priv_t *)DEV_PRIV(dev))->ifp)
++#define DHD_DEV_IFIDX(dev)      (((dhd_dev_priv_t *)DEV_PRIV(dev))->ifidx)
++#define DHD_DEV_LKUP(dev)		(((dhd_dev_priv_t *)DEV_PRIV(dev))->lkup)
++
++#if defined(DHD_OF_SUPPORT)
++extern int dhd_wlan_init(void);
++#endif /* defined(DHD_OF_SUPPORT) */
++/** Clear the dhd net_device's private structure. */
++static inline void
++dhd_dev_priv_clear(struct net_device * dev)
++{
++	dhd_dev_priv_t * dev_priv;
++	ASSERT(dev != (struct net_device *)NULL);
++	dev_priv = DHD_DEV_PRIV(dev);
++	dev_priv->dhd = (dhd_info_t *)NULL;
++	dev_priv->ifp = (dhd_if_t *)NULL;
++	dev_priv->ifidx = DHD_BAD_IF;
++	dev_priv->lkup = (void *)NULL;
++}
++
++/** Setup the dhd net_device's private structure. */
++static inline void
++dhd_dev_priv_save(struct net_device * dev, dhd_info_t * dhd, dhd_if_t * ifp,
++                  int ifidx)
++{
++	dhd_dev_priv_t * dev_priv;
++	ASSERT(dev != (struct net_device *)NULL);
++	dev_priv = DHD_DEV_PRIV(dev);
++	dev_priv->dhd = dhd;
++	dev_priv->ifp = ifp;
++	dev_priv->ifidx = ifidx;
++}
++
++#ifdef PCIE_FULL_DONGLE
++
++/** Dummy objects are defined with state representing bad|down.
++ * Performance gains from reducing branch conditionals, instruction parallelism,
++ * dual issue, reducing load shadows, avail of larger pipelines.
++ * Use DHD_XXX_NULL instead of (dhd_xxx_t *)NULL, whenever an object pointer
++ * is accessed via the dhd_sta_t.
++ */
++
++/* Dummy dhd_info object */
++dhd_info_t dhd_info_null = {
++#if defined(BCM_GMAC3)
++	.fwdh = FWDER_NULL,
++#endif
++	.pub = {
++	         .info = &dhd_info_null,
++#ifdef DHDTCPACK_SUPPRESS
++	         .tcpack_sup_mode = TCPACK_SUP_REPLACE,
++#endif /* DHDTCPACK_SUPPRESS */
++#if defined(TRAFFIC_MGMT_DWM)
++	         .dhd_tm_dwm_tbl = { .dhd_dwm_enabled = TRUE },
++#endif
++	         .up = FALSE,
++	         .busstate = DHD_BUS_DOWN
++	}
++};
++#define DHD_INFO_NULL (&dhd_info_null)
++#define DHD_PUB_NULL  (&dhd_info_null.pub)
++
++/* Dummy netdevice object */
++struct net_device dhd_net_dev_null = {
++	.reg_state = NETREG_UNREGISTERED
++};
++#define DHD_NET_DEV_NULL (&dhd_net_dev_null)
++
++/* Dummy dhd_if object */
++dhd_if_t dhd_if_null = {
++#if defined(BCM_GMAC3)
++	.fwdh = FWDER_NULL,
++#endif
++#ifdef WMF
++	.wmf = { .wmf_enable = TRUE },
++#endif
++	.info = DHD_INFO_NULL,
++	.net = DHD_NET_DEV_NULL,
++	.idx = DHD_BAD_IF
++};
++#define DHD_IF_NULL  (&dhd_if_null)
++
++#define DHD_STA_NULL ((dhd_sta_t *)NULL)
++
++/** Interface STA list management. */
++
++/** Fetch the dhd_if object, given the interface index in the dhd. */
++static inline dhd_if_t *dhd_get_ifp(dhd_pub_t *dhdp, uint32 ifidx);
++
++/** Alloc/Free a dhd_sta object from the dhd instances' sta_pool. */
++static void dhd_sta_free(dhd_pub_t *pub, dhd_sta_t *sta);
++static dhd_sta_t * dhd_sta_alloc(dhd_pub_t * dhdp);
++
++/* Delete a dhd_sta or flush all dhd_sta in an interface's sta_list. */
++static void dhd_if_del_sta_list(dhd_if_t * ifp);
++static void	dhd_if_flush_sta(dhd_if_t * ifp);
++
++/* Construct/Destruct a sta pool. */
++static int dhd_sta_pool_init(dhd_pub_t *dhdp, int max_sta);
++static void dhd_sta_pool_fini(dhd_pub_t *dhdp, int max_sta);
++/* Clear the pool of dhd_sta_t objects for built-in type driver */
++static void dhd_sta_pool_clear(dhd_pub_t *dhdp, int max_sta);
++
++
++/* Return interface pointer */
++static inline dhd_if_t *dhd_get_ifp(dhd_pub_t *dhdp, uint32 ifidx)
++{
++	ASSERT(ifidx < DHD_MAX_IFS);
++
++	if (ifidx >= DHD_MAX_IFS)
++		return NULL;
++
++	return dhdp->info->iflist[ifidx];
++}
++
++/** Reset a dhd_sta object and free into the dhd pool. */
++static void
++dhd_sta_free(dhd_pub_t * dhdp, dhd_sta_t * sta)
++{
++	int prio;
++
++	ASSERT((sta != DHD_STA_NULL) && (sta->idx != ID16_INVALID));
++
++	ASSERT((dhdp->staid_allocator != NULL) && (dhdp->sta_pool != NULL));
++
++	/*
++	 * Flush and free all packets in all flowring's queues belonging to sta.
++	 * Packets in flow ring will be flushed later.
++	 */
++	for (prio = 0; prio < (int)NUMPRIO; prio++) {
++		uint16 flowid = sta->flowid[prio];
++
++		if (flowid != FLOWID_INVALID) {
++			unsigned long flags;
++			flow_queue_t * queue = dhd_flow_queue(dhdp, flowid);
++			flow_ring_node_t * flow_ring_node;
++
++#ifdef DHDTCPACK_SUPPRESS
++			/* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt,
++			 * when there is a newly coming packet from network stack.
++			 */
++			dhd_tcpack_info_tbl_clean(dhdp);
++#endif /* DHDTCPACK_SUPPRESS */
++
++			flow_ring_node = dhd_flow_ring_node(dhdp, flowid);
++			DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++			flow_ring_node->status = FLOW_RING_STATUS_STA_FREEING;
++
++			if (!DHD_FLOW_QUEUE_EMPTY(queue)) {
++				void * pkt;
++				while ((pkt = dhd_flow_queue_dequeue(dhdp, queue)) != NULL) {
++					PKTFREE(dhdp->osh, pkt, TRUE);
++				}
++			}
++
++			DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++			ASSERT(DHD_FLOW_QUEUE_EMPTY(queue));
++		}
++
++		sta->flowid[prio] = FLOWID_INVALID;
++	}
++
++	id16_map_free(dhdp->staid_allocator, sta->idx);
++	DHD_CUMM_CTR_INIT(&sta->cumm_ctr);
++	sta->ifp = DHD_IF_NULL; /* dummy dhd_if object */
++	sta->ifidx = DHD_BAD_IF;
++	bzero(sta->ea.octet, ETHER_ADDR_LEN);
++	INIT_LIST_HEAD(&sta->list);
++	sta->idx = ID16_INVALID; /* implying free */
++}
++
++/** Allocate a dhd_sta object from the dhd pool. */
++static dhd_sta_t *
++dhd_sta_alloc(dhd_pub_t * dhdp)
++{
++	uint16 idx;
++	dhd_sta_t * sta;
++	dhd_sta_pool_t * sta_pool;
++
++	ASSERT((dhdp->staid_allocator != NULL) && (dhdp->sta_pool != NULL));
++
++	idx = id16_map_alloc(dhdp->staid_allocator);
++	if (idx == ID16_INVALID) {
++		DHD_ERROR(("%s: cannot get free staid\n", __FUNCTION__));
++		return DHD_STA_NULL;
++	}
++
++	sta_pool = (dhd_sta_pool_t *)(dhdp->sta_pool);
++	sta = &sta_pool[idx];
++
++	ASSERT((sta->idx == ID16_INVALID) &&
++	       (sta->ifp == DHD_IF_NULL) && (sta->ifidx == DHD_BAD_IF));
++
++	DHD_CUMM_CTR_INIT(&sta->cumm_ctr);
++
++	sta->idx = idx; /* implying allocated */
++
++	return sta;
++}
++
++/** Delete all STAs in an interface's STA list. */
++static void
++dhd_if_del_sta_list(dhd_if_t *ifp)
++{
++	dhd_sta_t *sta, *next;
++	unsigned long flags;
++
++	DHD_IF_STA_LIST_LOCK(ifp, flags);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	list_for_each_entry_safe(sta, next, &ifp->sta_list, list) {
++#if defined(BCM_GMAC3)
++		if (ifp->fwdh) {
++			/* Remove sta from WOFA forwarder. */
++			fwder_deassoc(ifp->fwdh, (uint16 *)(sta->ea.octet), (uintptr_t)sta);
++		}
++#endif /* BCM_GMAC3 */
++		list_del(&sta->list);
++		dhd_sta_free(&ifp->info->pub, sta);
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	DHD_IF_STA_LIST_UNLOCK(ifp, flags);
++
++	return;
++}
++
++/** Router/GMAC3: Flush all station entries in the forwarder's WOFA database. */
++static void
++dhd_if_flush_sta(dhd_if_t * ifp)
++{
++#if defined(BCM_GMAC3)
++
++	if (ifp && (ifp->fwdh != FWDER_NULL)) {
++		dhd_sta_t *sta, *next;
++		unsigned long flags;
++
++		DHD_IF_STA_LIST_LOCK(ifp, flags);
++
++		list_for_each_entry_safe(sta, next, &ifp->sta_list, list) {
++			/* Remove any sta entry from WOFA forwarder. */
++			fwder_flush(ifp->fwdh, (uintptr_t)sta);
++		}
++
++		DHD_IF_STA_LIST_UNLOCK(ifp, flags);
++	}
++#endif /* BCM_GMAC3 */
++}
++
++/** Construct a pool of dhd_sta_t objects to be used by interfaces. */
++static int
++dhd_sta_pool_init(dhd_pub_t *dhdp, int max_sta)
++{
++	int idx, prio, sta_pool_memsz;
++	dhd_sta_t * sta;
++	dhd_sta_pool_t * sta_pool;
++	void * staid_allocator;
++
++	ASSERT(dhdp != (dhd_pub_t *)NULL);
++	ASSERT((dhdp->staid_allocator == NULL) && (dhdp->sta_pool == NULL));
++
++	/* dhd_sta objects per radio are managed in a table. id#0 reserved. */
++	staid_allocator = id16_map_init(dhdp->osh, max_sta, 1);
++	if (staid_allocator == NULL) {
++		DHD_ERROR(("%s: sta id allocator init failure\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	/* Pre allocate a pool of dhd_sta objects (one extra). */
++	sta_pool_memsz = ((max_sta + 1) * sizeof(dhd_sta_t)); /* skip idx 0 */
++	sta_pool = (dhd_sta_pool_t *)MALLOC(dhdp->osh, sta_pool_memsz);
++	if (sta_pool == NULL) {
++		DHD_ERROR(("%s: sta table alloc failure\n", __FUNCTION__));
++		id16_map_fini(dhdp->osh, staid_allocator);
++		return BCME_ERROR;
++	}
++
++	dhdp->sta_pool = sta_pool;
++	dhdp->staid_allocator = staid_allocator;
++
++	/* Initialize all sta(s) for the pre-allocated free pool. */
++	bzero((uchar *)sta_pool, sta_pool_memsz);
++	for (idx = max_sta; idx >= 1; idx--) { /* skip sta_pool[0] */
++		sta = &sta_pool[idx];
++		sta->idx = id16_map_alloc(staid_allocator);
++		ASSERT(sta->idx <= max_sta);
++	}
++	/* Now place them into the pre-allocated free pool. */
++	for (idx = 1; idx <= max_sta; idx++) {
++		sta = &sta_pool[idx];
++		for (prio = 0; prio < (int)NUMPRIO; prio++) {
++			sta->flowid[prio] = FLOWID_INVALID; /* Flow rings do not exist */
++		}
++		dhd_sta_free(dhdp, sta);
++	}
++
++	return BCME_OK;
++}
++
++/** Destruct the pool of dhd_sta_t objects.
++ * Caller must ensure that no STA objects are currently associated with an if.
++ */
++static void
++dhd_sta_pool_fini(dhd_pub_t *dhdp, int max_sta)
++{
++	dhd_sta_pool_t * sta_pool = (dhd_sta_pool_t *)dhdp->sta_pool;
++
++	if (sta_pool) {
++		int idx;
++		int sta_pool_memsz = ((max_sta + 1) * sizeof(dhd_sta_t));
++		for (idx = 1; idx <= max_sta; idx++) {
++			ASSERT(sta_pool[idx].ifp == DHD_IF_NULL);
++			ASSERT(sta_pool[idx].idx == ID16_INVALID);
++		}
++		MFREE(dhdp->osh, dhdp->sta_pool, sta_pool_memsz);
++		dhdp->sta_pool = NULL;
++	}
++
++	id16_map_fini(dhdp->osh, dhdp->staid_allocator);
++	dhdp->staid_allocator = NULL;
++}
++
++/* Clear the pool of dhd_sta_t objects for built-in type driver */
++static void
++dhd_sta_pool_clear(dhd_pub_t *dhdp, int max_sta)
++{
++	int idx, prio, sta_pool_memsz;
++	dhd_sta_t * sta;
++	dhd_sta_pool_t * sta_pool;
++	void *staid_allocator;
++
++	if (!dhdp) {
++		DHD_ERROR(("%s: dhdp is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	sta_pool = (dhd_sta_pool_t *)dhdp->sta_pool;
++	staid_allocator = dhdp->staid_allocator;
++
++	if (!sta_pool) {
++		DHD_ERROR(("%s: sta_pool is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (!staid_allocator) {
++		DHD_ERROR(("%s: staid_allocator is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	/* clear free pool */
++	sta_pool_memsz = ((max_sta + 1) * sizeof(dhd_sta_t));
++	bzero((uchar *)sta_pool, sta_pool_memsz);
++
++	/* dhd_sta objects per radio are managed in a table. id#0 reserved. */
++	id16_map_clear(staid_allocator, max_sta, 1);
++
++	/* Initialize all sta(s) for the pre-allocated free pool. */
++	for (idx = max_sta; idx >= 1; idx--) { /* skip sta_pool[0] */
++		sta = &sta_pool[idx];
++		sta->idx = id16_map_alloc(staid_allocator);
++		ASSERT(sta->idx <= max_sta);
++	}
++	/* Now place them into the pre-allocated free pool. */
++	for (idx = 1; idx <= max_sta; idx++) {
++		sta = &sta_pool[idx];
++		for (prio = 0; prio < (int)NUMPRIO; prio++) {
++			sta->flowid[prio] = FLOWID_INVALID; /* Flow rings do not exist */
++		}
++		dhd_sta_free(dhdp, sta);
++	}
++}
++
++/** Find STA with MAC address ea in an interface's STA list. */
++dhd_sta_t *
++dhd_find_sta(void *pub, int ifidx, void *ea)
++{
++	dhd_sta_t *sta;
++	dhd_if_t *ifp;
++	unsigned long flags;
++
++	ASSERT(ea != NULL);
++	ifp = dhd_get_ifp((dhd_pub_t *)pub, ifidx);
++	if (ifp == NULL)
++		return DHD_STA_NULL;
++
++	DHD_IF_STA_LIST_LOCK(ifp, flags);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	list_for_each_entry(sta, &ifp->sta_list, list) {
++		if (!memcmp(sta->ea.octet, ea, ETHER_ADDR_LEN)) {
++			DHD_INFO(("%s: found STA " MACDBG "\n",
++				__FUNCTION__, MAC2STRDBG((char *)ea)));
++			DHD_IF_STA_LIST_UNLOCK(ifp, flags);
++			return sta;
++		}
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	DHD_IF_STA_LIST_UNLOCK(ifp, flags);
++
++	return DHD_STA_NULL;
++}
++
++/** Add STA into the interface's STA list. */
++dhd_sta_t *
++dhd_add_sta(void *pub, int ifidx, void *ea)
++{
++	dhd_sta_t *sta;
++	dhd_if_t *ifp;
++	unsigned long flags;
++
++	ASSERT(ea != NULL);
++	ifp = dhd_get_ifp((dhd_pub_t *)pub, ifidx);
++	if (ifp == NULL)
++		return DHD_STA_NULL;
++
++	sta = dhd_sta_alloc((dhd_pub_t *)pub);
++	if (sta == DHD_STA_NULL) {
++		DHD_ERROR(("%s: Alloc failed\n", __FUNCTION__));
++		return DHD_STA_NULL;
++	}
++
++	memcpy(sta->ea.octet, ea, ETHER_ADDR_LEN);
++
++	/* link the sta and the dhd interface */
++	sta->ifp = ifp;
++	sta->ifidx = ifidx;
++#ifdef DHD_WMF
++	sta->psta_prim = NULL;
++#endif
++	INIT_LIST_HEAD(&sta->list);
++
++	DHD_IF_STA_LIST_LOCK(ifp, flags);
++
++	list_add_tail(&sta->list, &ifp->sta_list);
++
++#if defined(BCM_GMAC3)
++	if (ifp->fwdh) {
++		ASSERT(ISALIGNED(ea, 2));
++		/* Add sta to WOFA forwarder. */
++		fwder_reassoc(ifp->fwdh, (uint16 *)ea, (uintptr_t)sta);
++	}
++#endif /* BCM_GMAC3 */
++
++	DHD_IF_STA_LIST_UNLOCK(ifp, flags);
++
++	return sta;
++}
++
++/** Delete all STAs from the interface's STA list. */
++void
++dhd_del_all_sta(void *pub, int ifidx)
++{
++	dhd_sta_t *sta, *next;
++	dhd_if_t *ifp;
++	unsigned long flags;
++
++	ifp = dhd_get_ifp((dhd_pub_t *)pub, ifidx);
++	if (ifp == NULL)
++		return;
++
++	DHD_IF_STA_LIST_LOCK(ifp, flags);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	list_for_each_entry_safe(sta, next, &ifp->sta_list, list) {
++#if defined(BCM_GMAC3)
++		if (ifp->fwdh) { /* Found a sta, remove from WOFA forwarder. */
++			ASSERT(ISALIGNED(sta->ea.octet, 2));
++			fwder_deassoc(ifp->fwdh, (uint16 *)sta->ea.octet, (uintptr_t)sta);
++		}
++#endif /* BCM_GMAC3 */
++
++		list_del(&sta->list);
++		dhd_sta_free(&ifp->info->pub, sta);
++#ifdef DHD_L2_FILTER
++		if (ifp->parp_enable) {
++			/* clear Proxy ARP cache of specific Ethernet Address */
++			bcm_l2_filter_arp_table_update(((dhd_pub_t*)pub)->osh,
++					ifp->phnd_arp_table, FALSE,
++					sta->ea.octet, FALSE, ((dhd_pub_t*)pub)->tickcnt);
++		}
++#endif /* DHD_L2_FILTER */
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	DHD_IF_STA_LIST_UNLOCK(ifp, flags);
++
++	return;
++}
++
++/** Delete STA from the interface's STA list. */
++void
++dhd_del_sta(void *pub, int ifidx, void *ea)
++{
++	dhd_sta_t *sta, *next;
++	dhd_if_t *ifp;
++	unsigned long flags;
++	char macstr[ETHER_ADDR_STR_LEN];
++
++	ASSERT(ea != NULL);
++	ifp = dhd_get_ifp((dhd_pub_t *)pub, ifidx);
++	if (ifp == NULL)
++		return;
++
++	DHD_IF_STA_LIST_LOCK(ifp, flags);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	list_for_each_entry_safe(sta, next, &ifp->sta_list, list) {
++		if (!memcmp(sta->ea.octet, ea, ETHER_ADDR_LEN)) {
++#if defined(BCM_GMAC3)
++			if (ifp->fwdh) { /* Found a sta, remove from WOFA forwarder. */
++				ASSERT(ISALIGNED(ea, 2));
++				fwder_deassoc(ifp->fwdh, (uint16 *)ea, (uintptr_t)sta);
++			}
++#endif /* BCM_GMAC3 */
++			DHD_MAC_TO_STR(((char *)ea), macstr);
++			DHD_ERROR(("%s: Deleting STA  %s\n", __FUNCTION__, macstr));
++			list_del(&sta->list);
++			dhd_sta_free(&ifp->info->pub, sta);
++		}
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	DHD_IF_STA_LIST_UNLOCK(ifp, flags);
++#ifdef DHD_L2_FILTER
++	if (ifp->parp_enable) {
++		/* clear Proxy ARP cache of specific Ethernet Address */
++		bcm_l2_filter_arp_table_update(((dhd_pub_t*)pub)->osh, ifp->phnd_arp_table, FALSE,
++			ea, FALSE, ((dhd_pub_t*)pub)->tickcnt);
++	}
++#endif /* DHD_L2_FILTER */
++	return;
++}
++
++/** Add STA if it doesn't exist. Not reentrant. */
++dhd_sta_t*
++dhd_findadd_sta(void *pub, int ifidx, void *ea)
++{
++	dhd_sta_t *sta;
++
++	sta = dhd_find_sta(pub, ifidx, ea);
++
++	if (!sta) {
++		/* Add entry */
++		sta = dhd_add_sta(pub, ifidx, ea);
++	}
++
++	return sta;
++}
++
++#if defined(DHD_IGMP_UCQUERY) || defined(DHD_UCAST_UPNP)
++#if !defined(BCM_GMAC3)
++static struct list_head *
++dhd_sta_list_snapshot(dhd_info_t *dhd, dhd_if_t *ifp, struct list_head *snapshot_list)
++{
++	unsigned long flags;
++	dhd_sta_t *sta, *snapshot;
++
++	INIT_LIST_HEAD(snapshot_list);
++
++	DHD_IF_STA_LIST_LOCK(ifp, flags);
++
++	list_for_each_entry(sta, &ifp->sta_list, list) {
++		/* allocate one and add to snapshot */
++		snapshot = (dhd_sta_t *)MALLOC(dhd->pub.osh, sizeof(dhd_sta_t));
++		if (snapshot == NULL) {
++			DHD_ERROR(("%s: Cannot allocate memory\n", __FUNCTION__));
++			continue;
++		}
++
++		memcpy(snapshot->ea.octet, sta->ea.octet, ETHER_ADDR_LEN);
++
++		INIT_LIST_HEAD(&snapshot->list);
++		list_add_tail(&snapshot->list, snapshot_list);
++	}
++
++	DHD_IF_STA_LIST_UNLOCK(ifp, flags);
++
++	return snapshot_list;
++}
++
++static void
++dhd_sta_list_snapshot_free(dhd_info_t *dhd, struct list_head *snapshot_list)
++{
++	dhd_sta_t *sta, *next;
++
++	list_for_each_entry_safe(sta, next, snapshot_list, list) {
++		list_del(&sta->list);
++		MFREE(dhd->pub.osh, sta, sizeof(dhd_sta_t));
++	}
++}
++#endif /* !BCM_GMAC3 */
++#endif /* DHD_IGMP_UCQUERY || DHD_UCAST_UPNP */
++
++#else
++static inline void dhd_if_flush_sta(dhd_if_t * ifp) { }
++static inline void dhd_if_del_sta_list(dhd_if_t *ifp) {}
++static inline int dhd_sta_pool_init(dhd_pub_t *dhdp, int max_sta) { return BCME_OK; }
++static inline void dhd_sta_pool_fini(dhd_pub_t *dhdp, int max_sta) {}
++static inline void dhd_sta_pool_clear(dhd_pub_t *dhdp, int max_sta) {}
++dhd_sta_t *dhd_findadd_sta(void *pub, int ifidx, void *ea) { return NULL; }
++dhd_sta_t *dhd_find_sta(void *pub, int ifidx, void *ea) { return NULL; }
++void dhd_del_sta(void *pub, int ifidx, void *ea) {}
++#endif /* PCIE_FULL_DONGLE */
++
++
++
++#if defined(DHD_LB)
++
++#if defined(DHD_LB_TXC) || defined(DHD_LB_RXC) || defined(DHD_LB_TXP)
++/**
++ * dhd_tasklet_schedule - Function that runs in IPI context of the destination
++ * CPU and schedules a tasklet.
++ * @tasklet: opaque pointer to the tasklet
++ */
++INLINE void
++dhd_tasklet_schedule(void *tasklet)
++{
++	tasklet_schedule((struct tasklet_struct *)tasklet);
++}
++/**
++ * dhd_tasklet_schedule_on - Executes the passed takslet in a given CPU
++ * @tasklet: tasklet to be scheduled
++ * @on_cpu: cpu core id
++ *
++ * If the requested cpu is online, then an IPI is sent to this cpu via the
++ * smp_call_function_single with no wait and the tasklet_schedule function
++ * will be invoked to schedule the specified tasklet on the requested CPU.
++ */
++INLINE void
++dhd_tasklet_schedule_on(struct tasklet_struct *tasklet, int on_cpu)
++{
++	const int wait = 0;
++	smp_call_function_single(on_cpu,
++		dhd_tasklet_schedule, (void *)tasklet, wait);
++}
++
++/**
++ * dhd_work_schedule_on - Executes the passed work in a given CPU
++ * @work: work to be scheduled
++ * @on_cpu: cpu core id
++ *
++ * If the requested cpu is online, then an IPI is sent to this cpu via the
++ * schedule_work_on and the work function
++ * will be invoked to schedule the specified work on the requested CPU.
++ */
++
++INLINE void
++dhd_work_schedule_on(struct work_struct *work, int on_cpu)
++{
++	schedule_work_on(on_cpu, work);
++}
++#endif /* DHD_LB_TXC || DHD_LB_RXC || DHD_LB_TXP */
++
++#if defined(DHD_LB_TXC)
++/**
++ * dhd_lb_tx_compl_dispatch - load balance by dispatching the tx_compl_tasklet
++ * on another cpu. The tx_compl_tasklet will take care of DMA unmapping and
++ * freeing the packets placed in the tx_compl workq
++ */
++void
++dhd_lb_tx_compl_dispatch(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++	int curr_cpu, on_cpu;
++
++	if (dhd->rx_napi_netdev == NULL) {
++		DHD_ERROR(("%s: dhd->rx_napi_netdev is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	DHD_LB_STATS_INCR(dhd->txc_sched_cnt);
++	/*
++	 * If the destination CPU is NOT online or is same as current CPU
++	 * no need to schedule the work
++	 */
++	curr_cpu = get_cpu();
++	put_cpu();
++
++	on_cpu = atomic_read(&dhd->tx_compl_cpu);
++
++	if ((on_cpu == curr_cpu) || (!cpu_online(on_cpu))) {
++		dhd_tasklet_schedule(&dhd->tx_compl_tasklet);
++	} else {
++		schedule_work(&dhd->tx_compl_dispatcher_work);
++	}
++}
++
++static void dhd_tx_compl_dispatcher_fn(struct work_struct * work)
++{
++	struct dhd_info *dhd =
++		container_of(work, struct dhd_info, tx_compl_dispatcher_work);
++	int cpu;
++
++	get_online_cpus();
++	cpu = atomic_read(&dhd->tx_compl_cpu);
++	if (!cpu_online(cpu))
++		dhd_tasklet_schedule(&dhd->tx_compl_tasklet);
++	else
++		dhd_tasklet_schedule_on(&dhd->tx_compl_tasklet, cpu);
++	put_online_cpus();
++}
++#endif /* DHD_LB_TXC */
++
++#if defined(DHD_LB_RXC)
++/**
++ * dhd_lb_rx_compl_dispatch - load balance by dispatching the rx_compl_tasklet
++ * on another cpu. The rx_compl_tasklet will take care of reposting rx buffers
++ * in the H2D RxBuffer Post common ring, by using the recycled pktids that were
++ * placed in the rx_compl workq.
++ *
++ * @dhdp: pointer to dhd_pub object
++ */
++void
++dhd_lb_rx_compl_dispatch(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++	int curr_cpu, on_cpu;
++
++	if (dhd->rx_napi_netdev == NULL) {
++		DHD_ERROR(("%s: dhd->rx_napi_netdev is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	DHD_LB_STATS_INCR(dhd->rxc_sched_cnt);
++	/*
++	 * If the destination CPU is NOT online or is same as current CPU
++	 * no need to schedule the work
++	 */
++	curr_cpu = get_cpu();
++	put_cpu();
++	on_cpu = atomic_read(&dhd->rx_compl_cpu);
++
++	if ((on_cpu == curr_cpu) || (!cpu_online(on_cpu))) {
++		dhd_tasklet_schedule(&dhd->rx_compl_tasklet);
++	} else {
++		dhd_rx_compl_dispatcher_fn(dhdp);
++	}
++}
++
++static void dhd_rx_compl_dispatcher_fn(dhd_pub_t *dhdp)
++{
++	struct dhd_info *dhd = dhdp->info;
++	int cpu;
++
++	preempt_disable();
++	cpu = atomic_read(&dhd->rx_compl_cpu);
++	if (!cpu_online(cpu))
++		dhd_tasklet_schedule(&dhd->rx_compl_tasklet);
++	else {
++		dhd_tasklet_schedule_on(&dhd->rx_compl_tasklet, cpu);
++	}
++	preempt_enable();
++}
++#endif /* DHD_LB_RXC */
++
++#if defined(DHD_LB_TXP)
++static void dhd_tx_dispatcher_work(struct work_struct * work)
++{
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	struct dhd_info *dhd =
++		container_of(work, struct dhd_info, tx_dispatcher_work);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	dhd_tasklet_schedule(&dhd->tx_tasklet);
++}
++
++static void dhd_tx_dispatcher_fn(dhd_pub_t *dhdp)
++{
++	int cpu;
++	int net_tx_cpu;
++	dhd_info_t *dhd = dhdp->info;
++
++	preempt_disable();
++	cpu = atomic_read(&dhd->tx_cpu);
++	net_tx_cpu = atomic_read(&dhd->net_tx_cpu);
++
++	/*
++	 * Now if the NET_TX has pushed the packet in the same
++	 * CPU that is chosen for Tx processing, seperate it out
++	 * i.e run the TX processing tasklet in compl_cpu
++	 */
++	if (net_tx_cpu == cpu)
++		cpu = atomic_read(&dhd->tx_compl_cpu);
++
++	if (!cpu_online(cpu)) {
++		/*
++		 * Ooohh... but the Chosen CPU is not online,
++		 * Do the job in the current CPU itself.
++		 */
++		dhd_tasklet_schedule(&dhd->tx_tasklet);
++	} else {
++		/*
++		 * Schedule tx_dispatcher_work to on the cpu which
++		 * in turn will schedule tx_tasklet.
++		 */
++		dhd_work_schedule_on(&dhd->tx_dispatcher_work, cpu);
++	}
++	preempt_enable();
++}
++
++/**
++ * dhd_lb_tx_dispatch - load balance by dispatching the tx_tasklet
++ * on another cpu. The tx_tasklet will take care of actually putting
++ * the skbs into appropriate flow ring and ringing H2D interrupt
++ *
++ * @dhdp: pointer to dhd_pub object
++ */
++static void
++dhd_lb_tx_dispatch(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++	int curr_cpu;
++
++	curr_cpu = get_cpu();
++	put_cpu();
++
++	/* Record the CPU in which the TX request from Network stack came */
++	atomic_set(&dhd->net_tx_cpu, curr_cpu);
++
++	/* Schedule the work to dispatch ... */
++	dhd_tx_dispatcher_fn(dhdp);
++
++}
++#endif /* DHD_LB_TXP */
++
++#if defined(DHD_LB_RXP)
++/**
++ * dhd_napi_poll - Load balance napi poll function to process received
++ * packets and send up the network stack using netif_receive_skb()
++ *
++ * @napi: napi object in which context this poll function is invoked
++ * @budget: number of packets to be processed.
++ *
++ * Fetch the dhd_info given the rx_napi_struct. Move all packets from the
++ * rx_napi_queue into a local rx_process_queue (lock and queue move and unlock).
++ * Dequeue each packet from head of rx_process_queue, fetch the ifid from the
++ * packet tag and sendup.
++ */
++static int
++dhd_napi_poll(struct napi_struct *napi, int budget)
++{
++	int ifid;
++	const int pkt_count = 1;
++	const int chan = 0;
++	struct sk_buff * skb;
++	unsigned long flags;
++	struct dhd_info *dhd;
++	int processed = 0;
++	struct sk_buff_head rx_process_queue;
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	dhd = container_of(napi, struct dhd_info, rx_napi_struct);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++	DHD_INFO(("%s napi_queue<%d> budget<%d>\n",
++		__FUNCTION__, skb_queue_len(&dhd->rx_napi_queue), budget));
++		__skb_queue_head_init(&rx_process_queue);
++
++	/* extract the entire rx_napi_queue into local rx_process_queue */
++	spin_lock_irqsave(&dhd->rx_napi_queue.lock, flags);
++	skb_queue_splice_tail_init(&dhd->rx_napi_queue, &rx_process_queue);
++	spin_unlock_irqrestore(&dhd->rx_napi_queue.lock, flags);
++
++	while ((skb = __skb_dequeue(&rx_process_queue)) != NULL) {
++		OSL_PREFETCH(skb->data);
++
++		ifid = DHD_PKTTAG_IFID((dhd_pkttag_fr_t *)PKTTAG(skb));
++
++		DHD_INFO(("%s dhd_rx_frame pkt<%p> ifid<%d>\n",
++			__FUNCTION__, skb, ifid));
++
++		dhd_rx_frame(&dhd->pub, ifid, skb, pkt_count, chan);
++		processed++;
++	}
++
++	DHD_LB_STATS_UPDATE_NAPI_HISTO(&dhd->pub, processed);
++
++	DHD_INFO(("%s processed %d\n", __FUNCTION__, processed));
++	napi_complete(napi);
++
++	return budget - 1;
++}
++
++/**
++ * dhd_napi_schedule - Place the napi struct into the current cpus softnet napi
++ * poll list. This function may be invoked via the smp_call_function_single
++ * from a remote CPU.
++ *
++ * This function will essentially invoke __raise_softirq_irqoff(NET_RX_SOFTIRQ)
++ * after the napi_struct is added to the softnet data's poll_list
++ *
++ * @info: pointer to a dhd_info struct
++ */
++static void
++dhd_napi_schedule(void *info)
++{
++	dhd_info_t *dhd = (dhd_info_t *)info;
++
++	DHD_INFO(("%s rx_napi_struct<%p> on cpu<%d>\n",
++		__FUNCTION__, &dhd->rx_napi_struct, atomic_read(&dhd->rx_napi_cpu)));
++
++	/* add napi_struct to softnet data poll list and raise NET_RX_SOFTIRQ */
++	if (napi_schedule_prep(&dhd->rx_napi_struct)) {
++		__napi_schedule(&dhd->rx_napi_struct);
++		DHD_LB_STATS_PERCPU_ARR_INCR(dhd->napi_percpu_run_cnt);
++	}
++
++	/*
++	 * If the rx_napi_struct was already running, then we let it complete
++	 * processing all its packets. The rx_napi_struct may only run on one
++	 * core at a time, to avoid out-of-order handling.
++	 */
++}
++
++/**
++ * dhd_napi_schedule_on - API to schedule on a desired CPU core a NET_RX_SOFTIRQ
++ * action after placing the dhd's rx_process napi object in the the remote CPU's
++ * softnet data's poll_list.
++ *
++ * @dhd: dhd_info which has the rx_process napi object
++ * @on_cpu: desired remote CPU id
++ */
++static INLINE int
++dhd_napi_schedule_on(dhd_info_t *dhd, int on_cpu)
++{
++	int wait = 0; /* asynchronous IPI */
++	DHD_INFO(("%s dhd<%p> napi<%p> on_cpu<%d>\n",
++		__FUNCTION__, dhd, &dhd->rx_napi_struct, on_cpu));
++
++	if (smp_call_function_single(on_cpu, dhd_napi_schedule, dhd, wait)) {
++		DHD_ERROR(("%s smp_call_function_single on_cpu<%d> failed\n",
++			__FUNCTION__, on_cpu));
++	}
++
++	DHD_LB_STATS_INCR(dhd->napi_sched_cnt);
++
++	return 0;
++}
++
++/*
++ * Call get_online_cpus/put_online_cpus around dhd_napi_schedule_on
++ * Why should we do this?
++ * The candidacy algorithm is run from the call back function
++ * registered to CPU hotplug notifier. This call back happens from Worker
++ * context. The dhd_napi_schedule_on is also from worker context.
++ * Note that both of this can run on two different CPUs at the same time.
++ * So we can possibly have a window where a given CPUn is being brought
++ * down from CPUm while we try to run a function on CPUn.
++ * To prevent this its better have the whole code to execute an SMP
++ * function under get_online_cpus.
++ * This function call ensures that hotplug mechanism does not kick-in
++ * until we are done dealing with online CPUs
++ * If the hotplug worker is already running, no worries because the
++ * candidacy algo would then reflect the same in dhd->rx_napi_cpu.
++ *
++ * The below mentioned code structure is proposed in
++ * https://www.kernel.org/doc/Documentation/cpu-hotplug.txt
++ * for the question
++ * Q: I need to ensure that a particular cpu is not removed when there is some
++ *    work specific to this cpu is in progress
++ *
++ * According to the documentation calling get_online_cpus is NOT required, if
++ * we are running from tasklet context. Since dhd_rx_napi_dispatcher_fn can
++ * run from Work Queue context we have to call these functions
++ */
++static void dhd_rx_napi_dispatcher_fn(struct work_struct * work)
++{
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	struct dhd_info *dhd =
++		container_of(work, struct dhd_info, rx_napi_dispatcher_work);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	int cpu;
++
++	get_online_cpus();
++	cpu = atomic_read(&dhd->rx_napi_cpu);
++
++	if (!cpu_online(cpu))
++		dhd_napi_schedule(dhd);
++	else
++		dhd_napi_schedule_on(dhd, cpu);
++
++	put_online_cpus();
++}
++
++/**
++ * dhd_lb_rx_napi_dispatch - load balance by dispatching the rx_napi_struct
++ * to run on another CPU. The rx_napi_struct's poll function will retrieve all
++ * the packets enqueued into the rx_napi_queue and sendup.
++ * The producer's rx packet queue is appended to the rx_napi_queue before
++ * dispatching the rx_napi_struct.
++ */
++void
++dhd_lb_rx_napi_dispatch(dhd_pub_t *dhdp)
++{
++	unsigned long flags;
++	dhd_info_t *dhd = dhdp->info;
++	int curr_cpu;
++	int on_cpu;
++
++	if (dhd->rx_napi_netdev == NULL) {
++		DHD_ERROR(("%s: dhd->rx_napi_netdev is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	DHD_INFO(("%s append napi_queue<%d> pend_queue<%d>\n", __FUNCTION__,
++		skb_queue_len(&dhd->rx_napi_queue), skb_queue_len(&dhd->rx_pend_queue)));
++
++	/* append the producer's queue of packets to the napi's rx process queue */
++	spin_lock_irqsave(&dhd->rx_napi_queue.lock, flags);
++	skb_queue_splice_tail_init(&dhd->rx_pend_queue, &dhd->rx_napi_queue);
++	spin_unlock_irqrestore(&dhd->rx_napi_queue.lock, flags);
++
++	/*
++	 * If the destination CPU is NOT online or is same as current CPU
++	 * no need to schedule the work
++	 */
++	curr_cpu = get_cpu();
++	put_cpu();
++
++	on_cpu = atomic_read(&dhd->rx_napi_cpu);
++	if ((on_cpu == curr_cpu) || (!cpu_online(on_cpu))) {
++		dhd_napi_schedule(dhd);
++	} else {
++		schedule_work(&dhd->rx_napi_dispatcher_work);
++	}
++}
++
++/**
++ * dhd_lb_rx_pkt_enqueue - Enqueue the packet into the producer's queue
++ */
++void
++dhd_lb_rx_pkt_enqueue(dhd_pub_t *dhdp, void *pkt, int ifidx)
++{
++	dhd_info_t *dhd = dhdp->info;
++
++	DHD_INFO(("%s enqueue pkt<%p> ifidx<%d> pend_queue<%d>\n", __FUNCTION__,
++		pkt, ifidx, skb_queue_len(&dhd->rx_pend_queue)));
++	DHD_PKTTAG_SET_IFID((dhd_pkttag_fr_t *)PKTTAG(pkt), ifidx);
++	__skb_queue_tail(&dhd->rx_pend_queue, pkt);
++}
++#endif /* DHD_LB_RXP */
++
++#endif /* DHD_LB */
++
++
++/** Returns dhd iflist index corresponding the the bssidx provided by apps */
++int dhd_bssidx2idx(dhd_pub_t *dhdp, uint32 bssidx)
++{
++	dhd_if_t *ifp;
++	dhd_info_t *dhd = dhdp->info;
++	int i;
++
++	ASSERT(bssidx < DHD_MAX_IFS);
++	ASSERT(dhdp);
++
++	for (i = 0; i < DHD_MAX_IFS; i++) {
++		ifp = dhd->iflist[i];
++		if (ifp && (ifp->bssidx == bssidx)) {
++			DHD_TRACE(("Index manipulated for %s from %d to %d\n",
++				ifp->name, bssidx, i));
++			break;
++		}
++	}
++	return i;
++}
++
++static inline int dhd_rxf_enqueue(dhd_pub_t *dhdp, void* skb)
++{
++	uint32 store_idx;
++	uint32 sent_idx;
++
++	if (!skb) {
++		DHD_ERROR(("dhd_rxf_enqueue: NULL skb!!!\n"));
++		return BCME_ERROR;
++	}
++
++	dhd_os_rxflock(dhdp);
++	store_idx = dhdp->store_idx;
++	sent_idx = dhdp->sent_idx;
++	if (dhdp->skbbuf[store_idx] != NULL) {
++		/* Make sure the previous packets are processed */
++		dhd_os_rxfunlock(dhdp);
++#ifdef RXF_DEQUEUE_ON_BUSY
++		DHD_TRACE(("dhd_rxf_enqueue: pktbuf not consumed %p, store idx %d sent idx %d\n",
++			skb, store_idx, sent_idx));
++		return BCME_BUSY;
++#else /* RXF_DEQUEUE_ON_BUSY */
++		DHD_ERROR(("dhd_rxf_enqueue: pktbuf not consumed %p, store idx %d sent idx %d\n",
++			skb, store_idx, sent_idx));
++		/* removed msleep here, should use wait_event_timeout if we
++		 * want to give rx frame thread a chance to run
++		 */
++#if defined(WAIT_DEQUEUE)
++		OSL_SLEEP(1);
++#endif
++		return BCME_ERROR;
++#endif /* RXF_DEQUEUE_ON_BUSY */
++	}
++	DHD_TRACE(("dhd_rxf_enqueue: Store SKB %p. idx %d -> %d\n",
++		skb, store_idx, (store_idx + 1) & (MAXSKBPEND - 1)));
++	dhdp->skbbuf[store_idx] = skb;
++	dhdp->store_idx = (store_idx + 1) & (MAXSKBPEND - 1);
++	dhd_os_rxfunlock(dhdp);
++
++	return BCME_OK;
++}
++
++static inline void* dhd_rxf_dequeue(dhd_pub_t *dhdp)
++{
++	uint32 store_idx;
++	uint32 sent_idx;
++	void *skb;
++
++	dhd_os_rxflock(dhdp);
++
++	store_idx = dhdp->store_idx;
++	sent_idx = dhdp->sent_idx;
++	skb = dhdp->skbbuf[sent_idx];
++
++	if (skb == NULL) {
++		dhd_os_rxfunlock(dhdp);
++		DHD_ERROR(("dhd_rxf_dequeue: Dequeued packet is NULL, store idx %d sent idx %d\n",
++			store_idx, sent_idx));
++		return NULL;
++	}
++
++	dhdp->skbbuf[sent_idx] = NULL;
++	dhdp->sent_idx = (sent_idx + 1) & (MAXSKBPEND - 1);
++
++	DHD_TRACE(("dhd_rxf_dequeue: netif_rx_ni(%p), sent idx %d\n",
++		skb, sent_idx));
++
++	dhd_os_rxfunlock(dhdp);
++
++	return skb;
++}
++
++int dhd_process_cid_mac(dhd_pub_t *dhdp, bool prepost)
++{
++	if (prepost) { /* pre process */
++		dhd_read_cis(dhdp);
++		dhd_check_module_cid(dhdp);
++		dhd_check_module_mac(dhdp);
++		dhd_set_macaddr_from_file(dhdp);
++	} else { /* post process */
++		dhd_write_macaddr(&dhdp->mac);
++		dhd_clear_cis(dhdp);
++	}
++
++	return 0;
++}
++
++// terence 20160615: fix building error if ARP_OFFLOAD_SUPPORT removed
++#if defined(PKT_FILTER_SUPPORT)
++#if defined(ARP_OFFLOAD_SUPPORT) && !defined(GAN_LITE_NAT_KEEPALIVE_FILTER)
++static bool
++_turn_on_arp_filter(dhd_pub_t *dhd, int op_mode_param)
++{
++	bool _apply = FALSE;
++	/* In case of IBSS mode, apply arp pkt filter */
++	if (op_mode_param & DHD_FLAG_IBSS_MODE) {
++		_apply = TRUE;
++		goto exit;
++	}
++	/* In case of P2P GO or GC, apply pkt filter to pass arp pkt to host */
++	if (op_mode_param & (DHD_FLAG_P2P_GC_MODE | DHD_FLAG_P2P_GO_MODE)) {
++		_apply = TRUE;
++		goto exit;
++	}
++
++exit:
++	return _apply;
++}
++#endif /* !GAN_LITE_NAT_KEEPALIVE_FILTER */
++
++void
++dhd_set_packet_filter(dhd_pub_t *dhd)
++{
++	int i;
++
++	DHD_TRACE(("%s: enter\n", __FUNCTION__));
++	if (dhd_pkt_filter_enable) {
++		for (i = 0; i < dhd->pktfilter_count; i++) {
++			dhd_pktfilter_offload_set(dhd, dhd->pktfilter[i]);
++		}
++	}
++}
++
++void
++dhd_enable_packet_filter(int value, dhd_pub_t *dhd)
++{
++	int i;
++
++	DHD_ERROR(("%s: enter, value = %d\n", __FUNCTION__, value));
++	if ((dhd->op_mode & DHD_FLAG_HOSTAP_MODE) && value &&
++			!dhd_conf_get_insuspend(dhd, AP_FILTER_IN_SUSPEND)) {
++		DHD_ERROR(("%s: DHD_FLAG_HOSTAP_MODE\n", __FUNCTION__));
++		return;
++	}
++	/* 1 - Enable packet filter, only allow unicast packet to send up */
++	/* 0 - Disable packet filter */
++	if (dhd_pkt_filter_enable && (!value ||
++	    (dhd_support_sta_mode(dhd) && !dhd->dhcp_in_progress) ||
++	    dhd_conf_get_insuspend(dhd, AP_FILTER_IN_SUSPEND)))
++	{
++		for (i = 0; i < dhd->pktfilter_count; i++) {
++// terence 20160615: fix building error if ARP_OFFLOAD_SUPPORT removed
++#if defined(ARP_OFFLOAD_SUPPORT) && !defined(GAN_LITE_NAT_KEEPALIVE_FILTER)
++			if (value && (i == DHD_ARP_FILTER_NUM) &&
++				!_turn_on_arp_filter(dhd, dhd->op_mode)) {
++				DHD_TRACE(("Do not turn on ARP white list pkt filter:"
++					"val %d, cnt %d, op_mode 0x%x\n",
++					value, i, dhd->op_mode));
++				continue;
++			}
++#endif /* !GAN_LITE_NAT_KEEPALIVE_FILTER */
++			dhd_pktfilter_offload_enable(dhd, dhd->pktfilter[i],
++				value, dhd_master_mode);
++		}
++	}
++}
++
++int
++dhd_packet_filter_add_remove(dhd_pub_t *dhdp, int add_remove, int num)
++{
++	char *filterp = NULL;
++	int filter_id = 0;
++
++	switch (num) {
++		case DHD_BROADCAST_FILTER_NUM:
++			filterp = "101 0 0 0 0xFFFFFFFFFFFF 0xFFFFFFFFFFFF";
++			filter_id = 101;
++			break;
++		case DHD_MULTICAST4_FILTER_NUM:
++			filter_id = 102;
++			if (FW_SUPPORTED((dhdp), pf6)) {
++				if (dhdp->pktfilter[num] != NULL) {
++					dhd_pktfilter_offload_delete(dhdp, filter_id);
++					dhdp->pktfilter[num] = NULL;
++				}
++				if (!add_remove) {
++					filterp = DISCARD_IPV4_MCAST;
++					add_remove = 1;
++					break;
++				}
++			}
++			filterp = "102 0 0 0 0xFFFFFF 0x01005E";
++			break;
++		case DHD_MULTICAST6_FILTER_NUM:
++			filter_id = 103;
++			if (FW_SUPPORTED((dhdp), pf6)) {
++				if (dhdp->pktfilter[num] != NULL) {
++					dhd_pktfilter_offload_delete(dhdp, filter_id);
++					dhdp->pktfilter[num] = NULL;
++				}
++				if (!add_remove) {
++					filterp = DISCARD_IPV6_MCAST;
++					add_remove = 1;
++					break;
++				}
++			}
++			filterp = "103 0 0 0 0xFFFF 0x3333";
++			break;
++		case DHD_MDNS_FILTER_NUM:
++			filterp = "104 0 0 0 0xFFFFFFFFFFFF 0x01005E0000FB";
++			filter_id = 104;
++			break;
++		case DHD_ARP_FILTER_NUM:
++			filterp = "105 0 0 12 0xFFFF 0x0806";
++			filter_id = 105;
++			break;
++		case DHD_BROADCAST_ARP_FILTER_NUM:
++			filterp = "106 0 0 0 0xFFFFFFFFFFFF0000000000000806"
++				" 0xFFFFFFFFFFFF0000000000000806";
++			filter_id = 106;
++			break;
++		default:
++			return -EINVAL;
++	}
++
++	/* Add filter */
++	if (add_remove) {
++		dhdp->pktfilter[num] = filterp;
++		dhd_pktfilter_offload_set(dhdp, dhdp->pktfilter[num]);
++	} else { /* Delete filter */
++		if (dhdp->pktfilter[num]) {
++			dhd_pktfilter_offload_delete(dhdp, filter_id);
++			dhdp->pktfilter[num] = NULL;
++		}
++	}
++
++	return 0;
++}
++#endif /* PKT_FILTER_SUPPORT */
++
++static int dhd_set_suspend(int value, dhd_pub_t *dhd)
++{
++#ifndef SUPPORT_PM2_ONLY
++	int power_mode = PM_MAX;
++#endif /* SUPPORT_PM2_ONLY */
++#ifdef SUPPORT_SENSORHUB
++	shub_control_t shub_ctl;
++#endif /* SUPPORT_SENSORHUB */
++	/* wl_pkt_filter_enable_t	enable_parm; */
++	int bcn_li_dtim = 0; /* Default bcn_li_dtim in resume mode is 0 */
++	int ret = 0;
++#ifdef DHD_USE_EARLYSUSPEND
++#ifdef CUSTOM_BCN_TIMEOUT_IN_SUSPEND
++	int bcn_timeout = 0;
++#endif /* CUSTOM_BCN_TIMEOUT_IN_SUSPEND */
++#ifdef CUSTOM_ROAM_TIME_THRESH_IN_SUSPEND
++	int roam_time_thresh = 0;   /* (ms) */
++#endif /* CUSTOM_ROAM_TIME_THRESH_IN_SUSPEND */
++#ifndef ENABLE_FW_ROAM_SUSPEND
++	uint roamvar = 1;
++#endif /* ENABLE_FW_ROAM_SUSPEND */
++#ifdef ENABLE_BCN_LI_BCN_WAKEUP
++	int bcn_li_bcn;
++#endif /* ENABLE_BCN_LI_BCN_WAKEUP */
++	uint nd_ra_filter = 0;
++#endif /* DHD_USE_EARLYSUSPEND */
++#ifdef PASS_ALL_MCAST_PKTS
++	struct dhd_info *dhdinfo;
++	uint32 allmulti;
++	uint i;
++#endif /* PASS_ALL_MCAST_PKTS */
++#ifdef ENABLE_IPMCAST_FILTER
++	int ipmcast_l2filter;
++#endif /* ENABLE_IPMCAST_FILTER */
++#ifdef DYNAMIC_SWOOB_DURATION
++#ifndef CUSTOM_INTR_WIDTH
++#define CUSTOM_INTR_WIDTH 100
++	int intr_width = 0;
++#endif /* CUSTOM_INTR_WIDTH */
++#endif /* DYNAMIC_SWOOB_DURATION */
++
++#if defined(BCMPCIE)
++	int lpas = 0;
++	int dtim_period = 0;
++	int bcn_interval = 0;
++	int bcn_to_dly = 0;
++#ifndef CUSTOM_ROAM_TIME_THRESH_IN_SUSPEND
++	int bcn_timeout = CUSTOM_BCN_TIMEOUT_SETTING;
++#else
++	bcn_timeout = CUSTOM_BCN_TIMEOUT_SETTING;
++#endif /* CUSTOM_ROAM_TIME_THRESH_IN_SUSPEND */
++#endif /* OEM_ANDROID && BCMPCIE */
++
++	if (!dhd)
++		return -ENODEV;
++
++#ifdef PASS_ALL_MCAST_PKTS
++	dhdinfo = dhd->info;
++#endif /* PASS_ALL_MCAST_PKTS */
++
++	DHD_TRACE(("%s: enter, value = %d in_suspend=%d\n",
++		__FUNCTION__, value, dhd->in_suspend));
++
++	dhd_suspend_lock(dhd);
++
++#ifdef CUSTOM_SET_CPUCORE
++	DHD_TRACE(("%s set cpucore(suspend%d)\n", __FUNCTION__, value));
++	/* set specific cpucore */
++	dhd_set_cpucore(dhd, TRUE);
++#endif /* CUSTOM_SET_CPUCORE */
++	if (dhd->up) {
++		if (value && dhd->in_suspend) {
++#ifdef PKT_FILTER_SUPPORT
++			dhd->early_suspended = 1;
++#endif
++			/* Kernel suspended */
++			DHD_ERROR(("%s: force extra suspend setting\n", __FUNCTION__));
++
++#ifndef SUPPORT_PM2_ONLY
++			dhd_wl_ioctl_cmd(dhd, WLC_SET_PM, (char *)&power_mode,
++				sizeof(power_mode), TRUE, 0);
++#endif /* SUPPORT_PM2_ONLY */
++
++#ifdef PKT_FILTER_SUPPORT
++			/* Enable packet filter,
++			 * only allow unicast packet to send up
++			 */
++			dhd_enable_packet_filter(1, dhd);
++#ifdef APF
++			dhd_dev_apf_enable_filter(dhd_linux_get_primary_netdev(dhd));
++#endif /* APF */
++#endif /* PKT_FILTER_SUPPORT */
++
++#ifdef SUPPORT_SENSORHUB
++			shub_ctl.enable = 1;
++			shub_ctl.cmd = 0x000;
++			shub_ctl.op_mode = 1;
++			shub_ctl.interval = 0;
++			if (dhd->info->shub_enable == 1) {
++				ret = dhd_iovar(dhd, 0, "shub_msreq",
++					(char *)&shub_ctl, sizeof(shub_ctl), NULL, 0, TRUE);
++				if (ret < 0) {
++					DHD_ERROR(("%s SensorHub MS start: failed %d\n",
++						__FUNCTION__, ret));
++				}
++			}
++#endif /* SUPPORT_SENSORHUB */
++
++
++#ifdef PASS_ALL_MCAST_PKTS
++			allmulti = 0;
++			for (i = 0; i < DHD_MAX_IFS; i++) {
++				if (dhdinfo->iflist[i] && dhdinfo->iflist[i]->net)
++					dhd_iovar(dhd, i, "allmulti", (char *)&allmulti,
++							sizeof(allmulti), NULL, 0, TRUE);
++
++			}
++#endif /* PASS_ALL_MCAST_PKTS */
++
++			/* If DTIM skip is set up as default, force it to wake
++			 * each third DTIM for better power savings.  Note that
++			 * one side effect is a chance to miss BC/MC packet.
++			 */
++#ifdef WLTDLS
++			/* Do not set bcn_li_ditm on WFD mode */
++			if (dhd->tdls_mode) {
++				bcn_li_dtim = 0;
++			} else
++#endif /* WLTDLS */
++#if defined(BCMPCIE)
++			bcn_li_dtim = dhd_get_suspend_bcn_li_dtim(dhd, &dtim_period,
++				&bcn_interval);
++			dhd_iovar(dhd, 0, "bcn_li_dtim", (char *)&bcn_li_dtim,
++					sizeof(bcn_li_dtim), NULL, 0, TRUE);
++
++			if ((bcn_li_dtim * dtim_period * bcn_interval) >=
++				MIN_DTIM_FOR_ROAM_THRES_EXTEND) {
++				/*
++				 * Increase max roaming threshold from 2 secs to 8 secs
++				 * the real roam threshold is MIN(max_roam_threshold,
++				 * bcn_timeout/2)
++				 */
++				lpas = 1;
++				dhd_iovar(dhd, 0, "lpas", (char *)&lpas, sizeof(lpas), NULL,
++						0, TRUE);
++
++				bcn_to_dly = 1;
++				/*
++				 * if bcn_to_dly is 1, the real roam threshold is
++				 * MIN(max_roam_threshold, bcn_timeout -1);
++				 * notify link down event after roaming procedure complete
++				 * if we hit bcn_timeout while we are in roaming progress.
++				 */
++				dhd_iovar(dhd, 0, "bcn_to_dly", (char *)&bcn_to_dly,
++						sizeof(bcn_to_dly), NULL, 0, TRUE);
++				/* Increase beacon timeout to 6 secs or use bigger one */
++				bcn_timeout = max(bcn_timeout, BCN_TIMEOUT_IN_SUSPEND);
++				dhd_iovar(dhd, 0, "bcn_timeout", (char *)&bcn_timeout,
++						sizeof(bcn_timeout), NULL, 0, TRUE);
++			}
++#else
++			bcn_li_dtim = dhd_get_suspend_bcn_li_dtim(dhd);
++			if (dhd_iovar(dhd, 0, "bcn_li_dtim", (char *)&bcn_li_dtim,
++					sizeof(bcn_li_dtim), NULL, 0, TRUE) < 0)
++				DHD_ERROR(("%s: set dtim failed\n", __FUNCTION__));
++#endif /* OEM_ANDROID && BCMPCIE */
++
++#ifdef DHD_USE_EARLYSUSPEND
++#ifdef CUSTOM_BCN_TIMEOUT_IN_SUSPEND
++			bcn_timeout = CUSTOM_BCN_TIMEOUT_IN_SUSPEND;
++			dhd_iovar(dhd, 0, "bcn_timeout", (char *)&bcn_timeout,
++					sizeof(bcn_timeout), NULL, 0, TRUE);
++#endif /* CUSTOM_BCN_TIMEOUT_IN_SUSPEND */
++#ifdef CUSTOM_ROAM_TIME_THRESH_IN_SUSPEND
++			roam_time_thresh = CUSTOM_ROAM_TIME_THRESH_IN_SUSPEND;
++			dhd_iovar(dhd, 0, "roam_time_thresh", (char *)&roam_time_thresh,
++					sizeof(roam_time_thresh), NULL, 0, TRUE);
++#endif /* CUSTOM_ROAM_TIME_THRESH_IN_SUSPEND */
++#ifndef ENABLE_FW_ROAM_SUSPEND
++			/* Disable firmware roaming during suspend */
++			dhd_iovar(dhd, 0, "roam_off", (char *)&roamvar, sizeof(roamvar),
++					NULL, 0, TRUE);
++#endif /* ENABLE_FW_ROAM_SUSPEND */
++#ifdef ENABLE_BCN_LI_BCN_WAKEUP
++			bcn_li_bcn = 0;
++			dhd_iovar(dhd, 0, "bcn_li_bcn", (char *)&bcn_li_bcn,
++					sizeof(bcn_li_bcn), NULL, 0, TRUE);
++#endif /* ENABLE_BCN_LI_BCN_WAKEUP */
++#ifdef NDO_CONFIG_SUPPORT
++			if (dhd->ndo_enable) {
++				if (!dhd->ndo_host_ip_overflow) {
++					/* enable ND offload on suspend */
++					ret = dhd_ndo_enable(dhd, 1);
++					if (ret < 0) {
++						DHD_ERROR(("%s: failed to enable NDO\n",
++							__FUNCTION__));
++					}
++				} else {
++					DHD_INFO(("%s: NDO disabled on suspend due to"
++							"HW capacity\n", __FUNCTION__));
++				}
++			}
++#endif /* NDO_CONFIG_SUPPORT */
++#ifndef APF
++			if (FW_SUPPORTED(dhd, ndoe))
++#else
++			if (FW_SUPPORTED(dhd, ndoe) && !FW_SUPPORTED(dhd, apf))
++#endif /* APF */
++			{
++				/* enable IPv6 RA filter in  firmware during suspend */
++				nd_ra_filter = 1;
++				ret = dhd_iovar(dhd, 0, "nd_ra_filter_enable",
++						(char *)&nd_ra_filter, sizeof(nd_ra_filter),
++						NULL, 0, TRUE);
++				if (ret < 0)
++					DHD_ERROR(("failed to set nd_ra_filter (%d)\n",
++						ret));
++			}
++			dhd_os_suppress_logging(dhd, TRUE);
++#ifdef ENABLE_IPMCAST_FILTER
++			ipmcast_l2filter = 1;
++			ret = dhd_iovar(dhd, 0, "ipmcast_l2filter",
++					(char *)&ipmcast_l2filter, sizeof(ipmcast_l2filter),
++					NULL, 0, TRUE);
++#endif /* ENABLE_IPMCAST_FILTER */
++#ifdef DYNAMIC_SWOOB_DURATION
++			intr_width = CUSTOM_INTR_WIDTH;
++			ret = dhd_iovar(dhd, 0, "bus:intr_width", (char *)&intr_width,
++					sizeof(intr_width), NULL, 0, TRUE);
++			if (ret < 0) {
++				DHD_ERROR(("failed to set intr_width (%d)\n", ret));
++			}
++#endif /* DYNAMIC_SWOOB_DURATION */
++#endif /* DHD_USE_EARLYSUSPEND */
++		} else {
++#ifdef PKT_FILTER_SUPPORT
++			dhd->early_suspended = 0;
++#endif
++			/* Kernel resumed  */
++			DHD_ERROR(("%s: Remove extra suspend setting \n", __FUNCTION__));
++
++#ifdef SUPPORT_SENSORHUB
++			shub_ctl.enable = 1;
++			shub_ctl.cmd = 0x000;
++			shub_ctl.op_mode = 0;
++			shub_ctl.interval = 0;
++			if (dhd->info->shub_enable == 1) {
++				ret = dhd_iovar(dhd, 0, "shub_msreq",
++						(char *)&shub_ctl, sizeof(shub_ctl),
++						NULL, 0, TRUE);
++				if (ret < 0) {
++					DHD_ERROR(("%s SensorHub MS stop: failed %d\n",
++						__FUNCTION__, ret));
++				}
++			}
++#endif /* SUPPORT_SENSORHUB */
++
++#ifdef DYNAMIC_SWOOB_DURATION
++			intr_width = 0;
++			ret = dhd_iovar(dhd, 0, "bus:intr_width", (char *)&intr_width,
++					sizeof(intr_width), NULL, 0, TRUE);
++			if (ret < 0) {
++				DHD_ERROR(("failed to set intr_width (%d)\n", ret));
++			}
++#endif /* DYNAMIC_SWOOB_DURATION */
++#ifndef SUPPORT_PM2_ONLY
++			power_mode = PM_FAST;
++			dhd_wl_ioctl_cmd(dhd, WLC_SET_PM, (char *)&power_mode,
++				sizeof(power_mode), TRUE, 0);
++#endif /* SUPPORT_PM2_ONLY */
++#ifdef PKT_FILTER_SUPPORT
++			/* disable pkt filter */
++			dhd_enable_packet_filter(0, dhd);
++#ifdef APF
++			dhd_dev_apf_disable_filter(dhd_linux_get_primary_netdev(dhd));
++#endif /* APF */
++#endif /* PKT_FILTER_SUPPORT */
++#ifdef PASS_ALL_MCAST_PKTS
++			allmulti = 1;
++			for (i = 0; i < DHD_MAX_IFS; i++) {
++				if (dhdinfo->iflist[i] && dhdinfo->iflist[i]->net)
++					dhd_iovar(dhd, i, "allmulti", (char *)&allmulti,
++							sizeof(allmulti), NULL, 0, TRUE);
++			}
++#endif /* PASS_ALL_MCAST_PKTS */
++#if defined(BCMPCIE)
++			/* restore pre-suspend setting */
++			ret = dhd_iovar(dhd, 0, "bcn_li_dtim", (char *)&bcn_li_dtim,
++					sizeof(bcn_li_dtim), NULL, 0, TRUE);
++			if (ret < 0) {
++				DHD_ERROR(("%s:bcn_li_ditm fail:%d\n", __FUNCTION__, ret));
++			}
++
++			dhd_iovar(dhd, 0, "lpas", (char *)&lpas, sizeof(lpas), NULL, 0,
++					TRUE);
++
++			dhd_iovar(dhd, 0, "bcn_to_dly", (char *)&bcn_to_dly,
++					sizeof(bcn_to_dly), NULL, 0, TRUE);
++
++			dhd_iovar(dhd, 0, "bcn_timeout", (char *)&bcn_timeout,
++					sizeof(bcn_timeout), NULL, 0, TRUE);
++#else
++			/* restore pre-suspend setting for dtim_skip */
++			ret = dhd_iovar(dhd, 0, "bcn_li_dtim", (char *)&bcn_li_dtim,
++					sizeof(bcn_li_dtim), NULL, 0, TRUE);
++			if (ret < 0) {
++				DHD_ERROR(("%s:bcn_li_ditm fail:%d\n", __FUNCTION__, ret));
++			}
++#endif /* OEM_ANDROID && BCMPCIE */
++#ifdef DHD_USE_EARLYSUSPEND
++#ifdef CUSTOM_BCN_TIMEOUT_IN_SUSPEND
++			bcn_timeout = CUSTOM_BCN_TIMEOUT;
++			dhd_iovar(dhd, 0, "bcn_timeout", (char *)&bcn_timeout,
++					sizeof(bcn_timeout), NULL, 0, TRUE);
++#endif /* CUSTOM_BCN_TIMEOUT_IN_SUSPEND */
++#ifdef CUSTOM_ROAM_TIME_THRESH_IN_SUSPEND
++			roam_time_thresh = 2000;
++			dhd_iovar(dhd, 0, "roam_time_thresh", (char *)&roam_time_thresh,
++					sizeof(roam_time_thresh), NULL, 0, TRUE);
++
++#endif /* CUSTOM_ROAM_TIME_THRESH_IN_SUSPEND */
++#ifndef ENABLE_FW_ROAM_SUSPEND
++			roamvar = dhd_roam_disable;
++			dhd_iovar(dhd, 0, "roam_off", (char *)&roamvar, sizeof(roamvar),
++					NULL, 0, TRUE);
++#endif /* ENABLE_FW_ROAM_SUSPEND */
++#ifdef ENABLE_BCN_LI_BCN_WAKEUP
++			bcn_li_bcn = 1;
++			dhd_iovar(dhd, 0, "bcn_li_bcn", (char *)&bcn_li_bcn,
++					sizeof(bcn_li_bcn), NULL, 0, TRUE);
++#endif /* ENABLE_BCN_LI_BCN_WAKEUP */
++#ifdef NDO_CONFIG_SUPPORT
++			if (dhd->ndo_enable) {
++				/* Disable ND offload on resume */
++				ret = dhd_ndo_enable(dhd, 0);
++				if (ret < 0) {
++					DHD_ERROR(("%s: failed to disable NDO\n",
++						__FUNCTION__));
++				}
++			}
++#endif /* NDO_CONFIG_SUPPORT */
++#ifndef APF
++			if (FW_SUPPORTED(dhd, ndoe))
++#else
++			if (FW_SUPPORTED(dhd, ndoe) && !FW_SUPPORTED(dhd, apf))
++#endif /* APF */
++			{
++				/* disable IPv6 RA filter in  firmware during suspend */
++				nd_ra_filter = 0;
++				ret = dhd_iovar(dhd, 0, "nd_ra_filter_enable",
++						(char *)&nd_ra_filter, sizeof(nd_ra_filter),
++						NULL, 0, TRUE);
++				if (ret < 0) {
++					DHD_ERROR(("failed to set nd_ra_filter (%d)\n",
++						ret));
++				}
++			}
++			dhd_os_suppress_logging(dhd, FALSE);
++#ifdef ENABLE_IPMCAST_FILTER
++			ipmcast_l2filter = 0;
++			ret = dhd_iovar(dhd, 0, "ipmcast_l2filter",
++					(char *)&ipmcast_l2filter, sizeof(ipmcast_l2filter),
++					NULL, 0, TRUE);
++#endif /* ENABLE_IPMCAST_FILTER */
++#endif /* DHD_USE_EARLYSUSPEND */
++		}
++	}
++	dhd_suspend_unlock(dhd);
++
++	return 0;
++}
++
++static int dhd_suspend_resume_helper(struct dhd_info *dhd, int val, int force)
++{
++	dhd_pub_t *dhdp = &dhd->pub;
++	int ret = 0;
++
++	DHD_OS_WAKE_LOCK(dhdp);
++	DHD_PERIM_LOCK(dhdp);
++
++	/* Set flag when early suspend was called */
++	dhdp->in_suspend = val;
++	if ((force || !dhdp->suspend_disable_flag) &&
++		(dhd_support_sta_mode(dhdp) || dhd_conf_get_insuspend(dhdp, ALL_IN_SUSPEND)))
++	{
++		ret = dhd_set_suspend(val, dhdp);
++	}
++
++	DHD_PERIM_UNLOCK(dhdp);
++	DHD_OS_WAKE_UNLOCK(dhdp);
++	return ret;
++}
++
++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND)
++static void dhd_early_suspend(struct early_suspend *h)
++{
++	struct dhd_info *dhd = container_of(h, struct dhd_info, early_suspend);
++	DHD_TRACE_HW4(("%s: enter\n", __FUNCTION__));
++
++	if (dhd && dhd->pub.conf->suspend_mode == EARLY_SUSPEND) {
++		dhd_suspend_resume_helper(dhd, 1, 0);
++		dhd_conf_set_suspend_resume(&dhd->pub, 1);
++	}
++}
++
++static void dhd_late_resume(struct early_suspend *h)
++{
++	struct dhd_info *dhd = container_of(h, struct dhd_info, early_suspend);
++	DHD_TRACE_HW4(("%s: enter\n", __FUNCTION__));
++
++	if (dhd && dhd->pub.conf->suspend_mode == EARLY_SUSPEND) {
++		dhd_conf_set_suspend_resume(&dhd->pub, 0);
++		dhd_suspend_resume_helper(dhd, 0, 0);
++	}
++}
++#endif /* CONFIG_HAS_EARLYSUSPEND && DHD_USE_EARLYSUSPEND */
++
++/*
++ * Generalized timeout mechanism.  Uses spin sleep with exponential back-off until
++ * the sleep time reaches one jiffy, then switches over to task delay.  Usage:
++ *
++ *      dhd_timeout_start(&tmo, usec);
++ *      while (!dhd_timeout_expired(&tmo))
++ *              if (poll_something())
++ *                      break;
++ *      if (dhd_timeout_expired(&tmo))
++ *              fatal();
++ */
++
++void
++dhd_timeout_start(dhd_timeout_t *tmo, uint usec)
++{
++	tmo->limit = usec;
++	tmo->increment = 0;
++	tmo->elapsed = 0;
++	tmo->tick = jiffies_to_usecs(1);
++}
++
++int
++dhd_timeout_expired(dhd_timeout_t *tmo)
++{
++	/* Does nothing the first call */
++	if (tmo->increment == 0) {
++		tmo->increment = 1;
++		return 0;
++	}
++
++	if (tmo->elapsed >= tmo->limit)
++		return 1;
++
++	/* Add the delay that's about to take place */
++	tmo->elapsed += tmo->increment;
++
++	if ((!CAN_SLEEP()) || tmo->increment < tmo->tick) {
++		OSL_DELAY(tmo->increment);
++		tmo->increment *= 2;
++		if (tmo->increment > tmo->tick)
++			tmo->increment = tmo->tick;
++	} else {
++		wait_queue_head_t delay_wait;
++		DECLARE_WAITQUEUE(wait, current);
++		init_waitqueue_head(&delay_wait);
++		add_wait_queue(&delay_wait, &wait);
++		set_current_state(TASK_INTERRUPTIBLE);
++		(void)schedule_timeout(1);
++		remove_wait_queue(&delay_wait, &wait);
++		set_current_state(TASK_RUNNING);
++	}
++
++	return 0;
++}
++
++int
++dhd_net2idx(dhd_info_t *dhd, struct net_device *net)
++{
++	int i = 0;
++
++	if (!dhd) {
++		DHD_ERROR(("%s : DHD_BAD_IF return\n", __FUNCTION__));
++		return DHD_BAD_IF;
++	}
++
++	while (i < DHD_MAX_IFS) {
++		if (dhd->iflist[i] && dhd->iflist[i]->net && (dhd->iflist[i]->net == net))
++			return i;
++		i++;
++	}
++
++	return DHD_BAD_IF;
++}
++
++struct net_device * dhd_idx2net(void *pub, int ifidx)
++{
++	struct dhd_pub *dhd_pub = (struct dhd_pub *)pub;
++	struct dhd_info *dhd_info;
++
++	if (!dhd_pub || ifidx < 0 || ifidx >= DHD_MAX_IFS)
++		return NULL;
++	dhd_info = dhd_pub->info;
++	if (dhd_info && dhd_info->iflist[ifidx])
++		return dhd_info->iflist[ifidx]->net;
++	return NULL;
++}
++
++int
++dhd_ifname2idx(dhd_info_t *dhd, char *name)
++{
++	int i = DHD_MAX_IFS;
++
++	ASSERT(dhd);
++
++	if (name == NULL || *name == '\0')
++		return 0;
++
++	while (--i > 0)
++		if (dhd->iflist[i] && !strncmp(dhd->iflist[i]->dngl_name, name, IFNAMSIZ))
++				break;
++
++	DHD_TRACE(("%s: return idx %d for \"%s\"\n", __FUNCTION__, i, name));
++
++	return i;	/* default - the primary interface */
++}
++
++char *
++dhd_ifname(dhd_pub_t *dhdp, int ifidx)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++
++	ASSERT(dhd);
++
++	if (ifidx < 0 || ifidx >= DHD_MAX_IFS) {
++		DHD_ERROR(("%s: ifidx %d out of range\n", __FUNCTION__, ifidx));
++		return "<if_bad>";
++	}
++
++	if (dhd->iflist[ifidx] == NULL) {
++		DHD_ERROR(("%s: null i/f %d\n", __FUNCTION__, ifidx));
++		return "<if_null>";
++	}
++
++	if (dhd->iflist[ifidx]->net)
++		return dhd->iflist[ifidx]->net->name;
++
++	return "<if_none>";
++}
++
++uint8 *
++dhd_bssidx2bssid(dhd_pub_t *dhdp, int idx)
++{
++	int i;
++	dhd_info_t *dhd = (dhd_info_t *)dhdp;
++
++	ASSERT(dhd);
++	for (i = 0; i < DHD_MAX_IFS; i++)
++	if (dhd->iflist[i] && dhd->iflist[i]->bssidx == idx)
++		return dhd->iflist[i]->mac_addr;
++
++	return NULL;
++}
++
++
++static void
++_dhd_set_multicast_list(dhd_info_t *dhd, int ifidx)
++{
++	struct net_device *dev;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)
++	struct netdev_hw_addr *ha;
++#else
++	struct dev_mc_list *mclist;
++#endif
++	uint32 allmulti, cnt;
++
++	wl_ioctl_t ioc;
++	char *buf, *bufp;
++	uint buflen;
++	int ret;
++
++	if (!dhd->iflist[ifidx]) {
++		DHD_ERROR(("%s : dhd->iflist[%d] was NULL\n", __FUNCTION__, ifidx));
++		return;
++	}
++	dev = dhd->iflist[ifidx]->net;
++	if (!dev)
++		return;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++	netif_addr_lock_bh(dev);
++#endif /* LINUX >= 2.6.27 */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)
++	cnt = netdev_mc_count(dev);
++#else
++	cnt = dev->mc_count;
++#endif /* LINUX >= 2.6.35 */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++	netif_addr_unlock_bh(dev);
++#endif /* LINUX >= 2.6.27 */
++
++	/* Determine initial value of allmulti flag */
++	allmulti = (dev->flags & IFF_ALLMULTI) ? TRUE : FALSE;
++
++#ifdef PASS_ALL_MCAST_PKTS
++#ifdef PKT_FILTER_SUPPORT
++	if (!dhd->pub.early_suspended)
++#endif /* PKT_FILTER_SUPPORT */
++		allmulti = TRUE;
++#endif /* PASS_ALL_MCAST_PKTS */
++
++	/* Send down the multicast list first. */
++
++
++	buflen = sizeof("mcast_list") + sizeof(cnt) + (cnt * ETHER_ADDR_LEN);
++	if (!(bufp = buf = MALLOC(dhd->pub.osh, buflen))) {
++		DHD_ERROR(("%s: out of memory for mcast_list, cnt %d\n",
++		           dhd_ifname(&dhd->pub, ifidx), cnt));
++		return;
++	}
++
++	strncpy(bufp, "mcast_list", buflen - 1);
++	bufp[buflen - 1] = '\0';
++	bufp += strlen("mcast_list") + 1;
++
++	cnt = htol32(cnt);
++	memcpy(bufp, &cnt, sizeof(cnt));
++	bufp += sizeof(cnt);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++	netif_addr_lock_bh(dev);
++#endif /* LINUX >= 2.6.27 */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	netdev_for_each_mc_addr(ha, dev) {
++		if (!cnt)
++			break;
++		memcpy(bufp, ha->addr, ETHER_ADDR_LEN);
++		bufp += ETHER_ADDR_LEN;
++		cnt--;
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++#else /* LINUX < 2.6.35 */
++	for (mclist = dev->mc_list; (mclist && (cnt > 0));
++		cnt--, mclist = mclist->next) {
++		memcpy(bufp, (void *)mclist->dmi_addr, ETHER_ADDR_LEN);
++		bufp += ETHER_ADDR_LEN;
++	}
++#endif /* LINUX >= 2.6.35 */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++	netif_addr_unlock_bh(dev);
++#endif /* LINUX >= 2.6.27 */
++
++	memset(&ioc, 0, sizeof(ioc));
++	ioc.cmd = WLC_SET_VAR;
++	ioc.buf = buf;
++	ioc.len = buflen;
++	ioc.set = TRUE;
++
++	ret = dhd_wl_ioctl(&dhd->pub, ifidx, &ioc, ioc.buf, ioc.len);
++	if (ret < 0) {
++		DHD_ERROR(("%s: set mcast_list failed, cnt %d\n",
++			dhd_ifname(&dhd->pub, ifidx), cnt));
++		allmulti = cnt ? TRUE : allmulti;
++	}
++
++	MFREE(dhd->pub.osh, buf, buflen);
++
++	/* Now send the allmulti setting.  This is based on the setting in the
++	 * net_device flags, but might be modified above to be turned on if we
++	 * were trying to set some addresses and dongle rejected it...
++	 */
++
++	allmulti = htol32(allmulti);
++	ret = dhd_iovar(&dhd->pub, ifidx, "allmulti", (char *)&allmulti,
++			sizeof(allmulti), NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: set allmulti %d failed\n",
++		           dhd_ifname(&dhd->pub, ifidx), ltoh32(allmulti)));
++	}
++
++	/* Finally, pick up the PROMISC flag as well, like the NIC driver does */
++
++	allmulti = (dev->flags & IFF_PROMISC) ? TRUE : FALSE;
++
++	allmulti = htol32(allmulti);
++
++	memset(&ioc, 0, sizeof(ioc));
++	ioc.cmd = WLC_SET_PROMISC;
++	ioc.buf = &allmulti;
++	ioc.len = sizeof(allmulti);
++	ioc.set = TRUE;
++
++	ret = dhd_wl_ioctl(&dhd->pub, ifidx, &ioc, ioc.buf, ioc.len);
++	if (ret < 0) {
++		DHD_ERROR(("%s: set promisc %d failed\n",
++		           dhd_ifname(&dhd->pub, ifidx), ltoh32(allmulti)));
++	}
++}
++
++int
++_dhd_set_mac_address(dhd_info_t *dhd, int ifidx, uint8 *addr)
++{
++	int ret;
++
++	ret = dhd_iovar(&dhd->pub, ifidx, "cur_etheraddr", (char *)addr,
++			ETHER_ADDR_LEN, NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: set cur_etheraddr failed\n", dhd_ifname(&dhd->pub, ifidx)));
++	} else {
++		memcpy(dhd->iflist[ifidx]->net->dev_addr, addr, ETHER_ADDR_LEN);
++		if (ifidx == 0)
++			memcpy(dhd->pub.mac.octet, addr, ETHER_ADDR_LEN);
++	}
++
++	return ret;
++}
++
++#ifdef DHD_WMF
++void dhd_update_psta_interface_for_sta(dhd_pub_t* dhdp, char* ifname, void* ea,
++		void* event_data)
++{
++	struct wl_psta_primary_intf_event *psta_prim_event =
++			(struct wl_psta_primary_intf_event*)event_data;
++	dhd_sta_t *psta_interface =  NULL;
++	dhd_sta_t *sta = NULL;
++	uint8 ifindex;
++	ASSERT(ifname);
++	ASSERT(psta_prim_event);
++	ASSERT(ea);
++
++	ifindex = (uint8)dhd_ifname2idx(dhdp->info, ifname);
++	sta = dhd_find_sta(dhdp, ifindex, ea);
++	if (sta != NULL) {
++		psta_interface = dhd_find_sta(dhdp, ifindex,
++				(void *)(psta_prim_event->prim_ea.octet));
++		if (psta_interface != NULL) {
++			sta->psta_prim = psta_interface;
++		}
++	}
++}
++
++/* Get wmf_psta_disable configuration configuration */
++int dhd_get_wmf_psta_disable(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++	ASSERT(idx < DHD_MAX_IFS);
++	ifp = dhd->iflist[idx];
++	return ifp->wmf_psta_disable;
++}
++
++/* Set wmf_psta_disable configuration configuration */
++int dhd_set_wmf_psta_disable(dhd_pub_t *dhdp, uint32 idx, int val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++	ASSERT(idx < DHD_MAX_IFS);
++	ifp = dhd->iflist[idx];
++	ifp->wmf_psta_disable = val;
++	return 0;
++}
++#endif /* DHD_WMF */
++
++#ifdef DHD_PSTA
++/* Get psta/psr configuration configuration */
++int dhd_get_psta_mode(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++	return (int)dhd->psta_mode;
++}
++/* Set psta/psr configuration configuration */
++int dhd_set_psta_mode(dhd_pub_t *dhdp, uint32 val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd->psta_mode = val;
++	return 0;
++}
++#endif /* DHD_PSTA */
++
++#if (defined(DHD_WET) || defined(DHD_MCAST_REGEN) || defined(DHD_L2_FILTER))
++static void
++dhd_update_rx_pkt_chainable_state(dhd_pub_t* dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	if (
++#ifdef DHD_L2_FILTER
++		(ifp->block_ping) ||
++#endif
++#ifdef DHD_WET
++		(dhd->wet_mode) ||
++#endif
++#ifdef DHD_MCAST_REGEN
++		(ifp->mcast_regen_bss_enable) ||
++#endif
++		FALSE) {
++		ifp->rx_pkt_chainable = FALSE;
++	}
++}
++#endif /* DHD_WET || DHD_MCAST_REGEN || DHD_L2_FILTER */
++
++#ifdef DHD_WET
++/* Get wet configuration configuration */
++int dhd_get_wet_mode(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++	return (int)dhd->wet_mode;
++}
++
++/* Set wet configuration configuration */
++int dhd_set_wet_mode(dhd_pub_t *dhdp, uint32 val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd->wet_mode = val;
++	dhd_update_rx_pkt_chainable_state(dhdp, 0);
++	return 0;
++}
++#endif /* DHD_WET */
++
++#if defined(WL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++int32 dhd_role_to_nl80211_iftype(int32 role)
++{
++	switch (role) {
++	case WLC_E_IF_ROLE_STA:
++		return NL80211_IFTYPE_STATION;
++	case WLC_E_IF_ROLE_AP:
++		return NL80211_IFTYPE_AP;
++	case WLC_E_IF_ROLE_WDS:
++		return NL80211_IFTYPE_WDS;
++	case WLC_E_IF_ROLE_P2P_GO:
++		return NL80211_IFTYPE_P2P_GO;
++	case WLC_E_IF_ROLE_P2P_CLIENT:
++		return NL80211_IFTYPE_P2P_CLIENT;
++	case WLC_E_IF_ROLE_IBSS:
++	case WLC_E_IF_ROLE_NAN:
++		return NL80211_IFTYPE_ADHOC;
++	default:
++		return NL80211_IFTYPE_UNSPECIFIED;
++	}
++}
++#endif /* WL_CFG80211 && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++
++static void
++dhd_ifadd_event_handler(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++	dhd_if_event_t *if_event = event_info;
++	struct net_device *ndev;
++	int ifidx, bssidx;
++	int ret;
++#if defined(WL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	struct wl_if_event_info info;
++#endif /* WL_CFG80211 && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++
++	if (event != DHD_WQ_WORK_IF_ADD) {
++		DHD_ERROR(("%s: unexpected event \n", __FUNCTION__));
++		return;
++	}
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd info not available \n", __FUNCTION__));
++		return;
++	}
++
++	if (!if_event) {
++		DHD_ERROR(("%s: event data is null \n", __FUNCTION__));
++		return;
++	}
++
++	dhd_net_if_lock_local(dhd);
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK(&dhd->pub);
++
++	ifidx = if_event->event.ifidx;
++	bssidx = if_event->event.bssidx;
++	DHD_TRACE(("%s: registering if with ifidx %d\n", __FUNCTION__, ifidx));
++
++
++#if defined(WL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	if (if_event->event.ifidx > 0) {
++		bzero(&info, sizeof(info));
++		info.ifidx = if_event->event.ifidx;
++		info.bssidx = if_event->event.bssidx;
++		info.role = if_event->event.role;
++		strncpy(info.name, if_event->name, IFNAMSIZ);
++		if (wl_cfg80211_post_ifcreate(dhd->pub.info->iflist[0]->net,
++			&info, if_event->mac, NULL, true) != NULL) {
++			/* Do the post interface create ops */
++			DHD_ERROR(("Post ifcreate ops done. Returning \n"));
++			goto done;
++		}
++	}
++#endif /* WL_CFG80211 && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++
++	/* This path is for non-android case */
++	/* The interface name in host and in event msg are same */
++	/* if name in event msg is used to create dongle if list on host */
++	ndev = dhd_allocate_if(&dhd->pub, ifidx, if_event->name,
++		if_event->mac, bssidx, TRUE, if_event->name);
++	if (!ndev) {
++		DHD_ERROR(("%s: net device alloc failed  \n", __FUNCTION__));
++		goto done;
++	}
++
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	ret = dhd_register_if(&dhd->pub, ifidx, TRUE);
++	DHD_PERIM_LOCK(&dhd->pub);
++	if (ret != BCME_OK) {
++		DHD_ERROR(("%s: dhd_register_if failed\n", __FUNCTION__));
++		dhd_remove_if(&dhd->pub, ifidx, TRUE);
++		goto done;
++	}
++#ifndef PCIE_FULL_DONGLE
++	/* Turn on AP isolation in the firmware for interfaces operating in AP mode */
++	if (FW_SUPPORTED((&dhd->pub), ap) && (if_event->event.role != WLC_E_IF_ROLE_STA)) {
++		uint32 var_int =  1;
++		ret = dhd_iovar(&dhd->pub, ifidx, "ap_isolate", (char *)&var_int, sizeof(var_int),
++				NULL, 0, TRUE);
++		if (ret != BCME_OK) {
++			DHD_ERROR(("%s: Failed to set ap_isolate to dongle\n", __FUNCTION__));
++			dhd_remove_if(&dhd->pub, ifidx, TRUE);
++		}
++	}
++#endif /* PCIE_FULL_DONGLE */
++
++done:
++	MFREE(dhd->pub.osh, if_event, sizeof(dhd_if_event_t));
++
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++	dhd_net_if_unlock_local(dhd);
++}
++
++static void
++dhd_ifdel_event_handler(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++	int ifidx;
++	dhd_if_event_t *if_event = event_info;
++
++
++	if (event != DHD_WQ_WORK_IF_DEL) {
++		DHD_ERROR(("%s: unexpected event \n", __FUNCTION__));
++		return;
++	}
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd info not available \n", __FUNCTION__));
++		return;
++	}
++
++	if (!if_event) {
++		DHD_ERROR(("%s: event data is null \n", __FUNCTION__));
++		return;
++	}
++
++	dhd_net_if_lock_local(dhd);
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK(&dhd->pub);
++
++	ifidx = if_event->event.ifidx;
++	DHD_TRACE(("Removing interface with idx %d\n", ifidx));
++
++	DHD_PERIM_UNLOCK(&dhd->pub);
++#if defined(WL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	if (if_event->event.ifidx > 0) {
++		/* Do the post interface del ops */
++		if (wl_cfg80211_post_ifdel(dhd->pub.info->iflist[ifidx]->net, true) == 0) {
++			DHD_TRACE(("Post ifdel ops done. Returning \n"));
++			DHD_PERIM_LOCK(&dhd->pub);
++			goto done;
++		}
++	}
++#endif /* WL_CFG80211 && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++
++	dhd_remove_if(&dhd->pub, ifidx, TRUE);
++	DHD_PERIM_LOCK(&dhd->pub);
++
++#if defined(WL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++done:
++#endif /* WL_CFG80211 && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++	MFREE(dhd->pub.osh, if_event, sizeof(dhd_if_event_t));
++
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++	dhd_net_if_unlock_local(dhd);
++}
++
++#ifdef DHD_UPDATE_INTF_MAC
++static void
++dhd_ifupdate_event_handler(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++	int ifidx;
++	dhd_if_event_t *if_event = event_info;
++
++	if (event != DHD_WQ_WORK_IF_UPDATE) {
++		DHD_ERROR(("%s: unexpected event \n", __FUNCTION__));
++		return;
++	}
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd info not available \n", __FUNCTION__));
++		return;
++	}
++
++	if (!if_event) {
++		DHD_ERROR(("%s: event data is null \n", __FUNCTION__));
++		return;
++	}
++
++	dhd_net_if_lock_local(dhd);
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++
++	ifidx = if_event->event.ifidx;
++	DHD_TRACE(("%s: Update interface with idx %d\n", __FUNCTION__, ifidx));
++
++	dhd_op_if_update(&dhd->pub, ifidx);
++
++	MFREE(dhd->pub.osh, if_event, sizeof(dhd_if_event_t));
++
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++	dhd_net_if_unlock_local(dhd);
++}
++
++int dhd_op_if_update(dhd_pub_t *dhdpub, int ifidx)
++{
++	dhd_info_t *    dhdinfo = NULL;
++	dhd_if_t   *    ifp = NULL;
++	int             ret = 0;
++	char            buf[128];
++
++	if ((NULL==dhdpub)||(NULL==dhdpub->info)) {
++		DHD_ERROR(("%s: *** DHD handler is NULL!\n", __FUNCTION__));
++		return -1;
++	} else {
++		dhdinfo = (dhd_info_t *)dhdpub->info;
++		ifp = dhdinfo->iflist[ifidx];
++		if (NULL==ifp) {
++		    DHD_ERROR(("%s: *** ifp handler is NULL!\n", __FUNCTION__));
++		    return -2;
++		}
++	}
++
++	DHD_TRACE(("%s: idx %d\n", __FUNCTION__, ifidx));
++	// Get MAC address
++	strcpy(buf, "cur_etheraddr");
++	ret = dhd_wl_ioctl_cmd(&dhdinfo->pub, WLC_GET_VAR, buf, sizeof(buf), FALSE, ifp->idx);
++	if (0>ret) {
++		DHD_ERROR(("Failed to upudate the MAC address for itf=%s, ret=%d\n", ifp->name, ret));
++		// avoid collision
++		dhdinfo->iflist[ifp->idx]->mac_addr[5] += 1;
++		// force locally administrate address
++		ETHER_SET_LOCALADDR(&dhdinfo->iflist[ifp->idx]->mac_addr);
++	} else {
++		DHD_EVENT(("Got mac for itf %s, idx %d, MAC=%02X:%02X:%02X:%02X:%02X:%02X\n",
++		           ifp->name, ifp->idx,
++		           (unsigned char)buf[0], (unsigned char)buf[1], (unsigned char)buf[2],
++		           (unsigned char)buf[3], (unsigned char)buf[4], (unsigned char)buf[5]));
++		memcpy(dhdinfo->iflist[ifp->idx]->mac_addr, buf, ETHER_ADDR_LEN);
++		if (dhdinfo->iflist[ifp->idx]->net) {
++		    memcpy(dhdinfo->iflist[ifp->idx]->net->dev_addr, buf, ETHER_ADDR_LEN);
++		}
++	}
++
++	return ret;
++}
++#endif /* DHD_UPDATE_INTF_MAC */
++
++static void
++dhd_set_mac_addr_handler(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++	dhd_if_t *ifp = event_info;
++
++	if (event != DHD_WQ_WORK_SET_MAC) {
++		DHD_ERROR(("%s: unexpected event \n", __FUNCTION__));
++	}
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd info not available \n", __FUNCTION__));
++		return;
++	}
++
++	dhd_net_if_lock_local(dhd);
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK(&dhd->pub);
++
++	// terence 20160907: fix for not able to set mac when wlan0 is down
++	if (ifp == NULL || !ifp->set_macaddress) {
++		goto done;
++	}
++	if (ifp == NULL || !dhd->pub.up) {
++		DHD_ERROR(("%s: interface info not available/down \n", __FUNCTION__));
++		goto done;
++	}
++
++	DHD_ERROR(("%s: MACID is overwritten\n", __FUNCTION__));
++	ifp->set_macaddress = FALSE;
++	if (_dhd_set_mac_address(dhd, ifp->idx, ifp->mac_addr) == 0)
++		DHD_INFO(("%s: MACID is overwritten\n",	__FUNCTION__));
++	else
++		DHD_ERROR(("%s: _dhd_set_mac_address() failed\n", __FUNCTION__));
++
++done:
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++	dhd_net_if_unlock_local(dhd);
++}
++
++static void
++dhd_set_mcast_list_handler(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++	int ifidx = (int)((long int)event_info);
++	dhd_if_t *ifp = NULL;
++
++	if (event != DHD_WQ_WORK_SET_MCAST_LIST) {
++		DHD_ERROR(("%s: unexpected event \n", __FUNCTION__));
++		return;
++	}
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd info not available \n", __FUNCTION__));
++		return;
++	}
++
++	dhd_net_if_lock_local(dhd);
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK(&dhd->pub);
++
++	ifp = dhd->iflist[ifidx];
++
++	if (ifp == NULL || !dhd->pub.up) {
++		DHD_ERROR(("%s: interface info not available/down \n", __FUNCTION__));
++		goto done;
++	}
++
++	if (ifp == NULL || !dhd->pub.up) {
++		DHD_ERROR(("%s: interface info not available/down \n", __FUNCTION__));
++		goto done;
++	}
++
++	ifidx = ifp->idx;
++
++
++	_dhd_set_multicast_list(dhd, ifidx);
++	DHD_INFO(("%s: set multicast list for if %d\n", __FUNCTION__, ifidx));
++
++done:
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++	dhd_net_if_unlock_local(dhd);
++}
++
++static int
++dhd_set_mac_address(struct net_device *dev, void *addr)
++{
++	int ret = 0;
++
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	struct sockaddr *sa = (struct sockaddr *)addr;
++	int ifidx;
++	dhd_if_t *dhdif;
++
++	ifidx = dhd_net2idx(dhd, dev);
++	if (ifidx == DHD_BAD_IF)
++		return -1;
++
++	dhdif = dhd->iflist[ifidx];
++
++	dhd_net_if_lock_local(dhd);
++	memcpy(dhdif->mac_addr, sa->sa_data, ETHER_ADDR_LEN);
++	dhdif->set_macaddress = TRUE;
++	dhd_net_if_unlock_local(dhd);
++	dhd_deferred_schedule_work(dhd->dhd_deferred_wq, (void *)dhdif, DHD_WQ_WORK_SET_MAC,
++		dhd_set_mac_addr_handler, DHD_WQ_WORK_PRIORITY_LOW);
++	return ret;
++}
++
++static void
++dhd_set_multicast_list(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ifidx;
++
++	ifidx = dhd_net2idx(dhd, dev);
++	if (ifidx == DHD_BAD_IF)
++		return;
++
++	dhd->iflist[ifidx]->set_multicast = TRUE;
++	dhd_deferred_schedule_work(dhd->dhd_deferred_wq, (void *)((long int)ifidx),
++		DHD_WQ_WORK_SET_MCAST_LIST, dhd_set_mcast_list_handler, DHD_WQ_WORK_PRIORITY_LOW);
++
++	// terence 20160907: fix for not able to set mac when wlan0 is down
++	dhd_deferred_schedule_work(dhd->dhd_deferred_wq, (void *)dhd->iflist[ifidx],
++		DHD_WQ_WORK_SET_MAC, dhd_set_mac_addr_handler, DHD_WQ_WORK_PRIORITY_LOW);
++}
++
++#ifdef DHD_UCODE_DOWNLOAD
++/* Get ucode path */
++char *
++dhd_get_ucode_path(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++	return dhd->uc_path;
++}
++#endif /* DHD_UCODE_DOWNLOAD */
++
++#ifdef PROP_TXSTATUS
++int
++dhd_os_wlfc_block(dhd_pub_t *pub)
++{
++	dhd_info_t *di = (dhd_info_t *)(pub->info);
++	ASSERT(di != NULL);
++	/* terence 20161229: don't do spin lock if proptx not enabled */
++	if (disable_proptx)
++		return 1;
++#ifdef BCMDBUS
++	spin_lock_irqsave(&di->wlfc_spinlock, di->wlfc_lock_flags);
++#else
++	spin_lock_bh(&di->wlfc_spinlock);
++#endif /* BCMDBUS */
++	return 1;
++}
++
++int
++dhd_os_wlfc_unblock(dhd_pub_t *pub)
++{
++	dhd_info_t *di = (dhd_info_t *)(pub->info);
++
++	ASSERT(di != NULL);
++	/* terence 20161229: don't do spin lock if proptx not enabled */
++	if (disable_proptx)
++		return 1;
++#ifdef BCMDBUS
++	spin_unlock_irqrestore(&di->wlfc_spinlock, di->wlfc_lock_flags);
++#else
++	spin_unlock_bh(&di->wlfc_spinlock);
++#endif /* BCMDBUS */
++	return 1;
++}
++
++#endif /* PROP_TXSTATUS */
++
++#if defined(DHD_RX_DUMP) || defined(DHD_TX_DUMP)
++typedef struct {
++	uint16 type;
++	const char *str;
++} PKTTYPE_INFO;
++
++static const PKTTYPE_INFO packet_type_info[] =
++{
++	{ ETHER_TYPE_IP, "IP" },
++	{ ETHER_TYPE_ARP, "ARP" },
++	{ ETHER_TYPE_BRCM, "BRCM" },
++	{ ETHER_TYPE_802_1X, "802.1X" },
++	{ ETHER_TYPE_WAI, "WAPI" },
++	{ 0, ""}
++};
++
++static const char *_get_packet_type_str(uint16 type)
++{
++	int i;
++	int n = sizeof(packet_type_info)/sizeof(packet_type_info[1]) - 1;
++
++	for (i = 0; i < n; i++) {
++		if (packet_type_info[i].type == type)
++			return packet_type_info[i].str;
++	}
++
++	return packet_type_info[n].str;
++}
++
++void
++dhd_trx_dump(struct net_device *ndev, uint8 *dump_data, uint datalen, bool tx)
++{
++	uint16 protocol;
++	char *ifname;
++
++	protocol = (dump_data[12] << 8) | dump_data[13];
++	ifname = ndev ? ndev->name : "N/A";
++
++	if (protocol != ETHER_TYPE_BRCM) {
++		printk("[dhd-%s] %s DUMP - %s\n", ifname, tx?"Tx":"Rx",
++			_get_packet_type_str(protocol));
++#if defined(DHD_TX_FULL_DUMP) || defined(DHD_RX_FULL_DUMP)
++		prhex("Data", dump_data, datalen);
++#endif /* DHD_TX_FULL_DUMP || DHD_RX_FULL_DUMP */
++	}
++}
++#endif /* DHD_TX_DUMP || DHD_RX_DUMP */
++
++/*  This routine do not support Packet chain feature, Currently tested for
++ *  proxy arp feature
++ */
++int dhd_sendup(dhd_pub_t *dhdp, int ifidx, void *p)
++{
++	struct sk_buff *skb;
++	void *skbhead = NULL;
++	void *skbprev = NULL;
++	dhd_if_t *ifp;
++	ASSERT(!PKTISCHAINED(p));
++	skb = PKTTONATIVE(dhdp->osh, p);
++
++	ifp = dhdp->info->iflist[ifidx];
++	skb->dev = ifp->net;
++#if defined(BCM_GMAC3)
++	/* Forwarder capable interfaces use WOFA based forwarding */
++	if (ifp->fwdh) {
++		struct ether_header *eh = (struct ether_header *)PKTDATA(dhdp->osh, p);
++		uint16 * da = (uint16 *)(eh->ether_dhost);
++		uintptr_t wofa_data;
++		ASSERT(ISALIGNED(da, 2));
++
++		wofa_data = fwder_lookup(ifp->fwdh->mate, da, ifp->idx);
++		if (wofa_data == WOFA_DATA_INVALID) { /* Unknown MAC address */
++			if (fwder_transmit(ifp->fwdh, skb, 1, skb->dev) == FWDER_SUCCESS) {
++				return BCME_OK;
++			}
++		}
++		PKTFRMNATIVE(dhdp->osh, p);
++		PKTFREE(dhdp->osh, p, FALSE);
++		return BCME_OK;
++	}
++#endif /* BCM_GMAC3 */
++
++	skb->protocol = eth_type_trans(skb, skb->dev);
++
++	if (in_interrupt()) {
++		bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE,
++			__FUNCTION__, __LINE__);
++		netif_rx(skb);
++	} else {
++		if (dhdp->info->rxthread_enabled) {
++			if (!skbhead) {
++				skbhead = skb;
++			} else {
++				PKTSETNEXT(dhdp->osh, skbprev, skb);
++			}
++			skbprev = skb;
++		} else {
++			/* If the receive is not processed inside an ISR,
++			 * the softirqd must be woken explicitly to service
++			 * the NET_RX_SOFTIRQ.	In 2.6 kernels, this is handled
++			 * by netif_rx_ni(), but in earlier kernels, we need
++			 * to do it manually.
++			 */
++			bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE,
++				__FUNCTION__, __LINE__);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
++			netif_rx_ni(skb);
++#else
++			ulong flags;
++			netif_rx(skb);
++			local_irq_save(flags);
++			RAISE_RX_SOFTIRQ();
++			local_irq_restore(flags);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0) */
++		}
++	}
++
++	if (dhdp->info->rxthread_enabled && skbhead)
++		dhd_sched_rxf(dhdp, skbhead);
++
++	return BCME_OK;
++}
++
++int BCMFASTPATH
++__dhd_sendpkt(dhd_pub_t *dhdp, int ifidx, void *pktbuf)
++{
++	int ret = BCME_OK;
++	dhd_info_t *dhd = (dhd_info_t *)(dhdp->info);
++	struct ether_header *eh = NULL;
++#if defined(DHD_L2_FILTER)
++	dhd_if_t *ifp = dhd_get_ifp(dhdp, ifidx);
++#endif 
++
++	/* Reject if down */
++	if (!dhdp->up || (dhdp->busstate == DHD_BUS_DOWN)) {
++		/* free the packet here since the caller won't */
++		PKTCFREE(dhdp->osh, pktbuf, TRUE);
++		return -ENODEV;
++	}
++
++#ifdef PCIE_FULL_DONGLE
++	if (dhdp->busstate == DHD_BUS_SUSPEND) {
++		DHD_ERROR(("%s : pcie is still in suspend state!!\n", __FUNCTION__));
++		PKTCFREE(dhdp->osh, pktbuf, TRUE);
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20))
++		return -ENODEV;
++#else
++		return NETDEV_TX_BUSY;
++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20) */
++	}
++#endif /* PCIE_FULL_DONGLE */
++
++#ifdef DHD_L2_FILTER
++	/* if dhcp_unicast is enabled, we need to convert the */
++	/* broadcast DHCP ACK/REPLY packets to Unicast. */
++	if (ifp->dhcp_unicast) {
++	    uint8* mac_addr;
++	    uint8* ehptr = NULL;
++	    int ret;
++	    ret = bcm_l2_filter_get_mac_addr_dhcp_pkt(dhdp->osh, pktbuf, ifidx, &mac_addr);
++	    if (ret == BCME_OK) {
++		/*  if given mac address having valid entry in sta list
++		 *  copy the given mac address, and return with BCME_OK
++		*/
++		if (dhd_find_sta(dhdp, ifidx, mac_addr)) {
++		    ehptr = PKTDATA(dhdp->osh, pktbuf);
++		    bcopy(mac_addr, ehptr + ETHER_DEST_OFFSET, ETHER_ADDR_LEN);
++		}
++	    }
++	}
++
++	if (ifp->grat_arp && DHD_IF_ROLE_AP(dhdp, ifidx)) {
++	    if (bcm_l2_filter_gratuitous_arp(dhdp->osh, pktbuf) == BCME_OK) {
++			PKTCFREE(dhdp->osh, pktbuf, TRUE);
++			return BCME_ERROR;
++	    }
++	}
++
++	if (ifp->parp_enable && DHD_IF_ROLE_AP(dhdp, ifidx)) {
++		ret = dhd_l2_filter_pkt_handle(dhdp, ifidx, pktbuf, TRUE);
++
++		/* Drop the packets if l2 filter has processed it already
++		 * otherwise continue with the normal path
++		 */
++		if (ret == BCME_OK) {
++			PKTCFREE(dhdp->osh, pktbuf, TRUE);
++			return BCME_ERROR;
++		}
++	}
++#endif /* DHD_L2_FILTER */
++	/* Update multicast statistic */
++	if (PKTLEN(dhdp->osh, pktbuf) >= ETHER_HDR_LEN) {
++		uint8 *pktdata = (uint8 *)PKTDATA(dhdp->osh, pktbuf);
++		eh = (struct ether_header *)pktdata;
++
++		if (ETHER_ISMULTI(eh->ether_dhost))
++			dhdp->tx_multicast++;
++		if (ntoh16(eh->ether_type) == ETHER_TYPE_802_1X) {
++#ifdef DHD_LOSSLESS_ROAMING
++			uint8 prio = (uint8)PKTPRIO(pktbuf);
++
++			/* back up 802.1x's priority */
++			dhdp->prio_8021x = prio;
++#endif /* DHD_LOSSLESS_ROAMING */
++			DBG_EVENT_LOG(dhdp, WIFI_EVENT_DRIVER_EAPOL_FRAME_TRANSMIT_REQUESTED);
++			atomic_inc(&dhd->pend_8021x_cnt);
++			dhd_dump_eapol_4way_message(dhdp, dhd_ifname(dhdp, ifidx), pktdata, TRUE);
++		}
++
++		if (ntoh16(eh->ether_type) == ETHER_TYPE_IP) {
++#ifdef DHD_DHCP_DUMP
++			dhd_dhcp_dump(dhd_ifname(dhdp, ifidx), pktdata, TRUE);
++#endif /* DHD_DHCP_DUMP */
++#ifdef DHD_ICMP_DUMP
++			dhd_icmp_dump(dhd_ifname(dhdp, ifidx), pktdata, TRUE);
++#endif /* DHD_ICMP_DUMP */
++		}
++#ifdef DHD_ARP_DUMP
++		if (ntoh16(eh->ether_type) == ETHER_TYPE_ARP) {
++			dhd_arp_dump(dhd_ifname(dhdp, ifidx), pktdata, TRUE);
++		}
++#endif /* DHD_ARP_DUMP */
++	} else {
++			PKTCFREE(dhdp->osh, pktbuf, TRUE);
++			return BCME_ERROR;
++	}
++
++	{
++		/* Look into the packet and update the packet priority */
++#ifndef PKTPRIO_OVERRIDE
++		if (PKTPRIO(pktbuf) == 0)
++#endif /* !PKTPRIO_OVERRIDE */
++		{
++#if defined(QOS_MAP_SET)
++			pktsetprio_qms(pktbuf, wl_get_up_table(dhdp, ifidx), FALSE);
++#else
++			pktsetprio(pktbuf, FALSE);
++#endif /* QOS_MAP_SET */
++		}
++	}
++
++
++#if defined(TRAFFIC_MGMT_DWM)
++	traffic_mgmt_pkt_set_prio(dhdp, pktbuf);
++
++#ifdef BCM_GMAC3
++	DHD_PKT_SET_DATAOFF(pktbuf, 0);
++#endif /* BCM_GMAC3 */
++#endif 
++
++#ifdef PCIE_FULL_DONGLE
++	/*
++	 * Lkup the per interface hash table, for a matching flowring. If one is not
++	 * available, allocate a unique flowid and add a flowring entry.
++	 * The found or newly created flowid is placed into the pktbuf's tag.
++	 */
++	ret = dhd_flowid_update(dhdp, ifidx, dhdp->flow_prio_map[(PKTPRIO(pktbuf))], pktbuf);
++	if (ret != BCME_OK) {
++		PKTCFREE(dhd->pub.osh, pktbuf, TRUE);
++		return ret;
++	}
++#endif
++
++#if defined(DHD_TX_DUMP)
++	dhd_trx_dump(dhd_idx2net(dhdp, ifidx), PKTDATA(dhdp->osh, pktbuf),
++		PKTLEN(dhdp->osh, pktbuf), TRUE);
++#endif
++	/* terence 20150901: Micky add to ajust the 802.1X priority */
++	/* Set the 802.1X packet with the highest priority 7 */
++	if (dhdp->conf->pktprio8021x >= 0)
++		pktset8021xprio(pktbuf, dhdp->conf->pktprio8021x);
++
++#ifdef PROP_TXSTATUS
++	if (dhd_wlfc_is_supported(dhdp)) {
++		/* store the interface ID */
++		DHD_PKTTAG_SETIF(PKTTAG(pktbuf), ifidx);
++
++		/* store destination MAC in the tag as well */
++		DHD_PKTTAG_SETDSTN(PKTTAG(pktbuf), eh->ether_dhost);
++
++		/* decide which FIFO this packet belongs to */
++		if (ETHER_ISMULTI(eh->ether_dhost))
++			/* one additional queue index (highest AC + 1) is used for bc/mc queue */
++			DHD_PKTTAG_SETFIFO(PKTTAG(pktbuf), AC_COUNT);
++		else
++			DHD_PKTTAG_SETFIFO(PKTTAG(pktbuf), WME_PRIO2AC(PKTPRIO(pktbuf)));
++	} else
++#endif /* PROP_TXSTATUS */
++	{
++		/* If the protocol uses a data header, apply it */
++		dhd_prot_hdrpush(dhdp, ifidx, pktbuf);
++	}
++
++	/* Use bus module to send data frame */
++#ifdef WLMEDIA_HTSF
++	dhd_htsf_addtxts(dhdp, pktbuf);
++#endif
++#ifdef PROP_TXSTATUS
++	{
++		if (dhd_wlfc_commit_packets(dhdp, (f_commitpkt_t)dhd_bus_txdata,
++			dhdp->bus, pktbuf, TRUE) == WLFC_UNSUPPORTED) {
++			/* non-proptxstatus way */
++#ifdef BCMPCIE
++			ret = dhd_bus_txdata(dhdp->bus, pktbuf, (uint8)ifidx);
++#else
++			ret = dhd_bus_txdata(dhdp->bus, pktbuf);
++#endif /* BCMPCIE */
++		}
++	}
++#else
++#ifdef BCMPCIE
++	ret = dhd_bus_txdata(dhdp->bus, pktbuf, (uint8)ifidx);
++#else
++	ret = dhd_bus_txdata(dhdp->bus, pktbuf);
++#endif /* BCMPCIE */
++#endif /* PROP_TXSTATUS */
++#ifdef BCMDBUS
++	if (ret)
++		PKTCFREE(dhdp->osh, pktbuf, TRUE);
++#endif /* BCMDBUS */
++
++	return ret;
++}
++
++int BCMFASTPATH
++dhd_sendpkt(dhd_pub_t *dhdp, int ifidx, void *pktbuf)
++{
++	int ret = 0;
++	unsigned long flags;
++
++	DHD_GENERAL_LOCK(dhdp, flags);
++	if (DHD_BUS_CHECK_DOWN_OR_DOWN_IN_PROGRESS(dhdp)) {
++		DHD_ERROR(("%s: returning as busstate=%d\n",
++			__FUNCTION__, dhdp->busstate));
++		DHD_GENERAL_UNLOCK(dhdp, flags);
++		PKTCFREE(dhdp->osh, pktbuf, TRUE);
++		return -ENODEV;
++	}
++	DHD_BUS_BUSY_SET_IN_SEND_PKT(dhdp);
++	DHD_GENERAL_UNLOCK(dhdp, flags);
++
++#ifdef DHD_PCIE_RUNTIMEPM
++	if (dhdpcie_runtime_bus_wake(dhdp, FALSE, __builtin_return_address(0))) {
++		DHD_ERROR(("%s : pcie is still in suspend state!!\n", __FUNCTION__));
++		PKTCFREE(dhdp->osh, pktbuf, TRUE);
++		ret = -EBUSY;
++		goto exit;
++	}
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++	DHD_GENERAL_LOCK(dhdp, flags);
++	if (DHD_BUS_CHECK_SUSPEND_OR_SUSPEND_IN_PROGRESS(dhdp)) {
++		DHD_ERROR(("%s: bus is in suspend(%d) or suspending(0x%x) state!!\n",
++			__FUNCTION__, dhdp->busstate, dhdp->dhd_bus_busy_state));
++		DHD_BUS_BUSY_CLEAR_IN_SEND_PKT(dhdp);
++		dhd_os_busbusy_wake(dhdp);
++		DHD_GENERAL_UNLOCK(dhdp, flags);
++		PKTCFREE(dhdp->osh, pktbuf, TRUE);
++		return -ENODEV;
++	}
++	DHD_GENERAL_UNLOCK(dhdp, flags);
++
++	ret = __dhd_sendpkt(dhdp, ifidx, pktbuf);
++
++#ifdef DHD_PCIE_RUNTIMEPM
++exit:
++#endif
++	DHD_GENERAL_LOCK(dhdp, flags);
++	DHD_BUS_BUSY_CLEAR_IN_SEND_PKT(dhdp);
++	dhd_os_busbusy_wake(dhdp);
++	DHD_GENERAL_UNLOCK(dhdp, flags);
++	return ret;
++}
++
++#if defined(DHD_LB_TXP)
++
++int BCMFASTPATH
++dhd_lb_sendpkt(dhd_info_t *dhd, struct net_device *net,
++	int ifidx, void *skb)
++{
++	DHD_LB_STATS_PERCPU_ARR_INCR(dhd->tx_start_percpu_run_cnt);
++
++	/* If the feature is disabled run-time do TX from here */
++	if (atomic_read(&dhd->lb_txp_active) == 0) {
++		DHD_LB_STATS_PERCPU_ARR_INCR(dhd->txp_percpu_run_cnt);
++		 return __dhd_sendpkt(&dhd->pub, ifidx, skb);
++	}
++
++	/* Store the address of net device and interface index in the Packet tag */
++	DHD_LB_TX_PKTTAG_SET_NETDEV((dhd_tx_lb_pkttag_fr_t *)PKTTAG(skb), net);
++	DHD_LB_TX_PKTTAG_SET_IFIDX((dhd_tx_lb_pkttag_fr_t *)PKTTAG(skb), ifidx);
++
++	/* Enqueue the skb into tx_pend_queue */
++	skb_queue_tail(&dhd->tx_pend_queue, skb);
++
++	DHD_TRACE(("%s(): Added skb %p for netdev %p \r\n", __FUNCTION__, skb, net));
++
++	/* Dispatch the Tx job to be processed by the tx_tasklet */
++	dhd_lb_tx_dispatch(&dhd->pub);
++
++	return NETDEV_TX_OK;
++}
++#endif /* DHD_LB_TXP */
++
++int BCMFASTPATH
++dhd_start_xmit(struct sk_buff *skb, struct net_device *net)
++{
++	int ret;
++	uint datalen;
++	void *pktbuf;
++	dhd_info_t *dhd = DHD_DEV_INFO(net);
++	dhd_if_t *ifp = NULL;
++	int ifidx;
++	unsigned long flags;
++#ifdef WLMEDIA_HTSF
++	uint8 htsfdlystat_sz = dhd->pub.htsfdlystat_sz;
++#else
++	uint8 htsfdlystat_sz = 0;
++#endif 
++#ifdef DHD_WMF
++	struct ether_header *eh;
++	uint8 *iph;
++#endif /* DHD_WMF */
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (dhd_query_bus_erros(&dhd->pub)) {
++		return -ENODEV;
++	}
++
++	DHD_GENERAL_LOCK(&dhd->pub, flags);
++	DHD_BUS_BUSY_SET_IN_TX(&dhd->pub);
++	DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++
++#ifdef DHD_PCIE_RUNTIMEPM
++	if (dhdpcie_runtime_bus_wake(&dhd->pub, FALSE, dhd_start_xmit)) {
++		/* In order to avoid pkt loss. Return NETDEV_TX_BUSY until run-time resumed. */
++		/* stop the network queue temporarily until resume done */
++		DHD_GENERAL_LOCK(&dhd->pub, flags);
++		if (!dhdpcie_is_resume_done(&dhd->pub)) {
++			dhd_bus_stop_queue(dhd->pub.bus);
++		}
++		DHD_BUS_BUSY_CLEAR_IN_TX(&dhd->pub);
++		dhd_os_busbusy_wake(&dhd->pub);
++		DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20))
++		return -ENODEV;
++#else
++		return NETDEV_TX_BUSY;
++#endif
++	}
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++	DHD_GENERAL_LOCK(&dhd->pub, flags);
++#ifdef BCMPCIE
++	if (DHD_BUS_CHECK_SUSPEND_OR_SUSPEND_IN_PROGRESS(&dhd->pub)) {
++		DHD_ERROR(("%s: bus is in suspend(%d) or suspending(0x%x) state!!\n",
++			__FUNCTION__, dhd->pub.busstate, dhd->pub.dhd_bus_busy_state));
++		DHD_BUS_BUSY_CLEAR_IN_TX(&dhd->pub);
++#ifdef PCIE_FULL_DONGLE
++		/* Stop tx queues if suspend is in progress */
++		if (DHD_BUS_CHECK_ANY_SUSPEND_IN_PROGRESS(&dhd->pub)) {
++			dhd_bus_stop_queue(dhd->pub.bus);
++		}
++#endif /* PCIE_FULL_DONGLE */
++		dhd_os_busbusy_wake(&dhd->pub);
++		DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20))
++		return -ENODEV;
++#else
++		return NETDEV_TX_BUSY;
++#endif
++	}
++#else
++	if (DHD_BUS_CHECK_SUSPEND_OR_SUSPEND_IN_PROGRESS(&dhd->pub)) {
++		DHD_ERROR(("%s: bus is in suspend(%d) or suspending(0x%x) state!!\n",
++			__FUNCTION__, dhd->pub.busstate, dhd->pub.dhd_bus_busy_state));
++	}
++#endif
++
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK_TRY(DHD_FWDER_UNIT(dhd), lock_taken);
++
++
++#if defined(DHD_HANG_SEND_UP_TEST)
++	if (dhd->pub.req_hang_type == HANG_REASON_BUS_DOWN) {
++		dhd->pub.busstate = DHD_BUS_DOWN;
++	}
++#endif /* DHD_HANG_SEND_UP_TEST */
++
++	/* Reject if down */
++	if (dhd->pub.hang_was_sent || DHD_BUS_CHECK_DOWN_OR_DOWN_IN_PROGRESS(&dhd->pub)) {
++		DHD_ERROR(("%s: xmit rejected pub.up=%d busstate=%d \n",
++			__FUNCTION__, dhd->pub.up, dhd->pub.busstate));
++		netif_stop_queue(net);
++		/* Send Event when bus down detected during data session */
++		if (dhd->pub.up && !dhd->pub.hang_was_sent && !DHD_BUS_CHECK_REMOVE(&dhd->pub)) {
++			DHD_ERROR(("%s: Event HANG sent up\n", __FUNCTION__));
++			dhd->pub.hang_reason = HANG_REASON_BUS_DOWN;
++			net_os_send_hang_message(net);
++		}
++		DHD_BUS_BUSY_CLEAR_IN_TX(&dhd->pub);
++		dhd_os_busbusy_wake(&dhd->pub);
++		DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++		DHD_PERIM_UNLOCK_TRY(DHD_FWDER_UNIT(dhd), lock_taken);
++		DHD_OS_WAKE_UNLOCK(&dhd->pub);
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20))
++		return -ENODEV;
++#else
++		return NETDEV_TX_BUSY;
++#endif
++	}
++
++	ifp = DHD_DEV_IFP(net);
++	ifidx = DHD_DEV_IFIDX(net);
++	if (ifidx == DHD_BAD_IF) {
++		DHD_ERROR(("%s: bad ifidx %d\n", __FUNCTION__, ifidx));
++		netif_stop_queue(net);
++		DHD_BUS_BUSY_CLEAR_IN_TX(&dhd->pub);
++		dhd_os_busbusy_wake(&dhd->pub);
++		DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++		DHD_PERIM_UNLOCK_TRY(DHD_FWDER_UNIT(dhd), lock_taken);
++		DHD_OS_WAKE_UNLOCK(&dhd->pub);
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20))
++		return -ENODEV;
++#else
++		return NETDEV_TX_BUSY;
++#endif
++	}
++
++	DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++
++	ASSERT(ifidx == dhd_net2idx(dhd, net));
++	ASSERT((ifp != NULL) && ((ifidx < DHD_MAX_IFS) && (ifp == dhd->iflist[ifidx])));
++
++	bcm_object_trace_opr(skb, BCM_OBJDBG_ADD_PKT, __FUNCTION__, __LINE__);
++
++	/* re-align socket buffer if "skb->data" is odd address */
++	if (((unsigned long)(skb->data)) & 0x1) {
++		unsigned char *data = skb->data;
++		uint32 length = skb->len;
++		PKTPUSH(dhd->pub.osh, skb, 1);
++		memmove(skb->data, data, length);
++		PKTSETLEN(dhd->pub.osh, skb, length);
++	}
++
++	datalen  = PKTLEN(dhd->pub.osh, skb);
++
++	/* Make sure there's enough room for any header */
++	if (skb_headroom(skb) < dhd->pub.hdrlen + htsfdlystat_sz) {
++		struct sk_buff *skb2;
++
++		DHD_INFO(("%s: insufficient headroom\n",
++		          dhd_ifname(&dhd->pub, ifidx)));
++		dhd->pub.tx_realloc++;
++
++		bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE, __FUNCTION__, __LINE__);
++		skb2 = skb_realloc_headroom(skb, dhd->pub.hdrlen + htsfdlystat_sz);
++
++		dev_kfree_skb(skb);
++		if ((skb = skb2) == NULL) {
++			DHD_ERROR(("%s: skb_realloc_headroom failed\n",
++			           dhd_ifname(&dhd->pub, ifidx)));
++			ret = -ENOMEM;
++			goto done;
++		}
++		bcm_object_trace_opr(skb, BCM_OBJDBG_ADD_PKT, __FUNCTION__, __LINE__);
++	}
++
++	/* move from dhdsdio_sendfromq(), try to orphan skb early */
++	if (dhd->pub.conf->orphan_move == 2)
++		PKTORPHAN(skb, dhd->pub.conf->tsq);
++	else if (dhd->pub.conf->orphan_move == 3)
++		skb_orphan(skb);
++
++	/* Convert to packet */
++	if (!(pktbuf = PKTFRMNATIVE(dhd->pub.osh, skb))) {
++		DHD_ERROR(("%s: PKTFRMNATIVE failed\n",
++		           dhd_ifname(&dhd->pub, ifidx)));
++		bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE, __FUNCTION__, __LINE__);
++		dev_kfree_skb_any(skb);
++		ret = -ENOMEM;
++		goto done;
++	}
++
++#if defined(WLMEDIA_HTSF)
++	if (htsfdlystat_sz && PKTLEN(dhd->pub.osh, pktbuf) >= ETHER_ADDR_LEN) {
++		uint8 *pktdata = (uint8 *)PKTDATA(dhd->pub.osh, pktbuf);
++		struct ether_header *eh = (struct ether_header *)pktdata;
++
++		if (!ETHER_ISMULTI(eh->ether_dhost) &&
++			(ntoh16(eh->ether_type) == ETHER_TYPE_IP)) {
++			eh->ether_type = hton16(ETHER_TYPE_BRCM_PKTDLYSTATS);
++		}
++	}
++#endif 
++#ifdef DHD_WET
++	/* wet related packet proto manipulation should be done in DHD
++	   since dongle doesn't have complete payload
++	 */
++	if (WET_ENABLED(&dhd->pub) &&
++			(dhd_wet_send_proc(dhd->pub.wet_info, pktbuf, &pktbuf) < 0)) {
++		DHD_INFO(("%s:%s: wet send proc failed\n",
++				__FUNCTION__, dhd_ifname(&dhd->pub, ifidx)));
++		PKTFREE(dhd->pub.osh, pktbuf, FALSE);
++		ret =  -EFAULT;
++		goto done;
++	}
++#endif /* DHD_WET */
++
++#ifdef DHD_WMF
++	eh = (struct ether_header *)PKTDATA(dhd->pub.osh, pktbuf);
++	iph = (uint8 *)eh + ETHER_HDR_LEN;
++
++	/* WMF processing for multicast packets
++	 * Only IPv4 packets are handled
++	 */
++	if (ifp->wmf.wmf_enable && (ntoh16(eh->ether_type) == ETHER_TYPE_IP) &&
++		(IP_VER(iph) == IP_VER_4) && (ETHER_ISMULTI(eh->ether_dhost) ||
++		((IPV4_PROT(iph) == IP_PROT_IGMP) && dhd->pub.wmf_ucast_igmp))) {
++#if defined(DHD_IGMP_UCQUERY) || defined(DHD_UCAST_UPNP)
++		void *sdu_clone;
++		bool ucast_convert = FALSE;
++#ifdef DHD_UCAST_UPNP
++		uint32 dest_ip;
++
++		dest_ip = ntoh32(*((uint32 *)(iph + IPV4_DEST_IP_OFFSET)));
++		ucast_convert = dhd->pub.wmf_ucast_upnp && MCAST_ADDR_UPNP_SSDP(dest_ip);
++#endif /* DHD_UCAST_UPNP */
++#ifdef DHD_IGMP_UCQUERY
++		ucast_convert |= dhd->pub.wmf_ucast_igmp_query &&
++			(IPV4_PROT(iph) == IP_PROT_IGMP) &&
++			(*(iph + IPV4_HLEN(iph)) == IGMPV2_HOST_MEMBERSHIP_QUERY);
++#endif /* DHD_IGMP_UCQUERY */
++		if (ucast_convert) {
++			dhd_sta_t *sta;
++			unsigned long flags;
++			struct list_head snapshot_list;
++			struct list_head *wmf_ucforward_list;
++
++			ret = NETDEV_TX_OK;
++
++			/* For non BCM_GMAC3 platform we need a snapshot sta_list to
++			 * resolve double DHD_IF_STA_LIST_LOCK call deadlock issue.
++			 */
++			wmf_ucforward_list = DHD_IF_WMF_UCFORWARD_LOCK(dhd, ifp, &snapshot_list);
++
++			/* Convert upnp/igmp query to unicast for each assoc STA */
++			list_for_each_entry(sta, wmf_ucforward_list, list) {
++				/* Skip sending to proxy interfaces of proxySTA */
++				if (sta->psta_prim != NULL && !ifp->wmf_psta_disable) {
++					continue;
++				}
++				if ((sdu_clone = PKTDUP(dhd->pub.osh, pktbuf)) == NULL) {
++					ret = WMF_NOP;
++					break;
++				}
++				dhd_wmf_forward(ifp->wmf.wmfh, sdu_clone, 0, sta, 1);
++			}
++			DHD_IF_WMF_UCFORWARD_UNLOCK(dhd, wmf_ucforward_list);
++
++			DHD_GENERAL_LOCK(&dhd->pub, flags);
++			DHD_BUS_BUSY_CLEAR_IN_TX(&dhd->pub);
++			dhd_os_busbusy_wake(&dhd->pub);
++			DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++			DHD_PERIM_UNLOCK_TRY(DHD_FWDER_UNIT(dhd), lock_taken);
++			DHD_OS_WAKE_UNLOCK(&dhd->pub);
++
++			if (ret == NETDEV_TX_OK)
++				PKTFREE(dhd->pub.osh, pktbuf, TRUE);
++
++			return ret;
++		} else
++#endif /* defined(DHD_IGMP_UCQUERY) || defined(DHD_UCAST_UPNP) */
++		{
++			/* There will be no STA info if the packet is coming from LAN host
++			 * Pass as NULL
++			 */
++			ret = dhd_wmf_packets_handle(&dhd->pub, pktbuf, NULL, ifidx, 0);
++			switch (ret) {
++			case WMF_TAKEN:
++			case WMF_DROP:
++				/* Either taken by WMF or we should drop it.
++				 * Exiting send path
++				 */
++
++				DHD_GENERAL_LOCK(&dhd->pub, flags);
++				DHD_BUS_BUSY_CLEAR_IN_TX(&dhd->pub);
++				dhd_os_busbusy_wake(&dhd->pub);
++				DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++				DHD_PERIM_UNLOCK_TRY(DHD_FWDER_UNIT(dhd), lock_taken);
++				DHD_OS_WAKE_UNLOCK(&dhd->pub);
++				return NETDEV_TX_OK;
++			default:
++				/* Continue the transmit path */
++				break;
++			}
++		}
++	}
++#endif /* DHD_WMF */
++#ifdef DHD_PSTA
++	/* PSR related packet proto manipulation should be done in DHD
++	 * since dongle doesn't have complete payload
++	 */
++	if (PSR_ENABLED(&dhd->pub) && (dhd_psta_proc(&dhd->pub,
++		ifidx, &pktbuf, TRUE) < 0)) {
++			DHD_ERROR(("%s:%s: psta send proc failed\n", __FUNCTION__,
++				dhd_ifname(&dhd->pub, ifidx)));
++	}
++#endif /* DHD_PSTA */
++
++#ifdef DHDTCPACK_SUPPRESS
++	if (dhd->pub.tcpack_sup_mode == TCPACK_SUP_HOLD) {
++		/* If this packet has been hold or got freed, just return */
++		if (dhd_tcpack_hold(&dhd->pub, pktbuf, ifidx)) {
++			ret = 0;
++			goto done;
++		}
++	} else {
++		/* If this packet has replaced another packet and got freed, just return */
++		if (dhd_tcpack_suppress(&dhd->pub, pktbuf)) {
++			ret = 0;
++			goto done;
++		}
++	}
++#endif /* DHDTCPACK_SUPPRESS */
++
++	/*
++	 * If Load Balance is enabled queue the packet
++	 * else send directly from here.
++	 */
++#if defined(DHD_LB_TXP)
++	ret = dhd_lb_sendpkt(dhd, net, ifidx, pktbuf);
++#else
++	ret = __dhd_sendpkt(&dhd->pub, ifidx, pktbuf);
++#endif
++
++done:
++	if (ret) {
++		ifp->stats.tx_dropped++;
++		dhd->pub.tx_dropped++;
++	} else {
++#ifdef PROP_TXSTATUS
++		/* tx_packets counter can counted only when wlfc is disabled */
++		if (!dhd_wlfc_is_supported(&dhd->pub))
++#endif
++		{
++			dhd->pub.tx_packets++;
++			ifp->stats.tx_packets++;
++			ifp->stats.tx_bytes += datalen;
++		}
++	}
++
++
++	DHD_GENERAL_LOCK(&dhd->pub, flags);
++	DHD_BUS_BUSY_CLEAR_IN_TX(&dhd->pub);
++	dhd_os_busbusy_wake(&dhd->pub);
++	DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++	DHD_PERIM_UNLOCK_TRY(DHD_FWDER_UNIT(dhd), lock_taken);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++	/* Return ok: we always eat the packet */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20))
++	return 0;
++#else
++	return NETDEV_TX_OK;
++#endif
++}
++
++
++void
++dhd_txflowcontrol(dhd_pub_t *dhdp, int ifidx, bool state)
++{
++	struct net_device *net;
++	dhd_info_t *dhd = dhdp->info;
++	int i;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	ASSERT(dhd);
++
++#ifdef DHD_LOSSLESS_ROAMING
++	/* block flowcontrol during roaming */
++	if ((dhdp->dequeue_prec_map == 1 << PRIO_8021D_NC) && state == ON) {
++		return;
++	}
++#endif
++
++	if (ifidx == ALL_INTERFACES) {
++		/* Flow control on all active interfaces */
++		dhdp->txoff = state;
++		for (i = 0; i < DHD_MAX_IFS; i++) {
++			if (dhd->iflist[i]) {
++				net = dhd->iflist[i]->net;
++				if (state == ON)
++					netif_stop_queue(net);
++				else
++					netif_wake_queue(net);
++			}
++		}
++	} else {
++		if (dhd->iflist[ifidx]) {
++			net = dhd->iflist[ifidx]->net;
++			if (state == ON)
++				netif_stop_queue(net);
++			else
++				netif_wake_queue(net);
++		}
++	}
++}
++
++
++#ifdef DHD_WMF
++bool
++dhd_is_rxthread_enabled(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++
++	return dhd->rxthread_enabled;
++}
++#endif /* DHD_WMF */
++
++#ifdef DHD_MCAST_REGEN
++/*
++ * Description: This function is called to do the reverse translation
++ *
++ * Input    eh - pointer to the ethernet header
++ */
++int32
++dhd_mcast_reverse_translation(struct ether_header *eh)
++{
++	uint8 *iph;
++	uint32 dest_ip;
++
++	iph = (uint8 *)eh + ETHER_HDR_LEN;
++	dest_ip = ntoh32(*((uint32 *)(iph + IPV4_DEST_IP_OFFSET)));
++
++	/* Only IP packets are handled */
++	if (eh->ether_type != hton16(ETHER_TYPE_IP))
++		return BCME_ERROR;
++
++	/* Non-IPv4 multicast packets are not handled */
++	if (IP_VER(iph) != IP_VER_4)
++		return BCME_ERROR;
++
++	/*
++	 * The packet has a multicast IP and unicast MAC. That means
++	 * we have to do the reverse translation
++	 */
++	if (IPV4_ISMULTI(dest_ip) && !ETHER_ISMULTI(&eh->ether_dhost)) {
++		ETHER_FILL_MCAST_ADDR_FROM_IP(eh->ether_dhost, dest_ip);
++		return BCME_OK;
++	}
++
++	return BCME_ERROR;
++}
++#endif /* MCAST_REGEN */
++
++#ifdef SHOW_LOGTRACE
++static int
++dhd_event_logtrace_pkt_process(dhd_pub_t *dhdp, struct sk_buff * skb)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++	int ret = BCME_OK;
++	uint datalen;
++	bcm_event_msg_u_t evu;
++	void *data = NULL;
++	void *pktdata = NULL;
++	bcm_event_t *pvt_data;
++	uint pktlen;
++
++	DHD_TRACE(("%s:Enter\n", __FUNCTION__));
++
++	/* In dhd_rx_frame, header is stripped using skb_pull
++	 * of size ETH_HLEN, so adjust pktlen accordingly
++	 */
++	pktlen = skb->len + ETH_HLEN;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
++	pktdata = (void *)skb_mac_header(skb);
++#else
++	pktdata = (void *)skb->mac.raw;
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22) */
++
++	ret = wl_host_event_get_data(pktdata, pktlen, &evu);
++
++	if (ret != BCME_OK) {
++		DHD_ERROR(("%s: wl_host_event_get_data err = %d\n",
++			__FUNCTION__, ret));
++		goto exit;
++	}
++
++	datalen = ntoh32(evu.event.datalen);
++
++	pvt_data = (bcm_event_t *)pktdata;
++	data = &pvt_data[1];
++
++	dhd_dbg_trace_evnt_handler(dhdp, data, &dhd->event_data, datalen);
++
++exit:
++	return ret;
++}
++
++static void
++dhd_event_logtrace_process(struct work_struct * work)
++{
++/* Ignore compiler warnings due to -Werror=cast-qual */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	struct dhd_info *dhd =
++		container_of(work, struct dhd_info, event_log_dispatcher_work);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++	dhd_pub_t *dhdp;
++	struct sk_buff *skb;
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd info not available \n", __FUNCTION__));
++		return;
++	}
++
++	dhdp = &dhd->pub;
++
++	if (!dhdp) {
++		DHD_ERROR(("%s: dhd pub is null \n", __FUNCTION__));
++		return;
++	}
++
++	DHD_TRACE(("%s:Enter\n", __FUNCTION__));
++
++	/* Run while(1) loop till all skbs are dequeued */
++	while ((skb = skb_dequeue(&dhd->evt_trace_queue)) != NULL) {
++#ifdef PCIE_FULL_DONGLE
++		int ifid;
++		ifid = DHD_PKTTAG_IFID((dhd_pkttag_fr_t *)PKTTAG(skb));
++		if (ifid == DHD_EVENT_IF) {
++			dhd_event_logtrace_infobuf_pkt_process(dhdp, skb, &dhd->event_data);
++			/* For sending skb to network layer, convert it to Native PKT
++			 * after that assign skb->dev with Primary interface n/w device
++			 * as for infobuf events, we are sending special DHD_EVENT_IF
++			 */
++#ifdef DHD_USE_STATIC_CTRLBUF
++			PKTFREE_STATIC(dhdp->osh, skb, FALSE);
++#else
++			PKTFREE(dhdp->osh, skb, FALSE);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++			continue;
++		}
++		else {
++			dhd_event_logtrace_pkt_process(dhdp, skb);
++		}
++#else
++		dhd_event_logtrace_pkt_process(dhdp, skb);
++#endif /* PCIE_FULL_DONGLE */
++
++		/* Free skb buffer here if DHD_DONOT_FORWARD_BCMEVENT_AS_NETWORK_PKT
++		* macro is defined the Info Ring event and WLC_E_TRACE event is freed in DHD
++		* else it is always sent up to network layers.
++		*/
++#ifdef DHD_DONOT_FORWARD_BCMEVENT_AS_NETWORK_PKT
++#ifdef DHD_USE_STATIC_CTRLBUF
++		PKTFREE_STATIC(dhdp->osh, skb, FALSE);
++#else
++		PKTFREE(dhdp->osh, skb, FALSE);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++#else /* !DHD_DONOT_FORWARD_BCMEVENT_AS_NETWORK_PKT */
++		/* Do not call netif_recieve_skb as this workqueue scheduler is not from NAPI
++		 * Also as we are not in INTR context, do not call netif_rx, instead call
++		 * netif_rx_ni (for kerenl >= 2.6) which  does netif_rx, disables irq, raise
++		 * NET_IF_RX softirq and enables interrupts back
++		 */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
++		netif_rx_ni(skb);
++#else
++		{
++			ulong flags;
++			netif_rx(skb);
++			local_irq_save(flags);
++			RAISE_RX_SOFTIRQ();
++			local_irq_restore(flags);
++		}
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0) */
++#endif /* DHD_DONOT_FORWARD_BCMEVENT_AS_NETWORK_PKT */
++	}
++}
++
++void
++dhd_event_logtrace_enqueue(dhd_pub_t *dhdp, int ifidx, void *pktbuf)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++
++#ifdef PCIE_FULL_DONGLE
++	/* Add ifidx in the PKTTAG */
++	DHD_PKTTAG_SET_IFID((dhd_pkttag_fr_t *)PKTTAG(pktbuf), ifidx);
++#endif /* PCIE_FULL_DONGLE */
++	skb_queue_tail(&dhd->evt_trace_queue, pktbuf);
++
++	schedule_work(&dhd->event_log_dispatcher_work);
++}
++
++void
++dhd_event_logtrace_flush_queue(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++	struct sk_buff *skb;
++
++	while ((skb = skb_dequeue(&dhd->evt_trace_queue)) != NULL) {
++#ifdef DHD_USE_STATIC_CTRLBUF
++		PKTFREE_STATIC(dhdp->osh, skb, FALSE);
++#else
++		PKTFREE(dhdp->osh, skb, FALSE);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++	}
++}
++#endif /* SHOW_LOGTRACE */
++
++/** Called when a frame is received by the dongle on interface 'ifidx' */
++void
++dhd_rx_frame(dhd_pub_t *dhdp, int ifidx, void *pktbuf, int numpkt, uint8 chan)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++	struct sk_buff *skb;
++	uchar *eth;
++	uint len;
++	void *data, *pnext = NULL;
++	int i;
++	dhd_if_t *ifp;
++	wl_event_msg_t event;
++	int tout_rx = 0;
++	int tout_ctrl = 0;
++	void *skbhead = NULL;
++	void *skbprev = NULL;
++	uint16 protocol;
++	unsigned char *dump_data;
++#ifdef DHD_MCAST_REGEN
++	uint8 interface_role;
++	if_flow_lkup_t *if_flow_lkup;
++	unsigned long flags;
++#endif
++#ifdef DHD_WAKE_STATUS
++	int pkt_wake = 0;
++	wake_counts_t *wcp = NULL;
++#endif /* DHD_WAKE_STATUS */
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	for (i = 0; pktbuf && i < numpkt; i++, pktbuf = pnext) {
++		struct ether_header *eh;
++
++		pnext = PKTNEXT(dhdp->osh, pktbuf);
++		PKTSETNEXT(dhdp->osh, pktbuf, NULL);
++
++		/* info ring "debug" data, which is not a 802.3 frame, is sent/hacked with a
++		 * special ifidx of DHD_EVENT_IF.  This is just internal to dhd to get the data from
++		 * dhd_msgbuf.c:dhd_prot_infobuf_cmplt_process() to here (dhd_rx_frame).
++		 */
++		if (ifidx == DHD_EVENT_IF) {
++			/* Event msg printing is called from dhd_rx_frame which is in Tasklet
++			 * context in case of PCIe FD, in case of other bus this will be from
++			 * DPC context. If we get bunch of events from Dongle then printing all
++			 * of them from Tasklet/DPC context that too in data path is costly.
++			 * Also in the new Dongle SW(4359, 4355 onwards) console prints too come as
++			 * events with type WLC_E_TRACE.
++			 * We'll print this console logs from the WorkQueue context by enqueing SKB
++			 * here and Dequeuing will be done in WorkQueue and will be freed only if
++			 * DHD_DONOT_FORWARD_BCMEVENT_AS_NETWORK_PKT is defined
++			 */
++#ifdef SHOW_LOGTRACE
++			dhd_event_logtrace_enqueue(dhdp, ifidx, pktbuf);
++#else /* !SHOW_LOGTRACE */
++		/* If SHOW_LOGTRACE not defined and ifidx is DHD_EVENT_IF,
++		 * free the PKT here itself
++		 */
++#ifdef DHD_USE_STATIC_CTRLBUF
++		PKTFREE_STATIC(dhdp->osh, pktbuf, FALSE);
++#else
++		PKTFREE(dhdp->osh, pktbuf, FALSE);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++#endif /* SHOW_LOGTRACE */
++			continue;
++		}
++#ifdef DHD_WAKE_STATUS
++#ifdef BCMDBUS
++		wcp = NULL;
++#else
++		pkt_wake = dhd_bus_get_bus_wake(dhdp);
++		wcp = dhd_bus_get_wakecount(dhdp);
++#endif /* BCMDBUS */
++		if (wcp == NULL) {
++			/* If wakeinfo count buffer is null do not update wake count values */
++			pkt_wake = 0;
++		}
++#endif /* DHD_WAKE_STATUS */
++
++		ifp = dhd->iflist[ifidx];
++		if (ifp == NULL) {
++			DHD_ERROR(("%s: ifp is NULL. drop packet\n",
++				__FUNCTION__));
++			PKTCFREE(dhdp->osh, pktbuf, FALSE);
++			continue;
++		}
++
++		eh = (struct ether_header *)PKTDATA(dhdp->osh, pktbuf);
++
++		/* Dropping only data packets before registering net device to avoid kernel panic */
++#ifndef PROP_TXSTATUS_VSDB
++		if ((!ifp->net || ifp->net->reg_state != NETREG_REGISTERED) &&
++			(ntoh16(eh->ether_type) != ETHER_TYPE_BRCM))
++#else
++		if ((!ifp->net || ifp->net->reg_state != NETREG_REGISTERED || !dhd->pub.up) &&
++			(ntoh16(eh->ether_type) != ETHER_TYPE_BRCM))
++#endif /* PROP_TXSTATUS_VSDB */
++		{
++			DHD_ERROR(("%s: net device is NOT registered yet. drop packet\n",
++			__FUNCTION__));
++			PKTCFREE(dhdp->osh, pktbuf, FALSE);
++			continue;
++		}
++
++#ifdef PROP_TXSTATUS
++		if (dhd_wlfc_is_header_only_pkt(dhdp, pktbuf)) {
++			/* WLFC may send header only packet when
++			there is an urgent message but no packet to
++			piggy-back on
++			*/
++			PKTCFREE(dhdp->osh, pktbuf, FALSE);
++			continue;
++		}
++#endif
++#ifdef DHD_L2_FILTER
++		/* If block_ping is enabled drop the ping packet */
++		if (ifp->block_ping) {
++			if (bcm_l2_filter_block_ping(dhdp->osh, pktbuf) == BCME_OK) {
++				PKTCFREE(dhdp->osh, pktbuf, FALSE);
++				continue;
++			}
++		}
++		if (ifp->grat_arp && DHD_IF_ROLE_STA(dhdp, ifidx)) {
++		    if (bcm_l2_filter_gratuitous_arp(dhdp->osh, pktbuf) == BCME_OK) {
++				PKTCFREE(dhdp->osh, pktbuf, FALSE);
++				continue;
++		    }
++		}
++		if (ifp->parp_enable && DHD_IF_ROLE_AP(dhdp, ifidx)) {
++			int ret = dhd_l2_filter_pkt_handle(dhdp, ifidx, pktbuf, FALSE);
++
++			/* Drop the packets if l2 filter has processed it already
++			 * otherwise continue with the normal path
++			 */
++			if (ret == BCME_OK) {
++				PKTCFREE(dhdp->osh, pktbuf, TRUE);
++				continue;
++			}
++		}
++#endif /* DHD_L2_FILTER */
++
++#ifdef DHD_MCAST_REGEN
++		DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++		if_flow_lkup = (if_flow_lkup_t *)dhdp->if_flow_lkup;
++		ASSERT(if_flow_lkup);
++
++		interface_role = if_flow_lkup[ifidx].role;
++		DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++
++		if (ifp->mcast_regen_bss_enable && (interface_role != WLC_E_IF_ROLE_WDS) &&
++				!DHD_IF_ROLE_AP(dhdp, ifidx) &&
++				ETHER_ISUCAST(eh->ether_dhost)) {
++			if (dhd_mcast_reverse_translation(eh) ==  BCME_OK) {
++#ifdef DHD_PSTA
++				/* Change bsscfg to primary bsscfg for unicast-multicast packets */
++				if ((dhd_get_psta_mode(dhdp) == DHD_MODE_PSTA) ||
++						(dhd_get_psta_mode(dhdp) == DHD_MODE_PSR)) {
++					if (ifidx != 0) {
++						/* Let the primary in PSTA interface handle this
++						 * frame after unicast to Multicast conversion
++						 */
++						ifp = dhd_get_ifp(dhdp, 0);
++						ASSERT(ifp);
++					}
++				}
++			}
++#endif /* PSTA */
++		}
++#endif /* MCAST_REGEN */
++
++#ifdef DHD_WMF
++		/* WMF processing for multicast packets */
++		if (ifp->wmf.wmf_enable && (ETHER_ISMULTI(eh->ether_dhost))) {
++			dhd_sta_t *sta;
++			int ret;
++
++			sta = dhd_find_sta(dhdp, ifidx, (void *)eh->ether_shost);
++			ret = dhd_wmf_packets_handle(dhdp, pktbuf, sta, ifidx, 1);
++			switch (ret) {
++				case WMF_TAKEN:
++					/* The packet is taken by WMF. Continue to next iteration */
++					continue;
++				case WMF_DROP:
++					/* Packet DROP decision by WMF. Toss it */
++					DHD_ERROR(("%s: WMF decides to drop packet\n",
++						__FUNCTION__));
++					PKTCFREE(dhdp->osh, pktbuf, FALSE);
++					continue;
++				default:
++					/* Continue the transmit path */
++					break;
++			}
++		}
++#endif /* DHD_WMF */
++
++#ifdef DHDTCPACK_SUPPRESS
++		dhd_tcpdata_info_get(dhdp, pktbuf);
++#endif
++		skb = PKTTONATIVE(dhdp->osh, pktbuf);
++
++		ASSERT(ifp);
++		skb->dev = ifp->net;
++#ifdef DHD_WET
++		/* wet related packet proto manipulation should be done in DHD
++		 * since dongle doesn't have complete payload
++		 */
++		if (WET_ENABLED(&dhd->pub) && (dhd_wet_recv_proc(dhd->pub.wet_info,
++				pktbuf) < 0)) {
++			DHD_INFO(("%s:%s: wet recv proc failed\n",
++				__FUNCTION__, dhd_ifname(dhdp, ifidx)));
++		}
++#endif /* DHD_WET */
++
++#ifdef DHD_PSTA
++		if (PSR_ENABLED(dhdp) && (dhd_psta_proc(dhdp, ifidx, &pktbuf, FALSE) < 0)) {
++				DHD_ERROR(("%s:%s: psta recv proc failed\n", __FUNCTION__,
++					dhd_ifname(dhdp, ifidx)));
++		}
++#endif /* DHD_PSTA */
++
++#ifdef PCIE_FULL_DONGLE
++		if ((DHD_IF_ROLE_AP(dhdp, ifidx) || DHD_IF_ROLE_P2PGO(dhdp, ifidx)) &&
++			(!ifp->ap_isolate)) {
++			eh = (struct ether_header *)PKTDATA(dhdp->osh, pktbuf);
++			if (ETHER_ISUCAST(eh->ether_dhost)) {
++				if (dhd_find_sta(dhdp, ifidx, (void *)eh->ether_dhost)) {
++					dhd_sendpkt(dhdp, ifidx, pktbuf);
++					continue;
++				}
++			} else {
++				void *npktbuf = PKTDUP(dhdp->osh, pktbuf);
++				if (npktbuf)
++					dhd_sendpkt(dhdp, ifidx, npktbuf);
++			}
++		}
++#endif /* PCIE_FULL_DONGLE */
++
++		/* Get the protocol, maintain skb around eth_type_trans()
++		 * The main reason for this hack is for the limitation of
++		 * Linux 2.4 where 'eth_type_trans' uses the 'net->hard_header_len'
++		 * to perform skb_pull inside vs ETH_HLEN. Since to avoid
++		 * coping of the packet coming from the network stack to add
++		 * BDC, Hardware header etc, during network interface registration
++		 * we set the 'net->hard_header_len' to ETH_HLEN + extra space required
++		 * for BDC, Hardware header etc. and not just the ETH_HLEN
++		 */
++		eth = skb->data;
++		len = skb->len;
++
++		dump_data = skb->data;
++
++		protocol = (skb->data[12] << 8) | skb->data[13];
++		if (protocol == ETHER_TYPE_802_1X) {
++			DBG_EVENT_LOG(dhdp, WIFI_EVENT_DRIVER_EAPOL_FRAME_RECEIVED);
++			dhd_dump_eapol_4way_message(dhdp, dhd_ifname(dhdp, ifidx), dump_data, FALSE);
++		}
++
++		if (protocol != ETHER_TYPE_BRCM && protocol == ETHER_TYPE_IP) {
++#ifdef DHD_DHCP_DUMP
++			dhd_dhcp_dump(dhd_ifname(dhdp, ifidx), dump_data, FALSE);
++#endif /* DHD_DHCP_DUMP */
++#ifdef DHD_ICMP_DUMP
++			dhd_icmp_dump(dhd_ifname(dhdp, ifidx), dump_data, FALSE);
++#endif /* DHD_ICMP_DUMP */
++		}
++#ifdef DHD_ARP_DUMP
++		if (ntoh16(eh->ether_type) == ETHER_TYPE_ARP) {
++			dhd_arp_dump(dhd_ifname(dhdp, ifidx), dump_data, FALSE);
++		}
++#endif /* DHD_ARP_DUMP */
++#ifdef DHD_RX_DUMP
++		dhd_trx_dump(dhd_idx2net(dhdp, ifidx), dump_data, skb->len, FALSE);
++#endif /* DHD_RX_DUMP */
++#if defined(DHD_WAKE_STATUS) && defined(DHD_WAKEPKT_DUMP)
++		if (pkt_wake) {
++			prhex("[wakepkt_dump]", (char*)dump_data, MIN(len, 32));
++		}
++#endif /* DHD_WAKE_STATUS && DHD_WAKEPKT_DUMP */
++
++		skb->protocol = eth_type_trans(skb, skb->dev);
++
++		if (skb->pkt_type == PACKET_MULTICAST) {
++			dhd->pub.rx_multicast++;
++			ifp->stats.multicast++;
++		}
++
++		skb->data = eth;
++		skb->len = len;
++
++#ifdef WLMEDIA_HTSF
++		dhd_htsf_addrxts(dhdp, pktbuf);
++#endif
++#ifdef DBG_PKT_MON
++		DHD_DBG_PKT_MON_RX(dhdp, skb);
++#endif /* DBG_PKT_MON */
++#ifdef DHD_PKT_LOGGING
++		DHD_PKTLOG_RX(dhdp, skb);
++#endif /* DHD_PKT_LOGGING */
++		/* Strip header, count, deliver upward */
++		skb_pull(skb, ETH_HLEN);
++
++		/* Process special event packets and then discard them */
++		memset(&event, 0, sizeof(event));
++
++		if (ntoh16(skb->protocol) == ETHER_TYPE_BRCM) {
++			bcm_event_msg_u_t evu;
++			int ret_event;
++			int event_type;
++
++			ret_event = wl_host_event_get_data(
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
++			skb_mac_header(skb),
++#else
++			skb->mac.raw,
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22) */
++			len, &evu);
++
++			if (ret_event != BCME_OK) {
++				DHD_ERROR(("%s: wl_host_event_get_data err = %d\n",
++					__FUNCTION__, ret_event));
++#ifdef DHD_USE_STATIC_CTRLBUF
++				PKTFREE_STATIC(dhdp->osh, pktbuf, FALSE);
++#else
++				PKTFREE(dhdp->osh, pktbuf, FALSE);
++#endif
++				continue;
++			}
++
++			memcpy(&event, &evu.event, sizeof(wl_event_msg_t));
++			event_type = ntoh32_ua((void *)&event.event_type);
++#ifdef SHOW_LOGTRACE
++			/* Event msg printing is called from dhd_rx_frame which is in Tasklet
++			 * context in case of PCIe FD, in case of other bus this will be from
++			 * DPC context. If we get bunch of events from Dongle then printing all
++			 * of them from Tasklet/DPC context that too in data path is costly.
++			 * Also in the new Dongle SW(4359, 4355 onwards) console prints too come as
++			 * events with type WLC_E_TRACE.
++			 * We'll print this console logs from the WorkQueue context by enqueing SKB
++			 * here and Dequeuing will be done in WorkQueue and will be freed only if
++			 * DHD_DONOT_FORWARD_BCMEVENT_AS_NETWORK_PKT is defined
++			 */
++			if (event_type == WLC_E_TRACE) {
++				DHD_TRACE(("%s: WLC_E_TRACE\n", __FUNCTION__));
++				dhd_event_logtrace_enqueue(dhdp, ifidx, pktbuf);
++				continue;
++			}
++#endif /* SHOW_LOGTRACE */
++
++			ret_event = dhd_wl_host_event(dhd, ifidx,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
++			skb_mac_header(skb),
++#else
++			skb->mac.raw,
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22) */
++			len, &event, &data);
++
++			wl_event_to_host_order(&event);
++			if (!tout_ctrl)
++				tout_ctrl = DHD_PACKET_TIMEOUT_MS;
++
++#if defined(PNO_SUPPORT)
++			if (event_type == WLC_E_PFN_NET_FOUND) {
++				/* enforce custom wake lock to garantee that Kernel not suspended */
++				tout_ctrl = CUSTOM_PNO_EVENT_LOCK_xTIME * DHD_PACKET_TIMEOUT_MS;
++			}
++#endif /* PNO_SUPPORT */
++			if (numpkt != 1) {
++				DHD_TRACE(("%s: Got BRCM event packet in a chained packet.\n",
++				__FUNCTION__));
++			}
++
++#ifdef DHD_WAKE_STATUS
++			if (unlikely(pkt_wake)) {
++#ifdef DHD_WAKE_EVENT_STATUS
++				if (event.event_type < WLC_E_LAST) {
++					wcp->rc_event[event.event_type]++;
++					wcp->rcwake++;
++					pkt_wake = 0;
++				}
++#endif /* DHD_WAKE_EVENT_STATUS */
++			}
++#endif /* DHD_WAKE_STATUS */
++
++			/* For delete virtual interface event, wl_host_event returns positive
++			 * i/f index, do not proceed. just free the pkt.
++			 */
++			if ((event_type == WLC_E_IF) && (ret_event > 0)) {
++				DHD_ERROR(("%s: interface is deleted. Free event packet\n",
++				__FUNCTION__));
++#ifdef DHD_USE_STATIC_CTRLBUF
++				PKTFREE_STATIC(dhdp->osh, pktbuf, FALSE);
++#else
++				PKTFREE(dhdp->osh, pktbuf, FALSE);
++#endif
++				continue;
++			}
++
++#if defined(DHD_DONOT_FORWARD_BCMEVENT_AS_NETWORK_PKT) && !defined(SENDPROB)
++#ifdef DHD_USE_STATIC_CTRLBUF
++			PKTFREE_STATIC(dhdp->osh, pktbuf, FALSE);
++#else
++			PKTFREE(dhdp->osh, pktbuf, FALSE);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++			continue;
++#else
++#ifdef SENDPROB
++			if (!dhdp->recv_probereq || (event.event_type != WLC_E_PROBREQ_MSG)) {
++#ifdef DHD_USE_STATIC_CTRLBUF
++				PKTFREE_STATIC(dhdp->osh, pktbuf, FALSE);
++#else
++				PKTFREE(dhdp->osh, pktbuf, FALSE);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++				continue;
++			}
++#endif
++			/*
++			 * For the event packets, there is a possibility
++			 * of ifidx getting modifed.Thus update the ifp
++			 * once again.
++			 */
++			ASSERT(ifidx < DHD_MAX_IFS && dhd->iflist[ifidx]);
++			ifp = dhd->iflist[ifidx];
++#ifndef PROP_TXSTATUS_VSDB
++			if (!(ifp && ifp->net && (ifp->net->reg_state == NETREG_REGISTERED)))
++#else
++			if (!(ifp && ifp->net && (ifp->net->reg_state == NETREG_REGISTERED) &&
++				dhd->pub.up))
++#endif /* PROP_TXSTATUS_VSDB */
++			{
++				DHD_ERROR(("%s: net device is NOT registered. drop event packet\n",
++				__FUNCTION__));
++#ifdef DHD_USE_STATIC_CTRLBUF
++				PKTFREE_STATIC(dhdp->osh, pktbuf, FALSE);
++#else
++				PKTFREE(dhdp->osh, pktbuf, FALSE);
++#endif
++				continue;
++			}
++#endif /* DHD_DONOT_FORWARD_BCMEVENT_AS_NETWORK_PKT */
++		} else {
++			tout_rx = DHD_PACKET_TIMEOUT_MS;
++
++#ifdef PROP_TXSTATUS
++			dhd_wlfc_save_rxpath_ac_time(dhdp, (uint8)PKTPRIO(skb));
++#endif /* PROP_TXSTATUS */
++
++#ifdef DHD_WAKE_STATUS
++			if (unlikely(pkt_wake)) {
++				wcp->rxwake++;
++#ifdef DHD_WAKE_RX_STATUS
++#define ETHER_ICMP6_HEADER	20
++#define ETHER_IPV6_SADDR (ETHER_ICMP6_HEADER + 2)
++#define ETHER_IPV6_DAADR (ETHER_IPV6_SADDR + IPV6_ADDR_LEN)
++#define ETHER_ICMPV6_TYPE (ETHER_IPV6_DAADR + IPV6_ADDR_LEN)
++
++				if (ntoh16(skb->protocol) == ETHER_TYPE_ARP) /* ARP */
++					wcp->rx_arp++;
++				if (dump_data[0] == 0xFF) { /* Broadcast */
++					wcp->rx_bcast++;
++				} else if (dump_data[0] & 0x01) { /* Multicast */
++					wcp->rx_mcast++;
++					if (ntoh16(skb->protocol) == ETHER_TYPE_IPV6) {
++					    wcp->rx_multi_ipv6++;
++					    if ((skb->len > ETHER_ICMP6_HEADER) &&
++					        (dump_data[ETHER_ICMP6_HEADER] == IPPROTO_ICMPV6)) {
++					        wcp->rx_icmpv6++;
++					        if (skb->len > ETHER_ICMPV6_TYPE) {
++					            switch (dump_data[ETHER_ICMPV6_TYPE]) {
++					            case NDISC_ROUTER_ADVERTISEMENT:
++					                wcp->rx_icmpv6_ra++;
++					                break;
++					            case NDISC_NEIGHBOUR_ADVERTISEMENT:
++					                wcp->rx_icmpv6_na++;
++					                break;
++					            case NDISC_NEIGHBOUR_SOLICITATION:
++					                wcp->rx_icmpv6_ns++;
++					                break;
++					            }
++					        }
++					    }
++					} else if (dump_data[2] == 0x5E) {
++						wcp->rx_multi_ipv4++;
++					} else {
++						wcp->rx_multi_other++;
++					}
++				} else { /* Unicast */
++					wcp->rx_ucast++;
++				}
++#undef ETHER_ICMP6_HEADER
++#undef ETHER_IPV6_SADDR
++#undef ETHER_IPV6_DAADR
++#undef ETHER_ICMPV6_TYPE
++#endif /* DHD_WAKE_RX_STATUS */
++				pkt_wake = 0;
++			}
++#endif /* DHD_WAKE_STATUS */
++		}
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0)
++		if (ifp->net)
++			ifp->net->last_rx = jiffies;
++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0) */
++
++		if (ntoh16(skb->protocol) != ETHER_TYPE_BRCM) {
++			dhdp->dstats.rx_bytes += skb->len;
++			dhdp->rx_packets++; /* Local count */
++			ifp->stats.rx_bytes += skb->len;
++			ifp->stats.rx_packets++;
++		}
++
++		if (in_interrupt()) {
++			bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE,
++				__FUNCTION__, __LINE__);
++			DHD_PERIM_UNLOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++#if defined(DHD_LB_RXP)
++			netif_receive_skb(skb);
++#else /* !defined(DHD_LB_RXP) */
++			netif_rx(skb);
++#endif /* !defined(DHD_LB_RXP) */
++			DHD_PERIM_LOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++		} else {
++			if (dhd->rxthread_enabled) {
++				if (!skbhead)
++					skbhead = skb;
++				else
++					PKTSETNEXT(dhdp->osh, skbprev, skb);
++				skbprev = skb;
++			} else {
++
++				/* If the receive is not processed inside an ISR,
++				 * the softirqd must be woken explicitly to service
++				 * the NET_RX_SOFTIRQ.	In 2.6 kernels, this is handled
++				 * by netif_rx_ni(), but in earlier kernels, we need
++				 * to do it manually.
++				 */
++				bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE,
++					__FUNCTION__, __LINE__);
++
++#if defined(DHD_LB_RXP)
++				DHD_PERIM_UNLOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++				netif_receive_skb(skb);
++				DHD_PERIM_LOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++#else /* !defined(DHD_LB_RXP) */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
++				DHD_PERIM_UNLOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++				netif_rx_ni(skb);
++				DHD_PERIM_LOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++#else
++				ulong flags;
++				DHD_PERIM_UNLOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++				netif_rx(skb);
++				DHD_PERIM_LOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++				local_irq_save(flags);
++				RAISE_RX_SOFTIRQ();
++				local_irq_restore(flags);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0) */
++#endif /* !defined(DHD_LB_RXP) */
++			}
++		}
++	}
++
++	if (dhd->rxthread_enabled && skbhead)
++		dhd_sched_rxf(dhdp, skbhead);
++
++	DHD_OS_WAKE_LOCK_RX_TIMEOUT_ENABLE(dhdp, tout_rx);
++	DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_ENABLE(dhdp, tout_ctrl);
++}
++
++void
++dhd_event(struct dhd_info *dhd, char *evpkt, int evlen, int ifidx)
++{
++	/* Linux version has nothing to do */
++	return;
++}
++
++void
++dhd_txcomplete(dhd_pub_t *dhdp, void *txp, bool success)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(dhdp->info);
++	struct ether_header *eh;
++	uint16 type;
++
++	dhd_prot_hdrpull(dhdp, NULL, txp, NULL, NULL);
++
++
++	eh = (struct ether_header *)PKTDATA(dhdp->osh, txp);
++	type  = ntoh16(eh->ether_type);
++
++	if ((type == ETHER_TYPE_802_1X) && (dhd_get_pend_8021x_cnt(dhd) > 0)) {
++		atomic_dec(&dhd->pend_8021x_cnt);
++	}
++
++#ifdef PROP_TXSTATUS
++	if (dhdp->wlfc_state && (dhdp->proptxstatus_mode != WLFC_FCMODE_NONE)) {
++		dhd_if_t *ifp = dhd->iflist[DHD_PKTTAG_IF(PKTTAG(txp))];
++		uint datalen  = PKTLEN(dhd->pub.osh, txp);
++		if (ifp != NULL) {
++			if (success) {
++				dhd->pub.tx_packets++;
++				ifp->stats.tx_packets++;
++				ifp->stats.tx_bytes += datalen;
++			} else {
++				ifp->stats.tx_dropped++;
++			}
++		}
++	}
++#endif
++}
++
++static struct net_device_stats *
++dhd_get_stats(struct net_device *net)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(net);
++	dhd_if_t *ifp;
++	int ifidx;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (!dhd) {
++		DHD_ERROR(("%s : dhd is NULL\n", __FUNCTION__));
++		goto error;
++	}
++
++	ifidx = dhd_net2idx(dhd, net);
++	if (ifidx == DHD_BAD_IF) {
++		DHD_ERROR(("%s: BAD_IF\n", __FUNCTION__));
++		goto error;
++	}
++
++	ifp = dhd->iflist[ifidx];
++
++	if (!ifp) {
++		ASSERT(ifp);
++		DHD_ERROR(("%s: ifp is NULL\n", __FUNCTION__));
++		goto error;
++	}
++
++	if (dhd->pub.up) {
++		/* Use the protocol to get dongle stats */
++		dhd_prot_dstats(&dhd->pub);
++	}
++	return &ifp->stats;
++
++error:
++	memset(&net->stats, 0, sizeof(net->stats));
++	return &net->stats;
++}
++
++#ifndef BCMDBUS
++static int
++dhd_watchdog_thread(void *data)
++{
++	tsk_ctl_t *tsk = (tsk_ctl_t *)data;
++	dhd_info_t *dhd = (dhd_info_t *)tsk->parent;
++	/* This thread doesn't need any user-level access,
++	 * so get rid of all our resources
++	 */
++	if (dhd_watchdog_prio > 0) {
++		struct sched_param param;
++		param.sched_priority = (dhd_watchdog_prio < MAX_RT_PRIO)?
++			dhd_watchdog_prio:(MAX_RT_PRIO-1);
++		setScheduler(current, SCHED_FIFO, &param);
++	}
++
++	while (1) {
++		if (down_interruptible (&tsk->sema) == 0) {
++			unsigned long flags;
++			unsigned long jiffies_at_start = jiffies;
++			unsigned long time_lapse;
++			DHD_OS_WD_WAKE_LOCK(&dhd->pub);
++
++			SMP_RD_BARRIER_DEPENDS();
++			if (tsk->terminated) {
++				break;
++			}
++
++			if (dhd->pub.dongle_reset == FALSE) {
++				DHD_TIMER(("%s:\n", __FUNCTION__));
++				dhd_bus_watchdog(&dhd->pub);
++
++#ifdef DHD_TIMESYNC
++				/* Call the timesync module watchdog */
++				dhd_timesync_watchdog(&dhd->pub);
++#endif /* DHD_TIMESYNC */
++
++				DHD_GENERAL_LOCK(&dhd->pub, flags);
++				/* Count the tick for reference */
++				dhd->pub.tickcnt++;
++#ifdef DHD_L2_FILTER
++				dhd_l2_filter_watchdog(&dhd->pub);
++#endif /* DHD_L2_FILTER */
++				time_lapse = jiffies - jiffies_at_start;
++
++				/* Reschedule the watchdog */
++				if (dhd->wd_timer_valid) {
++					mod_timer(&dhd->timer,
++					    jiffies +
++					    msecs_to_jiffies(dhd_watchdog_ms) -
++					    min(msecs_to_jiffies(dhd_watchdog_ms), time_lapse));
++				}
++				DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++			}
++			DHD_OS_WD_WAKE_UNLOCK(&dhd->pub);
++		} else {
++			break;
++		}
++	}
++
++	complete_and_exit(&tsk->completed, 0);
++}
++
++static void dhd_watchdog(ulong data)
++{
++	dhd_info_t *dhd = (dhd_info_t *)data;
++	unsigned long flags;
++
++	if (dhd->pub.dongle_reset) {
++		return;
++	}
++
++	if (dhd->thr_wdt_ctl.thr_pid >= 0) {
++		up(&dhd->thr_wdt_ctl.sema);
++		return;
++	}
++
++	DHD_OS_WD_WAKE_LOCK(&dhd->pub);
++	/* Call the bus module watchdog */
++	dhd_bus_watchdog(&dhd->pub);
++
++#ifdef DHD_TIMESYNC
++	/* Call the timesync module watchdog */
++	dhd_timesync_watchdog(&dhd->pub);
++#endif /* DHD_TIMESYNC */
++
++	DHD_GENERAL_LOCK(&dhd->pub, flags);
++	/* Count the tick for reference */
++	dhd->pub.tickcnt++;
++
++#ifdef DHD_L2_FILTER
++	dhd_l2_filter_watchdog(&dhd->pub);
++#endif /* DHD_L2_FILTER */
++	/* Reschedule the watchdog */
++	if (dhd->wd_timer_valid)
++		mod_timer(&dhd->timer, jiffies + msecs_to_jiffies(dhd_watchdog_ms));
++	DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++	DHD_OS_WD_WAKE_UNLOCK(&dhd->pub);
++}
++
++#ifdef DHD_PCIE_RUNTIMEPM
++static int
++dhd_rpm_state_thread(void *data)
++{
++	tsk_ctl_t *tsk = (tsk_ctl_t *)data;
++	dhd_info_t *dhd = (dhd_info_t *)tsk->parent;
++
++	while (1) {
++		if (down_interruptible (&tsk->sema) == 0) {
++			unsigned long flags;
++			unsigned long jiffies_at_start = jiffies;
++			unsigned long time_lapse;
++
++			SMP_RD_BARRIER_DEPENDS();
++			if (tsk->terminated) {
++				break;
++			}
++
++			if (dhd->pub.dongle_reset == FALSE) {
++				DHD_TIMER(("%s:\n", __FUNCTION__));
++				if (dhd->pub.up) {
++					dhd_runtimepm_state(&dhd->pub);
++				}
++
++				DHD_GENERAL_LOCK(&dhd->pub, flags);
++				time_lapse = jiffies - jiffies_at_start;
++
++				/* Reschedule the watchdog */
++				if (dhd->rpm_timer_valid) {
++					mod_timer(&dhd->rpm_timer,
++						jiffies +
++						msecs_to_jiffies(dhd_runtimepm_ms) -
++						min(msecs_to_jiffies(dhd_runtimepm_ms),
++							time_lapse));
++				}
++				DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++			}
++		} else {
++			break;
++		}
++	}
++
++	complete_and_exit(&tsk->completed, 0);
++}
++
++static void dhd_runtimepm(ulong data)
++{
++	dhd_info_t *dhd = (dhd_info_t *)data;
++
++	if (dhd->pub.dongle_reset) {
++		return;
++	}
++
++	if (dhd->thr_rpm_ctl.thr_pid >= 0) {
++		up(&dhd->thr_rpm_ctl.sema);
++		return;
++	}
++}
++
++void dhd_runtime_pm_disable(dhd_pub_t *dhdp)
++{
++	dhd_os_runtimepm_timer(dhdp, 0);
++	dhdpcie_runtime_bus_wake(dhdp, TRUE, __builtin_return_address(0));
++	DHD_ERROR(("DHD Runtime PM Disabled \n"));
++}
++
++void dhd_runtime_pm_enable(dhd_pub_t *dhdp)
++{
++	if (dhd_get_idletime(dhdp)) {
++		dhd_os_runtimepm_timer(dhdp, dhd_runtimepm_ms);
++		DHD_ERROR(("DHD Runtime PM Enabled \n"));
++	}
++}
++
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++
++#ifdef ENABLE_ADAPTIVE_SCHED
++static void
++dhd_sched_policy(int prio)
++{
++	struct sched_param param;
++	if (cpufreq_quick_get(0) <= CUSTOM_CPUFREQ_THRESH) {
++		param.sched_priority = 0;
++		setScheduler(current, SCHED_NORMAL, &param);
++	} else {
++		if (get_scheduler_policy(current) != SCHED_FIFO) {
++			param.sched_priority = (prio < MAX_RT_PRIO)? prio : (MAX_RT_PRIO-1);
++			setScheduler(current, SCHED_FIFO, &param);
++		}
++	}
++}
++#endif /* ENABLE_ADAPTIVE_SCHED */
++#ifdef DEBUG_CPU_FREQ
++static int dhd_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data)
++{
++	dhd_info_t *dhd = container_of(nb, struct dhd_info, freq_trans);
++	struct cpufreq_freqs *freq = data;
++	if (dhd) {
++		if (!dhd->new_freq)
++			goto exit;
++		if (val == CPUFREQ_POSTCHANGE) {
++			DHD_ERROR(("cpu freq is changed to %u kHZ on CPU %d\n",
++				freq->new, freq->cpu));
++			*per_cpu_ptr(dhd->new_freq, freq->cpu) = freq->new;
++		}
++	}
++exit:
++	return 0;
++}
++#endif /* DEBUG_CPU_FREQ */
++
++static int
++dhd_dpc_thread(void *data)
++{
++	tsk_ctl_t *tsk = (tsk_ctl_t *)data;
++	dhd_info_t *dhd = (dhd_info_t *)tsk->parent;
++
++	/* This thread doesn't need any user-level access,
++	 * so get rid of all our resources
++	 */
++	if (dhd_dpc_prio > 0)
++	{
++		struct sched_param param;
++		param.sched_priority = (dhd_dpc_prio < MAX_RT_PRIO)?dhd_dpc_prio:(MAX_RT_PRIO-1);
++		setScheduler(current, SCHED_FIFO, &param);
++	}
++
++#ifdef CUSTOM_DPC_CPUCORE
++	set_cpus_allowed_ptr(current, cpumask_of(CUSTOM_DPC_CPUCORE));
++#endif
++#ifdef CUSTOM_SET_CPUCORE
++	dhd->pub.current_dpc = current;
++#endif /* CUSTOM_SET_CPUCORE */
++	/* Run until signal received */
++	while (1) {
++		if (dhd->pub.conf->dpc_cpucore >= 0) {
++			printf("%s: set dpc_cpucore %d\n", __FUNCTION__, dhd->pub.conf->dpc_cpucore);
++			set_cpus_allowed_ptr(current, cpumask_of(dhd->pub.conf->dpc_cpucore));
++			dhd->pub.conf->dpc_cpucore = -1;
++		}
++		if (!binary_sema_down(tsk)) {
++#ifdef ENABLE_ADAPTIVE_SCHED
++			dhd_sched_policy(dhd_dpc_prio);
++#endif /* ENABLE_ADAPTIVE_SCHED */
++			SMP_RD_BARRIER_DEPENDS();
++			if (tsk->terminated) {
++				break;
++			}
++
++			/* Call bus dpc unless it indicated down (then clean stop) */
++			if (dhd->pub.busstate != DHD_BUS_DOWN) {
++#ifdef DEBUG_DPC_THREAD_WATCHDOG
++				int resched_cnt = 0;
++#endif /* DEBUG_DPC_THREAD_WATCHDOG */
++				dhd_os_wd_timer_extend(&dhd->pub, TRUE);
++				while (dhd_bus_dpc(dhd->pub.bus)) {
++					/* process all data */
++#ifdef DEBUG_DPC_THREAD_WATCHDOG
++					resched_cnt++;
++					if (resched_cnt > MAX_RESCHED_CNT) {
++						DHD_INFO(("%s Calling msleep to"
++							"let other processes run. \n",
++							__FUNCTION__));
++						dhd->pub.dhd_bug_on = true;
++						resched_cnt = 0;
++						OSL_SLEEP(1);
++					}
++#endif /* DEBUG_DPC_THREAD_WATCHDOG */
++				}
++				dhd_os_wd_timer_extend(&dhd->pub, FALSE);
++				DHD_OS_WAKE_UNLOCK(&dhd->pub);
++			} else {
++				if (dhd->pub.up)
++					dhd_bus_stop(dhd->pub.bus, TRUE);
++				DHD_OS_WAKE_UNLOCK(&dhd->pub);
++			}
++		} else {
++			break;
++		}
++	}
++	complete_and_exit(&tsk->completed, 0);
++}
++
++static int
++dhd_rxf_thread(void *data)
++{
++	tsk_ctl_t *tsk = (tsk_ctl_t *)data;
++	dhd_info_t *dhd = (dhd_info_t *)tsk->parent;
++#if defined(WAIT_DEQUEUE)
++#define RXF_WATCHDOG_TIME 250 /* BARK_TIME(1000) /  */
++	ulong watchdogTime = OSL_SYSUPTIME(); /* msec */
++#endif
++	dhd_pub_t *pub = &dhd->pub;
++
++	/* This thread doesn't need any user-level access,
++	 * so get rid of all our resources
++	 */
++	if (dhd_rxf_prio > 0)
++	{
++		struct sched_param param;
++		param.sched_priority = (dhd_rxf_prio < MAX_RT_PRIO)?dhd_rxf_prio:(MAX_RT_PRIO-1);
++		setScheduler(current, SCHED_FIFO, &param);
++	}
++
++#ifdef CUSTOM_SET_CPUCORE
++	dhd->pub.current_rxf = current;
++#endif /* CUSTOM_SET_CPUCORE */
++	/* Run until signal received */
++	while (1) {
++		if (dhd->pub.conf->rxf_cpucore >= 0) {
++			printf("%s: set rxf_cpucore %d\n", __FUNCTION__, dhd->pub.conf->rxf_cpucore);
++			set_cpus_allowed_ptr(current, cpumask_of(dhd->pub.conf->rxf_cpucore));
++			dhd->pub.conf->rxf_cpucore = -1;
++		}
++		if (down_interruptible(&tsk->sema) == 0) {
++			void *skb;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)
++			ulong flags;
++#endif
++#ifdef ENABLE_ADAPTIVE_SCHED
++			dhd_sched_policy(dhd_rxf_prio);
++#endif /* ENABLE_ADAPTIVE_SCHED */
++
++			SMP_RD_BARRIER_DEPENDS();
++
++			if (tsk->terminated) {
++				break;
++			}
++			skb = dhd_rxf_dequeue(pub);
++
++			if (skb == NULL) {
++				continue;
++			}
++			while (skb) {
++				void *skbnext = PKTNEXT(pub->osh, skb);
++				PKTSETNEXT(pub->osh, skb, NULL);
++				bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE,
++					__FUNCTION__, __LINE__);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
++				netif_rx_ni(skb);
++#else
++				netif_rx(skb);
++				local_irq_save(flags);
++				RAISE_RX_SOFTIRQ();
++				local_irq_restore(flags);
++
++#endif
++				skb = skbnext;
++			}
++#if defined(WAIT_DEQUEUE)
++			if (OSL_SYSUPTIME() - watchdogTime > RXF_WATCHDOG_TIME) {
++				OSL_SLEEP(1);
++				watchdogTime = OSL_SYSUPTIME();
++			}
++#endif
++
++			DHD_OS_WAKE_UNLOCK(pub);
++		} else {
++			break;
++		}
++	}
++	complete_and_exit(&tsk->completed, 0);
++}
++
++#ifdef BCMPCIE
++void dhd_dpc_enable(dhd_pub_t *dhdp)
++{
++#if defined(DHD_LB_RXP) || defined(DHD_LB_TXP)
++	dhd_info_t *dhd;
++
++	if (!dhdp || !dhdp->info)
++		return;
++	dhd = dhdp->info;
++#endif /* DHD_LB_RXP || DHD_LB_TXP */
++
++#ifdef DHD_LB_RXP
++	__skb_queue_head_init(&dhd->rx_pend_queue);
++#endif /* DHD_LB_RXP */
++
++#ifdef DHD_LB_TXP
++	skb_queue_head_init(&dhd->tx_pend_queue);
++#endif /* DHD_LB_TXP */
++}
++#endif /* BCMPCIE */
++
++#ifdef BCMPCIE
++void
++dhd_dpc_kill(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd;
++
++	if (!dhdp) {
++		return;
++	}
++
++	dhd = dhdp->info;
++
++	if (!dhd) {
++		return;
++	}
++
++	if (dhd->thr_dpc_ctl.thr_pid < 0) {
++		tasklet_kill(&dhd->tasklet);
++		DHD_ERROR(("%s: tasklet disabled\n", __FUNCTION__));
++	}
++
++#ifdef DHD_LB
++#ifdef DHD_LB_RXP
++	cancel_work_sync(&dhd->rx_napi_dispatcher_work);
++	__skb_queue_purge(&dhd->rx_pend_queue);
++#endif /* DHD_LB_RXP */
++#ifdef DHD_LB_TXP
++	cancel_work_sync(&dhd->tx_dispatcher_work);
++	skb_queue_purge(&dhd->tx_pend_queue);
++#endif /* DHD_LB_TXP */
++
++	/* Kill the Load Balancing Tasklets */
++#if defined(DHD_LB_TXC)
++	tasklet_kill(&dhd->tx_compl_tasklet);
++#endif /* DHD_LB_TXC */
++#if defined(DHD_LB_RXC)
++	tasklet_kill(&dhd->rx_compl_tasklet);
++#endif /* DHD_LB_RXC */
++#if defined(DHD_LB_TXP)
++	tasklet_kill(&dhd->tx_tasklet);
++#endif /* DHD_LB_TXP */
++#endif /* DHD_LB */
++}
++
++void
++dhd_dpc_tasklet_kill(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd;
++
++	if (!dhdp) {
++		return;
++	}
++
++	dhd = dhdp->info;
++
++	if (!dhd) {
++		return;
++	}
++
++	if (dhd->thr_dpc_ctl.thr_pid < 0) {
++		tasklet_kill(&dhd->tasklet);
++	}
++}
++#endif /* BCMPCIE */
++
++static void
++dhd_dpc(ulong data)
++{
++	dhd_info_t *dhd;
++
++	dhd = (dhd_info_t *)data;
++
++	/* this (tasklet) can be scheduled in dhd_sched_dpc[dhd_linux.c]
++	 * down below , wake lock is set,
++	 * the tasklet is initialized in dhd_attach()
++	 */
++	/* Call bus dpc unless it indicated down (then clean stop) */
++	if (dhd->pub.busstate != DHD_BUS_DOWN) {
++#if defined(DHD_LB_STATS) && defined(PCIE_FULL_DONGLE)
++		DHD_LB_STATS_INCR(dhd->dhd_dpc_cnt);
++#endif /* DHD_LB_STATS && PCIE_FULL_DONGLE */
++		if (dhd_bus_dpc(dhd->pub.bus)) {
++			tasklet_schedule(&dhd->tasklet);
++		}
++	} else {
++		dhd_bus_stop(dhd->pub.bus, TRUE);
++	}
++}
++
++void
++dhd_sched_dpc(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++
++	if (dhd->thr_dpc_ctl.thr_pid >= 0) {
++		DHD_OS_WAKE_LOCK(dhdp);
++		/* If the semaphore does not get up,
++		* wake unlock should be done here
++		*/
++		if (!binary_sema_up(&dhd->thr_dpc_ctl)) {
++			DHD_OS_WAKE_UNLOCK(dhdp);
++		}
++		return;
++	} else {
++		tasklet_schedule(&dhd->tasklet);
++	}
++}
++#endif /* BCMDBUS */
++
++static void
++dhd_sched_rxf(dhd_pub_t *dhdp, void *skb)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++#ifdef RXF_DEQUEUE_ON_BUSY
++	int ret = BCME_OK;
++	int retry = 2;
++#endif /* RXF_DEQUEUE_ON_BUSY */
++
++	DHD_OS_WAKE_LOCK(dhdp);
++
++	DHD_TRACE(("dhd_sched_rxf: Enter\n"));
++#ifdef RXF_DEQUEUE_ON_BUSY
++	do {
++		ret = dhd_rxf_enqueue(dhdp, skb);
++		if (ret == BCME_OK || ret == BCME_ERROR)
++			break;
++		else
++			OSL_SLEEP(50); /* waiting for dequeueing */
++	} while (retry-- > 0);
++
++	if (retry <= 0 && ret == BCME_BUSY) {
++		void *skbp = skb;
++
++		while (skbp) {
++			void *skbnext = PKTNEXT(dhdp->osh, skbp);
++			PKTSETNEXT(dhdp->osh, skbp, NULL);
++			bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE,
++				__FUNCTION__, __LINE__);
++			netif_rx_ni(skbp);
++			skbp = skbnext;
++		}
++		DHD_ERROR(("send skb to kernel backlog without rxf_thread\n"));
++	} else {
++		if (dhd->thr_rxf_ctl.thr_pid >= 0) {
++			up(&dhd->thr_rxf_ctl.sema);
++		}
++	}
++#else /* RXF_DEQUEUE_ON_BUSY */
++	do {
++		if (dhd_rxf_enqueue(dhdp, skb) == BCME_OK)
++			break;
++	} while (1);
++	if (dhd->thr_rxf_ctl.thr_pid >= 0) {
++		up(&dhd->thr_rxf_ctl.sema);
++	}
++	return;
++#endif /* RXF_DEQUEUE_ON_BUSY */
++}
++
++#if defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW)
++#endif /* defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW) */
++
++#ifdef TOE
++/* Retrieve current toe component enables, which are kept as a bitmap in toe_ol iovar */
++static int
++dhd_toe_get(dhd_info_t *dhd, int ifidx, uint32 *toe_ol)
++{
++	char buf[32];
++	int ret;
++
++	ret = dhd_iovar(&dhd->pub, ifidx, "toe_ol", NULL, 0, (char *)&buf, sizeof(buf), FALSE);
++
++	if (ret < 0) {
++		if (ret == -EIO) {
++			DHD_ERROR(("%s: toe not supported by device\n", dhd_ifname(&dhd->pub,
++				ifidx)));
++			return -EOPNOTSUPP;
++		}
++
++		DHD_INFO(("%s: could not get toe_ol: ret=%d\n", dhd_ifname(&dhd->pub, ifidx), ret));
++		return ret;
++	}
++
++	memcpy(toe_ol, buf, sizeof(uint32));
++	return 0;
++}
++
++/* Set current toe component enables in toe_ol iovar, and set toe global enable iovar */
++static int
++dhd_toe_set(dhd_info_t *dhd, int ifidx, uint32 toe_ol)
++{
++	int toe, ret;
++
++	/* Set toe_ol as requested */
++	ret = dhd_iovar(&dhd->pub, ifidx, "toe_ol", (char *)&toe_ol, sizeof(toe_ol), NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: could not set toe_ol: ret=%d\n",
++			dhd_ifname(&dhd->pub, ifidx), ret));
++		return ret;
++	}
++
++	/* Enable toe globally only if any components are enabled. */
++	toe = (toe_ol != 0);
++	ret = dhd_iovar(&dhd->pub, ifidx, "toe", (char *)&toe, sizeof(toe), NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: could not set toe: ret=%d\n", dhd_ifname(&dhd->pub, ifidx), ret));
++		return ret;
++	}
++
++	return 0;
++}
++#endif /* TOE */
++
++#if defined(WL_CFG80211) && defined(NUM_SCB_MAX_PROBE)
++void dhd_set_scb_probe(dhd_pub_t *dhd)
++{
++	wl_scb_probe_t scb_probe;
++	int ret;
++
++	if (dhd->op_mode & DHD_FLAG_HOSTAP_MODE) {
++		return;
++	}
++
++	ret = dhd_iovar(dhd, 0, "scb_probe", NULL, 0,
++			(char *)&scb_probe, sizeof(scb_probe), FALSE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: GET max_scb_probe failed\n", __FUNCTION__));
++	}
++
++	scb_probe.scb_max_probe = NUM_SCB_MAX_PROBE;
++
++	ret = dhd_iovar(dhd, 0, "scb_probe", (char *)&scb_probe, sizeof(scb_probe),
++			NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: max_scb_probe setting failed\n", __FUNCTION__));
++		return;
++	}
++}
++#endif /* WL_CFG80211 && NUM_SCB_MAX_PROBE */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
++static void
++dhd_ethtool_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *info)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(net);
++
++	snprintf(info->driver, sizeof(info->driver), "wl");
++	snprintf(info->version, sizeof(info->version), "%lu", dhd->pub.drv_version);
++}
++
++struct ethtool_ops dhd_ethtool_ops = {
++	.get_drvinfo = dhd_ethtool_get_drvinfo
++};
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24) */
++
++
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 4, 2)
++static int
++dhd_ethtool(dhd_info_t *dhd, void *uaddr)
++{
++	struct ethtool_drvinfo info;
++	char drvname[sizeof(info.driver)];
++	uint32 cmd;
++#ifdef TOE
++	struct ethtool_value edata;
++	uint32 toe_cmpnt, csum_dir;
++	int ret;
++#endif
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	/* all ethtool calls start with a cmd word */
++	if (copy_from_user(&cmd, uaddr, sizeof (uint32)))
++		return -EFAULT;
++
++	switch (cmd) {
++	case ETHTOOL_GDRVINFO:
++		/* Copy out any request driver name */
++		if (copy_from_user(&info, uaddr, sizeof(info)))
++			return -EFAULT;
++		strncpy(drvname, info.driver, sizeof(info.driver));
++		drvname[sizeof(info.driver)-1] = '\0';
++
++		/* clear struct for return */
++		memset(&info, 0, sizeof(info));
++		info.cmd = cmd;
++
++		/* if dhd requested, identify ourselves */
++		if (strcmp(drvname, "?dhd") == 0) {
++			snprintf(info.driver, sizeof(info.driver), "dhd");
++			strncpy(info.version, EPI_VERSION_STR, sizeof(info.version) - 1);
++			info.version[sizeof(info.version) - 1] = '\0';
++		}
++
++		/* otherwise, require dongle to be up */
++		else if (!dhd->pub.up) {
++			DHD_ERROR(("%s: dongle is not up\n", __FUNCTION__));
++			return -ENODEV;
++		}
++
++		/* finally, report dongle driver type */
++		else if (dhd->pub.iswl)
++			snprintf(info.driver, sizeof(info.driver), "wl");
++		else
++			snprintf(info.driver, sizeof(info.driver), "xx");
++
++		snprintf(info.version, sizeof(info.version), "%lu", dhd->pub.drv_version);
++		if (copy_to_user(uaddr, &info, sizeof(info)))
++			return -EFAULT;
++		DHD_CTL(("%s: given %*s, returning %s\n", __FUNCTION__,
++		         (int)sizeof(drvname), drvname, info.driver));
++		break;
++
++#ifdef TOE
++	/* Get toe offload components from dongle */
++	case ETHTOOL_GRXCSUM:
++	case ETHTOOL_GTXCSUM:
++		if ((ret = dhd_toe_get(dhd, 0, &toe_cmpnt)) < 0)
++			return ret;
++
++		csum_dir = (cmd == ETHTOOL_GTXCSUM) ? TOE_TX_CSUM_OL : TOE_RX_CSUM_OL;
++
++		edata.cmd = cmd;
++		edata.data = (toe_cmpnt & csum_dir) ? 1 : 0;
++
++		if (copy_to_user(uaddr, &edata, sizeof(edata)))
++			return -EFAULT;
++		break;
++
++	/* Set toe offload components in dongle */
++	case ETHTOOL_SRXCSUM:
++	case ETHTOOL_STXCSUM:
++		if (copy_from_user(&edata, uaddr, sizeof(edata)))
++			return -EFAULT;
++
++		/* Read the current settings, update and write back */
++		if ((ret = dhd_toe_get(dhd, 0, &toe_cmpnt)) < 0)
++			return ret;
++
++		csum_dir = (cmd == ETHTOOL_STXCSUM) ? TOE_TX_CSUM_OL : TOE_RX_CSUM_OL;
++
++		if (edata.data != 0)
++			toe_cmpnt |= csum_dir;
++		else
++			toe_cmpnt &= ~csum_dir;
++
++		if ((ret = dhd_toe_set(dhd, 0, toe_cmpnt)) < 0)
++			return ret;
++
++		/* If setting TX checksum mode, tell Linux the new mode */
++		if (cmd == ETHTOOL_STXCSUM) {
++			if (edata.data)
++				dhd->iflist[0]->net->features |= NETIF_F_IP_CSUM;
++			else
++				dhd->iflist[0]->net->features &= ~NETIF_F_IP_CSUM;
++		}
++
++		break;
++#endif /* TOE */
++
++	default:
++		return -EOPNOTSUPP;
++	}
++
++	return 0;
++}
++#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 4, 2) */
++
++static bool dhd_check_hang(struct net_device *net, dhd_pub_t *dhdp, int error)
++{
++	if (!dhdp) {
++		DHD_ERROR(("%s: dhdp is NULL\n", __FUNCTION__));
++		return FALSE;
++	}
++
++	if (!dhdp->up)
++		return FALSE;
++
++#if !defined(BCMPCIE) && !defined(BCMDBUS)
++	if (dhdp->info->thr_dpc_ctl.thr_pid < 0) {
++		DHD_ERROR(("%s : skipped due to negative pid - unloading?\n", __FUNCTION__));
++		return FALSE;
++	}
++#endif /* !BCMPCIE && !BCMDBUS */
++
++	if ((error == -ETIMEDOUT) || (error == -EREMOTEIO) ||
++		((dhdp->busstate == DHD_BUS_DOWN) && (!dhdp->dongle_reset))) {
++#ifdef BCMPCIE
++		DHD_ERROR(("%s: Event HANG send up due to  re=%d te=%d d3acke=%d e=%d s=%d\n",
++			__FUNCTION__, dhdp->rxcnt_timeout, dhdp->txcnt_timeout,
++			dhdp->d3ackcnt_timeout, error, dhdp->busstate));
++#else
++		DHD_ERROR(("%s: Event HANG send up due to  re=%d te=%d e=%d s=%d\n", __FUNCTION__,
++			dhdp->rxcnt_timeout, dhdp->txcnt_timeout, error, dhdp->busstate));
++#endif /* BCMPCIE */
++		if (dhdp->hang_reason == 0) {
++			if (dhdp->dongle_trap_occured) {
++				dhdp->hang_reason = HANG_REASON_DONGLE_TRAP;
++#ifdef BCMPCIE
++			} else if (dhdp->d3ackcnt_timeout) {
++				dhdp->hang_reason = HANG_REASON_D3_ACK_TIMEOUT;
++#endif /* BCMPCIE */
++			} else {
++				dhdp->hang_reason = HANG_REASON_IOCTL_RESP_TIMEOUT;
++			}
++		}
++		printf("%s\n", info_string);
++		net_os_send_hang_message(net);
++		return TRUE;
++	}
++	return FALSE;
++}
++
++#ifdef WL_MONITOR
++bool
++dhd_monitor_enabled(dhd_pub_t *dhd, int ifidx)
++{
++	return (dhd->info->monitor_type != 0);
++}
++
++void
++dhd_rx_mon_pkt(dhd_pub_t *dhdp, host_rxbuf_cmpl_t* msg, void *pkt, int ifidx)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++#ifdef HOST_RADIOTAP_CONV
++	uint16 len = 0, offset = 0;
++	monitor_pkt_info_t pkt_info;
++	memcpy(&pkt_info.marker, &msg->marker, sizeof(msg->marker));
++	memcpy(&pkt_info.ts, &msg->ts, sizeof(monitor_pkt_ts_t));
++
++	if (!dhd->monitor_skb) {
++		if ((dhd->monitor_skb = dev_alloc_skb(MAX_MON_PKT_SIZE)) == NULL)
++			return;
++	}
++
++	len = bcmwifi_monitor(dhd->monitor_info, &pkt_info, PKTDATA(dhdp->osh, pkt),
++		PKTLEN(dhdp->osh, pkt), PKTDATA(dhdp->osh, dhd->monitor_skb), &offset);
++
++	if (dhd->monitor_type && dhd->monitor_dev)
++		dhd->monitor_skb->dev = dhd->monitor_dev;
++	else {
++		PKTFREE(dhdp->osh, pkt, FALSE);
++		dev_kfree_skb(dhd->monitor_skb);
++		return;
++	}
++
++	PKTFREE(dhdp->osh, pkt, FALSE);
++
++	if (!len) {
++		return;
++	}
++
++	skb_put(dhd->monitor_skb, len);
++	skb_pull(dhd->monitor_skb, offset);
++
++	dhd->monitor_skb->protocol = eth_type_trans(dhd->monitor_skb, dhd->monitor_skb->dev);
++#else
++	uint8 amsdu_flag = (msg->flags & BCMPCIE_PKT_FLAGS_MONITOR_MASK) >>
++		BCMPCIE_PKT_FLAGS_MONITOR_SHIFT;
++	switch (amsdu_flag) {
++		case BCMPCIE_PKT_FLAGS_MONITOR_NO_AMSDU:
++		default:
++			if (!dhd->monitor_skb) {
++				if ((dhd->monitor_skb = PKTTONATIVE(dhdp->osh, pkt)) == NULL)
++					return;
++			}
++
++			if (dhd->monitor_type && dhd->monitor_dev)
++				dhd->monitor_skb->dev = dhd->monitor_dev;
++			else {
++				PKTFREE(dhdp->osh, pkt, FALSE);
++				dhd->monitor_skb = NULL;
++				return;
++			}
++
++			dhd->monitor_skb->protocol =
++				eth_type_trans(dhd->monitor_skb, dhd->monitor_skb->dev);
++			dhd->monitor_len = 0;
++			break;
++		case BCMPCIE_PKT_FLAGS_MONITOR_FIRST_PKT:
++			if (!dhd->monitor_skb) {
++				if ((dhd->monitor_skb = dev_alloc_skb(MAX_MON_PKT_SIZE)) == NULL)
++					return;
++				dhd->monitor_len = 0;
++			}
++			if (dhd->monitor_type && dhd->monitor_dev)
++				dhd->monitor_skb->dev = dhd->monitor_dev;
++			else {
++				PKTFREE(dhdp->osh, pkt, FALSE);
++				dev_kfree_skb(dhd->monitor_skb);
++				return;
++			}
++			memcpy(PKTDATA(dhdp->osh, dhd->monitor_skb),
++				PKTDATA(dhdp->osh, pkt), PKTLEN(dhdp->osh, pkt));
++
++			dhd->monitor_len = PKTLEN(dhdp->osh, pkt);
++			PKTFREE(dhdp->osh, pkt, FALSE);
++			return;
++		case BCMPCIE_PKT_FLAGS_MONITOR_INTER_PKT:
++			memcpy(PKTDATA(dhdp->osh, dhd->monitor_skb) + dhd->monitor_len,
++				PKTDATA(dhdp->osh, pkt), PKTLEN(dhdp->osh, pkt));
++			dhd->monitor_len += PKTLEN(dhdp->osh, pkt);
++
++			PKTFREE(dhdp->osh, pkt, FALSE);
++			return;
++		case BCMPCIE_PKT_FLAGS_MONITOR_LAST_PKT:
++			memcpy(PKTDATA(dhdp->osh, dhd->monitor_skb) + dhd->monitor_len,
++				PKTDATA(dhdp->osh, pkt), PKTLEN(dhdp->osh, pkt));
++			dhd->monitor_len += PKTLEN(dhdp->osh, pkt);
++
++			PKTFREE(dhdp->osh, pkt, FALSE);
++			skb_put(dhd->monitor_skb, dhd->monitor_len);
++			dhd->monitor_skb->protocol =
++				eth_type_trans(dhd->monitor_skb, dhd->monitor_skb->dev);
++			dhd->monitor_len = 0;
++			break;
++	}
++
++#endif /* HOST_RADIOTAP_CONV */
++	if (in_interrupt()) {
++		bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE,
++			__FUNCTION__, __LINE__);
++		DHD_PERIM_UNLOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++		netif_rx(dhd->monitor_skb);
++		DHD_PERIM_LOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++	} else {
++		/* If the receive is not processed inside an ISR,
++		 * the softirqd must be woken explicitly to service
++		 * the NET_RX_SOFTIRQ.	In 2.6 kernels, this is handled
++		 * by netif_rx_ni(), but in earlier kernels, we need
++		 * to do it manually.
++		 */
++		bcm_object_trace_opr(dhd->monitor_skb, BCM_OBJDBG_REMOVE,
++			__FUNCTION__, __LINE__);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
++		DHD_PERIM_UNLOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++		netif_rx_ni(dhd->monitor_skb);
++		DHD_PERIM_LOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++#else
++		ulong flags;
++		DHD_PERIM_UNLOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++		netif_rx(dhd->monitor_skb);
++		DHD_PERIM_LOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++		local_irq_save(flags);
++		RAISE_RX_SOFTIRQ();
++		local_irq_restore(flags);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0) */
++	}
++
++	dhd->monitor_skb = NULL;
++}
++
++typedef struct dhd_mon_dev_priv {
++	struct net_device_stats stats;
++} dhd_mon_dev_priv_t;
++
++#define DHD_MON_DEV_PRIV_SIZE		(sizeof(dhd_mon_dev_priv_t))
++#define DHD_MON_DEV_PRIV(dev)		((dhd_mon_dev_priv_t *)DEV_PRIV(dev))
++#define DHD_MON_DEV_STATS(dev)		(((dhd_mon_dev_priv_t *)DEV_PRIV(dev))->stats)
++
++static int
++dhd_monitor_start(struct sk_buff *skb, struct net_device *dev)
++{
++	PKTFREE(NULL, skb, FALSE);
++	return 0;
++}
++
++static int
++dhd_monitor_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
++{
++	return 0;
++}
++
++static struct net_device_stats*
++dhd_monitor_get_stats(struct net_device *dev)
++{
++	return &DHD_MON_DEV_STATS(dev);
++}
++
++static const struct net_device_ops netdev_monitor_ops =
++{
++	.ndo_start_xmit = dhd_monitor_start,
++	.ndo_get_stats = dhd_monitor_get_stats,
++	.ndo_do_ioctl = dhd_monitor_ioctl
++};
++
++static void
++dhd_add_monitor_if(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++	struct net_device *dev;
++	char *devname;
++
++	if (event != DHD_WQ_WORK_IF_ADD) {
++		DHD_ERROR(("%s: unexpected event \n", __FUNCTION__));
++		return;
++	}
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd info not available \n", __FUNCTION__));
++		return;
++	}
++
++	dev = alloc_etherdev(DHD_MON_DEV_PRIV_SIZE);
++	if (!dev) {
++		DHD_ERROR(("%s: alloc wlif failed\n", __FUNCTION__));
++		return;
++	}
++
++	devname = "radiotap";
++
++	snprintf(dev->name, sizeof(dev->name), "%s%u", devname, dhd->unit);
++
++#ifndef ARPHRD_IEEE80211_PRISM  /* From Linux 2.4.18 */
++#define ARPHRD_IEEE80211_PRISM 802
++#endif
++
++#ifndef ARPHRD_IEEE80211_RADIOTAP
++#define ARPHRD_IEEE80211_RADIOTAP	803 /* IEEE 802.11 + radiotap header */
++#endif /* ARPHRD_IEEE80211_RADIOTAP */
++
++	dev->type = ARPHRD_IEEE80211_RADIOTAP;
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31))
++	dev->hard_start_xmit = dhd_monitor_start;
++	dev->do_ioctl = dhd_monitor_ioctl;
++	dev->get_stats = dhd_monitor_get_stats;
++#else
++	dev->netdev_ops = &netdev_monitor_ops;
++#endif
++
++	if (register_netdev(dev)) {
++		DHD_ERROR(("%s, register_netdev failed for %s\n",
++			__FUNCTION__, dev->name));
++		free_netdev(dev);
++	}
++
++	bcmwifi_monitor_create(&dhd->monitor_info);
++	dhd->monitor_dev = dev;
++}
++
++static void
++dhd_del_monitor_if(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++
++	if (event != DHD_WQ_WORK_IF_DEL) {
++		DHD_ERROR(("%s: unexpected event \n", __FUNCTION__));
++		return;
++	}
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd info not available \n", __FUNCTION__));
++		return;
++	}
++
++	if (dhd->monitor_dev) {
++		unregister_netdev(dhd->monitor_dev);
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
++		MFREE(dhd->osh, dhd->monitor_dev->priv, DHD_MON_DEV_PRIV_SIZE);
++		MFREE(dhd->osh, dhd->monitor_dev, sizeof(struct net_device));
++#else
++		free_netdev(dhd->monitor_dev);
++#endif /* 2.6.24 */
++
++		dhd->monitor_dev = NULL;
++	}
++
++	if (dhd->monitor_info) {
++		bcmwifi_monitor_delete(dhd->monitor_info);
++		dhd->monitor_info = NULL;
++	}
++}
++
++static void
++dhd_set_monitor(dhd_pub_t *dhd, int ifidx, int val)
++{
++	dhd_info_t *info = dhd->info;
++
++	DHD_TRACE(("%s: val %d\n", __FUNCTION__, val));
++	if ((val && info->monitor_dev) || (!val && !info->monitor_dev)) {
++		DHD_ERROR(("%s: Mismatched params, return\n", __FUNCTION__));
++		return;
++	}
++
++	/* Delete monitor */
++	if (!val) {
++		info->monitor_type = val;
++		dhd_deferred_schedule_work(info->dhd_deferred_wq, NULL, DHD_WQ_WORK_IF_DEL,
++			dhd_del_monitor_if, DHD_WQ_WORK_PRIORITY_LOW);
++		return;
++	}
++
++	/* Add monitor */
++	info->monitor_type = val;
++	dhd_deferred_schedule_work(info->dhd_deferred_wq, NULL, DHD_WQ_WORK_IF_ADD,
++		dhd_add_monitor_if, DHD_WQ_WORK_PRIORITY_LOW);
++}
++#endif /* WL_MONITOR */
++
++int dhd_ioctl_process(dhd_pub_t *pub, int ifidx, dhd_ioctl_t *ioc, void *data_buf)
++{
++	int bcmerror = BCME_OK;
++	int buflen = 0;
++	struct net_device *net;
++
++#ifdef REPORT_FATAL_TIMEOUTS
++	if (ioc->cmd == WLC_SET_WPA_AUTH) {
++		int wpa_auth;
++
++		wpa_auth = *((int *)ioc->buf);
++		DHD_INFO(("wpa_auth:%d\n", wpa_auth));
++		if (wpa_auth != WPA_AUTH_DISABLED) {
++			/* If AP is with security then enable WLC_E_PSK_SUP event checking */
++			dhd_set_join_error(pub, WLC_WPA_MASK);
++		} else {
++			/* If AP is with open then disable WLC_E_PSK_SUP event checking */
++			dhd_clear_join_error(pub, WLC_WPA_MASK);
++		}
++	}
++
++	if (ioc->cmd == WLC_SET_AUTH) {
++		int auth;
++		auth = *((int *)ioc->buf);
++		DHD_INFO(("Auth:%d\n", auth));
++
++		if (auth != WL_AUTH_OPEN_SYSTEM) {
++			/* If AP is with security then enable WLC_E_PSK_SUP event checking */
++			dhd_set_join_error(pub, WLC_WPA_MASK);
++		} else {
++			/* If AP is with open then disable WLC_E_PSK_SUP event checking */
++			dhd_clear_join_error(pub, WLC_WPA_MASK);
++		}
++	}
++#endif /* REPORT_FATAL_TIMEOUTS */
++	net = dhd_idx2net(pub, ifidx);
++	if (!net) {
++		bcmerror = BCME_BADARG;
++		goto done;
++	}
++
++	/* check for local dhd ioctl and handle it */
++	if (ioc->driver == DHD_IOCTL_MAGIC) {
++		/* This is a DHD IOVAR, truncate buflen to DHD_IOCTL_MAXLEN */
++		if (data_buf)
++			buflen = MIN(ioc->len, DHD_IOCTL_MAXLEN);
++		bcmerror = dhd_ioctl((void *)pub, ioc, data_buf, buflen);
++		if (bcmerror)
++			pub->bcmerror = bcmerror;
++		goto done;
++	}
++
++	/* This is a WL IOVAR, truncate buflen to WLC_IOCTL_MAXLEN */
++	if (data_buf)
++		buflen = MIN(ioc->len, WLC_IOCTL_MAXLEN);
++
++#ifndef BCMDBUS
++	/* send to dongle (must be up, and wl). */
++	if (pub->busstate == DHD_BUS_DOWN || pub->busstate == DHD_BUS_LOAD) {
++		if ((!pub->dongle_trap_occured) && allow_delay_fwdl) {
++			int ret;
++			if (atomic_read(&exit_in_progress)) {
++				DHD_ERROR(("%s module exit in progress\n", __func__));
++				bcmerror = BCME_DONGLE_DOWN;
++				goto done;
++			}
++			ret = dhd_bus_start(pub);
++			if (ret != 0) {
++				DHD_ERROR(("%s: failed with code %d\n", __FUNCTION__, ret));
++				bcmerror = BCME_DONGLE_DOWN;
++				goto done;
++			}
++		} else {
++			bcmerror = BCME_DONGLE_DOWN;
++			goto done;
++		}
++	}
++
++	if (!pub->iswl) {
++		bcmerror = BCME_DONGLE_DOWN;
++		goto done;
++	}
++#endif /* !BCMDBUS */
++
++	/*
++	 * Flush the TX queue if required for proper message serialization:
++	 * Intercept WLC_SET_KEY IOCTL - serialize M4 send and set key IOCTL to
++	 * prevent M4 encryption and
++	 * intercept WLC_DISASSOC IOCTL - serialize WPS-DONE and WLC_DISASSOC IOCTL to
++	 * prevent disassoc frame being sent before WPS-DONE frame.
++	 */
++	if (ioc->cmd == WLC_SET_KEY ||
++	    (ioc->cmd == WLC_SET_VAR && data_buf != NULL &&
++	     strncmp("wsec_key", data_buf, 9) == 0) ||
++	    (ioc->cmd == WLC_SET_VAR && data_buf != NULL &&
++	     strncmp("bsscfg:wsec_key", data_buf, 15) == 0) ||
++	    ioc->cmd == WLC_DISASSOC)
++		dhd_wait_pend8021x(net);
++
++#ifdef WLMEDIA_HTSF
++	if (data_buf) {
++		/*  short cut wl ioctl calls here  */
++		if (strcmp("htsf", data_buf) == 0) {
++			dhd_ioctl_htsf_get(dhd, 0);
++			return BCME_OK;
++		}
++
++		if (strcmp("htsflate", data_buf) == 0) {
++			if (ioc->set) {
++				memset(ts, 0, sizeof(tstamp_t)*TSMAX);
++				memset(&maxdelayts, 0, sizeof(tstamp_t));
++				maxdelay = 0;
++				tspktcnt = 0;
++				maxdelaypktno = 0;
++				memset(&vi_d1.bin, 0, sizeof(uint32)*NUMBIN);
++				memset(&vi_d2.bin, 0, sizeof(uint32)*NUMBIN);
++				memset(&vi_d3.bin, 0, sizeof(uint32)*NUMBIN);
++				memset(&vi_d4.bin, 0, sizeof(uint32)*NUMBIN);
++			} else {
++				dhd_dump_latency();
++			}
++			return BCME_OK;
++		}
++		if (strcmp("htsfclear", data_buf) == 0) {
++			memset(&vi_d1.bin, 0, sizeof(uint32)*NUMBIN);
++			memset(&vi_d2.bin, 0, sizeof(uint32)*NUMBIN);
++			memset(&vi_d3.bin, 0, sizeof(uint32)*NUMBIN);
++			memset(&vi_d4.bin, 0, sizeof(uint32)*NUMBIN);
++			htsf_seqnum = 0;
++			return BCME_OK;
++		}
++		if (strcmp("htsfhis", data_buf) == 0) {
++			dhd_dump_htsfhisto(&vi_d1, "H to D");
++			dhd_dump_htsfhisto(&vi_d2, "D to D");
++			dhd_dump_htsfhisto(&vi_d3, "D to H");
++			dhd_dump_htsfhisto(&vi_d4, "H to H");
++			return BCME_OK;
++		}
++		if (strcmp("tsport", data_buf) == 0) {
++			if (ioc->set) {
++				memcpy(&tsport, data_buf + 7, 4);
++			} else {
++				DHD_ERROR(("current timestamp port: %d \n", tsport));
++			}
++			return BCME_OK;
++		}
++	}
++#endif /* WLMEDIA_HTSF */
++
++	if ((ioc->cmd == WLC_SET_VAR || ioc->cmd == WLC_GET_VAR) &&
++		data_buf != NULL && strncmp("rpc_", data_buf, 4) == 0) {
++#ifdef BCM_FD_AGGR
++		bcmerror = dhd_fdaggr_ioctl(pub, ifidx, (wl_ioctl_t *)ioc, data_buf, buflen);
++#else
++		bcmerror = BCME_UNSUPPORTED;
++#endif
++		goto done;
++	}
++	bcmerror = dhd_wl_ioctl(pub, ifidx, (wl_ioctl_t *)ioc, data_buf, buflen);
++
++#ifdef WL_MONITOR
++	/* Intercept monitor ioctl here, add/del monitor if */
++	if (bcmerror == BCME_OK && ioc->cmd == WLC_SET_MONITOR) {
++		dhd_set_monitor(pub, ifidx, *(int32*)data_buf);
++	}
++#endif
++
++#ifdef REPORT_FATAL_TIMEOUTS
++	if (ioc->cmd == WLC_SCAN && bcmerror == 0) {
++		dhd_start_scan_timer(pub);
++	}
++	if (ioc->cmd == WLC_SET_SSID && bcmerror == 0) {
++		dhd_start_join_timer(pub);
++	}
++#endif  /* REPORT_FATAL_TIMEOUTS */
++
++done:
++	dhd_check_hang(net, pub, bcmerror);
++
++	return bcmerror;
++}
++
++static int
++dhd_ioctl_entry(struct net_device *net, struct ifreq *ifr, int cmd)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(net);
++	dhd_ioctl_t ioc;
++	int bcmerror = 0;
++	int ifidx;
++	int ret;
++	void *local_buf = NULL;
++	void __user *ioc_buf_user = NULL;
++	u16 buflen = 0;
++
++	if (atomic_read(&exit_in_progress)) {
++		DHD_ERROR(("%s module exit in progress\n", __func__));
++		bcmerror = BCME_DONGLE_DOWN;
++		return OSL_ERROR(bcmerror);
++	}
++
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK(&dhd->pub);
++
++	/* Interface up check for built-in type */
++	if (!dhd_download_fw_on_driverload && dhd->pub.up == FALSE) {
++		DHD_ERROR(("%s: Interface is down \n", __FUNCTION__));
++		DHD_PERIM_UNLOCK(&dhd->pub);
++		DHD_OS_WAKE_UNLOCK(&dhd->pub);
++		return OSL_ERROR(BCME_NOTUP);
++	}
++
++	ifidx = dhd_net2idx(dhd, net);
++	DHD_TRACE(("%s: ifidx %d, cmd 0x%04x\n", __FUNCTION__, ifidx, cmd));
++
++	if (ifidx == DHD_BAD_IF) {
++		DHD_ERROR(("%s: BAD IF\n", __FUNCTION__));
++		DHD_PERIM_UNLOCK(&dhd->pub);
++		DHD_OS_WAKE_UNLOCK(&dhd->pub);
++		return -1;
++	}
++
++#if defined(WL_WIRELESS_EXT)
++	/* linux wireless extensions */
++	if ((cmd >= SIOCIWFIRST) && (cmd <= SIOCIWLAST)) {
++		/* may recurse, do NOT lock */
++		ret = wl_iw_ioctl(net, ifr, cmd);
++		DHD_PERIM_UNLOCK(&dhd->pub);
++		DHD_OS_WAKE_UNLOCK(&dhd->pub);
++		return ret;
++	}
++#endif /* defined(WL_WIRELESS_EXT) */
++
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 4, 2)
++	if (cmd == SIOCETHTOOL) {
++		ret = dhd_ethtool(dhd, (void*)ifr->ifr_data);
++		DHD_PERIM_UNLOCK(&dhd->pub);
++		DHD_OS_WAKE_UNLOCK(&dhd->pub);
++		return ret;
++	}
++#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 4, 2) */
++
++	if (cmd == SIOCDEVPRIVATE+1) {
++		ret = wl_android_priv_cmd(net, ifr, cmd);
++		dhd_check_hang(net, &dhd->pub, ret);
++		DHD_PERIM_UNLOCK(&dhd->pub);
++		DHD_OS_WAKE_UNLOCK(&dhd->pub);
++		return ret;
++	}
++
++	if (cmd != SIOCDEVPRIVATE) {
++		DHD_PERIM_UNLOCK(&dhd->pub);
++		DHD_OS_WAKE_UNLOCK(&dhd->pub);
++		return -EOPNOTSUPP;
++	}
++
++	memset(&ioc, 0, sizeof(ioc));
++
++#ifdef CONFIG_COMPAT
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 6, 0))
++	if (in_compat_syscall())
++#else
++	if (is_compat_task())
++#endif
++	{
++		compat_wl_ioctl_t compat_ioc;
++		if (copy_from_user(&compat_ioc, ifr->ifr_data, sizeof(compat_wl_ioctl_t))) {
++			bcmerror = BCME_BADADDR;
++			goto done;
++		}
++		ioc.cmd = compat_ioc.cmd;
++		if (ioc.cmd & WLC_SPEC_FLAG) {
++			memset(&ioc, 0, sizeof(ioc));
++			/* Copy the ioc control structure part of ioctl request */
++			if (copy_from_user(&ioc, ifr->ifr_data, sizeof(wl_ioctl_t))) {
++				bcmerror = BCME_BADADDR;
++				goto done;
++			}
++			ioc.cmd &= ~WLC_SPEC_FLAG; /* Clear the FLAG */
++
++			/* To differentiate between wl and dhd read 4 more byes */
++			if ((copy_from_user(&ioc.driver, (char *)ifr->ifr_data + sizeof(wl_ioctl_t),
++				sizeof(uint)) != 0)) {
++				bcmerror = BCME_BADADDR;
++				goto done;
++			}
++
++		} else { /* ioc.cmd & WLC_SPEC_FLAG */
++			ioc.buf = compat_ptr(compat_ioc.buf);
++			ioc.len = compat_ioc.len;
++			ioc.set = compat_ioc.set;
++			ioc.used = compat_ioc.used;
++			ioc.needed = compat_ioc.needed;
++			/* To differentiate between wl and dhd read 4 more byes */
++			if ((copy_from_user(&ioc.driver, (char *)ifr->ifr_data + sizeof(compat_wl_ioctl_t),
++				sizeof(uint)) != 0)) {
++				bcmerror = BCME_BADADDR;
++				goto done;
++			}
++		} /* ioc.cmd & WLC_SPEC_FLAG */
++	} else
++#endif /* CONFIG_COMPAT */
++	{
++		/* Copy the ioc control structure part of ioctl request */
++		if (copy_from_user(&ioc, ifr->ifr_data, sizeof(wl_ioctl_t))) {
++			bcmerror = BCME_BADADDR;
++			goto done;
++		}
++#ifdef CONFIG_COMPAT
++		ioc.cmd &= ~WLC_SPEC_FLAG; /* make sure it was clear when it isn't a compat task*/
++#endif
++
++		/* To differentiate between wl and dhd read 4 more byes */
++		if ((copy_from_user(&ioc.driver, (char *)ifr->ifr_data + sizeof(wl_ioctl_t),
++			sizeof(uint)) != 0)) {
++			bcmerror = BCME_BADADDR;
++			goto done;
++		}
++	}
++
++#ifndef CONFIG_VTS_SUPPORT
++	if (!capable(CAP_NET_ADMIN)) {
++		bcmerror = BCME_EPERM;
++		goto done;
++	}
++#endif
++
++	/* Take backup of ioc.buf and restore later */
++	ioc_buf_user = ioc.buf;
++
++	if (ioc.len > 0) {
++		buflen = MIN(ioc.len, DHD_IOCTL_MAXLEN);
++		if (!(local_buf = MALLOC(dhd->pub.osh, buflen+1))) {
++			bcmerror = BCME_NOMEM;
++			goto done;
++		}
++
++		DHD_PERIM_UNLOCK(&dhd->pub);
++		if (copy_from_user(local_buf, ioc.buf, buflen)) {
++			DHD_PERIM_LOCK(&dhd->pub);
++			bcmerror = BCME_BADADDR;
++			goto done;
++		}
++		DHD_PERIM_LOCK(&dhd->pub);
++
++		*((char *)local_buf + buflen) = '\0';
++
++		/* For some platforms accessing userspace memory
++		 * of ioc.buf is causing kernel panic, so to avoid that
++		 * make ioc.buf pointing to kernel space memory local_buf
++		 */
++		ioc.buf = local_buf;
++	}
++
++	/* Skip all the non DHD iovars (wl iovars) after f/w hang */
++	if (ioc.driver != DHD_IOCTL_MAGIC && dhd->pub.hang_was_sent) {
++		DHD_TRACE(("%s: HANG was sent up earlier\n", __FUNCTION__));
++		DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_ENABLE(&dhd->pub, DHD_EVENT_TIMEOUT_MS);
++		bcmerror = BCME_DONGLE_DOWN;
++		goto done;
++	}
++
++	bcmerror = dhd_ioctl_process(&dhd->pub, ifidx, &ioc, local_buf);
++
++	/* Restore back userspace pointer to ioc.buf */
++	ioc.buf = ioc_buf_user;
++
++	if (!bcmerror && buflen && local_buf && ioc.buf) {
++		DHD_PERIM_UNLOCK(&dhd->pub);
++		if (copy_to_user(ioc.buf, local_buf, buflen))
++			bcmerror = -EFAULT;
++		DHD_PERIM_LOCK(&dhd->pub);
++	}
++
++done:
++	if (local_buf)
++		MFREE(dhd->pub.osh, local_buf, buflen+1);
++
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++
++	return OSL_ERROR(bcmerror);
++}
++
++
++#ifdef FIX_CPU_MIN_CLOCK
++static int dhd_init_cpufreq_fix(dhd_info_t *dhd)
++{
++	if (dhd) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++		mutex_init(&dhd->cpufreq_fix);
++#endif
++		dhd->cpufreq_fix_status = FALSE;
++	}
++	return 0;
++}
++
++static void dhd_fix_cpu_freq(dhd_info_t *dhd)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	mutex_lock(&dhd->cpufreq_fix);
++#endif
++	if (dhd && !dhd->cpufreq_fix_status) {
++		pm_qos_add_request(&dhd->dhd_cpu_qos, PM_QOS_CPU_FREQ_MIN, 300000);
++#ifdef FIX_BUS_MIN_CLOCK
++		pm_qos_add_request(&dhd->dhd_bus_qos, PM_QOS_BUS_THROUGHPUT, 400000);
++#endif /* FIX_BUS_MIN_CLOCK */
++		DHD_ERROR(("pm_qos_add_requests called\n"));
++
++		dhd->cpufreq_fix_status = TRUE;
++	}
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	mutex_unlock(&dhd->cpufreq_fix);
++#endif
++}
++
++static void dhd_rollback_cpu_freq(dhd_info_t *dhd)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	mutex_lock(&dhd ->cpufreq_fix);
++#endif
++	if (dhd && dhd->cpufreq_fix_status != TRUE) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++		mutex_unlock(&dhd->cpufreq_fix);
++#endif
++		return;
++	}
++
++	pm_qos_remove_request(&dhd->dhd_cpu_qos);
++#ifdef FIX_BUS_MIN_CLOCK
++	pm_qos_remove_request(&dhd->dhd_bus_qos);
++#endif /* FIX_BUS_MIN_CLOCK */
++	DHD_ERROR(("pm_qos_add_requests called\n"));
++
++	dhd->cpufreq_fix_status = FALSE;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	mutex_unlock(&dhd->cpufreq_fix);
++#endif
++}
++#endif /* FIX_CPU_MIN_CLOCK */
++
++#if defined(BT_OVER_SDIO)
++
++void
++dhdsdio_bus_usr_cnt_inc(dhd_pub_t *dhdp)
++{
++	dhdp->info->bus_user_count++;
++}
++
++void
++dhdsdio_bus_usr_cnt_dec(dhd_pub_t *dhdp)
++{
++	dhdp->info->bus_user_count--;
++}
++
++/* Return values:
++ * Success: Returns 0
++ * Failure: Returns -1 or errono code
++ */
++int
++dhd_bus_get(wlan_bt_handle_t handle, bus_owner_t owner)
++{
++	dhd_pub_t *dhdp = (dhd_pub_t *)handle;
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++	int ret = 0;
++
++	mutex_lock(&dhd->bus_user_lock);
++	++dhd->bus_user_count;
++	if (dhd->bus_user_count < 0) {
++		DHD_ERROR(("%s(): bus_user_count is negative, which is invalid\n", __FUNCTION__));
++		ret = -1;
++		goto exit;
++	}
++
++	if (dhd->bus_user_count == 1) {
++
++		dhd->pub.hang_was_sent = 0;
++
++		/* First user, turn on WL_REG, start the bus */
++		DHD_ERROR(("%s(): First user Turn On WL_REG & start the bus", __FUNCTION__));
++
++		if (!wifi_platform_set_power(dhd->adapter, TRUE, WIFI_TURNON_DELAY)) {
++			/* Enable F1 */
++			ret = dhd_bus_resume(dhdp, 0);
++			if (ret) {
++				DHD_ERROR(("%s(): Failed to enable F1, err=%d\n",
++					__FUNCTION__, ret));
++				goto exit;
++			}
++		}
++
++		dhd_update_fw_nv_path(dhd);
++		/* update firmware and nvram path to sdio bus */
++		dhd_bus_update_fw_nv_path(dhd->pub.bus,
++			dhd->fw_path, dhd->nv_path);
++		/* download the firmware, Enable F2 */
++		/* TODO: Should be done only in case of FW switch */
++		ret = dhd_bus_devreset(dhdp, FALSE);
++		dhd_bus_resume(dhdp, 1);
++		if (!ret) {
++			if (dhd_sync_with_dongle(&dhd->pub) < 0) {
++				DHD_ERROR(("%s(): Sync with dongle failed!!\n", __FUNCTION__));
++				ret = -EFAULT;
++			}
++		} else {
++			DHD_ERROR(("%s(): Failed to download, err=%d\n", __FUNCTION__, ret));
++		}
++	} else {
++		DHD_ERROR(("%s(): BUS is already acquired, just increase the count %d \r\n",
++			__FUNCTION__, dhd->bus_user_count));
++	}
++exit:
++	mutex_unlock(&dhd->bus_user_lock);
++	return ret;
++}
++EXPORT_SYMBOL(dhd_bus_get);
++
++/* Return values:
++ * Success: Returns 0
++ * Failure: Returns -1 or errono code
++ */
++int
++dhd_bus_put(wlan_bt_handle_t handle, bus_owner_t owner)
++{
++	dhd_pub_t *dhdp = (dhd_pub_t *)handle;
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++	int ret = 0;
++	BCM_REFERENCE(owner);
++
++	mutex_lock(&dhd->bus_user_lock);
++	--dhd->bus_user_count;
++	if (dhd->bus_user_count < 0) {
++		DHD_ERROR(("%s(): bus_user_count is negative, which is invalid\n", __FUNCTION__));
++		dhd->bus_user_count = 0;
++		ret = -1;
++		goto exit;
++	}
++
++	if (dhd->bus_user_count == 0) {
++		/* Last user, stop the bus and turn Off WL_REG */
++		DHD_ERROR(("%s(): There are no owners left Trunf Off WL_REG & stop the bus \r\n",
++			__FUNCTION__));
++#ifdef PROP_TXSTATUS
++		if (dhd->pub.wlfc_enabled) {
++			dhd_wlfc_deinit(&dhd->pub);
++		}
++#endif /* PROP_TXSTATUS */
++#ifdef PNO_SUPPORT
++		if (dhd->pub.pno_state) {
++			dhd_pno_deinit(&dhd->pub);
++		}
++#endif /* PNO_SUPPORT */
++#ifdef RTT_SUPPORT
++		if (dhd->pub.rtt_state) {
++			dhd_rtt_deinit(&dhd->pub);
++		}
++#endif /* RTT_SUPPORT */
++		ret = dhd_bus_devreset(dhdp, TRUE);
++		if (!ret) {
++			dhd_bus_suspend(dhdp);
++			wifi_platform_set_power(dhd->adapter, FALSE, WIFI_TURNOFF_DELAY);
++		}
++	} else {
++		DHD_ERROR(("%s(): Other owners using bus, decrease the count %d \r\n",
++			__FUNCTION__, dhd->bus_user_count));
++	}
++exit:
++	mutex_unlock(&dhd->bus_user_lock);
++	return ret;
++}
++EXPORT_SYMBOL(dhd_bus_put);
++
++int
++dhd_net_bus_get(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	return dhd_bus_get(&dhd->pub, WLAN_MODULE);
++}
++
++int
++dhd_net_bus_put(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	return dhd_bus_put(&dhd->pub, WLAN_MODULE);
++}
++
++/*
++ * Function to enable the Bus Clock
++ * Returns BCME_OK on success and BCME_xxx on failure
++ *
++ * This function is not callable from non-sleepable context
++ */
++int dhd_bus_clk_enable(wlan_bt_handle_t handle, bus_owner_t owner)
++{
++	dhd_pub_t *dhdp = (dhd_pub_t *)handle;
++
++	int ret;
++
++	dhd_os_sdlock(dhdp);
++	/*
++	 * The second argument is TRUE, that means, we expect
++	 * the function to "wait" until the clocks are really
++	 * available
++	 */
++	ret = __dhdsdio_clk_enable(dhdp->bus, owner, TRUE);
++	dhd_os_sdunlock(dhdp);
++
++	return ret;
++}
++EXPORT_SYMBOL(dhd_bus_clk_enable);
++
++/*
++ * Function to disable the Bus Clock
++ * Returns BCME_OK on success and BCME_xxx on failure
++ *
++ * This function is not callable from non-sleepable context
++ */
++int dhd_bus_clk_disable(wlan_bt_handle_t handle, bus_owner_t owner)
++{
++	dhd_pub_t *dhdp = (dhd_pub_t *)handle;
++
++	int ret;
++
++	dhd_os_sdlock(dhdp);
++	/*
++	 * The second argument is TRUE, that means, we expect
++	 * the function to "wait" until the clocks are really
++	 * disabled
++	 */
++	ret = __dhdsdio_clk_disable(dhdp->bus, owner, TRUE);
++	dhd_os_sdunlock(dhdp);
++
++	return ret;
++}
++EXPORT_SYMBOL(dhd_bus_clk_disable);
++
++/*
++ * Function to reset bt_use_count counter to zero.
++ *
++ * This function is not callable from non-sleepable context
++ */
++void dhd_bus_reset_bt_use_count(wlan_bt_handle_t handle)
++{
++	dhd_pub_t *dhdp = (dhd_pub_t *)handle;
++
++	/* take the lock and reset bt use count */
++	dhd_os_sdlock(dhdp);
++	dhdsdio_reset_bt_use_count(dhdp->bus);
++	dhd_os_sdunlock(dhdp);
++}
++EXPORT_SYMBOL(dhd_bus_reset_bt_use_count);
++
++#endif /* BT_OVER_SDIO */
++
++#define MAX_TRY_CNT             5 /* Number of tries to disable deepsleep */
++int dhd_deepsleep(dhd_info_t *dhd, int flag)
++{
++	char iovbuf[20];
++	uint powervar = 0;
++	dhd_pub_t *dhdp;
++	int cnt = 0;
++	int ret = 0;
++
++	dhdp = &dhd->pub;
++
++	switch (flag) {
++		case 1 :  /* Deepsleep on */
++			DHD_ERROR(("dhd_deepsleep: ON\n"));
++			/* give some time to sysioc_work before deepsleep */
++			OSL_SLEEP(200);
++#ifdef PKT_FILTER_SUPPORT
++			/* disable pkt filter */
++			dhd_enable_packet_filter(0, dhdp);
++#endif /* PKT_FILTER_SUPPORT */
++			/* Disable MPC */
++			powervar = 0;
++			memset(iovbuf, 0, sizeof(iovbuf));
++			bcm_mkiovar("mpc", (char *)&powervar, 4, iovbuf, sizeof(iovbuf));
++			dhd_wl_ioctl_cmd(dhdp, WLC_SET_VAR, iovbuf, sizeof(iovbuf), TRUE, 0);
++
++			/* Enable Deepsleep */
++			powervar = 1;
++			memset(iovbuf, 0, sizeof(iovbuf));
++			bcm_mkiovar("deepsleep", (char *)&powervar, 4, iovbuf, sizeof(iovbuf));
++			dhd_wl_ioctl_cmd(dhdp, WLC_SET_VAR, iovbuf, sizeof(iovbuf), TRUE, 0);
++			break;
++
++		case 0: /* Deepsleep Off */
++			DHD_ERROR(("dhd_deepsleep: OFF\n"));
++
++			/* Disable Deepsleep */
++			for (cnt = 0; cnt < MAX_TRY_CNT; cnt++) {
++				powervar = 0;
++				memset(iovbuf, 0, sizeof(iovbuf));
++				bcm_mkiovar("deepsleep", (char *)&powervar, 4,
++					iovbuf, sizeof(iovbuf));
++				dhd_wl_ioctl_cmd(dhdp, WLC_SET_VAR, iovbuf,
++					sizeof(iovbuf), TRUE, 0);
++
++				memset(iovbuf, 0, sizeof(iovbuf));
++				bcm_mkiovar("deepsleep", (char *)&powervar, 4,
++					iovbuf, sizeof(iovbuf));
++				if ((ret = dhd_wl_ioctl_cmd(dhdp, WLC_GET_VAR, iovbuf,
++					sizeof(iovbuf),	FALSE, 0)) < 0) {
++					DHD_ERROR(("the error of dhd deepsleep status"
++						" ret value :%d\n", ret));
++				} else {
++					if (!(*(int *)iovbuf)) {
++						DHD_ERROR(("deepsleep mode is 0,"
++							" count: %d\n", cnt));
++						break;
++					}
++				}
++			}
++
++			/* Enable MPC */
++			powervar = 1;
++			memset(iovbuf, 0, sizeof(iovbuf));
++			bcm_mkiovar("mpc", (char *)&powervar, 4, iovbuf, sizeof(iovbuf));
++			dhd_wl_ioctl_cmd(dhdp, WLC_SET_VAR, iovbuf, sizeof(iovbuf), TRUE, 0);
++			break;
++	}
++
++	return 0;
++}
++
++static int
++dhd_stop(struct net_device *net)
++{
++	int ifidx = 0;
++#ifdef WL_CFG80211
++	unsigned long flags = 0;
++#endif /* WL_CFG80211 */
++	dhd_info_t *dhd = DHD_DEV_INFO(net);
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK(&dhd->pub);
++	printf("%s: Enter %p\n", __FUNCTION__, net);
++	dhd->pub.rxcnt_timeout = 0;
++	dhd->pub.txcnt_timeout = 0;
++
++#ifdef BCMPCIE
++	dhd->pub.d3ackcnt_timeout = 0;
++#endif /* BCMPCIE */
++
++	if (dhd->pub.up == 0) {
++		goto exit;
++	}
++#if defined(DHD_HANG_SEND_UP_TEST)
++	if (dhd->pub.req_hang_type) {
++		DHD_ERROR(("%s, Clear HANG test request 0x%x\n",
++			__FUNCTION__, dhd->pub.req_hang_type));
++		dhd->pub.req_hang_type = 0;
++	}
++#endif /* DHD_HANG_SEND_UP_TEST */
++
++	dhd_if_flush_sta(DHD_DEV_IFP(net));
++
++	/* Disable Runtime PM before interface down */
++	DHD_DISABLE_RUNTIME_PM(&dhd->pub);
++
++#ifdef FIX_CPU_MIN_CLOCK
++	if (dhd_get_fw_mode(dhd) == DHD_FLAG_HOSTAP_MODE)
++		dhd_rollback_cpu_freq(dhd);
++#endif /* FIX_CPU_MIN_CLOCK */
++
++	ifidx = dhd_net2idx(dhd, net);
++	BCM_REFERENCE(ifidx);
++
++	/* Set state and stop OS transmissions */
++	netif_stop_queue(net);
++#ifdef WL_CFG80211
++	spin_lock_irqsave(&dhd->pub.up_lock, flags);
++	dhd->pub.up = 0;
++	spin_unlock_irqrestore(&dhd->pub.up_lock, flags);
++#else
++	dhd->pub.up = 0;
++#endif /* WL_CFG80211 */
++
++#ifdef WL_CFG80211
++	if (ifidx == 0) {
++		dhd_if_t *ifp;
++		wl_cfg80211_down(net);
++
++		ifp = dhd->iflist[0];
++		ASSERT(ifp && ifp->net);
++		/*
++		 * For CFG80211: Clean up all the left over virtual interfaces
++		 * when the primary Interface is brought down. [ifconfig wlan0 down]
++		 */
++		if (!dhd_download_fw_on_driverload) {
++			if ((dhd->dhd_state & DHD_ATTACH_STATE_ADD_IF) &&
++				(dhd->dhd_state & DHD_ATTACH_STATE_CFG80211)) {
++				int i;
++#ifdef WL_CFG80211_P2P_DEV_IF
++				wl_cfg80211_del_p2p_wdev(net);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++				dhd_net_if_lock_local(dhd);
++				for (i = 1; i < DHD_MAX_IFS; i++)
++					dhd_remove_if(&dhd->pub, i, FALSE);
++
++				if (ifp && ifp->net) {
++					dhd_if_del_sta_list(ifp);
++				}
++#ifdef ARP_OFFLOAD_SUPPORT
++				if (dhd_inetaddr_notifier_registered) {
++					dhd_inetaddr_notifier_registered = FALSE;
++					unregister_inetaddr_notifier(&dhd_inetaddr_notifier);
++				}
++#endif /* ARP_OFFLOAD_SUPPORT */
++#if defined(CONFIG_IPV6) && defined(IPV6_NDO_SUPPORT)
++				if (dhd_inet6addr_notifier_registered) {
++					dhd_inet6addr_notifier_registered = FALSE;
++					unregister_inet6addr_notifier(&dhd_inet6addr_notifier);
++				}
++#endif /* CONFIG_IPV6 && IPV6_NDO_SUPPORT */
++				dhd_net_if_unlock_local(dhd);
++			}
++#if 0
++			// terence 20161024: remove this to prevent dev_close() get stuck in dhd_hang_process
++			cancel_work_sync(dhd->dhd_deferred_wq);
++#endif
++
++#ifdef SHOW_LOGTRACE
++			/* Wait till event_log_dispatcher_work finishes */
++			cancel_work_sync(&dhd->event_log_dispatcher_work);
++#endif /* SHOW_LOGTRACE */
++
++#if defined(DHD_LB_RXP)
++			__skb_queue_purge(&dhd->rx_pend_queue);
++#endif /* DHD_LB_RXP */
++
++#if defined(DHD_LB_TXP)
++			skb_queue_purge(&dhd->tx_pend_queue);
++#endif /* DHD_LB_TXP */
++		}
++
++		argos_register_notifier_deinit();
++#ifdef DHDTCPACK_SUPPRESS
++		dhd_tcpack_suppress_set(&dhd->pub, TCPACK_SUP_OFF);
++#endif /* DHDTCPACK_SUPPRESS */
++#if defined(DHD_LB_RXP)
++		if (ifp->net == dhd->rx_napi_netdev) {
++			DHD_INFO(("%s napi<%p> disabled ifp->net<%p,%s>\n",
++				__FUNCTION__, &dhd->rx_napi_struct, net, net->name));
++			skb_queue_purge(&dhd->rx_napi_queue);
++			napi_disable(&dhd->rx_napi_struct);
++			netif_napi_del(&dhd->rx_napi_struct);
++			dhd->rx_napi_netdev = NULL;
++		}
++#endif /* DHD_LB_RXP */
++	}
++#endif /* WL_CFG80211 */
++
++	DHD_SSSR_DUMP_DEINIT(&dhd->pub);
++
++#ifdef PROP_TXSTATUS
++	dhd_wlfc_cleanup(&dhd->pub, NULL, 0);
++#endif
++#ifdef SHOW_LOGTRACE
++	if (!dhd_download_fw_on_driverload) {
++		/* Release the skbs from queue for WLC_E_TRACE event */
++		dhd_event_logtrace_flush_queue(&dhd->pub);
++		if (dhd->dhd_state & DHD_ATTACH_LOGTRACE_INIT) {
++			if (dhd->event_data.fmts) {
++				MFREE(dhd->pub.osh, dhd->event_data.fmts,
++					dhd->event_data.fmts_size);
++				dhd->event_data.fmts = NULL;
++			}
++			if (dhd->event_data.raw_fmts) {
++				MFREE(dhd->pub.osh, dhd->event_data.raw_fmts,
++					dhd->event_data.raw_fmts_size);
++				dhd->event_data.raw_fmts = NULL;
++			}
++			if (dhd->event_data.raw_sstr) {
++				MFREE(dhd->pub.osh, dhd->event_data.raw_sstr,
++					dhd->event_data.raw_sstr_size);
++				dhd->event_data.raw_sstr = NULL;
++			}
++			if (dhd->event_data.rom_raw_sstr) {
++				MFREE(dhd->pub.osh, dhd->event_data.rom_raw_sstr,
++					dhd->event_data.rom_raw_sstr_size);
++				dhd->event_data.rom_raw_sstr = NULL;
++			}
++			dhd->dhd_state &= ~DHD_ATTACH_LOGTRACE_INIT;
++		}
++	}
++#endif /* SHOW_LOGTRACE */
++#ifdef APF
++	dhd_dev_apf_delete_filter(net);
++#endif /* APF */
++
++	/* Stop the protocol module */
++	dhd_prot_stop(&dhd->pub);
++
++	OLD_MOD_DEC_USE_COUNT;
++exit:
++#if defined(WL_WIRELESS_EXT)
++	if (ifidx == 0) {
++		wl_iw_down(net, &dhd->pub);
++	}
++#endif /* defined(WL_WIRELESS_EXT) */
++#ifdef WL_ESCAN
++	if (ifidx == 0) {
++		wl_escan_down(net, &dhd->pub);
++	}
++#endif /* WL_ESCAN */
++	if (ifidx == 0 && !dhd_download_fw_on_driverload) {
++#if defined(BT_OVER_SDIO)
++		dhd_bus_put(&dhd->pub, WLAN_MODULE);
++		wl_android_set_wifi_on_flag(FALSE);
++#else
++		wl_android_wifi_off(net, TRUE);
++#if defined(WL_EXT_IAPSTA) || defined(USE_IW) || defined(WL_ESCAN)
++#ifdef WL_EXT_IAPSTA
++		wl_ext_iapsta_dettach_netdev(net, ifidx);
++#endif /* WL_EXT_IAPSTA */
++#ifdef WL_ESCAN
++			wl_escan_event_dettach(net, &dhd->pub);
++#endif /* WL_ESCAN */
++			wl_ext_event_dettach_netdev(net, ifidx);
++#endif /* WL_EXT_IAPSTA || USE_IW || WL_ESCAN */
++	} else {
++		if (dhd->pub.conf->deepsleep)
++			dhd_deepsleep(dhd, 1);
++#endif /* BT_OVER_SDIO */
++	}
++	dhd->pub.hang_was_sent = 0;
++
++	/* Clear country spec for for built-in type driver */
++	if (!dhd_download_fw_on_driverload) {
++		dhd->pub.dhd_cspec.country_abbrev[0] = 0x00;
++		dhd->pub.dhd_cspec.rev = 0;
++		dhd->pub.dhd_cspec.ccode[0] = 0x00;
++	}
++
++#ifdef BCMDBGFS
++	dhd_dbgfs_remove();
++#endif
++
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++
++	/* Destroy wakelock */
++	if (!dhd_download_fw_on_driverload &&
++		(dhd->dhd_state & DHD_ATTACH_STATE_WAKELOCKS_INIT)) {
++		DHD_OS_WAKE_LOCK_DESTROY(dhd);
++		dhd->dhd_state &= ~DHD_ATTACH_STATE_WAKELOCKS_INIT;
++	}
++	printf("%s: Exit\n", __FUNCTION__);
++
++	return 0;
++}
++
++#if defined(WL_CFG80211) && defined(USE_INITIAL_SHORT_DWELL_TIME)
++extern bool g_first_broadcast_scan;
++#endif 
++
++#ifdef WL11U
++static int dhd_interworking_enable(dhd_pub_t *dhd)
++{
++	uint32 enable = true;
++	int ret = BCME_OK;
++
++	ret = dhd_iovar(dhd, 0, "interworking", (char *)&enable, sizeof(enable), NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: enableing interworking failed, ret=%d\n", __FUNCTION__, ret));
++	}
++
++	return ret;
++}
++#endif /* WL11u */
++
++static int
++dhd_open(struct net_device *net)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(net);
++#ifdef TOE
++	uint32 toe_ol;
++#endif
++#ifdef BCM_FD_AGGR
++	char iovbuf[WLC_IOCTL_SMLEN];
++	dbus_config_t config;
++	uint32 agglimit = 0;
++	uint32 rpc_agg = BCM_RPC_TP_DNGL_AGG_DPC; /* host aggr not enabled yet */
++#endif /* BCM_FD_AGGR */
++	int ifidx;
++	int32 ret = 0;
++#if defined(OOB_INTR_ONLY)
++	uint32 bus_type = -1;
++	uint32 bus_num = -1;
++	uint32 slot_num = -1;
++	wifi_adapter_info_t *adapter = NULL;
++#endif
++#if defined(WL_EXT_IAPSTA) && defined(ISAM_PREINIT)
++	int bytes_written = 0;
++#endif
++
++	if (!dhd_download_fw_on_driverload) {
++		if (!dhd_driver_init_done) {
++			DHD_ERROR(("%s: WLAN driver is not initialized\n", __FUNCTION__));
++			return -1;
++		}
++	}
++
++	printf("%s: Enter %p\n", __FUNCTION__, net);
++	DHD_MUTEX_LOCK();
++	/* Init wakelock */
++	if (!dhd_download_fw_on_driverload) {
++		if (!(dhd->dhd_state & DHD_ATTACH_STATE_WAKELOCKS_INIT)) {
++			DHD_OS_WAKE_LOCK_INIT(dhd);
++			dhd->dhd_state |= DHD_ATTACH_STATE_WAKELOCKS_INIT;
++		}
++#ifdef SHOW_LOGTRACE
++		skb_queue_head_init(&dhd->evt_trace_queue);
++
++		if (!(dhd->dhd_state & DHD_ATTACH_LOGTRACE_INIT)) {
++			ret = dhd_init_logstrs_array(dhd->pub.osh, &dhd->event_data);
++			if (ret == BCME_OK) {
++				dhd_init_static_strs_array(dhd->pub.osh, &dhd->event_data,
++					st_str_file_path, map_file_path);
++				dhd_init_static_strs_array(dhd->pub.osh, &dhd->event_data,
++					rom_st_str_file_path, rom_map_file_path);
++				dhd->dhd_state |= DHD_ATTACH_LOGTRACE_INIT;
++			}
++		}
++#endif /* SHOW_LOGTRACE */
++	}
++
++#if defined(PREVENT_REOPEN_DURING_HANG)
++	/* WAR : to prevent calling dhd_open abnormally in quick succession after hang event */
++	if (dhd->pub.hang_was_sent == 1) {
++		DHD_ERROR(("%s: HANG was sent up earlier\n", __FUNCTION__));
++		/* Force to bring down WLAN interface in case dhd_stop() is not called
++		 * from the upper layer when HANG event is triggered.
++		 */
++		if (!dhd_download_fw_on_driverload && dhd->pub.up == 1) {
++			DHD_ERROR(("%s: WLAN interface is not brought down\n", __FUNCTION__));
++			dhd_stop(net);
++		} else {
++			DHD_MUTEX_UNLOCK();
++			return -1;
++		}
++	}
++#endif /* PREVENT_REOPEN_DURING_HANG */
++
++
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK(&dhd->pub);
++	dhd->pub.dongle_trap_occured = 0;
++	dhd->pub.hang_was_sent = 0;
++	dhd->pub.hang_reason = 0;
++	dhd->pub.iovar_timeout_occured = 0;
++#ifdef PCIE_FULL_DONGLE
++	dhd->pub.d3ack_timeout_occured = 0;
++#endif /* PCIE_FULL_DONGLE */
++
++#ifdef DHD_LOSSLESS_ROAMING
++	dhd->pub.dequeue_prec_map = ALLPRIO;
++#endif
++#if 0
++	/*
++	 * Force start if ifconfig_up gets called before START command
++	 *  We keep WEXT's wl_control_wl_start to provide backward compatibility
++	 *  This should be removed in the future
++	 */
++	ret = wl_control_wl_start(net);
++	if (ret != 0) {
++		DHD_ERROR(("%s: failed with code %d\n", __FUNCTION__, ret));
++		ret = -1;
++		goto exit;
++	}
++#endif
++
++	ifidx = dhd_net2idx(dhd, net);
++	DHD_TRACE(("%s: ifidx %d\n", __FUNCTION__, ifidx));
++
++	if (ifidx < 0) {
++		DHD_ERROR(("%s: Error: called with invalid IF\n", __FUNCTION__));
++		ret = -1;
++		goto exit;
++	}
++
++	if (!dhd->iflist[ifidx]) {
++		DHD_ERROR(("%s: Error: called when IF already deleted\n", __FUNCTION__));
++		ret = -1;
++		goto exit;
++	}
++
++	if (ifidx == 0) {
++		atomic_set(&dhd->pend_8021x_cnt, 0);
++		if (!dhd_download_fw_on_driverload) {
++			DHD_ERROR(("\n%s\n", dhd_version));
++#if defined(WL_EXT_IAPSTA) || defined(USE_IW) || defined(WL_ESCAN)
++			wl_ext_event_attach_netdev(net, ifidx, dhd->iflist[ifidx]->bssidx);
++#ifdef WL_ESCAN
++			wl_escan_event_attach(net, &dhd->pub);
++#endif /* WL_ESCAN */
++#ifdef WL_EXT_IAPSTA
++			wl_ext_iapsta_attach_netdev(net, ifidx, dhd->iflist[ifidx]->bssidx);
++#endif /* WL_EXT_IAPSTA */
++#endif /* WL_EXT_IAPSTA || USE_IW || WL_ESCAN */
++#if defined(USE_INITIAL_SHORT_DWELL_TIME)
++			g_first_broadcast_scan = TRUE;
++#endif 
++#if defined(BT_OVER_SDIO)
++			ret = dhd_bus_get(&dhd->pub, WLAN_MODULE);
++			wl_android_set_wifi_on_flag(TRUE);
++#else
++			ret = wl_android_wifi_on(net);
++#endif /* BT_OVER_SDIO */
++			if (ret != 0) {
++				DHD_ERROR(("%s : wl_android_wifi_on failed (%d)\n",
++					__FUNCTION__, ret));
++				ret = -1;
++				goto exit;
++			}
++		}
++#ifdef FIX_CPU_MIN_CLOCK
++		if (dhd_get_fw_mode(dhd) == DHD_FLAG_HOSTAP_MODE) {
++			dhd_init_cpufreq_fix(dhd);
++			dhd_fix_cpu_freq(dhd);
++		}
++#endif /* FIX_CPU_MIN_CLOCK */
++#if defined(OOB_INTR_ONLY)
++		if (dhd->pub.conf->dpc_cpucore >= 0) {
++			dhd_bus_get_ids(dhd->pub.bus, &bus_type, &bus_num, &slot_num);
++			adapter = dhd_wifi_platform_get_adapter(bus_type, bus_num, slot_num);
++			if (adapter) {
++				printf("%s: set irq affinity hit %d\n", __FUNCTION__, dhd->pub.conf->dpc_cpucore);
++				irq_set_affinity_hint(adapter->irq_num, cpumask_of(dhd->pub.conf->dpc_cpucore));
++			}
++		}
++#endif
++
++		if (dhd->pub.busstate != DHD_BUS_DATA) {
++#ifdef BCMDBUS
++			dhd_set_path(&dhd->pub);
++			DHD_MUTEX_UNLOCK();
++			wait_event_interruptible_timeout(dhd->adapter->status_event,
++				wifi_get_adapter_status(dhd->adapter, WIFI_STATUS_FW_READY),
++				msecs_to_jiffies(DHD_FW_READY_TIMEOUT));
++			DHD_MUTEX_LOCK();
++			if ((ret = dbus_up(dhd->pub.bus)) != 0) {
++				DHD_ERROR(("%s: failed to dbus_up with code %d\n", __FUNCTION__, ret));
++				goto exit;
++			} else {
++				dhd->pub.busstate = DHD_BUS_DATA;
++			}
++			if ((ret = dhd_sync_with_dongle(&dhd->pub)) < 0) {
++				DHD_ERROR(("%s: failed with code %d\n", __FUNCTION__, ret));
++				goto exit;
++			}
++#else
++			/* try to bring up bus */
++			DHD_PERIM_UNLOCK(&dhd->pub);
++			ret = dhd_bus_start(&dhd->pub);
++			DHD_PERIM_LOCK(&dhd->pub);
++			if (ret) {
++				DHD_ERROR(("%s: failed with code %d\n", __FUNCTION__, ret));
++				ret = -1;
++				goto exit;
++			}
++#endif /* !BCMDBUS */
++
++		}
++#ifdef WL_EXT_IAPSTA
++		wl_ext_iapsta_attach_name(net, ifidx);
++#endif
++		if (dhd_download_fw_on_driverload) {
++			if (dhd->pub.conf->deepsleep)
++				dhd_deepsleep(dhd, 0);
++		}
++
++#ifdef BCM_FD_AGGR
++		config.config_id = DBUS_CONFIG_ID_AGGR_LIMIT;
++
++
++		memset(iovbuf, 0, sizeof(iovbuf));
++		bcm_mkiovar("rpc_dngl_agglimit", (char *)&agglimit, 4,
++			iovbuf, sizeof(iovbuf));
++
++		if (!dhd_wl_ioctl_cmd(&dhd->pub, WLC_GET_VAR, iovbuf, sizeof(iovbuf), FALSE, 0)) {
++			agglimit = *(uint32 *)iovbuf;
++			config.aggr_param.maxrxsf = agglimit >> BCM_RPC_TP_AGG_SF_SHIFT;
++			config.aggr_param.maxrxsize = agglimit & BCM_RPC_TP_AGG_BYTES_MASK;
++			DHD_ERROR(("rpc_dngl_agglimit %x : sf_limit %d bytes_limit %d\n",
++				agglimit, config.aggr_param.maxrxsf, config.aggr_param.maxrxsize));
++			if (bcm_rpc_tp_set_config(dhd->pub.info->rpc_th, &config)) {
++				DHD_ERROR(("set tx/rx queue size and buffersize failed\n"));
++			}
++		} else {
++			DHD_ERROR(("get rpc_dngl_agglimit failed\n"));
++			rpc_agg &= ~BCM_RPC_TP_DNGL_AGG_DPC;
++		}
++
++		/* Set aggregation for TX */
++		bcm_rpc_tp_agg_set(dhd->pub.info->rpc_th, BCM_RPC_TP_HOST_AGG_MASK,
++			rpc_agg & BCM_RPC_TP_HOST_AGG_MASK);
++
++		/* Set aggregation for RX */
++		memset(iovbuf, 0, sizeof(iovbuf));
++		bcm_mkiovar("rpc_agg", (char *)&rpc_agg, sizeof(rpc_agg), iovbuf, sizeof(iovbuf));
++		if (!dhd_wl_ioctl_cmd(&dhd->pub, WLC_SET_VAR, iovbuf, sizeof(iovbuf), TRUE, 0)) {
++			dhd->pub.info->fdaggr = 0;
++			if (rpc_agg & BCM_RPC_TP_HOST_AGG_MASK)
++				dhd->pub.info->fdaggr |= BCM_FDAGGR_H2D_ENABLED;
++			if (rpc_agg & BCM_RPC_TP_DNGL_AGG_MASK)
++				dhd->pub.info->fdaggr |= BCM_FDAGGR_D2H_ENABLED;
++		} else {
++			DHD_ERROR(("%s(): Setting RX aggregation failed %d\n", __FUNCTION__, ret));
++		}
++#endif /* BCM_FD_AGGR */
++
++#ifdef BT_OVER_SDIO
++		if (dhd->pub.is_bt_recovery_required) {
++			DHD_ERROR(("%s: Send Hang Notification 2 to BT\n", __FUNCTION__));
++			bcmsdh_btsdio_process_dhd_hang_notification(TRUE);
++		}
++		dhd->pub.is_bt_recovery_required = FALSE;
++#endif
++
++		/* dhd_sync_with_dongle has been called in dhd_bus_start or wl_android_wifi_on */
++		memcpy(net->dev_addr, dhd->pub.mac.octet, ETHER_ADDR_LEN);
++
++#ifdef TOE
++		/* Get current TOE mode from dongle */
++		if (dhd_toe_get(dhd, ifidx, &toe_ol) >= 0 && (toe_ol & TOE_TX_CSUM_OL) != 0) {
++			dhd->iflist[ifidx]->net->features |= NETIF_F_IP_CSUM;
++		} else {
++			dhd->iflist[ifidx]->net->features &= ~NETIF_F_IP_CSUM;
++		}
++#endif /* TOE */
++
++#if defined(DHD_LB_RXP)
++		__skb_queue_head_init(&dhd->rx_pend_queue);
++		if (dhd->rx_napi_netdev == NULL) {
++			dhd->rx_napi_netdev = dhd->iflist[ifidx]->net;
++			memset(&dhd->rx_napi_struct, 0, sizeof(struct napi_struct));
++			netif_napi_add(dhd->rx_napi_netdev, &dhd->rx_napi_struct,
++				dhd_napi_poll, dhd_napi_weight);
++			DHD_INFO(("%s napi<%p> enabled ifp->net<%p,%s>\n",
++				__FUNCTION__, &dhd->rx_napi_struct, net, net->name));
++			napi_enable(&dhd->rx_napi_struct);
++			DHD_INFO(("%s load balance init rx_napi_struct\n", __FUNCTION__));
++			skb_queue_head_init(&dhd->rx_napi_queue);
++		} /* rx_napi_netdev == NULL */
++#endif /* DHD_LB_RXP */
++
++#if defined(DHD_LB_TXP)
++		/* Use the variant that uses locks */
++		skb_queue_head_init(&dhd->tx_pend_queue);
++#endif /* DHD_LB_TXP */
++
++#if defined(WL_CFG80211)
++		if (unlikely(wl_cfg80211_up(net))) {
++			DHD_ERROR(("%s: failed to bring up cfg80211\n", __FUNCTION__));
++			ret = -1;
++			goto exit;
++		}
++		if (!dhd_download_fw_on_driverload) {
++#ifdef ARP_OFFLOAD_SUPPORT
++			dhd->pend_ipaddr = 0;
++			if (!dhd_inetaddr_notifier_registered) {
++				dhd_inetaddr_notifier_registered = TRUE;
++				register_inetaddr_notifier(&dhd_inetaddr_notifier);
++			}
++#endif /* ARP_OFFLOAD_SUPPORT */
++#if defined(CONFIG_IPV6) && defined(IPV6_NDO_SUPPORT)
++			if (!dhd_inet6addr_notifier_registered) {
++				dhd_inet6addr_notifier_registered = TRUE;
++				register_inet6addr_notifier(&dhd_inet6addr_notifier);
++			}
++#endif /* CONFIG_IPV6 && IPV6_NDO_SUPPORT */
++		}
++
++		argos_register_notifier_init(net);
++#if defined(NUM_SCB_MAX_PROBE)
++		dhd_set_scb_probe(&dhd->pub);
++#endif /* NUM_SCB_MAX_PROBE */
++#endif /* WL_CFG80211 */
++#if defined(WL_WIRELESS_EXT)
++		if (unlikely(wl_iw_up(net, &dhd->pub))) {
++			DHD_ERROR(("%s: failed to bring up wext\n", __FUNCTION__));
++			ret = -1;
++			goto exit;
++		}
++#endif
++#ifdef WL_ESCAN
++		if (unlikely(wl_escan_up(net, &dhd->pub))) {
++			DHD_ERROR(("%s: failed to bring up escan\n", __FUNCTION__));
++			ret = -1;
++			goto exit;
++		}
++#endif /* WL_ESCAN */
++#if defined(ISAM_PREINIT)
++		if (!dhd_download_fw_on_driverload) {
++			if (dhd->pub.conf) {
++				wl_android_ext_priv_cmd(net, dhd->pub.conf->isam_init, 0, &bytes_written);
++				wl_android_ext_priv_cmd(net, dhd->pub.conf->isam_config, 0, &bytes_written);
++				wl_android_ext_priv_cmd(net, dhd->pub.conf->isam_enable, 0, &bytes_written);
++			}
++		}
++#endif
++	}
++
++	/* Allow transmit calls */
++	netif_start_queue(net);
++	dhd->pub.up = 1;
++
++	OLD_MOD_INC_USE_COUNT;
++
++#ifdef BCMDBGFS
++	dhd_dbgfs_init(&dhd->pub);
++#endif
++
++exit:
++	if (ret) {
++		dhd_stop(net);
++	}
++
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++	DHD_MUTEX_UNLOCK();
++
++	printf("%s: Exit ret=%d\n", __FUNCTION__, ret);
++	return ret;
++}
++
++int dhd_do_driver_init(struct net_device *net)
++{
++	dhd_info_t *dhd = NULL;
++
++	if (!net) {
++		DHD_ERROR(("Primary Interface not initialized \n"));
++		return -EINVAL;
++	}
++
++	DHD_MUTEX_IS_LOCK_RETURN();
++
++	/*  && defined(OEM_ANDROID) && defined(BCMSDIO) */
++	dhd = DHD_DEV_INFO(net);
++
++	/* If driver is already initialized, do nothing
++	 */
++	if (dhd->pub.busstate == DHD_BUS_DATA) {
++		DHD_TRACE(("Driver already Inititalized. Nothing to do"));
++		return 0;
++	}
++
++	if (dhd_open(net) < 0) {
++		DHD_ERROR(("Driver Init Failed \n"));
++		return -1;
++	}
++
++	return 0;
++}
++
++int
++dhd_event_ifadd(dhd_info_t *dhdinfo, wl_event_data_if_t *ifevent, char *name, uint8 *mac)
++{
++
++#ifdef WL_CFG80211
++		if (wl_cfg80211_notify_ifadd(dhd_linux_get_primary_netdev(&dhdinfo->pub),
++			ifevent->ifidx, name, mac, ifevent->bssidx) == BCME_OK)
++		return BCME_OK;
++#endif
++
++	/* handle IF event caused by wl commands, SoftAP, WEXT and
++	 * anything else. This has to be done asynchronously otherwise
++	 * DPC will be blocked (and iovars will timeout as DPC has no chance
++	 * to read the response back)
++	 */
++	if (ifevent->ifidx > 0) {
++		dhd_if_event_t *if_event = MALLOC(dhdinfo->pub.osh, sizeof(dhd_if_event_t));
++		if (if_event == NULL) {
++			DHD_ERROR(("dhd_event_ifadd: Failed MALLOC, malloced %d bytes",
++				MALLOCED(dhdinfo->pub.osh)));
++			return BCME_NOMEM;
++		}
++
++		memcpy(&if_event->event, ifevent, sizeof(if_event->event));
++		memcpy(if_event->mac, mac, ETHER_ADDR_LEN);
++		strncpy(if_event->name, name, IFNAMSIZ);
++		if_event->name[IFNAMSIZ - 1] = '\0';
++		dhd_deferred_schedule_work(dhdinfo->dhd_deferred_wq, (void *)if_event,
++			DHD_WQ_WORK_IF_ADD, dhd_ifadd_event_handler, DHD_WQ_WORK_PRIORITY_LOW);
++	}
++
++	return BCME_OK;
++}
++
++int
++dhd_event_ifdel(dhd_info_t *dhdinfo, wl_event_data_if_t *ifevent, char *name, uint8 *mac)
++{
++	dhd_if_event_t *if_event;
++
++#ifdef WL_CFG80211
++		if (wl_cfg80211_notify_ifdel(dhd_linux_get_primary_netdev(&dhdinfo->pub),
++			ifevent->ifidx, name, mac, ifevent->bssidx) == BCME_OK)
++		return BCME_OK;
++#endif /* WL_CFG80211 */
++
++	/* handle IF event caused by wl commands, SoftAP, WEXT and
++	 * anything else
++	 */
++	if_event = MALLOC(dhdinfo->pub.osh, sizeof(dhd_if_event_t));
++	if (if_event == NULL) {
++		DHD_ERROR(("dhd_event_ifdel: malloc failed for if_event, malloced %d bytes",
++			MALLOCED(dhdinfo->pub.osh)));
++		return BCME_NOMEM;
++	}
++	memcpy(&if_event->event, ifevent, sizeof(if_event->event));
++	memcpy(if_event->mac, mac, ETHER_ADDR_LEN);
++	strncpy(if_event->name, name, IFNAMSIZ);
++	if_event->name[IFNAMSIZ - 1] = '\0';
++	dhd_deferred_schedule_work(dhdinfo->dhd_deferred_wq, (void *)if_event, DHD_WQ_WORK_IF_DEL,
++		dhd_ifdel_event_handler, DHD_WQ_WORK_PRIORITY_LOW);
++
++	return BCME_OK;
++}
++
++int
++dhd_event_ifchange(dhd_info_t *dhdinfo, wl_event_data_if_t *ifevent, char *name, uint8 *mac)
++{
++#ifdef DHD_UPDATE_INTF_MAC
++	dhd_if_event_t *if_event;
++#endif /* DHD_UPDATE_INTF_MAC */
++
++#ifdef WL_CFG80211
++	wl_cfg80211_notify_ifchange(dhd_linux_get_primary_netdev(&dhdinfo->pub),
++		ifevent->ifidx, name, mac, ifevent->bssidx);
++#endif /* WL_CFG80211 */
++
++#ifdef DHD_UPDATE_INTF_MAC
++	/* handle IF event caused by wl commands, SoftAP, WEXT, MBSS and
++	 * anything else
++	 */
++	if_event = MALLOC(dhdinfo->pub.osh, sizeof(dhd_if_event_t));
++	if (if_event == NULL) {
++		DHD_ERROR(("dhd_event_ifdel: malloc failed for if_event, malloced %d bytes",
++			MALLOCED(dhdinfo->pub.osh)));
++		return BCME_NOMEM;
++	}
++	memcpy(&if_event->event, ifevent, sizeof(if_event->event));
++	// construct a change event
++	if_event->event.ifidx = dhd_ifname2idx(dhdinfo, name);
++	if_event->event.opcode = WLC_E_IF_CHANGE;
++	memcpy(if_event->mac, mac, ETHER_ADDR_LEN);
++	strncpy(if_event->name, name, IFNAMSIZ);
++	if_event->name[IFNAMSIZ - 1] = '\0';
++	dhd_deferred_schedule_work(dhdinfo->dhd_deferred_wq, (void *)if_event, DHD_WQ_WORK_IF_UPDATE,
++		dhd_ifupdate_event_handler, DHD_WQ_WORK_PRIORITY_LOW);
++#endif /* DHD_UPDATE_INTF_MAC */
++
++	return BCME_OK;
++}
++
++/* unregister and free the existing net_device interface (if any) in iflist and
++ * allocate a new one. the slot is reused. this function does NOT register the
++ * new interface to linux kernel. dhd_register_if does the job
++ */
++struct net_device*
++dhd_allocate_if(dhd_pub_t *dhdpub, int ifidx, const char *name,
++	uint8 *mac, uint8 bssidx, bool need_rtnl_lock, const char *dngl_name)
++{
++	dhd_info_t *dhdinfo = (dhd_info_t *)dhdpub->info;
++	dhd_if_t *ifp;
++
++	ASSERT(dhdinfo && (ifidx < DHD_MAX_IFS));
++	ifp = dhdinfo->iflist[ifidx];
++
++	if (ifp != NULL) {
++		if (ifp->net != NULL) {
++			DHD_ERROR(("%s: free existing IF %s ifidx:%d \n",
++				__FUNCTION__, ifp->net->name, ifidx));
++
++			if (ifidx == 0) {
++				/* For primary ifidx (0), there shouldn't be
++				 * any netdev present already.
++				 */
++				DHD_ERROR(("Primary ifidx populated already\n"));
++				ASSERT(0);
++				return NULL;
++			}
++
++			dhd_dev_priv_clear(ifp->net); /* clear net_device private */
++
++			/* in unregister_netdev case, the interface gets freed by net->destructor
++			 * (which is set to free_netdev)
++			 */
++			if (ifp->net->reg_state == NETREG_UNINITIALIZED) {
++				free_netdev(ifp->net);
++			} else {
++				netif_stop_queue(ifp->net);
++				if (need_rtnl_lock)
++					unregister_netdev(ifp->net);
++				else
++					unregister_netdevice(ifp->net);
++			}
++			ifp->net = NULL;
++		}
++	} else {
++		ifp = MALLOC(dhdinfo->pub.osh, sizeof(dhd_if_t));
++		if (ifp == NULL) {
++			DHD_ERROR(("%s: OOM - dhd_if_t(%zu)\n", __FUNCTION__, sizeof(dhd_if_t)));
++			return NULL;
++		}
++	}
++
++	memset(ifp, 0, sizeof(dhd_if_t));
++	ifp->info = dhdinfo;
++	ifp->idx = ifidx;
++	ifp->bssidx = bssidx;
++#ifdef DHD_MCAST_REGEN
++	ifp->mcast_regen_bss_enable = FALSE;
++#endif
++	/* set to TRUE rx_pkt_chainable at alloc time */
++	ifp->rx_pkt_chainable = TRUE;
++
++	if (mac != NULL)
++		memcpy(&ifp->mac_addr, mac, ETHER_ADDR_LEN);
++
++	/* Allocate etherdev, including space for private structure */
++	ifp->net = alloc_etherdev(DHD_DEV_PRIV_SIZE);
++	if (ifp->net == NULL) {
++		DHD_ERROR(("%s: OOM - alloc_etherdev(%zu)\n", __FUNCTION__, sizeof(dhdinfo)));
++		goto fail;
++	}
++
++	/* Setup the dhd interface's netdevice private structure. */
++	dhd_dev_priv_save(ifp->net, dhdinfo, ifp, ifidx);
++
++	if (name && name[0]) {
++		strncpy(ifp->net->name, name, IFNAMSIZ);
++		ifp->net->name[IFNAMSIZ - 1] = '\0';
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 9))
++#define IFP_NET_DESTRUCTOR	ifp->net->priv_destructor
++#else
++#define IFP_NET_DESTRUCTOR	ifp->net->destructor
++#endif // endif
++
++#ifdef WL_CFG80211
++	if (ifidx == 0) {
++		IFP_NET_DESTRUCTOR = free_netdev;
++	} else {
++		IFP_NET_DESTRUCTOR = dhd_netdev_free;
++	}
++#else
++	IFP_NET_DESTRUCTOR = free_netdev;
++#endif /* WL_CFG80211 */
++	strncpy(ifp->name, ifp->net->name, IFNAMSIZ);
++	ifp->name[IFNAMSIZ - 1] = '\0';
++	dhdinfo->iflist[ifidx] = ifp;
++
++/* initialize the dongle provided if name */
++	if (dngl_name)
++		strncpy(ifp->dngl_name, dngl_name, IFNAMSIZ);
++	else if (name)
++		strncpy(ifp->dngl_name, name, IFNAMSIZ);
++
++#ifdef PCIE_FULL_DONGLE
++	/* Initialize STA info list */
++	INIT_LIST_HEAD(&ifp->sta_list);
++	DHD_IF_STA_LIST_LOCK_INIT(ifp);
++#endif /* PCIE_FULL_DONGLE */
++
++#ifdef DHD_L2_FILTER
++	ifp->phnd_arp_table = init_l2_filter_arp_table(dhdpub->osh);
++	ifp->parp_allnode = TRUE;
++#endif /* DHD_L2_FILTER */
++
++
++	DHD_CUMM_CTR_INIT(&ifp->cumm_ctr);
++
++	return ifp->net;
++
++fail:
++	if (ifp != NULL) {
++		if (ifp->net != NULL) {
++#if defined(DHD_LB_RXP) && defined(PCIE_FULL_DONGLE)
++			if (ifp->net == dhdinfo->rx_napi_netdev) {
++				napi_disable(&dhdinfo->rx_napi_struct);
++				netif_napi_del(&dhdinfo->rx_napi_struct);
++				skb_queue_purge(&dhdinfo->rx_napi_queue);
++				dhdinfo->rx_napi_netdev = NULL;
++			}
++#endif /* DHD_LB_RXP && PCIE_FULL_DONGLE */
++			dhd_dev_priv_clear(ifp->net);
++			free_netdev(ifp->net);
++			ifp->net = NULL;
++		}
++		MFREE(dhdinfo->pub.osh, ifp, sizeof(*ifp));
++		ifp = NULL;
++	}
++	dhdinfo->iflist[ifidx] = NULL;
++	return NULL;
++}
++
++/* unregister and free the the net_device interface associated with the indexed
++ * slot, also free the slot memory and set the slot pointer to NULL
++ */
++int
++dhd_remove_if(dhd_pub_t *dhdpub, int ifidx, bool need_rtnl_lock)
++{
++	dhd_info_t *dhdinfo = (dhd_info_t *)dhdpub->info;
++	dhd_if_t *ifp;
++#ifdef PCIE_FULL_DONGLE
++	if_flow_lkup_t *if_flow_lkup = (if_flow_lkup_t *)dhdpub->if_flow_lkup;
++#endif /* PCIE_FULL_DONGLE */
++
++	ifp = dhdinfo->iflist[ifidx];
++
++	if (ifp != NULL) {
++		if (ifp->net != NULL) {
++			DHD_ERROR(("deleting interface '%s' idx %d\n", ifp->net->name, ifp->idx));
++
++			dhdinfo->iflist[ifidx] = NULL;
++			/* in unregister_netdev case, the interface gets freed by net->destructor
++			 * (which is set to free_netdev)
++			 */
++			if (ifp->net->reg_state == NETREG_UNINITIALIZED) {
++				free_netdev(ifp->net);
++			} else {
++				netif_tx_disable(ifp->net);
++
++
++
++#if defined(SET_RPS_CPUS)
++				custom_rps_map_clear(ifp->net->_rx);
++#endif /* SET_RPS_CPUS */
++				if (need_rtnl_lock)
++					unregister_netdev(ifp->net);
++				else
++					unregister_netdevice(ifp->net);
++#if defined(WL_EXT_IAPSTA) || defined(USE_IW) || defined(WL_ESCAN)
++#ifdef WL_EXT_IAPSTA
++				wl_ext_iapsta_dettach_netdev(ifp->net, ifidx);
++#endif /* WL_EXT_IAPSTA */
++#ifdef WL_ESCAN
++				wl_escan_event_dettach(ifp->net, dhdpub);
++#endif /* WL_ESCAN */
++				wl_ext_event_dettach_netdev(ifp->net, ifidx);
++#endif /* WL_EXT_IAPSTA || USE_IW || WL_ESCAN */
++			}
++			ifp->net = NULL;
++		}
++#ifdef DHD_WMF
++		dhd_wmf_cleanup(dhdpub, ifidx);
++#endif /* DHD_WMF */
++#ifdef DHD_L2_FILTER
++		bcm_l2_filter_arp_table_update(dhdpub->osh, ifp->phnd_arp_table, TRUE,
++			NULL, FALSE, dhdpub->tickcnt);
++		deinit_l2_filter_arp_table(dhdpub->osh, ifp->phnd_arp_table);
++		ifp->phnd_arp_table = NULL;
++#endif /* DHD_L2_FILTER */
++
++
++		dhd_if_del_sta_list(ifp);
++#ifdef PCIE_FULL_DONGLE
++		/* Delete flowrings of WDS interface */
++		if (if_flow_lkup[ifidx].role == WLC_E_IF_ROLE_WDS) {
++			dhd_flow_rings_delete(dhdpub, ifidx);
++		}
++#endif /* PCIE_FULL_DONGLE */
++		DHD_CUMM_CTR_INIT(&ifp->cumm_ctr);
++
++		MFREE(dhdinfo->pub.osh, ifp, sizeof(*ifp));
++		ifp = NULL;
++	}
++
++	return BCME_OK;
++}
++
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
++static struct net_device_ops dhd_ops_pri = {
++	.ndo_open = dhd_open,
++	.ndo_stop = dhd_stop,
++	.ndo_get_stats = dhd_get_stats,
++	.ndo_do_ioctl = dhd_ioctl_entry,
++	.ndo_start_xmit = dhd_start_xmit,
++	.ndo_set_mac_address = dhd_set_mac_address,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	.ndo_set_rx_mode = dhd_set_multicast_list,
++#else
++	.ndo_set_multicast_list = dhd_set_multicast_list,
++#endif
++};
++
++static struct net_device_ops dhd_ops_virt = {
++	.ndo_get_stats = dhd_get_stats,
++	.ndo_do_ioctl = dhd_ioctl_entry,
++	.ndo_start_xmit = dhd_start_xmit,
++	.ndo_set_mac_address = dhd_set_mac_address,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	.ndo_set_rx_mode = dhd_set_multicast_list,
++#else
++	.ndo_set_multicast_list = dhd_set_multicast_list,
++#endif
++};
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31)) */
++
++#ifdef DEBUGGER
++extern void debugger_init(void *bus_handle);
++#endif
++
++
++#ifdef SHOW_LOGTRACE
++int
++dhd_os_read_file(void *file, char *buf, uint32 size)
++{
++	struct file *filep = (struct file *)file;
++
++	if (!file || !buf)
++		return -1;
++
++	return vfs_read(filep, buf, size, &filep->f_pos);
++}
++
++int
++dhd_os_seek_file(void *file, int64 offset)
++{
++	struct file *filep = (struct file *)file;
++	if (!file)
++		return -1;
++
++	/* offset can be -ve */
++	filep->f_pos = filep->f_pos + offset;
++
++	return 0;
++}
++
++static int
++dhd_init_logstrs_array(osl_t *osh, dhd_event_log_t *temp)
++{
++	struct file *filep = NULL;
++	struct kstat stat;
++	mm_segment_t fs;
++	char *raw_fmts =  NULL;
++	int logstrs_size = 0;
++	int error = 0;
++
++	fs = get_fs();
++	set_fs(KERNEL_DS);
++
++	filep = filp_open(logstrs_path, O_RDONLY, 0);
++
++	if (IS_ERR(filep)) {
++		DHD_ERROR(("%s: Failed to open the file %s \n", __FUNCTION__, logstrs_path));
++		goto fail;
++	}
++	error = vfs_stat(logstrs_path, &stat);
++	if (error) {
++		DHD_ERROR(("%s: Failed to stat file %s \n", __FUNCTION__, logstrs_path));
++		goto fail;
++	}
++	logstrs_size = (int) stat.size;
++
++	if (logstrs_size == 0) {
++		DHD_ERROR(("%s: return as logstrs_size is 0\n", __FUNCTION__));
++		goto fail1;
++	}
++
++	raw_fmts = MALLOC(osh, logstrs_size);
++	if (raw_fmts == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory \n", __FUNCTION__));
++		goto fail;
++	}
++	if (vfs_read(filep, raw_fmts, logstrs_size, &filep->f_pos) !=	logstrs_size) {
++		DHD_ERROR(("%s: Failed to read file %s\n", __FUNCTION__, logstrs_path));
++		goto fail;
++	}
++
++	if (dhd_parse_logstrs_file(osh, raw_fmts, logstrs_size, temp)
++				== BCME_OK) {
++		filp_close(filep, NULL);
++		set_fs(fs);
++		return BCME_OK;
++	}
++
++fail:
++	if (raw_fmts) {
++		MFREE(osh, raw_fmts, logstrs_size);
++		raw_fmts = NULL;
++	}
++
++fail1:
++	if (!IS_ERR(filep))
++		filp_close(filep, NULL);
++
++	set_fs(fs);
++	temp->fmts = NULL;
++	return BCME_ERROR;
++}
++
++static int
++dhd_read_map(osl_t *osh, char *fname, uint32 *ramstart, uint32 *rodata_start,
++		uint32 *rodata_end)
++{
++	struct file *filep = NULL;
++	mm_segment_t fs;
++	int err = BCME_ERROR;
++
++	if (fname == NULL) {
++		DHD_ERROR(("%s: ERROR fname is NULL \n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	fs = get_fs();
++	set_fs(KERNEL_DS);
++
++	filep = filp_open(fname, O_RDONLY, 0);
++	if (IS_ERR(filep)) {
++		DHD_ERROR(("%s: Failed to open %s \n",  __FUNCTION__, fname));
++		goto fail;
++	}
++
++	if ((err = dhd_parse_map_file(osh, filep, ramstart,
++			rodata_start, rodata_end)) < 0)
++		goto fail;
++
++fail:
++	if (!IS_ERR(filep))
++		filp_close(filep, NULL);
++
++	set_fs(fs);
++
++	return err;
++}
++
++static int
++dhd_init_static_strs_array(osl_t *osh, dhd_event_log_t *temp, char *str_file, char *map_file)
++{
++	struct file *filep = NULL;
++	mm_segment_t fs;
++	char *raw_fmts =  NULL;
++	uint32 logstrs_size = 0;
++
++	int error = 0;
++	uint32 ramstart = 0;
++	uint32 rodata_start = 0;
++	uint32 rodata_end = 0;
++	uint32 logfilebase = 0;
++
++	error = dhd_read_map(osh, map_file, &ramstart, &rodata_start, &rodata_end);
++	if (error != BCME_OK) {
++		DHD_ERROR(("readmap Error!! \n"));
++		/* don't do event log parsing in actual case */
++		if (strstr(str_file, ram_file_str) != NULL) {
++			temp->raw_sstr = NULL;
++		} else if (strstr(str_file, rom_file_str) != NULL) {
++			temp->rom_raw_sstr = NULL;
++		}
++		return error;
++	}
++	DHD_ERROR(("ramstart: 0x%x, rodata_start: 0x%x, rodata_end:0x%x\n",
++		ramstart, rodata_start, rodata_end));
++
++	fs = get_fs();
++	set_fs(KERNEL_DS);
++
++	filep = filp_open(str_file, O_RDONLY, 0);
++	if (IS_ERR(filep)) {
++		DHD_ERROR(("%s: Failed to open the file %s \n",  __FUNCTION__, str_file));
++		goto fail;
++	}
++
++	/* Full file size is huge. Just read required part */
++	logstrs_size = rodata_end - rodata_start;
++
++	if (logstrs_size == 0) {
++		DHD_ERROR(("%s: return as logstrs_size is 0\n", __FUNCTION__));
++		goto fail1;
++	}
++
++	raw_fmts = MALLOC(osh, logstrs_size);
++	if (raw_fmts == NULL) {
++		DHD_ERROR(("%s: Failed to allocate raw_fmts memory \n", __FUNCTION__));
++		goto fail;
++	}
++
++	logfilebase = rodata_start - ramstart;
++
++	error = generic_file_llseek(filep, logfilebase, SEEK_SET);
++	if (error < 0) {
++		DHD_ERROR(("%s: %s llseek failed %d \n", __FUNCTION__, str_file, error));
++		goto fail;
++	}
++
++	error = vfs_read(filep, raw_fmts, logstrs_size, (&filep->f_pos));
++	if (error != logstrs_size) {
++		DHD_ERROR(("%s: %s read failed %d \n", __FUNCTION__, str_file, error));
++		goto fail;
++	}
++
++	if (strstr(str_file, ram_file_str) != NULL) {
++		temp->raw_sstr = raw_fmts;
++		temp->raw_sstr_size = logstrs_size;
++		temp->ramstart = ramstart;
++		temp->rodata_start = rodata_start;
++		temp->rodata_end = rodata_end;
++	} else if (strstr(str_file, rom_file_str) != NULL) {
++		temp->rom_raw_sstr = raw_fmts;
++		temp->rom_raw_sstr_size = logstrs_size;
++		temp->rom_ramstart = ramstart;
++		temp->rom_rodata_start = rodata_start;
++		temp->rom_rodata_end = rodata_end;
++	}
++
++	filp_close(filep, NULL);
++	set_fs(fs);
++
++	return BCME_OK;
++
++fail:
++	if (raw_fmts) {
++		MFREE(osh, raw_fmts, logstrs_size);
++		raw_fmts = NULL;
++	}
++
++fail1:
++	if (!IS_ERR(filep))
++		filp_close(filep, NULL);
++
++	set_fs(fs);
++
++	if (strstr(str_file, ram_file_str) != NULL) {
++		temp->raw_sstr = NULL;
++	} else if (strstr(str_file, rom_file_str) != NULL) {
++		temp->rom_raw_sstr = NULL;
++	}
++
++	return error;
++}
++
++#endif /* SHOW_LOGTRACE */
++
++#ifdef BCMDBUS
++uint
++dhd_get_rxsz(dhd_pub_t *pub)
++{
++	struct net_device *net = NULL;
++	dhd_info_t *dhd = NULL;
++	uint rxsz;
++
++	/* Assign rxsz for dbus_attach */
++	dhd = pub->info;
++	net = dhd->iflist[0]->net;
++	net->hard_header_len = ETH_HLEN + pub->hdrlen;
++	rxsz = DBUS_RX_BUFFER_SIZE_DHD(net);
++
++	return rxsz;
++}
++
++void
++dhd_set_path(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = NULL;
++
++	dhd = pub->info;
++
++	/* try to download image and nvram to the dongle */
++	if	(dhd_update_fw_nv_path(dhd) && dhd->pub.bus) {
++		DHD_INFO(("%s: fw %s, nv %s, conf %s\n",
++			__FUNCTION__, dhd->fw_path, dhd->nv_path, dhd->conf_path));
++		dhd_bus_update_fw_nv_path(dhd->pub.bus,
++				dhd->fw_path, dhd->nv_path, dhd->clm_path, dhd->conf_path);
++	}
++}
++#endif
++
++dhd_pub_t *
++dhd_attach(osl_t *osh, struct dhd_bus *bus, uint bus_hdrlen
++#ifdef BCMDBUS
++	, void *data
++#endif
++)
++{
++	dhd_info_t *dhd = NULL;
++	struct net_device *net = NULL;
++	char if_name[IFNAMSIZ] = {'\0'};
++#ifdef SHOW_LOGTRACE
++	int ret;
++#endif /* SHOW_LOGTRACE */
++#if defined(BCMSDIO) || defined(BCMPCIE)
++	uint32 bus_type = -1;
++	uint32 bus_num = -1;
++	uint32 slot_num = -1;
++	wifi_adapter_info_t *adapter = NULL;
++#elif defined(BCMDBUS)
++	wifi_adapter_info_t *adapter = data;
++#endif
++#ifdef GET_CUSTOM_MAC_ENABLE
++	char hw_ether[62];
++#endif /* GET_CUSTOM_MAC_ENABLE */
++
++	dhd_attach_states_t dhd_state = DHD_ATTACH_STATE_INIT;
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++#ifdef STBLINUX
++	DHD_ERROR(("%s\n", driver_target));
++#endif /* STBLINUX */
++	/* will implement get_ids for DBUS later */
++#if defined(BCMSDIO)
++	dhd_bus_get_ids(bus, &bus_type, &bus_num, &slot_num);
++#endif 
++#if defined(BCMSDIO) || defined(BCMPCIE)
++	adapter = dhd_wifi_platform_get_adapter(bus_type, bus_num, slot_num);
++#endif
++
++	/* Allocate primary dhd_info */
++	dhd = wifi_platform_prealloc(adapter, DHD_PREALLOC_DHD_INFO, sizeof(dhd_info_t));
++	if (dhd == NULL) {
++		dhd = MALLOC(osh, sizeof(dhd_info_t));
++		if (dhd == NULL) {
++			DHD_ERROR(("%s: OOM - alloc dhd_info\n", __FUNCTION__));
++			goto dhd_null_flag;
++		}
++	}
++	memset(dhd, 0, sizeof(dhd_info_t));
++	dhd_state |= DHD_ATTACH_STATE_DHD_ALLOC;
++
++	dhd->unit = dhd_found + instance_base; /* do not increment dhd_found, yet */
++
++	dhd->pub.osh = osh;
++#ifdef DUMP_IOCTL_IOV_LIST
++	dll_init(&(dhd->pub.dump_iovlist_head));
++#endif /* DUMP_IOCTL_IOV_LIST */
++	dhd->adapter = adapter;
++	dhd->pub.adapter = (void *)adapter;
++#ifdef DHD_DEBUG
++	dll_init(&(dhd->pub.mw_list_head));
++#endif /* DHD_DEBUG */
++#ifdef BT_OVER_SDIO
++	dhd->pub.is_bt_recovery_required = FALSE;
++	mutex_init(&dhd->bus_user_lock);
++#endif /* BT_OVER_SDIO */
++
++#ifdef GET_CUSTOM_MAC_ENABLE
++	wifi_platform_get_mac_addr(dhd->adapter, hw_ether);
++	bcopy(hw_ether, dhd->pub.mac.octet, sizeof(struct ether_addr));
++#endif /* GET_CUSTOM_MAC_ENABLE */
++#ifdef CUSTOM_FORCE_NODFS_FLAG
++	dhd->pub.dhd_cflags |= WLAN_PLAT_NODFS_FLAG;
++	dhd->pub.force_country_change = TRUE;
++#endif /* CUSTOM_FORCE_NODFS_FLAG */
++#ifdef CUSTOM_COUNTRY_CODE
++	get_customized_country_code(dhd->adapter,
++		dhd->pub.dhd_cspec.country_abbrev, &dhd->pub.dhd_cspec,
++		dhd->pub.dhd_cflags);
++#endif /* CUSTOM_COUNTRY_CODE */
++#ifndef BCMDBUS
++	dhd->thr_dpc_ctl.thr_pid = DHD_PID_KT_TL_INVALID;
++	dhd->thr_wdt_ctl.thr_pid = DHD_PID_KT_INVALID;
++#ifdef DHD_WET
++	dhd->pub.wet_info = dhd_get_wet_info(&dhd->pub);
++#endif /* DHD_WET */
++	/* Initialize thread based operation and lock */
++	sema_init(&dhd->sdsem, 1);
++#endif /* !BCMDBUS */
++
++	/* Link to info module */
++	dhd->pub.info = dhd;
++
++
++	/* Link to bus module */
++	dhd->pub.bus = bus;
++	dhd->pub.hdrlen = bus_hdrlen;
++
++	/* dhd_conf must be attached after linking dhd to dhd->pub.info,
++	 * because dhd_detech will check .info is NULL or not.
++	*/
++	if (dhd_conf_attach(&dhd->pub) != 0) {
++		DHD_ERROR(("dhd_conf_attach failed\n"));
++		goto fail;
++	}
++#ifndef BCMDBUS
++	dhd_conf_reset(&dhd->pub);
++	dhd_conf_set_chiprev(&dhd->pub, dhd_bus_chip(bus), dhd_bus_chiprev(bus));
++	dhd_conf_preinit(&dhd->pub);
++#endif /* !BCMDBUS */
++
++	/* Some DHD modules (e.g. cfg80211) configures operation mode based on firmware name.
++	 * This is indeed a hack but we have to make it work properly before we have a better
++	 * solution
++	 */
++	dhd_update_fw_nv_path(dhd);
++
++	/* Set network interface name if it was provided as module parameter */
++	if (iface_name[0]) {
++		int len;
++		char ch;
++		strncpy(if_name, iface_name, IFNAMSIZ);
++		if_name[IFNAMSIZ - 1] = 0;
++		len = strlen(if_name);
++		ch = if_name[len - 1];
++		if ((ch > '9' || ch < '0') && (len < IFNAMSIZ - 2))
++			strncat(if_name, "%d", 2);
++	}
++
++	/* Passing NULL to dngl_name to ensure host gets if_name in dngl_name member */
++	net = dhd_allocate_if(&dhd->pub, 0, if_name, NULL, 0, TRUE, NULL);
++	if (net == NULL) {
++		goto fail;
++	}
++
++
++	dhd_state |= DHD_ATTACH_STATE_ADD_IF;
++#ifdef DHD_L2_FILTER
++	/* initialize the l2_filter_cnt */
++	dhd->pub.l2_filter_cnt = 0;
++#endif
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31))
++	net->open = NULL;
++#else
++	net->netdev_ops = NULL;
++#endif
++
++	mutex_init(&dhd->dhd_iovar_mutex);
++	sema_init(&dhd->proto_sem, 1);
++#ifdef DHD_ULP
++	if (!(dhd_ulp_init(osh, &dhd->pub)))
++		goto fail;
++#endif /* DHD_ULP */
++
++#if defined(DHD_HANG_SEND_UP_TEST)
++	dhd->pub.req_hang_type = 0;
++#endif /* DHD_HANG_SEND_UP_TEST */
++
++#ifdef PROP_TXSTATUS
++	spin_lock_init(&dhd->wlfc_spinlock);
++
++	dhd->pub.skip_fc = dhd_wlfc_skip_fc;
++	dhd->pub.plat_init = dhd_wlfc_plat_init;
++	dhd->pub.plat_deinit = dhd_wlfc_plat_deinit;
++
++#ifdef DHD_WLFC_THREAD
++	init_waitqueue_head(&dhd->pub.wlfc_wqhead);
++	dhd->pub.wlfc_thread = kthread_create(dhd_wlfc_transfer_packets, &dhd->pub, "wlfc-thread");
++	if (IS_ERR(dhd->pub.wlfc_thread)) {
++		DHD_ERROR(("create wlfc thread failed\n"));
++		goto fail;
++	} else {
++		wake_up_process(dhd->pub.wlfc_thread);
++	}
++#endif /* DHD_WLFC_THREAD */
++#endif /* PROP_TXSTATUS */
++
++	/* Initialize other structure content */
++	init_waitqueue_head(&dhd->ioctl_resp_wait);
++	init_waitqueue_head(&dhd->d3ack_wait);
++#ifdef PCIE_INB_DW
++	init_waitqueue_head(&dhd->ds_exit_wait);
++#endif /* PCIE_INB_DW */
++	init_waitqueue_head(&dhd->ctrl_wait);
++	init_waitqueue_head(&dhd->dhd_bus_busy_state_wait);
++	dhd->pub.dhd_bus_busy_state = 0;
++
++	/* Initialize the spinlocks */
++	spin_lock_init(&dhd->sdlock);
++	spin_lock_init(&dhd->txqlock);
++	spin_lock_init(&dhd->rxqlock);
++	spin_lock_init(&dhd->dhd_lock);
++	spin_lock_init(&dhd->rxf_lock);
++#ifdef WLTDLS
++	spin_lock_init(&dhd->pub.tdls_lock);
++#endif /* WLTDLS */
++#if defined(RXFRAME_THREAD)
++	dhd->rxthread_enabled = TRUE;
++#endif /* defined(RXFRAME_THREAD) */
++
++#ifdef DHDTCPACK_SUPPRESS
++	spin_lock_init(&dhd->tcpack_lock);
++#endif /* DHDTCPACK_SUPPRESS */
++
++	/* Initialize Wakelock stuff */
++	spin_lock_init(&dhd->wakelock_spinlock);
++	spin_lock_init(&dhd->wakelock_evt_spinlock);
++	DHD_OS_WAKE_LOCK_INIT(dhd);
++	dhd->wakelock_counter = 0;
++#ifdef CONFIG_HAS_WAKELOCK
++	// terence 20161023: can not destroy wl_wifi when wlan down, it will happen null pointer in dhd_ioctl_entry
++	wake_lock_init(&dhd->wl_wifi, WAKE_LOCK_SUSPEND, "wlan_wake");
++	wake_lock_init(&dhd->wl_wdwake, WAKE_LOCK_SUSPEND, "wlan_wd_wake");
++#endif /* CONFIG_HAS_WAKELOCK */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	mutex_init(&dhd->dhd_net_if_mutex);
++	mutex_init(&dhd->dhd_suspend_mutex);
++#if defined(PKT_FILTER_SUPPORT) && defined(APF)
++	mutex_init(&dhd->dhd_apf_mutex);
++#endif /* PKT_FILTER_SUPPORT && APF */
++#endif 
++	dhd_state |= DHD_ATTACH_STATE_WAKELOCKS_INIT;
++
++	/* Attach and link in the protocol */
++	if (dhd_prot_attach(&dhd->pub) != 0) {
++		DHD_ERROR(("dhd_prot_attach failed\n"));
++		goto fail;
++	}
++	dhd_state |= DHD_ATTACH_STATE_PROT_ATTACH;
++
++#ifdef DHD_TIMESYNC
++	/* attach the timesync module */
++	if (dhd_timesync_attach(&dhd->pub) != 0) {
++		DHD_ERROR(("dhd_timesync_attach failed\n"));
++		goto fail;
++	}
++	dhd_state |= DHD_ATTACH_TIMESYNC_ATTACH_DONE;
++#endif /* DHD_TIMESYNC */
++
++#ifdef WL_CFG80211
++	spin_lock_init(&dhd->pub.up_lock);
++	/* Attach and link in the cfg80211 */
++	if (unlikely(wl_cfg80211_attach(net, &dhd->pub))) {
++		DHD_ERROR(("wl_cfg80211_attach failed\n"));
++		goto fail;
++	}
++
++	dhd_monitor_init(&dhd->pub);
++	dhd_state |= DHD_ATTACH_STATE_CFG80211;
++#endif
++#ifdef DHD_LOG_DUMP
++	dhd_log_dump_init(&dhd->pub);
++#endif /* DHD_LOG_DUMP */
++#if defined(WL_EXT_IAPSTA) || defined(USE_IW) || defined(WL_ESCAN)
++	if (wl_ext_event_attach(net, &dhd->pub) != 0) {
++		DHD_ERROR(("wl_ext_event_attach failed\n"));
++		goto fail;
++	}
++#ifdef WL_ESCAN
++	/* Attach and link in the escan */
++	if (wl_escan_attach(net, &dhd->pub) != 0) {
++		DHD_ERROR(("wl_escan_attach failed\n"));
++		goto fail;
++	}
++#endif /* WL_ESCAN */
++#ifdef WL_EXT_IAPSTA
++	if (wl_ext_iapsta_attach(&dhd->pub) != 0) {
++		DHD_ERROR(("wl_ext_iapsta_attach failed\n"));
++		goto fail;
++	}
++#endif /* WL_EXT_IAPSTA */
++#endif /* WL_EXT_IAPSTA || USE_IW || WL_ESCAN */
++#if defined(WL_WIRELESS_EXT)
++	/* Attach and link in the iw */
++	if (wl_iw_attach(net, &dhd->pub) != 0) {
++		DHD_ERROR(("wl_iw_attach failed\n"));
++		goto fail;
++	}
++	dhd_state |= DHD_ATTACH_STATE_WL_ATTACH;
++#endif /* defined(WL_WIRELESS_EXT) */
++
++#ifdef SHOW_LOGTRACE
++	ret = dhd_init_logstrs_array(osh, &dhd->event_data);
++	if (ret == BCME_OK) {
++		dhd_init_static_strs_array(osh, &dhd->event_data, st_str_file_path, map_file_path);
++		dhd_init_static_strs_array(osh, &dhd->event_data, rom_st_str_file_path,
++			rom_map_file_path);
++		dhd_state |= DHD_ATTACH_LOGTRACE_INIT;
++	}
++#endif /* SHOW_LOGTRACE */
++
++#ifdef DEBUGABILITY
++	/* attach debug if support */
++	if (dhd_os_dbg_attach(&dhd->pub)) {
++		DHD_ERROR(("%s debug module attach failed\n", __FUNCTION__));
++		goto fail;
++	}
++
++#ifdef DBG_PKT_MON
++	dhd->pub.dbg->pkt_mon_lock = dhd_os_spin_lock_init(dhd->pub.osh);
++#ifdef DBG_PKT_MON_INIT_DEFAULT
++	dhd_os_dbg_attach_pkt_monitor(&dhd->pub);
++#endif /* DBG_PKT_MON_INIT_DEFAULT */
++#endif /* DBG_PKT_MON */
++#endif /* DEBUGABILITY */
++#ifdef DHD_PKT_LOGGING
++	dhd_os_attach_pktlog(&dhd->pub);
++#endif /* DHD_PKT_LOGGING */
++
++	if (dhd_sta_pool_init(&dhd->pub, DHD_MAX_STA) != BCME_OK) {
++		DHD_ERROR(("%s: Initializing %u sta\n", __FUNCTION__, DHD_MAX_STA));
++		goto fail;
++	}
++
++
++
++#ifndef BCMDBUS
++	/* Set up the watchdog timer */
++	init_timer_compat(&dhd->timer, dhd_watchdog, dhd);
++	dhd->default_wd_interval = dhd_watchdog_ms;
++
++	if (dhd_watchdog_prio >= 0) {
++		/* Initialize watchdog thread */
++		PROC_START(dhd_watchdog_thread, dhd, &dhd->thr_wdt_ctl, 0, "dhd_watchdog_thread");
++		if (dhd->thr_wdt_ctl.thr_pid < 0) {
++			goto fail;
++		}
++
++	} else {
++		dhd->thr_wdt_ctl.thr_pid = -1;
++	}
++
++#ifdef DHD_PCIE_RUNTIMEPM
++	/* Setup up the runtime PM Idlecount timer */
++	init_timer_compat(&dhd->rpm_timer, dhd_runtimepm, dhd);
++	dhd->rpm_timer_valid = FALSE;
++
++	dhd->thr_rpm_ctl.thr_pid = DHD_PID_KT_INVALID;
++	PROC_START(dhd_rpm_state_thread, dhd, &dhd->thr_rpm_ctl, 0, "dhd_rpm_state_thread");
++	if (dhd->thr_rpm_ctl.thr_pid < 0) {
++		goto fail;
++	}
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++#ifdef DEBUGGER
++	debugger_init((void *) bus);
++#endif
++
++	/* Set up the bottom half handler */
++	if (dhd_dpc_prio >= 0) {
++		/* Initialize DPC thread */
++		PROC_START(dhd_dpc_thread, dhd, &dhd->thr_dpc_ctl, 0, "dhd_dpc");
++		if (dhd->thr_dpc_ctl.thr_pid < 0) {
++			goto fail;
++		}
++	} else {
++		/*  use tasklet for dpc */
++		tasklet_init(&dhd->tasklet, dhd_dpc, (ulong)dhd);
++		dhd->thr_dpc_ctl.thr_pid = -1;
++	}
++
++	if (dhd->rxthread_enabled) {
++		bzero(&dhd->pub.skbbuf[0], sizeof(void *) * MAXSKBPEND);
++		/* Initialize RXF thread */
++		PROC_START(dhd_rxf_thread, dhd, &dhd->thr_rxf_ctl, 0, "dhd_rxf");
++		if (dhd->thr_rxf_ctl.thr_pid < 0) {
++			goto fail;
++		}
++	}
++#endif /* !BCMDBUS */
++#ifdef SHOW_LOGTRACE
++	skb_queue_head_init(&dhd->evt_trace_queue);
++#endif /* SHOW_LOGTRACE */
++
++	dhd_state |= DHD_ATTACH_STATE_THREADS_CREATED;
++
++#if defined(CONFIG_PM_SLEEP)
++	if (!dhd_pm_notifier_registered) {
++		dhd_pm_notifier_registered = TRUE;
++		dhd->pm_notifier.notifier_call = dhd_pm_callback;
++		dhd->pm_notifier.priority = 10;
++		register_pm_notifier(&dhd->pm_notifier);
++	}
++
++#endif /* CONFIG_PM_SLEEP */
++
++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND)
++	dhd->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 20;
++	dhd->early_suspend.suspend = dhd_early_suspend;
++	dhd->early_suspend.resume = dhd_late_resume;
++	register_early_suspend(&dhd->early_suspend);
++	dhd_state |= DHD_ATTACH_STATE_EARLYSUSPEND_DONE;
++#endif /* CONFIG_HAS_EARLYSUSPEND && DHD_USE_EARLYSUSPEND */
++
++#ifdef ARP_OFFLOAD_SUPPORT
++	dhd->pend_ipaddr = 0;
++	if (!dhd_inetaddr_notifier_registered) {
++		dhd_inetaddr_notifier_registered = TRUE;
++		register_inetaddr_notifier(&dhd_inetaddr_notifier);
++	}
++#endif /* ARP_OFFLOAD_SUPPORT */
++
++#if defined(CONFIG_IPV6) && defined(IPV6_NDO_SUPPORT)
++	if (!dhd_inet6addr_notifier_registered) {
++		dhd_inet6addr_notifier_registered = TRUE;
++		register_inet6addr_notifier(&dhd_inet6addr_notifier);
++	}
++#endif /* CONFIG_IPV6 && IPV6_NDO_SUPPORT */
++	dhd->dhd_deferred_wq = dhd_deferred_work_init((void *)dhd);
++#ifdef DEBUG_CPU_FREQ
++	dhd->new_freq = alloc_percpu(int);
++	dhd->freq_trans.notifier_call = dhd_cpufreq_notifier;
++	cpufreq_register_notifier(&dhd->freq_trans, CPUFREQ_TRANSITION_NOTIFIER);
++#endif
++#ifdef DHDTCPACK_SUPPRESS
++	dhd_tcpack_suppress_set(&dhd->pub, TCPACK_SUP_DEFAULT);
++#endif /* DHDTCPACK_SUPPRESS */
++
++#if defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW)
++#endif /* defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW) */
++
++
++#ifdef DHD_DEBUG_PAGEALLOC
++	register_page_corrupt_cb(dhd_page_corrupt_cb, &dhd->pub);
++#endif /* DHD_DEBUG_PAGEALLOC */
++
++#if defined(DHD_LB)
++
++	dhd_lb_set_default_cpus(dhd);
++
++	/* Initialize the CPU Masks */
++	if (dhd_cpumasks_init(dhd) == 0) {
++		/* Now we have the current CPU maps, run through candidacy */
++		dhd_select_cpu_candidacy(dhd);
++		/*
++		* If we are able to initialize CPU masks, lets register to the
++		* CPU Hotplug framework to change the CPU for each job dynamically
++		* using candidacy algorithm.
++		*/
++		dhd->cpu_notifier.notifier_call = dhd_cpu_callback;
++		register_hotcpu_notifier(&dhd->cpu_notifier); /* Register a callback */
++	} else {
++		/*
++		* We are unable to initialize CPU masks, so candidacy algorithm
++		* won't run, but still Load Balancing will be honoured based
++		* on the CPUs allocated for a given job statically during init
++		*/
++		dhd->cpu_notifier.notifier_call = NULL;
++		DHD_ERROR(("%s():dhd_cpumasks_init failed CPUs for JOB would be static\n",
++			__FUNCTION__));
++	}
++
++#ifdef DHD_LB_TXP
++#ifdef DHD_LB_TXP_DEFAULT_ENAB
++	/* Trun ON the feature by default */
++	atomic_set(&dhd->lb_txp_active, 1);
++#else
++	/* Trun OFF the feature by default */
++	atomic_set(&dhd->lb_txp_active, 0);
++#endif /* DHD_LB_TXP_DEFAULT_ENAB */
++#endif /* DHD_LB_TXP */
++
++	DHD_LB_STATS_INIT(&dhd->pub);
++
++	/* Initialize the Load Balancing Tasklets and Napi object */
++#if defined(DHD_LB_TXC)
++	tasklet_init(&dhd->tx_compl_tasklet,
++		dhd_lb_tx_compl_handler, (ulong)(&dhd->pub));
++	INIT_WORK(&dhd->tx_compl_dispatcher_work, dhd_tx_compl_dispatcher_fn);
++	DHD_INFO(("%s load balance init tx_compl_tasklet\n", __FUNCTION__));
++#endif /* DHD_LB_TXC */
++
++#if defined(DHD_LB_RXC)
++	tasklet_init(&dhd->rx_compl_tasklet,
++		dhd_lb_rx_compl_handler, (ulong)(&dhd->pub));
++	DHD_INFO(("%s load balance init rx_compl_tasklet\n", __FUNCTION__));
++#endif /* DHD_LB_RXC */
++
++#if defined(DHD_LB_RXP)
++	__skb_queue_head_init(&dhd->rx_pend_queue);
++	skb_queue_head_init(&dhd->rx_napi_queue);
++	/* Initialize the work that dispatches NAPI job to a given core */
++	INIT_WORK(&dhd->rx_napi_dispatcher_work, dhd_rx_napi_dispatcher_fn);
++	DHD_INFO(("%s load balance init rx_napi_queue\n", __FUNCTION__));
++#endif /* DHD_LB_RXP */
++
++#if defined(DHD_LB_TXP)
++	INIT_WORK(&dhd->tx_dispatcher_work, dhd_tx_dispatcher_work);
++	skb_queue_head_init(&dhd->tx_pend_queue);
++	/* Initialize the work that dispatches TX job to a given core */
++	tasklet_init(&dhd->tx_tasklet,
++		dhd_lb_tx_handler, (ulong)(dhd));
++	DHD_INFO(("%s load balance init tx_pend_queue\n", __FUNCTION__));
++#endif /* DHD_LB_TXP */
++
++	dhd_state |= DHD_ATTACH_STATE_LB_ATTACH_DONE;
++#endif /* DHD_LB */
++
++#ifdef SHOW_LOGTRACE
++	INIT_WORK(&dhd->event_log_dispatcher_work, dhd_event_logtrace_process);
++#endif /* SHOW_LOGTRACE */
++
++	DHD_SSSR_MEMPOOL_INIT(&dhd->pub);
++
++#ifdef REPORT_FATAL_TIMEOUTS
++	init_dhd_timeouts(&dhd->pub);
++#endif /* REPORT_FATAL_TIMEOUTS */
++#ifdef BCMPCIE
++	dhd->pub.extended_trap_data = MALLOCZ(osh, BCMPCIE_EXT_TRAP_DATA_MAXLEN);
++	if (dhd->pub.extended_trap_data == NULL) {
++		DHD_ERROR(("%s: Failed to alloc extended_trap_data\n", __FUNCTION__));
++	}
++#endif /* BCMPCIE */
++
++	(void)dhd_sysfs_init(dhd);
++
++	dhd_state |= DHD_ATTACH_STATE_DONE;
++	dhd->dhd_state = dhd_state;
++
++	dhd_found++;
++
++	return &dhd->pub;
++
++fail:
++	if (dhd_state >= DHD_ATTACH_STATE_DHD_ALLOC) {
++		DHD_TRACE(("%s: Calling dhd_detach dhd_state 0x%x &dhd->pub %p\n",
++			__FUNCTION__, dhd_state, &dhd->pub));
++		dhd->dhd_state = dhd_state;
++		dhd_detach(&dhd->pub);
++		dhd_free(&dhd->pub);
++	}
++dhd_null_flag:
++	return NULL;
++}
++
++int dhd_get_fw_mode(dhd_info_t *dhdinfo)
++{
++	if (strstr(dhdinfo->fw_path, "_apsta") != NULL)
++		return DHD_FLAG_HOSTAP_MODE;
++	if (strstr(dhdinfo->fw_path, "_p2p") != NULL)
++		return DHD_FLAG_P2P_MODE;
++	if (strstr(dhdinfo->fw_path, "_ibss") != NULL)
++		return DHD_FLAG_IBSS_MODE;
++	if (strstr(dhdinfo->fw_path, "_mfg") != NULL)
++		return DHD_FLAG_MFG_MODE;
++
++	return DHD_FLAG_STA_MODE;
++}
++
++int dhd_bus_get_fw_mode(dhd_pub_t *dhdp)
++{
++	return dhd_get_fw_mode(dhdp->info);
++}
++
++bool dhd_update_fw_nv_path(dhd_info_t *dhdinfo)
++{
++	int fw_len;
++	int nv_len;
++	int clm_len;
++	int conf_len;
++	const char *fw = NULL;
++	const char *nv = NULL;
++	const char *clm = NULL;
++	const char *conf = NULL;
++#ifdef DHD_UCODE_DOWNLOAD
++	int uc_len;
++	const char *uc = NULL;
++#endif /* DHD_UCODE_DOWNLOAD */
++	wifi_adapter_info_t *adapter = dhdinfo->adapter;
++	int fw_path_len = sizeof(dhdinfo->fw_path);
++	int nv_path_len = sizeof(dhdinfo->nv_path);
++
++
++	/* Update firmware and nvram path. The path may be from adapter info or module parameter
++	 * The path from adapter info is used for initialization only (as it won't change).
++	 *
++	 * The firmware_path/nvram_path module parameter may be changed by the system at run
++	 * time. When it changes we need to copy it to dhdinfo->fw_path. Also Android private
++	 * command may change dhdinfo->fw_path. As such we need to clear the path info in
++	 * module parameter after it is copied. We won't update the path until the module parameter
++	 * is changed again (first character is not '\0')
++	 */
++
++	/* set default firmware and nvram path for built-in type driver */
++//	if (!dhd_download_fw_on_driverload) {
++#ifdef CONFIG_BCMDHD_FW_PATH
++		fw = CONFIG_BCMDHD_FW_PATH;
++#endif /* CONFIG_BCMDHD_FW_PATH */
++#ifdef CONFIG_BCMDHD_NVRAM_PATH
++		nv = CONFIG_BCMDHD_NVRAM_PATH;
++#endif /* CONFIG_BCMDHD_NVRAM_PATH */
++//	}
++
++	/* check if we need to initialize the path */
++	if (dhdinfo->fw_path[0] == '\0') {
++		if (adapter && adapter->fw_path && adapter->fw_path[0] != '\0')
++			fw = adapter->fw_path;
++
++	}
++	if (dhdinfo->nv_path[0] == '\0') {
++		if (adapter && adapter->nv_path && adapter->nv_path[0] != '\0')
++			nv = adapter->nv_path;
++	}
++	if (dhdinfo->clm_path[0] == '\0') {
++		if (adapter && adapter->clm_path && adapter->clm_path[0] != '\0')
++			clm = adapter->clm_path;
++	}
++	if (dhdinfo->conf_path[0] == '\0') {
++		if (adapter && adapter->conf_path && adapter->conf_path[0] != '\0')
++			conf = adapter->conf_path;
++	}
++
++	/* Use module parameter if it is valid, EVEN IF the path has not been initialized
++	 *
++	 * TODO: need a solution for multi-chip, can't use the same firmware for all chips
++	 */
++	if (firmware_path[0] != '\0')
++		fw = firmware_path;
++	if (nvram_path[0] != '\0')
++		nv = nvram_path;
++	if (clm_path[0] != '\0')
++		clm = clm_path;
++	if (config_path[0] != '\0')
++		conf = config_path;
++#ifdef DHD_UCODE_DOWNLOAD
++	if (ucode_path[0] != '\0')
++		uc = ucode_path;
++#endif /* DHD_UCODE_DOWNLOAD */
++
++	if (fw && fw[0] != '\0') {
++		fw_len = strlen(fw);
++		if (fw_len >= fw_path_len) {
++			DHD_ERROR(("fw path len exceeds max len of dhdinfo->fw_path\n"));
++			return FALSE;
++		}
++		strncpy(dhdinfo->fw_path, fw, fw_path_len);
++		if (dhdinfo->fw_path[fw_len-1] == '\n')
++		       dhdinfo->fw_path[fw_len-1] = '\0';
++	}
++	if (nv && nv[0] != '\0') {
++		nv_len = strlen(nv);
++		if (nv_len >= nv_path_len) {
++			DHD_ERROR(("nvram path len exceeds max len of dhdinfo->nv_path\n"));
++			return FALSE;
++		}
++		memset(dhdinfo->nv_path, 0, nv_path_len);
++		strncpy(dhdinfo->nv_path, nv, nv_path_len);
++#ifdef DHD_USE_SINGLE_NVRAM_FILE
++		/* Remove "_net" or "_mfg" tag from current nvram path */
++		{
++			char *nvram_tag = "nvram_";
++			char *ext_tag = ".txt";
++			char *sp_nvram = strnstr(dhdinfo->nv_path, nvram_tag, nv_path_len);
++			bool valid_buf = sp_nvram && ((uint32)(sp_nvram + strlen(nvram_tag) +
++				strlen(ext_tag) - dhdinfo->nv_path) <= nv_path_len);
++			if (valid_buf) {
++				char *sp = sp_nvram + strlen(nvram_tag) - 1;
++				uint32 padding_size = (uint32)(dhdinfo->nv_path +
++					nv_path_len - sp);
++				memset(sp, 0, padding_size);
++				strncat(dhdinfo->nv_path, ext_tag, strlen(ext_tag));
++				nv_len = strlen(dhdinfo->nv_path);
++				DHD_INFO(("%s: new nvram path = %s\n",
++					__FUNCTION__, dhdinfo->nv_path));
++			} else if (sp_nvram) {
++				DHD_ERROR(("%s: buffer space for nvram path is not enough\n",
++					__FUNCTION__));
++				return FALSE;
++			} else {
++				DHD_ERROR(("%s: Couldn't find the nvram tag. current"
++					" nvram path = %s\n", __FUNCTION__, dhdinfo->nv_path));
++			}
++		}
++#endif /* DHD_USE_SINGLE_NVRAM_FILE */
++		if (dhdinfo->nv_path[nv_len-1] == '\n')
++		       dhdinfo->nv_path[nv_len-1] = '\0';
++	}
++	if (clm && clm[0] != '\0') {
++		clm_len = strlen(clm);
++		if (clm_len >= sizeof(dhdinfo->clm_path)) {
++			DHD_ERROR(("clm path len exceeds max len of dhdinfo->clm_path\n"));
++			return FALSE;
++		}
++		strncpy(dhdinfo->clm_path, clm, sizeof(dhdinfo->clm_path));
++		if (dhdinfo->clm_path[clm_len-1] == '\n')
++		       dhdinfo->clm_path[clm_len-1] = '\0';
++	}
++	if (conf && conf[0] != '\0') {
++		conf_len = strlen(conf);
++		if (conf_len >= sizeof(dhdinfo->conf_path)) {
++			DHD_ERROR(("config path len exceeds max len of dhdinfo->conf_path\n"));
++			return FALSE;
++		}
++		strncpy(dhdinfo->conf_path, conf, sizeof(dhdinfo->conf_path));
++		if (dhdinfo->conf_path[conf_len-1] == '\n')
++		       dhdinfo->conf_path[conf_len-1] = '\0';
++	}
++#ifdef DHD_UCODE_DOWNLOAD
++	if (uc && uc[0] != '\0') {
++		uc_len = strlen(uc);
++		if (uc_len >= sizeof(dhdinfo->uc_path)) {
++			DHD_ERROR(("uc path len exceeds max len of dhdinfo->uc_path\n"));
++			return FALSE;
++		}
++		strncpy(dhdinfo->uc_path, uc, sizeof(dhdinfo->uc_path));
++		if (dhdinfo->uc_path[uc_len-1] == '\n')
++		       dhdinfo->uc_path[uc_len-1] = '\0';
++	}
++#endif /* DHD_UCODE_DOWNLOAD */
++
++#if 0
++	/* clear the path in module parameter */
++	if (dhd_download_fw_on_driverload) {
++		firmware_path[0] = '\0';
++		nvram_path[0] = '\0';
++		clm_path[0] = '\0';
++		config_path[0] = '\0';
++	}
++#endif
++#ifdef DHD_UCODE_DOWNLOAD
++	ucode_path[0] = '\0';
++	DHD_ERROR(("ucode path: %s\n", dhdinfo->uc_path));
++#endif /* DHD_UCODE_DOWNLOAD */
++
++#ifndef BCMEMBEDIMAGE
++	/* fw_path and nv_path are not mandatory for BCMEMBEDIMAGE */
++	if (dhdinfo->fw_path[0] == '\0') {
++		DHD_ERROR(("firmware path not found\n"));
++		return FALSE;
++	}
++	if (dhdinfo->nv_path[0] == '\0') {
++		DHD_ERROR(("nvram path not found\n"));
++		return FALSE;
++	}
++#endif /* BCMEMBEDIMAGE */
++
++	return TRUE;
++}
++
++#if defined(BT_OVER_SDIO)
++extern bool dhd_update_btfw_path(dhd_info_t *dhdinfo, char* btfw_path)
++{
++	int fw_len;
++	const char *fw = NULL;
++	wifi_adapter_info_t *adapter = dhdinfo->adapter;
++
++
++	/* Update bt firmware path. The path may be from adapter info or module parameter
++	 * The path from adapter info is used for initialization only (as it won't change).
++	 *
++	 * The btfw_path module parameter may be changed by the system at run
++	 * time. When it changes we need to copy it to dhdinfo->btfw_path. Also Android private
++	 * command may change dhdinfo->btfw_path. As such we need to clear the path info in
++	 * module parameter after it is copied. We won't update the path until the module parameter
++	 * is changed again (first character is not '\0')
++	 */
++
++	/* set default firmware and nvram path for built-in type driver */
++	if (!dhd_download_fw_on_driverload) {
++#ifdef CONFIG_BCMDHD_BTFW_PATH
++		fw = CONFIG_BCMDHD_BTFW_PATH;
++#endif /* CONFIG_BCMDHD_FW_PATH */
++	}
++
++	/* check if we need to initialize the path */
++	if (dhdinfo->btfw_path[0] == '\0') {
++		if (adapter && adapter->btfw_path && adapter->btfw_path[0] != '\0')
++			fw = adapter->btfw_path;
++	}
++
++	/* Use module parameter if it is valid, EVEN IF the path has not been initialized
++	 */
++	if (btfw_path[0] != '\0')
++		fw = btfw_path;
++
++	if (fw && fw[0] != '\0') {
++		fw_len = strlen(fw);
++		if (fw_len >= sizeof(dhdinfo->btfw_path)) {
++			DHD_ERROR(("fw path len exceeds max len of dhdinfo->btfw_path\n"));
++			return FALSE;
++		}
++		strncpy(dhdinfo->btfw_path, fw, sizeof(dhdinfo->btfw_path));
++		if (dhdinfo->btfw_path[fw_len-1] == '\n')
++		       dhdinfo->btfw_path[fw_len-1] = '\0';
++	}
++
++	/* clear the path in module parameter */
++	btfw_path[0] = '\0';
++
++	if (dhdinfo->btfw_path[0] == '\0') {
++		DHD_ERROR(("bt firmware path not found\n"));
++		return FALSE;
++	}
++
++	return TRUE;
++}
++#endif /* defined (BT_OVER_SDIO) */
++
++
++#ifdef CUSTOMER_HW4_DEBUG
++bool dhd_validate_chipid(dhd_pub_t *dhdp)
++{
++	uint chipid = dhd_bus_chip_id(dhdp);
++	uint config_chipid;
++
++#ifdef BCM4361_CHIP
++	config_chipid = BCM4361_CHIP_ID;
++#elif defined(BCM4359_CHIP)
++	config_chipid = BCM4359_CHIP_ID;
++#elif defined(BCM4358_CHIP)
++	config_chipid = BCM4358_CHIP_ID;
++#elif defined(BCM4354_CHIP)
++	config_chipid = BCM4354_CHIP_ID;
++#elif defined(BCM4339_CHIP)
++	config_chipid = BCM4339_CHIP_ID;
++#elif defined(BCM43349_CHIP)
++	config_chipid = BCM43349_CHIP_ID;
++#elif defined(BCM4335_CHIP)
++	config_chipid = BCM4335_CHIP_ID;
++#elif defined(BCM43241_CHIP)
++	config_chipid = BCM4324_CHIP_ID;
++#elif defined(BCM4330_CHIP)
++	config_chipid = BCM4330_CHIP_ID;
++#elif defined(BCM43430_CHIP)
++	config_chipid = BCM43430_CHIP_ID;
++#elif defined(BCM43018_CHIP)
++	config_chipid = BCM43018_CHIP_ID;
++#elif defined(BCM43455_CHIP)
++	config_chipid = BCM4345_CHIP_ID;
++#elif defined(BCM4334W_CHIP)
++	config_chipid = BCM43342_CHIP_ID;
++#elif defined(BCM43454_CHIP)
++	config_chipid = BCM43454_CHIP_ID;
++#elif defined(BCM43012_CHIP_)
++	config_chipid = BCM43012_CHIP_ID;
++#else
++	DHD_ERROR(("%s: Unknown chip id, if you use new chipset,"
++		" please add CONFIG_BCMXXXX into the Kernel and"
++		" BCMXXXX_CHIP definition into the DHD driver\n",
++		__FUNCTION__));
++	config_chipid = 0;
++
++	return FALSE;
++#endif /* BCM4354_CHIP */
++
++#ifdef SUPPORT_MULTIPLE_CHIP_4345X
++	if (config_chipid == BCM43454_CHIP_ID || config_chipid == BCM4345_CHIP_ID) {
++		return TRUE;
++	}
++#endif /* SUPPORT_MULTIPLE_CHIP_4345X */
++#if defined(BCM4359_CHIP)
++	if (chipid == BCM4355_CHIP_ID && config_chipid == BCM4359_CHIP_ID) {
++		return TRUE;
++	}
++#endif /* BCM4359_CHIP */
++#if defined(BCM4361_CHIP)
++	if (chipid == BCM4347_CHIP_ID && config_chipid == BCM4361_CHIP_ID) {
++		return TRUE;
++	}
++#endif /* BCM4361_CHIP */
++
++	return config_chipid == chipid;
++}
++#endif /* CUSTOMER_HW4_DEBUG */
++
++#if defined(BT_OVER_SDIO)
++wlan_bt_handle_t dhd_bt_get_pub_hndl(void)
++{
++	DHD_ERROR(("%s: g_dhd_pub %p\n", __FUNCTION__, g_dhd_pub));
++	/* assuming that dhd_pub_t type pointer is available from a global variable */
++	return (wlan_bt_handle_t) g_dhd_pub;
++} EXPORT_SYMBOL(dhd_bt_get_pub_hndl);
++
++int dhd_download_btfw(wlan_bt_handle_t handle, char* btfw_path)
++{
++	int ret = -1;
++	dhd_pub_t *dhdp = (dhd_pub_t *)handle;
++	dhd_info_t *dhd = (dhd_info_t*)dhdp->info;
++
++
++	/* Download BT firmware image to the dongle */
++	if (dhd->pub.busstate == DHD_BUS_DATA && dhd_update_btfw_path(dhd, btfw_path)) {
++		DHD_INFO(("%s: download btfw from: %s\n", __FUNCTION__, dhd->btfw_path));
++		ret = dhd_bus_download_btfw(dhd->pub.bus, dhd->pub.osh, dhd->btfw_path);
++		if (ret < 0) {
++			DHD_ERROR(("%s: failed to download btfw from: %s\n",
++				__FUNCTION__, dhd->btfw_path));
++			return ret;
++		}
++	}
++	return ret;
++} EXPORT_SYMBOL(dhd_download_btfw);
++#endif /* defined (BT_OVER_SDIO) */
++
++#ifndef BCMDBUS
++int
++dhd_bus_start(dhd_pub_t *dhdp)
++{
++	int ret = -1;
++	dhd_info_t *dhd = (dhd_info_t*)dhdp->info;
++	unsigned long flags;
++
++#if defined(DHD_DEBUG) && defined(BCMSDIO)
++	int fw_download_start = 0, fw_download_end = 0, f2_sync_start = 0, f2_sync_end = 0;
++#endif /* DHD_DEBUG && BCMSDIO */
++	ASSERT(dhd);
++
++	DHD_TRACE(("Enter %s:\n", __FUNCTION__));
++
++	DHD_PERIM_LOCK(dhdp);
++#ifdef HOFFLOAD_MODULES
++	dhd_linux_get_modfw_address(dhdp);
++#endif
++	/* try to download image and nvram to the dongle */
++	if  (dhd->pub.busstate == DHD_BUS_DOWN && dhd_update_fw_nv_path(dhd)) {
++		/* Indicate FW Download has not yet done */
++		dhd->pub.fw_download_done = FALSE;
++		DHD_INFO(("%s download fw %s, nv %s, conf %s\n",
++			__FUNCTION__, dhd->fw_path, dhd->nv_path, dhd->conf_path));
++#if defined(DHD_DEBUG) && defined(BCMSDIO)
++		fw_download_start = OSL_SYSUPTIME();
++#endif /* DHD_DEBUG && BCMSDIO */
++		ret = dhd_bus_download_firmware(dhd->pub.bus, dhd->pub.osh,
++			dhd->fw_path, dhd->nv_path, dhd->clm_path, dhd->conf_path);
++#if defined(DHD_DEBUG) && defined(BCMSDIO)
++		fw_download_end = OSL_SYSUPTIME();
++#endif /* DHD_DEBUG && BCMSDIO */
++		if (ret < 0) {
++			DHD_ERROR(("%s: failed to download firmware %s\n",
++				__FUNCTION__, dhd->fw_path));
++			DHD_PERIM_UNLOCK(dhdp);
++			return ret;
++		}
++		/* Indicate FW Download has succeeded */
++		dhd->pub.fw_download_done = TRUE;
++	}
++	if (dhd->pub.busstate != DHD_BUS_LOAD) {
++		DHD_PERIM_UNLOCK(dhdp);
++		return -ENETDOWN;
++	}
++
++#ifdef BCMSDIO
++	dhd_os_sdlock(dhdp);
++#endif /* BCMSDIO */
++
++	/* Start the watchdog timer */
++	dhd->pub.tickcnt = 0;
++	dhd_os_wd_timer(&dhd->pub, dhd_watchdog_ms);
++
++	/* Bring up the bus */
++	if ((ret = dhd_bus_init(&dhd->pub, FALSE)) != 0) {
++
++		DHD_ERROR(("%s, dhd_bus_init failed %d\n", __FUNCTION__, ret));
++#ifdef BCMSDIO
++		dhd_os_sdunlock(dhdp);
++#endif /* BCMSDIO */
++		DHD_PERIM_UNLOCK(dhdp);
++		return ret;
++	}
++
++	DHD_ENABLE_RUNTIME_PM(&dhd->pub);
++
++#ifdef DHD_ULP
++	dhd_ulp_set_ulp_state(dhdp, DHD_ULP_DISABLED);
++#endif /* DHD_ULP */
++#if defined(OOB_INTR_ONLY) || defined(BCMPCIE_OOB_HOST_WAKE)
++	/* Host registration for OOB interrupt */
++	if (dhd_bus_oob_intr_register(dhdp)) {
++		/* deactivate timer and wait for the handler to finish */
++#if !defined(BCMPCIE_OOB_HOST_WAKE)
++		DHD_GENERAL_LOCK(&dhd->pub, flags);
++		dhd->wd_timer_valid = FALSE;
++		DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++		_del_timer_sync(&dhd->timer);
++
++#endif /* !BCMPCIE_OOB_HOST_WAKE */
++		DHD_DISABLE_RUNTIME_PM(&dhd->pub);
++		DHD_PERIM_UNLOCK(dhdp);
++		DHD_ERROR(("%s Host failed to register for OOB\n", __FUNCTION__));
++		return -ENODEV;
++	}
++
++#if defined(BCMPCIE_OOB_HOST_WAKE)
++	dhd_bus_oob_intr_set(dhdp, TRUE);
++#else
++	/* Enable oob at firmware */
++	dhd_enable_oob_intr(dhd->pub.bus, TRUE);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#elif defined(FORCE_WOWLAN)
++	/* Enable oob at firmware */
++	dhd_enable_oob_intr(dhd->pub.bus, TRUE);
++#endif 
++#ifdef PCIE_FULL_DONGLE
++	{
++		/* max_h2d_rings includes H2D common rings */
++		uint32 max_h2d_rings = dhd_bus_max_h2d_queues(dhd->pub.bus);
++
++		DHD_ERROR(("%s: Initializing %u h2drings\n", __FUNCTION__,
++			max_h2d_rings));
++		if ((ret = dhd_flow_rings_init(&dhd->pub, max_h2d_rings)) != BCME_OK) {
++#ifdef BCMSDIO
++			dhd_os_sdunlock(dhdp);
++#endif /* BCMSDIO */
++			DHD_PERIM_UNLOCK(dhdp);
++			return ret;
++		}
++	}
++#endif /* PCIE_FULL_DONGLE */
++
++	/* Do protocol initialization necessary for IOCTL/IOVAR */
++	ret = dhd_prot_init(&dhd->pub);
++	if (unlikely(ret) != BCME_OK) {
++		DHD_PERIM_UNLOCK(dhdp);
++		DHD_OS_WD_WAKE_UNLOCK(&dhd->pub);
++		return ret;
++	}
++
++	/* If bus is not ready, can't come up */
++	if (dhd->pub.busstate != DHD_BUS_DATA) {
++		DHD_GENERAL_LOCK(&dhd->pub, flags);
++		dhd->wd_timer_valid = FALSE;
++		DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++		_del_timer_sync(&dhd->timer);
++		DHD_ERROR(("%s failed bus is not ready\n", __FUNCTION__));
++		DHD_DISABLE_RUNTIME_PM(&dhd->pub);
++#ifdef BCMSDIO
++		dhd_os_sdunlock(dhdp);
++#endif /* BCMSDIO */
++		DHD_PERIM_UNLOCK(dhdp);
++		return -ENODEV;
++	}
++
++#ifdef BCMSDIO
++	dhd_os_sdunlock(dhdp);
++#endif /* BCMSDIO */
++
++	/* Bus is ready, query any dongle information */
++#if defined(DHD_DEBUG) && defined(BCMSDIO)
++	f2_sync_start = OSL_SYSUPTIME();
++#endif /* DHD_DEBUG && BCMSDIO */
++	if ((ret = dhd_sync_with_dongle(&dhd->pub)) < 0) {
++		DHD_GENERAL_LOCK(&dhd->pub, flags);
++		dhd->wd_timer_valid = FALSE;
++		DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++		_del_timer_sync(&dhd->timer);
++		DHD_ERROR(("%s failed to sync with dongle\n", __FUNCTION__));
++		DHD_OS_WD_WAKE_UNLOCK(&dhd->pub);
++		DHD_PERIM_UNLOCK(dhdp);
++		return ret;
++	}
++#if defined(CONFIG_SOC_EXYNOS8895)
++	DHD_ERROR(("%s: Enable L1ss EP side\n", __FUNCTION__));
++	exynos_pcie_l1ss_ctrl(1, PCIE_L1SS_CTRL_WIFI);
++#endif /* CONFIG_SOC_EXYNOS8895 */
++
++#if defined(DHD_DEBUG) && defined(BCMSDIO)
++	f2_sync_end = OSL_SYSUPTIME();
++	DHD_ERROR(("Time taken for FW download and F2 ready is: %d msec\n",
++			(fw_download_end - fw_download_start) + (f2_sync_end - f2_sync_start)));
++#endif /* DHD_DEBUG && BCMSDIO */
++
++#ifdef ARP_OFFLOAD_SUPPORT
++	if (dhd->pend_ipaddr) {
++#ifdef AOE_IP_ALIAS_SUPPORT
++		aoe_update_host_ipv4_table(&dhd->pub, dhd->pend_ipaddr, TRUE, 0);
++#endif /* AOE_IP_ALIAS_SUPPORT */
++		dhd->pend_ipaddr = 0;
++	}
++#endif /* ARP_OFFLOAD_SUPPORT */
++
++#if defined(TRAFFIC_MGMT_DWM)
++	bzero(&dhd->pub.dhd_tm_dwm_tbl, sizeof(dhd_trf_mgmt_dwm_tbl_t));
++#endif 
++	DHD_PERIM_UNLOCK(dhdp);
++	return 0;
++}
++#endif /* !BCMDBUS */
++
++#ifdef WLTDLS
++int _dhd_tdls_enable(dhd_pub_t *dhd, bool tdls_on, bool auto_on, struct ether_addr *mac)
++{
++	uint32 tdls = tdls_on;
++	int ret = 0;
++	uint32 tdls_auto_op = 0;
++	uint32 tdls_idle_time = CUSTOM_TDLS_IDLE_MODE_SETTING;
++	int32 tdls_rssi_high = CUSTOM_TDLS_RSSI_THRESHOLD_HIGH;
++	int32 tdls_rssi_low = CUSTOM_TDLS_RSSI_THRESHOLD_LOW;
++	BCM_REFERENCE(mac);
++	if (!FW_SUPPORTED(dhd, tdls))
++		return BCME_ERROR;
++
++	if (dhd->tdls_enable == tdls_on)
++		goto auto_mode;
++	ret = dhd_iovar(dhd, 0, "tdls_enable", (char *)&tdls, sizeof(tdls), NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: tdls %d failed %d\n", __FUNCTION__, tdls, ret));
++		goto exit;
++	}
++	dhd->tdls_enable = tdls_on;
++auto_mode:
++
++	tdls_auto_op = auto_on;
++	ret = dhd_iovar(dhd, 0, "tdls_auto_op", (char *)&tdls_auto_op, sizeof(tdls_auto_op), NULL,
++			0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: tdls_auto_op failed %d\n", __FUNCTION__, ret));
++		goto exit;
++	}
++
++	if (tdls_auto_op) {
++		ret = dhd_iovar(dhd, 0, "tdls_idle_time", (char *)&tdls_idle_time,
++				sizeof(tdls_idle_time), NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s: tdls_idle_time failed %d\n", __FUNCTION__, ret));
++			goto exit;
++		}
++		ret = dhd_iovar(dhd, 0, "tdls_rssi_high", (char *)&tdls_rssi_high,
++				sizeof(tdls_rssi_high), NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s: tdls_rssi_high failed %d\n", __FUNCTION__, ret));
++			goto exit;
++		}
++		ret = dhd_iovar(dhd, 0, "tdls_rssi_low", (char *)&tdls_rssi_low,
++				sizeof(tdls_rssi_low), NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s: tdls_rssi_low failed %d\n", __FUNCTION__, ret));
++			goto exit;
++		}
++	}
++
++exit:
++	return ret;
++}
++
++int dhd_tdls_enable(struct net_device *dev, bool tdls_on, bool auto_on, struct ether_addr *mac)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret = 0;
++	if (dhd)
++		ret = _dhd_tdls_enable(&dhd->pub, tdls_on, auto_on, mac);
++	else
++		ret = BCME_ERROR;
++	return ret;
++}
++
++int
++dhd_tdls_set_mode(dhd_pub_t *dhd, bool wfd_mode)
++{
++	int ret = 0;
++	bool auto_on = false;
++	uint32 mode =  wfd_mode;
++
++#ifdef ENABLE_TDLS_AUTO_MODE
++	if (wfd_mode) {
++		auto_on = false;
++	} else {
++		auto_on = true;
++	}
++#else
++	auto_on = false;
++#endif /* ENABLE_TDLS_AUTO_MODE */
++	ret = _dhd_tdls_enable(dhd, false, auto_on, NULL);
++	if (ret < 0) {
++		DHD_ERROR(("Disable tdls_auto_op failed. %d\n", ret));
++		return ret;
++	}
++
++	ret = dhd_iovar(dhd, 0, "tdls_wfd_mode", (char *)&mode, sizeof(mode), NULL, 0, TRUE);
++	if ((ret < 0) && (ret != BCME_UNSUPPORTED)) {
++		DHD_ERROR(("%s: tdls_wfd_mode faile_wfd_mode %d\n", __FUNCTION__, ret));
++		return ret;
++	}
++
++	ret = _dhd_tdls_enable(dhd, true, auto_on, NULL);
++	if (ret < 0) {
++		DHD_ERROR(("enable tdls_auto_op failed. %d\n", ret));
++		return ret;
++	}
++
++	dhd->tdls_mode = mode;
++	return ret;
++}
++#ifdef PCIE_FULL_DONGLE
++int dhd_tdls_update_peer_info(dhd_pub_t *dhdp, wl_event_msg_t *event)
++{
++	dhd_pub_t *dhd_pub = dhdp;
++	tdls_peer_node_t *cur = dhd_pub->peer_tbl.node;
++	tdls_peer_node_t *new = NULL, *prev = NULL;
++	int ifindex = dhd_ifname2idx(dhd_pub->info, event->ifname);
++	uint8 *da = (uint8 *)&event->addr.octet[0];
++	bool connect = FALSE;
++	uint32 reason = ntoh32(event->reason);
++	unsigned long flags;
++
++	if (reason == WLC_E_TDLS_PEER_CONNECTED)
++		connect = TRUE;
++	else if (reason == WLC_E_TDLS_PEER_DISCONNECTED)
++		connect = FALSE;
++	else
++	{
++		DHD_ERROR(("%s: TDLS Event reason is unknown\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++	if (ifindex == DHD_BAD_IF)
++		return BCME_ERROR;
++
++	if (connect) {
++		while (cur != NULL) {
++			if (!memcmp(da, cur->addr, ETHER_ADDR_LEN)) {
++				DHD_ERROR(("%s: TDLS Peer exist already %d\n",
++					__FUNCTION__, __LINE__));
++				return BCME_ERROR;
++			}
++			cur = cur->next;
++		}
++
++		new = MALLOC(dhd_pub->osh, sizeof(tdls_peer_node_t));
++		if (new == NULL) {
++			DHD_ERROR(("%s: Failed to allocate memory\n", __FUNCTION__));
++			return BCME_ERROR;
++		}
++		memcpy(new->addr, da, ETHER_ADDR_LEN);
++		DHD_TDLS_LOCK(&dhdp->tdls_lock, flags);
++		new->next = dhd_pub->peer_tbl.node;
++		dhd_pub->peer_tbl.node = new;
++		dhd_pub->peer_tbl.tdls_peer_count++;
++		DHD_TDLS_UNLOCK(&dhdp->tdls_lock, flags);
++
++	} else {
++		while (cur != NULL) {
++			if (!memcmp(da, cur->addr, ETHER_ADDR_LEN)) {
++				dhd_flow_rings_delete_for_peer(dhd_pub, (uint8)ifindex, da);
++				DHD_TDLS_LOCK(&dhdp->tdls_lock, flags);
++				if (prev)
++					prev->next = cur->next;
++				else
++					dhd_pub->peer_tbl.node = cur->next;
++				MFREE(dhd_pub->osh, cur, sizeof(tdls_peer_node_t));
++				dhd_pub->peer_tbl.tdls_peer_count--;
++				DHD_TDLS_UNLOCK(&dhdp->tdls_lock, flags);
++				return BCME_OK;
++			}
++			prev = cur;
++			cur = cur->next;
++		}
++		DHD_ERROR(("%s: TDLS Peer Entry Not found\n", __FUNCTION__));
++	}
++	return BCME_OK;
++}
++#endif /* PCIE_FULL_DONGLE */
++#endif 
++
++bool dhd_is_concurrent_mode(dhd_pub_t *dhd)
++{
++	if (!dhd)
++		return FALSE;
++
++	if (dhd->op_mode & DHD_FLAG_CONCURR_MULTI_CHAN_MODE)
++		return TRUE;
++	else if ((dhd->op_mode & DHD_FLAG_CONCURR_SINGLE_CHAN_MODE) ==
++		DHD_FLAG_CONCURR_SINGLE_CHAN_MODE)
++		return TRUE;
++	else
++		return FALSE;
++}
++#if !defined(AP) && defined(WLP2P)
++/* From Android JerryBean release, the concurrent mode is enabled by default and the firmware
++ * name would be fw_bcmdhd.bin. So we need to determine whether P2P is enabled in the STA
++ * firmware and accordingly enable concurrent mode (Apply P2P settings). SoftAP firmware
++ * would still be named as fw_bcmdhd_apsta.
++ */
++uint32
++dhd_get_concurrent_capabilites(dhd_pub_t *dhd)
++{
++	int32 ret = 0;
++	char buf[WLC_IOCTL_SMLEN];
++	bool mchan_supported = FALSE;
++	/* if dhd->op_mode is already set for HOSTAP and Manufacturing
++	 * test mode, that means we only will use the mode as it is
++	 */
++	if (dhd->op_mode & (DHD_FLAG_HOSTAP_MODE | DHD_FLAG_MFG_MODE))
++		return 0;
++	if (FW_SUPPORTED(dhd, vsdb)) {
++		mchan_supported = TRUE;
++	}
++	if (!FW_SUPPORTED(dhd, p2p)) {
++		DHD_TRACE(("Chip does not support p2p\n"));
++		return 0;
++	} else {
++		/* Chip supports p2p but ensure that p2p is really implemented in firmware or not */
++		memset(buf, 0, sizeof(buf));
++		ret = dhd_iovar(dhd, 0, "p2p", NULL, 0, (char *)&buf,
++				sizeof(buf), FALSE);
++		if (ret < 0) {
++			DHD_ERROR(("%s: Get P2P failed (error=%d)\n", __FUNCTION__, ret));
++			return 0;
++		} else {
++			if (buf[0] == 1) {
++				/* By default, chip supports single chan concurrency,
++				* now lets check for mchan
++				*/
++				ret = DHD_FLAG_CONCURR_SINGLE_CHAN_MODE;
++				if (mchan_supported)
++					ret |= DHD_FLAG_CONCURR_MULTI_CHAN_MODE;
++				if (FW_SUPPORTED(dhd, rsdb)) {
++					ret |= DHD_FLAG_RSDB_MODE;
++				}
++#ifdef WL_SUPPORT_MULTIP2P
++				if (FW_SUPPORTED(dhd, mp2p)) {
++					ret |= DHD_FLAG_MP2P_MODE;
++				}
++#endif /* WL_SUPPORT_MULTIP2P */
++#if defined(WL_ENABLE_P2P_IF) || defined(WL_CFG80211_P2P_DEV_IF)
++				return ret;
++#else
++				return 0;
++#endif /* WL_ENABLE_P2P_IF || WL_CFG80211_P2P_DEV_IF */
++			}
++		}
++	}
++	return 0;
++}
++#endif 
++
++#ifdef SUPPORT_AP_POWERSAVE
++#define RXCHAIN_PWRSAVE_PPS			10
++#define RXCHAIN_PWRSAVE_QUIET_TIME		10
++#define RXCHAIN_PWRSAVE_STAS_ASSOC_CHECK	0
++int dhd_set_ap_powersave(dhd_pub_t *dhdp, int ifidx, int enable)
++{
++	int32 pps = RXCHAIN_PWRSAVE_PPS;
++	int32 quiet_time = RXCHAIN_PWRSAVE_QUIET_TIME;
++	int32 stas_assoc_check = RXCHAIN_PWRSAVE_STAS_ASSOC_CHECK;
++	int ret;
++
++	if (enable) {
++		ret = dhd_iovar(dhdp, 0, "rxchain_pwrsave_enable", (char *)&enable, sizeof(enable),
++				NULL, 0, TRUE);
++		if (ret != BCME_OK) {
++			DHD_ERROR(("Failed to enable AP power save\n"));
++		}
++		ret = dhd_iovar(dhdp, 0, "rxchain_pwrsave_pps", (char *)&pps, sizeof(pps), NULL, 0,
++				TRUE);
++		if (ret != BCME_OK) {
++			DHD_ERROR(("Failed to set pps\n"));
++		}
++		ret = dhd_iovar(dhdp, 0, "rxchain_pwrsave_quiet_time", (char *)&quiet_time,
++				sizeof(quiet_time), NULL, 0, TRUE);
++		if (ret != BCME_OK) {
++			DHD_ERROR(("Failed to set quiet time\n"));
++		}
++		ret = dhd_iovar(dhdp, 0, "rxchain_pwrsave_stas_assoc_check",
++				(char *)&stas_assoc_check, sizeof(stas_assoc_check), NULL, 0, TRUE);
++		if (ret != BCME_OK) {
++			DHD_ERROR(("Failed to set stas assoc check\n"));
++		}
++	} else {
++		ret = dhd_iovar(dhdp, 0, "rxchain_pwrsave_enable", (char *)&enable, sizeof(enable),
++				NULL, 0, TRUE);
++		if (ret != BCME_OK) {
++			DHD_ERROR(("Failed to disable AP power save\n"));
++		}
++	}
++
++	return 0;
++}
++#endif /* SUPPORT_AP_POWERSAVE */
++
++
++
++
++#if defined(WLADPS) || defined(WLADPS_PRIVATE_CMD)
++int
++dhd_enable_adps(dhd_pub_t *dhd, uint8 on)
++{
++	int i;
++	int len;
++	int ret = BCME_OK;
++
++	bcm_iov_buf_t *iov_buf = NULL;
++	wl_adps_params_v1_t *data = NULL;
++	char buf[WL_EVENTING_MASK_LEN + 12];	/* Room for "event_msgs" + '\0' + bitvec  */
++
++	len = OFFSETOF(bcm_iov_buf_t, data) + sizeof(*data);
++	iov_buf = kmalloc(len, GFP_KERNEL);
++	if (iov_buf == NULL) {
++		DHD_ERROR(("%s - failed to allocate %d bytes for iov_buf\n", __FUNCTION__, len));
++		ret = BCME_NOMEM;
++		goto exit;
++	}
++
++	iov_buf->version = WL_ADPS_IOV_VER;
++	iov_buf->len = sizeof(*data);
++	iov_buf->id = WL_ADPS_IOV_MODE;
++
++	data = (wl_adps_params_v1_t *)iov_buf->data;
++	data->version = ADPS_SUB_IOV_VERSION_1;
++	data->length = sizeof(*data);
++	data->mode = on;
++
++	for (i = 1; i <= MAX_BANDS; i++) {
++		data->band = i;
++		bcm_mkiovar("adps", (char *)iov_buf, len, buf, sizeof(buf));
++		if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, buf, sizeof(buf), TRUE, 0)) < 0) {
++			if (ret == BCME_UNSUPPORTED) {
++				DHD_ERROR(("%s adps is not supported\n", __FUNCTION__));
++				ret = BCME_OK;
++				goto exit;
++			}
++			else {
++				DHD_ERROR(("%s fail to set adps %s for band %d (%d)\n",
++					__FUNCTION__, on ? "On" : "Off", i, ret));
++				goto exit;
++			}
++		}
++	}
++
++exit:
++	if (iov_buf) {
++		kfree(iov_buf);
++	}
++	return ret;
++}
++#endif /* WLADPS || WLADPS_PRIVATE_CMD */
++
++int
++dhd_preinit_ioctls(dhd_pub_t *dhd)
++{
++	int ret = 0;
++	char eventmask[WL_EVENTING_MASK_LEN];
++	char iovbuf[WL_EVENTING_MASK_LEN + 12];	/*  Room for "event_msgs" + '\0' + bitvec  */
++	uint32 buf_key_b4_m4 = 1;
++	uint8 msglen;
++	eventmsgs_ext_t *eventmask_msg = NULL;
++	char* iov_buf = NULL;
++	int ret2 = 0;
++	uint32 wnm_cap = 0;
++#if defined(CUSTOM_AMPDU_BA_WSIZE)
++	uint32 ampdu_ba_wsize = 0;
++#endif 
++#if defined(CUSTOM_AMPDU_MPDU)
++	int32 ampdu_mpdu = 0;
++#endif
++#if defined(CUSTOM_AMPDU_RELEASE)
++	int32 ampdu_release = 0;
++#endif
++#if defined(CUSTOM_AMSDU_AGGSF)
++	int32 amsdu_aggsf = 0;
++#endif
++	shub_control_t shub_ctl;
++
++#if defined(BCMSDIO) || defined(BCMDBUS)
++#ifdef PROP_TXSTATUS
++	int wlfc_enable = TRUE;
++#ifndef DISABLE_11N
++	uint32 hostreorder = 1;
++	uint wl_down = 1;
++#endif /* DISABLE_11N */
++#endif /* PROP_TXSTATUS */
++#endif /* BCMSDIO || BCMDBUS */
++#ifndef PCIE_FULL_DONGLE
++	uint32 wl_ap_isolate;
++#endif /* PCIE_FULL_DONGLE */
++	uint32 frameburst = CUSTOM_FRAMEBURST_SET;
++	uint wnm_bsstrans_resp = 0;
++#ifdef SUPPORT_SET_CAC
++	uint32 cac = 1;
++#endif /* SUPPORT_SET_CAC */
++#ifdef DHD_ENABLE_LPC
++	uint32 lpc = 1;
++#endif /* DHD_ENABLE_LPC */
++	uint power_mode = PM_FAST;
++#if defined(BCMSDIO)
++	uint32 dongle_align = DHD_SDALIGN;
++	uint32 glom = CUSTOM_GLOM_SETTING;
++#endif /* defined(BCMSDIO) */
++#if defined(CUSTOMER_HW2) && defined(USE_WL_CREDALL)
++	uint32 credall = 1;
++#endif
++	uint bcn_timeout = CUSTOM_BCN_TIMEOUT;
++	uint scancache_enab = TRUE;
++#ifdef ENABLE_BCN_LI_BCN_WAKEUP
++	uint32 bcn_li_bcn = 1;
++#endif /* ENABLE_BCN_LI_BCN_WAKEUP */
++	uint retry_max = CUSTOM_ASSOC_RETRY_MAX;
++#if defined(ARP_OFFLOAD_SUPPORT)
++	int arpoe = 1;
++#endif
++	int scan_assoc_time = DHD_SCAN_ASSOC_ACTIVE_TIME;
++	int scan_unassoc_time = DHD_SCAN_UNASSOC_ACTIVE_TIME;
++	int scan_passive_time = DHD_SCAN_PASSIVE_TIME;
++	char buf[WLC_IOCTL_SMLEN];
++	char *ptr;
++	uint32 listen_interval = CUSTOM_LISTEN_INTERVAL; /* Default Listen Interval in Beacons */
++#if defined(DHD_8021X_DUMP) && defined(SHOW_LOGTRACE)
++	wl_el_tag_params_t *el_tag = NULL;
++#endif /* DHD_8021X_DUMP */
++#ifdef ROAM_ENABLE
++	uint roamvar = 0;
++	int roam_trigger[2] = {CUSTOM_ROAM_TRIGGER_SETTING, WLC_BAND_ALL};
++	int roam_scan_period[2] = {10, WLC_BAND_ALL};
++	int roam_delta[2] = {CUSTOM_ROAM_DELTA_SETTING, WLC_BAND_ALL};
++#ifdef FULL_ROAMING_SCAN_PERIOD_60_SEC
++	int roam_fullscan_period = 60;
++#else /* FULL_ROAMING_SCAN_PERIOD_60_SEC */
++	int roam_fullscan_period = 120;
++#endif /* FULL_ROAMING_SCAN_PERIOD_60_SEC */
++#ifdef DISABLE_BCNLOSS_ROAM
++	uint roam_bcnloss_off = 1;
++#endif /* DISABLE_BCNLOSS_ROAM */
++#else
++#ifdef DISABLE_BUILTIN_ROAM
++	uint roamvar = 1;
++#endif /* DISABLE_BUILTIN_ROAM */
++#endif /* ROAM_ENABLE */
++
++#if defined(SOFTAP)
++	uint dtim = 1;
++#endif
++#if (defined(AP) && !defined(WLP2P)) || (!defined(AP) && defined(WL_CFG80211))
++	struct ether_addr p2p_ea;
++#endif
++#ifdef SOFTAP_UAPSD_OFF
++	uint32 wme_apsd = 0;
++#endif /* SOFTAP_UAPSD_OFF */
++#if (defined(AP) || defined(WLP2P)) && !defined(SOFTAP_AND_GC)
++	uint32 apsta = 1; /* Enable APSTA mode */
++#elif defined(SOFTAP_AND_GC)
++	uint32 apsta = 0;
++	int ap_mode = 1;
++#endif /* (defined(AP) || defined(WLP2P)) && !defined(SOFTAP_AND_GC) */
++#ifdef GET_CUSTOM_MAC_ENABLE
++	struct ether_addr ea_addr;
++	char hw_ether[62];
++#endif /* GET_CUSTOM_MAC_ENABLE */
++
++#ifdef DISABLE_11N
++	uint32 nmode = 0;
++#endif /* DISABLE_11N */
++
++#ifdef USE_WL_TXBF
++	uint32 txbf = 1;
++#endif /* USE_WL_TXBF */
++#ifdef DISABLE_TXBFR
++	uint32 txbf_bfr_cap = 0;
++#endif /* DISABLE_TXBFR */
++#if defined(PROP_TXSTATUS)
++#ifdef USE_WFA_CERT_CONF
++	uint32 proptx = 0;
++#endif /* USE_WFA_CERT_CONF */
++#endif /* PROP_TXSTATUS */
++#if defined(SUPPORT_5G_1024QAM_VHT)
++	uint32 vht_features = 0; /* init to 0, will be set based on each support */
++#endif 
++#ifdef DISABLE_11N_PROPRIETARY_RATES
++	uint32 ht_features = 0;
++#endif /* DISABLE_11N_PROPRIETARY_RATES */
++#ifdef CUSTOM_PSPRETEND_THR
++	uint32 pspretend_thr = CUSTOM_PSPRETEND_THR;
++#endif
++#ifdef CUSTOM_EVENT_PM_WAKE
++	uint32 pm_awake_thresh = CUSTOM_EVENT_PM_WAKE;
++#endif	/* CUSTOM_EVENT_PM_WAKE */
++	uint32 rsdb_mode = 0;
++#ifdef ENABLE_TEMP_THROTTLING
++	wl_temp_control_t temp_control;
++#endif /* ENABLE_TEMP_THROTTLING */
++#ifdef DISABLE_PRUNED_SCAN
++	uint32 scan_features = 0;
++#endif /* DISABLE_PRUNED_SCAN */
++#ifdef PKT_FILTER_SUPPORT
++	dhd_pkt_filter_enable = TRUE;
++#ifdef APF
++	dhd->apf_set = FALSE;
++#endif /* APF */
++#endif /* PKT_FILTER_SUPPORT */
++#ifdef WLTDLS
++	dhd->tdls_enable = FALSE;
++	dhd_tdls_set_mode(dhd, false);
++#endif /* WLTDLS */
++	dhd->suspend_bcn_li_dtim = CUSTOM_SUSPEND_BCN_LI_DTIM;
++#ifdef ENABLE_MAX_DTIM_IN_SUSPEND
++	dhd->max_dtim_enable = TRUE;
++#else
++	dhd->max_dtim_enable = FALSE;
++#endif /* ENABLE_MAX_DTIM_IN_SUSPEND */
++#ifdef CUSTOM_SET_OCLOFF
++	dhd->ocl_off = FALSE;
++#endif /* CUSTOM_SET_OCLOFF */
++	DHD_TRACE(("Enter %s\n", __FUNCTION__));
++
++#ifdef DHDTCPACK_SUPPRESS
++	dhd_tcpack_suppress_set(dhd, dhd->conf->tcpack_sup_mode);
++#endif
++	dhd->op_mode = 0;
++
++#if defined(CUSTOM_COUNTRY_CODE) && defined(CUSTOMER_HW2)
++	/* clear AP flags */
++	dhd->dhd_cflags &= ~WLAN_PLAT_AP_FLAG;
++#endif /* CUSTOM_COUNTRY_CODE && CUSTOMER_HW2 */
++
++#ifdef CUSTOMER_HW4_DEBUG
++	if (!dhd_validate_chipid(dhd)) {
++		DHD_ERROR(("%s: CONFIG_BCMXXX and CHIP ID(%x) is mismatched\n",
++			__FUNCTION__, dhd_bus_chip_id(dhd)));
++#ifndef SUPPORT_MULTIPLE_CHIPS
++		ret = BCME_BADARG;
++		goto done;
++#endif /* !SUPPORT_MULTIPLE_CHIPS */
++	}
++#endif /* CUSTOMER_HW4_DEBUG */
++	if ((!op_mode && dhd_get_fw_mode(dhd->info) == DHD_FLAG_MFG_MODE) ||
++		(op_mode == DHD_FLAG_MFG_MODE)) {
++		dhd->op_mode = DHD_FLAG_MFG_MODE;
++#ifdef DHD_PCIE_RUNTIMEPM
++		/* Disable RuntimePM in mfg mode */
++		DHD_DISABLE_RUNTIME_PM(dhd);
++		DHD_ERROR(("%s : Disable RuntimePM in Manufactring Firmware\n", __FUNCTION__));
++#endif /* DHD_PCIE_RUNTIME_PM */
++		/* Check and adjust IOCTL response timeout for Manufactring firmware */
++		dhd_os_set_ioctl_resp_timeout(MFG_IOCTL_RESP_TIMEOUT);
++		DHD_ERROR(("%s : Set IOCTL response time for Manufactring Firmware\n",
++			__FUNCTION__));
++	} else {
++		dhd_os_set_ioctl_resp_timeout(IOCTL_RESP_TIMEOUT);
++		DHD_INFO(("%s : Set IOCTL response time.\n", __FUNCTION__));
++	}
++#ifdef GET_CUSTOM_MAC_ENABLE
++	memset(hw_ether, 0, sizeof(hw_ether));
++	ret = wifi_platform_get_mac_addr(dhd->info->adapter, hw_ether);
++#ifdef GET_CUSTOM_MAC_FROM_CONFIG
++	if (!memcmp(&ether_null, &dhd->conf->hw_ether, ETHER_ADDR_LEN)) {
++		ret = 0;
++	} else
++#endif
++	if (!ret) {
++		memset(buf, 0, sizeof(buf));
++#ifdef GET_CUSTOM_MAC_FROM_CONFIG
++		memcpy(hw_ether, &dhd->conf->hw_ether, sizeof(dhd->conf->hw_ether));
++#endif
++		bcopy(hw_ether, ea_addr.octet, sizeof(struct ether_addr));
++		bcm_mkiovar("cur_etheraddr", (void *)&ea_addr, ETHER_ADDR_LEN, buf, sizeof(buf));
++		ret = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, buf, sizeof(buf), TRUE, 0);
++		if (ret < 0) {
++			memset(buf, 0, sizeof(buf));
++			bcm_mkiovar("hw_ether", hw_ether, sizeof(hw_ether), buf, sizeof(buf));
++			ret = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, buf, sizeof(buf), TRUE, 0);
++			if (ret) {
++				DHD_ERROR(("%s: can't set MAC address MAC="MACDBG", error=%d\n",
++					__FUNCTION__, MAC2STRDBG(hw_ether), ret));
++				prhex("MACPAD", &hw_ether[ETHER_ADDR_LEN], sizeof(hw_ether)-ETHER_ADDR_LEN);
++				ret = BCME_NOTUP;
++				goto done;
++			}
++		}
++	} else {
++		DHD_ERROR(("%s: can't get custom MAC address, ret=%d\n", __FUNCTION__, ret));
++		ret = BCME_NOTUP;
++		goto done;
++	}
++#endif /* GET_CUSTOM_MAC_ENABLE */
++	/* Get the default device MAC address directly from firmware */
++	memset(buf, 0, sizeof(buf));
++	bcm_mkiovar("cur_etheraddr", 0, 0, buf, sizeof(buf));
++	if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_GET_VAR, buf, sizeof(buf),
++		FALSE, 0)) < 0) {
++		DHD_ERROR(("%s: can't get MAC address , error=%d\n", __FUNCTION__, ret));
++		ret = BCME_NOTUP;
++		goto done;
++	}
++	/* Update public MAC address after reading from Firmware */
++	memcpy(dhd->mac.octet, buf, ETHER_ADDR_LEN);
++
++	if ((ret = dhd_apply_default_clm(dhd, dhd->clm_path)) < 0) {
++		DHD_ERROR(("%s: CLM set failed. Abort initialization.\n", __FUNCTION__));
++		goto done;
++	}
++
++	/* get a capabilities from firmware */
++	{
++		uint32 cap_buf_size = sizeof(dhd->fw_capabilities);
++		memset(dhd->fw_capabilities, 0, cap_buf_size);
++		ret = dhd_iovar(dhd, 0, "cap", NULL, 0, dhd->fw_capabilities, (cap_buf_size - 1),
++				FALSE);
++		if (ret < 0) {
++			DHD_ERROR(("%s: Get Capability failed (error=%d)\n",
++				__FUNCTION__, ret));
++			return 0;
++		}
++
++		memmove(&dhd->fw_capabilities[1], dhd->fw_capabilities, (cap_buf_size - 1));
++		dhd->fw_capabilities[0] = ' ';
++		dhd->fw_capabilities[cap_buf_size - 2] = ' ';
++		dhd->fw_capabilities[cap_buf_size - 1] = '\0';
++	}
++
++	if ((!op_mode && dhd_get_fw_mode(dhd->info) == DHD_FLAG_HOSTAP_MODE) ||
++		(op_mode == DHD_FLAG_HOSTAP_MODE)) {
++#ifdef SET_RANDOM_MAC_SOFTAP
++		uint rand_mac;
++#endif /* SET_RANDOM_MAC_SOFTAP */
++		dhd->op_mode = DHD_FLAG_HOSTAP_MODE;
++#if defined(ARP_OFFLOAD_SUPPORT)
++			arpoe = 0;
++#endif
++#ifdef PKT_FILTER_SUPPORT
++		if (dhd_conf_get_insuspend(dhd, AP_FILTER_IN_SUSPEND))
++			dhd_pkt_filter_enable = TRUE;
++		else
++			dhd_pkt_filter_enable = FALSE;
++#endif
++#ifdef SET_RANDOM_MAC_SOFTAP
++		SRANDOM32((uint)jiffies);
++		rand_mac = RANDOM32();
++		iovbuf[0] = (unsigned char)(vendor_oui >> 16) | 0x02;	/* local admin bit */
++		iovbuf[1] = (unsigned char)(vendor_oui >> 8);
++		iovbuf[2] = (unsigned char)vendor_oui;
++		iovbuf[3] = (unsigned char)(rand_mac & 0x0F) | 0xF0;
++		iovbuf[4] = (unsigned char)(rand_mac >> 8);
++		iovbuf[5] = (unsigned char)(rand_mac >> 16);
++
++		ret = dhd_iovar(dhd, 0, "cur_etheraddr", (char *)&iovbuf, ETHER_ADDR_LEN, NULL, 0,
++				TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s: can't set MAC address , error=%d\n", __FUNCTION__, ret));
++		} else
++			memcpy(dhd->mac.octet, iovbuf, ETHER_ADDR_LEN);
++#endif /* SET_RANDOM_MAC_SOFTAP */
++#ifdef USE_DYNAMIC_F2_BLKSIZE
++		dhdsdio_func_blocksize(dhd, 2, DYNAMIC_F2_BLKSIZE_FOR_NONLEGACY);
++#endif /* USE_DYNAMIC_F2_BLKSIZE */
++#ifdef SUPPORT_AP_POWERSAVE
++		dhd_set_ap_powersave(dhd, 0, TRUE);
++#endif /* SUPPORT_AP_POWERSAVE */
++#ifdef SOFTAP_UAPSD_OFF
++		ret = dhd_iovar(dhd, 0, "wme_apsd", (char *)&wme_apsd, sizeof(wme_apsd), NULL, 0,
++				TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s: set wme_apsd 0 fail (error=%d)\n",
++				__FUNCTION__, ret));
++		}
++#endif /* SOFTAP_UAPSD_OFF */
++#if defined(CUSTOM_COUNTRY_CODE) && defined(CUSTOMER_HW2)
++		/* set AP flag for specific country code of SOFTAP */
++		dhd->dhd_cflags |= WLAN_PLAT_AP_FLAG | WLAN_PLAT_NODFS_FLAG;
++#endif /* CUSTOM_COUNTRY_CODE && CUSTOMER_HW2 */
++	} else if ((!op_mode && dhd_get_fw_mode(dhd->info) == DHD_FLAG_MFG_MODE) ||
++		(op_mode == DHD_FLAG_MFG_MODE)) {
++#if defined(ARP_OFFLOAD_SUPPORT)
++		arpoe = 0;
++#endif /* ARP_OFFLOAD_SUPPORT */
++#ifdef PKT_FILTER_SUPPORT
++		dhd_pkt_filter_enable = FALSE;
++#endif /* PKT_FILTER_SUPPORT */
++		dhd->op_mode = DHD_FLAG_MFG_MODE;
++#ifdef USE_DYNAMIC_F2_BLKSIZE
++		dhdsdio_func_blocksize(dhd, 2, DYNAMIC_F2_BLKSIZE_FOR_NONLEGACY);
++#endif /* USE_DYNAMIC_F2_BLKSIZE */
++		if (FW_SUPPORTED(dhd, rsdb)) {
++			rsdb_mode = 0;
++			ret = dhd_iovar(dhd, 0, "rsdb_mode", (char *)&rsdb_mode, sizeof(rsdb_mode),
++					NULL, 0, TRUE);
++			if (ret < 0) {
++				DHD_ERROR(("%s Disable rsdb_mode is failed ret= %d\n",
++					__FUNCTION__, ret));
++			}
++		}
++	} else {
++		uint32 concurrent_mode = 0;
++		if ((!op_mode && dhd_get_fw_mode(dhd->info) == DHD_FLAG_P2P_MODE) ||
++			(op_mode == DHD_FLAG_P2P_MODE)) {
++#if defined(ARP_OFFLOAD_SUPPORT)
++			arpoe = 0;
++#endif
++#ifdef PKT_FILTER_SUPPORT
++			dhd_pkt_filter_enable = FALSE;
++#endif
++			dhd->op_mode = DHD_FLAG_P2P_MODE;
++		} else if ((!op_mode && dhd_get_fw_mode(dhd->info) == DHD_FLAG_IBSS_MODE) ||
++			(op_mode == DHD_FLAG_IBSS_MODE)) {
++			dhd->op_mode = DHD_FLAG_IBSS_MODE;
++		} else
++			dhd->op_mode = DHD_FLAG_STA_MODE;
++#if !defined(AP) && defined(WLP2P)
++		if (dhd->op_mode != DHD_FLAG_IBSS_MODE &&
++			(concurrent_mode = dhd_get_concurrent_capabilites(dhd))) {
++#if defined(ARP_OFFLOAD_SUPPORT)
++			arpoe = 1;
++#endif
++			dhd->op_mode |= concurrent_mode;
++		}
++
++		/* Check if we are enabling p2p */
++		if (dhd->op_mode & DHD_FLAG_P2P_MODE) {
++			ret = dhd_iovar(dhd, 0, "apsta", (char *)&apsta, sizeof(apsta), NULL, 0,
++					TRUE);
++			if (ret < 0)
++				DHD_ERROR(("%s APSTA for P2P failed ret= %d\n", __FUNCTION__, ret));
++
++#if defined(SOFTAP_AND_GC)
++		if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_SET_AP,
++			(char *)&ap_mode, sizeof(ap_mode), TRUE, 0)) < 0) {
++				DHD_ERROR(("%s WLC_SET_AP failed %d\n", __FUNCTION__, ret));
++		}
++#endif
++			memcpy(&p2p_ea, &dhd->mac, ETHER_ADDR_LEN);
++			ETHER_SET_LOCALADDR(&p2p_ea);
++			ret = dhd_iovar(dhd, 0, "p2p_da_override", (char *)&p2p_ea, sizeof(p2p_ea),
++					NULL, 0, TRUE);
++			if (ret < 0)
++				DHD_ERROR(("%s p2p_da_override ret= %d\n", __FUNCTION__, ret));
++			else
++				DHD_INFO(("dhd_preinit_ioctls: p2p_da_override succeeded\n"));
++		}
++#else
++	(void)concurrent_mode;
++#endif 
++	}
++
++#if defined(RSDB_MODE_FROM_FILE)
++	(void)dhd_rsdb_mode_from_file(dhd);
++#endif 
++
++#ifdef DISABLE_PRUNED_SCAN
++	if (FW_SUPPORTED(dhd, rsdb)) {
++		ret = dhd_iovar(dhd, 0, "scan_features", (char *)&scan_features,
++				sizeof(scan_features), iovbuf, sizeof(iovbuf), FALSE);
++		if (ret < 0) {
++			DHD_ERROR(("%s get scan_features is failed ret=%d\n",
++				__FUNCTION__, ret));
++		} else {
++			memcpy(&scan_features, iovbuf, 4);
++			scan_features &= ~RSDB_SCAN_DOWNGRADED_CH_PRUNE_ROAM;
++			ret = dhd_iovar(dhd, 0, "scan_features", (char *)&scan_features,
++					sizeof(scan_features), NULL, 0, TRUE);
++			if (ret < 0) {
++				DHD_ERROR(("%s set scan_features is failed ret=%d\n",
++					__FUNCTION__, ret));
++			}
++		}
++	}
++#endif /* DISABLE_PRUNED_SCAN */
++
++	DHD_ERROR(("Firmware up: op_mode=0x%04x, MAC="MACDBG"\n",
++		dhd->op_mode, MAC2STRDBG(dhd->mac.octet)));
++#ifdef CUSTOMER_HW2
++#if defined(DHD_BLOB_EXISTENCE_CHECK)
++	if (!dhd->pub.is_blob)
++#endif /* DHD_BLOB_EXISTENCE_CHECK */
++	{
++		/* get a ccode and revision for the country code */
++#if defined(CUSTOM_COUNTRY_CODE)
++		get_customized_country_code(dhd->info->adapter, dhd->dhd_cspec.country_abbrev,
++			&dhd->dhd_cspec, dhd->dhd_cflags);
++#else
++		get_customized_country_code(dhd->info->adapter, dhd->dhd_cspec.country_abbrev,
++			&dhd->dhd_cspec);
++#endif /* CUSTOM_COUNTRY_CODE */
++	}
++#endif /* CUSTOMER_HW2 */
++
++#if defined(RXFRAME_THREAD) && defined(RXTHREAD_ONLYSTA)
++	if (dhd->op_mode == DHD_FLAG_HOSTAP_MODE)
++		dhd->info->rxthread_enabled = FALSE;
++	else
++		dhd->info->rxthread_enabled = TRUE;
++#endif
++	/* Set Country code  */
++	if (dhd->dhd_cspec.ccode[0] != 0) {
++		ret = dhd_iovar(dhd, 0, "country", (char *)&dhd->dhd_cspec, sizeof(wl_country_t),
++				NULL, 0, TRUE);
++		if (ret < 0)
++			DHD_ERROR(("%s: country code setting failed\n", __FUNCTION__));
++	}
++
++
++	/* Set Listen Interval */
++	ret = dhd_iovar(dhd, 0, "assoc_listen", (char *)&listen_interval, sizeof(listen_interval),
++			NULL, 0, TRUE);
++	if (ret < 0)
++		DHD_ERROR(("%s assoc_listen failed %d\n", __FUNCTION__, ret));
++
++#if defined(ROAM_ENABLE) || defined(DISABLE_BUILTIN_ROAM)
++#ifdef USE_WFA_CERT_CONF
++	if (sec_get_param_wfa_cert(dhd, SET_PARAM_ROAMOFF, &roamvar) == BCME_OK) {
++		DHD_ERROR(("%s: read roam_off param =%d\n", __FUNCTION__, roamvar));
++	}
++#endif /* USE_WFA_CERT_CONF */
++	/* Disable built-in roaming to allowed ext supplicant to take care of roaming */
++	dhd_iovar(dhd, 0, "roam_off", (char *)&roamvar, sizeof(roamvar), NULL, 0, TRUE);
++#endif /* ROAM_ENABLE || DISABLE_BUILTIN_ROAM */
++#if defined(ROAM_ENABLE)
++#ifdef DISABLE_BCNLOSS_ROAM
++	dhd_iovar(dhd, 0, "roam_bcnloss_off", (char *)&roam_bcnloss_off, sizeof(roam_bcnloss_off),
++			NULL, 0, TRUE);
++#endif /* DISABLE_BCNLOSS_ROAM */
++	if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_SET_ROAM_TRIGGER, roam_trigger,
++		sizeof(roam_trigger), TRUE, 0)) < 0)
++		DHD_ERROR(("%s: roam trigger set failed %d\n", __FUNCTION__, ret));
++	if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_SET_ROAM_SCAN_PERIOD, roam_scan_period,
++		sizeof(roam_scan_period), TRUE, 0)) < 0)
++		DHD_ERROR(("%s: roam scan period set failed %d\n", __FUNCTION__, ret));
++	if ((dhd_wl_ioctl_cmd(dhd, WLC_SET_ROAM_DELTA, roam_delta,
++		sizeof(roam_delta), TRUE, 0)) < 0)
++		DHD_ERROR(("%s: roam delta set failed %d\n", __FUNCTION__, ret));
++	ret = dhd_iovar(dhd, 0, "fullroamperiod", (char *)&roam_fullscan_period,
++			sizeof(roam_fullscan_period), NULL, 0, TRUE);
++	if (ret < 0)
++		DHD_ERROR(("%s: roam fullscan period set failed %d\n", __FUNCTION__, ret));
++#endif /* ROAM_ENABLE */
++
++#ifdef CUSTOM_EVENT_PM_WAKE
++	ret = dhd_iovar(dhd, 0, "const_awake_thresh", (char *)&pm_awake_thresh,
++			sizeof(pm_awake_thresh), NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s set const_awake_thresh failed %d\n", __FUNCTION__, ret));
++	}
++#endif	/* CUSTOM_EVENT_PM_WAKE */
++#ifdef WLTDLS
++#ifdef ENABLE_TDLS_AUTO_MODE
++	/* by default TDLS on and auto mode on */
++	_dhd_tdls_enable(dhd, true, true, NULL);
++#else
++	/* by default TDLS on and auto mode off */
++	_dhd_tdls_enable(dhd, true, false, NULL);
++#endif /* ENABLE_TDLS_AUTO_MODE */
++#endif /* WLTDLS */
++
++#ifdef DHD_ENABLE_LPC
++	/* Set lpc 1 */
++	ret = dhd_iovar(dhd, 0, "lpc", (char *)&lpc, sizeof(lpc), NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s Set lpc failed  %d\n", __FUNCTION__, ret));
++
++		if (ret == BCME_NOTDOWN) {
++			uint wl_down = 1;
++			ret = dhd_wl_ioctl_cmd(dhd, WLC_DOWN,
++				(char *)&wl_down, sizeof(wl_down), TRUE, 0);
++			DHD_ERROR(("%s lpc fail WL_DOWN : %d, lpc = %d\n", __FUNCTION__, ret, lpc));
++
++			ret = dhd_iovar(dhd, 0, "lpc", (char *)&lpc, sizeof(lpc), NULL, 0, TRUE);
++			DHD_ERROR(("%s Set lpc ret --> %d\n", __FUNCTION__, ret));
++		}
++	}
++#endif /* DHD_ENABLE_LPC */
++
++#ifdef WLADPS
++#ifdef WLADPS_SEAK_AP_WAR
++	dhd->disabled_adps = FALSE;
++#endif /* WLADPS_SEAK_AP_WAR */
++	if (dhd->op_mode & DHD_FLAG_STA_MODE) {
++#ifdef ADPS_MODE_FROM_FILE
++		dhd_adps_mode_from_file(dhd);
++#else
++		if ((ret = dhd_enable_adps(dhd, ADPS_ENABLE)) != BCME_OK) {
++			DHD_ERROR(("%s dhd_enable_adps failed %d\n",
++					__FUNCTION__, ret));
++		}
++#endif /* ADPS_MODE_FROM_FILE */
++	}
++#endif /* WLADPS */
++
++	/* Set PowerSave mode */
++	(void) dhd_wl_ioctl_cmd(dhd, WLC_SET_PM, (char *)&power_mode, sizeof(power_mode), TRUE, 0);
++
++#if defined(BCMSDIO)
++	/* Match Host and Dongle rx alignment */
++	dhd_iovar(dhd, 0, "bus:txglomalign", (char *)&dongle_align, sizeof(dongle_align),
++			NULL, 0, TRUE);
++
++#if defined(CUSTOMER_HW2) && defined(USE_WL_CREDALL)
++	/* enable credall to reduce the chance of no bus credit happened. */
++	dhd_iovar(dhd, 0, "bus:credall", (char *)&credall, sizeof(credall), NULL, 0, TRUE);
++#endif
++
++#ifdef USE_WFA_CERT_CONF
++	if (sec_get_param_wfa_cert(dhd, SET_PARAM_BUS_TXGLOM_MODE, &glom) == BCME_OK) {
++		DHD_ERROR(("%s, read txglom param =%d\n", __FUNCTION__, glom));
++	}
++#endif /* USE_WFA_CERT_CONF */
++	if (glom != DEFAULT_GLOM_VALUE) {
++		DHD_INFO(("%s set glom=0x%X\n", __FUNCTION__, glom));
++		dhd_iovar(dhd, 0, "bus:txglom", (char *)&glom, sizeof(glom), NULL, 0, TRUE);
++	}
++#endif /* defined(BCMSDIO) */
++
++	/* Setup timeout if Beacons are lost and roam is off to report link down */
++	dhd_iovar(dhd, 0, "bcn_timeout", (char *)&bcn_timeout, sizeof(bcn_timeout), NULL, 0, TRUE);
++
++	/* Setup assoc_retry_max count to reconnect target AP in dongle */
++	dhd_iovar(dhd, 0, "assoc_retry_max", (char *)&retry_max, sizeof(retry_max), NULL, 0, TRUE);
++
++#if defined(AP) && !defined(WLP2P)
++	dhd_iovar(dhd, 0, "apsta", (char *)&apsta, sizeof(apsta), NULL, 0, TRUE);
++
++#endif /* defined(AP) && !defined(WLP2P) */
++
++#ifdef MIMO_ANT_SETTING
++	dhd_sel_ant_from_file(dhd);
++#endif /* MIMO_ANT_SETTING */
++
++#if defined(SOFTAP)
++	if (ap_fw_loaded == TRUE) {
++		dhd_wl_ioctl_cmd(dhd, WLC_SET_DTIMPRD, (char *)&dtim, sizeof(dtim), TRUE, 0);
++	}
++#endif 
++
++#if defined(KEEP_ALIVE)
++	{
++	/* Set Keep Alive : be sure to use FW with -keepalive */
++	int res;
++
++#if defined(SOFTAP)
++	if (ap_fw_loaded == FALSE)
++#endif 
++		if (!(dhd->op_mode &
++			(DHD_FLAG_HOSTAP_MODE | DHD_FLAG_MFG_MODE))) {
++			if ((res = dhd_keep_alive_onoff(dhd)) < 0)
++				DHD_ERROR(("%s set keeplive failed %d\n",
++				__FUNCTION__, res));
++		}
++	}
++#endif /* defined(KEEP_ALIVE) */
++
++#ifdef USE_WL_TXBF
++	ret = dhd_iovar(dhd, 0, "txbf", (char *)&txbf, sizeof(txbf), NULL, 0, TRUE);
++	if (ret < 0)
++		DHD_ERROR(("%s Set txbf failed  %d\n", __FUNCTION__, ret));
++
++#endif /* USE_WL_TXBF */
++
++	ret = dhd_iovar(dhd, 0, "scancache", (char *)&scancache_enab, sizeof(scancache_enab), NULL,
++			0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s Set scancache failed %d\n", __FUNCTION__, ret));
++	}
++
++#ifdef DISABLE_TXBFR
++	ret = dhd_iovar(dhd, 0, "txbf_bfr_cap", (char *)&txbf_bfr_cap, sizeof(txbf_bfr_cap), NULL,
++			0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s Clear txbf_bfr_cap failed  %d\n", __FUNCTION__, ret));
++	}
++#endif /* DISABLE_TXBFR */
++
++#ifdef USE_WFA_CERT_CONF
++#ifdef USE_WL_FRAMEBURST
++	 if (sec_get_param_wfa_cert(dhd, SET_PARAM_FRAMEBURST, &frameburst) == BCME_OK) {
++		DHD_ERROR(("%s, read frameburst param=%d\n", __FUNCTION__, frameburst));
++	 }
++#endif /* USE_WL_FRAMEBURST */
++#ifdef DISABLE_FRAMEBURST_VSDB
++	 g_frameburst = frameburst;
++#endif /* DISABLE_FRAMEBURST_VSDB */
++#endif /* USE_WFA_CERT_CONF */
++#ifdef DISABLE_WL_FRAMEBURST_SOFTAP
++	/* Disable Framebursting for SofAP */
++	if (dhd->op_mode & DHD_FLAG_HOSTAP_MODE) {
++		frameburst = 0;
++	}
++#endif /* DISABLE_WL_FRAMEBURST_SOFTAP */
++	/* Set frameburst to value */
++	if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_SET_FAKEFRAG, (char *)&frameburst,
++		sizeof(frameburst), TRUE, 0)) < 0) {
++		DHD_INFO(("%s frameburst not supported  %d\n", __FUNCTION__, ret));
++	}
++
++	iov_buf = (char*)kmalloc(WLC_IOCTL_SMLEN, GFP_KERNEL);
++	if (iov_buf == NULL) {
++		DHD_ERROR(("failed to allocate %d bytes for iov_buf\n", WLC_IOCTL_SMLEN));
++		ret = BCME_NOMEM;
++		goto done;
++	}
++
++
++#if defined(CUSTOM_AMPDU_BA_WSIZE)
++	/* Set ampdu ba wsize to 64 or 16 */
++#ifdef CUSTOM_AMPDU_BA_WSIZE
++	ampdu_ba_wsize = CUSTOM_AMPDU_BA_WSIZE;
++#endif
++	if (ampdu_ba_wsize != 0) {
++		ret = dhd_iovar(dhd, 0, "ampdu_ba_wsize", (char *)&ampdu_ba_wsize,
++				sizeof(ampdu_ba_wsize), NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s Set ampdu_ba_wsize to %d failed  %d\n",
++				__FUNCTION__, ampdu_ba_wsize, ret));
++		}
++	}
++#endif 
++
++#ifdef ENABLE_TEMP_THROTTLING
++	if (dhd->op_mode & DHD_FLAG_STA_MODE) {
++		memset(&temp_control, 0, sizeof(temp_control));
++		temp_control.enable = 1;
++		temp_control.control_bit = TEMP_THROTTLE_CONTROL_BIT;
++		ret = dhd_iovar(dhd, 0, "temp_throttle_control", (char *)&temp_control,
++				sizeof(temp_control), NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s Set temp_throttle_control to %d failed \n",
++				__FUNCTION__, ret));
++		}
++	}
++#endif /* ENABLE_TEMP_THROTTLING */
++
++#if defined(CUSTOM_AMPDU_MPDU)
++	ampdu_mpdu = CUSTOM_AMPDU_MPDU;
++	if (ampdu_mpdu != 0 && (ampdu_mpdu <= ampdu_ba_wsize)) {
++		ret = dhd_iovar(dhd, 0, "ampdu_mpdu", (char *)&ampdu_mpdu, sizeof(ampdu_mpdu),
++				NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s Set ampdu_mpdu to %d failed  %d\n",
++				__FUNCTION__, CUSTOM_AMPDU_MPDU, ret));
++		}
++	}
++#endif /* CUSTOM_AMPDU_MPDU */
++
++#if defined(CUSTOM_AMPDU_RELEASE)
++	ampdu_release = CUSTOM_AMPDU_RELEASE;
++	if (ampdu_release != 0 && (ampdu_release <= ampdu_ba_wsize)) {
++		ret = dhd_iovar(dhd, 0, "ampdu_release", (char *)&ampdu_release,
++				sizeof(ampdu_release), NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s Set ampdu_release to %d failed  %d\n",
++				__FUNCTION__, CUSTOM_AMPDU_RELEASE, ret));
++		}
++	}
++#endif /* CUSTOM_AMPDU_RELEASE */
++
++#if defined(CUSTOM_AMSDU_AGGSF)
++	amsdu_aggsf = CUSTOM_AMSDU_AGGSF;
++	if (amsdu_aggsf != 0) {
++		ret = dhd_iovar(dhd, 0, "amsdu_aggsf", (char *)&amsdu_aggsf, sizeof(amsdu_aggsf),
++				NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s Set amsdu_aggsf to %d failed %d\n",
++				__FUNCTION__, CUSTOM_AMSDU_AGGSF, ret));
++		}
++	}
++#endif /* CUSTOM_AMSDU_AGGSF */
++
++#if defined(SUPPORT_5G_1024QAM_VHT)
++#ifdef SUPPORT_5G_1024QAM_VHT
++	if (dhd_get_chipid(dhd) == BCM4361_CHIP_ID) {
++		vht_features |= 0x6; /* 5G 1024 QAM support */
++	}
++#endif /* SUPPORT_5G_1024QAM_VHT */
++	if (vht_features) {
++		ret = dhd_iovar(dhd, 0, "vht_features", (char *)&vht_features, sizeof(vht_features),
++				NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s vht_features set failed %d\n", __FUNCTION__, ret));
++
++			if (ret == BCME_NOTDOWN) {
++				uint wl_down = 1;
++				ret = dhd_wl_ioctl_cmd(dhd, WLC_DOWN,
++					(char *)&wl_down, sizeof(wl_down), TRUE, 0);
++				DHD_ERROR(("%s vht_features fail WL_DOWN : %d,"
++					" vht_features = 0x%x\n",
++					__FUNCTION__, ret, vht_features));
++
++				ret = dhd_iovar(dhd, 0, "vht_features", (char *)&vht_features,
++					sizeof(vht_features), NULL, 0, TRUE);
++				DHD_ERROR(("%s vht_features set. ret --> %d\n", __FUNCTION__, ret));
++			}
++		}
++	}
++#endif 
++#ifdef DISABLE_11N_PROPRIETARY_RATES
++	ret = dhd_iovar(dhd, 0, "ht_features", (char *)&ht_features, sizeof(ht_features), NULL, 0,
++			TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s ht_features set failed %d\n", __FUNCTION__, ret));
++	}
++#endif /* DISABLE_11N_PROPRIETARY_RATES */
++#ifdef CUSTOM_PSPRETEND_THR
++	/* Turn off MPC in AP mode */
++	ret = dhd_iovar(dhd, 0, "pspretend_threshold", (char *)&pspretend_thr,
++			sizeof(pspretend_thr), NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s pspretend_threshold for HostAPD failed  %d\n",
++			__FUNCTION__, ret));
++	}
++#endif
++
++	ret = dhd_iovar(dhd, 0, "buf_key_b4_m4", (char *)&buf_key_b4_m4, sizeof(buf_key_b4_m4),
++			NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s buf_key_b4_m4 set failed %d\n", __FUNCTION__, ret));
++	}
++#ifdef SUPPORT_SET_CAC
++	bcm_mkiovar("cac", (char *)&cac, sizeof(cac), iovbuf, sizeof(iovbuf));
++	if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, iovbuf, sizeof(iovbuf), TRUE, 0)) < 0) {
++		DHD_ERROR(("%s Failed to set cac to %d, %d\n", __FUNCTION__, cac, ret));
++	}
++#endif /* SUPPORT_SET_CAC */
++#ifdef DHD_ULP
++	/* Get the required details from dongle during preinit ioctl */
++	dhd_ulp_preinit(dhd);
++#endif /* DHD_ULP */
++
++	/* Read event_msgs mask */
++	ret = dhd_iovar(dhd, 0, "event_msgs", eventmask, WL_EVENTING_MASK_LEN, iovbuf,
++			sizeof(iovbuf), FALSE);
++	if (ret < 0) {
++		DHD_ERROR(("%s read Event mask failed %d\n", __FUNCTION__, ret));
++		goto done;
++	}
++	bcopy(iovbuf, eventmask, WL_EVENTING_MASK_LEN);
++
++	/* Setup event_msgs */
++	setbit(eventmask, WLC_E_SET_SSID);
++	setbit(eventmask, WLC_E_PRUNE);
++	setbit(eventmask, WLC_E_AUTH);
++	setbit(eventmask, WLC_E_AUTH_IND);
++	setbit(eventmask, WLC_E_ASSOC);
++	setbit(eventmask, WLC_E_REASSOC);
++	setbit(eventmask, WLC_E_REASSOC_IND);
++	if (!(dhd->op_mode & DHD_FLAG_IBSS_MODE))
++		setbit(eventmask, WLC_E_DEAUTH);
++	setbit(eventmask, WLC_E_DEAUTH_IND);
++	setbit(eventmask, WLC_E_DISASSOC_IND);
++	setbit(eventmask, WLC_E_DISASSOC);
++	setbit(eventmask, WLC_E_JOIN);
++	setbit(eventmask, WLC_E_BSSID);
++	setbit(eventmask, WLC_E_START);
++	setbit(eventmask, WLC_E_ASSOC_IND);
++	setbit(eventmask, WLC_E_PSK_SUP);
++	setbit(eventmask, WLC_E_LINK);
++	setbit(eventmask, WLC_E_MIC_ERROR);
++	setbit(eventmask, WLC_E_ASSOC_REQ_IE);
++	setbit(eventmask, WLC_E_ASSOC_RESP_IE);
++#ifdef LIMIT_BORROW
++	setbit(eventmask, WLC_E_ALLOW_CREDIT_BORROW);
++#endif
++#ifndef WL_CFG80211
++	setbit(eventmask, WLC_E_PMKID_CACHE);
++//	setbit(eventmask, WLC_E_TXFAIL); // terence 20181106: remove unnecessary event
++#endif
++	setbit(eventmask, WLC_E_JOIN_START);
++//	setbit(eventmask, WLC_E_SCAN_COMPLETE); // terence 20150628: remove redundant event
++#ifdef DHD_DEBUG
++	setbit(eventmask, WLC_E_SCAN_CONFIRM_IND);
++#endif
++#ifdef WLMEDIA_HTSF
++	setbit(eventmask, WLC_E_HTSFSYNC);
++#endif /* WLMEDIA_HTSF */
++#ifdef PNO_SUPPORT
++	setbit(eventmask, WLC_E_PFN_NET_FOUND);
++	setbit(eventmask, WLC_E_PFN_BEST_BATCHING);
++	setbit(eventmask, WLC_E_PFN_BSSID_NET_FOUND);
++	setbit(eventmask, WLC_E_PFN_BSSID_NET_LOST);
++#endif /* PNO_SUPPORT */
++	/* enable dongle roaming event */
++	setbit(eventmask, WLC_E_ROAM);
++#ifdef WLTDLS
++	setbit(eventmask, WLC_E_TDLS_PEER_EVENT);
++#endif /* WLTDLS */
++#ifdef WL_ESCAN
++	setbit(eventmask, WLC_E_ESCAN_RESULT);
++#endif /* WL_ESCAN */
++#ifdef RTT_SUPPORT
++	setbit(eventmask, WLC_E_PROXD);
++#endif /* RTT_SUPPORT */
++#ifdef WL_CFG80211
++	setbit(eventmask, WLC_E_ESCAN_RESULT);
++	setbit(eventmask, WLC_E_AP_STARTED);
++	setbit(eventmask, WLC_E_ACTION_FRAME_RX);
++	if (dhd->op_mode & DHD_FLAG_P2P_MODE) {
++		setbit(eventmask, WLC_E_P2P_DISC_LISTEN_COMPLETE);
++	}
++#endif /* WL_CFG80211 */
++
++#if defined(SHOW_LOGTRACE) && defined(LOGTRACE_FROM_FILE)
++	if (dhd_logtrace_from_file(dhd)) {
++		setbit(eventmask, WLC_E_TRACE);
++	} else {
++		clrbit(eventmask, WLC_E_TRACE);
++	}
++#elif defined(SHOW_LOGTRACE)
++	setbit(eventmask, WLC_E_TRACE);
++#else
++	clrbit(eventmask, WLC_E_TRACE);
++#endif /* defined(SHOW_LOGTRACE) && defined(LOGTRACE_FROM_FILE) */
++
++	setbit(eventmask, WLC_E_CSA_COMPLETE_IND);
++#ifdef DHD_WMF
++	setbit(eventmask, WLC_E_PSTA_PRIMARY_INTF_IND);
++#endif
++#ifdef CUSTOM_EVENT_PM_WAKE
++	setbit(eventmask, WLC_E_EXCESS_PM_WAKE_EVENT);
++#endif	/* CUSTOM_EVENT_PM_WAKE */
++#ifdef DHD_LOSSLESS_ROAMING
++	setbit(eventmask, WLC_E_ROAM_PREP);
++#endif
++#if defined(PCIE_FULL_DONGLE) && defined(DHD_LOSSLESS_ROAMING)
++	dhd_update_flow_prio_map(dhd, DHD_FLOW_PRIO_LLR_MAP);
++#endif /* defined(PCIE_FULL_DONGLE) && defined(DHD_LOSSLESS_ROAMING) */
++
++#if defined(BCMPCIE) && defined(EAPOL_PKT_PRIO)
++	dhd_update_flow_prio_map(dhd, DHD_FLOW_PRIO_LLR_MAP);
++#endif /* defined(BCMPCIE) && defined(EAPOL_PKT_PRIO) */
++
++	/* Write updated Event mask */
++	ret = dhd_iovar(dhd, 0, "event_msgs", eventmask, WL_EVENTING_MASK_LEN, NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s Set Event mask failed %d\n", __FUNCTION__, ret));
++		goto done;
++	}
++
++	/* make up event mask ext message iovar for event larger than 128 */
++	msglen = ROUNDUP(WLC_E_LAST, NBBY)/NBBY + EVENTMSGS_EXT_STRUCT_SIZE;
++	eventmask_msg = (eventmsgs_ext_t*)kmalloc(msglen, GFP_KERNEL);
++	if (eventmask_msg == NULL) {
++		DHD_ERROR(("failed to allocate %d bytes for event_msg_ext\n", msglen));
++		ret = BCME_NOMEM;
++		goto done;
++	}
++	bzero(eventmask_msg, msglen);
++	eventmask_msg->ver = EVENTMSGS_VER;
++	eventmask_msg->len = ROUNDUP(WLC_E_LAST, NBBY)/NBBY;
++
++	/* Read event_msgs_ext mask */
++	ret2 = dhd_iovar(dhd, 0, "event_msgs_ext", (char *)eventmask_msg, msglen, iov_buf,
++			WLC_IOCTL_SMLEN, FALSE);
++
++	if (ret2 == 0) { /* event_msgs_ext must be supported */
++		bcopy(iov_buf, eventmask_msg, msglen);
++#ifdef RSSI_MONITOR_SUPPORT
++		setbit(eventmask_msg->mask, WLC_E_RSSI_LQM);
++#endif /* RSSI_MONITOR_SUPPORT */
++#ifdef GSCAN_SUPPORT
++		setbit(eventmask_msg->mask, WLC_E_PFN_GSCAN_FULL_RESULT);
++		setbit(eventmask_msg->mask, WLC_E_PFN_SCAN_COMPLETE);
++		setbit(eventmask_msg->mask, WLC_E_PFN_SSID_EXT);
++		setbit(eventmask_msg->mask, WLC_E_ROAM_EXP_EVENT);
++#endif /* GSCAN_SUPPORT */
++		setbit(eventmask_msg->mask, WLC_E_RSSI_LQM);
++#ifdef BT_WIFI_HANDOVER
++		setbit(eventmask_msg->mask, WLC_E_BT_WIFI_HANDOVER_REQ);
++#endif /* BT_WIFI_HANDOVER */
++#ifdef DBG_PKT_MON
++		setbit(eventmask_msg->mask, WLC_E_ROAM_PREP);
++#endif /* DBG_PKT_MON */
++#ifdef DHD_ULP
++		setbit(eventmask_msg->mask, WLC_E_ULP);
++#endif
++#ifdef ENABLE_TEMP_THROTTLING
++		setbit(eventmask_msg->mask, WLC_E_TEMP_THROTTLE);
++#endif /* ENABLE_TEMP_THROTTLING */
++
++		/* Write updated Event mask */
++		eventmask_msg->ver = EVENTMSGS_VER;
++		eventmask_msg->command = EVENTMSGS_SET_MASK;
++		eventmask_msg->len = ROUNDUP(WLC_E_LAST, NBBY)/NBBY;
++		ret = dhd_iovar(dhd, 0, "event_msgs_ext", (char *)eventmask_msg, msglen, NULL, 0,
++				TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s write event mask ext failed %d\n", __FUNCTION__, ret));
++			goto done;
++		}
++	} else if (ret2 == BCME_UNSUPPORTED || ret2 == BCME_VERSION) {
++		/* Skip for BCME_UNSUPPORTED or BCME_VERSION */
++		DHD_ERROR(("%s event_msgs_ext not support or version mismatch %d\n",
++			__FUNCTION__, ret2));
++	} else {
++		DHD_ERROR(("%s read event mask ext failed %d\n", __FUNCTION__, ret2));
++		ret = ret2;
++		goto done;
++	}
++
++#if defined(DHD_8021X_DUMP) && defined(SHOW_LOGTRACE)
++	/* Enabling event log trace for EAP events */
++	el_tag = (wl_el_tag_params_t *)kmalloc(sizeof(wl_el_tag_params_t), GFP_KERNEL);
++	if (el_tag == NULL) {
++		DHD_ERROR(("failed to allocate %d bytes for event_msg_ext\n",
++				(int)sizeof(wl_el_tag_params_t)));
++		ret = BCME_NOMEM;
++		goto done;
++	}
++	el_tag->tag = EVENT_LOG_TAG_4WAYHANDSHAKE;
++	el_tag->set = 1;
++	el_tag->flags = EVENT_LOG_TAG_FLAG_LOG;
++	bcm_mkiovar("event_log_tag_control", (char *)el_tag,
++			sizeof(*el_tag), iovbuf, sizeof(iovbuf));
++	dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, iovbuf, sizeof(iovbuf), TRUE, 0);
++#endif /* DHD_8021X_DUMP */
++
++	dhd_wl_ioctl_cmd(dhd, WLC_SET_SCAN_CHANNEL_TIME, (char *)&scan_assoc_time,
++		sizeof(scan_assoc_time), TRUE, 0);
++	dhd_wl_ioctl_cmd(dhd, WLC_SET_SCAN_UNASSOC_TIME, (char *)&scan_unassoc_time,
++		sizeof(scan_unassoc_time), TRUE, 0);
++	dhd_wl_ioctl_cmd(dhd, WLC_SET_SCAN_PASSIVE_TIME, (char *)&scan_passive_time,
++		sizeof(scan_passive_time), TRUE, 0);
++
++#ifdef ARP_OFFLOAD_SUPPORT
++	/* Set and enable ARP offload feature for STA only  */
++#if defined(SOFTAP)
++	if (arpoe && !ap_fw_loaded)
++#else
++	if (arpoe)
++#endif
++	{
++		dhd_arp_offload_enable(dhd, TRUE);
++		dhd_arp_offload_set(dhd, dhd_arp_mode);
++	} else {
++		dhd_arp_offload_enable(dhd, FALSE);
++		dhd_arp_offload_set(dhd, 0);
++	}
++	dhd_arp_enable = arpoe;
++#endif /* ARP_OFFLOAD_SUPPORT */
++
++#ifdef PKT_FILTER_SUPPORT
++	/* Setup default defintions for pktfilter , enable in suspend */
++	if (dhd_master_mode) {
++		dhd->pktfilter_count = 6;
++		dhd->pktfilter[DHD_BROADCAST_FILTER_NUM] = NULL;
++		if (!FW_SUPPORTED(dhd, pf6)) {
++			dhd->pktfilter[DHD_MULTICAST4_FILTER_NUM] = NULL;
++			dhd->pktfilter[DHD_MULTICAST6_FILTER_NUM] = NULL;
++		} else {
++			/* Immediately pkt filter TYPE 6 Discard IPv4/IPv6 Multicast Packet */
++			dhd->pktfilter[DHD_MULTICAST4_FILTER_NUM] = DISCARD_IPV4_MCAST;
++			dhd->pktfilter[DHD_MULTICAST6_FILTER_NUM] = DISCARD_IPV6_MCAST;
++		}
++		/* apply APP pktfilter */
++		dhd->pktfilter[DHD_ARP_FILTER_NUM] = "105 0 0 12 0xFFFF 0x0806";
++
++		/* Setup filter to allow only unicast */
++		dhd->pktfilter[DHD_UNICAST_FILTER_NUM] = "100 0 0 0 0x01 0x00";
++
++		/* Add filter to pass multicastDNS packet and NOT filter out as Broadcast */
++		dhd->pktfilter[DHD_MDNS_FILTER_NUM] = NULL;
++
++		dhd->pktfilter[DHD_BROADCAST_ARP_FILTER_NUM] = NULL;
++		if (FW_SUPPORTED(dhd, pf6)) {
++			/* Immediately pkt filter TYPE 6 Dicard Broadcast IP packet */
++			dhd->pktfilter[DHD_IP4BCAST_DROP_FILTER_NUM] =
++				"107 1 6 IP4_H:16 0xf0 !0xe0 IP4_H:19 0xff 0xff";
++			dhd->pktfilter_count = 8;
++		}
++
++#ifdef GAN_LITE_NAT_KEEPALIVE_FILTER
++		dhd->pktfilter_count = 4;
++		/* Setup filter to block broadcast and NAT Keepalive packets */
++		/* discard all broadcast packets */
++		dhd->pktfilter[DHD_UNICAST_FILTER_NUM] = "100 0 0 0 0xffffff 0xffffff";
++		/* discard NAT Keepalive packets */
++		dhd->pktfilter[DHD_BROADCAST_FILTER_NUM] = "102 0 0 36 0xffffffff 0x11940009";
++		/* discard NAT Keepalive packets */
++		dhd->pktfilter[DHD_MULTICAST4_FILTER_NUM] = "104 0 0 38 0xffffffff 0x11940009";
++		dhd->pktfilter[DHD_MULTICAST6_FILTER_NUM] = NULL;
++#endif /* GAN_LITE_NAT_KEEPALIVE_FILTER */
++	} else
++		dhd_conf_discard_pkt_filter(dhd);
++	dhd_conf_add_pkt_filter(dhd);
++
++#if defined(SOFTAP)
++	if (ap_fw_loaded) {
++		dhd_enable_packet_filter(0, dhd);
++	}
++#endif /* defined(SOFTAP) */
++	dhd_set_packet_filter(dhd);
++#endif /* PKT_FILTER_SUPPORT */
++#ifdef DISABLE_11N
++	ret = dhd_iovar(dhd, 0, "nmode", (char *)&nmode, sizeof(nmode), NULL, 0, TRUE);
++	if (ret < 0)
++		DHD_ERROR(("%s wl nmode 0 failed %d\n", __FUNCTION__, ret));
++#endif /* DISABLE_11N */
++
++#ifdef ENABLE_BCN_LI_BCN_WAKEUP
++	dhd_iovar(dhd, 0, "bcn_li_bcn", (char *)&bcn_li_bcn, sizeof(bcn_li_bcn), NULL, 0, TRUE);
++#endif /* ENABLE_BCN_LI_BCN_WAKEUP */
++	/* query for 'clmver' to get clm version info from firmware */
++	memset(buf, 0, sizeof(buf));
++	ret = dhd_iovar(dhd, 0, "clmver", NULL, 0, buf, sizeof(buf), FALSE);
++	if (ret < 0)
++		DHD_ERROR(("%s clmver failed %d\n", __FUNCTION__, ret));
++	else {
++		char *ver_temp_buf = NULL, *ver_date_buf = NULL;
++		int len;
++
++		if ((ver_temp_buf = bcmstrstr(buf, "Data:")) == NULL) {
++			DHD_ERROR(("Couldn't find \"Data:\"\n"));
++		} else {
++			ver_date_buf = bcmstrstr(buf, "Creation:");
++			ptr = (ver_temp_buf + strlen("Data:"));
++			if ((ver_temp_buf = bcmstrtok(&ptr, "\n", 0)) == NULL) {
++				DHD_ERROR(("Couldn't find New line character\n"));
++			} else {
++				memset(clm_version, 0, CLM_VER_STR_LEN);
++				len = snprintf(clm_version, CLM_VER_STR_LEN - 1, "%s", ver_temp_buf);
++				if (ver_date_buf) {
++					ptr = (ver_date_buf + strlen("Creation:"));
++					ver_date_buf = bcmstrtok(&ptr, "\n", 0);
++					if (ver_date_buf)
++						snprintf(clm_version+len, CLM_VER_STR_LEN-1-len,
++							" (%s)", ver_date_buf);
++				}
++				DHD_INFO(("CLM version = %s\n", clm_version));
++			}
++		}
++	}
++
++	/* query for 'ver' to get version info from firmware */
++	memset(buf, 0, sizeof(buf));
++	ptr = buf;
++	ret = dhd_iovar(dhd, 0, "ver", NULL, 0, (char *)&buf, sizeof(buf), FALSE);
++	if (ret < 0)
++		DHD_ERROR(("%s failed %d\n", __FUNCTION__, ret));
++	else {
++		bcmstrtok(&ptr, "\n", 0);
++		strncpy(fw_version, buf, FW_VER_STR_LEN);
++		fw_version[FW_VER_STR_LEN-1] = '\0';
++		dhd_set_version_info(dhd, buf);
++#ifdef WRITE_WLANINFO
++		sec_save_wlinfo(buf, EPI_VERSION_STR, dhd->info->nv_path, clm_version);
++#endif /* WRITE_WLANINFO */
++	}
++#ifdef GEN_SOFTAP_INFO_FILE
++	sec_save_softap_info();
++#endif /* GEN_SOFTAP_INFO_FILE */
++
++#if defined(BCMSDIO)
++	dhd_txglom_enable(dhd, dhd->conf->bus_rxglom);
++#endif /* defined(BCMSDIO) */
++
++#if defined(BCMSDIO) || defined(BCMDBUS)
++#ifdef PROP_TXSTATUS
++	if (disable_proptx ||
++#ifdef PROP_TXSTATUS_VSDB
++		/* enable WLFC only if the firmware is VSDB when it is in STA mode */
++		(dhd->op_mode != DHD_FLAG_HOSTAP_MODE &&
++		 dhd->op_mode != DHD_FLAG_IBSS_MODE) ||
++#endif /* PROP_TXSTATUS_VSDB */
++		FALSE) {
++		wlfc_enable = FALSE;
++	}
++	ret = dhd_conf_get_disable_proptx(dhd);
++	if (ret == 0){
++		disable_proptx = 0;
++		wlfc_enable = TRUE;
++	} else if (ret >= 1) {
++		disable_proptx = 1;
++		wlfc_enable = FALSE;
++		/* terence 20161229: we should set ampdu_hostreorder=0 when disable_proptx=1 */
++		hostreorder = 0;
++	}
++
++#if defined(PROP_TXSTATUS)
++#ifdef USE_WFA_CERT_CONF
++	if (sec_get_param_wfa_cert(dhd, SET_PARAM_PROPTX, &proptx) == BCME_OK) {
++		DHD_ERROR(("%s , read proptx param=%d\n", __FUNCTION__, proptx));
++		wlfc_enable = proptx;
++	}
++#endif /* USE_WFA_CERT_CONF */
++#endif /* PROP_TXSTATUS */
++
++#ifndef DISABLE_11N
++	ret = dhd_wl_ioctl_cmd(dhd, WLC_DOWN, (char *)&wl_down, sizeof(wl_down), TRUE, 0);
++	ret2 = dhd_iovar(dhd, 0, "ampdu_hostreorder", (char *)&hostreorder, sizeof(hostreorder),
++			NULL, 0, TRUE);
++	if (ret2 < 0) {
++		DHD_ERROR(("%s wl ampdu_hostreorder failed %d\n", __FUNCTION__, ret2));
++		if (ret2 != BCME_UNSUPPORTED)
++			ret = ret2;
++
++		if (ret == BCME_NOTDOWN) {
++			uint wl_down = 1;
++			ret2 = dhd_wl_ioctl_cmd(dhd, WLC_DOWN, (char *)&wl_down,
++				sizeof(wl_down), TRUE, 0);
++			DHD_ERROR(("%s ampdu_hostreorder fail WL_DOWN : %d, hostreorder :%d\n",
++				__FUNCTION__, ret2, hostreorder));
++
++			ret2 = dhd_iovar(dhd, 0, "ampdu_hostreorder", (char *)&hostreorder,
++					sizeof(hostreorder), NULL, 0, TRUE);
++			DHD_ERROR(("%s wl ampdu_hostreorder. ret --> %d\n", __FUNCTION__, ret2));
++			if (ret2 != BCME_UNSUPPORTED)
++					ret = ret2;
++		}
++		if (ret2 != BCME_OK)
++			hostreorder = 0;
++	}
++#endif /* DISABLE_11N */
++
++
++	if (wlfc_enable) {
++		dhd_wlfc_init(dhd);
++		/* terence 20161229: enable ampdu_hostreorder if tlv enabled */
++		dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "ampdu_hostreorder", 1, 0, TRUE);
++	}
++#ifndef DISABLE_11N
++	else if (hostreorder)
++		dhd_wlfc_hostreorder_init(dhd);
++#endif /* DISABLE_11N */
++#else
++	/* terence 20161229: disable ampdu_hostreorder if PROP_TXSTATUS not defined */
++	printf("%s: not define PROP_TXSTATUS\n", __FUNCTION__);
++	dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "ampdu_hostreorder", 0, 0, TRUE);
++#endif /* PROP_TXSTATUS */
++#endif /* BCMSDIO || BCMDBUS */
++#ifndef PCIE_FULL_DONGLE
++	/* For FD we need all the packets at DHD to handle intra-BSS forwarding */
++	if (FW_SUPPORTED(dhd, ap)) {
++		wl_ap_isolate = AP_ISOLATE_SENDUP_ALL;
++		ret = dhd_iovar(dhd, 0, "ap_isolate", (char *)&wl_ap_isolate, sizeof(wl_ap_isolate),
++				NULL, 0, TRUE);
++		if (ret < 0)
++			DHD_ERROR(("%s failed %d\n", __FUNCTION__, ret));
++	}
++#endif /* PCIE_FULL_DONGLE */
++#ifdef PNO_SUPPORT
++	if (!dhd->pno_state) {
++		dhd_pno_init(dhd);
++	}
++#endif
++#ifdef RTT_SUPPORT
++	if (!dhd->rtt_state) {
++		ret = dhd_rtt_init(dhd);
++		if (ret < 0) {
++			DHD_ERROR(("%s failed to initialize RTT\n", __FUNCTION__));
++		}
++	}
++#endif
++#ifdef WL11U
++	dhd_interworking_enable(dhd);
++#endif /* WL11U */
++
++#ifdef SUPPORT_SENSORHUB
++	DHD_ERROR(("%s: SensorHub enabled %d\n",
++			__FUNCTION__, dhd->info->shub_enable));
++	ret2 = dhd_iovar(dhd, 0, "shub", NULL, 0,
++			(char *)&shub_ctl, sizeof(shub_ctl), FALSE);
++	if (ret2 < 0) {
++		DHD_ERROR(("%s failed to get shub hub enable information %d\n",
++			__FUNCTION__, ret2));
++		dhd->info->shub_enable = 0;
++	} else {
++		dhd->info->shub_enable = shub_ctl.enable;
++		DHD_ERROR(("%s: checking sensorhub enable %d\n",
++			__FUNCTION__, dhd->info->shub_enable));
++	}
++#else
++	DHD_ERROR(("%s: SensorHub diabled %d\n",
++			__FUNCTION__, dhd->info->shub_enable));
++	dhd->info->shub_enable = FALSE;
++	shub_ctl.enable = FALSE;
++	ret2 = dhd_iovar(dhd, 0, "shub", (char *)&shub_ctl, sizeof(shub_ctl),
++			NULL, 0, TRUE);
++	if (ret2 < 0) {
++		DHD_ERROR(("%s failed to set ShubHub disable\n",
++			__FUNCTION__));
++	}
++#endif /* SUPPORT_SENSORHUB */
++
++
++#ifdef NDO_CONFIG_SUPPORT
++	dhd->ndo_enable = FALSE;
++	dhd->ndo_host_ip_overflow = FALSE;
++	dhd->ndo_max_host_ip = NDO_MAX_HOST_IP_ENTRIES;
++#endif /* NDO_CONFIG_SUPPORT */
++
++	/* ND offload version supported */
++	dhd->ndo_version = dhd_ndo_get_version(dhd);
++	if (dhd->ndo_version > 0) {
++		DHD_INFO(("%s: ndo version %d\n", __FUNCTION__, dhd->ndo_version));
++
++#ifdef NDO_CONFIG_SUPPORT
++		/* enable Unsolicited NA filter */
++		ret = dhd_ndo_unsolicited_na_filter_enable(dhd, 1);
++		if (ret < 0) {
++			DHD_ERROR(("%s failed to enable Unsolicited NA filter\n", __FUNCTION__));
++		}
++#endif /* NDO_CONFIG_SUPPORT */
++	}
++
++	/* check dongle supports wbtext or not */
++	dhd->wbtext_support = FALSE;
++	if (dhd_wl_ioctl_get_intiovar(dhd, "wnm_bsstrans_resp", &wnm_bsstrans_resp,
++			WLC_GET_VAR, FALSE, 0) != BCME_OK) {
++		DHD_ERROR(("failed to get wnm_bsstrans_resp\n"));
++	}
++	if (wnm_bsstrans_resp == WL_BSSTRANS_POLICY_PRODUCT_WBTEXT) {
++		dhd->wbtext_support = TRUE;
++	}
++#ifndef WBTEXT
++	/* driver can turn off wbtext feature through makefile */
++	if (dhd->wbtext_support) {
++		if (dhd_wl_ioctl_set_intiovar(dhd, "wnm_bsstrans_resp",
++				WL_BSSTRANS_POLICY_ROAM_ALWAYS,
++				WLC_SET_VAR, FALSE, 0) != BCME_OK) {
++			DHD_ERROR(("failed to disable WBTEXT\n"));
++		}
++	}
++#endif /* !WBTEXT */
++
++	/* WNM capabilities */
++	wnm_cap = 0
++#ifdef WL11U
++		| WL_WNM_BSSTRANS | WL_WNM_NOTIF
++#endif
++#ifdef WBTEXT
++		| WL_WNM_BSSTRANS | WL_WNM_MAXIDLE
++#endif
++		;
++	if (dhd_iovar(dhd, 0, "wnm", (char *)&wnm_cap, sizeof(wnm_cap), NULL, 0, TRUE) < 0) {
++		DHD_ERROR(("failed to set WNM capabilities\n"));
++	}
++
++	dhd_conf_postinit_ioctls(dhd);
++done:
++
++	if (eventmask_msg)
++		kfree(eventmask_msg);
++	if (iov_buf)
++		kfree(iov_buf);
++#if defined(DHD_8021X_DUMP) && defined(SHOW_LOGTRACE)
++	if (el_tag)
++		kfree(el_tag);
++#endif /* DHD_8021X_DUMP */
++	return ret;
++}
++
++
++int
++dhd_iovar(dhd_pub_t *pub, int ifidx, char *name, char *param_buf, uint param_len, char *res_buf,
++		uint res_len, int set)
++{
++	char *buf = NULL;
++	int input_len;
++	wl_ioctl_t ioc;
++	int ret;
++
++	if (res_len > WLC_IOCTL_MAXLEN || param_len > WLC_IOCTL_MAXLEN)
++		return BCME_BADARG;
++
++	input_len = strlen(name) + 1 + param_len;
++	if (input_len > WLC_IOCTL_MAXLEN)
++		return BCME_BADARG;
++
++	buf = NULL;
++	if (set) {
++		if (res_buf || res_len != 0) {
++			DHD_ERROR(("%s: SET wrong arguemnet\n", __FUNCTION__));
++			ret = BCME_BADARG;
++			goto exit;
++		}
++		buf = kzalloc(input_len, GFP_KERNEL);
++		if (!buf) {
++			DHD_ERROR(("%s: mem alloc failed\n", __FUNCTION__));
++			ret = BCME_NOMEM;
++			goto exit;
++		}
++		ret = bcm_mkiovar(name, param_buf, param_len, buf, input_len);
++		if (!ret) {
++			ret = BCME_NOMEM;
++			goto exit;
++		}
++
++		ioc.cmd = WLC_SET_VAR;
++		ioc.buf = buf;
++		ioc.len = input_len;
++		ioc.set = set;
++
++		ret = dhd_wl_ioctl(pub, ifidx, &ioc, ioc.buf, ioc.len);
++	} else {
++		if (!res_buf || !res_len) {
++			DHD_ERROR(("%s: GET failed. resp_buf NULL or length 0.\n", __FUNCTION__));
++			ret = BCME_BADARG;
++			goto exit;
++		}
++
++		if (res_len < input_len) {
++			DHD_INFO(("%s: res_len(%d) < input_len(%d)\n", __FUNCTION__,
++					res_len, input_len));
++			buf = kzalloc(input_len, GFP_KERNEL);
++			if (!buf) {
++				DHD_ERROR(("%s: mem alloc failed\n", __FUNCTION__));
++				ret = BCME_NOMEM;
++				goto exit;
++			}
++			ret = bcm_mkiovar(name, param_buf, param_len, buf, input_len);
++			if (!ret) {
++				ret = BCME_NOMEM;
++				goto exit;
++			}
++
++			ioc.cmd = WLC_GET_VAR;
++			ioc.buf = buf;
++			ioc.len = input_len;
++			ioc.set = set;
++
++			ret = dhd_wl_ioctl(pub, ifidx, &ioc, ioc.buf, ioc.len);
++
++			if (ret == BCME_OK) {
++				memcpy(res_buf, buf, res_len);
++			}
++		} else {
++			memset(res_buf, 0, res_len);
++			ret = bcm_mkiovar(name, param_buf, param_len, res_buf, res_len);
++			if (!ret) {
++				ret = BCME_NOMEM;
++				goto exit;
++			}
++
++			ioc.cmd = WLC_GET_VAR;
++			ioc.buf = res_buf;
++			ioc.len = res_len;
++			ioc.set = set;
++
++			ret = dhd_wl_ioctl(pub, ifidx, &ioc, ioc.buf, ioc.len);
++		}
++	}
++exit:
++	kfree(buf);
++	return ret;
++}
++
++int
++dhd_getiovar(dhd_pub_t *pub, int ifidx, char *name, char *cmd_buf,
++	uint cmd_len, char **resptr, uint resp_len)
++{
++	int len = resp_len;
++	int ret;
++	char *buf = *resptr;
++	wl_ioctl_t ioc;
++	if (resp_len > WLC_IOCTL_MAXLEN)
++		return BCME_BADARG;
++
++	memset(buf, 0, resp_len);
++
++	ret = bcm_mkiovar(name, cmd_buf, cmd_len, buf, len);
++	if (ret == 0) {
++		return BCME_BUFTOOSHORT;
++	}
++
++	memset(&ioc, 0, sizeof(ioc));
++
++	ioc.cmd = WLC_GET_VAR;
++	ioc.buf = buf;
++	ioc.len = len;
++	ioc.set = 0;
++
++	ret = dhd_wl_ioctl(pub, ifidx, &ioc, ioc.buf, ioc.len);
++
++	return ret;
++}
++
++
++int dhd_change_mtu(dhd_pub_t *dhdp, int new_mtu, int ifidx)
++{
++	struct dhd_info *dhd = dhdp->info;
++	struct net_device *dev = NULL;
++
++	ASSERT(dhd && dhd->iflist[ifidx]);
++	dev = dhd->iflist[ifidx]->net;
++	ASSERT(dev);
++
++	if (netif_running(dev)) {
++		DHD_ERROR(("%s: Must be down to change its MTU\n", dev->name));
++		return BCME_NOTDOWN;
++	}
++
++#define DHD_MIN_MTU 1500
++#define DHD_MAX_MTU 1752
++
++	if ((new_mtu < DHD_MIN_MTU) || (new_mtu > DHD_MAX_MTU)) {
++		DHD_ERROR(("%s: MTU size %d is invalid.\n", __FUNCTION__, new_mtu));
++		return BCME_BADARG;
++	}
++
++	dev->mtu = new_mtu;
++	return 0;
++}
++
++#ifdef ARP_OFFLOAD_SUPPORT
++/* add or remove AOE host ip(s) (up to 8 IPs on the interface)  */
++void
++aoe_update_host_ipv4_table(dhd_pub_t *dhd_pub, u32 ipa, bool add, int idx)
++{
++	u32 ipv4_buf[MAX_IPV4_ENTRIES]; /* temp save for AOE host_ip table */
++	int i;
++	int ret;
++
++	bzero(ipv4_buf, sizeof(ipv4_buf));
++
++	/* display what we've got */
++	ret = dhd_arp_get_arp_hostip_table(dhd_pub, ipv4_buf, sizeof(ipv4_buf), idx);
++	DHD_ARPOE(("%s: hostip table read from Dongle:\n", __FUNCTION__));
++#ifdef AOE_DBG
++	dhd_print_buf(ipv4_buf, 32, 4); /* max 8 IPs 4b each */
++#endif
++	/* now we saved hoste_ip table, clr it in the dongle AOE */
++	dhd_aoe_hostip_clr(dhd_pub, idx);
++
++	if (ret) {
++		DHD_ERROR(("%s failed\n", __FUNCTION__));
++		return;
++	}
++
++	for (i = 0; i < MAX_IPV4_ENTRIES; i++) {
++		if (add && (ipv4_buf[i] == 0)) {
++				ipv4_buf[i] = ipa;
++				add = FALSE; /* added ipa to local table  */
++				DHD_ARPOE(("%s: Saved new IP in temp arp_hostip[%d]\n",
++				__FUNCTION__, i));
++		} else if (ipv4_buf[i] == ipa) {
++			ipv4_buf[i]	= 0;
++			DHD_ARPOE(("%s: removed IP:%x from temp table %d\n",
++				__FUNCTION__, ipa, i));
++		}
++
++		if (ipv4_buf[i] != 0) {
++			/* add back host_ip entries from our local cache */
++			dhd_arp_offload_add_ip(dhd_pub, ipv4_buf[i], idx);
++			DHD_ARPOE(("%s: added IP:%x to dongle arp_hostip[%d]\n\n",
++				__FUNCTION__, ipv4_buf[i], i));
++		}
++	}
++#ifdef AOE_DBG
++	/* see the resulting hostip table */
++	dhd_arp_get_arp_hostip_table(dhd_pub, ipv4_buf, sizeof(ipv4_buf), idx);
++	DHD_ARPOE(("%s: read back arp_hostip table:\n", __FUNCTION__));
++	dhd_print_buf(ipv4_buf, 32, 4); /* max 8 IPs 4b each */
++#endif
++}
++
++/*
++ * Notification mechanism from kernel to our driver. This function is called by the Linux kernel
++ * whenever there is an event related to an IP address.
++ * ptr : kernel provided pointer to IP address that has changed
++ */
++static int dhd_inetaddr_notifier_call(struct notifier_block *this,
++	unsigned long event,
++	void *ptr)
++{
++	struct in_ifaddr *ifa = (struct in_ifaddr *)ptr;
++
++	dhd_info_t *dhd;
++	dhd_pub_t *dhd_pub;
++	int idx;
++
++	if (!dhd_arp_enable)
++		return NOTIFY_DONE;
++	if (!ifa || !(ifa->ifa_dev->dev))
++		return NOTIFY_DONE;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
++	/* Filter notifications meant for non Broadcom devices */
++	if ((ifa->ifa_dev->dev->netdev_ops != &dhd_ops_pri) &&
++	    (ifa->ifa_dev->dev->netdev_ops != &dhd_ops_virt)) {
++#if defined(WL_ENABLE_P2P_IF)
++		if (!wl_cfgp2p_is_ifops(ifa->ifa_dev->dev->netdev_ops))
++#endif /* WL_ENABLE_P2P_IF */
++			return NOTIFY_DONE;
++	}
++#endif /* LINUX_VERSION_CODE */
++
++	dhd = DHD_DEV_INFO(ifa->ifa_dev->dev);
++	if (!dhd)
++		return NOTIFY_DONE;
++
++	dhd_pub = &dhd->pub;
++
++	if (dhd_pub->arp_version == 1) {
++		idx = 0;
++	} else {
++		for (idx = 0; idx < DHD_MAX_IFS; idx++) {
++			if (dhd->iflist[idx] && dhd->iflist[idx]->net == ifa->ifa_dev->dev)
++			break;
++		}
++		if (idx < DHD_MAX_IFS)
++			DHD_TRACE(("ifidx : %p %s %d\n", dhd->iflist[idx]->net,
++				dhd->iflist[idx]->name, dhd->iflist[idx]->idx));
++		else {
++			DHD_ERROR(("Cannot find ifidx for(%s) set to 0\n", ifa->ifa_label));
++			idx = 0;
++		}
++	}
++
++	switch (event) {
++		case NETDEV_UP:
++			DHD_ARPOE(("%s: [%s] Up IP: 0x%x\n",
++				__FUNCTION__, ifa->ifa_label, ifa->ifa_address));
++
++			if (dhd->pub.busstate != DHD_BUS_DATA) {
++				DHD_ERROR(("%s: bus not ready, exit\n", __FUNCTION__));
++				if (dhd->pend_ipaddr) {
++					DHD_ERROR(("%s: overwrite pending ipaddr: 0x%x\n",
++						__FUNCTION__, dhd->pend_ipaddr));
++				}
++				dhd->pend_ipaddr = ifa->ifa_address;
++				break;
++			}
++
++#ifdef AOE_IP_ALIAS_SUPPORT
++			DHD_ARPOE(("%s:add aliased IP to AOE hostip cache\n",
++				__FUNCTION__));
++			aoe_update_host_ipv4_table(dhd_pub, ifa->ifa_address, TRUE, idx);
++#endif /* AOE_IP_ALIAS_SUPPORT */
++			dhd_conf_set_garp(dhd_pub, idx, ifa->ifa_address, TRUE);
++			break;
++
++		case NETDEV_DOWN:
++			DHD_ARPOE(("%s: [%s] Down IP: 0x%x\n",
++				__FUNCTION__, ifa->ifa_label, ifa->ifa_address));
++			dhd->pend_ipaddr = 0;
++#ifdef AOE_IP_ALIAS_SUPPORT
++			DHD_ARPOE(("%s:interface is down, AOE clr all for this if\n",
++				__FUNCTION__));
++			if ((dhd_pub->op_mode & DHD_FLAG_HOSTAP_MODE) ||
++				(ifa->ifa_dev->dev != dhd_linux_get_primary_netdev(dhd_pub))) {
++				aoe_update_host_ipv4_table(dhd_pub, ifa->ifa_address, FALSE, idx);
++			} else
++#endif /* AOE_IP_ALIAS_SUPPORT */
++			{
++				dhd_aoe_hostip_clr(&dhd->pub, idx);
++				dhd_aoe_arp_clr(&dhd->pub, idx);
++			}
++			dhd_conf_set_garp(dhd_pub, idx, ifa->ifa_address, FALSE);
++			break;
++
++		default:
++			DHD_ARPOE(("%s: do noting for [%s] Event: %lu\n",
++				__func__, ifa->ifa_label, event));
++			break;
++	}
++	return NOTIFY_DONE;
++}
++#endif /* ARP_OFFLOAD_SUPPORT */
++
++#if defined(CONFIG_IPV6) && defined(IPV6_NDO_SUPPORT)
++/* Neighbor Discovery Offload: defered handler */
++static void
++dhd_inet6_work_handler(void *dhd_info, void *event_data, u8 event)
++{
++	struct ipv6_work_info_t *ndo_work = (struct ipv6_work_info_t *)event_data;
++	dhd_info_t *dhd = (dhd_info_t *)dhd_info;
++	dhd_pub_t *dhdp;
++	int ret;
++
++	if (!dhd) {
++		DHD_ERROR(("%s: invalid dhd_info\n", __FUNCTION__));
++		goto done;
++	}
++	dhdp = &dhd->pub;
++
++	if (event != DHD_WQ_WORK_IPV6_NDO) {
++		DHD_ERROR(("%s: unexpected event\n", __FUNCTION__));
++		goto done;
++	}
++
++	if (!ndo_work) {
++		DHD_ERROR(("%s: ipv6 work info is not initialized\n", __FUNCTION__));
++		return;
++	}
++
++	switch (ndo_work->event) {
++		case NETDEV_UP:
++#ifndef NDO_CONFIG_SUPPORT
++			DHD_TRACE(("%s: Enable NDO \n ", __FUNCTION__));
++			ret = dhd_ndo_enable(dhdp, TRUE);
++			if (ret < 0) {
++				DHD_ERROR(("%s: Enabling NDO Failed %d\n", __FUNCTION__, ret));
++			}
++#endif /* !NDO_CONFIG_SUPPORT */
++			DHD_TRACE(("%s: Add a host ip for NDO\n", __FUNCTION__));
++			if (dhdp->ndo_version > 0) {
++				/* inet6 addr notifier called only for unicast address */
++				ret = dhd_ndo_add_ip_with_type(dhdp, &ndo_work->ipv6_addr[0],
++					WL_ND_IPV6_ADDR_TYPE_UNICAST, ndo_work->if_idx);
++			} else {
++				ret = dhd_ndo_add_ip(dhdp, &ndo_work->ipv6_addr[0],
++						ndo_work->if_idx);
++			}
++			if (ret < 0) {
++				DHD_ERROR(("%s: Adding a host ip for NDO failed %d\n",
++					__FUNCTION__, ret));
++			}
++			break;
++		case NETDEV_DOWN:
++			if (dhdp->ndo_version > 0) {
++				DHD_TRACE(("%s: Remove a host ip for NDO\n", __FUNCTION__));
++				ret = dhd_ndo_remove_ip_by_addr(dhdp,
++					&ndo_work->ipv6_addr[0], ndo_work->if_idx);
++			} else {
++				DHD_TRACE(("%s: Clear host ip table for NDO \n", __FUNCTION__));
++				ret = dhd_ndo_remove_ip(dhdp, ndo_work->if_idx);
++			}
++			if (ret < 0) {
++				DHD_ERROR(("%s: Removing host ip for NDO failed %d\n",
++					__FUNCTION__, ret));
++				goto done;
++			}
++#ifdef NDO_CONFIG_SUPPORT
++			if (dhdp->ndo_host_ip_overflow) {
++				ret = dhd_dev_ndo_update_inet6addr(
++					dhd_idx2net(dhdp, ndo_work->if_idx));
++				if ((ret < 0) && (ret != BCME_NORESOURCE)) {
++					DHD_ERROR(("%s: Updating host ip for NDO failed %d\n",
++						__FUNCTION__, ret));
++					goto done;
++				}
++			}
++#else /* !NDO_CONFIG_SUPPORT */
++			DHD_TRACE(("%s: Disable NDO\n ", __FUNCTION__));
++			ret = dhd_ndo_enable(dhdp, FALSE);
++			if (ret < 0) {
++				DHD_ERROR(("%s: disabling NDO Failed %d\n", __FUNCTION__, ret));
++				goto done;
++			}
++#endif /* NDO_CONFIG_SUPPORT */
++			break;
++
++		default:
++			DHD_ERROR(("%s: unknown notifier event \n", __FUNCTION__));
++			break;
++	}
++done:
++	/* free ndo_work. alloced while scheduling the work */
++	if (ndo_work) {
++		kfree(ndo_work);
++	}
++
++	return;
++}
++
++/*
++ * Neighbor Discovery Offload: Called when an interface
++ * is assigned with ipv6 address.
++ * Handles only primary interface
++ */
++int dhd_inet6addr_notifier_call(struct notifier_block *this, unsigned long event, void *ptr)
++{
++	dhd_info_t *dhd;
++	dhd_pub_t *dhdp;
++	struct inet6_ifaddr *inet6_ifa = ptr;
++	struct ipv6_work_info_t *ndo_info;
++	int idx;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
++	/* Filter notifications meant for non Broadcom devices */
++	if (inet6_ifa->idev->dev->netdev_ops != &dhd_ops_pri) {
++			return NOTIFY_DONE;
++	}
++#endif /* LINUX_VERSION_CODE */
++
++	dhd = DHD_DEV_INFO(inet6_ifa->idev->dev);
++	if (!dhd) {
++		return NOTIFY_DONE;
++	}
++	dhdp = &dhd->pub;
++
++	/* Supports only primary interface */
++	idx = dhd_net2idx(dhd, inet6_ifa->idev->dev);
++	if (idx != 0) {
++		return NOTIFY_DONE;
++	}
++
++	/* FW capability */
++	if (!FW_SUPPORTED(dhdp, ndoe)) {
++		return NOTIFY_DONE;
++	}
++
++	ndo_info = (struct ipv6_work_info_t *)kzalloc(sizeof(struct ipv6_work_info_t), GFP_ATOMIC);
++	if (!ndo_info) {
++		DHD_ERROR(("%s: ipv6 work alloc failed\n", __FUNCTION__));
++		return NOTIFY_DONE;
++	}
++
++	/* fill up ndo_info */
++	ndo_info->event = event;
++	ndo_info->if_idx = idx;
++	memcpy(ndo_info->ipv6_addr, &inet6_ifa->addr, IPV6_ADDR_LEN);
++
++	/* defer the work to thread as it may block kernel */
++	dhd_deferred_schedule_work(dhd->dhd_deferred_wq, (void *)ndo_info, DHD_WQ_WORK_IPV6_NDO,
++		dhd_inet6_work_handler, DHD_WQ_WORK_PRIORITY_LOW);
++	return NOTIFY_DONE;
++}
++#endif /* CONFIG_IPV6 && IPV6_NDO_SUPPORT */
++
++int
++dhd_register_if(dhd_pub_t *dhdp, int ifidx, bool need_rtnl_lock)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++	dhd_if_t *ifp;
++	struct net_device *net = NULL;
++	int err = 0;
++	uint8 temp_addr[ETHER_ADDR_LEN] = { 0x00, 0x90, 0x4c, 0x11, 0x22, 0x33 };
++
++	DHD_TRACE(("%s: ifidx %d\n", __FUNCTION__, ifidx));
++
++	if (dhd == NULL || dhd->iflist[ifidx] == NULL) {
++		DHD_ERROR(("%s: Invalid Interface\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	ASSERT(dhd && dhd->iflist[ifidx]);
++	ifp = dhd->iflist[ifidx];
++	net = ifp->net;
++	ASSERT(net && (ifp->idx == ifidx));
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31))
++	ASSERT(!net->open);
++	net->get_stats = dhd_get_stats;
++	net->do_ioctl = dhd_ioctl_entry;
++	net->hard_start_xmit = dhd_start_xmit;
++	net->set_mac_address = dhd_set_mac_address;
++	net->set_multicast_list = dhd_set_multicast_list;
++	net->open = net->stop = NULL;
++#else
++	ASSERT(!net->netdev_ops);
++	net->netdev_ops = &dhd_ops_virt;
++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31) */
++
++	/* Ok, link into the network layer... */
++	if (ifidx == 0) {
++		/*
++		 * device functions for the primary interface only
++		 */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31))
++		net->open = dhd_open;
++		net->stop = dhd_stop;
++#else
++		net->netdev_ops = &dhd_ops_pri;
++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31) */
++		if (!ETHER_ISNULLADDR(dhd->pub.mac.octet))
++			memcpy(temp_addr, dhd->pub.mac.octet, ETHER_ADDR_LEN);
++	} else {
++		/*
++		 * We have to use the primary MAC for virtual interfaces
++		 */
++		memcpy(temp_addr, ifp->mac_addr, ETHER_ADDR_LEN);
++		/*
++		 * Android sets the locally administered bit to indicate that this is a
++		 * portable hotspot.  This will not work in simultaneous AP/STA mode,
++		 * nor with P2P.  Need to set the Donlge's MAC address, and then use that.
++		 */
++		if (!memcmp(temp_addr, dhd->iflist[0]->mac_addr,
++			ETHER_ADDR_LEN)) {
++			DHD_ERROR(("%s interface [%s]: set locally administered bit in MAC\n",
++			__func__, net->name));
++			temp_addr[0] |= 0x02;
++		}
++	}
++
++	net->hard_header_len = ETH_HLEN + dhd->pub.hdrlen;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
++	net->ethtool_ops = &dhd_ethtool_ops;
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24) */
++
++#if defined(WL_WIRELESS_EXT)
++#if WIRELESS_EXT < 19
++	net->get_wireless_stats = dhd_get_wireless_stats;
++#endif /* WIRELESS_EXT < 19 */
++#if WIRELESS_EXT > 12
++	net->wireless_handlers = &wl_iw_handler_def;
++#endif /* WIRELESS_EXT > 12 */
++#endif /* defined(WL_WIRELESS_EXT) */
++
++	dhd->pub.rxsz = DBUS_RX_BUFFER_SIZE_DHD(net);
++
++#ifdef WLMESH
++	if (ifidx >= 2 && dhdp->conf->fw_type == FW_TYPE_MESH) {
++		temp_addr[4] ^= 0x80;
++		temp_addr[4] += ifidx;
++		temp_addr[5] += ifidx;
++	}
++#endif
++	memcpy(net->dev_addr, temp_addr, ETHER_ADDR_LEN);
++
++	if (ifidx == 0)
++		printf("%s\n", dhd_version);
++	else {
++#ifdef WL_EXT_IAPSTA
++		wl_ext_iapsta_update_net_device(net, ifidx);
++#endif /* WL_EXT_IAPSTA */
++		if (_dhd_set_mac_address(dhd, ifidx, net->dev_addr) == 0)
++			DHD_INFO(("%s: MACID is overwritten\n", __FUNCTION__));
++		else
++			DHD_ERROR(("%s: _dhd_set_mac_address() failed\n", __FUNCTION__));
++	}
++
++	if (need_rtnl_lock)
++		err = register_netdev(net);
++	else
++		err = register_netdevice(net);
++
++	if (err != 0) {
++		DHD_ERROR(("couldn't register the net device [%s], err %d\n", net->name, err));
++		goto fail;
++	}
++#if defined(WL_EXT_IAPSTA) || defined(USE_IW) || defined(WL_ESCAN)
++	wl_ext_event_attach_netdev(net, ifidx, ifp->bssidx);
++#ifdef WL_ESCAN
++	wl_escan_event_attach(net, dhdp);
++#endif /* WL_ESCAN */
++#ifdef WL_EXT_IAPSTA
++	wl_ext_iapsta_attach_netdev(net, ifidx, ifp->bssidx);
++	wl_ext_iapsta_attach_name(net, ifidx);
++#endif /* WL_EXT_IAPSTA */
++#endif /* WL_EXT_IAPSTA || USE_IW || WL_ESCAN */
++
++
++
++	printf("Register interface [%s]  MAC: "MACDBG"\n\n", net->name,
++#if defined(CUSTOMER_HW4_DEBUG)
++		MAC2STRDBG(dhd->pub.mac.octet));
++#else
++		MAC2STRDBG(net->dev_addr));
++#endif /* CUSTOMER_HW4_DEBUG */
++
++#if defined(SOFTAP) && defined(WL_WIRELESS_EXT) && !defined(WL_CFG80211)
++//		wl_iw_iscan_set_scan_broadcast_prep(net, 1);
++#endif
++
++#if (defined(BCMPCIE) || (defined(BCMLXSDMMC) && (LINUX_VERSION_CODE >= \
++	KERNEL_VERSION(2, 6, 27))) || defined(BCMDBUS))
++	if (ifidx == 0) {
++#if defined(BCMLXSDMMC) && !defined(DHD_PRELOAD)
++		up(&dhd_registration_sem);
++#endif /* BCMLXSDMMC */
++		if (!dhd_download_fw_on_driverload) {
++#ifdef WL_CFG80211
++			wl_terminate_event_handler(net);
++#endif /* WL_CFG80211 */
++#if defined(DHD_LB_RXP)
++			__skb_queue_purge(&dhd->rx_pend_queue);
++#endif /* DHD_LB_RXP */
++
++#if defined(DHD_LB_TXP)
++			skb_queue_purge(&dhd->tx_pend_queue);
++#endif /* DHD_LB_TXP */
++
++#ifdef SHOW_LOGTRACE
++			/* Release the skbs from queue for WLC_E_TRACE event */
++			dhd_event_logtrace_flush_queue(dhdp);
++#endif /* SHOW_LOGTRACE */
++
++#ifdef DHDTCPACK_SUPPRESS
++			dhd_tcpack_suppress_set(dhdp, TCPACK_SUP_OFF);
++#endif /* DHDTCPACK_SUPPRESS */
++			dhd_net_bus_devreset(net, TRUE);
++#ifdef BCMLXSDMMC
++			dhd_net_bus_suspend(net);
++#endif /* BCMLXSDMMC */
++			wifi_platform_set_power(dhdp->info->adapter, FALSE, WIFI_TURNOFF_DELAY);
++#if defined(BT_OVER_SDIO)
++			dhd->bus_user_count--;
++#endif /* BT_OVER_SDIO */
++		}
++#if defined(WL_WIRELESS_EXT)
++		wl_iw_down(net, &dhd->pub);
++#endif /* defined(WL_WIRELESS_EXT) */
++	}
++#endif /* OEM_ANDROID && (BCMPCIE || (BCMLXSDMMC && KERNEL_VERSION >= 2.6.27)) */
++	return 0;
++
++fail:
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31)
++	net->open = NULL;
++#else
++	net->netdev_ops = NULL;
++#endif
++	return err;
++}
++
++void
++dhd_bus_detach(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (dhdp) {
++		dhd = (dhd_info_t *)dhdp->info;
++		if (dhd) {
++
++			/*
++			 * In case of Android cfg80211 driver, the bus is down in dhd_stop,
++			 *  calling stop again will cuase SD read/write errors.
++			 */
++			if (dhd->pub.busstate != DHD_BUS_DOWN && dhd_download_fw_on_driverload) {
++				/* Stop the protocol module */
++				dhd_prot_stop(&dhd->pub);
++
++				/* Stop the bus module */
++#ifdef BCMDBUS
++				/* Force Dongle terminated */
++				if (dhd_wl_ioctl_cmd(dhdp, WLC_TERMINATED, NULL, 0, TRUE, 0) < 0)
++					DHD_ERROR(("%s Setting WLC_TERMINATED failed\n",
++						__FUNCTION__));
++				dbus_stop(dhd->pub.bus);
++				dhd->pub.busstate = DHD_BUS_DOWN;
++#else
++				dhd_bus_stop(dhd->pub.bus, TRUE);
++#endif /* BCMDBUS */
++			}
++
++#if defined(OOB_INTR_ONLY) || defined(BCMPCIE_OOB_HOST_WAKE)
++			dhd_bus_oob_intr_unregister(dhdp);
++#endif 
++		}
++	}
++}
++
++
++void dhd_detach(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd;
++	unsigned long flags;
++	int timer_valid = FALSE;
++	struct net_device *dev;
++#ifdef WL_CFG80211
++	struct bcm_cfg80211 *cfg = NULL;
++#endif
++#ifdef HOFFLOAD_MODULES
++	struct module_metadata *hmem = NULL;
++#endif
++	if (!dhdp)
++		return;
++
++	dhd = (dhd_info_t *)dhdp->info;
++	if (!dhd)
++		return;
++
++	dev = dhd->iflist[0]->net;
++
++	if (dev) {
++		rtnl_lock();
++		if (dev->flags & IFF_UP) {
++			/* If IFF_UP is still up, it indicates that
++			 * "ifconfig wlan0 down" hasn't been called.
++			 * So invoke dev_close explicitly here to
++			 * bring down the interface.
++			 */
++			DHD_TRACE(("IFF_UP flag is up. Enforcing dev_close from detach \n"));
++			dev_close(dev);
++		}
++		rtnl_unlock();
++	}
++
++	DHD_TRACE(("%s: Enter state 0x%x\n", __FUNCTION__, dhd->dhd_state));
++
++	dhd->pub.up = 0;
++	if (!(dhd->dhd_state & DHD_ATTACH_STATE_DONE)) {
++		/* Give sufficient time for threads to start running in case
++		 * dhd_attach() has failed
++		 */
++		OSL_SLEEP(100);
++	}
++#ifdef DHD_WET
++	dhd_free_wet_info(&dhd->pub, dhd->pub.wet_info);
++#endif /* DHD_WET */
++#if defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW)
++#endif /* defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW) */
++
++#ifdef PROP_TXSTATUS
++#ifdef DHD_WLFC_THREAD
++	if (dhd->pub.wlfc_thread) {
++		kthread_stop(dhd->pub.wlfc_thread);
++		dhdp->wlfc_thread_go = TRUE;
++		wake_up_interruptible(&dhdp->wlfc_wqhead);
++	}
++	dhd->pub.wlfc_thread = NULL;
++#endif /* DHD_WLFC_THREAD */
++#endif /* PROP_TXSTATUS */
++
++#ifdef DHD_TIMESYNC
++	if (dhd->dhd_state & DHD_ATTACH_TIMESYNC_ATTACH_DONE) {
++		dhd_timesync_detach(dhdp);
++	}
++#endif /* DHD_TIMESYNC */
++#ifdef WL_CFG80211
++	if (dev) {
++		wl_cfg80211_down(dev);
++	}
++#endif /* WL_CFG80211 */
++
++	if (dhd->dhd_state & DHD_ATTACH_STATE_PROT_ATTACH) {
++		dhd_bus_detach(dhdp);
++#ifdef BCMPCIE
++		if (is_reboot == SYS_RESTART) {
++			extern bcmdhd_wifi_platdata_t *dhd_wifi_platdata;
++			if (dhd_wifi_platdata && !dhdp->dongle_reset) {
++				dhdpcie_bus_clock_stop(dhdp->bus);
++				wifi_platform_set_power(dhd_wifi_platdata->adapters,
++					FALSE, WIFI_TURNOFF_DELAY);
++			}
++		}
++#endif /* BCMPCIE */
++#ifndef PCIE_FULL_DONGLE
++		if (dhdp->prot)
++			dhd_prot_detach(dhdp);
++#endif /* !PCIE_FULL_DONGLE */
++	}
++
++#ifdef ARP_OFFLOAD_SUPPORT
++	if (dhd_inetaddr_notifier_registered) {
++		dhd_inetaddr_notifier_registered = FALSE;
++		unregister_inetaddr_notifier(&dhd_inetaddr_notifier);
++	}
++#endif /* ARP_OFFLOAD_SUPPORT */
++#if defined(CONFIG_IPV6) && defined(IPV6_NDO_SUPPORT)
++	if (dhd_inet6addr_notifier_registered) {
++		dhd_inet6addr_notifier_registered = FALSE;
++		unregister_inet6addr_notifier(&dhd_inet6addr_notifier);
++	}
++#endif /* CONFIG_IPV6 && IPV6_NDO_SUPPORT */
++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND)
++	if (dhd->dhd_state & DHD_ATTACH_STATE_EARLYSUSPEND_DONE) {
++		if (dhd->early_suspend.suspend)
++			unregister_early_suspend(&dhd->early_suspend);
++	}
++#endif /* CONFIG_HAS_EARLYSUSPEND && DHD_USE_EARLYSUSPEND */
++
++#if defined(WL_WIRELESS_EXT)
++	if (dhd->dhd_state & DHD_ATTACH_STATE_WL_ATTACH) {
++		/* Detatch and unlink in the iw */
++		wl_iw_detach(dev, dhdp);
++	}
++#endif /* defined(WL_WIRELESS_EXT) */
++#if defined(WL_EXT_IAPSTA) || defined(USE_IW) || defined(WL_ESCAN)
++#ifdef WL_EXT_IAPSTA
++	wl_ext_iapsta_dettach(dhdp);
++#endif /* WL_EXT_IAPSTA */
++#ifdef WL_ESCAN
++	wl_escan_detach(dev, dhdp);
++#endif /* WL_ESCAN */
++	wl_ext_event_dettach(dhdp);
++#endif /* WL_EXT_IAPSTA || USE_IW || WL_ESCAN */
++
++#ifdef DHD_ULP
++	dhd_ulp_deinit(dhd->pub.osh, dhdp);
++#endif /* DHD_ULP */
++
++	/* delete all interfaces, start with virtual  */
++	if (dhd->dhd_state & DHD_ATTACH_STATE_ADD_IF) {
++		int i = 1;
++		dhd_if_t *ifp;
++
++		/* Cleanup virtual interfaces */
++		dhd_net_if_lock_local(dhd);
++		for (i = 1; i < DHD_MAX_IFS; i++) {
++			if (dhd->iflist[i]) {
++				dhd_remove_if(&dhd->pub, i, TRUE);
++			}
++		}
++		dhd_net_if_unlock_local(dhd);
++
++		/*  delete primary interface 0 */
++		ifp = dhd->iflist[0];
++		ASSERT(ifp);
++		ASSERT(ifp->net);
++		if (ifp && ifp->net) {
++#ifdef WL_CFG80211
++			cfg = wl_get_cfg(ifp->net);
++#endif
++			/* in unregister_netdev case, the interface gets freed by net->destructor
++			 * (which is set to free_netdev)
++			 */
++			if (ifp->net->reg_state == NETREG_UNINITIALIZED) {
++				free_netdev(ifp->net);
++			} else {
++				argos_register_notifier_deinit();
++#ifdef SET_RPS_CPUS
++				custom_rps_map_clear(ifp->net->_rx);
++#endif /* SET_RPS_CPUS */
++				netif_tx_disable(ifp->net);
++				unregister_netdev(ifp->net);
++			}
++#ifdef PCIE_FULL_DONGLE
++			ifp->net = DHD_NET_DEV_NULL;
++#else
++			ifp->net = NULL;
++#endif /* PCIE_FULL_DONGLE */
++
++#ifdef DHD_WMF
++			dhd_wmf_cleanup(dhdp, 0);
++#endif /* DHD_WMF */
++#ifdef DHD_L2_FILTER
++			bcm_l2_filter_arp_table_update(dhdp->osh, ifp->phnd_arp_table, TRUE,
++				NULL, FALSE, dhdp->tickcnt);
++			deinit_l2_filter_arp_table(dhdp->osh, ifp->phnd_arp_table);
++			ifp->phnd_arp_table = NULL;
++#endif /* DHD_L2_FILTER */
++
++
++			dhd_if_del_sta_list(ifp);
++
++			MFREE(dhd->pub.osh, ifp, sizeof(*ifp));
++			dhd->iflist[0] = NULL;
++		}
++	}
++
++	/* Clear the watchdog timer */
++	DHD_GENERAL_LOCK(&dhd->pub, flags);
++	timer_valid = dhd->wd_timer_valid;
++	dhd->wd_timer_valid = FALSE;
++	DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++	if (timer_valid)
++		_del_timer_sync(&dhd->timer);
++	DHD_DISABLE_RUNTIME_PM(&dhd->pub);
++
++#ifdef BCMDBUS
++	tasklet_kill(&dhd->tasklet);
++#else
++	if (dhd->dhd_state & DHD_ATTACH_STATE_THREADS_CREATED) {
++#ifdef DHD_PCIE_RUNTIMEPM
++		if (dhd->thr_rpm_ctl.thr_pid >= 0) {
++			PROC_STOP(&dhd->thr_rpm_ctl);
++		}
++#endif /* DHD_PCIE_RUNTIMEPM */
++		if (dhd->thr_wdt_ctl.thr_pid >= 0) {
++			PROC_STOP(&dhd->thr_wdt_ctl);
++		}
++
++		if (dhd->rxthread_enabled && dhd->thr_rxf_ctl.thr_pid >= 0) {
++			PROC_STOP(&dhd->thr_rxf_ctl);
++		}
++
++		if (dhd->thr_dpc_ctl.thr_pid >= 0) {
++			PROC_STOP(&dhd->thr_dpc_ctl);
++		} else
++		{
++			tasklet_kill(&dhd->tasklet);
++		}
++	}
++#endif /* BCMDBUS */
++
++#ifdef DHD_LB
++	if (dhd->dhd_state & DHD_ATTACH_STATE_LB_ATTACH_DONE) {
++		/* Clear the flag first to avoid calling the cpu notifier */
++		dhd->dhd_state &= ~DHD_ATTACH_STATE_LB_ATTACH_DONE;
++
++		/* Kill the Load Balancing Tasklets */
++#ifdef DHD_LB_RXP
++		cancel_work_sync(&dhd->rx_napi_dispatcher_work);
++		__skb_queue_purge(&dhd->rx_pend_queue);
++#endif /* DHD_LB_RXP */
++#ifdef DHD_LB_TXP
++		cancel_work_sync(&dhd->tx_dispatcher_work);
++		tasklet_kill(&dhd->tx_tasklet);
++		__skb_queue_purge(&dhd->tx_pend_queue);
++#endif /* DHD_LB_TXP */
++#ifdef DHD_LB_TXC
++		cancel_work_sync(&dhd->tx_compl_dispatcher_work);
++		tasklet_kill(&dhd->tx_compl_tasklet);
++#endif /* DHD_LB_TXC */
++#ifdef DHD_LB_RXC
++		tasklet_kill(&dhd->rx_compl_tasklet);
++#endif /* DHD_LB_RXC */
++
++		if (dhd->cpu_notifier.notifier_call != NULL) {
++			unregister_cpu_notifier(&dhd->cpu_notifier);
++		}
++		dhd_cpumasks_deinit(dhd);
++		DHD_LB_STATS_DEINIT(&dhd->pub);
++	}
++#endif /* DHD_LB */
++
++	DHD_SSSR_MEMPOOL_DEINIT(&dhd->pub);
++
++#ifdef DHD_LOG_DUMP
++	dhd_log_dump_deinit(&dhd->pub);
++#endif /* DHD_LOG_DUMP */
++#ifdef WL_CFG80211
++	if (dhd->dhd_state & DHD_ATTACH_STATE_CFG80211) {
++		if (!cfg) {
++			DHD_ERROR(("cfg NULL!\n"));
++			ASSERT(0);
++		} else {
++			wl_cfg80211_detach(cfg);
++			dhd_monitor_uninit();
++		}
++	}
++#endif
++
++#ifdef DEBUGABILITY
++	if (dhdp->dbg) {
++#ifdef DBG_PKT_MON
++		dhd_os_dbg_detach_pkt_monitor(dhdp);
++		dhd_os_spin_lock_deinit(dhd->pub.osh, dhd->pub.dbg->pkt_mon_lock);
++#endif /* DBG_PKT_MON */
++		dhd_os_dbg_detach(dhdp);
++	}
++#endif /* DEBUGABILITY */
++#ifdef SHOW_LOGTRACE
++#ifdef DHD_PKT_LOGGING
++	dhd_os_detach_pktlog(dhdp);
++#endif /* DHD_PKT_LOGGING */
++	/* Release the skbs from queue for WLC_E_TRACE event */
++	dhd_event_logtrace_flush_queue(dhdp);
++
++	if (dhd->dhd_state & DHD_ATTACH_LOGTRACE_INIT) {
++		if (dhd->event_data.fmts) {
++			MFREE(dhd->pub.osh, dhd->event_data.fmts,
++					dhd->event_data.fmts_size);
++			dhd->event_data.fmts = NULL;
++		}
++		if (dhd->event_data.raw_fmts) {
++			MFREE(dhd->pub.osh, dhd->event_data.raw_fmts,
++					dhd->event_data.raw_fmts_size);
++			dhd->event_data.raw_fmts = NULL;
++		}
++		if (dhd->event_data.raw_sstr) {
++			MFREE(dhd->pub.osh, dhd->event_data.raw_sstr,
++					dhd->event_data.raw_sstr_size);
++			dhd->event_data.raw_sstr = NULL;
++		}
++		if (dhd->event_data.rom_raw_sstr) {
++			MFREE(dhd->pub.osh, dhd->event_data.rom_raw_sstr,
++					dhd->event_data.rom_raw_sstr_size);
++			dhd->event_data.rom_raw_sstr = NULL;
++		}
++		dhd->dhd_state &= ~DHD_ATTACH_LOGTRACE_INIT;
++	}
++#endif /* SHOW_LOGTRACE */
++#ifdef BCMPCIE
++	if (dhdp->extended_trap_data)
++	{
++		MFREE(dhdp->osh, dhdp->extended_trap_data, BCMPCIE_EXT_TRAP_DATA_MAXLEN);
++		dhdp->extended_trap_data = NULL;
++	}
++#endif /* BCMPCIE */
++#ifdef PNO_SUPPORT
++	if (dhdp->pno_state)
++		dhd_pno_deinit(dhdp);
++#endif
++#ifdef RTT_SUPPORT
++	if (dhdp->rtt_state) {
++		dhd_rtt_deinit(dhdp);
++	}
++#endif
++#if defined(CONFIG_PM_SLEEP)
++	if (dhd_pm_notifier_registered) {
++		unregister_pm_notifier(&dhd->pm_notifier);
++		dhd_pm_notifier_registered = FALSE;
++	}
++#endif /* CONFIG_PM_SLEEP */
++
++#ifdef DEBUG_CPU_FREQ
++		if (dhd->new_freq)
++			free_percpu(dhd->new_freq);
++		dhd->new_freq = NULL;
++		cpufreq_unregister_notifier(&dhd->freq_trans, CPUFREQ_TRANSITION_NOTIFIER);
++#endif
++	DHD_TRACE(("wd wakelock count:%d\n", dhd->wakelock_wd_counter));
++#ifdef CONFIG_HAS_WAKELOCK
++	dhd->wakelock_wd_counter = 0;
++	wake_lock_destroy(&dhd->wl_wdwake);
++	// terence 20161023: can not destroy wl_wifi when wlan down, it will happen null pointer in dhd_ioctl_entry
++	wake_lock_destroy(&dhd->wl_wifi);
++#endif /* CONFIG_HAS_WAKELOCK */
++	if (dhd->dhd_state & DHD_ATTACH_STATE_WAKELOCKS_INIT) {
++		DHD_OS_WAKE_LOCK_DESTROY(dhd);
++	}
++
++
++
++#ifdef DHDTCPACK_SUPPRESS
++	/* This will free all MEM allocated for TCPACK SUPPRESS */
++	dhd_tcpack_suppress_set(&dhd->pub, TCPACK_SUP_OFF);
++#endif /* DHDTCPACK_SUPPRESS */
++
++#ifdef PCIE_FULL_DONGLE
++	dhd_flow_rings_deinit(dhdp);
++	if (dhdp->prot)
++		dhd_prot_detach(dhdp);
++#endif
++
++#if defined(WLTDLS) && defined(PCIE_FULL_DONGLE)
++		dhd_free_tdls_peer_list(dhdp);
++#endif
++
++#ifdef HOFFLOAD_MODULES
++	hmem = &dhdp->hmem;
++	dhd_free_module_memory(dhdp->bus, hmem);
++#endif /* HOFFLOAD_MODULES */
++#if defined(BT_OVER_SDIO)
++	mutex_destroy(&dhd->bus_user_lock);
++#endif /* BT_OVER_SDIO */
++#ifdef DUMP_IOCTL_IOV_LIST
++	dhd_iov_li_delete(dhdp, &(dhdp->dump_iovlist_head));
++#endif /* DUMP_IOCTL_IOV_LIST */
++#ifdef DHD_DEBUG
++	/* memory waste feature list initilization */
++	dhd_mw_list_delete(dhdp, &(dhdp->mw_list_head));
++#endif /* DHD_DEBUG */
++#ifdef WL_MONITOR
++	dhd_del_monitor_if(dhd, NULL, DHD_WQ_WORK_IF_DEL);
++#endif /* WL_MONITOR */
++
++	/* Prefer adding de-init code above this comment unless necessary.
++	 * The idea is to cancel work queue, sysfs and flags at the end.
++	 */
++	dhd_deferred_work_deinit(dhd->dhd_deferred_wq);
++	dhd->dhd_deferred_wq = NULL;
++
++#ifdef SHOW_LOGTRACE
++	/* Wait till event_log_dispatcher_work finishes */
++	cancel_work_sync(&dhd->event_log_dispatcher_work);
++#endif /* SHOW_LOGTRACE */
++
++	dhd_sysfs_exit(dhd);
++	dhd->pub.fw_download_done = FALSE;
++	dhd_conf_detach(dhdp);
++}
++
++
++void
++dhd_free(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd;
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (dhdp) {
++		int i;
++		for (i = 0; i < ARRAYSIZE(dhdp->reorder_bufs); i++) {
++			if (dhdp->reorder_bufs[i]) {
++				reorder_info_t *ptr;
++				uint32 buf_size = sizeof(struct reorder_info);
++
++				ptr = dhdp->reorder_bufs[i];
++
++				buf_size += ((ptr->max_idx + 1) * sizeof(void*));
++				DHD_REORDER(("free flow id buf %d, maxidx is %d, buf_size %d\n",
++					i, ptr->max_idx, buf_size));
++
++				MFREE(dhdp->osh, dhdp->reorder_bufs[i], buf_size);
++				dhdp->reorder_bufs[i] = NULL;
++			}
++		}
++
++		dhd_sta_pool_fini(dhdp, DHD_MAX_STA);
++
++		dhd = (dhd_info_t *)dhdp->info;
++		if (dhdp->soc_ram) {
++#if defined(CONFIG_DHD_USE_STATIC_BUF) && defined(DHD_USE_STATIC_MEMDUMP)
++			DHD_OS_PREFREE(dhdp, dhdp->soc_ram, dhdp->soc_ram_length);
++#else
++			MFREE(dhdp->osh, dhdp->soc_ram, dhdp->soc_ram_length);
++#endif /* CONFIG_DHD_USE_STATIC_BUF && DHD_USE_STATIC_MEMDUMP */
++			dhdp->soc_ram = NULL;
++		}
++#ifdef CACHE_FW_IMAGES
++		if (dhdp->cached_fw) {
++			MFREE(dhdp->osh, dhdp->cached_fw, dhdp->bus->ramsize);
++			dhdp->cached_fw = NULL;
++		}
++
++		if (dhdp->cached_nvram) {
++			MFREE(dhdp->osh, dhdp->cached_nvram, MAX_NVRAMBUF_SIZE);
++			dhdp->cached_nvram = NULL;
++		}
++#endif
++		if (dhd) {
++#ifdef REPORT_FATAL_TIMEOUTS
++			deinit_dhd_timeouts(&dhd->pub);
++#endif /* REPORT_FATAL_TIMEOUTS */
++
++			/* If pointer is allocated by dhd_os_prealloc then avoid MFREE */
++			if (dhd != (dhd_info_t *)dhd_os_prealloc(dhdp,
++					DHD_PREALLOC_DHD_INFO, 0, FALSE))
++				MFREE(dhd->pub.osh, dhd, sizeof(*dhd));
++			dhd = NULL;
++		}
++	}
++}
++
++void
++dhd_clear(dhd_pub_t *dhdp)
++{
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (dhdp) {
++		int i;
++#ifdef DHDTCPACK_SUPPRESS
++		/* Clean up timer/data structure for any remaining/pending packet or timer. */
++		dhd_tcpack_info_tbl_clean(dhdp);
++#endif /* DHDTCPACK_SUPPRESS */
++		for (i = 0; i < ARRAYSIZE(dhdp->reorder_bufs); i++) {
++			if (dhdp->reorder_bufs[i]) {
++				reorder_info_t *ptr;
++				uint32 buf_size = sizeof(struct reorder_info);
++
++				ptr = dhdp->reorder_bufs[i];
++
++				buf_size += ((ptr->max_idx + 1) * sizeof(void*));
++				DHD_REORDER(("free flow id buf %d, maxidx is %d, buf_size %d\n",
++					i, ptr->max_idx, buf_size));
++
++				MFREE(dhdp->osh, dhdp->reorder_bufs[i], buf_size);
++				dhdp->reorder_bufs[i] = NULL;
++			}
++		}
++
++		dhd_sta_pool_clear(dhdp, DHD_MAX_STA);
++
++		if (dhdp->soc_ram) {
++#if defined(CONFIG_DHD_USE_STATIC_BUF) && defined(DHD_USE_STATIC_MEMDUMP)
++			DHD_OS_PREFREE(dhdp, dhdp->soc_ram, dhdp->soc_ram_length);
++#else
++			MFREE(dhdp->osh, dhdp->soc_ram, dhdp->soc_ram_length);
++#endif /* CONFIG_DHD_USE_STATIC_BUF && DHD_USE_STATIC_MEMDUMP */
++			dhdp->soc_ram = NULL;
++		}
++	}
++}
++
++static void
++dhd_module_cleanup(void)
++{
++	printf("%s: Enter\n", __FUNCTION__);
++
++	dhd_bus_unregister();
++
++	wl_android_exit();
++
++	dhd_wifi_platform_unregister_drv();
++	printf("%s: Exit\n", __FUNCTION__);
++}
++
++static void __exit
++dhd_module_exit(void)
++{
++	atomic_set(&exit_in_progress, 1);
++	dhd_module_cleanup();
++	unregister_reboot_notifier(&dhd_reboot_notifier);
++	dhd_destroy_to_notifier_skt();
++}
++
++static int __init
++dhd_module_init(void)
++{
++	int err;
++	int retry = POWERUP_MAX_RETRY;
++
++	printf("%s: in %s\n", __FUNCTION__, dhd_version);
++
++	DHD_PERIM_RADIO_INIT();
++
++
++	if (firmware_path[0] != '\0') {
++		strncpy(fw_bak_path, firmware_path, MOD_PARAM_PATHLEN);
++		fw_bak_path[MOD_PARAM_PATHLEN-1] = '\0';
++	}
++
++	if (nvram_path[0] != '\0') {
++		strncpy(nv_bak_path, nvram_path, MOD_PARAM_PATHLEN);
++		nv_bak_path[MOD_PARAM_PATHLEN-1] = '\0';
++	}
++
++	do {
++		err = dhd_wifi_platform_register_drv();
++		if (!err) {
++			register_reboot_notifier(&dhd_reboot_notifier);
++			break;
++		} else {
++			DHD_ERROR(("%s: Failed to load the driver, try cnt %d\n",
++				__FUNCTION__, retry));
++			strncpy(firmware_path, fw_bak_path, MOD_PARAM_PATHLEN);
++			firmware_path[MOD_PARAM_PATHLEN-1] = '\0';
++			strncpy(nvram_path, nv_bak_path, MOD_PARAM_PATHLEN);
++			nvram_path[MOD_PARAM_PATHLEN-1] = '\0';
++		}
++	} while (retry--);
++
++	dhd_create_to_notifier_skt();
++
++	if (err) {
++		DHD_ERROR(("%s: Failed to load driver max retry reached**\n", __FUNCTION__));
++	} else {
++		if (!dhd_download_fw_on_driverload) {
++			dhd_driver_init_done = TRUE;
++		}
++	}
++
++	printf("%s: Exit err=%d\n", __FUNCTION__, err);
++	return err;
++}
++
++static int
++dhd_reboot_callback(struct notifier_block *this, unsigned long code, void *unused)
++{
++	DHD_TRACE(("%s: code = %ld\n", __FUNCTION__, code));
++	if (code == SYS_RESTART) {
++#ifdef BCMPCIE
++		is_reboot = code;
++#endif /* BCMPCIE */
++	}
++	return NOTIFY_DONE;
++}
++
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
++#if defined(CONFIG_DEFERRED_INITCALLS) && !defined(EXYNOS_PCIE_MODULE_PATCH)
++#if defined(CONFIG_MACH_UNIVERSAL7420) || defined(CONFIG_SOC_EXYNOS8890) || \
++	defined(CONFIG_ARCH_MSM8996) || defined(CONFIG_SOC_EXYNOS8895) || \
++	defined(CONFIG_ARCH_MSM8998)
++deferred_module_init_sync(dhd_module_init);
++#else
++deferred_module_init(dhd_module_init);
++#endif /* CONFIG_MACH_UNIVERSAL7420 || CONFIG_SOC_EXYNOS8890 ||
++	* CONFIG_ARCH_MSM8996 || CONFIG_SOC_EXYNOS8895 || CONFIG_ARCH_MSM8998
++	*/
++#elif defined(USE_LATE_INITCALL_SYNC)
++late_initcall_sync(dhd_module_init);
++#else
++late_initcall(dhd_module_init);
++#endif /* USE_LATE_INITCALL_SYNC */
++#else
++module_init(dhd_module_init);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0) */
++
++module_exit(dhd_module_exit);
++
++/*
++ * OS specific functions required to implement DHD driver in OS independent way
++ */
++int
++dhd_os_proto_block(dhd_pub_t *pub)
++{
++	dhd_info_t * dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		DHD_PERIM_UNLOCK(pub);
++
++		down(&dhd->proto_sem);
++
++		DHD_PERIM_LOCK(pub);
++		return 1;
++	}
++
++	return 0;
++}
++
++int
++dhd_os_proto_unblock(dhd_pub_t *pub)
++{
++	dhd_info_t * dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		up(&dhd->proto_sem);
++		return 1;
++	}
++
++	return 0;
++}
++
++void
++dhd_os_dhdiovar_lock(dhd_pub_t *pub)
++{
++	dhd_info_t * dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		mutex_lock(&dhd->dhd_iovar_mutex);
++	}
++}
++
++void
++dhd_os_dhdiovar_unlock(dhd_pub_t *pub)
++{
++	dhd_info_t * dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		mutex_unlock(&dhd->dhd_iovar_mutex);
++	}
++}
++
++unsigned int
++dhd_os_get_ioctl_resp_timeout(void)
++{
++	return ((unsigned int)dhd_ioctl_timeout_msec);
++}
++
++void
++dhd_os_set_ioctl_resp_timeout(unsigned int timeout_msec)
++{
++	dhd_ioctl_timeout_msec = (int)timeout_msec;
++}
++
++int
++dhd_os_ioctl_resp_wait(dhd_pub_t *pub, uint *condition)
++{
++	dhd_info_t * dhd = (dhd_info_t *)(pub->info);
++	int timeout;
++
++	/* Convert timeout in millsecond to jiffies */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++	timeout = msecs_to_jiffies(dhd_ioctl_timeout_msec);
++#else
++	timeout = dhd_ioctl_timeout_msec * HZ / 1000;
++#endif
++
++	DHD_PERIM_UNLOCK(pub);
++
++	timeout = wait_event_timeout(dhd->ioctl_resp_wait, (*condition), timeout);
++
++	DHD_PERIM_LOCK(pub);
++
++	return timeout;
++}
++
++int
++dhd_os_ioctl_resp_wake(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	wake_up(&dhd->ioctl_resp_wait);
++	return 0;
++}
++
++int
++dhd_os_d3ack_wait(dhd_pub_t *pub, uint *condition)
++{
++	dhd_info_t * dhd = (dhd_info_t *)(pub->info);
++	int timeout;
++
++	/* Convert timeout in millsecond to jiffies */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++	timeout = msecs_to_jiffies(dhd_ioctl_timeout_msec);
++#else
++	timeout = dhd_ioctl_timeout_msec * HZ / 1000;
++#endif
++
++	DHD_PERIM_UNLOCK(pub);
++
++	timeout = wait_event_timeout(dhd->d3ack_wait, (*condition), timeout);
++
++	DHD_PERIM_LOCK(pub);
++
++	return timeout;
++}
++
++#ifdef PCIE_INB_DW
++int
++dhd_os_ds_exit_wait(dhd_pub_t *pub, uint *condition)
++{
++	dhd_info_t * dhd = (dhd_info_t *)(pub->info);
++	int timeout;
++
++	/* Convert timeout in millsecond to jiffies */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++	timeout = msecs_to_jiffies(ds_exit_timeout_msec);
++#else
++	timeout = ds_exit_timeout_msec * HZ / 1000;
++#endif
++
++	DHD_PERIM_UNLOCK(pub);
++
++	timeout = wait_event_timeout(dhd->ds_exit_wait, (*condition), timeout);
++
++	DHD_PERIM_LOCK(pub);
++
++	return timeout;
++}
++
++int
++dhd_os_ds_exit_wake(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	wake_up(&dhd->ds_exit_wait);
++	return 0;
++}
++
++#endif /* PCIE_INB_DW */
++
++int
++dhd_os_d3ack_wake(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	wake_up(&dhd->d3ack_wait);
++	return 0;
++}
++
++int
++dhd_os_busbusy_wait_negation(dhd_pub_t *pub, uint *condition)
++{
++	dhd_info_t * dhd = (dhd_info_t *)(pub->info);
++	int timeout;
++
++	/* Wait for bus usage contexts to gracefully exit within some timeout value
++	 * Set time out to little higher than dhd_ioctl_timeout_msec,
++	 * so that IOCTL timeout should not get affected.
++	 */
++	/* Convert timeout in millsecond to jiffies */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++	timeout = msecs_to_jiffies(DHD_BUS_BUSY_TIMEOUT);
++#else
++	timeout = DHD_BUS_BUSY_TIMEOUT * HZ / 1000;
++#endif
++
++	timeout = wait_event_timeout(dhd->dhd_bus_busy_state_wait, !(*condition), timeout);
++
++	return timeout;
++}
++
++/*
++ * Wait until the condition *var == condition is met.
++ * Returns 0 if the @condition evaluated to false after the timeout elapsed
++ * Returns 1 if the @condition evaluated to true
++ */
++int
++dhd_os_busbusy_wait_condition(dhd_pub_t *pub, uint *var, uint condition)
++{
++	dhd_info_t * dhd = (dhd_info_t *)(pub->info);
++	int timeout;
++
++	/* Convert timeout in millsecond to jiffies */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++	timeout = msecs_to_jiffies(DHD_BUS_BUSY_TIMEOUT);
++#else
++	timeout = DHD_BUS_BUSY_TIMEOUT * HZ / 1000;
++#endif
++
++	timeout = wait_event_timeout(dhd->dhd_bus_busy_state_wait, (*var == condition), timeout);
++
++	return timeout;
++}
++
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))
++/* Fix compilation error for FC11 */
++INLINE
++#endif
++int
++dhd_os_busbusy_wake(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	/* Call wmb() to make sure before waking up the other event value gets updated */
++	OSL_SMP_WMB();
++	wake_up(&dhd->dhd_bus_busy_state_wait);
++	return 0;
++}
++
++void
++dhd_os_wd_timer_extend(void *bus, bool extend)
++{
++#ifndef BCMDBUS
++	dhd_pub_t *pub = bus;
++	dhd_info_t *dhd = (dhd_info_t *)pub->info;
++
++	if (extend)
++		dhd_os_wd_timer(bus, WATCHDOG_EXTEND_INTERVAL);
++	else
++		dhd_os_wd_timer(bus, dhd->default_wd_interval);
++#endif /* !BCMDBUS */
++}
++
++
++void
++dhd_os_wd_timer(void *bus, uint wdtick)
++{
++#ifndef BCMDBUS
++	dhd_pub_t *pub = bus;
++	dhd_info_t *dhd = (dhd_info_t *)pub->info;
++	unsigned long flags;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd NULL\n", __FUNCTION__));
++		return;
++	}
++
++	DHD_GENERAL_LOCK(pub, flags);
++
++	/* don't start the wd until fw is loaded */
++	if (pub->busstate == DHD_BUS_DOWN) {
++		DHD_GENERAL_UNLOCK(pub, flags);
++		return;
++	}
++
++	/* Totally stop the timer */
++	if (!wdtick && dhd->wd_timer_valid == TRUE) {
++		dhd->wd_timer_valid = FALSE;
++		DHD_GENERAL_UNLOCK(pub, flags);
++		_del_timer_sync(&dhd->timer);
++		return;
++	}
++
++	if (wdtick) {
++		dhd_watchdog_ms = (uint)wdtick;
++		/* Re arm the timer, at last watchdog period */
++		mod_timer(&dhd->timer, jiffies + msecs_to_jiffies(dhd_watchdog_ms));
++		dhd->wd_timer_valid = TRUE;
++	}
++	DHD_GENERAL_UNLOCK(pub, flags);
++#endif /* !BCMDBUS */
++}
++
++#ifdef DHD_PCIE_RUNTIMEPM
++void
++dhd_os_runtimepm_timer(void *bus, uint tick)
++{
++	dhd_pub_t *pub = bus;
++	dhd_info_t *dhd = (dhd_info_t *)pub->info;
++	unsigned long flags;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	DHD_GENERAL_LOCK(pub, flags);
++
++	/* don't start the RPM until fw is loaded */
++	if (DHD_BUS_CHECK_DOWN_OR_DOWN_IN_PROGRESS(pub)) {
++		DHD_GENERAL_UNLOCK(pub, flags);
++		return;
++	}
++
++	/* If tick is non-zero, the request is to start the timer */
++	if (tick) {
++		/* Start the timer only if its not already running */
++		if (dhd->rpm_timer_valid == FALSE) {
++			mod_timer(&dhd->rpm_timer, jiffies + msecs_to_jiffies(dhd_runtimepm_ms));
++			dhd->rpm_timer_valid = TRUE;
++		}
++	} else {
++		/* tick is zero, we have to stop the timer */
++		/* Stop the timer only if its running, otherwise we don't have to do anything */
++		if (dhd->rpm_timer_valid == TRUE) {
++			dhd->rpm_timer_valid = FALSE;
++			DHD_GENERAL_UNLOCK(pub, flags);
++			_del_timer_sync(&dhd->rpm_timer);
++			/* we have already released the lock, so just go to exit */
++			goto exit;
++		}
++	}
++
++	DHD_GENERAL_UNLOCK(pub, flags);
++exit:
++	return;
++
++}
++
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++void *
++dhd_os_open_image(char *filename)
++{
++	struct file *fp;
++	int size;
++
++	fp = filp_open(filename, O_RDONLY, 0);
++	/*
++	 * 2.6.11 (FC4) supports filp_open() but later revs don't?
++	 * Alternative:
++	 * fp = open_namei(AT_FDCWD, filename, O_RD, 0);
++	 * ???
++	 */
++	 if (IS_ERR(fp)) {
++		 fp = NULL;
++		 goto err;
++	 }
++
++	 if (!S_ISREG(file_inode(fp)->i_mode)) {
++		 DHD_ERROR(("%s: %s is not regular file\n", __FUNCTION__, filename));
++		 fp = NULL;
++		 goto err;
++	 }
++
++	 size = i_size_read(file_inode(fp));
++	 if (size <= 0) {
++		 DHD_ERROR(("%s: %s file size invalid %d\n", __FUNCTION__, filename, size));
++		 fp = NULL;
++		 goto err;
++	 }
++
++	 DHD_ERROR(("%s: %s (%d bytes) open success\n", __FUNCTION__, filename, size));
++
++err:
++	 return fp;
++}
++
++int
++dhd_os_get_image_block(char *buf, int len, void *image)
++{
++	struct file *fp = (struct file *)image;
++	int rdlen;
++	int size;
++
++	if (!image) {
++		return 0;
++	}
++
++	size = i_size_read(file_inode(fp));
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++	rdlen = kernel_read(fp, buf, MIN(len, size), &fp->f_pos);
++#else
++	rdlen = kernel_read(fp, fp->f_pos, buf, MIN(len, size));
++#endif
++
++	if (len >= size && size != rdlen) {
++		return -EIO;
++	}
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0)
++	if (rdlen > 0) {
++		fp->f_pos += rdlen;
++	}
++#endif
++
++	return rdlen;
++}
++
++int
++dhd_os_get_image_size(void *image)
++{
++	struct file *fp = (struct file *)image;
++	int size;
++	if (!image) {
++		return 0;
++	}
++
++	size = i_size_read(file_inode(fp));
++
++	return size;
++}
++
++#if defined(BT_OVER_SDIO)
++int
++dhd_os_gets_image(dhd_pub_t *pub, char *str, int len, void *image)
++{
++	struct file *fp = (struct file *)image;
++	int rd_len;
++	uint str_len = 0;
++	char *str_end = NULL;
++
++	if (!image)
++		return 0;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++	rd_len = kernel_read(fp, str, len, &fp->f_pos);
++#else
++	rd_len = kernel_read(fp, fp->f_pos, str, len);
++#endif
++	str_end = strnchr(str, len, '\n');
++	if (str_end == NULL) {
++		goto err;
++	}
++	str_len = (uint)(str_end - str);
++
++	/* Advance file pointer past the string length */
++	fp->f_pos += str_len + 1;
++	bzero(str_end, rd_len - str_len);
++
++err:
++	return str_len;
++}
++#endif /* defined (BT_OVER_SDIO) */
++
++
++void
++dhd_os_close_image(void *image)
++{
++	if (image)
++		filp_close((struct file *)image, NULL);
++}
++
++void
++dhd_os_sdlock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd;
++
++	dhd = (dhd_info_t *)(pub->info);
++
++#ifdef BCMDBUS
++	spin_lock_bh(&dhd->sdlock);
++#else
++	if (dhd_dpc_prio >= 0)
++		down(&dhd->sdsem);
++	else
++		spin_lock_bh(&dhd->sdlock);
++#endif /* !BCMDBUS */
++}
++
++void
++dhd_os_sdunlock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd;
++
++	dhd = (dhd_info_t *)(pub->info);
++
++#ifdef BCMDBUS
++	spin_unlock_bh(&dhd->sdlock);
++#else
++	if (dhd_dpc_prio >= 0)
++		up(&dhd->sdsem);
++	else
++		spin_unlock_bh(&dhd->sdlock);
++#endif /* !BCMDBUS */
++}
++
++void
++dhd_os_sdlock_txq(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd;
++
++	dhd = (dhd_info_t *)(pub->info);
++#ifdef BCMDBUS
++	spin_lock_irqsave(&dhd->txqlock, dhd->txqlock_flags);
++#else
++	spin_lock_bh(&dhd->txqlock);
++#endif /* BCMDBUS */
++}
++
++void
++dhd_os_sdunlock_txq(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd;
++
++	dhd = (dhd_info_t *)(pub->info);
++#ifdef BCMDBUS
++	spin_unlock_irqrestore(&dhd->txqlock, dhd->txqlock_flags);
++#else
++	spin_unlock_bh(&dhd->txqlock);
++#endif /* BCMDBUS */
++}
++
++void
++dhd_os_sdlock_rxq(dhd_pub_t *pub)
++{
++#if 0
++	dhd_info_t *dhd;
++
++	dhd = (dhd_info_t *)(pub->info);
++	spin_lock_bh(&dhd->rxqlock);
++#endif
++}
++
++void
++dhd_os_sdunlock_rxq(dhd_pub_t *pub)
++{
++#if 0
++	dhd_info_t *dhd;
++
++	dhd = (dhd_info_t *)(pub->info);
++	spin_unlock_bh(&dhd->rxqlock);
++#endif
++}
++
++static void
++dhd_os_rxflock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd;
++
++	dhd = (dhd_info_t *)(pub->info);
++	spin_lock_bh(&dhd->rxf_lock);
++
++}
++
++static void
++dhd_os_rxfunlock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd;
++
++	dhd = (dhd_info_t *)(pub->info);
++	spin_unlock_bh(&dhd->rxf_lock);
++}
++
++#ifdef DHDTCPACK_SUPPRESS
++unsigned long
++dhd_os_tcpacklock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd;
++	unsigned long flags = 0;
++
++	dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++#ifdef BCMSDIO
++		spin_lock_bh(&dhd->tcpack_lock);
++#else
++		spin_lock_irqsave(&dhd->tcpack_lock, flags);
++#endif /* BCMSDIO */
++	}
++
++	return flags;
++}
++
++void
++dhd_os_tcpackunlock(dhd_pub_t *pub, unsigned long flags)
++{
++	dhd_info_t *dhd;
++
++#ifdef BCMSDIO
++	BCM_REFERENCE(flags);
++#endif /* BCMSDIO */
++
++	dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++#ifdef BCMSDIO
++		spin_unlock_bh(&dhd->tcpack_lock);
++#else
++		spin_unlock_irqrestore(&dhd->tcpack_lock, flags);
++#endif /* BCMSDIO */
++	}
++}
++#endif /* DHDTCPACK_SUPPRESS */
++
++uint8* dhd_os_prealloc(dhd_pub_t *dhdpub, int section, uint size, bool kmalloc_if_fail)
++{
++	uint8* buf;
++	gfp_t flags = CAN_SLEEP() ? GFP_KERNEL: GFP_ATOMIC;
++
++	buf = (uint8*)wifi_platform_prealloc(dhdpub->info->adapter, section, size);
++	if (buf == NULL && kmalloc_if_fail)
++		buf = kmalloc(size, flags);
++
++	return buf;
++}
++
++void dhd_os_prefree(dhd_pub_t *dhdpub, void *addr, uint size)
++{
++}
++
++#if defined(WL_WIRELESS_EXT)
++struct iw_statistics *
++dhd_get_wireless_stats(struct net_device *dev)
++{
++	int res = 0;
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	if (!dhd->pub.up) {
++		return NULL;
++	}
++
++	res = wl_iw_get_wireless_stats(dev, &dhd->iw.wstats);
++
++	if (res == 0)
++		return &dhd->iw.wstats;
++	else
++		return NULL;
++}
++#endif /* defined(WL_WIRELESS_EXT) */
++
++static int
++dhd_wl_host_event(dhd_info_t *dhd, int ifidx, void *pktdata, uint16 pktlen,
++	wl_event_msg_t *event, void **data)
++{
++	int bcmerror = 0;
++#ifdef WL_CFG80211
++	unsigned long flags = 0;
++#endif /* WL_CFG80211 */
++	ASSERT(dhd != NULL);
++
++#ifdef SHOW_LOGTRACE
++	bcmerror = wl_process_host_event(&dhd->pub, &ifidx, pktdata, pktlen, event, data,
++		&dhd->event_data);
++#else
++	bcmerror = wl_process_host_event(&dhd->pub, &ifidx, pktdata, pktlen, event, data,
++		NULL);
++#endif /* SHOW_LOGTRACE */
++
++	if (bcmerror != BCME_OK)
++		return (bcmerror);
++
++#if defined(WL_EXT_IAPSTA) || defined(USE_IW)
++	wl_ext_event_send(dhd->pub.event_params, event, *data);
++#endif
++
++#ifdef WL_CFG80211
++	ASSERT(dhd->iflist[ifidx] != NULL);
++	ASSERT(dhd->iflist[ifidx]->net != NULL);
++	if (dhd->iflist[ifidx]->net) {
++		spin_lock_irqsave(&dhd->pub.up_lock, flags);
++		if (dhd->pub.up) {
++			wl_cfg80211_event(dhd->iflist[ifidx]->net, event, *data);
++		}
++		spin_unlock_irqrestore(&dhd->pub.up_lock, flags);
++	}
++#endif /* defined(WL_CFG80211) */
++
++	return (bcmerror);
++}
++
++/* send up locally generated event */
++void
++dhd_sendup_event(dhd_pub_t *dhdp, wl_event_msg_t *event, void *data)
++{
++	/* Just return from here */
++	return;
++}
++
++#ifdef LOG_INTO_TCPDUMP
++void
++dhd_sendup_log(dhd_pub_t *dhdp, void *data, int data_len)
++{
++	struct sk_buff *p, *skb;
++	uint32 pktlen;
++	int len;
++	dhd_if_t *ifp;
++	dhd_info_t *dhd;
++	uchar *skb_data;
++	int ifidx = 0;
++	struct ether_header eth;
++
++	pktlen = sizeof(eth) + data_len;
++	dhd = dhdp->info;
++
++	if ((p = PKTGET(dhdp->osh, pktlen, FALSE))) {
++		ASSERT(ISALIGNED((uintptr)PKTDATA(dhdp->osh, p), sizeof(uint32)));
++
++		bcopy(&dhdp->mac, &eth.ether_dhost, ETHER_ADDR_LEN);
++		bcopy(&dhdp->mac, &eth.ether_shost, ETHER_ADDR_LEN);
++		ETHER_TOGGLE_LOCALADDR(&eth.ether_shost);
++		eth.ether_type = hton16(ETHER_TYPE_BRCM);
++
++		bcopy((void *)&eth, PKTDATA(dhdp->osh, p), sizeof(eth));
++		bcopy(data, PKTDATA(dhdp->osh, p) + sizeof(eth), data_len);
++		skb = PKTTONATIVE(dhdp->osh, p);
++		skb_data = skb->data;
++		len = skb->len;
++
++		ifidx = dhd_ifname2idx(dhd, "wlan0");
++		ifp = dhd->iflist[ifidx];
++		if (ifp == NULL)
++			 ifp = dhd->iflist[0];
++
++		ASSERT(ifp);
++		skb->dev = ifp->net;
++		skb->protocol = eth_type_trans(skb, skb->dev);
++		skb->data = skb_data;
++		skb->len = len;
++
++		/* Strip header, count, deliver upward */
++		skb_pull(skb, ETH_HLEN);
++
++		bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE,
++			__FUNCTION__, __LINE__);
++		/* Send the packet */
++		if (in_interrupt()) {
++			netif_rx(skb);
++		} else {
++			netif_rx_ni(skb);
++		}
++	} else {
++		/* Could not allocate a sk_buf */
++		DHD_ERROR(("%s: unable to alloc sk_buf\n", __FUNCTION__));
++	}
++}
++#endif /* LOG_INTO_TCPDUMP */
++
++void dhd_wait_for_event(dhd_pub_t *dhd, bool *lockvar)
++{
++#if defined(BCMSDIO) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++	struct dhd_info *dhdinfo =  dhd->info;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++	int timeout = msecs_to_jiffies(IOCTL_RESP_TIMEOUT);
++#else
++	int timeout = (IOCTL_RESP_TIMEOUT / 1000) * HZ;
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
++
++	dhd_os_sdunlock(dhd);
++	wait_event_timeout(dhdinfo->ctrl_wait, (*lockvar == FALSE), timeout);
++	dhd_os_sdlock(dhd);
++#endif /* defined(BCMSDIO) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)) */
++	return;
++}
++
++void dhd_wait_event_wakeup(dhd_pub_t *dhd)
++{
++#if defined(BCMSDIO) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++	struct dhd_info *dhdinfo =  dhd->info;
++	if (waitqueue_active(&dhdinfo->ctrl_wait))
++		wake_up(&dhdinfo->ctrl_wait);
++#endif
++	return;
++}
++
++#if defined(BCMSDIO) || defined(BCMPCIE) || defined(BCMDBUS)
++int
++dhd_net_bus_devreset(struct net_device *dev, uint8 flag)
++{
++	int ret;
++
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	if (flag == TRUE) {
++		/* Issue wl down command before resetting the chip */
++		if (dhd_wl_ioctl_cmd(&dhd->pub, WLC_DOWN, NULL, 0, TRUE, 0) < 0) {
++			DHD_TRACE(("%s: wl down failed\n", __FUNCTION__));
++		}
++#ifdef PROP_TXSTATUS
++		if (dhd->pub.wlfc_enabled) {
++			dhd_wlfc_deinit(&dhd->pub);
++		}
++#endif /* PROP_TXSTATUS */
++#ifdef PNO_SUPPORT
++		if (dhd->pub.pno_state) {
++			dhd_pno_deinit(&dhd->pub);
++		}
++#endif
++#ifdef RTT_SUPPORT
++		if (dhd->pub.rtt_state) {
++			dhd_rtt_deinit(&dhd->pub);
++		}
++#endif /* RTT_SUPPORT */
++
++#if defined(DBG_PKT_MON) && !defined(DBG_PKT_MON_INIT_DEFAULT)
++		dhd_os_dbg_detach_pkt_monitor(&dhd->pub);
++#endif /* DBG_PKT_MON */
++	}
++
++#ifdef BCMSDIO
++	if (!flag) {
++		dhd_update_fw_nv_path(dhd);
++		/* update firmware and nvram path to sdio bus */
++		dhd_bus_update_fw_nv_path(dhd->pub.bus,
++			dhd->fw_path, dhd->nv_path, dhd->clm_path, dhd->conf_path);
++	}
++#endif /* BCMSDIO */
++
++	ret = dhd_bus_devreset(&dhd->pub, flag);
++	if (ret) {
++		DHD_ERROR(("%s: dhd_bus_devreset: %d\n", __FUNCTION__, ret));
++		return ret;
++	}
++
++	return ret;
++}
++
++#ifdef BCMSDIO
++int
++dhd_net_bus_suspend(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	return dhd_bus_suspend(&dhd->pub);
++}
++
++int
++dhd_net_bus_resume(struct net_device *dev, uint8 stage)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	return dhd_bus_resume(&dhd->pub, stage);
++}
++
++#endif /* BCMSDIO */
++#endif /* BCMSDIO || BCMPCIE || BCMDBUS */
++
++int net_os_set_suspend_disable(struct net_device *dev, int val)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret = 0;
++
++	if (dhd) {
++		ret = dhd->pub.suspend_disable_flag;
++		dhd->pub.suspend_disable_flag = val;
++	}
++	return ret;
++}
++
++int net_os_set_suspend(struct net_device *dev, int val, int force)
++{
++	int ret = 0;
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	if (dhd && dhd->pub.conf->suspend_mode == EARLY_SUSPEND) {
++		if (!val)
++			dhd_conf_set_suspend_resume(&dhd->pub, val);
++#ifdef CONFIG_MACH_UNIVERSAL7420
++#endif /* CONFIG_MACH_UNIVERSAL7420 */
++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND)
++		ret = dhd_set_suspend(val, &dhd->pub);
++#else
++		ret = dhd_suspend_resume_helper(dhd, val, force);
++#endif
++#ifdef WL_CFG80211
++		wl_cfg80211_update_power_mode(dev);
++#endif
++		if (val)
++			dhd_conf_set_suspend_resume(&dhd->pub, val);
++	}
++	return ret;
++}
++
++int net_os_set_suspend_bcn_li_dtim(struct net_device *dev, int val)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	if (dhd)
++		dhd->pub.suspend_bcn_li_dtim = val;
++
++	return 0;
++}
++
++int net_os_set_max_dtim_enable(struct net_device *dev, int val)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	if (dhd) {
++		DHD_ERROR(("%s: use MAX bcn_li_dtim in suspend %s\n",
++			__FUNCTION__, (val ? "Enable" : "Disable")));
++		if (val) {
++			dhd->pub.max_dtim_enable = TRUE;
++		} else {
++			dhd->pub.max_dtim_enable = FALSE;
++		}
++	} else {
++		return -1;
++	}
++
++	return 0;
++}
++
++#ifdef PKT_FILTER_SUPPORT
++int net_os_rxfilter_add_remove(struct net_device *dev, int add_remove, int num)
++{
++	int ret = 0;
++
++#ifndef GAN_LITE_NAT_KEEPALIVE_FILTER
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	if (!dhd_master_mode)
++		add_remove = !add_remove;
++	DHD_ERROR(("%s: add_remove = %d, num = %d\n", __FUNCTION__, add_remove, num));
++	if (!dhd || (num == DHD_UNICAST_FILTER_NUM)) {
++		return 0;
++	}
++
++
++	if (num >= dhd->pub.pktfilter_count) {
++		return -EINVAL;
++	}
++
++	ret = dhd_packet_filter_add_remove(&dhd->pub, add_remove, num);
++#endif /* !GAN_LITE_NAT_KEEPALIVE_FILTER */
++
++	return ret;
++}
++
++int dhd_os_enable_packet_filter(dhd_pub_t *dhdp, int val)
++
++{
++	int ret = 0;
++
++	/* Packet filtering is set only if we still in early-suspend and
++	 * we need either to turn it ON or turn it OFF
++	 * We can always turn it OFF in case of early-suspend, but we turn it
++	 * back ON only if suspend_disable_flag was not set
++	*/
++	if (dhdp && dhdp->up) {
++		if (dhdp->in_suspend) {
++			if (!val || (val && !dhdp->suspend_disable_flag))
++				dhd_enable_packet_filter(val, dhdp);
++		}
++	}
++	return ret;
++}
++
++/* function to enable/disable packet for Network device */
++int net_os_enable_packet_filter(struct net_device *dev, int val)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	DHD_ERROR(("%s: val = %d\n", __FUNCTION__, val));
++	return dhd_os_enable_packet_filter(&dhd->pub, val);
++}
++#endif /* PKT_FILTER_SUPPORT */
++
++int
++dhd_dev_init_ioctl(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret;
++
++	if ((ret = dhd_sync_with_dongle(&dhd->pub)) < 0)
++		goto done;
++
++done:
++	return ret;
++}
++
++int
++dhd_dev_get_feature_set(struct net_device *dev)
++{
++	dhd_info_t *ptr = *(dhd_info_t **)netdev_priv(dev);
++	dhd_pub_t *dhd = (&ptr->pub);
++	int feature_set = 0;
++
++	if (FW_SUPPORTED(dhd, sta))
++		feature_set |= WIFI_FEATURE_INFRA;
++	if (FW_SUPPORTED(dhd, dualband))
++		feature_set |= WIFI_FEATURE_INFRA_5G;
++	if (FW_SUPPORTED(dhd, p2p))
++		feature_set |= WIFI_FEATURE_P2P;
++	if (dhd->op_mode & DHD_FLAG_HOSTAP_MODE)
++		feature_set |= WIFI_FEATURE_SOFT_AP;
++	if (FW_SUPPORTED(dhd, tdls))
++		feature_set |= WIFI_FEATURE_TDLS;
++	if (FW_SUPPORTED(dhd, vsdb))
++		feature_set |= WIFI_FEATURE_TDLS_OFFCHANNEL;
++	if (FW_SUPPORTED(dhd, nan)) {
++		feature_set |= WIFI_FEATURE_NAN;
++		/* NAN is essentail for d2d rtt */
++		if (FW_SUPPORTED(dhd, rttd2d))
++			feature_set |= WIFI_FEATURE_D2D_RTT;
++	}
++#ifdef RTT_SUPPORT
++	if (dhd->rtt_supported) {
++		feature_set |= WIFI_FEATURE_D2D_RTT;
++		feature_set |= WIFI_FEATURE_D2AP_RTT;
++	}
++#endif /* RTT_SUPPORT */
++#ifdef LINKSTAT_SUPPORT
++	feature_set |= WIFI_FEATURE_LINKSTAT;
++#endif /* LINKSTAT_SUPPORT */
++
++#ifdef PNO_SUPPORT
++	if (dhd_is_pno_supported(dhd)) {
++		feature_set |= WIFI_FEATURE_PNO;
++#ifdef GSCAN_SUPPORT
++		/* terence 20171115: remove to get GTS PASS
++		 * com.google.android.gts.wifi.WifiHostTest#testWifiScannerBatchTimestamp
++		 */
++//		feature_set |= WIFI_FEATURE_GSCAN;
++//		feature_set |= WIFI_FEATURE_HAL_EPNO;
++#endif /* GSCAN_SUPPORT */
++	}
++#endif /* PNO_SUPPORT */
++#ifdef RSSI_MONITOR_SUPPORT
++	if (FW_SUPPORTED(dhd, rssi_mon)) {
++		feature_set |= WIFI_FEATURE_RSSI_MONITOR;
++	}
++#endif /* RSSI_MONITOR_SUPPORT */
++#ifdef WL11U
++	feature_set |= WIFI_FEATURE_HOTSPOT;
++#endif /* WL11U */
++#ifdef NDO_CONFIG_SUPPORT
++	feature_set |= WIFI_FEATURE_CONFIG_NDO;
++#endif /* NDO_CONFIG_SUPPORT */
++#ifdef KEEP_ALIVE
++	feature_set |= WIFI_FEATURE_MKEEP_ALIVE;
++#endif /* KEEP_ALIVE */
++
++	return feature_set;
++}
++
++int
++dhd_dev_get_feature_set_matrix(struct net_device *dev, int num)
++{
++	int feature_set_full;
++	int ret = 0;
++
++	feature_set_full = dhd_dev_get_feature_set(dev);
++
++	/* Common feature set for all interface */
++	ret = (feature_set_full & WIFI_FEATURE_INFRA) |
++		(feature_set_full & WIFI_FEATURE_INFRA_5G) |
++		(feature_set_full & WIFI_FEATURE_D2D_RTT) |
++		(feature_set_full & WIFI_FEATURE_D2AP_RTT) |
++		(feature_set_full & WIFI_FEATURE_RSSI_MONITOR) |
++		(feature_set_full & WIFI_FEATURE_EPR);
++
++	/* Specific feature group for each interface */
++	switch (num) {
++	case 0:
++		ret |= (feature_set_full & WIFI_FEATURE_P2P) |
++			/* Not supported yet */
++			/* (feature_set_full & WIFI_FEATURE_NAN) | */
++			(feature_set_full & WIFI_FEATURE_TDLS) |
++			(feature_set_full & WIFI_FEATURE_PNO) |
++			(feature_set_full & WIFI_FEATURE_HAL_EPNO) |
++			(feature_set_full & WIFI_FEATURE_BATCH_SCAN) |
++			(feature_set_full & WIFI_FEATURE_GSCAN) |
++			(feature_set_full & WIFI_FEATURE_HOTSPOT) |
++			(feature_set_full & WIFI_FEATURE_ADDITIONAL_STA);
++		break;
++
++	case 1:
++		ret |= (feature_set_full & WIFI_FEATURE_P2P);
++		/* Not yet verified NAN with P2P */
++		/* (feature_set_full & WIFI_FEATURE_NAN) | */
++		break;
++
++	case 2:
++		ret |= (feature_set_full & WIFI_FEATURE_NAN) |
++			(feature_set_full & WIFI_FEATURE_TDLS) |
++			(feature_set_full & WIFI_FEATURE_TDLS_OFFCHANNEL);
++		break;
++
++	default:
++		ret = WIFI_FEATURE_INVALID;
++		DHD_ERROR(("%s: Out of index(%d) for get feature set\n", __FUNCTION__, num));
++		break;
++	}
++
++	return ret;
++}
++
++#ifdef CUSTOM_FORCE_NODFS_FLAG
++int
++dhd_dev_set_nodfs(struct net_device *dev, u32 nodfs)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	if (nodfs)
++		dhd->pub.dhd_cflags |= WLAN_PLAT_NODFS_FLAG;
++	else
++		dhd->pub.dhd_cflags &= ~WLAN_PLAT_NODFS_FLAG;
++	dhd->pub.force_country_change = TRUE;
++	return 0;
++}
++#endif /* CUSTOM_FORCE_NODFS_FLAG */
++
++#ifdef NDO_CONFIG_SUPPORT
++int
++dhd_dev_ndo_cfg(struct net_device *dev, u8 enable)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	dhd_pub_t *dhdp = &dhd->pub;
++	int ret = 0;
++
++	if (enable) {
++		/* enable ND offload feature (will be enabled in FW on suspend) */
++		dhdp->ndo_enable = TRUE;
++
++		/* Update changes of anycast address & DAD failed address */
++		ret = dhd_dev_ndo_update_inet6addr(dev);
++		if ((ret < 0) && (ret != BCME_NORESOURCE)) {
++			DHD_ERROR(("%s: failed to update host ip addr: %d\n", __FUNCTION__, ret));
++			return ret;
++		}
++	} else {
++		/* disable ND offload feature */
++		dhdp->ndo_enable = FALSE;
++
++		/* disable ND offload in FW */
++		ret = dhd_ndo_enable(dhdp, 0);
++		if (ret < 0) {
++			DHD_ERROR(("%s: failed to disable NDO: %d\n", __FUNCTION__, ret));
++		}
++	}
++	return ret;
++}
++
++/* #pragma used as a WAR to fix build failure,
++* ignore dropping of 'const' qualifier in 'list_entry' macro
++* this pragma disables the warning only for the following function
++*/
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++
++static int
++dhd_dev_ndo_get_valid_inet6addr_count(struct inet6_dev *inet6)
++{
++	struct inet6_ifaddr *ifa;
++	struct ifacaddr6 *acaddr = NULL;
++	int addr_count = 0;
++
++	/* lock */
++	read_lock_bh(&inet6->lock);
++
++	/* Count valid unicast address */
++	list_for_each_entry(ifa, &inet6->addr_list, if_list) {
++		if ((ifa->flags & IFA_F_DADFAILED) == 0) {
++			addr_count++;
++		}
++	}
++
++	/* Count anycast address */
++	acaddr = inet6->ac_list;
++	while (acaddr) {
++		addr_count++;
++		acaddr = acaddr->aca_next;
++	}
++
++	/* unlock */
++	read_unlock_bh(&inet6->lock);
++
++	return addr_count;
++}
++
++int
++dhd_dev_ndo_update_inet6addr(struct net_device *dev)
++{
++	dhd_info_t *dhd;
++	dhd_pub_t *dhdp;
++	struct inet6_dev *inet6;
++	struct inet6_ifaddr *ifa;
++	struct ifacaddr6 *acaddr = NULL;
++	struct in6_addr *ipv6_addr = NULL;
++	int cnt, i;
++	int ret = BCME_OK;
++
++	/*
++	 * this function evaulates host ip address in struct inet6_dev
++	 * unicast addr in inet6_dev->addr_list
++	 * anycast addr in inet6_dev->ac_list
++	 * while evaluating inet6_dev, read_lock_bh() is required to prevent
++	 * access on null(freed) pointer.
++	 */
++
++	if (dev) {
++		inet6 = dev->ip6_ptr;
++		if (!inet6) {
++			DHD_ERROR(("%s: Invalid inet6_dev\n", __FUNCTION__));
++			return BCME_ERROR;
++		}
++
++		dhd = DHD_DEV_INFO(dev);
++		if (!dhd) {
++			DHD_ERROR(("%s: Invalid dhd_info\n", __FUNCTION__));
++			return BCME_ERROR;
++		}
++		dhdp = &dhd->pub;
++
++		if (dhd_net2idx(dhd, dev) != 0) {
++			DHD_ERROR(("%s: Not primary interface\n", __FUNCTION__));
++			return BCME_ERROR;
++		}
++	} else {
++		DHD_ERROR(("%s: Invalid net_device\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	/* Check host IP overflow */
++	cnt = dhd_dev_ndo_get_valid_inet6addr_count(inet6);
++	if (cnt > dhdp->ndo_max_host_ip) {
++		if (!dhdp->ndo_host_ip_overflow) {
++			dhdp->ndo_host_ip_overflow = TRUE;
++			/* Disable ND offload in FW */
++			DHD_INFO(("%s: Host IP overflow, disable NDO\n", __FUNCTION__));
++			ret = dhd_ndo_enable(dhdp, 0);
++		}
++
++		return ret;
++	}
++
++	/*
++	 * Allocate ipv6 addr buffer to store addresses to be added/removed.
++	 * driver need to lock inet6_dev while accessing structure. but, driver
++	 * cannot use ioctl while inet6_dev locked since it requires scheduling
++	 * hence, copy addresses to the buffer and do ioctl after unlock.
++	 */
++	ipv6_addr = (struct in6_addr *)MALLOC(dhdp->osh,
++		sizeof(struct in6_addr) * dhdp->ndo_max_host_ip);
++	if (!ipv6_addr) {
++		DHD_ERROR(("%s: failed to alloc ipv6 addr buffer\n", __FUNCTION__));
++		return BCME_NOMEM;
++	}
++
++	/* Find DAD failed unicast address to be removed */
++	cnt = 0;
++	read_lock_bh(&inet6->lock);
++	list_for_each_entry(ifa, &inet6->addr_list, if_list) {
++		/* DAD failed unicast address */
++		if ((ifa->flags & IFA_F_DADFAILED) &&
++			(cnt < dhdp->ndo_max_host_ip)) {
++				memcpy(&ipv6_addr[cnt], &ifa->addr, sizeof(struct in6_addr));
++				cnt++;
++		}
++	}
++	read_unlock_bh(&inet6->lock);
++
++	/* Remove DAD failed unicast address */
++	for (i = 0; i < cnt; i++) {
++		DHD_INFO(("%s: Remove DAD failed addr\n", __FUNCTION__));
++		ret = dhd_ndo_remove_ip_by_addr(dhdp, (char *)&ipv6_addr[i], 0);
++		if (ret < 0) {
++			goto done;
++		}
++	}
++
++	/* Remove all anycast address */
++	ret = dhd_ndo_remove_ip_by_type(dhdp, WL_ND_IPV6_ADDR_TYPE_ANYCAST, 0);
++	if (ret < 0) {
++		goto done;
++	}
++
++	/*
++	 * if ND offload was disabled due to host ip overflow,
++	 * attempt to add valid unicast address.
++	 */
++	if (dhdp->ndo_host_ip_overflow) {
++		/* Find valid unicast address */
++		cnt = 0;
++		read_lock_bh(&inet6->lock);
++		list_for_each_entry(ifa, &inet6->addr_list, if_list) {
++			/* valid unicast address */
++			if (!(ifa->flags & IFA_F_DADFAILED) &&
++				(cnt < dhdp->ndo_max_host_ip)) {
++					memcpy(&ipv6_addr[cnt], &ifa->addr,
++						sizeof(struct in6_addr));
++					cnt++;
++			}
++		}
++		read_unlock_bh(&inet6->lock);
++
++		/* Add valid unicast address */
++		for (i = 0; i < cnt; i++) {
++			ret = dhd_ndo_add_ip_with_type(dhdp,
++				(char *)&ipv6_addr[i], WL_ND_IPV6_ADDR_TYPE_UNICAST, 0);
++			if (ret < 0) {
++				goto done;
++			}
++		}
++	}
++
++	/* Find anycast address */
++	cnt = 0;
++	read_lock_bh(&inet6->lock);
++	acaddr = inet6->ac_list;
++	while (acaddr) {
++		if (cnt < dhdp->ndo_max_host_ip) {
++			memcpy(&ipv6_addr[cnt], &acaddr->aca_addr, sizeof(struct in6_addr));
++			cnt++;
++		}
++		acaddr = acaddr->aca_next;
++	}
++	read_unlock_bh(&inet6->lock);
++
++	/* Add anycast address */
++	for (i = 0; i < cnt; i++) {
++		ret = dhd_ndo_add_ip_with_type(dhdp,
++			(char *)&ipv6_addr[i], WL_ND_IPV6_ADDR_TYPE_ANYCAST, 0);
++		if (ret < 0) {
++			goto done;
++		}
++	}
++
++	/* Now All host IP addr were added successfully */
++	if (dhdp->ndo_host_ip_overflow) {
++		dhdp->ndo_host_ip_overflow = FALSE;
++		if (dhdp->in_suspend) {
++			/* drvier is in (early) suspend state, need to enable ND offload in FW */
++			DHD_INFO(("%s: enable NDO\n", __FUNCTION__));
++			ret = dhd_ndo_enable(dhdp, 1);
++		}
++	}
++
++done:
++	if (ipv6_addr) {
++		MFREE(dhdp->osh, ipv6_addr, sizeof(struct in6_addr) * dhdp->ndo_max_host_ip);
++	}
++
++	return ret;
++}
++#pragma GCC diagnostic pop
++
++#endif /* NDO_CONFIG_SUPPORT */
++
++#ifdef PNO_SUPPORT
++/* Linux wrapper to call common dhd_pno_stop_for_ssid */
++int
++dhd_dev_pno_stop_for_ssid(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	return (dhd_pno_stop_for_ssid(&dhd->pub));
++}
++
++/* Linux wrapper to call common dhd_pno_set_for_ssid */
++int
++dhd_dev_pno_set_for_ssid(struct net_device *dev, wlc_ssid_ext_t* ssids_local, int nssid,
++	uint16  scan_fr, int pno_repeat, int pno_freq_expo_max, uint16 *channel_list, int nchan)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	return (dhd_pno_set_for_ssid(&dhd->pub, ssids_local, nssid, scan_fr,
++		pno_repeat, pno_freq_expo_max, channel_list, nchan));
++}
++
++/* Linux wrapper to call common dhd_pno_enable */
++int
++dhd_dev_pno_enable(struct net_device *dev, int enable)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	return (dhd_pno_enable(&dhd->pub, enable));
++}
++
++/* Linux wrapper to call common dhd_pno_set_for_hotlist */
++int
++dhd_dev_pno_set_for_hotlist(struct net_device *dev, wl_pfn_bssid_t *p_pfn_bssid,
++	struct dhd_pno_hotlist_params *hotlist_params)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	return (dhd_pno_set_for_hotlist(&dhd->pub, p_pfn_bssid, hotlist_params));
++}
++/* Linux wrapper to call common dhd_dev_pno_stop_for_batch */
++int
++dhd_dev_pno_stop_for_batch(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	return (dhd_pno_stop_for_batch(&dhd->pub));
++}
++
++/* Linux wrapper to call common dhd_dev_pno_set_for_batch */
++int
++dhd_dev_pno_set_for_batch(struct net_device *dev, struct dhd_pno_batch_params *batch_params)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	return (dhd_pno_set_for_batch(&dhd->pub, batch_params));
++}
++
++/* Linux wrapper to call common dhd_dev_pno_get_for_batch */
++int
++dhd_dev_pno_get_for_batch(struct net_device *dev, char *buf, int bufsize)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	return (dhd_pno_get_for_batch(&dhd->pub, buf, bufsize, PNO_STATUS_NORMAL));
++}
++#endif /* PNO_SUPPORT */
++
++#if defined(PNO_SUPPORT)
++#ifdef GSCAN_SUPPORT
++bool
++dhd_dev_is_legacy_pno_enabled(struct net_device *dev)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_is_legacy_pno_enabled(&dhd->pub));
++}
++
++int
++dhd_dev_set_epno(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	if (!dhd) {
++		return BCME_ERROR;
++	}
++	return dhd_pno_set_epno(&dhd->pub);
++}
++int
++dhd_dev_flush_fw_epno(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	if (!dhd) {
++		return BCME_ERROR;
++	}
++	return dhd_pno_flush_fw_epno(&dhd->pub);
++}
++
++/* Linux wrapper to call common dhd_pno_set_cfg_gscan */
++int
++dhd_dev_pno_set_cfg_gscan(struct net_device *dev, dhd_pno_gscan_cmd_cfg_t type,
++ void *buf, bool flush)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_pno_set_cfg_gscan(&dhd->pub, type, buf, flush));
++}
++
++/* Linux wrapper to call common dhd_wait_batch_results_complete */
++int
++dhd_dev_wait_batch_results_complete(struct net_device *dev)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_wait_batch_results_complete(&dhd->pub));
++}
++
++/* Linux wrapper to call common dhd_pno_lock_batch_results */
++int
++dhd_dev_pno_lock_access_batch_results(struct net_device *dev)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_pno_lock_batch_results(&dhd->pub));
++}
++/* Linux wrapper to call common dhd_pno_unlock_batch_results */
++void
++dhd_dev_pno_unlock_access_batch_results(struct net_device *dev)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_pno_unlock_batch_results(&dhd->pub));
++}
++
++/* Linux wrapper to call common dhd_pno_initiate_gscan_request */
++int
++dhd_dev_pno_run_gscan(struct net_device *dev, bool run, bool flush)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_pno_initiate_gscan_request(&dhd->pub, run, flush));
++}
++
++/* Linux wrapper to call common dhd_pno_enable_full_scan_result */
++int
++dhd_dev_pno_enable_full_scan_result(struct net_device *dev, bool real_time_flag)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_pno_enable_full_scan_result(&dhd->pub, real_time_flag));
++}
++
++/* Linux wrapper to call common dhd_handle_hotlist_scan_evt */
++void *
++dhd_dev_hotlist_scan_event(struct net_device *dev,
++      const void  *data, int *send_evt_bytes, hotlist_type_t type)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_handle_hotlist_scan_evt(&dhd->pub, data, send_evt_bytes, type));
++}
++
++/* Linux wrapper to call common dhd_process_full_gscan_result */
++void *
++dhd_dev_process_full_gscan_result(struct net_device *dev,
++const void  *data, uint32 len, int *send_evt_bytes)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_process_full_gscan_result(&dhd->pub, data, len, send_evt_bytes));
++}
++
++void
++dhd_dev_gscan_hotlist_cache_cleanup(struct net_device *dev, hotlist_type_t type)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	dhd_gscan_hotlist_cache_cleanup(&dhd->pub, type);
++
++	return;
++}
++
++int
++dhd_dev_gscan_batch_cache_cleanup(struct net_device *dev)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_gscan_batch_cache_cleanup(&dhd->pub));
++}
++
++/* Linux wrapper to call common dhd_retreive_batch_scan_results */
++int
++dhd_dev_retrieve_batch_scan(struct net_device *dev)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_retreive_batch_scan_results(&dhd->pub));
++}
++
++/* Linux wrapper to call common dhd_pno_process_epno_result */
++void * dhd_dev_process_epno_result(struct net_device *dev,
++	const void  *data, uint32 event, int *send_evt_bytes)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_pno_process_epno_result(&dhd->pub, data, event, send_evt_bytes));
++}
++
++int
++dhd_dev_set_lazy_roam_cfg(struct net_device *dev,
++             wlc_roam_exp_params_t *roam_param)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	wl_roam_exp_cfg_t roam_exp_cfg;
++	int err;
++
++	if (!roam_param) {
++		return BCME_BADARG;
++	}
++
++	DHD_ERROR(("a_band_boost_thr %d a_band_penalty_thr %d\n",
++	      roam_param->a_band_boost_threshold, roam_param->a_band_penalty_threshold));
++	DHD_ERROR(("a_band_boost_factor %d a_band_penalty_factor %d cur_bssid_boost %d\n",
++	      roam_param->a_band_boost_factor, roam_param->a_band_penalty_factor,
++	      roam_param->cur_bssid_boost));
++	DHD_ERROR(("alert_roam_trigger_thr %d a_band_max_boost %d\n",
++	      roam_param->alert_roam_trigger_threshold, roam_param->a_band_max_boost));
++
++	memcpy(&roam_exp_cfg.params, roam_param, sizeof(*roam_param));
++	roam_exp_cfg.version = ROAM_EXP_CFG_VERSION;
++	roam_exp_cfg.flags = ROAM_EXP_CFG_PRESENT;
++	if (dhd->pub.lazy_roam_enable) {
++		roam_exp_cfg.flags |= ROAM_EXP_ENABLE_FLAG;
++	}
++	err = dhd_iovar(&dhd->pub, 0, "roam_exp_params",
++			(char *)&roam_exp_cfg, sizeof(roam_exp_cfg), NULL, 0,
++			TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : Failed to execute roam_exp_params %d\n", __FUNCTION__, err));
++	}
++	return err;
++}
++
++int
++dhd_dev_lazy_roam_enable(struct net_device *dev, uint32 enable)
++{
++	int err;
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	wl_roam_exp_cfg_t roam_exp_cfg;
++
++	memset(&roam_exp_cfg, 0, sizeof(roam_exp_cfg));
++	roam_exp_cfg.version = ROAM_EXP_CFG_VERSION;
++	if (enable) {
++		roam_exp_cfg.flags = ROAM_EXP_ENABLE_FLAG;
++	}
++
++	err = dhd_iovar(&dhd->pub, 0, "roam_exp_params",
++			(char *)&roam_exp_cfg, sizeof(roam_exp_cfg), NULL, 0,
++			TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : Failed to execute roam_exp_params %d\n", __FUNCTION__, err));
++	} else {
++		dhd->pub.lazy_roam_enable = (enable != 0);
++	}
++	return err;
++}
++
++int
++dhd_dev_set_lazy_roam_bssid_pref(struct net_device *dev,
++       wl_bssid_pref_cfg_t *bssid_pref, uint32 flush)
++{
++	int err;
++	int len;
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	bssid_pref->version = BSSID_PREF_LIST_VERSION;
++	/* By default programming bssid pref flushes out old values */
++	bssid_pref->flags = (flush && !bssid_pref->count) ? ROAM_EXP_CLEAR_BSSID_PREF: 0;
++	len = sizeof(wl_bssid_pref_cfg_t);
++	len += (bssid_pref->count - 1) * sizeof(wl_bssid_pref_list_t);
++	err = dhd_iovar(&(dhd->pub), 0, "roam_exp_bssid_pref", (char *)bssid_pref,
++		len, NULL, 0, TRUE);
++	if (err != BCME_OK) {
++		DHD_ERROR(("%s : Failed to execute roam_exp_bssid_pref %d\n", __FUNCTION__, err));
++	}
++	return err;
++}
++
++int
++dhd_dev_set_blacklist_bssid(struct net_device *dev, maclist_t *blacklist,
++    uint32 len, uint32 flush)
++{
++	int err;
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	int macmode;
++
++	if (blacklist) {
++		err = dhd_wl_ioctl_cmd(&(dhd->pub), WLC_SET_MACLIST, (char *)blacklist,
++				len, TRUE, 0);
++		if (err != BCME_OK) {
++			DHD_ERROR(("%s : WLC_SET_MACLIST failed %d\n", __FUNCTION__, err));
++			return err;
++		}
++	}
++	/* By default programming blacklist flushes out old values */
++	macmode = (flush && !blacklist) ? WLC_MACMODE_DISABLED : WLC_MACMODE_DENY;
++	err = dhd_wl_ioctl_cmd(&(dhd->pub), WLC_SET_MACMODE, (char *)&macmode,
++	              sizeof(macmode), TRUE, 0);
++	if (err != BCME_OK) {
++		DHD_ERROR(("%s : WLC_SET_MACMODE failed %d\n", __FUNCTION__, err));
++	}
++	return err;
++}
++
++int
++dhd_dev_set_whitelist_ssid(struct net_device *dev, wl_ssid_whitelist_t *ssid_whitelist,
++    uint32 len, uint32 flush)
++{
++	int err;
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	wl_ssid_whitelist_t whitelist_ssid_flush;
++
++	if (!ssid_whitelist) {
++		if (flush) {
++			ssid_whitelist = &whitelist_ssid_flush;
++			ssid_whitelist->ssid_count = 0;
++		} else {
++			DHD_ERROR(("%s : Nothing to do here\n", __FUNCTION__));
++			return BCME_BADARG;
++		}
++	}
++	ssid_whitelist->version = SSID_WHITELIST_VERSION;
++	ssid_whitelist->flags = flush ? ROAM_EXP_CLEAR_SSID_WHITELIST : 0;
++	err = dhd_iovar(&(dhd->pub), 0, "roam_exp_ssid_whitelist", (char *)ssid_whitelist,
++			len, NULL, 0, TRUE);
++	if (err != BCME_OK) {
++		DHD_ERROR(("%s : Failed to execute roam_exp_bssid_pref %d\n", __FUNCTION__, err));
++	}
++	return err;
++}
++#endif /* GSCAN_SUPPORT */
++
++#if defined(GSCAN_SUPPORT) || defined(DHD_GET_VALID_CHANNELS)
++/* Linux wrapper to call common dhd_pno_get_gscan */
++void *
++dhd_dev_pno_get_gscan(struct net_device *dev, dhd_pno_gscan_cmd_cfg_t type,
++	void *info, uint32 *len)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_pno_get_gscan(&dhd->pub, type, info, len));
++}
++#endif /* GSCAN_SUPPORT || DHD_GET_VALID_CHANNELS */
++#endif 
++
++#ifdef  RSSI_MONITOR_SUPPORT
++int
++dhd_dev_set_rssi_monitor_cfg(struct net_device *dev, int start,
++             int8 max_rssi, int8 min_rssi)
++{
++	int err;
++	wl_rssi_monitor_cfg_t rssi_monitor;
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	rssi_monitor.version = RSSI_MONITOR_VERSION;
++	rssi_monitor.max_rssi = max_rssi;
++	rssi_monitor.min_rssi = min_rssi;
++	rssi_monitor.flags = start ? 0: RSSI_MONITOR_STOP;
++	err = dhd_iovar(&(dhd->pub), 0, "rssi_monitor", (char *)&rssi_monitor,
++		sizeof(rssi_monitor), NULL, 0, TRUE);
++	if (err < 0 && err != BCME_UNSUPPORTED) {
++		DHD_ERROR(("%s : Failed to execute rssi_monitor %d\n", __FUNCTION__, err));
++	}
++	return err;
++}
++#endif /* RSSI_MONITOR_SUPPORT */
++
++#ifdef DHDTCPACK_SUPPRESS
++int dhd_dev_set_tcpack_sup_mode_cfg(struct net_device *dev, uint8 enable)
++{
++	int err;
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	err = dhd_tcpack_suppress_set(&(dhd->pub), enable);
++	if (err != BCME_OK) {
++		DHD_ERROR(("%s : Failed to execute rssi_monitor %d\n", __FUNCTION__, err));
++	}
++	return err;
++}
++#endif /* DHDTCPACK_SUPPRESS */
++
++int
++dhd_dev_cfg_rand_mac_oui(struct net_device *dev, uint8 *oui)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	dhd_pub_t *dhdp = &dhd->pub;
++
++	if (!dhdp || !oui) {
++		DHD_ERROR(("NULL POINTER : %s\n",
++			__FUNCTION__));
++		return BCME_ERROR;
++	}
++	if (ETHER_ISMULTI(oui)) {
++		DHD_ERROR(("Expected unicast OUI\n"));
++		return BCME_ERROR;
++	} else {
++		uint8 *rand_mac_oui = dhdp->rand_mac_oui;
++		memcpy(rand_mac_oui, oui, DOT11_OUI_LEN);
++		DHD_ERROR(("Random MAC OUI to be used - %02x:%02x:%02x\n", rand_mac_oui[0],
++		    rand_mac_oui[1], rand_mac_oui[2]));
++	}
++	return BCME_OK;
++}
++
++int
++dhd_set_rand_mac_oui(dhd_pub_t *dhd)
++{
++	int err;
++	wl_pfn_macaddr_cfg_t wl_cfg;
++	uint8 *rand_mac_oui = dhd->rand_mac_oui;
++
++	memset(&wl_cfg.macaddr, 0, ETHER_ADDR_LEN);
++	memcpy(&wl_cfg.macaddr, rand_mac_oui, DOT11_OUI_LEN);
++	wl_cfg.version = WL_PFN_MACADDR_CFG_VER;
++	if (ETHER_ISNULLADDR(&wl_cfg.macaddr)) {
++		wl_cfg.flags = 0;
++	} else {
++		wl_cfg.flags = (WL_PFN_MAC_OUI_ONLY_MASK | WL_PFN_SET_MAC_UNASSOC_MASK);
++	}
++
++	DHD_ERROR(("Setting rand mac oui to FW - %02x:%02x:%02x\n", rand_mac_oui[0],
++		rand_mac_oui[1], rand_mac_oui[2]));
++
++	err = dhd_iovar(dhd, 0, "pfn_macaddr", (char *)&wl_cfg, sizeof(wl_cfg), NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfn_macaddr %d\n", __FUNCTION__, err));
++	}
++	return err;
++}
++
++#ifdef RTT_SUPPORT
++#ifdef WL_CFG80211
++/* Linux wrapper to call common dhd_pno_set_cfg_gscan */
++int
++dhd_dev_rtt_set_cfg(struct net_device *dev, void *buf)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_rtt_set_cfg(&dhd->pub, buf));
++}
++
++int
++dhd_dev_rtt_cancel_cfg(struct net_device *dev, struct ether_addr *mac_list, int mac_cnt)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_rtt_stop(&dhd->pub, mac_list, mac_cnt));
++}
++
++int
++dhd_dev_rtt_register_noti_callback(struct net_device *dev, void *ctx, dhd_rtt_compl_noti_fn noti_fn)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_rtt_register_noti_callback(&dhd->pub, ctx, noti_fn));
++}
++
++int
++dhd_dev_rtt_unregister_noti_callback(struct net_device *dev, dhd_rtt_compl_noti_fn noti_fn)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_rtt_unregister_noti_callback(&dhd->pub, noti_fn));
++}
++
++int
++dhd_dev_rtt_capability(struct net_device *dev, rtt_capabilities_t *capa)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_rtt_capability(&dhd->pub, capa));
++}
++
++int
++dhd_dev_rtt_avail_channel(struct net_device *dev, wifi_channel_info *channel_info)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	return (dhd_rtt_avail_channel(&dhd->pub, channel_info));
++}
++
++int
++dhd_dev_rtt_enable_responder(struct net_device *dev, wifi_channel_info *channel_info)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	return (dhd_rtt_enable_responder(&dhd->pub, channel_info));
++}
++
++int dhd_dev_rtt_cancel_responder(struct net_device *dev)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	return (dhd_rtt_cancel_responder(&dhd->pub));
++}
++#endif /* WL_CFG80211 */
++#endif /* RTT_SUPPORT */
++
++#ifdef KEEP_ALIVE
++#define KA_TEMP_BUF_SIZE 512
++#define KA_FRAME_SIZE 300
++
++int
++dhd_dev_start_mkeep_alive(dhd_pub_t *dhd_pub, uint8 mkeep_alive_id, uint8 *ip_pkt,
++	uint16 ip_pkt_len, uint8* src_mac, uint8* dst_mac, uint32 period_msec)
++{
++	const int		ETHERTYPE_LEN = 2;
++	char			*pbuf = NULL;
++	const char		*str;
++	wl_mkeep_alive_pkt_t	mkeep_alive_pkt;
++	wl_mkeep_alive_pkt_t	*mkeep_alive_pktp = NULL;
++	int			buf_len = 0;
++	int			str_len = 0;
++	int			res = BCME_ERROR;
++	int			len_bytes = 0;
++	int			i = 0;
++
++	/* ether frame to have both max IP pkt (256 bytes) and ether header */
++	char			*pmac_frame = NULL;
++	char			*pmac_frame_begin = NULL;
++
++	/*
++	 * The mkeep_alive packet is for STA interface only; if the bss is configured as AP,
++	 * dongle shall reject a mkeep_alive request.
++	 */
++	if (!dhd_support_sta_mode(dhd_pub))
++		return res;
++
++	DHD_TRACE(("%s execution\n", __FUNCTION__));
++
++	if ((pbuf = kzalloc(KA_TEMP_BUF_SIZE, GFP_KERNEL)) == NULL) {
++		DHD_ERROR(("failed to allocate buf with size %d\n", KA_TEMP_BUF_SIZE));
++		res = BCME_NOMEM;
++		return res;
++	}
++
++	if ((pmac_frame = kzalloc(KA_FRAME_SIZE, GFP_KERNEL)) == NULL) {
++		DHD_ERROR(("failed to allocate mac_frame with size %d\n", KA_FRAME_SIZE));
++		res = BCME_NOMEM;
++		goto exit;
++	}
++	pmac_frame_begin = pmac_frame;
++
++	/*
++	 * Get current mkeep-alive status.
++	 */
++	res = dhd_iovar(dhd_pub, 0, "mkeep_alive", &mkeep_alive_id, sizeof(mkeep_alive_id), pbuf,
++			KA_TEMP_BUF_SIZE, FALSE);
++	if (res < 0) {
++		DHD_ERROR(("%s: Get mkeep_alive failed (error=%d)\n", __FUNCTION__, res));
++		goto exit;
++	} else {
++		/* Check available ID whether it is occupied */
++		mkeep_alive_pktp = (wl_mkeep_alive_pkt_t *) pbuf;
++		if (dtoh32(mkeep_alive_pktp->period_msec != 0)) {
++			DHD_ERROR(("%s: Get mkeep_alive failed, ID %u is in use.\n",
++				__FUNCTION__, mkeep_alive_id));
++
++			/* Current occupied ID info */
++			DHD_ERROR(("%s: mkeep_alive\n", __FUNCTION__));
++			DHD_ERROR(("   Id    : %d\n"
++				"   Period: %d msec\n"
++				"   Length: %d\n"
++				"   Packet: 0x",
++				mkeep_alive_pktp->keep_alive_id,
++				dtoh32(mkeep_alive_pktp->period_msec),
++				dtoh16(mkeep_alive_pktp->len_bytes)));
++
++			for (i = 0; i < mkeep_alive_pktp->len_bytes; i++) {
++				DHD_ERROR(("%02x", mkeep_alive_pktp->data[i]));
++			}
++			DHD_ERROR(("\n"));
++
++			res = BCME_NOTFOUND;
++			goto exit;
++		}
++	}
++
++	/* Request the specified ID */
++	memset(&mkeep_alive_pkt, 0, sizeof(wl_mkeep_alive_pkt_t));
++	memset(pbuf, 0, KA_TEMP_BUF_SIZE);
++	str = "mkeep_alive";
++	str_len = strlen(str);
++	strncpy(pbuf, str, str_len);
++	pbuf[str_len] = '\0';
++
++	mkeep_alive_pktp = (wl_mkeep_alive_pkt_t *) (pbuf + str_len + 1);
++	mkeep_alive_pkt.period_msec = htod32(period_msec);
++	buf_len = str_len + 1;
++	mkeep_alive_pkt.version = htod16(WL_MKEEP_ALIVE_VERSION);
++	mkeep_alive_pkt.length = htod16(WL_MKEEP_ALIVE_FIXED_LEN);
++
++	/* ID assigned */
++	mkeep_alive_pkt.keep_alive_id = mkeep_alive_id;
++
++	buf_len += WL_MKEEP_ALIVE_FIXED_LEN;
++
++	/*
++	 * Build up Ethernet Frame
++	 */
++
++	/* Mapping dest mac addr */
++	memcpy(pmac_frame, dst_mac, ETHER_ADDR_LEN);
++	pmac_frame += ETHER_ADDR_LEN;
++
++	/* Mapping src mac addr */
++	memcpy(pmac_frame, src_mac, ETHER_ADDR_LEN);
++	pmac_frame += ETHER_ADDR_LEN;
++
++	/* Mapping Ethernet type (ETHERTYPE_IP: 0x0800) */
++	*(pmac_frame++) = 0x08;
++	*(pmac_frame++) = 0x00;
++
++	/* Mapping IP pkt */
++	memcpy(pmac_frame, ip_pkt, ip_pkt_len);
++	pmac_frame += ip_pkt_len;
++
++	/*
++	 * Length of ether frame (assume to be all hexa bytes)
++	 *     = src mac + dst mac + ether type + ip pkt len
++	 */
++	len_bytes = ETHER_ADDR_LEN*2 + ETHERTYPE_LEN + ip_pkt_len;
++	memcpy(mkeep_alive_pktp->data, pmac_frame_begin, len_bytes);
++	buf_len += len_bytes;
++	mkeep_alive_pkt.len_bytes = htod16(len_bytes);
++
++	/*
++	 * Keep-alive attributes are set in local variable (mkeep_alive_pkt), and
++	 * then memcpy'ed into buffer (mkeep_alive_pktp) since there is no
++	 * guarantee that the buffer is properly aligned.
++	 */
++	memcpy((char *)mkeep_alive_pktp, &mkeep_alive_pkt, WL_MKEEP_ALIVE_FIXED_LEN);
++
++	res = dhd_wl_ioctl_cmd(dhd_pub, WLC_SET_VAR, pbuf, buf_len, TRUE, 0);
++exit:
++	kfree(pmac_frame_begin);
++	kfree(pbuf);
++	return res;
++}
++
++int
++dhd_dev_stop_mkeep_alive(dhd_pub_t *dhd_pub, uint8 mkeep_alive_id)
++{
++	char			*pbuf;
++	wl_mkeep_alive_pkt_t	mkeep_alive_pkt;
++	wl_mkeep_alive_pkt_t	*mkeep_alive_pktp;
++	int			res = BCME_ERROR;
++	int			i;
++
++	/*
++	 * The mkeep_alive packet is for STA interface only; if the bss is configured as AP,
++	 * dongle shall reject a mkeep_alive request.
++	 */
++	if (!dhd_support_sta_mode(dhd_pub))
++		return res;
++
++	DHD_TRACE(("%s execution\n", __FUNCTION__));
++
++	/*
++	 * Get current mkeep-alive status. Skip ID 0 which is being used for NULL pkt.
++	 */
++	if ((pbuf = kmalloc(KA_TEMP_BUF_SIZE, GFP_KERNEL)) == NULL) {
++		DHD_ERROR(("failed to allocate buf with size %d\n", KA_TEMP_BUF_SIZE));
++		return res;
++	}
++
++	res = dhd_iovar(dhd_pub, 0, "mkeep_alive", &mkeep_alive_id,
++			sizeof(mkeep_alive_id), pbuf, KA_TEMP_BUF_SIZE, FALSE);
++	if (res < 0) {
++		DHD_ERROR(("%s: Get mkeep_alive failed (error=%d)\n", __FUNCTION__, res));
++		goto exit;
++	} else {
++		/* Check occupied ID */
++		mkeep_alive_pktp = (wl_mkeep_alive_pkt_t *) pbuf;
++		DHD_INFO(("%s: mkeep_alive\n", __FUNCTION__));
++		DHD_INFO(("   Id    : %d\n"
++			"   Period: %d msec\n"
++			"   Length: %d\n"
++			"   Packet: 0x",
++			mkeep_alive_pktp->keep_alive_id,
++			dtoh32(mkeep_alive_pktp->period_msec),
++			dtoh16(mkeep_alive_pktp->len_bytes)));
++
++		for (i = 0; i < mkeep_alive_pktp->len_bytes; i++) {
++			DHD_INFO(("%02x", mkeep_alive_pktp->data[i]));
++		}
++		DHD_INFO(("\n"));
++	}
++
++	/* Make it stop if available */
++	if (dtoh32(mkeep_alive_pktp->period_msec != 0)) {
++		DHD_INFO(("stop mkeep_alive on ID %d\n", mkeep_alive_id));
++		memset(&mkeep_alive_pkt, 0, sizeof(wl_mkeep_alive_pkt_t));
++
++		mkeep_alive_pkt.period_msec = 0;
++		mkeep_alive_pkt.version = htod16(WL_MKEEP_ALIVE_VERSION);
++		mkeep_alive_pkt.length = htod16(WL_MKEEP_ALIVE_FIXED_LEN);
++		mkeep_alive_pkt.keep_alive_id = mkeep_alive_id;
++
++		res = dhd_iovar(dhd_pub, 0, "mkeep_alive",
++				(char *)&mkeep_alive_pkt,
++				WL_MKEEP_ALIVE_FIXED_LEN, NULL, 0, TRUE);
++	} else {
++		DHD_ERROR(("%s: ID %u does not exist.\n", __FUNCTION__, mkeep_alive_id));
++		res = BCME_NOTFOUND;
++	}
++exit:
++	kfree(pbuf);
++	return res;
++}
++#endif /* KEEP_ALIVE */
++
++#if defined(PKT_FILTER_SUPPORT) && defined(APF)
++static void _dhd_apf_lock_local(dhd_info_t *dhd)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	if (dhd) {
++		mutex_lock(&dhd->dhd_apf_mutex);
++	}
++#endif
++}
++
++static void _dhd_apf_unlock_local(dhd_info_t *dhd)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	if (dhd) {
++		mutex_unlock(&dhd->dhd_apf_mutex);
++	}
++#endif
++}
++
++static int
++__dhd_apf_add_filter(struct net_device *ndev, uint32 filter_id,
++	u8* program, uint32 program_len)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(ndev);
++	dhd_pub_t *dhdp = &dhd->pub;
++	wl_pkt_filter_t * pkt_filterp;
++	wl_apf_program_t *apf_program;
++	char *buf;
++	u32 cmd_len, buf_len;
++	int ifidx, ret;
++	gfp_t kflags;
++	char cmd[] = "pkt_filter_add";
++
++	ifidx = dhd_net2idx(dhd, ndev);
++	if (ifidx == DHD_BAD_IF) {
++		DHD_ERROR(("%s: bad ifidx\n", __FUNCTION__));
++		return -ENODEV;
++	}
++
++	cmd_len = sizeof(cmd);
++
++	/* Check if the program_len is more than the expected len
++	 * and if the program is NULL return from here.
++	 */
++	if ((program_len > WL_APF_PROGRAM_MAX_SIZE) || (program == NULL)) {
++		DHD_ERROR(("%s Invalid program_len: %d, program: %pK\n",
++				__FUNCTION__, program_len, program));
++		return -EINVAL;
++	}
++	buf_len = cmd_len + WL_PKT_FILTER_FIXED_LEN +
++		WL_APF_PROGRAM_FIXED_LEN + program_len;
++
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	buf = kzalloc(buf_len, kflags);
++	if (unlikely(!buf)) {
++		DHD_ERROR(("%s: MALLOC failure, %d bytes\n", __FUNCTION__, buf_len));
++		return -ENOMEM;
++	}
++
++	memcpy(buf, cmd, cmd_len);
++
++	pkt_filterp = (wl_pkt_filter_t *) (buf + cmd_len);
++	pkt_filterp->id = htod32(filter_id);
++	pkt_filterp->negate_match = htod32(FALSE);
++	pkt_filterp->type = htod32(WL_PKT_FILTER_TYPE_APF_MATCH);
++
++	apf_program = &pkt_filterp->u.apf_program;
++	apf_program->version = htod16(WL_APF_INTERNAL_VERSION);
++	apf_program->instr_len = htod16(program_len);
++	memcpy(apf_program->instrs, program, program_len);
++
++	ret = dhd_wl_ioctl_cmd(dhdp, WLC_SET_VAR, buf, buf_len, TRUE, ifidx);
++	if (unlikely(ret)) {
++		DHD_ERROR(("%s: failed to add APF filter, id=%d, ret=%d\n",
++			__FUNCTION__, filter_id, ret));
++	}
++
++	if (buf) {
++		kfree(buf);
++	}
++	return ret;
++}
++
++static int
++__dhd_apf_config_filter(struct net_device *ndev, uint32 filter_id,
++	uint32 mode, uint32 enable)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(ndev);
++	dhd_pub_t *dhdp = &dhd->pub;
++	wl_pkt_filter_enable_t * pkt_filterp;
++	char *buf;
++	u32 cmd_len, buf_len;
++	int ifidx, ret;
++	gfp_t kflags;
++	char cmd[] = "pkt_filter_enable";
++
++	ifidx = dhd_net2idx(dhd, ndev);
++	if (ifidx == DHD_BAD_IF) {
++		DHD_ERROR(("%s: bad ifidx\n", __FUNCTION__));
++		return -ENODEV;
++	}
++
++	cmd_len = sizeof(cmd);
++	buf_len = cmd_len + sizeof(*pkt_filterp);
++
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	buf = kzalloc(buf_len, kflags);
++	if (unlikely(!buf)) {
++		DHD_ERROR(("%s: MALLOC failure, %d bytes\n", __FUNCTION__, buf_len));
++		return -ENOMEM;
++	}
++
++	memcpy(buf, cmd, cmd_len);
++
++	pkt_filterp = (wl_pkt_filter_enable_t *) (buf + cmd_len);
++	pkt_filterp->id = htod32(filter_id);
++	pkt_filterp->enable = htod32(enable);
++
++	ret = dhd_wl_ioctl_cmd(dhdp, WLC_SET_VAR, buf, buf_len, TRUE, ifidx);
++	if (unlikely(ret)) {
++		DHD_ERROR(("%s: failed to enable APF filter, id=%d, ret=%d\n",
++			__FUNCTION__, filter_id, ret));
++		goto exit;
++	}
++
++	ret = dhd_wl_ioctl_set_intiovar(dhdp, "pkt_filter_mode", dhd_master_mode,
++		WLC_SET_VAR, TRUE, ifidx);
++	if (unlikely(ret)) {
++		DHD_ERROR(("%s: failed to set APF filter mode, id=%d, ret=%d\n",
++			__FUNCTION__, filter_id, ret));
++	}
++
++exit:
++	if (buf) {
++		kfree(buf);
++	}
++	return ret;
++}
++
++static int
++__dhd_apf_delete_filter(struct net_device *ndev, uint32 filter_id)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(ndev);
++	dhd_pub_t *dhdp = &dhd->pub;
++	int ifidx, ret;
++
++	ifidx = dhd_net2idx(dhd, ndev);
++	if (ifidx == DHD_BAD_IF) {
++		DHD_ERROR(("%s: bad ifidx\n", __FUNCTION__));
++		return -ENODEV;
++	}
++
++	ret = dhd_wl_ioctl_set_intiovar(dhdp, "pkt_filter_delete",
++		htod32(filter_id), WLC_SET_VAR, TRUE, ifidx);
++	if (unlikely(ret)) {
++		DHD_ERROR(("%s: failed to delete APF filter, id=%d, ret=%d\n",
++			__FUNCTION__, filter_id, ret));
++	}
++
++	return ret;
++}
++
++void dhd_apf_lock(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	_dhd_apf_lock_local(dhd);
++}
++
++void dhd_apf_unlock(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	_dhd_apf_unlock_local(dhd);
++}
++
++int
++dhd_dev_apf_get_version(struct net_device *ndev, uint32 *version)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(ndev);
++	dhd_pub_t *dhdp = &dhd->pub;
++	int ifidx, ret;
++
++	if (!FW_SUPPORTED(dhdp, apf)) {
++		DHD_ERROR(("%s: firmware doesn't support APF\n", __FUNCTION__));
++
++		/*
++		 * Notify Android framework that APF is not supported by setting
++		 * version as zero.
++		 */
++		*version = 0;
++		return BCME_OK;
++	}
++
++	ifidx = dhd_net2idx(dhd, ndev);
++	if (ifidx == DHD_BAD_IF) {
++		DHD_ERROR(("%s: bad ifidx\n", __FUNCTION__));
++		return -ENODEV;
++	}
++
++	ret = dhd_wl_ioctl_get_intiovar(dhdp, "apf_ver", version,
++		WLC_GET_VAR, FALSE, ifidx);
++	if (unlikely(ret)) {
++		DHD_ERROR(("%s: failed to get APF version, ret=%d\n",
++			__FUNCTION__, ret));
++	}
++
++	return ret;
++}
++
++int
++dhd_dev_apf_get_max_len(struct net_device *ndev, uint32 *max_len)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(ndev);
++	dhd_pub_t *dhdp = &dhd->pub;
++	int ifidx, ret;
++
++	if (!FW_SUPPORTED(dhdp, apf)) {
++		DHD_ERROR(("%s: firmware doesn't support APF\n", __FUNCTION__));
++		*max_len = 0;
++		return BCME_OK;
++	}
++
++	ifidx = dhd_net2idx(dhd, ndev);
++	if (ifidx == DHD_BAD_IF) {
++		DHD_ERROR(("%s bad ifidx\n", __FUNCTION__));
++		return -ENODEV;
++	}
++
++	ret = dhd_wl_ioctl_get_intiovar(dhdp, "apf_size_limit", max_len,
++		WLC_GET_VAR, FALSE, ifidx);
++	if (unlikely(ret)) {
++		DHD_ERROR(("%s: failed to get APF size limit, ret=%d\n",
++			__FUNCTION__, ret));
++	}
++
++	return ret;
++}
++
++int
++dhd_dev_apf_add_filter(struct net_device *ndev, u8* program,
++	uint32 program_len)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(ndev);
++	dhd_pub_t *dhdp = &dhd->pub;
++	int ret;
++
++	DHD_APF_LOCK(ndev);
++
++	/* delete, if filter already exists */
++	if (dhdp->apf_set) {
++		ret = __dhd_apf_delete_filter(ndev, PKT_FILTER_APF_ID);
++		if (unlikely(ret)) {
++			goto exit;
++		}
++		dhdp->apf_set = FALSE;
++	}
++
++	ret = __dhd_apf_add_filter(ndev, PKT_FILTER_APF_ID, program, program_len);
++	if (ret) {
++		goto exit;
++	}
++	dhdp->apf_set = TRUE;
++
++	if (dhdp->in_suspend && dhdp->apf_set && !(dhdp->op_mode & DHD_FLAG_HOSTAP_MODE)) {
++		/* Driver is still in (early) suspend state, enable APF filter back */
++		ret = __dhd_apf_config_filter(ndev, PKT_FILTER_APF_ID,
++			PKT_FILTER_MODE_FORWARD_ON_MATCH, TRUE);
++	}
++exit:
++	DHD_APF_UNLOCK(ndev);
++
++	return ret;
++}
++
++int
++dhd_dev_apf_enable_filter(struct net_device *ndev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(ndev);
++	dhd_pub_t *dhdp = &dhd->pub;
++	int ret = 0;
++
++	DHD_APF_LOCK(ndev);
++
++	if (dhdp->apf_set && !(dhdp->op_mode & DHD_FLAG_HOSTAP_MODE)) {
++		ret = __dhd_apf_config_filter(ndev, PKT_FILTER_APF_ID,
++			PKT_FILTER_MODE_FORWARD_ON_MATCH, TRUE);
++	}
++
++	DHD_APF_UNLOCK(ndev);
++
++	return ret;
++}
++
++int
++dhd_dev_apf_disable_filter(struct net_device *ndev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(ndev);
++	dhd_pub_t *dhdp = &dhd->pub;
++	int ret = 0;
++
++	DHD_APF_LOCK(ndev);
++
++	if (dhdp->apf_set) {
++		ret = __dhd_apf_config_filter(ndev, PKT_FILTER_APF_ID,
++			PKT_FILTER_MODE_FORWARD_ON_MATCH, FALSE);
++	}
++
++	DHD_APF_UNLOCK(ndev);
++
++	return ret;
++}
++
++int
++dhd_dev_apf_delete_filter(struct net_device *ndev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(ndev);
++	dhd_pub_t *dhdp = &dhd->pub;
++	int ret = 0;
++
++	DHD_APF_LOCK(ndev);
++
++	if (dhdp->apf_set) {
++		ret = __dhd_apf_delete_filter(ndev, PKT_FILTER_APF_ID);
++		if (!ret) {
++			dhdp->apf_set = FALSE;
++		}
++	}
++
++	DHD_APF_UNLOCK(ndev);
++
++	return ret;
++}
++#endif /* PKT_FILTER_SUPPORT && APF */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++static void dhd_hang_process(void *dhd_info, void *event_info, u8 event)
++{
++	dhd_info_t *dhd;
++	struct net_device *dev;
++
++	dhd = (dhd_info_t *)dhd_info;
++	if (!dhd || !dhd->iflist[0])
++		return;
++	dev = dhd->iflist[0]->net;
++
++	if (dev) {
++		/*
++		 * For HW2, dev_close need to be done to recover
++		 * from upper layer after hang. For Interposer skip
++		 * dev_close so that dhd iovars can be used to take
++		 * socramdump after crash, also skip for HW4 as
++		 * handling of hang event is different
++		 */
++#if !defined(CUSTOMER_HW2_INTERPOSER)
++		rtnl_lock();
++		dev_close(dev);
++		rtnl_unlock();
++#endif 
++#if defined(WL_WIRELESS_EXT)
++		wl_iw_send_priv_event(dev, "HANG");
++#endif
++#if defined(WL_CFG80211)
++		wl_cfg80211_hang(dev, WLAN_REASON_UNSPECIFIED);
++#endif
++	}
++}
++
++#ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
++extern dhd_pub_t *link_recovery;
++void dhd_host_recover_link(void)
++{
++	DHD_ERROR(("****** %s ******\n", __FUNCTION__));
++	link_recovery->hang_reason = HANG_REASON_PCIE_LINK_DOWN;
++	dhd_bus_set_linkdown(link_recovery, TRUE);
++	dhd_os_send_hang_message(link_recovery);
++}
++EXPORT_SYMBOL(dhd_host_recover_link);
++#endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
++
++int dhd_os_send_hang_message(dhd_pub_t *dhdp)
++{
++	int ret = 0;
++	if (dhdp) {
++#if defined(DHD_HANG_SEND_UP_TEST)
++		if (dhdp->req_hang_type) {
++			DHD_ERROR(("%s, Clear HANG test request 0x%x\n",
++				__FUNCTION__, dhdp->req_hang_type));
++			dhdp->req_hang_type = 0;
++		}
++#endif /* DHD_HANG_SEND_UP_TEST */
++
++		if (!dhdp->hang_was_sent) {
++#if defined(CONFIG_BCM_DETECT_CONSECUTIVE_HANG)
++			dhdp->hang_counts++;
++			if (dhdp->hang_counts >= MAX_CONSECUTIVE_HANG_COUNTS) {
++				DHD_ERROR(("%s, Consecutive hang from Dongle :%u\n",
++					__func__, dhdp->hang_counts));
++				BUG_ON(1);
++			}
++#endif /* CONFIG_BCM_DETECT_CONSECUTIVE_HANG */
++#ifdef DHD_DEBUG_UART
++			/* If PCIe lane has broken, execute the debug uart application
++			 * to gether a ramdump data from dongle via uart
++			 */
++			if (!dhdp->info->duart_execute) {
++				dhd_deferred_schedule_work(dhdp->info->dhd_deferred_wq,
++					(void *)dhdp, DHD_WQ_WORK_DEBUG_UART_DUMP,
++					dhd_debug_uart_exec_rd, DHD_WQ_WORK_PRIORITY_HIGH);
++			}
++#endif	/* DHD_DEBUG_UART */
++			dhdp->hang_was_sent = 1;
++#ifdef BT_OVER_SDIO
++			dhdp->is_bt_recovery_required = TRUE;
++#endif
++			dhd_deferred_schedule_work(dhdp->info->dhd_deferred_wq, (void *)dhdp,
++				DHD_WQ_WORK_HANG_MSG, dhd_hang_process, DHD_WQ_WORK_PRIORITY_HIGH);
++			DHD_ERROR(("%s: Event HANG send up due to  re=%d te=%d s=%d\n", __FUNCTION__,
++				dhdp->rxcnt_timeout, dhdp->txcnt_timeout, dhdp->busstate));
++		}
++	}
++	return ret;
++}
++
++int net_os_send_hang_message(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret = 0;
++
++	if (dhd) {
++		/* Report FW problem when enabled */
++		if (dhd->pub.hang_report) {
++#ifdef BT_OVER_SDIO
++			if (netif_running(dev)) {
++#endif /* BT_OVER_SDIO */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++				ret = dhd_os_send_hang_message(&dhd->pub);
++#else
++				ret = wl_cfg80211_hang(dev, WLAN_REASON_UNSPECIFIED);
++#endif
++#ifdef BT_OVER_SDIO
++			}
++			DHD_ERROR(("%s: HANG -> Reset BT\n", __FUNCTION__));
++			bcmsdh_btsdio_process_dhd_hang_notification(!netif_running(dev));
++#endif /* BT_OVER_SDIO */
++		} else {
++			DHD_ERROR(("%s: FW HANG ignored (for testing purpose) and not sent up\n",
++				__FUNCTION__));
++		}
++	}
++	return ret;
++}
++
++int net_os_send_hang_message_reason(struct net_device *dev, const char *string_num)
++{
++	dhd_info_t *dhd = NULL;
++	dhd_pub_t *dhdp = NULL;
++	int reason;
++
++	dhd = DHD_DEV_INFO(dev);
++	if (dhd) {
++		dhdp = &dhd->pub;
++	}
++
++	if (!dhd || !dhdp) {
++		return 0;
++	}
++
++	reason = bcm_strtoul(string_num, NULL, 0);
++	DHD_INFO(("%s: Enter, reason=0x%x\n", __FUNCTION__, reason));
++
++	if ((reason <= HANG_REASON_MASK) || (reason >= HANG_REASON_MAX)) {
++		reason = 0;
++	}
++
++	dhdp->hang_reason = reason;
++
++	return net_os_send_hang_message(dev);
++}
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27) && OEM_ANDROID */
++
++
++int dhd_net_wifi_platform_set_power(struct net_device *dev, bool on, unsigned long delay_msec)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	return wifi_platform_set_power(dhd->adapter, on, delay_msec);
++}
++
++bool dhd_force_country_change(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	if (dhd && dhd->pub.up)
++		return dhd->pub.force_country_change;
++	return FALSE;
++}
++
++void dhd_get_customized_country_code(struct net_device *dev, char *country_iso_code,
++	wl_country_t *cspec)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++#if defined(DHD_BLOB_EXISTENCE_CHECK)
++	if (!dhd->pub.is_blob)
++#endif /* DHD_BLOB_EXISTENCE_CHECK */
++	{
++#if defined(CUSTOM_COUNTRY_CODE)
++		get_customized_country_code(dhd->adapter, country_iso_code, cspec,
++			dhd->pub.dhd_cflags);
++#else
++		get_customized_country_code(dhd->adapter, country_iso_code, cspec);
++#endif /* CUSTOM_COUNTRY_CODE */
++	}
++
++	BCM_REFERENCE(dhd);
++}
++
++void dhd_bus_country_set(struct net_device *dev, wl_country_t *cspec, bool notify)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++#ifdef WL_CFG80211
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++#endif
++
++	if (dhd && dhd->pub.up) {
++		memcpy(&dhd->pub.dhd_cspec, cspec, sizeof(wl_country_t));
++#ifdef WL_CFG80211
++		wl_update_wiphybands(cfg, notify);
++#endif
++	}
++}
++
++void dhd_bus_band_set(struct net_device *dev, uint band)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++#ifdef WL_CFG80211
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++#endif
++	if (dhd && dhd->pub.up) {
++#ifdef WL_CFG80211
++		wl_update_wiphybands(cfg, true);
++#endif
++	}
++}
++
++int dhd_net_set_fw_path(struct net_device *dev, char *fw)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	if (!fw || fw[0] == '\0')
++		return -EINVAL;
++
++	strncpy(dhd->fw_path, fw, sizeof(dhd->fw_path) - 1);
++	dhd->fw_path[sizeof(dhd->fw_path)-1] = '\0';
++
++#if defined(SOFTAP)
++	if (strstr(fw, "apsta") != NULL) {
++		DHD_INFO(("GOT APSTA FIRMWARE\n"));
++		ap_fw_loaded = TRUE;
++	} else {
++		DHD_INFO(("GOT STA FIRMWARE\n"));
++		ap_fw_loaded = FALSE;
++	}
++#endif 
++	return 0;
++}
++
++void dhd_net_if_lock(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	dhd_net_if_lock_local(dhd);
++}
++
++void dhd_net_if_unlock(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	dhd_net_if_unlock_local(dhd);
++}
++
++static void dhd_net_if_lock_local(dhd_info_t *dhd)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	if (dhd)
++		mutex_lock(&dhd->dhd_net_if_mutex);
++#endif
++}
++
++static void dhd_net_if_unlock_local(dhd_info_t *dhd)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	if (dhd)
++		mutex_unlock(&dhd->dhd_net_if_mutex);
++#endif
++}
++
++static void dhd_suspend_lock(dhd_pub_t *pub)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	if (dhd)
++		mutex_lock(&dhd->dhd_suspend_mutex);
++#endif
++}
++
++static void dhd_suspend_unlock(dhd_pub_t *pub)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	if (dhd)
++		mutex_unlock(&dhd->dhd_suspend_mutex);
++#endif
++}
++
++unsigned long dhd_os_general_spin_lock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags = 0;
++
++	if (dhd)
++		spin_lock_irqsave(&dhd->dhd_lock, flags);
++
++	return flags;
++}
++
++void dhd_os_general_spin_unlock(dhd_pub_t *pub, unsigned long flags)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd)
++		spin_unlock_irqrestore(&dhd->dhd_lock, flags);
++}
++
++/* Linux specific multipurpose spinlock API */
++void *
++dhd_os_spin_lock_init(osl_t *osh)
++{
++	/* Adding 4 bytes since the sizeof(spinlock_t) could be 0 */
++	/* if CONFIG_SMP and CONFIG_DEBUG_SPINLOCK are not defined */
++	/* and this results in kernel asserts in internal builds */
++	spinlock_t * lock = MALLOC(osh, sizeof(spinlock_t) + 4);
++	if (lock)
++		spin_lock_init(lock);
++	return ((void *)lock);
++}
++void
++dhd_os_spin_lock_deinit(osl_t *osh, void *lock)
++{
++	if (lock)
++		MFREE(osh, lock, sizeof(spinlock_t) + 4);
++}
++unsigned long
++dhd_os_spin_lock(void *lock)
++{
++	unsigned long flags = 0;
++
++	if (lock)
++		spin_lock_irqsave((spinlock_t *)lock, flags);
++
++	return flags;
++}
++void
++dhd_os_spin_unlock(void *lock, unsigned long flags)
++{
++	if (lock)
++		spin_unlock_irqrestore((spinlock_t *)lock, flags);
++}
++
++static int
++dhd_get_pend_8021x_cnt(dhd_info_t *dhd)
++{
++	return (atomic_read(&dhd->pend_8021x_cnt));
++}
++
++#define MAX_WAIT_FOR_8021X_TX	100
++
++int
++dhd_wait_pend8021x(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int timeout = msecs_to_jiffies(10);
++	int ntimes = MAX_WAIT_FOR_8021X_TX;
++	int pend = dhd_get_pend_8021x_cnt(dhd);
++
++	while (ntimes && pend) {
++		if (pend) {
++			set_current_state(TASK_INTERRUPTIBLE);
++			DHD_PERIM_UNLOCK(&dhd->pub);
++			schedule_timeout(timeout);
++			DHD_PERIM_LOCK(&dhd->pub);
++			set_current_state(TASK_RUNNING);
++			ntimes--;
++		}
++		pend = dhd_get_pend_8021x_cnt(dhd);
++	}
++	if (ntimes == 0)
++	{
++		atomic_set(&dhd->pend_8021x_cnt, 0);
++		DHD_ERROR(("%s: TIMEOUT\n", __FUNCTION__));
++	}
++	return pend;
++}
++
++#if defined(DHD_DEBUG)
++int write_file(const char * file_name, uint32 flags, uint8 *buf, int size)
++{
++	int ret = 0;
++	struct file *fp = NULL;
++	mm_segment_t old_fs;
++	loff_t pos = 0;
++	/* change to KERNEL_DS address limit */
++	old_fs = get_fs();
++	set_fs(KERNEL_DS);
++
++	/* open file to write */
++	fp = filp_open(file_name, flags, 0664);
++	if (IS_ERR(fp)) {
++		DHD_ERROR(("open file error, err = %ld\n", PTR_ERR(fp)));
++		ret = -1;
++		goto exit;
++	}
++
++	/* Write buf to file */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++	ret = kernel_write(fp, buf, size, &pos);
++#else
++	ret = vfs_write(fp, buf, size, &pos);
++#endif
++	if (ret < 0) {
++		DHD_ERROR(("write file error, err = %d\n", ret));
++		goto exit;
++	}
++
++	/* Sync file from filesystem to physical media */
++	ret = vfs_fsync(fp, 0);
++	if (ret < 0) {
++		DHD_ERROR(("sync file error, error = %d\n", ret));
++		goto exit;
++	}
++	ret = BCME_OK;
++
++exit:
++	/* close file before return */
++	if (!IS_ERR(fp))
++		filp_close(fp, current->files);
++
++	/* restore previous address limit */
++	set_fs(old_fs);
++
++	return ret;
++}
++#endif 
++
++#ifdef DHD_DEBUG
++static void
++dhd_convert_memdump_type_to_str(uint32 type, char *buf)
++{
++	char *type_str = NULL;
++
++	switch (type) {
++		case DUMP_TYPE_RESUMED_ON_TIMEOUT:
++			type_str = "resumed_on_timeout";
++			break;
++		case DUMP_TYPE_D3_ACK_TIMEOUT:
++			type_str = "D3_ACK_timeout";
++			break;
++		case DUMP_TYPE_DONGLE_TRAP:
++			type_str = "Dongle_Trap";
++			break;
++		case DUMP_TYPE_MEMORY_CORRUPTION:
++			type_str = "Memory_Corruption";
++			break;
++		case DUMP_TYPE_PKTID_AUDIT_FAILURE:
++			type_str = "PKTID_AUDIT_Fail";
++			break;
++		case DUMP_TYPE_PKTID_INVALID:
++			type_str = "PKTID_INVALID";
++			break;
++		case DUMP_TYPE_SCAN_TIMEOUT:
++			type_str = "SCAN_timeout";
++			break;
++		case DUMP_TYPE_JOIN_TIMEOUT:
++			type_str = "JOIN_timeout";
++			break;
++		case DUMP_TYPE_SCAN_BUSY:
++			type_str = "SCAN_Busy";
++			break;
++		case DUMP_TYPE_BY_SYSDUMP:
++			type_str = "BY_SYSDUMP";
++			break;
++		case DUMP_TYPE_BY_LIVELOCK:
++			type_str = "BY_LIVELOCK";
++			break;
++		case DUMP_TYPE_AP_LINKUP_FAILURE:
++			type_str = "BY_AP_LINK_FAILURE";
++			break;
++		case DUMP_TYPE_AP_ABNORMAL_ACCESS:
++			type_str = "INVALID_ACCESS";
++			break;
++		case DUMP_TYPE_CFG_VENDOR_TRIGGERED:
++			type_str = "CFG_VENDOR_TRIGGERED";
++			break;
++		case DUMP_TYPE_RESUMED_ON_TIMEOUT_RX:
++			type_str = "ERROR_RX_TIMED_OUT";
++			break;
++		case DUMP_TYPE_RESUMED_ON_TIMEOUT_TX:
++			type_str = "ERROR_TX_TIMED_OUT";
++			break;
++		case DUMP_TYPE_RESUMED_ON_INVALID_RING_RDWR:
++			type_str = "BY_INVALID_RING_RDWR";
++			break;
++		case DUMP_TYPE_DONGLE_HOST_EVENT:
++			type_str = "BY_DONGLE_HOST_EVENT";
++			break;
++		case DUMP_TYPE_TRANS_ID_MISMATCH:
++			type_str = "BY_TRANS_ID_MISMATCH";
++			break;
++		case DUMP_TYPE_HANG_ON_IFACE_OP_FAIL:
++			type_str = "HANG_IFACE_OP_FAIL";
++			break;
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++		case DUMP_TYPE_READ_SHM_FAIL:
++			type_str = "READ_SHM_FAIL";
++			break;
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++		default:
++			type_str = "Unknown_type";
++			break;
++	}
++
++	strncpy(buf, type_str, strlen(type_str));
++	buf[strlen(type_str)] = 0;
++}
++
++int
++write_dump_to_file(dhd_pub_t *dhd, uint8 *buf, int size, char *fname)
++{
++	int ret = 0;
++	char memdump_path[128];
++	char memdump_type[32];
++	struct osl_timespec curtime;
++	uint32 file_mode;
++
++	/* Init file name */
++	memset(memdump_path, 0, sizeof(memdump_path));
++	memset(memdump_type, 0, sizeof(memdump_type));
++	osl_do_gettimeofday(&curtime);
++	dhd_convert_memdump_type_to_str(dhd->memdump_type, memdump_type);
++#ifdef CUSTOMER_HW4_DEBUG
++	snprintf(memdump_path, sizeof(memdump_path), "%s%s_%s_%ld.%ld",
++		DHD_COMMON_DUMP_PATH, fname, memdump_type,
++		(unsigned long)curtime.tv_sec, (unsigned long)curtime.tv_usec);
++	file_mode = O_CREAT | O_WRONLY | O_SYNC;
++#elif defined(CUSTOMER_HW2)
++	snprintf(memdump_path, sizeof(memdump_path), "%s%s_%s_%ld.%ld",
++		"/data/misc/wifi/", fname, memdump_type,
++		(unsigned long)curtime.tv_sec, (unsigned long)curtime.tv_usec);
++	file_mode = O_CREAT | O_WRONLY | O_SYNC;
++#elif (defined(BOARD_PANDA) || defined(__ARM_ARCH_7A__))
++	snprintf(memdump_path, sizeof(memdump_path), "%s%s_%s_%ld.%ld",
++		"/data/misc/wifi/", fname, memdump_type,
++		(unsigned long)curtime.tv_sec, (unsigned long)curtime.tv_usec);
++	file_mode = O_CREAT | O_WRONLY;
++#else
++	snprintf(memdump_path, sizeof(memdump_path), "%s%s_%s_%ld.%ld",
++		"/installmedia/", fname, memdump_type,
++		(unsigned long)curtime.tv_sec, (unsigned long)curtime.tv_usec);
++	/* Extra flags O_DIRECT and O_SYNC are required for Brix Android, as we are
++	 * calling BUG_ON immediately after collecting the socram dump.
++	 * So the file write operation should directly write the contents into the
++	 * file instead of caching it. O_TRUNC flag ensures that file will be re-written
++	 * instead of appending.
++	 */
++	file_mode = O_CREAT | O_WRONLY | O_SYNC;
++	{
++		struct file *fp = filp_open(memdump_path, file_mode, 0664);
++		/* Check if it is live Brix image having /installmedia, else use /data */
++		if (IS_ERR(fp)) {
++			DHD_ERROR(("open file %s, try /data/\n", memdump_path));
++			snprintf(memdump_path, sizeof(memdump_path), "%s%s_%s_%ld.%ld",
++				"/data/", fname, memdump_type,
++				(unsigned long)curtime.tv_sec, (unsigned long)curtime.tv_usec);
++		} else {
++			filp_close(fp, NULL);
++		}
++	}
++#endif /* CUSTOMER_HW4_DEBUG */
++
++	/* print SOCRAM dump file path */
++	DHD_ERROR(("%s: file_path = %s\n", __FUNCTION__, memdump_path));
++
++	/* Write file */
++	ret = write_file(memdump_path, file_mode, buf, size);
++
++	return ret;
++}
++#endif /* DHD_DEBUG */
++
++int dhd_os_wake_lock_timeout(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++	int ret = 0;
++
++	if (dhd && (dhd->dhd_state & DHD_ATTACH_STATE_WAKELOCKS_INIT)) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++		ret = dhd->wakelock_rx_timeout_enable > dhd->wakelock_ctrl_timeout_enable ?
++			dhd->wakelock_rx_timeout_enable : dhd->wakelock_ctrl_timeout_enable;
++#ifdef CONFIG_HAS_WAKELOCK
++		if (dhd->wakelock_rx_timeout_enable)
++			wake_lock_timeout(&dhd->wl_rxwake,
++				msecs_to_jiffies(dhd->wakelock_rx_timeout_enable));
++		if (dhd->wakelock_ctrl_timeout_enable)
++			wake_lock_timeout(&dhd->wl_ctrlwake,
++				msecs_to_jiffies(dhd->wakelock_ctrl_timeout_enable));
++#endif
++		dhd->wakelock_rx_timeout_enable = 0;
++		dhd->wakelock_ctrl_timeout_enable = 0;
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++	return ret;
++}
++
++int net_os_wake_lock_timeout(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret = 0;
++
++	if (dhd)
++		ret = dhd_os_wake_lock_timeout(&dhd->pub);
++	return ret;
++}
++
++int dhd_os_wake_lock_rx_timeout_enable(dhd_pub_t *pub, int val)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++
++	if (dhd && (dhd->dhd_state & DHD_ATTACH_STATE_WAKELOCKS_INIT)) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++		if (val > dhd->wakelock_rx_timeout_enable)
++			dhd->wakelock_rx_timeout_enable = val;
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++	return 0;
++}
++
++int dhd_os_wake_lock_ctrl_timeout_enable(dhd_pub_t *pub, int val)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++
++	if (dhd && (dhd->dhd_state & DHD_ATTACH_STATE_WAKELOCKS_INIT)) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++		if (val > dhd->wakelock_ctrl_timeout_enable)
++			dhd->wakelock_ctrl_timeout_enable = val;
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++	return 0;
++}
++
++int dhd_os_wake_lock_ctrl_timeout_cancel(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++
++	if (dhd && (dhd->dhd_state & DHD_ATTACH_STATE_WAKELOCKS_INIT)) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++		dhd->wakelock_ctrl_timeout_enable = 0;
++#ifdef CONFIG_HAS_WAKELOCK
++		if (wake_lock_active(&dhd->wl_ctrlwake))
++			wake_unlock(&dhd->wl_ctrlwake);
++#endif
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++	return 0;
++}
++
++int net_os_wake_lock_rx_timeout_enable(struct net_device *dev, int val)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret = 0;
++
++	if (dhd)
++		ret = dhd_os_wake_lock_rx_timeout_enable(&dhd->pub, val);
++	return ret;
++}
++
++int net_os_wake_lock_ctrl_timeout_enable(struct net_device *dev, int val)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret = 0;
++
++	if (dhd)
++		ret = dhd_os_wake_lock_ctrl_timeout_enable(&dhd->pub, val);
++	return ret;
++}
++
++
++#if defined(DHD_TRACE_WAKE_LOCK)
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
++#include <linux/hashtable.h>
++#else
++#include <linux/hash.h>
++#endif /* KERNEL_VER >= KERNEL_VERSION(3, 7, 0) */
++
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
++/* Define 2^5 = 32 bucket size hash table */
++DEFINE_HASHTABLE(wklock_history, 5);
++#else
++/* Define 2^5 = 32 bucket size hash table */
++struct hlist_head wklock_history[32] = { [0 ... 31] = HLIST_HEAD_INIT };
++#endif /* KERNEL_VER >= KERNEL_VERSION(3, 7, 0) */
++
++int trace_wklock_onoff = 1;
++typedef enum dhd_wklock_type {
++	DHD_WAKE_LOCK,
++	DHD_WAKE_UNLOCK,
++	DHD_WAIVE_LOCK,
++	DHD_RESTORE_LOCK
++} dhd_wklock_t;
++
++struct wk_trace_record {
++	unsigned long addr;	            /* Address of the instruction */
++	dhd_wklock_t lock_type;         /* lock_type */
++	unsigned long long counter;		/* counter information */
++	struct hlist_node wklock_node;  /* hash node */
++};
++
++static struct wk_trace_record *find_wklock_entry(unsigned long addr)
++{
++	struct wk_trace_record *wklock_info;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
++	hash_for_each_possible(wklock_history, wklock_info, wklock_node, addr)
++#else
++	struct hlist_node *entry;
++	int index = hash_long(addr, ilog2(ARRAY_SIZE(wklock_history)));
++	hlist_for_each_entry(wklock_info, entry, &wklock_history[index], wklock_node)
++#endif /* KERNEL_VER >= KERNEL_VERSION(3, 7, 0) */
++	{
++		if (wklock_info->addr == addr) {
++			return wklock_info;
++		}
++	}
++	return NULL;
++}
++
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
++#define HASH_ADD(hashtable, node, key) \
++	do { \
++		hash_add(hashtable, node, key); \
++	} while (0);
++#else
++#define HASH_ADD(hashtable, node, key) \
++	do { \
++		int index = hash_long(key, ilog2(ARRAY_SIZE(hashtable))); \
++		hlist_add_head(node, &hashtable[index]); \
++	} while (0);
++#endif /* KERNEL_VER < KERNEL_VERSION(3, 7, 0) */
++
++#define STORE_WKLOCK_RECORD(wklock_type) \
++	do { \
++		struct wk_trace_record *wklock_info = NULL; \
++		unsigned long func_addr = (unsigned long)__builtin_return_address(0); \
++		wklock_info = find_wklock_entry(func_addr); \
++		if (wklock_info) { \
++			if (wklock_type == DHD_WAIVE_LOCK || wklock_type == DHD_RESTORE_LOCK) { \
++				wklock_info->counter = dhd->wakelock_counter; \
++			} else { \
++				wklock_info->counter++; \
++			} \
++		} else { \
++			wklock_info = kzalloc(sizeof(*wklock_info), GFP_ATOMIC); \
++			if (!wklock_info) {\
++				printk("Can't allocate wk_trace_record \n"); \
++			} else { \
++				wklock_info->addr = func_addr; \
++				wklock_info->lock_type = wklock_type; \
++				if (wklock_type == DHD_WAIVE_LOCK || \
++						wklock_type == DHD_RESTORE_LOCK) { \
++					wklock_info->counter = dhd->wakelock_counter; \
++				} else { \
++					wklock_info->counter++; \
++				} \
++				HASH_ADD(wklock_history, &wklock_info->wklock_node, func_addr); \
++			} \
++		} \
++	} while (0);
++
++static inline void dhd_wk_lock_rec_dump(void)
++{
++	int bkt;
++	struct wk_trace_record *wklock_info;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
++	hash_for_each(wklock_history, bkt, wklock_info, wklock_node)
++#else
++	struct hlist_node *entry = NULL;
++	int max_index = ARRAY_SIZE(wklock_history);
++	for (bkt = 0; bkt < max_index; bkt++)
++		hlist_for_each_entry(wklock_info, entry, &wklock_history[bkt], wklock_node)
++#endif /* KERNEL_VER >= KERNEL_VERSION(3, 7, 0) */
++		{
++			switch (wklock_info->lock_type) {
++				case DHD_WAKE_LOCK:
++					printk("wakelock lock : %pS  lock_counter : %llu \n",
++						(void *)wklock_info->addr, wklock_info->counter);
++					break;
++				case DHD_WAKE_UNLOCK:
++					printk("wakelock unlock : %pS, unlock_counter : %llu \n",
++						(void *)wklock_info->addr, wklock_info->counter);
++					break;
++				case DHD_WAIVE_LOCK:
++					printk("wakelock waive : %pS  before_waive : %llu \n",
++						(void *)wklock_info->addr, wklock_info->counter);
++					break;
++				case DHD_RESTORE_LOCK:
++					printk("wakelock restore : %pS, after_waive : %llu \n",
++						(void *)wklock_info->addr, wklock_info->counter);
++					break;
++			}
++		}
++}
++
++static void dhd_wk_lock_trace_init(struct dhd_info *dhd)
++{
++	unsigned long flags;
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0))
++	int i;
++#endif /* KERNEL_VER >= KERNEL_VERSION(3, 7, 0) */
++
++	spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
++	hash_init(wklock_history);
++#else
++	for (i = 0; i < ARRAY_SIZE(wklock_history); i++)
++		INIT_HLIST_HEAD(&wklock_history[i]);
++#endif /* KERNEL_VER >= KERNEL_VERSION(3, 7, 0) */
++	spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++}
++
++static void dhd_wk_lock_trace_deinit(struct dhd_info *dhd)
++{
++	int bkt;
++	struct wk_trace_record *wklock_info;
++	struct hlist_node *tmp;
++	unsigned long flags;
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0))
++	struct hlist_node *entry = NULL;
++	int max_index = ARRAY_SIZE(wklock_history);
++#endif /* KERNEL_VER >= KERNEL_VERSION(3, 7, 0) */
++
++	spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
++	hash_for_each_safe(wklock_history, bkt, tmp, wklock_info, wklock_node)
++#else
++	for (bkt = 0; bkt < max_index; bkt++)
++		hlist_for_each_entry_safe(wklock_info, entry, tmp,
++			&wklock_history[bkt], wklock_node)
++#endif /* KERNEL_VER >= KERNEL_VERSION(3, 7, 0)) */
++		{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
++			hash_del(&wklock_info->wklock_node);
++#else
++			hlist_del_init(&wklock_info->wklock_node);
++#endif /* KERNEL_VER >= KERNEL_VERSION(3, 7, 0)) */
++			kfree(wklock_info);
++		}
++	spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++}
++
++void dhd_wk_lock_stats_dump(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(dhdp->info);
++	unsigned long flags;
++
++	printk(KERN_ERR"DHD Printing wl_wake Lock/Unlock Record \r\n");
++	spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++	dhd_wk_lock_rec_dump();
++	spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++
++}
++#else
++#define STORE_WKLOCK_RECORD(wklock_type)
++#endif /* ! DHD_TRACE_WAKE_LOCK */
++
++int dhd_os_wake_lock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++	int ret = 0;
++
++	if (dhd && (dhd->dhd_state & DHD_ATTACH_STATE_WAKELOCKS_INIT)) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++		if (dhd->wakelock_counter == 0 && !dhd->waive_wakelock) {
++#ifdef CONFIG_HAS_WAKELOCK
++			wake_lock(&dhd->wl_wifi);
++#elif defined(BCMSDIO) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++			dhd_bus_dev_pm_stay_awake(pub);
++#endif
++		}
++#ifdef DHD_TRACE_WAKE_LOCK
++		if (trace_wklock_onoff) {
++			STORE_WKLOCK_RECORD(DHD_WAKE_LOCK);
++		}
++#endif /* DHD_TRACE_WAKE_LOCK */
++		dhd->wakelock_counter++;
++		ret = dhd->wakelock_counter;
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++
++	return ret;
++}
++
++void dhd_event_wake_lock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++#ifdef CONFIG_HAS_WAKELOCK
++		wake_lock(&dhd->wl_evtwake);
++#elif defined(BCMSDIO) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++		dhd_bus_dev_pm_stay_awake(pub);
++#endif
++	}
++}
++
++void
++dhd_pm_wake_lock_timeout(dhd_pub_t *pub, int val)
++{
++#ifdef CONFIG_HAS_WAKELOCK
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		wake_lock_timeout(&dhd->wl_pmwake, msecs_to_jiffies(val));
++	}
++#endif /* CONFIG_HAS_WAKE_LOCK */
++}
++
++void
++dhd_txfl_wake_lock_timeout(dhd_pub_t *pub, int val)
++{
++#ifdef CONFIG_HAS_WAKELOCK
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		wake_lock_timeout(&dhd->wl_txflwake, msecs_to_jiffies(val));
++	}
++#endif /* CONFIG_HAS_WAKE_LOCK */
++}
++
++int net_os_wake_lock(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret = 0;
++
++	if (dhd)
++		ret = dhd_os_wake_lock(&dhd->pub);
++	return ret;
++}
++
++int dhd_os_wake_unlock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++	int ret = 0;
++
++	dhd_os_wake_lock_timeout(pub);
++	if (dhd && (dhd->dhd_state & DHD_ATTACH_STATE_WAKELOCKS_INIT)) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++
++		if (dhd->wakelock_counter > 0) {
++			dhd->wakelock_counter--;
++#ifdef DHD_TRACE_WAKE_LOCK
++			if (trace_wklock_onoff) {
++				STORE_WKLOCK_RECORD(DHD_WAKE_UNLOCK);
++			}
++#endif /* DHD_TRACE_WAKE_LOCK */
++			if (dhd->wakelock_counter == 0 && !dhd->waive_wakelock) {
++#ifdef CONFIG_HAS_WAKELOCK
++				wake_unlock(&dhd->wl_wifi);
++#elif defined(BCMSDIO) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++				dhd_bus_dev_pm_relax(pub);
++#endif
++			}
++			ret = dhd->wakelock_counter;
++		}
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++	return ret;
++}
++
++void dhd_event_wake_unlock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++#ifdef CONFIG_HAS_WAKELOCK
++		wake_unlock(&dhd->wl_evtwake);
++#elif defined(BCMSDIO) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++		dhd_bus_dev_pm_relax(pub);
++#endif
++	}
++}
++
++void dhd_pm_wake_unlock(dhd_pub_t *pub)
++{
++#ifdef CONFIG_HAS_WAKELOCK
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		/* if wl_pmwake is active, unlock it */
++		if (wake_lock_active(&dhd->wl_pmwake)) {
++			wake_unlock(&dhd->wl_pmwake);
++		}
++	}
++#endif /* CONFIG_HAS_WAKELOCK */
++}
++
++void dhd_txfl_wake_unlock(dhd_pub_t *pub)
++{
++#ifdef CONFIG_HAS_WAKELOCK
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		/* if wl_txflwake is active, unlock it */
++		if (wake_lock_active(&dhd->wl_txflwake)) {
++			wake_unlock(&dhd->wl_txflwake);
++		}
++	}
++#endif /* CONFIG_HAS_WAKELOCK */
++}
++
++int dhd_os_check_wakelock(dhd_pub_t *pub)
++{
++#if defined(CONFIG_HAS_WAKELOCK) || (defined(BCMSDIO) && (LINUX_VERSION_CODE > \
++	KERNEL_VERSION(2, 6, 36)))
++	dhd_info_t *dhd;
++
++	if (!pub)
++		return 0;
++	dhd = (dhd_info_t *)(pub->info);
++#endif /* CONFIG_HAS_WAKELOCK || BCMSDIO */
++
++#ifdef CONFIG_HAS_WAKELOCK
++	/* Indicate to the SD Host to avoid going to suspend if internal locks are up */
++	if (dhd && (wake_lock_active(&dhd->wl_wifi) ||
++		(wake_lock_active(&dhd->wl_wdwake))))
++		return 1;
++#elif defined(BCMSDIO) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++	if (dhd && (dhd->wakelock_counter > 0) && dhd_bus_dev_pm_enabled(pub))
++		return 1;
++#endif
++	return 0;
++}
++
++int
++dhd_os_check_wakelock_all(dhd_pub_t *pub)
++{
++#if defined(CONFIG_HAS_WAKELOCK) || (defined(BCMSDIO) && (LINUX_VERSION_CODE > \
++	KERNEL_VERSION(2, 6, 36)))
++#if defined(CONFIG_HAS_WAKELOCK)
++	int l1, l2, l3, l4, l7, l8, l9;
++	int l5 = 0, l6 = 0;
++	int c, lock_active;
++#endif /* CONFIG_HAS_WAKELOCK */
++	dhd_info_t *dhd;
++
++	if (!pub) {
++		return 0;
++	}
++	dhd = (dhd_info_t *)(pub->info);
++	if (!dhd) {
++		return 0;
++	}
++#endif /* CONFIG_HAS_WAKELOCK || BCMSDIO */
++
++#ifdef CONFIG_HAS_WAKELOCK
++	c = dhd->wakelock_counter;
++	l1 = wake_lock_active(&dhd->wl_wifi);
++	l2 = wake_lock_active(&dhd->wl_wdwake);
++	l3 = wake_lock_active(&dhd->wl_rxwake);
++	l4 = wake_lock_active(&dhd->wl_ctrlwake);
++	l7 = wake_lock_active(&dhd->wl_evtwake);
++#ifdef BCMPCIE_OOB_HOST_WAKE
++	l5 = wake_lock_active(&dhd->wl_intrwake);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#ifdef DHD_USE_SCAN_WAKELOCK
++	l6 = wake_lock_active(&dhd->wl_scanwake);
++#endif /* DHD_USE_SCAN_WAKELOCK */
++	l8 = wake_lock_active(&dhd->wl_pmwake);
++	l9 = wake_lock_active(&dhd->wl_txflwake);
++	lock_active = (l1 || l2 || l3 || l4 || l5 || l6 || l7 || l8 || l9);
++
++	/* Indicate to the Host to avoid going to suspend if internal locks are up */
++	if (lock_active) {
++		DHD_ERROR(("%s wakelock c-%d wl-%d wd-%d rx-%d "
++			"ctl-%d intr-%d scan-%d evt-%d, pm-%d, txfl-%d\n",
++			__FUNCTION__, c, l1, l2, l3, l4, l5, l6, l7, l8, l9));
++		return 1;
++	}
++#elif defined(BCMSDIO) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++	if (dhd && (dhd->wakelock_counter > 0) && dhd_bus_dev_pm_enabled(pub)) {
++		return 1;
++	}
++#endif /* defined(BCMSDIO) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36)) */
++	return 0;
++}
++
++int net_os_wake_unlock(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret = 0;
++
++	if (dhd)
++		ret = dhd_os_wake_unlock(&dhd->pub);
++	return ret;
++}
++
++int dhd_os_wd_wake_lock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++	int ret = 0;
++
++	if (dhd) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++#ifdef CONFIG_HAS_WAKELOCK
++		/* if wakelock_wd_counter was never used : lock it at once */
++		if (!dhd->wakelock_wd_counter)
++			wake_lock(&dhd->wl_wdwake);
++#endif
++		dhd->wakelock_wd_counter++;
++		ret = dhd->wakelock_wd_counter;
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++	return ret;
++}
++
++int dhd_os_wd_wake_unlock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++	int ret = 0;
++
++	if (dhd) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++		if (dhd->wakelock_wd_counter) {
++			dhd->wakelock_wd_counter = 0;
++#ifdef CONFIG_HAS_WAKELOCK
++			wake_unlock(&dhd->wl_wdwake);
++#endif
++		}
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++	return ret;
++}
++
++#ifdef BCMPCIE_OOB_HOST_WAKE
++void
++dhd_os_oob_irq_wake_lock_timeout(dhd_pub_t *pub, int val)
++{
++#ifdef CONFIG_HAS_WAKELOCK
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		wake_lock_timeout(&dhd->wl_intrwake, msecs_to_jiffies(val));
++	}
++#endif /* CONFIG_HAS_WAKELOCK */
++}
++
++void
++dhd_os_oob_irq_wake_unlock(dhd_pub_t *pub)
++{
++#ifdef CONFIG_HAS_WAKELOCK
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		/* if wl_intrwake is active, unlock it */
++		if (wake_lock_active(&dhd->wl_intrwake)) {
++			wake_unlock(&dhd->wl_intrwake);
++		}
++	}
++#endif /* CONFIG_HAS_WAKELOCK */
++}
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++
++#ifdef DHD_USE_SCAN_WAKELOCK
++void
++dhd_os_scan_wake_lock_timeout(dhd_pub_t *pub, int val)
++{
++#ifdef CONFIG_HAS_WAKELOCK
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		wake_lock_timeout(&dhd->wl_scanwake, msecs_to_jiffies(val));
++	}
++#endif /* CONFIG_HAS_WAKELOCK */
++}
++
++void
++dhd_os_scan_wake_unlock(dhd_pub_t *pub)
++{
++#ifdef CONFIG_HAS_WAKELOCK
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		/* if wl_scanwake is active, unlock it */
++		if (wake_lock_active(&dhd->wl_scanwake)) {
++			wake_unlock(&dhd->wl_scanwake);
++		}
++	}
++#endif /* CONFIG_HAS_WAKELOCK */
++}
++#endif /* DHD_USE_SCAN_WAKELOCK */
++
++/* waive wakelocks for operations such as IOVARs in suspend function, must be closed
++ * by a paired function call to dhd_wakelock_restore. returns current wakelock counter
++ */
++int dhd_os_wake_lock_waive(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++	int ret = 0;
++
++	if (dhd && (dhd->dhd_state & DHD_ATTACH_STATE_WAKELOCKS_INIT)) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++
++		/* dhd_wakelock_waive/dhd_wakelock_restore must be paired */
++		if (dhd->waive_wakelock == FALSE) {
++#ifdef DHD_TRACE_WAKE_LOCK
++			if (trace_wklock_onoff) {
++				STORE_WKLOCK_RECORD(DHD_WAIVE_LOCK);
++			}
++#endif /* DHD_TRACE_WAKE_LOCK */
++			/* record current lock status */
++			dhd->wakelock_before_waive = dhd->wakelock_counter;
++			dhd->waive_wakelock = TRUE;
++		}
++		ret = dhd->wakelock_wd_counter;
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++	return ret;
++}
++
++int dhd_os_wake_lock_restore(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++	int ret = 0;
++
++	if (!dhd)
++		return 0;
++	if ((dhd->dhd_state & DHD_ATTACH_STATE_WAKELOCKS_INIT) == 0)
++		return 0;
++
++	spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++
++	/* dhd_wakelock_waive/dhd_wakelock_restore must be paired */
++	if (!dhd->waive_wakelock)
++		goto exit;
++
++	dhd->waive_wakelock = FALSE;
++	/* if somebody else acquires wakelock between dhd_wakelock_waive/dhd_wakelock_restore,
++	 * we need to make it up by calling wake_lock or pm_stay_awake. or if somebody releases
++	 * the lock in between, do the same by calling wake_unlock or pm_relax
++	 */
++#ifdef DHD_TRACE_WAKE_LOCK
++	if (trace_wklock_onoff) {
++		STORE_WKLOCK_RECORD(DHD_RESTORE_LOCK);
++	}
++#endif /* DHD_TRACE_WAKE_LOCK */
++
++	if (dhd->wakelock_before_waive == 0 && dhd->wakelock_counter > 0) {
++#ifdef CONFIG_HAS_WAKELOCK
++		wake_lock(&dhd->wl_wifi);
++#elif defined(BCMSDIO) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++		dhd_bus_dev_pm_stay_awake(&dhd->pub);
++#endif
++	} else if (dhd->wakelock_before_waive > 0 && dhd->wakelock_counter == 0) {
++#ifdef CONFIG_HAS_WAKELOCK
++		wake_unlock(&dhd->wl_wifi);
++#elif defined(BCMSDIO) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++		dhd_bus_dev_pm_relax(&dhd->pub);
++#endif
++	}
++	dhd->wakelock_before_waive = 0;
++exit:
++	ret = dhd->wakelock_wd_counter;
++	spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	return ret;
++}
++
++void dhd_os_wake_lock_init(struct dhd_info *dhd)
++{
++	DHD_TRACE(("%s: initialize wake_lock_counters\n", __FUNCTION__));
++	dhd->wakelock_counter = 0;
++	dhd->wakelock_rx_timeout_enable = 0;
++	dhd->wakelock_ctrl_timeout_enable = 0;
++#ifdef CONFIG_HAS_WAKELOCK
++	// terence 20161023: can not destroy wl_wifi when wlan down, it will happen null pointer in dhd_ioctl_entry
++	wake_lock_init(&dhd->wl_rxwake, WAKE_LOCK_SUSPEND, "wlan_rx_wake");
++	wake_lock_init(&dhd->wl_ctrlwake, WAKE_LOCK_SUSPEND, "wlan_ctrl_wake");
++	wake_lock_init(&dhd->wl_evtwake, WAKE_LOCK_SUSPEND, "wlan_evt_wake");
++	wake_lock_init(&dhd->wl_pmwake, WAKE_LOCK_SUSPEND, "wlan_pm_wake");
++	wake_lock_init(&dhd->wl_txflwake, WAKE_LOCK_SUSPEND, "wlan_txfl_wake");
++#ifdef BCMPCIE_OOB_HOST_WAKE
++	wake_lock_init(&dhd->wl_intrwake, WAKE_LOCK_SUSPEND, "wlan_oob_irq_wake");
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#ifdef DHD_USE_SCAN_WAKELOCK
++	wake_lock_init(&dhd->wl_scanwake, WAKE_LOCK_SUSPEND, "wlan_scan_wake");
++#endif /* DHD_USE_SCAN_WAKELOCK */
++#endif /* CONFIG_HAS_WAKELOCK */
++#ifdef DHD_TRACE_WAKE_LOCK
++	dhd_wk_lock_trace_init(dhd);
++#endif /* DHD_TRACE_WAKE_LOCK */
++}
++
++void dhd_os_wake_lock_destroy(struct dhd_info *dhd)
++{
++	DHD_TRACE(("%s: deinit wake_lock_counters\n", __FUNCTION__));
++#ifdef CONFIG_HAS_WAKELOCK
++	dhd->wakelock_counter = 0;
++	dhd->wakelock_rx_timeout_enable = 0;
++	dhd->wakelock_ctrl_timeout_enable = 0;
++	// terence 20161023: can not destroy wl_wifi when wlan down, it will happen null pointer in dhd_ioctl_entry
++	wake_lock_destroy(&dhd->wl_rxwake);
++	wake_lock_destroy(&dhd->wl_ctrlwake);
++	wake_lock_destroy(&dhd->wl_evtwake);
++	wake_lock_destroy(&dhd->wl_pmwake);
++	wake_lock_destroy(&dhd->wl_txflwake);
++#ifdef BCMPCIE_OOB_HOST_WAKE
++	wake_lock_destroy(&dhd->wl_intrwake);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#ifdef DHD_USE_SCAN_WAKELOCK
++	wake_lock_destroy(&dhd->wl_scanwake);
++#endif /* DHD_USE_SCAN_WAKELOCK */
++#ifdef DHD_TRACE_WAKE_LOCK
++	dhd_wk_lock_trace_deinit(dhd);
++#endif /* DHD_TRACE_WAKE_LOCK */
++#endif /* CONFIG_HAS_WAKELOCK */
++}
++
++bool dhd_os_check_if_up(dhd_pub_t *pub)
++{
++	if (!pub)
++		return FALSE;
++	return pub->up;
++}
++
++/* function to collect firmware, chip id and chip version info */
++void dhd_set_version_info(dhd_pub_t *dhdp, char *fw)
++{
++	int i;
++
++	i = snprintf(info_string, sizeof(info_string),
++		"  Driver: %s\n  Firmware: %s\n  CLM: %s ", EPI_VERSION_STR, fw, clm_version);
++	printf("%s\n", info_string);
++
++	if (!dhdp)
++		return;
++
++	i = snprintf(&info_string[i], sizeof(info_string) - i,
++		"\n  Chip: %x Rev %x", dhd_conf_get_chip(dhdp),
++		dhd_conf_get_chiprev(dhdp));
++}
++
++int dhd_ioctl_entry_local(struct net_device *net, wl_ioctl_t *ioc, int cmd)
++{
++	int ifidx;
++	int ret = 0;
++	dhd_info_t *dhd = NULL;
++
++	if (!net || !DEV_PRIV(net)) {
++		DHD_ERROR(("%s invalid parameter\n", __FUNCTION__));
++		return -EINVAL;
++	}
++
++	dhd = DHD_DEV_INFO(net);
++	if (!dhd)
++		return -EINVAL;
++
++	ifidx = dhd_net2idx(dhd, net);
++	if (ifidx == DHD_BAD_IF) {
++		DHD_ERROR(("%s bad ifidx\n", __FUNCTION__));
++		return -ENODEV;
++	}
++
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK(&dhd->pub);
++
++	ret = dhd_wl_ioctl(&dhd->pub, ifidx, ioc, ioc->buf, ioc->len);
++	dhd_check_hang(net, &dhd->pub, ret);
++
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++
++	return ret;
++}
++
++bool dhd_os_check_hang(dhd_pub_t *dhdp, int ifidx, int ret)
++{
++	struct net_device *net;
++
++	net = dhd_idx2net(dhdp, ifidx);
++	if (!net) {
++		DHD_ERROR(("%s : Invalid index : %d\n", __FUNCTION__, ifidx));
++		return -EINVAL;
++	}
++
++	return dhd_check_hang(net, dhdp, ret);
++}
++
++/* Return instance */
++int dhd_get_instance(dhd_pub_t *dhdp)
++{
++	return dhdp->info->unit;
++}
++
++
++#ifdef PROP_TXSTATUS
++
++void dhd_wlfc_plat_init(void *dhd)
++{
++#ifdef USE_DYNAMIC_F2_BLKSIZE
++	dhdsdio_func_blocksize((dhd_pub_t *)dhd, 2, DYNAMIC_F2_BLKSIZE_FOR_NONLEGACY);
++#endif /* USE_DYNAMIC_F2_BLKSIZE */
++	return;
++}
++
++void dhd_wlfc_plat_deinit(void *dhd)
++{
++#ifdef USE_DYNAMIC_F2_BLKSIZE
++	dhdsdio_func_blocksize((dhd_pub_t *)dhd, 2, sd_f2_blocksize);
++#endif /* USE_DYNAMIC_F2_BLKSIZE */
++	return;
++}
++
++bool dhd_wlfc_skip_fc(void * dhdp, uint8 idx)
++{
++#ifdef SKIP_WLFC_ON_CONCURRENT
++
++#ifdef WL_CFG80211
++	struct net_device * net =  dhd_idx2net((dhd_pub_t *)dhdp, idx);
++	if (net)
++	/* enable flow control in vsdb mode */
++	return !(wl_cfg80211_is_concurrent_mode(net));
++#else
++	return TRUE; /* skip flow control */
++#endif /* WL_CFG80211 */
++
++#else
++	return FALSE;
++#endif /* SKIP_WLFC_ON_CONCURRENT */
++	return FALSE;
++}
++#endif /* PROP_TXSTATUS */
++
++#ifdef BCMDBGFS
++#include <linux/debugfs.h>
++
++typedef struct dhd_dbgfs {
++	struct dentry	*debugfs_dir;
++	struct dentry	*debugfs_mem;
++	dhd_pub_t	*dhdp;
++	uint32		size;
++} dhd_dbgfs_t;
++
++dhd_dbgfs_t g_dbgfs;
++
++extern uint32 dhd_readregl(void *bp, uint32 addr);
++extern uint32 dhd_writeregl(void *bp, uint32 addr, uint32 data);
++
++static int
++dhd_dbg_state_open(struct inode *inode, struct file *file)
++{
++	file->private_data = inode->i_private;
++	return 0;
++}
++
++static ssize_t
++dhd_dbg_state_read(struct file *file, char __user *ubuf,
++                       size_t count, loff_t *ppos)
++{
++	ssize_t rval;
++	uint32 tmp;
++	loff_t pos = *ppos;
++	size_t ret;
++
++	if (pos < 0)
++		return -EINVAL;
++	if (pos >= g_dbgfs.size || !count)
++		return 0;
++	if (count > g_dbgfs.size - pos)
++		count = g_dbgfs.size - pos;
++
++	/* Basically enforce aligned 4 byte reads. It's up to the user to work out the details */
++	tmp = dhd_readregl(g_dbgfs.dhdp->bus, file->f_pos & (~3));
++
++	ret = copy_to_user(ubuf, &tmp, 4);
++	if (ret == count)
++		return -EFAULT;
++
++	count -= ret;
++	*ppos = pos + count;
++	rval = count;
++
++	return rval;
++}
++
++
++static ssize_t
++dhd_debugfs_write(struct file *file, const char __user *ubuf, size_t count, loff_t *ppos)
++{
++	loff_t pos = *ppos;
++	size_t ret;
++	uint32 buf;
++
++	if (pos < 0)
++		return -EINVAL;
++	if (pos >= g_dbgfs.size || !count)
++		return 0;
++	if (count > g_dbgfs.size - pos)
++		count = g_dbgfs.size - pos;
++
++	ret = copy_from_user(&buf, ubuf, sizeof(uint32));
++	if (ret == count)
++		return -EFAULT;
++
++	/* Basically enforce aligned 4 byte writes. It's up to the user to work out the details */
++	dhd_writeregl(g_dbgfs.dhdp->bus, file->f_pos & (~3), buf);
++
++	return count;
++}
++
++
++loff_t
++dhd_debugfs_lseek(struct file *file, loff_t off, int whence)
++{
++	loff_t pos = -1;
++
++	switch (whence) {
++		case 0:
++			pos = off;
++			break;
++		case 1:
++			pos = file->f_pos + off;
++			break;
++		case 2:
++			pos = g_dbgfs.size - off;
++	}
++	return (pos < 0 || pos > g_dbgfs.size) ? -EINVAL : (file->f_pos = pos);
++}
++
++static const struct file_operations dhd_dbg_state_ops = {
++	.read   = dhd_dbg_state_read,
++	.write	= dhd_debugfs_write,
++	.open   = dhd_dbg_state_open,
++	.llseek	= dhd_debugfs_lseek
++};
++
++static void dhd_dbgfs_create(void)
++{
++	if (g_dbgfs.debugfs_dir) {
++		g_dbgfs.debugfs_mem = debugfs_create_file("mem", 0644, g_dbgfs.debugfs_dir,
++			NULL, &dhd_dbg_state_ops);
++	}
++}
++
++void dhd_dbgfs_init(dhd_pub_t *dhdp)
++{
++	g_dbgfs.dhdp = dhdp;
++	g_dbgfs.size = 0x20000000; /* Allow access to various cores regs */
++
++	g_dbgfs.debugfs_dir = debugfs_create_dir("dhd", 0);
++	if (IS_ERR(g_dbgfs.debugfs_dir)) {
++		g_dbgfs.debugfs_dir = NULL;
++		return;
++	}
++
++	dhd_dbgfs_create();
++
++	return;
++}
++
++void dhd_dbgfs_remove(void)
++{
++	debugfs_remove(g_dbgfs.debugfs_mem);
++	debugfs_remove(g_dbgfs.debugfs_dir);
++
++	bzero((unsigned char *) &g_dbgfs, sizeof(g_dbgfs));
++}
++#endif /* BCMDBGFS */
++
++#ifdef WLMEDIA_HTSF
++
++static
++void dhd_htsf_addtxts(dhd_pub_t *dhdp, void *pktbuf)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(dhdp->info);
++	struct sk_buff *skb;
++	uint32 htsf = 0;
++	uint16 dport = 0, oldmagic = 0xACAC;
++	char *p1;
++	htsfts_t ts;
++
++	/*  timestamp packet  */
++
++	p1 = (char*) PKTDATA(dhdp->osh, pktbuf);
++
++	if (PKTLEN(dhdp->osh, pktbuf) > HTSF_MINLEN) {
++/*		memcpy(&proto, p1+26, 4);  	*/
++		memcpy(&dport, p1+40, 2);
++/* 	proto = ((ntoh32(proto))>> 16) & 0xFF;  */
++		dport = ntoh16(dport);
++	}
++
++	/* timestamp only if  icmp or udb iperf with port 5555 */
++/*	if (proto == 17 && dport == tsport) { */
++	if (dport >= tsport && dport <= tsport + 20) {
++
++		skb = (struct sk_buff *) pktbuf;
++
++		htsf = dhd_get_htsf(dhd, 0);
++		memset(skb->data + 44, 0, 2); /* clear checksum */
++		memcpy(skb->data+82, &oldmagic, 2);
++		memcpy(skb->data+84, &htsf, 4);
++
++		memset(&ts, 0, sizeof(htsfts_t));
++		ts.magic  = HTSFMAGIC;
++		ts.prio   = PKTPRIO(pktbuf);
++		ts.seqnum = htsf_seqnum++;
++		ts.c10    = get_cycles();
++		ts.t10    = htsf;
++		ts.endmagic = HTSFENDMAGIC;
++
++		memcpy(skb->data + HTSF_HOSTOFFSET, &ts, sizeof(ts));
++	}
++}
++
++static void dhd_dump_htsfhisto(histo_t *his, char *s)
++{
++	int pktcnt = 0, curval = 0, i;
++	for (i = 0; i < (NUMBIN-2); i++) {
++		curval += 500;
++		printf("%d ",  his->bin[i]);
++		pktcnt += his->bin[i];
++	}
++	printf(" max: %d TotPkt: %d neg: %d [%s]\n", his->bin[NUMBIN-2], pktcnt,
++		his->bin[NUMBIN-1], s);
++}
++
++static
++void sorttobin(int value, histo_t *histo)
++{
++	int i, binval = 0;
++
++	if (value < 0) {
++		histo->bin[NUMBIN-1]++;
++		return;
++	}
++	if (value > histo->bin[NUMBIN-2])  /* store the max value  */
++		histo->bin[NUMBIN-2] = value;
++
++	for (i = 0; i < (NUMBIN-2); i++) {
++		binval += 500; /* 500m s bins */
++		if (value <= binval) {
++			histo->bin[i]++;
++			return;
++		}
++	}
++	histo->bin[NUMBIN-3]++;
++}
++
++static
++void dhd_htsf_addrxts(dhd_pub_t *dhdp, void *pktbuf)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++	struct sk_buff *skb;
++	char *p1;
++	uint16 old_magic;
++	int d1, d2, d3, end2end;
++	htsfts_t *htsf_ts;
++	uint32 htsf;
++
++	skb = PKTTONATIVE(dhdp->osh, pktbuf);
++	p1 = (char*)PKTDATA(dhdp->osh, pktbuf);
++
++	if (PKTLEN(osh, pktbuf) > HTSF_MINLEN) {
++		memcpy(&old_magic, p1+78, 2);
++		htsf_ts = (htsfts_t*) (p1 + HTSF_HOSTOFFSET - 4);
++	} else {
++		return;
++	}
++
++	if (htsf_ts->magic == HTSFMAGIC) {
++		htsf_ts->tE0 = dhd_get_htsf(dhd, 0);
++		htsf_ts->cE0 = get_cycles();
++	}
++
++	if (old_magic == 0xACAC) {
++
++		tspktcnt++;
++		htsf = dhd_get_htsf(dhd, 0);
++		memcpy(skb->data+92, &htsf, sizeof(uint32));
++
++		memcpy(&ts[tsidx].t1, skb->data+80, 16);
++
++		d1 = ts[tsidx].t2 - ts[tsidx].t1;
++		d2 = ts[tsidx].t3 - ts[tsidx].t2;
++		d3 = ts[tsidx].t4 - ts[tsidx].t3;
++		end2end = ts[tsidx].t4 - ts[tsidx].t1;
++
++		sorttobin(d1, &vi_d1);
++		sorttobin(d2, &vi_d2);
++		sorttobin(d3, &vi_d3);
++		sorttobin(end2end, &vi_d4);
++
++		if (end2end > 0 && end2end >  maxdelay) {
++			maxdelay = end2end;
++			maxdelaypktno = tspktcnt;
++			memcpy(&maxdelayts, &ts[tsidx], 16);
++		}
++		if (++tsidx >= TSMAX)
++			tsidx = 0;
++	}
++}
++
++uint32 dhd_get_htsf(dhd_info_t *dhd, int ifidx)
++{
++	uint32 htsf = 0, cur_cycle, delta, delta_us;
++	uint32    factor, baseval, baseval2;
++	cycles_t t;
++
++	t = get_cycles();
++	cur_cycle = t;
++
++	if (cur_cycle >  dhd->htsf.last_cycle)
++		delta = cur_cycle -  dhd->htsf.last_cycle;
++	else {
++		delta = cur_cycle + (0xFFFFFFFF -  dhd->htsf.last_cycle);
++	}
++
++	delta = delta >> 4;
++
++	if (dhd->htsf.coef) {
++		/* times ten to get the first digit */
++	        factor = (dhd->htsf.coef*10 + dhd->htsf.coefdec1);
++		baseval  = (delta*10)/factor;
++		baseval2 = (delta*10)/(factor+1);
++		delta_us  = (baseval -  (((baseval - baseval2) * dhd->htsf.coefdec2)) / 10);
++		htsf = (delta_us << 4) +  dhd->htsf.last_tsf + HTSF_BUS_DELAY;
++	} else {
++		DHD_ERROR(("-------dhd->htsf.coef = 0 -------\n"));
++	}
++
++	return htsf;
++}
++
++static void dhd_dump_latency(void)
++{
++	int i, max = 0;
++	int d1, d2, d3, d4, d5;
++
++	printf("T1       T2       T3       T4           d1  d2   t4-t1     i    \n");
++	for (i = 0; i < TSMAX; i++) {
++		d1 = ts[i].t2 - ts[i].t1;
++		d2 = ts[i].t3 - ts[i].t2;
++		d3 = ts[i].t4 - ts[i].t3;
++		d4 = ts[i].t4 - ts[i].t1;
++		d5 = ts[max].t4-ts[max].t1;
++		if (d4 > d5 && d4 > 0)  {
++			max = i;
++		}
++		printf("%08X %08X %08X %08X \t%d %d %d   %d i=%d\n",
++			ts[i].t1, ts[i].t2, ts[i].t3, ts[i].t4,
++			d1, d2, d3, d4, i);
++	}
++
++	printf("current idx = %d \n", tsidx);
++
++	printf("Highest latency %d pkt no.%d total=%d\n", maxdelay, maxdelaypktno, tspktcnt);
++	printf("%08X %08X %08X %08X \t%d %d %d   %d\n",
++	maxdelayts.t1, maxdelayts.t2, maxdelayts.t3, maxdelayts.t4,
++	maxdelayts.t2 - maxdelayts.t1,
++	maxdelayts.t3 - maxdelayts.t2,
++	maxdelayts.t4 - maxdelayts.t3,
++	maxdelayts.t4 - maxdelayts.t1);
++}
++
++
++static int
++dhd_ioctl_htsf_get(dhd_info_t *dhd, int ifidx)
++{
++	char buf[32];
++	int ret;
++	uint32 s1, s2;
++
++	struct tsf {
++		uint32 low;
++		uint32 high;
++	} tsf_buf;
++
++	memset(&tsf_buf, 0, sizeof(tsf_buf));
++
++	s1 = dhd_get_htsf(dhd, 0);
++	ret = dhd_iovar(&dhd->pub, ifidx, "tsf", NULL, 0, buf, sizeof(buf), FALSE);
++	if (ret < 0) {
++		if (ret == -EIO) {
++			DHD_ERROR(("%s: tsf is not supported by device\n",
++				dhd_ifname(&dhd->pub, ifidx)));
++			return -EOPNOTSUPP;
++		}
++		return ret;
++	}
++	s2 = dhd_get_htsf(dhd, 0);
++
++	memcpy(&tsf_buf, buf, sizeof(tsf_buf));
++	printf(" TSF_h=%04X lo=%08X Calc:htsf=%08X, coef=%d.%d%d delta=%d ",
++		tsf_buf.high, tsf_buf.low, s2, dhd->htsf.coef, dhd->htsf.coefdec1,
++		dhd->htsf.coefdec2, s2-tsf_buf.low);
++	printf("lasttsf=%08X lastcycle=%08X\n", dhd->htsf.last_tsf, dhd->htsf.last_cycle);
++	return 0;
++}
++
++void htsf_update(dhd_info_t *dhd, void *data)
++{
++	static ulong  cur_cycle = 0, prev_cycle = 0;
++	uint32 htsf, tsf_delta = 0;
++	uint32 hfactor = 0, cyc_delta, dec1 = 0, dec2, dec3, tmp;
++	ulong b, a;
++	cycles_t t;
++
++	/* cycles_t in inlcude/mips/timex.h */
++
++	t = get_cycles();
++
++	prev_cycle = cur_cycle;
++	cur_cycle = t;
++
++	if (cur_cycle > prev_cycle)
++		cyc_delta = cur_cycle - prev_cycle;
++	else {
++		b = cur_cycle;
++		a = prev_cycle;
++		cyc_delta = cur_cycle + (0xFFFFFFFF - prev_cycle);
++	}
++
++	if (data == NULL)
++		printf(" tsf update ata point er is null \n");
++
++	memcpy(&prev_tsf, &cur_tsf, sizeof(tsf_t));
++	memcpy(&cur_tsf, data, sizeof(tsf_t));
++
++	if (cur_tsf.low == 0) {
++		DHD_INFO((" ---- 0 TSF, do not update, return\n"));
++		return;
++	}
++
++	if (cur_tsf.low > prev_tsf.low)
++		tsf_delta = (cur_tsf.low - prev_tsf.low);
++	else {
++		DHD_INFO((" ---- tsf low is smaller cur_tsf= %08X, prev_tsf=%08X, \n",
++		 cur_tsf.low, prev_tsf.low));
++		if (cur_tsf.high > prev_tsf.high) {
++			tsf_delta = cur_tsf.low + (0xFFFFFFFF - prev_tsf.low);
++			DHD_INFO((" ---- Wrap around tsf coutner  adjusted TSF=%08X\n", tsf_delta));
++		} else {
++			return; /* do not update */
++		}
++	}
++
++	if (tsf_delta)  {
++		hfactor = cyc_delta / tsf_delta;
++		tmp  = 	(cyc_delta - (hfactor * tsf_delta))*10;
++		dec1 =  tmp/tsf_delta;
++		dec2 =  ((tmp - dec1*tsf_delta)*10) / tsf_delta;
++		tmp  = 	(tmp   - (dec1*tsf_delta))*10;
++		dec3 =  ((tmp - dec2*tsf_delta)*10) / tsf_delta;
++
++		if (dec3 > 4) {
++			if (dec2 == 9) {
++				dec2 = 0;
++				if (dec1 == 9) {
++					dec1 = 0;
++					hfactor++;
++				} else {
++					dec1++;
++				}
++			} else {
++				dec2++;
++			}
++		}
++	}
++
++	if (hfactor) {
++		htsf = ((cyc_delta * 10)  / (hfactor*10+dec1)) + prev_tsf.low;
++		dhd->htsf.coef = hfactor;
++		dhd->htsf.last_cycle = cur_cycle;
++		dhd->htsf.last_tsf = cur_tsf.low;
++		dhd->htsf.coefdec1 = dec1;
++		dhd->htsf.coefdec2 = dec2;
++	} else {
++		htsf = prev_tsf.low;
++	}
++}
++
++#endif /* WLMEDIA_HTSF */
++
++#ifdef CUSTOM_SET_CPUCORE
++void dhd_set_cpucore(dhd_pub_t *dhd, int set)
++{
++	int e_dpc = 0, e_rxf = 0, retry_set = 0;
++
++	if (!(dhd->chan_isvht80)) {
++		DHD_ERROR(("%s: chan_status(%d) cpucore!!!\n", __FUNCTION__, dhd->chan_isvht80));
++		return;
++	}
++
++	if (DPC_CPUCORE) {
++		do {
++			if (set == TRUE) {
++				e_dpc = set_cpus_allowed_ptr(dhd->current_dpc,
++					cpumask_of(DPC_CPUCORE));
++			} else {
++				e_dpc = set_cpus_allowed_ptr(dhd->current_dpc,
++					cpumask_of(PRIMARY_CPUCORE));
++			}
++			if (retry_set++ > MAX_RETRY_SET_CPUCORE) {
++				DHD_ERROR(("%s: dpc(%d) invalid cpu!\n", __FUNCTION__, e_dpc));
++				return;
++			}
++			if (e_dpc < 0)
++				OSL_SLEEP(1);
++		} while (e_dpc < 0);
++	}
++	if (RXF_CPUCORE) {
++		do {
++			if (set == TRUE) {
++				e_rxf = set_cpus_allowed_ptr(dhd->current_rxf,
++					cpumask_of(RXF_CPUCORE));
++			} else {
++				e_rxf = set_cpus_allowed_ptr(dhd->current_rxf,
++					cpumask_of(PRIMARY_CPUCORE));
++			}
++			if (retry_set++ > MAX_RETRY_SET_CPUCORE) {
++				DHD_ERROR(("%s: rxf(%d) invalid cpu!\n", __FUNCTION__, e_rxf));
++				return;
++			}
++			if (e_rxf < 0)
++				OSL_SLEEP(1);
++		} while (e_rxf < 0);
++	}
++#ifdef DHD_OF_SUPPORT
++	interrupt_set_cpucore(set, DPC_CPUCORE, PRIMARY_CPUCORE);
++#endif /* DHD_OF_SUPPORT */
++	DHD_TRACE(("%s: set(%d) cpucore success!\n", __FUNCTION__, set));
++
++	return;
++}
++#endif /* CUSTOM_SET_CPUCORE */
++
++#ifdef DHD_MCAST_REGEN
++/* Get interface specific ap_isolate configuration */
++int dhd_get_mcast_regen_bss_enable(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	return ifp->mcast_regen_bss_enable;
++}
++
++/* Set interface specific mcast_regen configuration */
++int dhd_set_mcast_regen_bss_enable(dhd_pub_t *dhdp, uint32 idx, int val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	ifp->mcast_regen_bss_enable = val;
++
++	/* Disable rx_pkt_chain feature for interface, if mcast_regen feature
++	 * is enabled
++	 */
++	dhd_update_rx_pkt_chainable_state(dhdp, idx);
++	return BCME_OK;
++}
++#endif	/* DHD_MCAST_REGEN */
++
++/* Get interface specific ap_isolate configuration */
++int dhd_get_ap_isolate(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	return ifp->ap_isolate;
++}
++
++/* Set interface specific ap_isolate configuration */
++int dhd_set_ap_isolate(dhd_pub_t *dhdp, uint32 idx, int val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	if (ifp)
++		ifp->ap_isolate = val;
++
++	return 0;
++}
++
++#ifdef DHD_FW_COREDUMP
++#if defined(CONFIG_X86)
++#define MEMDUMPINFO_LIVE "/installmedia/.memdump.info"
++#define MEMDUMPINFO_INST "/data/.memdump.info"
++#endif /* CONFIG_X86 && OEM_ANDROID */
++
++#ifdef CUSTOMER_HW4_DEBUG
++#define MEMDUMPINFO PLATFORM_PATH".memdump.info"
++#elif defined(CUSTOMER_HW2)
++#define MEMDUMPINFO "/data/misc/wifi/.memdump.info"
++#elif (defined(BOARD_PANDA) || defined(__ARM_ARCH_7A__))
++#define MEMDUMPINFO "/data/misc/wifi/.memdump.info"
++#else
++#define MEMDUMPINFO "/data/misc/wifi/.memdump.info"
++#endif /* CUSTOMER_HW4_DEBUG */
++
++void dhd_get_memdump_info(dhd_pub_t *dhd)
++{
++	struct file *fp = NULL;
++	uint32 mem_val = DUMP_MEMFILE_MAX;
++	int ret = 0;
++	char *filepath = MEMDUMPINFO;
++
++	/* Read memdump info from the file */
++	fp = filp_open(filepath, O_RDONLY, 0);
++	if (IS_ERR(fp)) {
++		DHD_ERROR(("%s: File [%s] doesn't exist\n", __FUNCTION__, filepath));
++#if defined(CONFIG_X86)
++		/* Check if it is Live Brix Image */
++		if (strcmp(filepath, MEMDUMPINFO_LIVE) != 0) {
++			goto done;
++		}
++		/* Try if it is Installed Brix Image */
++		filepath = MEMDUMPINFO_INST;
++		DHD_ERROR(("%s: Try File [%s]\n", __FUNCTION__, filepath));
++		fp = filp_open(filepath, O_RDONLY, 0);
++		if (IS_ERR(fp)) {
++			DHD_ERROR(("%s: File [%s] doesn't exist\n", __FUNCTION__, filepath));
++			goto done;
++		}
++#else /* Non Brix Android platform */
++		goto done;
++#endif /* CONFIG_X86 && OEM_ANDROID */
++	}
++
++	/* Handle success case */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++	ret = kernel_read(fp, (char *)&mem_val, 4, NULL);
++#else
++	ret = kernel_read(fp, 0, (char *)&mem_val, 4);
++#endif
++	if (ret < 0) {
++		DHD_ERROR(("%s: File read error, ret=%d\n", __FUNCTION__, ret));
++		filp_close(fp, NULL);
++		goto done;
++	}
++
++	mem_val = bcm_atoi((char *)&mem_val);
++
++	filp_close(fp, NULL);
++
++#ifdef DHD_INIT_DEFAULT_MEMDUMP
++	if (mem_val == 0 || mem_val == DUMP_MEMFILE_MAX)
++		mem_val = DUMP_MEMFILE_BUGON;
++#endif /* DHD_INIT_DEFAULT_MEMDUMP */
++
++done:
++#ifdef CUSTOMER_HW4_DEBUG
++	dhd->memdump_enabled = (mem_val < DUMP_MEMFILE_MAX) ? mem_val : DUMP_DISABLED;
++#else
++	dhd->memdump_enabled = (mem_val < DUMP_MEMFILE_MAX) ? mem_val : DUMP_MEMFILE;
++#endif /* CUSTOMER_HW4_DEBUG */
++
++	DHD_ERROR(("%s: MEMDUMP ENABLED = %d\n", __FUNCTION__, dhd->memdump_enabled));
++}
++
++void dhd_schedule_memdump(dhd_pub_t *dhdp, uint8 *buf, uint32 size)
++{
++	dhd_dump_t *dump = NULL;
++	dump = (dhd_dump_t *)MALLOC(dhdp->osh, sizeof(dhd_dump_t));
++	if (dump == NULL) {
++		DHD_ERROR(("%s: dhd dump memory allocation failed\n", __FUNCTION__));
++		return;
++	}
++	dump->buf = buf;
++	dump->bufsize = size;
++
++#if defined(CONFIG_ARM64)
++	DHD_ERROR(("%s: buf(va)=%llx, buf(pa)=%llx, bufsize=%d\n", __FUNCTION__,
++		(uint64)buf, (uint64)__virt_to_phys((ulong)buf), size));
++#elif defined(__ARM_ARCH_7A__)
++	DHD_ERROR(("%s: buf(va)=%x, buf(pa)=%x, bufsize=%d\n", __FUNCTION__,
++		(uint32)buf, (uint32)__virt_to_phys((ulong)buf), size));
++#endif /* __ARM_ARCH_7A__ */
++	if (dhdp->memdump_enabled == DUMP_MEMONLY) {
++		BUG_ON(1);
++	}
++
++#ifdef DHD_LOG_DUMP
++	if (dhdp->memdump_type != DUMP_TYPE_BY_SYSDUMP) {
++		dhd_schedule_log_dump(dhdp);
++	}
++#endif /* DHD_LOG_DUMP */
++	dhd_deferred_schedule_work(dhdp->info->dhd_deferred_wq, (void *)dump,
++		DHD_WQ_WORK_SOC_RAM_DUMP, dhd_mem_dump, DHD_WQ_WORK_PRIORITY_HIGH);
++}
++
++static void
++dhd_mem_dump(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++	dhd_dump_t *dump = event_info;
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (!dump) {
++		DHD_ERROR(("%s: dump is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (write_dump_to_file(&dhd->pub, dump->buf, dump->bufsize, "mem_dump")) {
++		DHD_ERROR(("%s: writing SoC_RAM dump to the file failed\n", __FUNCTION__));
++		dhd->pub.memdump_success = FALSE;
++	}
++
++	if (dhd->pub.memdump_enabled == DUMP_MEMFILE_BUGON &&
++#ifdef DHD_LOG_DUMP
++		dhd->pub.memdump_type != DUMP_TYPE_BY_SYSDUMP &&
++#endif /* DHD_LOG_DUMP */
++#ifdef DHD_DEBUG_UART
++		dhd->pub.memdump_success == TRUE &&
++#endif	/* DHD_DEBUG_UART */
++		dhd->pub.memdump_type != DUMP_TYPE_CFG_VENDOR_TRIGGERED) {
++
++#ifdef SHOW_LOGTRACE
++		/* Wait till event_log_dispatcher_work finishes */
++		cancel_work_sync(&dhd->event_log_dispatcher_work);
++#endif /* SHOW_LOGTRACE */
++
++		BUG_ON(1);
++	}
++	MFREE(dhd->pub.osh, dump, sizeof(dhd_dump_t));
++}
++#endif /* DHD_FW_COREDUMP */
++
++#ifdef DHD_SSSR_DUMP
++
++static void
++dhd_sssr_dump(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++	dhd_pub_t *dhdp;
++	int i;
++	char before_sr_dump[128];
++	char after_sr_dump[128];
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	dhdp = &dhd->pub;
++
++	for (i = 0; i < MAX_NUM_D11CORES; i++) {
++		/* Init file name */
++		memset(before_sr_dump, 0, sizeof(before_sr_dump));
++		memset(after_sr_dump, 0, sizeof(after_sr_dump));
++
++		snprintf(before_sr_dump, sizeof(before_sr_dump), "%s_%d_%s",
++			"sssr_core", i, "before_SR");
++		snprintf(after_sr_dump, sizeof(after_sr_dump), "%s_%d_%s",
++			"sssr_core", i, "after_SR");
++
++		if (dhdp->sssr_d11_before[i] && dhdp->sssr_d11_outofreset[i]) {
++			if (write_dump_to_file(dhdp, (uint8 *)dhdp->sssr_d11_before[i],
++				dhdp->sssr_reg_info.mac_regs[i].sr_size, before_sr_dump)) {
++				DHD_ERROR(("%s: writing SSSR MAIN dump before to the file failed\n",
++					__FUNCTION__));
++			}
++		}
++		if (dhdp->sssr_d11_after[i] && dhdp->sssr_d11_outofreset[i]) {
++			if (write_dump_to_file(dhdp, (uint8 *)dhdp->sssr_d11_after[i],
++				dhdp->sssr_reg_info.mac_regs[i].sr_size, after_sr_dump)) {
++				DHD_ERROR(("%s: writing SSSR AUX dump after to the file failed\n",
++					__FUNCTION__));
++			}
++		}
++	}
++
++	if (dhdp->sssr_vasip_buf_before) {
++		if (write_dump_to_file(dhdp, (uint8 *)dhdp->sssr_vasip_buf_before,
++			dhdp->sssr_reg_info.vasip_regs.vasip_sr_size, "sssr_vasip_before_SR")) {
++			DHD_ERROR(("%s: writing SSSR VASIP dump before to the file failed\n",
++				__FUNCTION__));
++		}
++	}
++
++	if (dhdp->sssr_vasip_buf_after) {
++		if (write_dump_to_file(dhdp, (uint8 *)dhdp->sssr_vasip_buf_after,
++			dhdp->sssr_reg_info.vasip_regs.vasip_sr_size, "sssr_vasip_after_SR")) {
++			DHD_ERROR(("%s: writing SSSR VASIP dump after to the file failed\n",
++				__FUNCTION__));
++		}
++	}
++
++}
++
++void
++dhd_schedule_sssr_dump(dhd_pub_t *dhdp)
++{
++	dhd_deferred_schedule_work(dhdp->info->dhd_deferred_wq, NULL,
++		DHD_WQ_WORK_SSSR_DUMP, dhd_sssr_dump, DHD_WQ_WORK_PRIORITY_HIGH);
++}
++#endif /* DHD_SSSR_DUMP */
++
++#ifdef DHD_LOG_DUMP
++static void
++dhd_log_dump(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (do_dhd_log_dump(&dhd->pub)) {
++		DHD_ERROR(("%s: writing debug dump to the file failed\n", __FUNCTION__));
++		return;
++	}
++}
++
++void dhd_schedule_log_dump(dhd_pub_t *dhdp)
++{
++	dhd_deferred_schedule_work(dhdp->info->dhd_deferred_wq,
++		(void*)NULL, DHD_WQ_WORK_DHD_LOG_DUMP,
++		dhd_log_dump, DHD_WQ_WORK_PRIORITY_HIGH);
++}
++
++static int
++do_dhd_log_dump(dhd_pub_t *dhdp)
++{
++	int ret = 0, i = 0;
++	struct file *fp = NULL;
++	mm_segment_t old_fs;
++	loff_t pos = 0;
++	unsigned int wr_size = 0;
++	char dump_path[128];
++	struct osl_timespec curtime;
++	uint32 file_mode;
++	unsigned long flags = 0;
++	struct dhd_log_dump_buf *dld_buf = &g_dld_buf[0];
++
++	const char *pre_strs =
++		"-------------------- General log ---------------------------\n";
++
++	const char *post_strs =
++		"-------------------- Specific log --------------------------\n";
++
++	if (!dhdp) {
++		return -1;
++	}
++
++	DHD_ERROR(("DHD version: %s\n", dhd_version));
++	DHD_ERROR(("F/W version: %s\n", fw_version));
++
++	/* change to KERNEL_DS address limit */
++	old_fs = get_fs();
++	set_fs(KERNEL_DS);
++
++	/* Init file name */
++	memset(dump_path, 0, sizeof(dump_path));
++	osl_do_gettimeofday(&curtime);
++	snprintf(dump_path, sizeof(dump_path), "%s_%ld.%ld",
++		DHD_COMMON_DUMP_PATH "debug_dump",
++		(unsigned long)curtime.tv_sec, (unsigned long)curtime.tv_usec);
++	file_mode = O_CREAT | O_WRONLY | O_SYNC;
++
++	DHD_ERROR(("debug_dump_path = %s\n", dump_path));
++	fp = filp_open(dump_path, file_mode, 0664);
++	if (IS_ERR(fp)) {
++		ret = PTR_ERR(fp);
++		DHD_ERROR(("open file error, err = %d\n", ret));
++		goto exit;
++	}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++	ret = kernel_write(fp, pre_strs, strlen(pre_strs), &pos);
++#else
++	ret = vfs_write(fp, pre_strs, strlen(pre_strs), &pos);
++#endif
++	if (ret < 0) {
++		DHD_ERROR(("write file error, err = %d\n", ret));
++		goto exit;
++	}
++
++	do {
++		unsigned int buf_size = (unsigned int)(dld_buf->max -
++			(unsigned long)dld_buf->buffer);
++		if (dld_buf->wraparound) {
++			wr_size = buf_size;
++		} else {
++			if (!dld_buf->buffer[0]) { /* print log if buf is empty. */
++				DHD_ERROR_EX(("Buffer is empty. No event/log.\n"));
++			}
++			wr_size = (unsigned int)(dld_buf->present - dld_buf->front);
++		}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++		ret = kernel_write(fp, dld_buf->buffer, wr_size, &pos);
++#else
++		ret = vfs_write(fp, dld_buf->buffer, wr_size, &pos);
++#endif
++		if (ret < 0) {
++			DHD_ERROR(("write file error, err = %d\n", ret));
++			goto exit;
++		}
++
++		/* re-init dhd_log_dump_buf structure */
++		spin_lock_irqsave(&dld_buf->lock, flags);
++		dld_buf->wraparound = 0;
++		dld_buf->present = dld_buf->front;
++		dld_buf->remain = buf_size;
++		bzero(dld_buf->buffer, buf_size);
++		spin_unlock_irqrestore(&dld_buf->lock, flags);
++		ret = BCME_OK;
++
++		if (++i < DLD_BUFFER_NUM) {
++			dld_buf = &g_dld_buf[i];
++		} else {
++			break;
++		}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++		ret = kernel_write(fp, post_strs, strlen(post_strs), &pos);
++#else
++		ret = vfs_write(fp, post_strs, strlen(post_strs), &pos);
++#endif
++		if (ret < 0) {
++			DHD_ERROR(("write file error, err = %d\n", ret));
++			goto exit;
++		}
++	} while (1);
++
++exit:
++#if defined(STAT_REPORT)
++	if (!IS_ERR(fp) && ret >= 0) {
++		wl_stat_report_file_save(dhdp, fp);
++	}
++#endif /* STAT_REPORT */
++
++	if (!IS_ERR(fp)) {
++		filp_close(fp, NULL);
++	}
++	set_fs(old_fs);
++
++	return ret;
++}
++#endif /* DHD_LOG_DUMP */
++
++
++#ifdef BCMASSERT_LOG
++#ifdef CUSTOMER_HW4_DEBUG
++#define ASSERTINFO PLATFORM_PATH".assert.info"
++#elif defined(CUSTOMER_HW2)
++#define ASSERTINFO "/data/misc/wifi/.assert.info"
++#else
++#define ASSERTINFO "/installmedia/.assert.info"
++#endif /* CUSTOMER_HW4_DEBUG */
++void dhd_get_assert_info(dhd_pub_t *dhd)
++{
++	struct file *fp = NULL;
++	char *filepath = ASSERTINFO;
++	int mem_val = -1;
++
++	/*
++	 * Read assert info from the file
++	 * 0: Trigger Kernel crash by panic()
++	 * 1: Print out the logs and don't trigger Kernel panic. (default)
++	 * 2: Trigger Kernel crash by BUG()
++	 * File doesn't exist: Keep default value (1).
++	 */
++	fp = filp_open(filepath, O_RDONLY, 0);
++	if (IS_ERR(fp)) {
++		DHD_ERROR(("%s: File [%s] doesn't exist\n", __FUNCTION__, filepath));
++	} else {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++		ssize_t ret = kernel_read(fp, (char *)&mem_val, 4, NULL);
++#else
++		int ret = kernel_read(fp, 0, (char *)&mem_val, 4);
++#endif
++		if (ret < 0) {
++			DHD_ERROR(("%s: File read error, ret=%d\n", __FUNCTION__, ret));
++		} else {
++			mem_val = bcm_atoi((char *)&mem_val);
++			DHD_ERROR(("%s: ASSERT ENABLED = %d\n", __FUNCTION__, mem_val));
++		}
++		filp_close(fp, NULL);
++	}
++#ifdef CUSTOMER_HW4_DEBUG
++		/* By default. set to 1, No Kernel Panic */
++		g_assert_type = (mem_val >= 0) ? mem_val : 1;
++#else
++		/* By default. set to 0, Kernel Panic */
++		g_assert_type = (mem_val >= 0) ? mem_val : 0;
++#endif
++}
++#endif /* BCMASSERT_LOG */
++
++/*
++ * This call is to get the memdump size so that,
++ * halutil can alloc that much buffer in user space.
++ */
++int
++dhd_os_socram_dump(struct net_device *dev, uint32 *dump_size)
++{
++	int ret = BCME_OK;
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	dhd_pub_t *dhdp = &dhd->pub;
++
++	if (dhdp->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s: bus is down\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	if (DHD_BUS_CHECK_SUSPEND_OR_SUSPEND_IN_PROGRESS(dhdp)) {
++		DHD_ERROR(("%s: bus is in suspend(%d) or suspending(0x%x) state, so skip\n",
++			__FUNCTION__, dhdp->busstate, dhdp->dhd_bus_busy_state));
++		return BCME_ERROR;
++	}
++
++	ret = dhd_common_socram_dump(dhdp);
++	if (ret == BCME_OK) {
++		*dump_size = dhdp->soc_ram_length;
++	}
++	return ret;
++}
++
++/*
++ * This is to get the actual memdup after getting the memdump size
++ */
++int
++dhd_os_get_socram_dump(struct net_device *dev, char **buf, uint32 *size)
++{
++	int ret = BCME_OK;
++	int orig_len = 0;
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	dhd_pub_t *dhdp = &dhd->pub;
++	if (buf == NULL)
++		return BCME_ERROR;
++	orig_len = *size;
++	if (dhdp->soc_ram) {
++		if (orig_len >= dhdp->soc_ram_length) {
++			memcpy(*buf, dhdp->soc_ram, dhdp->soc_ram_length);
++			/* reset the storage of dump */
++			memset(dhdp->soc_ram, 0, dhdp->soc_ram_length);
++			*size = dhdp->soc_ram_length;
++		} else {
++			ret = BCME_BUFTOOSHORT;
++			DHD_ERROR(("The length of the buffer is too short"
++				" to save the memory dump with %d\n", dhdp->soc_ram_length));
++		}
++	} else {
++		DHD_ERROR(("socram_dump is not ready to get\n"));
++		ret = BCME_NOTREADY;
++	}
++	return ret;
++}
++
++int
++dhd_os_get_version(struct net_device *dev, bool dhd_ver, char **buf, uint32 size)
++{
++	char *fw_str;
++
++	if (size == 0)
++		return BCME_BADARG;
++
++	fw_str = strstr(info_string, "Firmware: ");
++	if (fw_str == NULL) {
++		return BCME_ERROR;
++	}
++
++	memset(*buf, 0, size);
++	if (dhd_ver) {
++		strncpy(*buf, dhd_version, size - 1);
++	} else {
++		strncpy(*buf, fw_str, size - 1);
++	}
++	return BCME_OK;
++}
++
++#ifdef DHD_WMF
++/* Returns interface specific WMF configuration */
++dhd_wmf_t* dhd_wmf_conf(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++	return &ifp->wmf;
++}
++#endif /* DHD_WMF */
++
++#if defined(TRAFFIC_MGMT_DWM)
++void traffic_mgmt_pkt_set_prio(dhd_pub_t *dhdp, void * pktbuf)
++{
++	struct ether_header *eh;
++	struct ethervlan_header *evh;
++	uint8 *pktdata, *ip_body;
++	uint8  dwm_filter;
++	uint8 tos_tc = 0;
++	uint8 dscp   = 0;
++	pktdata = (uint8 *)PKTDATA(dhdp->osh, pktbuf);
++	eh = (struct ether_header *) pktdata;
++	ip_body = NULL;
++
++	if (dhdp->dhd_tm_dwm_tbl.dhd_dwm_enabled) {
++		if (eh->ether_type == hton16(ETHER_TYPE_8021Q)) {
++			evh = (struct ethervlan_header *)eh;
++			if ((evh->ether_type == hton16(ETHER_TYPE_IP)) ||
++				(evh->ether_type == hton16(ETHER_TYPE_IPV6))) {
++				ip_body = pktdata + sizeof(struct ethervlan_header);
++			}
++		} else if ((eh->ether_type == hton16(ETHER_TYPE_IP)) ||
++			(eh->ether_type == hton16(ETHER_TYPE_IPV6))) {
++			ip_body = pktdata + sizeof(struct ether_header);
++		}
++		if (ip_body) {
++			tos_tc = IP_TOS46(ip_body);
++			dscp = tos_tc >> IPV4_TOS_DSCP_SHIFT;
++		}
++
++		if (dscp < DHD_DWM_TBL_SIZE) {
++			dwm_filter = dhdp->dhd_tm_dwm_tbl.dhd_dwm_tbl[dscp];
++			if (DHD_TRF_MGMT_DWM_IS_FILTER_SET(dwm_filter)) {
++				PKTSETPRIO(pktbuf, DHD_TRF_MGMT_DWM_PRIO(dwm_filter));
++			}
++		}
++	}
++}
++#endif 
++
++bool dhd_sta_associated(dhd_pub_t *dhdp, uint32 bssidx, uint8 *mac)
++{
++	return dhd_find_sta(dhdp, bssidx, mac) ? TRUE : FALSE;
++}
++
++#ifdef DHD_L2_FILTER
++arp_table_t*
++dhd_get_ifp_arp_table_handle(dhd_pub_t *dhdp, uint32 bssidx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(bssidx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[bssidx];
++	return ifp->phnd_arp_table;
++}
++
++int dhd_get_parp_status(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	if (ifp)
++		return ifp->parp_enable;
++	else
++		return FALSE;
++}
++
++/* Set interface specific proxy arp configuration */
++int dhd_set_parp_status(dhd_pub_t *dhdp, uint32 idx, int val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++	ASSERT(idx < DHD_MAX_IFS);
++	ifp = dhd->iflist[idx];
++
++	if (!ifp)
++	    return BCME_ERROR;
++
++	/* At present all 3 variables are being
++	 * handled at once
++	 */
++	ifp->parp_enable = val;
++	ifp->parp_discard = val;
++	ifp->parp_allnode = val;
++
++	/* Flush ARP entries when disabled */
++	if (val == FALSE) {
++		bcm_l2_filter_arp_table_update(dhdp->osh, ifp->phnd_arp_table, TRUE, NULL,
++			FALSE, dhdp->tickcnt);
++	}
++	return BCME_OK;
++}
++
++bool dhd_parp_discard_is_enabled(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	ASSERT(ifp);
++	return ifp->parp_discard;
++}
++
++bool
++dhd_parp_allnode_is_enabled(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	ASSERT(ifp);
++
++	return ifp->parp_allnode;
++}
++
++int dhd_get_dhcp_unicast_status(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	ASSERT(ifp);
++
++	return ifp->dhcp_unicast;
++}
++
++int dhd_set_dhcp_unicast_status(dhd_pub_t *dhdp, uint32 idx, int val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++	ASSERT(idx < DHD_MAX_IFS);
++	ifp = dhd->iflist[idx];
++
++	ASSERT(ifp);
++
++	ifp->dhcp_unicast = val;
++	return BCME_OK;
++}
++
++int dhd_get_block_ping_status(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	ASSERT(ifp);
++
++	return ifp->block_ping;
++}
++
++int dhd_set_block_ping_status(dhd_pub_t *dhdp, uint32 idx, int val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++	ASSERT(idx < DHD_MAX_IFS);
++	ifp = dhd->iflist[idx];
++
++	ASSERT(ifp);
++
++	ifp->block_ping = val;
++	/* Disable rx_pkt_chain feature for interface if block_ping option is
++	 * enabled
++	 */
++	dhd_update_rx_pkt_chainable_state(dhdp, idx);
++	return BCME_OK;
++}
++
++int dhd_get_grat_arp_status(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	ASSERT(ifp);
++
++	return ifp->grat_arp;
++}
++
++int dhd_set_grat_arp_status(dhd_pub_t *dhdp, uint32 idx, int val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++	ASSERT(idx < DHD_MAX_IFS);
++	ifp = dhd->iflist[idx];
++
++	ASSERT(ifp);
++
++	ifp->grat_arp = val;
++
++	return BCME_OK;
++}
++#endif /* DHD_L2_FILTER */
++
++
++#if defined(SET_RPS_CPUS)
++int dhd_rps_cpus_enable(struct net_device *net, int enable)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(net);
++	dhd_if_t *ifp;
++	int ifidx;
++	char * RPS_CPU_SETBUF;
++
++	ifidx = dhd_net2idx(dhd, net);
++	if (ifidx == DHD_BAD_IF) {
++		DHD_ERROR(("%s bad ifidx\n", __FUNCTION__));
++		return -ENODEV;
++	}
++
++	if (ifidx == PRIMARY_INF) {
++		if (dhd->pub.op_mode == DHD_FLAG_IBSS_MODE) {
++			DHD_INFO(("%s : set for IBSS.\n", __FUNCTION__));
++			RPS_CPU_SETBUF = RPS_CPUS_MASK_IBSS;
++		} else {
++			DHD_INFO(("%s : set for BSS.\n", __FUNCTION__));
++			RPS_CPU_SETBUF = RPS_CPUS_MASK;
++		}
++	} else if (ifidx == VIRTUAL_INF) {
++		DHD_INFO(("%s : set for P2P.\n", __FUNCTION__));
++		RPS_CPU_SETBUF = RPS_CPUS_MASK_P2P;
++	} else {
++		DHD_ERROR(("%s : Invalid index : %d.\n", __FUNCTION__, ifidx));
++		return -EINVAL;
++	}
++
++	ifp = dhd->iflist[ifidx];
++	if (ifp) {
++		if (enable) {
++			DHD_INFO(("%s : set rps_cpus as [%s]\n", __FUNCTION__, RPS_CPU_SETBUF));
++			custom_rps_map_set(ifp->net->_rx, RPS_CPU_SETBUF, strlen(RPS_CPU_SETBUF));
++		} else {
++			custom_rps_map_clear(ifp->net->_rx);
++		}
++	} else {
++		DHD_ERROR(("%s : ifp is NULL!!\n", __FUNCTION__));
++		return -ENODEV;
++	}
++	return BCME_OK;
++}
++
++int custom_rps_map_set(struct netdev_rx_queue *queue, char *buf, size_t len)
++{
++	struct rps_map *old_map, *map;
++	cpumask_var_t mask;
++	int err, cpu, i;
++	static DEFINE_SPINLOCK(rps_map_lock);
++
++	DHD_INFO(("%s : Entered.\n", __FUNCTION__));
++
++	if (!alloc_cpumask_var(&mask, GFP_KERNEL)) {
++		DHD_ERROR(("%s : alloc_cpumask_var fail.\n", __FUNCTION__));
++		return -ENOMEM;
++	}
++
++	err = bitmap_parse(buf, len, cpumask_bits(mask), nr_cpumask_bits);
++	if (err) {
++		free_cpumask_var(mask);
++		DHD_ERROR(("%s : bitmap_parse fail.\n", __FUNCTION__));
++		return err;
++	}
++
++	map = kzalloc(max_t(unsigned int,
++		RPS_MAP_SIZE(cpumask_weight(mask)), L1_CACHE_BYTES),
++		GFP_KERNEL);
++	if (!map) {
++		free_cpumask_var(mask);
++		DHD_ERROR(("%s : map malloc fail.\n", __FUNCTION__));
++		return -ENOMEM;
++	}
++
++	i = 0;
++	for_each_cpu(cpu, mask) {
++		map->cpus[i++] = cpu;
++	}
++
++	if (i) {
++		map->len = i;
++	} else {
++		kfree(map);
++		map = NULL;
++		free_cpumask_var(mask);
++		DHD_ERROR(("%s : mapping cpu fail.\n", __FUNCTION__));
++		return -1;
++	}
++
++	spin_lock(&rps_map_lock);
++	old_map = rcu_dereference_protected(queue->rps_map,
++		lockdep_is_held(&rps_map_lock));
++	rcu_assign_pointer(queue->rps_map, map);
++	spin_unlock(&rps_map_lock);
++
++	if (map) {
++		static_key_slow_inc(&rps_needed);
++	}
++	if (old_map) {
++		kfree_rcu(old_map, rcu);
++		static_key_slow_dec(&rps_needed);
++	}
++	free_cpumask_var(mask);
++
++	DHD_INFO(("%s : Done. mapping cpu nummber : %d\n", __FUNCTION__, map->len));
++	return map->len;
++}
++
++void custom_rps_map_clear(struct netdev_rx_queue *queue)
++{
++	struct rps_map *map;
++
++	DHD_INFO(("%s : Entered.\n", __FUNCTION__));
++
++	map = rcu_dereference_protected(queue->rps_map, 1);
++	if (map) {
++		RCU_INIT_POINTER(queue->rps_map, NULL);
++		kfree_rcu(map, rcu);
++		DHD_INFO(("%s : rps_cpus map clear.\n", __FUNCTION__));
++	}
++}
++#endif 
++
++
++
++#ifdef DHD_DEBUG_PAGEALLOC
++
++void
++dhd_page_corrupt_cb(void *handle, void *addr_corrupt, size_t len)
++{
++	dhd_pub_t *dhdp = (dhd_pub_t *)handle;
++
++	DHD_ERROR(("%s: Got dhd_page_corrupt_cb 0x%p %d\n",
++		__FUNCTION__, addr_corrupt, (uint32)len));
++
++	DHD_OS_WAKE_LOCK(dhdp);
++	prhex("Page Corruption:", addr_corrupt, len);
++	dhd_dump_to_kernelog(dhdp);
++#if defined(BCMPCIE) && defined(DHD_FW_COREDUMP)
++	/* Load the dongle side dump to host memory and then BUG_ON() */
++	dhdp->memdump_enabled = DUMP_MEMONLY;
++	dhdp->memdump_type = DUMP_TYPE_MEMORY_CORRUPTION;
++	dhd_bus_mem_dump(dhdp);
++#endif /* BCMPCIE && DHD_FW_COREDUMP */
++	DHD_OS_WAKE_UNLOCK(dhdp);
++}
++EXPORT_SYMBOL(dhd_page_corrupt_cb);
++#endif /* DHD_DEBUG_PAGEALLOC */
++
++#if defined(BCMPCIE) && defined(DHD_PKTID_AUDIT_ENABLED)
++void
++dhd_pktid_error_handler(dhd_pub_t *dhdp)
++{
++	DHD_ERROR(("%s: Got Pkt Id Audit failure \n", __FUNCTION__));
++	DHD_OS_WAKE_LOCK(dhdp);
++	dhd_dump_to_kernelog(dhdp);
++#ifdef DHD_FW_COREDUMP
++	/* Load the dongle side dump to host memory */
++	if (dhdp->memdump_enabled == DUMP_DISABLED) {
++		dhdp->memdump_enabled = DUMP_MEMFILE;
++	}
++	dhdp->memdump_type = DUMP_TYPE_PKTID_AUDIT_FAILURE;
++	dhd_bus_mem_dump(dhdp);
++#endif /* DHD_FW_COREDUMP */
++	dhdp->hang_reason = HANG_REASON_PCIE_PKTID_ERROR;
++	dhd_os_check_hang(dhdp, 0, -EREMOTEIO);
++	DHD_OS_WAKE_UNLOCK(dhdp);
++}
++#endif /* BCMPCIE && DHD_PKTID_AUDIT_ENABLED */
++
++struct net_device *
++dhd_linux_get_primary_netdev(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++
++	if (dhd->iflist[0] && dhd->iflist[0]->net)
++		return dhd->iflist[0]->net;
++	else
++		return NULL;
++}
++
++#ifdef DHD_ARP_DUMP
++#define ARP_PRINT(str) \
++	do { \
++		printk("[dhd-%s] " str " [%s] : %s(%s) %s %s(%s)\n", \
++			ifname, tx?"TX":"RX", \
++			tx?sabuf:dabuf, tx?seabuf:deabuf, \
++			tx?"->":"<-", tx?dabuf:sabuf, tx?deabuf:seabuf); \
++	} while (0)
++
++#define ARP_PRINT_OTHER(str) \
++	do { \
++		printk("[dhd-%s] " str " [%s] : %s(%s) %s %s(%s) op_code=%d\n", \
++			ifname, tx?"TX":"RX", \
++			tx?sabuf:dabuf, tx?seabuf:deabuf, \
++			tx?"->":"<-", tx?dabuf:sabuf, tx?deabuf:seabuf, opcode); \
++	} while (0)
++
++static void
++dhd_arp_dump(char *ifname, uint8 *pktdata, bool tx)
++{
++	uint8 *pkt = (uint8 *)&pktdata[ETHER_HDR_LEN];
++	struct bcmarp *arph = (struct bcmarp *)pkt;
++	uint16 opcode;
++	char sabuf[20]="", dabuf[20]="";
++	char seabuf[ETHER_ADDR_STR_LEN]="";
++	char deabuf[ETHER_ADDR_STR_LEN]="";
++
++	if (!(dump_msg_level & DUMP_ARP_VAL))
++		return;
++
++	/* validation check */
++	if (arph->htype != hton16(HTYPE_ETHERNET) ||
++		arph->hlen != ETHER_ADDR_LEN ||
++		arph->plen != 4) {
++		return;
++	}
++
++	opcode = ntoh16(arph->oper);
++	bcm_ip_ntoa((struct ipv4_addr *)arph->src_ip, sabuf);
++	bcm_ip_ntoa((struct ipv4_addr *)arph->dst_ip, dabuf);
++	bcm_ether_ntoa((struct ether_addr *)arph->dst_eth, deabuf);
++	bcm_ether_ntoa((struct ether_addr *)arph->src_eth, seabuf);
++	if (opcode == ARP_OPC_REQUEST) {
++		ARP_PRINT("ARP REQUEST ");
++	} else if (opcode == ARP_OPC_REPLY) {
++		ARP_PRINT("ARP RESPONSE");
++	} else {
++		ARP_PRINT_OTHER("ARP OTHER");
++	}
++}
++#endif /* DHD_ARP_DUMP */
++
++#ifdef DHD_DHCP_DUMP
++#define DHCP_PRINT(str) \
++	do { \
++		printk("[dhd-%s] " str " %8s, %8s [%s] : %s(%s) %s %s(%s)\n", \
++			ifname, dhcp_types[dhcp_type], dhcp_ops[b->op], \
++			tx?"TX":"RX", \
++			tx?sabuf:dabuf, tx?seabuf:deabuf, \
++			tx?"->":"<-", tx?dabuf:sabuf, tx?deabuf:seabuf); \
++	} while (0)
++static void
++dhd_dhcp_dump(char *ifname, uint8 *pktdata, bool tx)
++{
++	struct bootp_fmt *b = (struct bootp_fmt *) &pktdata[ETHER_HDR_LEN];
++	struct iphdr *h = &b->ip_header;
++	uint8 *ptr, *opt, *end = (uint8 *) b + ntohs(b->ip_header.tot_len);
++	int dhcp_type = 0, len, opt_len;
++	uint32 ip_saddr, ip_daddr;
++	char sabuf[20]="", dabuf[20]="";
++	char seabuf[ETHER_ADDR_STR_LEN]="";
++	char deabuf[ETHER_ADDR_STR_LEN]="";
++
++	if (!(dump_msg_level & DUMP_DHCP_VAL))
++		return;
++
++	/* check IP header */
++	if (h->ihl != 5 || h->version != 4 || h->protocol != IPPROTO_UDP) {
++		return;
++	}
++
++	/* check UDP port for bootp (67, 68) */
++	if (b->udp_header.source != htons(67) && b->udp_header.source != htons(68) &&
++			b->udp_header.dest != htons(67) && b->udp_header.dest != htons(68)) {
++		return;
++	}
++
++	/* check header length */
++	if (ntohs(h->tot_len) < ntohs(b->udp_header.len) + sizeof(struct iphdr)) {
++		return;
++	}
++	ip_saddr = h->saddr;
++	ip_daddr = h->daddr;
++	bcm_ip_ntoa((struct ipv4_addr *)&ip_saddr, sabuf);
++	bcm_ip_ntoa((struct ipv4_addr *)&ip_daddr, dabuf);
++	bcm_ether_ntoa((struct ether_addr *)pktdata, deabuf);
++	bcm_ether_ntoa((struct ether_addr *)(pktdata+6), seabuf);
++
++	len = ntohs(b->udp_header.len) - sizeof(struct udphdr);
++	opt_len = len
++		- (sizeof(*b) - sizeof(struct iphdr) - sizeof(struct udphdr) - sizeof(b->options));
++
++	/* parse bootp options */
++	if (opt_len >= 4 && !memcmp(b->options, bootp_magic_cookie, 4)) {
++		ptr = &b->options[4];
++		while (ptr < end && *ptr != 0xff) {
++			opt = ptr++;
++			if (*opt == 0) {
++				continue;
++			}
++			ptr += *ptr + 1;
++			if (ptr >= end) {
++				break;
++			}
++			/* 53 is dhcp type */
++			if (*opt == 53) {
++				if (opt[1]) {
++					dhcp_type = opt[2];
++					DHCP_PRINT("DHCP");
++					break;
++				}
++			}
++		}
++	}
++}
++#endif /* DHD_DHCP_DUMP */
++
++#ifdef DHD_ICMP_DUMP
++#define ICMP_TYPE_ECHO_REQUEST	8	/* ICMP type echo request */
++#define ICMP_TYPE_ECHO_REPLY		0	/* ICMP type echo reply */
++#define ICMP_TYPE_DEST_UNREACH		3
++#define ICMP_ECHO_SEQ_OFFSET		6
++#define ICMP_ECHO_SEQ(h) (*(uint16 *)((uint8 *)(h) + (ICMP_ECHO_SEQ_OFFSET)))
++#define ICMP_PING_PRINT(str) \
++	do { \
++		printk("[dhd-%s] " str " [%2s] : %s(%s) %s %s(%s) SEQNUM=%d\n", \
++			ifname, tx?"TX":"RX", tx?sabuf:dabuf, tx?seabuf:deabuf, \
++			tx?"->":"<-", tx?dabuf:sabuf, tx?deabuf:seabuf, seqnum); \
++	} while (0)
++#define ICMP_PRINT(str) \
++	do { \
++		printk("[dhd-%s] " str " [%2s] : %s(%s) %s %s(%s)\n", \
++			ifname, tx?"TX":"RX", tx?sabuf:dabuf, tx?seabuf:deabuf, \
++			tx?"->":"<-", tx?dabuf:sabuf, tx?deabuf:seabuf); \
++	} while (0)
++static void
++dhd_icmp_dump(char *ifname, uint8 *pktdata, bool tx)
++{
++	uint8 *pkt = (uint8 *)&pktdata[ETHER_HDR_LEN];
++	struct iphdr *iph = (struct iphdr *)pkt;
++	struct icmphdr *icmph;
++	uint32 ip_saddr, ip_daddr;
++	char sabuf[20]="", dabuf[20]="";
++	char seabuf[ETHER_ADDR_STR_LEN]="";
++	char deabuf[ETHER_ADDR_STR_LEN]="";
++	uint16 seqnum, type, code;
++
++	if (!(dump_msg_level & DUMP_ICMP_VAL))
++		return;
++
++	/* check IP header */
++	if (iph->ihl != 5 || iph->version != 4 || iph->protocol != IP_PROT_ICMP) {
++		return;
++	}
++
++	icmph = (struct icmphdr *)((uint8 *)pkt + sizeof(struct iphdr));
++	seqnum = 0;
++	type = icmph->type;
++	code = icmph->code;
++	ip_saddr = iph->saddr;
++	ip_daddr = iph->daddr;
++	bcm_ip_ntoa((struct ipv4_addr *)&ip_saddr, sabuf);
++	bcm_ip_ntoa((struct ipv4_addr *)&ip_daddr, dabuf);
++	bcm_ether_ntoa((struct ether_addr *)pktdata, deabuf);
++	bcm_ether_ntoa((struct ether_addr *)(pktdata+6), seabuf);
++	if (type == ICMP_TYPE_ECHO_REQUEST) {
++		seqnum = ntoh16(ICMP_ECHO_SEQ(icmph));
++		ICMP_PING_PRINT("PING REQUEST");
++	} else if (type == ICMP_TYPE_ECHO_REPLY) {
++		seqnum = ntoh16(ICMP_ECHO_SEQ(icmph));
++		ICMP_PING_PRINT("PING REPLY  ");
++	} else if (type == ICMP_TYPE_DEST_UNREACH) {
++		ICMP_PRINT("ICMP DEST UNREACH");
++	} else {
++		ICMP_PRINT("ICMP OTHER");
++	}
++}
++#endif /* DHD_ICMP_DUMP */
++
++#ifdef SHOW_LOGTRACE
++void
++dhd_get_read_buf_ptr(dhd_pub_t *dhd_pub, trace_buf_info_t *trace_buf_info)
++{
++	dhd_dbg_ring_status_t ring_status;
++	uint32 rlen;
++
++	rlen = dhd_dbg_ring_pull_single(dhd_pub, FW_VERBOSE_RING_ID, trace_buf_info->buf,
++		TRACE_LOG_BUF_MAX_SIZE, TRUE);
++	trace_buf_info->size = rlen;
++	trace_buf_info->availability = NEXT_BUF_NOT_AVAIL;
++	if (rlen == 0) {
++		trace_buf_info->availability = BUF_NOT_AVAILABLE;
++		return;
++	}
++	dhd_dbg_get_ring_status(dhd_pub, FW_VERBOSE_RING_ID, &ring_status);
++	if (ring_status.written_bytes != ring_status.read_bytes) {
++		trace_buf_info->availability = NEXT_BUF_AVAIL;
++	}
++}
++#endif /* SHOW_LOGTRACE */
++
++bool
++dhd_fw_download_status(dhd_pub_t * dhd_pub)
++{
++	return dhd_pub->fw_download_done;
++}
++
++int
++dhd_create_to_notifier_skt(void)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
++	/* Kernel 3.7 onwards this API accepts only 3 arguments. */
++	/* Kernel version 3.6 is a special case which accepts 4 arguments */
++	nl_to_event_sk = netlink_kernel_create(&init_net, BCM_NL_USER, &g_cfg);
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++	/* Kernel version 3.5 and below use this old API format */
++	nl_to_event_sk = netlink_kernel_create(&init_net, BCM_NL_USER, 0,
++			dhd_process_daemon_msg, NULL, THIS_MODULE);
++#else
++	nl_to_event_sk = netlink_kernel_create(&init_net, BCM_NL_USER, THIS_MODULE, &g_cfg);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0)) */
++	if (!nl_to_event_sk)
++	{
++		printf("Error creating socket.\n");
++		return -1;
++	}
++	DHD_INFO(("nl_to socket created successfully...\n"));
++	return 0;
++}
++
++void
++dhd_destroy_to_notifier_skt(void)
++{
++	DHD_INFO(("Destroying nl_to socket\n"));
++	if (nl_to_event_sk) {
++		netlink_kernel_release(nl_to_event_sk);
++	}
++}
++
++static void
++dhd_recv_msg_from_daemon(struct sk_buff *skb)
++{
++	struct nlmsghdr *nlh;
++	bcm_to_info_t *cmd;
++
++	nlh = (struct nlmsghdr *)skb->data;
++	cmd = (bcm_to_info_t *)nlmsg_data(nlh);
++	if ((cmd->magic == BCM_TO_MAGIC) && (cmd->reason == REASON_DAEMON_STARTED)) {
++		sender_pid = ((struct nlmsghdr *)(skb->data))->nlmsg_pid;
++		DHD_INFO(("DHD Daemon Started\n"));
++	}
++}
++
++int
++dhd_send_msg_to_daemon(struct sk_buff *skb, void *data, int size)
++{
++	struct nlmsghdr *nlh;
++	struct sk_buff *skb_out;
++
++	if (!nl_to_event_sk) {
++		DHD_INFO(("No socket available\n"));
++		return -1;
++	}
++
++	BCM_REFERENCE(skb);
++	if (sender_pid == 0) {
++		DHD_INFO(("Invalid PID 0\n"));
++		return -1;
++	}
++
++	if ((skb_out = nlmsg_new(size, 0)) == NULL) {
++		DHD_ERROR(("%s: skb alloc failed\n", __FUNCTION__));
++		return -1;
++	}
++	nlh = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, size, 0);
++	NETLINK_CB(skb_out).dst_group = 0; /* Unicast */
++	memcpy(nlmsg_data(nlh), (char *)data, size);
++
++	if ((nlmsg_unicast(nl_to_event_sk, skb_out, sender_pid)) < 0) {
++		DHD_INFO(("Error sending message\n"));
++	}
++	return 0;
++}
++
++
++static void
++dhd_process_daemon_msg(struct sk_buff *skb)
++{
++	bcm_to_info_t to_info;
++
++	to_info.magic = BCM_TO_MAGIC;
++	to_info.reason = REASON_DAEMON_STARTED;
++	to_info.trap = NO_TRAP;
++
++	dhd_recv_msg_from_daemon(skb);
++	dhd_send_msg_to_daemon(skb, &to_info, sizeof(to_info));
++}
++
++#ifdef REPORT_FATAL_TIMEOUTS
++static void
++dhd_send_trap_to_fw(dhd_pub_t * pub, int reason, int trap)
++{
++	bcm_to_info_t to_info;
++
++	to_info.magic = BCM_TO_MAGIC;
++	to_info.reason = reason;
++	to_info.trap = trap;
++
++	DHD_ERROR(("Sending Event reason:%d trap:%d\n", reason, trap));
++	dhd_send_msg_to_daemon(NULL, (void *)&to_info, sizeof(bcm_to_info_t));
++}
++
++void
++dhd_send_trap_to_fw_for_timeout(dhd_pub_t * pub, timeout_reasons_t reason)
++{
++	int to_reason;
++	int trap = NO_TRAP;
++	switch (reason) {
++	        case DHD_REASON_COMMAND_TO:
++	                to_reason = REASON_COMMAND_TO;
++	                trap = DO_TRAP;
++	                break;
++	        case DHD_REASON_JOIN_TO:
++	                to_reason = REASON_JOIN_TO;
++	                break;
++	        case DHD_REASON_SCAN_TO:
++	                to_reason = REASON_SCAN_TO;
++	                break;
++	        case DHD_REASON_OQS_TO:
++	                to_reason = REASON_OQS_TO;
++	                trap = DO_TRAP;
++	                break;
++	        default:
++	                to_reason = REASON_UNKOWN;
++	}
++	dhd_send_trap_to_fw(pub, to_reason, trap);
++}
++#endif /* REPORT_FATAL_TIMEOUTS */
++
++#ifdef DHD_LOG_DUMP
++void
++dhd_log_dump_init(dhd_pub_t *dhd)
++{
++	struct dhd_log_dump_buf *dld_buf;
++	int i = 0;
++#if defined(CONFIG_DHD_USE_STATIC_BUF) && defined(DHD_USE_STATIC_MEMDUMP)
++	int prealloc_idx = DHD_PREALLOC_DHD_LOG_DUMP_BUF;
++#endif /* CONFIG_DHD_USE_STATIC_BUF && DHD_USE_STATIC_MEMDUMP */
++
++	for (i = 0; i < DLD_BUFFER_NUM; i++) {
++		dld_buf = &g_dld_buf[i];
++		spin_lock_init(&dld_buf->lock);
++#if defined(CONFIG_DHD_USE_STATIC_BUF) && defined(DHD_USE_STATIC_MEMDUMP)
++		dld_buf->buffer = DHD_OS_PREALLOC(dhd, prealloc_idx++, dld_buf_size[i]);
++#else
++		dld_buf->buffer = kmalloc(dld_buf_size[i], GFP_KERNEL);
++#endif /* CONFIG_DHD_USE_STATIC_BUF && DHD_USE_STATIC_MEMDUMP */
++
++		if (!dld_buf->buffer) {
++			dld_buf->buffer = kmalloc(dld_buf_size[i], GFP_KERNEL);
++			DHD_ERROR(("Try to allocate memory using kmalloc().\n"));
++
++			if (!dld_buf->buffer) {
++				DHD_ERROR(("Failed to allocate memory for dld_buf[%d].\n", i));
++				goto fail;
++			}
++		}
++
++		dld_buf->wraparound = 0;
++		dld_buf->max = (unsigned long)dld_buf->buffer + dld_buf_size[i];
++		dld_buf->present = dld_buf->front = dld_buf->buffer;
++		dld_buf->remain = dld_buf_size[i];
++		dld_buf->enable = 1;
++	}
++	return;
++
++fail:
++	for (i = 0; i < DLD_BUFFER_NUM; i++) {
++		if (dld_buf[i].buffer) {
++			kfree(dld_buf[i].buffer);
++		}
++	}
++}
++
++void
++dhd_log_dump_deinit(dhd_pub_t *dhd)
++{
++	struct dhd_log_dump_buf *dld_buf;
++	int i = 0;
++
++	for (i = 0; i < DLD_BUFFER_NUM; i++) {
++		dld_buf = &g_dld_buf[i];
++		dld_buf->enable = 0;
++#if defined(CONFIG_DHD_USE_STATIC_BUF) && defined(DHD_USE_STATIC_MEMDUMP)
++		DHD_OS_PREFREE(dhd, dld_buf->buffer, dld_buf_size[i]);
++#else
++		kfree(dld_buf->buffer);
++#endif /* CONFIG_DHD_USE_STATIC_BUF && DHD_USE_STATIC_MEMDUMP */
++	}
++}
++
++void
++dhd_log_dump_write(int type, const char *fmt, ...)
++{
++	int len = 0;
++	char tmp_buf[DHD_LOG_DUMP_MAX_TEMP_BUFFER_SIZE] = {0, };
++	va_list args;
++	unsigned long flags = 0;
++	struct dhd_log_dump_buf *dld_buf = NULL;
++
++	switch (type)
++	{
++		case DLD_BUF_TYPE_GENERAL:
++			dld_buf = &g_dld_buf[type];
++			break;
++		case DLD_BUF_TYPE_SPECIAL:
++			dld_buf = &g_dld_buf[type];
++			break;
++		default:
++			DHD_ERROR(("%s: Unknown DHD_LOG_DUMP_BUF_TYPE(%d).\n",
++				__FUNCTION__, type));
++			return;
++	}
++
++	if (dld_buf->enable != 1) {
++		return;
++	}
++
++	va_start(args, fmt);
++
++	len = vsnprintf(tmp_buf, DHD_LOG_DUMP_MAX_TEMP_BUFFER_SIZE, fmt, args);
++	/* Non ANSI C99 compliant returns -1,
++	 * ANSI compliant return len >= DHD_LOG_DUMP_MAX_TEMP_BUFFER_SIZE
++	 */
++	if (len < 0) {
++		return;
++	}
++
++	if (len >= DHD_LOG_DUMP_MAX_TEMP_BUFFER_SIZE) {
++		len = DHD_LOG_DUMP_MAX_TEMP_BUFFER_SIZE - 1;
++		tmp_buf[len] = '\0';
++	}
++
++	/* make a critical section to eliminate race conditions */
++	spin_lock_irqsave(&dld_buf->lock, flags);
++	if (dld_buf->remain < len) {
++		dld_buf->wraparound = 1;
++		dld_buf->present = dld_buf->front;
++		dld_buf->remain = dld_buf_size[type];
++	}
++
++	strncpy(dld_buf->present, tmp_buf, len);
++	dld_buf->remain -= len;
++	dld_buf->present += len;
++	spin_unlock_irqrestore(&dld_buf->lock, flags);
++
++	/* double check invalid memory operation */
++	ASSERT((unsigned long)dld_buf->present <= dld_buf->max);
++	va_end(args);
++}
++
++char*
++dhd_log_dump_get_timestamp(void)
++{
++	static char buf[16];
++	u64 ts_nsec;
++	unsigned long rem_nsec;
++
++	ts_nsec = local_clock();
++	rem_nsec = do_div(ts_nsec, 1000000000);
++	snprintf(buf, sizeof(buf), "%5lu.%06lu",
++		(unsigned long)ts_nsec, rem_nsec / 1000);
++
++	return buf;
++}
++#endif /* DHD_LOG_DUMP */
++
++int
++dhd_write_file(const char *filepath, char *buf, int buf_len)
++{
++	struct file *fp = NULL;
++	mm_segment_t old_fs;
++	int ret = 0;
++
++	/* change to KERNEL_DS address limit */
++	old_fs = get_fs();
++	set_fs(KERNEL_DS);
++
++	/* File is always created. */
++	fp = filp_open(filepath, O_RDWR | O_CREAT, 0664);
++	if (IS_ERR(fp)) {
++		DHD_ERROR(("%s: Couldn't open file '%s' err %ld\n",
++			__FUNCTION__, filepath, PTR_ERR(fp)));
++		ret = BCME_ERROR;
++	} else {
++		if (fp->f_mode & FMODE_WRITE) {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++			ret = kernel_write(fp, buf, buf_len, &fp->f_pos);
++#else
++			ret = vfs_write(fp, buf, buf_len, &fp->f_pos);
++#endif
++			if (ret < 0) {
++				DHD_ERROR(("%s: Couldn't write file '%s'\n",
++					__FUNCTION__, filepath));
++				ret = BCME_ERROR;
++			} else {
++				ret = BCME_OK;
++			}
++		}
++		filp_close(fp, NULL);
++	}
++
++	/* restore previous address limit */
++	set_fs(old_fs);
++
++	return ret;
++}
++
++int
++dhd_read_file(const char *filepath, char *buf, int buf_len)
++{
++	struct file *fp = NULL;
++	mm_segment_t old_fs;
++	int ret;
++
++	/* change to KERNEL_DS address limit */
++	old_fs = get_fs();
++	set_fs(KERNEL_DS);
++
++	fp = filp_open(filepath, O_RDONLY, 0);
++	if (IS_ERR(fp)) {
++		set_fs(old_fs);
++		DHD_ERROR(("%s: File %s doesn't exist\n", __FUNCTION__, filepath));
++		return BCME_ERROR;
++	}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++	ret = kernel_read(fp, buf, buf_len, NULL);
++#else
++	ret = kernel_read(fp, 0, buf, buf_len);
++#endif
++	filp_close(fp, NULL);
++
++	/* restore previous address limit */
++	set_fs(old_fs);
++
++	/* Return the number of bytes read */
++	if (ret > 0) {
++		/* Success to read */
++		ret = 0;
++	} else {
++		DHD_ERROR(("%s: Couldn't read the file %s, ret=%d\n",
++			__FUNCTION__, filepath, ret));
++		ret = BCME_ERROR;
++	}
++
++	return ret;
++}
++
++int
++dhd_write_file_and_check(const char *filepath, char *buf, int buf_len)
++{
++	int ret;
++
++	ret = dhd_write_file(filepath, buf, buf_len);
++	if (ret < 0) {
++		return ret;
++	}
++
++	/* Read the file again and check if the file size is not zero */
++	memset(buf, 0, buf_len);
++	ret = dhd_read_file(filepath, buf, buf_len);
++
++	return ret;
++}
++
++#ifdef DHD_LB_TXP
++#define DHD_LB_TXBOUND	64
++/*
++ * Function that performs the TX processing on a given CPU
++ */
++bool
++dhd_lb_tx_process(dhd_info_t *dhd)
++{
++	struct sk_buff *skb;
++	int cnt = 0;
++	struct net_device *net;
++	int ifidx;
++	bool resched = FALSE;
++
++	DHD_TRACE(("%s(): TX Processing \r\n", __FUNCTION__));
++	if (dhd == NULL) {
++		DHD_ERROR((" Null pointer DHD \r\n"));
++		return resched;
++	}
++
++	DHD_LB_STATS_PERCPU_ARR_INCR(dhd->txp_percpu_run_cnt);
++
++	/* Base Loop to perform the actual Tx */
++	do {
++		skb = skb_dequeue(&dhd->tx_pend_queue);
++		if (skb == NULL) {
++			DHD_TRACE(("Dequeued a Null Packet \r\n"));
++			break;
++		}
++		cnt++;
++
++		net =  DHD_LB_TX_PKTTAG_NETDEV((dhd_tx_lb_pkttag_fr_t *)PKTTAG(skb));
++		ifidx = DHD_LB_TX_PKTTAG_IFIDX((dhd_tx_lb_pkttag_fr_t *)PKTTAG(skb));
++
++		BCM_REFERENCE(net);
++		DHD_TRACE(("Processing skb %p for net %p index %d \r\n", skb,
++			net, ifidx));
++
++		__dhd_sendpkt(&dhd->pub, ifidx, skb);
++
++		if (cnt >= DHD_LB_TXBOUND) {
++			resched = TRUE;
++			break;
++		}
++
++	} while (1);
++
++	DHD_INFO(("%s(): Processed %d packets \r\n", __FUNCTION__, cnt));
++
++	return resched;
++}
++
++void
++dhd_lb_tx_handler(unsigned long data)
++{
++	dhd_info_t *dhd = (dhd_info_t *)data;
++
++	if (dhd_lb_tx_process(dhd)) {
++		dhd_tasklet_schedule(&dhd->tx_tasklet);
++	}
++}
++
++#endif /* DHD_LB_TXP */
++
++/* ----------------------------------------------------------------------------
++ * Infrastructure code for sysfs interface support for DHD
++ *
++ * What is sysfs interface?
++ * https://www.kernel.org/doc/Documentation/filesystems/sysfs.txt
++ *
++ * Why sysfs interface?
++ * This is the Linux standard way of changing/configuring Run Time parameters
++ * for a driver. We can use this interface to control "linux" specific driver
++ * parameters.
++ *
++ * -----------------------------------------------------------------------------
++ */
++
++#include <linux/sysfs.h>
++#include <linux/kobject.h>
++
++#if defined(DHD_TRACE_WAKE_LOCK)
++
++/* Function to show the history buffer */
++static ssize_t
++show_wklock_trace(struct dhd_info *dev, char *buf)
++{
++	ssize_t ret = 0;
++	dhd_info_t *dhd = (dhd_info_t *)dev;
++
++	buf[ret] = '\n';
++	buf[ret+1] = 0;
++
++	dhd_wk_lock_stats_dump(&dhd->pub);
++	return ret+1;
++}
++
++/* Function to enable/disable wakelock trace */
++static ssize_t
++wklock_trace_onoff(struct dhd_info *dev, const char *buf, size_t count)
++{
++	unsigned long onoff;
++	unsigned long flags;
++	dhd_info_t *dhd = (dhd_info_t *)dev;
++
++	onoff = bcm_strtoul(buf, NULL, 10);
++	if (onoff != 0 && onoff != 1) {
++		return -EINVAL;
++	}
++
++	spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++	trace_wklock_onoff = onoff;
++	spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	if (trace_wklock_onoff) {
++		printk("ENABLE WAKLOCK TRACE\n");
++	} else {
++		printk("DISABLE WAKELOCK TRACE\n");
++	}
++
++	return (ssize_t)(onoff+1);
++}
++#endif /* DHD_TRACE_WAKE_LOCK */
++
++#if defined(DHD_LB_TXP)
++static ssize_t
++show_lbtxp(struct dhd_info *dev, char *buf)
++{
++	ssize_t ret = 0;
++	unsigned long onoff;
++	dhd_info_t *dhd = (dhd_info_t *)dev;
++
++	onoff = atomic_read(&dhd->lb_txp_active);
++	ret = scnprintf(buf, PAGE_SIZE - 1, "%lu \n",
++		onoff);
++	return ret;
++}
++
++static ssize_t
++lbtxp_onoff(struct dhd_info *dev, const char *buf, size_t count)
++{
++	unsigned long onoff;
++	dhd_info_t *dhd = (dhd_info_t *)dev;
++	int i;
++
++	onoff = bcm_strtoul(buf, NULL, 10);
++
++	sscanf(buf, "%lu", &onoff);
++	if (onoff != 0 && onoff != 1) {
++		return -EINVAL;
++	}
++	atomic_set(&dhd->lb_txp_active, onoff);
++
++	/* Since the scheme is changed clear the counters */
++	for (i = 0; i < NR_CPUS; i++) {
++		DHD_LB_STATS_CLR(dhd->txp_percpu_run_cnt[i]);
++		DHD_LB_STATS_CLR(dhd->tx_start_percpu_run_cnt[i]);
++	}
++
++	return count;
++}
++
++#endif /* DHD_LB_TXP */
++/*
++ * Generic Attribute Structure for DHD.
++ * If we have to add a new sysfs entry under /sys/bcm-dhd/, we have
++ * to instantiate an object of type dhd_attr,  populate it with
++ * the required show/store functions (ex:- dhd_attr_cpumask_primary)
++ * and add the object to default_attrs[] array, that gets registered
++ * to the kobject of dhd (named bcm-dhd).
++ */
++
++struct dhd_attr {
++	struct attribute attr;
++	ssize_t(*show)(struct dhd_info *, char *);
++	ssize_t(*store)(struct dhd_info *, const char *, size_t count);
++};
++
++#if defined(DHD_TRACE_WAKE_LOCK)
++static struct dhd_attr dhd_attr_wklock =
++	__ATTR(wklock_trace, 0660, show_wklock_trace, wklock_trace_onoff);
++#endif /* defined(DHD_TRACE_WAKE_LOCK */
++
++#if defined(DHD_LB_TXP)
++static struct dhd_attr dhd_attr_lbtxp =
++	__ATTR(lbtxp, 0660, show_lbtxp, lbtxp_onoff);
++#endif /* DHD_LB_TXP */
++
++/* Attribute object that gets registered with "bcm-dhd" kobject tree */
++static struct attribute *default_attrs[] = {
++#if defined(DHD_TRACE_WAKE_LOCK)
++	&dhd_attr_wklock.attr,
++#endif /* DHD_TRACE_WAKE_LOCK */
++#if defined(DHD_LB_TXP)
++	&dhd_attr_lbtxp.attr,
++#endif /* DHD_LB_TXP */
++	NULL
++};
++
++#define to_dhd(k) container_of(k, struct dhd_info, dhd_kobj)
++#define to_attr(a) container_of(a, struct dhd_attr, attr)
++
++/*
++ * bcm-dhd kobject show function, the "attr" attribute specifices to which
++ * node under "bcm-dhd" the show function is called.
++ */
++static ssize_t dhd_show(struct kobject *kobj, struct attribute *attr, char *buf)
++{
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	dhd_info_t *dhd = to_dhd(kobj);
++	struct dhd_attr *d_attr = to_attr(attr);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	int ret;
++
++	if (d_attr->show)
++		ret = d_attr->show(dhd, buf);
++	else
++		ret = -EIO;
++
++	return ret;
++}
++
++/*
++ * bcm-dhd kobject show function, the "attr" attribute specifices to which
++ * node under "bcm-dhd" the store function is called.
++ */
++static ssize_t dhd_store(struct kobject *kobj, struct attribute *attr,
++	const char *buf, size_t count)
++{
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	dhd_info_t *dhd = to_dhd(kobj);
++	struct dhd_attr *d_attr = to_attr(attr);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	int ret;
++
++	if (d_attr->store)
++		ret = d_attr->store(dhd, buf, count);
++	else
++		ret = -EIO;
++
++	return ret;
++
++}
++
++static struct sysfs_ops dhd_sysfs_ops = {
++	.show = dhd_show,
++	.store = dhd_store,
++};
++
++static struct kobj_type dhd_ktype = {
++	.sysfs_ops = &dhd_sysfs_ops,
++	.default_attrs = default_attrs,
++};
++
++/* Create a kobject and attach to sysfs interface */
++static int dhd_sysfs_init(dhd_info_t *dhd)
++{
++	int ret = -1;
++
++	if (dhd == NULL) {
++		DHD_ERROR(("%s(): dhd is NULL \r\n", __FUNCTION__));
++		return ret;
++	}
++
++	/* Initialize the kobject */
++	ret = kobject_init_and_add(&dhd->dhd_kobj, &dhd_ktype, NULL, "bcm-dhd");
++	if (ret) {
++		kobject_put(&dhd->dhd_kobj);
++		DHD_ERROR(("%s(): Unable to allocate kobject \r\n", __FUNCTION__));
++		return ret;
++	}
++
++	/*
++	 * We are always responsible for sending the uevent that the kobject
++	 * was added to the system.
++	 */
++	kobject_uevent(&dhd->dhd_kobj, KOBJ_ADD);
++
++	return ret;
++}
++
++/* Done with the kobject and detach the sysfs interface */
++static void dhd_sysfs_exit(dhd_info_t *dhd)
++{
++	if (dhd == NULL) {
++		DHD_ERROR(("%s(): dhd is NULL \r\n", __FUNCTION__));
++		return;
++	}
++
++	/* Releae the kobject */
++	if (dhd->dhd_kobj.state_initialized)
++		kobject_put(&dhd->dhd_kobj);
++}
++
++#ifdef DHD_DEBUG_UART
++bool
++dhd_debug_uart_is_running(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	if (dhd->duart_execute) {
++		return TRUE;
++	}
++
++	return FALSE;
++}
++
++static void
++dhd_debug_uart_exec_rd(void *handle, void *event_info, u8 event)
++{
++	dhd_pub_t *dhdp = handle;
++	dhd_debug_uart_exec(dhdp, "rd");
++}
++
++static void
++dhd_debug_uart_exec(dhd_pub_t *dhdp, char *cmd)
++{
++	int ret;
++
++	char *argv[] = {DHD_DEBUG_UART_EXEC_PATH, cmd, NULL};
++	char *envp[] = {"HOME=/", "TERM=linux", "PATH=/sbin:/system/bin", NULL};
++
++#ifdef DHD_FW_COREDUMP
++	if (dhdp->memdump_enabled == DUMP_MEMFILE_BUGON)
++#endif
++	{
++		if (dhdp->hang_reason == HANG_REASON_PCIE_LINK_DOWN ||
++#ifdef DHD_FW_COREDUMP
++			dhdp->memdump_success == FALSE ||
++#endif
++			FALSE) {
++			dhdp->info->duart_execute = TRUE;
++			DHD_ERROR(("DHD: %s - execute %s %s\n",
++				__FUNCTION__, DHD_DEBUG_UART_EXEC_PATH, cmd));
++			ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_PROC);
++			DHD_ERROR(("DHD: %s - %s %s ret = %d\n",
++				__FUNCTION__, DHD_DEBUG_UART_EXEC_PATH, cmd, ret));
++			dhdp->info->duart_execute = FALSE;
++
++#ifdef DHD_LOG_DUMP
++			if (dhdp->memdump_type != DUMP_TYPE_BY_SYSDUMP)
++#endif
++			{
++				BUG_ON(1);
++			}
++		}
++	}
++}
++#endif	/* DHD_DEBUG_UART */
++
++#if defined(DHD_BLOB_EXISTENCE_CHECK)
++void
++dhd_set_blob_support(dhd_pub_t *dhdp, char *fw_path)
++{
++	struct file *fp;
++	char *filepath = CONFIG_BCMDHD_CLM_PATH;
++
++	fp = filp_open(filepath, O_RDONLY, 0);
++	if (IS_ERR(fp)) {
++		DHD_ERROR(("%s: ----- blob file dosen't exist -----\n", __FUNCTION__));
++		dhdp->is_blob = FALSE;
++	} else {
++		DHD_ERROR(("%s: ----- blob file exist -----\n", __FUNCTION__));
++		dhdp->is_blob = TRUE;
++#if defined(CONCATE_BLOB)
++		strncat(fw_path, "_blob", strlen("_blob"));
++#else
++		BCM_REFERENCE(fw_path);
++#endif /* SKIP_CONCATE_BLOB */
++		filp_close(fp, NULL);
++	}
++}
++#endif /* DHD_BLOB_EXISTENCE_CHECK */
++
++#if defined(PCIE_FULL_DONGLE)
++/** test / loopback */
++void
++dmaxfer_free_dmaaddr_handler(void *handle, void *event_info, u8 event)
++{
++	dmaxref_mem_map_t *dmmap = (dmaxref_mem_map_t *)event_info;
++	dhd_info_t *dhd_info = (dhd_info_t *)handle;
++	dhd_pub_t *dhdp = &dhd_info->pub;
++
++	if (event != DHD_WQ_WORK_DMA_LB_MEM_REL) {
++		DHD_ERROR(("%s: unexpected event \n", __FUNCTION__));
++		return;
++	}
++
++	if ((dhd_info == NULL) || (dhdp == NULL)) {
++		DHD_ERROR(("%s: invalid dhd_info\n", __FUNCTION__));
++		return;
++	}
++
++	if (dmmap == NULL) {
++		DHD_ERROR(("%s: dmmap is null\n", __FUNCTION__));
++		return;
++	}
++	dmaxfer_free_prev_dmaaddr(dhdp, dmmap);
++}
++
++
++void
++dhd_schedule_dmaxfer_free(dhd_pub_t *dhdp, dmaxref_mem_map_t *dmmap)
++{
++	dhd_info_t *dhd_info = dhdp->info;
++
++	dhd_deferred_schedule_work(dhd_info->dhd_deferred_wq, (void *)dmmap,
++		DHD_WQ_WORK_DMA_LB_MEM_REL, dmaxfer_free_dmaaddr_handler, DHD_WQ_WORK_PRIORITY_LOW);
++}
++#endif /* PCIE_FULL_DONGLE */
++/* ---------------------------- End of sysfs implementation ------------------------------------- */
++#ifdef HOFFLOAD_MODULES
++void
++dhd_linux_get_modfw_address(dhd_pub_t *dhd)
++{
++	const char* module_name = NULL;
++	const struct firmware *module_fw;
++	struct module_metadata *hmem = &dhd->hmem;
++
++	if (dhd_hmem_module_string[0] != '\0') {
++		module_name = dhd_hmem_module_string;
++	} else {
++		DHD_ERROR(("%s No module image name specified\n", __FUNCTION__));
++		return;
++	}
++	if (request_firmware(&module_fw, module_name, dhd_bus_to_dev(dhd->bus))) {
++		DHD_ERROR(("modules.img not available\n"));
++		return;
++	}
++	if (!dhd_alloc_module_memory(dhd->bus, module_fw->size, hmem)) {
++		release_firmware(module_fw);
++		return;
++	}
++	memcpy(hmem->data, module_fw->data, module_fw->size);
++	release_firmware(module_fw);
++}
++#endif /* HOFFLOAD_MODULES */
++
++#ifdef SET_PCIE_IRQ_CPU_CORE
++void
++dhd_set_irq_cpucore(dhd_pub_t *dhdp, int set)
++{
++	unsigned int irq;
++	if (!dhdp) {
++		DHD_ERROR(("%s : dhd is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (!dhdp->bus) {
++		DHD_ERROR(("%s : dhd->bus is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (dhdpcie_get_pcieirq(dhdp->bus, &irq)) {
++		return;
++	}
++
++	set_irq_cpucore(irq, set);
++}
++#endif /* SET_PCIE_IRQ_CPU_CORE */
++
++#if defined(DHD_HANG_SEND_UP_TEST)
++void
++dhd_make_hang_with_reason(struct net_device *dev, const char *string_num)
++{
++	dhd_info_t *dhd = NULL;
++	dhd_pub_t *dhdp = NULL;
++	uint reason = HANG_REASON_MAX;
++	char buf[WLC_IOCTL_SMLEN] = {0, };
++	uint32 fw_test_code = 0;
++	dhd = DHD_DEV_INFO(dev);
++
++	if (dhd) {
++		dhdp = &dhd->pub;
++	}
++
++	if (!dhd || !dhdp) {
++		return;
++	}
++
++	reason = (uint) bcm_strtoul(string_num, NULL, 0);
++	DHD_ERROR(("Enter %s, reason=0x%x\n", __FUNCTION__,  reason));
++
++	if (reason == 0) {
++		if (dhdp->req_hang_type) {
++			DHD_ERROR(("%s, Clear HANG test request 0x%x\n",
++				__FUNCTION__, dhdp->req_hang_type));
++			dhdp->req_hang_type = 0;
++			return;
++		} else {
++			DHD_ERROR(("%s, No requested HANG test\n", __FUNCTION__));
++			return;
++		}
++	} else if ((reason <= HANG_REASON_MASK) || (reason >= HANG_REASON_MAX)) {
++		DHD_ERROR(("Invalid HANG request, reason 0x%x\n", reason));
++		return;
++	}
++
++	if (dhdp->req_hang_type != 0) {
++		DHD_ERROR(("Already HANG requested for test\n"));
++		return;
++	}
++
++	switch (reason) {
++		case HANG_REASON_IOCTL_RESP_TIMEOUT:
++			DHD_ERROR(("Make HANG!!!: IOCTL response timeout(0x%x)\n", reason));
++			dhdp->req_hang_type = reason;
++			fw_test_code = 102; /* resumed on timeour */
++			bcm_mkiovar("bus:disconnect", (void *)&fw_test_code, 4, buf, sizeof(buf));
++			dhd_wl_ioctl_cmd(dhdp, WLC_SET_VAR, buf, sizeof(buf), TRUE, 0);
++			break;
++		case HANG_REASON_DONGLE_TRAP:
++			DHD_ERROR(("Make HANG!!!: Dongle trap (0x%x)\n", reason));
++			dhdp->req_hang_type = reason;
++			fw_test_code = 99; /* dongle trap */
++			bcm_mkiovar("bus:disconnect", (void *)&fw_test_code, 4, buf, sizeof(buf));
++			dhd_wl_ioctl_cmd(dhdp, WLC_SET_VAR, buf, sizeof(buf), TRUE, 0);
++			break;
++		case HANG_REASON_D3_ACK_TIMEOUT:
++			DHD_ERROR(("Make HANG!!!: D3 ACK timeout (0x%x)\n", reason));
++			dhdp->req_hang_type = reason;
++			break;
++		case HANG_REASON_BUS_DOWN:
++			DHD_ERROR(("Make HANG!!!: BUS down(0x%x)\n", reason));
++			dhdp->req_hang_type = reason;
++			break;
++		case HANG_REASON_PCIE_LINK_DOWN:
++		case HANG_REASON_MSGBUF_LIVELOCK:
++			dhdp->req_hang_type = 0;
++			DHD_ERROR(("Does not support requested HANG(0x%x)\n", reason));
++			break;
++		case HANG_REASON_IFACE_OP_FAILURE:
++			DHD_ERROR(("Make HANG!!!: P2P inrerface delete failure(0x%x)\n", reason));
++			dhdp->req_hang_type = reason;
++			break;
++		case HANG_REASON_HT_AVAIL_ERROR:
++			dhdp->req_hang_type = 0;
++			DHD_ERROR(("PCIe does not support requested HANG(0x%x)\n", reason));
++			break;
++		case HANG_REASON_PCIE_RC_LINK_UP_FAIL:
++			DHD_ERROR(("Make HANG!!!:Link Up(0x%x)\n", reason));
++			dhdp->req_hang_type = reason;
++			break;
++		default:
++			dhdp->req_hang_type = 0;
++			DHD_ERROR(("Unknown HANG request (0x%x)\n", reason));
++			break;
++	}
++}
++#endif /* DHD_HANG_SEND_UP_TEST */
++#ifdef DHD_WAKE_STATUS
++wake_counts_t*
++dhd_get_wakecount(dhd_pub_t *dhdp)
++{
++#ifdef BCMDBUS
++	return NULL;
++#else
++	return dhd_bus_get_wakecount(dhdp);
++#endif /* BCMDBUS */
++}
++#endif /* DHD_WAKE_STATUS */
++
++#ifdef BCM_ASLR_HEAP
++uint32
++dhd_get_random_number(void)
++{
++	uint32 rand = 0;
++	get_random_bytes_arch(&rand, sizeof(rand));
++	return rand;
++}
++#endif /* BCM_ASLR_HEAP */
++
++#ifdef DHD_PKT_LOGGING
++void
++dhd_pktlog_dump(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (dhd_pktlog_write_file(&dhd->pub)) {
++		DHD_ERROR(("%s: writing pktlog dump to the file failed\n", __FUNCTION__));
++		return;
++	}
++}
++
++void
++dhd_schedule_pktlog_dump(dhd_pub_t *dhdp)
++{
++	dhd_deferred_schedule_work(dhdp->info->dhd_deferred_wq,
++			(void*)NULL, DHD_WQ_WORK_PKTLOG_DUMP,
++			dhd_pktlog_dump, DHD_WQ_WORK_PRIORITY_HIGH);
++}
++#endif /* DHD_PKT_LOGGING */
++
++void *dhd_get_pub(struct net_device *dev)
++{
++	dhd_info_t *dhdinfo = *(dhd_info_t **)netdev_priv(dev);
++	if (dhdinfo)
++		return (void *)&dhdinfo->pub;
++	else {
++		printf("%s: null dhdinfo\n", __FUNCTION__);
++		return NULL;
++	}
++}
++
++bool dhd_os_wd_timer_enabled(void *bus)
++{
++	dhd_pub_t *pub = bus;
++	dhd_info_t *dhd = (dhd_info_t *)pub->info;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd NULL\n", __FUNCTION__));
++		return FALSE;
++	}
++	return dhd->wd_timer_valid;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux.h b/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux.h
+new file mode 100644
+index 000000000..f19170628
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux.h
+@@ -0,0 +1,189 @@
++/*
++ * DHD Linux header file (dhd_linux exports for cfg80211 and other components)
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_linux.h 699532 2017-05-15 11:00:39Z $
++ */
++
++/* wifi platform functions for power, interrupt and pre-alloc, either
++ * from Android-like platform device data, or Broadcom wifi platform
++ * device data.
++ *
++ */
++#ifndef __DHD_LINUX_H__
++#define __DHD_LINUX_H__
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/fs.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#ifdef DHD_WMF
++#include <dhd_wmf_linux.h>
++#endif
++/* Linux wireless extension support */
++#if defined(WL_WIRELESS_EXT)
++#include <wl_iw.h>
++#endif /* defined(WL_WIRELESS_EXT) */
++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND)
++#include <linux/earlysuspend.h>
++#endif /* defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND) */
++
++/* dongle status */
++enum wifi_adapter_status {
++	WIFI_STATUS_POWER_ON = 0,
++	WIFI_STATUS_ATTACH,
++	WIFI_STATUS_FW_READY,
++	WIFI_STATUS_DETTACH
++};
++#define wifi_chk_adapter_status(adapter, stat) (test_bit(stat, &(adapter)->status))
++#define wifi_get_adapter_status(adapter, stat) (test_bit(stat, &(adapter)->status))
++#define wifi_set_adapter_status(adapter, stat) (set_bit(stat, &(adapter)->status))
++#define wifi_clr_adapter_status(adapter, stat) (clear_bit(stat, &(adapter)->status))
++#define wifi_chg_adapter_status(adapter, stat) (change_bit(stat, &(adapter)->status))
++
++#define DHD_REGISTRATION_TIMEOUT  12000  /* msec : allowed time to finished dhd registration */
++#define DHD_FW_READY_TIMEOUT  5000  /* msec : allowed time to finished fw download */
++
++typedef struct wifi_adapter_info {
++	const char	*name;
++	uint		irq_num;
++	uint		intr_flags;
++	const char	*fw_path;
++	const char	*nv_path;
++	const char	*clm_path;
++	const char	*conf_path;
++	void		*wifi_plat_data;	/* wifi ctrl func, for backward compatibility */
++	uint		bus_type;
++	uint		bus_num;
++	uint		slot_num;
++	wait_queue_head_t status_event;
++	unsigned long status;
++#if defined(BT_OVER_SDIO)
++	const char	*btfw_path;
++#endif /* defined (BT_OVER_SDIO) */
++#ifdef BUS_POWER_RESTORE
++#if defined(BCMSDIO)
++	struct sdio_func *sdio_func;
++#endif /* BCMSDIO */
++#if defined(BCMPCIE)
++	struct pci_dev *pci_dev;
++	struct pci_saved_state *pci_saved_state;
++#endif /* BCMPCIE */
++#endif
++} wifi_adapter_info_t;
++
++#define WLAN_PLAT_NODFS_FLAG	0x01
++#define WLAN_PLAT_AP_FLAG	0x02
++#if !defined(CONFIG_WIFI_CONTROL_FUNC)
++struct wifi_platform_data {
++#ifdef BUS_POWER_RESTORE
++	int (*set_power)(int val, wifi_adapter_info_t *adapter);
++#else
++	int (*set_power)(int val);
++#endif
++	int (*set_reset)(int val);
++	int (*set_carddetect)(int val);
++	void *(*mem_prealloc)(int section, unsigned long size);
++	int (*get_mac_addr)(unsigned char *buf);
++#ifdef CUSTOM_FORCE_NODFS_FLAG
++	void *(*get_country_code)(char *ccode, u32 flags);
++#else /* defined (CUSTOM_FORCE_NODFS_FLAG) */
++	void *(*get_country_code)(char *ccode);
++#endif
++};
++#endif
++
++typedef struct bcmdhd_wifi_platdata {
++	uint				num_adapters;
++	wifi_adapter_info_t	*adapters;
++} bcmdhd_wifi_platdata_t;
++
++/** Per STA params. A list of dhd_sta objects are managed in dhd_if */
++typedef struct dhd_sta {
++	cumm_ctr_t cumm_ctr;    /* cummulative queue length of child flowrings */
++	uint16 flowid[NUMPRIO]; /* allocated flow ring ids (by priority) */
++	void * ifp;             /* associated dhd_if */
++	struct ether_addr ea;   /* stations ethernet mac address */
++	struct list_head list;  /* link into dhd_if::sta_list */
++	int idx;                /* index of self in dhd_pub::sta_pool[] */
++	int ifidx;              /* index of interface in dhd */
++#ifdef DHD_WMF
++	struct dhd_sta *psta_prim; /* primary index of psta interface */
++#endif /* DHD_WMF */
++} dhd_sta_t;
++typedef dhd_sta_t dhd_sta_pool_t;
++
++int dhd_wifi_platform_register_drv(void);
++void dhd_wifi_platform_unregister_drv(void);
++wifi_adapter_info_t* dhd_wifi_platform_attach_adapter(uint32 bus_type,
++	uint32 bus_num, uint32 slot_num, unsigned long status);
++wifi_adapter_info_t* dhd_wifi_platform_get_adapter(uint32 bus_type, uint32 bus_num,
++	uint32 slot_num);
++int wifi_platform_set_power(wifi_adapter_info_t *adapter, bool on, unsigned long msec);
++int wifi_platform_bus_enumerate(wifi_adapter_info_t *adapter, bool device_present);
++int wifi_platform_get_irq_number(wifi_adapter_info_t *adapter, unsigned long *irq_flags_ptr);
++int wifi_platform_get_mac_addr(wifi_adapter_info_t *adapter, unsigned char *buf);
++#ifdef CUSTOM_COUNTRY_CODE
++void *wifi_platform_get_country_code(wifi_adapter_info_t *adapter, char *ccode,
++	u32 flags);
++#else
++void *wifi_platform_get_country_code(wifi_adapter_info_t *adapter, char *ccode);
++#endif /* CUSTOM_COUNTRY_CODE */
++void* wifi_platform_prealloc(wifi_adapter_info_t *adapter, int section, unsigned long size);
++void* wifi_platform_get_prealloc_func_ptr(wifi_adapter_info_t *adapter);
++
++int dhd_get_fw_mode(struct dhd_info *dhdinfo);
++bool dhd_update_fw_nv_path(struct dhd_info *dhdinfo);
++
++#ifdef DHD_WMF
++dhd_wmf_t* dhd_wmf_conf(dhd_pub_t *dhdp, uint32 idx);
++int dhd_get_wmf_psta_disable(dhd_pub_t *dhdp, uint32 idx);
++int dhd_set_wmf_psta_disable(dhd_pub_t *dhdp, uint32 idx, int val);
++void dhd_update_psta_interface_for_sta(dhd_pub_t *dhdp, char* ifname,
++		void* mac_addr, void* event_data);
++#endif /* DHD_WMF */
++#if defined(BT_OVER_SDIO)
++int dhd_net_bus_get(struct net_device *dev);
++int dhd_net_bus_put(struct net_device *dev);
++#endif /* BT_OVER_SDIO */
++#ifdef HOFFLOAD_MODULES
++extern void dhd_free_module_memory(struct dhd_bus *bus, struct module_metadata *hmem);
++extern void* dhd_alloc_module_memory(struct dhd_bus *bus, uint32_t size,
++	struct module_metadata *hmem);
++#endif /* HOFFLOAD_MODULES */
++#if defined(WLADPS) || defined(WLADPS_PRIVATE_CMD)
++#define ADPS_ENABLE	1
++#define ADPS_DISABLE	0
++typedef struct bcm_iov_buf {
++	uint16 version;
++	uint16 len;
++	uint16 id;
++	uint16 data[1];
++} bcm_iov_buf_t;
++
++int dhd_enable_adps(dhd_pub_t *dhd, uint8 on);
++#endif /* WLADPS || WLADPS_PRIVATE_CMD */
++#endif /* __DHD_LINUX_H__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux_platdev.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux_platdev.c
+new file mode 100644
+index 000000000..3848bc552
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux_platdev.c
+@@ -0,0 +1,1013 @@
++/*
++ * Linux platform device for DHD WLAN adapter
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_linux_platdev.c 662397 2016-09-29 10:15:08Z $
++ */
++#include <typedefs.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <bcmutils.h>
++#include <linux_osl.h>
++#include <dhd_dbg.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_bus.h>
++#include <dhd_linux.h>
++#include <wl_android.h>
++#if defined(CONFIG_WIFI_CONTROL_FUNC)
++#include <linux/wlan_plat.h>
++#endif
++#ifdef CONFIG_DTS
++#include<linux/regulator/consumer.h>
++#include<linux/of_gpio.h>
++#endif /* CONFIG_DTS */
++
++#if defined(CUSTOMER_HW)
++extern int dhd_wlan_init_plat_data(void);
++extern void dhd_wlan_deinit_plat_data(wifi_adapter_info_t *adapter);
++#endif /* CUSTOMER_HW */
++
++#define WIFI_PLAT_NAME		"bcmdhd_wlan"
++#define WIFI_PLAT_NAME2		"bcm4329_wlan"
++#define WIFI_PLAT_EXT		"bcmdhd_wifi_platform"
++
++#ifdef CONFIG_DTS
++struct regulator *wifi_regulator = NULL;
++extern struct wifi_platform_data dhd_wlan_control;
++#endif /* CONFIG_DTS */
++
++bool cfg_multichip = FALSE;
++bcmdhd_wifi_platdata_t *dhd_wifi_platdata = NULL;
++static int wifi_plat_dev_probe_ret = 0;
++static bool is_power_on = FALSE;
++#if !defined(CONFIG_DTS)
++#if defined(DHD_OF_SUPPORT)
++static bool dts_enabled = TRUE;
++extern struct resource dhd_wlan_resources;
++extern struct wifi_platform_data dhd_wlan_control;
++#else
++static bool dts_enabled = FALSE;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
++#endif
++struct resource dhd_wlan_resources = {0};
++struct wifi_platform_data dhd_wlan_control = {0};
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++#endif /* CONFIG_OF && !defined(CONFIG_ARCH_MSM) */
++#endif /* !defind(CONFIG_DTS) */
++
++static int dhd_wifi_platform_load(void);
++
++extern void* wl_cfg80211_get_dhdp(struct net_device *dev);
++
++#ifdef ENABLE_4335BT_WAR
++extern int bcm_bt_lock(int cookie);
++extern void bcm_bt_unlock(int cookie);
++static int lock_cookie_wifi = 'W' | 'i'<<8 | 'F'<<16 | 'i'<<24;	/* cookie is "WiFi" */
++#endif /* ENABLE_4335BT_WAR */
++
++wifi_adapter_info_t* dhd_wifi_platform_attach_adapter(uint32 bus_type,
++	uint32 bus_num, uint32 slot_num, unsigned long status)
++{
++	int i;
++
++	if (dhd_wifi_platdata == NULL)
++		return NULL;
++
++	for (i = 0; i < dhd_wifi_platdata->num_adapters; i++) {
++		wifi_adapter_info_t *adapter = &dhd_wifi_platdata->adapters[i];
++		if ((adapter->bus_type == -1 || adapter->bus_type == bus_type) &&
++			(adapter->bus_num == -1 || adapter->bus_num == bus_num) &&
++			(adapter->slot_num == -1 || adapter->slot_num == slot_num)
++#if defined(ENABLE_INSMOD_NO_FW_LOAD)
++			&& (wifi_chk_adapter_status(adapter, status))
++#endif
++		) {
++			DHD_ERROR(("attach adapter info '%s'\n", adapter->name));
++			return adapter;
++		}
++	}
++	return NULL;
++}
++
++wifi_adapter_info_t* dhd_wifi_platform_get_adapter(uint32 bus_type, uint32 bus_num, uint32 slot_num)
++{
++	int i;
++
++	if (dhd_wifi_platdata == NULL)
++		return NULL;
++
++	for (i = 0; i < dhd_wifi_platdata->num_adapters; i++) {
++		wifi_adapter_info_t *adapter = &dhd_wifi_platdata->adapters[i];
++		if ((adapter->bus_type == -1 || adapter->bus_type == bus_type) &&
++			(adapter->bus_num == -1 || adapter->bus_num == bus_num) &&
++			(adapter->slot_num == -1 || adapter->slot_num == slot_num)) {
++			DHD_TRACE(("found adapter info '%s'\n", adapter->name));
++			return adapter;
++		}
++	}
++	return NULL;
++}
++
++void* wifi_platform_prealloc(wifi_adapter_info_t *adapter, int section, unsigned long size)
++{
++	void *alloc_ptr = NULL;
++	struct wifi_platform_data *plat_data;
++
++	if (!adapter || !adapter->wifi_plat_data)
++		return NULL;
++	plat_data = adapter->wifi_plat_data;
++	if (plat_data->mem_prealloc) {
++		alloc_ptr = plat_data->mem_prealloc(section, size);
++		if (alloc_ptr) {
++			DHD_INFO(("success alloc section %d\n", section));
++			if (size != 0L)
++				bzero(alloc_ptr, size);
++			return alloc_ptr;
++		}
++	} else
++		return NULL;
++
++	DHD_ERROR(("%s: failed to alloc static mem section %d\n", __FUNCTION__, section));
++	return NULL;
++}
++
++void* wifi_platform_get_prealloc_func_ptr(wifi_adapter_info_t *adapter)
++{
++	struct wifi_platform_data *plat_data;
++
++	if (!adapter || !adapter->wifi_plat_data)
++		return NULL;
++	plat_data = adapter->wifi_plat_data;
++	return plat_data->mem_prealloc;
++}
++
++int wifi_platform_get_irq_number(wifi_adapter_info_t *adapter, unsigned long *irq_flags_ptr)
++{
++	if (adapter == NULL)
++		return -1;
++	if (irq_flags_ptr)
++		*irq_flags_ptr = adapter->intr_flags;
++	return adapter->irq_num;
++}
++
++int wifi_platform_set_power(wifi_adapter_info_t *adapter, bool on, unsigned long msec)
++{
++	int err = 0;
++#ifndef CONFIG_DTS
++	struct wifi_platform_data *plat_data;
++#endif
++#ifdef BT_OVER_SDIO
++	if (is_power_on == on) {
++		return -EINVAL;
++	}
++#endif /* BT_OVER_SDIO */
++	if (on) {
++		wifi_set_adapter_status(adapter, WIFI_STATUS_POWER_ON);
++	} else {
++		wifi_clr_adapter_status(adapter, WIFI_STATUS_POWER_ON);
++	}
++#ifdef CONFIG_DTS
++	if (on) {
++		printf("======== PULL WL_REG_ON HIGH! ========\n");
++		err = regulator_enable(wifi_regulator);
++		is_power_on = TRUE;
++	}
++	else {
++		printf("======== PULL WL_REG_ON LOW! ========\n");
++		err = regulator_disable(wifi_regulator);
++		is_power_on = FALSE;
++	}
++	if (err < 0) {
++		DHD_ERROR(("%s: regulator enable/disable failed", __FUNCTION__));
++		goto fail;
++	}
++#else
++	if (!adapter || !adapter->wifi_plat_data) {
++		err = -EINVAL;
++		goto fail;
++	}
++	plat_data = adapter->wifi_plat_data;
++
++	DHD_ERROR(("%s = %d\n", __FUNCTION__, on));
++	if (plat_data->set_power) {
++#ifdef ENABLE_4335BT_WAR
++		if (on) {
++			printk("WiFi: trying to acquire BT lock\n");
++			if (bcm_bt_lock(lock_cookie_wifi) != 0)
++				printk("** WiFi: timeout in acquiring bt lock**\n");
++			printk("%s: btlock acquired\n", __FUNCTION__);
++		}
++		else {
++			/* For a exceptional case, release btlock */
++			bcm_bt_unlock(lock_cookie_wifi);
++		}
++#endif /* ENABLE_4335BT_WAR */
++
++#ifdef BUS_POWER_RESTORE
++		err = plat_data->set_power(on, adapter);
++#else
++		err = plat_data->set_power(on);
++#endif
++	}
++
++	if (msec && !err)
++		OSL_SLEEP(msec);
++
++	if (on && !err)
++		is_power_on = TRUE;
++	else
++		is_power_on = FALSE;
++
++#endif /* CONFIG_DTS */
++
++	return err;
++fail:
++	if (on) {
++		wifi_clr_adapter_status(adapter, WIFI_STATUS_POWER_ON);
++	} else {
++		wifi_set_adapter_status(adapter, WIFI_STATUS_POWER_ON);
++	}
++	return err;
++}
++
++int wifi_platform_bus_enumerate(wifi_adapter_info_t *adapter, bool device_present)
++{
++	int err = 0;
++	struct wifi_platform_data *plat_data;
++
++	if (!adapter || !adapter->wifi_plat_data)
++		return -EINVAL;
++	plat_data = adapter->wifi_plat_data;
++
++	DHD_ERROR(("%s device present %d\n", __FUNCTION__, device_present));
++	if (plat_data->set_carddetect) {
++		err = plat_data->set_carddetect(device_present);
++	}
++	return err;
++
++}
++
++int wifi_platform_get_mac_addr(wifi_adapter_info_t *adapter, unsigned char *buf)
++{
++	struct wifi_platform_data *plat_data;
++
++	DHD_ERROR(("%s\n", __FUNCTION__));
++	if (!buf || !adapter || !adapter->wifi_plat_data)
++		return -EINVAL;
++	plat_data = adapter->wifi_plat_data;
++	if (plat_data->get_mac_addr) {
++		return plat_data->get_mac_addr(buf);
++	}
++	return -EOPNOTSUPP;
++}
++
++void *
++#ifdef CUSTOM_COUNTRY_CODE
++wifi_platform_get_country_code(wifi_adapter_info_t *adapter, char *ccode, u32 flags)
++#else
++wifi_platform_get_country_code(wifi_adapter_info_t *adapter, char *ccode)
++#endif /* CUSTOM_COUNTRY_CODE */
++{
++	/* get_country_code was added after 2.6.39 */
++#if	(LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39))
++	struct wifi_platform_data *plat_data;
++
++	if (!ccode || !adapter || !adapter->wifi_plat_data)
++		return NULL;
++	plat_data = adapter->wifi_plat_data;
++
++	DHD_TRACE(("%s\n", __FUNCTION__));
++	if (plat_data->get_country_code) {
++#ifdef CUSTOM_FORCE_NODFS_FLAG
++		return plat_data->get_country_code(ccode, flags);
++#else
++		return plat_data->get_country_code(ccode);
++#endif /* CUSTOM_COUNTRY_CODE */
++	}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) */
++
++	return NULL;
++}
++
++#ifndef CUSTOMER_HW
++static int wifi_plat_dev_drv_probe(struct platform_device *pdev)
++{
++	struct resource *resource;
++	wifi_adapter_info_t *adapter;
++#if defined(CONFIG_DTS) && defined(CUSTOMER_OOB)
++	int irq, gpio;
++#endif /* CONFIG_DTS */
++
++	/* Android style wifi platform data device ("bcmdhd_wlan" or "bcm4329_wlan")
++	 * is kept for backward compatibility and supports only 1 adapter
++	 */
++	ASSERT(dhd_wifi_platdata != NULL);
++	ASSERT(dhd_wifi_platdata->num_adapters == 1);
++	adapter = &dhd_wifi_platdata->adapters[0];
++#if defined(CONFIG_WIFI_CONTROL_FUNC)
++	adapter->wifi_plat_data = (struct wifi_platform_data *)(pdev->dev.platform_data);
++#else
++	adapter->wifi_plat_data = (void *)&dhd_wlan_control;
++#endif
++
++	resource = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "bcmdhd_wlan_irq");
++	if (resource == NULL)
++		resource = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "bcm4329_wlan_irq");
++	if (resource) {
++		adapter->irq_num = resource->start;
++		adapter->intr_flags = resource->flags & IRQF_TRIGGER_MASK;
++#ifdef DHD_ISR_NO_SUSPEND
++		adapter->intr_flags |= IRQF_NO_SUSPEND;
++#endif
++	}
++
++#ifdef CONFIG_DTS
++	wifi_regulator = regulator_get(&pdev->dev, "wlreg_on");
++	if (wifi_regulator == NULL) {
++		DHD_ERROR(("%s regulator is null\n", __FUNCTION__));
++		return -1;
++	}
++
++#if defined(CUSTOMER_OOB)
++	/* This is to get the irq for the OOB */
++	gpio = of_get_gpio(pdev->dev.of_node, 0);
++
++	if (gpio < 0) {
++		DHD_ERROR(("%s gpio information is incorrect\n", __FUNCTION__));
++		return -1;
++	}
++	irq = gpio_to_irq(gpio);
++	if (irq < 0) {
++		DHD_ERROR(("%s irq information is incorrect\n", __FUNCTION__));
++		return -1;
++	}
++	adapter->irq_num = irq;
++
++	/* need to change the flags according to our requirement */
++	adapter->intr_flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL |
++		IORESOURCE_IRQ_SHAREABLE;
++#endif
++#endif /* CONFIG_DTS */
++
++	wifi_plat_dev_probe_ret = dhd_wifi_platform_load();
++	return wifi_plat_dev_probe_ret;
++}
++
++static int wifi_plat_dev_drv_remove(struct platform_device *pdev)
++{
++	wifi_adapter_info_t *adapter;
++
++	/* Android style wifi platform data device ("bcmdhd_wlan" or "bcm4329_wlan")
++	 * is kept for backward compatibility and supports only 1 adapter
++	 */
++	ASSERT(dhd_wifi_platdata != NULL);
++	ASSERT(dhd_wifi_platdata->num_adapters == 1);
++	adapter = &dhd_wifi_platdata->adapters[0];
++	if (is_power_on) {
++#ifdef BCMPCIE
++		wifi_platform_bus_enumerate(adapter, FALSE);
++		wifi_platform_set_power(adapter, FALSE, WIFI_TURNOFF_DELAY);
++#else
++		wifi_platform_set_power(adapter, FALSE, WIFI_TURNOFF_DELAY);
++		wifi_platform_bus_enumerate(adapter, FALSE);
++#endif /* BCMPCIE */
++	}
++
++#ifdef CONFIG_DTS
++	regulator_put(wifi_regulator);
++#endif /* CONFIG_DTS */
++	return 0;
++}
++
++static int wifi_plat_dev_drv_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	DHD_TRACE(("##> %s\n", __FUNCTION__));
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY) && \
++	defined(BCMSDIO)
++	bcmsdh_oob_intr_set(0);
++#endif /* (OOB_INTR_ONLY) */
++	return 0;
++}
++
++static int wifi_plat_dev_drv_resume(struct platform_device *pdev)
++{
++	DHD_TRACE(("##> %s\n", __FUNCTION__));
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY) && \
++	defined(BCMSDIO)
++	if (dhd_os_check_if_up(wl_cfg80211_get_dhdp()))
++		bcmsdh_oob_intr_set(1);
++#endif /* (OOB_INTR_ONLY) */
++	return 0;
++}
++
++#ifdef CONFIG_DTS
++static const struct of_device_id wifi_device_dt_match[] = {
++	{ .compatible = "android,bcmdhd_wlan", },
++	{},
++};
++#endif /* CONFIG_DTS */
++
++static struct platform_driver wifi_platform_dev_driver = {
++	.probe          = wifi_plat_dev_drv_probe,
++	.remove         = wifi_plat_dev_drv_remove,
++	.suspend        = wifi_plat_dev_drv_suspend,
++	.resume         = wifi_plat_dev_drv_resume,
++	.driver         = {
++	.name   = WIFI_PLAT_NAME,
++#ifdef CONFIG_DTS
++	.of_match_table = wifi_device_dt_match,
++#endif /* CONFIG_DTS */
++	}
++};
++
++static struct platform_driver wifi_platform_dev_driver_legacy = {
++	.probe          = wifi_plat_dev_drv_probe,
++	.remove         = wifi_plat_dev_drv_remove,
++	.suspend        = wifi_plat_dev_drv_suspend,
++	.resume         = wifi_plat_dev_drv_resume,
++	.driver         = {
++	.name	= WIFI_PLAT_NAME2,
++	}
++};
++
++static int wifi_platdev_match(struct device *dev, void *data)
++{
++	char *name = (char*)data;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	const struct platform_device *pdev = to_platform_device(dev);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++	if (strcmp(pdev->name, name) == 0) {
++		DHD_ERROR(("found wifi platform device %s\n", name));
++		return TRUE;
++	}
++
++	return FALSE;
++}
++#endif
++
++static int wifi_ctrlfunc_register_drv(void)
++{
++	wifi_adapter_info_t *adapter;
++
++#ifndef CUSTOMER_HW
++	int err = 0;
++	struct device *dev1, *dev2;
++	dev1 = bus_find_device(&platform_bus_type, NULL, WIFI_PLAT_NAME, wifi_platdev_match);
++	dev2 = bus_find_device(&platform_bus_type, NULL, WIFI_PLAT_NAME2, wifi_platdev_match);
++#endif
++
++#if !defined(CONFIG_DTS) && !defined(CUSTOMER_HW)
++	if (!dts_enabled) {
++		if (dev1 == NULL && dev2 == NULL) {
++			DHD_ERROR(("no wifi platform data, skip\n"));
++			return -ENXIO;
++		}
++	}
++#endif /* !defined(CONFIG_DTS) */
++
++	/* multi-chip support not enabled, build one adapter information for
++	 * DHD (either SDIO, USB or PCIe)
++	 */
++	adapter = kzalloc(sizeof(wifi_adapter_info_t), GFP_KERNEL);
++	if (adapter == NULL) {
++		DHD_ERROR(("%s:adapter alloc failed", __FUNCTION__));
++		return -ENOMEM;
++	}
++	adapter->name = "DHD generic adapter";
++	adapter->bus_type = -1;
++	adapter->bus_num = -1;
++	adapter->slot_num = -1;
++	adapter->irq_num = -1;
++	is_power_on = FALSE;
++	wifi_plat_dev_probe_ret = 0;
++	dhd_wifi_platdata = kzalloc(sizeof(bcmdhd_wifi_platdata_t), GFP_KERNEL);
++	dhd_wifi_platdata->num_adapters = 1;
++	dhd_wifi_platdata->adapters = adapter;
++	init_waitqueue_head(&adapter->status_event);
++
++#ifndef CUSTOMER_HW
++	if (dev1) {
++		err = platform_driver_register(&wifi_platform_dev_driver);
++		if (err) {
++			DHD_ERROR(("%s: failed to register wifi ctrl func driver\n",
++				__FUNCTION__));
++			return err;
++		}
++	}
++	if (dev2) {
++		err = platform_driver_register(&wifi_platform_dev_driver_legacy);
++		if (err) {
++			DHD_ERROR(("%s: failed to register wifi ctrl func legacy driver\n",
++				__FUNCTION__));
++			return err;
++		}
++	}
++#endif
++
++#if !defined(CONFIG_DTS)
++	if (dts_enabled) {
++		struct resource *resource;
++		adapter->wifi_plat_data = (void *)&dhd_wlan_control;
++		resource = &dhd_wlan_resources;
++#ifdef CUSTOMER_HW
++		wifi_plat_dev_probe_ret = dhd_wlan_init_plat_data();
++		if (wifi_plat_dev_probe_ret)
++			return wifi_plat_dev_probe_ret;
++#endif
++		adapter->irq_num = resource->start;
++		adapter->intr_flags = resource->flags & IRQF_TRIGGER_MASK;
++#ifdef DHD_ISR_NO_SUSPEND
++		adapter->intr_flags |= IRQF_NO_SUSPEND;
++#endif
++		wifi_plat_dev_probe_ret = dhd_wifi_platform_load();
++	}
++#endif /* !defined(CONFIG_DTS) */
++
++
++#if defined(CONFIG_DTS) && !defined(CUSTOMER_HW)
++	wifi_plat_dev_probe_ret = platform_driver_register(&wifi_platform_dev_driver);
++#endif /* CONFIG_DTS */
++
++	/* return probe function's return value if registeration succeeded */
++	return wifi_plat_dev_probe_ret;
++}
++
++void wifi_ctrlfunc_unregister_drv(void)
++{
++#ifndef CONFIG_DTS
++	wifi_adapter_info_t *adapter;
++#endif
++
++#if defined(CONFIG_DTS) && !defined(CUSTOMER_HW)
++	DHD_ERROR(("unregister wifi platform drivers\n"));
++	platform_driver_unregister(&wifi_platform_dev_driver);
++#else
++#ifndef CUSTOMER_HW
++	struct device *dev1, *dev2;
++	dev1 = bus_find_device(&platform_bus_type, NULL, WIFI_PLAT_NAME, wifi_platdev_match);
++	dev2 = bus_find_device(&platform_bus_type, NULL, WIFI_PLAT_NAME2, wifi_platdev_match);
++	if (!dts_enabled)
++		if (dev1 == NULL && dev2 == NULL)
++			return;
++#endif
++	DHD_ERROR(("unregister wifi platform drivers\n"));
++#ifndef CUSTOMER_HW
++	if (dev1)
++		platform_driver_unregister(&wifi_platform_dev_driver);
++	if (dev2)
++		platform_driver_unregister(&wifi_platform_dev_driver_legacy);
++#endif
++	if (dts_enabled) {
++		adapter = &dhd_wifi_platdata->adapters[0];
++		if (is_power_on) {
++			wifi_platform_set_power(adapter, FALSE, WIFI_TURNOFF_DELAY);
++		}
++		wifi_platform_bus_enumerate(adapter, FALSE);
++	}
++#endif /* !defined(CONFIG_DTS) */
++
++#if defined(CUSTOMER_HW)
++	dhd_wlan_deinit_plat_data(adapter);
++#endif
++
++	kfree(dhd_wifi_platdata->adapters);
++	dhd_wifi_platdata->adapters = NULL;
++	dhd_wifi_platdata->num_adapters = 0;
++	kfree(dhd_wifi_platdata);
++	dhd_wifi_platdata = NULL;
++}
++
++#ifndef CUSTOMER_HW
++static int bcmdhd_wifi_plat_dev_drv_probe(struct platform_device *pdev)
++{
++	dhd_wifi_platdata = (bcmdhd_wifi_platdata_t *)(pdev->dev.platform_data);
++
++	return dhd_wifi_platform_load();
++}
++
++static int bcmdhd_wifi_plat_dev_drv_remove(struct platform_device *pdev)
++{
++	int i;
++	wifi_adapter_info_t *adapter;
++	ASSERT(dhd_wifi_platdata != NULL);
++
++	/* power down all adapters */
++	for (i = 0; i < dhd_wifi_platdata->num_adapters; i++) {
++		adapter = &dhd_wifi_platdata->adapters[i];
++		wifi_platform_set_power(adapter, FALSE, WIFI_TURNOFF_DELAY);
++		wifi_platform_bus_enumerate(adapter, FALSE);
++	}
++	return 0;
++}
++
++static struct platform_driver dhd_wifi_platform_dev_driver = {
++	.probe          = bcmdhd_wifi_plat_dev_drv_probe,
++	.remove         = bcmdhd_wifi_plat_dev_drv_remove,
++	.driver         = {
++	.name   = WIFI_PLAT_EXT,
++	}
++};
++#endif
++
++int dhd_wifi_platform_register_drv(void)
++{
++	int err = 0;
++#ifndef CUSTOMER_HW
++	struct device *dev;
++
++	/* register Broadcom wifi platform data driver if multi-chip is enabled,
++	 * otherwise use Android style wifi platform data (aka wifi control function)
++	 * if it exists
++	 *
++	 * to support multi-chip DHD, Broadcom wifi platform data device must
++	 * be added in kernel early boot (e.g. board config file).
++	 */
++	if (cfg_multichip) {
++		dev = bus_find_device(&platform_bus_type, NULL, WIFI_PLAT_EXT, wifi_platdev_match);
++		if (dev == NULL) {
++			DHD_ERROR(("bcmdhd wifi platform data device not found!!\n"));
++			return -ENXIO;
++		}
++		err = platform_driver_register(&dhd_wifi_platform_dev_driver);
++	} else
++#endif
++	{
++		err = wifi_ctrlfunc_register_drv();
++
++		/* no wifi ctrl func either, load bus directly and ignore this error */
++		if (err) {
++			if (err == -ENXIO) {
++				/* wifi ctrl function does not exist */
++				err = dhd_wifi_platform_load();
++			} else {
++				/* unregister driver due to initialization failure */
++				wifi_ctrlfunc_unregister_drv();
++			}
++		}
++	}
++
++	return err;
++}
++
++#ifdef BCMPCIE
++static int dhd_wifi_platform_load_pcie(void)
++{
++	int err = 0;
++	int i;
++	wifi_adapter_info_t *adapter;
++
++	BCM_REFERENCE(i);
++	BCM_REFERENCE(adapter);
++
++	if (dhd_wifi_platdata == NULL) {
++		err = dhd_bus_register();
++	} else {
++		if (dhd_download_fw_on_driverload) {
++			/* power up all adapters */
++			for (i = 0; i < dhd_wifi_platdata->num_adapters; i++) {
++				int retry = POWERUP_MAX_RETRY;
++				adapter = &dhd_wifi_platdata->adapters[i];
++
++				DHD_ERROR(("Power-up adapter '%s'\n", adapter->name));
++				DHD_INFO((" - irq %d [flags %d], firmware: %s, nvram: %s\n",
++					adapter->irq_num, adapter->intr_flags, adapter->fw_path,
++					adapter->nv_path));
++				DHD_INFO((" - bus type %d, bus num %d, slot num %d\n\n",
++					adapter->bus_type, adapter->bus_num, adapter->slot_num));
++
++				do {
++					err = wifi_platform_set_power(adapter,
++						TRUE, WIFI_TURNON_DELAY);
++					if (err) {
++						DHD_ERROR(("failed to power up %s,"
++							" %d retry left\n",
++							adapter->name, retry));
++						/* WL_REG_ON state unknown, Power off forcely */
++						wifi_platform_set_power(adapter,
++							FALSE, WIFI_TURNOFF_DELAY);
++						continue;
++					} else {
++						err = wifi_platform_bus_enumerate(adapter, TRUE);
++						if (err) {
++							DHD_ERROR(("failed to enumerate bus %s, "
++								"%d retry left\n",
++								adapter->name, retry));
++							wifi_platform_set_power(adapter, FALSE,
++								WIFI_TURNOFF_DELAY);
++						} else {
++							break;
++						}
++					}
++				} while (retry--);
++
++				if (retry < 0) {
++					DHD_ERROR(("failed to power up %s, max retry reached**\n",
++						adapter->name));
++					return -ENODEV;
++				}
++			}
++		}
++
++		err = dhd_bus_register();
++
++		if (err) {
++			DHD_ERROR(("%s: pcie_register_driver failed\n", __FUNCTION__));
++			if (dhd_download_fw_on_driverload) {
++				/* power down all adapters */
++				for (i = 0; i < dhd_wifi_platdata->num_adapters; i++) {
++					adapter = &dhd_wifi_platdata->adapters[i];
++					wifi_platform_bus_enumerate(adapter, FALSE);
++					wifi_platform_set_power(adapter,
++						FALSE, WIFI_TURNOFF_DELAY);
++				}
++			}
++		}
++	}
++
++	return err;
++}
++#else
++static int dhd_wifi_platform_load_pcie(void)
++{
++	return 0;
++}
++#endif /* BCMPCIE  */
++
++
++void dhd_wifi_platform_unregister_drv(void)
++{
++#ifndef CUSTOMER_HW
++	if (cfg_multichip)
++		platform_driver_unregister(&dhd_wifi_platform_dev_driver);
++	else
++#endif
++		wifi_ctrlfunc_unregister_drv();
++}
++
++extern int dhd_watchdog_prio;
++extern int dhd_dpc_prio;
++extern uint dhd_deferred_tx;
++#if defined(BCMLXSDMMC) || defined(BCMDBUS)
++extern struct semaphore dhd_registration_sem;
++#endif 
++
++#ifdef BCMSDIO
++static int dhd_wifi_platform_load_sdio(void)
++{
++	int i;
++	int err = 0;
++	wifi_adapter_info_t *adapter;
++
++	BCM_REFERENCE(i);
++	BCM_REFERENCE(adapter);
++	/* Sanity check on the module parameters
++	 * - Both watchdog and DPC as tasklets are ok
++	 * - If both watchdog and DPC are threads, TX must be deferred
++	 */
++	if (!(dhd_watchdog_prio < 0 && dhd_dpc_prio < 0) &&
++		!(dhd_watchdog_prio >= 0 && dhd_dpc_prio >= 0 && dhd_deferred_tx))
++		return -EINVAL;
++
++#if defined(BCMLXSDMMC) && !defined(DHD_PRELOAD)
++	sema_init(&dhd_registration_sem, 0);
++#endif
++
++	if (dhd_wifi_platdata == NULL) {
++		DHD_ERROR(("DHD wifi platform data is required for Android build\n"));
++		DHD_ERROR(("DHD registeing bus directly\n"));
++		/* x86 bring-up PC needs no power-up operations */
++		err = dhd_bus_register();
++		return err;
++	}
++
++#if defined(BCMLXSDMMC) && !defined(DHD_PRELOAD)
++	/* power up all adapters */
++	for (i = 0; i < dhd_wifi_platdata->num_adapters; i++) {
++		bool chip_up = FALSE;
++		int retry = POWERUP_MAX_RETRY;
++		struct semaphore dhd_chipup_sem;
++
++		adapter = &dhd_wifi_platdata->adapters[i];
++
++		DHD_ERROR(("Power-up adapter '%s'\n", adapter->name));
++		DHD_INFO((" - irq %d [flags %d], firmware: %s, nvram: %s\n",
++			adapter->irq_num, adapter->intr_flags, adapter->fw_path, adapter->nv_path));
++		DHD_INFO((" - bus type %d, bus num %d, slot num %d\n\n",
++			adapter->bus_type, adapter->bus_num, adapter->slot_num));
++
++		do {
++			sema_init(&dhd_chipup_sem, 0);
++			err = dhd_bus_reg_sdio_notify(&dhd_chipup_sem);
++			if (err) {
++				DHD_ERROR(("%s dhd_bus_reg_sdio_notify fail(%d)\n\n",
++					__FUNCTION__, err));
++				return err;
++			}
++
++#ifdef CUSTOMER_HW_INGENIC
++			/*case: sdio device probed earlier than wifi driver.*/
++			if(down_trylock(&dhd_chipup_sem) == 0) {
++				dhd_bus_unreg_sdio_notify();
++				chip_up = TRUE;
++				break;
++			}
++#endif
++
++			err = wifi_platform_set_power(adapter, TRUE, WIFI_TURNON_DELAY);
++			if (err) {
++				dhd_bus_unreg_sdio_notify();
++				/* WL_REG_ON state unknown, Power off forcely */
++				wifi_platform_set_power(adapter, FALSE, WIFI_TURNOFF_DELAY);
++				continue;
++			} else {
++				wifi_platform_bus_enumerate(adapter, TRUE);
++			}
++
++			if (down_timeout(&dhd_chipup_sem, msecs_to_jiffies(POWERUP_WAIT_MS)) == 0) {
++				dhd_bus_unreg_sdio_notify();
++				chip_up = TRUE;
++				break;
++			}
++
++			DHD_ERROR(("failed to power up %s, %d retry left\n", adapter->name, retry));
++			dhd_bus_unreg_sdio_notify();
++			wifi_platform_set_power(adapter, FALSE, WIFI_TURNOFF_DELAY);
++			wifi_platform_bus_enumerate(adapter, FALSE);
++		} while (retry--);
++
++		if (!chip_up) {
++			DHD_ERROR(("failed to power up %s, max retry reached**\n", adapter->name));
++			return -ENODEV;
++		}
++
++	}
++
++	err = dhd_bus_register();
++
++	if (err) {
++		DHD_ERROR(("%s: sdio_register_driver failed\n", __FUNCTION__));
++		goto fail;
++	}
++
++	/*
++	 * Wait till MMC sdio_register_driver callback called and made driver attach.
++	 * It's needed to make sync up exit from dhd insmod  and
++	 * Kernel MMC sdio device callback registration
++	 */
++	err = down_timeout(&dhd_registration_sem, msecs_to_jiffies(DHD_REGISTRATION_TIMEOUT));
++	if (err) {
++		DHD_ERROR(("%s: sdio_register_driver timeout or error \n", __FUNCTION__));
++		dhd_bus_unregister();
++		goto fail;
++	}
++
++	return err;
++
++fail:
++	/* power down all adapters */
++	for (i = 0; i < dhd_wifi_platdata->num_adapters; i++) {
++		adapter = &dhd_wifi_platdata->adapters[i];
++		wifi_platform_set_power(adapter, FALSE, WIFI_TURNOFF_DELAY);
++		wifi_platform_bus_enumerate(adapter, FALSE);
++	}
++#else
++	/* x86 bring-up PC needs no power-up operations */
++	err = dhd_bus_register();
++#endif 
++
++	return err;
++}
++#else /* BCMSDIO */
++static int dhd_wifi_platform_load_sdio(void)
++{
++	return 0;
++}
++#endif /* BCMSDIO */
++
++#ifdef BCMDBUS
++static int dhd_wifi_platform_load_usb(void)
++{
++	int err = 0;
++#if !defined(DHD_PRELOAD)
++	wifi_adapter_info_t *adapter;
++	s32 timeout = -1;
++	int i;
++	enum wifi_adapter_status wait_status;
++#endif
++
++	err = dhd_bus_register();
++	if (err) {
++		DHD_ERROR(("%s: usb_register failed\n", __FUNCTION__));
++		goto exit;
++	}
++
++#if !defined(DHD_PRELOAD)
++	/* power up all adapters */
++	for (i = 0; i < dhd_wifi_platdata->num_adapters; i++) {
++		adapter = &dhd_wifi_platdata->adapters[i];
++		DHD_ERROR(("Power-up adapter '%s'\n", adapter->name));
++		DHD_INFO((" - irq %d [flags %d], firmware: %s, nvram: %s\n",
++			adapter->irq_num, adapter->intr_flags, adapter->fw_path, adapter->nv_path));
++		DHD_INFO((" - bus type %d, bus num %d, slot num %d\n\n",
++			adapter->bus_type, adapter->bus_num, adapter->slot_num));
++		err = wifi_platform_set_power(adapter, TRUE, WIFI_TURNON_DELAY);
++		if (err) {
++			DHD_ERROR(("failed to wifi_platform_set_power on %s\n", adapter->name));
++			goto fail;
++		}
++		if (dhd_download_fw_on_driverload)
++			wait_status = WIFI_STATUS_ATTACH;
++		else
++			wait_status = WIFI_STATUS_DETTACH;
++		timeout = wait_event_interruptible_timeout(adapter->status_event,
++			wifi_get_adapter_status(adapter, wait_status),
++			msecs_to_jiffies(DHD_REGISTRATION_TIMEOUT));
++		if (timeout <= 0) {
++			err = -1;
++			DHD_ERROR(("%s: usb_register_driver timeout\n", __FUNCTION__));
++			goto fail;
++		}
++	}
++#endif
++
++exit:
++	return err;
++
++#if !defined(DHD_PRELOAD)
++fail:
++	dhd_bus_unregister();
++	/* power down all adapters */
++	for (i = 0; i < dhd_wifi_platdata->num_adapters; i++) {
++		adapter = &dhd_wifi_platdata->adapters[i];
++		wifi_platform_set_power(adapter, FALSE, WIFI_TURNOFF_DELAY);
++	}
++
++	return err;
++#endif
++}
++#else /* BCMDBUS */
++static int dhd_wifi_platform_load_usb(void)
++{
++	return 0;
++}
++#endif /* BCMDBUS */
++
++static int dhd_wifi_platform_load()
++{
++	int err = 0;
++	printf("%s: Enter\n", __FUNCTION__);
++
++	wl_android_init();
++
++	if ((err = dhd_wifi_platform_load_usb()))
++		goto end;
++	else if ((err = dhd_wifi_platform_load_sdio()))
++		goto end;
++	else
++		err = dhd_wifi_platform_load_pcie();
++
++end:
++	if (err)
++		wl_android_exit();
++#if !defined(MULTIPLE_SUPPLICANT)
++	else
++		wl_android_post_init();
++#endif
++
++	return err;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux_sched.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux_sched.c
+new file mode 100644
+index 000000000..88c0cce63
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux_sched.c
+@@ -0,0 +1,51 @@
++/*
++ * Expose some of the kernel scheduler routines
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_linux_sched.c 514727 2014-11-12 03:02:48Z $
++ */
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/sched.h>
++#include <typedefs.h>
++#include <linuxver.h>
++
++int setScheduler(struct task_struct *p, int policy, struct sched_param *param)
++{
++	int rc = 0;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++	rc = sched_setscheduler(p, policy, param);
++#endif /* LinuxVer */
++	return rc;
++}
++
++int get_scheduler_policy(struct task_struct *p)
++{
++	int rc = SCHED_NORMAL;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++	rc = p->policy;
++#endif /* LinuxVer */
++	return rc;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux_wq.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux_wq.c
+new file mode 100644
+index 000000000..1cba8d140
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux_wq.c
+@@ -0,0 +1,379 @@
++/*
++ * Broadcom Dongle Host Driver (DHD), Generic work queue framework
++ * Generic interface to handle dhd deferred work events
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_linux_wq.c 641330 2016-06-02 06:55:00Z $
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/spinlock.h>
++#include <linux/fcntl.h>
++#include <linux/fs.h>
++#include <linux/ip.h>
++#include <linux/kfifo.h>
++
++#include <linuxver.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <bcmdevs.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_dbg.h>
++#include <dhd_linux_wq.h>
++
++typedef struct dhd_deferred_event {
++	u8 event;		/* holds the event */
++	void *event_data;	/* holds event specific data */
++	event_handler_t event_handler;
++	unsigned long pad;	/* for memory alignment to power of 2 */
++} dhd_deferred_event_t;
++
++#define DEFRD_EVT_SIZE	(sizeof(dhd_deferred_event_t))
++
++/*
++ * work events may occur simultaneously.
++ * can hold upto 64 low priority events and 16 high priority events
++ */
++#define DHD_PRIO_WORK_FIFO_SIZE	(16 * DEFRD_EVT_SIZE)
++#define DHD_WORK_FIFO_SIZE	(64 * DEFRD_EVT_SIZE)
++
++#define DHD_FIFO_HAS_FREE_SPACE(fifo) \
++	((fifo) && (kfifo_avail(fifo) >= DEFRD_EVT_SIZE))
++#define DHD_FIFO_HAS_ENOUGH_DATA(fifo) \
++	((fifo) && (kfifo_len(fifo) >= DEFRD_EVT_SIZE))
++
++struct dhd_deferred_wq {
++	struct work_struct deferred_work; /* should be the first member */
++
++	struct kfifo *prio_fifo;
++	struct kfifo *work_fifo;
++	u8 *prio_fifo_buf;
++	u8 *work_fifo_buf;
++	spinlock_t work_lock;
++	void *dhd_info; /* review: does it require */
++};
++
++static inline struct kfifo*
++dhd_kfifo_init(u8 *buf, int size, spinlock_t *lock)
++{
++	struct kfifo *fifo;
++	gfp_t flags = CAN_SLEEP() ? GFP_KERNEL : GFP_ATOMIC;
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33))
++	fifo = kfifo_init(buf, size, flags, lock);
++#else
++	fifo = (struct kfifo *)kzalloc(sizeof(struct kfifo), flags);
++	if (!fifo) {
++		return NULL;
++	}
++	kfifo_init(fifo, buf, size);
++#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33)) */
++	return fifo;
++}
++
++static inline void
++dhd_kfifo_free(struct kfifo *fifo)
++{
++	kfifo_free(fifo);
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 31))
++	/* FC11 releases the fifo memory */
++	kfree(fifo);
++#endif
++}
++
++/* deferred work functions */
++static void dhd_deferred_work_handler(struct work_struct *data);
++
++void*
++dhd_deferred_work_init(void *dhd_info)
++{
++	struct dhd_deferred_wq *work = NULL;
++	u8* buf;
++	unsigned long fifo_size = 0;
++	gfp_t flags = CAN_SLEEP() ? GFP_KERNEL : GFP_ATOMIC;
++
++	if (!dhd_info) {
++		DHD_ERROR(("%s: dhd info not initialized\n", __FUNCTION__));
++		goto return_null;
++	}
++
++	work = (struct dhd_deferred_wq *)kzalloc(sizeof(struct dhd_deferred_wq),
++		flags);
++	if (!work) {
++		DHD_ERROR(("%s: work queue creation failed\n", __FUNCTION__));
++		goto return_null;
++	}
++
++	INIT_WORK((struct work_struct *)work, dhd_deferred_work_handler);
++
++	/* initialize event fifo */
++	spin_lock_init(&work->work_lock);
++
++	/* allocate buffer to hold prio events */
++	fifo_size = DHD_PRIO_WORK_FIFO_SIZE;
++	fifo_size = is_power_of_2(fifo_size) ? fifo_size :
++			roundup_pow_of_two(fifo_size);
++	buf = (u8*)kzalloc(fifo_size, flags);
++	if (!buf) {
++		DHD_ERROR(("%s: prio work fifo allocation failed\n",
++			__FUNCTION__));
++		goto return_null;
++	}
++
++	/* Initialize prio event fifo */
++	work->prio_fifo = dhd_kfifo_init(buf, fifo_size, &work->work_lock);
++	if (!work->prio_fifo) {
++		kfree(buf);
++		goto return_null;
++	}
++
++	/* allocate buffer to hold work events */
++	fifo_size = DHD_WORK_FIFO_SIZE;
++	fifo_size = is_power_of_2(fifo_size) ? fifo_size :
++			roundup_pow_of_two(fifo_size);
++	buf = (u8*)kzalloc(fifo_size, flags);
++	if (!buf) {
++		DHD_ERROR(("%s: work fifo allocation failed\n", __FUNCTION__));
++		goto return_null;
++	}
++
++	/* Initialize event fifo */
++	work->work_fifo = dhd_kfifo_init(buf, fifo_size, &work->work_lock);
++	if (!work->work_fifo) {
++		kfree(buf);
++		goto return_null;
++	}
++
++	work->dhd_info = dhd_info;
++	DHD_ERROR(("%s: work queue initialized\n", __FUNCTION__));
++	return work;
++
++return_null:
++	if (work) {
++		dhd_deferred_work_deinit(work);
++	}
++
++	return NULL;
++}
++
++void
++dhd_deferred_work_deinit(void *work)
++{
++	struct dhd_deferred_wq *deferred_work = work;
++
++
++	if (!deferred_work) {
++		DHD_ERROR(("%s: deferred work has been freed already\n",
++			__FUNCTION__));
++		return;
++	}
++
++	/* cancel the deferred work handling */
++	cancel_work_sync((struct work_struct *)deferred_work);
++
++	/*
++	 * free work event fifo.
++	 * kfifo_free frees locally allocated fifo buffer
++	 */
++	if (deferred_work->prio_fifo) {
++		dhd_kfifo_free(deferred_work->prio_fifo);
++	}
++
++	if (deferred_work->work_fifo) {
++		dhd_kfifo_free(deferred_work->work_fifo);
++	}
++
++	kfree(deferred_work);
++}
++
++/* select kfifo according to priority */
++static inline struct kfifo *
++dhd_deferred_work_select_kfifo(struct dhd_deferred_wq *deferred_wq,
++	u8 priority)
++{
++	if (priority == DHD_WQ_WORK_PRIORITY_HIGH) {
++		return deferred_wq->prio_fifo;
++	} else if (priority == DHD_WQ_WORK_PRIORITY_LOW) {
++		return deferred_wq->work_fifo;
++	} else {
++		return NULL;
++	}
++}
++
++/*
++ *	Prepares event to be queued
++ *	Schedules the event
++ */
++int
++dhd_deferred_schedule_work(void *workq, void *event_data, u8 event,
++	event_handler_t event_handler, u8 priority)
++{
++	struct dhd_deferred_wq *deferred_wq = (struct dhd_deferred_wq *)workq;
++	struct kfifo *fifo;
++	dhd_deferred_event_t deferred_event;
++	int bytes_copied = 0;
++
++	if (!deferred_wq) {
++		DHD_ERROR(("%s: work queue not initialized\n", __FUNCTION__));
++		ASSERT(0);
++		return DHD_WQ_STS_UNINITIALIZED;
++	}
++
++	if (!event || (event >= DHD_MAX_WQ_EVENTS)) {
++		DHD_ERROR(("%s: unknown event, event=%d\n", __FUNCTION__,
++			event));
++		return DHD_WQ_STS_UNKNOWN_EVENT;
++	}
++
++	if (!priority || (priority >= DHD_WQ_MAX_PRIORITY)) {
++		DHD_ERROR(("%s: unknown priority, priority=%d\n",
++			__FUNCTION__, priority));
++		return DHD_WQ_STS_UNKNOWN_PRIORITY;
++	}
++
++	/*
++	 * default element size is 1, which can be changed
++	 * using kfifo_esize(). Older kernel(FC11) doesn't support
++	 * changing element size. For compatibility changing
++	 * element size is not prefered
++	 */
++	ASSERT(kfifo_esize(deferred_wq->prio_fifo) == 1);
++	ASSERT(kfifo_esize(deferred_wq->work_fifo) == 1);
++
++	deferred_event.event = event;
++	deferred_event.event_data = event_data;
++	deferred_event.event_handler = event_handler;
++
++	fifo = dhd_deferred_work_select_kfifo(deferred_wq, priority);
++	if (DHD_FIFO_HAS_FREE_SPACE(fifo)) {
++		bytes_copied = kfifo_in_spinlocked(fifo, &deferred_event,
++			DEFRD_EVT_SIZE, &deferred_wq->work_lock);
++	}
++	if (bytes_copied != DEFRD_EVT_SIZE) {
++		DHD_ERROR(("%s: failed to schedule deferred work, "
++			"priority=%d, bytes_copied=%d\n", __FUNCTION__,
++			priority, bytes_copied));
++		return DHD_WQ_STS_SCHED_FAILED;
++	}
++	schedule_work((struct work_struct *)deferred_wq);
++	return DHD_WQ_STS_OK;
++}
++
++static bool
++dhd_get_scheduled_work(struct dhd_deferred_wq *deferred_wq,
++	dhd_deferred_event_t *event)
++{
++	int bytes_copied = 0;
++
++	if (!deferred_wq) {
++		DHD_ERROR(("%s: work queue not initialized\n", __FUNCTION__));
++		return DHD_WQ_STS_UNINITIALIZED;
++	}
++
++	/*
++	 * default element size is 1 byte, which can be changed
++	 * using kfifo_esize(). Older kernel(FC11) doesn't support
++	 * changing element size. For compatibility changing
++	 * element size is not prefered
++	 */
++	ASSERT(kfifo_esize(deferred_wq->prio_fifo) == 1);
++	ASSERT(kfifo_esize(deferred_wq->work_fifo) == 1);
++
++	/* handle priority work */
++	if (DHD_FIFO_HAS_ENOUGH_DATA(deferred_wq->prio_fifo)) {
++		bytes_copied = kfifo_out_spinlocked(deferred_wq->prio_fifo,
++			event, DEFRD_EVT_SIZE, &deferred_wq->work_lock);
++	}
++
++	/* handle normal work if priority work doesn't have enough data */
++	if ((bytes_copied != DEFRD_EVT_SIZE) &&
++		DHD_FIFO_HAS_ENOUGH_DATA(deferred_wq->work_fifo)) {
++		bytes_copied = kfifo_out_spinlocked(deferred_wq->work_fifo,
++			event, DEFRD_EVT_SIZE, &deferred_wq->work_lock);
++	}
++
++	return (bytes_copied == DEFRD_EVT_SIZE);
++}
++
++static inline void
++dhd_deferred_dump_work_event(dhd_deferred_event_t *work_event)
++{
++	if (!work_event) {
++		DHD_ERROR(("%s: work_event is null\n", __FUNCTION__));
++		return;
++	}
++
++	DHD_ERROR(("%s: work_event->event = %d\n", __FUNCTION__,
++		work_event->event));
++	DHD_ERROR(("%s: work_event->event_data = %p\n", __FUNCTION__,
++		work_event->event_data));
++	DHD_ERROR(("%s: work_event->event_handler = %p\n", __FUNCTION__,
++		work_event->event_handler));
++}
++
++/*
++ *	Called when work is scheduled
++ */
++static void
++dhd_deferred_work_handler(struct work_struct *work)
++{
++	struct dhd_deferred_wq *deferred_work = (struct dhd_deferred_wq *)work;
++	dhd_deferred_event_t work_event;
++
++	if (!deferred_work) {
++		DHD_ERROR(("%s: work queue not initialized\n", __FUNCTION__));
++		return;
++	}
++
++	do {
++		if (!dhd_get_scheduled_work(deferred_work, &work_event)) {
++			DHD_TRACE(("%s: no event to handle\n", __FUNCTION__));
++			break;
++		}
++
++		if (work_event.event >= DHD_MAX_WQ_EVENTS) {
++			DHD_ERROR(("%s: unknown event\n", __FUNCTION__));
++			dhd_deferred_dump_work_event(&work_event);
++			ASSERT(work_event.event < DHD_MAX_WQ_EVENTS);
++			continue;
++		}
++
++
++		if (work_event.event_handler) {
++			work_event.event_handler(deferred_work->dhd_info,
++				work_event.event_data, work_event.event);
++		} else {
++			DHD_ERROR(("%s: event handler is null\n",
++				__FUNCTION__));
++			dhd_deferred_dump_work_event(&work_event);
++			ASSERT(work_event.event_handler != NULL);
++		}
++	} while (1);
++
++	return;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux_wq.h b/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux_wq.h
+new file mode 100644
+index 000000000..9c51d0665
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_linux_wq.h
+@@ -0,0 +1,81 @@
++/*
++ * Broadcom Dongle Host Driver (DHD), Generic work queue framework
++ * Generic interface to handle dhd deferred work events
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_linux_wq.h 704361 2017-06-13 08:50:38Z $
++ */
++#ifndef _dhd_linux_wq_h_
++#define _dhd_linux_wq_h_
++/*
++ *	Work event definitions
++ */
++enum _wq_event {
++	DHD_WQ_WORK_IF_ADD = 1,
++	DHD_WQ_WORK_IF_DEL,
++	DHD_WQ_WORK_SET_MAC,
++	DHD_WQ_WORK_SET_MCAST_LIST,
++	DHD_WQ_WORK_IPV6_NDO,
++	DHD_WQ_WORK_HANG_MSG,
++	DHD_WQ_WORK_SOC_RAM_DUMP,
++	DHD_WQ_WORK_DHD_LOG_DUMP,
++	DHD_WQ_WORK_INFORM_DHD_MON,
++	DHD_WQ_WORK_EVENT_LOGTRACE,
++	DHD_WQ_WORK_DMA_LB_MEM_REL,
++	DHD_WQ_WORK_DEBUG_UART_DUMP,
++	DHD_WQ_WORK_SSSR_DUMP,
++	DHD_WQ_WORK_PKTLOG_DUMP,
++#ifdef DHD_UPDATE_INTF_MAC
++	DHD_WQ_WORK_IF_UPDATE,
++#endif /* DHD_UPDATE_INTF_MAC */
++	DHD_MAX_WQ_EVENTS
++};
++
++/*
++ *	Work event priority
++ */
++enum wq_priority {
++	DHD_WQ_WORK_PRIORITY_LOW = 1,
++	DHD_WQ_WORK_PRIORITY_HIGH,
++	DHD_WQ_MAX_PRIORITY
++};
++
++/*
++ *	Error definitions
++ */
++#define DHD_WQ_STS_OK			 0
++#define DHD_WQ_STS_FAILED		-1	/* General failure */
++#define DHD_WQ_STS_UNINITIALIZED	-2
++#define DHD_WQ_STS_SCHED_FAILED		-3
++#define DHD_WQ_STS_UNKNOWN_EVENT	-4
++#define DHD_WQ_STS_UNKNOWN_PRIORITY	-5
++
++typedef void (*event_handler_t)(void *handle, void *event_data, u8 event);
++
++void *dhd_deferred_work_init(void *dhd);
++void dhd_deferred_work_deinit(void *workq);
++int dhd_deferred_schedule_work(void *workq, void *event_data, u8 event,
++	event_handler_t evt_handler, u8 priority);
++#endif /* _dhd_linux_wq_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_mschdbg.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_mschdbg.c
+new file mode 100644
+index 000000000..c1032f203
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_mschdbg.c
+@@ -0,0 +1,747 @@
++/*
++ * DHD debugability support
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * $Id: dhd_mschdbg.c 639872 2016-05-25 05:39:30Z $
++ */
++#ifdef SHOW_LOGTRACE
++#include <typedefs.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_dbg.h>
++#include <dhd_debug.h>
++#include <dhd_mschdbg.h>
++
++#include <event_log.h>
++#include <event_trace.h>
++#include <msgtrace.h>
++
++static const char *head_log = "";
++#define MSCH_EVENT_HEAD(space) \
++	do { \
++		MSCH_EVENT(("%s_E:  ", head_log)); \
++		if (space > 0) { \
++			int ii; \
++			for (ii = 0; ii < space; ii += 4) MSCH_EVENT(("    ")); \
++		} \
++	} while (0)
++#define MSCH_EVENT(args) do {if (dhd_msg_level & DHD_EVENT_VAL) printf args;} while (0)
++
++static uint64 solt_start_time[4], req_start_time[4], profiler_start_time[4];
++static uint32 solt_chanspec[4] = {0, }, req_start[4] = {0, };
++static bool lastMessages = FALSE;
++
++#define US_PRE_SEC		1000000
++
++static void dhd_mschdbg_us_to_sec(uint32 time_h, uint32 time_l, uint32 *sec, uint32 *remain)
++{
++	uint64 cur_time = ((uint64)(ntoh32(time_h)) << 32) | ntoh32(time_l);
++	uint64 r, u = 0;
++
++	r = cur_time;
++	while (time_h != 0) {
++		u += (uint64)((0xffffffff / US_PRE_SEC)) * time_h;
++		r = cur_time - u * US_PRE_SEC;
++		time_h = (uint32)(r >> 32);
++	}
++
++	*sec = (uint32)(u + ((uint32)(r) / US_PRE_SEC));
++	*remain = (uint32)(r) % US_PRE_SEC;
++}
++
++static char *dhd_mschdbg_display_time(uint32 time_h, uint32 time_l)
++{
++	static char display_time[32];
++	uint32 s, ss;
++
++	if (time_h == 0xffffffff && time_l == 0xffffffff) {
++		snprintf(display_time, 31, "-1");
++	} else {
++		dhd_mschdbg_us_to_sec(time_h, time_l, &s, &ss);
++		snprintf(display_time, 31, "%d.%06d", s, ss);
++	}
++	return display_time;
++}
++
++static void
++dhd_mschdbg_chanspec_list(int sp, char *data, uint16 ptr, uint16 chanspec_cnt)
++{
++	int i, cnt = (int)ntoh16(chanspec_cnt);
++	uint16 *chanspec_list = (uint16 *)(data + ntoh16(ptr));
++	char buf[CHANSPEC_STR_LEN];
++	chanspec_t c;
++
++	MSCH_EVENT_HEAD(sp);
++	MSCH_EVENT(("<chanspec_list>:"));
++	for (i = 0; i < cnt; i++) {
++		c = (chanspec_t)ntoh16(chanspec_list[i]);
++		MSCH_EVENT((" %s", wf_chspec_ntoa(c, buf)));
++	}
++	MSCH_EVENT(("\n"));
++}
++
++static void
++dhd_mschdbg_elem_list(int sp, char *title, char *data, uint16 ptr, uint16 list_cnt)
++{
++	int i, cnt = (int)ntoh16(list_cnt);
++	uint32 *list = (uint32 *)(data + ntoh16(ptr));
++
++	MSCH_EVENT_HEAD(sp);
++	MSCH_EVENT(("%s_list: ", title));
++	for (i = 0; i < cnt; i++) {
++		MSCH_EVENT(("0x%08x->", ntoh32(list[i])));
++	}
++	MSCH_EVENT(("null\n"));
++}
++
++static void
++dhd_mschdbg_req_param_profiler_event_data(int sp, int ver, char *data, uint16 ptr)
++{
++	int sn = sp + 4;
++	msch_req_param_profiler_event_data_t *p =
++		(msch_req_param_profiler_event_data_t *)(data + ntoh16(ptr));
++	uint32 type, flags;
++
++	MSCH_EVENT_HEAD(sp);
++	MSCH_EVENT(("<request parameters>\n"));
++	MSCH_EVENT_HEAD(sn);
++	MSCH_EVENT(("req_type: "));
++
++	type = p->req_type;
++	if (type < 4) {
++		char *req_type[] = {"fixed", "start-flexible", "duration-flexible",
++			"both-flexible"};
++		MSCH_EVENT(("%s", req_type[type]));
++	}
++	else
++		MSCH_EVENT(("unknown(%d)", type));
++
++	flags = ntoh16(p->flags);
++	if (flags & WL_MSCH_REQ_FLAGS_CHAN_CONTIGUOUS)
++		MSCH_EVENT((", CHAN_CONTIGUOUS"));
++	if (flags & WL_MSCH_REQ_FLAGS_MERGE_CONT_SLOTS)
++		MSCH_EVENT((", MERGE_CONT_SLOTS"));
++	if (flags & WL_MSCH_REQ_FLAGS_PREMTABLE)
++		MSCH_EVENT((", PREMTABLE"));
++	if (flags & WL_MSCH_REQ_FLAGS_PREMT_CURTS)
++		MSCH_EVENT((", PREMT_CURTS"));
++	if (flags & WL_MSCH_REQ_FLAGS_PREMT_IMMEDIATE)
++		MSCH_EVENT((", PREMT_IMMEDIATE"));
++	MSCH_EVENT((", priority: %d\n", p->priority));
++
++	MSCH_EVENT_HEAD(sn);
++	MSCH_EVENT(("start-time: %s, duration: %d(us), interval: %d(us)\n",
++		dhd_mschdbg_display_time(p->start_time_h, p->start_time_l),
++		ntoh32(p->duration), ntoh32(p->interval)));
++
++	if (type == WL_MSCH_RT_DUR_FLEX) {
++		MSCH_EVENT_HEAD(sn);
++		MSCH_EVENT(("dur_flex: %d(us)\n", ntoh32(p->flex.dur_flex)));
++	} else if (type == WL_MSCH_RT_BOTH_FLEX) {
++		MSCH_EVENT_HEAD(sn);
++		MSCH_EVENT(("min_dur: %d(us), max_away_dur: %d(us)\n",
++			ntoh32(p->flex.bf.min_dur), ntoh32(p->flex.bf.max_away_dur)));
++
++		MSCH_EVENT_HEAD(sn);
++		MSCH_EVENT(("hi_prio_time: %s, hi_prio_interval: %d(us)\n",
++			dhd_mschdbg_display_time(p->flex.bf.hi_prio_time_h,
++			p->flex.bf.hi_prio_time_l),
++			ntoh32(p->flex.bf.hi_prio_interval)));
++	}
++}
++
++static void
++dhd_mschdbg_timeslot_profiler_event_data(int sp, int ver, char *title, char *data,
++	uint16 ptr, bool empty)
++{
++	int s, sn = sp + 4;
++	msch_timeslot_profiler_event_data_t *p =
++		(msch_timeslot_profiler_event_data_t *)(data + ntoh16(ptr));
++	char *state[] = {"NONE", "CHN_SW", "ONCHAN_FIRE", "OFF_CHN_PREP",
++		"OFF_CHN_DONE", "TS_COMPLETE"};
++
++	MSCH_EVENT_HEAD(sp);
++	MSCH_EVENT(("<%s timeslot>: ", title));
++	if (empty) {
++		MSCH_EVENT((" null\n"));
++		return;
++	}
++	else
++		MSCH_EVENT(("0x%08x\n", ntoh32(p->p_timeslot)));
++
++	s = (int)(ntoh32(p->state));
++	if (s > 5) s = 0;
++
++	MSCH_EVENT_HEAD(sn);
++	MSCH_EVENT(("id: %d, state[%d]: %s, chan_ctxt: [0x%08x]\n",
++		ntoh32(p->timeslot_id), ntoh32(p->state), state[s], ntoh32(p->p_chan_ctxt)));
++
++	MSCH_EVENT_HEAD(sn);
++	MSCH_EVENT(("fire_time: %s",
++		dhd_mschdbg_display_time(p->fire_time_h, p->fire_time_l)));
++
++	MSCH_EVENT((", pre_start_time: %s",
++		dhd_mschdbg_display_time(p->pre_start_time_h, p->pre_start_time_l)));
++
++	MSCH_EVENT((", end_time: %s",
++		dhd_mschdbg_display_time(p->end_time_h, p->end_time_l)));
++
++	MSCH_EVENT((", sch_dur: %s\n",
++		dhd_mschdbg_display_time(p->sch_dur_h, p->sch_dur_l)));
++}
++
++static void
++dhd_mschdbg_req_timing_profiler_event_data(int sp, int ver, char *title, char *data,
++	uint16 ptr, bool empty)
++{
++	int sn = sp + 4;
++	msch_req_timing_profiler_event_data_t *p =
++		(msch_req_timing_profiler_event_data_t *)(data + ntoh16(ptr));
++	uint32 type;
++
++	MSCH_EVENT_HEAD(sp);
++	MSCH_EVENT(("<%s req_timing>: ", title));
++	if (empty) {
++		MSCH_EVENT((" null\n"));
++		return;
++	}
++	else
++		MSCH_EVENT(("0x%08x (prev 0x%08x, next 0x%08x)\n",
++			ntoh32(p->p_req_timing), ntoh32(p->p_prev), ntoh32(p->p_next)));
++
++	MSCH_EVENT_HEAD(sn);
++	MSCH_EVENT(("flags:"));
++	type = ntoh16(p->flags);
++	if ((type & 0x7f) == 0)
++		MSCH_EVENT((" NONE"));
++	else {
++		if (type & WL_MSCH_RC_FLAGS_ONCHAN_FIRE)
++			MSCH_EVENT((" ONCHAN_FIRE"));
++		if (type & WL_MSCH_RC_FLAGS_START_FIRE_DONE)
++			MSCH_EVENT((" START_FIRE"));
++		if (type & WL_MSCH_RC_FLAGS_END_FIRE_DONE)
++			MSCH_EVENT((" END_FIRE"));
++		if (type & WL_MSCH_RC_FLAGS_ONFIRE_DONE)
++			MSCH_EVENT((" ONFIRE_DONE"));
++		if (type & WL_MSCH_RC_FLAGS_SPLIT_SLOT_START)
++			MSCH_EVENT((" SPLIT_SLOT_START"));
++		if (type & WL_MSCH_RC_FLAGS_SPLIT_SLOT_END)
++			MSCH_EVENT((" SPLIT_SLOT_END"));
++		if (type & WL_MSCH_RC_FLAGS_PRE_ONFIRE_DONE)
++			MSCH_EVENT((" PRE_ONFIRE_DONE"));
++	}
++	MSCH_EVENT(("\n"));
++
++	MSCH_EVENT_HEAD(sn);
++	MSCH_EVENT(("pre_start_time: %s",
++		dhd_mschdbg_display_time(p->pre_start_time_h, p->pre_start_time_l)));
++
++	MSCH_EVENT((", start_time: %s",
++		dhd_mschdbg_display_time(p->start_time_h, p->start_time_l)));
++
++	MSCH_EVENT((", end_time: %s\n",
++		dhd_mschdbg_display_time(p->end_time_h, p->end_time_l)));
++
++	if (p->p_timeslot && (p->timeslot_ptr == 0)) {
++		MSCH_EVENT_HEAD(sn);
++		MSCH_EVENT(("<%s timeslot>: 0x%08x\n", title, ntoh32(p->p_timeslot)));
++	} else
++		dhd_mschdbg_timeslot_profiler_event_data(sn, ver, title, data, p->timeslot_ptr,
++			(p->timeslot_ptr == 0));
++}
++
++static void
++dhd_mschdbg_chan_ctxt_profiler_event_data(int sp, int ver, char *data, uint16 ptr, bool empty)
++{
++	int sn = sp + 4;
++	msch_chan_ctxt_profiler_event_data_t *p =
++		(msch_chan_ctxt_profiler_event_data_t *)(data + ntoh16(ptr));
++	chanspec_t c;
++	char buf[CHANSPEC_STR_LEN];
++
++	MSCH_EVENT_HEAD(sp);
++	MSCH_EVENT(("<chan_ctxt>: "));
++	if (empty) {
++		MSCH_EVENT((" null\n"));
++		return;
++	}
++	else
++		MSCH_EVENT(("0x%08x (prev 0x%08x, next 0x%08x)\n",
++			ntoh32(p->p_chan_ctxt), ntoh32(p->p_prev), ntoh32(p->p_next)));
++
++	c = (chanspec_t)ntoh16(p->chanspec);
++
++	MSCH_EVENT_HEAD(sn);
++	MSCH_EVENT(("channel: %s, bf_sch_pending: %s, bf_skipped: %d\n",
++		wf_chspec_ntoa(c, buf), p->bf_sch_pending? "TRUE" : "FALSE",
++		ntoh32(p->bf_skipped_count)));
++
++	MSCH_EVENT_HEAD(sn);
++	MSCH_EVENT(("bf_link: prev 0x%08x, next 0x%08x\n",
++		ntoh32(p->bf_link_prev), ntoh32(p->bf_link_next)));
++
++	MSCH_EVENT_HEAD(sn);
++	MSCH_EVENT(("onchan_time: %s",
++		dhd_mschdbg_display_time(p->onchan_time_h, p->onchan_time_l)));
++	MSCH_EVENT((", actual_onchan_dur: %s",
++		dhd_mschdbg_display_time(p->actual_onchan_dur_h, p->actual_onchan_dur_l)));
++	MSCH_EVENT((", pend_onchan_dur: %s\n",
++		dhd_mschdbg_display_time(p->pend_onchan_dur_h, p->pend_onchan_dur_l)));
++
++	dhd_mschdbg_elem_list(sn, "req_entity", data, p->req_entity_list_ptr,
++		p->req_entity_list_cnt);
++	dhd_mschdbg_elem_list(sn, "bf_entity", data, p->bf_entity_list_ptr,
++		p->bf_entity_list_cnt);
++}
++
++static void
++dhd_mschdbg_req_entity_profiler_event_data(int sp, int ver, char *data, uint16 ptr, bool empty)
++{
++	int sn = sp + 4;
++	msch_req_entity_profiler_event_data_t *p =
++		(msch_req_entity_profiler_event_data_t *)(data + ntoh16(ptr));
++	char buf[CHANSPEC_STR_LEN];
++	chanspec_t c;
++	uint32 flags;
++
++	MSCH_EVENT_HEAD(sp);
++	MSCH_EVENT(("<req_entity>: "));
++	if (empty) {
++		MSCH_EVENT((" null\n"));
++		return;
++	}
++	else
++		MSCH_EVENT(("0x%08x (prev 0x%08x, next 0x%08x)\n",
++			ntoh32(p->p_req_entity), ntoh32(p->req_hdl_link_prev),
++			ntoh32(p->req_hdl_link_next)));
++
++	MSCH_EVENT_HEAD(sn);
++	MSCH_EVENT(("req_hdl: [0x%08x]\n", ntoh32(p->p_req_hdl)));
++
++	MSCH_EVENT_HEAD(sn);
++	MSCH_EVENT(("chan_ctxt_link: prev 0x%08x, next 0x%08x\n",
++		ntoh32(p->chan_ctxt_link_prev), ntoh32(p->chan_ctxt_link_next)));
++	MSCH_EVENT_HEAD(sn);
++	MSCH_EVENT(("rt_specific_link: prev 0x%08x, next 0x%08x\n",
++		ntoh32(p->rt_specific_link_prev), ntoh32(p->rt_specific_link_next)));
++	MSCH_EVENT_HEAD(sn);
++	MSCH_EVENT(("start_fixed_link: prev 0x%08x, next 0x%08x\n",
++		ntoh32(p->start_fixed_link_prev), ntoh32(p->start_fixed_link_next)));
++	MSCH_EVENT_HEAD(sn);
++	MSCH_EVENT(("both_flex_list: prev 0x%08x, next 0x%08x\n",
++		ntoh32(p->both_flex_list_prev), ntoh32(p->both_flex_list_next)));
++
++	c = (chanspec_t)ntoh16(p->chanspec);
++	MSCH_EVENT_HEAD(sn);
++	if (ver >= 2) {
++		MSCH_EVENT(("channel: %s, onchan Id %d, current chan Id %d, priority %d",
++			wf_chspec_ntoa(c, buf), ntoh16(p->onchan_chn_idx), ntoh16(p->cur_chn_idx),
++			ntoh16(p->priority)));
++		flags = ntoh32(p->flags);
++		if (flags & WL_MSCH_ENTITY_FLAG_MULTI_INSTANCE)
++			MSCH_EVENT((" : MULTI_INSTANCE\n"));
++		else
++			MSCH_EVENT(("\n"));
++		MSCH_EVENT_HEAD(sn);
++		MSCH_EVENT(("actual_start_time: %s, ",
++			dhd_mschdbg_display_time(p->actual_start_time_h, p->actual_start_time_l)));
++		MSCH_EVENT(("curts_fire_time: %s, ",
++			dhd_mschdbg_display_time(p->curts_fire_time_h, p->curts_fire_time_l)));
++	} else {
++		MSCH_EVENT(("channel: %s, priority %d, ", wf_chspec_ntoa(c, buf),
++			ntoh16(p->priority)));
++	}
++	MSCH_EVENT(("bf_last_serv_time: %s\n",
++		dhd_mschdbg_display_time(p->bf_last_serv_time_h, p->bf_last_serv_time_l)));
++
++	dhd_mschdbg_req_timing_profiler_event_data(sn, ver, "current", data, p->cur_slot_ptr,
++		(p->cur_slot_ptr == 0));
++	dhd_mschdbg_req_timing_profiler_event_data(sn, ver, "pending", data, p->pend_slot_ptr,
++		(p->pend_slot_ptr == 0));
++
++	if (p->p_chan_ctxt && (p->chan_ctxt_ptr == 0)) {
++		MSCH_EVENT_HEAD(sn);
++		MSCH_EVENT(("<chan_ctxt>: 0x%08x\n", ntoh32(p->p_chan_ctxt)));
++	}
++	else
++		dhd_mschdbg_chan_ctxt_profiler_event_data(sn, ver, data, p->chan_ctxt_ptr,
++			(p->chan_ctxt_ptr == 0));
++}
++
++static void
++dhd_mschdbg_req_handle_profiler_event_data(int sp, int ver, char *data, uint16 ptr, bool empty)
++{
++	int sn = sp + 4;
++	msch_req_handle_profiler_event_data_t *p =
++		(msch_req_handle_profiler_event_data_t *)(data + ntoh16(ptr));
++	uint32 flags;
++
++	MSCH_EVENT_HEAD(sp);
++	MSCH_EVENT(("<req_handle>: "));
++	if (empty) {
++		MSCH_EVENT((" null\n"));
++		return;
++	}
++	else
++		MSCH_EVENT(("0x%08x (prev 0x%08x, next 0x%08x)\n",
++			ntoh32(p->p_req_handle), ntoh32(p->p_prev), ntoh32(p->p_next)));
++
++	dhd_mschdbg_elem_list(sn, "req_entity", data, p->req_entity_list_ptr,
++		p->req_entity_list_cnt);
++	MSCH_EVENT_HEAD(sn);
++	MSCH_EVENT(("cb_func: [0x%08x], cb_func: [0x%08x]",
++		ntoh32(p->cb_func), ntoh32(p->cb_ctxt)));
++	if (ver < 2) {
++		MSCH_EVENT((", chan_cnt: %d", ntoh16(p->chan_cnt)));
++	}
++	flags = ntoh32(p->flags);
++	if (flags & WL_MSCH_REQ_HDL_FLAGS_NEW_REQ)
++		MSCH_EVENT((", NEW_REQ"));
++	MSCH_EVENT(("\n"));
++
++	dhd_mschdbg_req_param_profiler_event_data(sn, ver, data, p->req_param_ptr);
++
++	if (ver >= 2) {
++		MSCH_EVENT_HEAD(sn);
++		MSCH_EVENT(("req_time: %s\n",
++			dhd_mschdbg_display_time(p->req_time_h, p->req_time_l)));
++		MSCH_EVENT_HEAD(sn);
++		MSCH_EVENT(("chan_cnt: %d, chan idx %d, last chan idx %d\n",
++			ntoh16(p->chan_cnt), ntoh16(p->chan_idx), ntoh16(p->last_chan_idx)));
++		if (p->chanspec_list && p->chanspec_cnt) {
++			dhd_mschdbg_chanspec_list(sn, data, p->chanspec_list, p->chanspec_cnt);
++		}
++	}
++}
++
++static void
++dhd_mschdbg_profiler_profiler_event_data(int sp, int ver, char *data, uint16 ptr)
++{
++	msch_profiler_profiler_event_data_t *p =
++		(msch_profiler_profiler_event_data_t *)(data + ntoh16(ptr));
++	uint32 flags;
++
++	MSCH_EVENT_HEAD(sp);
++	MSCH_EVENT(("free list: req_hdl 0x%08x, req_entity 0x%08x,"
++		" chan_ctxt 0x%08x, chanspec 0x%08x\n",
++		ntoh32(p->free_req_hdl_list), ntoh32(p->free_req_entity_list),
++		ntoh32(p->free_chan_ctxt_list), ntoh32(p->free_chanspec_list)));
++
++	MSCH_EVENT_HEAD(sp);
++	MSCH_EVENT(("alloc count: chanspec %d, req_entity %d, req_hdl %d, "
++		"chan_ctxt %d, timeslot %d\n",
++		ntoh16(p->msch_chanspec_alloc_cnt), ntoh16(p->msch_req_entity_alloc_cnt),
++		ntoh16(p->msch_req_hdl_alloc_cnt), ntoh16(p->msch_chan_ctxt_alloc_cnt),
++		ntoh16(p->msch_timeslot_alloc_cnt)));
++
++	dhd_mschdbg_elem_list(sp, "req_hdl", data, p->msch_req_hdl_list_ptr,
++		p->msch_req_hdl_list_cnt);
++	dhd_mschdbg_elem_list(sp, "chan_ctxt", data, p->msch_chan_ctxt_list_ptr,
++		p->msch_chan_ctxt_list_cnt);
++	dhd_mschdbg_elem_list(sp, "req_timing", data, p->msch_req_timing_list_ptr,
++		p->msch_req_timing_list_cnt);
++	dhd_mschdbg_elem_list(sp, "start_fixed", data, p->msch_start_fixed_list_ptr,
++		p->msch_start_fixed_list_cnt);
++	dhd_mschdbg_elem_list(sp, "both_flex_req_entity", data,
++		p->msch_both_flex_req_entity_list_ptr,
++		p->msch_both_flex_req_entity_list_cnt);
++	dhd_mschdbg_elem_list(sp, "start_flex", data, p->msch_start_flex_list_ptr,
++		p->msch_start_flex_list_cnt);
++	dhd_mschdbg_elem_list(sp, "both_flex", data, p->msch_both_flex_list_ptr,
++		p->msch_both_flex_list_cnt);
++
++	if (p->p_cur_msch_timeslot && (p->cur_msch_timeslot_ptr == 0)) {
++		MSCH_EVENT_HEAD(sp);
++		MSCH_EVENT(("<cur_msch timeslot>: 0x%08x\n",
++			ntoh32(p->p_cur_msch_timeslot)));
++	} else
++		dhd_mschdbg_timeslot_profiler_event_data(sp, ver, "cur_msch", data,
++			p->cur_msch_timeslot_ptr, (p->cur_msch_timeslot_ptr == 0));
++
++	if (p->p_next_timeslot && (p->next_timeslot_ptr == 0)) {
++		MSCH_EVENT_HEAD(sp);
++		MSCH_EVENT(("<next timeslot>: 0x%08x\n",
++			ntoh32(p->p_next_timeslot)));
++	} else
++		dhd_mschdbg_timeslot_profiler_event_data(sp, ver, "next", data,
++			p->next_timeslot_ptr, (p->next_timeslot_ptr == 0));
++
++	MSCH_EVENT_HEAD(sp);
++	MSCH_EVENT(("ts_id: %d, ", ntoh32(p->ts_id)));
++	flags = ntoh32(p->flags);
++	if (flags & WL_MSCH_STATE_IN_TIEMR_CTXT)
++		MSCH_EVENT(("IN_TIEMR_CTXT, "));
++	if (flags & WL_MSCH_STATE_SCHD_PENDING)
++		MSCH_EVENT(("SCHD_PENDING, "));
++	MSCH_EVENT(("slotskip_flags: %d, cur_armed_timeslot: 0x%08x\n",
++		(ver >= 2)? ntoh32(p->slotskip_flag) : 0, ntoh32(p->cur_armed_timeslot)));
++	MSCH_EVENT_HEAD(sp);
++	MSCH_EVENT(("flex_list_cnt: %d, service_interval: %d, "
++		"max_lo_prio_interval: %d\n",
++		ntoh16(p->flex_list_cnt), ntoh32(p->service_interval),
++		ntoh32(p->max_lo_prio_interval)));
++}
++
++static void dhd_mschdbg_dump_data(dhd_pub_t *dhdp, void *raw_event_ptr, int type,
++	char *data, int len)
++{
++	uint64 t = 0, tt = 0;
++	uint32 s = 0, ss = 0;
++	int wlc_index, ver;
++
++	ver = (type & WL_MSCH_PROFILER_VER_MASK) >> WL_MSCH_PROFILER_VER_SHIFT;
++	wlc_index = (type & WL_MSCH_PROFILER_WLINDEX_MASK) >> WL_MSCH_PROFILER_WLINDEX_SHIFT;
++	if (wlc_index >= 4)
++		return;
++
++	type &= WL_MSCH_PROFILER_TYPE_MASK;
++	if (type <= WL_MSCH_PROFILER_PROFILE_END) {
++		msch_profiler_event_data_t *pevent = (msch_profiler_event_data_t *)data;
++		tt = ((uint64)(ntoh32(pevent->time_hi)) << 32) | ntoh32(pevent->time_lo);
++		dhd_mschdbg_us_to_sec(pevent->time_hi, pevent->time_lo, &s, &ss);
++	}
++
++	if (lastMessages && (type != WL_MSCH_PROFILER_MESSAGE) &&
++		(type != WL_MSCH_PROFILER_EVENT_LOG)) {
++		MSCH_EVENT_HEAD(0);
++		MSCH_EVENT(("\n"));
++		lastMessages = FALSE;
++	}
++
++	switch (type) {
++	case WL_MSCH_PROFILER_START:
++		MSCH_EVENT_HEAD(0);
++		MSCH_EVENT(("%06d.%06d START\n", s, ss));
++		break;
++
++	case WL_MSCH_PROFILER_EXIT:
++		MSCH_EVENT_HEAD(0);
++		MSCH_EVENT(("%06d.%06d EXIT\n", s, ss));
++		break;
++
++	case WL_MSCH_PROFILER_REQ:
++	{
++		msch_req_profiler_event_data_t *p = (msch_req_profiler_event_data_t *)data;
++		MSCH_EVENT_HEAD(0);
++		MSCH_EVENT(("\n"));
++		MSCH_EVENT_HEAD(0);
++		MSCH_EVENT(("===============================\n"));
++		MSCH_EVENT_HEAD(0);
++		MSCH_EVENT(("%06d.%06d [wl%d] REGISTER:\n", s, ss, wlc_index));
++		dhd_mschdbg_req_param_profiler_event_data(4, ver, data, p->req_param_ptr);
++		dhd_mschdbg_chanspec_list(4, data, p->chanspec_ptr, p->chanspec_cnt);
++		MSCH_EVENT_HEAD(0);
++		MSCH_EVENT(("===============================\n"));
++		MSCH_EVENT_HEAD(0);
++		MSCH_EVENT(("\n"));
++	}
++		break;
++
++	case WL_MSCH_PROFILER_CALLBACK:
++	{
++		msch_callback_profiler_event_data_t *p =
++			(msch_callback_profiler_event_data_t *)data;
++		char buf[CHANSPEC_STR_LEN];
++		chanspec_t chanspec;
++		uint16 cbtype;
++
++		MSCH_EVENT_HEAD(0);
++		MSCH_EVENT(("%06d.%06d [wl%d] CALLBACK: ", s, ss, wlc_index));
++		chanspec = (chanspec_t)ntoh16(p->chanspec);
++		MSCH_EVENT(("req_hdl[0x%08x], channel %s --",
++			ntoh32(p->p_req_hdl), wf_chspec_ntoa(chanspec, buf)));
++
++		cbtype = ntoh16(p->type);
++		if (cbtype & WL_MSCH_CT_ON_CHAN)
++			MSCH_EVENT((" ON_CHAN"));
++		if (cbtype & WL_MSCH_CT_OFF_CHAN)
++			MSCH_EVENT((" OFF_CHAN"));
++		if (cbtype & WL_MSCH_CT_REQ_START)
++			MSCH_EVENT((" REQ_START"));
++		if (cbtype & WL_MSCH_CT_REQ_END)
++			MSCH_EVENT((" REQ_END"));
++		if (cbtype & WL_MSCH_CT_SLOT_START)
++			MSCH_EVENT((" SLOT_START"));
++		if (cbtype & WL_MSCH_CT_SLOT_SKIP)
++			MSCH_EVENT((" SLOT_SKIP"));
++		if (cbtype & WL_MSCH_CT_SLOT_END)
++			MSCH_EVENT((" SLOT_END"));
++		if (cbtype & WL_MSCH_CT_OFF_CHAN_DONE)
++			MSCH_EVENT((" OFF_CHAN_DONE"));
++		if (cbtype & WL_MSCH_CT_PARTIAL)
++			MSCH_EVENT((" PARTIAL"));
++		if (cbtype & WL_MSCH_CT_PRE_ONCHAN)
++			MSCH_EVENT((" PRE_ONCHAN"));
++		if (cbtype & WL_MSCH_CT_PRE_REQ_START)
++			MSCH_EVENT((" PRE_REQ_START"));
++
++		if (cbtype & WL_MSCH_CT_REQ_START) {
++			req_start[wlc_index] = 1;
++			req_start_time[wlc_index] = tt;
++		} else if (cbtype & WL_MSCH_CT_REQ_END) {
++			if (req_start[wlc_index]) {
++				MSCH_EVENT((" : REQ duration %d",
++					(uint32)(tt - req_start_time[wlc_index])));
++				req_start[wlc_index] = 0;
++			}
++		}
++
++		if (cbtype & WL_MSCH_CT_SLOT_START) {
++			solt_chanspec[wlc_index] = p->chanspec;
++			solt_start_time[wlc_index] = tt;
++		} else if (cbtype & WL_MSCH_CT_SLOT_END) {
++			if (p->chanspec == solt_chanspec[wlc_index]) {
++				MSCH_EVENT((" : SLOT duration %d",
++					(uint32)(tt - solt_start_time[wlc_index])));
++				solt_chanspec[wlc_index] = 0;
++			}
++		}
++		MSCH_EVENT(("\n"));
++
++		if (cbtype & (WL_MSCH_CT_ON_CHAN | WL_MSCH_CT_SLOT_SKIP)) {
++			MSCH_EVENT_HEAD(4);
++			if (cbtype & WL_MSCH_CT_ON_CHAN) {
++				MSCH_EVENT(("ID %d onchan idx %d cur_chan_seq_start %s ",
++					ntoh32(p->timeslot_id), ntoh32(p->onchan_idx),
++					dhd_mschdbg_display_time(p->cur_chan_seq_start_time_h,
++					p->cur_chan_seq_start_time_l)));
++			}
++			t = ((uint64)(ntoh32(p->start_time_h)) << 32) |
++				ntoh32(p->start_time_l);
++			MSCH_EVENT(("start %s ",
++				dhd_mschdbg_display_time(p->start_time_h,
++				p->start_time_l)));
++			tt = ((uint64)(ntoh32(p->end_time_h)) << 32) | ntoh32(p->end_time_l);
++			MSCH_EVENT(("end %s duration %d\n",
++				dhd_mschdbg_display_time(p->end_time_h, p->end_time_l),
++				(p->end_time_h == 0xffffffff && p->end_time_l == 0xffffffff)?
++				-1 : (int)(tt - t)));
++		}
++
++	}
++		break;
++
++	case WL_MSCH_PROFILER_EVENT_LOG:
++	{
++		while (len > 0) {
++			msch_event_log_profiler_event_data_t *p =
++				(msch_event_log_profiler_event_data_t *)data;
++			int size = WL_MSCH_EVENT_LOG_HEAD_SIZE + p->hdr.count * sizeof(uint32);
++			data += size;
++			len -= size;
++			dhd_mschdbg_us_to_sec(p->time_hi, p->time_lo, &s, &ss);
++			MSCH_EVENT_HEAD(0);
++			MSCH_EVENT(("%06d.%06d [wl%d]: ", s, ss, p->hdr.tag));
++			p->hdr.tag = EVENT_LOG_TAG_MSCHPROFILE;
++			p->hdr.fmt_num = ntoh16(p->hdr.fmt_num);
++			dhd_dbg_verboselog_printf(dhdp, &p->hdr, raw_event_ptr, p->data);
++		}
++		lastMessages = TRUE;
++		break;
++	}
++
++	case WL_MSCH_PROFILER_MESSAGE:
++	{
++		msch_message_profiler_event_data_t *p = (msch_message_profiler_event_data_t *)data;
++		MSCH_EVENT_HEAD(0);
++		MSCH_EVENT(("%06d.%06d [wl%d]: %s", s, ss, wlc_index, p->message));
++		lastMessages = TRUE;
++		break;
++	}
++
++	case WL_MSCH_PROFILER_PROFILE_START:
++		profiler_start_time[wlc_index] = tt;
++		MSCH_EVENT_HEAD(0);
++		MSCH_EVENT(("-------------------------------\n"));
++		MSCH_EVENT_HEAD(0);
++		MSCH_EVENT(("%06d.%06d [wl%d] PROFILE DATA:\n", s, ss, wlc_index));
++		dhd_mschdbg_profiler_profiler_event_data(4, ver, data, 0);
++		break;
++
++	case WL_MSCH_PROFILER_PROFILE_END:
++		MSCH_EVENT_HEAD(0);
++		MSCH_EVENT(("%06d.%06d [wl%d] PROFILE END: take time %d\n", s, ss,
++			wlc_index, (uint32)(tt - profiler_start_time[wlc_index])));
++		MSCH_EVENT_HEAD(0);
++		MSCH_EVENT(("-------------------------------\n"));
++		MSCH_EVENT_HEAD(0);
++		MSCH_EVENT(("\n"));
++		break;
++
++	case WL_MSCH_PROFILER_REQ_HANDLE:
++		dhd_mschdbg_req_handle_profiler_event_data(4, ver, data, 0, FALSE);
++		break;
++
++	case WL_MSCH_PROFILER_REQ_ENTITY:
++		dhd_mschdbg_req_entity_profiler_event_data(4, ver, data, 0, FALSE);
++		break;
++
++	case WL_MSCH_PROFILER_CHAN_CTXT:
++		dhd_mschdbg_chan_ctxt_profiler_event_data(4, ver, data, 0, FALSE);
++		break;
++
++	case WL_MSCH_PROFILER_REQ_TIMING:
++		dhd_mschdbg_req_timing_profiler_event_data(4, ver, "msch", data, 0, FALSE);
++		break;
++
++	default:
++		MSCH_EVENT_HEAD(0);
++		MSCH_EVENT(("[wl%d] ERROR: unsupported EVENT reason code:%d; ",
++			wlc_index, type));
++		break;
++	}
++}
++
++void
++wl_mschdbg_event_handler(dhd_pub_t *dhdp, void *raw_event_ptr, int type, void *data, int len)
++{
++	head_log = "MSCH";
++	dhd_mschdbg_dump_data(dhdp, raw_event_ptr, type, (char *)data, len);
++}
++
++void
++wl_mschdbg_verboselog_handler(dhd_pub_t *dhdp, void *raw_event_ptr, int tag, uint32 *log_ptr)
++{
++	head_log = "CONSOLE";
++	if (tag == EVENT_LOG_TAG_MSCHPROFILE) {
++		msch_event_log_profiler_event_data_t *p =
++			(msch_event_log_profiler_event_data_t *)log_ptr;
++		uint32 s, ss;
++		dhd_mschdbg_us_to_sec(p->time_hi, p->time_lo, &s, &ss);
++		MSCH_EVENT_HEAD(0);
++		MSCH_EVENT(("%06d.%06d [wl%d]: ", s, ss, p->hdr.tag));
++		p->hdr.tag = EVENT_LOG_TAG_MSCHPROFILE;
++		p->hdr.fmt_num = ntoh16(p->hdr.fmt_num);
++		dhd_dbg_verboselog_printf(dhdp, &p->hdr, raw_event_ptr, p->data);
++	} else {
++		msch_collect_tlv_t *p = (msch_collect_tlv_t *)log_ptr;
++		int type = ntoh16(p->type);
++		int len = ntoh16(p->size);
++		dhd_mschdbg_dump_data(dhdp, raw_event_ptr, type, p->value, len);
++	}
++}
++#endif /* SHOW_LOGTRACE */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_mschdbg.h b/module_drivers/drivers/net/wireless/bcmdhd/dhd_mschdbg.h
+new file mode 100644
+index 000000000..749e1119f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_mschdbg.h
+@@ -0,0 +1,39 @@
++/*
++ * DHD debugability header file
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * $Id: dhd_mschdbg.h 571265 2015-07-14 20:50:18Z $
++ */
++
++#ifndef _dhd_mschdbg_h_
++#define _dhd_mschdbg_h_
++
++#ifdef SHOW_LOGTRACE
++extern void wl_mschdbg_event_handler(dhd_pub_t *dhdp, void *raw_event_ptr, int type,
++	void *data, int len);
++extern void wl_mschdbg_verboselog_handler(dhd_pub_t *dhdp, void *raw_event_ptr, int tag,
++	uint32 *log_ptr);
++#endif /* SHOW_LOGTRACE */
++
++#endif /* _dhd_mschdbg_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_msgbuf.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_msgbuf.c
+new file mode 100644
+index 000000000..bb56c1aa0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_msgbuf.c
+@@ -0,0 +1,8951 @@
++/**
++ * @file definition of host message ring functionality
++ * Provides type definitions and function prototypes used to link the
++ * DHD OS, bus, and protocol modules.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_msgbuf.c 704361 2017-06-13 08:50:38Z $
++ */
++
++
++#include <typedefs.h>
++#include <osl.h>
++
++#include <bcmutils.h>
++#include <bcmmsgbuf.h>
++#include <bcmendian.h>
++
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_proto.h>
++
++#include <dhd_bus.h>
++
++#include <dhd_dbg.h>
++#include <siutils.h>
++#include <dhd_debug.h>
++
++#include <dhd_flowring.h>
++
++#include <pcie_core.h>
++#include <bcmpcie.h>
++#include <dhd_pcie.h>
++#include <dhd_config.h>
++#ifdef DHD_TIMESYNC
++#include <dhd_timesync.h>
++#endif /* DHD_TIMESYNC */
++
++#if defined(DHD_LB)
++#include <linux/cpu.h>
++#include <bcm_ring.h>
++#define DHD_LB_WORKQ_SZ			    (8192)
++#define DHD_LB_WORKQ_SYNC           (16)
++#define DHD_LB_WORK_SCHED           (DHD_LB_WORKQ_SYNC * 2)
++#endif /* DHD_LB */
++
++#include <hnd_debug.h>
++#include <hnd_armtrap.h>
++
++#ifdef DHD_PKT_LOGGING
++#include <dhd_pktlog.h>
++#endif /* DHD_PKT_LOGGING */
++
++extern char dhd_version[];
++extern char fw_version[];
++
++/**
++ * Host configures a soft doorbell for d2h rings, by specifying a 32bit host
++ * address where a value must be written. Host may also interrupt coalescing
++ * on this soft doorbell.
++ * Use Case: Hosts with network processors, may register with the dongle the
++ * network processor's thread wakeup register and a value corresponding to the
++ * core/thread context. Dongle will issue a write transaction <address,value>
++ * to the PCIE RC which will need to be routed to the mapped register space, by
++ * the host.
++ */
++/* #define DHD_D2H_SOFT_DOORBELL_SUPPORT */
++
++/* Dependency Check */
++#if defined(IOCTLRESP_USE_CONSTMEM) && defined(DHD_USE_STATIC_CTRLBUF)
++#error "DHD_USE_STATIC_CTRLBUF is NOT working with DHD_USE_OSLPKT_FOR_RESPBUF"
++#endif /* IOCTLRESP_USE_CONSTMEM && DHD_USE_STATIC_CTRLBUF */
++
++#define RETRIES 2		/* # of retries to retrieve matching ioctl response */
++
++#define DEFAULT_RX_BUFFERS_TO_POST	256
++#define RXBUFPOST_THRESHOLD			32
++#define RX_BUF_BURST				32 /* Rx buffers for MSDU Data */
++
++#define DHD_STOP_QUEUE_THRESHOLD	200
++#define DHD_START_QUEUE_THRESHOLD	100
++
++#define RX_DMA_OFFSET		8 /* Mem2mem DMA inserts an extra 8 */
++#define IOCT_RETBUF_SIZE	(RX_DMA_OFFSET + WLC_IOCTL_MAXLEN)
++
++/* flags for ioctl pending status */
++#define MSGBUF_IOCTL_ACK_PENDING	(1<<0)
++#define MSGBUF_IOCTL_RESP_PENDING	(1<<1)
++
++#define DMA_ALIGN_LEN		4
++
++#define DMA_D2H_SCRATCH_BUF_LEN	8
++#define DMA_XFER_LEN_LIMIT	0x400000
++
++#ifdef BCM_HOST_BUF
++#ifndef DMA_HOST_BUFFER_LEN
++#define DMA_HOST_BUFFER_LEN	0x200000
++#endif
++#endif /* BCM_HOST_BUF */
++
++#define DHD_FLOWRING_IOCTL_BUFPOST_PKTSZ		8192
++
++#define DHD_FLOWRING_DEFAULT_NITEMS_POSTED_H2D		1
++#define DHD_FLOWRING_MAX_EVENTBUF_POST			32
++#define DHD_FLOWRING_MAX_IOCTLRESPBUF_POST		8
++#define DHD_H2D_INFORING_MAX_BUF_POST			32
++#define DHD_MAX_TSBUF_POST			8
++
++#define DHD_PROT_FUNCS	41
++
++/* Length of buffer in host for bus throughput measurement */
++#define DHD_BUS_TPUT_BUF_LEN 2048
++
++#define TXP_FLUSH_NITEMS
++
++/* optimization to write "n" tx items at a time to ring */
++#define TXP_FLUSH_MAX_ITEMS_FLUSH_CNT	48
++
++#define RING_NAME_MAX_LENGTH		24
++#define CTRLSUB_HOSTTS_MEESAGE_SIZE		1024
++/* Giving room before ioctl_trans_id rollsover. */
++#define BUFFER_BEFORE_ROLLOVER 300
++
++struct msgbuf_ring; /* ring context for common and flow rings */
++
++/**
++ * PCIE D2H DMA Complete Sync Modes
++ *
++ * Firmware may interrupt the host, prior to the D2H Mem2Mem DMA completes into
++ * Host system memory. A WAR using one of 3 approaches is needed:
++ * 1. Dongle places a modulo-253 seqnum in last word of each D2H message
++ * 2. XOR Checksum, with epoch# in each work item. Dongle builds an XOR checksum
++ *    writes in the last word of each work item. Each work item has a seqnum
++ *    number = sequence num % 253.
++ *
++ * 3. Read Barrier: Dongle does a host memory read access prior to posting an
++ *    interrupt, ensuring that D2H data transfer indeed completed.
++ * 4. Dongle DMA's all indices after producing items in the D2H ring, flushing
++ *    ring contents before the indices.
++ *
++ * Host does not sync for DMA to complete with option #3 or #4, and a noop sync
++ * callback (see dhd_prot_d2h_sync_none) may be bound.
++ *
++ * Dongle advertizes host side sync mechanism requirements.
++ */
++
++#define PCIE_D2H_SYNC_WAIT_TRIES    (512UL)
++#define PCIE_D2H_SYNC_NUM_OF_STEPS  (5UL)
++#define PCIE_D2H_SYNC_DELAY         (100UL)	/* in terms of usecs */
++
++/**
++ * Custom callback attached based upon D2H DMA Sync mode advertized by dongle.
++ *
++ * On success: return cmn_msg_hdr_t::msg_type
++ * On failure: return 0 (invalid msg_type)
++ */
++typedef uint8 (* d2h_sync_cb_t)(dhd_pub_t *dhd, struct msgbuf_ring *ring,
++                                volatile cmn_msg_hdr_t *msg, int msglen);
++
++/*
++ * +----------------------------------------------------------------------------
++ *
++ * RingIds and FlowId are not equivalent as ringids include D2H rings whereas
++ * flowids do not.
++ *
++ * Dongle advertizes the max H2D rings, as max_sub_queues = 'N' which includes
++ * the H2D common rings as well as the (N-BCMPCIE_H2D_COMMON_MSGRINGS) flowrings
++ *
++ * Here is a sample mapping for (based on PCIE Full Dongle Rev5) where,
++ *  BCMPCIE_H2D_COMMON_MSGRINGS = 2, i.e. 2 H2D common rings,
++ *  BCMPCIE_COMMON_MSGRINGS     = 5, i.e. include 3 D2H common rings.
++ *
++ *  H2D Control  Submit   RingId = 0        FlowId = 0 reserved never allocated
++ *  H2D RxPost   Submit   RingId = 1        FlowId = 1 reserved never allocated
++ *
++ *  D2H Control  Complete RingId = 2
++ *  D2H Transmit Complete RingId = 3
++ *  D2H Receive  Complete RingId = 4
++ *
++ *  H2D TxPost   FLOWRING RingId = 5         FlowId = 2     (1st flowring)
++ *  H2D TxPost   FLOWRING RingId = 6         FlowId = 3     (2nd flowring)
++ *  H2D TxPost   FLOWRING RingId = 5 + (N-1) FlowId = (N-1) (Nth flowring)
++ *
++ * When TxPost FlowId(s) are allocated, the FlowIds [0..FLOWID_RESERVED) are
++ * unused, where FLOWID_RESERVED is BCMPCIE_H2D_COMMON_MSGRINGS.
++ *
++ * Example: when a system supports 4 bc/mc and 128 uc flowrings, with
++ * BCMPCIE_H2D_COMMON_MSGRINGS = 2, and BCMPCIE_H2D_COMMON_MSGRINGS = 5, and the
++ * FlowId values would be in the range [2..133] and the corresponding
++ * RingId values would be in the range [5..136].
++ *
++ * The flowId allocator, may chose to, allocate Flowids:
++ *   bc/mc (per virtual interface) in one consecutive range [2..(2+VIFS))
++ *   X# of uc flowids in consecutive ranges (per station Id), where X is the
++ *   packet's access category (e.g. 4 uc flowids per station).
++ *
++ * CAUTION:
++ * When DMA indices array feature is used, RingId=5, corresponding to the 0th
++ * FLOWRING, will actually use the FlowId as index into the H2D DMA index,
++ * since the FlowId truly represents the index in the H2D DMA indices array.
++ *
++ * Likewise, in the D2H direction, the RingId - BCMPCIE_H2D_COMMON_MSGRINGS,
++ * will represent the index in the D2H DMA indices array.
++ *
++ * +----------------------------------------------------------------------------
++ */
++
++/* First TxPost Flowring Id */
++#define DHD_FLOWRING_START_FLOWID   BCMPCIE_H2D_COMMON_MSGRINGS
++
++/* Determine whether a ringid belongs to a TxPost flowring */
++#define DHD_IS_FLOWRING(ringid, max_flow_rings) \
++	((ringid) >= BCMPCIE_COMMON_MSGRINGS && \
++	(ringid) < ((max_flow_rings) + BCMPCIE_COMMON_MSGRINGS))
++
++/* Convert a H2D TxPost FlowId to a MsgBuf RingId */
++#define DHD_FLOWID_TO_RINGID(flowid) \
++	(BCMPCIE_COMMON_MSGRINGS + ((flowid) - BCMPCIE_H2D_COMMON_MSGRINGS))
++
++/* Convert a MsgBuf RingId to a H2D TxPost FlowId */
++#define DHD_RINGID_TO_FLOWID(ringid) \
++	(BCMPCIE_H2D_COMMON_MSGRINGS + ((ringid) - BCMPCIE_COMMON_MSGRINGS))
++
++/* Convert a H2D MsgBuf RingId to an offset index into the H2D DMA indices array
++ * This may be used for the H2D DMA WR index array or H2D DMA RD index array or
++ * any array of H2D rings.
++ */
++#define DHD_H2D_RING_OFFSET(ringid) \
++	(((ringid) >= BCMPCIE_COMMON_MSGRINGS) ? DHD_RINGID_TO_FLOWID(ringid) : (ringid))
++
++/* Convert a H2D MsgBuf Flowring Id to an offset index into the H2D DMA indices array
++ * This may be used for IFRM.
++ */
++#define DHD_H2D_FRM_FLOW_RING_OFFSET(ringid) \
++	((ringid) - BCMPCIE_COMMON_MSGRINGS)
++
++/* Convert a D2H MsgBuf RingId to an offset index into the D2H DMA indices array
++ * This may be used for the D2H DMA WR index array or D2H DMA RD index array or
++ * any array of D2H rings.
++ * d2h debug ring is located at the end, i.e. after all the tx flow rings and h2d debug ring
++ * max_h2d_rings: total number of h2d rings
++ */
++#define DHD_D2H_RING_OFFSET(ringid, max_h2d_rings) \
++	((ringid) > (max_h2d_rings) ? \
++		((ringid) - max_h2d_rings) : \
++		((ringid) - BCMPCIE_H2D_COMMON_MSGRINGS))
++
++/* Convert a D2H DMA Indices Offset to a RingId */
++#define DHD_D2H_RINGID(offset) \
++	((offset) + BCMPCIE_H2D_COMMON_MSGRINGS)
++
++
++#define DHD_DMAH_NULL      ((void*)NULL)
++
++/*
++ * Pad a DMA-able buffer by an additional cachline. If the end of the DMA-able
++ * buffer does not occupy the entire cacheline, and another object is placed
++ * following the DMA-able buffer, data corruption may occur if the DMA-able
++ * buffer is used to DMAing into (e.g. D2H direction), when HW cache coherency
++ * is not available.
++ */
++#if defined(L1_CACHE_BYTES)
++#define DHD_DMA_PAD        (L1_CACHE_BYTES)
++#else
++#define DHD_DMA_PAD        (128)
++#endif
++
++/* Used in loopback tests */
++typedef struct dhd_dmaxfer {
++	dhd_dma_buf_t srcmem;
++	dhd_dma_buf_t dstmem;
++	uint32        srcdelay;
++	uint32        destdelay;
++	uint32        len;
++	bool          in_progress;
++	uint64        start_usec;
++	uint32	      d11_lpbk;
++} dhd_dmaxfer_t;
++
++/**
++ * msgbuf_ring : This object manages the host side ring that includes a DMA-able
++ * buffer, the WR and RD indices, ring parameters such as max number of items
++ * an length of each items, and other miscellaneous runtime state.
++ * A msgbuf_ring may be used to represent a H2D or D2H common ring or a
++ * H2D TxPost ring as specified in the PCIE FullDongle Spec.
++ * Ring parameters are conveyed to the dongle, which maintains its own peer end
++ * ring state. Depending on whether the DMA Indices feature is supported, the
++ * host will update the WR/RD index in the DMA indices array in host memory or
++ * directly in dongle memory.
++ */
++typedef struct msgbuf_ring {
++	bool           inited;
++	uint16         idx;       /* ring id */
++	uint16         rd;        /* read index */
++	uint16         curr_rd;   /* read index for debug */
++	uint16         wr;        /* write index */
++	uint16         max_items; /* maximum number of items in ring */
++	uint16         item_len;  /* length of each item in the ring */
++	sh_addr_t      base_addr; /* LITTLE ENDIAN formatted: base address */
++	dhd_dma_buf_t  dma_buf;   /* DMA-able buffer: pa, va, len, dmah, secdma */
++	uint32         seqnum;    /* next expected item's sequence number */
++#ifdef TXP_FLUSH_NITEMS
++	void           *start_addr;
++	/* # of messages on ring not yet announced to dongle */
++	uint16         pend_items_count;
++#endif /* TXP_FLUSH_NITEMS */
++
++	uint8   ring_type;
++	uint8   n_completion_ids;
++	bool    create_pending;
++	uint16  create_req_id;
++	uint8   current_phase;
++	uint16	compeltion_ring_ids[MAX_COMPLETION_RING_IDS_ASSOCIATED];
++	uchar		name[RING_NAME_MAX_LENGTH];
++	uint32		ring_mem_allocated;
++} msgbuf_ring_t;
++
++#define DHD_RING_BGN_VA(ring)           ((ring)->dma_buf.va)
++#define DHD_RING_END_VA(ring) \
++	((uint8 *)(DHD_RING_BGN_VA((ring))) + \
++	 (((ring)->max_items - 1) * (ring)->item_len))
++
++
++
++/* This can be overwritten by module parameter defined in dhd_linux.c
++ * or by dhd iovar h2d_max_txpost.
++ */
++int h2d_max_txpost = H2DRING_TXPOST_MAX_ITEM;
++
++/** DHD protocol handle. Is an opaque type to other DHD software layers. */
++typedef struct dhd_prot {
++	osl_t *osh;		/* OSL handle */
++	uint16 rxbufpost;
++	uint16 max_rxbufpost;
++	uint16 max_eventbufpost;
++	uint16 max_ioctlrespbufpost;
++	uint16 max_tsbufpost;
++	uint16 max_infobufpost;
++	uint16 infobufpost;
++	uint16 cur_event_bufs_posted;
++	uint16 cur_ioctlresp_bufs_posted;
++	uint16 cur_ts_bufs_posted;
++
++	/* Flow control mechanism based on active transmits pending */
++	uint16 active_tx_count; /* increments on every packet tx, and decrements on tx_status */
++	uint16 h2d_max_txpost;
++	uint16 txp_threshold;  /* optimization to write "n" tx items at a time to ring */
++
++	/* MsgBuf Ring info: has a dhd_dma_buf that is dynamically allocated */
++	msgbuf_ring_t h2dring_ctrl_subn; /* H2D ctrl message submission ring */
++	msgbuf_ring_t h2dring_rxp_subn; /* H2D RxBuf post ring */
++	msgbuf_ring_t d2hring_ctrl_cpln; /* D2H ctrl completion ring */
++	msgbuf_ring_t d2hring_tx_cpln; /* D2H Tx complete message ring */
++	msgbuf_ring_t d2hring_rx_cpln; /* D2H Rx complete message ring */
++	msgbuf_ring_t *h2dring_info_subn; /* H2D info submission ring */
++	msgbuf_ring_t *d2hring_info_cpln; /* D2H info completion ring */
++
++	msgbuf_ring_t *h2d_flowrings_pool; /* Pool of preallocated flowings */
++	dhd_dma_buf_t flowrings_dma_buf; /* Contiguous DMA buffer for flowrings */
++	uint16        h2d_rings_total; /* total H2D (common rings + flowrings) */
++
++	uint32		rx_dataoffset;
++
++	dhd_mb_ring_t	mb_ring_fn;	/* called when dongle needs to be notified of new msg */
++	dhd_mb_ring_2_t	mb_2_ring_fn;	/* called when dongle needs to be notified of new msg */
++
++	/* ioctl related resources */
++	uint8 ioctl_state;
++	int16 ioctl_status;		/* status returned from dongle */
++	uint16 ioctl_resplen;
++	dhd_ioctl_recieved_status_t ioctl_received;
++	uint curr_ioctl_cmd;
++	dhd_dma_buf_t	retbuf;		/* For holding ioctl response */
++	dhd_dma_buf_t	ioctbuf;	/* For holding ioctl request */
++
++	dhd_dma_buf_t	d2h_dma_scratch_buf;	/* For holding d2h scratch */
++
++	/* DMA-able arrays for holding WR and RD indices */
++	uint32          rw_index_sz; /* Size of a RD or WR index in dongle */
++	dhd_dma_buf_t   h2d_dma_indx_wr_buf;	/* Array of H2D WR indices */
++	dhd_dma_buf_t	h2d_dma_indx_rd_buf;	/* Array of H2D RD indices */
++	dhd_dma_buf_t	d2h_dma_indx_wr_buf;	/* Array of D2H WR indices */
++	dhd_dma_buf_t	d2h_dma_indx_rd_buf;	/* Array of D2H RD indices */
++	dhd_dma_buf_t h2d_ifrm_indx_wr_buf;	/* Array of H2D WR indices for ifrm */
++
++	dhd_dma_buf_t	host_bus_throughput_buf; /* bus throughput measure buffer */
++
++	dhd_dma_buf_t   *flowring_buf;    /* pool of flow ring buf */
++	uint32			flowring_num;
++
++	d2h_sync_cb_t d2h_sync_cb; /* Sync on D2H DMA done: SEQNUM or XORCSUM */
++	ulong d2h_sync_wait_max; /* max number of wait loops to receive one msg */
++	ulong d2h_sync_wait_tot; /* total wait loops */
++
++	dhd_dmaxfer_t	dmaxfer; /* for test/DMA loopback */
++
++	uint16		ioctl_seq_no;
++	uint16		data_seq_no;
++	uint16		ioctl_trans_id;
++	void		*pktid_ctrl_map; /* a pktid maps to a packet and its metadata */
++	void		*pktid_rx_map;	/* pktid map for rx path */
++	void		*pktid_tx_map;	/* pktid map for tx path */
++	void		*rx_lock;	/* rx pktid map and rings access protection */
++	bool		metadata_dbg;
++	void		*pktid_map_handle_ioctl;
++
++	/* Applications/utilities can read tx and rx metadata using IOVARs */
++	uint16		rx_metadata_offset;
++	uint16		tx_metadata_offset;
++
++
++#if defined(DHD_D2H_SOFT_DOORBELL_SUPPORT)
++	/* Host's soft doorbell configuration */
++	bcmpcie_soft_doorbell_t soft_doorbell[BCMPCIE_D2H_COMMON_MSGRINGS];
++#endif /* DHD_D2H_SOFT_DOORBELL_SUPPORT */
++
++	/* Work Queues to be used by the producer and the consumer, and threshold
++	 * when the WRITE index must be synced to consumer's workq
++	 */
++#if defined(DHD_LB_TXC)
++	uint32 tx_compl_prod_sync ____cacheline_aligned;
++	bcm_workq_t tx_compl_prod, tx_compl_cons;
++#endif /* DHD_LB_TXC */
++#if defined(DHD_LB_RXC)
++	uint32 rx_compl_prod_sync ____cacheline_aligned;
++	bcm_workq_t rx_compl_prod, rx_compl_cons;
++#endif /* DHD_LB_RXC */
++
++	dhd_dma_buf_t	fw_trap_buf; /* firmware trap buffer */
++
++    uint32  host_ipc_version; /* Host sypported IPC rev */
++	uint32  device_ipc_version; /* FW supported IPC rev */
++	uint32  active_ipc_version; /* Host advertised IPC rev */
++	dhd_dma_buf_t   hostts_req_buf; /* For holding host timestamp request buf */
++	bool    hostts_req_buf_inuse;
++	bool    rx_ts_log_enabled;
++	bool    tx_ts_log_enabled;
++} dhd_prot_t;
++
++extern void dhd_schedule_dmaxfer_free(dhd_pub_t* dhdp, dmaxref_mem_map_t *dmmap);
++
++static atomic_t dhd_msgbuf_rxbuf_post_event_bufs_running = ATOMIC_INIT(0);
++
++/* Convert a dmaaddr_t to a base_addr with htol operations */
++static INLINE void dhd_base_addr_htolpa(sh_addr_t *base_addr, dmaaddr_t pa);
++
++/* APIs for managing a DMA-able buffer */
++static int  dhd_dma_buf_audit(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf);
++static int  dhd_dma_buf_alloc(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf, uint32 buf_len);
++static void dhd_dma_buf_reset(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf);
++static void dhd_dma_buf_free(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf);
++
++/* msgbuf ring management */
++static int dhd_prot_ring_attach(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++	const char *name, uint16 max_items, uint16 len_item, uint16 ringid);
++static void dhd_prot_ring_init(dhd_pub_t *dhd, msgbuf_ring_t *ring);
++static void dhd_prot_ring_reset(dhd_pub_t *dhd, msgbuf_ring_t *ring);
++static void dhd_prot_ring_detach(dhd_pub_t *dhd, msgbuf_ring_t *ring);
++static void dhd_prot_process_fw_timestamp(dhd_pub_t *dhd, void* buf);
++
++/* Pool of pre-allocated msgbuf_ring_t with DMA-able buffers for Flowrings */
++static int  dhd_prot_flowrings_pool_attach(dhd_pub_t *dhd);
++static void dhd_prot_flowrings_pool_reset(dhd_pub_t *dhd);
++static void dhd_prot_flowrings_pool_detach(dhd_pub_t *dhd);
++
++/* Fetch and Release a flowring msgbuf_ring from flowring  pool */
++static msgbuf_ring_t *dhd_prot_flowrings_pool_fetch(dhd_pub_t *dhd,
++	uint16 flowid);
++/* see also dhd_prot_flowrings_pool_release() in dhd_prot.h */
++
++/* Producer: Allocate space in a msgbuf ring */
++static void* dhd_prot_alloc_ring_space(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++	uint16 nitems, uint16 *alloced, bool exactly_nitems);
++static void* dhd_prot_get_ring_space(msgbuf_ring_t *ring, uint16 nitems,
++	uint16 *alloced, bool exactly_nitems);
++
++/* Consumer: Determine the location where the next message may be consumed */
++static uint8* dhd_prot_get_read_addr(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++	uint32 *available_len);
++
++/* Producer (WR index update) or Consumer (RD index update) indication */
++static void dhd_prot_ring_write_complete(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++	void *p, uint16 len);
++static void dhd_prot_upd_read_idx(dhd_pub_t *dhd, msgbuf_ring_t *ring);
++
++static INLINE int dhd_prot_dma_indx_alloc(dhd_pub_t *dhd, uint8 type,
++	dhd_dma_buf_t *dma_buf, uint32 bufsz);
++
++/* Set/Get a RD or WR index in the array of indices */
++/* See also: dhd_prot_dma_indx_init() */
++void dhd_prot_dma_indx_set(dhd_pub_t *dhd, uint16 new_index, uint8 type,
++	uint16 ringid);
++static uint16 dhd_prot_dma_indx_get(dhd_pub_t *dhd, uint8 type, uint16 ringid);
++
++/* Locate a packet given a pktid */
++static INLINE void *dhd_prot_packet_get(dhd_pub_t *dhd, uint32 pktid, uint8 pkttype,
++	bool free_pktid);
++/* Locate a packet given a PktId and free it. */
++static INLINE void dhd_prot_packet_free(dhd_pub_t *dhd, void *pkt, uint8 pkttype, bool send);
++
++static int dhd_msgbuf_query_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd,
++	void *buf, uint len, uint8 action);
++static int dhd_msgbuf_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd,
++	void *buf, uint len, uint8 action);
++static int dhd_msgbuf_wait_ioctl_cmplt(dhd_pub_t *dhd, uint32 len, void *buf);
++static int dhd_fillup_ioct_reqst(dhd_pub_t *dhd, uint16 len, uint cmd,
++	void *buf, int ifidx);
++
++/* Post buffers for Rx, control ioctl response and events */
++static uint16 dhd_msgbuf_rxbuf_post_ctrlpath(dhd_pub_t *dhd, uint8 msgid, uint32 max_to_post);
++static void dhd_msgbuf_rxbuf_post_ioctlresp_bufs(dhd_pub_t *pub);
++static void dhd_msgbuf_rxbuf_post_event_bufs(dhd_pub_t *pub);
++static void dhd_msgbuf_rxbuf_post(dhd_pub_t *dhd, bool use_rsv_pktid);
++static int dhd_prot_rxbuf_post(dhd_pub_t *dhd, uint16 count, bool use_rsv_pktid);
++static int dhd_msgbuf_rxbuf_post_ts_bufs(dhd_pub_t *pub);
++
++static void dhd_prot_return_rxbuf(dhd_pub_t *dhd, uint32 pktid, uint32 rxcnt);
++
++
++/* D2H Message handling */
++static int dhd_prot_process_msgtype(dhd_pub_t *dhd, msgbuf_ring_t *ring, uint8 *buf, uint32 len);
++
++/* D2H Message handlers */
++static void dhd_prot_noop(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_txstatus_process(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_ioctcmplt_process(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_ioctack_process(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_ringstatus_process(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_genstatus_process(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_event_process(dhd_pub_t *dhd, void *msg);
++
++/* Loopback test with dongle */
++static void dmaxfer_free_dmaaddr(dhd_pub_t *dhd, dhd_dmaxfer_t *dma);
++static int dmaxfer_prepare_dmaaddr(dhd_pub_t *dhd, uint len, uint srcdelay,
++	uint destdelay, dhd_dmaxfer_t *dma);
++static void dhd_msgbuf_dmaxfer_process(dhd_pub_t *dhd, void *msg);
++
++/* Flowring management communication with dongle */
++static void dhd_prot_flow_ring_create_response_process(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_flow_ring_delete_response_process(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_flow_ring_flush_response_process(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_process_flow_ring_resume_response(dhd_pub_t *dhd, void* msg);
++static void dhd_prot_process_flow_ring_suspend_response(dhd_pub_t *dhd, void* msg);
++
++/* Monitor Mode */
++#ifdef WL_MONITOR
++extern bool dhd_monitor_enabled(dhd_pub_t *dhd, int ifidx);
++extern void dhd_rx_mon_pkt(dhd_pub_t *dhdp, host_rxbuf_cmpl_t* msg, void *pkt, int ifidx);
++#endif /* WL_MONITOR */
++
++/* Configure a soft doorbell per D2H ring */
++static void dhd_msgbuf_ring_config_d2h_soft_doorbell(dhd_pub_t *dhd);
++static void dhd_prot_process_d2h_ring_config_complete(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_process_d2h_ring_create_complete(dhd_pub_t *dhd, void *buf);
++static void dhd_prot_process_h2d_ring_create_complete(dhd_pub_t *dhd, void *buf);
++static void dhd_prot_process_d2h_mb_data(dhd_pub_t *dhd, void* buf);
++static void dhd_prot_process_infobuf_complete(dhd_pub_t *dhd, void* buf);
++static void dhd_prot_detach_info_rings(dhd_pub_t *dhd);
++static void dhd_prot_process_d2h_host_ts_complete(dhd_pub_t *dhd, void* buf);
++
++typedef void (*dhd_msgbuf_func_t)(dhd_pub_t *dhd, void *msg);
++
++/** callback functions for messages generated by the dongle */
++#define MSG_TYPE_INVALID 0
++
++static dhd_msgbuf_func_t table_lookup[DHD_PROT_FUNCS] = {
++	dhd_prot_noop, /* 0 is MSG_TYPE_INVALID */
++	dhd_prot_genstatus_process, /* MSG_TYPE_GEN_STATUS */
++	dhd_prot_ringstatus_process, /* MSG_TYPE_RING_STATUS */
++	NULL,
++	dhd_prot_flow_ring_create_response_process, /* MSG_TYPE_FLOW_RING_CREATE_CMPLT */
++	NULL,
++	dhd_prot_flow_ring_delete_response_process, /* MSG_TYPE_FLOW_RING_DELETE_CMPLT */
++	NULL,
++	dhd_prot_flow_ring_flush_response_process, /* MSG_TYPE_FLOW_RING_FLUSH_CMPLT */
++	NULL,
++	dhd_prot_ioctack_process, /* MSG_TYPE_IOCTLPTR_REQ_ACK */
++	NULL,
++	dhd_prot_ioctcmplt_process, /* MSG_TYPE_IOCTL_CMPLT */
++	NULL,
++	dhd_prot_event_process, /* MSG_TYPE_WL_EVENT */
++	NULL,
++	dhd_prot_txstatus_process, /* MSG_TYPE_TX_STATUS */
++	NULL,
++	NULL,	/* MSG_TYPE_RX_CMPLT use dedicated handler */
++	NULL,
++	dhd_msgbuf_dmaxfer_process, /* MSG_TYPE_LPBK_DMAXFER_CMPLT */
++	NULL, /* MSG_TYPE_FLOW_RING_RESUME */
++	dhd_prot_process_flow_ring_resume_response, /* MSG_TYPE_FLOW_RING_RESUME_CMPLT */
++	NULL, /* MSG_TYPE_FLOW_RING_SUSPEND */
++	dhd_prot_process_flow_ring_suspend_response, /* MSG_TYPE_FLOW_RING_SUSPEND_CMPLT */
++	NULL, /* MSG_TYPE_INFO_BUF_POST */
++	dhd_prot_process_infobuf_complete, /* MSG_TYPE_INFO_BUF_CMPLT */
++	NULL, /* MSG_TYPE_H2D_RING_CREATE */
++	NULL, /* MSG_TYPE_D2H_RING_CREATE */
++	dhd_prot_process_h2d_ring_create_complete, /* MSG_TYPE_H2D_RING_CREATE_CMPLT */
++	dhd_prot_process_d2h_ring_create_complete, /* MSG_TYPE_D2H_RING_CREATE_CMPLT */
++	NULL, /* MSG_TYPE_H2D_RING_CONFIG */
++	NULL, /* MSG_TYPE_D2H_RING_CONFIG */
++	NULL, /* MSG_TYPE_H2D_RING_CONFIG_CMPLT */
++	dhd_prot_process_d2h_ring_config_complete, /* MSG_TYPE_D2H_RING_CONFIG_CMPLT */
++	NULL, /* MSG_TYPE_H2D_MAILBOX_DATA */
++	dhd_prot_process_d2h_mb_data, /* MSG_TYPE_D2H_MAILBOX_DATA */
++	NULL,	/* MSG_TYPE_TIMSTAMP_BUFPOST */
++	NULL,	/* MSG_TYPE_HOSTTIMSTAMP */
++	dhd_prot_process_d2h_host_ts_complete,	/* MSG_TYPE_HOSTTIMSTAMP_CMPLT */
++	dhd_prot_process_fw_timestamp,	/* MSG_TYPE_FIRMWARE_TIMESTAMP */
++};
++
++
++#ifdef DHD_RX_CHAINING
++
++#define PKT_CTF_CHAINABLE(dhd, ifidx, evh, prio, h_sa, h_da, h_prio) \
++	(dhd_wet_chainable(dhd) && \
++	dhd_rx_pkt_chainable((dhd), (ifidx)) && \
++	!ETHER_ISNULLDEST(((struct ether_header *)(evh))->ether_dhost) && \
++	!ETHER_ISMULTI(((struct ether_header *)(evh))->ether_dhost) && \
++	!eacmp((h_da), ((struct ether_header *)(evh))->ether_dhost) && \
++	!eacmp((h_sa), ((struct ether_header *)(evh))->ether_shost) && \
++	((h_prio) == (prio)) && (dhd_ctf_hotbrc_check((dhd), (evh), (ifidx))) && \
++	((((struct ether_header *)(evh))->ether_type == HTON16(ETHER_TYPE_IP)) || \
++	(((struct ether_header *)(evh))->ether_type == HTON16(ETHER_TYPE_IPV6))))
++
++static INLINE void BCMFASTPATH dhd_rxchain_reset(rxchain_info_t *rxchain);
++static void BCMFASTPATH dhd_rxchain_frame(dhd_pub_t *dhd, void *pkt, uint ifidx);
++static void BCMFASTPATH dhd_rxchain_commit(dhd_pub_t *dhd);
++
++#define DHD_PKT_CTF_MAX_CHAIN_LEN	64
++
++#endif /* DHD_RX_CHAINING */
++
++static void dhd_prot_h2d_sync_init(dhd_pub_t *dhd);
++
++/**
++ * D2H DMA to completion callback handlers. Based on the mode advertised by the
++ * dongle through the PCIE shared region, the appropriate callback will be
++ * registered in the proto layer to be invoked prior to precessing any message
++ * from a D2H DMA ring. If the dongle uses a read barrier or another mode that
++ * does not require host participation, then a noop callback handler will be
++ * bound that simply returns the msg_type.
++ */
++static void dhd_prot_d2h_sync_livelock(dhd_pub_t *dhd, uint32 msg_seqnum, msgbuf_ring_t *ring,
++                                       uint32 tries, volatile uchar *msg, int msglen);
++static uint8 dhd_prot_d2h_sync_seqnum(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++                                      volatile cmn_msg_hdr_t *msg, int msglen);
++static uint8 dhd_prot_d2h_sync_xorcsum(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++                                       volatile cmn_msg_hdr_t *msg, int msglen);
++static uint8 dhd_prot_d2h_sync_none(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++                                    volatile cmn_msg_hdr_t *msg, int msglen);
++static void dhd_prot_d2h_sync_init(dhd_pub_t *dhd);
++static int dhd_send_d2h_ringcreate(dhd_pub_t *dhd, msgbuf_ring_t *ring_to_create);
++static int dhd_send_h2d_ringcreate(dhd_pub_t *dhd, msgbuf_ring_t *ring_to_create);
++static uint16 dhd_get_max_flow_rings(dhd_pub_t *dhd);
++
++bool
++dhd_prot_is_cmpl_ring_empty(dhd_pub_t *dhd, void *prot_info)
++{
++	msgbuf_ring_t *flow_ring = (msgbuf_ring_t *)prot_info;
++	uint16 rd, wr;
++	bool ret;
++
++	if (dhd->dma_d2h_ring_upd_support) {
++		wr = flow_ring->wr;
++	} else {
++		dhd_bus_cmn_readshared(dhd->bus, &wr, RING_WR_UPD, flow_ring->idx);
++	}
++	if (dhd->dma_h2d_ring_upd_support) {
++		rd = flow_ring->rd;
++	} else {
++		dhd_bus_cmn_readshared(dhd->bus, &rd, RING_RD_UPD, flow_ring->idx);
++	}
++	ret = (wr == rd) ? TRUE : FALSE;
++	return ret;
++}
++uint16
++dhd_prot_get_h2d_max_txpost(dhd_pub_t *dhd)
++{
++	return (uint16)h2d_max_txpost;
++}
++void
++dhd_prot_set_h2d_max_txpost(dhd_pub_t *dhd, uint16 max_txpost)
++{
++	h2d_max_txpost = max_txpost;
++}
++/**
++ * dhd_prot_d2h_sync_livelock - when the host determines that a DMA transfer has
++ * not completed, a livelock condition occurs. Host will avert this livelock by
++ * dropping this message and moving to the next. This dropped message can lead
++ * to a packet leak, or even something disastrous in the case the dropped
++ * message happens to be a control response.
++ * Here we will log this condition. One may choose to reboot the dongle.
++ *
++ */
++static void
++dhd_prot_d2h_sync_livelock(dhd_pub_t *dhd, uint32 msg_seqnum, msgbuf_ring_t *ring, uint32 tries,
++                           volatile uchar *msg, int msglen)
++{
++	uint32 ring_seqnum = ring->seqnum;
++	DHD_ERROR((
++		"LIVELOCK DHD<%p> ring<%s> msg_seqnum<%u> ring_seqnum<%u:%u> tries<%u> max<%lu>"
++		" tot<%lu> dma_buf va<%p> msg<%p> curr_rd<%d>\n",
++		dhd, ring->name, msg_seqnum, ring_seqnum, ring_seqnum% D2H_EPOCH_MODULO, tries,
++		dhd->prot->d2h_sync_wait_max, dhd->prot->d2h_sync_wait_tot,
++		ring->dma_buf.va, msg, ring->curr_rd));
++	prhex("D2H MsgBuf Failure", (volatile uchar *)msg, msglen);
++
++	dhd_bus_dump_console_buffer(dhd->bus);
++	dhd_prot_debug_info_print(dhd);
++
++#ifdef DHD_FW_COREDUMP
++	if (dhd->memdump_enabled) {
++		/* collect core dump */
++		dhd->memdump_type = DUMP_TYPE_BY_LIVELOCK;
++		dhd_bus_mem_dump(dhd);
++	}
++#endif /* DHD_FW_COREDUMP */
++
++	dhd_schedule_reset(dhd);
++
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#ifdef CONFIG_ARCH_MSM
++	dhd->bus->no_cfg_restore = 1;
++#endif /* CONFIG_ARCH_MSM */
++	dhd->hang_reason = HANG_REASON_MSGBUF_LIVELOCK;
++	dhd_os_send_hang_message(dhd);
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++}
++
++/**
++ * dhd_prot_d2h_sync_seqnum - Sync on a D2H DMA completion using the SEQNUM
++ * mode. Sequence number is always in the last word of a message.
++ */
++static uint8 BCMFASTPATH
++dhd_prot_d2h_sync_seqnum(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++                         volatile cmn_msg_hdr_t *msg, int msglen)
++{
++	uint32 tries;
++	uint32 ring_seqnum = ring->seqnum % D2H_EPOCH_MODULO;
++	int num_words = msglen / sizeof(uint32); /* num of 32bit words */
++	volatile uint32 *marker = (volatile uint32 *)msg + (num_words - 1); /* last word */
++	dhd_prot_t *prot = dhd->prot;
++	uint32 msg_seqnum;
++	uint32 step = 0;
++	uint32 delay = PCIE_D2H_SYNC_DELAY;
++	uint32 total_tries = 0;
++
++	ASSERT(msglen == ring->item_len);
++
++	BCM_REFERENCE(delay);
++	/*
++	 * For retries we have to make some sort of stepper algorithm.
++	 * We see that every time when the Dongle comes out of the D3
++	 * Cold state, the first D2H mem2mem DMA takes more time to
++	 * complete, leading to livelock issues.
++	 *
++	 * Case 1 - Apart from Host CPU some other bus master is
++	 * accessing the DDR port, probably page close to the ring
++	 * so, PCIE does not get a change to update the memory.
++	 * Solution - Increase the number of tries.
++	 *
++	 * Case 2 - The 50usec delay given by the Host CPU is not
++	 * sufficient for the PCIe RC to start its work.
++	 * In this case the breathing time of 50usec given by
++	 * the Host CPU is not sufficient.
++	 * Solution: Increase the delay in a stepper fashion.
++	 * This is done to ensure that there are no
++	 * unwanted extra delay introdcued in normal conditions.
++	 */
++	for (step = 1; step <= PCIE_D2H_SYNC_NUM_OF_STEPS; step++) {
++		for (tries = 0; tries < PCIE_D2H_SYNC_WAIT_TRIES; tries++) {
++			msg_seqnum = *marker;
++			if (ltoh32(msg_seqnum) == ring_seqnum) { /* dma upto last word done */
++				ring->seqnum++; /* next expected sequence number */
++				goto dma_completed;
++			}
++
++			total_tries = ((step-1) * PCIE_D2H_SYNC_WAIT_TRIES) + tries;
++
++			if (total_tries > prot->d2h_sync_wait_max)
++				prot->d2h_sync_wait_max = total_tries;
++
++			OSL_CACHE_INV(msg, msglen); /* invalidate and try again */
++			OSL_CPU_RELAX(); /* CPU relax for msg_seqnum  value to update */
++			OSL_DELAY(delay * step); /* Add stepper delay */
++
++		} /* for PCIE_D2H_SYNC_WAIT_TRIES */
++	} /* for PCIE_D2H_SYNC_NUM_OF_STEPS */
++
++	dhd_prot_d2h_sync_livelock(dhd, msg_seqnum, ring, total_tries,
++		(volatile uchar *) msg, msglen);
++
++	ring->seqnum++; /* skip this message ... leak of a pktid */
++	return MSG_TYPE_INVALID; /* invalid msg_type 0 -> noop callback */
++
++dma_completed:
++
++	prot->d2h_sync_wait_tot += tries;
++	return msg->msg_type;
++}
++
++/**
++ * dhd_prot_d2h_sync_xorcsum - Sync on a D2H DMA completion using the XORCSUM
++ * mode. The xorcsum is placed in the last word of a message. Dongle will also
++ * place a seqnum in the epoch field of the cmn_msg_hdr.
++ */
++static uint8 BCMFASTPATH
++dhd_prot_d2h_sync_xorcsum(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++                          volatile cmn_msg_hdr_t *msg, int msglen)
++{
++	uint32 tries;
++	uint32 prot_checksum = 0; /* computed checksum */
++	int num_words = msglen / sizeof(uint32); /* num of 32bit words */
++	uint8 ring_seqnum = ring->seqnum % D2H_EPOCH_MODULO;
++	dhd_prot_t *prot = dhd->prot;
++	uint32 step = 0;
++	uint32 delay = PCIE_D2H_SYNC_DELAY;
++	uint32 total_tries = 0;
++
++	ASSERT(msglen == ring->item_len);
++
++	BCM_REFERENCE(delay);
++	/*
++	 * For retries we have to make some sort of stepper algorithm.
++	 * We see that every time when the Dongle comes out of the D3
++	 * Cold state, the first D2H mem2mem DMA takes more time to
++	 * complete, leading to livelock issues.
++	 *
++	 * Case 1 - Apart from Host CPU some other bus master is
++	 * accessing the DDR port, probably page close to the ring
++	 * so, PCIE does not get a change to update the memory.
++	 * Solution - Increase the number of tries.
++	 *
++	 * Case 2 - The 50usec delay given by the Host CPU is not
++	 * sufficient for the PCIe RC to start its work.
++	 * In this case the breathing time of 50usec given by
++	 * the Host CPU is not sufficient.
++	 * Solution: Increase the delay in a stepper fashion.
++	 * This is done to ensure that there are no
++	 * unwanted extra delay introdcued in normal conditions.
++	 */
++	for (step = 1; step <= PCIE_D2H_SYNC_NUM_OF_STEPS; step++) {
++		for (tries = 0; tries < PCIE_D2H_SYNC_WAIT_TRIES; tries++) {
++			prot_checksum = bcm_compute_xor32((volatile uint32 *)msg, num_words);
++			if (prot_checksum == 0U) { /* checksum is OK */
++				if (msg->epoch == ring_seqnum) {
++					ring->seqnum++; /* next expected sequence number */
++					goto dma_completed;
++				}
++			}
++
++			total_tries = ((step-1) * PCIE_D2H_SYNC_WAIT_TRIES) + tries;
++
++			if (total_tries > prot->d2h_sync_wait_max)
++				prot->d2h_sync_wait_max = total_tries;
++
++			OSL_CACHE_INV(msg, msglen); /* invalidate and try again */
++			OSL_CPU_RELAX(); /* CPU relax for msg_seqnum  value to update */
++			OSL_DELAY(delay * step); /* Add stepper delay */
++
++		} /* for PCIE_D2H_SYNC_WAIT_TRIES */
++	} /* for PCIE_D2H_SYNC_NUM_OF_STEPS */
++
++	DHD_ERROR(("%s: prot_checksum = 0x%x\n", __FUNCTION__, prot_checksum));
++	dhd_prot_d2h_sync_livelock(dhd, msg->epoch, ring, total_tries,
++		(volatile uchar *) msg, msglen);
++
++	ring->seqnum++; /* skip this message ... leak of a pktid */
++	return MSG_TYPE_INVALID; /* invalid msg_type 0 -> noop callback */
++
++dma_completed:
++
++	prot->d2h_sync_wait_tot += tries;
++	return msg->msg_type;
++}
++
++/**
++ * dhd_prot_d2h_sync_none - Dongle ensure that the DMA will complete and host
++ * need to try to sync. This noop sync handler will be bound when the dongle
++ * advertises that neither the SEQNUM nor XORCSUM mode of DMA sync is required.
++ */
++static uint8 BCMFASTPATH
++dhd_prot_d2h_sync_none(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++                       volatile cmn_msg_hdr_t *msg, int msglen)
++{
++	return msg->msg_type;
++}
++
++INLINE void
++dhd_wakeup_ioctl_event(dhd_pub_t *dhd, dhd_ioctl_recieved_status_t reason)
++{
++	/* To synchronize with the previous memory operations call wmb() */
++	OSL_SMP_WMB();
++	dhd->prot->ioctl_received = reason;
++	/* Call another wmb() to make sure before waking up the other event value gets updated */
++	OSL_SMP_WMB();
++	dhd_os_ioctl_resp_wake(dhd);
++}
++
++/**
++ * dhd_prot_d2h_sync_init - Setup the host side DMA sync mode based on what
++ * dongle advertizes.
++ */
++static void
++dhd_prot_d2h_sync_init(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	prot->d2h_sync_wait_max = 0UL;
++	prot->d2h_sync_wait_tot = 0UL;
++
++	prot->d2hring_ctrl_cpln.seqnum = D2H_EPOCH_INIT_VAL;
++	prot->d2hring_ctrl_cpln.current_phase = BCMPCIE_CMNHDR_PHASE_BIT_INIT;
++
++	prot->d2hring_tx_cpln.seqnum = D2H_EPOCH_INIT_VAL;
++	prot->d2hring_tx_cpln.current_phase = BCMPCIE_CMNHDR_PHASE_BIT_INIT;
++
++	prot->d2hring_rx_cpln.seqnum = D2H_EPOCH_INIT_VAL;
++	prot->d2hring_rx_cpln.current_phase = BCMPCIE_CMNHDR_PHASE_BIT_INIT;
++
++	if (dhd->d2h_sync_mode & PCIE_SHARED_D2H_SYNC_SEQNUM) {
++		prot->d2h_sync_cb = dhd_prot_d2h_sync_seqnum;
++		DHD_ERROR(("%s(): D2H sync mechanism is SEQNUM \r\n", __FUNCTION__));
++	} else if (dhd->d2h_sync_mode & PCIE_SHARED_D2H_SYNC_XORCSUM) {
++		prot->d2h_sync_cb = dhd_prot_d2h_sync_xorcsum;
++		DHD_ERROR(("%s(): D2H sync mechanism is XORCSUM \r\n", __FUNCTION__));
++	} else {
++		prot->d2h_sync_cb = dhd_prot_d2h_sync_none;
++		DHD_ERROR(("%s(): D2H sync mechanism is NONE \r\n", __FUNCTION__));
++	}
++}
++
++/**
++ * dhd_prot_h2d_sync_init - Per H2D common ring, setup the msgbuf ring seqnum
++ */
++static void
++dhd_prot_h2d_sync_init(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	prot->h2dring_rxp_subn.seqnum = H2D_EPOCH_INIT_VAL;
++	prot->h2dring_rxp_subn.current_phase = 0;
++
++	prot->h2dring_ctrl_subn.seqnum = H2D_EPOCH_INIT_VAL;
++	prot->h2dring_ctrl_subn.current_phase = 0;
++}
++
++/* +-----------------  End of PCIE DHD H2D DMA SYNC ------------------------+ */
++
++
++/*
++ * +---------------------------------------------------------------------------+
++ * PCIE DMA-able buffer. Sets up a dhd_dma_buf_t object, which includes the
++ * virtual and physical address, the buffer lenght and the DMA handler.
++ * A secdma handler is also included in the dhd_dma_buf object.
++ * +---------------------------------------------------------------------------+
++ */
++
++static INLINE void
++dhd_base_addr_htolpa(sh_addr_t *base_addr, dmaaddr_t pa)
++{
++	base_addr->low_addr = htol32(PHYSADDRLO(pa));
++	base_addr->high_addr = htol32(PHYSADDRHI(pa));
++}
++
++
++/**
++ * dhd_dma_buf_audit - Any audits on a DHD DMA Buffer.
++ */
++static int
++dhd_dma_buf_audit(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf)
++{
++	uint32 pa_lowaddr, end; /* dongle uses 32bit ptr arithmetic */
++	ASSERT(dma_buf);
++	pa_lowaddr = PHYSADDRLO(dma_buf->pa);
++	ASSERT(PHYSADDRLO(dma_buf->pa) || PHYSADDRHI(dma_buf->pa));
++	ASSERT(ISALIGNED(pa_lowaddr, DMA_ALIGN_LEN));
++	ASSERT(dma_buf->len != 0);
++
++	/* test 32bit offset arithmetic over dma buffer for loss of carry-over */
++	end = (pa_lowaddr + dma_buf->len); /* end address */
++
++	if ((end & 0xFFFFFFFF) < (pa_lowaddr & 0xFFFFFFFF)) { /* exclude carryover */
++		DHD_ERROR(("%s: dma_buf %x len %d spans dongle 32bit ptr arithmetic\n",
++			__FUNCTION__, pa_lowaddr, dma_buf->len));
++		return BCME_ERROR;
++	}
++
++	return BCME_OK;
++}
++
++/**
++ * dhd_dma_buf_alloc - Allocate a cache coherent DMA-able buffer.
++ * returns BCME_OK=0 on success
++ * returns non-zero negative error value on failure.
++ */
++static int
++dhd_dma_buf_alloc(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf, uint32 buf_len)
++{
++	uint32 dma_pad = 0;
++	osl_t *osh = dhd->osh;
++	uint16 dma_align = DMA_ALIGN_LEN;
++
++
++	ASSERT(dma_buf != NULL);
++	ASSERT(dma_buf->va == NULL);
++	ASSERT(dma_buf->len == 0);
++
++	/* Pad the buffer length by one extra cacheline size.
++	 * Required for D2H direction.
++	 */
++	dma_pad = (buf_len % DHD_DMA_PAD) ? DHD_DMA_PAD : 0;
++	dma_buf->va = DMA_ALLOC_CONSISTENT(osh, buf_len + dma_pad,
++		dma_align, &dma_buf->_alloced, &dma_buf->pa, &dma_buf->dmah);
++
++	if (dma_buf->va == NULL) {
++		DHD_ERROR(("%s: buf_len %d, no memory available\n",
++			__FUNCTION__, buf_len));
++		return BCME_NOMEM;
++	}
++
++	dma_buf->len = buf_len; /* not including padded len */
++
++	if (dhd_dma_buf_audit(dhd, dma_buf) != BCME_OK) { /* audit dma buf */
++		dhd_dma_buf_free(dhd, dma_buf);
++		return BCME_ERROR;
++	}
++
++	dhd_dma_buf_reset(dhd, dma_buf); /* zero out and cache flush */
++
++	return BCME_OK;
++}
++
++/**
++ * dhd_dma_buf_reset - Reset a cache coherent DMA-able buffer.
++ */
++static void
++dhd_dma_buf_reset(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf)
++{
++	if ((dma_buf == NULL) || (dma_buf->va == NULL))
++		return;
++
++	(void)dhd_dma_buf_audit(dhd, dma_buf);
++
++	/* Zero out the entire buffer and cache flush */
++	memset((void*)dma_buf->va, 0, dma_buf->len);
++	OSL_CACHE_FLUSH((void *)dma_buf->va, dma_buf->len);
++}
++
++/**
++ * dhd_dma_buf_free - Free a DMA-able buffer that was previously allocated using
++ * dhd_dma_buf_alloc().
++ */
++static void
++dhd_dma_buf_free(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf)
++{
++	osl_t *osh = dhd->osh;
++
++	ASSERT(dma_buf);
++
++	if (dma_buf->va == NULL)
++		return; /* Allow for free invocation, when alloc failed */
++
++	/* DEBUG: dhd_dma_buf_reset(dhd, dma_buf) */
++	(void)dhd_dma_buf_audit(dhd, dma_buf);
++
++	/* dma buffer may have been padded at allocation */
++	DMA_FREE_CONSISTENT(osh, dma_buf->va, dma_buf->_alloced,
++		dma_buf->pa, dma_buf->dmah);
++
++	memset(dma_buf, 0, sizeof(dhd_dma_buf_t));
++}
++
++/**
++ * dhd_dma_buf_init - Initialize a dhd_dma_buf with speicifed values.
++ * Do not use dhd_dma_buf_init to zero out a dhd_dma_buf_t object. Use memset 0.
++ */
++void
++dhd_dma_buf_init(dhd_pub_t *dhd, void *dhd_dma_buf,
++	void *va, uint32 len, dmaaddr_t pa, void *dmah, void *secdma)
++{
++	dhd_dma_buf_t *dma_buf;
++	ASSERT(dhd_dma_buf);
++	dma_buf = (dhd_dma_buf_t *)dhd_dma_buf;
++	dma_buf->va = va;
++	dma_buf->len = len;
++	dma_buf->pa = pa;
++	dma_buf->dmah = dmah;
++	dma_buf->secdma = secdma;
++
++	/* Audit user defined configuration */
++	(void)dhd_dma_buf_audit(dhd, dma_buf);
++}
++
++/* +------------------  End of PCIE DHD DMA BUF ADT ------------------------+ */
++
++/*
++ * +---------------------------------------------------------------------------+
++ * PktId Map: Provides a native packet pointer to unique 32bit PktId mapping.
++ * Main purpose is to save memory on the dongle, has other purposes as well.
++ * The packet id map, also includes storage for some packet parameters that
++ * may be saved. A native packet pointer along with the parameters may be saved
++ * and a unique 32bit pkt id will be returned. Later, the saved packet pointer
++ * and the metadata may be retrieved using the previously allocated packet id.
++ * +---------------------------------------------------------------------------+
++ */
++#define DHD_PCIE_PKTID
++#define MAX_CTRL_PKTID		(1024) /* Maximum number of pktids supported */
++#define MAX_RX_PKTID		(1024)
++#define MAX_TX_PKTID		(3072 * 2)
++
++/* On Router, the pktptr serves as a pktid. */
++
++
++#if defined(PROP_TXSTATUS) && !defined(DHD_PCIE_PKTID)
++#error "PKTIDMAP must be supported with PROP_TXSTATUS/WLFC"
++#endif
++
++/* Enum for marking the buffer color based on usage */
++typedef enum dhd_pkttype {
++	PKTTYPE_DATA_TX = 0,
++	PKTTYPE_DATA_RX,
++	PKTTYPE_IOCTL_RX,
++	PKTTYPE_EVENT_RX,
++	PKTTYPE_INFO_RX,
++	/* dhd_prot_pkt_free no check, if pktid reserved and no space avail case */
++	PKTTYPE_NO_CHECK,
++	PKTTYPE_TSBUF_RX
++} dhd_pkttype_t;
++
++#define DHD_PKTID_INVALID               (0U)
++#define DHD_IOCTL_REQ_PKTID             (0xFFFE)
++#define DHD_FAKE_PKTID                  (0xFACE)
++#define DHD_H2D_DBGRING_REQ_PKTID	0xFFFD
++#define DHD_D2H_DBGRING_REQ_PKTID	0xFFFC
++#define DHD_H2D_HOSTTS_REQ_PKTID	0xFFFB
++
++#define IS_FLOWRING(ring) \
++	((strncmp(ring->name, "h2dflr", sizeof("h2dflr"))) == (0))
++
++typedef void * dhd_pktid_map_handle_t; /* opaque handle to a pktid map */
++
++/* Construct a packet id mapping table, returning an opaque map handle */
++static dhd_pktid_map_handle_t *dhd_pktid_map_init(dhd_pub_t *dhd, uint32 num_items);
++
++/* Destroy a packet id mapping table, freeing all packets active in the table */
++static void dhd_pktid_map_fini(dhd_pub_t *dhd, dhd_pktid_map_handle_t *map);
++
++#define DHD_NATIVE_TO_PKTID_INIT(dhd, items) dhd_pktid_map_init((dhd), (items))
++#define DHD_NATIVE_TO_PKTID_RESET(dhd, map)  dhd_pktid_map_reset((dhd), (map))
++#define DHD_NATIVE_TO_PKTID_FINI(dhd, map)   dhd_pktid_map_fini((dhd), (map))
++#define DHD_NATIVE_TO_PKTID_FINI_IOCTL(osh, map)  dhd_pktid_map_fini_ioctl((osh), (map))
++
++#ifdef MACOSX_DHD
++#undef DHD_PCIE_PKTID
++#define DHD_PCIE_PKTID 1
++#endif /* MACOSX_DHD */
++
++#if defined(DHD_PCIE_PKTID)
++#if defined(MACOSX_DHD) || defined(DHD_EFI)
++#define IOCTLRESP_USE_CONSTMEM
++static void free_ioctl_return_buffer(dhd_pub_t *dhd, dhd_dma_buf_t *retbuf);
++static int  alloc_ioctl_return_buffer(dhd_pub_t *dhd, dhd_dma_buf_t *retbuf);
++#endif 
++
++/* Determine number of pktids that are available */
++static INLINE uint32 dhd_pktid_map_avail_cnt(dhd_pktid_map_handle_t *handle);
++
++/* Allocate a unique pktid against which a pkt and some metadata is saved */
++static INLINE uint32 dhd_pktid_map_reserve(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle,
++	void *pkt, dhd_pkttype_t pkttype);
++static INLINE void dhd_pktid_map_save(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle,
++	void *pkt, uint32 nkey, dmaaddr_t pa, uint32 len, uint8 dma,
++	void *dmah, void *secdma, dhd_pkttype_t pkttype);
++static uint32 dhd_pktid_map_alloc(dhd_pub_t *dhd, dhd_pktid_map_handle_t *map,
++	void *pkt, dmaaddr_t pa, uint32 len, uint8 dma,
++	void *dmah, void *secdma, dhd_pkttype_t pkttype);
++
++/* Return an allocated pktid, retrieving previously saved pkt and metadata */
++static void *dhd_pktid_map_free(dhd_pub_t *dhd, dhd_pktid_map_handle_t *map,
++	uint32 id, dmaaddr_t *pa, uint32 *len, void **dmah,
++	void **secdma, dhd_pkttype_t pkttype, bool rsv_locker);
++
++/*
++ * DHD_PKTID_AUDIT_ENABLED: Audit of PktIds in DHD for duplicate alloc and frees
++ *
++ * DHD_PKTID_AUDIT_MAP: Audit the LIFO or FIFO PktIdMap allocator
++ * DHD_PKTID_AUDIT_RING: Audit the pktid during producer/consumer ring operation
++ *
++ * CAUTION: When DHD_PKTID_AUDIT_ENABLED is defined,
++ *    either DHD_PKTID_AUDIT_MAP or DHD_PKTID_AUDIT_RING may be selected.
++ */
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++#define USE_DHD_PKTID_AUDIT_LOCK 1
++/* Audit the pktidmap allocator */
++/* #define DHD_PKTID_AUDIT_MAP */
++
++/* Audit the pktid during production/consumption of workitems */
++#define DHD_PKTID_AUDIT_RING
++
++#if defined(DHD_PKTID_AUDIT_MAP) && defined(DHD_PKTID_AUDIT_RING)
++#error "May only enabled audit of MAP or RING, at a time."
++#endif /* DHD_PKTID_AUDIT_MAP && DHD_PKTID_AUDIT_RING */
++
++#define DHD_DUPLICATE_ALLOC     1
++#define DHD_DUPLICATE_FREE      2
++#define DHD_TEST_IS_ALLOC       3
++#define DHD_TEST_IS_FREE        4
++
++#ifdef USE_DHD_PKTID_AUDIT_LOCK
++#define DHD_PKTID_AUDIT_LOCK_INIT(osh)          dhd_os_spin_lock_init(osh)
++#define DHD_PKTID_AUDIT_LOCK_DEINIT(osh, lock)  dhd_os_spin_lock_deinit(osh, lock)
++#define DHD_PKTID_AUDIT_LOCK(lock)              dhd_os_spin_lock(lock)
++#define DHD_PKTID_AUDIT_UNLOCK(lock, flags)     dhd_os_spin_unlock(lock, flags)
++#else
++#define DHD_PKTID_AUDIT_LOCK_INIT(osh)          (void *)(1)
++#define DHD_PKTID_AUDIT_LOCK_DEINIT(osh, lock)  do { /* noop */ } while (0)
++#define DHD_PKTID_AUDIT_LOCK(lock)              0
++#define DHD_PKTID_AUDIT_UNLOCK(lock, flags)     do { /* noop */ } while (0)
++#endif /* !USE_DHD_PKTID_AUDIT_LOCK */
++
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++/* #define USE_DHD_PKTID_LOCK   1 */
++
++#ifdef USE_DHD_PKTID_LOCK
++#define DHD_PKTID_LOCK_INIT(osh)                dhd_os_spin_lock_init(osh)
++#define DHD_PKTID_LOCK_DEINIT(osh, lock)        dhd_os_spin_lock_deinit(osh, lock)
++#define DHD_PKTID_LOCK(lock)                    dhd_os_spin_lock(lock)
++#define DHD_PKTID_UNLOCK(lock, flags)           dhd_os_spin_unlock(lock, flags)
++#else
++#define DHD_PKTID_LOCK_INIT(osh)                (void *)(1)
++#define DHD_PKTID_LOCK_DEINIT(osh, lock)	\
++	do { \
++		BCM_REFERENCE(osh); \
++		BCM_REFERENCE(lock); \
++	} while (0)
++#define DHD_PKTID_LOCK(lock)                    0
++#define DHD_PKTID_UNLOCK(lock, flags)           \
++	do { \
++		BCM_REFERENCE(lock); \
++		BCM_REFERENCE(flags); \
++	} while (0)
++#endif /* !USE_DHD_PKTID_LOCK */
++
++typedef enum dhd_locker_state {
++	LOCKER_IS_FREE,
++	LOCKER_IS_BUSY,
++	LOCKER_IS_RSVD
++} dhd_locker_state_t;
++
++/* Packet metadata saved in packet id mapper */
++
++typedef struct dhd_pktid_item {
++	dhd_locker_state_t state;  /* tag a locker to be free, busy or reserved */
++	uint8       dir;      /* dma map direction (Tx=flush or Rx=invalidate) */
++	dhd_pkttype_t pkttype; /* pktlists are maintained based on pkttype */
++	uint16      len;      /* length of mapped packet's buffer */
++	void        *pkt;     /* opaque native pointer to a packet */
++	dmaaddr_t   pa;       /* physical address of mapped packet's buffer */
++	void        *dmah;    /* handle to OS specific DMA map */
++	void		*secdma;
++} dhd_pktid_item_t;
++
++typedef uint32 dhd_pktid_key_t;
++
++typedef struct dhd_pktid_map {
++	uint32      items;    /* total items in map */
++	uint32      avail;    /* total available items */
++	int         failures; /* lockers unavailable count */
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++	void		*pktid_audit_lock;
++	struct bcm_mwbmap *pktid_audit; /* multi word bitmap based audit */
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++	dhd_pktid_key_t	*keys; /* map_items +1 unique pkt ids */
++	dhd_pktid_item_t lockers[0];           /* metadata storage */
++} dhd_pktid_map_t;
++
++/*
++ * PktId (Locker) #0 is never allocated and is considered invalid.
++ *
++ * On request for a pktid, a value DHD_PKTID_INVALID must be treated as a
++ * depleted pktid pool and must not be used by the caller.
++ *
++ * Likewise, a caller must never free a pktid of value DHD_PKTID_INVALID.
++ */
++
++#define DHD_PKTID_FREE_LOCKER           (FALSE)
++#define DHD_PKTID_RSV_LOCKER            (TRUE)
++
++#define DHD_PKTID_ITEM_SZ               (sizeof(dhd_pktid_item_t))
++#define DHD_PKIDMAP_ITEMS(items)        (items)
++#define DHD_PKTID_MAP_SZ(items)         (sizeof(dhd_pktid_map_t) + \
++	                                     (DHD_PKTID_ITEM_SZ * ((items) + 1)))
++#define DHD_PKTIDMAP_KEYS_SZ(items)     (sizeof(dhd_pktid_key_t) * ((items) + 1))
++
++#define DHD_NATIVE_TO_PKTID_RESET_IOCTL(dhd, map)  dhd_pktid_map_reset_ioctl((dhd), (map))
++
++/* Convert a packet to a pktid, and save pkt pointer in busy locker */
++#define DHD_NATIVE_TO_PKTID_RSV(dhd, map, pkt, pkttype)    \
++	dhd_pktid_map_reserve((dhd), (map), (pkt), (pkttype))
++/* Reuse a previously reserved locker to save packet params */
++#define DHD_NATIVE_TO_PKTID_SAVE(dhd, map, pkt, nkey, pa, len, dir, dmah, secdma, pkttype) \
++	dhd_pktid_map_save((dhd), (map), (void *)(pkt), (nkey), (pa), (uint32)(len), \
++		(uint8)(dir), (void *)(dmah), (void *)(secdma), \
++		(dhd_pkttype_t)(pkttype))
++/* Convert a packet to a pktid, and save packet params in locker */
++#define DHD_NATIVE_TO_PKTID(dhd, map, pkt, pa, len, dir, dmah, secdma, pkttype) \
++	dhd_pktid_map_alloc((dhd), (map), (void *)(pkt), (pa), (uint32)(len), \
++		(uint8)(dir), (void *)(dmah), (void *)(secdma), \
++		(dhd_pkttype_t)(pkttype))
++
++/* Convert pktid to a packet, and free the locker */
++#define DHD_PKTID_TO_NATIVE(dhd, map, pktid, pa, len, dmah, secdma, pkttype) \
++	dhd_pktid_map_free((dhd), (map), (uint32)(pktid), \
++		(dmaaddr_t *)&(pa), (uint32 *)&(len), (void **)&(dmah), \
++		(void **)&(secdma), (dhd_pkttype_t)(pkttype), DHD_PKTID_FREE_LOCKER)
++
++/* Convert the pktid to a packet, empty locker, but keep it reserved */
++#define DHD_PKTID_TO_NATIVE_RSV(dhd, map, pktid, pa, len, dmah, secdma, pkttype) \
++	dhd_pktid_map_free((dhd), (map), (uint32)(pktid), \
++	                   (dmaaddr_t *)&(pa), (uint32 *)&(len), (void **)&(dmah), \
++	                   (void **)&(secdma), (dhd_pkttype_t)(pkttype), DHD_PKTID_RSV_LOCKER)
++
++#define DHD_PKTID_AVAIL(map)                 dhd_pktid_map_avail_cnt(map)
++
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++/**
++* dhd_pktid_audit - Use the mwbmap to audit validity of a pktid.
++*/
++static int
++dhd_pktid_audit(dhd_pub_t *dhd, dhd_pktid_map_t *pktid_map, uint32 pktid,
++	const int test_for, const char *errmsg)
++{
++#define DHD_PKT_AUDIT_STR "ERROR: %16s Host PktId Audit: "
++	struct bcm_mwbmap *handle;
++	uint32	flags;
++	bool ignore_audit;
++
++	if (pktid_map == (dhd_pktid_map_t *)NULL) {
++		DHD_ERROR((DHD_PKT_AUDIT_STR "Pkt id map NULL\n", errmsg));
++		return BCME_OK;
++	}
++
++	flags = DHD_PKTID_AUDIT_LOCK(pktid_map->pktid_audit_lock);
++
++	handle = pktid_map->pktid_audit;
++	if (handle == (struct bcm_mwbmap *)NULL) {
++		DHD_ERROR((DHD_PKT_AUDIT_STR "Handle NULL\n", errmsg));
++		DHD_PKTID_AUDIT_UNLOCK(pktid_map->pktid_audit_lock, flags);
++		return BCME_OK;
++	}
++
++	/* Exclude special pktids from audit */
++	ignore_audit = (pktid == DHD_IOCTL_REQ_PKTID) | (pktid == DHD_FAKE_PKTID);
++	if (ignore_audit) {
++		DHD_PKTID_AUDIT_UNLOCK(pktid_map->pktid_audit_lock, flags);
++		return BCME_OK;
++	}
++
++	if ((pktid == DHD_PKTID_INVALID) || (pktid > pktid_map->items)) {
++		DHD_ERROR((DHD_PKT_AUDIT_STR "PktId<%d> invalid\n", errmsg, pktid));
++		/* lock is released in "error" */
++		goto error;
++	}
++
++	/* Perform audit */
++	switch (test_for) {
++		case DHD_DUPLICATE_ALLOC:
++			if (!bcm_mwbmap_isfree(handle, pktid)) {
++				DHD_ERROR((DHD_PKT_AUDIT_STR "PktId<%d> alloc duplicate\n",
++				           errmsg, pktid));
++				goto error;
++			}
++			bcm_mwbmap_force(handle, pktid);
++			break;
++
++		case DHD_DUPLICATE_FREE:
++			if (bcm_mwbmap_isfree(handle, pktid)) {
++				DHD_ERROR((DHD_PKT_AUDIT_STR "PktId<%d> free duplicate\n",
++				           errmsg, pktid));
++				goto error;
++			}
++			bcm_mwbmap_free(handle, pktid);
++			break;
++
++		case DHD_TEST_IS_ALLOC:
++			if (bcm_mwbmap_isfree(handle, pktid)) {
++				DHD_ERROR((DHD_PKT_AUDIT_STR "PktId<%d> is not allocated\n",
++				           errmsg, pktid));
++				goto error;
++			}
++			break;
++
++		case DHD_TEST_IS_FREE:
++			if (!bcm_mwbmap_isfree(handle, pktid)) {
++				DHD_ERROR((DHD_PKT_AUDIT_STR "PktId<%d> is not free",
++				           errmsg, pktid));
++				goto error;
++			}
++			break;
++
++		default:
++			goto error;
++	}
++
++	DHD_PKTID_AUDIT_UNLOCK(pktid_map->pktid_audit_lock, flags);
++	return BCME_OK;
++
++error:
++
++	DHD_PKTID_AUDIT_UNLOCK(pktid_map->pktid_audit_lock, flags);
++	/* May insert any trap mechanism here ! */
++	dhd_pktid_error_handler(dhd);
++
++	return BCME_ERROR;
++}
++
++#define DHD_PKTID_AUDIT(dhdp, map, pktid, test_for) \
++	dhd_pktid_audit((dhdp), (dhd_pktid_map_t *)(map), (pktid), (test_for), __FUNCTION__)
++
++static int
++dhd_pktid_audit_ring_debug(dhd_pub_t *dhdp, dhd_pktid_map_t *map, uint32 pktid,
++	const int test_for, void *msg, uint32 msg_len, const char * func)
++{
++	int ret = 0;
++	ret = DHD_PKTID_AUDIT(dhdp, map, pktid, test_for);
++	if (ret == BCME_ERROR) {
++		prhex(func, (uchar *)msg, msg_len);
++	}
++	return ret;
++}
++#define DHD_PKTID_AUDIT_RING_DEBUG(dhdp, map, pktid, test_for, msg, msg_len) \
++	dhd_pktid_audit_ring_debug((dhdp), (dhd_pktid_map_t *)(map), \
++		(pktid), (test_for), msg, msg_len, __FUNCTION__)
++
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++
++/**
++ * +---------------------------------------------------------------------------+
++ * Packet to Packet Id mapper using a <numbered_key, locker> paradigm.
++ *
++ * dhd_pktid_map manages a set of unique Packet Ids range[1..MAX_xxx_PKTID].
++ *
++ * dhd_pktid_map_alloc() may be used to save some packet metadata, and a unique
++ * packet id is returned. This unique packet id may be used to retrieve the
++ * previously saved packet metadata, using dhd_pktid_map_free(). On invocation
++ * of dhd_pktid_map_free(), the unique packet id is essentially freed. A
++ * subsequent call to dhd_pktid_map_alloc() may reuse this packet id.
++ *
++ * Implementation Note:
++ * Convert this into a <key,locker> abstraction and place into bcmutils !
++ * Locker abstraction should treat contents as opaque storage, and a
++ * callback should be registered to handle busy lockers on destructor.
++ *
++ * +---------------------------------------------------------------------------+
++ */
++
++/** Allocate and initialize a mapper of num_items <numbered_key, locker> */
++
++static dhd_pktid_map_handle_t *
++dhd_pktid_map_init(dhd_pub_t *dhd, uint32 num_items)
++{
++	void* osh;
++	uint32 nkey;
++	dhd_pktid_map_t *map;
++	uint32 dhd_pktid_map_sz;
++	uint32 map_items;
++	uint32 map_keys_sz;
++	osh = dhd->osh;
++
++	dhd_pktid_map_sz = DHD_PKTID_MAP_SZ(num_items);
++
++	map = (dhd_pktid_map_t *)VMALLOC(osh, dhd_pktid_map_sz);
++	if (map == NULL) {
++		DHD_ERROR(("%s:%d: MALLOC failed for size %d\n",
++			__FUNCTION__, __LINE__, dhd_pktid_map_sz));
++		return (dhd_pktid_map_handle_t *)NULL;
++	}
++
++	/* Initialize the lock that protects this structure */
++	map->items = num_items;
++	map->avail = num_items;
++
++	map_items = DHD_PKIDMAP_ITEMS(map->items);
++
++	map_keys_sz = DHD_PKTIDMAP_KEYS_SZ(map->items);
++	map->keys = (dhd_pktid_key_t *)MALLOC(osh, map_keys_sz);
++	if (map->keys == NULL) {
++		DHD_ERROR(("%s:%d: MALLOC failed for map->keys size %d\n",
++			__FUNCTION__, __LINE__, map_keys_sz));
++		goto error;
++	}
++
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++		/* Incarnate a hierarchical multiword bitmap for auditing pktid allocator */
++		map->pktid_audit = bcm_mwbmap_init(osh, map_items + 1);
++		if (map->pktid_audit == (struct bcm_mwbmap *)NULL) {
++			DHD_ERROR(("%s:%d: pktid_audit init failed\r\n", __FUNCTION__, __LINE__));
++			goto error;
++		} else {
++			DHD_ERROR(("%s:%d: pktid_audit init succeeded %d\n",
++				__FUNCTION__, __LINE__, map_items + 1));
++		}
++		map->pktid_audit_lock = DHD_PKTID_AUDIT_LOCK_INIT(osh);
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++	for (nkey = 1; nkey <= map_items; nkey++) { /* locker #0 is reserved */
++		map->keys[nkey] = nkey; /* populate with unique keys */
++		map->lockers[nkey].state = LOCKER_IS_FREE;
++		map->lockers[nkey].pkt   = NULL; /* bzero: redundant */
++		map->lockers[nkey].len   = 0;
++	}
++
++	/* Reserve pktid #0, i.e. DHD_PKTID_INVALID to be inuse */
++	map->lockers[DHD_PKTID_INVALID].state = LOCKER_IS_BUSY; /* tag locker #0 as inuse */
++	map->lockers[DHD_PKTID_INVALID].pkt   = NULL; /* bzero: redundant */
++	map->lockers[DHD_PKTID_INVALID].len   = 0;
++
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++	/* do not use dhd_pktid_audit() here, use bcm_mwbmap_force directly */
++	bcm_mwbmap_force(map->pktid_audit, DHD_PKTID_INVALID);
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++	return (dhd_pktid_map_handle_t *)map; /* opaque handle */
++
++error:
++	if (map) {
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++		if (map->pktid_audit != (struct bcm_mwbmap *)NULL) {
++			bcm_mwbmap_fini(osh, map->pktid_audit); /* Destruct pktid_audit */
++			map->pktid_audit = (struct bcm_mwbmap *)NULL;
++			if (map->pktid_audit_lock)
++				DHD_PKTID_AUDIT_LOCK_DEINIT(osh, map->pktid_audit_lock);
++		}
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++		if (map->keys) {
++			MFREE(osh, map->keys, map_keys_sz);
++		}
++		VMFREE(osh, map, dhd_pktid_map_sz);
++	}
++	return (dhd_pktid_map_handle_t *)NULL;
++}
++
++/**
++ * Retrieve all allocated keys and free all <numbered_key, locker>.
++ * Freeing implies: unmapping the buffers and freeing the native packet
++ * This could have been a callback registered with the pktid mapper.
++ */
++static void
++dhd_pktid_map_reset(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle)
++{
++	void *osh;
++	uint32 nkey;
++	dhd_pktid_map_t *map;
++	dhd_pktid_item_t *locker;
++	uint32 map_items;
++	uint32 flags;
++	bool data_tx = FALSE;
++
++	map = (dhd_pktid_map_t *)handle;
++	DHD_GENERAL_LOCK(dhd, flags);
++	osh = dhd->osh;
++
++	map_items = DHD_PKIDMAP_ITEMS(map->items);
++	/* skip reserved KEY #0, and start from 1 */
++
++	for (nkey = 1; nkey <= map_items; nkey++) {
++		if (map->lockers[nkey].state == LOCKER_IS_BUSY) {
++			locker = &map->lockers[nkey];
++			locker->state = LOCKER_IS_FREE;
++			data_tx = (locker->pkttype == PKTTYPE_DATA_TX);
++			if (data_tx) {
++				dhd->prot->active_tx_count--;
++			}
++
++#ifdef DHD_PKTID_AUDIT_RING
++			DHD_PKTID_AUDIT(dhd, map, nkey, DHD_DUPLICATE_FREE); /* duplicate frees */
++#endif /* DHD_PKTID_AUDIT_RING */
++
++			{
++				if (SECURE_DMA_ENAB(dhd->osh))
++					SECURE_DMA_UNMAP(osh, locker->pa,
++						locker->len, locker->dir, 0,
++						locker->dmah, locker->secdma, 0);
++				else
++					DMA_UNMAP(osh, locker->pa, locker->len,
++						locker->dir, 0, locker->dmah);
++			}
++			dhd_prot_packet_free(dhd, (ulong*)locker->pkt,
++				locker->pkttype, data_tx);
++		}
++		else {
++#ifdef DHD_PKTID_AUDIT_RING
++			DHD_PKTID_AUDIT(dhd, map, nkey, DHD_TEST_IS_FREE);
++#endif /* DHD_PKTID_AUDIT_RING */
++		}
++		map->keys[nkey] = nkey; /* populate with unique keys */
++	}
++
++	map->avail = map_items;
++	memset(&map->lockers[1], 0, sizeof(dhd_pktid_item_t) * map_items);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++}
++
++#ifdef IOCTLRESP_USE_CONSTMEM
++/** Called in detach scenario. Releasing IOCTL buffers. */
++static void
++dhd_pktid_map_reset_ioctl(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle)
++{
++	uint32 nkey;
++	dhd_pktid_map_t *map;
++	dhd_pktid_item_t *locker;
++	uint32 map_items;
++	uint32 flags;
++
++	map = (dhd_pktid_map_t *)handle;
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	map_items = DHD_PKIDMAP_ITEMS(map->items);
++	/* skip reserved KEY #0, and start from 1 */
++	for (nkey = 1; nkey <= map_items; nkey++) {
++		if (map->lockers[nkey].state == LOCKER_IS_BUSY) {
++			dhd_dma_buf_t retbuf;
++
++#ifdef DHD_PKTID_AUDIT_RING
++			DHD_PKTID_AUDIT(dhd, map, nkey, DHD_DUPLICATE_FREE); /* duplicate frees */
++#endif /* DHD_PKTID_AUDIT_RING */
++
++			locker = &map->lockers[nkey];
++			retbuf.va = locker->pkt;
++			retbuf.len = locker->len;
++			retbuf.pa = locker->pa;
++			retbuf.dmah = locker->dmah;
++			retbuf.secdma = locker->secdma;
++
++			/* This could be a callback registered with dhd_pktid_map */
++			DHD_GENERAL_UNLOCK(dhd, flags);
++			free_ioctl_return_buffer(dhd, &retbuf);
++			DHD_GENERAL_LOCK(dhd, flags);
++		}
++		else {
++#ifdef DHD_PKTID_AUDIT_RING
++			DHD_PKTID_AUDIT(dhd, map, nkey, DHD_TEST_IS_FREE);
++#endif /* DHD_PKTID_AUDIT_RING */
++		}
++		map->keys[nkey] = nkey; /* populate with unique keys */
++	}
++
++	map->avail = map_items;
++	memset(&map->lockers[1], 0, sizeof(dhd_pktid_item_t) * map_items);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++}
++#endif /* IOCTLRESP_USE_CONSTMEM */
++
++
++/**
++ * Free the pktid map.
++ */
++static void
++dhd_pktid_map_fini(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle)
++{
++	dhd_pktid_map_t *map;
++	uint32 dhd_pktid_map_sz;
++	uint32 map_keys_sz;
++
++	/* Free any pending packets */
++	dhd_pktid_map_reset(dhd, handle);
++
++	map = (dhd_pktid_map_t *)handle;
++	dhd_pktid_map_sz = DHD_PKTID_MAP_SZ(map->items);
++	map_keys_sz = DHD_PKTIDMAP_KEYS_SZ(map->items);
++
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++	if (map->pktid_audit != (struct bcm_mwbmap *)NULL) {
++		bcm_mwbmap_fini(dhd->osh, map->pktid_audit); /* Destruct pktid_audit */
++		map->pktid_audit = (struct bcm_mwbmap *)NULL;
++		if (map->pktid_audit_lock) {
++			DHD_PKTID_AUDIT_LOCK_DEINIT(dhd->osh, map->pktid_audit_lock);
++		}
++	}
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++	MFREE(dhd->osh, map->keys, map_keys_sz);
++	VMFREE(dhd->osh, handle, dhd_pktid_map_sz);
++}
++#ifdef IOCTLRESP_USE_CONSTMEM
++static void
++dhd_pktid_map_fini_ioctl(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle)
++{
++	dhd_pktid_map_t *map;
++	uint32 dhd_pktid_map_sz;
++	uint32 map_keys_sz;
++
++	/* Free any pending packets */
++	dhd_pktid_map_reset_ioctl(dhd, handle);
++
++	map = (dhd_pktid_map_t *)handle;
++	dhd_pktid_map_sz = DHD_PKTID_MAP_SZ(map->items);
++	map_keys_sz = DHD_PKTIDMAP_KEYS_SZ(map->items);
++
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++	if (map->pktid_audit != (struct bcm_mwbmap *)NULL) {
++		bcm_mwbmap_fini(dhd->osh, map->pktid_audit); /* Destruct pktid_audit */
++		map->pktid_audit = (struct bcm_mwbmap *)NULL;
++		if (map->pktid_audit_lock) {
++			DHD_PKTID_AUDIT_LOCK_DEINIT(dhd->osh, map->pktid_audit_lock);
++		}
++	}
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++	MFREE(dhd->osh, map->keys, map_keys_sz);
++	VMFREE(dhd->osh, handle, dhd_pktid_map_sz);
++}
++#endif /* IOCTLRESP_USE_CONSTMEM */
++
++/** Get the pktid free count */
++static INLINE uint32 BCMFASTPATH
++dhd_pktid_map_avail_cnt(dhd_pktid_map_handle_t *handle)
++{
++	dhd_pktid_map_t *map;
++	uint32	avail;
++
++	ASSERT(handle != NULL);
++	map = (dhd_pktid_map_t *)handle;
++
++	avail = map->avail;
++
++	return avail;
++}
++
++/**
++ * dhd_pktid_map_reserve - reserve a unique numbered key. Reserved locker is not
++ * yet populated. Invoke the pktid save api to populate the packet parameters
++ * into the locker. This function is not reentrant, and is the caller's
++ * responsibility. Caller must treat a returned value DHD_PKTID_INVALID as
++ * a failure case, implying a depleted pool of pktids.
++ */
++static INLINE uint32
++dhd_pktid_map_reserve(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle,
++	void *pkt, dhd_pkttype_t pkttype)
++{
++	uint32 nkey;
++	dhd_pktid_map_t *map;
++	dhd_pktid_item_t *locker;
++
++	ASSERT(handle != NULL);
++	map = (dhd_pktid_map_t *)handle;
++
++	if ((int)(map->avail) <= 0) { /* no more pktids to allocate */
++		map->failures++;
++		DHD_INFO(("%s:%d: failed, no free keys\n", __FUNCTION__, __LINE__));
++		return DHD_PKTID_INVALID; /* failed alloc request */
++	}
++
++	ASSERT(map->avail <= map->items);
++	nkey = map->keys[map->avail]; /* fetch a free locker, pop stack */
++
++	if ((map->avail > map->items) || (nkey > map->items)) {
++		map->failures++;
++		DHD_ERROR(("%s:%d: failed to allocate a new pktid,"
++			" map->avail<%u>, nkey<%u>, pkttype<%u>\n",
++			__FUNCTION__, __LINE__, map->avail, nkey,
++			pkttype));
++		return DHD_PKTID_INVALID; /* failed alloc request */
++	}
++
++	locker = &map->lockers[nkey]; /* save packet metadata in locker */
++	map->avail--;
++	locker->pkt = pkt; /* pkt is saved, other params not yet saved. */
++	locker->len = 0;
++	locker->state = LOCKER_IS_BUSY; /* reserve this locker */
++
++	ASSERT(nkey != DHD_PKTID_INVALID);
++	return nkey; /* return locker's numbered key */
++}
++
++/*
++ * dhd_pktid_map_save - Save a packet's parameters into a locker
++ * corresponding to a previously reserved unique numbered key.
++ */
++static INLINE void
++dhd_pktid_map_save(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle, void *pkt,
++	uint32 nkey, dmaaddr_t pa, uint32 len, uint8 dir, void *dmah, void *secdma,
++	dhd_pkttype_t pkttype)
++{
++	dhd_pktid_map_t *map;
++	dhd_pktid_item_t *locker;
++
++	ASSERT(handle != NULL);
++	map = (dhd_pktid_map_t *)handle;
++
++	if ((nkey == DHD_PKTID_INVALID) || (nkey > DHD_PKIDMAP_ITEMS(map->items))) {
++		DHD_ERROR(("%s:%d: Error! saving invalid pktid<%u> pkttype<%u>\n",
++			__FUNCTION__, __LINE__, nkey, pkttype));
++#ifdef DHD_FW_COREDUMP
++		if (dhd->memdump_enabled) {
++			/* collect core dump */
++			dhd->memdump_type = DUMP_TYPE_PKTID_INVALID;
++			dhd_bus_mem_dump(dhd);
++		}
++#else
++		ASSERT(0);
++#endif /* DHD_FW_COREDUMP */
++		return;
++	}
++
++	locker = &map->lockers[nkey];
++
++	ASSERT(((locker->state == LOCKER_IS_BUSY) && (locker->pkt == pkt)) ||
++		((locker->state == LOCKER_IS_RSVD) && (locker->pkt == NULL)));
++
++	/* store contents in locker */
++	locker->dir = dir;
++	locker->pa = pa;
++	locker->len = (uint16)len; /* 16bit len */
++	locker->dmah = dmah; /* 16bit len */
++	locker->secdma = secdma;
++	locker->pkttype = pkttype;
++	locker->pkt = pkt;
++	locker->state = LOCKER_IS_BUSY; /* make this locker busy */
++}
++
++/**
++ * dhd_pktid_map_alloc - Allocate a unique numbered key and save the packet
++ * contents into the corresponding locker. Return the numbered key.
++ */
++static uint32 BCMFASTPATH
++dhd_pktid_map_alloc(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle, void *pkt,
++	dmaaddr_t pa, uint32 len, uint8 dir, void *dmah, void *secdma,
++	dhd_pkttype_t pkttype)
++{
++	uint32 nkey;
++
++	nkey = dhd_pktid_map_reserve(dhd, handle, pkt, pkttype);
++	if (nkey != DHD_PKTID_INVALID) {
++		dhd_pktid_map_save(dhd, handle, pkt, nkey, pa,
++			len, dir, dmah, secdma, pkttype);
++	}
++
++	return nkey;
++}
++
++/**
++ * dhd_pktid_map_free - Given a numbered key, return the locker contents.
++ * dhd_pktid_map_free() is not reentrant, and is the caller's responsibility.
++ * Caller may not free a pktid value DHD_PKTID_INVALID or an arbitrary pktid
++ * value. Only a previously allocated pktid may be freed.
++ */
++static void * BCMFASTPATH
++dhd_pktid_map_free(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle, uint32 nkey,
++	dmaaddr_t *pa, uint32 *len, void **dmah, void **secdma, dhd_pkttype_t pkttype,
++	bool rsv_locker)
++{
++	dhd_pktid_map_t *map;
++	dhd_pktid_item_t *locker;
++	void * pkt;
++	unsigned long long locker_addr;
++
++	ASSERT(handle != NULL);
++
++	map = (dhd_pktid_map_t *)handle;
++
++	if ((nkey == DHD_PKTID_INVALID) || (nkey > DHD_PKIDMAP_ITEMS(map->items))) {
++		DHD_ERROR(("%s:%d: Error! Try to free invalid pktid<%u>, pkttype<%d>\n",
++		           __FUNCTION__, __LINE__, nkey, pkttype));
++#ifdef DHD_FW_COREDUMP
++		if (dhd->memdump_enabled) {
++			/* collect core dump */
++			dhd->memdump_type = DUMP_TYPE_PKTID_INVALID;
++			dhd_bus_mem_dump(dhd);
++		}
++#else
++		ASSERT(0);
++#endif /* DHD_FW_COREDUMP */
++		return NULL;
++	}
++
++	locker = &map->lockers[nkey];
++
++#if defined(DHD_PKTID_AUDIT_MAP)
++	DHD_PKTID_AUDIT(dhd, map, nkey, DHD_DUPLICATE_FREE); /* Audit duplicate FREE */
++#endif /* DHD_PKTID_AUDIT_MAP */
++
++	/* Debug check for cloned numbered key */
++	if (locker->state == LOCKER_IS_FREE) {
++		DHD_ERROR(("%s:%d: Error! freeing already freed invalid pktid<%u>\n",
++		           __FUNCTION__, __LINE__, nkey));
++#ifdef DHD_FW_COREDUMP
++		if (dhd->memdump_enabled) {
++			/* collect core dump */
++			dhd->memdump_type = DUMP_TYPE_PKTID_INVALID;
++			dhd_bus_mem_dump(dhd);
++		}
++#else
++		ASSERT(0);
++#endif /* DHD_FW_COREDUMP */
++		return NULL;
++	}
++
++	/* Check for the colour of the buffer i.e The buffer posted for TX,
++	 * should be freed for TX completion. Similarly the buffer posted for
++	 * IOCTL should be freed for IOCT completion etc.
++	 */
++	if ((pkttype != PKTTYPE_NO_CHECK) && (locker->pkttype != pkttype)) {
++
++		DHD_ERROR(("%s:%d: Error! Invalid Buffer Free for pktid<%u> \n",
++			__FUNCTION__, __LINE__, nkey));
++#ifdef BCMDMA64OSL
++		PHYSADDRTOULONG(locker->pa, locker_addr);
++#else
++		locker_addr = PHYSADDRLO(locker->pa);
++#endif /* BCMDMA64OSL */
++		DHD_ERROR(("%s:%d: locker->state <%d>, locker->pkttype <%d>,"
++			"pkttype <%d> locker->pa <0x%llx> \n",
++			__FUNCTION__, __LINE__, locker->state, locker->pkttype,
++			pkttype, locker_addr));
++#ifdef DHD_FW_COREDUMP
++		if (dhd->memdump_enabled) {
++			/* collect core dump */
++			dhd->memdump_type = DUMP_TYPE_PKTID_INVALID;
++			dhd_bus_mem_dump(dhd);
++		}
++#else
++		ASSERT(0);
++#endif /* DHD_FW_COREDUMP */
++		return NULL;
++	}
++
++	if (rsv_locker == DHD_PKTID_FREE_LOCKER) {
++		map->avail++;
++		map->keys[map->avail] = nkey; /* make this numbered key available */
++		locker->state = LOCKER_IS_FREE; /* open and free Locker */
++	} else {
++		/* pktid will be reused, but the locker does not have a valid pkt */
++		locker->state = LOCKER_IS_RSVD;
++	}
++
++#if defined(DHD_PKTID_AUDIT_MAP)
++	DHD_PKTID_AUDIT(dhd, map, nkey, DHD_TEST_IS_FREE);
++#endif /* DHD_PKTID_AUDIT_MAP */
++
++	*pa = locker->pa; /* return contents of locker */
++	*len = (uint32)locker->len;
++	*dmah = locker->dmah;
++	*secdma = locker->secdma;
++
++	pkt = locker->pkt;
++	locker->pkt = NULL; /* Clear pkt */
++	locker->len = 0;
++
++	return pkt;
++}
++
++#else /* ! DHD_PCIE_PKTID */
++
++
++typedef struct pktlist {
++	PKT_LIST *tx_pkt_list;		/* list for tx packets */
++	PKT_LIST *rx_pkt_list;		/* list for rx packets */
++	PKT_LIST *ctrl_pkt_list;	/* list for ioctl/event buf post */
++} pktlists_t;
++
++/*
++ * Given that each workitem only uses a 32bit pktid, only 32bit hosts may avail
++ * of a one to one mapping 32bit pktptr and a 32bit pktid.
++ *
++ * - When PKTIDMAP is not used, DHD_NATIVE_TO_PKTID variants will never fail.
++ * - Neither DHD_NATIVE_TO_PKTID nor DHD_PKTID_TO_NATIVE need to be protected by
++ *   a lock.
++ * - Hence DHD_PKTID_INVALID is not defined when DHD_PCIE_PKTID is undefined.
++ */
++#define DHD_PKTID32(pktptr32)	((uint32)(pktptr32))
++#define DHD_PKTPTR32(pktid32)	((void *)(pktid32))
++
++
++static INLINE uint32 dhd_native_to_pktid(dhd_pktid_map_handle_t *map, void *pktptr32,
++	dmaaddr_t pa, uint32 dma_len, void *dmah, void *secdma,
++	dhd_pkttype_t pkttype);
++static INLINE void * dhd_pktid_to_native(dhd_pktid_map_handle_t *map, uint32 pktid32,
++	dmaaddr_t *pa, uint32 *dma_len, void **dmah, void **secdma,
++	dhd_pkttype_t pkttype);
++
++static dhd_pktid_map_handle_t *
++dhd_pktid_map_init(dhd_pub_t *dhd, uint32 num_items)
++{
++	osl_t *osh = dhd->osh;
++	pktlists_t *handle = NULL;
++
++	if ((handle = (pktlists_t *) MALLOCZ(osh, sizeof(pktlists_t))) == NULL) {
++		DHD_ERROR(("%s:%d: MALLOC failed for lists allocation, size=%d\n",
++		           __FUNCTION__, __LINE__, sizeof(pktlists_t)));
++		goto error_done;
++	}
++
++	if ((handle->tx_pkt_list = (PKT_LIST *) MALLOC(osh, sizeof(PKT_LIST))) == NULL) {
++		DHD_ERROR(("%s:%d: MALLOC failed for list allocation, size=%d\n",
++		           __FUNCTION__, __LINE__, sizeof(PKT_LIST)));
++		goto error;
++	}
++
++	if ((handle->rx_pkt_list = (PKT_LIST *) MALLOC(osh, sizeof(PKT_LIST))) == NULL) {
++		DHD_ERROR(("%s:%d: MALLOC failed for list allocation, size=%d\n",
++		           __FUNCTION__, __LINE__, sizeof(PKT_LIST)));
++		goto error;
++	}
++
++	if ((handle->ctrl_pkt_list = (PKT_LIST *) MALLOC(osh, sizeof(PKT_LIST))) == NULL) {
++		DHD_ERROR(("%s:%d: MALLOC failed for list allocation, size=%d\n",
++		           __FUNCTION__, __LINE__, sizeof(PKT_LIST)));
++		goto error;
++	}
++
++	PKTLIST_INIT(handle->tx_pkt_list);
++	PKTLIST_INIT(handle->rx_pkt_list);
++	PKTLIST_INIT(handle->ctrl_pkt_list);
++
++	return (dhd_pktid_map_handle_t *) handle;
++
++error:
++	if (handle->ctrl_pkt_list) {
++		MFREE(osh, handle->ctrl_pkt_list, sizeof(PKT_LIST));
++	}
++
++	if (handle->rx_pkt_list) {
++		MFREE(osh, handle->rx_pkt_list, sizeof(PKT_LIST));
++	}
++
++	if (handle->tx_pkt_list) {
++		MFREE(osh, handle->tx_pkt_list, sizeof(PKT_LIST));
++	}
++
++	if (handle) {
++		MFREE(osh, handle, sizeof(pktlists_t));
++	}
++
++error_done:
++	return (dhd_pktid_map_handle_t *)NULL;
++}
++
++static void
++dhd_pktid_map_fini(dhd_pub_t *dhd, dhd_pktid_map_handle_t *map)
++{
++	osl_t *osh = dhd->osh;
++	pktlists_t *handle = (pktlists_t *) map;
++
++	ASSERT(handle != NULL);
++	if (handle == (pktlists_t *)NULL)
++		return;
++
++	if (handle->ctrl_pkt_list) {
++		PKTLIST_FINI(handle->ctrl_pkt_list);
++		MFREE(osh, handle->ctrl_pkt_list, sizeof(PKT_LIST));
++	}
++
++	if (handle->rx_pkt_list) {
++		PKTLIST_FINI(handle->rx_pkt_list);
++		MFREE(osh, handle->rx_pkt_list, sizeof(PKT_LIST));
++	}
++
++	if (handle->tx_pkt_list) {
++		PKTLIST_FINI(handle->tx_pkt_list);
++		MFREE(osh, handle->tx_pkt_list, sizeof(PKT_LIST));
++	}
++
++	if (handle) {
++		MFREE(osh, handle, sizeof(pktlists_t));
++	}
++}
++
++/** Save dma parameters into the packet's pkttag and convert a pktptr to pktid */
++static INLINE uint32
++dhd_native_to_pktid(dhd_pktid_map_handle_t *map, void *pktptr32,
++	dmaaddr_t pa, uint32 dma_len, void *dmah, void *secdma,
++	dhd_pkttype_t pkttype)
++{
++	pktlists_t *handle = (pktlists_t *) map;
++	ASSERT(pktptr32 != NULL);
++	DHD_PKT_SET_DMA_LEN(pktptr32, dma_len);
++	DHD_PKT_SET_DMAH(pktptr32, dmah);
++	DHD_PKT_SET_PA(pktptr32, pa);
++	DHD_PKT_SET_SECDMA(pktptr32, secdma);
++
++	if (pkttype == PKTTYPE_DATA_TX) {
++		PKTLIST_ENQ(handle->tx_pkt_list,  pktptr32);
++	} else if (pkttype == PKTTYPE_DATA_RX) {
++		PKTLIST_ENQ(handle->rx_pkt_list,  pktptr32);
++	} else {
++		PKTLIST_ENQ(handle->ctrl_pkt_list,  pktptr32);
++	}
++
++	return DHD_PKTID32(pktptr32);
++}
++
++/** Convert a pktid to pktptr and retrieve saved dma parameters from packet */
++static INLINE void *
++dhd_pktid_to_native(dhd_pktid_map_handle_t *map, uint32 pktid32,
++	dmaaddr_t *pa, uint32 *dma_len, void **dmah, void **secdma,
++	dhd_pkttype_t pkttype)
++{
++	pktlists_t *handle = (pktlists_t *) map;
++	void *pktptr32;
++
++	ASSERT(pktid32 != 0U);
++	pktptr32 = DHD_PKTPTR32(pktid32);
++	*dma_len = DHD_PKT_GET_DMA_LEN(pktptr32);
++	*dmah = DHD_PKT_GET_DMAH(pktptr32);
++	*pa = DHD_PKT_GET_PA(pktptr32);
++	*secdma = DHD_PKT_GET_SECDMA(pktptr32);
++
++	if (pkttype == PKTTYPE_DATA_TX) {
++		PKTLIST_UNLINK(handle->tx_pkt_list,  pktptr32);
++	} else if (pkttype == PKTTYPE_DATA_RX) {
++		PKTLIST_UNLINK(handle->rx_pkt_list,  pktptr32);
++	} else {
++		PKTLIST_UNLINK(handle->ctrl_pkt_list,  pktptr32);
++	}
++
++	return pktptr32;
++}
++
++#define DHD_NATIVE_TO_PKTID_RSV(dhd, map, pkt, pkttype)  DHD_PKTID32(pkt)
++
++#define DHD_NATIVE_TO_PKTID_SAVE(dhd, map, pkt, nkey, pa, len, dma_dir, dmah, secdma, pkttype) \
++	({ BCM_REFERENCE(dhd); BCM_REFERENCE(nkey); BCM_REFERENCE(dma_dir); \
++	   dhd_native_to_pktid((dhd_pktid_map_handle_t *) map, (pkt), (pa), (len), \
++			   (dmah), (secdma), (dhd_pkttype_t)(pkttype)); \
++	})
++
++#define DHD_NATIVE_TO_PKTID(dhd, map, pkt, pa, len, dma_dir, dmah, secdma, pkttype) \
++	({ BCM_REFERENCE(dhd); BCM_REFERENCE(dma_dir); \
++	   dhd_native_to_pktid((dhd_pktid_map_handle_t *) map, (pkt), (pa), (len), \
++			   (dmah), (secdma), (dhd_pkttype_t)(pkttype)); \
++	})
++
++#define DHD_PKTID_TO_NATIVE(dhd, map, pktid, pa, len, dmah, secdma, pkttype) \
++	({ BCM_REFERENCE(dhd); BCM_REFERENCE(pkttype);	\
++		dhd_pktid_to_native((dhd_pktid_map_handle_t *) map, (uint32)(pktid), \
++				(dmaaddr_t *)&(pa), (uint32 *)&(len), (void **)&(dmah), \
++				(void **)&secdma, (dhd_pkttype_t)(pkttype)); \
++	})
++
++#define DHD_PKTID_AVAIL(map)  (~0)
++
++#endif /* ! DHD_PCIE_PKTID */
++
++/* +------------------ End of PCIE DHD PKTID MAPPER  -----------------------+ */
++
++
++/**
++ * The PCIE FD protocol layer is constructed in two phases:
++ *    Phase 1. dhd_prot_attach()
++ *    Phase 2. dhd_prot_init()
++ *
++ * dhd_prot_attach() - Allocates a dhd_prot_t object and resets all its fields.
++ * All Common rings are allose attached (msgbuf_ring_t objects are allocated
++ * with DMA-able buffers).
++ * All dhd_dma_buf_t objects are also allocated here.
++ *
++ * As dhd_prot_attach is invoked prior to the pcie_shared object is read, any
++ * initialization of objects that requires information advertized by the dongle
++ * may not be performed here.
++ * E.g. the number of TxPost flowrings is not know at this point, neither do
++ * we know shich form of D2H DMA sync mechanism is advertized by the dongle, or
++ * whether the dongle supports DMA-ing of WR/RD indices for the H2D and/or D2H
++ * rings (common + flow).
++ *
++ * dhd_prot_init() is invoked after the bus layer has fetched the information
++ * advertized by the dongle in the pcie_shared_t.
++ */
++int
++dhd_prot_attach(dhd_pub_t *dhd)
++{
++	osl_t *osh = dhd->osh;
++	dhd_prot_t *prot;
++
++	/* Allocate prot structure */
++	if (!(prot = (dhd_prot_t *)DHD_OS_PREALLOC(dhd, DHD_PREALLOC_PROT,
++		sizeof(dhd_prot_t)))) {
++		DHD_ERROR(("%s: kmalloc failed\n", __FUNCTION__));
++		goto fail;
++	}
++	memset(prot, 0, sizeof(*prot));
++
++	prot->osh = osh;
++	dhd->prot = prot;
++
++	/* DMAing ring completes supported? FALSE by default  */
++	dhd->dma_d2h_ring_upd_support = FALSE;
++	dhd->dma_h2d_ring_upd_support = FALSE;
++	dhd->dma_ring_upd_overwrite = FALSE;
++
++	dhd->idma_inited = 0;
++	dhd->ifrm_inited = 0;
++
++	/* Common Ring Allocations */
++
++	/* Ring  0: H2D Control Submission */
++	if (dhd_prot_ring_attach(dhd, &prot->h2dring_ctrl_subn, "h2dctrl",
++	        H2DRING_CTRL_SUB_MAX_ITEM, H2DRING_CTRL_SUB_ITEMSIZE,
++	        BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT) != BCME_OK) {
++		DHD_ERROR(("%s: dhd_prot_ring_attach H2D Ctrl Submission failed\n",
++			__FUNCTION__));
++		goto fail;
++	}
++
++	/* Ring  1: H2D Receive Buffer Post */
++	if (dhd_prot_ring_attach(dhd, &prot->h2dring_rxp_subn, "h2drxp",
++	        H2DRING_RXPOST_MAX_ITEM, H2DRING_RXPOST_ITEMSIZE,
++	        BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT) != BCME_OK) {
++		DHD_ERROR(("%s: dhd_prot_ring_attach H2D RxPost failed\n",
++			__FUNCTION__));
++		goto fail;
++	}
++
++	/* Ring  2: D2H Control Completion */
++	if (dhd_prot_ring_attach(dhd, &prot->d2hring_ctrl_cpln, "d2hctrl",
++	        D2HRING_CTRL_CMPLT_MAX_ITEM, D2HRING_CTRL_CMPLT_ITEMSIZE,
++	        BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE) != BCME_OK) {
++		DHD_ERROR(("%s: dhd_prot_ring_attach D2H Ctrl Completion failed\n",
++			__FUNCTION__));
++		goto fail;
++	}
++
++	/* Ring  3: D2H Transmit Complete */
++	if (dhd_prot_ring_attach(dhd, &prot->d2hring_tx_cpln, "d2htxcpl",
++	        D2HRING_TXCMPLT_MAX_ITEM, D2HRING_TXCMPLT_ITEMSIZE,
++	        BCMPCIE_D2H_MSGRING_TX_COMPLETE) != BCME_OK) {
++		DHD_ERROR(("%s: dhd_prot_ring_attach D2H Tx Completion failed\n",
++			__FUNCTION__));
++		goto fail;
++
++	}
++
++	/* Ring  4: D2H Receive Complete */
++	if (dhd_prot_ring_attach(dhd, &prot->d2hring_rx_cpln, "d2hrxcpl",
++	        D2HRING_RXCMPLT_MAX_ITEM, D2HRING_RXCMPLT_ITEMSIZE,
++	        BCMPCIE_D2H_MSGRING_RX_COMPLETE) != BCME_OK) {
++		DHD_ERROR(("%s: dhd_prot_ring_attach D2H Rx Completion failed\n",
++			__FUNCTION__));
++		goto fail;
++
++	}
++
++	/*
++	 * Max number of flowrings is not yet known. msgbuf_ring_t with DMA-able
++	 * buffers for flowrings will be instantiated, in dhd_prot_init() .
++	 * See dhd_prot_flowrings_pool_attach()
++	 */
++	/* ioctl response buffer */
++	if (dhd_dma_buf_alloc(dhd, &prot->retbuf, IOCT_RETBUF_SIZE)) {
++		goto fail;
++	}
++
++	/* IOCTL request buffer */
++	if (dhd_dma_buf_alloc(dhd, &prot->ioctbuf, IOCT_RETBUF_SIZE)) {
++		goto fail;
++	}
++
++	/* Host TS request buffer one buffer for now */
++	if (dhd_dma_buf_alloc(dhd, &prot->hostts_req_buf, CTRLSUB_HOSTTS_MEESAGE_SIZE)) {
++		goto fail;
++	}
++	prot->hostts_req_buf_inuse = FALSE;
++
++	/* Scratch buffer for dma rx offset */
++#ifdef BCM_HOST_BUF
++	if (dhd_dma_buf_alloc(dhd, &prot->d2h_dma_scratch_buf,
++		ROUNDUP(DMA_D2H_SCRATCH_BUF_LEN, 16) + DMA_HOST_BUFFER_LEN))
++#else
++	if (dhd_dma_buf_alloc(dhd, &prot->d2h_dma_scratch_buf, DMA_D2H_SCRATCH_BUF_LEN))
++#endif /* BCM_HOST_BUF */
++	{
++		goto fail;
++	}
++
++	/* scratch buffer bus throughput measurement */
++	if (dhd_dma_buf_alloc(dhd, &prot->host_bus_throughput_buf, DHD_BUS_TPUT_BUF_LEN)) {
++		goto fail;
++	}
++
++#ifdef DHD_RX_CHAINING
++	dhd_rxchain_reset(&prot->rxchain);
++#endif
++
++	prot->rx_lock = dhd_os_spin_lock_init(dhd->osh);
++
++	prot->pktid_ctrl_map = DHD_NATIVE_TO_PKTID_INIT(dhd, MAX_CTRL_PKTID);
++	if (prot->pktid_ctrl_map == NULL) {
++		goto fail;
++	}
++
++	prot->pktid_rx_map = DHD_NATIVE_TO_PKTID_INIT(dhd, MAX_RX_PKTID);
++	if (prot->pktid_rx_map == NULL)
++		goto fail;
++
++	prot->pktid_tx_map = DHD_NATIVE_TO_PKTID_INIT(dhd, MAX_TX_PKTID);
++	if (prot->pktid_rx_map == NULL)
++		goto fail;
++
++#ifdef IOCTLRESP_USE_CONSTMEM
++	prot->pktid_map_handle_ioctl = DHD_NATIVE_TO_PKTID_INIT(dhd,
++		DHD_FLOWRING_MAX_IOCTLRESPBUF_POST);
++	if (prot->pktid_map_handle_ioctl == NULL) {
++		goto fail;
++	}
++#endif /* IOCTLRESP_USE_CONSTMEM */
++
++	   /* Initialize the work queues to be used by the Load Balancing logic */
++#if defined(DHD_LB_TXC)
++	{
++		void *buffer;
++		buffer = MALLOC(dhd->osh, sizeof(void*) * DHD_LB_WORKQ_SZ);
++		bcm_workq_init(&prot->tx_compl_prod, &prot->tx_compl_cons,
++			buffer, DHD_LB_WORKQ_SZ);
++		prot->tx_compl_prod_sync = 0;
++		DHD_INFO(("%s: created tx_compl_workq <%p,%d>\n",
++			__FUNCTION__, buffer, DHD_LB_WORKQ_SZ));
++	}
++#endif /* DHD_LB_TXC */
++
++#if defined(DHD_LB_RXC)
++	{
++		void *buffer;
++		buffer = MALLOC(dhd->osh, sizeof(void*) * DHD_LB_WORKQ_SZ);
++		bcm_workq_init(&prot->rx_compl_prod, &prot->rx_compl_cons,
++			buffer, DHD_LB_WORKQ_SZ);
++		prot->rx_compl_prod_sync = 0;
++		DHD_INFO(("%s: created rx_compl_workq <%p,%d>\n",
++			__FUNCTION__, buffer, DHD_LB_WORKQ_SZ));
++	}
++#endif /* DHD_LB_RXC */
++	/* Initialize trap buffer */
++	if (dhd_dma_buf_alloc(dhd, &dhd->prot->fw_trap_buf, BCMPCIE_EXT_TRAP_DATA_MAXLEN)) {
++		DHD_ERROR(("%s: dhd_init_trap_buffer falied\n", __FUNCTION__));
++		goto fail;
++	}
++
++	return BCME_OK;
++
++fail:
++
++#ifndef CONFIG_DHD_USE_STATIC_BUF
++	if (prot != NULL) {
++		dhd_prot_detach(dhd);
++	}
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++
++	return BCME_NOMEM;
++} /* dhd_prot_attach */
++
++void
++dhd_set_host_cap(dhd_pub_t *dhd)
++{
++	uint32 data = 0;
++	dhd_prot_t *prot = dhd->prot;
++
++	if (dhd->bus->api.fw_rev >= PCIE_SHARED_VERSION_6) {
++		if (dhd->h2d_phase_supported) {
++
++			data |= HOSTCAP_H2D_VALID_PHASE;
++
++			if (dhd->force_dongletrap_on_bad_h2d_phase) {
++				data |= HOSTCAP_H2D_ENABLE_TRAP_ON_BADPHASE;
++			}
++		}
++		if (prot->host_ipc_version > prot->device_ipc_version) {
++			prot->active_ipc_version = prot->device_ipc_version;
++		} else {
++			prot->active_ipc_version = prot->host_ipc_version;
++		}
++
++		data |= prot->active_ipc_version;
++
++		if (dhdpcie_bus_get_pcie_hostready_supported(dhd->bus)) {
++
++			DHD_INFO(("Advertise Hostready Capability\n"));
++
++			data |= HOSTCAP_H2D_ENABLE_HOSTRDY;
++		}
++#ifdef PCIE_INB_DW
++		if (dhdpcie_bus_get_pcie_inband_dw_supported(dhd->bus)) {
++			DHD_INFO(("Advertise Inband-DW Capability\n"));
++			data |= HOSTCAP_DS_INBAND_DW;
++			data |= HOSTCAP_DS_NO_OOB_DW;
++			dhdpcie_bus_enab_pcie_dw(dhd->bus, DEVICE_WAKE_INB);
++		} else
++#endif /* PCIE_INB_DW */
++#ifdef PCIE_OOB
++		if (dhdpcie_bus_get_pcie_oob_dw_supported(dhd->bus)) {
++			dhdpcie_bus_enab_pcie_dw(dhd->bus, DEVICE_WAKE_OOB);
++		} else
++#endif /* PCIE_OOB */
++		{
++			/* Disable DS altogether */
++			data |= HOSTCAP_DS_NO_OOB_DW;
++			dhdpcie_bus_enab_pcie_dw(dhd->bus, DEVICE_WAKE_NONE);
++		}
++
++		if (dhdpcie_bus_get_pcie_idma_supported(dhd->bus)) {
++
++			DHD_ERROR(("IDMA inited\n"));
++			data |= HOSTCAP_H2D_IDMA;
++			dhd->idma_inited = TRUE;
++		}
++
++		if (dhdpcie_bus_get_pcie_ifrm_supported(dhd->bus)) {
++			DHD_ERROR(("IFRM Inited\n"));
++			data |= HOSTCAP_H2D_IFRM;
++			dhd->ifrm_inited = TRUE;
++			dhd->dma_h2d_ring_upd_support = FALSE;
++			dhd_prot_dma_indx_free(dhd);
++		}
++
++		/* Indicate support for TX status metadata */
++		data |= HOSTCAP_TXSTATUS_METADATA;
++
++		/* Indicate support for extended trap data */
++		data |= HOSTCAP_EXTENDED_TRAP_DATA;
++
++		DHD_INFO(("%s:Active Ver:%d, Host Ver:%d, FW Ver:%d\n",
++			__FUNCTION__,
++			prot->active_ipc_version, prot->host_ipc_version,
++			prot->device_ipc_version));
++
++		dhd_bus_cmn_writeshared(dhd->bus, &data, sizeof(uint32), HOST_API_VERSION, 0);
++		dhd_bus_cmn_writeshared(dhd->bus, &prot->fw_trap_buf.pa,
++			sizeof(prot->fw_trap_buf.pa), DNGL_TO_HOST_TRAP_ADDR, 0);
++	}
++#ifdef HOFFLOAD_MODULES
++		dhd_bus_cmn_writeshared(dhd->bus, &dhd->hmem.data_addr,
++			sizeof(dhd->hmem.data_addr), WRT_HOST_MODULE_ADDR, 0);
++#endif
++
++#ifdef DHD_TIMESYNC
++	dhd_timesync_notify_ipc_rev(dhd->ts, prot->active_ipc_version);
++#endif /* DHD_TIMESYNC */
++}
++
++/**
++ * dhd_prot_init - second stage of dhd_prot_attach. Now that the dongle has
++ * completed it's initialization of the pcie_shared structure, we may now fetch
++ * the dongle advertized features and adjust the protocol layer accordingly.
++ *
++ * dhd_prot_init() may be invoked again after a dhd_prot_reset().
++ */
++int
++dhd_prot_init(dhd_pub_t *dhd)
++{
++	sh_addr_t base_addr;
++	dhd_prot_t *prot = dhd->prot;
++	int ret = 0;
++
++	/**
++	 * A user defined value can be assigned to global variable h2d_max_txpost via
++	 * 1. DHD IOVAR h2d_max_txpost, before firmware download
++	 * 2. module parameter h2d_max_txpost
++	 * prot->h2d_max_txpost is assigned with H2DRING_TXPOST_MAX_ITEM,
++	 * if user has not defined any buffers by one of the above methods.
++	 */
++	prot->h2d_max_txpost = (uint16)h2d_max_txpost;
++
++	DHD_ERROR(("%s:%d: h2d_max_txpost = %d\n", __FUNCTION__, __LINE__, prot->h2d_max_txpost));
++
++	/* Read max rx packets supported by dongle */
++	dhd_bus_cmn_readshared(dhd->bus, &prot->max_rxbufpost, MAX_HOST_RXBUFS, 0);
++	if (prot->max_rxbufpost == 0) {
++		/* This would happen if the dongle firmware is not */
++		/* using the latest shared structure template */
++		prot->max_rxbufpost = DEFAULT_RX_BUFFERS_TO_POST;
++	}
++	DHD_INFO(("%s:%d: MAX_RXBUFPOST = %d\n", __FUNCTION__, __LINE__, prot->max_rxbufpost));
++
++	/* Initialize.  bzero() would blow away the dma pointers. */
++	prot->max_eventbufpost = DHD_FLOWRING_MAX_EVENTBUF_POST;
++	prot->max_ioctlrespbufpost = DHD_FLOWRING_MAX_IOCTLRESPBUF_POST;
++	prot->max_infobufpost = DHD_H2D_INFORING_MAX_BUF_POST;
++	prot->max_tsbufpost = DHD_MAX_TSBUF_POST;
++
++	prot->cur_ioctlresp_bufs_posted = 0;
++	prot->active_tx_count = 0;
++	prot->data_seq_no = 0;
++	prot->ioctl_seq_no = 0;
++	prot->rxbufpost = 0;
++	prot->cur_event_bufs_posted = 0;
++	prot->ioctl_state = 0;
++	prot->curr_ioctl_cmd = 0;
++	prot->cur_ts_bufs_posted = 0;
++	prot->infobufpost = 0;
++
++	prot->dmaxfer.srcmem.va = NULL;
++	prot->dmaxfer.dstmem.va = NULL;
++	prot->dmaxfer.in_progress = FALSE;
++
++	prot->metadata_dbg = FALSE;
++	prot->rx_metadata_offset = 0;
++	prot->tx_metadata_offset = 0;
++	prot->txp_threshold = TXP_FLUSH_MAX_ITEMS_FLUSH_CNT;
++
++	/* To catch any rollover issues fast, starting with higher ioctl_trans_id */
++	prot->ioctl_trans_id = MAXBITVAL(NBITS(prot->ioctl_trans_id)) - BUFFER_BEFORE_ROLLOVER;
++	prot->ioctl_state = 0;
++	prot->ioctl_status = 0;
++	prot->ioctl_resplen = 0;
++	prot->ioctl_received = IOCTL_WAIT;
++
++	/* Register the interrupt function upfront */
++	/* remove corerev checks in data path */
++	prot->mb_ring_fn = dhd_bus_get_mbintr_fn(dhd->bus);
++
++	prot->mb_2_ring_fn = dhd_bus_get_mbintr_2_fn(dhd->bus);
++
++	/* Initialize Common MsgBuf Rings */
++
++	prot->device_ipc_version = dhd->bus->api.fw_rev;
++	prot->host_ipc_version = PCIE_SHARED_VERSION;
++
++	/* Init the host API version */
++	dhd_set_host_cap(dhd);
++
++	dhd_prot_ring_init(dhd, &prot->h2dring_ctrl_subn);
++	dhd_prot_ring_init(dhd, &prot->h2dring_rxp_subn);
++	dhd_prot_ring_init(dhd, &prot->d2hring_ctrl_cpln);
++
++	/* Make it compatibile with pre-rev7 Firmware */
++	if (prot->active_ipc_version < PCIE_SHARED_VERSION_7) {
++		prot->d2hring_tx_cpln.item_len =
++			D2HRING_TXCMPLT_ITEMSIZE_PREREV7;
++		prot->d2hring_rx_cpln.item_len =
++			D2HRING_RXCMPLT_ITEMSIZE_PREREV7;
++	}
++	dhd_prot_ring_init(dhd, &prot->d2hring_tx_cpln);
++	dhd_prot_ring_init(dhd, &prot->d2hring_rx_cpln);
++
++	dhd_prot_d2h_sync_init(dhd);
++
++	dhd_prot_h2d_sync_init(dhd);
++
++#ifdef PCIE_INB_DW
++	/* Set the initial DS state */
++	if (INBAND_DW_ENAB(dhd->bus)) {
++		dhdpcie_bus_set_pcie_inband_dw_state(dhd->bus,
++			DW_DEVICE_DS_ACTIVE);
++	}
++#endif /* PCIE_INB_DW */
++
++	/* init the scratch buffer */
++	dhd_base_addr_htolpa(&base_addr, prot->d2h_dma_scratch_buf.pa);
++	dhd_bus_cmn_writeshared(dhd->bus, &base_addr, sizeof(base_addr),
++		D2H_DMA_SCRATCH_BUF, 0);
++	dhd_bus_cmn_writeshared(dhd->bus, &prot->d2h_dma_scratch_buf.len,
++		sizeof(prot->d2h_dma_scratch_buf.len), D2H_DMA_SCRATCH_BUF_LEN, 0);
++
++	/* If supported by the host, indicate the memory block
++	 * for completion writes / submission reads to shared space
++	 */
++	if (dhd->dma_d2h_ring_upd_support) {
++		dhd_base_addr_htolpa(&base_addr, prot->d2h_dma_indx_wr_buf.pa);
++		dhd_bus_cmn_writeshared(dhd->bus, &base_addr, sizeof(base_addr),
++			D2H_DMA_INDX_WR_BUF, 0);
++		dhd_base_addr_htolpa(&base_addr, prot->h2d_dma_indx_rd_buf.pa);
++		dhd_bus_cmn_writeshared(dhd->bus, &base_addr, sizeof(base_addr),
++			H2D_DMA_INDX_RD_BUF, 0);
++	}
++
++	if (dhd->dma_h2d_ring_upd_support || IDMA_ENAB(dhd)) {
++		dhd_base_addr_htolpa(&base_addr, prot->h2d_dma_indx_wr_buf.pa);
++		dhd_bus_cmn_writeshared(dhd->bus, &base_addr, sizeof(base_addr),
++			H2D_DMA_INDX_WR_BUF, 0);
++		dhd_base_addr_htolpa(&base_addr, prot->d2h_dma_indx_rd_buf.pa);
++		dhd_bus_cmn_writeshared(dhd->bus, &base_addr, sizeof(base_addr),
++			D2H_DMA_INDX_RD_BUF, 0);
++
++	}
++
++	/* Signal to the dongle that common ring init is complete */
++	dhd_bus_hostready(dhd->bus);
++
++	/*
++	 * If the DMA-able buffers for flowring needs to come from a specific
++	 * contiguous memory region, then setup prot->flowrings_dma_buf here.
++	 * dhd_prot_flowrings_pool_attach() will carve out DMA-able buffers from
++	 * this contiguous memory region, for each of the flowrings.
++	 */
++
++	/* Pre-allocate pool of msgbuf_ring for flowrings */
++	if (dhd_prot_flowrings_pool_attach(dhd) != BCME_OK) {
++		return BCME_ERROR;
++	}
++
++	/* If IFRM is enabled, wait for FW to setup the DMA channel */
++	if (IFRM_ENAB(dhd)) {
++		dhd_base_addr_htolpa(&base_addr, prot->h2d_ifrm_indx_wr_buf.pa);
++		dhd_bus_cmn_writeshared(dhd->bus, &base_addr, sizeof(base_addr),
++			H2D_IFRM_INDX_WR_BUF, 0);
++	}
++
++	/* See if info rings could be created */
++	if (dhd->bus->api.fw_rev >= PCIE_SHARED_VERSION_6) {
++		if ((ret = dhd_prot_init_info_rings(dhd)) != BCME_OK) {
++			/* For now log and proceed, further clean up action maybe necessary
++			 * when we have more clarity.
++			 */
++			DHD_ERROR(("%s Info rings couldn't be created: Err Code%d",
++				__FUNCTION__, ret));
++		}
++	}
++
++	/* Host should configure soft doorbells if needed ... here */
++
++	/* Post to dongle host configured soft doorbells */
++	dhd_msgbuf_ring_config_d2h_soft_doorbell(dhd);
++
++	/* Post buffers for packet reception and ioctl/event responses */
++	dhd_msgbuf_rxbuf_post(dhd, FALSE); /* alloc pkt ids */
++	dhd_msgbuf_rxbuf_post_ioctlresp_bufs(dhd);
++	/* Fix re-entry problem without general lock */
++	atomic_set(&dhd_msgbuf_rxbuf_post_event_bufs_running, 0);
++	dhd_msgbuf_rxbuf_post_event_bufs(dhd);
++
++	return BCME_OK;
++} /* dhd_prot_init */
++
++
++/**
++ * dhd_prot_detach - PCIE FD protocol layer destructor.
++ * Unlink, frees allocated protocol memory (including dhd_prot)
++ */
++void dhd_prot_detach(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++
++	/* Stop the protocol module */
++	if (prot) {
++
++		/* free up all DMA-able buffers allocated during prot attach/init */
++
++		dhd_dma_buf_free(dhd, &prot->d2h_dma_scratch_buf);
++		dhd_dma_buf_free(dhd, &prot->retbuf);
++		dhd_dma_buf_free(dhd, &prot->ioctbuf);
++		dhd_dma_buf_free(dhd, &prot->host_bus_throughput_buf);
++		dhd_dma_buf_free(dhd, &prot->hostts_req_buf);
++		dhd_dma_buf_free(dhd, &prot->fw_trap_buf);
++
++		/* DMA-able buffers for DMAing H2D/D2H WR/RD indices */
++		dhd_dma_buf_free(dhd, &prot->h2d_dma_indx_wr_buf);
++		dhd_dma_buf_free(dhd, &prot->h2d_dma_indx_rd_buf);
++		dhd_dma_buf_free(dhd, &prot->d2h_dma_indx_wr_buf);
++		dhd_dma_buf_free(dhd, &prot->d2h_dma_indx_rd_buf);
++
++		dhd_dma_buf_free(dhd, &prot->h2d_ifrm_indx_wr_buf);
++
++		/* Common MsgBuf Rings */
++		dhd_prot_ring_detach(dhd, &prot->h2dring_ctrl_subn);
++		dhd_prot_ring_detach(dhd, &prot->h2dring_rxp_subn);
++		dhd_prot_ring_detach(dhd, &prot->d2hring_ctrl_cpln);
++		dhd_prot_ring_detach(dhd, &prot->d2hring_tx_cpln);
++		dhd_prot_ring_detach(dhd, &prot->d2hring_rx_cpln);
++
++		/* Detach each DMA-able buffer and free the pool of msgbuf_ring_t */
++		dhd_prot_flowrings_pool_detach(dhd);
++
++		/* detach info rings */
++		dhd_prot_detach_info_rings(dhd);
++
++		/* if IOCTLRESP_USE_CONSTMEM is defined IOCTL PKTs use pktid_map_handle_ioctl
++		 * handler and PKT memory is allocated using alloc_ioctl_return_buffer(), Otherwise
++		 * they will be part of pktid_ctrl_map handler and PKT memory is allocated using
++		 * PKTGET_STATIC (if DHD_USE_STATIC_CTRLBUF is defined) OR PKGET.
++		 * Similarly for freeing PKT buffers DHD_NATIVE_TO_PKTID_FINI will be used
++		 * which calls PKTFREE_STATIC (if DHD_USE_STATIC_CTRLBUF is defined) OR PKFREE.
++		 * Else if IOCTLRESP_USE_CONSTMEM is defined IOCTL PKTs will be freed using
++		 * DHD_NATIVE_TO_PKTID_FINI_IOCTL which calls free_ioctl_return_buffer.
++		 */
++		DHD_NATIVE_TO_PKTID_FINI(dhd, prot->pktid_ctrl_map);
++		DHD_NATIVE_TO_PKTID_FINI(dhd, prot->pktid_rx_map);
++		DHD_NATIVE_TO_PKTID_FINI(dhd, prot->pktid_tx_map);
++#ifdef IOCTLRESP_USE_CONSTMEM
++		DHD_NATIVE_TO_PKTID_FINI_IOCTL(dhd, prot->pktid_map_handle_ioctl);
++#endif
++
++		dhd_os_spin_lock_deinit(dhd->osh, prot->rx_lock);
++
++#ifndef CONFIG_DHD_USE_STATIC_BUF
++		MFREE(dhd->osh, dhd->prot, sizeof(dhd_prot_t));
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++
++#if defined(DHD_LB_TXC)
++		if (prot->tx_compl_prod.buffer)
++			MFREE(dhd->osh, prot->tx_compl_prod.buffer,
++			      sizeof(void*) * DHD_LB_WORKQ_SZ);
++#endif /* DHD_LB_TXC */
++#if defined(DHD_LB_RXC)
++		if (prot->rx_compl_prod.buffer)
++			MFREE(dhd->osh, prot->rx_compl_prod.buffer,
++			      sizeof(void*) * DHD_LB_WORKQ_SZ);
++#endif /* DHD_LB_RXC */
++
++		dhd->prot = NULL;
++	}
++} /* dhd_prot_detach */
++
++
++/**
++ * dhd_prot_reset - Reset the protocol layer without freeing any objects.
++ * This may be invoked to soft reboot the dongle, without having to
++ * detach and attach the entire protocol layer.
++ *
++ * After dhd_prot_reset(), dhd_prot_init() may be invoked
++ * without going througha dhd_prot_attach() phase.
++ */
++void
++dhd_prot_reset(dhd_pub_t *dhd)
++{
++	struct dhd_prot *prot = dhd->prot;
++
++	DHD_TRACE(("%s\n", __FUNCTION__));
++
++	if (prot == NULL) {
++		return;
++	}
++
++	dhd_prot_flowrings_pool_reset(dhd);
++
++	/* Reset Common MsgBuf Rings */
++	dhd_prot_ring_reset(dhd, &prot->h2dring_ctrl_subn);
++	dhd_prot_ring_reset(dhd, &prot->h2dring_rxp_subn);
++	dhd_prot_ring_reset(dhd, &prot->d2hring_ctrl_cpln);
++	dhd_prot_ring_reset(dhd, &prot->d2hring_tx_cpln);
++	dhd_prot_ring_reset(dhd, &prot->d2hring_rx_cpln);
++
++	/* Reset info rings */
++	if (prot->h2dring_info_subn) {
++		dhd_prot_ring_reset(dhd, prot->h2dring_info_subn);
++	}
++
++	if (prot->d2hring_info_cpln) {
++		dhd_prot_ring_reset(dhd, prot->d2hring_info_cpln);
++	}
++
++	/* Reset all DMA-able buffers allocated during prot attach */
++	dhd_dma_buf_reset(dhd, &prot->d2h_dma_scratch_buf);
++	dhd_dma_buf_reset(dhd, &prot->retbuf);
++	dhd_dma_buf_reset(dhd, &prot->ioctbuf);
++	dhd_dma_buf_reset(dhd, &prot->host_bus_throughput_buf);
++	dhd_dma_buf_reset(dhd, &prot->hostts_req_buf);
++	dhd_dma_buf_reset(dhd, &prot->fw_trap_buf);
++
++	dhd_dma_buf_reset(dhd, &prot->h2d_ifrm_indx_wr_buf);
++
++	/* Reset all DMA-able buffers for DMAing H2D/D2H WR/RD indices */
++	dhd_dma_buf_reset(dhd, &prot->h2d_dma_indx_rd_buf);
++	dhd_dma_buf_reset(dhd, &prot->h2d_dma_indx_wr_buf);
++	dhd_dma_buf_reset(dhd, &prot->d2h_dma_indx_rd_buf);
++	dhd_dma_buf_reset(dhd, &prot->d2h_dma_indx_wr_buf);
++
++
++	prot->rx_metadata_offset = 0;
++	prot->tx_metadata_offset = 0;
++
++	prot->rxbufpost = 0;
++	prot->cur_event_bufs_posted = 0;
++	prot->cur_ioctlresp_bufs_posted = 0;
++
++	prot->active_tx_count = 0;
++	prot->data_seq_no = 0;
++	prot->ioctl_seq_no = 0;
++	prot->ioctl_state = 0;
++	prot->curr_ioctl_cmd = 0;
++	prot->ioctl_received = IOCTL_WAIT;
++	/* To catch any rollover issues fast, starting with higher ioctl_trans_id */
++	prot->ioctl_trans_id = MAXBITVAL(NBITS(prot->ioctl_trans_id)) - BUFFER_BEFORE_ROLLOVER;
++
++	/* dhd_flow_rings_init is located at dhd_bus_start,
++	 * so when stopping bus, flowrings shall be deleted
++	 */
++	if (dhd->flow_rings_inited) {
++		dhd_flow_rings_deinit(dhd);
++	}
++
++	/* Reset PKTID map */
++	DHD_NATIVE_TO_PKTID_RESET(dhd, prot->pktid_ctrl_map);
++	DHD_NATIVE_TO_PKTID_RESET(dhd, prot->pktid_rx_map);
++	DHD_NATIVE_TO_PKTID_RESET(dhd, prot->pktid_tx_map);
++#ifdef IOCTLRESP_USE_CONSTMEM
++	DHD_NATIVE_TO_PKTID_RESET_IOCTL(dhd, prot->pktid_map_handle_ioctl);
++#endif /* IOCTLRESP_USE_CONSTMEM */
++#ifdef DMAMAP_STATS
++	dhd->dma_stats.txdata = dhd->dma_stats.txdata_sz = 0;
++	dhd->dma_stats.rxdata = dhd->dma_stats.rxdata_sz = 0;
++#ifndef IOCTLRESP_USE_CONSTMEM
++	dhd->dma_stats.ioctl_rx = dhd->dma_stats.ioctl_rx_sz = 0;
++#endif /* IOCTLRESP_USE_CONSTMEM */
++	dhd->dma_stats.event_rx = dhd->dma_stats.event_rx_sz = 0;
++	dhd->dma_stats.info_rx = dhd->dma_stats.info_rx_sz = 0;
++	dhd->dma_stats.tsbuf_rx = dhd->dma_stats.tsbuf_rx_sz = 0;
++#endif /* DMAMAP_STATS */
++} /* dhd_prot_reset */
++
++#if defined(DHD_LB_RXP)
++#define DHD_LB_DISPATCH_RX_PROCESS(dhdp)	dhd_lb_dispatch_rx_process(dhdp)
++#else /* !DHD_LB_RXP */
++#define DHD_LB_DISPATCH_RX_PROCESS(dhdp)	do { /* noop */ } while (0)
++#endif /* !DHD_LB_RXP */
++
++#if defined(DHD_LB_RXC)
++#define DHD_LB_DISPATCH_RX_COMPL(dhdp)	dhd_lb_dispatch_rx_compl(dhdp)
++#else /* !DHD_LB_RXC */
++#define DHD_LB_DISPATCH_RX_COMPL(dhdp)	do { /* noop */ } while (0)
++#endif /* !DHD_LB_RXC */
++
++#if defined(DHD_LB_TXC)
++#define DHD_LB_DISPATCH_TX_COMPL(dhdp)	dhd_lb_dispatch_tx_compl(dhdp)
++#else /* !DHD_LB_TXC */
++#define DHD_LB_DISPATCH_TX_COMPL(dhdp)	do { /* noop */ } while (0)
++#endif /* !DHD_LB_TXC */
++
++
++#if defined(DHD_LB)
++/* DHD load balancing: deferral of work to another online CPU */
++/* DHD_LB_TXC DHD_LB_RXC DHD_LB_RXP dispatchers, in dhd_linux.c */
++extern void dhd_lb_tx_compl_dispatch(dhd_pub_t *dhdp);
++extern void dhd_lb_rx_compl_dispatch(dhd_pub_t *dhdp);
++extern void dhd_lb_rx_napi_dispatch(dhd_pub_t *dhdp);
++extern void dhd_lb_rx_pkt_enqueue(dhd_pub_t *dhdp, void *pkt, int ifidx);
++
++#if defined(DHD_LB_RXP)
++/**
++ * dhd_lb_dispatch_rx_process - load balance by dispatch Rx processing work
++ * to other CPU cores
++ */
++static INLINE void
++dhd_lb_dispatch_rx_process(dhd_pub_t *dhdp)
++{
++	dhd_lb_rx_napi_dispatch(dhdp); /* dispatch rx_process_napi */
++}
++#endif /* DHD_LB_RXP */
++
++#if defined(DHD_LB_TXC)
++/**
++ * dhd_lb_dispatch_tx_compl - load balance by dispatch Tx complition work
++ * to other CPU cores
++ */
++static INLINE void
++dhd_lb_dispatch_tx_compl(dhd_pub_t *dhdp, uint16 ring_idx)
++{
++	bcm_workq_prod_sync(&dhdp->prot->tx_compl_prod); /* flush WR index */
++	dhd_lb_tx_compl_dispatch(dhdp); /* dispatch tx_compl_tasklet */
++}
++
++/**
++ * DHD load balanced tx completion tasklet handler, that will perform the
++ * freeing of packets on the selected CPU. Packet pointers are delivered to
++ * this tasklet via the tx complete workq.
++ */
++void
++dhd_lb_tx_compl_handler(unsigned long data)
++{
++	int elem_ix;
++	void *pkt, **elem;
++	dmaaddr_t pa;
++	uint32 pa_len;
++	dhd_pub_t *dhd = (dhd_pub_t *)data;
++	dhd_prot_t *prot = dhd->prot;
++	bcm_workq_t *workq = &prot->tx_compl_cons;
++	uint32 count = 0;
++
++	int curr_cpu;
++	curr_cpu = get_cpu();
++	put_cpu();
++
++	DHD_LB_STATS_TXC_PERCPU_CNT_INCR(dhd);
++
++	while (1) {
++		elem_ix = bcm_ring_cons(WORKQ_RING(workq), DHD_LB_WORKQ_SZ);
++
++		if (elem_ix == BCM_RING_EMPTY) {
++			break;
++		}
++
++		elem = WORKQ_ELEMENT(void *, workq, elem_ix);
++		pkt = *elem;
++
++		DHD_INFO(("%s: tx_compl_cons pkt<%p>\n", __FUNCTION__, pkt));
++
++		OSL_PREFETCH(PKTTAG(pkt));
++		OSL_PREFETCH(pkt);
++
++		pa = DHD_PKTTAG_PA((dhd_pkttag_fr_t *)PKTTAG(pkt));
++		pa_len = DHD_PKTTAG_PA_LEN((dhd_pkttag_fr_t *)PKTTAG(pkt));
++
++		DMA_UNMAP(dhd->osh, pa, pa_len, DMA_RX, 0, 0);
++#if defined(BCMPCIE)
++		dhd_txcomplete(dhd, pkt, true);
++#endif 
++
++		PKTFREE(dhd->osh, pkt, TRUE);
++		count++;
++	}
++
++	/* smp_wmb(); */
++	bcm_workq_cons_sync(workq);
++	DHD_LB_STATS_UPDATE_TXC_HISTO(dhd, count);
++}
++#endif /* DHD_LB_TXC */
++
++#if defined(DHD_LB_RXC)
++
++/**
++ * dhd_lb_dispatch_rx_compl - load balance by dispatch rx complition work
++ * to other CPU cores
++ */
++static INLINE void
++dhd_lb_dispatch_rx_compl(dhd_pub_t *dhdp)
++{
++	dhd_prot_t *prot = dhdp->prot;
++	/* Schedule the takslet only if we have to */
++	if (prot->rxbufpost <= (prot->max_rxbufpost - RXBUFPOST_THRESHOLD)) {
++		/* flush WR index */
++		bcm_workq_prod_sync(&dhdp->prot->rx_compl_prod);
++		dhd_lb_rx_compl_dispatch(dhdp); /* dispatch rx_compl_tasklet */
++	}
++}
++
++void
++dhd_lb_rx_compl_handler(unsigned long data)
++{
++	dhd_pub_t *dhd = (dhd_pub_t *)data;
++	bcm_workq_t *workq = &dhd->prot->rx_compl_cons;
++
++	DHD_LB_STATS_RXC_PERCPU_CNT_INCR(dhd);
++
++	dhd_msgbuf_rxbuf_post(dhd, TRUE); /* re-use pktids */
++	bcm_workq_cons_sync(workq);
++}
++#endif /* DHD_LB_RXC */
++#endif /* DHD_LB */
++
++void
++dhd_prot_rx_dataoffset(dhd_pub_t *dhd, uint32 rx_offset)
++{
++	dhd_prot_t *prot = dhd->prot;
++	prot->rx_dataoffset = rx_offset;
++}
++
++static int
++dhd_check_create_info_rings(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	int ret = BCME_ERROR;
++	uint16 ringid = dhd->bus->max_tx_flowrings + BCMPCIE_COMMON_MSGRINGS;
++
++	if (prot->h2dring_info_subn && prot->d2hring_info_cpln) {
++		return BCME_OK; /* dhd_prot_init rentry after a dhd_prot_reset */
++	}
++
++	if (prot->h2dring_info_subn == NULL) {
++		prot->h2dring_info_subn = MALLOCZ(prot->osh, sizeof(msgbuf_ring_t));
++
++		if (prot->h2dring_info_subn == NULL) {
++			DHD_ERROR(("%s: couldn't alloc memory for h2dring_info_subn\n",
++				__FUNCTION__));
++			return BCME_NOMEM;
++		}
++
++		DHD_INFO(("%s: about to create debug submit ring\n", __FUNCTION__));
++		ret = dhd_prot_ring_attach(dhd, prot->h2dring_info_subn, "h2dinfo",
++			H2DRING_DYNAMIC_INFO_MAX_ITEM, H2DRING_INFO_BUFPOST_ITEMSIZE,
++			ringid);
++		if (ret != BCME_OK) {
++			DHD_ERROR(("%s: couldn't alloc resources for dbg submit ring\n",
++				__FUNCTION__));
++			goto err;
++		}
++	}
++
++	if (prot->d2hring_info_cpln == NULL) {
++		prot->d2hring_info_cpln = MALLOCZ(prot->osh, sizeof(msgbuf_ring_t));
++
++		if (prot->d2hring_info_cpln == NULL) {
++			DHD_ERROR(("%s: couldn't alloc memory for h2dring_info_subn\n",
++				__FUNCTION__));
++			return BCME_NOMEM;
++		}
++
++		/* create the debug info completion ring next to debug info submit ring
++		* ringid = id next to debug info submit ring
++		*/
++		ringid = ringid + 1;
++
++		DHD_INFO(("%s: about to create debug cpl ring\n", __FUNCTION__));
++		ret = dhd_prot_ring_attach(dhd, prot->d2hring_info_cpln, "d2hinfo",
++			D2HRING_DYNAMIC_INFO_MAX_ITEM, D2HRING_INFO_BUFCMPLT_ITEMSIZE,
++			ringid);
++		if (ret != BCME_OK) {
++			DHD_ERROR(("%s: couldn't alloc resources for dbg cpl ring\n",
++				__FUNCTION__));
++			dhd_prot_ring_detach(dhd, prot->h2dring_info_subn);
++			goto err;
++		}
++	}
++
++	return ret;
++err:
++	MFREE(prot->osh, prot->h2dring_info_subn, sizeof(msgbuf_ring_t));
++	prot->h2dring_info_subn = NULL;
++
++	if (prot->d2hring_info_cpln) {
++		MFREE(prot->osh, prot->d2hring_info_cpln, sizeof(msgbuf_ring_t));
++		prot->d2hring_info_cpln = NULL;
++	}
++	return ret;
++} /* dhd_check_create_info_rings */
++
++int
++dhd_prot_init_info_rings(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	int ret = BCME_OK;
++
++	if ((ret = dhd_check_create_info_rings(dhd)) != BCME_OK) {
++		DHD_ERROR(("%s: info rings aren't created! \n",
++			__FUNCTION__));
++		return ret;
++	}
++
++	if ((prot->d2hring_info_cpln->inited) || (prot->d2hring_info_cpln->create_pending)) {
++		DHD_INFO(("Info completion ring was created!\n"));
++		return ret;
++	}
++
++	DHD_TRACE(("trying to send create d2h info ring: id %d\n", prot->d2hring_info_cpln->idx));
++	ret = dhd_send_d2h_ringcreate(dhd, prot->d2hring_info_cpln);
++	if (ret != BCME_OK)
++		return ret;
++
++	prot->d2hring_info_cpln->seqnum = D2H_EPOCH_INIT_VAL;
++
++	DHD_TRACE(("trying to send create h2d info ring id %d\n", prot->h2dring_info_subn->idx));
++	prot->h2dring_info_subn->n_completion_ids = 1;
++	prot->h2dring_info_subn->compeltion_ring_ids[0] = prot->d2hring_info_cpln->idx;
++
++	ret = dhd_send_h2d_ringcreate(dhd, prot->h2dring_info_subn);
++
++	/* Note that there is no way to delete d2h or h2d ring deletion incase either fails,
++	 * so can not cleanup if one ring was created while the other failed
++	 */
++	return ret;
++} /* dhd_prot_init_info_rings */
++
++static void
++dhd_prot_detach_info_rings(dhd_pub_t *dhd)
++{
++	if (dhd->prot->h2dring_info_subn) {
++		dhd_prot_ring_detach(dhd, dhd->prot->h2dring_info_subn);
++		MFREE(dhd->prot->osh, dhd->prot->h2dring_info_subn, sizeof(msgbuf_ring_t));
++		dhd->prot->h2dring_info_subn = NULL;
++	}
++	if (dhd->prot->d2hring_info_cpln) {
++		dhd_prot_ring_detach(dhd, dhd->prot->d2hring_info_cpln);
++		MFREE(dhd->prot->osh, dhd->prot->d2hring_info_cpln, sizeof(msgbuf_ring_t));
++		dhd->prot->d2hring_info_cpln = NULL;
++	}
++}
++
++/**
++ * Initialize protocol: sync w/dongle state.
++ * Sets dongle media info (iswl, drv_version, mac address).
++ */
++int dhd_sync_with_dongle(dhd_pub_t *dhd)
++{
++	int ret = 0;
++	wlc_rev_info_t revinfo;
++
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	dhd_os_set_ioctl_resp_timeout(IOCTL_RESP_TIMEOUT);
++
++	/* Post ts buffer after shim layer is attached */
++	ret = dhd_msgbuf_rxbuf_post_ts_bufs(dhd);
++
++
++#ifdef DHD_FW_COREDUMP
++	/* Check the memdump capability */
++	dhd_get_memdump_info(dhd);
++#endif /* DHD_FW_COREDUMP */
++#ifdef BCMASSERT_LOG
++	dhd_get_assert_info(dhd);
++#endif /* BCMASSERT_LOG */
++
++	/* Get the device rev info */
++	memset(&revinfo, 0, sizeof(revinfo));
++	ret = dhd_wl_ioctl_cmd(dhd, WLC_GET_REVINFO, &revinfo, sizeof(revinfo), FALSE, 0);
++	if (ret < 0) {
++		DHD_ERROR(("%s: GET revinfo FAILED\n", __FUNCTION__));
++		goto done;
++	}
++	DHD_ERROR(("%s: GET_REVINFO device 0x%x, vendor 0x%x, chipnum 0x%x\n", __FUNCTION__,
++		revinfo.deviceid, revinfo.vendorid, revinfo.chipnum));
++
++	DHD_SSSR_DUMP_INIT(dhd);
++
++	dhd_process_cid_mac(dhd, TRUE);
++	ret = dhd_preinit_ioctls(dhd);
++	dhd_process_cid_mac(dhd, FALSE);
++
++	/* Always assumes wl for now */
++	dhd->iswl = TRUE;
++done:
++	return ret;
++} /* dhd_sync_with_dongle */
++
++
++#define DHD_DBG_SHOW_METADATA	0
++
++#if DHD_DBG_SHOW_METADATA
++static void BCMFASTPATH
++dhd_prot_print_metadata(dhd_pub_t *dhd, void *ptr, int len)
++{
++	uint8 tlv_t;
++	uint8 tlv_l;
++	uint8 *tlv_v = (uint8 *)ptr;
++
++	if (len <= BCMPCIE_D2H_METADATA_HDRLEN)
++		return;
++
++	len -= BCMPCIE_D2H_METADATA_HDRLEN;
++	tlv_v += BCMPCIE_D2H_METADATA_HDRLEN;
++
++	while (len > TLV_HDR_LEN) {
++		tlv_t = tlv_v[TLV_TAG_OFF];
++		tlv_l = tlv_v[TLV_LEN_OFF];
++
++		len -= TLV_HDR_LEN;
++		tlv_v += TLV_HDR_LEN;
++		if (len < tlv_l)
++			break;
++		if ((tlv_t == 0) || (tlv_t == WLFC_CTL_TYPE_FILLER))
++			break;
++
++		switch (tlv_t) {
++		case WLFC_CTL_TYPE_TXSTATUS: {
++			uint32 txs;
++			memcpy(&txs, tlv_v, sizeof(uint32));
++			if (tlv_l < (sizeof(wl_txstatus_additional_info_t) + sizeof(uint32))) {
++				printf("METADATA TX_STATUS: %08x\n", txs);
++			} else {
++				wl_txstatus_additional_info_t tx_add_info;
++				memcpy(&tx_add_info, tlv_v + sizeof(uint32),
++					sizeof(wl_txstatus_additional_info_t));
++				printf("METADATA TX_STATUS: %08x WLFCTS[%04x | %08x - %08x - %08x]"
++					" rate = %08x tries = %d - %d\n", txs,
++					tx_add_info.seq, tx_add_info.entry_ts,
++					tx_add_info.enq_ts, tx_add_info.last_ts,
++					tx_add_info.rspec, tx_add_info.rts_cnt,
++					tx_add_info.tx_cnt);
++			}
++			} break;
++
++		case WLFC_CTL_TYPE_RSSI: {
++			if (tlv_l == 1)
++				printf("METADATA RX_RSSI: rssi = %d\n", *tlv_v);
++			else
++				printf("METADATA RX_RSSI[%04x]: rssi = %d snr = %d\n",
++					(*(tlv_v + 3) << 8) | *(tlv_v + 2),
++					(int8)(*tlv_v), *(tlv_v + 1));
++			} break;
++
++		case WLFC_CTL_TYPE_FIFO_CREDITBACK:
++			bcm_print_bytes("METADATA FIFO_CREDITBACK", tlv_v, tlv_l);
++			break;
++
++		case WLFC_CTL_TYPE_TX_ENTRY_STAMP:
++			bcm_print_bytes("METADATA TX_ENTRY", tlv_v, tlv_l);
++			break;
++
++		case WLFC_CTL_TYPE_RX_STAMP: {
++			struct {
++				uint32 rspec;
++				uint32 bus_time;
++				uint32 wlan_time;
++			} rx_tmstamp;
++			memcpy(&rx_tmstamp, tlv_v, sizeof(rx_tmstamp));
++			printf("METADATA RX TIMESTMAP: WLFCTS[%08x - %08x] rate = %08x\n",
++				rx_tmstamp.wlan_time, rx_tmstamp.bus_time, rx_tmstamp.rspec);
++			} break;
++
++		case WLFC_CTL_TYPE_TRANS_ID:
++			bcm_print_bytes("METADATA TRANS_ID", tlv_v, tlv_l);
++			break;
++
++		case WLFC_CTL_TYPE_COMP_TXSTATUS:
++			bcm_print_bytes("METADATA COMP_TXSTATUS", tlv_v, tlv_l);
++			break;
++
++		default:
++			bcm_print_bytes("METADATA UNKNOWN", tlv_v, tlv_l);
++			break;
++		}
++
++		len -= tlv_l;
++		tlv_v += tlv_l;
++	}
++}
++#endif /* DHD_DBG_SHOW_METADATA */
++
++static INLINE void BCMFASTPATH
++dhd_prot_packet_free(dhd_pub_t *dhd, void *pkt, uint8 pkttype, bool send)
++{
++	if (pkt) {
++		if (pkttype == PKTTYPE_IOCTL_RX ||
++			pkttype == PKTTYPE_EVENT_RX ||
++			pkttype == PKTTYPE_INFO_RX ||
++			pkttype == PKTTYPE_TSBUF_RX) {
++#ifdef DHD_USE_STATIC_CTRLBUF
++			PKTFREE_STATIC(dhd->osh, pkt, send);
++#else
++			PKTFREE(dhd->osh, pkt, send);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++		} else {
++			PKTFREE(dhd->osh, pkt, send);
++		}
++	}
++}
++
++/* dhd_prot_packet_get should be called only for items having pktid_ctrl_map handle */
++static INLINE void * BCMFASTPATH
++dhd_prot_packet_get(dhd_pub_t *dhd, uint32 pktid, uint8 pkttype, bool free_pktid)
++{
++	void *PKTBUF;
++	dmaaddr_t pa;
++	uint32 len;
++	void *dmah;
++	void *secdma;
++
++#ifdef DHD_PCIE_PKTID
++	if (free_pktid) {
++		PKTBUF = DHD_PKTID_TO_NATIVE(dhd, dhd->prot->pktid_ctrl_map,
++			pktid, pa, len, dmah, secdma, pkttype);
++	} else {
++		PKTBUF = DHD_PKTID_TO_NATIVE_RSV(dhd, dhd->prot->pktid_ctrl_map,
++			pktid, pa, len, dmah, secdma, pkttype);
++	}
++#else
++	PKTBUF = DHD_PKTID_TO_NATIVE(dhd, dhd->prot->pktid_ctrl_map, pktid, pa,
++		len, dmah, secdma, pkttype);
++#endif /* DHD_PCIE_PKTID */
++	if (PKTBUF) {
++		{
++			if (SECURE_DMA_ENAB(dhd->osh))
++				SECURE_DMA_UNMAP(dhd->osh, pa, (uint) len, DMA_RX, 0, dmah,
++					secdma, 0);
++			else
++				DMA_UNMAP(dhd->osh, pa, (uint) len, DMA_RX, 0, dmah);
++#ifdef DMAMAP_STATS
++			switch (pkttype) {
++#ifndef IOCTLRESP_USE_CONSTMEM
++				case PKTTYPE_IOCTL_RX:
++					dhd->dma_stats.ioctl_rx--;
++					dhd->dma_stats.ioctl_rx_sz -= len;
++					break;
++#endif /* IOCTLRESP_USE_CONSTMEM */
++				case PKTTYPE_EVENT_RX:
++					dhd->dma_stats.event_rx--;
++					dhd->dma_stats.event_rx_sz -= len;
++					break;
++				case PKTTYPE_INFO_RX:
++					dhd->dma_stats.info_rx--;
++					dhd->dma_stats.info_rx_sz -= len;
++					break;
++				case PKTTYPE_TSBUF_RX:
++					dhd->dma_stats.tsbuf_rx--;
++					dhd->dma_stats.tsbuf_rx_sz -= len;
++					break;
++			}
++#endif /* DMAMAP_STATS */
++		}
++	}
++
++	return PKTBUF;
++}
++
++#ifdef IOCTLRESP_USE_CONSTMEM
++static INLINE void BCMFASTPATH
++dhd_prot_ioctl_ret_buffer_get(dhd_pub_t *dhd, uint32 pktid, dhd_dma_buf_t *retbuf)
++{
++	memset(retbuf, 0, sizeof(dhd_dma_buf_t));
++	retbuf->va = DHD_PKTID_TO_NATIVE(dhd, dhd->prot->pktid_map_handle_ioctl, pktid,
++		retbuf->pa, retbuf->len, retbuf->dmah, retbuf->secdma, PKTTYPE_IOCTL_RX);
++
++	return;
++}
++#endif
++
++#ifdef PCIE_INB_DW
++static int
++dhd_prot_inc_hostactive_devwake_assert(dhd_bus_t *bus)
++{
++	unsigned long flags = 0;
++
++	if (INBAND_DW_ENAB(bus)) {
++		DHD_BUS_INB_DW_LOCK(bus->inb_lock, flags);
++		bus->host_active_cnt++;
++		DHD_BUS_INB_DW_UNLOCK(bus->inb_lock, flags);
++		if (dhd_bus_set_device_wake(bus, TRUE) != BCME_OK) {
++			DHD_BUS_INB_DW_LOCK(bus->inb_lock, flags);
++			bus->host_active_cnt--;
++			dhd_bus_inb_ack_pending_ds_req(bus);
++			DHD_BUS_INB_DW_UNLOCK(bus->inb_lock, flags);
++			return BCME_ERROR;
++		}
++	}
++
++	return BCME_OK;
++}
++
++static void
++dhd_prot_dec_hostactive_ack_pending_dsreq(dhd_bus_t *bus)
++{
++	unsigned long flags = 0;
++	if (INBAND_DW_ENAB(bus)) {
++		DHD_BUS_INB_DW_LOCK(bus->inb_lock, flags);
++		bus->host_active_cnt--;
++		dhd_bus_inb_ack_pending_ds_req(bus);
++		DHD_BUS_INB_DW_UNLOCK(bus->inb_lock, flags);
++	}
++}
++#endif /* PCIE_INB_DW */
++
++static void BCMFASTPATH
++dhd_msgbuf_rxbuf_post(dhd_pub_t *dhd, bool use_rsv_pktid)
++{
++	dhd_prot_t *prot = dhd->prot;
++	int16 fillbufs;
++	uint16 cnt = 256;
++	int retcount = 0;
++
++	fillbufs = prot->max_rxbufpost - prot->rxbufpost;
++	while (fillbufs >= RX_BUF_BURST) {
++		cnt--;
++		if (cnt == 0) {
++			/* find a better way to reschedule rx buf post if space not available */
++			DHD_ERROR(("h2d rx post ring not available to post host buffers \n"));
++			DHD_ERROR(("Current posted host buf count %d \n", prot->rxbufpost));
++			break;
++		}
++
++		/* Post in a burst of 32 buffers at a time */
++		fillbufs = MIN(fillbufs, RX_BUF_BURST);
++
++		/* Post buffers */
++		retcount = dhd_prot_rxbuf_post(dhd, fillbufs, use_rsv_pktid);
++
++		if (retcount >= 0) {
++			prot->rxbufpost += (uint16)retcount;
++#ifdef DHD_LB_RXC
++			/* dhd_prot_rxbuf_post returns the number of buffers posted */
++			DHD_LB_STATS_UPDATE_RXC_HISTO(dhd, retcount);
++#endif /* DHD_LB_RXC */
++			/* how many more to post */
++			fillbufs = prot->max_rxbufpost - prot->rxbufpost;
++		} else {
++			/* Make sure we don't run loop any further */
++			fillbufs = 0;
++		}
++	}
++}
++
++/** Post 'count' no of rx buffers to dongle */
++static int BCMFASTPATH
++dhd_prot_rxbuf_post(dhd_pub_t *dhd, uint16 count, bool use_rsv_pktid)
++{
++	void *p, **pktbuf;
++	uint16 pktsz = DHD_FLOWRING_RX_BUFPOST_PKTSZ;
++	uint8 *rxbuf_post_tmp;
++	host_rxbuf_post_t *rxbuf_post;
++	void *msg_start;
++	dmaaddr_t pa, *pktbuf_pa;
++	uint32 *pktlen;
++	uint16 i = 0, alloced = 0;
++	unsigned long flags;
++	uint32 pktid;
++	dhd_prot_t *prot = dhd->prot;
++	msgbuf_ring_t *ring = &prot->h2dring_rxp_subn;
++	void *lcl_buf;
++	uint16 lcl_buf_size;
++
++#ifdef PCIE_INB_DW
++	if (dhd_prot_inc_hostactive_devwake_assert(dhd->bus) != BCME_OK)
++		return BCME_ERROR;
++#endif /* PCIE_INB_DW */
++
++	/* allocate a local buffer to store pkt buffer va, pa and length */
++	lcl_buf_size = (sizeof(void *) + sizeof(dmaaddr_t) + sizeof(uint32)) *
++		RX_BUF_BURST;
++	lcl_buf = MALLOC(dhd->osh, lcl_buf_size);
++	if (!lcl_buf) {
++		DHD_ERROR(("%s: local scratch buffer allocation failed\n", __FUNCTION__));
++#ifdef PCIE_INB_DW
++		dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++		return 0;
++	}
++	pktbuf = lcl_buf;
++	pktbuf_pa = (dmaaddr_t *)((uint8 *)pktbuf + sizeof(void *) * RX_BUF_BURST);
++	pktlen = (uint32 *)((uint8 *)pktbuf_pa + sizeof(dmaaddr_t) * RX_BUF_BURST);
++
++	for (i = 0; i < count; i++) {
++		if ((p = PKTGET(dhd->osh, pktsz, FALSE)) == NULL) {
++			DHD_ERROR(("%s:%d: PKTGET for rxbuf failed\n", __FUNCTION__, __LINE__));
++			dhd->rx_pktgetfail++;
++			break;
++		}
++
++		pktlen[i] = PKTLEN(dhd->osh, p);
++		if (SECURE_DMA_ENAB(dhd->osh)) {
++			pa = SECURE_DMA_MAP(dhd->osh, PKTDATA(dhd->osh, p), pktlen[i],
++				DMA_RX, p, 0, ring->dma_buf.secdma, 0);
++		}
++#ifndef BCM_SECURE_DMA
++		else
++			pa = DMA_MAP(dhd->osh, PKTDATA(dhd->osh, p), pktlen[i], DMA_RX, p, 0);
++#endif /* #ifndef BCM_SECURE_DMA */
++
++		if (PHYSADDRISZERO(pa)) {
++			PKTFREE(dhd->osh, p, FALSE);
++			DHD_ERROR(("Invalid phyaddr 0\n"));
++			ASSERT(0);
++			break;
++		}
++#ifdef DMAMAP_STATS
++		dhd->dma_stats.rxdata++;
++		dhd->dma_stats.rxdata_sz += pktlen[i];
++#endif /* DMAMAP_STATS */
++
++		PKTPULL(dhd->osh, p, prot->rx_metadata_offset);
++		pktlen[i] = PKTLEN(dhd->osh, p);
++		pktbuf[i] = p;
++		pktbuf_pa[i] = pa;
++	}
++
++	/* only post what we have */
++	count = i;
++
++	/* grab the rx lock to allocate pktid and post on ring */
++	DHD_SPIN_LOCK(prot->rx_lock, flags);
++
++	/* Claim space for exactly 'count' no of messages, for mitigation purpose */
++	msg_start = (void *)
++		dhd_prot_alloc_ring_space(dhd, ring, count, &alloced, TRUE);
++	if (msg_start == NULL) {
++		DHD_INFO(("%s:%d: Rxbufpost Msgbuf Not available\n", __FUNCTION__, __LINE__));
++		goto cleanup;
++	}
++	/* if msg_start !=  NULL, we should have alloced space for atleast 1 item */
++	ASSERT(alloced > 0);
++
++	rxbuf_post_tmp = (uint8*)msg_start;
++
++	for (i = 0; i < alloced; i++) {
++		rxbuf_post = (host_rxbuf_post_t *)rxbuf_post_tmp;
++		p = pktbuf[i];
++		pa = pktbuf_pa[i];
++
++#if defined(DHD_LB_RXC)
++		if (use_rsv_pktid == TRUE) {
++			bcm_workq_t *workq = &prot->rx_compl_cons;
++			int elem_ix = bcm_ring_cons(WORKQ_RING(workq), DHD_LB_WORKQ_SZ);
++
++			if (elem_ix == BCM_RING_EMPTY) {
++				DHD_INFO(("%s rx_compl_cons ring is empty\n", __FUNCTION__));
++				pktid = DHD_PKTID_INVALID;
++				goto alloc_pkt_id;
++			} else {
++				uint32 *elem = WORKQ_ELEMENT(uint32, workq, elem_ix);
++				pktid = *elem;
++			}
++
++			rxbuf_post->cmn_hdr.request_id = htol32(pktid);
++
++			/* Now populate the previous locker with valid information */
++			if (pktid != DHD_PKTID_INVALID) {
++				DHD_NATIVE_TO_PKTID_SAVE(dhd, dhd->prot->pktid_rx_map,
++					p, pktid, pa, pktlen[i], DMA_RX, NULL, NULL,
++					PKTTYPE_DATA_RX);
++			}
++		} else
++#endif /* ! DHD_LB_RXC */
++		{
++#if defined(DHD_LB_RXC)
++alloc_pkt_id:
++#endif /* DHD_LB_RXC */
++		pktid = DHD_NATIVE_TO_PKTID(dhd, dhd->prot->pktid_rx_map, p, pa,
++			pktlen[i], DMA_RX, NULL, ring->dma_buf.secdma, PKTTYPE_DATA_RX);
++#if defined(DHD_PCIE_PKTID)
++		if (pktid == DHD_PKTID_INVALID) {
++			break;
++		}
++#endif /* DHD_PCIE_PKTID */
++		}
++
++		/* Common msg header */
++		rxbuf_post->cmn_hdr.msg_type = MSG_TYPE_RXBUF_POST;
++		rxbuf_post->cmn_hdr.if_id = 0;
++		rxbuf_post->cmn_hdr.epoch = ring->seqnum % H2D_EPOCH_MODULO;
++		rxbuf_post->cmn_hdr.flags = ring->current_phase;
++		ring->seqnum++;
++		rxbuf_post->data_buf_len = htol16((uint16)pktlen[i]);
++		rxbuf_post->data_buf_addr.high_addr = htol32(PHYSADDRHI(pa));
++		rxbuf_post->data_buf_addr.low_addr =
++			htol32(PHYSADDRLO(pa) + prot->rx_metadata_offset);
++
++		if (prot->rx_metadata_offset) {
++			rxbuf_post->metadata_buf_len = prot->rx_metadata_offset;
++			rxbuf_post->metadata_buf_addr.high_addr = htol32(PHYSADDRHI(pa));
++			rxbuf_post->metadata_buf_addr.low_addr  = htol32(PHYSADDRLO(pa));
++		} else {
++			rxbuf_post->metadata_buf_len = 0;
++			rxbuf_post->metadata_buf_addr.high_addr = 0;
++			rxbuf_post->metadata_buf_addr.low_addr  = 0;
++		}
++
++#ifdef DHD_PKTID_AUDIT_RING
++		DHD_PKTID_AUDIT(dhd, prot->pktid_rx_map, pktid, DHD_DUPLICATE_ALLOC);
++#endif /* DHD_PKTID_AUDIT_RING */
++
++		rxbuf_post->cmn_hdr.request_id = htol32(pktid);
++
++		/* Move rxbuf_post_tmp to next item */
++		rxbuf_post_tmp = rxbuf_post_tmp + ring->item_len;
++	}
++
++	if (i < alloced) {
++		if (ring->wr < (alloced - i))
++			ring->wr = ring->max_items - (alloced - i);
++		else
++			ring->wr -= (alloced - i);
++
++		if (ring->wr == 0) {
++			DHD_INFO(("%s: flipping the phase now\n", ring->name));
++				ring->current_phase = ring->current_phase ?
++				0 : BCMPCIE_CMNHDR_PHASE_BIT_INIT;
++		}
++
++		alloced = i;
++	}
++
++	/* update ring's WR index and ring doorbell to dongle */
++	if (alloced > 0) {
++		unsigned long flags1;
++		DHD_GENERAL_LOCK(dhd, flags1);
++		dhd_prot_ring_write_complete(dhd, ring, msg_start, alloced);
++		DHD_GENERAL_UNLOCK(dhd, flags1);
++	}
++
++	DHD_SPIN_UNLOCK(prot->rx_lock, flags);
++
++cleanup:
++	for (i = alloced; i < count; i++) {
++		p = pktbuf[i];
++		pa = pktbuf_pa[i];
++
++		if (SECURE_DMA_ENAB(dhd->osh))
++			SECURE_DMA_UNMAP(dhd->osh, pa, pktlen[i], DMA_RX, 0,
++				DHD_DMAH_NULL, ring->dma_buf.secdma, 0);
++		else
++			DMA_UNMAP(dhd->osh, pa, pktlen[i], DMA_RX, 0, DHD_DMAH_NULL);
++		PKTFREE(dhd->osh, p, FALSE);
++	}
++
++	MFREE(dhd->osh, lcl_buf, lcl_buf_size);
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++	return alloced;
++} /* dhd_prot_rxbufpost */
++
++static int
++dhd_prot_infobufpost(dhd_pub_t *dhd)
++{
++	unsigned long flags;
++	uint32 pktid;
++	dhd_prot_t *prot = dhd->prot;
++	msgbuf_ring_t *ring = prot->h2dring_info_subn;
++	uint16 alloced = 0;
++	uint16 pktsz = DHD_FLOWRING_RX_BUFPOST_PKTSZ;
++	uint32 pktlen;
++	info_buf_post_msg_t *infobuf_post;
++	uint8 *infobuf_post_tmp;
++	void *p;
++	void* msg_start;
++	uint8 i = 0;
++	dmaaddr_t pa;
++	int16 count;
++
++	if (ring == NULL)
++		return 0;
++
++	if (ring->inited != TRUE)
++		return 0;
++	if (prot->max_infobufpost == 0)
++		return 0;
++
++	count = prot->max_infobufpost - prot->infobufpost;
++
++	if (count <= 0) {
++		DHD_INFO(("%s: Cannot post more than max info resp buffers\n",
++			__FUNCTION__));
++		return 0;
++	}
++
++#ifdef PCIE_INB_DW
++	if (dhd_prot_inc_hostactive_devwake_assert(dhd->bus) != BCME_OK)
++		return BCME_ERROR;
++#endif /* PCIE_INB_DW */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++	/* Claim space for exactly 'count' no of messages, for mitigation purpose */
++	msg_start = (void *) dhd_prot_alloc_ring_space(dhd, ring, count, &alloced, FALSE);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	if (msg_start == NULL) {
++		DHD_INFO(("%s:%d: infobufpost Msgbuf Not available\n", __FUNCTION__, __LINE__));
++#ifdef PCIE_INB_DW
++		dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++		return -1;
++	}
++
++	/* if msg_start !=  NULL, we should have alloced space for atleast 1 item */
++	ASSERT(alloced > 0);
++
++	infobuf_post_tmp = (uint8*) msg_start;
++
++	/* loop through each allocated message in the host ring */
++	for (i = 0; i < alloced; i++) {
++		infobuf_post = (info_buf_post_msg_t *) infobuf_post_tmp;
++		/* Create a rx buffer */
++#ifdef DHD_USE_STATIC_CTRLBUF
++		p = PKTGET_STATIC(dhd->osh, pktsz, FALSE);
++#else
++		p = PKTGET(dhd->osh, pktsz, FALSE);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++		if (p == NULL) {
++			DHD_ERROR(("%s:%d: PKTGET for infobuf failed\n", __FUNCTION__, __LINE__));
++			dhd->rx_pktgetfail++;
++			break;
++		}
++		pktlen = PKTLEN(dhd->osh, p);
++		if (SECURE_DMA_ENAB(dhd->osh)) {
++			pa = SECURE_DMA_MAP(dhd->osh, PKTDATA(dhd->osh, p), pktlen,
++				DMA_RX, p, 0, ring->dma_buf.secdma, 0);
++		}
++#ifndef BCM_SECURE_DMA
++		else
++			pa = DMA_MAP(dhd->osh, PKTDATA(dhd->osh, p), pktlen, DMA_RX, p, 0);
++#endif /* #ifndef BCM_SECURE_DMA */
++		if (PHYSADDRISZERO(pa)) {
++			if (SECURE_DMA_ENAB(dhd->osh)) {
++				SECURE_DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, 0, DHD_DMAH_NULL,
++					ring->dma_buf.secdma, 0);
++			}
++			else
++				DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, 0, DHD_DMAH_NULL);
++#ifdef DHD_USE_STATIC_CTRLBUF
++			PKTFREE_STATIC(dhd->osh, p, FALSE);
++#else
++			PKTFREE(dhd->osh, p, FALSE);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++			DHD_ERROR(("Invalid phyaddr 0\n"));
++			ASSERT(0);
++			break;
++		}
++#ifdef DMAMAP_STATS
++		dhd->dma_stats.info_rx++;
++		dhd->dma_stats.info_rx_sz += pktlen;
++#endif /* DMAMAP_STATS */
++		pktlen = PKTLEN(dhd->osh, p);
++
++		/* Common msg header */
++		infobuf_post->cmn_hdr.msg_type = MSG_TYPE_INFO_BUF_POST;
++		infobuf_post->cmn_hdr.if_id = 0;
++		infobuf_post->cmn_hdr.epoch = ring->seqnum % H2D_EPOCH_MODULO;
++		infobuf_post->cmn_hdr.flags = ring->current_phase;
++		ring->seqnum++;
++
++#if defined(DHD_PCIE_PKTID)
++		/* get the lock before calling DHD_NATIVE_TO_PKTID */
++		DHD_GENERAL_LOCK(dhd, flags);
++#endif /* DHD_PCIE_PKTID */
++
++		pktid = DHD_NATIVE_TO_PKTID(dhd, dhd->prot->pktid_ctrl_map, p, pa,
++			pktlen, DMA_RX, NULL, ring->dma_buf.secdma, PKTTYPE_INFO_RX);
++
++
++#if defined(DHD_PCIE_PKTID)
++		/* free lock */
++		DHD_GENERAL_UNLOCK(dhd, flags);
++
++		if (pktid == DHD_PKTID_INVALID) {
++			if (SECURE_DMA_ENAB(dhd->osh)) {
++				DHD_GENERAL_LOCK(dhd, flags);
++				SECURE_DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, 0, 0,
++					ring->dma_buf.secdma, 0);
++				DHD_GENERAL_UNLOCK(dhd, flags);
++			} else
++				DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, 0, 0);
++
++#ifdef DHD_USE_STATIC_CTRLBUF
++			PKTFREE_STATIC(dhd->osh, p, FALSE);
++#else
++			PKTFREE(dhd->osh, p, FALSE);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++			DHD_ERROR(("%s: Pktid pool depleted.\n", __FUNCTION__));
++			break;
++		}
++#endif /* DHD_PCIE_PKTID */
++
++		infobuf_post->host_buf_len = htol16((uint16)pktlen);
++		infobuf_post->host_buf_addr.high_addr = htol32(PHYSADDRHI(pa));
++		infobuf_post->host_buf_addr.low_addr = htol32(PHYSADDRLO(pa));
++
++#ifdef DHD_PKTID_AUDIT_RING
++		DHD_PKTID_AUDIT(dhd, prot->pktid_ctrl_map, pktid, DHD_DUPLICATE_ALLOC);
++#endif /* DHD_PKTID_AUDIT_RING */
++
++		DHD_INFO(("ID %d, low_addr 0x%08x, high_addr 0x%08x\n",
++			infobuf_post->cmn_hdr.request_id,  infobuf_post->host_buf_addr.low_addr,
++			infobuf_post->host_buf_addr.high_addr));
++
++		infobuf_post->cmn_hdr.request_id = htol32(pktid);
++		/* Move rxbuf_post_tmp to next item */
++		infobuf_post_tmp = infobuf_post_tmp + ring->item_len;
++	}
++
++	if (i < alloced) {
++		if (ring->wr < (alloced - i))
++			ring->wr = ring->max_items - (alloced - i);
++		else
++			ring->wr -= (alloced - i);
++
++		alloced = i;
++		if (alloced && ring->wr == 0) {
++			DHD_INFO(("%s: flipping the phase now\n", ring->name));
++			ring->current_phase = ring->current_phase ?
++				0 : BCMPCIE_CMNHDR_PHASE_BIT_INIT;
++		}
++	}
++
++	/* Update the write pointer in TCM & ring bell */
++	if (alloced > 0) {
++		prot->infobufpost += alloced;
++		DHD_INFO(("allocated %d buffers for info ring\n",  alloced));
++		DHD_GENERAL_LOCK(dhd, flags);
++		dhd_prot_ring_write_complete(dhd, ring, msg_start, alloced);
++		DHD_GENERAL_UNLOCK(dhd, flags);
++	}
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++	return alloced;
++} /* dhd_prot_infobufpost */
++
++#ifdef IOCTLRESP_USE_CONSTMEM
++static int
++alloc_ioctl_return_buffer(dhd_pub_t *dhd, dhd_dma_buf_t *retbuf)
++{
++	int err;
++	memset(retbuf, 0, sizeof(dhd_dma_buf_t));
++
++	if ((err = dhd_dma_buf_alloc(dhd, retbuf, IOCT_RETBUF_SIZE)) != BCME_OK) {
++		DHD_ERROR(("%s: dhd_dma_buf_alloc err %d\n", __FUNCTION__, err));
++		ASSERT(0);
++		return BCME_NOMEM;
++	}
++
++	return BCME_OK;
++}
++
++static void
++free_ioctl_return_buffer(dhd_pub_t *dhd, dhd_dma_buf_t *retbuf)
++{
++	/* retbuf (declared on stack) not fully populated ...  */
++	if (retbuf->va) {
++		uint32 dma_pad;
++		dma_pad = (IOCT_RETBUF_SIZE % DHD_DMA_PAD) ? DHD_DMA_PAD : 0;
++		retbuf->len = IOCT_RETBUF_SIZE;
++		retbuf->_alloced = retbuf->len + dma_pad;
++	}
++
++	dhd_dma_buf_free(dhd, retbuf);
++	return;
++}
++#endif /* IOCTLRESP_USE_CONSTMEM */
++
++static int
++dhd_prot_rxbufpost_ctrl(dhd_pub_t *dhd, uint8 msg_type)
++{
++	void *p;
++	uint16 pktsz;
++	ioctl_resp_evt_buf_post_msg_t *rxbuf_post;
++	dmaaddr_t pa;
++	uint32 pktlen;
++	dhd_prot_t *prot = dhd->prot;
++	uint16 alloced = 0;
++	unsigned long flags;
++	dhd_dma_buf_t retbuf;
++	void *dmah = NULL;
++	uint32 pktid;
++	void *map_handle;
++	msgbuf_ring_t *ring = &prot->h2dring_ctrl_subn;
++	bool non_ioctl_resp_buf = 0;
++	dhd_pkttype_t buf_type;
++
++	if (dhd->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s: bus is already down.\n", __FUNCTION__));
++		return -1;
++	}
++	memset(&retbuf, 0, sizeof(dhd_dma_buf_t));
++
++	if (msg_type == MSG_TYPE_IOCTLRESP_BUF_POST)
++		buf_type = PKTTYPE_IOCTL_RX;
++	else if (msg_type == MSG_TYPE_EVENT_BUF_POST)
++		buf_type = PKTTYPE_EVENT_RX;
++	else if (msg_type == MSG_TYPE_TIMSTAMP_BUFPOST)
++		buf_type = PKTTYPE_TSBUF_RX;
++	else {
++		DHD_ERROR(("invalid message type to be posted to Ctrl ring %d\n", msg_type));
++		return -1;
++	}
++
++
++	if ((msg_type == MSG_TYPE_EVENT_BUF_POST) || (msg_type == MSG_TYPE_TIMSTAMP_BUFPOST))
++		non_ioctl_resp_buf = TRUE;
++	else
++		non_ioctl_resp_buf = FALSE;
++
++	if (non_ioctl_resp_buf) {
++		/* Allocate packet for not ioctl resp buffer post */
++		pktsz = DHD_FLOWRING_RX_BUFPOST_PKTSZ;
++	} else {
++		/* Allocate packet for ctrl/ioctl buffer post */
++		pktsz = DHD_FLOWRING_IOCTL_BUFPOST_PKTSZ;
++	}
++
++#ifdef IOCTLRESP_USE_CONSTMEM
++	if (!non_ioctl_resp_buf) {
++		if (alloc_ioctl_return_buffer(dhd, &retbuf) != BCME_OK) {
++			DHD_ERROR(("Could not allocate IOCTL response buffer\n"));
++			return -1;
++		}
++		ASSERT(retbuf.len == IOCT_RETBUF_SIZE);
++		p = retbuf.va;
++		pktlen = retbuf.len;
++		pa = retbuf.pa;
++		dmah = retbuf.dmah;
++	} else
++#endif /* IOCTLRESP_USE_CONSTMEM */
++	{
++#ifdef DHD_USE_STATIC_CTRLBUF
++		p = PKTGET_STATIC(dhd->osh, pktsz, FALSE);
++#else
++		p = PKTGET(dhd->osh, pktsz, FALSE);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++		if (p == NULL) {
++			DHD_ERROR(("%s:%d: PKTGET for %s buf failed\n",
++				__FUNCTION__, __LINE__, non_ioctl_resp_buf ?
++				"EVENT" : "IOCTL RESP"));
++			dhd->rx_pktgetfail++;
++			return -1;
++		}
++
++		pktlen = PKTLEN(dhd->osh, p);
++
++		if (SECURE_DMA_ENAB(dhd->osh)) {
++			DHD_GENERAL_LOCK(dhd, flags);
++			pa = SECURE_DMA_MAP(dhd->osh, PKTDATA(dhd->osh, p), pktlen,
++				DMA_RX, p, 0, ring->dma_buf.secdma, 0);
++			DHD_GENERAL_UNLOCK(dhd, flags);
++		}
++#ifndef BCM_SECURE_DMA
++		else
++			pa = DMA_MAP(dhd->osh, PKTDATA(dhd->osh, p), pktlen, DMA_RX, p, 0);
++#endif /* #ifndef BCM_SECURE_DMA */
++
++		if (PHYSADDRISZERO(pa)) {
++			DHD_ERROR(("Invalid physaddr 0\n"));
++			ASSERT(0);
++			goto free_pkt_return;
++		}
++
++#ifdef DMAMAP_STATS
++		switch (buf_type) {
++#ifndef IOCTLRESP_USE_CONSTMEM
++			case PKTTYPE_IOCTL_RX:
++				dhd->dma_stats.ioctl_rx++;
++				dhd->dma_stats.ioctl_rx_sz += pktlen;
++				break;
++#endif /* !IOCTLRESP_USE_CONSTMEM */
++			case PKTTYPE_EVENT_RX:
++				dhd->dma_stats.event_rx++;
++				dhd->dma_stats.event_rx_sz += pktlen;
++				break;
++			case PKTTYPE_TSBUF_RX:
++				dhd->dma_stats.tsbuf_rx++;
++				dhd->dma_stats.tsbuf_rx_sz += pktlen;
++				break;
++			default:
++				break;
++		}
++#endif /* DMAMAP_STATS */
++
++	}
++#ifdef PCIE_INB_DW
++	if (dhd_prot_inc_hostactive_devwake_assert(dhd->bus) != BCME_OK)
++		return BCME_ERROR;
++#endif /* PCIE_INB_DW */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	rxbuf_post = (ioctl_resp_evt_buf_post_msg_t *)
++		dhd_prot_alloc_ring_space(dhd, ring, 1, &alloced, FALSE);
++
++	if (rxbuf_post == NULL) {
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		DHD_ERROR(("%s:%d: Ctrl submit Msgbuf Not available to post buffer \n",
++			__FUNCTION__, __LINE__));
++
++#ifdef IOCTLRESP_USE_CONSTMEM
++		if (non_ioctl_resp_buf)
++#endif /* IOCTLRESP_USE_CONSTMEM */
++		{
++			if (SECURE_DMA_ENAB(dhd->osh)) {
++				DHD_GENERAL_LOCK(dhd, flags);
++				SECURE_DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, 0, DHD_DMAH_NULL,
++					ring->dma_buf.secdma, 0);
++				DHD_GENERAL_UNLOCK(dhd, flags);
++			} else {
++				DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, 0, DHD_DMAH_NULL);
++			}
++		}
++		goto free_pkt_return;
++	}
++
++	/* CMN msg header */
++	rxbuf_post->cmn_hdr.msg_type = msg_type;
++
++#ifdef IOCTLRESP_USE_CONSTMEM
++	if (!non_ioctl_resp_buf) {
++		map_handle = dhd->prot->pktid_map_handle_ioctl;
++		pktid = DHD_NATIVE_TO_PKTID(dhd, map_handle, p, pa, pktlen, DMA_RX, dmah,
++			ring->dma_buf.secdma, buf_type);
++	} else
++#endif /* IOCTLRESP_USE_CONSTMEM */
++	{
++		map_handle = dhd->prot->pktid_ctrl_map;
++		pktid = DHD_NATIVE_TO_PKTID(dhd, map_handle,
++			p, pa, pktlen, DMA_RX, dmah, ring->dma_buf.secdma,
++			buf_type);
++	}
++
++	if (pktid == DHD_PKTID_INVALID) {
++		if (ring->wr == 0) {
++			ring->wr = ring->max_items - 1;
++		} else {
++			ring->wr--;
++			if (ring->wr == 0) {
++				ring->current_phase = ring->current_phase ? 0 :
++					BCMPCIE_CMNHDR_PHASE_BIT_INIT;
++			}
++		}
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, 0, DHD_DMAH_NULL);
++		DHD_ERROR(("%s: Pktid pool depleted.\n", __FUNCTION__));
++		goto free_pkt_return;
++	}
++
++#ifdef DHD_PKTID_AUDIT_RING
++	DHD_PKTID_AUDIT(dhd, map_handle, pktid, DHD_DUPLICATE_ALLOC);
++#endif /* DHD_PKTID_AUDIT_RING */
++
++	rxbuf_post->cmn_hdr.request_id = htol32(pktid);
++	rxbuf_post->cmn_hdr.if_id = 0;
++	rxbuf_post->cmn_hdr.epoch =  ring->seqnum % H2D_EPOCH_MODULO;
++	ring->seqnum++;
++	rxbuf_post->cmn_hdr.flags = ring->current_phase;
++
++#if defined(DHD_PCIE_PKTID)
++	if (rxbuf_post->cmn_hdr.request_id == DHD_PKTID_INVALID) {
++		if (ring->wr == 0) {
++			ring->wr = ring->max_items - 1;
++		} else {
++			if (ring->wr == 0) {
++				ring->current_phase = ring->current_phase ? 0 :
++					BCMPCIE_CMNHDR_PHASE_BIT_INIT;
++			}
++		}
++		DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef IOCTLRESP_USE_CONSTMEM
++		if (non_ioctl_resp_buf)
++#endif /* IOCTLRESP_USE_CONSTMEM */
++		{
++			if (SECURE_DMA_ENAB(dhd->osh)) {
++				DHD_GENERAL_LOCK(dhd, flags);
++				SECURE_DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, 0, DHD_DMAH_NULL,
++					ring->dma_buf.secdma, 0);
++				DHD_GENERAL_UNLOCK(dhd, flags);
++			} else
++				DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, 0, DHD_DMAH_NULL);
++		}
++		goto free_pkt_return;
++	}
++#endif /* DHD_PCIE_PKTID */
++
++#ifndef IOCTLRESP_USE_CONSTMEM
++	rxbuf_post->host_buf_len = htol16((uint16)PKTLEN(dhd->osh, p));
++#else
++	rxbuf_post->host_buf_len = htol16((uint16)pktlen);
++#endif /* IOCTLRESP_USE_CONSTMEM */
++	rxbuf_post->host_buf_addr.high_addr = htol32(PHYSADDRHI(pa));
++	rxbuf_post->host_buf_addr.low_addr  = htol32(PHYSADDRLO(pa));
++
++	/* update ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ring, rxbuf_post, 1);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++
++	return 1;
++
++free_pkt_return:
++#ifdef IOCTLRESP_USE_CONSTMEM
++	if (!non_ioctl_resp_buf) {
++		free_ioctl_return_buffer(dhd, &retbuf);
++	} else
++#endif
++	{
++		dhd_prot_packet_free(dhd, p, buf_type, FALSE);
++	}
++
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++
++	return -1;
++} /* dhd_prot_rxbufpost_ctrl */
++
++static uint16
++dhd_msgbuf_rxbuf_post_ctrlpath(dhd_pub_t *dhd, uint8 msg_type, uint32 max_to_post)
++{
++	uint32 i = 0;
++	int32 ret_val;
++
++	DHD_INFO(("max to post %d, event %d \n", max_to_post, msg_type));
++
++	if (dhd->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s: bus is already down.\n", __FUNCTION__));
++		return 0;
++	}
++
++	while (i < max_to_post) {
++		ret_val  = dhd_prot_rxbufpost_ctrl(dhd, msg_type);
++		if (ret_val < 0)
++			break;
++		i++;
++	}
++	DHD_INFO(("posted %d buffers of type %d\n", i, msg_type));
++	return (uint16)i;
++}
++
++static void
++dhd_msgbuf_rxbuf_post_ioctlresp_bufs(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	int max_to_post;
++
++	DHD_INFO(("ioctl resp buf post\n"));
++	max_to_post = prot->max_ioctlrespbufpost - prot->cur_ioctlresp_bufs_posted;
++	if (max_to_post <= 0) {
++		DHD_INFO(("%s: Cannot post more than max IOCTL resp buffers\n",
++			__FUNCTION__));
++		return;
++	}
++	prot->cur_ioctlresp_bufs_posted += dhd_msgbuf_rxbuf_post_ctrlpath(dhd,
++		MSG_TYPE_IOCTLRESP_BUF_POST, max_to_post);
++}
++
++static void
++dhd_msgbuf_rxbuf_post_event_bufs(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	int max_to_post;
++
++	/* Use atomic variable to avoid re-entry */
++	if (atomic_read(&dhd_msgbuf_rxbuf_post_event_bufs_running) > 0) {
++		return;
++	}
++	atomic_inc(&dhd_msgbuf_rxbuf_post_event_bufs_running);
++
++	max_to_post = prot->max_eventbufpost - prot->cur_event_bufs_posted;
++	if (max_to_post <= 0) {
++		DHD_ERROR(("%s: Cannot post more than max event buffers\n",
++			__FUNCTION__));
++		return;
++	}
++	prot->cur_event_bufs_posted += dhd_msgbuf_rxbuf_post_ctrlpath(dhd,
++		MSG_TYPE_EVENT_BUF_POST, max_to_post);
++
++	atomic_dec(&dhd_msgbuf_rxbuf_post_event_bufs_running);
++}
++
++static int
++dhd_msgbuf_rxbuf_post_ts_bufs(dhd_pub_t *dhd)
++{
++#ifdef DHD_TIMESYNC
++	dhd_prot_t *prot = dhd->prot;
++	int max_to_post;
++
++	if (prot->active_ipc_version < 7) {
++		DHD_ERROR(("no ts buffers to device ipc rev is %d, needs to be atleast 7\n",
++			prot->active_ipc_version));
++		return 0;
++	}
++
++	max_to_post = prot->max_tsbufpost - prot->cur_ts_bufs_posted;
++	if (max_to_post <= 0) {
++		DHD_INFO(("%s: Cannot post more than max ts buffers\n",
++			__FUNCTION__));
++		return 0;
++	}
++
++	prot->cur_ts_bufs_posted += dhd_msgbuf_rxbuf_post_ctrlpath(dhd,
++		MSG_TYPE_TIMSTAMP_BUFPOST, max_to_post);
++#endif /* DHD_TIMESYNC */
++	return 0;
++}
++
++bool BCMFASTPATH
++dhd_prot_process_msgbuf_infocpl(dhd_pub_t *dhd, uint bound)
++{
++	dhd_prot_t *prot = dhd->prot;
++	bool more = TRUE;
++	uint n = 0;
++	msgbuf_ring_t *ring = prot->d2hring_info_cpln;
++
++	if (ring == NULL)
++		return FALSE;
++	if (ring->inited != TRUE)
++		return FALSE;
++
++	/* Process all the messages - DTOH direction */
++	while (!dhd_is_device_removed(dhd)) {
++		uint8 *msg_addr;
++		uint32 msg_len;
++
++		if (dhd->hang_was_sent) {
++			more = FALSE;
++			break;
++		}
++
++		/* Get the message from ring */
++		msg_addr = dhd_prot_get_read_addr(dhd, ring, &msg_len);
++		if (msg_addr == NULL) {
++			more = FALSE;
++			break;
++		}
++
++		/* Prefetch data to populate the cache */
++		OSL_PREFETCH(msg_addr);
++
++		if (dhd_prot_process_msgtype(dhd, ring, msg_addr, msg_len) != BCME_OK) {
++			DHD_ERROR(("%s: Error at  process rxpl msgbuf of len %d\n",
++				__FUNCTION__, msg_len));
++		}
++
++		/* Update read pointer */
++		dhd_prot_upd_read_idx(dhd, ring);
++
++		/* After batch processing, check RX bound */
++		n += msg_len / ring->item_len;
++		if (n >= bound) {
++			break;
++		}
++	}
++
++	return more;
++}
++
++/** called when DHD needs to check for 'receive complete' messages from the dongle */
++bool BCMFASTPATH
++dhd_prot_process_msgbuf_rxcpl(dhd_pub_t *dhd, uint bound)
++{
++	bool more = FALSE;
++	uint n = 0;
++	dhd_prot_t *prot = dhd->prot;
++	msgbuf_ring_t *ring = &prot->d2hring_rx_cpln;
++	uint16 item_len = ring->item_len;
++	host_rxbuf_cmpl_t *msg = NULL;
++	uint8 *msg_addr;
++	uint32 msg_len;
++	uint16 pkt_cnt, pkt_cnt_newidx;
++	unsigned long flags;
++	dmaaddr_t pa;
++	uint32 len;
++	void *dmah;
++	void *secdma;
++	int ifidx = 0, if_newidx = 0;
++	void *pkt, *pktqhead = NULL, *prevpkt = NULL, *pkt_newidx, *nextpkt;
++	uint32 pktid;
++	int i;
++	uint8 sync;
++
++	while (1) {
++		if (dhd_is_device_removed(dhd))
++			break;
++
++		if (dhd->hang_was_sent)
++			break;
++
++		pkt_cnt = 0;
++		pktqhead = pkt_newidx = NULL;
++		pkt_cnt_newidx = 0;
++
++		DHD_SPIN_LOCK(prot->rx_lock, flags);
++
++		/* Get the address of the next message to be read from ring */
++		msg_addr = dhd_prot_get_read_addr(dhd, ring, &msg_len);
++		if (msg_addr == NULL) {
++			DHD_SPIN_UNLOCK(prot->rx_lock, flags);
++			break;
++		}
++
++		while (msg_len > 0) {
++			msg = (host_rxbuf_cmpl_t *)msg_addr;
++
++			/* Wait until DMA completes, then fetch msg_type */
++			sync = prot->d2h_sync_cb(dhd, ring, &msg->cmn_hdr, item_len);
++			/*
++			 * Update the curr_rd to the current index in the ring, from where
++			 * the work item is fetched. This way if the fetched work item
++			 * fails in LIVELOCK, we can print the exact read index in the ring
++			 * that shows up the corrupted work item.
++			 */
++			if ((ring->curr_rd + 1) >= ring->max_items) {
++				ring->curr_rd = 0;
++			} else {
++				ring->curr_rd += 1;
++			}
++
++			if (!sync) {
++				msg_len -= item_len;
++				msg_addr += item_len;
++				continue;
++			}
++
++			pktid = ltoh32(msg->cmn_hdr.request_id);
++
++#ifdef DHD_PKTID_AUDIT_RING
++			DHD_PKTID_AUDIT_RING_DEBUG(dhd, dhd->prot->pktid_rx_map, pktid,
++				DHD_DUPLICATE_FREE, msg, D2HRING_RXCMPLT_ITEMSIZE);
++#endif /* DHD_PKTID_AUDIT_RING */
++
++			pkt = DHD_PKTID_TO_NATIVE(dhd, prot->pktid_rx_map, pktid, pa,
++			        len, dmah, secdma, PKTTYPE_DATA_RX);
++			if (!pkt) {
++				msg_len -= item_len;
++				msg_addr += item_len;
++				continue;
++			}
++
++			if (SECURE_DMA_ENAB(dhd->osh))
++				SECURE_DMA_UNMAP(dhd->osh, pa, (uint) len, DMA_RX, 0,
++				    dmah, secdma, 0);
++			else
++				DMA_UNMAP(dhd->osh, pa, (uint) len, DMA_RX, 0, dmah);
++
++#ifdef DMAMAP_STATS
++			dhd->dma_stats.rxdata--;
++			dhd->dma_stats.rxdata_sz -= len;
++#endif /* DMAMAP_STATS */
++			DHD_INFO(("id 0x%04x, offset %d, len %d, idx %d, phase 0x%02x, "
++				"pktdata %p, metalen %d\n",
++				ltoh32(msg->cmn_hdr.request_id),
++				ltoh16(msg->data_offset),
++				ltoh16(msg->data_len), msg->cmn_hdr.if_id,
++				msg->cmn_hdr.flags, PKTDATA(dhd->osh, pkt),
++				ltoh16(msg->metadata_len)));
++
++			pkt_cnt++;
++			msg_len -= item_len;
++			msg_addr += item_len;
++
++#if DHD_DBG_SHOW_METADATA
++			if (prot->metadata_dbg && prot->rx_metadata_offset &&
++			        msg->metadata_len) {
++				uchar *ptr;
++				ptr = PKTDATA(dhd->osh, pkt) - (prot->rx_metadata_offset);
++				/* header followed by data */
++				bcm_print_bytes("rxmetadata", ptr, msg->metadata_len);
++				dhd_prot_print_metadata(dhd, ptr, msg->metadata_len);
++			}
++#endif /* DHD_DBG_SHOW_METADATA */
++
++			/* data_offset from buf start */
++			if (ltoh16(msg->data_offset)) {
++				/* data offset given from dongle after split rx */
++				PKTPULL(dhd->osh, pkt, ltoh16(msg->data_offset));
++			}
++			else if (prot->rx_dataoffset) {
++				/* DMA RX offset updated through shared area */
++				PKTPULL(dhd->osh, pkt, prot->rx_dataoffset);
++			}
++			/* Actual length of the packet */
++			PKTSETLEN(dhd->osh, pkt, ltoh16(msg->data_len));
++#if defined(WL_MONITOR)
++			if (dhd_monitor_enabled(dhd, ifidx) &&
++				(msg->flags & BCMPCIE_PKT_FLAGS_FRAME_802_11)) {
++				dhd_rx_mon_pkt(dhd, msg, pkt, ifidx);
++				continue;
++			}
++#endif 
++
++			if (!pktqhead) {
++				pktqhead = prevpkt = pkt;
++				ifidx = msg->cmn_hdr.if_id;
++			} else {
++				if (ifidx != msg->cmn_hdr.if_id) {
++					pkt_newidx = pkt;
++					if_newidx = msg->cmn_hdr.if_id;
++					pkt_cnt--;
++					pkt_cnt_newidx = 1;
++					break;
++				} else {
++					PKTSETNEXT(dhd->osh, prevpkt, pkt);
++					prevpkt = pkt;
++				}
++			}
++
++#ifdef DHD_TIMESYNC
++			if (dhd->prot->rx_ts_log_enabled) {
++				ts_timestamp_t *ts = (ts_timestamp_t *)&msg->ts;
++				dhd_timesync_log_rx_timestamp(dhd->ts, ifidx, ts->low, ts->high);
++			}
++#endif /* DHD_TIMESYNC */
++		}
++
++		/* roll back read pointer for unprocessed message */
++		if (msg_len > 0) {
++			if (ring->rd < msg_len / item_len)
++				ring->rd = ring->max_items - msg_len / item_len;
++			else
++				ring->rd -= msg_len / item_len;
++		}
++
++		/* Update read pointer */
++		dhd_prot_upd_read_idx(dhd, ring);
++
++		DHD_SPIN_UNLOCK(prot->rx_lock, flags);
++
++		pkt = pktqhead;
++		for (i = 0; pkt && i < pkt_cnt; i++, pkt = nextpkt) {
++			nextpkt = PKTNEXT(dhd->osh, pkt);
++			PKTSETNEXT(dhd->osh, pkt, NULL);
++#ifdef DHD_LB_RXP
++			dhd_lb_rx_pkt_enqueue(dhd, pkt, ifidx);
++#elif defined(DHD_RX_CHAINING)
++			dhd_rxchain_frame(dhd, pkt, ifidx);
++#else
++			dhd_bus_rx_frame(dhd->bus, pkt, ifidx, 1);
++#endif /* DHD_LB_RXP */
++		}
++
++		if (pkt_newidx) {
++#ifdef DHD_LB_RXP
++			dhd_lb_rx_pkt_enqueue(dhd, pkt_newidx, if_newidx);
++#elif defined(DHD_RX_CHAINING)
++			dhd_rxchain_frame(dhd, pkt_newidx, if_newidx);
++#else
++			dhd_bus_rx_frame(dhd->bus, pkt_newidx, if_newidx, 1);
++#endif /* DHD_LB_RXP */
++		}
++
++		pkt_cnt += pkt_cnt_newidx;
++
++		/* Post another set of rxbufs to the device */
++		dhd_prot_return_rxbuf(dhd, 0, pkt_cnt);
++
++		/* After batch processing, check RX bound */
++		n += pkt_cnt;
++		if (n >= bound) {
++			more = TRUE;
++			break;
++		}
++	}
++
++	/* Call lb_dispatch only if packets are queued */
++	if (n) {
++		DHD_LB_DISPATCH_RX_COMPL(dhd);
++		DHD_LB_DISPATCH_RX_PROCESS(dhd);
++	}
++
++	return more;
++}
++
++/**
++ * Hands transmit packets (with a caller provided flow_id) over to dongle territory (the flow ring)
++ */
++void
++dhd_prot_update_txflowring(dhd_pub_t *dhd, uint16 flowid, void *msgring)
++{
++	msgbuf_ring_t *ring = (msgbuf_ring_t *)msgring;
++
++	if (ring == NULL) {
++		DHD_ERROR(("%s: NULL txflowring. exiting...\n",  __FUNCTION__));
++		return;
++	}
++	/* Update read pointer */
++	if (dhd->dma_d2h_ring_upd_support) {
++		ring->rd = dhd_prot_dma_indx_get(dhd, H2D_DMA_INDX_RD_UPD, ring->idx);
++	}
++
++	DHD_TRACE(("ringid %d flowid %d write %d read %d \n\n",
++		ring->idx, flowid, ring->wr, ring->rd));
++
++	/* Need more logic here, but for now use it directly */
++	dhd_bus_schedule_queue(dhd->bus, flowid, TRUE); /* from queue to flowring */
++}
++
++/** called when DHD needs to check for 'transmit complete' messages from the dongle */
++bool BCMFASTPATH
++dhd_prot_process_msgbuf_txcpl(dhd_pub_t *dhd, uint bound)
++{
++	bool more = TRUE;
++	uint n = 0;
++	msgbuf_ring_t *ring = &dhd->prot->d2hring_tx_cpln;
++
++	/* Process all the messages - DTOH direction */
++	while (!dhd_is_device_removed(dhd)) {
++		uint8 *msg_addr;
++		uint32 msg_len;
++
++		if (dhd->hang_was_sent) {
++			more = FALSE;
++			break;
++		}
++
++		/* Get the address of the next message to be read from ring */
++		msg_addr = dhd_prot_get_read_addr(dhd, ring, &msg_len);
++		if (msg_addr == NULL) {
++			more = FALSE;
++			break;
++		}
++
++		/* Prefetch data to populate the cache */
++		OSL_PREFETCH(msg_addr);
++
++		if (dhd_prot_process_msgtype(dhd, ring, msg_addr, msg_len) != BCME_OK) {
++			DHD_ERROR(("%s: process %s msg addr %p len %d\n",
++				__FUNCTION__, ring->name, msg_addr, msg_len));
++		}
++
++		/* Write to dngl rd ptr */
++		dhd_prot_upd_read_idx(dhd, ring);
++
++		/* After batch processing, check bound */
++		n += msg_len / ring->item_len;
++		if (n >= bound) {
++			break;
++		}
++	}
++
++	DHD_LB_DISPATCH_TX_COMPL(dhd);
++
++	return more;
++}
++
++int BCMFASTPATH
++dhd_prot_process_trapbuf(dhd_pub_t *dhd)
++{
++	uint32 data;
++	dhd_dma_buf_t *trap_addr = &dhd->prot->fw_trap_buf;
++
++	/* Interrupts can come in before this struct
++	 *  has been initialized.
++	 */
++	if (trap_addr->va == NULL) {
++		DHD_ERROR(("%s: trap_addr->va is NULL\n", __FUNCTION__));
++		return 0;
++	}
++
++	OSL_CACHE_INV((void *)trap_addr->va, sizeof(uint32));
++	data = *(uint32 *)(trap_addr->va);
++
++	if (data & D2H_DEV_FWHALT) {
++		DHD_ERROR(("Firmware trapped and trap_data is 0x%04x\n", data));
++		if (data & D2H_DEV_EXT_TRAP_DATA)
++		{
++			if (dhd->extended_trap_data) {
++				OSL_CACHE_INV((void *)trap_addr->va,
++				       BCMPCIE_EXT_TRAP_DATA_MAXLEN);
++				memcpy(dhd->extended_trap_data, (uint32 *)trap_addr->va,
++				       BCMPCIE_EXT_TRAP_DATA_MAXLEN);
++			}
++			DHD_ERROR(("Extended trap data available\n"));
++		}
++		return data;
++	}
++	return 0;
++}
++
++/** called when DHD needs to check for 'ioctl complete' messages from the dongle */
++int BCMFASTPATH
++dhd_prot_process_ctrlbuf(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	msgbuf_ring_t *ring = &prot->d2hring_ctrl_cpln;
++
++	/* Process all the messages - DTOH direction */
++	while (!dhd_is_device_removed(dhd)) {
++		uint8 *msg_addr;
++		uint32 msg_len;
++
++		if (dhd->hang_was_sent) {
++			break;
++		}
++
++		/* Get the address of the next message to be read from ring */
++		msg_addr = dhd_prot_get_read_addr(dhd, ring, &msg_len);
++		if (msg_addr == NULL) {
++			break;
++		}
++
++		/* Prefetch data to populate the cache */
++		OSL_PREFETCH(msg_addr);
++		if (dhd_prot_process_msgtype(dhd, ring, msg_addr, msg_len) != BCME_OK) {
++			DHD_ERROR(("%s: process %s msg addr %p len %d\n",
++				__FUNCTION__, ring->name, msg_addr, msg_len));
++		}
++
++		/* Write to dngl rd ptr */
++		dhd_prot_upd_read_idx(dhd, ring);
++	}
++
++	return 0;
++}
++
++/**
++ * Consume messages out of the D2H ring. Ensure that the message's DMA to host
++ * memory has completed, before invoking the message handler via a table lookup
++ * of the cmn_msg_hdr::msg_type.
++ */
++static int BCMFASTPATH
++dhd_prot_process_msgtype(dhd_pub_t *dhd, msgbuf_ring_t *ring, uint8 *buf, uint32 len)
++{
++	uint32 buf_len = len;
++	uint16 item_len;
++	uint8 msg_type;
++	cmn_msg_hdr_t *msg = NULL;
++	int ret = BCME_OK;
++
++	ASSERT(ring);
++	item_len = ring->item_len;
++	if (item_len == 0) {
++		DHD_ERROR(("%s: ringidx %d, item_len %d buf_len %d \n",
++			__FUNCTION__, ring->idx, item_len, buf_len));
++		return BCME_ERROR;
++	}
++
++	while (buf_len > 0) {
++		if (dhd->hang_was_sent) {
++			ret = BCME_ERROR;
++			goto done;
++		}
++
++		msg = (cmn_msg_hdr_t *)buf;
++
++		/* Wait until DMA completes, then fetch msg_type */
++		msg_type = dhd->prot->d2h_sync_cb(dhd, ring, msg, item_len);
++
++		/*
++		 * Update the curr_rd to the current index in the ring, from where
++		 * the work item is fetched. This way if the fetched work item
++		 * fails in LIVELOCK, we can print the exact read index in the ring
++		 * that shows up the corrupted work item.
++		 */
++		if ((ring->curr_rd + 1) >= ring->max_items) {
++			ring->curr_rd = 0;
++		} else {
++			ring->curr_rd += 1;
++		}
++
++		/* Prefetch data to populate the cache */
++		OSL_PREFETCH(buf + item_len);
++
++		DHD_INFO(("msg_type %d item_len %d buf_len %d\n",
++			msg_type, item_len, buf_len));
++
++		if (msg_type == MSG_TYPE_LOOPBACK) {
++			bcm_print_bytes("LPBK RESP: ", (uint8 *)msg, item_len);
++			DHD_ERROR((" MSG_TYPE_LOOPBACK, len %d\n", item_len));
++		}
++
++		ASSERT(msg_type < DHD_PROT_FUNCS);
++		if (msg_type >= DHD_PROT_FUNCS) {
++			DHD_ERROR(("%s: msg_type %d, item_len %d buf_len %d\n",
++				__FUNCTION__, msg_type, item_len, buf_len));
++			ret = BCME_ERROR;
++			goto done;
++		}
++
++		if (table_lookup[msg_type]) {
++			table_lookup[msg_type](dhd, buf);
++		}
++
++		if (buf_len < item_len) {
++			ret = BCME_ERROR;
++			goto done;
++		}
++		buf_len = buf_len - item_len;
++		buf = buf + item_len;
++	}
++
++done:
++
++#ifdef DHD_RX_CHAINING
++	dhd_rxchain_commit(dhd);
++#endif
++
++	return ret;
++} /* dhd_prot_process_msgtype */
++
++static void
++dhd_prot_noop(dhd_pub_t *dhd, void *msg)
++{
++	return;
++}
++
++/** called on MSG_TYPE_RING_STATUS message received from dongle */
++static void
++dhd_prot_ringstatus_process(dhd_pub_t *dhd, void *msg)
++{
++	pcie_ring_status_t *ring_status = (pcie_ring_status_t *) msg;
++	uint32 request_id = ltoh32(ring_status->cmn_hdr.request_id);
++	uint16 status = ltoh16(ring_status->compl_hdr.status);
++	uint16 ring_id = ltoh16(ring_status->compl_hdr.flow_ring_id);
++
++	DHD_ERROR(("ring status: request_id %d, status 0x%04x, flow ring %d, write_idx %d \n",
++		request_id, status, ring_id, ltoh16(ring_status->write_idx)));
++
++	if (ltoh16(ring_status->compl_hdr.ring_id) != BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT)
++		return;
++	if (status == BCMPCIE_BAD_PHASE) {
++		/* bad phase report from */
++		DHD_ERROR(("Bad phase\n"));
++	}
++	if (status != BCMPCIE_BADOPTION)
++		return;
++
++	if (request_id == DHD_H2D_DBGRING_REQ_PKTID) {
++		if (dhd->prot->h2dring_info_subn != NULL) {
++			if (dhd->prot->h2dring_info_subn->create_pending == TRUE) {
++				DHD_ERROR(("H2D ring create failed for info ring\n"));
++				dhd->prot->h2dring_info_subn->create_pending = FALSE;
++			}
++			else
++				DHD_ERROR(("ring create ID for a ring, create not pending\n"));
++		} else {
++			DHD_ERROR(("%s info submit ring doesn't exist\n", __FUNCTION__));
++		}
++	}
++	else if (request_id == DHD_D2H_DBGRING_REQ_PKTID) {
++		if (dhd->prot->d2hring_info_cpln != NULL) {
++			if (dhd->prot->d2hring_info_cpln->create_pending == TRUE) {
++				DHD_ERROR(("D2H ring create failed for info ring\n"));
++				dhd->prot->d2hring_info_cpln->create_pending = FALSE;
++			}
++			else
++				DHD_ERROR(("ring create ID for info ring, create not pending\n"));
++		} else {
++			DHD_ERROR(("%s info cpl ring doesn't exist\n", __FUNCTION__));
++		}
++	}
++	else {
++		DHD_ERROR(("don;t know how to pair with original request\n"));
++	}
++	/* How do we track this to pair it with ??? */
++	return;
++}
++
++/** called on MSG_TYPE_GEN_STATUS ('general status') message received from dongle */
++static void
++dhd_prot_genstatus_process(dhd_pub_t *dhd, void *msg)
++{
++	pcie_gen_status_t *gen_status = (pcie_gen_status_t *)msg;
++	DHD_ERROR(("ERROR: gen status: request_id %d, STATUS 0x%04x, flow ring %d \n",
++		gen_status->cmn_hdr.request_id, gen_status->compl_hdr.status,
++		gen_status->compl_hdr.flow_ring_id));
++
++	/* How do we track this to pair it with ??? */
++	return;
++}
++
++/**
++ * Called on MSG_TYPE_IOCTLPTR_REQ_ACK ('ioctl ack') message received from dongle, meaning that the
++ * dongle received the ioctl message in dongle memory.
++ */
++static void
++dhd_prot_ioctack_process(dhd_pub_t *dhd, void *msg)
++{
++	ioctl_req_ack_msg_t *ioct_ack = (ioctl_req_ack_msg_t *)msg;
++	unsigned long flags;
++#ifdef DHD_PKTID_AUDIT_RING
++	uint32 pktid = ltoh32(ioct_ack->cmn_hdr.request_id);
++
++	/* Skip audit for ADHD_IOCTL_REQ_PKTID = 0xFFFE */
++	if (pktid != DHD_IOCTL_REQ_PKTID) {
++#ifndef IOCTLRESP_USE_CONSTMEM
++		DHD_PKTID_AUDIT_RING_DEBUG(dhd, dhd->prot->pktid_ctrl_map, pktid,
++			DHD_TEST_IS_ALLOC, msg, D2HRING_CTRL_CMPLT_ITEMSIZE);
++#else
++		DHD_PKTID_AUDIT_RING_DEBUG(dhd, dhd->prot->pktid_map_handle_ioctl, pktid,
++			DHD_TEST_IS_ALLOC, msg, D2HRING_CTRL_CMPLT_ITEMSIZE);
++#endif /* !IOCTLRESP_USE_CONSTMEM */
++	}
++#endif /* DHD_PKTID_AUDIT_RING */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++	if ((dhd->prot->ioctl_state & MSGBUF_IOCTL_ACK_PENDING) &&
++		(dhd->prot->ioctl_state & MSGBUF_IOCTL_RESP_PENDING)) {
++		dhd->prot->ioctl_state &= ~MSGBUF_IOCTL_ACK_PENDING;
++	} else {
++		DHD_ERROR(("%s: received ioctl ACK with state %02x trans_id = %d\n",
++			__FUNCTION__, dhd->prot->ioctl_state, dhd->prot->ioctl_trans_id));
++		prhex("dhd_prot_ioctack_process:",
++			(uchar *)msg, D2HRING_CTRL_CMPLT_ITEMSIZE);
++	}
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	DHD_CTL(("ioctl req ack: request_id %d, status 0x%04x, flow ring %d \n",
++		ioct_ack->cmn_hdr.request_id, ioct_ack->compl_hdr.status,
++		ioct_ack->compl_hdr.flow_ring_id));
++	if (ioct_ack->compl_hdr.status != 0)  {
++		DHD_ERROR(("got an error status for the ioctl request...need to handle that\n"));
++	}
++#ifdef REPORT_FATAL_TIMEOUTS
++	else {
++		dhd_stop_bus_timer(dhd);
++	}
++#endif /* REPORT_FATAL_TIMEOUTS */
++}
++
++/** called on MSG_TYPE_IOCTL_CMPLT message received from dongle */
++static void
++dhd_prot_ioctcmplt_process(dhd_pub_t *dhd, void *msg)
++{
++	dhd_prot_t *prot = dhd->prot;
++	uint32 pkt_id, xt_id;
++	ioctl_comp_resp_msg_t *ioct_resp = (ioctl_comp_resp_msg_t *)msg;
++	void *pkt;
++	unsigned long flags;
++	dhd_dma_buf_t retbuf;
++#ifdef REPORT_FATAL_TIMEOUTS
++	uint16	dhd_xt_id;
++#endif
++
++	memset(&retbuf, 0, sizeof(dhd_dma_buf_t));
++
++	pkt_id = ltoh32(ioct_resp->cmn_hdr.request_id);
++
++#ifdef DHD_PKTID_AUDIT_RING
++#ifndef IOCTLRESP_USE_CONSTMEM
++	DHD_PKTID_AUDIT_RING_DEBUG(dhd, prot->pktid_ctrl_map, pkt_id,
++		DHD_DUPLICATE_FREE, msg, D2HRING_CTRL_CMPLT_ITEMSIZE);
++#else
++	DHD_PKTID_AUDIT_RING_DEBUG(dhd, prot->pktid_map_handle_ioctl, pkt_id,
++		DHD_DUPLICATE_FREE, msg, D2HRING_CTRL_CMPLT_ITEMSIZE);
++#endif /* !IOCTLRESP_USE_CONSTMEM */
++#endif /* DHD_PKTID_AUDIT_RING */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++	if ((prot->ioctl_state & MSGBUF_IOCTL_ACK_PENDING) ||
++		!(prot->ioctl_state & MSGBUF_IOCTL_RESP_PENDING)) {
++		DHD_ERROR(("%s: received ioctl response with state %02x trans_id = %d\n",
++			__FUNCTION__, dhd->prot->ioctl_state, dhd->prot->ioctl_trans_id));
++		prhex("dhd_prot_ioctcmplt_process:",
++			(uchar *)msg, D2HRING_CTRL_CMPLT_ITEMSIZE);
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		return;
++	}
++
++	/* Clear Response pending bit */
++	prot->ioctl_state &= ~MSGBUF_IOCTL_RESP_PENDING;
++
++#ifndef IOCTLRESP_USE_CONSTMEM
++	pkt = dhd_prot_packet_get(dhd, pkt_id, PKTTYPE_IOCTL_RX, TRUE);
++#else
++	dhd_prot_ioctl_ret_buffer_get(dhd, pkt_id, &retbuf);
++	pkt = retbuf.va;
++#endif /* !IOCTLRESP_USE_CONSTMEM */
++	if (!pkt) {
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		DHD_ERROR(("%s: received ioctl response with NULL pkt\n", __FUNCTION__));
++		prhex("dhd_prot_ioctcmplt_process:",
++			(uchar *)msg, D2HRING_CTRL_CMPLT_ITEMSIZE);
++		return;
++	}
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	prot->ioctl_resplen = ltoh16(ioct_resp->resp_len);
++	prot->ioctl_status = ltoh16(ioct_resp->compl_hdr.status);
++	xt_id = ltoh16(ioct_resp->trans_id);
++
++	if (xt_id != prot->ioctl_trans_id || prot->curr_ioctl_cmd != ioct_resp->cmd) {
++		DHD_ERROR(("%s: transaction id(%d %d) or cmd(%d %d) mismatch\n",
++			__FUNCTION__, xt_id, prot->ioctl_trans_id,
++			prot->curr_ioctl_cmd, ioct_resp->cmd));
++#ifdef REPORT_FATAL_TIMEOUTS
++		dhd_stop_cmd_timer(dhd);
++#endif /* REPORT_FATAL_TIMEOUTS */
++		dhd_wakeup_ioctl_event(dhd, IOCTL_RETURN_ON_ERROR);
++		dhd_prot_debug_info_print(dhd);
++#ifdef DHD_FW_COREDUMP
++		if (dhd->memdump_enabled) {
++			/* collect core dump */
++			dhd->memdump_type = DUMP_TYPE_TRANS_ID_MISMATCH;
++			dhd_bus_mem_dump(dhd);
++		}
++#else
++		ASSERT(0);
++#endif /* DHD_FW_COREDUMP */
++		dhd_schedule_reset(dhd);
++		goto exit;
++	}
++#ifdef REPORT_FATAL_TIMEOUTS
++	dhd_xt_id = dhd_get_request_id(dhd);
++	if (xt_id == dhd_xt_id) {
++		dhd_stop_cmd_timer(dhd);
++	} else {
++		DHD_ERROR(("%s: Cmd timer not stopped received xt_id %d stored xt_id %d",
++			__FUNCTION__, xt_id, dhd_xt_id));
++	}
++#endif /* REPORT_FATAL_TIMEOUTS */
++	DHD_CTL(("IOCTL_COMPLETE: req_id %x transid %d status %x resplen %d\n",
++		pkt_id, xt_id, prot->ioctl_status, prot->ioctl_resplen));
++
++	if (prot->ioctl_resplen > 0) {
++#ifndef IOCTLRESP_USE_CONSTMEM
++		bcopy(PKTDATA(dhd->osh, pkt), prot->retbuf.va, prot->ioctl_resplen);
++#else
++		bcopy(pkt, prot->retbuf.va, prot->ioctl_resplen);
++#endif /* !IOCTLRESP_USE_CONSTMEM */
++	}
++
++	/* wake up any dhd_os_ioctl_resp_wait() */
++	dhd_wakeup_ioctl_event(dhd, IOCTL_RETURN_ON_SUCCESS);
++
++exit:
++#ifndef IOCTLRESP_USE_CONSTMEM
++	dhd_prot_packet_free(dhd, pkt,
++		PKTTYPE_IOCTL_RX, FALSE);
++#else
++	free_ioctl_return_buffer(dhd, &retbuf);
++#endif /* !IOCTLRESP_USE_CONSTMEM */
++
++	/* Post another ioctl buf to the device */
++	if (prot->cur_ioctlresp_bufs_posted > 0) {
++		prot->cur_ioctlresp_bufs_posted--;
++	}
++
++	dhd_msgbuf_rxbuf_post_ioctlresp_bufs(dhd);
++}
++
++/** called on MSG_TYPE_TX_STATUS message received from dongle */
++static void BCMFASTPATH
++dhd_prot_txstatus_process(dhd_pub_t *dhd, void *msg)
++{
++	dhd_prot_t *prot = dhd->prot;
++	host_txbuf_cmpl_t * txstatus;
++	unsigned long flags;
++	uint32 pktid;
++	void *pkt;
++	dmaaddr_t pa;
++	uint32 len;
++	void *dmah;
++	void *secdma;
++	bool pkt_fate;
++#ifdef DEVICE_TX_STUCK_DETECT
++	flow_ring_node_t *flow_ring_node;
++	uint16 flowid;
++#endif /* DEVICE_TX_STUCK_DETECT */
++
++
++	txstatus = (host_txbuf_cmpl_t *)msg;
++#ifdef DEVICE_TX_STUCK_DETECT
++	flowid = txstatus->compl_hdr.flow_ring_id;
++	flow_ring_node = DHD_FLOW_RING(dhd, flowid);
++	/**
++	 * Since we got a completion message on this flowid,
++	 * update tx_cmpl time stamp
++	 */
++	flow_ring_node->tx_cmpl = OSL_SYSUPTIME();
++#endif /* DEVICE_TX_STUCK_DETECT */
++
++	/* locks required to protect circular buffer accesses */
++	DHD_GENERAL_LOCK(dhd, flags);
++	pktid = ltoh32(txstatus->cmn_hdr.request_id);
++	pkt_fate = TRUE;
++
++#ifdef DHD_PKTID_AUDIT_RING
++	DHD_PKTID_AUDIT_RING_DEBUG(dhd, dhd->prot->pktid_tx_map, pktid,
++			DHD_DUPLICATE_FREE, msg, D2HRING_TXCMPLT_ITEMSIZE);
++#endif /* DHD_PKTID_AUDIT_RING */
++
++	DHD_INFO(("txstatus for pktid 0x%04x\n", pktid));
++	if (prot->active_tx_count) {
++		prot->active_tx_count--;
++
++		/* Release the Lock when no more tx packets are pending */
++		if (prot->active_tx_count == 0)
++			 DHD_TXFL_WAKE_UNLOCK(dhd);
++	} else {
++		DHD_ERROR(("Extra packets are freed\n"));
++	}
++
++	ASSERT(pktid != 0);
++#if defined(DHD_LB_TXC) && !defined(BCM_SECURE_DMA)
++	{
++		int elem_ix;
++		void **elem;
++		bcm_workq_t *workq;
++		dmaaddr_t pa;
++		uint32 pa_len;
++
++		pkt = DHD_PKTID_TO_NATIVE(dhd, dhd->prot->pktid_tx_map,
++			pktid, pa, pa_len, dmah, secdma, PKTTYPE_DATA_TX);
++
++		workq = &prot->tx_compl_prod;
++		/*
++		 * Produce the packet into the tx_compl workq for the tx compl tasklet
++		 * to consume.
++		 */
++		OSL_PREFETCH(PKTTAG(pkt));
++
++		/* fetch next available slot in workq */
++		elem_ix = bcm_ring_prod(WORKQ_RING(workq), DHD_LB_WORKQ_SZ);
++
++		DHD_PKTTAG_SET_PA((dhd_pkttag_fr_t *)PKTTAG(pkt), pa);
++		DHD_PKTTAG_SET_PA_LEN((dhd_pkttag_fr_t *)PKTTAG(pkt), pa_len);
++
++		if (elem_ix == BCM_RING_FULL) {
++			DHD_ERROR(("tx_compl_prod BCM_RING_FULL\n"));
++			goto workq_ring_full;
++		}
++
++		elem = WORKQ_ELEMENT(void *, &prot->tx_compl_prod, elem_ix);
++		*elem = pkt;
++
++		smp_wmb();
++
++		/* Sync WR index to consumer if the SYNC threshold has been reached */
++		if (++prot->tx_compl_prod_sync >= DHD_LB_WORKQ_SYNC) {
++			bcm_workq_prod_sync(workq);
++			prot->tx_compl_prod_sync = 0;
++		}
++
++		DHD_INFO(("%s: tx_compl_prod pkt<%p> sync<%d>\n",
++			__FUNCTION__, pkt, prot->tx_compl_prod_sync));
++
++		DHD_GENERAL_UNLOCK(dhd, flags);
++
++		return;
++	}
++
++workq_ring_full:
++
++#endif /* !DHD_LB_TXC */
++
++	pkt = DHD_PKTID_TO_NATIVE(dhd, dhd->prot->pktid_tx_map, pktid,
++		pa, len, dmah, secdma, PKTTYPE_DATA_TX);
++
++	if (pkt) {
++		if (SECURE_DMA_ENAB(dhd->osh)) {
++			int offset = 0;
++			BCM_REFERENCE(offset);
++
++			if (dhd->prot->tx_metadata_offset)
++				offset = dhd->prot->tx_metadata_offset + ETHER_HDR_LEN;
++			SECURE_DMA_UNMAP(dhd->osh, (uint) pa,
++				(uint) dhd->prot->tx_metadata_offset, DMA_RX, 0, dmah,
++				secdma, offset);
++		} else
++			DMA_UNMAP(dhd->osh, pa, (uint) len, DMA_RX, 0, dmah);
++#ifdef DMAMAP_STATS
++		dhd->dma_stats.txdata--;
++		dhd->dma_stats.txdata_sz -= len;
++#endif /* DMAMAP_STATS */
++#if defined(DBG_PKT_MON) || defined(DHD_PKT_LOGGING)
++		if (dhd->d11_tx_status) {
++			uint16 tx_status;
++
++			tx_status = ltoh16(txstatus->compl_hdr.status) &
++				WLFC_CTL_PKTFLAG_MASK;
++			pkt_fate = (tx_status == WLFC_CTL_PKTFLAG_DISCARD) ? TRUE : FALSE;
++
++			DHD_DBG_PKT_MON_TX_STATUS(dhd, pkt, pktid, tx_status);
++#ifdef DHD_PKT_LOGGING
++			DHD_PKTLOG_TXS(dhd, pkt, pktid, tx_status);
++#endif /* DHD_PKT_LOGGING */
++		}
++#endif /* DBG_PKT_MON || DHD_PKT_LOGGING */
++#if defined(BCMPCIE)
++		dhd_txcomplete(dhd, pkt, pkt_fate);
++#endif 
++
++#if DHD_DBG_SHOW_METADATA
++		if (dhd->prot->metadata_dbg &&
++		    dhd->prot->tx_metadata_offset && txstatus->metadata_len) {
++			uchar *ptr;
++			/* The Ethernet header of TX frame was copied and removed.
++			 * Here, move the data pointer forward by Ethernet header size.
++			 */
++			PKTPULL(dhd->osh, pkt, ETHER_HDR_LEN);
++			ptr = PKTDATA(dhd->osh, pkt)  - (dhd->prot->tx_metadata_offset);
++			bcm_print_bytes("txmetadata", ptr, txstatus->metadata_len);
++			dhd_prot_print_metadata(dhd, ptr, txstatus->metadata_len);
++		}
++#endif /* DHD_DBG_SHOW_METADATA */
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		PKTFREE(dhd->osh, pkt, TRUE);
++		DHD_GENERAL_LOCK(dhd, flags);
++		DHD_FLOWRING_TXSTATUS_CNT_UPDATE(dhd->bus, txstatus->compl_hdr.flow_ring_id,
++		txstatus->tx_status);
++
++#ifdef DHD_TIMESYNC
++		if (dhd->prot->tx_ts_log_enabled) {
++			ts_timestamp_t *ts = (ts_timestamp_t *)&(txstatus->ts);
++			dhd_timesync_log_tx_timestamp(dhd->ts,
++				txstatus->compl_hdr.flow_ring_id,
++				txstatus->cmn_hdr.if_id,
++				ts->low, ts->high);
++		}
++#endif /* DHD_TIMESYNC */
++	}
++
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	return;
++} /* dhd_prot_txstatus_process */
++
++/** called on MSG_TYPE_WL_EVENT message received from dongle */
++static void
++dhd_prot_event_process(dhd_pub_t *dhd, void *msg)
++{
++	wlevent_req_msg_t *evnt;
++	uint32 bufid;
++	uint16 buflen;
++	int ifidx = 0;
++	void* pkt;
++	unsigned long flags;
++	dhd_prot_t *prot = dhd->prot;
++
++	/* Event complete header */
++	evnt = (wlevent_req_msg_t *)msg;
++	bufid = ltoh32(evnt->cmn_hdr.request_id);
++
++#ifdef DHD_PKTID_AUDIT_RING
++	DHD_PKTID_AUDIT_RING_DEBUG(dhd, dhd->prot->pktid_ctrl_map, bufid,
++			DHD_DUPLICATE_FREE, msg, D2HRING_CTRL_CMPLT_ITEMSIZE);
++#endif /* DHD_PKTID_AUDIT_RING */
++
++	buflen = ltoh16(evnt->event_data_len);
++
++	ifidx = BCMMSGBUF_API_IFIDX(&evnt->cmn_hdr);
++
++	/* Post another rxbuf to the device */
++	if (prot->cur_event_bufs_posted)
++		prot->cur_event_bufs_posted--;
++	dhd_msgbuf_rxbuf_post_event_bufs(dhd);
++
++	/* locks required to protect pktid_map */
++	DHD_GENERAL_LOCK(dhd, flags);
++	pkt = dhd_prot_packet_get(dhd, bufid, PKTTYPE_EVENT_RX, TRUE);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	if (!pkt) {
++		DHD_ERROR(("%s: pkt is NULL for pktid %d\n", __FUNCTION__, bufid));
++		return;
++	}
++
++	/* DMA RX offset updated through shared area */
++	if (dhd->prot->rx_dataoffset)
++		PKTPULL(dhd->osh, pkt, dhd->prot->rx_dataoffset);
++
++	PKTSETLEN(dhd->osh, pkt, buflen);
++
++	dhd_bus_rx_frame(dhd->bus, pkt, ifidx, 1);
++}
++
++/** called on MSG_TYPE_INFO_BUF_CMPLT message received from dongle */
++static void BCMFASTPATH
++dhd_prot_process_infobuf_complete(dhd_pub_t *dhd, void* buf)
++{
++	info_buf_resp_t *resp;
++	uint32 pktid;
++	uint16 buflen;
++	void * pkt;
++	unsigned long flags;
++
++	resp = (info_buf_resp_t *)buf;
++	pktid = ltoh32(resp->cmn_hdr.request_id);
++	buflen = ltoh16(resp->info_data_len);
++
++#ifdef DHD_PKTID_AUDIT_RING
++	DHD_PKTID_AUDIT_RING_DEBUG(dhd, dhd->prot->pktid_ctrl_map, pktid,
++			DHD_DUPLICATE_FREE, buf, D2HRING_INFO_BUFCMPLT_ITEMSIZE);
++#endif /* DHD_PKTID_AUDIT_RING */
++
++	DHD_INFO(("id 0x%04x, len %d, phase 0x%02x, seqnum %d, rx_dataoffset %d\n",
++		pktid, buflen, resp->cmn_hdr.flags, ltoh16(resp->seqnum),
++		dhd->prot->rx_dataoffset));
++
++	if (!dhd->prot->infobufpost) {
++		DHD_ERROR(("infobuf posted are zero, but there is a completion\n"));
++		return;
++	}
++
++	dhd->prot->infobufpost--;
++	dhd_prot_infobufpost(dhd);
++
++	DHD_GENERAL_LOCK(dhd, flags);
++	pkt = dhd_prot_packet_get(dhd, pktid, PKTTYPE_INFO_RX, TRUE);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	if (!pkt)
++		return;
++
++	/* DMA RX offset updated through shared area */
++	if (dhd->prot->rx_dataoffset)
++		PKTPULL(dhd->osh, pkt, dhd->prot->rx_dataoffset);
++
++	PKTSETLEN(dhd->osh, pkt, buflen);
++
++	/* info ring "debug" data, which is not a 802.3 frame, is sent/hacked with a
++	 * special ifidx of -1.  This is just internal to dhd to get the data to
++	 * dhd_linux.c:dhd_rx_frame() from here (dhd_prot_infobuf_cmplt_process).
++	 */
++	dhd_bus_rx_frame(dhd->bus, pkt, DHD_EVENT_IF /* ifidx HACK */, 1);
++}
++
++/** Stop protocol: sync w/dongle state. */
++void dhd_prot_stop(dhd_pub_t *dhd)
++{
++	ASSERT(dhd);
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++}
++
++/* Add any protocol-specific data header.
++ * Caller must reserve prot_hdrlen prepend space.
++ */
++void BCMFASTPATH
++dhd_prot_hdrpush(dhd_pub_t *dhd, int ifidx, void *PKTBUF)
++{
++	return;
++}
++
++uint
++dhd_prot_hdrlen(dhd_pub_t *dhd, void *PKTBUF)
++{
++	return 0;
++}
++
++
++#define PKTBUF pktbuf
++
++/**
++ * Called when a tx ethernet packet has been dequeued from a flow queue, and has to be inserted in
++ * the corresponding flow ring.
++ */
++int BCMFASTPATH
++dhd_prot_txdata(dhd_pub_t *dhd, void *PKTBUF, uint8 ifidx)
++{
++	unsigned long flags;
++	dhd_prot_t *prot = dhd->prot;
++	host_txbuf_post_t *txdesc = NULL;
++	dmaaddr_t pa, meta_pa;
++	uint8 *pktdata;
++	uint32 pktlen;
++	uint32 pktid;
++	uint8	prio;
++	uint16 flowid = 0;
++	uint16 alloced = 0;
++	uint16	headroom;
++	msgbuf_ring_t *ring;
++	flow_ring_table_t *flow_ring_table;
++	flow_ring_node_t *flow_ring_node;
++
++	if (dhd->flow_ring_table == NULL) {
++		return BCME_NORESOURCE;
++	}
++
++	flowid = DHD_PKT_GET_FLOWID(PKTBUF);
++	flow_ring_table = (flow_ring_table_t *)dhd->flow_ring_table;
++	flow_ring_node = (flow_ring_node_t *)&flow_ring_table[flowid];
++
++	ring = (msgbuf_ring_t *)flow_ring_node->prot_info;
++
++#ifdef PCIE_INB_DW
++	if (dhd_prot_inc_hostactive_devwake_assert(dhd->bus) != BCME_OK)
++		return BCME_ERROR;
++#endif /* PCIE_INB_DW */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	/* Create a unique 32-bit packet id */
++	pktid = DHD_NATIVE_TO_PKTID_RSV(dhd, dhd->prot->pktid_tx_map,
++		PKTBUF, PKTTYPE_DATA_TX);
++#if defined(DHD_PCIE_PKTID)
++	if (pktid == DHD_PKTID_INVALID) {
++		DHD_ERROR(("%s: Pktid pool depleted.\n", __FUNCTION__));
++		/*
++		 * If we return error here, the caller would queue the packet
++		 * again. So we'll just free the skb allocated in DMA Zone.
++		 * Since we have not freed the original SKB yet the caller would
++		 * requeue the same.
++		 */
++		goto err_no_res_pktfree;
++	}
++#endif /* DHD_PCIE_PKTID */
++
++	/* Reserve space in the circular buffer */
++	txdesc = (host_txbuf_post_t *)
++		dhd_prot_alloc_ring_space(dhd, ring, 1, &alloced, FALSE);
++	if (txdesc == NULL) {
++		DHD_INFO(("%s:%d: HTOD Msgbuf Not available TxCount = %d\n",
++			__FUNCTION__, __LINE__, prot->active_tx_count));
++		goto err_free_pktid;
++	}
++
++#ifdef DBG_PKT_MON
++	DHD_DBG_PKT_MON_TX(dhd, PKTBUF, pktid);
++#endif /* DBG_PKT_MON */
++#ifdef DHD_PKT_LOGGING
++	DHD_PKTLOG_TX(dhd, PKTBUF, pktid);
++#endif /* DHD_PKT_LOGGING */
++
++
++	/* Extract the data pointer and length information */
++	pktdata = PKTDATA(dhd->osh, PKTBUF);
++	pktlen  = PKTLEN(dhd->osh, PKTBUF);
++
++	/* Ethernet header: Copy before we cache flush packet using DMA_MAP */
++	bcopy(pktdata, txdesc->txhdr, ETHER_HDR_LEN);
++
++	/* Extract the ethernet header and adjust the data pointer and length */
++	pktdata = PKTPULL(dhd->osh, PKTBUF, ETHER_HDR_LEN);
++	pktlen -= ETHER_HDR_LEN;
++
++	/* Map the data pointer to a DMA-able address */
++	if (SECURE_DMA_ENAB(dhd->osh)) {
++		int offset = 0;
++		BCM_REFERENCE(offset);
++
++		if (prot->tx_metadata_offset)
++			offset = prot->tx_metadata_offset + ETHER_HDR_LEN;
++
++		pa = SECURE_DMA_MAP(dhd->osh, PKTDATA(dhd->osh, PKTBUF), pktlen,
++			DMA_TX, PKTBUF, 0, ring->dma_buf.secdma, offset);
++	}
++#ifndef BCM_SECURE_DMA
++	else
++		pa = DMA_MAP(dhd->osh, PKTDATA(dhd->osh, PKTBUF), pktlen, DMA_TX, PKTBUF, 0);
++#endif /* #ifndef BCM_SECURE_DMA */
++
++	if (PHYSADDRISZERO(pa)) {
++		DHD_ERROR(("%s: Something really bad, unless 0 is "
++			"a valid phyaddr for pa\n", __FUNCTION__));
++		ASSERT(0);
++		goto err_rollback_idx;
++	}
++
++#ifdef DMAMAP_STATS
++	dhd->dma_stats.txdata++;
++	dhd->dma_stats.txdata_sz += pktlen;
++#endif /* DMAMAP_STATS */
++	/* No need to lock. Save the rest of the packet's metadata */
++	DHD_NATIVE_TO_PKTID_SAVE(dhd, dhd->prot->pktid_tx_map, PKTBUF, pktid,
++	    pa, pktlen, DMA_TX, NULL, ring->dma_buf.secdma, PKTTYPE_DATA_TX);
++
++#ifdef TXP_FLUSH_NITEMS
++	if (ring->pend_items_count == 0)
++		ring->start_addr = (void *)txdesc;
++	ring->pend_items_count++;
++#endif
++
++	/* Form the Tx descriptor message buffer */
++
++	/* Common message hdr */
++	txdesc->cmn_hdr.msg_type = MSG_TYPE_TX_POST;
++	txdesc->cmn_hdr.if_id = ifidx;
++	txdesc->cmn_hdr.flags = ring->current_phase;
++
++	txdesc->flags = BCMPCIE_PKT_FLAGS_FRAME_802_3;
++	prio = (uint8)PKTPRIO(PKTBUF);
++
++
++	txdesc->flags |= (prio & 0x7) << BCMPCIE_PKT_FLAGS_PRIO_SHIFT;
++	txdesc->seg_cnt = 1;
++
++	txdesc->data_len = htol16((uint16) pktlen);
++	txdesc->data_buf_addr.high_addr = htol32(PHYSADDRHI(pa));
++	txdesc->data_buf_addr.low_addr  = htol32(PHYSADDRLO(pa));
++
++	/* Move data pointer to keep ether header in local PKTBUF for later reference */
++	PKTPUSH(dhd->osh, PKTBUF, ETHER_HDR_LEN);
++
++	/* Handle Tx metadata */
++	headroom = (uint16)PKTHEADROOM(dhd->osh, PKTBUF);
++	if (prot->tx_metadata_offset && (headroom < prot->tx_metadata_offset))
++		DHD_ERROR(("No headroom for Metadata tx %d %d\n",
++		prot->tx_metadata_offset, headroom));
++
++	if (prot->tx_metadata_offset && (headroom >= prot->tx_metadata_offset)) {
++		DHD_TRACE(("Metadata in tx %d\n", prot->tx_metadata_offset));
++
++		/* Adjust the data pointer to account for meta data in DMA_MAP */
++		PKTPUSH(dhd->osh, PKTBUF, prot->tx_metadata_offset);
++
++		if (SECURE_DMA_ENAB(dhd->osh)) {
++			meta_pa = SECURE_DMA_MAP_TXMETA(dhd->osh, PKTDATA(dhd->osh, PKTBUF),
++				prot->tx_metadata_offset + ETHER_HDR_LEN, DMA_RX, PKTBUF,
++				0, ring->dma_buf.secdma);
++		}
++#ifndef BCM_SECURE_DMA
++		else
++			meta_pa = DMA_MAP(dhd->osh, PKTDATA(dhd->osh, PKTBUF),
++				prot->tx_metadata_offset, DMA_RX, PKTBUF, 0);
++#endif /* #ifndef BCM_SECURE_DMA */
++
++		if (PHYSADDRISZERO(meta_pa)) {
++			/* Unmap the data pointer to a DMA-able address */
++			if (SECURE_DMA_ENAB(dhd->osh)) {
++
++				int offset = 0;
++				BCM_REFERENCE(offset);
++
++				if (prot->tx_metadata_offset) {
++					offset = prot->tx_metadata_offset + ETHER_HDR_LEN;
++				}
++
++				SECURE_DMA_UNMAP(dhd->osh, pa, pktlen,
++					DMA_TX, 0, DHD_DMAH_NULL, ring->dma_buf.secdma, offset);
++			}
++#ifndef BCM_SECURE_DMA
++			else {
++				DMA_UNMAP(dhd->osh, pa, pktlen, DMA_TX, 0, DHD_DMAH_NULL);
++			}
++#endif /* #ifndef BCM_SECURE_DMA */
++#ifdef TXP_FLUSH_NITEMS
++			/* update pend_items_count */
++			ring->pend_items_count--;
++#endif /* TXP_FLUSH_NITEMS */
++
++			DHD_ERROR(("%s: Something really bad, unless 0 is "
++				"a valid phyaddr for meta_pa\n", __FUNCTION__));
++			ASSERT(0);
++			goto err_rollback_idx;
++		}
++
++		/* Adjust the data pointer back to original value */
++		PKTPULL(dhd->osh, PKTBUF, prot->tx_metadata_offset);
++
++		txdesc->metadata_buf_len = prot->tx_metadata_offset;
++		txdesc->metadata_buf_addr.high_addr = htol32(PHYSADDRHI(meta_pa));
++		txdesc->metadata_buf_addr.low_addr = htol32(PHYSADDRLO(meta_pa));
++	} else {
++		txdesc->metadata_buf_len = htol16(0);
++		txdesc->metadata_buf_addr.high_addr = 0;
++		txdesc->metadata_buf_addr.low_addr = 0;
++	}
++
++#ifdef DHD_PKTID_AUDIT_RING
++	DHD_PKTID_AUDIT(dhd, prot->pktid_tx_map, pktid, DHD_DUPLICATE_ALLOC);
++#endif /* DHD_PKTID_AUDIT_RING */
++
++	txdesc->cmn_hdr.request_id = htol32(pktid);
++
++	DHD_TRACE(("txpost: data_len %d, pktid 0x%04x\n", txdesc->data_len,
++		txdesc->cmn_hdr.request_id));
++
++	/* Update the write pointer in TCM & ring bell */
++#ifdef TXP_FLUSH_NITEMS
++	/* Flush if we have either hit the txp_threshold or if this msg is */
++	/* occupying the last slot in the flow_ring - before wrap around.  */
++	if ((ring->pend_items_count == prot->txp_threshold) ||
++		((uint8 *) txdesc == (uint8 *) DHD_RING_END_VA(ring))) {
++		dhd_prot_txdata_write_flush(dhd, flowid, TRUE);
++	}
++#else
++	/* update ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ring, txdesc, 1);
++#endif
++
++	prot->active_tx_count++;
++
++	/*
++	 * Take a wake lock, do not sleep if we have atleast one packet
++	 * to finish.
++	 */
++	if (prot->active_tx_count >= 1)
++		DHD_TXFL_WAKE_LOCK_TIMEOUT(dhd, MAX_TX_TIMEOUT);
++
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++
++	return BCME_OK;
++
++err_rollback_idx:
++	/* roll back write pointer for unprocessed message */
++	if (ring->wr == 0) {
++		ring->wr = ring->max_items - 1;
++	} else {
++		ring->wr--;
++		if (ring->wr == 0) {
++			DHD_INFO(("%s: flipping the phase now\n", ring->name));
++			ring->current_phase = ring->current_phase ?
++				0 : BCMPCIE_CMNHDR_PHASE_BIT_INIT;
++		}
++	}
++
++err_free_pktid:
++#if defined(DHD_PCIE_PKTID)
++	{
++		void *dmah;
++		void *secdma;
++		/* Free up the PKTID. physaddr and pktlen will be garbage. */
++		DHD_PKTID_TO_NATIVE(dhd, dhd->prot->pktid_tx_map, pktid,
++			pa, pktlen, dmah, secdma, PKTTYPE_NO_CHECK);
++	}
++
++err_no_res_pktfree:
++#endif /* DHD_PCIE_PKTID */
++
++
++
++	DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++	return BCME_NORESOURCE;
++} /* dhd_prot_txdata */
++
++/* called with a lock */
++/** optimization to write "n" tx items at a time to ring */
++void BCMFASTPATH
++dhd_prot_txdata_write_flush(dhd_pub_t *dhd, uint16 flowid, bool in_lock)
++{
++#ifdef TXP_FLUSH_NITEMS
++	unsigned long flags = 0;
++	flow_ring_table_t *flow_ring_table;
++	flow_ring_node_t *flow_ring_node;
++	msgbuf_ring_t *ring;
++
++	if (dhd->flow_ring_table == NULL) {
++		return;
++	}
++
++	if (!in_lock) {
++		DHD_GENERAL_LOCK(dhd, flags);
++	}
++
++	flow_ring_table = (flow_ring_table_t *)dhd->flow_ring_table;
++	flow_ring_node = (flow_ring_node_t *)&flow_ring_table[flowid];
++	ring = (msgbuf_ring_t *)flow_ring_node->prot_info;
++
++	if (ring->pend_items_count) {
++		/* update ring's WR index and ring doorbell to dongle */
++		dhd_prot_ring_write_complete(dhd, ring, ring->start_addr,
++			ring->pend_items_count);
++		ring->pend_items_count = 0;
++		ring->start_addr = NULL;
++	}
++
++	if (!in_lock) {
++		DHD_GENERAL_UNLOCK(dhd, flags);
++	}
++#endif /* TXP_FLUSH_NITEMS */
++}
++
++#undef PKTBUF	/* Only defined in the above routine */
++
++int BCMFASTPATH
++dhd_prot_hdrpull(dhd_pub_t *dhd, int *ifidx, void *pkt, uchar *buf, uint *len)
++{
++	return 0;
++}
++
++/** post a set of receive buffers to the dongle */
++static void BCMFASTPATH
++dhd_prot_return_rxbuf(dhd_pub_t *dhd, uint32 pktid, uint32 rxcnt)
++{
++	dhd_prot_t *prot = dhd->prot;
++#if defined(DHD_LB_RXC)
++	int elem_ix;
++	uint32 *elem;
++	bcm_workq_t *workq;
++
++	workq = &prot->rx_compl_prod;
++
++	/* Produce the work item */
++	elem_ix = bcm_ring_prod(WORKQ_RING(workq), DHD_LB_WORKQ_SZ);
++	if (elem_ix == BCM_RING_FULL) {
++		DHD_ERROR(("%s LB RxCompl workQ is full\n", __FUNCTION__));
++		ASSERT(0);
++		return;
++	}
++
++	elem = WORKQ_ELEMENT(uint32, workq, elem_ix);
++	*elem = pktid;
++
++	smp_wmb();
++
++	/* Sync WR index to consumer if the SYNC threshold has been reached */
++	if (++prot->rx_compl_prod_sync >= DHD_LB_WORKQ_SYNC) {
++		bcm_workq_prod_sync(workq);
++		prot->rx_compl_prod_sync = 0;
++	}
++
++	DHD_INFO(("%s: rx_compl_prod pktid<%u> sync<%d>\n",
++		__FUNCTION__, pktid, prot->rx_compl_prod_sync));
++
++#endif /* DHD_LB_RXC */
++
++	if (prot->rxbufpost >= rxcnt) {
++		prot->rxbufpost -= (uint16)rxcnt;
++	} else {
++		/* ASSERT(0); */
++		prot->rxbufpost = 0;
++	}
++
++#if !defined(DHD_LB_RXC)
++	if (prot->rxbufpost <= (prot->max_rxbufpost - RXBUFPOST_THRESHOLD))
++		dhd_msgbuf_rxbuf_post(dhd, FALSE); /* alloc pkt ids */
++#endif /* !DHD_LB_RXC */
++	return;
++}
++
++/* called before an ioctl is sent to the dongle */
++static void
++dhd_prot_wlioctl_intercept(dhd_pub_t *dhd, wl_ioctl_t * ioc, void * buf)
++{
++	dhd_prot_t *prot = dhd->prot;
++
++	if (ioc->cmd == WLC_SET_VAR && buf != NULL && !strcmp(buf, "pcie_bus_tput")) {
++		int slen = 0;
++		pcie_bus_tput_params_t *tput_params;
++
++		slen = strlen("pcie_bus_tput") + 1;
++		tput_params = (pcie_bus_tput_params_t*)((char *)buf + slen);
++		bcopy(&prot->host_bus_throughput_buf.pa, &tput_params->host_buf_addr,
++			sizeof(tput_params->host_buf_addr));
++		tput_params->host_buf_len = DHD_BUS_TPUT_BUF_LEN;
++	}
++}
++
++
++/** Use protocol to issue ioctl to dongle. Only one ioctl may be in transit. */
++int dhd_prot_ioctl(dhd_pub_t *dhd, int ifidx, wl_ioctl_t * ioc, void * buf, int len)
++{
++	int ret = -1;
++	uint8 action;
++
++	if ((dhd->busstate == DHD_BUS_DOWN) || dhd->hang_was_sent) {
++		DHD_ERROR(("%s : bus is down. we have nothing to do - bs: %d, has: %d\n",
++				__FUNCTION__, dhd->busstate, dhd->hang_was_sent));
++		goto done;
++	}
++
++	if (dhd->busstate == DHD_BUS_SUSPEND) {
++		DHD_ERROR(("%s : bus is suspended\n", __FUNCTION__));
++		goto done;
++	}
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (ioc->cmd == WLC_SET_PM) {
++		DHD_TRACE_HW4(("%s: SET PM to %d\n", __FUNCTION__, buf ? *(char *)buf : 0));
++	}
++
++	ASSERT(len <= WLC_IOCTL_MAXLEN);
++
++	if (len > WLC_IOCTL_MAXLEN)
++		goto done;
++
++	action = ioc->set;
++
++	dhd_prot_wlioctl_intercept(dhd, ioc, buf);
++
++	if (action & WL_IOCTL_ACTION_SET) {
++		ret = dhd_msgbuf_set_ioctl(dhd, ifidx, ioc->cmd, buf, len, action);
++	} else {
++		ret = dhd_msgbuf_query_ioctl(dhd, ifidx, ioc->cmd, buf, len, action);
++		if (ret > 0)
++			ioc->used = ret;
++	}
++
++	/* Too many programs assume ioctl() returns 0 on success */
++	if (ret >= 0) {
++		ret = 0;
++	} else {
++		DHD_INFO(("%s: status ret value is %d \n", __FUNCTION__, ret));
++		dhd->dongle_error = ret;
++	}
++
++	if (!ret && ioc->cmd == WLC_SET_VAR && buf != NULL) {
++		/* Intercept the wme_dp ioctl here */
++		if (!strcmp(buf, "wme_dp")) {
++			int slen, val = 0;
++
++			slen = strlen("wme_dp") + 1;
++			if (len >= (int)(slen + sizeof(int)))
++				bcopy(((char *)buf + slen), &val, sizeof(int));
++			dhd->wme_dp = (uint8) ltoh32(val);
++		}
++
++	}
++
++done:
++	return ret;
++
++} /* dhd_prot_ioctl */
++
++/** test / loopback */
++
++int
++dhdmsgbuf_lpbk_req(dhd_pub_t *dhd, uint len)
++{
++	unsigned long flags;
++	dhd_prot_t *prot = dhd->prot;
++	uint16 alloced = 0;
++
++	ioct_reqst_hdr_t *ioct_rqst;
++
++	uint16 hdrlen = sizeof(ioct_reqst_hdr_t);
++	uint16 msglen = len + hdrlen;
++	msgbuf_ring_t *ring = &prot->h2dring_ctrl_subn;
++
++	msglen = ALIGN_SIZE(msglen, DMA_ALIGN_LEN);
++	msglen = LIMIT_TO_MAX(msglen, MSGBUF_MAX_MSG_SIZE);
++
++#ifdef PCIE_INB_DW
++	if (dhd_prot_inc_hostactive_devwake_assert(dhd->bus) != BCME_OK)
++		return BCME_ERROR;
++#endif /* PCIE_INB_DW */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	ioct_rqst = (ioct_reqst_hdr_t *)
++		dhd_prot_alloc_ring_space(dhd, ring, 1, &alloced, FALSE);
++
++	if (ioct_rqst == NULL) {
++		DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++		dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++		return 0;
++	}
++
++	{
++		uint8 *ptr;
++		uint16 i;
++
++		ptr = (uint8 *)ioct_rqst;
++		for (i = 0; i < msglen; i++) {
++			ptr[i] = i % 256;
++		}
++	}
++
++	/* Common msg buf hdr */
++	ioct_rqst->msg.epoch = ring->seqnum % H2D_EPOCH_MODULO;
++	ring->seqnum++;
++
++	ioct_rqst->msg.msg_type = MSG_TYPE_LOOPBACK;
++	ioct_rqst->msg.if_id = 0;
++	ioct_rqst->msg.flags = ring->current_phase;
++
++	bcm_print_bytes("LPBK REQ: ", (uint8 *)ioct_rqst, msglen);
++
++	/* update ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ring, ioct_rqst, 1);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++
++	return 0;
++}
++
++/** test / loopback */
++void dmaxfer_free_dmaaddr(dhd_pub_t *dhd, dhd_dmaxfer_t *dmaxfer)
++{
++	if (dmaxfer == NULL)
++		return;
++
++	dhd_dma_buf_free(dhd, &dmaxfer->srcmem);
++	dhd_dma_buf_free(dhd, &dmaxfer->dstmem);
++}
++
++/** test / loopback */
++int
++dhd_prepare_schedule_dmaxfer_free(dhd_pub_t *dhdp)
++{
++	dhd_prot_t *prot = dhdp->prot;
++	dhd_dmaxfer_t *dmaxfer = &prot->dmaxfer;
++	dmaxref_mem_map_t *dmap = NULL;
++
++	dmap = MALLOCZ(dhdp->osh, sizeof(dmaxref_mem_map_t));
++	if (!dmap) {
++		DHD_ERROR(("%s: dmap alloc failed\n", __FUNCTION__));
++		goto mem_alloc_fail;
++	}
++	dmap->srcmem = &(dmaxfer->srcmem);
++	dmap->dstmem = &(dmaxfer->dstmem);
++
++	DMAXFER_FREE(dhdp, dmap);
++	return BCME_OK;
++
++mem_alloc_fail:
++	if (dmap) {
++		MFREE(dhdp->osh, dmap, sizeof(dmaxref_mem_map_t));
++		dmap = NULL;
++	}
++	return BCME_NOMEM;
++} /* dhd_prepare_schedule_dmaxfer_free */
++
++
++/** test / loopback */
++void
++dmaxfer_free_prev_dmaaddr(dhd_pub_t *dhdp, dmaxref_mem_map_t *dmmap)
++{
++
++	dhd_dma_buf_free(dhdp, dmmap->srcmem);
++	dhd_dma_buf_free(dhdp, dmmap->dstmem);
++
++	MFREE(dhdp->osh, dmmap, sizeof(dmaxref_mem_map_t));
++	dmmap = NULL;
++
++} /* dmaxfer_free_prev_dmaaddr */
++
++
++/** test / loopback */
++int dmaxfer_prepare_dmaaddr(dhd_pub_t *dhd, uint len,
++	uint srcdelay, uint destdelay, dhd_dmaxfer_t *dmaxfer)
++{
++	uint i;
++	if (!dmaxfer)
++		return BCME_ERROR;
++
++	/* First free up existing buffers */
++	dmaxfer_free_dmaaddr(dhd, dmaxfer);
++
++	if (dhd_dma_buf_alloc(dhd, &dmaxfer->srcmem, len)) {
++		return BCME_NOMEM;
++	}
++
++	if (dhd_dma_buf_alloc(dhd, &dmaxfer->dstmem, len + 8)) {
++		dhd_dma_buf_free(dhd, &dmaxfer->srcmem);
++		return BCME_NOMEM;
++	}
++
++	dmaxfer->len = len;
++
++	/* Populate source with a pattern */
++	for (i = 0; i < dmaxfer->len; i++) {
++		((uint8*)dmaxfer->srcmem.va)[i] = i % 256;
++	}
++	OSL_CACHE_FLUSH(dmaxfer->srcmem.va, dmaxfer->len);
++
++	dmaxfer->srcdelay = srcdelay;
++	dmaxfer->destdelay = destdelay;
++
++	return BCME_OK;
++} /* dmaxfer_prepare_dmaaddr */
++
++static void
++dhd_msgbuf_dmaxfer_process(dhd_pub_t *dhd, void *msg)
++{
++	dhd_prot_t *prot = dhd->prot;
++	uint64 end_usec;
++	pcie_dmaxfer_cmplt_t *cmplt = (pcie_dmaxfer_cmplt_t *)msg;
++
++	BCM_REFERENCE(cmplt);
++	DHD_INFO(("DMA status: %d\n", cmplt->compl_hdr.status));
++	OSL_CACHE_INV(prot->dmaxfer.dstmem.va, prot->dmaxfer.len);
++	if (prot->dmaxfer.srcmem.va && prot->dmaxfer.dstmem.va) {
++		if (memcmp(prot->dmaxfer.srcmem.va,
++		        prot->dmaxfer.dstmem.va, prot->dmaxfer.len)) {
++			prhex("XFER SRC: ",
++			    prot->dmaxfer.srcmem.va, prot->dmaxfer.len);
++			prhex("XFER DST: ",
++			    prot->dmaxfer.dstmem.va, prot->dmaxfer.len);
++		        DHD_ERROR(("DMA failed\n"));
++		}
++		else {
++			if (prot->dmaxfer.d11_lpbk) {
++				DHD_ERROR(("DMA successful with d11 loopback\n"));
++			} else {
++				DHD_ERROR(("DMA successful without d11 loopback\n"));
++			}
++		}
++	}
++	end_usec = OSL_SYSUPTIME_US();
++	dhd_prepare_schedule_dmaxfer_free(dhd);
++	end_usec -= prot->dmaxfer.start_usec;
++	DHD_ERROR(("DMA loopback %d bytes in %llu usec, %u kBps\n",
++		prot->dmaxfer.len, end_usec,
++		(prot->dmaxfer.len * (1000 * 1000 / 1024) / (uint32)(end_usec + 1))));
++	dhd->prot->dmaxfer.in_progress = FALSE;
++}
++
++/** Test functionality.
++ * Transfers bytes from host to dongle and to host again using DMA
++ * This function is not reentrant, as prot->dmaxfer.in_progress is not protected
++ * by a spinlock.
++ */
++int
++dhdmsgbuf_dmaxfer_req(dhd_pub_t *dhd, uint len, uint srcdelay, uint destdelay, uint d11_lpbk)
++{
++	unsigned long flags;
++	int ret = BCME_OK;
++	dhd_prot_t *prot = dhd->prot;
++	pcie_dma_xfer_params_t *dmap;
++	uint32 xferlen = LIMIT_TO_MAX(len, DMA_XFER_LEN_LIMIT);
++	uint16 alloced = 0;
++	msgbuf_ring_t *ring = &prot->h2dring_ctrl_subn;
++
++	if (prot->dmaxfer.in_progress) {
++		DHD_ERROR(("DMA is in progress...\n"));
++		return ret;
++	}
++
++	prot->dmaxfer.in_progress = TRUE;
++	if ((ret = dmaxfer_prepare_dmaaddr(dhd, xferlen, srcdelay, destdelay,
++	        &prot->dmaxfer)) != BCME_OK) {
++		prot->dmaxfer.in_progress = FALSE;
++		return ret;
++	}
++
++#ifdef PCIE_INB_DW
++	if (dhd_prot_inc_hostactive_devwake_assert(dhd->bus) != BCME_OK)
++		return BCME_ERROR;
++#endif /* PCIE_INB_DW */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	dmap = (pcie_dma_xfer_params_t *)
++		dhd_prot_alloc_ring_space(dhd, ring, 1, &alloced, FALSE);
++
++	if (dmap == NULL) {
++		dmaxfer_free_dmaaddr(dhd, &prot->dmaxfer);
++		prot->dmaxfer.in_progress = FALSE;
++		DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++		dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++		return BCME_NOMEM;
++	}
++
++	/* Common msg buf hdr */
++	dmap->cmn_hdr.msg_type = MSG_TYPE_LPBK_DMAXFER;
++	dmap->cmn_hdr.request_id = htol32(DHD_FAKE_PKTID);
++	dmap->cmn_hdr.epoch = ring->seqnum % H2D_EPOCH_MODULO;
++	dmap->cmn_hdr.flags = ring->current_phase;
++	ring->seqnum++;
++
++	dmap->host_input_buf_addr.high = htol32(PHYSADDRHI(prot->dmaxfer.srcmem.pa));
++	dmap->host_input_buf_addr.low = htol32(PHYSADDRLO(prot->dmaxfer.srcmem.pa));
++	dmap->host_ouput_buf_addr.high = htol32(PHYSADDRHI(prot->dmaxfer.dstmem.pa));
++	dmap->host_ouput_buf_addr.low = htol32(PHYSADDRLO(prot->dmaxfer.dstmem.pa));
++	dmap->xfer_len = htol32(prot->dmaxfer.len);
++	dmap->srcdelay = htol32(prot->dmaxfer.srcdelay);
++	dmap->destdelay = htol32(prot->dmaxfer.destdelay);
++	prot->dmaxfer.d11_lpbk = d11_lpbk ? 1 : 0;
++	dmap->flags = (prot->dmaxfer.d11_lpbk << PCIE_DMA_XFER_FLG_D11_LPBK_SHIFT)
++			& PCIE_DMA_XFER_FLG_D11_LPBK_MASK;
++
++	/* update ring's WR index and ring doorbell to dongle */
++	prot->dmaxfer.start_usec = OSL_SYSUPTIME_US();
++	dhd_prot_ring_write_complete(dhd, ring, dmap, 1);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++
++	DHD_INFO(("DMA Started...\n"));
++
++	return BCME_OK;
++} /* dhdmsgbuf_dmaxfer_req */
++
++/** Called in the process of submitting an ioctl to the dongle */
++static int
++dhd_msgbuf_query_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len, uint8 action)
++{
++	int ret = 0;
++	uint copylen = 0;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (cmd == WLC_GET_VAR && buf)
++	{
++		if (!len || !*(uint8 *)buf) {
++			DHD_ERROR(("%s(): Zero length bailing\n", __FUNCTION__));
++			ret = BCME_BADARG;
++			goto done;
++		}
++
++		/* Respond "bcmerror" and "bcmerrorstr" with local cache */
++		copylen = MIN(len, BCME_STRLEN);
++
++		if ((len >= strlen("bcmerrorstr")) &&
++			(!strcmp((char *)buf, "bcmerrorstr"))) {
++
++			strncpy((char *)buf, bcmerrorstr(dhd->dongle_error), copylen);
++			*(uint8 *)((uint8 *)buf + (copylen - 1)) = '\0';
++
++			goto done;
++		} else if ((len >= strlen("bcmerror")) &&
++			!strcmp((char *)buf, "bcmerror")) {
++
++			*(uint32 *)(uint32 *)buf = dhd->dongle_error;
++
++			goto done;
++		}
++	}
++
++
++	DHD_CTL(("query_ioctl: ACTION %d ifdix %d cmd %d len %d \n",
++	    action, ifidx, cmd, len));
++#ifdef REPORT_FATAL_TIMEOUTS
++	/*
++	 * These timers "should" be started before sending H2D interrupt.
++	 * Think of the scenario where H2D interrupt is fired and the Dongle
++	 * responds back immediately. From the DPC we would stop the cmd, bus
++	 * timers. But the process context could have switched out leading to
++	 * a situation where the timers are Not started yet, but are actually stopped.
++	 *
++	 * Disable preemption from the time we start the timer until we are done
++	 * with seding H2D interrupts.
++	 */
++	OSL_DISABLE_PREEMPTION(dhd->osh);
++	dhd_set_request_id(dhd, dhd->prot->ioctl_trans_id+1, cmd);
++	dhd_start_cmd_timer(dhd);
++	dhd_start_bus_timer(dhd);
++#endif /* REPORT_FATAL_TIMEOUTS */
++
++	ret = dhd_fillup_ioct_reqst(dhd, (uint16)len, cmd, buf, ifidx);
++
++#ifdef REPORT_FATAL_TIMEOUTS
++	/* For some reason if we fail to ring door bell, stop the timers */
++	if (ret < 0) {
++		DHD_ERROR(("%s(): dhd_fillup_ioct_reqst failed \r\n", __FUNCTION__));
++		dhd_stop_cmd_timer(dhd);
++		dhd_stop_bus_timer(dhd);
++		OSL_ENABLE_PREEMPTION(dhd->osh);
++		goto done;
++	}
++	OSL_ENABLE_PREEMPTION(dhd->osh);
++#else
++	if (ret < 0) {
++		DHD_ERROR(("%s(): dhd_fillup_ioct_reqst failed \r\n", __FUNCTION__));
++		goto done;
++	}
++#endif /* REPORT_FATAL_TIMEOUTS */
++
++	/* wait for IOCTL completion message from dongle and get first fragment */
++	ret = dhd_msgbuf_wait_ioctl_cmplt(dhd, len, buf);
++
++done:
++	return ret;
++}
++
++/**
++ * Waits for IOCTL completion message from the dongle, copies this into caller
++ * provided parameter 'buf'.
++ */
++static int
++dhd_msgbuf_wait_ioctl_cmplt(dhd_pub_t *dhd, uint32 len, void *buf)
++{
++	dhd_prot_t *prot = dhd->prot;
++	int timeleft;
++	unsigned long flags;
++	int ret = 0;
++	static uint cnt = 0;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (dhd_query_bus_erros(dhd)) {
++		ret = -EIO;
++		goto out;
++	}
++
++	timeleft = dhd_os_ioctl_resp_wait(dhd, (uint *)&prot->ioctl_received);
++
++#ifdef DHD_RECOVER_TIMEOUT
++	if (prot->ioctl_received == 0) {
++		uint32 intstatus = 0;
++		uint32 intmask = 0;
++		intstatus = si_corereg(dhd->bus->sih,
++			dhd->bus->sih->buscoreidx, PCIMailBoxInt, 0, 0);
++		intmask = si_corereg(dhd->bus->sih,
++			dhd->bus->sih->buscoreidx, PCIMailBoxMask, 0, 0);
++		if ((intstatus) && (!intmask) && (timeleft == 0) && (!dhd_query_bus_erros(dhd)))
++		{
++			DHD_ERROR(("%s: iovar timeout trying again intstatus=%x intmask=%x\n",
++				__FUNCTION__, intstatus, intmask));
++			DHD_ERROR(("\n ------- DUMPING INTR enable/disable counters\r\n"));
++			DHD_ERROR(("resume_intr_enable_count=%lu dpc_intr_enable_count=%lu\n"
++				"isr_intr_disable_count=%lu suspend_intr_disable_count=%lu\n"
++				"dpc_return_busdown_count=%lu\n",
++				dhd->bus->resume_intr_enable_count, dhd->bus->dpc_intr_enable_count,
++				dhd->bus->isr_intr_disable_count,
++				dhd->bus->suspend_intr_disable_count,
++				dhd->bus->dpc_return_busdown_count));
++
++			dhd_prot_process_ctrlbuf(dhd);
++
++			timeleft = dhd_os_ioctl_resp_wait(dhd, (uint *)&prot->ioctl_received);
++			/* Enable Back Interrupts using IntMask */
++			dhdpcie_bus_intr_enable(dhd->bus);
++		}
++	}
++#endif /* DHD_RECOVER_TIMEOUT */
++
++	if (dhd->conf->ctrl_resched > 0 && timeleft == 0 && (!dhd_query_bus_erros(dhd))) {
++		cnt++;
++		if (cnt <= dhd->conf->ctrl_resched) {
++			uint32 intstatus = 0, intmask = 0;
++			intstatus = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, PCIMailBoxInt, 0, 0);
++			intmask = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, PCIMailBoxMask, 0, 0);
++			if (intstatus) {
++				DHD_ERROR(("%s: reschedule dhd_dpc, cnt=%d, intstatus=0x%x, intmask=0x%x\n",
++					__FUNCTION__, cnt, intstatus, intmask));
++				dhd->bus->intstatus = intstatus;
++				dhd->bus->ipend = TRUE;
++				dhd->bus->dpc_sched = TRUE;
++				dhd_sched_dpc(dhd);
++				timeleft = dhd_os_ioctl_resp_wait(dhd, &prot->ioctl_received);
++			}
++		}
++	} else {
++		cnt = 0;
++	}
++
++	if (timeleft == 0 && (!dhd_query_bus_erros(dhd))) {
++		uint32 intstatus;
++
++		dhd->rxcnt_timeout++;
++		dhd->rx_ctlerrs++;
++		dhd->iovar_timeout_occured = TRUE;
++		DHD_ERROR(("%s: resumed on timeout rxcnt_timeout %d ioctl_cmd %d "
++			"trans_id %d state %d busstate=%d ioctl_received=%d\n",
++			__FUNCTION__, dhd->rxcnt_timeout, prot->curr_ioctl_cmd,
++			prot->ioctl_trans_id, prot->ioctl_state,
++			dhd->busstate, prot->ioctl_received));
++		if (prot->curr_ioctl_cmd == WLC_SET_VAR ||
++			prot->curr_ioctl_cmd == WLC_GET_VAR) {
++			char iovbuf[32];
++			int i;
++			int dump_size = 128;
++			uint8 *ioctl_buf = (uint8 *)prot->ioctbuf.va;
++			memset(iovbuf, 0, sizeof(iovbuf));
++			strncpy(iovbuf, ioctl_buf, sizeof(iovbuf) - 1);
++			iovbuf[sizeof(iovbuf) - 1] = '\0';
++			DHD_ERROR(("Current IOVAR (%s): %s\n",
++				prot->curr_ioctl_cmd == WLC_SET_VAR ?
++				"WLC_SET_VAR" : "WLC_GET_VAR", iovbuf));
++			DHD_ERROR(("========== START IOCTL REQBUF DUMP ==========\n"));
++			for (i = 0; i < dump_size; i++) {
++				DHD_ERROR(("%02X ", ioctl_buf[i]));
++				if ((i % 32) == 31) {
++					DHD_ERROR(("\n"));
++				}
++			}
++			DHD_ERROR(("\n========== END IOCTL REQBUF DUMP ==========\n"));
++		}
++
++		/* Check the PCIe link status by reading intstatus register */
++		intstatus = si_corereg(dhd->bus->sih,
++			dhd->bus->sih->buscoreidx, PCIMailBoxInt, 0, 0);
++		if (intstatus == (uint32)-1) {
++			DHD_ERROR(("%s : PCIe link might be down\n", __FUNCTION__));
++			dhd->bus->is_linkdown = TRUE;
++		}
++
++		dhd_bus_dump_console_buffer(dhd->bus);
++		dhd_prot_debug_info_print(dhd);
++
++#ifdef DHD_FW_COREDUMP
++		/* Collect socram dump */
++		if (dhd->memdump_enabled) {
++			/* collect core dump */
++			dhd->memdump_type = DUMP_TYPE_RESUMED_ON_TIMEOUT;
++			dhd_bus_mem_dump(dhd);
++		}
++#endif /* DHD_FW_COREDUMP */
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#ifdef CONFIG_ARCH_MSM
++		dhd->bus->no_cfg_restore = 1;
++#endif /* CONFIG_ARCH_MSM */
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++		ret = -ETIMEDOUT;
++		goto out;
++	} else {
++		if (prot->ioctl_received != IOCTL_RETURN_ON_SUCCESS) {
++			DHD_ERROR(("%s: IOCTL failure due to ioctl_received = %d\n",
++				__FUNCTION__, prot->ioctl_received));
++			ret = -EINVAL;
++			goto out;
++		}
++		dhd->rxcnt_timeout = 0;
++		dhd->rx_ctlpkts++;
++		DHD_CTL(("%s: ioctl resp resumed, got %d\n",
++			__FUNCTION__, prot->ioctl_resplen));
++	}
++
++	if (dhd->prot->ioctl_resplen > len)
++		dhd->prot->ioctl_resplen = (uint16)len;
++	if (buf)
++		bcopy(dhd->prot->retbuf.va, buf, dhd->prot->ioctl_resplen);
++
++	ret = (int)(dhd->prot->ioctl_status);
++
++out:
++	DHD_GENERAL_LOCK(dhd, flags);
++	dhd->prot->ioctl_state = 0;
++	dhd->prot->ioctl_resplen = 0;
++	dhd->prot->ioctl_received = IOCTL_WAIT;
++	dhd->prot->curr_ioctl_cmd = 0;
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	return ret;
++} /* dhd_msgbuf_wait_ioctl_cmplt */
++
++static int
++dhd_msgbuf_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len, uint8 action)
++{
++	int ret = 0;
++
++	DHD_TRACE(("%s: Enter \n", __FUNCTION__));
++
++	if (dhd->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s : bus is down. we have nothing to do\n", __FUNCTION__));
++		return -EIO;
++	}
++
++	/* don't talk to the dongle if fw is about to be reloaded */
++	if (dhd->hang_was_sent) {
++		DHD_ERROR(("%s: HANG was sent up earlier. Not talking to the chip\n",
++			__FUNCTION__));
++		return -EIO;
++	}
++
++	DHD_CTL(("ACTION %d ifdix %d cmd %d len %d \n",
++		action, ifidx, cmd, len));
++
++#ifdef REPORT_FATAL_TIMEOUTS
++	/*
++	 * These timers "should" be started before sending H2D interrupt.
++	 * Think of the scenario where H2D interrupt is fired and the Dongle
++	 * responds back immediately. From the DPC we would stop the cmd, bus
++	 * timers. But the process context could have switched out leading to
++	 * a situation where the timers are Not started yet, but are actually stopped.
++	 *
++	 * Disable preemption from the time we start the timer until we are done
++	 * with seding H2D interrupts.
++	 */
++	OSL_DISABLE_PREEMPTION(dhd->osh);
++	dhd_set_request_id(dhd, dhd->prot->ioctl_trans_id+1, cmd);
++	dhd_start_cmd_timer(dhd);
++	dhd_start_bus_timer(dhd);
++#endif /* REPORT_FATAL_TIMEOUTS */
++
++	/* Fill up msgbuf for ioctl req */
++	ret = dhd_fillup_ioct_reqst(dhd, (uint16)len, cmd, buf, ifidx);
++
++#ifdef REPORT_FATAL_TIMEOUTS
++	/* For some reason if we fail to ring door bell, stop the timers */
++	if (ret < 0) {
++		DHD_ERROR(("%s(): dhd_fillup_ioct_reqst failed \r\n", __FUNCTION__));
++		dhd_stop_cmd_timer(dhd);
++		dhd_stop_bus_timer(dhd);
++		OSL_ENABLE_PREEMPTION(dhd->osh);
++		goto done;
++	}
++
++	OSL_ENABLE_PREEMPTION(dhd->osh);
++#else
++	if (ret < 0) {
++		DHD_ERROR(("%s(): dhd_fillup_ioct_reqst failed \r\n", __FUNCTION__));
++		goto done;
++	}
++#endif /* REPORT_FATAL_TIMEOUTS */
++
++	ret = dhd_msgbuf_wait_ioctl_cmplt(dhd, len, buf);
++
++done:
++	return ret;
++}
++
++/** Called by upper DHD layer. Handles a protocol control response asynchronously. */
++int dhd_prot_ctl_complete(dhd_pub_t *dhd)
++{
++	return 0;
++}
++
++/** Called by upper DHD layer. Check for and handle local prot-specific iovar commands */
++int dhd_prot_iovar_op(dhd_pub_t *dhd, const char *name,
++                             void *params, int plen, void *arg, int len, bool set)
++{
++	return BCME_UNSUPPORTED;
++}
++
++/** Add prot dump output to a buffer */
++void dhd_prot_dump(dhd_pub_t *dhd, struct bcmstrbuf *b)
++{
++
++	if (dhd->d2h_sync_mode & PCIE_SHARED_D2H_SYNC_SEQNUM)
++		bcm_bprintf(b, "\nd2h_sync: SEQNUM:");
++	else if (dhd->d2h_sync_mode & PCIE_SHARED_D2H_SYNC_XORCSUM)
++		bcm_bprintf(b, "\nd2h_sync: XORCSUM:");
++	else
++		bcm_bprintf(b, "\nd2h_sync: NONE:");
++	bcm_bprintf(b, " d2h_sync_wait max<%lu> tot<%lu>\n",
++		dhd->prot->d2h_sync_wait_max, dhd->prot->d2h_sync_wait_tot);
++
++	bcm_bprintf(b, "\nDongle DMA Indices: h2d %d  d2h %d index size %d bytes\n",
++		dhd->dma_h2d_ring_upd_support,
++		dhd->dma_d2h_ring_upd_support,
++		dhd->prot->rw_index_sz);
++	bcm_bprintf(b, "h2d_max_txpost: %d, prot->h2d_max_txpost: %d\n",
++		h2d_max_txpost, dhd->prot->h2d_max_txpost);
++}
++
++/* Update local copy of dongle statistics */
++void dhd_prot_dstats(dhd_pub_t *dhd)
++{
++	return;
++}
++
++/** Called by upper DHD layer */
++int dhd_process_pkt_reorder_info(dhd_pub_t *dhd, uchar *reorder_info_buf,
++	uint reorder_info_len, void **pkt, uint32 *free_buf_count)
++{
++	return 0;
++}
++
++/** Debug related, post a dummy message to interrupt dongle. Used to process cons commands. */
++int
++dhd_post_dummy_msg(dhd_pub_t *dhd)
++{
++	unsigned long flags;
++	hostevent_hdr_t *hevent = NULL;
++	uint16 alloced = 0;
++
++	dhd_prot_t *prot = dhd->prot;
++	msgbuf_ring_t *ring = &prot->h2dring_ctrl_subn;
++
++#ifdef PCIE_INB_DW
++	if (dhd_prot_inc_hostactive_devwake_assert(dhd->bus) != BCME_OK)
++		return BCME_ERROR;
++#endif /* PCIE_INB_DW */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	hevent = (hostevent_hdr_t *)
++		dhd_prot_alloc_ring_space(dhd, ring, 1, &alloced, FALSE);
++
++	if (hevent == NULL) {
++		DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++		dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++		return -1;
++	}
++
++	/* CMN msg header */
++	hevent->msg.epoch = ring->seqnum % H2D_EPOCH_MODULO;
++	ring->seqnum++;
++	hevent->msg.msg_type = MSG_TYPE_HOST_EVNT;
++	hevent->msg.if_id = 0;
++	hevent->msg.flags = ring->current_phase;
++
++	/* Event payload */
++	hevent->evnt_pyld = htol32(HOST_EVENT_CONS_CMD);
++
++	/* Since, we are filling the data directly into the bufptr obtained
++	 * from the msgbuf, we can directly call the write_complete
++	 */
++	dhd_prot_ring_write_complete(dhd, ring, hevent, 1);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++
++	return 0;
++}
++
++/**
++ * If exactly_nitems is true, this function will allocate space for nitems or fail
++ * If exactly_nitems is false, this function will allocate space for nitems or less
++ */
++static void * BCMFASTPATH
++dhd_prot_alloc_ring_space(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++	uint16 nitems, uint16 * alloced, bool exactly_nitems)
++{
++	void * ret_buf;
++
++	/* Alloc space for nitems in the ring */
++	ret_buf = dhd_prot_get_ring_space(ring, nitems, alloced, exactly_nitems);
++
++	if (ret_buf == NULL) {
++		/* if alloc failed , invalidate cached read ptr */
++		if (dhd->dma_d2h_ring_upd_support) {
++			ring->rd = dhd_prot_dma_indx_get(dhd, H2D_DMA_INDX_RD_UPD, ring->idx);
++		} else {
++			dhd_bus_cmn_readshared(dhd->bus, &(ring->rd), RING_RD_UPD, ring->idx);
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++			/* Check if ring->rd is valid */
++			if (ring->rd >= ring->max_items) {
++				dhd->bus->read_shm_fail = TRUE;
++				DHD_ERROR(("%s: Invalid rd idx=%d\n", ring->name, ring->rd));
++				return NULL;
++			}
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++		}
++
++		/* Try allocating once more */
++		ret_buf = dhd_prot_get_ring_space(ring, nitems, alloced, exactly_nitems);
++
++		if (ret_buf == NULL) {
++			DHD_INFO(("%s: Ring space not available  \n", ring->name));
++			return NULL;
++		}
++	}
++
++	if (ret_buf == HOST_RING_BASE(ring)) {
++		DHD_INFO(("%s: setting the phase now\n", ring->name));
++		ring->current_phase = ring->current_phase ? 0 : BCMPCIE_CMNHDR_PHASE_BIT_INIT;
++	}
++
++	/* Return alloced space */
++	return ret_buf;
++}
++
++/**
++ * Non inline ioct request.
++ * Form a ioctl request first as per ioctptr_reqst_hdr_t header in the circular buffer
++ * Form a separate request buffer where a 4 byte cmn header is added in the front
++ * buf contents from parent function is copied to remaining section of this buffer
++ */
++static int
++dhd_fillup_ioct_reqst(dhd_pub_t *dhd, uint16 len, uint cmd, void* buf, int ifidx)
++{
++	dhd_prot_t *prot = dhd->prot;
++	ioctl_req_msg_t *ioct_rqst;
++	void * ioct_buf;	/* For ioctl payload */
++	uint16  rqstlen, resplen;
++	unsigned long flags;
++	uint16 alloced = 0;
++	msgbuf_ring_t *ring = &prot->h2dring_ctrl_subn;
++
++	if (dhd_query_bus_erros(dhd)) {
++		return -EIO;
++	}
++
++	rqstlen = len;
++	resplen = len;
++
++	/* Limit ioct request to MSGBUF_MAX_MSG_SIZE bytes including hdrs */
++	/* 8K allocation of dongle buffer fails */
++	/* dhd doesnt give separate input & output buf lens */
++	/* so making the assumption that input length can never be more than 1.5k */
++	rqstlen = MIN(rqstlen, MSGBUF_MAX_MSG_SIZE);
++
++#ifdef PCIE_INB_DW
++	if (dhd_prot_inc_hostactive_devwake_assert(dhd->bus) != BCME_OK)
++		return BCME_ERROR;
++#endif /* PCIE_INB_DW */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	if (prot->ioctl_state) {
++		DHD_ERROR(("%s: pending ioctl %02x\n", __FUNCTION__, prot->ioctl_state));
++		DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++		dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++		return BCME_BUSY;
++	} else {
++		prot->ioctl_state = MSGBUF_IOCTL_ACK_PENDING | MSGBUF_IOCTL_RESP_PENDING;
++	}
++
++	/* Request for cbuf space */
++	ioct_rqst = (ioctl_req_msg_t*)
++		dhd_prot_alloc_ring_space(dhd, ring, 1, &alloced, FALSE);
++	if (ioct_rqst == NULL) {
++		DHD_ERROR(("couldn't allocate space on msgring to send ioctl request\n"));
++		prot->ioctl_state = 0;
++		prot->curr_ioctl_cmd = 0;
++		prot->ioctl_received = IOCTL_WAIT;
++		DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++		dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++		return -1;
++	}
++
++	/* Common msg buf hdr */
++	ioct_rqst->cmn_hdr.msg_type = MSG_TYPE_IOCTLPTR_REQ;
++	ioct_rqst->cmn_hdr.if_id = (uint8)ifidx;
++	ioct_rqst->cmn_hdr.flags = ring->current_phase;
++	ioct_rqst->cmn_hdr.request_id = htol32(DHD_IOCTL_REQ_PKTID);
++	ioct_rqst->cmn_hdr.epoch = ring->seqnum % H2D_EPOCH_MODULO;
++	ring->seqnum++;
++
++	ioct_rqst->cmd = htol32(cmd);
++	prot->curr_ioctl_cmd = cmd;
++	ioct_rqst->output_buf_len = htol16(resplen);
++	prot->ioctl_trans_id++;
++	ioct_rqst->trans_id = prot->ioctl_trans_id;
++
++	/* populate ioctl buffer info */
++	ioct_rqst->input_buf_len = htol16(rqstlen);
++	ioct_rqst->host_input_buf_addr.high = htol32(PHYSADDRHI(prot->ioctbuf.pa));
++	ioct_rqst->host_input_buf_addr.low = htol32(PHYSADDRLO(prot->ioctbuf.pa));
++	/* copy ioct payload */
++	ioct_buf = (void *) prot->ioctbuf.va;
++
++	if (buf)
++		memcpy(ioct_buf, buf, len);
++
++	OSL_CACHE_FLUSH((void *) prot->ioctbuf.va, len);
++
++	if (!ISALIGNED(ioct_buf, DMA_ALIGN_LEN))
++		DHD_ERROR(("host ioct address unaligned !!!!! \n"));
++
++	DHD_CTL(("submitted IOCTL request request_id %d, cmd %d, output_buf_len %d, tx_id %d\n",
++		ioct_rqst->cmn_hdr.request_id, cmd, ioct_rqst->output_buf_len,
++		ioct_rqst->trans_id));
++
++	/* update ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ring, ioct_rqst, 1);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++
++	return 0;
++} /* dhd_fillup_ioct_reqst */
++
++
++/**
++ * dhd_prot_ring_attach - Initialize the msgbuf_ring object and attach a
++ * DMA-able buffer to it. The ring is NOT tagged as inited until all the ring
++ * information is posted to the dongle.
++ *
++ * Invoked in dhd_prot_attach for the common rings, and in dhd_prot_init for
++ * each flowring in pool of flowrings.
++ *
++ * returns BCME_OK=0 on success
++ * returns non-zero negative error value on failure.
++ */
++static int
++dhd_prot_ring_attach(dhd_pub_t *dhd, msgbuf_ring_t *ring, const char *name,
++	uint16 max_items, uint16 item_len, uint16 ringid)
++{
++	int dma_buf_alloced = BCME_NOMEM;
++	uint32 dma_buf_len = max_items * item_len;
++	dhd_prot_t *prot = dhd->prot;
++	uint16 max_flowrings = dhd->bus->max_tx_flowrings;
++
++	ASSERT(ring);
++	ASSERT(name);
++	ASSERT((max_items < 0xFFFF) && (item_len < 0xFFFF) && (ringid < 0xFFFF));
++
++	/* Init name */
++	strncpy(ring->name, name, RING_NAME_MAX_LENGTH);
++	ring->name[RING_NAME_MAX_LENGTH - 1] = '\0';
++
++	ring->idx = ringid;
++
++	ring->max_items = max_items;
++	ring->item_len = item_len;
++
++	/* A contiguous space may be reserved for all flowrings */
++	if (DHD_IS_FLOWRING(ringid, max_flowrings) && (prot->flowrings_dma_buf.va)) {
++		/* Carve out from the contiguous DMA-able flowring buffer */
++		uint16 flowid;
++		uint32 base_offset;
++
++		dhd_dma_buf_t *dma_buf = &ring->dma_buf;
++		dhd_dma_buf_t *rsv_buf = &prot->flowrings_dma_buf;
++
++		flowid = DHD_RINGID_TO_FLOWID(ringid);
++		base_offset = (flowid - BCMPCIE_H2D_COMMON_MSGRINGS) * dma_buf_len;
++
++		ASSERT(base_offset + dma_buf_len <= rsv_buf->len);
++
++		dma_buf->len = dma_buf_len;
++		dma_buf->va = (void *)((uintptr)rsv_buf->va + base_offset);
++		PHYSADDRHISET(dma_buf->pa, PHYSADDRHI(rsv_buf->pa));
++		PHYSADDRLOSET(dma_buf->pa, PHYSADDRLO(rsv_buf->pa) + base_offset);
++
++		/* On 64bit, contiguous space may not span across 0x00000000FFFFFFFF */
++		ASSERT(PHYSADDRLO(dma_buf->pa) >= PHYSADDRLO(rsv_buf->pa));
++
++		dma_buf->dmah   = rsv_buf->dmah;
++		dma_buf->secdma = rsv_buf->secdma;
++
++		(void)dhd_dma_buf_audit(dhd, &ring->dma_buf);
++	} else {
++		/* Allocate a dhd_dma_buf */
++		dma_buf_alloced = dhd_dma_buf_alloc(dhd, &ring->dma_buf, dma_buf_len);
++		if (dma_buf_alloced != BCME_OK) {
++			return BCME_NOMEM;
++		}
++	}
++
++	/* CAUTION: Save ring::base_addr in little endian format! */
++	dhd_base_addr_htolpa(&ring->base_addr, ring->dma_buf.pa);
++
++#ifdef BCM_SECURE_DMA
++	if (SECURE_DMA_ENAB(prot->osh)) {
++		ring->dma_buf.secdma = MALLOCZ(prot->osh, sizeof(sec_cma_info_t));
++		if (ring->dma_buf.secdma == NULL) {
++			goto free_dma_buf;
++		}
++	}
++#endif /* BCM_SECURE_DMA */
++
++	DHD_INFO(("RING_ATTACH : %s Max item %d len item %d total size %d "
++		"ring start %p buf phys addr  %x:%x \n",
++		ring->name, ring->max_items, ring->item_len,
++		dma_buf_len, ring->dma_buf.va, ltoh32(ring->base_addr.high_addr),
++		ltoh32(ring->base_addr.low_addr)));
++
++	return BCME_OK;
++
++#ifdef BCM_SECURE_DMA
++free_dma_buf:
++	if (dma_buf_alloced == BCME_OK) {
++		dhd_dma_buf_free(dhd, &ring->dma_buf);
++	}
++#endif /* BCM_SECURE_DMA */
++
++	return BCME_NOMEM;
++
++} /* dhd_prot_ring_attach */
++
++
++/**
++ * dhd_prot_ring_init - Post the common ring information to dongle.
++ *
++ * Used only for common rings.
++ *
++ * The flowrings information is passed via the create flowring control message
++ * (tx_flowring_create_request_t) sent over the H2D control submission common
++ * ring.
++ */
++static void
++dhd_prot_ring_init(dhd_pub_t *dhd, msgbuf_ring_t *ring)
++{
++	ring->wr = 0;
++	ring->rd = 0;
++	ring->curr_rd = 0;
++
++	/* CAUTION: ring::base_addr already in Little Endian */
++	dhd_bus_cmn_writeshared(dhd->bus, &ring->base_addr,
++		sizeof(sh_addr_t), RING_BUF_ADDR, ring->idx);
++	dhd_bus_cmn_writeshared(dhd->bus, &ring->max_items,
++		sizeof(uint16), RING_MAX_ITEMS, ring->idx);
++	dhd_bus_cmn_writeshared(dhd->bus, &ring->item_len,
++		sizeof(uint16), RING_ITEM_LEN, ring->idx);
++
++	dhd_bus_cmn_writeshared(dhd->bus, &(ring->wr),
++		sizeof(uint16), RING_WR_UPD, ring->idx);
++	dhd_bus_cmn_writeshared(dhd->bus, &(ring->rd),
++		sizeof(uint16), RING_RD_UPD, ring->idx);
++
++	/* ring inited */
++	ring->inited = TRUE;
++
++} /* dhd_prot_ring_init */
++
++
++/**
++ * dhd_prot_ring_reset - bzero a ring's DMA-ble buffer and cache flush
++ * Reset WR and RD indices to 0.
++ */
++static void
++dhd_prot_ring_reset(dhd_pub_t *dhd, msgbuf_ring_t *ring)
++{
++	DHD_TRACE(("%s\n", __FUNCTION__));
++
++	dhd_dma_buf_reset(dhd, &ring->dma_buf);
++
++	ring->rd = ring->wr = 0;
++	ring->curr_rd = 0;
++	ring->inited = FALSE;
++	ring->create_pending = FALSE;
++}
++
++
++/**
++ * dhd_prot_ring_detach - Detach the DMA-able buffer and any other objects
++ * hanging off the msgbuf_ring.
++ */
++static void
++dhd_prot_ring_detach(dhd_pub_t *dhd, msgbuf_ring_t *ring)
++{
++	dhd_prot_t *prot = dhd->prot;
++	uint16 max_flowrings = dhd->bus->max_tx_flowrings;
++	ASSERT(ring);
++
++	ring->inited = FALSE;
++	/* rd = ~0, wr = ring->rd - 1, max_items = 0, len_item = ~0 */
++
++#ifdef BCM_SECURE_DMA
++	if (SECURE_DMA_ENAB(prot->osh)) {
++		if (ring->dma_buf.secdma) {
++			SECURE_DMA_UNMAP_ALL(prot->osh, ring->dma_buf.secdma);
++			MFREE(prot->osh, ring->dma_buf.secdma, sizeof(sec_cma_info_t));
++			ring->dma_buf.secdma = NULL;
++		}
++	}
++#endif /* BCM_SECURE_DMA */
++
++	/* If the DMA-able buffer was carved out of a pre-reserved contiguous
++	 * memory, then simply stop using it.
++	 */
++	if (DHD_IS_FLOWRING(ring->idx, max_flowrings) && (prot->flowrings_dma_buf.va)) {
++		(void)dhd_dma_buf_audit(dhd, &ring->dma_buf);
++		memset(&ring->dma_buf, 0, sizeof(dhd_dma_buf_t));
++	} else {
++		dhd_dma_buf_free(dhd, &ring->dma_buf);
++	}
++
++} /* dhd_prot_ring_detach */
++
++
++/*
++ * +----------------------------------------------------------------------------
++ * Flowring Pool
++ *
++ * Unlike common rings, which are attached very early on (dhd_prot_attach),
++ * flowrings are dynamically instantiated. Moreover, flowrings may require a
++ * larger DMA-able buffer. To avoid issues with fragmented cache coherent
++ * DMA-able memory, a pre-allocated pool of msgbuf_ring_t is allocated once.
++ * The DMA-able buffers are attached to these pre-allocated msgbuf_ring.
++ *
++ * Each DMA-able buffer may be allocated independently, or may be carved out
++ * of a single large contiguous region that is registered with the protocol
++ * layer into flowrings_dma_buf. On a 64bit platform, this contiguous region
++ * may not span 0x00000000FFFFFFFF (avoid dongle side 64bit ptr arithmetic).
++ *
++ * No flowring pool action is performed in dhd_prot_attach(), as the number
++ * of h2d rings is not yet known.
++ *
++ * In dhd_prot_init(), the dongle advertized number of h2d rings is used to
++ * determine the number of flowrings required, and a pool of msgbuf_rings are
++ * allocated and a DMA-able buffer (carved or allocated) is attached.
++ * See: dhd_prot_flowrings_pool_attach()
++ *
++ * A flowring msgbuf_ring object may be fetched from this pool during flowring
++ * creation, using the flowid. Likewise, flowrings may be freed back into the
++ * pool on flowring deletion.
++ * See: dhd_prot_flowrings_pool_fetch(), dhd_prot_flowrings_pool_release()
++ *
++ * In dhd_prot_detach(), the flowring pool is detached. The DMA-able buffers
++ * are detached (returned back to the carved region or freed), and the pool of
++ * msgbuf_ring and any objects allocated against it are freed.
++ * See: dhd_prot_flowrings_pool_detach()
++ *
++ * In dhd_prot_reset(), the flowring pool is simply reset by returning it to a
++ * state as-if upon an attach. All DMA-able buffers are retained.
++ * Following a dhd_prot_reset(), in a subsequent dhd_prot_init(), the flowring
++ * pool attach will notice that the pool persists and continue to use it. This
++ * will avoid the case of a fragmented DMA-able region.
++ *
++ * +----------------------------------------------------------------------------
++ */
++
++/* Conversion of a flowid to a flowring pool index */
++#define DHD_FLOWRINGS_POOL_OFFSET(flowid) \
++	((flowid) - BCMPCIE_H2D_COMMON_MSGRINGS)
++
++/* Fetch the msgbuf_ring_t from the flowring pool given a flowid */
++#define DHD_RING_IN_FLOWRINGS_POOL(prot, flowid) \
++	(msgbuf_ring_t*)((prot)->h2d_flowrings_pool) + \
++	    DHD_FLOWRINGS_POOL_OFFSET(flowid)
++
++/* Traverse each flowring in the flowring pool, assigning ring and flowid */
++#define FOREACH_RING_IN_FLOWRINGS_POOL(prot, ring, flowid, total_flowrings) \
++	for ((flowid) = DHD_FLOWRING_START_FLOWID, \
++		(ring) = DHD_RING_IN_FLOWRINGS_POOL(prot, flowid); \
++		 (flowid) < ((total_flowrings) + DHD_FLOWRING_START_FLOWID); \
++		 (ring)++, (flowid)++)
++
++/* Fetch number of H2D flowrings given the total number of h2d rings */
++static uint16
++dhd_get_max_flow_rings(dhd_pub_t *dhd)
++{
++	if (dhd->bus->api.fw_rev >= PCIE_SHARED_VERSION_6)
++		return dhd->bus->max_tx_flowrings;
++	else
++		return (dhd->bus->max_tx_flowrings - BCMPCIE_H2D_COMMON_MSGRINGS);
++}
++
++/**
++ * dhd_prot_flowrings_pool_attach - Initialize a pool of flowring msgbuf_ring_t.
++ *
++ * Allocate a pool of msgbuf_ring along with DMA-able buffers for flowrings.
++ * Dongle includes common rings when it advertizes the number of H2D rings.
++ * Allocates a pool of msgbuf_ring_t and invokes dhd_prot_ring_attach to
++ * allocate the DMA-able buffer and initialize each msgbuf_ring_t object.
++ *
++ * dhd_prot_ring_attach is invoked to perform the actual initialization and
++ * attaching the DMA-able buffer.
++ *
++ * Later dhd_prot_flowrings_pool_fetch() may be used to fetch a preallocated and
++ * initialized msgbuf_ring_t object.
++ *
++ * returns BCME_OK=0 on success
++ * returns non-zero negative error value on failure.
++ */
++static int
++dhd_prot_flowrings_pool_attach(dhd_pub_t *dhd)
++{
++	uint16 flowid;
++	msgbuf_ring_t *ring;
++	uint16 h2d_flowrings_total; /* exclude H2D common rings */
++	dhd_prot_t *prot = dhd->prot;
++	char ring_name[RING_NAME_MAX_LENGTH];
++
++	if (prot->h2d_flowrings_pool != NULL)
++		return BCME_OK; /* dhd_prot_init rentry after a dhd_prot_reset */
++
++	ASSERT(prot->h2d_rings_total == 0);
++
++	/* h2d_rings_total includes H2D common rings: ctrl and rxbuf subn */
++	prot->h2d_rings_total = (uint16)dhd_bus_max_h2d_queues(dhd->bus);
++
++	if (prot->h2d_rings_total < BCMPCIE_H2D_COMMON_MSGRINGS) {
++		DHD_ERROR(("%s: h2d_rings_total advertized as %u\n",
++			__FUNCTION__, prot->h2d_rings_total));
++		return BCME_ERROR;
++	}
++
++	/* Subtract number of H2D common rings, to determine number of flowrings */
++	h2d_flowrings_total = dhd_get_max_flow_rings(dhd);
++
++	DHD_ERROR(("Attach flowrings pool for %d rings\n", h2d_flowrings_total));
++
++	/* Allocate pool of msgbuf_ring_t objects for all flowrings */
++	prot->h2d_flowrings_pool = (msgbuf_ring_t *)MALLOCZ(prot->osh,
++		(h2d_flowrings_total * sizeof(msgbuf_ring_t)));
++
++	if (prot->h2d_flowrings_pool == NULL) {
++		DHD_ERROR(("%s: flowrings pool for %d flowrings, alloc failure\n",
++			__FUNCTION__, h2d_flowrings_total));
++		goto fail;
++	}
++
++	/* Setup & Attach a DMA-able buffer to each flowring in the flowring pool */
++	FOREACH_RING_IN_FLOWRINGS_POOL(prot, ring, flowid, h2d_flowrings_total) {
++		snprintf(ring_name, sizeof(ring_name), "h2dflr_%03u", flowid);
++		if (dhd_prot_ring_attach(dhd, ring, ring_name,
++		        prot->h2d_max_txpost, H2DRING_TXPOST_ITEMSIZE,
++		        DHD_FLOWID_TO_RINGID(flowid)) != BCME_OK) {
++			goto attach_fail;
++		}
++	}
++
++	return BCME_OK;
++
++attach_fail:
++	dhd_prot_flowrings_pool_detach(dhd); /* Free entire pool of flowrings */
++
++fail:
++	prot->h2d_rings_total = 0;
++	return BCME_NOMEM;
++
++} /* dhd_prot_flowrings_pool_attach */
++
++
++/**
++ * dhd_prot_flowrings_pool_reset - Reset all msgbuf_ring_t objects in the pool.
++ * Invokes dhd_prot_ring_reset to perform the actual reset.
++ *
++ * The DMA-able buffer is not freed during reset and neither is the flowring
++ * pool freed.
++ *
++ * dhd_prot_flowrings_pool_reset will be invoked in dhd_prot_reset. Following
++ * the dhd_prot_reset, dhd_prot_init will be re-invoked, and the flowring pool
++ * from a previous flowring pool instantiation will be reused.
++ *
++ * This will avoid a fragmented DMA-able memory condition, if multiple
++ * dhd_prot_reset were invoked to reboot the dongle without a full detach/attach
++ * cycle.
++ */
++static void
++dhd_prot_flowrings_pool_reset(dhd_pub_t *dhd)
++{
++	uint16 flowid, h2d_flowrings_total;
++	msgbuf_ring_t *ring;
++	dhd_prot_t *prot = dhd->prot;
++
++	if (prot->h2d_flowrings_pool == NULL) {
++		ASSERT(prot->h2d_rings_total == 0);
++		return;
++	}
++	h2d_flowrings_total = dhd_get_max_flow_rings(dhd);
++	/* Reset each flowring in the flowring pool */
++	FOREACH_RING_IN_FLOWRINGS_POOL(prot, ring, flowid, h2d_flowrings_total) {
++		dhd_prot_ring_reset(dhd, ring);
++		ring->inited = FALSE;
++	}
++
++	/* Flowring pool state must be as-if dhd_prot_flowrings_pool_attach */
++}
++
++
++/**
++ * dhd_prot_flowrings_pool_detach - Free pool of msgbuf_ring along with
++ * DMA-able buffers for flowrings.
++ * dhd_prot_ring_detach is invoked to free the DMA-able buffer and perform any
++ * de-initialization of each msgbuf_ring_t.
++ */
++static void
++dhd_prot_flowrings_pool_detach(dhd_pub_t *dhd)
++{
++	int flowid;
++	msgbuf_ring_t *ring;
++	uint16 h2d_flowrings_total; /* exclude H2D common rings */
++	dhd_prot_t *prot = dhd->prot;
++
++	if (prot->h2d_flowrings_pool == NULL) {
++		ASSERT(prot->h2d_rings_total == 0);
++		return;
++	}
++
++	h2d_flowrings_total = dhd_get_max_flow_rings(dhd);
++	/* Detach the DMA-able buffer for each flowring in the flowring pool */
++	FOREACH_RING_IN_FLOWRINGS_POOL(prot, ring, flowid, h2d_flowrings_total) {
++		dhd_prot_ring_detach(dhd, ring);
++	}
++
++
++	MFREE(prot->osh, prot->h2d_flowrings_pool,
++		(h2d_flowrings_total * sizeof(msgbuf_ring_t)));
++
++	prot->h2d_flowrings_pool = (msgbuf_ring_t*)NULL;
++	prot->h2d_rings_total = 0;
++
++} /* dhd_prot_flowrings_pool_detach */
++
++
++/**
++ * dhd_prot_flowrings_pool_fetch - Fetch a preallocated and initialized
++ * msgbuf_ring from the flowring pool, and assign it.
++ *
++ * Unlike common rings, which uses a dhd_prot_ring_init() to pass the common
++ * ring information to the dongle, a flowring's information is passed via a
++ * flowring create control message.
++ *
++ * Only the ring state (WR, RD) index are initialized.
++ */
++static msgbuf_ring_t *
++dhd_prot_flowrings_pool_fetch(dhd_pub_t *dhd, uint16 flowid)
++{
++	msgbuf_ring_t *ring;
++	dhd_prot_t *prot = dhd->prot;
++
++	ASSERT(flowid >= DHD_FLOWRING_START_FLOWID);
++	ASSERT(flowid < prot->h2d_rings_total);
++	ASSERT(prot->h2d_flowrings_pool != NULL);
++
++	ring = DHD_RING_IN_FLOWRINGS_POOL(prot, flowid);
++
++	/* ASSERT flow_ring->inited == FALSE */
++
++	ring->wr = 0;
++	ring->rd = 0;
++	ring->curr_rd = 0;
++	ring->inited = TRUE;
++	/**
++	 * Every time a flowring starts dynamically, initialize current_phase with 0
++	 * then flip to BCMPCIE_CMNHDR_PHASE_BIT_INIT
++	 */
++	ring->current_phase = 0;
++	return ring;
++}
++
++
++/**
++ * dhd_prot_flowrings_pool_release - release a previously fetched flowring's
++ * msgbuf_ring back to the flow_ring pool.
++ */
++void
++dhd_prot_flowrings_pool_release(dhd_pub_t *dhd, uint16 flowid, void *flow_ring)
++{
++	msgbuf_ring_t *ring;
++	dhd_prot_t *prot = dhd->prot;
++
++	ASSERT(flowid >= DHD_FLOWRING_START_FLOWID);
++	ASSERT(flowid < prot->h2d_rings_total);
++	ASSERT(prot->h2d_flowrings_pool != NULL);
++
++	ring = DHD_RING_IN_FLOWRINGS_POOL(prot, flowid);
++
++	ASSERT(ring == (msgbuf_ring_t*)flow_ring);
++	/* ASSERT flow_ring->inited == TRUE */
++
++	(void)dhd_dma_buf_audit(dhd, &ring->dma_buf);
++
++	ring->wr = 0;
++	ring->rd = 0;
++	ring->inited = FALSE;
++
++	ring->curr_rd = 0;
++}
++
++
++/* Assumes only one index is updated at a time */
++/* If exactly_nitems is true, this function will allocate space for nitems or fail */
++/*    Exception: when wrap around is encountered, to prevent hangup (last nitems of ring buffer) */
++/* If exactly_nitems is false, this function will allocate space for nitems or less */
++static void *BCMFASTPATH
++dhd_prot_get_ring_space(msgbuf_ring_t *ring, uint16 nitems, uint16 * alloced,
++	bool exactly_nitems)
++{
++	void *ret_ptr = NULL;
++	uint16 ring_avail_cnt;
++
++	ASSERT(nitems <= ring->max_items);
++
++	ring_avail_cnt = CHECK_WRITE_SPACE(ring->rd, ring->wr, ring->max_items);
++
++	if ((ring_avail_cnt == 0) ||
++	       (exactly_nitems && (ring_avail_cnt < nitems) &&
++	       ((ring->max_items - ring->wr) >= nitems))) {
++		DHD_INFO(("Space not available: ring %s items %d write %d read %d\n",
++			ring->name, nitems, ring->wr, ring->rd));
++		return NULL;
++	}
++	*alloced = MIN(nitems, ring_avail_cnt);
++
++	/* Return next available space */
++	ret_ptr = (char *)DHD_RING_BGN_VA(ring) + (ring->wr * ring->item_len);
++
++	/* Update write index */
++	if ((ring->wr + *alloced) == ring->max_items)
++		ring->wr = 0;
++	else if ((ring->wr + *alloced) < ring->max_items)
++		ring->wr += *alloced;
++	else {
++		/* Should never hit this */
++		ASSERT(0);
++		return NULL;
++	}
++
++	return ret_ptr;
++} /* dhd_prot_get_ring_space */
++
++
++/**
++ * dhd_prot_ring_write_complete - Host updates the new WR index on producing
++ * new messages in a H2D ring. The messages are flushed from cache prior to
++ * posting the new WR index. The new WR index will be updated in the DMA index
++ * array or directly in the dongle's ring state memory.
++ * A PCIE doorbell will be generated to wake up the dongle.
++ * This is a non-atomic function, make sure the callers
++ * always hold appropriate locks.
++ */
++static void BCMFASTPATH
++dhd_prot_ring_write_complete(dhd_pub_t *dhd, msgbuf_ring_t * ring, void* p,
++	uint16 nitems)
++{
++	dhd_prot_t *prot = dhd->prot;
++	uint8 db_index;
++	uint16 max_flowrings = dhd->bus->max_tx_flowrings;
++
++	/* cache flush */
++	OSL_CACHE_FLUSH(p, ring->item_len * nitems);
++
++	if (IDMA_DS_ACTIVE(dhd) && IDMA_ACTIVE(dhd)) {
++		dhd_bus_cmn_writeshared(dhd->bus, &(ring->wr),
++			sizeof(uint16), RING_WR_UPD, ring->idx);
++	} else if (IDMA_ACTIVE(dhd) || dhd->dma_h2d_ring_upd_support) {
++			dhd_prot_dma_indx_set(dhd, ring->wr,
++			                      H2D_DMA_INDX_WR_UPD, ring->idx);
++	} else if (IFRM_ACTIVE(dhd) && DHD_IS_FLOWRING(ring->idx, max_flowrings)) {
++			dhd_prot_dma_indx_set(dhd, ring->wr,
++			H2D_IFRM_INDX_WR_UPD, ring->idx);
++	} else {
++			dhd_bus_cmn_writeshared(dhd->bus, &(ring->wr),
++				sizeof(uint16), RING_WR_UPD, ring->idx);
++	}
++
++	/* raise h2d interrupt */
++	if (IDMA_ACTIVE(dhd) ||
++		(IFRM_ACTIVE(dhd) && DHD_IS_FLOWRING(ring->idx, max_flowrings))) {
++		if (IDMA_DS_ACTIVE(dhd)) {
++			prot->mb_ring_fn(dhd->bus, ring->wr);
++		} else {
++			db_index = IDMA_IDX0;
++			prot->mb_2_ring_fn(dhd->bus, db_index, TRUE);
++		}
++	} else {
++		prot->mb_ring_fn(dhd->bus, ring->wr);
++	}
++}
++
++/**
++ * dhd_prot_upd_read_idx - Host updates the new RD index on consuming messages
++ * from a D2H ring. The new RD index will be updated in the DMA Index array or
++ * directly in dongle's ring state memory.
++ */
++static void
++dhd_prot_upd_read_idx(dhd_pub_t *dhd, msgbuf_ring_t * ring)
++{
++	dhd_prot_t *prot = dhd->prot;
++	uint8 db_index;
++
++	/* update read index */
++	/* If dma'ing h2d indices supported
++	 * update the r -indices in the
++	 * host memory o/w in TCM
++	 */
++	if (IDMA_ACTIVE(dhd)) {
++		dhd_prot_dma_indx_set(dhd, ring->rd,
++		                      D2H_DMA_INDX_RD_UPD, ring->idx);
++		if (IDMA_DS_ACTIVE(dhd)) {
++			dhd_bus_cmn_writeshared(dhd->bus, &(ring->rd),
++				sizeof(uint16), RING_RD_UPD, ring->idx);
++		} else {
++			db_index = IDMA_IDX1;
++			prot->mb_2_ring_fn(dhd->bus, db_index, FALSE);
++		}
++	} else if (dhd->dma_h2d_ring_upd_support) {
++		dhd_prot_dma_indx_set(dhd, ring->rd,
++		                      D2H_DMA_INDX_RD_UPD, ring->idx);
++	} else {
++		dhd_bus_cmn_writeshared(dhd->bus, &(ring->rd),
++			sizeof(uint16), RING_RD_UPD, ring->idx);
++	}
++}
++
++static int
++dhd_send_d2h_ringcreate(dhd_pub_t *dhd, msgbuf_ring_t *ring_to_create)
++{
++	unsigned long flags;
++	d2h_ring_create_req_t  *d2h_ring;
++	uint16 alloced = 0;
++	int ret = BCME_OK;
++	uint16 max_h2d_rings = dhd->bus->max_submission_rings;
++
++#ifdef PCIE_INB_DW
++	if (dhd_prot_inc_hostactive_devwake_assert(dhd->bus) != BCME_OK)
++		return BCME_ERROR;
++#endif /* PCIE_INB_DW */
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	DHD_TRACE(("%s trying to send D2H ring create Req\n", __FUNCTION__));
++
++	if (ring_to_create == NULL) {
++		DHD_ERROR(("%s: FATAL: ring_to_create is NULL\n", __FUNCTION__));
++		ret = BCME_ERROR;
++		goto err;
++	}
++
++	/* Request for ring buffer space */
++	d2h_ring = (d2h_ring_create_req_t *) dhd_prot_alloc_ring_space(dhd,
++		&dhd->prot->h2dring_ctrl_subn, DHD_FLOWRING_DEFAULT_NITEMS_POSTED_H2D,
++		&alloced, FALSE);
++
++	if (d2h_ring == NULL) {
++		DHD_ERROR(("%s: FATAL: No space in control ring to send D2H ring create\n",
++			__FUNCTION__));
++		ret = BCME_NOMEM;
++		goto err;
++	}
++	ring_to_create->create_req_id = DHD_D2H_DBGRING_REQ_PKTID;
++	ring_to_create->create_pending = TRUE;
++
++	/* Common msg buf hdr */
++	d2h_ring->msg.msg_type = MSG_TYPE_D2H_RING_CREATE;
++	d2h_ring->msg.if_id = 0;
++	d2h_ring->msg.flags = dhd->prot->h2dring_ctrl_subn.current_phase;
++	d2h_ring->msg.request_id = htol32(ring_to_create->create_req_id);
++	d2h_ring->ring_id = htol16(DHD_D2H_RING_OFFSET(ring_to_create->idx, max_h2d_rings));
++	d2h_ring->ring_type = BCMPCIE_D2H_RING_TYPE_DBGBUF_CPL;
++	d2h_ring->max_items = htol16(D2HRING_DYNAMIC_INFO_MAX_ITEM);
++	d2h_ring->len_item = htol16(D2HRING_INFO_BUFCMPLT_ITEMSIZE);
++	d2h_ring->ring_ptr.low_addr = ring_to_create->base_addr.low_addr;
++	d2h_ring->ring_ptr.high_addr = ring_to_create->base_addr.high_addr;
++
++	d2h_ring->flags = 0;
++	d2h_ring->msg.epoch =
++		dhd->prot->h2dring_ctrl_subn.seqnum % H2D_EPOCH_MODULO;
++	dhd->prot->h2dring_ctrl_subn.seqnum++;
++
++	/* Update the flow_ring's WRITE index */
++	dhd_prot_ring_write_complete(dhd, &dhd->prot->h2dring_ctrl_subn, d2h_ring,
++		DHD_FLOWRING_DEFAULT_NITEMS_POSTED_H2D);
++
++err:
++	DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++	return ret;
++}
++
++static int
++dhd_send_h2d_ringcreate(dhd_pub_t *dhd, msgbuf_ring_t *ring_to_create)
++{
++	unsigned long flags;
++	h2d_ring_create_req_t  *h2d_ring;
++	uint16 alloced = 0;
++	uint8 i = 0;
++	int ret = BCME_OK;
++
++
++#ifdef PCIE_INB_DW
++	if (dhd_prot_inc_hostactive_devwake_assert(dhd->bus) != BCME_OK)
++		return BCME_ERROR;
++#endif /* PCIE_INB_DW */
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	DHD_TRACE(("%s trying to send H2D ring create Req\n", __FUNCTION__));
++
++	if (ring_to_create == NULL) {
++		DHD_ERROR(("%s: FATAL: ring_to_create is NULL\n", __FUNCTION__));
++		ret = BCME_ERROR;
++		goto err;
++	}
++
++	/* Request for ring buffer space */
++	h2d_ring = (h2d_ring_create_req_t *)dhd_prot_alloc_ring_space(dhd,
++		&dhd->prot->h2dring_ctrl_subn, DHD_FLOWRING_DEFAULT_NITEMS_POSTED_H2D,
++		&alloced, FALSE);
++
++	if (h2d_ring == NULL) {
++		DHD_ERROR(("%s: FATAL: No space in control ring to send H2D ring create\n",
++			__FUNCTION__));
++		ret = BCME_NOMEM;
++		goto err;
++	}
++	ring_to_create->create_req_id = DHD_H2D_DBGRING_REQ_PKTID;
++	ring_to_create->create_pending = TRUE;
++
++	/* Common msg buf hdr */
++	h2d_ring->msg.msg_type = MSG_TYPE_H2D_RING_CREATE;
++	h2d_ring->msg.if_id = 0;
++	h2d_ring->msg.request_id = htol32(ring_to_create->create_req_id);
++	h2d_ring->msg.flags = dhd->prot->h2dring_ctrl_subn.current_phase;
++	h2d_ring->ring_id = htol16(DHD_H2D_RING_OFFSET(ring_to_create->idx));
++	h2d_ring->ring_type = BCMPCIE_H2D_RING_TYPE_DBGBUF_SUBMIT;
++	h2d_ring->max_items = htol16(H2DRING_DYNAMIC_INFO_MAX_ITEM);
++	h2d_ring->n_completion_ids = ring_to_create->n_completion_ids;
++	h2d_ring->len_item = htol16(H2DRING_INFO_BUFPOST_ITEMSIZE);
++	h2d_ring->ring_ptr.low_addr = ring_to_create->base_addr.low_addr;
++	h2d_ring->ring_ptr.high_addr = ring_to_create->base_addr.high_addr;
++
++	for (i = 0; i < ring_to_create->n_completion_ids; i++) {
++		h2d_ring->completion_ring_ids[i] = htol16(ring_to_create->compeltion_ring_ids[i]);
++	}
++
++	h2d_ring->flags = 0;
++	h2d_ring->msg.epoch =
++		dhd->prot->h2dring_ctrl_subn.seqnum % H2D_EPOCH_MODULO;
++	dhd->prot->h2dring_ctrl_subn.seqnum++;
++
++	/* Update the flow_ring's WRITE index */
++	dhd_prot_ring_write_complete(dhd, &dhd->prot->h2dring_ctrl_subn, h2d_ring,
++		DHD_FLOWRING_DEFAULT_NITEMS_POSTED_H2D);
++
++err:
++	DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++	return ret;
++}
++
++/**
++ * dhd_prot_dma_indx_set - set a new WR or RD index in the DMA index array.
++ * Dongle will DMA the entire array (if DMA_INDX feature is enabled).
++ * See dhd_prot_dma_indx_init()
++ */
++void
++dhd_prot_dma_indx_set(dhd_pub_t *dhd, uint16 new_index, uint8 type, uint16 ringid)
++{
++	uint8 *ptr;
++	uint16 offset;
++	dhd_prot_t *prot = dhd->prot;
++	uint16 max_h2d_rings = dhd->bus->max_submission_rings;
++
++	switch (type) {
++		case H2D_DMA_INDX_WR_UPD:
++			ptr = (uint8 *)(prot->h2d_dma_indx_wr_buf.va);
++			offset = DHD_H2D_RING_OFFSET(ringid);
++			break;
++
++		case D2H_DMA_INDX_RD_UPD:
++			ptr = (uint8 *)(prot->d2h_dma_indx_rd_buf.va);
++			offset = DHD_D2H_RING_OFFSET(ringid, max_h2d_rings);
++			break;
++
++		case H2D_IFRM_INDX_WR_UPD:
++			ptr = (uint8 *)(prot->h2d_ifrm_indx_wr_buf.va);
++			offset = DHD_H2D_FRM_FLOW_RING_OFFSET(ringid);
++			break;
++
++		default:
++			DHD_ERROR(("%s: Invalid option for DMAing read/write index\n",
++				__FUNCTION__));
++			return;
++	}
++
++	ASSERT(prot->rw_index_sz != 0);
++	ptr += offset * prot->rw_index_sz;
++
++	*(uint16*)ptr = htol16(new_index);
++
++	OSL_CACHE_FLUSH((void *)ptr, prot->rw_index_sz);
++
++	DHD_TRACE(("%s: data %d type %d ringid %d ptr 0x%p offset %d\n",
++		__FUNCTION__, new_index, type, ringid, ptr, offset));
++
++} /* dhd_prot_dma_indx_set */
++
++
++/**
++ * dhd_prot_dma_indx_get - Fetch a WR or RD index from the dongle DMA-ed index
++ * array.
++ * Dongle DMAes an entire array to host memory (if the feature is enabled).
++ * See dhd_prot_dma_indx_init()
++ */
++static uint16
++dhd_prot_dma_indx_get(dhd_pub_t *dhd, uint8 type, uint16 ringid)
++{
++	uint8 *ptr;
++	uint16 data;
++	uint16 offset;
++	dhd_prot_t *prot = dhd->prot;
++	uint16 max_h2d_rings = dhd->bus->max_submission_rings;
++
++	switch (type) {
++		case H2D_DMA_INDX_WR_UPD:
++			ptr = (uint8 *)(prot->h2d_dma_indx_wr_buf.va);
++			offset = DHD_H2D_RING_OFFSET(ringid);
++			break;
++
++		case H2D_DMA_INDX_RD_UPD:
++			ptr = (uint8 *)(prot->h2d_dma_indx_rd_buf.va);
++			offset = DHD_H2D_RING_OFFSET(ringid);
++			break;
++
++		case D2H_DMA_INDX_WR_UPD:
++			ptr = (uint8 *)(prot->d2h_dma_indx_wr_buf.va);
++			offset = DHD_D2H_RING_OFFSET(ringid, max_h2d_rings);
++			break;
++
++		case D2H_DMA_INDX_RD_UPD:
++			ptr = (uint8 *)(prot->d2h_dma_indx_rd_buf.va);
++			offset = DHD_D2H_RING_OFFSET(ringid, max_h2d_rings);
++			break;
++
++		default:
++			DHD_ERROR(("%s: Invalid option for DMAing read/write index\n",
++				__FUNCTION__));
++			return 0;
++	}
++
++	ASSERT(prot->rw_index_sz != 0);
++	ptr += offset * prot->rw_index_sz;
++
++	OSL_CACHE_INV((void *)ptr, prot->rw_index_sz);
++
++	data = LTOH16(*((uint16*)ptr));
++
++	DHD_TRACE(("%s: data %d type %d ringid %d ptr 0x%p offset %d\n",
++		__FUNCTION__, data, type, ringid, ptr, offset));
++
++	return (data);
++
++} /* dhd_prot_dma_indx_get */
++
++/**
++ * An array of DMA read/write indices, containing information about host rings, can be maintained
++ * either in host memory or in device memory, dependent on preprocessor options. This function is,
++ * dependent on these options, called during driver initialization. It reserves and initializes
++ * blocks of DMA'able host memory containing an array of DMA read or DMA write indices. The physical
++ * address of these host memory blocks are communicated to the dongle later on. By reading this host
++ * memory, the dongle learns about the state of the host rings.
++ */
++
++static INLINE int
++dhd_prot_dma_indx_alloc(dhd_pub_t *dhd, uint8 type,
++	dhd_dma_buf_t *dma_buf, uint32 bufsz)
++{
++	int rc;
++
++	if ((dma_buf->len == bufsz) || (dma_buf->va != NULL))
++		return BCME_OK;
++
++	rc = dhd_dma_buf_alloc(dhd, dma_buf, bufsz);
++
++	return rc;
++}
++
++int
++dhd_prot_dma_indx_init(dhd_pub_t *dhd, uint32 rw_index_sz, uint8 type, uint32 length)
++{
++	uint32 bufsz;
++	dhd_prot_t *prot = dhd->prot;
++	dhd_dma_buf_t *dma_buf;
++
++	if (prot == NULL) {
++		DHD_ERROR(("prot is not inited\n"));
++		return BCME_ERROR;
++	}
++
++	/* Dongle advertizes 2B or 4B RW index size */
++	ASSERT(rw_index_sz != 0);
++	prot->rw_index_sz = rw_index_sz;
++
++	bufsz = rw_index_sz * length;
++
++	switch (type) {
++		case H2D_DMA_INDX_WR_BUF:
++			dma_buf = &prot->h2d_dma_indx_wr_buf;
++			if (dhd_prot_dma_indx_alloc(dhd, type, dma_buf, bufsz))
++				goto ret_no_mem;
++			DHD_ERROR(("H2D DMA WR INDX : array size %d = %d * %d\n",
++				dma_buf->len, rw_index_sz, length));
++			break;
++
++		case H2D_DMA_INDX_RD_BUF:
++			dma_buf = &prot->h2d_dma_indx_rd_buf;
++			if (dhd_prot_dma_indx_alloc(dhd, type, dma_buf, bufsz))
++				goto ret_no_mem;
++			DHD_ERROR(("H2D DMA RD INDX : array size %d = %d * %d\n",
++				dma_buf->len, rw_index_sz, length));
++			break;
++
++		case D2H_DMA_INDX_WR_BUF:
++			dma_buf = &prot->d2h_dma_indx_wr_buf;
++			if (dhd_prot_dma_indx_alloc(dhd, type, dma_buf, bufsz))
++				goto ret_no_mem;
++			DHD_ERROR(("D2H DMA WR INDX : array size %d = %d * %d\n",
++				dma_buf->len, rw_index_sz, length));
++			break;
++
++		case D2H_DMA_INDX_RD_BUF:
++			dma_buf = &prot->d2h_dma_indx_rd_buf;
++			if (dhd_prot_dma_indx_alloc(dhd, type, dma_buf, bufsz))
++				goto ret_no_mem;
++			DHD_ERROR(("D2H DMA RD INDX : array size %d = %d * %d\n",
++				dma_buf->len, rw_index_sz, length));
++			break;
++
++		case H2D_IFRM_INDX_WR_BUF:
++			dma_buf = &prot->h2d_ifrm_indx_wr_buf;
++			if (dhd_prot_dma_indx_alloc(dhd, type, dma_buf, bufsz))
++				goto ret_no_mem;
++			DHD_ERROR(("H2D IFRM WR INDX : array size %d = %d * %d\n",
++				dma_buf->len, rw_index_sz, length));
++			break;
++
++		default:
++			DHD_ERROR(("%s: Unexpected option\n", __FUNCTION__));
++			return BCME_BADOPTION;
++	}
++
++	return BCME_OK;
++
++ret_no_mem:
++	DHD_ERROR(("%s: dhd_prot_dma_indx_alloc type %d buf_sz %d failure\n",
++		__FUNCTION__, type, bufsz));
++	return BCME_NOMEM;
++
++} /* dhd_prot_dma_indx_init */
++
++
++/**
++ * Called on checking for 'completion' messages from the dongle. Returns next host buffer to read
++ * from, or NULL if there are no more messages to read.
++ */
++static uint8*
++dhd_prot_get_read_addr(dhd_pub_t *dhd, msgbuf_ring_t *ring, uint32 *available_len)
++{
++	uint16 wr;
++	uint16 rd;
++	uint16 depth;
++	uint16 items;
++	void  *read_addr = NULL; /* address of next msg to be read in ring */
++	uint16 d2h_wr = 0;
++
++	DHD_TRACE(("%s: d2h_dma_indx_rd_buf %p, d2h_dma_indx_wr_buf %p\n",
++		__FUNCTION__, (uint32 *)(dhd->prot->d2h_dma_indx_rd_buf.va),
++		(uint32 *)(dhd->prot->d2h_dma_indx_wr_buf.va)));
++
++	/* Remember the read index in a variable.
++	 * This is becuase ring->rd gets updated in the end of this function
++	 * So if we have to print the exact read index from which the
++	 * message is read its not possible.
++	 */
++	ring->curr_rd = ring->rd;
++
++	/* update write pointer */
++	if (dhd->dma_d2h_ring_upd_support) {
++		/* DMAing write/read indices supported */
++		d2h_wr = dhd_prot_dma_indx_get(dhd, D2H_DMA_INDX_WR_UPD, ring->idx);
++		ring->wr = d2h_wr;
++	} else {
++		dhd_bus_cmn_readshared(dhd->bus, &(ring->wr), RING_WR_UPD, ring->idx);
++	}
++
++	wr = ring->wr;
++	rd = ring->rd;
++	depth = ring->max_items;
++
++	/* check for avail space, in number of ring items */
++	items = READ_AVAIL_SPACE(wr, rd, depth);
++	if (items == 0)
++		return NULL;
++
++	/*
++	 * Note that there are builds where Assert translates to just printk
++	 * so, even if we had hit this condition we would never halt. Now
++	 * dhd_prot_process_msgtype can get into an big loop if this
++	 * happens.
++	 */
++	if (items > ring->max_items) {
++		DHD_ERROR(("\r\n======================= \r\n"));
++		DHD_ERROR(("%s(): ring %p, ring->name %s, ring->max_items %d, items %d \r\n",
++			__FUNCTION__, ring, ring->name, ring->max_items, items));
++		DHD_ERROR(("wr: %d,  rd: %d,  depth: %d  \r\n", wr, rd, depth));
++		DHD_ERROR(("dhd->busstate %d bus->wait_for_d3_ack %d \r\n",
++			dhd->busstate, dhd->bus->wait_for_d3_ack));
++		DHD_ERROR(("\r\n======================= \r\n"));
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++		if (wr >= ring->max_items) {
++			dhd->bus->read_shm_fail = TRUE;
++		}
++#else
++#ifdef DHD_FW_COREDUMP
++		if (dhd->memdump_enabled) {
++			/* collect core dump */
++			dhd->memdump_type = DUMP_TYPE_RESUMED_ON_INVALID_RING_RDWR;
++			dhd_bus_mem_dump(dhd);
++
++		}
++#endif /* DHD_FW_COREDUMP */
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++
++		*available_len = 0;
++		dhd_schedule_reset(dhd);
++
++		return NULL;
++	}
++
++	/* if space is available, calculate address to be read */
++	read_addr = (char*)ring->dma_buf.va + (rd * ring->item_len);
++
++	/* update read pointer */
++	if ((ring->rd + items) >= ring->max_items)
++		ring->rd = 0;
++	else
++		ring->rd += items;
++
++	ASSERT(ring->rd < ring->max_items);
++
++	/* convert items to bytes : available_len must be 32bits */
++	*available_len = (uint32)(items * ring->item_len);
++
++	OSL_CACHE_INV(read_addr, *available_len);
++
++	/* return read address */
++	return read_addr;
++
++} /* dhd_prot_get_read_addr */
++
++/**
++ * dhd_prot_h2d_mbdata_send_ctrlmsg is a non-atomic function,
++ * make sure the callers always hold appropriate locks.
++ */
++int dhd_prot_h2d_mbdata_send_ctrlmsg(dhd_pub_t *dhd, uint32 mb_data)
++{
++	h2d_mailbox_data_t *h2d_mb_data;
++	uint16 alloced = 0;
++	int num_post = 1;
++	int i;
++
++	DHD_INFO(("%s Sending H2D MB data Req data 0x%04x\n",
++		__FUNCTION__, mb_data));
++	if (!dhd->prot->h2dring_ctrl_subn.inited) {
++		DHD_ERROR(("%s: Ctrl Submit Ring: not inited\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++#ifdef PCIE_INB_DW
++	if ((INBAND_DW_ENAB(dhd->bus)) &&
++		(dhdpcie_bus_get_pcie_inband_dw_state(dhd->bus) ==
++			DW_DEVICE_DS_DEV_SLEEP)) {
++		if (mb_data == H2D_HOST_CONS_INT) {
++			/* One additional device_wake post needed */
++			num_post = 2;
++		}
++	}
++#endif /* PCIE_INB_DW */
++
++	for (i = 0; i < num_post; i ++) {
++		/* Request for ring buffer space */
++		h2d_mb_data = (h2d_mailbox_data_t *)dhd_prot_alloc_ring_space(dhd,
++			&dhd->prot->h2dring_ctrl_subn, DHD_FLOWRING_DEFAULT_NITEMS_POSTED_H2D,
++			&alloced, FALSE);
++
++		if (h2d_mb_data == NULL) {
++			DHD_ERROR(("%s: FATAL: No space in control ring to send H2D Mb data\n",
++				__FUNCTION__));
++			return BCME_NOMEM;
++		}
++
++		memset(h2d_mb_data, 0, sizeof(h2d_mailbox_data_t));
++	/* Common msg buf hdr */
++		h2d_mb_data->msg.msg_type = MSG_TYPE_H2D_MAILBOX_DATA;
++		h2d_mb_data->msg.flags = dhd->prot->h2dring_ctrl_subn.current_phase;
++
++		h2d_mb_data->msg.epoch =
++			dhd->prot->h2dring_ctrl_subn.seqnum % H2D_EPOCH_MODULO;
++		dhd->prot->h2dring_ctrl_subn.seqnum++;
++
++#ifdef PCIE_INB_DW
++		/* post device_wake first */
++		if ((num_post == 2) && (i == 0)) {
++			h2d_mb_data->mail_box_data = htol32(H2DMB_DS_DEVICE_WAKE);
++		} else
++#endif /* PCIE_INB_DW */
++		{
++			h2d_mb_data->mail_box_data = htol32(mb_data);
++		}
++
++		DHD_INFO(("%s Send H2D MB data Req data 0x%04x\n", __FUNCTION__, mb_data));
++
++		/* upd wrt ptr and raise interrupt */
++		/* caller of dhd_prot_h2d_mbdata_send_ctrlmsg already holding general lock */
++		dhd_prot_ring_write_complete(dhd, &dhd->prot->h2dring_ctrl_subn, h2d_mb_data,
++			DHD_FLOWRING_DEFAULT_NITEMS_POSTED_H2D);
++#ifdef PCIE_INB_DW
++		/* Add a delay if device_wake is posted */
++		if ((num_post == 2) && (i == 0)) {
++			OSL_DELAY(1000);
++		}
++#endif /* PCIE_INB_DW */
++	}
++
++	return 0;
++}
++
++/** Creates a flow ring and informs dongle of this event */
++int
++dhd_prot_flow_ring_create(dhd_pub_t *dhd, flow_ring_node_t *flow_ring_node)
++{
++	tx_flowring_create_request_t *flow_create_rqst;
++	msgbuf_ring_t *flow_ring;
++	dhd_prot_t *prot = dhd->prot;
++	unsigned long flags;
++	uint16 alloced = 0;
++	msgbuf_ring_t *ctrl_ring = &prot->h2dring_ctrl_subn;
++	uint16 max_flowrings = dhd->bus->max_tx_flowrings;
++
++	/* Fetch a pre-initialized msgbuf_ring from the flowring pool */
++	flow_ring = dhd_prot_flowrings_pool_fetch(dhd, flow_ring_node->flowid);
++	if (flow_ring == NULL) {
++		DHD_ERROR(("%s: dhd_prot_flowrings_pool_fetch TX Flowid %d failed\n",
++			__FUNCTION__, flow_ring_node->flowid));
++		return BCME_NOMEM;
++	}
++
++#ifdef PCIE_INB_DW
++	if (dhd_prot_inc_hostactive_devwake_assert(dhd->bus) != BCME_OK)
++		return BCME_ERROR;
++#endif /* PCIE_INB_DW */
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	/* Request for ctrl_ring buffer space */
++	flow_create_rqst = (tx_flowring_create_request_t *)
++		dhd_prot_alloc_ring_space(dhd, ctrl_ring, 1, &alloced, FALSE);
++
++	if (flow_create_rqst == NULL) {
++		dhd_prot_flowrings_pool_release(dhd, flow_ring_node->flowid, flow_ring);
++		DHD_ERROR(("%s: Flow Create Req flowid %d - failure ring space\n",
++			__FUNCTION__, flow_ring_node->flowid));
++		DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++		dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++		return BCME_NOMEM;
++	}
++
++	flow_ring_node->prot_info = (void *)flow_ring;
++
++	/* Common msg buf hdr */
++	flow_create_rqst->msg.msg_type = MSG_TYPE_FLOW_RING_CREATE;
++	flow_create_rqst->msg.if_id = (uint8)flow_ring_node->flow_info.ifindex;
++	flow_create_rqst->msg.request_id = htol32(0); /* TBD */
++	flow_create_rqst->msg.flags = ctrl_ring->current_phase;
++
++	flow_create_rqst->msg.epoch = ctrl_ring->seqnum % H2D_EPOCH_MODULO;
++	ctrl_ring->seqnum++;
++
++	/* Update flow create message */
++	flow_create_rqst->tid = flow_ring_node->flow_info.tid;
++	flow_create_rqst->flow_ring_id = htol16((uint16)flow_ring_node->flowid);
++	memcpy(flow_create_rqst->sa, flow_ring_node->flow_info.sa, sizeof(flow_create_rqst->sa));
++	memcpy(flow_create_rqst->da, flow_ring_node->flow_info.da, sizeof(flow_create_rqst->da));
++	/* CAUTION: ring::base_addr already in Little Endian */
++	flow_create_rqst->flow_ring_ptr.low_addr = flow_ring->base_addr.low_addr;
++	flow_create_rqst->flow_ring_ptr.high_addr = flow_ring->base_addr.high_addr;
++	flow_create_rqst->max_items = htol16(prot->h2d_max_txpost);
++	flow_create_rqst->len_item = htol16(H2DRING_TXPOST_ITEMSIZE);
++
++	/* definition for ifrm mask : bit0:d11ac core, bit1:d11ad core
++	 * currently it is not used for priority. so uses solely for ifrm mask
++	 */
++	if (IFRM_ACTIVE(dhd))
++		flow_create_rqst->priority_ifrmmask = (1 << IFRM_DEV_0);
++
++	DHD_ERROR(("%s: Send Flow Create Req flow ID %d for peer " MACDBG
++		" prio %d ifindex %d\n", __FUNCTION__, flow_ring_node->flowid,
++		MAC2STRDBG(flow_ring_node->flow_info.da), flow_ring_node->flow_info.tid,
++		flow_ring_node->flow_info.ifindex));
++
++	/* Update the flow_ring's WRITE index */
++	if (IDMA_ACTIVE(dhd) || dhd->dma_h2d_ring_upd_support) {
++		dhd_prot_dma_indx_set(dhd, flow_ring->wr,
++		                      H2D_DMA_INDX_WR_UPD, flow_ring->idx);
++	} else if (IFRM_ACTIVE(dhd) && DHD_IS_FLOWRING(flow_ring->idx, max_flowrings)) {
++		dhd_prot_dma_indx_set(dhd, flow_ring->wr,
++			H2D_IFRM_INDX_WR_UPD, flow_ring->idx);
++	} else {
++		dhd_bus_cmn_writeshared(dhd->bus, &(flow_ring->wr),
++			sizeof(uint16), RING_WR_UPD, flow_ring->idx);
++	}
++
++	/* update control subn ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ctrl_ring, flow_create_rqst, 1);
++
++	DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++
++	return BCME_OK;
++} /* dhd_prot_flow_ring_create */
++
++/** called on receiving MSG_TYPE_FLOW_RING_CREATE_CMPLT message from dongle */
++static void
++dhd_prot_flow_ring_create_response_process(dhd_pub_t *dhd, void *msg)
++{
++	tx_flowring_create_response_t *flow_create_resp = (tx_flowring_create_response_t *)msg;
++
++	DHD_ERROR(("%s: Flow Create Response status = %d Flow %d\n", __FUNCTION__,
++		ltoh16(flow_create_resp->cmplt.status),
++		ltoh16(flow_create_resp->cmplt.flow_ring_id)));
++
++	dhd_bus_flow_ring_create_response(dhd->bus,
++		ltoh16(flow_create_resp->cmplt.flow_ring_id),
++		ltoh16(flow_create_resp->cmplt.status));
++}
++
++static void
++dhd_prot_process_h2d_ring_create_complete(dhd_pub_t *dhd, void *buf)
++{
++	h2d_ring_create_response_t *resp = (h2d_ring_create_response_t *)buf;
++	DHD_INFO(("%s ring create Response status = %d ring %d, id 0x%04x\n", __FUNCTION__,
++		ltoh16(resp->cmplt.status),
++		ltoh16(resp->cmplt.ring_id),
++		ltoh32(resp->cmn_hdr.request_id)));
++	if (ltoh32(resp->cmn_hdr.request_id) != DHD_H2D_DBGRING_REQ_PKTID) {
++		DHD_ERROR(("invalid request ID with h2d ring create complete\n"));
++		return;
++	}
++	if (!dhd->prot->h2dring_info_subn->create_pending) {
++		DHD_ERROR(("info ring create status for not pending submit ring\n"));
++	}
++
++	if (ltoh16(resp->cmplt.status) != BCMPCIE_SUCCESS) {
++		DHD_ERROR(("info ring create failed with status %d\n",
++			ltoh16(resp->cmplt.status)));
++		return;
++	}
++	dhd->prot->h2dring_info_subn->create_pending = FALSE;
++	dhd->prot->h2dring_info_subn->inited = TRUE;
++	dhd_prot_infobufpost(dhd);
++}
++
++static void
++dhd_prot_process_d2h_ring_create_complete(dhd_pub_t *dhd, void *buf)
++{
++	d2h_ring_create_response_t *resp = (d2h_ring_create_response_t *)buf;
++	DHD_INFO(("%s ring create Response status = %d ring %d, id 0x%04x\n", __FUNCTION__,
++		ltoh16(resp->cmplt.status),
++		ltoh16(resp->cmplt.ring_id),
++		ltoh32(resp->cmn_hdr.request_id)));
++	if (ltoh32(resp->cmn_hdr.request_id) != DHD_D2H_DBGRING_REQ_PKTID) {
++		DHD_ERROR(("invalid request ID with d2h ring create complete\n"));
++		return;
++	}
++	if (!dhd->prot->d2hring_info_cpln->create_pending) {
++		DHD_ERROR(("info ring create status for not pending cpl ring\n"));
++		return;
++	}
++
++	if (ltoh16(resp->cmplt.status) != BCMPCIE_SUCCESS) {
++		DHD_ERROR(("info cpl ring create failed with status %d\n",
++			ltoh16(resp->cmplt.status)));
++		return;
++	}
++	dhd->prot->d2hring_info_cpln->create_pending = FALSE;
++	dhd->prot->d2hring_info_cpln->inited = TRUE;
++}
++
++static void
++dhd_prot_process_d2h_mb_data(dhd_pub_t *dhd, void* buf)
++{
++	d2h_mailbox_data_t *d2h_data;
++
++	d2h_data = (d2h_mailbox_data_t *)buf;
++	DHD_INFO(("%s dhd_prot_process_d2h_mb_data, 0x%04x\n", __FUNCTION__,
++		d2h_data->d2h_mailbox_data));
++	dhd_bus_handle_mb_data(dhd->bus, d2h_data->d2h_mailbox_data);
++}
++
++static void
++dhd_prot_process_d2h_host_ts_complete(dhd_pub_t *dhd, void* buf)
++{
++#ifdef DHD_TIMESYNC
++	host_timestamp_msg_cpl_t  *host_ts_cpl;
++	uint32 pktid;
++	dhd_prot_t *prot = dhd->prot;
++
++	host_ts_cpl = (host_timestamp_msg_cpl_t *)buf;
++	DHD_INFO(("%s host TS cpl: status %d, req_ID: 0x%04x, xt_id %d \n", __FUNCTION__,
++		host_ts_cpl->cmplt.status, host_ts_cpl->msg.request_id, host_ts_cpl->xt_id));
++
++	pktid = ltoh32(host_ts_cpl->msg.request_id);
++	if (prot->hostts_req_buf_inuse == FALSE) {
++		DHD_ERROR(("No Pending Host TS req, but completion\n"));
++		return;
++	}
++	prot->hostts_req_buf_inuse = FALSE;
++	if (pktid != DHD_H2D_HOSTTS_REQ_PKTID) {
++		DHD_ERROR(("Host TS req CPL, but req ID different 0x%04x, exp 0x%04x\n",
++			pktid, DHD_H2D_HOSTTS_REQ_PKTID));
++		return;
++	}
++	dhd_timesync_handle_host_ts_complete(dhd->ts, host_ts_cpl->xt_id,
++		host_ts_cpl->cmplt.status);
++#else /* DHD_TIMESYNC */
++	DHD_ERROR(("Timesunc feature not compiled in but GOT HOST_TS_COMPLETE\n"));
++#endif /* DHD_TIMESYNC */
++
++}
++
++/** called on e.g. flow ring delete */
++void dhd_prot_clean_flow_ring(dhd_pub_t *dhd, void *msgbuf_flow_info)
++{
++	msgbuf_ring_t *flow_ring = (msgbuf_ring_t *)msgbuf_flow_info;
++	dhd_prot_ring_detach(dhd, flow_ring);
++	DHD_INFO(("%s Cleaning up Flow \n", __FUNCTION__));
++}
++
++void dhd_prot_print_flow_ring(dhd_pub_t *dhd, void *msgbuf_flow_info,
++	struct bcmstrbuf *strbuf, const char * fmt)
++{
++	const char *default_fmt = "RD %d WR %d BASE(VA) %p BASE(PA) %x:%x"
++		" WORK ITEM SIZE %d MAX WORK ITEMS %d SIZE %d\n";
++	msgbuf_ring_t *flow_ring = (msgbuf_ring_t *)msgbuf_flow_info;
++	uint16 rd, wr;
++	uint32 dma_buf_len = flow_ring->max_items * flow_ring->item_len;
++
++	if (fmt == NULL) {
++		fmt = default_fmt;
++	}
++	dhd_bus_cmn_readshared(dhd->bus, &rd, RING_RD_UPD, flow_ring->idx);
++	dhd_bus_cmn_readshared(dhd->bus, &wr, RING_WR_UPD, flow_ring->idx);
++	bcm_bprintf(strbuf, fmt, rd, wr, flow_ring->dma_buf.va,
++		ltoh32(flow_ring->base_addr.high_addr),
++		ltoh32(flow_ring->base_addr.low_addr),
++		flow_ring->item_len, flow_ring->max_items, dma_buf_len);
++}
++
++void dhd_prot_print_info(dhd_pub_t *dhd, struct bcmstrbuf *strbuf)
++{
++	dhd_prot_t *prot = dhd->prot;
++	bcm_bprintf(strbuf, "IPCrevs: Dev %d, \t Host %d, \tactive %d\n",
++		dhd->prot->device_ipc_version,
++		dhd->prot->host_ipc_version,
++		dhd->prot->active_ipc_version);
++
++	bcm_bprintf(strbuf, "max Host TS bufs to post: %d, \t posted %d \n",
++		dhd->prot->max_tsbufpost, dhd->prot->cur_ts_bufs_posted);
++	bcm_bprintf(strbuf, "max INFO bufs to post: %d, \t posted %d \n",
++		dhd->prot->max_infobufpost, dhd->prot->infobufpost);
++	bcm_bprintf(strbuf, "max event bufs to post: %d, \t posted %d \n",
++		dhd->prot->max_eventbufpost, dhd->prot->cur_event_bufs_posted);
++	bcm_bprintf(strbuf, "max ioctlresp bufs to post: %d, \t posted %d \n",
++		dhd->prot->max_ioctlrespbufpost, dhd->prot->cur_ioctlresp_bufs_posted);
++	bcm_bprintf(strbuf, "max RX bufs to post: %d, \t posted %d \n",
++		dhd->prot->max_rxbufpost, dhd->prot->rxbufpost);
++
++	bcm_bprintf(strbuf,
++		"%14s %5s %5s %17s %17s %14s %14s %10s\n",
++		"Type", "RD", "WR", "BASE(VA)", "BASE(PA)",
++		"WORK_ITEM_SIZE", "MAX_WORK_ITEMS", "TOTAL_SIZE");
++	bcm_bprintf(strbuf, "%14s", "H2DCtrlPost");
++	dhd_prot_print_flow_ring(dhd, &prot->h2dring_ctrl_subn, strbuf,
++		" %5d %5d %17p %8x:%8x %14d %14d %10d\n");
++	bcm_bprintf(strbuf, "%14s", "D2HCtrlCpl");
++	dhd_prot_print_flow_ring(dhd, &prot->d2hring_ctrl_cpln, strbuf,
++		" %5d %5d %17p %8x:%8x %14d %14d %10d\n");
++	bcm_bprintf(strbuf, "%14s", "H2DRxPost", prot->rxbufpost);
++	dhd_prot_print_flow_ring(dhd, &prot->h2dring_rxp_subn, strbuf,
++		" %5d %5d %17p %8x:%8x %14d %14d %10d\n");
++	bcm_bprintf(strbuf, "%14s", "D2HRxCpl");
++	dhd_prot_print_flow_ring(dhd, &prot->d2hring_rx_cpln, strbuf,
++		" %5d %5d %17p %8x:%8x %14d %14d %10d\n");
++	bcm_bprintf(strbuf, "%14s", "D2HTxCpl");
++	dhd_prot_print_flow_ring(dhd, &prot->d2hring_tx_cpln, strbuf,
++		" %5d %5d %17p %8x:%8x %14d %14d %10d\n");
++	if (dhd->prot->h2dring_info_subn != NULL && dhd->prot->d2hring_info_cpln != NULL) {
++		bcm_bprintf(strbuf, "%14s", "H2DRingInfoSub");
++		dhd_prot_print_flow_ring(dhd, prot->h2dring_info_subn, strbuf,
++			" %5d %5d %17p %8x:%8x %14d %14d %10d\n");
++		bcm_bprintf(strbuf, "%14s", "D2HRingInfoCpl");
++		dhd_prot_print_flow_ring(dhd, prot->d2hring_info_cpln, strbuf,
++			" %5d %5d %17p %8x:%8x %14d %14d %10d\n");
++	}
++
++	bcm_bprintf(strbuf, "active_tx_count %d	 pktidmap_avail(ctrl/rx/tx) %d %d %d\n",
++		dhd->prot->active_tx_count,
++		DHD_PKTID_AVAIL(dhd->prot->pktid_ctrl_map),
++		DHD_PKTID_AVAIL(dhd->prot->pktid_rx_map),
++		DHD_PKTID_AVAIL(dhd->prot->pktid_tx_map));
++
++}
++
++int
++dhd_prot_flow_ring_delete(dhd_pub_t *dhd, flow_ring_node_t *flow_ring_node)
++{
++	tx_flowring_delete_request_t *flow_delete_rqst;
++	dhd_prot_t *prot = dhd->prot;
++	unsigned long flags;
++	uint16 alloced = 0;
++	msgbuf_ring_t *ring = &prot->h2dring_ctrl_subn;
++
++#ifdef PCIE_INB_DW
++	if (dhd_prot_inc_hostactive_devwake_assert(dhd->bus) != BCME_OK)
++		return BCME_ERROR;
++#endif /* PCIE_INB_DW */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	/* Request for ring buffer space */
++	flow_delete_rqst = (tx_flowring_delete_request_t *)
++		dhd_prot_alloc_ring_space(dhd, ring, 1, &alloced, FALSE);
++
++	if (flow_delete_rqst == NULL) {
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		DHD_ERROR(("%s: Flow Delete Req - failure ring space\n", __FUNCTION__));
++#ifdef PCIE_INB_DW
++		dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++		return BCME_NOMEM;
++	}
++
++	/* Common msg buf hdr */
++	flow_delete_rqst->msg.msg_type = MSG_TYPE_FLOW_RING_DELETE;
++	flow_delete_rqst->msg.if_id = (uint8)flow_ring_node->flow_info.ifindex;
++	flow_delete_rqst->msg.request_id = htol32(0); /* TBD */
++	flow_delete_rqst->msg.flags = ring->current_phase;
++
++	flow_delete_rqst->msg.epoch = ring->seqnum % H2D_EPOCH_MODULO;
++	ring->seqnum++;
++
++	/* Update Delete info */
++	flow_delete_rqst->flow_ring_id = htol16((uint16)flow_ring_node->flowid);
++	flow_delete_rqst->reason = htol16(BCME_OK);
++
++	DHD_ERROR(("%s: Send Flow Delete Req RING ID %d for peer " MACDBG
++		" prio %d ifindex %d\n", __FUNCTION__, flow_ring_node->flowid,
++		MAC2STRDBG(flow_ring_node->flow_info.da), flow_ring_node->flow_info.tid,
++		flow_ring_node->flow_info.ifindex));
++
++	/* update ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ring, flow_delete_rqst, 1);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++
++	return BCME_OK;
++}
++
++static void
++dhd_prot_flow_ring_delete_response_process(dhd_pub_t *dhd, void *msg)
++{
++	tx_flowring_delete_response_t *flow_delete_resp = (tx_flowring_delete_response_t *)msg;
++
++	DHD_ERROR(("%s: Flow Delete Response status = %d Flow %d\n", __FUNCTION__,
++		flow_delete_resp->cmplt.status, flow_delete_resp->cmplt.flow_ring_id));
++
++	dhd_bus_flow_ring_delete_response(dhd->bus, flow_delete_resp->cmplt.flow_ring_id,
++		flow_delete_resp->cmplt.status);
++}
++
++static void
++dhd_prot_process_flow_ring_resume_response(dhd_pub_t *dhd, void* msg)
++{
++#ifdef IDLE_TX_FLOW_MGMT
++	tx_idle_flowring_resume_response_t	*flow_resume_resp =
++		(tx_idle_flowring_resume_response_t *)msg;
++
++	DHD_ERROR(("%s Flow resume Response status = %d Flow %d\n", __FUNCTION__,
++		flow_resume_resp->cmplt.status, flow_resume_resp->cmplt.flow_ring_id));
++
++	dhd_bus_flow_ring_resume_response(dhd->bus, flow_resume_resp->cmplt.flow_ring_id,
++		flow_resume_resp->cmplt.status);
++#endif /* IDLE_TX_FLOW_MGMT */
++}
++
++static void
++dhd_prot_process_flow_ring_suspend_response(dhd_pub_t *dhd, void* msg)
++{
++#ifdef IDLE_TX_FLOW_MGMT
++	int16 status;
++	tx_idle_flowring_suspend_response_t	*flow_suspend_resp =
++		(tx_idle_flowring_suspend_response_t *)msg;
++	status = flow_suspend_resp->cmplt.status;
++
++	DHD_ERROR(("%s Flow id %d suspend Response status = %d\n",
++		__FUNCTION__, flow_suspend_resp->cmplt.flow_ring_id,
++		status));
++
++	if (status != BCME_OK) {
++
++		DHD_ERROR(("%s Error in Suspending Flow rings!!"
++			"Dongle will still be polling idle rings!!Status = %d \n",
++			__FUNCTION__, status));
++	}
++#endif /* IDLE_TX_FLOW_MGMT */
++}
++
++int
++dhd_prot_flow_ring_flush(dhd_pub_t *dhd, flow_ring_node_t *flow_ring_node)
++{
++	tx_flowring_flush_request_t *flow_flush_rqst;
++	dhd_prot_t *prot = dhd->prot;
++	unsigned long flags;
++	uint16 alloced = 0;
++	msgbuf_ring_t *ring = &prot->h2dring_ctrl_subn;
++
++#ifdef PCIE_INB_DW
++	if (dhd_prot_inc_hostactive_devwake_assert(dhd->bus) != BCME_OK)
++		return BCME_ERROR;
++#endif /* PCIE_INB_DW */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	/* Request for ring buffer space */
++	flow_flush_rqst = (tx_flowring_flush_request_t *)
++		dhd_prot_alloc_ring_space(dhd, ring, 1, &alloced, FALSE);
++	if (flow_flush_rqst == NULL) {
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		DHD_ERROR(("%s: Flow Flush Req - failure ring space\n", __FUNCTION__));
++#ifdef PCIE_INB_DW
++		dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++		return BCME_NOMEM;
++	}
++
++	/* Common msg buf hdr */
++	flow_flush_rqst->msg.msg_type = MSG_TYPE_FLOW_RING_FLUSH;
++	flow_flush_rqst->msg.if_id = (uint8)flow_ring_node->flow_info.ifindex;
++	flow_flush_rqst->msg.request_id = htol32(0); /* TBD */
++	flow_flush_rqst->msg.flags = ring->current_phase;
++	flow_flush_rqst->msg.epoch = ring->seqnum % H2D_EPOCH_MODULO;
++	ring->seqnum++;
++
++	flow_flush_rqst->flow_ring_id = htol16((uint16)flow_ring_node->flowid);
++	flow_flush_rqst->reason = htol16(BCME_OK);
++
++	DHD_INFO(("%s: Send Flow Flush Req\n", __FUNCTION__));
++
++	/* update ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ring, flow_flush_rqst, 1);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++
++	return BCME_OK;
++} /* dhd_prot_flow_ring_flush */
++
++static void
++dhd_prot_flow_ring_flush_response_process(dhd_pub_t *dhd, void *msg)
++{
++	tx_flowring_flush_response_t *flow_flush_resp = (tx_flowring_flush_response_t *)msg;
++
++	DHD_INFO(("%s: Flow Flush Response status = %d\n", __FUNCTION__,
++		flow_flush_resp->cmplt.status));
++
++	dhd_bus_flow_ring_flush_response(dhd->bus, flow_flush_resp->cmplt.flow_ring_id,
++		flow_flush_resp->cmplt.status);
++}
++
++/**
++ * Request dongle to configure soft doorbells for D2H rings. Host populated soft
++ * doorbell information is transferred to dongle via the d2h ring config control
++ * message.
++ */
++void
++dhd_msgbuf_ring_config_d2h_soft_doorbell(dhd_pub_t *dhd)
++{
++#if defined(DHD_D2H_SOFT_DOORBELL_SUPPORT)
++	uint16 ring_idx;
++	uint8 *msg_next;
++	void *msg_start;
++	uint16 alloced = 0;
++	unsigned long flags;
++	dhd_prot_t *prot = dhd->prot;
++	ring_config_req_t *ring_config_req;
++	bcmpcie_soft_doorbell_t *soft_doorbell;
++	msgbuf_ring_t *ctrl_ring = &prot->h2dring_ctrl_subn;
++	const uint16 d2h_rings = BCMPCIE_D2H_COMMON_MSGRINGS;
++
++#ifdef PCIE_INB_DW
++	if (dhd_prot_inc_hostactive_devwake_assert(dhd->bus) != BCME_OK)
++		return BCME_ERROR;
++#endif /* PCIE_INB_DW */
++	/* Claim space for d2h_ring number of d2h_ring_config_req_t messages */
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	msg_start = dhd_prot_alloc_ring_space(dhd, ctrl_ring, d2h_rings, &alloced, TRUE);
++
++	if (msg_start == NULL) {
++		DHD_ERROR(("%s Msgbuf no space for %d D2H ring config soft doorbells\n",
++			__FUNCTION__, d2h_rings));
++		DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++		dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++		return;
++	}
++
++	msg_next = (uint8*)msg_start;
++
++	for (ring_idx = 0; ring_idx < d2h_rings; ring_idx++) {
++
++		/* position the ring_config_req into the ctrl subm ring */
++		ring_config_req = (ring_config_req_t *)msg_next;
++
++		/* Common msg header */
++		ring_config_req->msg.msg_type = MSG_TYPE_D2H_RING_CONFIG;
++		ring_config_req->msg.if_id = 0;
++		ring_config_req->msg.flags = 0;
++
++		ring_config_req->msg.epoch = ctrl_ring->seqnum % H2D_EPOCH_MODULO;
++		ctrl_ring->seqnum++;
++
++		ring_config_req->msg.request_id = htol32(DHD_FAKE_PKTID); /* unused */
++
++		/* Ring Config subtype and d2h ring_id */
++		ring_config_req->subtype = htol16(D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL);
++		ring_config_req->ring_id = htol16(DHD_D2H_RINGID(ring_idx));
++
++		/* Host soft doorbell configuration */
++		soft_doorbell = &prot->soft_doorbell[ring_idx];
++
++		ring_config_req->soft_doorbell.value = htol32(soft_doorbell->value);
++		ring_config_req->soft_doorbell.haddr.high =
++			htol32(soft_doorbell->haddr.high);
++		ring_config_req->soft_doorbell.haddr.low =
++			htol32(soft_doorbell->haddr.low);
++		ring_config_req->soft_doorbell.items = htol16(soft_doorbell->items);
++		ring_config_req->soft_doorbell.msecs = htol16(soft_doorbell->msecs);
++
++		DHD_INFO(("%s: Soft doorbell haddr 0x%08x 0x%08x value 0x%08x\n",
++			__FUNCTION__, ring_config_req->soft_doorbell.haddr.high,
++			ring_config_req->soft_doorbell.haddr.low,
++			ring_config_req->soft_doorbell.value));
++
++		msg_next = msg_next + ctrl_ring->item_len;
++	}
++
++	/* update control subn ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ctrl_ring, msg_start, d2h_rings);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++#endif /* DHD_D2H_SOFT_DOORBELL_SUPPORT */
++}
++
++static void
++dhd_prot_process_d2h_ring_config_complete(dhd_pub_t *dhd, void *msg)
++{
++	DHD_INFO(("%s: Ring Config Response - status %d ringid %d\n",
++		__FUNCTION__, ltoh16(((ring_config_resp_t *)msg)->compl_hdr.status),
++		ltoh16(((ring_config_resp_t *)msg)->compl_hdr.flow_ring_id)));
++}
++
++int
++dhd_prot_debug_dma_info_print(dhd_pub_t *dhd)
++{
++	if (dhd->bus->is_linkdown) {
++		DHD_ERROR(("\n ------- SKIP DUMPING DMA Registers "
++			"due to PCIe link down ------- \r\n"));
++		return 0;
++	}
++
++	DHD_ERROR(("\n ------- DUMPING DMA Registers ------- \r\n"));
++
++	//HostToDev
++	DHD_ERROR(("HostToDev TX: XmtCtrl=0x%08x XmtPtr=0x%08x\n",
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x200, 0, 0),
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x204, 0, 0)));
++	DHD_ERROR(("            : XmtAddrLow=0x%08x XmtAddrHigh=0x%08x\n",
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x208, 0, 0),
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x20C, 0, 0)));
++	DHD_ERROR(("            : XmtStatus0=0x%08x XmtStatus1=0x%08x\n",
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x210, 0, 0),
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x214, 0, 0)));
++
++	DHD_ERROR(("HostToDev RX: RcvCtrl=0x%08x RcvPtr=0x%08x\n",
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x220, 0, 0),
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x224, 0, 0)));
++	DHD_ERROR(("            : RcvAddrLow=0x%08x RcvAddrHigh=0x%08x\n",
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x228, 0, 0),
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x22C, 0, 0)));
++	DHD_ERROR(("            : RcvStatus0=0x%08x RcvStatus1=0x%08x\n",
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x230, 0, 0),
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x234, 0, 0)));
++
++	//DevToHost
++	DHD_ERROR(("DevToHost TX: XmtCtrl=0x%08x XmtPtr=0x%08x\n",
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x240, 0, 0),
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x244, 0, 0)));
++	DHD_ERROR(("            : XmtAddrLow=0x%08x XmtAddrHigh=0x%08x\n",
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x248, 0, 0),
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x24C, 0, 0)));
++	DHD_ERROR(("            : XmtStatus0=0x%08x XmtStatus1=0x%08x\n",
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x250, 0, 0),
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x254, 0, 0)));
++
++	DHD_ERROR(("DevToHost RX: RcvCtrl=0x%08x RcvPtr=0x%08x\n",
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x260, 0, 0),
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x264, 0, 0)));
++	DHD_ERROR(("            : RcvAddrLow=0x%08x RcvAddrHigh=0x%08x\n",
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x268, 0, 0),
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x26C, 0, 0)));
++	DHD_ERROR(("            : RcvStatus0=0x%08x RcvStatus1=0x%08x\n",
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x270, 0, 0),
++		si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, 0x274, 0, 0)));
++
++	return 0;
++}
++
++int
++dhd_prot_debug_info_print(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	msgbuf_ring_t *ring;
++	uint16 rd, wr;
++	uint32 intstatus = 0;
++	uint32 intmask = 0;
++	uint32 mbintstatus = 0;
++	uint32 d2h_mb_data = 0;
++	uint32 dma_buf_len;
++
++	DHD_ERROR(("\n ------- DUMPING VERSION INFORMATION ------- \r\n"));
++	DHD_ERROR(("DHD: %s\n", dhd_version));
++	DHD_ERROR(("Firmware: %s\n", fw_version));
++
++	DHD_ERROR(("\n ------- DUMPING PROTOCOL INFORMATION ------- \r\n"));
++	DHD_ERROR(("ICPrevs: Dev %d, Host %d, active %d\n",
++		prot->device_ipc_version,
++		prot->host_ipc_version,
++		prot->active_ipc_version));
++	DHD_ERROR(("max Host TS bufs to post: %d, posted %d\n",
++		prot->max_tsbufpost, prot->cur_ts_bufs_posted));
++	DHD_ERROR(("max INFO bufs to post: %d, posted %d\n",
++		prot->max_infobufpost, prot->infobufpost));
++	DHD_ERROR(("max event bufs to post: %d, posted %d\n",
++		prot->max_eventbufpost, prot->cur_event_bufs_posted));
++	DHD_ERROR(("max ioctlresp bufs to post: %d, posted %d\n",
++		prot->max_ioctlrespbufpost, prot->cur_ioctlresp_bufs_posted));
++	DHD_ERROR(("max RX bufs to post: %d, posted %d\n",
++		prot->max_rxbufpost, prot->rxbufpost));
++	DHD_ERROR(("h2d_max_txpost: %d, prot->h2d_max_txpost: %d\n",
++		h2d_max_txpost, prot->h2d_max_txpost));
++
++	DHD_ERROR(("\n ------- DUMPING IOCTL RING RD WR Pointers ------- \r\n"));
++
++	ring = &prot->h2dring_ctrl_subn;
++	dma_buf_len = ring->max_items * ring->item_len;
++	DHD_ERROR(("CtrlPost: Mem Info: BASE(VA) %p BASE(PA) %x:%x SIZE %d \r\n",
++		ring->dma_buf.va, ltoh32(ring->base_addr.high_addr),
++		ltoh32(ring->base_addr.low_addr), dma_buf_len));
++	DHD_ERROR(("CtrlPost: From Host mem: RD: %d WR %d \r\n", ring->rd, ring->wr));
++	dhd_bus_cmn_readshared(dhd->bus, &rd, RING_RD_UPD, ring->idx);
++	dhd_bus_cmn_readshared(dhd->bus, &wr, RING_WR_UPD, ring->idx);
++	DHD_ERROR(("CtrlPost: From Shared Mem: RD: %d WR %d \r\n", rd, wr));
++	DHD_ERROR(("CtrlPost: seq num: %d \r\n", ring->seqnum % H2D_EPOCH_MODULO));
++
++	ring = &prot->d2hring_ctrl_cpln;
++	dma_buf_len = ring->max_items * ring->item_len;
++	DHD_ERROR(("CtrlCpl: Mem Info: BASE(VA) %p BASE(PA) %x:%x SIZE %d \r\n",
++		ring->dma_buf.va, ltoh32(ring->base_addr.high_addr),
++		ltoh32(ring->base_addr.low_addr), dma_buf_len));
++	DHD_ERROR(("CtrlCpl: From Host mem: RD: %d WR %d \r\n", ring->rd, ring->wr));
++	dhd_bus_cmn_readshared(dhd->bus, &rd, RING_RD_UPD, ring->idx);
++	dhd_bus_cmn_readshared(dhd->bus, &wr, RING_WR_UPD, ring->idx);
++	DHD_ERROR(("CtrlCpl: From Shared Mem: RD: %d WR %d \r\n", rd, wr));
++	DHD_ERROR(("CtrlCpl: Expected seq num: %d \r\n", ring->seqnum % H2D_EPOCH_MODULO));
++
++	ring = prot->h2dring_info_subn;
++	if (ring) {
++		dma_buf_len = ring->max_items * ring->item_len;
++		DHD_ERROR(("InfoSub: Mem Info: BASE(VA) %p BASE(PA) %x:%x SIZE %d \r\n",
++			ring->dma_buf.va, ltoh32(ring->base_addr.high_addr),
++			ltoh32(ring->base_addr.low_addr), dma_buf_len));
++		DHD_ERROR(("InfoSub: From Host mem: RD: %d WR %d \r\n", ring->rd, ring->wr));
++		dhd_bus_cmn_readshared(dhd->bus, &rd, RING_RD_UPD, ring->idx);
++		dhd_bus_cmn_readshared(dhd->bus, &wr, RING_WR_UPD, ring->idx);
++		DHD_ERROR(("InfoSub: From Shared Mem: RD: %d WR %d \r\n", rd, wr));
++		DHD_ERROR(("InfoSub: seq num: %d \r\n", ring->seqnum % H2D_EPOCH_MODULO));
++	}
++	ring = prot->d2hring_info_cpln;
++	if (ring) {
++		dma_buf_len = ring->max_items * ring->item_len;
++		DHD_ERROR(("InfoCpl: Mem Info: BASE(VA) %p BASE(PA) %x:%x SIZE %d \r\n",
++			ring->dma_buf.va, ltoh32(ring->base_addr.high_addr),
++			ltoh32(ring->base_addr.low_addr), dma_buf_len));
++		DHD_ERROR(("InfoCpl: From Host mem: RD: %d WR %d \r\n", ring->rd, ring->wr));
++		dhd_bus_cmn_readshared(dhd->bus, &rd, RING_RD_UPD, ring->idx);
++		dhd_bus_cmn_readshared(dhd->bus, &wr, RING_WR_UPD, ring->idx);
++		DHD_ERROR(("InfoCpl: From Shared Mem: RD: %d WR %d \r\n", rd, wr));
++		DHD_ERROR(("InfoCpl: Expected seq num: %d \r\n", ring->seqnum % H2D_EPOCH_MODULO));
++	}
++
++	DHD_ERROR(("%s: cur_ioctlresp_bufs_posted %d cur_event_bufs_posted %d\n",
++		__FUNCTION__, prot->cur_ioctlresp_bufs_posted, prot->cur_event_bufs_posted));
++
++	if (!dhd->bus->is_linkdown && dhd->bus->intstatus != (uint32)-1) {
++		DHD_ERROR(("\n ------- DUMPING INTR Status and Masks ------- \r\n"));
++		intstatus = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx,
++			PCIMailBoxInt, 0, 0);
++		intmask = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx,
++			PCIMailBoxMask, 0, 0);
++		mbintstatus = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx,
++			PCID2H_MailBox, 0, 0);
++		dhd_bus_cmn_readshared(dhd->bus, &d2h_mb_data, D2H_MB_DATA, 0);
++
++		DHD_ERROR(("intstatus=0x%x intmask=0x%x mbintstatus=0x%x\n",
++			intstatus, intmask, mbintstatus));
++		DHD_ERROR(("d2h_mb_data=0x%x def_intmask=0x%x \r\n", d2h_mb_data,
++			dhd->bus->def_intmask));
++
++		DHD_ERROR(("host pcie_irq enabled = %d\n", dhdpcie_irq_enabled(dhd->bus)));
++
++		DHD_ERROR(("\n ------- DUMPING PCIE Registers ------- \r\n"));
++		/* hwnbu-twiki.sj.broadcom.com/bin/view/Mwgroup/CurrentPcieGen2ProgramGuide */
++		DHD_ERROR(("Status Command(0x%x)=0x%x, BaseAddress0(0x%x)=0x%x\n",
++			PCIECFGREG_STATUS_CMD,
++			dhd_pcie_config_read(dhd->bus->osh, PCIECFGREG_STATUS_CMD, sizeof(uint32)),
++			PCIECFGREG_BASEADDR0,
++			dhd_pcie_config_read(dhd->bus->osh, PCIECFGREG_BASEADDR0, sizeof(uint32))));
++		DHD_ERROR(("LinkCtl(0x%x)=0x%x DeviceStatusControl2(0x%x)=0x%x "
++			"L1SSControl(0x%x)=0x%x\n", PCIECFGREG_LINK_STATUS_CTRL,
++			dhd_pcie_config_read(dhd->bus->osh, PCIECFGREG_LINK_STATUS_CTRL,
++			sizeof(uint32)), PCIECFGGEN_DEV_STATUS_CTRL2,
++			dhd_pcie_config_read(dhd->bus->osh, PCIECFGGEN_DEV_STATUS_CTRL2,
++			sizeof(uint32)), PCIECFGREG_PML1_SUB_CTRL1,
++			dhd_pcie_config_read(dhd->bus->osh, PCIECFGREG_PML1_SUB_CTRL1,
++			sizeof(uint32))));
++
++		/* hwnbu-twiki.sj.broadcom.com/twiki/pub/Mwgroup/
++		 * CurrentPcieGen2ProgramGuide/pcie_ep.htm
++		 */
++		DHD_ERROR(("ClkReq0(0x%x)=0x%x ClkReq1(0x%x)=0x%x ClkReq2(0x%x)=0x%x "
++			"ClkReq3(0x%x)=0x%x\n", PCIECFGREG_PHY_DBG_CLKREQ0,
++			dhd_pcie_corereg_read(dhd->bus->sih, PCIECFGREG_PHY_DBG_CLKREQ0),
++			PCIECFGREG_PHY_DBG_CLKREQ1,
++			dhd_pcie_corereg_read(dhd->bus->sih, PCIECFGREG_PHY_DBG_CLKREQ1),
++			PCIECFGREG_PHY_DBG_CLKREQ2,
++			dhd_pcie_corereg_read(dhd->bus->sih, PCIECFGREG_PHY_DBG_CLKREQ2),
++			PCIECFGREG_PHY_DBG_CLKREQ3,
++			dhd_pcie_corereg_read(dhd->bus->sih, PCIECFGREG_PHY_DBG_CLKREQ3)));
++
++#if defined(PCIE_RC_VENDOR_ID) && defined(PCIE_RC_DEVICE_ID)
++		DHD_ERROR(("Pcie RC Error Status Val=0x%x\n",
++			dhdpcie_rc_access_cap(dhd->bus, PCIE_EXTCAP_ID_ERR,
++			PCIE_EXTCAP_AER_UCERR_OFFSET, TRUE, FALSE, 0)));
++
++		DHD_ERROR(("RootPort PCIe linkcap=0x%08x\n",
++			dhd_debug_get_rc_linkcap(dhd->bus)));
++#endif
++
++		DHD_ERROR(("\n ------- DUMPING INTR enable/disable counters  ------- \r\n"));
++		DHD_ERROR(("resume_intr_enable_count=%lu dpc_intr_enable_count=%lu\n"
++			"isr_intr_disable_count=%lu suspend_intr_disable_count=%lu\n"
++			"dpc_return_busdown_count=%lu\n",
++			dhd->bus->resume_intr_enable_count, dhd->bus->dpc_intr_enable_count,
++			dhd->bus->isr_intr_disable_count, dhd->bus->suspend_intr_disable_count,
++			dhd->bus->dpc_return_busdown_count));
++
++	}
++	dhd_prot_debug_dma_info_print(dhd);
++#ifdef DHD_FW_COREDUMP
++	if (dhd->memdump_enabled) {
++#ifdef DHD_SSSR_DUMP
++		if (dhd->sssr_inited) {
++			dhdpcie_sssr_dump(dhd);
++		}
++#endif /* DHD_SSSR_DUMP */
++	}
++#endif /* DHD_FW_COREDUMP */
++	return 0;
++}
++
++int
++dhd_prot_ringupd_dump(dhd_pub_t *dhd, struct bcmstrbuf *b)
++{
++	uint32 *ptr;
++	uint32 value;
++	uint32 i;
++	uint32 max_h2d_queues = dhd_bus_max_h2d_queues(dhd->bus);
++
++	OSL_CACHE_INV((void *)dhd->prot->d2h_dma_indx_wr_buf.va,
++		dhd->prot->d2h_dma_indx_wr_buf.len);
++
++	ptr = (uint32 *)(dhd->prot->d2h_dma_indx_wr_buf.va);
++
++	bcm_bprintf(b, "\n max_tx_queues %d\n", max_h2d_queues);
++
++	bcm_bprintf(b, "\nRPTR block H2D common rings, 0x%04x\n", ptr);
++	value = ltoh32(*ptr);
++	bcm_bprintf(b, "\tH2D CTRL: value 0x%04x\n", value);
++	ptr++;
++	value = ltoh32(*ptr);
++	bcm_bprintf(b, "\tH2D RXPOST: value 0x%04x\n", value);
++
++	ptr++;
++	bcm_bprintf(b, "RPTR block Flow rings , 0x%04x\n", ptr);
++	for (i = BCMPCIE_H2D_COMMON_MSGRINGS; i < max_h2d_queues; i++) {
++		value = ltoh32(*ptr);
++		bcm_bprintf(b, "\tflowring ID %d: value 0x%04x\n", i, value);
++		ptr++;
++	}
++
++	OSL_CACHE_INV((void *)dhd->prot->h2d_dma_indx_rd_buf.va,
++		dhd->prot->h2d_dma_indx_rd_buf.len);
++
++	ptr = (uint32 *)(dhd->prot->h2d_dma_indx_rd_buf.va);
++
++	bcm_bprintf(b, "\nWPTR block D2H common rings, 0x%04x\n", ptr);
++	value = ltoh32(*ptr);
++	bcm_bprintf(b, "\tD2H CTRLCPLT: value 0x%04x\n", value);
++	ptr++;
++	value = ltoh32(*ptr);
++	bcm_bprintf(b, "\tD2H TXCPLT: value 0x%04x\n", value);
++	ptr++;
++	value = ltoh32(*ptr);
++	bcm_bprintf(b, "\tD2H RXCPLT: value 0x%04x\n", value);
++
++	return 0;
++}
++
++uint32
++dhd_prot_metadata_dbg_set(dhd_pub_t *dhd, bool val)
++{
++	dhd_prot_t *prot = dhd->prot;
++#if DHD_DBG_SHOW_METADATA
++	prot->metadata_dbg = val;
++#endif
++	return (uint32)prot->metadata_dbg;
++}
++
++uint32
++dhd_prot_metadata_dbg_get(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	return (uint32)prot->metadata_dbg;
++}
++
++uint32
++dhd_prot_metadatalen_set(dhd_pub_t *dhd, uint32 val, bool rx)
++{
++	dhd_prot_t *prot = dhd->prot;
++	if (rx)
++		prot->rx_metadata_offset = (uint16)val;
++	else
++		prot->tx_metadata_offset = (uint16)val;
++	return dhd_prot_metadatalen_get(dhd, rx);
++}
++
++uint32
++dhd_prot_metadatalen_get(dhd_pub_t *dhd, bool rx)
++{
++	dhd_prot_t *prot = dhd->prot;
++	if (rx)
++		return prot->rx_metadata_offset;
++	else
++		return prot->tx_metadata_offset;
++}
++
++/** optimization to write "n" tx items at a time to ring */
++uint32
++dhd_prot_txp_threshold(dhd_pub_t *dhd, bool set, uint32 val)
++{
++	dhd_prot_t *prot = dhd->prot;
++	if (set)
++		prot->txp_threshold = (uint16)val;
++	val = prot->txp_threshold;
++	return val;
++}
++
++#ifdef DHD_RX_CHAINING
++
++static INLINE void BCMFASTPATH
++dhd_rxchain_reset(rxchain_info_t *rxchain)
++{
++	rxchain->pkt_count = 0;
++}
++
++static void BCMFASTPATH
++dhd_rxchain_frame(dhd_pub_t *dhd, void *pkt, uint ifidx)
++{
++	uint8 *eh;
++	uint8 prio;
++	dhd_prot_t *prot = dhd->prot;
++	rxchain_info_t *rxchain = &prot->rxchain;
++
++	ASSERT(!PKTISCHAINED(pkt));
++	ASSERT(PKTCLINK(pkt) == NULL);
++	ASSERT(PKTCGETATTR(pkt) == 0);
++
++	eh = PKTDATA(dhd->osh, pkt);
++	prio = IP_TOS46(eh + ETHER_HDR_LEN) >> IPV4_TOS_PREC_SHIFT;
++
++	if (rxchain->pkt_count && !(PKT_CTF_CHAINABLE(dhd, ifidx, eh, prio, rxchain->h_sa,
++		rxchain->h_da, rxchain->h_prio))) {
++		/* Different flow - First release the existing chain */
++		dhd_rxchain_commit(dhd);
++	}
++
++	/* For routers, with HNDCTF, link the packets using PKTSETCLINK, */
++	/* so that the chain can be handed off to CTF bridge as is. */
++	if (rxchain->pkt_count == 0) {
++		/* First packet in chain */
++		rxchain->pkthead = rxchain->pkttail = pkt;
++
++		/* Keep a copy of ptr to ether_da, ether_sa and prio */
++		rxchain->h_da = ((struct ether_header *)eh)->ether_dhost;
++		rxchain->h_sa = ((struct ether_header *)eh)->ether_shost;
++		rxchain->h_prio = prio;
++		rxchain->ifidx = ifidx;
++		rxchain->pkt_count++;
++	} else {
++		/* Same flow - keep chaining */
++		PKTSETCLINK(rxchain->pkttail, pkt);
++		rxchain->pkttail = pkt;
++		rxchain->pkt_count++;
++	}
++
++	if ((dhd_rx_pkt_chainable(dhd, ifidx)) && (!ETHER_ISMULTI(rxchain->h_da)) &&
++		((((struct ether_header *)eh)->ether_type == HTON16(ETHER_TYPE_IP)) ||
++		(((struct ether_header *)eh)->ether_type == HTON16(ETHER_TYPE_IPV6)))) {
++		PKTSETCHAINED(dhd->osh, pkt);
++		PKTCINCRCNT(rxchain->pkthead);
++		PKTCADDLEN(rxchain->pkthead, PKTLEN(dhd->osh, pkt));
++	} else {
++		dhd_rxchain_commit(dhd);
++		return;
++	}
++
++	/* If we have hit the max chain length, dispatch the chain and reset */
++	if (rxchain->pkt_count >= DHD_PKT_CTF_MAX_CHAIN_LEN) {
++		dhd_rxchain_commit(dhd);
++	}
++}
++
++static void BCMFASTPATH
++dhd_rxchain_commit(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	rxchain_info_t *rxchain = &prot->rxchain;
++
++	if (rxchain->pkt_count == 0)
++		return;
++
++	/* Release the packets to dhd_linux */
++	dhd_bus_rx_frame(dhd->bus, rxchain->pkthead, rxchain->ifidx, rxchain->pkt_count);
++
++	/* Reset the chain */
++	dhd_rxchain_reset(rxchain);
++}
++
++#endif /* DHD_RX_CHAINING */
++
++
++#ifdef IDLE_TX_FLOW_MGMT
++int
++dhd_prot_flow_ring_resume(dhd_pub_t *dhd, flow_ring_node_t *flow_ring_node)
++{
++	tx_idle_flowring_resume_request_t *flow_resume_rqst;
++	msgbuf_ring_t *flow_ring;
++	dhd_prot_t *prot = dhd->prot;
++	unsigned long flags;
++	uint16 alloced = 0;
++	msgbuf_ring_t *ctrl_ring = &prot->h2dring_ctrl_subn;
++
++	/* Fetch a pre-initialized msgbuf_ring from the flowring pool */
++	flow_ring = dhd_prot_flowrings_pool_fetch(dhd, flow_ring_node->flowid);
++	if (flow_ring == NULL) {
++		DHD_ERROR(("%s: dhd_prot_flowrings_pool_fetch TX Flowid %d failed\n",
++			__FUNCTION__, flow_ring_node->flowid));
++		return BCME_NOMEM;
++	}
++#ifdef PCIE_INB_DW
++	if (dhd_prot_inc_hostactive_devwake_assert(dhd->bus) != BCME_OK)
++		return BCME_ERROR;
++#endif /* PCIE_INB_DW */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	/* Request for ctrl_ring buffer space */
++	flow_resume_rqst = (tx_idle_flowring_resume_request_t *)
++		dhd_prot_alloc_ring_space(dhd, ctrl_ring, 1, &alloced, FALSE);
++
++	if (flow_resume_rqst == NULL) {
++		dhd_prot_flowrings_pool_release(dhd, flow_ring_node->flowid, flow_ring);
++		DHD_ERROR(("%s: Flow resume Req flowid %d - failure ring space\n",
++			__FUNCTION__, flow_ring_node->flowid));
++		DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++		dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++		return BCME_NOMEM;
++	}
++
++	flow_ring_node->prot_info = (void *)flow_ring;
++
++	/* Common msg buf hdr */
++	flow_resume_rqst->msg.msg_type = MSG_TYPE_FLOW_RING_RESUME;
++	flow_resume_rqst->msg.if_id = (uint8)flow_ring_node->flow_info.ifindex;
++	flow_resume_rqst->msg.request_id = htol32(0); /* TBD */
++
++	flow_resume_rqst->msg.epoch = ctrl_ring->seqnum % H2D_EPOCH_MODULO;
++	ctrl_ring->seqnum++;
++
++	flow_resume_rqst->flow_ring_id = htol16((uint16)flow_ring_node->flowid);
++	DHD_ERROR(("%s Send Flow resume Req flow ID %d\n",
++		__FUNCTION__, flow_ring_node->flowid));
++
++	/* Update the flow_ring's WRITE index */
++	if (IDMA_ACTIVE(dhd) || dhd->dma_h2d_ring_upd_support) {
++		dhd_prot_dma_indx_set(dhd, flow_ring->wr,
++		                      H2D_DMA_INDX_WR_UPD, flow_ring->idx);
++	} else if (IFRM_ACTIVE(dhd) && (flow_ring->idx >= BCMPCIE_H2D_MSGRING_TXFLOW_IDX_START)) {
++		dhd_prot_dma_indx_set(dhd, flow_ring->wr,
++			H2D_IFRM_INDX_WR_UPD,
++			(flow_ring->idx - BCMPCIE_H2D_MSGRING_TXFLOW_IDX_START));
++	} else {
++		dhd_bus_cmn_writeshared(dhd->bus, &(flow_ring->wr),
++			sizeof(uint16), RING_WR_UPD, flow_ring->idx);
++	}
++
++	/* update control subn ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ctrl_ring, flow_resume_rqst, 1);
++
++	DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++
++	return BCME_OK;
++} /* dhd_prot_flow_ring_create */
++
++int
++dhd_prot_flow_ring_batch_suspend_request(dhd_pub_t *dhd, uint16 *ringid, uint16 count)
++{
++	tx_idle_flowring_suspend_request_t *flow_suspend_rqst;
++	dhd_prot_t *prot = dhd->prot;
++	unsigned long flags;
++	uint16 index;
++	uint16 alloced = 0;
++	msgbuf_ring_t *ring = &prot->h2dring_ctrl_subn;
++
++#ifdef PCIE_INB_DW
++	if (dhd_prot_inc_hostactive_devwake_assert(dhd->bus) != BCME_OK)
++		return BCME_ERROR;
++#endif /* PCIE_INB_DW */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	/* Request for ring buffer space */
++	flow_suspend_rqst = (tx_idle_flowring_suspend_request_t *)
++		dhd_prot_alloc_ring_space(dhd, ring, 1, &alloced, FALSE);
++
++	if (flow_suspend_rqst == NULL) {
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		DHD_ERROR(("%s: Flow suspend Req - failure ring space\n", __FUNCTION__));
++#ifdef PCIE_INB_DW
++		dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++		return BCME_NOMEM;
++	}
++
++	/* Common msg buf hdr */
++	flow_suspend_rqst->msg.msg_type = MSG_TYPE_FLOW_RING_SUSPEND;
++	/* flow_suspend_rqst->msg.if_id = (uint8)flow_ring_node->flow_info.ifindex; */
++	flow_suspend_rqst->msg.request_id = htol32(0); /* TBD */
++
++	flow_suspend_rqst->msg.epoch = ring->seqnum % H2D_EPOCH_MODULO;
++	ring->seqnum++;
++
++	/* Update flow id  info */
++	for (index = 0; index < count; index++)
++	{
++		flow_suspend_rqst->ring_id[index] = ringid[index];
++	}
++	flow_suspend_rqst->num = count;
++
++	DHD_ERROR(("%s sending batch suspend!! count is %d\n", __FUNCTION__, count));
++
++	/* update ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ring, flow_suspend_rqst, 1);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhd->bus);
++#endif
++
++	return BCME_OK;
++}
++#endif /* IDLE_TX_FLOW_MGMT */
++
++
++int dhd_prot_dump_extended_trap(dhd_pub_t *dhdp, struct bcmstrbuf *b, bool raw)
++{
++	uint32 i;
++	uint32 *ext_data;
++	hnd_ext_trap_hdr_t *hdr;
++	bcm_tlv_t *tlv;
++	trap_t *tr;
++	uint32 *stack;
++	hnd_ext_trap_bp_err_t *bpe;
++	uint32 raw_len;
++
++	ext_data = dhdp->extended_trap_data;
++
++	/* return if there is no extended trap data */
++	if (!ext_data || !(dhdp->dongle_trap_data & D2H_DEV_EXT_TRAP_DATA))
++	{
++		bcm_bprintf(b, "%d (0x%x)", dhdp->dongle_trap_data, dhdp->dongle_trap_data);
++		return BCME_OK;
++	}
++
++	bcm_bprintf(b, "Extended trap data\n");
++
++	/* First word is original trap_data */
++	bcm_bprintf(b, "trap_data = 0x%08x\n", *ext_data);
++	ext_data++;
++
++	/* Followed by the extended trap data header */
++	hdr = (hnd_ext_trap_hdr_t *)ext_data;
++	bcm_bprintf(b, "version: %d, len: %d\n", hdr->version, hdr->len);
++
++	if (raw)
++	{
++		raw_len = sizeof(hnd_ext_trap_hdr_t) + (hdr->len / 4) + (hdr->len % 4 ? 1 : 0);
++		for (i = 0; i < raw_len; i++)
++		{
++			bcm_bprintf(b, "0x%08x ", ext_data[i]);
++			if (i % 4 == 3)
++				bcm_bprintf(b, "\n");
++		}
++		return BCME_OK;
++	}
++
++	/* Extract the various supported TLVs from the extended trap data */
++	tlv = bcm_parse_tlvs(hdr->data, hdr->len, TAG_TRAP_SIGNATURE);
++	if (tlv)
++	{
++		bcm_bprintf(b, "\nTAG_TRAP_SIGNATURE len: %d\n", tlv->len);
++		tr = (trap_t *)tlv->data;
++
++		bcm_bprintf(b, "TRAP %x: pc %x, lr %x, sp %x, cpsr %x, spsr %x\n",
++		       tr->type, tr->pc, tr->r14, tr->r13, tr->cpsr, tr->spsr);
++		bcm_bprintf(b, "  r0 %x, r1 %x, r2 %x, r3 %x, r4 %x, r5 %x, r6 %x\n",
++		       tr->r0, tr->r1, tr->r2, tr->r3, tr->r4, tr->r5, tr->r6);
++		bcm_bprintf(b, "  r7 %x, r8 %x, r9 %x, r10 %x, r11 %x, r12 %x\n",
++		       tr->r7, tr->r8, tr->r9, tr->r10, tr->r11, tr->r12);
++	}
++
++	tlv = bcm_parse_tlvs(hdr->data, hdr->len, TAG_TRAP_STACK);
++	if (tlv)
++	{
++		bcm_bprintf(b, "\nTAG_TRAP_STACK len: %d\n", tlv->len);
++		stack = (uint32 *)tlv->data;
++		for (i = 0; i < (uint32)(tlv->len / 4); i++)
++		{
++			bcm_bprintf(b, "  0x%08x\n", *stack);
++			stack++;
++		}
++	}
++
++	tlv = bcm_parse_tlvs(hdr->data, hdr->len, TAG_TRAP_BACKPLANE);
++	if (tlv)
++	{
++		bcm_bprintf(b, "\nTAG_TRAP_BACKPLANE len: %d\n", tlv->len);
++		bpe = (hnd_ext_trap_bp_err_t *)tlv->data;
++		bcm_bprintf(b, " error: %x\n", bpe->error);
++		bcm_bprintf(b, " coreid: %x\n", bpe->coreid);
++		bcm_bprintf(b, " baseaddr: %x\n", bpe->baseaddr);
++		bcm_bprintf(b, " ioctrl: %x\n", bpe->ioctrl);
++		bcm_bprintf(b, " iostatus: %x\n", bpe->iostatus);
++		bcm_bprintf(b, " resetctrl: %x\n", bpe->resetctrl);
++		bcm_bprintf(b, " resetstatus: %x\n", bpe->resetstatus);
++		bcm_bprintf(b, " errlogctrl: %x\n", bpe->errlogctrl);
++		bcm_bprintf(b, " errlogdone: %x\n", bpe->errlogdone);
++		bcm_bprintf(b, " errlogstatus: %x\n", bpe->errlogstatus);
++		bcm_bprintf(b, " errlogaddrlo: %x\n", bpe->errlogaddrlo);
++		bcm_bprintf(b, " errlogaddrhi: %x\n", bpe->errlogaddrhi);
++		bcm_bprintf(b, " errlogid: %x\n", bpe->errlogid);
++		bcm_bprintf(b, " errloguser: %x\n", bpe->errloguser);
++		bcm_bprintf(b, " errlogflags: %x\n", bpe->errlogflags);
++	}
++
++	return BCME_OK;
++}
++
++
++#ifdef BCMPCIE
++int
++dhd_prot_send_host_timestamp(dhd_pub_t *dhdp, uchar *tlvs, uint16 tlv_len,
++	uint16 seqnum, uint16 xt_id)
++{
++	dhd_prot_t *prot = dhdp->prot;
++	host_timestamp_msg_t *ts_req;
++	unsigned long flags;
++	uint16 alloced = 0;
++	uchar *ts_tlv_buf;
++
++	if ((tlvs == NULL) || (tlv_len == 0)) {
++		DHD_ERROR(("%s: argument error tlv: %p, tlv_len %d\n",
++			__FUNCTION__, tlvs, tlv_len));
++		return -1;
++	}
++#ifdef PCIE_INB_DW
++	if (dhd_prot_inc_hostactive_devwake_assert(dhdp->bus) != BCME_OK)
++		return BCME_ERROR;
++#endif /* PCIE_INB_DW */
++
++	DHD_GENERAL_LOCK(dhdp, flags);
++
++	/* if Host TS req already pending go away */
++	if (prot->hostts_req_buf_inuse == TRUE) {
++		DHD_ERROR(("one host TS request already pending at device\n"));
++		DHD_GENERAL_UNLOCK(dhdp, flags);
++#ifdef PCIE_INB_DW
++		dhd_prot_dec_hostactive_ack_pending_dsreq(dhdp->bus);
++#endif
++		return -1;
++	}
++
++	/* Request for cbuf space */
++	ts_req = (host_timestamp_msg_t*)dhd_prot_alloc_ring_space(dhdp, &prot->h2dring_ctrl_subn,
++		DHD_FLOWRING_DEFAULT_NITEMS_POSTED_H2D,	&alloced, FALSE);
++	if (ts_req == NULL) {
++		DHD_ERROR(("couldn't allocate space on msgring to send host TS request\n"));
++		DHD_GENERAL_UNLOCK(dhdp, flags);
++#ifdef PCIE_INB_DW
++		dhd_prot_dec_hostactive_ack_pending_dsreq(dhdp->bus);
++#endif
++		return -1;
++	}
++
++	/* Common msg buf hdr */
++	ts_req->msg.msg_type = MSG_TYPE_HOSTTIMSTAMP;
++	ts_req->msg.if_id = 0;
++	ts_req->msg.flags =  prot->h2dring_ctrl_subn.current_phase;
++	ts_req->msg.request_id = DHD_H2D_HOSTTS_REQ_PKTID;
++
++	ts_req->msg.epoch = prot->h2dring_ctrl_subn.seqnum % H2D_EPOCH_MODULO;
++	prot->h2dring_ctrl_subn.seqnum++;
++
++	ts_req->xt_id = xt_id;
++	ts_req->seqnum = seqnum;
++	/* populate TS req buffer info */
++	ts_req->input_data_len = htol16(tlv_len);
++	ts_req->host_buf_addr.high = htol32(PHYSADDRHI(prot->hostts_req_buf.pa));
++	ts_req->host_buf_addr.low = htol32(PHYSADDRLO(prot->hostts_req_buf.pa));
++	/* copy ioct payload */
++	ts_tlv_buf = (void *) prot->hostts_req_buf.va;
++	prot->hostts_req_buf_inuse = TRUE;
++	memcpy(ts_tlv_buf, tlvs, tlv_len);
++
++	OSL_CACHE_FLUSH((void *) prot->hostts_req_buf.va, tlv_len);
++
++	if (ISALIGNED(ts_tlv_buf, DMA_ALIGN_LEN) == FALSE) {
++		DHD_ERROR(("host TS req buffer address unaligned !!!!! \n"));
++	}
++
++	DHD_CTL(("submitted Host TS request request_id %d, data_len %d, tx_id %d, seq %d\n",
++		ts_req->msg.request_id, ts_req->input_data_len,
++		ts_req->xt_id, ts_req->seqnum));
++
++
++	/* upd wrt ptr and raise interrupt */
++	dhd_prot_ring_write_complete(dhdp, &prot->h2dring_ctrl_subn, ts_req,
++		DHD_FLOWRING_DEFAULT_NITEMS_POSTED_H2D);
++	DHD_GENERAL_UNLOCK(dhdp, flags);
++#ifdef PCIE_INB_DW
++	dhd_prot_dec_hostactive_ack_pending_dsreq(dhdp->bus);
++#endif
++
++	return 0;
++} /* dhd_prot_send_host_timestamp */
++
++
++bool
++dhd_prot_data_path_tx_timestamp_logging(dhd_pub_t *dhd,  bool enable, bool set)
++{
++	if (set)
++		dhd->prot->tx_ts_log_enabled = enable;
++
++	return dhd->prot->tx_ts_log_enabled;
++}
++
++bool
++dhd_prot_data_path_rx_timestamp_logging(dhd_pub_t *dhd,  bool enable, bool set)
++{
++	if (set)
++		dhd->prot->rx_ts_log_enabled = enable;
++
++	return dhd->prot->rx_ts_log_enabled;
++}
++#endif /* BCMPCIE */
++
++void
++dhd_prot_dma_indx_free(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++
++	dhd_dma_buf_free(dhd, &prot->h2d_dma_indx_wr_buf);
++	dhd_dma_buf_free(dhd, &prot->d2h_dma_indx_rd_buf);
++}
++
++static void BCMFASTPATH
++dhd_prot_process_fw_timestamp(dhd_pub_t *dhd, void* buf)
++{
++#ifdef DHD_TIMESYNC
++	fw_timestamp_event_msg_t *resp;
++	uint32 pktid;
++	uint16 buflen, seqnum;
++	void * pkt;
++	unsigned long flags;
++
++	resp = (fw_timestamp_event_msg_t *)buf;
++	pktid = ltoh32(resp->msg.request_id);
++	buflen = ltoh16(resp->buf_len);
++	seqnum = ltoh16(resp->seqnum);
++
++#if defined(DHD_PKTID_AUDIT_RING)
++	DHD_PKTID_AUDIT(dhd, dhd->prot->pktid_ctrl_map, pktid,
++		DHD_DUPLICATE_FREE);
++#endif /* DHD_PKTID_AUDIT_RING */
++
++	DHD_INFO(("id 0x%04x, len %d, phase 0x%02x, seqnum %d\n",
++		pktid, buflen, resp->msg.flags, ltoh16(resp->seqnum)));
++
++	if (!dhd->prot->cur_ts_bufs_posted) {
++		DHD_ERROR(("tsbuf posted are zero, but there is a completion\n"));
++		return;
++	}
++
++	dhd->prot->cur_ts_bufs_posted--;
++	if (dhd->prot->max_tsbufpost > 0)
++		dhd_msgbuf_rxbuf_post_ts_bufs(dhd);
++
++	DHD_GENERAL_LOCK(dhd, flags);
++	pkt = dhd_prot_packet_get(dhd, pktid, PKTTYPE_TSBUF_RX, TRUE);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	if (!pkt) {
++		DHD_ERROR(("no ts buffer associated with pktid 0x%04x\n", pktid));
++		return;
++	}
++
++	PKTSETLEN(dhd->osh, pkt, buflen);
++	dhd_timesync_handle_fw_timestamp(dhd->ts, PKTDATA(dhd->osh, pkt), buflen, seqnum);
++#ifdef DHD_USE_STATIC_CTRLBUF
++	PKTFREE_STATIC(dhd->osh, pkt, TRUE);
++#else
++	PKTFREE(dhd->osh, pkt, TRUE);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++#else /* DHD_TIMESYNC */
++	DHD_ERROR(("Timesunc feature not compiled in but GOT FW TS message\n"));
++#endif /* DHD_TIMESYNC */
++
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_pcie.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_pcie.c
+new file mode 100644
+index 000000000..3d302287f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_pcie.c
+@@ -0,0 +1,8489 @@
++/*
++ * DHD Bus Module for PCIE
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_pcie.c 710862 2017-07-14 07:43:59Z $
++ */
++
++
++/* include files */
++#include <typedefs.h>
++#include <bcmutils.h>
++#include <bcmdevs.h>
++#include <siutils.h>
++#include <hndsoc.h>
++#include <hndpmu.h>
++#include <hnd_debug.h>
++#include <sbchipc.h>
++#include <hnd_armtrap.h>
++#if defined(DHD_DEBUG)
++#include <hnd_cons.h>
++#endif /* defined(DHD_DEBUG) */
++#include <dngl_stats.h>
++#include <pcie_core.h>
++#include <dhd.h>
++#include <dhd_bus.h>
++#include <dhd_flowring.h>
++#include <dhd_proto.h>
++#include <dhd_dbg.h>
++#include <dhd_daemon.h>
++#include <dhdioctl.h>
++#include <sdiovar.h>
++#include <bcmmsgbuf.h>
++#include <pcicfg.h>
++#include <dhd_pcie.h>
++#include <bcmpcie.h>
++#include <bcmendian.h>
++#ifdef DHDTCPACK_SUPPRESS
++#include <dhd_ip.h>
++#endif /* DHDTCPACK_SUPPRESS */
++#include <bcmevent.h>
++#include <dhd_config.h>
++
++#ifdef DHD_TIMESYNC
++#include <dhd_timesync.h>
++#endif /* DHD_TIMESYNC */
++
++#if defined(BCMEMBEDIMAGE)
++#ifndef DHD_EFI
++#include BCMEMBEDIMAGE
++#else
++#include <rtecdc_4364.h>
++#endif /* !DHD_EFI */
++#endif /* BCMEMBEDIMAGE */
++
++#define MEMBLOCK	2048		/* Block size used for downloading of dongle image */
++#define MAX_WKLK_IDLE_CHECK	3	/* times wake_lock checked before deciding not to suspend */
++
++#define ARMCR4REG_BANKIDX	(0x40/sizeof(uint32))
++#define ARMCR4REG_BANKPDA	(0x4C/sizeof(uint32))
++/* Temporary war to fix precommit till sync issue between trunk & precommit branch is resolved */
++
++/* CTO Prevention Recovery */
++#define CTO_TO_CLEAR_WAIT_MS 1000
++#define CTO_TO_CLEAR_WAIT_MAX_CNT 10
++
++#if defined(SUPPORT_MULTIPLE_BOARD_REV)
++	extern unsigned int system_rev;
++#endif /* SUPPORT_MULTIPLE_BOARD_REV */
++
++int dhd_dongle_memsize;
++int dhd_dongle_ramsize;
++static int dhdpcie_checkdied(dhd_bus_t *bus, char *data, uint size);
++static int dhdpcie_bus_readconsole(dhd_bus_t *bus);
++#if defined(DHD_FW_COREDUMP)
++struct dhd_bus *g_dhd_bus = NULL;
++static int dhdpcie_mem_dump(dhd_bus_t *bus);
++#endif /* DHD_FW_COREDUMP */
++
++static int dhdpcie_bus_membytes(dhd_bus_t *bus, bool write, ulong address, uint8 *data, uint size);
++static int dhdpcie_bus_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
++	const char *name, void *params,
++	int plen, void *arg, int len, int val_size);
++static int dhdpcie_bus_lpback_req(struct  dhd_bus *bus, uint32 intval);
++static int dhdpcie_bus_dmaxfer_req(struct  dhd_bus *bus,
++	uint32 len, uint32 srcdelay, uint32 destdelay, uint32 d11_lpbk);
++static int dhdpcie_bus_download_state(dhd_bus_t *bus, bool enter);
++static int _dhdpcie_download_firmware(struct dhd_bus *bus);
++static int dhdpcie_download_firmware(dhd_bus_t *bus, osl_t *osh);
++static int dhdpcie_bus_write_vars(dhd_bus_t *bus);
++static bool dhdpcie_bus_process_mailbox_intr(dhd_bus_t *bus, uint32 intstatus);
++static bool dhdpci_bus_read_frames(dhd_bus_t *bus);
++static int dhdpcie_readshared(dhd_bus_t *bus);
++static void dhdpcie_init_shared_addr(dhd_bus_t *bus);
++static bool dhdpcie_dongle_attach(dhd_bus_t *bus);
++static void dhdpcie_bus_dongle_setmemsize(dhd_bus_t *bus, int mem_size);
++static void dhdpcie_bus_release_dongle(dhd_bus_t *bus, osl_t *osh,
++	bool dongle_isolation, bool reset_flag);
++static void dhdpcie_bus_release_malloc(dhd_bus_t *bus, osl_t *osh);
++static int dhdpcie_downloadvars(dhd_bus_t *bus, void *arg, int len);
++static uint8 dhdpcie_bus_rtcm8(dhd_bus_t *bus, ulong offset);
++static void dhdpcie_bus_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data);
++static void dhdpcie_bus_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data);
++static uint16 dhdpcie_bus_rtcm16(dhd_bus_t *bus, ulong offset);
++static void dhdpcie_bus_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data);
++static uint32 dhdpcie_bus_rtcm32(dhd_bus_t *bus, ulong offset);
++#ifdef DHD_SUPPORT_64BIT
++static void dhdpcie_bus_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data);
++static uint64 dhdpcie_bus_rtcm64(dhd_bus_t *bus, ulong offset);
++#endif /* DHD_SUPPORT_64BIT */
++static void dhdpcie_bus_cfg_set_bar0_win(dhd_bus_t *bus, uint32 data);
++static void dhdpcie_bus_reg_unmap(osl_t *osh, volatile char *addr, int size);
++static int dhdpcie_cc_nvmshadow(dhd_bus_t *bus, struct bcmstrbuf *b);
++static void dhdpcie_fw_trap(dhd_bus_t *bus);
++static void dhd_fillup_ring_sharedptr_info(dhd_bus_t *bus, ring_info_t *ring_info);
++extern void dhd_dpc_enable(dhd_pub_t *dhdp);
++extern void dhd_dpc_kill(dhd_pub_t *dhdp);
++
++#ifdef IDLE_TX_FLOW_MGMT
++static void dhd_bus_check_idle_scan(dhd_bus_t *bus);
++static void dhd_bus_idle_scan(dhd_bus_t *bus);
++#endif /* IDLE_TX_FLOW_MGMT */
++
++#ifdef BCMEMBEDIMAGE
++static int dhdpcie_download_code_array(dhd_bus_t *bus);
++#endif /* BCMEMBEDIMAGE */
++
++
++#ifdef EXYNOS_PCIE_DEBUG
++extern void exynos_pcie_register_dump(int ch_num);
++#endif /* EXYNOS_PCIE_DEBUG */
++
++#define     PCI_VENDOR_ID_BROADCOM          0x14e4
++
++#define DHD_DEFAULT_DOORBELL_TIMEOUT 200	/* ms */
++#if defined(PCIE_OOB) || defined(PCIE_INB_DW)
++static uint dhd_doorbell_timeout = DHD_DEFAULT_DOORBELL_TIMEOUT;
++#endif /* defined(PCIE_OOB) || defined(PCIE_INB_DW) */
++static bool dhdpcie_check_firmware_compatible(uint32 f_api_version, uint32 h_api_version);
++static void dhdpcie_cto_error_recovery(struct dhd_bus *bus);
++
++#ifdef BCM_ASLR_HEAP
++static void dhdpcie_wrt_rnd(struct dhd_bus *bus);
++#endif /* BCM_ASLR_HEAP */
++
++extern uint16 dhd_prot_get_h2d_max_txpost(dhd_pub_t *dhd);
++extern void dhd_prot_set_h2d_max_txpost(dhd_pub_t *dhd, uint16 max_txpost);
++
++/* IOVar table */
++enum {
++	IOV_INTR = 1,
++	IOV_MEMSIZE,
++	IOV_SET_DOWNLOAD_STATE,
++	IOV_DEVRESET,
++	IOV_VARS,
++	IOV_MSI_SIM,
++	IOV_PCIE_LPBK,
++	IOV_CC_NVMSHADOW,
++	IOV_RAMSIZE,
++	IOV_RAMSTART,
++	IOV_SLEEP_ALLOWED,
++	IOV_PCIE_DMAXFER,
++	IOV_PCIE_SUSPEND,
++	IOV_DONGLEISOLATION,
++	IOV_LTRSLEEPON_UNLOOAD,
++	IOV_METADATA_DBG,
++	IOV_RX_METADATALEN,
++	IOV_TX_METADATALEN,
++	IOV_TXP_THRESHOLD,
++	IOV_BUZZZ_DUMP,
++	IOV_DUMP_RINGUPD_BLOCK,
++	IOV_DMA_RINGINDICES,
++	IOV_FORCE_FW_TRAP,
++	IOV_DB1_FOR_MB,
++	IOV_FLOW_PRIO_MAP,
++#ifdef DHD_PCIE_RUNTIMEPM
++	IOV_IDLETIME,
++#endif /* DHD_PCIE_RUNTIMEPM */
++	IOV_RXBOUND,
++	IOV_TXBOUND,
++	IOV_HANGREPORT,
++	IOV_H2D_MAILBOXDATA,
++	IOV_INFORINGS,
++	IOV_H2D_PHASE,
++	IOV_H2D_ENABLE_TRAP_BADPHASE,
++	IOV_H2D_TXPOST_MAX_ITEM,
++	IOV_TRAPDATA,
++	IOV_TRAPDATA_RAW,
++	IOV_CTO_PREVENTION,
++#ifdef PCIE_OOB
++	IOV_OOB_BT_REG_ON,
++	IOV_OOB_ENABLE,
++#endif /* PCIE_OOB */
++	IOV_PCIE_WD_RESET,
++	IOV_CTO_THRESHOLD,
++#ifdef DHD_EFI
++	IOV_CONTROL_SIGNAL,
++#if defined(PCIE_OOB) || defined(PCIE_INB_DW)
++	IOV_DEEP_SLEEP,
++#endif /* PCIE_OOB || PCIE_INB_DW */
++#endif /* DHD_EFI */
++#ifdef DEVICE_TX_STUCK_DETECT
++	IOV_DEVICE_TX_STUCK_DETECT,
++#endif /* DEVICE_TX_STUCK_DETECT */
++	IOV_INB_DW_ENABLE,
++	IOV_IDMA_ENABLE,
++	IOV_IFRM_ENABLE,
++	IOV_CLEAR_RING,
++#ifdef DHD_EFI
++	IOV_WIFI_PROPERTIES,
++	IOV_OTP_DUMP
++#endif
++};
++
++
++const bcm_iovar_t dhdpcie_iovars[] = {
++	{"intr",	IOV_INTR,	0,	0, IOVT_BOOL,	0 },
++	{"memsize",	IOV_MEMSIZE,	0,	0, IOVT_UINT32,	0 },
++	{"dwnldstate",	IOV_SET_DOWNLOAD_STATE,	0,	0, IOVT_BOOL,	0 },
++	{"vars",	IOV_VARS,	0,	0, IOVT_BUFFER,	0 },
++	{"devreset",	IOV_DEVRESET,	0,	0, IOVT_BOOL,	0 },
++	{"pcie_device_trap", IOV_FORCE_FW_TRAP, 0,	0, 0,	0 },
++	{"pcie_lpbk",	IOV_PCIE_LPBK,	0,	0, IOVT_UINT32,	0 },
++	{"cc_nvmshadow", IOV_CC_NVMSHADOW, 0, 0, IOVT_BUFFER, 0 },
++	{"ramsize",	IOV_RAMSIZE,	0,	0, IOVT_UINT32,	0 },
++	{"ramstart",	IOV_RAMSTART,	0,	0, IOVT_UINT32,	0 },
++	{"pcie_dmaxfer",	IOV_PCIE_DMAXFER,	0,	0, IOVT_BUFFER,	3 * sizeof(int32) },
++	{"pcie_suspend", IOV_PCIE_SUSPEND,	0,	0, IOVT_UINT32,	0 },
++#ifdef PCIE_OOB
++	{"oob_bt_reg_on", IOV_OOB_BT_REG_ON,    0, 0,  IOVT_UINT32,    0 },
++	{"oob_enable",   IOV_OOB_ENABLE,    0, 0,  IOVT_UINT32,    0 },
++#endif /* PCIE_OOB */
++	{"sleep_allowed",	IOV_SLEEP_ALLOWED,	0,	0, IOVT_BOOL,	0 },
++	{"dngl_isolation", IOV_DONGLEISOLATION,	0,	0, IOVT_UINT32,	0 },
++	{"ltrsleep_on_unload", IOV_LTRSLEEPON_UNLOOAD,	0,	0, IOVT_UINT32,	0 },
++	{"dump_ringupdblk", IOV_DUMP_RINGUPD_BLOCK,	0,	0, IOVT_BUFFER,	0 },
++	{"dma_ring_indices", IOV_DMA_RINGINDICES,	0,	0, IOVT_UINT32,	0},
++	{"metadata_dbg", IOV_METADATA_DBG,	0,	0, IOVT_BOOL,	0 },
++	{"rx_metadata_len", IOV_RX_METADATALEN,	0,	0, IOVT_UINT32,	0 },
++	{"tx_metadata_len", IOV_TX_METADATALEN,	0,	0, IOVT_UINT32,	0 },
++	{"db1_for_mb", IOV_DB1_FOR_MB,	0,	0, IOVT_UINT32,	0 },
++	{"txp_thresh", IOV_TXP_THRESHOLD,	0,	0, IOVT_UINT32,	0 },
++	{"buzzz_dump", IOV_BUZZZ_DUMP,		0,	0, IOVT_UINT32,	0 },
++	{"flow_prio_map", IOV_FLOW_PRIO_MAP,	0,	0, IOVT_UINT32,	0 },
++#ifdef DHD_PCIE_RUNTIMEPM
++	{"idletime",    IOV_IDLETIME,   0, 0,      IOVT_INT32,     0 },
++#endif /* DHD_PCIE_RUNTIMEPM */
++	{"rxbound",     IOV_RXBOUND,    0, 0,      IOVT_UINT32,    0 },
++	{"txbound",     IOV_TXBOUND,    0, 0,      IOVT_UINT32,    0 },
++	{"fw_hang_report", IOV_HANGREPORT,	0,	0, IOVT_BOOL,	0 },
++	{"h2d_mb_data",     IOV_H2D_MAILBOXDATA,    0, 0,      IOVT_UINT32,    0 },
++	{"inforings",   IOV_INFORINGS,    0, 0,      IOVT_UINT32,    0 },
++	{"h2d_phase",   IOV_H2D_PHASE,    0, 0,      IOVT_UINT32,    0 },
++	{"force_trap_bad_h2d_phase", IOV_H2D_ENABLE_TRAP_BADPHASE,    0, 0,
++	IOVT_UINT32,    0 },
++	{"h2d_max_txpost",   IOV_H2D_TXPOST_MAX_ITEM,    0, 0,      IOVT_UINT32,    0 },
++	{"trap_data",	IOV_TRAPDATA,	0,	0,	IOVT_BUFFER,	0 },
++	{"trap_data_raw",	IOV_TRAPDATA_RAW,	0, 0,	IOVT_BUFFER,	0 },
++	{"cto_prevention",	IOV_CTO_PREVENTION,	0,	0, IOVT_UINT32,	0 },
++	{"pcie_wd_reset",	IOV_PCIE_WD_RESET,	0,	0, IOVT_BOOL,	0 },
++	{"cto_threshold",	IOV_CTO_THRESHOLD,	0,	0, IOVT_UINT32,	0 },
++#ifdef DHD_EFI
++	{"control_signal", IOV_CONTROL_SIGNAL,	0, 0, IOVT_UINT32, 0},
++#if defined(PCIE_OOB) || defined(PCIE_INB_DW)
++	{"deep_sleep", IOV_DEEP_SLEEP, 0, 0, IOVT_UINT32,    0},
++#endif /* PCIE_OOB || PCIE_INB_DW */
++#endif /* DHD_EFI */
++	{"inb_dw_enable",   IOV_INB_DW_ENABLE,    0, 0,  IOVT_UINT32,    0 },
++#ifdef DEVICE_TX_STUCK_DETECT
++	{"dev_tx_stuck_monitor", IOV_DEVICE_TX_STUCK_DETECT, 0, 0, IOVT_UINT32, 0 },
++#endif /* DEVICE_TX_STUCK_DETECT */
++	{"idma_enable",   IOV_IDMA_ENABLE,    0, 0,  IOVT_UINT32,    0 },
++	{"ifrm_enable",   IOV_IFRM_ENABLE,    0, 0,  IOVT_UINT32,    0 },
++	{"clear_ring",   IOV_CLEAR_RING,    0, 0,  IOVT_UINT32,    0 },
++#ifdef DHD_EFI
++	{"properties", IOV_WIFI_PROPERTIES,	0, 0, IOVT_BUFFER, 0},
++	{"otp_dump", IOV_OTP_DUMP,	0, 0, IOVT_BUFFER, 0},
++#endif
++	{NULL, 0, 0, 0, 0, 0 }
++};
++
++
++#define MAX_READ_TIMEOUT	5 * 1000 * 1000
++
++#ifndef DHD_RXBOUND
++#define DHD_RXBOUND		64
++#endif
++#ifndef DHD_TXBOUND
++#define DHD_TXBOUND		64
++#endif
++
++#define DHD_INFORING_BOUND	32
++
++uint dhd_rxbound = DHD_RXBOUND;
++uint dhd_txbound = DHD_TXBOUND;
++
++/**
++ * Register/Unregister functions are called by the main DHD entry point (eg module insertion) to
++ * link with the bus driver, in order to look for or await the device.
++ */
++int
++dhd_bus_register(void)
++{
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	return dhdpcie_bus_register();
++}
++
++void
++dhd_bus_unregister(void)
++{
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	dhdpcie_bus_unregister();
++	return;
++}
++
++
++/** returns a host virtual address */
++uint32 *
++dhdpcie_bus_reg_map(osl_t *osh, ulong addr, int size)
++{
++	return (uint32 *)REG_MAP(addr, size);
++}
++
++void
++dhdpcie_bus_reg_unmap(osl_t *osh, volatile char *addr, int size)
++{
++	REG_UNMAP(addr);
++	return;
++}
++
++/**
++ * 'regs' is the host virtual address that maps to the start of the PCIe BAR0 window. The first 4096
++ * bytes in this window are mapped to the backplane address in the PCIEBAR0Window register. The
++ * precondition is that the PCIEBAR0Window register 'points' at the PCIe core.
++ *
++ * 'tcm' is the *host* virtual address at which tcm is mapped.
++ */
++dhd_bus_t* dhdpcie_bus_attach(osl_t *osh,
++	volatile char *regs, volatile char *tcm, void *pci_dev)
++{
++	dhd_bus_t *bus;
++
++	DHD_TRACE(("%s: ENTER\n", __FUNCTION__));
++
++	do {
++		if (!(bus = MALLOCZ(osh, sizeof(dhd_bus_t)))) {
++			DHD_ERROR(("%s: MALLOC of dhd_bus_t failed\n", __FUNCTION__));
++			break;
++		}
++
++		bus->regs = regs;
++		bus->tcm = tcm;
++		bus->osh = osh;
++		/* Save pci_dev into dhd_bus, as it may be needed in dhd_attach */
++		bus->dev = (struct pci_dev *)pci_dev;
++
++
++		dll_init(&bus->flowring_active_list);
++#ifdef IDLE_TX_FLOW_MGMT
++		bus->active_list_last_process_ts = OSL_SYSUPTIME();
++#endif /* IDLE_TX_FLOW_MGMT */
++
++#ifdef DEVICE_TX_STUCK_DETECT
++		/* Enable the Device stuck detection feature by default */
++		bus->dev_tx_stuck_monitor = TRUE;
++		bus->device_tx_stuck_check = OSL_SYSUPTIME();
++#endif /* DEVICE_TX_STUCK_DETECT */
++
++		/* Attach pcie shared structure */
++		if (!(bus->pcie_sh = MALLOCZ(osh, sizeof(pciedev_shared_t)))) {
++			DHD_ERROR(("%s: MALLOC of bus->pcie_sh failed\n", __FUNCTION__));
++			break;
++		}
++
++		/* dhd_common_init(osh); */
++
++		if (dhdpcie_dongle_attach(bus)) {
++			DHD_ERROR(("%s: dhdpcie_probe_attach failed\n", __FUNCTION__));
++			break;
++		}
++
++		/* software resources */
++		if (!(bus->dhd = dhd_attach(osh, bus, PCMSGBUF_HDRLEN))) {
++			DHD_ERROR(("%s: dhd_attach failed\n", __FUNCTION__));
++
++			break;
++		}
++		bus->dhd->busstate = DHD_BUS_DOWN;
++		bus->db1_for_mb = TRUE;
++		bus->dhd->hang_report = TRUE;
++		bus->use_mailbox = FALSE;
++		bus->use_d0_inform = FALSE;
++#ifdef IDLE_TX_FLOW_MGMT
++		bus->enable_idle_flowring_mgmt = FALSE;
++#endif /* IDLE_TX_FLOW_MGMT */
++		bus->irq_registered = FALSE;
++
++		DHD_TRACE(("%s: EXIT SUCCESS\n",
++			__FUNCTION__));
++#ifdef DHD_FW_COREDUMP
++		g_dhd_bus = bus;
++#endif
++		return bus;
++	} while (0);
++
++	DHD_TRACE(("%s: EXIT FAILURE\n", __FUNCTION__));
++
++	if (bus && bus->pcie_sh) {
++		MFREE(osh, bus->pcie_sh, sizeof(pciedev_shared_t));
++	}
++
++	if (bus) {
++		MFREE(osh, bus, sizeof(dhd_bus_t));
++	}
++	return NULL;
++}
++
++uint
++dhd_bus_chip(struct dhd_bus *bus)
++{
++	ASSERT(bus->sih != NULL);
++	return bus->sih->chip;
++}
++
++uint
++dhd_bus_chiprev(struct dhd_bus *bus)
++{
++	ASSERT(bus);
++	ASSERT(bus->sih != NULL);
++	return bus->sih->chiprev;
++}
++
++void *
++dhd_bus_pub(struct dhd_bus *bus)
++{
++	return bus->dhd;
++}
++
++const void *
++dhd_bus_sih(struct dhd_bus *bus)
++{
++	return (const void *)bus->sih;
++}
++
++void *
++dhd_bus_txq(struct dhd_bus *bus)
++{
++	return &bus->txq;
++}
++
++/** Get Chip ID version */
++uint dhd_bus_chip_id(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	return  bus->sih->chip;
++}
++
++/** Get Chip Rev ID version */
++uint dhd_bus_chiprev_id(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	return bus->sih->chiprev;
++}
++
++/** Get Chip Pkg ID version */
++uint dhd_bus_chippkg_id(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	return bus->sih->chippkg;
++}
++
++/** Read and clear intstatus. This should be called with interrupts disabled or inside isr */
++uint32
++dhdpcie_bus_intstatus(dhd_bus_t *bus)
++{
++	uint32 intstatus = 0;
++#ifndef DHD_READ_INTSTATUS_IN_DPC
++	uint32 intmask = 0;
++#endif /* DHD_READ_INTSTATUS_IN_DPC */
++
++	if ((bus->dhd->busstate == DHD_BUS_SUSPEND || bus->d3_suspend_pending) &&
++		bus->wait_for_d3_ack) {
++#ifdef DHD_EFI
++		DHD_INFO(("%s: trying to clear intstatus during suspend (%d)"
++			" or suspend in progress %d\n",
++			__FUNCTION__, bus->dhd->busstate, bus->d3_suspend_pending));
++#else
++		DHD_ERROR(("%s: trying to clear intstatus during suspend (%d)"
++			" or suspend in progress %d\n",
++			__FUNCTION__, bus->dhd->busstate, bus->d3_suspend_pending));
++#endif /* !DHD_EFI */
++		return intstatus;
++	}
++	if ((bus->sih->buscorerev == 6) || (bus->sih->buscorerev == 4) ||
++		(bus->sih->buscorerev == 2)) {
++		intstatus = dhdpcie_bus_cfg_read_dword(bus, PCIIntstatus, 4);
++		dhdpcie_bus_cfg_write_dword(bus, PCIIntstatus, 4, intstatus);
++		intstatus &= I_MB;
++	} else {
++		/* this is a PCIE core register..not a config register... */
++		intstatus = si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxInt, 0, 0);
++
++#ifndef DHD_READ_INTSTATUS_IN_DPC
++		/* this is a PCIE core register..not a config register... */
++		intmask = si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxMask, 0, 0);
++
++		intstatus &= intmask;
++#endif /* DHD_READ_INTSTATUS_IN_DPC */
++		/* Is device removed. intstatus & intmask read 0xffffffff */
++		if (intstatus == (uint32)-1) {
++			DHD_ERROR(("%s: Device is removed or Link is down.\n", __FUNCTION__));
++#ifdef CUSTOMER_HW4_DEBUG
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++			bus->dhd->hang_reason = HANG_REASON_PCIE_LINK_DOWN;
++			dhd_os_send_hang_message(bus->dhd);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27) && OEM_ANDROID */
++#endif /* CUSTOMER_HW4_DEBUG */
++			return intstatus;
++		}
++
++
++		/*
++		 * The fourth argument to si_corereg is the "mask" fields of the register to update
++		 * and the fifth field is the "value" to update. Now if we are interested in only
++		 * few fields of the "mask" bit map, we should not be writing back what we read
++		 * By doing so, we might clear/ack interrupts that are not handled yet.
++		 */
++		si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxInt, bus->def_intmask,
++			intstatus);
++
++		intstatus &= bus->def_intmask;
++	}
++
++	return intstatus;
++}
++
++/**
++ * Name:  dhdpcie_bus_isr
++ * Parameters:
++ * 1: IN int irq   -- interrupt vector
++ * 2: IN void *arg      -- handle to private data structure
++ * Return value:
++ * Status (TRUE or FALSE)
++ *
++ * Description:
++ * Interrupt Service routine checks for the status register,
++ * disable interrupt and queue DPC if mail box interrupts are raised.
++ */
++int32
++dhdpcie_bus_isr(dhd_bus_t *bus)
++{
++	uint32 intstatus = 0;
++
++	do {
++		DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++		/* verify argument */
++		if (!bus) {
++			DHD_ERROR(("%s : bus is null pointer, exit \n", __FUNCTION__));
++			break;
++		}
++
++		if (bus->dhd->dongle_reset) {
++			break;
++		}
++
++		if (bus->dhd->busstate == DHD_BUS_DOWN) {
++			break;
++		}
++
++
++		if (PCIECTO_ENAB(bus->dhd)) {
++			/* read pci_intstatus */
++			intstatus = dhdpcie_bus_cfg_read_dword(bus, PCI_INT_STATUS, 4);
++
++			if (intstatus & PCI_CTO_INT_MASK) {
++				/* reset backplane and cto,
++				 *  then access through pcie is recovered.
++				 */
++				dhdpcie_cto_error_recovery(bus);
++				return TRUE;
++			}
++		}
++
++#ifndef DHD_READ_INTSTATUS_IN_DPC
++		intstatus = dhdpcie_bus_intstatus(bus);
++
++		/* Check if the interrupt is ours or not */
++		if (intstatus == 0) {
++			break;
++		}
++
++		/* save the intstatus */
++		/* read interrupt status register!! Status bits will be cleared in DPC !! */
++		bus->intstatus = intstatus;
++
++		/* return error for 0xFFFFFFFF */
++		if (intstatus == (uint32)-1) {
++			dhdpcie_disable_irq_nosync(bus);
++			bus->is_linkdown = TRUE;
++			return BCME_ERROR;
++		}
++
++		/*  Overall operation:
++		 *    - Mask further interrupts
++		 *    - Read/ack intstatus
++		 *    - Take action based on bits and state
++		 *    - Reenable interrupts (as per state)
++		 */
++
++		/* Count the interrupt call */
++		bus->intrcount++;
++#endif /* DHD_READ_INTSTATUS_IN_DPC */
++
++		bus->ipend = TRUE;
++
++		bus->isr_intr_disable_count++;
++		dhdpcie_bus_intr_disable(bus); /* Disable interrupt using IntMask!! */
++
++		bus->intdis = TRUE;
++
++#if defined(PCIE_ISR_THREAD)
++
++		DHD_TRACE(("Calling dhd_bus_dpc() from %s\n", __FUNCTION__));
++		DHD_OS_WAKE_LOCK(bus->dhd);
++		while (dhd_bus_dpc(bus));
++		DHD_OS_WAKE_UNLOCK(bus->dhd);
++#else
++		bus->dpc_sched = TRUE;
++		dhd_sched_dpc(bus->dhd);     /* queue DPC now!! */
++#endif /* defined(SDIO_ISR_THREAD) */
++
++		DHD_TRACE(("%s: Exit Success DPC Queued\n", __FUNCTION__));
++		return TRUE;
++
++	} while (0);
++
++	DHD_TRACE(("%s: Exit Failure\n", __FUNCTION__));
++	return FALSE;
++}
++
++int
++dhdpcie_set_pwr_state(dhd_bus_t *bus, uint state)
++{
++	uint32 cur_state = 0;
++	uint32 pm_csr = 0;
++	osl_t *osh = bus->osh;
++
++	pm_csr = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_PM_CSR, sizeof(uint32));
++	cur_state = pm_csr & PCIECFGREG_PM_CSR_STATE_MASK;
++
++	if (cur_state == state) {
++		DHD_ERROR(("%s: Already in state %u \n", __FUNCTION__, cur_state));
++		return BCME_OK;
++	}
++
++	if (state > PCIECFGREG_PM_CSR_STATE_D3_HOT)
++		return BCME_ERROR;
++
++	/* Validate the state transition
++	* if already in a lower power state, return error
++	*/
++	if (state != PCIECFGREG_PM_CSR_STATE_D0 &&
++			cur_state <= PCIECFGREG_PM_CSR_STATE_D3_COLD &&
++			cur_state > state) {
++		DHD_ERROR(("%s: Invalid power state transition !\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	pm_csr &= ~PCIECFGREG_PM_CSR_STATE_MASK;
++	pm_csr |= state;
++
++	OSL_PCI_WRITE_CONFIG(osh, PCIECFGREG_PM_CSR, sizeof(uint32), pm_csr);
++
++	/* need to wait for the specified mandatory pcie power transition delay time */
++	if (state == PCIECFGREG_PM_CSR_STATE_D3_HOT ||
++			cur_state == PCIECFGREG_PM_CSR_STATE_D3_HOT)
++			OSL_DELAY(DHDPCIE_PM_D3_DELAY);
++	else if (state == PCIECFGREG_PM_CSR_STATE_D2 ||
++			cur_state == PCIECFGREG_PM_CSR_STATE_D2)
++			OSL_DELAY(DHDPCIE_PM_D2_DELAY);
++
++	/* read back the power state and verify */
++	pm_csr = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_PM_CSR, sizeof(uint32));
++	cur_state = pm_csr & PCIECFGREG_PM_CSR_STATE_MASK;
++	if (cur_state != state) {
++		DHD_ERROR(("%s: power transition failed ! Current state is %u \n",
++				__FUNCTION__, cur_state));
++		return BCME_ERROR;
++	} else {
++		DHD_ERROR(("%s: power transition to %u success \n",
++				__FUNCTION__, cur_state));
++	}
++
++	return BCME_OK;
++
++}
++
++int
++dhdpcie_config_check(dhd_bus_t *bus)
++{
++	uint32 i, val;
++	int ret = BCME_ERROR;
++
++	for (i = 0; i < DHDPCIE_CONFIG_CHECK_RETRY_COUNT; i++) {
++		val = OSL_PCI_READ_CONFIG(bus->osh, PCI_CFG_VID, sizeof(uint32));
++		if ((val & 0xFFFF) == VENDOR_BROADCOM) {
++			ret = BCME_OK;
++			break;
++		}
++		OSL_DELAY(DHDPCIE_CONFIG_CHECK_DELAY_MS * 1000);
++	}
++
++	return ret;
++}
++
++int
++dhdpcie_config_restore(dhd_bus_t *bus,  bool restore_pmcsr)
++{
++	uint32 i;
++	osl_t *osh = bus->osh;
++
++	if (BCME_OK != dhdpcie_config_check(bus)) {
++		return BCME_ERROR;
++	}
++
++	for (i = PCI_CFG_REV >> 2; i < DHDPCIE_CONFIG_HDR_SIZE; i++) {
++		OSL_PCI_WRITE_CONFIG(osh, i << 2, sizeof(uint32), bus->saved_config.header[i]);
++	}
++	OSL_PCI_WRITE_CONFIG(osh, PCI_CFG_CMD, sizeof(uint32), bus->saved_config.header[1]);
++
++	if (restore_pmcsr)
++		OSL_PCI_WRITE_CONFIG(osh, PCIECFGREG_PM_CSR,
++				sizeof(uint32), bus->saved_config.pmcsr);
++
++	OSL_PCI_WRITE_CONFIG(osh, PCIECFGREG_MSI_CAP, sizeof(uint32), bus->saved_config.msi_cap);
++	OSL_PCI_WRITE_CONFIG(osh, PCIECFGREG_MSI_ADDR_L, sizeof(uint32),
++			bus->saved_config.msi_addr0);
++	OSL_PCI_WRITE_CONFIG(osh, PCIECFGREG_MSI_ADDR_H,
++			sizeof(uint32), bus->saved_config.msi_addr1);
++	OSL_PCI_WRITE_CONFIG(osh, PCIECFGREG_MSI_DATA,
++			sizeof(uint32), bus->saved_config.msi_data);
++
++	OSL_PCI_WRITE_CONFIG(osh, PCIECFGREG_DEV_STATUS_CTRL,
++			sizeof(uint32), bus->saved_config.exp_dev_ctrl_stat);
++	OSL_PCI_WRITE_CONFIG(osh, PCIECFGGEN_DEV_STATUS_CTRL2,
++			sizeof(uint32), bus->saved_config.exp_dev_ctrl_stat2);
++	OSL_PCI_WRITE_CONFIG(osh, PCIECFGREG_LINK_STATUS_CTRL,
++			sizeof(uint32), bus->saved_config.exp_link_ctrl_stat);
++	OSL_PCI_WRITE_CONFIG(osh, PCIECFGREG_LINK_STATUS_CTRL2,
++			sizeof(uint32), bus->saved_config.exp_link_ctrl_stat2);
++
++	OSL_PCI_WRITE_CONFIG(osh, PCIECFGREG_PML1_SUB_CTRL1,
++			sizeof(uint32), bus->saved_config.l1pm0);
++	OSL_PCI_WRITE_CONFIG(osh, PCIECFGREG_PML1_SUB_CTRL2,
++			sizeof(uint32), bus->saved_config.l1pm1);
++
++	OSL_PCI_WRITE_CONFIG(bus->osh, PCI_BAR0_WIN,
++			sizeof(uint32), bus->saved_config.bar0_win);
++	OSL_PCI_WRITE_CONFIG(bus->osh, PCI_BAR1_WIN,
++			sizeof(uint32), bus->saved_config.bar1_win);
++
++	return BCME_OK;
++}
++
++int
++dhdpcie_config_save(dhd_bus_t *bus)
++{
++	uint32 i;
++	osl_t *osh = bus->osh;
++
++	if (BCME_OK != dhdpcie_config_check(bus)) {
++		return BCME_ERROR;
++	}
++
++	for (i = 0; i < DHDPCIE_CONFIG_HDR_SIZE; i++) {
++		bus->saved_config.header[i] = OSL_PCI_READ_CONFIG(osh, i << 2, sizeof(uint32));
++	}
++
++	bus->saved_config.pmcsr = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_PM_CSR, sizeof(uint32));
++
++	bus->saved_config.msi_cap = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_MSI_CAP,
++			sizeof(uint32));
++	bus->saved_config.msi_addr0 = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_MSI_ADDR_L,
++			sizeof(uint32));
++	bus->saved_config.msi_addr1 = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_MSI_ADDR_H,
++			sizeof(uint32));
++	bus->saved_config.msi_data = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_MSI_DATA,
++			sizeof(uint32));
++
++	bus->saved_config.exp_dev_ctrl_stat = OSL_PCI_READ_CONFIG(osh,
++			PCIECFGREG_DEV_STATUS_CTRL, sizeof(uint32));
++	bus->saved_config.exp_dev_ctrl_stat2 = OSL_PCI_READ_CONFIG(osh,
++			PCIECFGGEN_DEV_STATUS_CTRL2, sizeof(uint32));
++	bus->saved_config.exp_link_ctrl_stat = OSL_PCI_READ_CONFIG(osh,
++			PCIECFGREG_LINK_STATUS_CTRL, sizeof(uint32));
++	bus->saved_config.exp_link_ctrl_stat2 = OSL_PCI_READ_CONFIG(osh,
++			PCIECFGREG_LINK_STATUS_CTRL2, sizeof(uint32));
++
++	bus->saved_config.l1pm0 = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_PML1_SUB_CTRL1,
++			sizeof(uint32));
++	bus->saved_config.l1pm1 = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_PML1_SUB_CTRL2,
++			sizeof(uint32));
++
++	bus->saved_config.bar0_win = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN,
++			sizeof(uint32));
++	bus->saved_config.bar1_win = OSL_PCI_READ_CONFIG(osh, PCI_BAR1_WIN,
++			sizeof(uint32));
++	return BCME_OK;
++}
++
++#ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
++dhd_pub_t *link_recovery = NULL;
++#endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
++static bool
++dhdpcie_dongle_attach(dhd_bus_t *bus)
++{
++
++	osl_t *osh = bus->osh;
++	volatile void *regsva = (volatile void*)bus->regs;
++	uint16 devid = bus->cl_devid;
++	uint32 val;
++	sbpcieregs_t *sbpcieregs;
++
++	DHD_TRACE(("%s: ENTER\n", __FUNCTION__));
++
++#ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
++	link_recovery = bus->dhd;
++#endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
++
++	bus->alp_only = TRUE;
++	bus->sih = NULL;
++
++	/* Set bar0 window to si_enum_base */
++	dhdpcie_bus_cfg_set_bar0_win(bus, SI_ENUM_BASE);
++
++	/* Checking PCIe bus status with reading configuration space */
++	val = OSL_PCI_READ_CONFIG(osh, PCI_CFG_VID, sizeof(uint32));
++	if ((val & 0xFFFF) != VENDOR_BROADCOM) {
++		DHD_ERROR(("%s : failed to read PCI configuration space!\n", __FUNCTION__));
++		goto fail;
++	}
++
++	/*
++	 * Checking PCI_SPROM_CONTROL register for preventing invalid address access
++	 * due to switch address space from PCI_BUS to SI_BUS.
++	 */
++	val = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
++	if (val == 0xffffffff) {
++		DHD_ERROR(("%s : failed to read SPROM control register\n", __FUNCTION__));
++		goto fail;
++	}
++
++#ifdef DHD_EFI
++	/* Save good copy of PCIe config space */
++	if (BCME_OK != dhdpcie_config_save(bus)) {
++		DHD_ERROR(("%s : failed to save PCI configuration space!\n", __FUNCTION__));
++		goto fail;
++	}
++#endif /* DHD_EFI */
++
++	/* si_attach() will provide an SI handle and scan the backplane */
++	if (!(bus->sih = si_attach((uint)devid, osh, regsva, PCI_BUS, bus,
++	                           &bus->vars, &bus->varsz))) {
++		DHD_ERROR(("%s: si_attach failed!\n", __FUNCTION__));
++		goto fail;
++	}
++
++	/* Olympic EFI requirement - stop driver load if FW is already running
++	*  need to do this here before pcie_watchdog_reset, because
++	*  pcie_watchdog_reset will put the ARM back into halt state
++	*/
++	if (!dhdpcie_is_arm_halted(bus)) {
++		DHD_ERROR(("%s: ARM is not halted,FW is already running! Abort.\n",
++				__FUNCTION__));
++		goto fail;
++	}
++
++	/* Enable CLKREQ# */
++	dhdpcie_clkreq(bus->osh, 1, 1);
++
++#ifndef DONGLE_ENABLE_ISOLATION
++	/*
++	 * Issue CC watchdog to reset all the cores on the chip - similar to rmmod dhd
++	 * This is required to avoid spurious interrupts to the Host and bring back
++	 * dongle to a sane state (on host soft-reboot / watchdog-reboot).
++	 */
++	pcie_watchdog_reset(bus->osh, bus->sih, (sbpcieregs_t *) bus->regs);
++#endif /* !DONGLE_ENABLE_ISOLATION */
++
++#ifdef DHD_EFI
++	dhdpcie_dongle_pwr_toggle(bus);
++#endif
++
++	si_setcore(bus->sih, PCIE2_CORE_ID, 0);
++	sbpcieregs = (sbpcieregs_t*)(bus->regs);
++
++	/* WAR where the BAR1 window may not be sized properly */
++	W_REG(osh, &sbpcieregs->configaddr, 0x4e0);
++	val = R_REG(osh, &sbpcieregs->configdata);
++	W_REG(osh, &sbpcieregs->configdata, val);
++
++	/* Get info on the ARM and SOCRAM cores... */
++	/* Should really be qualified by device id */
++	if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
++	    (si_setcore(bus->sih, ARMCM3_CORE_ID, 0)) ||
++	    (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) ||
++	    (si_setcore(bus->sih, ARMCA7_CORE_ID, 0))) {
++		bus->armrev = si_corerev(bus->sih);
++	} else {
++		DHD_ERROR(("%s: failed to find ARM core!\n", __FUNCTION__));
++		goto fail;
++	}
++
++	if (si_setcore(bus->sih, SYSMEM_CORE_ID, 0)) {
++		/* Only set dongle RAMSIZE to default value when ramsize is not adjusted */
++		if (!bus->ramsize_adjusted) {
++			if (!(bus->orig_ramsize = si_sysmem_size(bus->sih))) {
++				DHD_ERROR(("%s: failed to find SYSMEM memory!\n", __FUNCTION__));
++				goto fail;
++			}
++			/* also populate base address */
++			bus->dongle_ram_base = CA7_4365_RAM_BASE;
++			/* Default reserve 1.75MB for CA7 */
++			bus->orig_ramsize = 0x1c0000;
++		}
++	} else if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
++		if (!(bus->orig_ramsize = si_socram_size(bus->sih))) {
++			DHD_ERROR(("%s: failed to find SOCRAM memory!\n", __FUNCTION__));
++			goto fail;
++		}
++	} else {
++		/* cr4 has a different way to find the RAM size from TCM's */
++		if (!(bus->orig_ramsize = si_tcm_size(bus->sih))) {
++			DHD_ERROR(("%s: failed to find CR4-TCM memory!\n", __FUNCTION__));
++			goto fail;
++		}
++		/* also populate base address */
++		switch ((uint16)bus->sih->chip) {
++		case BCM4339_CHIP_ID:
++		case BCM4335_CHIP_ID:
++			bus->dongle_ram_base = CR4_4335_RAM_BASE;
++			break;
++		case BCM4358_CHIP_ID:
++		case BCM4354_CHIP_ID:
++		case BCM43567_CHIP_ID:
++		case BCM43569_CHIP_ID:
++		case BCM4350_CHIP_ID:
++		case BCM43570_CHIP_ID:
++			bus->dongle_ram_base = CR4_4350_RAM_BASE;
++			break;
++		case BCM4360_CHIP_ID:
++			bus->dongle_ram_base = CR4_4360_RAM_BASE;
++			break;
++
++		case BCM4364_CHIP_ID:
++			bus->dongle_ram_base = CR4_4364_RAM_BASE;
++			break;
++
++		CASE_BCM4345_CHIP:
++			bus->dongle_ram_base = (bus->sih->chiprev < 6)  /* changed at 4345C0 */
++				? CR4_4345_LT_C0_RAM_BASE : CR4_4345_GE_C0_RAM_BASE;
++			break;
++		CASE_BCM43602_CHIP:
++			bus->dongle_ram_base = CR4_43602_RAM_BASE;
++			break;
++		case BCM4349_CHIP_GRPID:
++			/* RAM based changed from 4349c0(revid=9) onwards */
++			bus->dongle_ram_base = ((bus->sih->chiprev < 9) ?
++				CR4_4349_RAM_BASE : CR4_4349_RAM_BASE_FROM_REV_9);
++			break;
++		case BCM4347_CHIP_GRPID:
++			bus->dongle_ram_base = CR4_4347_RAM_BASE;
++			break;
++		case BCM4362_CHIP_ID:
++			bus->dongle_ram_base = CR4_4362_RAM_BASE;
++			break;
++		default:
++			bus->dongle_ram_base = 0;
++			DHD_ERROR(("%s: WARNING: Using default ram base at 0x%x\n",
++			           __FUNCTION__, bus->dongle_ram_base));
++		}
++	}
++	bus->ramsize = bus->orig_ramsize;
++	if (dhd_dongle_memsize)
++		dhdpcie_bus_dongle_setmemsize(bus, dhd_dongle_memsize);
++
++	DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d) at 0x%x\n",
++	           bus->ramsize, bus->orig_ramsize, bus->dongle_ram_base));
++
++	bus->srmemsize = si_socram_srmem_size(bus->sih);
++
++
++	bus->def_intmask = PCIE_MB_D2H_MB_MASK | PCIE_MB_TOPCIE_FN0_0 | PCIE_MB_TOPCIE_FN0_1;
++
++	/* Set the poll and/or interrupt flags */
++	bus->intr = (bool)dhd_intr;
++	if ((bus->poll = (bool)dhd_poll))
++		bus->pollrate = 1;
++
++	bus->wait_for_d3_ack = 1;
++#ifdef PCIE_OOB
++	dhdpcie_oob_init(bus);
++#endif /* PCIE_OOB */
++#ifdef PCIE_INB_DW
++	bus->inb_enabled = TRUE;
++#endif /* PCIE_INB_DW */
++	bus->dongle_in_ds = FALSE;
++	bus->idma_enabled = TRUE;
++	bus->ifrm_enabled = TRUE;
++#if defined(PCIE_OOB) || defined(PCIE_INB_DW)
++	bus->ds_enabled = TRUE;
++#endif
++	DHD_TRACE(("%s: EXIT: SUCCESS\n", __FUNCTION__));
++	return 0;
++
++fail:
++	if (bus->sih != NULL) {
++		si_detach(bus->sih);
++		bus->sih = NULL;
++	}
++	DHD_TRACE(("%s: EXIT: FAILURE\n", __FUNCTION__));
++	return -1;
++}
++
++int
++dhpcie_bus_unmask_interrupt(dhd_bus_t *bus)
++{
++	dhdpcie_bus_cfg_write_dword(bus, PCIIntmask, 4, I_MB);
++	return 0;
++}
++int
++dhpcie_bus_mask_interrupt(dhd_bus_t *bus)
++{
++	dhdpcie_bus_cfg_write_dword(bus, PCIIntmask, 4, 0x0);
++	return 0;
++}
++
++void
++dhdpcie_bus_intr_enable(dhd_bus_t *bus)
++{
++	DHD_TRACE(("%s Enter\n", __FUNCTION__));
++	if (bus && bus->sih && !bus->is_linkdown) {
++		if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) ||
++			(bus->sih->buscorerev == 4)) {
++			dhpcie_bus_unmask_interrupt(bus);
++		} else {
++			/* Skip after recieving D3 ACK */
++			if ((bus->dhd->busstate == DHD_BUS_SUSPEND || bus->d3_suspend_pending) &&
++				bus->wait_for_d3_ack) {
++				return;
++			}
++			si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxMask,
++				bus->def_intmask, bus->def_intmask);
++		}
++	}
++	DHD_TRACE(("%s Exit\n", __FUNCTION__));
++}
++
++void
++dhdpcie_bus_intr_disable(dhd_bus_t *bus)
++{
++	DHD_TRACE(("%s Enter\n", __FUNCTION__));
++	if (bus && bus->sih && !bus->is_linkdown) {
++		if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) ||
++			(bus->sih->buscorerev == 4)) {
++			dhpcie_bus_mask_interrupt(bus);
++		} else {
++			/* Skip after recieving D3 ACK */
++			if ((bus->dhd->busstate == DHD_BUS_SUSPEND || bus->d3_suspend_pending) &&
++				bus->wait_for_d3_ack) {
++				return;
++			}
++			si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxMask,
++				bus->def_intmask, 0);
++		}
++	}
++	DHD_TRACE(("%s Exit\n", __FUNCTION__));
++}
++
++/*
++ *  dhdpcie_advertise_bus_cleanup advertises that clean up is under progress
++ * to other bus user contexts like Tx, Rx, IOVAR, WD etc and it waits for other contexts
++ * to gracefully exit. All the bus usage contexts before marking busstate as busy, will check for
++ * whether the busstate is DHD_BUS_DOWN or DHD_BUS_DOWN_IN_PROGRESS, if so
++ * they will exit from there itself without marking dhd_bus_busy_state as BUSY.
++ */
++static void
++dhdpcie_advertise_bus_cleanup(dhd_pub_t	 *dhdp)
++{
++	unsigned long flags;
++	int timeleft;
++
++	DHD_GENERAL_LOCK(dhdp, flags);
++	dhdp->busstate = DHD_BUS_DOWN_IN_PROGRESS;
++	DHD_GENERAL_UNLOCK(dhdp, flags);
++
++	timeleft = dhd_os_busbusy_wait_negation(dhdp, &dhdp->dhd_bus_busy_state);
++	if ((timeleft == 0) || (timeleft == 1)) {
++		DHD_ERROR(("%s : Timeout due to dhd_bus_busy_state=0x%x\n",
++				__FUNCTION__, dhdp->dhd_bus_busy_state));
++		ASSERT(0);
++	}
++
++	return;
++}
++
++static void
++dhdpcie_advertise_bus_remove(dhd_pub_t	 *dhdp)
++{
++	unsigned long flags;
++	int timeleft;
++
++	DHD_GENERAL_LOCK(dhdp, flags);
++	dhdp->busstate = DHD_BUS_REMOVE;
++	DHD_GENERAL_UNLOCK(dhdp, flags);
++
++	timeleft = dhd_os_busbusy_wait_negation(dhdp, &dhdp->dhd_bus_busy_state);
++	if ((timeleft == 0) || (timeleft == 1)) {
++		DHD_ERROR(("%s : Timeout due to dhd_bus_busy_state=0x%x\n",
++				__FUNCTION__, dhdp->dhd_bus_busy_state));
++		ASSERT(0);
++	}
++
++	return;
++}
++
++
++static void
++dhdpcie_bus_remove_prep(dhd_bus_t *bus)
++{
++	unsigned long flags;
++	DHD_TRACE(("%s Enter\n", __FUNCTION__));
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	bus->dhd->busstate = DHD_BUS_DOWN;
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++#ifdef PCIE_INB_DW
++	/* De-Initialize the lock to serialize Device Wake Inband activities */
++	if (bus->inb_lock) {
++		dhd_os_spin_lock_deinit(bus->dhd->osh, bus->inb_lock);
++		bus->inb_lock = NULL;
++	}
++#endif
++
++
++	dhd_os_sdlock(bus->dhd);
++
++	if (bus->sih && !bus->dhd->dongle_isolation) {
++		/* Has insmod fails after rmmod issue in Brix Android */
++		/* if the pcie link is down, watchdog reset should not be done, as it may hang */
++		if (!bus->is_linkdown)
++			pcie_watchdog_reset(bus->osh, bus->sih, (sbpcieregs_t *) bus->regs);
++		else
++			DHD_ERROR(("%s: skipping watchdog reset, due to pcie link down ! \n",
++					__FUNCTION__));
++
++		bus->dhd->is_pcie_watchdog_reset = TRUE;
++	}
++
++	dhd_os_sdunlock(bus->dhd);
++
++	DHD_TRACE(("%s Exit\n", __FUNCTION__));
++}
++
++/** Detach and free everything */
++void
++dhdpcie_bus_release(dhd_bus_t *bus)
++{
++	bool dongle_isolation = FALSE;
++	osl_t *osh = NULL;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus) {
++
++		osh = bus->osh;
++		ASSERT(osh);
++
++		if (bus->dhd) {
++			dhdpcie_advertise_bus_remove(bus->dhd);
++			dongle_isolation = bus->dhd->dongle_isolation;
++			bus->dhd->is_pcie_watchdog_reset = FALSE;
++			dhdpcie_bus_remove_prep(bus);
++
++			if (bus->intr) {
++				dhdpcie_bus_intr_disable(bus);
++				dhdpcie_free_irq(bus);
++			}
++			dhdpcie_bus_release_dongle(bus, osh, dongle_isolation, TRUE);
++			dhd_detach(bus->dhd);
++			dhd_free(bus->dhd);
++			bus->dhd = NULL;
++		}
++
++		/* unmap the regs and tcm here!! */
++		if (bus->regs) {
++			dhdpcie_bus_reg_unmap(osh, bus->regs, DONGLE_REG_MAP_SIZE);
++			bus->regs = NULL;
++		}
++		if (bus->tcm) {
++			dhdpcie_bus_reg_unmap(osh, bus->tcm, DONGLE_TCM_MAP_SIZE);
++			bus->tcm = NULL;
++		}
++
++		dhdpcie_bus_release_malloc(bus, osh);
++		/* Detach pcie shared structure */
++		if (bus->pcie_sh) {
++			MFREE(osh, bus->pcie_sh, sizeof(pciedev_shared_t));
++			bus->pcie_sh = NULL;
++		}
++
++		if (bus->console.buf != NULL) {
++			MFREE(osh, bus->console.buf, bus->console.bufsize);
++		}
++
++
++		/* Finally free bus info */
++		MFREE(osh, bus, sizeof(dhd_bus_t));
++
++	}
++
++	DHD_TRACE(("%s: Exit\n", __FUNCTION__));
++} /* dhdpcie_bus_release */
++
++
++void
++dhdpcie_bus_release_dongle(dhd_bus_t *bus, osl_t *osh, bool dongle_isolation, bool reset_flag)
++{
++	DHD_TRACE(("%s: Enter bus->dhd %p bus->dhd->dongle_reset %d \n", __FUNCTION__,
++		bus->dhd, bus->dhd->dongle_reset));
++
++	if ((bus->dhd && bus->dhd->dongle_reset) && reset_flag) {
++		DHD_TRACE(("%s Exit\n", __FUNCTION__));
++		return;
++	}
++
++	if (bus->sih) {
++
++		if (!dongle_isolation &&
++		(bus->dhd && !bus->dhd->is_pcie_watchdog_reset))
++			pcie_watchdog_reset(bus->osh, bus->sih,
++				(sbpcieregs_t *) bus->regs);
++#ifdef DHD_EFI
++		dhdpcie_dongle_pwr_toggle(bus);
++#endif
++		if (bus->ltrsleep_on_unload) {
++			si_corereg(bus->sih, bus->sih->buscoreidx,
++				OFFSETOF(sbpcieregs_t, u.pcie2.ltr_state), ~0, 0);
++		}
++
++		if (bus->sih->buscorerev == 13)
++			 pcie_serdes_iddqdisable(bus->osh, bus->sih,
++			                         (sbpcieregs_t *) bus->regs);
++
++		/* Disable CLKREQ# */
++		dhdpcie_clkreq(bus->osh, 1, 0);
++
++		if (bus->sih != NULL) {
++			si_detach(bus->sih);
++			bus->sih = NULL;
++		}
++		if (bus->vars && bus->varsz)
++			MFREE(osh, bus->vars, bus->varsz);
++		bus->vars = NULL;
++	}
++
++	DHD_TRACE(("%s Exit\n", __FUNCTION__));
++}
++
++uint32
++dhdpcie_bus_cfg_read_dword(dhd_bus_t *bus, uint32 addr, uint32 size)
++{
++	uint32 data = OSL_PCI_READ_CONFIG(bus->osh, addr, size);
++	return data;
++}
++
++/** 32 bit config write */
++void
++dhdpcie_bus_cfg_write_dword(dhd_bus_t *bus, uint32 addr, uint32 size, uint32 data)
++{
++	OSL_PCI_WRITE_CONFIG(bus->osh, addr, size, data);
++}
++
++void
++dhdpcie_bus_cfg_set_bar0_win(dhd_bus_t *bus, uint32 data)
++{
++	OSL_PCI_WRITE_CONFIG(bus->osh, PCI_BAR0_WIN, 4, data);
++}
++
++void
++dhdpcie_bus_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
++{
++	int32 min_size =  DONGLE_MIN_MEMSIZE;
++	/* Restrict the memsize to user specified limit */
++	DHD_ERROR(("user: Restrict the dongle ram size to %d, min accepted %d\n",
++		dhd_dongle_memsize, min_size));
++	if ((dhd_dongle_memsize > min_size) &&
++		(dhd_dongle_memsize < (int32)bus->orig_ramsize))
++		bus->ramsize = dhd_dongle_memsize;
++}
++
++void
++dhdpcie_bus_release_malloc(dhd_bus_t *bus, osl_t *osh)
++{
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus->dhd && bus->dhd->dongle_reset)
++		return;
++
++	if (bus->vars && bus->varsz) {
++		MFREE(osh, bus->vars, bus->varsz);
++		bus->vars = NULL;
++	}
++
++	DHD_TRACE(("%s: Exit\n", __FUNCTION__));
++	return;
++
++}
++
++/** Stop bus module: clear pending frames, disable data flow */
++void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
++{
++	uint32 status;
++	unsigned long flags;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (!bus->dhd)
++		return;
++
++	if (bus->dhd->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s: already down by net_dev_reset\n", __FUNCTION__));
++		goto done;
++	}
++
++	DHD_DISABLE_RUNTIME_PM(bus->dhd);
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	bus->dhd->busstate = DHD_BUS_DOWN;
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	dhdpcie_bus_intr_disable(bus);
++	status =  dhdpcie_bus_cfg_read_dword(bus, PCIIntstatus, 4);
++	dhdpcie_bus_cfg_write_dword(bus, PCIIntstatus, 4, status);
++
++	if (!dhd_download_fw_on_driverload) {
++		dhd_dpc_kill(bus->dhd);
++	}
++
++	/* Clear rx control and wake any waiters */
++	dhd_os_set_ioctl_resp_timeout(IOCTL_DISABLE_TIMEOUT);
++	dhd_wakeup_ioctl_event(bus->dhd, IOCTL_RETURN_ON_BUS_STOP);
++
++done:
++	return;
++}
++
++#ifdef DEVICE_TX_STUCK_DETECT
++void
++dhd_bus_send_msg_to_daemon(int reason)
++{
++	bcm_to_info_t to_info;
++
++	to_info.magic = BCM_TO_MAGIC;
++	to_info.reason = reason;
++
++	dhd_send_msg_to_daemon(NULL, (void *)&to_info, sizeof(bcm_to_info_t));
++	return;
++}
++
++/**
++ * scan the flow rings in active list to check if stuck and notify application
++ * The conditions for warn/stuck detection are
++ * 1. Flow ring is active
++ * 2. There are packets to be consumed by the consumer (wr != rd)
++ * If 1 and 2 are true, then
++ * 3. Warn, if Tx completion is not received for a duration of DEVICE_TX_STUCK_WARN_DURATION
++ * 4. Trap FW, if Tx completion is not received for a duration of DEVICE_TX_STUCK_DURATION
++ */
++static void
++dhd_bus_device_tx_stuck_scan(dhd_bus_t *bus)
++{
++	uint32 tx_cmpl;
++	unsigned long list_lock_flags;
++	unsigned long ring_lock_flags;
++	dll_t *item, *prev;
++	flow_ring_node_t *flow_ring_node;
++	bool ring_empty;
++	bool active;
++
++	DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, list_lock_flags);
++
++	for (item = dll_tail_p(&bus->flowring_active_list);
++			!dll_end(&bus->flowring_active_list, item); item = prev) {
++
++		prev = dll_prev_p(item);
++
++		flow_ring_node = dhd_constlist_to_flowring(item);
++		DHD_FLOWRING_LOCK(flow_ring_node->lock, ring_lock_flags);
++		tx_cmpl = flow_ring_node->tx_cmpl;
++		active = flow_ring_node->active;
++		ring_empty = dhd_prot_is_cmpl_ring_empty(bus->dhd, flow_ring_node->prot_info);
++		DHD_FLOWRING_UNLOCK(flow_ring_node->lock, ring_lock_flags);
++
++		if (ring_empty) {
++			/* reset conters... etc */
++			flow_ring_node->stuck_count = 0;
++			flow_ring_node->tx_cmpl_prev = tx_cmpl;
++			continue;
++		}
++		/**
++		 * DEVICE_TX_STUCK_WARN_DURATION, DEVICE_TX_STUCK_DURATION are integer
++		 * representation of time, to decide if a flow is in warn state or stuck.
++		 *
++		 * flow_ring_node->stuck_count is an integer counter representing how long
++		 * tx_cmpl is not received though there are pending packets in the ring
++		 * to be consumed by the dongle for that particular flow.
++		 *
++		 * This method of determining time elapsed is helpful in sleep/wake scenarios.
++		 * If host sleeps and wakes up, that sleep time is not considered into
++		 * stuck duration.
++		 */
++		if ((tx_cmpl == flow_ring_node->tx_cmpl_prev) && active) {
++
++			flow_ring_node->stuck_count++;
++
++			DHD_ERROR(("%s: flowid: %d tx_cmpl: %u tx_cmpl_prev: %u stuck_count: %d\n",
++				__func__, flow_ring_node->flowid, tx_cmpl,
++				flow_ring_node->tx_cmpl_prev, flow_ring_node->stuck_count));
++
++			switch (flow_ring_node->stuck_count) {
++				case DEVICE_TX_STUCK_WARN_DURATION:
++					/**
++					 * Notify Device Tx Stuck Notification App about the
++					 * device Tx stuck warning for this flowid.
++					 * App will collect the logs required.
++					 */
++					DHD_ERROR(("stuck warning for flowid: %d sent to app\n",
++						flow_ring_node->flowid));
++					dhd_bus_send_msg_to_daemon(REASON_DEVICE_TX_STUCK_WARNING);
++					break;
++				case DEVICE_TX_STUCK_DURATION:
++					/**
++					 * Notify Device Tx Stuck Notification App about the
++					 * device Tx stuck info for this flowid.
++					 * App will collect the logs required.
++					 */
++					DHD_ERROR(("stuck information for flowid: %d sent to app\n",
++						flow_ring_node->flowid));
++					dhd_bus_send_msg_to_daemon(REASON_DEVICE_TX_STUCK);
++					break;
++				default:
++					break;
++			}
++		} else {
++			flow_ring_node->tx_cmpl_prev = tx_cmpl;
++			flow_ring_node->stuck_count = 0;
++		}
++	}
++	DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, list_lock_flags);
++}
++/**
++ * schedules dhd_bus_device_tx_stuck_scan after DEVICE_TX_STUCK_CKECK_TIMEOUT,
++ * to determine if any flowid is stuck.
++ */
++static void
++dhd_bus_device_stuck_scan(dhd_bus_t *bus)
++{
++	uint32 time_stamp; /* in millisec */
++	uint32 diff;
++
++	/* Need not run the algorith if Dongle has trapped */
++	if (bus->dhd->dongle_trap_occured) {
++		return;
++	}
++	time_stamp = OSL_SYSUPTIME();
++	diff = time_stamp - bus->device_tx_stuck_check;
++	if (diff > DEVICE_TX_STUCK_CKECK_TIMEOUT) {
++		dhd_bus_device_tx_stuck_scan(bus);
++		bus->device_tx_stuck_check = OSL_SYSUPTIME();
++	}
++	return;
++}
++#endif /* DEVICE_TX_STUCK_DETECT */
++
++/** Watchdog timer function */
++bool dhd_bus_watchdog(dhd_pub_t *dhd)
++{
++	unsigned long flags;
++	dhd_bus_t *bus;
++	bus = dhd->bus;
++
++	DHD_GENERAL_LOCK(dhd, flags);
++	if (DHD_BUS_CHECK_DOWN_OR_DOWN_IN_PROGRESS(dhd) ||
++			DHD_BUS_CHECK_SUSPEND_OR_SUSPEND_IN_PROGRESS(dhd)) {
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		return FALSE;
++	}
++	DHD_BUS_BUSY_SET_IN_WD(dhd);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++#ifdef DHD_PCIE_RUNTIMEPM
++	dhdpcie_runtime_bus_wake(dhd, TRUE, __builtin_return_address(0));
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++
++
++	/* Poll for console output periodically */
++	if (dhd->busstate == DHD_BUS_DATA &&
++		dhd_console_ms != 0 && !bus->d3_suspend_pending) {
++		bus->console.count += dhd_watchdog_ms;
++		if (bus->console.count >= dhd_console_ms) {
++			bus->console.count -= dhd_console_ms;
++			/* Make sure backplane clock is on */
++			if (dhdpcie_bus_readconsole(bus) < 0)
++				dhd_console_ms = 0;	/* On error, stop trying */
++		}
++	}
++
++#ifdef DHD_READ_INTSTATUS_IN_DPC
++	if (bus->poll) {
++		bus->ipend = TRUE;
++		bus->dpc_sched = TRUE;
++		dhd_sched_dpc(bus->dhd);     /* queue DPC now!! */
++	}
++#endif /* DHD_READ_INTSTATUS_IN_DPC */
++
++#if defined(PCIE_OOB) || defined(PCIE_INB_DW)
++	/* If haven't communicated with device for a while, deassert the Device_Wake GPIO */
++	if (dhd_doorbell_timeout != 0 && dhd->busstate == DHD_BUS_DATA &&
++		dhd->up && dhd_timeout_expired(&bus->doorbell_timer)) {
++		dhd_bus_set_device_wake(bus, FALSE);
++	}
++#endif /* defined(PCIE_OOB) || defined(PCIE_INB_DW) */
++#ifdef PCIE_INB_DW
++	if (INBAND_DW_ENAB(bus)) {
++		if (bus->ds_exit_timeout) {
++			bus->ds_exit_timeout --;
++			if (bus->ds_exit_timeout == 1) {
++				DHD_ERROR(("DS-EXIT TIMEOUT\n"));
++				bus->ds_exit_timeout = 0;
++				bus->inband_ds_exit_to_cnt++;
++			}
++		}
++		if (bus->host_sleep_exit_timeout) {
++			bus->host_sleep_exit_timeout --;
++			if (bus->host_sleep_exit_timeout == 1) {
++				DHD_ERROR(("HOST_SLEEP-EXIT TIMEOUT\n"));
++				bus->host_sleep_exit_timeout = 0;
++				bus->inband_host_sleep_exit_to_cnt++;
++			}
++		}
++	}
++#endif /* PCIE_INB_DW */
++
++#ifdef DEVICE_TX_STUCK_DETECT
++	if (dhd->bus->dev_tx_stuck_monitor == TRUE) {
++		dhd_bus_device_stuck_scan(dhd->bus);
++	}
++#endif /* DEVICE_TX_STUCK_DETECT */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++	DHD_BUS_BUSY_CLEAR_IN_WD(dhd);
++	dhd_os_busbusy_wake(dhd);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++	return TRUE;
++} /* dhd_bus_watchdog */
++
++
++uint16
++dhd_get_chipid(dhd_pub_t *dhd)
++{
++	dhd_bus_t *bus = dhd->bus;
++
++	if (bus && bus->sih)
++		return (uint16)si_chipid(bus->sih);
++	else
++		return 0;
++}
++
++/* Download firmware image and nvram image */
++int
++dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh,
++                          char *pfw_path, char *pnv_path,
++                          char *pclm_path, char *pconf_path)
++{
++	int ret;
++
++	bus->fw_path = pfw_path;
++	bus->nv_path = pnv_path;
++	bus->dhd->clm_path = pclm_path;
++	bus->dhd->conf_path = pconf_path;
++
++
++#if defined(DHD_BLOB_EXISTENCE_CHECK)
++	dhd_set_blob_support(bus->dhd, bus->fw_path);
++#endif /* DHD_BLOB_EXISTENCE_CHECK */
++
++	DHD_ERROR(("%s: firmware path=%s, nvram path=%s\n",
++		__FUNCTION__, bus->fw_path, bus->nv_path));
++
++	ret = dhdpcie_download_firmware(bus, osh);
++
++	return ret;
++}
++
++void
++dhd_set_bus_params(struct dhd_bus *bus)
++{
++	if (bus->dhd->conf->dhd_poll >= 0) {
++		bus->poll = bus->dhd->conf->dhd_poll;
++		if (!bus->pollrate)
++			bus->pollrate = 1;
++		printf("%s: set polling mode %d\n", __FUNCTION__, bus->dhd->conf->dhd_poll);
++	}
++}
++
++static int
++dhdpcie_download_firmware(struct dhd_bus *bus, osl_t *osh)
++{
++	int ret = 0;
++#if defined(BCM_REQUEST_FW)
++	uint chipid = bus->sih->chip;
++	uint revid = bus->sih->chiprev;
++	char fw_path[64] = "/lib/firmware/brcm/bcm";	/* path to firmware image */
++	char nv_path[64];		/* path to nvram vars file */
++	bus->fw_path = fw_path;
++	bus->nv_path = nv_path;
++	switch (chipid) {
++	case BCM43570_CHIP_ID:
++		bcmstrncat(fw_path, "43570", 5);
++		switch (revid) {
++		case 0:
++			bcmstrncat(fw_path, "a0", 2);
++			break;
++		case 2:
++			bcmstrncat(fw_path, "a2", 2);
++			break;
++		default:
++			DHD_ERROR(("%s: revid is not found %x\n", __FUNCTION__,
++			revid));
++			break;
++		}
++		break;
++	default:
++		DHD_ERROR(("%s: unsupported device %x\n", __FUNCTION__,
++		chipid));
++		return 0;
++	}
++	/* load board specific nvram file */
++	snprintf(bus->nv_path, sizeof(nv_path), "%s.nvm", fw_path);
++	/* load firmware */
++	snprintf(bus->fw_path, sizeof(fw_path), "%s-firmware.bin", fw_path);
++#endif /* BCM_REQUEST_FW */
++
++	DHD_OS_WAKE_LOCK(bus->dhd);
++
++	dhd_conf_set_path_params(bus->dhd, NULL, bus->fw_path, bus->nv_path);
++	dhd_set_bus_params(bus);
++
++	ret = _dhdpcie_download_firmware(bus);
++
++	DHD_OS_WAKE_UNLOCK(bus->dhd);
++	return ret;
++}
++
++static int
++dhdpcie_download_code_file(struct dhd_bus *bus, char *pfw_path)
++{
++	int bcmerror = BCME_ERROR;
++	int offset = 0;
++	int len = 0;
++	bool store_reset;
++	char *imgbuf = NULL;
++	uint8 *memblock = NULL, *memptr;
++	uint8 *memptr_tmp = NULL; // terence: check downloaded firmware is correct
++
++	int offset_end = bus->ramsize;
++
++#ifndef DHD_EFI
++	DHD_ERROR(("%s: download firmware %s\n", __FUNCTION__, pfw_path));
++#endif /* DHD_EFI */
++
++	/* Should succeed in opening image if it is actually given through registry
++	 * entry or in module param.
++	 */
++	imgbuf = dhd_os_open_image(pfw_path);
++	if (imgbuf == NULL) {
++		printf("%s: Open firmware file failed %s\n", __FUNCTION__, pfw_path);
++		goto err;
++	}
++
++	memptr = memblock = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN);
++	if (memblock == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK));
++		goto err;
++	}
++	if (dhd_msg_level & DHD_TRACE_VAL) {
++		memptr_tmp = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN);
++		if (memptr_tmp == NULL) {
++			DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK));
++			goto err;
++		}
++	}
++	if ((uint32)(uintptr)memblock % DHD_SDALIGN) {
++		memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN));
++	}
++
++
++	/* check if CR4/CA7 */
++	store_reset = (si_setcore(bus->sih, ARMCR4_CORE_ID, 0) ||
++			si_setcore(bus->sih, ARMCA7_CORE_ID, 0));
++
++	/* Download image with MEMBLOCK size */
++	while ((len = dhd_os_get_image_block((char*)memptr, MEMBLOCK, imgbuf))) {
++		if (len < 0) {
++			DHD_ERROR(("%s: dhd_os_get_image_block failed (%d)\n", __FUNCTION__, len));
++			bcmerror = BCME_ERROR;
++			goto err;
++		}
++		/* if address is 0, store the reset instruction to be written in 0 */
++		if (store_reset) {
++			ASSERT(offset == 0);
++			bus->resetinstr = *(((uint32*)memptr));
++			/* Add start of RAM address to the address given by user */
++			offset += bus->dongle_ram_base;
++			offset_end += offset;
++			store_reset = FALSE;
++		}
++
++		bcmerror = dhdpcie_bus_membytes(bus, TRUE, offset, (uint8 *)memptr, len);
++		if (bcmerror) {
++			DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
++				__FUNCTION__, bcmerror, MEMBLOCK, offset));
++			goto err;
++		}
++
++		if (dhd_msg_level & DHD_TRACE_VAL) {
++			bcmerror = dhdpcie_bus_membytes(bus, FALSE, offset, memptr_tmp, len);
++			if (bcmerror) {
++				DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
++				        __FUNCTION__, bcmerror, MEMBLOCK, offset));
++				goto err;
++			}
++			if (memcmp(memptr_tmp, memptr, len)) {
++				DHD_ERROR(("%s: Downloaded image is corrupted.\n", __FUNCTION__));
++				goto err;
++			} else
++				DHD_INFO(("%s: Download, Upload and compare succeeded.\n", __FUNCTION__));
++		}
++		offset += MEMBLOCK;
++
++		if (offset >= offset_end) {
++			DHD_ERROR(("%s: invalid address access to %x (offset end: %x)\n",
++				__FUNCTION__, offset, offset_end));
++			bcmerror = BCME_ERROR;
++			goto err;
++		}
++	}
++
++err:
++	if (memblock) {
++		MFREE(bus->dhd->osh, memblock, MEMBLOCK + DHD_SDALIGN);
++		if (dhd_msg_level & DHD_TRACE_VAL) {
++			if (memptr_tmp)
++				MFREE(bus->dhd->osh, memptr_tmp, MEMBLOCK + DHD_SDALIGN);
++		}
++	}
++
++	if (imgbuf) {
++		dhd_os_close_image(imgbuf);
++	}
++
++	return bcmerror;
++} /* dhdpcie_download_code_file */
++
++#ifdef CUSTOMER_HW4_DEBUG
++#define MIN_NVRAMVARS_SIZE 128
++#endif /* CUSTOMER_HW4_DEBUG */
++
++static int
++dhdpcie_download_nvram(struct dhd_bus *bus)
++{
++	int bcmerror = BCME_ERROR;
++	uint len;
++	char * memblock = NULL;
++	char *bufp;
++	char *pnv_path;
++	bool nvram_file_exists;
++	bool nvram_uefi_exists = FALSE;
++	bool local_alloc = FALSE;
++	pnv_path = bus->nv_path;
++
++#ifdef BCMEMBEDIMAGE
++	nvram_file_exists = TRUE;
++#else
++	nvram_file_exists = ((pnv_path != NULL) && (pnv_path[0] != '\0'));
++#endif
++
++	/* First try UEFI */
++	len = MAX_NVRAMBUF_SIZE;
++	dhd_get_download_buffer(bus->dhd, NULL, NVRAM, &memblock, (int *)&len);
++
++	/* If UEFI empty, then read from file system */
++	if ((len <= 0) || (memblock == NULL)) {
++
++		if (nvram_file_exists) {
++			len = MAX_NVRAMBUF_SIZE;
++			dhd_get_download_buffer(bus->dhd, pnv_path, NVRAM, &memblock, (int *)&len);
++			if ((len <= 0 || len > MAX_NVRAMBUF_SIZE)) {
++				goto err;
++			}
++		}
++		else {
++			/* For SROM OTP no external file or UEFI required */
++			bcmerror = BCME_OK;
++		}
++	} else {
++		nvram_uefi_exists = TRUE;
++	}
++
++	DHD_ERROR(("%s: dhd_get_download_buffer len %d\n", __FUNCTION__, len));
++
++	if (len > 0 && len <= MAX_NVRAMBUF_SIZE && memblock != NULL) {
++		bufp = (char *) memblock;
++
++#ifdef CACHE_FW_IMAGES
++		if (bus->processed_nvram_params_len) {
++			len = bus->processed_nvram_params_len;
++		}
++
++		if (!bus->processed_nvram_params_len) {
++			bufp[len] = 0;
++			if (nvram_uefi_exists || nvram_file_exists) {
++				len = process_nvram_vars(bufp, len);
++				bus->processed_nvram_params_len = len;
++			}
++		} else
++#else
++		{
++			bufp[len] = 0;
++			if (nvram_uefi_exists || nvram_file_exists) {
++				len = process_nvram_vars(bufp, len);
++			}
++		}
++#endif /* CACHE_FW_IMAGES */
++
++		DHD_ERROR(("%s: process_nvram_vars len %d\n", __FUNCTION__, len));
++#ifdef CUSTOMER_HW4_DEBUG
++		if (len < MIN_NVRAMVARS_SIZE) {
++			DHD_ERROR(("%s: invalid nvram size in process_nvram_vars \n",
++				__FUNCTION__));
++			bcmerror = BCME_ERROR;
++			goto err;
++		}
++#endif /* CUSTOMER_HW4_DEBUG */
++
++		if (len % 4) {
++			len += 4 - (len % 4);
++		}
++		bufp += len;
++		*bufp++ = 0;
++		if (len)
++			bcmerror = dhdpcie_downloadvars(bus, memblock, len + 1);
++		if (bcmerror) {
++			DHD_ERROR(("%s: error downloading vars: %d\n",
++				__FUNCTION__, bcmerror));
++		}
++	}
++
++
++err:
++	if (memblock) {
++		if (local_alloc) {
++			MFREE(bus->dhd->osh, memblock, MAX_NVRAMBUF_SIZE);
++		} else {
++			dhd_free_download_buffer(bus->dhd, memblock, MAX_NVRAMBUF_SIZE);
++		}
++	}
++
++	return bcmerror;
++}
++
++
++#ifdef BCMEMBEDIMAGE
++int
++dhdpcie_download_code_array(struct dhd_bus *bus)
++{
++	int bcmerror = -1;
++	int offset = 0;
++	unsigned char *p_dlarray  = NULL;
++	unsigned int dlarray_size = 0;
++	unsigned int downloded_len, remaining_len, len;
++	char *p_dlimagename, *p_dlimagever, *p_dlimagedate;
++	uint8 *memblock = NULL, *memptr;
++
++	downloded_len = 0;
++	remaining_len = 0;
++	len = 0;
++
++#ifdef DHD_EFI
++	p_dlarray = rtecdc_fw_arr;
++	dlarray_size = sizeof(rtecdc_fw_arr);
++#else
++	p_dlarray = dlarray;
++	dlarray_size = sizeof(dlarray);
++	p_dlimagename = dlimagename;
++	p_dlimagever  = dlimagever;
++	p_dlimagedate = dlimagedate;
++#endif /* DHD_EFI */
++
++#ifndef DHD_EFI
++	if ((p_dlarray == 0) ||	(dlarray_size == 0) ||(dlarray_size > bus->ramsize) ||
++		(p_dlimagename == 0) ||	(p_dlimagever  == 0) ||	(p_dlimagedate == 0))
++		goto err;
++#endif /* DHD_EFI */
++
++	memptr = memblock = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN);
++	if (memblock == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK));
++		goto err;
++	}
++	if ((uint32)(uintptr)memblock % DHD_SDALIGN)
++		memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN));
++
++	while (downloded_len  < dlarray_size) {
++		remaining_len = dlarray_size - downloded_len;
++		if (remaining_len >= MEMBLOCK)
++			len = MEMBLOCK;
++		else
++			len = remaining_len;
++
++		memcpy(memptr, (p_dlarray + downloded_len), len);
++		/* check if CR4/CA7 */
++		if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0) ||
++			si_setcore(bus->sih, SYSMEM_CORE_ID, 0)) {
++			/* if address is 0, store the reset instruction to be written in 0 */
++			if (offset == 0) {
++				bus->resetinstr = *(((uint32*)memptr));
++				/* Add start of RAM address to the address given by user */
++				offset += bus->dongle_ram_base;
++			}
++		}
++		bcmerror = dhdpcie_bus_membytes(bus, TRUE, offset, (uint8 *)memptr, len);
++		downloded_len += len;
++		if (bcmerror) {
++			DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
++				__FUNCTION__, bcmerror, MEMBLOCK, offset));
++			goto err;
++		}
++		offset += MEMBLOCK;
++	}
++
++#ifdef DHD_DEBUG
++	/* Upload and compare the downloaded code */
++	{
++		unsigned char *ularray = NULL;
++		unsigned int uploded_len;
++		uploded_len = 0;
++		bcmerror = -1;
++		ularray = MALLOC(bus->dhd->osh, dlarray_size);
++		if (ularray == NULL)
++			goto upload_err;
++		/* Upload image to verify downloaded contents. */
++		offset = bus->dongle_ram_base;
++		memset(ularray, 0xaa, dlarray_size);
++		while (uploded_len  < dlarray_size) {
++			remaining_len = dlarray_size - uploded_len;
++			if (remaining_len >= MEMBLOCK)
++				len = MEMBLOCK;
++			else
++				len = remaining_len;
++			bcmerror = dhdpcie_bus_membytes(bus, FALSE, offset,
++				(uint8 *)(ularray + uploded_len), len);
++			if (bcmerror) {
++				DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
++					__FUNCTION__, bcmerror, MEMBLOCK, offset));
++				goto upload_err;
++			}
++
++			uploded_len += len;
++			offset += MEMBLOCK;
++		}
++#ifdef DHD_EFI
++		if (memcmp(p_dlarray, ularray, dlarray_size)) {
++			DHD_ERROR(("%s: Downloaded image is corrupted ! \n", __FUNCTION__));
++			goto upload_err;
++		} else
++			DHD_ERROR(("%s: Download, Upload and compare succeeded .\n", __FUNCTION__));
++#else
++		if (memcmp(p_dlarray, ularray, dlarray_size)) {
++			DHD_ERROR(("%s: Downloaded image is corrupted (%s, %s, %s).\n",
++				__FUNCTION__, p_dlimagename, p_dlimagever, p_dlimagedate));
++			goto upload_err;
++
++		} else
++			DHD_ERROR(("%s: Download, Upload and compare succeeded (%s, %s, %s).\n",
++				__FUNCTION__, p_dlimagename, p_dlimagever, p_dlimagedate));
++#endif /* DHD_EFI */
++
++upload_err:
++		if (ularray)
++			MFREE(bus->dhd->osh, ularray, dlarray_size);
++	}
++#endif /* DHD_DEBUG */
++err:
++
++	if (memblock)
++		MFREE(bus->dhd->osh, memblock, MEMBLOCK + DHD_SDALIGN);
++
++	return bcmerror;
++} /* dhdpcie_download_code_array */
++#endif /* BCMEMBEDIMAGE */
++
++
++static int
++dhdpcie_ramsize_read_image(struct dhd_bus *bus, char *buf, int len)
++{
++	int bcmerror = BCME_ERROR;
++	char *imgbuf = NULL;
++
++	if (buf == NULL || len == 0)
++		goto err;
++
++	/* External image takes precedence if specified */
++	if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
++		imgbuf = dhd_os_open_image(bus->fw_path);
++		if (imgbuf == NULL) {
++			DHD_ERROR(("%s: Failed to open firmware file\n", __FUNCTION__));
++			goto err;
++		}
++
++		/* Read it */
++		if (len != dhd_os_get_image_block(buf, len, imgbuf)) {
++			DHD_ERROR(("%s: Failed to read %d bytes data\n", __FUNCTION__, len));
++			goto err;
++		}
++
++		bcmerror = BCME_OK;
++	}
++
++err:
++	if (imgbuf)
++		dhd_os_close_image(imgbuf);
++
++	return bcmerror;
++}
++
++
++/* The ramsize can be changed in the dongle image, for example 4365 chip share the sysmem
++ * with BMC and we can adjust how many sysmem belong to CA7 during dongle compilation.
++ * So in DHD we need to detect this case and update the correct dongle RAMSIZE as well.
++ */
++static void
++dhdpcie_ramsize_adj(struct dhd_bus *bus)
++{
++	int i, search_len = 0;
++	uint8 *memptr = NULL;
++	uint8 *ramsizeptr = NULL;
++	uint ramsizelen;
++	uint32 ramsize_ptr_ptr[] = {RAMSIZE_PTR_PTR_LIST};
++	hnd_ramsize_ptr_t ramsize_info;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	/* Adjust dongle RAMSIZE already called. */
++	if (bus->ramsize_adjusted) {
++		return;
++	}
++
++	/* success or failure,  we don't want to be here
++	 * more than once.
++	 */
++	bus->ramsize_adjusted = TRUE;
++
++	/* Not handle if user restrict dongle ram size enabled */
++	if (dhd_dongle_memsize) {
++		DHD_ERROR(("%s: user restrict dongle ram size to %d.\n", __FUNCTION__,
++			dhd_dongle_memsize));
++		return;
++	}
++
++#ifndef BCMEMBEDIMAGE
++	/* Out immediately if no image to download */
++	if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
++		DHD_ERROR(("%s: no fimrware file\n", __FUNCTION__));
++		return;
++	}
++#endif /* !BCMEMBEDIMAGE */
++
++	/* Get maximum RAMSIZE info search length */
++	for (i = 0; ; i++) {
++		if (ramsize_ptr_ptr[i] == RAMSIZE_PTR_PTR_END)
++			break;
++
++		if (search_len < (int)ramsize_ptr_ptr[i])
++			search_len = (int)ramsize_ptr_ptr[i];
++	}
++
++	if (!search_len)
++		return;
++
++	search_len += sizeof(hnd_ramsize_ptr_t);
++
++	memptr = MALLOC(bus->dhd->osh, search_len);
++	if (memptr == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, search_len));
++		return;
++	}
++
++	/* External image takes precedence if specified */
++	if (dhdpcie_ramsize_read_image(bus, (char *)memptr, search_len) != BCME_OK) {
++#if defined(BCMEMBEDIMAGE) && !defined(DHD_EFI)
++		unsigned char *p_dlarray  = NULL;
++		unsigned int dlarray_size = 0;
++		char *p_dlimagename, *p_dlimagever, *p_dlimagedate;
++
++		p_dlarray = dlarray;
++		dlarray_size = sizeof(dlarray);
++		p_dlimagename = dlimagename;
++		p_dlimagever  = dlimagever;
++		p_dlimagedate = dlimagedate;
++
++		if ((p_dlarray == 0) ||	(dlarray_size == 0) || (p_dlimagename == 0) ||
++			(p_dlimagever  == 0) ||	(p_dlimagedate == 0))
++			goto err;
++
++		ramsizeptr = p_dlarray;
++		ramsizelen = dlarray_size;
++#else
++		goto err;
++#endif /* BCMEMBEDIMAGE && !DHD_EFI */
++	}
++	else {
++		ramsizeptr = memptr;
++		ramsizelen = search_len;
++	}
++
++	if (ramsizeptr) {
++		/* Check Magic */
++		for (i = 0; ; i++) {
++			if (ramsize_ptr_ptr[i] == RAMSIZE_PTR_PTR_END)
++				break;
++
++			if (ramsize_ptr_ptr[i] + sizeof(hnd_ramsize_ptr_t) > ramsizelen)
++				continue;
++
++			memcpy((char *)&ramsize_info, ramsizeptr + ramsize_ptr_ptr[i],
++				sizeof(hnd_ramsize_ptr_t));
++
++			if (ramsize_info.magic == HTOL32(HND_RAMSIZE_PTR_MAGIC)) {
++				bus->orig_ramsize = LTOH32(ramsize_info.ram_size);
++				bus->ramsize = LTOH32(ramsize_info.ram_size);
++				DHD_ERROR(("%s: Adjust dongle RAMSIZE to 0x%x\n", __FUNCTION__,
++					bus->ramsize));
++				break;
++			}
++		}
++	}
++
++err:
++	if (memptr)
++		MFREE(bus->dhd->osh, memptr, search_len);
++
++	return;
++} /* _dhdpcie_download_firmware */
++
++static int
++_dhdpcie_download_firmware(struct dhd_bus *bus)
++{
++	int bcmerror = -1;
++
++	bool embed = FALSE;	/* download embedded firmware */
++	bool dlok = FALSE;	/* download firmware succeeded */
++
++	/* Out immediately if no image to download */
++	if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
++#ifdef BCMEMBEDIMAGE
++		embed = TRUE;
++#else
++		DHD_ERROR(("%s: no fimrware file\n", __FUNCTION__));
++		return 0;
++#endif
++	}
++	/* Adjust ram size */
++	dhdpcie_ramsize_adj(bus);
++
++	/* Keep arm in reset */
++	if (dhdpcie_bus_download_state(bus, TRUE)) {
++		DHD_ERROR(("%s: error placing ARM core in reset\n", __FUNCTION__));
++		goto err;
++	}
++
++	/* External image takes precedence if specified */
++	if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
++		if (dhdpcie_download_code_file(bus, bus->fw_path)) {
++			DHD_ERROR(("%s: dongle image file download failed\n", __FUNCTION__));
++#ifdef BCMEMBEDIMAGE
++			embed = TRUE;
++#else
++			goto err;
++#endif
++		} else {
++			embed = FALSE;
++			dlok = TRUE;
++		}
++	}
++
++#ifdef BCMEMBEDIMAGE
++	if (embed) {
++		if (dhdpcie_download_code_array(bus)) {
++			DHD_ERROR(("%s: dongle image array download failed\n", __FUNCTION__));
++			goto err;
++		} else {
++			dlok = TRUE;
++		}
++	}
++#else
++	BCM_REFERENCE(embed);
++#endif
++	if (!dlok) {
++		DHD_ERROR(("%s: dongle image download failed\n", __FUNCTION__));
++		goto err;
++	}
++
++	/* EXAMPLE: nvram_array */
++	/* If a valid nvram_arry is specified as above, it can be passed down to dongle */
++	/* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
++
++
++	/* External nvram takes precedence if specified */
++	if (dhdpcie_download_nvram(bus)) {
++		DHD_ERROR(("%s: dongle nvram file download failed\n", __FUNCTION__));
++		goto err;
++	}
++
++	/* Take arm out of reset */
++	if (dhdpcie_bus_download_state(bus, FALSE)) {
++		DHD_ERROR(("%s: error getting out of ARM core reset\n", __FUNCTION__));
++		goto err;
++	}
++
++	bcmerror = 0;
++
++err:
++	return bcmerror;
++} /* _dhdpcie_download_firmware */
++
++#define CONSOLE_LINE_MAX	192
++
++static int
++dhdpcie_bus_readconsole(dhd_bus_t *bus)
++{
++	dhd_console_t *c = &bus->console;
++	uint8 line[CONSOLE_LINE_MAX], ch;
++	uint32 n, idx, addr;
++	int rv;
++
++	/* Don't do anything until FWREADY updates console address */
++	if (bus->console_addr == 0)
++		return -1;
++
++	/* Read console log struct */
++	addr = bus->console_addr + OFFSETOF(hnd_cons_t, log);
++
++	if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)&c->log, sizeof(c->log))) < 0)
++		return rv;
++
++	/* Allocate console buffer (one time only) */
++	if (c->buf == NULL) {
++		c->bufsize = ltoh32(c->log.buf_size);
++		if ((c->buf = MALLOC(bus->dhd->osh, c->bufsize)) == NULL)
++			return BCME_NOMEM;
++	}
++	idx = ltoh32(c->log.idx);
++
++	/* Protect against corrupt value */
++	if (idx > c->bufsize)
++		return BCME_ERROR;
++
++	/* Skip reading the console buffer if the index pointer has not moved */
++	if (idx == c->last)
++		return BCME_OK;
++
++	/* Read the console buffer */
++	addr = ltoh32(c->log.buf);
++	if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, c->buf, c->bufsize)) < 0)
++		return rv;
++
++	while (c->last != idx) {
++		for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
++			if (c->last == idx) {
++				/* This would output a partial line.  Instead, back up
++				 * the buffer pointer and output this line next time around.
++				 */
++				if (c->last >= n)
++					c->last -= n;
++				else
++					c->last = c->bufsize - n;
++				goto break2;
++			}
++			ch = c->buf[c->last];
++			c->last = (c->last + 1) % c->bufsize;
++			if (ch == '\n')
++				break;
++			line[n] = ch;
++		}
++
++		if (n > 0) {
++			if (line[n - 1] == '\r')
++				n--;
++			line[n] = 0;
++			DHD_FWLOG(("CONSOLE: %s\n", line));
++		}
++	}
++break2:
++
++	return BCME_OK;
++} /* dhdpcie_bus_readconsole */
++
++void
++dhd_bus_dump_console_buffer(dhd_bus_t *bus)
++{
++	uint32 n, i;
++	uint32 addr;
++	char *console_buffer = NULL;
++	uint32 console_ptr, console_size, console_index;
++	uint8 line[CONSOLE_LINE_MAX], ch;
++	int rv;
++
++	DHD_ERROR(("%s: Dump Complete Console Buffer\n", __FUNCTION__));
++
++	if (bus->is_linkdown) {
++		DHD_ERROR(("%s: Skip dump Console Buffer due to PCIe link down\n", __FUNCTION__));
++		return;
++	}
++
++	addr =	bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log);
++	if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr,
++		(uint8 *)&console_ptr, sizeof(console_ptr))) < 0) {
++		goto exit;
++	}
++
++	addr =	bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log.buf_size);
++	if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr,
++		(uint8 *)&console_size, sizeof(console_size))) < 0) {
++		goto exit;
++	}
++
++	addr =	bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log.idx);
++	if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr,
++		(uint8 *)&console_index, sizeof(console_index))) < 0) {
++		goto exit;
++	}
++
++	console_ptr = ltoh32(console_ptr);
++	console_size = ltoh32(console_size);
++	console_index = ltoh32(console_index);
++
++	if (console_size > CONSOLE_BUFFER_MAX ||
++		!(console_buffer = MALLOC(bus->dhd->osh, console_size))) {
++		goto exit;
++	}
++
++	if ((rv = dhdpcie_bus_membytes(bus, FALSE, console_ptr,
++		(uint8 *)console_buffer, console_size)) < 0) {
++		goto exit;
++	}
++
++	for (i = 0, n = 0; i < console_size; i += n + 1) {
++		for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
++			ch = console_buffer[(console_index + i + n) % console_size];
++			if (ch == '\n')
++				break;
++			line[n] = ch;
++		}
++
++
++		if (n > 0) {
++			if (line[n - 1] == '\r')
++				n--;
++			line[n] = 0;
++			/* Don't use DHD_ERROR macro since we print
++			 * a lot of information quickly. The macro
++			 * will truncate a lot of the printfs
++			 */
++
++			DHD_FWLOG(("CONSOLE: %s\n", line));
++		}
++	}
++
++exit:
++	if (console_buffer)
++		MFREE(bus->dhd->osh, console_buffer, console_size);
++	return;
++}
++
++static int
++dhdpcie_checkdied(dhd_bus_t *bus, char *data, uint size)
++{
++	int bcmerror = 0;
++	uint msize = 512;
++	char *mbuffer = NULL;
++	uint maxstrlen = 256;
++	char *str = NULL;
++	pciedev_shared_t *local_pciedev_shared = bus->pcie_sh;
++	struct bcmstrbuf strbuf;
++	unsigned long flags;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (DHD_NOCHECKDIED_ON()) {
++		return 0;
++	}
++
++	if (data == NULL) {
++		/*
++		 * Called after a rx ctrl timeout. "data" is NULL.
++		 * allocate memory to trace the trap or assert.
++		 */
++		size = msize;
++		mbuffer = data = MALLOC(bus->dhd->osh, msize);
++
++		if (mbuffer == NULL) {
++			DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, msize));
++			bcmerror = BCME_NOMEM;
++			goto done;
++		}
++	}
++
++	if ((str = MALLOC(bus->dhd->osh, maxstrlen)) == NULL) {
++		DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, maxstrlen));
++		bcmerror = BCME_NOMEM;
++		goto done;
++	}
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	DHD_BUS_BUSY_SET_IN_CHECKDIED(bus->dhd);
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	if ((bcmerror = dhdpcie_readshared(bus)) < 0) {
++		goto done;
++	}
++
++	bcm_binit(&strbuf, data, size);
++
++	bcm_bprintf(&strbuf, "msgtrace address : 0x%08X\nconsole address  : 0x%08X\n",
++	            local_pciedev_shared->msgtrace_addr, local_pciedev_shared->console_addr);
++
++	if ((local_pciedev_shared->flags & PCIE_SHARED_ASSERT_BUILT) == 0) {
++		/* NOTE: Misspelled assert is intentional - DO NOT FIX.
++		 * (Avoids conflict with real asserts for programmatic parsing of output.)
++		 */
++		bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
++	}
++
++	if ((bus->pcie_sh->flags & (PCIE_SHARED_ASSERT|PCIE_SHARED_TRAP)) == 0) {
++		/* NOTE: Misspelled assert is intentional - DO NOT FIX.
++		 * (Avoids conflict with real asserts for programmatic parsing of output.)
++		 */
++		bcm_bprintf(&strbuf, "No trap%s in dongle",
++		          (bus->pcie_sh->flags & PCIE_SHARED_ASSERT_BUILT)
++		          ?"/assrt" :"");
++	} else {
++		if (bus->pcie_sh->flags & PCIE_SHARED_ASSERT) {
++			/* Download assert */
++			bcm_bprintf(&strbuf, "Dongle assert");
++			if (bus->pcie_sh->assert_exp_addr != 0) {
++				str[0] = '\0';
++				if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE,
++					bus->pcie_sh->assert_exp_addr,
++					(uint8 *)str, maxstrlen)) < 0) {
++					goto done;
++				}
++
++				str[maxstrlen - 1] = '\0';
++				bcm_bprintf(&strbuf, " expr \"%s\"", str);
++			}
++
++			if (bus->pcie_sh->assert_file_addr != 0) {
++				str[0] = '\0';
++				if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE,
++					bus->pcie_sh->assert_file_addr,
++					(uint8 *)str, maxstrlen)) < 0) {
++					goto done;
++				}
++
++				str[maxstrlen - 1] = '\0';
++				bcm_bprintf(&strbuf, " file \"%s\"", str);
++			}
++
++			bcm_bprintf(&strbuf, " line %d ",  bus->pcie_sh->assert_line);
++		}
++
++		if (bus->pcie_sh->flags & PCIE_SHARED_TRAP) {
++			trap_t *tr = &bus->dhd->last_trap_info;
++			bus->dhd->dongle_trap_occured = TRUE;
++			if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE,
++				bus->pcie_sh->trap_addr, (uint8*)tr, sizeof(trap_t))) < 0) {
++				goto done;
++			}
++			dhd_bus_dump_trap_info(bus, &strbuf);
++
++			dhd_bus_dump_console_buffer(bus);
++		}
++	}
++
++	if (bus->pcie_sh->flags & (PCIE_SHARED_ASSERT | PCIE_SHARED_TRAP)) {
++		printf("%s: %s\n", __FUNCTION__, strbuf.origbuf);
++#ifdef REPORT_FATAL_TIMEOUTS
++		/**
++		 * stop the timers as FW trapped
++		 */
++		if (dhd_stop_scan_timer(bus->dhd)) {
++			DHD_ERROR(("dhd_stop_scan_timer failed\n"));
++			ASSERT(0);
++		}
++		if (dhd_stop_bus_timer(bus->dhd)) {
++			DHD_ERROR(("dhd_stop_bus_timer failed\n"));
++			ASSERT(0);
++		}
++		if (dhd_stop_cmd_timer(bus->dhd)) {
++			DHD_ERROR(("dhd_stop_cmd_timer failed\n"));
++			ASSERT(0);
++		}
++		if (dhd_stop_join_timer(bus->dhd)) {
++			DHD_ERROR(("dhd_stop_join_timer failed\n"));
++			ASSERT(0);
++		}
++#endif /* REPORT_FATAL_TIMEOUTS */
++
++		dhd_prot_debug_info_print(bus->dhd);
++
++#if defined(DHD_FW_COREDUMP)
++		/* save core dump or write to a file */
++		if (bus->dhd->memdump_enabled) {
++			bus->dhd->memdump_type = DUMP_TYPE_DONGLE_TRAP;
++			dhdpcie_mem_dump(bus);
++		}
++#endif /* DHD_FW_COREDUMP */
++
++		/* wake up IOCTL wait event */
++		dhd_wakeup_ioctl_event(bus->dhd, IOCTL_RETURN_ON_TRAP);
++
++		dhd_schedule_reset(bus->dhd);
++
++
++	}
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	DHD_BUS_BUSY_CLEAR_IN_CHECKDIED(bus->dhd);
++	dhd_os_busbusy_wake(bus->dhd);
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++done:
++	if (mbuffer)
++		MFREE(bus->dhd->osh, mbuffer, msize);
++	if (str)
++		MFREE(bus->dhd->osh, str, maxstrlen);
++
++	return bcmerror;
++} /* dhdpcie_checkdied */
++
++
++/* Custom copy of dhdpcie_mem_dump() that can be called at interrupt level */
++void dhdpcie_mem_dump_bugcheck(dhd_bus_t *bus, uint8 *buf)
++{
++	int ret = 0;
++	int size; /* Full mem size */
++	int start; /* Start address */
++	int read_size = 0; /* Read size of each iteration */
++	uint8 *databuf = buf;
++
++	if (bus == NULL) {
++		return;
++	}
++
++	start = bus->dongle_ram_base;
++	read_size = 4;
++	/* check for dead bus */
++	{
++		uint test_word = 0;
++		ret = dhdpcie_bus_membytes(bus, FALSE, start, (uint8*)&test_word, read_size);
++		/* if read error or bus timeout */
++		if (ret || (test_word == 0xFFFFFFFF)) {
++			return;
++		}
++	}
++
++	/* Get full mem size */
++	size = bus->ramsize;
++	/* Read mem content */
++	while (size)
++	{
++		read_size = MIN(MEMBLOCK, size);
++		if ((ret = dhdpcie_bus_membytes(bus, FALSE, start, databuf, read_size))) {
++			return;
++		}
++
++		/* Decrement size and increment start address */
++		size -= read_size;
++		start += read_size;
++		databuf += read_size;
++	}
++	bus->dhd->soc_ram = buf;
++	bus->dhd->soc_ram_length = bus->ramsize;
++	return;
++}
++
++
++#if defined(DHD_FW_COREDUMP)
++static int
++dhdpcie_mem_dump(dhd_bus_t *bus)
++{
++	int ret = 0;
++	int size; /* Full mem size */
++	int start = bus->dongle_ram_base; /* Start address */
++	int read_size = 0; /* Read size of each iteration */
++	uint8 *buf = NULL, *databuf = NULL;
++
++#ifdef EXYNOS_PCIE_DEBUG
++	exynos_pcie_register_dump(1);
++#endif /* EXYNOS_PCIE_DEBUG */
++
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++	if (bus->is_linkdown) {
++		DHD_ERROR(("%s: PCIe link is down so skip\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++
++	/* Get full mem size */
++	size = bus->ramsize;
++	buf = dhd_get_fwdump_buf(bus->dhd, size);
++	if (!buf) {
++		DHD_ERROR(("%s: Out of memory (%d bytes)\n", __FUNCTION__, size));
++		return BCME_ERROR;
++	}
++
++	/* Read mem content */
++	DHD_TRACE_HW4(("Dump dongle memory\n"));
++	databuf = buf;
++	while (size)
++	{
++		read_size = MIN(MEMBLOCK, size);
++		if ((ret = dhdpcie_bus_membytes(bus, FALSE, start, databuf, read_size)))
++		{
++			DHD_ERROR(("%s: Error membytes %d\n", __FUNCTION__, ret));
++			bus->dhd->memdump_success = FALSE;
++			return BCME_ERROR;
++		}
++		DHD_TRACE(("."));
++
++		/* Decrement size and increment start address */
++		size -= read_size;
++		start += read_size;
++		databuf += read_size;
++	}
++	bus->dhd->memdump_success = TRUE;
++
++	dhd_schedule_memdump(bus->dhd, buf, bus->ramsize);
++	/* buf, actually soc_ram free handled in dhd_{free,clear} */
++
++	return ret;
++}
++
++int
++dhd_bus_mem_dump(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++
++	if (dhdp->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s bus is down\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++#ifdef DHD_PCIE_RUNTIMEPM
++	if (dhdp->memdump_type == DUMP_TYPE_BY_SYSDUMP) {
++		DHD_ERROR(("%s : bus wakeup by SYSDUMP\n", __FUNCTION__));
++		dhdpcie_runtime_bus_wake(dhdp, TRUE, __builtin_return_address(0));
++	}
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++	if (DHD_BUS_CHECK_SUSPEND_OR_SUSPEND_IN_PROGRESS(dhdp)) {
++		DHD_ERROR(("%s: bus is in suspend(%d) or suspending(0x%x) state, so skip\n",
++			__FUNCTION__, dhdp->busstate, dhdp->dhd_bus_busy_state));
++		return BCME_ERROR;
++	}
++
++	return dhdpcie_mem_dump(bus);
++}
++
++int
++dhd_dongle_mem_dump(void)
++{
++	if (!g_dhd_bus) {
++		DHD_ERROR(("%s: Bus is NULL\n", __FUNCTION__));
++		return -ENODEV;
++	}
++
++	dhd_bus_dump_console_buffer(g_dhd_bus);
++	dhd_prot_debug_info_print(g_dhd_bus->dhd);
++
++	g_dhd_bus->dhd->memdump_enabled = DUMP_MEMFILE_BUGON;
++	g_dhd_bus->dhd->memdump_type = DUMP_TYPE_AP_ABNORMAL_ACCESS;
++
++#ifdef DHD_PCIE_RUNTIMEPM
++	dhdpcie_runtime_bus_wake(g_dhd_bus->dhd, TRUE, __builtin_return_address(0));
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++	DHD_OS_WAKE_LOCK(g_dhd_bus->dhd);
++	dhd_bus_mem_dump(g_dhd_bus->dhd);
++	DHD_OS_WAKE_UNLOCK(g_dhd_bus->dhd);
++	return 0;
++}
++EXPORT_SYMBOL(dhd_dongle_mem_dump);
++#endif	/* DHD_FW_COREDUMP */
++
++int
++dhd_socram_dump(dhd_bus_t *bus)
++{
++#ifdef DHD_PCIE_RUNTIMEPM
++	dhdpcie_runtime_bus_wake(bus->dhd, TRUE, __builtin_return_address(0));
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++#if defined(DHD_FW_COREDUMP)
++	DHD_OS_WAKE_LOCK(bus->dhd);
++	dhd_bus_mem_dump(bus->dhd);
++	DHD_OS_WAKE_UNLOCK(bus->dhd);
++	return 0;
++#else
++	return -1;
++#endif
++}
++
++/**
++ * Transfers bytes from host to dongle using pio mode.
++ * Parameter 'address' is a backplane address.
++ */
++static int
++dhdpcie_bus_membytes(dhd_bus_t *bus, bool write, ulong address, uint8 *data, uint size)
++{
++	uint dsize;
++	int detect_endian_flag = 0x01;
++	bool little_endian;
++
++	if (write && bus->is_linkdown) {
++		DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++
++	/* Detect endianness. */
++	little_endian = *(char *)&detect_endian_flag;
++
++	/* In remap mode, adjust address beyond socram and redirect
++	 * to devram at SOCDEVRAM_BP_ADDR since remap address > orig_ramsize
++	 * is not backplane accessible
++	 */
++
++	/* Determine initial transfer parameters */
++#ifdef DHD_SUPPORT_64BIT
++	dsize = sizeof(uint64);
++#else /* !DHD_SUPPORT_64BIT */
++	dsize = sizeof(uint32);
++#endif /* DHD_SUPPORT_64BIT */
++
++	/* Do the transfer(s) */
++	DHD_INFO(("%s: %s %d bytes in window 0x%08lx\n",
++	          __FUNCTION__, (write ? "write" : "read"), size, address));
++	if (write) {
++		while (size) {
++#ifdef DHD_SUPPORT_64BIT
++			if (size >= sizeof(uint64) && little_endian &&	!(address % 8)) {
++				dhdpcie_bus_wtcm64(bus, address, *((uint64 *)data));
++			}
++#else /* !DHD_SUPPORT_64BIT */
++			if (size >= sizeof(uint32) && little_endian &&	!(address % 4)) {
++				dhdpcie_bus_wtcm32(bus, address, *((uint32*)data));
++			}
++#endif /* DHD_SUPPORT_64BIT */
++			else {
++				dsize = sizeof(uint8);
++				dhdpcie_bus_wtcm8(bus, address, *data);
++			}
++
++			/* Adjust for next transfer (if any) */
++			if ((size -= dsize)) {
++				data += dsize;
++				address += dsize;
++			}
++		}
++	} else {
++		while (size) {
++#ifdef DHD_SUPPORT_64BIT
++			if (size >= sizeof(uint64) && little_endian &&	!(address % 8))
++			{
++				*(uint64 *)data = dhdpcie_bus_rtcm64(bus, address);
++			}
++#else /* !DHD_SUPPORT_64BIT */
++			if (size >= sizeof(uint32) && little_endian &&	!(address % 4))
++			{
++				*(uint32 *)data = dhdpcie_bus_rtcm32(bus, address);
++			}
++#endif /* DHD_SUPPORT_64BIT */
++			else {
++				dsize = sizeof(uint8);
++				*data = dhdpcie_bus_rtcm8(bus, address);
++			}
++
++			/* Adjust for next transfer (if any) */
++			if ((size -= dsize) > 0) {
++				data += dsize;
++				address += dsize;
++			}
++		}
++	}
++	return BCME_OK;
++} /* dhdpcie_bus_membytes */
++
++/**
++ * Transfers one transmit (ethernet) packet that was queued in the (flow controlled) flow ring queue
++ * to the (non flow controlled) flow ring.
++ */
++int BCMFASTPATH
++dhd_bus_schedule_queue(struct dhd_bus  *bus, uint16 flow_id, bool txs)
++{
++	flow_ring_node_t *flow_ring_node;
++	int ret = BCME_OK;
++#ifdef DHD_LOSSLESS_ROAMING
++	dhd_pub_t *dhdp = bus->dhd;
++#endif
++	DHD_INFO(("%s: flow_id is %d\n", __FUNCTION__, flow_id));
++
++	/* ASSERT on flow_id */
++	if (flow_id >= bus->max_submission_rings) {
++		DHD_ERROR(("%s: flow_id is invalid %d, max %d\n", __FUNCTION__,
++			flow_id, bus->max_submission_rings));
++		return 0;
++	}
++
++	flow_ring_node = DHD_FLOW_RING(bus->dhd, flow_id);
++
++#ifdef DHD_LOSSLESS_ROAMING
++	if ((dhdp->dequeue_prec_map & (1 << flow_ring_node->flow_info.tid)) == 0) {
++		DHD_INFO(("%s: tid %d is not in precedence map. block scheduling\n",
++			__FUNCTION__, flow_ring_node->flow_info.tid));
++		return BCME_OK;
++	}
++#endif /* DHD_LOSSLESS_ROAMING */
++
++	{
++		unsigned long flags;
++		void *txp = NULL;
++		flow_queue_t *queue;
++#ifdef DHD_LOSSLESS_ROAMING
++		struct ether_header *eh;
++		uint8 *pktdata;
++#endif /* DHD_LOSSLESS_ROAMING */
++
++		queue = &flow_ring_node->queue; /* queue associated with flow ring */
++
++		DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++
++		if (flow_ring_node->status != FLOW_RING_STATUS_OPEN) {
++			DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++			return BCME_NOTREADY;
++		}
++
++		while ((txp = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) {
++			if (bus->dhd->conf->orphan_move <= 1)
++				PKTORPHAN(txp, bus->dhd->conf->tsq);
++
++			/*
++			 * Modifying the packet length caused P2P cert failures.
++			 * Specifically on test cases where a packet of size 52 bytes
++			 * was injected, the sniffer capture showed 62 bytes because of
++			 * which the cert tests failed. So making the below change
++			 * only Router specific.
++			 */
++
++#ifdef DHDTCPACK_SUPPRESS
++			if (bus->dhd->tcpack_sup_mode != TCPACK_SUP_HOLD) {
++				ret = dhd_tcpack_check_xmit(bus->dhd, txp);
++				if (ret != BCME_OK) {
++					DHD_ERROR(("%s: dhd_tcpack_check_xmit() error.\n",
++						__FUNCTION__));
++				}
++			}
++#endif /* DHDTCPACK_SUPPRESS */
++#ifdef DHD_LOSSLESS_ROAMING
++			pktdata = (uint8 *)PKTDATA(OSH_NULL, txp);
++			eh = (struct ether_header *) pktdata;
++			if (eh->ether_type == hton16(ETHER_TYPE_802_1X)) {
++				uint8 prio = (uint8)PKTPRIO(txp);
++
++				/* Restore to original priority for 802.1X packet */
++				if (prio == PRIO_8021D_NC) {
++					PKTSETPRIO(txp, dhdp->prio_8021x);
++				}
++			}
++#endif /* DHD_LOSSLESS_ROAMING */
++
++			/* Attempt to transfer packet over flow ring */
++			ret = dhd_prot_txdata(bus->dhd, txp, flow_ring_node->flow_info.ifindex);
++			if (ret != BCME_OK) { /* may not have resources in flow ring */
++				DHD_INFO(("%s: Reinserrt %d\n", __FUNCTION__, ret));
++				dhd_prot_txdata_write_flush(bus->dhd, flow_id, FALSE);
++				/* reinsert at head */
++				dhd_flow_queue_reinsert(bus->dhd, queue, txp);
++				DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++
++				/* If we are able to requeue back, return success */
++				return BCME_OK;
++			}
++		}
++
++		dhd_prot_txdata_write_flush(bus->dhd, flow_id, FALSE);
++
++		DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++	}
++
++	return ret;
++} /* dhd_bus_schedule_queue */
++
++/** Sends an (ethernet) data frame (in 'txp') to the dongle. Callee disposes of txp. */
++int BCMFASTPATH
++dhd_bus_txdata(struct dhd_bus *bus, void *txp, uint8 ifidx)
++{
++	uint16 flowid;
++#ifdef IDLE_TX_FLOW_MGMT
++	uint8	node_status;
++#endif /* IDLE_TX_FLOW_MGMT */
++	flow_queue_t *queue;
++	flow_ring_node_t *flow_ring_node;
++	unsigned long flags;
++	int ret = BCME_OK;
++	void *txp_pend = NULL;
++
++	if (!bus->dhd->flowid_allocator) {
++		DHD_ERROR(("%s: Flow ring not intited yet  \n", __FUNCTION__));
++		goto toss;
++	}
++
++	flowid = DHD_PKT_GET_FLOWID(txp);
++
++	flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid);
++
++	DHD_TRACE(("%s: pkt flowid %d, status %d active %d\n",
++		__FUNCTION__, flowid, flow_ring_node->status, flow_ring_node->active));
++
++	DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++	if ((flowid >= bus->dhd->num_flow_rings) ||
++#ifdef IDLE_TX_FLOW_MGMT
++		(!flow_ring_node->active))
++#else
++		(!flow_ring_node->active) ||
++		(flow_ring_node->status == FLOW_RING_STATUS_DELETE_PENDING) ||
++		(flow_ring_node->status == FLOW_RING_STATUS_STA_FREEING))
++#endif /* IDLE_TX_FLOW_MGMT */
++	{
++		DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++		DHD_INFO(("%s: Dropping pkt flowid %d, status %d active %d\n",
++			__FUNCTION__, flowid, flow_ring_node->status,
++			flow_ring_node->active));
++		ret = BCME_ERROR;
++			goto toss;
++	}
++
++#ifdef IDLE_TX_FLOW_MGMT
++	node_status = flow_ring_node->status;
++
++	/* handle diffrent status states here!! */
++	switch (node_status)
++	{
++		case FLOW_RING_STATUS_OPEN:
++
++			if (bus->enable_idle_flowring_mgmt) {
++				/* Move the node to the head of active list */
++				dhd_flow_ring_move_to_active_list_head(bus, flow_ring_node);
++			}
++			break;
++
++		case FLOW_RING_STATUS_SUSPENDED:
++			DHD_INFO(("Need to Initiate TX Flow resume\n"));
++			/* Issue resume_ring request */
++			dhd_bus_flow_ring_resume_request(bus,
++					flow_ring_node);
++			break;
++
++		case FLOW_RING_STATUS_CREATE_PENDING:
++		case FLOW_RING_STATUS_RESUME_PENDING:
++			/* Dont do anything here!! */
++			DHD_INFO(("Waiting for Flow create/resume! status is %u\n",
++				node_status));
++			break;
++
++		case FLOW_RING_STATUS_DELETE_PENDING:
++		default:
++			DHD_ERROR(("Dropping packet!! flowid %u status is %u\n",
++				flowid, node_status));
++			/* error here!! */
++			ret = BCME_ERROR;
++			DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++			goto toss;
++	}
++	/* Now queue the packet */
++#endif /* IDLE_TX_FLOW_MGMT */
++
++	queue = &flow_ring_node->queue; /* queue associated with flow ring */
++
++	if ((ret = dhd_flow_queue_enqueue(bus->dhd, queue, txp)) != BCME_OK)
++		txp_pend = txp;
++
++	DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++
++	if (flow_ring_node->status) {
++		DHD_INFO(("%s: Enq pkt flowid %d, status %d active %d\n",
++		    __FUNCTION__, flowid, flow_ring_node->status,
++		    flow_ring_node->active));
++		if (txp_pend) {
++			txp = txp_pend;
++			goto toss;
++		}
++		return BCME_OK;
++	}
++	ret = dhd_bus_schedule_queue(bus, flowid, FALSE); /* from queue to flowring */
++
++	/* If we have anything pending, try to push into q */
++	if (txp_pend) {
++		DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++
++		if ((ret = dhd_flow_queue_enqueue(bus->dhd, queue, txp_pend)) != BCME_OK) {
++			DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++			txp = txp_pend;
++			goto toss;
++		}
++
++		DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++	}
++
++	return ret;
++
++toss:
++	DHD_INFO(("%s: Toss %d\n", __FUNCTION__, ret));
++/* for EFI, pass the 'send' flag as false, to avoid enqueuing the failed tx pkt
++* into the Tx done queue
++*/
++#ifdef DHD_EFI
++	PKTCFREE(bus->dhd->osh, txp, FALSE);
++#else
++	PKTCFREE(bus->dhd->osh, txp, TRUE);
++#endif
++	return ret;
++} /* dhd_bus_txdata */
++
++
++void
++dhd_bus_stop_queue(struct dhd_bus *bus)
++{
++	dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, ON);
++	bus->bus_flowctrl = TRUE;
++}
++
++void
++dhd_bus_start_queue(struct dhd_bus *bus)
++{
++	dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, OFF);
++	bus->bus_flowctrl = TRUE;
++}
++
++/* Device console input function */
++int dhd_bus_console_in(dhd_pub_t *dhd, uchar *msg, uint msglen)
++{
++	dhd_bus_t *bus = dhd->bus;
++	uint32 addr, val;
++	int rv;
++	/* Address could be zero if CONSOLE := 0 in dongle Makefile */
++	if (bus->console_addr == 0)
++		return BCME_UNSUPPORTED;
++
++	/* Don't allow input if dongle is in reset */
++	if (bus->dhd->dongle_reset) {
++		return BCME_NOTREADY;
++	}
++
++	/* Zero cbuf_index */
++	addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf_idx);
++	val = htol32(0);
++	if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0)
++		goto done;
++
++	/* Write message into cbuf */
++	addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf);
++	if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)msg, msglen)) < 0)
++		goto done;
++
++	/* Write length into vcons_in */
++	addr = bus->console_addr + OFFSETOF(hnd_cons_t, vcons_in);
++	val = htol32(msglen);
++	if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0)
++		goto done;
++
++	/* generate an interrupt to dongle to indicate that it needs to process cons command */
++	dhdpcie_send_mb_data(bus, H2D_HOST_CONS_INT);
++done:
++	return rv;
++} /* dhd_bus_console_in */
++
++/**
++ * Called on frame reception, the frame was received from the dongle on interface 'ifidx' and is
++ * contained in 'pkt'. Processes rx frame, forwards up the layer to netif.
++ */
++void BCMFASTPATH
++dhd_bus_rx_frame(struct dhd_bus *bus, void* pkt, int ifidx, uint pkt_count)
++{
++	dhd_rx_frame(bus->dhd, ifidx, pkt, pkt_count, 0);
++}
++
++/** 'offset' is a backplane address */
++void
++dhdpcie_bus_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data)
++{
++	W_REG(bus->dhd->osh, (volatile uint8 *)(bus->tcm + offset), data);
++}
++
++uint8
++dhdpcie_bus_rtcm8(dhd_bus_t *bus, ulong offset)
++{
++	volatile uint8 data;
++	data = R_REG(bus->dhd->osh, (volatile uint8 *)(bus->tcm + offset));
++	return data;
++}
++
++void
++dhdpcie_bus_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data)
++{
++	W_REG(bus->dhd->osh, (volatile uint32 *)(bus->tcm + offset), data);
++}
++void
++dhdpcie_bus_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data)
++{
++	W_REG(bus->dhd->osh, (volatile uint16 *)(bus->tcm + offset), data);
++}
++#ifdef DHD_SUPPORT_64BIT
++void
++dhdpcie_bus_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data)
++{
++	W_REG(bus->dhd->osh, (volatile uint64 *)(bus->tcm + offset), data);
++}
++#endif /* DHD_SUPPORT_64BIT */
++
++uint16
++dhdpcie_bus_rtcm16(dhd_bus_t *bus, ulong offset)
++{
++	volatile uint16 data;
++	data = R_REG(bus->dhd->osh, (volatile uint16 *)(bus->tcm + offset));
++	return data;
++}
++
++uint32
++dhdpcie_bus_rtcm32(dhd_bus_t *bus, ulong offset)
++{
++	volatile uint32 data;
++	data = R_REG(bus->dhd->osh, (volatile uint32 *)(bus->tcm + offset));
++	return data;
++}
++
++#ifdef DHD_SUPPORT_64BIT
++uint64
++dhdpcie_bus_rtcm64(dhd_bus_t *bus, ulong offset)
++{
++	volatile uint64 data;
++	data = R_REG(bus->dhd->osh, (volatile uint64 *)(bus->tcm + offset));
++	return data;
++}
++#endif /* DHD_SUPPORT_64BIT */
++
++/** A snippet of dongle memory is shared between host and dongle */
++void
++dhd_bus_cmn_writeshared(dhd_bus_t *bus, void *data, uint32 len, uint8 type, uint16 ringid)
++{
++	uint64 long_data;
++	uintptr tcm_offset;
++
++	DHD_INFO(("%s: writing to dongle type %d len %d\n", __FUNCTION__, type, len));
++
++	if (bus->is_linkdown) {
++		DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__));
++		return;
++	}
++
++	switch (type) {
++		case D2H_DMA_SCRATCH_BUF:
++		{
++			pciedev_shared_t *sh = (pciedev_shared_t*)bus->shared_addr;
++			long_data = HTOL64(*(uint64 *)data);
++			tcm_offset = (uintptr)&(sh->host_dma_scratch_buffer);
++			dhdpcie_bus_membytes(bus, TRUE,
++				(ulong)tcm_offset, (uint8*) &long_data, len);
++			if (dhd_msg_level & DHD_INFO_VAL) {
++				prhex(__FUNCTION__, data, len);
++			}
++			break;
++		}
++
++		case D2H_DMA_SCRATCH_BUF_LEN :
++		{
++			pciedev_shared_t *sh = (pciedev_shared_t*)bus->shared_addr;
++			tcm_offset = (uintptr)&(sh->host_dma_scratch_buffer_len);
++			dhdpcie_bus_wtcm32(bus,
++				(ulong)tcm_offset, (uint32) HTOL32(*(uint32 *)data));
++			if (dhd_msg_level & DHD_INFO_VAL) {
++				prhex(__FUNCTION__, data, len);
++			}
++			break;
++		}
++
++		case H2D_DMA_INDX_WR_BUF:
++		{
++			pciedev_shared_t *shmem = (pciedev_shared_t *)bus->pcie_sh;
++
++			long_data = HTOL64(*(uint64 *)data);
++			tcm_offset = (uintptr)shmem->rings_info_ptr;
++			tcm_offset += OFFSETOF(ring_info_t, h2d_w_idx_hostaddr);
++			dhdpcie_bus_membytes(bus, TRUE,
++				(ulong)tcm_offset, (uint8*) &long_data, len);
++			if (dhd_msg_level & DHD_INFO_VAL) {
++				prhex(__FUNCTION__, data, len);
++			}
++			break;
++		}
++
++		case H2D_DMA_INDX_RD_BUF:
++		{
++			pciedev_shared_t *shmem = (pciedev_shared_t *)bus->pcie_sh;
++			long_data = HTOL64(*(uint64 *)data);
++			tcm_offset = (uintptr)shmem->rings_info_ptr;
++			tcm_offset += OFFSETOF(ring_info_t, h2d_r_idx_hostaddr);
++			dhdpcie_bus_membytes(bus, TRUE,
++				(ulong)tcm_offset, (uint8*) &long_data, len);
++			if (dhd_msg_level & DHD_INFO_VAL) {
++				prhex(__FUNCTION__, data, len);
++			}
++			break;
++		}
++
++		case D2H_DMA_INDX_WR_BUF:
++		{
++			pciedev_shared_t *shmem = (pciedev_shared_t *)bus->pcie_sh;
++			long_data = HTOL64(*(uint64 *)data);
++			tcm_offset = (uintptr)shmem->rings_info_ptr;
++			tcm_offset += OFFSETOF(ring_info_t, d2h_w_idx_hostaddr);
++			dhdpcie_bus_membytes(bus, TRUE,
++				(ulong)tcm_offset, (uint8*) &long_data, len);
++			if (dhd_msg_level & DHD_INFO_VAL) {
++				prhex(__FUNCTION__, data, len);
++			}
++			break;
++		}
++
++		case D2H_DMA_INDX_RD_BUF:
++		{
++			pciedev_shared_t *shmem = (pciedev_shared_t *)bus->pcie_sh;
++			long_data = HTOL64(*(uint64 *)data);
++			tcm_offset = (uintptr)shmem->rings_info_ptr;
++			tcm_offset += OFFSETOF(ring_info_t, d2h_r_idx_hostaddr);
++			dhdpcie_bus_membytes(bus, TRUE,
++				(ulong)tcm_offset, (uint8*) &long_data, len);
++			if (dhd_msg_level & DHD_INFO_VAL) {
++				prhex(__FUNCTION__, data, len);
++			}
++			break;
++		}
++
++		case H2D_IFRM_INDX_WR_BUF:
++		{
++			pciedev_shared_t *shmem = (pciedev_shared_t *)bus->pcie_sh;
++
++			long_data = HTOL64(*(uint64 *)data);
++			tcm_offset = (uintptr)shmem->rings_info_ptr;
++			tcm_offset += OFFSETOF(ring_info_t, ifrm_w_idx_hostaddr);
++			dhdpcie_bus_membytes(bus, TRUE,
++				(ulong)tcm_offset, (uint8*) &long_data, len);
++			if (dhd_msg_level & DHD_INFO_VAL) {
++				prhex(__FUNCTION__, data, len);
++			}
++			break;
++		}
++
++		case RING_ITEM_LEN :
++			tcm_offset = bus->ring_sh[ringid].ring_mem_addr;
++			tcm_offset += OFFSETOF(ring_mem_t, len_items);
++			dhdpcie_bus_wtcm16(bus,
++				(ulong)tcm_offset, (uint16) HTOL16(*(uint16 *)data));
++			break;
++
++		case RING_MAX_ITEMS :
++			tcm_offset = bus->ring_sh[ringid].ring_mem_addr;
++			tcm_offset += OFFSETOF(ring_mem_t, max_item);
++			dhdpcie_bus_wtcm16(bus,
++				(ulong)tcm_offset, (uint16) HTOL16(*(uint16 *)data));
++			break;
++
++		case RING_BUF_ADDR :
++			long_data = HTOL64(*(uint64 *)data);
++			tcm_offset = bus->ring_sh[ringid].ring_mem_addr;
++			tcm_offset += OFFSETOF(ring_mem_t, base_addr);
++			dhdpcie_bus_membytes(bus, TRUE,
++				(ulong)tcm_offset, (uint8 *) &long_data, len);
++			if (dhd_msg_level & DHD_INFO_VAL) {
++				prhex(__FUNCTION__, data, len);
++			}
++			break;
++
++		case RING_WR_UPD :
++			tcm_offset = bus->ring_sh[ringid].ring_state_w;
++			dhdpcie_bus_wtcm16(bus,
++				(ulong)tcm_offset, (uint16) HTOL16(*(uint16 *)data));
++			break;
++
++		case RING_RD_UPD :
++			tcm_offset = bus->ring_sh[ringid].ring_state_r;
++			dhdpcie_bus_wtcm16(bus,
++				(ulong)tcm_offset, (uint16) HTOL16(*(uint16 *)data));
++			break;
++
++		case D2H_MB_DATA:
++			dhdpcie_bus_wtcm32(bus, bus->d2h_mb_data_ptr_addr,
++				(uint32) HTOL32(*(uint32 *)data));
++			break;
++
++		case H2D_MB_DATA:
++			dhdpcie_bus_wtcm32(bus, bus->h2d_mb_data_ptr_addr,
++				(uint32) HTOL32(*(uint32 *)data));
++			break;
++
++		case HOST_API_VERSION:
++		{
++			pciedev_shared_t *sh = (pciedev_shared_t*) bus->shared_addr;
++			tcm_offset = (uintptr)sh + OFFSETOF(pciedev_shared_t, host_cap);
++			dhdpcie_bus_wtcm32(bus,
++				(ulong)tcm_offset, (uint32) HTOL32(*(uint32 *)data));
++			break;
++		}
++
++		case DNGL_TO_HOST_TRAP_ADDR:
++		{
++			pciedev_shared_t *sh = (pciedev_shared_t*) bus->shared_addr;
++			long_data = HTOL64(*(uint64 *)data);
++			tcm_offset = (uintptr)&(sh->host_trap_addr);
++			dhdpcie_bus_membytes(bus, TRUE,
++				(ulong)tcm_offset, (uint8*) &long_data, len);
++			break;
++		}
++
++#ifdef HOFFLOAD_MODULES
++		case WRT_HOST_MODULE_ADDR:
++		{
++			pciedev_shared_t *sh = (pciedev_shared_t*) bus->shared_addr;
++			long_data = HTOL64(*(uint64 *)data);
++			tcm_offset = (uintptr)&(sh->hoffload_addr);
++			dhdpcie_bus_membytes(bus, TRUE,
++				(ulong)tcm_offset, (uint8*) &long_data, len);
++			break;
++		}
++#endif
++		default:
++			break;
++	}
++} /* dhd_bus_cmn_writeshared */
++
++/** A snippet of dongle memory is shared between host and dongle */
++void
++dhd_bus_cmn_readshared(dhd_bus_t *bus, void* data, uint8 type, uint16 ringid)
++{
++	ulong tcm_offset;
++
++	switch (type) {
++		case RING_WR_UPD :
++			tcm_offset = bus->ring_sh[ringid].ring_state_w;
++			*(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, tcm_offset));
++			break;
++		case RING_RD_UPD :
++			tcm_offset = bus->ring_sh[ringid].ring_state_r;
++			*(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, tcm_offset));
++			break;
++		case TOTAL_LFRAG_PACKET_CNT :
++		{
++			pciedev_shared_t *sh = (pciedev_shared_t*)bus->shared_addr;
++			*(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus,
++				(ulong)(uintptr) &sh->total_lfrag_pkt_cnt));
++			break;
++		}
++		case H2D_MB_DATA:
++			*(uint32*)data = LTOH32(dhdpcie_bus_rtcm32(bus, bus->h2d_mb_data_ptr_addr));
++			break;
++		case D2H_MB_DATA:
++			*(uint32*)data = LTOH32(dhdpcie_bus_rtcm32(bus, bus->d2h_mb_data_ptr_addr));
++			break;
++		case MAX_HOST_RXBUFS :
++		{
++			pciedev_shared_t *sh = (pciedev_shared_t*)bus->shared_addr;
++			*(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus,
++				(ulong)(uintptr) &sh->max_host_rxbufs));
++			break;
++		}
++		default :
++			break;
++	}
++}
++
++uint32 dhd_bus_get_sharedflags(dhd_bus_t *bus)
++{
++	return ((pciedev_shared_t*)bus->pcie_sh)->flags;
++}
++
++void
++dhd_bus_clearcounts(dhd_pub_t *dhdp)
++{
++}
++
++int
++dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
++                 void *params, int plen, void *arg, int len, bool set)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	const bcm_iovar_t *vi = NULL;
++	int bcmerror = BCME_UNSUPPORTED;
++	int val_size;
++	uint32 actionid;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	ASSERT(name);
++	ASSERT(len >= 0);
++
++	/* Get MUST have return space */
++	ASSERT(set || (arg && len));
++
++	/* Set does NOT take qualifiers */
++	ASSERT(!set || (!params && !plen));
++
++	DHD_INFO(("%s: %s %s, len %d plen %d\n", __FUNCTION__,
++	         name, (set ? "set" : "get"), len, plen));
++
++	/* Look up var locally; if not found pass to host driver */
++	if ((vi = bcm_iovar_lookup(dhdpcie_iovars, name)) == NULL) {
++		goto exit;
++	}
++
++
++	/* set up 'params' pointer in case this is a set command so that
++	 * the convenience int and bool code can be common to set and get
++	 */
++	if (params == NULL) {
++		params = arg;
++		plen = len;
++	}
++
++	if (vi->type == IOVT_VOID)
++		val_size = 0;
++	else if (vi->type == IOVT_BUFFER)
++		val_size = len;
++	else
++		/* all other types are integer sized */
++		val_size = sizeof(int);
++
++	actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
++	bcmerror = dhdpcie_bus_doiovar(bus, vi, actionid, name, params, plen, arg, len, val_size);
++
++exit:
++	return bcmerror;
++} /* dhd_bus_iovar_op */
++
++#ifdef BCM_BUZZZ
++#include <bcm_buzzz.h>
++
++int
++dhd_buzzz_dump_cntrs(char *p, uint32 *core, uint32 *log,
++	const int num_counters)
++{
++	int bytes = 0;
++	uint32 ctr;
++	uint32 curr[BCM_BUZZZ_COUNTERS_MAX], prev[BCM_BUZZZ_COUNTERS_MAX];
++	uint32 delta[BCM_BUZZZ_COUNTERS_MAX];
++
++	/* Compute elapsed counter values per counter event type */
++	for (ctr = 0U; ctr < num_counters; ctr++) {
++		prev[ctr] = core[ctr];
++		curr[ctr] = *log++;
++		core[ctr] = curr[ctr];  /* saved for next log */
++
++		if (curr[ctr] < prev[ctr])
++			delta[ctr] = curr[ctr] + (~0U - prev[ctr]);
++		else
++			delta[ctr] = (curr[ctr] - prev[ctr]);
++
++		bytes += sprintf(p + bytes, "%12u ", delta[ctr]);
++	}
++
++	return bytes;
++}
++
++typedef union cm3_cnts { /* export this in bcm_buzzz.h */
++	uint32 u32;
++	uint8  u8[4];
++	struct {
++		uint8 cpicnt;
++		uint8 exccnt;
++		uint8 sleepcnt;
++		uint8 lsucnt;
++	};
++} cm3_cnts_t;
++
++int
++dhd_bcm_buzzz_dump_cntrs6(char *p, uint32 *core, uint32 *log)
++{
++	int bytes = 0;
++
++	uint32 cyccnt, instrcnt;
++	cm3_cnts_t cm3_cnts;
++	uint8 foldcnt;
++
++	{   /* 32bit cyccnt */
++		uint32 curr, prev, delta;
++		prev = core[0]; curr = *log++; core[0] = curr;
++		if (curr < prev)
++			delta = curr + (~0U - prev);
++		else
++			delta = (curr - prev);
++
++		bytes += sprintf(p + bytes, "%12u ", delta);
++		cyccnt = delta;
++	}
++
++	{	/* Extract the 4 cnts: cpi, exc, sleep and lsu */
++		int i;
++		uint8 max8 = ~0;
++		cm3_cnts_t curr, prev, delta;
++		prev.u32 = core[1]; curr.u32 = * log++; core[1] = curr.u32;
++		for (i = 0; i < 4; i++) {
++			if (curr.u8[i] < prev.u8[i])
++				delta.u8[i] = curr.u8[i] + (max8 - prev.u8[i]);
++			else
++				delta.u8[i] = (curr.u8[i] - prev.u8[i]);
++			bytes += sprintf(p + bytes, "%4u ", delta.u8[i]);
++		}
++		cm3_cnts.u32 = delta.u32;
++	}
++
++	{   /* Extract the foldcnt from arg0 */
++		uint8 curr, prev, delta, max8 = ~0;
++		bcm_buzzz_arg0_t arg0; arg0.u32 = *log;
++		prev = core[2]; curr = arg0.klog.cnt; core[2] = curr;
++		if (curr < prev)
++			delta = curr + (max8 - prev);
++		else
++			delta = (curr - prev);
++		bytes += sprintf(p + bytes, "%4u ", delta);
++		foldcnt = delta;
++	}
++
++	instrcnt = cyccnt - (cm3_cnts.u8[0] + cm3_cnts.u8[1] + cm3_cnts.u8[2]
++		                 + cm3_cnts.u8[3]) + foldcnt;
++	if (instrcnt > 0xFFFFFF00)
++		bytes += sprintf(p + bytes, "[%10s] ", "~");
++	else
++		bytes += sprintf(p + bytes, "[%10u] ", instrcnt);
++	return bytes;
++}
++
++int
++dhd_buzzz_dump_log(char *p, uint32 *core, uint32 *log, bcm_buzzz_t *buzzz)
++{
++	int bytes = 0;
++	bcm_buzzz_arg0_t arg0;
++	static uint8 * fmt[] = BCM_BUZZZ_FMT_STRINGS;
++
++	if (buzzz->counters == 6) {
++		bytes += dhd_bcm_buzzz_dump_cntrs6(p, core, log);
++		log += 2; /* 32bit cyccnt + (4 x 8bit) CM3 */
++	} else {
++		bytes += dhd_buzzz_dump_cntrs(p, core, log, buzzz->counters);
++		log += buzzz->counters; /* (N x 32bit) CR4=3, CA7=4 */
++	}
++
++	/* Dump the logged arguments using the registered formats */
++	arg0.u32 = *log++;
++
++	switch (arg0.klog.args) {
++		case 0:
++			bytes += sprintf(p + bytes, fmt[arg0.klog.id]);
++			break;
++		case 1:
++		{
++			uint32 arg1 = *log++;
++			bytes += sprintf(p + bytes, fmt[arg0.klog.id], arg1);
++			break;
++		}
++		case 2:
++		{
++			uint32 arg1, arg2;
++			arg1 = *log++; arg2 = *log++;
++			bytes += sprintf(p + bytes, fmt[arg0.klog.id], arg1, arg2);
++			break;
++		}
++		case 3:
++		{
++			uint32 arg1, arg2, arg3;
++			arg1 = *log++; arg2 = *log++; arg3 = *log++;
++			bytes += sprintf(p + bytes, fmt[arg0.klog.id], arg1, arg2, arg3);
++			break;
++		}
++		case 4:
++		{
++			uint32 arg1, arg2, arg3, arg4;
++			arg1 = *log++; arg2 = *log++;
++			arg3 = *log++; arg4 = *log++;
++			bytes += sprintf(p + bytes, fmt[arg0.klog.id], arg1, arg2, arg3, arg4);
++			break;
++		}
++		default:
++			printf("%s: Maximum one argument supported\n", __FUNCTION__);
++			break;
++	}
++
++	bytes += sprintf(p + bytes, "\n");
++
++	return bytes;
++}
++
++void dhd_buzzz_dump(bcm_buzzz_t *buzzz_p, void *buffer_p, char *p)
++{
++	int i;
++	uint32 total, part1, part2, log_sz, core[BCM_BUZZZ_COUNTERS_MAX];
++	void * log;
++
++	for (i = 0; i < BCM_BUZZZ_COUNTERS_MAX; i++) {
++		core[i] = 0;
++	}
++
++	log_sz = buzzz_p->log_sz;
++
++	part1 = ((uint32)buzzz_p->cur - (uint32)buzzz_p->log) / log_sz;
++
++	if (buzzz_p->wrap == TRUE) {
++		part2 = ((uint32)buzzz_p->end - (uint32)buzzz_p->cur) / log_sz;
++		total = (buzzz_p->buffer_sz - BCM_BUZZZ_LOGENTRY_MAXSZ) / log_sz;
++	} else {
++		part2 = 0U;
++		total = buzzz_p->count;
++	}
++
++	if (total == 0U) {
++		printf("%s: bcm_buzzz_dump total<%u> done\n", __FUNCTION__, total);
++		return;
++	} else {
++		printf("%s: bcm_buzzz_dump total<%u> : part2<%u> + part1<%u>\n", __FUNCTION__,
++		       total, part2, part1);
++	}
++
++	if (part2) {   /* with wrap */
++		log = (void*)((size_t)buffer_p + (buzzz_p->cur - buzzz_p->log));
++		while (part2--) {   /* from cur to end : part2 */
++			p[0] = '\0';
++			dhd_buzzz_dump_log(p, core, (uint32 *)log, buzzz_p);
++			printf("%s", p);
++			log = (void*)((size_t)log + buzzz_p->log_sz);
++		}
++	}
++
++	log = (void*)buffer_p;
++	while (part1--) {
++		p[0] = '\0';
++		dhd_buzzz_dump_log(p, core, (uint32 *)log, buzzz_p);
++		printf("%s", p);
++		log = (void*)((size_t)log + buzzz_p->log_sz);
++	}
++
++	printf("%s: bcm_buzzz_dump done.\n", __FUNCTION__);
++}
++
++int dhd_buzzz_dump_dngl(dhd_bus_t *bus)
++{
++	bcm_buzzz_t * buzzz_p = NULL;
++	void * buffer_p = NULL;
++	char * page_p = NULL;
++	pciedev_shared_t *sh;
++	int ret = 0;
++
++	if (bus->dhd->busstate != DHD_BUS_DATA) {
++		return BCME_UNSUPPORTED;
++	}
++	if ((page_p = (char *)MALLOC(bus->dhd->osh, 4096)) == NULL) {
++		printf("%s: Page memory allocation failure\n", __FUNCTION__);
++		goto done;
++	}
++	if ((buzzz_p = MALLOC(bus->dhd->osh, sizeof(bcm_buzzz_t))) == NULL) {
++		printf("%s: BCM BUZZZ memory allocation failure\n", __FUNCTION__);
++		goto done;
++	}
++
++	ret = dhdpcie_readshared(bus);
++	if (ret < 0) {
++		DHD_ERROR(("%s :Shared area read failed \n", __FUNCTION__));
++		goto done;
++	}
++
++	sh = bus->pcie_sh;
++
++	DHD_INFO(("%s buzzz:%08x\n", __FUNCTION__, sh->buzz_dbg_ptr));
++
++	if (sh->buzz_dbg_ptr != 0U) {	/* Fetch and display dongle BUZZZ Trace */
++
++		dhdpcie_bus_membytes(bus, FALSE, (ulong)sh->buzz_dbg_ptr,
++		                     (uint8 *)buzzz_p, sizeof(bcm_buzzz_t));
++
++		printf("BUZZZ[0x%08x]: log<0x%08x> cur<0x%08x> end<0x%08x> "
++			"count<%u> status<%u> wrap<%u>\n"
++			"cpu<0x%02X> counters<%u> group<%u> buffer_sz<%u> log_sz<%u>\n",
++			(int)sh->buzz_dbg_ptr,
++			(int)buzzz_p->log, (int)buzzz_p->cur, (int)buzzz_p->end,
++			buzzz_p->count, buzzz_p->status, buzzz_p->wrap,
++			buzzz_p->cpu_idcode, buzzz_p->counters, buzzz_p->group,
++			buzzz_p->buffer_sz, buzzz_p->log_sz);
++
++		if (buzzz_p->count == 0) {
++			printf("%s: Empty dongle BUZZZ trace\n\n", __FUNCTION__);
++			goto done;
++		}
++
++		/* Allocate memory for trace buffer and format strings */
++		buffer_p = MALLOC(bus->dhd->osh, buzzz_p->buffer_sz);
++		if (buffer_p == NULL) {
++			printf("%s: Buffer memory allocation failure\n", __FUNCTION__);
++			goto done;
++		}
++
++		/* Fetch the trace. format strings are exported via bcm_buzzz.h */
++		dhdpcie_bus_membytes(bus, FALSE, (uint32)buzzz_p->log,   /* Trace */
++		                     (uint8 *)buffer_p, buzzz_p->buffer_sz);
++
++		/* Process and display the trace using formatted output */
++
++		{
++			int ctr;
++			for (ctr = 0; ctr < buzzz_p->counters; ctr++) {
++				printf("<Evt[%02X]> ", buzzz_p->eventid[ctr]);
++			}
++			printf("<code execution point>\n");
++		}
++
++		dhd_buzzz_dump(buzzz_p, buffer_p, page_p);
++
++		printf("%s: ----- End of dongle BCM BUZZZ Trace -----\n\n", __FUNCTION__);
++
++		MFREE(bus->dhd->osh, buffer_p, buzzz_p->buffer_sz); buffer_p = NULL;
++	}
++
++done:
++
++	if (page_p)   MFREE(bus->dhd->osh, page_p, 4096);
++	if (buzzz_p)  MFREE(bus->dhd->osh, buzzz_p, sizeof(bcm_buzzz_t));
++	if (buffer_p) MFREE(bus->dhd->osh, buffer_p, buzzz_p->buffer_sz);
++
++	return BCME_OK;
++}
++#endif /* BCM_BUZZZ */
++
++#define PCIE_GEN2(sih) ((BUSTYPE((sih)->bustype) == PCI_BUS) &&	\
++	((sih)->buscoretype == PCIE2_CORE_ID))
++
++int
++dhd_bus_devreset(dhd_pub_t *dhdp, uint8 flag)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	int bcmerror = 0;
++	unsigned long flags;
++#ifdef CONFIG_ARCH_MSM
++	int retry = POWERUP_MAX_RETRY;
++#endif /* CONFIG_ARCH_MSM */
++
++	if (dhd_download_fw_on_driverload) {
++		bcmerror = dhd_bus_start(dhdp);
++	} else {
++		if (flag == TRUE) { /* Turn off WLAN */
++			/* Removing Power */
++			DHD_ERROR(("%s: == Power OFF ==\n", __FUNCTION__));
++
++			bus->dhd->up = FALSE;
++
++			if (bus->dhd->busstate != DHD_BUS_DOWN) {
++				dhdpcie_advertise_bus_cleanup(bus->dhd);
++				if (bus->intr) {
++					dhdpcie_bus_intr_disable(bus);
++					dhdpcie_free_irq(bus);
++				}
++#ifdef BCMPCIE_OOB_HOST_WAKE
++				/* Clean up any pending host wake IRQ */
++				dhd_bus_oob_intr_set(bus->dhd, FALSE);
++				dhd_bus_oob_intr_unregister(bus->dhd);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++				dhd_os_wd_timer(dhdp, 0);
++				dhd_bus_stop(bus, TRUE);
++				dhd_prot_reset(dhdp);
++				dhd_clear(dhdp);
++				dhd_bus_release_dongle(bus);
++				dhdpcie_bus_free_resource(bus);
++				bcmerror = dhdpcie_bus_disable_device(bus);
++				if (bcmerror) {
++					DHD_ERROR(("%s: dhdpcie_bus_disable_device: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++#ifdef CONFIG_ARCH_MSM
++				bcmerror = dhdpcie_bus_clock_stop(bus);
++				if (bcmerror) {
++					DHD_ERROR(("%s: host clock stop failed: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++#endif /* CONFIG_ARCH_MSM */
++				DHD_GENERAL_LOCK(bus->dhd, flags);
++				bus->dhd->busstate = DHD_BUS_DOWN;
++				DHD_GENERAL_UNLOCK(bus->dhd, flags);
++			} else {
++				if (bus->intr) {
++					dhdpcie_free_irq(bus);
++				}
++#ifdef BCMPCIE_OOB_HOST_WAKE
++				/* Clean up any pending host wake IRQ */
++				dhd_bus_oob_intr_set(bus->dhd, FALSE);
++				dhd_bus_oob_intr_unregister(bus->dhd);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++				dhd_dpc_kill(bus->dhd);
++				dhd_prot_reset(dhdp);
++				dhd_clear(dhdp);
++				dhd_bus_release_dongle(bus);
++				dhdpcie_bus_free_resource(bus);
++				bcmerror = dhdpcie_bus_disable_device(bus);
++				if (bcmerror) {
++					DHD_ERROR(("%s: dhdpcie_bus_disable_device: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++
++#ifdef CONFIG_ARCH_MSM
++				bcmerror = dhdpcie_bus_clock_stop(bus);
++				if (bcmerror) {
++					DHD_ERROR(("%s: host clock stop failed: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++#endif  /* CONFIG_ARCH_MSM */
++			}
++
++			bus->dhd->dongle_reset = TRUE;
++			DHD_ERROR(("%s:  WLAN OFF Done\n", __FUNCTION__));
++
++		} else { /* Turn on WLAN */
++			if (bus->dhd->busstate == DHD_BUS_DOWN) {
++				/* Powering On */
++				DHD_ERROR(("%s: == Power ON ==\n", __FUNCTION__));
++#ifdef CONFIG_ARCH_MSM
++				while (--retry) {
++					bcmerror = dhdpcie_bus_clock_start(bus);
++					if (!bcmerror) {
++						DHD_ERROR(("%s: dhdpcie_bus_clock_start OK\n",
++							__FUNCTION__));
++						break;
++					} else {
++						OSL_SLEEP(10);
++					}
++				}
++
++				if (bcmerror && !retry) {
++					DHD_ERROR(("%s: host pcie clock enable failed: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++#endif /* CONFIG_ARCH_MSM */
++				bus->is_linkdown = 0;
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++				bus->read_shm_fail = FALSE;
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++				bcmerror = dhdpcie_bus_enable_device(bus);
++				if (bcmerror) {
++					DHD_ERROR(("%s: host configuration restore failed: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++
++				bcmerror = dhdpcie_bus_alloc_resource(bus);
++				if (bcmerror) {
++					DHD_ERROR(("%s: dhdpcie_bus_resource_alloc failed: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++
++				bcmerror = dhdpcie_bus_dongle_attach(bus);
++				if (bcmerror) {
++					DHD_ERROR(("%s: dhdpcie_bus_dongle_attach failed: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++
++				bcmerror = dhd_bus_request_irq(bus);
++				if (bcmerror) {
++					DHD_ERROR(("%s: dhd_bus_request_irq failed: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++
++				bus->dhd->dongle_reset = FALSE;
++
++				bcmerror = dhd_bus_start(dhdp);
++				if (bcmerror) {
++					DHD_ERROR(("%s: dhd_bus_start: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++
++				bus->dhd->up = TRUE;
++				DHD_ERROR(("%s: WLAN Power On Done\n", __FUNCTION__));
++			} else {
++				DHD_ERROR(("%s: what should we do here\n", __FUNCTION__));
++				goto done;
++			}
++		}
++	}
++
++done:
++	if (bcmerror) {
++		DHD_GENERAL_LOCK(bus->dhd, flags);
++		bus->dhd->busstate = DHD_BUS_DOWN;
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++	}
++
++	return bcmerror;
++}
++
++static int
++dhdpcie_bus_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, const char *name,
++                void *params, int plen, void *arg, int len, int val_size)
++{
++	int bcmerror = 0;
++	int32 int_val = 0;
++	int32 int_val2 = 0;
++	int32 int_val3 = 0;
++	bool bool_val = 0;
++
++	DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p len %d val_size %d\n",
++	           __FUNCTION__, actionid, name, params, plen, arg, len, val_size));
++
++	if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid))) != 0)
++		goto exit;
++
++	if (plen >= (int)sizeof(int_val))
++		bcopy(params, &int_val, sizeof(int_val));
++
++	if (plen >= (int)sizeof(int_val) * 2)
++		bcopy((void*)((uintptr)params + sizeof(int_val)), &int_val2, sizeof(int_val2));
++
++	if (plen >= (int)sizeof(int_val) * 3)
++		bcopy((void*)((uintptr)params + 2 * sizeof(int_val)), &int_val3, sizeof(int_val3));
++
++	bool_val = (int_val != 0) ? TRUE : FALSE;
++
++	/* Check if dongle is in reset. If so, only allow DEVRESET iovars */
++	if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
++	                                actionid == IOV_GVAL(IOV_DEVRESET))) {
++		bcmerror = BCME_NOTREADY;
++		goto exit;
++	}
++
++	switch (actionid) {
++
++
++	case IOV_SVAL(IOV_VARS):
++		bcmerror = dhdpcie_downloadvars(bus, arg, len);
++		break;
++	case IOV_SVAL(IOV_PCIE_LPBK):
++		bcmerror = dhdpcie_bus_lpback_req(bus, int_val);
++		break;
++
++	case IOV_SVAL(IOV_PCIE_DMAXFER): {
++		int int_val4 = 0;
++		if (plen >= (int)sizeof(int_val) * 4) {
++			bcopy((void*)((uintptr)params + 3 * sizeof(int_val)),
++				&int_val4, sizeof(int_val4));
++		}
++		bcmerror = dhdpcie_bus_dmaxfer_req(bus, int_val, int_val2, int_val3, int_val4);
++		break;
++	}
++
++#ifdef DEVICE_TX_STUCK_DETECT
++	case IOV_GVAL(IOV_DEVICE_TX_STUCK_DETECT):
++		int_val = bus->dev_tx_stuck_monitor;
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_SVAL(IOV_DEVICE_TX_STUCK_DETECT):
++		bus->dev_tx_stuck_monitor = (bool)int_val;
++		break;
++#endif /* DEVICE_TX_STUCK_DETECT */
++	case IOV_GVAL(IOV_PCIE_SUSPEND):
++		int_val = (bus->dhd->busstate == DHD_BUS_SUSPEND) ? 1 : 0;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_PCIE_SUSPEND):
++		if (bool_val) { /* Suspend */
++			int ret;
++			unsigned long flags;
++
++			/*
++			 * If some other context is busy, wait until they are done,
++			 * before starting suspend
++			 */
++			ret = dhd_os_busbusy_wait_condition(bus->dhd,
++				&bus->dhd->dhd_bus_busy_state, DHD_BUS_BUSY_IN_DHD_IOVAR);
++			if (ret == 0) {
++				DHD_ERROR(("%s:Wait Timedout, dhd_bus_busy_state = 0x%x\n",
++					__FUNCTION__, bus->dhd->dhd_bus_busy_state));
++				return BCME_BUSY;
++			}
++
++			DHD_GENERAL_LOCK(bus->dhd, flags);
++			DHD_BUS_BUSY_SET_SUSPEND_IN_PROGRESS(bus->dhd);
++			DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++			dhdpcie_bus_suspend(bus, TRUE);
++
++			DHD_GENERAL_LOCK(bus->dhd, flags);
++			DHD_BUS_BUSY_CLEAR_SUSPEND_IN_PROGRESS(bus->dhd);
++			dhd_os_busbusy_wake(bus->dhd);
++			DHD_GENERAL_UNLOCK(bus->dhd, flags);
++		} else { /* Resume */
++			unsigned long flags;
++			DHD_GENERAL_LOCK(bus->dhd, flags);
++			DHD_BUS_BUSY_SET_RESUME_IN_PROGRESS(bus->dhd);
++			DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++			dhdpcie_bus_suspend(bus, FALSE);
++
++			DHD_GENERAL_LOCK(bus->dhd, flags);
++			DHD_BUS_BUSY_CLEAR_RESUME_IN_PROGRESS(bus->dhd);
++			dhd_os_busbusy_wake(bus->dhd);
++			DHD_GENERAL_UNLOCK(bus->dhd, flags);
++		}
++		break;
++
++	case IOV_GVAL(IOV_MEMSIZE):
++		int_val = (int32)bus->ramsize;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++#ifdef BCM_BUZZZ
++	/* Dump dongle side buzzz trace to console */
++	case IOV_GVAL(IOV_BUZZZ_DUMP):
++		bcmerror = dhd_buzzz_dump_dngl(bus);
++		break;
++#endif /* BCM_BUZZZ */
++
++	case IOV_SVAL(IOV_SET_DOWNLOAD_STATE):
++		bcmerror = dhdpcie_bus_download_state(bus, bool_val);
++		break;
++
++	case IOV_GVAL(IOV_RAMSIZE):
++		int_val = (int32)bus->ramsize;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_RAMSIZE):
++		bus->ramsize = int_val;
++		bus->orig_ramsize = int_val;
++		break;
++
++	case IOV_GVAL(IOV_RAMSTART):
++		int_val = (int32)bus->dongle_ram_base;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_CC_NVMSHADOW):
++	{
++		struct bcmstrbuf dump_b;
++
++		bcm_binit(&dump_b, arg, len);
++		bcmerror = dhdpcie_cc_nvmshadow(bus, &dump_b);
++		break;
++	}
++
++	case IOV_GVAL(IOV_SLEEP_ALLOWED):
++		bool_val = bus->sleep_allowed;
++		bcopy(&bool_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_SLEEP_ALLOWED):
++		bus->sleep_allowed = bool_val;
++		break;
++
++	case IOV_GVAL(IOV_DONGLEISOLATION):
++		int_val = bus->dhd->dongle_isolation;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DONGLEISOLATION):
++		bus->dhd->dongle_isolation = bool_val;
++		break;
++
++	case IOV_GVAL(IOV_LTRSLEEPON_UNLOOAD):
++		int_val = bus->ltrsleep_on_unload;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_LTRSLEEPON_UNLOOAD):
++		bus->ltrsleep_on_unload = bool_val;
++		break;
++
++	case IOV_GVAL(IOV_DUMP_RINGUPD_BLOCK):
++	{
++		struct bcmstrbuf dump_b;
++		bcm_binit(&dump_b, arg, len);
++		bcmerror = dhd_prot_ringupd_dump(bus->dhd, &dump_b);
++		break;
++	}
++	case IOV_GVAL(IOV_DMA_RINGINDICES):
++	{	int h2d_support, d2h_support;
++
++		d2h_support = bus->dhd->dma_d2h_ring_upd_support ? 1 : 0;
++		h2d_support = bus->dhd->dma_h2d_ring_upd_support ? 1 : 0;
++		int_val = d2h_support | (h2d_support << 1);
++		bcopy(&int_val, arg, sizeof(int_val));
++		break;
++	}
++	case IOV_SVAL(IOV_DMA_RINGINDICES):
++		/* Can change it only during initialization/FW download */
++		if (bus->dhd->busstate == DHD_BUS_DOWN) {
++			if ((int_val > 3) || (int_val < 0)) {
++				DHD_ERROR(("%s: Bad argument. Possible values: 0, 1, 2 & 3\n", __FUNCTION__));
++				bcmerror = BCME_BADARG;
++			} else {
++				bus->dhd->dma_d2h_ring_upd_support = (int_val & 1) ? TRUE : FALSE;
++				bus->dhd->dma_h2d_ring_upd_support = (int_val & 2) ? TRUE : FALSE;
++				bus->dhd->dma_ring_upd_overwrite = TRUE;
++			}
++		} else {
++			DHD_ERROR(("%s: Can change only when bus down (before FW download)\n",
++				__FUNCTION__));
++			bcmerror = BCME_NOTDOWN;
++		}
++		break;
++
++	case IOV_GVAL(IOV_METADATA_DBG):
++		int_val = dhd_prot_metadata_dbg_get(bus->dhd);
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_SVAL(IOV_METADATA_DBG):
++		dhd_prot_metadata_dbg_set(bus->dhd, (int_val != 0));
++		break;
++
++	case IOV_GVAL(IOV_RX_METADATALEN):
++		int_val = dhd_prot_metadatalen_get(bus->dhd, TRUE);
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_RX_METADATALEN):
++		if (int_val > 64) {
++			bcmerror = BCME_BUFTOOLONG;
++			break;
++		}
++		dhd_prot_metadatalen_set(bus->dhd, int_val, TRUE);
++		break;
++
++	case IOV_SVAL(IOV_TXP_THRESHOLD):
++		dhd_prot_txp_threshold(bus->dhd, TRUE, int_val);
++		break;
++
++	case IOV_GVAL(IOV_TXP_THRESHOLD):
++		int_val = dhd_prot_txp_threshold(bus->dhd, FALSE, int_val);
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DB1_FOR_MB):
++		if (int_val)
++			bus->db1_for_mb = TRUE;
++		else
++			bus->db1_for_mb = FALSE;
++		break;
++
++	case IOV_GVAL(IOV_DB1_FOR_MB):
++		if (bus->db1_for_mb)
++			int_val = 1;
++		else
++			int_val = 0;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_TX_METADATALEN):
++		int_val = dhd_prot_metadatalen_get(bus->dhd, FALSE);
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_TX_METADATALEN):
++		if (int_val > 64) {
++			bcmerror = BCME_BUFTOOLONG;
++			break;
++		}
++		dhd_prot_metadatalen_set(bus->dhd, int_val, FALSE);
++		break;
++
++	case IOV_SVAL(IOV_DEVRESET):
++		dhd_bus_devreset(bus->dhd, (uint8)bool_val);
++		break;
++	case IOV_SVAL(IOV_FORCE_FW_TRAP):
++		if (bus->dhd->busstate == DHD_BUS_DATA)
++			dhdpcie_fw_trap(bus);
++		else {
++			DHD_ERROR(("%s: Bus is NOT up\n", __FUNCTION__));
++			bcmerror = BCME_NOTUP;
++		}
++		break;
++	case IOV_GVAL(IOV_FLOW_PRIO_MAP):
++		int_val = bus->dhd->flow_prio_map_type;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_FLOW_PRIO_MAP):
++		int_val = (int32)dhd_update_flow_prio_map(bus->dhd, (uint8)int_val);
++		bcopy(&int_val, arg, val_size);
++		break;
++
++#ifdef DHD_PCIE_RUNTIMEPM
++	case IOV_GVAL(IOV_IDLETIME):
++		int_val = bus->idletime;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_IDLETIME):
++		if (int_val < 0) {
++			bcmerror = BCME_BADARG;
++		} else {
++			bus->idletime = int_val;
++			if (bus->idletime) {
++				DHD_ENABLE_RUNTIME_PM(bus->dhd);
++			} else {
++				DHD_DISABLE_RUNTIME_PM(bus->dhd);
++			}
++		}
++		break;
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++	case IOV_GVAL(IOV_TXBOUND):
++		int_val = (int32)dhd_txbound;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_TXBOUND):
++		dhd_txbound = (uint)int_val;
++		break;
++
++	case IOV_SVAL(IOV_H2D_MAILBOXDATA):
++		dhdpcie_send_mb_data(bus, (uint)int_val);
++		break;
++
++	case IOV_SVAL(IOV_INFORINGS):
++		dhd_prot_init_info_rings(bus->dhd);
++		break;
++
++	case IOV_SVAL(IOV_H2D_PHASE):
++		if (bus->dhd->busstate != DHD_BUS_DOWN) {
++			DHD_ERROR(("%s: Can change only when bus down (before FW download)\n",
++				__FUNCTION__));
++			bcmerror = BCME_NOTDOWN;
++			break;
++		}
++		if (int_val)
++			bus->dhd->h2d_phase_supported = TRUE;
++		else
++			bus->dhd->h2d_phase_supported = FALSE;
++		break;
++
++	case IOV_GVAL(IOV_H2D_PHASE):
++		int_val = (int32) bus->dhd->h2d_phase_supported;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_H2D_ENABLE_TRAP_BADPHASE):
++		if (bus->dhd->busstate != DHD_BUS_DOWN) {
++			DHD_ERROR(("%s: Can change only when bus down (before FW download)\n",
++				__FUNCTION__));
++			bcmerror = BCME_NOTDOWN;
++			break;
++		}
++		if (int_val)
++			bus->dhd->force_dongletrap_on_bad_h2d_phase = TRUE;
++		else
++			bus->dhd->force_dongletrap_on_bad_h2d_phase = FALSE;
++		break;
++
++	case IOV_GVAL(IOV_H2D_ENABLE_TRAP_BADPHASE):
++		int_val = (int32) bus->dhd->force_dongletrap_on_bad_h2d_phase;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_H2D_TXPOST_MAX_ITEM):
++		if (bus->dhd->busstate != DHD_BUS_DOWN) {
++			DHD_ERROR(("%s: Can change only when bus down (before FW download)\n",
++				__FUNCTION__));
++			bcmerror = BCME_NOTDOWN;
++			break;
++		}
++		dhd_prot_set_h2d_max_txpost(bus->dhd, (uint16)int_val);
++		break;
++
++	case IOV_GVAL(IOV_H2D_TXPOST_MAX_ITEM):
++		int_val = dhd_prot_get_h2d_max_txpost(bus->dhd);
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_RXBOUND):
++		int_val = (int32)dhd_rxbound;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_RXBOUND):
++		dhd_rxbound = (uint)int_val;
++		break;
++
++	case IOV_GVAL(IOV_TRAPDATA):
++	{
++		struct bcmstrbuf dump_b;
++		bcm_binit(&dump_b, arg, len);
++		bcmerror = dhd_prot_dump_extended_trap(bus->dhd, &dump_b, FALSE);
++		break;
++	}
++
++	case IOV_GVAL(IOV_TRAPDATA_RAW):
++	{
++		struct bcmstrbuf dump_b;
++		bcm_binit(&dump_b, arg, len);
++		bcmerror = dhd_prot_dump_extended_trap(bus->dhd, &dump_b, TRUE);
++		break;
++	}
++	case IOV_SVAL(IOV_HANGREPORT):
++		bus->dhd->hang_report = bool_val;
++		DHD_ERROR(("%s: Set hang_report as %d\n",
++			__FUNCTION__, bus->dhd->hang_report));
++		break;
++
++	case IOV_GVAL(IOV_HANGREPORT):
++		int_val = (int32)bus->dhd->hang_report;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_CTO_PREVENTION):
++		{
++			uint32 pcie_lnkst;
++
++			if (bus->sih->buscorerev < 19) {
++				bcmerror = BCME_UNSUPPORTED;
++				break;
++			}
++			si_corereg(bus->sih, bus->sih->buscoreidx,
++					OFFSETOF(sbpcieregs_t, configaddr), ~0, PCI_LINK_STATUS);
++
++			pcie_lnkst = si_corereg(bus->sih, bus->sih->buscoreidx,
++				OFFSETOF(sbpcieregs_t, configdata), 0, 0);
++
++			/* 4347A0 in PCIEGEN1 doesn't support CTO prevention due to
++			 * 4347A0 DAR Issue : JIRA:CRWLPCIEGEN2-443: Issue in DAR write
++			 */
++			if ((bus->sih->buscorerev == 19) &&
++				(((pcie_lnkst >> PCI_LINK_SPEED_SHIFT) &
++					PCI_LINK_SPEED_MASK) == PCIE_LNK_SPEED_GEN1)) {
++				bcmerror = BCME_UNSUPPORTED;
++				break;
++			}
++			bus->dhd->cto_enable = bool_val;
++			dhdpcie_cto_init(bus, bus->dhd->cto_enable);
++			DHD_ERROR(("%s: set CTO prevention and recovery enable/disable %d\n",
++				__FUNCTION__, bus->dhd->cto_enable));
++		}
++		break;
++
++	case IOV_GVAL(IOV_CTO_PREVENTION):
++		if (bus->sih->buscorerev < 19) {
++			bcmerror = BCME_UNSUPPORTED;
++			break;
++		}
++		int_val = (int32)bus->dhd->cto_enable;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_CTO_THRESHOLD):
++		{
++			if (bus->sih->buscorerev < 19) {
++				bcmerror = BCME_UNSUPPORTED;
++				break;
++			}
++			bus->dhd->cto_threshold = (uint32)int_val;
++		}
++		break;
++
++	case IOV_GVAL(IOV_CTO_THRESHOLD):
++		if (bus->sih->buscorerev < 19) {
++			bcmerror = BCME_UNSUPPORTED;
++			break;
++		}
++		if (bus->dhd->cto_threshold)
++			int_val = (int32)bus->dhd->cto_threshold;
++		else
++			int_val = (int32)PCIE_CTO_TO_THRESH_DEFAULT;
++
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_PCIE_WD_RESET):
++		if (bool_val) {
++			pcie_watchdog_reset(bus->osh, bus->sih, (sbpcieregs_t *) bus->regs);
++		}
++		break;
++#ifdef DHD_EFI
++	case IOV_SVAL(IOV_CONTROL_SIGNAL):
++		{
++			bcmerror = dhd_control_signal(bus, arg, TRUE);
++			break;
++		}
++
++	case IOV_GVAL(IOV_CONTROL_SIGNAL):
++		{
++			bcmerror = dhd_control_signal(bus, params, FALSE);
++			break;
++		}
++#if defined(PCIE_OOB) || defined(PCIE_INB_DW)
++	case IOV_GVAL(IOV_DEEP_SLEEP):
++		int_val = bus->ds_enabled;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DEEP_SLEEP):
++		if (int_val == 1) {
++			bus->ds_enabled = TRUE;
++			/* Deassert */
++			if (dhd_bus_set_device_wake(bus, FALSE) == BCME_OK) {
++#ifdef PCIE_INB_DW
++				int timeleft;
++				timeleft = dhd_os_ds_enter_wait(bus->dhd, NULL);
++				if (timeleft == 0) {
++					DHD_ERROR(("DS-ENTER timeout\n"));
++					bus->ds_enabled = FALSE;
++					break;
++				}
++#endif /* PCIE_INB_DW */
++			}
++			else {
++				DHD_ERROR(("%s: Enable Deep Sleep failed !\n", __FUNCTION__));
++				bus->ds_enabled = FALSE;
++			}
++		}
++		else if (int_val == 0) {
++			/* Assert */
++			if (dhd_bus_set_device_wake(bus, TRUE) == BCME_OK)
++				bus->ds_enabled = FALSE;
++			else
++				DHD_ERROR(("%s: Disable Deep Sleep failed !\n", __FUNCTION__));
++		}
++		else
++			DHD_ERROR(("%s: Invalid number, allowed only 0|1\n", __FUNCTION__));
++
++		break;
++#endif /* PCIE_OOB || PCIE_INB_DW */
++
++	case IOV_GVAL(IOV_WIFI_PROPERTIES):
++		bcmerror = dhd_wifi_properties(bus, params);
++		break;
++
++	case IOV_GVAL(IOV_OTP_DUMP):
++		bcmerror = dhd_otp_dump(bus, params);
++		break;
++#endif /* DHD_EFI */
++
++	case IOV_GVAL(IOV_IDMA_ENABLE):
++		int_val = bus->idma_enabled;
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_SVAL(IOV_IDMA_ENABLE):
++		bus->idma_enabled = (bool)int_val;
++		break;
++	case IOV_GVAL(IOV_IFRM_ENABLE):
++		int_val = bus->ifrm_enabled;
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_SVAL(IOV_IFRM_ENABLE):
++		bus->ifrm_enabled = (bool)int_val;
++		break;
++	case IOV_GVAL(IOV_CLEAR_RING):
++		bcopy(&int_val, arg, val_size);
++		dhd_flow_rings_flush(bus->dhd, 0);
++		break;
++	default:
++		bcmerror = BCME_UNSUPPORTED;
++		break;
++	}
++
++exit:
++	return bcmerror;
++} /* dhdpcie_bus_doiovar */
++
++/** Transfers bytes from host to dongle using pio mode */
++static int
++dhdpcie_bus_lpback_req(struct  dhd_bus *bus, uint32 len)
++{
++	if (bus->dhd == NULL) {
++		DHD_ERROR(("%s: bus not inited\n", __FUNCTION__));
++		return 0;
++	}
++	if (bus->dhd->prot == NULL) {
++		DHD_ERROR(("%s: prot is not inited\n", __FUNCTION__));
++		return 0;
++	}
++	if (bus->dhd->busstate != DHD_BUS_DATA) {
++		DHD_ERROR(("%s: not in a readystate to LPBK  is not inited\n", __FUNCTION__));
++		return 0;
++	}
++	dhdmsgbuf_lpbk_req(bus->dhd, len);
++	return 0;
++}
++
++/* Ring DoorBell1 to indicate Hostready i.e. D3 Exit */
++void
++dhd_bus_hostready(struct  dhd_bus *bus)
++{
++	if (!bus->dhd->d2h_hostrdy_supported) {
++		return;
++	}
++
++	if (bus->is_linkdown) {
++		DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__));
++		return;
++	}
++
++	DHD_INFO_HW4(("%s : Read PCICMD Reg: 0x%08X\n", __FUNCTION__,
++		dhd_pcie_config_read(bus->osh, PCI_CFG_CMD, sizeof(uint32))));
++	si_corereg(bus->sih, bus->sih->buscoreidx, PCIH2D_DB1, ~0, 0x12345678);
++	bus->hostready_count ++;
++	DHD_INFO_HW4(("%s: Ring Hostready:%d\n", __FUNCTION__, bus->hostready_count));
++}
++
++/* Clear INTSTATUS */
++void
++dhdpcie_bus_clear_intstatus(struct dhd_bus *bus)
++{
++	uint32 intstatus = 0;
++	if ((bus->sih->buscorerev == 6) || (bus->sih->buscorerev == 4) ||
++		(bus->sih->buscorerev == 2)) {
++		intstatus = dhdpcie_bus_cfg_read_dword(bus, PCIIntstatus, 4);
++		dhdpcie_bus_cfg_write_dword(bus, PCIIntstatus, 4, intstatus);
++	} else {
++		/* this is a PCIE core register..not a config register... */
++		intstatus = si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxInt, 0, 0);
++		si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxInt, bus->def_intmask,
++			intstatus);
++	}
++}
++
++int
++dhdpcie_bus_suspend(struct dhd_bus *bus, bool state)
++{
++	int timeleft;
++	int rc = 0;
++	unsigned long flags;
++
++	printf("%s: state=%d\n", __FUNCTION__, state);
++	if (bus->dhd == NULL) {
++		DHD_ERROR(("%s: bus not inited\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++	if (bus->dhd->prot == NULL) {
++		DHD_ERROR(("%s: prot is not inited\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	if (dhd_query_bus_erros(bus->dhd)) {
++		return BCME_ERROR;
++	}
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	if (!(bus->dhd->busstate == DHD_BUS_DATA || bus->dhd->busstate == DHD_BUS_SUSPEND)) {
++		DHD_ERROR(("%s: not in a readystate\n", __FUNCTION__));
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++		return BCME_ERROR;
++	}
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++	if (bus->dhd->dongle_reset) {
++		DHD_ERROR(("Dongle is in reset state.\n"));
++		return -EIO;
++	}
++
++	/* Check whether we are already in the requested state.
++	 * state=TRUE means Suspend
++	 * state=FALSE meanse Resume
++	 */
++	if (state == TRUE && bus->dhd->busstate == DHD_BUS_SUSPEND) {
++		DHD_ERROR(("Bus is already in SUSPEND state.\n"));
++		return BCME_OK;
++	} else if (state == FALSE && bus->dhd->busstate == DHD_BUS_DATA) {
++		DHD_ERROR(("Bus is already in RESUME state.\n"));
++		return BCME_OK;
++	}
++
++	if (bus->d3_suspend_pending) {
++		DHD_ERROR(("Suspend pending ...\n"));
++		return BCME_ERROR;
++	}
++
++
++	if (state) {
++		int idle_retry = 0;
++		int active;
++
++		if (bus->is_linkdown) {
++			DHD_ERROR(("%s: PCIe link was down, state=%d\n",
++				__FUNCTION__, state));
++			return BCME_ERROR;
++		}
++
++		/* Suspend */
++		DHD_ERROR(("%s: Entering suspend state\n", __FUNCTION__));
++
++		DHD_GENERAL_LOCK(bus->dhd, flags);
++		if (DHD_BUS_BUSY_CHECK_IN_TX(bus->dhd)) {
++			DHD_ERROR(("Tx Request is not ended\n"));
++			bus->dhd->busstate = DHD_BUS_DATA;
++			DHD_GENERAL_UNLOCK(bus->dhd, flags);
++#ifndef DHD_EFI
++			return -EBUSY;
++#else
++			return BCME_ERROR;
++#endif
++		}
++
++		/* stop all interface network queue. */
++		dhd_bus_stop_queue(bus);
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++		DHD_OS_WAKE_LOCK_WAIVE(bus->dhd);
++#ifdef DHD_TIMESYNC
++		/* disable time sync mechanism, if configed */
++		dhd_timesync_control(bus->dhd, TRUE);
++#endif /* DHD_TIMESYNC */
++#if defined(PCIE_OOB) || defined(PCIE_INB_DW)
++		dhd_bus_set_device_wake(bus, TRUE);
++#endif /* defined(PCIE_OOB) || defined(PCIE_INB_DW) */
++#ifdef PCIE_OOB
++		bus->oob_presuspend = TRUE;
++#endif
++#ifdef PCIE_INB_DW
++		/* De-assert at this point for In-band device_wake */
++		if (INBAND_DW_ENAB(bus)) {
++			dhd_bus_set_device_wake(bus, FALSE);
++			dhdpcie_bus_set_pcie_inband_dw_state(bus, DW_DEVICE_HOST_SLEEP_WAIT);
++		}
++#endif /* PCIE_INB_DW */
++
++		/* Clear wait_for_d3_ack */
++		bus->wait_for_d3_ack = 0;
++		/*
++		 * Send H2D_HOST_D3_INFORM to dongle and mark
++		 * bus->d3_suspend_pending to TRUE in dhdpcie_send_mb_data
++		 * inside atomic context, so that no more DBs will be
++		 * rung after sending D3_INFORM
++		 */
++		dhdpcie_send_mb_data(bus, H2D_HOST_D3_INFORM);
++
++		/* Wait for D3 ACK for D3_ACK_RESP_TIMEOUT seconds */
++		dhd_os_set_ioctl_resp_timeout(D3_ACK_RESP_TIMEOUT);
++		timeleft = dhd_os_d3ack_wait(bus->dhd, &bus->wait_for_d3_ack);
++
++#ifdef DHD_RECOVER_TIMEOUT
++		if (bus->wait_for_d3_ack == 0) {
++			/* If wait_for_d3_ack was not updated because D2H MB was not received */
++			uint32 intstatus = 0;
++			uint32 intmask = 0;
++			intstatus = si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxInt, 0, 0);
++			intmask = si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxMask, 0, 0);
++			if ((intstatus) && (!intmask) && (timeleft == 0) &&
++				(!dhd_query_bus_erros(bus->dhd))) {
++
++				DHD_ERROR(("%s: D3 ACK trying again intstatus=%x intmask=%x\n",
++					__FUNCTION__, intstatus, intmask));
++				DHD_ERROR(("\n ------- DUMPING INTR enable/disable counters\r\n"));
++				DHD_ERROR(("resume_intr_enable_count=%lu dpc_intr_en_count=%lu\n"
++					"isr_intr_disable_count=%lu suspend_intr_dis_count=%lu\n"
++					"dpc_return_busdown_count=%lu\n",
++					bus->resume_intr_enable_count, bus->dpc_intr_enable_count,
++					bus->isr_intr_disable_count,
++					bus->suspend_intr_disable_count,
++					bus->dpc_return_busdown_count));
++
++				dhd_prot_process_ctrlbuf(bus->dhd);
++
++				timeleft = dhd_os_d3ack_wait(bus->dhd, &bus->wait_for_d3_ack);
++
++				/* Enable Back Interrupts using IntMask  */
++				dhdpcie_bus_intr_enable(bus);
++			}
++
++
++		} /* bus->wait_for_d3_ack was 0 */
++#endif /* DHD_RECOVER_TIMEOUT */
++
++		DHD_OS_WAKE_LOCK_RESTORE(bus->dhd);
++
++		/* To allow threads that got pre-empted to complete.
++		 */
++		while ((active = dhd_os_check_wakelock_all(bus->dhd)) &&
++			(idle_retry < MAX_WKLK_IDLE_CHECK)) {
++			OSL_SLEEP(1);
++			idle_retry++;
++		}
++
++		if (bus->wait_for_d3_ack) {
++			DHD_ERROR(("%s: Got D3 Ack \n", __FUNCTION__));
++
++			/* Got D3 Ack. Suspend the bus */
++			if (active) {
++				DHD_ERROR(("%s():Suspend failed because of wakelock"
++					"restoring Dongle to D0\n", __FUNCTION__));
++
++				/*
++				 * Dongle still thinks that it has to be in D3 state until
++				 * it gets a D0 Inform, but we are backing off from suspend.
++				 * Ensure that Dongle is brought back to D0.
++				 *
++				 * Bringing back Dongle from D3 Ack state to D0 state is a
++				 * 2 step process. Dongle would want to know that D0 Inform
++				 * would be sent as a MB interrupt to bring it out of D3 Ack
++				 * state to D0 state. So we have to send both this message.
++				 */
++
++				/* Clear wait_for_d3_ack to send D0_INFORM or host_ready */
++				bus->wait_for_d3_ack = 0;
++
++				/* Enable back the intmask which was cleared in DPC
++				 * after getting D3_ACK.
++				 */
++				bus->resume_intr_enable_count++;
++				dhdpcie_bus_intr_enable(bus);
++
++				if (bus->use_d0_inform) {
++					DHD_OS_WAKE_LOCK_WAIVE(bus->dhd);
++					dhdpcie_send_mb_data(bus,
++						(H2D_HOST_D0_INFORM_IN_USE | H2D_HOST_D0_INFORM));
++					DHD_OS_WAKE_LOCK_RESTORE(bus->dhd);
++				}
++				/* ring doorbell 1 (hostready) */
++				dhd_bus_hostready(bus);
++
++				DHD_GENERAL_LOCK(bus->dhd, flags);
++				bus->d3_suspend_pending = FALSE;
++				bus->dhd->busstate = DHD_BUS_DATA;
++				/* resume all interface network queue. */
++				dhd_bus_start_queue(bus);
++				DHD_GENERAL_UNLOCK(bus->dhd, flags);
++				rc = BCME_ERROR;
++			} else {
++#ifdef PCIE_OOB
++				bus->oob_presuspend = FALSE;
++				if (OOB_DW_ENAB(bus)) {
++					dhd_bus_set_device_wake(bus, FALSE);
++				}
++#endif /* PCIE_OOB */
++#if defined(PCIE_OOB) || defined(BCMPCIE_OOB_HOST_WAKE)
++				bus->oob_presuspend = TRUE;
++#endif /* PCIE_OOB || BCMPCIE_OOB_HOST_WAKE */
++#ifdef PCIE_INB_DW
++				if (INBAND_DW_ENAB(bus)) {
++					if (dhdpcie_bus_get_pcie_inband_dw_state(bus) ==
++						DW_DEVICE_HOST_SLEEP_WAIT) {
++						dhdpcie_bus_set_pcie_inband_dw_state(bus,
++							DW_DEVICE_HOST_SLEEP);
++					}
++				}
++#endif /* PCIE_INB_DW */
++				if (bus->use_d0_inform &&
++					(bus->api.fw_rev < PCIE_SHARED_VERSION_6)) {
++					DHD_OS_WAKE_LOCK_WAIVE(bus->dhd);
++					dhdpcie_send_mb_data(bus, (H2D_HOST_D0_INFORM_IN_USE));
++					DHD_OS_WAKE_LOCK_RESTORE(bus->dhd);
++				}
++#if defined(BCMPCIE_OOB_HOST_WAKE)
++				dhdpcie_oob_intr_set(bus, TRUE);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++
++				DHD_GENERAL_LOCK(bus->dhd, flags);
++				/* The Host cannot process interrupts now so disable the same.
++				 * No need to disable the dongle INTR using intmask, as we are
++				 * already calling dhdpcie_bus_intr_disable from DPC context after
++				 * getting D3_ACK. Code may not look symmetric between Suspend and
++				 * Resume paths but this is done to close down the timing window
++				 * between DPC and suspend context.
++				 */
++				/* Disable interrupt from host side!! */
++				dhdpcie_disable_irq_nosync(bus);
++
++				bus->dhd->d3ackcnt_timeout = 0;
++				bus->d3_suspend_pending = FALSE;
++				bus->dhd->busstate = DHD_BUS_SUSPEND;
++				DHD_GENERAL_UNLOCK(bus->dhd, flags);
++				/* Handle Host Suspend */
++				rc = dhdpcie_pci_suspend_resume(bus, state);
++			}
++		} else if (timeleft == 0) {
++			bus->dhd->d3ack_timeout_occured = TRUE;
++			/* If the D3 Ack has timeout */
++			bus->dhd->d3ackcnt_timeout++;
++			DHD_ERROR(("%s: resumed on timeout for D3 ACK d3_inform_cnt %d \n",
++					__FUNCTION__, bus->dhd->d3ackcnt_timeout));
++			DHD_GENERAL_LOCK(bus->dhd, flags);
++			bus->d3_suspend_pending = FALSE;
++			bus->dhd->busstate = DHD_BUS_DATA;
++			/* resume all interface network queue. */
++			dhd_bus_start_queue(bus);
++			DHD_GENERAL_UNLOCK(bus->dhd, flags);
++			if (!bus->dhd->dongle_trap_occured) {
++				uint32 intstatus = 0;
++
++				/* Check if PCIe bus status is valid */
++				intstatus = si_corereg(bus->sih,
++					bus->sih->buscoreidx, PCIMailBoxInt, 0, 0);
++				if (intstatus == (uint32)-1) {
++					/* Invalidate PCIe bus status */
++					bus->is_linkdown = 1;
++				}
++
++				dhd_bus_dump_console_buffer(bus);
++				dhd_prot_debug_info_print(bus->dhd);
++#ifdef DHD_FW_COREDUMP
++				if (bus->dhd->memdump_enabled) {
++					/* write core dump to file */
++					bus->dhd->memdump_type = DUMP_TYPE_D3_ACK_TIMEOUT;
++					dhdpcie_mem_dump(bus);
++				}
++#endif /* DHD_FW_COREDUMP */
++				DHD_ERROR(("%s: Event HANG send up due to D3_ACK timeout\n",
++					__FUNCTION__));
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#ifdef CONFIG_ARCH_MSM
++				bus->no_cfg_restore = 1;
++#endif /* CONFIG_ARCH_MSM */
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++				dhd_os_check_hang(bus->dhd, 0, -ETIMEDOUT);
++			}
++			rc = -ETIMEDOUT;
++		}
++		bus->wait_for_d3_ack = 1;
++
++#ifdef PCIE_OOB
++		bus->oob_presuspend = FALSE;
++#endif /* PCIE_OOB */
++	} else {
++		/* Resume */
++		/**
++		 * PCIE2_BAR0_CORE2_WIN gets reset after D3 cold.
++		 * si_backplane_access(function to read/write backplane)
++		 * updates the window(PCIE2_BAR0_CORE2_WIN) only if
++		 * window being accessed is different form the window
++		 * being pointed by second_bar0win.
++		 * Since PCIE2_BAR0_CORE2_WIN is already reset because of D3 cold,
++		 * invalidating second_bar0win after resume updates
++		 * PCIE2_BAR0_CORE2_WIN with right window.
++		 */
++		si_invalidate_second_bar0win(bus->sih);
++#if defined(BCMPCIE_OOB_HOST_WAKE)
++		DHD_OS_OOB_IRQ_WAKE_UNLOCK(bus->dhd);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#ifdef PCIE_INB_DW
++		if (INBAND_DW_ENAB(bus)) {
++			if (dhdpcie_bus_get_pcie_inband_dw_state(bus) == DW_DEVICE_HOST_SLEEP) {
++				dhdpcie_bus_set_pcie_inband_dw_state(bus, DW_DEVICE_HOST_WAKE_WAIT);
++			}
++		}
++#endif /* PCIE_INB_DW */
++		rc = dhdpcie_pci_suspend_resume(bus, state);
++
++#ifdef BCMPCIE_OOB_HOST_WAKE
++		bus->oob_presuspend = FALSE;
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++
++		if (bus->dhd->busstate == DHD_BUS_SUSPEND) {
++			if (bus->use_d0_inform) {
++				DHD_OS_WAKE_LOCK_WAIVE(bus->dhd);
++				dhdpcie_send_mb_data(bus, (H2D_HOST_D0_INFORM));
++				DHD_OS_WAKE_LOCK_RESTORE(bus->dhd);
++			}
++			/* ring doorbell 1 (hostready) */
++			dhd_bus_hostready(bus);
++		}
++
++		DHD_GENERAL_LOCK(bus->dhd, flags);
++		bus->dhd->busstate = DHD_BUS_DATA;
++#ifdef DHD_PCIE_RUNTIMEPM
++		if (DHD_BUS_BUSY_CHECK_RPM_SUSPEND_DONE(bus->dhd)) {
++			bus->bus_wake = 1;
++			OSL_SMP_WMB();
++			wake_up_interruptible(&bus->rpm_queue);
++		}
++#endif /* DHD_PCIE_RUNTIMEPM */
++#ifdef PCIE_OOB
++		/*
++		 * Assert & Deassert the Device Wake. The following is the explanation for doing so.
++		 * 0) At this point,
++		 *    Host is in suspend state, Link is in L2/L3, Dongle is in D3 Cold
++		 *    Device Wake is enabled.
++		 * 1) When the Host comes out of Suspend, it first sends PERST# in the Link.
++		 *    Looking at this the Dongle moves from D3 Cold to NO DS State
++		 * 2) Now The Host OS calls the "resume" function of DHD. From here the DHD first
++		 *    Asserts the Device Wake.
++		 *    From the defn, when the Device Wake is asserted, The dongle FW will ensure
++		 *    that the Dongle is out of deep sleep IF the device is already in deep sleep.
++		 *    But note that now the Dongle is NOT in Deep sleep and is actually in
++		 *    NO DS state. So just driving the Device Wake high does not trigger any state
++		 *    transitions. The Host should actually "Toggle" the Device Wake to ensure
++		 *    that Dongle synchronizes with the Host and starts the State Transition to D0.
++		 * 4) Note that the above explanation is applicable Only when the Host comes out of
++		 *    suspend and the Dongle comes out of D3 Cold
++		 */
++		/* This logic is not required when hostready is enabled */
++
++		if (!bus->dhd->d2h_hostrdy_supported) {
++			if (OOB_DW_ENAB(bus)) {
++				dhd_bus_set_device_wake(bus, TRUE);
++				OSL_DELAY(1000);
++				dhd_bus_set_device_wake(bus, FALSE);
++			}
++		}
++#endif /* PCIE_OOB */
++		/* resume all interface network queue. */
++		dhd_bus_start_queue(bus);
++		/* The Host is ready to process interrupts now so enable the same. */
++
++		/* TODO: for NDIS also we need to use enable_irq in future */
++		bus->resume_intr_enable_count++;
++		dhdpcie_bus_intr_enable(bus); /* Enable back interrupt using Intmask!! */
++		dhdpcie_enable_irq(bus); /* Enable back interrupt from Host side!! */
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++#ifdef DHD_TIMESYNC
++		DHD_OS_WAKE_LOCK_WAIVE(bus->dhd);
++		/* enable time sync mechanism, if configed */
++		dhd_timesync_control(bus->dhd, FALSE);
++		DHD_OS_WAKE_LOCK_RESTORE(bus->dhd);
++#endif /* DHD_TIMESYNC */
++	}
++	return rc;
++}
++
++uint32
++dhdpcie_force_alp(struct dhd_bus *bus, bool enable)
++{
++	ASSERT(bus && bus->sih);
++	if (enable) {
++	si_corereg(bus->sih, bus->sih->buscoreidx,
++		OFFSETOF(sbpcieregs_t, u.pcie2.clk_ctl_st), CCS_FORCEALP, CCS_FORCEALP);
++	} else {
++		si_corereg(bus->sih, bus->sih->buscoreidx,
++			OFFSETOF(sbpcieregs_t, u.pcie2.clk_ctl_st), CCS_FORCEALP, 0);
++	}
++	return 0;
++}
++
++/* set pcie l1 entry time: dhd pciereg 0x1004[22:16] */
++uint32
++dhdpcie_set_l1_entry_time(struct dhd_bus *bus, int l1_entry_time)
++{
++	uint reg_val;
++
++	ASSERT(bus && bus->sih);
++
++	si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0,
++		0x1004);
++	reg_val = si_corereg(bus->sih, bus->sih->buscoreidx,
++		OFFSETOF(sbpcieregs_t, configdata), 0, 0);
++	reg_val = (reg_val & ~(0x7f << 16)) | ((l1_entry_time & 0x7f) << 16);
++	si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata), ~0,
++		reg_val);
++
++	return 0;
++}
++
++/** Transfers bytes from host to dongle and to host again using DMA */
++static int
++dhdpcie_bus_dmaxfer_req(
++	struct  dhd_bus *bus, uint32 len, uint32 srcdelay, uint32 destdelay, uint32 d11_lpbk)
++{
++	if (bus->dhd == NULL) {
++		DHD_ERROR(("%s: bus not inited\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++	if (bus->dhd->prot == NULL) {
++		DHD_ERROR(("%s: prot is not inited\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++	if (bus->dhd->busstate != DHD_BUS_DATA) {
++		DHD_ERROR(("%s: not in a readystate to LPBK  is not inited\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	if (len < 5 || len > 4194296) {
++		DHD_ERROR(("%s: len is too small or too large\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++	return dhdmsgbuf_dmaxfer_req(bus->dhd, len, srcdelay, destdelay, d11_lpbk);
++}
++
++
++
++static int
++dhdpcie_bus_download_state(dhd_bus_t *bus, bool enter)
++{
++	int bcmerror = 0;
++	volatile uint32 *cr4_regs;
++
++	if (!bus->sih) {
++		DHD_ERROR(("%s: NULL sih!!\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++	/* To enter download state, disable ARM and reset SOCRAM.
++	 * To exit download state, simply reset ARM (default is RAM boot).
++	 */
++	if (enter) {
++		/* Make sure BAR1 maps to backplane address 0 */
++		dhdpcie_bus_cfg_write_dword(bus, PCI_BAR1_WIN, 4, 0x00000000);
++		bus->alp_only = TRUE;
++
++		/* some chips (e.g. 43602) have two ARM cores, the CR4 is receives the firmware. */
++		cr4_regs = si_setcore(bus->sih, ARMCR4_CORE_ID, 0);
++
++		if (cr4_regs == NULL && !(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
++		    !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0)) &&
++		    !(si_setcore(bus->sih, ARMCA7_CORE_ID, 0))) {
++			DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__));
++			bcmerror = BCME_ERROR;
++			goto fail;
++		}
++
++		if (si_setcore(bus->sih, ARMCA7_CORE_ID, 0)) {
++			/* Halt ARM & remove reset */
++			si_core_reset(bus->sih, SICF_CPUHALT, SICF_CPUHALT);
++			if (!(si_setcore(bus->sih, SYSMEM_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find SYSMEM core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++			si_core_reset(bus->sih, 0, 0);
++			/* reset last 4 bytes of RAM address. to be used for shared area */
++			dhdpcie_init_shared_addr(bus);
++		} else if (cr4_regs == NULL) { /* no CR4 present on chip */
++			si_core_disable(bus->sih, 0);
++
++			if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++
++			si_core_reset(bus->sih, 0, 0);
++
++			/* Clear the top bit of memory */
++			if (bus->ramsize) {
++				uint32 zeros = 0;
++				if (dhdpcie_bus_membytes(bus, TRUE, bus->ramsize - 4,
++				                     (uint8*)&zeros, 4) < 0) {
++					bcmerror = BCME_ERROR;
++					goto fail;
++				}
++			}
++		} else {
++			/* For CR4,
++			 * Halt ARM
++			 * Remove ARM reset
++			 * Read RAM base address [0x18_0000]
++			 * [next] Download firmware
++			 * [done at else] Populate the reset vector
++			 * [done at else] Remove ARM halt
++			*/
++			/* Halt ARM & remove reset */
++			si_core_reset(bus->sih, SICF_CPUHALT, SICF_CPUHALT);
++			if (BCM43602_CHIP(bus->sih->chip)) {
++				W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKIDX, 5);
++				W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKPDA, 0);
++				W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKIDX, 7);
++				W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKPDA, 0);
++			}
++			/* reset last 4 bytes of RAM address. to be used for shared area */
++			dhdpcie_init_shared_addr(bus);
++		}
++	} else {
++		if (si_setcore(bus->sih, ARMCA7_CORE_ID, 0)) {
++			/* write vars */
++			if ((bcmerror = dhdpcie_bus_write_vars(bus))) {
++				DHD_ERROR(("%s: could not write vars to RAM\n", __FUNCTION__));
++				goto fail;
++			}
++			/* switch back to arm core again */
++			if (!(si_setcore(bus->sih, ARMCA7_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find ARM CA7 core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++			/* write address 0 with reset instruction */
++			bcmerror = dhdpcie_bus_membytes(bus, TRUE, 0,
++				(uint8 *)&bus->resetinstr, sizeof(bus->resetinstr));
++			/* now remove reset and halt and continue to run CA7 */
++		} else if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
++			if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++
++			if (!si_iscoreup(bus->sih)) {
++				DHD_ERROR(("%s: SOCRAM core is down after reset?\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++
++			/* Enable remap before ARM reset but after vars.
++			 * No backplane access in remap mode
++			 */
++			if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
++			    !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
++				DHD_ERROR(("%s: Can't change back to SDIO core?\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++
++
++			if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
++			    !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++		} else {
++			if (BCM43602_CHIP(bus->sih->chip)) {
++				/* Firmware crashes on SOCSRAM access when core is in reset */
++				if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
++					DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
++						__FUNCTION__));
++					bcmerror = BCME_ERROR;
++					goto fail;
++				}
++				si_core_reset(bus->sih, 0, 0);
++				si_setcore(bus->sih, ARMCR4_CORE_ID, 0);
++			}
++
++			/* write vars */
++			if ((bcmerror = dhdpcie_bus_write_vars(bus))) {
++				DHD_ERROR(("%s: could not write vars to RAM\n", __FUNCTION__));
++				goto fail;
++			}
++
++#ifdef BCM_ASLR_HEAP
++			/* write a random number to TCM for the purpose of
++			 * randomizing heap address space.
++			 */
++			dhdpcie_wrt_rnd(bus);
++#endif /* BCM_ASLR_HEAP */
++
++			/* switch back to arm core again */
++			if (!(si_setcore(bus->sih, ARMCR4_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find ARM CR4 core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++
++			/* write address 0 with reset instruction */
++			bcmerror = dhdpcie_bus_membytes(bus, TRUE, 0,
++				(uint8 *)&bus->resetinstr, sizeof(bus->resetinstr));
++
++			if (bcmerror == BCME_OK) {
++				uint32 tmp;
++
++				bcmerror = dhdpcie_bus_membytes(bus, FALSE, 0,
++				                                (uint8 *)&tmp, sizeof(tmp));
++
++				if (bcmerror == BCME_OK && tmp != bus->resetinstr) {
++					DHD_ERROR(("%s: Failed to write 0x%08x to addr 0\n",
++					          __FUNCTION__, bus->resetinstr));
++					DHD_ERROR(("%s: contents of addr 0 is 0x%08x\n",
++					          __FUNCTION__, tmp));
++					bcmerror = BCME_ERROR;
++					goto fail;
++				}
++			}
++
++			/* now remove reset and halt and continue to run CR4 */
++		}
++
++		si_core_reset(bus->sih, 0, 0);
++
++		/* Allow HT Clock now that the ARM is running. */
++		bus->alp_only = FALSE;
++
++		bus->dhd->busstate = DHD_BUS_LOAD;
++	}
++
++fail:
++	/* Always return to PCIE core */
++	si_setcore(bus->sih, PCIE2_CORE_ID, 0);
++
++	return bcmerror;
++} /* dhdpcie_bus_download_state */
++
++static int
++dhdpcie_bus_write_vars(dhd_bus_t *bus)
++{
++	int bcmerror = 0;
++	uint32 varsize, phys_size;
++	uint32 varaddr;
++	uint8 *vbuffer;
++	uint32 varsizew;
++#ifdef DHD_DEBUG
++	uint8 *nvram_ularray;
++#endif /* DHD_DEBUG */
++
++	/* Even if there are no vars are to be written, we still need to set the ramsize. */
++	varsize = bus->varsz ? ROUNDUP(bus->varsz, 4) : 0;
++	varaddr = (bus->ramsize - 4) - varsize;
++
++	varaddr += bus->dongle_ram_base;
++
++	if (bus->vars) {
++
++		vbuffer = (uint8 *)MALLOC(bus->dhd->osh, varsize);
++		if (!vbuffer)
++			return BCME_NOMEM;
++
++		bzero(vbuffer, varsize);
++		bcopy(bus->vars, vbuffer, bus->varsz);
++		/* Write the vars list */
++		bcmerror = dhdpcie_bus_membytes(bus, TRUE, varaddr, vbuffer, varsize);
++
++		/* Implement read back and verify later */
++#ifdef DHD_DEBUG
++		/* Verify NVRAM bytes */
++		DHD_INFO(("%s: Compare NVRAM dl & ul; varsize=%d\n", __FUNCTION__, varsize));
++		nvram_ularray = (uint8*)MALLOC(bus->dhd->osh, varsize);
++		if (!nvram_ularray)
++			return BCME_NOMEM;
++
++		/* Upload image to verify downloaded contents. */
++		memset(nvram_ularray, 0xaa, varsize);
++
++		/* Read the vars list to temp buffer for comparison */
++		bcmerror = dhdpcie_bus_membytes(bus, FALSE, varaddr, nvram_ularray, varsize);
++		if (bcmerror) {
++				DHD_ERROR(("%s: error %d on reading %d nvram bytes at 0x%08x\n",
++					__FUNCTION__, bcmerror, varsize, varaddr));
++		}
++
++		/* Compare the org NVRAM with the one read from RAM */
++		if (memcmp(vbuffer, nvram_ularray, varsize)) {
++			DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n", __FUNCTION__));
++		} else
++			DHD_ERROR(("%s: Download, Upload and compare of NVRAM succeeded.\n",
++			__FUNCTION__));
++
++		MFREE(bus->dhd->osh, nvram_ularray, varsize);
++#endif /* DHD_DEBUG */
++
++		MFREE(bus->dhd->osh, vbuffer, varsize);
++	}
++
++	phys_size = REMAP_ENAB(bus) ? bus->ramsize : bus->orig_ramsize;
++
++	phys_size += bus->dongle_ram_base;
++
++	/* adjust to the user specified RAM */
++	DHD_INFO(("%s: Physical memory size: %d, usable memory size: %d\n", __FUNCTION__,
++		phys_size, bus->ramsize));
++	DHD_INFO(("%s: Vars are at %d, orig varsize is %d\n", __FUNCTION__,
++		varaddr, varsize));
++	varsize = ((phys_size - 4) - varaddr);
++
++	/*
++	 * Determine the length token:
++	 * Varsize, converted to words, in lower 16-bits, checksum in upper 16-bits.
++	 */
++	if (bcmerror) {
++		varsizew = 0;
++		bus->nvram_csm = varsizew;
++	} else {
++		varsizew = varsize / 4;
++		varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
++		bus->nvram_csm = varsizew;
++		varsizew = htol32(varsizew);
++	}
++
++	DHD_INFO(("%s: New varsize is %d, length token=0x%08x\n", __FUNCTION__, varsize, varsizew));
++
++	/* Write the length token to the last word */
++	bcmerror = dhdpcie_bus_membytes(bus, TRUE, (phys_size - 4),
++		(uint8*)&varsizew, 4);
++
++	return bcmerror;
++} /* dhdpcie_bus_write_vars */
++
++int
++dhdpcie_downloadvars(dhd_bus_t *bus, void *arg, int len)
++{
++	int bcmerror = BCME_OK;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	/* Basic sanity checks */
++	if (bus->dhd->up) {
++		bcmerror = BCME_NOTDOWN;
++		goto err;
++	}
++	if (!len) {
++		bcmerror = BCME_BUFTOOSHORT;
++		goto err;
++	}
++
++	/* Free the old ones and replace with passed variables */
++	if (bus->vars)
++		MFREE(bus->dhd->osh, bus->vars, bus->varsz);
++
++	bus->vars = MALLOC(bus->dhd->osh, len);
++	bus->varsz = bus->vars ? len : 0;
++	if (bus->vars == NULL) {
++		bcmerror = BCME_NOMEM;
++		goto err;
++	}
++
++	/* Copy the passed variables, which should include the terminating double-null */
++	bcopy(arg, bus->vars, bus->varsz);
++
++#ifdef DHD_USE_SINGLE_NVRAM_FILE
++	if (dhd_bus_get_fw_mode(bus->dhd) == DHD_FLAG_MFG_MODE) {
++		char *sp = NULL;
++		char *ep = NULL;
++		int i;
++		char tag[2][8] = {"ccode=", "regrev="};
++
++		/* Find ccode and regrev info */
++		for (i = 0; i < 2; i++) {
++			sp = strnstr(bus->vars, tag[i], bus->varsz);
++			if (!sp) {
++				DHD_ERROR(("%s: Could not find ccode info from the nvram %s\n",
++					__FUNCTION__, bus->nv_path));
++				bcmerror = BCME_ERROR;
++				goto err;
++			}
++			sp = strchr(sp, '=');
++			ep = strchr(sp, '\0');
++			/* We assumed that string length of both ccode and
++			 * regrev values should not exceed WLC_CNTRY_BUF_SZ
++			 */
++			if (sp && ep && ((ep - sp) <= WLC_CNTRY_BUF_SZ)) {
++				sp++;
++				while (*sp != '\0') {
++					DHD_INFO(("%s: parse '%s', current sp = '%c'\n",
++						__FUNCTION__, tag[i], *sp));
++					*sp++ = '0';
++				}
++			} else {
++				DHD_ERROR(("%s: Invalid parameter format when parsing for %s\n",
++					__FUNCTION__, tag[i]));
++				bcmerror = BCME_ERROR;
++				goto err;
++			}
++		}
++	}
++#endif /* DHD_USE_SINGLE_NVRAM_FILE */
++
++
++err:
++	return bcmerror;
++}
++
++/* loop through the capability list and see if the pcie capabilty exists */
++uint8
++dhdpcie_find_pci_capability(osl_t *osh, uint8 req_cap_id)
++{
++	uint8 cap_id;
++	uint8 cap_ptr = 0;
++	uint8 byte_val;
++
++	/* check for Header type 0 */
++	byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
++	if ((byte_val & 0x7f) != PCI_HEADER_NORMAL) {
++		DHD_ERROR(("%s : PCI config header not normal.\n", __FUNCTION__));
++		goto end;
++	}
++
++	/* check if the capability pointer field exists */
++	byte_val = read_pci_cfg_byte(PCI_CFG_STAT);
++	if (!(byte_val & PCI_CAPPTR_PRESENT)) {
++		DHD_ERROR(("%s : PCI CAP pointer not present.\n", __FUNCTION__));
++		goto end;
++	}
++
++	cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR);
++	/* check if the capability pointer is 0x00 */
++	if (cap_ptr == 0x00) {
++		DHD_ERROR(("%s : PCI CAP pointer is 0x00.\n", __FUNCTION__));
++		goto end;
++	}
++
++	/* loop thr'u the capability list and see if the pcie capabilty exists */
++
++	cap_id = read_pci_cfg_byte(cap_ptr);
++
++	while (cap_id != req_cap_id) {
++		cap_ptr = read_pci_cfg_byte((cap_ptr + 1));
++		if (cap_ptr == 0x00) break;
++		cap_id = read_pci_cfg_byte(cap_ptr);
++	}
++
++end:
++	return cap_ptr;
++}
++
++void
++dhdpcie_pme_active(osl_t *osh, bool enable)
++{
++	uint8 cap_ptr;
++	uint32 pme_csr;
++
++	cap_ptr = dhdpcie_find_pci_capability(osh, PCI_CAP_POWERMGMTCAP_ID);
++
++	if (!cap_ptr) {
++		DHD_ERROR(("%s : Power Management Capability not present\n", __FUNCTION__));
++		return;
++	}
++
++	pme_csr = OSL_PCI_READ_CONFIG(osh, cap_ptr + PME_CSR_OFFSET, sizeof(uint32));
++	DHD_ERROR(("%s : pme_sts_ctrl 0x%x\n", __FUNCTION__, pme_csr));
++
++	pme_csr |= PME_CSR_PME_STAT;
++	if (enable) {
++		pme_csr |= PME_CSR_PME_EN;
++	} else {
++		pme_csr &= ~PME_CSR_PME_EN;
++	}
++
++	OSL_PCI_WRITE_CONFIG(osh, cap_ptr + PME_CSR_OFFSET, sizeof(uint32), pme_csr);
++}
++
++bool
++dhdpcie_pme_cap(osl_t *osh)
++{
++	uint8 cap_ptr;
++	uint32 pme_cap;
++
++	cap_ptr = dhdpcie_find_pci_capability(osh, PCI_CAP_POWERMGMTCAP_ID);
++
++	if (!cap_ptr) {
++		DHD_ERROR(("%s : Power Management Capability not present\n", __FUNCTION__));
++		return FALSE;
++	}
++
++	pme_cap = OSL_PCI_READ_CONFIG(osh, cap_ptr, sizeof(uint32));
++
++	DHD_ERROR(("%s : pme_cap 0x%x\n", __FUNCTION__, pme_cap));
++
++	return ((pme_cap & PME_CAP_PM_STATES) != 0);
++}
++
++uint32
++dhdpcie_lcreg(osl_t *osh, uint32 mask, uint32 val)
++{
++
++	uint8	pcie_cap;
++	uint8	lcreg_offset;	/* PCIE capability LCreg offset in the config space */
++	uint32	reg_val;
++
++
++	pcie_cap = dhdpcie_find_pci_capability(osh, PCI_CAP_PCIECAP_ID);
++
++	if (!pcie_cap) {
++		DHD_ERROR(("%s : PCIe Capability not present\n", __FUNCTION__));
++		return 0;
++	}
++
++	lcreg_offset = pcie_cap + PCIE_CAP_LINKCTRL_OFFSET;
++
++	/* set operation */
++	if (mask) {
++		/* read */
++		reg_val = OSL_PCI_READ_CONFIG(osh, lcreg_offset, sizeof(uint32));
++
++		/* modify */
++		reg_val &= ~mask;
++		reg_val |= (mask & val);
++
++		/* write */
++		OSL_PCI_WRITE_CONFIG(osh, lcreg_offset, sizeof(uint32), reg_val);
++	}
++	return OSL_PCI_READ_CONFIG(osh, lcreg_offset, sizeof(uint32));
++}
++
++
++
++uint8
++dhdpcie_clkreq(osl_t *osh, uint32 mask, uint32 val)
++{
++	uint8	pcie_cap;
++	uint32	reg_val;
++	uint8	lcreg_offset;	/* PCIE capability LCreg offset in the config space */
++
++	pcie_cap = dhdpcie_find_pci_capability(osh, PCI_CAP_PCIECAP_ID);
++
++	if (!pcie_cap) {
++		DHD_ERROR(("%s : PCIe Capability not present\n", __FUNCTION__));
++		return 0;
++	}
++
++	lcreg_offset = pcie_cap + PCIE_CAP_LINKCTRL_OFFSET;
++
++	reg_val = OSL_PCI_READ_CONFIG(osh, lcreg_offset, sizeof(uint32));
++	/* set operation */
++	if (mask) {
++		if (val)
++			reg_val |= PCIE_CLKREQ_ENAB;
++		else
++			reg_val &= ~PCIE_CLKREQ_ENAB;
++		OSL_PCI_WRITE_CONFIG(osh, lcreg_offset, sizeof(uint32), reg_val);
++		reg_val = OSL_PCI_READ_CONFIG(osh, lcreg_offset, sizeof(uint32));
++	}
++	if (reg_val & PCIE_CLKREQ_ENAB)
++		return 1;
++	else
++		return 0;
++}
++
++void dhd_dump_intr_registers(dhd_pub_t *dhd, struct bcmstrbuf *strbuf)
++{
++	uint32 intstatus = 0;
++	uint32 intmask = 0;
++	uint32 mbintstatus = 0;
++	uint32 d2h_mb_data = 0;
++
++	intstatus = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, PCIMailBoxInt, 0, 0);
++	intmask = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, PCIMailBoxMask, 0, 0);
++	mbintstatus = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, PCID2H_MailBox, 0, 0);
++	dhd_bus_cmn_readshared(dhd->bus, &d2h_mb_data, D2H_MB_DATA, 0);
++
++	bcm_bprintf(strbuf, "intstatus=0x%x intmask=0x%x mbintstatus=0x%x\n",
++		intstatus, intmask, mbintstatus);
++	bcm_bprintf(strbuf, "d2h_mb_data=0x%x def_intmask=0x%x\n",
++		d2h_mb_data, dhd->bus->def_intmask);
++	bcm_bprintf(strbuf, "\n ------- DUMPING INTR enable/disable counters-------\n");
++	bcm_bprintf(strbuf, "resume_intr_enable_count=%lu dpc_intr_enable_count=%lu\n"
++		"isr_intr_disable_count=%lu suspend_intr_disable_count=%lu\n"
++		"dpc_return_busdown_count=%lu\n",
++		dhd->bus->resume_intr_enable_count, dhd->bus->dpc_intr_enable_count,
++		dhd->bus->isr_intr_disable_count, dhd->bus->suspend_intr_disable_count,
++		dhd->bus->dpc_return_busdown_count);
++}
++
++/** Add bus dump output to a buffer */
++void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
++{
++	uint16 flowid;
++	int ix = 0;
++	flow_ring_node_t *flow_ring_node;
++	flow_info_t *flow_info;
++	char eabuf[ETHER_ADDR_STR_LEN];
++
++	if (dhdp->busstate != DHD_BUS_DATA)
++		return;
++
++#ifdef DHD_WAKE_STATUS
++	bcm_bprintf(strbuf, "wake %u rxwake %u readctrlwake %u\n",
++		bcmpcie_get_total_wake(dhdp->bus), dhdp->bus->wake_counts.rxwake,
++		dhdp->bus->wake_counts.rcwake);
++#ifdef DHD_WAKE_RX_STATUS
++	bcm_bprintf(strbuf, " unicast %u muticast %u broadcast %u arp %u\n",
++		dhdp->bus->wake_counts.rx_ucast, dhdp->bus->wake_counts.rx_mcast,
++		dhdp->bus->wake_counts.rx_bcast, dhdp->bus->wake_counts.rx_arp);
++	bcm_bprintf(strbuf, " multi4 %u multi6 %u icmp6 %u multiother %u\n",
++		dhdp->bus->wake_counts.rx_multi_ipv4, dhdp->bus->wake_counts.rx_multi_ipv6,
++		dhdp->bus->wake_counts.rx_icmpv6, dhdp->bus->wake_counts.rx_multi_other);
++	bcm_bprintf(strbuf, " icmp6_ra %u, icmp6_na %u, icmp6_ns %u\n",
++		dhdp->bus->wake_counts.rx_icmpv6_ra, dhdp->bus->wake_counts.rx_icmpv6_na,
++		dhdp->bus->wake_counts.rx_icmpv6_ns);
++#endif /* DHD_WAKE_RX_STATUS */
++#ifdef DHD_WAKE_EVENT_STATUS
++	for (flowid = 0; flowid < WLC_E_LAST; flowid++)
++		if (dhdp->bus->wake_counts.rc_event[flowid] != 0)
++			bcm_bprintf(strbuf, " %s = %u\n", bcmevent_get_name(flowid),
++				dhdp->bus->wake_counts.rc_event[flowid]);
++	bcm_bprintf(strbuf, "\n");
++#endif /* DHD_WAKE_EVENT_STATUS */
++#endif /* DHD_WAKE_STATUS */
++
++	dhd_prot_print_info(dhdp, strbuf);
++	dhd_dump_intr_registers(dhdp, strbuf);
++	bcm_bprintf(strbuf, "h2d_mb_data_ptr_addr 0x%x, d2h_mb_data_ptr_addr 0x%x\n",
++		dhdp->bus->h2d_mb_data_ptr_addr, dhdp->bus->d2h_mb_data_ptr_addr);
++	bcm_bprintf(strbuf, "dhd cumm_ctr %d\n", DHD_CUMM_CTR_READ(&dhdp->cumm_ctr));
++	bcm_bprintf(strbuf,
++		"%s %4s %2s %4s %17s %4s %4s %6s %10s %4s %4s ",
++		"Num:", "Flow", "If", "Prio", ":Dest_MacAddress:", "Qlen", "CLen", "L2CLen",
++		"Overflows", "RD", "WR");
++	bcm_bprintf(strbuf, "%5s %6s %5s \n", "Acked", "tossed", "noack");
++
++	for (flowid = 0; flowid < dhdp->num_flow_rings; flowid++) {
++		flow_ring_node = DHD_FLOW_RING(dhdp, flowid);
++		if (!flow_ring_node->active)
++			continue;
++
++		flow_info = &flow_ring_node->flow_info;
++		bcm_bprintf(strbuf,
++			"%3d. %4d %2d %4d %17s %4d %4d %6d %10u ", ix++,
++			flow_ring_node->flowid, flow_info->ifindex, flow_info->tid,
++			bcm_ether_ntoa((struct ether_addr *)&flow_info->da, eabuf),
++			DHD_FLOW_QUEUE_LEN(&flow_ring_node->queue),
++			DHD_CUMM_CTR_READ(DHD_FLOW_QUEUE_CLEN_PTR(&flow_ring_node->queue)),
++			DHD_CUMM_CTR_READ(DHD_FLOW_QUEUE_L2CLEN_PTR(&flow_ring_node->queue)),
++			DHD_FLOW_QUEUE_FAILURES(&flow_ring_node->queue));
++		dhd_prot_print_flow_ring(dhdp, flow_ring_node->prot_info, strbuf,
++			"%4d %4d ");
++		bcm_bprintf(strbuf,
++			"%5s %6s %5s\n", "NA", "NA", "NA");
++	}
++	bcm_bprintf(strbuf, "D3 inform cnt %d\n", dhdp->bus->d3_inform_cnt);
++	bcm_bprintf(strbuf, "D0 inform cnt %d\n", dhdp->bus->d0_inform_cnt);
++	bcm_bprintf(strbuf, "D0 inform in use cnt %d\n", dhdp->bus->d0_inform_in_use_cnt);
++	if (dhdp->d2h_hostrdy_supported) {
++		bcm_bprintf(strbuf, "hostready count:%d\n", dhdp->bus->hostready_count);
++	}
++#ifdef PCIE_INB_DW
++	/* Inband device wake counters */
++	if (INBAND_DW_ENAB(dhdp->bus)) {
++		bcm_bprintf(strbuf, "Inband device_wake assert count: %d\n",
++			dhdp->bus->inband_dw_assert_cnt);
++		bcm_bprintf(strbuf, "Inband device_wake deassert count: %d\n",
++			dhdp->bus->inband_dw_deassert_cnt);
++		bcm_bprintf(strbuf, "Inband DS-EXIT <host initiated> count: %d\n",
++			dhdp->bus->inband_ds_exit_host_cnt);
++		bcm_bprintf(strbuf, "Inband DS-EXIT <device initiated> count: %d\n",
++			dhdp->bus->inband_ds_exit_device_cnt);
++		bcm_bprintf(strbuf, "Inband DS-EXIT Timeout count: %d\n",
++			dhdp->bus->inband_ds_exit_to_cnt);
++		bcm_bprintf(strbuf, "Inband HOST_SLEEP-EXIT Timeout count: %d\n",
++			dhdp->bus->inband_host_sleep_exit_to_cnt);
++	}
++#endif /* PCIE_INB_DW */
++}
++
++/**
++ * Brings transmit packets on all flow rings closer to the dongle, by moving (a subset) from their
++ * flow queue to their flow ring.
++ */
++static void
++dhd_update_txflowrings(dhd_pub_t *dhd)
++{
++	unsigned long flags;
++	dll_t *item, *next;
++	flow_ring_node_t *flow_ring_node;
++	struct dhd_bus *bus = dhd->bus;
++
++	/* Hold flowring_list_lock to ensure no race condition while accessing the List */
++	DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags);
++	for (item = dll_head_p(&bus->flowring_active_list);
++		(!dhd_is_device_removed(dhd) && !dll_end(&bus->flowring_active_list, item));
++		item = next) {
++		if (dhd->hang_was_sent) {
++			break;
++		}
++
++		next = dll_next_p(item);
++		flow_ring_node = dhd_constlist_to_flowring(item);
++
++		/* Ensure that flow_ring_node in the list is Not Null */
++		ASSERT(flow_ring_node != NULL);
++
++		/* Ensure that the flowring node has valid contents */
++		ASSERT(flow_ring_node->prot_info != NULL);
++
++		dhd_prot_update_txflowring(dhd, flow_ring_node->flowid, flow_ring_node->prot_info);
++	}
++	DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags);
++}
++
++/** Mailbox ringbell Function */
++static void
++dhd_bus_gen_devmb_intr(struct dhd_bus *bus)
++{
++	if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) ||
++		(bus->sih->buscorerev == 4)) {
++		DHD_ERROR(("%s: mailbox communication not supported\n", __FUNCTION__));
++		return;
++	}
++	if (bus->db1_for_mb)  {
++		/* this is a pcie core register, not the config register */
++		DHD_INFO(("%s: writing a mail box interrupt to the device, through doorbell 1\n", __FUNCTION__));
++		si_corereg(bus->sih, bus->sih->buscoreidx, PCIH2D_DB1, ~0, 0x12345678);
++	} else {
++		DHD_INFO(("%s: writing a mail box interrupt to the device, through config space\n", __FUNCTION__));
++		dhdpcie_bus_cfg_write_dword(bus, PCISBMbx, 4, (1 << 0));
++		dhdpcie_bus_cfg_write_dword(bus, PCISBMbx, 4, (1 << 0));
++	}
++}
++
++/* Upon receiving a mailbox interrupt,
++ * if H2D_FW_TRAP bit is set in mailbox location
++ * device traps
++ */
++static void
++dhdpcie_fw_trap(dhd_bus_t *bus)
++{
++	/* Send the mailbox data and generate mailbox intr. */
++	dhdpcie_send_mb_data(bus, H2D_FW_TRAP);
++}
++
++#if defined(PCIE_OOB) || defined(PCIE_INB_DW)
++void
++dhd_bus_doorbell_timeout_reset(struct dhd_bus *bus)
++{
++	if (dhd_doorbell_timeout)
++		dhd_timeout_start(&bus->doorbell_timer,
++			(dhd_doorbell_timeout * 1000) / dhd_watchdog_ms);
++	else if (!(bus->dhd->busstate == DHD_BUS_SUSPEND)) {
++		dhd_bus_set_device_wake(bus, FALSE);
++	}
++}
++#endif /* defined(PCIE_OOB) || defined(PCIE_INB_DW) */
++
++#ifdef PCIE_INB_DW
++
++void
++dhd_bus_inb_ack_pending_ds_req(dhd_bus_t *bus)
++{
++	/* The DHD_BUS_INB_DW_LOCK must be held before
++	* calling this function !!
++	*/
++	if ((dhdpcie_bus_get_pcie_inband_dw_state(bus) ==
++		DW_DEVICE_DS_DEV_SLEEP_PEND) &&
++		(bus->host_active_cnt == 0)) {
++		dhdpcie_bus_set_pcie_inband_dw_state(bus, DW_DEVICE_DS_DEV_SLEEP);
++		dhdpcie_send_mb_data(bus, H2D_HOST_DS_ACK);
++	}
++}
++
++int
++dhd_bus_inb_set_device_wake(struct dhd_bus *bus, bool val)
++{
++	int timeleft;
++	unsigned long flags;
++	int ret;
++
++	if (!INBAND_DW_ENAB(bus)) {
++		return BCME_ERROR;
++	}
++
++	if (val) {
++		DHD_BUS_INB_DW_LOCK(bus->inb_lock, flags);
++
++		/*
++		 * Reset the Door Bell Timeout value. So that the Watchdog
++		 * doesn't try to Deassert Device Wake, while we are in
++		 * the process of still Asserting the same.
++		 */
++		if (dhd_doorbell_timeout) {
++			dhd_timeout_start(&bus->doorbell_timer,
++				(dhd_doorbell_timeout * 1000) / dhd_watchdog_ms);
++		}
++
++		if (dhdpcie_bus_get_pcie_inband_dw_state(bus) ==
++			DW_DEVICE_DS_DEV_SLEEP) {
++			/* Clear wait_for_ds_exit */
++			bus->wait_for_ds_exit = 0;
++			ret = dhdpcie_send_mb_data(bus, H2DMB_DS_DEVICE_WAKE_ASSERT);
++			if (ret != BCME_OK) {
++				DHD_ERROR(("Failed: assert Inband device_wake\n"));
++				bus->wait_for_ds_exit = 1;
++				DHD_BUS_INB_DW_UNLOCK(bus->inb_lock, flags);
++				ret = BCME_ERROR;
++				goto exit;
++			}
++			dhdpcie_bus_set_pcie_inband_dw_state(bus,
++				DW_DEVICE_DS_DISABLED_WAIT);
++			bus->inband_dw_assert_cnt++;
++		} else {
++			DHD_INFO(("Not in DS SLEEP state \n"));
++			DHD_BUS_INB_DW_UNLOCK(bus->inb_lock, flags);
++			ret = BCME_OK;
++			goto exit;
++		}
++
++		/*
++		 * Since we are going to wait/sleep .. release the lock.
++		 * The Device Wake sanity is still valid, because
++		 * a) If there is another context that comes in and tries
++		 *    to assert DS again and if it gets the lock, since
++		 *    ds_state would be now != DW_DEVICE_DS_DEV_SLEEP the
++		 *    context would return saying Not in DS Sleep.
++		 * b) If ther is another context that comes in and tries
++		 *    to de-assert DS and gets the lock,
++		 *    since the ds_state is != DW_DEVICE_DS_DEV_WAKE
++		 *    that context would return too. This can not happen
++		 *    since the watchdog is the only context that can
++		 *    De-Assert Device Wake and as the first step of
++		 *    Asserting the Device Wake, we have pushed out the
++		 *    Door Bell Timeout.
++		 *
++		 */
++		DHD_BUS_INB_DW_UNLOCK(bus->inb_lock, flags);
++
++		if (!CAN_SLEEP()) {
++			/* Called from context that cannot sleep */
++			OSL_DELAY(1000);
++			bus->wait_for_ds_exit = 1;
++		} else {
++			/* Wait for DS EXIT for DS_EXIT_TIMEOUT seconds */
++			timeleft = dhd_os_ds_exit_wait(bus->dhd, &bus->wait_for_ds_exit);
++			if (!bus->wait_for_ds_exit && timeleft == 0) {
++				DHD_ERROR(("DS-EXIT timeout\n"));
++				bus->inband_ds_exit_to_cnt++;
++				bus->ds_exit_timeout = 0;
++				ret = BCME_ERROR;
++				goto exit;
++			}
++		}
++
++		DHD_BUS_INB_DW_LOCK(bus->inb_lock, flags);
++		dhdpcie_bus_set_pcie_inband_dw_state(bus,
++			DW_DEVICE_DS_DEV_WAKE);
++		DHD_BUS_INB_DW_UNLOCK(bus->inb_lock, flags);
++
++		ret = BCME_OK;
++	} else {
++		DHD_BUS_INB_DW_LOCK(bus->inb_lock, flags);
++		if ((dhdpcie_bus_get_pcie_inband_dw_state(bus) ==
++			DW_DEVICE_DS_DEV_WAKE)) {
++			ret = dhdpcie_send_mb_data(bus, H2DMB_DS_DEVICE_WAKE_DEASSERT);
++			if (ret != BCME_OK) {
++				DHD_ERROR(("Failed: deassert Inband device_wake\n"));
++				DHD_BUS_INB_DW_UNLOCK(bus->inb_lock, flags);
++				goto exit;
++			}
++			dhdpcie_bus_set_pcie_inband_dw_state(bus,
++				DW_DEVICE_DS_ACTIVE);
++			bus->inband_dw_deassert_cnt++;
++		} else if ((dhdpcie_bus_get_pcie_inband_dw_state(bus) ==
++			DW_DEVICE_DS_DEV_SLEEP_PEND) &&
++			(bus->host_active_cnt == 0)) {
++			dhdpcie_bus_set_pcie_inband_dw_state(bus, DW_DEVICE_DS_DEV_SLEEP);
++			dhdpcie_send_mb_data(bus, H2D_HOST_DS_ACK);
++		}
++
++		ret = BCME_OK;
++		DHD_BUS_INB_DW_UNLOCK(bus->inb_lock, flags);
++	}
++
++exit:
++	return ret;
++}
++#endif /* PCIE_INB_DW */
++
++
++#if defined(PCIE_OOB) || defined(PCIE_INB_DW)
++int
++dhd_bus_set_device_wake(struct dhd_bus *bus, bool val)
++{
++	if (bus->ds_enabled) {
++#ifdef PCIE_INB_DW
++		if (INBAND_DW_ENAB(bus)) {
++			return dhd_bus_inb_set_device_wake(bus, val);
++		}
++#endif /* PCIE_INB_DW */
++#ifdef PCIE_OOB
++		if (OOB_DW_ENAB(bus)) {
++			return dhd_os_oob_set_device_wake(bus, val);
++		}
++#endif /* PCIE_OOB */
++	}
++	return BCME_OK;
++}
++#endif /* defined(PCIE_OOB) || defined(PCIE_INB_DW) */
++
++/** mailbox doorbell ring function */
++void
++dhd_bus_ringbell(struct dhd_bus *bus, uint32 value)
++{
++	/* Skip after sending D3_INFORM */
++	if (bus->dhd->busstate == DHD_BUS_SUSPEND || bus->d3_suspend_pending) {
++		DHD_ERROR(("%s: trying to ring the doorbell when in suspend state :"
++			"busstate=%d, d3_suspend_pending=%d\n",
++			__FUNCTION__, bus->dhd->busstate, bus->d3_suspend_pending));
++		return;
++	}
++	if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) ||
++		(bus->sih->buscorerev == 4)) {
++		si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxInt, PCIE_INTB, PCIE_INTB);
++	} else {
++		/* this is a pcie core register, not the config regsiter */
++		DHD_INFO(("%s: writing a door bell to the device\n", __FUNCTION__));
++		if (IDMA_ACTIVE(bus->dhd)) {
++			si_corereg(bus->sih, bus->sih->buscoreidx, PCIH2D_MailBox_2,
++				~0, value);
++		} else {
++			si_corereg(bus->sih, bus->sih->buscoreidx,
++				PCIH2D_MailBox, ~0, 0x12345678);
++		}
++	}
++}
++
++/** mailbox doorbell ring function for IDMA/IFRM using dma channel2 */
++void
++dhd_bus_ringbell_2(struct dhd_bus *bus, uint32 value, bool devwake)
++{
++	/* this is a pcie core register, not the config regsiter */
++	/* Skip after sending D3_INFORM */
++	if (bus->dhd->busstate == DHD_BUS_SUSPEND || bus->d3_suspend_pending) {
++		DHD_ERROR(("%s: trying to ring the doorbell when in suspend state :"
++			"busstate=%d, d3_suspend_pending=%d\n",
++			__FUNCTION__, bus->dhd->busstate, bus->d3_suspend_pending));
++		return;
++	}
++	DHD_INFO(("writing a door bell 2 to the device\n"));
++	si_corereg(bus->sih, bus->sih->buscoreidx, PCIH2D_MailBox_2,
++		~0, value);
++}
++
++void
++dhdpcie_bus_ringbell_fast(struct dhd_bus *bus, uint32 value)
++{
++	/* Skip after sending D3_INFORM */
++	if (bus->dhd->busstate == DHD_BUS_SUSPEND || bus->d3_suspend_pending) {
++		DHD_ERROR(("%s: trying to ring the doorbell when in suspend state :"
++			"busstate=%d, d3_suspend_pending=%d\n",
++			__FUNCTION__, bus->dhd->busstate, bus->d3_suspend_pending));
++		return;
++	}
++#if defined(PCIE_OOB) || defined(PCIE_INB_DW)
++	if (OOB_DW_ENAB(bus)) {
++		dhd_bus_set_device_wake(bus, TRUE);
++	}
++	dhd_bus_doorbell_timeout_reset(bus);
++#endif /* defined(PCIE_OOB) || defined(PCIE_INB_DW) */
++	W_REG(bus->pcie_mb_intr_osh, bus->pcie_mb_intr_addr, value);
++}
++
++void
++dhdpcie_bus_ringbell_2_fast(struct dhd_bus *bus, uint32 value, bool devwake)
++{
++	/* Skip after sending D3_INFORM */
++	if (bus->dhd->busstate == DHD_BUS_SUSPEND || bus->d3_suspend_pending) {
++		DHD_ERROR(("%s: trying to ring the doorbell when in suspend state :"
++			"busstate=%d, d3_suspend_pending=%d\n",
++			__FUNCTION__, bus->dhd->busstate, bus->d3_suspend_pending));
++		return;
++	}
++#if defined(PCIE_OOB) || defined(PCIE_INB_DW)
++	if (devwake) {
++		if (OOB_DW_ENAB(bus)) {
++			dhd_bus_set_device_wake(bus, TRUE);
++		}
++	}
++	dhd_bus_doorbell_timeout_reset(bus);
++#endif /* defined(PCIE_OOB) || defined(PCIE_INB_DW) */
++
++	W_REG(bus->pcie_mb_intr_osh, bus->pcie_mb_intr_2_addr, value);
++}
++
++static void
++dhd_bus_ringbell_oldpcie(struct dhd_bus *bus, uint32 value)
++{
++	uint32 w;
++	/* Skip after sending D3_INFORM */
++	if (bus->dhd->busstate == DHD_BUS_SUSPEND || bus->d3_suspend_pending) {
++		DHD_ERROR(("%s: trying to ring the doorbell when in suspend state :"
++			"busstate=%d, d3_suspend_pending=%d\n",
++			__FUNCTION__, bus->dhd->busstate, bus->d3_suspend_pending));
++		return;
++	}
++	w = (R_REG(bus->pcie_mb_intr_osh, bus->pcie_mb_intr_addr) & ~PCIE_INTB) | PCIE_INTB;
++	W_REG(bus->pcie_mb_intr_osh, bus->pcie_mb_intr_addr, w);
++}
++
++dhd_mb_ring_t
++dhd_bus_get_mbintr_fn(struct dhd_bus *bus)
++{
++	if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) ||
++		(bus->sih->buscorerev == 4)) {
++		bus->pcie_mb_intr_addr = si_corereg_addr(bus->sih, bus->sih->buscoreidx,
++			PCIMailBoxInt);
++		if (bus->pcie_mb_intr_addr) {
++			bus->pcie_mb_intr_osh = si_osh(bus->sih);
++			return dhd_bus_ringbell_oldpcie;
++		}
++	} else {
++		bus->pcie_mb_intr_addr = si_corereg_addr(bus->sih, bus->sih->buscoreidx,
++			PCIH2D_MailBox);
++		if (bus->pcie_mb_intr_addr) {
++			bus->pcie_mb_intr_osh = si_osh(bus->sih);
++			return dhdpcie_bus_ringbell_fast;
++		}
++	}
++	return dhd_bus_ringbell;
++}
++
++dhd_mb_ring_2_t
++dhd_bus_get_mbintr_2_fn(struct dhd_bus *bus)
++{
++	bus->pcie_mb_intr_2_addr = si_corereg_addr(bus->sih, bus->sih->buscoreidx,
++		PCIH2D_MailBox_2);
++	if (bus->pcie_mb_intr_2_addr) {
++		bus->pcie_mb_intr_osh = si_osh(bus->sih);
++		return dhdpcie_bus_ringbell_2_fast;
++	}
++	return dhd_bus_ringbell_2;
++}
++
++bool BCMFASTPATH
++dhd_bus_dpc(struct dhd_bus *bus)
++{
++	bool resched = FALSE;	  /* Flag indicating resched wanted */
++	unsigned long flags;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	/* Check for only DHD_BUS_DOWN and not for DHD_BUS_DOWN_IN_PROGRESS
++	 * to avoid IOCTL Resumed On timeout when ioctl is waiting for response
++	 * and rmmod is fired in parallel, which will make DHD_BUS_DOWN_IN_PROGRESS
++	 * and if we return from here, then IOCTL response will never be handled
++	 */
++	if (bus->dhd->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s: Bus down, ret\n", __FUNCTION__));
++		bus->intstatus = 0;
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++		bus->dpc_return_busdown_count++;
++		return 0;
++	}
++#ifdef DHD_PCIE_RUNTIMEPM
++	bus->idlecount = 0;
++#endif /* DHD_PCIE_RUNTIMEPM */
++	DHD_BUS_BUSY_SET_IN_DPC(bus->dhd);
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++#ifdef DHD_READ_INTSTATUS_IN_DPC
++	if (bus->ipend) {
++		bus->ipend = FALSE;
++		bus->intstatus = dhdpcie_bus_intstatus(bus);
++		/* Check if the interrupt is ours or not */
++		if (bus->intstatus == 0) {
++			goto INTR_ON;
++		}
++		bus->intrcount++;
++	}
++#endif /* DHD_READ_INTSTATUS_IN_DPC */
++
++	resched = dhdpcie_bus_process_mailbox_intr(bus, bus->intstatus);
++	if (!resched) {
++		bus->intstatus = 0;
++#ifdef DHD_READ_INTSTATUS_IN_DPC
++INTR_ON:
++#endif /* DHD_READ_INTSTATUS_IN_DPC */
++		bus->dpc_intr_enable_count++;
++		dhdpcie_bus_intr_enable(bus); /* Enable back interrupt using Intmask!! */
++	}
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	DHD_BUS_BUSY_CLEAR_IN_DPC(bus->dhd);
++	dhd_os_busbusy_wake(bus->dhd);
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	return resched;
++
++}
++
++
++int
++dhdpcie_send_mb_data(dhd_bus_t *bus, uint32 h2d_mb_data)
++{
++	uint32 cur_h2d_mb_data = 0;
++	unsigned long flags;
++
++	DHD_INFO_HW4(("%s: H2D_MB_DATA: 0x%08X\n", __FUNCTION__, h2d_mb_data));
++
++	if (bus->is_linkdown) {
++		DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++
++	if (bus->api.fw_rev >= PCIE_SHARED_VERSION_6 && !bus->use_mailbox) {
++		DHD_INFO(("API rev is 6, sending mb data as H2D Ctrl message to dongle, 0x%04x\n",
++			h2d_mb_data));
++		/* Prevent asserting device_wake during doorbell ring for mb data to avoid loop. */
++#ifdef PCIE_OOB
++		bus->oob_enabled = FALSE;
++#endif /* PCIE_OOB */
++		if (dhd_prot_h2d_mbdata_send_ctrlmsg(bus->dhd, h2d_mb_data)) {
++			DHD_ERROR(("failure sending the H2D Mailbox message to firmware\n"));
++			goto fail;
++		}
++#ifdef PCIE_OOB
++		bus->oob_enabled = TRUE;
++#endif /* PCIE_OOB */
++		goto done;
++	}
++
++	dhd_bus_cmn_readshared(bus, &cur_h2d_mb_data, H2D_MB_DATA, 0);
++
++	if (cur_h2d_mb_data != 0) {
++		uint32 i = 0;
++		DHD_INFO(("%s: GRRRRRRR: MB transaction is already pending 0x%04x\n", __FUNCTION__, cur_h2d_mb_data));
++		while ((i++ < 100) && cur_h2d_mb_data) {
++			OSL_DELAY(10);
++			dhd_bus_cmn_readshared(bus, &cur_h2d_mb_data, H2D_MB_DATA, 0);
++		}
++		if (i >= 100) {
++			DHD_ERROR(("%s : waited 1ms for the dngl "
++				"to ack the previous mb transaction\n", __FUNCTION__));
++			DHD_ERROR(("%s : MB transaction is still pending 0x%04x\n",
++				__FUNCTION__, cur_h2d_mb_data));
++		}
++	}
++
++	dhd_bus_cmn_writeshared(bus, &h2d_mb_data, sizeof(uint32), H2D_MB_DATA, 0);
++	dhd_bus_gen_devmb_intr(bus);
++
++done:
++	if (h2d_mb_data == H2D_HOST_D3_INFORM) {
++		DHD_INFO_HW4(("%s: send H2D_HOST_D3_INFORM to dongle\n", __FUNCTION__));
++		/* Mark D3_INFORM in the atomic context to
++		 * skip ringing H2D DB after D3_INFORM
++		 */
++		bus->d3_suspend_pending = TRUE;
++		bus->d3_inform_cnt++;
++	}
++	if (h2d_mb_data == H2D_HOST_D0_INFORM_IN_USE) {
++		DHD_INFO_HW4(("%s: send H2D_HOST_D0_INFORM_IN_USE to dongle\n", __FUNCTION__));
++		bus->d0_inform_in_use_cnt++;
++	}
++	if (h2d_mb_data == H2D_HOST_D0_INFORM) {
++		DHD_INFO_HW4(("%s: send H2D_HOST_D0_INFORM to dongle\n", __FUNCTION__));
++		bus->d0_inform_cnt++;
++	}
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++	return BCME_OK;
++
++fail:
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++	return BCME_ERROR;
++}
++
++void
++dhd_bus_handle_mb_data(dhd_bus_t *bus, uint32 d2h_mb_data)
++{
++#ifdef PCIE_INB_DW
++	unsigned long flags = 0;
++#endif
++	DHD_INFO(("D2H_MB_DATA: 0x%04x\n", d2h_mb_data));
++
++	if (d2h_mb_data & D2H_DEV_FWHALT)  {
++		DHD_ERROR(("FW trap has happened\n"));
++		dhdpcie_checkdied(bus, NULL, 0);
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#ifdef CONFIG_ARCH_MSM
++		bus->no_cfg_restore = 1;
++#endif /* CONFIG_ARCH_MSM */
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++		dhd_os_check_hang(bus->dhd, 0, -EREMOTEIO);
++		return;
++	}
++	if (d2h_mb_data & D2H_DEV_DS_ENTER_REQ)  {
++		if ((bus->dhd->busstate == DHD_BUS_SUSPEND || bus->d3_suspend_pending) &&
++			bus->wait_for_d3_ack) {
++			DHD_ERROR(("DS-ENTRY AFTER D3-ACK!!!!! QUITING\n"));
++			bus->dhd->busstate = DHD_BUS_DOWN;
++			return;
++		}
++		/* what should we do */
++		DHD_INFO(("D2H_MB_DATA: DEEP SLEEP REQ\n"));
++#ifdef PCIE_INB_DW
++		if (INBAND_DW_ENAB(bus)) {
++			DHD_BUS_INB_DW_LOCK(bus->inb_lock, flags);
++			if (dhdpcie_bus_get_pcie_inband_dw_state(bus) == DW_DEVICE_DS_ACTIVE) {
++				dhdpcie_bus_set_pcie_inband_dw_state(bus,
++						DW_DEVICE_DS_DEV_SLEEP_PEND);
++				if (bus->host_active_cnt == 0) {
++					dhdpcie_bus_set_pcie_inband_dw_state(bus,
++						DW_DEVICE_DS_DEV_SLEEP);
++					dhdpcie_send_mb_data(bus, H2D_HOST_DS_ACK);
++				}
++			}
++			DHD_BUS_INB_DW_UNLOCK(bus->inb_lock, flags);
++			dhd_os_ds_enter_wake(bus->dhd);
++		} else
++#endif /* PCIE_INB_DW */
++		{
++			dhdpcie_send_mb_data(bus, H2D_HOST_DS_ACK);
++		}
++		if (IDMA_DS_ENAB(bus->dhd)) {
++			bus->dongle_in_ds = TRUE;
++		}
++		DHD_INFO(("D2H_MB_DATA: sent DEEP SLEEP ACK\n"));
++	}
++	if (d2h_mb_data & D2H_DEV_DS_EXIT_NOTE)  {
++		/* what should we do */
++		bus->dongle_in_ds = FALSE;
++		DHD_INFO(("D2H_MB_DATA: DEEP SLEEP EXIT\n"));
++#ifdef PCIE_INB_DW
++		if (INBAND_DW_ENAB(bus)) {
++			bus->inband_ds_exit_device_cnt++;
++			DHD_BUS_INB_DW_LOCK(bus->inb_lock, flags);
++			if (dhdpcie_bus_get_pcie_inband_dw_state(bus) ==
++					DW_DEVICE_DS_DISABLED_WAIT) {
++				/* wake up only if some one is waiting in
++				* DW_DEVICE_DS_DISABLED_WAIT state
++				* in this case the waiter will change the state
++				* to DW_DEVICE_DS_DEV_WAKE
++				*/
++				bus->wait_for_ds_exit = 1;
++				DHD_BUS_INB_DW_UNLOCK(bus->inb_lock, flags);
++				dhd_os_ds_exit_wake(bus->dhd);
++			} else {
++				DHD_INFO(("D2H_MB_DATA: not in DW_DEVICE_DS_DISABLED_WAIT!\n"));
++				/*
++				* If there is no one waiting, then update the state from here
++				*/
++				bus->wait_for_ds_exit = 1;
++				dhdpcie_bus_set_pcie_inband_dw_state(bus,
++					DW_DEVICE_DS_DEV_WAKE);
++				DHD_BUS_INB_DW_UNLOCK(bus->inb_lock, flags);
++			}
++		}
++#endif /* PCIE_INB_DW */
++	}
++	if (d2h_mb_data & D2HMB_DS_HOST_SLEEP_EXIT_ACK)  {
++		/* what should we do */
++		DHD_INFO(("D2H_MB_DATA: D0 ACK\n"));
++#ifdef PCIE_INB_DW
++		if (INBAND_DW_ENAB(bus)) {
++			DHD_BUS_INB_DW_LOCK(bus->inb_lock, flags);
++			if (dhdpcie_bus_get_pcie_inband_dw_state(bus) ==
++				DW_DEVICE_HOST_WAKE_WAIT) {
++				dhdpcie_bus_set_pcie_inband_dw_state(bus, DW_DEVICE_DS_ACTIVE);
++			}
++			DHD_BUS_INB_DW_UNLOCK(bus->inb_lock, flags);
++		}
++#endif /* PCIE_INB_DW */
++	}
++	if (d2h_mb_data & D2H_DEV_D3_ACK)  {
++		/* what should we do */
++		DHD_INFO_HW4(("D2H_MB_DATA: D3 ACK\n"));
++		if (!bus->wait_for_d3_ack) {
++			/* Disable dongle Interrupts Immediately after D3 */
++			bus->suspend_intr_disable_count++;
++			dhdpcie_bus_intr_disable(bus);
++#if defined(DHD_HANG_SEND_UP_TEST)
++			if (bus->dhd->req_hang_type == HANG_REASON_D3_ACK_TIMEOUT) {
++				DHD_ERROR(("TEST HANG: Skip to process D3 ACK\n"));
++			} else {
++				bus->wait_for_d3_ack = 1;
++				dhd_os_d3ack_wake(bus->dhd);
++			}
++#else /* DHD_HANG_SEND_UP_TEST */
++			bus->wait_for_d3_ack = 1;
++			dhd_os_d3ack_wake(bus->dhd);
++#endif /* DHD_HANG_SEND_UP_TEST */
++		}
++	}
++}
++
++static void
++dhdpcie_handle_mb_data(dhd_bus_t *bus)
++{
++	uint32 d2h_mb_data = 0;
++	uint32 zero = 0;
++	dhd_bus_cmn_readshared(bus, &d2h_mb_data, D2H_MB_DATA, 0);
++	if (D2H_DEV_MB_INVALIDATED(d2h_mb_data)) {
++		DHD_ERROR(("%s: Invalid D2H_MB_DATA: 0x%08x\n",
++			__FUNCTION__, d2h_mb_data));
++		return;
++	}
++
++	dhd_bus_cmn_writeshared(bus, &zero, sizeof(uint32), D2H_MB_DATA, 0);
++
++	DHD_INFO_HW4(("%s: D2H_MB_DATA: 0x%04x\n", __FUNCTION__, d2h_mb_data));
++	if (d2h_mb_data & D2H_DEV_FWHALT)  {
++		DHD_ERROR(("FW trap has happened\n"));
++		dhdpcie_checkdied(bus, NULL, 0);
++		/* not ready yet dhd_os_ind_firmware_stall(bus->dhd); */
++		return;
++	}
++	if (d2h_mb_data & D2H_DEV_DS_ENTER_REQ)  {
++		/* what should we do */
++		DHD_INFO(("%s: D2H_MB_DATA: DEEP SLEEP REQ\n", __FUNCTION__));
++		dhdpcie_send_mb_data(bus, H2D_HOST_DS_ACK);
++		if (IDMA_DS_ENAB(bus->dhd)) {
++			bus->dongle_in_ds = TRUE;
++		}
++		DHD_INFO(("%s: D2H_MB_DATA: sent DEEP SLEEP ACK\n", __FUNCTION__));
++	}
++	if (d2h_mb_data & D2H_DEV_DS_EXIT_NOTE)  {
++		/* what should we do */
++		DHD_INFO(("%s: D2H_MB_DATA: DEEP SLEEP EXIT\n", __FUNCTION__));
++		bus->dongle_in_ds = FALSE;
++	}
++	if (d2h_mb_data & D2H_DEV_D3_ACK)  {
++		/* what should we do */
++		DHD_INFO_HW4(("%s: D2H_MB_DATA: D3 ACK\n", __FUNCTION__));
++		if (!bus->wait_for_d3_ack) {
++#if defined(DHD_HANG_SEND_UP_TEST)
++			if (bus->dhd->req_hang_type == HANG_REASON_D3_ACK_TIMEOUT) {
++				DHD_ERROR(("TEST HANG: Skip to process D3 ACK\n"));
++			} else {
++				bus->wait_for_d3_ack = 1;
++				dhd_os_d3ack_wake(bus->dhd);
++			}
++#else /* DHD_HANG_SEND_UP_TEST */
++			bus->wait_for_d3_ack = 1;
++			dhd_os_d3ack_wake(bus->dhd);
++#endif /* DHD_HANG_SEND_UP_TEST */
++		}
++	}
++}
++
++static void
++dhdpcie_read_handle_mb_data(dhd_bus_t *bus)
++{
++	uint32 d2h_mb_data = 0;
++	uint32 zero = 0;
++
++	dhd_bus_cmn_readshared(bus, &d2h_mb_data, D2H_MB_DATA, 0);
++	if (!d2h_mb_data)
++		return;
++
++	dhd_bus_cmn_writeshared(bus, &zero, sizeof(uint32), D2H_MB_DATA, 0);
++
++	dhd_bus_handle_mb_data(bus, d2h_mb_data);
++}
++
++static bool
++dhdpcie_bus_process_mailbox_intr(dhd_bus_t *bus, uint32 intstatus)
++{
++	bool resched = FALSE;
++
++	if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) ||
++		(bus->sih->buscorerev == 4)) {
++		/* Msg stream interrupt */
++		if (intstatus & I_BIT1) {
++			resched = dhdpci_bus_read_frames(bus);
++		} else if (intstatus & I_BIT0) {
++			/* do nothing for Now */
++		}
++	} else {
++		if (intstatus & (PCIE_MB_TOPCIE_FN0_0 | PCIE_MB_TOPCIE_FN0_1))
++			bus->api.handle_mb_data(bus);
++
++		if (bus->dhd->busstate == DHD_BUS_SUSPEND) {
++			goto exit;
++		}
++
++		if (intstatus & PCIE_MB_D2H_MB_MASK) {
++			resched = dhdpci_bus_read_frames(bus);
++		}
++	}
++
++exit:
++	return resched;
++}
++
++static bool
++dhdpci_bus_read_frames(dhd_bus_t *bus)
++{
++	bool more = FALSE;
++
++	/* First check if there a FW trap */
++	if ((bus->api.fw_rev >= PCIE_SHARED_VERSION_6) &&
++		(bus->dhd->dongle_trap_data = dhd_prot_process_trapbuf(bus->dhd))) {
++		dhd_bus_handle_mb_data(bus, D2H_DEV_FWHALT);
++		return FALSE;
++	}
++
++	/* There may be frames in both ctrl buf and data buf; check ctrl buf first */
++	DHD_PERIM_LOCK_ALL((bus->dhd->fwder_unit % FWDER_MAX_UNIT));
++
++	dhd_prot_process_ctrlbuf(bus->dhd);
++	/* Unlock to give chance for resp to be handled */
++	DHD_PERIM_UNLOCK_ALL((bus->dhd->fwder_unit % FWDER_MAX_UNIT));
++
++	DHD_PERIM_LOCK_ALL((bus->dhd->fwder_unit % FWDER_MAX_UNIT));
++	/* update the flow ring cpls */
++	dhd_update_txflowrings(bus->dhd);
++
++	/* With heavy TX traffic, we could get a lot of TxStatus
++	 * so add bound
++	 */
++	more |= dhd_prot_process_msgbuf_txcpl(bus->dhd, dhd_txbound);
++
++	/* With heavy RX traffic, this routine potentially could spend some time
++	 * processing RX frames without RX bound
++	 */
++	more |= dhd_prot_process_msgbuf_rxcpl(bus->dhd, dhd_rxbound);
++
++	/* Process info ring completion messages */
++	more |= dhd_prot_process_msgbuf_infocpl(bus->dhd, DHD_INFORING_BOUND);
++
++#ifdef IDLE_TX_FLOW_MGMT
++	if (bus->enable_idle_flowring_mgmt) {
++		/* Look for idle flow rings */
++		dhd_bus_check_idle_scan(bus);
++	}
++#endif /* IDLE_TX_FLOW_MGMT */
++
++	/* don't talk to the dongle if fw is about to be reloaded */
++	if (bus->dhd->hang_was_sent) {
++		more = FALSE;
++	}
++	DHD_PERIM_UNLOCK_ALL((bus->dhd->fwder_unit % FWDER_MAX_UNIT));
++
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++	if (bus->read_shm_fail) {
++		/* Read interrupt state once again to confirm linkdown */
++		int intstatus = si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxInt, 0, 0);
++		if (intstatus != (uint32)-1) {
++			DHD_ERROR(("%s: read SHM failed but intstatus is valid\n", __FUNCTION__));
++#ifdef DHD_FW_COREDUMP
++			if (bus->dhd->memdump_enabled) {
++				DHD_OS_WAKE_LOCK(bus->dhd);
++				bus->dhd->memdump_type = DUMP_TYPE_READ_SHM_FAIL;
++				dhd_bus_mem_dump(bus->dhd);
++				DHD_OS_WAKE_UNLOCK(bus->dhd);
++			}
++#endif /* DHD_FW_COREDUMP */
++			bus->dhd->hang_reason = HANG_REASON_PCIE_LINK_DOWN;
++			dhd_os_send_hang_message(bus->dhd);
++		} else {
++			DHD_ERROR(("%s: Link is Down.\n", __FUNCTION__));
++#ifdef CONFIG_ARCH_MSM
++			bus->no_cfg_restore = 1;
++#endif /* CONFIG_ARCH_MSM */
++			bus->is_linkdown = 1;
++			bus->dhd->hang_reason = HANG_REASON_PCIE_LINK_DOWN;
++			dhd_os_send_hang_message(bus->dhd);
++		}
++	}
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++	return more;
++}
++
++bool
++dhdpcie_tcm_valid(dhd_bus_t *bus)
++{
++	uint32 addr = 0;
++	int rv;
++	uint32 shaddr = 0;
++	pciedev_shared_t sh;
++
++	shaddr = bus->dongle_ram_base + bus->ramsize - 4;
++
++	/* Read last word in memory to determine address of pciedev_shared structure */
++	addr = LTOH32(dhdpcie_bus_rtcm32(bus, shaddr));
++
++	if ((addr == 0) || (addr == bus->nvram_csm) || (addr < bus->dongle_ram_base) ||
++		(addr > shaddr)) {
++		DHD_ERROR(("%s: address (0x%08x) of pciedev_shared invalid addr\n",
++			__FUNCTION__, addr));
++		return FALSE;
++	}
++
++	/* Read hndrte_shared structure */
++	if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)&sh,
++		sizeof(pciedev_shared_t))) < 0) {
++		DHD_ERROR(("Failed to read PCIe shared struct with %d\n", rv));
++		return FALSE;
++	}
++
++	/* Compare any field in pciedev_shared_t */
++	if (sh.console_addr != bus->pcie_sh->console_addr) {
++		DHD_ERROR(("Contents of pciedev_shared_t structure are not matching.\n"));
++		return FALSE;
++	}
++
++	return TRUE;
++}
++
++static void
++dhdpcie_update_bus_api_revisions(uint32 firmware_api_version, uint32 host_api_version)
++{
++	snprintf(bus_api_revision, BUS_API_REV_STR_LEN, "\nBus API revisions:(FW rev%d)(DHD rev%d)",
++			firmware_api_version, host_api_version);
++	return;
++}
++
++static bool
++dhdpcie_check_firmware_compatible(uint32 firmware_api_version, uint32 host_api_version)
++{
++	bool retcode = FALSE;
++
++	DHD_INFO(("firmware api revision %d, host api revision %d\n",
++		firmware_api_version, host_api_version));
++
++	switch (firmware_api_version) {
++	case PCIE_SHARED_VERSION_7:
++	case PCIE_SHARED_VERSION_6:
++	case PCIE_SHARED_VERSION_5:
++		retcode = TRUE;
++		break;
++	default:
++		if (firmware_api_version <= host_api_version)
++			retcode = TRUE;
++	}
++	return retcode;
++}
++
++static int
++dhdpcie_readshared(dhd_bus_t *bus)
++{
++	uint32 addr = 0;
++	int rv, dma_indx_wr_buf, dma_indx_rd_buf;
++	uint32 shaddr = 0;
++	pciedev_shared_t *sh = bus->pcie_sh;
++	dhd_timeout_t tmo;
++
++	shaddr = bus->dongle_ram_base + bus->ramsize - 4;
++	/* start a timer for 5 seconds */
++	dhd_timeout_start(&tmo, MAX_READ_TIMEOUT);
++
++	while (((addr == 0) || (addr == bus->nvram_csm)) && !dhd_timeout_expired(&tmo)) {
++		/* Read last word in memory to determine address of pciedev_shared structure */
++		addr = LTOH32(dhdpcie_bus_rtcm32(bus, shaddr));
++	}
++
++	if ((addr == 0) || (addr == bus->nvram_csm) || (addr < bus->dongle_ram_base) ||
++		(addr > shaddr)) {
++		DHD_ERROR(("%s: address (0x%08x) of pciedev_shared invalid\n",
++			__FUNCTION__, addr));
++		DHD_ERROR(("%s: Waited %u usec, dongle is not ready\n", __FUNCTION__, tmo.elapsed));
++		return BCME_ERROR;
++	} else {
++		bus->shared_addr = (ulong)addr;
++		DHD_ERROR(("%s: PCIe shared addr (0x%08x) read took %u usec "
++			"before dongle is ready\n", __FUNCTION__, addr, tmo.elapsed));
++	}
++
++	/* Read hndrte_shared structure */
++	if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)sh,
++		sizeof(pciedev_shared_t))) < 0) {
++		DHD_ERROR(("%s: Failed to read PCIe shared struct with %d\n", __FUNCTION__, rv));
++		return rv;
++	}
++
++	/* Endianness */
++	sh->flags = ltoh32(sh->flags);
++	sh->trap_addr = ltoh32(sh->trap_addr);
++	sh->assert_exp_addr = ltoh32(sh->assert_exp_addr);
++	sh->assert_file_addr = ltoh32(sh->assert_file_addr);
++	sh->assert_line = ltoh32(sh->assert_line);
++	sh->console_addr = ltoh32(sh->console_addr);
++	sh->msgtrace_addr = ltoh32(sh->msgtrace_addr);
++	sh->dma_rxoffset = ltoh32(sh->dma_rxoffset);
++	sh->rings_info_ptr = ltoh32(sh->rings_info_ptr);
++	sh->flags2 = ltoh32(sh->flags2);
++
++	/* load bus console address */
++	bus->console_addr = sh->console_addr;
++
++	/* Read the dma rx offset */
++	bus->dma_rxoffset = bus->pcie_sh->dma_rxoffset;
++	dhd_prot_rx_dataoffset(bus->dhd, bus->dma_rxoffset);
++
++	DHD_INFO(("%s: DMA RX offset from shared Area %d\n", __FUNCTION__, bus->dma_rxoffset));
++
++	bus->api.fw_rev = sh->flags & PCIE_SHARED_VERSION_MASK;
++	if (!(dhdpcie_check_firmware_compatible(bus->api.fw_rev, PCIE_SHARED_VERSION)))
++	{
++		DHD_ERROR(("%s: pcie_shared version %d in dhd "
++		           "is older than pciedev_shared version %d in dongle\n",
++		           __FUNCTION__, PCIE_SHARED_VERSION,
++		           bus->api.fw_rev));
++		return BCME_ERROR;
++	}
++	dhdpcie_update_bus_api_revisions(bus->api.fw_rev, PCIE_SHARED_VERSION);
++
++	bus->rw_index_sz = (sh->flags & PCIE_SHARED_2BYTE_INDICES) ?
++		sizeof(uint16) : sizeof(uint32);
++	DHD_INFO(("%s: Dongle advertizes %d size indices\n",
++		__FUNCTION__, bus->rw_index_sz));
++
++#ifdef IDLE_TX_FLOW_MGMT
++	if (sh->flags & PCIE_SHARED_IDLE_FLOW_RING) {
++		DHD_ERROR(("%s: FW Supports IdleFlow ring managment!\n",
++			__FUNCTION__));
++		bus->enable_idle_flowring_mgmt = TRUE;
++	}
++#endif /* IDLE_TX_FLOW_MGMT */
++
++	bus->dhd->idma_enable = (sh->flags & PCIE_SHARED_IDMA) ? TRUE : FALSE;
++	bus->dhd->ifrm_enable = (sh->flags & PCIE_SHARED_IFRM) ? TRUE : FALSE;
++
++	bus->dhd->idma_retention_ds = (sh->flags & PCIE_SHARED_IDMA_RETENTION_DS) ? TRUE : FALSE;
++
++	bus->dhd->d2h_sync_mode = sh->flags & PCIE_SHARED_D2H_SYNC_MODE_MASK;
++
++	/* Does the FW support DMA'ing r/w indices */
++	if (sh->flags & PCIE_SHARED_DMA_INDEX) {
++		if (!bus->dhd->dma_ring_upd_overwrite) {
++			{
++				if (!IFRM_ENAB(bus->dhd)) {
++					bus->dhd->dma_h2d_ring_upd_support = TRUE;
++				}
++				bus->dhd->dma_d2h_ring_upd_support = TRUE;
++			}
++		}
++
++		if (bus->dhd->dma_d2h_ring_upd_support)
++			bus->dhd->d2h_sync_mode = 0;
++
++		DHD_INFO(("%s: Host support DMAing indices: H2D:%d - D2H:%d. FW supports it\n",
++			__FUNCTION__,
++			(bus->dhd->dma_h2d_ring_upd_support ? 1 : 0),
++			(bus->dhd->dma_d2h_ring_upd_support ? 1 : 0)));
++	} else if (!(sh->flags & PCIE_SHARED_D2H_SYNC_MODE_MASK)) {
++		DHD_ERROR(("%s FW has to support either dma indices or d2h sync\n",
++			__FUNCTION__));
++		return BCME_UNSUPPORTED;
++	} else {
++		bus->dhd->dma_h2d_ring_upd_support = FALSE;
++		bus->dhd->dma_d2h_ring_upd_support = FALSE;
++	}
++
++	/* get ring_info, ring_state and mb data ptrs and store the addresses in bus structure */
++	{
++		ring_info_t  ring_info;
++
++		if ((rv = dhdpcie_bus_membytes(bus, FALSE, sh->rings_info_ptr,
++			(uint8 *)&ring_info, sizeof(ring_info_t))) < 0)
++			return rv;
++
++		bus->h2d_mb_data_ptr_addr = ltoh32(sh->h2d_mb_data_ptr);
++		bus->d2h_mb_data_ptr_addr = ltoh32(sh->d2h_mb_data_ptr);
++
++
++		if (bus->api.fw_rev >= PCIE_SHARED_VERSION_6) {
++			bus->max_tx_flowrings = ltoh16(ring_info.max_tx_flowrings);
++			bus->max_submission_rings = ltoh16(ring_info.max_submission_queues);
++			bus->max_completion_rings = ltoh16(ring_info.max_completion_rings);
++			bus->max_cmn_rings = bus->max_submission_rings - bus->max_tx_flowrings;
++			bus->api.handle_mb_data = dhdpcie_read_handle_mb_data;
++			bus->use_mailbox = sh->flags & PCIE_SHARED_USE_MAILBOX;
++		}
++		else {
++			bus->max_tx_flowrings = ltoh16(ring_info.max_tx_flowrings);
++			bus->max_submission_rings = bus->max_tx_flowrings;
++			bus->max_completion_rings = BCMPCIE_D2H_COMMON_MSGRINGS;
++			bus->max_cmn_rings = BCMPCIE_H2D_COMMON_MSGRINGS;
++			bus->api.handle_mb_data = dhdpcie_handle_mb_data;
++		}
++		if (bus->max_completion_rings == 0) {
++			DHD_ERROR(("dongle completion rings are invalid %d\n",
++				bus->max_completion_rings));
++			return BCME_ERROR;
++		}
++		if (bus->max_submission_rings == 0) {
++			DHD_ERROR(("dongle submission rings are invalid %d\n",
++				bus->max_submission_rings));
++			return BCME_ERROR;
++		}
++		if (bus->max_tx_flowrings == 0) {
++			DHD_ERROR(("dongle txflow rings are invalid %d\n", bus->max_tx_flowrings));
++			return BCME_ERROR;
++		}
++
++		/* If both FW and Host support DMA'ing indices, allocate memory and notify FW
++		 * The max_sub_queues is read from FW initialized ring_info
++		 */
++		if (bus->dhd->dma_h2d_ring_upd_support || IDMA_ENAB(bus->dhd)) {
++			dma_indx_wr_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz,
++				H2D_DMA_INDX_WR_BUF, bus->max_submission_rings);
++			dma_indx_rd_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz,
++				D2H_DMA_INDX_RD_BUF, bus->max_completion_rings);
++
++			if ((dma_indx_wr_buf != BCME_OK) || (dma_indx_rd_buf != BCME_OK)) {
++				DHD_ERROR(("%s: Failed to allocate memory for dma'ing h2d indices"
++						"Host will use w/r indices in TCM\n",
++						__FUNCTION__));
++				bus->dhd->dma_h2d_ring_upd_support = FALSE;
++				bus->dhd->idma_enable = FALSE;
++			}
++		}
++
++		if (bus->dhd->dma_d2h_ring_upd_support) {
++			dma_indx_wr_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz,
++				D2H_DMA_INDX_WR_BUF, bus->max_completion_rings);
++			dma_indx_rd_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz,
++				H2D_DMA_INDX_RD_BUF, bus->max_submission_rings);
++
++			if ((dma_indx_wr_buf != BCME_OK) || (dma_indx_rd_buf != BCME_OK)) {
++				DHD_ERROR(("%s: Failed to allocate memory for dma'ing d2h indices"
++						"Host will use w/r indices in TCM\n",
++						__FUNCTION__));
++				bus->dhd->dma_d2h_ring_upd_support = FALSE;
++			}
++		}
++
++		if (IFRM_ENAB(bus->dhd)) {
++			dma_indx_wr_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz,
++				H2D_IFRM_INDX_WR_BUF, bus->max_tx_flowrings);
++
++			if (dma_indx_wr_buf != BCME_OK) {
++				DHD_ERROR(("%s: Failed to alloc memory for Implicit DMA\n",
++						__FUNCTION__));
++				bus->dhd->ifrm_enable = FALSE;
++			}
++		}
++
++		/* read ringmem and ringstate ptrs from shared area and store in host variables */
++		dhd_fillup_ring_sharedptr_info(bus, &ring_info);
++		if (dhd_msg_level & DHD_INFO_VAL) {
++			bcm_print_bytes("ring_info_raw", (uchar *)&ring_info, sizeof(ring_info_t));
++		}
++		DHD_INFO(("%s: ring_info\n", __FUNCTION__));
++
++		DHD_ERROR(("%s: max H2D queues %d\n",
++			__FUNCTION__, ltoh16(ring_info.max_tx_flowrings)));
++
++		DHD_INFO(("mail box address\n"));
++		DHD_INFO(("%s: h2d_mb_data_ptr_addr 0x%04x\n",
++			__FUNCTION__, bus->h2d_mb_data_ptr_addr));
++		DHD_INFO(("%s: d2h_mb_data_ptr_addr 0x%04x\n",
++			__FUNCTION__, bus->d2h_mb_data_ptr_addr));
++	}
++
++	DHD_INFO(("%s: d2h_sync_mode 0x%08x\n",
++		__FUNCTION__, bus->dhd->d2h_sync_mode));
++
++	bus->dhd->d2h_hostrdy_supported =
++		((sh->flags & PCIE_SHARED_HOSTRDY_SUPPORT) == PCIE_SHARED_HOSTRDY_SUPPORT);
++
++#ifdef PCIE_OOB
++	bus->dhd->d2h_no_oob_dw = (sh->flags & PCIE_SHARED_NO_OOB_DW) ? TRUE : FALSE;
++#endif /* PCIE_OOB */
++
++#ifdef PCIE_INB_DW
++	bus->dhd->d2h_inband_dw = (sh->flags & PCIE_SHARED_INBAND_DS) ? TRUE : FALSE;
++#endif /* PCIE_INB_DW */
++
++#if defined(PCIE_OOB) && defined(PCIE_INB_DW)
++	DHD_ERROR(("FW supports Inband dw ? %s oob dw ? %s\n",
++		bus->dhd->d2h_inband_dw ? "Y":"N",
++		bus->dhd->d2h_no_oob_dw ? "N":"Y"));
++#endif /* defined(PCIE_OOB) && defined(PCIE_INB_DW) */
++
++	bus->dhd->ext_trap_data_supported =
++		((sh->flags2 & PCIE_SHARED2_EXTENDED_TRAP_DATA) == PCIE_SHARED2_EXTENDED_TRAP_DATA);
++
++	return BCME_OK;
++} /* dhdpcie_readshared */
++
++/** Read ring mem and ring state ptr info from shared memory area in device memory */
++static void
++dhd_fillup_ring_sharedptr_info(dhd_bus_t *bus, ring_info_t *ring_info)
++{
++	uint16 i = 0;
++	uint16 j = 0;
++	uint32 tcm_memloc;
++	uint32	d2h_w_idx_ptr, d2h_r_idx_ptr, h2d_w_idx_ptr, h2d_r_idx_ptr;
++	uint16  max_tx_flowrings = bus->max_tx_flowrings;
++
++	/* Ring mem ptr info */
++	/* Alloated in the order
++		H2D_MSGRING_CONTROL_SUBMIT              0
++		H2D_MSGRING_RXPOST_SUBMIT               1
++		D2H_MSGRING_CONTROL_COMPLETE            2
++		D2H_MSGRING_TX_COMPLETE                 3
++		D2H_MSGRING_RX_COMPLETE                 4
++	*/
++
++	{
++		/* ringmemptr holds start of the mem block address space */
++		tcm_memloc = ltoh32(ring_info->ringmem_ptr);
++
++		/* Find out ringmem ptr for each ring common  ring */
++		for (i = 0; i <= BCMPCIE_COMMON_MSGRING_MAX_ID; i++) {
++			bus->ring_sh[i].ring_mem_addr = tcm_memloc;
++			/* Update mem block */
++			tcm_memloc = tcm_memloc + sizeof(ring_mem_t);
++			DHD_INFO(("%s: ring id %d ring mem addr 0x%04x \n", __FUNCTION__,
++				i, bus->ring_sh[i].ring_mem_addr));
++		}
++	}
++
++	/* Ring state mem ptr info */
++	{
++		d2h_w_idx_ptr = ltoh32(ring_info->d2h_w_idx_ptr);
++		d2h_r_idx_ptr = ltoh32(ring_info->d2h_r_idx_ptr);
++		h2d_w_idx_ptr = ltoh32(ring_info->h2d_w_idx_ptr);
++		h2d_r_idx_ptr = ltoh32(ring_info->h2d_r_idx_ptr);
++
++		/* Store h2d common ring write/read pointers */
++		for (i = 0; i < BCMPCIE_H2D_COMMON_MSGRINGS; i++) {
++			bus->ring_sh[i].ring_state_w = h2d_w_idx_ptr;
++			bus->ring_sh[i].ring_state_r = h2d_r_idx_ptr;
++
++			/* update mem block */
++			h2d_w_idx_ptr = h2d_w_idx_ptr + bus->rw_index_sz;
++			h2d_r_idx_ptr = h2d_r_idx_ptr + bus->rw_index_sz;
++
++			DHD_INFO(("%s: h2d w/r : idx %d write %x read %x \n", __FUNCTION__, i,
++				bus->ring_sh[i].ring_state_w, bus->ring_sh[i].ring_state_r));
++		}
++
++		/* Store d2h common ring write/read pointers */
++		for (j = 0; j < BCMPCIE_D2H_COMMON_MSGRINGS; j++, i++) {
++			bus->ring_sh[i].ring_state_w = d2h_w_idx_ptr;
++			bus->ring_sh[i].ring_state_r = d2h_r_idx_ptr;
++
++			/* update mem block */
++			d2h_w_idx_ptr = d2h_w_idx_ptr + bus->rw_index_sz;
++			d2h_r_idx_ptr = d2h_r_idx_ptr + bus->rw_index_sz;
++
++			DHD_INFO(("%s: d2h w/r : idx %d write %x read %x \n", __FUNCTION__, i,
++				bus->ring_sh[i].ring_state_w, bus->ring_sh[i].ring_state_r));
++		}
++
++		/* Store txflow ring write/read pointers */
++		if (bus->api.fw_rev < PCIE_SHARED_VERSION_6) {
++			max_tx_flowrings -= BCMPCIE_H2D_COMMON_MSGRINGS;
++		} else {
++			/* Account for Debug info h2d ring located after the last tx flow ring */
++			max_tx_flowrings = max_tx_flowrings + 1;
++		}
++		for (j = 0; j < max_tx_flowrings; i++, j++)
++		{
++			bus->ring_sh[i].ring_state_w = h2d_w_idx_ptr;
++			bus->ring_sh[i].ring_state_r = h2d_r_idx_ptr;
++
++			/* update mem block */
++			h2d_w_idx_ptr = h2d_w_idx_ptr + bus->rw_index_sz;
++			h2d_r_idx_ptr = h2d_r_idx_ptr + bus->rw_index_sz;
++
++			DHD_INFO(("%s: FLOW Rings h2d w/r : idx %d write %x read %x \n",
++				__FUNCTION__, i,
++				bus->ring_sh[i].ring_state_w,
++				bus->ring_sh[i].ring_state_r));
++		}
++		/* store wr/rd pointers for  debug info completion ring */
++		bus->ring_sh[i].ring_state_w = d2h_w_idx_ptr;
++		bus->ring_sh[i].ring_state_r = d2h_r_idx_ptr;
++		d2h_w_idx_ptr = d2h_w_idx_ptr + bus->rw_index_sz;
++		d2h_r_idx_ptr = d2h_r_idx_ptr + bus->rw_index_sz;
++		DHD_INFO(("d2h w/r : idx %d write %x read %x \n", i,
++			bus->ring_sh[i].ring_state_w, bus->ring_sh[i].ring_state_r));
++	}
++} /* dhd_fillup_ring_sharedptr_info */
++
++/**
++ * Initialize bus module: prepare for communication with the dongle. Called after downloading
++ * firmware into the dongle.
++ */
++int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	int  ret = 0;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	ASSERT(bus->dhd);
++	if (!bus->dhd)
++		return 0;
++
++	/* Make sure we're talking to the core. */
++	bus->reg = si_setcore(bus->sih, PCIE2_CORE_ID, 0);
++	ASSERT(bus->reg != NULL);
++
++	/* before opening up bus for data transfer, check if shared are is intact */
++	ret = dhdpcie_readshared(bus);
++	if (ret < 0) {
++		DHD_ERROR(("%s :Shared area read failed \n", __FUNCTION__));
++		return ret;
++	}
++
++	/* Make sure we're talking to the core. */
++	bus->reg = si_setcore(bus->sih, PCIE2_CORE_ID, 0);
++	ASSERT(bus->reg != NULL);
++
++	/* Set bus state according to enable result */
++	dhdp->busstate = DHD_BUS_DATA;
++	bus->d3_suspend_pending = FALSE;
++
++#if defined(DBG_PKT_MON) || defined(DHD_PKT_LOGGING)
++	if (bus->pcie_sh->flags2 & PCIE_SHARED_D2H_D11_TX_STATUS) {
++		uint32 flags2 = bus->pcie_sh->flags2;
++		uint32 addr;
++
++		addr = bus->shared_addr + OFFSETOF(pciedev_shared_t, flags2);
++		flags2 |= PCIE_SHARED_H2D_D11_TX_STATUS;
++		ret = dhdpcie_bus_membytes(bus, TRUE, addr,
++			(uint8 *)&flags2, sizeof(flags2));
++		if (ret < 0) {
++			DHD_ERROR(("%s: update flag bit (H2D_D11_TX_STATUS) failed\n",
++				__FUNCTION__));
++			return ret;
++		}
++		bus->pcie_sh->flags2 = flags2;
++		bus->dhd->d11_tx_status = TRUE;
++	}
++#endif /* DBG_PKT_MON || DHD_PKT_LOGGING */
++
++	if (!dhd_download_fw_on_driverload)
++		dhd_dpc_enable(bus->dhd);
++	/* Enable the interrupt after device is up */
++	dhdpcie_bus_intr_enable(bus);
++
++	/* bcmsdh_intr_unmask(bus->sdh); */
++#ifdef DHD_PCIE_RUNTIMEPM
++	bus->idlecount = 0;
++	bus->idletime = (int32)MAX_IDLE_COUNT;
++	init_waitqueue_head(&bus->rpm_queue);
++	mutex_init(&bus->pm_lock);
++#else
++	bus->idletime = 0;
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++#ifdef PCIE_INB_DW
++	/* Initialize the lock to serialize Device Wake Inband activities */
++	if (!bus->inb_lock) {
++		bus->inb_lock = dhd_os_spin_lock_init(bus->dhd->osh);
++	}
++#endif
++
++
++	/* Make use_d0_inform TRUE for Rev 5 for backward compatibility */
++	if (bus->api.fw_rev < PCIE_SHARED_VERSION_6) {
++		bus->use_d0_inform = TRUE;
++	} else {
++		bus->use_d0_inform = FALSE;
++	}
++
++	return ret;
++}
++
++static void
++dhdpcie_init_shared_addr(dhd_bus_t *bus)
++{
++	uint32 addr = 0;
++	uint32 val = 0;
++	addr = bus->dongle_ram_base + bus->ramsize - 4;
++#ifdef DHD_PCIE_RUNTIMEPM
++	dhdpcie_runtime_bus_wake(bus->dhd, TRUE, __builtin_return_address(0));
++#endif /* DHD_PCIE_RUNTIMEPM */
++	dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val));
++}
++
++
++bool
++dhdpcie_chipmatch(uint16 vendor, uint16 device)
++{
++	if (vendor != PCI_VENDOR_ID_BROADCOM) {
++#ifndef DHD_EFI
++		DHD_ERROR(("%s: Unsupported vendor %x device %x\n", __FUNCTION__,
++			vendor, device));
++#endif /* DHD_EFI */
++		return (-ENODEV);
++	}
++
++	if ((device == BCM4350_D11AC_ID) || (device == BCM4350_D11AC2G_ID) ||
++		(device == BCM4350_D11AC5G_ID) || (device == BCM4350_CHIP_ID) ||
++		(device == BCM43569_CHIP_ID))
++		return 0;
++
++	if ((device == BCM4354_D11AC_ID) || (device == BCM4354_D11AC2G_ID) ||
++		(device == BCM4354_D11AC5G_ID) || (device == BCM4354_CHIP_ID))
++		return 0;
++
++	if ((device == BCM4356_D11AC_ID) || (device == BCM4356_D11AC2G_ID) ||
++		(device == BCM4356_D11AC5G_ID) || (device == BCM4356_CHIP_ID))
++		return 0;
++
++	if ((device == BCM4371_D11AC_ID) || (device == BCM4371_D11AC2G_ID) ||
++		(device == BCM4371_D11AC5G_ID) || (device == BCM4371_CHIP_ID))
++		return 0;
++
++	if ((device == BCM4345_D11AC_ID) || (device == BCM4345_D11AC2G_ID) ||
++		(device == BCM4345_D11AC5G_ID) || BCM4345_CHIP(device))
++		return 0;
++
++	if ((device == BCM43452_D11AC_ID) || (device == BCM43452_D11AC2G_ID) ||
++		(device == BCM43452_D11AC5G_ID))
++		return 0;
++
++	if ((device == BCM4335_D11AC_ID) || (device == BCM4335_D11AC2G_ID) ||
++		(device == BCM4335_D11AC5G_ID) || (device == BCM4335_CHIP_ID))
++		return 0;
++
++	if ((device == BCM43602_D11AC_ID) || (device == BCM43602_D11AC2G_ID) ||
++		(device == BCM43602_D11AC5G_ID) || (device == BCM43602_CHIP_ID))
++		return 0;
++
++	if ((device == BCM43569_D11AC_ID) || (device == BCM43569_D11AC2G_ID) ||
++		(device == BCM43569_D11AC5G_ID) || (device == BCM43569_CHIP_ID))
++		return 0;
++
++	if ((device == BCM4358_D11AC_ID) || (device == BCM4358_D11AC2G_ID) ||
++		(device == BCM4358_D11AC5G_ID))
++		return 0;
++
++	if ((device == BCM4349_D11AC_ID) || (device == BCM4349_D11AC2G_ID) ||
++		(device == BCM4349_D11AC5G_ID) || (device == BCM4349_CHIP_ID))
++		return 0;
++
++	if ((device == BCM4355_D11AC_ID) || (device == BCM4355_D11AC2G_ID) ||
++		(device == BCM4355_D11AC5G_ID) || (device == BCM4355_CHIP_ID))
++		return 0;
++
++	if ((device == BCM4359_D11AC_ID) || (device == BCM4359_D11AC2G_ID) ||
++		(device == BCM4359_D11AC5G_ID))
++		return 0;
++
++	if ((device == BCM43596_D11AC_ID) || (device == BCM43596_D11AC2G_ID) ||
++		(device == BCM43596_D11AC5G_ID))
++		return 0;
++
++	if ((device == BCM43597_D11AC_ID) || (device == BCM43597_D11AC2G_ID) ||
++		(device == BCM43597_D11AC5G_ID))
++		return 0;
++
++	if ((device == BCM4364_D11AC_ID) || (device == BCM4364_D11AC2G_ID) ||
++		(device == BCM4364_D11AC5G_ID) || (device == BCM4364_CHIP_ID))
++		return 0;
++
++	if ((device == BCM4347_D11AC_ID) || (device == BCM4347_D11AC2G_ID) ||
++		(device == BCM4347_D11AC5G_ID) || (device == BCM4347_CHIP_ID))
++		return 0;
++
++	if ((device == BCM4361_D11AC_ID) || (device == BCM4361_D11AC2G_ID) ||
++		(device == BCM4361_D11AC5G_ID) || (device == BCM4361_CHIP_ID))
++		return 0;
++	
++	if ((device == BCM4362_D11AX_ID) || (device == BCM4362_D11AX2G_ID) ||
++		(device == BCM4362_D11AX5G_ID) || (device == BCM4362_CHIP_ID)) {
++		return 0;
++	}
++
++	if ((device == BCM4365_D11AC_ID) || (device == BCM4365_D11AC2G_ID) ||
++		(device == BCM4365_D11AC5G_ID) || (device == BCM4365_CHIP_ID))
++		return 0;
++
++	if ((device == BCM4366_D11AC_ID) || (device == BCM4366_D11AC2G_ID) ||
++		(device == BCM4366_D11AC5G_ID) || (device == BCM4366_CHIP_ID))
++		return 0;
++#ifndef DHD_EFI
++	DHD_ERROR(("%s: Unsupported vendor %x device %x\n", __FUNCTION__, vendor, device));
++#endif
++	return (-ENODEV);
++} /* dhdpcie_chipmatch */
++
++/**
++ * Name:  dhdpcie_cc_nvmshadow
++ *
++ * Description:
++ * A shadow of OTP/SPROM exists in ChipCommon Region
++ * betw. 0x800 and 0xBFF (Backplane Addr. 0x1800_0800 and 0x1800_0BFF).
++ * Strapping option (SPROM vs. OTP), presence of OTP/SPROM and its size
++ * can also be read from ChipCommon Registers.
++ */
++static int
++dhdpcie_cc_nvmshadow(dhd_bus_t *bus, struct bcmstrbuf *b)
++{
++	uint16 dump_offset = 0;
++	uint32 dump_size = 0, otp_size = 0, sprom_size = 0;
++
++	/* Table for 65nm OTP Size (in bits) */
++	int  otp_size_65nm[8] = {0, 2048, 4096, 8192, 4096, 6144, 512, 1024};
++
++	volatile uint16 *nvm_shadow;
++
++	uint cur_coreid;
++	uint chipc_corerev;
++	chipcregs_t *chipcregs;
++
++	/* Save the current core */
++	cur_coreid = si_coreid(bus->sih);
++	/* Switch to ChipC */
++	chipcregs = (chipcregs_t *)si_setcore(bus->sih, CC_CORE_ID, 0);
++	ASSERT(chipcregs != NULL);
++
++	chipc_corerev = si_corerev(bus->sih);
++
++	/* Check ChipcommonCore Rev */
++	if (chipc_corerev < 44) {
++		DHD_ERROR(("%s: ChipcommonCore Rev %d < 44\n", __FUNCTION__, chipc_corerev));
++		return BCME_UNSUPPORTED;
++	}
++
++	/* Check ChipID */
++	if (((uint16)bus->sih->chip != BCM4350_CHIP_ID) && !BCM4345_CHIP((uint16)bus->sih->chip) &&
++	        ((uint16)bus->sih->chip != BCM4355_CHIP_ID) &&
++	        ((uint16)bus->sih->chip != BCM4364_CHIP_ID)) {
++		DHD_ERROR(("%s: cc_nvmdump cmd. supported for Olympic chips"
++					"4350/4345/4355/4364 only\n", __FUNCTION__));
++		return BCME_UNSUPPORTED;
++	}
++
++	/* Check if SRC_PRESENT in SpromCtrl(0x190 in ChipCommon Regs) is set */
++	if (chipcregs->sromcontrol & SRC_PRESENT) {
++		/* SPROM Size: 1Kbits (0x0), 4Kbits (0x1), 16Kbits(0x2) */
++		sprom_size = (1 << (2 * ((chipcregs->sromcontrol & SRC_SIZE_MASK)
++					>> SRC_SIZE_SHIFT))) * 1024;
++		bcm_bprintf(b, "\nSPROM Present (Size %d bits)\n", sprom_size);
++	}
++
++	if (chipcregs->sromcontrol & SRC_OTPPRESENT) {
++		bcm_bprintf(b, "\nOTP Present");
++
++		if (((chipcregs->otplayout & OTPL_WRAP_TYPE_MASK) >> OTPL_WRAP_TYPE_SHIFT)
++			== OTPL_WRAP_TYPE_40NM) {
++			/* 40nm OTP: Size = (OtpSize + 1) * 1024 bits */
++			/* Chipcommon rev51 is a variation on rev45 and does not support
++			 * the latest OTP configuration.
++			 */
++			if (chipc_corerev != 51 && chipc_corerev >= 49) {
++				otp_size = (((chipcregs->otplayout & OTPL_ROW_SIZE_MASK)
++					>> OTPL_ROW_SIZE_SHIFT) + 1) * 1024;
++				bcm_bprintf(b, "(Size %d bits)\n", otp_size);
++			} else {
++				otp_size =  (((chipcregs->capabilities & CC_CAP_OTPSIZE)
++				        >> CC_CAP_OTPSIZE_SHIFT) + 1) * 1024;
++				bcm_bprintf(b, "(Size %d bits)\n", otp_size);
++			}
++		} else {
++			/* This part is untested since newer chips have 40nm OTP */
++			/* Chipcommon rev51 is a variation on rev45 and does not support
++			 * the latest OTP configuration.
++			 */
++			if (chipc_corerev != 51 && chipc_corerev >= 49) {
++				otp_size = otp_size_65nm[(chipcregs->otplayout & OTPL_ROW_SIZE_MASK)
++						>> OTPL_ROW_SIZE_SHIFT];
++				bcm_bprintf(b, "(Size %d bits)\n", otp_size);
++			} else {
++				otp_size = otp_size_65nm[(chipcregs->capabilities & CC_CAP_OTPSIZE)
++					        >> CC_CAP_OTPSIZE_SHIFT];
++				bcm_bprintf(b, "(Size %d bits)\n", otp_size);
++				DHD_INFO(("%s: 65nm/130nm OTP Size not tested. \n",
++					__FUNCTION__));
++			}
++		}
++	}
++
++	/* Chipcommon rev51 is a variation on rev45 and does not support
++	 * the latest OTP configuration.
++	 */
++	if (chipc_corerev != 51 && chipc_corerev >= 49) {
++		if (((chipcregs->sromcontrol & SRC_PRESENT) == 0) &&
++			((chipcregs->otplayout & OTPL_ROW_SIZE_MASK) == 0)) {
++			DHD_ERROR(("%s: SPROM and OTP could not be found "
++				"sromcontrol = %x, otplayout = %x \n",
++				__FUNCTION__, chipcregs->sromcontrol, chipcregs->otplayout));
++			return BCME_NOTFOUND;
++		}
++	} else {
++		if (((chipcregs->sromcontrol & SRC_PRESENT) == 0) &&
++			((chipcregs->capabilities & CC_CAP_OTPSIZE) == 0)) {
++			DHD_ERROR(("%s: SPROM and OTP could not be found "
++				"sromcontrol = %x, capablities = %x \n",
++				__FUNCTION__, chipcregs->sromcontrol, chipcregs->capabilities));
++			return BCME_NOTFOUND;
++		}
++	}
++
++	/* Check the strapping option in SpromCtrl: Set = OTP otherwise SPROM */
++	if ((!(chipcregs->sromcontrol & SRC_PRESENT) || (chipcregs->sromcontrol & SRC_OTPSEL)) &&
++		(chipcregs->sromcontrol & SRC_OTPPRESENT)) {
++
++		bcm_bprintf(b, "OTP Strap selected.\n"
++		               "\nOTP Shadow in ChipCommon:\n");
++
++		dump_size = otp_size / 16 ; /* 16bit words */
++
++	} else if (((chipcregs->sromcontrol & SRC_OTPSEL) == 0) &&
++		(chipcregs->sromcontrol & SRC_PRESENT)) {
++
++		bcm_bprintf(b, "SPROM Strap selected\n"
++				"\nSPROM Shadow in ChipCommon:\n");
++
++		/* If SPROM > 8K only 8Kbits is mapped to ChipCommon (0x800 - 0xBFF) */
++		/* dump_size in 16bit words */
++		dump_size = sprom_size > 8 ? (8 * 1024) / 16 : sprom_size / 16;
++	} else {
++		DHD_ERROR(("%s: NVM Shadow does not exist in ChipCommon\n",
++			__FUNCTION__));
++		return BCME_NOTFOUND;
++	}
++
++	if (bus->regs == NULL) {
++		DHD_ERROR(("ChipCommon Regs. not initialized\n"));
++		return BCME_NOTREADY;
++	} else {
++		bcm_bprintf(b, "\n OffSet:");
++
++		/* Chipcommon rev51 is a variation on rev45 and does not support
++		 * the latest OTP configuration.
++		 */
++		if (chipc_corerev != 51 && chipc_corerev >= 49) {
++			/* Chip common can read only 8kbits,
++			* for ccrev >= 49 otp size is around 12 kbits so use GCI core
++			*/
++			nvm_shadow = (volatile uint16 *)si_setcore(bus->sih, GCI_CORE_ID, 0);
++		} else {
++			/* Point to the SPROM/OTP shadow in ChipCommon */
++			nvm_shadow = chipcregs->sromotp;
++		}
++
++		if (nvm_shadow == NULL) {
++			DHD_ERROR(("%s: NVM Shadow is not intialized\n", __FUNCTION__));
++			return BCME_NOTFOUND;
++		}
++
++		/*
++		* Read 16 bits / iteration.
++		* dump_size & dump_offset in 16-bit words
++		*/
++		while (dump_offset < dump_size) {
++			if (dump_offset % 2 == 0)
++				/* Print the offset in the shadow space in Bytes */
++				bcm_bprintf(b, "\n 0x%04x", dump_offset * 2);
++
++			bcm_bprintf(b, "\t0x%04x", *(nvm_shadow + dump_offset));
++			dump_offset += 0x1;
++		}
++	}
++
++	/* Switch back to the original core */
++	si_setcore(bus->sih, cur_coreid, 0);
++
++	return BCME_OK;
++} /* dhdpcie_cc_nvmshadow */
++
++/** Flow rings are dynamically created and destroyed */
++void dhd_bus_clean_flow_ring(dhd_bus_t *bus, void *node)
++{
++	void *pkt;
++	flow_queue_t *queue;
++	flow_ring_node_t *flow_ring_node = (flow_ring_node_t *)node;
++	unsigned long flags;
++
++	queue = &flow_ring_node->queue;
++
++#ifdef DHDTCPACK_SUPPRESS
++	/* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt,
++	 * when there is a newly coming packet from network stack.
++	 */
++	dhd_tcpack_info_tbl_clean(bus->dhd);
++#endif /* DHDTCPACK_SUPPRESS */
++
++	/* clean up BUS level info */
++	DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++
++	/* Flush all pending packets in the queue, if any */
++	while ((pkt = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) {
++		PKTFREE(bus->dhd->osh, pkt, TRUE);
++	}
++	ASSERT(DHD_FLOW_QUEUE_EMPTY(queue));
++
++	/* Reinitialise flowring's queue */
++	dhd_flow_queue_reinit(bus->dhd, queue, FLOW_RING_QUEUE_THRESHOLD);
++	flow_ring_node->status = FLOW_RING_STATUS_CLOSED;
++	flow_ring_node->active = FALSE;
++
++	DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++
++	/* Hold flowring_list_lock to ensure no race condition while accessing the List */
++	DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags);
++	dll_delete(&flow_ring_node->list);
++	DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags);
++
++	/* Release the flowring object back into the pool */
++	dhd_prot_flowrings_pool_release(bus->dhd,
++		flow_ring_node->flowid, flow_ring_node->prot_info);
++
++	/* Free the flowid back to the flowid allocator */
++	dhd_flowid_free(bus->dhd, flow_ring_node->flow_info.ifindex,
++	                flow_ring_node->flowid);
++}
++
++/**
++ * Allocate a Flow ring buffer,
++ * Init Ring buffer, send Msg to device about flow ring creation
++*/
++int
++dhd_bus_flow_ring_create_request(dhd_bus_t *bus, void *arg)
++{
++	flow_ring_node_t *flow_ring_node = (flow_ring_node_t *)arg;
++
++	DHD_INFO(("%s :Flow create\n", __FUNCTION__));
++
++	/* Send Msg to device about flow ring creation */
++	if (dhd_prot_flow_ring_create(bus->dhd, flow_ring_node) != BCME_OK)
++		return BCME_NOMEM;
++
++	return BCME_OK;
++}
++
++/** Handle response from dongle on a 'flow ring create' request */
++void
++dhd_bus_flow_ring_create_response(dhd_bus_t *bus, uint16 flowid, int32 status)
++{
++	flow_ring_node_t *flow_ring_node;
++	unsigned long flags;
++
++	DHD_INFO(("%s :Flow Response %d \n", __FUNCTION__, flowid));
++
++	flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid);
++	ASSERT(flow_ring_node->flowid == flowid);
++
++	if (status != BCME_OK) {
++		DHD_ERROR(("%s Flow create Response failure error status = %d \n",
++		     __FUNCTION__, status));
++		/* Call Flow clean up */
++		dhd_bus_clean_flow_ring(bus, flow_ring_node);
++		return;
++	}
++
++	DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++	flow_ring_node->status = FLOW_RING_STATUS_OPEN;
++	DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++
++	/* Now add the Flow ring node into the active list
++	 * Note that this code to add the newly created node to the active
++	 * list was living in dhd_flowid_lookup. But note that after
++	 * adding the node to the active list the contents of node is being
++	 * filled in dhd_prot_flow_ring_create.
++	 * If there is a D2H interrupt after the node gets added to the
++	 * active list and before the node gets populated with values
++	 * from the Bottom half dhd_update_txflowrings would be called.
++	 * which will then try to walk through the active flow ring list,
++	 * pickup the nodes and operate on them. Now note that since
++	 * the function dhd_prot_flow_ring_create is not finished yet
++	 * the contents of flow_ring_node can still be NULL leading to
++	 * crashes. Hence the flow_ring_node should be added to the
++	 * active list only after its truely created, which is after
++	 * receiving the create response message from the Host.
++	 */
++	DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags);
++	dll_prepend(&bus->flowring_active_list, &flow_ring_node->list);
++	DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags);
++
++	dhd_bus_schedule_queue(bus, flowid, FALSE); /* from queue to flowring */
++
++	return;
++}
++
++int
++dhd_bus_flow_ring_delete_request(dhd_bus_t *bus, void *arg)
++{
++	void * pkt;
++	flow_queue_t *queue;
++	flow_ring_node_t *flow_ring_node;
++	unsigned long flags;
++
++	DHD_INFO(("%s :Flow Delete\n", __FUNCTION__));
++
++	flow_ring_node = (flow_ring_node_t *)arg;
++
++	DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++	if (flow_ring_node->status == FLOW_RING_STATUS_DELETE_PENDING) {
++		DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++		DHD_ERROR(("%s :Delete Pending flowid %u\n", __FUNCTION__, flow_ring_node->flowid));
++		return BCME_ERROR;
++	}
++	flow_ring_node->status = FLOW_RING_STATUS_DELETE_PENDING;
++
++	queue = &flow_ring_node->queue; /* queue associated with flow ring */
++
++#ifdef DHDTCPACK_SUPPRESS
++	/* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt,
++	 * when there is a newly coming packet from network stack.
++	 */
++	dhd_tcpack_info_tbl_clean(bus->dhd);
++#endif /* DHDTCPACK_SUPPRESS */
++	/* Flush all pending packets in the queue, if any */
++	while ((pkt = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) {
++		PKTFREE(bus->dhd->osh, pkt, TRUE);
++	}
++	ASSERT(DHD_FLOW_QUEUE_EMPTY(queue));
++
++	DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++
++	/* Send Msg to device about flow ring deletion */
++	dhd_prot_flow_ring_delete(bus->dhd, flow_ring_node);
++
++	return BCME_OK;
++}
++
++void
++dhd_bus_flow_ring_delete_response(dhd_bus_t *bus, uint16 flowid, uint32 status)
++{
++	flow_ring_node_t *flow_ring_node;
++
++	DHD_INFO(("%s :Flow Delete Response %d \n", __FUNCTION__, flowid));
++
++	flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid);
++	ASSERT(flow_ring_node->flowid == flowid);
++
++	if (status != BCME_OK) {
++		DHD_ERROR(("%s Flow Delete Response failure error status = %d \n",
++		    __FUNCTION__, status));
++		return;
++	}
++	/* Call Flow clean up */
++	dhd_bus_clean_flow_ring(bus, flow_ring_node);
++
++	return;
++
++}
++
++int dhd_bus_flow_ring_flush_request(dhd_bus_t *bus, void *arg)
++{
++	void *pkt;
++	flow_queue_t *queue;
++	flow_ring_node_t *flow_ring_node;
++	unsigned long flags;
++
++	DHD_INFO(("%s :Flow Flush\n", __FUNCTION__));
++
++	flow_ring_node = (flow_ring_node_t *)arg;
++
++	DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++	queue = &flow_ring_node->queue; /* queue associated with flow ring */
++	/* Flow ring status will be set back to FLOW_RING_STATUS_OPEN
++	 * once flow ring flush response is received for this flowring node.
++	 */
++	flow_ring_node->status = FLOW_RING_STATUS_FLUSH_PENDING;
++
++#ifdef DHDTCPACK_SUPPRESS
++	/* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt,
++	 * when there is a newly coming packet from network stack.
++	 */
++	dhd_tcpack_info_tbl_clean(bus->dhd);
++#endif /* DHDTCPACK_SUPPRESS */
++
++	/* Flush all pending packets in the queue, if any */
++	while ((pkt = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) {
++		PKTFREE(bus->dhd->osh, pkt, TRUE);
++	}
++	ASSERT(DHD_FLOW_QUEUE_EMPTY(queue));
++
++	DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++
++	/* Send Msg to device about flow ring flush */
++	dhd_prot_flow_ring_flush(bus->dhd, flow_ring_node);
++
++	return BCME_OK;
++}
++
++void
++dhd_bus_flow_ring_flush_response(dhd_bus_t *bus, uint16 flowid, uint32 status)
++{
++	flow_ring_node_t *flow_ring_node;
++
++	if (status != BCME_OK) {
++		DHD_ERROR(("%s Flow flush Response failure error status = %d \n",
++		    __FUNCTION__, status));
++		return;
++	}
++
++	flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid);
++	ASSERT(flow_ring_node->flowid == flowid);
++
++	flow_ring_node->status = FLOW_RING_STATUS_OPEN;
++	return;
++}
++
++uint32
++dhd_bus_max_h2d_queues(struct dhd_bus *bus)
++{
++	return bus->max_submission_rings;
++}
++
++/* To be symmetric with SDIO */
++void
++dhd_bus_pktq_flush(dhd_pub_t *dhdp)
++{
++	return;
++}
++
++void
++dhd_bus_set_linkdown(dhd_pub_t *dhdp, bool val)
++{
++	dhdp->bus->is_linkdown = val;
++}
++
++#ifdef IDLE_TX_FLOW_MGMT
++/* resume request */
++int
++dhd_bus_flow_ring_resume_request(dhd_bus_t *bus, void *arg)
++{
++	flow_ring_node_t *flow_ring_node = (flow_ring_node_t *)arg;
++
++	DHD_ERROR(("%s :Flow Resume Request flow id %u\n", __FUNCTION__, flow_ring_node->flowid));
++
++	flow_ring_node->status = FLOW_RING_STATUS_RESUME_PENDING;
++
++	/* Send Msg to device about flow ring resume */
++	dhd_prot_flow_ring_resume(bus->dhd, flow_ring_node);
++
++	return BCME_OK;
++}
++
++/* add the node back to active flowring */
++void
++dhd_bus_flow_ring_resume_response(dhd_bus_t *bus, uint16 flowid, int32 status)
++{
++
++	flow_ring_node_t *flow_ring_node;
++
++	DHD_TRACE(("%s :flowid %d \n", __FUNCTION__, flowid));
++
++	flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid);
++	ASSERT(flow_ring_node->flowid == flowid);
++
++	if (status != BCME_OK) {
++		DHD_ERROR(("%s Error Status = %d \n",
++			__FUNCTION__, status));
++		return;
++	}
++
++	DHD_TRACE(("%s :Number of pkts queued in FlowId:%d is -> %u!!\n",
++		__FUNCTION__, flow_ring_node->flowid,  flow_ring_node->queue.len));
++
++	flow_ring_node->status = FLOW_RING_STATUS_OPEN;
++
++	dhd_bus_schedule_queue(bus, flowid, FALSE);
++	return;
++}
++
++/* scan the flow rings in active list for idle time out */
++void
++dhd_bus_check_idle_scan(dhd_bus_t *bus)
++{
++	uint64 time_stamp; /* in millisec */
++	uint64 diff;
++
++	time_stamp = OSL_SYSUPTIME();
++	diff = time_stamp - bus->active_list_last_process_ts;
++
++	if (diff > IDLE_FLOW_LIST_TIMEOUT) {
++		dhd_bus_idle_scan(bus);
++		bus->active_list_last_process_ts = OSL_SYSUPTIME();
++	}
++
++	return;
++}
++
++
++/* scan the nodes in active list till it finds a non idle node */
++void
++dhd_bus_idle_scan(dhd_bus_t *bus)
++{
++	dll_t *item, *prev;
++	flow_ring_node_t *flow_ring_node;
++	uint64 time_stamp, diff;
++	unsigned long flags;
++	uint16 ringid[MAX_SUSPEND_REQ];
++	uint16 count = 0;
++
++	time_stamp = OSL_SYSUPTIME();
++	DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags);
++
++	for (item = dll_tail_p(&bus->flowring_active_list);
++	         !dll_end(&bus->flowring_active_list, item); item = prev) {
++		prev = dll_prev_p(item);
++
++		flow_ring_node = dhd_constlist_to_flowring(item);
++
++		if (flow_ring_node->flowid == (bus->max_submission_rings - 1))
++			continue;
++
++		if (flow_ring_node->status != FLOW_RING_STATUS_OPEN) {
++			/* Takes care of deleting zombie rings */
++			/* delete from the active list */
++			DHD_INFO(("deleting flow id %u from active list\n",
++				flow_ring_node->flowid));
++			__dhd_flow_ring_delete_from_active_list(bus, flow_ring_node);
++			continue;
++		}
++
++		diff = time_stamp - flow_ring_node->last_active_ts;
++
++		if ((diff > IDLE_FLOW_RING_TIMEOUT) && !(flow_ring_node->queue.len))  {
++			DHD_ERROR(("\nSuspending flowid %d\n", flow_ring_node->flowid));
++			/* delete from the active list */
++			__dhd_flow_ring_delete_from_active_list(bus, flow_ring_node);
++			flow_ring_node->status = FLOW_RING_STATUS_SUSPENDED;
++			ringid[count] = flow_ring_node->flowid;
++			count++;
++			if (count == MAX_SUSPEND_REQ) {
++				/* create a batch message now!! */
++				dhd_prot_flow_ring_batch_suspend_request(bus->dhd, ringid, count);
++				count = 0;
++			}
++
++		} else {
++
++			/* No more scanning, break from here! */
++			break;
++		}
++	}
++
++	if (count) {
++		dhd_prot_flow_ring_batch_suspend_request(bus->dhd, ringid, count);
++	}
++
++	DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags);
++
++	return;
++}
++
++void dhd_flow_ring_move_to_active_list_head(struct dhd_bus *bus, flow_ring_node_t *flow_ring_node)
++{
++	unsigned long flags;
++	dll_t* list;
++
++	DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags);
++	/* check if the node is already at head, otherwise delete it and prepend */
++	list = dll_head_p(&bus->flowring_active_list);
++	if (&flow_ring_node->list != list) {
++		dll_delete(&flow_ring_node->list);
++		dll_prepend(&bus->flowring_active_list, &flow_ring_node->list);
++	}
++
++	/* update flow ring timestamp */
++	flow_ring_node->last_active_ts = OSL_SYSUPTIME();
++
++	DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags);
++
++	return;
++}
++
++void dhd_flow_ring_add_to_active_list(struct dhd_bus *bus, flow_ring_node_t *flow_ring_node)
++{
++	unsigned long flags;
++
++	DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags);
++
++	dll_prepend(&bus->flowring_active_list, &flow_ring_node->list);
++	/* update flow ring timestamp */
++	flow_ring_node->last_active_ts = OSL_SYSUPTIME();
++
++	DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags);
++
++	return;
++}
++void __dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus, flow_ring_node_t *flow_ring_node)
++{
++	dll_delete(&flow_ring_node->list);
++}
++
++void dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus, flow_ring_node_t *flow_ring_node)
++{
++	unsigned long flags;
++
++	DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags);
++
++	__dhd_flow_ring_delete_from_active_list(bus, flow_ring_node);
++
++	DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags);
++
++	return;
++}
++#endif /* IDLE_TX_FLOW_MGMT */
++
++int
++dhdpcie_bus_clock_start(struct dhd_bus *bus)
++{
++	return dhdpcie_start_host_pcieclock(bus);
++}
++
++int
++dhdpcie_bus_clock_stop(struct dhd_bus *bus)
++{
++	return dhdpcie_stop_host_pcieclock(bus);
++}
++
++int
++dhdpcie_bus_disable_device(struct dhd_bus *bus)
++{
++	return dhdpcie_disable_device(bus);
++}
++
++int
++dhdpcie_bus_enable_device(struct dhd_bus *bus)
++{
++	return dhdpcie_enable_device(bus);
++}
++
++int
++dhdpcie_bus_alloc_resource(struct dhd_bus *bus)
++{
++	return dhdpcie_alloc_resource(bus);
++}
++
++void
++dhdpcie_bus_free_resource(struct dhd_bus *bus)
++{
++	dhdpcie_free_resource(bus);
++}
++
++int
++dhd_bus_request_irq(struct dhd_bus *bus)
++{
++	return dhdpcie_bus_request_irq(bus);
++}
++
++bool
++dhdpcie_bus_dongle_attach(struct dhd_bus *bus)
++{
++	return dhdpcie_dongle_attach(bus);
++}
++
++int
++dhd_bus_release_dongle(struct dhd_bus *bus)
++{
++	bool dongle_isolation;
++	osl_t *osh;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus) {
++		osh = bus->osh;
++		ASSERT(osh);
++
++		if (bus->dhd) {
++			dongle_isolation = bus->dhd->dongle_isolation;
++			dhdpcie_bus_release_dongle(bus, osh, dongle_isolation, TRUE);
++		}
++	}
++
++	return 0;
++}
++
++void
++dhdpcie_cto_init(struct dhd_bus *bus, bool enable)
++{
++	if (enable) {
++		dhdpcie_bus_cfg_write_dword(bus, PCI_INT_MASK, 4,
++			PCI_CTO_INT_MASK | PCI_SBIM_MASK_SERR);
++		dhdpcie_bus_cfg_write_dword(bus, PCI_SPROM_CONTROL, 4, SPROM_BACKPLANE_EN);
++
++		if (bus->dhd->cto_threshold == 0) {
++			bus->dhd->cto_threshold = PCIE_CTO_TO_THRESH_DEFAULT;
++		}
++
++		si_corereg(bus->sih, bus->sih->buscoreidx,
++				OFFSETOF(sbpcieregs_t, ctoctrl), ~0,
++				((bus->dhd->cto_threshold << PCIE_CTO_TO_THRESHOLD_SHIFT) &
++				PCIE_CTO_TO_THRESHHOLD_MASK) |
++				((PCIE_CTO_CLKCHKCNT_VAL << PCIE_CTO_CLKCHKCNT_SHIFT) &
++				PCIE_CTO_CLKCHKCNT_MASK) |
++				PCIE_CTO_ENAB_MASK);
++	} else {
++		dhdpcie_bus_cfg_write_dword(bus, PCI_INT_MASK, 4, 0);
++		dhdpcie_bus_cfg_write_dword(bus, PCI_SPROM_CONTROL, 4, 0);
++
++		si_corereg(bus->sih, bus->sih->buscoreidx,
++				OFFSETOF(sbpcieregs_t, ctoctrl), ~0, 0);
++	}
++}
++
++static void
++dhdpcie_cto_error_recovery(struct dhd_bus *bus)
++{
++	uint32 pci_intmask, err_status;
++	uint8 i = 0;
++
++	pci_intmask = dhdpcie_bus_cfg_read_dword(bus, PCI_INT_MASK, 4);
++	dhdpcie_bus_cfg_write_dword(bus, PCI_INT_MASK, 4, pci_intmask & ~PCI_CTO_INT_MASK);
++
++	DHD_OS_WAKE_LOCK(bus->dhd);
++
++	/* reset backplane */
++	dhdpcie_bus_cfg_write_dword(bus, PCI_SPROM_CONTROL, 4, SPROM_CFG_TO_SB_RST);
++
++	/* clear timeout error */
++	while (1) {
++		err_status =  si_corereg(bus->sih, bus->sih->buscoreidx,
++			OFFSETOF(sbpcieregs_t, dm_errlog),
++			0, 0);
++		if (err_status & PCIE_CTO_ERR_MASK) {
++			si_corereg(bus->sih, bus->sih->buscoreidx,
++					OFFSETOF(sbpcieregs_t, dm_errlog),
++					~0, PCIE_CTO_ERR_MASK);
++		} else {
++			break;
++		}
++		OSL_DELAY(CTO_TO_CLEAR_WAIT_MS * 1000);
++		i++;
++		if (i > CTO_TO_CLEAR_WAIT_MAX_CNT) {
++			DHD_ERROR(("cto recovery fail\n"));
++
++			DHD_OS_WAKE_UNLOCK(bus->dhd);
++			return;
++		}
++	}
++
++	/* clear interrupt status */
++	dhdpcie_bus_cfg_write_dword(bus, PCI_INT_STATUS, 4, PCI_CTO_INT_MASK);
++
++	/* Halt ARM & remove reset */
++	/* TBD : we can add ARM Halt here in case */
++
++	DHD_ERROR(("cto recovery success\n"));
++
++	DHD_OS_WAKE_UNLOCK(bus->dhd);
++}
++
++#ifdef BCMPCIE_OOB_HOST_WAKE
++int
++dhd_bus_oob_intr_register(dhd_pub_t *dhdp)
++{
++	return dhdpcie_oob_intr_register(dhdp->bus);
++}
++
++void
++dhd_bus_oob_intr_unregister(dhd_pub_t *dhdp)
++{
++	dhdpcie_oob_intr_unregister(dhdp->bus);
++}
++
++void
++dhd_bus_oob_intr_set(dhd_pub_t *dhdp, bool enable)
++{
++	dhdpcie_oob_intr_set(dhdp->bus, enable);
++}
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++
++
++
++bool
++dhdpcie_bus_get_pcie_hostready_supported(dhd_bus_t *bus)
++{
++	return bus->dhd->d2h_hostrdy_supported;
++}
++
++void
++dhd_pcie_dump_core_regs(dhd_pub_t * pub, uint32 index, uint32 first_addr, uint32 last_addr)
++{
++	dhd_bus_t *bus = pub->bus;
++	uint32	coreoffset = index << 12;
++	uint32	core_addr = SI_ENUM_BASE + coreoffset;
++	uint32 value;
++
++
++	while (first_addr <= last_addr) {
++		core_addr = SI_ENUM_BASE + coreoffset + first_addr;
++		if (si_backplane_access(bus->sih, core_addr, 4, &value, TRUE) != BCME_OK) {
++			DHD_ERROR(("Invalid size/addr combination \n"));
++		}
++		DHD_ERROR(("[0x%08x]: 0x%08x\n", core_addr, value));
++		first_addr = first_addr + 4;
++	}
++}
++
++#ifdef PCIE_OOB
++bool
++dhdpcie_bus_get_pcie_oob_dw_supported(dhd_bus_t *bus)
++{
++	if (!bus->dhd)
++		return FALSE;
++	if (bus->oob_enabled) {
++		return !bus->dhd->d2h_no_oob_dw;
++	} else {
++		return FALSE;
++	}
++}
++#endif /* PCIE_OOB */
++
++void
++dhdpcie_bus_enab_pcie_dw(dhd_bus_t *bus, uint8 dw_option)
++{
++	DHD_ERROR(("ENABLING DW:%d\n", dw_option));
++	bus->dw_option = dw_option;
++}
++
++#ifdef PCIE_INB_DW
++bool
++dhdpcie_bus_get_pcie_inband_dw_supported(dhd_bus_t *bus)
++{
++	if (!bus->dhd)
++		return FALSE;
++	if (bus->inb_enabled) {
++		return bus->dhd->d2h_inband_dw;
++	} else {
++		return FALSE;
++	}
++}
++
++void
++dhdpcie_bus_set_pcie_inband_dw_state(dhd_bus_t *bus, enum dhd_bus_ds_state state)
++{
++	if (!INBAND_DW_ENAB(bus))
++		return;
++
++	DHD_INFO(("%s:%d\n", __FUNCTION__, state));
++	bus->dhd->ds_state = state;
++	if (state == DW_DEVICE_DS_DISABLED_WAIT || state == DW_DEVICE_DS_D3_INFORM_WAIT) {
++		bus->ds_exit_timeout = 100;
++	}
++	if (state == DW_DEVICE_HOST_WAKE_WAIT) {
++		bus->host_sleep_exit_timeout = 100;
++	}
++	if (state == DW_DEVICE_DS_DEV_WAKE) {
++		bus->ds_exit_timeout = 0;
++	}
++	if (state == DW_DEVICE_DS_ACTIVE) {
++		bus->host_sleep_exit_timeout = 0;
++	}
++}
++
++enum dhd_bus_ds_state
++dhdpcie_bus_get_pcie_inband_dw_state(dhd_bus_t *bus)
++{
++	if (!INBAND_DW_ENAB(bus))
++		return DW_DEVICE_DS_INVALID;
++	return bus->dhd->ds_state;
++}
++#endif /* PCIE_INB_DW */
++
++bool
++dhdpcie_bus_get_pcie_idma_supported(dhd_bus_t *bus)
++{
++	if (!bus->dhd)
++		return FALSE;
++	else if (bus->idma_enabled) {
++		return bus->dhd->idma_enable;
++	} else {
++		return FALSE;
++	}
++}
++
++bool
++dhdpcie_bus_get_pcie_ifrm_supported(dhd_bus_t *bus)
++{
++	if (!bus->dhd)
++		return FALSE;
++	else if (bus->ifrm_enabled) {
++		return bus->dhd->ifrm_enable;
++	} else {
++		return FALSE;
++	}
++}
++
++
++void
++dhd_bus_dump_trap_info(dhd_bus_t *bus, struct bcmstrbuf *strbuf)
++{
++	trap_t *tr = &bus->dhd->last_trap_info;
++	bcm_bprintf(strbuf,
++		"\nTRAP type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
++		" lp 0x%x, rpc 0x%x"
++		"\nTrap offset 0x%x, r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, "
++		"r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n\n",
++		ltoh32(tr->type), ltoh32(tr->epc), ltoh32(tr->cpsr), ltoh32(tr->spsr),
++		ltoh32(tr->r13), ltoh32(tr->r14), ltoh32(tr->pc),
++		ltoh32(bus->pcie_sh->trap_addr),
++		ltoh32(tr->r0), ltoh32(tr->r1), ltoh32(tr->r2), ltoh32(tr->r3),
++		ltoh32(tr->r4), ltoh32(tr->r5), ltoh32(tr->r6), ltoh32(tr->r7));
++}
++
++int
++dhd_bus_readwrite_bp_addr(dhd_pub_t *dhdp, uint addr, uint size, uint* data, bool read)
++{
++	int bcmerror = 0;
++	struct dhd_bus *bus = dhdp->bus;
++
++	if (si_backplane_access(bus->sih, addr, size, data, read) != BCME_OK) {
++			DHD_ERROR(("Invalid size/addr combination \n"));
++			bcmerror = BCME_ERROR;
++	}
++
++	return bcmerror;
++}
++
++int
++dhd_get_idletime(dhd_pub_t *dhd)
++{
++	return dhd->bus->idletime;
++}
++
++#ifdef DHD_SSSR_DUMP
++
++static INLINE void
++dhd_sbreg_op(dhd_pub_t *dhd, uint addr, uint *val, bool read)
++{
++	OSL_DELAY(1);
++	si_backplane_access(dhd->bus->sih, addr, sizeof(uint), val, read);
++	DHD_ERROR(("%s: addr:0x%x val:0x%x read:%d\n", __FUNCTION__, addr, *val, read));
++	return;
++}
++
++static int
++dhdpcie_get_sssr_fifo_dump(dhd_pub_t *dhd, uint *buf, uint fifo_size,
++	uint addr_reg, uint data_reg)
++{
++	uint addr;
++	uint val = 0;
++	int i;
++
++	DHD_ERROR(("%s\n", __FUNCTION__));
++
++	if (!buf) {
++		DHD_ERROR(("%s: buf is NULL\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	if (!fifo_size) {
++		DHD_ERROR(("%s: fifo_size is 0\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	/* Set the base address offset to 0 */
++	addr = addr_reg;
++	val = 0;
++	dhd_sbreg_op(dhd, addr, &val, FALSE);
++
++	addr = data_reg;
++	/* Read 4 bytes at once and loop for fifo_size / 4 */
++	for (i = 0; i < fifo_size / 4; i++) {
++		si_backplane_access(dhd->bus->sih, addr, sizeof(uint), &val, TRUE);
++		buf[i] = val;
++		OSL_DELAY(1);
++	}
++	return BCME_OK;
++}
++
++static int
++dhdpcie_get_sssr_vasip_dump(dhd_pub_t *dhd, uint *buf, uint fifo_size,
++	uint addr_reg)
++{
++	uint addr;
++	uint val = 0;
++	int i;
++
++	DHD_ERROR(("%s\n", __FUNCTION__));
++
++	if (!buf) {
++		DHD_ERROR(("%s: buf is NULL\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	if (!fifo_size) {
++		DHD_ERROR(("%s: fifo_size is 0\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	/* Check if vasip clk is disabled, if yes enable it */
++	addr = dhd->sssr_reg_info.vasip_regs.wrapper_regs.ioctrl;
++	dhd_sbreg_op(dhd, addr, &val, TRUE);
++	if (!val) {
++		val = 1;
++		dhd_sbreg_op(dhd, addr, &val, FALSE);
++	}
++
++	addr = addr_reg;
++	/* Read 4 bytes at once and loop for fifo_size / 4 */
++	for (i = 0; i < fifo_size / 4; i++, addr += 4) {
++		si_backplane_access(dhd->bus->sih, addr, sizeof(uint), &val, TRUE);
++		buf[i] = val;
++		OSL_DELAY(1);
++	}
++	return BCME_OK;
++}
++
++static int
++dhdpcie_resume_chipcommon_powerctrl(dhd_pub_t *dhd)
++{
++	uint addr;
++	uint val;
++
++	DHD_ERROR(("%s\n", __FUNCTION__));
++
++	/* conditionally clear bits [11:8] of PowerCtrl */
++	addr = dhd->sssr_reg_info.chipcommon_regs.base_regs.powerctrl;
++	dhd_sbreg_op(dhd, addr, &val, TRUE);
++	if (!(val & dhd->sssr_reg_info.chipcommon_regs.base_regs.powerctrl_mask)) {
++		addr = dhd->sssr_reg_info.chipcommon_regs.base_regs.powerctrl;
++		val = dhd->sssr_reg_info.chipcommon_regs.base_regs.powerctrl_mask;
++		dhd_sbreg_op(dhd, addr, &val, FALSE);
++	}
++	return BCME_OK;
++}
++
++static int
++dhdpcie_suspend_chipcommon_powerctrl(dhd_pub_t *dhd)
++{
++	uint addr;
++	uint val;
++
++	DHD_ERROR(("%s\n", __FUNCTION__));
++
++	/* conditionally clear bits [11:8] of PowerCtrl */
++	addr = dhd->sssr_reg_info.chipcommon_regs.base_regs.powerctrl;
++	dhd_sbreg_op(dhd, addr, &val, TRUE);
++	if (val & dhd->sssr_reg_info.chipcommon_regs.base_regs.powerctrl_mask) {
++		addr = dhd->sssr_reg_info.chipcommon_regs.base_regs.powerctrl;
++		val = 0;
++		dhd_sbreg_op(dhd, addr, &val, FALSE);
++	}
++	return BCME_OK;
++}
++
++static int
++dhdpcie_clear_intmask_and_timer(dhd_pub_t *dhd)
++{
++	uint addr;
++	uint val;
++
++	DHD_ERROR(("%s\n", __FUNCTION__));
++
++	/* clear chipcommon intmask */
++	addr = dhd->sssr_reg_info.chipcommon_regs.base_regs.intmask;
++	val = 0x0;
++	dhd_sbreg_op(dhd, addr, &val, FALSE);
++
++	/* clear PMUIntMask0 */
++	addr = dhd->sssr_reg_info.pmu_regs.base_regs.pmuintmask0;
++	val = 0x0;
++	dhd_sbreg_op(dhd, addr, &val, FALSE);
++
++	/* clear PMUIntMask1 */
++	addr = dhd->sssr_reg_info.pmu_regs.base_regs.pmuintmask1;
++	val = 0x0;
++	dhd_sbreg_op(dhd, addr, &val, FALSE);
++
++	/* clear res_req_timer */
++	addr = dhd->sssr_reg_info.pmu_regs.base_regs.resreqtimer;
++	val = 0x0;
++	dhd_sbreg_op(dhd, addr, &val, FALSE);
++
++	/* clear macresreqtimer */
++	addr = dhd->sssr_reg_info.pmu_regs.base_regs.macresreqtimer;
++	val = 0x0;
++	dhd_sbreg_op(dhd, addr, &val, FALSE);
++
++	/* clear macresreqtimer1 */
++	addr = dhd->sssr_reg_info.pmu_regs.base_regs.macresreqtimer1;
++	val = 0x0;
++	dhd_sbreg_op(dhd, addr, &val, FALSE);
++
++	/* clear VasipClkEn */
++	if (dhd->sssr_reg_info.vasip_regs.vasip_sr_size) {
++		addr = dhd->sssr_reg_info.vasip_regs.wrapper_regs.ioctrl;
++		val = 0x0;
++		dhd_sbreg_op(dhd, addr, &val, FALSE);
++	}
++
++	return BCME_OK;
++}
++
++static int
++dhdpcie_d11_check_outofreset(dhd_pub_t *dhd)
++{
++	int i;
++	uint addr;
++	uint val = 0;
++
++	DHD_ERROR(("%s\n", __FUNCTION__));
++
++	for (i = 0; i < MAX_NUM_D11CORES; i++) {
++		/* Check if bit 0 of resetctrl is cleared */
++		addr = dhd->sssr_reg_info.mac_regs[i].wrapper_regs.resetctrl;
++		dhd_sbreg_op(dhd, addr, &val, TRUE);
++		if (!(val & 1)) {
++			dhd->sssr_d11_outofreset[i] = TRUE;
++		} else {
++			dhd->sssr_d11_outofreset[i] = FALSE;
++		}
++		DHD_ERROR(("%s: sssr_d11_outofreset[%d] : %d\n",
++			__FUNCTION__, i, dhd->sssr_d11_outofreset[i]));
++	}
++	return BCME_OK;
++}
++
++static int
++dhdpcie_d11_clear_clk_req(dhd_pub_t *dhd)
++{
++	int i;
++	uint addr;
++	uint val = 0;
++
++	DHD_ERROR(("%s\n", __FUNCTION__));
++
++	for (i = 0; i < MAX_NUM_D11CORES; i++) {
++		if (dhd->sssr_d11_outofreset[i]) {
++			/* clear request clk only if itopoobb is non zero */
++			addr = dhd->sssr_reg_info.mac_regs[i].wrapper_regs.itopoobb;
++			dhd_sbreg_op(dhd, addr, &val, TRUE);
++			if (val != 0) {
++				/* clear clockcontrolstatus */
++				addr = dhd->sssr_reg_info.mac_regs[i].base_regs.clockcontrolstatus;
++				val =
++				dhd->sssr_reg_info.mac_regs[i].base_regs.clockcontrolstatus_val;
++				dhd_sbreg_op(dhd, addr, &val, FALSE);
++			}
++		}
++	}
++	return BCME_OK;
++}
++
++static int
++dhdpcie_arm_clear_clk_req(dhd_pub_t *dhd)
++{
++	uint addr;
++	uint val = 0;
++
++	DHD_ERROR(("%s\n", __FUNCTION__));
++
++	/* Check if bit 0 of resetctrl is cleared */
++	addr = dhd->sssr_reg_info.arm_regs.wrapper_regs.resetctrl;
++	dhd_sbreg_op(dhd, addr, &val, TRUE);
++	if (!(val & 1)) {
++		/* clear request clk only if itopoobb is non zero */
++		addr = dhd->sssr_reg_info.arm_regs.wrapper_regs.itopoobb;
++		dhd_sbreg_op(dhd, addr, &val, TRUE);
++		if (val != 0) {
++			/* clear clockcontrolstatus */
++			addr = dhd->sssr_reg_info.arm_regs.base_regs.clockcontrolstatus;
++			val = dhd->sssr_reg_info.arm_regs.base_regs.clockcontrolstatus_val;
++			dhd_sbreg_op(dhd, addr, &val, FALSE);
++		}
++	}
++	return BCME_OK;
++}
++
++static int
++dhdpcie_pcie_clear_clk_req(dhd_pub_t *dhd)
++{
++	uint addr;
++	uint val = 0;
++
++	DHD_ERROR(("%s\n", __FUNCTION__));
++
++	/* clear request clk only if itopoobb is non zero */
++	addr = dhd->sssr_reg_info.pcie_regs.wrapper_regs.itopoobb;
++	dhd_sbreg_op(dhd, addr, &val, TRUE);
++	if (val) {
++		/* clear clockcontrolstatus */
++		addr = dhd->sssr_reg_info.pcie_regs.base_regs.clockcontrolstatus;
++		val = dhd->sssr_reg_info.pcie_regs.base_regs.clockcontrolstatus_val;
++		dhd_sbreg_op(dhd, addr, &val, FALSE);
++	}
++	return BCME_OK;
++}
++
++static int
++dhdpcie_pcie_send_ltrsleep(dhd_pub_t *dhd)
++{
++	uint addr;
++	uint val = 0;
++
++	DHD_ERROR(("%s\n", __FUNCTION__));
++
++	addr = dhd->sssr_reg_info.pcie_regs.base_regs.ltrstate;
++	val = LTR_ACTIVE;
++	dhd_sbreg_op(dhd, addr, &val, FALSE);
++
++	val = LTR_SLEEP;
++	dhd_sbreg_op(dhd, addr, &val, FALSE);
++
++	return BCME_OK;
++}
++
++static int
++dhdpcie_clear_clk_req(dhd_pub_t *dhd)
++{
++	DHD_ERROR(("%s\n", __FUNCTION__));
++
++	dhdpcie_arm_clear_clk_req(dhd);
++
++	dhdpcie_d11_clear_clk_req(dhd);
++
++	dhdpcie_pcie_clear_clk_req(dhd);
++
++	return BCME_OK;
++}
++
++static int
++dhdpcie_bring_d11_outofreset(dhd_pub_t *dhd)
++{
++	int i;
++	uint addr;
++	uint val = 0;
++
++	DHD_ERROR(("%s\n", __FUNCTION__));
++
++	for (i = 0; i < MAX_NUM_D11CORES; i++) {
++		if (dhd->sssr_d11_outofreset[i]) {
++			/* disable core by setting bit 0 */
++			addr = dhd->sssr_reg_info.mac_regs[i].wrapper_regs.resetctrl;
++			val = 1;
++			dhd_sbreg_op(dhd, addr, &val, FALSE);
++			OSL_DELAY(6000);
++
++			addr = dhd->sssr_reg_info.mac_regs[i].wrapper_regs.ioctrl;
++			val = dhd->sssr_reg_info.mac_regs[0].wrapper_regs.ioctrl_resetseq_val[0];
++			dhd_sbreg_op(dhd, addr, &val, FALSE);
++
++			val = dhd->sssr_reg_info.mac_regs[0].wrapper_regs.ioctrl_resetseq_val[1];
++			dhd_sbreg_op(dhd, addr, &val, FALSE);
++
++			/* enable core by clearing bit 0 */
++			addr = dhd->sssr_reg_info.mac_regs[i].wrapper_regs.resetctrl;
++			val = 0;
++			dhd_sbreg_op(dhd, addr, &val, FALSE);
++
++			addr = dhd->sssr_reg_info.mac_regs[i].wrapper_regs.ioctrl;
++			val = dhd->sssr_reg_info.mac_regs[0].wrapper_regs.ioctrl_resetseq_val[2];
++			dhd_sbreg_op(dhd, addr, &val, FALSE);
++
++			val = dhd->sssr_reg_info.mac_regs[0].wrapper_regs.ioctrl_resetseq_val[3];
++			dhd_sbreg_op(dhd, addr, &val, FALSE);
++
++			val = dhd->sssr_reg_info.mac_regs[0].wrapper_regs.ioctrl_resetseq_val[4];
++			dhd_sbreg_op(dhd, addr, &val, FALSE);
++		}
++	}
++	return BCME_OK;
++}
++
++static int
++dhdpcie_sssr_dump_get_before_sr(dhd_pub_t *dhd)
++{
++	int i;
++
++	DHD_ERROR(("%s\n", __FUNCTION__));
++
++	for (i = 0; i < MAX_NUM_D11CORES; i++) {
++		if (dhd->sssr_d11_outofreset[i]) {
++			dhdpcie_get_sssr_fifo_dump(dhd, dhd->sssr_d11_before[i],
++				dhd->sssr_reg_info.mac_regs[i].sr_size,
++				dhd->sssr_reg_info.mac_regs[i].base_regs.xmtaddress,
++				dhd->sssr_reg_info.mac_regs[i].base_regs.xmtdata);
++		}
++	}
++
++	if (dhd->sssr_reg_info.vasip_regs.vasip_sr_size) {
++		dhdpcie_get_sssr_vasip_dump(dhd, dhd->sssr_vasip_buf_before,
++			dhd->sssr_reg_info.vasip_regs.vasip_sr_size,
++			dhd->sssr_reg_info.vasip_regs.vasip_sr_addr);
++	}
++
++	return BCME_OK;
++}
++
++static int
++dhdpcie_sssr_dump_get_after_sr(dhd_pub_t *dhd)
++{
++	int i;
++
++	DHD_ERROR(("%s\n", __FUNCTION__));
++
++	for (i = 0; i < MAX_NUM_D11CORES; i++) {
++		if (dhd->sssr_d11_outofreset[i]) {
++			dhdpcie_get_sssr_fifo_dump(dhd, dhd->sssr_d11_after[i],
++				dhd->sssr_reg_info.mac_regs[i].sr_size,
++				dhd->sssr_reg_info.mac_regs[i].base_regs.xmtaddress,
++				dhd->sssr_reg_info.mac_regs[i].base_regs.xmtdata);
++		}
++	}
++
++	if (dhd->sssr_reg_info.vasip_regs.vasip_sr_size) {
++		dhdpcie_get_sssr_vasip_dump(dhd, dhd->sssr_vasip_buf_after,
++			dhd->sssr_reg_info.vasip_regs.vasip_sr_size,
++			dhd->sssr_reg_info.vasip_regs.vasip_sr_addr);
++	}
++
++	return BCME_OK;
++}
++
++int
++dhdpcie_sssr_dump(dhd_pub_t *dhd)
++{
++	if (!dhd->sssr_inited) {
++		DHD_ERROR(("%s: SSSR not inited\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	if (dhd->bus->is_linkdown) {
++		DHD_ERROR(("%s: PCIe link is down\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	dhdpcie_d11_check_outofreset(dhd);
++
++	DHD_ERROR(("%s: Collecting Dump before SR\n", __FUNCTION__));
++	if (dhdpcie_sssr_dump_get_before_sr(dhd) != BCME_OK) {
++		DHD_ERROR(("%s: dhdpcie_sssr_dump_get_before_sr failed\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	dhdpcie_clear_intmask_and_timer(dhd);
++	dhdpcie_suspend_chipcommon_powerctrl(dhd);
++	dhdpcie_clear_clk_req(dhd);
++	dhdpcie_pcie_send_ltrsleep(dhd);
++
++	/* Wait for some time before Restore */
++	OSL_DELAY(6000);
++
++	dhdpcie_resume_chipcommon_powerctrl(dhd);
++	dhdpcie_bring_d11_outofreset(dhd);
++
++	DHD_ERROR(("%s: Collecting Dump after SR\n", __FUNCTION__));
++	if (dhdpcie_sssr_dump_get_after_sr(dhd) != BCME_OK) {
++		DHD_ERROR(("%s: dhdpcie_sssr_dump_get_after_sr failed\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	dhd_schedule_sssr_dump(dhd);
++
++	return BCME_OK;
++}
++#endif /* DHD_SSSR_DUMP */
++
++#ifdef DHD_WAKE_STATUS
++wake_counts_t*
++dhd_bus_get_wakecount(dhd_pub_t *dhd)
++{
++	if (!dhd->bus) {
++		return NULL;
++	}
++	return &dhd->bus->wake_counts;
++}
++int
++dhd_bus_get_bus_wake(dhd_pub_t *dhd)
++{
++	return bcmpcie_set_get_wake(dhd->bus, 0);
++}
++#endif /* DHD_WAKE_STATUS */
++
++#ifdef BCM_ASLR_HEAP
++/* Writes random number(s) to the TCM. FW upon initialization reads the metadata
++ * of the random number and then based on metadata, reads the random number from the TCM.
++ */
++static void
++dhdpcie_wrt_rnd(struct dhd_bus *bus)
++{
++	bcm_rand_metadata_t rnd_data;
++	uint32 rand_no;
++	uint32 count = 1;	/* start with 1 random number */
++
++	uint32 addr = bus->dongle_ram_base + (bus->ramsize - BCM_NVRAM_OFFSET_TCM) -
++		((bus->nvram_csm & 0xffff)* BCM_NVRAM_IMG_COMPRS_FACTOR + sizeof(rnd_data));
++	rnd_data.signature = htol32(BCM_RNG_SIGNATURE);
++	rnd_data.count = htol32(count);
++	/* write the metadata about random number */
++	dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&rnd_data, sizeof(rnd_data));
++	/* scale back by number of random number counts */
++	addr -= sizeof(count) * count;
++	/* Now write the random number(s) */
++	rand_no = htol32(dhd_get_random_number());
++	dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&rand_no, sizeof(rand_no));
++}
++#endif /* BCM_ASLR_HEAP */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_pcie.h b/module_drivers/drivers/net/wireless/bcmdhd/dhd_pcie.h
+new file mode 100644
+index 000000000..92b07c6e4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_pcie.h
+@@ -0,0 +1,607 @@
++/*
++ * Linux DHD Bus Module for PCIE
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_pcie.h 707536 2017-06-28 04:23:48Z $
++ */
++
++
++#ifndef dhd_pcie_h
++#define dhd_pcie_h
++
++#include <bcmpcie.h>
++#include <hnd_cons.h>
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#ifdef CONFIG_ARCH_MSM
++#ifdef CONFIG_PCI_MSM
++#include <linux/msm_pcie.h>
++#else
++#include <mach/msm_pcie.h>
++#endif /* CONFIG_PCI_MSM */
++#endif /* CONFIG_ARCH_MSM */
++#ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
++#if defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS8895)
++#include <linux/exynos-pci-noti.h>
++extern int exynos_pcie_register_event(struct exynos_pcie_register_event *reg);
++extern int exynos_pcie_deregister_event(struct exynos_pcie_register_event *reg);
++#endif /* CONFIG_SOC_EXYNOS8890 || CONFIG_SOC_EXYNOS8895 */
++#endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++
++#ifdef DHD_PCIE_RUNTIMEPM
++#include <linux/mutex.h>
++#include <linux/wait.h>
++
++#define DEFAULT_DHD_RUNTIME_MS 100
++#ifndef CUSTOM_DHD_RUNTIME_MS
++#define CUSTOM_DHD_RUNTIME_MS DEFAULT_DHD_RUNTIME_MS
++#endif /* CUSTOM_DHD_RUNTIME_MS */
++
++
++#ifndef MAX_IDLE_COUNT
++#define MAX_IDLE_COUNT 16
++#endif /* MAX_IDLE_COUNT */
++
++#ifndef MAX_RESUME_WAIT
++#define MAX_RESUME_WAIT 100
++#endif /* MAX_RESUME_WAIT */
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++/* defines */
++
++#define PCMSGBUF_HDRLEN 0
++#define DONGLE_REG_MAP_SIZE (32 * 1024)
++#define DONGLE_TCM_MAP_SIZE (4096 * 1024)
++#define DONGLE_MIN_MEMSIZE (128 *1024)
++#ifdef DHD_DEBUG
++#define DHD_PCIE_SUCCESS 0
++#define DHD_PCIE_FAILURE 1
++#endif /* DHD_DEBUG */
++#define	REMAP_ENAB(bus)			((bus)->remap)
++#define	REMAP_ISADDR(bus, a)		(((a) >= ((bus)->orig_ramsize)) && ((a) < ((bus)->ramsize)))
++
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#ifdef CONFIG_ARCH_MSM
++#define struct_pcie_notify		struct msm_pcie_notify
++#define struct_pcie_register_event	struct msm_pcie_register_event
++#endif /* CONFIG_ARCH_MSM */
++#ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
++#if defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS8895)
++#define struct_pcie_notify		struct exynos_pcie_notify
++#define struct_pcie_register_event	struct exynos_pcie_register_event
++#endif /* CONFIG_SOC_EXYNOS8890 || CONFIG_SOC_EXYNOS8895 */
++#endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++
++#define MAX_DHD_TX_FLOWS	320
++
++/* user defined data structures */
++/* Device console log buffer state */
++#define CONSOLE_LINE_MAX	192
++#define CONSOLE_BUFFER_MAX	(8 * 1024)
++
++#ifdef IDLE_TX_FLOW_MGMT
++#define IDLE_FLOW_LIST_TIMEOUT 5000
++#define IDLE_FLOW_RING_TIMEOUT 5000
++#endif /* IDLE_TX_FLOW_MGMT */
++
++#ifdef DEVICE_TX_STUCK_DETECT
++#define DEVICE_TX_STUCK_CKECK_TIMEOUT	1000 /* 1 sec */
++#define DEVICE_TX_STUCK_TIMEOUT		10000 /* 10 secs */
++#define DEVICE_TX_STUCK_WARN_DURATION (DEVICE_TX_STUCK_TIMEOUT / DEVICE_TX_STUCK_CKECK_TIMEOUT)
++#define DEVICE_TX_STUCK_DURATION (DEVICE_TX_STUCK_WARN_DURATION * 2)
++#endif /* DEVICE_TX_STUCK_DETECT */
++
++/* implicit DMA for h2d wr and d2h rd indice from Host memory to TCM */
++#define IDMA_ENAB(dhd)		((dhd)->idma_enable)
++#define IDMA_ACTIVE(dhd)	(((dhd)->idma_enable) && ((dhd)->idma_inited))
++
++#define IDMA_DS_ENAB(dhd)	((dhd)->idma_retention_ds)
++#define IDMA_DS_ACTIVE(dhd)	((dhd)->bus->dongle_in_ds)
++
++/* IFRM (Implicit Flow Ring Manager enable and inited */
++#define IFRM_ENAB(dhd)		((dhd)->ifrm_enable)
++#define IFRM_ACTIVE(dhd)	(((dhd)->ifrm_enable) && ((dhd)->ifrm_inited))
++
++/* PCIE CTO Prevention and Recovery */
++#define PCIECTO_ENAB(dhd)		((dhd)->cto_enable)
++
++/* Implicit DMA index usage :
++ * Index 0 for h2d write index transfer
++ * Index 1 for d2h read index transfer
++ */
++#define IDMA_IDX0 0
++#define IDMA_IDX1 1
++#define IDMA_IDX2 2
++#define IDMA_IDX3 3
++
++#define DHDPCIE_CONFIG_HDR_SIZE 16
++#define DHDPCIE_CONFIG_CHECK_DELAY_MS 10 /* 10ms */
++#define DHDPCIE_CONFIG_CHECK_RETRY_COUNT 20
++#define DHDPCIE_DONGLE_PWR_TOGGLE_DELAY 1000 /* 1ms in units of us */
++#define DHDPCIE_PM_D3_DELAY 200000 /* 200ms in units of us */
++#define DHDPCIE_PM_D2_DELAY 200 /* 200us */
++
++typedef struct dhd_console {
++	 uint		count;	/* Poll interval msec counter */
++	 uint		log_addr;		 /* Log struct address (fixed) */
++	 hnd_log_t	 log;			 /* Log struct (host copy) */
++	 uint		 bufsize;		 /* Size of log buffer */
++	 uint8		 *buf;			 /* Log buffer (host copy) */
++	 uint		 last;			 /* Last buffer read index */
++} dhd_console_t;
++
++typedef struct ring_sh_info {
++	uint32 ring_mem_addr;
++	uint32 ring_state_w;
++	uint32 ring_state_r;
++} ring_sh_info_t;
++
++
++#define DEVICE_WAKE_NONE	0
++#define DEVICE_WAKE_OOB		1
++#define DEVICE_WAKE_INB		2
++
++#define INBAND_DW_ENAB(bus)		((bus)->dw_option == DEVICE_WAKE_INB)
++#define OOB_DW_ENAB(bus)		((bus)->dw_option == DEVICE_WAKE_OOB)
++#define NO_DW_ENAB(bus)			((bus)->dw_option == DEVICE_WAKE_NONE)
++
++struct dhd_bus;
++
++struct dhd_pcie_rev {
++	uint8	fw_rev;
++	void (*handle_mb_data)(struct dhd_bus *);
++};
++
++typedef struct dhdpcie_config_save
++{
++	uint32 header[DHDPCIE_CONFIG_HDR_SIZE];
++	/* pmcsr save */
++	uint32 pmcsr;
++	/* express save */
++	uint32 exp_dev_ctrl_stat;
++	uint32 exp_link_ctrl_stat;
++	uint32 exp_dev_ctrl_stat2;
++	uint32 exp_link_ctrl_stat2;
++	/* msi save */
++	uint32 msi_cap;
++	uint32 msi_addr0;
++	uint32 msi_addr1;
++	uint32 msi_data;
++	/* l1pm save */
++	uint32 l1pm0;
++	uint32 l1pm1;
++	/* ltr save */
++	uint32 ltr;
++	/* aer save */
++	uint32 aer_caps_ctrl; /* 0x18 */
++	uint32 aer_severity;  /* 0x0C */
++	uint32 aer_umask;     /* 0x08 */
++	uint32 aer_cmask;     /* 0x14 */
++	uint32 aer_root_cmd;  /* 0x2c */
++	/* BAR0 and BAR1 windows */
++	uint32 bar0_win;
++	uint32 bar1_win;
++} dhdpcie_config_save_t;
++
++typedef struct dhd_bus {
++	dhd_pub_t	*dhd;
++	struct pci_dev  *rc_dev;	/* pci RC device handle */
++	struct pci_dev  *dev;		/* pci device handle */
++#ifdef DHD_EFI
++	void *pcie_dev;
++#endif
++
++	dll_t		flowring_active_list; /* constructed list of tx flowring queues */
++#ifdef IDLE_TX_FLOW_MGMT
++	uint64		active_list_last_process_ts;
++						/* stores the timestamp of active list processing */
++#endif /* IDLE_TX_FLOW_MGMT */
++
++#ifdef DEVICE_TX_STUCK_DETECT
++	/* Flag to enable/disable device tx stuck monitor by DHD IOVAR dev_tx_stuck_monitor */
++	uint32 dev_tx_stuck_monitor;
++	/* Stores the timestamp (msec) of the last device Tx stuck check */
++	uint32	device_tx_stuck_check;
++#endif /* DEVICE_TX_STUCK_DETECT */
++
++	si_t		*sih;			/* Handle for SI calls */
++	char		*vars;			/* Variables (from CIS and/or other) */
++	uint		varsz;			/* Size of variables buffer */
++	uint32		sbaddr;			/* Current SB window pointer (-1, invalid) */
++	sbpcieregs_t	*reg;			/* Registers for PCIE core */
++
++	uint		armrev;			/* CPU core revision */
++	uint		ramrev;			/* SOCRAM core revision */
++	uint32		ramsize;		/* Size of RAM in SOCRAM (bytes) */
++	uint32		orig_ramsize;		/* Size of RAM in SOCRAM (bytes) */
++	bool		ramsize_adjusted;	/* flag to note adjustment, so that
++						 * adjustment routine and file io
++						 * are avoided on D3 cold -> D0
++						 */
++	uint32		srmemsize;		/* Size of SRMEM */
++
++	uint32		bus;			/* gSPI or SDIO bus */
++	uint32		intstatus;		/* Intstatus bits (events) pending */
++	bool		dpc_sched;		/* Indicates DPC schedule (intrpt rcvd) */
++	bool		fcstate;		/* State of dongle flow-control */
++
++	uint16		cl_devid;		/* cached devid for dhdsdio_probe_attach() */
++	char		*fw_path;		/* module_param: path to firmware image */
++	char		*nv_path;		/* module_param: path to nvram vars file */
++#ifdef CACHE_FW_IMAGES
++	int			processed_nvram_params_len;	/* Modified len of NVRAM info */
++#endif
++
++
++	struct pktq	txq;			/* Queue length used for flow-control */
++
++	bool		intr;			/* Use interrupts */
++	bool		poll;			/* Use polling */
++	bool		ipend;			/* Device interrupt is pending */
++	bool		intdis;			/* Interrupts disabled by isr */
++	uint		intrcount;		/* Count of device interrupt callbacks */
++	uint		lastintrs;		/* Count as of last watchdog timer */
++
++	dhd_console_t	console;		/* Console output polling support */
++	uint		console_addr;		/* Console address from shared struct */
++
++	bool		alp_only;		/* Don't use HT clock (ALP only) */
++
++	bool		remap;		/* Contiguous 1MB RAM: 512K socram + 512K devram
++					 * Available with socram rev 16
++					 * Remap region not DMA-able
++					 */
++	uint32		resetinstr;
++	uint32		dongle_ram_base;
++
++	ulong		shared_addr;
++	pciedev_shared_t	*pcie_sh;
++	bool bus_flowctrl;
++	uint32		dma_rxoffset;
++	volatile char	*regs;		/* pci device memory va */
++	volatile char	*tcm;		/* pci device memory va */
++	osl_t		*osh;
++	uint32		nvram_csm;	/* Nvram checksum */
++	uint16		pollrate;
++	uint16  polltick;
++
++	volatile uint32  *pcie_mb_intr_addr;
++	volatile uint32  *pcie_mb_intr_2_addr;
++	void    *pcie_mb_intr_osh;
++	bool	sleep_allowed;
++
++	wake_counts_t	wake_counts;
++
++	/* version 3 shared struct related info start */
++	ring_sh_info_t	ring_sh[BCMPCIE_COMMON_MSGRINGS + MAX_DHD_TX_FLOWS];
++
++	uint8	h2d_ring_count;
++	uint8	d2h_ring_count;
++	uint32  ringmem_ptr;
++	uint32  ring_state_ptr;
++
++	uint32 d2h_dma_scratch_buffer_mem_addr;
++
++	uint32 h2d_mb_data_ptr_addr;
++	uint32 d2h_mb_data_ptr_addr;
++	/* version 3 shared struct related info end */
++
++	uint32 def_intmask;
++	bool	ltrsleep_on_unload;
++	uint	wait_for_d3_ack;
++	uint16	max_tx_flowrings;
++	uint16	max_submission_rings;
++	uint16	max_completion_rings;
++	uint16	max_cmn_rings;
++	uint32	rw_index_sz;
++	bool	db1_for_mb;
++
++	dhd_timeout_t doorbell_timer;
++	bool	device_wake_state;
++#ifdef PCIE_OOB
++	bool	oob_enabled;
++#endif /* PCIE_OOB */
++	bool	irq_registered;
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#if defined(CONFIG_ARCH_MSM) || (defined(EXYNOS_PCIE_LINKDOWN_RECOVERY) && \
++	defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS8895))
++#ifdef CONFIG_ARCH_MSM
++	uint8 no_cfg_restore;
++#endif /* CONFIG_ARCH_MSM */
++	struct_pcie_register_event pcie_event;
++#endif /* CONFIG_ARCH_MSM || (EXYNOS_PCIE_LINKDOWN_RECOVERY &&
++	* (CONFIG_SOC_EXYNOS8890 || CONFIG_SOC_EXYNOS8895))
++	*/
++	bool read_shm_fail;
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++	int32 idletime;                 /* Control for activity timeout */
++#ifdef DHD_PCIE_RUNTIMEPM
++	int32 idlecount;                /* Activity timeout counter */
++	int32 bus_wake;                 /* For wake up the bus */
++	bool runtime_resume_done;       /* For check runtime suspend end */
++	struct mutex pm_lock;            /* Synchronize for system PM & runtime PM */
++	wait_queue_head_t rpm_queue;    /* wait-queue for bus wake up */
++#endif /* DHD_PCIE_RUNTIMEPM */
++	uint32 d3_inform_cnt;
++	uint32 d0_inform_cnt;
++	uint32 d0_inform_in_use_cnt;
++	uint8 force_suspend;
++	uint8 is_linkdown;
++#ifdef IDLE_TX_FLOW_MGMT
++	bool enable_idle_flowring_mgmt;
++#endif /* IDLE_TX_FLOW_MGMT */
++	struct	dhd_pcie_rev api;
++	bool use_mailbox;
++	bool	d3_suspend_pending;
++	bool    use_d0_inform;
++	uint32  hostready_count; /* Number of hostready issued */
++#if defined(PCIE_OOB) || defined(BCMPCIE_OOB_HOST_WAKE)
++	bool	oob_presuspend;
++#endif /* PCIE_OOB || BCMPCIE_OOB_HOST_WAKE */
++	bool	dongle_in_ds;
++	uint8	dw_option;
++#ifdef PCIE_INB_DW
++	bool	inb_enabled;
++	uint32	ds_exit_timeout;
++	uint32	host_sleep_exit_timeout;
++	uint	wait_for_ds_exit;
++	uint32	inband_dw_assert_cnt; /* # of inband device_wake assert */
++	uint32	inband_dw_deassert_cnt; /* # of inband device_wake deassert */
++	uint32	inband_ds_exit_host_cnt; /* # of DS-EXIT , host initiated */
++	uint32	inband_ds_exit_device_cnt; /* # of DS-EXIT , device initiated */
++	uint32	inband_ds_exit_to_cnt; /* # of DS-EXIT timeout */
++	uint32	inband_host_sleep_exit_to_cnt; /* # of Host_Sleep exit timeout */
++	void	*inb_lock;	/* Lock to serialize in band device wake activity */
++	/* # of contexts in the host which currently want a FW transaction */
++	uint32  host_active_cnt;
++#endif /* PCIE_INB_DW */
++	dhdpcie_config_save_t saved_config;
++	ulong resume_intr_enable_count;
++	ulong dpc_intr_enable_count;
++	ulong isr_intr_disable_count;
++	ulong suspend_intr_disable_count;
++	ulong dpc_return_busdown_count;
++	bool  idma_enabled;
++	bool  ifrm_enabled;
++#if defined(PCIE_OOB) || defined(PCIE_INB_DW)
++	bool  ds_enabled;
++#endif
++#ifdef DHD_PCIE_RUNTIMEPM
++	bool chk_pm;	/* To avoid counting of wake up from Runtime PM */
++#endif /* DHD_PCIE_RUNTIMEPM */
++} dhd_bus_t;
++
++/* function declarations */
++
++extern uint32* dhdpcie_bus_reg_map(osl_t *osh, ulong addr, int size);
++extern int dhdpcie_bus_register(void);
++extern void dhdpcie_bus_unregister(void);
++extern bool dhdpcie_chipmatch(uint16 vendor, uint16 device);
++
++extern struct dhd_bus* dhdpcie_bus_attach(osl_t *osh,
++	volatile char *regs, volatile char *tcm, void *pci_dev);
++extern uint32 dhdpcie_bus_cfg_read_dword(struct dhd_bus *bus, uint32 addr, uint32 size);
++extern void dhdpcie_bus_cfg_write_dword(struct dhd_bus *bus, uint32 addr, uint32 size, uint32 data);
++extern void dhdpcie_bus_intr_enable(struct dhd_bus *bus);
++extern void dhdpcie_bus_intr_disable(struct dhd_bus *bus);
++extern int dhpcie_bus_mask_interrupt(dhd_bus_t *bus);
++extern void dhdpcie_bus_release(struct dhd_bus *bus);
++extern int32 dhdpcie_bus_isr(struct dhd_bus *bus);
++extern void dhdpcie_free_irq(dhd_bus_t *bus);
++extern void dhdpcie_bus_ringbell_fast(struct dhd_bus *bus, uint32 value);
++extern void dhdpcie_bus_ringbell_2_fast(struct dhd_bus *bus, uint32 value, bool devwake);
++extern int dhdpcie_bus_suspend(struct  dhd_bus *bus, bool state);
++extern int dhdpcie_pci_suspend_resume(struct  dhd_bus *bus, bool state);
++extern uint32 dhdpcie_force_alp(struct dhd_bus *bus, bool enable);
++extern uint32 dhdpcie_set_l1_entry_time(struct dhd_bus *bus, int force_l1_entry_time);
++extern bool dhdpcie_tcm_valid(dhd_bus_t *bus);
++extern void dhdpcie_pme_active(osl_t *osh, bool enable);
++extern bool dhdpcie_pme_cap(osl_t *osh);
++extern uint32 dhdpcie_lcreg(osl_t *osh, uint32 mask, uint32 val);
++extern void dhdpcie_set_pmu_min_res_mask(struct dhd_bus *bus, uint min_res_mask);
++extern uint8 dhdpcie_clkreq(osl_t *osh, uint32 mask, uint32 val);
++extern int dhdpcie_disable_irq(dhd_bus_t *bus);
++extern int dhdpcie_disable_irq_nosync(dhd_bus_t *bus);
++extern int dhdpcie_enable_irq(dhd_bus_t *bus);
++extern uint32 dhdpcie_rc_config_read(dhd_bus_t *bus, uint offset);
++extern uint32 dhdpcie_rc_access_cap(dhd_bus_t *bus, int cap, uint offset, bool is_ext,
++		bool is_write, uint32 writeval);
++extern uint32 dhd_debug_get_rc_linkcap(dhd_bus_t *bus);
++extern int dhdpcie_start_host_pcieclock(dhd_bus_t *bus);
++extern int dhdpcie_stop_host_pcieclock(dhd_bus_t *bus);
++extern int dhdpcie_disable_device(dhd_bus_t *bus);
++extern int dhdpcie_alloc_resource(dhd_bus_t *bus);
++extern void dhdpcie_free_resource(dhd_bus_t *bus);
++extern int dhdpcie_bus_request_irq(struct dhd_bus *bus);
++extern int dhdpcie_enable_device(dhd_bus_t *bus);
++#ifdef BCMPCIE_OOB_HOST_WAKE
++extern int dhdpcie_oob_intr_register(dhd_bus_t *bus);
++extern void dhdpcie_oob_intr_unregister(dhd_bus_t *bus);
++extern void dhdpcie_oob_intr_set(dhd_bus_t *bus, bool enable);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#ifdef PCIE_OOB
++extern void dhd_oob_set_bt_reg_on(struct dhd_bus *bus, bool val);
++extern int dhd_oob_get_bt_reg_on(struct dhd_bus *bus);
++extern void dhdpcie_oob_init(dhd_bus_t *bus);
++extern void dhd_bus_doorbell_timeout_reset(struct dhd_bus *bus);
++extern int dhd_os_oob_set_device_wake(struct dhd_bus *bus, bool val);
++extern void dhd_os_ib_set_device_wake(struct dhd_bus *bus, bool val);
++#endif /* PCIE_OOB */
++
++#if defined(CONFIG_ARCH_EXYNOS)
++#define SAMSUNG_PCIE_VENDOR_ID 0x144d
++#if defined(CONFIG_MACH_UNIVERSAL5433)
++#define SAMSUNG_PCIE_DEVICE_ID 0xa5e3
++#define SAMSUNG_PCIE_CH_NUM
++#elif defined(CONFIG_MACH_UNIVERSAL7420)
++#define SAMSUNG_PCIE_DEVICE_ID 0xa575
++#define SAMSUNG_PCIE_CH_NUM 1
++#elif defined(CONFIG_SOC_EXYNOS8890)
++#define SAMSUNG_PCIE_DEVICE_ID 0xa544
++#define SAMSUNG_PCIE_CH_NUM 0
++#elif defined(CONFIG_SOC_EXYNOS7420)
++#define SAMSUNG_PCIE_DEVICE_ID 0xa575
++#define SAMSUNG_PCIE_CH_NUM 1
++#elif defined(CONFIG_SOC_EXYNOS8895)
++#define SAMSUNG_PCIE_DEVICE_ID 0xecec
++#define SAMSUNG_PCIE_CH_NUM 0
++#else
++#error "Not supported platform"
++#endif /* CONFIG_SOC_EXYNOSXXXX & CONFIG_MACH_UNIVERSALXXXX */
++#endif /* CONFIG_ARCH_EXYNOS */
++
++#if defined(CONFIG_ARCH_MSM)
++#define MSM_PCIE_VENDOR_ID 0x17cb
++#if defined(CONFIG_ARCH_APQ8084)
++#define MSM_PCIE_DEVICE_ID 0x0101
++#elif defined(CONFIG_ARCH_MSM8994)
++#define MSM_PCIE_DEVICE_ID 0x0300
++#elif defined(CONFIG_ARCH_MSM8996)
++#define MSM_PCIE_DEVICE_ID 0x0104
++#elif defined(CONFIG_ARCH_MSM8998)
++#define MSM_PCIE_DEVICE_ID 0x0105
++#else
++#error "Not supported platform"
++#endif
++#endif /* CONFIG_ARCH_MSM */
++
++#if defined(CONFIG_X86)
++#define X86_PCIE_VENDOR_ID 0x8086
++#define X86_PCIE_DEVICE_ID 0x9c1a
++#endif /* CONFIG_X86 */
++
++#if defined(CONFIG_ARCH_TEGRA)
++#define TEGRA_PCIE_VENDOR_ID 0x14e4
++#define TEGRA_PCIE_DEVICE_ID 0x4347
++#endif /* CONFIG_ARCH_TEGRA */
++
++#if defined(CONFIG_ARCH_EXYNOS)
++#define PCIE_RC_VENDOR_ID SAMSUNG_PCIE_VENDOR_ID
++#define PCIE_RC_DEVICE_ID SAMSUNG_PCIE_DEVICE_ID
++#elif defined(CONFIG_ARCH_MSM)
++#define PCIE_RC_VENDOR_ID MSM_PCIE_VENDOR_ID
++#define PCIE_RC_DEVICE_ID MSM_PCIE_DEVICE_ID
++#elif defined(CONFIG_X86)
++#define PCIE_RC_VENDOR_ID X86_PCIE_VENDOR_ID
++#define PCIE_RC_DEVICE_ID X86_PCIE_DEVICE_ID
++#elif defined(CONFIG_ARCH_TEGRA)
++#define PCIE_RC_VENDOR_ID TEGRA_PCIE_VENDOR_ID
++#define PCIE_RC_DEVICE_ID TEGRA_PCIE_DEVICE_ID
++#endif /* CONFIG_ARCH_EXYNOS */
++
++#ifdef USE_EXYNOS_PCIE_RC_PMPATCH
++#ifdef CONFIG_MACH_UNIVERSAL5433
++extern int exynos_pcie_pm_suspend(void);
++extern int exynos_pcie_pm_resume(void);
++#else
++extern int exynos_pcie_pm_suspend(int ch_num);
++extern int exynos_pcie_pm_resume(int ch_num);
++#endif /* CONFIG_MACH_UNIVERSAL5433 */
++#endif /* USE_EXYNOS_PCIE_RC_PMPATCH */
++
++#ifdef CONFIG_ARCH_TEGRA
++extern int tegra_pcie_pm_suspend(void);
++extern int tegra_pcie_pm_resume(void);
++#endif /* CONFIG_ARCH_TEGRA */
++
++extern int dhd_buzzz_dump_dngl(dhd_bus_t *bus);
++#ifdef IDLE_TX_FLOW_MGMT
++extern int dhd_bus_flow_ring_resume_request(struct dhd_bus *bus, void *arg);
++extern void dhd_bus_flow_ring_resume_response(struct dhd_bus *bus, uint16 flowid, int32 status);
++extern int dhd_bus_flow_ring_suspend_request(struct dhd_bus *bus, void *arg);
++extern void dhd_bus_flow_ring_suspend_response(struct dhd_bus *bus, uint16 flowid, uint32 status);
++extern void dhd_flow_ring_move_to_active_list_head(struct dhd_bus *bus,
++	flow_ring_node_t *flow_ring_node);
++extern void dhd_flow_ring_add_to_active_list(struct dhd_bus *bus,
++	flow_ring_node_t *flow_ring_node);
++extern void dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus,
++	flow_ring_node_t *flow_ring_node);
++extern void __dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus,
++	flow_ring_node_t *flow_ring_node);
++#endif /* IDLE_TX_FLOW_MGMT */
++
++extern int dhdpcie_send_mb_data(dhd_bus_t *bus, uint32 h2d_mb_data);
++
++#ifdef DHD_WAKE_STATUS
++int bcmpcie_get_total_wake(struct dhd_bus *bus);
++int bcmpcie_set_get_wake(struct dhd_bus *bus, int flag);
++#endif /* DHD_WAKE_STATUS */
++extern bool dhdpcie_bus_get_pcie_hostready_supported(dhd_bus_t *bus);
++extern void dhd_bus_hostready(struct  dhd_bus *bus);
++#ifdef PCIE_OOB
++extern bool dhdpcie_bus_get_pcie_oob_dw_supported(dhd_bus_t *bus);
++#endif /* PCIE_OOB */
++#ifdef PCIE_INB_DW
++extern bool dhdpcie_bus_get_pcie_inband_dw_supported(dhd_bus_t *bus);
++extern void dhdpcie_bus_set_pcie_inband_dw_state(dhd_bus_t *bus,
++	enum dhd_bus_ds_state state);
++extern enum dhd_bus_ds_state dhdpcie_bus_get_pcie_inband_dw_state(dhd_bus_t *bus);
++extern const char * dhd_convert_inb_state_names(enum dhd_bus_ds_state inbstate);
++extern const char * dhd_convert_dsval(uint32 val, bool d2h);
++extern int dhd_bus_inb_set_device_wake(struct dhd_bus *bus, bool val);
++extern void dhd_bus_inb_ack_pending_ds_req(dhd_bus_t *bus);
++#endif /* PCIE_INB_DW */
++extern void dhdpcie_bus_enab_pcie_dw(dhd_bus_t *bus, uint8 dw_option);
++extern bool dhdpcie_irq_enabled(struct dhd_bus *bus);
++extern bool dhdpcie_bus_get_pcie_idma_supported(dhd_bus_t *bus);
++extern bool dhdpcie_bus_get_pcie_ifrm_supported(dhd_bus_t *bus);
++
++static INLINE uint32
++dhd_pcie_config_read(osl_t *osh, uint offset, uint size)
++{
++	OSL_DELAY(100);
++	return OSL_PCI_READ_CONFIG(osh, offset, size);
++}
++
++static INLINE uint32
++dhd_pcie_corereg_read(si_t *sih, uint val)
++{
++	OSL_DELAY(100);
++	si_corereg(sih, sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0, val);
++	return si_corereg(sih, sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata), 0, 0);
++}
++
++#ifdef DHD_SSSR_DUMP
++extern int dhdpcie_sssr_dump(dhd_pub_t *dhd);
++#endif /* DHD_SSSR_DUMP */
++
++#ifdef DHD_EFI
++extern int dhd_os_wifi_platform_set_power(uint32 value);
++int dhd_control_signal(dhd_bus_t *bus, char *arg, int set);
++extern int dhd_wifi_properties(struct dhd_bus *bus, char *arg);
++extern bool dhdpcie_is_arm_halted(struct dhd_bus *bus);
++extern void dhdpcie_dongle_pwr_toggle(dhd_bus_t *bus);
++extern int dhd_otp_dump(dhd_bus_t *bus, char *arg);
++#else
++static INLINE int dhd_os_wifi_platform_set_power(uint32 value) {return BCME_OK; }
++static INLINE bool dhdpcie_is_arm_halted(struct dhd_bus *bus) {return TRUE;}
++#endif /* DHD_EFI */
++int dhdpcie_config_check(dhd_bus_t *bus);
++int dhdpcie_config_restore(dhd_bus_t *bus, bool restore_pmcsr);
++int dhdpcie_config_save(dhd_bus_t *bus);
++int dhdpcie_set_pwr_state(dhd_bus_t *bus, uint state);
++
++#endif /* dhd_pcie_h */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_pcie_linux.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_pcie_linux.c
+new file mode 100644
+index 000000000..928c72ba1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_pcie_linux.c
+@@ -0,0 +1,2316 @@
++/*
++ * Linux DHD Bus Module for PCIE
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_pcie_linux.c 707536 2017-06-28 04:23:48Z $
++ */
++
++
++/* include files */
++#include <typedefs.h>
++#include <bcmutils.h>
++#include <bcmdevs.h>
++#include <siutils.h>
++#include <hndsoc.h>
++#include <hndpmu.h>
++#include <sbchipc.h>
++#if defined(DHD_DEBUG)
++#include <hnd_armtrap.h>
++#include <hnd_cons.h>
++#endif /* defined(DHD_DEBUG) */
++#include <dngl_stats.h>
++#include <pcie_core.h>
++#include <dhd.h>
++#include <dhd_bus.h>
++#include <dhd_proto.h>
++#include <dhd_dbg.h>
++#include <dhdioctl.h>
++#include <bcmmsgbuf.h>
++#include <pcicfg.h>
++#include <dhd_pcie.h>
++#include <dhd_linux.h>
++#ifdef CONFIG_ARCH_MSM
++#if defined(CONFIG_PCI_MSM) || defined(CONFIG_ARCH_MSM8996)
++#include <linux/msm_pcie.h>
++#else
++#include <mach/msm_pcie.h>
++#endif /* CONFIG_PCI_MSM */
++#endif /* CONFIG_ARCH_MSM */
++#ifdef PCIE_OOB
++#include "ftdi_sio_external.h"
++#endif /* PCIE_OOB */
++#include <linux/irq.h>
++#ifdef USE_SMMU_ARCH_MSM
++#include <asm/dma-iommu.h>
++#include <linux/iommu.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#endif /* USE_SMMU_ARCH_MSM */
++
++#define PCI_CFG_RETRY 		10
++#define OS_HANDLE_MAGIC		0x1234abcd	/* Magic # to recognize osh */
++#define BCM_MEM_FILENAME_LEN 	24		/* Mem. filename length */
++
++#define OSL_PKTTAG_CLEAR(p) \
++do { \
++	struct sk_buff *s = (struct sk_buff *)(p); \
++	ASSERT(OSL_PKTTAG_SZ == 32); \
++	*(uint32 *)(&s->cb[0]) = 0; *(uint32 *)(&s->cb[4]) = 0; \
++	*(uint32 *)(&s->cb[8]) = 0; *(uint32 *)(&s->cb[12]) = 0; \
++	*(uint32 *)(&s->cb[16]) = 0; *(uint32 *)(&s->cb[20]) = 0; \
++	*(uint32 *)(&s->cb[24]) = 0; *(uint32 *)(&s->cb[28]) = 0; \
++} while (0)
++
++#ifdef PCIE_OOB
++#define HOST_WAKE 4   /* GPIO_0 (HOST_WAKE) - Output from WLAN */
++#define DEVICE_WAKE 5  /* GPIO_1 (DEVICE_WAKE) - Input to WLAN */
++#define BIT_WL_REG_ON 6
++#define BIT_BT_REG_ON 7
++
++int gpio_handle_val = 0;
++unsigned char gpio_port = 0;
++unsigned char gpio_direction = 0;
++#define OOB_PORT "ttyUSB0"
++#endif /* PCIE_OOB */
++
++/* user defined data structures  */
++
++typedef struct dhd_pc_res {
++	uint32 bar0_size;
++	void* bar0_addr;
++	uint32 bar1_size;
++	void* bar1_addr;
++} pci_config_res, *pPci_config_res;
++
++typedef bool (*dhdpcie_cb_fn_t)(void *);
++
++typedef struct dhdpcie_info
++{
++	dhd_bus_t	*bus;
++	osl_t 			*osh;
++	struct pci_dev  *dev;		/* pci device handle */
++	volatile char 	*regs;		/* pci device memory va */
++	volatile char 	*tcm;		/* pci device memory va */
++	uint32			tcm_size;	/* pci device memory size */
++	struct pcos_info *pcos_info;
++	uint16		last_intrstatus;	/* to cache intrstatus */
++	int	irq;
++	char pciname[32];
++	struct pci_saved_state* default_state;
++	struct pci_saved_state* state;
++#ifdef BCMPCIE_OOB_HOST_WAKE
++	void *os_cxt;			/* Pointer to per-OS private data */
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#ifdef DHD_WAKE_STATUS
++	spinlock_t	pcie_lock;
++	unsigned int	total_wake_count;
++	int		pkt_wake;
++	int		wake_irq;
++#endif /* DHD_WAKE_STATUS */
++#ifdef USE_SMMU_ARCH_MSM
++	void *smmu_cxt;
++#endif /* USE_SMMU_ARCH_MSM */
++} dhdpcie_info_t;
++
++
++struct pcos_info {
++	dhdpcie_info_t *pc;
++	spinlock_t lock;
++	wait_queue_head_t intr_wait_queue;
++	timer_list_compat_t tuning_timer;
++	int tuning_timer_exp;
++	atomic_t timer_enab;
++	struct tasklet_struct tuning_tasklet;
++};
++
++#ifdef BCMPCIE_OOB_HOST_WAKE
++typedef struct dhdpcie_os_info {
++	int			oob_irq_num;	/* valid when hardware or software oob in use */
++	unsigned long		oob_irq_flags;	/* valid when hardware or software oob in use */
++	bool			oob_irq_registered;
++	bool			oob_irq_enabled;
++	bool			oob_irq_wake_enabled;
++	spinlock_t		oob_irq_spinlock;
++	void			*dev;		/* handle to the underlying device */
++} dhdpcie_os_info_t;
++static irqreturn_t wlan_oob_irq(int irq, void *data);
++#if defined(CUSTOMER_HW2) && defined(CONFIG_ARCH_APQ8084)
++extern struct brcm_pcie_wake brcm_pcie_wake;
++#endif /* CUSTOMER_HW2 && CONFIG_ARCH_APQ8084 */
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++
++#ifdef USE_SMMU_ARCH_MSM
++typedef struct dhdpcie_smmu_info {
++	struct dma_iommu_mapping *smmu_mapping;
++	dma_addr_t smmu_iova_start;
++	size_t smmu_iova_len;
++} dhdpcie_smmu_info_t;
++#endif /* USE_SMMU_ARCH_MSM */
++
++/* function declarations */
++static int __devinit
++dhdpcie_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
++static void __devexit
++dhdpcie_pci_remove(struct pci_dev *pdev);
++static int dhdpcie_init(struct pci_dev *pdev);
++static irqreturn_t dhdpcie_isr(int irq, void *arg);
++/* OS Routine functions for PCI suspend/resume */
++
++static int dhdpcie_set_suspend_resume(dhd_bus_t *bus, bool state);
++static int dhdpcie_resume_host_dev(dhd_bus_t *bus);
++static int dhdpcie_suspend_host_dev(dhd_bus_t *bus);
++static int dhdpcie_resume_dev(struct pci_dev *dev);
++static int dhdpcie_suspend_dev(struct pci_dev *dev);
++#ifdef DHD_PCIE_RUNTIMEPM
++static int dhdpcie_pm_suspend(struct device *dev);
++static int dhdpcie_pm_prepare(struct device *dev);
++static int dhdpcie_pm_resume(struct device *dev);
++static void dhdpcie_pm_complete(struct device *dev);
++#else
++static int dhdpcie_pci_suspend(struct pci_dev *dev, pm_message_t state);
++static int dhdpcie_pci_resume(struct pci_dev *dev);
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++static struct pci_device_id dhdpcie_pci_devid[] __devinitdata = {
++	{ vendor: 0x14e4,
++	device: PCI_ANY_ID,
++	subvendor: PCI_ANY_ID,
++	subdevice: PCI_ANY_ID,
++	class: PCI_CLASS_NETWORK_OTHER << 8,
++	class_mask: 0xffff00,
++	driver_data: 0,
++	},
++	{ 0, 0, 0, 0, 0, 0, 0}
++};
++MODULE_DEVICE_TABLE(pci, dhdpcie_pci_devid);
++
++/* Power Management Hooks */
++#ifdef DHD_PCIE_RUNTIMEPM
++static const struct dev_pm_ops dhd_pcie_pm_ops = {
++	.prepare = dhdpcie_pm_prepare,
++	.suspend = dhdpcie_pm_suspend,
++	.resume = dhdpcie_pm_resume,
++	.complete = dhdpcie_pm_complete,
++};
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++static struct pci_driver dhdpcie_driver = {
++	node:		{&dhdpcie_driver.node, &dhdpcie_driver.node},
++	name:		"pcieh",
++	id_table:	dhdpcie_pci_devid,
++	probe:		dhdpcie_pci_probe,
++	remove:		dhdpcie_pci_remove,
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
++	save_state:	NULL,
++#endif
++#ifdef DHD_PCIE_RUNTIMEPM
++	.driver.pm = &dhd_pcie_pm_ops,
++#else
++	suspend:	dhdpcie_pci_suspend,
++	resume:		dhdpcie_pci_resume,
++#endif /* DHD_PCIE_RUNTIMEPM */
++};
++
++int dhdpcie_init_succeeded = FALSE;
++
++#ifdef USE_SMMU_ARCH_MSM
++static int dhdpcie_smmu_init(struct pci_dev *pdev, void *smmu_cxt)
++{
++	struct dma_iommu_mapping *mapping;
++	struct device_node *root_node = NULL;
++	dhdpcie_smmu_info_t *smmu_info = (dhdpcie_smmu_info_t *)smmu_cxt;
++	int smmu_iova_address[2];
++	char *wlan_node = "android,bcmdhd_wlan";
++	char *wlan_smmu_node = "wlan-smmu-iova-address";
++	int atomic_ctx = 1;
++	int s1_bypass = 1;
++	int ret = 0;
++
++	DHD_ERROR(("%s: SMMU initialize\n", __FUNCTION__));
++
++	root_node = of_find_compatible_node(NULL, NULL, wlan_node);
++	if (!root_node) {
++		WARN(1, "failed to get device node of BRCM WLAN\n");
++		return -ENODEV;
++	}
++
++	if (of_property_read_u32_array(root_node, wlan_smmu_node,
++		smmu_iova_address, 2) == 0) {
++		DHD_ERROR(("%s : get SMMU start address 0x%x, size 0x%x\n",
++			__FUNCTION__, smmu_iova_address[0], smmu_iova_address[1]));
++		smmu_info->smmu_iova_start = smmu_iova_address[0];
++		smmu_info->smmu_iova_len = smmu_iova_address[1];
++	} else {
++		printf("%s : can't get smmu iova address property\n",
++			__FUNCTION__);
++		return -ENODEV;
++	}
++
++	if (smmu_info->smmu_iova_len <= 0) {
++		DHD_ERROR(("%s: Invalid smmu iova len %d\n",
++			__FUNCTION__, (int)smmu_info->smmu_iova_len));
++		return -EINVAL;
++	}
++
++	DHD_ERROR(("%s : SMMU init start\n", __FUNCTION__));
++	mapping = arm_iommu_create_mapping(&platform_bus_type,
++		smmu_info->smmu_iova_start, smmu_info->smmu_iova_len);
++	if (IS_ERR(mapping)) {
++		DHD_ERROR(("%s: create mapping failed, err = %d\n",
++			__FUNCTION__, ret));
++		ret = PTR_ERR(mapping);
++		goto map_fail;
++	}
++
++	ret = iommu_domain_set_attr(mapping->domain,
++		DOMAIN_ATTR_ATOMIC, &atomic_ctx);
++	if (ret) {
++		DHD_ERROR(("%s: set atomic_ctx attribute failed, err = %d\n",
++			__FUNCTION__, ret));
++		goto set_attr_fail;
++	}
++
++	ret = iommu_domain_set_attr(mapping->domain,
++		DOMAIN_ATTR_S1_BYPASS, &s1_bypass);
++	if (ret < 0) {
++		DHD_ERROR(("%s: set s1_bypass attribute failed, err = %d\n",
++			__FUNCTION__, ret));
++		goto set_attr_fail;
++	}
++
++	ret = arm_iommu_attach_device(&pdev->dev, mapping);
++	if (ret) {
++		DHD_ERROR(("%s: attach device failed, err = %d\n",
++			__FUNCTION__, ret));
++		goto attach_fail;
++	}
++
++	smmu_info->smmu_mapping = mapping;
++
++	return ret;
++
++attach_fail:
++set_attr_fail:
++	arm_iommu_release_mapping(mapping);
++map_fail:
++	return ret;
++}
++
++static void dhdpcie_smmu_remove(struct pci_dev *pdev, void *smmu_cxt)
++{
++	dhdpcie_smmu_info_t *smmu_info;
++
++	if (!smmu_cxt) {
++		return;
++	}
++
++	smmu_info = (dhdpcie_smmu_info_t *)smmu_cxt;
++	if (smmu_info->smmu_mapping) {
++		arm_iommu_detach_device(&pdev->dev);
++		arm_iommu_release_mapping(smmu_info->smmu_mapping);
++		smmu_info->smmu_mapping = NULL;
++	}
++}
++#endif /* USE_SMMU_ARCH_MSM */
++
++#ifdef DHD_PCIE_RUNTIMEPM
++static int dhdpcie_pm_suspend(struct device *dev)
++{
++	int ret = 0;
++	struct pci_dev *pdev = to_pci_dev(dev);
++	dhdpcie_info_t *pch = pci_get_drvdata(pdev);
++	dhd_bus_t *bus = NULL;
++	unsigned long flags;
++
++	if (pch) {
++		bus = pch->bus;
++	}
++	if (!bus) {
++		return ret;
++	}
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	if (!DHD_BUS_BUSY_CHECK_IDLE(bus->dhd)) {
++		DHD_ERROR(("%s: Bus not IDLE!! dhd_bus_busy_state = 0x%x\n",
++			__FUNCTION__, bus->dhd->dhd_bus_busy_state));
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++		return -EBUSY;
++	}
++	DHD_BUS_BUSY_SET_SUSPEND_IN_PROGRESS(bus->dhd);
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	if (!bus->dhd->dongle_reset)
++		ret = dhdpcie_set_suspend_resume(bus, TRUE);
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	DHD_BUS_BUSY_CLEAR_SUSPEND_IN_PROGRESS(bus->dhd);
++	dhd_os_busbusy_wake(bus->dhd);
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	return ret;
++
++}
++
++static int dhdpcie_pm_prepare(struct device *dev)
++{
++	struct pci_dev *pdev = to_pci_dev(dev);
++	dhdpcie_info_t *pch = pci_get_drvdata(pdev);
++	dhd_bus_t *bus = NULL;
++
++	if (pch) {
++		bus = pch->bus;
++		DHD_DISABLE_RUNTIME_PM(bus->dhd);
++	}
++
++	bus->chk_pm = TRUE;
++	return 0;
++}
++
++static int dhdpcie_pm_resume(struct device *dev)
++{
++	int ret = 0;
++	struct pci_dev *pdev = to_pci_dev(dev);
++	dhdpcie_info_t *pch = pci_get_drvdata(pdev);
++	dhd_bus_t *bus = NULL;
++	unsigned long flags;
++
++	if (pch) {
++		bus = pch->bus;
++	}
++	if (!bus) {
++		return ret;
++	}
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	DHD_BUS_BUSY_SET_RESUME_IN_PROGRESS(bus->dhd);
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	if (!bus->dhd->dongle_reset) {
++		ret = dhdpcie_set_suspend_resume(bus, FALSE);
++		bus->chk_pm = FALSE;
++	}
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	DHD_BUS_BUSY_CLEAR_RESUME_IN_PROGRESS(bus->dhd);
++	dhd_os_busbusy_wake(bus->dhd);
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	return ret;
++}
++
++static void dhdpcie_pm_complete(struct device *dev)
++{
++	struct pci_dev *pdev = to_pci_dev(dev);
++	dhdpcie_info_t *pch = pci_get_drvdata(pdev);
++	dhd_bus_t *bus = NULL;
++
++	if (pch) {
++		bus = pch->bus;
++		DHD_ENABLE_RUNTIME_PM(bus->dhd);
++	}
++
++	return;
++}
++#else
++static int dhdpcie_pci_suspend(struct pci_dev * pdev, pm_message_t state)
++{
++	int ret = 0;
++	dhdpcie_info_t *pch = pci_get_drvdata(pdev);
++	dhd_bus_t *bus = NULL;
++	unsigned long flags;
++
++	if (pch) {
++		bus = pch->bus;
++	}
++	if (!bus) {
++		return ret;
++	}
++
++	BCM_REFERENCE(state);
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	if (!DHD_BUS_BUSY_CHECK_IDLE(bus->dhd)) {
++		DHD_ERROR(("%s: Bus not IDLE!! dhd_bus_busy_state = 0x%x\n",
++			__FUNCTION__, bus->dhd->dhd_bus_busy_state));
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++		return -EBUSY;
++	}
++	DHD_BUS_BUSY_SET_SUSPEND_IN_PROGRESS(bus->dhd);
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	if (!bus->dhd->dongle_reset)
++		ret = dhdpcie_set_suspend_resume(bus, TRUE);
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	DHD_BUS_BUSY_CLEAR_SUSPEND_IN_PROGRESS(bus->dhd);
++	dhd_os_busbusy_wake(bus->dhd);
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	return ret;
++}
++
++static int dhdpcie_pci_resume(struct pci_dev *pdev)
++{
++	int ret = 0;
++	dhdpcie_info_t *pch = pci_get_drvdata(pdev);
++	dhd_bus_t *bus = NULL;
++	unsigned long flags;
++
++	if (pch) {
++		bus = pch->bus;
++	}
++	if (!bus) {
++		return ret;
++	}
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	DHD_BUS_BUSY_SET_RESUME_IN_PROGRESS(bus->dhd);
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	if (!bus->dhd->dongle_reset)
++		ret = dhdpcie_set_suspend_resume(bus, FALSE);
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	DHD_BUS_BUSY_CLEAR_RESUME_IN_PROGRESS(bus->dhd);
++	dhd_os_busbusy_wake(bus->dhd);
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	return ret;
++}
++
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++static int dhdpcie_set_suspend_resume(dhd_bus_t *bus, bool state)
++{
++	int ret = 0;
++
++	ASSERT(bus && !bus->dhd->dongle_reset);
++
++#ifdef DHD_PCIE_RUNTIMEPM
++		/* if wakelock is held during suspend, return failed */
++		if (state == TRUE && dhd_os_check_wakelock_all(bus->dhd)) {
++			return -EBUSY;
++		}
++		mutex_lock(&bus->pm_lock);
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++	/* When firmware is not loaded do the PCI bus */
++	/* suspend/resume only */
++	if (bus->dhd->busstate == DHD_BUS_DOWN) {
++		ret = dhdpcie_pci_suspend_resume(bus, state);
++#ifdef DHD_PCIE_RUNTIMEPM
++		mutex_unlock(&bus->pm_lock);
++#endif /* DHD_PCIE_RUNTIMEPM */
++		return ret;
++	}
++
++		ret = dhdpcie_bus_suspend(bus, state);
++
++#ifdef DHD_PCIE_RUNTIMEPM
++		mutex_unlock(&bus->pm_lock);
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++	return ret;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++extern void dhd_dpc_tasklet_kill(dhd_pub_t *dhdp);
++#endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++
++static int dhdpcie_suspend_dev(struct pci_dev *dev)
++{
++	int ret;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	dhdpcie_info_t *pch = pci_get_drvdata(dev);
++	dhd_bus_t *bus = pch->bus;
++
++	if (bus->is_linkdown) {
++		DHD_ERROR(("%s: PCIe link is down\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++#endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++	DHD_TRACE_HW4(("%s: Enter\n", __FUNCTION__));
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	dhd_dpc_tasklet_kill(bus->dhd);
++#endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++	pci_save_state(dev);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	pch->state = pci_store_saved_state(dev);
++#endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++	pci_enable_wake(dev, PCI_D0, TRUE);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
++	if (pci_is_enabled(dev))
++#endif
++		pci_disable_device(dev);
++
++	ret = pci_set_power_state(dev, PCI_D3hot);
++	if (ret) {
++		DHD_ERROR(("%s: pci_set_power_state error %d\n",
++			__FUNCTION__, ret));
++	}
++//	dev->state_saved = FALSE;
++	return ret;
++}
++
++#ifdef DHD_WAKE_STATUS
++int bcmpcie_get_total_wake(struct dhd_bus *bus)
++{
++	dhdpcie_info_t *pch = pci_get_drvdata(bus->dev);
++
++	return pch->total_wake_count;
++}
++
++int bcmpcie_set_get_wake(struct dhd_bus *bus, int flag)
++{
++	dhdpcie_info_t *pch = pci_get_drvdata(bus->dev);
++	unsigned long flags;
++	int ret;
++
++	spin_lock_irqsave(&pch->pcie_lock, flags);
++
++	ret = pch->pkt_wake;
++	pch->total_wake_count += flag;
++	pch->pkt_wake = flag;
++
++	spin_unlock_irqrestore(&pch->pcie_lock, flags);
++	return ret;
++}
++#endif /* DHD_WAKE_STATUS */
++
++static int dhdpcie_resume_dev(struct pci_dev *dev)
++{
++	int err = 0;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	dhdpcie_info_t *pch = pci_get_drvdata(dev);
++	pci_load_and_free_saved_state(dev, &pch->state);
++#endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++	DHD_TRACE_HW4(("%s: Enter\n", __FUNCTION__));
++//	dev->state_saved = TRUE;
++	pci_restore_state(dev);
++	err = pci_enable_device(dev);
++	if (err) {
++		printf("%s:pci_enable_device error %d \n", __FUNCTION__, err);
++		goto out;
++	}
++	pci_set_master(dev);
++	err = pci_set_power_state(dev, PCI_D0);
++	if (err) {
++		printf("%s:pci_set_power_state error %d \n", __FUNCTION__, err);
++		goto out;
++	}
++
++out:
++	return err;
++}
++
++static int dhdpcie_resume_host_dev(dhd_bus_t *bus)
++{
++	int bcmerror = 0;
++#ifdef USE_EXYNOS_PCIE_RC_PMPATCH
++	bcmerror = exynos_pcie_pm_resume(SAMSUNG_PCIE_CH_NUM);
++#endif /* USE_EXYNOS_PCIE_RC_PMPATCH */
++#ifdef CONFIG_ARCH_MSM
++	bcmerror = dhdpcie_start_host_pcieclock(bus);
++#endif /* CONFIG_ARCH_MSM */
++#ifdef CONFIG_ARCH_TEGRA
++	bcmerror = tegra_pcie_pm_resume();
++#endif /* CONFIG_ARCH_TEGRA */
++	if (bcmerror < 0) {
++		DHD_ERROR(("%s: PCIe RC resume failed!!! (%d)\n",
++			__FUNCTION__, bcmerror));
++		bus->is_linkdown = 1;
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#ifdef CONFIG_ARCH_MSM
++		bus->no_cfg_restore = 1;
++#endif /* CONFIG_ARCH_MSM */
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++	}
++
++	return bcmerror;
++}
++
++static int dhdpcie_suspend_host_dev(dhd_bus_t *bus)
++{
++	int bcmerror = 0;
++#ifdef USE_EXYNOS_PCIE_RC_PMPATCH
++	if (bus->rc_dev) {
++		pci_save_state(bus->rc_dev);
++	} else {
++		DHD_ERROR(("%s: RC %x:%x handle is NULL\n",
++			__FUNCTION__, PCIE_RC_VENDOR_ID, PCIE_RC_DEVICE_ID));
++	}
++	exynos_pcie_pm_suspend(SAMSUNG_PCIE_CH_NUM);
++#endif	/* USE_EXYNOS_PCIE_RC_PMPATCH */
++#ifdef CONFIG_ARCH_MSM
++	bcmerror = dhdpcie_stop_host_pcieclock(bus);
++#endif	/* CONFIG_ARCH_MSM */
++#ifdef CONFIG_ARCH_TEGRA
++	bcmerror = tegra_pcie_pm_suspend();
++#endif /* CONFIG_ARCH_TEGRA */
++	return bcmerror;
++}
++
++#if defined(PCIE_RC_VENDOR_ID) && defined(PCIE_RC_DEVICE_ID)
++uint32
++dhdpcie_rc_config_read(dhd_bus_t *bus, uint offset)
++{
++	uint val = -1; /* Initialise to 0xfffffff */
++	if (bus->rc_dev) {
++		pci_read_config_dword(bus->rc_dev, offset, &val);
++		OSL_DELAY(100);
++	} else {
++		DHD_ERROR(("%s: RC %x:%x handle is NULL\n",
++			__FUNCTION__, PCIE_RC_VENDOR_ID, PCIE_RC_DEVICE_ID));
++	}
++	DHD_ERROR(("%s: RC %x:%x offset 0x%x val 0x%x\n",
++		__FUNCTION__, PCIE_RC_VENDOR_ID, PCIE_RC_DEVICE_ID, offset, val));
++	return (val);
++}
++
++/*
++ * Reads/ Writes the value of capability register
++ * from the given CAP_ID section of PCI Root Port
++ *
++ * Arguements
++ * @bus current dhd_bus_t pointer
++ * @cap Capability or Extended Capability ID to get
++ * @offset offset of Register to Read
++ * @is_ext TRUE if @cap is given for Extended Capability
++ * @is_write is set to TRUE to indicate write
++ * @val value to write
++ *
++ * Return Value
++ * Returns 0xffffffff on error
++ * on write success returns BCME_OK (0)
++ * on Read Success returns the value of register requested
++ * Note: caller shoud ensure valid capability ID and Ext. Capability ID.
++ */
++
++uint32
++dhdpcie_rc_access_cap(dhd_bus_t *bus, int cap, uint offset, bool is_ext, bool is_write,
++	uint32 writeval)
++{
++	int cap_ptr = 0;
++	uint32 ret = -1;
++	uint32 readval;
++
++	if (!(bus->rc_dev)) {
++		DHD_ERROR(("%s: RC %x:%x handle is NULL\n",
++			__FUNCTION__, PCIE_RC_VENDOR_ID, PCIE_RC_DEVICE_ID));
++		return ret;
++	}
++
++	/* Find Capability offset */
++	if (is_ext) {
++		/* removing max EXT_CAP_ID check as
++		 * linux kernel definition's max value is not upadted yet as per spec
++		 */
++		cap_ptr = pci_find_ext_capability(bus->rc_dev, cap);
++
++	} else {
++		/* removing max PCI_CAP_ID_MAX check as
++		 * pervious kernel versions dont have this definition
++		 */
++		cap_ptr = pci_find_capability(bus->rc_dev, cap);
++	}
++
++	/* Return if capability with given ID not found */
++	if (cap_ptr == 0) {
++		DHD_ERROR(("%s: RC %x:%x PCI Cap(0x%02x) not supported.\n",
++			__FUNCTION__, PCIE_RC_VENDOR_ID, PCIE_RC_DEVICE_ID, cap));
++		return BCME_ERROR;
++	}
++
++	if (is_write) {
++		ret = pci_write_config_dword(bus->rc_dev, (cap_ptr + offset), writeval);
++		if (ret) {
++			DHD_ERROR(("%s: pci_write_config_dword failed. cap=%d offset=%d\n",
++				__FUNCTION__, cap, offset));
++			return BCME_ERROR;
++		}
++		ret = BCME_OK;
++
++	} else {
++
++		ret = pci_read_config_dword(bus->rc_dev, (cap_ptr + offset), &readval);
++
++		if (ret) {
++			DHD_ERROR(("%s: pci_read_config_dword failed. cap=%d offset=%d\n",
++				__FUNCTION__, cap, offset));
++			return BCME_ERROR;
++		}
++		ret = readval;
++	}
++
++	return ret;
++}
++
++/* API wrapper to read Root Port link capability
++ * Returns 2 = GEN2 1 = GEN1 BCME_ERR on linkcap not found
++ */
++
++uint32 dhd_debug_get_rc_linkcap(dhd_bus_t *bus)
++{
++	uint32 linkcap = -1;
++	linkcap = dhdpcie_rc_access_cap(bus, PCIE_CAP_ID_EXP,
++			PCIE_CAP_LINKCAP_OFFSET, FALSE, FALSE, 0);
++	linkcap &= PCIE_CAP_LINKCAP_LNKSPEED_MASK;
++	return linkcap;
++}
++#endif
++
++int dhdpcie_pci_suspend_resume(dhd_bus_t *bus, bool state)
++{
++	int rc;
++
++	struct pci_dev *dev = bus->dev;
++
++	if (state) {
++#ifndef BCMPCIE_OOB_HOST_WAKE
++		dhdpcie_pme_active(bus->osh, state);
++#endif /* !BCMPCIE_OOB_HOST_WAKE */
++		rc = dhdpcie_suspend_dev(dev);
++		if (!rc) {
++			dhdpcie_suspend_host_dev(bus);
++		}
++	} else {
++		dhdpcie_resume_host_dev(bus);
++		rc = dhdpcie_resume_dev(dev);
++#ifndef	BCMPCIE_OOB_HOST_WAKE
++		dhdpcie_pme_active(bus->osh, state);
++#endif /* !BCMPCIE_OOB_HOST_WAKE */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++#if defined(DHD_HANG_SEND_UP_TEST)
++		if (bus->is_linkdown ||
++			bus->dhd->req_hang_type == HANG_REASON_PCIE_RC_LINK_UP_FAIL)
++#else /* DHD_HANG_SEND_UP_TEST */
++		if (bus->is_linkdown)
++#endif /* DHD_HANG_SEND_UP_TEST */
++		{
++			bus->dhd->hang_reason = HANG_REASON_PCIE_RC_LINK_UP_FAIL;
++			dhd_os_send_hang_message(bus->dhd);
++		}
++#endif 
++	}
++	return rc;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++static int dhdpcie_device_scan(struct device *dev, void *data)
++{
++	struct pci_dev *pcidev;
++	int *cnt = data;
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	pcidev = container_of(dev, struct pci_dev, dev);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	if (pcidev->vendor != 0x14e4)
++		return 0;
++
++	DHD_INFO(("Found Broadcom PCI device 0x%04x\n", pcidev->device));
++	*cnt += 1;
++	if (pcidev->driver && strcmp(pcidev->driver->name, dhdpcie_driver.name))
++		DHD_ERROR(("Broadcom PCI Device 0x%04x has allocated with driver %s\n",
++			pcidev->device, pcidev->driver->name));
++
++	return 0;
++}
++#endif /* LINUX_VERSION >= 2.6.0 */
++
++int
++dhdpcie_bus_register(void)
++{
++	int error = 0;
++
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
++	if (!(error = pci_module_init(&dhdpcie_driver)))
++		return 0;
++
++	DHD_ERROR(("%s: pci_module_init failed 0x%x\n", __FUNCTION__, error));
++#else
++	if (!(error = pci_register_driver(&dhdpcie_driver))) {
++		bus_for_each_dev(dhdpcie_driver.driver.bus, NULL, &error, dhdpcie_device_scan);
++		if (!error) {
++			DHD_ERROR(("No Broadcom PCI device enumerated!\n"));
++		} else if (!dhdpcie_init_succeeded) {
++			DHD_ERROR(("%s: dhdpcie initialize failed.\n", __FUNCTION__));
++		} else {
++			return 0;
++		}
++
++		pci_unregister_driver(&dhdpcie_driver);
++		error = BCME_ERROR;
++	}
++#endif /* LINUX_VERSION < 2.6.0 */
++
++	return error;
++}
++
++
++void
++dhdpcie_bus_unregister(void)
++{
++	pci_unregister_driver(&dhdpcie_driver);
++}
++
++int __devinit
++dhdpcie_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
++{
++	int err = 0;
++	DHD_MUTEX_LOCK();
++
++	if (dhdpcie_chipmatch (pdev->vendor, pdev->device)) {
++		DHD_ERROR(("%s: chipmatch failed!!\n", __FUNCTION__));
++		err = -ENODEV;
++		goto exit;
++	}
++	printf("PCI_PROBE:  bus %X, slot %X,vendor %X, device %X"
++		"(good PCI location)\n", pdev->bus->number,
++		PCI_SLOT(pdev->devfn), pdev->vendor, pdev->device);
++
++	if (dhdpcie_init (pdev)) {
++		DHD_ERROR(("%s: PCIe Enumeration failed\n", __FUNCTION__));
++		err = -ENODEV;
++		goto exit;
++	}
++
++#ifdef BCMPCIE_DISABLE_ASYNC_SUSPEND
++	/* disable async suspend */
++	device_disable_async_suspend(&pdev->dev);
++#endif /* BCMPCIE_DISABLE_ASYNC_SUSPEND */
++
++	DHD_TRACE(("%s: PCIe Enumeration done!!\n", __FUNCTION__));
++
++exit:
++	DHD_MUTEX_UNLOCK();
++	return err;
++}
++
++int
++dhdpcie_detach(dhdpcie_info_t *pch)
++{
++	if (pch) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++		if (!dhd_download_fw_on_driverload) {
++			pci_load_and_free_saved_state(pch->dev, &pch->default_state);
++		}
++#endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++		MFREE(pch->osh, pch, sizeof(dhdpcie_info_t));
++	}
++	return 0;
++}
++
++
++void __devexit
++dhdpcie_pci_remove(struct pci_dev *pdev)
++{
++	osl_t *osh = NULL;
++	dhdpcie_info_t *pch = NULL;
++	dhd_bus_t *bus = NULL;
++
++	DHD_TRACE(("%s Enter\n", __FUNCTION__));
++
++	DHD_MUTEX_LOCK();
++
++	pch = pci_get_drvdata(pdev);
++	bus = pch->bus;
++	osh = pch->osh;
++
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++	if (bus) {
++#ifdef CONFIG_ARCH_MSM
++		msm_pcie_deregister_event(&bus->pcie_event);
++#endif /* CONFIG_ARCH_MSM */
++#ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
++#ifdef CONFIG_SOC_EXYNOS8890
++		exynos_pcie_deregister_event(&bus->pcie_event);
++#endif /* CONFIG_SOC_EXYNOS8890 */
++#endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
++	}
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++
++	bus->rc_dev = NULL;
++
++	dhdpcie_bus_release(bus);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
++	if (pci_is_enabled(pdev))
++#endif
++		pci_disable_device(pdev);
++#ifdef BCMPCIE_OOB_HOST_WAKE
++	/* pcie os info detach */
++	MFREE(osh, pch->os_cxt, sizeof(dhdpcie_os_info_t));
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#ifdef USE_SMMU_ARCH_MSM
++	/* smmu info detach */
++	dhdpcie_smmu_remove(pdev, pch->smmu_cxt);
++	MFREE(osh, pch->smmu_cxt, sizeof(dhdpcie_smmu_info_t));
++#endif /* USE_SMMU_ARCH_MSM */
++	/* pcie info detach */
++	dhdpcie_detach(pch);
++	/* osl detach */
++	osl_detach(osh);
++
++#if defined(BCMPCIE_OOB_HOST_WAKE) && defined(CUSTOMER_HW2) && \
++	defined(CONFIG_ARCH_APQ8084)
++	brcm_pcie_wake.wake_irq = NULL;
++	brcm_pcie_wake.data = NULL;
++#endif /* BCMPCIE_OOB_HOST_WAKE && CUSTOMR_HW2 && CONFIG_ARCH_APQ8084 */
++
++	dhdpcie_init_succeeded = FALSE;
++
++	DHD_MUTEX_UNLOCK();
++
++	DHD_TRACE(("%s Exit\n", __FUNCTION__));
++
++	return;
++}
++
++/* Free Linux irq */
++int
++dhdpcie_request_irq(dhdpcie_info_t *dhdpcie_info)
++{
++	dhd_bus_t *bus = dhdpcie_info->bus;
++	struct pci_dev *pdev = dhdpcie_info->bus->dev;
++	int err = 0;
++
++	if (!bus->irq_registered) {
++		snprintf(dhdpcie_info->pciname, sizeof(dhdpcie_info->pciname),
++		    "dhdpcie:%s", pci_name(pdev));
++#ifdef DHD_USE_MSI
++		printf("%s: MSI enabled\n", __FUNCTION__);
++		err = pci_enable_msi(pdev);
++		if (err < 0) {
++			DHD_ERROR(("%s: pci_enable_msi() failed, %d, fall back to INTx\n", __FUNCTION__, err));
++		}
++#else
++		printf("%s: MSI not enabled\n", __FUNCTION__);
++#endif /* DHD_USE_MSI */
++		err = request_irq(pdev->irq, dhdpcie_isr, IRQF_SHARED,
++			dhdpcie_info->pciname, bus);
++		if (err) {
++			DHD_ERROR(("%s: request_irq() failed\n", __FUNCTION__));
++#ifdef DHD_USE_MSI
++			pci_disable_msi(pdev);
++#endif /* DHD_USE_MSI */
++			return -1;
++		} else {
++			bus->irq_registered = TRUE;
++		}
++	} else {
++		DHD_ERROR(("%s: PCI IRQ is already registered\n", __FUNCTION__));
++	}
++
++	if (!dhdpcie_irq_enabled(bus)) {
++		DHD_ERROR(("%s: PCIe IRQ was disabled, so, enabled it again\n", __FUNCTION__));
++		dhdpcie_enable_irq(bus);
++	}
++
++	DHD_TRACE(("%s %s\n", __FUNCTION__, dhdpcie_info->pciname));
++
++
++	return 0; /* SUCCESS */
++}
++
++/**
++ *	dhdpcie_get_pcieirq - return pcie irq number to linux-dhd
++ */
++int
++dhdpcie_get_pcieirq(struct dhd_bus *bus, unsigned int *irq)
++{
++	struct pci_dev *pdev = bus->dev;
++
++	if (!pdev) {
++		DHD_ERROR(("%s : bus->dev is NULL\n", __FUNCTION__));
++		return -ENODEV;
++	}
++
++	*irq  = pdev->irq;
++
++	return 0; /* SUCCESS */
++}
++
++#ifdef CONFIG_PHYS_ADDR_T_64BIT
++#define PRINTF_RESOURCE	"0x%016llx"
++#else
++#define PRINTF_RESOURCE	"0x%08x"
++#endif
++
++/*
++
++Name:  osl_pci_get_resource
++
++Parametrs:
++
++1: struct pci_dev *pdev   -- pci device structure
++2: pci_res                       -- structure containing pci configuration space values
++
++
++Return value:
++
++int   - Status (TRUE or FALSE)
++
++Description:
++Access PCI configuration space, retrieve  PCI allocated resources , updates in resource structure.
++
++ */
++int dhdpcie_get_resource(dhdpcie_info_t *dhdpcie_info)
++{
++	phys_addr_t  bar0_addr, bar1_addr;
++	ulong bar1_size;
++	struct pci_dev *pdev = NULL;
++	pdev = dhdpcie_info->dev;
++#ifdef EXYNOS_PCIE_MODULE_PATCH
++	pci_restore_state(pdev);
++#endif /* EXYNOS_MODULE_PATCH */
++	do {
++		if (pci_enable_device(pdev)) {
++			printf("%s: Cannot enable PCI device\n", __FUNCTION__);
++			break;
++		}
++		pci_set_master(pdev);
++		bar0_addr = pci_resource_start(pdev, 0);	/* Bar-0 mapped address */
++		bar1_addr = pci_resource_start(pdev, 2);	/* Bar-1 mapped address */
++
++		/* read Bar-1 mapped memory range */
++		bar1_size = pci_resource_len(pdev, 2);
++
++		if ((bar1_size == 0) || (bar1_addr == 0)) {
++			printf("%s: BAR1 Not enabled for this device  size(%ld),"
++				" addr(0x"PRINTF_RESOURCE")\n",
++				__FUNCTION__, bar1_size, bar1_addr);
++			goto err;
++		}
++
++		dhdpcie_info->regs = (volatile char *) REG_MAP(bar0_addr, DONGLE_REG_MAP_SIZE);
++		dhdpcie_info->tcm_size =
++			(bar1_size > DONGLE_TCM_MAP_SIZE) ? bar1_size : DONGLE_TCM_MAP_SIZE;
++		dhdpcie_info->tcm = (volatile char *) REG_MAP(bar1_addr, dhdpcie_info->tcm_size);
++
++		if (!dhdpcie_info->regs || !dhdpcie_info->tcm) {
++			DHD_ERROR(("%s:ioremap() failed\n", __FUNCTION__));
++			break;
++		}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++		if (!dhd_download_fw_on_driverload) {
++			/* Backup PCIe configuration so as to use Wi-Fi on/off process
++			 * in case of built in driver
++			 */
++			pci_save_state(pdev);
++			dhdpcie_info->default_state = pci_store_saved_state(pdev);
++
++			if (dhdpcie_info->default_state == NULL) {
++				DHD_ERROR(("%s pci_store_saved_state returns NULL\n",
++					__FUNCTION__));
++				REG_UNMAP(dhdpcie_info->regs);
++				REG_UNMAP(dhdpcie_info->tcm);
++				pci_disable_device(pdev);
++				break;
++			}
++		}
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++
++#ifdef EXYNOS_PCIE_MODULE_PATCH
++		pci_save_state(pdev);
++#endif /* EXYNOS_MODULE_PATCH */
++
++		DHD_TRACE(("%s:Phys addr : reg space = %p base addr 0x"PRINTF_RESOURCE" \n",
++			__FUNCTION__, dhdpcie_info->regs, bar0_addr));
++		DHD_TRACE(("%s:Phys addr : tcm_space = %p base addr 0x"PRINTF_RESOURCE" \n",
++			__FUNCTION__, dhdpcie_info->tcm, bar1_addr));
++
++		return 0; /* SUCCESS  */
++	} while (0);
++err:
++	return -1;  /* FAILURE */
++}
++
++int dhdpcie_scan_resource(dhdpcie_info_t *dhdpcie_info)
++{
++
++	DHD_TRACE(("%s: ENTER\n", __FUNCTION__));
++
++	do {
++		/* define it here only!! */
++		if (dhdpcie_get_resource (dhdpcie_info)) {
++			DHD_ERROR(("%s: Failed to get PCI resources\n", __FUNCTION__));
++			break;
++		}
++		DHD_TRACE(("%s:Exit - SUCCESS \n",
++			__FUNCTION__));
++
++		return 0; /* SUCCESS */
++
++	} while (0);
++
++	DHD_TRACE(("%s:Exit - FAILURE \n", __FUNCTION__));
++
++	return -1; /* FAILURE */
++
++}
++
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#if defined(CONFIG_ARCH_MSM) || (defined(EXYNOS_PCIE_LINKDOWN_RECOVERY) && \
++	(defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS8895)))
++void dhdpcie_linkdown_cb(struct_pcie_notify *noti)
++{
++	struct pci_dev *pdev = (struct pci_dev *)noti->user;
++	dhdpcie_info_t *pch = NULL;
++
++	if (pdev) {
++		pch = pci_get_drvdata(pdev);
++		if (pch) {
++			dhd_bus_t *bus = pch->bus;
++			if (bus) {
++				dhd_pub_t *dhd = bus->dhd;
++				if (dhd) {
++					DHD_ERROR(("%s: Event HANG send up "
++						"due to PCIe linkdown\n",
++						__FUNCTION__));
++#ifdef CONFIG_ARCH_MSM
++					bus->no_cfg_restore = 1;
++#endif /* CONFIG_ARCH_MSM */
++					bus->is_linkdown = 1;
++					DHD_OS_WAKE_LOCK(dhd);
++					dhd->hang_reason = HANG_REASON_PCIE_LINK_DOWN;
++					dhd_os_send_hang_message(dhd);
++				}
++			}
++		}
++	}
++
++}
++#endif
++/* CONFIG_ARCH_MSM || (EXYNOS_PCIE_LINKDOWN_RECOVERY &&
++	* (CONFIG_SOC_EXYNOS8890 || CONFIG_SOC_EXYNOS8895))
++	*/
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++
++int dhdpcie_init(struct pci_dev *pdev)
++{
++
++	osl_t 				*osh = NULL;
++	dhd_bus_t 			*bus = NULL;
++	dhdpcie_info_t		*dhdpcie_info =  NULL;
++	wifi_adapter_info_t	*adapter = NULL;
++#ifdef BCMPCIE_OOB_HOST_WAKE
++	dhdpcie_os_info_t	*dhdpcie_osinfo = NULL;
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#ifdef USE_SMMU_ARCH_MSM
++	dhdpcie_smmu_info_t	*dhdpcie_smmu_info = NULL;
++#endif /* USE_SMMU_ARCH_MSM */
++
++	do {
++		/* osl attach */
++		if (!(osh = osl_attach(pdev, PCI_BUS, FALSE))) {
++			DHD_ERROR(("%s: osl_attach failed\n", __FUNCTION__));
++			break;
++		}
++
++		/* initialize static buffer */
++		adapter = dhd_wifi_platform_get_adapter(PCI_BUS, pdev->bus->number,
++			PCI_SLOT(pdev->devfn));
++		if (adapter != NULL) {
++			DHD_ERROR(("%s: found adapter info '%s'\n", __FUNCTION__, adapter->name));
++#ifdef BUS_POWER_RESTORE
++			adapter->pci_dev = pdev;
++#endif
++		} else
++			DHD_ERROR(("%s: can't find adapter info for this chip\n", __FUNCTION__));
++		osl_static_mem_init(osh, adapter);
++
++		/* Set ACP coherence flag */
++		if (OSL_ACP_WAR_ENAB() || OSL_ARCH_IS_COHERENT())
++			osl_flag_set(osh, OSL_ACP_COHERENCE);
++
++		/*  allocate linux spcific pcie structure here */
++		if (!(dhdpcie_info = MALLOC(osh, sizeof(dhdpcie_info_t)))) {
++			DHD_ERROR(("%s: MALLOC of dhd_bus_t failed\n", __FUNCTION__));
++			break;
++		}
++		bzero(dhdpcie_info, sizeof(dhdpcie_info_t));
++		dhdpcie_info->osh = osh;
++		dhdpcie_info->dev = pdev;
++
++#ifdef BCMPCIE_OOB_HOST_WAKE
++		/* allocate OS speicific structure */
++		dhdpcie_osinfo = MALLOC(osh, sizeof(dhdpcie_os_info_t));
++		if (dhdpcie_osinfo == NULL) {
++			DHD_ERROR(("%s: MALLOC of dhdpcie_os_info_t failed\n",
++				__FUNCTION__));
++			break;
++		}
++		bzero(dhdpcie_osinfo, sizeof(dhdpcie_os_info_t));
++		dhdpcie_info->os_cxt = (void *)dhdpcie_osinfo;
++
++		/* Initialize host wake IRQ */
++		spin_lock_init(&dhdpcie_osinfo->oob_irq_spinlock);
++		/* Get customer specific host wake IRQ parametres: IRQ number as IRQ type */
++		dhdpcie_osinfo->oob_irq_num = wifi_platform_get_irq_number(adapter,
++			&dhdpcie_osinfo->oob_irq_flags);
++		if (dhdpcie_osinfo->oob_irq_num < 0) {
++			DHD_ERROR(("%s: Host OOB irq is not defined\n", __FUNCTION__));
++		}
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++
++#ifdef USE_SMMU_ARCH_MSM
++		/* allocate private structure for using SMMU */
++		dhdpcie_smmu_info = MALLOC(osh, sizeof(dhdpcie_smmu_info_t));
++		if (dhdpcie_smmu_info == NULL) {
++			DHD_ERROR(("%s: MALLOC of dhdpcie_smmu_info_t failed\n",
++				__FUNCTION__));
++			break;
++		}
++		bzero(dhdpcie_smmu_info, sizeof(dhdpcie_smmu_info_t));
++		dhdpcie_info->smmu_cxt = (void *)dhdpcie_smmu_info;
++
++		/* Initialize smmu structure */
++		if (dhdpcie_smmu_init(pdev, dhdpcie_info->smmu_cxt) < 0) {
++			DHD_ERROR(("%s: Failed to initialize SMMU\n",
++				__FUNCTION__));
++			break;
++		}
++#endif /* USE_SMMU_ARCH_MSM */
++
++#ifdef DHD_WAKE_STATUS
++		/* Initialize pcie_lock */
++		spin_lock_init(&dhdpcie_info->pcie_lock);
++#endif /* DHD_WAKE_STATUS */
++
++		/* Find the PCI resources, verify the  */
++		/* vendor and device ID, map BAR regions and irq,  update in structures */
++		if (dhdpcie_scan_resource(dhdpcie_info)) {
++			DHD_ERROR(("%s: dhd_Scan_PCI_Res failed\n", __FUNCTION__));
++
++			break;
++		}
++
++		/* Bus initialization */
++		bus = dhdpcie_bus_attach(osh, dhdpcie_info->regs, dhdpcie_info->tcm, pdev);
++		if (!bus) {
++			DHD_ERROR(("%s:dhdpcie_bus_attach() failed\n", __FUNCTION__));
++			break;
++		}
++
++		dhdpcie_info->bus = bus;
++		bus->is_linkdown = 0;
++
++		/* Get RC Device Handle */
++#if defined(PCIE_RC_VENDOR_ID) && defined(PCIE_RC_DEVICE_ID)
++		bus->rc_dev = pci_get_device(PCIE_RC_VENDOR_ID, PCIE_RC_DEVICE_ID, NULL);
++#else
++		bus->rc_dev = NULL;
++#endif
++
++#if defined(BCMPCIE_OOB_HOST_WAKE) && defined(CUSTOMER_HW2) && \
++	defined(CONFIG_ARCH_APQ8084)
++		brcm_pcie_wake.wake_irq = wlan_oob_irq;
++		brcm_pcie_wake.data = bus;
++#endif /* BCMPCIE_OOB_HOST_WAKE && CUSTOMR_HW2 && CONFIG_ARCH_APQ8084 */
++
++#ifdef DONGLE_ENABLE_ISOLATION
++		bus->dhd->dongle_isolation = TRUE;
++#endif /* DONGLE_ENABLE_ISOLATION */
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#ifdef CONFIG_ARCH_MSM
++		bus->pcie_event.events = MSM_PCIE_EVENT_LINKDOWN;
++		bus->pcie_event.user = pdev;
++		bus->pcie_event.mode = MSM_PCIE_TRIGGER_CALLBACK;
++		bus->pcie_event.callback = dhdpcie_linkdown_cb;
++		bus->pcie_event.options = MSM_PCIE_CONFIG_NO_RECOVERY;
++		msm_pcie_register_event(&bus->pcie_event);
++		bus->no_cfg_restore = 0;
++#endif /* CONFIG_ARCH_MSM */
++#ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
++#if defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS8895)
++		bus->pcie_event.events = EXYNOS_PCIE_EVENT_LINKDOWN;
++		bus->pcie_event.user = pdev;
++		bus->pcie_event.mode = EXYNOS_PCIE_TRIGGER_CALLBACK;
++		bus->pcie_event.callback = dhdpcie_linkdown_cb;
++		exynos_pcie_register_event(&bus->pcie_event);
++#endif /* CONFIG_SOC_EXYNOS8890 || CONFIG_SOC_EXYNOS8895 */
++#endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
++		bus->read_shm_fail = FALSE;
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++
++		if (bus->intr) {
++			/* Register interrupt callback, but mask it (not operational yet). */
++			DHD_INTR(("%s: Registering and masking interrupts\n", __FUNCTION__));
++			dhdpcie_bus_intr_disable(bus);
++
++			if (dhdpcie_request_irq(dhdpcie_info)) {
++				DHD_ERROR(("%s: request_irq() failed\n", __FUNCTION__));
++				break;
++			}
++		} else {
++			bus->pollrate = 1;
++			DHD_INFO(("%s: PCIe interrupt function is NOT registered "
++				"due to polling mode\n", __FUNCTION__));
++		}
++
++#if defined(BCM_REQUEST_FW)
++		if (dhd_bus_download_firmware(bus, osh, NULL, NULL) < 0) {
++		DHD_ERROR(("%s: failed to download firmware\n", __FUNCTION__));
++		}
++		bus->nv_path = NULL;
++		bus->fw_path = NULL;
++#endif /* BCM_REQUEST_FW */
++
++		/* set private data for pci_dev */
++		pci_set_drvdata(pdev, dhdpcie_info);
++
++		if (dhd_download_fw_on_driverload) {
++			if (dhd_bus_start(bus->dhd)) {
++				DHD_ERROR(("%s: dhd_bud_start() failed\n", __FUNCTION__));
++				if (!allow_delay_fwdl)
++					break;
++			}
++		} else {
++			/* Set ramdom MAC address during boot time */
++			get_random_bytes(&bus->dhd->mac.octet[3], 3);
++			/* Adding BRCM OUI */
++			bus->dhd->mac.octet[0] = 0;
++			bus->dhd->mac.octet[1] = 0x90;
++			bus->dhd->mac.octet[2] = 0x4C;
++		}
++
++		/* Attach to the OS network interface */
++		DHD_TRACE(("%s(): Calling dhd_register_if() \n", __FUNCTION__));
++		if (dhd_register_if(bus->dhd, 0, TRUE)) {
++			DHD_ERROR(("%s(): ERROR.. dhd_register_if() failed\n", __FUNCTION__));
++			break;
++		}
++
++		dhdpcie_init_succeeded = TRUE;
++
++#if defined(MULTIPLE_SUPPLICANT)
++		wl_android_post_init(); // terence 20120530: fix critical section in dhd_open and dhdsdio_probe
++#endif /* MULTIPLE_SUPPLICANT */
++
++		DHD_TRACE(("%s:Exit - SUCCESS \n", __FUNCTION__));
++		return 0;  /* return  SUCCESS  */
++
++	} while (0);
++	/* reverse the initialization in order in case of error */
++
++	if (bus)
++		dhdpcie_bus_release(bus);
++
++#ifdef BCMPCIE_OOB_HOST_WAKE
++	if (dhdpcie_osinfo) {
++		MFREE(osh, dhdpcie_osinfo, sizeof(dhdpcie_os_info_t));
++	}
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++
++#ifdef USE_SMMU_ARCH_MSM
++	if (dhdpcie_smmu_info) {
++		MFREE(osh, dhdpcie_smmu_info, sizeof(dhdpcie_smmu_info_t));
++		dhdpcie_info->smmu_cxt = NULL;
++	}
++#endif /* USE_SMMU_ARCH_MSM */
++
++	if (dhdpcie_info)
++		dhdpcie_detach(dhdpcie_info);
++	pci_disable_device(pdev);
++	if (osh)
++		osl_detach(osh);
++
++	dhdpcie_init_succeeded = FALSE;
++
++	DHD_TRACE(("%s:Exit - FAILURE \n", __FUNCTION__));
++
++	return -1; /* return FAILURE  */
++}
++
++/* Free Linux irq */
++void
++dhdpcie_free_irq(dhd_bus_t *bus)
++{
++	struct pci_dev *pdev = NULL;
++
++	DHD_TRACE(("%s: freeing up the IRQ\n", __FUNCTION__));
++	if (bus) {
++		pdev = bus->dev;
++		if (bus->irq_registered) {
++			free_irq(pdev->irq, bus);
++			bus->irq_registered = FALSE;
++#ifdef DHD_USE_MSI
++			pci_disable_msi(pdev);
++#endif /* DHD_USE_MSI */
++		} else {
++			DHD_ERROR(("%s: PCIe IRQ is not registered\n", __FUNCTION__));
++		}
++	}
++	DHD_TRACE(("%s: Exit\n", __FUNCTION__));
++	return;
++}
++
++/*
++
++Name:  dhdpcie_isr
++
++Parametrs:
++
++1: IN int irq   -- interrupt vector
++2: IN void *arg      -- handle to private data structure
++
++Return value:
++
++Status (TRUE or FALSE)
++
++Description:
++Interrupt Service routine checks for the status register,
++disable interrupt and queue DPC if mail box interrupts are raised.
++*/
++
++
++irqreturn_t
++dhdpcie_isr(int irq, void *arg)
++{
++	dhd_bus_t *bus = (dhd_bus_t*)arg;
++	if (dhdpcie_bus_isr(bus))
++		return TRUE;
++	else
++		return FALSE;
++}
++
++int
++dhdpcie_disable_irq_nosync(dhd_bus_t *bus)
++{
++	struct pci_dev *dev;
++	if ((bus == NULL) || (bus->dev == NULL)) {
++		DHD_ERROR(("%s: bus or bus->dev is NULL\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	dev = bus->dev;
++	disable_irq_nosync(dev->irq);
++	return BCME_OK;
++}
++
++int
++dhdpcie_disable_irq(dhd_bus_t *bus)
++{
++	struct pci_dev *dev;
++	if ((bus == NULL) || (bus->dev == NULL)) {
++		DHD_ERROR(("%s: bus or bus->dev is NULL\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	dev = bus->dev;
++	disable_irq(dev->irq);
++	return BCME_OK;
++}
++
++int
++dhdpcie_enable_irq(dhd_bus_t *bus)
++{
++	struct pci_dev *dev;
++	if ((bus == NULL) || (bus->dev == NULL)) {
++		DHD_ERROR(("%s: bus or bus->dev is NULL\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	dev = bus->dev;
++	enable_irq(dev->irq);
++	return BCME_OK;
++}
++
++bool
++dhdpcie_irq_enabled(dhd_bus_t *bus)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
++	struct irq_desc *desc = irq_to_desc(bus->dev->irq);
++	/* depth will be zero, if enabled */
++	if (!desc->depth) {
++		DHD_ERROR(("%s: depth:%d\n", __FUNCTION__, desc->depth));
++	}
++	return desc->depth ? FALSE : TRUE;
++#else
++	/* return TRUE by default as there is no support for lower versions */
++	return TRUE;
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++}
++
++int
++dhdpcie_start_host_pcieclock(dhd_bus_t *bus)
++{
++	int ret = 0;
++#ifdef CONFIG_ARCH_MSM
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++	int options = 0;
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++#endif /* CONFIG_ARCH_MSM */
++	DHD_TRACE(("%s Enter:\n", __FUNCTION__));
++
++	if (bus == NULL) {
++		return BCME_ERROR;
++	}
++
++	if (bus->dev == NULL) {
++		return BCME_ERROR;
++	}
++
++#ifdef CONFIG_ARCH_MSM
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++	if (bus->no_cfg_restore) {
++		options = MSM_PCIE_CONFIG_NO_CFG_RESTORE;
++	}
++	ret = msm_pcie_pm_control(MSM_PCIE_RESUME, bus->dev->bus->number,
++		bus->dev, NULL, options);
++	if (bus->no_cfg_restore && !ret) {
++		msm_pcie_recover_config(bus->dev);
++		bus->no_cfg_restore = 0;
++	}
++#else
++	ret = msm_pcie_pm_control(MSM_PCIE_RESUME, bus->dev->bus->number,
++		bus->dev, NULL, 0);
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++	if (ret) {
++		DHD_ERROR(("%s Failed to bring up PCIe link\n", __FUNCTION__));
++		goto done;
++	}
++
++done:
++#endif /* CONFIG_ARCH_MSM */
++	DHD_TRACE(("%s Exit:\n", __FUNCTION__));
++	return ret;
++}
++
++int
++dhdpcie_stop_host_pcieclock(dhd_bus_t *bus)
++{
++	int ret = 0;
++#ifdef CONFIG_ARCH_MSM
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++	int options = 0;
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++#endif /* CONFIG_ARCH_MSM */
++
++	DHD_TRACE(("%s Enter:\n", __FUNCTION__));
++
++	if (bus == NULL) {
++		return BCME_ERROR;
++	}
++
++	if (bus->dev == NULL) {
++		return BCME_ERROR;
++	}
++
++#ifdef CONFIG_ARCH_MSM
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++	/* Always reset the PCIe host when wifi off */
++	bus->no_cfg_restore = 1;
++
++	if (bus->no_cfg_restore) {
++		options = MSM_PCIE_CONFIG_NO_CFG_RESTORE | MSM_PCIE_CONFIG_LINKDOWN;
++	}
++
++	ret = msm_pcie_pm_control(MSM_PCIE_SUSPEND, bus->dev->bus->number,
++		bus->dev, NULL, options);
++#else
++	ret = msm_pcie_pm_control(MSM_PCIE_SUSPEND, bus->dev->bus->number,
++		bus->dev, NULL, 0);
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++	if (ret) {
++		DHD_ERROR(("Failed to stop PCIe link\n"));
++		goto done;
++	}
++done:
++#endif /* CONFIG_ARCH_MSM */
++	DHD_TRACE(("%s Exit:\n", __FUNCTION__));
++	return ret;
++}
++
++int
++dhdpcie_disable_device(dhd_bus_t *bus)
++{
++	DHD_TRACE(("%s Enter:\n", __FUNCTION__));
++
++	if (bus == NULL) {
++		return BCME_ERROR;
++	}
++
++	if (bus->dev == NULL) {
++		return BCME_ERROR;
++	}
++
++	pci_disable_device(bus->dev);
++
++	return 0;
++}
++
++int
++dhdpcie_enable_device(dhd_bus_t *bus)
++{
++	int ret = BCME_ERROR;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	dhdpcie_info_t *pch;
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++
++	DHD_TRACE(("%s Enter:\n", __FUNCTION__));
++
++	if (bus == NULL) {
++		return BCME_ERROR;
++	}
++
++	if (bus->dev == NULL) {
++		return BCME_ERROR;
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	pch = pci_get_drvdata(bus->dev);
++	if (pch == NULL) {
++		return BCME_ERROR;
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) && (LINUX_VERSION_CODE < \
++	KERNEL_VERSION(3, 19, 0)) && !defined(CONFIG_SOC_EXYNOS8890)
++	/* Updated with pci_load_and_free_saved_state to compatible
++	 * with Kernel version 3.14.0 to 3.18.41.
++	 */
++	pci_load_and_free_saved_state(bus->dev, &pch->default_state);
++	pch->default_state = pci_store_saved_state(bus->dev);
++#else
++	pci_load_saved_state(bus->dev, pch->default_state);
++#endif /* LINUX_VERSION >= 3.14.0 && LINUX_VERSION < 3.19.0 && !CONFIG_SOC_EXYNOS8890 */
++
++	pci_restore_state(bus->dev);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) */
++
++	ret = pci_enable_device(bus->dev);
++	if (ret) {
++		pci_disable_device(bus->dev);
++	} else {
++		pci_set_master(bus->dev);
++	}
++
++	return ret;
++}
++
++int
++dhdpcie_alloc_resource(dhd_bus_t *bus)
++{
++	dhdpcie_info_t *dhdpcie_info;
++	phys_addr_t bar0_addr, bar1_addr;
++	ulong bar1_size;
++
++	do {
++		if (bus == NULL) {
++			DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
++			break;
++		}
++
++		if (bus->dev == NULL) {
++			DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
++			break;
++		}
++
++		dhdpcie_info = pci_get_drvdata(bus->dev);
++		if (dhdpcie_info == NULL) {
++			DHD_ERROR(("%s: dhdpcie_info is NULL\n", __FUNCTION__));
++			break;
++		}
++
++		bar0_addr = pci_resource_start(bus->dev, 0);	/* Bar-0 mapped address */
++		bar1_addr = pci_resource_start(bus->dev, 2);	/* Bar-1 mapped address */
++
++		/* read Bar-1 mapped memory range */
++		bar1_size = pci_resource_len(bus->dev, 2);
++
++		if ((bar1_size == 0) || (bar1_addr == 0)) {
++			printf("%s: BAR1 Not enabled for this device size(%ld),"
++				" addr(0x"PRINTF_RESOURCE")\n",
++				__FUNCTION__, bar1_size, bar1_addr);
++			break;
++		}
++
++		dhdpcie_info->regs = (volatile char *) REG_MAP(bar0_addr, DONGLE_REG_MAP_SIZE);
++		if (!dhdpcie_info->regs) {
++			DHD_ERROR(("%s: ioremap() for regs is failed\n", __FUNCTION__));
++			break;
++		}
++
++		bus->regs = dhdpcie_info->regs;
++		dhdpcie_info->tcm_size =
++			(bar1_size > DONGLE_TCM_MAP_SIZE) ? bar1_size : DONGLE_TCM_MAP_SIZE;
++		dhdpcie_info->tcm = (volatile char *) REG_MAP(bar1_addr, dhdpcie_info->tcm_size);
++		if (!dhdpcie_info->tcm) {
++			DHD_ERROR(("%s: ioremap() for regs is failed\n", __FUNCTION__));
++			REG_UNMAP(dhdpcie_info->regs);
++			bus->regs = NULL;
++			break;
++		}
++
++		bus->tcm = dhdpcie_info->tcm;
++
++		DHD_TRACE(("%s:Phys addr : reg space = %p base addr 0x"PRINTF_RESOURCE" \n",
++			__FUNCTION__, dhdpcie_info->regs, bar0_addr));
++		DHD_TRACE(("%s:Phys addr : tcm_space = %p base addr 0x"PRINTF_RESOURCE" \n",
++			__FUNCTION__, dhdpcie_info->tcm, bar1_addr));
++
++		return 0;
++	} while (0);
++
++	return BCME_ERROR;
++}
++
++void
++dhdpcie_free_resource(dhd_bus_t *bus)
++{
++	dhdpcie_info_t *dhdpcie_info;
++
++	if (bus == NULL) {
++		DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (bus->dev == NULL) {
++		DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	dhdpcie_info = pci_get_drvdata(bus->dev);
++	if (dhdpcie_info == NULL) {
++		DHD_ERROR(("%s: dhdpcie_info is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (bus->regs) {
++		REG_UNMAP(dhdpcie_info->regs);
++		bus->regs = NULL;
++	}
++
++	if (bus->tcm) {
++		REG_UNMAP(dhdpcie_info->tcm);
++		bus->tcm = NULL;
++	}
++}
++
++int
++dhdpcie_bus_request_irq(struct dhd_bus *bus)
++{
++	dhdpcie_info_t *dhdpcie_info;
++	int ret = 0;
++
++	if (bus == NULL) {
++		DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	if (bus->dev == NULL) {
++		DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	dhdpcie_info = pci_get_drvdata(bus->dev);
++	if (dhdpcie_info == NULL) {
++		DHD_ERROR(("%s: dhdpcie_info is NULL\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	if (bus->intr) {
++		/* Register interrupt callback, but mask it (not operational yet). */
++		DHD_INTR(("%s: Registering and masking interrupts\n", __FUNCTION__));
++		dhdpcie_bus_intr_disable(bus);
++		ret = dhdpcie_request_irq(dhdpcie_info);
++		if (ret) {
++			DHD_ERROR(("%s: request_irq() failed, ret=%d\n",
++				__FUNCTION__, ret));
++			return ret;
++		}
++	}
++
++	return ret;
++}
++
++#ifdef BCMPCIE_OOB_HOST_WAKE
++void dhdpcie_oob_intr_set(dhd_bus_t *bus, bool enable)
++{
++	unsigned long flags;
++	dhdpcie_info_t *pch;
++	dhdpcie_os_info_t *dhdpcie_osinfo;
++
++	if (bus == NULL) {
++		DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (bus->dev == NULL) {
++		DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	pch = pci_get_drvdata(bus->dev);
++	if (pch == NULL) {
++		DHD_ERROR(("%s: pch is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	dhdpcie_osinfo = (dhdpcie_os_info_t *)pch->os_cxt;
++	spin_lock_irqsave(&dhdpcie_osinfo->oob_irq_spinlock, flags);
++	if ((dhdpcie_osinfo->oob_irq_enabled != enable) &&
++		(dhdpcie_osinfo->oob_irq_num > 0)) {
++		if (enable) {
++			enable_irq(dhdpcie_osinfo->oob_irq_num);
++		} else {
++			disable_irq_nosync(dhdpcie_osinfo->oob_irq_num);
++		}
++		dhdpcie_osinfo->oob_irq_enabled = enable;
++	}
++	spin_unlock_irqrestore(&dhdpcie_osinfo->oob_irq_spinlock, flags);
++}
++
++static irqreturn_t wlan_oob_irq(int irq, void *data)
++{
++	dhd_bus_t *bus;
++	DHD_TRACE(("%s: IRQ Triggered\n", __FUNCTION__));
++	bus = (dhd_bus_t *)data;
++	dhdpcie_oob_intr_set(bus, FALSE);
++#ifdef DHD_WAKE_STATUS
++#ifdef DHD_PCIE_RUNTIMEPM
++	/* This condition is for avoiding counting of wake up from Runtime PM */
++	if (bus->chk_pm)
++#endif /* DHD_PCIE_RUNTIMPM */
++	{
++		bcmpcie_set_get_wake(bus, 1);
++	}
++#endif /* DHD_WAKE_STATUS */
++#ifdef DHD_PCIE_RUNTIMEPM
++	dhdpcie_runtime_bus_wake(bus->dhd, FALSE, wlan_oob_irq);
++#endif /* DHD_PCIE_RUNTIMPM */
++	if (bus->dhd->up && bus->oob_presuspend) {
++		DHD_OS_OOB_IRQ_WAKE_LOCK_TIMEOUT(bus->dhd, OOB_WAKE_LOCK_TIMEOUT);
++	}
++	return IRQ_HANDLED;
++}
++
++int dhdpcie_oob_intr_register(dhd_bus_t *bus)
++{
++	int err = 0;
++	dhdpcie_info_t *pch;
++	dhdpcie_os_info_t *dhdpcie_osinfo;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++	if (bus == NULL) {
++		DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
++		return -EINVAL;
++	}
++
++	if (bus->dev == NULL) {
++		DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
++		return -EINVAL;
++	}
++
++	pch = pci_get_drvdata(bus->dev);
++	if (pch == NULL) {
++		DHD_ERROR(("%s: pch is NULL\n", __FUNCTION__));
++		return -EINVAL;
++	}
++
++	dhdpcie_osinfo = (dhdpcie_os_info_t *)pch->os_cxt;
++	if (dhdpcie_osinfo->oob_irq_registered) {
++		DHD_ERROR(("%s: irq is already registered\n", __FUNCTION__));
++		return -EBUSY;
++	}
++
++	if (dhdpcie_osinfo->oob_irq_num > 0) {
++		printf("%s OOB irq=%d flags=0x%X\n", __FUNCTION__,
++			(int)dhdpcie_osinfo->oob_irq_num,
++			(int)dhdpcie_osinfo->oob_irq_flags);
++		err = request_irq(dhdpcie_osinfo->oob_irq_num, wlan_oob_irq,
++			dhdpcie_osinfo->oob_irq_flags, "dhdpcie_host_wake",
++			bus);
++		if (err) {
++			DHD_ERROR(("%s: request_irq failed with %d\n",
++				__FUNCTION__, err));
++			return err;
++		}
++#if defined(DISABLE_WOWLAN)
++		printf("%s: disable_irq_wake\n", __FUNCTION__);
++		dhdpcie_osinfo->oob_irq_wake_enabled = FALSE;
++#else
++		printf("%s: enable_irq_wake\n", __FUNCTION__);
++		err = enable_irq_wake(dhdpcie_osinfo->oob_irq_num);
++		if (!err) {
++			dhdpcie_osinfo->oob_irq_wake_enabled = TRUE;
++		} else
++			printf("%s: enable_irq_wake failed with %d\n", __FUNCTION__, err);
++#endif
++		dhdpcie_osinfo->oob_irq_enabled = TRUE;
++	}
++
++	dhdpcie_osinfo->oob_irq_registered = TRUE;
++
++	return err;
++}
++
++void dhdpcie_oob_intr_unregister(dhd_bus_t *bus)
++{
++	int err = 0;
++	dhdpcie_info_t *pch;
++	dhdpcie_os_info_t *dhdpcie_osinfo;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++	if (bus == NULL) {
++		DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (bus->dev == NULL) {
++		DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	pch = pci_get_drvdata(bus->dev);
++	if (pch == NULL) {
++		DHD_ERROR(("%s: pch is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	dhdpcie_osinfo = (dhdpcie_os_info_t *)pch->os_cxt;
++	if (!dhdpcie_osinfo->oob_irq_registered) {
++		DHD_ERROR(("%s: irq is not registered\n", __FUNCTION__));
++		return;
++	}
++	if (dhdpcie_osinfo->oob_irq_num > 0) {
++		if (dhdpcie_osinfo->oob_irq_wake_enabled) {
++			err = disable_irq_wake(dhdpcie_osinfo->oob_irq_num);
++			if (!err) {
++				dhdpcie_osinfo->oob_irq_wake_enabled = FALSE;
++			}
++		}
++		if (dhdpcie_osinfo->oob_irq_enabled) {
++			disable_irq(dhdpcie_osinfo->oob_irq_num);
++			dhdpcie_osinfo->oob_irq_enabled = FALSE;
++		}
++		free_irq(dhdpcie_osinfo->oob_irq_num, bus);
++	}
++	dhdpcie_osinfo->oob_irq_registered = FALSE;
++}
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++
++#ifdef PCIE_OOB
++void dhdpcie_oob_init(dhd_bus_t *bus)
++{
++	gpio_handle_val = get_handle(OOB_PORT);
++	if (gpio_handle_val < 0)
++	{
++		DHD_ERROR(("%s: Could not get GPIO handle.\n", __FUNCTION__));
++		ASSERT(FALSE);
++	}
++
++	gpio_direction = 0;
++	ftdi_set_bitmode(gpio_handle_val, 0, BITMODE_BITBANG);
++
++	/* Note BT core is also enabled here */
++	gpio_port = 1 << BIT_WL_REG_ON | 1 << BIT_BT_REG_ON | 1 << DEVICE_WAKE;
++	gpio_write_port(gpio_handle_val, gpio_port);
++
++	gpio_direction = 1 << BIT_WL_REG_ON | 1 << BIT_BT_REG_ON | 1 << DEVICE_WAKE;
++	ftdi_set_bitmode(gpio_handle_val, gpio_direction, BITMODE_BITBANG);
++
++	bus->oob_enabled = TRUE;
++	bus->oob_presuspend = FALSE;
++
++	/* drive the Device_Wake GPIO low on startup */
++	bus->device_wake_state = TRUE;
++	dhd_bus_set_device_wake(bus, FALSE);
++	dhd_bus_doorbell_timeout_reset(bus);
++
++}
++
++void
++dhd_oob_set_bt_reg_on(struct dhd_bus *bus, bool val)
++{
++	DHD_INFO(("Set Device_Wake to %d\n", val));
++	if (val)
++	{
++		gpio_port = gpio_port | (1 << BIT_BT_REG_ON);
++		gpio_write_port(gpio_handle_val, gpio_port);
++	} else {
++		gpio_port = gpio_port & (0xff ^ (1 << BIT_BT_REG_ON));
++		gpio_write_port(gpio_handle_val, gpio_port);
++	}
++}
++
++int
++dhd_oob_get_bt_reg_on(struct dhd_bus *bus)
++{
++	int ret;
++	uint8 val;
++	ret = gpio_read_port(gpio_handle_val, &val);
++
++	if (ret < 0) {
++		DHD_ERROR(("gpio_read_port returns %d\n", ret));
++		return ret;
++	}
++
++	if (val & (1 << BIT_BT_REG_ON))
++	{
++		ret = 1;
++	} else {
++		ret = 0;
++	}
++
++	return ret;
++}
++
++int
++dhd_os_oob_set_device_wake(struct dhd_bus *bus, bool val)
++{
++	if (bus->device_wake_state != val)
++	{
++		DHD_INFO(("Set Device_Wake to %d\n", val));
++
++		if (bus->oob_enabled && !bus->oob_presuspend)
++		{
++			if (val)
++			{
++				gpio_port = gpio_port | (1 << DEVICE_WAKE);
++				gpio_write_port_non_block(gpio_handle_val, gpio_port);
++			} else {
++				gpio_port = gpio_port & (0xff ^ (1 << DEVICE_WAKE));
++				gpio_write_port_non_block(gpio_handle_val, gpio_port);
++			}
++		}
++
++		bus->device_wake_state = val;
++	}
++	return BCME_OK;
++}
++
++INLINE void
++dhd_os_ib_set_device_wake(struct dhd_bus *bus, bool val)
++{
++	/* TODO: Currently Inband implementation of Device_Wake is not supported,
++	 * so this function is left empty later this can be used to support the same.
++	 */
++}
++#endif /* PCIE_OOB */
++
++#ifdef DHD_PCIE_RUNTIMEPM
++bool dhd_runtimepm_state(dhd_pub_t *dhd)
++{
++	dhd_bus_t *bus;
++	unsigned long flags;
++	bus = dhd->bus;
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	bus->idlecount++;
++
++	DHD_TRACE(("%s : Enter \n", __FUNCTION__));
++	if ((bus->idletime > 0) && (bus->idlecount >= bus->idletime)) {
++		bus->idlecount = 0;
++		if (DHD_BUS_BUSY_CHECK_IDLE(dhd) && !DHD_BUS_CHECK_DOWN_OR_DOWN_IN_PROGRESS(dhd)) {
++			bus->bus_wake = 0;
++			DHD_BUS_BUSY_SET_RPM_SUSPEND_IN_PROGRESS(dhd);
++			bus->runtime_resume_done = FALSE;
++			/* stop all interface network queue. */
++			dhd_bus_stop_queue(bus);
++			DHD_GENERAL_UNLOCK(dhd, flags);
++			DHD_ERROR(("%s: DHD Idle state!! -  idletime :%d, wdtick :%d \n",
++					__FUNCTION__, bus->idletime, dhd_runtimepm_ms));
++			/* RPM suspend is failed, return FALSE then re-trying */
++			if (dhdpcie_set_suspend_resume(bus, TRUE)) {
++				DHD_ERROR(("%s: exit with wakelock \n", __FUNCTION__));
++				DHD_GENERAL_LOCK(dhd, flags);
++				DHD_BUS_BUSY_CLEAR_RPM_SUSPEND_IN_PROGRESS(dhd);
++				dhd_os_busbusy_wake(bus->dhd);
++				bus->runtime_resume_done = TRUE;
++				/* It can make stuck NET TX Queue without below */
++				dhd_bus_start_queue(bus);
++				DHD_GENERAL_UNLOCK(dhd, flags);
++				smp_wmb();
++				wake_up_interruptible(&bus->rpm_queue);
++				return FALSE;
++			}
++
++			DHD_GENERAL_LOCK(dhd, flags);
++			DHD_BUS_BUSY_CLEAR_RPM_SUSPEND_IN_PROGRESS(dhd);
++			DHD_BUS_BUSY_SET_RPM_SUSPEND_DONE(dhd);
++			/* For making sure NET TX Queue active  */
++			dhd_bus_start_queue(bus);
++			DHD_GENERAL_UNLOCK(dhd, flags);
++
++			wait_event_interruptible(bus->rpm_queue, bus->bus_wake);
++
++			DHD_GENERAL_LOCK(dhd, flags);
++			DHD_BUS_BUSY_CLEAR_RPM_SUSPEND_DONE(dhd);
++			DHD_BUS_BUSY_SET_RPM_RESUME_IN_PROGRESS(dhd);
++			DHD_GENERAL_UNLOCK(dhd, flags);
++
++			dhdpcie_set_suspend_resume(bus, FALSE);
++
++			DHD_GENERAL_LOCK(dhd, flags);
++			DHD_BUS_BUSY_CLEAR_RPM_RESUME_IN_PROGRESS(dhd);
++			dhd_os_busbusy_wake(bus->dhd);
++			/* Inform the wake up context that Resume is over */
++			bus->runtime_resume_done = TRUE;
++			/* For making sure NET TX Queue active  */
++			dhd_bus_start_queue(bus);
++			DHD_GENERAL_UNLOCK(dhd, flags);
++
++			smp_wmb();
++			wake_up_interruptible(&bus->rpm_queue);
++			DHD_ERROR(("%s : runtime resume ended \n", __FUNCTION__));
++			return TRUE;
++		} else {
++			DHD_GENERAL_UNLOCK(dhd, flags);
++			/* Since one of the contexts are busy (TX, IOVAR or RX)
++			 * we should not suspend
++			 */
++			DHD_ERROR(("%s : bus is active with dhd_bus_busy_state = 0x%x\n",
++				__FUNCTION__, dhd->dhd_bus_busy_state));
++			return FALSE;
++		}
++	}
++
++	DHD_GENERAL_UNLOCK(dhd, flags);
++	return FALSE;
++} /* dhd_runtimepm_state */
++
++/*
++ * dhd_runtime_bus_wake
++ *  TRUE - related with runtime pm context
++ *  FALSE - It isn't invloved in runtime pm context
++ */
++bool dhd_runtime_bus_wake(dhd_bus_t *bus, bool wait, void *func_addr)
++{
++	unsigned long flags;
++	bus->idlecount = 0;
++	DHD_TRACE(("%s : enter\n", __FUNCTION__));
++	if (bus->dhd->up == FALSE) {
++		DHD_INFO(("%s : dhd is not up\n", __FUNCTION__));
++		return FALSE;
++	}
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	if (DHD_BUS_BUSY_CHECK_RPM_ALL(bus->dhd)) {
++		/* Wake up RPM state thread if it is suspend in progress or suspended */
++		if (DHD_BUS_BUSY_CHECK_RPM_SUSPEND_IN_PROGRESS(bus->dhd) ||
++				DHD_BUS_BUSY_CHECK_RPM_SUSPEND_DONE(bus->dhd)) {
++			bus->bus_wake = 1;
++
++			DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++			DHD_ERROR(("Runtime Resume is called in %pf\n", func_addr));
++			smp_wmb();
++			wake_up_interruptible(&bus->rpm_queue);
++		/* No need to wake up the RPM state thread */
++		} else if (DHD_BUS_BUSY_CHECK_RPM_RESUME_IN_PROGRESS(bus->dhd)) {
++			DHD_GENERAL_UNLOCK(bus->dhd, flags);
++		}
++
++		/* If wait is TRUE, function with wait = TRUE will be wait in here  */
++		if (wait) {
++			wait_event_interruptible(bus->rpm_queue, bus->runtime_resume_done);
++		} else {
++			DHD_INFO(("%s: bus wakeup but no wait until resume done\n", __FUNCTION__));
++		}
++		/* If it is called from RPM context, it returns TRUE */
++		return TRUE;
++	}
++
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	return FALSE;
++}
++
++bool dhdpcie_runtime_bus_wake(dhd_pub_t *dhdp, bool wait, void* func_addr)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	return dhd_runtime_bus_wake(bus, wait, func_addr);
++}
++
++void dhdpcie_block_runtime_pm(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	bus->idletime = 0;
++}
++
++bool dhdpcie_is_resume_done(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	return bus->runtime_resume_done;
++}
++#endif /* DHD_PCIE_RUNTIMEPM */
++
++struct device * dhd_bus_to_dev(dhd_bus_t *bus)
++{
++	struct pci_dev *pdev;
++	pdev = bus->dev;
++
++	if (pdev)
++		return &pdev->dev;
++	else
++		return NULL;
++}
++
++#ifdef HOFFLOAD_MODULES
++void
++dhd_free_module_memory(struct dhd_bus *bus, struct module_metadata *hmem)
++{
++	struct device *dev = &bus->dev->dev;
++	if (hmem) {
++		dma_unmap_single(dev, (dma_addr_t) hmem->data_addr, hmem->size, DMA_TO_DEVICE);
++		kfree(hmem->data);
++		hmem->data = NULL;
++		hmem->size = 0;
++	} else {
++		DHD_ERROR(("dev:%p pci unmapping error\n", dev));
++	}
++}
++
++void *
++dhd_alloc_module_memory(struct dhd_bus *bus, uint32_t size, struct module_metadata *hmem)
++{
++	struct device *dev = &bus->dev->dev;
++	if (!hmem->data) {
++		hmem->data = kzalloc(size, GFP_KERNEL);
++		if (!hmem->data) {
++			DHD_ERROR(("dev:%p mem alloc failure\n", dev));
++			return NULL;
++		}
++	}
++	hmem->size = size;
++	DHD_INFO(("module size: 0x%x \n", hmem->size));
++	hmem->data_addr = (u64) dma_map_single(dev, hmem->data, hmem->size, DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, hmem->data_addr)) {
++		DHD_ERROR(("dev:%p dma mapping error\n", dev));
++		kfree(hmem->data);
++		hmem->data = NULL;
++		return hmem->data;
++	}
++	return hmem->data;
++}
++#endif /* HOFFLOAD_MODULES */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_pno.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_pno.c
+new file mode 100644
+index 000000000..af8f35cd0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_pno.c
+@@ -0,0 +1,4050 @@
++/*
++ * Broadcom Dongle Host Driver (DHD)
++ * Prefered Network Offload and Wi-Fi Location Service(WLS) code.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_pno.c 707287 2017-06-27 06:44:29Z $
++ */
++
++#if defined(GSCAN_SUPPORT) && !defined(PNO_SUPPORT)
++#error "GSCAN needs PNO to be enabled!"
++#endif
++
++#ifdef PNO_SUPPORT
++#include <typedefs.h>
++#include <osl.h>
++
++#include <epivers.h>
++#include <bcmutils.h>
++
++#include <bcmendian.h>
++#include <linuxver.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/sort.h>
++#include <dngl_stats.h>
++#include <wlioctl.h>
++
++#include <bcmevent.h>
++#include <dhd.h>
++#include <dhd_pno.h>
++#include <dhd_dbg.h>
++#ifdef GSCAN_SUPPORT
++#include <linux/gcd.h>
++#endif /* GSCAN_SUPPORT */
++#ifdef WL_CFG80211
++#include <wl_cfg80211.h>
++#endif /* WL_CFG80211 */
++
++#ifdef __BIG_ENDIAN
++#include <bcmendian.h>
++#define htod32(i) (bcmswap32(i))
++#define htod16(i) (bcmswap16(i))
++#define dtoh32(i) (bcmswap32(i))
++#define dtoh16(i) (bcmswap16(i))
++#define htodchanspec(i) htod16(i)
++#define dtohchanspec(i) dtoh16(i)
++#else
++#define htod32(i) (i)
++#define htod16(i) (i)
++#define dtoh32(i) (i)
++#define dtoh16(i) (i)
++#define htodchanspec(i) (i)
++#define dtohchanspec(i) (i)
++#endif /* IL_BIGENDINA */
++
++#define NULL_CHECK(p, s, err)  \
++			do { \
++				if (!(p)) { \
++					printf("NULL POINTER (%s) : %s\n", __FUNCTION__, (s)); \
++					err = BCME_ERROR; \
++					return err; \
++				} \
++			} while (0)
++#define PNO_GET_PNOSTATE(dhd) ((dhd_pno_status_info_t *)dhd->pno_state)
++#define PNO_BESTNET_LEN 1024
++#define PNO_ON 1
++#define PNO_OFF 0
++#define CHANNEL_2G_MAX 14
++#define CHANNEL_5G_MAX 165
++#define MAX_NODE_CNT 5
++#define WLS_SUPPORTED(pno_state) (pno_state->wls_supported == TRUE)
++#define TIME_DIFF(timestamp1, timestamp2) (abs((uint32)(timestamp1/1000)  \
++						- (uint32)(timestamp2/1000)))
++#define TIME_DIFF_MS(timestamp1, timestamp2) (abs((uint32)(timestamp1)  \
++						- (uint32)(timestamp2)))
++#define TIMESPEC_TO_US(ts)  (((uint64)(ts).tv_sec * USEC_PER_SEC) + \
++							(ts).tv_nsec / NSEC_PER_USEC)
++
++#define ENTRY_OVERHEAD strlen("bssid=\nssid=\nfreq=\nlevel=\nage=\ndist=\ndistSd=\n====")
++#define TIME_MIN_DIFF 5
++
++#define EVENT_DATABUF_MAXLEN	(512 - sizeof(bcm_event_t))
++#define EVENT_MAX_NETCNT_V1 \
++	((EVENT_DATABUF_MAXLEN - sizeof(wl_pfn_scanresults_v1_t)) \
++	/ sizeof(wl_pfn_net_info_v1_t) + 1)
++#define EVENT_MAX_NETCNT_V2 \
++	((EVENT_DATABUF_MAXLEN - sizeof(wl_pfn_scanresults_v2_t)) \
++	/ sizeof(wl_pfn_net_info_v2_t) + 1)
++
++#ifdef GSCAN_SUPPORT
++static int _dhd_pno_flush_ssid(dhd_pub_t *dhd);
++static wl_pfn_gscan_ch_bucket_cfg_t *
++dhd_pno_gscan_create_channel_list(dhd_pub_t *dhd, dhd_pno_status_info_t *pno_state,
++      uint16 *chan_list, uint32 *num_buckets, uint32 *num_buckets_to_fw);
++#endif /* GSCAN_SUPPORT */
++static int dhd_pno_set_legacy_pno(dhd_pub_t *dhd, uint16  scan_fr, int pno_repeat,
++		int pno_freq_expo_max, uint16 *channel_list, int nchan);
++
++static inline bool
++is_dfs(uint16 channel)
++{
++	if (channel >= 52 && channel <= 64)			/* class 2 */
++		return TRUE;
++	else if (channel >= 100 && channel <= 140)	/* class 4 */
++		return TRUE;
++	else
++		return FALSE;
++}
++int
++dhd_pno_clean(dhd_pub_t *dhd)
++{
++	int pfn = 0;
++	int err;
++	dhd_pno_status_info_t *_pno_state;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	/* Disable PNO */
++	err = dhd_iovar(dhd, 0, "pfn", (char *)&pfn, sizeof(pfn), NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfn(error : %d)\n",
++			__FUNCTION__, err));
++		goto exit;
++	}
++	_pno_state->pno_status = DHD_PNO_DISABLED;
++	err = dhd_iovar(dhd, 0, "pfnclear", NULL, 0, NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfnclear(error : %d)\n",
++			__FUNCTION__, err));
++	}
++exit:
++	return err;
++}
++
++bool
++dhd_is_pno_supported(dhd_pub_t *dhd)
++{
++	dhd_pno_status_info_t *_pno_state;
++
++	if (!dhd || !dhd->pno_state) {
++		DHD_ERROR(("NULL POINTER : %s\n",
++			__FUNCTION__));
++		return FALSE;
++	}
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	return WLS_SUPPORTED(_pno_state);
++}
++
++bool
++dhd_is_legacy_pno_enabled(dhd_pub_t *dhd)
++{
++	dhd_pno_status_info_t *_pno_state;
++
++	if (!dhd || !dhd->pno_state) {
++		DHD_ERROR(("NULL POINTER : %s\n",
++			__FUNCTION__));
++		return FALSE;
++	}
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	return ((_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) != 0);
++}
++
++#ifdef GSCAN_SUPPORT
++static uint64
++convert_fw_rel_time_to_systime(struct osl_timespec *ts, uint32 fw_ts_ms)
++{
++	return ((uint64)(TIMESPEC_TO_US(*ts)) - (uint64)(fw_ts_ms * 1000));
++}
++
++static void
++dhd_pno_idx_to_ssid(struct dhd_pno_gscan_params *gscan_params,
++            dhd_epno_results_t *res, uint32 idx)
++{
++	dhd_pno_ssid_t *iter, *next;
++	int i;
++
++	/* If idx doesn't make sense */
++	if (idx >= gscan_params->epno_cfg.num_epno_ssid) {
++		DHD_ERROR(("No match, idx %d num_ssid %d\n", idx,
++			gscan_params->epno_cfg.num_epno_ssid));
++		goto exit;
++	}
++
++	if (gscan_params->epno_cfg.num_epno_ssid > 0) {
++		i = 0;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++		list_for_each_entry_safe(iter, next,
++			&gscan_params->epno_cfg.epno_ssid_list, list) {
++			if (i++ == idx) {
++				memcpy(res->ssid, iter->SSID, iter->SSID_len);
++				res->ssid_len = iter->SSID_len;
++				return;
++			}
++		}
++	}
++exit:
++	/* If we are here then there was no match */
++	res->ssid[0] = '\0';
++	res->ssid_len = 0;
++	return;
++}
++
++/* Translate HAL flag bitmask to BRCM FW flag bitmask */
++void dhd_pno_translate_epno_fw_flags(uint32 *flags)
++{
++	uint32 in_flags, fw_flags = 0;
++	in_flags = *flags;
++
++	if (in_flags & DHD_EPNO_A_BAND_TRIG) {
++		fw_flags |= WL_PFN_SSID_A_BAND_TRIG;
++	}
++
++	if (in_flags & DHD_EPNO_BG_BAND_TRIG) {
++		fw_flags |= WL_PFN_SSID_BG_BAND_TRIG;
++	}
++
++	if (!(in_flags & DHD_EPNO_STRICT_MATCH) &&
++	    !(in_flags & DHD_EPNO_HIDDEN_SSID)) {
++		fw_flags |= WL_PFN_SSID_IMPRECISE_MATCH;
++	}
++
++	if (in_flags & DHD_EPNO_SAME_NETWORK) {
++		fw_flags |= WL_PFN_SSID_SAME_NETWORK;
++	}
++
++	/* Add any hard coded flags needed */
++	fw_flags |= WL_PFN_SUPPRESS_AGING_MASK;
++	*flags = fw_flags;
++
++	return;
++}
++
++/* Translate HAL auth bitmask to BRCM FW bitmask */
++void dhd_pno_set_epno_auth_flag(uint32 *wpa_auth)
++{
++	switch (*wpa_auth) {
++		case DHD_PNO_AUTH_CODE_OPEN:
++			*wpa_auth = WPA_AUTH_DISABLED;
++			break;
++		case DHD_PNO_AUTH_CODE_PSK:
++			*wpa_auth = (WPA_AUTH_PSK | WPA2_AUTH_PSK);
++			break;
++		case DHD_PNO_AUTH_CODE_EAPOL:
++			*wpa_auth = ~WPA_AUTH_NONE;
++			break;
++		default:
++			DHD_ERROR(("%s: Unknown auth %d", __FUNCTION__, *wpa_auth));
++			*wpa_auth = WPA_AUTH_PFN_ANY;
++			break;
++	}
++	return;
++}
++
++/* Cleanup all results */
++static void
++dhd_gscan_clear_all_batch_results(dhd_pub_t *dhd)
++{
++	struct dhd_pno_gscan_params *gscan_params;
++	dhd_pno_status_info_t *_pno_state;
++	gscan_results_cache_t *iter;
++
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	gscan_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS].params_gscan;
++	iter = gscan_params->gscan_batch_cache;
++	/* Mark everything as consumed */
++	while (iter) {
++		iter->tot_consumed = iter->tot_count;
++		iter = iter->next;
++	}
++	dhd_gscan_batch_cache_cleanup(dhd);
++	return;
++}
++
++static int
++_dhd_pno_gscan_cfg(dhd_pub_t *dhd, wl_pfn_gscan_cfg_t *pfncfg_gscan_param, int size)
++{
++	int err = BCME_OK;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	err = dhd_iovar(dhd, 0, "pfn_gscan_cfg", (char *)pfncfg_gscan_param, size, NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfncfg_gscan_param\n", __FUNCTION__));
++		goto exit;
++	}
++exit:
++	return err;
++}
++
++#ifdef GSCAN_SUPPORT
++static int
++_dhd_pno_flush_ssid(dhd_pub_t *dhd)
++{
++	int err;
++	wl_pfn_t pfn_elem;
++	memset(&pfn_elem, 0, sizeof(wl_pfn_t));
++	pfn_elem.flags = htod32(WL_PFN_FLUSH_ALL_SSIDS);
++	err = dhd_iovar(dhd, 0, "pfn_add", (char *)&pfn_elem, sizeof(wl_pfn_t), NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfn_add\n", __FUNCTION__));
++	}
++	return err;
++}
++#endif /* GSCAN_SUPPORT */
++
++static bool
++is_batch_retrieval_complete(struct dhd_pno_gscan_params *gscan_params)
++{
++	smp_rmb();
++	return (gscan_params->get_batch_flag == GSCAN_BATCH_RETRIEVAL_COMPLETE);
++}
++#endif /* GSCAN_SUPPORT */
++
++static int
++_dhd_pno_suspend(dhd_pub_t *dhd)
++{
++	int err;
++	int suspend = 1;
++	dhd_pno_status_info_t *_pno_state;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	err = dhd_iovar(dhd, 0, "pfn_suspend", (char *)&suspend, sizeof(suspend), NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to suspend pfn(error :%d)\n", __FUNCTION__, err));
++		goto exit;
++
++	}
++	_pno_state->pno_status = DHD_PNO_SUSPEND;
++exit:
++	return err;
++}
++static int
++_dhd_pno_enable(dhd_pub_t *dhd, int enable)
++{
++	int err = BCME_OK;
++	dhd_pno_status_info_t *_pno_state;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	if (enable & 0xfffe) {
++		DHD_ERROR(("%s invalid value\n", __FUNCTION__));
++		err = BCME_BADARG;
++		goto exit;
++	}
++	if (!dhd_support_sta_mode(dhd)) {
++		DHD_ERROR(("PNO is not allowed for non-STA mode"));
++		err = BCME_BADOPTION;
++		goto exit;
++	}
++	if (enable) {
++		if ((_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) &&
++			dhd_is_associated(dhd, 0, NULL)) {
++			DHD_ERROR(("%s Legacy PNO mode cannot be enabled "
++				"in assoc mode , ignore it\n", __FUNCTION__));
++			err = BCME_BADOPTION;
++			goto exit;
++		}
++	}
++	/* Enable/Disable PNO */
++	err = dhd_iovar(dhd, 0, "pfn", (char *)&enable, sizeof(enable), NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfn_set - %d\n", __FUNCTION__, err));
++		goto exit;
++	}
++	_pno_state->pno_status = (enable)?
++		DHD_PNO_ENABLED : DHD_PNO_DISABLED;
++	if (!enable)
++		_pno_state->pno_mode = DHD_PNO_NONE_MODE;
++
++	DHD_PNO(("%s set pno as %s\n",
++		__FUNCTION__, enable ? "Enable" : "Disable"));
++exit:
++	return err;
++}
++
++static int
++_dhd_pno_set(dhd_pub_t *dhd, const dhd_pno_params_t *pno_params, dhd_pno_mode_t mode)
++{
++	int err = BCME_OK;
++	wl_pfn_param_t pfn_param;
++	dhd_pno_params_t *_params;
++	dhd_pno_status_info_t *_pno_state;
++	bool combined_scan = FALSE;
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++
++	memset(&pfn_param, 0, sizeof(pfn_param));
++
++	/* set pfn parameters */
++	pfn_param.version = htod32(PFN_VERSION);
++	pfn_param.flags = ((PFN_LIST_ORDER << SORT_CRITERIA_BIT) |
++		(ENABLE << IMMEDIATE_SCAN_BIT) | (ENABLE << REPORT_SEPERATELY_BIT));
++	if (mode == DHD_PNO_LEGACY_MODE) {
++		/* check and set extra pno params */
++		if ((pno_params->params_legacy.pno_repeat != 0) ||
++			(pno_params->params_legacy.pno_freq_expo_max != 0)) {
++			pfn_param.flags |= htod16(ENABLE << ENABLE_ADAPTSCAN_BIT);
++			pfn_param.repeat = (uchar) (pno_params->params_legacy.pno_repeat);
++			pfn_param.exp = (uchar) (pno_params->params_legacy.pno_freq_expo_max);
++		}
++		/* set up pno scan fr */
++		if (pno_params->params_legacy.scan_fr != 0)
++			pfn_param.scan_freq = htod32(pno_params->params_legacy.scan_fr);
++		if (_pno_state->pno_mode & DHD_PNO_BATCH_MODE) {
++			DHD_PNO(("will enable combined scan with BATCHIG SCAN MODE\n"));
++			mode |= DHD_PNO_BATCH_MODE;
++			combined_scan = TRUE;
++		} else if (_pno_state->pno_mode & DHD_PNO_HOTLIST_MODE) {
++			DHD_PNO(("will enable combined scan with HOTLIST SCAN MODE\n"));
++			mode |= DHD_PNO_HOTLIST_MODE;
++			combined_scan = TRUE;
++		}
++#ifdef GSCAN_SUPPORT
++		else if (_pno_state->pno_mode & DHD_PNO_GSCAN_MODE) {
++			DHD_PNO(("will enable combined scan with GSCAN SCAN MODE\n"));
++			mode |= DHD_PNO_GSCAN_MODE;
++		}
++#endif /* GSCAN_SUPPORT */
++	}
++	if (mode & (DHD_PNO_BATCH_MODE | DHD_PNO_HOTLIST_MODE)) {
++		/* Scan frequency of 30 sec */
++		pfn_param.scan_freq = htod32(30);
++		/* slow adapt scan is off by default */
++		pfn_param.slow_freq = htod32(0);
++		/* RSSI margin of 30 dBm */
++		pfn_param.rssi_margin = htod16(PNO_RSSI_MARGIN_DBM);
++		/* Network timeout 60 sec */
++		pfn_param.lost_network_timeout = htod32(60);
++		/* best n = 2 by default */
++		pfn_param.bestn = DEFAULT_BESTN;
++		/* mscan m=0 by default, so not record best networks by default */
++		pfn_param.mscan = DEFAULT_MSCAN;
++		/*  default repeat = 10 */
++		pfn_param.repeat = DEFAULT_REPEAT;
++		/* by default, maximum scan interval = 2^2
++		 * scan_freq when adaptive scan is turned on
++		 */
++		pfn_param.exp = DEFAULT_EXP;
++		if (mode == DHD_PNO_BATCH_MODE) {
++			/* In case of BATCH SCAN */
++			if (pno_params->params_batch.bestn)
++				pfn_param.bestn = pno_params->params_batch.bestn;
++			if (pno_params->params_batch.scan_fr)
++				pfn_param.scan_freq = htod32(pno_params->params_batch.scan_fr);
++			if (pno_params->params_batch.mscan)
++				pfn_param.mscan = pno_params->params_batch.mscan;
++			/* enable broadcast scan */
++			pfn_param.flags |= (ENABLE << ENABLE_BD_SCAN_BIT);
++		} else if (mode == DHD_PNO_HOTLIST_MODE) {
++			/* In case of HOTLIST SCAN */
++			if (pno_params->params_hotlist.scan_fr)
++				pfn_param.scan_freq = htod32(pno_params->params_hotlist.scan_fr);
++			pfn_param.bestn = 0;
++			pfn_param.repeat = 0;
++			/* enable broadcast scan */
++			pfn_param.flags |= (ENABLE << ENABLE_BD_SCAN_BIT);
++		}
++		if (combined_scan) {
++			/* Disable Adaptive Scan */
++			pfn_param.flags &= ~(htod16(ENABLE << ENABLE_ADAPTSCAN_BIT));
++			pfn_param.flags |= (ENABLE << ENABLE_BD_SCAN_BIT);
++			pfn_param.repeat = 0;
++			pfn_param.exp = 0;
++			if (_pno_state->pno_mode & DHD_PNO_BATCH_MODE) {
++				/* In case of Legacy PNO + BATCH SCAN */
++				_params = &(_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS]);
++				if (_params->params_batch.bestn)
++					pfn_param.bestn = _params->params_batch.bestn;
++				if (_params->params_batch.scan_fr)
++					pfn_param.scan_freq = htod32(_params->params_batch.scan_fr);
++				if (_params->params_batch.mscan)
++					pfn_param.mscan = _params->params_batch.mscan;
++			} else if (_pno_state->pno_mode & DHD_PNO_HOTLIST_MODE) {
++				/* In case of Legacy PNO + HOTLIST SCAN */
++				_params = &(_pno_state->pno_params_arr[INDEX_OF_HOTLIST_PARAMS]);
++				if (_params->params_hotlist.scan_fr)
++				pfn_param.scan_freq = htod32(_params->params_hotlist.scan_fr);
++				pfn_param.bestn = 0;
++				pfn_param.repeat = 0;
++			}
++		}
++	}
++#ifdef GSCAN_SUPPORT
++	if (mode & DHD_PNO_GSCAN_MODE) {
++		uint32 lost_network_timeout;
++
++		pfn_param.scan_freq = htod32(pno_params->params_gscan.scan_fr);
++		if (pno_params->params_gscan.mscan) {
++			pfn_param.bestn = pno_params->params_gscan.bestn;
++			pfn_param.mscan =  pno_params->params_gscan.mscan;
++			pfn_param.flags |= (ENABLE << ENABLE_BD_SCAN_BIT);
++		}
++		/* RSSI margin of 30 dBm */
++		pfn_param.rssi_margin = htod16(PNO_RSSI_MARGIN_DBM);
++		pfn_param.repeat = 0;
++		pfn_param.exp = 0;
++		pfn_param.slow_freq = 0;
++		pfn_param.flags |= htod16(ENABLE << ENABLE_ADAPTSCAN_BIT);
++
++		if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) {
++			dhd_pno_params_t *params;
++
++			params = &(_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS]);
++
++			pfn_param.scan_freq = gcd(pno_params->params_gscan.scan_fr,
++			                 params->params_legacy.scan_fr);
++
++			if ((params->params_legacy.pno_repeat != 0) ||
++				(params->params_legacy.pno_freq_expo_max != 0)) {
++				pfn_param.repeat = (uchar) (params->params_legacy.pno_repeat);
++				pfn_param.exp = (uchar) (params->params_legacy.pno_freq_expo_max);
++			}
++		}
++
++		lost_network_timeout = (pno_params->params_gscan.max_ch_bucket_freq *
++		                        pfn_param.scan_freq *
++		                        pno_params->params_gscan.lost_ap_window);
++		if (lost_network_timeout) {
++			pfn_param.lost_network_timeout = htod32(MIN(lost_network_timeout,
++			                                 GSCAN_MIN_BSSID_TIMEOUT));
++		} else {
++			pfn_param.lost_network_timeout = htod32(GSCAN_MIN_BSSID_TIMEOUT);
++		}
++	} else
++#endif /* GSCAN_SUPPORT */
++	{
++		if (pfn_param.scan_freq < htod32(PNO_SCAN_MIN_FW_SEC) ||
++			pfn_param.scan_freq > htod32(PNO_SCAN_MAX_FW_SEC)) {
++			DHD_ERROR(("%s pno freq(%d sec) is not valid \n",
++				__FUNCTION__, PNO_SCAN_MIN_FW_SEC));
++			err = BCME_BADARG;
++			goto exit;
++		}
++	}
++
++	err = dhd_set_rand_mac_oui(dhd);
++	/* Ignore if chip doesnt support the feature */
++	if (err < 0 && err != BCME_UNSUPPORTED) {
++		DHD_ERROR(("%s : failed to set random mac for PNO scan, %d\n", __FUNCTION__, err));
++		goto exit;
++	}
++
++#ifdef GSCAN_SUPPORT
++	if (mode == DHD_PNO_BATCH_MODE ||
++		((mode & DHD_PNO_GSCAN_MODE) && pno_params->params_gscan.mscan))
++#else
++	if (mode == DHD_PNO_BATCH_MODE)
++#endif /* GSCAN_SUPPORT */
++	{
++		int _tmp = pfn_param.bestn;
++		/* set bestn to calculate the max mscan which firmware supports */
++		err = dhd_iovar(dhd, 0, "pfnmem", (char *)&_tmp, sizeof(_tmp), NULL, 0, TRUE);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to set pfnmem\n", __FUNCTION__));
++			goto exit;
++		}
++		/* get max mscan which the firmware supports */
++		err = dhd_iovar(dhd, 0, "pfnmem", NULL, 0, (char *)&_tmp, sizeof(_tmp), FALSE);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to get pfnmem\n", __FUNCTION__));
++			goto exit;
++		}
++		pfn_param.mscan = MIN(pfn_param.mscan, _tmp);
++		DHD_PNO((" returned mscan : %d, set bestn : %d mscan %d\n", _tmp, pfn_param.bestn,
++		        pfn_param.mscan));
++	}
++	err = dhd_iovar(dhd, 0, "pfn_set", (char *)&pfn_param, sizeof(pfn_param), NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfn_set %d\n", __FUNCTION__, err));
++		goto exit;
++	}
++	/* need to return mscan if this is for batch scan instead of err */
++	err = (mode == DHD_PNO_BATCH_MODE)? pfn_param.mscan : err;
++exit:
++	return err;
++}
++
++static int
++_dhd_pno_add_ssid(dhd_pub_t *dhd, struct list_head *ssid_list, int nssid)
++{
++	int err = BCME_OK;
++	int i = 0, mem_needed;
++	wl_pfn_t *pfn_elem_buf;
++	struct dhd_pno_ssid *iter, *next;
++
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	if (!nssid) {
++		NULL_CHECK(ssid_list, "ssid list is NULL", err);
++		return BCME_ERROR;
++	}
++	mem_needed = (sizeof(wl_pfn_t) * nssid);
++	pfn_elem_buf = (wl_pfn_t *) kzalloc(mem_needed, GFP_KERNEL);
++	if (!pfn_elem_buf) {
++		DHD_ERROR(("%s: Can't malloc %d bytes!\n", __FUNCTION__, mem_needed));
++		return BCME_NOMEM;
++	}
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	list_for_each_entry_safe(iter, next, ssid_list, list) {
++		pfn_elem_buf[i].infra = htod32(1);
++		pfn_elem_buf[i].auth = htod32(DOT11_OPEN_SYSTEM);
++		pfn_elem_buf[i].wpa_auth = htod32(iter->wpa_auth);
++		pfn_elem_buf[i].flags = htod32(iter->flags);
++		if (iter->hidden)
++			pfn_elem_buf[i].flags |= htod32(ENABLE << WL_PFN_HIDDEN_BIT);
++		/* If a single RSSI threshold is defined, use that */
++#ifdef PNO_MIN_RSSI_TRIGGER
++		pfn_elem_buf[i].flags |= ((PNO_MIN_RSSI_TRIGGER & 0xFF) << WL_PFN_RSSI_SHIFT);
++#else
++		pfn_elem_buf[i].flags |= ((iter->rssi_thresh & 0xFF) << WL_PFN_RSSI_SHIFT);
++#endif /* PNO_MIN_RSSI_TRIGGER */
++		memcpy((char *)pfn_elem_buf[i].ssid.SSID, iter->SSID,
++			iter->SSID_len);
++		pfn_elem_buf[i].ssid.SSID_len = iter->SSID_len;
++		DHD_PNO(("%s size = %d hidden = %d flags = %x rssi_thresh %d\n",
++			iter->SSID, iter->SSID_len, iter->hidden,
++			iter->flags, iter->rssi_thresh));
++		if (++i >= nssid) {
++			/* shouldn't happen */
++			break;
++		}
++	}
++	err = dhd_iovar(dhd, 0, "pfn_add", (char *)pfn_elem_buf, mem_needed, NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfn_add\n", __FUNCTION__));
++	}
++	kfree(pfn_elem_buf);
++	return err;
++}
++
++/* qsort compare function */
++static int
++_dhd_pno_cmpfunc(const void *a, const void *b)
++{
++	return (*(const uint16*)a - *(const uint16*)b);
++}
++
++static int
++_dhd_pno_chan_merge(uint16 *d_chan_list, int *nchan,
++	uint16 *chan_list1, int nchan1, uint16 *chan_list2, int nchan2)
++{
++	int err = BCME_OK;
++	int i = 0, j = 0, k = 0;
++	uint16 tmp;
++	NULL_CHECK(d_chan_list, "d_chan_list is NULL", err);
++	NULL_CHECK(nchan, "nchan is NULL", err);
++	NULL_CHECK(chan_list1, "chan_list1 is NULL", err);
++	NULL_CHECK(chan_list2, "chan_list2 is NULL", err);
++	/* chan_list1 and chan_list2 should be sorted at first */
++	while (i < nchan1 && j < nchan2) {
++		tmp = chan_list1[i] < chan_list2[j]?
++			chan_list1[i++] : chan_list2[j++];
++		for (; i < nchan1 && chan_list1[i] == tmp; i++);
++		for (; j < nchan2 && chan_list2[j] == tmp; j++);
++		d_chan_list[k++] = tmp;
++	}
++
++	while (i < nchan1) {
++		tmp = chan_list1[i++];
++		for (; i < nchan1 && chan_list1[i] == tmp; i++);
++		d_chan_list[k++] = tmp;
++	}
++
++	while (j < nchan2) {
++		tmp = chan_list2[j++];
++		for (; j < nchan2 && chan_list2[j] == tmp; j++);
++		d_chan_list[k++] = tmp;
++
++	}
++	*nchan = k;
++	return err;
++}
++
++static int
++_dhd_pno_get_channels(dhd_pub_t *dhd, uint16 *d_chan_list,
++	int *nchan, uint8 band, bool skip_dfs)
++{
++	int err = BCME_OK;
++	int i, j;
++	uint32 chan_buf[WL_NUMCHANNELS + 1];
++	wl_uint32_list_t *list;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	if (*nchan) {
++		NULL_CHECK(d_chan_list, "d_chan_list is NULL", err);
++	}
++	memset(&chan_buf, 0, sizeof(chan_buf));
++	list = (wl_uint32_list_t *) (void *)chan_buf;
++	list->count = htod32(WL_NUMCHANNELS);
++	err = dhd_wl_ioctl_cmd(dhd, WLC_GET_VALID_CHANNELS, chan_buf, sizeof(chan_buf), FALSE, 0);
++	if (err < 0) {
++		DHD_ERROR(("failed to get channel list (err: %d)\n", err));
++		goto exit;
++	}
++	for (i = 0, j = 0; i < dtoh32(list->count) && i < *nchan; i++) {
++		if (band == WLC_BAND_2G) {
++			if (dtoh32(list->element[i]) > CHANNEL_2G_MAX)
++				continue;
++		} else if (band == WLC_BAND_5G) {
++			if (dtoh32(list->element[i]) <= CHANNEL_2G_MAX)
++				continue;
++			if (skip_dfs && is_dfs(dtoh32(list->element[i])))
++				continue;
++
++		} else if (band == WLC_BAND_AUTO) {
++			if (skip_dfs || !is_dfs(dtoh32(list->element[i])))
++				continue;
++
++		} else { /* All channels */
++			if (skip_dfs && is_dfs(dtoh32(list->element[i])))
++				continue;
++		}
++		if (dtoh32(list->element[i]) <= CHANNEL_5G_MAX) {
++			d_chan_list[j++] = (uint16) dtoh32(list->element[i]);
++		} else {
++			err = BCME_BADCHAN;
++			goto exit;
++		}
++	}
++	*nchan = j;
++exit:
++	return err;
++}
++
++static int
++_dhd_pno_convert_format(dhd_pub_t *dhd, struct dhd_pno_batch_params *params_batch,
++	char *buf, int nbufsize)
++{
++	int err = BCME_OK;
++	int bytes_written = 0, nreadsize = 0;
++	int t_delta = 0;
++	int nleftsize = nbufsize;
++	uint8 cnt = 0;
++	char *bp = buf;
++	char eabuf[ETHER_ADDR_STR_LEN];
++#ifdef PNO_DEBUG
++	char *_base_bp;
++	char msg[150];
++#endif
++	dhd_pno_bestnet_entry_t *iter, *next;
++	dhd_pno_scan_results_t *siter, *snext;
++	dhd_pno_best_header_t *phead, *pprev;
++	NULL_CHECK(params_batch, "params_batch is NULL", err);
++	if (nbufsize > 0)
++		NULL_CHECK(buf, "buf is NULL", err);
++	/* initialize the buffer */
++	memset(buf, 0, nbufsize);
++	DHD_PNO(("%s enter \n", __FUNCTION__));
++	/* # of scans */
++	if (!params_batch->get_batch.batch_started) {
++		bp += nreadsize = snprintf(bp, nleftsize, "scancount=%d\n",
++			params_batch->get_batch.expired_tot_scan_cnt);
++		nleftsize -= nreadsize;
++		params_batch->get_batch.batch_started = TRUE;
++	}
++	DHD_PNO(("%s scancount %d\n", __FUNCTION__, params_batch->get_batch.expired_tot_scan_cnt));
++	/* preestimate scan count until which scan result this report is going to end */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	list_for_each_entry_safe(siter, snext,
++		&params_batch->get_batch.expired_scan_results_list, list) {
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++		phead = siter->bestnetheader;
++		while (phead != NULL) {
++			/* if left_size is less than bestheader total size , stop this */
++			if (nleftsize <=
++				(phead->tot_size + phead->tot_cnt * ENTRY_OVERHEAD))
++				goto exit;
++			/* increase scan count */
++			cnt++;
++			/* # best of each scan */
++			DHD_PNO(("\n<loop : %d, apcount %d>\n", cnt - 1, phead->tot_cnt));
++			/* attribute of the scan */
++			if (phead->reason & PNO_STATUS_ABORT_MASK) {
++				bp += nreadsize = snprintf(bp, nleftsize, "trunc\n");
++				nleftsize -= nreadsize;
++			}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++			list_for_each_entry_safe(iter, next,
++				&phead->entry_list, list) {
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++				t_delta = jiffies_to_msecs(jiffies - iter->recorded_time);
++#ifdef PNO_DEBUG
++				_base_bp = bp;
++				memset(msg, 0, sizeof(msg));
++#endif
++				/* BSSID info */
++				bp += nreadsize = snprintf(bp, nleftsize, "bssid=%s\n",
++				bcm_ether_ntoa((const struct ether_addr *)&iter->BSSID, eabuf));
++				nleftsize -= nreadsize;
++				/* SSID */
++				bp += nreadsize = snprintf(bp, nleftsize, "ssid=%s\n", iter->SSID);
++				nleftsize -= nreadsize;
++				/* channel */
++				bp += nreadsize = snprintf(bp, nleftsize, "freq=%d\n",
++				wf_channel2mhz(iter->channel,
++				iter->channel <= CH_MAX_2G_CHANNEL?
++				WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G));
++				nleftsize -= nreadsize;
++				/* RSSI */
++				bp += nreadsize = snprintf(bp, nleftsize, "level=%d\n", iter->RSSI);
++				nleftsize -= nreadsize;
++				/* add the time consumed in Driver to the timestamp of firmware */
++				iter->timestamp += t_delta;
++				bp += nreadsize = snprintf(bp, nleftsize,
++					"age=%d\n", iter->timestamp);
++				nleftsize -= nreadsize;
++				/* RTT0 */
++				bp += nreadsize = snprintf(bp, nleftsize, "dist=%d\n",
++				(iter->rtt0 == 0)? -1 : iter->rtt0);
++				nleftsize -= nreadsize;
++				/* RTT1 */
++				bp += nreadsize = snprintf(bp, nleftsize, "distSd=%d\n",
++				(iter->rtt0 == 0)? -1 : iter->rtt1);
++				nleftsize -= nreadsize;
++				bp += nreadsize = snprintf(bp, nleftsize, "%s", AP_END_MARKER);
++				nleftsize -= nreadsize;
++				list_del(&iter->list);
++				MFREE(dhd->osh, iter, BESTNET_ENTRY_SIZE);
++#ifdef PNO_DEBUG
++				memcpy(msg, _base_bp, bp - _base_bp);
++				DHD_PNO(("Entry : \n%s", msg));
++#endif
++			}
++			bp += nreadsize = snprintf(bp, nleftsize, "%s", SCAN_END_MARKER);
++			DHD_PNO(("%s", SCAN_END_MARKER));
++			nleftsize -= nreadsize;
++			pprev = phead;
++			/* reset the header */
++			siter->bestnetheader = phead = phead->next;
++			MFREE(dhd->osh, pprev, BEST_HEADER_SIZE);
++
++			siter->cnt_header--;
++		}
++		if (phead == NULL) {
++			/* we store all entry in this scan , so it is ok to delete */
++			list_del(&siter->list);
++			MFREE(dhd->osh, siter, SCAN_RESULTS_SIZE);
++		}
++	}
++exit:
++	if (cnt < params_batch->get_batch.expired_tot_scan_cnt) {
++		DHD_ERROR(("Buffer size is small to save all batch entry,"
++			" cnt : %d (remained_scan_cnt): %d\n",
++			cnt, params_batch->get_batch.expired_tot_scan_cnt - cnt));
++	}
++	params_batch->get_batch.expired_tot_scan_cnt -= cnt;
++	/* set FALSE only if the link list  is empty after returning the data */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	if (list_empty(&params_batch->get_batch.expired_scan_results_list)) {
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++		params_batch->get_batch.batch_started = FALSE;
++		bp += snprintf(bp, nleftsize, "%s", RESULTS_END_MARKER);
++		DHD_PNO(("%s", RESULTS_END_MARKER));
++		DHD_PNO(("%s : Getting the batching data is complete\n", __FUNCTION__));
++	}
++	/* return used memory in buffer */
++	bytes_written = (int32)(bp - buf);
++	return bytes_written;
++}
++
++static int
++_dhd_pno_clear_all_batch_results(dhd_pub_t *dhd, struct list_head *head, bool only_last)
++{
++	int err = BCME_OK;
++	int removed_scan_cnt = 0;
++	dhd_pno_scan_results_t *siter, *snext;
++	dhd_pno_best_header_t *phead, *pprev;
++	dhd_pno_bestnet_entry_t *iter, *next;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(head, "head is NULL", err);
++	NULL_CHECK(head->next, "head->next is NULL", err);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	list_for_each_entry_safe(siter, snext,
++		head, list) {
++		if (only_last) {
++			/* in case that we need to delete only last one */
++			if (!list_is_last(&siter->list, head)) {
++				/* skip if the one is not last */
++				continue;
++			}
++		}
++		/* delete all data belong if the one is last */
++		phead = siter->bestnetheader;
++		while (phead != NULL) {
++			removed_scan_cnt++;
++			list_for_each_entry_safe(iter, next,
++			&phead->entry_list, list) {
++				list_del(&iter->list);
++				MFREE(dhd->osh, iter, BESTNET_ENTRY_SIZE);
++			}
++			pprev = phead;
++			phead = phead->next;
++			MFREE(dhd->osh, pprev, BEST_HEADER_SIZE);
++		}
++		if (phead == NULL) {
++			/* it is ok to delete top node */
++			list_del(&siter->list);
++			MFREE(dhd->osh, siter, SCAN_RESULTS_SIZE);
++		}
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	return removed_scan_cnt;
++}
++
++static int
++_dhd_pno_cfg(dhd_pub_t *dhd, uint16 *channel_list, int nchan)
++{
++	int err = BCME_OK;
++	int i = 0;
++	wl_pfn_cfg_t pfncfg_param;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	if (nchan) {
++		NULL_CHECK(channel_list, "nchan is NULL", err);
++	}
++	if (nchan > WL_NUMCHANNELS) {
++		return BCME_RANGE;
++	}
++	DHD_PNO(("%s enter :  nchan : %d\n", __FUNCTION__, nchan));
++	memset(&pfncfg_param, 0, sizeof(wl_pfn_cfg_t));
++	/* Setup default values */
++	pfncfg_param.reporttype = htod32(WL_PFN_REPORT_ALLNET);
++	pfncfg_param.channel_num = htod32(0);
++
++	for (i = 0; i < nchan; i++)
++		pfncfg_param.channel_list[i] = channel_list[i];
++
++	pfncfg_param.channel_num = htod32(nchan);
++	err = dhd_iovar(dhd, 0, "pfn_cfg", (char *)&pfncfg_param, sizeof(pfncfg_param), NULL, 0,
++			TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfn_cfg\n", __FUNCTION__));
++		goto exit;
++	}
++exit:
++	return err;
++}
++
++static int
++_dhd_pno_reinitialize_prof(dhd_pub_t *dhd, dhd_pno_params_t *params, dhd_pno_mode_t mode)
++{
++	int err = BCME_OK;
++	dhd_pno_status_info_t *_pno_state;
++	NULL_CHECK(dhd, "dhd is NULL\n", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL\n", err);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	mutex_lock(&_pno_state->pno_mutex);
++	switch (mode) {
++	case DHD_PNO_LEGACY_MODE: {
++		struct dhd_pno_ssid *iter, *next;
++		if (params->params_legacy.nssid > 0) {
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++			list_for_each_entry_safe(iter, next,
++				&params->params_legacy.ssid_list, list) {
++				list_del(&iter->list);
++				kfree(iter);
++			}
++		}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++		params->params_legacy.nssid = 0;
++		params->params_legacy.scan_fr = 0;
++		params->params_legacy.pno_freq_expo_max = 0;
++		params->params_legacy.pno_repeat = 0;
++		params->params_legacy.nchan = 0;
++		memset(params->params_legacy.chan_list, 0,
++			sizeof(params->params_legacy.chan_list));
++		break;
++	}
++	case DHD_PNO_BATCH_MODE: {
++		params->params_batch.scan_fr = 0;
++		params->params_batch.mscan = 0;
++		params->params_batch.nchan = 0;
++		params->params_batch.rtt = 0;
++		params->params_batch.bestn = 0;
++		params->params_batch.nchan = 0;
++		params->params_batch.band = WLC_BAND_AUTO;
++		memset(params->params_batch.chan_list, 0,
++			sizeof(params->params_batch.chan_list));
++		params->params_batch.get_batch.batch_started = FALSE;
++		params->params_batch.get_batch.buf = NULL;
++		params->params_batch.get_batch.bufsize = 0;
++		params->params_batch.get_batch.reason = 0;
++		_dhd_pno_clear_all_batch_results(dhd,
++			&params->params_batch.get_batch.scan_results_list, FALSE);
++		_dhd_pno_clear_all_batch_results(dhd,
++			&params->params_batch.get_batch.expired_scan_results_list, FALSE);
++		params->params_batch.get_batch.tot_scan_cnt = 0;
++		params->params_batch.get_batch.expired_tot_scan_cnt = 0;
++		params->params_batch.get_batch.top_node_cnt = 0;
++		INIT_LIST_HEAD(&params->params_batch.get_batch.scan_results_list);
++		INIT_LIST_HEAD(&params->params_batch.get_batch.expired_scan_results_list);
++		break;
++	}
++	case DHD_PNO_HOTLIST_MODE: {
++		struct dhd_pno_bssid *iter, *next;
++		if (params->params_hotlist.nbssid > 0) {
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++			list_for_each_entry_safe(iter, next,
++				&params->params_hotlist.bssid_list, list) {
++				list_del(&iter->list);
++				kfree(iter);
++			}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++		}
++		params->params_hotlist.scan_fr = 0;
++		params->params_hotlist.nbssid = 0;
++		params->params_hotlist.nchan = 0;
++		params->params_batch.band = WLC_BAND_AUTO;
++		memset(params->params_hotlist.chan_list, 0,
++			sizeof(params->params_hotlist.chan_list));
++		break;
++	}
++	default:
++		DHD_ERROR(("%s : unknown mode : %d\n", __FUNCTION__, mode));
++		break;
++	}
++	mutex_unlock(&_pno_state->pno_mutex);
++	return err;
++}
++
++static int
++_dhd_pno_add_bssid(dhd_pub_t *dhd, wl_pfn_bssid_t *p_pfn_bssid, int nbssid)
++{
++	int err = BCME_OK;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	if (nbssid) {
++		NULL_CHECK(p_pfn_bssid, "bssid list is NULL", err);
++	}
++	err = dhd_iovar(dhd, 0, "pfn_add_bssid", (char *)p_pfn_bssid,
++			sizeof(wl_pfn_bssid_t) * nbssid, NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfn_cfg\n", __FUNCTION__));
++		goto exit;
++	}
++exit:
++	return err;
++}
++
++int
++dhd_pno_stop_for_ssid(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	uint32 mode = 0;
++	dhd_pno_status_info_t *_pno_state;
++	dhd_pno_params_t *_params;
++	wl_pfn_bssid_t *p_pfn_bssid = NULL;
++	NULL_CHECK(dhd, "dev is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	if (!(_pno_state->pno_mode & DHD_PNO_LEGACY_MODE)) {
++		DHD_ERROR(("%s : LEGACY PNO MODE is not enabled\n", __FUNCTION__));
++		goto exit;
++	}
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	_pno_state->pno_mode &= ~DHD_PNO_LEGACY_MODE;
++#ifdef GSCAN_SUPPORT
++	if (_pno_state->pno_mode & DHD_PNO_GSCAN_MODE) {
++		struct dhd_pno_gscan_params *gscan_params;
++
++		_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++		gscan_params = &_params->params_gscan;
++		if (gscan_params->mscan) {
++			/* retrieve the batching data from firmware into host */
++			err = dhd_wait_batch_results_complete(dhd);
++			if (err != BCME_OK)
++				goto exit;
++		}
++		/* save current pno_mode before calling dhd_pno_clean */
++		mutex_lock(&_pno_state->pno_mutex);
++		mode = _pno_state->pno_mode;
++		err = dhd_pno_clean(dhd);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++				__FUNCTION__, err));
++			mutex_unlock(&_pno_state->pno_mutex);
++			goto exit;
++		}
++		/* restore previous pno_mode */
++		_pno_state->pno_mode = mode;
++		mutex_unlock(&_pno_state->pno_mutex);
++		/* Restart gscan */
++		err = dhd_pno_initiate_gscan_request(dhd, 1, 0);
++		goto exit;
++	}
++#endif /* GSCAN_SUPPORT */
++	/* restart Batch mode  if the batch mode is on */
++	if (_pno_state->pno_mode & (DHD_PNO_BATCH_MODE | DHD_PNO_HOTLIST_MODE)) {
++		/* retrieve the batching data from firmware into host */
++		dhd_pno_get_for_batch(dhd, NULL, 0, PNO_STATUS_DISABLE);
++		/* save current pno_mode before calling dhd_pno_clean */
++		mode = _pno_state->pno_mode;
++		err = dhd_pno_clean(dhd);
++		if (err < 0) {
++			err = BCME_ERROR;
++			DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++
++		/* restore previous pno_mode */
++		_pno_state->pno_mode = mode;
++		if (_pno_state->pno_mode & DHD_PNO_BATCH_MODE) {
++			_params = &(_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS]);
++			/* restart BATCH SCAN */
++			err = dhd_pno_set_for_batch(dhd, &_params->params_batch);
++			if (err < 0) {
++				_pno_state->pno_mode &= ~DHD_PNO_BATCH_MODE;
++				DHD_ERROR(("%s : failed to restart batch scan(err: %d)\n",
++					__FUNCTION__, err));
++				goto exit;
++			}
++		} else if (_pno_state->pno_mode & DHD_PNO_HOTLIST_MODE) {
++			/* restart HOTLIST SCAN */
++			struct dhd_pno_bssid *iter, *next;
++			_params = &(_pno_state->pno_params_arr[INDEX_OF_HOTLIST_PARAMS]);
++			p_pfn_bssid = kzalloc(sizeof(wl_pfn_bssid_t) *
++			_params->params_hotlist.nbssid, GFP_KERNEL);
++			if (p_pfn_bssid == NULL) {
++				DHD_ERROR(("%s : failed to allocate wl_pfn_bssid_t array"
++				" (count: %d)",
++					__FUNCTION__, _params->params_hotlist.nbssid));
++				err = BCME_ERROR;
++				_pno_state->pno_mode &= ~DHD_PNO_HOTLIST_MODE;
++				goto exit;
++			}
++			/* convert dhd_pno_bssid to wl_pfn_bssid */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++			list_for_each_entry_safe(iter, next,
++			&_params->params_hotlist.bssid_list, list) {
++				memcpy(&p_pfn_bssid->macaddr,
++				&iter->macaddr, ETHER_ADDR_LEN);
++				p_pfn_bssid->flags = iter->flags;
++				p_pfn_bssid++;
++			}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++			err = dhd_pno_set_for_hotlist(dhd, p_pfn_bssid, &_params->params_hotlist);
++			if (err < 0) {
++				_pno_state->pno_mode &= ~DHD_PNO_HOTLIST_MODE;
++				DHD_ERROR(("%s : failed to restart hotlist scan(err: %d)\n",
++					__FUNCTION__, err));
++				goto exit;
++			}
++		}
++	} else {
++		err = dhd_pno_clean(dhd);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++	}
++exit:
++	kfree(p_pfn_bssid);
++	return err;
++}
++
++int
++dhd_pno_enable(dhd_pub_t *dhd, int enable)
++{
++	int err = BCME_OK;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	return (_dhd_pno_enable(dhd, enable));
++}
++
++static int
++dhd_pno_add_to_ssid_list(struct list_head *ptr, wlc_ssid_ext_t *ssid_list,
++    int nssid, int *num_ssid_added)
++{
++	int ret = BCME_OK;
++	int i;
++	struct dhd_pno_ssid *_pno_ssid;
++
++	for (i = 0; i < nssid; i++) {
++		if (ssid_list[i].SSID_len > DOT11_MAX_SSID_LEN) {
++			DHD_ERROR(("%s : Invalid SSID length %d\n",
++				__FUNCTION__, ssid_list[i].SSID_len));
++			ret = BCME_ERROR;
++			goto exit;
++		}
++		/* Check for broadcast ssid */
++		if (!ssid_list[i].SSID_len) {
++			DHD_ERROR(("%d: Broadcast SSID is illegal for PNO setting\n", i));
++			ret = BCME_ERROR;
++			goto exit;
++		}
++
++		_pno_ssid = kzalloc(sizeof(struct dhd_pno_ssid), GFP_KERNEL);
++		if (_pno_ssid == NULL) {
++			DHD_ERROR(("%s : failed to allocate struct dhd_pno_ssid\n",
++				__FUNCTION__));
++			ret = BCME_ERROR;
++			goto exit;
++		}
++		_pno_ssid->SSID_len = ssid_list[i].SSID_len;
++		_pno_ssid->hidden = ssid_list[i].hidden;
++		_pno_ssid->rssi_thresh = ssid_list[i].rssi_thresh;
++		_pno_ssid->flags = ssid_list[i].flags;
++		_pno_ssid->wpa_auth = WPA_AUTH_PFN_ANY;
++
++		memcpy(_pno_ssid->SSID, ssid_list[i].SSID, _pno_ssid->SSID_len);
++		list_add_tail(&_pno_ssid->list, ptr);
++	}
++
++exit:
++	*num_ssid_added = i;
++	return ret;
++}
++
++int
++dhd_pno_set_for_ssid(dhd_pub_t *dhd, wlc_ssid_ext_t* ssid_list, int nssid,
++	uint16  scan_fr, int pno_repeat, int pno_freq_expo_max, uint16 *channel_list, int nchan)
++{
++
++	dhd_pno_status_info_t *_pno_state;
++	dhd_pno_params_t *_params;
++	struct dhd_pno_legacy_params *params_legacy;
++	int err = BCME_OK;
++
++	if (!dhd || !dhd->pno_state) {
++		DHD_ERROR(("%s: PNO Not enabled/Not ready\n", __FUNCTION__));
++		return BCME_NOTREADY;
++	}
++
++	if (!dhd_support_sta_mode(dhd)) {
++		return BCME_BADOPTION;
++	}
++
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	_params = &(_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS]);
++	params_legacy = &(_params->params_legacy);
++	err = _dhd_pno_reinitialize_prof(dhd, _params, DHD_PNO_LEGACY_MODE);
++
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to reinitialize profile (err %d)\n",
++			__FUNCTION__, err));
++		return err;
++	}
++
++	INIT_LIST_HEAD(&params_legacy->ssid_list);
++
++	if (dhd_pno_add_to_ssid_list(&params_legacy->ssid_list, ssid_list,
++	      nssid, &params_legacy->nssid) < 0) {
++		_dhd_pno_reinitialize_prof(dhd, _params, DHD_PNO_LEGACY_MODE);
++		return BCME_ERROR;
++	}
++
++	DHD_PNO(("%s enter : nssid %d, scan_fr :%d, pno_repeat :%d,"
++			"pno_freq_expo_max: %d, nchan :%d\n", __FUNCTION__,
++			params_legacy->nssid, scan_fr, pno_repeat, pno_freq_expo_max, nchan));
++
++	return dhd_pno_set_legacy_pno(dhd, scan_fr, pno_repeat,
++	     pno_freq_expo_max, channel_list, nchan);
++
++}
++
++static int
++dhd_pno_set_legacy_pno(dhd_pub_t *dhd, uint16  scan_fr, int pno_repeat,
++	int pno_freq_expo_max, uint16 *channel_list, int nchan)
++{
++	dhd_pno_params_t *_params;
++	dhd_pno_params_t *_params2;
++	dhd_pno_status_info_t *_pno_state;
++	uint16 _chan_list[WL_NUMCHANNELS];
++	int32 tot_nchan = 0;
++	int err = BCME_OK;
++	int i, nssid;
++	int mode = 0;
++	struct list_head *ssid_list;
++
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	_params = &(_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS]);
++	/* If GSCAN is also ON will handle this down below */
++#ifdef GSCAN_SUPPORT
++	if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE &&
++		!(_pno_state->pno_mode & DHD_PNO_GSCAN_MODE))
++#else
++	if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE)
++#endif /* GSCAN_SUPPORT */
++	{
++		DHD_ERROR(("%s : Legacy PNO mode was already started, "
++			"will disable previous one to start new one\n", __FUNCTION__));
++		err = dhd_pno_stop_for_ssid(dhd);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to stop legacy PNO (err %d)\n",
++				__FUNCTION__, err));
++			return err;
++		}
++	}
++	_pno_state->pno_mode |= DHD_PNO_LEGACY_MODE;
++	memset(_chan_list, 0, sizeof(_chan_list));
++	tot_nchan = MIN(nchan, WL_NUMCHANNELS);
++	if (tot_nchan > 0 && channel_list) {
++		for (i = 0; i < tot_nchan; i++)
++		_params->params_legacy.chan_list[i] = _chan_list[i] = channel_list[i];
++	}
++#ifdef GSCAN_SUPPORT
++	else {
++		tot_nchan = WL_NUMCHANNELS;
++		err = _dhd_pno_get_channels(dhd, _chan_list, &tot_nchan,
++				(WLC_BAND_2G | WLC_BAND_5G), FALSE);
++		if (err < 0) {
++			tot_nchan = 0;
++			DHD_PNO(("Could not get channel list for PNO SSID\n"));
++		} else {
++			for (i = 0; i < tot_nchan; i++)
++			_params->params_legacy.chan_list[i] = _chan_list[i];
++		}
++	}
++#endif /* GSCAN_SUPPORT */
++
++	if (_pno_state->pno_mode & (DHD_PNO_BATCH_MODE | DHD_PNO_HOTLIST_MODE)) {
++		DHD_PNO(("BATCH SCAN is on progress in firmware\n"));
++		/* retrieve the batching data from firmware into host */
++		dhd_pno_get_for_batch(dhd, NULL, 0, PNO_STATUS_DISABLE);
++		/* store current pno_mode before disabling pno */
++		mode = _pno_state->pno_mode;
++		err = _dhd_pno_enable(dhd, PNO_OFF);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to disable PNO\n", __FUNCTION__));
++			goto exit;
++		}
++		/* restore the previous mode */
++		_pno_state->pno_mode = mode;
++		/* use superset of channel list between two mode */
++		if (_pno_state->pno_mode & DHD_PNO_BATCH_MODE) {
++			_params2 = &(_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS]);
++			if (_params2->params_batch.nchan > 0 && tot_nchan > 0) {
++				err = _dhd_pno_chan_merge(_chan_list, &tot_nchan,
++					&_params2->params_batch.chan_list[0],
++					_params2->params_batch.nchan,
++					&channel_list[0], tot_nchan);
++				if (err < 0) {
++					DHD_ERROR(("%s : failed to merge channel list"
++					" between legacy and batch\n",
++						__FUNCTION__));
++					goto exit;
++				}
++			}  else {
++				DHD_PNO(("superset channel will use"
++				" all channels in firmware\n"));
++			}
++		} else if (_pno_state->pno_mode & DHD_PNO_HOTLIST_MODE) {
++			_params2 = &(_pno_state->pno_params_arr[INDEX_OF_HOTLIST_PARAMS]);
++			if (_params2->params_hotlist.nchan > 0 && tot_nchan > 0) {
++				err = _dhd_pno_chan_merge(_chan_list, &tot_nchan,
++					&_params2->params_hotlist.chan_list[0],
++					_params2->params_hotlist.nchan,
++					&channel_list[0], tot_nchan);
++				if (err < 0) {
++					DHD_ERROR(("%s : failed to merge channel list"
++					" between legacy and hotlist\n",
++						__FUNCTION__));
++					goto exit;
++				}
++			}
++		}
++	}
++	_params->params_legacy.scan_fr = scan_fr;
++	_params->params_legacy.pno_repeat = pno_repeat;
++	_params->params_legacy.pno_freq_expo_max = pno_freq_expo_max;
++	_params->params_legacy.nchan = tot_nchan;
++	ssid_list = &_params->params_legacy.ssid_list;
++	nssid = _params->params_legacy.nssid;
++
++#ifdef GSCAN_SUPPORT
++	/* dhd_pno_initiate_gscan_request will handle simultaneous Legacy PNO and GSCAN */
++	if (_pno_state->pno_mode & DHD_PNO_GSCAN_MODE) {
++		struct dhd_pno_gscan_params *gscan_params;
++		gscan_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS].params_gscan;
++		/* ePNO and Legacy PNO do not co-exist */
++		if (gscan_params->epno_cfg.num_epno_ssid) {
++			DHD_PNO(("ePNO and Legacy PNO do not co-exist\n"));
++			err = BCME_EPERM;
++			goto exit;
++		}
++		DHD_PNO(("GSCAN mode is ON! Will restart GSCAN+Legacy PNO\n"));
++		err = dhd_pno_initiate_gscan_request(dhd, 1, 0);
++		goto exit;
++	}
++#endif /* GSCAN_SUPPORT */
++	if ((err = _dhd_pno_set(dhd, _params, DHD_PNO_LEGACY_MODE)) < 0) {
++		DHD_ERROR(("failed to set call pno_set (err %d) in firmware\n", err));
++		goto exit;
++	}
++	if ((err = _dhd_pno_add_ssid(dhd, ssid_list, nssid)) < 0) {
++		DHD_ERROR(("failed to add ssid list(err %d), %d in firmware\n", err, nssid));
++		goto exit;
++	}
++	if (tot_nchan > 0) {
++		if ((err = _dhd_pno_cfg(dhd, _chan_list, tot_nchan)) < 0) {
++			DHD_ERROR(("%s : failed to set call pno_cfg (err %d) in firmware\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++	}
++	if (_pno_state->pno_status == DHD_PNO_DISABLED) {
++		if ((err = _dhd_pno_enable(dhd, PNO_ON)) < 0)
++			DHD_ERROR(("%s : failed to enable PNO\n", __FUNCTION__));
++	}
++exit:
++	if (err < 0) {
++		_dhd_pno_reinitialize_prof(dhd, _params, DHD_PNO_LEGACY_MODE);
++	}
++	/* clear mode in case of error */
++	if (err < 0) {
++		int ret = dhd_pno_clean(dhd);
++
++		if (ret < 0) {
++			DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++				__FUNCTION__, ret));
++		} else {
++			_pno_state->pno_mode &= ~DHD_PNO_LEGACY_MODE;
++		}
++	}
++	return err;
++}
++
++int
++dhd_pno_set_for_batch(dhd_pub_t *dhd, struct dhd_pno_batch_params *batch_params)
++{
++	int err = BCME_OK;
++	uint16 _chan_list[WL_NUMCHANNELS];
++	int rem_nchan = 0, tot_nchan = 0;
++	int mode = 0, mscan = 0;
++	dhd_pno_params_t *_params;
++	dhd_pno_params_t *_params2;
++	dhd_pno_status_info_t *_pno_state;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	NULL_CHECK(batch_params, "batch_params is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	if (!dhd_support_sta_mode(dhd)) {
++		err = BCME_BADOPTION;
++		goto exit;
++	}
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n", __FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++	_params = &_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS];
++	if (!(_pno_state->pno_mode & DHD_PNO_BATCH_MODE)) {
++		_pno_state->pno_mode |= DHD_PNO_BATCH_MODE;
++		err = _dhd_pno_reinitialize_prof(dhd, _params, DHD_PNO_BATCH_MODE);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call _dhd_pno_reinitialize_prof\n",
++				__FUNCTION__));
++			goto exit;
++		}
++	} else {
++		/* batch mode is already started */
++		return -EBUSY;
++	}
++	_params->params_batch.scan_fr = batch_params->scan_fr;
++	_params->params_batch.bestn = batch_params->bestn;
++	_params->params_batch.mscan = (batch_params->mscan)?
++		batch_params->mscan : DEFAULT_BATCH_MSCAN;
++	_params->params_batch.nchan = batch_params->nchan;
++	memcpy(_params->params_batch.chan_list, batch_params->chan_list,
++		sizeof(_params->params_batch.chan_list));
++
++	memset(_chan_list, 0, sizeof(_chan_list));
++
++	rem_nchan = ARRAYSIZE(batch_params->chan_list) - batch_params->nchan;
++	if (batch_params->band == WLC_BAND_2G || batch_params->band == WLC_BAND_5G) {
++		/* get a valid channel list based on band B or A */
++		err = _dhd_pno_get_channels(dhd,
++		&_params->params_batch.chan_list[batch_params->nchan],
++		&rem_nchan, batch_params->band, FALSE);
++		if (err < 0) {
++			DHD_ERROR(("%s: failed to get valid channel list(band : %d)\n",
++				__FUNCTION__, batch_params->band));
++			goto exit;
++		}
++		/* now we need to update nchan because rem_chan has valid channel count */
++		_params->params_batch.nchan += rem_nchan;
++		/* need to sort channel list */
++		sort(_params->params_batch.chan_list, _params->params_batch.nchan,
++			sizeof(_params->params_batch.chan_list[0]), _dhd_pno_cmpfunc, NULL);
++	}
++#ifdef PNO_DEBUG
++{
++		DHD_PNO(("Channel list : "));
++		for (i = 0; i < _params->params_batch.nchan; i++) {
++			DHD_PNO(("%d ", _params->params_batch.chan_list[i]));
++		}
++		DHD_PNO(("\n"));
++}
++#endif
++	if (_params->params_batch.nchan) {
++		/* copy the channel list into local array */
++		memcpy(_chan_list, _params->params_batch.chan_list, sizeof(_chan_list));
++		tot_nchan = _params->params_batch.nchan;
++	}
++	if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) {
++		DHD_PNO(("PNO SSID is on progress in firmware\n"));
++		/* store current pno_mode before disabling pno */
++		mode = _pno_state->pno_mode;
++		err = _dhd_pno_enable(dhd, PNO_OFF);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to disable PNO\n", __FUNCTION__));
++			goto exit;
++		}
++		/* restore the previous mode */
++		_pno_state->pno_mode = mode;
++		/* Use the superset for channelist between two mode */
++		_params2 = &(_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS]);
++		if (_params2->params_legacy.nchan > 0 && _params->params_batch.nchan > 0) {
++			err = _dhd_pno_chan_merge(_chan_list, &tot_nchan,
++				&_params2->params_legacy.chan_list[0],
++				_params2->params_legacy.nchan,
++				&_params->params_batch.chan_list[0], _params->params_batch.nchan);
++			if (err < 0) {
++				DHD_ERROR(("%s : failed to merge channel list"
++				" between legacy and batch\n",
++					__FUNCTION__));
++				goto exit;
++			}
++		} else {
++			DHD_PNO(("superset channel will use all channels in firmware\n"));
++		}
++		if ((err = _dhd_pno_add_ssid(dhd, &_params2->params_legacy.ssid_list,
++				_params2->params_legacy.nssid)) < 0) {
++			DHD_ERROR(("failed to add ssid list (err %d) in firmware\n", err));
++			goto exit;
++		}
++	}
++	if ((err = _dhd_pno_set(dhd, _params, DHD_PNO_BATCH_MODE)) < 0) {
++		DHD_ERROR(("%s : failed to set call pno_set (err %d) in firmware\n",
++			__FUNCTION__, err));
++		goto exit;
++	} else {
++		/* we need to return mscan */
++		mscan = err;
++	}
++	if (tot_nchan > 0) {
++		if ((err = _dhd_pno_cfg(dhd, _chan_list, tot_nchan)) < 0) {
++			DHD_ERROR(("%s : failed to set call pno_cfg (err %d) in firmware\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++	}
++	if (_pno_state->pno_status == DHD_PNO_DISABLED) {
++		if ((err = _dhd_pno_enable(dhd, PNO_ON)) < 0)
++			DHD_ERROR(("%s : failed to enable PNO\n", __FUNCTION__));
++	}
++exit:
++	/* clear mode in case of error */
++	if (err < 0)
++		_pno_state->pno_mode &= ~DHD_PNO_BATCH_MODE;
++	else {
++		/* return #max scan firmware can do */
++		err = mscan;
++	}
++	return err;
++}
++
++
++#ifdef GSCAN_SUPPORT
++
++static int
++dhd_set_epno_params(dhd_pub_t *dhd, wl_pfn_ssid_params_t *params, bool set)
++{
++	wl_pfn_ssid_cfg_t cfg;
++	int err;
++	NULL_CHECK(dhd, "dhd is NULL\n", err);
++	memset(&cfg, 0, sizeof(wl_pfn_ssid_cfg_t));
++	cfg.version = WL_PFN_SSID_CFG_VERSION;
++
++	/* If asked to clear params (set == FALSE) just set the CLEAR bit */
++	if (!set)
++		cfg.flags |= WL_PFN_SSID_CFG_CLEAR;
++	else if (params)
++		memcpy(&cfg.params, params, sizeof(wl_pfn_ssid_params_t));
++	err = dhd_iovar(dhd, 0, "pfn_ssid_cfg", (char *)&cfg,
++			sizeof(wl_pfn_ssid_cfg_t), NULL, 0, TRUE);
++	if (err != BCME_OK) {
++		DHD_ERROR(("%s : Failed to execute pfn_ssid_cfg %d\n", __FUNCTION__, err));
++	}
++	return err;
++}
++
++int
++dhd_pno_flush_fw_epno(dhd_pub_t *dhd)
++{
++	int err;
++
++	NULL_CHECK(dhd, "dhd is NULL\n", err);
++
++	err = dhd_set_epno_params(dhd, NULL, FALSE);
++	if (err < 0) {
++		DHD_ERROR(("failed to set ePNO params %d\n", err));
++		return err;
++	}
++	err = _dhd_pno_flush_ssid(dhd);
++	return err;
++}
++
++int
++dhd_pno_set_epno(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	dhd_pno_params_t *params;
++	dhd_pno_status_info_t *_pno_state;
++
++	struct dhd_pno_gscan_params *gscan_params;
++
++	NULL_CHECK(dhd, "dhd is NULL\n", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++	gscan_params = &params->params_gscan;
++
++	if (gscan_params->epno_cfg.num_epno_ssid) {
++		DHD_PNO(("num_epno_ssid %d\n", gscan_params->epno_cfg.num_epno_ssid));
++		if ((err = _dhd_pno_add_ssid(dhd, &gscan_params->epno_cfg.epno_ssid_list,
++			gscan_params->epno_cfg.num_epno_ssid)) < 0) {
++			DHD_ERROR(("failed to add ssid list (err %d) to firmware\n", err));
++			return err;
++		}
++		err = dhd_set_epno_params(dhd, &gscan_params->epno_cfg.params, TRUE);
++		if (err < 0) {
++			DHD_ERROR(("failed to set ePNO params %d\n", err));
++		}
++	}
++	return err;
++}
++
++
++static void
++dhd_pno_reset_cfg_gscan(dhd_pno_params_t *_params,
++            dhd_pno_status_info_t *_pno_state, uint8 flags)
++{
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	if (flags & GSCAN_FLUSH_SCAN_CFG) {
++		_params->params_gscan.bestn = 0;
++		_params->params_gscan.mscan = 0;
++		_params->params_gscan.buffer_threshold = GSCAN_BATCH_NO_THR_SET;
++		_params->params_gscan.scan_fr = 0;
++		_params->params_gscan.send_all_results_flag = 0;
++		memset(_params->params_gscan.channel_bucket, 0,
++		_params->params_gscan.nchannel_buckets *
++		 sizeof(struct dhd_pno_gscan_channel_bucket));
++		_params->params_gscan.nchannel_buckets = 0;
++		DHD_PNO(("Flush Scan config\n"));
++	}
++	if (flags & GSCAN_FLUSH_HOTLIST_CFG) {
++		struct dhd_pno_bssid *iter, *next;
++		if (_params->params_gscan.nbssid_hotlist > 0) {
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++			list_for_each_entry_safe(iter, next,
++				&_params->params_gscan.hotlist_bssid_list, list) {
++				list_del(&iter->list);
++				kfree(iter);
++			}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++		}
++		_params->params_gscan.nbssid_hotlist = 0;
++		DHD_PNO(("Flush Hotlist Config\n"));
++	}
++	if (flags & GSCAN_FLUSH_EPNO_CFG) {
++		dhd_pno_ssid_t *iter, *next;
++		dhd_epno_ssid_cfg_t *epno_cfg = &_params->params_gscan.epno_cfg;
++
++		if (epno_cfg->num_epno_ssid > 0) {
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++			list_for_each_entry_safe(iter, next,
++				&epno_cfg->epno_ssid_list, list) {
++				list_del(&iter->list);
++				kfree(iter);
++			}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++		epno_cfg->num_epno_ssid = 0;
++		}
++		memset(&epno_cfg->params, 0, sizeof(wl_pfn_ssid_params_t));
++		DHD_PNO(("Flushed ePNO Config\n"));
++	}
++
++	return;
++}
++
++int
++dhd_pno_lock_batch_results(dhd_pub_t *dhd)
++{
++	dhd_pno_status_info_t *_pno_state;
++	int err = BCME_OK;
++
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	mutex_lock(&_pno_state->pno_mutex);
++	return err;
++}
++
++void
++dhd_pno_unlock_batch_results(dhd_pub_t *dhd)
++{
++	dhd_pno_status_info_t *_pno_state;
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	mutex_unlock(&_pno_state->pno_mutex);
++	return;
++}
++
++int dhd_wait_batch_results_complete(dhd_pub_t *dhd)
++{
++	dhd_pno_status_info_t *_pno_state;
++	dhd_pno_params_t *_params;
++	int err = BCME_OK;
++
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++
++	/* Has the workqueue finished its job already?? */
++	if (_params->params_gscan.get_batch_flag == GSCAN_BATCH_RETRIEVAL_IN_PROGRESS) {
++		DHD_PNO(("%s: Waiting to complete retrieval..\n", __FUNCTION__));
++		wait_event_interruptible_timeout(_pno_state->batch_get_wait,
++		     is_batch_retrieval_complete(&_params->params_gscan),
++		     msecs_to_jiffies(GSCAN_BATCH_GET_MAX_WAIT));
++	} else { /* GSCAN_BATCH_RETRIEVAL_COMPLETE */
++		gscan_results_cache_t *iter;
++		uint16 num_results = 0;
++
++		mutex_lock(&_pno_state->pno_mutex);
++		iter = _params->params_gscan.gscan_batch_cache;
++		while (iter) {
++			num_results += iter->tot_count - iter->tot_consumed;
++			iter = iter->next;
++		}
++		mutex_unlock(&_pno_state->pno_mutex);
++
++		/* All results consumed/No results cached??
++		 * Get fresh results from FW
++		 */
++		if ((_pno_state->pno_mode & DHD_PNO_GSCAN_MODE) && !num_results) {
++			DHD_PNO(("%s: No results cached, getting from FW..\n", __FUNCTION__));
++			err = dhd_retreive_batch_scan_results(dhd);
++			if (err == BCME_OK) {
++				wait_event_interruptible_timeout(_pno_state->batch_get_wait,
++				  is_batch_retrieval_complete(&_params->params_gscan),
++				  msecs_to_jiffies(GSCAN_BATCH_GET_MAX_WAIT));
++			}
++		}
++	}
++	DHD_PNO(("%s: Wait complete\n", __FUNCTION__));
++	return err;
++}
++
++static void *
++dhd_get_gscan_batch_results(dhd_pub_t *dhd, uint32 *len)
++{
++	gscan_results_cache_t *iter, *results;
++	dhd_pno_status_info_t *_pno_state;
++	dhd_pno_params_t *_params;
++	uint16 num_scan_ids = 0, num_results = 0;
++
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++
++	iter = results = _params->params_gscan.gscan_batch_cache;
++	while (iter) {
++		num_results += iter->tot_count - iter->tot_consumed;
++		num_scan_ids++;
++		iter = iter->next;
++	}
++
++	*len = ((num_results << 16) | (num_scan_ids));
++	return results;
++}
++
++int
++dhd_pno_set_cfg_gscan(dhd_pub_t *dhd, dhd_pno_gscan_cmd_cfg_t type,
++    void *buf, bool flush)
++{
++	int err = BCME_OK;
++	dhd_pno_params_t *_params;
++	int i;
++	dhd_pno_status_info_t *_pno_state;
++
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++	mutex_lock(&_pno_state->pno_mutex);
++
++	switch (type) {
++	case DHD_PNO_BATCH_SCAN_CFG_ID:
++		{
++			gscan_batch_params_t *ptr = (gscan_batch_params_t *)buf;
++			_params->params_gscan.bestn = ptr->bestn;
++			_params->params_gscan.mscan = ptr->mscan;
++			_params->params_gscan.buffer_threshold = ptr->buffer_threshold;
++		}
++		break;
++		case DHD_PNO_GEOFENCE_SCAN_CFG_ID:
++		{
++			gscan_hotlist_scan_params_t *ptr = (gscan_hotlist_scan_params_t *)buf;
++			struct dhd_pno_bssid *_pno_bssid;
++			struct bssid_t *bssid_ptr;
++			int8 flags;
++
++			if (flush) {
++				dhd_pno_reset_cfg_gscan(_params, _pno_state,
++				    GSCAN_FLUSH_HOTLIST_CFG);
++			}
++
++			if (!ptr->nbssid) {
++				break;
++			}
++			if (!_params->params_gscan.nbssid_hotlist) {
++				INIT_LIST_HEAD(&_params->params_gscan.hotlist_bssid_list);
++			}
++
++			for (i = 0, bssid_ptr = ptr->bssid; i < ptr->nbssid; i++, bssid_ptr++) {
++				_pno_bssid = kzalloc(sizeof(struct dhd_pno_bssid), GFP_KERNEL);
++
++				if (!_pno_bssid) {
++					DHD_ERROR(("_pno_bssid is NULL, cannot kalloc %zd bytes",
++					       sizeof(struct dhd_pno_bssid)));
++					err = BCME_NOMEM;
++					goto exit;
++				}
++				memcpy(&_pno_bssid->macaddr, &bssid_ptr->macaddr, ETHER_ADDR_LEN);
++
++				flags = (int8) bssid_ptr->rssi_reporting_threshold;
++				_pno_bssid->flags = flags  << WL_PFN_RSSI_SHIFT;
++				list_add_tail(&_pno_bssid->list,
++				   &_params->params_gscan.hotlist_bssid_list);
++			}
++
++			_params->params_gscan.nbssid_hotlist += ptr->nbssid;
++			_params->params_gscan.lost_ap_window = ptr->lost_ap_window;
++		}
++		break;
++	case DHD_PNO_SCAN_CFG_ID:
++		{
++			int k;
++			uint16 band;
++			gscan_scan_params_t *ptr = (gscan_scan_params_t *)buf;
++			struct dhd_pno_gscan_channel_bucket *ch_bucket;
++
++			if (ptr->nchannel_buckets <= GSCAN_MAX_CH_BUCKETS) {
++				_params->params_gscan.nchannel_buckets = ptr->nchannel_buckets;
++
++				memcpy(_params->params_gscan.channel_bucket, ptr->channel_bucket,
++				    _params->params_gscan.nchannel_buckets *
++				    sizeof(struct dhd_pno_gscan_channel_bucket));
++				ch_bucket = _params->params_gscan.channel_bucket;
++
++				for (i = 0; i < ptr->nchannel_buckets; i++) {
++					band = ch_bucket[i].band;
++					for (k = 0; k < ptr->channel_bucket[i].num_channels; k++)  {
++						ch_bucket[i].chan_list[k] =
++						wf_mhz2channel(ptr->channel_bucket[i].chan_list[k],
++							0);
++					}
++					ch_bucket[i].band = 0;
++					/* HAL and DHD use different bits for 2.4G and
++					 * 5G in bitmap. Hence translating it here...
++					 */
++					if (band & GSCAN_BG_BAND_MASK) {
++						ch_bucket[i].band |= WLC_BAND_2G;
++					}
++					if (band & GSCAN_A_BAND_MASK) {
++						ch_bucket[i].band |= WLC_BAND_5G;
++					}
++					if (band & GSCAN_DFS_MASK) {
++						ch_bucket[i].band |= GSCAN_DFS_MASK;
++					}
++					DHD_PNO(("band %d report_flag %d\n", ch_bucket[i].band,
++					          ch_bucket[i].report_flag));
++				}
++
++				for (i = 0; i < ptr->nchannel_buckets; i++) {
++					ch_bucket[i].bucket_freq_multiple =
++					ch_bucket[i].bucket_freq_multiple/ptr->scan_fr;
++					ch_bucket[i].bucket_max_multiple =
++					ch_bucket[i].bucket_max_multiple/ptr->scan_fr;
++					DHD_PNO(("mult %d max_mult %d\n",
++					                 ch_bucket[i].bucket_freq_multiple,
++					                 ch_bucket[i].bucket_max_multiple));
++				}
++				_params->params_gscan.scan_fr = ptr->scan_fr;
++
++				DHD_PNO(("num_buckets %d scan_fr %d\n", ptr->nchannel_buckets,
++				        _params->params_gscan.scan_fr));
++			} else {
++				err = BCME_BADARG;
++			}
++		}
++		break;
++	case DHD_PNO_EPNO_CFG_ID:
++		if (flush) {
++			dhd_pno_reset_cfg_gscan(_params, _pno_state,
++			   GSCAN_FLUSH_EPNO_CFG);
++		}
++		break;
++	case DHD_PNO_EPNO_PARAMS_ID:
++		if (flush) {
++			memset(&_params->params_gscan.epno_cfg.params, 0,
++			     sizeof(wl_pfn_ssid_params_t));
++		}
++		if (buf) {
++			memcpy(&_params->params_gscan.epno_cfg.params, buf,
++			     sizeof(wl_pfn_ssid_params_t));
++		}
++		break;
++	default:
++			err = BCME_BADARG;
++			DHD_ERROR(("%s: Unrecognized cmd type - %d\n", __FUNCTION__, type));
++			break;
++	}
++exit:
++	mutex_unlock(&_pno_state->pno_mutex);
++	return err;
++
++}
++
++
++static bool
++validate_gscan_params(struct dhd_pno_gscan_params *gscan_params)
++{
++	unsigned int i, k;
++
++	if (!gscan_params->scan_fr || !gscan_params->nchannel_buckets) {
++		DHD_ERROR(("%s : Scan freq - %d or number of channel buckets - %d is empty\n",
++		 __FUNCTION__, gscan_params->scan_fr, gscan_params->nchannel_buckets));
++		return false;
++	}
++
++	for (i = 0; i < gscan_params->nchannel_buckets; i++) {
++		if (!gscan_params->channel_bucket[i].band) {
++			for (k = 0; k < gscan_params->channel_bucket[i].num_channels; k++) {
++				if (gscan_params->channel_bucket[i].chan_list[k] > CHANNEL_5G_MAX) {
++					DHD_ERROR(("%s : Unknown channel %d\n", __FUNCTION__,
++					 gscan_params->channel_bucket[i].chan_list[k]));
++					return false;
++				}
++			}
++		}
++	}
++
++	return true;
++}
++
++static int
++dhd_pno_set_for_gscan(dhd_pub_t *dhd, struct dhd_pno_gscan_params *gscan_params)
++{
++	int err = BCME_OK;
++	int mode, i = 0;
++	uint16 _chan_list[WL_NUMCHANNELS];
++	int tot_nchan = 0;
++	int num_buckets_to_fw, tot_num_buckets, gscan_param_size;
++	dhd_pno_status_info_t *_pno_state = PNO_GET_PNOSTATE(dhd);
++	wl_pfn_gscan_ch_bucket_cfg_t *ch_bucket = NULL;
++	wl_pfn_gscan_cfg_t *pfn_gscan_cfg_t = NULL;
++	wl_pfn_significant_bssid_t *p_pfn_significant_bssid = NULL;
++	wl_pfn_bssid_t *p_pfn_bssid = NULL;
++	dhd_pno_params_t	*_params;
++	bool fw_flushed = FALSE;
++
++	_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	NULL_CHECK(gscan_params, "gscan_params is NULL", err);
++
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	if (!dhd_support_sta_mode(dhd)) {
++		err = BCME_BADOPTION;
++		goto exit;
++	}
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n", __FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++	if (!validate_gscan_params(gscan_params)) {
++		DHD_ERROR(("%s : Cannot start gscan - bad params\n", __FUNCTION__));
++		err = BCME_BADARG;
++		goto exit;
++	}
++
++	if (!(ch_bucket = dhd_pno_gscan_create_channel_list(dhd, _pno_state,
++	    _chan_list, &tot_num_buckets, &num_buckets_to_fw))) {
++		goto exit;
++	}
++
++	mutex_lock(&_pno_state->pno_mutex);
++	/* Clear any pre-existing results in our cache
++	 * not consumed by framework
++	 */
++	dhd_gscan_clear_all_batch_results(dhd);
++	if (_pno_state->pno_mode & (DHD_PNO_GSCAN_MODE | DHD_PNO_LEGACY_MODE)) {
++		/* store current pno_mode before disabling pno */
++		mode = _pno_state->pno_mode;
++		err = dhd_pno_clean(dhd);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to disable PNO\n", __FUNCTION__));
++			mutex_unlock(&_pno_state->pno_mutex);
++			goto exit;
++		}
++		fw_flushed = TRUE;
++		/* restore the previous mode */
++		_pno_state->pno_mode = mode;
++	}
++	_pno_state->pno_mode |= DHD_PNO_GSCAN_MODE;
++	mutex_unlock(&_pno_state->pno_mutex);
++
++	if ((_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) &&
++		!gscan_params->epno_cfg.num_epno_ssid) {
++		struct dhd_pno_legacy_params *params_legacy;
++		params_legacy = &(_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS].params_legacy);
++
++		if ((err = _dhd_pno_add_ssid(dhd, &params_legacy->ssid_list,
++			params_legacy->nssid)) < 0) {
++			DHD_ERROR(("failed to add ssid list (err %d) in firmware\n", err));
++			goto exit;
++		}
++	}
++
++	if ((err = _dhd_pno_set(dhd, _params, DHD_PNO_GSCAN_MODE)) < 0) {
++		DHD_ERROR(("failed to set call pno_set (err %d) in firmware\n", err));
++		goto exit;
++	}
++
++	gscan_param_size = sizeof(wl_pfn_gscan_cfg_t) +
++	          (num_buckets_to_fw - 1) * sizeof(wl_pfn_gscan_ch_bucket_cfg_t);
++	pfn_gscan_cfg_t = (wl_pfn_gscan_cfg_t *) MALLOCZ(dhd->osh, gscan_param_size);
++
++	if (!pfn_gscan_cfg_t) {
++		DHD_ERROR(("%s: failed to malloc memory of size %d\n",
++		   __FUNCTION__, gscan_param_size));
++		err = BCME_NOMEM;
++		goto exit;
++	}
++
++	pfn_gscan_cfg_t->version = WL_GSCAN_CFG_VERSION;
++	if (gscan_params->mscan)
++		pfn_gscan_cfg_t->buffer_threshold = gscan_params->buffer_threshold;
++	else
++		pfn_gscan_cfg_t->buffer_threshold = GSCAN_BATCH_NO_THR_SET;
++
++	pfn_gscan_cfg_t->flags =
++	         (gscan_params->send_all_results_flag & GSCAN_SEND_ALL_RESULTS_MASK);
++	pfn_gscan_cfg_t->flags |= GSCAN_ALL_BUCKETS_IN_FIRST_SCAN_MASK;
++	pfn_gscan_cfg_t->count_of_channel_buckets = num_buckets_to_fw;
++	pfn_gscan_cfg_t->retry_threshold = GSCAN_RETRY_THRESHOLD;
++
++	for (i = 0; i < num_buckets_to_fw; i++) {
++		pfn_gscan_cfg_t->channel_bucket[i].bucket_end_index =
++		           ch_bucket[i].bucket_end_index;
++		pfn_gscan_cfg_t->channel_bucket[i].bucket_freq_multiple =
++		           ch_bucket[i].bucket_freq_multiple;
++		pfn_gscan_cfg_t->channel_bucket[i].max_freq_multiple =
++		           ch_bucket[i].max_freq_multiple;
++		pfn_gscan_cfg_t->channel_bucket[i].repeat =
++		           ch_bucket[i].repeat;
++		pfn_gscan_cfg_t->channel_bucket[i].flag =
++		           ch_bucket[i].flag;
++	}
++
++	tot_nchan = pfn_gscan_cfg_t->channel_bucket[num_buckets_to_fw - 1].bucket_end_index + 1;
++	DHD_PNO(("Total channel num %d total ch_buckets  %d ch_buckets_to_fw %d \n", tot_nchan,
++	      tot_num_buckets, num_buckets_to_fw));
++
++	if ((err = _dhd_pno_cfg(dhd, _chan_list, tot_nchan)) < 0) {
++		DHD_ERROR(("%s : failed to set call pno_cfg (err %d) in firmware\n",
++			__FUNCTION__, err));
++		goto exit;
++	}
++
++	if ((err = _dhd_pno_gscan_cfg(dhd, pfn_gscan_cfg_t, gscan_param_size)) < 0) {
++		DHD_ERROR(("%s : failed to set call pno_gscan_cfg (err %d) in firmware\n",
++			__FUNCTION__, err));
++		goto exit;
++	}
++	/* Reprogram ePNO cfg from dhd cache if FW has been flushed */
++	if (fw_flushed) {
++		dhd_pno_set_epno(dhd);
++	}
++
++	if (gscan_params->nbssid_hotlist) {
++		struct dhd_pno_bssid *iter, *next;
++		wl_pfn_bssid_t *ptr;
++		p_pfn_bssid = (wl_pfn_bssid_t *)kzalloc(sizeof(wl_pfn_bssid_t) *
++		       gscan_params->nbssid_hotlist, GFP_KERNEL);
++		if (p_pfn_bssid == NULL) {
++			DHD_ERROR(("%s : failed to allocate wl_pfn_bssid_t array"
++			" (count: %d)",
++				__FUNCTION__, _params->params_hotlist.nbssid));
++			err = BCME_NOMEM;
++			_pno_state->pno_mode &= ~DHD_PNO_HOTLIST_MODE;
++			goto exit;
++		}
++		ptr = p_pfn_bssid;
++		/* convert dhd_pno_bssid to wl_pfn_bssid */
++		DHD_PNO(("nhotlist %d\n", gscan_params->nbssid_hotlist));
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++		list_for_each_entry_safe(iter, next,
++		          &gscan_params->hotlist_bssid_list, list) {
++			char buffer_hotlist[64];
++			memcpy(&ptr->macaddr,
++			&iter->macaddr, ETHER_ADDR_LEN);
++			DHD_PNO(("%s\n", bcm_ether_ntoa(&ptr->macaddr, buffer_hotlist)));
++			BCM_REFERENCE(buffer_hotlist);
++			ptr->flags = iter->flags;
++			ptr++;
++		}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++		err = _dhd_pno_add_bssid(dhd, p_pfn_bssid, gscan_params->nbssid_hotlist);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call _dhd_pno_add_bssid(err :%d)\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++	}
++	if ((err = _dhd_pno_enable(dhd, PNO_ON)) < 0) {
++		DHD_ERROR(("%s : failed to enable PNO err %d\n", __FUNCTION__, err));
++	}
++
++exit:
++	/* clear mode in case of error */
++	if (err < 0) {
++		int ret = dhd_pno_clean(dhd);
++
++		if (ret < 0) {
++			DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++				__FUNCTION__, ret));
++		} else {
++			_pno_state->pno_mode &= ~DHD_PNO_GSCAN_MODE;
++		}
++	}
++	kfree(p_pfn_significant_bssid);
++	kfree(p_pfn_bssid);
++	if (pfn_gscan_cfg_t) {
++		MFREE(dhd->osh, pfn_gscan_cfg_t, gscan_param_size);
++	}
++	if (ch_bucket) {
++		MFREE(dhd->osh, ch_bucket,
++		(tot_num_buckets * sizeof(wl_pfn_gscan_ch_bucket_cfg_t)));
++	}
++	return err;
++
++}
++
++static wl_pfn_gscan_ch_bucket_cfg_t *
++dhd_pno_gscan_create_channel_list(dhd_pub_t *dhd,
++                                  dhd_pno_status_info_t *_pno_state,
++                                  uint16 *chan_list,
++                                  uint32 *num_buckets,
++                                  uint32 *num_buckets_to_fw)
++{
++	int i, num_channels, err, nchan = WL_NUMCHANNELS, ch_cnt;
++	uint16 *ptr = chan_list, max;
++	wl_pfn_gscan_ch_bucket_cfg_t *ch_bucket;
++	dhd_pno_params_t *_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++	bool is_pno_legacy_running;
++	dhd_pno_gscan_channel_bucket_t *gscan_buckets = _params->params_gscan.channel_bucket;
++
++	/* ePNO and Legacy PNO do not co-exist */
++	is_pno_legacy_running = ((_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) &&
++		!_params->params_gscan.epno_cfg.num_epno_ssid);
++
++	if (is_pno_legacy_running)
++		*num_buckets = _params->params_gscan.nchannel_buckets + 1;
++	else
++		*num_buckets = _params->params_gscan.nchannel_buckets;
++
++	*num_buckets_to_fw = 0;
++
++	ch_bucket = (wl_pfn_gscan_ch_bucket_cfg_t *) MALLOC(dhd->osh,
++	   ((*num_buckets) * sizeof(wl_pfn_gscan_ch_bucket_cfg_t)));
++
++	if (!ch_bucket) {
++		DHD_ERROR(("%s: failed to malloc memory of size %zd\n",
++			__FUNCTION__, (*num_buckets) * sizeof(wl_pfn_gscan_ch_bucket_cfg_t)));
++		*num_buckets_to_fw = *num_buckets = 0;
++		return NULL;
++	}
++
++	max = gscan_buckets[0].bucket_freq_multiple;
++	num_channels = 0;
++	/* nchan is the remaining space left in chan_list buffer
++	 * So any overflow list of channels is ignored
++	 */
++	for (i = 0; i < _params->params_gscan.nchannel_buckets && nchan; i++) {
++		if (!gscan_buckets[i].band) {
++			ch_cnt = MIN(gscan_buckets[i].num_channels, (uint8)nchan);
++			num_channels += ch_cnt;
++			memcpy(ptr, gscan_buckets[i].chan_list,
++			    ch_cnt * sizeof(uint16));
++			ptr = ptr + ch_cnt;
++		} else {
++			/* get a valid channel list based on band B or A */
++			err = _dhd_pno_get_channels(dhd, ptr,
++			        &nchan, (gscan_buckets[i].band & GSCAN_ABG_BAND_MASK),
++			        !(gscan_buckets[i].band & GSCAN_DFS_MASK));
++
++			if (err < 0) {
++				DHD_ERROR(("%s: failed to get valid channel list(band : %d)\n",
++					__FUNCTION__, gscan_buckets[i].band));
++				MFREE(dhd->osh, ch_bucket,
++				      ((*num_buckets) * sizeof(wl_pfn_gscan_ch_bucket_cfg_t)));
++				*num_buckets_to_fw = *num_buckets = 0;
++				return NULL;
++			}
++
++			num_channels += nchan;
++			ptr = ptr + nchan;
++		}
++
++		ch_bucket[i].bucket_end_index = num_channels - 1;
++		ch_bucket[i].bucket_freq_multiple = gscan_buckets[i].bucket_freq_multiple;
++		ch_bucket[i].repeat = gscan_buckets[i].repeat;
++		ch_bucket[i].max_freq_multiple = gscan_buckets[i].bucket_max_multiple;
++		ch_bucket[i].flag = gscan_buckets[i].report_flag;
++		/* HAL and FW interpretations are opposite for this bit */
++		ch_bucket[i].flag ^= DHD_PNO_REPORT_NO_BATCH;
++		if (max < gscan_buckets[i].bucket_freq_multiple)
++			max = gscan_buckets[i].bucket_freq_multiple;
++		nchan = WL_NUMCHANNELS - num_channels;
++		*num_buckets_to_fw = *num_buckets_to_fw + 1;
++		DHD_PNO(("end_idx  %d freq_mult - %d\n",
++		ch_bucket[i].bucket_end_index, ch_bucket[i].bucket_freq_multiple));
++	}
++
++	_params->params_gscan.max_ch_bucket_freq = max;
++	/* Legacy PNO maybe running, which means we need to create a legacy PNO bucket
++	 * Get GCF of Legacy PNO and Gscan scanfreq
++	 */
++	if (is_pno_legacy_running) {
++		dhd_pno_params_t *_params1 = &_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS];
++		uint16 *legacy_chan_list = _params1->params_legacy.chan_list;
++		uint16 common_freq;
++		uint32 legacy_bucket_idx = _params->params_gscan.nchannel_buckets;
++		/* If no space is left then only gscan buckets will be sent to FW */
++		if (nchan) {
++			common_freq = gcd(_params->params_gscan.scan_fr,
++			                  _params1->params_legacy.scan_fr);
++			max = gscan_buckets[0].bucket_freq_multiple;
++			/* GSCAN buckets */
++			for (i = 0; i < _params->params_gscan.nchannel_buckets; i++) {
++				ch_bucket[i].bucket_freq_multiple *= _params->params_gscan.scan_fr;
++				ch_bucket[i].bucket_freq_multiple /= common_freq;
++				if (max < gscan_buckets[i].bucket_freq_multiple)
++					max = gscan_buckets[i].bucket_freq_multiple;
++			}
++			/* Legacy PNO bucket */
++			ch_bucket[legacy_bucket_idx].bucket_freq_multiple =
++			           _params1->params_legacy.scan_fr;
++			ch_bucket[legacy_bucket_idx].bucket_freq_multiple /=
++			           common_freq;
++			_params->params_gscan.max_ch_bucket_freq = MAX(max,
++			         ch_bucket[legacy_bucket_idx].bucket_freq_multiple);
++			ch_bucket[legacy_bucket_idx].flag = CH_BUCKET_REPORT_REGULAR;
++			/* Now add channels to the legacy scan bucket */
++			for (i = 0; i < _params1->params_legacy.nchan && nchan; i++, nchan--) {
++				ptr[i] = legacy_chan_list[i];
++				num_channels++;
++			}
++			ch_bucket[legacy_bucket_idx].bucket_end_index = num_channels - 1;
++			*num_buckets_to_fw = *num_buckets_to_fw + 1;
++			DHD_PNO(("end_idx  %d freq_mult - %d\n",
++			            ch_bucket[legacy_bucket_idx].bucket_end_index,
++			            ch_bucket[legacy_bucket_idx].bucket_freq_multiple));
++		}
++	}
++	return ch_bucket;
++}
++
++static int
++dhd_pno_stop_for_gscan(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	int mode;
++	dhd_pno_status_info_t *_pno_state;
++
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	if (!dhd_support_sta_mode(dhd)) {
++		err = BCME_BADOPTION;
++		goto exit;
++	}
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n",
++			__FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++	if (!(_pno_state->pno_mode & DHD_PNO_GSCAN_MODE)) {
++		DHD_ERROR(("%s : GSCAN is not enabled\n", __FUNCTION__));
++		goto exit;
++	}
++	if (_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS].params_gscan.mscan) {
++		/* retrieve the batching data from firmware into host */
++		err = dhd_wait_batch_results_complete(dhd);
++		if (err != BCME_OK)
++			goto exit;
++	}
++	mutex_lock(&_pno_state->pno_mutex);
++	mode = _pno_state->pno_mode & ~DHD_PNO_GSCAN_MODE;
++	err = dhd_pno_clean(dhd);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++			__FUNCTION__, err));
++		mutex_unlock(&_pno_state->pno_mutex);
++		return err;
++	}
++	_pno_state->pno_mode = mode;
++	mutex_unlock(&_pno_state->pno_mutex);
++
++	/* Reprogram Legacy PNO if it was running */
++	if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) {
++		struct dhd_pno_legacy_params *params_legacy;
++		uint16 chan_list[WL_NUMCHANNELS];
++
++		params_legacy = &(_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS].params_legacy);
++		_pno_state->pno_mode &= ~DHD_PNO_LEGACY_MODE;
++		DHD_PNO(("Restarting Legacy PNO SSID scan...\n"));
++		memcpy(chan_list, params_legacy->chan_list,
++		    (params_legacy->nchan * sizeof(uint16)));
++		err = dhd_pno_set_legacy_pno(dhd, params_legacy->scan_fr,
++			params_legacy->pno_repeat, params_legacy->pno_freq_expo_max,
++			chan_list, params_legacy->nchan);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to restart legacy PNO scan(err: %d)\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++
++	}
++
++exit:
++	return err;
++}
++
++int
++dhd_pno_initiate_gscan_request(dhd_pub_t *dhd, bool run, bool flush)
++{
++	int err = BCME_OK;
++	dhd_pno_params_t *params;
++	dhd_pno_status_info_t *_pno_state;
++	struct dhd_pno_gscan_params *gscan_params;
++
++	NULL_CHECK(dhd, "dhd is NULL\n", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++
++	DHD_PNO(("%s enter - run %d flush %d\n", __FUNCTION__, run, flush));
++
++	params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++	gscan_params = &params->params_gscan;
++
++	if (run) {
++		err = dhd_pno_set_for_gscan(dhd, gscan_params);
++	} else {
++		if (flush) {
++			mutex_lock(&_pno_state->pno_mutex);
++			dhd_pno_reset_cfg_gscan(params, _pno_state, GSCAN_FLUSH_ALL_CFG);
++			mutex_unlock(&_pno_state->pno_mutex);
++		}
++		/* Need to stop all gscan */
++		err = dhd_pno_stop_for_gscan(dhd);
++	}
++
++	return err;
++}
++
++int
++dhd_pno_enable_full_scan_result(dhd_pub_t *dhd, bool real_time_flag)
++{
++	int err = BCME_OK;
++	dhd_pno_params_t *params;
++	dhd_pno_status_info_t *_pno_state;
++	struct dhd_pno_gscan_params *gscan_params;
++	uint8 old_flag;
++
++	NULL_CHECK(dhd, "dhd is NULL\n", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n", __FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++	params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++	gscan_params = &params->params_gscan;
++
++	mutex_lock(&_pno_state->pno_mutex);
++
++	old_flag = gscan_params->send_all_results_flag;
++	gscan_params->send_all_results_flag = (uint8) real_time_flag;
++	if (_pno_state->pno_mode & DHD_PNO_GSCAN_MODE) {
++	    if (old_flag != gscan_params->send_all_results_flag) {
++			wl_pfn_gscan_cfg_t gscan_cfg;
++
++			gscan_cfg.version = WL_GSCAN_CFG_VERSION;
++			gscan_cfg.flags = (gscan_params->send_all_results_flag &
++			                           GSCAN_SEND_ALL_RESULTS_MASK);
++			gscan_cfg.flags |= GSCAN_CFG_FLAGS_ONLY_MASK;
++
++			if ((err = _dhd_pno_gscan_cfg(dhd, &gscan_cfg,
++			            sizeof(wl_pfn_gscan_cfg_t))) < 0) {
++				DHD_ERROR(("%s : pno_gscan_cfg failed (err %d) in firmware\n",
++					__FUNCTION__, err));
++				goto exit_mutex_unlock;
++			}
++		} else {
++			DHD_PNO(("No change in flag - %d\n", old_flag));
++		}
++	} else {
++		DHD_PNO(("Gscan not started\n"));
++	}
++exit_mutex_unlock:
++	mutex_unlock(&_pno_state->pno_mutex);
++exit:
++	return err;
++}
++
++/* Cleanup any consumed results
++ * Return TRUE if all results consumed, else FALSE
++ */
++int dhd_gscan_batch_cache_cleanup(dhd_pub_t *dhd)
++{
++	int ret = 0;
++	dhd_pno_params_t *params;
++	struct dhd_pno_gscan_params *gscan_params;
++	dhd_pno_status_info_t *_pno_state;
++	gscan_results_cache_t *iter, *tmp;
++
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++	gscan_params = &params->params_gscan;
++	iter = gscan_params->gscan_batch_cache;
++
++	while (iter) {
++		if (iter->tot_consumed == iter->tot_count) {
++			tmp = iter->next;
++			kfree(iter);
++			iter = tmp;
++		} else
++			break;
++	}
++	gscan_params->gscan_batch_cache = iter;
++	ret = (iter == NULL);
++	return ret;
++}
++
++static int
++_dhd_pno_get_gscan_batch_from_fw(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	uint32 timestamp = 0, ts = 0, i, j, timediff;
++	dhd_pno_params_t *params;
++	dhd_pno_status_info_t *_pno_state;
++	wl_pfn_lnet_info_v2_t *plnetinfo;
++	struct dhd_pno_gscan_params *gscan_params;
++	wl_pfn_lscanresults_v2_t *plbestnet = NULL;
++	gscan_results_cache_t *iter, *tail;
++	wifi_gscan_result_t *result;
++	uint8 *nAPs_per_scan = NULL;
++	uint8 num_scans_in_cur_iter;
++	uint16 count;
++	struct osl_timespec tm_spec;
++
++	NULL_CHECK(dhd, "dhd is NULL\n", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n", __FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++	if (!(_pno_state->pno_mode & DHD_PNO_GSCAN_MODE)) {
++		DHD_ERROR(("%s: GSCAN is not enabled\n", __FUNCTION__));
++		goto exit;
++	}
++	gscan_params = &params->params_gscan;
++	nAPs_per_scan = (uint8 *) MALLOC(dhd->osh, gscan_params->mscan);
++
++	if (!nAPs_per_scan) {
++		DHD_ERROR(("%s :Out of memory!! Cant malloc %d bytes\n", __FUNCTION__,
++		gscan_params->mscan));
++		err = BCME_NOMEM;
++		goto exit;
++	}
++
++	plbestnet = (wl_pfn_lscanresults_v2_t *)MALLOC(dhd->osh, PNO_BESTNET_LEN);
++	if (!plbestnet) {
++		DHD_ERROR(("%s :Out of memory!! Cant malloc %d bytes\n", __FUNCTION__,
++		      PNO_BESTNET_LEN));
++		err = BCME_NOMEM;
++		goto exit;
++	}
++
++	mutex_lock(&_pno_state->pno_mutex);
++
++	dhd_gscan_clear_all_batch_results(dhd);
++
++	if (!(_pno_state->pno_mode & DHD_PNO_GSCAN_MODE)) {
++		DHD_ERROR(("%s : GSCAN is not enabled\n", __FUNCTION__));
++		goto exit_mutex_unlock;
++	}
++
++	timediff = gscan_params->scan_fr * 1000;
++	timediff = timediff >> 1;
++
++	/* Ok, now lets start getting results from the FW */
++	plbestnet->status = PFN_INCOMPLETE;
++	tail = gscan_params->gscan_batch_cache;
++	while (plbestnet->status != PFN_COMPLETE) {
++		memset(plbestnet, 0, PNO_BESTNET_LEN);
++		err = dhd_iovar(dhd, 0, "pfnlbest", NULL, 0, (char *)plbestnet, PNO_BESTNET_LEN,
++				FALSE);
++		if (err < 0) {
++			DHD_ERROR(("%s : Cannot get all the batch results, err :%d\n",
++				__FUNCTION__, err));
++			goto exit_mutex_unlock;
++		}
++		osl_get_monotonic_boottime(&tm_spec);
++		DHD_PNO(("ver %d, status : %d, count %d\n", plbestnet->version,
++			plbestnet->status, plbestnet->count));
++		if (plbestnet->version != PFN_SCANRESULT_VERSION) {
++			err = BCME_VERSION;
++			DHD_ERROR(("bestnet version(%d) is mismatch with Driver version(%d)\n",
++				plbestnet->version, PFN_SCANRESULT_VERSION));
++			goto exit_mutex_unlock;
++		}
++		if (plbestnet->count == 0) {
++			DHD_PNO(("No more batch results\n"));
++			goto exit_mutex_unlock;
++		}
++		num_scans_in_cur_iter = 0;
++		timestamp = plbestnet->netinfo[0].timestamp;
++		/* find out how many scans' results did we get in this batch of FW results */
++		for (i = 0, count = 0; i < plbestnet->count; i++, count++) {
++			plnetinfo = &plbestnet->netinfo[i];
++			/* Unlikely to happen, but just in case the results from
++			 * FW doesnt make sense..... Assume its part of one single scan
++			 */
++			if (num_scans_in_cur_iter >= gscan_params->mscan) {
++				num_scans_in_cur_iter = 0;
++				count = plbestnet->count;
++				break;
++			}
++			if (TIME_DIFF_MS(timestamp, plnetinfo->timestamp) > timediff) {
++				nAPs_per_scan[num_scans_in_cur_iter] = count;
++				count = 0;
++				num_scans_in_cur_iter++;
++			}
++			timestamp = plnetinfo->timestamp;
++		}
++		if (num_scans_in_cur_iter < gscan_params->mscan) {
++			nAPs_per_scan[num_scans_in_cur_iter] = count;
++			num_scans_in_cur_iter++;
++		}
++
++		DHD_PNO(("num_scans_in_cur_iter %d\n", num_scans_in_cur_iter));
++		plnetinfo = &plbestnet->netinfo[0];
++
++		for (i = 0; i < num_scans_in_cur_iter; i++) {
++			iter = (gscan_results_cache_t *)
++			kmalloc(((nAPs_per_scan[i] - 1) * sizeof(wifi_gscan_result_t)) +
++			              sizeof(gscan_results_cache_t), GFP_KERNEL);
++			if (!iter) {
++				DHD_ERROR(("%s :Out of memory!! Cant malloc %d bytes\n",
++				 __FUNCTION__, gscan_params->mscan));
++				err = BCME_NOMEM;
++				goto exit_mutex_unlock;
++			}
++			/* Need this check because the new set of results from FW
++			 * maybe a continuation of previous sets' scan results
++			 */
++			if (TIME_DIFF_MS(ts, plnetinfo->timestamp) > timediff) {
++				iter->scan_id = ++gscan_params->scan_id;
++			} else {
++				iter->scan_id = gscan_params->scan_id;
++			}
++			DHD_PNO(("scan_id %d tot_count %d ch_bucket %x\n",
++				gscan_params->scan_id, nAPs_per_scan[i],
++				plbestnet->scan_ch_buckets[i]));
++			iter->tot_count = nAPs_per_scan[i];
++			iter->scan_ch_bucket = plbestnet->scan_ch_buckets[i];
++			iter->tot_consumed = 0;
++			iter->flag = 0;
++			if (plnetinfo->flags & PFN_PARTIAL_SCAN_MASK) {
++				DHD_PNO(("This scan is aborted\n"));
++				iter->flag = (ENABLE << PNO_STATUS_ABORT);
++			} else if (gscan_params->reason) {
++				iter->flag = (ENABLE << gscan_params->reason);
++			}
++
++			if (!tail) {
++				gscan_params->gscan_batch_cache = iter;
++			} else {
++				tail->next = iter;
++			}
++			tail = iter;
++			iter->next = NULL;
++			for (j = 0; j < nAPs_per_scan[i]; j++, plnetinfo++) {
++				result = &iter->results[j];
++
++				result->channel = wf_channel2mhz(plnetinfo->pfnsubnet.channel,
++					(plnetinfo->pfnsubnet.channel <= CH_MAX_2G_CHANNEL?
++					WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G));
++				result->rssi = (int32) plnetinfo->RSSI;
++				/* Info not available & not expected */
++				result->beacon_period = 0;
++				result->capability = 0;
++				result->rtt = (uint64) plnetinfo->rtt0;
++				result->rtt_sd = (uint64) plnetinfo->rtt1;
++				result->ts = convert_fw_rel_time_to_systime(&tm_spec,
++				                  plnetinfo->timestamp);
++				ts = plnetinfo->timestamp;
++				if (plnetinfo->pfnsubnet.SSID_len > DOT11_MAX_SSID_LEN) {
++					DHD_ERROR(("%s: Invalid SSID length %d\n",
++					      __FUNCTION__, plnetinfo->pfnsubnet.SSID_len));
++					plnetinfo->pfnsubnet.SSID_len = DOT11_MAX_SSID_LEN;
++				}
++				memcpy(result->ssid, plnetinfo->pfnsubnet.u.SSID,
++					plnetinfo->pfnsubnet.SSID_len);
++				result->ssid[plnetinfo->pfnsubnet.SSID_len] = '\0';
++				memcpy(&result->macaddr, &plnetinfo->pfnsubnet.BSSID,
++				    ETHER_ADDR_LEN);
++
++				DHD_PNO(("\tSSID : "));
++				DHD_PNO(("\n"));
++				DHD_PNO(("\tBSSID: %02x:%02x:%02x:%02x:%02x:%02x\n",
++					result->macaddr.octet[0],
++					result->macaddr.octet[1],
++					result->macaddr.octet[2],
++					result->macaddr.octet[3],
++					result->macaddr.octet[4],
++					result->macaddr.octet[5]));
++				DHD_PNO(("\tchannel: %d, RSSI: %d, timestamp: %d ms\n",
++					plnetinfo->pfnsubnet.channel,
++					plnetinfo->RSSI, plnetinfo->timestamp));
++				DHD_PNO(("\tRTT0 : %d, RTT1: %d\n",
++				    plnetinfo->rtt0, plnetinfo->rtt1));
++
++			}
++		}
++	}
++exit_mutex_unlock:
++	mutex_unlock(&_pno_state->pno_mutex);
++exit:
++	params->params_gscan.get_batch_flag = GSCAN_BATCH_RETRIEVAL_COMPLETE;
++	smp_wmb();
++	wake_up_interruptible(&_pno_state->batch_get_wait);
++	if (nAPs_per_scan) {
++		MFREE(dhd->osh, nAPs_per_scan, gscan_params->mscan * sizeof(uint8));
++	}
++	if (plbestnet) {
++		MFREE(dhd->osh, plbestnet, PNO_BESTNET_LEN);
++	}
++	DHD_PNO(("Batch retrieval done!\n"));
++	return err;
++}
++#endif /* GSCAN_SUPPORT */
++
++#if defined(GSCAN_SUPPORT) || defined(DHD_GET_VALID_CHANNELS)
++void *
++dhd_pno_get_gscan(dhd_pub_t *dhd, dhd_pno_gscan_cmd_cfg_t type,
++         void *info, uint32 *len)
++{
++	void *ret = NULL;
++	dhd_pno_gscan_capabilities_t *ptr;
++	dhd_pno_ssid_t *ssid_elem;
++	dhd_pno_params_t *_params;
++	dhd_epno_ssid_cfg_t *epno_cfg;
++	dhd_pno_status_info_t *_pno_state;
++
++
++	if (!dhd || !dhd->pno_state) {
++		DHD_ERROR(("NULL POINTER : %s\n", __FUNCTION__));
++		return NULL;
++	}
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++	if (!len) {
++		DHD_ERROR(("%s: len is NULL\n", __FUNCTION__));
++		return NULL;
++	}
++
++	switch (type) {
++		case DHD_PNO_GET_CAPABILITIES:
++			ptr = (dhd_pno_gscan_capabilities_t *)
++			kmalloc(sizeof(dhd_pno_gscan_capabilities_t), GFP_KERNEL);
++			if (!ptr)
++				break;
++			/* Hardcoding these values for now, need to get
++			 * these values from FW, will change in a later check-in
++			 */
++			ptr->max_scan_cache_size = GSCAN_MAX_AP_CACHE;
++			ptr->max_scan_buckets = GSCAN_MAX_CH_BUCKETS;
++			ptr->max_ap_cache_per_scan = GSCAN_MAX_AP_CACHE_PER_SCAN;
++			ptr->max_scan_reporting_threshold = 100;
++			ptr->max_hotlist_aps = PFN_HOTLIST_MAX_NUM_APS;
++			ptr->max_epno_ssid_crc32 = MAX_EPNO_SSID_NUM;
++			ptr->max_epno_hidden_ssid = MAX_EPNO_HIDDEN_SSID;
++			ptr->max_white_list_ssid = MAX_WHITELIST_SSID;
++			ret = (void *)ptr;
++			*len = sizeof(dhd_pno_gscan_capabilities_t);
++			break;
++#ifdef GSCAN_SUPPORT
++		case DHD_PNO_GET_BATCH_RESULTS:
++			ret = dhd_get_gscan_batch_results(dhd, len);
++			break;
++#endif /* GSCAN_SUPPORT */
++		case DHD_PNO_GET_CHANNEL_LIST:
++			if (info) {
++				uint16 ch_list[WL_NUMCHANNELS];
++				uint32 *p, mem_needed, i;
++				int32 err, nchan = WL_NUMCHANNELS;
++				uint32 *gscan_band = (uint32 *) info;
++				uint8 band = 0;
++
++				/* No band specified?, nothing to do */
++				if ((*gscan_band & GSCAN_BAND_MASK) == 0) {
++					DHD_PNO(("No band specified\n"));
++					*len = 0;
++					break;
++				}
++
++				/* HAL and DHD use different bits for 2.4G and
++				 * 5G in bitmap. Hence translating it here...
++				 */
++				if (*gscan_band & GSCAN_BG_BAND_MASK) {
++					band |= WLC_BAND_2G;
++				}
++				if (*gscan_band & GSCAN_A_BAND_MASK) {
++					band |= WLC_BAND_5G;
++				}
++
++				err = _dhd_pno_get_channels(dhd, ch_list, &nchan,
++				                          (band & GSCAN_ABG_BAND_MASK),
++				                          !(*gscan_band & GSCAN_DFS_MASK));
++
++				if (err < 0) {
++					DHD_ERROR(("%s: failed to get valid channel list\n",
++						__FUNCTION__));
++					*len = 0;
++				} else {
++					mem_needed = sizeof(uint32) * nchan;
++					p = (uint32 *) kmalloc(mem_needed, GFP_KERNEL);
++					if (!p) {
++						DHD_ERROR(("%s: Unable to malloc %d bytes\n",
++							__FUNCTION__, mem_needed));
++						break;
++					}
++					for (i = 0; i < nchan; i++) {
++						p[i] = wf_channel2mhz(ch_list[i],
++							(ch_list[i] <= CH_MAX_2G_CHANNEL?
++							WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G));
++					}
++					ret = p;
++					*len = mem_needed;
++				}
++			} else {
++				*len = 0;
++				DHD_ERROR(("%s: info buffer is NULL\n", __FUNCTION__));
++			}
++			break;
++		case DHD_PNO_GET_NEW_EPNO_SSID_ELEM:
++			epno_cfg = &_params->params_gscan.epno_cfg;
++			if (epno_cfg->num_epno_ssid >=
++			           MAX_EPNO_SSID_NUM) {
++				DHD_ERROR(("Excessive number of ePNO SSIDs programmed %d\n",
++				     epno_cfg->num_epno_ssid));
++				return NULL;
++			}
++			if (!epno_cfg->num_epno_ssid) {
++				INIT_LIST_HEAD(&epno_cfg->epno_ssid_list);
++			}
++			ssid_elem = kzalloc(sizeof(dhd_pno_ssid_t), GFP_KERNEL);
++			if (!ssid_elem) {
++				DHD_ERROR(("EPNO ssid: cannot alloc %zd bytes",
++				   sizeof(dhd_pno_ssid_t)));
++				return NULL;
++			}
++			epno_cfg->num_epno_ssid++;
++			list_add_tail(&ssid_elem->list, &epno_cfg->epno_ssid_list);
++			ret = ssid_elem;
++			break;
++
++		default:
++			DHD_ERROR(("%s: Unrecognized cmd type - %d\n", __FUNCTION__, type));
++			break;
++	}
++
++	return ret;
++
++}
++#endif /* GSCAN_SUPPORT || DHD_GET_VALID_CHANNELS */
++
++static int
++_dhd_pno_get_for_batch(dhd_pub_t *dhd, char *buf, int bufsize, int reason)
++{
++	int err = BCME_OK;
++	int i, j;
++	uint32 timestamp = 0;
++	dhd_pno_params_t *_params = NULL;
++	dhd_pno_status_info_t *_pno_state = NULL;
++	wl_pfn_lscanresults_v2_t *plbestnet = NULL;
++	wl_pfn_lnet_info_v2_t *plnetinfo;
++	dhd_pno_bestnet_entry_t *pbestnet_entry;
++	dhd_pno_best_header_t *pbestnetheader = NULL;
++	dhd_pno_scan_results_t *pscan_results = NULL, *siter, *snext;
++	bool allocate_header = FALSE;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++
++	if (!dhd_support_sta_mode(dhd)) {
++		err = BCME_BADOPTION;
++		goto exit_no_unlock;
++	}
++
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n", __FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit_no_unlock;
++	}
++
++	if (!(_pno_state->pno_mode & DHD_PNO_BATCH_MODE)) {
++		DHD_ERROR(("%s: Batching SCAN mode is not enabled\n", __FUNCTION__));
++		goto exit_no_unlock;
++	}
++	mutex_lock(&_pno_state->pno_mutex);
++	_params = &_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS];
++	if (buf && bufsize) {
++		if (!list_empty(&_params->params_batch.get_batch.expired_scan_results_list)) {
++			/* need to check whether we have cashed data or not */
++			DHD_PNO(("%s: have cashed batching data in Driver\n",
++				__FUNCTION__));
++			/* convert to results format */
++			goto convert_format;
++		} else {
++			/* this is a first try to get batching results */
++			if (!list_empty(&_params->params_batch.get_batch.scan_results_list)) {
++				/* move the scan_results_list to expired_scan_results_lists */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++				list_for_each_entry_safe(siter, snext,
++					&_params->params_batch.get_batch.scan_results_list, list) {
++					list_move_tail(&siter->list,
++					&_params->params_batch.get_batch.expired_scan_results_list);
++				}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++				_params->params_batch.get_batch.top_node_cnt = 0;
++				_params->params_batch.get_batch.expired_tot_scan_cnt =
++					_params->params_batch.get_batch.tot_scan_cnt;
++				_params->params_batch.get_batch.tot_scan_cnt = 0;
++				goto convert_format;
++			}
++		}
++	}
++	/* create dhd_pno_scan_results_t whenever we got event WLC_E_PFN_BEST_BATCHING */
++	pscan_results = (dhd_pno_scan_results_t *)MALLOC(dhd->osh, SCAN_RESULTS_SIZE);
++	if (pscan_results == NULL) {
++		err = BCME_NOMEM;
++		DHD_ERROR(("failed to allocate dhd_pno_scan_results_t\n"));
++		goto exit;
++	}
++	pscan_results->bestnetheader = NULL;
++	pscan_results->cnt_header = 0;
++	/* add the element into list unless total node cnt is less than MAX_NODE_ CNT */
++	if (_params->params_batch.get_batch.top_node_cnt < MAX_NODE_CNT) {
++		list_add(&pscan_results->list, &_params->params_batch.get_batch.scan_results_list);
++		_params->params_batch.get_batch.top_node_cnt++;
++	} else {
++		int _removed_scan_cnt;
++		/* remove oldest one and add new one */
++		DHD_PNO(("%s : Remove oldest node and add new one\n", __FUNCTION__));
++		_removed_scan_cnt = _dhd_pno_clear_all_batch_results(dhd,
++			&_params->params_batch.get_batch.scan_results_list, TRUE);
++		_params->params_batch.get_batch.tot_scan_cnt -= _removed_scan_cnt;
++		list_add(&pscan_results->list, &_params->params_batch.get_batch.scan_results_list);
++
++	}
++	plbestnet = (wl_pfn_lscanresults_v2_t *)MALLOC(dhd->osh, PNO_BESTNET_LEN);
++	if (!(plbestnet))
++	{
++		DHD_ERROR(("(%s) : plbestnet (%p) is NULL\n", __FUNCTION__, (plbestnet)));
++		goto exit;
++	}
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	memset(plbestnet, 0, PNO_BESTNET_LEN);
++	while (plbestnet->status != PFN_COMPLETE) {
++		memset(plbestnet, 0, PNO_BESTNET_LEN);
++		err = dhd_iovar(dhd, 0, "pfnlbest", NULL, 0, (char *)plbestnet, PNO_BESTNET_LEN, 0);
++		if (err < 0) {
++			if (err == BCME_EPERM) {
++				DHD_ERROR(("we cannot get the batching data "
++					"during scanning in firmware, try again\n,"));
++				msleep(500);
++				continue;
++			} else {
++				DHD_ERROR(("%s : failed to execute pfnlbest (err :%d)\n",
++					__FUNCTION__, err));
++				goto exit;
++			}
++		}
++		DHD_PNO(("ver %d, status : %d, count %d\n", plbestnet->version,
++			plbestnet->status, plbestnet->count));
++		if (plbestnet->version != PFN_SCANRESULT_VERSION) {
++			err = BCME_VERSION;
++			DHD_ERROR(("bestnet version(%d) is mismatch with Driver version(%d)\n",
++				plbestnet->version, PFN_SCANRESULT_VERSION));
++			goto exit;
++		}
++		plnetinfo = plbestnet->netinfo;
++		for (i = 0; i < plbestnet->count; i++) {
++			pbestnet_entry = (dhd_pno_bestnet_entry_t *)
++			MALLOC(dhd->osh, BESTNET_ENTRY_SIZE);
++			if (pbestnet_entry == NULL) {
++				err = BCME_NOMEM;
++				DHD_ERROR(("failed to allocate dhd_pno_bestnet_entry\n"));
++				goto exit;
++			}
++			memset(pbestnet_entry, 0, BESTNET_ENTRY_SIZE);
++			pbestnet_entry->recorded_time = jiffies; /* record the current time */
++			/* create header for the first entry */
++			allocate_header = (i == 0)? TRUE : FALSE;
++			/* check whether the new generation is started or not */
++			if (timestamp && (TIME_DIFF(timestamp, plnetinfo->timestamp)
++				> TIME_MIN_DIFF))
++				allocate_header = TRUE;
++			timestamp = plnetinfo->timestamp;
++			if (allocate_header) {
++				pbestnetheader = (dhd_pno_best_header_t *)
++				MALLOC(dhd->osh, BEST_HEADER_SIZE);
++				if (pbestnetheader == NULL) {
++					err = BCME_NOMEM;
++					if (pbestnet_entry)
++						MFREE(dhd->osh, pbestnet_entry,
++						BESTNET_ENTRY_SIZE);
++					DHD_ERROR(("failed to allocate dhd_pno_bestnet_entry\n"));
++					goto exit;
++				}
++				/* increase total cnt of bestnet header */
++				pscan_results->cnt_header++;
++				/* need to record the reason to call dhd_pno_get_for_bach */
++				if (reason)
++					pbestnetheader->reason = (ENABLE << reason);
++				memset(pbestnetheader, 0, BEST_HEADER_SIZE);
++				/* initialize the head of linked list */
++				INIT_LIST_HEAD(&(pbestnetheader->entry_list));
++				/* link the pbestnet heaer into existed list */
++				if (pscan_results->bestnetheader == NULL)
++					/* In case of header */
++					pscan_results->bestnetheader = pbestnetheader;
++				else {
++					dhd_pno_best_header_t *head = pscan_results->bestnetheader;
++					pscan_results->bestnetheader = pbestnetheader;
++					pbestnetheader->next = head;
++				}
++			}
++			/* fills the best network info */
++			pbestnet_entry->channel = plnetinfo->pfnsubnet.channel;
++			pbestnet_entry->RSSI = plnetinfo->RSSI;
++			if (plnetinfo->flags & PFN_PARTIAL_SCAN_MASK) {
++				/* if RSSI is positive value, we assume that
++				 * this scan is aborted by other scan
++				 */
++				DHD_PNO(("This scan is aborted\n"));
++				pbestnetheader->reason = (ENABLE << PNO_STATUS_ABORT);
++			}
++			pbestnet_entry->rtt0 = plnetinfo->rtt0;
++			pbestnet_entry->rtt1 = plnetinfo->rtt1;
++			pbestnet_entry->timestamp = plnetinfo->timestamp;
++			if (plnetinfo->pfnsubnet.SSID_len > DOT11_MAX_SSID_LEN) {
++				DHD_ERROR(("%s: Invalid SSID length %d: trimming it to max\n",
++				      __FUNCTION__, plnetinfo->pfnsubnet.SSID_len));
++				plnetinfo->pfnsubnet.SSID_len = DOT11_MAX_SSID_LEN;
++			}
++			pbestnet_entry->SSID_len = plnetinfo->pfnsubnet.SSID_len;
++			memcpy(pbestnet_entry->SSID, plnetinfo->pfnsubnet.u.SSID,
++				pbestnet_entry->SSID_len);
++			memcpy(&pbestnet_entry->BSSID, &plnetinfo->pfnsubnet.BSSID, ETHER_ADDR_LEN);
++			/* add the element into list */
++			list_add_tail(&pbestnet_entry->list, &pbestnetheader->entry_list);
++			/* increase best entry count */
++			pbestnetheader->tot_cnt++;
++			pbestnetheader->tot_size += BESTNET_ENTRY_SIZE;
++			DHD_PNO(("Header %d\n", pscan_results->cnt_header - 1));
++			DHD_PNO(("\tSSID : "));
++			for (j = 0; j < plnetinfo->pfnsubnet.SSID_len; j++)
++				DHD_PNO(("%c", plnetinfo->pfnsubnet.u.SSID[j]));
++			DHD_PNO(("\n"));
++			DHD_PNO(("\tBSSID: %02x:%02x:%02x:%02x:%02x:%02x\n",
++				plnetinfo->pfnsubnet.BSSID.octet[0],
++				plnetinfo->pfnsubnet.BSSID.octet[1],
++				plnetinfo->pfnsubnet.BSSID.octet[2],
++				plnetinfo->pfnsubnet.BSSID.octet[3],
++				plnetinfo->pfnsubnet.BSSID.octet[4],
++				plnetinfo->pfnsubnet.BSSID.octet[5]));
++			DHD_PNO(("\tchannel: %d, RSSI: %d, timestamp: %d ms\n",
++				plnetinfo->pfnsubnet.channel,
++				plnetinfo->RSSI, plnetinfo->timestamp));
++			DHD_PNO(("\tRTT0 : %d, RTT1: %d\n", plnetinfo->rtt0, plnetinfo->rtt1));
++			plnetinfo++;
++		}
++	}
++	if (pscan_results->cnt_header == 0) {
++		/* In case that we didn't get any data from the firmware
++		 * Remove the current scan_result list from get_bach.scan_results_list.
++		 */
++		DHD_PNO(("NO BATCH DATA from Firmware, Delete current SCAN RESULT LIST\n"));
++		list_del(&pscan_results->list);
++		MFREE(dhd->osh, pscan_results, SCAN_RESULTS_SIZE);
++		_params->params_batch.get_batch.top_node_cnt--;
++	} else {
++		/* increase total scan count using current scan count */
++		_params->params_batch.get_batch.tot_scan_cnt += pscan_results->cnt_header;
++	}
++
++	if (buf && bufsize) {
++		/* This is a first try to get batching results */
++		if (!list_empty(&_params->params_batch.get_batch.scan_results_list)) {
++			/* move the scan_results_list to expired_scan_results_lists */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++			list_for_each_entry_safe(siter, snext,
++				&_params->params_batch.get_batch.scan_results_list, list) {
++				list_move_tail(&siter->list,
++					&_params->params_batch.get_batch.expired_scan_results_list);
++			}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++			/* reset gloval values after  moving to expired list */
++			_params->params_batch.get_batch.top_node_cnt = 0;
++			_params->params_batch.get_batch.expired_tot_scan_cnt =
++				_params->params_batch.get_batch.tot_scan_cnt;
++			_params->params_batch.get_batch.tot_scan_cnt = 0;
++		}
++convert_format:
++		err = _dhd_pno_convert_format(dhd, &_params->params_batch, buf, bufsize);
++		if (err < 0) {
++			DHD_ERROR(("failed to convert the data into upper layer format\n"));
++			goto exit;
++		}
++	}
++exit:
++	if (plbestnet)
++		MFREE(dhd->osh, plbestnet, PNO_BESTNET_LEN);
++	if (_params) {
++		_params->params_batch.get_batch.buf = NULL;
++		_params->params_batch.get_batch.bufsize = 0;
++		_params->params_batch.get_batch.bytes_written = err;
++	}
++	mutex_unlock(&_pno_state->pno_mutex);
++exit_no_unlock:
++	if (waitqueue_active((struct wait_queue_head *)&_pno_state->get_batch_done.wait))
++		complete(&_pno_state->get_batch_done);
++	return err;
++}
++
++static void
++_dhd_pno_get_batch_handler(struct work_struct *work)
++{
++	dhd_pno_status_info_t *_pno_state;
++	dhd_pub_t *dhd;
++	struct dhd_pno_batch_params *params_batch;
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	_pno_state = container_of(work, struct dhd_pno_status_info, work);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	dhd = _pno_state->dhd;
++	if (dhd == NULL) {
++		DHD_ERROR(("%s : dhd is NULL\n", __FUNCTION__));
++		return;
++	}
++
++#ifdef GSCAN_SUPPORT
++	_dhd_pno_get_gscan_batch_from_fw(dhd);
++#endif /* GSCAN_SUPPORT */
++	if (_pno_state->pno_mode & DHD_PNO_BATCH_MODE) {
++		params_batch = &_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS].params_batch;
++
++		_dhd_pno_get_for_batch(dhd, params_batch->get_batch.buf,
++			params_batch->get_batch.bufsize, params_batch->get_batch.reason);
++	}
++}
++
++int
++dhd_pno_get_for_batch(dhd_pub_t *dhd, char *buf, int bufsize, int reason)
++{
++	int err = BCME_OK;
++	char *pbuf = buf;
++	dhd_pno_status_info_t *_pno_state;
++	struct dhd_pno_batch_params *params_batch;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	if (!dhd_support_sta_mode(dhd)) {
++		err = BCME_BADOPTION;
++		goto exit;
++	}
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n", __FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++	params_batch = &_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS].params_batch;
++#ifdef GSCAN_SUPPORT
++	if (_pno_state->pno_mode & DHD_PNO_GSCAN_MODE) {
++		struct dhd_pno_gscan_params *gscan_params;
++		gscan_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS].params_gscan;
++		gscan_params->reason = reason;
++		err = dhd_retreive_batch_scan_results(dhd);
++		if (err == BCME_OK) {
++			wait_event_interruptible_timeout(_pno_state->batch_get_wait,
++			     is_batch_retrieval_complete(gscan_params),
++			     msecs_to_jiffies(GSCAN_BATCH_GET_MAX_WAIT));
++		}
++	} else
++#endif
++	{
++		if (!(_pno_state->pno_mode & DHD_PNO_BATCH_MODE)) {
++			DHD_ERROR(("%s: Batching SCAN mode is not enabled\n", __FUNCTION__));
++			memset(pbuf, 0, bufsize);
++			pbuf += snprintf(pbuf, bufsize, "scancount=%d\n", 0);
++			snprintf(pbuf, bufsize, "%s", RESULTS_END_MARKER);
++			err = strlen(buf);
++			goto exit;
++		}
++		params_batch->get_batch.buf = buf;
++		params_batch->get_batch.bufsize = bufsize;
++		params_batch->get_batch.reason = reason;
++		params_batch->get_batch.bytes_written = 0;
++		schedule_work(&_pno_state->work);
++		wait_for_completion(&_pno_state->get_batch_done);
++	}
++
++#ifdef GSCAN_SUPPORT
++	if (!(_pno_state->pno_mode & DHD_PNO_GSCAN_MODE))
++#endif
++	err = params_batch->get_batch.bytes_written;
++exit:
++	return err;
++}
++
++int
++dhd_pno_stop_for_batch(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	int mode = 0;
++	int i = 0;
++	dhd_pno_status_info_t *_pno_state;
++	dhd_pno_params_t *_params;
++	wl_pfn_bssid_t *p_pfn_bssid = NULL;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	if (!dhd_support_sta_mode(dhd)) {
++		err = BCME_BADOPTION;
++		goto exit;
++	}
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n",
++			__FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++#ifdef GSCAN_SUPPORT
++	if (_pno_state->pno_mode & DHD_PNO_GSCAN_MODE) {
++		DHD_PNO(("Gscan is ongoing, nothing to stop here\n"));
++		return err;
++	}
++#endif
++
++	if (!(_pno_state->pno_mode & DHD_PNO_BATCH_MODE)) {
++		DHD_ERROR(("%s : PNO BATCH MODE is not enabled\n", __FUNCTION__));
++		goto exit;
++	}
++	_pno_state->pno_mode &= ~DHD_PNO_BATCH_MODE;
++	if (_pno_state->pno_mode & (DHD_PNO_LEGACY_MODE | DHD_PNO_HOTLIST_MODE)) {
++		mode = _pno_state->pno_mode;
++		err = dhd_pno_clean(dhd);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++
++		_pno_state->pno_mode = mode;
++		/* restart Legacy PNO if the Legacy PNO is on */
++		if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) {
++			struct dhd_pno_legacy_params *_params_legacy;
++			_params_legacy =
++				&(_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS].params_legacy);
++			err = dhd_pno_set_legacy_pno(dhd, _params_legacy->scan_fr,
++					_params_legacy->pno_repeat,
++					_params_legacy->pno_freq_expo_max,
++					_params_legacy->chan_list, _params_legacy->nchan);
++			if (err < 0) {
++				DHD_ERROR(("%s : failed to restart legacy PNO scan(err: %d)\n",
++					__FUNCTION__, err));
++				goto exit;
++			}
++		} else if (_pno_state->pno_mode & DHD_PNO_HOTLIST_MODE) {
++			struct dhd_pno_bssid *iter, *next;
++			_params = &(_pno_state->pno_params_arr[INDEX_OF_HOTLIST_PARAMS]);
++			p_pfn_bssid = kzalloc(sizeof(wl_pfn_bssid_t) *
++				_params->params_hotlist.nbssid, GFP_KERNEL);
++			if (p_pfn_bssid == NULL) {
++				DHD_ERROR(("%s : failed to allocate wl_pfn_bssid_t array"
++					" (count: %d)",
++					__FUNCTION__, _params->params_hotlist.nbssid));
++				err = BCME_ERROR;
++				_pno_state->pno_mode &= ~DHD_PNO_HOTLIST_MODE;
++				goto exit;
++			}
++			i = 0;
++			/* convert dhd_pno_bssid to wl_pfn_bssid */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++			list_for_each_entry_safe(iter, next,
++				&_params->params_hotlist.bssid_list, list) {
++				memcpy(&p_pfn_bssid[i].macaddr, &iter->macaddr, ETHER_ADDR_LEN);
++				p_pfn_bssid[i].flags = iter->flags;
++				i++;
++			}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++			err = dhd_pno_set_for_hotlist(dhd, p_pfn_bssid, &_params->params_hotlist);
++			if (err < 0) {
++				_pno_state->pno_mode &= ~DHD_PNO_HOTLIST_MODE;
++				DHD_ERROR(("%s : failed to restart hotlist scan(err: %d)\n",
++					__FUNCTION__, err));
++				goto exit;
++			}
++		}
++	} else {
++		err = dhd_pno_clean(dhd);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++	}
++exit:
++	_params = &_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS];
++	_dhd_pno_reinitialize_prof(dhd, _params, DHD_PNO_BATCH_MODE);
++	kfree(p_pfn_bssid);
++	return err;
++}
++
++int
++dhd_pno_set_for_hotlist(dhd_pub_t *dhd, wl_pfn_bssid_t *p_pfn_bssid,
++	struct dhd_pno_hotlist_params *hotlist_params)
++{
++	int err = BCME_OK;
++	int i;
++	uint16 _chan_list[WL_NUMCHANNELS];
++	int rem_nchan = 0;
++	int tot_nchan = 0;
++	int mode = 0;
++	dhd_pno_params_t *_params;
++	dhd_pno_params_t *_params2;
++	struct dhd_pno_bssid *_pno_bssid;
++	dhd_pno_status_info_t *_pno_state;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	NULL_CHECK(hotlist_params, "hotlist_params is NULL", err);
++	NULL_CHECK(p_pfn_bssid, "p_pfn_bssid is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	if (!dhd_support_sta_mode(dhd)) {
++		err = BCME_BADOPTION;
++		goto exit;
++	}
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n", __FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++	_params = &_pno_state->pno_params_arr[INDEX_OF_HOTLIST_PARAMS];
++	if (!(_pno_state->pno_mode & DHD_PNO_HOTLIST_MODE)) {
++		_pno_state->pno_mode |= DHD_PNO_HOTLIST_MODE;
++		err = _dhd_pno_reinitialize_prof(dhd, _params, DHD_PNO_HOTLIST_MODE);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call _dhd_pno_reinitialize_prof\n",
++				__FUNCTION__));
++			goto exit;
++		}
++	}
++	_params->params_batch.nchan = hotlist_params->nchan;
++	_params->params_batch.scan_fr = hotlist_params->scan_fr;
++	if (hotlist_params->nchan)
++		memcpy(_params->params_hotlist.chan_list, hotlist_params->chan_list,
++			sizeof(_params->params_hotlist.chan_list));
++	memset(_chan_list, 0, sizeof(_chan_list));
++
++	rem_nchan = ARRAYSIZE(hotlist_params->chan_list) - hotlist_params->nchan;
++	if (hotlist_params->band == WLC_BAND_2G || hotlist_params->band == WLC_BAND_5G) {
++		/* get a valid channel list based on band B or A */
++		err = _dhd_pno_get_channels(dhd,
++		&_params->params_hotlist.chan_list[hotlist_params->nchan],
++		&rem_nchan, hotlist_params->band, FALSE);
++		if (err < 0) {
++			DHD_ERROR(("%s: failed to get valid channel list(band : %d)\n",
++				__FUNCTION__, hotlist_params->band));
++			goto exit;
++		}
++		/* now we need to update nchan because rem_chan has valid channel count */
++		_params->params_hotlist.nchan += rem_nchan;
++		/* need to sort channel list */
++		sort(_params->params_hotlist.chan_list, _params->params_hotlist.nchan,
++			sizeof(_params->params_hotlist.chan_list[0]), _dhd_pno_cmpfunc, NULL);
++	}
++#ifdef PNO_DEBUG
++{
++		int i;
++		DHD_PNO(("Channel list : "));
++		for (i = 0; i < _params->params_batch.nchan; i++) {
++			DHD_PNO(("%d ", _params->params_batch.chan_list[i]));
++		}
++		DHD_PNO(("\n"));
++}
++#endif
++	if (_params->params_hotlist.nchan) {
++		/* copy the channel list into local array */
++		memcpy(_chan_list, _params->params_hotlist.chan_list,
++			sizeof(_chan_list));
++		tot_nchan = _params->params_hotlist.nchan;
++	}
++	if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) {
++			DHD_PNO(("PNO SSID is on progress in firmware\n"));
++			/* store current pno_mode before disabling pno */
++			mode = _pno_state->pno_mode;
++			err = _dhd_pno_enable(dhd, PNO_OFF);
++			if (err < 0) {
++				DHD_ERROR(("%s : failed to disable PNO\n", __FUNCTION__));
++				goto exit;
++			}
++			/* restore the previous mode */
++			_pno_state->pno_mode = mode;
++			/* Use the superset for channelist between two mode */
++			_params2 = &(_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS]);
++			if (_params2->params_legacy.nchan > 0 &&
++				_params->params_hotlist.nchan > 0) {
++				err = _dhd_pno_chan_merge(_chan_list, &tot_nchan,
++					&_params2->params_legacy.chan_list[0],
++					_params2->params_legacy.nchan,
++					&_params->params_hotlist.chan_list[0],
++					_params->params_hotlist.nchan);
++				if (err < 0) {
++					DHD_ERROR(("%s : failed to merge channel list"
++						"between legacy and hotlist\n",
++						__FUNCTION__));
++					goto exit;
++				}
++			}
++
++	}
++
++	INIT_LIST_HEAD(&(_params->params_hotlist.bssid_list));
++
++	err = _dhd_pno_add_bssid(dhd, p_pfn_bssid, hotlist_params->nbssid);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to call _dhd_pno_add_bssid(err :%d)\n",
++			__FUNCTION__, err));
++		goto exit;
++	}
++	if ((err = _dhd_pno_set(dhd, _params, DHD_PNO_HOTLIST_MODE)) < 0) {
++		DHD_ERROR(("%s : failed to set call pno_set (err %d) in firmware\n",
++			__FUNCTION__, err));
++		goto exit;
++	}
++	if (tot_nchan > 0) {
++		if ((err = _dhd_pno_cfg(dhd, _chan_list, tot_nchan)) < 0) {
++			DHD_ERROR(("%s : failed to set call pno_cfg (err %d) in firmware\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++	}
++	for (i = 0; i < hotlist_params->nbssid; i++) {
++		_pno_bssid = kzalloc(sizeof(struct dhd_pno_bssid), GFP_KERNEL);
++		NULL_CHECK(_pno_bssid, "_pfn_bssid is NULL", err);
++		memcpy(&_pno_bssid->macaddr, &p_pfn_bssid[i].macaddr, ETHER_ADDR_LEN);
++		_pno_bssid->flags = p_pfn_bssid[i].flags;
++		list_add_tail(&_pno_bssid->list, &_params->params_hotlist.bssid_list);
++	}
++	_params->params_hotlist.nbssid = hotlist_params->nbssid;
++	if (_pno_state->pno_status == DHD_PNO_DISABLED) {
++		if ((err = _dhd_pno_enable(dhd, PNO_ON)) < 0)
++			DHD_ERROR(("%s : failed to enable PNO\n", __FUNCTION__));
++	}
++exit:
++	/* clear mode in case of error */
++	if (err < 0)
++		_pno_state->pno_mode &= ~DHD_PNO_HOTLIST_MODE;
++	return err;
++}
++
++int
++dhd_pno_stop_for_hotlist(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	uint32 mode = 0;
++	dhd_pno_status_info_t *_pno_state;
++	dhd_pno_params_t *_params;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n",
++			__FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++	if (!(_pno_state->pno_mode & DHD_PNO_HOTLIST_MODE)) {
++		DHD_ERROR(("%s : Hotlist MODE is not enabled\n",
++			__FUNCTION__));
++		goto exit;
++	}
++	_pno_state->pno_mode &= ~DHD_PNO_BATCH_MODE;
++
++	if (_pno_state->pno_mode & (DHD_PNO_LEGACY_MODE | DHD_PNO_BATCH_MODE)) {
++		/* retrieve the batching data from firmware into host */
++		dhd_pno_get_for_batch(dhd, NULL, 0, PNO_STATUS_DISABLE);
++		/* save current pno_mode before calling dhd_pno_clean */
++		mode = _pno_state->pno_mode;
++		err = dhd_pno_clean(dhd);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++		/* restore previos pno mode */
++		_pno_state->pno_mode = mode;
++		if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) {
++			/* restart Legacy PNO Scan */
++			struct dhd_pno_legacy_params *_params_legacy;
++			_params_legacy =
++			&(_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS].params_legacy);
++
++			err = dhd_pno_set_legacy_pno(dhd, _params_legacy->scan_fr,
++				_params_legacy->pno_repeat, _params_legacy->pno_freq_expo_max,
++				_params_legacy->chan_list, _params_legacy->nchan);
++			if (err < 0) {
++				DHD_ERROR(("%s : failed to restart legacy PNO scan(err: %d)\n",
++					__FUNCTION__, err));
++				goto exit;
++			}
++		} else if (_pno_state->pno_mode & DHD_PNO_BATCH_MODE) {
++			/* restart Batching Scan */
++			_params = &(_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS]);
++			/* restart BATCH SCAN */
++			err = dhd_pno_set_for_batch(dhd, &_params->params_batch);
++			if (err < 0) {
++				_pno_state->pno_mode &= ~DHD_PNO_BATCH_MODE;
++				DHD_ERROR(("%s : failed to restart batch scan(err: %d)\n",
++					__FUNCTION__,  err));
++				goto exit;
++			}
++		}
++	} else {
++		err = dhd_pno_clean(dhd);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++	}
++exit:
++	return err;
++}
++
++#ifdef GSCAN_SUPPORT
++int
++dhd_retreive_batch_scan_results(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	dhd_pno_status_info_t *_pno_state;
++	dhd_pno_params_t *_params;
++	struct dhd_pno_batch_params *params_batch;
++
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++
++	params_batch = &_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS].params_batch;
++	if (_params->params_gscan.get_batch_flag == GSCAN_BATCH_RETRIEVAL_COMPLETE) {
++		DHD_PNO(("Retreive batch results\n"));
++		params_batch->get_batch.buf = NULL;
++		params_batch->get_batch.bufsize = 0;
++		params_batch->get_batch.reason = PNO_STATUS_EVENT;
++		_params->params_gscan.get_batch_flag = GSCAN_BATCH_RETRIEVAL_IN_PROGRESS;
++		smp_wmb();
++		schedule_work(&_pno_state->work);
++	} else {
++		DHD_PNO(("%s : WLC_E_PFN_BEST_BATCHING retrieval"
++			"already in progress, will skip\n", __FUNCTION__));
++		err = BCME_ERROR;
++	}
++
++	return err;
++}
++
++void
++dhd_gscan_hotlist_cache_cleanup(dhd_pub_t *dhd, hotlist_type_t type)
++{
++	dhd_pno_status_info_t *_pno_state = PNO_GET_PNOSTATE(dhd);
++	struct dhd_pno_gscan_params *gscan_params;
++	gscan_results_cache_t *iter, *tmp;
++
++	if (!_pno_state) {
++		return;
++	}
++	gscan_params = &(_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS].params_gscan);
++
++	if (type == HOTLIST_FOUND) {
++		iter = gscan_params->gscan_hotlist_found;
++		gscan_params->gscan_hotlist_found = NULL;
++	} else {
++		iter = gscan_params->gscan_hotlist_lost;
++		gscan_params->gscan_hotlist_lost = NULL;
++	}
++
++	while (iter) {
++		tmp = iter->next;
++		kfree(iter);
++		iter = tmp;
++	}
++
++	return;
++}
++
++void *
++dhd_process_full_gscan_result(dhd_pub_t *dhd, const void *data, uint32 len, int *size)
++{
++	wl_bss_info_t *bi = NULL;
++	wl_gscan_result_t *gscan_result;
++	wifi_gscan_full_result_t *result = NULL;
++	u32 bi_length = 0;
++	uint8 channel;
++	uint32 mem_needed;
++	struct osl_timespec ts;
++	u32 bi_ie_length = 0;
++	u32 bi_ie_offset = 0;
++
++	*size = 0;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	gscan_result = (wl_gscan_result_t *)data;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	if (!gscan_result) {
++		DHD_ERROR(("Invalid gscan result (NULL pointer)\n"));
++		goto exit;
++	}
++
++	if ((len < sizeof(*gscan_result)) ||
++	    (len < dtoh32(gscan_result->buflen)) ||
++	    (dtoh32(gscan_result->buflen) >
++	    (sizeof(*gscan_result) + WL_SCAN_IE_LEN_MAX))) {
++		DHD_ERROR(("%s: invalid gscan buflen:%u\n", __FUNCTION__,
++			dtoh32(gscan_result->buflen)));
++		goto exit;
++	}
++
++	bi = &gscan_result->bss_info[0].info;
++	bi_length = dtoh32(bi->length);
++	if (bi_length != (dtoh32(gscan_result->buflen) -
++	       WL_GSCAN_RESULTS_FIXED_SIZE - WL_GSCAN_INFO_FIXED_FIELD_SIZE)) {
++		DHD_ERROR(("Invalid bss_info length %d: ignoring\n", bi_length));
++		goto exit;
++	}
++	bi_ie_offset = dtoh32(bi->ie_offset);
++	bi_ie_length = dtoh32(bi->ie_length);
++	if ((bi_ie_offset + bi_ie_length) > bi_length) {
++		DHD_ERROR(("%s: Invalid ie_length:%u or ie_offset:%u\n",
++			__FUNCTION__, bi_ie_length, bi_ie_offset));
++		goto exit;
++	}
++	if (bi->SSID_len > DOT11_MAX_SSID_LEN) {
++		DHD_ERROR(("%s: Invalid SSID length:%u\n", __FUNCTION__, bi->SSID_len));
++		goto exit;
++	}
++	mem_needed = OFFSETOF(wifi_gscan_full_result_t, ie_data) + bi_ie_length;
++	result = (wifi_gscan_full_result_t *) kmalloc(mem_needed, GFP_KERNEL);
++	if (!result) {
++		DHD_ERROR(("%s Cannot malloc scan result buffer %d bytes\n",
++		  __FUNCTION__, mem_needed));
++		goto exit;
++	}
++	result->scan_ch_bucket = gscan_result->scan_ch_bucket;
++	memcpy(result->fixed.ssid, bi->SSID, bi->SSID_len);
++	result->fixed.ssid[bi->SSID_len] = '\0';
++	channel = wf_chspec_ctlchan(bi->chanspec);
++	result->fixed.channel = wf_channel2mhz(channel,
++		(channel <= CH_MAX_2G_CHANNEL?
++		WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G));
++	result->fixed.rssi = (int32) bi->RSSI;
++	result->fixed.rtt = 0;
++	result->fixed.rtt_sd = 0;
++	osl_get_monotonic_boottime(&ts);
++	result->fixed.ts = (uint64) TIMESPEC_TO_US(ts);
++	result->fixed.beacon_period = dtoh16(bi->beacon_period);
++	result->fixed.capability = dtoh16(bi->capability);
++	result->ie_length = bi_ie_length;
++	memcpy(&result->fixed.macaddr, &bi->BSSID, ETHER_ADDR_LEN);
++	memcpy(result->ie_data, ((uint8 *)bi + bi_ie_offset), bi_ie_length);
++	*size = mem_needed;
++exit:
++	return result;
++}
++
++void *
++dhd_pno_process_epno_result(dhd_pub_t *dhd, const void *data, uint32 event, int *size)
++{
++	dhd_epno_results_t *results = NULL;
++	dhd_pno_status_info_t *_pno_state = PNO_GET_PNOSTATE(dhd);
++	struct dhd_pno_gscan_params *gscan_params;
++	uint32 count, mem_needed = 0, i;
++	uint8 ssid[DOT11_MAX_SSID_LEN + 1];
++	struct ether_addr *bssid;
++
++	*size = 0;
++	if (!_pno_state)
++		return NULL;
++	gscan_params = &(_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS].params_gscan);
++
++	 if (event == WLC_E_PFN_NET_FOUND || event == WLC_E_PFN_NET_LOST) {
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++		 wl_pfn_scanresults_v2_t *pfn_result = (wl_pfn_scanresults_v2_t *)data;
++		 wl_pfn_net_info_v2_t *net;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++		if (pfn_result->version != PFN_SCANRESULT_VERSION) {
++			DHD_ERROR(("%s event %d: Incorrect version %d %d\n", __FUNCTION__, event,
++			          pfn_result->version, PFN_SCANRESULT_VERSION));
++			return NULL;
++		}
++		/* Check if count of pfn results is corrupted */
++		if (pfn_result->count > EVENT_MAX_NETCNT_V2) {
++			DHD_ERROR(("%s event %d: pfn results count %d"
++				"exceeds the max limit\n", __FUNCTION__, event,
++				pfn_result->count));
++			return NULL;
++		}
++
++		count = pfn_result->count;
++		mem_needed = sizeof(dhd_epno_results_t) * count;
++		results = (dhd_epno_results_t *) kmalloc(mem_needed, GFP_KERNEL);
++		if (!results) {
++			DHD_ERROR(("%s: Can't malloc %d bytes for results\n", __FUNCTION__,
++			        mem_needed));
++			return NULL;
++		}
++		for (i = 0; i < count; i++) {
++			net = &pfn_result->netinfo[i];
++			results[i].rssi = net->RSSI;
++			results[i].channel =  wf_channel2mhz(net->pfnsubnet.channel,
++			                  (net->pfnsubnet.channel <= CH_MAX_2G_CHANNEL ?
++			                  WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G));
++			results[i].flags = (event == WLC_E_PFN_NET_FOUND) ?
++			               WL_PFN_SSID_EXT_FOUND: WL_PFN_SSID_EXT_LOST;
++			results[i].ssid_len = min(net->pfnsubnet.SSID_len,
++			               (uint8)DOT11_MAX_SSID_LEN);
++			bssid = &results[i].bssid;
++			memcpy(bssid, &net->pfnsubnet.BSSID, ETHER_ADDR_LEN);
++			if (!net->pfnsubnet.SSID_len) {
++				dhd_pno_idx_to_ssid(gscan_params, &results[i],
++				       net->pfnsubnet.u.index);
++			} else {
++				memcpy(results[i].ssid, net->pfnsubnet.u.SSID, results[i].ssid_len);
++			}
++			memcpy(ssid, results[i].ssid, results[i].ssid_len);
++			ssid[results[i].ssid_len] = '\0';
++			DHD_PNO(("ssid - %s bssid %02x:%02x:%02x:%02x:%02x:%02x "
++			        "ch %d rssi %d flags %d\n", ssid,
++			        bssid->octet[0], bssid->octet[1],
++			        bssid->octet[2], bssid->octet[3],
++			        bssid->octet[4], bssid->octet[5],
++			        results[i].channel, results[i].rssi, results[i].flags));
++		}
++	}
++	*size = mem_needed;
++	return results;
++}
++
++void *
++dhd_handle_hotlist_scan_evt(dhd_pub_t *dhd, const void *event_data,
++        int *send_evt_bytes, hotlist_type_t type)
++{
++	void *ptr = NULL;
++	dhd_pno_status_info_t *_pno_state = PNO_GET_PNOSTATE(dhd);
++	struct dhd_pno_gscan_params *gscan_params;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	wl_pfn_scanresults_v2_t *results = (wl_pfn_scanresults_v2_t *)event_data;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	wifi_gscan_result_t *hotlist_found_array;
++	wl_pfn_net_info_v2_t *plnetinfo;
++	gscan_results_cache_t *gscan_hotlist_cache;
++	int malloc_size = 0, i, total = 0;
++	struct osl_timespec tm_spec;
++
++	gscan_params = &(_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS].params_gscan);
++
++	if ((results->count == 0) || (results->count > EVENT_MAX_NETCNT_V2)) {
++		DHD_ERROR(("%s: wrong result count:%d\n", __FUNCTION__, results->count));
++		*send_evt_bytes = 0;
++		return ptr;
++	}
++
++	osl_get_monotonic_boottime(&tm_spec);
++	malloc_size = sizeof(gscan_results_cache_t) +
++	((results->count - 1) * sizeof(wifi_gscan_result_t));
++	gscan_hotlist_cache = (gscan_results_cache_t *) kmalloc(malloc_size, GFP_KERNEL);
++
++	if (!gscan_hotlist_cache) {
++		DHD_ERROR(("%s Cannot Malloc %d bytes!!\n", __FUNCTION__, malloc_size));
++		*send_evt_bytes = 0;
++		return ptr;
++	}
++
++	if (type == HOTLIST_FOUND) {
++		gscan_hotlist_cache->next = gscan_params->gscan_hotlist_found;
++		gscan_params->gscan_hotlist_found = gscan_hotlist_cache;
++		DHD_PNO(("%s enter, FOUND results count %d\n", __FUNCTION__, results->count));
++	} else {
++		gscan_hotlist_cache->next = gscan_params->gscan_hotlist_lost;
++		gscan_params->gscan_hotlist_lost = gscan_hotlist_cache;
++		DHD_PNO(("%s enter, LOST results count %d\n", __FUNCTION__, results->count));
++	}
++
++	gscan_hotlist_cache->tot_count = results->count;
++	gscan_hotlist_cache->tot_consumed = 0;
++	gscan_hotlist_cache->scan_ch_bucket = results->scan_ch_bucket;
++	plnetinfo = results->netinfo;
++
++	for (i = 0; i < results->count; i++, plnetinfo++) {
++		hotlist_found_array = &gscan_hotlist_cache->results[i];
++		memset(hotlist_found_array, 0, sizeof(wifi_gscan_result_t));
++		hotlist_found_array->channel = wf_channel2mhz(plnetinfo->pfnsubnet.channel,
++			(plnetinfo->pfnsubnet.channel <= CH_MAX_2G_CHANNEL?
++			WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G));
++		hotlist_found_array->rssi = (int32) plnetinfo->RSSI;
++
++		hotlist_found_array->ts =
++		       convert_fw_rel_time_to_systime(&tm_spec, (plnetinfo->timestamp * 1000));
++		if (plnetinfo->pfnsubnet.SSID_len > DOT11_MAX_SSID_LEN) {
++			DHD_ERROR(("Invalid SSID length %d: trimming it to max\n",
++			          plnetinfo->pfnsubnet.SSID_len));
++			plnetinfo->pfnsubnet.SSID_len = DOT11_MAX_SSID_LEN;
++		}
++		memcpy(hotlist_found_array->ssid, plnetinfo->pfnsubnet.u.SSID,
++			plnetinfo->pfnsubnet.SSID_len);
++		hotlist_found_array->ssid[plnetinfo->pfnsubnet.SSID_len] = '\0';
++
++		memcpy(&hotlist_found_array->macaddr, &plnetinfo->pfnsubnet.BSSID, ETHER_ADDR_LEN);
++		DHD_PNO(("\t%s %02x:%02x:%02x:%02x:%02x:%02x rssi %d\n", hotlist_found_array->ssid,
++		hotlist_found_array->macaddr.octet[0],
++		hotlist_found_array->macaddr.octet[1],
++		hotlist_found_array->macaddr.octet[2],
++		hotlist_found_array->macaddr.octet[3],
++		hotlist_found_array->macaddr.octet[4],
++		hotlist_found_array->macaddr.octet[5],
++		hotlist_found_array->rssi));
++	}
++
++
++	if (results->status == PFN_COMPLETE) {
++		ptr = (void *) gscan_hotlist_cache;
++		while (gscan_hotlist_cache) {
++			total += gscan_hotlist_cache->tot_count;
++			gscan_hotlist_cache = gscan_hotlist_cache->next;
++		}
++		*send_evt_bytes =  total * sizeof(wifi_gscan_result_t);
++	}
++
++	return ptr;
++}
++#endif /* GSCAN_SUPPORT */
++int
++dhd_pno_event_handler(dhd_pub_t *dhd, wl_event_msg_t *event, void *event_data)
++{
++	int err = BCME_OK;
++	uint event_type;
++	dhd_pno_status_info_t *_pno_state;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n", __FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++	event_type = ntoh32(event->event_type);
++	DHD_PNO(("%s enter : event_type :%d\n", __FUNCTION__, event_type));
++	switch (event_type) {
++	case WLC_E_PFN_BSSID_NET_FOUND:
++	case WLC_E_PFN_BSSID_NET_LOST:
++		/* TODO : need to implement event logic using generic netlink */
++		break;
++	case WLC_E_PFN_BEST_BATCHING:
++#ifndef GSCAN_SUPPORT
++	{
++		struct dhd_pno_batch_params *params_batch;
++		params_batch = &_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS].params_batch;
++		if (!waitqueue_active((struct wait_queue_head *)&_pno_state->get_batch_done.wait)) {
++			DHD_PNO(("%s : WLC_E_PFN_BEST_BATCHING\n", __FUNCTION__));
++			params_batch->get_batch.buf = NULL;
++			params_batch->get_batch.bufsize = 0;
++			params_batch->get_batch.reason = PNO_STATUS_EVENT;
++			schedule_work(&_pno_state->work);
++		} else
++			DHD_PNO(("%s : WLC_E_PFN_BEST_BATCHING"
++				"will skip this event\n", __FUNCTION__));
++		break;
++	}
++#else
++		break;
++#endif /* !GSCAN_SUPPORT */
++	default:
++		DHD_ERROR(("unknown event : %d\n", event_type));
++	}
++exit:
++	return err;
++}
++
++int dhd_pno_init(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	dhd_pno_status_info_t *_pno_state;
++	char *buf = NULL;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	UNUSED_PARAMETER(_dhd_pno_suspend);
++	if (dhd->pno_state)
++		goto exit;
++	dhd->pno_state = MALLOC(dhd->osh, sizeof(dhd_pno_status_info_t));
++	NULL_CHECK(dhd->pno_state, "failed to create dhd_pno_state", err);
++	memset(dhd->pno_state, 0, sizeof(dhd_pno_status_info_t));
++	/* need to check whether current firmware support batching and hotlist scan */
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	_pno_state->wls_supported = TRUE;
++	_pno_state->dhd = dhd;
++	mutex_init(&_pno_state->pno_mutex);
++	INIT_WORK(&_pno_state->work, _dhd_pno_get_batch_handler);
++	init_completion(&_pno_state->get_batch_done);
++#ifdef GSCAN_SUPPORT
++	init_waitqueue_head(&_pno_state->batch_get_wait);
++#endif /* GSCAN_SUPPORT */
++	buf = kmalloc(WLC_IOCTL_SMLEN, GFP_KERNEL);
++	if (!buf) {
++		DHD_ERROR((":%s buf alloc err.\n", __FUNCTION__));
++		return BCME_NOMEM;
++	}
++	err = dhd_iovar(dhd, 0, "pfnlbest", NULL, 0, buf, WLC_IOCTL_SMLEN,
++			FALSE);
++	if (err == BCME_UNSUPPORTED) {
++		_pno_state->wls_supported = FALSE;
++		DHD_INFO(("Current firmware doesn't support"
++			" Android Location Service\n"));
++	} else {
++		DHD_ERROR(("%s: Support Android Location Service\n",
++			__FUNCTION__));
++	}
++exit:
++	kfree(buf);
++	return err;
++}
++
++int dhd_pno_deinit(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	dhd_pno_status_info_t *_pno_state;
++	dhd_pno_params_t *_params;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	NULL_CHECK(_pno_state, "pno_state is NULL", err);
++	/* may need to free legacy ssid_list */
++	if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) {
++		_params = &_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS];
++		_dhd_pno_reinitialize_prof(dhd, _params, DHD_PNO_LEGACY_MODE);
++	}
++
++#ifdef GSCAN_SUPPORT
++	if (_pno_state->pno_mode & DHD_PNO_GSCAN_MODE) {
++		_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++		mutex_lock(&_pno_state->pno_mutex);
++		dhd_pno_reset_cfg_gscan(_params, _pno_state, GSCAN_FLUSH_ALL_CFG);
++		mutex_unlock(&_pno_state->pno_mutex);
++	}
++#endif /* GSCAN_SUPPORT */
++
++	if (_pno_state->pno_mode & DHD_PNO_BATCH_MODE) {
++		_params = &_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS];
++		/* clear resource if the BATCH MODE is on */
++		_dhd_pno_reinitialize_prof(dhd, _params, DHD_PNO_BATCH_MODE);
++	}
++	cancel_work_sync(&_pno_state->work);
++	MFREE(dhd->osh, _pno_state, sizeof(dhd_pno_status_info_t));
++	dhd->pno_state = NULL;
++	return err;
++}
++#endif /* PNO_SUPPORT */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_pno.h b/module_drivers/drivers/net/wireless/bcmdhd/dhd_pno.h
+new file mode 100644
+index 000000000..7b56c5512
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_pno.h
+@@ -0,0 +1,572 @@
++/*
++ * Header file of Broadcom Dongle Host Driver (DHD)
++ * Prefered Network Offload code and Wi-Fi Location Service(WLS) code.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_pno.h 707287 2017-06-27 06:44:29Z $
++ */
++
++#ifndef __DHD_PNO_H__
++#define __DHD_PNO_H__
++
++#if defined(PNO_SUPPORT)
++#define PNO_TLV_PREFIX			'S'
++#define PNO_TLV_VERSION			'1'
++#define PNO_TLV_SUBTYPE_LEGACY_PNO '2'
++#define PNO_TLV_RESERVED		'0'
++
++#define PNO_BATCHING_SET "SET"
++#define PNO_BATCHING_GET "GET"
++#define PNO_BATCHING_STOP "STOP"
++
++#define PNO_PARAMS_DELIMETER " "
++#define PNO_PARAM_CHANNEL_DELIMETER ","
++#define PNO_PARAM_VALUE_DELLIMETER '='
++#define PNO_PARAM_SCANFREQ "SCANFREQ"
++#define PNO_PARAM_BESTN	"BESTN"
++#define PNO_PARAM_MSCAN "MSCAN"
++#define PNO_PARAM_CHANNEL "CHANNEL"
++#define PNO_PARAM_RTT "RTT"
++
++#define PNO_TLV_TYPE_SSID_IE		'S'
++#define PNO_TLV_TYPE_TIME		'T'
++#define PNO_TLV_FREQ_REPEAT		'R'
++#define PNO_TLV_FREQ_EXPO_MAX		'M'
++
++#define MAXNUM_SSID_PER_ADD	16
++#define MAXNUM_PNO_PARAMS 2
++#define PNO_TLV_COMMON_LENGTH	1
++#define DEFAULT_BATCH_MSCAN 16
++
++#define RESULTS_END_MARKER "----\n"
++#define SCAN_END_MARKER "####\n"
++#define AP_END_MARKER "====\n"
++#define PNO_RSSI_MARGIN_DBM          30
++
++#define CSCAN_COMMAND			"CSCAN "
++#define CSCAN_TLV_PREFIX		'S'
++#define CSCAN_TLV_VERSION		1
++#define CSCAN_TLV_SUBVERSION		0
++#define CSCAN_TLV_TYPE_SSID_IE		'S'
++#define CSCAN_TLV_TYPE_CHANNEL_IE	'C'
++#define CSCAN_TLV_TYPE_NPROBE_IE	'N'
++#define CSCAN_TLV_TYPE_ACTIVE_IE	'A'
++#define CSCAN_TLV_TYPE_PASSIVE_IE	'P'
++#define CSCAN_TLV_TYPE_HOME_IE		'H'
++#define CSCAN_TLV_TYPE_STYPE_IE		'T'
++
++#define WL_SCAN_PARAMS_SSID_MAX         10
++#define GET_SSID                        "SSID="
++#define GET_CHANNEL                     "CH="
++#define GET_NPROBE                      "NPROBE="
++#define GET_ACTIVE_ASSOC_DWELL          "ACTIVE="
++#define GET_PASSIVE_ASSOC_DWELL         "PASSIVE="
++#define GET_HOME_DWELL                  "HOME="
++#define GET_SCAN_TYPE                   "TYPE="
++
++#if defined(GSCAN_SUPPORT) || defined(DHD_GET_VALID_CHANNELS)
++#define GSCAN_MAX_CH_BUCKETS             8
++#define GSCAN_MAX_CHANNELS_IN_BUCKET     32
++#define GSCAN_MAX_AP_CACHE_PER_SCAN      32
++#define GSCAN_MAX_AP_CACHE               320
++#define GSCAN_BG_BAND_MASK             (1 << 0)
++#define GSCAN_A_BAND_MASK              (1 << 1)
++#define GSCAN_DFS_MASK                 (1 << 2)
++#define GSCAN_ABG_BAND_MASK            (GSCAN_A_BAND_MASK | GSCAN_BG_BAND_MASK)
++#define GSCAN_BAND_MASK                (GSCAN_ABG_BAND_MASK | GSCAN_DFS_MASK)
++
++#define GSCAN_FLUSH_HOTLIST_CFG      (1 << 0)
++#define GSCAN_FLUSH_SIGNIFICANT_CFG  (1 << 1)
++#define GSCAN_FLUSH_SCAN_CFG         (1 << 2)
++#define GSCAN_FLUSH_EPNO_CFG         (1 << 3)
++#define GSCAN_FLUSH_ALL_CFG     (GSCAN_FLUSH_SCAN_CFG | \
++								GSCAN_FLUSH_SIGNIFICANT_CFG | \
++								GSCAN_FLUSH_HOTLIST_CFG  | \
++								GSCAN_FLUSH_EPNO_CFG)
++#define DHD_EPNO_HIDDEN_SSID          (1 << 0)
++#define DHD_EPNO_A_BAND_TRIG          (1 << 1)
++#define DHD_EPNO_BG_BAND_TRIG         (1 << 2)
++#define DHD_EPNO_STRICT_MATCH         (1 << 3)
++#define DHD_EPNO_SAME_NETWORK         (1 << 4)
++#define DHD_PNO_USE_SSID              (DHD_EPNO_HIDDEN_SSID | DHD_EPNO_STRICT_MATCH)
++
++/* Do not change GSCAN_BATCH_RETRIEVAL_COMPLETE */
++#define GSCAN_BATCH_RETRIEVAL_COMPLETE      0
++#define GSCAN_BATCH_RETRIEVAL_IN_PROGRESS   1
++#define GSCAN_BATCH_NO_THR_SET              101
++#define GSCAN_LOST_AP_WINDOW_DEFAULT        4
++#define GSCAN_MIN_BSSID_TIMEOUT             90
++#define GSCAN_BATCH_GET_MAX_WAIT            500
++#define CHANNEL_BUCKET_EMPTY_INDEX                      0xFFFF
++#define GSCAN_RETRY_THRESHOLD              3
++
++#define MAX_EPNO_SSID_NUM                   64
++#endif /* GSCAN_SUPPORT || DHD_GET_VALID_CHANNELS */
++
++enum scan_status {
++	/* SCAN ABORT by other scan */
++	PNO_STATUS_ABORT,
++	/* RTT is presence or not */
++	PNO_STATUS_RTT_PRESENCE,
++	/* Disable PNO by Driver */
++	PNO_STATUS_DISABLE,
++	/* NORMAL BATCHING GET */
++	PNO_STATUS_NORMAL,
++	/* WLC_E_PFN_BEST_BATCHING */
++	PNO_STATUS_EVENT,
++	PNO_STATUS_MAX
++};
++#define PNO_STATUS_ABORT_MASK 0x0001
++#define PNO_STATUS_RTT_MASK 0x0002
++#define PNO_STATUS_DISABLE_MASK 0x0004
++#define PNO_STATUS_OOM_MASK 0x0010
++
++enum index_mode {
++	INDEX_OF_LEGACY_PARAMS,
++	INDEX_OF_BATCH_PARAMS,
++	INDEX_OF_HOTLIST_PARAMS,
++	/* GSCAN includes hotlist scan and they do not run
++	 * independent of each other
++	 */
++	INDEX_OF_GSCAN_PARAMS = INDEX_OF_HOTLIST_PARAMS,
++	INDEX_MODE_MAX
++};
++enum dhd_pno_status {
++	DHD_PNO_DISABLED,
++	DHD_PNO_ENABLED,
++	DHD_PNO_SUSPEND
++};
++typedef struct cmd_tlv {
++	char prefix;
++	char version;
++	char subtype;
++	char reserved;
++} cmd_tlv_t;
++#if defined(GSCAN_SUPPORT) || defined(DHD_GET_VALID_CHANNELS)
++typedef enum {
++    WIFI_BAND_UNSPECIFIED,
++    WIFI_BAND_BG = 1,                       /* 2.4 GHz                   */
++    WIFI_BAND_A = 2,                        /* 5 GHz without DFS         */
++    WIFI_BAND_A_DFS = 4,                    /* 5 GHz DFS only            */
++    WIFI_BAND_A_WITH_DFS = 6,               /* 5 GHz with DFS            */
++    WIFI_BAND_ABG = 3,                      /* 2.4 GHz + 5 GHz; no DFS   */
++    WIFI_BAND_ABG_WITH_DFS = 7,             /* 2.4 GHz + 5 GHz with DFS  */
++} gscan_wifi_band_t;
++
++typedef enum {
++	HOTLIST_LOST,
++	HOTLIST_FOUND
++} hotlist_type_t;
++
++typedef enum dhd_pno_gscan_cmd_cfg {
++	DHD_PNO_BATCH_SCAN_CFG_ID = 0,
++	DHD_PNO_GEOFENCE_SCAN_CFG_ID,
++	DHD_PNO_SIGNIFICANT_SCAN_CFG_ID,
++	DHD_PNO_SCAN_CFG_ID,
++	DHD_PNO_GET_CAPABILITIES,
++	DHD_PNO_GET_BATCH_RESULTS,
++	DHD_PNO_GET_CHANNEL_LIST,
++	DHD_PNO_GET_NEW_EPNO_SSID_ELEM,
++	DHD_PNO_EPNO_CFG_ID,
++	DHD_PNO_GET_AUTOJOIN_CAPABILITIES,
++	DHD_PNO_EPNO_PARAMS_ID
++} dhd_pno_gscan_cmd_cfg_t;
++
++typedef enum dhd_pno_mode {
++	/* Wi-Fi Legacy PNO Mode */
++	DHD_PNO_NONE_MODE   = 0,
++	DHD_PNO_LEGACY_MODE = (1 << (0)),
++	/* Wi-Fi Android BATCH SCAN Mode */
++	DHD_PNO_BATCH_MODE = (1 << (1)),
++	/* Wi-Fi Android Hotlist SCAN Mode */
++	DHD_PNO_HOTLIST_MODE = (1 << (2)),
++	/* Wi-Fi Google Android SCAN Mode */
++	DHD_PNO_GSCAN_MODE = (1 << (3))
++} dhd_pno_mode_t;
++#else
++typedef enum dhd_pno_mode {
++	/* Wi-Fi Legacy PNO Mode */
++	DHD_PNO_NONE_MODE   = 0,
++	DHD_PNO_LEGACY_MODE = (1 << (0)),
++	/* Wi-Fi Android BATCH SCAN Mode */
++	DHD_PNO_BATCH_MODE = (1 << (1)),
++	/* Wi-Fi Android Hotlist SCAN Mode */
++	DHD_PNO_HOTLIST_MODE = (1 << (2))
++} dhd_pno_mode_t;
++#endif /* GSCAN_SUPPORT || DHD_GET_VALID_CHANNELS */
++
++typedef struct dhd_pno_ssid {
++	bool		hidden;
++	int8		rssi_thresh;
++	uint8		dummy;
++	uint16		SSID_len;
++	uint32		flags;
++	int32		wpa_auth;
++	uchar		SSID[DOT11_MAX_SSID_LEN];
++	struct list_head list;
++} dhd_pno_ssid_t;
++
++struct dhd_pno_bssid {
++	struct ether_addr	macaddr;
++	/* Bit4: suppress_lost, Bit3: suppress_found */
++	uint16			flags;
++	struct list_head list;
++};
++
++typedef struct dhd_pno_bestnet_entry {
++	struct ether_addr BSSID;
++	uint8	SSID_len;
++	uint8	SSID[DOT11_MAX_SSID_LEN];
++	int8	RSSI;
++	uint8	channel;
++	uint32	timestamp;
++	uint16	rtt0; /* distance_cm based on RTT */
++	uint16	rtt1; /* distance_cm based on sample standard deviation */
++	unsigned long recorded_time;
++	struct list_head list;
++} dhd_pno_bestnet_entry_t;
++#define BESTNET_ENTRY_SIZE (sizeof(dhd_pno_bestnet_entry_t))
++
++typedef struct dhd_pno_bestnet_header {
++	struct dhd_pno_bestnet_header *next;
++	uint8 reason;
++	uint32 tot_cnt;
++	uint32 tot_size;
++	struct list_head entry_list;
++} dhd_pno_best_header_t;
++#define BEST_HEADER_SIZE (sizeof(dhd_pno_best_header_t))
++
++typedef struct dhd_pno_scan_results {
++	dhd_pno_best_header_t *bestnetheader;
++	uint8 cnt_header;
++	struct list_head list;
++} dhd_pno_scan_results_t;
++#define SCAN_RESULTS_SIZE (sizeof(dhd_pno_scan_results_t))
++
++struct dhd_pno_get_batch_info {
++	/* info related to get batch */
++	char *buf;
++	bool batch_started;
++	uint32 tot_scan_cnt;
++	uint32 expired_tot_scan_cnt;
++	uint32 top_node_cnt;
++	uint32 bufsize;
++	uint32 bytes_written;
++	int reason;
++	struct list_head scan_results_list;
++	struct list_head expired_scan_results_list;
++};
++struct dhd_pno_legacy_params {
++	uint16 scan_fr;
++	uint16 chan_list[WL_NUMCHANNELS];
++	uint16 nchan;
++	int pno_repeat;
++	int pno_freq_expo_max;
++	int nssid;
++	struct list_head ssid_list;
++};
++struct dhd_pno_batch_params {
++	int32 scan_fr;
++	uint8 bestn;
++	uint8 mscan;
++	uint8 band;
++	uint16 chan_list[WL_NUMCHANNELS];
++	uint16 nchan;
++	uint16 rtt;
++	struct dhd_pno_get_batch_info get_batch;
++};
++struct dhd_pno_hotlist_params {
++	uint8 band;
++	int32 scan_fr;
++	uint16 chan_list[WL_NUMCHANNELS];
++	uint16 nchan;
++	uint16 nbssid;
++	struct list_head bssid_list;
++};
++#if defined(GSCAN_SUPPORT) || defined(DHD_GET_VALID_CHANNELS)
++#define DHD_PNO_REPORT_NO_BATCH      (1 << 2)
++
++typedef struct dhd_pno_gscan_channel_bucket {
++	uint16 bucket_freq_multiple;
++	/* band = 1 All bg band channels,
++	 * band = 2 All a band channels,
++	 * band = 0 chan_list channels
++	 */
++	uint16 band;
++	uint8 report_flag;
++	uint8 num_channels;
++	uint16 repeat;
++	uint16 bucket_max_multiple;
++	uint16 chan_list[GSCAN_MAX_CHANNELS_IN_BUCKET];
++} dhd_pno_gscan_channel_bucket_t;
++
++
++#define DHD_PNO_AUTH_CODE_OPEN  1 /*  Open   */
++#define DHD_PNO_AUTH_CODE_PSK   2 /* WPA_PSK or WPA2PSK */
++#define DHD_PNO_AUTH_CODE_EAPOL 4 /* any EAPOL    */
++
++#define DHD_EPNO_DEFAULT_INDEX     0xFFFFFFFF
++
++typedef struct dhd_epno_params {
++	uint8 ssid[DOT11_MAX_SSID_LEN];
++	uint8 ssid_len;
++	int8 rssi_thresh;
++	uint8 flags;
++	uint8 auth;
++	/* index required only for visble ssid */
++	uint32 index;
++	struct list_head list;
++} dhd_epno_params_t;
++
++typedef struct dhd_epno_results {
++	uint8 ssid[DOT11_MAX_SSID_LEN];
++	uint8 ssid_len;
++	int8 rssi;
++	uint16 channel;
++	uint16 flags;
++	struct ether_addr bssid;
++} dhd_epno_results_t;
++
++typedef struct wifi_gscan_result {
++	uint64 ts;                           /* Time of discovery           */
++	char ssid[DOT11_MAX_SSID_LEN+1];     /* null terminated             */
++	struct ether_addr	macaddr;         /* BSSID                      */
++	uint32 channel;                      /* channel frequency in MHz    */
++	int32 rssi;                          /* in db                       */
++	uint64 rtt;                          /* in nanoseconds              */
++	uint64 rtt_sd;                       /* standard deviation in rtt   */
++	uint16 beacon_period;                /* units are Kusec             */
++	uint16 capability;                   /* Capability information       */
++	uint32 pad;
++} wifi_gscan_result_t;
++
++typedef struct wifi_gscan_full_result {
++    wifi_gscan_result_t fixed;
++    uint32 scan_ch_bucket;
++    uint32 ie_length;		/* byte length of Information Elements */
++    char  ie_data[1];		/* IE  data to follow       */
++} wifi_gscan_full_result_t;
++
++typedef struct gscan_results_cache {
++	struct gscan_results_cache *next;
++	uint8  scan_id;
++	uint8  flag;
++	uint8  tot_count;
++	uint8  tot_consumed;
++	uint32 scan_ch_bucket;
++	wifi_gscan_result_t results[1];
++} gscan_results_cache_t;
++
++typedef struct dhd_pno_gscan_capabilities {
++	int max_scan_cache_size;
++	int max_scan_buckets;
++	int max_ap_cache_per_scan;
++	int max_rssi_sample_size;
++	int max_scan_reporting_threshold;
++	int max_hotlist_aps;
++	int max_significant_wifi_change_aps;
++	int max_epno_ssid_crc32;
++	int max_epno_hidden_ssid;
++	int max_white_list_ssid;
++} dhd_pno_gscan_capabilities_t;
++
++typedef struct dhd_epno_ssid_cfg {
++	wl_pfn_ssid_params_t params;
++	uint32 num_epno_ssid;
++	struct list_head epno_ssid_list;
++} dhd_epno_ssid_cfg_t;
++
++struct dhd_pno_gscan_params {
++	int32 scan_fr;
++	uint8 bestn;
++	uint8 mscan;
++	uint8 buffer_threshold;
++	uint8 lost_ap_window;
++	uint8 nchannel_buckets;
++	uint8 reason;
++	uint8 get_batch_flag;
++	uint8 send_all_results_flag;
++	uint16 max_ch_bucket_freq;
++	gscan_results_cache_t *gscan_batch_cache;
++	gscan_results_cache_t *gscan_hotlist_found;
++	gscan_results_cache_t *gscan_hotlist_lost;
++	uint16 nbssid_hotlist;
++	struct dhd_pno_gscan_channel_bucket channel_bucket[GSCAN_MAX_CH_BUCKETS];
++	struct list_head hotlist_bssid_list;
++	dhd_epno_ssid_cfg_t epno_cfg;
++	uint32 scan_id;
++};
++
++typedef struct gscan_scan_params {
++	int32 scan_fr;
++	uint16 nchannel_buckets;
++	struct dhd_pno_gscan_channel_bucket channel_bucket[GSCAN_MAX_CH_BUCKETS];
++} gscan_scan_params_t;
++
++typedef struct gscan_batch_params {
++	uint8 bestn;
++	uint8 mscan;
++	uint8 buffer_threshold;
++} gscan_batch_params_t;
++
++struct bssid_t {
++	struct ether_addr	macaddr;
++	int16 rssi_reporting_threshold;  /* 0 -> no reporting threshold */
++};
++
++typedef struct gscan_hotlist_scan_params {
++	uint16 lost_ap_window; /* number of scans to declare LOST */
++	uint16 nbssid;   /* number of bssids  */
++	struct bssid_t bssid[1];  /* n bssids to follow */
++} gscan_hotlist_scan_params_t;
++
++#endif /* GSCAN_SUPPORT || DHD_GET_VALID_CHANNELS */
++typedef union dhd_pno_params {
++	struct dhd_pno_legacy_params params_legacy;
++	struct dhd_pno_batch_params params_batch;
++	struct dhd_pno_hotlist_params params_hotlist;
++#if defined(GSCAN_SUPPORT) || defined(DHD_GET_VALID_CHANNELS)
++	struct dhd_pno_gscan_params params_gscan;
++#endif /* GSCAN_SUPPORT || DHD_GET_VALID_CHANNELS */
++} dhd_pno_params_t;
++typedef struct dhd_pno_status_info {
++	dhd_pub_t *dhd;
++	struct work_struct work;
++	struct mutex pno_mutex;
++#ifdef GSCAN_SUPPORT
++	wait_queue_head_t batch_get_wait;
++#endif /* GSCAN_SUPPORT */
++	struct completion get_batch_done;
++	bool wls_supported; /* wifi location service supported or not */
++	enum dhd_pno_status pno_status;
++	enum dhd_pno_mode pno_mode;
++	dhd_pno_params_t pno_params_arr[INDEX_MODE_MAX];
++	struct list_head head_list;
++} dhd_pno_status_info_t;
++
++/* wrapper functions */
++extern int
++dhd_dev_pno_enable(struct net_device *dev, int enable);
++
++extern int
++dhd_dev_pno_stop_for_ssid(struct net_device *dev);
++
++extern int
++dhd_dev_pno_set_for_ssid(struct net_device *dev, wlc_ssid_ext_t* ssids_local, int nssid,
++	uint16 scan_fr, int pno_repeat, int pno_freq_expo_max, uint16 *channel_list, int nchan);
++
++extern int
++dhd_dev_pno_set_for_batch(struct net_device *dev,
++	struct dhd_pno_batch_params *batch_params);
++
++extern int
++dhd_dev_pno_get_for_batch(struct net_device *dev, char *buf, int bufsize);
++
++extern int
++dhd_dev_pno_stop_for_batch(struct net_device *dev);
++
++extern int
++dhd_dev_pno_set_for_hotlist(struct net_device *dev, wl_pfn_bssid_t *p_pfn_bssid,
++	struct dhd_pno_hotlist_params *hotlist_params);
++extern bool dhd_dev_is_legacy_pno_enabled(struct net_device *dev);
++#if defined(GSCAN_SUPPORT) || defined(DHD_GET_VALID_CHANNELS)
++extern void *
++dhd_dev_pno_get_gscan(struct net_device *dev, dhd_pno_gscan_cmd_cfg_t type, void *info,
++        uint32 *len);
++#endif /* GSCAN_SUPPORT || DHD_GET_VALID_CHANNELS */
++#ifdef GSCAN_SUPPORT
++extern int
++dhd_dev_pno_set_cfg_gscan(struct net_device *dev, dhd_pno_gscan_cmd_cfg_t type,
++              void *buf, bool flush);
++int dhd_dev_pno_lock_access_batch_results(struct net_device *dev);
++void dhd_dev_pno_unlock_access_batch_results(struct net_device *dev);
++extern int dhd_dev_pno_run_gscan(struct net_device *dev, bool run, bool flush);
++extern int dhd_dev_pno_enable_full_scan_result(struct net_device *dev, bool real_time);
++int dhd_retreive_batch_scan_results(dhd_pub_t *dhd);
++extern void * dhd_dev_hotlist_scan_event(struct net_device *dev,
++            const void  *data, int *send_evt_bytes, hotlist_type_t type);
++void * dhd_dev_process_full_gscan_result(struct net_device *dev,
++            const void  *data, uint32 len, int *send_evt_bytes);
++extern int dhd_dev_gscan_batch_cache_cleanup(struct net_device *dev);
++extern void dhd_dev_gscan_hotlist_cache_cleanup(struct net_device *dev, hotlist_type_t type);
++extern int dhd_dev_wait_batch_results_complete(struct net_device *dev);
++extern void * dhd_dev_process_epno_result(struct net_device *dev,
++		const void  *data, uint32 event, int *send_evt_bytes);
++extern int dhd_dev_set_epno(struct net_device *dev);
++extern int dhd_dev_flush_fw_epno(struct net_device *dev);
++#endif /* GSCAN_SUPPORT */
++/* dhd pno fuctions */
++extern int dhd_pno_stop_for_ssid(dhd_pub_t *dhd);
++extern int dhd_pno_enable(dhd_pub_t *dhd, int enable);
++extern int dhd_pno_set_for_ssid(dhd_pub_t *dhd, wlc_ssid_ext_t* ssid_list, int nssid,
++	uint16  scan_fr, int pno_repeat, int pno_freq_expo_max, uint16 *channel_list, int nchan);
++
++extern int dhd_pno_set_for_batch(dhd_pub_t *dhd, struct dhd_pno_batch_params *batch_params);
++
++extern int dhd_pno_get_for_batch(dhd_pub_t *dhd, char *buf, int bufsize, int reason);
++
++
++extern int dhd_pno_stop_for_batch(dhd_pub_t *dhd);
++
++extern int dhd_pno_set_for_hotlist(dhd_pub_t *dhd, wl_pfn_bssid_t *p_pfn_bssid,
++	struct dhd_pno_hotlist_params *hotlist_params);
++
++extern int dhd_pno_stop_for_hotlist(dhd_pub_t *dhd);
++
++extern int dhd_pno_event_handler(dhd_pub_t *dhd, wl_event_msg_t *event, void *event_data);
++extern int dhd_pno_init(dhd_pub_t *dhd);
++extern int dhd_pno_deinit(dhd_pub_t *dhd);
++extern bool dhd_is_pno_supported(dhd_pub_t *dhd);
++extern bool dhd_is_legacy_pno_enabled(dhd_pub_t *dhd);
++#if defined(GSCAN_SUPPORT) || defined(DHD_GET_VALID_CHANNELS)
++extern void * dhd_pno_get_gscan(dhd_pub_t *dhd, dhd_pno_gscan_cmd_cfg_t type, void *info,
++                       uint32 *len);
++#endif /* GSCAN_SUPPORT || DHD_GET_VALID_CHANNELS */
++#ifdef GSCAN_SUPPORT
++extern int dhd_pno_set_cfg_gscan(dhd_pub_t *dhd, dhd_pno_gscan_cmd_cfg_t type,
++                       void *buf, bool flush);
++extern int dhd_pno_lock_batch_results(dhd_pub_t *dhd);
++extern void dhd_pno_unlock_batch_results(dhd_pub_t *dhd);
++extern int dhd_pno_initiate_gscan_request(dhd_pub_t *dhd, bool run, bool flush);
++extern int dhd_pno_enable_full_scan_result(dhd_pub_t *dhd, bool real_time_flag);
++extern int dhd_pno_cfg_gscan(dhd_pub_t *dhd, dhd_pno_gscan_cmd_cfg_t type, void *buf);
++extern int dhd_dev_retrieve_batch_scan(struct net_device *dev);
++extern void *dhd_handle_hotlist_scan_evt(dhd_pub_t *dhd, const void *event_data,
++                       int *send_evt_bytes, hotlist_type_t type);
++extern void *dhd_process_full_gscan_result(dhd_pub_t *dhd, const void *event_data,
++                       uint32 len, int *send_evt_bytes);
++extern int dhd_gscan_batch_cache_cleanup(dhd_pub_t *dhd);
++extern void dhd_gscan_hotlist_cache_cleanup(dhd_pub_t *dhd, hotlist_type_t type);
++extern int dhd_wait_batch_results_complete(dhd_pub_t *dhd);
++extern void * dhd_pno_process_epno_result(dhd_pub_t *dhd, const void *data,
++         uint32 event, int *size);
++extern void dhd_pno_translate_epno_fw_flags(uint32 *flags);
++extern int dhd_pno_set_epno(dhd_pub_t *dhd);
++extern int dhd_pno_flush_fw_epno(dhd_pub_t *dhd);
++extern void dhd_pno_set_epno_auth_flag(uint32 *wpa_auth);
++#endif /* GSCAN_SUPPORT */
++#endif 
++
++#endif /* __DHD_PNO_H__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_proto.h b/module_drivers/drivers/net/wireless/bcmdhd/dhd_proto.h
+new file mode 100644
+index 000000000..820e3449f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_proto.h
+@@ -0,0 +1,201 @@
++/*
++ * Header file describing the internal (inter-module) DHD interfaces.
++ *
++ * Provides type definitions and function prototypes used to link the
++ * DHD OS, bus, and protocol modules.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_proto.h 678890 2017-01-11 11:48:36Z $
++ */
++
++#ifndef _dhd_proto_h_
++#define _dhd_proto_h_
++
++#include <dhdioctl.h>
++#include <wlioctl.h>
++#ifdef BCMPCIE
++#include <dhd_flowring.h>
++#endif
++
++#define DEFAULT_IOCTL_RESP_TIMEOUT	4000
++#ifndef IOCTL_RESP_TIMEOUT
++/* In milli second default value for Production FW */
++#define IOCTL_RESP_TIMEOUT  DEFAULT_IOCTL_RESP_TIMEOUT
++#endif /* IOCTL_RESP_TIMEOUT */
++
++#ifndef MFG_IOCTL_RESP_TIMEOUT
++#define MFG_IOCTL_RESP_TIMEOUT  20000  /* In milli second default value for MFG FW */
++#endif /* MFG_IOCTL_RESP_TIMEOUT */
++
++#define DEFAULT_D3_ACK_RESP_TIMEOUT	1000
++#ifndef D3_ACK_RESP_TIMEOUT
++#define D3_ACK_RESP_TIMEOUT		DEFAULT_D3_ACK_RESP_TIMEOUT
++#endif /* D3_ACK_RESP_TIMEOUT */
++
++#define DEFAULT_DHD_BUS_BUSY_TIMEOUT	(IOCTL_RESP_TIMEOUT + 1000)
++#ifndef DHD_BUS_BUSY_TIMEOUT
++#define DHD_BUS_BUSY_TIMEOUT	DEFAULT_DHD_BUS_BUSY_TIMEOUT
++#endif /* DEFAULT_DHD_BUS_BUSY_TIMEOUT */
++
++#define DS_EXIT_TIMEOUT	1000 /* In ms */
++#define DS_ENTER_TIMEOUT 1000 /* In ms */
++
++#define IOCTL_DISABLE_TIMEOUT 0
++
++/*
++ * Exported from the dhd protocol module (dhd_cdc, dhd_rndis)
++ */
++
++/* Linkage, sets prot link and updates hdrlen in pub */
++extern int dhd_prot_attach(dhd_pub_t *dhdp);
++
++/* Initilizes the index block for dma'ing indices */
++extern int dhd_prot_dma_indx_init(dhd_pub_t *dhdp, uint32 rw_index_sz,
++	uint8 type, uint32 length);
++
++/* Unlink, frees allocated protocol memory (including dhd_prot) */
++extern void dhd_prot_detach(dhd_pub_t *dhdp);
++
++/* Initialize protocol: sync w/dongle state.
++ * Sets dongle media info (iswl, drv_version, mac address).
++ */
++extern int dhd_sync_with_dongle(dhd_pub_t *dhdp);
++
++/* Protocol initialization needed for IOCTL/IOVAR path */
++extern int dhd_prot_init(dhd_pub_t *dhd);
++
++/* Stop protocol: sync w/dongle state. */
++extern void dhd_prot_stop(dhd_pub_t *dhdp);
++
++/* Add any protocol-specific data header.
++ * Caller must reserve prot_hdrlen prepend space.
++ */
++extern void dhd_prot_hdrpush(dhd_pub_t *, int ifidx, void *txp);
++extern uint dhd_prot_hdrlen(dhd_pub_t *, void *txp);
++
++/* Remove any protocol-specific data header. */
++extern int dhd_prot_hdrpull(dhd_pub_t *, int *ifidx, void *rxp, uchar *buf, uint *len);
++
++/* Use protocol to issue ioctl to dongle */
++extern int dhd_prot_ioctl(dhd_pub_t *dhd, int ifidx, wl_ioctl_t * ioc, void * buf, int len);
++
++/* Handles a protocol control response asynchronously */
++extern int dhd_prot_ctl_complete(dhd_pub_t *dhd);
++
++/* Check for and handle local prot-specific iovar commands */
++extern int dhd_prot_iovar_op(dhd_pub_t *dhdp, const char *name,
++                             void *params, int plen, void *arg, int len, bool set);
++
++/* Add prot dump output to a buffer */
++extern void dhd_prot_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf);
++
++/* Dump extended trap data */
++extern int dhd_prot_dump_extended_trap(dhd_pub_t *dhdp, struct bcmstrbuf *b, bool raw);
++
++/* Update local copy of dongle statistics */
++extern void dhd_prot_dstats(dhd_pub_t *dhdp);
++
++extern int dhd_ioctl(dhd_pub_t * dhd_pub, dhd_ioctl_t *ioc, void * buf, uint buflen);
++
++extern int dhd_preinit_ioctls(dhd_pub_t *dhd);
++
++extern int dhd_process_pkt_reorder_info(dhd_pub_t *dhd, uchar *reorder_info_buf,
++	uint reorder_info_len, void **pkt, uint32 *free_buf_count);
++
++#ifdef BCMPCIE
++extern bool dhd_prot_process_msgbuf_txcpl(dhd_pub_t *dhd, uint bound);
++extern bool dhd_prot_process_msgbuf_rxcpl(dhd_pub_t *dhd, uint bound);
++extern bool dhd_prot_process_msgbuf_infocpl(dhd_pub_t *dhd, uint bound);
++extern int dhd_prot_process_ctrlbuf(dhd_pub_t * dhd);
++extern int dhd_prot_process_trapbuf(dhd_pub_t * dhd);
++extern bool dhd_prot_dtohsplit(dhd_pub_t * dhd);
++extern int dhd_post_dummy_msg(dhd_pub_t *dhd);
++extern int dhdmsgbuf_lpbk_req(dhd_pub_t *dhd, uint len);
++extern void dhd_prot_rx_dataoffset(dhd_pub_t *dhd, uint32 offset);
++extern int dhd_prot_txdata(dhd_pub_t *dhd, void *p, uint8 ifidx);
++extern int dhdmsgbuf_dmaxfer_req(dhd_pub_t *dhd,
++	uint len, uint srcdelay, uint destdelay, uint d11_lpbk);
++
++extern void dhd_dma_buf_init(dhd_pub_t *dhd, void *dma_buf,
++	void *va, uint32 len, dmaaddr_t pa, void *dmah, void *secdma);
++extern void dhd_prot_flowrings_pool_release(dhd_pub_t *dhd,
++	uint16 flowid, void *msgbuf_ring);
++extern int dhd_prot_flow_ring_create(dhd_pub_t *dhd, flow_ring_node_t *flow_ring_node);
++extern int dhd_post_tx_ring_item(dhd_pub_t *dhd, void *PKTBUF, uint8 ifindex);
++extern int dhd_prot_flow_ring_delete(dhd_pub_t *dhd, flow_ring_node_t *flow_ring_node);
++extern int dhd_prot_flow_ring_flush(dhd_pub_t *dhd, flow_ring_node_t *flow_ring_node);
++extern int dhd_prot_ringupd_dump(dhd_pub_t *dhd, struct bcmstrbuf *b);
++extern uint32 dhd_prot_metadata_dbg_set(dhd_pub_t *dhd, bool val);
++extern uint32 dhd_prot_metadata_dbg_get(dhd_pub_t *dhd);
++extern uint32 dhd_prot_metadatalen_set(dhd_pub_t *dhd, uint32 val, bool rx);
++extern uint32 dhd_prot_metadatalen_get(dhd_pub_t *dhd, bool rx);
++extern void dhd_prot_print_flow_ring(dhd_pub_t *dhd, void *msgbuf_flow_info,
++	struct bcmstrbuf *strbuf, const char * fmt);
++extern void dhd_prot_print_info(dhd_pub_t *dhd, struct bcmstrbuf *strbuf);
++extern void dhd_prot_update_txflowring(dhd_pub_t *dhdp, uint16 flow_id, void *msgring_info);
++extern void dhd_prot_txdata_write_flush(dhd_pub_t *dhd, uint16 flow_id, bool in_lock);
++extern uint32 dhd_prot_txp_threshold(dhd_pub_t *dhd, bool set, uint32 val);
++extern void dhd_prot_reset(dhd_pub_t *dhd);
++
++#ifdef IDLE_TX_FLOW_MGMT
++extern int dhd_prot_flow_ring_batch_suspend_request(dhd_pub_t *dhd, uint16 *ringid, uint16 count);
++extern int dhd_prot_flow_ring_resume(dhd_pub_t *dhd, flow_ring_node_t *flow_ring_node);
++#endif /* IDLE_TX_FLOW_MGMT */
++extern int dhd_prot_init_info_rings(dhd_pub_t *dhd);
++
++#endif /* BCMPCIE */
++
++#ifdef DHD_LB
++extern void dhd_lb_tx_compl_handler(unsigned long data);
++extern void dhd_lb_rx_compl_handler(unsigned long data);
++extern void dhd_lb_rx_process_handler(unsigned long data);
++#endif /* DHD_LB */
++extern int dhd_prot_h2d_mbdata_send_ctrlmsg(dhd_pub_t *dhd, uint32 mb_data);
++
++#ifdef BCMPCIE
++extern int dhd_prot_send_host_timestamp(dhd_pub_t *dhdp, uchar *tlv, uint16 tlv_len,
++	uint16 seq, uint16 xt_id);
++extern bool dhd_prot_data_path_tx_timestamp_logging(dhd_pub_t *dhd,  bool enable, bool set);
++extern bool dhd_prot_data_path_rx_timestamp_logging(dhd_pub_t *dhd,  bool enable, bool set);
++#else /* BCMPCIE */
++#define dhd_prot_send_host_timestamp(a, b, c, d, e)		0
++#define dhd_prot_data_path_tx_timestamp_logging(a, b, c)	0
++#define dhd_prot_data_path_rx_timestamp_logging(a, b, c)	0
++#endif /* BCMPCIE */
++
++extern void dhd_prot_dma_indx_free(dhd_pub_t *dhd);
++
++/********************************
++ * For version-string expansion *
++ */
++#if defined(BDC)
++#define DHD_PROTOCOL "bdc"
++#elif defined(CDC)
++#define DHD_PROTOCOL "cdc"
++#else
++#define DHD_PROTOCOL "unknown"
++#endif /* proto */
++
++#endif /* _dhd_proto_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_rtt.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_rtt.c
+new file mode 100644
+index 000000000..a13f7ae14
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_rtt.c
+@@ -0,0 +1,2421 @@
++/*
++ * Broadcom Dongle Host Driver (DHD), RTT
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id$
++ */
++#include <typedefs.h>
++#include <osl.h>
++
++#include <epivers.h>
++#include <bcmutils.h>
++
++#include <bcmendian.h>
++#include <linuxver.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/sort.h>
++#include <dngl_stats.h>
++#include <wlioctl.h>
++
++#include <bcmevent.h>
++#include <dhd.h>
++#include <dhd_rtt.h>
++#include <dhd_dbg.h>
++#include <wldev_common.h>
++#ifdef WL_CFG80211
++#include <wl_cfg80211.h>
++#endif /* WL_CFG80211 */
++static DEFINE_SPINLOCK(noti_list_lock);
++#define NULL_CHECK(p, s, err)  \
++			do { \
++				if (!(p)) { \
++					printf("NULL POINTER (%s) : %s\n", __FUNCTION__, (s)); \
++					err = BCME_ERROR; \
++					return err; \
++				} \
++			} while (0)
++
++#define RTT_IS_ENABLED(rtt_status) (rtt_status->status == RTT_ENABLED)
++#define RTT_IS_STOPPED(rtt_status) (rtt_status->status == RTT_STOPPED)
++#define TIMESPEC_TO_US(ts)  (((uint64)(ts).tv_sec * USEC_PER_SEC) + \
++							(ts).tv_nsec / NSEC_PER_USEC)
++
++#define FTM_IOC_BUFSZ  2048	/* ioc buffsize for our module (> BCM_XTLV_HDR_SIZE) */
++#define FTM_AVAIL_MAX_SLOTS		32
++#define FTM_MAX_CONFIGS 10
++#define FTM_MAX_PARAMS 10
++#define FTM_DEFAULT_SESSION 1
++#define FTM_BURST_TIMEOUT_UNIT 250 /* 250 ns */
++#define FTM_INVALID -1
++#define	FTM_DEFAULT_CNT_20M		12
++#define FTM_DEFAULT_CNT_40M		10
++#define FTM_DEFAULT_CNT_80M		5
++
++/* convenience macros */
++#define FTM_TU2MICRO(_tu) ((uint64)(_tu) << 10)
++#define FTM_MICRO2TU(_tu) ((uint64)(_tu) >> 10)
++#define FTM_TU2MILLI(_tu) ((uint32)FTM_TU2MICRO(_tu) / 1000)
++#define FTM_MICRO2MILLI(_x) ((uint32)(_x) / 1000)
++#define FTM_MICRO2SEC(_x) ((uint32)(_x) / 1000000)
++#define FTM_INTVL2NSEC(_intvl) ((uint32)ftm_intvl2nsec(_intvl))
++#define FTM_INTVL2USEC(_intvl) ((uint32)ftm_intvl2usec(_intvl))
++#define FTM_INTVL2MSEC(_intvl) (FTM_INTVL2USEC(_intvl) / 1000)
++#define FTM_INTVL2SEC(_intvl) (FTM_INTVL2USEC(_intvl) / 1000000)
++#define FTM_USECIN100MILLI(_usec) ((_usec) / 100000)
++
++/* broadcom specific set to have more accurate data */
++#define ENABLE_VHT_ACK
++#define CH_MIN_5G_CHANNEL 34
++#define CH_MIN_2G_CHANNEL 1
++
++struct rtt_noti_callback {
++	struct list_head list;
++	void *ctx;
++	dhd_rtt_compl_noti_fn noti_fn;
++};
++
++
++/* bitmask indicating which command groups; */
++typedef enum {
++	FTM_SUBCMD_FLAG_METHOD	= 0x01,	/* FTM method command */
++	FTM_SUBCMD_FLAG_SESSION = 0x02,	/* FTM session command */
++	FTM_SUBCMD_FLAG_ALL = FTM_SUBCMD_FLAG_METHOD | FTM_SUBCMD_FLAG_SESSION
++} ftm_subcmd_flag_t;
++
++/* proxd ftm config-category definition */
++typedef enum {
++	FTM_CONFIG_CAT_GENERAL = 1,	/* generial configuration */
++	FTM_CONFIG_CAT_OPTIONS = 2,	/* 'config options' */
++	FTM_CONFIG_CAT_AVAIL = 3,	/* 'config avail' */
++} ftm_config_category_t;
++
++
++typedef struct ftm_subcmd_info {
++	int16				version;    /* FTM version (optional) */
++	char				*name;		/* cmd-name string as cmdline input */
++	wl_proxd_cmd_t		cmdid;		/* cmd-id */
++	bcm_xtlv_unpack_cbfn_t *handler;  /* cmd response handler (optional) */
++	ftm_subcmd_flag_t	cmdflag; /* CMD flag (optional)  */
++} ftm_subcmd_info_t;
++
++
++typedef struct ftm_config_options_info {
++	uint32 flags;				/* wl_proxd_flags_t/wl_proxd_session_flags_t */
++	bool enable;
++} ftm_config_options_info_t;
++
++typedef struct ftm_config_param_info {
++	uint16		tlvid;	/* mapping TLV id for the item */
++	union {
++		uint32  chanspec;
++		struct ether_addr mac_addr;
++		wl_proxd_intvl_t data_intvl;
++		uint32 data32;
++		uint16 data16;
++		uint8 data8;
++	};
++} ftm_config_param_info_t;
++
++/*
++* definition for id-string mapping.
++*   This is used to map an id (can be cmd-id, tlv-id, ....) to a text-string
++*   for debug-display or cmd-log-display
++*/
++typedef struct ftm_strmap_entry {
++	int32		id;
++	char		*text;
++} ftm_strmap_entry_t;
++
++
++typedef struct ftm_status_map_host_entry {
++	wl_proxd_status_t proxd_status;
++	rtt_reason_t rtt_reason;
++} ftm_status_map_host_entry_t;
++
++static int
++dhd_rtt_convert_results_to_host(rtt_report_t *rtt_report, uint8 *p_data, uint16 tlvid, uint16 len);
++
++static wifi_rate_t
++dhd_rtt_convert_rate_to_host(uint32 ratespec);
++
++#ifdef WL_CFG80211
++static int
++dhd_rtt_start(dhd_pub_t *dhd);
++#endif /* WL_CFG80211 */
++static const int burst_duration_idx[]  = {0, 0, 1, 2, 4, 8, 16, 32, 64, 128, 0, 0};
++
++/* ftm status mapping to host status */
++static const ftm_status_map_host_entry_t ftm_status_map_info[] = {
++	{WL_PROXD_E_INCOMPLETE, RTT_REASON_FAILURE},
++	{WL_PROXD_E_OVERRIDDEN, RTT_REASON_FAILURE},
++	{WL_PROXD_E_ASAP_FAILED, RTT_REASON_FAILURE},
++	{WL_PROXD_E_NOTSTARTED, RTT_REASON_FAIL_NOT_SCHEDULED_YET},
++	{WL_PROXD_E_INVALIDMEAS, RTT_REASON_FAIL_INVALID_TS},
++	{WL_PROXD_E_INCAPABLE, RTT_REASON_FAIL_NO_CAPABILITY},
++	{WL_PROXD_E_MISMATCH, RTT_REASON_FAILURE},
++	{WL_PROXD_E_DUP_SESSION, RTT_REASON_FAILURE},
++	{WL_PROXD_E_REMOTE_FAIL, RTT_REASON_FAILURE},
++	{WL_PROXD_E_REMOTE_INCAPABLE, RTT_REASON_FAILURE},
++	{WL_PROXD_E_SCHED_FAIL, RTT_REASON_FAIL_SCHEDULE},
++	{WL_PROXD_E_PROTO, RTT_REASON_FAIL_PROTOCOL},
++	{WL_PROXD_E_EXPIRED, RTT_REASON_FAILURE},
++	{WL_PROXD_E_TIMEOUT, RTT_REASON_FAIL_TM_TIMEOUT},
++	{WL_PROXD_E_NOACK, RTT_REASON_FAIL_NO_RSP},
++	{WL_PROXD_E_DEFERRED, RTT_REASON_FAILURE},
++	{WL_PROXD_E_INVALID_SID, RTT_REASON_FAILURE},
++	{WL_PROXD_E_REMOTE_CANCEL, RTT_REASON_FAILURE},
++	{WL_PROXD_E_CANCELED, RTT_REASON_ABORTED},
++	{WL_PROXD_E_INVALID_SESSION, RTT_REASON_FAILURE},
++	{WL_PROXD_E_BAD_STATE, RTT_REASON_FAILURE},
++	{WL_PROXD_E_ERROR, RTT_REASON_FAILURE},
++	{WL_PROXD_E_OK, RTT_REASON_SUCCESS}
++};
++
++/* ftm tlv-id mapping */
++static const ftm_strmap_entry_t ftm_tlvid_loginfo[] = {
++	/* { WL_PROXD_TLV_ID_xxx,				"text for WL_PROXD_TLV_ID_xxx" }, */
++	{ WL_PROXD_TLV_ID_NONE,				"none" },
++	{ WL_PROXD_TLV_ID_METHOD,			"method" },
++	{ WL_PROXD_TLV_ID_FLAGS,			"flags" },
++	{ WL_PROXD_TLV_ID_CHANSPEC,			"chanspec" },
++	{ WL_PROXD_TLV_ID_TX_POWER,			"tx power" },
++	{ WL_PROXD_TLV_ID_RATESPEC,			"ratespec" },
++	{ WL_PROXD_TLV_ID_BURST_DURATION,		"burst duration" },
++	{ WL_PROXD_TLV_ID_BURST_PERIOD,			"burst period" },
++	{ WL_PROXD_TLV_ID_BURST_FTM_SEP,		"burst ftm sep" },
++	{ WL_PROXD_TLV_ID_BURST_NUM_FTM,		"burst num ftm" },
++	{ WL_PROXD_TLV_ID_NUM_BURST,			"num burst" },
++	{ WL_PROXD_TLV_ID_FTM_RETRIES,			"ftm retries" },
++	{ WL_PROXD_TLV_ID_BSS_INDEX,			"BSS index" },
++	{ WL_PROXD_TLV_ID_BSSID,			"bssid" },
++	{ WL_PROXD_TLV_ID_INIT_DELAY,			"burst init delay" },
++	{ WL_PROXD_TLV_ID_BURST_TIMEOUT,		"burst timeout" },
++	{ WL_PROXD_TLV_ID_EVENT_MASK,			"event mask" },
++	{ WL_PROXD_TLV_ID_FLAGS_MASK,			"flags mask" },
++	{ WL_PROXD_TLV_ID_PEER_MAC,			"peer addr" },
++	{ WL_PROXD_TLV_ID_FTM_REQ,			"ftm req" },
++	{ WL_PROXD_TLV_ID_LCI_REQ,			"lci req" },
++	{ WL_PROXD_TLV_ID_LCI,				"lci" },
++	{ WL_PROXD_TLV_ID_CIVIC_REQ,			"civic req" },
++	{ WL_PROXD_TLV_ID_CIVIC,			"civic" },
++	{ WL_PROXD_TLV_ID_AVAIL,			"availability" },
++	{ WL_PROXD_TLV_ID_SESSION_FLAGS,		"session flags" },
++	{ WL_PROXD_TLV_ID_SESSION_FLAGS_MASK,		"session flags mask" },
++	{ WL_PROXD_TLV_ID_RX_MAX_BURST,			"rx max bursts" },
++	{ WL_PROXD_TLV_ID_RANGING_INFO,			"ranging info" },
++	{ WL_PROXD_TLV_ID_RANGING_FLAGS,		"ranging flags" },
++	{ WL_PROXD_TLV_ID_RANGING_FLAGS_MASK,		"ranging flags mask" },
++	/* output - 512 + x */
++	{ WL_PROXD_TLV_ID_STATUS,			"status" },
++	{ WL_PROXD_TLV_ID_COUNTERS,			"counters" },
++	{ WL_PROXD_TLV_ID_INFO,				"info" },
++	{ WL_PROXD_TLV_ID_RTT_RESULT,			"rtt result" },
++	{ WL_PROXD_TLV_ID_AOA_RESULT,			"aoa result" },
++	{ WL_PROXD_TLV_ID_SESSION_INFO,			"session info" },
++	{ WL_PROXD_TLV_ID_SESSION_STATUS,		"session status" },
++	{ WL_PROXD_TLV_ID_SESSION_ID_LIST,		"session ids" },
++	/* debug tlvs can be added starting 1024 */
++	{ WL_PROXD_TLV_ID_DEBUG_MASK,			"debug mask" },
++	{ WL_PROXD_TLV_ID_COLLECT,			"collect" },
++	{ WL_PROXD_TLV_ID_STRBUF,			"result" },
++	{ WL_PROXD_TLV_ID_COLLECT_DATA,			"collect-data" },
++	{ WL_PROXD_TLV_ID_RI_RR,			"ri_rr" },
++	{ WL_PROXD_TLV_ID_COLLECT_CHAN_DATA,		"chan est"}
++};
++
++static const ftm_strmap_entry_t ftm_event_type_loginfo[] = {
++	/* wl_proxd_event_type_t,			text-string */
++	{ WL_PROXD_EVENT_NONE,				"none" },
++	{ WL_PROXD_EVENT_SESSION_CREATE,		"session create" },
++	{ WL_PROXD_EVENT_SESSION_START,			"session start" },
++	{ WL_PROXD_EVENT_FTM_REQ,			"FTM req" },
++	{ WL_PROXD_EVENT_BURST_START,			"burst start" },
++	{ WL_PROXD_EVENT_BURST_END,			"burst end" },
++	{ WL_PROXD_EVENT_SESSION_END,			"session end" },
++	{ WL_PROXD_EVENT_SESSION_RESTART,		"session restart" },
++	{ WL_PROXD_EVENT_BURST_RESCHED,			"burst rescheduled" },
++	{ WL_PROXD_EVENT_SESSION_DESTROY,		"session destroy" },
++	{ WL_PROXD_EVENT_RANGE_REQ,			"range request" },
++	{ WL_PROXD_EVENT_FTM_FRAME,			"FTM frame" },
++	{ WL_PROXD_EVENT_DELAY,				"delay" },
++	{ WL_PROXD_EVENT_VS_INITIATOR_RPT,		"initiator-report " }, /* rx */
++	{ WL_PROXD_EVENT_RANGING,			"ranging " },
++	{ WL_PROXD_EVENT_COLLECT,			"collect" },
++};
++
++/*
++* session-state --> text string mapping
++*/
++static const ftm_strmap_entry_t ftm_session_state_value_loginfo[] = {
++	/* wl_proxd_session_state_t,			text string */
++	{ WL_PROXD_SESSION_STATE_CREATED,		"created" },
++	{ WL_PROXD_SESSION_STATE_CONFIGURED,		"configured" },
++	{ WL_PROXD_SESSION_STATE_STARTED,		"started" },
++	{ WL_PROXD_SESSION_STATE_DELAY,			"delay" },
++	{ WL_PROXD_SESSION_STATE_USER_WAIT,		"user-wait" },
++	{ WL_PROXD_SESSION_STATE_SCHED_WAIT,		"sched-wait" },
++	{ WL_PROXD_SESSION_STATE_BURST,			"burst" },
++	{ WL_PROXD_SESSION_STATE_STOPPING,		"stopping" },
++	{ WL_PROXD_SESSION_STATE_ENDED,			"ended" },
++	{ WL_PROXD_SESSION_STATE_DESTROYING,		"destroying" },
++	{ WL_PROXD_SESSION_STATE_NONE,			"none" }
++};
++
++/*
++* ranging-state --> text string mapping
++*/
++static const ftm_strmap_entry_t ftm_ranging_state_value_loginfo [] = {
++	/* wl_proxd_ranging_state_t,			text string */
++	{ WL_PROXD_RANGING_STATE_NONE,			"none" },
++	{ WL_PROXD_RANGING_STATE_NOTSTARTED,		"nonstarted" },
++	{ WL_PROXD_RANGING_STATE_INPROGRESS,		"inprogress" },
++	{ WL_PROXD_RANGING_STATE_DONE,			"done" },
++};
++
++/*
++* status --> text string mapping
++*/
++static const ftm_strmap_entry_t ftm_status_value_loginfo[] = {
++	/* wl_proxd_status_t,			text-string */
++	{ WL_PROXD_E_OVERRIDDEN,		"overridden" },
++	{ WL_PROXD_E_ASAP_FAILED,		"ASAP failed" },
++	{ WL_PROXD_E_NOTSTARTED,		"not started" },
++	{ WL_PROXD_E_INVALIDMEAS,		"invalid measurement" },
++	{ WL_PROXD_E_INCAPABLE,			"incapable" },
++	{ WL_PROXD_E_MISMATCH,			"mismatch"},
++	{ WL_PROXD_E_DUP_SESSION,		"dup session" },
++	{ WL_PROXD_E_REMOTE_FAIL,		"remote fail" },
++	{ WL_PROXD_E_REMOTE_INCAPABLE,		"remote incapable" },
++	{ WL_PROXD_E_SCHED_FAIL,		"sched failure" },
++	{ WL_PROXD_E_PROTO,			"protocol error" },
++	{ WL_PROXD_E_EXPIRED,			"expired" },
++	{ WL_PROXD_E_TIMEOUT,			"timeout" },
++	{ WL_PROXD_E_NOACK,			"no ack" },
++	{ WL_PROXD_E_DEFERRED,			"deferred" },
++	{ WL_PROXD_E_INVALID_SID,		"invalid session id" },
++	{ WL_PROXD_E_REMOTE_CANCEL,		"remote cancel" },
++	{ WL_PROXD_E_CANCELED,			"canceled" },
++	{ WL_PROXD_E_INVALID_SESSION,		"invalid session" },
++	{ WL_PROXD_E_BAD_STATE,			"bad state" },
++	{ WL_PROXD_E_ERROR,			"error" },
++	{ WL_PROXD_E_OK,			"OK" }
++};
++
++/*
++* time interval unit --> text string mapping
++*/
++static const ftm_strmap_entry_t ftm_tmu_value_loginfo[] = {
++	/* wl_proxd_tmu_t,			text-string */
++	{ WL_PROXD_TMU_TU,			"TU" },
++	{ WL_PROXD_TMU_SEC,			"sec" },
++	{ WL_PROXD_TMU_MILLI_SEC,		"ms" },
++	{ WL_PROXD_TMU_MICRO_SEC,		"us" },
++	{ WL_PROXD_TMU_NANO_SEC,		"ns" },
++	{ WL_PROXD_TMU_PICO_SEC,		"ps" }
++};
++
++#define RSPEC_BW(rspec)         ((rspec) & WL_RSPEC_BW_MASK)
++#define RSPEC_IS20MHZ(rspec)	(RSPEC_BW(rspec) == WL_RSPEC_BW_20MHZ)
++#define RSPEC_IS40MHZ(rspec)	(RSPEC_BW(rspec) == WL_RSPEC_BW_40MHZ)
++#define RSPEC_IS80MHZ(rspec)    (RSPEC_BW(rspec) == WL_RSPEC_BW_80MHZ)
++#define RSPEC_IS160MHZ(rspec)   (RSPEC_BW(rspec) == WL_RSPEC_BW_160MHZ)
++
++#define IS_MCS(rspec)     	(((rspec) & WL_RSPEC_ENCODING_MASK) != WL_RSPEC_ENCODE_RATE)
++#define IS_STBC(rspec)     	(((((rspec) & WL_RSPEC_ENCODING_MASK) == WL_RSPEC_ENCODE_HT) ||	\
++	(((rspec) & WL_RSPEC_ENCODING_MASK) == WL_RSPEC_ENCODE_VHT)) &&	\
++	(((rspec) & WL_RSPEC_STBC) == WL_RSPEC_STBC))
++#define RSPEC_ISSGI(rspec)      (((rspec) & WL_RSPEC_SGI) != 0)
++#define RSPEC_ISLDPC(rspec)     (((rspec) & WL_RSPEC_LDPC) != 0)
++#define RSPEC_ISSTBC(rspec)     (((rspec) & WL_RSPEC_STBC) != 0)
++#define RSPEC_ISTXBF(rspec)     (((rspec) & WL_RSPEC_TXBF) != 0)
++#define RSPEC_ISVHT(rspec)    	(((rspec) & WL_RSPEC_ENCODING_MASK) == WL_RSPEC_ENCODE_VHT)
++#define RSPEC_ISHT(rspec)	(((rspec) & WL_RSPEC_ENCODING_MASK) == WL_RSPEC_ENCODE_HT)
++#define RSPEC_ISLEGACY(rspec)   (((rspec) & WL_RSPEC_ENCODING_MASK) == WL_RSPEC_ENCODE_RATE)
++#define RSPEC2RATE(rspec)	(RSPEC_ISLEGACY(rspec) ? \
++				 ((rspec) & RSPEC_RATE_MASK) : rate_rspec2rate(rspec))
++/* return rate in unit of 500Kbps -- for internal use in wlc_rate_sel.c */
++#define RSPEC2KBPS(rspec)	rate_rspec2rate(rspec)
++
++struct ieee_80211_mcs_rate_info {
++	uint8 constellation_bits;
++	uint8 coding_q;
++	uint8 coding_d;
++};
++
++static const struct ieee_80211_mcs_rate_info wl_mcs_info[] = {
++	{ 1, 1, 2 }, /* MCS  0: MOD: BPSK,   CR 1/2 */
++	{ 2, 1, 2 }, /* MCS  1: MOD: QPSK,   CR 1/2 */
++	{ 2, 3, 4 }, /* MCS  2: MOD: QPSK,   CR 3/4 */
++	{ 4, 1, 2 }, /* MCS  3: MOD: 16QAM,  CR 1/2 */
++	{ 4, 3, 4 }, /* MCS  4: MOD: 16QAM,  CR 3/4 */
++	{ 6, 2, 3 }, /* MCS  5: MOD: 64QAM,  CR 2/3 */
++	{ 6, 3, 4 }, /* MCS  6: MOD: 64QAM,  CR 3/4 */
++	{ 6, 5, 6 }, /* MCS  7: MOD: 64QAM,  CR 5/6 */
++	{ 8, 3, 4 }, /* MCS  8: MOD: 256QAM, CR 3/4 */
++	{ 8, 5, 6 }  /* MCS  9: MOD: 256QAM, CR 5/6 */
++};
++
++/**
++ * Returns the rate in [Kbps] units for a caller supplied MCS/bandwidth/Nss/Sgi combination.
++ *     'mcs' : a *single* spatial stream MCS (11n or 11ac)
++ */
++uint
++rate_mcs2rate(uint mcs, uint nss, uint bw, int sgi)
++{
++	const int ksps = 250; /* kilo symbols per sec, 4 us sym */
++	const int Nsd_20MHz = 52;
++	const int Nsd_40MHz = 108;
++	const int Nsd_80MHz = 234;
++	const int Nsd_160MHz = 468;
++	uint rate;
++
++	if (mcs == 32) {
++		/* just return fixed values for mcs32 instead of trying to parametrize */
++		rate = (sgi == 0) ? 6000 : 6778;
++	} else if (mcs <= 9) {
++		/* This calculation works for 11n HT and 11ac VHT if the HT mcs values
++		 * are decomposed into a base MCS = MCS % 8, and Nss = 1 + MCS / 8.
++		 * That is, HT MCS 23 is a base MCS = 7, Nss = 3
++		 */
++
++		/* find the number of complex numbers per symbol */
++		if (RSPEC_IS20MHZ(bw)) {
++			rate = Nsd_20MHz;
++		} else if (RSPEC_IS40MHZ(bw)) {
++			rate = Nsd_40MHz;
++		} else if (bw == WL_RSPEC_BW_80MHZ) {
++			rate = Nsd_80MHz;
++		} else if (bw == WL_RSPEC_BW_160MHZ) {
++			rate = Nsd_160MHz;
++		} else {
++			rate = 0;
++		}
++
++		/* multiply by bits per number from the constellation in use */
++		rate = rate * wl_mcs_info[mcs].constellation_bits;
++
++		/* adjust for the number of spatial streams */
++		rate = rate * nss;
++
++		/* adjust for the coding rate given as a quotient and divisor */
++		rate = (rate * wl_mcs_info[mcs].coding_q) / wl_mcs_info[mcs].coding_d;
++
++		/* multiply by Kilo symbols per sec to get Kbps */
++		rate = rate * ksps;
++
++		/* adjust the symbols per sec for SGI
++		 * symbol duration is 4 us without SGI, and 3.6 us with SGI,
++		 * so ratio is 10 / 9
++		 */
++		if (sgi) {
++			/* add 4 for rounding of division by 9 */
++			rate = ((rate * 10) + 4) / 9;
++		}
++	} else {
++		rate = 0;
++	}
++
++	return rate;
++} /* wlc_rate_mcs2rate */
++
++/** take a well formed ratespec_t arg and return phy rate in [Kbps] units */
++int
++rate_rspec2rate(uint32 rspec)
++{
++	int rate = -1;
++
++	if (RSPEC_ISLEGACY(rspec)) {
++		rate = 500 * (rspec & WL_RSPEC_RATE_MASK);
++	} else if (RSPEC_ISHT(rspec)) {
++		uint mcs = (rspec & WL_RSPEC_RATE_MASK);
++
++		if (mcs == 32) {
++			rate = rate_mcs2rate(mcs, 1, WL_RSPEC_BW_40MHZ, RSPEC_ISSGI(rspec));
++		} else {
++			uint nss = 1 + (mcs / 8);
++			mcs = mcs % 8;
++			rate = rate_mcs2rate(mcs, nss, RSPEC_BW(rspec), RSPEC_ISSGI(rspec));
++		}
++	} else if (RSPEC_ISVHT(rspec)) {
++		uint mcs = (rspec & WL_RSPEC_VHT_MCS_MASK);
++		uint nss = (rspec & WL_RSPEC_VHT_NSS_MASK) >> WL_RSPEC_VHT_NSS_SHIFT;
++
++		ASSERT(mcs <= 9);
++		ASSERT(nss <= 8);
++
++		rate = rate_mcs2rate(mcs, nss, RSPEC_BW(rspec), RSPEC_ISSGI(rspec));
++	} else {
++		ASSERT(0);
++	}
++
++	return (rate == 0) ? -1 : rate;
++}
++
++char resp_buf[WLC_IOCTL_SMLEN];
++
++static uint64
++ftm_intvl2nsec(const wl_proxd_intvl_t *intvl)
++{
++	uint64 ret;
++	ret = intvl->intvl;
++	switch (intvl->tmu) {
++	case WL_PROXD_TMU_TU:			ret = FTM_TU2MICRO(ret) * 1000; break;
++	case WL_PROXD_TMU_SEC:			ret *= 1000000000; break;
++	case WL_PROXD_TMU_MILLI_SEC:	ret *= 1000000; break;
++	case WL_PROXD_TMU_MICRO_SEC:	ret *= 1000; break;
++	case WL_PROXD_TMU_PICO_SEC:		ret = intvl->intvl / 1000; break;
++	case WL_PROXD_TMU_NANO_SEC:		/* fall through */
++	default:						break;
++	}
++	return ret;
++}
++uint64
++ftm_intvl2usec(const wl_proxd_intvl_t *intvl)
++{
++	uint64 ret;
++	ret = intvl->intvl;
++	switch (intvl->tmu) {
++	case WL_PROXD_TMU_TU:			ret = FTM_TU2MICRO(ret); break;
++	case WL_PROXD_TMU_SEC:			ret *= 1000000; break;
++	case WL_PROXD_TMU_NANO_SEC:		ret = intvl->intvl / 1000; break;
++	case WL_PROXD_TMU_PICO_SEC:		ret = intvl->intvl / 1000000; break;
++	case WL_PROXD_TMU_MILLI_SEC:	ret *= 1000; break;
++	case WL_PROXD_TMU_MICRO_SEC:	/* fall through */
++	default:						break;
++	}
++	return ret;
++}
++
++/*
++* lookup 'id' (as a key) from a fw status to host map table
++* if found, return the corresponding reason code
++*/
++
++static rtt_reason_t
++ftm_get_statusmap_info(wl_proxd_status_t id, const ftm_status_map_host_entry_t *p_table,
++	uint32 num_entries)
++{
++	int i;
++	const ftm_status_map_host_entry_t *p_entry;
++	/* scan thru the table till end */
++	p_entry = p_table;
++	for (i = 0; i < (int) num_entries; i++)
++	{
++		if (p_entry->proxd_status == id) {
++			return p_entry->rtt_reason;
++		}
++		p_entry++;		/* next entry */
++	}
++	return RTT_REASON_FAILURE; /* not found */
++}
++/*
++* lookup 'id' (as a key) from a table
++* if found, return the entry pointer, otherwise return NULL
++*/
++static const ftm_strmap_entry_t*
++ftm_get_strmap_info(int32 id, const ftm_strmap_entry_t *p_table, uint32 num_entries)
++{
++	int i;
++	const ftm_strmap_entry_t *p_entry;
++
++	/* scan thru the table till end */
++	p_entry = p_table;
++	for (i = 0; i < (int) num_entries; i++)
++	{
++		if (p_entry->id == id)
++			return p_entry;
++		p_entry++;		/* next entry */
++	}
++	return NULL;			/* not found */
++}
++
++/*
++* map enum to a text-string for display, this function is called by the following:
++* For debug/trace:
++*     ftm_[cmdid|tlvid]_to_str()
++* For TLV-output log for 'get' commands
++*     ftm_[method|tmu|caps|status|state]_value_to_logstr()
++* Input:
++*     pTable -- point to a 'enum to string' table.
++*/
++static const char *
++ftm_map_id_to_str(int32 id, const ftm_strmap_entry_t *p_table, uint32 num_entries)
++{
++	const ftm_strmap_entry_t*p_entry = ftm_get_strmap_info(id, p_table, num_entries);
++	if (p_entry)
++		return (p_entry->text);
++
++	return "invalid";
++}
++
++
++#ifdef RTT_DEBUG
++
++/* define entry, e.g. { WL_PROXD_CMD_xxx, "WL_PROXD_CMD_xxx" } */
++#define DEF_STRMAP_ENTRY(id) { (id), #id }
++
++/* ftm cmd-id mapping */
++static const ftm_strmap_entry_t ftm_cmdid_map[] = {
++	/* {wl_proxd_cmd_t(WL_PROXD_CMD_xxx), "WL_PROXD_CMD_xxx" }, */
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_NONE),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_GET_VERSION),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_ENABLE),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_DISABLE),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_CONFIG),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_START_SESSION),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_BURST_REQUEST),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_STOP_SESSION),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_DELETE_SESSION),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_GET_RESULT),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_GET_INFO),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_GET_STATUS),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_GET_SESSIONS),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_GET_COUNTERS),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_CLEAR_COUNTERS),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_COLLECT),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_TUNE),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_DUMP),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_START_RANGING),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_STOP_RANGING),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_GET_RANGING_INFO),
++};
++
++/*
++* map a ftm cmd-id to a text-string for display
++*/
++static const char *
++ftm_cmdid_to_str(uint16 cmdid)
++{
++	return ftm_map_id_to_str((int32) cmdid, &ftm_cmdid_map[0], ARRAYSIZE(ftm_cmdid_map));
++}
++#endif /* RTT_DEBUG */
++
++
++/*
++* convert BCME_xxx error codes into related error strings
++* note, bcmerrorstr() defined in bcmutils is for BCMDRIVER only,
++*       this duplicate copy is for WL access and may need to clean up later
++*/
++static const char *ftm_bcmerrorstrtable[] = BCMERRSTRINGTABLE;
++static const char *
++ftm_status_value_to_logstr(wl_proxd_status_t status)
++{
++	static char ftm_msgbuf_status_undef[32];
++	const ftm_strmap_entry_t *p_loginfo;
++	int bcmerror;
++
++	/* check if within BCME_xxx error range */
++	bcmerror = (int) status;
++	if (VALID_BCMERROR(bcmerror))
++		return ftm_bcmerrorstrtable[-bcmerror];
++
++	/* otherwise, look for 'proxd ftm status' range */
++	p_loginfo = ftm_get_strmap_info((int32) status,
++		&ftm_status_value_loginfo[0], ARRAYSIZE(ftm_status_value_loginfo));
++	if (p_loginfo)
++		return p_loginfo->text;
++
++	/* report for 'out of range' FTM-status error code */
++	memset(ftm_msgbuf_status_undef, 0, sizeof(ftm_msgbuf_status_undef));
++	snprintf(ftm_msgbuf_status_undef, sizeof(ftm_msgbuf_status_undef),
++		"Undefined status %d", status);
++	return &ftm_msgbuf_status_undef[0];
++}
++
++static const char *
++ftm_tmu_value_to_logstr(wl_proxd_tmu_t tmu)
++{
++	return ftm_map_id_to_str((int32)tmu,
++		&ftm_tmu_value_loginfo[0], ARRAYSIZE(ftm_tmu_value_loginfo));
++}
++
++static const ftm_strmap_entry_t*
++ftm_get_event_type_loginfo(wl_proxd_event_type_t	event_type)
++{
++	/* look up 'event-type' from a predefined table  */
++	return ftm_get_strmap_info((int32) event_type,
++		ftm_event_type_loginfo, ARRAYSIZE(ftm_event_type_loginfo));
++}
++
++static const char *
++ftm_session_state_value_to_logstr(wl_proxd_session_state_t state)
++{
++	return ftm_map_id_to_str((int32)state, &ftm_session_state_value_loginfo[0],
++		ARRAYSIZE(ftm_session_state_value_loginfo));
++}
++
++
++#ifdef WL_CFG80211
++/*
++* send 'proxd' iovar for all ftm get-related commands
++*/
++static int
++rtt_do_get_ioctl(dhd_pub_t *dhd, wl_proxd_iov_t *p_proxd_iov, uint16 proxd_iovsize,
++		ftm_subcmd_info_t *p_subcmd_info)
++{
++
++	wl_proxd_iov_t *p_iovresp = (wl_proxd_iov_t *)resp_buf;
++	int status;
++	int tlvs_len;
++	/*  send getbuf proxd iovar */
++	status = dhd_getiovar(dhd, 0, "proxd", (char *)p_proxd_iov,
++			proxd_iovsize, (char **)&p_iovresp, WLC_IOCTL_SMLEN);
++	if (status != BCME_OK) {
++		DHD_ERROR(("%s: failed to send getbuf proxd iovar (CMD ID : %d), status=%d\n",
++			__FUNCTION__, p_subcmd_info->cmdid, status));
++		return status;
++	}
++	if (p_subcmd_info->cmdid == WL_PROXD_CMD_GET_VERSION) {
++		p_subcmd_info->version = ltoh16(p_iovresp->version);
++		DHD_RTT(("ftm version: 0x%x\n", ltoh16(p_iovresp->version)));
++		goto exit;
++	}
++
++	tlvs_len = ltoh16(p_iovresp->len) - WL_PROXD_IOV_HDR_SIZE;
++	if (tlvs_len < 0) {
++		DHD_ERROR(("%s: alert, p_iovresp->len(%d) should not be smaller than %d\n",
++			__FUNCTION__, ltoh16(p_iovresp->len), (int) WL_PROXD_IOV_HDR_SIZE));
++		tlvs_len = 0;
++	}
++
++	if (tlvs_len > 0 && p_subcmd_info->handler) {
++		/* unpack TLVs and invokes the cbfn for processing */
++		status = bcm_unpack_xtlv_buf(p_proxd_iov, (uint8 *)p_iovresp->tlvs,
++				tlvs_len, BCM_XTLV_OPTION_ALIGN32, p_subcmd_info->handler);
++	}
++exit:
++	return status;
++}
++
++
++static wl_proxd_iov_t *
++rtt_alloc_getset_buf(wl_proxd_method_t method, wl_proxd_session_id_t session_id,
++	wl_proxd_cmd_t cmdid, uint16 tlvs_bufsize, uint16 *p_out_bufsize)
++{
++	uint16 proxd_iovsize;
++	uint16 kflags;
++	wl_proxd_tlv_t *p_tlv;
++	wl_proxd_iov_t *p_proxd_iov = (wl_proxd_iov_t *) NULL;
++
++	*p_out_bufsize = 0;	/* init */
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	/* calculate the whole buffer size, including one reserve-tlv entry in the header */
++	proxd_iovsize = sizeof(wl_proxd_iov_t) + tlvs_bufsize;
++
++	p_proxd_iov = kzalloc(proxd_iovsize, kflags);
++	if (p_proxd_iov == NULL) {
++		DHD_ERROR(("error: failed to allocate %d bytes of memory\n", proxd_iovsize));
++		return NULL;
++	}
++
++	/* setup proxd-FTM-method iovar header */
++	p_proxd_iov->version = htol16(WL_PROXD_API_VERSION);
++	p_proxd_iov->len = htol16(proxd_iovsize); /* caller may adjust it based on #of TLVs */
++	p_proxd_iov->cmd = htol16(cmdid);
++	p_proxd_iov->method = htol16(method);
++	p_proxd_iov->sid = htol16(session_id);
++
++	/* initialize the reserved/dummy-TLV in iovar header */
++	p_tlv = p_proxd_iov->tlvs;
++	p_tlv->id = htol16(WL_PROXD_TLV_ID_NONE);
++	p_tlv->len = htol16(0);
++
++	*p_out_bufsize = proxd_iovsize;	/* for caller's reference */
++
++	return p_proxd_iov;
++}
++
++
++static int
++dhd_rtt_common_get_handler(dhd_pub_t *dhd, ftm_subcmd_info_t *p_subcmd_info,
++		wl_proxd_method_t method,
++		wl_proxd_session_id_t session_id)
++{
++	int status = BCME_OK;
++	uint16 proxd_iovsize = 0;
++	wl_proxd_iov_t *p_proxd_iov;
++#ifdef RTT_DEBUG
++	DHD_RTT(("enter %s: method=%d, session_id=%d, cmdid=%d(%s)\n",
++		__FUNCTION__, method, session_id, p_subcmd_info->cmdid,
++		ftm_cmdid_to_str(p_subcmd_info->cmdid)));
++#endif
++	/* alloc mem for ioctl headr + reserved 0 bufsize for tlvs (initialize to zero) */
++	p_proxd_iov = rtt_alloc_getset_buf(method, session_id, p_subcmd_info->cmdid,
++		0, &proxd_iovsize);
++
++	if (p_proxd_iov == NULL)
++		return BCME_NOMEM;
++
++	status = rtt_do_get_ioctl(dhd, p_proxd_iov, proxd_iovsize, p_subcmd_info);
++
++	if (status != BCME_OK) {
++		DHD_RTT(("%s failed: status=%d\n", __FUNCTION__, status));
++	}
++	kfree(p_proxd_iov);
++	return status;
++}
++
++/*
++* common handler for set-related proxd method commands which require no TLV as input
++*   wl proxd ftm [session-id] <set-subcmd>
++* e.g.
++*   wl proxd ftm enable -- to enable ftm
++*   wl proxd ftm disable -- to disable ftm
++*   wl proxd ftm <session-id> start -- to start a specified session
++*   wl proxd ftm <session-id> stop  -- to cancel a specified session;
++*                                    state is maintained till session is delete.
++*   wl proxd ftm <session-id> delete -- to delete a specified session
++*   wl proxd ftm [<session-id>] clear-counters -- to clear counters
++*   wl proxd ftm <session-id> burst-request -- on initiator: to send burst request;
++*                                              on target: send FTM frame
++*   wl proxd ftm <session-id> collect
++*   wl proxd ftm tune     (TBD)
++*/
++static int
++dhd_rtt_common_set_handler(dhd_pub_t *dhd, const ftm_subcmd_info_t *p_subcmd_info,
++	wl_proxd_method_t method, wl_proxd_session_id_t session_id)
++{
++	uint16 proxd_iovsize;
++	wl_proxd_iov_t *p_proxd_iov;
++	int ret;
++
++#ifdef RTT_DEBUG
++	DHD_RTT(("enter %s: method=%d, session_id=%d, cmdid=%d(%s)\n",
++		__FUNCTION__, method, session_id, p_subcmd_info->cmdid,
++		ftm_cmdid_to_str(p_subcmd_info->cmdid)));
++#endif
++
++	/* allocate and initialize a temp buffer for 'set proxd' iovar */
++	proxd_iovsize = 0;
++	p_proxd_iov = rtt_alloc_getset_buf(method, session_id, p_subcmd_info->cmdid,
++							0, &proxd_iovsize);		/* no TLV */
++	if (p_proxd_iov == NULL)
++		return BCME_NOMEM;
++
++	/* no TLV to pack, simply issue a set-proxd iovar */
++	ret = dhd_iovar(dhd, 0, "proxd", (char *)p_proxd_iov, proxd_iovsize, NULL, 0, TRUE);
++#ifdef RTT_DEBUG
++	if (ret != BCME_OK) {
++		DHD_RTT(("error: IOVAR failed, status=%d\n", ret));
++	}
++#endif
++	/* clean up */
++	kfree(p_proxd_iov);
++
++	return ret;
++}
++#endif /* WL_CFG80211 */
++
++static int
++rtt_unpack_xtlv_cbfn(void *ctx, uint8 *p_data, uint16 tlvid, uint16 len)
++{
++	int ret = BCME_OK;
++	int i;
++	wl_proxd_ftm_session_status_t *p_data_info = NULL;
++	wl_proxd_collect_event_data_t *p_collect_data = NULL;
++	uint32 chan_data_entry = 0;
++
++	switch (tlvid) {
++	case WL_PROXD_TLV_ID_RTT_RESULT:
++		ret = dhd_rtt_convert_results_to_host((rtt_report_t *)ctx,
++				p_data, tlvid, len);
++		break;
++	case WL_PROXD_TLV_ID_SESSION_STATUS:
++		DHD_RTT(("WL_PROXD_TLV_ID_SESSION_STATUS\n"));
++		memcpy(ctx, p_data, sizeof(wl_proxd_ftm_session_status_t));
++		p_data_info = (wl_proxd_ftm_session_status_t *)ctx;
++		p_data_info->sid = ltoh16_ua(&p_data_info->sid);
++		p_data_info->state = ltoh16_ua(&p_data_info->state);
++		p_data_info->status = ltoh32_ua(&p_data_info->status);
++		p_data_info->burst_num = ltoh16_ua(&p_data_info->burst_num);
++		DHD_RTT(("\tsid=%u, state=%d, status=%d, burst_num=%u\n",
++			p_data_info->sid, p_data_info->state,
++			p_data_info->status, p_data_info->burst_num));
++
++		break;
++	case WL_PROXD_TLV_ID_COLLECT_DATA:
++		DHD_RTT(("WL_PROXD_TLV_ID_COLLECT_DATA\n"));
++		memcpy(ctx, p_data, sizeof(wl_proxd_collect_event_data_t));
++		p_collect_data = (wl_proxd_collect_event_data_t *)ctx;
++		DHD_RTT(("\tH_RX\n"));
++		for (i = 0; i < K_TOF_COLLECT_H_SIZE_20MHZ; i++) {
++			p_collect_data->H_RX[i] = ltoh32_ua(&p_collect_data->H_RX[i]);
++			DHD_RTT(("\t%u\n", p_collect_data->H_RX[i]));
++		}
++		DHD_RTT(("\n"));
++		DHD_RTT(("\tH_LB\n"));
++		for (i = 0; i < K_TOF_COLLECT_H_SIZE_20MHZ; i++) {
++			p_collect_data->H_LB[i] = ltoh32_ua(&p_collect_data->H_LB[i]);
++			DHD_RTT(("\t%u\n", p_collect_data->H_LB[i]));
++		}
++		DHD_RTT(("\n"));
++		DHD_RTT(("\tri_rr\n"));
++		for (i = 0; i < FTM_TPK_RI_RR_LEN; i++) {
++			DHD_RTT(("\t%u\n", p_collect_data->ri_rr[i]));
++		}
++		p_collect_data->phy_err_mask = ltoh32_ua(&p_collect_data->phy_err_mask);
++		DHD_RTT(("\tphy_err_mask=0x%x\n", p_collect_data->phy_err_mask));
++		break;
++	case WL_PROXD_TLV_ID_COLLECT_CHAN_DATA:
++		DHD_RTT(("WL_PROXD_TLV_ID_COLLECT_CHAN_DATA\n"));
++		DHD_RTT(("\tchan est %u\n", (uint32) (len / sizeof(uint32))));
++		for (i = 0; i < (len/sizeof(chan_data_entry)); i++) {
++			uint32 *p = (uint32*)p_data;
++			chan_data_entry = ltoh32_ua(p + i);
++			DHD_RTT(("\t%u\n", chan_data_entry));
++		}
++		break;
++	default:
++		DHD_ERROR(("> Unsupported TLV ID %d\n", tlvid));
++		ret = BCME_ERROR;
++		break;
++	}
++
++	return ret;
++}
++
++#ifdef WL_CFG80211
++static int
++rtt_handle_config_options(wl_proxd_session_id_t session_id, wl_proxd_tlv_t **p_tlv,
++	uint16 *p_buf_space_left, ftm_config_options_info_t *ftm_configs, int ftm_cfg_cnt)
++{
++	int ret = BCME_OK;
++	int cfg_idx = 0;
++	uint32 flags = WL_PROXD_FLAG_NONE;
++	uint32 flags_mask = WL_PROXD_FLAG_NONE;
++	uint32 new_mask;		/* cmdline input */
++	ftm_config_options_info_t *p_option_info;
++	uint16 type = (session_id == WL_PROXD_SESSION_ID_GLOBAL) ?
++			WL_PROXD_TLV_ID_FLAGS_MASK : WL_PROXD_TLV_ID_SESSION_FLAGS_MASK;
++	for (cfg_idx = 0; cfg_idx < ftm_cfg_cnt; cfg_idx++) {
++		p_option_info = (ftm_configs + cfg_idx);
++		if (p_option_info != NULL) {
++			new_mask = p_option_info->flags;
++			/* update flags mask */
++			flags_mask |= new_mask;
++			if (p_option_info->enable) {
++				flags |= new_mask;	/* set the bit on */
++			} else {
++				flags &= ~new_mask;	/* set the bit off */
++			}
++		}
++	}
++	flags = htol32(flags);
++	flags_mask = htol32(flags_mask);
++	/* setup flags_mask TLV */
++	ret = bcm_pack_xtlv_entry((uint8 **)p_tlv, p_buf_space_left,
++		type, sizeof(uint32), &flags_mask, BCM_XTLV_OPTION_ALIGN32);
++	if (ret != BCME_OK) {
++		DHD_ERROR(("%s : bcm_pack_xltv_entry() for mask flags failed, status=%d\n",
++			__FUNCTION__, ret));
++		goto exit;
++	}
++
++	type = (session_id == WL_PROXD_SESSION_ID_GLOBAL)?
++		WL_PROXD_TLV_ID_FLAGS : WL_PROXD_TLV_ID_SESSION_FLAGS;
++	/* setup flags TLV */
++	ret = bcm_pack_xtlv_entry((uint8 **)p_tlv, p_buf_space_left,
++			type, sizeof(uint32), &flags, BCM_XTLV_OPTION_ALIGN32);
++		if (ret != BCME_OK) {
++#ifdef RTT_DEBUG
++			DHD_RTT(("%s: bcm_pack_xltv_entry() for flags failed, status=%d\n",
++				__FUNCTION__, ret));
++#endif
++		}
++exit:
++	return ret;
++}
++
++static int
++rtt_handle_config_general(wl_proxd_session_id_t session_id, wl_proxd_tlv_t **p_tlv,
++	uint16 *p_buf_space_left, ftm_config_param_info_t *ftm_configs, int ftm_cfg_cnt)
++{
++	int ret = BCME_OK;
++	int cfg_idx = 0;
++	uint32 chanspec;
++	ftm_config_param_info_t *p_config_param_info;
++	void		*p_src_data;
++	uint16	src_data_size;	/* size of data pointed by p_src_data as 'source' */
++	for (cfg_idx = 0; cfg_idx < ftm_cfg_cnt; cfg_idx++) {
++		p_config_param_info = (ftm_configs + cfg_idx);
++		if (p_config_param_info != NULL) {
++			switch (p_config_param_info->tlvid)	{
++			case WL_PROXD_TLV_ID_BSS_INDEX:
++			case WL_PROXD_TLV_ID_FTM_RETRIES:
++			case WL_PROXD_TLV_ID_FTM_REQ_RETRIES:
++				p_src_data = &p_config_param_info->data8;
++				src_data_size = sizeof(uint8);
++				break;
++			case WL_PROXD_TLV_ID_BURST_NUM_FTM: /* uint16 */
++			case WL_PROXD_TLV_ID_NUM_BURST:
++			case WL_PROXD_TLV_ID_RX_MAX_BURST:
++				p_src_data = &p_config_param_info->data16;
++				src_data_size = sizeof(uint16);
++				break;
++			case WL_PROXD_TLV_ID_TX_POWER:		/* uint32 */
++			case WL_PROXD_TLV_ID_RATESPEC:
++			case WL_PROXD_TLV_ID_EVENT_MASK: /* wl_proxd_event_mask_t/uint32 */
++			case WL_PROXD_TLV_ID_DEBUG_MASK:
++				p_src_data = &p_config_param_info->data32;
++				src_data_size = sizeof(uint32);
++				break;
++			case WL_PROXD_TLV_ID_CHANSPEC:		/* chanspec_t --> 32bit */
++				chanspec = p_config_param_info->chanspec;
++				p_src_data = (void *) &chanspec;
++				src_data_size = sizeof(uint32);
++				break;
++			case WL_PROXD_TLV_ID_BSSID: /* mac address */
++			case WL_PROXD_TLV_ID_PEER_MAC:
++				p_src_data = &p_config_param_info->mac_addr;
++				src_data_size = sizeof(struct ether_addr);
++				break;
++			case WL_PROXD_TLV_ID_BURST_DURATION:	/* wl_proxd_intvl_t */
++			case WL_PROXD_TLV_ID_BURST_PERIOD:
++			case WL_PROXD_TLV_ID_BURST_FTM_SEP:
++			case WL_PROXD_TLV_ID_BURST_TIMEOUT:
++			case WL_PROXD_TLV_ID_INIT_DELAY:
++				p_src_data = &p_config_param_info->data_intvl;
++				src_data_size = sizeof(wl_proxd_intvl_t);
++				break;
++			default:
++				ret = BCME_BADARG;
++				break;
++			}
++			if (ret != BCME_OK) {
++				DHD_ERROR(("%s bad TLV ID : %d\n",
++					__FUNCTION__, p_config_param_info->tlvid));
++				break;
++			}
++
++			ret = bcm_pack_xtlv_entry((uint8 **) p_tlv, p_buf_space_left,
++				p_config_param_info->tlvid, src_data_size, p_src_data,
++				BCM_XTLV_OPTION_ALIGN32);
++			if (ret != BCME_OK) {
++				DHD_ERROR(("%s: bcm_pack_xltv_entry() failed,"
++					" status=%d\n", __FUNCTION__, ret));
++				break;
++			}
++
++		}
++	}
++	return ret;
++}
++
++static int
++dhd_rtt_ftm_enable(dhd_pub_t *dhd, bool enable)
++{
++	ftm_subcmd_info_t subcmd_info;
++	subcmd_info.name = (enable)? "enable" : "disable";
++	subcmd_info.cmdid = (enable)? WL_PROXD_CMD_ENABLE: WL_PROXD_CMD_DISABLE;
++	subcmd_info.handler = NULL;
++	return dhd_rtt_common_set_handler(dhd, &subcmd_info,
++			WL_PROXD_METHOD_FTM, WL_PROXD_SESSION_ID_GLOBAL);
++}
++
++static int
++dhd_rtt_start_session(dhd_pub_t *dhd, wl_proxd_session_id_t session_id, bool start)
++{
++	ftm_subcmd_info_t subcmd_info;
++	subcmd_info.name = (start)? "start session" : "stop session";
++	subcmd_info.cmdid = (start)? WL_PROXD_CMD_START_SESSION: WL_PROXD_CMD_STOP_SESSION;
++	subcmd_info.handler = NULL;
++	return dhd_rtt_common_set_handler(dhd, &subcmd_info,
++			WL_PROXD_METHOD_FTM, session_id);
++}
++
++static int
++dhd_rtt_delete_session(dhd_pub_t *dhd, wl_proxd_session_id_t session_id)
++{
++	ftm_subcmd_info_t subcmd_info;
++	subcmd_info.name = "delete session";
++	subcmd_info.cmdid = WL_PROXD_CMD_DELETE_SESSION;
++	subcmd_info.handler = NULL;
++	return dhd_rtt_common_set_handler(dhd, &subcmd_info,
++			WL_PROXD_METHOD_FTM, session_id);
++}
++
++static int
++dhd_rtt_ftm_config(dhd_pub_t *dhd, wl_proxd_session_id_t session_id,
++	ftm_config_category_t catagory, void *ftm_configs, int ftm_cfg_cnt)
++{
++	ftm_subcmd_info_t subcmd_info;
++	wl_proxd_tlv_t *p_tlv;
++	/* alloc mem for ioctl headr + reserved 0 bufsize for tlvs (initialize to zero) */
++	wl_proxd_iov_t *p_proxd_iov;
++	uint16 proxd_iovsize = 0;
++	uint16 bufsize;
++	uint16 buf_space_left;
++	uint16 all_tlvsize;
++	int ret = BCME_OK;
++
++	subcmd_info.name = "config";
++	subcmd_info.cmdid = WL_PROXD_CMD_CONFIG;
++
++	p_proxd_iov = rtt_alloc_getset_buf(WL_PROXD_METHOD_FTM, session_id, subcmd_info.cmdid,
++		FTM_IOC_BUFSZ, &proxd_iovsize);
++
++	if (p_proxd_iov == NULL) {
++		DHD_ERROR(("%s : failed to allocate the iovar (size :%d)\n",
++			__FUNCTION__, FTM_IOC_BUFSZ));
++		return BCME_NOMEM;
++	}
++	/* setup TLVs */
++	bufsize = proxd_iovsize - WL_PROXD_IOV_HDR_SIZE; /* adjust available size for TLVs */
++	p_tlv = &p_proxd_iov->tlvs[0];
++	/* TLV buffer starts with a full size, will decrement for each packed TLV */
++	buf_space_left = bufsize;
++	if (catagory == FTM_CONFIG_CAT_OPTIONS) {
++		ret = rtt_handle_config_options(session_id, &p_tlv, &buf_space_left,
++				(ftm_config_options_info_t *)ftm_configs, ftm_cfg_cnt);
++	} else if (catagory == FTM_CONFIG_CAT_GENERAL) {
++		ret = rtt_handle_config_general(session_id, &p_tlv, &buf_space_left,
++				(ftm_config_param_info_t *)ftm_configs, ftm_cfg_cnt);
++	}
++	if (ret == BCME_OK) {
++		/* update the iov header, set len to include all TLVs + header */
++		all_tlvsize = (bufsize - buf_space_left);
++		p_proxd_iov->len = htol16(all_tlvsize + WL_PROXD_IOV_HDR_SIZE);
++		ret = dhd_iovar(dhd, 0, "proxd", (char *)p_proxd_iov,
++				all_tlvsize + WL_PROXD_IOV_HDR_SIZE, NULL, 0, TRUE);
++		if (ret != BCME_OK) {
++			DHD_ERROR(("%s : failed to set config\n", __FUNCTION__));
++		}
++	}
++	/* clean up */
++	kfree(p_proxd_iov);
++	return ret;
++}
++
++static int
++dhd_rtt_get_version(dhd_pub_t *dhd, int *out_version)
++{
++	int ret;
++	ftm_subcmd_info_t subcmd_info;
++	subcmd_info.name = "ver";
++	subcmd_info.cmdid = WL_PROXD_CMD_GET_VERSION;
++	subcmd_info.handler = NULL;
++	ret = dhd_rtt_common_get_handler(dhd, &subcmd_info,
++			WL_PROXD_METHOD_FTM, WL_PROXD_SESSION_ID_GLOBAL);
++	*out_version = (ret == BCME_OK) ? subcmd_info.version : 0;
++	return ret;
++}
++#endif /* WL_CFG80211 */
++
++chanspec_t
++dhd_rtt_convert_to_chspec(wifi_channel_info_t channel)
++{
++	int bw;
++	chanspec_t chanspec = 0;
++	uint8 center_chan;
++	uint8 primary_chan;
++	/* set witdh to 20MHZ for 2.4G HZ */
++	if (channel.center_freq >= 2400 && channel.center_freq <= 2500) {
++		channel.width = WIFI_CHAN_WIDTH_20;
++	}
++	switch (channel.width) {
++	case WIFI_CHAN_WIDTH_20:
++		bw = WL_CHANSPEC_BW_20;
++		primary_chan = wf_mhz2channel(channel.center_freq, 0);
++		chanspec = wf_channel2chspec(primary_chan, bw);
++		break;
++	case WIFI_CHAN_WIDTH_40:
++		bw = WL_CHANSPEC_BW_40;
++		primary_chan = wf_mhz2channel(channel.center_freq, 0);
++		chanspec = wf_channel2chspec(primary_chan, bw);
++		break;
++	case WIFI_CHAN_WIDTH_80:
++		bw = WL_CHANSPEC_BW_80;
++		primary_chan = wf_mhz2channel(channel.center_freq, 0);
++		center_chan = wf_mhz2channel(channel.center_freq0, 0);
++		chanspec = wf_chspec_80(center_chan, primary_chan);
++		break;
++	default:
++		DHD_ERROR(("doesn't support this bandwith : %d", channel.width));
++		bw = -1;
++		break;
++	}
++	return chanspec;
++}
++
++int
++dhd_rtt_idx_to_burst_duration(uint idx)
++{
++	if (idx >= ARRAY_SIZE(burst_duration_idx)) {
++		return -1;
++	}
++	return burst_duration_idx[idx];
++}
++
++int
++dhd_rtt_set_cfg(dhd_pub_t *dhd, rtt_config_params_t *params)
++{
++	int err = BCME_OK;
++	int idx;
++	rtt_status_info_t *rtt_status;
++	NULL_CHECK(params, "params is NULL", err);
++
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", err);
++	if (!HAS_11MC_CAP(rtt_status->rtt_capa.proto)) {
++		DHD_ERROR(("doesn't support RTT \n"));
++		return BCME_ERROR;
++	}
++	if (rtt_status->status != RTT_STOPPED) {
++		DHD_ERROR(("rtt is already started\n"));
++		return BCME_BUSY;
++	}
++	DHD_RTT(("%s enter\n", __FUNCTION__));
++
++	memset(rtt_status->rtt_config.target_info, 0, TARGET_INFO_SIZE(RTT_MAX_TARGET_CNT));
++	rtt_status->rtt_config.rtt_target_cnt = params->rtt_target_cnt;
++	memcpy(rtt_status->rtt_config.target_info,
++		params->target_info, TARGET_INFO_SIZE(params->rtt_target_cnt));
++	rtt_status->status = RTT_STARTED;
++	/* start to measure RTT from first device */
++	/* find next target to trigger RTT */
++	for (idx = rtt_status->cur_idx; idx < rtt_status->rtt_config.rtt_target_cnt; idx++) {
++		/* skip the disabled device */
++		if (rtt_status->rtt_config.target_info[idx].disable) {
++			continue;
++		} else {
++			/* set the idx to cur_idx */
++			rtt_status->cur_idx = idx;
++			break;
++		}
++	}
++	if (idx < rtt_status->rtt_config.rtt_target_cnt) {
++		DHD_RTT(("rtt_status->cur_idx : %d\n", rtt_status->cur_idx));
++		schedule_work(&rtt_status->work);
++	}
++	return err;
++}
++
++int
++dhd_rtt_stop(dhd_pub_t *dhd, struct ether_addr *mac_list, int mac_cnt)
++{
++	int err = BCME_OK;
++#ifdef WL_CFG8011
++	int i = 0, j = 0;
++	rtt_status_info_t *rtt_status;
++	rtt_results_header_t *entry, *next;
++	rtt_result_t *rtt_result, *next2;
++	struct rtt_noti_callback *iter;
++
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", err);
++	if (rtt_status->status == RTT_STOPPED) {
++		DHD_ERROR(("rtt is not started\n"));
++		return BCME_OK;
++	}
++	DHD_RTT(("%s enter\n", __FUNCTION__));
++	mutex_lock(&rtt_status->rtt_mutex);
++	for (i = 0; i < mac_cnt; i++) {
++		for (j = 0; j < rtt_status->rtt_config.rtt_target_cnt; j++) {
++			if (!bcmp(&mac_list[i], &rtt_status->rtt_config.target_info[j].addr,
++				ETHER_ADDR_LEN)) {
++				rtt_status->rtt_config.target_info[j].disable = TRUE;
++			}
++		}
++	}
++	if (rtt_status->all_cancel) {
++		/* cancel all of request */
++		rtt_status->status = RTT_STOPPED;
++		DHD_RTT(("current RTT process is cancelled\n"));
++		/* remove the rtt results in cache */
++		if (!list_empty(&rtt_status->rtt_results_cache)) {
++			/* Iterate rtt_results_header list */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++			list_for_each_entry_safe(entry, next,
++				&rtt_status->rtt_results_cache, list) {
++				list_del(&entry->list);
++				/* Iterate rtt_result list */
++				list_for_each_entry_safe(rtt_result, next2,
++					&entry->result_list, list) {
++					list_del(&rtt_result->list);
++					kfree(rtt_result);
++				}
++				kfree(entry);
++			}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++		}
++		/* send the rtt complete event to wake up the user process */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++		list_for_each_entry(iter, &rtt_status->noti_fn_list, list) {
++			iter->noti_fn(iter->ctx, &rtt_status->rtt_results_cache);
++		}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++		/* reinitialize the HEAD */
++		INIT_LIST_HEAD(&rtt_status->rtt_results_cache);
++		/* clear information for rtt_config */
++		rtt_status->rtt_config.rtt_target_cnt = 0;
++		memset(rtt_status->rtt_config.target_info, 0,
++			TARGET_INFO_SIZE(RTT_MAX_TARGET_CNT));
++		rtt_status->cur_idx = 0;
++		dhd_rtt_delete_session(dhd, FTM_DEFAULT_SESSION);
++		dhd_rtt_ftm_enable(dhd, FALSE);
++	}
++	mutex_unlock(&rtt_status->rtt_mutex);
++#endif /* WL_CFG80211 */
++	return err;
++}
++
++
++#ifdef WL_CFG80211
++static int
++dhd_rtt_start(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	char eabuf[ETHER_ADDR_STR_LEN];
++	char chanbuf[CHANSPEC_STR_LEN];
++	int ftm_cfg_cnt = 0;
++	int ftm_param_cnt = 0;
++	uint32 rspec = 0;
++	ftm_config_options_info_t ftm_configs[FTM_MAX_CONFIGS];
++	ftm_config_param_info_t ftm_params[FTM_MAX_PARAMS];
++	rtt_target_info_t *rtt_target;
++	rtt_status_info_t *rtt_status;
++	int pm = PM_OFF;
++	struct net_device *dev = dhd_linux_get_primary_netdev(dhd);
++	NULL_CHECK(dhd, "dhd is NULL", err);
++
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", err);
++
++	DHD_RTT(("Enter %s\n", __FUNCTION__));
++	if (rtt_status->cur_idx >= rtt_status->rtt_config.rtt_target_cnt) {
++		err = BCME_RANGE;
++		DHD_RTT(("%s : idx %d is out of range\n", __FUNCTION__, rtt_status->cur_idx));
++		if (rtt_status->flags == WL_PROXD_SESSION_FLAG_TARGET) {
++			DHD_ERROR(("STA is set as Target/Responder \n"));
++			return BCME_ERROR;
++		}
++		goto exit;
++	}
++	if (RTT_IS_STOPPED(rtt_status)) {
++		DHD_RTT(("RTT is stopped\n"));
++		goto exit;
++	}
++	err = wldev_ioctl_get(dev, WLC_GET_PM, &rtt_status->pm, sizeof(rtt_status->pm));
++	if (err) {
++		DHD_ERROR(("Failed to get the PM value\n"));
++	} else {
++		err = wldev_ioctl_set(dev, WLC_SET_PM, &pm, sizeof(pm));
++		if (err) {
++			DHD_ERROR(("Failed to set the PM\n"));
++			rtt_status->pm_restore = FALSE;
++		} else {
++			rtt_status->pm_restore = TRUE;
++		}
++	}
++
++	mutex_lock(&rtt_status->rtt_mutex);
++	/* Get a target information */
++	rtt_target = &rtt_status->rtt_config.target_info[rtt_status->cur_idx];
++	mutex_unlock(&rtt_status->rtt_mutex);
++	DHD_RTT(("%s enter\n", __FUNCTION__));
++	if (!RTT_IS_ENABLED(rtt_status)) {
++		/* enable ftm */
++		err = dhd_rtt_ftm_enable(dhd, TRUE);
++		if (err) {
++			DHD_ERROR(("failed to enable FTM (%d)\n", err));
++			goto exit;
++		}
++	}
++
++	/* delete session of index default sesession  */
++	err = dhd_rtt_delete_session(dhd, FTM_DEFAULT_SESSION);
++	if (err < 0 && err != BCME_NOTFOUND) {
++		DHD_ERROR(("failed to delete session of FTM (%d)\n", err));
++		goto exit;
++	}
++	rtt_status->status = RTT_ENABLED;
++	memset(ftm_configs, 0, sizeof(ftm_configs));
++	memset(ftm_params, 0, sizeof(ftm_params));
++
++	/* configure the session 1 as initiator */
++	ftm_configs[ftm_cfg_cnt].enable = TRUE;
++	ftm_configs[ftm_cfg_cnt++].flags = WL_PROXD_SESSION_FLAG_INITIATOR;
++	dhd_rtt_ftm_config(dhd, FTM_DEFAULT_SESSION, FTM_CONFIG_CAT_OPTIONS,
++		ftm_configs, ftm_cfg_cnt);
++	/* target's mac address */
++	if (!ETHER_ISNULLADDR(rtt_target->addr.octet)) {
++		ftm_params[ftm_param_cnt].mac_addr = rtt_target->addr;
++		ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_PEER_MAC;
++		bcm_ether_ntoa(&rtt_target->addr, eabuf);
++		DHD_RTT((">\t target %s\n", eabuf));
++	}
++	/* target's chanspec */
++	if (rtt_target->chanspec) {
++		ftm_params[ftm_param_cnt].chanspec = htol32((uint32)rtt_target->chanspec);
++		ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_CHANSPEC;
++		wf_chspec_ntoa(rtt_target->chanspec, chanbuf);
++		DHD_RTT((">\t chanspec : %s\n", chanbuf));
++	}
++	/* num-burst */
++	if (rtt_target->num_burst) {
++		ftm_params[ftm_param_cnt].data16 = htol16(rtt_target->num_burst);
++		ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_NUM_BURST;
++		DHD_RTT((">\t num of burst : %d\n", rtt_target->num_burst));
++	}
++	/* number of frame per burst */
++	if (rtt_target->num_frames_per_burst == 0) {
++		rtt_target->num_frames_per_burst =
++			CHSPEC_IS20(rtt_target->chanspec) ? FTM_DEFAULT_CNT_20M :
++			CHSPEC_IS40(rtt_target->chanspec) ? FTM_DEFAULT_CNT_40M :
++			FTM_DEFAULT_CNT_80M;
++	}
++	ftm_params[ftm_param_cnt].data16 = htol16(rtt_target->num_frames_per_burst);
++	ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_BURST_NUM_FTM;
++	DHD_RTT((">\t number of frame per burst : %d\n", rtt_target->num_frames_per_burst));
++	/* FTM retry count */
++	if (rtt_target->num_retries_per_ftm) {
++		ftm_params[ftm_param_cnt].data8 = rtt_target->num_retries_per_ftm;
++		ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_FTM_RETRIES;
++		DHD_RTT((">\t retry count of FTM  : %d\n", rtt_target->num_retries_per_ftm));
++	}
++	/* FTM Request retry count */
++	if (rtt_target->num_retries_per_ftmr) {
++		ftm_params[ftm_param_cnt].data8 = rtt_target->num_retries_per_ftmr;
++		ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_FTM_REQ_RETRIES;
++		DHD_RTT((">\t retry count of FTM Req : %d\n", rtt_target->num_retries_per_ftmr));
++	}
++	/* burst-period */
++	if (rtt_target->burst_period) {
++		ftm_params[ftm_param_cnt].data_intvl.intvl =
++			htol32(rtt_target->burst_period); /* ms */
++		ftm_params[ftm_param_cnt].data_intvl.tmu = WL_PROXD_TMU_MILLI_SEC;
++		ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_BURST_PERIOD;
++		DHD_RTT((">\t burst period : %d ms\n", rtt_target->burst_period));
++	}
++	/* burst-duration */
++	if (rtt_target->burst_duration) {
++		ftm_params[ftm_param_cnt].data_intvl.intvl =
++			htol32(rtt_target->burst_duration); /* ms */
++		ftm_params[ftm_param_cnt].data_intvl.tmu = WL_PROXD_TMU_MILLI_SEC;
++		ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_BURST_DURATION;
++		DHD_RTT((">\t burst duration : %d ms\n",
++			rtt_target->burst_duration));
++	}
++	if (rtt_target->bw && rtt_target->preamble) {
++		bool use_default = FALSE;
++		int nss;
++		int mcs;
++		switch (rtt_target->preamble) {
++		case RTT_PREAMBLE_LEGACY:
++			rspec |= WL_RSPEC_ENCODE_RATE; /* 11abg */
++			rspec |= WL_RATE_6M;
++			break;
++		case RTT_PREAMBLE_HT:
++			rspec |= WL_RSPEC_ENCODE_HT; /* 11n HT */
++			mcs = 0; /* default MCS 0 */
++			rspec |= mcs;
++			break;
++		case RTT_PREAMBLE_VHT:
++			rspec |= WL_RSPEC_ENCODE_VHT; /* 11ac VHT */
++			mcs = 0; /* default MCS 0 */
++			nss = 1; /* default Nss = 1  */
++			rspec |= (nss << WL_RSPEC_VHT_NSS_SHIFT) | mcs;
++			break;
++		default:
++			DHD_RTT(("doesn't support this preamble : %d\n", rtt_target->preamble));
++			use_default = TRUE;
++			break;
++		}
++		switch (rtt_target->bw) {
++		case RTT_BW_20:
++			rspec |= WL_RSPEC_BW_20MHZ;
++			break;
++		case RTT_BW_40:
++			rspec |= WL_RSPEC_BW_40MHZ;
++			break;
++		case RTT_BW_80:
++			rspec |= WL_RSPEC_BW_80MHZ;
++			break;
++		default:
++			DHD_RTT(("doesn't support this BW : %d\n", rtt_target->bw));
++			use_default = TRUE;
++			break;
++		}
++		if (!use_default) {
++			ftm_params[ftm_param_cnt].data32 = htol32(rspec);
++			ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_RATESPEC;
++			DHD_RTT((">\t ratespec : %d\n", rspec));
++		}
++
++	}
++	dhd_set_rand_mac_oui(dhd);
++	dhd_rtt_ftm_config(dhd, FTM_DEFAULT_SESSION, FTM_CONFIG_CAT_GENERAL,
++		ftm_params, ftm_param_cnt);
++
++	err = dhd_rtt_start_session(dhd, FTM_DEFAULT_SESSION, TRUE);
++	if (err) {
++		DHD_ERROR(("failed to start session of FTM : error %d\n", err));
++	}
++exit:
++	if (err) {
++		DHD_ERROR(("rtt is stopped %s \n", __FUNCTION__));
++		rtt_status->status = RTT_STOPPED;
++		/* disable FTM */
++		dhd_rtt_ftm_enable(dhd, FALSE);
++		if (rtt_status->pm_restore) {
++			DHD_ERROR(("pm_restore =%d func =%s \n",
++				rtt_status->pm_restore, __FUNCTION__));
++			pm = PM_FAST;
++			err = wldev_ioctl_set(dev, WLC_SET_PM, &pm, sizeof(pm));
++			if (err) {
++				DHD_ERROR(("Failed to set PM \n"));
++			} else {
++				rtt_status->pm_restore = FALSE;
++			}
++		}
++	}
++	return err;
++}
++#endif /* WL_CFG80211 */
++
++int
++dhd_rtt_register_noti_callback(dhd_pub_t *dhd, void *ctx, dhd_rtt_compl_noti_fn noti_fn)
++{
++	int err = BCME_OK;
++	struct rtt_noti_callback *cb = NULL, *iter;
++	rtt_status_info_t *rtt_status;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(noti_fn, "noti_fn is NULL", err);
++
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", err);
++	spin_lock_bh(&noti_list_lock);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	list_for_each_entry(iter, &rtt_status->noti_fn_list, list) {
++		if (iter->noti_fn == noti_fn) {
++			goto exit;
++		}
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	cb = kmalloc(sizeof(struct rtt_noti_callback), GFP_ATOMIC);
++	if (!cb) {
++		err = -ENOMEM;
++		goto exit;
++	}
++	cb->noti_fn = noti_fn;
++	cb->ctx = ctx;
++	list_add(&cb->list, &rtt_status->noti_fn_list);
++exit:
++	spin_unlock_bh(&noti_list_lock);
++	return err;
++}
++
++int
++dhd_rtt_unregister_noti_callback(dhd_pub_t *dhd, dhd_rtt_compl_noti_fn noti_fn)
++{
++	int err = BCME_OK;
++	struct rtt_noti_callback *cb = NULL, *iter;
++	rtt_status_info_t *rtt_status;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(noti_fn, "noti_fn is NULL", err);
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", err);
++	spin_lock_bh(&noti_list_lock);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	list_for_each_entry(iter, &rtt_status->noti_fn_list, list) {
++		if (iter->noti_fn == noti_fn) {
++			cb = iter;
++			list_del(&cb->list);
++			break;
++		}
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++	spin_unlock_bh(&noti_list_lock);
++	if (cb) {
++		kfree(cb);
++	}
++	return err;
++}
++
++static wifi_rate_t
++dhd_rtt_convert_rate_to_host(uint32 rspec)
++{
++	wifi_rate_t host_rate;
++	memset(&host_rate, 0, sizeof(wifi_rate_t));
++	if ((rspec & WL_RSPEC_ENCODING_MASK) == WL_RSPEC_ENCODE_RATE) {
++		host_rate.preamble = 0;
++	} else if ((rspec & WL_RSPEC_ENCODING_MASK) == WL_RSPEC_ENCODE_HT) {
++		host_rate.preamble = 2;
++		host_rate.rateMcsIdx = rspec & WL_RSPEC_RATE_MASK;
++	} else if ((rspec & WL_RSPEC_ENCODING_MASK) == WL_RSPEC_ENCODE_VHT) {
++		host_rate.preamble = 3;
++		host_rate.rateMcsIdx = rspec & WL_RSPEC_VHT_MCS_MASK;
++		host_rate.nss = (rspec & WL_RSPEC_VHT_NSS_MASK) >> WL_RSPEC_VHT_NSS_SHIFT;
++	}
++	host_rate.bw = (rspec & WL_RSPEC_BW_MASK) - 1;
++	host_rate.bitrate = rate_rspec2rate(rspec) / 100; /* 100kbps */
++	DHD_RTT(("bit rate : %d\n", host_rate.bitrate));
++	return host_rate;
++}
++
++
++static int
++dhd_rtt_convert_results_to_host(rtt_report_t *rtt_report, uint8 *p_data, uint16 tlvid, uint16 len)
++{
++	int err = BCME_OK;
++	char eabuf[ETHER_ADDR_STR_LEN];
++	wl_proxd_rtt_result_t *p_data_info;
++	wl_proxd_result_flags_t flags;
++	wl_proxd_session_state_t session_state;
++	wl_proxd_status_t proxd_status;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39))
++	struct osl_timespec ts;
++#endif /* LINUX_VER >= 2.6.39 */
++	uint32 ratespec;
++	uint32 avg_dist;
++	wl_proxd_rtt_sample_t *p_sample;
++	wl_proxd_intvl_t rtt;
++	wl_proxd_intvl_t p_time;
++
++	NULL_CHECK(rtt_report, "rtt_report is NULL", err);
++	NULL_CHECK(p_data, "p_data is NULL", err);
++	DHD_RTT(("%s enter\n", __FUNCTION__));
++	p_data_info = (wl_proxd_rtt_result_t *) p_data;
++	/* unpack and format 'flags' for display */
++	flags = ltoh16_ua(&p_data_info->flags);
++
++	/* session state and status */
++	session_state = ltoh16_ua(&p_data_info->state);
++	proxd_status = ltoh32_ua(&p_data_info->status);
++	bcm_ether_ntoa((&(p_data_info->peer)), eabuf);
++	ftm_session_state_value_to_logstr(session_state);
++	ftm_status_value_to_logstr(proxd_status);
++	DHD_RTT((">\tTarget(%s) session state=%d(%s), status=%d(%s)\n",
++		eabuf,
++		session_state,
++		ftm_session_state_value_to_logstr(session_state),
++		proxd_status,
++		ftm_status_value_to_logstr(proxd_status)));
++
++	/* show avg_dist (1/256m units), burst_num */
++	avg_dist = ltoh32_ua(&p_data_info->avg_dist);
++	if (avg_dist == 0xffffffff) {	/* report 'failure' case */
++		DHD_RTT((">\tavg_dist=-1m, burst_num=%d, valid_measure_cnt=%d\n",
++		ltoh16_ua(&p_data_info->burst_num),
++		p_data_info->num_valid_rtt)); /* in a session */
++		avg_dist = FTM_INVALID;
++	}
++	else {
++		DHD_RTT((">\tavg_dist=%d.%04dm, burst_num=%d, valid_measure_cnt=%d num_ftm=%d\n",
++			avg_dist >> 8, /* 1/256m units */
++			((avg_dist & 0xff) * 625) >> 4,
++			ltoh16_ua(&p_data_info->burst_num),
++			p_data_info->num_valid_rtt,
++			p_data_info->num_ftm)); /* in a session */
++	}
++	/* show 'avg_rtt' sample */
++	p_sample = &p_data_info->avg_rtt;
++	ftm_tmu_value_to_logstr(ltoh16_ua(&p_sample->rtt.tmu));
++	DHD_RTT((">\tavg_rtt sample: rssi=%d rtt=%d%s std_deviation =%d.%d ratespec=0x%08x\n",
++		(int16) ltoh16_ua(&p_sample->rssi),
++		ltoh32_ua(&p_sample->rtt.intvl),
++		ftm_tmu_value_to_logstr(ltoh16_ua(&p_sample->rtt.tmu)),
++		ltoh16_ua(&p_data_info->sd_rtt)/10, ltoh16_ua(&p_data_info->sd_rtt)%10,
++		ltoh32_ua(&p_sample->ratespec)));
++
++	/* set peer address */
++	rtt_report->addr = p_data_info->peer;
++	/* burst num */
++	rtt_report->burst_num = ltoh16_ua(&p_data_info->burst_num);
++	/* success num */
++	rtt_report->success_num = p_data_info->num_valid_rtt;
++	/* actual number of FTM supported by peer */
++	rtt_report->num_per_burst_peer = p_data_info->num_ftm;
++	rtt_report->negotiated_burst_num = p_data_info->num_ftm;
++	/* status */
++	rtt_report->status = ftm_get_statusmap_info(proxd_status,
++			&ftm_status_map_info[0], ARRAYSIZE(ftm_status_map_info));
++
++	/* rssi (0.5db) */
++	rtt_report->rssi = ABS((wl_proxd_rssi_t)ltoh16_ua(&p_data_info->avg_rtt.rssi)) * 2;
++
++	/* rx rate */
++	ratespec = ltoh32_ua(&p_data_info->avg_rtt.ratespec);
++	rtt_report->rx_rate = dhd_rtt_convert_rate_to_host(ratespec);
++	/* tx rate */
++	if (flags & WL_PROXD_RESULT_FLAG_VHTACK) {
++		rtt_report->tx_rate = dhd_rtt_convert_rate_to_host(0x2010010);
++	} else {
++		rtt_report->tx_rate = dhd_rtt_convert_rate_to_host(0xc);
++	}
++	/* rtt_sd */
++	rtt.tmu = ltoh16_ua(&p_data_info->avg_rtt.rtt.tmu);
++	rtt.intvl = ltoh32_ua(&p_data_info->avg_rtt.rtt.intvl);
++	rtt_report->rtt = (wifi_timespan)FTM_INTVL2NSEC(&rtt) * 1000; /* nano -> pico seconds */
++	rtt_report->rtt_sd = ltoh16_ua(&p_data_info->sd_rtt); /* nano -> 0.1 nano */
++	DHD_RTT(("rtt_report->rtt : %llu\n", rtt_report->rtt));
++	DHD_RTT(("rtt_report->rssi : %d (0.5db)\n", rtt_report->rssi));
++
++	/* average distance */
++	if (avg_dist != FTM_INVALID) {
++		rtt_report->distance = (avg_dist >> 8) * 1000; /* meter -> mm */
++		rtt_report->distance += (avg_dist & 0xff) * 1000 / 256;
++	} else {
++		rtt_report->distance = FTM_INVALID;
++	}
++	/* time stamp */
++	/* get the time elapsed from boot time */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39))
++	osl_get_monotonic_boottime(&ts);
++	rtt_report->ts = (uint64)TIMESPEC_TO_US(ts);
++#endif /* LINUX_VER >= 2.6.39 */
++
++	if (proxd_status == WL_PROXD_E_REMOTE_FAIL) {
++		/* retry time  after failure */
++		p_time.intvl = ltoh32_ua(&p_data_info->u.retry_after.intvl);
++		p_time.tmu = ltoh16_ua(&p_data_info->u.retry_after.tmu);
++		rtt_report->retry_after_duration = FTM_INTVL2SEC(&p_time); /* s -> s */
++		DHD_RTT((">\tretry_after: %d%s\n",
++			ltoh32_ua(&p_data_info->u.retry_after.intvl),
++			ftm_tmu_value_to_logstr(ltoh16_ua(&p_data_info->u.retry_after.tmu))));
++	} else {
++		/* burst duration */
++		p_time.intvl = ltoh32_ua(&p_data_info->u.retry_after.intvl);
++		p_time.tmu = ltoh16_ua(&p_data_info->u.retry_after.tmu);
++		rtt_report->burst_duration =  FTM_INTVL2MSEC(&p_time); /* s -> ms */
++		DHD_RTT((">\tburst_duration: %d%s\n",
++			ltoh32_ua(&p_data_info->u.burst_duration.intvl),
++			ftm_tmu_value_to_logstr(ltoh16_ua(&p_data_info->u.burst_duration.tmu))));
++		DHD_RTT(("rtt_report->burst_duration : %d\n", rtt_report->burst_duration));
++	}
++	return err;
++}
++
++int
++dhd_rtt_event_handler(dhd_pub_t *dhd, wl_event_msg_t *event, void *event_data)
++{
++	int ret = BCME_OK;
++	int tlvs_len;
++	uint16 version;
++	wl_proxd_event_t *p_event;
++	wl_proxd_event_type_t event_type;
++	wl_proxd_ftm_session_status_t session_status;
++	wl_proxd_collect_event_data_t *collect_event_data;
++	const ftm_strmap_entry_t *p_loginfo;
++	rtt_result_t *rtt_result;
++	gfp_t kflags;
++#ifdef WL_CFG80211
++	int idx;
++	struct rtt_noti_callback *iter;
++	bool is_new = TRUE;
++	rtt_status_info_t *rtt_status;
++	rtt_result_t *next2;
++	rtt_results_header_t *next = NULL;
++	rtt_target_info_t *rtt_target_info;
++	rtt_results_header_t *entry, *rtt_results_header = NULL;
++#endif /* WL_CFG80211 */
++
++	DHD_RTT(("Enter %s \n", __FUNCTION__));
++	NULL_CHECK(dhd, "dhd is NULL", ret);
++
++#ifdef WL_CFG80211
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", ret);
++
++	if (RTT_IS_STOPPED(rtt_status)) {
++		/* Ignore the Proxd event */
++		DHD_RTT((" event handler rtt is stopped \n"));
++		if (rtt_status->flags == WL_PROXD_SESSION_FLAG_TARGET) {
++			DHD_RTT(("Device is target/Responder. Recv the event. \n"));
++		} else {
++			return ret;
++		}
++	}
++#endif /* WL_CFG80211 */
++	if (ntoh32_ua((void *)&event->datalen) < OFFSETOF(wl_proxd_event_t, tlvs)) {
++		DHD_RTT(("%s: wrong datalen:%d\n", __FUNCTION__,
++			ntoh32_ua((void *)&event->datalen)));
++		return -EINVAL;
++	}
++	event_type = ntoh32_ua((void *)&event->event_type);
++	if (event_type != WLC_E_PROXD) {
++		DHD_ERROR((" failed event \n"));
++		return -EINVAL;
++	}
++
++	if (!event_data) {
++		DHD_ERROR(("%s: event_data:NULL\n", __FUNCTION__));
++		return -EINVAL;
++	}
++	p_event = (wl_proxd_event_t *) event_data;
++	version = ltoh16(p_event->version);
++	if (version < WL_PROXD_API_VERSION) {
++		DHD_ERROR(("ignore non-ftm event version = 0x%0x < WL_PROXD_API_VERSION (0x%x)\n",
++			version, WL_PROXD_API_VERSION));
++		return ret;
++	}
++#ifdef WL_CFG80211
++	if (!in_atomic()) {
++		mutex_lock(&rtt_status->rtt_mutex);
++	}
++#endif /* WL_CFG80211 */
++	event_type = (wl_proxd_event_type_t) ltoh16(p_event->type);
++
++	kflags = in_softirq()? GFP_ATOMIC : GFP_KERNEL;
++
++	DHD_RTT(("event_type=0x%x, ntoh16()=0x%x, ltoh16()=0x%x\n",
++		p_event->type, ntoh16(p_event->type), ltoh16(p_event->type)));
++	p_loginfo = ftm_get_event_type_loginfo(event_type);
++	if (p_loginfo == NULL) {
++		DHD_ERROR(("receive an invalid FTM event %d\n", event_type));
++		ret = -EINVAL;
++		goto exit;	/* ignore this event */
++	}
++	/* get TLVs len, skip over event header */
++	if (ltoh16(p_event->len) < OFFSETOF(wl_proxd_event_t, tlvs)) {
++		DHD_ERROR(("invalid FTM event length:%d\n", ltoh16(p_event->len)));
++		ret = -EINVAL;
++		goto exit;
++	}
++	tlvs_len = ltoh16(p_event->len) - OFFSETOF(wl_proxd_event_t, tlvs);
++	DHD_RTT(("receive '%s' event: version=0x%x len=%d method=%d sid=%d tlvs_len=%d\n",
++		p_loginfo->text,
++		version,
++		ltoh16(p_event->len),
++		ltoh16(p_event->method),
++		ltoh16(p_event->sid),
++		tlvs_len));
++#ifdef WL_CFG80211
++	rtt_target_info = &rtt_status->rtt_config.target_info[rtt_status->cur_idx];
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	/* find a rtt_report_header for this mac address */
++	list_for_each_entry(entry, &rtt_status->rtt_results_cache, list) {
++		 if (!memcmp(&entry->peer_mac, &event->addr, ETHER_ADDR_LEN))  {
++			/* found a rtt_report_header for peer_mac in the list */
++			is_new = FALSE;
++			rtt_results_header = entry;
++			break;
++		 }
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++#endif /* WL_CFG80211 */
++	switch (event_type) {
++	case WL_PROXD_EVENT_SESSION_CREATE:
++		DHD_RTT(("WL_PROXD_EVENT_SESSION_CREATE\n"));
++		break;
++	case WL_PROXD_EVENT_SESSION_START:
++		DHD_RTT(("WL_PROXD_EVENT_SESSION_START\n"));
++		break;
++	case WL_PROXD_EVENT_BURST_START:
++		DHD_RTT(("WL_PROXD_EVENT_BURST_START\n"));
++		break;
++	case WL_PROXD_EVENT_BURST_END:
++		DHD_RTT(("WL_PROXD_EVENT_BURST_END\n"));
++#ifdef WL_CFG80211
++		if (is_new) {
++			/* allocate new header for rtt_results */
++			rtt_results_header = kzalloc(sizeof(rtt_results_header_t), kflags);
++			if (!rtt_results_header) {
++				ret = -ENOMEM;
++				goto exit;
++			}
++			/* Initialize the head of list for rtt result */
++			INIT_LIST_HEAD(&rtt_results_header->result_list);
++			rtt_results_header->peer_mac = event->addr;
++			list_add_tail(&rtt_results_header->list, &rtt_status->rtt_results_cache);
++		}
++#endif /* WL_CFG80211 */
++		if (tlvs_len > 0) {
++			/* allocate rtt_results for new results */
++			rtt_result = kzalloc(sizeof(rtt_result_t), kflags);
++			if (!rtt_result) {
++				ret = -ENOMEM;
++				goto exit;
++			}
++			/* unpack TLVs and invokes the cbfn to print the event content TLVs */
++			ret = bcm_unpack_xtlv_buf((void *) &(rtt_result->report),
++				(uint8 *)&p_event->tlvs[0], tlvs_len,
++				BCM_XTLV_OPTION_ALIGN32, rtt_unpack_xtlv_cbfn);
++			if (ret != BCME_OK) {
++				DHD_ERROR(("%s : Failed to unpack xtlv for an event\n",
++					__FUNCTION__));
++				goto exit;
++			}
++#ifdef WL_CFG80211
++			/* fill out the results from the configuration param */
++			rtt_result->report.ftm_num = rtt_target_info->num_frames_per_burst;
++			rtt_result->report.type = RTT_TWO_WAY;
++			DHD_RTT(("report->ftm_num : %d\n", rtt_result->report.ftm_num));
++			rtt_result->report_len = RTT_REPORT_SIZE;
++
++			list_add_tail(&rtt_result->list, &rtt_results_header->result_list);
++			rtt_results_header->result_cnt++;
++			rtt_results_header->result_tot_len += rtt_result->report_len;
++#endif /* WL_CFG80211 */
++		}
++		break;
++	case WL_PROXD_EVENT_SESSION_END:
++			DHD_RTT(("WL_PROXD_EVENT_SESSION_END\n"));
++#ifdef WL_CFG80211
++		if (!RTT_IS_ENABLED(rtt_status)) {
++			DHD_RTT(("Ignore the session end evt\n"));
++			goto exit;
++		}
++#endif /* WL_CFG80211 */
++		if (tlvs_len > 0) {
++			/* unpack TLVs and invokes the cbfn to print the event content TLVs */
++			ret = bcm_unpack_xtlv_buf((void *) &session_status,
++				(uint8 *)&p_event->tlvs[0], tlvs_len,
++				BCM_XTLV_OPTION_ALIGN32, rtt_unpack_xtlv_cbfn);
++			if (ret != BCME_OK) {
++				DHD_ERROR(("%s : Failed to unpack xtlv for an event\n",
++					__FUNCTION__));
++				goto exit;
++			}
++		}
++#ifdef WL_CFG80211
++		/* In case of no result for the peer device, make fake result for error case */
++		if (is_new) {
++			/* allocate new header for rtt_results */
++			rtt_results_header = kzalloc(sizeof(rtt_results_header_t), GFP_KERNEL);
++			if (!rtt_results_header) {
++				ret = -ENOMEM;
++				goto exit;
++			}
++			/* Initialize the head of list for rtt result */
++			INIT_LIST_HEAD(&rtt_results_header->result_list);
++			rtt_results_header->peer_mac = event->addr;
++			list_add_tail(&rtt_results_header->list, &rtt_status->rtt_results_cache);
++
++			/* allocate rtt_results for new results */
++			rtt_result = kzalloc(sizeof(rtt_result_t), kflags);
++			if (!rtt_result) {
++				ret = -ENOMEM;
++				kfree(rtt_results_header);
++				goto exit;
++			}
++			/* fill out the results from the configuration param */
++			rtt_result->report.ftm_num = rtt_target_info->num_frames_per_burst;
++			rtt_result->report.type = RTT_TWO_WAY;
++			DHD_RTT(("report->ftm_num : %d\n", rtt_result->report.ftm_num));
++			rtt_result->report_len = RTT_REPORT_SIZE;
++			rtt_result->report.status = RTT_REASON_FAIL_NO_RSP;
++			rtt_result->report.addr = rtt_target_info->addr;
++			rtt_result->report.distance = FTM_INVALID;
++			list_add_tail(&rtt_result->list, &rtt_results_header->result_list);
++			rtt_results_header->result_cnt++;
++			rtt_results_header->result_tot_len += rtt_result->report_len;
++		}
++		/* find next target to trigger RTT */
++		for (idx = (rtt_status->cur_idx + 1);
++			idx < rtt_status->rtt_config.rtt_target_cnt; idx++) {
++			/* skip the disabled device */
++			if (rtt_status->rtt_config.target_info[idx].disable) {
++				continue;
++			} else {
++				/* set the idx to cur_idx */
++				rtt_status->cur_idx = idx;
++				break;
++			}
++		}
++		if (idx < rtt_status->rtt_config.rtt_target_cnt) {
++			/* restart to measure RTT from next device */
++			DHD_ERROR(("restart to measure rtt\n"));
++			schedule_work(&rtt_status->work);
++		} else {
++			DHD_RTT(("RTT_STOPPED\n"));
++			rtt_status->status = RTT_STOPPED;
++			/* to turn on mpc mode */
++			schedule_work(&rtt_status->work);
++			/* notify the completed information to others */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++			list_for_each_entry(iter, &rtt_status->noti_fn_list, list) {
++				iter->noti_fn(iter->ctx, &rtt_status->rtt_results_cache);
++			}
++			/* remove the rtt results in cache */
++			if (!list_empty(&rtt_status->rtt_results_cache)) {
++				/* Iterate rtt_results_header list */
++				list_for_each_entry_safe(entry, next,
++					&rtt_status->rtt_results_cache, list) {
++					list_del(&entry->list);
++					/* Iterate rtt_result list */
++					list_for_each_entry_safe(rtt_result, next2,
++						&entry->result_list, list) {
++						list_del(&rtt_result->list);
++						kfree(rtt_result);
++					}
++					kfree(entry);
++				}
++			}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++			/* reinitialize the HEAD */
++			INIT_LIST_HEAD(&rtt_status->rtt_results_cache);
++			/* clear information for rtt_config */
++			rtt_status->rtt_config.rtt_target_cnt = 0;
++			memset(rtt_status->rtt_config.target_info, 0,
++				TARGET_INFO_SIZE(RTT_MAX_TARGET_CNT));
++			rtt_status->cur_idx = 0;
++		}
++#endif /* WL_CFG80211 */
++		break;
++	case WL_PROXD_EVENT_SESSION_RESTART:
++		DHD_RTT(("WL_PROXD_EVENT_SESSION_RESTART\n"));
++		break;
++	case WL_PROXD_EVENT_BURST_RESCHED:
++		DHD_RTT(("WL_PROXD_EVENT_BURST_RESCHED\n"));
++		break;
++	case WL_PROXD_EVENT_SESSION_DESTROY:
++		DHD_RTT(("WL_PROXD_EVENT_SESSION_DESTROY\n"));
++		break;
++	case WL_PROXD_EVENT_FTM_FRAME:
++		DHD_RTT(("WL_PROXD_EVENT_FTM_FRAME\n"));
++		break;
++	case WL_PROXD_EVENT_DELAY:
++		DHD_RTT(("WL_PROXD_EVENT_DELAY\n"));
++		break;
++	case WL_PROXD_EVENT_VS_INITIATOR_RPT:
++		DHD_RTT(("WL_PROXD_EVENT_VS_INITIATOR_RPT\n "));
++		break;
++	case WL_PROXD_EVENT_RANGING:
++		DHD_RTT(("WL_PROXD_EVENT_RANGING\n"));
++		break;
++	case WL_PROXD_EVENT_COLLECT:
++		DHD_RTT(("WL_PROXD_EVENT_COLLECT\n"));
++		if (tlvs_len > 0) {
++			collect_event_data = kzalloc(sizeof(wl_proxd_collect_event_data_t), kflags);
++			if (!collect_event_data) {
++				ret = -ENOMEM;
++				goto exit;
++			}
++			/* unpack TLVs and invokes the cbfn to print the event content TLVs */
++			ret = bcm_unpack_xtlv_buf((void *) collect_event_data,
++				(uint8 *)&p_event->tlvs[0], tlvs_len,
++				BCM_XTLV_OPTION_NONE, rtt_unpack_xtlv_cbfn);
++			kfree(collect_event_data);
++			if (ret != BCME_OK) {
++				DHD_ERROR(("%s : Failed to unpack xtlv for an event\n",
++					__FUNCTION__));
++				goto exit;
++			}
++		}
++		break;
++
++
++	default:
++		DHD_ERROR(("WLC_E_PROXD: not supported EVENT Type:%d\n", event_type));
++		break;
++	}
++exit:
++#ifdef WL_CFG80211
++	if (!in_atomic()) {
++		mutex_unlock(&rtt_status->rtt_mutex);
++	}
++#endif /* WL_CFG80211 */
++
++	return ret;
++}
++
++#ifdef WL_CFG80211
++static void
++dhd_rtt_work(struct work_struct *work)
++{
++	rtt_status_info_t *rtt_status;
++	dhd_pub_t *dhd;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	rtt_status = container_of(work, rtt_status_info_t, work);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	if (rtt_status == NULL) {
++		DHD_ERROR(("%s : rtt_status is NULL\n", __FUNCTION__));
++		return;
++	}
++	dhd = rtt_status->dhd;
++	if (dhd == NULL) {
++		DHD_ERROR(("%s : dhd is NULL\n", __FUNCTION__));
++		return;
++	}
++	(void) dhd_rtt_start(dhd);
++}
++#endif /* WL_CFG80211 */
++
++int
++dhd_rtt_capability(dhd_pub_t *dhd, rtt_capabilities_t *capa)
++{
++	rtt_status_info_t *rtt_status;
++	int err = BCME_OK;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", err);
++	NULL_CHECK(capa, "capa is NULL", err);
++	bzero(capa, sizeof(rtt_capabilities_t));
++
++	/* set rtt capabilities */
++	if (rtt_status->rtt_capa.proto & RTT_CAP_ONE_WAY)
++		capa->rtt_one_sided_supported = 1;
++	if (rtt_status->rtt_capa.proto & RTT_CAP_FTM_WAY)
++		capa->rtt_ftm_supported = 1;
++
++	if (rtt_status->rtt_capa.feature & RTT_FEATURE_LCI)
++		capa->lci_support = 1;
++	if (rtt_status->rtt_capa.feature & RTT_FEATURE_LCR)
++		capa->lcr_support = 1;
++	if (rtt_status->rtt_capa.feature & RTT_FEATURE_PREAMBLE)
++		capa->preamble_support = 1;
++	if (rtt_status->rtt_capa.feature & RTT_FEATURE_BW)
++		capa->bw_support = 1;
++
++	/* bit mask */
++	capa->preamble_support = rtt_status->rtt_capa.preamble;
++	capa->bw_support = rtt_status->rtt_capa.bw;
++
++	return err;
++}
++
++#ifdef WL_CFG80211
++int
++dhd_rtt_avail_channel(dhd_pub_t *dhd, wifi_channel_info *channel_info)
++{
++	u32 chanspec = 0;
++	int err = BCME_OK;
++	chanspec_t c = 0;
++	u32 channel;
++	struct net_device *dev = dhd_linux_get_primary_netdev(dhd);
++
++	if ((err = wldev_iovar_getint(dev, "chanspec",
++		(s32 *)&chanspec)) == BCME_OK) {
++		c = (chanspec_t)dtoh32(chanspec);
++		c = wl_chspec_driver_to_host(c);
++		channel  = wf_chspec_ctlchan(c);
++		DHD_RTT((" control channel is %d \n", channel));
++		if (CHSPEC_IS20(c)) {
++			channel_info->width = WIFI_CHAN_WIDTH_20;
++			DHD_RTT((" band is 20 \n"));
++		} else if (CHSPEC_IS40(c)) {
++			channel_info->width = WIFI_CHAN_WIDTH_40;
++			DHD_RTT(("band is 40 \n"));
++		} else {
++			channel_info->width = WIFI_CHAN_WIDTH_80;
++			DHD_RTT(("band is 80 \n"));
++		}
++		if (CHSPEC_IS2G(c) && (channel >= CH_MIN_2G_CHANNEL) &&
++			(channel <= CH_MAX_2G_CHANNEL)) {
++			channel_info->center_freq =
++				ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ);
++		} else if (CHSPEC_IS5G(c) && channel >= CH_MIN_5G_CHANNEL) {
++			channel_info->center_freq =
++				ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ);
++		}
++		if ((channel_info->width == WIFI_CHAN_WIDTH_80) ||
++			(channel_info->width == WIFI_CHAN_WIDTH_40)) {
++			channel = CHSPEC_CHANNEL(c);
++			channel_info->center_freq0 =
++				ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ);
++		}
++	} else {
++		DHD_ERROR(("Failed to get the chanspec \n"));
++	}
++	return err;
++}
++
++int
++dhd_rtt_enable_responder(dhd_pub_t *dhd, wifi_channel_info *channel_info)
++{
++	int err = BCME_OK;
++	char chanbuf[CHANSPEC_STR_LEN];
++	int pm = PM_OFF;
++	int ftm_cfg_cnt = 0;
++	chanspec_t chanspec;
++	wifi_channel_info_t channel;
++	struct net_device *dev = dhd_linux_get_primary_netdev(dhd);
++	ftm_config_options_info_t ftm_configs[FTM_MAX_CONFIGS];
++	ftm_config_param_info_t ftm_params[FTM_MAX_PARAMS];
++	rtt_status_info_t *rtt_status;
++
++	memset(&channel, 0, sizeof(channel));
++	BCM_REFERENCE(chanbuf);
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", err);
++	if (RTT_IS_STOPPED(rtt_status)) {
++		DHD_RTT(("STA responder/Target. \n"));
++	}
++	DHD_RTT(("Enter %s \n", __FUNCTION__));
++	if (!dhd_is_associated(dhd, 0, NULL)) {
++		if (channel_info) {
++			channel.width = channel_info->width;
++			channel.center_freq = channel_info->center_freq;
++			channel.center_freq0 = channel_info->center_freq;
++		}
++		else {
++			channel.width = WIFI_CHAN_WIDTH_80;
++			channel.center_freq = DEFAULT_FTM_FREQ;
++			channel.center_freq0 = DEFAULT_FTM_CNTR_FREQ0;
++		}
++		chanspec =  dhd_rtt_convert_to_chspec(channel);
++		DHD_RTT(("chanspec/channel set as %s for rtt.\n",
++			wf_chspec_ntoa(chanspec, chanbuf)));
++		err = wldev_iovar_setint(dev, "chanspec", chanspec);
++		if (err) {
++			DHD_ERROR(("Failed to set the chanspec \n"));
++		}
++	}
++	err = wldev_ioctl_get(dev, WLC_GET_PM, &rtt_status->pm, sizeof(rtt_status->pm));
++	DHD_RTT(("Current PM value read %d\n", rtt_status->pm));
++	if (err) {
++		DHD_ERROR(("Failed to get the PM value \n"));
++	} else {
++		err = wldev_ioctl_set(dev, WLC_SET_PM, &pm, sizeof(pm));
++		if (err) {
++			DHD_ERROR(("Failed to set the PM \n"));
++			rtt_status->pm_restore = FALSE;
++		} else {
++			rtt_status->pm_restore = TRUE;
++		}
++	}
++	if (!RTT_IS_ENABLED(rtt_status)) {
++		err = dhd_rtt_ftm_enable(dhd, TRUE);
++		if (err) {
++			DHD_ERROR(("Failed to enable FTM (%d)\n", err));
++			goto exit;
++		}
++		DHD_RTT(("FTM enabled \n"));
++	}
++	rtt_status->status = RTT_ENABLED;
++	DHD_RTT(("Responder enabled \n"));
++	memset(ftm_configs, 0, sizeof(ftm_configs));
++	memset(ftm_params, 0, sizeof(ftm_params));
++	ftm_configs[ftm_cfg_cnt].enable = TRUE;
++	ftm_configs[ftm_cfg_cnt++].flags = WL_PROXD_SESSION_FLAG_TARGET;
++	rtt_status->flags = WL_PROXD_SESSION_FLAG_TARGET;
++	DHD_RTT(("Set the device as responder \n"));
++	err = dhd_rtt_ftm_config(dhd, FTM_DEFAULT_SESSION, FTM_CONFIG_CAT_OPTIONS,
++		ftm_configs, ftm_cfg_cnt);
++exit:
++	if (err) {
++		rtt_status->status = RTT_STOPPED;
++		DHD_ERROR(("rtt is stopped  %s \n", __FUNCTION__));
++		dhd_rtt_ftm_enable(dhd, FALSE);
++		DHD_RTT(("restoring the PM value \n"));
++		if (rtt_status->pm_restore) {
++			pm = PM_FAST;
++			err = wldev_ioctl_set(dev, WLC_SET_PM, &pm, sizeof(pm));
++			if (err) {
++				DHD_ERROR(("Failed to restore PM \n"));
++			} else {
++				rtt_status->pm_restore = FALSE;
++			}
++		}
++	}
++	return err;
++}
++
++int
++dhd_rtt_cancel_responder(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	rtt_status_info_t *rtt_status;
++	int pm = 0;
++	struct net_device *dev = dhd_linux_get_primary_netdev(dhd);
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", err);
++	DHD_RTT(("Enter %s \n", __FUNCTION__));
++	err = dhd_rtt_ftm_enable(dhd, FALSE);
++	if (err) {
++		DHD_ERROR(("failed to disable FTM (%d)\n", err));
++	}
++	rtt_status->status = RTT_STOPPED;
++	if (rtt_status->pm_restore) {
++		pm = PM_FAST;
++		DHD_RTT(("pm_restore =%d \n", rtt_status->pm_restore));
++		err = wldev_ioctl_set(dev, WLC_SET_PM, &pm, sizeof(pm));
++		if (err) {
++			DHD_ERROR(("Failed to restore PM \n"));
++		} else {
++			rtt_status->pm_restore = FALSE;
++		}
++	}
++	return err;
++}
++#endif /* WL_CFG80211 */
++
++int
++dhd_rtt_init(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++#ifdef WL_CFG80211
++	int ret;
++	int32 drv_up = 1;
++	int32 version;
++	rtt_status_info_t *rtt_status;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	dhd->rtt_supported = FALSE;
++	if (dhd->rtt_state) {
++		return err;
++	}
++	dhd->rtt_state = kzalloc(sizeof(rtt_status_info_t), GFP_KERNEL);
++	if (dhd->rtt_state == NULL) {
++		err = BCME_NOMEM;
++		DHD_ERROR(("%s : failed to create rtt_state\n", __FUNCTION__));
++		return err;
++	}
++	bzero(dhd->rtt_state, sizeof(rtt_status_info_t));
++	rtt_status = GET_RTTSTATE(dhd);
++	rtt_status->rtt_config.target_info =
++			kzalloc(TARGET_INFO_SIZE(RTT_MAX_TARGET_CNT), GFP_KERNEL);
++	if (rtt_status->rtt_config.target_info == NULL) {
++		DHD_ERROR(("%s failed to allocate the target info for %d\n",
++			__FUNCTION__, RTT_MAX_TARGET_CNT));
++		err = BCME_NOMEM;
++		goto exit;
++	}
++	rtt_status->dhd = dhd;
++	/* need to do WLC_UP  */
++	dhd_wl_ioctl_cmd(dhd, WLC_UP, (char *)&drv_up, sizeof(int32), TRUE, 0);
++
++	ret = dhd_rtt_get_version(dhd, &version);
++	if (ret == BCME_OK && (version == WL_PROXD_API_VERSION)) {
++		DHD_ERROR(("%s : FTM is supported\n", __FUNCTION__));
++		dhd->rtt_supported = TRUE;
++		/* rtt_status->rtt_capa.proto |= RTT_CAP_ONE_WAY; */
++		rtt_status->rtt_capa.proto |= RTT_CAP_FTM_WAY;
++
++		/* indicate to set tx rate */
++		rtt_status->rtt_capa.feature |= RTT_FEATURE_LCI;
++		rtt_status->rtt_capa.feature |= RTT_FEATURE_LCR;
++		rtt_status->rtt_capa.feature |= RTT_FEATURE_PREAMBLE;
++		rtt_status->rtt_capa.preamble |= RTT_PREAMBLE_VHT;
++		rtt_status->rtt_capa.preamble |= RTT_PREAMBLE_HT;
++
++		/* indicate to set bandwith */
++		rtt_status->rtt_capa.feature |= RTT_FEATURE_BW;
++		rtt_status->rtt_capa.bw |= RTT_BW_20;
++		rtt_status->rtt_capa.bw |= RTT_BW_40;
++		rtt_status->rtt_capa.bw |= RTT_BW_80;
++	} else {
++		if ((ret != BCME_OK) || (version == 0)) {
++			DHD_ERROR(("%s : FTM is not supported\n", __FUNCTION__));
++		} else {
++			DHD_ERROR(("%s : FTM version mismatch between HOST (%d) and FW (%d)\n",
++				__FUNCTION__, WL_PROXD_API_VERSION, version));
++		}
++	}
++	/* cancel all of RTT request once we got the cancel request */
++	rtt_status->all_cancel = TRUE;
++	mutex_init(&rtt_status->rtt_mutex);
++	INIT_LIST_HEAD(&rtt_status->noti_fn_list);
++	INIT_LIST_HEAD(&rtt_status->rtt_results_cache);
++	INIT_WORK(&rtt_status->work, dhd_rtt_work);
++exit:
++	if (err < 0) {
++		kfree(rtt_status->rtt_config.target_info);
++		kfree(dhd->rtt_state);
++	}
++#endif /* WL_CFG80211 */
++	return err;
++
++}
++
++int
++dhd_rtt_deinit(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++#ifdef WL_CFG80211
++	rtt_status_info_t *rtt_status;
++	rtt_results_header_t *rtt_header, *next;
++	rtt_result_t *rtt_result, *next2;
++	struct rtt_noti_callback *iter, *iter2;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", err);
++	rtt_status->status = RTT_STOPPED;
++	DHD_RTT(("rtt is stopped %s \n", __FUNCTION__));
++	/* clear evt callback list */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++
++	if (!list_empty(&rtt_status->noti_fn_list)) {
++		list_for_each_entry_safe(iter, iter2, &rtt_status->noti_fn_list, list) {
++			list_del(&iter->list);
++			kfree(iter);
++		}
++	}
++	/* remove the rtt results */
++	if (!list_empty(&rtt_status->rtt_results_cache)) {
++		list_for_each_entry_safe(rtt_header, next, &rtt_status->rtt_results_cache, list) {
++			list_del(&rtt_header->list);
++			list_for_each_entry_safe(rtt_result, next2,
++				&rtt_header->result_list, list) {
++				list_del(&rtt_result->list);
++				kfree(rtt_result);
++			}
++			kfree(rtt_header);
++		}
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	kfree(rtt_status->rtt_config.target_info);
++	kfree(dhd->rtt_state);
++	dhd->rtt_state = NULL;
++#endif /* WL_CFG80211 */
++	return err;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_rtt.h b/module_drivers/drivers/net/wireless/bcmdhd/dhd_rtt.h
+new file mode 100644
+index 000000000..b3ca820b7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_rtt.h
+@@ -0,0 +1,387 @@
++/*
++ * Broadcom Dongle Host Driver (DHD), RTT
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id$
++ */
++#ifndef __DHD_RTT_H__
++#define __DHD_RTT_H__
++
++#include "dngl_stats.h"
++
++#define RTT_MAX_TARGET_CNT 50
++#define RTT_MAX_FRAME_CNT 25
++#define RTT_MAX_RETRY_CNT 10
++#define DEFAULT_FTM_CNT 6
++#define DEFAULT_RETRY_CNT 6
++#define DEFAULT_FTM_FREQ 5180
++#define DEFAULT_FTM_CNTR_FREQ0 5210
++
++#define TARGET_INFO_SIZE(count) (sizeof(rtt_target_info_t) * count)
++
++#define TARGET_TYPE(target) (target->type)
++
++#ifndef BIT
++#define BIT(x) (1 << (x))
++#endif
++
++/* DSSS, CCK and 802.11n rates in [500kbps] units */
++#define WL_MAXRATE	108	/* in 500kbps units */
++#define WL_RATE_1M	2	/* in 500kbps units */
++#define WL_RATE_2M	4	/* in 500kbps units */
++#define WL_RATE_5M5	11	/* in 500kbps units */
++#define WL_RATE_11M	22	/* in 500kbps units */
++#define WL_RATE_6M	12	/* in 500kbps units */
++#define WL_RATE_9M	18	/* in 500kbps units */
++#define WL_RATE_12M	24	/* in 500kbps units */
++#define WL_RATE_18M	36	/* in 500kbps units */
++#define WL_RATE_24M	48	/* in 500kbps units */
++#define WL_RATE_36M	72	/* in 500kbps units */
++#define WL_RATE_48M	96	/* in 500kbps units */
++#define WL_RATE_54M	108	/* in 500kbps units */
++#define GET_RTTSTATE(dhd) ((rtt_status_info_t *)dhd->rtt_state)
++
++enum rtt_role {
++	RTT_INITIATOR = 0,
++	RTT_TARGET = 1
++};
++enum rtt_status {
++	RTT_STOPPED = 0,
++	RTT_STARTED = 1,
++	RTT_ENABLED = 2
++};
++typedef int64_t wifi_timestamp; /* In microseconds (us) */
++typedef int64_t wifi_timespan;
++typedef int32 wifi_rssi_rtt;
++
++typedef enum {
++	RTT_INVALID,
++	RTT_ONE_WAY,
++	RTT_TWO_WAY,
++	RTT_AUTO
++} rtt_type_t;
++
++typedef enum {
++	RTT_PEER_STA,
++	RTT_PEER_AP,
++	RTT_PEER_P2P,
++	RTT_PEER_NAN,
++	RTT_PEER_INVALID
++} rtt_peer_type_t;
++
++typedef enum rtt_reason {
++    RTT_REASON_SUCCESS,
++    RTT_REASON_FAILURE,
++    RTT_REASON_FAIL_NO_RSP,
++    RTT_REASON_FAIL_INVALID_TS, /* Invalid timestamp */
++    RTT_REASON_FAIL_PROTOCOL, /* 11mc protocol failed */
++    RTT_REASON_FAIL_REJECTED,
++    RTT_REASON_FAIL_NOT_SCHEDULED_YET,
++    RTT_REASON_FAIL_SCHEDULE, /* schedule failed */
++    RTT_REASON_FAIL_TM_TIMEOUT,
++    RTT_REASON_FAIL_AP_ON_DIFF_CHANNEL,
++    RTT_REASON_FAIL_NO_CAPABILITY,
++    RTT_REASON_FAIL_BUSY_TRY_LATER,
++    RTT_REASON_ABORTED
++} rtt_reason_t;
++
++enum {
++	RTT_CAP_ONE_WAY	 = BIT(0),
++	/* IEEE802.11mc */
++	RTT_CAP_FTM_WAY  = BIT(1)
++};
++
++enum {
++	RTT_FEATURE_LCI = BIT(0),
++	RTT_FEATURE_LCR = BIT(1),
++	RTT_FEATURE_PREAMBLE = BIT(2),
++	RTT_FEATURE_BW = BIT(3)
++};
++
++enum {
++	RTT_PREAMBLE_LEGACY = BIT(0),
++	RTT_PREAMBLE_HT = BIT(1),
++	RTT_PREAMBLE_VHT = BIT(2)
++};
++
++
++enum {
++	RTT_BW_5 = BIT(0),
++	RTT_BW_10 = BIT(1),
++	RTT_BW_20 = BIT(2),
++	RTT_BW_40 = BIT(3),
++	RTT_BW_80 = BIT(4),
++	RTT_BW_160 = BIT(5)
++};
++#define FTM_MAX_NUM_BURST_EXP	14
++#define HAS_11MC_CAP(cap) (cap & RTT_CAP_FTM_WAY)
++#define HAS_ONEWAY_CAP(cap) (cap & RTT_CAP_ONE_WAY)
++#define HAS_RTT_CAP(cap) (HAS_ONEWAY_CAP(cap) || HAS_11MC_CAP(cap))
++
++typedef struct wifi_channel_info {
++	wifi_channel_width_t width;
++	wifi_channel center_freq; /* primary 20 MHz channel */
++	wifi_channel center_freq0; /* center freq (MHz) first segment */
++	wifi_channel center_freq1; /* center freq (MHz) second segment valid for 80 + 80 */
++} wifi_channel_info_t;
++
++typedef struct wifi_rate {
++	uint32 preamble :3; /* 0: OFDM, 1: CCK, 2 : HT, 3: VHT, 4..7 reserved */
++	uint32 nss		:2; /* 1 : 1x1, 2: 2x2, 3: 3x3, 4: 4x4 */
++	uint32 bw		:3; /* 0: 20Mhz, 1: 40Mhz, 2: 80Mhz, 3: 160Mhz */
++	/* OFDM/CCK rate code would be as per IEEE std in the unit of 0.5 mb
++	* HT/VHT it would be mcs index
++	*/
++	uint32 rateMcsIdx :8;
++	uint32 reserved :16; /* reserved */
++	uint32 bitrate;	/* unit of 100 Kbps */
++} wifi_rate_t;
++
++typedef struct rtt_target_info {
++	struct ether_addr addr;
++	rtt_type_t type; /* rtt_type */
++	rtt_peer_type_t peer; /* peer type */
++	wifi_channel_info_t channel; /* channel information */
++	chanspec_t chanspec; /* chanspec for channel */
++	bool	disable; /* disable for RTT measurement */
++	/*
++	* Time interval between bursts (units: 100 ms).
++	* Applies to 1-sided and 2-sided RTT multi-burst requests.
++	* Range: 0-31, 0: no preference by initiator (2-sided RTT)
++	*/
++	uint32	burst_period;
++	/*
++	* Total number of RTT bursts to be executed. It will be
++	* specified in the same way as the parameter "Number of
++	* Burst Exponent" found in the FTM frame format. It
++	* applies to both: 1-sided RTT and 2-sided RTT. Valid
++	* values are 0 to 15 as defined in 802.11mc std.
++	* 0 means single shot
++	* The implication of this parameter on the maximum
++	* number of RTT results is the following:
++	* for 1-sided RTT: max num of RTT results = (2^num_burst)*(num_frames_per_burst)
++	* for 2-sided RTT: max num of RTT results = (2^num_burst)*(num_frames_per_burst - 1)
++	*/
++	uint16 num_burst;
++	/*
++	* num of frames per burst.
++	* Minimum value = 1, Maximum value = 31
++	* For 2-sided this equals the number of FTM frames
++	* to be attempted in a single burst. This also
++	* equals the number of FTM frames that the
++	* initiator will request that the responder send
++	* in a single frame
++	*/
++    uint32 num_frames_per_burst;
++	/* num of frames in each RTT burst
++	 * for single side, measurement result num = frame number
++	 * for 2 side RTT, measurement result num  = frame number - 1
++	 */
++	uint32 num_retries_per_ftm; /* retry time for RTT measurment frame */
++	/* following fields are only valid for 2 side RTT */
++	uint32 num_retries_per_ftmr;
++	uint8  LCI_request;
++	uint8  LCR_request;
++	/*
++	* Applies to 1-sided and 2-sided RTT. Valid values will
++	* be 2-11 and 15 as specified by the 802.11mc std for
++	* the FTM parameter burst duration. In a multi-burst
++	* request, if responder overrides with larger value,
++	* the initiator will return failure. In a single-burst
++	* request if responder overrides with larger value,
++	* the initiator will sent TMR_STOP to terminate RTT
++	* at the end of the burst_duration it requested.
++	*/
++	uint32 burst_duration;
++	uint8  preamble; /* 1 - Legacy, 2 - HT, 4 - VHT */
++	uint8  bw;  /* 5, 10, 20, 40, 80, 160 */
++} rtt_target_info_t;
++
++typedef struct rtt_config_params {
++	int8 rtt_target_cnt;
++	rtt_target_info_t *target_info;
++} rtt_config_params_t;
++
++typedef struct rtt_status_info {
++    dhd_pub_t *dhd;
++    int8 status;   /* current status for the current entry */
++    int8 txchain; /* current device tx chain */
++    int8 mpc; /* indicate we change mpc mode */
++    int pm; /* to save current value of pm */
++    int8 pm_restore; /* flag to reset the old value of pm */
++    int8 cur_idx; /* current entry to do RTT */
++    bool all_cancel; /* cancel all request once we got the cancel requet */
++    uint32 flags; /* indicate whether device is configured as initiator or target */
++    struct capability {
++		int32 proto     :8;
++		int32 feature   :8;
++		int32 preamble  :8;
++		int32 bw        :8;
++	} rtt_capa; /* rtt capability */
++    struct mutex rtt_mutex;
++    rtt_config_params_t rtt_config;
++    struct work_struct work;
++    struct list_head noti_fn_list;
++    struct list_head rtt_results_cache; /* store results for RTT */
++} rtt_status_info_t;
++
++typedef struct rtt_report {
++	struct ether_addr addr;
++	unsigned int burst_num; /* # of burst inside a multi-burst request */
++	unsigned int ftm_num; /* total RTT measurement frames attempted */
++	unsigned int success_num; /* total successful RTT measurement frames */
++	uint8  num_per_burst_peer; /* max number of FTM number per burst the peer support */
++	rtt_reason_t status; /* raging status */
++	/* in s, 11mc only, only for RTT_REASON_FAIL_BUSY_TRY_LATER, 1- 31s */
++	uint8 retry_after_duration;
++	rtt_type_t type; /* rtt type */
++	wifi_rssi_rtt  rssi; /* average rssi in 0.5 dB steps e.g. 143 implies -71.5 dB */
++	wifi_rssi_rtt  rssi_spread; /* rssi spread in 0.5 db steps e.g. 5 implies 2.5 spread */
++	/*
++	* 1-sided RTT: TX rate of RTT frame.
++	* 2-sided RTT: TX rate of initiator's Ack in response to FTM frame.
++	*/
++	wifi_rate_t tx_rate;
++	/*
++	* 1-sided RTT: TX rate of Ack from other side.
++	* 2-sided RTT: TX rate of FTM frame coming from responder.
++	*/
++	wifi_rate_t rx_rate;
++	wifi_timespan rtt;	/*  round trip time in 0.1 nanoseconds */
++	wifi_timespan rtt_sd;	/* rtt standard deviation in 0.1 nanoseconds */
++	wifi_timespan rtt_spread; /* difference between max and min rtt times recorded */
++	int distance; /* distance in cm (optional) */
++	int distance_sd; /* standard deviation in cm (optional) */
++	int distance_spread; /* difference between max and min distance recorded (optional) */
++	wifi_timestamp ts; /* time of the measurement (in microseconds since boot) */
++	int burst_duration; /* in ms, how long the FW time is to fininish one burst measurement */
++	int negotiated_burst_num; /* Number of bursts allowed by the responder */
++	bcm_tlv_t *LCI; /* LCI Report */
++	bcm_tlv_t *LCR; /* Location Civic Report */
++} rtt_report_t;
++#define RTT_REPORT_SIZE (sizeof(rtt_report_t))
++
++/* rtt_results_header to maintain rtt result list per mac address */
++typedef struct rtt_results_header {
++	struct ether_addr peer_mac;
++	uint32 result_cnt;
++	uint32 result_tot_len; /* sum of report_len of rtt_result */
++	struct list_head list;
++	struct list_head result_list;
++} rtt_results_header_t;
++
++/* rtt_result to link all of rtt_report */
++typedef struct rtt_result {
++	struct list_head list;
++	struct rtt_report report;
++	int32 report_len; /* total length of rtt_report */
++} rtt_result_t;
++
++/* RTT Capabilities */
++typedef struct rtt_capabilities {
++	uint8 rtt_one_sided_supported;  /* if 1-sided rtt data collection is supported */
++	uint8 rtt_ftm_supported;        /* if ftm rtt data collection is supported */
++	uint8 lci_support;		/* location configuration information */
++	uint8 lcr_support;		/* Civic Location */
++	uint8 preamble_support;         /* bit mask indicate what preamble is supported */
++	uint8 bw_support;               /* bit mask indicate what BW is supported */
++} rtt_capabilities_t;
++
++
++/* RTT responder information */
++typedef struct wifi_rtt_responder {
++	wifi_channel_info channel;   /* channel of responder */
++	uint8 preamble;             /* preamble supported by responder */
++} wifi_rtt_responder_t;
++
++typedef void (*dhd_rtt_compl_noti_fn)(void *ctx, void *rtt_data);
++/* Linux wrapper to call common dhd_rtt_set_cfg */
++int
++dhd_dev_rtt_set_cfg(struct net_device *dev, void *buf);
++
++int
++dhd_dev_rtt_cancel_cfg(struct net_device *dev, struct ether_addr *mac_list, int mac_cnt);
++
++int
++dhd_dev_rtt_register_noti_callback(struct net_device *dev, void *ctx,
++	dhd_rtt_compl_noti_fn noti_fn);
++
++int
++dhd_dev_rtt_unregister_noti_callback(struct net_device *dev, dhd_rtt_compl_noti_fn noti_fn);
++
++int
++dhd_dev_rtt_capability(struct net_device *dev, rtt_capabilities_t *capa);
++
++#ifdef WL_CFG80211
++int
++dhd_dev_rtt_avail_channel(struct net_device *dev, wifi_channel_info *channel_info);
++#endif /* WL_CFG80211 */
++
++int
++dhd_dev_rtt_enable_responder(struct net_device *dev, wifi_channel_info *channel_info);
++
++int
++dhd_dev_rtt_cancel_responder(struct net_device *dev);
++/* export to upper layer */
++chanspec_t
++dhd_rtt_convert_to_chspec(wifi_channel_info_t channel);
++
++int
++dhd_rtt_idx_to_burst_duration(uint idx);
++
++int
++dhd_rtt_set_cfg(dhd_pub_t *dhd, rtt_config_params_t *params);
++
++int
++dhd_rtt_stop(dhd_pub_t *dhd, struct ether_addr *mac_list, int mac_cnt);
++
++
++int
++dhd_rtt_register_noti_callback(dhd_pub_t *dhd, void *ctx, dhd_rtt_compl_noti_fn noti_fn);
++
++int
++dhd_rtt_unregister_noti_callback(dhd_pub_t *dhd, dhd_rtt_compl_noti_fn noti_fn);
++
++int
++dhd_rtt_event_handler(dhd_pub_t *dhd, wl_event_msg_t *event, void *event_data);
++
++int
++dhd_rtt_capability(dhd_pub_t *dhd, rtt_capabilities_t *capa);
++
++int
++dhd_rtt_avail_channel(dhd_pub_t *dhd, wifi_channel_info *channel_info);
++
++int
++dhd_rtt_enable_responder(dhd_pub_t *dhd, wifi_channel_info *channel_info);
++
++int
++dhd_rtt_cancel_responder(dhd_pub_t *dhd);
++
++int
++dhd_rtt_init(dhd_pub_t *dhd);
++
++int
++dhd_rtt_deinit(dhd_pub_t *dhd);
++#endif /* __DHD_RTT_H__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_sdio.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_sdio.c
+new file mode 100644
+index 000000000..50637fead
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_sdio.c
+@@ -0,0 +1,10180 @@
++/*
++ * DHD Bus Module for SDIO
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_sdio.c 705650 2017-06-19 03:00:50Z $
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++#include <bcmsdh.h>
++
++#ifdef BCMEMBEDIMAGE
++#include BCMEMBEDIMAGE
++#endif /* BCMEMBEDIMAGE */
++
++#include <bcmdefs.h>
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <bcmdevs.h>
++
++#include <siutils.h>
++#include <hndpmu.h>
++#include <hndsoc.h>
++#include <bcmsdpcm.h>
++#include <hnd_armtrap.h>
++#include <hnd_cons.h>
++#include <sbchipc.h>
++#include <sbhnddma.h>
++
++#include <sdio.h>
++#include <sbsdio.h>
++#include <sbsdpcmdev.h>
++#include <bcmsdpcm.h>
++#include <bcmsdbus.h>
++
++#include <ethernet.h>
++#include <802.1d.h>
++#include <802.11.h>
++
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_bus.h>
++#include <dhd_proto.h>
++#include <dhd_dbg.h>
++#include <dhdioctl.h>
++#include <sdiovar.h>
++#include <dhd_config.h>
++
++#ifdef PROP_TXSTATUS
++#include <dhd_wlfc.h>
++#endif
++#ifdef DHDTCPACK_SUPPRESS
++#include <dhd_ip.h>
++#endif /* DHDTCPACK_SUPPRESS */
++
++#ifdef BT_OVER_SDIO
++#include <dhd_bt_interface.h>
++#endif /* BT_OVER_SDIO */
++
++bool dhd_mp_halting(dhd_pub_t *dhdp);
++extern void bcmsdh_waitfor_iodrain(void *sdh);
++extern void bcmsdh_reject_ioreqs(void *sdh, bool reject);
++extern bool  bcmsdh_fatal_error(void *sdh);
++static int dhdsdio_suspend(void *context);
++static int dhdsdio_resume(void *context);
++
++
++#ifndef DHDSDIO_MEM_DUMP_FNAME
++#define DHDSDIO_MEM_DUMP_FNAME         "mem_dump"
++#endif
++
++#define QLEN		(1024) /* bulk rx and tx queue lengths */
++#define FCHI		(QLEN - 10)
++#define FCLOW		(FCHI / 2)
++#define PRIOMASK	7
++
++#define F0_BLOCK_SIZE 32
++#define TXRETRIES	2	/* # of retries for tx frames */
++#define READ_FRM_CNT_RETRIES	3
++#ifndef DHD_RXBOUND
++#define DHD_RXBOUND	50	/* Default for max rx frames in one scheduling */
++#endif
++
++#ifndef DHD_TXBOUND
++#define DHD_TXBOUND	20	/* Default for max tx frames in one scheduling */
++#endif
++
++#define DHD_TXMINMAX	1	/* Max tx frames if rx still pending */
++
++#define MEMBLOCK	2048		/* Block size used for downloading of dongle image */
++#define MAX_MEMBLOCK  (32 * 1024)	/* Block size used for downloading of dongle image */
++
++#define MAX_DATA_BUF	(64 * 1024)	/* Must be large enough to hold biggest possible glom */
++#define MAX_MEM_BUF	4096
++
++#ifndef DHD_FIRSTREAD
++#define DHD_FIRSTREAD   32
++#endif
++#if !ISPOWEROF2(DHD_FIRSTREAD)
++#error DHD_FIRSTREAD is not a power of 2!
++#endif
++
++/* Total length of frame header for dongle protocol */
++#define SDPCM_HDRLEN	(SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
++#define SDPCM_HDRLEN_TXGLOM	(SDPCM_HDRLEN + SDPCM_HWEXT_LEN)
++#define MAX_TX_PKTCHAIN_CNT	SDPCM_MAXGLOM_SIZE
++
++#ifdef SDTEST
++#define SDPCM_RESERVE	(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
++#else
++#define SDPCM_RESERVE	(SDPCM_HDRLEN + DHD_SDALIGN)
++#endif
++
++/* Space for header read, limit for data packets */
++#ifndef MAX_HDR_READ
++#define MAX_HDR_READ	32
++#endif
++#if !ISPOWEROF2(MAX_HDR_READ)
++#error MAX_HDR_READ is not a power of 2!
++#endif
++
++#define MAX_RX_DATASZ	2048
++
++/* Maximum milliseconds to wait for F2 to come up */
++#define DHD_WAIT_F2RDY	3000
++
++/* Maximum usec to wait for HTAVAIL to come up */
++#define DHD_WAIT_HTAVAIL	10000
++
++/* Bump up limit on waiting for HT to account for first startup;
++ * if the image is doing a CRC calculation before programming the PMU
++ * for HT availability, it could take a couple hundred ms more, so
++ * max out at a 1 second (1000000us).
++ */
++#if (PMU_MAX_TRANSITION_DLY <= 1000000)
++#undef PMU_MAX_TRANSITION_DLY
++#define PMU_MAX_TRANSITION_DLY 1000000
++#endif
++
++/* hooks for limiting threshold custom tx num in rx processing */
++#define DEFAULT_TXINRX_THRES    0
++#ifndef CUSTOM_TXINRX_THRES
++#define CUSTOM_TXINRX_THRES     DEFAULT_TXINRX_THRES
++#endif
++
++/* Value for ChipClockCSR during initial setup */
++#define DHD_INIT_CLKCTL1	(SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ)
++#define DHD_INIT_CLKCTL2	(SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
++
++/* Flags for SDH calls */
++#define F2SYNC	(SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
++
++/* Packet free applicable unconditionally for sdio and sdspi.  Conditional if
++ * bufpool was present for gspi bus.
++ */
++#define PKTFREE2()		if ((bus->bus != SPI_BUS) || bus->usebufpool) \
++					PKTFREE(bus->dhd->osh, pkt, FALSE);
++DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
++
++#ifdef PKT_STATICS
++pkt_statics_t tx_statics = {0};
++#endif
++
++#ifdef SUPPORT_MULTIPLE_BOARD_REV_FROM_HW
++extern unsigned int system_hw_rev;
++#endif /* SUPPORT_MULTIPLE_BOARD_REV_FROM_HW */
++
++/* Device console log buffer state */
++#define CONSOLE_LINE_MAX	192
++#define CONSOLE_BUFFER_MAX	8192
++typedef struct dhd_console {
++	uint		count;			/* Poll interval msec counter */
++	uint		log_addr;		/* Log struct address (fixed) */
++	hnd_log_t	log;			/* Log struct (host copy) */
++	uint		bufsize;		/* Size of log buffer */
++	uint8		*buf;			/* Log buffer (host copy) */
++	uint		last;			/* Last buffer read index */
++} dhd_console_t;
++
++#define	REMAP_ENAB(bus)			((bus)->remap)
++#define	REMAP_ISADDR(bus, a)		(((a) >= ((bus)->orig_ramsize)) && ((a) < ((bus)->ramsize)))
++#define	KSO_ENAB(bus)			((bus)->kso)
++#define	SR_ENAB(bus)			((bus)->_srenab)
++#define	SLPAUTO_ENAB(bus)		((SR_ENAB(bus)) && ((bus)->_slpauto))
++
++#define	MIN_RSRC_SR			0x3
++#define	CORE_CAPEXT_ADDR_OFFSET		(0x64c)
++#define	CORE_CAPEXT_SR_SUPPORTED_MASK	(1 << 1)
++#define RCTL_MACPHY_DISABLE_MASK	(1 << 26)
++#define RCTL_LOGIC_DISABLE_MASK		(1 << 27)
++
++#define	OOB_WAKEUP_ENAB(bus)		((bus)->_oobwakeup)
++#define	GPIO_DEV_SRSTATE		16	/* Host gpio17 mapped to device gpio0 SR state */
++#define	GPIO_DEV_SRSTATE_TIMEOUT	320000	/* 320ms */
++#define	GPIO_DEV_WAKEUP			17	/* Host gpio17 mapped to device gpio1 wakeup */
++#define	CC_CHIPCTRL2_GPIO1_WAKEUP	(1  << 0)
++#define	CC_CHIPCTRL3_SR_ENG_ENABLE	(1  << 2)
++#define OVERFLOW_BLKSZ512_WM		96
++#define OVERFLOW_BLKSZ512_MES		80
++
++#define CC_PMUCC3	(0x3)
++
++#ifdef DHD_UCODE_DOWNLOAD
++/* Ucode host download related macros */
++#define UCODE_DOWNLOAD_REQUEST  0xCAFECAFE
++#define UCODE_DOWNLOAD_COMPLETE 0xABCDABCD
++#endif /* DHD_UCODE_DOWNLOAD */
++
++#if defined(BT_OVER_SDIO)
++#define BTMEM_OFFSET			0x19000000
++/* BIT0 => WLAN Power UP and BIT1=> WLAN Wake */
++#define BT2WLAN_PWRUP_WAKE		0x03
++#define BT2WLAN_PWRUP_ADDR		0x640894	/* This address is specific to 43012B0 */
++
++#define BTFW_MAX_STR_LEN		600
++#define BTFW_DOWNLOAD_BLK_SIZE		(BTFW_MAX_STR_LEN/2 + 8)
++
++#define BTFW_ADDR_MODE_UNKNOWN		0
++#define BTFW_ADDR_MODE_EXTENDED		1
++#define BTFW_ADDR_MODE_SEGMENT		2
++#define BTFW_ADDR_MODE_LINEAR32		3
++
++#define BTFW_HEX_LINE_TYPE_DATA				0
++#define BTFW_HEX_LINE_TYPE_END_OF_DATA			1
++#define BTFW_HEX_LINE_TYPE_EXTENDED_SEGMENT_ADDRESS	2
++#define BTFW_HEX_LINE_TYPE_EXTENDED_ADDRESS		4
++#define BTFW_HEX_LINE_TYPE_ABSOLUTE_32BIT_ADDRESS	5
++
++#endif /* defined (BT_OVER_SDIO) */
++
++/* Private data for SDIO bus interaction */
++typedef struct dhd_bus {
++	dhd_pub_t	*dhd;
++
++	bcmsdh_info_t	*sdh;			/* Handle for BCMSDH calls */
++	si_t		*sih;			/* Handle for SI calls */
++	char		*vars;			/* Variables (from CIS and/or other) */
++	uint		varsz;			/* Size of variables buffer */
++	uint32		sbaddr;			/* Current SB window pointer (-1, invalid) */
++
++	sdpcmd_regs_t	*regs;			/* Registers for SDIO core */
++	uint		sdpcmrev;		/* SDIO core revision */
++	uint		armrev;			/* CPU core revision */
++	uint		ramrev;			/* SOCRAM core revision */
++	uint32		ramsize;		/* Size of RAM in SOCRAM (bytes) */
++	uint32		orig_ramsize;		/* Size of RAM in SOCRAM (bytes) */
++	uint32		srmemsize;		/* Size of SRMEM */
++
++	uint32		bus;			/* gSPI or SDIO bus */
++	uint32		bus_num;		/* bus number */
++	uint32		slot_num;		/* slot ID */
++	uint32		hostintmask;	/* Copy of Host Interrupt Mask */
++	uint32		intstatus;		/* Intstatus bits (events) pending */
++	bool		dpc_sched;		/* Indicates DPC schedule (intrpt rcvd) */
++	bool		fcstate;		/* State of dongle flow-control */
++
++	uint16		cl_devid;		/* cached devid for dhdsdio_probe_attach() */
++	char		*fw_path;		/* module_param: path to firmware image */
++	char		*nv_path;		/* module_param: path to nvram vars file */
++
++	uint		blocksize;		/* Block size of SDIO transfers */
++	uint		roundup;		/* Max roundup limit */
++
++	struct pktq	txq;			/* Queue length used for flow-control */
++	uint8		flowcontrol;		/* per prio flow control bitmask */
++	uint8		tx_seq;			/* Transmit sequence number (next) */
++	uint8		tx_max;			/* Maximum transmit sequence allowed */
++
++	uint8		hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
++	uint8		*rxhdr;			/* Header of current rx frame (in hdrbuf) */
++	uint16		nextlen;		/* Next Read Len from last header */
++	uint8		rx_seq;			/* Receive sequence number (expected) */
++	bool		rxskip;			/* Skip receive (awaiting NAK ACK) */
++
++	void		*glomd;			/* Packet containing glomming descriptor */
++	void		*glom;			/* Packet chain for glommed superframe */
++	uint		glomerr;		/* Glom packet read errors */
++
++	uint8		*rxbuf;			/* Buffer for receiving control packets */
++	uint		rxblen;			/* Allocated length of rxbuf */
++	uint8		*rxctl;			/* Aligned pointer into rxbuf */
++	uint8		*databuf;		/* Buffer for receiving big glom packet */
++	uint8		*dataptr;		/* Aligned pointer into databuf */
++	uint		rxlen;			/* Length of valid data in buffer */
++
++	uint8		sdpcm_ver;		/* Bus protocol reported by dongle */
++
++	bool		intr;			/* Use interrupts */
++	bool		poll;			/* Use polling */
++	bool		ipend;			/* Device interrupt is pending */
++	bool		intdis;			/* Interrupts disabled by isr */
++	uint 		intrcount;		/* Count of device interrupt callbacks */
++	uint		lastintrs;		/* Count as of last watchdog timer */
++	uint		spurious;		/* Count of spurious interrupts */
++	uint		pollrate;		/* Ticks between device polls */
++	uint		polltick;		/* Tick counter */
++	uint		pollcnt;		/* Count of active polls */
++
++	dhd_console_t	console;		/* Console output polling support */
++	uint		console_addr;		/* Console address from shared struct */
++
++	uint		regfails;		/* Count of R_REG/W_REG failures */
++
++	uint		clkstate;		/* State of sd and backplane clock(s) */
++	bool		activity;		/* Activity flag for clock down */
++	int32		idletime;		/* Control for activity timeout */
++	int32		idlecount;		/* Activity timeout counter */
++	int32		idleclock;		/* How to set bus driver when idle */
++	int32		sd_divisor;		/* Speed control to bus driver */
++	int32		sd_mode;		/* Mode control to bus driver */
++	int32		sd_rxchain;		/* If bcmsdh api accepts PKT chains */
++	bool		use_rxchain;		/* If dhd should use PKT chains */
++	bool		sleeping;		/* Is SDIO bus sleeping? */
++#if defined(SUPPORT_P2P_GO_PS)
++	wait_queue_head_t bus_sleep;
++#endif /* LINUX && SUPPORT_P2P_GO_PS */
++	bool		ctrl_wait;
++	wait_queue_head_t ctrl_tx_wait;
++	uint		rxflow_mode;		/* Rx flow control mode */
++	bool		rxflow;			/* Is rx flow control on */
++	uint		prev_rxlim_hit;		/* Is prev rx limit exceeded (per dpc schedule) */
++	bool		alp_only;		/* Don't use HT clock (ALP only) */
++	/* Field to decide if rx of control frames happen in rxbuf or lb-pool */
++	bool		usebufpool;
++	int32		txinrx_thres;	/* num of in-queued pkts */
++	int32		dotxinrx;	/* tx first in dhdsdio_readframes */
++#ifdef BCMSDIO_RXLIM_POST
++	bool		rxlim_en;
++	uint32		rxlim_addr;
++#endif /* BCMSDIO_RXLIM_POST */
++#ifdef SDTEST
++	/* external loopback */
++	bool		ext_loop;
++	uint8		loopid;
++
++	/* pktgen configuration */
++	uint		pktgen_freq;		/* Ticks between bursts */
++	uint		pktgen_count;		/* Packets to send each burst */
++	uint		pktgen_print;		/* Bursts between count displays */
++	uint		pktgen_total;		/* Stop after this many */
++	uint		pktgen_minlen;		/* Minimum packet data len */
++	uint		pktgen_maxlen;		/* Maximum packet data len */
++	uint		pktgen_mode;		/* Configured mode: tx, rx, or echo */
++	uint		pktgen_stop;		/* Number of tx failures causing stop */
++
++	/* active pktgen fields */
++	uint		pktgen_tick;		/* Tick counter for bursts */
++	uint		pktgen_ptick;		/* Burst counter for printing */
++	uint		pktgen_sent;		/* Number of test packets generated */
++	uint		pktgen_rcvd;		/* Number of test packets received */
++	uint		pktgen_prev_time;	/* Time at which previous stats where printed */
++	uint		pktgen_prev_sent;	/* Number of test packets generated when
++						 * previous stats were printed
++						 */
++	uint		pktgen_prev_rcvd;	/* Number of test packets received when
++						 * previous stats were printed
++						 */
++	uint		pktgen_fail;		/* Number of failed send attempts */
++	uint16		pktgen_len;		/* Length of next packet to send */
++#define PKTGEN_RCV_IDLE     (0)
++#define PKTGEN_RCV_ONGOING  (1)
++	uint16		pktgen_rcv_state;		/* receive state */
++	uint		pktgen_rcvd_rcvsession;	/* test pkts rcvd per rcv session. */
++#endif /* SDTEST */
++
++	/* Some additional counters */
++	uint		tx_sderrs;		/* Count of tx attempts with sd errors */
++	uint		fcqueued;		/* Tx packets that got queued */
++	uint		rxrtx;			/* Count of rtx requests (NAK to dongle) */
++	uint		rx_toolong;		/* Receive frames too long to receive */
++	uint		rxc_errors;		/* SDIO errors when reading control frames */
++	uint		rx_hdrfail;		/* SDIO errors on header reads */
++	uint		rx_badhdr;		/* Bad received headers (roosync?) */
++	uint		rx_badseq;		/* Mismatched rx sequence number */
++	uint		fc_rcvd;		/* Number of flow-control events received */
++	uint		fc_xoff;		/* Number which turned on flow-control */
++	uint		fc_xon;			/* Number which turned off flow-control */
++	uint		rxglomfail;		/* Failed deglom attempts */
++	uint		rxglomframes;		/* Number of glom frames (superframes) */
++	uint		rxglompkts;		/* Number of packets from glom frames */
++	uint		f2rxhdrs;		/* Number of header reads */
++	uint		f2rxdata;		/* Number of frame data reads */
++	uint		f2txdata;		/* Number of f2 frame writes */
++	uint		f1regdata;		/* Number of f1 register accesses */
++	wake_counts_t	wake_counts;		/* Wake up counter */
++#ifdef DHDENABLE_TAILPAD
++	uint		tx_tailpad_chain;	/* Number of tail padding by chaining pad_pkt */
++	uint		tx_tailpad_pktget;	/* Number of tail padding by new PKTGET */
++#endif /* DHDENABLE_TAILPAD */
++	uint8		*ctrl_frame_buf;
++	uint32		ctrl_frame_len;
++	bool		ctrl_frame_stat;
++	uint32		rxint_mode;	/* rx interrupt mode */
++	bool		remap;		/* Contiguous 1MB RAM: 512K socram + 512K devram
++					 * Available with socram rev 16
++					 * Remap region not DMA-able
++					 */
++	bool		kso;
++	bool		_slpauto;
++	bool		_oobwakeup;
++	bool		_srenab;
++	bool        readframes;
++	bool        reqbussleep;
++	uint32		resetinstr;
++	uint32		dongle_ram_base;
++
++	void		*glom_pkt_arr[SDPCM_MAXGLOM_SIZE];	/* Array of pkts for glomming */
++	uint32		txglom_cnt;	/* Number of pkts in the glom array */
++	uint32		txglom_total_len;	/* Total length of pkts in glom array */
++	bool		txglom_enable;	/* Flag to indicate whether tx glom is enabled/disabled */
++	uint32		txglomsize;	/* Glom size limitation */
++#ifdef DHDENABLE_TAILPAD
++	void		*pad_pkt;
++#endif /* DHDENABLE_TAILPAD */
++	uint32		dongle_trap_addr; /* device trap addr location in device memory */
++#if defined(BT_OVER_SDIO)
++	char		*btfw_path;	/* module_param: path to BT firmware image */
++	uint32		bt_use_count; /* Counter that tracks whether BT is using the bus */
++#endif /* defined (BT_OVER_SDIO) */
++	uint		txglomframes;	/* Number of tx glom frames (superframes) */
++	uint		txglompkts;		/* Number of packets from tx glom frames */
++	uint8		*membuf;		/* Buffer for dhdsdio_membytes */
++#ifdef CONSOLE_DPC
++	char		cons_cmd[16];
++#endif
++} dhd_bus_t;
++
++
++/*
++ * Whenever DHD_IDLE_IMMEDIATE condition is handled, we have to now check if
++ * BT is active too. Instead of adding #ifdef code in all the places, we thought
++ * of adding one macro check as part of the if condition that checks for DHD_IDLE_IMMEDIATE
++ * In case of non BT over SDIO builds, this macro will always return TRUE. In case
++ * of the builds where BT_OVER_SDIO is enabled, it will expand to a condition check
++ * that checks if bt_use_count is zero. So this macro will return equate to 1 if
++ * bt_use_count is 0, indicating that there are no active users and if bt_use_count
++ * is non zero it would return 0 there by preventing the caller from executing the
++ * sleep calls.
++ */
++#ifdef BT_OVER_SDIO
++#define NO_OTHER_ACTIVE_BUS_USER(bus)		(bus->bt_use_count == 0)
++#else
++#define NO_OTHER_ACTIVE_BUS_USER(bus)		(1)
++#endif /* BT_OVER_SDIO */
++
++/* clkstate */
++#define CLK_NONE	0
++#define CLK_SDONLY	1
++#define CLK_PENDING	2	/* Not used yet */
++#define CLK_AVAIL	3
++
++#define DHD_NOPMU(dhd)	(FALSE)
++
++#if defined(BCMSDIOH_STD)
++#define BLK_64_MAXTXGLOM 20
++#endif /* BCMSDIOH_STD */
++
++#ifdef DHD_DEBUG
++static int qcount[NUMPRIO];
++static int tx_packets[NUMPRIO];
++#endif /* DHD_DEBUG */
++
++/* Deferred transmit */
++const uint dhd_deferred_tx = 1;
++
++extern uint dhd_watchdog_ms;
++extern uint sd_f1_blocksize;
++
++
++#if defined(BT_OVER_SDIO)
++extern dhd_pub_t	*g_dhd_pub;
++#endif /* (BT_OVER_SDIO) */
++extern void dhd_os_wd_timer(void *bus, uint wdtick);
++int dhd_enableOOB(dhd_pub_t *dhd, bool sleep);
++
++
++/* Tx/Rx bounds */
++uint dhd_txbound;
++uint dhd_rxbound;
++uint dhd_txminmax = DHD_TXMINMAX;
++
++/* override the RAM size if possible */
++#define DONGLE_MIN_RAMSIZE (128 *1024)
++int dhd_dongle_ramsize;
++
++uint dhd_doflow = TRUE;
++uint dhd_dpcpoll = FALSE;
++
++module_param(dhd_doflow, uint, 0644);
++module_param(dhd_dpcpoll, uint, 0644);
++
++static bool dhd_alignctl;
++
++static bool sd1idle;
++
++static bool retrydata;
++#define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
++
++static uint watermark = 8;
++static uint mesbusyctrl = 0;
++static const uint firstread = DHD_FIRSTREAD;
++
++/* Retry count for register access failures */
++static const uint retry_limit = 2;
++
++/* Force even SD lengths (some host controllers mess up on odd bytes) */
++static bool forcealign;
++
++#define ALIGNMENT  4
++
++#if (defined(OOB_INTR_ONLY) && defined(HW_OOB)) || defined(FORCE_WOWLAN)
++extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
++#endif
++
++#if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
++#error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
++#endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
++#define PKTALIGN(osh, p, len, align)					\
++	do {								\
++		uintptr datalign;						\
++		datalign = (uintptr)PKTDATA((osh), (p));		\
++		datalign = ROUNDUP(datalign, (align)) - datalign;	\
++		ASSERT(datalign < (align));				\
++		ASSERT(PKTLEN((osh), (p)) >= ((len) + datalign));	\
++		if (datalign)						\
++			PKTPULL((osh), (p), (uint)datalign);			\
++		PKTSETLEN((osh), (p), (len));				\
++	} while (0)
++
++/* Limit on rounding up frames */
++static const uint max_roundup = 512;
++
++/* Try doing readahead */
++static bool dhd_readahead;
++
++#if defined(BCMSDIOH_TXGLOM_EXT)
++bool
++dhdsdio_is_dataok(dhd_bus_t *bus) {
++	return (((uint8)(bus->tx_max - bus->tx_seq) - bus->dhd->conf->tx_max_offset > 1) && \
++	(((uint8)(bus->tx_max - bus->tx_seq) & 0x80) == 0));
++}
++
++uint8
++dhdsdio_get_databufcnt(dhd_bus_t *bus) {
++	return ((uint8)(bus->tx_max - bus->tx_seq) - 1 - bus->dhd->conf->tx_max_offset);
++}
++#endif
++
++/* To check if there's window offered */
++#if defined(BCMSDIOH_TXGLOM_EXT)
++#define DATAOK(bus) dhdsdio_is_dataok(bus)
++#else
++#define DATAOK(bus) \
++	(((uint8)(bus->tx_max - bus->tx_seq) > 1) && \
++	(((uint8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
++#endif
++
++/* To check if there's window offered for ctrl frame */
++#define TXCTLOK(bus) \
++	(((uint8)(bus->tx_max - bus->tx_seq) != 0) && \
++	(((uint8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
++
++/* Number of pkts available in dongle for data RX */
++#if defined(BCMSDIOH_TXGLOM_EXT)
++#define DATABUFCNT(bus) dhdsdio_get_databufcnt(bus)
++#else
++#define DATABUFCNT(bus) \
++	((uint8)(bus->tx_max - bus->tx_seq) - 1)
++#endif
++
++/* Macros to get register read/write status */
++/* NOTE: these assume a local dhdsdio_bus_t *bus! */
++#define R_SDREG(regvar, regaddr, retryvar) \
++do { \
++	retryvar = 0; \
++	do { \
++		regvar = R_REG(bus->dhd->osh, regaddr); \
++	} while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
++	if (retryvar) { \
++		bus->regfails += (retryvar-1); \
++		if (retryvar > retry_limit) { \
++			DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
++			           __FUNCTION__, __LINE__)); \
++			regvar = 0; \
++		} \
++	} \
++} while (0)
++
++#define W_SDREG(regval, regaddr, retryvar) \
++do { \
++	retryvar = 0; \
++	do { \
++		W_REG(bus->dhd->osh, regaddr, regval); \
++	} while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
++	if (retryvar) { \
++		bus->regfails += (retryvar-1); \
++		if (retryvar > retry_limit) \
++			DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
++			           __FUNCTION__, __LINE__)); \
++	} \
++} while (0)
++
++#define BUS_WAKE(bus) \
++	do { \
++		bus->idlecount = 0; \
++		if ((bus)->sleeping) \
++			dhdsdio_bussleep((bus), FALSE); \
++	} while (0);
++
++/*
++ * pktavail interrupts from dongle to host can be managed in 3 different ways
++ * whenever there is a packet available in dongle to transmit to host.
++ *
++ * Mode 0:	Dongle writes the software host mailbox and host is interrupted.
++ * Mode 1:	(sdiod core rev >= 4)
++ *		Device sets a new bit in the intstatus whenever there is a packet
++ *		available in fifo.  Host can't clear this specific status bit until all the
++ *		packets are read from the FIFO.  No need to ack dongle intstatus.
++ * Mode 2:	(sdiod core rev >= 4)
++ *		Device sets a bit in the intstatus, and host acks this by writing
++ *		one to this bit.  Dongle won't generate anymore packet interrupts
++ *		until host reads all the packets from the dongle and reads a zero to
++ *		figure that there are no more packets.  No need to disable host ints.
++ *		Need to ack the intstatus.
++ */
++
++#define SDIO_DEVICE_HMB_RXINT		0	/* default old way */
++#define SDIO_DEVICE_RXDATAINT_MODE_0	1	/* from sdiod rev 4 */
++#define SDIO_DEVICE_RXDATAINT_MODE_1	2	/* from sdiod rev 4 */
++
++
++#define FRAME_AVAIL_MASK(bus) 	\
++	((bus->rxint_mode == SDIO_DEVICE_HMB_RXINT) ? I_HMB_FRAME_IND : I_XMTDATA_AVAIL)
++
++#define DHD_BUS			SDIO_BUS
++
++#define PKT_AVAILABLE(bus, intstatus)	((intstatus) & (FRAME_AVAIL_MASK(bus)))
++
++#define HOSTINTMASK		(I_HMB_SW_MASK | I_CHIPACTIVE)
++
++#define GSPI_PR55150_BAILOUT
++
++#ifdef SDTEST
++static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
++static void dhdsdio_sdtest_set(dhd_bus_t *bus, uint count);
++#endif
++
++static int dhdsdio_checkdied(dhd_bus_t *bus, char *data, uint size);
++#ifdef DHD_DEBUG
++static int dhd_serialconsole(dhd_bus_t *bus, bool get, bool enable, int *bcmerror);
++#endif /* DHD_DEBUG */
++
++#if defined(DHD_FW_COREDUMP)
++static int dhdsdio_mem_dump(dhd_bus_t *bus);
++#endif /* DHD_FW_COREDUMP */
++static int dhdsdio_devcap_set(dhd_bus_t *bus, uint8 cap);
++static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
++
++static void dhdsdio_release(dhd_bus_t *bus, osl_t *osh);
++static void dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh);
++static void dhdsdio_disconnect(void *ptr);
++static bool dhdsdio_chipmatch(uint16 chipid);
++static bool dhdsdio_probe_attach(dhd_bus_t *bus, osl_t *osh, void *sdh,
++                                 void * regsva, uint16  devid);
++static bool dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh);
++static bool dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh);
++static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t *osh, bool dongle_isolation,
++	bool reset_flag);
++
++static void dhd_dongle_setramsize(struct dhd_bus *bus, int mem_size);
++static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags,
++	uint8 *buf, uint nbytes,
++	void *pkt, bcmsdh_cmplt_fn_t complete, void *handle);
++static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags,
++	uint8 *buf, uint nbytes,
++	void *pkt, bcmsdh_cmplt_fn_t complete, void *handle, int max_retry);
++static int dhdsdio_txpkt(dhd_bus_t *bus, uint chan, void** pkts, int num_pkt, bool free_pkt);
++static int dhdsdio_txpkt_preprocess(dhd_bus_t *bus, void *pkt, int chan, int txseq,
++	int prev_chain_total_len, bool last_chained_pkt,
++	int *pad_pkt_len, void **new_pkt
++#if defined(BCMSDIOH_TXGLOM_EXT)
++	, int first_frame
++#endif
++);
++static int dhdsdio_txpkt_postprocess(dhd_bus_t *bus, void *pkt);
++
++static int dhdsdio_download_firmware(dhd_bus_t *bus, osl_t *osh, void *sdh);
++static int _dhdsdio_download_firmware(dhd_bus_t *bus);
++
++#ifdef DHD_UCODE_DOWNLOAD
++static int dhdsdio_download_ucode_file(struct dhd_bus *bus, char *ucode_path);
++#endif /* DHD_UCODE_DOWNLOAD */
++static int dhdsdio_download_code_file(dhd_bus_t *bus, char *image_path);
++static int dhdsdio_download_nvram(dhd_bus_t *bus);
++#ifdef BCMEMBEDIMAGE
++static int dhdsdio_download_code_array(dhd_bus_t *bus);
++#endif
++static int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep);
++static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok);
++static uint8 dhdsdio_sleepcsr_get(dhd_bus_t *bus);
++static bool dhdsdio_dpc(dhd_bus_t *bus);
++static int dhd_bcmsdh_send_buffer(void *bus, uint8 *frame, uint16 len);
++static int dhdsdio_set_sdmode(dhd_bus_t *bus, int32 sd_mode);
++static int dhdsdio_sdclk(dhd_bus_t *bus, bool on);
++static void dhdsdio_advertise_bus_cleanup(dhd_pub_t *dhdp);
++static void dhdsdio_advertise_bus_remove(dhd_pub_t *dhdp);
++#ifdef SUPPORT_MULTIPLE_BOARD_REV_FROM_DT
++int dhd_get_system_rev(void);
++#endif /* SUPPORT_MULTIPLE_BOARD_REV_FROM_DT */
++
++#ifdef WLMEDIA_HTSF
++#include <htsf.h>
++extern uint32 dhd_get_htsf(void *dhd, int ifidx);
++#endif /* WLMEDIA_HTSF */
++
++#if defined(BT_OVER_SDIO)
++static int extract_hex_field(char * line, uint16 start_pos, uint16 num_chars, uint16 * value);
++static int read_more_btbytes(struct dhd_bus *bus, void * file, char *line, int * addr_mode,
++	uint16 * hi_addr, uint32 * dest_addr, uint8 *data_bytes, uint32 * num_bytes);
++static int dhdsdio_download_btfw(struct dhd_bus *bus, osl_t *osh, void *sdh);
++static int _dhdsdio_download_btfw(struct dhd_bus *bus);
++#endif /* defined (BT_OVER_SDIO) */
++
++#ifdef DHD_ULP
++#include <dhd_ulp.h>
++static int dhd_bus_ulp_reinit_fw(dhd_bus_t *bus);
++#endif /* DHD_ULP */
++
++#ifdef DHD_WAKE_STATUS
++int bcmsdh_get_total_wake(bcmsdh_info_t *bcmsdh);
++int bcmsdh_set_get_wake(bcmsdh_info_t *bcmsdh, int flag);
++#endif /* DHD_WAKE_STATUS */
++
++static void
++dhdsdio_tune_fifoparam(struct dhd_bus *bus)
++{
++	int err;
++	uint8 devctl, wm, mes;
++
++	if (bus->sih->buscorerev >= 15) {
++		/* See .ppt in PR for these recommended values */
++		if (bus->blocksize == 512) {
++			wm = OVERFLOW_BLKSZ512_WM;
++			mes = OVERFLOW_BLKSZ512_MES;
++		} else {
++			mes = bus->blocksize/4;
++			wm = bus->blocksize/4;
++		}
++
++		watermark = wm;
++		mesbusyctrl = mes;
++	} else {
++		DHD_INFO(("skip fifotune: SdioRev(%d) is lower than minimal requested ver\n",
++			bus->sih->buscorerev));
++		return;
++	}
++
++	/* Update watermark */
++	if (wm > 0) {
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK, wm, &err);
++
++		devctl = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
++		devctl |= SBSDIO_DEVCTL_F2WM_ENAB;
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
++	}
++
++	/* Update MES */
++	if (mes > 0) {
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_MESBUSYCTRL,
++			(mes | SBSDIO_MESBUSYCTRL_ENAB), &err);
++	}
++
++	DHD_INFO(("Apply overflow WAR: 0x%02x 0x%02x 0x%02x\n",
++		bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err),
++		bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK, &err),
++		bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_MESBUSYCTRL, &err)));
++}
++
++static void
++dhd_dongle_setramsize(struct dhd_bus *bus, int mem_size)
++{
++	int32 min_size =  DONGLE_MIN_RAMSIZE;
++	/* Restrict the ramsize to user specified limit */
++	DHD_ERROR(("user: Restrict the dongle ram size to %d, min accepted %d\n",
++		dhd_dongle_ramsize, min_size));
++	if ((dhd_dongle_ramsize > min_size) &&
++		(dhd_dongle_ramsize < (int32)bus->orig_ramsize))
++		bus->ramsize = dhd_dongle_ramsize;
++}
++
++static int
++dhdsdio_set_siaddr_window(dhd_bus_t *bus, uint32 address)
++{
++	int err = 0;
++	bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
++	                 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
++	if (!err)
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
++		                 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
++	if (!err)
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
++		                 (address >> 24) & SBSDIO_SBADDRHIGH_MASK, &err);
++	return err;
++}
++
++
++#ifdef USE_OOB_GPIO1
++static int
++dhdsdio_oobwakeup_init(dhd_bus_t *bus)
++{
++	uint32 val, addr, data;
++
++	bcmsdh_gpioouten(bus->sdh, GPIO_DEV_WAKEUP);
++
++	addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_addr);
++	data = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_data);
++
++	/* Set device for gpio1 wakeup */
++	bcmsdh_reg_write(bus->sdh, addr, 4, 2);
++	val = bcmsdh_reg_read(bus->sdh, data, 4);
++	val |= CC_CHIPCTRL2_GPIO1_WAKEUP;
++	bcmsdh_reg_write(bus->sdh, data, 4, val);
++
++	bus->_oobwakeup = TRUE;
++
++	return 0;
++}
++#endif /* USE_OOB_GPIO1 */
++
++/*
++ * Query if FW is in SR mode
++ */
++static bool
++dhdsdio_sr_cap(dhd_bus_t *bus)
++{
++	bool cap = FALSE;
++	uint32  core_capext, addr, data;
++
++	if (bus->sih->chip == BCM43430_CHIP_ID ||
++		bus->sih->chip == BCM43018_CHIP_ID) {
++		/* check if fw initialized sr engine */
++		addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, sr_control1);
++		if (bcmsdh_reg_read(bus->sdh, addr, 4) != 0)
++			cap = TRUE;
++
++		return cap;
++	}
++	if (bus->sih->chip == BCM4324_CHIP_ID) {
++			addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_addr);
++			data = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_data);
++			bcmsdh_reg_write(bus->sdh, addr, 4, 3);
++			core_capext = bcmsdh_reg_read(bus->sdh, data, 4);
++	} else if ((bus->sih->chip == BCM4330_CHIP_ID) ||
++		(bus->sih->chip == BCM43362_CHIP_ID) ||
++		(BCM4347_CHIP(bus->sih->chip))) {
++			core_capext = FALSE;
++	} else if ((bus->sih->chip == BCM4335_CHIP_ID) ||
++		(bus->sih->chip == BCM4339_CHIP_ID) ||
++		(bus->sih->chip == BCM43349_CHIP_ID) ||
++		BCM4345_CHIP(bus->sih->chip) ||
++		(bus->sih->chip == BCM4354_CHIP_ID) ||
++		(bus->sih->chip == BCM4358_CHIP_ID) ||
++		(bus->sih->chip == BCM43569_CHIP_ID) ||
++		(bus->sih->chip == BCM4371_CHIP_ID) ||
++		(BCM4349_CHIP(bus->sih->chip))		||
++		(bus->sih->chip == BCM4350_CHIP_ID) ||
++		(bus->sih->chip == BCM43012_CHIP_ID) ||
++		(bus->sih->chip == BCM4362_CHIP_ID)) {
++		core_capext = TRUE;
++	} else {
++		core_capext = bcmsdh_reg_read(bus->sdh,
++			si_get_pmu_reg_addr(bus->sih, OFFSETOF(chipcregs_t, core_cap_ext)),
++			4);
++		core_capext = (core_capext & CORE_CAPEXT_SR_SUPPORTED_MASK);
++	}
++	if (!(core_capext))
++		return FALSE;
++
++	if (bus->sih->chip == BCM4324_CHIP_ID) {
++		/* FIX: Should change to query SR control register instead */
++		cap = TRUE;
++	} else if ((bus->sih->chip == BCM4335_CHIP_ID) ||
++		(bus->sih->chip == BCM4339_CHIP_ID) ||
++		(bus->sih->chip == BCM43349_CHIP_ID) ||
++		BCM4345_CHIP(bus->sih->chip) ||
++		(bus->sih->chip == BCM4354_CHIP_ID) ||
++		(bus->sih->chip == BCM4358_CHIP_ID) ||
++		(bus->sih->chip == BCM43569_CHIP_ID) ||
++		(bus->sih->chip == BCM4371_CHIP_ID) ||
++		(bus->sih->chip == BCM4350_CHIP_ID)) {
++		uint32 enabval = 0;
++		addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_addr);
++		data = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_data);
++		bcmsdh_reg_write(bus->sdh, addr, 4, CC_PMUCC3);
++		enabval = bcmsdh_reg_read(bus->sdh, data, 4);
++
++		if ((bus->sih->chip == BCM4350_CHIP_ID) ||
++			BCM4345_CHIP(bus->sih->chip) ||
++			(bus->sih->chip == BCM4354_CHIP_ID) ||
++			(bus->sih->chip == BCM4358_CHIP_ID) ||
++			(bus->sih->chip == BCM43569_CHIP_ID) ||
++			(bus->sih->chip == BCM4371_CHIP_ID))
++			enabval &= CC_CHIPCTRL3_SR_ENG_ENABLE;
++
++		if (enabval)
++			cap = TRUE;
++	} else {
++		data = bcmsdh_reg_read(bus->sdh,
++			si_get_pmu_reg_addr(bus->sih, OFFSETOF(chipcregs_t, retention_ctl)),
++			4);
++		if ((data & (RCTL_MACPHY_DISABLE_MASK | RCTL_LOGIC_DISABLE_MASK)) == 0)
++			cap = TRUE;
++	}
++
++	return cap;
++}
++
++static int
++dhdsdio_srwar_init(dhd_bus_t *bus)
++{
++	bcmsdh_gpio_init(bus->sdh);
++
++#ifdef USE_OOB_GPIO1
++	dhdsdio_oobwakeup_init(bus);
++#endif
++
++
++	return 0;
++}
++
++static int
++dhdsdio_sr_init(dhd_bus_t *bus)
++{
++	uint8 val;
++	int err = 0;
++
++	if ((bus->sih->chip == BCM4334_CHIP_ID) && (bus->sih->chiprev == 2))
++		dhdsdio_srwar_init(bus);
++
++
++	if (bus->sih->chip == BCM43012_CHIP_ID) {
++		val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, NULL);
++		val |= 1 << SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT;
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL,
++			1 << SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT, &err);
++		val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, NULL);
++	} else {
++		val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, NULL);
++		val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL,
++			1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT, &err);
++		val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, NULL);
++	}
++
++#ifdef USE_CMD14
++	/* Add CMD14 Support */
++	dhdsdio_devcap_set(bus,
++		(SDIOD_CCCR_BRCM_CARDCAP_CMD14_SUPPORT | SDIOD_CCCR_BRCM_CARDCAP_CMD14_EXT));
++#endif /* USE_CMD14 */
++
++	if (CHIPID(bus->sih->chip) == BCM43430_CHIP_ID ||
++		CHIPID(bus->sih->chip) == BCM43018_CHIP_ID ||
++		CHIPID(bus->sih->chip) == BCM4339_CHIP_ID ||
++		CHIPID(bus->sih->chip) == BCM43012_CHIP_ID ||
++		CHIPID(bus->sih->chip) == BCM4362_CHIP_ID)
++		dhdsdio_devcap_set(bus, SDIOD_CCCR_BRCM_CARDCAP_CMD_NODEC);
++
++	if (bus->sih->chip == BCM43012_CHIP_ID) {
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
++			SBSDIO_FUNC1_CHIPCLKCSR, SBSDIO_HT_AVAIL_REQ, &err);
++	} else {
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
++			SBSDIO_FUNC1_CHIPCLKCSR, SBSDIO_FORCE_HT, &err);
++	}
++	bus->_slpauto = dhd_slpauto ? TRUE : FALSE;
++
++	bus->_srenab = TRUE;
++
++	return 0;
++}
++
++/*
++ * FIX: Be sure KSO bit is enabled
++ * Currently, it's defaulting to 0 which should be 1.
++ */
++static int
++dhdsdio_clk_kso_init(dhd_bus_t *bus)
++{
++	uint8 val;
++	int err = 0;
++
++	/* set flag */
++	bus->kso = TRUE;
++
++	/*
++	 * Enable KeepSdioOn (KSO) bit for normal operation
++	 * Default is 0 (4334A0) so set it. Fixed in B0.
++	 */
++	val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, NULL);
++	if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
++		val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, val, &err);
++		if (err)
++			DHD_ERROR(("%s: SBSDIO_FUNC1_SLEEPCSR err: 0x%x\n", __FUNCTION__, err));
++	}
++
++	return 0;
++}
++
++#define KSO_DBG(x)
++#define KSO_WAIT_US 50
++#define KSO_WAIT_MS 1
++#define KSO_SLEEP_RETRY_COUNT 20
++#define KSO_WAKE_RETRY_COUNT 100
++#define ERROR_BCME_NODEVICE_MAX 1
++
++#define DEFAULT_MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
++#ifndef CUSTOM_MAX_KSO_ATTEMPTS
++#define CUSTOM_MAX_KSO_ATTEMPTS DEFAULT_MAX_KSO_ATTEMPTS
++#endif
++
++static int
++dhdsdio_clk_kso_enab(dhd_bus_t *bus, bool on)
++{
++	uint8 wr_val = 0, rd_val, cmp_val, bmask;
++	int err = 0;
++	int try_cnt = 0;
++
++	KSO_DBG(("%s> op:%s\n", __FUNCTION__, (on ? "KSO_SET" : "KSO_CLR")));
++
++	wr_val |= (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
++
++	bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err);
++
++
++	/* In case of 43012 chip, the chip could go down immediately after KSO bit is cleared.
++	 * So the further reads of KSO register could fail. Thereby just bailing out immediately
++	 * after clearing KSO bit, to avoid polling of KSO bit.
++	 */
++	if ((!on) && (bus->sih->chip == BCM43012_CHIP_ID)) {
++		return err;
++	}
++
++	if (on) {
++		cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |  SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
++		bmask = cmp_val;
++
++		OSL_SLEEP(3);
++
++	} else {
++		/* Put device to sleep, turn off  KSO  */
++		cmp_val = 0;
++		bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
++	}
++
++	do {
++		rd_val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, &err);
++		if (((rd_val & bmask) == cmp_val) && !err)
++			break;
++
++		KSO_DBG(("%s> KSO wr/rd retry:%d, ERR:%x \n", __FUNCTION__, try_cnt, err));
++
++		if (((try_cnt + 1) % KSO_SLEEP_RETRY_COUNT) == 0) {
++			OSL_SLEEP(KSO_WAIT_MS);
++		} else
++			OSL_DELAY(KSO_WAIT_US);
++
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err);
++	} while (try_cnt++ < CUSTOM_MAX_KSO_ATTEMPTS);
++
++
++	if (try_cnt > 2)
++		KSO_DBG(("%s> op:%s, try_cnt:%d, rd_val:%x, ERR:%x \n",
++			__FUNCTION__, (on ? "KSO_SET" : "KSO_CLR"), try_cnt, rd_val, err));
++
++	if (try_cnt > CUSTOM_MAX_KSO_ATTEMPTS)  {
++		DHD_ERROR(("%s> op:%s, ERROR: try_cnt:%d, rd_val:%x, ERR:%x \n",
++			__FUNCTION__, (on ? "KSO_SET" : "KSO_CLR"), try_cnt, rd_val, err));
++	}
++
++	return err;
++}
++
++static int
++dhdsdio_clk_kso_iovar(dhd_bus_t *bus, bool on)
++{
++	int err = 0;
++
++	if (on == FALSE) {
++
++		BUS_WAKE(bus);
++		dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++		DHD_ERROR(("%s: KSO disable clk: 0x%x\n", __FUNCTION__,
++			bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
++			SBSDIO_FUNC1_CHIPCLKCSR, &err)));
++		dhdsdio_clk_kso_enab(bus, FALSE);
++	} else {
++		DHD_ERROR(("%s: KSO enable\n", __FUNCTION__));
++
++		/* Make sure we have SD bus access */
++		if (bus->clkstate == CLK_NONE) {
++			DHD_ERROR(("%s: Request SD clk\n", __FUNCTION__));
++			dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++		}
++
++		dhdsdio_clk_kso_enab(bus, TRUE);
++
++		DHD_ERROR(("%s: sleepcsr: 0x%x\n", __FUNCTION__,
++			dhdsdio_sleepcsr_get(bus)));
++	}
++
++	bus->kso = on;
++	BCM_REFERENCE(err);
++
++	return 0;
++}
++
++static uint8
++dhdsdio_sleepcsr_get(dhd_bus_t *bus)
++{
++	int err = 0;
++	uint8 val = 0;
++
++	val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, &err);
++	if (err)
++		DHD_TRACE(("Failed to read SLEEPCSR: %d\n", err));
++
++	return val;
++}
++
++uint8
++dhdsdio_devcap_get(dhd_bus_t *bus)
++{
++	return bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_BRCM_CARDCAP, NULL);
++}
++
++static int
++dhdsdio_devcap_set(dhd_bus_t *bus, uint8 cap)
++{
++	int err = 0;
++
++	bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_BRCM_CARDCAP, cap, &err);
++	if (err)
++		DHD_ERROR(("%s: devcap set err: 0x%x\n", __FUNCTION__, err));
++
++	return 0;
++}
++
++static int
++dhdsdio_clk_devsleep_iovar(dhd_bus_t *bus, bool on)
++{
++	int err = 0, retry;
++	uint8 val;
++
++	retry = 0;
++	if (on == TRUE) {
++		/* Enter Sleep */
++
++		/* Be sure we request clk before going to sleep
++		 * so we can wake-up with clk request already set
++		 * else device can go back to sleep immediately
++		 */
++		if (!SLPAUTO_ENAB(bus))
++			dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++		else {
++			val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
++			if ((val & SBSDIO_CSR_MASK) == 0) {
++				DHD_ERROR(("%s: No clock before enter sleep:0x%x\n",
++					__FUNCTION__, val));
++
++				/* Reset clock request */
++				bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
++					SBSDIO_ALP_AVAIL_REQ, &err);
++				DHD_ERROR(("%s: clock before sleep:0x%x\n", __FUNCTION__,
++					bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
++					SBSDIO_FUNC1_CHIPCLKCSR, &err)));
++			}
++		}
++
++		DHD_TRACE(("%s: clk before sleep: 0x%x\n", __FUNCTION__,
++			bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
++			SBSDIO_FUNC1_CHIPCLKCSR, &err)));
++#ifdef USE_CMD14
++		err = bcmsdh_sleep(bus->sdh, TRUE);
++#else
++		if ((SLPAUTO_ENAB(bus)) && (bus->idleclock == DHD_IDLE_STOP)) {
++			if (sd1idle) {
++				/* Change to SD1 mode */
++				dhdsdio_set_sdmode(bus, 1);
++			}
++		}
++
++		err = dhdsdio_clk_kso_enab(bus, FALSE);
++		if (OOB_WAKEUP_ENAB(bus))
++		{
++			err = bcmsdh_gpioout(bus->sdh, GPIO_DEV_WAKEUP, FALSE);  /* GPIO_1 is off */
++		}
++#endif /* USE_CMD14 */
++
++		if ((SLPAUTO_ENAB(bus)) && (bus->idleclock != DHD_IDLE_ACTIVE)) {
++			DHD_TRACE(("%s: Turnoff SD clk\n", __FUNCTION__));
++			/* Now remove the SD clock */
++			err = dhdsdio_sdclk(bus, FALSE);
++		}
++	} else {
++		/* Exit Sleep */
++		/* Make sure we have SD bus access */
++		if (bus->clkstate == CLK_NONE) {
++			DHD_TRACE(("%s: Request SD clk\n", __FUNCTION__));
++			dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++		}
++
++		if ((bus->sih->chip == BCM4334_CHIP_ID) && (bus->sih->chiprev == 2)) {
++			SPINWAIT_SLEEP(sdioh_spinwait_sleep,
++				(bcmsdh_gpioin(bus->sdh, GPIO_DEV_SRSTATE) != TRUE),
++				GPIO_DEV_SRSTATE_TIMEOUT);
++
++			if (bcmsdh_gpioin(bus->sdh, GPIO_DEV_SRSTATE) == FALSE) {
++				DHD_ERROR(("ERROR: GPIO_DEV_SRSTATE still low!\n"));
++			}
++		}
++#ifdef USE_CMD14
++		err = bcmsdh_sleep(bus->sdh, FALSE);
++		if (SLPAUTO_ENAB(bus) && (err != 0)) {
++			OSL_DELAY(10000);
++			DHD_TRACE(("%s: Resync device sleep\n", __FUNCTION__));
++
++			/* Toggle sleep to resync with host and device */
++			err = bcmsdh_sleep(bus->sdh, TRUE);
++			OSL_DELAY(10000);
++			err = bcmsdh_sleep(bus->sdh, FALSE);
++
++			if (err) {
++				OSL_DELAY(10000);
++				DHD_ERROR(("%s: CMD14 exit failed again!\n", __FUNCTION__));
++
++				/* Toggle sleep to resync with host and device */
++				err = bcmsdh_sleep(bus->sdh, TRUE);
++				OSL_DELAY(10000);
++				err = bcmsdh_sleep(bus->sdh, FALSE);
++				if (err) {
++					DHD_ERROR(("%s: CMD14 exit failed twice!\n", __FUNCTION__));
++					DHD_ERROR(("%s: FATAL: Device non-response!\n",
++						__FUNCTION__));
++					err = 0;
++				}
++			}
++		}
++#else
++		if (OOB_WAKEUP_ENAB(bus))
++		{
++			err = bcmsdh_gpioout(bus->sdh, GPIO_DEV_WAKEUP, TRUE);  /* GPIO_1 is on */
++		}
++		do {
++			err = dhdsdio_clk_kso_enab(bus, TRUE);
++			if (err)
++				OSL_SLEEP(10);
++		} while ((err != 0) && (++retry < 3));
++
++		if (err != 0) {
++			DHD_ERROR(("ERROR: kso set failed retry: %d\n", retry));
++#ifndef BT_OVER_SDIO
++			err = 0; /* continue anyway */
++#endif /* BT_OVER_SDIO */
++		}
++
++		if ((SLPAUTO_ENAB(bus)) && (bus->idleclock == DHD_IDLE_STOP)) {
++			dhdsdio_set_sdmode(bus, bus->sd_mode);
++		}
++#endif /* !USE_CMD14 */
++
++		if (err == 0) {
++			uint8 csr;
++
++			/* Wait for device ready during transition to wake-up */
++			SPINWAIT_SLEEP(sdioh_spinwait_sleep,
++				(((csr = dhdsdio_sleepcsr_get(bus)) &
++				SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK) !=
++				(SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK)), (20000));
++
++			DHD_TRACE(("%s: ExitSleep sleepcsr: 0x%x\n", __FUNCTION__, csr));
++
++			if (!(csr & SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK)) {
++				DHD_ERROR(("%s:ERROR: ExitSleep device NOT Ready! 0x%x\n",
++					__FUNCTION__, csr));
++				err = BCME_NODEVICE;
++			}
++
++			SPINWAIT_SLEEP(sdioh_spinwait_sleep,
++				(((csr = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
++				SBSDIO_FUNC1_CHIPCLKCSR, &err)) & SBSDIO_HT_AVAIL) !=
++				(SBSDIO_HT_AVAIL)), (DHD_WAIT_HTAVAIL));
++
++			DHD_TRACE(("%s: SBSDIO_FUNC1_CHIPCLKCSR : 0x%x\n", __FUNCTION__, csr));
++			if (!err && ((csr & SBSDIO_HT_AVAIL) != SBSDIO_HT_AVAIL)) {
++				DHD_ERROR(("%s:ERROR: device NOT Ready! 0x%x\n",
++					__FUNCTION__, csr));
++				err = BCME_NODEVICE;
++			}
++		}
++	}
++
++	/* Update if successful */
++	if (err == 0)
++		bus->kso = on ? FALSE : TRUE;
++	else {
++		DHD_ERROR(("%s: Sleep request failed: kso:%d on:%d err:%d\n",
++			__FUNCTION__, bus->kso, on, err));
++		if (!on && retry > 2)
++			bus->kso = FALSE;
++	}
++
++	return err;
++}
++
++/* Turn backplane clock on or off */
++static int
++dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
++{
++#define HT_AVAIL_ERROR_MAX 10
++	static int ht_avail_error = 0;
++	int err;
++	uint8 clkctl, clkreq, devctl;
++	bcmsdh_info_t *sdh;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	clkctl = 0;
++	sdh = bus->sdh;
++
++
++	if (!KSO_ENAB(bus))
++		return BCME_OK;
++
++	if (SLPAUTO_ENAB(bus)) {
++		bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
++		return BCME_OK;
++	}
++
++	if (on) {
++		/* Request HT Avail */
++		clkreq = bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
++
++
++
++		bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
++		if (err) {
++			ht_avail_error++;
++			if (ht_avail_error < HT_AVAIL_ERROR_MAX) {
++				DHD_ERROR(("%s: HT Avail request error: %d\n", __FUNCTION__, err));
++			}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++			else if (ht_avail_error == HT_AVAIL_ERROR_MAX) {
++				bus->dhd->hang_reason = HANG_REASON_HT_AVAIL_ERROR;
++				dhd_os_send_hang_message(bus->dhd);
++			}
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27) */
++			return BCME_ERROR;
++		} else {
++			ht_avail_error = 0;
++		}
++
++
++		/* Check current status */
++		clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
++		if (err) {
++			DHD_ERROR(("%s: HT Avail read error: %d\n", __FUNCTION__, err));
++			return BCME_ERROR;
++		}
++
++#if !defined(OOB_INTR_ONLY)
++		/* Go to pending and await interrupt if appropriate */
++		if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
++			/* Allow only clock-available interrupt */
++			devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
++			if (err) {
++				DHD_ERROR(("%s: Devctl access error setting CA: %d\n",
++				           __FUNCTION__, err));
++				return BCME_ERROR;
++			}
++
++			devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
++			bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
++			DHD_INFO(("CLKCTL: set PENDING\n"));
++			bus->clkstate = CLK_PENDING;
++			return BCME_OK;
++		} else
++#endif /* !defined (OOB_INTR_ONLY) */
++		{
++			if (bus->clkstate == CLK_PENDING) {
++				/* Cancel CA-only interrupt filter */
++				devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
++				devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
++				bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
++			}
++		}
++
++		/* Otherwise, wait here (polling) for HT Avail */
++		if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
++			SPINWAIT_SLEEP(sdioh_spinwait_sleep,
++				((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
++			                                    SBSDIO_FUNC1_CHIPCLKCSR, &err)),
++			          !SBSDIO_CLKAV(clkctl, bus->alp_only)), PMU_MAX_TRANSITION_DLY);
++		}
++		if (err) {
++			DHD_ERROR(("%s: HT Avail request error: %d\n", __FUNCTION__, err));
++			return BCME_ERROR;
++		}
++		if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
++			DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
++			           __FUNCTION__, PMU_MAX_TRANSITION_DLY, clkctl));
++			return BCME_ERROR;
++		}
++
++		/* Mark clock available */
++		bus->clkstate = CLK_AVAIL;
++		DHD_INFO(("CLKCTL: turned ON\n"));
++
++#if defined(DHD_DEBUG)
++		if (bus->alp_only == TRUE) {
++#if !defined(BCMLXSDMMC)
++			if (!SBSDIO_ALPONLY(clkctl)) {
++				DHD_ERROR(("%s: HT Clock, when ALP Only\n", __FUNCTION__));
++			}
++#endif /* !defined(BCMLXSDMMC) */
++		} else {
++			if (SBSDIO_ALPONLY(clkctl)) {
++				DHD_ERROR(("%s: HT Clock should be on.\n", __FUNCTION__));
++			}
++		}
++#endif /* defined (DHD_DEBUG) */
++
++		bus->activity = TRUE;
++#ifdef DHD_USE_IDLECOUNT
++		bus->idlecount = 0;
++#endif /* DHD_USE_IDLECOUNT */
++	} else {
++		clkreq = 0;
++
++		if (bus->clkstate == CLK_PENDING) {
++			/* Cancel CA-only interrupt filter */
++			devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
++			devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
++			bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
++		}
++
++		bus->clkstate = CLK_SDONLY;
++		if (!SR_ENAB(bus)) {
++			bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
++			DHD_INFO(("CLKCTL: turned OFF\n"));
++			if (err) {
++				DHD_ERROR(("%s: Failed access turning clock off: %d\n",
++				           __FUNCTION__, err));
++				return BCME_ERROR;
++			}
++		}
++	}
++	return BCME_OK;
++}
++
++/* Change SD1/SD4 bus mode */
++static int
++dhdsdio_set_sdmode(dhd_bus_t *bus, int32 sd_mode)
++{
++	int err;
++
++	err = bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
++		&sd_mode, sizeof(sd_mode), TRUE);
++	if (err) {
++		DHD_ERROR(("%s: error changing sd_mode: %d\n",
++			__FUNCTION__, err));
++		return BCME_ERROR;
++	}
++	return BCME_OK;
++}
++
++/* Change idle/active SD state */
++static int
++dhdsdio_sdclk(dhd_bus_t *bus, bool on)
++{
++	int err;
++	int32 iovalue;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (on) {
++		if (bus->idleclock == DHD_IDLE_STOP) {
++			/* Turn on clock and restore mode */
++			iovalue = 1;
++			err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
++			                      &iovalue, sizeof(iovalue), TRUE);
++			if (err) {
++				DHD_ERROR(("%s: error enabling sd_clock: %d\n",
++				           __FUNCTION__, err));
++				return BCME_ERROR;
++			}
++
++		} else if (bus->idleclock != DHD_IDLE_ACTIVE) {
++			/* Restore clock speed */
++			iovalue = bus->sd_divisor;
++			err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
++			                      &iovalue, sizeof(iovalue), TRUE);
++			if (err) {
++				DHD_ERROR(("%s: error restoring sd_divisor: %d\n",
++				           __FUNCTION__, err));
++				return BCME_ERROR;
++			}
++		}
++		bus->clkstate = CLK_SDONLY;
++	} else {
++		/* Stop or slow the SD clock itself */
++		if ((bus->sd_divisor == -1) || (bus->sd_mode == -1)) {
++			DHD_TRACE(("%s: can't idle clock, divisor %d mode %d\n",
++			           __FUNCTION__, bus->sd_divisor, bus->sd_mode));
++			return BCME_ERROR;
++		}
++		if (bus->idleclock == DHD_IDLE_STOP) {
++			iovalue = 0;
++			err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
++			                      &iovalue, sizeof(iovalue), TRUE);
++			if (err) {
++				DHD_ERROR(("%s: error disabling sd_clock: %d\n",
++				           __FUNCTION__, err));
++				return BCME_ERROR;
++			}
++		} else if (bus->idleclock != DHD_IDLE_ACTIVE) {
++			/* Set divisor to idle value */
++			iovalue = bus->idleclock;
++			err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
++			                      &iovalue, sizeof(iovalue), TRUE);
++			if (err) {
++				DHD_ERROR(("%s: error changing sd_divisor: %d\n",
++				           __FUNCTION__, err));
++				return BCME_ERROR;
++			}
++		}
++		bus->clkstate = CLK_NONE;
++	}
++
++	return BCME_OK;
++}
++
++/* Transition SD and backplane clock readiness */
++static int
++dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
++{
++	int ret = BCME_OK;
++#ifdef DHD_DEBUG
++	uint oldstate = bus->clkstate;
++#endif /* DHD_DEBUG */
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	/* Early exit if we're already there */
++	if (bus->clkstate == target) {
++		if (target == CLK_AVAIL) {
++			dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
++			bus->activity = TRUE;
++#ifdef DHD_USE_IDLECOUNT
++			bus->idlecount = 0;
++#endif /* DHD_USE_IDLECOUNT */
++		}
++		return ret;
++	}
++
++	switch (target) {
++	case CLK_AVAIL:
++		/* Make sure SD clock is available */
++		if (bus->clkstate == CLK_NONE)
++			dhdsdio_sdclk(bus, TRUE);
++		/* Now request HT Avail on the backplane */
++		ret = dhdsdio_htclk(bus, TRUE, pendok);
++		if (ret == BCME_OK) {
++			dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
++		bus->activity = TRUE;
++#ifdef DHD_USE_IDLECOUNT
++			bus->idlecount = 0;
++#endif /* DHD_USE_IDLECOUNT */
++		}
++		break;
++
++	case CLK_SDONLY:
++
++#ifdef BT_OVER_SDIO
++		/*
++		 * If the request is to switch off Back plane clock,
++		 * confirm that BT is inactive before doing so.
++		 * If this call had come from Non Watchdog context any way
++		 * the Watchdog would switch off the clock again when
++		 * nothing is to be done & Bt has finished using the bus.
++		 */
++		if (bus->bt_use_count != 0) {
++			DHD_INFO(("%s(): Req CLK_SDONLY, BT is active %d not switching off \r\n",
++				__FUNCTION__, bus->bt_use_count));
++			ret = BCME_OK;
++			dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
++			break;
++		}
++
++		DHD_INFO(("%s(): Request CLK_NONE BT is NOT active switching off \r\n",
++			__FUNCTION__));
++#endif /* BT_OVER_SDIO */
++
++		/* Remove HT request, or bring up SD clock */
++		if (bus->clkstate == CLK_NONE)
++			ret = dhdsdio_sdclk(bus, TRUE);
++		else if (bus->clkstate == CLK_AVAIL)
++			ret = dhdsdio_htclk(bus, FALSE, FALSE);
++		else
++			DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
++			           bus->clkstate, target));
++		if (ret == BCME_OK) {
++			dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
++		}
++		break;
++
++	case CLK_NONE:
++
++#ifdef BT_OVER_SDIO
++		/*
++		 * If the request is to switch off Back plane clock,
++		 * confirm that BT is inactive before doing so.
++		 * If this call had come from Non Watchdog context any way
++		 * the Watchdog would switch off the clock again when
++		 * nothing is to be done & Bt has finished using the bus.
++		 */
++		if (bus->bt_use_count != 0) {
++			DHD_INFO(("%s(): Request CLK_NONE BT is active %d not switching off \r\n",
++				__FUNCTION__, bus->bt_use_count));
++			ret = BCME_OK;
++			break;
++		}
++
++		DHD_INFO(("%s(): Request CLK_NONE BT is NOT active switching off \r\n",
++			__FUNCTION__));
++#endif /* BT_OVER_SDIO */
++
++		/* Make sure to remove HT request */
++		if (bus->clkstate == CLK_AVAIL)
++			ret = dhdsdio_htclk(bus, FALSE, FALSE);
++		/* Now remove the SD clock */
++		ret = dhdsdio_sdclk(bus, FALSE);
++#ifdef DHD_DEBUG
++		if (dhd_console_ms == 0)
++#endif /* DHD_DEBUG */
++		if (bus->poll == 0)
++			dhd_os_wd_timer(bus->dhd, 0);
++		break;
++	}
++#ifdef DHD_DEBUG
++	DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
++#endif /* DHD_DEBUG */
++
++	return ret;
++}
++
++static int
++dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
++{
++	int err = 0;
++	bcmsdh_info_t *sdh = bus->sdh;
++	sdpcmd_regs_t *regs = bus->regs;
++	uint retries = 0;
++
++	DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
++	         (sleep ? "SLEEP" : "WAKE"),
++	          (bus->sleeping ? "SLEEP" : "WAKE")));
++
++	if (bus->dhd->hang_was_sent)
++		return BCME_ERROR;
++
++	/* Done if we're already in the requested state */
++	if (sleep == bus->sleeping)
++		return BCME_OK;
++
++	/* Going to sleep: set the alarm and turn off the lights... */
++	if (sleep) {
++		/* Don't sleep if something is pending */
++#ifdef DHD_USE_IDLECOUNT
++		if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq) || bus->readframes ||
++			bus->ctrl_frame_stat)
++#else
++		if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
++#endif /* DHD_USE_IDLECOUNT */
++			return BCME_BUSY;
++
++#ifdef BT_OVER_SDIO
++		/*
++		 * The following is the assumption based on which the hook is placed.
++		 * From WLAN driver, either from the active contexts OR from the Watchdog contexts
++		 * we will be attempting to Go to Sleep. AT that moment if we see that BT is still
++		 * actively using the bus, we will return BCME_BUSY from here, but the bus->sleeping
++		 * state would not have changed. So the caller can then schedule the Watchdog again
++		 * which will come and attempt to sleep at a later point.
++		 *
++		 * In case if BT is the only one and is the last user, we don't switch off the clock
++		 * immediately, we allow the WLAN to decide when to sleep i.e from the watchdog.
++		 * Now if the watchdog becomes active and attempts to switch off the clock and if
++		 * another WLAN context is active they are any way serialized with sdlock.
++		 */
++		if (bus->bt_use_count != 0) {
++			DHD_INFO(("%s(): Cannot sleep BT is active \r\n", __FUNCTION__));
++			return BCME_BUSY;
++		}
++#endif /* !BT_OVER_SDIO */
++
++
++		if (!SLPAUTO_ENAB(bus)) {
++			/* Disable SDIO interrupts (no longer interested) */
++			bcmsdh_intr_disable(bus->sdh);
++
++			/* Make sure the controller has the bus up */
++			dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++			/* Tell device to start using OOB wakeup */
++			W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
++			if (retries > retry_limit)
++				DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
++
++			/* Turn off our contribution to the HT clock request */
++			dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++
++			bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
++				SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
++
++			/* Isolate the bus */
++			bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
++					SBSDIO_DEVCTL_PADS_ISO, NULL);
++		} else {
++			/* Leave interrupts enabled since device can exit sleep and
++			 * interrupt host
++			 */
++			err = dhdsdio_clk_devsleep_iovar(bus, TRUE /* sleep */);
++		}
++
++		/* Change state */
++		bus->sleeping = TRUE;
++#if defined(SUPPORT_P2P_GO_PS)
++		wake_up(&bus->bus_sleep);
++#endif /* LINUX && SUPPORT_P2P_GO_PS */
++	} else {
++		/* Waking up: bus power up is ok, set local state */
++
++		if (!SLPAUTO_ENAB(bus)) {
++			bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, &err);
++
++			/* Force pad isolation off if possible (in case power never toggled) */
++			bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0, NULL);
++
++
++			/* Make sure the controller has the bus up */
++			dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++			/* Send misc interrupt to indicate OOB not needed */
++			W_SDREG(0, &regs->tosbmailboxdata, retries);
++			if (retries <= retry_limit)
++				W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
++
++			if (retries > retry_limit)
++				DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
++
++			/* Make sure we have SD bus access */
++			dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++
++			/* Enable interrupts again */
++			if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
++				bus->intdis = FALSE;
++				bcmsdh_intr_enable(bus->sdh);
++			}
++		} else {
++			err = dhdsdio_clk_devsleep_iovar(bus, FALSE /* wake */);
++#ifdef BT_OVER_SDIO
++			if (err < 0) {
++				struct net_device *net = NULL;
++				dhd_pub_t *dhd = bus->dhd;
++				net = dhd_idx2net(dhd, 0);
++				if (net != NULL) {
++					DHD_ERROR(("<<<<<< WIFI HANG by KSO Enabled failure\n"));
++					dhd_os_sdunlock(dhd);
++					net_os_send_hang_message(net);
++					dhd_os_sdlock(dhd);
++				} else {
++					DHD_ERROR(("<<<<< WIFI HANG Fail because net is NULL\n"));
++				}
++			}
++#endif /* BT_OVER_SDIO */
++		}
++
++		if (err == 0) {
++			/* Change state */
++			bus->sleeping = FALSE;
++		}
++	}
++
++	return err;
++}
++
++#ifdef BT_OVER_SDIO
++/*
++ * Call this function to Get the Clock running.
++ * Assumes that the caller holds the sdlock.
++ * bus - Pointer to the dhd_bus handle
++ * can_wait - TRUE if the caller can wait until the clock becomes ready
++ *            FALSE if the caller cannot wait
++ */
++int __dhdsdio_clk_enable(struct dhd_bus *bus, bus_owner_t owner, int can_wait)
++{
++	int ret = BCME_ERROR;
++
++	BCM_REFERENCE(owner);
++
++	bus->bt_use_count++;
++
++	/*
++	 * We can call BUS_WAKE, clkctl multiple times, both of the items
++	 * have states and if its already ON, no new configuration is done
++	 */
++
++	/* Wake up the Dongle FW from SR */
++	BUS_WAKE(bus);
++
++	/*
++	 * Make sure back plane ht clk is on
++	 * CLK_AVAIL - Turn On both SD & HT clock
++	 */
++	ret = dhdsdio_clkctl(bus, CLK_AVAIL, can_wait);
++
++	DHD_INFO(("%s():bt_use_count %d \r\n", __FUNCTION__,
++		bus->bt_use_count));
++	return ret;
++}
++
++/*
++ * Call this function to relinquish the Clock.
++ * Assumes that the caller holds the sdlock.
++ * bus - Pointer to the dhd_bus handle
++ * can_wait - TRUE if the caller can wait until the clock becomes ready
++ *            FALSE if the caller cannot wait
++ */
++int __dhdsdio_clk_disable(struct dhd_bus *bus, bus_owner_t owner, int can_wait)
++{
++	int ret = BCME_ERROR;
++
++	BCM_REFERENCE(owner);
++	BCM_REFERENCE(can_wait);
++
++	if (bus->bt_use_count == 0) {
++		DHD_ERROR(("%s(): Clocks are already turned off \r\n",
++			__FUNCTION__));
++		return ret;
++	}
++
++	bus->bt_use_count--;
++
++	/*
++	 * When the SDIO Bus is shared between BT & WLAN, we turn Off the clock
++	 * once the last user has relinqushed the same. But there are two schemes
++	 * in that too. We consider WLAN as the  bus master (even if its not
++	 * active). Even when the WLAN is OFF the DHD Watchdog is active.
++	 * So this Bus Watchdog is the context whill put the Bus to sleep.
++	 * Refer dhd_bus_watchdog function
++	 */
++
++	ret = BCME_OK;
++	DHD_INFO(("%s():bt_use_count %d \r\n", __FUNCTION__,
++		bus->bt_use_count));
++	return ret;
++}
++
++void dhdsdio_reset_bt_use_count(struct dhd_bus *bus)
++{
++	/* reset bt use count */
++	bus->bt_use_count = 0;
++}
++#endif /* BT_OVER_SDIO */
++
++#ifdef USE_DYNAMIC_F2_BLKSIZE
++int dhdsdio_func_blocksize(dhd_pub_t *dhd, int function_num, int block_size)
++{
++	int func_blk_size = function_num;
++	int bcmerr = 0;
++	int result;
++
++	bcmerr = dhd_bus_iovar_op(dhd, "sd_blocksize", &func_blk_size,
++		sizeof(int), &result, sizeof(int), IOV_GET);
++
++	if (bcmerr != BCME_OK) {
++		DHD_ERROR(("%s: Get F%d Block size error\n", __FUNCTION__, function_num));
++		return BCME_ERROR;
++	}
++
++	if (result != block_size) {
++		DHD_TRACE_HW4(("%s: F%d Block size set from %d to %d\n",
++			__FUNCTION__, function_num, result, block_size));
++		func_blk_size = function_num << 16 | block_size;
++		bcmerr = dhd_bus_iovar_op(dhd, "sd_blocksize", NULL,
++			0, &func_blk_size, sizeof(int32), IOV_SET);
++		if (bcmerr != BCME_OK) {
++			DHD_ERROR(("%s: Set F2 Block size error\n", __FUNCTION__));
++			return BCME_ERROR;
++		}
++	}
++
++	return BCME_OK;
++}
++#endif /* USE_DYNAMIC_F2_BLKSIZE */
++
++#if defined(OOB_INTR_ONLY) || defined(FORCE_WOWLAN)
++void
++dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
++{
++#if defined(HW_OOB) || defined(FORCE_WOWLAN)
++	bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
++#else
++	sdpcmd_regs_t *regs = bus->regs;
++	uint retries = 0;
++
++	dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++	if (enable == TRUE) {
++
++		/* Tell device to start using OOB wakeup */
++		W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
++		if (retries > retry_limit)
++			DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
++
++	} else {
++		/* Send misc interrupt to indicate OOB not needed */
++		W_SDREG(0, &regs->tosbmailboxdata, retries);
++		if (retries <= retry_limit)
++			W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
++	}
++
++	/* Turn off our contribution to the HT clock request */
++	dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++#endif /* !defined(HW_OOB) */
++}
++#endif 
++
++int
++dhd_bus_txdata(struct dhd_bus *bus, void *pkt)
++{
++	int ret = BCME_ERROR;
++	osl_t *osh;
++	uint datalen, prec;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	osh = bus->dhd->osh;
++	datalen = PKTLEN(osh, pkt);
++
++#ifdef SDTEST
++	/* Push the test header if doing loopback */
++	if (bus->ext_loop) {
++		uint8* data;
++		PKTPUSH(osh, pkt, SDPCM_TEST_HDRLEN);
++		data = PKTDATA(osh, pkt);
++		*data++ = SDPCM_TEST_ECHOREQ;
++		*data++ = (uint8)bus->loopid++;
++		*data++ = (datalen >> 0);
++		*data++ = (datalen >> 8);
++		datalen += SDPCM_TEST_HDRLEN;
++	}
++#else /* SDTEST */
++	BCM_REFERENCE(datalen);
++#endif /* SDTEST */
++
++	prec = PRIO2PREC((PKTPRIO(pkt) & PRIOMASK));
++
++	/* move from dhdsdio_sendfromq(), try to orphan skb early */
++	if (bus->dhd->conf->orphan_move == 1)
++		PKTORPHAN(pkt, bus->dhd->conf->tsq);
++
++	/* Check for existing queue, current flow-control, pending event, or pending clock */
++	if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq) || bus->dpc_sched ||
++	    (!DATAOK(bus)) || (bus->flowcontrol & NBITVAL(prec)) ||
++	    (bus->clkstate != CLK_AVAIL)) {
++		bool deq_ret;
++		int pkq_len = 0;
++
++		DHD_TRACE(("%s: deferring pktq len %d\n", __FUNCTION__, pktq_len(&bus->txq)));
++		bus->fcqueued++;
++
++		/* Priority based enq */
++		dhd_os_sdlock_txq(bus->dhd);
++		deq_ret = dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec);
++		dhd_os_sdunlock_txq(bus->dhd);
++
++		if (!deq_ret) {
++#ifdef PROP_TXSTATUS
++			if (DHD_PKTTAG_WLFCPKT(PKTTAG(pkt)) == 0)
++#endif /* PROP_TXSTATUS */
++			{
++#ifdef DHDTCPACK_SUPPRESS
++				if (dhd_tcpack_check_xmit(bus->dhd, pkt) == BCME_ERROR) {
++					DHD_ERROR(("%s %d: tcpack_suppress ERROR!!! Stop using\n",
++						__FUNCTION__, __LINE__));
++					dhd_tcpack_suppress_set(bus->dhd, TCPACK_SUP_OFF);
++				}
++#endif /* DHDTCPACK_SUPPRESS */
++				dhd_txcomplete(bus->dhd, pkt, FALSE);
++				PKTFREE(osh, pkt, TRUE);
++			}
++			ret = BCME_NORESOURCE;
++		} else
++			ret = BCME_OK;
++
++		if (dhd_doflow) {
++			dhd_os_sdlock_txq(bus->dhd);
++			pkq_len = pktq_len(&bus->txq);
++			dhd_os_sdunlock_txq(bus->dhd);
++		}
++		if (dhd_doflow && pkq_len >= FCHI) {
++			bool wlfc_enabled = FALSE;
++#ifdef PROP_TXSTATUS
++			wlfc_enabled = (dhd_wlfc_flowcontrol(bus->dhd, ON, FALSE) !=
++				WLFC_UNSUPPORTED);
++#endif
++			if (!wlfc_enabled && dhd_doflow) {
++				dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, ON);
++			}
++		}
++
++#ifdef DHD_DEBUG
++		dhd_os_sdlock_txq(bus->dhd);
++		if (pktq_plen(&bus->txq, prec) > qcount[prec])
++			qcount[prec] = pktq_plen(&bus->txq, prec);
++		dhd_os_sdunlock_txq(bus->dhd);
++#endif
++
++		/* Schedule DPC if needed to send queued packet(s) */
++		if (dhd_deferred_tx && !bus->dpc_sched) {
++			if (bus->dhd->conf->deferred_tx_len) {
++				if(dhd_os_wd_timer_enabled(bus->dhd) == FALSE) {
++					bus->dpc_sched = TRUE;
++					dhd_sched_dpc(bus->dhd);
++				}
++				if(pktq_len(&bus->txq) >= bus->dhd->conf->deferred_tx_len &&
++						dhd_os_wd_timer_enabled(bus->dhd) == FALSE) {
++					bus->dpc_sched = TRUE;
++					dhd_sched_dpc(bus->dhd);
++				}
++			} else {
++				bus->dpc_sched = TRUE;
++				dhd_sched_dpc(bus->dhd);
++			}
++		}
++	} else {
++		int chan = SDPCM_DATA_CHANNEL;
++
++#ifdef SDTEST
++		chan = (bus->ext_loop ? SDPCM_TEST_CHANNEL : SDPCM_DATA_CHANNEL);
++#endif
++		/* Lock: we're about to use shared data/code (and SDIO) */
++		dhd_os_sdlock(bus->dhd);
++
++		/* Otherwise, send it now */
++		BUS_WAKE(bus);
++		/* Make sure back plane ht clk is on, no pending allowed */
++		dhdsdio_clkctl(bus, CLK_AVAIL, TRUE);
++
++		ret = dhdsdio_txpkt(bus, chan, &pkt, 1, TRUE);
++
++		if (ret != BCME_OK)
++			bus->dhd->tx_errors++;
++		else
++			bus->dhd->dstats.tx_bytes += datalen;
++
++		if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched &&
++				NO_OTHER_ACTIVE_BUS_USER(bus)) {
++			bus->activity = FALSE;
++			dhdsdio_bussleep(bus, TRUE);
++			dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++		}
++
++		dhd_os_sdunlock(bus->dhd);
++	}
++
++	return ret;
++}
++
++/* align packet data pointer and packet length to n-byte boundary, process packet headers,
++ * a new packet may be allocated if there is not enough head and/or tail from for padding.
++ * the caller is responsible for updating the glom size in the head packet (when glom is
++ * used)
++ *
++ * pad_pkt_len: returns the length of extra padding needed from the padding packet, this parameter
++ * is taken in tx glom mode only
++ *
++ * new_pkt: out, pointer of the new packet allocated due to insufficient head room for alignment
++ * padding, NULL if not needed, the caller is responsible for freeing the new packet
++ *
++ * return: positive value - length of the packet, including head and tail padding
++ *		   negative value - errors
++ */
++static int dhdsdio_txpkt_preprocess(dhd_bus_t *bus, void *pkt, int chan, int txseq,
++	int prev_chain_total_len, bool last_chained_pkt,
++	int *pad_pkt_len, void **new_pkt
++#if defined(BCMSDIOH_TXGLOM_EXT)
++	, int first_frame
++#endif
++)
++{
++	osl_t *osh;
++	uint8 *frame;
++	int pkt_len;
++	int modulo;
++	int head_padding;
++	int tail_padding = 0;
++	uint32 swheader;
++	uint32 swhdr_offset;
++	bool alloc_new_pkt = FALSE;
++	uint8 sdpcm_hdrlen = bus->txglom_enable ? SDPCM_HDRLEN_TXGLOM : SDPCM_HDRLEN;
++#ifdef PKT_STATICS
++	uint16 len;
++#endif
++
++	*new_pkt = NULL;
++	osh = bus->dhd->osh;
++
++#ifdef DHDTCPACK_SUPPRESS
++	if (dhd_tcpack_check_xmit(bus->dhd, pkt) == BCME_ERROR) {
++		DHD_ERROR(("%s %d: tcpack_suppress ERROR!!! Stop using it\n",
++			__FUNCTION__, __LINE__));
++		dhd_tcpack_suppress_set(bus->dhd, TCPACK_SUP_OFF);
++	}
++#endif /* DHDTCPACK_SUPPRESS */
++
++	/* Add space for the SDPCM hardware/software headers */
++	PKTPUSH(osh, pkt, sdpcm_hdrlen);
++	ASSERT(ISALIGNED((uintptr)PKTDATA(osh, pkt), 2));
++
++	frame = (uint8*)PKTDATA(osh, pkt);
++	pkt_len = (uint16)PKTLEN(osh, pkt);
++
++#ifdef WLMEDIA_HTSF
++	frame = (uint8*)PKTDATA(osh, pkt);
++	if (PKTLEN(osh, pkt) >= 100) {
++		htsf_ts = (htsfts_t*) (frame + HTSF_HOSTOFFSET + 12);
++		if (htsf_ts->magic == HTSFMAGIC) {
++			htsf_ts->c20 = get_cycles();
++			htsf_ts->t20 = dhd_get_htsf(bus->dhd->info, 0);
++		}
++	}
++#endif /* WLMEDIA_HTSF */
++#ifdef PKT_STATICS
++	len = (uint16)PKTLEN(osh, pkt);
++	switch(chan) {
++		case SDPCM_CONTROL_CHANNEL:
++			tx_statics.ctrl_count++;
++			tx_statics.ctrl_size += len;
++			break;
++		case SDPCM_DATA_CHANNEL:
++			tx_statics.data_count++;
++			tx_statics.data_size += len;
++			break;
++		case SDPCM_GLOM_CHANNEL:
++			tx_statics.glom_count++;
++			tx_statics.glom_size += len;
++			break;
++		case SDPCM_EVENT_CHANNEL:
++			tx_statics.event_count++;
++			tx_statics.event_size += len;
++			break;
++		case SDPCM_TEST_CHANNEL:
++			tx_statics.test_count++;
++			tx_statics.test_size += len;
++			break;
++
++		default:
++			break;
++	}
++#endif /* PKT_STATICS */
++#ifdef DHD_DEBUG
++	if (PKTPRIO(pkt) < ARRAYSIZE(tx_packets))
++		tx_packets[PKTPRIO(pkt)]++;
++#endif /* DHD_DEBUG */
++
++	/* align the data pointer, allocate a new packet if there is not enough space (new
++	 * packet data pointer will be aligned thus no padding will be needed)
++	 */
++	head_padding = (uintptr)frame % DHD_SDALIGN;
++	if (PKTHEADROOM(osh, pkt) < head_padding) {
++		head_padding = 0;
++		alloc_new_pkt = TRUE;
++	} else {
++		uint cur_chain_total_len;
++		int chain_tail_padding = 0;
++
++		/* All packets need to be aligned by DHD_SDALIGN */
++		modulo = (pkt_len + head_padding) % DHD_SDALIGN;
++		tail_padding = modulo > 0 ? (DHD_SDALIGN - modulo) : 0;
++
++		/* Total pkt chain length needs to be aligned by block size,
++		 * unless it is a single pkt chain with total length less than one block size,
++		 * which we prefer sending by byte mode.
++		 *
++		 * Do the chain alignment here if
++		 * 1. This is the last pkt of the chain of multiple pkts or a single pkt.
++		 * 2-1. This chain is of multiple pkts, or
++		 * 2-2. This is a single pkt whose size is longer than one block size.
++		 */
++		cur_chain_total_len = prev_chain_total_len +
++			(head_padding + pkt_len + tail_padding);
++		if (last_chained_pkt && bus->blocksize != 0 &&
++			(cur_chain_total_len > (int)bus->blocksize || prev_chain_total_len > 0)) {
++			modulo = cur_chain_total_len % bus->blocksize;
++			chain_tail_padding = modulo > 0 ? (bus->blocksize - modulo) : 0;
++		}
++
++#ifdef DHDENABLE_TAILPAD
++		if (PKTTAILROOM(osh, pkt) < tail_padding) {
++			/* We don't have tail room to align by DHD_SDALIGN */
++			alloc_new_pkt = TRUE;
++			bus->tx_tailpad_pktget++;
++		} else if (PKTTAILROOM(osh, pkt) < tail_padding + chain_tail_padding) {
++			/* We have tail room for tail_padding of this pkt itself, but not for
++			 * total pkt chain alignment by block size.
++			 * Use the padding packet to avoid memory copy if applicable,
++			 * otherwise, just allocate a new pkt.
++			 */
++			if (bus->pad_pkt) {
++				*pad_pkt_len = chain_tail_padding;
++				bus->tx_tailpad_chain++;
++			} else {
++				alloc_new_pkt = TRUE;
++				bus->tx_tailpad_pktget++;
++			}
++		} else
++		/* This last pkt's tailroom is sufficient to hold both tail_padding
++		 * of the pkt itself and chain_tail_padding of total pkt chain
++		 */
++#endif /* DHDENABLE_TAILPAD */
++		tail_padding += chain_tail_padding;
++	}
++
++	DHD_INFO(("%s sdhdr len + orig_pkt_len %d h_pad %d t_pad %d pad_pkt_len %d\n",
++		__FUNCTION__, pkt_len, head_padding, tail_padding, *pad_pkt_len));
++
++	if (alloc_new_pkt) {
++		void *tmp_pkt;
++		int newpkt_size;
++		int cur_total_len;
++
++		ASSERT(*pad_pkt_len == 0);
++
++		DHD_INFO(("%s allocating new packet for padding\n", __FUNCTION__));
++
++		/* head pointer is aligned now, no padding needed */
++		head_padding = 0;
++
++		/* update the tail padding as it depends on the head padding, since a new packet is
++		 * allocated, the head padding is non longer needed and packet length is chagned
++		 */
++
++		cur_total_len = prev_chain_total_len + pkt_len;
++		if (last_chained_pkt && bus->blocksize != 0 &&
++			(cur_total_len > (int)bus->blocksize || prev_chain_total_len > 0)) {
++			modulo = cur_total_len % bus->blocksize;
++			tail_padding = modulo > 0 ? (bus->blocksize - modulo) : 0;
++		} else {
++			modulo = pkt_len % DHD_SDALIGN;
++			tail_padding = modulo > 0 ? (DHD_SDALIGN - modulo) : 0;
++		}
++
++		newpkt_size = PKTLEN(osh, pkt) + bus->blocksize + DHD_SDALIGN;
++		bus->dhd->tx_realloc++;
++		tmp_pkt = PKTGET(osh, newpkt_size, TRUE);
++		if (tmp_pkt == NULL) {
++			DHD_ERROR(("failed to alloc new %d byte packet\n", newpkt_size));
++			return BCME_NOMEM;
++		}
++		PKTALIGN(osh, tmp_pkt, PKTLEN(osh, pkt), DHD_SDALIGN);
++		bcopy(PKTDATA(osh, pkt), PKTDATA(osh, tmp_pkt), PKTLEN(osh, pkt));
++		*new_pkt = tmp_pkt;
++		pkt = tmp_pkt;
++	}
++
++	if (head_padding)
++		PKTPUSH(osh, pkt, head_padding);
++
++	frame = (uint8*)PKTDATA(osh, pkt);
++	bzero(frame, head_padding + sdpcm_hdrlen);
++	pkt_len = (uint16)PKTLEN(osh, pkt);
++
++	/* the header has the followming format
++	 * 4-byte HW frame tag: length, ~length (for glom this is the total length)
++	 *
++	 * 8-byte HW extesion flags (glom mode only) as the following:
++	 *			2-byte packet length, excluding HW tag and padding
++	 *			2-byte frame channel and frame flags (e.g. next frame following)
++	 *			2-byte header length
++	 *			2-byte tail padding size
++	 *
++	 * 8-byte SW frame tags as the following
++	 *			4-byte flags: host tx seq, channel, data offset
++	 *			4-byte flags: TBD
++	 */
++
++	swhdr_offset = SDPCM_FRAMETAG_LEN;
++
++	/* hardware frame tag:
++	 *
++	 * in tx-glom mode, dongle only checks the hardware frame tag in the first
++	 * packet and sees it as the total lenght of the glom (including tail padding),
++	 * for each packet in the glom, the packet length needs to be updated, (see
++	 * below PKTSETLEN)
++	 *
++	 * in non tx-glom mode, PKTLEN still need to include tail padding as to be
++	 * referred to in sdioh_request_buffer(). The tail length will be excluded in
++	 * dhdsdio_txpkt_postprocess().
++	 */
++#if defined(BCMSDIOH_TXGLOM_EXT)
++	if (bus->dhd->conf->txglom_bucket_size)
++		tail_padding = 0;
++#endif
++	*(uint16*)frame = (uint16)htol16(pkt_len);
++	*(((uint16*)frame) + 1) = (uint16)htol16(~pkt_len);
++	pkt_len += tail_padding;
++
++	/* hardware extesion flags */
++	if (bus->txglom_enable) {
++		uint32 hwheader1;
++		uint32 hwheader2;
++#ifdef BCMSDIOH_TXGLOM_EXT
++		uint32 act_len = pkt_len - tail_padding;
++		uint32 real_pad = 0;
++		if(bus->dhd->conf->txglom_ext && !last_chained_pkt) {
++			tail_padding = 0;
++			if(first_frame == 0) {
++				// first pkt, add pad to bucket size - recv offset
++				pkt_len = bus->dhd->conf->txglom_bucket_size - TXGLOM_RECV_OFFSET;
++			} else {
++				// add pad to bucket size
++				pkt_len = bus->dhd->conf->txglom_bucket_size;
++			}
++			swhdr_offset += SDPCM_HWEXT_LEN;
++			hwheader1 = (act_len - SDPCM_FRAMETAG_LEN) | (last_chained_pkt << 24);
++			hwheader2 = (pkt_len - act_len) << 16;
++			htol32_ua_store(hwheader1, frame + SDPCM_FRAMETAG_LEN);
++			htol32_ua_store(hwheader2, frame + SDPCM_FRAMETAG_LEN + 4);
++			real_pad = pkt_len - act_len;
++
++			if (PKTTAILROOM(osh, pkt) < real_pad) {
++				DHD_INFO(("%s : insufficient tailroom %d for %d real_pad\n", 
++					__func__, (int)PKTTAILROOM(osh, pkt), real_pad));
++				if (PKTPADTAILROOM(osh, pkt, real_pad)) {
++					DHD_ERROR(("CHK1: padding error size %d\n", real_pad));
++				} else
++					frame = (uint8 *)PKTDATA(osh, pkt);
++			}
++		} else 
++#endif
++		{
++			swhdr_offset += SDPCM_HWEXT_LEN;
++			hwheader1 = (pkt_len - SDPCM_FRAMETAG_LEN - tail_padding) |
++				(last_chained_pkt << 24);
++			hwheader2 = (tail_padding) << 16;
++			htol32_ua_store(hwheader1, frame + SDPCM_FRAMETAG_LEN);
++			htol32_ua_store(hwheader2, frame + SDPCM_FRAMETAG_LEN + 4);
++		}
++	}
++	PKTSETLEN((osh), (pkt), (pkt_len));
++
++	/* software frame tags */
++	swheader = ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK)
++		| (txseq % SDPCM_SEQUENCE_WRAP) |
++		(((head_padding + sdpcm_hdrlen) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
++	htol32_ua_store(swheader, frame + swhdr_offset);
++	htol32_ua_store(0, frame + swhdr_offset + sizeof(swheader));
++
++	return pkt_len;
++}
++
++static int dhdsdio_txpkt_postprocess(dhd_bus_t *bus, void *pkt)
++{
++	osl_t *osh;
++	uint8 *frame;
++	int data_offset;
++	int tail_padding;
++	int swhdr_offset = SDPCM_FRAMETAG_LEN + (bus->txglom_enable ? SDPCM_HWEXT_LEN : 0);
++
++	(void)osh;
++	osh = bus->dhd->osh;
++
++	/* restore pkt buffer pointer, but keeps the header pushed by dhd_prot_hdrpush */
++	frame = (uint8*)PKTDATA(osh, pkt);
++
++	DHD_INFO(("%s PKTLEN before postprocess %d",
++		__FUNCTION__, PKTLEN(osh, pkt)));
++
++	/* PKTLEN still includes tail_padding, so exclude it.
++	 * We shall have head_padding + original pkt_len for PKTLEN afterwards.
++	 */
++	if (bus->txglom_enable) {
++		/* txglom pkts have tail_padding length in HW ext header */
++		tail_padding = ltoh32_ua(frame + SDPCM_FRAMETAG_LEN + 4) >> 16;
++		PKTSETLEN(osh, pkt, PKTLEN(osh, pkt) - tail_padding);
++		DHD_INFO((" txglom pkt: tail_padding %d PKTLEN %d\n",
++			tail_padding, PKTLEN(osh, pkt)));
++	} else {
++		/* non-txglom pkts have head_padding + original pkt length in HW frame tag.
++		 * We cannot refer to this field for txglom pkts as the first pkt of the chain will
++		 * have the field for the total length of the chain.
++		 */
++		PKTSETLEN(osh, pkt, *(uint16*)frame);
++		DHD_INFO((" non-txglom pkt: HW frame tag len %d after PKTLEN %d\n",
++			*(uint16*)frame, PKTLEN(osh, pkt)));
++	}
++
++	data_offset = ltoh32_ua(frame + swhdr_offset);
++	data_offset = (data_offset & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT;
++	/* Get rid of sdpcm header + head_padding */
++	PKTPULL(osh, pkt, data_offset);
++
++	DHD_INFO(("%s data_offset %d, PKTLEN %d\n",
++		__FUNCTION__, data_offset, PKTLEN(osh, pkt)));
++
++	return BCME_OK;
++}
++
++static int dhdsdio_txpkt(dhd_bus_t *bus, uint chan, void** pkts, int num_pkt, bool free_pkt)
++{
++	int i;
++	int ret = 0;
++	osl_t *osh;
++	bcmsdh_info_t *sdh;
++	void *pkt = NULL;
++	void *pkt_chain;
++	int total_len = 0;
++	void *head_pkt = NULL;
++	void *prev_pkt = NULL;
++	int pad_pkt_len = 0;
++	int new_pkt_num = 0;
++	void *new_pkts[MAX_TX_PKTCHAIN_CNT];
++	bool wlfc_enabled = FALSE;
++
++	if (bus->dhd->dongle_reset)
++		return BCME_NOTREADY;
++
++	if (num_pkt <= 0)
++		return BCME_BADARG;
++
++	sdh = bus->sdh;
++	osh = bus->dhd->osh;
++	/* init new_pkts[0] to make some compiler happy, not necessary as we check new_pkt_num */
++	new_pkts[0] = NULL;
++
++	for (i = 0; i < num_pkt; i++) {
++		int pkt_len;
++		bool last_pkt;
++		void *new_pkt = NULL;
++
++		pkt = pkts[i];
++		ASSERT(pkt);
++		last_pkt = (i == num_pkt - 1);
++		pkt_len = dhdsdio_txpkt_preprocess(bus, pkt, chan, bus->tx_seq + i,
++			total_len, last_pkt, &pad_pkt_len, &new_pkt
++#if defined(BCMSDIOH_TXGLOM_EXT)
++			, i
++#endif
++		);
++		if (pkt_len <= 0)
++			goto done;
++		if (new_pkt) {
++			pkt = new_pkt;
++			new_pkts[new_pkt_num++] = new_pkt;
++		}
++		total_len += pkt_len;
++
++		PKTSETNEXT(osh, pkt, NULL);
++		/* insert the packet into the list */
++		head_pkt ? PKTSETNEXT(osh, prev_pkt, pkt) : (head_pkt = pkt);
++		prev_pkt = pkt;
++
++	}
++
++	/* Update the HW frame tag (total length) in the first pkt of the glom */
++	if (bus->txglom_enable) {
++		uint8 *frame;
++
++		total_len += pad_pkt_len;
++		frame = (uint8*)PKTDATA(osh, head_pkt);
++		*(uint16*)frame = (uint16)htol16(total_len);
++		*(((uint16*)frame) + 1) = (uint16)htol16(~total_len);
++
++	}
++
++#ifdef DHDENABLE_TAILPAD
++	/* if a padding packet if needed, insert it to the end of the link list */
++	if (pad_pkt_len) {
++		PKTSETLEN(osh, bus->pad_pkt, pad_pkt_len);
++		PKTSETNEXT(osh, pkt, bus->pad_pkt);
++	}
++#endif /* DHDENABLE_TAILPAD */
++
++	/* dhd_bcmsdh_send_buf ignores the buffer pointer if he packet
++	 * parameter is not NULL, for non packet chian we pass NULL pkt pointer
++	 * so it will take the aligned length and buffer pointer.
++	 */
++	pkt_chain = PKTNEXT(osh, head_pkt) ? head_pkt : NULL;
++	ret = dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
++		PKTDATA(osh, head_pkt), total_len, pkt_chain, NULL, NULL, TXRETRIES);
++	if (ret == BCME_OK)
++		bus->tx_seq = (bus->tx_seq + num_pkt) % SDPCM_SEQUENCE_WRAP;
++
++	/* if a padding packet was needed, remove it from the link list as it not a data pkt */
++	if (pad_pkt_len && pkt)
++		PKTSETNEXT(osh, pkt, NULL);
++
++done:
++	pkt = head_pkt;
++	while (pkt) {
++		void *pkt_next = PKTNEXT(osh, pkt);
++		PKTSETNEXT(osh, pkt, NULL);
++		dhdsdio_txpkt_postprocess(bus, pkt);
++		pkt = pkt_next;
++	}
++
++	/* new packets might be allocated due to insufficient room for padding, but we
++	 * still have to indicate the original packets to upper layer
++	 */
++	for (i = 0; i < num_pkt; i++) {
++		pkt = pkts[i];
++		wlfc_enabled = FALSE;
++#ifdef PROP_TXSTATUS
++		if (DHD_PKTTAG_WLFCPKT(PKTTAG(pkt))) {
++			wlfc_enabled = (dhd_wlfc_txcomplete(bus->dhd, pkt, ret == 0) !=
++				WLFC_UNSUPPORTED);
++		}
++#endif /* PROP_TXSTATUS */
++		if (!wlfc_enabled) {
++			PKTSETNEXT(osh, pkt, NULL);
++			dhd_txcomplete(bus->dhd, pkt, ret != 0);
++			if (free_pkt)
++				PKTFREE(osh, pkt, TRUE);
++		}
++	}
++
++	for (i = 0; i < new_pkt_num; i++)
++		PKTFREE(osh, new_pkts[i], TRUE);
++
++	return ret;
++}
++
++static uint
++dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
++{
++	uint cnt = 0;
++	uint8 tx_prec_map;
++	uint16 txpktqlen = 0;
++	uint32 intstatus = 0;
++	uint retries = 0;
++	osl_t *osh;
++	uint datalen = 0;
++	dhd_pub_t *dhd = bus->dhd;
++	sdpcmd_regs_t *regs = bus->regs;
++#ifdef DHD_LOSSLESS_ROAMING
++	uint8 *pktdata;
++	struct ether_header *eh;
++#endif /* DHD_LOSSLESS_ROAMING */
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (!KSO_ENAB(bus)) {
++		DHD_ERROR(("%s: Device asleep\n", __FUNCTION__));
++		return BCME_NODEVICE;
++	}
++
++	osh = dhd->osh;
++	tx_prec_map = ~bus->flowcontrol;
++#ifdef DHD_LOSSLESS_ROAMING
++	tx_prec_map &= dhd->dequeue_prec_map;
++#endif /* DHD_LOSSLESS_ROAMING */
++	for (cnt = 0; (cnt < maxframes) && DATAOK(bus);) {
++		int i;
++		int num_pkt = 1;
++		void *pkts[MAX_TX_PKTCHAIN_CNT];
++		int prec_out;
++
++		dhd_os_sdlock_txq(bus->dhd);
++		if (bus->txglom_enable) {
++			uint32 glomlimit = (uint32)bus->txglomsize;
++#if defined(BCMSDIOH_STD)
++			if (bus->blocksize == 64) {
++				glomlimit = MIN((uint32)bus->txglomsize, BLK_64_MAXTXGLOM);
++			}
++#endif /* BCMSDIOH_STD */
++			num_pkt = MIN((uint32)DATABUFCNT(bus), glomlimit);
++			num_pkt = MIN(num_pkt, ARRAYSIZE(pkts));
++		}
++		num_pkt = MIN(num_pkt, pktq_mlen(&bus->txq, tx_prec_map));
++		for (i = 0; i < num_pkt; i++) {
++			pkts[i] = pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
++			if (!pkts[i]) {
++				DHD_ERROR(("%s: pktq_mlen non-zero when no pkt\n",
++					__FUNCTION__));
++				ASSERT(0);
++				break;
++			}
++#ifdef DHD_LOSSLESS_ROAMING
++			pktdata = (uint8 *)PKTDATA(osh, pkts[i]);
++#ifdef BDC
++			/* Skip BDC header */
++			pktdata += BDC_HEADER_LEN + ((struct bdc_header *)pktdata)->dataOffset;
++#endif
++			eh = (struct ether_header *)pktdata;
++			if (eh->ether_type == hton16(ETHER_TYPE_802_1X)) {
++				uint8 prio = (uint8)PKTPRIO(pkts[i]);
++
++				/* Restore to original priority for 802.1X packet */
++				if (prio == PRIO_8021D_NC) {
++					PKTSETPRIO(pkts[i], dhd->prio_8021x);
++				}
++			}
++#endif /* DHD_LOSSLESS_ROAMING */
++			if (!bus->dhd->conf->orphan_move)
++				PKTORPHAN(pkts[i], bus->dhd->conf->tsq);
++			datalen += PKTLEN(osh, pkts[i]);
++		}
++		dhd_os_sdunlock_txq(bus->dhd);
++
++		if (i == 0)
++			break;
++		if (dhdsdio_txpkt(bus, SDPCM_DATA_CHANNEL, pkts, i, TRUE) != BCME_OK)
++			dhd->tx_errors++;
++		else {
++			dhd->dstats.tx_bytes += datalen;
++			bus->txglomframes++;
++			bus->txglompkts += num_pkt;
++		}
++		cnt += i;
++#ifdef PKT_STATICS
++		if (num_pkt) {
++			tx_statics.glom_cnt[num_pkt-1]++;
++			if (num_pkt > tx_statics.glom_max)
++				tx_statics.glom_max = num_pkt;
++		}
++#endif
++
++		/* In poll mode, need to check for other events */
++		if (!bus->intr && cnt)
++		{
++			/* Check device status, signal pending interrupt */
++			R_SDREG(intstatus, &regs->intstatus, retries);
++			bus->f2txdata++;
++			if (bcmsdh_regfail(bus->sdh))
++				break;
++			if (intstatus & bus->hostintmask)
++				bus->ipend = TRUE;
++		}
++
++	}
++
++	if (dhd_doflow) {
++		dhd_os_sdlock_txq(bus->dhd);
++		txpktqlen = pktq_len(&bus->txq);
++		dhd_os_sdunlock_txq(bus->dhd);
++	}
++
++	/* Do flow-control if needed */
++	if (dhd->up && (dhd->busstate == DHD_BUS_DATA) && (txpktqlen < FCLOW)) {
++		bool wlfc_enabled = FALSE;
++#ifdef PROP_TXSTATUS
++		wlfc_enabled = (dhd_wlfc_flowcontrol(dhd, OFF, TRUE) != WLFC_UNSUPPORTED);
++#endif
++		if (!wlfc_enabled && dhd_doflow && dhd->txoff) {
++			dhd_txflowcontrol(dhd, ALL_INTERFACES, OFF);
++		}
++	}
++
++	return cnt;
++}
++
++static void
++dhdsdio_sendpendctl(dhd_bus_t *bus)
++{
++	bcmsdh_info_t *sdh = bus->sdh;
++	int ret;
++	uint8* frame_seq = bus->ctrl_frame_buf + SDPCM_FRAMETAG_LEN;
++
++	if (bus->txglom_enable)
++		frame_seq += SDPCM_HWEXT_LEN;
++
++	if (*frame_seq != bus->tx_seq) {
++		DHD_INFO(("%s IOCTL frame seq lag detected!"
++			" frm_seq:%d != bus->tx_seq:%d, corrected\n",
++			__FUNCTION__, *frame_seq, bus->tx_seq));
++		*frame_seq = bus->tx_seq;
++	}
++
++	ret = dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
++		(uint8 *)bus->ctrl_frame_buf, (uint32)bus->ctrl_frame_len,
++		NULL, NULL, NULL, 1);
++	if (ret == BCME_OK)
++		bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
++
++	bus->ctrl_frame_stat = FALSE;
++	dhd_wait_event_wakeup(bus->dhd);
++}
++
++int
++dhd_bus_txctl(struct dhd_bus *bus, uchar *msg, uint msglen)
++{
++	static int err_nodevice = 0;
++	uint8 *frame;
++	uint16 len;
++	uint32 swheader;
++	uint8 doff = 0;
++	int ret = -1;
++	uint8 sdpcm_hdrlen = bus->txglom_enable ? SDPCM_HDRLEN_TXGLOM : SDPCM_HDRLEN;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus->dhd->dongle_reset)
++		return -EIO;
++
++	/* Back the pointer to make a room for bus header */
++	frame = msg - sdpcm_hdrlen;
++	len = (msglen += sdpcm_hdrlen);
++
++	/* Add alignment padding (optional for ctl frames) */
++	if (dhd_alignctl) {
++		if ((doff = ((uintptr)frame % DHD_SDALIGN))) {
++			frame -= doff;
++			len += doff;
++			msglen += doff;
++			bzero(frame, doff + sdpcm_hdrlen);
++		}
++		ASSERT(doff < DHD_SDALIGN);
++	}
++	doff += sdpcm_hdrlen;
++
++	/* Round send length to next SDIO block */
++	if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
++		uint16 pad = bus->blocksize - (len % bus->blocksize);
++		if ((pad <= bus->roundup) && (pad < bus->blocksize))
++			len += pad;
++	} else if (len % DHD_SDALIGN) {
++		len += DHD_SDALIGN - (len % DHD_SDALIGN);
++	}
++
++	/* Satisfy length-alignment requirements */
++	if (forcealign && (len & (ALIGNMENT - 1)))
++		len = ROUNDUP(len, ALIGNMENT);
++
++	ASSERT(ISALIGNED((uintptr)frame, 2));
++
++
++	/* Need to lock here to protect txseq and SDIO tx calls */
++	dhd_os_sdlock(bus->dhd);
++	if (bus->dhd->conf->txctl_tmo_fix > 0 && !TXCTLOK(bus)) {
++		bus->ctrl_wait = TRUE;
++		dhd_os_sdunlock(bus->dhd);
++		wait_event_interruptible_timeout(bus->ctrl_tx_wait, TXCTLOK(bus),
++			msecs_to_jiffies(bus->dhd->conf->txctl_tmo_fix));
++		dhd_os_sdlock(bus->dhd);
++		bus->ctrl_wait = FALSE;
++	}
++
++	BUS_WAKE(bus);
++
++	/* Make sure backplane clock is on */
++	dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++	/* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
++	*(uint16*)frame = htol16((uint16)msglen);
++	*(((uint16*)frame) + 1) = htol16(~msglen);
++
++	if (bus->txglom_enable) {
++		uint32 hwheader1, hwheader2;
++		/* Software tag: channel, sequence number, data offset */
++		swheader = ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK)
++				| bus->tx_seq
++				| ((doff << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
++		htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN + SDPCM_HWEXT_LEN);
++		htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN
++			+ SDPCM_HWEXT_LEN + sizeof(swheader));
++
++		hwheader1 = (msglen - SDPCM_FRAMETAG_LEN) | (1 << 24);
++		hwheader2 = (len - (msglen)) << 16;
++		htol32_ua_store(hwheader1, frame + SDPCM_FRAMETAG_LEN);
++		htol32_ua_store(hwheader2, frame + SDPCM_FRAMETAG_LEN + 4);
++
++		*(uint16*)frame = htol16(len);
++		*(((uint16*)frame) + 1) = htol16(~(len));
++	} else {
++		/* Software tag: channel, sequence number, data offset */
++		swheader = ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK)
++		        | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
++		htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN);
++		htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
++	}
++
++#ifdef DHD_ULP
++	dhd_ulp_set_path(bus->dhd, DHD_ULP_TX_CTRL);
++
++	if (!TXCTLOK(bus) || !dhd_ulp_f2_ready(bus->dhd, bus->sdh))
++#else
++	if (!TXCTLOK(bus))
++#endif
++	{
++		DHD_CTL(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
++			__FUNCTION__, bus->tx_max, bus->tx_seq));
++		bus->ctrl_frame_stat = TRUE;
++		/* Send from dpc */
++		bus->ctrl_frame_buf = frame;
++		bus->ctrl_frame_len = len;
++
++		if (!bus->dpc_sched) {
++			bus->dpc_sched = TRUE;
++			dhd_sched_dpc(bus->dhd);
++		}
++		if (bus->ctrl_frame_stat) {
++			dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
++		}
++
++		if (bus->ctrl_frame_stat == FALSE) {
++			DHD_INFO(("%s: ctrl_frame_stat == FALSE\n", __FUNCTION__));
++			ret = 0;
++		} else {
++			bus->dhd->txcnt_timeout++;
++			if (!bus->dhd->hang_was_sent) {
++#ifdef CUSTOMER_HW4_DEBUG
++				uint32 status, retry = 0;
++				R_SDREG(status, &bus->regs->intstatus, retry);
++				DHD_TRACE_HW4(("%s: txcnt_timeout, INT status=0x%08X\n",
++					__FUNCTION__, status));
++				DHD_TRACE_HW4(("%s : tx_max : %d, tx_seq : %d, clkstate : %d \n",
++					__FUNCTION__, bus->tx_max, bus->tx_seq, bus->clkstate));
++#endif /* CUSTOMER_HW4_DEBUG */
++				DHD_ERROR(("%s: ctrl_frame_stat == TRUE txcnt_timeout=%d\n",
++					__FUNCTION__, bus->dhd->txcnt_timeout));
++#ifdef BCMSDIO_RXLIM_POST
++				DHD_ERROR(("%s: rxlim_en=%d, rxlim enable=%d, rxlim_addr=%d\n",
++					__FUNCTION__,
++					bus->dhd->conf->rxlim_en, bus->rxlim_en, bus->rxlim_addr));
++#endif /* BCMSDIO_RXLIM_POST */
++			}
++#ifdef DHD_FW_COREDUMP
++			/* Collect socram dump */
++			if (bus->dhd->memdump_enabled) {
++				/* collect core dump */
++				bus->dhd->memdump_type = DUMP_TYPE_RESUMED_ON_TIMEOUT_TX;
++				dhd_os_sdunlock(bus->dhd);
++				dhd_bus_mem_dump(bus->dhd);
++				dhd_os_sdlock(bus->dhd);
++			}
++#endif /* DHD_FW_COREDUMP */
++			ret = -1;
++			bus->ctrl_frame_stat = FALSE;
++			goto done;
++		}
++	}
++
++	bus->dhd->txcnt_timeout = 0;
++	bus->ctrl_frame_stat = TRUE;
++
++	if (ret == -1) {
++#ifdef DHD_DEBUG
++		if (DHD_BYTES_ON() && DHD_CTL_ON()) {
++			prhex("Tx Frame", frame, len);
++		} else if (DHD_HDRS_ON()) {
++			prhex("TxHdr", frame, MIN(len, 16));
++		}
++#endif
++#ifdef PKT_STATICS
++		tx_statics.ctrl_count++;
++		tx_statics.ctrl_size += len;
++#endif
++		ret = dhd_bcmsdh_send_buffer(bus, frame, len);
++	}
++	bus->ctrl_frame_stat = FALSE;
++#ifdef DHD_ULP
++	dhd_ulp_enable_cached_sbwad(bus->dhd, bus->sdh);
++#endif /* DHD_ULP */
++
++done:
++	if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched &&
++		NO_OTHER_ACTIVE_BUS_USER(bus)) {
++		bus->activity = FALSE;
++		dhdsdio_bussleep(bus, TRUE);
++		dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++	}
++
++	dhd_os_sdunlock(bus->dhd);
++
++	if (ret)
++		bus->dhd->tx_ctlerrs++;
++	else
++		bus->dhd->tx_ctlpkts++;
++
++	if (bus->dhd->txcnt_timeout >= MAX_CNTL_TX_TIMEOUT) {
++		return -ETIMEDOUT;
++	}
++
++	if (ret == BCME_NODEVICE)
++		err_nodevice++;
++	else
++		err_nodevice = 0;
++
++	return ret ? err_nodevice >= ERROR_BCME_NODEVICE_MAX ? -ETIMEDOUT : -EIO : 0;
++}
++
++int
++dhd_bus_rxctl(struct dhd_bus *bus, uchar *msg, uint msglen)
++{
++	int timeleft;
++	uint rxlen = 0;
++	static uint cnt = 0;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus->dhd->dongle_reset)
++		return -EIO;
++
++	/* Wait until control frame is available */
++	timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen);
++
++	dhd_os_sdlock(bus->dhd);
++	rxlen = bus->rxlen;
++	bcopy(bus->rxctl, msg, MIN(msglen, rxlen));
++	bus->rxlen = 0;
++	dhd_os_sdunlock(bus->dhd);
++
++	if (bus->dhd->conf->ctrl_resched > 0 && !rxlen && timeleft == 0) {
++		cnt++;
++		if (cnt <= bus->dhd->conf->ctrl_resched) {
++			uint32 status, retry = 0;
++			R_SDREG(status, &bus->regs->intstatus, retry);
++			if ((status & I_HMB_HOST_INT) || PKT_AVAILABLE(bus, status)) {
++				DHD_ERROR(("%s: reschedule dhd_dpc, cnt=%d, status=0x%x\n",
++					__FUNCTION__, cnt, status));
++				bus->ipend = TRUE;
++				bus->dpc_sched = TRUE;
++				dhd_sched_dpc(bus->dhd);
++
++				/* Wait until control frame is available */
++				timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen);
++
++				dhd_os_sdlock(bus->dhd);
++				rxlen = bus->rxlen;
++				bcopy(bus->rxctl, msg, MIN(msglen, rxlen));
++				bus->rxlen = 0;
++				dhd_os_sdunlock(bus->dhd);
++			}
++		}
++	} else {
++		cnt = 0;
++	}
++
++	if (rxlen) {
++		DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
++			__FUNCTION__, rxlen, msglen));
++	} else {
++		if (timeleft == 0) {
++#ifdef DHD_DEBUG
++			uint32 status, retry = 0;
++			R_SDREG(status, &bus->regs->intstatus, retry);
++			DHD_ERROR(("%s: resumed on timeout, INT status=0x%08X\n",
++				__FUNCTION__, status));
++#else
++			DHD_ERROR(("%s: resumed on timeout\n", __FUNCTION__));
++#endif /* DHD_DEBUG */
++			if (!bus->dhd->dongle_trap_occured) {
++#ifdef DHD_FW_COREDUMP
++				bus->dhd->memdump_type = DUMP_TYPE_RESUMED_ON_TIMEOUT;
++#endif /* DHD_FW_COREDUMP */
++				dhd_os_sdlock(bus->dhd);
++				dhdsdio_checkdied(bus, NULL, 0);
++				dhd_os_sdunlock(bus->dhd);
++			}
++		} else {
++			DHD_CTL(("%s: resumed for unknown reason?\n", __FUNCTION__));
++			if (!bus->dhd->dongle_trap_occured) {
++#ifdef DHD_FW_COREDUMP
++				bus->dhd->memdump_type = DUMP_TYPE_RESUMED_UNKNOWN;
++#endif /* DHD_FW_COREDUMP */
++				dhd_os_sdlock(bus->dhd);
++				dhdsdio_checkdied(bus, NULL, 0);
++				dhd_os_sdunlock(bus->dhd);
++			}
++		}
++#ifdef DHD_FW_COREDUMP
++		/* Dump the ram image */
++		if (bus->dhd->memdump_enabled && !bus->dhd->dongle_trap_occured)
++			dhdsdio_mem_dump(bus);
++#endif /* DHD_FW_COREDUMP */
++	}
++	if (timeleft == 0) {
++		if (rxlen == 0)
++			bus->dhd->rxcnt_timeout++;
++		DHD_ERROR(("%s: rxcnt_timeout=%d, rxlen=%d\n", __FUNCTION__,
++			bus->dhd->rxcnt_timeout, rxlen));
++#ifdef DHD_FW_COREDUMP
++		/* collect socram dump */
++		if (bus->dhd->memdump_enabled) {
++			bus->dhd->memdump_type = DUMP_TYPE_RESUMED_ON_TIMEOUT_RX;
++			dhd_bus_mem_dump(bus->dhd);
++		}
++#endif /* DHD_FW_COREDUMP */
++	} else {
++		bus->dhd->rxcnt_timeout = 0;
++	}
++
++	if (rxlen)
++		bus->dhd->rx_ctlpkts++;
++	else
++		bus->dhd->rx_ctlerrs++;
++
++	if (bus->dhd->rxcnt_timeout >= MAX_CNTL_RX_TIMEOUT) {
++		return -ETIMEDOUT;
++	}
++
++
++	if (bus->dhd->dongle_trap_occured)
++		return -EREMOTEIO;
++
++	return rxlen ? (int)rxlen : -EIO;
++}
++
++/* IOVar table */
++enum {
++	IOV_INTR = 1,
++	IOV_POLLRATE,
++	IOV_SDREG,
++	IOV_SBREG,
++	IOV_SDCIS,
++	IOV_RAMSIZE,
++	IOV_RAMSTART,
++#ifdef DHD_DEBUG
++	IOV_CHECKDIED,
++	IOV_SERIALCONS,
++#endif /* DHD_DEBUG */
++	IOV_SET_DOWNLOAD_STATE,
++	IOV_SOCRAM_STATE,
++	IOV_FORCEEVEN,
++	IOV_SDIOD_DRIVE,
++	IOV_READAHEAD,
++	IOV_SDRXCHAIN,
++	IOV_ALIGNCTL,
++	IOV_SDALIGN,
++	IOV_DEVRESET,
++	IOV_CPU,
++#if defined(USE_SDIOFIFO_IOVAR)
++	IOV_WATERMARK,
++	IOV_MESBUSYCTRL,
++#endif /* USE_SDIOFIFO_IOVAR */
++#ifdef SDTEST
++	IOV_PKTGEN,
++	IOV_EXTLOOP,
++#endif /* SDTEST */
++	IOV_SPROM,
++	IOV_TXBOUND,
++	IOV_RXBOUND,
++	IOV_TXMINMAX,
++	IOV_IDLETIME,
++	IOV_IDLECLOCK,
++	IOV_SD1IDLE,
++	IOV_SLEEP,
++	IOV_DONGLEISOLATION,
++	IOV_KSO,
++	IOV_DEVSLEEP,
++	IOV_DEVCAP,
++	IOV_VARS,
++#ifdef SOFTAP
++	IOV_FWPATH,
++#endif
++	IOV_TXGLOMSIZE,
++	IOV_TXGLOMMODE,
++	IOV_HANGREPORT,
++	IOV_TXINRX_THRES,
++	IOV_SDIO_SUSPEND
++};
++
++const bcm_iovar_t dhdsdio_iovars[] = {
++	{"intr",	IOV_INTR,	0, 0,	IOVT_BOOL,	0 },
++	{"sleep",	IOV_SLEEP,	0, 0,	IOVT_BOOL,	0 },
++	{"pollrate",	IOV_POLLRATE,	0, 0,	IOVT_UINT32,	0 },
++	{"idletime",	IOV_IDLETIME,	0, 0,	IOVT_INT32,	0 },
++	{"idleclock",	IOV_IDLECLOCK,	0, 0,	IOVT_INT32,	0 },
++	{"sd1idle",	IOV_SD1IDLE,	0, 0,	IOVT_BOOL,	0 },
++	{"ramsize",	IOV_RAMSIZE,	0, 0,	IOVT_UINT32,	0 },
++	{"ramstart",	IOV_RAMSTART,	0, 0,	IOVT_UINT32,	0 },
++	{"dwnldstate",	IOV_SET_DOWNLOAD_STATE,	0, 0,	IOVT_BOOL,	0 },
++	{"socram_state",	IOV_SOCRAM_STATE,	0, 0,	IOVT_BOOL,	0 },
++	{"vars",	IOV_VARS,	0, 0,	IOVT_BUFFER,	0 },
++	{"sdiod_drive",	IOV_SDIOD_DRIVE, 0, 0,	IOVT_UINT32,	0 },
++	{"readahead",	IOV_READAHEAD,	0, 0,	IOVT_BOOL,	0 },
++	{"sdrxchain",	IOV_SDRXCHAIN,	0, 0,	IOVT_BOOL,	0 },
++	{"alignctl",	IOV_ALIGNCTL,	0, 0,	IOVT_BOOL,	0 },
++	{"sdalign",	IOV_SDALIGN,	0, 0,	IOVT_BOOL,	0 },
++	{"devreset",	IOV_DEVRESET,	0, 0,	IOVT_BOOL,	0 },
++#ifdef DHD_DEBUG
++	{"sdreg",	IOV_SDREG,	0, 0,	IOVT_BUFFER,	sizeof(sdreg_t) },
++	{"sbreg",	IOV_SBREG,	0, 0,	IOVT_BUFFER,	sizeof(sdreg_t) },
++	{"sd_cis",	IOV_SDCIS,	0, 0,	IOVT_BUFFER,	DHD_IOCTL_MAXLEN },
++	{"forcealign",	IOV_FORCEEVEN,	0, 0,	IOVT_BOOL,	0 },
++	{"txbound",	IOV_TXBOUND,	0, 0,	IOVT_UINT32,	0 },
++	{"rxbound",	IOV_RXBOUND,	0, 0,	IOVT_UINT32,	0 },
++	{"txminmax",	IOV_TXMINMAX,	0, 0,	IOVT_UINT32,	0 },
++	{"cpu",		IOV_CPU,	0, 0,	IOVT_BOOL,	0 },
++#ifdef DHD_DEBUG
++	{"checkdied",	IOV_CHECKDIED,	0, 0,	IOVT_BUFFER,	0 },
++	{"serial",	IOV_SERIALCONS,	0, 0,	IOVT_UINT32,	0 },
++#endif /* DHD_DEBUG  */
++#endif /* DHD_DEBUG */
++#ifdef SDTEST
++	{"extloop",	IOV_EXTLOOP,	0, 0,	IOVT_BOOL,	0 },
++	{"pktgen",	IOV_PKTGEN,	0, 0,	IOVT_BUFFER,	sizeof(dhd_pktgen_t) },
++#endif /* SDTEST */
++#if defined(USE_SDIOFIFO_IOVAR)
++	{"watermark",	IOV_WATERMARK,	0, 0,	IOVT_UINT32,	0 },
++	{"mesbusyctrl",	IOV_MESBUSYCTRL,	0, 0,	IOVT_UINT32,	0 },
++#endif /* USE_SDIOFIFO_IOVAR */
++	{"devcap", IOV_DEVCAP,	0, 0,	IOVT_UINT32,	0 },
++	{"dngl_isolation", IOV_DONGLEISOLATION,	0, 0,	IOVT_UINT32,	0 },
++	{"kso",	IOV_KSO,	0, 0,	IOVT_UINT32,	0 },
++	{"devsleep", IOV_DEVSLEEP,	0, 0,	IOVT_UINT32,	0 },
++#ifdef SOFTAP
++	{"fwpath", IOV_FWPATH, 0, 0, IOVT_BUFFER, 0 },
++#endif
++	{"txglomsize", IOV_TXGLOMSIZE, 0, 0, IOVT_UINT32, 0 },
++	{"fw_hang_report", IOV_HANGREPORT, 0, 0, IOVT_BOOL, 0 },
++	{"txinrx_thres", IOV_TXINRX_THRES, 0, 0, IOVT_INT32, 0 },
++	{"sdio_suspend", IOV_SDIO_SUSPEND, 0, 0, IOVT_UINT32, 0 },
++	{NULL, 0, 0, 0, 0, 0 }
++};
++
++static void
++dhd_dump_pct(struct bcmstrbuf *strbuf, char *desc, uint num, uint div)
++{
++	uint q1, q2;
++
++	if (!div) {
++		bcm_bprintf(strbuf, "%s N/A", desc);
++	} else {
++		q1 = num / div;
++		q2 = (100 * (num - (q1 * div))) / div;
++		bcm_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
++	}
++}
++
++void
++dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
++{
++	dhd_bus_t *bus = dhdp->bus;
++#if defined(DHD_WAKE_STATUS) && defined(DHD_WAKE_EVENT_STATUS)
++	int i;
++#endif
++
++	bcm_bprintf(strbuf, "Bus SDIO structure:\n");
++	bcm_bprintf(strbuf, "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
++	            bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
++	bcm_bprintf(strbuf, "fcstate %d qlen %u tx_seq %d, max %d, rxskip %d rxlen %u rx_seq %d\n",
++	            bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max, bus->rxskip,
++	            bus->rxlen, bus->rx_seq);
++	bcm_bprintf(strbuf, "intr %d intrcount %u lastintrs %u spurious %u\n",
++	            bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
++
++#ifdef DHD_WAKE_STATUS
++	bcm_bprintf(strbuf, "wake %u rxwake %u readctrlwake %u\n",
++		bcmsdh_get_total_wake(bus->sdh), bus->wake_counts.rxwake,
++		bus->wake_counts.rcwake);
++#ifdef DHD_WAKE_RX_STATUS
++	bcm_bprintf(strbuf, " unicast %u multicast %u broadcast %u arp %u\n",
++		bus->wake_counts.rx_ucast, bus->wake_counts.rx_mcast,
++		bus->wake_counts.rx_bcast, bus->wake_counts.rx_arp);
++	bcm_bprintf(strbuf, " multi4 %u multi6 %u icmp6 %u multiother %u\n",
++		bus->wake_counts.rx_multi_ipv4, bus->wake_counts.rx_multi_ipv6,
++		bus->wake_counts.rx_icmpv6, bus->wake_counts.rx_multi_other);
++	bcm_bprintf(strbuf, " icmp6_ra %u, icmp6_na %u, icmp6_ns %u\n",
++		bus->wake_counts.rx_icmpv6_ra, bus->wake_counts.rx_icmpv6_na,
++		bus->wake_counts.rx_icmpv6_ns);
++#endif /* DHD_WAKE_RX_STATUS */
++#ifdef DHD_WAKE_EVENT_STATUS
++	for (i = 0; i < WLC_E_LAST; i++)
++		if (bus->wake_counts.rc_event[i] != 0)
++			bcm_bprintf(strbuf, " %s = %u\n", bcmevent_get_name(i),
++				bus->wake_counts.rc_event[i]);
++	bcm_bprintf(strbuf, "\n");
++#endif /* DHD_WAKE_EVENT_STATUS */
++#endif /* DHD_WAKE_STATUS */
++
++	bcm_bprintf(strbuf, "pollrate %u pollcnt %u regfails %u\n",
++	            bus->pollrate, bus->pollcnt, bus->regfails);
++
++	bcm_bprintf(strbuf, "\nAdditional counters:\n");
++#ifdef DHDENABLE_TAILPAD
++	bcm_bprintf(strbuf, "tx_tailpad_chain %u tx_tailpad_pktget %u\n",
++	            bus->tx_tailpad_chain, bus->tx_tailpad_pktget);
++#endif /* DHDENABLE_TAILPAD */
++	bcm_bprintf(strbuf, "tx_sderrs %u fcqueued %u rxrtx %u rx_toolong %u rxc_errors %u\n",
++	            bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
++	            bus->rxc_errors);
++	bcm_bprintf(strbuf, "rx_hdrfail %u badhdr %u badseq %u\n",
++	            bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
++	bcm_bprintf(strbuf, "fc_rcvd %u, fc_xoff %u, fc_xon %u\n",
++	            bus->fc_rcvd, bus->fc_xoff, bus->fc_xon);
++	bcm_bprintf(strbuf, "rxglomfail %u, rxglomframes %u, rxglompkts %u\n",
++	            bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
++	bcm_bprintf(strbuf, "f2rx (hdrs/data) %u (%u/%u), f2tx %u f1regs %u\n",
++	            (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs, bus->f2rxdata,
++	            bus->f2txdata, bus->f1regdata);
++	{
++		dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
++		             (bus->f2rxhdrs + bus->f2rxdata));
++		dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets, bus->f1regdata);
++		dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
++		             (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
++		dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets, bus->intrcount);
++		bcm_bprintf(strbuf, "\n");
++
++		dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
++		             bus->dhd->rx_packets);
++		dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts, bus->rxglomframes);
++		bcm_bprintf(strbuf, "\n");
++
++		dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets, bus->f2txdata);
++		dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets, bus->f1regdata);
++		dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
++		             (bus->f2txdata + bus->f1regdata));
++		dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets, bus->intrcount);
++		bcm_bprintf(strbuf, "\n");
++
++		dhd_dump_pct(strbuf, "Total: pkts/f2rw",
++		             (bus->dhd->tx_packets + bus->dhd->rx_packets),
++		             (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
++		dhd_dump_pct(strbuf, ", pkts/f1sd",
++		             (bus->dhd->tx_packets + bus->dhd->rx_packets), bus->f1regdata);
++		dhd_dump_pct(strbuf, ", pkts/sd",
++		             (bus->dhd->tx_packets + bus->dhd->rx_packets),
++		             (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
++		dhd_dump_pct(strbuf, ", pkts/int",
++		             (bus->dhd->tx_packets + bus->dhd->rx_packets), bus->intrcount);
++		bcm_bprintf(strbuf, "\n\n");
++	}
++
++#ifdef SDTEST
++	if (bus->pktgen_count) {
++		bcm_bprintf(strbuf, "pktgen config and count:\n");
++		bcm_bprintf(strbuf, "freq %u count %u print %u total %u min %u len %u\n",
++		            bus->pktgen_freq, bus->pktgen_count, bus->pktgen_print,
++		            bus->pktgen_total, bus->pktgen_minlen, bus->pktgen_maxlen);
++		bcm_bprintf(strbuf, "send attempts %u rcvd %u fail %u\n",
++		            bus->pktgen_sent, bus->pktgen_rcvd, bus->pktgen_fail);
++	}
++#endif /* SDTEST */
++#ifdef DHD_DEBUG
++	bcm_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
++	            bus->dpc_sched, (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
++	bcm_bprintf(strbuf, "blocksize %u roundup %u\n", bus->blocksize, bus->roundup);
++#endif /* DHD_DEBUG */
++	bcm_bprintf(strbuf, "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
++	            bus->clkstate, bus->activity, bus->idletime, bus->idlecount, bus->sleeping);
++	dhd_dump_pct(strbuf, "Tx: glom pct", (100 * bus->txglompkts), bus->dhd->tx_packets);
++	dhd_dump_pct(strbuf, ", pkts/glom", bus->txglompkts, bus->txglomframes);
++	bcm_bprintf(strbuf, "\n");
++	bcm_bprintf(strbuf, "txglomframes %u, txglompkts %u\n", bus->txglomframes, bus->txglompkts);
++	bcm_bprintf(strbuf, "\n");
++}
++
++void
++dhd_bus_clearcounts(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = (dhd_bus_t *)dhdp->bus;
++
++	bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
++	bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
++	bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
++#ifdef DHDENABLE_TAILPAD
++	bus->tx_tailpad_chain = bus->tx_tailpad_pktget = 0;
++#endif /* DHDENABLE_TAILPAD */
++	bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
++	bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
++	bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
++	bus->txglomframes = bus->txglompkts = 0;
++}
++
++#ifdef SDTEST
++static int
++dhdsdio_pktgen_get(dhd_bus_t *bus, uint8 *arg)
++{
++	dhd_pktgen_t pktgen;
++
++	pktgen.version = DHD_PKTGEN_VERSION;
++	pktgen.freq = bus->pktgen_freq;
++	pktgen.count = bus->pktgen_count;
++	pktgen.print = bus->pktgen_print;
++	pktgen.total = bus->pktgen_total;
++	pktgen.minlen = bus->pktgen_minlen;
++	pktgen.maxlen = bus->pktgen_maxlen;
++	pktgen.numsent = bus->pktgen_sent;
++	pktgen.numrcvd = bus->pktgen_rcvd;
++	pktgen.numfail = bus->pktgen_fail;
++	pktgen.mode = bus->pktgen_mode;
++	pktgen.stop = bus->pktgen_stop;
++
++	bcopy(&pktgen, arg, sizeof(pktgen));
++
++	return 0;
++}
++
++static int
++dhdsdio_pktgen_set(dhd_bus_t *bus, uint8 *arg)
++{
++	dhd_pktgen_t pktgen;
++	uint oldcnt, oldmode;
++
++	bcopy(arg, &pktgen, sizeof(pktgen));
++	if (pktgen.version != DHD_PKTGEN_VERSION)
++		return BCME_BADARG;
++
++	oldcnt = bus->pktgen_count;
++	oldmode = bus->pktgen_mode;
++
++	bus->pktgen_freq = pktgen.freq;
++	bus->pktgen_count = pktgen.count;
++	bus->pktgen_print = pktgen.print;
++	bus->pktgen_total = pktgen.total;
++	bus->pktgen_minlen = pktgen.minlen;
++	bus->pktgen_maxlen = pktgen.maxlen;
++	bus->pktgen_mode = pktgen.mode;
++	bus->pktgen_stop = pktgen.stop;
++
++	bus->pktgen_tick = bus->pktgen_ptick = 0;
++	bus->pktgen_prev_time = jiffies;
++	bus->pktgen_len = MAX(bus->pktgen_len, bus->pktgen_minlen);
++	bus->pktgen_len = MIN(bus->pktgen_len, bus->pktgen_maxlen);
++
++	/* Clear counts for a new pktgen (mode change, or was stopped) */
++	if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode)) {
++		bus->pktgen_sent = bus->pktgen_prev_sent = bus->pktgen_rcvd = 0;
++		bus->pktgen_prev_rcvd = bus->pktgen_fail = 0;
++	}
++
++	return 0;
++}
++#endif /* SDTEST */
++
++static void
++dhdsdio_devram_remap(dhd_bus_t *bus, bool val)
++{
++	uint8 enable, protect, remap;
++
++	si_socdevram(bus->sih, FALSE, &enable, &protect, &remap);
++	remap = val ? TRUE : FALSE;
++	si_socdevram(bus->sih, TRUE, &enable, &protect, &remap);
++}
++
++static int
++dhdsdio_membytes(dhd_bus_t *bus, bool write, uint32 address, uint8 *data, uint size)
++{
++	int bcmerror = 0;
++	uint32 sdaddr;
++	uint dsize;
++	uint8 *pdata;
++
++	/* In remap mode, adjust address beyond socram and redirect
++	 * to devram at SOCDEVRAM_BP_ADDR since remap address > orig_ramsize
++	 * is not backplane accessible
++	 */
++	if (REMAP_ENAB(bus) && REMAP_ISADDR(bus, address)) {
++		address -= bus->orig_ramsize;
++		address += SOCDEVRAM_BP_ADDR;
++	}
++
++	/* Determine initial transfer parameters */
++	sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
++	if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
++		dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
++	else
++		dsize = size;
++
++	/* Set the backplane window to include the start address */
++	if ((bcmerror = dhdsdio_set_siaddr_window(bus, address))) {
++		DHD_ERROR(("%s: window change failed\n", __FUNCTION__));
++		goto xfer_done;
++	}
++
++	/* Do the transfer(s) */
++	while (size) {
++		DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
++		          __FUNCTION__, (write ? "write" : "read"), dsize, sdaddr,
++		          (address & SBSDIO_SBWINDOW_MASK)));
++		if (dsize <= MAX_MEM_BUF) {
++			pdata = bus->membuf;
++			if (write)
++				memcpy(bus->membuf, data, dsize);
++		} else {
++			pdata = data;
++		}
++		if ((bcmerror = bcmsdh_rwdata(bus->sdh, write, sdaddr, pdata, dsize))) {
++			DHD_ERROR(("%s: membytes transfer failed\n", __FUNCTION__));
++			break;
++		}
++		if (dsize <= MAX_MEM_BUF && !write)
++			memcpy(data, bus->membuf, dsize);
++
++		/* Adjust for next transfer (if any) */
++		if ((size -= dsize)) {
++			data += dsize;
++			address += dsize;
++			if ((bcmerror = dhdsdio_set_siaddr_window(bus, address))) {
++				DHD_ERROR(("%s: window change failed\n", __FUNCTION__));
++				break;
++			}
++			sdaddr = 0;
++			dsize = MIN(SBSDIO_SB_OFT_ADDR_LIMIT, size);
++		}
++
++	}
++
++xfer_done:
++	/* Return the window to backplane enumeration space for core access */
++	if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
++		DHD_ERROR(("%s: FAILED to set window back to 0x%x\n", __FUNCTION__,
++			bcmsdh_cur_sbwad(bus->sdh)));
++	}
++
++	return bcmerror;
++}
++
++static int
++dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
++{
++	uint32 addr;
++	int rv, i;
++	uint32 shaddr = 0;
++
++	if (bus->sih == NULL) {
++		if (bus->dhd && bus->dhd->dongle_reset) {
++			DHD_ERROR(("%s: Dongle is in reset state\n", __FUNCTION__));
++			return BCME_NOTREADY;
++		} else {
++			ASSERT(bus->dhd);
++			ASSERT(bus->sih);
++			DHD_ERROR(("%s: The address of sih is invalid\n", __FUNCTION__));
++			return BCME_ERROR;
++		}
++	}
++	if ((CHIPID(bus->sih->chip) == BCM43430_CHIP_ID ||
++		CHIPID(bus->sih->chip) == BCM43018_CHIP_ID) && !dhdsdio_sr_cap(bus))
++		bus->srmemsize = 0;
++
++	shaddr = bus->dongle_ram_base + bus->ramsize - 4;
++	i = 0;
++	do {
++		/* Read last word in memory to determine address of sdpcm_shared structure */
++		if ((rv = dhdsdio_membytes(bus, FALSE, shaddr, (uint8 *)&addr, 4)) < 0)
++			return rv;
++
++		addr = ltoh32(addr);
++
++		DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
++
++		/*
++		 * Check if addr is valid.
++		 * NVRAM length at the end of memory should have been overwritten.
++		 */
++		if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
++			if ((bus->srmemsize > 0) && (i++ == 0)) {
++				shaddr -= bus->srmemsize;
++			} else {
++				DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
++					__FUNCTION__, addr));
++				return BCME_ERROR;
++			}
++		} else
++			break;
++	} while (i < 2);
++
++	/* Read hndrte_shared structure */
++	if ((rv = dhdsdio_membytes(bus, FALSE, addr, (uint8 *)sh, sizeof(sdpcm_shared_t))) < 0)
++		return rv;
++
++	/* Endianness */
++	sh->flags = ltoh32(sh->flags);
++	sh->trap_addr = ltoh32(sh->trap_addr);
++	sh->assert_exp_addr = ltoh32(sh->assert_exp_addr);
++	sh->assert_file_addr = ltoh32(sh->assert_file_addr);
++	sh->assert_line = ltoh32(sh->assert_line);
++	sh->console_addr = ltoh32(sh->console_addr);
++	sh->msgtrace_addr = ltoh32(sh->msgtrace_addr);
++
++#ifdef BCMSDIO_RXLIM_POST
++	if (sh->flags & SDPCM_SHARED_RXLIM_POST) {
++		if (bus->dhd->conf->rxlim_en)
++			bus->rxlim_en = !!sh->msgtrace_addr;
++		bus->rxlim_addr = sh->msgtrace_addr;
++		DHD_INFO(("%s: rxlim_en=%d, rxlim enable=%d, rxlim_addr=%d\n",
++			__FUNCTION__,
++			bus->dhd->conf->rxlim_en, bus->rxlim_en, bus->rxlim_addr));
++		sh->flags &= ~SDPCM_SHARED_RXLIM_POST;
++	} else {
++		bus->rxlim_en = 0;
++		DHD_INFO(("%s: FW has no rx limit post support\n", __FUNCTION__));
++	}
++#endif /* BCMSDIO_RXLIM_POST */
++
++	if ((sh->flags & SDPCM_SHARED_VERSION_MASK) == 3 && SDPCM_SHARED_VERSION == 1)
++		return BCME_OK;
++
++	if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
++		DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
++		           "is different than sdpcm_shared version %d in dongle\n",
++		           __FUNCTION__, SDPCM_SHARED_VERSION,
++		           sh->flags & SDPCM_SHARED_VERSION_MASK));
++		return BCME_ERROR;
++	}
++
++	return BCME_OK;
++}
++
++#define CONSOLE_LINE_MAX	192
++
++#ifdef DHD_DEBUG
++static int
++dhdsdio_readconsole(dhd_bus_t *bus)
++{
++	dhd_console_t *c = &bus->console;
++	uint8 line[CONSOLE_LINE_MAX], ch;
++	uint32 n, idx, addr;
++	int rv;
++
++	/* Don't do anything until FWREADY updates console address */
++	if (bus->console_addr == 0)
++		return 0;
++
++	if (!KSO_ENAB(bus))
++		return 0;
++
++	/* Read console log struct */
++	addr = bus->console_addr + OFFSETOF(hnd_cons_t, log);
++	if ((rv = dhdsdio_membytes(bus, FALSE, addr, (uint8 *)&c->log, sizeof(c->log))) < 0)
++		return rv;
++
++	/* Allocate console buffer (one time only) */
++	if (c->buf == NULL) {
++		c->bufsize = ltoh32(c->log.buf_size);
++		if ((c->buf = MALLOC(bus->dhd->osh, c->bufsize)) == NULL)
++			return BCME_NOMEM;
++	}
++
++	idx = ltoh32(c->log.idx);
++
++	/* Protect against corrupt value */
++	if (idx > c->bufsize)
++		return BCME_ERROR;
++
++	/* Skip reading the console buffer if the index pointer has not moved */
++	if (idx == c->last)
++		return BCME_OK;
++
++	/* Read the console buffer */
++	addr = ltoh32(c->log.buf);
++	if ((rv = dhdsdio_membytes(bus, FALSE, addr, c->buf, c->bufsize)) < 0)
++		return rv;
++
++	while (c->last != idx) {
++		for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
++			if (c->last == idx) {
++				/* This would output a partial line.  Instead, back up
++				 * the buffer pointer and output this line next time around.
++				 */
++				if (c->last >= n)
++					c->last -= n;
++				else
++					c->last = c->bufsize - n;
++				goto break2;
++			}
++			ch = c->buf[c->last];
++			c->last = (c->last + 1) % c->bufsize;
++			if (ch == '\n')
++				break;
++			line[n] = ch;
++		}
++
++		if (n > 0) {
++			if (line[n - 1] == '\r')
++				n--;
++			line[n] = 0;
++			printf("CONSOLE: %s\n", line);
++#ifdef LOG_INTO_TCPDUMP
++			dhd_sendup_log(bus->dhd, line, n);
++#endif /* LOG_INTO_TCPDUMP */
++		}
++	}
++break2:
++
++	return BCME_OK;
++}
++#endif /* DHD_DEBUG */
++
++static int
++dhdsdio_checkdied(dhd_bus_t *bus, char *data, uint size)
++{
++	int bcmerror = 0;
++	uint msize = 512;
++	char *mbuffer = NULL;
++	char *console_buffer = NULL;
++	uint maxstrlen = 256;
++	char *str = NULL;
++	sdpcm_shared_t l_sdpcm_shared;
++	struct bcmstrbuf strbuf;
++	uint32 console_ptr, console_size, console_index;
++	uint8 line[CONSOLE_LINE_MAX], ch;
++	uint32 n, i, addr;
++	int rv;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (DHD_NOCHECKDIED_ON())
++		return 0;
++
++	if (data == NULL) {
++		/*
++		 * Called after a rx ctrl timeout. "data" is NULL.
++		 * allocate memory to trace the trap or assert.
++		 */
++		size = msize;
++		mbuffer = data = MALLOC(bus->dhd->osh, msize);
++		if (mbuffer == NULL) {
++			DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, msize));
++			bcmerror = BCME_NOMEM;
++			goto done;
++		}
++	}
++
++	if ((str = MALLOC(bus->dhd->osh, maxstrlen)) == NULL) {
++		DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, maxstrlen));
++		bcmerror = BCME_NOMEM;
++		goto done;
++	}
++
++	if ((bcmerror = dhdsdio_readshared(bus, &l_sdpcm_shared)) < 0)
++		goto done;
++
++	bcm_binit(&strbuf, data, size);
++
++	bcm_bprintf(&strbuf, "msgtrace address : 0x%08X\nconsole address  : 0x%08X\n",
++	            l_sdpcm_shared.msgtrace_addr, l_sdpcm_shared.console_addr);
++
++	if ((l_sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
++		/* NOTE: Misspelled assert is intentional - DO NOT FIX.
++		 * (Avoids conflict with real asserts for programmatic parsing of output.)
++		 */
++		bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
++	}
++
++	if ((l_sdpcm_shared.flags & (SDPCM_SHARED_ASSERT|SDPCM_SHARED_TRAP)) == 0) {
++		/* NOTE: Misspelled assert is intentional - DO NOT FIX.
++		 * (Avoids conflict with real asserts for programmatic parsing of output.)
++		 */
++		bcm_bprintf(&strbuf, "No trap%s in dongle",
++		          (l_sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
++		          ?"/assrt" :"");
++	} else {
++		if (l_sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
++			/* Download assert */
++			bcm_bprintf(&strbuf, "Dongle assert");
++			if (l_sdpcm_shared.assert_exp_addr != 0) {
++				str[0] = '\0';
++				if ((bcmerror = dhdsdio_membytes(bus, FALSE,
++				                                 l_sdpcm_shared.assert_exp_addr,
++				                                 (uint8 *)str, maxstrlen)) < 0)
++					goto done;
++
++				str[maxstrlen - 1] = '\0';
++				bcm_bprintf(&strbuf, " expr \"%s\"", str);
++			}
++
++			if (l_sdpcm_shared.assert_file_addr != 0) {
++				str[0] = '\0';
++				if ((bcmerror = dhdsdio_membytes(bus, FALSE,
++				                   l_sdpcm_shared.assert_file_addr,
++				                                 (uint8 *)str, maxstrlen)) < 0)
++					goto done;
++
++				str[maxstrlen - 1] = '\0';
++				bcm_bprintf(&strbuf, " file \"%s\"", str);
++			}
++
++			bcm_bprintf(&strbuf, " line %d ", l_sdpcm_shared.assert_line);
++		}
++
++		if (l_sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
++			trap_t *tr = &bus->dhd->last_trap_info;
++			bus->dhd->dongle_trap_occured = TRUE;
++			if ((bcmerror = dhdsdio_membytes(bus, FALSE,
++			                                 l_sdpcm_shared.trap_addr,
++			                                 (uint8*)tr, sizeof(trap_t))) < 0)
++				goto done;
++
++			bus->dongle_trap_addr = ltoh32(l_sdpcm_shared.trap_addr);
++
++			dhd_bus_dump_trap_info(bus, &strbuf);
++
++			addr = l_sdpcm_shared.console_addr + OFFSETOF(hnd_cons_t, log);
++			if ((rv = dhdsdio_membytes(bus, FALSE, addr,
++				(uint8 *)&console_ptr, sizeof(console_ptr))) < 0)
++				goto printbuf;
++
++			addr = l_sdpcm_shared.console_addr + OFFSETOF(hnd_cons_t, log.buf_size);
++			if ((rv = dhdsdio_membytes(bus, FALSE, addr,
++				(uint8 *)&console_size, sizeof(console_size))) < 0)
++				goto printbuf;
++
++			addr = l_sdpcm_shared.console_addr + OFFSETOF(hnd_cons_t, log.idx);
++			if ((rv = dhdsdio_membytes(bus, FALSE, addr,
++				(uint8 *)&console_index, sizeof(console_index))) < 0)
++				goto printbuf;
++
++			console_ptr = ltoh32(console_ptr);
++			console_size = ltoh32(console_size);
++			console_index = ltoh32(console_index);
++
++			if (console_size > CONSOLE_BUFFER_MAX ||
++				!(console_buffer = MALLOC(bus->dhd->osh, console_size)))
++				goto printbuf;
++
++			if ((rv = dhdsdio_membytes(bus, FALSE, console_ptr,
++				(uint8 *)console_buffer, console_size)) < 0)
++				goto printbuf;
++
++			for (i = 0, n = 0; i < console_size; i += n + 1) {
++				for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
++					ch = console_buffer[(console_index + i + n) % console_size];
++					if (ch == '\n')
++						break;
++					line[n] = ch;
++				}
++
++
++				if (n > 0) {
++					if (line[n - 1] == '\r')
++						n--;
++					line[n] = 0;
++					/* Don't use DHD_ERROR macro since we print
++					 * a lot of information quickly. The macro
++					 * will truncate a lot of the printfs
++					 */
++
++					if (dhd_msg_level & DHD_ERROR_VAL)
++						printf("CONSOLE: %s\n", line);
++				}
++			}
++		}
++	}
++
++printbuf:
++	if (l_sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) {
++		DHD_ERROR(("%s: %s\n", __FUNCTION__, strbuf.origbuf));
++	}
++
++#if defined(DHD_FW_COREDUMP)
++	if (bus->dhd->memdump_enabled && (l_sdpcm_shared.flags & SDPCM_SHARED_TRAP)) {
++		/* Mem dump to a file on device */
++		bus->dhd->memdump_type = DUMP_TYPE_DONGLE_TRAP;
++		dhd_os_sdunlock(bus->dhd);
++		dhdsdio_mem_dump(bus);
++		dhd_os_sdlock(bus->dhd);
++	}
++#endif /* #if defined(DHD_FW_COREDUMP) */
++
++done:
++	if (mbuffer)
++		MFREE(bus->dhd->osh, mbuffer, msize);
++	if (str)
++		MFREE(bus->dhd->osh, str, maxstrlen);
++	if (console_buffer)
++		MFREE(bus->dhd->osh, console_buffer, console_size);
++
++	return bcmerror;
++}
++
++#if defined(DHD_FW_COREDUMP)
++int
++dhd_bus_mem_dump(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	if (dhdp->busstate == DHD_BUS_SUSPEND) {
++		DHD_ERROR(("%s: Bus is suspend so skip\n", __FUNCTION__));
++		return 0;
++	}
++	return dhdsdio_mem_dump(bus);
++}
++
++static int
++dhdsdio_mem_dump(dhd_bus_t *bus)
++{
++	int ret = 0;
++	int size;				/* Full mem size */
++	uint32 start = bus->dongle_ram_base;	/* Start address */
++	uint read_size = 0;			/* Read size of each iteration */
++	uint8 *buf = NULL, *databuf = NULL;
++
++	/* Get full mem size */
++	size = bus->ramsize;
++	buf = dhd_get_fwdump_buf(bus->dhd, size);
++	if (!buf) {
++		DHD_ERROR(("%s: Out of memory (%d bytes)\n", __FUNCTION__, size));
++		return -1;
++	}
++
++	dhd_os_sdlock(bus->dhd);
++	BUS_WAKE(bus);
++	dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++	/* Read mem content */
++	DHD_ERROR(("Dump dongle memory\n"));
++	databuf = buf;
++	while (size)
++	{
++		read_size = MIN(MEMBLOCK, size);
++		if ((ret = dhdsdio_membytes(bus, FALSE, start, databuf, read_size)))
++		{
++			DHD_ERROR(("%s: Error membytes %d\n", __FUNCTION__, ret));
++			ret = BCME_ERROR;
++			break;
++		}
++		/* Decrement size and increment start address */
++		size -= read_size;
++		start += read_size;
++		databuf += read_size;
++	}
++
++	if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched &&
++		NO_OTHER_ACTIVE_BUS_USER(bus)) {
++		bus->activity = FALSE;
++		dhdsdio_clkctl(bus, CLK_NONE, TRUE);
++	}
++
++	dhd_os_sdunlock(bus->dhd);
++
++	/* schedule a work queue to perform actual memdump. dhd_mem_dump() performs the job */
++	if (!ret) {
++		/* buf, actually soc_ram free handled in dhd_{free,clear} */
++		dhd_schedule_memdump(bus->dhd, buf, bus->ramsize);
++	}
++
++	return ret;
++}
++#endif /* DHD_FW_COREDUMP */
++
++int
++dhd_socram_dump(dhd_bus_t * bus)
++{
++#if defined(DHD_FW_COREDUMP)
++	return (dhdsdio_mem_dump(bus));
++#else
++	return -1;
++#endif
++}
++
++int
++dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
++{
++	int bcmerror = BCME_OK;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus->dhd->up &&
++#ifdef DHD_ULP
++		(DHD_ULP_DISABLED == dhd_ulp_get_ulp_state(bus->dhd)) &&
++#endif /* DHD_ULP */
++		1) {
++		bcmerror = BCME_NOTDOWN;
++		goto err;
++	}
++	if (!len) {
++		bcmerror = BCME_BUFTOOSHORT;
++		goto err;
++	}
++
++	/* Free the old ones and replace with passed variables */
++	if (bus->vars)
++		MFREE(bus->dhd->osh, bus->vars, bus->varsz);
++
++	bus->vars = MALLOC(bus->dhd->osh, len);
++	bus->varsz = bus->vars ? len : 0;
++	if (bus->vars == NULL) {
++		bcmerror = BCME_NOMEM;
++		goto err;
++	}
++
++	/* Copy the passed variables, which should include the terminating double-null */
++	bcopy(arg, bus->vars, bus->varsz);
++err:
++	return bcmerror;
++}
++
++#ifdef DHD_DEBUG
++
++#define CC_PLL_CHIPCTRL_SERIAL_ENAB		(1  << 24)
++#define CC_CHIPCTRL_JTAG_SEL			(1  << 3)
++#define CC_CHIPCTRL_GPIO_SEL				(0x3)
++#define CC_PLL_CHIPCTRL_SERIAL_ENAB_4334	(1  << 28)
++
++static int
++dhd_serialconsole(dhd_bus_t *bus, bool set, bool enable, int *bcmerror)
++{
++	int int_val;
++	uint32 addr, data, uart_enab = 0;
++	uint32 jtag_sel = CC_CHIPCTRL_JTAG_SEL;
++	uint32 gpio_sel = CC_CHIPCTRL_GPIO_SEL;
++
++	addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_addr);
++	data = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_data);
++	*bcmerror = 0;
++
++	bcmsdh_reg_write(bus->sdh, addr, 4, 1);
++	if (bcmsdh_regfail(bus->sdh)) {
++		*bcmerror = BCME_SDIO_ERROR;
++		return -1;
++	}
++	int_val = bcmsdh_reg_read(bus->sdh, data, 4);
++	if (bcmsdh_regfail(bus->sdh)) {
++		*bcmerror = BCME_SDIO_ERROR;
++		return -1;
++	}
++
++	if (bus->sih->chip == BCM4330_CHIP_ID) {
++		uart_enab = CC_PLL_CHIPCTRL_SERIAL_ENAB;
++	} else if (bus->sih->chip == BCM4334_CHIP_ID ||
++		bus->sih->chip == BCM43340_CHIP_ID ||
++		bus->sih->chip == BCM43341_CHIP_ID ||
++		bus->sih->chip == BCM43342_CHIP_ID ||
++		0) {
++		if (enable) {
++			/* Moved to PMU chipcontrol 1 from 4330 */
++			int_val &= ~gpio_sel;
++			int_val |= jtag_sel;
++		} else {
++			int_val |= gpio_sel;
++			int_val &= ~jtag_sel;
++		}
++		uart_enab = CC_PLL_CHIPCTRL_SERIAL_ENAB_4334;
++	}
++
++	if (!set)
++		return (int_val & uart_enab);
++	if (enable)
++		int_val |= uart_enab;
++	else
++		int_val &= ~uart_enab;
++	bcmsdh_reg_write(bus->sdh, data, 4, int_val);
++	if (bcmsdh_regfail(bus->sdh)) {
++		*bcmerror = BCME_SDIO_ERROR;
++		return -1;
++	}
++	if (bus->sih->chip == BCM4330_CHIP_ID) {
++		uint32 chipcontrol;
++		addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol);
++		chipcontrol = bcmsdh_reg_read(bus->sdh, addr, 4);
++		chipcontrol &= ~jtag_sel;
++		if (enable) {
++			chipcontrol |=  jtag_sel;
++			chipcontrol &= ~gpio_sel;
++		}
++		bcmsdh_reg_write(bus->sdh, addr, 4, chipcontrol);
++	}
++
++	return (int_val & uart_enab);
++}
++#endif 
++
++static int
++dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, const char *name,
++                void *params, int plen, void *arg, int len, int val_size)
++{
++	int bcmerror = 0;
++	int32 int_val = 0;
++	bool bool_val = 0;
++
++	DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p len %d val_size %d\n",
++	           __FUNCTION__, actionid, name, params, plen, arg, len, val_size));
++
++	if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid))) != 0)
++		goto exit;
++
++	if (plen >= (int)sizeof(int_val))
++		bcopy(params, &int_val, sizeof(int_val));
++
++	bool_val = (int_val != 0) ? TRUE : FALSE;
++
++
++	/* Some ioctls use the bus */
++	dhd_os_sdlock(bus->dhd);
++
++	/* Check if dongle is in reset. If so, only allow DEVRESET iovars */
++	if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
++	                                actionid == IOV_GVAL(IOV_DEVRESET))) {
++		bcmerror = BCME_NOTREADY;
++		goto exit;
++	}
++
++	/*
++	 * Special handling for keepSdioOn: New SDIO Wake-up Mechanism
++	 */
++	if ((vi->varid == IOV_KSO) && (IOV_ISSET(actionid))) {
++		dhdsdio_clk_kso_iovar(bus, bool_val);
++		goto exit;
++	} else if ((vi->varid == IOV_DEVSLEEP) && (IOV_ISSET(actionid))) {
++		{
++			dhdsdio_clk_devsleep_iovar(bus, bool_val);
++			if (!SLPAUTO_ENAB(bus) && (bool_val == FALSE) && (bus->ipend)) {
++				DHD_ERROR(("INT pending in devsleep 1, dpc_sched: %d\n",
++					bus->dpc_sched));
++				if (!bus->dpc_sched) {
++					bus->dpc_sched = TRUE;
++					dhd_sched_dpc(bus->dhd);
++				}
++			}
++		}
++		goto exit;
++	}
++
++	/* Handle sleep stuff before any clock mucking */
++	if (vi->varid == IOV_SLEEP) {
++		if (IOV_ISSET(actionid)) {
++			bcmerror = dhdsdio_bussleep(bus, bool_val);
++		} else {
++			int_val = (int32)bus->sleeping;
++			bcopy(&int_val, arg, val_size);
++		}
++		goto exit;
++	}
++
++	/* Request clock to allow SDIO accesses */
++	if (!bus->dhd->dongle_reset) {
++		BUS_WAKE(bus);
++		dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++	}
++
++	switch (actionid) {
++	case IOV_GVAL(IOV_INTR):
++		int_val = (int32)bus->intr;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_INTR):
++		bus->intr = bool_val;
++		bus->intdis = FALSE;
++		if (bus->dhd->up) {
++			if (bus->intr) {
++				DHD_INTR(("%s: enable SDIO device interrupts\n", __FUNCTION__));
++				// terence 20141207: enbale intdis
++				bus->intdis = TRUE;
++				bcmsdh_intr_enable(bus->sdh);
++			} else {
++				DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__));
++				bcmsdh_intr_disable(bus->sdh);
++			}
++		}
++		break;
++
++	case IOV_GVAL(IOV_POLLRATE):
++		int_val = (int32)bus->pollrate;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_POLLRATE):
++		bus->pollrate = (uint)int_val;
++		bus->poll = (bus->pollrate != 0);
++		break;
++
++	case IOV_GVAL(IOV_IDLETIME):
++		int_val = bus->idletime;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_IDLETIME):
++		if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE)) {
++			bcmerror = BCME_BADARG;
++		} else {
++			bus->idletime = int_val;
++		}
++		break;
++
++	case IOV_GVAL(IOV_IDLECLOCK):
++		int_val = (int32)bus->idleclock;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_IDLECLOCK):
++		bus->idleclock = int_val;
++		break;
++
++	case IOV_GVAL(IOV_SD1IDLE):
++		int_val = (int32)sd1idle;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_SD1IDLE):
++		sd1idle = bool_val;
++		break;
++
++
++
++	case IOV_GVAL(IOV_RAMSIZE):
++		int_val = (int32)bus->ramsize;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_RAMSTART):
++		int_val = (int32)bus->dongle_ram_base;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_SDIOD_DRIVE):
++		int_val = (int32)dhd_sdiod_drive_strength;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_SDIOD_DRIVE):
++		dhd_sdiod_drive_strength = int_val;
++		si_sdiod_drive_strength_init(bus->sih, bus->dhd->osh, dhd_sdiod_drive_strength);
++		break;
++
++	case IOV_SVAL(IOV_SET_DOWNLOAD_STATE):
++		bcmerror = dhdsdio_download_state(bus, bool_val);
++		break;
++
++	case IOV_SVAL(IOV_SOCRAM_STATE):
++		bcmerror = dhdsdio_download_state(bus, bool_val);
++		break;
++
++	case IOV_SVAL(IOV_VARS):
++		bcmerror = dhdsdio_downloadvars(bus, arg, len);
++		break;
++
++	case IOV_GVAL(IOV_READAHEAD):
++		int_val = (int32)dhd_readahead;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_READAHEAD):
++		if (bool_val && !dhd_readahead)
++			bus->nextlen = 0;
++		dhd_readahead = bool_val;
++		break;
++
++	case IOV_GVAL(IOV_SDRXCHAIN):
++		int_val = (int32)bus->use_rxchain;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_SDRXCHAIN):
++		if (bool_val && !bus->sd_rxchain)
++			bcmerror = BCME_UNSUPPORTED;
++		else
++			bus->use_rxchain = bool_val;
++		break;
++	case IOV_GVAL(IOV_ALIGNCTL):
++		int_val = (int32)dhd_alignctl;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_ALIGNCTL):
++		dhd_alignctl = bool_val;
++		break;
++
++	case IOV_GVAL(IOV_SDALIGN):
++		int_val = DHD_SDALIGN;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++#ifdef DHD_DEBUG
++	case IOV_GVAL(IOV_VARS):
++		if (bus->varsz < (uint)len)
++			bcopy(bus->vars, arg, bus->varsz);
++		else
++			bcmerror = BCME_BUFTOOSHORT;
++		break;
++#endif /* DHD_DEBUG */
++
++#ifdef DHD_DEBUG
++	case IOV_GVAL(IOV_SDREG):
++	{
++		sdreg_t *sd_ptr;
++		uintptr addr;
++		uint size;
++
++		sd_ptr = (sdreg_t *)params;
++
++		addr = ((uintptr)bus->regs + sd_ptr->offset);
++		size = sd_ptr->func;
++		int_val = (int32)bcmsdh_reg_read(bus->sdh, addr, size);
++		if (bcmsdh_regfail(bus->sdh))
++			bcmerror = BCME_SDIO_ERROR;
++		bcopy(&int_val, arg, sizeof(int32));
++		break;
++	}
++
++	case IOV_SVAL(IOV_SDREG):
++	{
++		sdreg_t *sd_ptr;
++		uintptr addr;
++		uint size;
++
++		sd_ptr = (sdreg_t *)params;
++
++		addr = ((uintptr)bus->regs + sd_ptr->offset);
++		size = sd_ptr->func;
++		bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
++		if (bcmsdh_regfail(bus->sdh))
++			bcmerror = BCME_SDIO_ERROR;
++		break;
++	}
++
++	/* Same as above, but offset is not backplane (not SDIO core) */
++	case IOV_GVAL(IOV_SBREG):
++	{
++		sdreg_t sdreg;
++		uint32 addr, size;
++
++		bcopy(params, &sdreg, sizeof(sdreg));
++
++		addr = SI_ENUM_BASE + sdreg.offset;
++		size = sdreg.func;
++		int_val = (int32)bcmsdh_reg_read(bus->sdh, addr, size);
++		if (bcmsdh_regfail(bus->sdh))
++			bcmerror = BCME_SDIO_ERROR;
++		bcopy(&int_val, arg, sizeof(int32));
++		break;
++	}
++
++	case IOV_SVAL(IOV_SBREG):
++	{
++		sdreg_t sdreg;
++		uint32 addr, size;
++
++		bcopy(params, &sdreg, sizeof(sdreg));
++
++		addr = SI_ENUM_BASE + sdreg.offset;
++		size = sdreg.func;
++		bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
++		if (bcmsdh_regfail(bus->sdh))
++			bcmerror = BCME_SDIO_ERROR;
++		break;
++	}
++
++	case IOV_GVAL(IOV_SDCIS):
++	{
++		*(char *)arg = 0;
++
++		bcmstrcat(arg, "\nFunc 0\n");
++		bcmsdh_cis_read(bus->sdh, 0x10, (uint8 *)arg + strlen(arg), SBSDIO_CIS_SIZE_LIMIT);
++		bcmstrcat(arg, "\nFunc 1\n");
++		bcmsdh_cis_read(bus->sdh, 0x11, (uint8 *)arg + strlen(arg), SBSDIO_CIS_SIZE_LIMIT);
++		bcmstrcat(arg, "\nFunc 2\n");
++		bcmsdh_cis_read(bus->sdh, 0x12, (uint8 *)arg + strlen(arg), SBSDIO_CIS_SIZE_LIMIT);
++		break;
++	}
++
++	case IOV_GVAL(IOV_FORCEEVEN):
++		int_val = (int32)forcealign;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_FORCEEVEN):
++		forcealign = bool_val;
++		break;
++
++	case IOV_GVAL(IOV_TXBOUND):
++		int_val = (int32)dhd_txbound;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_TXBOUND):
++		dhd_txbound = (uint)int_val;
++		break;
++
++	case IOV_GVAL(IOV_RXBOUND):
++		int_val = (int32)dhd_rxbound;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_RXBOUND):
++		dhd_rxbound = (uint)int_val;
++		break;
++
++	case IOV_GVAL(IOV_TXMINMAX):
++		int_val = (int32)dhd_txminmax;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_TXMINMAX):
++		dhd_txminmax = (uint)int_val;
++		break;
++
++	case IOV_GVAL(IOV_SERIALCONS):
++		int_val = dhd_serialconsole(bus, FALSE, 0, &bcmerror);
++		if (bcmerror != 0)
++			break;
++
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_SERIALCONS):
++		dhd_serialconsole(bus, TRUE, bool_val, &bcmerror);
++		break;
++
++
++#endif /* DHD_DEBUG */
++
++
++#ifdef SDTEST
++	case IOV_GVAL(IOV_EXTLOOP):
++		int_val = (int32)bus->ext_loop;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_EXTLOOP):
++		bus->ext_loop = bool_val;
++		break;
++
++	case IOV_GVAL(IOV_PKTGEN):
++		bcmerror = dhdsdio_pktgen_get(bus, arg);
++		break;
++
++	case IOV_SVAL(IOV_PKTGEN):
++		bcmerror = dhdsdio_pktgen_set(bus, arg);
++		break;
++#endif /* SDTEST */
++
++#if defined(USE_SDIOFIFO_IOVAR)
++	case IOV_GVAL(IOV_WATERMARK):
++		int_val = (int32)watermark;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_WATERMARK):
++		watermark = (uint)int_val;
++		watermark = (watermark > SBSDIO_WATERMARK_MASK) ? SBSDIO_WATERMARK_MASK : watermark;
++		DHD_ERROR(("Setting watermark as 0x%x.\n", watermark));
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK, (uint8)watermark, NULL);
++		break;
++
++	case IOV_GVAL(IOV_MESBUSYCTRL):
++		int_val = (int32)mesbusyctrl;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_MESBUSYCTRL):
++		mesbusyctrl = (uint)int_val;
++		mesbusyctrl = (mesbusyctrl > SBSDIO_MESBUSYCTRL_MASK)
++			? SBSDIO_MESBUSYCTRL_MASK : mesbusyctrl;
++		DHD_ERROR(("Setting mesbusyctrl as 0x%x.\n", mesbusyctrl));
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_MESBUSYCTRL,
++			((uint8)mesbusyctrl | 0x80), NULL);
++		break;
++#endif 
++
++
++	case IOV_GVAL(IOV_DONGLEISOLATION):
++		int_val = bus->dhd->dongle_isolation;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DONGLEISOLATION):
++		bus->dhd->dongle_isolation = bool_val;
++		break;
++
++	case IOV_SVAL(IOV_DEVRESET):
++		DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d busstate=%d\n",
++		           __FUNCTION__, bool_val, bus->dhd->dongle_reset,
++		           bus->dhd->busstate));
++
++		ASSERT(bus->dhd->osh);
++		/* ASSERT(bus->cl_devid); */
++
++		dhd_bus_devreset(bus->dhd, (uint8)bool_val);
++
++		break;
++	/*
++	 * softap firmware is updated through module parameter or android private command
++	 */
++
++	case IOV_GVAL(IOV_DEVRESET):
++		DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __FUNCTION__));
++
++		/* Get its status */
++		int_val = (bool) bus->dhd->dongle_reset;
++		bcopy(&int_val, arg, val_size);
++
++		break;
++
++	case IOV_GVAL(IOV_KSO):
++		int_val = dhdsdio_sleepcsr_get(bus);
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_DEVCAP):
++		int_val = dhdsdio_devcap_get(bus);
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DEVCAP):
++		dhdsdio_devcap_set(bus, (uint8) int_val);
++		break;
++	case IOV_GVAL(IOV_TXGLOMSIZE):
++		int_val = (int32)bus->txglomsize;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_TXGLOMSIZE):
++		if (int_val > SDPCM_MAXGLOM_SIZE) {
++			bcmerror = BCME_ERROR;
++		} else {
++			bus->txglomsize = (uint)int_val;
++		}
++		break;
++	case IOV_SVAL(IOV_HANGREPORT):
++		bus->dhd->hang_report = bool_val;
++		DHD_ERROR(("%s: Set hang_report as %d\n", __FUNCTION__, bus->dhd->hang_report));
++		break;
++
++	case IOV_GVAL(IOV_HANGREPORT):
++		int_val = (int32)bus->dhd->hang_report;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_TXINRX_THRES):
++		int_val = bus->txinrx_thres;
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_SVAL(IOV_TXINRX_THRES):
++		if (int_val < 0) {
++			bcmerror = BCME_BADARG;
++		} else {
++			bus->txinrx_thres = int_val;
++		}
++		break;
++
++	case IOV_GVAL(IOV_SDIO_SUSPEND):
++		int_val = (bus->dhd->busstate == DHD_BUS_SUSPEND) ? 1 : 0;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_SDIO_SUSPEND):
++		if (bool_val) { /* Suspend */
++			dhdsdio_suspend(bus);
++		}
++		else { /* Resume */
++			dhdsdio_resume(bus);
++		}
++		break;
++
++	default:
++		bcmerror = BCME_UNSUPPORTED;
++		break;
++	}
++
++exit:
++	if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched &&
++		NO_OTHER_ACTIVE_BUS_USER(bus)) {
++		bus->activity = FALSE;
++		dhdsdio_bussleep(bus, TRUE);
++		dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++	}
++
++	dhd_os_sdunlock(bus->dhd);
++
++	return bcmerror;
++}
++
++static int
++dhdsdio_write_vars(dhd_bus_t *bus)
++{
++	int bcmerror = 0;
++	uint32 varsize, phys_size;
++	uint32 varaddr;
++	uint8 *vbuffer;
++	uint32 varsizew;
++#ifdef DHD_DEBUG
++	uint8 *nvram_ularray;
++#endif /* DHD_DEBUG */
++
++	/* Even if there are no vars are to be written, we still need to set the ramsize. */
++	varsize = bus->varsz ? ROUNDUP(bus->varsz, 4) : 0;
++	varaddr = (bus->ramsize - 4) - varsize;
++
++	// terence 20150412: fix for nvram failed to download
++	if (bus->dhd->conf->chip == BCM43340_CHIP_ID ||
++			bus->dhd->conf->chip == BCM43341_CHIP_ID) {
++		varsize = varsize ? ROUNDUP(varsize, 64) : 0;
++		varaddr = (bus->ramsize - 64) - varsize;
++	}
++
++	varaddr += bus->dongle_ram_base;
++
++	if (bus->vars) {
++		if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev == 7)) {
++			if (((varaddr & 0x3C) == 0x3C) && (varsize > 4)) {
++				DHD_ERROR(("PR85623WAR in place\n"));
++				varsize += 4;
++				varaddr -= 4;
++			}
++		}
++
++		vbuffer = (uint8 *)MALLOC(bus->dhd->osh, varsize);
++		if (!vbuffer)
++			return BCME_NOMEM;
++
++		bzero(vbuffer, varsize);
++		bcopy(bus->vars, vbuffer, bus->varsz);
++
++		/* Write the vars list */
++		bcmerror = dhdsdio_membytes(bus, TRUE, varaddr, vbuffer, varsize);
++		if (bcmerror) {
++			DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
++				__FUNCTION__, bcmerror, varsize, varaddr));
++			return bcmerror;
++		}
++
++#ifdef DHD_DEBUG
++		/* Verify NVRAM bytes */
++		DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
++		nvram_ularray = (uint8*)MALLOC(bus->dhd->osh, varsize);
++		if (!nvram_ularray) {
++			MFREE(bus->dhd->osh, vbuffer, varsize);
++			return BCME_NOMEM;
++		}
++
++		/* Upload image to verify downloaded contents. */
++		memset(nvram_ularray, 0xaa, varsize);
++
++		/* Read the vars list to temp buffer for comparison */
++		bcmerror = dhdsdio_membytes(bus, FALSE, varaddr, nvram_ularray, varsize);
++		if (bcmerror) {
++				DHD_ERROR(("%s: error %d on reading %d nvram bytes at 0x%08x\n",
++					__FUNCTION__, bcmerror, varsize, varaddr));
++		}
++		/* Compare the org NVRAM with the one read from RAM */
++		if (memcmp(vbuffer, nvram_ularray, varsize)) {
++			DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n", __FUNCTION__));
++		} else
++			DHD_ERROR(("%s: Download, Upload and compare of NVRAM succeeded.\n",
++			__FUNCTION__));
++
++		MFREE(bus->dhd->osh, nvram_ularray, varsize);
++#endif /* DHD_DEBUG */
++
++		MFREE(bus->dhd->osh, vbuffer, varsize);
++	}
++
++	phys_size = REMAP_ENAB(bus) ? bus->ramsize : bus->orig_ramsize;
++
++	phys_size += bus->dongle_ram_base;
++
++	/* adjust to the user specified RAM */
++	DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
++		phys_size, bus->ramsize));
++	DHD_INFO(("Vars are at %d, orig varsize is %d\n",
++		varaddr, varsize));
++	varsize = ((phys_size - 4) - varaddr);
++
++	/*
++	 * Determine the length token:
++	 * Varsize, converted to words, in lower 16-bits, checksum in upper 16-bits.
++	 */
++	if (bcmerror) {
++		varsizew = 0;
++	} else {
++		varsizew = varsize / 4;
++		varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
++		varsizew = htol32(varsizew);
++	}
++
++	DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize, varsizew));
++
++	/* Write the length token to the last word */
++	bcmerror = dhdsdio_membytes(bus, TRUE, (phys_size - 4),
++		(uint8*)&varsizew, 4);
++
++	return bcmerror;
++}
++
++static int
++dhdsdio_download_state(dhd_bus_t *bus, bool enter)
++{
++	uint retries;
++	int bcmerror = 0;
++	int foundcr4 = 0;
++
++	if (!bus->sih)
++		return BCME_ERROR;
++	/* To enter download state, disable ARM and reset SOCRAM.
++	 * To exit download state, simply reset ARM (default is RAM boot).
++	 */
++	if (enter) {
++		bus->alp_only = TRUE;
++
++		if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
++		    !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
++			if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
++				foundcr4 = 1;
++			} else {
++				DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++		}
++
++		if (!foundcr4) {
++			si_core_disable(bus->sih, 0);
++			if (bcmsdh_regfail(bus->sdh)) {
++				bcmerror = BCME_SDIO_ERROR;
++				goto fail;
++			}
++
++			if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++
++			si_core_reset(bus->sih, 0, 0);
++			if (bcmsdh_regfail(bus->sdh)) {
++				DHD_ERROR(("%s: Failure trying reset SOCRAM core?\n",
++				           __FUNCTION__));
++				bcmerror = BCME_SDIO_ERROR;
++				goto fail;
++			}
++
++			/* Disable remap for download */
++			if (REMAP_ENAB(bus) && si_socdevram_remap_isenb(bus->sih))
++				dhdsdio_devram_remap(bus, FALSE);
++
++			if (CHIPID(bus->sih->chip) == BCM43430_CHIP_ID ||
++				CHIPID(bus->sih->chip) == BCM43018_CHIP_ID) {
++				/* Disabling Remap for SRAM_3 */
++				si_socram_set_bankpda(bus->sih, 0x3, 0x0);
++			}
++
++			/* Clear the top bit of memory */
++			if (bus->ramsize) {
++				uint32 zeros = 0;
++				if (dhdsdio_membytes(bus, TRUE, bus->ramsize - 4,
++				                     (uint8*)&zeros, 4) < 0) {
++					bcmerror = BCME_SDIO_ERROR;
++					goto fail;
++				}
++			}
++		} else {
++			/* For CR4,
++			 * Halt ARM
++			 * Remove ARM reset
++			 * Read RAM base address [0x18_0000]
++			 * [next] Download firmware
++			 * [done at else] Populate the reset vector
++			 * [done at else] Remove ARM halt
++			*/
++			/* Halt ARM & remove reset */
++			si_core_reset(bus->sih, SICF_CPUHALT, SICF_CPUHALT);
++		}
++	} else {
++		if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
++			if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++
++			if (!si_iscoreup(bus->sih)) {
++				DHD_ERROR(("%s: SOCRAM core is down after reset?\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++
++			if ((bcmerror = dhdsdio_write_vars(bus))) {
++				DHD_ERROR(("%s: could not write vars to RAM\n", __FUNCTION__));
++				goto fail;
++			}
++
++			/* Enable remap before ARM reset but after vars.
++			 * No backplane access in remap mode
++			 */
++			if (REMAP_ENAB(bus) && !si_socdevram_remap_isenb(bus->sih))
++				dhdsdio_devram_remap(bus, TRUE);
++
++			if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
++			    !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
++				DHD_ERROR(("%s: Can't change back to SDIO core?\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++			W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
++
++
++			if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
++			    !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++		} else {
++			/* cr4 has no socram, but tcm's */
++			/* write vars */
++			if ((bcmerror = dhdsdio_write_vars(bus))) {
++				DHD_ERROR(("%s: could not write vars to RAM\n", __FUNCTION__));
++				goto fail;
++			}
++
++			if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
++			    !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
++				DHD_ERROR(("%s: Can't change back to SDIO core?\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++			W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
++
++			/* switch back to arm core again */
++			if (!(si_setcore(bus->sih, ARMCR4_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find ARM CR4 core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++			/* write address 0 with reset instruction */
++			bcmerror = dhdsdio_membytes(bus, TRUE, 0,
++				(uint8 *)&bus->resetinstr, sizeof(bus->resetinstr));
++
++			if (bcmerror == BCME_OK) {
++				uint32 tmp;
++
++				/* verify write */
++				bcmerror = dhdsdio_membytes(bus, FALSE, 0,
++				                            (uint8 *)&tmp, sizeof(tmp));
++
++				if (bcmerror == BCME_OK && tmp != bus->resetinstr) {
++					DHD_ERROR(("%s: Failed to write 0x%08x to addr 0\n",
++					          __FUNCTION__, bus->resetinstr));
++					DHD_ERROR(("%s: contents of addr 0 is 0x%08x\n",
++					          __FUNCTION__, tmp));
++					bcmerror = BCME_SDIO_ERROR;
++					goto fail;
++				}
++			}
++
++			/* now remove reset and halt and continue to run CR4 */
++		}
++
++		si_core_reset(bus->sih, 0, 0);
++		if (bcmsdh_regfail(bus->sdh)) {
++			DHD_ERROR(("%s: Failure trying to reset ARM core?\n", __FUNCTION__));
++			bcmerror = BCME_SDIO_ERROR;
++			goto fail;
++		}
++
++		/* Allow HT Clock now that the ARM is running. */
++		bus->alp_only = FALSE;
++
++		bus->dhd->busstate = DHD_BUS_LOAD;
++	}
++
++fail:
++	/* Always return to SDIOD core */
++	if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0))
++		si_setcore(bus->sih, SDIOD_CORE_ID, 0);
++
++	return bcmerror;
++}
++
++int
++dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
++                 void *params, int plen, void *arg, int len, bool set)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	const bcm_iovar_t *vi = NULL;
++	int bcmerror = 0;
++	int val_size;
++	uint32 actionid;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	ASSERT(name);
++	ASSERT(len >= 0);
++
++	/* Get MUST have return space */
++	ASSERT(set || (arg && len));
++
++	/* Set does NOT take qualifiers */
++	ASSERT(!set || (!params && !plen));
++
++	/* Look up var locally; if not found pass to host driver */
++	if ((vi = bcm_iovar_lookup(dhdsdio_iovars, name)) == NULL) {
++		dhd_os_sdlock(bus->dhd);
++
++		BUS_WAKE(bus);
++
++		/* Turn on clock in case SD command needs backplane */
++		dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++		bcmerror = bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len, set);
++
++		/* Check for bus configuration changes of interest */
++
++		/* If it was divisor change, read the new one */
++		if (set && strcmp(name, "sd_divisor") == 0) {
++			if (bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
++			                    &bus->sd_divisor, sizeof(int32), FALSE) != BCME_OK) {
++				bus->sd_divisor = -1;
++				DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, name));
++			} else {
++				DHD_INFO(("%s: noted %s update, value now %d\n",
++				          __FUNCTION__, name, bus->sd_divisor));
++			}
++		}
++		/* If it was a mode change, read the new one */
++		if (set && strcmp(name, "sd_mode") == 0) {
++			if (bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
++			                    &bus->sd_mode, sizeof(int32), FALSE) != BCME_OK) {
++				bus->sd_mode = -1;
++				DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, name));
++			} else {
++				DHD_INFO(("%s: noted %s update, value now %d\n",
++				          __FUNCTION__, name, bus->sd_mode));
++			}
++		}
++		/* Similar check for blocksize change */
++		if (set && strcmp(name, "sd_blocksize") == 0) {
++			int32 fnum = 2;
++			if (bcmsdh_iovar_op(bus->sdh, "sd_blocksize", &fnum, sizeof(int32),
++			                    &bus->blocksize, sizeof(int32), FALSE) != BCME_OK) {
++				bus->blocksize = 0;
++				DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_blocksize"));
++			} else {
++				DHD_INFO(("%s: noted %s update, value now %d\n",
++				          __FUNCTION__, "sd_blocksize", bus->blocksize));
++
++				dhdsdio_tune_fifoparam(bus);
++			}
++		}
++		bus->roundup = MIN(max_roundup, bus->blocksize);
++
++		if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched &&
++			NO_OTHER_ACTIVE_BUS_USER(bus)) {
++			bus->activity = FALSE;
++			dhdsdio_bussleep(bus, TRUE);
++			dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++		}
++
++		dhd_os_sdunlock(bus->dhd);
++		goto exit;
++	}
++
++	DHD_CTL(("%s: %s %s, len %d plen %d\n", __FUNCTION__,
++	         name, (set ? "set" : "get"), len, plen));
++
++	/* set up 'params' pointer in case this is a set command so that
++	 * the convenience int and bool code can be common to set and get
++	 */
++	if (params == NULL) {
++		params = arg;
++		plen = len;
++	}
++
++	if (vi->type == IOVT_VOID)
++		val_size = 0;
++	else if (vi->type == IOVT_BUFFER)
++		val_size = len;
++	else
++		/* all other types are integer sized */
++		val_size = sizeof(int);
++
++	actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
++	bcmerror = dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len, val_size);
++
++exit:
++	return bcmerror;
++}
++
++void
++dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
++{
++	osl_t *osh;
++	uint32 local_hostintmask;
++	uint8 saveclk;
++	uint retries;
++	int err;
++	bool wlfc_enabled = FALSE;
++	unsigned long flags;
++
++	if (!bus->dhd)
++		return;
++
++	osh = bus->dhd->osh;
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	bcmsdh_waitlockfree(bus->sdh);
++
++	if (enforce_mutex)
++		dhd_os_sdlock(bus->dhd);
++
++	if ((bus->dhd->busstate == DHD_BUS_DOWN) || bus->dhd->hang_was_sent) {
++		/* if Firmware already hangs disbale any interrupt */
++		bus->dhd->busstate = DHD_BUS_DOWN;
++		bus->hostintmask = 0;
++		bcmsdh_intr_disable(bus->sdh);
++	} else {
++
++		BUS_WAKE(bus);
++
++		if (KSO_ENAB(bus)) {
++
++		/* Enable clock for device interrupts */
++		dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++		/* Disable and clear interrupts at the chip level also */
++		W_SDREG(0, &bus->regs->hostintmask, retries);
++		local_hostintmask = bus->hostintmask;
++		bus->hostintmask = 0;
++
++		/* Force clocks on backplane to be sure F2 interrupt propagates */
++		saveclk = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
++		if (!err) {
++			bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
++			                 (saveclk | SBSDIO_FORCE_HT), &err);
++		}
++		if (err) {
++			DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
++			            __FUNCTION__, err));
++		}
++
++		/* Turn off the bus (F2), free any pending packets */
++		DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__));
++		bcmsdh_intr_disable(bus->sdh);
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1, NULL);
++
++		/* Clear any pending interrupts now that F2 is disabled */
++		W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
++		}
++
++		/* Turn off the backplane clock (only) */
++		dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++
++		/* Change our idea of bus state */
++		DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
++		bus->dhd->busstate = DHD_BUS_DOWN;
++		DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
++	}
++
++#ifdef PROP_TXSTATUS
++	wlfc_enabled = (dhd_wlfc_cleanup_txq(bus->dhd, NULL, 0) != WLFC_UNSUPPORTED);
++#endif
++	if (!wlfc_enabled) {
++#ifdef DHDTCPACK_SUPPRESS
++		/* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt,
++		 * when there is a newly coming packet from network stack.
++		 */
++		dhd_tcpack_info_tbl_clean(bus->dhd);
++#endif /* DHDTCPACK_SUPPRESS */
++		dhd_os_sdlock_txq(bus->dhd);
++		/* Clear the data packet queues */
++		pktq_flush(osh, &bus->txq, TRUE);
++		dhd_os_sdunlock_txq(bus->dhd);
++	}
++
++	/* Clear any held glomming stuff */
++	if (bus->glomd)
++		PKTFREE(osh, bus->glomd, FALSE);
++
++	if (bus->glom)
++		PKTFREE(osh, bus->glom, FALSE);
++
++	bus->glom = bus->glomd = NULL;
++
++	/* Clear rx control and wake any waiters */
++	bus->rxlen = 0;
++	dhd_os_ioctl_resp_wake(bus->dhd);
++
++	/* Reset some F2 state stuff */
++	bus->rxskip = FALSE;
++	bus->tx_seq = bus->rx_seq = 0;
++
++	bus->tx_max = 4;
++
++	if (enforce_mutex)
++		dhd_os_sdunlock(bus->dhd);
++}
++
++#if defined(BCMSDIOH_TXGLOM) && defined(BCMSDIOH_STD)
++extern uint sd_txglom;
++#endif
++void
++dhd_txglom_enable(dhd_pub_t *dhdp, bool enable)
++{
++	/* can't enable host txglom by default, some platforms have no
++	 * (or crappy) ADMA support and txglom will cause kernel assertions (e.g.
++	 * panda board)
++	 */
++	dhd_bus_t *bus = dhdp->bus;
++#ifdef BCMSDIOH_TXGLOM
++	uint32 rxglom;
++	int32 ret;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++#ifdef BCMSDIOH_STD
++	if (enable)
++		enable = sd_txglom;
++#endif /* BCMSDIOH_STD */
++
++	if (enable) {
++		rxglom = 1;
++		ret = dhd_iovar(dhdp, 0, "bus:rxglom", (char *)&rxglom, sizeof(rxglom), NULL, 0,
++				TRUE);
++		if (ret >= 0)
++			bus->txglom_enable = TRUE;
++		else {
++#ifdef BCMSDIOH_STD
++			sd_txglom = 0;
++#endif /* BCMSDIOH_STD */
++			bus->txglom_enable = FALSE;
++		}
++	} else
++#endif /* BCMSDIOH_TXGLOM */
++		bus->txglom_enable = FALSE;
++	printf("%s: enable %d\n",  __FUNCTION__, bus->txglom_enable);
++	dhd_conf_set_txglom_params(bus->dhd, bus->txglom_enable);
++	bcmsdh_set_mode(bus->sdh, bus->dhd->conf->txglom_mode);
++}
++
++int
++dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	dhd_timeout_t tmo;
++	uint retries = 0;
++	uint8 ready, enable;
++	int err, ret = 0;
++	uint8 saveclk;
++#if defined(SDIO_ISR_THREAD)
++	int intr_extn;
++#endif
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	ASSERT(bus->dhd);
++	if (!bus->dhd)
++		return 0;
++
++	if (enforce_mutex)
++		dhd_os_sdlock(bus->dhd);
++
++	if (bus->sih->chip == BCM43362_CHIP_ID) {
++		printf("%s: delay 100ms for BCM43362\n", __FUNCTION__);
++		OSL_DELAY(100000); // terence 20131209: delay for 43362
++	}
++
++	/* Make sure backplane clock is on, needed to generate F2 interrupt */
++	dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++	if (bus->clkstate != CLK_AVAIL) {
++		DHD_ERROR(("%s: clock state is wrong. state = %d\n", __FUNCTION__, bus->clkstate));
++		ret = -1;
++		goto exit;
++	}
++
++	/* Force clocks on backplane to be sure F2 interrupt propagates */
++	saveclk = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
++
++	if (!err) {
++		if (bus->sih->chip == BCM43012_CHIP_ID) {
++			bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
++				(saveclk | SBSDIO_HT_AVAIL_REQ), &err);
++		} else {
++			bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
++				(saveclk | SBSDIO_FORCE_HT), &err);
++		}
++	}
++
++	if (err) {
++		DHD_ERROR(("%s: Failed to force clock for F2: err %d\n", __FUNCTION__, err));
++		ret = -1;
++		goto exit;
++	}
++
++	/* Enable function 2 (frame transfers) */
++	W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
++	        &bus->regs->tosbmailboxdata, retries);
++	enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
++
++	bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
++
++	/* Give the dongle some time to do its thing and set IOR2 */
++	dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
++
++	ready = 0;
++	while (ready != enable && !dhd_timeout_expired(&tmo))
++	        ready = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY, NULL);
++
++	DHD_ERROR(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
++	          __FUNCTION__, enable, ready, tmo.elapsed));
++
++#if defined(SDIO_ISR_THREAD)
++	if (dhdp->conf->intr_extn) {
++		intr_extn = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_INTR_EXTN, NULL);
++		if (intr_extn & 0x1) {
++			intr_extn |= 0x2;
++			bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_INTR_EXTN, intr_extn, NULL);
++		}
++	}
++#endif
++
++	/* If F2 successfully enabled, set core and enable interrupts */
++	if (ready == enable) {
++		/* Make sure we're talking to the core. */
++		if (!(bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0)))
++			bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
++		ASSERT(bus->regs != NULL);
++
++		/* Set up the interrupt mask and enable interrupts */
++		bus->hostintmask = HOSTINTMASK;
++		/* corerev 4 could use the newer interrupt logic to detect the frames */
++		if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev == 4) &&
++			(bus->rxint_mode != SDIO_DEVICE_HMB_RXINT)) {
++			bus->hostintmask &= ~I_HMB_FRAME_IND;
++			bus->hostintmask |= I_XMTDATA_AVAIL;
++		}
++		W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
++
++		if (bus->sih->buscorerev < 15) {
++			bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
++				(uint8)watermark, &err);
++		}
++
++		/* Set bus state according to enable result */
++		dhdp->busstate = DHD_BUS_DATA;
++
++		/* Need to set fn2 block size to match fn1 block size.
++		 * Requests to fn2 go thru fn1. *
++		 * faltwig has this code contitioned with #if !BCMSPI_ANDROID.
++		 * It would be cleaner to use the ->sdh->block_sz[fno] instead of
++		 * 64, but this layer has no access to sdh types.
++		 */
++
++		/* bcmsdh_intr_unmask(bus->sdh); */
++
++		bus->intdis = FALSE;
++		if (bus->intr) {
++			DHD_INTR(("%s: enable SDIO device interrupts\n", __FUNCTION__));
++			bcmsdh_intr_enable(bus->sdh);
++		} else {
++			DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__));
++			bcmsdh_intr_disable(bus->sdh);
++		}
++
++	}
++
++
++	else {
++		/* Disable F2 again */
++		enable = SDIO_FUNC_ENABLE_1;
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
++	}
++
++	if (dhdsdio_sr_cap(bus)) {
++		dhdsdio_sr_init(bus);
++		/* Masking the chip active interrupt  permanantly */
++		bus->hostintmask &= ~I_CHIPACTIVE;
++		W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
++		DHD_INFO(("%s: disable I_CHIPACTIVE in hostintmask[0x%08x]\n",
++		__FUNCTION__, bus->hostintmask));
++	} else {
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
++			SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
++	}
++
++	/* If we didn't come up, turn off backplane clock */
++	if (dhdp->busstate != DHD_BUS_DATA)
++		dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++
++exit:
++	if (enforce_mutex)
++		dhd_os_sdunlock(bus->dhd);
++
++	return ret;
++}
++
++static void
++dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
++{
++	bcmsdh_info_t *sdh = bus->sdh;
++	sdpcmd_regs_t *regs = bus->regs;
++	uint retries = 0;
++	uint16 lastrbc;
++	uint8 hi, lo;
++	int err;
++
++	DHD_ERROR(("%s: %sterminate frame%s\n", __FUNCTION__,
++	           (abort ? "abort command, " : ""), (rtx ? ", send NAK" : "")));
++
++	if (!KSO_ENAB(bus)) {
++		DHD_ERROR(("%s: Device asleep\n", __FUNCTION__));
++		return;
++	}
++
++	if (abort) {
++		bcmsdh_abort(sdh, SDIO_FUNC_2);
++	}
++
++	bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM, &err);
++	if (err) {
++		DHD_ERROR(("%s: SBSDIO_FUNC1_FRAMECTRL cmd err\n", __FUNCTION__));
++		goto fail;
++	}
++	bus->f1regdata++;
++
++	/* Wait until the packet has been flushed (device/FIFO stable) */
++	for (lastrbc = retries = 0xffff; retries > 0; retries--) {
++		hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI, NULL);
++		lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO, &err);
++		if (err) {
++			DHD_ERROR(("%s: SBSDIO_FUNC1_RFAMEBCLO cmd err\n", __FUNCTION__));
++			goto fail;
++		}
++
++		bus->f1regdata += 2;
++
++		if ((hi == 0) && (lo == 0))
++			break;
++
++		if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
++			DHD_ERROR(("%s: count growing: last 0x%04x now 0x%04x\n",
++			           __FUNCTION__, lastrbc, ((hi << 8) + lo)));
++		}
++		lastrbc = (hi << 8) + lo;
++	}
++
++	if (!retries) {
++		DHD_ERROR(("%s: count never zeroed: last 0x%04x\n", __FUNCTION__, lastrbc));
++	} else {
++		DHD_INFO(("%s: flush took %d iterations\n", __FUNCTION__, (0xffff - retries)));
++	}
++
++	if (rtx) {
++		bus->rxrtx++;
++		W_SDREG(SMB_NAK, &regs->tosbmailbox, retries);
++		bus->f1regdata++;
++		if (retries <= retry_limit) {
++			bus->rxskip = TRUE;
++		}
++	}
++
++	/* Clear partial in any case */
++	bus->nextlen = 0;
++
++fail:
++	/* If we can't reach the device, signal failure */
++	if (err || bcmsdh_regfail(sdh))
++		bus->dhd->busstate = DHD_BUS_DOWN;
++}
++
++static void
++dhdsdio_read_control(dhd_bus_t *bus, uint8 *hdr, uint len, uint doff)
++{
++	bcmsdh_info_t *sdh = bus->sdh;
++	uint rdlen, pad;
++
++	int sdret;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	/* Control data already received in aligned rxctl */
++	if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
++		goto gotpkt;
++
++	ASSERT(bus->rxbuf);
++	/* Set rxctl for frame (w/optional alignment) */
++	bus->rxctl = bus->rxbuf;
++	if (dhd_alignctl) {
++		bus->rxctl += firstread;
++		if ((pad = ((uintptr)bus->rxctl % DHD_SDALIGN)))
++			bus->rxctl += (DHD_SDALIGN - pad);
++		bus->rxctl -= firstread;
++	}
++	ASSERT(bus->rxctl >= bus->rxbuf);
++
++	/* Copy the already-read portion over */
++	bcopy(hdr, bus->rxctl, firstread);
++	if (len <= firstread)
++		goto gotpkt;
++
++	/* Copy the full data pkt in gSPI case and process ioctl. */
++	if (bus->bus == SPI_BUS) {
++		bcopy(hdr, bus->rxctl, len);
++		goto gotpkt;
++	}
++
++	/* Raise rdlen to next SDIO block to avoid tail command */
++	rdlen = len - firstread;
++	if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
++		pad = bus->blocksize - (rdlen % bus->blocksize);
++		if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
++		    ((len + pad) < bus->dhd->maxctl))
++			rdlen += pad;
++	} else if (rdlen % DHD_SDALIGN) {
++		rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
++	}
++
++	/* Satisfy length-alignment requirements */
++	if (forcealign && (rdlen & (ALIGNMENT - 1)))
++		rdlen = ROUNDUP(rdlen, ALIGNMENT);
++
++	/* Drop if the read is too big or it exceeds our maximum */
++	if ((rdlen + firstread) > bus->dhd->maxctl) {
++		DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
++		           __FUNCTION__, rdlen, bus->dhd->maxctl));
++		bus->dhd->rx_errors++;
++		dhdsdio_rxfail(bus, FALSE, FALSE);
++		goto done;
++	}
++
++	if ((len - doff) > bus->dhd->maxctl) {
++		DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
++		           __FUNCTION__, len, (len - doff), bus->dhd->maxctl));
++		bus->dhd->rx_errors++; bus->rx_toolong++;
++		dhdsdio_rxfail(bus, FALSE, FALSE);
++		goto done;
++	}
++
++
++	/* Read remainder of frame body into the rxctl buffer */
++	sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
++	                            (bus->rxctl + firstread), rdlen, NULL, NULL, NULL);
++	bus->f2rxdata++;
++	ASSERT(sdret != BCME_PENDING);
++
++	/* Control frame failures need retransmission */
++	if (sdret < 0) {
++		DHD_ERROR(("%s: read %d control bytes failed: %d\n", __FUNCTION__, rdlen, sdret));
++		bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
++		dhdsdio_rxfail(bus, TRUE, TRUE);
++		goto done;
++	}
++
++gotpkt:
++
++#ifdef DHD_DEBUG
++	if (DHD_BYTES_ON() && DHD_CTL_ON()) {
++		prhex("RxCtrl", bus->rxctl, len);
++	}
++#endif
++
++	/* Point to valid data and indicate its length */
++	bus->rxctl += doff;
++	bus->rxlen = len - doff;
++
++done:
++	/* Awake any waiters */
++	dhd_os_ioctl_resp_wake(bus->dhd);
++}
++int
++dhd_process_pkt_reorder_info(dhd_pub_t *dhd, uchar *reorder_info_buf, uint reorder_info_len,
++	void **pkt, uint32 *pkt_count);
++
++static uint8
++dhdsdio_rxglom(dhd_bus_t *bus, uint8 rxseq)
++{
++	uint16 dlen, totlen;
++	uint8 *dptr, num = 0;
++
++	uint16 sublen, check;
++	void *pfirst, *plast, *pnext;
++	void * list_tail[DHD_MAX_IFS] = { NULL };
++	void * list_head[DHD_MAX_IFS] = { NULL };
++	uint8 idx;
++	osl_t *osh = bus->dhd->osh;
++
++	int errcode;
++	uint8 chan, seq, doff, sfdoff;
++	uint8 txmax;
++	uchar reorder_info_buf[WLHOST_REORDERDATA_TOTLEN];
++	uint reorder_info_len;
++
++	int ifidx = 0;
++	bool usechain = bus->use_rxchain;
++
++	/* If packets, issue read(s) and send up packet chain */
++	/* Return sequence numbers consumed? */
++
++	DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd, bus->glom));
++
++	/* If there's a descriptor, generate the packet chain */
++	if (bus->glomd) {
++		dhd_os_sdlock_rxq(bus->dhd);
++
++		pfirst = plast = pnext = NULL;
++		dlen = (uint16)PKTLEN(osh, bus->glomd);
++		dptr = PKTDATA(osh, bus->glomd);
++		if (!dlen || (dlen & 1)) {
++			DHD_ERROR(("%s: bad glomd len (%d), ignore descriptor\n",
++			           __FUNCTION__, dlen));
++			dlen = 0;
++		}
++
++		for (totlen = num = 0; dlen; num++) {
++			/* Get (and move past) next length */
++			sublen = ltoh16_ua(dptr);
++			dlen -= sizeof(uint16);
++			dptr += sizeof(uint16);
++			if ((sublen < SDPCM_HDRLEN) ||
++			    ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
++				DHD_ERROR(("%s: descriptor len %d bad: %d\n",
++				           __FUNCTION__, num, sublen));
++				pnext = NULL;
++				break;
++			}
++			if (sublen % DHD_SDALIGN) {
++				DHD_ERROR(("%s: sublen %d not a multiple of %d\n",
++				           __FUNCTION__, sublen, DHD_SDALIGN));
++				usechain = FALSE;
++			}
++			totlen += sublen;
++
++			/* For last frame, adjust read len so total is a block multiple */
++			if (!dlen) {
++				sublen += (ROUNDUP(totlen, bus->blocksize) - totlen);
++				totlen = ROUNDUP(totlen, bus->blocksize);
++			}
++
++			/* Allocate/chain packet for next subframe */
++			if ((pnext = PKTGET(osh, sublen + DHD_SDALIGN, FALSE)) == NULL) {
++				DHD_ERROR(("%s: PKTGET failed, num %d len %d\n",
++				           __FUNCTION__, num, sublen));
++				break;
++			}
++			ASSERT(!PKTLINK(pnext));
++			if (!pfirst) {
++				ASSERT(!plast);
++				pfirst = plast = pnext;
++			} else {
++				ASSERT(plast);
++				PKTSETNEXT(osh, plast, pnext);
++				plast = pnext;
++			}
++
++			/* Adhere to start alignment requirements */
++			PKTALIGN(osh, pnext, sublen, DHD_SDALIGN);
++		}
++
++		/* If all allocations succeeded, save packet chain in bus structure */
++		if (pnext) {
++			DHD_GLOM(("%s: allocated %d-byte packet chain for %d subframes\n",
++			          __FUNCTION__, totlen, num));
++			if (DHD_GLOM_ON() && bus->nextlen) {
++				if (totlen != bus->nextlen) {
++					DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d "
++					          "rxseq %d\n", __FUNCTION__, bus->nextlen,
++					          totlen, rxseq));
++				}
++			}
++			bus->glom = pfirst;
++			pfirst = pnext = NULL;
++		} else {
++			if (pfirst)
++				PKTFREE(osh, pfirst, FALSE);
++			bus->glom = NULL;
++			num = 0;
++		}
++
++		/* Done with descriptor packet */
++		PKTFREE(osh, bus->glomd, FALSE);
++		bus->glomd = NULL;
++		bus->nextlen = 0;
++
++		dhd_os_sdunlock_rxq(bus->dhd);
++	}
++
++	/* Ok -- either we just generated a packet chain, or had one from before */
++	if (bus->glom) {
++		if (DHD_GLOM_ON()) {
++			DHD_GLOM(("%s: attempt superframe read, packet chain:\n", __FUNCTION__));
++			for (pnext = bus->glom; pnext; pnext = PKTNEXT(osh, pnext)) {
++				DHD_GLOM(("    %p: %p len 0x%04x (%d)\n",
++				          pnext, (uint8*)PKTDATA(osh, pnext),
++				          PKTLEN(osh, pnext), PKTLEN(osh, pnext)));
++			}
++		}
++
++		pfirst = bus->glom;
++		dlen = (uint16)pkttotlen(osh, pfirst);
++
++		/* Do an SDIO read for the superframe.  Configurable iovar to
++		 * read directly into the chained packet, or allocate a large
++		 * packet and and copy into the chain.
++		 */
++		if (usechain) {
++			errcode = dhd_bcmsdh_recv_buf(bus,
++			                              bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
++			                              F2SYNC, (uint8*)PKTDATA(osh, pfirst),
++			                              dlen, pfirst, NULL, NULL);
++		} else if (bus->dataptr) {
++			errcode = dhd_bcmsdh_recv_buf(bus,
++			                              bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
++			                              F2SYNC, bus->dataptr,
++			                              dlen, NULL, NULL, NULL);
++			sublen = (uint16)pktfrombuf(osh, pfirst, 0, dlen, bus->dataptr);
++			if (sublen != dlen) {
++				DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
++				           __FUNCTION__, dlen, sublen));
++				errcode = -1;
++			}
++			pnext = NULL;
++			BCM_REFERENCE(pnext);
++		} else {
++			DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n", dlen));
++			errcode = -1;
++		}
++		bus->f2rxdata++;
++		ASSERT(errcode != BCME_PENDING);
++
++		/* On failure, kill the superframe, allow a couple retries */
++		if (errcode < 0) {
++			DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
++			           __FUNCTION__, dlen, errcode));
++			bus->dhd->rx_errors++;
++
++			if (bus->glomerr++ < 3) {
++				dhdsdio_rxfail(bus, TRUE, TRUE);
++			} else {
++				bus->glomerr = 0;
++				dhdsdio_rxfail(bus, TRUE, FALSE);
++				dhd_os_sdlock_rxq(bus->dhd);
++				PKTFREE(osh, bus->glom, FALSE);
++				dhd_os_sdunlock_rxq(bus->dhd);
++				bus->rxglomfail++;
++				bus->glom = NULL;
++			}
++			return 0;
++		}
++
++#ifdef DHD_DEBUG
++		if (DHD_GLOM_ON()) {
++			prhex("SUPERFRAME", PKTDATA(osh, pfirst),
++			      MIN(PKTLEN(osh, pfirst), 48));
++		}
++#endif
++
++
++		/* Validate the superframe header */
++		dptr = (uint8 *)PKTDATA(osh, pfirst);
++		sublen = ltoh16_ua(dptr);
++		check = ltoh16_ua(dptr + sizeof(uint16));
++
++		chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
++		seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
++		bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
++		if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
++			DHD_INFO(("%s: got frame w/nextlen too large (%d) seq %d\n",
++			          __FUNCTION__, bus->nextlen, seq));
++			bus->nextlen = 0;
++		}
++		doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
++		txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
++
++		errcode = 0;
++		if ((uint16)~(sublen^check)) {
++			DHD_ERROR(("%s (superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
++			           __FUNCTION__, sublen, check));
++			errcode = -1;
++		} else if (ROUNDUP(sublen, bus->blocksize) != dlen) {
++			DHD_ERROR(("%s (superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
++			           __FUNCTION__, sublen, ROUNDUP(sublen, bus->blocksize), dlen));
++			errcode = -1;
++		} else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) != SDPCM_GLOM_CHANNEL) {
++			DHD_ERROR(("%s (superframe): bad channel %d\n", __FUNCTION__,
++			           SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN])));
++			errcode = -1;
++		} else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
++			DHD_ERROR(("%s (superframe): got second descriptor?\n", __FUNCTION__));
++			errcode = -1;
++		} else if ((doff < SDPCM_HDRLEN) ||
++		           (doff > (PKTLEN(osh, pfirst) - SDPCM_HDRLEN))) {
++			DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d pkt %d min %d\n",
++				__FUNCTION__, doff, sublen, PKTLEN(osh, pfirst),
++				SDPCM_HDRLEN));
++			errcode = -1;
++		}
++
++		/* Check sequence number of superframe SW header */
++		if (rxseq != seq) {
++			DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
++			          __FUNCTION__, seq, rxseq));
++			bus->rx_badseq++;
++			rxseq = seq;
++		}
++
++		/* Check window for sanity */
++		if ((uint8)(txmax - bus->tx_seq) > 0x70) {
++			DHD_INFO(("%s: got unlikely tx max %d with tx_seq %d\n",
++			           __FUNCTION__, txmax, bus->tx_seq));
++			txmax = bus->tx_max;
++		}
++		bus->tx_max = txmax;
++
++		/* Remove superframe header, remember offset */
++		PKTPULL(osh, pfirst, doff);
++		sfdoff = doff;
++
++		/* Validate all the subframe headers */
++		for (num = 0, pnext = pfirst; pnext && !errcode;
++		     num++, pnext = PKTNEXT(osh, pnext)) {
++			dptr = (uint8 *)PKTDATA(osh, pnext);
++			dlen = (uint16)PKTLEN(osh, pnext);
++			sublen = ltoh16_ua(dptr);
++			check = ltoh16_ua(dptr + sizeof(uint16));
++			chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
++			doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
++#ifdef DHD_DEBUG
++			if (DHD_GLOM_ON()) {
++				prhex("subframe", dptr, 32);
++			}
++#endif
++
++			if ((uint16)~(sublen^check)) {
++				DHD_ERROR(("%s (subframe %d): HW hdr error: "
++				           "len/check 0x%04x/0x%04x\n",
++				           __FUNCTION__, num, sublen, check));
++				errcode = -1;
++			} else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
++				DHD_ERROR(("%s (subframe %d): length mismatch: "
++				           "len 0x%04x, expect 0x%04x\n",
++				           __FUNCTION__, num, sublen, dlen));
++				errcode = -1;
++			} else if ((chan != SDPCM_DATA_CHANNEL) &&
++			           (chan != SDPCM_EVENT_CHANNEL)) {
++				DHD_ERROR(("%s (subframe %d): bad channel %d\n",
++				           __FUNCTION__, num, chan));
++				errcode = -1;
++			} else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
++				DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
++				           __FUNCTION__, num, doff, sublen, SDPCM_HDRLEN));
++				errcode = -1;
++			}
++		}
++
++		if (errcode) {
++			/* Terminate frame on error, request a couple retries */
++			if (bus->glomerr++ < 3) {
++				/* Restore superframe header space */
++				PKTPUSH(osh, pfirst, sfdoff);
++				dhdsdio_rxfail(bus, TRUE, TRUE);
++			} else {
++				bus->glomerr = 0;
++				dhdsdio_rxfail(bus, TRUE, FALSE);
++				dhd_os_sdlock_rxq(bus->dhd);
++				PKTFREE(osh, bus->glom, FALSE);
++				dhd_os_sdunlock_rxq(bus->dhd);
++				bus->rxglomfail++;
++				bus->glom = NULL;
++			}
++			bus->nextlen = 0;
++			return 0;
++		}
++
++		/* Basic SD framing looks ok - process each packet (header) */
++		bus->glom = NULL;
++		plast = NULL;
++
++		dhd_os_sdlock_rxq(bus->dhd);
++		for (num = 0; pfirst; rxseq++, pfirst = pnext) {
++			pnext = PKTNEXT(osh, pfirst);
++			PKTSETNEXT(osh, pfirst, NULL);
++
++			dptr = (uint8 *)PKTDATA(osh, pfirst);
++			sublen = ltoh16_ua(dptr);
++			chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
++			seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
++			doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
++
++			DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
++			          __FUNCTION__, num, pfirst, PKTDATA(osh, pfirst),
++			          PKTLEN(osh, pfirst), sublen, chan, seq));
++
++			ASSERT((chan == SDPCM_DATA_CHANNEL) || (chan == SDPCM_EVENT_CHANNEL));
++
++			if (rxseq != seq) {
++				DHD_GLOM(("%s: rx_seq %d, expected %d\n",
++				          __FUNCTION__, seq, rxseq));
++				bus->rx_badseq++;
++				rxseq = seq;
++			}
++
++#ifdef DHD_DEBUG
++			if (DHD_BYTES_ON() && DHD_DATA_ON()) {
++				prhex("Rx Subframe Data", dptr, dlen);
++			}
++#endif
++
++			PKTSETLEN(osh, pfirst, sublen);
++			PKTPULL(osh, pfirst, doff);
++
++			reorder_info_len = sizeof(reorder_info_buf);
++
++			if (PKTLEN(osh, pfirst) == 0) {
++				PKTFREE(bus->dhd->osh, pfirst, FALSE);
++				continue;
++			} else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst, reorder_info_buf,
++				&reorder_info_len) != 0) {
++				DHD_ERROR(("%s: rx protocol error\n", __FUNCTION__));
++				bus->dhd->rx_errors++;
++				PKTFREE(osh, pfirst, FALSE);
++				continue;
++			}
++			if (reorder_info_len) {
++				uint32 free_buf_count;
++				void *ppfirst;
++
++				ppfirst = pfirst;
++				/* Reordering info from the firmware */
++				dhd_process_pkt_reorder_info(bus->dhd, reorder_info_buf,
++					reorder_info_len, &ppfirst, &free_buf_count);
++
++				if (free_buf_count == 0) {
++					continue;
++				} else {
++					void *temp;
++
++					/*  go to the end of the chain and attach the pnext there */
++					temp = ppfirst;
++					while (PKTNEXT(osh, temp) != NULL) {
++						temp = PKTNEXT(osh, temp);
++					}
++					pfirst = temp;
++					if (list_tail[ifidx] == NULL)
++						list_head[ifidx] = ppfirst;
++					else
++						PKTSETNEXT(osh, list_tail[ifidx], ppfirst);
++					list_tail[ifidx] = pfirst;
++				}
++
++				num += (uint8)free_buf_count;
++			} else {
++				/* this packet will go up, link back into chain and count it */
++
++				if (list_tail[ifidx] == NULL) {
++					list_head[ifidx] = list_tail[ifidx] = pfirst;
++				} else {
++					PKTSETNEXT(osh, list_tail[ifidx], pfirst);
++					list_tail[ifidx] = pfirst;
++				}
++				num++;
++			}
++#ifdef DHD_DEBUG
++			if (DHD_GLOM_ON()) {
++				DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) nxt/lnk %p/%p\n",
++				          __FUNCTION__, num, pfirst,
++				          PKTDATA(osh, pfirst), PKTLEN(osh, pfirst),
++				          PKTNEXT(osh, pfirst), PKTLINK(pfirst)));
++				prhex("", (uint8 *)PKTDATA(osh, pfirst),
++				      MIN(PKTLEN(osh, pfirst), 32));
++			}
++#endif /* DHD_DEBUG */
++		}
++		dhd_os_sdunlock_rxq(bus->dhd);
++
++		for (idx = 0; idx < DHD_MAX_IFS; idx++) {
++			if (list_head[idx]) {
++				void *temp;
++				uint8 cnt = 0;
++				temp = list_head[idx];
++				do {
++					temp = PKTNEXT(osh, temp);
++					cnt++;
++				} while (temp);
++				if (cnt) {
++					dhd_os_sdunlock(bus->dhd);
++					dhd_rx_frame(bus->dhd, idx, list_head[idx], cnt, 0);
++					dhd_os_sdlock(bus->dhd);
++#if defined(SDIO_ISR_THREAD)
++					/* terence 20150615: fix for below error due to bussleep in watchdog after dhd_os_sdunlock here,
++					  * so call BUS_WAKE to wake up bus again
++					  * dhd_bcmsdh_recv_buf: Device asleep
++					  * dhdsdio_readframes: RXHEADER FAILED: -40
++					  * dhdsdio_rxfail: abort command, terminate frame, send NAK
++					*/
++					BUS_WAKE(bus);
++#endif
++				}
++			}
++		}
++		bus->rxglomframes++;
++		bus->rxglompkts += num;
++	}
++	return num;
++}
++
++
++/* Return TRUE if there may be more frames to read */
++static uint
++dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
++{
++	osl_t *osh = bus->dhd->osh;
++	bcmsdh_info_t *sdh = bus->sdh;
++
++	uint16 len, check;	/* Extracted hardware header fields */
++	uint8 chan, seq, doff;	/* Extracted software header fields */
++	uint8 fcbits;		/* Extracted fcbits from software header */
++	uint8 delta;
++
++	void *pkt;	/* Packet for event or data frames */
++	uint16 pad;	/* Number of pad bytes to read */
++	uint16 rdlen;	/* Total number of bytes to read */
++	uint8 rxseq;	/* Next sequence number to expect */
++	uint rxleft = 0;	/* Remaining number of frames allowed */
++	int sdret;	/* Return code from bcmsdh calls */
++	uint8 txmax;	/* Maximum tx sequence offered */
++	bool len_consistent; /* Result of comparing readahead len and len from hw-hdr */
++	uint8 *rxbuf;
++	int ifidx = 0;
++	uint rxcount = 0; /* Total frames read */
++	uchar reorder_info_buf[WLHOST_REORDERDATA_TOTLEN];
++	uint reorder_info_len;
++	uint pkt_count;
++
++#if defined(DHD_DEBUG) || defined(SDTEST)
++	bool sdtest = FALSE;	/* To limit message spew from test mode */
++#endif
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++	bus->readframes = TRUE;
++
++	if (!KSO_ENAB(bus)) {
++		DHD_ERROR(("%s: KSO off\n", __FUNCTION__));
++		bus->readframes = FALSE;
++		return 0;
++	}
++
++	ASSERT(maxframes);
++
++#ifdef SDTEST
++	/* Allow pktgen to override maxframes */
++	if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
++		maxframes = bus->pktgen_count;
++		sdtest = TRUE;
++	}
++#endif
++
++	/* Not finished unless we encounter no more frames indication */
++	*finished = FALSE;
++
++
++	for (rxseq = bus->rx_seq, rxleft = maxframes;
++	     !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
++	     rxseq++, rxleft--) {
++#ifdef DHDTCPACK_SUP_DBG
++		if (bus->dhd->tcpack_sup_mode != TCPACK_SUP_DELAYTX) {
++			if (bus->dotxinrx == FALSE)
++				DHD_ERROR(("%s %d: dotxinrx FALSE with tcpack_sub_mode %d\n",
++					__FUNCTION__, __LINE__, bus->dhd->tcpack_sup_mode));
++		}
++#ifdef DEBUG_COUNTER
++		else if (pktq_mlen(&bus->txq, ~bus->flowcontrol) > 0) {
++			tack_tbl.cnt[bus->dotxinrx ? 6 : 7]++;
++		}
++#endif /* DEBUG_COUNTER */
++#endif /* DHDTCPACK_SUP_DBG */
++		/* tx more to improve rx performance */
++		if (TXCTLOK(bus) && bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL)) {
++			dhdsdio_sendpendctl(bus);
++		} else if (bus->dotxinrx && (bus->clkstate == CLK_AVAIL) &&
++			!bus->fcstate && DATAOK(bus) &&
++			(pktq_mlen(&bus->txq, ~bus->flowcontrol) > bus->txinrx_thres)) {
++			dhdsdio_sendfromq(bus, dhd_txbound);
++#ifdef DHDTCPACK_SUPPRESS
++			/* In TCPACK_SUP_DELAYTX mode, do txinrx only if
++			 * 1. Any DATA packet to TX
++			 * 2. TCPACK to TCPDATA PSH packets.
++			 * in bus txq.
++			 */
++			bus->dotxinrx = (bus->dhd->tcpack_sup_mode == TCPACK_SUP_DELAYTX) ?
++				FALSE : TRUE;
++#endif
++		}
++
++		/* Handle glomming separately */
++		if (bus->glom || bus->glomd) {
++			uint8 cnt;
++			DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
++			          __FUNCTION__, bus->glomd, bus->glom));
++			cnt = dhdsdio_rxglom(bus, rxseq);
++			DHD_GLOM(("%s: rxglom returned %d\n", __FUNCTION__, cnt));
++			rxseq += cnt - 1;
++			rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
++			continue;
++		}
++
++		/* Try doing single read if we can */
++		if (dhd_readahead && bus->nextlen) {
++			uint16 nextlen = bus->nextlen;
++			bus->nextlen = 0;
++
++			if (bus->bus == SPI_BUS) {
++				rdlen = len = nextlen;
++			} else {
++				rdlen = len = nextlen << 4;
++
++				/* Pad read to blocksize for efficiency */
++				if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
++					pad = bus->blocksize - (rdlen % bus->blocksize);
++					if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
++						((rdlen + pad + firstread) < MAX_RX_DATASZ))
++						rdlen += pad;
++				} else if (rdlen % DHD_SDALIGN) {
++					rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
++				}
++			}
++
++			/* We use bus->rxctl buffer in WinXP for initial control pkt receives.
++			 * Later we use buffer-poll for data as well as control packets.
++			 * This is required because dhd receives full frame in gSPI unlike SDIO.
++			 * After the frame is received we have to distinguish whether it is data
++			 * or non-data frame.
++			 */
++			/* Allocate a packet buffer */
++			dhd_os_sdlock_rxq(bus->dhd);
++			if (!(pkt = PKTGET(osh, rdlen + DHD_SDALIGN, FALSE))) {
++				if (bus->bus == SPI_BUS) {
++					bus->usebufpool = FALSE;
++					bus->rxctl = bus->rxbuf;
++					if (dhd_alignctl) {
++						bus->rxctl += firstread;
++						if ((pad = ((uintptr)bus->rxctl % DHD_SDALIGN)))
++							bus->rxctl += (DHD_SDALIGN - pad);
++						bus->rxctl -= firstread;
++					}
++					ASSERT(bus->rxctl >= bus->rxbuf);
++					rxbuf = bus->rxctl;
++					/* Read the entire frame */
++					sdret = dhd_bcmsdh_recv_buf(bus,
++					                            bcmsdh_cur_sbwad(sdh),
++					                            SDIO_FUNC_2,
++					                            F2SYNC, rxbuf, rdlen,
++					                            NULL, NULL, NULL);
++					bus->f2rxdata++;
++					ASSERT(sdret != BCME_PENDING);
++
++
++					/* Control frame failures need retransmission */
++					if (sdret < 0) {
++						DHD_ERROR(("%s: read %d control bytes failed: %d\n",
++						   __FUNCTION__, rdlen, sdret));
++						/* dhd.rx_ctlerrs is higher level */
++						bus->rxc_errors++;
++						dhd_os_sdunlock_rxq(bus->dhd);
++						dhdsdio_rxfail(bus, TRUE,
++						    (bus->bus == SPI_BUS) ? FALSE : TRUE);
++						continue;
++					}
++				} else {
++					/* Give up on data, request rtx of events */
++					DHD_ERROR(("%s (nextlen): PKTGET failed: len %d rdlen %d "
++					           "expected rxseq %d\n",
++					           __FUNCTION__, len, rdlen, rxseq));
++					/* Just go try again w/normal header read */
++					dhd_os_sdunlock_rxq(bus->dhd);
++					continue;
++				}
++			} else {
++				if (bus->bus == SPI_BUS)
++					bus->usebufpool = TRUE;
++
++				ASSERT(!PKTLINK(pkt));
++				PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
++				rxbuf = (uint8 *)PKTDATA(osh, pkt);
++				/* Read the entire frame */
++				sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh),
++				                            SDIO_FUNC_2,
++				                            F2SYNC, rxbuf, rdlen,
++				                            pkt, NULL, NULL);
++				bus->f2rxdata++;
++				ASSERT(sdret != BCME_PENDING);
++
++				if (sdret < 0) {
++					DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
++					   __FUNCTION__, rdlen, sdret));
++					PKTFREE(bus->dhd->osh, pkt, FALSE);
++					bus->dhd->rx_errors++;
++					dhd_os_sdunlock_rxq(bus->dhd);
++					/* Force retry w/normal header read.  Don't attempt NAK for
++					 * gSPI
++					 */
++					dhdsdio_rxfail(bus, TRUE,
++					      (bus->bus == SPI_BUS) ? FALSE : TRUE);
++					continue;
++				}
++			}
++			dhd_os_sdunlock_rxq(bus->dhd);
++
++			/* Now check the header */
++			bcopy(rxbuf, bus->rxhdr, SDPCM_HDRLEN);
++
++			/* Extract hardware header fields */
++			len = ltoh16_ua(bus->rxhdr);
++			check = ltoh16_ua(bus->rxhdr + sizeof(uint16));
++
++			/* All zeros means readahead info was bad */
++			if (!(len|check)) {
++				DHD_INFO(("%s (nextlen): read zeros in HW header???\n",
++				           __FUNCTION__));
++				dhd_os_sdlock_rxq(bus->dhd);
++				PKTFREE2();
++				dhd_os_sdunlock_rxq(bus->dhd);
++				GSPI_PR55150_BAILOUT;
++				continue;
++			}
++
++			/* Validate check bytes */
++			if ((uint16)~(len^check)) {
++				DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check"
++				           " 0x%04x/0x%04x/0x%04x\n", __FUNCTION__, nextlen,
++				           len, check));
++				dhd_os_sdlock_rxq(bus->dhd);
++				PKTFREE2();
++				dhd_os_sdunlock_rxq(bus->dhd);
++				bus->rx_badhdr++;
++				dhdsdio_rxfail(bus, FALSE, FALSE);
++				GSPI_PR55150_BAILOUT;
++				continue;
++			}
++
++			/* Validate frame length */
++			if (len < SDPCM_HDRLEN) {
++				DHD_ERROR(("%s (nextlen): HW hdr length invalid: %d\n",
++				           __FUNCTION__, len));
++				dhd_os_sdlock_rxq(bus->dhd);
++				PKTFREE2();
++				dhd_os_sdunlock_rxq(bus->dhd);
++				GSPI_PR55150_BAILOUT;
++				continue;
++			}
++
++			/* Check for consistency with readahead info */
++				len_consistent = (nextlen != (ROUNDUP(len, 16) >> 4));
++			if (len_consistent) {
++				/* Mismatch, force retry w/normal header (may be >4K) */
++				DHD_ERROR(("%s (nextlen): mismatch, nextlen %d len %d rnd %d; "
++				           "expected rxseq %d\n",
++				           __FUNCTION__, nextlen, len, ROUNDUP(len, 16), rxseq));
++				dhd_os_sdlock_rxq(bus->dhd);
++				PKTFREE2();
++				dhd_os_sdunlock_rxq(bus->dhd);
++				dhdsdio_rxfail(bus, TRUE, (bus->bus == SPI_BUS) ? FALSE : TRUE);
++				GSPI_PR55150_BAILOUT;
++				continue;
++			}
++
++
++			/* Extract software header fields */
++			chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++			seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++			doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++			txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++
++				bus->nextlen =
++				         bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
++				if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
++					DHD_INFO(("%s (nextlen): got frame w/nextlen too large"
++					          " (%d), seq %d\n", __FUNCTION__, bus->nextlen,
++					          seq));
++					bus->nextlen = 0;
++				}
++
++				bus->dhd->rx_readahead_cnt ++;
++			/* Handle Flow Control */
++			fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++
++			delta = 0;
++			if (~bus->flowcontrol & fcbits) {
++				bus->fc_xoff++;
++				delta = 1;
++			}
++			if (bus->flowcontrol & ~fcbits) {
++				bus->fc_xon++;
++				delta = 1;
++			}
++
++			if (delta) {
++				bus->fc_rcvd++;
++				bus->flowcontrol = fcbits;
++			}
++
++			/* Check and update sequence number */
++			if (rxseq != seq) {
++				DHD_INFO(("%s (nextlen): rx_seq %d, expected %d\n",
++				          __FUNCTION__, seq, rxseq));
++				bus->rx_badseq++;
++				rxseq = seq;
++			}
++
++			/* Check window for sanity */
++			if ((uint8)(txmax - bus->tx_seq) > 0x70) {
++					DHD_INFO(("%s: got unlikely tx max %d with tx_seq %d\n",
++						__FUNCTION__, txmax, bus->tx_seq));
++					txmax = bus->tx_max;
++			}
++			bus->tx_max = txmax;
++
++#ifdef DHD_DEBUG
++			if (DHD_BYTES_ON() && DHD_DATA_ON()) {
++				prhex("Rx Data", rxbuf, len);
++			} else if (DHD_HDRS_ON()) {
++				prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
++			}
++#endif
++
++			if (chan == SDPCM_CONTROL_CHANNEL) {
++				if (bus->bus == SPI_BUS) {
++					dhdsdio_read_control(bus, rxbuf, len, doff);
++					if (bus->usebufpool) {
++						dhd_os_sdlock_rxq(bus->dhd);
++						PKTFREE(bus->dhd->osh, pkt, FALSE);
++						dhd_os_sdunlock_rxq(bus->dhd);
++					}
++					continue;
++				} else {
++					DHD_ERROR(("%s (nextlen): readahead on control"
++					           " packet %d?\n", __FUNCTION__, seq));
++					/* Force retry w/normal header read */
++					bus->nextlen = 0;
++					dhdsdio_rxfail(bus, FALSE, TRUE);
++					dhd_os_sdlock_rxq(bus->dhd);
++					PKTFREE2();
++					dhd_os_sdunlock_rxq(bus->dhd);
++					continue;
++				}
++			}
++
++			if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
++				DHD_ERROR(("Received %d bytes on %d channel. Running out of "
++				           "rx pktbuf's or not yet malloced.\n", len, chan));
++				continue;
++			}
++
++			/* Validate data offset */
++			if ((doff < SDPCM_HDRLEN) || (doff > len)) {
++				DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
++				           __FUNCTION__, doff, len, SDPCM_HDRLEN));
++				dhd_os_sdlock_rxq(bus->dhd);
++				PKTFREE2();
++				dhd_os_sdunlock_rxq(bus->dhd);
++				ASSERT(0);
++				dhdsdio_rxfail(bus, FALSE, FALSE);
++				continue;
++			}
++
++			/* All done with this one -- now deliver the packet */
++			goto deliver;
++		}
++		/* gSPI frames should not be handled in fractions */
++		if (bus->bus == SPI_BUS) {
++			break;
++		}
++
++		/* Read frame header (hardware and software) */
++		sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
++		                            bus->rxhdr, firstread, NULL, NULL, NULL);
++		bus->f2rxhdrs++;
++		ASSERT(sdret != BCME_PENDING);
++
++		if (sdret < 0) {
++			DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __FUNCTION__, sdret));
++			bus->rx_hdrfail++;
++			dhdsdio_rxfail(bus, TRUE, TRUE);
++			continue;
++		}
++
++#ifdef DHD_DEBUG
++		if (DHD_BYTES_ON() || DHD_HDRS_ON()) {
++			prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
++		}
++#endif
++
++		/* Extract hardware header fields */
++		len = ltoh16_ua(bus->rxhdr);
++		check = ltoh16_ua(bus->rxhdr + sizeof(uint16));
++
++		/* All zeros means no more frames */
++		if (!(len|check)) {
++			*finished = TRUE;
++			break;
++		}
++
++		/* Validate check bytes */
++		if ((uint16)~(len^check)) {
++			DHD_ERROR(("%s: HW hdr error: len/check 0x%04x/0x%04x\n",
++			           __FUNCTION__, len, check));
++			bus->rx_badhdr++;
++			dhdsdio_rxfail(bus, FALSE, FALSE);
++			continue;
++		}
++
++		/* Validate frame length */
++		if (len < SDPCM_HDRLEN) {
++			DHD_ERROR(("%s: HW hdr length invalid: %d\n", __FUNCTION__, len));
++			continue;
++		}
++
++		/* Extract software header fields */
++		chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++		seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++		doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++		txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++
++		/* Validate data offset */
++		if ((doff < SDPCM_HDRLEN) || (doff > len)) {
++			DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d seq %d\n",
++			           __FUNCTION__, doff, len, SDPCM_HDRLEN, seq));
++			bus->rx_badhdr++;
++			ASSERT(0);
++			dhdsdio_rxfail(bus, FALSE, FALSE);
++			continue;
++		}
++
++		/* Save the readahead length if there is one */
++		bus->nextlen = bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
++		if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
++			DHD_INFO(("%s (nextlen): got frame w/nextlen too large (%d), seq %d\n",
++			          __FUNCTION__, bus->nextlen, seq));
++			bus->nextlen = 0;
++		}
++
++		/* Handle Flow Control */
++		fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++
++		delta = 0;
++		if (~bus->flowcontrol & fcbits) {
++			bus->fc_xoff++;
++			delta = 1;
++		}
++		if (bus->flowcontrol & ~fcbits) {
++			bus->fc_xon++;
++			delta = 1;
++		}
++
++		if (delta) {
++			bus->fc_rcvd++;
++			bus->flowcontrol = fcbits;
++		}
++
++		/* Check and update sequence number */
++		if (rxseq != seq) {
++			DHD_INFO(("%s: rx_seq %d, expected %d\n", __FUNCTION__, seq, rxseq));
++			bus->rx_badseq++;
++			rxseq = seq;
++		}
++
++		/* Check window for sanity */
++		if ((uint8)(txmax - bus->tx_seq) > 0x70) {
++			DHD_INFO(("%s: got unlikely tx max %d with tx_seq %d\n",
++			           __FUNCTION__, txmax, bus->tx_seq));
++			txmax = bus->tx_max;
++		}
++		bus->tx_max = txmax;
++
++		/* Call a separate function for control frames */
++		if (chan == SDPCM_CONTROL_CHANNEL) {
++			dhdsdio_read_control(bus, bus->rxhdr, len, doff);
++			continue;
++		}
++
++		ASSERT((chan == SDPCM_DATA_CHANNEL) || (chan == SDPCM_EVENT_CHANNEL) ||
++		       (chan == SDPCM_TEST_CHANNEL) || (chan == SDPCM_GLOM_CHANNEL));
++
++		/* Length to read */
++		rdlen = (len > firstread) ? (len - firstread) : 0;
++
++		/* May pad read to blocksize for efficiency */
++		if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
++			pad = bus->blocksize - (rdlen % bus->blocksize);
++			if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
++			    ((rdlen + pad + firstread) < MAX_RX_DATASZ))
++				rdlen += pad;
++		} else if (rdlen % DHD_SDALIGN) {
++			rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
++		}
++
++		/* Satisfy length-alignment requirements */
++		if (forcealign && (rdlen & (ALIGNMENT - 1)))
++			rdlen = ROUNDUP(rdlen, ALIGNMENT);
++
++		if ((rdlen + firstread) > MAX_RX_DATASZ) {
++			/* Too long -- skip this frame */
++			DHD_ERROR(("%s: too long: len %d rdlen %d\n", __FUNCTION__, len, rdlen));
++			bus->dhd->rx_errors++; bus->rx_toolong++;
++			dhdsdio_rxfail(bus, FALSE, FALSE);
++			continue;
++		}
++
++		dhd_os_sdlock_rxq(bus->dhd);
++		if (!(pkt = PKTGET(osh, (rdlen + firstread + DHD_SDALIGN), FALSE))) {
++			/* Give up on data, request rtx of events */
++			DHD_ERROR(("%s: PKTGET failed: rdlen %d chan %d\n",
++			           __FUNCTION__, rdlen, chan));
++			bus->dhd->rx_dropped++;
++			dhd_os_sdunlock_rxq(bus->dhd);
++			dhdsdio_rxfail(bus, FALSE, RETRYCHAN(chan));
++			continue;
++		}
++		dhd_os_sdunlock_rxq(bus->dhd);
++
++		ASSERT(!PKTLINK(pkt));
++
++		/* Leave room for what we already read, and align remainder */
++		ASSERT(firstread < (PKTLEN(osh, pkt)));
++		PKTPULL(osh, pkt, firstread);
++		PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
++
++		/* Read the remaining frame data */
++		sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
++		                            ((uint8 *)PKTDATA(osh, pkt)), rdlen, pkt, NULL, NULL);
++		bus->f2rxdata++;
++		ASSERT(sdret != BCME_PENDING);
++
++		if (sdret < 0) {
++			DHD_ERROR(("%s: read %d %s bytes failed: %d\n", __FUNCTION__, rdlen,
++			           ((chan == SDPCM_EVENT_CHANNEL) ? "event" :
++			            ((chan == SDPCM_DATA_CHANNEL) ? "data" : "test")), sdret));
++			dhd_os_sdlock_rxq(bus->dhd);
++			PKTFREE(bus->dhd->osh, pkt, FALSE);
++			dhd_os_sdunlock_rxq(bus->dhd);
++			bus->dhd->rx_errors++;
++			dhdsdio_rxfail(bus, TRUE, RETRYCHAN(chan));
++			continue;
++		}
++
++		/* Copy the already-read portion */
++		PKTPUSH(osh, pkt, firstread);
++		bcopy(bus->rxhdr, PKTDATA(osh, pkt), firstread);
++
++#ifdef DHD_DEBUG
++		if (DHD_BYTES_ON() && DHD_DATA_ON()) {
++			prhex("Rx Data", PKTDATA(osh, pkt), len);
++		}
++#endif
++
++deliver:
++		/* Save superframe descriptor and allocate packet frame */
++		if (chan == SDPCM_GLOM_CHANNEL) {
++			if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
++				DHD_GLOM(("%s: got glom descriptor, %d bytes:\n",
++				          __FUNCTION__, len));
++#ifdef DHD_DEBUG
++				if (DHD_GLOM_ON()) {
++					prhex("Glom Data", PKTDATA(osh, pkt), len);
++				}
++#endif
++				PKTSETLEN(osh, pkt, len);
++				ASSERT(doff == SDPCM_HDRLEN);
++				PKTPULL(osh, pkt, SDPCM_HDRLEN);
++				bus->glomd = pkt;
++			} else {
++				DHD_ERROR(("%s: glom superframe w/o descriptor!\n", __FUNCTION__));
++				dhdsdio_rxfail(bus, FALSE, FALSE);
++			}
++			continue;
++		}
++
++		/* Fill in packet len and prio, deliver upward */
++		PKTSETLEN(osh, pkt, len);
++		PKTPULL(osh, pkt, doff);
++
++#ifdef SDTEST
++		/* Test channel packets are processed separately */
++		if (chan == SDPCM_TEST_CHANNEL) {
++			dhdsdio_testrcv(bus, pkt, seq);
++			continue;
++		}
++#endif /* SDTEST */
++
++		if (PKTLEN(osh, pkt) == 0) {
++			dhd_os_sdlock_rxq(bus->dhd);
++			PKTFREE(bus->dhd->osh, pkt, FALSE);
++			dhd_os_sdunlock_rxq(bus->dhd);
++			continue;
++		} else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt, reorder_info_buf,
++			&reorder_info_len) != 0) {
++			DHD_ERROR(("%s: rx protocol error\n", __FUNCTION__));
++			dhd_os_sdlock_rxq(bus->dhd);
++			PKTFREE(bus->dhd->osh, pkt, FALSE);
++			dhd_os_sdunlock_rxq(bus->dhd);
++			bus->dhd->rx_errors++;
++			continue;
++		}
++
++		if (reorder_info_len) {
++			/* Reordering info from the firmware */
++			dhd_process_pkt_reorder_info(bus->dhd, reorder_info_buf, reorder_info_len,
++				&pkt, &pkt_count);
++			if (pkt_count == 0)
++				continue;
++		} else {
++			pkt_count = 1;
++		}
++
++		/* Unlock during rx call */
++		dhd_os_sdunlock(bus->dhd);
++		dhd_rx_frame(bus->dhd, ifidx, pkt, pkt_count, chan);
++		dhd_os_sdlock(bus->dhd);
++#if defined(SDIO_ISR_THREAD)
++		/* terence 20150615: fix for below error due to bussleep in watchdog after dhd_os_sdunlock here,
++		  * so call BUS_WAKE to wake up bus again
++		  * dhd_bcmsdh_recv_buf: Device asleep
++		  * dhdsdio_readframes: RXHEADER FAILED: -40
++		  * dhdsdio_rxfail: abort command, terminate frame, send NAK
++		*/
++		BUS_WAKE(bus);
++#endif
++	}
++	rxcount = maxframes - rxleft;
++#ifdef DHD_DEBUG
++	/* Message if we hit the limit */
++	if (!rxleft && !sdtest)
++		DHD_DATA(("%s: hit rx limit of %d frames\n", __FUNCTION__, maxframes));
++	else
++#endif /* DHD_DEBUG */
++	DHD_DATA(("%s: processed %d frames\n", __FUNCTION__, rxcount));
++	/* Back off rxseq if awaiting rtx, update rx_seq */
++	if (bus->rxskip)
++		rxseq--;
++	bus->rx_seq = rxseq;
++
++	if (bus->reqbussleep)
++	{
++		dhdsdio_bussleep(bus, TRUE);
++		bus->reqbussleep = FALSE;
++	}
++	bus->readframes = FALSE;
++
++	return rxcount;
++}
++
++static uint32
++dhdsdio_hostmail(dhd_bus_t *bus, uint32 *hmbd)
++{
++	sdpcmd_regs_t *regs = bus->regs;
++	uint32 intstatus = 0;
++	uint32 hmb_data;
++	uint8 fcbits;
++	uint retries = 0;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	/* Read mailbox data and ack that we did so */
++	R_SDREG(hmb_data, &regs->tohostmailboxdata, retries);
++	if (retries <= retry_limit)
++		W_SDREG(SMB_INT_ACK, &regs->tosbmailbox, retries);
++	bus->f1regdata += 2;
++
++	/* Dongle recomposed rx frames, accept them again */
++	if (hmb_data & HMB_DATA_NAKHANDLED) {
++		DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n", bus->rx_seq));
++		if (!bus->rxskip) {
++			DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __FUNCTION__));
++		}
++		bus->rxskip = FALSE;
++		intstatus |= FRAME_AVAIL_MASK(bus);
++	}
++
++	/*
++	 * DEVREADY does not occur with gSPI.
++	 */
++	if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
++		bus->sdpcm_ver = (hmb_data & HMB_DATA_VERSION_MASK) >> HMB_DATA_VERSION_SHIFT;
++		if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
++			DHD_ERROR(("Version mismatch, dongle reports %d, expecting %d\n",
++			           bus->sdpcm_ver, SDPCM_PROT_VERSION));
++		else
++			DHD_INFO(("Dongle ready, protocol version %d\n", bus->sdpcm_ver));
++		/* make sure for the SDIO_DEVICE_RXDATAINT_MODE_1 corecontrol is proper */
++		if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev >= 4) &&
++		    (bus->rxint_mode  == SDIO_DEVICE_RXDATAINT_MODE_1)) {
++			uint32 val;
++
++			val = R_REG(bus->dhd->osh, &bus->regs->corecontrol);
++			val &= ~CC_XMTDATAAVAIL_MODE;
++			val |= CC_XMTDATAAVAIL_CTRL;
++			W_REG(bus->dhd->osh, &bus->regs->corecontrol, val);
++
++			val = R_REG(bus->dhd->osh, &bus->regs->corecontrol);
++		}
++
++#ifdef DHD_DEBUG
++		/* Retrieve console state address now that firmware should have updated it */
++		{
++			sdpcm_shared_t shared;
++			if (dhdsdio_readshared(bus, &shared) == 0)
++				bus->console_addr = shared.console_addr;
++		}
++#endif /* DHD_DEBUG */
++	}
++
++	/*
++	 * Flow Control has been moved into the RX headers and this out of band
++	 * method isn't used any more.  Leave this here for possibly remaining backward
++	 * compatible with older dongles
++	 */
++	if (hmb_data & HMB_DATA_FC) {
++		fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> HMB_DATA_FCDATA_SHIFT;
++
++		if (fcbits & ~bus->flowcontrol)
++			bus->fc_xoff++;
++		if (bus->flowcontrol & ~fcbits)
++			bus->fc_xon++;
++
++		bus->fc_rcvd++;
++		bus->flowcontrol = fcbits;
++	}
++
++	/* At least print a message if FW halted */
++	if (hmb_data & HMB_DATA_FWHALT) {
++		DHD_ERROR(("INTERNAL ERROR: FIRMWARE HALTED : set BUS DOWN\n"));
++		dhdsdio_checkdied(bus, NULL, 0);
++		bus->dhd->busstate = DHD_BUS_DOWN;
++	}
++
++	/* Shouldn't be any others */
++	if (hmb_data & ~(HMB_DATA_DEVREADY |
++	                 HMB_DATA_FWHALT |
++	                 HMB_DATA_NAKHANDLED |
++	                 HMB_DATA_FC |
++	                 HMB_DATA_FWREADY |
++	                 HMB_DATA_FCDATA_MASK |
++	                 HMB_DATA_VERSION_MASK)) {
++		DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
++	}
++
++	if (hmbd) {
++		*hmbd = hmb_data;
++	}
++
++	return intstatus;
++}
++
++static bool
++dhdsdio_dpc(dhd_bus_t *bus)
++{
++	bcmsdh_info_t *sdh = bus->sdh;
++	sdpcmd_regs_t *regs = bus->regs;
++	uint32 intstatus, newstatus = 0;
++	uint retries = 0;
++	uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
++	uint txlimit = dhd_txbound; /* Tx frames to send before resched */
++	uint framecnt = 0;		  /* Temporary counter of tx/rx frames */
++	bool rxdone = TRUE;		  /* Flag for no more read data */
++	bool resched = FALSE;	  /* Flag indicating resched wanted */
++	unsigned long flags;
++#ifdef DEBUG_DPC_THREAD_WATCHDOG
++	bool is_resched_by_readframe = FALSE;
++#endif /* DEBUG_DPC_THREAD_WATCHDOG */
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	dhd_os_sdlock(bus->dhd);
++	DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
++	if (bus->dhd->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s: Bus down, ret\n", __FUNCTION__));
++		bus->intstatus = 0;
++		DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
++		dhd_os_sdunlock(bus->dhd);
++		return 0;
++	}
++
++	DHD_BUS_BUSY_SET_IN_DPC(bus->dhd);
++	DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
++
++	/* Start with leftover status bits */
++	intstatus = bus->intstatus;
++
++	if (!SLPAUTO_ENAB(bus) && !KSO_ENAB(bus)) {
++		DHD_ERROR(("%s: Device asleep\n", __FUNCTION__));
++		goto exit;
++	}
++
++	/* If waiting for HTAVAIL, check status */
++	if (!SLPAUTO_ENAB(bus) && (bus->clkstate == CLK_PENDING)) {
++		int err;
++		uint8 clkctl, devctl = 0;
++
++#ifdef DHD_DEBUG
++		/* Check for inconsistent device control */
++		devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
++		if (err) {
++			DHD_ERROR(("%s: error reading DEVCTL: %d\n", __FUNCTION__, err));
++			bus->dhd->busstate = DHD_BUS_DOWN;
++		} else {
++			ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
++		}
++#endif /* DHD_DEBUG */
++
++		/* Read CSR, if clock on switch to AVAIL, else ignore */
++		clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
++		if (err) {
++			DHD_ERROR(("%s: error reading CSR: %d\n", __FUNCTION__, err));
++			bus->dhd->busstate = DHD_BUS_DOWN;
++		}
++
++		DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl, clkctl));
++
++		if (SBSDIO_HTAV(clkctl)) {
++			devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
++			if (err) {
++				DHD_ERROR(("%s: error reading DEVCTL: %d\n",
++				           __FUNCTION__, err));
++				bus->dhd->busstate = DHD_BUS_DOWN;
++			}
++			devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
++			bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
++			if (err) {
++				DHD_ERROR(("%s: error writing DEVCTL: %d\n",
++				           __FUNCTION__, err));
++				bus->dhd->busstate = DHD_BUS_DOWN;
++			}
++			bus->clkstate = CLK_AVAIL;
++		} else {
++			goto clkwait;
++		}
++	}
++
++	BUS_WAKE(bus);
++
++	/* Make sure backplane clock is on */
++	dhdsdio_clkctl(bus, CLK_AVAIL, TRUE);
++	if (bus->clkstate != CLK_AVAIL)
++		goto clkwait;
++
++	/* Pending interrupt indicates new device status */
++	if (bus->ipend) {
++		bus->ipend = FALSE;
++#if defined(BT_OVER_SDIO)
++	bcmsdh_btsdio_process_f3_intr();
++#endif /* defined (BT_OVER_SDIO) */
++
++		R_SDREG(newstatus, &regs->intstatus, retries);
++		bus->f1regdata++;
++		if (bcmsdh_regfail(bus->sdh))
++			newstatus = 0;
++		newstatus &= bus->hostintmask;
++		bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
++		if (newstatus) {
++			bus->f1regdata++;
++			if ((bus->rxint_mode == SDIO_DEVICE_RXDATAINT_MODE_0) &&
++				(newstatus == I_XMTDATA_AVAIL)) {
++			} else
++				W_SDREG(newstatus, &regs->intstatus, retries);
++		}
++	}
++
++	/* Merge new bits with previous */
++	intstatus |= newstatus;
++	bus->intstatus = 0;
++
++	/* Handle flow-control change: read new state in case our ack
++	 * crossed another change interrupt.  If change still set, assume
++	 * FC ON for safety, let next loop through do the debounce.
++	 */
++	if (intstatus & I_HMB_FC_CHANGE) {
++		intstatus &= ~I_HMB_FC_CHANGE;
++		W_SDREG(I_HMB_FC_CHANGE, &regs->intstatus, retries);
++		R_SDREG(newstatus, &regs->intstatus, retries);
++		bus->f1regdata += 2;
++		bus->fcstate = !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
++		intstatus |= (newstatus & bus->hostintmask);
++	}
++
++	/* Handle host mailbox indication */
++	if (intstatus & I_HMB_HOST_INT) {
++		uint32 hmbdata = 0;
++
++		intstatus &= ~I_HMB_HOST_INT;
++		intstatus |= dhdsdio_hostmail(bus, &hmbdata);
++
++#ifdef DHD_ULP
++		/* ULP prototyping. Redowload fw on oob interupt */
++
++		/* all the writes after this point CAN use cached sbwad value */
++		bcmsdh_force_sbwad_calc(bus->sdh, FALSE);
++
++		if (dhd_ulp_pre_redownload_check(bus->dhd, bus->sdh, hmbdata)) {
++			if (dhd_bus_ulp_reinit_fw(bus) < 0) {
++				DHD_ERROR(("%s:%d FW redownload failed\n",
++					__FUNCTION__, __LINE__));
++				goto exit;
++			}
++		}
++#endif
++
++	}
++
++	/* Just being here means nothing more to do for chipactive */
++	if (intstatus & I_CHIPACTIVE) {
++		/* ASSERT(bus->clkstate == CLK_AVAIL); */
++		intstatus &= ~I_CHIPACTIVE;
++	}
++
++	/* Handle host mailbox indication */
++	if (intstatus & I_HMB_HOST_INT) {
++		intstatus &= ~I_HMB_HOST_INT;
++		intstatus |= dhdsdio_hostmail(bus, NULL);
++	}
++
++	/* Generally don't ask for these, can get CRC errors... */
++	if (intstatus & I_WR_OOSYNC) {
++		DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
++		intstatus &= ~I_WR_OOSYNC;
++	}
++
++	if (intstatus & I_RD_OOSYNC) {
++		DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
++		intstatus &= ~I_RD_OOSYNC;
++	}
++
++	if (intstatus & I_SBINT) {
++		DHD_ERROR(("Dongle reports SBINT\n"));
++		intstatus &= ~I_SBINT;
++	}
++
++	/* Would be active due to wake-wlan in gSPI */
++	if (intstatus & I_CHIPACTIVE) {
++		DHD_INFO(("Dongle reports CHIPACTIVE\n"));
++		intstatus &= ~I_CHIPACTIVE;
++	}
++
++	if (intstatus & I_HMB_FC_STATE) {
++		DHD_INFO(("Dongle reports HMB_FC_STATE\n"));
++		intstatus &= ~I_HMB_FC_STATE;
++	}
++
++	/* Ignore frame indications if rxskip is set */
++	if (bus->rxskip) {
++		intstatus &= ~FRAME_AVAIL_MASK(bus);
++	}
++
++	/* On frame indication, read available frames */
++	if (PKT_AVAILABLE(bus, intstatus)) {
++
++		framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
++		if (rxdone || bus->rxskip)
++			intstatus  &= ~FRAME_AVAIL_MASK(bus);
++		rxlimit -= MIN(framecnt, rxlimit);
++	}
++
++	/* Keep still-pending events for next scheduling */
++	bus->intstatus = intstatus;
++
++clkwait:
++	/* Re-enable interrupts to detect new device events (mailbox, rx frame)
++	 * or clock availability.  (Allows tx loop to check ipend if desired.)
++	 * (Unless register access seems hosed, as we may not be able to ACK...)
++	 */
++	if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh) &&
++			!(bus->dhd->conf->oob_enabled_later && !bus->ctrl_frame_stat)) {
++		DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
++		          __FUNCTION__, rxdone, framecnt));
++		bus->intdis = FALSE;
++#if defined(OOB_INTR_ONLY)
++		bcmsdh_oob_intr_set(bus->sdh, TRUE);
++#endif /* defined(OOB_INTR_ONLY) */
++		bcmsdh_intr_enable(sdh);
++	}
++
++#if defined(OOB_INTR_ONLY) && !defined(HW_OOB)
++	/* In case of SW-OOB(using edge trigger),
++	 * Check interrupt status in the dongle again after enable irq on the host.
++	 * and rechedule dpc if interrupt is pended in the dongle.
++	 * There is a chance to miss OOB interrupt while irq is disabled on the host.
++	 * No need to do this with HW-OOB(level trigger)
++	 */
++	R_SDREG(newstatus, &regs->intstatus, retries);
++	if (bcmsdh_regfail(bus->sdh))
++		newstatus = 0;
++	if (newstatus & bus->hostintmask) {
++		bus->ipend = TRUE;
++		resched = TRUE;
++	}
++#endif /* defined(OOB_INTR_ONLY) && !defined(HW_OOB) */
++
++#ifdef BCMSDIO_RXLIM_POST
++	if (!DATAOK(bus) && bus->rxlim_en) {
++		uint8 rxlim = 0;
++		if (0 == dhdsdio_membytes(bus, FALSE, bus->rxlim_addr, (uint8 *)&rxlim, 1)) {
++			if (bus->tx_max != rxlim) {
++				DHD_INFO(("%s: bus->tx_max/rxlim=%d/%d\n", __FUNCTION__,
++					bus->tx_max, rxlim));
++				bus->tx_max = rxlim;
++			}
++		}
++	}
++#endif /* BCMSDIO_RXLIM_POST */
++
++#ifdef PROP_TXSTATUS
++	dhd_wlfc_commit_packets(bus->dhd, (f_commitpkt_t)dhd_bus_txdata, (void *)bus, NULL, FALSE);
++#endif
++
++	if (TXCTLOK(bus) && bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL))
++		dhdsdio_sendpendctl(bus);
++#ifdef CONSOLE_DPC
++	else if (DATAOK(bus) && strlen(bus->cons_cmd) && (bus->clkstate == CLK_AVAIL) &&
++			!bus->fcstate) {
++		dhd_bus_console_in(bus->dhd, bus->cons_cmd, strlen(bus->cons_cmd));
++	}
++#endif
++
++	/* Send queued frames (limit 1 if rx may still be pending) */
++	else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
++	    pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit && DATAOK(bus)) {
++
++#ifdef DHD_ULP
++		if (dhd_ulp_f2_ready(bus->dhd, bus->sdh)) {
++#endif /* DHD_ULP */
++			if (bus->dhd->conf->dhd_txminmax < 0)
++				framecnt = rxdone ? txlimit : MIN(txlimit, DATABUFCNT(bus));
++			else
++				framecnt = rxdone ? txlimit : MIN(txlimit, bus->dhd->conf->dhd_txminmax);
++			framecnt = dhdsdio_sendfromq(bus, framecnt);
++			txlimit -= framecnt;
++#ifdef DHD_ULP
++		} else {
++			/* In other transient states like DHD_ULP_, after the states are
++			* DHD_ULP_F2ENAB_CLEARING and DHD_ULP_F2ENAB_SETTING,
++			* dpc is scheduled after steady-state and dhdsdio_sendfromq() will
++			* execute again
++			*/
++		}
++#endif /* DHD_ULP */
++	}
++	/* Resched the DPC if ctrl cmd is pending on bus credit */
++	if (bus->ctrl_frame_stat) {
++		if (bus->dhd->conf->txctl_tmo_fix) {
++			set_current_state(TASK_INTERRUPTIBLE);
++			if (!kthread_should_stop())
++				schedule_timeout(1);
++			set_current_state(TASK_RUNNING);
++		}
++		resched = TRUE;
++	}
++
++	/* Resched if events or tx frames are pending, else await next interrupt */
++	/* On failed register access, all bets are off: no resched or interrupts */
++	if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
++		if ((bus->sih && bus->sih->buscorerev >= 12) && !(dhdsdio_sleepcsr_get(bus) &
++			SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
++			/* Bus failed because of KSO */
++			DHD_ERROR(("%s: Bus failed due to KSO\n", __FUNCTION__));
++			bus->kso = FALSE;
++		} else {
++			DHD_ERROR(("%s: failed backplane access over SDIO, halting operation\n",
++				__FUNCTION__));
++			bus->dhd->busstate = DHD_BUS_DOWN;
++			bus->intstatus = 0;
++		}
++	} else if (bus->clkstate == CLK_PENDING) {
++		/* Awaiting I_CHIPACTIVE; don't resched */
++	} else if (bus->intstatus || bus->ipend ||
++	           (!bus->fcstate && pktq_mlen(&bus->txq, ~bus->flowcontrol) && DATAOK(bus)) ||
++			PKT_AVAILABLE(bus, bus->intstatus)) {  /* Read multiple frames */
++		resched = TRUE;
++	}
++
++	bus->dpc_sched = resched;
++
++	/* If we're done for now, turn off clock request. */
++	if ((bus->idletime == DHD_IDLE_IMMEDIATE) && (bus->clkstate != CLK_PENDING) &&
++		NO_OTHER_ACTIVE_BUS_USER(bus)) {
++		bus->activity = FALSE;
++		dhdsdio_bussleep(bus, TRUE);
++		dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++	}
++
++exit:
++
++	if (!resched) {
++		/* Re-enable interrupts to detect new device events (mailbox, rx frame)
++		 * or clock availability.  (Allows tx loop to check ipend if desired.)
++		 * (Unless register access seems hosed, as we may not be able to ACK...)
++		 */
++		if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh) &&
++				(bus->dhd->conf->oob_enabled_later && !bus->ctrl_frame_stat)) {
++			DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
++					  __FUNCTION__, rxdone, framecnt));
++			bus->intdis = FALSE;
++#if defined(OOB_INTR_ONLY)
++			bcmsdh_oob_intr_set(bus->sdh, TRUE);
++#endif /* defined(OOB_INTR_ONLY) */
++			bcmsdh_intr_enable(sdh);
++		}
++		if (dhd_dpcpoll) {
++			if (dhdsdio_readframes(bus, dhd_rxbound, &rxdone) != 0) {
++				resched = TRUE;
++#ifdef DEBUG_DPC_THREAD_WATCHDOG
++				is_resched_by_readframe = TRUE;
++#endif /* DEBUG_DPC_THREAD_WATCHDOG */
++			}
++		}
++	}
++
++	if (bus->ctrl_wait && TXCTLOK(bus))
++		wake_up_interruptible(&bus->ctrl_tx_wait);
++	dhd_os_sdunlock(bus->dhd);
++#ifdef DEBUG_DPC_THREAD_WATCHDOG
++	if (bus->dhd->dhd_bug_on) {
++		DHD_INFO(("%s: resched = %d ctrl_frame_stat = %d intstatus 0x%08x"
++			" ipend = %d pktq_mlen = %d is_resched_by_readframe = %d \n",
++			__FUNCTION__, resched, bus->ctrl_frame_stat,
++			bus->intstatus, bus->ipend,
++			pktq_mlen(&bus->txq, ~bus->flowcontrol), is_resched_by_readframe));
++
++			bus->dhd->dhd_bug_on = FALSE;
++	}
++#endif /* DEBUG_DPC_THREAD_WATCHDOG */
++
++	DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
++	DHD_BUS_BUSY_CLEAR_IN_DPC(bus->dhd);
++	dhd_os_busbusy_wake(bus->dhd);
++	DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
++
++	return resched;
++}
++
++bool
++dhd_bus_dpc(struct dhd_bus *bus)
++{
++	bool resched;
++
++	/* Call the DPC directly. */
++	DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __FUNCTION__));
++	resched = dhdsdio_dpc(bus);
++
++	return resched;
++}
++
++void
++dhdsdio_isr(void *arg)
++{
++	dhd_bus_t *bus = (dhd_bus_t*)arg;
++	bcmsdh_info_t *sdh;
++
++	DHD_INTR(("%s: Enter\n", __FUNCTION__));
++
++	if (!bus) {
++		DHD_ERROR(("%s : bus is null pointer , exit \n", __FUNCTION__));
++		return;
++	}
++	sdh = bus->sdh;
++
++	if (bus->dhd->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s : bus is down. we have nothing to do\n", __FUNCTION__));
++		return;
++	}
++
++	/* Count the interrupt call */
++	bus->intrcount++;
++	bus->ipend = TRUE;
++
++	/* Shouldn't get this interrupt if we're sleeping? */
++	if (!SLPAUTO_ENAB(bus)) {
++		if (bus->sleeping) {
++			DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
++			return;
++		} else if (!KSO_ENAB(bus)) {
++			DHD_ERROR(("ISR in devsleep 1\n"));
++		}
++	}
++
++	/* Disable additional interrupts (is this needed now)? */
++	if (bus->intr) {
++		DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__));
++	} else {
++		DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
++	}
++
++	bcmsdh_intr_disable(sdh);
++	bus->intdis = TRUE;
++
++#if defined(SDIO_ISR_THREAD)
++	DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __FUNCTION__));
++	DHD_OS_WAKE_LOCK(bus->dhd);
++	/* terence 20150209: dpc should be scheded again if dpc_sched is TRUE or dhd_bus_txdata can
++	    not schedule anymore because dpc_sched is TRUE now.
++	 */
++	if (dhdsdio_dpc(bus)) {
++		bus->dpc_sched = TRUE;
++		dhd_sched_dpc(bus->dhd);
++	}
++	DHD_OS_WAKE_UNLOCK(bus->dhd);
++#else
++	bus->dpc_sched = TRUE;
++	dhd_sched_dpc(bus->dhd);
++#endif /* defined(SDIO_ISR_THREAD) */
++
++}
++
++#ifdef PKT_STATICS
++void dhdsdio_txpktstatics(void)
++{
++	uint i, total = 0;
++
++	printf("%s: TYPE EVENT: %d pkts (size=%d) transfered\n",
++		__FUNCTION__, tx_statics.event_count, tx_statics.event_size);
++	printf("%s: TYPE CTRL:  %d pkts (size=%d) transfered\n",
++		__FUNCTION__, tx_statics.ctrl_count, tx_statics.ctrl_size);
++	printf("%s: TYPE DATA:  %d pkts (size=%d) transfered\n",
++		__FUNCTION__, tx_statics.data_count, tx_statics.data_size);
++	printf("%s: Glom size distribution:\n", __FUNCTION__);
++	for (i=0;i<tx_statics.glom_max;i++) {
++		total += tx_statics.glom_cnt[i];
++	}
++	for (i=0;i<tx_statics.glom_max;i++) {
++		printf("%02d: %d", i+1, tx_statics.glom_cnt[i]);
++		if ((i+1)%8)
++			printf(", ");
++		else
++			printf("\n");
++	}
++	printf("\n");
++	for (i=0;i<tx_statics.glom_max;i++) {
++		printf("%02d:%3d%%", i+1, (tx_statics.glom_cnt[i]*100)/total);
++		if ((i+1)%8)
++			printf(", ");
++		else
++			printf("\n");
++	}
++	printf("\n");
++	printf("%s: data/glom=%d, glom_max=%d\n",
++		__FUNCTION__, tx_statics.data_count/total, tx_statics.glom_max);
++	printf("%s: TYPE RX GLOM: %d pkts (size=%d) transfered\n",
++		__FUNCTION__, tx_statics.glom_count, tx_statics.glom_size);
++	printf("%s: TYPE TEST: %d pkts (size=%d) transfered\n\n\n",
++		__FUNCTION__, tx_statics.test_count, tx_statics.test_size);
++}
++#endif
++
++#ifdef SDTEST
++static void
++dhdsdio_pktgen_init(dhd_bus_t *bus)
++{
++	/* Default to specified length, or full range */
++	if (dhd_pktgen_len) {
++		bus->pktgen_maxlen = MIN(dhd_pktgen_len, MAX_PKTGEN_LEN);
++		bus->pktgen_minlen = bus->pktgen_maxlen;
++	} else {
++		bus->pktgen_maxlen = MAX_PKTGEN_LEN;
++		bus->pktgen_minlen = 0;
++	}
++	bus->pktgen_len = (uint16)bus->pktgen_minlen;
++
++	/* Default to per-watchdog burst with 10s print time */
++	bus->pktgen_freq = 1;
++	bus->pktgen_print = dhd_watchdog_ms ? (10000 / dhd_watchdog_ms) : 0;
++	bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
++
++	/* Default to echo mode */
++	bus->pktgen_mode = DHD_PKTGEN_ECHO;
++	bus->pktgen_stop = 1;
++}
++
++static void
++dhdsdio_pktgen(dhd_bus_t *bus)
++{
++	void *pkt;
++	uint8 *data;
++	uint pktcount;
++	uint fillbyte;
++	osl_t *osh = bus->dhd->osh;
++	uint16 len;
++	ulong time_lapse;
++	uint sent_pkts;
++	uint rcvd_pkts;
++
++	/* Display current count if appropriate */
++	if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
++		bus->pktgen_ptick = 0;
++		printf("%s: send attempts %d, rcvd %d, errors %d\n",
++		       __FUNCTION__, bus->pktgen_sent, bus->pktgen_rcvd, bus->pktgen_fail);
++
++		/* Print throughput stats only for constant length packet runs */
++		if (bus->pktgen_minlen == bus->pktgen_maxlen) {
++			time_lapse = jiffies - bus->pktgen_prev_time;
++			bus->pktgen_prev_time = jiffies;
++			sent_pkts = bus->pktgen_sent - bus->pktgen_prev_sent;
++			bus->pktgen_prev_sent = bus->pktgen_sent;
++			rcvd_pkts = bus->pktgen_rcvd - bus->pktgen_prev_rcvd;
++			bus->pktgen_prev_rcvd = bus->pktgen_rcvd;
++
++			printf("%s: Tx Throughput %d kbps, Rx Throughput %d kbps\n",
++			  __FUNCTION__,
++			  (sent_pkts * bus->pktgen_len / jiffies_to_msecs(time_lapse)) * 8,
++			  (rcvd_pkts * bus->pktgen_len  / jiffies_to_msecs(time_lapse)) * 8);
++		}
++	}
++
++	/* For recv mode, just make sure dongle has started sending */
++	if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
++		if (bus->pktgen_rcv_state == PKTGEN_RCV_IDLE) {
++			bus->pktgen_rcv_state = PKTGEN_RCV_ONGOING;
++			dhdsdio_sdtest_set(bus, bus->pktgen_total);
++		}
++		return;
++	}
++
++	/* Otherwise, generate or request the specified number of packets */
++	for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
++		/* Stop if total has been reached */
++		if (bus->pktgen_total && (bus->pktgen_sent >= bus->pktgen_total)) {
++			bus->pktgen_count = 0;
++			break;
++		}
++
++		/* Allocate an appropriate-sized packet */
++		if (bus->pktgen_mode == DHD_PKTGEN_RXBURST) {
++			len = SDPCM_TEST_PKT_CNT_FLD_LEN;
++		} else {
++			len = bus->pktgen_len;
++		}
++		if (!(pkt = PKTGET(osh, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
++		                   TRUE))) {;
++			DHD_ERROR(("%s: PKTGET failed!\n", __FUNCTION__));
++			break;
++		}
++		PKTALIGN(osh, pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
++		data = (uint8*)PKTDATA(osh, pkt) + SDPCM_HDRLEN;
++
++		/* Write test header cmd and extra based on mode */
++		switch (bus->pktgen_mode) {
++		case DHD_PKTGEN_ECHO:
++			*data++ = SDPCM_TEST_ECHOREQ;
++			*data++ = (uint8)bus->pktgen_sent;
++			break;
++
++		case DHD_PKTGEN_SEND:
++			*data++ = SDPCM_TEST_DISCARD;
++			*data++ = (uint8)bus->pktgen_sent;
++			break;
++
++		case DHD_PKTGEN_RXBURST:
++			*data++ = SDPCM_TEST_BURST;
++			*data++ = (uint8)bus->pktgen_count; /* Just for backward compatability */
++			break;
++
++		default:
++			DHD_ERROR(("Unrecognized pktgen mode %d\n", bus->pktgen_mode));
++			PKTFREE(osh, pkt, TRUE);
++			bus->pktgen_count = 0;
++			return;
++		}
++
++		/* Write test header length field */
++		*data++ = (bus->pktgen_len >> 0);
++		*data++ = (bus->pktgen_len >> 8);
++
++		/* Write frame count in a 4 byte field adjucent to SDPCM test header for
++		 * burst mode
++		 */
++		if (bus->pktgen_mode == DHD_PKTGEN_RXBURST) {
++			*data++ = (uint8)(bus->pktgen_count >> 0);
++			*data++ = (uint8)(bus->pktgen_count >> 8);
++			*data++ = (uint8)(bus->pktgen_count >> 16);
++			*data++ = (uint8)(bus->pktgen_count >> 24);
++		} else {
++
++			/* Then fill in the remainder -- N/A for burst */
++			for (fillbyte = 0; fillbyte < len; fillbyte++)
++				*data++ = SDPCM_TEST_FILL(fillbyte, (uint8)bus->pktgen_sent);
++		}
++
++#ifdef DHD_DEBUG
++		if (DHD_BYTES_ON() && DHD_DATA_ON()) {
++			data = (uint8*)PKTDATA(osh, pkt) + SDPCM_HDRLEN;
++			prhex("dhdsdio_pktgen: Tx Data", data, PKTLEN(osh, pkt) - SDPCM_HDRLEN);
++		}
++#endif
++
++		/* Send it */
++		if (dhdsdio_txpkt(bus, SDPCM_TEST_CHANNEL, &pkt, 1, TRUE) != BCME_OK) {
++			bus->pktgen_fail++;
++			if (bus->pktgen_stop && bus->pktgen_stop == bus->pktgen_fail)
++				bus->pktgen_count = 0;
++		}
++		bus->pktgen_sent++;
++
++		/* Bump length if not fixed, wrap at max */
++		if (++bus->pktgen_len > bus->pktgen_maxlen)
++			bus->pktgen_len = (uint16)bus->pktgen_minlen;
++
++		/* Special case for burst mode: just send one request! */
++		if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
++			break;
++	}
++}
++
++static void
++dhdsdio_sdtest_set(dhd_bus_t *bus, uint count)
++{
++	void *pkt;
++	uint8 *data;
++	osl_t *osh = bus->dhd->osh;
++
++	/* Allocate the packet */
++	if (!(pkt = PKTGET(osh, SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
++		SDPCM_TEST_PKT_CNT_FLD_LEN + DHD_SDALIGN, TRUE))) {
++		DHD_ERROR(("%s: PKTGET failed!\n", __FUNCTION__));
++		return;
++	}
++	PKTALIGN(osh, pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
++		SDPCM_TEST_PKT_CNT_FLD_LEN), DHD_SDALIGN);
++	data = (uint8*)PKTDATA(osh, pkt) + SDPCM_HDRLEN;
++
++	/* Fill in the test header */
++	*data++ = SDPCM_TEST_SEND;
++	*data++ = (count > 0)?TRUE:FALSE;
++	*data++ = (bus->pktgen_maxlen >> 0);
++	*data++ = (bus->pktgen_maxlen >> 8);
++	*data++ = (uint8)(count >> 0);
++	*data++ = (uint8)(count >> 8);
++	*data++ = (uint8)(count >> 16);
++	*data++ = (uint8)(count >> 24);
++
++	/* Send it */
++	if (dhdsdio_txpkt(bus, SDPCM_TEST_CHANNEL, &pkt, 1, TRUE) != BCME_OK)
++		bus->pktgen_fail++;
++}
++
++
++static void
++dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq)
++{
++	osl_t *osh = bus->dhd->osh;
++	uint8 *data;
++	uint pktlen;
++
++	uint8 cmd;
++	uint8 extra;
++	uint16 len;
++	uint16 offset;
++
++	/* Check for min length */
++	if ((pktlen = PKTLEN(osh, pkt)) < SDPCM_TEST_HDRLEN) {
++		DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n", pktlen));
++		PKTFREE(osh, pkt, FALSE);
++		return;
++	}
++
++	/* Extract header fields */
++	data = PKTDATA(osh, pkt);
++	cmd = *data++;
++	extra = *data++;
++	len = *data++; len += *data++ << 8;
++	DHD_TRACE(("%s:cmd:%d, xtra:%d,len:%d\n", __FUNCTION__, cmd, extra, len));
++	/* Check length for relevant commands */
++	if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ || cmd == SDPCM_TEST_ECHORSP) {
++		if (pktlen != len + SDPCM_TEST_HDRLEN) {
++			DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, pktlen %d seq %d"
++			           " cmd %d extra %d len %d\n", pktlen, seq, cmd, extra, len));
++			PKTFREE(osh, pkt, FALSE);
++			return;
++		}
++	}
++
++	/* Process as per command */
++	switch (cmd) {
++	case SDPCM_TEST_ECHOREQ:
++		/* Rx->Tx turnaround ok (even on NDIS w/current implementation) */
++		*(uint8 *)(PKTDATA(osh, pkt)) = SDPCM_TEST_ECHORSP;
++		if (dhdsdio_txpkt(bus, SDPCM_TEST_CHANNEL, &pkt, 1, TRUE) == BCME_OK) {
++			bus->pktgen_sent++;
++		} else {
++			bus->pktgen_fail++;
++			PKTFREE(osh, pkt, FALSE);
++		}
++		bus->pktgen_rcvd++;
++		break;
++
++	case SDPCM_TEST_ECHORSP:
++		if (bus->ext_loop) {
++			PKTFREE(osh, pkt, FALSE);
++			bus->pktgen_rcvd++;
++			break;
++		}
++
++		for (offset = 0; offset < len; offset++, data++) {
++			if (*data != SDPCM_TEST_FILL(offset, extra)) {
++				DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: "
++				           "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
++				           offset, len, SDPCM_TEST_FILL(offset, extra), *data));
++				break;
++			}
++		}
++		PKTFREE(osh, pkt, FALSE);
++		bus->pktgen_rcvd++;
++		break;
++
++	case SDPCM_TEST_DISCARD:
++		{
++			int i = 0;
++			uint8 *prn = data;
++			uint8 testval = extra;
++			for (i = 0; i < len; i++) {
++				if (*prn != testval) {
++					DHD_ERROR(("DIErr@Pkt#:%d,Ix:%d, expected:0x%x, got:0x%x\n",
++						i, bus->pktgen_rcvd_rcvsession, testval, *prn));
++					prn++; testval++;
++				}
++			}
++		}
++		PKTFREE(osh, pkt, FALSE);
++		bus->pktgen_rcvd++;
++		break;
++
++	case SDPCM_TEST_BURST:
++	case SDPCM_TEST_SEND:
++	default:
++		DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, pktlen %d seq %d"
++		          " cmd %d extra %d len %d\n", pktlen, seq, cmd, extra, len));
++		PKTFREE(osh, pkt, FALSE);
++		break;
++	}
++
++	/* For recv mode, stop at limit (and tell dongle to stop sending) */
++	if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
++		if (bus->pktgen_rcv_state != PKTGEN_RCV_IDLE) {
++			bus->pktgen_rcvd_rcvsession++;
++
++			if (bus->pktgen_total &&
++				(bus->pktgen_rcvd_rcvsession >= bus->pktgen_total)) {
++			bus->pktgen_count = 0;
++			DHD_ERROR(("Pktgen:rcv test complete!\n"));
++			bus->pktgen_rcv_state = PKTGEN_RCV_IDLE;
++			dhdsdio_sdtest_set(bus, FALSE);
++				bus->pktgen_rcvd_rcvsession = 0;
++			}
++		}
++	}
++}
++#endif /* SDTEST */
++
++int dhd_bus_oob_intr_register(dhd_pub_t *dhdp)
++{
++	int err = 0;
++
++#if defined(OOB_INTR_ONLY)
++	err = bcmsdh_oob_intr_register(dhdp->bus->sdh, dhdsdio_isr, dhdp->bus);
++#endif
++	return err;
++}
++
++void dhd_bus_oob_intr_unregister(dhd_pub_t *dhdp)
++{
++#if defined(OOB_INTR_ONLY)
++	bcmsdh_oob_intr_unregister(dhdp->bus->sdh);
++#endif
++}
++
++void dhd_bus_oob_intr_set(dhd_pub_t *dhdp, bool enable)
++{
++#if defined(OOB_INTR_ONLY)
++	bcmsdh_oob_intr_set(dhdp->bus->sdh, enable);
++#endif
++}
++
++void dhd_bus_dev_pm_stay_awake(dhd_pub_t *dhdpub)
++{
++	bcmsdh_dev_pm_stay_awake(dhdpub->bus->sdh);
++}
++
++void dhd_bus_dev_pm_relax(dhd_pub_t *dhdpub)
++{
++	bcmsdh_dev_relax(dhdpub->bus->sdh);
++}
++
++bool dhd_bus_dev_pm_enabled(dhd_pub_t *dhdpub)
++{
++	bool enabled = FALSE;
++
++	enabled = bcmsdh_dev_pm_enabled(dhdpub->bus->sdh);
++	return enabled;
++}
++
++extern bool
++dhd_bus_watchdog(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus;
++	unsigned long flags;
++
++	DHD_TIMER(("%s: Enter\n", __FUNCTION__));
++
++	bus = dhdp->bus;
++
++	if (bus->dhd->dongle_reset)
++		return FALSE;
++
++	if (bus->dhd->hang_was_sent) {
++		dhd_os_wd_timer(bus->dhd, 0);
++		return FALSE;
++	}
++
++	/* Ignore the timer if simulating bus down */
++	if (!SLPAUTO_ENAB(bus) && bus->sleeping)
++		return FALSE;
++
++	DHD_LINUX_GENERAL_LOCK(dhdp, flags);
++	if (DHD_BUS_CHECK_DOWN_OR_DOWN_IN_PROGRESS(dhdp) ||
++			DHD_BUS_CHECK_SUSPEND_OR_SUSPEND_IN_PROGRESS(dhdp)) {
++		DHD_LINUX_GENERAL_UNLOCK(dhdp, flags);
++		return FALSE;
++	}
++	DHD_BUS_BUSY_SET_IN_WD(dhdp);
++	DHD_LINUX_GENERAL_UNLOCK(dhdp, flags);
++
++	dhd_os_sdlock(bus->dhd);
++
++	/* Poll period: check device if appropriate. */
++	// terence 20160615: remove !SLPAUTO_ENAB(bus) to fix not able to polling if sr supported
++	if (1 && (bus->poll && (++bus->polltick >= bus->pollrate))) {
++		uint32 intstatus = 0;
++
++		/* Reset poll tick */
++		bus->polltick = 0;
++
++		/* Check device if no interrupts */
++		if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
++
++			if (!bus->dpc_sched) {
++				uint8 devpend;
++				devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
++				                          SDIOD_CCCR_INTPEND, NULL);
++				intstatus = devpend & (INTR_STATUS_FUNC1 | INTR_STATUS_FUNC2);
++			}
++
++			/* If there is something, make like the ISR and schedule the DPC */
++			if (intstatus) {
++				bus->pollcnt++;
++				bus->ipend = TRUE;
++				if (bus->intr) {
++					bcmsdh_intr_disable(bus->sdh);
++				}
++				bus->dpc_sched = TRUE;
++				dhd_sched_dpc(bus->dhd);
++			}
++		}
++
++		/* Update interrupt tracking */
++		bus->lastintrs = bus->intrcount;
++	}
++
++	if ((!bus->dpc_sched) && pktq_len(&bus->txq)) {
++		bus->dpc_sched = TRUE;
++		dhd_sched_dpc(bus->dhd);
++	}
++
++#ifdef DHD_DEBUG
++	/* Poll for console output periodically */
++	if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
++		bus->console.count += dhd_watchdog_ms;
++		if (bus->console.count >= dhd_console_ms) {
++			bus->console.count -= dhd_console_ms;
++			/* Make sure backplane clock is on */
++			if (SLPAUTO_ENAB(bus))
++				dhdsdio_bussleep(bus, FALSE);
++			else
++			dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++			if (dhdsdio_readconsole(bus) < 0)
++				dhd_console_ms = 0;	/* On error, stop trying */
++		}
++	}
++#endif /* DHD_DEBUG */
++
++#ifdef SDTEST
++	/* Generate packets if configured */
++	if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
++		/* Make sure backplane clock is on */
++		if (SLPAUTO_ENAB(bus))
++			dhdsdio_bussleep(bus, FALSE);
++		else
++			dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++		bus->pktgen_tick = 0;
++		dhdsdio_pktgen(bus);
++	}
++#endif
++
++	/* On idle timeout clear activity flag and/or turn off clock */
++#ifdef DHD_USE_IDLECOUNT
++	if (bus->activity)
++		bus->activity = FALSE;
++	else {
++		bus->idlecount++;
++
++		/*
++		 * If the condition to switch off the clock is reached And if
++		 * BT is inactive (in case of BT_OVER_SDIO build) turn off clk.
++		 *
++		 * Consider the following case, DHD is configured with
++		 * 1) idletime == DHD_IDLE_IMMEDIATE
++		 * 2) BT is the last user of the clock
++		 * We cannot disable the clock from __dhdsdio_clk_disable
++		 * since WLAN might be using it. If WLAN is active then
++		 * from the respective function/context after doing the job
++		 * the clk is turned off.
++		 * But if WLAN is actually inactive then the watchdog should
++		 * disable the clock. So the condition check below should be
++		 * bus->idletime != 0 instead of idletime == 0
++		 */
++		if ((bus->idletime != 0) && (bus->idlecount >= bus->idletime) &&
++			NO_OTHER_ACTIVE_BUS_USER(bus)) {
++			DHD_TIMER(("%s: DHD Idle state!!\n", __FUNCTION__));
++			if (!bus->poll && SLPAUTO_ENAB(bus)) {
++				if (dhdsdio_bussleep(bus, TRUE) != BCME_BUSY)
++					dhd_os_wd_timer(bus->dhd, 0);
++			} else
++				dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++
++			bus->idlecount = 0;
++		}
++	}
++#else
++	if ((bus->idletime != 0) && (bus->clkstate == CLK_AVAIL) &&
++		NO_OTHER_ACTIVE_BUS_USER(bus)) {
++		if (++bus->idlecount >= bus->idletime) {
++			bus->idlecount = 0;
++			if (bus->activity) {
++				bus->activity = FALSE;
++				if (!bus->poll && SLPAUTO_ENAB(bus)) {
++					if (!bus->readframes)
++						dhdsdio_bussleep(bus, TRUE);
++					else
++						bus->reqbussleep = TRUE;
++				} else {
++					dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++				}
++			}
++		}
++	}
++#endif /* DHD_USE_IDLECOUNT */
++
++	dhd_os_sdunlock(bus->dhd);
++
++	DHD_LINUX_GENERAL_LOCK(dhdp, flags);
++	DHD_BUS_BUSY_CLEAR_IN_WD(dhdp);
++	dhd_os_busbusy_wake(dhdp);
++	DHD_LINUX_GENERAL_UNLOCK(dhdp, flags);
++
++	return bus->ipend;
++}
++
++extern int
++dhd_bus_console_in(dhd_pub_t *dhdp, uchar *msg, uint msglen)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	uint32 addr, val;
++	int rv;
++	void *pkt;
++
++#ifndef CONSOLE_DPC
++	/* Exclusive bus access */
++	dhd_os_sdlock(bus->dhd);
++#endif
++
++	/* Address could be zero if CONSOLE := 0 in dongle Makefile */
++	if (bus->console_addr == 0) {
++		rv = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++	/* Don't allow input if dongle is in reset */
++	if (bus->dhd->dongle_reset) {
++		rv = BCME_NOTREADY;
++		goto exit;
++	}
++
++#ifndef CONSOLE_DPC
++	if (!DATAOK(bus)) {
++		DHD_CTL(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d, pktq_len %d\n",
++			__FUNCTION__, bus->tx_max, bus->tx_seq, pktq_len(&bus->txq)));
++		rv = BCME_NOTREADY;
++		goto exit;
++	}
++
++	/* Request clock to allow SDIO accesses */
++	BUS_WAKE(bus);
++	/* No pend allowed since txpkt is called later, ht clk has to be on */
++	dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++#endif
++
++	/* Zero cbuf_index */
++	addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf_idx);
++	val = htol32(0);
++	if ((rv = dhdsdio_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0)
++		goto done;
++
++	/* Write message into cbuf */
++	addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf);
++	if ((rv = dhdsdio_membytes(bus, TRUE, addr, (uint8 *)msg, msglen)) < 0)
++		goto done;
++
++	/* Write length into vcons_in */
++	addr = bus->console_addr + OFFSETOF(hnd_cons_t, vcons_in);
++	val = htol32(msglen);
++	if ((rv = dhdsdio_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0)
++		goto done;
++
++	/* Bump dongle by sending an empty packet on the event channel.
++	 * sdpcm_sendup (RX) checks for virtual console input.
++	 */
++	if ((pkt = PKTGET(bus->dhd->osh, 4 + SDPCM_RESERVE, TRUE)) != NULL)
++		rv = dhdsdio_txpkt(bus, SDPCM_EVENT_CHANNEL, &pkt, 1, TRUE);
++
++done:
++#ifndef CONSOLE_DPC
++	if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched &&
++		NO_OTHER_ACTIVE_BUS_USER(bus)) {
++		bus->activity = FALSE;
++		dhdsdio_bussleep(bus, TRUE);
++		dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++	}
++#endif
++
++exit:
++#ifdef CONSOLE_DPC
++	memset(bus->cons_cmd, 0, sizeof(bus->cons_cmd));
++#else
++	dhd_os_sdunlock(bus->dhd);
++#endif
++	return rv;
++}
++
++#ifdef CONSOLE_DPC
++extern int
++dhd_bus_txcons(dhd_pub_t *dhdp, uchar *msg, uint msglen)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	int ret = BCME_OK;
++
++	dhd_os_sdlock(bus->dhd);
++
++	/* Address could be zero if CONSOLE := 0 in dongle Makefile */
++	if (bus->console_addr == 0) {
++		ret = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++	/* Don't allow input if dongle is in reset */
++	if (bus->dhd->dongle_reset) {
++		ret = BCME_NOTREADY;
++		goto exit;
++	}
++
++	if (msglen >= sizeof(bus->cons_cmd)) {
++		DHD_ERROR(("%s: \"%s\"(%d) too long\n", __FUNCTION__, msg, msglen));
++		ret = BCME_BADARG;
++		goto exit;
++	}
++
++	if (!strlen(bus->cons_cmd)) {
++		strncpy(bus->cons_cmd, msg, sizeof(bus->cons_cmd));
++		DHD_CTL(("%s: \"%s\" delay send, tx_max %d, tx_seq %d, pktq_len %d\n",
++			__FUNCTION__, bus->cons_cmd, bus->tx_max, bus->tx_seq, pktq_len(&bus->txq)));
++		if (!bus->dpc_sched) {
++			bus->dpc_sched = TRUE;
++			dhd_sched_dpc(bus->dhd);
++		}
++	} else {
++		DHD_CTL(("%s: \"%s\" is pending, tx_max %d, tx_seq %d, pktq_len %d\n",
++			__FUNCTION__, bus->cons_cmd, bus->tx_max, bus->tx_seq, pktq_len(&bus->txq)));
++		ret = BCME_NOTREADY;
++	}
++
++exit:
++	dhd_os_sdunlock(bus->dhd);
++
++	return ret;
++}
++#endif
++
++#ifdef DHD_DEBUG
++static void
++dhd_dump_cis(uint fn, uint8 *cis)
++{
++	uint byte, tag, tdata;
++	DHD_INFO(("Function %d CIS:\n", fn));
++
++	for (tdata = byte = 0; byte < SBSDIO_CIS_SIZE_LIMIT; byte++) {
++		if ((byte % 16) == 0)
++			DHD_INFO(("    "));
++		DHD_INFO(("%02x ", cis[byte]));
++		if ((byte % 16) == 15)
++			DHD_INFO(("\n"));
++		if (!tdata--) {
++			tag = cis[byte];
++			if (tag == 0xff)
++				break;
++			else if (!tag)
++				tdata = 0;
++			else if ((byte + 1) < SBSDIO_CIS_SIZE_LIMIT)
++				tdata = cis[byte + 1] + 1;
++			else
++				DHD_INFO(("]"));
++		}
++	}
++	if ((byte % 16) != 15)
++		DHD_INFO(("\n"));
++}
++#endif /* DHD_DEBUG */
++
++static bool
++dhdsdio_chipmatch(uint16 chipid)
++{
++	if (chipid == BCM4336_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4330_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43237_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43362_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4314_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43242_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43340_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43341_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43143_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43342_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4334_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43239_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4324_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4335_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4339_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43349_CHIP_ID)
++		return TRUE;
++	if (BCM4345_CHIP(chipid))
++		return TRUE;
++	if (chipid == BCM4350_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4354_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4358_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43569_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4371_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43430_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43018_CHIP_ID)
++		return TRUE;
++	if (BCM4349_CHIP(chipid))
++		return TRUE;
++	if (BCM4347_CHIP(chipid))
++		return TRUE;
++	if (chipid == BCM4364_CHIP_ID)
++			return TRUE;
++
++	if (chipid == BCM43012_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4362_CHIP_ID)
++		return TRUE;
++
++	return FALSE;
++}
++
++static void *
++dhdsdio_probe(uint16 venid, uint16 devid, uint16 bus_no, uint16 slot,
++	uint16 func, uint bustype, void *regsva, osl_t * osh, void *sdh)
++{
++	int ret;
++	dhd_bus_t *bus;
++
++	DHD_MUTEX_LOCK();
++
++	/* Init global variables at run-time, not as part of the declaration.
++	 * This is required to support init/de-init of the driver. Initialization
++	 * of globals as part of the declaration results in non-deterministic
++	 * behavior since the value of the globals may be different on the
++	 * first time that the driver is initialized vs subsequent initializations.
++	 */
++	dhd_txbound = DHD_TXBOUND;
++	dhd_rxbound = DHD_RXBOUND;
++	dhd_alignctl = TRUE;
++	sd1idle = TRUE;
++	dhd_readahead = TRUE;
++	retrydata = FALSE;
++
++#ifdef DISABLE_FLOW_CONTROL
++	dhd_doflow = FALSE;
++#endif /* DISABLE_FLOW_CONTROL */
++	dhd_dongle_ramsize = 0;
++	dhd_txminmax = DHD_TXMINMAX;
++
++	forcealign = TRUE;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++	DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __FUNCTION__, venid, devid));
++
++	/* We make assumptions about address window mappings */
++	ASSERT((uintptr)regsva == SI_ENUM_BASE);
++
++	/* BCMSDH passes venid and devid based on CIS parsing -- but low-power start
++	 * means early parse could fail, so here we should get either an ID
++	 * we recognize OR (-1) indicating we must request power first.
++	 */
++	/* Check the Vendor ID */
++	switch (venid) {
++		case 0x0000:
++		case VENDOR_BROADCOM:
++			break;
++		default:
++			DHD_ERROR(("%s: unknown vendor: 0x%04x\n",
++			           __FUNCTION__, venid));
++			goto forcereturn;
++	}
++
++	/* Check the Device ID and make sure it's one that we support */
++	switch (devid) {
++		case 0:
++			DHD_INFO(("%s: allow device id 0, will check chip internals\n",
++			          __FUNCTION__));
++			break;
++
++		default:
++			DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
++			           __FUNCTION__, venid, devid));
++			goto forcereturn;
++	}
++
++	if (osh == NULL) {
++		DHD_ERROR(("%s: osh is NULL!\n", __FUNCTION__));
++		goto forcereturn;
++	}
++
++	/* Allocate private bus interface state */
++	if (!(bus = MALLOC(osh, sizeof(dhd_bus_t)))) {
++		DHD_ERROR(("%s: MALLOC of dhd_bus_t failed\n", __FUNCTION__));
++		goto fail;
++	}
++	bzero(bus, sizeof(dhd_bus_t));
++	bus->sdh = sdh;
++	bus->cl_devid = (uint16)devid;
++	bus->bus = DHD_BUS;
++	bus->bus_num = bus_no;
++	bus->slot_num = slot;
++	bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
++	bus->usebufpool = FALSE; /* Use bufpool if allocated, else use locally malloced rxbuf */
++#ifdef BT_OVER_SDIO
++	bus->bt_use_count = 0;
++#endif
++
++#if defined(SUPPORT_P2P_GO_PS)
++	init_waitqueue_head(&bus->bus_sleep);
++#endif /* LINUX && SUPPORT_P2P_GO_PS */
++	init_waitqueue_head(&bus->ctrl_tx_wait);
++
++	/* attempt to attach to the dongle */
++	if (!(dhdsdio_probe_attach(bus, osh, sdh, regsva, devid))) {
++		DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __FUNCTION__));
++		goto fail;
++	}
++
++	/* Attach to the dhd/OS/network interface */
++	if (!(bus->dhd = dhd_attach(osh, bus, SDPCM_RESERVE))) {
++		DHD_ERROR(("%s: dhd_attach failed\n", __FUNCTION__));
++		goto fail;
++	}
++#if defined(BT_OVER_SDIO)
++	g_dhd_pub = bus->dhd;
++	DHD_ERROR(("%s: g_dhd_pub %p\n", __FUNCTION__, g_dhd_pub));
++#endif /* defined (BT_OVER_SDIO) */
++
++#if defined(GET_OTP_MAC_ENABLE) || defined(GET_OTP_MODULE_NAME)
++	dhd_conf_get_otp(bus->dhd, sdh);
++#endif
++
++	/* Allocate buffers */
++	if (!(dhdsdio_probe_malloc(bus, osh, sdh))) {
++		DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __FUNCTION__));
++		goto fail;
++	}
++
++	if (!(dhdsdio_probe_init(bus, osh, sdh))) {
++		DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __FUNCTION__));
++		goto fail;
++	}
++
++	if (bus->intr) {
++		/* Register interrupt callback, but mask it (not operational yet). */
++		DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n", __FUNCTION__));
++		bcmsdh_intr_disable(sdh);
++		if ((ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus)) != 0) {
++			DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
++			           __FUNCTION__, ret));
++			goto fail;
++		}
++		DHD_INTR(("%s: registered SDIO interrupt function ok\n", __FUNCTION__));
++	} else {
++		DHD_INFO(("%s: SDIO interrupt function is NOT registered due to polling mode\n",
++		           __FUNCTION__));
++	}
++
++	DHD_INFO(("%s: completed!!\n", __FUNCTION__));
++
++	/* if firmware path present try to download and bring up bus */
++	bus->dhd->hang_report  = TRUE;
++#if 0 // terence 20150325: fix for WPA/WPA2 4-way handshake fail in hostapd
++	if (dhd_download_fw_on_driverload) {
++		if ((ret = dhd_bus_start(bus->dhd)) != 0) {
++			DHD_ERROR(("%s: dhd_bus_start failed\n", __FUNCTION__));
++				goto fail;
++		}
++	}
++	else {
++		/* Set random MAC address during boot time */
++		get_random_bytes(&bus->dhd->mac.octet[3], 3);
++		/* Adding BRCM OUI */
++		bus->dhd->mac.octet[0] = 0;
++		bus->dhd->mac.octet[1] = 0x90;
++		bus->dhd->mac.octet[2] = 0x4C;
++	}
++#endif
++#if defined(BT_OVER_SDIO)
++	/* At this point Regulators are turned on and iconditionaly sdio bus is started
++	 * based upon dhd_download_fw_on_driverload check, so
++	 * increase the bus user count, this count will only be disabled inside
++	 * dhd_register_if() function if flag dhd_download_fw_on_driverload is set to false,
++	 * i.e FW download during insmod is not needed, otherwise it will not be decremented
++	 * so that WALN will always hold the bus untill rmmod is done.
++	 */
++	dhdsdio_bus_usr_cnt_inc(bus->dhd);
++#endif /* BT_OVER_SDIO */
++
++#ifdef GET_OTP_MAC_ENABLE
++	if (memcmp(&ether_null, &bus->dhd->conf->otp_mac, ETHER_ADDR_LEN))
++		memcpy(bus->dhd->mac.octet, (void *)&bus->dhd->conf->otp_mac, ETHER_ADDR_LEN);
++#endif /* GET_CUSTOM_MAC_ENABLE */
++
++	/* Ok, have the per-port tell the stack we're open for business */
++	if (dhd_register_if(bus->dhd, 0, TRUE) != 0) {
++		DHD_ERROR(("%s: Net attach failed!!\n", __FUNCTION__));
++		goto fail;
++	}
++
++#ifdef BCMHOST_XTAL_PU_TIME_MOD
++	bcmsdh_reg_write(bus->sdh, 0x18000620, 2, 11);
++#ifdef BCM4330_CHIP
++	bcmsdh_reg_write(bus->sdh, 0x18000628, 4, 0x0000F801);
++#else
++	bcmsdh_reg_write(bus->sdh, 0x18000628, 4, 0x00F80001);
++#endif /* BCM4330_CHIP */
++#endif /* BCMHOST_XTAL_PU_TIME_MOD */
++
++#if defined(MULTIPLE_SUPPLICANT)
++	wl_android_post_init(); // terence 20120530: fix critical section in dhd_open and dhdsdio_probe
++#endif /* MULTIPLE_SUPPLICANT */
++	DHD_MUTEX_UNLOCK();
++
++	return bus;
++
++fail:
++	dhdsdio_release(bus, osh);
++
++forcereturn:
++	DHD_MUTEX_UNLOCK();
++
++	return NULL;
++}
++
++static bool
++dhdsdio_probe_attach(struct dhd_bus *bus, osl_t *osh, void *sdh, void *regsva,
++                     uint16 devid)
++{
++	uint8 clkctl = 0;
++	uint fn, numfn;
++	uint8 *cis[SDIOD_MAX_IOFUNCS];
++	int err = 0;
++
++
++	bus->alp_only = TRUE;
++	bus->sih = NULL;
++
++	/* Return the window to backplane enumeration space for core access */
++	if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE)) {
++		DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __FUNCTION__));
++	}
++
++#if defined(DHD_DEBUG) && !defined(CUSTOMER_HW4_DEBUG)
++	DHD_ERROR(("F1 signature read @0x18000000=0x%4x\n",
++		bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4)));
++#endif /* DHD_DEBUG && !CUSTOMER_HW4_DEBUG */
++
++
++	/* Force PLL off until si_attach() programs PLL control regs */
++
++
++
++	bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, DHD_INIT_CLKCTL1, &err);
++	if (!err)
++		clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
++
++	if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
++		DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
++		           err, DHD_INIT_CLKCTL1, clkctl));
++		goto fail;
++	}
++	numfn = bcmsdh_query_iofnum(sdh);
++	ASSERT(numfn <= SDIOD_MAX_IOFUNCS);
++
++	/* Make sure ALP is available before trying to read CIS */
++	SPINWAIT(((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
++	                                    SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
++	          !SBSDIO_ALPAV(clkctl)), PMU_MAX_TRANSITION_DLY);
++
++	/* Now request ALP be put on the bus */
++	bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
++	                 DHD_INIT_CLKCTL2, &err);
++	OSL_DELAY(200);
++
++	if (DHD_INFO_ON()) {
++		for (fn = 0; fn <= numfn; fn++) {
++			if (!(cis[fn] = MALLOC(osh, SBSDIO_CIS_SIZE_LIMIT))) {
++				DHD_INFO(("dhdsdio_probe: fn %d cis malloc failed\n", fn));
++				break;
++			}
++			bzero(cis[fn], SBSDIO_CIS_SIZE_LIMIT);
++
++			if ((err = bcmsdh_cis_read(sdh, fn, cis[fn],
++			                                 SBSDIO_CIS_SIZE_LIMIT))) {
++				DHD_INFO(("dhdsdio_probe: fn %d cis read err %d\n", fn, err));
++				MFREE(osh, cis[fn], SBSDIO_CIS_SIZE_LIMIT);
++				break;
++			}
++#if 0
++		/* Reading the F1, F2 and F3 max blocksize values from CIS
++		  * and writing into the F1, F2 and F3	block size registers.
++		  * There is no max block size register value available for F0 in CIS register.
++		  * So, setting default value for F0 block size as 32 (which was set earlier
++		  * in iovar). IOVAR takes only one arguement.
++		  * So, we are passing the function number alongwith the value (fn<<16)
++		*/
++			if (!fn)
++				value = F0_BLOCK_SIZE;
++			else
++				value = (cis[fn][25]<<8) | cis[fn][24] | (fn<<16);
++			printf("%s: fn=%d, value=%d\n", __FUNCTION__, fn, value);
++			if (bcmsdh_iovar_op(sdh, "sd_blocksize", NULL, 0, &value,
++				sizeof(value), TRUE) != BCME_OK) {
++				bus->blocksize = 0;
++				DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__,
++					"sd_blocksize"));
++			}
++#endif
++#ifdef DHD_DEBUG
++			if (DHD_INFO_ON()) {
++				dhd_dump_cis(fn, cis[fn]);
++			}
++#endif /* DHD_DEBUG */
++		}
++		while (fn-- > 0) {
++			ASSERT(cis[fn]);
++			MFREE(osh, cis[fn], SBSDIO_CIS_SIZE_LIMIT);
++		}
++	}
++#if 0
++	if (dhd_conf_set_blksize(sdh)) {
++		bus->blocksize = 0;
++	}
++#endif
++	if (err) {
++		DHD_ERROR(("dhdsdio_probe: failure reading or parsing CIS\n"));
++		goto fail;
++	}
++	/* si_attach() will provide an SI handle and scan the backplane */
++	if (!(bus->sih = si_attach((uint)devid, osh, regsva, DHD_BUS, sdh,
++	                           &bus->vars, &bus->varsz))) {
++		DHD_ERROR(("%s: si_attach failed!\n", __FUNCTION__));
++		goto fail;
++	}
++
++#ifdef DHD_DEBUG
++	DHD_ERROR(("F1 signature OK, socitype:0x%x chip:0x%4x rev:0x%x pkg:0x%x\n",
++		bus->sih->socitype, bus->sih->chip, bus->sih->chiprev, bus->sih->chippkg));
++#endif /* DHD_DEBUG */
++
++
++	bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev);
++
++	if (!dhdsdio_chipmatch((uint16)bus->sih->chip)) {
++		DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
++		           __FUNCTION__, bus->sih->chip));
++		goto fail;
++	}
++
++	if (bus->sih->buscorerev >= 12)
++		dhdsdio_clk_kso_init(bus);
++	else
++		bus->kso = TRUE;
++
++	if (CST4330_CHIPMODE_SDIOD(bus->sih->chipst)) {
++	}
++
++	si_sdiod_drive_strength_init(bus->sih, osh, dhd_sdiod_drive_strength);
++
++
++	/* Get info on the ARM and SOCRAM cores... */
++	if (!DHD_NOPMU(bus)) {
++		if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
++		    (si_setcore(bus->sih, ARMCM3_CORE_ID, 0)) ||
++		    (si_setcore(bus->sih, ARMCR4_CORE_ID, 0))) {
++			bus->armrev = si_corerev(bus->sih);
++		} else {
++			DHD_ERROR(("%s: failed to find ARM core!\n", __FUNCTION__));
++			goto fail;
++		}
++
++		if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
++			if (!(bus->orig_ramsize = si_socram_size(bus->sih))) {
++				DHD_ERROR(("%s: failed to find SOCRAM memory!\n", __FUNCTION__));
++				goto fail;
++			}
++		} else {
++			/* cr4 has a different way to find the RAM size from TCM's */
++			if (!(bus->orig_ramsize = si_tcm_size(bus->sih))) {
++				DHD_ERROR(("%s: failed to find CR4-TCM memory!\n", __FUNCTION__));
++				goto fail;
++			}
++			/* also populate base address */
++			switch ((uint16)bus->sih->chip) {
++			case BCM4335_CHIP_ID:
++			case BCM4339_CHIP_ID:
++			case BCM43349_CHIP_ID:
++				bus->dongle_ram_base = CR4_4335_RAM_BASE;
++				break;
++			case BCM4350_CHIP_ID:
++			case BCM4354_CHIP_ID:
++			case BCM4358_CHIP_ID:
++			case BCM43569_CHIP_ID:
++			case BCM4371_CHIP_ID:
++				bus->dongle_ram_base = CR4_4350_RAM_BASE;
++				break;
++			case BCM4360_CHIP_ID:
++				bus->dongle_ram_base = CR4_4360_RAM_BASE;
++				break;
++			CASE_BCM4345_CHIP:
++				bus->dongle_ram_base = (bus->sih->chiprev < 6)  /* from 4345C0 */
++					? CR4_4345_LT_C0_RAM_BASE : CR4_4345_GE_C0_RAM_BASE;
++				break;
++			case BCM4349_CHIP_GRPID:
++				/* RAM based changed from 4349c0(revid=9) onwards */
++				bus->dongle_ram_base = ((bus->sih->chiprev < 9) ?
++					CR4_4349_RAM_BASE: CR4_4349_RAM_BASE_FROM_REV_9);
++				break;
++			case BCM4364_CHIP_ID:
++				bus->dongle_ram_base = CR4_4364_RAM_BASE;
++				break;
++			case BCM4347_CHIP_GRPID:
++				bus->dongle_ram_base = CR4_4347_RAM_BASE;
++				break;
++			case BCM4362_CHIP_ID:
++				bus->dongle_ram_base = CR4_4362_RAM_BASE;
++				break;
++			default:
++				bus->dongle_ram_base = 0;
++				DHD_ERROR(("%s: WARNING: Using default ram base at 0x%x\n",
++				           __FUNCTION__, bus->dongle_ram_base));
++			}
++		}
++		bus->ramsize = bus->orig_ramsize;
++		if (dhd_dongle_ramsize)
++			dhd_dongle_setramsize(bus, dhd_dongle_ramsize);
++
++		DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d) at 0x%x\n",
++		           bus->ramsize, bus->orig_ramsize, bus->dongle_ram_base));
++
++		bus->srmemsize = si_socram_srmem_size(bus->sih);
++	}
++
++	/* ...but normally deal with the SDPCMDEV core */
++	if (!(bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0)) &&
++	    !(bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0))) {
++		DHD_ERROR(("%s: failed to find SDIODEV core!\n", __FUNCTION__));
++		goto fail;
++	}
++	bus->sdpcmrev = si_corerev(bus->sih);
++
++	/* Set core control so an SDIO reset does a backplane reset */
++	OR_REG(osh, &bus->regs->corecontrol, CC_BPRESEN);
++	bus->rxint_mode = SDIO_DEVICE_HMB_RXINT;
++
++	if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev >= 4) &&
++		(bus->rxint_mode  == SDIO_DEVICE_RXDATAINT_MODE_1))
++	{
++		uint32 val;
++
++		val = R_REG(osh, &bus->regs->corecontrol);
++		val &= ~CC_XMTDATAAVAIL_MODE;
++		val |= CC_XMTDATAAVAIL_CTRL;
++		W_REG(osh, &bus->regs->corecontrol, val);
++	}
++
++
++	pktq_init(&bus->txq, (PRIOMASK + 1), QLEN);
++
++	/* Locate an appropriately-aligned portion of hdrbuf */
++	bus->rxhdr = (uint8 *)ROUNDUP((uintptr)&bus->hdrbuf[0], DHD_SDALIGN);
++
++	/* Set the poll and/or interrupt flags */
++	bus->intr = (bool)dhd_intr;
++	if ((bus->poll = (bool)dhd_poll))
++		bus->pollrate = 1;
++
++	/* Setting default Glom size */
++	bus->txglomsize = SDPCM_DEFGLOM_SIZE;
++
++	return TRUE;
++
++fail:
++	if (bus->sih != NULL) {
++		si_detach(bus->sih);
++		bus->sih = NULL;
++	}
++	return FALSE;
++}
++
++static bool
++dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh)
++{
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus->dhd->maxctl) {
++		bus->rxblen = ROUNDUP((bus->dhd->maxctl+SDPCM_HDRLEN), ALIGNMENT) + DHD_SDALIGN;
++		if (!(bus->rxbuf = DHD_OS_PREALLOC(bus->dhd, DHD_PREALLOC_RXBUF, bus->rxblen))) {
++			DHD_ERROR(("%s: MALLOC of %d-byte rxbuf failed\n",
++			           __FUNCTION__, bus->rxblen));
++			goto fail;
++		}
++	}
++	/* Allocate buffer to receive glomed packet */
++	if (!(bus->databuf = DHD_OS_PREALLOC(bus->dhd, DHD_PREALLOC_DATABUF, MAX_DATA_BUF))) {
++		DHD_ERROR(("%s: MALLOC of %d-byte databuf failed\n",
++			__FUNCTION__, MAX_DATA_BUF));
++		/* release rxbuf which was already located as above */
++		if (!bus->rxblen)
++			DHD_OS_PREFREE(bus->dhd, bus->rxbuf, bus->rxblen);
++		goto fail;
++	}
++	/* Allocate buffer to membuf */
++	bus->membuf = MALLOC(osh, MAX_MEM_BUF);
++	if (bus->membuf == NULL) {
++		DHD_ERROR(("%s: MALLOC of %d-byte membuf failed\n",
++			__FUNCTION__, MAX_MEM_BUF));
++		if (bus->databuf) {
++#ifndef CONFIG_DHD_USE_STATIC_BUF
++			MFREE(osh, bus->databuf, MAX_DATA_BUF);
++#endif
++			bus->databuf = NULL;
++		}
++		/* release rxbuf which was already located as above */
++		if (!bus->rxblen)
++			DHD_OS_PREFREE(bus->dhd, bus->rxbuf, bus->rxblen);
++		goto fail;
++	}
++	memset(bus->membuf, 0, MAX_MEM_BUF);
++
++	/* Align the buffer */
++	if ((uintptr)bus->databuf % DHD_SDALIGN)
++		bus->dataptr = bus->databuf + (DHD_SDALIGN - ((uintptr)bus->databuf % DHD_SDALIGN));
++	else
++		bus->dataptr = bus->databuf;
++
++	return TRUE;
++
++fail:
++	return FALSE;
++}
++
++static bool
++dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh)
++{
++	int32 fnum;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	bus->_srenab = FALSE;
++
++#ifdef SDTEST
++	dhdsdio_pktgen_init(bus);
++#endif /* SDTEST */
++
++	/* set PMU minimum resource mask to default */
++	dhd_bus_set_default_min_res_mask(bus);
++	/* Disable F2 to clear any intermediate frame state on the dongle */
++	bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1, NULL);
++
++	bus->dhd->busstate = DHD_BUS_DOWN;
++	bus->sleeping = FALSE;
++	bus->rxflow = FALSE;
++	bus->prev_rxlim_hit = 0;
++
++	/* Done with backplane-dependent accesses, can drop clock... */
++	bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
++
++	/* ...and initialize clock/power states */
++	bus->clkstate = CLK_SDONLY;
++	bus->idletime = (int32)dhd_idletime;
++	bus->idleclock = DHD_IDLE_ACTIVE;
++
++	/* Query the SD clock speed */
++	if (bcmsdh_iovar_op(sdh, "sd_divisor", NULL, 0,
++	                    &bus->sd_divisor, sizeof(int32), FALSE) != BCME_OK) {
++		DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_divisor"));
++		bus->sd_divisor = -1;
++	} else {
++		DHD_INFO(("%s: Initial value for %s is %d\n",
++		          __FUNCTION__, "sd_divisor", bus->sd_divisor));
++	}
++
++	/* Query the SD bus mode */
++	if (bcmsdh_iovar_op(sdh, "sd_mode", NULL, 0,
++	                    &bus->sd_mode, sizeof(int32), FALSE) != BCME_OK) {
++		DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_mode"));
++		bus->sd_mode = -1;
++	} else {
++		DHD_INFO(("%s: Initial value for %s is %d\n",
++		          __FUNCTION__, "sd_mode", bus->sd_mode));
++	}
++
++	/* Query the F2 block size, set roundup accordingly */
++	fnum = 2;
++	if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(int32),
++	                    &bus->blocksize, sizeof(int32), FALSE) != BCME_OK) {
++		bus->blocksize = 0;
++		DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_blocksize"));
++	} else {
++		DHD_INFO(("%s: Initial value for %s is %d\n",
++		          __FUNCTION__, "sd_blocksize", bus->blocksize));
++
++		dhdsdio_tune_fifoparam(bus);
++	}
++	bus->roundup = MIN(max_roundup, bus->blocksize);
++
++#ifdef DHDENABLE_TAILPAD
++	if (bus->pad_pkt)
++		PKTFREE(osh, bus->pad_pkt, FALSE);
++	bus->pad_pkt = PKTGET(osh, SDIO_MAX_BLOCK_SIZE, FALSE);
++	if (bus->pad_pkt == NULL)
++		DHD_ERROR(("failed to allocate padding packet\n"));
++	else {
++		int alignment_offset = 0;
++		uintptr pktprt = (uintptr)PKTDATA(osh, bus->pad_pkt);
++		if (!(pktprt&1) && (pktprt = (pktprt % DHD_SDALIGN)))
++			PKTPUSH(osh, bus->pad_pkt, alignment_offset);
++		PKTSETNEXT(osh, bus->pad_pkt, NULL);
++	}
++#endif /* DHDENABLE_TAILPAD */
++
++	/* Query if bus module supports packet chaining, default to use if supported */
++	if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
++	                    &bus->sd_rxchain, sizeof(int32), FALSE) != BCME_OK) {
++		bus->sd_rxchain = FALSE;
++	} else {
++		DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
++		          __FUNCTION__, (bus->sd_rxchain ? "supports" : "does not support")));
++	}
++	bus->use_rxchain = (bool)bus->sd_rxchain;
++	bus->txinrx_thres = CUSTOM_TXINRX_THRES;
++	/* TX first in dhdsdio_readframes() */
++	bus->dotxinrx = TRUE;
++
++#ifdef PKT_STATICS
++	memset((uint8*) &tx_statics, 0, sizeof(pkt_statics_t));
++#endif
++
++	return TRUE;
++}
++
++int
++dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh,
++                          char *pfw_path, char *pnv_path,
++                          char *pclm_path, char *pconf_path)
++{
++	int ret;
++
++	bus->fw_path = pfw_path;
++	bus->nv_path = pnv_path;
++	bus->dhd->clm_path = pclm_path;
++	bus->dhd->conf_path = pconf_path;
++
++	ret = dhdsdio_download_firmware(bus, osh, bus->sdh);
++
++	return ret;
++}
++
++void
++dhd_set_bus_params(struct dhd_bus *bus)
++{
++	if (bus->dhd->conf->dhd_poll >= 0) {
++		bus->poll = bus->dhd->conf->dhd_poll;
++		if (!bus->pollrate)
++			bus->pollrate = 1;
++		printf("%s: set polling mode %d\n", __FUNCTION__, bus->dhd->conf->dhd_poll);
++	}
++	if (bus->dhd->conf->use_rxchain >= 0) {
++		bus->use_rxchain = (bool)bus->dhd->conf->use_rxchain;
++	}
++	if (bus->dhd->conf->txinrx_thres >= 0) {
++		bus->txinrx_thres = bus->dhd->conf->txinrx_thres;
++	}
++	if (bus->dhd->conf->txglomsize >= 0) {
++		bus->txglomsize = bus->dhd->conf->txglomsize;
++	}
++}
++
++static int
++dhdsdio_download_firmware(struct dhd_bus *bus, osl_t *osh, void *sdh)
++{
++	int ret;
++
++
++#if defined(DHD_BLOB_EXISTENCE_CHECK)
++	dhd_set_blob_support(bus->dhd, bus->fw_path);
++#endif /* DHD_BLOB_EXISTENCE_CHECK */
++
++	DHD_TRACE_HW4(("%s: firmware path=%s, nvram path=%s\n",
++		__FUNCTION__, bus->fw_path, bus->nv_path));
++	DHD_OS_WAKE_LOCK(bus->dhd);
++
++	dhd_conf_set_path_params(bus->dhd, bus->fw_path, bus->nv_path);
++	dhd_set_bus_params(bus);
++
++	/* Download the firmware */
++	dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++	ret = _dhdsdio_download_firmware(bus);
++
++	dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++
++	DHD_OS_WAKE_UNLOCK(bus->dhd);
++	return ret;
++}
++
++/* Detach and free everything */
++static void
++dhdsdio_release(dhd_bus_t *bus, osl_t *osh)
++{
++	bool dongle_isolation = FALSE;
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus) {
++		ASSERT(osh);
++
++		if (bus->dhd) {
++			dongle_isolation = bus->dhd->dongle_isolation;
++			dhd_detach(bus->dhd);
++		}
++
++		/* De-register interrupt handler */
++		bcmsdh_intr_disable(bus->sdh);
++		bcmsdh_intr_dereg(bus->sdh);
++
++		if (bus->dhd) {
++			dhdsdio_release_dongle(bus, osh, dongle_isolation, TRUE);
++			dhd_free(bus->dhd);
++			bus->dhd = NULL;
++		}
++
++		dhdsdio_release_malloc(bus, osh);
++
++#ifdef DHD_DEBUG
++		if (bus->console.buf != NULL)
++			MFREE(osh, bus->console.buf, bus->console.bufsize);
++#endif
++
++#ifdef DHDENABLE_TAILPAD
++		if (bus->pad_pkt)
++			PKTFREE(osh, bus->pad_pkt, FALSE);
++#endif /* DHDENABLE_TAILPAD */
++
++		MFREE(osh, bus, sizeof(dhd_bus_t));
++	}
++
++	DHD_TRACE(("%s: Disconnected\n", __FUNCTION__));
++}
++
++static void
++dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh)
++{
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus->dhd && bus->dhd->dongle_reset)
++		return;
++
++	if (bus->rxbuf) {
++#ifndef CONFIG_DHD_USE_STATIC_BUF
++		MFREE(osh, bus->rxbuf, bus->rxblen);
++#endif
++		bus->rxctl = bus->rxbuf = NULL;
++		bus->rxlen = 0;
++	}
++
++	if (bus->databuf) {
++#ifndef CONFIG_DHD_USE_STATIC_BUF
++		MFREE(osh, bus->databuf, MAX_DATA_BUF);
++#endif
++		bus->databuf = NULL;
++	}
++
++	if (bus->membuf) {
++		MFREE(osh, bus->membuf, MAX_DATA_BUF);
++		bus->membuf = NULL;
++	}
++
++	if (bus->vars && bus->varsz) {
++		MFREE(osh, bus->vars, bus->varsz);
++		bus->vars = NULL;
++	}
++
++}
++
++
++static void
++dhdsdio_release_dongle(dhd_bus_t *bus, osl_t *osh, bool dongle_isolation, bool reset_flag)
++{
++	DHD_TRACE(("%s: Enter bus->dhd %p bus->dhd->dongle_reset %d \n", __FUNCTION__,
++		bus->dhd, bus->dhd->dongle_reset));
++
++	if ((bus->dhd && bus->dhd->dongle_reset) && reset_flag)
++		return;
++
++	if (bus->sih) {
++		/* In Win10, system will be BSOD if using "sysprep" to do OS image */
++		/* Skip this will not cause the BSOD. */
++#if !defined(BCMLXSDMMC)
++		if (bus->dhd) {
++			dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++		}
++		if (KSO_ENAB(bus) && (dongle_isolation == FALSE))
++			si_watchdog(bus->sih, 4);
++#endif /* !defined(BCMLXSDMMC) */
++		if (bus->dhd) {
++			dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++		}
++		si_detach(bus->sih);
++		bus->sih = NULL;
++		if (bus->vars && bus->varsz)
++			MFREE(osh, bus->vars, bus->varsz);
++		bus->vars = NULL;
++	}
++
++	DHD_TRACE(("%s: Disconnected\n", __FUNCTION__));
++}
++
++static void
++dhdsdio_disconnect(void *ptr)
++{
++	dhd_bus_t *bus = (dhd_bus_t *)ptr;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	DHD_MUTEX_LOCK();
++	if (bus) {
++		ASSERT(bus->dhd);
++		/* Advertise bus remove during rmmod */
++		dhdsdio_advertise_bus_remove(bus->dhd);
++		dhdsdio_release(bus, bus->dhd->osh);
++	}
++	DHD_MUTEX_UNLOCK();
++
++	DHD_TRACE(("%s: Disconnected\n", __FUNCTION__));
++}
++
++static int
++dhdsdio_suspend(void *context)
++{
++	int ret = 0;
++#ifdef SUPPORT_P2P_GO_PS
++	int wait_time = 0;
++#endif /* SUPPORT_P2P_GO_PS */
++
++	dhd_bus_t *bus = (dhd_bus_t*)context;
++	unsigned long flags;
++
++	DHD_ERROR(("%s Enter\n", __FUNCTION__));
++	if (bus->dhd == NULL) {
++		DHD_ERROR(("bus not inited\n"));
++		return BCME_ERROR;
++	}
++	if (bus->dhd->prot == NULL) {
++		DHD_ERROR(("prot is not inited\n"));
++		return BCME_ERROR;
++	}
++
++	if (bus->dhd->up == FALSE) {
++		return BCME_OK;
++	}
++
++	DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
++	if (bus->dhd->busstate != DHD_BUS_DATA && bus->dhd->busstate != DHD_BUS_SUSPEND) {
++		DHD_ERROR(("not in a readystate to LPBK  is not inited\n"));
++		DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
++		return BCME_ERROR;
++	}
++	DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
++	if (bus->dhd->dongle_reset) {
++		DHD_ERROR(("Dongle is in reset state.\n"));
++		return -EIO;
++	}
++
++	DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
++	bus->dhd->busstate = DHD_BUS_SUSPEND;
++	if (DHD_BUS_BUSY_CHECK_IN_TX(bus->dhd)) {
++		DHD_ERROR(("Tx Request is not ended\n"));
++		bus->dhd->busstate = DHD_BUS_DATA;
++		DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
++		return -EBUSY;
++	}
++	DHD_BUS_BUSY_SET_SUSPEND_IN_PROGRESS(bus->dhd);
++	DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
++
++#ifdef SUPPORT_P2P_GO_PS
++	if (bus->idletime > 0) {
++		wait_time = msecs_to_jiffies(bus->idletime * dhd_watchdog_ms);
++	}
++#endif /* SUPPORT_P2P_GO_PS */
++	ret = dhd_os_check_wakelock(bus->dhd);
++#ifdef SUPPORT_P2P_GO_PS
++	// terence 20141124: fix for suspend issue
++	if (SLPAUTO_ENAB(bus) && (!ret) && (bus->dhd->up) && (bus->dhd->op_mode != DHD_FLAG_HOSTAP_MODE)) {
++		if (wait_event_timeout(bus->bus_sleep, bus->sleeping, wait_time) == 0) {
++			if (!bus->sleeping) {
++				ret = 1;
++			}
++		}
++	}
++#endif /* SUPPORT_P2P_GO_PS */
++
++	DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
++	if (ret) {
++		bus->dhd->busstate = DHD_BUS_DATA;
++	}
++	DHD_BUS_BUSY_CLEAR_SUSPEND_IN_PROGRESS(bus->dhd);
++	dhd_os_busbusy_wake(bus->dhd);
++	DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
++	return ret;
++}
++
++static int
++dhdsdio_resume(void *context)
++{
++	dhd_bus_t *bus = (dhd_bus_t*)context;
++	ulong flags;
++
++	DHD_ERROR(("%s Enter\n", __FUNCTION__));
++
++	if (bus->dhd->up == FALSE) {
++		return BCME_OK;
++	}
++
++	DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
++	DHD_BUS_BUSY_SET_RESUME_IN_PROGRESS(bus->dhd);
++	DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
++
++#if defined(OOB_INTR_ONLY)
++	if (dhd_os_check_if_up(bus->dhd))
++		bcmsdh_oob_intr_set(bus->sdh, TRUE);
++#endif 
++
++	DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
++	DHD_BUS_BUSY_CLEAR_RESUME_IN_PROGRESS(bus->dhd);
++	bus->dhd->busstate = DHD_BUS_DATA;
++	dhd_os_busbusy_wake(bus->dhd);
++	DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
++
++	return 0;
++}
++
++
++/* Register/Unregister functions are called by the main DHD entry
++ * point (e.g. module insertion) to link with the bus driver, in
++ * order to look for or await the device.
++ */
++
++static bcmsdh_driver_t dhd_sdio = {
++	dhdsdio_probe,
++	dhdsdio_disconnect,
++	dhdsdio_suspend,
++	dhdsdio_resume
++};
++
++int
++dhd_bus_register(void)
++{
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	return bcmsdh_register(&dhd_sdio);
++}
++
++void
++dhd_bus_unregister(void)
++{
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	bcmsdh_unregister();
++}
++
++#if defined(BCMLXSDMMC)
++/* Register a dummy SDIO client driver in order to be notified of new SDIO device */
++int dhd_bus_reg_sdio_notify(void* semaphore)
++{
++	return bcmsdh_reg_sdio_notify(semaphore);
++}
++
++void dhd_bus_unreg_sdio_notify(void)
++{
++	bcmsdh_unreg_sdio_notify();
++}
++#endif /* defined(BCMLXSDMMC) */
++
++#ifdef BCMEMBEDIMAGE
++static int
++dhdsdio_download_code_array(struct dhd_bus *bus)
++{
++	int bcmerror = -1;
++	int offset = 0;
++	unsigned char *ularray = NULL;
++
++	DHD_INFO(("%s: download embedded firmware...\n", __FUNCTION__));
++
++	/* Download image */
++	while ((offset + MEMBLOCK) < sizeof(dlarray)) {
++		/* check if CR4 */
++		if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
++			/* if address is 0, store the reset instruction to be written in 0 */
++
++			if (offset == 0) {
++				bus->resetinstr = *(((uint32*)dlarray));
++				/* Add start of RAM address to the address given by user */
++				offset += bus->dongle_ram_base;
++			}
++		}
++
++		bcmerror = dhdsdio_membytes(bus, TRUE, offset,
++			(uint8 *) (dlarray + offset), MEMBLOCK);
++		if (bcmerror) {
++			DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
++			        __FUNCTION__, bcmerror, MEMBLOCK, offset));
++			goto err;
++		}
++
++		offset += MEMBLOCK;
++	}
++
++	if (offset < sizeof(dlarray)) {
++		bcmerror = dhdsdio_membytes(bus, TRUE, offset,
++			(uint8 *) (dlarray + offset), sizeof(dlarray) - offset);
++		if (bcmerror) {
++			DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
++			        __FUNCTION__, bcmerror, sizeof(dlarray) - offset, offset));
++			goto err;
++		}
++	}
++
++#ifdef DHD_DEBUG
++	/* Upload and compare the downloaded code */
++	{
++		ularray = MALLOC(bus->dhd->osh, bus->ramsize);
++		/* Upload image to verify downloaded contents. */
++		offset = 0;
++		memset(ularray, 0xaa, bus->ramsize);
++		while ((offset + MEMBLOCK) < sizeof(dlarray)) {
++			bcmerror = dhdsdio_membytes(bus, FALSE, offset, ularray + offset, MEMBLOCK);
++			if (bcmerror) {
++				DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
++					__FUNCTION__, bcmerror, MEMBLOCK, offset));
++				goto err;
++			}
++
++			offset += MEMBLOCK;
++		}
++
++		if (offset < sizeof(dlarray)) {
++			bcmerror = dhdsdio_membytes(bus, FALSE, offset,
++				ularray + offset, sizeof(dlarray) - offset);
++			if (bcmerror) {
++				DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
++					__FUNCTION__, bcmerror, sizeof(dlarray) - offset, offset));
++				goto err;
++			}
++		}
++
++		if (memcmp(dlarray, ularray, sizeof(dlarray))) {
++			DHD_ERROR(("%s: Downloaded image is corrupted (%s, %s, %s).\n",
++			           __FUNCTION__, dlimagename, dlimagever, dlimagedate));
++			goto err;
++		} else
++			DHD_ERROR(("%s: Download, Upload and compare succeeded (%s, %s, %s).\n",
++			           __FUNCTION__, dlimagename, dlimagever, dlimagedate));
++
++	}
++#endif /* DHD_DEBUG */
++
++err:
++	if (ularray)
++		MFREE(bus->dhd->osh, ularray, bus->ramsize);
++	return bcmerror;
++}
++#endif /* BCMEMBEDIMAGE */
++
++static int
++dhdsdio_download_code_file(struct dhd_bus *bus, char *pfw_path)
++{
++	int bcmerror = -1;
++	int offset = 0;
++	int len;
++	void *image = NULL;
++	uint8 *memblock = NULL, *memptr;
++	uint8 *memptr_tmp = NULL; // terence: check downloaded firmware is correct
++	uint memblock_size = MEMBLOCK;
++#ifdef DHD_DEBUG_DOWNLOADTIME
++	unsigned long initial_jiffies = 0;
++	uint firmware_sz = 0;
++#endif
++
++	DHD_INFO(("%s: download firmware %s\n", __FUNCTION__, pfw_path));
++
++	image = dhd_os_open_image(pfw_path);
++	if (image == NULL) {
++		printf("%s: Open firmware file failed %s\n", __FUNCTION__, pfw_path);
++		goto err;
++	}
++
++	/* Update the dongle image download block size depending on the F1 block size */
++	if (sd_f1_blocksize == 512)
++		memblock_size = MAX_MEMBLOCK;
++
++	memptr = memblock = MALLOC(bus->dhd->osh, memblock_size + DHD_SDALIGN);
++	if (memblock == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__,
++			memblock_size));
++		goto err;
++	}
++	if (dhd_msg_level & DHD_TRACE_VAL) {
++		memptr_tmp = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN);
++		if (memptr_tmp == NULL) {
++			DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK));
++			goto err;
++		}
++	}
++	if ((uint32)(uintptr)memblock % DHD_SDALIGN)
++		memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN));
++
++#ifdef DHD_DEBUG_DOWNLOADTIME
++	initial_jiffies = jiffies;
++#endif
++
++	/* Download image */
++	while ((len = dhd_os_get_image_block((char*)memptr, memblock_size, image))) {
++		// terence 20150412: fix for firmware failed to download
++		if (bus->dhd->conf->chip == BCM43340_CHIP_ID ||
++				bus->dhd->conf->chip == BCM43341_CHIP_ID) {
++			if (len % 64 != 0) {
++				memset(memptr+len, 0, len%64);
++				len += (64 - len%64);
++			}
++		}
++		if (len < 0) {
++			DHD_ERROR(("%s: dhd_os_get_image_block failed (%d)\n", __FUNCTION__, len));
++			bcmerror = BCME_ERROR;
++			goto err;
++		}
++		/* check if CR4 */
++		if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
++			/* if address is 0, store the reset instruction to be written in 0 */
++
++			if (offset == 0) {
++				bus->resetinstr = *(((uint32*)memptr));
++				/* Add start of RAM address to the address given by user */
++				offset += bus->dongle_ram_base;
++			}
++		}
++
++		bcmerror = dhdsdio_membytes(bus, TRUE, offset, memptr, len);
++		if (bcmerror) {
++			DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
++			        __FUNCTION__, bcmerror, memblock_size, offset));
++			goto err;
++		}
++
++		if (dhd_msg_level & DHD_TRACE_VAL) {
++			bcmerror = dhdsdio_membytes(bus, FALSE, offset, memptr_tmp, len);
++			if (bcmerror) {
++				DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
++				        __FUNCTION__, bcmerror, MEMBLOCK, offset));
++				goto err;
++			}
++			if (memcmp(memptr_tmp, memptr, len)) {
++				DHD_ERROR(("%s: Downloaded image is corrupted.\n", __FUNCTION__));
++				goto err;
++			} else
++				DHD_INFO(("%s: Download, Upload and compare succeeded.\n", __FUNCTION__));
++		}
++
++		offset += memblock_size;
++#ifdef DHD_DEBUG_DOWNLOADTIME
++		firmware_sz += len;
++#endif
++	}
++
++#ifdef DHD_DEBUG_DOWNLOADTIME
++	DHD_ERROR(("Firmware download time for %u bytes: %u ms\n",
++			firmware_sz, jiffies_to_msecs(jiffies - initial_jiffies)));
++#endif
++
++err:
++	if (memblock)
++		MFREE(bus->dhd->osh, memblock, memblock_size + DHD_SDALIGN);
++	if (dhd_msg_level & DHD_TRACE_VAL) {
++		if (memptr_tmp)
++			MFREE(bus->dhd->osh, memptr_tmp, MEMBLOCK + DHD_SDALIGN);
++	}
++
++	if (image)
++		dhd_os_close_image(image);
++
++	return bcmerror;
++}
++
++#ifdef DHD_UCODE_DOWNLOAD
++/* Currently supported only for the chips in which ucode RAM is AXI addressable */
++static uint32
++dhdsdio_ucode_base(struct dhd_bus *bus)
++{
++	uint32 ucode_base = 0;
++
++	switch ((uint16)bus->sih->chip) {
++	case BCM43012_CHIP_ID:
++		ucode_base = 0xE8020000;
++		break;
++	default:
++		DHD_ERROR(("%s: Unsupported!\n", __func__));
++		break;
++	}
++
++	return ucode_base;
++}
++
++static int
++dhdsdio_download_ucode_file(struct dhd_bus *bus, char *ucode_path)
++{
++	int bcmerror = -1;
++	int offset = 0;
++	int len;
++	uint32 ucode_base;
++	void *image = NULL;
++	uint8 *memblock = NULL, *memptr;
++	uint memblock_size = MEMBLOCK;
++#ifdef DHD_DEBUG_DOWNLOADTIME
++	unsigned long initial_jiffies = 0;
++	uint firmware_sz = 0;
++#endif
++
++	DHD_INFO(("%s: download firmware %s\n", __FUNCTION__, ucode_path));
++
++	ucode_base = dhdsdio_ucode_base(bus);
++
++	image = dhd_os_open_image(ucode_path);
++	if (image == NULL)
++		goto err;
++
++	/* Update the dongle image download block size depending on the F1 block size */
++	if (sd_f1_blocksize == 512)
++		memblock_size = MAX_MEMBLOCK;
++
++	memptr = memblock = MALLOC(bus->dhd->osh, memblock_size + DHD_SDALIGN);
++	if (memblock == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__,
++			memblock_size));
++		goto err;
++	}
++	if ((uint32)(uintptr)memblock % DHD_SDALIGN)
++		memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN));
++
++#ifdef DHD_DEBUG_DOWNLOADTIME
++	initial_jiffies = jiffies;
++#endif
++
++	/* Download image */
++	while ((len = dhd_os_get_image_block((char*)memptr, memblock_size, image))) {
++		if (len < 0) {
++			DHD_ERROR(("%s: dhd_os_get_image_block failed (%d)\n", __FUNCTION__, len));
++			bcmerror = BCME_ERROR;
++			goto err;
++		}
++
++		bcmerror = dhdsdio_membytes(bus, TRUE, (ucode_base + offset), memptr, len);
++		if (bcmerror) {
++			DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
++			        __FUNCTION__, bcmerror, memblock_size, offset));
++			goto err;
++		}
++
++		offset += memblock_size;
++#ifdef DHD_DEBUG_DOWNLOADTIME
++		firmware_sz += len;
++#endif
++	}
++
++#ifdef DHD_DEBUG_DOWNLOADTIME
++	DHD_ERROR(("ucode download time for %u bytes: %u ms\n",
++			firmware_sz, jiffies_to_msecs(jiffies - initial_jiffies)));
++#endif
++
++err:
++	if (memblock)
++		MFREE(bus->dhd->osh, memblock, memblock_size + DHD_SDALIGN);
++
++	if (image)
++		dhd_os_close_image(image);
++
++	return bcmerror;
++}
++
++void
++dhd_bus_ucode_download(struct dhd_bus *bus)
++{
++	uint32 shaddr = 0, shdata = 0;
++
++	shaddr = bus->dongle_ram_base + bus->ramsize - 4;
++	dhdsdio_membytes(bus, FALSE, shaddr, (uint8 *)&shdata, 4);
++
++	DHD_TRACE(("%s: shdata:[0x%08x :0x%08x]\n", __func__, shaddr, shdata));
++
++	if (shdata == UCODE_DOWNLOAD_REQUEST)
++	{
++		DHD_ERROR(("%s: Received ucode download request!\n", __func__));
++
++		/* Download the ucode */
++		if (!dhd_get_ucode_path(bus->dhd)) {
++			DHD_ERROR(("%s: bus->uc_path not set!\n", __func__));
++			return;
++		}
++		dhdsdio_download_ucode_file(bus, dhd_get_ucode_path(bus->dhd));
++
++		DHD_ERROR(("%s: Ucode downloaded successfully!\n", __func__));
++
++		shdata = UCODE_DOWNLOAD_COMPLETE;
++		dhdsdio_membytes(bus, TRUE, shaddr, (uint8 *)&shdata, 4);
++	}
++}
++
++#endif /* DHD_UCODE_DOWNLOAD */
++
++static int
++dhdsdio_download_nvram(struct dhd_bus *bus)
++{
++	int bcmerror = -1;
++	uint len;
++	void * image = NULL;
++	char * memblock = NULL;
++	char *bufp;
++	char *pnv_path;
++	bool nvram_file_exists;
++
++	pnv_path = bus->nv_path;
++
++	nvram_file_exists = ((pnv_path != NULL) && (pnv_path[0] != '\0'));
++
++	/* For Get nvram from UEFI */
++	if (nvram_file_exists) {
++		image = dhd_os_open_image(pnv_path);
++		if (image == NULL) {
++			printf("%s: Open nvram file failed %s\n", __FUNCTION__, pnv_path);
++			goto err;
++		}
++	}
++
++	memblock = MALLOC(bus->dhd->osh, MAX_NVRAMBUF_SIZE);
++	if (memblock == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
++		           __FUNCTION__, MAX_NVRAMBUF_SIZE));
++		goto err;
++	}
++
++	/* For Get nvram from image or UEFI (when image == NULL ) */
++	len = dhd_os_get_image_block(memblock, MAX_NVRAMBUF_SIZE, image);
++
++	if (len > 0 && len < MAX_NVRAMBUF_SIZE) {
++		bufp = (char *)memblock;
++		bufp[len] = 0;
++		len = process_nvram_vars(bufp, len);
++		if (len % 4) {
++			len += 4 - (len % 4);
++		}
++		bufp += len;
++		*bufp++ = 0;
++		if (len)
++			bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
++		if (bcmerror) {
++			DHD_ERROR(("%s: error downloading vars: %d\n",
++			           __FUNCTION__, bcmerror));
++		}
++	} else {
++		DHD_ERROR(("%s: error reading nvram file: %d\n",
++		           __FUNCTION__, len));
++		bcmerror = BCME_SDIO_ERROR;
++	}
++
++err:
++	if (memblock)
++		MFREE(bus->dhd->osh, memblock, MAX_NVRAMBUF_SIZE);
++
++	if (image)
++		dhd_os_close_image(image);
++
++	return bcmerror;
++}
++
++static int
++_dhdsdio_download_firmware(struct dhd_bus *bus)
++{
++	int bcmerror = -1;
++
++	bool embed = FALSE;	/* download embedded firmware */
++	bool dlok = FALSE;	/* download firmware succeeded */
++
++	/* Out immediately if no image to download */
++	if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
++#ifdef BCMEMBEDIMAGE
++		embed = TRUE;
++#else
++		return 0;
++#endif
++	}
++
++	/* Keep arm in reset */
++	if (dhdsdio_download_state(bus, TRUE)) {
++		DHD_ERROR(("%s: error placing ARM core in reset\n", __FUNCTION__));
++		goto err;
++	}
++
++	/* External image takes precedence if specified */
++	if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
++		if (dhdsdio_download_code_file(bus, bus->fw_path)) {
++			DHD_ERROR(("%s: dongle image file download failed\n", __FUNCTION__));
++#ifdef BCMEMBEDIMAGE
++			embed = TRUE;
++#else
++			goto err;
++#endif
++		} else {
++			embed = FALSE;
++			dlok = TRUE;
++		}
++	}
++
++#ifdef BCMEMBEDIMAGE
++	if (embed) {
++		if (dhdsdio_download_code_array(bus)) {
++			DHD_ERROR(("%s: dongle image array download failed\n", __FUNCTION__));
++			goto err;
++		} else {
++			dlok = TRUE;
++		}
++	}
++#else
++	BCM_REFERENCE(embed);
++#endif
++	if (!dlok) {
++		DHD_ERROR(("%s: dongle image download failed\n", __FUNCTION__));
++		goto err;
++	}
++
++	/* External nvram takes precedence if specified */
++	if (dhdsdio_download_nvram(bus)) {
++		DHD_ERROR(("%s: dongle nvram file download failed\n", __FUNCTION__));
++		goto err;
++	}
++
++	/* Take arm out of reset */
++	if (dhdsdio_download_state(bus, FALSE)) {
++		DHD_ERROR(("%s: error getting out of ARM core reset\n", __FUNCTION__));
++		goto err;
++	}
++
++	bcmerror = 0;
++
++err:
++	return bcmerror;
++}
++
++static int
++dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags, uint8 *buf, uint nbytes,
++	void *pkt, bcmsdh_cmplt_fn_t complete_fn, void *handle)
++{
++	int status;
++
++	if (!KSO_ENAB(bus)) {
++		DHD_ERROR(("%s: Device asleep\n", __FUNCTION__));
++		return BCME_NODEVICE;
++	}
++
++	status = bcmsdh_recv_buf(bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete_fn, handle);
++
++	return status;
++}
++
++static int
++dhd_bcmsdh_send_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags, uint8 *buf, uint nbytes,
++	void *pkt, bcmsdh_cmplt_fn_t complete_fn, void *handle, int max_retry)
++{
++	int ret;
++	int i = 0;
++	int retries = 0;
++	bcmsdh_info_t *sdh;
++
++	if (!KSO_ENAB(bus)) {
++		DHD_ERROR(("%s: Device asleep\n", __FUNCTION__));
++		return BCME_NODEVICE;
++	}
++
++	sdh = bus->sdh;
++	do {
++		ret = bcmsdh_send_buf(bus->sdh, addr, fn, flags, buf, nbytes,
++			pkt, complete_fn, handle);
++
++		bus->f2txdata++;
++		ASSERT(ret != BCME_PENDING);
++
++		if (ret == BCME_NODEVICE) {
++			DHD_ERROR(("%s: Device asleep already\n", __FUNCTION__));
++		} else if (ret < 0) {
++			/* On failure, abort the command and terminate the frame */
++			DHD_ERROR(("%s: sdio error %d, abort command and terminate frame.\n",
++				__FUNCTION__, ret));
++			bus->tx_sderrs++;
++			bus->f1regdata++;
++			bus->dhd->tx_errors++;
++			bcmsdh_abort(sdh, SDIO_FUNC_2);
++			bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL,
++				SFC_WF_TERM, NULL);
++			for (i = 0; i < READ_FRM_CNT_RETRIES; i++) {
++				uint8 hi, lo;
++				hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WFRAMEBCHI,
++					NULL);
++				lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WFRAMEBCLO,
++					NULL);
++				bus->f1regdata += 2;
++				if ((hi == 0) && (lo == 0))
++					break;
++			}
++		}
++	} while ((ret < 0) && retrydata && ++retries < max_retry);
++
++	return ret;
++}
++
++uint8
++dhd_bus_is_ioready(struct dhd_bus *bus)
++{
++	uint8 enable;
++	bcmsdh_info_t *sdh;
++	ASSERT(bus);
++	ASSERT(bus->sih != NULL);
++	enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
++	sdh = bus->sdh;
++	return (enable == bcmsdh_cfg_read(sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY, NULL));
++}
++
++uint
++dhd_bus_chip(struct dhd_bus *bus)
++{
++	ASSERT(bus->sih != NULL);
++	return bus->sih->chip;
++}
++
++uint
++dhd_bus_chiprev(struct dhd_bus *bus)
++{
++	ASSERT(bus);
++	ASSERT(bus->sih != NULL);
++	return bus->sih->chiprev;
++}
++
++void *
++dhd_bus_pub(struct dhd_bus *bus)
++{
++	return bus->dhd;
++}
++
++const void *
++dhd_bus_sih(struct dhd_bus *bus)
++{
++	return (const void *)bus->sih;
++}
++
++void *
++dhd_bus_txq(struct dhd_bus *bus)
++{
++	return &bus->txq;
++}
++
++uint
++dhd_bus_hdrlen(struct dhd_bus *bus)
++{
++	return (bus->txglom_enable) ? SDPCM_HDRLEN_TXGLOM : SDPCM_HDRLEN;
++}
++
++void
++dhd_bus_set_dotxinrx(struct dhd_bus *bus, bool val)
++{
++	bus->dotxinrx = val;
++}
++
++/*
++ *  dhdsdio_advertise_bus_cleanup advertises that clean up is under progress
++ * to other bus user contexts like Tx, Rx, IOVAR, WD etc and it waits for other contexts
++ * to gracefully exit. All the bus usage contexts before marking busstate as busy, will check for
++ * whether the busstate is DHD_BUS_DOWN or DHD_BUS_DOWN_IN_PROGRESS, if so
++ * they will exit from there itself without marking dhd_bus_busy_state as BUSY.
++ */
++static void
++dhdsdio_advertise_bus_cleanup(dhd_pub_t	 *dhdp)
++{
++	unsigned long flags;
++	int timeleft;
++
++	DHD_LINUX_GENERAL_LOCK(dhdp, flags);
++	dhdp->busstate = DHD_BUS_DOWN_IN_PROGRESS;
++	DHD_LINUX_GENERAL_UNLOCK(dhdp, flags);
++
++	timeleft = dhd_os_busbusy_wait_negation(dhdp, &dhdp->dhd_bus_busy_state);
++	if ((timeleft == 0) || (timeleft == 1)) {
++		DHD_ERROR(("%s : Timeout due to dhd_bus_busy_state=0x%x\n",
++				__FUNCTION__, dhdp->dhd_bus_busy_state));
++		ASSERT(0);
++	}
++
++	return;
++}
++
++static void
++dhdsdio_advertise_bus_remove(dhd_pub_t	 *dhdp)
++{
++	unsigned long flags;
++	int timeleft;
++
++	DHD_LINUX_GENERAL_LOCK(dhdp, flags);
++	dhdp->busstate = DHD_BUS_REMOVE;
++	DHD_LINUX_GENERAL_UNLOCK(dhdp, flags);
++
++	timeleft = dhd_os_busbusy_wait_negation(dhdp, &dhdp->dhd_bus_busy_state);
++	if ((timeleft == 0) || (timeleft == 1)) {
++		DHD_ERROR(("%s : Timeout due to dhd_bus_busy_state=0x%x\n",
++				__FUNCTION__, dhdp->dhd_bus_busy_state));
++		ASSERT(0);
++	}
++
++	return;
++}
++
++
++int
++dhd_bus_devreset(dhd_pub_t *dhdp, uint8 flag)
++{
++	int bcmerror = 0;
++	dhd_bus_t *bus;
++	unsigned long flags;
++
++	bus = dhdp->bus;
++
++	if (flag == TRUE) {
++		if (!bus->dhd->dongle_reset) {
++			DHD_ERROR(("%s: == Power OFF ==\n", __FUNCTION__));
++			dhdsdio_advertise_bus_cleanup(bus->dhd);
++			dhd_os_sdlock(dhdp);
++			dhd_os_wd_timer(dhdp, 0);
++#if !defined(IGNORE_ETH0_DOWN)
++			/* Force flow control as protection when stop come before ifconfig_down */
++			dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, ON);
++#endif /* !defined(IGNORE_ETH0_DOWN) */
++			/* Expect app to have torn down any connection before calling */
++			/* Stop the bus, disable F2 */
++			dhd_bus_stop(bus, FALSE);
++
++#if defined(OOB_INTR_ONLY)
++			/* Clean up any pending IRQ */
++			dhd_enable_oob_intr(bus, FALSE);
++			bcmsdh_oob_intr_set(bus->sdh, FALSE);
++			bcmsdh_oob_intr_unregister(bus->sdh);
++#endif 
++
++			/* Clean tx/rx buffer pointers, detach from the dongle */
++			dhdsdio_release_dongle(bus, bus->dhd->osh, TRUE, TRUE);
++
++			bus->dhd->dongle_reset = TRUE;
++			bus->dhd->up = FALSE;
++			dhd_txglom_enable(dhdp, FALSE);
++			dhd_os_sdunlock(dhdp);
++
++			DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
++			bus->dhd->busstate = DHD_BUS_DOWN;
++			DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
++
++			printf("%s:  WLAN OFF DONE\n", __FUNCTION__);
++			/* App can now remove power from device */
++		} else
++			bcmerror = BCME_SDIO_ERROR;
++	} else {
++		/* App must have restored power to device before calling */
++
++		printf("\n\n%s: == WLAN ON ==\n", __FUNCTION__);
++
++		if (bus->dhd->dongle_reset) {
++			/* Turn on WLAN */
++			dhd_os_sdlock(dhdp);
++			/* Reset SD client */
++			bcmsdh_reset(bus->sdh);
++
++			/* Attempt to re-attach & download */
++			if (dhdsdio_probe_attach(bus, bus->dhd->osh, bus->sdh,
++				(uint32 *)SI_ENUM_BASE,
++				bus->cl_devid)) {
++
++				DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
++				bus->dhd->busstate = DHD_BUS_DOWN;
++				DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
++				/* Attempt to download binary to the dongle */
++				if (dhdsdio_probe_init(bus, bus->dhd->osh, bus->sdh) &&
++				    dhdsdio_download_firmware(bus, bus->dhd->osh, bus->sdh) >= 0) {
++
++					/* Re-init bus, enable F2 transfer */
++					bcmerror = dhd_bus_init((dhd_pub_t *) bus->dhd, FALSE);
++					if (bcmerror == BCME_OK) {
++#if defined(OOB_INTR_ONLY)
++						dhd_enable_oob_intr(bus, TRUE);
++						bcmsdh_oob_intr_register(bus->sdh,
++							dhdsdio_isr, bus);
++						bcmsdh_oob_intr_set(bus->sdh, TRUE);
++#elif defined(FORCE_WOWLAN)
++						dhd_enable_oob_intr(bus, TRUE);
++#endif 
++
++						bus->dhd->dongle_reset = FALSE;
++						bus->dhd->up = TRUE;
++
++#if !defined(IGNORE_ETH0_DOWN)
++						/* Restore flow control  */
++						dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, OFF);
++#endif 
++						dhd_os_wd_timer(dhdp, dhd_watchdog_ms);
++
++						DHD_TRACE(("%s: WLAN ON DONE\n", __FUNCTION__));
++					} else {
++						dhd_bus_stop(bus, FALSE);
++						dhdsdio_release_dongle(bus, bus->dhd->osh,
++							TRUE, FALSE);
++					}
++				} else {
++					DHD_ERROR(("%s Failed to download binary to the dongle\n",
++						__FUNCTION__));
++					if (bus->sih != NULL) {
++						si_detach(bus->sih);
++						bus->sih = NULL;
++					}
++					bcmerror = BCME_SDIO_ERROR;
++				}
++			} else
++				bcmerror = BCME_SDIO_ERROR;
++
++			dhd_os_sdunlock(dhdp);
++		} else {
++			printf("%s called when dongle is not in reset\n",
++				__FUNCTION__);
++			printf("Will call dhd_bus_start instead\n");
++			dhd_bus_resume(dhdp, 1);
++#if defined(HW_OOB) || defined(FORCE_WOWLAN)
++			dhd_conf_set_hw_oob_intr(bus->sdh, bus->sih->chip); // terence 20120615: fix for OOB initial issue
++#endif
++			if ((bcmerror = dhd_bus_start(dhdp)) != 0)
++				DHD_ERROR(("%s: dhd_bus_start fail with %d\n",
++					__FUNCTION__, bcmerror));
++		}
++	}
++
++#ifdef PKT_STATICS
++	memset((uint8*) &tx_statics, 0, sizeof(pkt_statics_t));
++#endif
++	return bcmerror;
++}
++
++int dhd_bus_suspend(dhd_pub_t *dhdpub)
++{
++	return bcmsdh_stop(dhdpub->bus->sdh);
++}
++
++int dhd_bus_resume(dhd_pub_t *dhdpub, int stage)
++{
++	return bcmsdh_start(dhdpub->bus->sdh, stage);
++}
++
++/* Get Chip ID version */
++uint dhd_bus_chip_id(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++
++	if (bus && bus->sih)
++		return bus->sih->chip;
++	else
++		return 0;
++}
++
++/* Get Chip Rev ID version */
++uint dhd_bus_chiprev_id(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++
++	if (bus && bus->sih)
++		return bus->sih->chiprev;
++	else
++		return 0;
++}
++
++/* Get Chip Pkg ID version */
++uint dhd_bus_chippkg_id(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++
++	return bus->sih->chippkg;
++}
++
++int dhd_bus_get_ids(struct dhd_bus *bus, uint32 *bus_type, uint32 *bus_num, uint32 *slot_num)
++{
++	*bus_type = bus->bus;
++	*bus_num = bus->bus_num;
++	*slot_num = bus->slot_num;
++	return 0;
++}
++
++int
++dhd_bus_membytes(dhd_pub_t *dhdp, bool set, uint32 address, uint8 *data, uint size)
++{
++	dhd_bus_t *bus;
++
++	bus = dhdp->bus;
++	return dhdsdio_membytes(bus, set, address, data, size);
++}
++
++
++void
++dhd_bus_update_fw_nv_path(struct dhd_bus *bus, char *pfw_path, char *pnv_path,
++									char *pclm_path, char *pconf_path)
++{
++	bus->fw_path = pfw_path;
++	bus->nv_path = pnv_path;
++	bus->dhd->clm_path = pclm_path;
++	bus->dhd->conf_path = pconf_path;
++}
++
++int
++dhd_enableOOB(dhd_pub_t *dhd, bool sleep)
++{
++	dhd_bus_t *bus = dhd->bus;
++	sdpcmd_regs_t *regs = bus->regs;
++	uint retries = 0;
++
++	if (sleep) {
++		dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++		/* Tell device to start using OOB wakeup */
++		W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
++		if (retries > retry_limit) {
++			DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
++			return BCME_BUSY;
++		}
++		/* Turn off our contribution to the HT clock request */
++		dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++	} else {
++		/* Make sure the controller has the bus up */
++		dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++		/* Send misc interrupt to indicate OOB not needed */
++		W_SDREG(0, &regs->tosbmailboxdata, retries);
++		if (retries <= retry_limit)
++			W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
++
++		if (retries > retry_limit)
++			DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
++
++		/* Make sure we have SD bus access */
++		dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++	}
++	return BCME_OK;
++}
++
++void
++dhd_bus_pktq_flush(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	bool wlfc_enabled = FALSE;
++
++#ifdef PROP_TXSTATUS
++	wlfc_enabled = (dhd_wlfc_cleanup_txq(dhdp, NULL, 0) != WLFC_UNSUPPORTED);
++#endif
++	if (!wlfc_enabled) {
++#ifdef DHDTCPACK_SUPPRESS
++		/* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt,
++		 * when there is a newly coming packet from network stack.
++		 */
++		dhd_tcpack_info_tbl_clean(bus->dhd);
++#endif /* DHDTCPACK_SUPPRESS */
++		/* Clear the data packet queues */
++		pktq_flush(dhdp->osh, &bus->txq, TRUE);
++	}
++}
++
++#ifdef BCMSDIO
++int
++dhd_sr_config(dhd_pub_t *dhd, bool on)
++{
++	dhd_bus_t *bus = dhd->bus;
++
++	if (!bus->_srenab)
++		return -1;
++
++	return dhdsdio_clk_devsleep_iovar(bus, on);
++}
++
++uint16
++dhd_get_chipid(dhd_pub_t *dhd)
++{
++	dhd_bus_t *bus = dhd->bus;
++
++	if (bus && bus->sih)
++		return (uint16)bus->sih->chip;
++	else
++		return 0;
++}
++#endif /* BCMSDIO */
++
++#ifdef DEBUGGER
++uint32 dhd_sdio_reg_read(void *h, uint32 addr)
++{
++	uint32 rval;
++	struct dhd_bus *bus = (struct dhd_bus *) h;
++
++	dhd_os_sdlock(bus->dhd);
++
++	BUS_WAKE(bus);
++
++	dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++	rval = bcmsdh_reg_read(bus->sdh, addr, 4);
++
++	dhd_os_sdunlock(bus->dhd);
++
++	return rval;
++}
++
++void dhd_sdio_reg_write(void *h, uint32 addr, uint32 val)
++{
++	struct dhd_bus *bus = (struct dhd_bus *) h;
++
++	dhd_os_sdlock(bus->dhd);
++
++	BUS_WAKE(bus);
++
++	dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++	bcmsdh_reg_write(bus->sdh, addr, 4, val);
++
++	dhd_os_sdunlock(bus->dhd);
++}
++
++#endif /* DEBUGGER */
++
++
++#if defined(BT_OVER_SDIO)
++uint8 dhd_bus_cfg_read(void *h, uint fun_num, uint32 addr, int *err)
++{
++	uint8 intrd;
++	dhd_pub_t *dhdp = (dhd_pub_t *)h;
++	dhd_bus_t *bus = (dhd_bus_t *)dhdp->bus;
++
++	dhd_os_sdlock(bus->dhd);
++
++	intrd = bcmsdh_cfg_read(bus->sdh, fun_num, addr, err);
++
++	dhd_os_sdunlock(bus->dhd);
++
++	return intrd;
++} EXPORT_SYMBOL(dhd_bus_cfg_read);
++
++void dhd_bus_cfg_write(void *h, uint fun_num, uint32 addr, uint8 val, int *err)
++{
++	dhd_pub_t *dhdp = (dhd_pub_t *)h;
++	dhd_bus_t *bus = (dhd_bus_t *)dhdp->bus;
++
++	dhd_os_sdlock(bus->dhd);
++
++	bcmsdh_cfg_write(bus->sdh, fun_num, addr, val, err);
++
++	dhd_os_sdunlock(bus->dhd);
++
++} EXPORT_SYMBOL(dhd_bus_cfg_write);
++
++static int
++extract_hex_field(char * line, uint16 start_pos, uint16 num_chars, uint16 * value)
++{
++	char field [8];
++
++	strncpy(field, line + start_pos, num_chars);
++	field [num_chars] = '\0';
++
++	return (sscanf (field, "%hX", value) == 1);
++}
++
++static int
++read_more_btbytes(struct dhd_bus *bus, void * file, char *line, int * addr_mode, uint16 * hi_addr,
++	uint32 * dest_addr, uint8 *data_bytes, uint32 * num_bytes)
++{
++	int		str_len;
++	uint16	num_data_bytes, addr, data_pos, type, w, i;
++	uint32	abs_base_addr32 = 0;
++	*num_bytes = 0;
++
++	while (!*num_bytes)
++	{
++		str_len = dhd_os_gets_image(bus->dhd, line, BTFW_MAX_STR_LEN, file);
++
++		DHD_TRACE(("%s: Len :0x%x  %s\n", __FUNCTION__, str_len, line));
++
++		if (str_len == 0) {
++			break;
++		} else if (str_len > 9) {
++			extract_hex_field(line, 1, 2, &num_data_bytes);
++			extract_hex_field(line, 3, 4, &addr);
++			extract_hex_field(line, 7, 2, &type);
++
++			data_pos = 9;
++			for (i = 0; i < num_data_bytes; i++) {
++				extract_hex_field(line, data_pos, 2, &w);
++				data_bytes [i] = (uint8)(w & 0x00FF);
++				data_pos += 2;
++			}
++
++			if (type == BTFW_HEX_LINE_TYPE_EXTENDED_ADDRESS) {
++				*hi_addr = (data_bytes [0] << 8) | data_bytes [1];
++				*addr_mode = BTFW_ADDR_MODE_EXTENDED;
++			} else if (type == BTFW_HEX_LINE_TYPE_EXTENDED_SEGMENT_ADDRESS) {
++				*hi_addr = (data_bytes [0] << 8) | data_bytes [1];
++				*addr_mode = BTFW_ADDR_MODE_SEGMENT;
++			} else if (type == BTFW_HEX_LINE_TYPE_ABSOLUTE_32BIT_ADDRESS) {
++				abs_base_addr32 = (data_bytes [0] << 24) | (data_bytes [1] << 16) |
++					(data_bytes [2] << 8) | data_bytes [3];
++				*addr_mode = BTFW_ADDR_MODE_LINEAR32;
++			} else if (type == BTFW_HEX_LINE_TYPE_DATA) {
++				*dest_addr = addr;
++				if (*addr_mode == BTFW_ADDR_MODE_EXTENDED)
++					*dest_addr += (*hi_addr << 16);
++				else if (*addr_mode == BTFW_ADDR_MODE_SEGMENT)
++					*dest_addr += (*hi_addr << 4);
++				else if (*addr_mode == BTFW_ADDR_MODE_LINEAR32)
++					*dest_addr += abs_base_addr32;
++				*num_bytes = num_data_bytes;
++			}
++		}
++	}
++	return (*num_bytes > 0);
++}
++
++static int
++_dhdsdio_download_btfw(struct dhd_bus *bus)
++{
++	int	bcm_error = -1;
++	void	*image = NULL;
++	uint8	*mem_blk = NULL, *mem_ptr = NULL, *data_ptr = NULL;
++
++
++	uint32 offset_addr = 0, offset_len = 0, bytes_to_write = 0;
++
++	char	*line = NULL;
++	uint32	dest_addr = 0, num_bytes;
++	uint16	hiAddress = 0;
++	uint32	start_addr, start_data, end_addr, end_data, i, index, pad;
++	uint32	bt2wlan_pwrup_adr;
++
++	int	addr_mode		= BTFW_ADDR_MODE_EXTENDED;
++
++	/* Out immediately if no image to download */
++	if ((bus->btfw_path == NULL) || (bus->btfw_path[0] == '\0')) {
++		return 0;
++	}
++
++	image = dhd_os_open_image(bus->btfw_path);
++	if (image == NULL)
++		goto err;
++
++	mem_ptr = mem_blk = MALLOC(bus->dhd->osh, BTFW_DOWNLOAD_BLK_SIZE + DHD_SDALIGN);
++	if (mem_blk == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__,
++			BTFW_DOWNLOAD_BLK_SIZE + DHD_SDALIGN));
++		goto err;
++	}
++	if ((uint32)(uintptr)mem_blk % DHD_SDALIGN)
++		mem_ptr += (DHD_SDALIGN - ((uint32)(uintptr)mem_blk % DHD_SDALIGN));
++
++	data_ptr = MALLOC(bus->dhd->osh, BTFW_DOWNLOAD_BLK_SIZE - 8);
++	if (data_ptr == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__,
++			BTFW_DOWNLOAD_BLK_SIZE - 8));
++		goto err;
++	}
++	/* Write to BT register to hold WLAN wake high during BT FW download */
++	bt2wlan_pwrup_adr = BTMEM_OFFSET + BT2WLAN_PWRUP_ADDR;
++	bcmsdh_reg_write(bus->sdh, bt2wlan_pwrup_adr, 4, BT2WLAN_PWRUP_WAKE);
++	/*
++	  * Wait for at least 2msec for the clock to be ready/Available.
++	  */
++	OSL_DELAY(2000);
++
++	line = MALLOC(bus->dhd->osh, BTFW_MAX_STR_LEN);
++	if (line == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
++			__FUNCTION__, BTFW_MAX_STR_LEN));
++		goto err;
++	}
++	memset(line, 0, BTFW_MAX_STR_LEN);
++
++	while (read_more_btbytes (bus, image, line, &addr_mode, &hiAddress, &dest_addr,
++		data_ptr, &num_bytes)) {
++
++		DHD_TRACE(("read %d bytes at address %08X\n", num_bytes, dest_addr));
++
++		start_addr = BTMEM_OFFSET + dest_addr;
++		index = 0;
++
++		/* Make sure the start address is 4 byte aligned to avoid alignment issues
++		 * with SD host controllers
++		 */
++		if (!ISALIGNED(start_addr, 4)) {
++			pad = start_addr % 4;
++			start_addr = ROUNDDN(start_addr, 4);
++			start_data = bcmsdh_reg_read(bus->sdh, start_addr, 4);
++			for (i = 0; i < pad; i++, index++) {
++			    mem_ptr[index] = (uint8)((uint8 *)&start_data)[i];
++			}
++		}
++		bcopy(data_ptr, &(mem_ptr[index]), num_bytes);
++		index += num_bytes;
++
++		/* Make sure the length is multiple of 4bytes to avoid alignment issues
++		 * with SD host controllers
++		 */
++		end_addr = start_addr + index;
++		if (!ISALIGNED(end_addr, 4)) {
++			end_addr = ROUNDDN(end_addr, 4);
++			end_data = bcmsdh_reg_read(bus->sdh, end_addr, 4);
++			for (i = (index % 4); i < 4; i++, index++) {
++				mem_ptr[index] = (uint8)((uint8 *)&end_data)[i];
++			}
++		}
++
++		offset_addr = start_addr & 0xFFF;
++		offset_len =  offset_addr + index;
++		if (offset_len <= 0x1000) {
++			bcm_error = dhdsdio_membytes(bus, TRUE, start_addr, mem_ptr, index);
++			if (bcm_error) {
++				DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
++				__FUNCTION__, bcm_error, num_bytes, start_addr));
++				goto err;
++			}
++		}
++		else {
++			bytes_to_write = 0x1000 - offset_addr;
++			bcm_error = dhdsdio_membytes(bus, TRUE, start_addr, mem_ptr,
++				bytes_to_write);
++			if (bcm_error) {
++				DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
++				__FUNCTION__, bcm_error, num_bytes, start_addr));
++				goto err;
++			}
++
++			OSL_DELAY(10000);
++
++			bcm_error = dhdsdio_membytes(bus, TRUE, (start_addr + bytes_to_write),
++				(mem_ptr + bytes_to_write), (index - bytes_to_write));
++			if (bcm_error) {
++				DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
++					__FUNCTION__, bcm_error, num_bytes, start_addr));
++				goto err;
++			}
++		}
++		memset(line, 0, BTFW_MAX_STR_LEN);
++	}
++
++	bcm_error = 0;
++err:
++	if (mem_blk)
++		MFREE(bus->dhd->osh, mem_blk, BTFW_DOWNLOAD_BLK_SIZE + DHD_SDALIGN);
++
++	if (data_ptr)
++		MFREE(bus->dhd->osh, data_ptr, BTFW_DOWNLOAD_BLK_SIZE - 8);
++
++	if (line)
++		MFREE(bus->dhd->osh, line, BTFW_MAX_STR_LEN);
++
++	if (image)
++		dhd_os_close_image(image);
++
++	return bcm_error;
++}
++
++static int
++dhdsdio_download_btfw(struct dhd_bus *bus, osl_t *osh, void *sdh)
++{
++	int ret;
++
++	DHD_TRACE(("%s: btfw path=%s\n",
++		__FUNCTION__, bus->btfw_path));
++	DHD_OS_WAKE_LOCK(bus->dhd);
++	dhd_os_sdlock(bus->dhd);
++
++	/* Download the firmware */
++	ret = _dhdsdio_download_btfw(bus);
++
++	dhd_os_sdunlock(bus->dhd);
++	DHD_OS_WAKE_UNLOCK(bus->dhd);
++
++	return ret;
++}
++
++int
++dhd_bus_download_btfw(struct dhd_bus *bus, osl_t *osh,
++                          char *pbtfw_path)
++{
++	int ret;
++
++	bus->btfw_path = pbtfw_path;
++
++	ret = dhdsdio_download_btfw(bus, osh, bus->sdh);
++
++	return ret;
++}
++#endif /* defined (BT_OVER_SDIO) */
++
++void
++dhd_bus_dump_trap_info(dhd_bus_t *bus, struct bcmstrbuf *strbuf)
++{
++	trap_t *tr = &bus->dhd->last_trap_info;
++
++	bcm_bprintf(strbuf,
++		"Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
++		"lp 0x%x, rpc 0x%x Trap offset 0x%x, "
++		"r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, "
++		"r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n\n",
++		ltoh32(tr->type), ltoh32(tr->epc), ltoh32(tr->cpsr), ltoh32(tr->spsr),
++		ltoh32(tr->r13), ltoh32(tr->r14), ltoh32(tr->pc),
++		ltoh32(bus->dongle_trap_addr),
++		ltoh32(tr->r0), ltoh32(tr->r1), ltoh32(tr->r2), ltoh32(tr->r3),
++		ltoh32(tr->r4), ltoh32(tr->r5), ltoh32(tr->r6), ltoh32(tr->r7));
++
++}
++
++static int
++dhd_bcmsdh_send_buffer(void *bus, uint8 *frame, uint16 len)
++{
++	int ret = -1;
++
++	ret = dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(((dhd_bus_t*)bus)->sdh),
++		SDIO_FUNC_2, F2SYNC, frame, len, NULL, NULL, NULL, TXRETRIES);
++
++	if (ret == BCME_OK)
++		((dhd_bus_t*)bus)->tx_seq = (((dhd_bus_t*)bus)->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
++
++	return ret;
++}
++
++/* Function to set the min res mask depending on the chip ID used */
++bool
++dhd_bus_set_default_min_res_mask(struct dhd_bus *bus)
++{
++	if ((bus == NULL) || (bus->sih == NULL)) {
++		DHD_ERROR(("%s(): Invalid Arguments \r\n", __FUNCTION__));
++		return FALSE;
++	}
++
++	switch (bus->sih->chip) {
++	case BCM4339_CHIP_ID:
++		bcmsdh_reg_write(bus->sdh, SI_ENUM_BASE + 0x618, 4, 0x3fcaf377);
++		if (bcmsdh_regfail(bus->sdh)) {
++			DHD_ERROR(("%s:%d Setting min_res_mask failed\n", __FUNCTION__, __LINE__));
++			return FALSE;
++		}
++		break;
++
++	case BCM43012_CHIP_ID:
++		bcmsdh_reg_write(bus->sdh,
++			si_get_pmu_reg_addr(bus->sih, OFFSETOF(pmuregs_t, min_res_mask)),
++			4, DEFAULT_43012_MIN_RES_MASK);
++		if (bcmsdh_regfail(bus->sdh)) {
++			DHD_ERROR(("%s:%d Setting min_res_mask failed\n", __FUNCTION__, __LINE__));
++			return FALSE;
++		}
++		break;
++
++	default:
++		DHD_ERROR(("%s: Unhandled chip id\n", __FUNCTION__));
++		return FALSE;
++	}
++
++	return TRUE;
++}
++
++/* Function to reset PMU registers */
++void
++dhd_bus_pmu_reg_reset(dhd_pub_t *dhdp)
++{
++	struct dhd_bus *bus = dhdp->bus;
++	bcmsdh_reg_write(bus->sdh, si_get_pmu_reg_addr(bus->sih,
++		OFFSETOF(pmuregs_t, swscratch)), 4, 0x0);
++	if (bcmsdh_regfail(bus->sdh)) {
++		DHD_ERROR(("%s:%d Setting min_res_mask failed\n", __FUNCTION__, __LINE__));
++	}
++}
++
++
++#ifdef DHD_ULP
++/* Function to disable console messages on entering ULP mode */
++void
++dhd_bus_ulp_disable_console(dhd_pub_t *dhdp)
++{
++#ifdef DHD_DEBUG
++	DHD_ERROR(("Flushing and disabling console messages\n"));
++
++	/* Save the console print interval */
++	dhd_ulp_save_console_interval(dhdp);
++
++	/* Flush the console buffer before disabling */
++	dhdsdio_readconsole(dhdp->bus);
++	dhd_console_ms = 0;
++#endif /* DHD_DEBUG */
++}
++
++/* Function for redownloading firmaware */
++static int
++dhd_bus_ulp_reinit_fw(dhd_bus_t *bus)
++{
++	int bcmerror = 0;
++
++	/* After firmware redownload tx/rx seq are reset accordingly these values are
++	reset on DHD side tx_max is initially set to 4, which later is updated by FW
++	*/
++	bus->tx_seq = bus->rx_seq = 0;
++	bus->tx_max = 4;
++
++	if (dhd_bus_download_firmware(bus, bus->dhd->osh,
++		bus->fw_path, bus->nv_path) >= 0) {
++
++		/* Re-init bus, enable F2 transfer */
++		bcmerror = dhd_bus_init((dhd_pub_t *) bus->dhd, FALSE);
++		if (bcmerror == BCME_OK) {
++			bus->dhd->up = TRUE;
++			dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
++
++			dhd_ulp_set_ulp_state(bus->dhd, DHD_ULP_READY);
++#if defined(OOB_INTR_ONLY)
++			dhd_enable_oob_intr(bus, TRUE);
++			bcmsdh_oob_intr_set(bus->sdh, TRUE);
++#endif 
++#ifdef DHD_DEBUG
++		/* Re-enable the console messages on FW redownload to default value */
++		dhd_ulp_restore_console_interval(bus->dhd);
++#endif /* DHD_DEBUG */
++		} else {
++			DHD_ERROR(("bus init failed\n"));
++			dhd_bus_stop(bus, FALSE);
++			dhdsdio_release_dongle(bus, bus->dhd->osh,
++				TRUE, FALSE);
++		}
++	} else
++		bcmerror = BCME_SDIO_ERROR;
++
++	return bcmerror;
++}
++#endif /* DHD_ULP */
++
++int
++dhd_bus_readwrite_bp_addr(dhd_pub_t *dhdp, uint addr, uint size, uint* data, bool read)
++{
++	int bcmerror = 0;
++	struct dhd_bus *bus = dhdp->bus;
++
++	if (read) {
++		*data = (int32)bcmsdh_reg_read(bus->sdh, addr, size);
++	} else {
++		bcmsdh_reg_write(bus->sdh, addr, size, *data);
++	}
++
++	if (bcmsdh_regfail(bus->sdh))
++		bcmerror = BCME_SDIO_ERROR;
++
++	return bcmerror;
++}
++
++int dhd_get_idletime(dhd_pub_t *dhd)
++{
++	return dhd->bus->idletime;
++}
++
++#ifdef DHD_WAKE_STATUS
++wake_counts_t*
++dhd_bus_get_wakecount(dhd_pub_t *dhd)
++{
++	if (!dhd->bus) {
++		return NULL;
++	}
++	return &dhd->bus->wake_counts;
++}
++int
++dhd_bus_get_bus_wake(dhd_pub_t *dhd)
++{
++	return bcmsdh_set_get_wake(dhd->bus->sdh, 0);
++}
++#endif /* DHD_WAKE_STATUS */
++
++int
++dhd_bus_sleep(dhd_pub_t *dhdp, bool sleep, uint32 *intstatus)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	uint32 retry = 0;
++	int ret = 0;
++
++	if (bus) {
++		dhd_os_sdlock(dhdp);
++		BUS_WAKE(bus);
++		R_SDREG(*intstatus, &bus->regs->intstatus, retry);
++		if (sleep) {
++			if (SLPAUTO_ENAB(bus)) {
++				ret = dhdsdio_bussleep(bus, sleep);
++				if (ret != BCME_BUSY)
++					dhd_os_wd_timer(bus->dhd, 0);
++			} else
++				dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++		}
++		dhd_os_sdunlock(dhdp);
++	} else {
++		DHD_ERROR(("bus is NULL\n"));
++		ret = -1;
++	}
++
++	return ret;
++}
+\ No newline at end of file
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_static_buf.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_static_buf.c
+new file mode 100644
+index 000000000..38dd04404
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_static_buf.c
+@@ -0,0 +1,535 @@
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/skbuff.h>
++
++#define	DHD_STATIC_VERSION_STR		"1.579.77.41.9"
++
++#define BCMDHD_SDIO
++#define BCMDHD_PCIE
++
++enum dhd_prealloc_index {
++	DHD_PREALLOC_PROT = 0,
++#if defined(BCMDHD_SDIO)
++	DHD_PREALLOC_RXBUF = 1,
++	DHD_PREALLOC_DATABUF = 2,
++#endif
++	DHD_PREALLOC_OSL_BUF = 3,
++	DHD_PREALLOC_SKB_BUF = 4,
++	DHD_PREALLOC_WIPHY_ESCAN0 = 5,
++	DHD_PREALLOC_WIPHY_ESCAN1 = 6,
++	DHD_PREALLOC_DHD_INFO = 7,
++	DHD_PREALLOC_DHD_WLFC_INFO = 8,
++#ifdef BCMDHD_PCIE
++	DHD_PREALLOC_IF_FLOW_LKUP = 9,
++#endif
++	DHD_PREALLOC_MEMDUMP_BUF = 10,
++	DHD_PREALLOC_MEMDUMP_RAM = 11,
++	DHD_PREALLOC_DHD_WLFC_HANGER = 12,
++	DHD_PREALLOC_PKTID_MAP = 13,
++	DHD_PREALLOC_PKTID_MAP_IOCTL = 14,
++	DHD_PREALLOC_DHD_LOG_DUMP_BUF = 15,
++	DHD_PREALLOC_DHD_LOG_DUMP_BUF_EX = 16,
++	DHD_PREALLOC_DHD_PKTLOG_DUMP_BUF = 17,
++	DHD_PREALLOC_STAT_REPORT_BUF = 18,
++	DHD_PREALLOC_WL_ESCAN = 19,
++	DHD_PREALLOC_FW_VERBOSE_RING = 20,
++	DHD_PREALLOC_FW_EVENT_RING = 21,
++	DHD_PREALLOC_DHD_EVENT_RING = 22,
++	DHD_PREALLOC_NAN_EVENT_RING = 23,
++	DHD_PREALLOC_MAX
++};
++
++#define STATIC_BUF_MAX_NUM	20
++#define STATIC_BUF_SIZE	(PAGE_SIZE*2)
++
++#define DHD_PREALLOC_PROT_SIZE	(16 * 1024)
++#define DHD_PREALLOC_RXBUF_SIZE	(24 * 1024)
++#define DHD_PREALLOC_DATABUF_SIZE	(64 * 1024)
++#define DHD_PREALLOC_OSL_BUF_SIZE	(STATIC_BUF_MAX_NUM * STATIC_BUF_SIZE)
++#define DHD_PREALLOC_WIPHY_ESCAN0_SIZE	(64 * 1024)
++#define DHD_PREALLOC_DHD_INFO_SIZE	(32 * 1024)
++#define DHD_PREALLOC_MEMDUMP_RAM_SIZE	(810 * 1024)
++#define DHD_PREALLOC_DHD_WLFC_HANGER_SIZE	(73 * 1024)
++#define DHD_PREALLOC_WL_ESCAN_SIZE	(70 * 1024)
++#ifdef CONFIG_64BIT
++#define DHD_PREALLOC_IF_FLOW_LKUP_SIZE	(20 * 1024 * 2)
++#else
++#define DHD_PREALLOC_IF_FLOW_LKUP_SIZE	(20 * 1024)
++#endif
++#define FW_VERBOSE_RING_SIZE		(64 * 1024)
++#define FW_EVENT_RING_SIZE		(64 * 1024)
++#define DHD_EVENT_RING_SIZE		(64 * 1024)
++#define NAN_EVENT_RING_SIZE		(64 * 1024)
++
++#if defined(CONFIG_64BIT)
++#define WLAN_DHD_INFO_BUF_SIZE	(24 * 1024)
++#define WLAN_DHD_WLFC_BUF_SIZE	(64 * 1024)
++#define WLAN_DHD_IF_FLOW_LKUP_SIZE	(64 * 1024)
++#else
++#define WLAN_DHD_INFO_BUF_SIZE	(16 * 1024)
++#define WLAN_DHD_WLFC_BUF_SIZE	(24 * 1024)
++#define WLAN_DHD_IF_FLOW_LKUP_SIZE	(20 * 1024)
++#endif /* CONFIG_64BIT */
++#define WLAN_DHD_MEMDUMP_SIZE	(800 * 1024)
++
++#define DHD_SKB_1PAGE_BUFSIZE	(PAGE_SIZE*1)
++#define DHD_SKB_2PAGE_BUFSIZE	(PAGE_SIZE*2)
++#define DHD_SKB_4PAGE_BUFSIZE	(PAGE_SIZE*4)
++
++#define DHD_SKB_1PAGE_BUF_NUM	8
++#ifdef BCMDHD_PCIE
++#define DHD_SKB_2PAGE_BUF_NUM	64
++#elif defined(BCMDHD_SDIO)
++#define DHD_SKB_2PAGE_BUF_NUM	8
++#endif
++#define DHD_SKB_4PAGE_BUF_NUM	1
++
++/* The number is defined in linux_osl.c
++ * WLAN_SKB_1_2PAGE_BUF_NUM => STATIC_PKT_1_2PAGE_NUM
++ * WLAN_SKB_BUF_NUM => STATIC_PKT_MAX_NUM
++ */
++#define WLAN_SKB_1_2PAGE_BUF_NUM ((DHD_SKB_1PAGE_BUF_NUM) + \
++		(DHD_SKB_2PAGE_BUF_NUM))
++#define WLAN_SKB_BUF_NUM ((WLAN_SKB_1_2PAGE_BUF_NUM) + (DHD_SKB_4PAGE_BUF_NUM))
++
++void *wlan_static_prot = NULL;
++void *wlan_static_rxbuf = NULL;
++void *wlan_static_databuf = NULL;
++void *wlan_static_osl_buf = NULL;
++void *wlan_static_scan_buf0 = NULL;
++void *wlan_static_scan_buf1 = NULL;
++void *wlan_static_dhd_info_buf = NULL;
++void *wlan_static_dhd_wlfc_info_buf = NULL;
++void *wlan_static_if_flow_lkup = NULL;
++void *wlan_static_dhd_memdump_ram_buf = NULL;
++void *wlan_static_dhd_wlfc_hanger_buf = NULL;
++void *wlan_static_wl_escan_info_buf = NULL;
++void *wlan_static_fw_verbose_ring_buf = NULL;
++void *wlan_static_fw_event_ring_buf = NULL;
++void *wlan_static_dhd_event_ring_buf = NULL;
++void *wlan_static_nan_event_ring_buf = NULL;
++
++static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
++
++void *dhd_wlan_mem_prealloc(int section, unsigned long size)
++{
++	pr_err("%s: sectoin %d, %ld\n", __func__, section, size);
++	if (section == DHD_PREALLOC_PROT)
++		return wlan_static_prot;
++
++#if defined(BCMDHD_SDIO)
++	if (section == DHD_PREALLOC_RXBUF)
++		return wlan_static_rxbuf;
++
++	if (section == DHD_PREALLOC_DATABUF)
++		return wlan_static_databuf;
++#endif /* BCMDHD_SDIO */
++
++	if (section == DHD_PREALLOC_SKB_BUF)
++		return wlan_static_skb;
++
++	if (section == DHD_PREALLOC_WIPHY_ESCAN0)
++		return wlan_static_scan_buf0;
++
++	if (section == DHD_PREALLOC_WIPHY_ESCAN1)
++		return wlan_static_scan_buf1;
++
++	if (section == DHD_PREALLOC_OSL_BUF) {
++		if (size > DHD_PREALLOC_OSL_BUF_SIZE) {
++			pr_err("request OSL_BUF(%lu) > %ld\n",
++				size, DHD_PREALLOC_OSL_BUF_SIZE);
++			return NULL;
++		}
++		return wlan_static_osl_buf;
++	}
++
++	if (section == DHD_PREALLOC_DHD_INFO) {
++		if (size > DHD_PREALLOC_DHD_INFO_SIZE) {
++			pr_err("request DHD_INFO size(%lu) > %d\n",
++				size, DHD_PREALLOC_DHD_INFO_SIZE);
++			return NULL;
++		}
++		return wlan_static_dhd_info_buf;
++	}
++	if (section == DHD_PREALLOC_DHD_WLFC_INFO) {
++		if (size > WLAN_DHD_WLFC_BUF_SIZE) {
++			pr_err("request DHD_WLFC_INFO size(%lu) > %d\n",
++				size, WLAN_DHD_WLFC_BUF_SIZE);
++			return NULL;
++		}
++		return wlan_static_dhd_wlfc_info_buf;
++	}
++#ifdef BCMDHD_PCIE
++	if (section == DHD_PREALLOC_IF_FLOW_LKUP)  {
++		if (size > DHD_PREALLOC_IF_FLOW_LKUP_SIZE) {
++			pr_err("request DHD_IF_FLOW_LKUP size(%lu) > %d\n",
++				size, DHD_PREALLOC_IF_FLOW_LKUP_SIZE);
++			return NULL;
++		}
++
++		return wlan_static_if_flow_lkup;
++	}
++#endif /* BCMDHD_PCIE */
++	if (section == DHD_PREALLOC_MEMDUMP_RAM) {
++		if (size > DHD_PREALLOC_MEMDUMP_RAM_SIZE) {
++			pr_err("request DHD_PREALLOC_MEMDUMP_RAM_SIZE(%lu) > %d\n",
++				size, DHD_PREALLOC_MEMDUMP_RAM_SIZE);
++			return NULL;
++		}
++
++		return wlan_static_dhd_memdump_ram_buf;
++	}
++	if (section == DHD_PREALLOC_DHD_WLFC_HANGER) {
++		if (size > DHD_PREALLOC_DHD_WLFC_HANGER_SIZE) {
++			pr_err("request DHD_WLFC_HANGER size(%lu) > %d\n",
++				size, DHD_PREALLOC_DHD_WLFC_HANGER_SIZE);
++			return NULL;
++		}
++		return wlan_static_dhd_wlfc_hanger_buf;
++	}
++	if (section == DHD_PREALLOC_WL_ESCAN) {
++		if (size > DHD_PREALLOC_WL_ESCAN_SIZE) {
++			pr_err("request DHD_PREALLOC_WL_ESCAN_SIZE(%lu) > %d\n",
++				size, DHD_PREALLOC_WL_ESCAN_SIZE);
++			return NULL;
++		}
++
++		return wlan_static_wl_escan_info_buf;
++	}
++	if (section == DHD_PREALLOC_FW_VERBOSE_RING) {
++		if (size > FW_VERBOSE_RING_SIZE) {
++			pr_err("request DHD_PREALLOC_FW_VERBOSE_RING(%lu) > %d\n",
++				size, FW_VERBOSE_RING_SIZE);
++			return NULL;
++		}
++
++		return wlan_static_fw_verbose_ring_buf;
++	}
++	if (section == DHD_PREALLOC_FW_EVENT_RING) {
++		if (size > FW_EVENT_RING_SIZE) {
++			pr_err("request DHD_PREALLOC_FW_EVENT_RING(%lu) > %d\n",
++				size, FW_EVENT_RING_SIZE);
++			return NULL;
++		}
++
++		return wlan_static_fw_event_ring_buf;
++	}
++	if (section == DHD_PREALLOC_DHD_EVENT_RING) {
++		if (size > DHD_EVENT_RING_SIZE) {
++			pr_err("request DHD_PREALLOC_DHD_EVENT_RING(%lu) > %d\n",
++				size, DHD_EVENT_RING_SIZE);
++			return NULL;
++		}
++
++		return wlan_static_dhd_event_ring_buf;
++	}
++	if (section == DHD_PREALLOC_NAN_EVENT_RING) {
++		if (size > NAN_EVENT_RING_SIZE) {
++			pr_err("request DHD_PREALLOC_NAN_EVENT_RING(%lu) > %d\n",
++				size, NAN_EVENT_RING_SIZE);
++			return NULL;
++		}
++
++		return wlan_static_nan_event_ring_buf;
++	}
++	if ((section < 0) || (section > DHD_PREALLOC_MAX))
++		pr_err("request section id(%d) is out of max index %d\n",
++				section, DHD_PREALLOC_MAX);
++
++	pr_err("%s: failed to alloc section %d, size=%ld\n",
++		__func__, section, size);
++
++	return NULL;
++}
++EXPORT_SYMBOL(dhd_wlan_mem_prealloc);
++
++static int dhd_init_wlan_mem(void)
++{
++	int i;
++	int j;
++	printk(KERN_ERR "%s(): %s\n", __func__, DHD_STATIC_VERSION_STR);
++
++	for (i = 0; i < DHD_SKB_1PAGE_BUF_NUM; i++) {
++		wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_1PAGE_BUFSIZE);
++		if (!wlan_static_skb[i]) {
++			goto err_skb_alloc;
++		}
++		pr_err("%s: sectoin %d skb[%d], size=%ld\n", __func__,
++			DHD_PREALLOC_SKB_BUF, i, DHD_SKB_1PAGE_BUFSIZE);
++	}
++
++	for (i = DHD_SKB_1PAGE_BUF_NUM; i < WLAN_SKB_1_2PAGE_BUF_NUM; i++) {
++		wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_2PAGE_BUFSIZE);
++		if (!wlan_static_skb[i]) {
++			goto err_skb_alloc;
++		}
++		pr_err("%s: sectoin %d skb[%d], size=%ld\n", __func__,
++			DHD_PREALLOC_SKB_BUF, i, DHD_SKB_2PAGE_BUFSIZE);
++	}
++
++#if defined(BCMDHD_SDIO)
++	wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_4PAGE_BUFSIZE);
++	if (!wlan_static_skb[i])
++		goto err_skb_alloc;
++	pr_err("%s: sectoin %d skb[%d], size=%ld\n", __func__,
++		DHD_PREALLOC_SKB_BUF, i, DHD_SKB_4PAGE_BUFSIZE);
++#endif /* BCMDHD_SDIO */
++
++	wlan_static_prot = kmalloc(DHD_PREALLOC_PROT_SIZE, GFP_KERNEL);
++	if (!wlan_static_prot)
++		goto err_mem_alloc;
++	pr_err("%s: sectoin %d, size=%d\n", __func__,
++		DHD_PREALLOC_PROT, DHD_PREALLOC_PROT_SIZE);
++
++#if defined(BCMDHD_SDIO)
++	wlan_static_rxbuf = kmalloc(DHD_PREALLOC_RXBUF_SIZE, GFP_KERNEL);
++	if (!wlan_static_rxbuf)
++		goto err_mem_alloc;
++	pr_err("%s: sectoin %d, size=%d\n", __func__,
++		DHD_PREALLOC_RXBUF, DHD_PREALLOC_RXBUF_SIZE);
++
++	wlan_static_databuf = kmalloc(DHD_PREALLOC_DATABUF_SIZE, GFP_KERNEL);
++	if (!wlan_static_databuf)
++		goto err_mem_alloc;
++	pr_err("%s: sectoin %d, size=%d\n", __func__,
++		DHD_PREALLOC_DATABUF, DHD_PREALLOC_DATABUF_SIZE);
++#endif /* BCMDHD_SDIO */
++
++	wlan_static_osl_buf = kmalloc(DHD_PREALLOC_OSL_BUF_SIZE, GFP_KERNEL);
++	if (!wlan_static_osl_buf)
++		goto err_mem_alloc;
++	pr_err("%s: sectoin %d, size=%ld\n", __func__,
++		DHD_PREALLOC_OSL_BUF, DHD_PREALLOC_OSL_BUF_SIZE);
++
++	wlan_static_scan_buf0 = kmalloc(DHD_PREALLOC_WIPHY_ESCAN0_SIZE, GFP_KERNEL);
++	if (!wlan_static_scan_buf0)
++		goto err_mem_alloc;
++	pr_err("%s: sectoin %d, size=%d\n", __func__,
++		DHD_PREALLOC_WIPHY_ESCAN0, DHD_PREALLOC_WIPHY_ESCAN0_SIZE);
++
++	wlan_static_dhd_info_buf = kmalloc(DHD_PREALLOC_DHD_INFO_SIZE, GFP_KERNEL);
++	if (!wlan_static_dhd_info_buf)
++		goto err_mem_alloc;
++	pr_err("%s: sectoin %d, size=%d\n", __func__,
++		DHD_PREALLOC_DHD_INFO, DHD_PREALLOC_DHD_INFO_SIZE);
++
++	wlan_static_dhd_wlfc_info_buf = kmalloc(WLAN_DHD_WLFC_BUF_SIZE, GFP_KERNEL);
++	if (!wlan_static_dhd_wlfc_info_buf)
++		goto err_mem_alloc;
++	pr_err("%s: sectoin %d, size=%d\n", __func__,
++		DHD_PREALLOC_DHD_WLFC_INFO, WLAN_DHD_WLFC_BUF_SIZE);
++
++#ifdef BCMDHD_PCIE
++	wlan_static_if_flow_lkup = kmalloc(DHD_PREALLOC_IF_FLOW_LKUP_SIZE, GFP_KERNEL);
++	if (!wlan_static_if_flow_lkup)
++		goto err_mem_alloc;
++	pr_err("%s: sectoin %d, size=%d\n", __func__,
++		DHD_PREALLOC_IF_FLOW_LKUP, DHD_PREALLOC_IF_FLOW_LKUP_SIZE);
++#endif /* BCMDHD_PCIE */
++
++	wlan_static_dhd_memdump_ram_buf = kmalloc(DHD_PREALLOC_MEMDUMP_RAM_SIZE, GFP_KERNEL);
++	if (!wlan_static_dhd_memdump_ram_buf)
++		goto err_mem_alloc;
++	pr_err("%s: sectoin %d, size=%d\n", __func__,
++		DHD_PREALLOC_MEMDUMP_RAM, DHD_PREALLOC_MEMDUMP_RAM_SIZE);
++
++	wlan_static_dhd_wlfc_hanger_buf = kmalloc(DHD_PREALLOC_DHD_WLFC_HANGER_SIZE, GFP_KERNEL);
++	if (!wlan_static_dhd_wlfc_hanger_buf)
++		goto err_mem_alloc;
++	pr_err("%s: sectoin %d, size=%d\n", __func__,
++		DHD_PREALLOC_DHD_WLFC_HANGER, DHD_PREALLOC_DHD_WLFC_HANGER_SIZE);
++
++	wlan_static_wl_escan_info_buf = kmalloc(DHD_PREALLOC_WL_ESCAN_SIZE, GFP_KERNEL);
++	if (!wlan_static_wl_escan_info_buf)
++		goto err_mem_alloc;
++	pr_err("%s: sectoin %d, size=%d\n", __func__,
++		DHD_PREALLOC_WL_ESCAN, DHD_PREALLOC_WL_ESCAN_SIZE);
++
++	wlan_static_fw_verbose_ring_buf = kmalloc(FW_VERBOSE_RING_SIZE, GFP_KERNEL);
++	if (!wlan_static_fw_verbose_ring_buf)
++		goto err_mem_alloc;
++	pr_err("%s: sectoin %d, size=%d\n", __func__,
++		DHD_PREALLOC_FW_VERBOSE_RING, FW_VERBOSE_RING_SIZE);
++
++	wlan_static_fw_event_ring_buf = kmalloc(FW_EVENT_RING_SIZE, GFP_KERNEL);
++	if (!wlan_static_fw_event_ring_buf)
++		goto err_mem_alloc;
++	pr_err("%s: sectoin %d, size=%d\n", __func__,
++		DHD_PREALLOC_FW_EVENT_RING, FW_EVENT_RING_SIZE);
++
++	wlan_static_dhd_event_ring_buf = kmalloc(DHD_EVENT_RING_SIZE, GFP_KERNEL);
++	if (!wlan_static_dhd_event_ring_buf)
++		goto err_mem_alloc;
++	pr_err("%s: sectoin %d, size=%d\n", __func__,
++		DHD_PREALLOC_DHD_EVENT_RING, DHD_EVENT_RING_SIZE);
++
++	wlan_static_nan_event_ring_buf = kmalloc(NAN_EVENT_RING_SIZE, GFP_KERNEL);
++	if (!wlan_static_nan_event_ring_buf)
++		goto err_mem_alloc;
++	pr_err("%s: sectoin %d, size=%d\n", __func__,
++		DHD_PREALLOC_NAN_EVENT_RING, NAN_EVENT_RING_SIZE);
++
++	return 0;
++
++err_mem_alloc:
++
++	if (wlan_static_prot)
++		kfree(wlan_static_prot);
++
++#if defined(BCMDHD_SDIO)
++	if (wlan_static_rxbuf)
++		kfree(wlan_static_rxbuf);
++
++	if (wlan_static_databuf)
++		kfree(wlan_static_databuf);
++#endif /* BCMDHD_SDIO */
++
++	if (wlan_static_osl_buf)
++		kfree(wlan_static_osl_buf);
++
++	if (wlan_static_scan_buf0)
++		kfree(wlan_static_scan_buf0);
++
++	if (wlan_static_scan_buf1)
++		kfree(wlan_static_scan_buf1);
++
++	if (wlan_static_dhd_info_buf)
++		kfree(wlan_static_dhd_info_buf);
++
++	if (wlan_static_dhd_wlfc_info_buf)
++		kfree(wlan_static_dhd_wlfc_info_buf);
++
++#ifdef BCMDHD_PCIE
++	if (wlan_static_if_flow_lkup)
++		kfree(wlan_static_if_flow_lkup);
++#endif /* BCMDHD_PCIE */
++
++	if (wlan_static_dhd_memdump_ram_buf)
++		kfree(wlan_static_dhd_memdump_ram_buf);
++
++	if (wlan_static_dhd_wlfc_hanger_buf)
++		kfree(wlan_static_dhd_wlfc_hanger_buf);
++
++	if (wlan_static_wl_escan_info_buf)
++		kfree(wlan_static_wl_escan_info_buf);
++
++#ifdef BCMDHD_PCIE
++	if (wlan_static_fw_verbose_ring_buf)
++		kfree(wlan_static_fw_verbose_ring_buf);
++
++	if (wlan_static_fw_event_ring_buf)
++		kfree(wlan_static_fw_event_ring_buf);
++
++	if (wlan_static_dhd_event_ring_buf)
++		kfree(wlan_static_dhd_event_ring_buf);
++
++	if (wlan_static_nan_event_ring_buf)
++		kfree(wlan_static_nan_event_ring_buf);
++#endif /* BCMDHD_PCIE */
++
++	pr_err("%s: Failed to mem_alloc for WLAN\n", __func__);
++
++	i = WLAN_SKB_BUF_NUM;
++
++err_skb_alloc:
++	pr_err("%s: Failed to skb_alloc for WLAN\n", __func__);
++	for (j = 0; j < i; j++)
++		dev_kfree_skb(wlan_static_skb[j]);
++
++	return -ENOMEM;
++}
++
++static int __init
++dhd_static_buf_init(void)
++{
++	dhd_init_wlan_mem();
++
++	return 0;
++}
++
++static void __exit
++dhd_static_buf_exit(void)
++{
++	int i;
++
++	pr_err("%s()\n", __FUNCTION__);
++
++	for (i = 0; i < DHD_SKB_1PAGE_BUF_NUM; i++) {
++		if (wlan_static_skb[i])
++			dev_kfree_skb(wlan_static_skb[i]);
++	}
++
++	for (i = DHD_SKB_1PAGE_BUF_NUM; i < WLAN_SKB_1_2PAGE_BUF_NUM; i++) {
++		if (wlan_static_skb[i])
++			dev_kfree_skb(wlan_static_skb[i]);
++	}
++
++#if defined(BCMDHD_SDIO)
++	if (wlan_static_skb[i])
++		dev_kfree_skb(wlan_static_skb[i]);
++#endif /* BCMDHD_SDIO */
++
++	if (wlan_static_prot)
++		kfree(wlan_static_prot);
++
++#if defined(BCMDHD_SDIO)
++	if (wlan_static_rxbuf)
++		kfree(wlan_static_rxbuf);
++
++	if (wlan_static_databuf)
++		kfree(wlan_static_databuf);
++#endif /* BCMDHD_SDIO */
++
++	if (wlan_static_osl_buf)
++		kfree(wlan_static_osl_buf);
++
++	if (wlan_static_scan_buf0)
++		kfree(wlan_static_scan_buf0);
++
++	if (wlan_static_scan_buf1)
++		kfree(wlan_static_scan_buf1);
++
++	if (wlan_static_dhd_info_buf)
++		kfree(wlan_static_dhd_info_buf);
++
++	if (wlan_static_dhd_wlfc_info_buf)
++		kfree(wlan_static_dhd_wlfc_info_buf);
++
++#ifdef BCMDHD_PCIE
++	if (wlan_static_if_flow_lkup)
++		kfree(wlan_static_if_flow_lkup);
++#endif /* BCMDHD_PCIE */
++
++	if (wlan_static_dhd_memdump_ram_buf)
++		kfree(wlan_static_dhd_memdump_ram_buf);
++
++	if (wlan_static_dhd_wlfc_hanger_buf)
++		kfree(wlan_static_dhd_wlfc_hanger_buf);
++
++	if (wlan_static_wl_escan_info_buf)
++		kfree(wlan_static_wl_escan_info_buf);
++
++#ifdef BCMDHD_PCIE
++	if (wlan_static_fw_verbose_ring_buf)
++		kfree(wlan_static_fw_verbose_ring_buf);
++
++	if (wlan_static_fw_event_ring_buf)
++		kfree(wlan_static_fw_event_ring_buf);
++
++	if (wlan_static_dhd_event_ring_buf)
++		kfree(wlan_static_dhd_event_ring_buf);
++
++	if (wlan_static_nan_event_ring_buf)
++		kfree(wlan_static_nan_event_ring_buf);
++#endif
++
++	return;
++}
++
++module_init(dhd_static_buf_init);
++
++module_exit(dhd_static_buf_exit);
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_wlfc.c b/module_drivers/drivers/net/wireless/bcmdhd/dhd_wlfc.c
+new file mode 100644
+index 000000000..1768c90e0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_wlfc.c
+@@ -0,0 +1,4567 @@
++/*
++ * DHD PROP_TXSTATUS Module.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_wlfc.c 679733 2017-01-17 06:40:39Z $
++ *
++ */
++
++
++#include <typedefs.h>
++#include <osl.h>
++
++#include <bcmutils.h>
++#include <bcmendian.h>
++
++#include <dngl_stats.h>
++#include <dhd.h>
++
++#include <dhd_bus.h>
++
++#include <dhd_dbg.h>
++#include <dhd_config.h>
++
++#ifdef PROP_TXSTATUS /* a form of flow control between host and dongle */
++#include <wlfc_proto.h>
++#include <dhd_wlfc.h>
++#endif
++
++#ifdef DHDTCPACK_SUPPRESS
++#include <dhd_ip.h>
++#endif /* DHDTCPACK_SUPPRESS */
++
++
++/*
++ * wlfc naming and lock rules:
++ *
++ * 1. Private functions name like _dhd_wlfc_XXX, declared as static and avoid wlfc lock operation.
++ * 2. Public functions name like dhd_wlfc_XXX, use wlfc lock if needed.
++ * 3. Non-Proptxstatus module call public functions only and avoid wlfc lock operation.
++ *
++ */
++
++#if defined(DHD_WLFC_THREAD)
++#define WLFC_THREAD_QUICK_RETRY_WAIT_MS    10      /* 10 msec */
++#define WLFC_THREAD_RETRY_WAIT_MS          10000   /* 10 sec */
++#endif /* defined (DHD_WLFC_THREAD) */
++
++
++#ifdef PROP_TXSTATUS
++
++#define DHD_WLFC_QMON_COMPLETE(entry)
++
++
++/** reordering related */
++
++#if defined(DHD_WLFC_THREAD)
++static void
++_dhd_wlfc_thread_wakeup(dhd_pub_t *dhdp)
++{
++	dhdp->wlfc_thread_go = TRUE;
++	wake_up_interruptible(&dhdp->wlfc_wqhead);
++}
++#endif /* DHD_WLFC_THREAD */
++
++static uint16
++_dhd_wlfc_adjusted_seq(void* p, uint8 current_seq)
++{
++	uint16 seq;
++
++	if (!p) {
++		return 0xffff;
++	}
++
++	seq = WL_TXSTATUS_GET_FREERUNCTR(DHD_PKTTAG_H2DTAG(PKTTAG(p)));
++	if (seq < current_seq) {
++		/* wrap around */
++		seq += 256;
++	}
++
++	return seq;
++}
++
++/**
++ * Enqueue a caller supplied packet on a caller supplied precedence queue, optionally reorder
++ * suppressed packets.
++ *    @param[in] pq       caller supplied packet queue to enqueue the packet on
++ *    @param[in] prec     precedence of the to-be-queued packet
++ *    @param[in] p        transmit packet to enqueue
++ *    @param[in] qHead    if TRUE, enqueue to head instead of tail. Used to maintain d11 seq order.
++ *    @param[in] current_seq
++ *    @param[in] reOrder  reOrder on odd precedence (=suppress queue)
++ */
++static void
++_dhd_wlfc_prec_enque(struct pktq *pq, int prec, void* p, bool qHead,
++	uint8 current_seq, bool reOrder)
++{
++	struct pktq_prec *q;
++	uint16 seq, seq2;
++	void *p2, *p2_prev;
++
++	if (!p)
++		return;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++	ASSERT(PKTLINK(p) == NULL);		/* queueing chains not allowed */
++
++	ASSERT(!pktq_full(pq));
++	ASSERT(!pktq_pfull(pq, prec));
++
++	q = &pq->q[prec];
++
++	PKTSETLINK(p, NULL);
++	if (q->head == NULL) {
++		/* empty queue */
++		q->head = p;
++		q->tail = p;
++	} else {
++		if (reOrder && (prec & 1)) {
++			seq = _dhd_wlfc_adjusted_seq(p, current_seq);
++			p2 = qHead ? q->head : q->tail;
++			seq2 = _dhd_wlfc_adjusted_seq(p2, current_seq);
++
++			if ((qHead &&((seq+1) > seq2)) || (!qHead && ((seq2+1) > seq))) {
++				/* need reorder */
++				p2 = q->head;
++				p2_prev = NULL;
++				seq2 = _dhd_wlfc_adjusted_seq(p2, current_seq);
++
++				while (seq > seq2) {
++					p2_prev = p2;
++					p2 = PKTLINK(p2);
++					if (!p2) {
++						break;
++					}
++					seq2 = _dhd_wlfc_adjusted_seq(p2, current_seq);
++				}
++
++				if (p2_prev == NULL) {
++					/* insert head */
++					PKTSETLINK(p, q->head);
++					q->head = p;
++				} else if (p2 == NULL) {
++					/* insert tail */
++					PKTSETLINK(p2_prev, p);
++					q->tail = p;
++				} else {
++					/* insert after p2_prev */
++					PKTSETLINK(p, PKTLINK(p2_prev));
++					PKTSETLINK(p2_prev, p);
++				}
++				goto exit;
++			}
++		}
++
++		if (qHead) {
++			PKTSETLINK(p, q->head);
++			q->head = p;
++		} else {
++			PKTSETLINK(q->tail, p);
++			q->tail = p;
++		}
++	}
++
++exit:
++
++	q->len++;
++	pq->len++;
++
++	if (pq->hi_prec < prec)
++		pq->hi_prec = (uint8)prec;
++} /* _dhd_wlfc_prec_enque */
++
++/**
++ * Create a place to store all packet pointers submitted to the firmware until a status comes back,
++ * suppress or otherwise.
++ *
++ * hang-er: noun, a contrivance on which things are hung, as a hook.
++ */
++/** @deprecated soon */
++static void*
++_dhd_wlfc_hanger_create(dhd_pub_t *dhd, int max_items)
++{
++	int i;
++	wlfc_hanger_t* hanger;
++
++	/* allow only up to a specific size for now */
++	ASSERT(max_items == WLFC_HANGER_MAXITEMS);
++
++	if ((hanger = (wlfc_hanger_t*)DHD_OS_PREALLOC(dhd, DHD_PREALLOC_DHD_WLFC_HANGER,
++		WLFC_HANGER_SIZE(max_items))) == NULL) {
++		return NULL;
++	}
++	memset(hanger, 0, WLFC_HANGER_SIZE(max_items));
++	hanger->max_items = max_items;
++
++	for (i = 0; i < hanger->max_items; i++) {
++		hanger->items[i].state = WLFC_HANGER_ITEM_STATE_FREE;
++	}
++	return hanger;
++}
++
++/** @deprecated soon */
++static int
++_dhd_wlfc_hanger_delete(dhd_pub_t *dhd, void* hanger)
++{
++	wlfc_hanger_t* h = (wlfc_hanger_t*)hanger;
++
++	if (h) {
++		DHD_OS_PREFREE(dhd, h, WLFC_HANGER_SIZE(h->max_items));
++		return BCME_OK;
++	}
++	return BCME_BADARG;
++}
++
++/** @deprecated soon */
++static uint16
++_dhd_wlfc_hanger_get_free_slot(void* hanger)
++{
++	uint32 i;
++	wlfc_hanger_t* h = (wlfc_hanger_t*)hanger;
++
++	if (h) {
++		i = h->slot_pos + 1;
++		if (i == h->max_items) {
++			i = 0;
++		}
++		while (i != h->slot_pos) {
++			if (h->items[i].state == WLFC_HANGER_ITEM_STATE_FREE) {
++				h->slot_pos = i;
++				return (uint16)i;
++			}
++			i++;
++			if (i == h->max_items)
++				i = 0;
++		}
++		h->failed_slotfind++;
++	}
++	return WLFC_HANGER_MAXITEMS;
++}
++
++/** @deprecated soon */
++static int
++_dhd_wlfc_hanger_get_genbit(void* hanger, void* pkt, uint32 slot_id, int* gen)
++{
++	int rc = BCME_OK;
++	wlfc_hanger_t* h = (wlfc_hanger_t*)hanger;
++
++	*gen = 0xff;
++
++	/* this packet was not pushed at the time it went to the firmware */
++	if (slot_id == WLFC_HANGER_MAXITEMS)
++		return BCME_NOTFOUND;
++
++	if (h) {
++		if (h->items[slot_id].state != WLFC_HANGER_ITEM_STATE_FREE) {
++			*gen = h->items[slot_id].gen;
++		}
++		else {
++			DHD_ERROR(("Error: %s():%d item not used\n",
++				__FUNCTION__, __LINE__));
++			rc = BCME_NOTFOUND;
++		}
++
++	} else {
++		rc = BCME_BADARG;
++	}
++
++	return rc;
++}
++
++/** @deprecated soon */
++static int
++_dhd_wlfc_hanger_pushpkt(void* hanger, void* pkt, uint32 slot_id)
++{
++	int rc = BCME_OK;
++	wlfc_hanger_t* h = (wlfc_hanger_t*)hanger;
++
++	if (h && (slot_id < WLFC_HANGER_MAXITEMS)) {
++		if (h->items[slot_id].state == WLFC_HANGER_ITEM_STATE_FREE) {
++			h->items[slot_id].state = WLFC_HANGER_ITEM_STATE_INUSE;
++			h->items[slot_id].pkt = pkt;
++			h->items[slot_id].pkt_state = 0;
++			h->items[slot_id].pkt_txstatus = 0;
++			h->pushed++;
++		} else {
++			h->failed_to_push++;
++			rc = BCME_NOTFOUND;
++		}
++	} else {
++		rc = BCME_BADARG;
++	}
++
++	return rc;
++}
++
++/** @deprecated soon */
++static int
++_dhd_wlfc_hanger_poppkt(void* hanger, uint32 slot_id, void** pktout, bool remove_from_hanger)
++{
++	int rc = BCME_OK;
++	wlfc_hanger_t* h = (wlfc_hanger_t*)hanger;
++
++	*pktout = NULL;
++
++	/* this packet was not pushed at the time it went to the firmware */
++	if (slot_id == WLFC_HANGER_MAXITEMS)
++		return BCME_NOTFOUND;
++
++	if (h) {
++		if (h->items[slot_id].state != WLFC_HANGER_ITEM_STATE_FREE) {
++			*pktout = h->items[slot_id].pkt;
++			if (remove_from_hanger) {
++				h->items[slot_id].state =
++					WLFC_HANGER_ITEM_STATE_FREE;
++				h->items[slot_id].pkt = NULL;
++				h->items[slot_id].gen = 0xff;
++				h->items[slot_id].identifier = 0;
++				h->popped++;
++			}
++		} else {
++			h->failed_to_pop++;
++			rc = BCME_NOTFOUND;
++		}
++	} else {
++		rc = BCME_BADARG;
++	}
++
++	return rc;
++}
++
++/** @deprecated soon */
++static int
++_dhd_wlfc_hanger_mark_suppressed(void* hanger, uint32 slot_id, uint8 gen)
++{
++	int rc = BCME_OK;
++	wlfc_hanger_t* h = (wlfc_hanger_t*)hanger;
++
++	/* this packet was not pushed at the time it went to the firmware */
++	if (slot_id == WLFC_HANGER_MAXITEMS)
++		return BCME_NOTFOUND;
++	if (h) {
++		h->items[slot_id].gen = gen;
++		if (h->items[slot_id].state == WLFC_HANGER_ITEM_STATE_INUSE) {
++			h->items[slot_id].state = WLFC_HANGER_ITEM_STATE_INUSE_SUPPRESSED;
++		} else {
++			rc = BCME_BADARG;
++		}
++	} else {
++		rc = BCME_BADARG;
++	}
++
++	return rc;
++}
++
++/** remove reference of specific packet in hanger */
++/** @deprecated soon */
++static bool
++_dhd_wlfc_hanger_remove_reference(wlfc_hanger_t* h, void* pkt)
++{
++	int i;
++
++	if (!h || !pkt) {
++		return FALSE;
++	}
++
++	i = WL_TXSTATUS_GET_HSLOT(DHD_PKTTAG_H2DTAG(PKTTAG(pkt)));
++
++	if ((i < h->max_items) && (pkt == h->items[i].pkt)) {
++		if (h->items[i].state == WLFC_HANGER_ITEM_STATE_INUSE_SUPPRESSED) {
++			h->items[i].state = WLFC_HANGER_ITEM_STATE_FREE;
++			h->items[i].pkt = NULL;
++			h->items[i].gen = 0xff;
++			h->items[i].identifier = 0;
++			return TRUE;
++		} else {
++			DHD_ERROR(("Error: %s():%d item not suppressed\n",
++				__FUNCTION__, __LINE__));
++		}
++	}
++
++	return FALSE;
++}
++
++/** afq = At Firmware Queue, queue containing packets pending in the dongle */
++static int
++_dhd_wlfc_enque_afq(athost_wl_status_info_t* ctx, void *p)
++{
++	wlfc_mac_descriptor_t* entry;
++	uint16 entry_idx = WL_TXSTATUS_GET_HSLOT(DHD_PKTTAG_H2DTAG(PKTTAG(p)));
++	uint8 prec = DHD_PKTTAG_FIFO(PKTTAG(p));
++
++	if (entry_idx < WLFC_MAC_DESC_TABLE_SIZE)
++		entry  = &ctx->destination_entries.nodes[entry_idx];
++	else if (entry_idx < (WLFC_MAC_DESC_TABLE_SIZE + WLFC_MAX_IFNUM))
++		entry = &ctx->destination_entries.interfaces[entry_idx - WLFC_MAC_DESC_TABLE_SIZE];
++	else
++		entry = &ctx->destination_entries.other;
++
++	pktq_penq(&entry->afq, prec, p);
++
++	return BCME_OK;
++}
++
++/** afq = At Firmware Queue, queue containing packets pending in the dongle */
++static int
++_dhd_wlfc_deque_afq(athost_wl_status_info_t* ctx, uint16 hslot, uint8 hcnt, uint8 prec,
++	void **pktout)
++{
++	wlfc_mac_descriptor_t *entry;
++	struct pktq *pq;
++	struct pktq_prec *q;
++	void *p, *b;
++
++	if (!ctx) {
++		DHD_ERROR(("%s: ctx(%p), pktout(%p)\n", __FUNCTION__, ctx, pktout));
++		return BCME_BADARG;
++	}
++
++	if (pktout) {
++		*pktout = NULL;
++	}
++
++	ASSERT(hslot < (WLFC_MAC_DESC_TABLE_SIZE + WLFC_MAX_IFNUM + 1));
++
++	if (hslot < WLFC_MAC_DESC_TABLE_SIZE)
++		entry  = &ctx->destination_entries.nodes[hslot];
++	else if (hslot < (WLFC_MAC_DESC_TABLE_SIZE + WLFC_MAX_IFNUM))
++		entry = &ctx->destination_entries.interfaces[hslot - WLFC_MAC_DESC_TABLE_SIZE];
++	else
++		entry = &ctx->destination_entries.other;
++
++	pq = &entry->afq;
++
++	ASSERT(prec < pq->num_prec);
++
++	q = &pq->q[prec];
++
++	b = NULL;
++	p = q->head;
++
++	while (p && (hcnt != WL_TXSTATUS_GET_FREERUNCTR(DHD_PKTTAG_H2DTAG(PKTTAG(p)))))
++	{
++		b = p;
++		p = PKTLINK(p);
++	}
++
++	if (p == NULL) {
++		/* none is matched */
++		if (b) {
++			DHD_ERROR(("%s: can't find matching seq(%d)\n", __FUNCTION__, hcnt));
++		} else {
++			DHD_ERROR(("%s: queue is empty\n", __FUNCTION__));
++		}
++
++		return BCME_ERROR;
++	}
++
++	bcm_pkt_validate_chk(p);
++
++	if (!b) {
++		/* head packet is matched */
++		if ((q->head = PKTLINK(p)) == NULL) {
++			q->tail = NULL;
++		}
++	} else {
++		/* middle packet is matched */
++		DHD_INFO(("%s: out of order, seq(%d), head_seq(%d)\n", __FUNCTION__, hcnt,
++			WL_TXSTATUS_GET_FREERUNCTR(DHD_PKTTAG_H2DTAG(PKTTAG(q->head)))));
++		ctx->stats.ooo_pkts[prec]++;
++		PKTSETLINK(b, PKTLINK(p));
++		if (PKTLINK(p) == NULL) {
++			q->tail = b;
++		}
++	}
++
++	q->len--;
++	pq->len--;
++
++	PKTSETLINK(p, NULL);
++
++	if (pktout) {
++		*pktout = p;
++	}
++
++	return BCME_OK;
++} /* _dhd_wlfc_deque_afq */
++
++/**
++ * Flow control information piggy backs on packets, in the form of one or more TLVs. This function
++ * pushes one or more TLVs onto a packet that is going to be sent towards the dongle.
++ *
++ *     @param[in]     ctx
++ *     @param[in/out] packet
++ *     @param[in]     tim_signal TRUE if parameter 'tim_bmp' is valid
++ *     @param[in]     tim_bmp
++ *     @param[in]     mac_handle
++ *     @param[in]     htodtag
++ *     @param[in]     htodseq d11 seqno for seqno reuse, only used if 'seq reuse' was agreed upon
++ *                    earlier between host and firmware.
++ *     @param[in]     skip_wlfc_hdr
++ */
++static int
++_dhd_wlfc_pushheader(athost_wl_status_info_t* ctx, void** packet, bool tim_signal,
++	uint8 tim_bmp, uint8 mac_handle, uint32 htodtag, uint16 htodseq, bool skip_wlfc_hdr)
++{
++	uint32 wl_pktinfo = 0;
++	uint8* wlh;
++	uint8 dataOffset = 0;
++	uint8 fillers;
++	uint8 tim_signal_len = 0;
++	dhd_pub_t *dhdp = (dhd_pub_t *)ctx->dhdp;
++
++	struct bdc_header *h;
++	void *p = *packet;
++
++	if (skip_wlfc_hdr)
++		goto push_bdc_hdr;
++
++	if (tim_signal) {
++		tim_signal_len = TLV_HDR_LEN + WLFC_CTL_VALUE_LEN_PENDING_TRAFFIC_BMP;
++	}
++
++	/* +2 is for Type[1] and Len[1] in TLV, plus TIM signal */
++	dataOffset = WLFC_CTL_VALUE_LEN_PKTTAG + TLV_HDR_LEN + tim_signal_len;
++	if (WLFC_GET_REUSESEQ(dhdp->wlfc_mode)) {
++		dataOffset += WLFC_CTL_VALUE_LEN_SEQ;
++	}
++
++	fillers = ROUNDUP(dataOffset, 4) - dataOffset;
++	dataOffset += fillers;
++
++	PKTPUSH(ctx->osh, p, dataOffset);
++	wlh = (uint8*) PKTDATA(ctx->osh, p);
++
++	wl_pktinfo = htol32(htodtag);
++
++	wlh[TLV_TAG_OFF] = WLFC_CTL_TYPE_PKTTAG;
++	wlh[TLV_LEN_OFF] = WLFC_CTL_VALUE_LEN_PKTTAG;
++	memcpy(&wlh[TLV_HDR_LEN] /* dst */, &wl_pktinfo, sizeof(uint32));
++
++	if (WLFC_GET_REUSESEQ(dhdp->wlfc_mode)) {
++		uint16 wl_seqinfo = htol16(htodseq);
++		wlh[TLV_LEN_OFF] += WLFC_CTL_VALUE_LEN_SEQ;
++		memcpy(&wlh[TLV_HDR_LEN + WLFC_CTL_VALUE_LEN_PKTTAG], &wl_seqinfo,
++			WLFC_CTL_VALUE_LEN_SEQ);
++	}
++
++	if (tim_signal_len) {
++		wlh[dataOffset - fillers - tim_signal_len ] =
++			WLFC_CTL_TYPE_PENDING_TRAFFIC_BMP;
++		wlh[dataOffset - fillers - tim_signal_len + 1] =
++			WLFC_CTL_VALUE_LEN_PENDING_TRAFFIC_BMP;
++		wlh[dataOffset - fillers - tim_signal_len + 2] = mac_handle;
++		wlh[dataOffset - fillers - tim_signal_len + 3] = tim_bmp;
++	}
++	if (fillers)
++		memset(&wlh[dataOffset - fillers], WLFC_CTL_TYPE_FILLER, fillers);
++
++push_bdc_hdr:
++	PKTPUSH(ctx->osh, p, BDC_HEADER_LEN);
++	h = (struct bdc_header *)PKTDATA(ctx->osh, p);
++	h->flags = (BDC_PROTO_VER << BDC_FLAG_VER_SHIFT);
++	if (PKTSUMNEEDED(p))
++		h->flags |= BDC_FLAG_SUM_NEEDED;
++
++
++	h->priority = (PKTPRIO(p) & BDC_PRIORITY_MASK);
++	h->flags2 = 0;
++	h->dataOffset = dataOffset >> 2;
++	BDC_SET_IF_IDX(h, DHD_PKTTAG_IF(PKTTAG(p)));
++	*packet = p;
++	return BCME_OK;
++} /* _dhd_wlfc_pushheader */
++
++/**
++ * Removes (PULLs) flow control related headers from the caller supplied packet, is invoked eg
++ * when a packet is about to be freed.
++ */
++static int
++_dhd_wlfc_pullheader(athost_wl_status_info_t* ctx, void* pktbuf)
++{
++	struct bdc_header *h;
++
++	if (PKTLEN(ctx->osh, pktbuf) < BDC_HEADER_LEN) {
++		DHD_ERROR(("%s: rx data too short (%d < %d)\n", __FUNCTION__,
++		           PKTLEN(ctx->osh, pktbuf), BDC_HEADER_LEN));
++		return BCME_ERROR;
++	}
++	h = (struct bdc_header *)PKTDATA(ctx->osh, pktbuf);
++
++	/* pull BDC header */
++	PKTPULL(ctx->osh, pktbuf, BDC_HEADER_LEN);
++
++	if (PKTLEN(ctx->osh, pktbuf) < (uint)(h->dataOffset << 2)) {
++		DHD_ERROR(("%s: rx data too short (%d < %d)\n", __FUNCTION__,
++		           PKTLEN(ctx->osh, pktbuf), (h->dataOffset << 2)));
++		return BCME_ERROR;
++	}
++
++	/* pull wl-header */
++	PKTPULL(ctx->osh, pktbuf, (h->dataOffset << 2));
++	return BCME_OK;
++}
++
++/**
++ * @param[in/out] p packet
++ */
++static wlfc_mac_descriptor_t*
++_dhd_wlfc_find_table_entry(athost_wl_status_info_t* ctx, void* p)
++{
++	int i;
++	wlfc_mac_descriptor_t* table = ctx->destination_entries.nodes;
++	uint8 ifid = DHD_PKTTAG_IF(PKTTAG(p));
++	uint8* dstn = DHD_PKTTAG_DSTN(PKTTAG(p));
++	wlfc_mac_descriptor_t* entry = DHD_PKTTAG_ENTRY(PKTTAG(p));
++	int iftype = ctx->destination_entries.interfaces[ifid].iftype;
++
++	/* saved one exists, return it */
++	if (entry)
++		return entry;
++
++	/* Multicast destination, STA and P2P clients get the interface entry.
++	 * STA/GC gets the Mac Entry for TDLS destinations, TDLS destinations
++	 * have their own entry.
++	 */
++	if ((iftype == WLC_E_IF_ROLE_STA || ETHER_ISMULTI(dstn) ||
++		iftype == WLC_E_IF_ROLE_P2P_CLIENT) &&
++		(ctx->destination_entries.interfaces[ifid].occupied)) {
++			entry = &ctx->destination_entries.interfaces[ifid];
++	}
++
++	if (entry && ETHER_ISMULTI(dstn)) {
++		DHD_PKTTAG_SET_ENTRY(PKTTAG(p), entry);
++		return entry;
++	}
++
++	for (i = 0; i < WLFC_MAC_DESC_TABLE_SIZE; i++) {
++		if (table[i].occupied) {
++			if (table[i].interface_id == ifid) {
++				if (!memcmp(table[i].ea, dstn, ETHER_ADDR_LEN)) {
++					entry = &table[i];
++					break;
++				}
++			}
++		}
++	}
++
++	if (entry == NULL)
++		entry = &ctx->destination_entries.other;
++
++	DHD_PKTTAG_SET_ENTRY(PKTTAG(p), entry);
++
++	return entry;
++} /* _dhd_wlfc_find_table_entry */
++
++/**
++ * In case a packet must be dropped (because eg the queues are full), various tallies have to be
++ * be updated. Called from several other functions.
++ *     @param[in] dhdp pointer to public DHD structure
++ *     @param[in] prec precedence of the packet
++ *     @param[in] p    the packet to be dropped
++ *     @param[in] bPktInQ TRUE if packet is part of a queue
++ */
++static int
++_dhd_wlfc_prec_drop(dhd_pub_t *dhdp, int prec, void* p, bool bPktInQ)
++{
++	athost_wl_status_info_t* ctx;
++	void *pout = NULL;
++
++	ASSERT(dhdp && p);
++	ASSERT(prec >= 0 && prec <= WLFC_PSQ_PREC_COUNT);
++
++	ctx = (athost_wl_status_info_t*)dhdp->wlfc_state;
++
++	if (!WLFC_GET_AFQ(dhdp->wlfc_mode) && (prec & 1)) {
++		/* suppressed queue, need pop from hanger */
++		_dhd_wlfc_hanger_poppkt(ctx->hanger, WL_TXSTATUS_GET_HSLOT(DHD_PKTTAG_H2DTAG
++					(PKTTAG(p))), &pout, TRUE);
++		ASSERT(p == pout);
++	}
++
++	if (!(prec & 1)) {
++#ifdef DHDTCPACK_SUPPRESS
++		/* pkt in delayed q, so fake push BDC header for
++		 * dhd_tcpack_check_xmit() and dhd_txcomplete().
++		 */
++		_dhd_wlfc_pushheader(ctx, &p, FALSE, 0, 0, 0, 0, TRUE);
++
++		/* This packet is about to be freed, so remove it from tcp_ack_info_tbl
++		 * This must be one of...
++		 * 1. A pkt already in delayQ is evicted by another pkt with higher precedence
++		 * in _dhd_wlfc_prec_enq_with_drop()
++		 * 2. A pkt could not be enqueued to delayQ because it is full,
++		 * in _dhd_wlfc_enque_delayq().
++		 * 3. A pkt could not be enqueued to delayQ because it is full,
++		 * in _dhd_wlfc_rollback_packet_toq().
++		 */
++		if (dhd_tcpack_check_xmit(dhdp, p) == BCME_ERROR) {
++			DHD_ERROR(("%s %d: tcpack_suppress ERROR!!!"
++				" Stop using it\n",
++				__FUNCTION__, __LINE__));
++			dhd_tcpack_suppress_set(dhdp, TCPACK_SUP_OFF);
++		}
++#endif /* DHDTCPACK_SUPPRESS */
++	}
++
++	if (bPktInQ) {
++		ctx->pkt_cnt_in_q[DHD_PKTTAG_IF(PKTTAG(p))][prec>>1]--;
++		ctx->pkt_cnt_per_ac[prec>>1]--;
++		ctx->pkt_cnt_in_psq--;
++	}
++
++	ctx->pkt_cnt_in_drv[DHD_PKTTAG_IF(PKTTAG(p))][DHD_PKTTAG_FIFO(PKTTAG(p))]--;
++	ctx->stats.pktout++;
++	ctx->stats.drop_pkts[prec]++;
++
++	dhd_txcomplete(dhdp, p, FALSE);
++	PKTFREE(ctx->osh, p, TRUE);
++
++	return 0;
++} /* _dhd_wlfc_prec_drop */
++
++/**
++ * Called when eg the host handed a new packet over to the driver, or when the dongle reported
++ * that a packet could currently not be transmitted (=suppressed). This function enqueues a transmit
++ * packet in the host driver to be (re)transmitted at a later opportunity.
++ *     @param[in] dhdp pointer to public DHD structure
++ *     @param[in] qHead When TRUE, queue packet at head instead of tail, to preserve d11 sequence
++ */
++static bool
++_dhd_wlfc_prec_enq_with_drop(dhd_pub_t *dhdp, struct pktq *pq, void *pkt, int prec, bool qHead,
++	uint8 current_seq)
++{
++	void *p = NULL;
++	int eprec = -1;		/* precedence to evict from */
++	athost_wl_status_info_t* ctx;
++
++	ASSERT(dhdp && pq && pkt);
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	ctx = (athost_wl_status_info_t*)dhdp->wlfc_state;
++
++	/* Fast case, precedence queue is not full and we are also not
++	 * exceeding total queue length
++	 */
++	if (!pktq_pfull(pq, prec) && !pktq_full(pq)) {
++		goto exit;
++	}
++
++	/* Determine precedence from which to evict packet, if any */
++	if (pktq_pfull(pq, prec)) {
++		eprec = prec;
++	} else if (pktq_full(pq)) {
++		p = pktq_peek_tail(pq, &eprec);
++		if (!p) {
++			DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++			return FALSE;
++		}
++		if ((eprec > prec) || (eprec < 0)) {
++			if (!pktq_pempty(pq, prec)) {
++				eprec = prec;
++			} else {
++				return FALSE;
++			}
++		}
++	}
++
++	/* Evict if needed */
++	if (eprec >= 0) {
++		/* Detect queueing to unconfigured precedence */
++		ASSERT(!pktq_pempty(pq, eprec));
++		/* Evict all fragmented frames */
++		dhd_prec_drop_pkts(dhdp, pq, eprec, _dhd_wlfc_prec_drop);
++	}
++
++exit:
++	/* Enqueue */
++	_dhd_wlfc_prec_enque(pq, prec, pkt, qHead, current_seq,
++		WLFC_GET_REORDERSUPP(dhdp->wlfc_mode));
++	ctx->pkt_cnt_in_q[DHD_PKTTAG_IF(PKTTAG(pkt))][prec>>1]++;
++	ctx->pkt_cnt_per_ac[prec>>1]++;
++	ctx->pkt_cnt_in_psq++;
++
++	return TRUE;
++} /* _dhd_wlfc_prec_enq_with_drop */
++
++/**
++ * Called during eg the 'committing' of a transmit packet from the OS layer to a lower layer, in
++ * the event that this 'commit' failed.
++ */
++static int
++_dhd_wlfc_rollback_packet_toq(athost_wl_status_info_t* ctx,
++	void* p, ewlfc_packet_state_t pkt_type, uint32 hslot)
++{
++	/*
++	 * put the packet back to the head of queue
++	 * - suppressed packet goes back to suppress sub-queue
++	 * - pull out the header, if new or delayed packet
++	 *
++	 * Note: hslot is used only when header removal is done.
++	 */
++	wlfc_mac_descriptor_t* entry;
++	int rc = BCME_OK;
++	int prec, fifo_id;
++
++	entry = _dhd_wlfc_find_table_entry(ctx, p);
++	prec = DHD_PKTTAG_FIFO(PKTTAG(p));
++	fifo_id = prec << 1;
++	if (pkt_type == eWLFC_PKTTYPE_SUPPRESSED)
++		fifo_id += 1;
++	if (entry != NULL) {
++		/*
++		if this packet did not count against FIFO credit, it must have
++		taken a requested_credit from the firmware (for pspoll etc.)
++		*/
++		if ((prec != AC_COUNT) && !DHD_PKTTAG_CREDITCHECK(PKTTAG(p)))
++			entry->requested_credit++;
++
++		if (pkt_type == eWLFC_PKTTYPE_DELAYED) {
++			/* decrement sequence count */
++			WLFC_DECR_SEQCOUNT(entry, prec);
++			/* remove header first */
++			rc = _dhd_wlfc_pullheader(ctx, p);
++			if (rc != BCME_OK) {
++				DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++				goto exit;
++			}
++		}
++
++		if (_dhd_wlfc_prec_enq_with_drop(ctx->dhdp, &entry->psq, p, fifo_id, TRUE,
++			WLFC_SEQCOUNT(entry, fifo_id>>1))
++			== FALSE) {
++			/* enque failed */
++			DHD_ERROR(("Error: %s():%d, fifo_id(%d)\n",
++				__FUNCTION__, __LINE__, fifo_id));
++			rc = BCME_ERROR;
++		}
++	} else {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		rc = BCME_ERROR;
++	}
++
++exit:
++	if (rc != BCME_OK) {
++		ctx->stats.rollback_failed++;
++		_dhd_wlfc_prec_drop(ctx->dhdp, fifo_id, p, FALSE);
++	} else {
++		ctx->stats.rollback++;
++	}
++
++	return rc;
++} /* _dhd_wlfc_rollback_packet_toq */
++
++/** Returns TRUE if host OS -> DHD flow control is allowed on the caller supplied interface */
++static bool
++_dhd_wlfc_allow_fc(athost_wl_status_info_t* ctx, uint8 ifid)
++{
++	int prec, ac_traffic = WLFC_NO_TRAFFIC;
++
++	for (prec = 0; prec < AC_COUNT; prec++) {
++		if (ctx->pkt_cnt_in_drv[ifid][prec] > 0) {
++			if (ac_traffic == WLFC_NO_TRAFFIC)
++				ac_traffic = prec + 1;
++			else if (ac_traffic != (prec + 1))
++				ac_traffic = WLFC_MULTI_TRAFFIC;
++		}
++	}
++
++	if (ac_traffic >= 1 && ac_traffic <= AC_COUNT) {
++		/* single AC (BE/BK/VI/VO) in queue */
++		if (ctx->allow_fc) {
++			return TRUE;
++		} else {
++			uint32 delta;
++			uint32 curr_t = OSL_SYSUPTIME();
++
++			if (ctx->fc_defer_timestamp == 0) {
++				/* first single ac scenario */
++				ctx->fc_defer_timestamp = curr_t;
++				return FALSE;
++			}
++
++			/* single AC duration, this handles wrap around, e.g. 1 - ~0 = 2. */
++			delta = curr_t - ctx->fc_defer_timestamp;
++			if (delta >= WLFC_FC_DEFER_PERIOD_MS) {
++				ctx->allow_fc = TRUE;
++			}
++		}
++	} else {
++		/* multiple ACs or BCMC in queue */
++		ctx->allow_fc = FALSE;
++		ctx->fc_defer_timestamp = 0;
++	}
++
++	return ctx->allow_fc;
++} /* _dhd_wlfc_allow_fc */
++
++/**
++ * Starts or stops the flow of transmit packets from the host OS towards the DHD, depending on
++ * low/high watermarks.
++ */
++static void
++_dhd_wlfc_flow_control_check(athost_wl_status_info_t* ctx, struct pktq* pq, uint8 if_id)
++{
++	dhd_pub_t *dhdp;
++
++	ASSERT(ctx);
++
++	dhdp = (dhd_pub_t *)ctx->dhdp;
++	ASSERT(dhdp);
++
++	if (dhdp->skip_fc && dhdp->skip_fc((void *)dhdp, if_id))
++		return;
++
++	if ((ctx->hostif_flow_state[if_id] == OFF) && !_dhd_wlfc_allow_fc(ctx, if_id))
++		return;
++
++	if ((pq->len <= WLFC_FLOWCONTROL_LOWATER) && (ctx->hostif_flow_state[if_id] == ON)) {
++		/* start traffic */
++		ctx->hostif_flow_state[if_id] = OFF;
++		/*
++		WLFC_DBGMESG(("qlen:%02d, if:%02d, ->OFF, start traffic %s()\n",
++		pq->len, if_id, __FUNCTION__));
++		*/
++		WLFC_DBGMESG(("F"));
++
++		dhd_txflowcontrol(dhdp, if_id, OFF);
++
++		ctx->toggle_host_if = 0;
++	}
++
++	if ((pq->len >= WLFC_FLOWCONTROL_HIWATER) && (ctx->hostif_flow_state[if_id] == OFF)) {
++		/* stop traffic */
++		ctx->hostif_flow_state[if_id] = ON;
++		/*
++		WLFC_DBGMESG(("qlen:%02d, if:%02d, ->ON, stop traffic   %s()\n",
++		pq->len, if_id, __FUNCTION__));
++		*/
++		WLFC_DBGMESG(("N"));
++
++		dhd_txflowcontrol(dhdp, if_id, ON);
++
++		ctx->host_ifidx = if_id;
++		ctx->toggle_host_if = 1;
++	}
++
++	return;
++} /* _dhd_wlfc_flow_control_check */
++
++static int
++_dhd_wlfc_send_signalonly_packet(athost_wl_status_info_t* ctx, wlfc_mac_descriptor_t* entry,
++	uint8 ta_bmp)
++{
++	int rc = BCME_OK;
++	void* p = NULL;
++	int dummylen = ((dhd_pub_t *)ctx->dhdp)->hdrlen+ 16;
++	dhd_pub_t *dhdp = (dhd_pub_t *)ctx->dhdp;
++
++	if (dhdp->proptxstatus_txoff) {
++		rc = BCME_NORESOURCE;
++		return rc;
++	}
++
++	/* allocate a dummy packet */
++	p = PKTGET(ctx->osh, dummylen, TRUE);
++	if (p) {
++		PKTPULL(ctx->osh, p, dummylen);
++		DHD_PKTTAG_SET_H2DTAG(PKTTAG(p), 0);
++		_dhd_wlfc_pushheader(ctx, &p, TRUE, ta_bmp, entry->mac_handle, 0, 0, FALSE);
++		DHD_PKTTAG_SETSIGNALONLY(PKTTAG(p), 1);
++		DHD_PKTTAG_WLFCPKT_SET(PKTTAG(p), 1);
++#ifdef PROP_TXSTATUS_DEBUG
++		ctx->stats.signal_only_pkts_sent++;
++#endif
++
++#if defined(BCMPCIE)
++		rc = dhd_bus_txdata(dhdp->bus, p, ctx->host_ifidx);
++#else
++		rc = dhd_bus_txdata(dhdp->bus, p);
++#endif
++		if (rc != BCME_OK) {
++			_dhd_wlfc_pullheader(ctx, p);
++			PKTFREE(ctx->osh, p, TRUE);
++		}
++	} else {
++		DHD_ERROR(("%s: couldn't allocate new %d-byte packet\n",
++		           __FUNCTION__, dummylen));
++		rc = BCME_NOMEM;
++		dhdp->tx_pktgetfail++;
++	}
++
++	return rc;
++} /* _dhd_wlfc_send_signalonly_packet */
++
++/**
++ * Called on eg receiving 'mac close' indication from dongle. Updates the per-MAC administration
++ * maintained in caller supplied parameter 'entry'.
++ *
++ *    @param[in/out] entry  administration about a remote MAC entity
++ *    @param[in]     prec   precedence queue for this remote MAC entitity
++ *
++ * Return value: TRUE if traffic availability changed
++ */
++static bool
++_dhd_wlfc_traffic_pending_check(athost_wl_status_info_t* ctx, wlfc_mac_descriptor_t* entry,
++	int prec)
++{
++	bool rc = FALSE;
++
++	if (entry->state == WLFC_STATE_CLOSE) {
++		if ((pktq_plen(&entry->psq, (prec << 1)) == 0) &&
++			(pktq_plen(&entry->psq, ((prec << 1) + 1)) == 0)) {
++			/* no packets in both 'normal' and 'suspended' queues */
++			if (entry->traffic_pending_bmp & NBITVAL(prec)) {
++				rc = TRUE;
++				entry->traffic_pending_bmp =
++					entry->traffic_pending_bmp & ~ NBITVAL(prec);
++			}
++		} else {
++			/* packets are queued in host for transmission to dongle */
++			if (!(entry->traffic_pending_bmp & NBITVAL(prec))) {
++				rc = TRUE;
++				entry->traffic_pending_bmp =
++					entry->traffic_pending_bmp | NBITVAL(prec);
++			}
++		}
++	}
++
++	if (rc) {
++		/* request a TIM update to firmware at the next piggyback opportunity */
++		if (entry->traffic_lastreported_bmp != entry->traffic_pending_bmp) {
++			entry->send_tim_signal = 1;
++			_dhd_wlfc_send_signalonly_packet(ctx, entry, entry->traffic_pending_bmp);
++			entry->traffic_lastreported_bmp = entry->traffic_pending_bmp;
++			entry->send_tim_signal = 0;
++		} else {
++			rc = FALSE;
++		}
++	}
++
++	return rc;
++} /* _dhd_wlfc_traffic_pending_check */
++
++/**
++ * Called on receiving a 'd11 suppressed' or 'wl suppressed' tx status from the firmware. Enqueues
++ * the packet to transmit to firmware again at a later opportunity.
++ */
++static int
++_dhd_wlfc_enque_suppressed(athost_wl_status_info_t* ctx, int prec, void* p)
++{
++	wlfc_mac_descriptor_t* entry;
++
++	entry = _dhd_wlfc_find_table_entry(ctx, p);
++	if (entry == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_NOTFOUND;
++	}
++	/*
++	- suppressed packets go to sub_queue[2*prec + 1] AND
++	- delayed packets go to sub_queue[2*prec + 0] to ensure
++	order of delivery.
++	*/
++	if (_dhd_wlfc_prec_enq_with_drop(ctx->dhdp, &entry->psq, p, ((prec << 1) + 1), FALSE,
++		WLFC_SEQCOUNT(entry, prec))
++		== FALSE) {
++		ctx->stats.delayq_full_error++;
++		/* WLFC_DBGMESG(("Error: %s():%d\n", __FUNCTION__, __LINE__)); */
++		WLFC_DBGMESG(("s"));
++		return BCME_ERROR;
++	}
++
++	/* A packet has been pushed, update traffic availability bitmap, if applicable */
++	_dhd_wlfc_traffic_pending_check(ctx, entry, prec);
++	_dhd_wlfc_flow_control_check(ctx, &entry->psq, DHD_PKTTAG_IF(PKTTAG(p)));
++	return BCME_OK;
++}
++
++/**
++ * Called when a transmit packet is about to be 'committed' from the OS layer to a lower layer
++ * towards the dongle (eg the DBUS layer). Updates wlfc administration. May modify packet.
++ *
++ *     @param[in/out] ctx    driver specific flow control administration
++ *     @param[in/out] entry  The remote MAC entity for which the packet is destined.
++ *     @param[in/out] packet Packet to send. This function optionally adds TLVs to the packet.
++ *     @param[in] header_needed True if packet is 'new' to flow control
++ *     @param[out] slot Handle to container in which the packet was 'parked'
++ */
++static int
++_dhd_wlfc_pretx_pktprocess(athost_wl_status_info_t* ctx,
++	wlfc_mac_descriptor_t* entry, void** packet, int header_needed, uint32* slot)
++{
++	int rc = BCME_OK;
++	int hslot = WLFC_HANGER_MAXITEMS;
++	bool send_tim_update = FALSE;
++	uint32 htod = 0;
++	uint16 htodseq = 0;
++	uint8 free_ctr;
++	int gen = 0xff;
++	dhd_pub_t *dhdp = (dhd_pub_t *)ctx->dhdp;
++	void * p = *packet;
++
++	*slot = hslot;
++
++	if (entry == NULL) {
++		entry = _dhd_wlfc_find_table_entry(ctx, p);
++	}
++
++	if (entry == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_ERROR;
++	}
++
++	if (entry->send_tim_signal) {
++		/* sends a traffic indication bitmap to the dongle */
++		send_tim_update = TRUE;
++		entry->send_tim_signal = 0;
++		entry->traffic_lastreported_bmp = entry->traffic_pending_bmp;
++	}
++
++	if (header_needed) {
++		if (WLFC_GET_AFQ(dhdp->wlfc_mode)) {
++			hslot = (uint)(entry - &ctx->destination_entries.nodes[0]);
++		} else {
++			hslot = _dhd_wlfc_hanger_get_free_slot(ctx->hanger);
++		}
++		gen = entry->generation;
++		free_ctr = WLFC_SEQCOUNT(entry, DHD_PKTTAG_FIFO(PKTTAG(p)));
++	} else {
++		if (WLFC_GET_REUSESEQ(dhdp->wlfc_mode)) {
++			htodseq = DHD_PKTTAG_H2DSEQ(PKTTAG(p));
++		}
++
++		hslot = WL_TXSTATUS_GET_HSLOT(DHD_PKTTAG_H2DTAG(PKTTAG(p)));
++
++		if (WLFC_GET_REORDERSUPP(dhdp->wlfc_mode)) {
++			gen = entry->generation;
++		} else if (WLFC_GET_AFQ(dhdp->wlfc_mode)) {
++			gen = WL_TXSTATUS_GET_GENERATION(DHD_PKTTAG_H2DTAG(PKTTAG(p)));
++		} else {
++			_dhd_wlfc_hanger_get_genbit(ctx->hanger, p, hslot, &gen);
++		}
++
++		free_ctr = WL_TXSTATUS_GET_FREERUNCTR(DHD_PKTTAG_H2DTAG(PKTTAG(p)));
++		/* remove old header */
++		_dhd_wlfc_pullheader(ctx, p);
++	}
++
++	if (hslot >= WLFC_HANGER_MAXITEMS) {
++		DHD_ERROR(("Error: %s():no hanger slot available\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	WL_TXSTATUS_SET_FREERUNCTR(htod, free_ctr);
++	WL_TXSTATUS_SET_HSLOT(htod, hslot);
++	WL_TXSTATUS_SET_FIFO(htod, DHD_PKTTAG_FIFO(PKTTAG(p)));
++	WL_TXSTATUS_SET_FLAGS(htod, WLFC_PKTFLAG_PKTFROMHOST);
++	WL_TXSTATUS_SET_GENERATION(htod, gen);
++	DHD_PKTTAG_SETPKTDIR(PKTTAG(p), 1);
++
++	if (!DHD_PKTTAG_CREDITCHECK(PKTTAG(p))) {
++		/*
++		Indicate that this packet is being sent in response to an
++		explicit request from the firmware side.
++		*/
++		WLFC_PKTFLAG_SET_PKTREQUESTED(htod);
++	} else {
++		WLFC_PKTFLAG_CLR_PKTREQUESTED(htod);
++	}
++
++	rc = _dhd_wlfc_pushheader(ctx, &p, send_tim_update,
++		entry->traffic_lastreported_bmp, entry->mac_handle, htod, htodseq, FALSE);
++	if (rc == BCME_OK) {
++		DHD_PKTTAG_SET_H2DTAG(PKTTAG(p), htod);
++
++		if (!WLFC_GET_AFQ(dhdp->wlfc_mode)) {
++			wlfc_hanger_t *h = (wlfc_hanger_t*)(ctx->hanger);
++			if (header_needed) {
++				/*
++				a new header was created for this packet.
++				push to hanger slot and scrub q. Since bus
++				send succeeded, increment seq number as well.
++				*/
++				rc = _dhd_wlfc_hanger_pushpkt(ctx->hanger, p, hslot);
++				if (rc == BCME_OK) {
++#ifdef PROP_TXSTATUS_DEBUG
++					h->items[hslot].push_time =
++						OSL_SYSUPTIME();
++#endif
++				} else {
++					DHD_ERROR(("%s() hanger_pushpkt() failed, rc: %d\n",
++						__FUNCTION__, rc));
++				}
++			} else {
++				/* clear hanger state */
++				if (((wlfc_hanger_t*)(ctx->hanger))->items[hslot].pkt != p)
++					DHD_ERROR(("%s() pkt not match: cur %p, hanger pkt %p\n",
++						__FUNCTION__, p, h->items[hslot].pkt));
++				ASSERT(h->items[hslot].pkt == p);
++				bcm_object_feature_set(h->items[hslot].pkt,
++					BCM_OBJECT_FEATURE_PKT_STATE, 0);
++				h->items[hslot].pkt_state = 0;
++				h->items[hslot].pkt_txstatus = 0;
++				h->items[hslot].state = WLFC_HANGER_ITEM_STATE_INUSE;
++			}
++		}
++
++		if ((rc == BCME_OK) && header_needed) {
++			/* increment free running sequence count */
++			WLFC_INCR_SEQCOUNT(entry, DHD_PKTTAG_FIFO(PKTTAG(p)));
++		}
++	}
++	*slot = hslot;
++	*packet = p;
++	return rc;
++} /* _dhd_wlfc_pretx_pktprocess */
++
++/**
++ * A remote wireless mac may be temporarily 'closed' due to power management. Returns '1' if remote
++ * mac is in the 'open' state, otherwise '0'.
++ */
++static int
++_dhd_wlfc_is_destination_open(athost_wl_status_info_t* ctx,
++	wlfc_mac_descriptor_t* entry, int prec)
++{
++	wlfc_mac_descriptor_t* interfaces = ctx->destination_entries.interfaces;
++
++	if (entry->interface_id >= WLFC_MAX_IFNUM) {
++		ASSERT(&ctx->destination_entries.other == entry);
++		return 1;
++	}
++
++	if (interfaces[entry->interface_id].iftype ==
++		WLC_E_IF_ROLE_P2P_GO) {
++		/* - destination interface is of type p2p GO.
++		For a p2pGO interface, if the destination is OPEN but the interface is
++		CLOSEd, do not send traffic. But if the dstn is CLOSEd while there is
++		destination-specific-credit left send packets. This is because the
++		firmware storing the destination-specific-requested packet in queue.
++		*/
++		if ((entry->state == WLFC_STATE_CLOSE) && (entry->requested_credit == 0) &&
++			(entry->requested_packet == 0)) {
++			return 0;
++		}
++	}
++
++	/* AP, p2p_go -> unicast desc entry, STA/p2p_cl -> interface desc. entry */
++	if ((((entry->state == WLFC_STATE_CLOSE) ||
++		(interfaces[entry->interface_id].state == WLFC_STATE_CLOSE)) &&
++		(entry->requested_credit == 0) &&
++		(entry->requested_packet == 0)) ||
++		(!(entry->ac_bitmap & (1 << prec)))) {
++		return 0;
++	}
++
++	return 1;
++} /* _dhd_wlfc_is_destination_open */
++
++/**
++ * Dequeues a suppressed or delayed packet from a queue
++ *    @param[in/out] ctx          Driver specific flow control administration
++ *    @param[in]  prec            Precedence of queue to dequeue from
++ *    @param[out] ac_credit_spent Boolean, returns 0 or 1
++ *    @param[out] needs_hdr       Boolean, returns 0 or 1
++ *    @param[out] entry_out       The remote MAC for which the packet is destined
++ *    @param[in]  only_no_credit  If TRUE, searches all entries instead of just the active ones
++ *
++ * Return value: the dequeued packet
++ */
++static void*
++_dhd_wlfc_deque_delayedq(athost_wl_status_info_t* ctx, int prec,
++	uint8* ac_credit_spent, uint8* needs_hdr, wlfc_mac_descriptor_t** entry_out,
++	bool only_no_credit)
++{
++	wlfc_mac_descriptor_t* entry;
++	int total_entries;
++	void* p = NULL;
++	int i;
++	uint8 credit_spent = ((prec == AC_COUNT) && !ctx->bcmc_credit_supported) ? 0 : 1;
++
++	*entry_out = NULL;
++	/* most cases a packet will count against FIFO credit */
++	*ac_credit_spent = credit_spent;
++
++	/* search all entries, include nodes as well as interfaces */
++	if (only_no_credit) {
++		total_entries = ctx->requested_entry_count;
++	} else {
++		total_entries = ctx->active_entry_count;
++	}
++
++	for (i = 0; i < total_entries; i++) {
++		if (only_no_credit) {
++			entry = ctx->requested_entry[i];
++		} else {
++			entry = ctx->active_entry_head;
++			/* move head to ensure fair round-robin */
++			ctx->active_entry_head = ctx->active_entry_head->next;
++		}
++		ASSERT(entry);
++
++		if (entry->occupied && _dhd_wlfc_is_destination_open(ctx, entry, prec) &&
++			(entry->transit_count < WL_TXSTATUS_FREERUNCTR_MASK) &&
++			(!entry->suppressed)) {
++			*ac_credit_spent = credit_spent;
++			if (entry->state == WLFC_STATE_CLOSE) {
++				*ac_credit_spent = 0;
++			}
++
++			/* higher precedence will be picked up first,
++			 * i.e. suppressed packets before delayed ones
++			 */
++			p = pktq_pdeq(&entry->psq, PSQ_SUP_IDX(prec));
++			*needs_hdr = 0;
++			if (p == NULL) {
++				/* De-Q from delay Q */
++				p = pktq_pdeq(&entry->psq, PSQ_DLY_IDX(prec));
++				*needs_hdr = 1;
++			}
++
++			if (p != NULL) {
++				bcm_pkt_validate_chk(p);
++				/* did the packet come from suppress sub-queue? */
++				if (entry->requested_credit > 0) {
++					entry->requested_credit--;
++#ifdef PROP_TXSTATUS_DEBUG
++					entry->dstncredit_sent_packets++;
++#endif
++				} else if (entry->requested_packet > 0) {
++					entry->requested_packet--;
++					DHD_PKTTAG_SETONETIMEPKTRQST(PKTTAG(p));
++				}
++
++				*entry_out = entry;
++				ctx->pkt_cnt_in_q[DHD_PKTTAG_IF(PKTTAG(p))][prec]--;
++				ctx->pkt_cnt_per_ac[prec]--;
++				ctx->pkt_cnt_in_psq--;
++				_dhd_wlfc_flow_control_check(ctx, &entry->psq,
++					DHD_PKTTAG_IF(PKTTAG(p)));
++				/*
++				 * A packet has been picked up, update traffic availability bitmap,
++				 * if applicable.
++				 */
++				_dhd_wlfc_traffic_pending_check(ctx, entry, prec);
++				return p;
++			}
++		}
++	}
++	return NULL;
++} /* _dhd_wlfc_deque_delayedq */
++
++/** Enqueues caller supplied packet on either a 'suppressed' or 'delayed' queue */
++static int
++_dhd_wlfc_enque_delayq(athost_wl_status_info_t* ctx, void* pktbuf, int prec)
++{
++	wlfc_mac_descriptor_t* entry;
++
++	if (pktbuf != NULL) {
++		entry = _dhd_wlfc_find_table_entry(ctx, pktbuf);
++		if (entry == NULL) {
++			DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++			return BCME_ERROR;
++		}
++
++		/*
++		- suppressed packets go to sub_queue[2*prec + 1] AND
++		- delayed packets go to sub_queue[2*prec + 0] to ensure
++		order of delivery.
++		*/
++		if (_dhd_wlfc_prec_enq_with_drop(ctx->dhdp, &entry->psq, pktbuf, (prec << 1),
++			FALSE, WLFC_SEQCOUNT(entry, prec))
++			== FALSE) {
++			WLFC_DBGMESG(("D"));
++			ctx->stats.delayq_full_error++;
++			return BCME_ERROR;
++		}
++
++
++		/* A packet has been pushed, update traffic availability bitmap, if applicable */
++		_dhd_wlfc_traffic_pending_check(ctx, entry, prec);
++	}
++
++	return BCME_OK;
++} /* _dhd_wlfc_enque_delayq */
++
++/** Returns TRUE if caller supplied packet is destined for caller supplied interface */
++static bool _dhd_wlfc_ifpkt_fn(void* p, void *p_ifid)
++{
++	if (!p || !p_ifid)
++		return FALSE;
++
++	return (DHD_PKTTAG_WLFCPKT(PKTTAG(p))&& (*((uint8 *)p_ifid) == DHD_PKTTAG_IF(PKTTAG(p))));
++}
++
++/** Returns TRUE if caller supplied packet is destined for caller supplied remote MAC */
++static bool _dhd_wlfc_entrypkt_fn(void* p, void *entry)
++{
++	if (!p || !entry)
++		return FALSE;
++
++	return (DHD_PKTTAG_WLFCPKT(PKTTAG(p))&& (entry == DHD_PKTTAG_ENTRY(PKTTAG(p))));
++}
++
++static void
++_dhd_wlfc_return_implied_credit(athost_wl_status_info_t* wlfc, void* pkt)
++{
++	dhd_pub_t *dhdp;
++	bool credit_return = FALSE;
++
++	if (!wlfc || !pkt) {
++		return;
++	}
++
++	dhdp = (dhd_pub_t *)(wlfc->dhdp);
++	if (dhdp && (dhdp->proptxstatus_mode == WLFC_FCMODE_IMPLIED_CREDIT) &&
++		DHD_PKTTAG_CREDITCHECK(PKTTAG(pkt))) {
++		int lender, credit_returned = 0;
++		uint8 fifo_id = DHD_PKTTAG_FIFO(PKTTAG(pkt));
++
++		credit_return = TRUE;
++
++		/* Note that borrower is fifo_id */
++		/* Return credits to highest priority lender first */
++		for (lender = AC_COUNT; lender >= 0; lender--) {
++			if (wlfc->credits_borrowed[fifo_id][lender] > 0) {
++				wlfc->FIFO_credit[lender]++;
++				wlfc->credits_borrowed[fifo_id][lender]--;
++				credit_returned = 1;
++				break;
++			}
++		}
++
++		if (!credit_returned) {
++			wlfc->FIFO_credit[fifo_id]++;
++		}
++	}
++
++	BCM_REFERENCE(credit_return);
++#if defined(DHD_WLFC_THREAD)
++	if (credit_return) {
++		_dhd_wlfc_thread_wakeup(dhdp);
++	}
++#endif /* defined(DHD_WLFC_THREAD) */
++}
++
++/** Removes and frees a packet from the hanger. Called during eg tx complete. */
++static void
++_dhd_wlfc_hanger_free_pkt(athost_wl_status_info_t* wlfc, uint32 slot_id, uint8 pkt_state,
++	int pkt_txstatus)
++{
++	wlfc_hanger_t* hanger;
++	wlfc_hanger_item_t* item;
++
++	if (!wlfc)
++		return;
++
++	hanger = (wlfc_hanger_t*)wlfc->hanger;
++	if (!hanger)
++		return;
++
++	if (slot_id == WLFC_HANGER_MAXITEMS)
++		return;
++
++	item = &hanger->items[slot_id];
++
++	if (item->pkt) {
++		item->pkt_state |= pkt_state;
++		if (pkt_txstatus != -1)
++			item->pkt_txstatus = (uint8)pkt_txstatus;
++		bcm_object_feature_set(item->pkt, BCM_OBJECT_FEATURE_PKT_STATE, item->pkt_state);
++		if (item->pkt_state == WLFC_HANGER_PKT_STATE_COMPLETE) {
++			void *p = NULL;
++			void *pkt = item->pkt;
++			uint8 old_state = item->state;
++			int ret = _dhd_wlfc_hanger_poppkt(wlfc->hanger, slot_id, &p, TRUE);
++			BCM_REFERENCE(ret);
++			BCM_REFERENCE(pkt);
++			ASSERT((ret == BCME_OK) && p && (pkt == p));
++			if (old_state == WLFC_HANGER_ITEM_STATE_INUSE_SUPPRESSED) {
++				printf("ERROR: free a suppressed pkt %p state %d pkt_state %d\n",
++					pkt, old_state, item->pkt_state);
++			}
++			ASSERT(old_state != WLFC_HANGER_ITEM_STATE_INUSE_SUPPRESSED);
++
++			/* free packet */
++			wlfc->pkt_cnt_in_drv[DHD_PKTTAG_IF(PKTTAG(p))]
++				[DHD_PKTTAG_FIFO(PKTTAG(p))]--;
++			wlfc->stats.pktout++;
++			dhd_txcomplete((dhd_pub_t *)wlfc->dhdp, p, item->pkt_txstatus);
++			PKTFREE(wlfc->osh, p, TRUE);
++		}
++	} else {
++		/* free slot */
++		if (item->state == WLFC_HANGER_ITEM_STATE_FREE)
++			DHD_ERROR(("Error: %s():%d Multiple TXSTATUS or BUSRETURNED: %d (%d)\n",
++			    __FUNCTION__, __LINE__, item->pkt_state, pkt_state));
++		item->state = WLFC_HANGER_ITEM_STATE_FREE;
++	}
++} /* _dhd_wlfc_hanger_free_pkt */
++
++/** Called during eg detach() */
++static void
++_dhd_wlfc_pktq_flush(athost_wl_status_info_t* ctx, struct pktq *pq,
++	bool dir, f_processpkt_t fn, void *arg, q_type_t q_type)
++{
++	int prec;
++	dhd_pub_t *dhdp = (dhd_pub_t *)ctx->dhdp;
++
++	ASSERT(dhdp);
++
++	/* Optimize flush, if pktq len = 0, just return.
++	 * pktq len of 0 means pktq's prec q's are all empty.
++	 */
++	if (pq->len == 0) {
++		return;
++	}
++
++	for (prec = 0; prec < pq->num_prec; prec++) {
++		struct pktq_prec *q;
++		void *p, *prev = NULL;
++
++		q = &pq->q[prec];
++		p = q->head;
++		while (p) {
++			bcm_pkt_validate_chk(p);
++			if (fn == NULL || (*fn)(p, arg)) {
++				bool head = (p == q->head);
++				if (head)
++					q->head = PKTLINK(p);
++				else
++					PKTSETLINK(prev, PKTLINK(p));
++				if (q_type == Q_TYPE_PSQ) {
++					if (!WLFC_GET_AFQ(dhdp->wlfc_mode) && (prec & 1)) {
++						_dhd_wlfc_hanger_remove_reference(ctx->hanger, p);
++					}
++					ctx->pkt_cnt_in_q[DHD_PKTTAG_IF(PKTTAG(p))][prec>>1]--;
++					ctx->pkt_cnt_per_ac[prec>>1]--;
++					ctx->pkt_cnt_in_psq--;
++					ctx->stats.cleanup_psq_cnt++;
++					if (!(prec & 1)) {
++						/* pkt in delayed q, so fake push BDC header for
++						 * dhd_tcpack_check_xmit() and dhd_txcomplete().
++						 */
++						_dhd_wlfc_pushheader(ctx, &p, FALSE, 0, 0,
++							0, 0, TRUE);
++#ifdef DHDTCPACK_SUPPRESS
++						if (dhd_tcpack_check_xmit(dhdp, p) == BCME_ERROR) {
++							DHD_ERROR(("%s %d: tcpack_suppress ERROR!!!"
++								" Stop using it\n",
++								__FUNCTION__, __LINE__));
++							dhd_tcpack_suppress_set(dhdp,
++								TCPACK_SUP_OFF);
++						}
++#endif /* DHDTCPACK_SUPPRESS */
++					}
++				} else if (q_type == Q_TYPE_AFQ) {
++					wlfc_mac_descriptor_t* entry =
++						_dhd_wlfc_find_table_entry(ctx, p);
++					if (entry->transit_count)
++						entry->transit_count--;
++					if (entry->suppr_transit_count) {
++						entry->suppr_transit_count--;
++						if (entry->suppressed &&
++							(!entry->onbus_pkts_count) &&
++							(!entry->suppr_transit_count))
++							entry->suppressed = FALSE;
++					}
++					_dhd_wlfc_return_implied_credit(ctx, p);
++					ctx->stats.cleanup_fw_cnt++;
++				}
++				PKTSETLINK(p, NULL);
++				if (dir) {
++					ctx->pkt_cnt_in_drv[DHD_PKTTAG_IF(PKTTAG(p))][prec>>1]--;
++					ctx->stats.pktout++;
++					dhd_txcomplete(dhdp, p, FALSE);
++				}
++				PKTFREE(ctx->osh, p, dir);
++
++				q->len--;
++				pq->len--;
++				p = (head ? q->head : PKTLINK(prev));
++			} else {
++				prev = p;
++				p = PKTLINK(p);
++			}
++		}
++
++		if (q->head == NULL) {
++			ASSERT(q->len == 0);
++			q->tail = NULL;
++		}
++
++	}
++
++	if (fn == NULL)
++		ASSERT(pq->len == 0);
++} /* _dhd_wlfc_pktq_flush */
++
++#ifndef BCMDBUS
++/** !BCMDBUS specific function. Dequeues a packet from the caller supplied queue. */
++static void*
++_dhd_wlfc_pktq_pdeq_with_fn(struct pktq *pq, int prec, f_processpkt_t fn, void *arg)
++{
++	struct pktq_prec *q;
++	void *p, *prev = NULL;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	q = &pq->q[prec];
++	p = q->head;
++
++	while (p) {
++		if (fn == NULL || (*fn)(p, arg)) {
++			break;
++		} else {
++			prev = p;
++			p = PKTLINK(p);
++		}
++	}
++	if (p == NULL)
++		return NULL;
++
++	bcm_pkt_validate_chk(p);
++
++	if (prev == NULL) {
++		if ((q->head = PKTLINK(p)) == NULL) {
++			q->tail = NULL;
++		}
++	} else {
++		PKTSETLINK(prev, PKTLINK(p));
++		if (q->tail == p) {
++			q->tail = prev;
++		}
++	}
++
++	q->len--;
++
++	pq->len--;
++
++	PKTSETLINK(p, NULL);
++
++	return p;
++}
++
++/** !BCMDBUS specific function */
++static void
++_dhd_wlfc_cleanup_txq(dhd_pub_t *dhd, f_processpkt_t fn, void *arg)
++{
++	int prec;
++	void *pkt = NULL, *head = NULL, *tail = NULL;
++	struct pktq *txq = (struct pktq *)dhd_bus_txq(dhd->bus);
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	wlfc_hanger_t* h = (wlfc_hanger_t*)wlfc->hanger;
++	wlfc_mac_descriptor_t* entry;
++
++	dhd_os_sdlock_txq(dhd);
++	for (prec = 0; prec < txq->num_prec; prec++) {
++		while ((pkt = _dhd_wlfc_pktq_pdeq_with_fn(txq, prec, fn, arg))) {
++#ifdef DHDTCPACK_SUPPRESS
++			if (dhd_tcpack_check_xmit(dhd, pkt) == BCME_ERROR) {
++				DHD_ERROR(("%s %d: tcpack_suppress ERROR!!! Stop using it\n",
++					__FUNCTION__, __LINE__));
++				dhd_tcpack_suppress_set(dhd, TCPACK_SUP_OFF);
++			}
++#endif /* DHDTCPACK_SUPPRESS */
++			if (!head) {
++				head = pkt;
++			}
++			if (tail) {
++				PKTSETLINK(tail, pkt);
++			}
++			tail = pkt;
++		}
++	}
++	dhd_os_sdunlock_txq(dhd);
++
++
++	while ((pkt = head)) {
++		head = PKTLINK(pkt);
++		PKTSETLINK(pkt, NULL);
++		entry = _dhd_wlfc_find_table_entry(wlfc, pkt);
++
++		if (!WLFC_GET_AFQ(dhd->wlfc_mode) &&
++			!_dhd_wlfc_hanger_remove_reference(h, pkt)) {
++			DHD_ERROR(("%s: can't find pkt(%p) in hanger, free it anyway\n",
++				__FUNCTION__, pkt));
++		}
++		if (entry->transit_count)
++			entry->transit_count--;
++		if (entry->suppr_transit_count) {
++			entry->suppr_transit_count--;
++			if (entry->suppressed &&
++				(!entry->onbus_pkts_count) &&
++				(!entry->suppr_transit_count))
++				entry->suppressed = FALSE;
++		}
++		_dhd_wlfc_return_implied_credit(wlfc, pkt);
++		wlfc->pkt_cnt_in_drv[DHD_PKTTAG_IF(PKTTAG(pkt))][DHD_PKTTAG_FIFO(PKTTAG(pkt))]--;
++		wlfc->stats.pktout++;
++		wlfc->stats.cleanup_txq_cnt++;
++		dhd_txcomplete(dhd, pkt, FALSE);
++		PKTFREE(wlfc->osh, pkt, TRUE);
++	}
++} /* _dhd_wlfc_cleanup_txq */
++#endif /* !BCMDBUS */
++
++/** called during eg detach */
++void
++_dhd_wlfc_cleanup(dhd_pub_t *dhd, f_processpkt_t fn, void *arg)
++{
++	int i;
++	int total_entries;
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	wlfc_mac_descriptor_t* table;
++	wlfc_hanger_t* h = (wlfc_hanger_t*)wlfc->hanger;
++
++	wlfc->stats.cleanup_txq_cnt = 0;
++	wlfc->stats.cleanup_psq_cnt = 0;
++	wlfc->stats.cleanup_fw_cnt = 0;
++
++	/*
++	*  flush sequence should be txq -> psq -> hanger/afq, hanger has to be last one
++	*/
++#ifndef BCMDBUS
++	/* flush bus->txq */
++	_dhd_wlfc_cleanup_txq(dhd, fn, arg);
++#endif /* !BCMDBUS */
++
++	/* flush psq, search all entries, include nodes as well as interfaces */
++	total_entries = sizeof(wlfc->destination_entries)/sizeof(wlfc_mac_descriptor_t);
++	table = (wlfc_mac_descriptor_t*)&wlfc->destination_entries;
++
++	for (i = 0; i < total_entries; i++) {
++		if (table[i].occupied) {
++			/* release packets held in PSQ (both delayed and suppressed) */
++			if (table[i].psq.len) {
++				WLFC_DBGMESG(("%s(): PSQ[%d].len = %d\n",
++					__FUNCTION__, i, table[i].psq.len));
++				_dhd_wlfc_pktq_flush(wlfc, &table[i].psq, TRUE,
++					fn, arg, Q_TYPE_PSQ);
++			}
++
++			/* free packets held in AFQ */
++			if (WLFC_GET_AFQ(dhd->wlfc_mode) && (table[i].afq.len)) {
++				_dhd_wlfc_pktq_flush(wlfc, &table[i].afq, TRUE,
++					fn, arg, Q_TYPE_AFQ);
++			}
++
++			if ((fn == NULL) && (&table[i] != &wlfc->destination_entries.other)) {
++				table[i].occupied = 0;
++				if (table[i].transit_count || table[i].suppr_transit_count) {
++					DHD_ERROR(("%s: table[%d] transit(%d), suppr_tansit(%d)\n",
++						__FUNCTION__, i,
++						table[i].transit_count,
++						table[i].suppr_transit_count));
++				}
++			}
++		}
++	}
++
++	/*
++		. flush remained pkt in hanger queue, not in bus->txq nor psq.
++		. the remained pkt was successfully downloaded to dongle already.
++		. hanger slot state cannot be set to free until receive txstatus update.
++	*/
++	if (!WLFC_GET_AFQ(dhd->wlfc_mode)) {
++		for (i = 0; i < h->max_items; i++) {
++			if ((h->items[i].state == WLFC_HANGER_ITEM_STATE_INUSE) ||
++				(h->items[i].state == WLFC_HANGER_ITEM_STATE_INUSE_SUPPRESSED)) {
++				if (fn == NULL || (*fn)(h->items[i].pkt, arg)) {
++					h->items[i].state = WLFC_HANGER_ITEM_STATE_FLUSHED;
++				}
++			}
++		}
++	}
++
++	return;
++} /* _dhd_wlfc_cleanup */
++
++/** Called after eg the dongle signalled a new remote MAC that it connected with to the DHD */
++static int
++_dhd_wlfc_mac_entry_update(athost_wl_status_info_t* ctx, wlfc_mac_descriptor_t* entry,
++	uint8 action, uint8 ifid, uint8 iftype, uint8* ea,
++	f_processpkt_t fn, void *arg)
++{
++	int rc = BCME_OK;
++
++
++	if ((action == eWLFC_MAC_ENTRY_ACTION_ADD) || (action == eWLFC_MAC_ENTRY_ACTION_UPDATE)) {
++		entry->occupied = 1;
++		entry->state = WLFC_STATE_OPEN;
++		entry->requested_credit = 0;
++		entry->interface_id = ifid;
++		entry->iftype = iftype;
++		entry->ac_bitmap = 0xff; /* update this when handling APSD */
++
++		/* for an interface entry we may not care about the MAC address */
++		if (ea != NULL)
++			memcpy(&entry->ea[0], ea, ETHER_ADDR_LEN);
++
++		if (action == eWLFC_MAC_ENTRY_ACTION_ADD) {
++			entry->suppressed = FALSE;
++			entry->transit_count = 0;
++			entry->suppr_transit_count = 0;
++			entry->onbus_pkts_count = 0;
++		}
++
++		if (action == eWLFC_MAC_ENTRY_ACTION_ADD) {
++			dhd_pub_t *dhdp = (dhd_pub_t *)(ctx->dhdp);
++
++			pktq_init(&entry->psq, WLFC_PSQ_PREC_COUNT, WLFC_PSQ_LEN);
++			_dhd_wlfc_flow_control_check(ctx, &entry->psq, ifid);
++
++			if (WLFC_GET_AFQ(dhdp->wlfc_mode)) {
++				pktq_init(&entry->afq, WLFC_AFQ_PREC_COUNT, WLFC_PSQ_LEN);
++			}
++
++			if (entry->next == NULL) {
++				/* not linked to anywhere, add to tail */
++				if (ctx->active_entry_head) {
++					entry->prev = ctx->active_entry_head->prev;
++					ctx->active_entry_head->prev->next = entry;
++					ctx->active_entry_head->prev = entry;
++					entry->next = ctx->active_entry_head;
++				} else {
++					ASSERT(ctx->active_entry_count == 0);
++					entry->prev = entry->next = entry;
++					ctx->active_entry_head = entry;
++				}
++				ctx->active_entry_count++;
++			} else {
++				DHD_ERROR(("%s():%d, entry(%d)\n", __FUNCTION__, __LINE__,
++					(int)(entry - &ctx->destination_entries.nodes[0])));
++			}
++		}
++	} else if (action == eWLFC_MAC_ENTRY_ACTION_DEL) {
++		/* When the entry is deleted, the packets that are queued in the entry must be
++		   cleanup. The cleanup action should be before the occupied is set as 0.
++		*/
++		_dhd_wlfc_cleanup(ctx->dhdp, fn, arg);
++		_dhd_wlfc_flow_control_check(ctx, &entry->psq, ifid);
++
++		entry->occupied = 0;
++		entry->state = WLFC_STATE_CLOSE;
++		memset(&entry->ea[0], 0, ETHER_ADDR_LEN);
++
++		if (entry->next) {
++			/* not floating, remove from Q */
++			if (ctx->active_entry_count <= 1) {
++				/* last item */
++				ctx->active_entry_head = NULL;
++				ctx->active_entry_count = 0;
++			} else {
++				entry->prev->next = entry->next;
++				entry->next->prev = entry->prev;
++				if (entry == ctx->active_entry_head) {
++					ctx->active_entry_head = entry->next;
++				}
++				ctx->active_entry_count--;
++			}
++			entry->next = entry->prev = NULL;
++		} else {
++			DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		}
++	}
++	return rc;
++} /* _dhd_wlfc_mac_entry_update */
++
++
++#ifdef LIMIT_BORROW
++
++/** LIMIT_BORROW specific function */
++static int
++_dhd_wlfc_borrow_credit(athost_wl_status_info_t* ctx, int highest_lender_ac, int borrower_ac,
++	bool bBorrowAll)
++{
++	int lender_ac, borrow_limit = 0;
++	int rc = -1;
++
++	if (ctx == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return -1;
++	}
++
++	/* Borrow from lowest priority available AC (including BC/MC credits) */
++	for (lender_ac = 0; lender_ac <= highest_lender_ac; lender_ac++) {
++		if (!bBorrowAll) {
++			borrow_limit = ctx->Init_FIFO_credit[lender_ac]/WLFC_BORROW_LIMIT_RATIO;
++		} else {
++			borrow_limit = 0;
++		}
++
++		if (ctx->FIFO_credit[lender_ac] > borrow_limit) {
++			ctx->credits_borrowed[borrower_ac][lender_ac]++;
++			ctx->FIFO_credit[lender_ac]--;
++			rc = lender_ac;
++			break;
++		}
++	}
++
++	return rc;
++}
++
++/** LIMIT_BORROW specific function */
++static int _dhd_wlfc_return_credit(athost_wl_status_info_t* ctx, int lender_ac, int borrower_ac)
++{
++	if ((ctx == NULL) || (lender_ac < 0) || (lender_ac > AC_COUNT) ||
++		(borrower_ac < 0) || (borrower_ac > AC_COUNT)) {
++		DHD_ERROR(("Error: %s():%d, ctx(%p), lender_ac(%d), borrower_ac(%d)\n",
++			__FUNCTION__, __LINE__, ctx, lender_ac, borrower_ac));
++
++		return BCME_BADARG;
++	}
++
++	ctx->credits_borrowed[borrower_ac][lender_ac]--;
++	ctx->FIFO_credit[lender_ac]++;
++
++	return BCME_OK;
++}
++
++#endif /* LIMIT_BORROW */
++
++/**
++ * Called on an interface event (WLC_E_IF) indicated by firmware.
++ *     @param action : eg eWLFC_MAC_ENTRY_ACTION_UPDATE or eWLFC_MAC_ENTRY_ACTION_ADD
++ */
++static int
++_dhd_wlfc_interface_entry_update(void* state,
++	uint8 action, uint8 ifid, uint8 iftype, uint8* ea)
++{
++	athost_wl_status_info_t* ctx = (athost_wl_status_info_t*)state;
++	wlfc_mac_descriptor_t* entry;
++
++	if (ifid >= WLFC_MAX_IFNUM)
++		return BCME_BADARG;
++
++	entry = &ctx->destination_entries.interfaces[ifid];
++
++	return _dhd_wlfc_mac_entry_update(ctx, entry, action, ifid, iftype, ea,
++		_dhd_wlfc_ifpkt_fn, &ifid);
++}
++
++/**
++ * Called eg on receiving a WLC_E_BCMC_CREDIT_SUPPORT event from the dongle (broadcast/multicast
++ * specific)
++ */
++static int
++_dhd_wlfc_BCMCCredit_support_update(void* state)
++{
++	athost_wl_status_info_t* ctx = (athost_wl_status_info_t*)state;
++
++	ctx->bcmc_credit_supported = TRUE;
++	return BCME_OK;
++}
++
++/** Called eg on receiving a WLC_E_FIFO_CREDIT_MAP event from the dongle */
++static int
++_dhd_wlfc_FIFOcreditmap_update(void* state, uint8* credits)
++{
++	athost_wl_status_info_t* ctx = (athost_wl_status_info_t*)state;
++	int i;
++
++	for (i = 0; i <= 4; i++) {
++		if (ctx->Init_FIFO_credit[i] != ctx->FIFO_credit[i]) {
++			DHD_ERROR(("%s: credit[i] is not returned, (%d %d)\n",
++				__FUNCTION__, ctx->Init_FIFO_credit[i], ctx->FIFO_credit[i]));
++		}
++	}
++
++	/* update the AC FIFO credit map */
++	ctx->FIFO_credit[0] += (credits[0] - ctx->Init_FIFO_credit[0]);
++	ctx->FIFO_credit[1] += (credits[1] - ctx->Init_FIFO_credit[1]);
++	ctx->FIFO_credit[2] += (credits[2] - ctx->Init_FIFO_credit[2]);
++	ctx->FIFO_credit[3] += (credits[3] - ctx->Init_FIFO_credit[3]);
++	ctx->FIFO_credit[4] += (credits[4] - ctx->Init_FIFO_credit[4]);
++
++	ctx->Init_FIFO_credit[0] = credits[0];
++	ctx->Init_FIFO_credit[1] = credits[1];
++	ctx->Init_FIFO_credit[2] = credits[2];
++	ctx->Init_FIFO_credit[3] = credits[3];
++	ctx->Init_FIFO_credit[4] = credits[4];
++
++	/* credit for ATIM FIFO is not used yet. */
++	ctx->Init_FIFO_credit[5] = ctx->FIFO_credit[5] = 0;
++
++	return BCME_OK;
++}
++
++/**
++ * Called during committing of a transmit packet from the OS DHD layer to the next layer towards
++ * the dongle (eg the DBUS layer). All transmit packets flow via this function to the next layer.
++ *
++ *     @param[in/out] ctx      Driver specific flow control administration
++ *     @param[in] ac           Access Category (QoS) of called supplied packet
++ *     @param[in] commit_info  Contains eg the packet to send
++ *     @param[in] fcommit      Function pointer to transmit function of next software layer
++ *     @param[in] commit_ctx   Opaque context used when calling next layer
++ */
++static int
++_dhd_wlfc_handle_packet_commit(athost_wl_status_info_t* ctx, int ac,
++    dhd_wlfc_commit_info_t *commit_info, f_commitpkt_t fcommit, void* commit_ctx)
++{
++	uint32 hslot;
++	int	rc;
++	dhd_pub_t *dhdp = (dhd_pub_t *)(ctx->dhdp);
++
++	/*
++		if ac_fifo_credit_spent = 0
++
++		This packet will not count against the FIFO credit.
++		To ensure the txstatus corresponding to this packet
++		does not provide an implied credit (default behavior)
++		mark the packet accordingly.
++
++		if ac_fifo_credit_spent = 1
++
++		This is a normal packet and it counts against the FIFO
++		credit count.
++	*/
++	DHD_PKTTAG_SETCREDITCHECK(PKTTAG(commit_info->p), commit_info->ac_fifo_credit_spent);
++	rc = _dhd_wlfc_pretx_pktprocess(ctx, commit_info->mac_entry, &commit_info->p,
++	     commit_info->needs_hdr, &hslot);
++
++	if (rc == BCME_OK) {
++		rc = fcommit(commit_ctx, commit_info->p);
++		if (rc == BCME_OK) {
++			uint8 gen = WL_TXSTATUS_GET_GENERATION(
++				DHD_PKTTAG_H2DTAG(PKTTAG(commit_info->p)));
++			ctx->stats.pkt2bus++;
++			if (commit_info->ac_fifo_credit_spent || (ac == AC_COUNT)) {
++				ctx->stats.send_pkts[ac]++;
++				WLFC_HOST_FIFO_CREDIT_INC_SENTCTRS(ctx, ac);
++			}
++
++			if (gen != commit_info->mac_entry->generation) {
++				/* will be suppressed back by design */
++				if (!commit_info->mac_entry->suppressed) {
++					commit_info->mac_entry->suppressed = TRUE;
++				}
++				commit_info->mac_entry->suppr_transit_count++;
++			}
++			commit_info->mac_entry->transit_count++;
++			commit_info->mac_entry->onbus_pkts_count++;
++		} else if (commit_info->needs_hdr) {
++			if (!WLFC_GET_AFQ(dhdp->wlfc_mode)) {
++				void *pout = NULL;
++				/* pop hanger for delayed packet */
++				_dhd_wlfc_hanger_poppkt(ctx->hanger, WL_TXSTATUS_GET_HSLOT(
++					DHD_PKTTAG_H2DTAG(PKTTAG(commit_info->p))), &pout, TRUE);
++				ASSERT(commit_info->p == pout);
++			}
++		}
++	} else {
++		ctx->stats.generic_error++;
++	}
++
++	if (rc != BCME_OK) {
++		/*
++		   pretx pkt process or bus commit has failed, rollback.
++		   - remove wl-header for a delayed packet
++		   - save wl-header header for suppressed packets
++		   - reset credit check flag
++		*/
++		_dhd_wlfc_rollback_packet_toq(ctx, commit_info->p, commit_info->pkt_type, hslot);
++		DHD_PKTTAG_SETCREDITCHECK(PKTTAG(commit_info->p), 0);
++	}
++
++	return rc;
++} /* _dhd_wlfc_handle_packet_commit */
++
++/** Returns remote MAC descriptor for caller supplied MAC address */
++static uint8
++_dhd_wlfc_find_mac_desc_id_from_mac(dhd_pub_t *dhdp, uint8 *ea)
++{
++	wlfc_mac_descriptor_t* table =
++		((athost_wl_status_info_t*)dhdp->wlfc_state)->destination_entries.nodes;
++	uint8 table_index;
++
++	if (ea != NULL) {
++		for (table_index = 0; table_index < WLFC_MAC_DESC_TABLE_SIZE; table_index++) {
++			if ((memcmp(ea, &table[table_index].ea[0], ETHER_ADDR_LEN) == 0) &&
++				table[table_index].occupied)
++				return table_index;
++		}
++	}
++	return WLFC_MAC_DESC_ID_INVALID;
++}
++
++/**
++ * Called when the host receives a WLFC_CTL_TYPE_TXSTATUS event from the dongle, indicating the
++ * status of a frame that the dongle attempted to transmit over the wireless medium.
++ */
++static int
++dhd_wlfc_suppressed_acked_update(dhd_pub_t *dhd, uint16 hslot, uint8 prec, uint8 hcnt)
++{
++	athost_wl_status_info_t* ctx;
++	wlfc_mac_descriptor_t* entry = NULL;
++	struct pktq *pq;
++	struct pktq_prec *q;
++	void *p, *b;
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd(%p)\n", __FUNCTION__, dhd));
++		return BCME_BADARG;
++	}
++	ctx = (athost_wl_status_info_t*)dhd->wlfc_state;
++	if (!ctx) {
++		DHD_ERROR(("%s: ctx(%p)\n", __FUNCTION__, ctx));
++		return BCME_ERROR;
++	}
++
++	ASSERT(hslot < (WLFC_MAC_DESC_TABLE_SIZE + WLFC_MAX_IFNUM + 1));
++
++	if (hslot < WLFC_MAC_DESC_TABLE_SIZE)
++		entry  = &ctx->destination_entries.nodes[hslot];
++	else if (hslot < (WLFC_MAC_DESC_TABLE_SIZE + WLFC_MAX_IFNUM))
++		entry = &ctx->destination_entries.interfaces[hslot - WLFC_MAC_DESC_TABLE_SIZE];
++	else
++		entry = &ctx->destination_entries.other;
++
++	pq = &entry->psq;
++
++	ASSERT(((prec << 1) + 1) < pq->num_prec);
++
++	q = &pq->q[((prec << 1) + 1)];
++
++	b = NULL;
++	p = q->head;
++
++	while (p && (hcnt != WL_TXSTATUS_GET_FREERUNCTR(DHD_PKTTAG_H2DTAG(PKTTAG(p))))) {
++		b = p;
++		p = PKTLINK(p);
++	}
++
++	if (p == NULL) {
++		/* none is matched */
++		if (b) {
++			DHD_ERROR(("%s: can't find matching seq(%d)\n", __FUNCTION__, hcnt));
++		} else {
++			DHD_ERROR(("%s: queue is empty\n", __FUNCTION__));
++		}
++
++		return BCME_ERROR;
++	}
++
++	if (!b) {
++		/* head packet is matched */
++		if ((q->head = PKTLINK(p)) == NULL) {
++			q->tail = NULL;
++		}
++	} else {
++		/* middle packet is matched */
++		PKTSETLINK(b, PKTLINK(p));
++		if (PKTLINK(p) == NULL) {
++			q->tail = b;
++		}
++	}
++
++	q->len--;
++	pq->len--;
++	ctx->pkt_cnt_in_q[DHD_PKTTAG_IF(PKTTAG(p))][prec]--;
++	ctx->pkt_cnt_per_ac[prec]--;
++
++	PKTSETLINK(p, NULL);
++
++	if (WLFC_GET_AFQ(dhd->wlfc_mode)) {
++		_dhd_wlfc_enque_afq(ctx, p);
++	} else {
++		_dhd_wlfc_hanger_pushpkt(ctx->hanger, p, hslot);
++	}
++
++	entry->transit_count++;
++
++	return BCME_OK;
++}
++
++static int
++_dhd_wlfc_compressed_txstatus_update(dhd_pub_t *dhd, uint8* pkt_info, uint8 len, void** p_mac)
++{
++	uint8 status_flag_ori, status_flag;
++	uint32 status;
++	int ret = BCME_OK;
++	int remove_from_hanger_ori, remove_from_hanger = 1;
++	void* pktbuf = NULL;
++	uint8 fifo_id = 0, gen = 0, count = 0, hcnt;
++	uint16 hslot;
++	wlfc_mac_descriptor_t* entry = NULL;
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	uint16 seq = 0, seq_fromfw = 0, seq_num = 0;
++
++	memcpy(&status, pkt_info, sizeof(uint32));
++	status = ltoh32(status);
++	status_flag = WL_TXSTATUS_GET_FLAGS(status);
++	hcnt = WL_TXSTATUS_GET_FREERUNCTR(status);
++	hslot = WL_TXSTATUS_GET_HSLOT(status);
++	fifo_id = WL_TXSTATUS_GET_FIFO(status);
++	gen = WL_TXSTATUS_GET_GENERATION(status);
++
++	if (WLFC_GET_REUSESEQ(dhd->wlfc_mode)) {
++		memcpy(&seq, pkt_info + WLFC_CTL_VALUE_LEN_TXSTATUS, WLFC_CTL_VALUE_LEN_SEQ);
++		seq = ltoh16(seq);
++		seq_fromfw = GET_WL_HAS_ASSIGNED_SEQ(seq);
++		seq_num = WL_SEQ_GET_NUM(seq);
++	}
++
++	wlfc->stats.txstatus_in += len;
++
++	if (status_flag == WLFC_CTL_PKTFLAG_DISCARD) {
++		wlfc->stats.pkt_freed += len;
++	} else if (status_flag == WLFC_CTL_PKTFLAG_DISCARD_NOACK) {
++		wlfc->stats.pkt_freed += len;
++	} else if (status_flag == WLFC_CTL_PKTFLAG_D11SUPPRESS) {
++		wlfc->stats.d11_suppress += len;
++		remove_from_hanger = 0;
++	} else if (status_flag == WLFC_CTL_PKTFLAG_WLSUPPRESS) {
++		wlfc->stats.wl_suppress += len;
++		remove_from_hanger = 0;
++	} else if (status_flag == WLFC_CTL_PKTFLAG_TOSSED_BYWLC) {
++		wlfc->stats.wlc_tossed_pkts += len;
++	} else if (status_flag == WLFC_CTL_PKTFLAG_SUPPRESS_ACKED) {
++		wlfc->stats.pkt_freed += len;
++	}
++
++	if (dhd->proptxstatus_txstatus_ignore) {
++		if (!remove_from_hanger) {
++			DHD_ERROR(("suppress txstatus: %d\n", status_flag));
++		}
++		return BCME_OK;
++	}
++
++	status_flag_ori = status_flag;
++	remove_from_hanger_ori = remove_from_hanger;
++
++	while (count < len) {
++		if (status_flag == WLFC_CTL_PKTFLAG_SUPPRESS_ACKED) {
++			dhd_wlfc_suppressed_acked_update(dhd, hslot, fifo_id, hcnt);
++		}
++		if (WLFC_GET_AFQ(dhd->wlfc_mode)) {
++			ret = _dhd_wlfc_deque_afq(wlfc, hslot, hcnt, fifo_id, &pktbuf);
++		} else {
++			status_flag = status_flag_ori;
++			remove_from_hanger = remove_from_hanger_ori;
++			ret = _dhd_wlfc_hanger_poppkt(wlfc->hanger, hslot, &pktbuf, FALSE);
++			if (!pktbuf) {
++				_dhd_wlfc_hanger_free_pkt(wlfc, hslot,
++					WLFC_HANGER_PKT_STATE_TXSTATUS, -1);
++				goto cont;
++			} else {
++				wlfc_hanger_t* h = (wlfc_hanger_t*)wlfc->hanger;
++				if (h->items[hslot].state == WLFC_HANGER_ITEM_STATE_FLUSHED) {
++					status_flag = WLFC_CTL_PKTFLAG_DISCARD;
++					remove_from_hanger = 1;
++				}
++			}
++		}
++
++		if ((ret != BCME_OK) || !pktbuf) {
++			goto cont;
++		}
++
++		bcm_pkt_validate_chk(pktbuf);
++
++		/* set fifo_id to correct value because not all FW does that */
++		fifo_id = DHD_PKTTAG_FIFO(PKTTAG(pktbuf));
++
++		entry = _dhd_wlfc_find_table_entry(wlfc, pktbuf);
++
++		if (!remove_from_hanger) {
++			/* this packet was suppressed */
++			if (!entry->suppressed || (entry->generation != gen)) {
++				if (!entry->suppressed) {
++					entry->suppr_transit_count = entry->transit_count;
++					if (p_mac) {
++						*p_mac = entry;
++					}
++				} else {
++					DHD_ERROR(("gen(%d), entry->generation(%d)\n",
++						gen, entry->generation));
++				}
++				entry->suppressed = TRUE;
++
++			}
++			entry->generation = gen;
++		}
++
++#ifdef PROP_TXSTATUS_DEBUG
++		if (!WLFC_GET_AFQ(dhd->wlfc_mode))
++		{
++			uint32 new_t = OSL_SYSUPTIME();
++			uint32 old_t;
++			uint32 delta;
++			old_t = ((wlfc_hanger_t*)(wlfc->hanger))->items[hslot].push_time;
++
++
++			wlfc->stats.latency_sample_count++;
++			if (new_t > old_t)
++				delta = new_t - old_t;
++			else
++				delta = 0xffffffff + new_t - old_t;
++			wlfc->stats.total_status_latency += delta;
++			wlfc->stats.latency_most_recent = delta;
++
++			wlfc->stats.deltas[wlfc->stats.idx_delta++] = delta;
++			if (wlfc->stats.idx_delta == sizeof(wlfc->stats.deltas)/sizeof(uint32))
++				wlfc->stats.idx_delta = 0;
++		}
++#endif /* PROP_TXSTATUS_DEBUG */
++
++		/* pick up the implicit credit from this packet */
++		if (DHD_PKTTAG_CREDITCHECK(PKTTAG(pktbuf))) {
++			_dhd_wlfc_return_implied_credit(wlfc, pktbuf);
++		} else {
++			/*
++			if this packet did not count against FIFO credit, it must have
++			taken a requested_credit from the destination entry (for pspoll etc.)
++			*/
++			if (!DHD_PKTTAG_ONETIMEPKTRQST(PKTTAG(pktbuf))) {
++				entry->requested_credit++;
++#if defined(DHD_WLFC_THREAD)
++				_dhd_wlfc_thread_wakeup(dhd);
++#endif /* DHD_WLFC_THREAD */
++			}
++#ifdef PROP_TXSTATUS_DEBUG
++			entry->dstncredit_acks++;
++#endif
++		}
++
++		if ((status_flag == WLFC_CTL_PKTFLAG_D11SUPPRESS) ||
++			(status_flag == WLFC_CTL_PKTFLAG_WLSUPPRESS)) {
++			/* save generation bit inside packet */
++			WL_TXSTATUS_SET_GENERATION(DHD_PKTTAG_H2DTAG(PKTTAG(pktbuf)), gen);
++
++			if (WLFC_GET_REUSESEQ(dhd->wlfc_mode)) {
++				WL_SEQ_SET_REUSE(DHD_PKTTAG_H2DSEQ(PKTTAG(pktbuf)), seq_fromfw);
++				WL_SEQ_SET_NUM(DHD_PKTTAG_H2DSEQ(PKTTAG(pktbuf)), seq_num);
++			}
++
++			ret = _dhd_wlfc_enque_suppressed(wlfc, fifo_id, pktbuf);
++			if (ret != BCME_OK) {
++				/* delay q is full, drop this packet */
++				DHD_WLFC_QMON_COMPLETE(entry);
++				_dhd_wlfc_prec_drop(dhd, (fifo_id << 1) + 1, pktbuf, FALSE);
++			} else {
++				if (!WLFC_GET_AFQ(dhd->wlfc_mode)) {
++					/* Mark suppressed to avoid a double free
++					during wlfc cleanup
++					*/
++					_dhd_wlfc_hanger_mark_suppressed(wlfc->hanger, hslot, gen);
++				}
++			}
++		} else {
++
++			DHD_WLFC_QMON_COMPLETE(entry);
++
++			if (!WLFC_GET_AFQ(dhd->wlfc_mode)) {
++				_dhd_wlfc_hanger_free_pkt(wlfc, hslot,
++					WLFC_HANGER_PKT_STATE_TXSTATUS, TRUE);
++			} else {
++				dhd_txcomplete(dhd, pktbuf, TRUE);
++				wlfc->pkt_cnt_in_drv[DHD_PKTTAG_IF(PKTTAG(pktbuf))]
++					[DHD_PKTTAG_FIFO(PKTTAG(pktbuf))]--;
++				wlfc->stats.pktout++;
++				/* free the packet */
++				PKTFREE(wlfc->osh, pktbuf, TRUE);
++			}
++		}
++		/* pkt back from firmware side */
++		if (entry->transit_count)
++			entry->transit_count--;
++		if (entry->suppr_transit_count) {
++			entry->suppr_transit_count--;
++			if (entry->suppressed &&
++				(!entry->onbus_pkts_count) &&
++				(!entry->suppr_transit_count))
++				entry->suppressed = FALSE;
++		}
++
++cont:
++		hcnt = (hcnt + 1) & WL_TXSTATUS_FREERUNCTR_MASK;
++		if (!WLFC_GET_AFQ(dhd->wlfc_mode)) {
++			hslot = (hslot + 1) & WL_TXSTATUS_HSLOT_MASK;
++		}
++
++		if (WLFC_GET_REUSESEQ(dhd->wlfc_mode) && seq_fromfw) {
++			seq_num = (seq_num + 1) & WL_SEQ_NUM_MASK;
++		}
++
++		count++;
++	}
++
++	return BCME_OK;
++} /* _dhd_wlfc_compressed_txstatus_update */
++
++/**
++ * Called when eg host receives a 'WLFC_CTL_TYPE_FIFO_CREDITBACK' event from the dongle.
++ *    @param[in] credits caller supplied credit that will be added to the host credit.
++ */
++static int
++_dhd_wlfc_fifocreditback_indicate(dhd_pub_t *dhd, uint8* credits)
++{
++	int i;
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	for (i = 0; i < WLFC_CTL_VALUE_LEN_FIFO_CREDITBACK; i++) {
++#ifdef PROP_TXSTATUS_DEBUG
++		wlfc->stats.fifo_credits_back[i] += credits[i];
++#endif
++
++		/* update FIFO credits */
++		if (dhd->proptxstatus_mode == WLFC_FCMODE_EXPLICIT_CREDIT)
++		{
++			int lender; /* Note that borrower is i */
++
++			/* Return credits to highest priority lender first */
++			for (lender = AC_COUNT; (lender >= 0) && (credits[i] > 0); lender--) {
++				if (wlfc->credits_borrowed[i][lender] > 0) {
++					if (credits[i] >= wlfc->credits_borrowed[i][lender]) {
++						credits[i] -=
++							(uint8)wlfc->credits_borrowed[i][lender];
++						wlfc->FIFO_credit[lender] +=
++						    wlfc->credits_borrowed[i][lender];
++						wlfc->credits_borrowed[i][lender] = 0;
++					} else {
++						wlfc->credits_borrowed[i][lender] -= credits[i];
++						wlfc->FIFO_credit[lender] += credits[i];
++						credits[i] = 0;
++					}
++				}
++			}
++
++			/* If we have more credits left over, these must belong to the AC */
++			if (credits[i] > 0) {
++				wlfc->FIFO_credit[i] += credits[i];
++			}
++
++			if (wlfc->FIFO_credit[i] > wlfc->Init_FIFO_credit[i]) {
++				wlfc->FIFO_credit[i] = wlfc->Init_FIFO_credit[i];
++			}
++		}
++	}
++
++#if defined(DHD_WLFC_THREAD)
++	_dhd_wlfc_thread_wakeup(dhd);
++#endif /* defined(DHD_WLFC_THREAD) */
++
++	return BCME_OK;
++} /* _dhd_wlfc_fifocreditback_indicate */
++
++#ifndef BCMDBUS
++/** !BCMDBUS specific function */
++static void
++_dhd_wlfc_suppress_txq(dhd_pub_t *dhd, f_processpkt_t fn, void *arg)
++{
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	wlfc_mac_descriptor_t* entry;
++	int prec;
++	void *pkt = NULL, *head = NULL, *tail = NULL;
++	struct pktq *txq = (struct pktq *)dhd_bus_txq(dhd->bus);
++	uint8	results[WLFC_CTL_VALUE_LEN_TXSTATUS+WLFC_CTL_VALUE_LEN_SEQ];
++	uint8 credits[WLFC_CTL_VALUE_LEN_FIFO_CREDITBACK] = {0};
++	uint32 htod = 0;
++	uint16 htodseq = 0;
++	bool bCreditUpdate = FALSE;
++
++	dhd_os_sdlock_txq(dhd);
++	for (prec = 0; prec < txq->num_prec; prec++) {
++		while ((pkt = _dhd_wlfc_pktq_pdeq_with_fn(txq, prec, fn, arg))) {
++			if (!head) {
++				head = pkt;
++			}
++			if (tail) {
++				PKTSETLINK(tail, pkt);
++			}
++			tail = pkt;
++		}
++	}
++	dhd_os_sdunlock_txq(dhd);
++
++	while ((pkt = head)) {
++		head = PKTLINK(pkt);
++		PKTSETLINK(pkt, NULL);
++
++		entry = _dhd_wlfc_find_table_entry(wlfc, pkt);
++		if (!entry) {
++			PKTFREE(dhd->osh, pkt, TRUE);
++			continue;
++		}
++		if (entry->onbus_pkts_count > 0) {
++			entry->onbus_pkts_count--;
++		}
++		if (entry->suppressed &&
++				(!entry->onbus_pkts_count) &&
++				(!entry->suppr_transit_count)) {
++			entry->suppressed = FALSE;
++		}
++		/* fake a suppression txstatus */
++		htod = DHD_PKTTAG_H2DTAG(PKTTAG(pkt));
++		WL_TXSTATUS_SET_FLAGS(htod, WLFC_CTL_PKTFLAG_WLSUPPRESS);
++		WL_TXSTATUS_SET_GENERATION(htod, entry->generation);
++		htod = htol32(htod);
++		memcpy(results, &htod, WLFC_CTL_VALUE_LEN_TXSTATUS);
++		if (WLFC_GET_REUSESEQ(dhd->wlfc_mode)) {
++			htodseq = DHD_PKTTAG_H2DSEQ(PKTTAG(pkt));
++			if (IS_WL_TO_REUSE_SEQ(htodseq)) {
++				SET_WL_HAS_ASSIGNED_SEQ(htodseq);
++				RESET_WL_TO_REUSE_SEQ(htodseq);
++			}
++			htodseq = htol16(htodseq);
++			memcpy(results + WLFC_CTL_VALUE_LEN_TXSTATUS, &htodseq,
++				WLFC_CTL_VALUE_LEN_SEQ);
++		}
++		if (WLFC_GET_AFQ(dhd->wlfc_mode)) {
++			_dhd_wlfc_enque_afq(wlfc, pkt);
++		}
++		_dhd_wlfc_compressed_txstatus_update(dhd, results, 1, NULL);
++
++		/* fake a fifo credit back */
++		if (DHD_PKTTAG_CREDITCHECK(PKTTAG(pkt))) {
++			credits[DHD_PKTTAG_FIFO(PKTTAG(pkt))]++;
++			bCreditUpdate = TRUE;
++		}
++	}
++
++	if (bCreditUpdate) {
++		_dhd_wlfc_fifocreditback_indicate(dhd, credits);
++	}
++} /* _dhd_wlfc_suppress_txq */
++#endif /* !BCMDBUS */
++
++static int
++_dhd_wlfc_dbg_senum_check(dhd_pub_t *dhd, uint8 *value)
++{
++	uint32 timestamp;
++
++	(void)dhd;
++
++	bcopy(&value[2], &timestamp, sizeof(uint32));
++	timestamp = ltoh32(timestamp);
++	DHD_INFO(("RXPKT: SEQ: %d, timestamp %d\n", value[1], timestamp));
++	return BCME_OK;
++}
++
++static int
++_dhd_wlfc_rssi_indicate(dhd_pub_t *dhd, uint8* rssi)
++{
++	(void)dhd;
++	(void)rssi;
++	return BCME_OK;
++}
++
++static void
++_dhd_wlfc_add_requested_entry(athost_wl_status_info_t* wlfc, wlfc_mac_descriptor_t* entry)
++{
++	int i;
++
++	if (!wlfc || !entry) {
++		return;
++	}
++
++	for (i = 0; i < wlfc->requested_entry_count; i++) {
++		if (entry == wlfc->requested_entry[i]) {
++			break;
++		}
++	}
++
++	if (i == wlfc->requested_entry_count) {
++		/* no match entry found */
++		ASSERT(wlfc->requested_entry_count <= (WLFC_MAC_DESC_TABLE_SIZE-1));
++		wlfc->requested_entry[wlfc->requested_entry_count++] = entry;
++	}
++}
++
++/** called on eg receiving 'mac open' event from the dongle. */
++static void
++_dhd_wlfc_remove_requested_entry(athost_wl_status_info_t* wlfc, wlfc_mac_descriptor_t* entry)
++{
++	int i;
++
++	if (!wlfc || !entry) {
++		return;
++	}
++
++	for (i = 0; i < wlfc->requested_entry_count; i++) {
++		if (entry == wlfc->requested_entry[i]) {
++			break;
++		}
++	}
++
++	if (i < wlfc->requested_entry_count) {
++		/* found */
++		ASSERT(wlfc->requested_entry_count > 0);
++		wlfc->requested_entry_count--;
++		if (i != wlfc->requested_entry_count) {
++			wlfc->requested_entry[i] =
++				wlfc->requested_entry[wlfc->requested_entry_count];
++		}
++		wlfc->requested_entry[wlfc->requested_entry_count] = NULL;
++	}
++}
++
++/** called on eg receiving a WLFC_CTL_TYPE_MACDESC_ADD TLV from the dongle */
++static int
++_dhd_wlfc_mac_table_update(dhd_pub_t *dhd, uint8* value, uint8 type)
++{
++	int rc;
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	wlfc_mac_descriptor_t* table;
++	uint8 existing_index;
++	uint8 table_index;
++	uint8 ifid;
++	uint8* ea;
++
++	WLFC_DBGMESG(("%s(), mac [%02x:%02x:%02x:%02x:%02x:%02x],%s,idx:%d,id:0x%02x\n",
++		__FUNCTION__, value[2], value[3], value[4], value[5], value[6], value[7],
++		((type == WLFC_CTL_TYPE_MACDESC_ADD) ? "ADD":"DEL"),
++		WLFC_MAC_DESC_GET_LOOKUP_INDEX(value[0]), value[0]));
++
++	table = wlfc->destination_entries.nodes;
++	table_index = WLFC_MAC_DESC_GET_LOOKUP_INDEX(value[0]);
++	ifid = value[1];
++	ea = &value[2];
++
++	_dhd_wlfc_remove_requested_entry(wlfc, &table[table_index]);
++	if (type == WLFC_CTL_TYPE_MACDESC_ADD) {
++		existing_index = _dhd_wlfc_find_mac_desc_id_from_mac(dhd, &value[2]);
++		if ((existing_index != WLFC_MAC_DESC_ID_INVALID) &&
++			(existing_index != table_index) && table[existing_index].occupied) {
++			/*
++			there is an existing different entry, free the old one
++			and move it to new index if necessary.
++			*/
++			rc = _dhd_wlfc_mac_entry_update(wlfc, &table[existing_index],
++				eWLFC_MAC_ENTRY_ACTION_DEL, table[existing_index].interface_id,
++				table[existing_index].iftype, NULL, _dhd_wlfc_entrypkt_fn,
++				&table[existing_index]);
++		}
++
++		if (!table[table_index].occupied) {
++			/* this new MAC entry does not exist, create one */
++			table[table_index].mac_handle = value[0];
++			rc = _dhd_wlfc_mac_entry_update(wlfc, &table[table_index],
++				eWLFC_MAC_ENTRY_ACTION_ADD, ifid,
++				wlfc->destination_entries.interfaces[ifid].iftype,
++				ea, NULL, NULL);
++		} else {
++			/* the space should have been empty, but it's not */
++			wlfc->stats.mac_update_failed++;
++		}
++	}
++
++	if (type == WLFC_CTL_TYPE_MACDESC_DEL) {
++		if (table[table_index].occupied) {
++				rc = _dhd_wlfc_mac_entry_update(wlfc, &table[table_index],
++					eWLFC_MAC_ENTRY_ACTION_DEL, ifid,
++					wlfc->destination_entries.interfaces[ifid].iftype,
++					ea, _dhd_wlfc_entrypkt_fn, &table[table_index]);
++		} else {
++			/* the space should have been occupied, but it's not */
++			wlfc->stats.mac_update_failed++;
++		}
++	}
++	BCM_REFERENCE(rc);
++	return BCME_OK;
++} /* _dhd_wlfc_mac_table_update */
++
++/** Called on a 'mac open' or 'mac close' event indicated by the dongle */
++static int
++_dhd_wlfc_psmode_update(dhd_pub_t *dhd, uint8* value, uint8 type)
++{
++	/* Handle PS on/off indication */
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	wlfc_mac_descriptor_t* table;
++	wlfc_mac_descriptor_t* desc; /* a table maps from mac handle to mac descriptor */
++	uint8 mac_handle = value[0];
++	int i;
++
++	table = wlfc->destination_entries.nodes;
++	desc = &table[WLFC_MAC_DESC_GET_LOOKUP_INDEX(mac_handle)];
++	if (desc->occupied) {
++		if (type == WLFC_CTL_TYPE_MAC_OPEN) {
++			desc->state = WLFC_STATE_OPEN;
++			desc->ac_bitmap = 0xff;
++			DHD_WLFC_CTRINC_MAC_OPEN(desc);
++			desc->requested_credit = 0;
++			desc->requested_packet = 0;
++			_dhd_wlfc_remove_requested_entry(wlfc, desc);
++		} else {
++			desc->state = WLFC_STATE_CLOSE;
++			DHD_WLFC_CTRINC_MAC_CLOSE(desc);
++			/* Indicate to firmware if there is any traffic pending. */
++			for (i = 0; i < AC_COUNT; i++) {
++				_dhd_wlfc_traffic_pending_check(wlfc, desc, i);
++			}
++		}
++	} else {
++		wlfc->stats.psmode_update_failed++;
++	}
++
++	return BCME_OK;
++} /* _dhd_wlfc_psmode_update */
++
++/** called upon receiving 'interface open' or 'interface close' event from the dongle */
++static int
++_dhd_wlfc_interface_update(dhd_pub_t *dhd, uint8* value, uint8 type)
++{
++	/* Handle PS on/off indication */
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	wlfc_mac_descriptor_t* table;
++	uint8 if_id = value[0];
++
++	if (if_id < WLFC_MAX_IFNUM) {
++		table = wlfc->destination_entries.interfaces;
++		if (table[if_id].occupied) {
++			if (type == WLFC_CTL_TYPE_INTERFACE_OPEN) {
++				table[if_id].state = WLFC_STATE_OPEN;
++				/* WLFC_DBGMESG(("INTERFACE[%d] OPEN\n", if_id)); */
++			} else {
++				table[if_id].state = WLFC_STATE_CLOSE;
++				/* WLFC_DBGMESG(("INTERFACE[%d] CLOSE\n", if_id)); */
++			}
++			return BCME_OK;
++		}
++	}
++	wlfc->stats.interface_update_failed++;
++
++	return BCME_OK;
++}
++
++/** Called on receiving a WLFC_CTL_TYPE_MAC_REQUEST_CREDIT TLV from the dongle */
++static int
++_dhd_wlfc_credit_request(dhd_pub_t *dhd, uint8* value)
++{
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	wlfc_mac_descriptor_t* table;
++	wlfc_mac_descriptor_t* desc;
++	uint8 mac_handle;
++	uint8 credit;
++
++	table = wlfc->destination_entries.nodes;
++	mac_handle = value[1];
++	credit = value[0];
++
++	desc = &table[WLFC_MAC_DESC_GET_LOOKUP_INDEX(mac_handle)];
++	if (desc->occupied) {
++		desc->requested_credit = credit;
++
++		desc->ac_bitmap = value[2] & (~(1<<AC_COUNT));
++		_dhd_wlfc_add_requested_entry(wlfc, desc);
++#if defined(DHD_WLFC_THREAD)
++		if (credit) {
++			_dhd_wlfc_thread_wakeup(dhd);
++		}
++#endif /* DHD_WLFC_THREAD */
++	} else {
++		wlfc->stats.credit_request_failed++;
++	}
++
++	return BCME_OK;
++}
++
++/** Called on receiving a WLFC_CTL_TYPE_MAC_REQUEST_PACKET TLV from the dongle */
++static int
++_dhd_wlfc_packet_request(dhd_pub_t *dhd, uint8* value)
++{
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	wlfc_mac_descriptor_t* table;
++	wlfc_mac_descriptor_t* desc;
++	uint8 mac_handle;
++	uint8 packet_count;
++
++	table = wlfc->destination_entries.nodes;
++	mac_handle = value[1];
++	packet_count = value[0];
++
++	desc = &table[WLFC_MAC_DESC_GET_LOOKUP_INDEX(mac_handle)];
++	if (desc->occupied) {
++		desc->requested_packet = packet_count;
++
++		desc->ac_bitmap = value[2] & (~(1<<AC_COUNT));
++		_dhd_wlfc_add_requested_entry(wlfc, desc);
++#if defined(DHD_WLFC_THREAD)
++		if (packet_count) {
++			_dhd_wlfc_thread_wakeup(dhd);
++		}
++#endif /* DHD_WLFC_THREAD */
++	} else {
++		wlfc->stats.packet_request_failed++;
++	}
++
++	return BCME_OK;
++}
++
++/** Called when host receives a WLFC_CTL_TYPE_HOST_REORDER_RXPKTS TLV from the dongle */
++static void
++_dhd_wlfc_reorderinfo_indicate(uint8 *val, uint8 len, uchar *info_buf, uint *info_len)
++{
++	if (info_len) {
++		/* Check copy length to avoid buffer overrun. In case of length exceeding
++		*  WLHOST_REORDERDATA_TOTLEN, return failure instead sending incomplete result
++		*  of length WLHOST_REORDERDATA_TOTLEN
++		*/
++		if ((info_buf) && (len <= WLHOST_REORDERDATA_TOTLEN)) {
++			bcopy(val, info_buf, len);
++			*info_len = len;
++		} else {
++			*info_len = 0;
++		}
++	}
++}
++
++/*
++ * public functions
++ */
++
++bool dhd_wlfc_is_supported(dhd_pub_t *dhd)
++{
++	bool rc = TRUE;
++
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return FALSE;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		rc =  FALSE;
++	}
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return rc;
++}
++
++int dhd_wlfc_enable(dhd_pub_t *dhd)
++{
++	int i, rc = BCME_OK;
++	athost_wl_status_info_t* wlfc;
++
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_enabled || dhd->wlfc_state) {
++		rc = BCME_OK;
++		goto exit;
++	}
++
++	/* allocate space to track txstatus propagated from firmware */
++	dhd->wlfc_state = DHD_OS_PREALLOC(dhd, DHD_PREALLOC_DHD_WLFC_INFO,
++		sizeof(athost_wl_status_info_t));
++	if (dhd->wlfc_state == NULL) {
++		rc = BCME_NOMEM;
++		goto exit;
++	}
++
++	/* initialize state space */
++	wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	memset(wlfc, 0, sizeof(athost_wl_status_info_t));
++
++	/* remember osh & dhdp */
++	wlfc->osh = dhd->osh;
++	wlfc->dhdp = dhd;
++
++	if (!WLFC_GET_AFQ(dhd->wlfc_mode)) {
++		wlfc->hanger = _dhd_wlfc_hanger_create(dhd, WLFC_HANGER_MAXITEMS);
++		if (wlfc->hanger == NULL) {
++			DHD_OS_PREFREE(dhd, dhd->wlfc_state,
++				sizeof(athost_wl_status_info_t));
++			dhd->wlfc_state = NULL;
++			rc = BCME_NOMEM;
++			goto exit;
++		}
++	}
++
++	dhd->proptxstatus_mode = WLFC_FCMODE_EXPLICIT_CREDIT;
++	/* default to check rx pkt */
++	dhd->wlfc_rxpkt_chk = TRUE;
++	if (dhd->op_mode & DHD_FLAG_IBSS_MODE) {
++		dhd->wlfc_rxpkt_chk = FALSE;
++	}
++
++	/* initialize all interfaces to accept traffic */
++	for (i = 0; i < WLFC_MAX_IFNUM; i++) {
++		wlfc->hostif_flow_state[i] = OFF;
++	}
++
++	_dhd_wlfc_mac_entry_update(wlfc, &wlfc->destination_entries.other,
++		eWLFC_MAC_ENTRY_ACTION_ADD, 0xff, 0, NULL, NULL, NULL);
++
++	wlfc->allow_credit_borrow = 0;
++	wlfc->single_ac = 0;
++	wlfc->single_ac_timestamp = 0;
++
++
++exit:
++	DHD_ERROR(("%s: ret=%d\n", __FUNCTION__, rc));
++	dhd_os_wlfc_unblock(dhd);
++
++	return rc;
++} /* dhd_wlfc_enable */
++
++#ifdef SUPPORT_P2P_GO_PS
++
++/**
++ * Called when the host platform enters a lower power mode, eg right before a system hibernate.
++ * SUPPORT_P2P_GO_PS specific function.
++ */
++int
++dhd_wlfc_suspend(dhd_pub_t *dhd)
++{
++	uint32 tlv = 0;
++
++	DHD_TRACE(("%s: masking wlfc events\n", __FUNCTION__));
++	if (!dhd->wlfc_enabled)
++		return -1;
++
++	if (!dhd_wl_ioctl_get_intiovar(dhd, "tlv", &tlv, WLC_GET_VAR, FALSE, 0))
++		return -1;
++	if ((tlv & (WLFC_FLAGS_RSSI_SIGNALS | WLFC_FLAGS_XONXOFF_SIGNALS)) == 0)
++		return 0;
++	tlv &= ~(WLFC_FLAGS_RSSI_SIGNALS | WLFC_FLAGS_XONXOFF_SIGNALS);
++	if (!dhd_wl_ioctl_set_intiovar(dhd, "tlv", tlv, WLC_SET_VAR, TRUE, 0))
++		return -1;
++
++	return 0;
++}
++
++/**
++ * Called when the host platform resumes from a power management operation, eg resume after a
++ * system hibernate. SUPPORT_P2P_GO_PS specific function.
++ */
++int
++dhd_wlfc_resume(dhd_pub_t *dhd)
++{
++	uint32 tlv = 0;
++
++	DHD_TRACE(("%s: unmasking wlfc events\n", __FUNCTION__));
++	if (!dhd->wlfc_enabled)
++		return -1;
++
++	if (!dhd_wl_ioctl_get_intiovar(dhd, "tlv", &tlv, WLC_GET_VAR, FALSE, 0))
++		return -1;
++	if ((tlv & (WLFC_FLAGS_RSSI_SIGNALS | WLFC_FLAGS_XONXOFF_SIGNALS)) ==
++		(WLFC_FLAGS_RSSI_SIGNALS | WLFC_FLAGS_XONXOFF_SIGNALS))
++		return 0;
++	tlv |= (WLFC_FLAGS_RSSI_SIGNALS | WLFC_FLAGS_XONXOFF_SIGNALS);
++	if (!dhd_wl_ioctl_set_intiovar(dhd, "tlv", tlv, WLC_SET_VAR, TRUE, 0))
++		return -1;
++
++	return 0;
++}
++
++#endif /* SUPPORT_P2P_GO_PS */
++
++/** A flow control header was received from firmware, containing one or more TLVs */
++int
++dhd_wlfc_parse_header_info(dhd_pub_t *dhd, void* pktbuf, int tlv_hdr_len, uchar *reorder_info_buf,
++	uint *reorder_info_len)
++{
++	uint8 type, len;
++	uint8* value;
++	uint8* tmpbuf;
++	uint16 remainder = (uint16)tlv_hdr_len;
++	uint16 processed = 0;
++	athost_wl_status_info_t* wlfc = NULL;
++	void* entry;
++
++	if ((dhd == NULL) || (pktbuf == NULL)) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (dhd->proptxstatus_mode != WLFC_ONLY_AMPDU_HOSTREORDER) {
++		if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++			dhd_os_wlfc_unblock(dhd);
++			return WLFC_UNSUPPORTED;
++		}
++		wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	}
++
++	tmpbuf = (uint8*)PKTDATA(dhd->osh, pktbuf);
++
++	if (remainder) {
++		while ((processed < (WLFC_MAX_PENDING_DATALEN * 2)) && (remainder > 0)) {
++			type = tmpbuf[processed];
++			if (type == WLFC_CTL_TYPE_FILLER) {
++				remainder -= 1;
++				processed += 1;
++				continue;
++			}
++
++			len  = tmpbuf[processed + 1];
++			value = &tmpbuf[processed + 2];
++
++			if (remainder < (2 + len))
++				break;
++
++			remainder -= 2 + len;
++			processed += 2 + len;
++			entry = NULL;
++
++			DHD_INFO(("%s():%d type %d remainder %d processed %d\n",
++				__FUNCTION__, __LINE__, type, remainder, processed));
++
++			if (type == WLFC_CTL_TYPE_HOST_REORDER_RXPKTS)
++				_dhd_wlfc_reorderinfo_indicate(value, len, reorder_info_buf,
++					reorder_info_len);
++
++			if (wlfc == NULL) {
++				ASSERT(dhd->proptxstatus_mode == WLFC_ONLY_AMPDU_HOSTREORDER);
++
++				if (type != WLFC_CTL_TYPE_HOST_REORDER_RXPKTS &&
++					type != WLFC_CTL_TYPE_TRANS_ID)
++					DHD_INFO(("%s():%d dhd->wlfc_state is NULL yet!"
++					" type %d remainder %d processed %d\n",
++					__FUNCTION__, __LINE__, type, remainder, processed));
++				continue;
++			}
++
++			if (type == WLFC_CTL_TYPE_TXSTATUS) {
++				_dhd_wlfc_compressed_txstatus_update(dhd, value, 1, &entry);
++			} else if (type == WLFC_CTL_TYPE_COMP_TXSTATUS) {
++				uint8 compcnt_offset = WLFC_CTL_VALUE_LEN_TXSTATUS;
++
++				if (WLFC_GET_REUSESEQ(dhd->wlfc_mode)) {
++					compcnt_offset += WLFC_CTL_VALUE_LEN_SEQ;
++				}
++				_dhd_wlfc_compressed_txstatus_update(dhd, value,
++					value[compcnt_offset], &entry);
++			} else if (type == WLFC_CTL_TYPE_FIFO_CREDITBACK) {
++				_dhd_wlfc_fifocreditback_indicate(dhd, value);
++			} else if (type == WLFC_CTL_TYPE_RSSI) {
++				_dhd_wlfc_rssi_indicate(dhd, value);
++			} else if (type == WLFC_CTL_TYPE_MAC_REQUEST_CREDIT) {
++				_dhd_wlfc_credit_request(dhd, value);
++			} else if (type == WLFC_CTL_TYPE_MAC_REQUEST_PACKET) {
++				_dhd_wlfc_packet_request(dhd, value);
++			} else if ((type == WLFC_CTL_TYPE_MAC_OPEN) ||
++				(type == WLFC_CTL_TYPE_MAC_CLOSE)) {
++				_dhd_wlfc_psmode_update(dhd, value, type);
++			} else if ((type == WLFC_CTL_TYPE_MACDESC_ADD) ||
++				(type == WLFC_CTL_TYPE_MACDESC_DEL)) {
++				_dhd_wlfc_mac_table_update(dhd, value, type);
++			} else if (type == WLFC_CTL_TYPE_TRANS_ID) {
++				_dhd_wlfc_dbg_senum_check(dhd, value);
++			} else if ((type == WLFC_CTL_TYPE_INTERFACE_OPEN) ||
++				(type == WLFC_CTL_TYPE_INTERFACE_CLOSE)) {
++				_dhd_wlfc_interface_update(dhd, value, type);
++			}
++
++#ifndef BCMDBUS
++			if (entry && WLFC_GET_REORDERSUPP(dhd->wlfc_mode)) {
++				/* suppress all packets for this mac entry from bus->txq */
++				_dhd_wlfc_suppress_txq(dhd, _dhd_wlfc_entrypkt_fn, entry);
++			}
++#endif /* !BCMDBUS */
++		} /* while */
++
++		if (remainder != 0 && wlfc) {
++			/* trouble..., something is not right */
++			wlfc->stats.tlv_parse_failed++;
++		}
++	} /* if */
++
++	if (wlfc)
++		wlfc->stats.dhd_hdrpulls++;
++
++	dhd_os_wlfc_unblock(dhd);
++	return BCME_OK;
++}
++
++KERNEL_THREAD_RETURN_TYPE
++dhd_wlfc_transfer_packets(void *data)
++{
++	dhd_pub_t *dhdp = (dhd_pub_t *)data;
++	int ac, single_ac = 0, rc = BCME_OK;
++	dhd_wlfc_commit_info_t  commit_info;
++	athost_wl_status_info_t* ctx;
++	int bus_retry_count = 0;
++	int pkt_send = 0;
++	int pkt_send_per_ac = 0;
++
++	uint8 tx_map = 0; /* packets (send + in queue), Bitmask for 4 ACs + BC/MC */
++	uint8 rx_map = 0; /* received packets, Bitmask for 4 ACs + BC/MC */
++	uint8 packets_map = 0; /* packets in queue, Bitmask for 4 ACs + BC/MC */
++	bool no_credit = FALSE;
++
++	int lender;
++
++#if defined(DHD_WLFC_THREAD)
++	/* wait till someone wakeup me up, will change it at running time */
++	int wait_msec = msecs_to_jiffies(0xFFFFFFFF);
++#endif /* defined(DHD_WLFC_THREAD) */
++
++#if defined(DHD_WLFC_THREAD)
++	while (1) {
++		bus_retry_count = 0;
++		pkt_send = 0;
++		tx_map = 0;
++		rx_map = 0;
++		packets_map = 0;
++		wait_msec = wait_event_interruptible_timeout(dhdp->wlfc_wqhead,
++			dhdp->wlfc_thread_go, wait_msec);
++		if (kthread_should_stop()) {
++			break;
++		}
++		dhdp->wlfc_thread_go = FALSE;
++
++		dhd_os_wlfc_block(dhdp);
++#endif /* defined(DHD_WLFC_THREAD) */
++		ctx = (athost_wl_status_info_t*)dhdp->wlfc_state;
++#if defined(DHD_WLFC_THREAD)
++		if (!ctx)
++			goto exit;
++#endif /* defined(DHD_WLFC_THREAD) */
++
++	memset(&commit_info, 0, sizeof(commit_info));
++
++	/*
++	Commit packets for regular AC traffic. Higher priority first.
++	First, use up FIFO credits available to each AC. Based on distribution
++	and credits left, borrow from other ACs as applicable
++
++	-NOTE:
++	If the bus between the host and firmware is overwhelmed by the
++	traffic from host, it is possible that higher priority traffic
++	starves the lower priority queue. If that occurs often, we may
++	have to employ weighted round-robin or ucode scheme to avoid
++	low priority packet starvation.
++	*/
++
++	for (ac = AC_COUNT; ac >= 0; ac--) {
++		if (dhdp->wlfc_rxpkt_chk) {
++			/* check rx packet */
++			uint32 curr_t = OSL_SYSUPTIME(), delta;
++
++			delta = curr_t - ctx->rx_timestamp[ac];
++			if (delta < WLFC_RX_DETECTION_THRESHOLD_MS) {
++				rx_map |= (1 << ac);
++			}
++		}
++
++		if (ctx->pkt_cnt_per_ac[ac] == 0) {
++			continue;
++		}
++
++		tx_map |= (1 << ac);
++		single_ac = ac + 1;
++		pkt_send_per_ac = 0;
++		while ((FALSE == dhdp->proptxstatus_txoff) &&
++				(pkt_send_per_ac < WLFC_PACKET_BOUND)) {
++			/* packets from delayQ with less priority are fresh and
++			 * they'd need header and have no MAC entry
++			 */
++			no_credit = (ctx->FIFO_credit[ac] < 1);
++			if (dhdp->proptxstatus_credit_ignore ||
++				((ac == AC_COUNT) && !ctx->bcmc_credit_supported)) {
++				no_credit = FALSE;
++			}
++
++			lender = -1;
++#ifdef LIMIT_BORROW
++			if (no_credit && (ac < AC_COUNT) && (tx_map >= rx_map) &&
++				dhdp->wlfc_borrow_allowed) {
++				/* try borrow from lower priority */
++				lender = _dhd_wlfc_borrow_credit(ctx, ac - 1, ac, FALSE);
++				if (lender != -1) {
++					no_credit = FALSE;
++				}
++			}
++#endif
++			commit_info.needs_hdr = 1;
++			commit_info.mac_entry = NULL;
++			commit_info.p = _dhd_wlfc_deque_delayedq(ctx, ac,
++				&(commit_info.ac_fifo_credit_spent),
++				&(commit_info.needs_hdr),
++				&(commit_info.mac_entry),
++				no_credit);
++			commit_info.pkt_type = (commit_info.needs_hdr) ? eWLFC_PKTTYPE_DELAYED :
++				eWLFC_PKTTYPE_SUPPRESSED;
++
++			if (commit_info.p == NULL) {
++#ifdef LIMIT_BORROW
++				if (lender != -1 && dhdp->wlfc_borrow_allowed) {
++					_dhd_wlfc_return_credit(ctx, lender, ac);
++				}
++#endif
++				break;
++			}
++
++			if (!dhdp->proptxstatus_credit_ignore && (lender == -1)) {
++				ASSERT(ctx->FIFO_credit[ac] >= commit_info.ac_fifo_credit_spent);
++			}
++			/* here we can ensure have credit or no credit needed */
++			rc = _dhd_wlfc_handle_packet_commit(ctx, ac, &commit_info,
++				ctx->fcommit, ctx->commit_ctx);
++
++			/* Bus commits may fail (e.g. flow control); abort after retries */
++			if (rc == BCME_OK) {
++				pkt_send++;
++				pkt_send_per_ac++;
++				if (commit_info.ac_fifo_credit_spent && (lender == -1)) {
++					ctx->FIFO_credit[ac]--;
++				}
++#ifdef LIMIT_BORROW
++				else if (!commit_info.ac_fifo_credit_spent && (lender != -1) &&
++					dhdp->wlfc_borrow_allowed) {
++					_dhd_wlfc_return_credit(ctx, lender, ac);
++				}
++#endif
++			} else {
++#ifdef LIMIT_BORROW
++				if (lender != -1 && dhdp->wlfc_borrow_allowed) {
++					_dhd_wlfc_return_credit(ctx, lender, ac);
++				}
++#endif
++				bus_retry_count++;
++				if (bus_retry_count >= BUS_RETRIES) {
++					DHD_ERROR(("%s: bus error %d\n", __FUNCTION__, rc));
++					goto exit;
++				}
++			}
++		}
++
++		if (ctx->pkt_cnt_per_ac[ac]) {
++			packets_map |= (1 << ac);
++		}
++	}
++
++	if ((tx_map == 0) || dhdp->proptxstatus_credit_ignore) {
++		/* nothing send out or remain in queue */
++		rc = BCME_OK;
++		goto exit;
++	}
++
++	if (((tx_map & (tx_map - 1)) == 0) && (tx_map >= rx_map)) {
++		/* only one tx ac exist and no higher rx ac */
++		if ((single_ac == ctx->single_ac) && ctx->allow_credit_borrow) {
++			ac = single_ac - 1;
++		} else {
++			uint32 delta;
++			uint32 curr_t = OSL_SYSUPTIME();
++
++			if (single_ac != ctx->single_ac) {
++				/* new single ac traffic (first single ac or different single ac) */
++				ctx->allow_credit_borrow = 0;
++				ctx->single_ac_timestamp = curr_t;
++				ctx->single_ac = (uint8)single_ac;
++				rc = BCME_OK;
++				goto exit;
++			}
++			/* same ac traffic, check if it lasts enough time */
++			delta = curr_t - ctx->single_ac_timestamp;
++
++			if (delta >= WLFC_BORROW_DEFER_PERIOD_MS) {
++				/* wait enough time, can borrow now */
++				ctx->allow_credit_borrow = 1;
++				ac = single_ac - 1;
++			} else {
++				rc = BCME_OK;
++				goto exit;
++			}
++		}
++	} else {
++		/* If we have multiple AC traffic, turn off borrowing, mark time and bail out */
++		ctx->allow_credit_borrow = 0;
++		ctx->single_ac_timestamp = 0;
++		ctx->single_ac = 0;
++		rc = BCME_OK;
++		goto exit;
++	}
++
++	if (packets_map == 0) {
++		/* nothing to send, skip borrow */
++		rc = BCME_OK;
++		goto exit;
++	}
++
++	/* At this point, borrow all credits only for ac */
++	while (FALSE == dhdp->proptxstatus_txoff) {
++#ifdef LIMIT_BORROW
++		if (dhdp->wlfc_borrow_allowed) {
++			if ((lender = _dhd_wlfc_borrow_credit(ctx, AC_COUNT, ac, TRUE)) == -1) {
++				break;
++			}
++		}
++		else
++			break;
++#endif
++		commit_info.p = _dhd_wlfc_deque_delayedq(ctx, ac,
++			&(commit_info.ac_fifo_credit_spent),
++			&(commit_info.needs_hdr),
++			&(commit_info.mac_entry),
++			FALSE);
++		if (commit_info.p == NULL) {
++			/* before borrow only one ac exists and now this only ac is empty */
++#ifdef LIMIT_BORROW
++			_dhd_wlfc_return_credit(ctx, lender, ac);
++#endif
++			break;
++		}
++
++		commit_info.pkt_type = (commit_info.needs_hdr) ? eWLFC_PKTTYPE_DELAYED :
++			eWLFC_PKTTYPE_SUPPRESSED;
++
++		rc = _dhd_wlfc_handle_packet_commit(ctx, ac, &commit_info,
++		     ctx->fcommit, ctx->commit_ctx);
++
++		/* Bus commits may fail (e.g. flow control); abort after retries */
++		if (rc == BCME_OK) {
++			pkt_send++;
++			if (commit_info.ac_fifo_credit_spent) {
++#ifndef LIMIT_BORROW
++				ctx->FIFO_credit[ac]--;
++#endif
++			} else {
++#ifdef LIMIT_BORROW
++				_dhd_wlfc_return_credit(ctx, lender, ac);
++#endif
++			}
++		} else {
++#ifdef LIMIT_BORROW
++			_dhd_wlfc_return_credit(ctx, lender, ac);
++#endif
++			bus_retry_count++;
++			if (bus_retry_count >= BUS_RETRIES) {
++				DHD_ERROR(("%s: bus error %d\n", __FUNCTION__, rc));
++				goto exit;
++			}
++		}
++	}
++
++	BCM_REFERENCE(pkt_send);
++
++exit:
++#if defined(DHD_WLFC_THREAD)
++		dhd_os_wlfc_unblock(dhdp);
++		if (ctx && ctx->pkt_cnt_in_psq && pkt_send) {
++			wait_msec = msecs_to_jiffies(WLFC_THREAD_QUICK_RETRY_WAIT_MS);
++		} else {
++			wait_msec = msecs_to_jiffies(WLFC_THREAD_RETRY_WAIT_MS);
++		}
++	}
++	return 0;
++#else
++	return rc;
++#endif /* defined(DHD_WLFC_THREAD) */
++}
++
++/**
++ * Enqueues a transmit packet in the next layer towards the dongle, eg the DBUS layer. Called by
++ * eg dhd_sendpkt().
++ *     @param[in] dhdp                  Pointer to public DHD structure
++ *     @param[in] fcommit               Pointer to transmit function of next layer
++ *     @param[in] commit_ctx            Opaque context used when calling next layer
++ *     @param[in] pktbuf                Packet to send
++ *     @param[in] need_toggle_host_if   If TRUE, resets flag ctx->toggle_host_if
++ */
++int
++dhd_wlfc_commit_packets(dhd_pub_t *dhdp, f_commitpkt_t fcommit, void* commit_ctx, void *pktbuf,
++	bool need_toggle_host_if)
++{
++	int rc = BCME_OK;
++	athost_wl_status_info_t* ctx;
++
++#if defined(DHD_WLFC_THREAD)
++	if (!pktbuf)
++		return BCME_OK;
++#endif /* defined(DHD_WLFC_THREAD) */
++
++	if ((dhdp == NULL) || (fcommit == NULL)) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhdp);
++
++	if (!dhdp->wlfc_state || (dhdp->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		if (pktbuf) {
++			DHD_PKTTAG_WLFCPKT_SET(PKTTAG(pktbuf), 0);
++		}
++		rc =  WLFC_UNSUPPORTED;
++		goto exit;
++	}
++
++	ctx = (athost_wl_status_info_t*)dhdp->wlfc_state;
++
++#ifdef BCMDBUS
++	if (!dhdp->up || (dhdp->busstate == DHD_BUS_DOWN)) {
++		if (pktbuf) {
++			PKTFREE(ctx->osh, pktbuf, TRUE);
++			rc = BCME_OK;
++		}
++		goto exit;
++	}
++#endif /* BCMDBUS */
++
++	if (dhdp->proptxstatus_module_ignore) {
++		if (pktbuf) {
++			uint32 htod = 0;
++			WL_TXSTATUS_SET_FLAGS(htod, WLFC_PKTFLAG_PKTFROMHOST);
++			_dhd_wlfc_pushheader(ctx, &pktbuf, FALSE, 0, 0, htod, 0, FALSE);
++			if (fcommit(commit_ctx, pktbuf)) {
++				/* free it if failed, otherwise do it in tx complete cb */
++				PKTFREE(ctx->osh, pktbuf, TRUE);
++			}
++			rc = BCME_OK;
++		}
++		goto exit;
++	}
++
++	if (pktbuf) {
++		int ac = DHD_PKTTAG_FIFO(PKTTAG(pktbuf));
++		ASSERT(ac <= AC_COUNT);
++		DHD_PKTTAG_WLFCPKT_SET(PKTTAG(pktbuf), 1);
++		/* en-queue the packets to respective queue. */
++		rc = _dhd_wlfc_enque_delayq(ctx, pktbuf, ac);
++		if (rc) {
++			_dhd_wlfc_prec_drop(ctx->dhdp, (ac << 1), pktbuf, FALSE);
++		} else {
++			ctx->stats.pktin++;
++			ctx->pkt_cnt_in_drv[DHD_PKTTAG_IF(PKTTAG(pktbuf))][ac]++;
++		}
++	}
++
++	if (!ctx->fcommit) {
++		ctx->fcommit = fcommit;
++	} else {
++		ASSERT(ctx->fcommit == fcommit);
++	}
++	if (!ctx->commit_ctx) {
++		ctx->commit_ctx = commit_ctx;
++	} else {
++		ASSERT(ctx->commit_ctx == commit_ctx);
++	}
++
++#if defined(DHD_WLFC_THREAD)
++	_dhd_wlfc_thread_wakeup(dhdp);
++#else
++	dhd_wlfc_transfer_packets(dhdp);
++#endif /* defined(DHD_WLFC_THREAD) */
++
++exit:
++	dhd_os_wlfc_unblock(dhdp);
++	return rc;
++} /* dhd_wlfc_commit_packets */
++
++/**
++ * Called when the (lower) DBUS layer indicates completion (succesfull or not) of a transmit packet
++ */
++int
++dhd_wlfc_txcomplete(dhd_pub_t *dhd, void *txp, bool success)
++{
++	athost_wl_status_info_t* wlfc;
++	wlfc_mac_descriptor_t *entry;
++	void* pout = NULL;
++	int rtn = BCME_OK;
++	if ((dhd == NULL) || (txp == NULL)) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	bcm_pkt_validate_chk(txp);
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		rtn = WLFC_UNSUPPORTED;
++		goto EXIT;
++	}
++
++	wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	if (DHD_PKTTAG_SIGNALONLY(PKTTAG(txp))) {
++#ifdef PROP_TXSTATUS_DEBUG
++		wlfc->stats.signal_only_pkts_freed++;
++#endif
++		/* is this a signal-only packet? */
++		_dhd_wlfc_pullheader(wlfc, txp);
++		PKTFREE(wlfc->osh, txp, TRUE);
++		goto EXIT;
++	}
++
++	entry = _dhd_wlfc_find_table_entry(wlfc, txp);
++	ASSERT(entry);
++
++	if (!success || dhd->proptxstatus_txstatus_ignore) {
++		WLFC_DBGMESG(("At: %s():%d, bus_complete() failure for %p, htod_tag:0x%08x\n",
++			__FUNCTION__, __LINE__, txp, DHD_PKTTAG_H2DTAG(PKTTAG(txp))));
++		if (!WLFC_GET_AFQ(dhd->wlfc_mode)) {
++			_dhd_wlfc_hanger_poppkt(wlfc->hanger, WL_TXSTATUS_GET_HSLOT(
++				DHD_PKTTAG_H2DTAG(PKTTAG(txp))), &pout, TRUE);
++			ASSERT(txp == pout);
++		}
++
++		/* indicate failure and free the packet */
++		dhd_txcomplete(dhd, txp, success);
++
++		/* return the credit, if necessary */
++		_dhd_wlfc_return_implied_credit(wlfc, txp);
++
++		if (entry->transit_count)
++			entry->transit_count--;
++		if (entry->suppr_transit_count)
++			entry->suppr_transit_count--;
++		wlfc->pkt_cnt_in_drv[DHD_PKTTAG_IF(PKTTAG(txp))][DHD_PKTTAG_FIFO(PKTTAG(txp))]--;
++		wlfc->stats.pktout++;
++		PKTFREE(wlfc->osh, txp, TRUE);
++	} else {
++		/* bus confirmed pkt went to firmware side */
++		if (WLFC_GET_AFQ(dhd->wlfc_mode)) {
++			_dhd_wlfc_enque_afq(wlfc, txp);
++		} else {
++			int hslot = WL_TXSTATUS_GET_HSLOT(DHD_PKTTAG_H2DTAG(PKTTAG(txp)));
++			_dhd_wlfc_hanger_free_pkt(wlfc, hslot,
++				WLFC_HANGER_PKT_STATE_BUSRETURNED, -1);
++		}
++	}
++
++	ASSERT(entry->onbus_pkts_count > 0);
++	if (entry->onbus_pkts_count > 0)
++		entry->onbus_pkts_count--;
++	if (entry->suppressed &&
++		(!entry->onbus_pkts_count) &&
++		(!entry->suppr_transit_count))
++		entry->suppressed = FALSE;
++EXIT:
++	dhd_os_wlfc_unblock(dhd);
++	return rtn;
++} /* dhd_wlfc_txcomplete */
++
++int
++dhd_wlfc_init(dhd_pub_t *dhd)
++{
++	/* enable all signals & indicate host proptxstatus logic is active */
++	uint32 tlv, mode, fw_caps;
++	int ret = 0;
++
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++	if (dhd->wlfc_enabled) {
++		DHD_ERROR(("%s():%d, Already enabled!\n", __FUNCTION__, __LINE__));
++		dhd_os_wlfc_unblock(dhd);
++		return BCME_OK;
++	}
++	dhd->wlfc_enabled = TRUE;
++	dhd_os_wlfc_unblock(dhd);
++
++	tlv = WLFC_FLAGS_RSSI_SIGNALS |
++		WLFC_FLAGS_XONXOFF_SIGNALS |
++		WLFC_FLAGS_CREDIT_STATUS_SIGNALS |
++		WLFC_FLAGS_HOST_PROPTXSTATUS_ACTIVE |
++		WLFC_FLAGS_HOST_RXRERODER_ACTIVE;
++
++
++	/*
++	try to enable/disable signaling by sending "tlv" iovar. if that fails,
++	fallback to no flow control? Print a message for now.
++	*/
++
++	/* enable proptxtstatus signaling by default */
++	if (!dhd_wl_ioctl_set_intiovar(dhd, "tlv", tlv, WLC_SET_VAR, TRUE, 0)) {
++		/*
++		Leaving the message for now, it should be removed after a while; once
++		the tlv situation is stable.
++		*/
++		DHD_ERROR(("dhd_wlfc_init(): successfully %s bdcv2 tlv signaling, %d\n",
++			dhd->wlfc_enabled?"enabled":"disabled", tlv));
++	}
++
++	mode = 0;
++
++	/* query caps */
++	ret = dhd_wl_ioctl_get_intiovar(dhd, "wlfc_mode", &fw_caps, WLC_GET_VAR, FALSE, 0);
++
++	if (!ret) {
++		DHD_ERROR(("%s: query wlfc_mode succeed, fw_caps=0x%x\n", __FUNCTION__, fw_caps));
++
++		if (WLFC_IS_OLD_DEF(fw_caps)) {
++#ifdef BCMDBUS
++			mode = WLFC_MODE_HANGER;
++#else
++			/* enable proptxtstatus v2 by default */
++			mode = WLFC_MODE_AFQ;
++#endif /* BCMDBUS */
++		} else {
++			WLFC_SET_AFQ(mode, WLFC_GET_AFQ(fw_caps));
++#ifdef BCMDBUS
++			WLFC_SET_AFQ(mode, 0);
++#endif /* BCMDBUS */
++			WLFC_SET_REUSESEQ(mode, WLFC_GET_REUSESEQ(fw_caps));
++			WLFC_SET_REORDERSUPP(mode, WLFC_GET_REORDERSUPP(fw_caps));
++		}
++		ret = dhd_wl_ioctl_set_intiovar(dhd, "wlfc_mode", mode, WLC_SET_VAR, TRUE, 0);
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	dhd->wlfc_mode = 0;
++	if (ret >= 0) {
++		if (WLFC_IS_OLD_DEF(mode)) {
++			WLFC_SET_AFQ(dhd->wlfc_mode, (mode == WLFC_MODE_AFQ));
++		} else {
++			dhd->wlfc_mode = mode;
++		}
++	}
++
++	DHD_ERROR(("dhd_wlfc_init(): wlfc_mode=0x%x, ret=%d\n", dhd->wlfc_mode, ret));
++#ifdef LIMIT_BORROW
++	dhd->wlfc_borrow_allowed = TRUE;
++#endif
++	dhd_os_wlfc_unblock(dhd);
++
++	if (dhd->plat_init)
++		dhd->plat_init((void *)dhd);
++
++	return BCME_OK;
++} /* dhd_wlfc_init */
++
++/** AMPDU host reorder specific function */
++int
++dhd_wlfc_hostreorder_init(dhd_pub_t *dhd)
++{
++	/* enable only ampdu hostreorder here */
++	uint32 tlv;
++
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	DHD_TRACE(("%s():%d Enter\n", __FUNCTION__, __LINE__));
++
++	tlv = WLFC_FLAGS_HOST_RXRERODER_ACTIVE;
++
++	/* enable proptxtstatus signaling by default */
++	if (dhd_wl_ioctl_set_intiovar(dhd, "tlv", tlv, WLC_SET_VAR, TRUE, 0)) {
++		DHD_ERROR(("%s(): failed to enable/disable bdcv2 tlv signaling\n",
++			__FUNCTION__));
++	} else {
++		/*
++		Leaving the message for now, it should be removed after a while; once
++		the tlv situation is stable.
++		*/
++		DHD_ERROR(("%s(): successful bdcv2 tlv signaling, %d\n",
++			__FUNCTION__, tlv));
++	}
++
++	dhd_os_wlfc_block(dhd);
++	dhd->proptxstatus_mode = WLFC_ONLY_AMPDU_HOSTREORDER;
++	dhd_os_wlfc_unblock(dhd);
++	/* terence 20161229: enable ampdu_hostreorder if tlv enable hostreorder */
++	dhd_conf_set_intiovar(dhd, WLC_SET_VAR, "ampdu_hostreorder", 1, 0, TRUE);
++
++	return BCME_OK;
++}
++
++int
++dhd_wlfc_cleanup_txq(dhd_pub_t *dhd, f_processpkt_t fn, void *arg)
++{
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhd);
++		return WLFC_UNSUPPORTED;
++	}
++
++#ifndef BCMDBUS
++	_dhd_wlfc_cleanup_txq(dhd, fn, arg);
++#endif /* !BCMDBUS */
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** release all packet resources */
++int
++dhd_wlfc_cleanup(dhd_pub_t *dhd, f_processpkt_t fn, void *arg)
++{
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhd);
++		return WLFC_UNSUPPORTED;
++	}
++
++	_dhd_wlfc_cleanup(dhd, fn, arg);
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++int
++dhd_wlfc_deinit(dhd_pub_t *dhd)
++{
++	/* cleanup all psq related resources */
++	athost_wl_status_info_t* wlfc;
++	uint32 tlv = 0;
++	uint32 hostreorder = 0;
++
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++	if (!dhd->wlfc_enabled) {
++		DHD_ERROR(("%s():%d, Already disabled!\n", __FUNCTION__, __LINE__));
++		dhd_os_wlfc_unblock(dhd);
++		return BCME_OK;
++	}
++
++	dhd->wlfc_enabled = FALSE;
++	dhd_os_wlfc_unblock(dhd);
++
++	/* query ampdu hostreorder */
++	(void) dhd_wl_ioctl_get_intiovar(dhd, "ampdu_hostreorder",
++		&hostreorder, WLC_GET_VAR, FALSE, 0);
++
++	if (hostreorder) {
++		tlv = WLFC_FLAGS_HOST_RXRERODER_ACTIVE;
++		DHD_ERROR(("%s():%d, maintain HOST RXRERODER flag in tvl\n",
++			__FUNCTION__, __LINE__));
++	}
++
++	/* Disable proptxtstatus signaling for deinit */
++	(void) dhd_wl_ioctl_set_intiovar(dhd, "tlv", tlv, WLC_SET_VAR, TRUE, 0);
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhd);
++		return WLFC_UNSUPPORTED;
++	}
++
++	wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++
++	_dhd_wlfc_cleanup(dhd, NULL, NULL);
++
++	if (!WLFC_GET_AFQ(dhd->wlfc_mode)) {
++		int i;
++		wlfc_hanger_t* h = (wlfc_hanger_t*)wlfc->hanger;
++		for (i = 0; i < h->max_items; i++) {
++			if (h->items[i].state != WLFC_HANGER_ITEM_STATE_FREE) {
++				_dhd_wlfc_hanger_free_pkt(wlfc, i,
++					WLFC_HANGER_PKT_STATE_COMPLETE, TRUE);
++			}
++		}
++
++		/* delete hanger */
++		_dhd_wlfc_hanger_delete(dhd, h);
++	}
++
++
++	/* free top structure */
++	DHD_OS_PREFREE(dhd, dhd->wlfc_state,
++		sizeof(athost_wl_status_info_t));
++	dhd->wlfc_state = NULL;
++	dhd->proptxstatus_mode = hostreorder ?
++		WLFC_ONLY_AMPDU_HOSTREORDER : WLFC_FCMODE_NONE;
++
++	DHD_ERROR(("%s: wlfc_mode=0x%x, tlv=%d\n", __FUNCTION__, dhd->wlfc_mode, tlv));
++
++	dhd_os_wlfc_unblock(dhd);
++
++	if (dhd->plat_deinit)
++		dhd->plat_deinit((void *)dhd);
++	return BCME_OK;
++} /* dhd_wlfc_init */
++
++/**
++ * Called on an interface event (WLC_E_IF) indicated by firmware
++ *     @param[in] dhdp   Pointer to public DHD structure
++ *     @param[in] action eg eWLFC_MAC_ENTRY_ACTION_UPDATE or eWLFC_MAC_ENTRY_ACTION_ADD
++ */
++int dhd_wlfc_interface_event(dhd_pub_t *dhdp, uint8 action, uint8 ifid, uint8 iftype, uint8* ea)
++{
++	int rc;
++
++	if (dhdp == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhdp);
++
++	if (!dhdp->wlfc_state || (dhdp->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhdp);
++		return WLFC_UNSUPPORTED;
++	}
++
++	rc = _dhd_wlfc_interface_entry_update(dhdp->wlfc_state, action, ifid, iftype, ea);
++
++	dhd_os_wlfc_unblock(dhdp);
++	return rc;
++}
++
++/** Called eg on receiving a WLC_E_FIFO_CREDIT_MAP event from the dongle */
++int dhd_wlfc_FIFOcreditmap_event(dhd_pub_t *dhdp, uint8* event_data)
++{
++	int rc;
++
++	if (dhdp == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhdp);
++
++	if (!dhdp->wlfc_state || (dhdp->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhdp);
++		return WLFC_UNSUPPORTED;
++	}
++
++	rc = _dhd_wlfc_FIFOcreditmap_update(dhdp->wlfc_state, event_data);
++
++	dhd_os_wlfc_unblock(dhdp);
++
++	return rc;
++}
++#ifdef LIMIT_BORROW
++int dhd_wlfc_disable_credit_borrow_event(dhd_pub_t *dhdp, uint8* event_data)
++{
++	if (dhdp == NULL || event_data == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++	dhd_os_wlfc_block(dhdp);
++	dhdp->wlfc_borrow_allowed = (bool)(*(uint32 *)event_data);
++	dhd_os_wlfc_unblock(dhdp);
++
++	return BCME_OK;
++}
++#endif /* LIMIT_BORROW */
++
++/**
++ * Called eg on receiving a WLC_E_BCMC_CREDIT_SUPPORT event from the dongle (broadcast/multicast
++ * specific)
++ */
++int dhd_wlfc_BCMCCredit_support_event(dhd_pub_t *dhdp)
++{
++	int rc;
++
++	if (dhdp == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhdp);
++
++	if (!dhdp->wlfc_state || (dhdp->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhdp);
++		return WLFC_UNSUPPORTED;
++	}
++
++	rc = _dhd_wlfc_BCMCCredit_support_update(dhdp->wlfc_state);
++
++	dhd_os_wlfc_unblock(dhdp);
++	return rc;
++}
++
++/** debug specific function */
++int
++dhd_wlfc_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
++{
++	int i;
++	uint8* ea;
++	athost_wl_status_info_t* wlfc;
++	wlfc_hanger_t* h;
++	wlfc_mac_descriptor_t* mac_table;
++	wlfc_mac_descriptor_t* interfaces;
++	char* iftypes[] = {"STA", "AP", "WDS", "p2pGO", "p2pCL"};
++
++	if (!dhdp || !strbuf) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhdp);
++
++	if (!dhdp->wlfc_state || (dhdp->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhdp);
++		return WLFC_UNSUPPORTED;
++	}
++
++	wlfc = (athost_wl_status_info_t*)dhdp->wlfc_state;
++
++	h = (wlfc_hanger_t*)wlfc->hanger;
++	if (h == NULL) {
++		bcm_bprintf(strbuf, "wlfc-hanger not initialized yet\n");
++	}
++
++	mac_table = wlfc->destination_entries.nodes;
++	interfaces = wlfc->destination_entries.interfaces;
++	bcm_bprintf(strbuf, "---- wlfc stats ----\n");
++
++	if (!WLFC_GET_AFQ(dhdp->wlfc_mode)) {
++		h = (wlfc_hanger_t*)wlfc->hanger;
++		if (h == NULL) {
++			bcm_bprintf(strbuf, "wlfc-hanger not initialized yet\n");
++		} else {
++			bcm_bprintf(strbuf, "wlfc hanger (pushed,popped,f_push,"
++				"f_pop,f_slot, pending) = (%d,%d,%d,%d,%d,%d)\n",
++				h->pushed,
++				h->popped,
++				h->failed_to_push,
++				h->failed_to_pop,
++				h->failed_slotfind,
++				(h->pushed - h->popped));
++		}
++	}
++
++	bcm_bprintf(strbuf, "wlfc fail(tlv,credit_rqst,mac_update,psmode_update), "
++		"(dq_full,rollback_fail) = (%d,%d,%d,%d), (%d,%d)\n",
++		wlfc->stats.tlv_parse_failed,
++		wlfc->stats.credit_request_failed,
++		wlfc->stats.mac_update_failed,
++		wlfc->stats.psmode_update_failed,
++		wlfc->stats.delayq_full_error,
++		wlfc->stats.rollback_failed);
++
++	bcm_bprintf(strbuf, "PKTS (init_credit,credit,sent,drop_d,drop_s,outoforder) "
++		"(AC0[%d,%d,%d,%d,%d,%d],AC1[%d,%d,%d,%d,%d,%d],AC2[%d,%d,%d,%d,%d,%d],"
++		"AC3[%d,%d,%d,%d,%d,%d],BC_MC[%d,%d,%d,%d,%d,%d])\n",
++		wlfc->Init_FIFO_credit[0], wlfc->FIFO_credit[0], wlfc->stats.send_pkts[0],
++		wlfc->stats.drop_pkts[0], wlfc->stats.drop_pkts[1], wlfc->stats.ooo_pkts[0],
++		wlfc->Init_FIFO_credit[1], wlfc->FIFO_credit[1], wlfc->stats.send_pkts[1],
++		wlfc->stats.drop_pkts[2], wlfc->stats.drop_pkts[3], wlfc->stats.ooo_pkts[1],
++		wlfc->Init_FIFO_credit[2], wlfc->FIFO_credit[2], wlfc->stats.send_pkts[2],
++		wlfc->stats.drop_pkts[4], wlfc->stats.drop_pkts[5], wlfc->stats.ooo_pkts[2],
++		wlfc->Init_FIFO_credit[3], wlfc->FIFO_credit[3], wlfc->stats.send_pkts[3],
++		wlfc->stats.drop_pkts[6], wlfc->stats.drop_pkts[7], wlfc->stats.ooo_pkts[3],
++		wlfc->Init_FIFO_credit[4], wlfc->FIFO_credit[4], wlfc->stats.send_pkts[4],
++		wlfc->stats.drop_pkts[8], wlfc->stats.drop_pkts[9], wlfc->stats.ooo_pkts[4]);
++
++	bcm_bprintf(strbuf, "\n");
++	for (i = 0; i < WLFC_MAX_IFNUM; i++) {
++		if (interfaces[i].occupied) {
++			char* iftype_desc;
++
++			if (interfaces[i].iftype > WLC_E_IF_ROLE_P2P_CLIENT)
++				iftype_desc = "<Unknown";
++			else
++				iftype_desc = iftypes[interfaces[i].iftype];
++
++			ea = interfaces[i].ea;
++			bcm_bprintf(strbuf, "INTERFACE[%d].ea = "
++				"[%02x:%02x:%02x:%02x:%02x:%02x], if:%d, type: %s "
++				"netif_flow_control:%s\n", i,
++				ea[0], ea[1], ea[2], ea[3], ea[4], ea[5],
++				interfaces[i].interface_id,
++				iftype_desc, ((wlfc->hostif_flow_state[i] == OFF)
++				? " OFF":" ON"));
++
++			bcm_bprintf(strbuf, "INTERFACE[%d].PSQ(len,state,credit),"
++				"(trans,supp_trans,onbus)"
++				"= (%d,%s,%d),(%d,%d,%d)\n",
++				i,
++				interfaces[i].psq.len,
++				((interfaces[i].state ==
++				WLFC_STATE_OPEN) ? "OPEN":"CLOSE"),
++				interfaces[i].requested_credit,
++				interfaces[i].transit_count,
++				interfaces[i].suppr_transit_count,
++				interfaces[i].onbus_pkts_count);
++
++			bcm_bprintf(strbuf, "INTERFACE[%d].PSQ"
++				"(delay0,sup0,afq0),(delay1,sup1,afq1),(delay2,sup2,afq2),"
++				"(delay3,sup3,afq3),(delay4,sup4,afq4) = (%d,%d,%d),"
++				"(%d,%d,%d),(%d,%d,%d),(%d,%d,%d),(%d,%d,%d)\n",
++				i,
++				interfaces[i].psq.q[0].len,
++				interfaces[i].psq.q[1].len,
++				interfaces[i].afq.q[0].len,
++				interfaces[i].psq.q[2].len,
++				interfaces[i].psq.q[3].len,
++				interfaces[i].afq.q[1].len,
++				interfaces[i].psq.q[4].len,
++				interfaces[i].psq.q[5].len,
++				interfaces[i].afq.q[2].len,
++				interfaces[i].psq.q[6].len,
++				interfaces[i].psq.q[7].len,
++				interfaces[i].afq.q[3].len,
++				interfaces[i].psq.q[8].len,
++				interfaces[i].psq.q[9].len,
++				interfaces[i].afq.q[4].len);
++		}
++	}
++
++	bcm_bprintf(strbuf, "\n");
++	for (i = 0; i < WLFC_MAC_DESC_TABLE_SIZE; i++) {
++		if (mac_table[i].occupied) {
++			ea = mac_table[i].ea;
++			bcm_bprintf(strbuf, "MAC_table[%d].ea = "
++				"[%02x:%02x:%02x:%02x:%02x:%02x], if:%d \n", i,
++				ea[0], ea[1], ea[2], ea[3], ea[4], ea[5],
++				mac_table[i].interface_id);
++
++			bcm_bprintf(strbuf, "MAC_table[%d].PSQ(len,state,credit),"
++				"(trans,supp_trans,onbus)"
++				"= (%d,%s,%d),(%d,%d,%d)\n",
++				i,
++				mac_table[i].psq.len,
++				((mac_table[i].state ==
++				WLFC_STATE_OPEN) ? " OPEN":"CLOSE"),
++				mac_table[i].requested_credit,
++				mac_table[i].transit_count,
++				mac_table[i].suppr_transit_count,
++				mac_table[i].onbus_pkts_count);
++#ifdef PROP_TXSTATUS_DEBUG
++			bcm_bprintf(strbuf, "MAC_table[%d]: (opened, closed) = (%d, %d)\n",
++				i, mac_table[i].opened_ct, mac_table[i].closed_ct);
++#endif
++			bcm_bprintf(strbuf, "MAC_table[%d].PSQ"
++				"(delay0,sup0,afq0),(delay1,sup1,afq1),(delay2,sup2,afq2),"
++				"(delay3,sup3,afq3),(delay4,sup4,afq4) =(%d,%d,%d),"
++				"(%d,%d,%d),(%d,%d,%d),(%d,%d,%d),(%d,%d,%d)\n",
++				i,
++				mac_table[i].psq.q[0].len,
++				mac_table[i].psq.q[1].len,
++				mac_table[i].afq.q[0].len,
++				mac_table[i].psq.q[2].len,
++				mac_table[i].psq.q[3].len,
++				mac_table[i].afq.q[1].len,
++				mac_table[i].psq.q[4].len,
++				mac_table[i].psq.q[5].len,
++				mac_table[i].afq.q[2].len,
++				mac_table[i].psq.q[6].len,
++				mac_table[i].psq.q[7].len,
++				mac_table[i].afq.q[3].len,
++				mac_table[i].psq.q[8].len,
++				mac_table[i].psq.q[9].len,
++				mac_table[i].afq.q[4].len);
++
++		}
++	}
++
++#ifdef PROP_TXSTATUS_DEBUG
++	{
++		int avg;
++		int moving_avg = 0;
++		int moving_samples;
++
++		if (wlfc->stats.latency_sample_count) {
++			moving_samples = sizeof(wlfc->stats.deltas)/sizeof(uint32);
++
++			for (i = 0; i < moving_samples; i++)
++				moving_avg += wlfc->stats.deltas[i];
++			moving_avg /= moving_samples;
++
++			avg = (100 * wlfc->stats.total_status_latency) /
++				wlfc->stats.latency_sample_count;
++			bcm_bprintf(strbuf, "txstatus latency (average, last, moving[%d]) = "
++				"(%d.%d, %03d, %03d)\n",
++				moving_samples, avg/100, (avg - (avg/100)*100),
++				wlfc->stats.latency_most_recent,
++				moving_avg);
++		}
++	}
++
++	bcm_bprintf(strbuf, "wlfc- fifo[0-5] credit stats: sent = (%d,%d,%d,%d,%d,%d), "
++		"back = (%d,%d,%d,%d,%d,%d)\n",
++		wlfc->stats.fifo_credits_sent[0],
++		wlfc->stats.fifo_credits_sent[1],
++		wlfc->stats.fifo_credits_sent[2],
++		wlfc->stats.fifo_credits_sent[3],
++		wlfc->stats.fifo_credits_sent[4],
++		wlfc->stats.fifo_credits_sent[5],
++
++		wlfc->stats.fifo_credits_back[0],
++		wlfc->stats.fifo_credits_back[1],
++		wlfc->stats.fifo_credits_back[2],
++		wlfc->stats.fifo_credits_back[3],
++		wlfc->stats.fifo_credits_back[4],
++		wlfc->stats.fifo_credits_back[5]);
++	{
++		uint32 fifo_cr_sent = 0;
++		uint32 fifo_cr_acked = 0;
++		uint32 request_cr_sent = 0;
++		uint32 request_cr_ack = 0;
++		uint32 bc_mc_cr_ack = 0;
++
++		for (i = 0; i < sizeof(wlfc->stats.fifo_credits_sent)/sizeof(uint32); i++) {
++			fifo_cr_sent += wlfc->stats.fifo_credits_sent[i];
++		}
++
++		for (i = 0; i < sizeof(wlfc->stats.fifo_credits_back)/sizeof(uint32); i++) {
++			fifo_cr_acked += wlfc->stats.fifo_credits_back[i];
++		}
++
++		for (i = 0; i < WLFC_MAC_DESC_TABLE_SIZE; i++) {
++			if (wlfc->destination_entries.nodes[i].occupied) {
++				request_cr_sent +=
++					wlfc->destination_entries.nodes[i].dstncredit_sent_packets;
++			}
++		}
++		for (i = 0; i < WLFC_MAX_IFNUM; i++) {
++			if (wlfc->destination_entries.interfaces[i].occupied) {
++				request_cr_sent +=
++				wlfc->destination_entries.interfaces[i].dstncredit_sent_packets;
++			}
++		}
++		for (i = 0; i < WLFC_MAC_DESC_TABLE_SIZE; i++) {
++			if (wlfc->destination_entries.nodes[i].occupied) {
++				request_cr_ack +=
++					wlfc->destination_entries.nodes[i].dstncredit_acks;
++			}
++		}
++		for (i = 0; i < WLFC_MAX_IFNUM; i++) {
++			if (wlfc->destination_entries.interfaces[i].occupied) {
++				request_cr_ack +=
++					wlfc->destination_entries.interfaces[i].dstncredit_acks;
++			}
++		}
++		bcm_bprintf(strbuf, "wlfc- (sent, status) => pq(%d,%d), vq(%d,%d),"
++			"other:%d, bc_mc:%d, signal-only, (sent,freed): (%d,%d)",
++			fifo_cr_sent, fifo_cr_acked,
++			request_cr_sent, request_cr_ack,
++			wlfc->destination_entries.other.dstncredit_acks,
++			bc_mc_cr_ack,
++			wlfc->stats.signal_only_pkts_sent, wlfc->stats.signal_only_pkts_freed);
++	}
++#endif /* PROP_TXSTATUS_DEBUG */
++	bcm_bprintf(strbuf, "\n");
++	bcm_bprintf(strbuf, "wlfc- pkt((in,2bus,txstats,hdrpull,out),(dropped,hdr_only,wlc_tossed)"
++		"(freed,free_err,rollback)) = "
++		"((%d,%d,%d,%d,%d),(%d,%d,%d),(%d,%d,%d))\n",
++		wlfc->stats.pktin,
++		wlfc->stats.pkt2bus,
++		wlfc->stats.txstatus_in,
++		wlfc->stats.dhd_hdrpulls,
++		wlfc->stats.pktout,
++
++		wlfc->stats.pktdropped,
++		wlfc->stats.wlfc_header_only_pkt,
++		wlfc->stats.wlc_tossed_pkts,
++
++		wlfc->stats.pkt_freed,
++		wlfc->stats.pkt_free_err, wlfc->stats.rollback);
++
++	bcm_bprintf(strbuf, "wlfc- suppress((d11,wlc,err),enq(d11,wl,hq,mac?),retx(d11,wlc,hq)) = "
++		"((%d,%d,%d),(%d,%d,%d,%d),(%d,%d,%d))\n",
++		wlfc->stats.d11_suppress,
++		wlfc->stats.wl_suppress,
++		wlfc->stats.bad_suppress,
++
++		wlfc->stats.psq_d11sup_enq,
++		wlfc->stats.psq_wlsup_enq,
++		wlfc->stats.psq_hostq_enq,
++		wlfc->stats.mac_handle_notfound,
++
++		wlfc->stats.psq_d11sup_retx,
++		wlfc->stats.psq_wlsup_retx,
++		wlfc->stats.psq_hostq_retx);
++
++	bcm_bprintf(strbuf, "wlfc- cleanup(txq,psq,fw) = (%d,%d,%d)\n",
++		wlfc->stats.cleanup_txq_cnt,
++		wlfc->stats.cleanup_psq_cnt,
++		wlfc->stats.cleanup_fw_cnt);
++
++	bcm_bprintf(strbuf, "wlfc- generic error: %d\n", wlfc->stats.generic_error);
++
++	for (i = 0; i < WLFC_MAX_IFNUM; i++) {
++		bcm_bprintf(strbuf, "wlfc- if[%d], pkt_cnt_in_q/AC[0-4] = (%d,%d,%d,%d,%d)\n", i,
++			wlfc->pkt_cnt_in_q[i][0],
++			wlfc->pkt_cnt_in_q[i][1],
++			wlfc->pkt_cnt_in_q[i][2],
++			wlfc->pkt_cnt_in_q[i][3],
++			wlfc->pkt_cnt_in_q[i][4]);
++	}
++	bcm_bprintf(strbuf, "\n");
++
++	dhd_os_wlfc_unblock(dhdp);
++	return BCME_OK;
++} /* dhd_wlfc_dump */
++
++int dhd_wlfc_clear_counts(dhd_pub_t *dhd)
++{
++	athost_wl_status_info_t* wlfc;
++	wlfc_hanger_t* hanger;
++
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhd);
++		return WLFC_UNSUPPORTED;
++	}
++
++	wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++
++	memset(&wlfc->stats, 0, sizeof(athost_wl_stat_counters_t));
++
++	if (!WLFC_GET_AFQ(dhd->wlfc_mode)) {
++		hanger = (wlfc_hanger_t*)wlfc->hanger;
++
++		hanger->pushed = 0;
++		hanger->popped = 0;
++		hanger->failed_slotfind = 0;
++		hanger->failed_to_pop = 0;
++		hanger->failed_to_push = 0;
++	}
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** returns TRUE if flow control is enabled */
++int dhd_wlfc_get_enable(dhd_pub_t *dhd, bool *val)
++{
++	if (!dhd || !val) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	*val = dhd->wlfc_enabled;
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** Called via an IOVAR */
++int dhd_wlfc_get_mode(dhd_pub_t *dhd, int *val)
++{
++	if (!dhd || !val) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	*val = dhd->wlfc_state ? dhd->proptxstatus_mode : 0;
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** Called via an IOVAR */
++int dhd_wlfc_set_mode(dhd_pub_t *dhd, int val)
++{
++	if (!dhd) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (dhd->wlfc_state) {
++		dhd->proptxstatus_mode = val & 0xff;
++	}
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** Called when rx frame is received from the dongle */
++bool dhd_wlfc_is_header_only_pkt(dhd_pub_t * dhd, void *pktbuf)
++{
++	athost_wl_status_info_t* wlfc;
++	bool rc = FALSE;
++
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return FALSE;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhd);
++		return FALSE;
++	}
++
++	wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++
++	if (PKTLEN(wlfc->osh, pktbuf) == 0) {
++		wlfc->stats.wlfc_header_only_pkt++;
++		rc = TRUE;
++	}
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return rc;
++}
++
++int dhd_wlfc_flowcontrol(dhd_pub_t *dhdp, bool state, bool bAcquireLock)
++{
++	if (dhdp == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	if (bAcquireLock) {
++		dhd_os_wlfc_block(dhdp);
++	}
++
++	if (!dhdp->wlfc_state || (dhdp->proptxstatus_mode == WLFC_FCMODE_NONE) ||
++		dhdp->proptxstatus_module_ignore) {
++		if (bAcquireLock) {
++			dhd_os_wlfc_unblock(dhdp);
++		}
++		return WLFC_UNSUPPORTED;
++	}
++
++	if (state != dhdp->proptxstatus_txoff) {
++		dhdp->proptxstatus_txoff = state;
++	}
++
++	if (bAcquireLock) {
++		dhd_os_wlfc_unblock(dhdp);
++	}
++
++	return BCME_OK;
++}
++
++/** Called when eg an rx frame is received from the dongle */
++int dhd_wlfc_save_rxpath_ac_time(dhd_pub_t * dhd, uint8 prio)
++{
++	athost_wl_status_info_t* wlfc;
++	int rx_path_ac = -1;
++
++	if ((dhd == NULL) || (prio >= NUMPRIO)) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_rxpkt_chk) {
++		dhd_os_wlfc_unblock(dhd);
++		return BCME_OK;
++	}
++
++	if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhd);
++		return WLFC_UNSUPPORTED;
++	}
++
++	wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++
++	rx_path_ac = prio2fifo[prio];
++	wlfc->rx_timestamp[rx_path_ac] = OSL_SYSUPTIME();
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** called via an IOVAR */
++int dhd_wlfc_get_module_ignore(dhd_pub_t *dhd, int *val)
++{
++	if (!dhd || !val) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	*val = dhd->proptxstatus_module_ignore;
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** called via an IOVAR */
++int dhd_wlfc_set_module_ignore(dhd_pub_t *dhd, int val)
++{
++	uint32 tlv = 0;
++	bool bChanged = FALSE;
++
++	if (!dhd) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if ((bool)val != dhd->proptxstatus_module_ignore) {
++		dhd->proptxstatus_module_ignore = (val != 0);
++		/* force txstatus_ignore sync with proptxstatus_module_ignore */
++		dhd->proptxstatus_txstatus_ignore = dhd->proptxstatus_module_ignore;
++		if (FALSE == dhd->proptxstatus_module_ignore) {
++			tlv = WLFC_FLAGS_RSSI_SIGNALS |
++				WLFC_FLAGS_XONXOFF_SIGNALS |
++				WLFC_FLAGS_CREDIT_STATUS_SIGNALS |
++				WLFC_FLAGS_HOST_PROPTXSTATUS_ACTIVE;
++		}
++		/* always enable host reorder */
++		tlv |= WLFC_FLAGS_HOST_RXRERODER_ACTIVE;
++		bChanged = TRUE;
++	}
++
++	dhd_os_wlfc_unblock(dhd);
++
++	if (bChanged) {
++		/* select enable proptxtstatus signaling */
++		if (dhd_wl_ioctl_set_intiovar(dhd, "tlv", tlv, WLC_SET_VAR, TRUE, 0)) {
++			DHD_ERROR(("%s: failed to set bdcv2 tlv signaling to 0x%x\n",
++				__FUNCTION__, tlv));
++		} else {
++			DHD_ERROR(("%s: successfully set bdcv2 tlv signaling to 0x%x\n",
++				__FUNCTION__, tlv));
++		}
++	}
++
++#if defined(DHD_WLFC_THREAD)
++	_dhd_wlfc_thread_wakeup(dhd);
++#endif /* defined(DHD_WLFC_THREAD) */
++
++	return BCME_OK;
++}
++
++/** called via an IOVAR */
++int dhd_wlfc_get_credit_ignore(dhd_pub_t *dhd, int *val)
++{
++	if (!dhd || !val) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	*val = dhd->proptxstatus_credit_ignore;
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** called via an IOVAR */
++int dhd_wlfc_set_credit_ignore(dhd_pub_t *dhd, int val)
++{
++	if (!dhd) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	dhd->proptxstatus_credit_ignore = (val != 0);
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** called via an IOVAR */
++int dhd_wlfc_get_txstatus_ignore(dhd_pub_t *dhd, int *val)
++{
++	if (!dhd || !val) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	*val = dhd->proptxstatus_txstatus_ignore;
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** called via an IOVAR */
++int dhd_wlfc_set_txstatus_ignore(dhd_pub_t *dhd, int val)
++{
++	if (!dhd) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	dhd->proptxstatus_txstatus_ignore = (val != 0);
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** called via an IOVAR */
++int dhd_wlfc_get_rxpkt_chk(dhd_pub_t *dhd, int *val)
++{
++	if (!dhd || !val) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	*val = dhd->wlfc_rxpkt_chk;
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** called via an IOVAR */
++int dhd_wlfc_set_rxpkt_chk(dhd_pub_t *dhd, int val)
++{
++	if (!dhd) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	dhd->wlfc_rxpkt_chk = (val != 0);
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++#endif /* PROP_TXSTATUS */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dhd_wlfc.h b/module_drivers/drivers/net/wireless/bcmdhd/dhd_wlfc.h
+new file mode 100644
+index 000000000..54c6b3b4b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dhd_wlfc.h
+@@ -0,0 +1,562 @@
++/*
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_wlfc.h 671530 2016-11-22 08:43:33Z $
++ *
++ */
++#ifndef __wlfc_host_driver_definitions_h__
++#define __wlfc_host_driver_definitions_h__
++
++
++/* #define OOO_DEBUG */
++
++#define KERNEL_THREAD_RETURN_TYPE int
++
++typedef int (*f_commitpkt_t)(void* ctx, void* p);
++typedef bool (*f_processpkt_t)(void* p, void* arg);
++
++#define WLFC_UNSUPPORTED -9999
++
++#define WLFC_NO_TRAFFIC	-1
++#define WLFC_MULTI_TRAFFIC 0
++
++#define BUS_RETRIES 1	/* # of retries before aborting a bus tx operation */
++
++/** 16 bits will provide an absolute max of 65536 slots */
++#define WLFC_HANGER_MAXITEMS 3072
++
++#define WLFC_HANGER_ITEM_STATE_FREE			1
++#define WLFC_HANGER_ITEM_STATE_INUSE			2
++#define WLFC_HANGER_ITEM_STATE_INUSE_SUPPRESSED		3
++#define WLFC_HANGER_ITEM_STATE_FLUSHED			4
++
++#define WLFC_HANGER_PKT_STATE_TXSTATUS			1
++#define WLFC_HANGER_PKT_STATE_BUSRETURNED		2
++#define WLFC_HANGER_PKT_STATE_COMPLETE			\
++	(WLFC_HANGER_PKT_STATE_TXSTATUS | WLFC_HANGER_PKT_STATE_BUSRETURNED)
++
++typedef enum {
++	Q_TYPE_PSQ, /**< Power Save Queue, contains both delayed and suppressed packets */
++	Q_TYPE_AFQ  /**< At Firmware Queue */
++} q_type_t;
++
++typedef enum ewlfc_packet_state {
++	eWLFC_PKTTYPE_NEW,        /**< unused in the code (Jan 2015) */
++	eWLFC_PKTTYPE_DELAYED,    /**< packet did not enter wlfc yet */
++	eWLFC_PKTTYPE_SUPPRESSED, /**< packet entered wlfc and was suppressed by the dongle */
++	eWLFC_PKTTYPE_MAX
++} ewlfc_packet_state_t;
++
++typedef enum ewlfc_mac_entry_action {
++	eWLFC_MAC_ENTRY_ACTION_ADD,
++	eWLFC_MAC_ENTRY_ACTION_DEL,
++	eWLFC_MAC_ENTRY_ACTION_UPDATE,
++	eWLFC_MAC_ENTRY_ACTION_MAX
++} ewlfc_mac_entry_action_t;
++
++typedef struct wlfc_hanger_item {
++	uint8	state;
++	uint8   gen;
++	uint8	pkt_state;     /**< bitmask containing eg WLFC_HANGER_PKT_STATE_TXCOMPLETE */
++	uint8	pkt_txstatus;
++	uint32	identifier;
++	void*	pkt;
++#ifdef PROP_TXSTATUS_DEBUG
++	uint32	push_time;
++#endif
++	struct wlfc_hanger_item *next;
++} wlfc_hanger_item_t;
++
++/** hanger contains packets that have been posted by the dhd to the dongle and are expected back */
++typedef struct wlfc_hanger {
++	int max_items;
++	uint32 pushed;
++	uint32 popped;
++	uint32 failed_to_push;
++	uint32 failed_to_pop;
++	uint32 failed_slotfind;
++	uint32 slot_pos;
++	wlfc_hanger_item_t items[1];
++} wlfc_hanger_t;
++
++#define WLFC_HANGER_SIZE(n)	((sizeof(wlfc_hanger_t) - \
++	sizeof(wlfc_hanger_item_t)) + ((n)*sizeof(wlfc_hanger_item_t)))
++
++#define WLFC_STATE_OPEN		1	/**< remote MAC is able to receive packets */
++#define WLFC_STATE_CLOSE	2	/**< remote MAC is in power save mode */
++
++#define WLFC_PSQ_PREC_COUNT		((AC_COUNT + 1) * 2) /**< 2 for each AC traffic and bc/mc */
++#define WLFC_AFQ_PREC_COUNT		(AC_COUNT + 1)
++
++#define WLFC_PSQ_LEN			(4096 * 8)
++
++#ifdef BCMDBUS
++#define WLFC_FLOWCONTROL_HIWATER	512
++#define WLFC_FLOWCONTROL_LOWATER	(WLFC_FLOWCONTROL_HIWATER / 4)
++#else
++#define WLFC_FLOWCONTROL_HIWATER	((4096 * 8) - 256)
++#define WLFC_FLOWCONTROL_LOWATER	256
++#endif
++
++#if (WLFC_FLOWCONTROL_HIWATER >= (WLFC_PSQ_LEN - 256))
++#undef WLFC_FLOWCONTROL_HIWATER
++#define WLFC_FLOWCONTROL_HIWATER	(WLFC_PSQ_LEN - 256)
++#undef WLFC_FLOWCONTROL_LOWATER
++#define WLFC_FLOWCONTROL_LOWATER	(WLFC_FLOWCONTROL_HIWATER / 4)
++#endif
++
++#define WLFC_LOG_BUF_SIZE		(1024*1024)
++
++/** Properties related to a remote MAC entity */
++typedef struct wlfc_mac_descriptor {
++	uint8 occupied;         /**< if 0, this descriptor is unused and thus can be (re)used */
++	uint8 interface_id;
++	uint8 iftype;           /**< eg WLC_E_IF_ROLE_STA */
++	uint8 state;            /**< eg WLFC_STATE_OPEN */
++	uint8 ac_bitmap;        /**< automatic power save delivery (APSD) */
++	uint8 requested_credit;
++	uint8 requested_packet; /**< unit: [number of packets] */
++	uint8 ea[ETHER_ADDR_LEN];
++
++	/** maintain (MAC,AC) based seq count for packets going to the device. As well as bc/mc. */
++	uint8 seq[AC_COUNT + 1];
++	uint8 generation;       /**< toggles between 0 and 1 */
++	struct pktq	psq;    /**< contains both 'delayed' and 'suppressed' packets */
++	/** packets at firmware queue */
++	struct pktq	afq;
++	/** The AC pending bitmap that was reported to the fw at last change */
++	uint8 traffic_lastreported_bmp;
++	/** The new AC pending bitmap */
++	uint8 traffic_pending_bmp;
++	/** 1= send on next opportunity */
++	uint8 send_tim_signal;
++	uint8 mac_handle;          /**< mac handles are assigned by the dongle */
++	/** Number of packets at dongle for this entry. */
++	int transit_count;
++	/** Number of suppression to wait before evict from delayQ */
++	int suppr_transit_count;
++	/** pkt sent to bus but no bus TX complete yet */
++	int onbus_pkts_count;
++	/** flag. TRUE when remote MAC is in suppressed state */
++	uint8 suppressed;
++
++
++#ifdef PROP_TXSTATUS_DEBUG
++	uint32 dstncredit_sent_packets;
++	uint32 dstncredit_acks;
++	uint32 opened_ct;
++	uint32 closed_ct;
++#endif
++	struct wlfc_mac_descriptor* prev;
++	struct wlfc_mac_descriptor* next;
++} wlfc_mac_descriptor_t;
++
++/** A 'commit' is the hand over of a packet from the host OS layer to the layer below (eg DBUS) */
++typedef struct dhd_wlfc_commit_info {
++	uint8					needs_hdr;
++	uint8					ac_fifo_credit_spent;
++	ewlfc_packet_state_t	pkt_type;
++	wlfc_mac_descriptor_t*	mac_entry;
++	void*					p;
++} dhd_wlfc_commit_info_t;
++
++#define WLFC_DECR_SEQCOUNT(entry, prec) do { if (entry->seq[(prec)] == 0) {\
++	entry->seq[prec] = 0xff; } else entry->seq[prec]--;} while (0)
++
++#define WLFC_INCR_SEQCOUNT(entry, prec) entry->seq[(prec)]++
++#define WLFC_SEQCOUNT(entry, prec) entry->seq[(prec)]
++
++typedef struct athost_wl_stat_counters {
++	uint32	pktin;
++	uint32	pktout;
++	uint32	pkt2bus;
++	uint32	pktdropped;
++	uint32	tlv_parse_failed;
++	uint32	rollback;
++	uint32	rollback_failed;
++	uint32	delayq_full_error;
++	uint32	credit_request_failed;
++	uint32	packet_request_failed;
++	uint32	mac_update_failed;
++	uint32	psmode_update_failed;
++	uint32	interface_update_failed;
++	uint32	wlfc_header_only_pkt;
++	uint32	txstatus_in;
++	uint32	d11_suppress;
++	uint32	wl_suppress;
++	uint32	bad_suppress;
++	uint32	pkt_freed;
++	uint32	pkt_free_err;
++	uint32	psq_wlsup_retx;
++	uint32	psq_wlsup_enq;
++	uint32	psq_d11sup_retx;
++	uint32	psq_d11sup_enq;
++	uint32	psq_hostq_retx;
++	uint32	psq_hostq_enq;
++	uint32	mac_handle_notfound;
++	uint32	wlc_tossed_pkts;
++	uint32	dhd_hdrpulls;
++	uint32	generic_error;
++	/* an extra one for bc/mc traffic */
++	uint32	send_pkts[AC_COUNT + 1];
++	uint32	drop_pkts[WLFC_PSQ_PREC_COUNT];
++	uint32	ooo_pkts[AC_COUNT + 1];
++#ifdef PROP_TXSTATUS_DEBUG
++	/** all pkt2bus -> txstatus latency accumulated */
++	uint32	latency_sample_count;
++	uint32	total_status_latency;
++	uint32	latency_most_recent;
++	int	idx_delta;
++	uint32	deltas[10];
++	uint32	fifo_credits_sent[6];
++	uint32	fifo_credits_back[6];
++	uint32	dropped_qfull[6];
++	uint32	signal_only_pkts_sent;
++	uint32	signal_only_pkts_freed;
++#endif
++	uint32	cleanup_txq_cnt;
++	uint32	cleanup_psq_cnt;
++	uint32	cleanup_fw_cnt;
++} athost_wl_stat_counters_t;
++
++#ifdef PROP_TXSTATUS_DEBUG
++#define WLFC_HOST_FIFO_CREDIT_INC_SENTCTRS(ctx, ac) do { \
++	(ctx)->stats.fifo_credits_sent[(ac)]++;} while (0)
++#define WLFC_HOST_FIFO_CREDIT_INC_BACKCTRS(ctx, ac) do { \
++	(ctx)->stats.fifo_credits_back[(ac)]++;} while (0)
++#define WLFC_HOST_FIFO_DROPPEDCTR_INC(ctx, ac) do { \
++	(ctx)->stats.dropped_qfull[(ac)]++;} while (0)
++#else
++#define WLFC_HOST_FIFO_CREDIT_INC_SENTCTRS(ctx, ac) do {} while (0)
++#define WLFC_HOST_FIFO_CREDIT_INC_BACKCTRS(ctx, ac) do {} while (0)
++#define WLFC_HOST_FIFO_DROPPEDCTR_INC(ctx, ac) do {} while (0)
++#endif
++#define WLFC_PACKET_BOUND              10
++#define WLFC_FCMODE_NONE				0
++#define WLFC_FCMODE_IMPLIED_CREDIT		1
++#define WLFC_FCMODE_EXPLICIT_CREDIT		2
++#define WLFC_ONLY_AMPDU_HOSTREORDER		3
++
++/** Reserved credits ratio when borrowed by hihger priority */
++#define WLFC_BORROW_LIMIT_RATIO		4
++
++/** How long to defer borrowing in milliseconds */
++#define WLFC_BORROW_DEFER_PERIOD_MS 100
++
++/** How long to defer flow control in milliseconds */
++#define WLFC_FC_DEFER_PERIOD_MS 200
++
++/** How long to detect occurance per AC in miliseconds */
++#define WLFC_RX_DETECTION_THRESHOLD_MS	100
++
++/** Mask to represent available ACs (note: BC/MC is ignored) */
++#define WLFC_AC_MASK 0xF
++
++/** flow control specific information, only 1 instance during driver lifetime */
++typedef struct athost_wl_status_info {
++	uint8	last_seqid_to_wlc;
++
++	/** OSL handle */
++	osl_t *osh;
++	/** dhd public struct pointer */
++	void *dhdp;
++
++	f_commitpkt_t fcommit;
++	void* commit_ctx;
++
++	/** statistics */
++	athost_wl_stat_counters_t stats;
++
++	/** incremented on eg receiving a credit map event from the dongle */
++	int		Init_FIFO_credit[AC_COUNT + 2];
++	/** the additional ones are for bc/mc and ATIM FIFO */
++	int		FIFO_credit[AC_COUNT + 2];
++	/** Credit borrow counts for each FIFO from each of the other FIFOs */
++	int		credits_borrowed[AC_COUNT + 2][AC_COUNT + 2];
++
++	/** packet hanger and MAC->handle lookup table */
++	void *hanger;
++
++	struct {
++		/** table for individual nodes */
++		wlfc_mac_descriptor_t	nodes[WLFC_MAC_DESC_TABLE_SIZE];
++		/** table for interfaces */
++		wlfc_mac_descriptor_t	interfaces[WLFC_MAX_IFNUM];
++		/* OS may send packets to unknown (unassociated) destinations */
++		/** A place holder for bc/mc and packets to unknown destinations */
++		wlfc_mac_descriptor_t	other;
++	} destination_entries;
++
++	wlfc_mac_descriptor_t *active_entry_head; /**< a chain of MAC descriptors */
++	int active_entry_count;
++
++	wlfc_mac_descriptor_t *requested_entry[WLFC_MAC_DESC_TABLE_SIZE];
++	int requested_entry_count;
++
++	/* pkt counts for each interface and ac */
++	int	pkt_cnt_in_q[WLFC_MAX_IFNUM][AC_COUNT+1];
++	int	pkt_cnt_per_ac[AC_COUNT+1];
++	int	pkt_cnt_in_drv[WLFC_MAX_IFNUM][AC_COUNT+1];
++	int	pkt_cnt_in_psq;
++	uint8	allow_fc;              /**< Boolean */
++	uint32  fc_defer_timestamp;
++	uint32	rx_timestamp[AC_COUNT+1];
++
++	/** ON/OFF state for flow control to the host network interface */
++	uint8	hostif_flow_state[WLFC_MAX_IFNUM];
++	uint8	host_ifidx;
++
++	/** to flow control an OS interface */
++	uint8	toggle_host_if;
++
++	/** To borrow credits */
++	uint8   allow_credit_borrow;
++
++	/** ac number for the first single ac traffic */
++	uint8	single_ac;
++
++	/** Timestamp for the first single ac traffic */
++	uint32  single_ac_timestamp;
++
++	bool	bcmc_credit_supported;
++
++} athost_wl_status_info_t;
++
++/** Please be mindful that total pkttag space is 32 octets only */
++typedef struct dhd_pkttag {
++
++#ifdef BCM_OBJECT_TRACE
++	/* if use this field, keep it at the first 4 bytes */
++	uint32 sn;
++#endif /* BCM_OBJECT_TRACE */
++
++	/**
++	b[15]  - 1 = wlfc packet
++	b[14:13]  - encryption exemption
++	b[12 ] - 1 = event channel
++	b[11 ] - 1 = this packet was sent in response to one time packet request,
++	do not increment credit on status for this one. [WLFC_CTL_TYPE_MAC_REQUEST_PACKET].
++	b[10 ] - 1 = signal-only-packet to firmware [i.e. nothing to piggyback on]
++	b[9  ] - 1 = packet is host->firmware (transmit direction)
++	       - 0 = packet received from firmware (firmware->host)
++	b[8  ] - 1 = packet was sent due to credit_request (pspoll),
++	             packet does not count against FIFO credit.
++	       - 0 = normal transaction, packet counts against FIFO credit
++	b[7  ] - 1 = AP, 0 = STA
++	b[6:4] - AC FIFO number
++	b[3:0] - interface index
++	*/
++	uint16	if_flags;
++
++	/**
++	 * destination MAC address for this packet so that not every module needs to open the packet
++	 * to find this
++	 */
++	uint8	dstn_ether[ETHER_ADDR_LEN];
++
++	/** This 32-bit goes from host to device for every packet. */
++	uint32	htod_tag;
++
++	/** This 16-bit is original d11seq number for every suppressed packet. */
++	uint16	htod_seq;
++
++	/** This address is mac entry for every packet. */
++	void *entry;
++
++	/** bus specific stuff */
++	union {
++		struct {
++			void *stuff;
++			uint32 thing1;
++			uint32 thing2;
++		} sd;
++
++		struct {
++			void *bus;
++			void *urb;
++		} usb;
++	} bus_specific;
++} dhd_pkttag_t;
++
++#define DHD_PKTTAG_WLFCPKT_MASK			0x1
++#define DHD_PKTTAG_WLFCPKT_SHIFT		15
++#define DHD_PKTTAG_WLFCPKT_SET(tag, value)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & \
++	~(DHD_PKTTAG_WLFCPKT_MASK << DHD_PKTTAG_WLFCPKT_SHIFT)) | \
++	(((value) & DHD_PKTTAG_WLFCPKT_MASK) << DHD_PKTTAG_WLFCPKT_SHIFT)
++#define DHD_PKTTAG_WLFCPKT(tag)	((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_WLFCPKT_SHIFT) & DHD_PKTTAG_WLFCPKT_MASK)
++
++#define DHD_PKTTAG_EXEMPT_MASK			0x3
++#define DHD_PKTTAG_EXEMPT_SHIFT			13
++#define DHD_PKTTAG_EXEMPT_SET(tag, value)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & \
++	~(DHD_PKTTAG_EXEMPT_MASK << DHD_PKTTAG_EXEMPT_SHIFT)) | \
++	(((value) & DHD_PKTTAG_EXEMPT_MASK) << DHD_PKTTAG_EXEMPT_SHIFT)
++#define DHD_PKTTAG_EXEMPT(tag)	((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_EXEMPT_SHIFT) & DHD_PKTTAG_EXEMPT_MASK)
++
++#define DHD_PKTTAG_EVENT_MASK			0x1
++#define DHD_PKTTAG_EVENT_SHIFT			12
++#define DHD_PKTTAG_SETEVENT(tag, event)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & \
++	~(DHD_PKTTAG_EVENT_MASK << DHD_PKTTAG_EVENT_SHIFT)) | \
++	(((event) & DHD_PKTTAG_EVENT_MASK) << DHD_PKTTAG_EVENT_SHIFT)
++#define DHD_PKTTAG_EVENT(tag)	((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_EVENT_SHIFT) & DHD_PKTTAG_EVENT_MASK)
++
++#define DHD_PKTTAG_ONETIMEPKTRQST_MASK		0x1
++#define DHD_PKTTAG_ONETIMEPKTRQST_SHIFT		11
++#define DHD_PKTTAG_SETONETIMEPKTRQST(tag)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & \
++	~(DHD_PKTTAG_ONETIMEPKTRQST_MASK << DHD_PKTTAG_ONETIMEPKTRQST_SHIFT)) | \
++	(1 << DHD_PKTTAG_ONETIMEPKTRQST_SHIFT)
++#define DHD_PKTTAG_ONETIMEPKTRQST(tag)	((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_ONETIMEPKTRQST_SHIFT) & DHD_PKTTAG_ONETIMEPKTRQST_MASK)
++
++#define DHD_PKTTAG_SIGNALONLY_MASK		0x1
++#define DHD_PKTTAG_SIGNALONLY_SHIFT		10
++#define DHD_PKTTAG_SETSIGNALONLY(tag, signalonly)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & \
++	~(DHD_PKTTAG_SIGNALONLY_MASK << DHD_PKTTAG_SIGNALONLY_SHIFT)) | \
++	(((signalonly) & DHD_PKTTAG_SIGNALONLY_MASK) << DHD_PKTTAG_SIGNALONLY_SHIFT)
++#define DHD_PKTTAG_SIGNALONLY(tag)	((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_SIGNALONLY_SHIFT) & DHD_PKTTAG_SIGNALONLY_MASK)
++
++#define DHD_PKTTAG_PKTDIR_MASK			0x1
++#define DHD_PKTTAG_PKTDIR_SHIFT			9
++#define DHD_PKTTAG_SETPKTDIR(tag, dir)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & \
++	~(DHD_PKTTAG_PKTDIR_MASK << DHD_PKTTAG_PKTDIR_SHIFT)) | \
++	(((dir) & DHD_PKTTAG_PKTDIR_MASK) << DHD_PKTTAG_PKTDIR_SHIFT)
++#define DHD_PKTTAG_PKTDIR(tag)	((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_PKTDIR_SHIFT) & DHD_PKTTAG_PKTDIR_MASK)
++
++#define DHD_PKTTAG_CREDITCHECK_MASK		0x1
++#define DHD_PKTTAG_CREDITCHECK_SHIFT		8
++#define DHD_PKTTAG_SETCREDITCHECK(tag, check)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & \
++	~(DHD_PKTTAG_CREDITCHECK_MASK << DHD_PKTTAG_CREDITCHECK_SHIFT)) | \
++	(((check) & DHD_PKTTAG_CREDITCHECK_MASK) << DHD_PKTTAG_CREDITCHECK_SHIFT)
++#define DHD_PKTTAG_CREDITCHECK(tag)	((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_CREDITCHECK_SHIFT) & DHD_PKTTAG_CREDITCHECK_MASK)
++
++#define DHD_PKTTAG_IFTYPE_MASK			0x1
++#define DHD_PKTTAG_IFTYPE_SHIFT			7
++#define DHD_PKTTAG_SETIFTYPE(tag, isAP)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & \
++	~(DHD_PKTTAG_IFTYPE_MASK << DHD_PKTTAG_IFTYPE_SHIFT)) | \
++	(((isAP) & DHD_PKTTAG_IFTYPE_MASK) << DHD_PKTTAG_IFTYPE_SHIFT)
++#define DHD_PKTTAG_IFTYPE(tag)	((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_IFTYPE_SHIFT) & DHD_PKTTAG_IFTYPE_MASK)
++
++#define DHD_PKTTAG_FIFO_MASK			0x7
++#define DHD_PKTTAG_FIFO_SHIFT			4
++#define DHD_PKTTAG_SETFIFO(tag, fifo)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & ~(DHD_PKTTAG_FIFO_MASK << DHD_PKTTAG_FIFO_SHIFT)) | \
++	(((fifo) & DHD_PKTTAG_FIFO_MASK) << DHD_PKTTAG_FIFO_SHIFT)
++#define DHD_PKTTAG_FIFO(tag)		((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_FIFO_SHIFT) & DHD_PKTTAG_FIFO_MASK)
++
++#define DHD_PKTTAG_IF_MASK			0xf
++#define DHD_PKTTAG_IF_SHIFT			0
++#define DHD_PKTTAG_SETIF(tag, if)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & ~(DHD_PKTTAG_IF_MASK << DHD_PKTTAG_IF_SHIFT)) | \
++	(((if) & DHD_PKTTAG_IF_MASK) << DHD_PKTTAG_IF_SHIFT)
++#define DHD_PKTTAG_IF(tag)		((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_IF_SHIFT) & DHD_PKTTAG_IF_MASK)
++
++#define DHD_PKTTAG_SETDSTN(tag, dstn_MAC_ea)	memcpy(((dhd_pkttag_t*)((tag)))->dstn_ether, \
++	(dstn_MAC_ea), ETHER_ADDR_LEN)
++#define DHD_PKTTAG_DSTN(tag)	((dhd_pkttag_t*)(tag))->dstn_ether
++
++#define DHD_PKTTAG_SET_H2DTAG(tag, h2dvalue)	((dhd_pkttag_t*)(tag))->htod_tag = (h2dvalue)
++#define DHD_PKTTAG_H2DTAG(tag)			(((dhd_pkttag_t*)(tag))->htod_tag)
++
++#define DHD_PKTTAG_SET_H2DSEQ(tag, seq)		((dhd_pkttag_t*)(tag))->htod_seq = (seq)
++#define DHD_PKTTAG_H2DSEQ(tag)			(((dhd_pkttag_t*)(tag))->htod_seq)
++
++#define DHD_PKTTAG_SET_ENTRY(tag, entry)	((dhd_pkttag_t*)(tag))->entry = (entry)
++#define DHD_PKTTAG_ENTRY(tag)			(((dhd_pkttag_t*)(tag))->entry)
++
++#define PSQ_SUP_IDX(x) (x * 2 + 1)
++#define PSQ_DLY_IDX(x) (x * 2)
++
++#ifdef PROP_TXSTATUS_DEBUG
++#define DHD_WLFC_CTRINC_MAC_CLOSE(entry)	do { (entry)->closed_ct++; } while (0)
++#define DHD_WLFC_CTRINC_MAC_OPEN(entry)		do { (entry)->opened_ct++; } while (0)
++#else
++#define DHD_WLFC_CTRINC_MAC_CLOSE(entry)	do {} while (0)
++#define DHD_WLFC_CTRINC_MAC_OPEN(entry)		do {} while (0)
++#endif
++
++#ifdef BCM_OBJECT_TRACE
++#define DHD_PKTTAG_SET_SN(tag, val)		((dhd_pkttag_t*)(tag))->sn = (val)
++#define DHD_PKTTAG_SN(tag)			(((dhd_pkttag_t*)(tag))->sn)
++#endif /* BCM_OBJECT_TRACE */
++
++/* public functions */
++int dhd_wlfc_parse_header_info(dhd_pub_t *dhd, void* pktbuf, int tlv_hdr_len,
++	uchar *reorder_info_buf, uint *reorder_info_len);
++KERNEL_THREAD_RETURN_TYPE dhd_wlfc_transfer_packets(void *data);
++int dhd_wlfc_commit_packets(dhd_pub_t *dhdp, f_commitpkt_t fcommit,
++	void* commit_ctx, void *pktbuf, bool need_toggle_host_if);
++int dhd_wlfc_txcomplete(dhd_pub_t *dhd, void *txp, bool success);
++int dhd_wlfc_init(dhd_pub_t *dhd);
++#ifdef SUPPORT_P2P_GO_PS
++int dhd_wlfc_suspend(dhd_pub_t *dhd);
++int dhd_wlfc_resume(dhd_pub_t *dhd);
++#endif /* SUPPORT_P2P_GO_PS */
++int dhd_wlfc_hostreorder_init(dhd_pub_t *dhd);
++int dhd_wlfc_cleanup_txq(dhd_pub_t *dhd, f_processpkt_t fn, void *arg);
++int dhd_wlfc_cleanup(dhd_pub_t *dhd, f_processpkt_t fn, void* arg);
++int dhd_wlfc_deinit(dhd_pub_t *dhd);
++int dhd_wlfc_interface_event(dhd_pub_t *dhdp, uint8 action, uint8 ifid, uint8 iftype, uint8* ea);
++int dhd_wlfc_FIFOcreditmap_event(dhd_pub_t *dhdp, uint8* event_data);
++#ifdef LIMIT_BORROW
++int dhd_wlfc_disable_credit_borrow_event(dhd_pub_t *dhdp, uint8* event_data);
++#endif /* LIMIT_BORROW */
++int dhd_wlfc_BCMCCredit_support_event(dhd_pub_t *dhdp);
++int dhd_wlfc_enable(dhd_pub_t *dhdp);
++int dhd_wlfc_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf);
++int dhd_wlfc_clear_counts(dhd_pub_t *dhd);
++int dhd_wlfc_get_enable(dhd_pub_t *dhd, bool *val);
++int dhd_wlfc_get_mode(dhd_pub_t *dhd, int *val);
++int dhd_wlfc_set_mode(dhd_pub_t *dhd, int val);
++bool dhd_wlfc_is_supported(dhd_pub_t *dhd);
++bool dhd_wlfc_is_header_only_pkt(dhd_pub_t * dhd, void *pktbuf);
++int dhd_wlfc_flowcontrol(dhd_pub_t *dhdp, bool state, bool bAcquireLock);
++int dhd_wlfc_save_rxpath_ac_time(dhd_pub_t * dhd, uint8 prio);
++
++int dhd_wlfc_get_module_ignore(dhd_pub_t *dhd, int *val);
++int dhd_wlfc_set_module_ignore(dhd_pub_t *dhd, int val);
++int dhd_wlfc_get_credit_ignore(dhd_pub_t *dhd, int *val);
++int dhd_wlfc_set_credit_ignore(dhd_pub_t *dhd, int val);
++int dhd_wlfc_get_txstatus_ignore(dhd_pub_t *dhd, int *val);
++int dhd_wlfc_set_txstatus_ignore(dhd_pub_t *dhd, int val);
++
++int dhd_wlfc_get_rxpkt_chk(dhd_pub_t *dhd, int *val);
++int dhd_wlfc_set_rxpkt_chk(dhd_pub_t *dhd, int val);
++
++#endif /* __wlfc_host_driver_definitions_h__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dngl_stats.h b/module_drivers/drivers/net/wireless/bcmdhd/dngl_stats.h
+new file mode 100644
+index 000000000..b995ec5b0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dngl_stats.h
+@@ -0,0 +1,383 @@
++/*
++ * Common stats definitions for clients of dongle
++ * ports
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dngl_stats.h 681171 2017-01-25 05:27:08Z $
++ */
++
++#ifndef _dngl_stats_h_
++#define _dngl_stats_h_
++
++#include <ethernet.h>
++#include <802.11.h>
++
++typedef struct {
++	unsigned long	rx_packets;		/* total packets received */
++	unsigned long	tx_packets;		/* total packets transmitted */
++	unsigned long	rx_bytes;		/* total bytes received */
++	unsigned long	tx_bytes;		/* total bytes transmitted */
++	unsigned long	rx_errors;		/* bad packets received */
++	unsigned long	tx_errors;		/* packet transmit problems */
++	unsigned long	rx_dropped;		/* packets dropped by dongle */
++	unsigned long	tx_dropped;		/* packets dropped by dongle */
++	unsigned long   multicast;      /* multicast packets received */
++} dngl_stats_t;
++
++typedef int32 wifi_radio;
++typedef int32 wifi_channel;
++typedef int32 wifi_rssi;
++typedef struct { uint16 version; uint16 length; } ver_len;
++
++typedef enum wifi_channel_width {
++	WIFI_CHAN_WIDTH_20	  = 0,
++	WIFI_CHAN_WIDTH_40	  = 1,
++	WIFI_CHAN_WIDTH_80	  = 2,
++	WIFI_CHAN_WIDTH_160   = 3,
++	WIFI_CHAN_WIDTH_80P80 = 4,
++	WIFI_CHAN_WIDTH_5	  = 5,
++	WIFI_CHAN_WIDTH_10	  = 6,
++	WIFI_CHAN_WIDTH_INVALID = -1
++} wifi_channel_width_t;
++
++typedef enum {
++	WIFI_DISCONNECTED = 0,
++	WIFI_AUTHENTICATING = 1,
++	WIFI_ASSOCIATING = 2,
++	WIFI_ASSOCIATED = 3,
++	WIFI_EAPOL_STARTED = 4,   /* if done by firmware/driver */
++	WIFI_EAPOL_COMPLETED = 5, /* if done by firmware/driver */
++} wifi_connection_state;
++
++typedef enum {
++	WIFI_ROAMING_IDLE = 0,
++	WIFI_ROAMING_ACTIVE = 1
++} wifi_roam_state;
++
++typedef enum {
++	WIFI_INTERFACE_STA = 0,
++	WIFI_INTERFACE_SOFTAP = 1,
++	WIFI_INTERFACE_IBSS = 2,
++	WIFI_INTERFACE_P2P_CLIENT = 3,
++	WIFI_INTERFACE_P2P_GO = 4,
++	WIFI_INTERFACE_NAN = 5,
++	WIFI_INTERFACE_MESH = 6
++} wifi_interface_mode;
++
++#define WIFI_CAPABILITY_QOS          0x00000001     /* set for QOS association */
++#define WIFI_CAPABILITY_PROTECTED    0x00000002     /* set for protected association (802.11
++						     * beacon frame control protected bit set)
++						     */
++#define WIFI_CAPABILITY_INTERWORKING 0x00000004     /* set if 802.11 Extended Capabilities
++						     * element interworking bit is set
++						     */
++#define WIFI_CAPABILITY_HS20         0x00000008     /* set for HS20 association */
++#define WIFI_CAPABILITY_SSID_UTF8    0x00000010     /* set is 802.11 Extended Capabilities
++						     * element UTF-8 SSID bit is set
++						     */
++#define WIFI_CAPABILITY_COUNTRY      0x00000020     /* set is 802.11 Country Element is present */
++#define PACK_ATTRIBUTE __attribute__ ((packed))
++typedef struct {
++	wifi_interface_mode mode;     /* interface mode */
++	uint8 mac_addr[6];               /* interface mac address (self) */
++	wifi_connection_state state;  /* connection state (valid for STA, CLI only) */
++	wifi_roam_state roaming;      /* roaming state */
++	uint32 capabilities;             /* WIFI_CAPABILITY_XXX (self) */
++	uint8 ssid[DOT11_MAX_SSID_LEN+1]; /* null terminated SSID */
++	uint8 bssid[ETHER_ADDR_LEN];     /* bssid */
++	uint8 ap_country_str[3];         /* country string advertised by AP */
++	uint8 country_str[3];            /* country string for this association */
++} wifi_interface_info;
++
++typedef wifi_interface_info *wifi_interface_handle;
++
++/* channel information */
++typedef struct {
++	wifi_channel_width_t width;   /* channel width (20, 40, 80, 80+80, 160) */
++	wifi_channel center_freq;   /* primary 20 MHz channel */
++	wifi_channel center_freq0;  /* center frequency (MHz) first segment */
++	wifi_channel center_freq1;  /* center frequency (MHz) second segment */
++} wifi_channel_info;
++
++/* wifi rate */
++typedef struct {
++	uint32 preamble;   /* 0: OFDM, 1:CCK, 2:HT 3:VHT 4..7 reserved */
++	uint32 nss;   	/* 0:1x1, 1:2x2, 3:3x3, 4:4x4 */
++	uint32 bw;   	/* 0:20MHz, 1:40Mhz, 2:80Mhz, 3:160Mhz */
++	uint32 rateMcsIdx; /* OFDM/CCK rate code would be as per ieee std
++			    * in the units of 0.5mbps
++			    */
++			/* HT/VHT it would be mcs index */
++	uint32 reserved;   /* reserved */
++	uint32 bitrate;    /* units of 100 Kbps */
++} wifi_rate;
++
++typedef struct {
++	uint32 preamble   :3;   /* 0: OFDM, 1:CCK, 2:HT 3:VHT 4..7 reserved */
++	uint32 nss        :2;   /* 0:1x1, 1:2x2, 3:3x3, 4:4x4 */
++	uint32 bw         :3;   /* 0:20MHz, 1:40Mhz, 2:80Mhz, 3:160Mhz */
++	uint32 rateMcsIdx :8;   /* OFDM/CCK rate code would be as per ieee std
++					* in the units of 0.5mbps HT/VHT it would be
++					* mcs index
++					*/
++	uint32 reserved  :16;   /* reserved */
++	uint32 bitrate;         /* units of 100 Kbps */
++} wifi_rate_v1;
++
++/* channel statistics */
++typedef struct {
++	wifi_channel_info channel;  /* channel */
++	uint32 on_time;         	/* msecs the radio is awake (32 bits number
++				         * accruing over time)
++					 */
++	uint32 cca_busy_time;          /* msecs the CCA register is busy (32 bits number
++					* accruing over time)
++					*/
++} wifi_channel_stat;
++
++/* radio statistics */
++typedef struct {
++	struct {
++		uint16 version;
++		uint16 length;
++	};
++	wifi_radio radio;               /* wifi radio (if multiple radio supported) */
++	uint32 on_time;                    /* msecs the radio is awake (32 bits number
++					    * accruing over time)
++					    */
++	uint32 tx_time;                    /* msecs the radio is transmitting (32 bits
++					    * number accruing over time)
++					    */
++	uint32 rx_time;                    /* msecs the radio is in active receive (32 bits
++					    * number accruing over time)
++					    */
++	uint32 on_time_scan;               /* msecs the radio is awake due to all scan (32 bits
++					    * number accruing over time)
++					    */
++	uint32 on_time_nbd;                /* msecs the radio is awake due to NAN (32 bits
++					    * number accruing over time)
++					    */
++	uint32 on_time_gscan;              /* msecs the radio is awake due to G?scan (32 bits
++					    * number accruing over time)
++					    */
++	uint32 on_time_roam_scan;          /* msecs the radio is awake due to roam?scan (32 bits
++					    * number accruing over time)
++					    */
++	uint32 on_time_pno_scan;           /* msecs the radio is awake due to PNO scan (32 bits
++					    * number accruing over time)
++					    */
++	uint32 on_time_hs20;               /* msecs the radio is awake due to HS2.0 scans and
++					    * GAS exchange (32 bits number accruing over time)
++					    */
++	uint32 num_channels;               /* number of channels */
++	wifi_channel_stat channels[1];   /* channel statistics */
++} wifi_radio_stat;
++
++typedef struct {
++	wifi_radio radio;
++	uint32 on_time;
++	uint32 tx_time;
++	uint32 rx_time;
++	uint32 on_time_scan;
++	uint32 on_time_nbd;
++	uint32 on_time_gscan;
++	uint32 on_time_roam_scan;
++	uint32 on_time_pno_scan;
++	uint32 on_time_hs20;
++	uint32 num_channels;
++} wifi_radio_stat_h;
++
++/* per rate statistics */
++typedef struct {
++	wifi_rate_v1 rate;     /* rate information */
++	uint32 tx_mpdu;        /* number of successfully transmitted data pkts (ACK rcvd) */
++	uint32 rx_mpdu;        /* number of received data pkts */
++	uint32 mpdu_lost;      /* number of data packet losses (no ACK) */
++	uint32 retries;        /* total number of data pkt retries */
++	uint32 retries_short;  /* number of short data pkt retries */
++	uint32 retries_long;   /* number of long data pkt retries */
++} wifi_rate_stat_v1;
++
++typedef struct {
++	uint16 version;
++	uint16 length;
++	uint32 tx_mpdu;        /* number of successfully transmitted data pkts (ACK rcvd) */
++	uint32 rx_mpdu;        /* number of received data pkts */
++	uint32 mpdu_lost;      /* number of data packet losses (no ACK) */
++	uint32 retries;        /* total number of data pkt retries */
++	uint32 retries_short;  /* number of short data pkt retries */
++	uint32 retries_long;   /* number of long data pkt retries */
++	wifi_rate rate;
++} wifi_rate_stat;
++
++/* access categories */
++typedef enum {
++	WIFI_AC_VO  = 0,
++	WIFI_AC_VI  = 1,
++	WIFI_AC_BE  = 2,
++	WIFI_AC_BK  = 3,
++	WIFI_AC_MAX = 4
++} wifi_traffic_ac;
++
++/* wifi peer type */
++typedef enum
++{
++	WIFI_PEER_STA,
++	WIFI_PEER_AP,
++	WIFI_PEER_P2P_GO,
++	WIFI_PEER_P2P_CLIENT,
++	WIFI_PEER_NAN,
++	WIFI_PEER_TDLS,
++	WIFI_PEER_INVALID
++} wifi_peer_type;
++
++/* per peer statistics */
++typedef struct {
++	wifi_peer_type type;           /* peer type (AP, TDLS, GO etc.) */
++	uint8 peer_mac_address[6];        /* mac address */
++	uint32 capabilities;              /* peer WIFI_CAPABILITY_XXX */
++	uint32 num_rate;                  /* number of rates */
++	wifi_rate_stat rate_stats[1];   /* per rate statistics, number of entries  = num_rate */
++} wifi_peer_info;
++
++/* per access category statistics */
++typedef struct {
++	wifi_traffic_ac ac;             /* access category (VI, VO, BE, BK) */
++	uint32 tx_mpdu;                    /* number of successfully transmitted unicast data pkts
++					    * (ACK rcvd)
++					    */
++	uint32 rx_mpdu;                    /* number of received unicast mpdus */
++	uint32 tx_mcast;                   /* number of succesfully transmitted multicast
++					    * data packets
++					    */
++					   /* STA case: implies ACK received from AP for the
++					    * unicast packet in which mcast pkt was sent
++					    */
++	uint32 rx_mcast;                   /* number of received multicast data packets */
++	uint32 rx_ampdu;                   /* number of received unicast a-mpdus */
++	uint32 tx_ampdu;                   /* number of transmitted unicast a-mpdus */
++	uint32 mpdu_lost;                  /* number of data pkt losses (no ACK) */
++	uint32 retries;                    /* total number of data pkt retries */
++	uint32 retries_short;              /* number of short data pkt retries */
++	uint32 retries_long;               /* number of long data pkt retries */
++	uint32 contention_time_min;        /* data pkt min contention time (usecs) */
++	uint32 contention_time_max;        /* data pkt max contention time (usecs) */
++	uint32 contention_time_avg;        /* data pkt avg contention time (usecs) */
++	uint32 contention_num_samples;     /* num of data pkts used for contention statistics */
++} wifi_wmm_ac_stat;
++
++/* interface statistics */
++typedef struct {
++	wifi_interface_handle iface;          /* wifi interface */
++	wifi_interface_info info;             /* current state of the interface */
++	uint32 beacon_rx;                     /* access point beacon received count from
++					       * connected AP
++					       */
++	uint64 average_tsf_offset;	/* average beacon offset encountered (beacon_TSF - TBTT)
++					* The average_tsf_offset field is used so as to calculate
++					* the typical beacon contention time on the channel as well
++					* may be used to debug beacon synchronization and related
++					* power consumption issue
++					*/
++	uint32 leaky_ap_detected;	/* indicate that this AP
++					* typically leaks packets beyond
++					* the driver guard time.
++					*/
++	uint32 leaky_ap_avg_num_frames_leaked;	/* average number of frame leaked by AP after
++					* frame with PM bit set was ACK'ed by AP
++					*/
++	uint32 leaky_ap_guard_time;		/* guard time currently in force
++					* (when implementing IEEE power management
++					* based on frame control PM bit), How long
++					* driver waits before shutting down the radio and after
++					* receiving an ACK for a data frame with PM bit set)
++					*/
++	uint32 mgmt_rx;                       /* access point mgmt frames received count from
++				       * connected AP (including Beacon)
++				       */
++	uint32 mgmt_action_rx;                /* action frames received count */
++	uint32 mgmt_action_tx;                /* action frames transmit count */
++	wifi_rssi rssi_mgmt;                  /* access Point Beacon and Management frames RSSI
++					       * (averaged)
++					       */
++	wifi_rssi rssi_data;                  /* access Point Data Frames RSSI (averaged) from
++					       * connected AP
++					       */
++	wifi_rssi rssi_ack;                   /* access Point ACK RSSI (averaged) from
++					       * connected AP
++					       */
++	wifi_wmm_ac_stat ac[WIFI_AC_MAX];     /* per ac data packet statistics */
++	uint32 num_peers;                        /* number of peers */
++	wifi_peer_info peer_info[1];           /* per peer statistics */
++} wifi_iface_stat;
++
++#ifdef CONFIG_COMPAT
++/* interface statistics */
++typedef struct {
++	compat_uptr_t iface;          /* wifi interface */
++	wifi_interface_info info;             /* current state of the interface */
++	uint32 beacon_rx;                     /* access point beacon received count from
++					       * connected AP
++					       */
++	uint64 average_tsf_offset;	/* average beacon offset encountered (beacon_TSF - TBTT)
++					* The average_tsf_offset field is used so as to calculate
++					* the typical beacon contention time on the channel as well
++					* may be used to debug beacon synchronization and related
++					* power consumption issue
++					*/
++	uint32 leaky_ap_detected;	/* indicate that this AP
++					* typically leaks packets beyond
++					* the driver guard time.
++					*/
++	uint32 leaky_ap_avg_num_frames_leaked;	/* average number of frame leaked by AP after
++					* frame with PM bit set was ACK'ed by AP
++					*/
++	uint32 leaky_ap_guard_time;		/* guard time currently in force
++					* (when implementing IEEE power management
++					* based on frame control PM bit), How long
++					* driver waits before shutting down the radio and after
++					* receiving an ACK for a data frame with PM bit set)
++					*/
++	uint32 mgmt_rx;                       /* access point mgmt frames received count from
++				       * connected AP (including Beacon)
++				       */
++	uint32 mgmt_action_rx;                /* action frames received count */
++	uint32 mgmt_action_tx;                /* action frames transmit count */
++	wifi_rssi rssi_mgmt;                  /* access Point Beacon and Management frames RSSI
++					       * (averaged)
++					       */
++	wifi_rssi rssi_data;                  /* access Point Data Frames RSSI (averaged) from
++					       * connected AP
++					       */
++	wifi_rssi rssi_ack;                   /* access Point ACK RSSI (averaged) from
++					       * connected AP
++					       */
++	wifi_wmm_ac_stat ac[WIFI_AC_MAX];     /* per ac data packet statistics */
++	uint32 num_peers;                        /* number of peers */
++	wifi_peer_info peer_info[1];           /* per peer statistics */
++} compat_wifi_iface_stat;
++#endif /* CONFIG_COMPAT */
++
++#endif /* _dngl_stats_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/dngl_wlhdr.h b/module_drivers/drivers/net/wireless/bcmdhd/dngl_wlhdr.h
+new file mode 100644
+index 000000000..96da42e5f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/dngl_wlhdr.h
+@@ -0,0 +1,43 @@
++/*
++ * Dongle WL Header definitions
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dngl_wlhdr.h 514727 2014-11-12 03:02:48Z $
++ */
++
++#ifndef _dngl_wlhdr_h_
++#define _dngl_wlhdr_h_
++
++typedef struct wl_header {
++    uint8   type;           /* Header type */
++    uint8   version;        /* Header version */
++	int8	rssi;			/* RSSI */
++	uint8	pad;			/* Unused */
++} wl_header_t;
++
++#define WL_HEADER_LEN   sizeof(wl_header_t)
++#define WL_HEADER_TYPE  0
++#define WL_HEADER_VER   1
++#endif /* _dngl_wlhdr_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/hnd_pktpool.c b/module_drivers/drivers/net/wireless/bcmdhd/hnd_pktpool.c
+new file mode 100644
+index 000000000..0c5c3a8a3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/hnd_pktpool.c
+@@ -0,0 +1,1180 @@
++/*
++ * HND generic packet pool operation primitives
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: hnd_pktpool.c 613891 2016-01-20 10:05:44Z $
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++#include <osl_ext.h>
++#include <bcmutils.h>
++#include <hnd_pktpool.h>
++
++
++/* mutex macros for thread safe */
++#ifdef HND_PKTPOOL_THREAD_SAFE
++#define HND_PKTPOOL_MUTEX_CREATE(name, mutex)	osl_ext_mutex_create(name, mutex)
++#define HND_PKTPOOL_MUTEX_DELETE(mutex)		osl_ext_mutex_delete(mutex)
++#define HND_PKTPOOL_MUTEX_ACQUIRE(mutex, msec)	osl_ext_mutex_acquire(mutex, msec)
++#define HND_PKTPOOL_MUTEX_RELEASE(mutex)	osl_ext_mutex_release(mutex)
++#else
++#define HND_PKTPOOL_MUTEX_CREATE(name, mutex)	OSL_EXT_SUCCESS
++#define HND_PKTPOOL_MUTEX_DELETE(mutex)		OSL_EXT_SUCCESS
++#define HND_PKTPOOL_MUTEX_ACQUIRE(mutex, msec)	OSL_EXT_SUCCESS
++#define HND_PKTPOOL_MUTEX_RELEASE(mutex)	OSL_EXT_SUCCESS
++#endif
++
++/* Registry size is one larger than max pools, as slot #0 is reserved */
++#define PKTPOOLREG_RSVD_ID				(0U)
++#define PKTPOOLREG_RSVD_PTR				(POOLPTR(0xdeaddead))
++#define PKTPOOLREG_FREE_PTR				(POOLPTR(NULL))
++
++#define PKTPOOL_REGISTRY_SET(id, pp)	(pktpool_registry_set((id), (pp)))
++#define PKTPOOL_REGISTRY_CMP(id, pp)	(pktpool_registry_cmp((id), (pp)))
++
++/* Tag a registry entry as free for use */
++#define PKTPOOL_REGISTRY_CLR(id)		\
++		PKTPOOL_REGISTRY_SET((id), PKTPOOLREG_FREE_PTR)
++#define PKTPOOL_REGISTRY_ISCLR(id)		\
++		(PKTPOOL_REGISTRY_CMP((id), PKTPOOLREG_FREE_PTR))
++
++/* Tag registry entry 0 as reserved */
++#define PKTPOOL_REGISTRY_RSV()			\
++		PKTPOOL_REGISTRY_SET(PKTPOOLREG_RSVD_ID, PKTPOOLREG_RSVD_PTR)
++#define PKTPOOL_REGISTRY_ISRSVD()		\
++		(PKTPOOL_REGISTRY_CMP(PKTPOOLREG_RSVD_ID, PKTPOOLREG_RSVD_PTR))
++
++/* Walk all un-reserved entries in registry */
++#define PKTPOOL_REGISTRY_FOREACH(id)	\
++		for ((id) = 1U; (id) <= pktpools_max; (id)++)
++
++enum pktpool_empty_cb_state {
++	EMPTYCB_ENABLED = 0,	/* Enable callback when new packets are added to pool */
++	EMPTYCB_DISABLED,	/* Disable callback when new packets are added to pool */
++	EMPTYCB_SKIPPED		/* Packet was added to pool when callback was disabled */
++};
++
++uint32 pktpools_max = 0U; /* maximum number of pools that may be initialized */
++pktpool_t *pktpools_registry[PKTPOOL_MAXIMUM_ID + 1]; /* Pktpool registry */
++
++/* Register/Deregister a pktpool with registry during pktpool_init/deinit */
++static int pktpool_register(pktpool_t * poolptr);
++static int pktpool_deregister(pktpool_t * poolptr);
++
++/** add declaration */
++static void pktpool_avail_notify(pktpool_t *pktp);
++
++/** accessor functions required when ROMming this file, forced into RAM */
++
++
++pktpool_t *
++BCMRAMFN(get_pktpools_registry)(int id)
++{
++	return pktpools_registry[id];
++}
++
++static void
++BCMRAMFN(pktpool_registry_set)(int id, pktpool_t *pp)
++{
++	pktpools_registry[id] = pp;
++}
++
++static bool
++BCMRAMFN(pktpool_registry_cmp)(int id, pktpool_t *pp)
++{
++	return pktpools_registry[id] == pp;
++}
++
++/** Constructs a pool registry to serve a maximum of total_pools */
++int
++pktpool_attach(osl_t *osh, uint32 total_pools)
++{
++	uint32 poolid;
++	BCM_REFERENCE(osh);
++
++	if (pktpools_max != 0U) {
++		return BCME_ERROR;
++	}
++
++	ASSERT(total_pools <= PKTPOOL_MAXIMUM_ID);
++
++	/* Initialize registry: reserve slot#0 and tag others as free */
++	PKTPOOL_REGISTRY_RSV();		/* reserve slot#0 */
++
++	PKTPOOL_REGISTRY_FOREACH(poolid) {	/* tag all unreserved entries as free */
++		PKTPOOL_REGISTRY_CLR(poolid);
++	}
++
++	pktpools_max = total_pools;
++
++	return (int)pktpools_max;
++}
++
++/** Destructs the pool registry. Ascertain all pools were first de-inited */
++int
++pktpool_dettach(osl_t *osh)
++{
++	uint32 poolid;
++	BCM_REFERENCE(osh);
++
++	if (pktpools_max == 0U) {
++		return BCME_OK;
++	}
++
++	/* Ascertain that no pools are still registered */
++	ASSERT(PKTPOOL_REGISTRY_ISRSVD()); /* assert reserved slot */
++
++	PKTPOOL_REGISTRY_FOREACH(poolid) {	/* ascertain all others are free */
++		ASSERT(PKTPOOL_REGISTRY_ISCLR(poolid));
++	}
++
++	pktpools_max = 0U; /* restore boot state */
++
++	return BCME_OK;
++}
++
++/** Registers a pool in a free slot; returns the registry slot index */
++static int
++pktpool_register(pktpool_t * poolptr)
++{
++	uint32 poolid;
++
++	if (pktpools_max == 0U) {
++		return PKTPOOL_INVALID_ID; /* registry has not yet been constructed */
++	}
++
++	ASSERT(pktpools_max != 0U);
++
++	/* find an empty slot in pktpools_registry */
++	PKTPOOL_REGISTRY_FOREACH(poolid) {
++		if (PKTPOOL_REGISTRY_ISCLR(poolid)) {
++			PKTPOOL_REGISTRY_SET(poolid, POOLPTR(poolptr)); /* register pool */
++			return (int)poolid; /* return pool ID */
++		}
++	} /* FOREACH */
++
++	return PKTPOOL_INVALID_ID;	/* error: registry is full */
++}
++
++/** Deregisters a pktpool, given the pool pointer; tag slot as free */
++static int
++pktpool_deregister(pktpool_t * poolptr)
++{
++	uint32 poolid;
++
++	ASSERT(POOLPTR(poolptr) != POOLPTR(NULL));
++
++	poolid = POOLID(poolptr);
++	ASSERT(poolid <= pktpools_max);
++
++	/* Asertain that a previously registered poolptr is being de-registered */
++	if (PKTPOOL_REGISTRY_CMP(poolid, POOLPTR(poolptr))) {
++		PKTPOOL_REGISTRY_CLR(poolid); /* mark as free */
++	} else {
++		ASSERT(0);
++		return BCME_ERROR; /* mismatch in registry */
++	}
++
++	return BCME_OK;
++}
++
++/**
++ * pktpool_init:
++ * User provides a pktpool_t structure and specifies the number of packets to
++ * be pre-filled into the pool (pplen).
++ * pktpool_init first attempts to register the pool and fetch a unique poolid.
++ * If registration fails, it is considered an BCME_ERR, caused by either the
++ * registry was not pre-created (pktpool_attach) or the registry is full.
++ * If registration succeeds, then the requested number of packets will be filled
++ * into the pool as part of initialization. In the event that there is no
++ * available memory to service the request, then BCME_NOMEM will be returned
++ * along with the count of how many packets were successfully allocated.
++ * In dongle builds, prior to memory reclaimation, one should limit the number
++ * of packets to be allocated during pktpool_init and fill the pool up after
++ * reclaim stage.
++ *
++ * @param pplen  Number of packets to be pre-filled into the pool
++ * @param plen   The size of all packets in a pool must be the same, [bytes] units. E.g. PKTBUFSZ.
++ * @param type   e.g. 'lbuf_frag'
++ */
++int
++pktpool_init(osl_t *osh, pktpool_t *pktp, int *pplen, int plen, bool istx, uint8 type)
++{
++	int i, err = BCME_OK;
++	int pktplen;
++	uint8 pktp_id;
++
++	ASSERT(pktp != NULL);
++	ASSERT(osh != NULL);
++	ASSERT(pplen != NULL);
++
++	pktplen = *pplen;
++
++	bzero(pktp, sizeof(pktpool_t));
++
++	/* assign a unique pktpool id */
++	if ((pktp_id = (uint8) pktpool_register(pktp)) == PKTPOOL_INVALID_ID) {
++		return BCME_ERROR;
++	}
++	POOLSETID(pktp, pktp_id);
++
++	pktp->inited = TRUE;
++	pktp->istx = istx ? TRUE : FALSE;
++	pktp->plen = (uint16)plen;
++	pktp->type = type;
++
++	if (HND_PKTPOOL_MUTEX_CREATE("pktpool", &pktp->mutex) != OSL_EXT_SUCCESS) {
++		return BCME_ERROR;
++	}
++
++	pktp->maxlen = PKTPOOL_LEN_MAX;
++	pktplen = LIMIT_TO_MAX(pktplen, pktp->maxlen);
++
++	for (i = 0; i < pktplen; i++) {
++		void *p;
++		p = PKTGET(osh, plen, TRUE);
++
++		if (p == NULL) {
++			/* Not able to allocate all requested pkts
++			 * so just return what was actually allocated
++			 * We can add to the pool later
++			 */
++			if (pktp->freelist == NULL) /* pktpool free list is empty */
++				err = BCME_NOMEM;
++
++			goto exit;
++		}
++
++		PKTSETPOOL(osh, p, TRUE, pktp); /* Tag packet with pool ID */
++
++		PKTSETFREELIST(p, pktp->freelist); /* insert p at head of free list */
++		pktp->freelist = p;
++
++		pktp->avail++;
++
++#ifdef BCMDBG_POOL
++		pktp->dbg_q[pktp->dbg_qlen++].p = p;
++#endif
++	}
++
++exit:
++	pktp->len = pktp->avail;
++
++	*pplen = pktp->len; /* number of packets managed by pool */
++	return err;
++} /* pktpool_init */
++
++/**
++ * pktpool_deinit:
++ * Prior to freeing a pktpool, all packets must be first freed into the pktpool.
++ * Upon pktpool_deinit, all packets in the free pool will be freed to the heap.
++ * An assert is in place to ensure that there are no packets still lingering
++ * around. Packets freed to a pool after the deinit will cause a memory
++ * corruption as the pktpool_t structure no longer exists.
++ */
++int
++pktpool_deinit(osl_t *osh, pktpool_t *pktp)
++{
++	uint16 freed = 0;
++
++	ASSERT(osh != NULL);
++	ASSERT(pktp != NULL);
++
++#ifdef BCMDBG_POOL
++	{
++		int i;
++		for (i = 0; i <= pktp->len; i++) {
++			pktp->dbg_q[i].p = NULL;
++		}
++	}
++#endif
++
++	while (pktp->freelist != NULL) {
++		void * p = pktp->freelist;
++
++		pktp->freelist = PKTFREELIST(p); /* unlink head packet from free list */
++		PKTSETFREELIST(p, NULL);
++
++		PKTSETPOOL(osh, p, FALSE, NULL); /* clear pool ID tag in pkt */
++
++		PKTFREE(osh, p, pktp->istx); /* free the packet */
++
++		freed++;
++		ASSERT(freed <= pktp->len);
++	}
++
++	pktp->avail -= freed;
++	ASSERT(pktp->avail == 0);
++
++	pktp->len -= freed;
++
++	pktpool_deregister(pktp); /* release previously acquired unique pool id */
++	POOLSETID(pktp, PKTPOOL_INVALID_ID);
++
++	if (HND_PKTPOOL_MUTEX_DELETE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	pktp->inited = FALSE;
++
++	/* Are there still pending pkts? */
++	ASSERT(pktp->len == 0);
++
++	return 0;
++}
++
++int
++pktpool_fill(osl_t *osh, pktpool_t *pktp, bool minimal)
++{
++	void *p;
++	int err = 0;
++	int len, psize, maxlen;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	ASSERT(pktp->plen != 0);
++
++	maxlen = pktp->maxlen;
++	psize = minimal ? (maxlen >> 2) : maxlen;
++	for (len = (int)pktp->len; len < psize; len++) {
++
++		p = PKTGET(osh, pktp->len, TRUE);
++
++		if (p == NULL) {
++			err = BCME_NOMEM;
++			break;
++		}
++
++		if (pktpool_add(pktp, p) != BCME_OK) {
++			PKTFREE(osh, p, FALSE);
++			err = BCME_ERROR;
++			break;
++		}
++	}
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	if (pktp->cbcnt) {
++		if (pktp->empty == FALSE)
++			pktpool_avail_notify(pktp);
++	}
++
++	return err;
++}
++
++static void *
++pktpool_deq(pktpool_t *pktp)
++{
++	void *p = NULL;
++
++	if (pktp->avail == 0)
++		return NULL;
++
++	ASSERT(pktp->freelist != NULL);
++
++	p = pktp->freelist;  /* dequeue packet from head of pktpool free list */
++	pktp->freelist = PKTFREELIST(p); /* free list points to next packet */
++
++
++	PKTSETFREELIST(p, NULL);
++
++	pktp->avail--;
++
++	return p;
++}
++
++static void
++pktpool_enq(pktpool_t *pktp, void *p)
++{
++	ASSERT(p != NULL);
++
++	PKTSETFREELIST(p, pktp->freelist); /* insert at head of pktpool free list */
++	pktp->freelist = p; /* free list points to newly inserted packet */
++
++
++	pktp->avail++;
++	ASSERT(pktp->avail <= pktp->len);
++}
++
++/** utility for registering host addr fill function called from pciedev */
++int
++/* BCMATTACHFN */
++(pktpool_hostaddr_fill_register)(pktpool_t *pktp, pktpool_cb_extn_t cb, void *arg)
++{
++
++	ASSERT(cb != NULL);
++
++	ASSERT(pktp->cbext.cb == NULL);
++	pktp->cbext.cb = cb;
++	pktp->cbext.arg = arg;
++	return 0;
++}
++
++int
++pktpool_rxcplid_fill_register(pktpool_t *pktp, pktpool_cb_extn_t cb, void *arg)
++{
++
++	ASSERT(cb != NULL);
++
++	if (pktp == NULL)
++		return BCME_ERROR;
++	ASSERT(pktp->rxcplidfn.cb == NULL);
++	pktp->rxcplidfn.cb = cb;
++	pktp->rxcplidfn.arg = arg;
++	return 0;
++}
++
++/** whenever host posts rxbuffer, invoke dma_rxfill from pciedev layer */
++void
++pktpool_invoke_dmarxfill(pktpool_t *pktp)
++{
++	ASSERT(pktp->dmarxfill.cb);
++	ASSERT(pktp->dmarxfill.arg);
++
++	if (pktp->dmarxfill.cb)
++		pktp->dmarxfill.cb(pktp, pktp->dmarxfill.arg);
++}
++
++/** Registers callback functions for split rx mode */
++int
++pkpool_haddr_avail_register_cb(pktpool_t *pktp, pktpool_cb_t cb, void *arg)
++{
++
++	ASSERT(cb != NULL);
++
++	pktp->dmarxfill.cb = cb;
++	pktp->dmarxfill.arg = arg;
++
++	return 0;
++}
++
++/**
++ * Registers callback functions.
++ * No BCMATTACHFN as it is used in xdc_enable_ep which is not an attach function
++ */
++int
++pktpool_avail_register(pktpool_t *pktp, pktpool_cb_t cb, void *arg)
++{
++	int err = 0;
++	int i;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	ASSERT(cb != NULL);
++
++	i = pktp->cbcnt;
++	if (i == PKTPOOL_CB_MAX_AVL) {
++		err = BCME_ERROR;
++		goto done;
++	}
++
++	ASSERT(pktp->cbs[i].cb == NULL);
++	pktp->cbs[i].cb = cb;
++	pktp->cbs[i].arg = arg;
++	pktp->cbcnt++;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return err;
++}
++
++/** Registers callback functions */
++int
++pktpool_empty_register(pktpool_t *pktp, pktpool_cb_t cb, void *arg)
++{
++	int err = 0;
++	int i;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	ASSERT(cb != NULL);
++
++	i = pktp->ecbcnt;
++	if (i == PKTPOOL_CB_MAX) {
++		err = BCME_ERROR;
++		goto done;
++	}
++
++	ASSERT(pktp->ecbs[i].cb == NULL);
++	pktp->ecbs[i].cb = cb;
++	pktp->ecbs[i].arg = arg;
++	pktp->ecbcnt++;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return err;
++}
++
++/** Calls registered callback functions */
++static int
++pktpool_empty_notify(pktpool_t *pktp)
++{
++	int i;
++
++	pktp->empty = TRUE;
++	for (i = 0; i < pktp->ecbcnt; i++) {
++		ASSERT(pktp->ecbs[i].cb != NULL);
++		pktp->ecbs[i].cb(pktp, pktp->ecbs[i].arg);
++	}
++	pktp->empty = FALSE;
++
++	return 0;
++}
++
++#ifdef BCMDBG_POOL
++int
++pktpool_dbg_register(pktpool_t *pktp, pktpool_cb_t cb, void *arg)
++{
++	int err = 0;
++	int i;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	ASSERT(cb);
++
++	i = pktp->dbg_cbcnt;
++	if (i == PKTPOOL_CB_MAX) {
++		err = BCME_ERROR;
++		goto done;
++	}
++
++	ASSERT(pktp->dbg_cbs[i].cb == NULL);
++	pktp->dbg_cbs[i].cb = cb;
++	pktp->dbg_cbs[i].arg = arg;
++	pktp->dbg_cbcnt++;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return err;
++}
++
++int pktpool_dbg_notify(pktpool_t *pktp);
++
++int
++pktpool_dbg_notify(pktpool_t *pktp)
++{
++	int i;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	for (i = 0; i < pktp->dbg_cbcnt; i++) {
++		ASSERT(pktp->dbg_cbs[i].cb);
++		pktp->dbg_cbs[i].cb(pktp, pktp->dbg_cbs[i].arg);
++	}
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return 0;
++}
++
++int
++pktpool_dbg_dump(pktpool_t *pktp)
++{
++	int i;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	printf("pool len=%d maxlen=%d\n",  pktp->dbg_qlen, pktp->maxlen);
++	for (i = 0; i < pktp->dbg_qlen; i++) {
++		ASSERT(pktp->dbg_q[i].p);
++		printf("%d, p: 0x%x dur:%lu us state:%d\n", i,
++			pktp->dbg_q[i].p, pktp->dbg_q[i].dur/100, PKTPOOLSTATE(pktp->dbg_q[i].p));
++	}
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return 0;
++}
++
++int
++pktpool_stats_dump(pktpool_t *pktp, pktpool_stats_t *stats)
++{
++	int i;
++	int state;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	bzero(stats, sizeof(pktpool_stats_t));
++	for (i = 0; i < pktp->dbg_qlen; i++) {
++		ASSERT(pktp->dbg_q[i].p != NULL);
++
++		state = PKTPOOLSTATE(pktp->dbg_q[i].p);
++		switch (state) {
++			case POOL_TXENQ:
++				stats->enq++; break;
++			case POOL_TXDH:
++				stats->txdh++; break;
++			case POOL_TXD11:
++				stats->txd11++; break;
++			case POOL_RXDH:
++				stats->rxdh++; break;
++			case POOL_RXD11:
++				stats->rxd11++; break;
++			case POOL_RXFILL:
++				stats->rxfill++; break;
++			case POOL_IDLE:
++				stats->idle++; break;
++		}
++	}
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return 0;
++}
++
++int
++pktpool_start_trigger(pktpool_t *pktp, void *p)
++{
++	uint32 cycles, i;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	if (!PKTPOOL(OSH_NULL, p))
++		goto done;
++
++	OSL_GETCYCLES(cycles);
++
++	for (i = 0; i < pktp->dbg_qlen; i++) {
++		ASSERT(pktp->dbg_q[i].p != NULL);
++
++		if (pktp->dbg_q[i].p == p) {
++			pktp->dbg_q[i].cycles = cycles;
++			break;
++		}
++	}
++
++done:
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return 0;
++}
++
++int pktpool_stop_trigger(pktpool_t *pktp, void *p);
++
++int
++pktpool_stop_trigger(pktpool_t *pktp, void *p)
++{
++	uint32 cycles, i;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	if (!PKTPOOL(OSH_NULL, p))
++		goto done;
++
++	OSL_GETCYCLES(cycles);
++
++	for (i = 0; i < pktp->dbg_qlen; i++) {
++		ASSERT(pktp->dbg_q[i].p != NULL);
++
++		if (pktp->dbg_q[i].p == p) {
++			if (pktp->dbg_q[i].cycles == 0)
++				break;
++
++			if (cycles >= pktp->dbg_q[i].cycles)
++				pktp->dbg_q[i].dur = cycles - pktp->dbg_q[i].cycles;
++			else
++				pktp->dbg_q[i].dur =
++					(((uint32)-1) - pktp->dbg_q[i].cycles) + cycles + 1;
++
++			pktp->dbg_q[i].cycles = 0;
++			break;
++		}
++	}
++
++done:
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return 0;
++}
++#endif /* BCMDBG_POOL */
++
++int
++pktpool_avail_notify_normal(osl_t *osh, pktpool_t *pktp)
++{
++	BCM_REFERENCE(osh);
++	ASSERT(pktp);
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	pktp->availcb_excl = NULL;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return 0;
++}
++
++int
++pktpool_avail_notify_exclusive(osl_t *osh, pktpool_t *pktp, pktpool_cb_t cb)
++{
++	int i;
++	int err;
++	BCM_REFERENCE(osh);
++
++	ASSERT(pktp);
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	ASSERT(pktp->availcb_excl == NULL);
++	for (i = 0; i < pktp->cbcnt; i++) {
++		if (cb == pktp->cbs[i].cb) {
++			pktp->availcb_excl = &pktp->cbs[i];
++			break;
++		}
++	}
++
++	if (pktp->availcb_excl == NULL)
++		err = BCME_ERROR;
++	else
++		err = 0;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return err;
++}
++
++static void
++pktpool_avail_notify(pktpool_t *pktp)
++{
++	int i, k, idx;
++	int avail;
++
++	ASSERT(pktp);
++	if (pktp->availcb_excl != NULL) {
++		pktp->availcb_excl->cb(pktp, pktp->availcb_excl->arg);
++		return;
++	}
++
++	k = pktp->cbcnt - 1;
++	for (i = 0; i < pktp->cbcnt; i++) {
++		avail = pktp->avail;
++
++		if (avail) {
++			if (pktp->cbtoggle)
++				idx = i;
++			else
++				idx = k--;
++
++			ASSERT(pktp->cbs[idx].cb != NULL);
++			pktp->cbs[idx].cb(pktp, pktp->cbs[idx].arg);
++		}
++	}
++
++	/* Alternate between filling from head or tail
++	 */
++	pktp->cbtoggle ^= 1;
++
++	return;
++}
++
++/** Gets an empty packet from the caller provided pool */
++void *
++pktpool_get(pktpool_t *pktp)
++{
++	void *p;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++
++	p = pktpool_deq(pktp);
++
++	if (p == NULL) {
++		/* Notify and try to reclaim tx pkts */
++		if (pktp->ecbcnt)
++			pktpool_empty_notify(pktp);
++
++		p = pktpool_deq(pktp);
++		if (p == NULL)
++			goto done;
++	}
++
++
++done:
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void
++pktpool_free(pktpool_t *pktp, void *p)
++{
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return;
++
++	ASSERT(p != NULL);
++#ifdef BCMDBG_POOL
++	/* pktpool_stop_trigger(pktp, p); */
++#endif
++
++	pktpool_enq(pktp, p);
++
++	/**
++	 * Feed critical DMA with freshly freed packets, to avoid DMA starvation.
++	 * If any avail callback functions are registered, send a notification
++	 * that a new packet is available in the pool.
++	 */
++	if (pktp->cbcnt) {
++		/* To more efficiently use the cpu cycles, callbacks can be temporarily disabled.
++		 * This allows to feed on burst basis as opposed to inefficient per-packet basis.
++		 */
++		if (pktp->emptycb_disable == EMPTYCB_ENABLED) {
++			/**
++			 * If the call originated from pktpool_empty_notify, the just freed packet
++			 * is needed in pktpool_get.
++			 * Therefore don't call pktpool_avail_notify.
++			 */
++			if (pktp->empty == FALSE)
++				pktpool_avail_notify(pktp);
++		} else {
++			/**
++			 * The callback is temporarily disabled, log that a packet has been freed.
++			 */
++			pktp->emptycb_disable = EMPTYCB_SKIPPED;
++		}
++	}
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return;
++}
++
++/** Adds a caller provided (empty) packet to the caller provided pool */
++int
++pktpool_add(pktpool_t *pktp, void *p)
++{
++	int err = 0;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	ASSERT(p != NULL);
++
++	if (pktp->len == pktp->maxlen) {
++		err = BCME_RANGE;
++		goto done;
++	}
++
++	/* pkts in pool have same length */
++	ASSERT(pktp->plen == PKTLEN(OSH_NULL, p));
++	PKTSETPOOL(OSH_NULL, p, TRUE, pktp);
++
++	pktp->len++;
++	pktpool_enq(pktp, p);
++
++#ifdef BCMDBG_POOL
++	pktp->dbg_q[pktp->dbg_qlen++].p = p;
++#endif
++
++done:
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return err;
++}
++
++/**
++ * Force pktpool_setmaxlen () into RAM as it uses a constant
++ * (PKTPOOL_LEN_MAX) that may be changed post tapeout for ROM-based chips.
++ */
++int
++BCMRAMFN(pktpool_setmaxlen)(pktpool_t *pktp, uint16 maxlen)
++{
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	if (maxlen > PKTPOOL_LEN_MAX)
++		maxlen = PKTPOOL_LEN_MAX;
++
++	/* if pool is already beyond maxlen, then just cap it
++	 * since we currently do not reduce the pool len
++	 * already allocated
++	 */
++	pktp->maxlen = (pktp->len > maxlen) ? pktp->len : maxlen;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return pktp->maxlen;
++}
++
++void
++pktpool_emptycb_disable(pktpool_t *pktp, bool disable)
++{
++	ASSERT(pktp);
++
++	/**
++	 * To more efficiently use the cpu cycles, callbacks can be temporarily disabled.
++	 * If callback is going to be re-enabled, check if any packet got
++	 * freed and added back to the pool while callback was disabled.
++	 * When this is the case do the callback now, provided that callback functions
++	 * are registered and this call did not originate from pktpool_empty_notify.
++	 */
++	if ((!disable) && (pktp->cbcnt) && (pktp->empty == FALSE) &&
++		(pktp->emptycb_disable == EMPTYCB_SKIPPED)) {
++			pktpool_avail_notify(pktp);
++	}
++
++	/* Enable or temporarily disable callback when packet becomes available. */
++	pktp->emptycb_disable = disable ? EMPTYCB_DISABLED : EMPTYCB_ENABLED;
++}
++
++bool
++pktpool_emptycb_disabled(pktpool_t *pktp)
++{
++	ASSERT(pktp);
++	return pktp->emptycb_disable != EMPTYCB_ENABLED;
++}
++
++#ifdef BCMPKTPOOL
++#include <hnd_lbuf.h>
++
++pktpool_t *pktpool_shared = NULL;
++
++#ifdef BCMFRAGPOOL
++pktpool_t *pktpool_shared_lfrag = NULL;
++#endif /* BCMFRAGPOOL */
++
++pktpool_t *pktpool_shared_rxlfrag = NULL;
++
++static osl_t *pktpool_osh = NULL;
++
++/**
++ * Initializes several packet pools and allocates packets within those pools.
++ */
++int
++hnd_pktpool_init(osl_t *osh)
++{
++	int err;
++	int n;
++
++	/* Construct a packet pool registry before initializing packet pools */
++	n = pktpool_attach(osh, PKTPOOL_MAXIMUM_ID);
++	if (n != PKTPOOL_MAXIMUM_ID) {
++		ASSERT(0);
++		err = BCME_ERROR;
++		goto error0;
++	}
++
++	pktpool_shared = MALLOCZ(osh, sizeof(pktpool_t));
++	if (pktpool_shared == NULL) {
++		ASSERT(0);
++		err = BCME_NOMEM;
++		goto error1;
++	}
++
++#if defined(BCMFRAGPOOL) && !defined(BCMFRAGPOOL_DISABLED)
++	pktpool_shared_lfrag = MALLOCZ(osh, sizeof(pktpool_t));
++	if (pktpool_shared_lfrag == NULL) {
++		ASSERT(0);
++		err = BCME_NOMEM;
++		goto error2;
++	}
++#endif
++
++#if defined(BCMRXFRAGPOOL) && !defined(BCMRXFRAGPOOL_DISABLED)
++	pktpool_shared_rxlfrag = MALLOCZ(osh, sizeof(pktpool_t));
++	if (pktpool_shared_rxlfrag == NULL) {
++		ASSERT(0);
++		err = BCME_NOMEM;
++		goto error3;
++	}
++#endif
++
++
++	/*
++	 * At this early stage, there's not enough memory to allocate all
++	 * requested pkts in the shared pool.  Need to add to the pool
++	 * after reclaim
++	 *
++	 * n = NRXBUFPOST + SDPCMD_RXBUFS;
++	 *
++	 * Initialization of packet pools may fail (BCME_ERROR), if the packet pool
++	 * registry is not initialized or the registry is depleted.
++	 *
++	 * A BCME_NOMEM error only indicates that the requested number of packets
++	 * were not filled into the pool.
++	 */
++	n = 1;
++	if ((err = pktpool_init(osh, pktpool_shared,
++	                        &n, PKTBUFSZ, FALSE, lbuf_basic)) != BCME_OK) {
++		ASSERT(0);
++		goto error4;
++	}
++	pktpool_setmaxlen(pktpool_shared, SHARED_POOL_LEN);
++
++#if defined(BCMFRAGPOOL) && !defined(BCMFRAGPOOL_DISABLED)
++	n = 1;
++	if ((err = pktpool_init(osh, pktpool_shared_lfrag,
++	                        &n, PKTFRAGSZ, TRUE, lbuf_frag)) != BCME_OK) {
++		ASSERT(0);
++		goto error5;
++	}
++	pktpool_setmaxlen(pktpool_shared_lfrag, SHARED_FRAG_POOL_LEN);
++#endif
++#if defined(BCMRXFRAGPOOL) && !defined(BCMRXFRAGPOOL_DISABLED)
++	n = 1;
++	if ((err = pktpool_init(osh, pktpool_shared_rxlfrag,
++	                        &n, PKTRXFRAGSZ, TRUE, lbuf_rxfrag)) != BCME_OK) {
++		ASSERT(0);
++		goto error6;
++	}
++	pktpool_setmaxlen(pktpool_shared_rxlfrag, SHARED_RXFRAG_POOL_LEN);
++#endif
++
++	pktpool_osh = osh;
++
++	return BCME_OK;
++
++#if defined(BCMRXFRAGPOOL) && !defined(BCMRXFRAGPOOL_DISABLED)
++error6:
++#endif
++
++#if defined(BCMFRAGPOOL) && !defined(BCMFRAGPOOL_DISABLED)
++	pktpool_deinit(osh, pktpool_shared_lfrag);
++error5:
++#endif
++
++#if (defined(BCMRXFRAGPOOL) && !defined(BCMRXFRAGPOOL_DISABLED)) || \
++	(defined(BCMFRAGPOOL) && !defined(BCMFRAGPOOL_DISABLED))
++	pktpool_deinit(osh, pktpool_shared);
++#endif
++
++error4:
++#if defined(BCMRXFRAGPOOL) && !defined(BCMRXFRAGPOOL_DISABLED)
++	hnd_free(pktpool_shared_rxlfrag);
++	pktpool_shared_rxlfrag = (pktpool_t *)NULL;
++error3:
++#endif /* BCMRXFRAGPOOL */
++
++#if defined(BCMFRAGPOOL) && !defined(BCMFRAGPOOL_DISABLED)
++	hnd_free(pktpool_shared_lfrag);
++	pktpool_shared_lfrag = (pktpool_t *)NULL;
++error2:
++#endif /* BCMFRAGPOOL */
++
++	hnd_free(pktpool_shared);
++	pktpool_shared = (pktpool_t *)NULL;
++
++error1:
++	pktpool_dettach(osh);
++error0:
++	return err;
++} /* hnd_pktpool_init */
++
++int
++hnd_pktpool_fill(pktpool_t *pktpool, bool minimal)
++{
++	return (pktpool_fill(pktpool_osh, pktpool, minimal));
++}
++
++/** refills pktpools after reclaim */
++void
++hnd_pktpool_refill(bool minimal)
++{
++	if (POOL_ENAB(pktpool_shared)) {
++		pktpool_fill(pktpool_osh, pktpool_shared, minimal);
++	}
++/* fragpool reclaim */
++#ifdef BCMFRAGPOOL
++	if (POOL_ENAB(pktpool_shared_lfrag)) {
++#if defined(SRMEM)
++		if (SRMEM_ENAB()) {
++			int maxlen = pktpool_maxlen(pktpool_shared);
++			int len = pktpool_len(pktpool_shared);
++
++			for (; len < maxlen; len++)	{
++				void *p;
++				if ((p = PKTSRGET(pktpool_plen(pktpool_shared))) == NULL)
++					break;
++				pktpool_add(pktpool_shared, p);
++			}
++		}
++#endif /* SRMEM */
++		pktpool_fill(pktpool_osh, pktpool_shared_lfrag, minimal);
++	}
++#endif /* BCMFRAGPOOL */
++/* rx fragpool reclaim */
++#ifdef BCMRXFRAGPOOL
++	if (POOL_ENAB(pktpool_shared_rxlfrag)) {
++		pktpool_fill(pktpool_osh, pktpool_shared_rxlfrag, minimal);
++	}
++#endif
++}
++#endif /* BCMPKTPOOL */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/hnd_pktq.c b/module_drivers/drivers/net/wireless/bcmdhd/hnd_pktq.c
+new file mode 100644
+index 000000000..132b32135
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/hnd_pktq.c
+@@ -0,0 +1,973 @@
++/*
++ * HND generic pktq operation primitives
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: hnd_pktq.c 644628 2016-06-21 06:25:58Z $
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++#include <osl_ext.h>
++#include <bcmutils.h>
++#include <hnd_pktq.h>
++
++/* mutex macros for thread safe */
++#ifdef HND_PKTQ_THREAD_SAFE
++#define HND_PKTQ_MUTEX_CREATE(name, mutex)	osl_ext_mutex_create(name, mutex)
++#define HND_PKTQ_MUTEX_DELETE(mutex)		osl_ext_mutex_delete(mutex)
++#define HND_PKTQ_MUTEX_ACQUIRE(mutex, msec)	osl_ext_mutex_acquire(mutex, msec)
++#define HND_PKTQ_MUTEX_RELEASE(mutex)		osl_ext_mutex_release(mutex)
++#else
++#define HND_PKTQ_MUTEX_CREATE(name, mutex)	OSL_EXT_SUCCESS
++#define HND_PKTQ_MUTEX_DELETE(mutex)		OSL_EXT_SUCCESS
++#define HND_PKTQ_MUTEX_ACQUIRE(mutex, msec)	OSL_EXT_SUCCESS
++#define HND_PKTQ_MUTEX_RELEASE(mutex)		OSL_EXT_SUCCESS
++#endif /* */
++
++/*
++ * osl multiple-precedence packet queue
++ * hi_prec is always >= the number of the highest non-empty precedence
++ */
++void * BCMFASTPATH
++pktq_penq(struct pktq *pq, int prec, void *p)
++{
++	struct pktq_prec *q;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++	ASSERT(PKTLINK(p) == NULL);		/* queueing chains not allowed */
++
++	ASSERT(!pktq_full(pq));
++	ASSERT(!pktq_pfull(pq, prec));
++
++	q = &pq->q[prec];
++
++	if (q->head)
++		PKTSETLINK(q->tail, p);
++	else
++		q->head = p;
++
++	q->tail = p;
++	q->len++;
++
++	pq->len++;
++
++	if (pq->hi_prec < prec)
++		pq->hi_prec = (uint8)prec;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void * BCMFASTPATH
++pktq_penq_head(struct pktq *pq, int prec, void *p)
++{
++	struct pktq_prec *q;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++	ASSERT(PKTLINK(p) == NULL);		/* queueing chains not allowed */
++
++	ASSERT(!pktq_full(pq));
++	ASSERT(!pktq_pfull(pq, prec));
++
++	q = &pq->q[prec];
++
++	if (q->head == NULL)
++		q->tail = p;
++
++	PKTSETLINK(p, q->head);
++	q->head = p;
++	q->len++;
++
++	pq->len++;
++
++	if (pq->hi_prec < prec)
++		pq->hi_prec = (uint8)prec;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++/*
++ * Append spktq 'list' to the tail of pktq 'pq'
++ */
++void BCMFASTPATH
++pktq_append(struct pktq *pq, int prec, struct spktq *list)
++{
++	struct pktq_prec *q;
++	struct pktq_prec *list_q;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return;
++
++	list_q = &list->q[0];
++
++	/* empty list check */
++	if (list_q->head == NULL)
++		goto done;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++	ASSERT(PKTLINK(list_q->tail) == NULL);         /* terminated list */
++
++	ASSERT(!pktq_full(pq));
++	ASSERT(!pktq_pfull(pq, prec));
++
++	q = &pq->q[prec];
++
++	if (q->head)
++		PKTSETLINK(q->tail, list_q->head);
++	else
++		q->head = list_q->head;
++
++	q->tail = list_q->tail;
++	q->len += list_q->len;
++	pq->len += list_q->len;
++
++	if (pq->hi_prec < prec)
++		pq->hi_prec = (uint8)prec;
++
++	list_q->head = NULL;
++	list_q->tail = NULL;
++	list_q->len = 0;
++	list->len = 0;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return;
++}
++
++/*
++ * Prepend spktq 'list' to the head of pktq 'pq'
++ */
++void BCMFASTPATH
++pktq_prepend(struct pktq *pq, int prec, struct spktq *list)
++{
++	struct pktq_prec *q;
++	struct pktq_prec *list_q;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return;
++
++	list_q = &list->q[0];
++
++	/* empty list check */
++	if (list_q->head == NULL)
++		goto done;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++	ASSERT(PKTLINK(list_q->tail) == NULL);         /* terminated list */
++
++	ASSERT(!pktq_full(pq));
++	ASSERT(!pktq_pfull(pq, prec));
++
++	q = &pq->q[prec];
++
++	/* set the tail packet of list to point at the former pq head */
++	PKTSETLINK(list_q->tail, q->head);
++	/* the new q head is the head of list */
++	q->head = list_q->head;
++
++	/* If the q tail was non-null, then it stays as is.
++	 * If the q tail was null, it is now the tail of list
++	 */
++	if (q->tail == NULL) {
++		q->tail = list_q->tail;
++	}
++
++	q->len += list_q->len;
++	pq->len += list_q->len;
++
++	if (pq->hi_prec < prec)
++		pq->hi_prec = (uint8)prec;
++
++	list_q->head = NULL;
++	list_q->tail = NULL;
++	list_q->len = 0;
++	list->len = 0;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return;
++}
++
++void * BCMFASTPATH
++pktq_pdeq(struct pktq *pq, int prec)
++{
++	struct pktq_prec *q;
++	void *p;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	q = &pq->q[prec];
++
++	if ((p = q->head) == NULL)
++		goto done;
++
++	if ((q->head = PKTLINK(p)) == NULL)
++		q->tail = NULL;
++
++	q->len--;
++
++	pq->len--;
++
++	PKTSETLINK(p, NULL);
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void * BCMFASTPATH
++pktq_pdeq_prev(struct pktq *pq, int prec, void *prev_p)
++{
++	struct pktq_prec *q;
++	void *p = NULL;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	q = &pq->q[prec];
++
++	if (prev_p == NULL)
++		goto done;
++
++	if ((p = PKTLINK(prev_p)) == NULL)
++		goto done;
++
++	q->len--;
++
++	pq->len--;
++
++	PKTSETLINK(prev_p, PKTLINK(p));
++	PKTSETLINK(p, NULL);
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void * BCMFASTPATH
++pktq_pdeq_with_fn(struct pktq *pq, int prec, ifpkt_cb_t fn, int arg)
++{
++	struct pktq_prec *q;
++	void *p, *prev = NULL;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	q = &pq->q[prec];
++	p = q->head;
++
++	while (p) {
++		if (fn == NULL || (*fn)(p, arg)) {
++			break;
++		} else {
++			prev = p;
++			p = PKTLINK(p);
++		}
++	}
++	if (p == NULL)
++		goto done;
++
++	if (prev == NULL) {
++		if ((q->head = PKTLINK(p)) == NULL) {
++			q->tail = NULL;
++		}
++	} else {
++		PKTSETLINK(prev, PKTLINK(p));
++		if (q->tail == p) {
++			q->tail = prev;
++		}
++	}
++
++	q->len--;
++
++	pq->len--;
++
++	PKTSETLINK(p, NULL);
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void * BCMFASTPATH
++pktq_pdeq_tail(struct pktq *pq, int prec)
++{
++	struct pktq_prec *q;
++	void *p, *prev;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	q = &pq->q[prec];
++
++	if ((p = q->head) == NULL)
++		goto done;
++
++	for (prev = NULL; p != q->tail; p = PKTLINK(p))
++		prev = p;
++
++	if (prev)
++		PKTSETLINK(prev, NULL);
++	else
++		q->head = NULL;
++
++	q->tail = prev;
++	q->len--;
++
++	pq->len--;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++bool BCMFASTPATH
++pktq_pdel(struct pktq *pq, void *pktbuf, int prec)
++{
++	bool ret = FALSE;
++	struct pktq_prec *q;
++	void *p = NULL;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return FALSE;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	/* Should this just assert pktbuf? */
++	if (!pktbuf)
++		goto done;
++
++	q = &pq->q[prec];
++
++	if (q->head == pktbuf) {
++		if ((q->head = PKTLINK(pktbuf)) == NULL)
++			q->tail = NULL;
++	} else {
++		for (p = q->head; p && PKTLINK(p) != pktbuf; p = PKTLINK(p))
++			;
++		if (p == NULL)
++			goto done;
++
++		PKTSETLINK(p, PKTLINK(pktbuf));
++		if (q->tail == pktbuf)
++			q->tail = p;
++	}
++
++	q->len--;
++	pq->len--;
++	PKTSETLINK(pktbuf, NULL);
++	ret = TRUE;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return FALSE;
++
++	return ret;
++}
++
++static void
++_pktq_pfilter(struct pktq *pq, int prec, pktq_filter_t fltr, void* fltr_ctx,
++              defer_free_pkt_fn_t defer, void *defer_ctx)
++{
++	struct pktq_prec wq;
++	struct pktq_prec *q;
++	void *p;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return;
++
++	/* move the prec queue aside to a work queue */
++	q = &pq->q[prec];
++
++	wq = *q;
++
++	q->head = NULL;
++	q->tail = NULL;
++	q->len = 0;
++
++	pq->len -= wq.len;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return;
++
++	/* start with the head of the work queue */
++	while ((p = wq.head) != NULL) {
++		/* unlink the current packet from the list */
++		wq.head = PKTLINK(p);
++		PKTSETLINK(p, NULL);
++		wq.len--;
++
++		/* call the filter function on current packet */
++		ASSERT(fltr != NULL);
++		switch ((*fltr)(fltr_ctx, p)) {
++		case PKT_FILTER_NOACTION:
++			/* put this packet back */
++			pktq_penq(pq, prec, p);
++			break;
++
++		case PKT_FILTER_DELETE:
++			/* delete this packet */
++			ASSERT(defer != NULL);
++			(*defer)(defer_ctx, p);
++			break;
++
++		case PKT_FILTER_REMOVE:
++			/* pkt already removed from list */
++			break;
++
++		default:
++			ASSERT(0);
++			break;
++		}
++	}
++
++	ASSERT(wq.len == 0);
++}
++
++void
++pktq_pfilter(struct pktq *pq, int prec, pktq_filter_t fltr, void* fltr_ctx,
++	defer_free_pkt_fn_t defer, void *defer_ctx, flush_free_pkt_fn_t flush, void *flush_ctx)
++{
++	_pktq_pfilter(pq, prec, fltr, fltr_ctx, defer, defer_ctx);
++
++	ASSERT(flush != NULL);
++	(*flush)(flush_ctx);
++}
++
++void
++pktq_filter(struct pktq *pq, pktq_filter_t fltr, void* fltr_ctx,
++	defer_free_pkt_fn_t defer, void *defer_ctx, flush_free_pkt_fn_t flush, void *flush_ctx)
++{
++	bool filter = FALSE;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return;
++
++	/* Optimize if pktq len = 0, just return.
++	 * pktq len of 0 means pktq's prec q's are all empty.
++	 */
++	if (pq->len > 0) {
++		filter = TRUE;
++	}
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return;
++
++	if (filter) {
++		int prec;
++
++		PKTQ_PREC_ITER(pq, prec) {
++			_pktq_pfilter(pq, prec, fltr, fltr_ctx, defer, defer_ctx);
++		}
++
++		ASSERT(flush != NULL);
++		(*flush)(flush_ctx);
++	}
++}
++
++bool
++pktq_init(struct pktq *pq, int num_prec, int max_len)
++{
++	int prec;
++
++	if (HND_PKTQ_MUTEX_CREATE("pktq", &pq->mutex) != OSL_EXT_SUCCESS)
++		return FALSE;
++
++	ASSERT(num_prec > 0 && num_prec <= PKTQ_MAX_PREC);
++
++	/* pq is variable size; only zero out what's requested */
++	bzero(pq, OFFSETOF(struct pktq, q) + (sizeof(struct pktq_prec) * num_prec));
++
++	pq->num_prec = (uint16)num_prec;
++
++	pq->max = (uint16)max_len;
++
++	for (prec = 0; prec < num_prec; prec++)
++		pq->q[prec].max = pq->max;
++
++	return TRUE;
++}
++
++bool
++pktq_deinit(struct pktq *pq)
++{
++	BCM_REFERENCE(pq);
++	if (HND_PKTQ_MUTEX_DELETE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return FALSE;
++
++	return TRUE;
++}
++
++void
++pktq_set_max_plen(struct pktq *pq, int prec, int max_len)
++{
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return;
++
++	if (prec < pq->num_prec)
++		pq->q[prec].max = (uint16)max_len;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return;
++}
++
++void * BCMFASTPATH
++pktq_deq(struct pktq *pq, int *prec_out)
++{
++	struct pktq_prec *q;
++	void *p = NULL;
++	int prec;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	if (pq->len == 0)
++		goto done;
++
++	while ((prec = pq->hi_prec) > 0 && pq->q[prec].head == NULL)
++		pq->hi_prec--;
++
++	q = &pq->q[prec];
++
++	if ((p = q->head) == NULL)
++		goto done;
++
++	if ((q->head = PKTLINK(p)) == NULL)
++		q->tail = NULL;
++
++	q->len--;
++
++	pq->len--;
++
++	if (prec_out)
++		*prec_out = prec;
++
++	PKTSETLINK(p, NULL);
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void * BCMFASTPATH
++pktq_deq_tail(struct pktq *pq, int *prec_out)
++{
++	struct pktq_prec *q;
++	void *p = NULL, *prev;
++	int prec;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	if (pq->len == 0)
++		goto done;
++
++	for (prec = 0; prec < pq->hi_prec; prec++)
++		if (pq->q[prec].head)
++			break;
++
++	q = &pq->q[prec];
++
++	if ((p = q->head) == NULL)
++		goto done;
++
++	for (prev = NULL; p != q->tail; p = PKTLINK(p))
++		prev = p;
++
++	if (prev)
++		PKTSETLINK(prev, NULL);
++	else
++		q->head = NULL;
++
++	q->tail = prev;
++	q->len--;
++
++	pq->len--;
++
++	if (prec_out)
++		*prec_out = prec;
++
++	PKTSETLINK(p, NULL);
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void *
++pktq_peek(struct pktq *pq, int *prec_out)
++{
++	int prec;
++	void *p = NULL;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	if (pq->len == 0)
++		goto done;
++
++	while ((prec = pq->hi_prec) > 0 && pq->q[prec].head == NULL)
++		pq->hi_prec--;
++
++	if (prec_out)
++		*prec_out = prec;
++
++	p = pq->q[prec].head;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void *
++pktq_peek_tail(struct pktq *pq, int *prec_out)
++{
++	int prec;
++	void *p = NULL;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	if (pq->len == 0)
++		goto done;
++
++	for (prec = 0; prec < pq->hi_prec; prec++)
++		if (pq->q[prec].head)
++			break;
++
++	if (prec_out)
++		*prec_out = prec;
++
++	p = pq->q[prec].tail;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void
++pktq_pflush(osl_t *osh, struct pktq *pq, int prec, bool dir)
++{
++	void *p;
++
++	/* no need for a mutex protection! */
++
++	/* start with the head of the list */
++	while ((p = pktq_pdeq(pq, prec)) != NULL) {
++
++		/* delete this packet */
++		PKTFREE(osh, p, dir);
++	}
++}
++
++void
++pktq_flush(osl_t *osh, struct pktq *pq, bool dir)
++{
++	bool flush = FALSE;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return;
++
++	/* Optimize flush, if pktq len = 0, just return.
++	 * pktq len of 0 means pktq's prec q's are all empty.
++	 */
++	if (pq->len > 0) {
++		flush = TRUE;
++	}
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return;
++
++	if (flush) {
++		int prec;
++
++		PKTQ_PREC_ITER(pq, prec) {
++			pktq_pflush(osh, pq, prec, dir);
++		}
++	}
++}
++
++/* Return sum of lengths of a specific set of precedences */
++int
++pktq_mlen(struct pktq *pq, uint prec_bmp)
++{
++	int prec, len;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return 0;
++
++	len = 0;
++
++	for (prec = 0; prec <= pq->hi_prec; prec++)
++		if (prec_bmp & (1 << prec))
++			len += pq->q[prec].len;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return 0;
++
++	return len;
++}
++
++/* Priority peek from a specific set of precedences */
++void * BCMFASTPATH
++pktq_mpeek(struct pktq *pq, uint prec_bmp, int *prec_out)
++{
++	struct pktq_prec *q;
++	void *p = NULL;
++	int prec;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	if (pq->len == 0)
++		goto done;
++
++	while ((prec = pq->hi_prec) > 0 && pq->q[prec].head == NULL)
++		pq->hi_prec--;
++
++	while ((prec_bmp & (1 << prec)) == 0 || pq->q[prec].head == NULL)
++		if (prec-- == 0)
++			goto done;
++
++	q = &pq->q[prec];
++
++	if ((p = q->head) == NULL)
++		goto done;
++
++	if (prec_out)
++		*prec_out = prec;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++/* Priority dequeue from a specific set of precedences */
++void * BCMFASTPATH
++pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out)
++{
++	struct pktq_prec *q;
++	void *p = NULL;
++	int prec;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	if (pq->len == 0)
++		goto done;
++
++	while ((prec = pq->hi_prec) > 0 && pq->q[prec].head == NULL)
++		pq->hi_prec--;
++
++	while ((pq->q[prec].head == NULL) || ((prec_bmp & (1 << prec)) == 0))
++		if (prec-- == 0)
++			goto done;
++
++	q = &pq->q[prec];
++
++	if ((p = q->head) == NULL)
++		goto done;
++
++	if ((q->head = PKTLINK(p)) == NULL)
++		q->tail = NULL;
++
++	q->len--;
++
++	// terence 20150308: fix for non-null pointer of skb->prev sent from ndo_start_xmit
++	if (q->len == 0) {
++		q->head = NULL;
++		q->tail = NULL;
++	}
++
++	if (prec_out)
++		*prec_out = prec;
++
++	pq->len--;
++
++	PKTSETLINK(p, NULL);
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++#ifdef HND_PKTQ_THREAD_SAFE
++int
++pktq_pavail(struct pktq *pq, int prec)
++{
++	int ret;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return 0;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	ret = pq->q[prec].max - pq->q[prec].len;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return 0;
++
++	return ret;
++}
++
++bool
++pktq_pfull(struct pktq *pq, int prec)
++{
++	bool ret;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return FALSE;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	ret = pq->q[prec].len >= pq->q[prec].max;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return FALSE;
++
++	return ret;
++}
++
++int
++pktq_avail(struct pktq *pq)
++{
++	int ret;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return 0;
++
++	ret = pq->max - pq->len;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return 0;
++
++	return ret;
++}
++
++bool
++pktq_full(struct pktq *pq)
++{
++	bool ret;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return FALSE;
++
++	ret = pq->len >= pq->max;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return FALSE;
++
++	return ret;
++}
++#endif	/* HND_PKTQ_THREAD_SAFE */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/hndpmu.c b/module_drivers/drivers/net/wireless/bcmdhd/hndpmu.c
+new file mode 100644
+index 000000000..c76a943da
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/hndpmu.c
+@@ -0,0 +1,382 @@
++/*
++ * Misc utility routines for accessing PMU corerev specific features
++ * of the SiliconBackplane-based Broadcom chips.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: hndpmu.c 657872 2016-09-02 22:17:34Z $
++ */
++
++
++/*
++ * Note: this file contains PLL/FLL related functions. A chip can contain multiple PLLs/FLLs.
++ * However, in the context of this file the baseband ('BB') PLL/FLL is referred to.
++ *
++ * Throughout this code, the prefixes 'pmu0_', 'pmu1_' and 'pmu2_' are used.
++ * They refer to different revisions of the PMU (which is at revision 18 @ Apr 25, 2012)
++ * pmu1_ marks the transition from PLL to ADFLL (Digital Frequency Locked Loop). It supports
++ * fractional frequency generation. pmu2_ does not support fractional frequency generation.
++ */
++
++#include <bcm_cfg.h>
++#include <typedefs.h>
++#include <bcmdefs.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <siutils.h>
++#include <bcmdevs.h>
++#include <hndsoc.h>
++#include <sbchipc.h>
++#include <hndpmu.h>
++#if defined(BCMULP)
++#include <ulp.h>
++#endif /* defined(BCMULP) */
++#include <sbgci.h>
++#ifdef EVENT_LOG_COMPILE
++#include <event_log.h>
++#endif
++#include <sbgci.h>
++
++#define	PMU_ERROR(args)
++
++#define	PMU_MSG(args)
++
++/* To check in verbose debugging messages not intended
++ * to be on except on private builds.
++ */
++#define	PMU_NONE(args)
++
++/** contains resource bit positions for a specific chip */
++struct rsc_per_chip_s {
++	uint8 ht_avail;
++	uint8 macphy_clkavail;
++	uint8 ht_start;
++	uint8 otp_pu;
++};
++
++typedef struct rsc_per_chip_s rsc_per_chip_t;
++
++
++/* SDIO Pad drive strength to select value mappings.
++ * The last strength value in each table must be 0 (the tri-state value).
++ */
++typedef struct {
++	uint8 strength;			/* Pad Drive Strength in mA */
++	uint8 sel;			/* Chip-specific select value */
++} sdiod_drive_str_t;
++
++/* SDIO Drive Strength to sel value table for PMU Rev 1 */
++static const sdiod_drive_str_t sdiod_drive_strength_tab1[] = {
++	{4, 0x2},
++	{2, 0x3},
++	{1, 0x0},
++	{0, 0x0} };
++
++/* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
++static const sdiod_drive_str_t sdiod_drive_strength_tab2[] = {
++	{12, 0x7},
++	{10, 0x6},
++	{8, 0x5},
++	{6, 0x4},
++	{4, 0x2},
++	{2, 0x1},
++	{0, 0x0} };
++
++
++/* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
++static const sdiod_drive_str_t sdiod_drive_strength_tab3[] = {
++	{32, 0x7},
++	{26, 0x6},
++	{22, 0x5},
++	{16, 0x4},
++	{12, 0x3},
++	{8, 0x2},
++	{4, 0x1},
++	{0, 0x0} };
++
++/* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8v) */
++static const sdiod_drive_str_t sdiod_drive_strength_tab4_1v8[] = {
++	{32, 0x6},
++	{26, 0x7},
++	{22, 0x4},
++	{16, 0x5},
++	{12, 0x2},
++	{8, 0x3},
++	{4, 0x0},
++	{0, 0x1} };
++
++/* SDIO Drive Strength to sel value table for PMU Rev 11 (1.2v) */
++
++/* SDIO Drive Strength to sel value table for PMU Rev 11 (2.5v) */
++
++/* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
++static const sdiod_drive_str_t sdiod_drive_strength_tab5_1v8[] = {
++	{6, 0x7},
++	{5, 0x6},
++	{4, 0x5},
++	{3, 0x4},
++	{2, 0x2},
++	{1, 0x1},
++	{0, 0x0} };
++
++/* SDIO Drive Strength to sel value table for PMU Rev 13 (3.3v) */
++
++/** SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
++static const sdiod_drive_str_t sdiod_drive_strength_tab6_1v8[] = {
++	{3, 0x3},
++	{2, 0x2},
++	{1, 0x1},
++	{0, 0x0} };
++
++
++/**
++ * SDIO Drive Strength to sel value table for 43143 PMU Rev 17, see Confluence 43143 Toplevel
++ * architecture page, section 'PMU Chip Control 1 Register definition', click link to picture
++ * BCM43143_sel_sdio_signals.jpg. Valid after PMU Chip Control 0 Register, bit31 (override) has
++ * been written '1'.
++ */
++#if !defined(BCM_SDIO_VDDIO) || BCM_SDIO_VDDIO == 33
++
++static const sdiod_drive_str_t sdiod_drive_strength_tab7_3v3[] = {
++	/* note: for 14, 10, 6 and 2mA hw timing is not met according to rtl team */
++	{16, 0x7},
++	{12, 0x5},
++	{8,  0x3},
++	{4,  0x1} }; /* note: 43143 does not support tristate */
++
++#else
++
++static const sdiod_drive_str_t sdiod_drive_strength_tab7_1v8[] = {
++	/* note: for 7, 5, 3 and 1mA hw timing is not met according to rtl team */
++	{8, 0x7},
++	{6, 0x5},
++	{4,  0x3},
++	{2,  0x1} }; /* note: 43143 does not support tristate */
++
++#endif /* BCM_SDIO_VDDIO */
++
++#define SDIOD_DRVSTR_KEY(chip, pmu)	(((chip) << 16) | (pmu))
++
++/**
++ * Balance between stable SDIO operation and power consumption is achieved using this function.
++ * Note that each drive strength table is for a specific VDDIO of the SDIO pads, ideally this
++ * function should read the VDDIO itself to select the correct table. For now it has been solved
++ * with the 'BCM_SDIO_VDDIO' preprocessor constant.
++ *
++ * 'drivestrength': desired pad drive strength in mA. Drive strength of 0 requests tri-state (if
++ *		    hardware supports this), if no hw support drive strength is not programmed.
++ */
++void
++si_sdiod_drive_strength_init(si_t *sih, osl_t *osh, uint32 drivestrength)
++{
++	sdiod_drive_str_t *str_tab = NULL;
++	uint32 str_mask = 0;	/* only alter desired bits in PMU chipcontrol 1 register */
++	uint32 str_shift = 0;
++	uint32 str_ovr_pmuctl = PMU_CHIPCTL0; /* PMU chipcontrol register containing override bit */
++	uint32 str_ovr_pmuval = 0;            /* position of bit within this register */
++	pmuregs_t *pmu;
++	uint origidx;
++
++	if (!(sih->cccaps & CC_CAP_PMU)) {
++		return;
++	}
++	BCM_REFERENCE(sdiod_drive_strength_tab1);
++	BCM_REFERENCE(sdiod_drive_strength_tab2);
++	/* Remember original core before switch to chipc/pmu */
++	origidx = si_coreidx(sih);
++	if (AOB_ENAB(sih)) {
++		pmu = si_setcore(sih, PMU_CORE_ID, 0);
++	} else {
++		pmu = si_setcoreidx(sih, SI_CC_IDX);
++	}
++	ASSERT(pmu != NULL);
++
++	switch (SDIOD_DRVSTR_KEY(CHIPID(sih->chip), PMUREV(sih->pmurev))) {
++	case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
++	case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 11):
++		if (PMUREV(sih->pmurev) == 8) {
++			str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab3;
++		} else if (PMUREV(sih->pmurev) == 11) {
++			str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab4_1v8;
++		}
++		str_mask = 0x00003800;
++		str_shift = 11;
++		break;
++	case SDIOD_DRVSTR_KEY(BCM4330_CHIP_ID, 12):
++		str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab4_1v8;
++		str_mask = 0x00003800;
++		str_shift = 11;
++		break;
++	case SDIOD_DRVSTR_KEY(BCM43362_CHIP_ID, 13):
++		str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab5_1v8;
++		str_mask = 0x00003800;
++		str_shift = 11;
++		break;
++	case SDIOD_DRVSTR_KEY(BCM4334_CHIP_ID, 17):
++		str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab6_1v8;
++		str_mask = 0x00001800;
++		str_shift = 11;
++		break;
++	case SDIOD_DRVSTR_KEY(BCM43143_CHIP_ID, 17):
++#if !defined(BCM_SDIO_VDDIO) || BCM_SDIO_VDDIO == 33
++		if (drivestrength >=  ARRAYLAST(sdiod_drive_strength_tab7_3v3)->strength) {
++			str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab7_3v3;
++		}
++#else
++		if (drivestrength >=  ARRAYLAST(sdiod_drive_strength_tab7_1v8)->strength) {
++			str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab7_1v8;
++		}
++#endif /* BCM_SDIO_VDDIO */
++		str_mask = 0x00000007;
++		str_ovr_pmuval = PMU43143_CC0_SDIO_DRSTR_OVR;
++		break;
++	default:
++		PMU_MSG(("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
++		         bcm_chipname(
++			 CHIPID(sih->chip), chn, 8), CHIPREV(sih->chiprev), PMUREV(sih->pmurev)));
++		break;
++	}
++
++	if (str_tab != NULL) {
++		uint32 cc_data_temp;
++		int i;
++
++		/* Pick the lowest available drive strength equal or greater than the
++		 * requested strength.	Drive strength of 0 requests tri-state.
++		 */
++		for (i = 0; drivestrength < str_tab[i].strength; i++)
++			;
++
++		if (i > 0 && drivestrength > str_tab[i].strength)
++			i--;
++
++		W_REG(osh, &pmu->chipcontrol_addr, PMU_CHIPCTL1);
++		cc_data_temp = R_REG(osh, &pmu->chipcontrol_data);
++		cc_data_temp &= ~str_mask;
++		cc_data_temp |= str_tab[i].sel << str_shift;
++		W_REG(osh, &pmu->chipcontrol_data, cc_data_temp);
++		if (str_ovr_pmuval) { /* enables the selected drive strength */
++			W_REG(osh,  &pmu->chipcontrol_addr, str_ovr_pmuctl);
++			OR_REG(osh, &pmu->chipcontrol_data, str_ovr_pmuval);
++		}
++		PMU_MSG(("SDIO: %dmA drive strength requested; set to %dmA\n",
++		         drivestrength, str_tab[i].strength));
++	}
++
++	/* Return to original core */
++	si_setcoreidx(sih, origidx);
++} /* si_sdiod_drive_strength_init */
++
++
++#if defined(BCMULP)
++int
++si_pmu_ulp_register(si_t *sih)
++{
++	return ulp_p1_module_register(ULP_MODULE_ID_PMU, &ulp_pmu_ctx, (void *)sih);
++}
++
++static uint
++si_pmu_ulp_get_retention_size_cb(void *handle, ulp_ext_info_t *einfo)
++{
++	ULP_DBG(("%s: sz: %d\n", __FUNCTION__, sizeof(si_pmu_ulp_cr_dat_t)));
++	return sizeof(si_pmu_ulp_cr_dat_t);
++}
++
++static int
++si_pmu_ulp_enter_cb(void *handle, ulp_ext_info_t *einfo, uint8 *cache_data)
++{
++	si_pmu_ulp_cr_dat_t crinfo = {0};
++	crinfo.ilpcycles_per_sec = ilpcycles_per_sec;
++	ULP_DBG(("%s: ilpcycles_per_sec: %x\n", __FUNCTION__, ilpcycles_per_sec));
++	memcpy(cache_data, (void*)&crinfo, sizeof(crinfo));
++	return BCME_OK;
++}
++
++static int
++si_pmu_ulp_exit_cb(void *handle, uint8 *cache_data,
++	uint8 *p2_cache_data)
++{
++	si_pmu_ulp_cr_dat_t *crinfo = (si_pmu_ulp_cr_dat_t *)cache_data;
++
++	ilpcycles_per_sec = crinfo->ilpcycles_per_sec;
++	ULP_DBG(("%s: ilpcycles_per_sec: %x, cache_data: %p\n", __FUNCTION__,
++		ilpcycles_per_sec, cache_data));
++	return BCME_OK;
++}
++
++void
++si_pmu_ulp_ilp_config(si_t *sih, osl_t *osh, uint32 ilp_period)
++{
++	pmuregs_t *pmu;
++	pmu = si_setcoreidx(sih, si_findcoreidx(sih, PMU_CORE_ID, 0));
++	W_REG(osh, &pmu->ILPPeriod, ilp_period);
++}
++#endif /* defined(BCMULP) */
++
++
++
++void si_pmu_set_min_res_mask(si_t *sih, osl_t *osh, uint min_res_mask)
++{
++	pmuregs_t *pmu;
++	uint origidx;
++
++	/* Remember original core before switch to chipc/pmu */
++	origidx = si_coreidx(sih);
++	if (AOB_ENAB(sih)) {
++		pmu = si_setcore(sih, PMU_CORE_ID, 0);
++	}
++	else {
++		pmu = si_setcoreidx(sih, SI_CC_IDX);
++	}
++	ASSERT(pmu != NULL);
++
++	W_REG(osh, &pmu->min_res_mask, min_res_mask);
++	OSL_DELAY(100);
++
++	/* Return to original core */
++	si_setcoreidx(sih, origidx);
++}
++
++bool
++si_pmu_cap_fast_lpo(si_t *sih)
++{
++	return (PMU_REG(sih, core_cap_ext, 0, 0) & PCAP_EXT_USE_MUXED_ILP_CLK_MASK) ? TRUE : FALSE;
++}
++
++int
++si_pmu_fast_lpo_disable(si_t *sih)
++{
++	if (!si_pmu_cap_fast_lpo(sih)) {
++		PMU_ERROR(("%s: No Fast LPO capability\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	PMU_REG(sih, pmucontrol_ext,
++		PCTL_EXT_FASTLPO_ENAB |
++		PCTL_EXT_FASTLPO_SWENAB |
++		PCTL_EXT_FASTLPO_PCIE_SWENAB,
++		0);
++	OSL_DELAY(1000);
++	return BCME_OK;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/802.11.h b/module_drivers/drivers/net/wireless/bcmdhd/include/802.11.h
+new file mode 100644
+index 000000000..f2847ecbe
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/802.11.h
+@@ -0,0 +1,5128 @@
++/*
++ * Fundamental types and constants relating to 802.11
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: 802.11.h 700693 2017-05-20 20:29:07Z $
++ */
++
++#ifndef _802_11_H_
++#define _802_11_H_
++
++#ifndef _TYPEDEFS_H_
++#include <typedefs.h>
++#endif
++
++#ifndef _NET_ETHERNET_H_
++#include <ethernet.h>
++#endif
++
++#include <wpa.h>
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++
++
++#define DOT11_TU_TO_US			1024	/* 802.11 Time Unit is 1024 microseconds */
++
++/* Generic 802.11 frame constants */
++#define DOT11_A3_HDR_LEN		24	/* d11 header length with A3 */
++#define DOT11_A4_HDR_LEN		30	/* d11 header length with A4 */
++#define DOT11_MAC_HDR_LEN		DOT11_A3_HDR_LEN	/* MAC header length */
++#define DOT11_FCS_LEN			4	/* d11 FCS length */
++#define DOT11_ICV_LEN			4	/* d11 ICV length */
++#define DOT11_ICV_AES_LEN		8	/* d11 ICV/AES length */
++#define DOT11_QOS_LEN			2	/* d11 QoS length */
++#define DOT11_HTC_LEN			4	/* d11 HT Control field length */
++
++#define DOT11_KEY_INDEX_SHIFT		6	/* d11 key index shift */
++#define DOT11_IV_LEN			4	/* d11 IV length */
++#define DOT11_IV_TKIP_LEN		8	/* d11 IV TKIP length */
++#define DOT11_IV_AES_OCB_LEN		4	/* d11 IV/AES/OCB length */
++#define DOT11_IV_AES_CCM_LEN		8	/* d11 IV/AES/CCM length */
++#define DOT11_IV_MAX_LEN		8	/* maximum iv len for any encryption */
++
++/* Includes MIC */
++#define DOT11_MAX_MPDU_BODY_LEN		2304	/* max MPDU body length */
++/* A4 header + QoS + CCMP + PDU + ICV + FCS = 2352 */
++#define DOT11_MAX_MPDU_LEN		(DOT11_A4_HDR_LEN + \
++					 DOT11_QOS_LEN + \
++					 DOT11_IV_AES_CCM_LEN + \
++					 DOT11_MAX_MPDU_BODY_LEN + \
++					 DOT11_ICV_LEN + \
++					 DOT11_FCS_LEN)	/* d11 max MPDU length */
++
++#define DOT11_MAX_SSID_LEN		32	/* d11 max ssid length */
++
++/* dot11RTSThreshold */
++#define DOT11_DEFAULT_RTS_LEN		2347	/* d11 default RTS length */
++#define DOT11_MAX_RTS_LEN		2347	/* d11 max RTS length */
++
++/* dot11FragmentationThreshold */
++#define DOT11_MIN_FRAG_LEN		256	/* d11 min fragmentation length */
++#define DOT11_MAX_FRAG_LEN		2346	/* Max frag is also limited by aMPDUMaxLength
++						* of the attached PHY
++						*/
++#define DOT11_DEFAULT_FRAG_LEN		2346	/* d11 default fragmentation length */
++
++/* dot11BeaconPeriod */
++#define DOT11_MIN_BEACON_PERIOD		1	/* d11 min beacon period */
++#define DOT11_MAX_BEACON_PERIOD		0xFFFF	/* d11 max beacon period */
++
++/* dot11DTIMPeriod */
++#define DOT11_MIN_DTIM_PERIOD		1	/* d11 min DTIM period */
++#define DOT11_MAX_DTIM_PERIOD		0xFF	/* d11 max DTIM period */
++
++/** 802.2 LLC/SNAP header used by 802.11 per 802.1H */
++#define DOT11_LLC_SNAP_HDR_LEN		8	/* d11 LLC/SNAP header length */
++/* minimum LLC header length; DSAP, SSAP, 8 bit Control (unnumbered) */
++#define DOT11_LLC_HDR_LEN_MIN		3
++#define DOT11_OUI_LEN			3	/* d11 OUI length */
++BWL_PRE_PACKED_STRUCT struct dot11_llc_snap_header {
++	uint8	dsap;				/* always 0xAA */
++	uint8	ssap;				/* always 0xAA */
++	uint8	ctl;				/* always 0x03 */
++	uint8	oui[DOT11_OUI_LEN];		/* RFC1042: 0x00 0x00 0x00
++						 * Bridge-Tunnel: 0x00 0x00 0xF8
++						 */
++	uint16	type;				/* ethertype */
++} BWL_POST_PACKED_STRUCT;
++
++/* RFC1042 header used by 802.11 per 802.1H */
++#define RFC1042_HDR_LEN	(ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN)	/* RCF1042 header length */
++
++/* Generic 802.11 MAC header */
++/**
++ * N.B.: This struct reflects the full 4 address 802.11 MAC header.
++ *		 The fields are defined such that the shorter 1, 2, and 3
++ *		 address headers just use the first k fields.
++ */
++BWL_PRE_PACKED_STRUCT struct dot11_header {
++	uint16			fc;		/* frame control */
++	uint16			durid;		/* duration/ID */
++	struct ether_addr	a1;		/* address 1 */
++	struct ether_addr	a2;		/* address 2 */
++	struct ether_addr	a3;		/* address 3 */
++	uint16			seq;		/* sequence control */
++	struct ether_addr	a4;		/* address 4 */
++} BWL_POST_PACKED_STRUCT;
++
++/* Control frames */
++
++BWL_PRE_PACKED_STRUCT struct dot11_rts_frame {
++	uint16			fc;		/* frame control */
++	uint16			durid;		/* duration/ID */
++	struct ether_addr	ra;		/* receiver address */
++	struct ether_addr	ta;		/* transmitter address */
++} BWL_POST_PACKED_STRUCT;
++#define	DOT11_RTS_LEN		16		/* d11 RTS frame length */
++
++BWL_PRE_PACKED_STRUCT struct dot11_cts_frame {
++	uint16			fc;		/* frame control */
++	uint16			durid;		/* duration/ID */
++	struct ether_addr	ra;		/* receiver address */
++} BWL_POST_PACKED_STRUCT;
++#define	DOT11_CTS_LEN		10		/* d11 CTS frame length */
++
++BWL_PRE_PACKED_STRUCT struct dot11_ack_frame {
++	uint16			fc;		/* frame control */
++	uint16			durid;		/* duration/ID */
++	struct ether_addr	ra;		/* receiver address */
++} BWL_POST_PACKED_STRUCT;
++#define	DOT11_ACK_LEN		10		/* d11 ACK frame length */
++
++BWL_PRE_PACKED_STRUCT struct dot11_ps_poll_frame {
++	uint16			fc;		/* frame control */
++	uint16			durid;		/* AID */
++	struct ether_addr	bssid;		/* receiver address, STA in AP */
++	struct ether_addr	ta;		/* transmitter address */
++} BWL_POST_PACKED_STRUCT;
++#define	DOT11_PS_POLL_LEN	16		/* d11 PS poll frame length */
++
++BWL_PRE_PACKED_STRUCT struct dot11_cf_end_frame {
++	uint16			fc;		/* frame control */
++	uint16			durid;		/* duration/ID */
++	struct ether_addr	ra;		/* receiver address */
++	struct ether_addr	bssid;		/* transmitter address, STA in AP */
++} BWL_POST_PACKED_STRUCT;
++#define	DOT11_CS_END_LEN	16		/* d11 CF-END frame length */
++
++/**
++ * RWL wifi protocol: The Vendor Specific Action frame is defined for vendor-specific signaling
++ *  category+OUI+vendor specific content ( this can be variable)
++ */
++BWL_PRE_PACKED_STRUCT struct dot11_action_wifi_vendor_specific {
++	uint8	category;
++	uint8	OUI[3];
++	uint8	type;
++	uint8	subtype;
++	uint8	data[1040];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_action_wifi_vendor_specific dot11_action_wifi_vendor_specific_t;
++
++/** generic vendor specific action frame with variable length */
++BWL_PRE_PACKED_STRUCT struct dot11_action_vs_frmhdr {
++	uint8	category;
++	uint8	OUI[3];
++	uint8	type;
++	uint8	subtype;
++	uint8	data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_action_vs_frmhdr dot11_action_vs_frmhdr_t;
++
++#define DOT11_ACTION_VS_HDR_LEN	6
++
++#define BCM_ACTION_OUI_BYTE0	0x00
++#define BCM_ACTION_OUI_BYTE1	0x90
++#define BCM_ACTION_OUI_BYTE2	0x4c
++
++/* BA/BAR Control parameters */
++#define DOT11_BA_CTL_POLICY_NORMAL	0x0000	/* normal ack */
++#define DOT11_BA_CTL_POLICY_NOACK	0x0001	/* no ack */
++#define DOT11_BA_CTL_POLICY_MASK	0x0001	/* ack policy mask */
++
++#define DOT11_BA_CTL_MTID		0x0002	/* multi tid BA */
++#define DOT11_BA_CTL_COMPRESSED		0x0004	/* compressed bitmap */
++
++#define DOT11_BA_CTL_NUMMSDU_MASK	0x0FC0	/* num msdu in bitmap mask */
++#define DOT11_BA_CTL_NUMMSDU_SHIFT	6	/* num msdu in bitmap shift */
++
++#define DOT11_BA_CTL_TID_MASK		0xF000	/* tid mask */
++#define DOT11_BA_CTL_TID_SHIFT		12	/* tid shift */
++
++/** control frame header (BA/BAR) */
++BWL_PRE_PACKED_STRUCT struct dot11_ctl_header {
++	uint16			fc;		/* frame control */
++	uint16			durid;		/* duration/ID */
++	struct ether_addr	ra;		/* receiver address */
++	struct ether_addr	ta;		/* transmitter address */
++} BWL_POST_PACKED_STRUCT;
++#define DOT11_CTL_HDR_LEN	16		/* control frame hdr len */
++
++/** BAR frame payload */
++BWL_PRE_PACKED_STRUCT struct dot11_bar {
++	uint16			bar_control;	/* BAR Control */
++	uint16			seqnum;		/* Starting Sequence control */
++} BWL_POST_PACKED_STRUCT;
++#define DOT11_BAR_LEN		4		/* BAR frame payload length */
++
++#define DOT11_BA_BITMAP_LEN	128		/* bitmap length */
++#define DOT11_BA_CMP_BITMAP_LEN	8		/* compressed bitmap length */
++/** BA frame payload */
++BWL_PRE_PACKED_STRUCT struct dot11_ba {
++	uint16			ba_control;	/* BA Control */
++	uint16			seqnum;		/* Starting Sequence control */
++	uint8			bitmap[DOT11_BA_BITMAP_LEN];	/* Block Ack Bitmap */
++} BWL_POST_PACKED_STRUCT;
++#define DOT11_BA_LEN		4		/* BA frame payload len (wo bitmap) */
++
++/** Management frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_management_header {
++	uint16			fc;		/* frame control */
++	uint16			durid;		/* duration/ID */
++	struct ether_addr	da;		/* receiver address */
++	struct ether_addr	sa;		/* transmitter address */
++	struct ether_addr	bssid;		/* BSS ID */
++	uint16			seq;		/* sequence control */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_management_header dot11_management_header_t;
++#define	DOT11_MGMT_HDR_LEN	24		/* d11 management header length */
++
++/* Management frame payloads */
++
++BWL_PRE_PACKED_STRUCT struct dot11_bcn_prb {
++	uint32			timestamp[2];
++	uint16			beacon_interval;
++	uint16			capability;
++} BWL_POST_PACKED_STRUCT;
++#define	DOT11_BCN_PRB_LEN	12		/* 802.11 beacon/probe frame fixed length */
++#define	DOT11_BCN_PRB_FIXED_LEN	12		/* 802.11 beacon/probe frame fixed length */
++
++BWL_PRE_PACKED_STRUCT struct dot11_auth {
++	uint16			alg;		/* algorithm */
++	uint16			seq;		/* sequence control */
++	uint16			status;		/* status code */
++} BWL_POST_PACKED_STRUCT;
++#define DOT11_AUTH_FIXED_LEN		6	/* length of auth frame without challenge IE */
++#define DOT11_AUTH_SEQ_STATUS_LEN	4	/* length of auth frame without challenge IE and
++						 * without algorithm
++						 */
++
++BWL_PRE_PACKED_STRUCT struct dot11_assoc_req {
++	uint16			capability;	/* capability information */
++	uint16			listen;		/* listen interval */
++} BWL_POST_PACKED_STRUCT;
++#define DOT11_ASSOC_REQ_FIXED_LEN	4	/* length of assoc frame without info elts */
++
++BWL_PRE_PACKED_STRUCT struct dot11_reassoc_req {
++	uint16			capability;	/* capability information */
++	uint16			listen;		/* listen interval */
++	struct ether_addr	ap;		/* Current AP address */
++} BWL_POST_PACKED_STRUCT;
++#define DOT11_REASSOC_REQ_FIXED_LEN	10	/* length of assoc frame without info elts */
++
++BWL_PRE_PACKED_STRUCT struct dot11_assoc_resp {
++	uint16			capability;	/* capability information */
++	uint16			status;		/* status code */
++	uint16			aid;		/* association ID */
++} BWL_POST_PACKED_STRUCT;
++#define DOT11_ASSOC_RESP_FIXED_LEN	6	/* length of assoc resp frame without info elts */
++
++BWL_PRE_PACKED_STRUCT struct dot11_action_measure {
++	uint8	category;
++	uint8	action;
++	uint8	token;
++	uint8	data[1];
++} BWL_POST_PACKED_STRUCT;
++#define DOT11_ACTION_MEASURE_LEN	3	/* d11 action measurement header length */
++
++BWL_PRE_PACKED_STRUCT struct dot11_action_ht_ch_width {
++	uint8	category;
++	uint8	action;
++	uint8	ch_width;
++} BWL_POST_PACKED_STRUCT;
++
++BWL_PRE_PACKED_STRUCT struct dot11_action_ht_mimops {
++	uint8	category;
++	uint8	action;
++	uint8	control;
++} BWL_POST_PACKED_STRUCT;
++
++BWL_PRE_PACKED_STRUCT struct dot11_action_sa_query {
++	uint8	category;
++	uint8	action;
++	uint16	id;
++} BWL_POST_PACKED_STRUCT;
++
++BWL_PRE_PACKED_STRUCT struct dot11_action_vht_oper_mode {
++	uint8	category;
++	uint8	action;
++	uint8	mode;
++} BWL_POST_PACKED_STRUCT;
++
++/* These lengths assume 64 MU groups, as specified in 802.11ac-2013 */
++#define DOT11_ACTION_GID_MEMBERSHIP_LEN  8    /* bytes */
++#define DOT11_ACTION_GID_USER_POS_LEN   16    /* bytes */
++BWL_PRE_PACKED_STRUCT struct dot11_action_group_id {
++	uint8   category;
++	uint8   action;
++	uint8   membership_status[DOT11_ACTION_GID_MEMBERSHIP_LEN];
++	uint8   user_position[DOT11_ACTION_GID_USER_POS_LEN];
++} BWL_POST_PACKED_STRUCT;
++
++#define SM_PWRSAVE_ENABLE	1
++#define SM_PWRSAVE_MODE		2
++
++/* ************* 802.11h related definitions. ************* */
++BWL_PRE_PACKED_STRUCT struct dot11_power_cnst {
++	uint8 id;
++	uint8 len;
++	uint8 power;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_power_cnst dot11_power_cnst_t;
++
++BWL_PRE_PACKED_STRUCT struct dot11_power_cap {
++	int8 min;
++	int8 max;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_power_cap dot11_power_cap_t;
++
++BWL_PRE_PACKED_STRUCT struct dot11_tpc_rep {
++	uint8 id;
++	uint8 len;
++	uint8 tx_pwr;
++	uint8 margin;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tpc_rep dot11_tpc_rep_t;
++#define DOT11_MNG_IE_TPC_REPORT_LEN	2 	/* length of IE data, not including 2 byte header */
++
++BWL_PRE_PACKED_STRUCT struct dot11_supp_channels {
++	uint8 id;
++	uint8 len;
++	uint8 first_channel;
++	uint8 num_channels;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_supp_channels dot11_supp_channels_t;
++
++/**
++ * Extension Channel Offset IE: 802.11n-D1.0 spec. added sideband
++ * offset for 40MHz operation.  The possible 3 values are:
++ * 1 = above control channel
++ * 3 = below control channel
++ * 0 = no extension channel
++ */
++BWL_PRE_PACKED_STRUCT struct dot11_extch {
++	uint8	id;		/* IE ID, 62, DOT11_MNG_EXT_CHANNEL_OFFSET */
++	uint8	len;		/* IE length */
++	uint8	extch;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_extch dot11_extch_ie_t;
++
++BWL_PRE_PACKED_STRUCT struct dot11_brcm_extch {
++	uint8	id;		/* IE ID, 221, DOT11_MNG_PROPR_ID */
++	uint8	len;		/* IE length */
++	uint8	oui[3];
++	uint8	type;           /* type indicates what follows */
++	uint8	extch;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_brcm_extch dot11_brcm_extch_ie_t;
++
++#define BRCM_EXTCH_IE_LEN	5
++#define BRCM_EXTCH_IE_TYPE	53	/* 802.11n ID not yet assigned */
++#define DOT11_EXTCH_IE_LEN	1
++#define DOT11_EXT_CH_MASK	0x03	/* extension channel mask */
++#define DOT11_EXT_CH_UPPER	0x01	/* ext. ch. on upper sb */
++#define DOT11_EXT_CH_LOWER	0x03	/* ext. ch. on lower sb */
++#define DOT11_EXT_CH_NONE	0x00	/* no extension ch.  */
++
++BWL_PRE_PACKED_STRUCT struct dot11_action_frmhdr {
++	uint8	category;
++	uint8	action;
++	uint8	data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_action_frmhdr dot11_action_frmhdr_t;
++
++/* Action Field length */
++#define DOT11_ACTION_CATEGORY_LEN	1
++#define DOT11_ACTION_ACTION_LEN		1
++#define DOT11_ACTION_DIALOG_TOKEN_LEN	1
++#define DOT11_ACTION_CAPABILITY_LEN	2
++#define DOT11_ACTION_STATUS_CODE_LEN	2
++#define DOT11_ACTION_REASON_CODE_LEN	2
++#define DOT11_ACTION_TARGET_CH_LEN	1
++#define DOT11_ACTION_OPER_CLASS_LEN	1
++
++#define DOT11_ACTION_FRMHDR_LEN	2
++
++/** CSA IE data structure */
++BWL_PRE_PACKED_STRUCT struct dot11_channel_switch {
++	uint8 id;	/* id DOT11_MNG_CHANNEL_SWITCH_ID */
++	uint8 len;	/* length of IE */
++	uint8 mode;	/* mode 0 or 1 */
++	uint8 channel;	/* channel switch to */
++	uint8 count;	/* number of beacons before switching */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_channel_switch dot11_chan_switch_ie_t;
++
++#define DOT11_SWITCH_IE_LEN	3	/* length of IE data, not including 2 byte header */
++/* CSA mode - 802.11h-2003 $7.3.2.20 */
++#define DOT11_CSA_MODE_ADVISORY		0	/* no DOT11_CSA_MODE_NO_TX restriction imposed */
++#define DOT11_CSA_MODE_NO_TX		1	/* no transmission upon receiving CSA frame. */
++
++BWL_PRE_PACKED_STRUCT struct dot11_action_switch_channel {
++	uint8	category;
++	uint8	action;
++	dot11_chan_switch_ie_t chan_switch_ie;	/* for switch IE */
++	dot11_brcm_extch_ie_t extch_ie;		/* extension channel offset */
++} BWL_POST_PACKED_STRUCT;
++
++BWL_PRE_PACKED_STRUCT struct dot11_csa_body {
++	uint8 mode;	/* mode 0 or 1 */
++	uint8 reg;	/* regulatory class */
++	uint8 channel;	/* channel switch to */
++	uint8 count;	/* number of beacons before switching */
++} BWL_POST_PACKED_STRUCT;
++
++/** 11n Extended Channel Switch IE data structure */
++BWL_PRE_PACKED_STRUCT struct dot11_ext_csa {
++	uint8 id;	/* id DOT11_MNG_EXT_CSA_ID */
++	uint8 len;	/* length of IE */
++	struct dot11_csa_body b;	/* body of the ie */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_ext_csa dot11_ext_csa_ie_t;
++#define DOT11_EXT_CSA_IE_LEN	4	/* length of extended channel switch IE body */
++
++BWL_PRE_PACKED_STRUCT struct dot11_action_ext_csa {
++	uint8	category;
++	uint8	action;
++	dot11_ext_csa_ie_t chan_switch_ie;	/* for switch IE */
++} BWL_POST_PACKED_STRUCT;
++
++BWL_PRE_PACKED_STRUCT struct dot11y_action_ext_csa {
++	uint8	category;
++	uint8	action;
++	struct dot11_csa_body b;	/* body of the ie */
++} BWL_POST_PACKED_STRUCT;
++
++/**  Wide Bandwidth Channel Switch IE data structure */
++BWL_PRE_PACKED_STRUCT struct dot11_wide_bw_channel_switch {
++	uint8 id;				/* id DOT11_MNG_WIDE_BW_CHANNEL_SWITCH_ID */
++	uint8 len;				/* length of IE */
++	uint8 channel_width;			/* new channel width */
++	uint8 center_frequency_segment_0;	/* center frequency segment 0 */
++	uint8 center_frequency_segment_1;	/* center frequency segment 1 */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_wide_bw_channel_switch dot11_wide_bw_chan_switch_ie_t;
++
++#define DOT11_WIDE_BW_SWITCH_IE_LEN     3       /* length of IE data, not including 2 byte header */
++
++/** Channel Switch Wrapper IE data structure */
++BWL_PRE_PACKED_STRUCT struct dot11_channel_switch_wrapper {
++	uint8 id;				/* id DOT11_MNG_WIDE_BW_CHANNEL_SWITCH_ID */
++	uint8 len;				/* length of IE */
++	dot11_wide_bw_chan_switch_ie_t wb_chan_switch_ie;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_channel_switch_wrapper dot11_chan_switch_wrapper_ie_t;
++
++typedef enum wide_bw_chan_width {
++	WIDE_BW_CHAN_WIDTH_20	= 0,
++	WIDE_BW_CHAN_WIDTH_40	= 1,
++	WIDE_BW_CHAN_WIDTH_80	= 2,
++	WIDE_BW_CHAN_WIDTH_160	= 3,
++	WIDE_BW_CHAN_WIDTH_80_80	= 4
++} wide_bw_chan_width_t;
++
++/**  Wide Bandwidth Channel IE data structure */
++BWL_PRE_PACKED_STRUCT struct dot11_wide_bw_channel {
++	uint8 id;				/* id DOT11_MNG_WIDE_BW_CHANNEL_ID */
++	uint8 len;				/* length of IE */
++	uint8 channel_width;			/* channel width */
++	uint8 center_frequency_segment_0;	/* center frequency segment 0 */
++	uint8 center_frequency_segment_1;	/* center frequency segment 1 */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_wide_bw_channel dot11_wide_bw_chan_ie_t;
++
++#define DOT11_WIDE_BW_IE_LEN     3       /* length of IE data, not including 2 byte header */
++/** VHT Transmit Power Envelope IE data structure */
++BWL_PRE_PACKED_STRUCT struct dot11_vht_transmit_power_envelope {
++	uint8 id;				/* id DOT11_MNG_WIDE_BW_CHANNEL_SWITCH_ID */
++	uint8 len;				/* length of IE */
++	uint8 transmit_power_info;
++	uint8 local_max_transmit_power_20;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_vht_transmit_power_envelope dot11_vht_transmit_power_envelope_ie_t;
++
++/* vht transmit power envelope IE length depends on channel width */
++#define DOT11_VHT_TRANSMIT_PWR_ENVELOPE_IE_LEN_40MHZ	1
++#define DOT11_VHT_TRANSMIT_PWR_ENVELOPE_IE_LEN_80MHZ	2
++#define DOT11_VHT_TRANSMIT_PWR_ENVELOPE_IE_LEN_160MHZ	3
++
++BWL_PRE_PACKED_STRUCT struct dot11_obss_coex {
++	uint8	id;
++	uint8	len;
++	uint8	info;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_obss_coex dot11_obss_coex_t;
++#define DOT11_OBSS_COEXINFO_LEN	1	/* length of OBSS Coexistence INFO IE */
++
++#define	DOT11_OBSS_COEX_INFO_REQ		0x01
++#define	DOT11_OBSS_COEX_40MHZ_INTOLERANT	0x02
++#define	DOT11_OBSS_COEX_20MHZ_WIDTH_REQ	0x04
++
++BWL_PRE_PACKED_STRUCT struct dot11_obss_chanlist {
++	uint8	id;
++	uint8	len;
++	uint8	regclass;
++	uint8	chanlist[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_obss_chanlist dot11_obss_chanlist_t;
++#define DOT11_OBSS_CHANLIST_FIXED_LEN	1	/* fixed length of regclass */
++
++BWL_PRE_PACKED_STRUCT struct dot11_extcap_ie {
++	uint8 id;
++	uint8 len;
++	uint8 cap[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_extcap_ie dot11_extcap_ie_t;
++
++#define DOT11_EXTCAP_LEN_COEX	1
++#define DOT11_EXTCAP_LEN_BT	3
++#define DOT11_EXTCAP_LEN_IW	4
++#define DOT11_EXTCAP_LEN_SI	6
++
++#define DOT11_EXTCAP_LEN_TDLS	5
++#define DOT11_11AC_EXTCAP_LEN_TDLS	8
++
++#define DOT11_EXTCAP_LEN_FMS			2
++#define DOT11_EXTCAP_LEN_PROXY_ARP		2
++#define DOT11_EXTCAP_LEN_TFS			3
++#define DOT11_EXTCAP_LEN_WNM_SLEEP		3
++#define DOT11_EXTCAP_LEN_TIMBC			3
++#define DOT11_EXTCAP_LEN_BSSTRANS		3
++#define DOT11_EXTCAP_LEN_DMS			4
++#define DOT11_EXTCAP_LEN_WNM_NOTIFICATION	6
++#define DOT11_EXTCAP_LEN_TDLS_WBW		8
++#define DOT11_EXTCAP_LEN_OPMODE_NOTIFICATION	8
++
++/* TDLS Capabilities */
++#define DOT11_TDLS_CAP_TDLS			37		/* TDLS support */
++#define DOT11_TDLS_CAP_PU_BUFFER_STA	28		/* TDLS Peer U-APSD buffer STA support */
++#define DOT11_TDLS_CAP_PEER_PSM		20		/* TDLS Peer PSM support */
++#define DOT11_TDLS_CAP_CH_SW			30		/* TDLS Channel switch */
++#define DOT11_TDLS_CAP_PROH			38		/* TDLS prohibited */
++#define DOT11_TDLS_CAP_CH_SW_PROH		39		/* TDLS Channel switch prohibited */
++#define DOT11_TDLS_CAP_TDLS_WIDER_BW	61	/* TDLS Wider Band-Width */
++
++#define TDLS_CAP_MAX_BIT		39		/* TDLS max bit defined in ext cap */
++
++/* 802.11h/802.11k Measurement Request/Report IEs */
++/* Measurement Type field */
++#define DOT11_MEASURE_TYPE_BASIC 	0   /* d11 measurement basic type */
++#define DOT11_MEASURE_TYPE_CCA 		1   /* d11 measurement CCA type */
++#define DOT11_MEASURE_TYPE_RPI		2   /* d11 measurement RPI type */
++#define DOT11_MEASURE_TYPE_CHLOAD	3   /* d11 measurement Channel Load type */
++#define DOT11_MEASURE_TYPE_NOISE	4   /* d11 measurement Noise Histogram type */
++#define DOT11_MEASURE_TYPE_BEACON	5   /* d11 measurement Beacon type */
++#define DOT11_MEASURE_TYPE_FRAME	6   /* d11 measurement Frame type */
++#define DOT11_MEASURE_TYPE_STAT		7   /* d11 measurement STA Statistics type */
++#define DOT11_MEASURE_TYPE_LCI		8   /* d11 measurement LCI type */
++#define DOT11_MEASURE_TYPE_TXSTREAM	9   /* d11 measurement TX Stream type */
++#define DOT11_MEASURE_TYPE_MCDIAGS	10  /* d11 measurement multicast diagnostics */
++#define DOT11_MEASURE_TYPE_CIVICLOC	11  /* d11 measurement location civic */
++#define DOT11_MEASURE_TYPE_LOC_ID	12  /* d11 measurement location identifier */
++#define DOT11_MEASURE_TYPE_DIRCHANQ	13  /* d11 measurement dir channel quality */
++#define DOT11_MEASURE_TYPE_DIRMEAS	14  /* d11 measurement directional */
++#define DOT11_MEASURE_TYPE_DIRSTATS	15  /* d11 measurement directional stats */
++#define DOT11_MEASURE_TYPE_FTMRANGE	16  /* d11 measurement Fine Timing */
++#define DOT11_MEASURE_TYPE_PAUSE	255	/* d11 measurement pause type */
++
++/* Measurement Request Modes */
++#define DOT11_MEASURE_MODE_PARALLEL 	(1<<0)	/* d11 measurement parallel */
++#define DOT11_MEASURE_MODE_ENABLE 	(1<<1)	/* d11 measurement enable */
++#define DOT11_MEASURE_MODE_REQUEST	(1<<2)	/* d11 measurement request */
++#define DOT11_MEASURE_MODE_REPORT 	(1<<3)	/* d11 measurement report */
++#define DOT11_MEASURE_MODE_DUR 	(1<<4)	/* d11 measurement dur mandatory */
++/* Measurement Report Modes */
++#define DOT11_MEASURE_MODE_LATE 	(1<<0)	/* d11 measurement late */
++#define DOT11_MEASURE_MODE_INCAPABLE	(1<<1)	/* d11 measurement incapable */
++#define DOT11_MEASURE_MODE_REFUSED	(1<<2)	/* d11 measurement refuse */
++/* Basic Measurement Map bits */
++#define DOT11_MEASURE_BASIC_MAP_BSS	((uint8)(1<<0))	/* d11 measurement basic map BSS */
++#define DOT11_MEASURE_BASIC_MAP_OFDM	((uint8)(1<<1))	/* d11 measurement map OFDM */
++#define DOT11_MEASURE_BASIC_MAP_UKNOWN	((uint8)(1<<2))	/* d11 measurement map unknown */
++#define DOT11_MEASURE_BASIC_MAP_RADAR	((uint8)(1<<3))	/* d11 measurement map radar */
++#define DOT11_MEASURE_BASIC_MAP_UNMEAS	((uint8)(1<<4))	/* d11 measurement map unmeasuremnt */
++
++BWL_PRE_PACKED_STRUCT struct dot11_meas_req {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++	uint8 channel;
++	uint8 start_time[8];
++	uint16 duration;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_meas_req dot11_meas_req_t;
++#define DOT11_MNG_IE_MREQ_LEN 14	/* d11 measurement request IE length */
++/* length of Measure Request IE data not including variable len */
++#define DOT11_MNG_IE_MREQ_FIXED_LEN 3	/* d11 measurement request IE fixed length */
++
++BWL_PRE_PACKED_STRUCT struct dot11_meas_req_loc {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++	BWL_PRE_PACKED_STRUCT union
++	{
++		BWL_PRE_PACKED_STRUCT struct {
++			uint8 subject;
++			uint8 data[1];
++		} BWL_POST_PACKED_STRUCT lci;
++		BWL_PRE_PACKED_STRUCT struct {
++			uint8 subject;
++			uint8 type;  /* type of civic location */
++			uint8 siu;   /* service interval units */
++			uint16 si; /* service interval */
++			uint8 data[1];
++		} BWL_POST_PACKED_STRUCT civic;
++		BWL_PRE_PACKED_STRUCT struct {
++			uint8 subject;
++			uint8 siu;   /* service interval units */
++			uint16 si; /* service interval */
++			uint8 data[1];
++		} BWL_POST_PACKED_STRUCT locid;
++		BWL_PRE_PACKED_STRUCT struct {
++			uint16 max_init_delay;		/* maximum random initial delay */
++			uint8 min_ap_count;
++			uint8 data[1];
++		} BWL_POST_PACKED_STRUCT ftm_range;
++	} BWL_POST_PACKED_STRUCT req;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_meas_req_loc dot11_meas_req_loc_t;
++#define DOT11_MNG_IE_MREQ_MIN_LEN           4	/* d11 measurement report IE length */
++#define DOT11_MNG_IE_MREQ_LCI_FIXED_LEN     4	/* d11 measurement report IE length */
++#define DOT11_MNG_IE_MREQ_CIVIC_FIXED_LEN   8	/* d11 measurement report IE length */
++#define DOT11_MNG_IE_MREQ_FRNG_FIXED_LEN    6	/* d11 measurement report IE length */
++
++BWL_PRE_PACKED_STRUCT struct dot11_lci_subelement {
++	uint8 subelement;
++	uint8 length;
++	uint8 lci_data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_lci_subelement dot11_lci_subelement_t;
++
++BWL_PRE_PACKED_STRUCT struct dot11_colocated_bssid_list_se {
++	uint8 sub_id;
++	uint8 length;
++	uint8 max_bssid_ind; /* MaxBSSID Indicator */
++	struct ether_addr bssid[1]; /* variable */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_colocated_bssid_list_se dot11_colocated_bssid_list_se_t;
++#define DOT11_LCI_COLOCATED_BSSID_LIST_FIXED_LEN     3
++#define DOT11_LCI_COLOCATED_BSSID_SUBELEM_ID         7
++
++BWL_PRE_PACKED_STRUCT struct dot11_civic_subelement {
++	uint8 type;  /* type of civic location */
++	uint8 subelement;
++	uint8 length;
++	uint8 civic_data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_civic_subelement dot11_civic_subelement_t;
++
++BWL_PRE_PACKED_STRUCT struct dot11_meas_rep {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++	BWL_PRE_PACKED_STRUCT union
++	{
++		BWL_PRE_PACKED_STRUCT struct {
++			uint8 channel;
++			uint8 start_time[8];
++			uint16 duration;
++			uint8 map;
++		} BWL_POST_PACKED_STRUCT basic;
++		BWL_PRE_PACKED_STRUCT struct {
++			uint8 subelement;
++			uint8 length;
++			uint8 data[1];
++		} BWL_POST_PACKED_STRUCT lci;
++		BWL_PRE_PACKED_STRUCT struct {
++			uint8 type;  /* type of civic location */
++			uint8 subelement;
++			uint8 length;
++			uint8 data[1];
++		} BWL_POST_PACKED_STRUCT civic;
++		BWL_PRE_PACKED_STRUCT struct {
++			uint8 exp_tsf[8];
++			uint8 subelement;
++			uint8 length;
++			uint8 data[1];
++		} BWL_POST_PACKED_STRUCT locid;
++		BWL_PRE_PACKED_STRUCT struct {
++			uint8 entry_count;
++			uint8 data[1];
++		} BWL_POST_PACKED_STRUCT ftm_range;
++		uint8 data[1];
++	} BWL_POST_PACKED_STRUCT rep;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_meas_rep dot11_meas_rep_t;
++#define DOT11_MNG_IE_MREP_MIN_LEN           5	/* d11 measurement report IE length */
++#define DOT11_MNG_IE_MREP_LCI_FIXED_LEN     5	/* d11 measurement report IE length */
++#define DOT11_MNG_IE_MREP_CIVIC_FIXED_LEN   6	/* d11 measurement report IE length */
++#define DOT11_MNG_IE_MREP_LOCID_FIXED_LEN   13	/* d11 measurement report IE length */
++#define DOT11_MNG_IE_MREP_BASIC_FIXED_LEN   15	/* d11 measurement report IE length */
++#define DOT11_MNG_IE_MREP_FRNG_FIXED_LEN    4
++
++/* length of Measure Report IE data not including variable len */
++#define DOT11_MNG_IE_MREP_FIXED_LEN	3	/* d11 measurement response IE fixed length */
++
++BWL_PRE_PACKED_STRUCT struct dot11_meas_rep_basic {
++	uint8 channel;
++	uint8 start_time[8];
++	uint16 duration;
++	uint8 map;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_meas_rep_basic dot11_meas_rep_basic_t;
++#define DOT11_MEASURE_BASIC_REP_LEN	12	/* d11 measurement basic report length */
++
++BWL_PRE_PACKED_STRUCT struct dot11_quiet {
++	uint8 id;
++	uint8 len;
++	uint8 count;	/* TBTTs until beacon interval in quiet starts */
++	uint8 period;	/* Beacon intervals between periodic quiet periods ? */
++	uint16 duration;	/* Length of quiet period, in TU's */
++	uint16 offset;	/* TU's offset from TBTT in Count field */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_quiet dot11_quiet_t;
++
++BWL_PRE_PACKED_STRUCT struct chan_map_tuple {
++	uint8 channel;
++	uint8 map;
++} BWL_POST_PACKED_STRUCT;
++typedef struct chan_map_tuple chan_map_tuple_t;
++
++BWL_PRE_PACKED_STRUCT struct dot11_ibss_dfs {
++	uint8 id;
++	uint8 len;
++	uint8 eaddr[ETHER_ADDR_LEN];
++	uint8 interval;
++	chan_map_tuple_t map[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_ibss_dfs dot11_ibss_dfs_t;
++
++/* WME Elements */
++#define WME_OUI			"\x00\x50\xf2"	/* WME OUI */
++#define WME_OUI_LEN		3
++#define WME_OUI_TYPE		2	/* WME type */
++#define WME_TYPE		2	/* WME type, deprecated */
++#define WME_SUBTYPE_IE		0	/* Information Element */
++#define WME_SUBTYPE_PARAM_IE	1	/* Parameter Element */
++#define WME_SUBTYPE_TSPEC	2	/* Traffic Specification */
++#define WME_VER			1	/* WME version */
++
++/* WME Access Category Indices (ACIs) */
++#define AC_BE			0	/* Best Effort */
++#define AC_BK			1	/* Background */
++#define AC_VI			2	/* Video */
++#define AC_VO			3	/* Voice */
++#define AC_COUNT		4	/* number of ACs */
++
++typedef uint8 ac_bitmap_t;	/* AC bitmap of (1 << AC_xx) */
++
++#define AC_BITMAP_NONE		0x0	/* No ACs */
++#define AC_BITMAP_ALL		0xf	/* All ACs */
++#define AC_BITMAP_TST(ab, ac)	(((ab) & (1 << (ac))) != 0)
++#define AC_BITMAP_SET(ab, ac)	(((ab) |= (1 << (ac))))
++#define AC_BITMAP_RESET(ab, ac) (((ab) &= ~(1 << (ac))))
++
++/* Management PKT Lifetime indices */
++/* Removing flag checks 'BCMINTERNAL || WLTEST'
++ * while merging MERGE BIS120RC4 to DINGO2
++ */
++#define MGMT_ALL		0xffff
++#define MGMT_AUTH_LT	FC_SUBTYPE_AUTH
++#define MGMT_ASSOC_LT	FC_SUBTYPE_ASSOC_REQ
++
++/** WME Information Element (IE) */
++BWL_PRE_PACKED_STRUCT struct wme_ie {
++	uint8 oui[3];
++	uint8 type;
++	uint8 subtype;
++	uint8 version;
++	uint8 qosinfo;
++} BWL_POST_PACKED_STRUCT;
++typedef struct wme_ie wme_ie_t;
++#define WME_IE_LEN 7	/* WME IE length */
++
++BWL_PRE_PACKED_STRUCT struct edcf_acparam {
++	uint8	ACI;
++	uint8	ECW;
++	uint16  TXOP;		/* stored in network order (ls octet first) */
++} BWL_POST_PACKED_STRUCT;
++typedef struct edcf_acparam edcf_acparam_t;
++
++/** WME Parameter Element (PE) */
++BWL_PRE_PACKED_STRUCT struct wme_param_ie {
++	uint8 oui[3];
++	uint8 type;
++	uint8 subtype;
++	uint8 version;
++	uint8 qosinfo;
++	uint8 rsvd;
++	edcf_acparam_t acparam[AC_COUNT];
++} BWL_POST_PACKED_STRUCT;
++typedef struct wme_param_ie wme_param_ie_t;
++#define WME_PARAM_IE_LEN            24          /* WME Parameter IE length */
++
++/* QoS Info field for IE as sent from AP */
++#define WME_QI_AP_APSD_MASK         0x80        /* U-APSD Supported mask */
++#define WME_QI_AP_APSD_SHIFT        7           /* U-APSD Supported shift */
++#define WME_QI_AP_COUNT_MASK        0x0f        /* Parameter set count mask */
++#define WME_QI_AP_COUNT_SHIFT       0           /* Parameter set count shift */
++
++/* QoS Info field for IE as sent from STA */
++#define WME_QI_STA_MAXSPLEN_MASK    0x60        /* Max Service Period Length mask */
++#define WME_QI_STA_MAXSPLEN_SHIFT   5           /* Max Service Period Length shift */
++#define WME_QI_STA_APSD_ALL_MASK    0xf         /* APSD all AC bits mask */
++#define WME_QI_STA_APSD_ALL_SHIFT   0           /* APSD all AC bits shift */
++#define WME_QI_STA_APSD_BE_MASK     0x8         /* APSD AC_BE mask */
++#define WME_QI_STA_APSD_BE_SHIFT    3           /* APSD AC_BE shift */
++#define WME_QI_STA_APSD_BK_MASK     0x4         /* APSD AC_BK mask */
++#define WME_QI_STA_APSD_BK_SHIFT    2           /* APSD AC_BK shift */
++#define WME_QI_STA_APSD_VI_MASK     0x2         /* APSD AC_VI mask */
++#define WME_QI_STA_APSD_VI_SHIFT    1           /* APSD AC_VI shift */
++#define WME_QI_STA_APSD_VO_MASK     0x1         /* APSD AC_VO mask */
++#define WME_QI_STA_APSD_VO_SHIFT    0           /* APSD AC_VO shift */
++
++/* ACI */
++#define EDCF_AIFSN_MIN               1           /* AIFSN minimum value */
++#define EDCF_AIFSN_MAX               15          /* AIFSN maximum value */
++#define EDCF_AIFSN_MASK              0x0f        /* AIFSN mask */
++#define EDCF_ACM_MASK                0x10        /* ACM mask */
++#define EDCF_ACI_MASK                0x60        /* ACI mask */
++#define EDCF_ACI_SHIFT               5           /* ACI shift */
++#define EDCF_AIFSN_SHIFT             12          /* 4 MSB(0xFFF) in ifs_ctl for AC idx */
++
++/* ECW */
++#define EDCF_ECW_MIN                 0           /* cwmin/cwmax exponent minimum value */
++#define EDCF_ECW_MAX                 15          /* cwmin/cwmax exponent maximum value */
++#define EDCF_ECW2CW(exp)             ((1 << (exp)) - 1)
++#define EDCF_ECWMIN_MASK             0x0f        /* cwmin exponent form mask */
++#define EDCF_ECWMAX_MASK             0xf0        /* cwmax exponent form mask */
++#define EDCF_ECWMAX_SHIFT            4           /* cwmax exponent form shift */
++
++/* TXOP */
++#define EDCF_TXOP_MIN                0           /* TXOP minimum value */
++#define EDCF_TXOP_MAX                65535       /* TXOP maximum value */
++#define EDCF_TXOP2USEC(txop)         ((txop) << 5)
++
++/* Default BE ACI value for non-WME connection STA */
++#define NON_EDCF_AC_BE_ACI_STA          0x02
++
++/* Default EDCF parameters that AP advertises for STA to use; WMM draft Table 12 */
++#define EDCF_AC_BE_ACI_STA           0x03	/* STA ACI value for best effort AC */
++#define EDCF_AC_BE_ECW_STA           0xA4	/* STA ECW value for best effort AC */
++#define EDCF_AC_BE_TXOP_STA          0x0000	/* STA TXOP value for best effort AC */
++#define EDCF_AC_BK_ACI_STA           0x27	/* STA ACI value for background AC */
++#define EDCF_AC_BK_ECW_STA           0xA4	/* STA ECW value for background AC */
++#define EDCF_AC_BK_TXOP_STA          0x0000	/* STA TXOP value for background AC */
++#define EDCF_AC_VI_ACI_STA           0x42	/* STA ACI value for video AC */
++#define EDCF_AC_VI_ECW_STA           0x43	/* STA ECW value for video AC */
++#define EDCF_AC_VI_TXOP_STA          0x005e	/* STA TXOP value for video AC */
++#define EDCF_AC_VO_ACI_STA           0x62	/* STA ACI value for audio AC */
++#define EDCF_AC_VO_ECW_STA           0x32	/* STA ECW value for audio AC */
++#define EDCF_AC_VO_TXOP_STA          0x002f	/* STA TXOP value for audio AC */
++
++/* Default EDCF parameters that AP uses; WMM draft Table 14 */
++#define EDCF_AC_BE_ACI_AP            0x03	/* AP ACI value for best effort AC */
++#define EDCF_AC_BE_ECW_AP            0x64	/* AP ECW value for best effort AC */
++#define EDCF_AC_BE_TXOP_AP           0x0000	/* AP TXOP value for best effort AC */
++#define EDCF_AC_BK_ACI_AP            0x27	/* AP ACI value for background AC */
++#define EDCF_AC_BK_ECW_AP            0xA4	/* AP ECW value for background AC */
++#define EDCF_AC_BK_TXOP_AP           0x0000	/* AP TXOP value for background AC */
++#define EDCF_AC_VI_ACI_AP            0x41	/* AP ACI value for video AC */
++#define EDCF_AC_VI_ECW_AP            0x43	/* AP ECW value for video AC */
++#define EDCF_AC_VI_TXOP_AP           0x005e	/* AP TXOP value for video AC */
++#define EDCF_AC_VO_ACI_AP            0x61	/* AP ACI value for audio AC */
++#define EDCF_AC_VO_ECW_AP            0x32	/* AP ECW value for audio AC */
++#define EDCF_AC_VO_TXOP_AP           0x002f	/* AP TXOP value for audio AC */
++
++/** EDCA Parameter IE */
++BWL_PRE_PACKED_STRUCT struct edca_param_ie {
++	uint8 qosinfo;
++	uint8 rsvd;
++	edcf_acparam_t acparam[AC_COUNT];
++} BWL_POST_PACKED_STRUCT;
++typedef struct edca_param_ie edca_param_ie_t;
++#define EDCA_PARAM_IE_LEN            18          /* EDCA Parameter IE length */
++
++/** QoS Capability IE */
++BWL_PRE_PACKED_STRUCT struct qos_cap_ie {
++	uint8 qosinfo;
++} BWL_POST_PACKED_STRUCT;
++typedef struct qos_cap_ie qos_cap_ie_t;
++
++BWL_PRE_PACKED_STRUCT struct dot11_qbss_load_ie {
++	uint8 id; 			/* 11, DOT11_MNG_QBSS_LOAD_ID */
++	uint8 length;
++	uint16 station_count; 		/* total number of STAs associated */
++	uint8 channel_utilization;	/* % of time, normalized to 255, QAP sensed medium busy */
++	uint16 aac; 			/* available admission capacity */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_qbss_load_ie dot11_qbss_load_ie_t;
++#define BSS_LOAD_IE_SIZE 	7	/* BSS load IE size */
++
++#define WLC_QBSS_LOAD_CHAN_FREE_MAX	0xff	/* max for channel free score */
++
++/* nom_msdu_size */
++#define FIXED_MSDU_SIZE 0x8000		/* MSDU size is fixed */
++#define MSDU_SIZE_MASK	0x7fff		/* (Nominal or fixed) MSDU size */
++
++/* surplus_bandwidth */
++/* Represented as 3 bits of integer, binary point, 13 bits fraction */
++#define	INTEGER_SHIFT	13	/* integer shift */
++#define FRACTION_MASK	0x1FFF	/* fraction mask */
++
++/** Management Notification Frame */
++BWL_PRE_PACKED_STRUCT struct dot11_management_notification {
++	uint8 category;			/* DOT11_ACTION_NOTIFICATION */
++	uint8 action;
++	uint8 token;
++	uint8 status;
++	uint8 data[1];			/* Elements */
++} BWL_POST_PACKED_STRUCT;
++#define DOT11_MGMT_NOTIFICATION_LEN 4	/* Fixed length */
++
++/** Timeout Interval IE */
++BWL_PRE_PACKED_STRUCT struct ti_ie {
++	uint8 ti_type;
++	uint32 ti_val;
++} BWL_POST_PACKED_STRUCT;
++typedef struct ti_ie ti_ie_t;
++#define TI_TYPE_REASSOC_DEADLINE	1
++#define TI_TYPE_KEY_LIFETIME		2
++
++#ifndef CISCO_AIRONET_OUI
++#define CISCO_AIRONET_OUI	"\x00\x40\x96"	/* Cisco AIRONET OUI */
++#endif
++/* QoS FastLane IE. */
++BWL_PRE_PACKED_STRUCT struct ccx_qfl_ie {
++	uint8	id;		/* 221, DOT11_MNG_VS_ID */
++	uint8	length;		/* 5 */
++	uint8	oui[3];		/* 00:40:96 */
++	uint8	type;		/* 11 */
++	uint8	data;
++} BWL_POST_PACKED_STRUCT;
++typedef struct ccx_qfl_ie ccx_qfl_ie_t;
++#define CCX_QFL_IE_TYPE	11
++#define CCX_QFL_ENABLE_SHIFT	5
++#define CCX_QFL_ENALBE (1 << CCX_QFL_ENABLE_SHIFT)
++
++/* WME Action Codes */
++#define WME_ADDTS_REQUEST	0	/* WME ADDTS request */
++#define WME_ADDTS_RESPONSE	1	/* WME ADDTS response */
++#define WME_DELTS_REQUEST	2	/* WME DELTS request */
++
++/* WME Setup Response Status Codes */
++#define WME_ADMISSION_ACCEPTED		0	/* WME admission accepted */
++#define WME_INVALID_PARAMETERS		1	/* WME invalide parameters */
++#define WME_ADMISSION_REFUSED		3	/* WME admission refused */
++
++/* Macro to take a pointer to a beacon or probe response
++ * body and return the char* pointer to the SSID info element
++ */
++#define BCN_PRB_SSID(body) ((char*)(body) + DOT11_BCN_PRB_LEN)
++
++/* Authentication frame payload constants */
++#define DOT11_OPEN_SYSTEM	0	/* d11 open authentication */
++#define DOT11_SHARED_KEY	1	/* d11 shared authentication */
++#define DOT11_FAST_BSS		2	/* d11 fast bss authentication */
++#define DOT11_SAE		3	/* d11 simultaneous authentication of equals */
++#define DOT11_FILS_SKEY_PFS	4	/* d11 fils shared key authentication w/o pfs */
++#define DOT11_FILS_SKEY		5	/* d11 fils shared key authentication w/ pfs */
++#define DOT11_FILS_PKEY		6	/* d11 fils public key authentication */
++#define DOT11_CHALLENGE_LEN	128	/* d11 challenge text length */
++
++/* Frame control macros */
++#define FC_PVER_MASK		0x3	/* PVER mask */
++#define FC_PVER_SHIFT		0	/* PVER shift */
++#define FC_TYPE_MASK		0xC	/* type mask */
++#define FC_TYPE_SHIFT		2	/* type shift */
++#define FC_SUBTYPE_MASK		0xF0	/* subtype mask */
++#define FC_SUBTYPE_SHIFT	4	/* subtype shift */
++#define FC_TODS			0x100	/* to DS */
++#define FC_TODS_SHIFT		8	/* to DS shift */
++#define FC_FROMDS		0x200	/* from DS */
++#define FC_FROMDS_SHIFT		9	/* from DS shift */
++#define FC_MOREFRAG		0x400	/* more frag. */
++#define FC_MOREFRAG_SHIFT	10	/* more frag. shift */
++#define FC_RETRY		0x800	/* retry */
++#define FC_RETRY_SHIFT		11	/* retry shift */
++#define FC_PM			0x1000	/* PM */
++#define FC_PM_SHIFT		12	/* PM shift */
++#define FC_MOREDATA		0x2000	/* more data */
++#define FC_MOREDATA_SHIFT	13	/* more data shift */
++#define FC_WEP			0x4000	/* WEP */
++#define FC_WEP_SHIFT		14	/* WEP shift */
++#define FC_ORDER		0x8000	/* order */
++#define FC_ORDER_SHIFT		15	/* order shift */
++
++/* sequence control macros */
++#define SEQNUM_SHIFT		4	/* seq. number shift */
++#define SEQNUM_MAX		0x1000	/* max seqnum + 1 */
++#define FRAGNUM_MASK		0xF	/* frag. number mask */
++
++/* Frame Control type/subtype defs */
++
++/* FC Types */
++#define FC_TYPE_MNG		0	/* management type */
++#define FC_TYPE_CTL		1	/* control type */
++#define FC_TYPE_DATA		2	/* data type */
++
++/* Management Subtypes */
++#define FC_SUBTYPE_ASSOC_REQ		0	/* assoc. request */
++#define FC_SUBTYPE_ASSOC_RESP		1	/* assoc. response */
++#define FC_SUBTYPE_REASSOC_REQ		2	/* reassoc. request */
++#define FC_SUBTYPE_REASSOC_RESP		3	/* reassoc. response */
++#define FC_SUBTYPE_PROBE_REQ		4	/* probe request */
++#define FC_SUBTYPE_PROBE_RESP		5	/* probe response */
++#define FC_SUBTYPE_BEACON		8	/* beacon */
++#define FC_SUBTYPE_ATIM			9	/* ATIM */
++#define FC_SUBTYPE_DISASSOC		10	/* disassoc. */
++#define FC_SUBTYPE_AUTH			11	/* authentication */
++#define FC_SUBTYPE_DEAUTH		12	/* de-authentication */
++#define FC_SUBTYPE_ACTION		13	/* action */
++#define FC_SUBTYPE_ACTION_NOACK		14	/* action no-ack */
++
++/* Control Subtypes */
++#define FC_SUBTYPE_CTL_WRAPPER		7	/* Control Wrapper */
++#define FC_SUBTYPE_BLOCKACK_REQ		8	/* Block Ack Req */
++#define FC_SUBTYPE_BLOCKACK		9	/* Block Ack */
++#define FC_SUBTYPE_PS_POLL		10	/* PS poll */
++#define FC_SUBTYPE_RTS			11	/* RTS */
++#define FC_SUBTYPE_CTS			12	/* CTS */
++#define FC_SUBTYPE_ACK			13	/* ACK */
++#define FC_SUBTYPE_CF_END		14	/* CF-END */
++#define FC_SUBTYPE_CF_END_ACK		15	/* CF-END ACK */
++
++/* Data Subtypes */
++#define FC_SUBTYPE_DATA			0	/* Data */
++#define FC_SUBTYPE_DATA_CF_ACK		1	/* Data + CF-ACK */
++#define FC_SUBTYPE_DATA_CF_POLL		2	/* Data + CF-Poll */
++#define FC_SUBTYPE_DATA_CF_ACK_POLL	3	/* Data + CF-Ack + CF-Poll */
++#define FC_SUBTYPE_NULL			4	/* Null */
++#define FC_SUBTYPE_CF_ACK		5	/* CF-Ack */
++#define FC_SUBTYPE_CF_POLL		6	/* CF-Poll */
++#define FC_SUBTYPE_CF_ACK_POLL		7	/* CF-Ack + CF-Poll */
++#define FC_SUBTYPE_QOS_DATA		8	/* QoS Data */
++#define FC_SUBTYPE_QOS_DATA_CF_ACK	9	/* QoS Data + CF-Ack */
++#define FC_SUBTYPE_QOS_DATA_CF_POLL	10	/* QoS Data + CF-Poll */
++#define FC_SUBTYPE_QOS_DATA_CF_ACK_POLL	11	/* QoS Data + CF-Ack + CF-Poll */
++#define FC_SUBTYPE_QOS_NULL		12	/* QoS Null */
++#define FC_SUBTYPE_QOS_CF_POLL		14	/* QoS CF-Poll */
++#define FC_SUBTYPE_QOS_CF_ACK_POLL	15	/* QoS CF-Ack + CF-Poll */
++
++/* Data Subtype Groups */
++#define FC_SUBTYPE_ANY_QOS(s)		(((s) & 8) != 0)
++#define FC_SUBTYPE_ANY_NULL(s)		(((s) & 4) != 0)
++#define FC_SUBTYPE_ANY_CF_POLL(s)	(((s) & 2) != 0)
++#define FC_SUBTYPE_ANY_CF_ACK(s)	(((s) & 1) != 0)
++#define FC_SUBTYPE_ANY_PSPOLL(s)	(((s) & 10) != 0)
++
++/* Type/Subtype Combos */
++#define FC_KIND_MASK		(FC_TYPE_MASK | FC_SUBTYPE_MASK)	/* FC kind mask */
++
++#define FC_KIND(t, s)	(((t) << FC_TYPE_SHIFT) | ((s) << FC_SUBTYPE_SHIFT))	/* FC kind */
++
++#define FC_SUBTYPE(fc)	(((fc) & FC_SUBTYPE_MASK) >> FC_SUBTYPE_SHIFT)	/* Subtype from FC */
++#define FC_TYPE(fc)	(((fc) & FC_TYPE_MASK) >> FC_TYPE_SHIFT)	/* Type from FC */
++
++#define FC_ASSOC_REQ	FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_REQ)	/* assoc. request */
++#define FC_ASSOC_RESP	FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_RESP)	/* assoc. response */
++#define FC_REASSOC_REQ	FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_REQ)	/* reassoc. request */
++#define FC_REASSOC_RESP	FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_RESP)	/* reassoc. response */
++#define FC_PROBE_REQ	FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_REQ)	/* probe request */
++#define FC_PROBE_RESP	FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_RESP)	/* probe response */
++#define FC_BEACON	FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_BEACON)		/* beacon */
++#define FC_ATIM		FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ATIM)		/* ATIM */
++#define FC_DISASSOC	FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DISASSOC)	/* disassoc */
++#define FC_AUTH		FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_AUTH)		/* authentication */
++#define FC_DEAUTH	FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DEAUTH)		/* deauthentication */
++#define FC_ACTION	FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ACTION)		/* action */
++#define FC_ACTION_NOACK	FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ACTION_NOACK)	/* action no-ack */
++
++#define FC_CTL_WRAPPER	FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CTL_WRAPPER)	/* Control Wrapper */
++#define FC_BLOCKACK_REQ	FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_BLOCKACK_REQ)	/* Block Ack Req */
++#define FC_BLOCKACK	FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_BLOCKACK)	/* Block Ack */
++#define FC_PS_POLL	FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_PS_POLL)	/* PS poll */
++#define FC_RTS		FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_RTS)		/* RTS */
++#define FC_CTS		FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CTS)		/* CTS */
++#define FC_ACK		FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_ACK)		/* ACK */
++#define FC_CF_END	FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END)		/* CF-END */
++#define FC_CF_END_ACK	FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END_ACK)	/* CF-END ACK */
++
++#define FC_DATA		FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA)		/* data */
++#define FC_NULL_DATA	FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_NULL)		/* null data */
++#define FC_DATA_CF_ACK	FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA_CF_ACK)	/* data CF ACK */
++#define FC_QOS_DATA	FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_DATA)	/* QoS data */
++#define FC_QOS_NULL	FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_NULL)	/* QoS null */
++
++/* QoS Control Field */
++
++/* 802.1D Priority */
++#define QOS_PRIO_SHIFT		0	/* QoS priority shift */
++#define QOS_PRIO_MASK		0x0007	/* QoS priority mask */
++#define QOS_PRIO(qos)		(((qos) & QOS_PRIO_MASK) >> QOS_PRIO_SHIFT)	/* QoS priority */
++
++/* Traffic Identifier */
++#define QOS_TID_SHIFT		0	/* QoS TID shift */
++#define QOS_TID_MASK		0x000f	/* QoS TID mask */
++#define QOS_TID(qos)		(((qos) & QOS_TID_MASK) >> QOS_TID_SHIFT)	/* QoS TID */
++
++/* End of Service Period (U-APSD) */
++#define QOS_EOSP_SHIFT		4	/* QoS End of Service Period shift */
++#define QOS_EOSP_MASK		0x0010	/* QoS End of Service Period mask */
++#define QOS_EOSP(qos)		(((qos) & QOS_EOSP_MASK) >> QOS_EOSP_SHIFT)	/* Qos EOSP */
++
++/* Ack Policy */
++#define QOS_ACK_NORMAL_ACK	0	/* Normal Ack */
++#define QOS_ACK_NO_ACK		1	/* No Ack (eg mcast) */
++#define QOS_ACK_NO_EXP_ACK	2	/* No Explicit Ack */
++#define QOS_ACK_BLOCK_ACK	3	/* Block Ack */
++#define QOS_ACK_SHIFT		5	/* QoS ACK shift */
++#define QOS_ACK_MASK		0x0060	/* QoS ACK mask */
++#define QOS_ACK(qos)		(((qos) & QOS_ACK_MASK) >> QOS_ACK_SHIFT)	/* QoS ACK */
++
++/* A-MSDU flag */
++#define QOS_AMSDU_SHIFT		7	/* AMSDU shift */
++#define QOS_AMSDU_MASK		0x0080	/* AMSDU mask */
++
++/* Management Frames */
++
++/* Management Frame Constants */
++
++/* Fixed fields */
++#define DOT11_MNG_AUTH_ALGO_LEN		2	/* d11 management auth. algo. length */
++#define DOT11_MNG_AUTH_SEQ_LEN		2	/* d11 management auth. seq. length */
++#define DOT11_MNG_BEACON_INT_LEN	2	/* d11 management beacon interval length */
++#define DOT11_MNG_CAP_LEN		2	/* d11 management cap. length */
++#define DOT11_MNG_AP_ADDR_LEN		6	/* d11 management AP address length */
++#define DOT11_MNG_LISTEN_INT_LEN	2	/* d11 management listen interval length */
++#define DOT11_MNG_REASON_LEN		2	/* d11 management reason length */
++#define DOT11_MNG_AID_LEN		2	/* d11 management AID length */
++#define DOT11_MNG_STATUS_LEN		2	/* d11 management status length */
++#define DOT11_MNG_TIMESTAMP_LEN		8	/* d11 management timestamp length */
++
++/* DUR/ID field in assoc resp is 0xc000 | AID */
++#define DOT11_AID_MASK			0x3fff	/* d11 AID mask */
++
++/* Reason Codes */
++#define DOT11_RC_RESERVED		0	/* d11 RC reserved */
++#define DOT11_RC_UNSPECIFIED		1	/* Unspecified reason */
++#define DOT11_RC_AUTH_INVAL		2	/* Previous authentication no longer valid */
++#define DOT11_RC_DEAUTH_LEAVING		3	/* Deauthenticated because sending station
++						 * is leaving (or has left) IBSS or ESS
++						 */
++#define DOT11_RC_INACTIVITY		4	/* Disassociated due to inactivity */
++#define DOT11_RC_BUSY			5	/* Disassociated because AP is unable to handle
++						 * all currently associated stations
++						 */
++#define DOT11_RC_INVAL_CLASS_2		6	/* Class 2 frame received from
++						 * nonauthenticated station
++						 */
++#define DOT11_RC_INVAL_CLASS_3		7	/* Class 3 frame received from
++						 *  nonassociated station
++						 */
++#define DOT11_RC_DISASSOC_LEAVING	8	/* Disassociated because sending station is
++						 * leaving (or has left) BSS
++						 */
++#define DOT11_RC_NOT_AUTH		9	/* Station requesting (re)association is not
++						 * authenticated with responding station
++						 */
++#define DOT11_RC_BAD_PC			10	/* Unacceptable power capability element */
++#define DOT11_RC_BAD_CHANNELS		11	/* Unacceptable supported channels element */
++
++/* 12 is unused by STA but could be used by AP/GO */
++#define DOT11_RC_DISASSOC_BTM		12	/* Disassociated due to BSS Transition Magmt */
++
++
++/* 32-39 are QSTA specific reasons added in 11e */
++#define DOT11_RC_UNSPECIFIED_QOS	32	/* unspecified QoS-related reason */
++#define DOT11_RC_INSUFFCIENT_BW		33	/* QAP lacks sufficient bandwidth */
++#define DOT11_RC_EXCESSIVE_FRAMES	34	/* excessive number of frames need ack */
++#define DOT11_RC_TX_OUTSIDE_TXOP	35	/* transmitting outside the limits of txop */
++#define DOT11_RC_LEAVING_QBSS		36	/* QSTA is leaving the QBSS (or restting) */
++#define DOT11_RC_BAD_MECHANISM		37	/* does not want to use the mechanism */
++#define DOT11_RC_SETUP_NEEDED		38	/* mechanism needs a setup */
++#define DOT11_RC_TIMEOUT		39	/* timeout */
++
++#define DOT11_RC_MESH_PEERING_CANCELLED		52
++#define DOT11_RC_MESH_MAX_PEERS			53
++#define DOT11_RC_MESH_CONFIG_POLICY_VIOLN	54
++#define DOT11_RC_MESH_CLOSE_RECVD		55
++#define DOT11_RC_MESH_MAX_RETRIES		56
++#define DOT11_RC_MESH_CONFIRM_TIMEOUT		57
++#define DOT11_RC_MESH_INVALID_GTK		58
++#define DOT11_RC_MESH_INCONSISTENT_PARAMS	59
++
++#define DOT11_RC_MESH_INVALID_SEC_CAP		60
++#define DOT11_RC_MESH_PATHERR_NOPROXYINFO	61
++#define DOT11_RC_MESH_PATHERR_NOFWINFO		62
++#define DOT11_RC_MESH_PATHERR_DSTUNREACH	63
++#define DOT11_RC_MESH_MBSSMAC_EXISTS		64
++#define DOT11_RC_MESH_CHANSWITCH_REGREQ		65
++#define DOT11_RC_MESH_CHANSWITCH_UNSPEC		66
++
++#define DOT11_RC_MAX			66	/* Reason codes > 66 are reserved */
++
++#define DOT11_RC_TDLS_PEER_UNREACH	25
++#define DOT11_RC_TDLS_DOWN_UNSPECIFIED	26
++
++/* Status Codes */
++#define DOT11_SC_SUCCESS		0	/* Successful */
++#define DOT11_SC_FAILURE		1	/* Unspecified failure */
++#define DOT11_SC_TDLS_WAKEUP_SCH_ALT 2	/* TDLS wakeup schedule rejected but alternative  */
++					/* schedule provided */
++#define DOT11_SC_TDLS_WAKEUP_SCH_REJ 3	/* TDLS wakeup schedule rejected */
++#define DOT11_SC_TDLS_SEC_DISABLED	5	/* TDLS Security disabled */
++#define DOT11_SC_LIFETIME_REJ		6	/* Unacceptable lifetime */
++#define DOT11_SC_NOT_SAME_BSS		7	/* Not in same BSS */
++#define DOT11_SC_CAP_MISMATCH		10	/* Cannot support all requested
++						 * capabilities in the Capability
++						 * Information field
++						 */
++#define DOT11_SC_REASSOC_FAIL		11	/* Reassociation denied due to inability
++						 * to confirm that association exists
++						 */
++#define DOT11_SC_ASSOC_FAIL		12	/* Association denied due to reason
++						 * outside the scope of this standard
++						 */
++#define DOT11_SC_AUTH_MISMATCH		13	/* Responding station does not support
++						 * the specified authentication
++						 * algorithm
++						 */
++#define DOT11_SC_AUTH_SEQ		14	/* Received an Authentication frame
++						 * with authentication transaction
++						 * sequence number out of expected
++						 * sequence
++						 */
++#define DOT11_SC_AUTH_CHALLENGE_FAIL	15	/* Authentication rejected because of
++						 * challenge failure
++						 */
++#define DOT11_SC_AUTH_TIMEOUT		16	/* Authentication rejected due to timeout
++						 * waiting for next frame in sequence
++						 */
++#define DOT11_SC_ASSOC_BUSY_FAIL	17	/* Association denied because AP is
++						 * unable to handle additional
++						 * associated stations
++						 */
++#define DOT11_SC_ASSOC_RATE_MISMATCH	18	/* Association denied due to requesting
++						 * station not supporting all of the
++						 * data rates in the BSSBasicRateSet
++						 * parameter
++						 */
++#define DOT11_SC_ASSOC_SHORT_REQUIRED	19	/* Association denied due to requesting
++						 * station not supporting the Short
++						 * Preamble option
++						 */
++#define DOT11_SC_ASSOC_PBCC_REQUIRED	20	/* Association denied due to requesting
++						 * station not supporting the PBCC
++						 * Modulation option
++						 */
++#define DOT11_SC_ASSOC_AGILITY_REQUIRED	21	/* Association denied due to requesting
++						 * station not supporting the Channel
++						 * Agility option
++						 */
++#define DOT11_SC_ASSOC_SPECTRUM_REQUIRED	22	/* Association denied because Spectrum
++							 * Management capability is required.
++							 */
++#define DOT11_SC_ASSOC_BAD_POWER_CAP	23	/* Association denied because the info
++						 * in the Power Cap element is
++						 * unacceptable.
++						 */
++#define DOT11_SC_ASSOC_BAD_SUP_CHANNELS	24	/* Association denied because the info
++						 * in the Supported Channel element is
++						 * unacceptable
++						 */
++#define DOT11_SC_ASSOC_SHORTSLOT_REQUIRED	25	/* Association denied due to requesting
++							 * station not supporting the Short Slot
++							 * Time option
++							 */
++#define DOT11_SC_ASSOC_DSSSOFDM_REQUIRED 26	/* Association denied because requesting station
++						 * does not support the DSSS-OFDM option
++						 */
++#define DOT11_SC_ASSOC_HT_REQUIRED	27	/* Association denied because the requesting
++						 * station does not support HT features
++						 */
++#define DOT11_SC_ASSOC_R0KH_UNREACHABLE	28	/* Association denied due to AP
++						 * being unable to reach the R0 Key Holder
++						 */
++#define DOT11_SC_ASSOC_TRY_LATER	30	/* Association denied temporarily, try again later
++						 */
++#define DOT11_SC_ASSOC_MFP_VIOLATION	31	/* Association denied due to Robust Management
++						 * frame policy violation
++						 */
++
++#define	DOT11_SC_DECLINED		37	/* request declined */
++#define	DOT11_SC_INVALID_PARAMS		38	/* One or more params have invalid values */
++#define DOT11_SC_INVALID_PAIRWISE_CIPHER	42 /* invalid pairwise cipher */
++#define	DOT11_SC_INVALID_AKMP		43	/* Association denied due to invalid AKMP */
++#define DOT11_SC_INVALID_RSNIE_CAP	45	/* invalid RSN IE capabilities */
++#define DOT11_SC_DLS_NOT_ALLOWED	48	/* DLS is not allowed in the BSS by policy */
++#define	DOT11_SC_INVALID_PMKID		53	/* Association denied due to invalid PMKID */
++#define	DOT11_SC_INVALID_MDID		54	/* Association denied due to invalid MDID */
++#define	DOT11_SC_INVALID_FTIE		55	/* Association denied due to invalid FTIE */
++
++#define DOT11_SC_ADV_PROTO_NOT_SUPPORTED	59	/* ad proto not supported */
++#define DOT11_SC_NO_OUTSTAND_REQ			60	/* no outstanding req */
++#define DOT11_SC_RSP_NOT_RX_FROM_SERVER		61	/* no response from server */
++#define DOT11_SC_TIMEOUT					62	/* timeout */
++#define DOT11_SC_QUERY_RSP_TOO_LARGE		63	/* query rsp too large */
++#define DOT11_SC_SERVER_UNREACHABLE			65	/* server unreachable */
++
++#define DOT11_SC_UNEXP_MSG			70	/* Unexpected message */
++#define DOT11_SC_INVALID_SNONCE		71	/* Invalid SNonce */
++#define DOT11_SC_INVALID_RSNIE		72	/* Invalid contents of RSNIE */
++
++#define DOT11_SC_ANTICLOG_TOCKEN_REQUIRED	76	/* Anti-clogging tocken required */
++#define DOT11_SC_INVALID_FINITE_CYCLIC_GRP	77	/* Invalid contents of RSNIE */
++
++#define DOT11_SC_ASSOC_VHT_REQUIRED	104	/* Association denied because the requesting
++						 * station does not support VHT features.
++						 */
++
++#define DOT11_SC_TRANSMIT_FAILURE	79	/* transmission failure */
++
++/* Info Elts, length of INFORMATION portion of Info Elts */
++#define DOT11_MNG_DS_PARAM_LEN			1	/* d11 management DS parameter length */
++#define DOT11_MNG_IBSS_PARAM_LEN		2	/* d11 management IBSS parameter length */
++
++/* TIM Info element has 3 bytes fixed info in INFORMATION field,
++ * followed by 1 to 251 bytes of Partial Virtual Bitmap
++ */
++#define DOT11_MNG_TIM_FIXED_LEN			3	/* d11 management TIM fixed length */
++#define DOT11_MNG_TIM_DTIM_COUNT		0	/* d11 management DTIM count */
++#define DOT11_MNG_TIM_DTIM_PERIOD		1	/* d11 management DTIM period */
++#define DOT11_MNG_TIM_BITMAP_CTL		2	/* d11 management TIM BITMAP control  */
++#define DOT11_MNG_TIM_PVB			3	/* d11 management TIM PVB */
++
++/* TLV defines */
++#define TLV_TAG_OFF		0	/* tag offset */
++#define TLV_LEN_OFF		1	/* length offset */
++#define TLV_HDR_LEN		2	/* header length */
++#define TLV_BODY_OFF		2	/* body offset */
++#define TLV_BODY_LEN_MAX	255	/* max body length */
++
++/* Management Frame Information Element IDs */
++#define DOT11_MNG_SSID_ID			0	/* d11 management SSID id */
++#define DOT11_MNG_RATES_ID			1	/* d11 management rates id */
++#define DOT11_MNG_FH_PARMS_ID			2	/* d11 management FH parameter id */
++#define DOT11_MNG_DS_PARMS_ID			3	/* d11 management DS parameter id */
++#define DOT11_MNG_CF_PARMS_ID			4	/* d11 management CF parameter id */
++#define DOT11_MNG_TIM_ID			5	/* d11 management TIM id */
++#define DOT11_MNG_IBSS_PARMS_ID			6	/* d11 management IBSS parameter id */
++#define DOT11_MNG_COUNTRY_ID			7	/* d11 management country id */
++#define DOT11_MNG_HOPPING_PARMS_ID		8	/* d11 management hopping parameter id */
++#define DOT11_MNG_HOPPING_TABLE_ID		9	/* d11 management hopping table id */
++#define DOT11_MNG_FTM_SYNC_INFO_ID		9	/* 11mc D4.3 */
++#define DOT11_MNG_REQUEST_ID			10	/* d11 management request id */
++#define DOT11_MNG_QBSS_LOAD_ID 			11	/* d11 management QBSS Load id */
++#define DOT11_MNG_EDCA_PARAM_ID			12	/* 11E EDCA Parameter id */
++#define DOT11_MNG_TSPEC_ID			13	/* d11 management TSPEC id */
++#define DOT11_MNG_TCLAS_ID			14	/* d11 management TCLAS id */
++#define DOT11_MNG_CHALLENGE_ID			16	/* d11 management chanllenge id */
++#define DOT11_MNG_PWR_CONSTRAINT_ID		32	/* 11H PowerConstraint */
++#define DOT11_MNG_PWR_CAP_ID			33	/* 11H PowerCapability */
++#define DOT11_MNG_TPC_REQUEST_ID 		34	/* 11H TPC Request */
++#define DOT11_MNG_TPC_REPORT_ID			35	/* 11H TPC Report */
++#define DOT11_MNG_SUPP_CHANNELS_ID		36	/* 11H Supported Channels */
++#define DOT11_MNG_CHANNEL_SWITCH_ID		37	/* 11H ChannelSwitch Announcement */
++#define DOT11_MNG_MEASURE_REQUEST_ID		38	/* 11H MeasurementRequest */
++#define DOT11_MNG_MEASURE_REPORT_ID		39	/* 11H MeasurementReport */
++#define DOT11_MNG_QUIET_ID			40	/* 11H Quiet */
++#define DOT11_MNG_IBSS_DFS_ID			41	/* 11H IBSS_DFS */
++#define DOT11_MNG_ERP_ID			42	/* d11 management ERP id */
++#define DOT11_MNG_TS_DELAY_ID			43	/* d11 management TS Delay id */
++#define DOT11_MNG_TCLAS_PROC_ID			44	/* d11 management TCLAS processing id */
++#define	DOT11_MNG_HT_CAP			45	/* d11 mgmt HT cap id */
++#define DOT11_MNG_QOS_CAP_ID			46	/* 11E QoS Capability id */
++#define DOT11_MNG_NONERP_ID			47	/* d11 management NON-ERP id */
++#define DOT11_MNG_RSN_ID			48	/* d11 management RSN id */
++#define DOT11_MNG_EXT_RATES_ID			50	/* d11 management ext. rates id */
++#define DOT11_MNG_AP_CHREP_ID			51	/* 11k AP Channel report id */
++#define DOT11_MNG_NEIGHBOR_REP_ID		52	/* 11k & 11v Neighbor report id */
++#define DOT11_MNG_RCPI_ID			53	/* 11k RCPI */
++#define DOT11_MNG_MDIE_ID			54	/* 11r Mobility domain id */
++#define DOT11_MNG_FTIE_ID			55	/* 11r Fast Bss Transition id */
++#define DOT11_MNG_FT_TI_ID			56	/* 11r Timeout Interval id */
++#define DOT11_MNG_RDE_ID			57	/* 11r RIC Data Element id */
++#define	DOT11_MNG_REGCLASS_ID			59	/* d11 management regulatory class id */
++#define DOT11_MNG_EXT_CSA_ID			60	/* d11 Extended CSA */
++#define	DOT11_MNG_HT_ADD			61	/* d11 mgmt additional HT info */
++#define	DOT11_MNG_EXT_CHANNEL_OFFSET		62	/* d11 mgmt ext channel offset */
++#define DOT11_MNG_BSS_AVR_ACCESS_DELAY_ID	63	/* 11k bss average access delay */
++#define DOT11_MNG_ANTENNA_ID			64	/* 11k antenna id */
++#define DOT11_MNG_RSNI_ID			65	/* 11k RSNI id */
++#define DOT11_MNG_MEASUREMENT_PILOT_TX_ID	66	/* 11k measurement pilot tx info id */
++#define DOT11_MNG_BSS_AVAL_ADMISSION_CAP_ID	67	/* 11k bss aval admission cap id */
++#define DOT11_MNG_BSS_AC_ACCESS_DELAY_ID	68	/* 11k bss AC access delay id */
++#define DOT11_MNG_WAPI_ID			68	/* d11 management WAPI id */
++#define DOT11_MNG_TIME_ADVERTISE_ID	69	/* 11p time advertisement */
++#define DOT11_MNG_RRM_CAP_ID		70	/* 11k radio measurement capability */
++#define DOT11_MNG_MULTIPLE_BSSID_ID		71	/* 11k multiple BSSID id */
++#define	DOT11_MNG_HT_BSS_COEXINFO_ID		72	/* d11 mgmt OBSS Coexistence INFO */
++#define	DOT11_MNG_HT_BSS_CHANNEL_REPORT_ID	73	/* d11 mgmt OBSS Intolerant Channel list */
++#define	DOT11_MNG_HT_OBSS_ID			74	/* d11 mgmt OBSS HT info */
++#define DOT11_MNG_MMIE_ID			76	/* d11 mgmt MIC IE */
++#define DOT11_MNG_FMS_DESCR_ID			86	/* 11v FMS descriptor */
++#define DOT11_MNG_FMS_REQ_ID			87	/* 11v FMS request id */
++#define DOT11_MNG_FMS_RESP_ID			88	/* 11v FMS response id */
++#define DOT11_MNG_BSS_MAX_IDLE_PERIOD_ID	90	/* 11v bss max idle id */
++#define DOT11_MNG_TFS_REQUEST_ID		91	/* 11v tfs request id */
++#define DOT11_MNG_TFS_RESPONSE_ID		92	/* 11v tfs response id */
++#define DOT11_MNG_WNM_SLEEP_MODE_ID		93	/* 11v wnm-sleep mode id */
++#define DOT11_MNG_TIMBC_REQ_ID			94	/* 11v TIM broadcast request id */
++#define DOT11_MNG_TIMBC_RESP_ID			95	/* 11v TIM broadcast response id */
++#define DOT11_MNG_CHANNEL_USAGE			97	/* 11v channel usage */
++#define DOT11_MNG_TIME_ZONE_ID			98	/* 11v time zone */
++#define DOT11_MNG_DMS_REQUEST_ID		99	/* 11v dms request id */
++#define DOT11_MNG_DMS_RESPONSE_ID		100	/* 11v dms response id */
++#define DOT11_MNG_LINK_IDENTIFIER_ID		101	/* 11z TDLS Link Identifier IE */
++#define DOT11_MNG_WAKEUP_SCHEDULE_ID		102	/* 11z TDLS Wakeup Schedule IE */
++#define DOT11_MNG_CHANNEL_SWITCH_TIMING_ID	104	/* 11z TDLS Channel Switch Timing IE */
++#define DOT11_MNG_PTI_CONTROL_ID		105	/* 11z TDLS PTI Control IE */
++#define DOT11_MNG_PU_BUFFER_STATUS_ID		106	/* 11z TDLS PU Buffer Status IE */
++#define DOT11_MNG_INTERWORKING_ID		107	/* 11u interworking */
++#define DOT11_MNG_ADVERTISEMENT_ID		108	/* 11u advertisement protocol */
++#define DOT11_MNG_EXP_BW_REQ_ID			109	/* 11u expedited bandwith request */
++#define DOT11_MNG_QOS_MAP_ID			110	/* 11u QoS map set */
++#define DOT11_MNG_ROAM_CONSORT_ID		111	/* 11u roaming consortium */
++#define DOT11_MNG_EMERGCY_ALERT_ID		112	/* 11u emergency alert identifier */
++#define DOT11_MNG_MESH_CONFIG			113	/* Mesh Configuration */
++#define DOT11_MNG_MESH_ID			114	/* Mesh ID */
++#define DOT11_MNG_MESH_PEER_MGMT_ID		117	/* Mesh PEER MGMT IE */
++#define DOT11_MNG_EXT_CAP_ID			127	/* d11 mgmt ext capability */
++#define DOT11_MNG_EXT_PREQ_ID			130	/* Mesh PREQ IE */
++#define DOT11_MNG_EXT_PREP_ID			131	/* Mesh PREP IE */
++#define DOT11_MNG_EXT_PERR_ID			132	/* Mesh PERR IE */
++#define	DOT11_MNG_VHT_CAP_ID			191	/* d11 mgmt VHT cap id */
++#define	DOT11_MNG_VHT_OPERATION_ID		192	/* d11 mgmt VHT op id */
++#define	DOT11_MNG_EXT_BSSLOAD_ID		193	/* d11 mgmt VHT extended bss load id */
++#define DOT11_MNG_WIDE_BW_CHANNEL_SWITCH_ID	194	/* Wide BW Channel Switch IE */
++#define DOT11_MNG_VHT_TRANSMIT_POWER_ENVELOPE_ID 195	/* VHT transmit Power Envelope IE */
++#define DOT11_MNG_CHANNEL_SWITCH_WRAPPER_ID	196	/* Channel Switch Wrapper IE */
++#define DOT11_MNG_AID_ID			197	/* Association ID  IE */
++#define	DOT11_MNG_OPER_MODE_NOTIF_ID		199	/* d11 mgmt VHT oper mode notif */
++#define DOT11_MNG_RNR_ID			201
++#define DOT11_MNG_HE_CAP_ID			202
++#define DOT11_MNG_HE_OP_ID			203
++#define DOT11_MNG_FTM_PARAMS_ID			206
++#define DOT11_MNG_TWT_ID			216	/* 11ah D5.0 */
++#define DOT11_MNG_WPA_ID			221	/* d11 management WPA id */
++#define DOT11_MNG_PROPR_ID			221
++/* should start using this one instead of above two */
++#define DOT11_MNG_VS_ID				221	/* d11 management Vendor Specific IE */
++#define DOT11_MNG_MESH_CSP_ID			222	/* d11 Mesh Channel Switch Parameter */
++#define DOT11_MNG_FILS_IND_ID			240	/* 11ai FILS Indication element */
++
++/* The follwing ID extensions should be defined >= 255
++ * i.e. the values should include 255 (DOT11_MNG_ID_EXT_ID + ID Extension).
++ */
++#define DOT11_MNG_ID_EXT_ID			255	/* Element ID Extension 11mc D4.3 */
++#define DOT11_MNG_RAPS_ID	(DOT11_MNG_ID_EXT_ID+11)  /* OFDMA Random Access Parameter Set */
++
++/* FILS ext ids */
++#define FILS_REQ_PARAMS_EXT_ID		2
++#define DOT11_MNG_FILS_REQ_PARAMS	(DOT11_MNG_ID_EXT_ID + FILS_REQ_PARAMS_EXT_ID)
++#define FILS_SESSION_EXT_ID		4
++#define DOT11_MNG_FILS_SESSION		(DOT11_MNG_ID_EXT_ID + FILS_SESSION_EXT_ID)
++#define FILS_HLP_CONTAINER_EXT_ID		5
++#define DOT11_MNG_FILS_HLP_CONTAINER		(DOT11_MNG_ID_EXT_ID + FILS_HLP_CONTAINER_EXT_ID)
++#define FILS_WRAPPED_DATA_EXT_ID	8
++#define DOT11_MNG_FILS_WRAPPED_DATA	(DOT11_MNG_ID_EXT_ID + FILS_WRAPPED_DATA_EXT_ID)
++#define FILS_NONCE_EXT_ID		13
++#define DOT11_MNG_FILS_NONCE		(DOT11_MNG_ID_EXT_ID + FILS_NONCE_EXT_ID)
++
++#define DOT11_MNG_IE_ID_EXT_MATCH(_ie, _id) (\
++	((_ie)->id == DOT11_MNG_ID_EXT_ID) && \
++	((_ie)->len > 0) && \
++	((_id) == ((uint8 *)(_ie) + TLV_HDR_LEN)[0]))
++
++#define DOT11_MNG_IE_ID_EXT_INIT(_ie, _id, _len) do {\
++		(_ie)->id = DOT11_MNG_ID_EXT_ID; \
++		(_ie)->len = _len; \
++		(_ie)->id_ext = _id; \
++	} while (0)
++
++/* Rate Defines */
++
++/* Valid rates for the Supported Rates and Extended Supported Rates IEs.
++ * Encoding is the rate in 500kbps units, rouding up for fractional values.
++ * 802.11-2012, section 6.5.5.2, DATA_RATE parameter enumerates all the values.
++ * The rate values cover DSSS, HR/DSSS, ERP, and OFDM phy rates.
++ * The defines below do not cover the rates specific to 10MHz, {3, 4.5, 27},
++ * and 5MHz, {1.5, 2.25, 3, 4.5, 13.5}, which are not supported by Broadcom devices.
++ */
++
++#define DOT11_RATE_1M   2       /* 1  Mbps in 500kbps units */
++#define DOT11_RATE_2M   4       /* 2  Mbps in 500kbps units */
++#define DOT11_RATE_5M5  11      /* 5.5 Mbps in 500kbps units */
++#define DOT11_RATE_11M  22      /* 11 Mbps in 500kbps units */
++#define DOT11_RATE_6M   12      /* 6  Mbps in 500kbps units */
++#define DOT11_RATE_9M   18      /* 9  Mbps in 500kbps units */
++#define DOT11_RATE_12M  24      /* 12 Mbps in 500kbps units */
++#define DOT11_RATE_18M  36      /* 18 Mbps in 500kbps units */
++#define DOT11_RATE_24M  48      /* 24 Mbps in 500kbps units */
++#define DOT11_RATE_36M  72      /* 36 Mbps in 500kbps units */
++#define DOT11_RATE_48M  96      /* 48 Mbps in 500kbps units */
++#define DOT11_RATE_54M  108     /* 54 Mbps in 500kbps units */
++#define DOT11_RATE_MAX  108     /* highest rate (54 Mbps) in 500kbps units */
++
++/* Supported Rates and Extended Supported Rates IEs
++ * The supported rates octets are defined a the MSB indicatin a Basic Rate
++ * and bits 0-6 as the rate value
++ */
++#define DOT11_RATE_BASIC                0x80 /* flag for a Basic Rate */
++#define DOT11_RATE_MASK                 0x7F /* mask for numeric part of rate */
++
++/* BSS Membership Selector parameters
++ * 802.11-2016 (and 802.11ax-D1.1), Sec 9.4.2.3
++ * These selector values are advertised in Supported Rates and Extended Supported Rates IEs
++ * in the supported rates list with the Basic rate bit set.
++ * Constants below include the basic bit.
++ */
++#define DOT11_BSS_MEMBERSHIP_HT         0xFF  /* Basic 0x80 + 127, HT Required to join */
++#define DOT11_BSS_MEMBERSHIP_VHT        0xFE  /* Basic 0x80 + 126, VHT Required to join */
++#define DOT11_BSS_MEMBERSHIP_HE         0xFD  /* Basic 0x80 + 125, HE Required to join */
++
++/* ERP info element bit values */
++#define DOT11_MNG_ERP_LEN			1	/* ERP is currently 1 byte long */
++#define DOT11_MNG_NONERP_PRESENT		0x01	/* NonERP (802.11b) STAs are present
++							 *in the BSS
++							 */
++#define DOT11_MNG_USE_PROTECTION		0x02	/* Use protection mechanisms for
++							 *ERP-OFDM frames
++							 */
++#define DOT11_MNG_BARKER_PREAMBLE		0x04	/* Short Preambles: 0 == allowed,
++							 * 1 == not allowed
++							 */
++/* TS Delay element offset & size */
++#define DOT11_MGN_TS_DELAY_LEN		4	/* length of TS DELAY IE */
++#define TS_DELAY_FIELD_SIZE			4	/* TS DELAY field size */
++
++/* Capability Information Field */
++#define DOT11_CAP_ESS				0x0001	/* d11 cap. ESS */
++#define DOT11_CAP_IBSS				0x0002	/* d11 cap. IBSS */
++#define DOT11_CAP_POLLABLE			0x0004	/* d11 cap. pollable */
++#define DOT11_CAP_POLL_RQ			0x0008	/* d11 cap. poll request */
++#define DOT11_CAP_PRIVACY			0x0010	/* d11 cap. privacy */
++#define DOT11_CAP_SHORT				0x0020	/* d11 cap. short */
++#define DOT11_CAP_PBCC				0x0040	/* d11 cap. PBCC */
++#define DOT11_CAP_AGILITY			0x0080	/* d11 cap. agility */
++#define DOT11_CAP_SPECTRUM			0x0100	/* d11 cap. spectrum */
++#define DOT11_CAP_QOS				0x0200	/* d11 cap. qos */
++#define DOT11_CAP_SHORTSLOT			0x0400	/* d11 cap. shortslot */
++#define DOT11_CAP_APSD				0x0800	/* d11 cap. apsd */
++#define DOT11_CAP_RRM				0x1000	/* d11 cap. 11k radio measurement */
++#define DOT11_CAP_CCK_OFDM			0x2000	/* d11 cap. CCK/OFDM */
++#define DOT11_CAP_DELAY_BA			0x4000	/* d11 cap. delayed block ack */
++#define DOT11_CAP_IMMEDIATE_BA			0x8000	/* d11 cap. immediate block ack */
++
++/* Extended capabilities IE bitfields */
++/* 20/40 BSS Coexistence Management support bit position */
++#define DOT11_EXT_CAP_OBSS_COEX_MGMT		0
++/* Extended Channel Switching support bit position */
++#define DOT11_EXT_CAP_EXT_CHAN_SWITCHING	2
++/* scheduled PSMP support bit position */
++#define DOT11_EXT_CAP_SPSMP			6
++/*  Flexible Multicast Service */
++#define DOT11_EXT_CAP_FMS			11
++/* proxy ARP service support bit position */
++#define DOT11_EXT_CAP_PROXY_ARP			12
++/* Civic Location */
++#define DOT11_EXT_CAP_CIVIC_LOC			14
++/* Geospatial Location */
++#define DOT11_EXT_CAP_LCI			15
++/* Traffic Filter Service */
++#define DOT11_EXT_CAP_TFS			16
++/* WNM-Sleep Mode */
++#define DOT11_EXT_CAP_WNM_SLEEP			17
++/* TIM Broadcast service */
++#define DOT11_EXT_CAP_TIMBC			18
++/* BSS Transition Management support bit position */
++#define DOT11_EXT_CAP_BSSTRANS_MGMT		19
++/* Direct Multicast Service */
++#define DOT11_EXT_CAP_DMS			26
++/* Interworking support bit position */
++#define DOT11_EXT_CAP_IW			31
++/* QoS map support bit position */
++#define DOT11_EXT_CAP_QOS_MAP		32
++/* service Interval granularity bit position and mask */
++#define DOT11_EXT_CAP_SI			41
++#define DOT11_EXT_CAP_SI_MASK			0x0E
++/* Location Identifier service */
++#define DOT11_EXT_CAP_IDENT_LOC			44
++/* WNM notification */
++#define DOT11_EXT_CAP_WNM_NOTIF			46
++/* Operating mode notification - VHT (11ac D3.0 - 8.4.2.29) */
++#define DOT11_EXT_CAP_OPER_MODE_NOTIF		62
++/* Fine timing measurement - D3.0 */
++#define DOT11_EXT_CAP_FTM_RESPONDER		70
++#define DOT11_EXT_CAP_FTM_INITIATOR		71 /* tentative 11mcd3.0 */
++/* TWT support */
++#define DOT11_EXT_CAP_TWT_REQUESTER		75
++#define DOT11_EXT_CAP_TWT_RESPONDER		76
++/* TODO: Update DOT11_EXT_CAP_MAX_IDX to reflect the highest offset.
++ * Note: DOT11_EXT_CAP_MAX_IDX must only be used in attach path.
++ *       It will cause ROM invalidation otherwise.
++ */
++#define DOT11_EXT_CAP_MAX_IDX	76
++
++#ifdef WL_FTM
++#define DOT11_EXT_CAP_MAX_BIT_IDX		95	/* !!!update this please!!! */
++#else
++#define DOT11_EXT_CAP_MAX_BIT_IDX		62	/* !!!update this please!!! */
++#endif
++/* extended capability */
++#ifndef DOT11_EXTCAP_LEN_MAX
++#define DOT11_EXTCAP_LEN_MAX ((DOT11_EXT_CAP_MAX_BIT_IDX + 8) >> 3)
++#endif
++BWL_PRE_PACKED_STRUCT struct dot11_extcap {
++	uint8 extcap[DOT11_EXTCAP_LEN_MAX];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_extcap dot11_extcap_t;
++
++/* VHT Operating mode bit fields -  (11ac D8.0/802.11-2016 - 9.4.1.53) */
++#define DOT11_OPER_MODE_CHANNEL_WIDTH_SHIFT 0
++#define DOT11_OPER_MODE_CHANNEL_WIDTH_MASK 0x3
++#define DOT11_OPER_MODE_160_8080_BW_SHIFT 2
++#define DOT11_OPER_MODE_160_8080_BW_MASK 0x04
++#define DOT11_OPER_MODE_NOLDPC_SHIFT 3
++#define DOT11_OPER_MODE_NOLDPC_MASK 0x08
++#define DOT11_OPER_MODE_RXNSS_SHIFT 4
++#define DOT11_OPER_MODE_RXNSS_MASK 0x70
++#define DOT11_OPER_MODE_RXNSS_TYPE_SHIFT 7
++#define DOT11_OPER_MODE_RXNSS_TYPE_MASK 0x80
++
++#define DOT11_OPER_MODE(type, nss, chanw) (\
++	((type) << DOT11_OPER_MODE_RXNSS_TYPE_SHIFT &\
++		 DOT11_OPER_MODE_RXNSS_TYPE_MASK) |\
++	(((nss) - 1) << DOT11_OPER_MODE_RXNSS_SHIFT & DOT11_OPER_MODE_RXNSS_MASK) |\
++	((chanw) << DOT11_OPER_MODE_CHANNEL_WIDTH_SHIFT &\
++		 DOT11_OPER_MODE_CHANNEL_WIDTH_MASK))
++
++#define DOT11_D8_OPER_MODE(type, nss, ldpc, bw160_8080, chanw) (\
++	((type) << DOT11_OPER_MODE_RXNSS_TYPE_SHIFT &\
++		 DOT11_OPER_MODE_RXNSS_TYPE_MASK) |\
++	(((nss) - 1) << DOT11_OPER_MODE_RXNSS_SHIFT & DOT11_OPER_MODE_RXNSS_MASK) |\
++	((ldpc) << DOT11_OPER_MODE_NOLDPC_SHIFT & DOT11_OPER_MODE_NOLDPC_MASK) |\
++	((bw160_8080) << DOT11_OPER_MODE_160_8080_BW_SHIFT &\
++		 DOT11_OPER_MODE_160_8080_BW_MASK) |\
++	((chanw) << DOT11_OPER_MODE_CHANNEL_WIDTH_SHIFT &\
++		 DOT11_OPER_MODE_CHANNEL_WIDTH_MASK))
++
++#define DOT11_OPER_MODE_CHANNEL_WIDTH(mode) \
++	(((mode) & DOT11_OPER_MODE_CHANNEL_WIDTH_MASK)\
++		>> DOT11_OPER_MODE_CHANNEL_WIDTH_SHIFT)
++#define DOT11_OPER_MODE_160_8080(mode) \
++	(((mode) & DOT11_OPER_MODE_160_8080_BW_MASK)\
++		>> DOT11_OPER_MODE_160_8080_BW_SHIFT)
++#define DOT11_OPER_MODE_RXNSS(mode) \
++	((((mode) & DOT11_OPER_MODE_RXNSS_MASK)		\
++		>> DOT11_OPER_MODE_RXNSS_SHIFT) + 1)
++#define DOT11_OPER_MODE_RXNSS_TYPE(mode) \
++	(((mode) & DOT11_OPER_MODE_RXNSS_TYPE_MASK)\
++		>> DOT11_OPER_MODE_RXNSS_TYPE_SHIFT)
++
++#define DOT11_OPER_MODE_20MHZ 0
++#define DOT11_OPER_MODE_40MHZ 1
++#define DOT11_OPER_MODE_80MHZ 2
++#define DOT11_OPER_MODE_160MHZ 3
++#define DOT11_OPER_MODE_8080MHZ 3
++#define DOT11_OPER_MODE_1608080MHZ 1
++
++#define DOT11_OPER_MODE_CHANNEL_WIDTH_20MHZ(mode) (\
++	((mode) & DOT11_OPER_MODE_CHANNEL_WIDTH_MASK) == DOT11_OPER_MODE_20MHZ)
++#define DOT11_OPER_MODE_CHANNEL_WIDTH_40MHZ(mode) (\
++	((mode) & DOT11_OPER_MODE_CHANNEL_WIDTH_MASK) == DOT11_OPER_MODE_40MHZ)
++#define DOT11_OPER_MODE_CHANNEL_WIDTH_80MHZ(mode) (\
++	((mode) & DOT11_OPER_MODE_CHANNEL_WIDTH_MASK) == DOT11_OPER_MODE_80MHZ)
++#define DOT11_OPER_MODE_CHANNEL_WIDTH_160MHZ(mode) (\
++	((mode) & DOT11_OPER_MODE_160_8080_BW_MASK))
++#define DOT11_OPER_MODE_CHANNEL_WIDTH_8080MHZ(mode) (\
++	((mode) & DOT11_OPER_MODE_160_8080_BW_MASK))
++
++/* Operating mode information element 802.11ac D3.0 - 8.4.2.168 */
++BWL_PRE_PACKED_STRUCT struct dot11_oper_mode_notif_ie {
++	uint8 mode;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_oper_mode_notif_ie dot11_oper_mode_notif_ie_t;
++
++#define DOT11_OPER_MODE_NOTIF_IE_LEN 1
++
++/* Extended Capability Information Field */
++#define DOT11_OBSS_COEX_MNG_SUPPORT	0x01	/* 20/40 BSS Coexistence Management support */
++
++/*
++ * Action Frame Constants
++ */
++#define DOT11_ACTION_HDR_LEN		2	/* action frame category + action field */
++#define DOT11_ACTION_CAT_OFF		0	/* category offset */
++#define DOT11_ACTION_ACT_OFF		1	/* action offset */
++
++/* Action Category field (sec 8.4.1.11) */
++#define DOT11_ACTION_CAT_ERR_MASK	0x80	/* category error mask */
++#define DOT11_ACTION_CAT_MASK		0x7F	/* category mask */
++#define DOT11_ACTION_CAT_SPECT_MNG	0	/* category spectrum management */
++#define DOT11_ACTION_CAT_QOS		1	/* category QoS */
++#define DOT11_ACTION_CAT_DLS		2	/* category DLS */
++#define DOT11_ACTION_CAT_BLOCKACK	3	/* category block ack */
++#define DOT11_ACTION_CAT_PUBLIC		4	/* category public */
++#define DOT11_ACTION_CAT_RRM		5	/* category radio measurements */
++#define DOT11_ACTION_CAT_FBT	6	/* category fast bss transition */
++#define DOT11_ACTION_CAT_HT		7	/* category for HT */
++#define	DOT11_ACTION_CAT_SA_QUERY	8	/* security association query */
++#define	DOT11_ACTION_CAT_PDPA		9	/* protected dual of public action */
++#define DOT11_ACTION_CAT_WNM		10	/* category for WNM */
++#define DOT11_ACTION_CAT_UWNM		11	/* category for Unprotected WNM */
++#define DOT11_ACTION_CAT_MESH		13	/* category for Mesh */
++#define DOT11_ACTION_CAT_SELFPROT	15	/* category for Mesh, self protected */
++#define DOT11_ACTION_NOTIFICATION	17
++#define DOT11_ACTION_CAT_VHT		21	/* VHT action */
++#define DOT11_ACTION_CAT_S1G		22	/* S1G action */
++#define DOT11_ACTION_CAT_HE		27	/* HE action frame */
++#define DOT11_ACTION_CAT_FILS		26	/* FILS action frame */
++#define DOT11_ACTION_CAT_VSP		126	/* protected vendor specific */
++#define DOT11_ACTION_CAT_VS		127	/* category Vendor Specific */
++
++/* Spectrum Management Action IDs (sec 7.4.1) */
++#define DOT11_SM_ACTION_M_REQ		0	/* d11 action measurement request */
++#define DOT11_SM_ACTION_M_REP		1	/* d11 action measurement response */
++#define DOT11_SM_ACTION_TPC_REQ		2	/* d11 action TPC request */
++#define DOT11_SM_ACTION_TPC_REP		3	/* d11 action TPC response */
++#define DOT11_SM_ACTION_CHANNEL_SWITCH	4	/* d11 action channel switch */
++#define DOT11_SM_ACTION_EXT_CSA		5	/* d11 extened CSA for 11n */
++
++/* QoS action ids */
++#define DOT11_QOS_ACTION_ADDTS_REQ	0	/* d11 action ADDTS request */
++#define DOT11_QOS_ACTION_ADDTS_RESP	1	/* d11 action ADDTS response */
++#define DOT11_QOS_ACTION_DELTS		2	/* d11 action DELTS */
++#define DOT11_QOS_ACTION_SCHEDULE	3	/* d11 action schedule */
++#define DOT11_QOS_ACTION_QOS_MAP	4	/* d11 action QOS map */
++
++/* HT action ids */
++#define DOT11_ACTION_ID_HT_CH_WIDTH	0	/* notify channel width action id */
++#define DOT11_ACTION_ID_HT_MIMO_PS	1	/* mimo ps action id */
++
++/* Public action ids */
++#define DOT11_PUB_ACTION_BSS_COEX_MNG	0	/* 20/40 Coexistence Management action id */
++#define DOT11_PUB_ACTION_CHANNEL_SWITCH	4	/* d11 action channel switch */
++#define DOT11_PUB_ACTION_VENDOR_SPEC	9	/* Vendor specific */
++#define DOT11_PUB_ACTION_GAS_CB_REQ	12	/* GAS Comeback Request */
++#define DOT11_PUB_ACTION_FTM_REQ	32		/* FTM request */
++#define DOT11_PUB_ACTION_FTM		33		/* FTM measurement */
++
++/* Block Ack action types */
++#define DOT11_BA_ACTION_ADDBA_REQ	0	/* ADDBA Req action frame type */
++#define DOT11_BA_ACTION_ADDBA_RESP	1	/* ADDBA Resp action frame type */
++#define DOT11_BA_ACTION_DELBA		2	/* DELBA action frame type */
++
++/* ADDBA action parameters */
++#define DOT11_ADDBA_PARAM_AMSDU_SUP	0x0001	/* AMSDU supported under BA */
++#define DOT11_ADDBA_PARAM_POLICY_MASK	0x0002	/* policy mask(ack vs delayed) */
++#define DOT11_ADDBA_PARAM_POLICY_SHIFT	1	/* policy shift */
++#define DOT11_ADDBA_PARAM_TID_MASK	0x003c	/* tid mask */
++#define DOT11_ADDBA_PARAM_TID_SHIFT	2	/* tid shift */
++#define DOT11_ADDBA_PARAM_BSIZE_MASK	0xffc0	/* buffer size mask */
++#define DOT11_ADDBA_PARAM_BSIZE_SHIFT	6	/* buffer size shift */
++
++#define DOT11_ADDBA_POLICY_DELAYED	0	/* delayed BA policy */
++#define DOT11_ADDBA_POLICY_IMMEDIATE	1	/* immediate BA policy */
++
++/* Fast Transition action types */
++#define DOT11_FT_ACTION_FT_RESERVED		0
++#define DOT11_FT_ACTION_FT_REQ			1	/* FBT request - for over-the-DS FBT */
++#define DOT11_FT_ACTION_FT_RES			2	/* FBT response - for over-the-DS FBT */
++#define DOT11_FT_ACTION_FT_CON			3	/* FBT confirm - for OTDS with RRP */
++#define DOT11_FT_ACTION_FT_ACK			4	/* FBT ack */
++
++/* DLS action types */
++#define DOT11_DLS_ACTION_REQ			0	/* DLS Request */
++#define DOT11_DLS_ACTION_RESP			1	/* DLS Response */
++#define DOT11_DLS_ACTION_TD			2	/* DLS Teardown */
++
++/* Wireless Network Management (WNM) action types */
++#define DOT11_WNM_ACTION_EVENT_REQ		0
++#define DOT11_WNM_ACTION_EVENT_REP		1
++#define DOT11_WNM_ACTION_DIAG_REQ		2
++#define DOT11_WNM_ACTION_DIAG_REP		3
++#define DOT11_WNM_ACTION_LOC_CFG_REQ		4
++#define DOT11_WNM_ACTION_LOC_RFG_RESP		5
++#define DOT11_WNM_ACTION_BSSTRANS_QUERY		6
++#define DOT11_WNM_ACTION_BSSTRANS_REQ		7
++#define DOT11_WNM_ACTION_BSSTRANS_RESP		8
++#define DOT11_WNM_ACTION_FMS_REQ		9
++#define DOT11_WNM_ACTION_FMS_RESP		10
++#define DOT11_WNM_ACTION_COL_INTRFRNCE_REQ	11
++#define DOT11_WNM_ACTION_COL_INTRFRNCE_REP	12
++#define DOT11_WNM_ACTION_TFS_REQ		13
++#define DOT11_WNM_ACTION_TFS_RESP		14
++#define DOT11_WNM_ACTION_TFS_NOTIFY_REQ		15
++#define DOT11_WNM_ACTION_WNM_SLEEP_REQ		16
++#define DOT11_WNM_ACTION_WNM_SLEEP_RESP		17
++#define DOT11_WNM_ACTION_TIMBC_REQ		18
++#define DOT11_WNM_ACTION_TIMBC_RESP		19
++#define DOT11_WNM_ACTION_QOS_TRFC_CAP_UPD	20
++#define DOT11_WNM_ACTION_CHAN_USAGE_REQ		21
++#define DOT11_WNM_ACTION_CHAN_USAGE_RESP	22
++#define DOT11_WNM_ACTION_DMS_REQ		23
++#define DOT11_WNM_ACTION_DMS_RESP		24
++#define DOT11_WNM_ACTION_TMNG_MEASUR_REQ	25
++#define DOT11_WNM_ACTION_NOTFCTN_REQ		26
++#define DOT11_WNM_ACTION_NOTFCTN_RESP		27
++#define DOT11_WNM_ACTION_TFS_NOTIFY_RESP	28
++
++/* Unprotected Wireless Network Management (WNM) action types */
++#define DOT11_UWNM_ACTION_TIM			0
++#define DOT11_UWNM_ACTION_TIMING_MEASUREMENT	1
++
++#define DOT11_MNG_COUNTRY_ID_LEN 3
++
++/* VHT category action types - 802.11ac D3.0 - 8.5.23.1 */
++#define DOT11_VHT_ACTION_CBF				0	/* Compressed Beamforming */
++#define DOT11_VHT_ACTION_GID_MGMT			1	/* Group ID Management */
++#define DOT11_VHT_ACTION_OPER_MODE_NOTIF	2	/* Operating mode notif'n */
++
++/* FILS category action types - 802.11ai D11.0 - 9.6.8.1 */
++#define DOT11_FILS_ACTION_DISCOVERY		34	/* FILS Discovery */
++
++/** DLS Request frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_dls_req {
++	uint8 category;			/* category of action frame (2) */
++	uint8 action;				/* DLS action: req (0) */
++	struct ether_addr	da;		/* destination address */
++	struct ether_addr	sa;		/* source address */
++	uint16 cap;				/* capability */
++	uint16 timeout;			/* timeout value */
++	uint8 data[1];				/* IE:support rate, extend support rate, HT cap */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_dls_req dot11_dls_req_t;
++#define DOT11_DLS_REQ_LEN 18	/* Fixed length */
++
++/** DLS response frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_dls_resp {
++	uint8 category;			/* category of action frame (2) */
++	uint8 action;				/* DLS action: req (0) */
++	uint16 status;				/* status code field */
++	struct ether_addr	da;		/* destination address */
++	struct ether_addr	sa;		/* source address */
++	uint8 data[1];				/* optional: capability, rate ... */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_dls_resp dot11_dls_resp_t;
++#define DOT11_DLS_RESP_LEN 16	/* Fixed length */
++
++
++/* ************* 802.11v related definitions. ************* */
++
++/** BSS Management Transition Query frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_bsstrans_query {
++	uint8 category;			/* category of action frame (10) */
++	uint8 action;			/* WNM action: trans_query (6) */
++	uint8 token;			/* dialog token */
++	uint8 reason;			/* transition query reason */
++	uint8 data[1];			/* Elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_bsstrans_query dot11_bsstrans_query_t;
++#define DOT11_BSSTRANS_QUERY_LEN 4	/* Fixed length */
++
++/* BTM transition reason */
++#define DOT11_BSSTRANS_REASON_UNSPECIFIED		0
++#define DOT11_BSSTRANS_REASON_EXC_FRAME_LOSS		1
++#define DOT11_BSSTRANS_REASON_EXC_TRAFFIC_DELAY		2
++#define DOT11_BSSTRANS_REASON_INSUFF_QOS_CAPACITY	3
++#define DOT11_BSSTRANS_REASON_FIRST_ASSOC		4
++#define DOT11_BSSTRANS_REASON_LOAD_BALANCING		5
++#define DOT11_BSSTRANS_REASON_BETTER_AP_FOUND		6
++#define DOT11_BSSTRANS_REASON_DEAUTH_RX			7
++#define DOT11_BSSTRANS_REASON_8021X_EAP_AUTH_FAIL	8
++#define DOT11_BSSTRANS_REASON_4WAY_HANDSHK_FAIL		9
++#define DOT11_BSSTRANS_REASON_MANY_REPLAYCNT_FAIL	10
++#define DOT11_BSSTRANS_REASON_MANY_DATAMIC_FAIL		11
++#define DOT11_BSSTRANS_REASON_EXCEED_MAX_RETRANS	12
++#define DOT11_BSSTRANS_REASON_MANY_BCAST_DISASSOC_RX	13
++#define DOT11_BSSTRANS_REASON_MANY_BCAST_DEAUTH_RX	14
++#define DOT11_BSSTRANS_REASON_PREV_TRANSITION_FAIL	15
++#define DOT11_BSSTRANS_REASON_LOW_RSSI			16
++#define DOT11_BSSTRANS_REASON_ROAM_FROM_NON_80211	17
++#define DOT11_BSSTRANS_REASON_RX_BTM_REQ		18
++#define DOT11_BSSTRANS_REASON_PREF_LIST_INCLUDED	19
++#define DOT11_BSSTRANS_REASON_LEAVING_ESS		20
++
++/** BSS Management Transition Request frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_bsstrans_req {
++	uint8 category;			/* category of action frame (10) */
++	uint8 action;			/* WNM action: trans_req (7) */
++	uint8 token;			/* dialog token */
++	uint8 reqmode;			/* transition request mode */
++	uint16 disassoc_tmr;		/* disassociation timer */
++	uint8 validity_intrvl;		/* validity interval */
++	uint8 data[1];			/* optional: BSS term duration, ... */
++						/* ...session info URL, candidate list */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_bsstrans_req dot11_bsstrans_req_t;
++#define DOT11_BSSTRANS_REQ_LEN 7	/* Fixed length */
++
++/* BSS Mgmt Transition Request Mode Field - 802.11v */
++#define DOT11_BSSTRANS_REQMODE_PREF_LIST_INCL		0x01
++#define DOT11_BSSTRANS_REQMODE_ABRIDGED			0x02
++#define DOT11_BSSTRANS_REQMODE_DISASSOC_IMMINENT	0x04
++#define DOT11_BSSTRANS_REQMODE_BSS_TERM_INCL		0x08
++#define DOT11_BSSTRANS_REQMODE_ESS_DISASSOC_IMNT	0x10
++
++/** BSS Management transition response frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_bsstrans_resp {
++	uint8 category;			/* category of action frame (10) */
++	uint8 action;			/* WNM action: trans_resp (8) */
++	uint8 token;			/* dialog token */
++	uint8 status;			/* transition status */
++	uint8 term_delay;		/* validity interval */
++	uint8 data[1];			/* optional: BSSID target, candidate list */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_bsstrans_resp dot11_bsstrans_resp_t;
++#define DOT11_BSSTRANS_RESP_LEN 5	/* Fixed length */
++
++/* BSS Mgmt Transition Response Status Field */
++#define DOT11_BSSTRANS_RESP_STATUS_ACCEPT			0
++#define DOT11_BSSTRANS_RESP_STATUS_REJECT			1
++#define DOT11_BSSTRANS_RESP_STATUS_REJ_INSUFF_BCN		2
++#define DOT11_BSSTRANS_RESP_STATUS_REJ_INSUFF_CAP		3
++#define DOT11_BSSTRANS_RESP_STATUS_REJ_TERM_UNDESIRED		4
++#define DOT11_BSSTRANS_RESP_STATUS_REJ_TERM_DELAY_REQ		5
++#define DOT11_BSSTRANS_RESP_STATUS_REJ_BSS_LIST_PROVIDED	6
++#define DOT11_BSSTRANS_RESP_STATUS_REJ_NO_SUITABLE_BSS		7
++#define DOT11_BSSTRANS_RESP_STATUS_REJ_LEAVING_ESS		8
++
++
++/** BSS Max Idle Period element */
++BWL_PRE_PACKED_STRUCT struct dot11_bss_max_idle_period_ie {
++	uint8 id;				/* 90, DOT11_MNG_BSS_MAX_IDLE_PERIOD_ID */
++	uint8 len;
++	uint16 max_idle_period;			/* in unit of 1000 TUs */
++	uint8 idle_opt;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_bss_max_idle_period_ie dot11_bss_max_idle_period_ie_t;
++#define DOT11_BSS_MAX_IDLE_PERIOD_IE_LEN	3	/* bss max idle period IE size */
++#define DOT11_BSS_MAX_IDLE_PERIOD_OPT_PROTECTED	1	/* BSS max idle option */
++
++/** TIM Broadcast request element */
++BWL_PRE_PACKED_STRUCT struct dot11_timbc_req_ie {
++	uint8 id;				/* 94, DOT11_MNG_TIMBC_REQ_ID */
++	uint8 len;
++	uint8 interval;				/* in unit of beacon interval */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_timbc_req_ie dot11_timbc_req_ie_t;
++#define DOT11_TIMBC_REQ_IE_LEN		1	/* Fixed length */
++
++/** TIM Broadcast request frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_timbc_req {
++	uint8 category;				/* category of action frame (10) */
++	uint8 action;				/* WNM action: DOT11_WNM_ACTION_TIMBC_REQ(18) */
++	uint8 token;				/* dialog token */
++	uint8 data[1];				/* TIM broadcast request element */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_timbc_req dot11_timbc_req_t;
++#define DOT11_TIMBC_REQ_LEN		3	/* Fixed length */
++
++/** TIM Broadcast response element */
++BWL_PRE_PACKED_STRUCT struct dot11_timbc_resp_ie {
++	uint8 id;				/* 95, DOT11_MNG_TIM_BROADCAST_RESP_ID */
++	uint8 len;
++	uint8 status;				/* status of add request */
++	uint8 interval;				/* in unit of beacon interval */
++	int32 offset;				/* in unit of ms */
++	uint16 high_rate;			/* in unit of 0.5 Mb/s */
++	uint16 low_rate;			/* in unit of 0.5 Mb/s */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_timbc_resp_ie dot11_timbc_resp_ie_t;
++#define DOT11_TIMBC_DENY_RESP_IE_LEN	1	/* Deny. Fixed length */
++#define DOT11_TIMBC_ACCEPT_RESP_IE_LEN	10	/* Accept. Fixed length */
++
++#define DOT11_TIMBC_STATUS_ACCEPT		0
++#define DOT11_TIMBC_STATUS_ACCEPT_TSTAMP	1
++#define DOT11_TIMBC_STATUS_DENY			2
++#define DOT11_TIMBC_STATUS_OVERRIDDEN		3
++#define DOT11_TIMBC_STATUS_RESERVED		4
++
++/** TIM Broadcast request frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_timbc_resp {
++	uint8 category;			/* category of action frame (10) */
++	uint8 action;			/* action: DOT11_WNM_ACTION_TIMBC_RESP(19) */
++	uint8 token;			/* dialog token */
++	uint8 data[1];			/* TIM broadcast response element */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_timbc_resp dot11_timbc_resp_t;
++#define DOT11_TIMBC_RESP_LEN	3	/* Fixed length */
++
++/** TIM element */
++BWL_PRE_PACKED_STRUCT struct dot11_tim_ie {
++	uint8 id;			/* 5, DOT11_MNG_TIM_ID	 */
++	uint8 len;			/* 4 - 255 */
++	uint8 dtim_count;		/* DTIM decrementing counter */
++	uint8 dtim_period;		/* DTIM period */
++	uint8 bitmap_control;		/* AID 0 + bitmap offset */
++	uint8 pvb[1];			/* Partial Virtual Bitmap, variable length */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tim_ie dot11_tim_ie_t;
++#define DOT11_TIM_IE_FIXED_LEN	3	/* Fixed length, without id and len */
++#define DOT11_TIM_IE_FIXED_TOTAL_LEN	5	/* Fixed length, with id and len */
++
++/** TIM Broadcast frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_timbc {
++	uint8 category;			/* category of action frame (11) */
++	uint8 action;			/* action: TIM (0) */
++	uint8 check_beacon;		/* need to check-beacon */
++	uint8 tsf[8];			/* Time Synchronization Function */
++	dot11_tim_ie_t tim_ie;		/* TIM element */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_timbc dot11_timbc_t;
++#define DOT11_TIMBC_HDR_LEN	(sizeof(dot11_timbc_t) - sizeof(dot11_tim_ie_t))
++#define DOT11_TIMBC_FIXED_LEN	(sizeof(dot11_timbc_t) - 1)	/* Fixed length */
++#define DOT11_TIMBC_LEN			11	/* Fixed length */
++
++/** TCLAS frame classifier type */
++BWL_PRE_PACKED_STRUCT struct dot11_tclas_fc_hdr {
++	uint8 type;
++	uint8 mask;
++	uint8 data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tclas_fc_hdr dot11_tclas_fc_hdr_t;
++#define DOT11_TCLAS_FC_HDR_LEN		2	/* Fixed length */
++
++#define DOT11_TCLAS_MASK_0		0x1
++#define DOT11_TCLAS_MASK_1		0x2
++#define DOT11_TCLAS_MASK_2		0x4
++#define DOT11_TCLAS_MASK_3		0x8
++#define DOT11_TCLAS_MASK_4		0x10
++#define DOT11_TCLAS_MASK_5		0x20
++#define DOT11_TCLAS_MASK_6		0x40
++#define DOT11_TCLAS_MASK_7		0x80
++
++#define DOT11_TCLAS_FC_0_ETH		0
++#define DOT11_TCLAS_FC_1_IP		1
++#define DOT11_TCLAS_FC_2_8021Q		2
++#define DOT11_TCLAS_FC_3_OFFSET		3
++#define DOT11_TCLAS_FC_4_IP_HIGHER	4
++#define DOT11_TCLAS_FC_5_8021D		5
++
++/** TCLAS frame classifier type 0 parameters for Ethernet */
++BWL_PRE_PACKED_STRUCT struct dot11_tclas_fc_0_eth {
++	uint8 type;
++	uint8 mask;
++	uint8 sa[ETHER_ADDR_LEN];
++	uint8 da[ETHER_ADDR_LEN];
++	uint16 eth_type;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tclas_fc_0_eth dot11_tclas_fc_0_eth_t;
++#define DOT11_TCLAS_FC_0_ETH_LEN	16
++
++/** TCLAS frame classifier type 1 parameters for IPV4 */
++BWL_PRE_PACKED_STRUCT struct dot11_tclas_fc_1_ipv4 {
++	uint8 type;
++	uint8 mask;
++	uint8 version;
++	uint32 src_ip;
++	uint32 dst_ip;
++	uint16 src_port;
++	uint16 dst_port;
++	uint8 dscp;
++	uint8 protocol;
++	uint8 reserved;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tclas_fc_1_ipv4 dot11_tclas_fc_1_ipv4_t;
++#define DOT11_TCLAS_FC_1_IPV4_LEN	18
++
++/** TCLAS frame classifier type 2 parameters for 802.1Q */
++BWL_PRE_PACKED_STRUCT struct dot11_tclas_fc_2_8021q {
++	uint8 type;
++	uint8 mask;
++	uint16 tci;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tclas_fc_2_8021q dot11_tclas_fc_2_8021q_t;
++#define DOT11_TCLAS_FC_2_8021Q_LEN	4
++
++/** TCLAS frame classifier type 3 parameters for filter offset */
++BWL_PRE_PACKED_STRUCT struct dot11_tclas_fc_3_filter {
++	uint8 type;
++	uint8 mask;
++	uint16 offset;
++	uint8 data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tclas_fc_3_filter dot11_tclas_fc_3_filter_t;
++#define DOT11_TCLAS_FC_3_FILTER_LEN	4
++
++/** TCLAS frame classifier type 4 parameters for IPV4 is the same as TCLAS type 1 */
++typedef struct dot11_tclas_fc_1_ipv4 dot11_tclas_fc_4_ipv4_t;
++#define DOT11_TCLAS_FC_4_IPV4_LEN	DOT11_TCLAS_FC_1_IPV4_LEN
++
++/** TCLAS frame classifier type 4 parameters for IPV6 */
++BWL_PRE_PACKED_STRUCT struct dot11_tclas_fc_4_ipv6 {
++	uint8 type;
++	uint8 mask;
++	uint8 version;
++	uint8 saddr[16];
++	uint8 daddr[16];
++	uint16 src_port;
++	uint16 dst_port;
++	uint8 dscp;
++	uint8 nexthdr;
++	uint8 flow_lbl[3];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tclas_fc_4_ipv6 dot11_tclas_fc_4_ipv6_t;
++#define DOT11_TCLAS_FC_4_IPV6_LEN	44
++
++/** TCLAS frame classifier type 5 parameters for 802.1D */
++BWL_PRE_PACKED_STRUCT struct dot11_tclas_fc_5_8021d {
++	uint8 type;
++	uint8 mask;
++	uint8 pcp;
++	uint8 cfi;
++	uint16 vid;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tclas_fc_5_8021d dot11_tclas_fc_5_8021d_t;
++#define DOT11_TCLAS_FC_5_8021D_LEN	6
++
++/** TCLAS frame classifier type parameters */
++BWL_PRE_PACKED_STRUCT union dot11_tclas_fc {
++	uint8 data[1];
++	dot11_tclas_fc_hdr_t hdr;
++	dot11_tclas_fc_0_eth_t t0_eth;
++	dot11_tclas_fc_1_ipv4_t	t1_ipv4;
++	dot11_tclas_fc_2_8021q_t t2_8021q;
++	dot11_tclas_fc_3_filter_t t3_filter;
++	dot11_tclas_fc_4_ipv4_t	t4_ipv4;
++	dot11_tclas_fc_4_ipv6_t	t4_ipv6;
++	dot11_tclas_fc_5_8021d_t t5_8021d;
++} BWL_POST_PACKED_STRUCT;
++typedef union dot11_tclas_fc dot11_tclas_fc_t;
++
++#define DOT11_TCLAS_FC_MIN_LEN		4	/* Classifier Type 2 has the min size */
++#define DOT11_TCLAS_FC_MAX_LEN		254
++
++/** TCLAS element */
++BWL_PRE_PACKED_STRUCT struct dot11_tclas_ie {
++	uint8 id;				/* 14, DOT11_MNG_TCLAS_ID */
++	uint8 len;
++	uint8 user_priority;
++	dot11_tclas_fc_t fc;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tclas_ie dot11_tclas_ie_t;
++#define DOT11_TCLAS_IE_LEN		3	/* Fixed length, include id and len */
++
++/** TCLAS processing element */
++BWL_PRE_PACKED_STRUCT struct dot11_tclas_proc_ie {
++	uint8 id;				/* 44, DOT11_MNG_TCLAS_PROC_ID */
++	uint8 len;
++	uint8 process;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tclas_proc_ie dot11_tclas_proc_ie_t;
++#define DOT11_TCLAS_PROC_IE_LEN		3	/* Fixed length, include id and len */
++
++#define DOT11_TCLAS_PROC_MATCHALL	0	/* All high level element need to match */
++#define DOT11_TCLAS_PROC_MATCHONE	1	/* One high level element need to match */
++#define DOT11_TCLAS_PROC_NONMATCH	2	/* Non match to any high level element */
++
++
++/* TSPEC element defined in 802.11 std section 8.4.2.32 - Not supported */
++#define DOT11_TSPEC_IE_LEN		57	/* Fixed length */
++
++/** TFS request element */
++BWL_PRE_PACKED_STRUCT struct dot11_tfs_req_ie {
++	uint8 id;				/* 91, DOT11_MNG_TFS_REQUEST_ID */
++	uint8 len;
++	uint8 tfs_id;
++	uint8 actcode;
++	uint8 data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tfs_req_ie dot11_tfs_req_ie_t;
++#define DOT11_TFS_REQ_IE_LEN		2	/* Fixed length, without id and len */
++
++/** TFS request action codes (bitfield) */
++#define DOT11_TFS_ACTCODE_DELETE	1
++#define DOT11_TFS_ACTCODE_NOTIFY	2
++
++/** TFS request subelement IDs */
++#define DOT11_TFS_REQ_TFS_SE_ID		1
++#define DOT11_TFS_REQ_VENDOR_SE_ID	221
++
++/** TFS subelement */
++BWL_PRE_PACKED_STRUCT struct dot11_tfs_se {
++	uint8 sub_id;
++	uint8 len;
++	uint8 data[1];				/* TCLAS element(s) + optional TCLAS proc */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tfs_se dot11_tfs_se_t;
++
++
++/** TFS response element */
++BWL_PRE_PACKED_STRUCT struct dot11_tfs_resp_ie {
++	uint8 id;				/* 92, DOT11_MNG_TFS_RESPONSE_ID */
++	uint8 len;
++	uint8 tfs_id;
++	uint8 data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tfs_resp_ie dot11_tfs_resp_ie_t;
++#define DOT11_TFS_RESP_IE_LEN		1	/* Fixed length, without id and len */
++
++/** TFS response subelement IDs (same subelments, but different IDs than in TFS request */
++#define DOT11_TFS_RESP_TFS_STATUS_SE_ID		1
++#define DOT11_TFS_RESP_TFS_SE_ID		2
++#define DOT11_TFS_RESP_VENDOR_SE_ID		221
++
++/** TFS status subelement */
++BWL_PRE_PACKED_STRUCT struct dot11_tfs_status_se {
++	uint8 sub_id;				/* 92, DOT11_MNG_TFS_RESPONSE_ID */
++	uint8 len;
++	uint8 resp_st;
++	uint8 data[1];				/* Potential dot11_tfs_se_t included */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tfs_status_se dot11_tfs_status_se_t;
++#define DOT11_TFS_STATUS_SE_LEN			1	/* Fixed length, without id and len */
++
++/* Following Definition should be merged to FMS_TFS macro below */
++/* TFS Response status code. Identical to FMS Element status, without N/A  */
++#define DOT11_TFS_STATUS_ACCEPT			0
++#define DOT11_TFS_STATUS_DENY_FORMAT		1
++#define DOT11_TFS_STATUS_DENY_RESOURCE		2
++#define DOT11_TFS_STATUS_DENY_POLICY		4
++#define DOT11_TFS_STATUS_DENY_UNSPECIFIED	5
++#define DOT11_TFS_STATUS_ALTPREF_POLICY		7
++#define DOT11_TFS_STATUS_ALTPREF_TCLAS_UNSUPP	14
++
++/* FMS Element Status and TFS Response Status Definition */
++#define DOT11_FMS_TFS_STATUS_ACCEPT		0
++#define DOT11_FMS_TFS_STATUS_DENY_FORMAT	1
++#define DOT11_FMS_TFS_STATUS_DENY_RESOURCE	2
++#define DOT11_FMS_TFS_STATUS_DENY_MULTIPLE_DI	3
++#define DOT11_FMS_TFS_STATUS_DENY_POLICY	4
++#define DOT11_FMS_TFS_STATUS_DENY_UNSPECIFIED	5
++#define DOT11_FMS_TFS_STATUS_ALT_DIFF_DI	6
++#define DOT11_FMS_TFS_STATUS_ALT_POLICY		7
++#define DOT11_FMS_TFS_STATUS_ALT_CHANGE_DI	8
++#define DOT11_FMS_TFS_STATUS_ALT_MCRATE		9
++#define DOT11_FMS_TFS_STATUS_TERM_POLICY	10
++#define DOT11_FMS_TFS_STATUS_TERM_RESOURCE	11
++#define DOT11_FMS_TFS_STATUS_TERM_HIGHER_PRIO	12
++#define DOT11_FMS_TFS_STATUS_ALT_CHANGE_MDI	13
++#define DOT11_FMS_TFS_STATUS_ALT_TCLAS_UNSUPP	14
++
++/** TFS Management Request frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_tfs_req {
++	uint8 category;				/* category of action frame (10) */
++	uint8 action;				/* WNM action: TFS request (13) */
++	uint8 token;				/* dialog token */
++	uint8 data[1];				/* Elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tfs_req dot11_tfs_req_t;
++#define DOT11_TFS_REQ_LEN		3	/* Fixed length */
++
++/** TFS Management Response frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_tfs_resp {
++	uint8 category;				/* category of action frame (10) */
++	uint8 action;				/* WNM action: TFS request (14) */
++	uint8 token;				/* dialog token */
++	uint8 data[1];				/* Elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tfs_resp dot11_tfs_resp_t;
++#define DOT11_TFS_RESP_LEN		3	/* Fixed length */
++
++/** TFS Management Notify frame request header */
++BWL_PRE_PACKED_STRUCT struct dot11_tfs_notify_req {
++	uint8 category;				/* category of action frame (10) */
++	uint8 action;				/* WNM action: TFS notify request (15) */
++	uint8 tfs_id_cnt;			/* TFS IDs count */
++	uint8 tfs_id[1];			/* Array of TFS IDs */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tfs_notify_req dot11_tfs_notify_req_t;
++#define DOT11_TFS_NOTIFY_REQ_LEN	3	/* Fixed length */
++
++/** TFS Management Notify frame response header */
++BWL_PRE_PACKED_STRUCT struct dot11_tfs_notify_resp {
++	uint8 category;				/* category of action frame (10) */
++	uint8 action;				/* WNM action: TFS notify response (28) */
++	uint8 tfs_id_cnt;			/* TFS IDs count */
++	uint8 tfs_id[1];			/* Array of TFS IDs */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tfs_notify_resp dot11_tfs_notify_resp_t;
++#define DOT11_TFS_NOTIFY_RESP_LEN	3	/* Fixed length */
++
++
++/** WNM-Sleep Management Request frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_wnm_sleep_req {
++	uint8 category;				/* category of action frame (10) */
++	uint8 action;				/* WNM action: wnm-sleep request (16) */
++	uint8 token;				/* dialog token */
++	uint8 data[1];				/* Elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_wnm_sleep_req dot11_wnm_sleep_req_t;
++#define DOT11_WNM_SLEEP_REQ_LEN		3	/* Fixed length */
++
++/** WNM-Sleep Management Response frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_wnm_sleep_resp {
++	uint8 category;				/* category of action frame (10) */
++	uint8 action;				/* WNM action: wnm-sleep request (17) */
++	uint8 token;				/* dialog token */
++	uint16 key_len;				/* key data length */
++	uint8 data[1];				/* Elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_wnm_sleep_resp dot11_wnm_sleep_resp_t;
++#define DOT11_WNM_SLEEP_RESP_LEN	5	/* Fixed length */
++
++#define DOT11_WNM_SLEEP_SUBELEM_ID_GTK	0
++#define DOT11_WNM_SLEEP_SUBELEM_ID_IGTK	1
++
++BWL_PRE_PACKED_STRUCT struct dot11_wnm_sleep_subelem_gtk {
++	uint8 sub_id;
++	uint8 len;
++	uint16 key_info;
++	uint8 key_length;
++	uint8 rsc[8];
++	uint8 key[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_wnm_sleep_subelem_gtk dot11_wnm_sleep_subelem_gtk_t;
++#define DOT11_WNM_SLEEP_SUBELEM_GTK_FIXED_LEN	11	/* without sub_id, len, and key */
++#define DOT11_WNM_SLEEP_SUBELEM_GTK_MAX_LEN	43	/* without sub_id and len */
++
++BWL_PRE_PACKED_STRUCT struct dot11_wnm_sleep_subelem_igtk {
++	uint8 sub_id;
++	uint8 len;
++	uint16 key_id;
++	uint8 pn[6];
++	uint8 key[16];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_wnm_sleep_subelem_igtk dot11_wnm_sleep_subelem_igtk_t;
++#define DOT11_WNM_SLEEP_SUBELEM_IGTK_LEN 24	/* Fixed length */
++
++BWL_PRE_PACKED_STRUCT struct dot11_wnm_sleep_ie {
++	uint8 id;				/* 93, DOT11_MNG_WNM_SLEEP_MODE_ID */
++	uint8 len;
++	uint8 act_type;
++	uint8 resp_status;
++	uint16 interval;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_wnm_sleep_ie dot11_wnm_sleep_ie_t;
++#define DOT11_WNM_SLEEP_IE_LEN		4	/* Fixed length */
++
++#define DOT11_WNM_SLEEP_ACT_TYPE_ENTER	0
++#define DOT11_WNM_SLEEP_ACT_TYPE_EXIT	1
++
++#define DOT11_WNM_SLEEP_RESP_ACCEPT	0
++#define DOT11_WNM_SLEEP_RESP_UPDATE	1
++#define DOT11_WNM_SLEEP_RESP_DENY	2
++#define DOT11_WNM_SLEEP_RESP_DENY_TEMP	3
++#define DOT11_WNM_SLEEP_RESP_DENY_KEY	4
++#define DOT11_WNM_SLEEP_RESP_DENY_INUSE	5
++#define DOT11_WNM_SLEEP_RESP_LAST	6
++
++/** DMS Management Request frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_dms_req {
++	uint8 category;				/* category of action frame (10) */
++	uint8 action;				/* WNM action: dms request (23) */
++	uint8 token;				/* dialog token */
++	uint8 data[1];				/* Elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_dms_req dot11_dms_req_t;
++#define DOT11_DMS_REQ_LEN		3	/* Fixed length */
++
++/** DMS Management Response frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_dms_resp {
++	uint8 category;				/* category of action frame (10) */
++	uint8 action;				/* WNM action: dms request (24) */
++	uint8 token;				/* dialog token */
++	uint8 data[1];				/* Elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_dms_resp dot11_dms_resp_t;
++#define DOT11_DMS_RESP_LEN		3	/* Fixed length */
++
++/** DMS request element */
++BWL_PRE_PACKED_STRUCT struct dot11_dms_req_ie {
++	uint8 id;				/* 99, DOT11_MNG_DMS_REQUEST_ID */
++	uint8 len;
++	uint8 data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_dms_req_ie dot11_dms_req_ie_t;
++#define DOT11_DMS_REQ_IE_LEN		2	/* Fixed length */
++
++/** DMS response element */
++BWL_PRE_PACKED_STRUCT struct dot11_dms_resp_ie {
++	uint8 id;				/* 100, DOT11_MNG_DMS_RESPONSE_ID */
++	uint8 len;
++	uint8 data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_dms_resp_ie dot11_dms_resp_ie_t;
++#define DOT11_DMS_RESP_IE_LEN		2	/* Fixed length */
++
++/** DMS request descriptor */
++BWL_PRE_PACKED_STRUCT struct dot11_dms_req_desc {
++	uint8 dms_id;
++	uint8 len;
++	uint8 type;
++	uint8 data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_dms_req_desc dot11_dms_req_desc_t;
++#define DOT11_DMS_REQ_DESC_LEN		3	/* Fixed length */
++
++#define DOT11_DMS_REQ_TYPE_ADD		0
++#define DOT11_DMS_REQ_TYPE_REMOVE	1
++#define DOT11_DMS_REQ_TYPE_CHANGE	2
++
++/** DMS response status */
++BWL_PRE_PACKED_STRUCT struct dot11_dms_resp_st {
++	uint8 dms_id;
++	uint8 len;
++	uint8 type;
++	uint16 lsc;
++	uint8 data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_dms_resp_st dot11_dms_resp_st_t;
++#define DOT11_DMS_RESP_STATUS_LEN	5	/* Fixed length */
++
++#define DOT11_DMS_RESP_TYPE_ACCEPT	0
++#define DOT11_DMS_RESP_TYPE_DENY	1
++#define DOT11_DMS_RESP_TYPE_TERM	2
++
++#define DOT11_DMS_RESP_LSC_UNSUPPORTED	0xFFFF
++
++/** WNM-Notification Request frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_wnm_notif_req {
++	uint8 category;				/* category of action frame (10) */
++	uint8 action;				/* WNM action: Notification request (26) */
++	uint8 token;				/* dialog token */
++	uint8 type;				   /* type */
++	uint8 data[1];				/* Sub-elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_wnm_notif_req dot11_wnm_notif_req_t;
++#define DOT11_WNM_NOTIF_REQ_LEN		4	/* Fixed length */
++
++/** FMS Management Request frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_fms_req {
++	uint8 category;				/* category of action frame (10) */
++	uint8 action;				/* WNM action: fms request (9) */
++	uint8 token;				/* dialog token */
++	uint8 data[1];				/* Elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_fms_req dot11_fms_req_t;
++#define DOT11_FMS_REQ_LEN		3	/* Fixed length */
++
++/** FMS Management Response frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_fms_resp {
++	uint8 category;				/* category of action frame (10) */
++	uint8 action;				/* WNM action: fms request (10) */
++	uint8 token;				/* dialog token */
++	uint8 data[1];				/* Elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_fms_resp dot11_fms_resp_t;
++#define DOT11_FMS_RESP_LEN		3	/* Fixed length */
++
++/** FMS Descriptor element */
++BWL_PRE_PACKED_STRUCT struct dot11_fms_desc {
++	uint8 id;
++	uint8 len;
++	uint8 num_fms_cnt;
++	uint8 data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_fms_desc dot11_fms_desc_t;
++#define DOT11_FMS_DESC_LEN		1	/* Fixed length */
++
++#define DOT11_FMS_CNTR_MAX		0x8
++#define DOT11_FMS_CNTR_ID_MASK		0x7
++#define DOT11_FMS_CNTR_ID_SHIFT		0x0
++#define DOT11_FMS_CNTR_COUNT_MASK	0xf1
++#define DOT11_FMS_CNTR_SHIFT		0x3
++
++/** FMS request element */
++BWL_PRE_PACKED_STRUCT struct dot11_fms_req_ie {
++	uint8 id;
++	uint8 len;
++	uint8 fms_token;			/* token used to identify fms stream set */
++	uint8 data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_fms_req_ie dot11_fms_req_ie_t;
++#define DOT11_FMS_REQ_IE_FIX_LEN		1	/* Fixed length */
++
++BWL_PRE_PACKED_STRUCT struct dot11_rate_id_field {
++	uint8 mask;
++	uint8 mcs_idx;
++	uint16 rate;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rate_id_field dot11_rate_id_field_t;
++#define DOT11_RATE_ID_FIELD_MCS_SEL_MASK	0x7
++#define DOT11_RATE_ID_FIELD_MCS_SEL_OFFSET	0
++#define DOT11_RATE_ID_FIELD_RATETYPE_MASK	0x18
++#define DOT11_RATE_ID_FIELD_RATETYPE_OFFSET	3
++#define DOT11_RATE_ID_FIELD_LEN		sizeof(dot11_rate_id_field_t)
++
++/** FMS request subelements */
++BWL_PRE_PACKED_STRUCT struct dot11_fms_se {
++	uint8 sub_id;
++	uint8 len;
++	uint8 interval;
++	uint8 max_interval;
++	dot11_rate_id_field_t rate;
++	uint8 data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_fms_se dot11_fms_se_t;
++#define DOT11_FMS_REQ_SE_LEN		6	/* Fixed length */
++
++#define DOT11_FMS_REQ_SE_ID_FMS		1	/* FMS subelement */
++#define DOT11_FMS_REQ_SE_ID_VS		221	/* Vendor Specific subelement */
++
++/** FMS response element */
++BWL_PRE_PACKED_STRUCT struct dot11_fms_resp_ie {
++	uint8 id;
++	uint8 len;
++	uint8 fms_token;
++	uint8 data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_fms_resp_ie dot11_fms_resp_ie_t;
++#define DOT11_FMS_RESP_IE_FIX_LEN		1	/* Fixed length */
++
++/* FMS status subelements */
++#define DOT11_FMS_STATUS_SE_ID_FMS	1	/* FMS Status */
++#define DOT11_FMS_STATUS_SE_ID_TCLAS	2	/* TCLAS Status */
++#define DOT11_FMS_STATUS_SE_ID_VS	221	/* Vendor Specific subelement */
++
++/** FMS status subelement */
++BWL_PRE_PACKED_STRUCT struct dot11_fms_status_se {
++	uint8 sub_id;
++	uint8 len;
++	uint8 status;
++	uint8 interval;
++	uint8 max_interval;
++	uint8 fmsid;
++	uint8 counter;
++	dot11_rate_id_field_t rate;
++	uint8 mcast_addr[ETHER_ADDR_LEN];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_fms_status_se dot11_fms_status_se_t;
++#define DOT11_FMS_STATUS_SE_LEN		15	/* Fixed length */
++
++/** TCLAS status subelement */
++BWL_PRE_PACKED_STRUCT struct dot11_tclas_status_se {
++	uint8 sub_id;
++	uint8 len;
++	uint8 fmsid;
++	uint8 data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_tclas_status_se dot11_tclas_status_se_t;
++#define DOT11_TCLAS_STATUS_SE_LEN		1	/* Fixed length */
++
++BWL_PRE_PACKED_STRUCT struct dot11_addba_req {
++	uint8 category;				/* category of action frame (3) */
++	uint8 action;				/* action: addba req */
++	uint8 token;				/* identifier */
++	uint16 addba_param_set;		/* parameter set */
++	uint16 timeout;				/* timeout in seconds */
++	uint16 start_seqnum;		/* starting sequence number */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_addba_req dot11_addba_req_t;
++#define DOT11_ADDBA_REQ_LEN		9	/* length of addba req frame */
++
++BWL_PRE_PACKED_STRUCT struct dot11_addba_resp {
++	uint8 category;				/* category of action frame (3) */
++	uint8 action;				/* action: addba resp */
++	uint8 token;				/* identifier */
++	uint16 status;				/* status of add request */
++	uint16 addba_param_set;			/* negotiated parameter set */
++	uint16 timeout;				/* negotiated timeout in seconds */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_addba_resp dot11_addba_resp_t;
++#define DOT11_ADDBA_RESP_LEN		9	/* length of addba resp frame */
++
++/* DELBA action parameters */
++#define DOT11_DELBA_PARAM_INIT_MASK	0x0800	/* initiator mask */
++#define DOT11_DELBA_PARAM_INIT_SHIFT	11	/* initiator shift */
++#define DOT11_DELBA_PARAM_TID_MASK	0xf000	/* tid mask */
++#define DOT11_DELBA_PARAM_TID_SHIFT	12	/* tid shift */
++
++BWL_PRE_PACKED_STRUCT struct dot11_delba {
++	uint8 category;				/* category of action frame (3) */
++	uint8 action;				/* action: addba req */
++	uint16 delba_param_set;			/* paarmeter set */
++	uint16 reason;				/* reason for dellba */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_delba dot11_delba_t;
++#define DOT11_DELBA_LEN			6	/* length of delba frame */
++
++/* SA Query action field value */
++#define SA_QUERY_REQUEST		0
++#define SA_QUERY_RESPONSE		1
++
++/* ************* 802.11r related definitions. ************* */
++
++/** Over-the-DS Fast Transition Request frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_ft_req {
++	uint8 category;			/* category of action frame (6) */
++	uint8 action;			/* action: ft req */
++	uint8 sta_addr[ETHER_ADDR_LEN];
++	uint8 tgt_ap_addr[ETHER_ADDR_LEN];
++	uint8 data[1];			/* Elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_ft_req dot11_ft_req_t;
++#define DOT11_FT_REQ_FIXED_LEN 14
++
++/** Over-the-DS Fast Transition Response frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_ft_res {
++	uint8 category;			/* category of action frame (6) */
++	uint8 action;			/* action: ft resp */
++	uint8 sta_addr[ETHER_ADDR_LEN];
++	uint8 tgt_ap_addr[ETHER_ADDR_LEN];
++	uint16 status;			/* status code */
++	uint8 data[1];			/* Elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_ft_res dot11_ft_res_t;
++#define DOT11_FT_RES_FIXED_LEN 16
++
++/** RDE RIC Data Element. */
++BWL_PRE_PACKED_STRUCT struct dot11_rde_ie {
++	uint8 id;			/* 11r, DOT11_MNG_RDE_ID */
++	uint8 length;
++	uint8 rde_id;			/* RDE identifier. */
++	uint8 rd_count;			/* Resource Descriptor Count. */
++	uint16 status;			/* Status Code. */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rde_ie dot11_rde_ie_t;
++
++/* 11r - Size of the RDE (RIC Data Element) IE, including TLV header. */
++#define DOT11_MNG_RDE_IE_LEN sizeof(dot11_rde_ie_t)
++
++
++/* ************* 802.11k related definitions. ************* */
++
++/* Radio measurements enabled capability ie */
++#define DOT11_RRM_CAP_LEN		5	/* length of rrm cap bitmap */
++#define RCPI_IE_LEN 1
++#define RSNI_IE_LEN 1
++BWL_PRE_PACKED_STRUCT struct dot11_rrm_cap_ie {
++	uint8 cap[DOT11_RRM_CAP_LEN];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rrm_cap_ie dot11_rrm_cap_ie_t;
++
++/* Bitmap definitions for cap ie */
++#define DOT11_RRM_CAP_LINK		0
++#define DOT11_RRM_CAP_NEIGHBOR_REPORT	1
++#define DOT11_RRM_CAP_PARALLEL		2
++#define DOT11_RRM_CAP_REPEATED		3
++#define DOT11_RRM_CAP_BCN_PASSIVE	4
++#define DOT11_RRM_CAP_BCN_ACTIVE	5
++#define DOT11_RRM_CAP_BCN_TABLE		6
++#define DOT11_RRM_CAP_BCN_REP_COND	7
++#define DOT11_RRM_CAP_FM		8
++#define DOT11_RRM_CAP_CLM		9
++#define DOT11_RRM_CAP_NHM		10
++#define DOT11_RRM_CAP_SM		11
++#define DOT11_RRM_CAP_LCIM		12
++#define DOT11_RRM_CAP_LCIA		13
++#define DOT11_RRM_CAP_TSCM		14
++#define DOT11_RRM_CAP_TTSCM		15
++#define DOT11_RRM_CAP_AP_CHANREP	16
++#define DOT11_RRM_CAP_RMMIB		17
++/* bit18-bit23, not used for RRM_IOVAR */
++#define DOT11_RRM_CAP_MPC0		24
++#define DOT11_RRM_CAP_MPC1		25
++#define DOT11_RRM_CAP_MPC2		26
++#define DOT11_RRM_CAP_MPTI		27
++#define DOT11_RRM_CAP_NBRTSFO		28
++#define DOT11_RRM_CAP_RCPI		29
++#define DOT11_RRM_CAP_RSNI		30
++#define DOT11_RRM_CAP_BSSAAD		31
++#define DOT11_RRM_CAP_BSSAAC		32
++#define DOT11_RRM_CAP_AI		33
++#define DOT11_RRM_CAP_FTM_RANGE		34
++#define DOT11_RRM_CAP_CIVIC_LOC		35
++#define DOT11_RRM_CAP_IDENT_LOC		36
++#define DOT11_RRM_CAP_LAST		36
++
++#ifdef WL11K_ALL_MEAS
++#define DOT11_RRM_CAP_LINK_ENAB			(1 << DOT11_RRM_CAP_LINK)
++#define DOT11_RRM_CAP_FM_ENAB			(1 << (DOT11_RRM_CAP_FM - 8))
++#define DOT11_RRM_CAP_CLM_ENAB			(1 << (DOT11_RRM_CAP_CLM - 8))
++#define DOT11_RRM_CAP_NHM_ENAB			(1 << (DOT11_RRM_CAP_NHM - 8))
++#define DOT11_RRM_CAP_SM_ENAB			(1 << (DOT11_RRM_CAP_SM - 8))
++#define DOT11_RRM_CAP_LCIM_ENAB			(1 << (DOT11_RRM_CAP_LCIM - 8))
++#define DOT11_RRM_CAP_TSCM_ENAB			(1 << (DOT11_RRM_CAP_TSCM - 8))
++#ifdef WL11K_AP
++#define DOT11_RRM_CAP_MPC0_ENAB			(1 << (DOT11_RRM_CAP_MPC0 - 24))
++#define DOT11_RRM_CAP_MPC1_ENAB			(1 << (DOT11_RRM_CAP_MPC1 - 24))
++#define DOT11_RRM_CAP_MPC2_ENAB			(1 << (DOT11_RRM_CAP_MPC2 - 24))
++#define DOT11_RRM_CAP_MPTI_ENAB			(1 << (DOT11_RRM_CAP_MPTI - 24))
++#else
++#define DOT11_RRM_CAP_MPC0_ENAB			0
++#define DOT11_RRM_CAP_MPC1_ENAB			0
++#define DOT11_RRM_CAP_MPC2_ENAB			0
++#define DOT11_RRM_CAP_MPTI_ENAB			0
++#endif /* WL11K_AP */
++#define DOT11_RRM_CAP_CIVIC_LOC_ENAB		(1 << (DOT11_RRM_CAP_CIVIC_LOC - 32))
++#define DOT11_RRM_CAP_IDENT_LOC_ENAB		(1 << (DOT11_RRM_CAP_IDENT_LOC - 32))
++#else
++#define DOT11_RRM_CAP_LINK_ENAB			0
++#define DOT11_RRM_CAP_FM_ENAB			0
++#define DOT11_RRM_CAP_CLM_ENAB			0
++#define DOT11_RRM_CAP_NHM_ENAB			0
++#define DOT11_RRM_CAP_SM_ENAB			0
++#define DOT11_RRM_CAP_LCIM_ENAB			0
++#define DOT11_RRM_CAP_TSCM_ENAB			0
++#define DOT11_RRM_CAP_MPC0_ENAB			0
++#define DOT11_RRM_CAP_MPC1_ENAB			0
++#define DOT11_RRM_CAP_MPC2_ENAB			0
++#define DOT11_RRM_CAP_MPTI_ENAB			0
++#define DOT11_RRM_CAP_CIVIC_LOC_ENAB		0
++#define DOT11_RRM_CAP_IDENT_LOC_ENAB		0
++#endif /* WL11K_ALL_MEAS */
++#ifdef WL11K_NBR_MEAS
++#define DOT11_RRM_CAP_NEIGHBOR_REPORT_ENAB	(1 << DOT11_RRM_CAP_NEIGHBOR_REPORT)
++#else
++#define DOT11_RRM_CAP_NEIGHBOR_REPORT_ENAB	0
++#endif /* WL11K_NBR_MEAS */
++#ifdef WL11K_BCN_MEAS
++#define DOT11_RRM_CAP_BCN_PASSIVE_ENAB		(1 << DOT11_RRM_CAP_BCN_PASSIVE)
++#define DOT11_RRM_CAP_BCN_ACTIVE_ENAB		(1 << DOT11_RRM_CAP_BCN_ACTIVE)
++#else
++#define DOT11_RRM_CAP_BCN_PASSIVE_ENAB		0
++#define DOT11_RRM_CAP_BCN_ACTIVE_ENAB		0
++#endif /* WL11K_BCN_MEAS */
++#define DOT11_RRM_CAP_MPA_MASK		0x7
++/* Operating Class (formerly "Regulatory Class") definitions */
++#define DOT11_OP_CLASS_NONE			255
++
++BWL_PRE_PACKED_STRUCT struct do11_ap_chrep {
++	uint8 id;
++	uint8 len;
++	uint8 reg;
++	uint8 chanlist[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct do11_ap_chrep dot11_ap_chrep_t;
++
++/* Radio Measurements action ids */
++#define DOT11_RM_ACTION_RM_REQ		0	/* Radio measurement request */
++#define DOT11_RM_ACTION_RM_REP		1	/* Radio measurement report */
++#define DOT11_RM_ACTION_LM_REQ		2	/* Link measurement request */
++#define DOT11_RM_ACTION_LM_REP		3	/* Link measurement report */
++#define DOT11_RM_ACTION_NR_REQ		4	/* Neighbor report request */
++#define DOT11_RM_ACTION_NR_REP		5	/* Neighbor report response */
++#define DOT11_PUB_ACTION_MP		7	/* Measurement Pilot public action id */
++
++/** Generic radio measurement action frame header */
++BWL_PRE_PACKED_STRUCT struct dot11_rm_action {
++	uint8 category;				/* category of action frame (5) */
++	uint8 action;				/* radio measurement action */
++	uint8 token;				/* dialog token */
++	uint8 data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rm_action dot11_rm_action_t;
++#define DOT11_RM_ACTION_LEN 3
++
++BWL_PRE_PACKED_STRUCT struct dot11_rmreq {
++	uint8 category;				/* category of action frame (5) */
++	uint8 action;				/* radio measurement action */
++	uint8 token;				/* dialog token */
++	uint16 reps;				/* no. of repetitions */
++	uint8 data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmreq dot11_rmreq_t;
++#define DOT11_RMREQ_LEN	5
++
++BWL_PRE_PACKED_STRUCT struct dot11_rm_ie {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rm_ie dot11_rm_ie_t;
++#define DOT11_RM_IE_LEN	5
++
++/* Definitions for "mode" bits in rm req */
++#define DOT11_RMREQ_MODE_PARALLEL	1
++#define DOT11_RMREQ_MODE_ENABLE		2
++#define DOT11_RMREQ_MODE_REQUEST	4
++#define DOT11_RMREQ_MODE_REPORT		8
++#define DOT11_RMREQ_MODE_DURMAND	0x10	/* Duration Mandatory */
++
++/* Definitions for "mode" bits in rm rep */
++#define DOT11_RMREP_MODE_LATE		1
++#define DOT11_RMREP_MODE_INCAPABLE	2
++#define DOT11_RMREP_MODE_REFUSED	4
++
++BWL_PRE_PACKED_STRUCT struct dot11_rmreq_bcn {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++	uint8 reg;
++	uint8 channel;
++	uint16 interval;
++	uint16 duration;
++	uint8 bcn_mode;
++	struct ether_addr	bssid;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmreq_bcn dot11_rmreq_bcn_t;
++#define DOT11_RMREQ_BCN_LEN	18
++
++BWL_PRE_PACKED_STRUCT struct dot11_rmrep_bcn {
++	uint8 reg;
++	uint8 channel;
++	uint32 starttime[2];
++	uint16 duration;
++	uint8 frame_info;
++	uint8 rcpi;
++	uint8 rsni;
++	struct ether_addr	bssid;
++	uint8 antenna_id;
++	uint32 parent_tsf;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmrep_bcn dot11_rmrep_bcn_t;
++#define DOT11_RMREP_BCN_LEN	26
++
++/* Beacon request measurement mode */
++#define DOT11_RMREQ_BCN_PASSIVE	0
++#define DOT11_RMREQ_BCN_ACTIVE	1
++#define DOT11_RMREQ_BCN_TABLE	2
++
++/* Sub-element IDs for Beacon Request */
++#define DOT11_RMREQ_BCN_SSID_ID 0
++#define DOT11_RMREQ_BCN_REPINFO_ID  1
++#define DOT11_RMREQ_BCN_REPDET_ID   2
++#define DOT11_RMREQ_BCN_REQUEST_ID  10
++#define DOT11_RMREQ_BCN_APCHREP_ID  DOT11_MNG_AP_CHREP_ID
++
++/* Reporting Detail element definition */
++#define DOT11_RMREQ_BCN_REPDET_FIXED	0	/* Fixed length fields only */
++#define DOT11_RMREQ_BCN_REPDET_REQUEST	1	/* + requested information elems */
++#define DOT11_RMREQ_BCN_REPDET_ALL	2	/* All fields */
++
++/* Reporting Information (reporting condition) element definition */
++#define DOT11_RMREQ_BCN_REPINFO_LEN	2	/* Beacon Reporting Information length */
++#define DOT11_RMREQ_BCN_REPCOND_DEFAULT	0	/* Report to be issued after each measurement */
++
++/* Sub-element IDs for Beacon Report */
++#define DOT11_RMREP_BCN_FRM_BODY	1
++#define DOT11_RMREP_BCN_FRM_BODY_LEN_MAX	224 /* 802.11k-2008 7.3.2.22.6 */
++
++/* Sub-element IDs for Frame Report */
++#define DOT11_RMREP_FRAME_COUNT_REPORT 1
++
++/* Channel load request */
++BWL_PRE_PACKED_STRUCT struct dot11_rmreq_chanload {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++	uint8 reg;
++	uint8 channel;
++	uint16 interval;
++	uint16 duration;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmreq_chanload dot11_rmreq_chanload_t;
++#define DOT11_RMREQ_CHANLOAD_LEN	11
++
++/** Channel load report */
++BWL_PRE_PACKED_STRUCT struct dot11_rmrep_chanload {
++	uint8 reg;
++	uint8 channel;
++	uint32 starttime[2];
++	uint16 duration;
++	uint8 channel_load;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmrep_chanload dot11_rmrep_chanload_t;
++#define DOT11_RMREP_CHANLOAD_LEN	13
++
++/** Noise histogram request */
++BWL_PRE_PACKED_STRUCT struct dot11_rmreq_noise {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++	uint8 reg;
++	uint8 channel;
++	uint16 interval;
++	uint16 duration;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmreq_noise dot11_rmreq_noise_t;
++#define DOT11_RMREQ_NOISE_LEN 11
++
++/** Noise histogram report */
++BWL_PRE_PACKED_STRUCT struct dot11_rmrep_noise {
++	uint8 reg;
++	uint8 channel;
++	uint32 starttime[2];
++	uint16 duration;
++	uint8 antid;
++	uint8 anpi;
++	uint8 ipi0_dens;
++	uint8 ipi1_dens;
++	uint8 ipi2_dens;
++	uint8 ipi3_dens;
++	uint8 ipi4_dens;
++	uint8 ipi5_dens;
++	uint8 ipi6_dens;
++	uint8 ipi7_dens;
++	uint8 ipi8_dens;
++	uint8 ipi9_dens;
++	uint8 ipi10_dens;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmrep_noise dot11_rmrep_noise_t;
++#define DOT11_RMREP_NOISE_LEN 25
++
++/** Frame request */
++BWL_PRE_PACKED_STRUCT struct dot11_rmreq_frame {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++	uint8 reg;
++	uint8 channel;
++	uint16 interval;
++	uint16 duration;
++	uint8 req_type;
++	struct ether_addr	ta;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmreq_frame dot11_rmreq_frame_t;
++#define DOT11_RMREQ_FRAME_LEN 18
++
++/** Frame report */
++BWL_PRE_PACKED_STRUCT struct dot11_rmrep_frame {
++	uint8 reg;
++	uint8 channel;
++	uint32 starttime[2];
++	uint16 duration;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmrep_frame dot11_rmrep_frame_t;
++#define DOT11_RMREP_FRAME_LEN 12
++
++/** Frame report entry */
++BWL_PRE_PACKED_STRUCT struct dot11_rmrep_frmentry {
++	struct ether_addr	ta;
++	struct ether_addr	bssid;
++	uint8 phy_type;
++	uint8 avg_rcpi;
++	uint8 last_rsni;
++	uint8 last_rcpi;
++	uint8 ant_id;
++	uint16 frame_cnt;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmrep_frmentry dot11_rmrep_frmentry_t;
++#define DOT11_RMREP_FRMENTRY_LEN 19
++
++/** STA statistics request */
++BWL_PRE_PACKED_STRUCT struct dot11_rmreq_stat {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++	struct ether_addr	peer;
++	uint16 interval;
++	uint16 duration;
++	uint8 group_id;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmreq_stat dot11_rmreq_stat_t;
++#define DOT11_RMREQ_STAT_LEN 16
++
++/** STA statistics report */
++BWL_PRE_PACKED_STRUCT struct dot11_rmrep_stat {
++	uint16 duration;
++	uint8 group_id;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmrep_stat dot11_rmrep_stat_t;
++
++/* Statistics Group Report: Group IDs */
++enum {
++	DOT11_RRM_STATS_GRP_ID_0 = 0,
++	DOT11_RRM_STATS_GRP_ID_1,
++	DOT11_RRM_STATS_GRP_ID_2,
++	DOT11_RRM_STATS_GRP_ID_3,
++	DOT11_RRM_STATS_GRP_ID_4,
++	DOT11_RRM_STATS_GRP_ID_5,
++	DOT11_RRM_STATS_GRP_ID_6,
++	DOT11_RRM_STATS_GRP_ID_7,
++	DOT11_RRM_STATS_GRP_ID_8,
++	DOT11_RRM_STATS_GRP_ID_9,
++	DOT11_RRM_STATS_GRP_ID_10,
++	DOT11_RRM_STATS_GRP_ID_11,
++	DOT11_RRM_STATS_GRP_ID_12,
++	DOT11_RRM_STATS_GRP_ID_13,
++	DOT11_RRM_STATS_GRP_ID_14,
++	DOT11_RRM_STATS_GRP_ID_15,
++	DOT11_RRM_STATS_GRP_ID_16
++};
++
++/* Statistics Group Report: Group Data length  */
++#define DOT11_RRM_STATS_RPT_LEN_GRP_ID_0	28
++typedef struct rrm_stat_group_0 {
++	uint32	txfrag;
++	uint32	txmulti;
++	uint32	txfail;
++	uint32	rxframe;
++	uint32	rxmulti;
++	uint32	rxbadfcs;
++	uint32	txframe;
++} rrm_stat_group_0_t;
++
++#define DOT11_RRM_STATS_RPT_LEN_GRP_ID_1	24
++typedef struct rrm_stat_group_1 {
++	uint32	txretry;
++	uint32	txretries;
++	uint32	rxdup;
++	uint32	txrts;
++	uint32	rtsfail;
++	uint32	ackfail;
++} rrm_stat_group_1_t;
++
++/* group 2-9 use same qos data structure (tid 0-7), total 52 bytes */
++#define DOT11_RRM_STATS_RPT_LEN_GRP_ID_2_9	52
++typedef struct rrm_stat_group_qos {
++	uint32	txfrag;
++	uint32	txfail;
++	uint32	txretry;
++	uint32	txretries;
++	uint32	rxdup;
++	uint32	txrts;
++	uint32	rtsfail;
++	uint32	ackfail;
++	uint32	rxfrag;
++	uint32	txframe;
++	uint32	txdrop;
++	uint32	rxmpdu;
++	uint32	rxretries;
++} rrm_stat_group_qos_t;
++
++/* dot11BSSAverageAccessDelay Group (only available at an AP): 8 byte */
++#define DOT11_RRM_STATS_RPT_LEN_GRP_ID_10	8
++typedef BWL_PRE_PACKED_STRUCT struct rrm_stat_group_10 {
++	uint8	apavgdelay;
++	uint8	avgdelaybe;
++	uint8	avgdelaybg;
++	uint8	avgdelayvi;
++	uint8	avgdelayvo;
++	uint16	stacount;
++	uint8	chanutil;
++} BWL_POST_PACKED_STRUCT rrm_stat_group_10_t;
++
++/* AMSDU, 40 bytes */
++#define DOT11_RRM_STATS_RPT_LEN_GRP_ID_11	40
++typedef struct rrm_stat_group_11 {
++	uint32	txamsdu;
++	uint32	amsdufail;
++	uint32	amsduretry;
++	uint32	amsduretries;
++	uint32	txamsdubyte_h;
++	uint32	txamsdubyte_l;
++	uint32	amsduackfail;
++	uint32	rxamsdu;
++	uint32	rxamsdubyte_h;
++	uint32	rxamsdubyte_l;
++} rrm_stat_group_11_t;
++
++/* AMPDU, 36 bytes */
++#define DOT11_RRM_STATS_RPT_LEN_GRP_ID_12	36
++typedef struct rrm_stat_group_12 {
++	uint32	txampdu;
++	uint32	txmpdu;
++	uint32	txampdubyte_h;
++	uint32	txampdubyte_l;
++	uint32	rxampdu;
++	uint32	rxmpdu;
++	uint32	rxampdubyte_h;
++	uint32	rxampdubyte_l;
++	uint32	ampducrcfail;
++} rrm_stat_group_12_t;
++
++/* BACK etc, 36 bytes */
++#define DOT11_RRM_STATS_RPT_LEN_GRP_ID_13	36
++typedef struct rrm_stat_group_13 {
++	uint32	rximpbarfail;
++	uint32	rxexpbarfail;
++	uint32	chanwidthsw;
++	uint32	txframe20mhz;
++	uint32	txframe40mhz;
++	uint32	rxframe20mhz;
++	uint32	rxframe40mhz;
++	uint32	psmpgrantdur;
++	uint32	psmpuseddur;
++} rrm_stat_group_13_t;
++
++/* RD Dual CTS etc, 36 bytes */
++#define DOT11_RRM_STATS_RPT_LEN_GRP_ID_14	36
++typedef struct rrm_stat_group_14 {
++	uint32	grantrdgused;
++	uint32	grantrdgunused;
++	uint32	txframeingrantrdg;
++	uint32	txbyteingrantrdg_h;
++	uint32	txbyteingrantrdg_l;
++	uint32	dualcts;
++	uint32	dualctsfail;
++	uint32	rtslsi;
++	uint32	rtslsifail;
++} rrm_stat_group_14_t;
++
++/* bf and STBC etc, 20 bytes */
++#define DOT11_RRM_STATS_RPT_LEN_GRP_ID_15	20
++typedef struct rrm_stat_group_15 {
++	uint32	bfframe;
++	uint32	stbccts;
++	uint32	stbcctsfail;
++	uint32	nonstbccts;
++	uint32	nonstbcctsfail;
++} rrm_stat_group_15_t;
++
++/* RSNA, 28 bytes */
++#define DOT11_RRM_STATS_RPT_LEN_GRP_ID_16	28
++typedef struct rrm_stat_group_16 {
++	uint32	rsnacmacicverr;
++	uint32	rsnacmacreplay;
++	uint32	rsnarobustmgmtccmpreplay;
++	uint32	rsnatkipicverr;
++	uint32	rsnatkipicvreplay;
++	uint32	rsnaccmpdecrypterr;
++	uint32	rsnaccmpreplay;
++} rrm_stat_group_16_t;
++
++/* Transmit stream/category measurement request */
++BWL_PRE_PACKED_STRUCT struct dot11_rmreq_tx_stream {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++	uint16 interval;
++	uint16 duration;
++	struct ether_addr	peer;
++	uint8 traffic_id;
++	uint8 bin0_range;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmreq_tx_stream dot11_rmreq_tx_stream_t;
++#define DOT11_RMREQ_TXSTREAM_LEN	17
++
++/** Transmit stream/category measurement report */
++BWL_PRE_PACKED_STRUCT struct dot11_rmrep_tx_stream {
++	uint32 starttime[2];
++	uint16 duration;
++	struct ether_addr	peer;
++	uint8 traffic_id;
++	uint8 reason;
++	uint32 txmsdu_cnt;
++	uint32 msdu_discarded_cnt;
++	uint32 msdufailed_cnt;
++	uint32 msduretry_cnt;
++	uint32 cfpolls_lost_cnt;
++	uint32 avrqueue_delay;
++	uint32 avrtx_delay;
++	uint8 bin0_range;
++	uint32 bin0;
++	uint32 bin1;
++	uint32 bin2;
++	uint32 bin3;
++	uint32 bin4;
++	uint32 bin5;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmrep_tx_stream dot11_rmrep_tx_stream_t;
++#define DOT11_RMREP_TXSTREAM_LEN	71
++
++typedef struct rrm_tscm {
++	uint32 msdu_tx;
++	uint32 msdu_exp;
++	uint32 msdu_fail;
++	uint32 msdu_retries;
++	uint32 cfpolls_lost;
++	uint32 queue_delay;
++	uint32 tx_delay_sum;
++	uint32 tx_delay_cnt;
++	uint32 bin0_range_us;
++	uint32 bin0;
++	uint32 bin1;
++	uint32 bin2;
++	uint32 bin3;
++	uint32 bin4;
++	uint32 bin5;
++} rrm_tscm_t;
++enum {
++	DOT11_FTM_LOCATION_SUBJ_LOCAL = 0, 		/* Where am I? */
++	DOT11_FTM_LOCATION_SUBJ_REMOTE = 1,		/* Where are you? */
++	DOT11_FTM_LOCATION_SUBJ_THIRDPARTY = 2   /* Where is he/she? */
++};
++
++BWL_PRE_PACKED_STRUCT struct dot11_rmreq_ftm_lci {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++	uint8 subj;
++
++	/* Following 3 fields are unused. Keep for ROM compatibility. */
++	uint8 lat_res;
++	uint8 lon_res;
++	uint8 alt_res;
++
++	/* optional sub-elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmreq_ftm_lci dot11_rmreq_ftm_lci_t;
++#define DOT11_RMREQ_LCI_LEN	9
++
++BWL_PRE_PACKED_STRUCT struct dot11_rmrep_ftm_lci {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++	uint8 lci_sub_id;
++	uint8 lci_sub_len;
++	/* optional LCI field */
++	/* optional sub-elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmrep_ftm_lci dot11_rmrep_ftm_lci_t;
++
++#define DOT11_FTM_LCI_SUBELEM_ID 		0
++#define DOT11_FTM_LCI_SUBELEM_LEN 		2
++#define DOT11_FTM_LCI_FIELD_LEN 		16
++#define DOT11_FTM_LCI_UNKNOWN_LEN 		2
++
++BWL_PRE_PACKED_STRUCT struct dot11_rmreq_ftm_civic {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++	uint8 subj;
++	uint8 civloc_type;
++	uint8 siu;	/* service interval units */
++	uint16 si;  /* service interval */
++	/* optional sub-elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmreq_ftm_civic dot11_rmreq_ftm_civic_t;
++#define DOT11_RMREQ_CIVIC_LEN	10
++
++BWL_PRE_PACKED_STRUCT struct dot11_rmrep_ftm_civic {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++	uint8 civloc_type;
++	uint8 civloc_sub_id;
++	uint8 civloc_sub_len;
++	/* optional location civic field */
++	/* optional sub-elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmrep_ftm_civic dot11_rmrep_ftm_civic_t;
++
++#define DOT11_FTM_CIVIC_LOC_TYPE_RFC4776	0
++#define DOT11_FTM_CIVIC_SUBELEM_ID 			0
++#define DOT11_FTM_CIVIC_SUBELEM_LEN 		2
++#define DOT11_FTM_CIVIC_LOC_SI_NONE			0
++#define DOT11_FTM_CIVIC_TYPE_LEN			1
++#define DOT11_FTM_CIVIC_UNKNOWN_LEN 		3
++
++/* Location Identifier measurement request */
++BWL_PRE_PACKED_STRUCT struct dot11_rmreq_locid {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++	uint8 subj;
++	uint8 siu;
++	uint16 si;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmreq_locid dot11_rmreq_locid_t;
++#define DOT11_RMREQ_LOCID_LEN	9
++
++/* Location Identifier measurement report */
++BWL_PRE_PACKED_STRUCT struct dot11_rmrep_locid {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++	uint8 exp_tsf[8];
++	uint8 locid_sub_id;
++	uint8 locid_sub_len;
++	/* optional location identifier field */
++	/* optional sub-elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmrep_locid dot11_rmrep_locid_t;
++#define DOT11_LOCID_UNKNOWN_LEN		10
++#define DOT11_LOCID_SUBELEM_ID		0
++
++BWL_PRE_PACKED_STRUCT struct dot11_ftm_range_subel {
++	uint8 id;
++	uint8 len;
++	uint16 max_age;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_ftm_range_subel dot11_ftm_range_subel_t;
++#define DOT11_FTM_RANGE_SUBELEM_ID      4
++#define DOT11_FTM_RANGE_SUBELEM_LEN     2
++
++BWL_PRE_PACKED_STRUCT struct dot11_rmreq_ftm_range {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++	uint16 max_init_delay;		/* maximum random initial delay */
++	uint8 min_ap_count;
++	uint8 data[1];
++	/* neighbor report sub-elements */
++	/* optional sub-elements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmreq_ftm_range dot11_rmreq_ftm_range_t;
++#define DOT11_RMREQ_FTM_RANGE_LEN 8
++
++#define DOT11_FTM_RANGE_LEN		3
++BWL_PRE_PACKED_STRUCT struct dot11_ftm_range_entry {
++	uint32 start_tsf;		/* 4 lsb of tsf */
++	struct ether_addr bssid;
++	uint8 range[DOT11_FTM_RANGE_LEN];
++	uint8 max_err[DOT11_FTM_RANGE_LEN];
++	uint8  rsvd;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_ftm_range_entry dot11_ftm_range_entry_t;
++#define DOT11_FTM_RANGE_ENTRY_MAX_COUNT   15
++
++enum {
++	DOT11_FTM_RANGE_ERROR_AP_INCAPABLE = 2,
++	DOT11_FTM_RANGE_ERROR_AP_FAILED = 3,
++	DOT11_FTM_RANGE_ERROR_TX_FAILED = 8,
++	DOT11_FTM_RANGE_ERROR_MAX
++};
++
++BWL_PRE_PACKED_STRUCT struct dot11_ftm_range_error_entry {
++	uint32 start_tsf;		/* 4 lsb of tsf */
++	struct ether_addr bssid;
++	uint8  code;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_ftm_range_error_entry dot11_ftm_range_error_entry_t;
++#define DOT11_FTM_RANGE_ERROR_ENTRY_MAX_COUNT   11
++
++BWL_PRE_PACKED_STRUCT struct dot11_rmrep_ftm_range {
++    uint8 id;
++    uint8 len;
++    uint8 token;
++    uint8 mode;
++    uint8 type;
++    uint8 entry_count;
++    uint8 data[2]; /* includes pad */
++	/*
++	dot11_ftm_range_entry_t entries[entry_count];
++	uint8 error_count;
++	dot11_ftm_error_entry_t errors[error_count];
++	 */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmrep_ftm_range dot11_rmrep_ftm_range_t;
++
++#define DOT11_FTM_RANGE_REP_MIN_LEN     6       /* No extra byte for error_count */
++#define DOT11_FTM_RANGE_ENTRY_CNT_MAX   15
++#define DOT11_FTM_RANGE_ERROR_CNT_MAX   11
++#define DOT11_FTM_RANGE_REP_FIXED_LEN   1       /* No extra byte for error_count */
++/** Measurement pause request */
++BWL_PRE_PACKED_STRUCT struct dot11_rmreq_pause_time {
++	uint8 id;
++	uint8 len;
++	uint8 token;
++	uint8 mode;
++	uint8 type;
++	uint16 pause_time;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_rmreq_pause_time dot11_rmreq_pause_time_t;
++#define DOT11_RMREQ_PAUSE_LEN	7
++
++
++/* Neighbor Report subelements ID (11k & 11v) */
++#define DOT11_NGBR_TSF_INFO_SE_ID	1
++#define DOT11_NGBR_CCS_SE_ID		2
++#define DOT11_NGBR_BSSTRANS_PREF_SE_ID	3
++#define DOT11_NGBR_BSS_TERM_DUR_SE_ID	4
++#define DOT11_NGBR_BEARING_SE_ID	5
++#define DOT11_NGBR_WIDE_BW_CHAN_SE_ID	6
++
++/** Neighbor Report, BSS Transition Candidate Preference subelement */
++BWL_PRE_PACKED_STRUCT struct dot11_ngbr_bsstrans_pref_se {
++	uint8 sub_id;
++	uint8 len;
++	uint8 preference;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_ngbr_bsstrans_pref_se dot11_ngbr_bsstrans_pref_se_t;
++#define DOT11_NGBR_BSSTRANS_PREF_SE_LEN		1
++#define DOT11_NGBR_BSSTRANS_PREF_SE_IE_LEN	3
++#define DOT11_NGBR_BSSTRANS_PREF_SE_HIGHEST	0xff
++
++/** Neighbor Report, BSS Termination Duration subelement */
++BWL_PRE_PACKED_STRUCT struct dot11_ngbr_bss_term_dur_se {
++	uint8 sub_id;
++	uint8 len;
++	uint8 tsf[8];
++	uint16 duration;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_ngbr_bss_term_dur_se dot11_ngbr_bss_term_dur_se_t;
++#define DOT11_NGBR_BSS_TERM_DUR_SE_LEN	10
++
++/* Neighbor Report BSSID Information Field */
++#define DOT11_NGBR_BI_REACHABILTY_UNKN	0x0002
++#define DOT11_NGBR_BI_REACHABILTY	0x0003
++#define DOT11_NGBR_BI_SEC		0x0004
++#define DOT11_NGBR_BI_KEY_SCOPE		0x0008
++#define DOT11_NGBR_BI_CAP		0x03f0
++#define DOT11_NGBR_BI_CAP_SPEC_MGMT	0x0010
++#define DOT11_NGBR_BI_CAP_QOS		0x0020
++#define DOT11_NGBR_BI_CAP_APSD		0x0040
++#define DOT11_NGBR_BI_CAP_RDIO_MSMT	0x0080
++#define DOT11_NGBR_BI_CAP_DEL_BA	0x0100
++#define DOT11_NGBR_BI_CAP_IMM_BA	0x0200
++#define DOT11_NGBR_BI_MOBILITY		0x0400
++#define DOT11_NGBR_BI_HT		0x0800
++#define DOT11_NGBR_BI_VHT		0x1000
++#define DOT11_NGBR_BI_FTM		0x2000
++
++/** Neighbor Report element (11k & 11v) */
++BWL_PRE_PACKED_STRUCT struct dot11_neighbor_rep_ie {
++	uint8 id;
++	uint8 len;
++	struct ether_addr bssid;
++	uint32 bssid_info;
++	uint8 reg;		/* Operating class */
++	uint8 channel;
++	uint8 phytype;
++	uint8 data[1]; 		/* Variable size subelements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_neighbor_rep_ie dot11_neighbor_rep_ie_t;
++#define DOT11_NEIGHBOR_REP_IE_FIXED_LEN	13
++
++
++/* MLME Enumerations */
++#define DOT11_BSSTYPE_INFRASTRUCTURE		0	/* d11 infrastructure */
++#define DOT11_BSSTYPE_INDEPENDENT		1	/* d11 independent */
++#define DOT11_BSSTYPE_ANY			2	/* d11 any BSS type */
++#define DOT11_BSSTYPE_MESH			3	/* d11 Mesh */
++#define DOT11_SCANTYPE_ACTIVE			0	/* d11 scan active */
++#define DOT11_SCANTYPE_PASSIVE			1	/* d11 scan passive */
++
++/** Link Measurement */
++BWL_PRE_PACKED_STRUCT struct dot11_lmreq {
++	uint8 category;				/* category of action frame (5) */
++	uint8 action;				/* radio measurement action */
++	uint8 token;				/* dialog token */
++	uint8 txpwr;				/* Transmit Power Used */
++	uint8 maxtxpwr;				/* Max Transmit Power */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_lmreq dot11_lmreq_t;
++#define DOT11_LMREQ_LEN	5
++
++BWL_PRE_PACKED_STRUCT struct dot11_lmrep {
++	uint8 category;				/* category of action frame (5) */
++	uint8 action;				/* radio measurement action */
++	uint8 token;				/* dialog token */
++	dot11_tpc_rep_t tpc;			/* TPC element */
++	uint8 rxant;				/* Receive Antenna ID */
++	uint8 txant;				/* Transmit Antenna ID */
++	uint8 rcpi;				/* RCPI */
++	uint8 rsni;				/* RSNI */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_lmrep dot11_lmrep_t;
++#define DOT11_LMREP_LEN	11
++
++#define DOT11_MP_CAP_SPECTRUM			0x01	/* d11 cap. spectrum */
++#define DOT11_MP_CAP_SHORTSLOT			0x02	/* d11 cap. shortslot */
++/* Measurement Pilot */
++BWL_PRE_PACKED_STRUCT struct dot11_mprep {
++	uint8 cap_info;				/* Condensed capability Info. */
++	uint8 country[2];				/* Condensed country string */
++	uint8 opclass;				/* Op. Class */
++	uint8 channel;				/* Channel */
++	uint8 mp_interval;			/* Measurement Pilot Interval */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_mprep dot11_mprep_t;
++#define DOT11_MPREP_LEN	6
++
++/* 802.11 BRCM "Compromise" Pre N constants */
++#define PREN_PREAMBLE		24	/* green field preamble time */
++#define PREN_MM_EXT		12	/* extra mixed mode preamble time */
++#define PREN_PREAMBLE_EXT	4	/* extra preamble (multiply by unique_streams-1) */
++
++/* 802.11N PHY constants */
++#define RIFS_11N_TIME		2	/* NPHY RIFS time */
++
++/* 802.11 HT PLCP format 802.11n-2009, sec 20.3.9.4.3
++ * HT-SIG is composed of two 24 bit parts, HT-SIG1 and HT-SIG2
++ */
++/* HT-SIG1 */
++#define HT_SIG1_MCS_MASK        0x00007F
++#define HT_SIG1_CBW             0x000080
++#define HT_SIG1_HT_LENGTH       0xFFFF00
++
++/* HT-SIG2 */
++#define HT_SIG2_SMOOTHING       0x000001
++#define HT_SIG2_NOT_SOUNDING    0x000002
++#define HT_SIG2_RESERVED        0x000004
++#define HT_SIG2_AGGREGATION     0x000008
++#define HT_SIG2_STBC_MASK       0x000030
++#define HT_SIG2_STBC_SHIFT      4
++#define HT_SIG2_FEC_CODING      0x000040
++#define HT_SIG2_SHORT_GI        0x000080
++#define HT_SIG2_ESS_MASK        0x000300
++#define HT_SIG2_ESS_SHIFT       8
++#define HT_SIG2_CRC             0x03FC00
++#define HT_SIG2_TAIL            0x1C0000
++
++/* HT Timing-related parameters (802.11-2012, sec 20.3.6) */
++#define HT_T_LEG_PREAMBLE      16
++#define HT_T_L_SIG              4
++#define HT_T_SIG                8
++#define HT_T_LTF1               4
++#define HT_T_GF_LTF1            8
++#define HT_T_LTFs               4
++#define HT_T_STF                4
++#define HT_T_GF_STF             8
++#define HT_T_SYML               4
++
++#define HT_N_SERVICE           16       /* bits in SERVICE field */
++#define HT_N_TAIL               6       /* tail bits per BCC encoder */
++
++/* 802.11 A PHY constants */
++#define APHY_SLOT_TIME          9       /* APHY slot time */
++#define APHY_SIFS_TIME          16      /* APHY SIFS time */
++#define APHY_DIFS_TIME          (APHY_SIFS_TIME + (2 * APHY_SLOT_TIME))  /* APHY DIFS time */
++#define APHY_PREAMBLE_TIME      16      /* APHY preamble time */
++#define APHY_SIGNAL_TIME        4       /* APHY signal time */
++#define APHY_SYMBOL_TIME        4       /* APHY symbol time */
++#define APHY_SERVICE_NBITS      16      /* APHY service nbits */
++#define APHY_TAIL_NBITS         6       /* APHY tail nbits */
++#define APHY_CWMIN              15      /* APHY cwmin */
++#define APHY_PHYHDR_DUR		20	/* APHY PHY Header Duration */
++
++/* 802.11 B PHY constants */
++#define BPHY_SLOT_TIME          20      /* BPHY slot time */
++#define BPHY_SIFS_TIME          10      /* BPHY SIFS time */
++#define BPHY_DIFS_TIME          50      /* BPHY DIFS time */
++#define BPHY_PLCP_TIME          192     /* BPHY PLCP time */
++#define BPHY_PLCP_SHORT_TIME    96      /* BPHY PLCP short time */
++#define BPHY_CWMIN              31      /* BPHY cwmin */
++#define BPHY_SHORT_PHYHDR_DUR	96	/* BPHY Short PHY Header Duration */
++#define BPHY_LONG_PHYHDR_DUR	192	/* BPHY Long PHY Header Duration */
++
++/* 802.11 G constants */
++#define DOT11_OFDM_SIGNAL_EXTENSION	6	/* d11 OFDM signal extension */
++
++#define PHY_CWMAX		1023	/* PHY cwmax */
++
++#define	DOT11_MAXNUMFRAGS	16	/* max # fragments per MSDU */
++
++/* 802.11 VHT constants */
++
++typedef int vht_group_id_t;
++
++/* for VHT-A1 */
++/* SIG-A1 reserved bits */
++#define VHT_SIGA1_CONST_MASK            0x800004
++
++#define VHT_SIGA1_BW_MASK               0x000003
++#define VHT_SIGA1_20MHZ_VAL             0x000000
++#define VHT_SIGA1_40MHZ_VAL             0x000001
++#define VHT_SIGA1_80MHZ_VAL             0x000002
++#define VHT_SIGA1_160MHZ_VAL            0x000003
++
++#define VHT_SIGA1_STBC                  0x000008
++
++#define VHT_SIGA1_GID_MASK              0x0003f0
++#define VHT_SIGA1_GID_SHIFT             4
++#define VHT_SIGA1_GID_TO_AP             0x00
++#define VHT_SIGA1_GID_NOT_TO_AP         0x3f
++#define VHT_SIGA1_GID_MAX_GID           0x3f
++
++#define VHT_SIGA1_NSTS_SHIFT_MASK_USER0 0x001C00
++#define VHT_SIGA1_NSTS_SHIFT            10
++#define VHT_SIGA1_MAX_USERPOS           3
++
++#define VHT_SIGA1_PARTIAL_AID_MASK      0x3fe000
++#define VHT_SIGA1_PARTIAL_AID_SHIFT     13
++
++#define VHT_SIGA1_TXOP_PS_NOT_ALLOWED   0x400000
++
++/* for VHT-A2 */
++#define VHT_SIGA2_GI_NONE               0x000000
++#define VHT_SIGA2_GI_SHORT              0x000001
++#define VHT_SIGA2_GI_W_MOD10            0x000002
++#define VHT_SIGA2_CODING_LDPC           0x000004
++#define VHT_SIGA2_LDPC_EXTRA_OFDM_SYM   0x000008
++#define VHT_SIGA2_BEAMFORM_ENABLE       0x000100
++#define VHT_SIGA2_MCS_SHIFT             4
++
++#define VHT_SIGA2_B9_RESERVED           0x000200
++#define VHT_SIGA2_TAIL_MASK             0xfc0000
++#define VHT_SIGA2_TAIL_VALUE            0x000000
++
++/* VHT Timing-related parameters (802.11ac D4.0, sec 22.3.6) */
++#define VHT_T_LEG_PREAMBLE      16
++#define VHT_T_L_SIG              4
++#define VHT_T_SIG_A              8
++#define VHT_T_LTF                4
++#define VHT_T_STF                4
++#define VHT_T_SIG_B              4
++#define VHT_T_SYML               4
++
++#define VHT_N_SERVICE           16	/* bits in SERVICE field */
++#define VHT_N_TAIL               6	/* tail bits per BCC encoder */
++
++/** dot11Counters Table - 802.11 spec., Annex D */
++typedef struct d11cnt {
++	uint32		txfrag;		/* dot11TransmittedFragmentCount */
++	uint32		txmulti;	/* dot11MulticastTransmittedFrameCount */
++	uint32		txfail;		/* dot11FailedCount */
++	uint32		txretry;	/* dot11RetryCount */
++	uint32		txretrie;	/* dot11MultipleRetryCount */
++	uint32		rxdup;		/* dot11FrameduplicateCount */
++	uint32		txrts;		/* dot11RTSSuccessCount */
++	uint32		txnocts;	/* dot11RTSFailureCount */
++	uint32		txnoack;	/* dot11ACKFailureCount */
++	uint32		rxfrag;		/* dot11ReceivedFragmentCount */
++	uint32		rxmulti;	/* dot11MulticastReceivedFrameCount */
++	uint32		rxcrc;		/* dot11FCSErrorCount */
++	uint32		txfrmsnt;	/* dot11TransmittedFrameCount */
++	uint32		rxundec;	/* dot11WEPUndecryptableCount */
++} d11cnt_t;
++
++#define BRCM_PROP_OUI		"\x00\x90\x4C"
++
++
++#define BRCM_FTM_IE_TYPE			14
++
++/* #define HT_CAP_IE_TYPE			51
++ * #define HT_ADD_IE_TYPE			52
++ * #define BRCM_EXTCH_IE_TYPE		53
++ * #define MEMBER_OF_BRCM_PROP_IE_TYPE	54
++ * #define BRCM_RELMACST_IE_TYPE		55
++ * #define BRCM_EVT_WL_BSS_INFO		64
++ * #define RWL_ACTION_WIFI_FRAG_TYPE	85
++ * #define BTC_INFO_BRCM_PROP_IE_TYPE	90
++ * #define ULB_BRCM_PROP_IE_TYPE	91
++ * #define SDB_BRCM_PROP_IE_TYPE	92
++ */
++
++/* Action frame type for RWL */
++#define RWL_WIFI_DEFAULT		0
++#define RWL_WIFI_FIND_MY_PEER		9 /* Used while finding server */
++#define RWL_WIFI_FOUND_PEER		10 /* Server response to the client  */
++#define RWL_ACTION_WIFI_FRAG_TYPE	85 /* Fragment indicator for receiver */
++
++#define PROXD_AF_TYPE			11 /* Wifi proximity action frame type */
++#define BRCM_RELMACST_AF_TYPE	        12 /* RMC action frame type */
++
++/* Action frame type for FTM Initiator Report */
++#define BRCM_FTM_VS_AF_TYPE	14
++enum {
++	BRCM_FTM_VS_INITIATOR_RPT_SUBTYPE = 1,	/* FTM Initiator Report */
++	BRCM_FTM_VS_COLLECT_SUBTYPE = 2,	/* FTM Collect debug protocol */
++};
++
++
++
++
++/* brcm syscap_ie cap */
++#define BRCM_SYSCAP_WET_TUNNEL	0x0100	/* Device with WET_TUNNEL support */
++
++#define BRCM_OUI		"\x00\x10\x18"	/* Broadcom OUI */
++
++/** BRCM info element */
++BWL_PRE_PACKED_STRUCT struct brcm_ie {
++	uint8	id;		/* IE ID, 221, DOT11_MNG_PROPR_ID */
++	uint8	len;		/* IE length */
++	uint8	oui[3];
++	uint8	ver;		/* type/ver of this IE */
++	uint8	assoc;		/* # of assoc STAs */
++	uint8	flags;		/* misc flags */
++	uint8	flags1;		/* misc flags */
++	uint16	amsdu_mtu_pref;	/* preferred A-MSDU MTU */
++} BWL_POST_PACKED_STRUCT;
++typedef	struct brcm_ie brcm_ie_t;
++#define BRCM_IE_LEN		11	/* BRCM IE length */
++#define BRCM_IE_VER		2	/* BRCM IE version */
++#define BRCM_IE_LEGACY_AES_VER	1	/* BRCM IE legacy AES version */
++
++/* brcm_ie flags */
++#define	BRF_ABCAP		0x1	/* afterburner is obsolete,  defined for backward compat */
++#define	BRF_ABRQRD		0x2	/* afterburner is obsolete,  defined for backward compat */
++#define	BRF_LZWDS		0x4	/* lazy wds enabled */
++#define	BRF_BLOCKACK		0x8	/* BlockACK capable */
++#define BRF_ABCOUNTER_MASK	0xf0	/* afterburner is obsolete,  defined for backward compat */
++#define BRF_PROP_11N_MCS	0x10	/* re-use afterburner bit */
++#define BRF_MEDIA_CLIENT	0x20	/* re-use afterburner bit to indicate media client device */
++
++#define GET_BRF_PROP_11N_MCS(brcm_ie) \
++	(!((brcm_ie)->flags & BRF_ABCAP) && ((brcm_ie)->flags & BRF_PROP_11N_MCS))
++
++/* brcm_ie flags1 */
++#define	BRF1_AMSDU		0x1	/* A-MSDU capable */
++#define	BRF1_WNM		0x2	/* WNM capable */
++#define BRF1_WMEPS		0x4	/* AP is capable of handling WME + PS w/o APSD */
++#define BRF1_PSOFIX		0x8	/* AP has fixed PS mode out-of-order packets */
++#define	BRF1_RX_LARGE_AGG	0x10	/* device can rx large aggregates */
++#define BRF1_RFAWARE_DCS	0x20    /* RFAWARE dynamic channel selection (DCS) */
++#define BRF1_SOFTAP		0x40    /* Configure as Broadcom SOFTAP */
++#define BRF1_DWDS		0x80    /* DWDS capable */
++
++/** Vendor IE structure */
++BWL_PRE_PACKED_STRUCT struct vndr_ie {
++	uchar id;
++	uchar len;
++	uchar oui [3];
++	uchar data [1]; 	/* Variable size data */
++} BWL_POST_PACKED_STRUCT;
++typedef struct vndr_ie vndr_ie_t;
++
++#define VNDR_IE_HDR_LEN		2	/* id + len field */
++#define VNDR_IE_MIN_LEN		3	/* size of the oui field */
++#define VNDR_IE_FIXED_LEN	(VNDR_IE_HDR_LEN + VNDR_IE_MIN_LEN)
++
++#define VNDR_IE_MAX_LEN		255	/* vendor IE max length, without ID and len */
++
++/** BRCM PROP DEVICE PRIMARY MAC ADDRESS IE */
++BWL_PRE_PACKED_STRUCT struct member_of_brcm_prop_ie {
++	uchar id;
++	uchar len;
++	uchar oui[3];
++	uint8	type;           /* type indicates what follows */
++	struct ether_addr ea;   /* Device Primary MAC Adrress */
++} BWL_POST_PACKED_STRUCT;
++typedef struct member_of_brcm_prop_ie member_of_brcm_prop_ie_t;
++
++#define MEMBER_OF_BRCM_PROP_IE_LEN		10	/* IE max length */
++#define MEMBER_OF_BRCM_PROP_IE_HDRLEN	        (sizeof(member_of_brcm_prop_ie_t))
++#define MEMBER_OF_BRCM_PROP_IE_TYPE		54
++
++/** BRCM Reliable Multicast IE */
++BWL_PRE_PACKED_STRUCT struct relmcast_brcm_prop_ie {
++	uint8 id;
++	uint8 len;
++	uint8 oui[3];
++	uint8 type;           /* type indicates what follows */
++	struct ether_addr ea;   /* The ack sender's MAC Adrress */
++	struct ether_addr mcast_ea;  /* The multicast MAC address */
++	uint8 updtmo; /* time interval(second) for client to send null packet to report its rssi */
++} BWL_POST_PACKED_STRUCT;
++typedef struct relmcast_brcm_prop_ie relmcast_brcm_prop_ie_t;
++
++/* IE length */
++/* BRCM_PROP_IE_LEN = sizeof(relmcast_brcm_prop_ie_t)-((sizeof (id) + sizeof (len)))? */
++#define RELMCAST_BRCM_PROP_IE_LEN	(sizeof(relmcast_brcm_prop_ie_t)-(2*sizeof(uint8)))
++
++#define RELMCAST_BRCM_PROP_IE_TYPE	55
++
++/* BRCM BTC IE */
++BWL_PRE_PACKED_STRUCT struct btc_brcm_prop_ie {
++	uint8 id;
++	uint8 len;
++	uint8 oui[3];
++	uint8 type;           /* type inidicates what follows */
++	uint32 info;
++} BWL_POST_PACKED_STRUCT;
++typedef struct btc_brcm_prop_ie btc_brcm_prop_ie_t;
++
++#define BTC_INFO_BRCM_PROP_IE_TYPE	90
++#define BRCM_BTC_INFO_TYPE_LEN	(sizeof(btc_brcm_prop_ie_t) - (2 * sizeof(uint8)))
++
++/* ************* HT definitions. ************* */
++#define MCSSET_LEN	16	/* 16-bits per 8-bit set to give 128-bits bitmap of MCS Index */
++#define MAX_MCS_NUM	(128)	/* max mcs number = 128 */
++
++BWL_PRE_PACKED_STRUCT struct ht_cap_ie {
++	uint16	cap;
++	uint8	params;
++	uint8	supp_mcs[MCSSET_LEN];
++	uint16	ext_htcap;
++	uint32	txbf_cap;
++	uint8	as_cap;
++} BWL_POST_PACKED_STRUCT;
++typedef struct ht_cap_ie ht_cap_ie_t;
++
++BWL_PRE_PACKED_STRUCT struct dot11_ht_cap_ie {
++	uint8	id;
++	uint8	len;
++	ht_cap_ie_t ht_cap;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_ht_cap_ie dot11_ht_cap_ie_t;
++
++/* CAP IE: HT 1.0 spec. simply stole a 802.11 IE, we use our prop. IE until this is resolved */
++/* the capability IE is primarily used to convey this nodes abilities */
++BWL_PRE_PACKED_STRUCT struct ht_prop_cap_ie {
++	uint8	id;		/* IE ID, 221, DOT11_MNG_PROPR_ID */
++	uint8	len;		/* IE length */
++	uint8	oui[3];
++	uint8	type;           /* type indicates what follows */
++	ht_cap_ie_t cap_ie;
++} BWL_POST_PACKED_STRUCT;
++typedef struct ht_prop_cap_ie ht_prop_cap_ie_t;
++
++#define HT_PROP_IE_OVERHEAD	4	/* overhead bytes for prop oui ie */
++#define HT_CAP_IE_LEN		26	/* HT capability len (based on .11n d2.0) */
++#define HT_CAP_IE_TYPE		51
++
++#define HT_CAP_LDPC_CODING	0x0001	/* Support for rx of LDPC coded pkts */
++#define HT_CAP_40MHZ		0x0002  /* FALSE:20Mhz, TRUE:20/40MHZ supported */
++#define HT_CAP_MIMO_PS_MASK	0x000C  /* Mimo PS mask */
++#define HT_CAP_MIMO_PS_SHIFT	0x0002	/* Mimo PS shift */
++#define HT_CAP_MIMO_PS_OFF	0x0003	/* Mimo PS, no restriction */
++#define HT_CAP_MIMO_PS_RTS	0x0001	/* Mimo PS, send RTS/CTS around MIMO frames */
++#define HT_CAP_MIMO_PS_ON	0x0000	/* Mimo PS, MIMO disallowed */
++#define HT_CAP_GF		0x0010	/* Greenfield preamble support */
++#define HT_CAP_SHORT_GI_20	0x0020	/* 20MHZ short guard interval support */
++#define HT_CAP_SHORT_GI_40	0x0040	/* 40Mhz short guard interval support */
++#define HT_CAP_TX_STBC		0x0080	/* Tx STBC support */
++#define HT_CAP_RX_STBC_MASK	0x0300	/* Rx STBC mask */
++#define HT_CAP_RX_STBC_SHIFT	8	/* Rx STBC shift */
++#define HT_CAP_DELAYED_BA	0x0400	/* delayed BA support */
++#define HT_CAP_MAX_AMSDU	0x0800	/* Max AMSDU size in bytes , 0=3839, 1=7935 */
++
++#define HT_CAP_DSSS_CCK	0x1000	/* DSSS/CCK supported by the BSS */
++#define HT_CAP_PSMP		0x2000	/* Power Save Multi Poll support */
++#define HT_CAP_40MHZ_INTOLERANT 0x4000	/* 40MHz Intolerant */
++#define HT_CAP_LSIG_TXOP	0x8000	/* L-SIG TXOP protection support */
++
++#define HT_CAP_RX_STBC_NO		0x0	/* no rx STBC support */
++#define HT_CAP_RX_STBC_ONE_STREAM	0x1	/* rx STBC support of 1 spatial stream */
++#define HT_CAP_RX_STBC_TWO_STREAM	0x2	/* rx STBC support of 1-2 spatial streams */
++#define HT_CAP_RX_STBC_THREE_STREAM	0x3	/* rx STBC support of 1-3 spatial streams */
++
++
++#define HT_CAP_TXBF_CAP_IMPLICIT_TXBF_RX	0x1
++#define HT_CAP_TXBF_CAP_NDP_RX			0x8
++#define HT_CAP_TXBF_CAP_NDP_TX			0x10
++#define HT_CAP_TXBF_CAP_EXPLICIT_CSI		0x100
++#define HT_CAP_TXBF_CAP_EXPLICIT_NC_STEERING	0x200
++#define HT_CAP_TXBF_CAP_EXPLICIT_C_STEERING	0x400
++#define HT_CAP_TXBF_CAP_EXPLICIT_CSI_FB_MASK	0x1800
++#define HT_CAP_TXBF_CAP_EXPLICIT_CSI_FB_SHIFT	11
++#define HT_CAP_TXBF_CAP_EXPLICIT_NC_FB_MASK	0x6000
++#define HT_CAP_TXBF_CAP_EXPLICIT_NC_FB_SHIFT	13
++#define HT_CAP_TXBF_CAP_EXPLICIT_C_FB_MASK	0x18000
++#define HT_CAP_TXBF_CAP_EXPLICIT_C_FB_SHIFT	15
++#define HT_CAP_TXBF_CAP_CSI_BFR_ANT_SHIFT	19
++#define HT_CAP_TXBF_CAP_NC_BFR_ANT_SHIFT	21
++#define HT_CAP_TXBF_CAP_C_BFR_ANT_SHIFT		23
++#define HT_CAP_TXBF_CAP_C_BFR_ANT_MASK		0x1800000
++
++#define HT_CAP_TXBF_CAP_CHAN_ESTIM_SHIFT	27
++#define HT_CAP_TXBF_CAP_CHAN_ESTIM_MASK		0x18000000
++
++#define HT_CAP_TXBF_FB_TYPE_NONE 	0
++#define HT_CAP_TXBF_FB_TYPE_DELAYED 	1
++#define HT_CAP_TXBF_FB_TYPE_IMMEDIATE 	2
++#define HT_CAP_TXBF_FB_TYPE_BOTH 	3
++
++#define HT_CAP_TX_BF_CAP_EXPLICIT_CSI_FB_MASK	0x400
++#define HT_CAP_TX_BF_CAP_EXPLICIT_CSI_FB_SHIFT	10
++#define HT_CAP_TX_BF_CAP_EXPLICIT_COMPRESSED_FB_MASK 0x18000
++#define HT_CAP_TX_BF_CAP_EXPLICIT_COMPRESSED_FB_SHIFT 15
++
++#define HT_CAP_MCS_FLAGS_SUPP_BYTE 12 /* byte offset in HT Cap Supported MCS for various flags */
++#define HT_CAP_MCS_RX_8TO15_BYTE_OFFSET                1
++#define HT_CAP_MCS_FLAGS_TX_RX_UNEQUAL              0x02
++#define HT_CAP_MCS_FLAGS_MAX_SPATIAL_STREAM_MASK    0x0C
++
++#define VHT_MAX_MPDU		11454	/* max mpdu size for now (bytes) */
++#define VHT_MPDU_MSDU_DELTA	56		/* Difference in spec - vht mpdu, amsdu len */
++/* Max AMSDU len - per spec */
++#define VHT_MAX_AMSDU		(VHT_MAX_MPDU - VHT_MPDU_MSDU_DELTA)
++
++#define HT_MAX_AMSDU		7935	/* max amsdu size (bytes) per the HT spec */
++#define HT_MIN_AMSDU		3835	/* min amsdu size (bytes) per the HT spec */
++
++#define HT_PARAMS_RX_FACTOR_MASK	0x03	/* ampdu rcv factor mask */
++#define HT_PARAMS_DENSITY_MASK		0x1C	/* ampdu density mask */
++#define HT_PARAMS_DENSITY_SHIFT	2	/* ampdu density shift */
++
++/* HT/AMPDU specific define */
++#define AMPDU_MAX_MPDU_DENSITY  7       /* max mpdu density; in 1/4 usec units */
++#define AMPDU_DENSITY_NONE      0       /* No density requirement */
++#define AMPDU_DENSITY_1over4_US 1       /* 1/4 us density */
++#define AMPDU_DENSITY_1over2_US 2       /* 1/2 us density */
++#define AMPDU_DENSITY_1_US      3       /*   1 us density */
++#define AMPDU_DENSITY_2_US      4       /*   2 us density */
++#define AMPDU_DENSITY_4_US      5       /*   4 us density */
++#define AMPDU_DENSITY_8_US      6       /*   8 us density */
++#define AMPDU_DENSITY_16_US     7       /*  16 us density */
++#define AMPDU_RX_FACTOR_8K      0       /* max rcv ampdu len (8kb) */
++#define AMPDU_RX_FACTOR_16K     1       /* max rcv ampdu len (16kb) */
++#define AMPDU_RX_FACTOR_32K     2       /* max rcv ampdu len (32kb) */
++#define AMPDU_RX_FACTOR_64K     3       /* max rcv ampdu len (64kb) */
++
++/* AMPDU RX factors for VHT rates */
++#define AMPDU_RX_FACTOR_128K    4       /* max rcv ampdu len (128kb) */
++#define AMPDU_RX_FACTOR_256K    5       /* max rcv ampdu len (256kb) */
++#define AMPDU_RX_FACTOR_512K    6       /* max rcv ampdu len (512kb) */
++#define AMPDU_RX_FACTOR_1024K   7       /* max rcv ampdu len (1024kb) */
++
++#define AMPDU_RX_FACTOR_BASE    8*1024  /* ampdu factor base for rx len */
++#define AMPDU_RX_FACTOR_BASE_PWR	13	/* ampdu factor base for rx len in power of 2 */
++
++#define AMPDU_DELIMITER_LEN	4	/* length of ampdu delimiter */
++#define AMPDU_DELIMITER_LEN_MAX	63	/* max length of ampdu delimiter(enforced in HW) */
++
++#define HT_CAP_EXT_PCO			0x0001
++#define HT_CAP_EXT_PCO_TTIME_MASK	0x0006
++#define HT_CAP_EXT_PCO_TTIME_SHIFT	1
++#define HT_CAP_EXT_MCS_FEEDBACK_MASK	0x0300
++#define HT_CAP_EXT_MCS_FEEDBACK_SHIFT	8
++#define HT_CAP_EXT_HTC			0x0400
++#define HT_CAP_EXT_RD_RESP		0x0800
++
++/** 'ht_add' is called 'HT Operation' information element in the 802.11 standard */
++BWL_PRE_PACKED_STRUCT struct ht_add_ie {
++	uint8	ctl_ch;			/* control channel number */
++	uint8	byte1;			/* ext ch,rec. ch. width, RIFS support */
++	uint16	opmode;			/* operation mode */
++	uint16	misc_bits;		/* misc bits */
++	uint8	basic_mcs[MCSSET_LEN];  /* required MCS set */
++} BWL_POST_PACKED_STRUCT;
++typedef struct ht_add_ie ht_add_ie_t;
++
++/* ADD IE: HT 1.0 spec. simply stole a 802.11 IE, we use our prop. IE until this is resolved */
++/* the additional IE is primarily used to convey the current BSS configuration */
++BWL_PRE_PACKED_STRUCT struct ht_prop_add_ie {
++	uint8	id;		/* IE ID, 221, DOT11_MNG_PROPR_ID */
++	uint8	len;		/* IE length */
++	uint8	oui[3];
++	uint8	type;		/* indicates what follows */
++	ht_add_ie_t add_ie;
++} BWL_POST_PACKED_STRUCT;
++typedef struct ht_prop_add_ie ht_prop_add_ie_t;
++
++#define HT_ADD_IE_LEN	22
++#define HT_ADD_IE_TYPE	52
++
++/* byte1 defn's */
++#define HT_BW_ANY		0x04	/* set, STA can use 20 or 40MHz */
++#define HT_RIFS_PERMITTED     	0x08	/* RIFS allowed */
++
++/* opmode defn's */
++#define HT_OPMODE_MASK	        0x0003	/* protection mode mask */
++#define HT_OPMODE_SHIFT		0	/* protection mode shift */
++#define HT_OPMODE_PURE		0x0000	/* protection mode PURE */
++#define HT_OPMODE_OPTIONAL	0x0001	/* protection mode optional */
++#define HT_OPMODE_HT20IN40	0x0002	/* protection mode 20MHz HT in 40MHz BSS */
++#define HT_OPMODE_MIXED	0x0003	/* protection mode Mixed Mode */
++#define HT_OPMODE_NONGF	0x0004	/* protection mode non-GF */
++#define DOT11N_TXBURST		0x0008	/* Tx burst limit */
++#define DOT11N_OBSS_NONHT	0x0010	/* OBSS Non-HT STA present */
++#define HT_OPMODE_CCFS2_MASK	0x1fe0	/* Channel Center Frequency Segment 2 mask */
++#define HT_OPMODE_CCFS2_SHIFT	5	/* Channel Center Frequency Segment 2 shift */
++
++/* misc_bites defn's */
++#define HT_BASIC_STBC_MCS	0x007f	/* basic STBC MCS */
++#define HT_DUAL_STBC_PROT	0x0080	/* Dual STBC Protection */
++#define HT_SECOND_BCN		0x0100	/* Secondary beacon support */
++#define HT_LSIG_TXOP		0x0200	/* L-SIG TXOP Protection full support */
++#define HT_PCO_ACTIVE		0x0400	/* PCO active */
++#define HT_PCO_PHASE		0x0800	/* PCO phase */
++#define HT_DUALCTS_PROTECTION	0x0080	/* DUAL CTS protection needed */
++
++/* Tx Burst Limits */
++#define DOT11N_2G_TXBURST_LIMIT	6160	/* 2G band Tx burst limit per 802.11n Draft 1.10 (usec) */
++#define DOT11N_5G_TXBURST_LIMIT	3080	/* 5G band Tx burst limit per 802.11n Draft 1.10 (usec) */
++
++/* Macros for opmode */
++#define GET_HT_OPMODE(add_ie)		((ltoh16_ua(&add_ie->opmode) & HT_OPMODE_MASK) \
++					>> HT_OPMODE_SHIFT)
++#define HT_MIXEDMODE_PRESENT(add_ie)	((ltoh16_ua(&add_ie->opmode) & HT_OPMODE_MASK) \
++					== HT_OPMODE_MIXED)	/* mixed mode present */
++#define HT_HT20_PRESENT(add_ie)	((ltoh16_ua(&add_ie->opmode) & HT_OPMODE_MASK) \
++					== HT_OPMODE_HT20IN40)	/* 20MHz HT present */
++#define HT_OPTIONAL_PRESENT(add_ie)	((ltoh16_ua(&add_ie->opmode) & HT_OPMODE_MASK) \
++					== HT_OPMODE_OPTIONAL)	/* Optional protection present */
++#define HT_USE_PROTECTION(add_ie)	(HT_HT20_PRESENT((add_ie)) || \
++					HT_MIXEDMODE_PRESENT((add_ie))) /* use protection */
++#define HT_NONGF_PRESENT(add_ie)	((ltoh16_ua(&add_ie->opmode) & HT_OPMODE_NONGF) \
++					== HT_OPMODE_NONGF)	/* non-GF present */
++#define DOT11N_TXBURST_PRESENT(add_ie)	((ltoh16_ua(&add_ie->opmode) & DOT11N_TXBURST) \
++					== DOT11N_TXBURST)	/* Tx Burst present */
++#define DOT11N_OBSS_NONHT_PRESENT(add_ie)	((ltoh16_ua(&add_ie->opmode) & DOT11N_OBSS_NONHT) \
++					== DOT11N_OBSS_NONHT)	/* OBSS Non-HT present */
++#define HT_OPMODE_CCFS2_GET(add_ie)	((ltoh16_ua(&(add_ie)->opmode) & HT_OPMODE_CCFS2_MASK) \
++					>> HT_OPMODE_CCFS2_SHIFT)	/* get CCFS2 */
++#define HT_OPMODE_CCFS2_SET(add_ie, ccfs2)	do { /* set CCFS2 */ \
++	(add_ie)->opmode &= htol16(~HT_OPMODE_CCFS2_MASK); \
++	(add_ie)->opmode |= htol16(((ccfs2) << HT_OPMODE_CCFS2_SHIFT) & HT_OPMODE_CCFS2_MASK); \
++} while (0)
++
++/* Macros for HT MCS field access */
++#define HT_CAP_MCS_BITMASK(supp_mcs)                 \
++	((supp_mcs)[HT_CAP_MCS_RX_8TO15_BYTE_OFFSET])
++#define HT_CAP_MCS_TX_RX_UNEQUAL(supp_mcs)          \
++	((supp_mcs)[HT_CAP_MCS_FLAGS_SUPP_BYTE] & HT_CAP_MCS_FLAGS_TX_RX_UNEQUAL)
++#define HT_CAP_MCS_TX_STREAM_SUPPORT(supp_mcs)          \
++		((supp_mcs)[HT_CAP_MCS_FLAGS_SUPP_BYTE] & HT_CAP_MCS_FLAGS_MAX_SPATIAL_STREAM_MASK)
++
++BWL_PRE_PACKED_STRUCT struct obss_params {
++	uint16	passive_dwell;
++	uint16	active_dwell;
++	uint16	bss_widthscan_interval;
++	uint16	passive_total;
++	uint16	active_total;
++	uint16	chanwidth_transition_dly;
++	uint16	activity_threshold;
++} BWL_POST_PACKED_STRUCT;
++typedef struct obss_params obss_params_t;
++
++BWL_PRE_PACKED_STRUCT struct dot11_obss_ie {
++	uint8	id;
++	uint8	len;
++	obss_params_t obss_params;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_obss_ie dot11_obss_ie_t;
++#define DOT11_OBSS_SCAN_IE_LEN	sizeof(obss_params_t)	/* HT OBSS len (based on 802.11n d3.0) */
++
++/* HT control field */
++#define HT_CTRL_LA_TRQ		0x00000002	/* sounding request */
++#define HT_CTRL_LA_MAI		0x0000003C	/* MCS request or antenna selection indication */
++#define HT_CTRL_LA_MAI_SHIFT	2
++#define HT_CTRL_LA_MAI_MRQ	0x00000004	/* MCS request */
++#define HT_CTRL_LA_MAI_MSI	0x00000038	/* MCS request sequence identifier */
++#define HT_CTRL_LA_MFSI		0x000001C0	/* MFB sequence identifier */
++#define HT_CTRL_LA_MFSI_SHIFT	6
++#define HT_CTRL_LA_MFB_ASELC	0x0000FE00	/* MCS feedback, antenna selection command/data */
++#define HT_CTRL_LA_MFB_ASELC_SH	9
++#define HT_CTRL_LA_ASELC_CMD	0x00000C00	/* ASEL command */
++#define HT_CTRL_LA_ASELC_DATA	0x0000F000	/* ASEL data */
++#define HT_CTRL_CAL_POS		0x00030000	/* Calibration position */
++#define HT_CTRL_CAL_SEQ		0x000C0000	/* Calibration sequence */
++#define HT_CTRL_CSI_STEERING	0x00C00000	/* CSI/Steering */
++#define HT_CTRL_CSI_STEER_SHIFT	22
++#define HT_CTRL_CSI_STEER_NFB	0		/* no fedback required */
++#define HT_CTRL_CSI_STEER_CSI	1		/* CSI, H matrix */
++#define HT_CTRL_CSI_STEER_NCOM	2		/* non-compressed beamforming */
++#define HT_CTRL_CSI_STEER_COM	3		/* compressed beamforming */
++#define HT_CTRL_NDP_ANNOUNCE	0x01000000	/* NDP announcement */
++#define HT_CTRL_AC_CONSTRAINT	0x40000000	/* AC Constraint */
++#define HT_CTRL_RDG_MOREPPDU	0x80000000	/* RDG/More PPDU */
++
++/* ************* VHT definitions. ************* */
++
++/**
++ * VHT Capabilites IE (sec 8.4.2.160)
++ */
++
++BWL_PRE_PACKED_STRUCT struct vht_cap_ie {
++	uint32  vht_cap_info;
++	/* supported MCS set - 64 bit field */
++	uint16	rx_mcs_map;
++	uint16  rx_max_rate;
++	uint16  tx_mcs_map;
++	uint16	tx_max_rate;
++} BWL_POST_PACKED_STRUCT;
++typedef struct vht_cap_ie vht_cap_ie_t;
++
++/* 4B cap_info + 8B supp_mcs */
++#define VHT_CAP_IE_LEN 12
++
++/* VHT Capabilities Info field - 32bit - in VHT Cap IE */
++#define VHT_CAP_INFO_MAX_MPDU_LEN_MASK          0x00000003
++#define VHT_CAP_INFO_SUPP_CHAN_WIDTH_MASK       0x0000000c
++#define VHT_CAP_INFO_LDPC                       0x00000010
++#define VHT_CAP_INFO_SGI_80MHZ                  0x00000020
++#define VHT_CAP_INFO_SGI_160MHZ                 0x00000040
++#define VHT_CAP_INFO_TX_STBC                    0x00000080
++#define VHT_CAP_INFO_RX_STBC_MASK               0x00000700
++#define VHT_CAP_INFO_RX_STBC_SHIFT              8
++#define VHT_CAP_INFO_SU_BEAMFMR                 0x00000800
++#define VHT_CAP_INFO_SU_BEAMFMEE                0x00001000
++#define VHT_CAP_INFO_NUM_BMFMR_ANT_MASK         0x0000e000
++#define VHT_CAP_INFO_NUM_BMFMR_ANT_SHIFT        13
++#define VHT_CAP_INFO_NUM_SOUNDING_DIM_MASK      0x00070000
++#define VHT_CAP_INFO_NUM_SOUNDING_DIM_SHIFT     16
++#define VHT_CAP_INFO_MU_BEAMFMR                 0x00080000
++#define VHT_CAP_INFO_MU_BEAMFMEE                0x00100000
++#define VHT_CAP_INFO_TXOPPS                     0x00200000
++#define VHT_CAP_INFO_HTCVHT                     0x00400000
++#define VHT_CAP_INFO_AMPDU_MAXLEN_EXP_MASK      0x03800000
++#define VHT_CAP_INFO_AMPDU_MAXLEN_EXP_SHIFT     23
++#define VHT_CAP_INFO_LINK_ADAPT_CAP_MASK        0x0c000000
++#define VHT_CAP_INFO_LINK_ADAPT_CAP_SHIFT       26
++#define VHT_CAP_INFO_EXT_NSS_BW_SUP_MASK        0xc0000000
++#define VHT_CAP_INFO_EXT_NSS_BW_SUP_SHIFT       30
++
++/* get Extended NSS BW Support passing vht cap info */
++#define VHT_CAP_EXT_NSS_BW_SUP(cap_info) \
++	(((cap_info) & VHT_CAP_INFO_EXT_NSS_BW_SUP_MASK) >> VHT_CAP_INFO_EXT_NSS_BW_SUP_SHIFT)
++
++/* VHT CAP INFO extended NSS BW support - refer to IEEE 802.11 REVmc D8.0 Figure 9-559 */
++#define VHT_CAP_INFO_EXT_NSS_BW_HALF_160	1 /* 160MHz at half NSS CAP */
++#define VHT_CAP_INFO_EXT_NSS_BW_HALF_160_80P80	2 /* 160 & 80p80 MHz at half NSS CAP */
++
++/* VHT Supported MCS Set - 64-bit - in VHT Cap IE */
++#define VHT_CAP_SUPP_MCS_RX_HIGHEST_RATE_MASK   0x1fff
++#define VHT_CAP_SUPP_MCS_RX_HIGHEST_RATE_SHIFT  0
++#define VHT_CAP_SUPP_CHAN_WIDTH_SHIFT		5
++
++#define VHT_CAP_SUPP_MCS_TX_HIGHEST_RATE_MASK   0x1fff
++#define VHT_CAP_SUPP_MCS_TX_HIGHEST_RATE_SHIFT  0
++
++/* defines for field(s) in vht_cap_ie->rx_max_rate */
++#define VHT_CAP_MAX_NSTS_MASK			0xe000
++#define VHT_CAP_MAX_NSTS_SHIFT			13
++
++/* defines for field(s) in vht_cap_ie->tx_max_rate */
++#define VHT_CAP_EXT_NSS_BW_CAP			0x2000
++
++#define VHT_CAP_MCS_MAP_0_7                     0
++#define VHT_CAP_MCS_MAP_0_8                     1
++#define VHT_CAP_MCS_MAP_0_9                     2
++#define VHT_CAP_MCS_MAP_NONE                    3
++#define VHT_CAP_MCS_MAP_S                       2 /* num bits for 1-stream */
++#define VHT_CAP_MCS_MAP_M                       0x3 /* mask for 1-stream */
++/* assumes VHT_CAP_MCS_MAP_NONE is 3 and 2 bits are used for encoding */
++#define VHT_CAP_MCS_MAP_NONE_ALL                0xffff
++
++/* VHT rates bitmap */
++#define VHT_CAP_MCS_0_7_RATEMAP		0x00ff
++#define VHT_CAP_MCS_0_8_RATEMAP		0x01ff
++#define VHT_CAP_MCS_0_9_RATEMAP		0x03ff
++#define VHT_CAP_MCS_FULL_RATEMAP 	VHT_CAP_MCS_0_9_RATEMAP
++
++#define VHT_PROP_MCS_MAP_10_11                   0
++#define VHT_PROP_MCS_MAP_UNUSED1                 1
++#define VHT_PROP_MCS_MAP_UNUSED2                 2
++#define VHT_PROP_MCS_MAP_NONE                    3
++#define VHT_PROP_MCS_MAP_NONE_ALL                0xffff
++
++/* VHT prop rates bitmap */
++#define VHT_PROP_MCS_10_11_RATEMAP	0x0c00
++#define VHT_PROP_MCS_FULL_RATEMAP	VHT_PROP_MCS_10_11_RATEMAP
++
++#if !defined(VHT_CAP_MCS_MAP_0_9_NSS3)
++/* mcsmap with MCS0-9 for Nss = 3 */
++#define VHT_CAP_MCS_MAP_0_9_NSS3 \
++	        ((VHT_CAP_MCS_MAP_0_9 << VHT_MCS_MAP_GET_SS_IDX(1)) | \
++	         (VHT_CAP_MCS_MAP_0_9 << VHT_MCS_MAP_GET_SS_IDX(2)) | \
++	         (VHT_CAP_MCS_MAP_0_9 << VHT_MCS_MAP_GET_SS_IDX(3)))
++#endif /* !VHT_CAP_MCS_MAP_0_9_NSS3 */
++
++#define VHT_CAP_MCS_MAP_NSS_MAX                 8
++
++/* get mcsmap with given mcs for given nss streams */
++#define VHT_CAP_MCS_MAP_CREATE(mcsmap, nss, mcs) \
++	do { \
++		int i; \
++		for (i = 1; i <= nss; i++) { \
++			VHT_MCS_MAP_SET_MCS_PER_SS(i, mcs, mcsmap); \
++		} \
++	} while (0)
++
++/* Map the mcs code to mcs bit map */
++#define VHT_MCS_CODE_TO_MCS_MAP(mcs_code) \
++	((mcs_code == VHT_CAP_MCS_MAP_0_7) ? VHT_CAP_MCS_0_7_RATEMAP : \
++	 (mcs_code == VHT_CAP_MCS_MAP_0_8) ? VHT_CAP_MCS_0_8_RATEMAP : \
++	 (mcs_code == VHT_CAP_MCS_MAP_0_9) ? VHT_CAP_MCS_0_9_RATEMAP : 0)
++
++#define VHT_PROP_MCS_CODE_TO_PROP_MCS_MAP(mcs_code) \
++	((mcs_code == VHT_PROP_MCS_MAP_10_11) ? VHT_PROP_MCS_10_11_RATEMAP : 0)
++
++/* Map the mcs bit map to mcs code */
++#define VHT_MCS_MAP_TO_MCS_CODE(mcs_map) \
++	((mcs_map == VHT_CAP_MCS_0_7_RATEMAP) ? VHT_CAP_MCS_MAP_0_7 : \
++	 (mcs_map == VHT_CAP_MCS_0_8_RATEMAP) ? VHT_CAP_MCS_MAP_0_8 : \
++	 (mcs_map == VHT_CAP_MCS_0_9_RATEMAP) ? VHT_CAP_MCS_MAP_0_9 : VHT_CAP_MCS_MAP_NONE)
++
++#define VHT_PROP_MCS_MAP_TO_PROP_MCS_CODE(mcs_map) \
++	(((mcs_map & 0xc00) == 0xc00)  ? VHT_PROP_MCS_MAP_10_11 : VHT_PROP_MCS_MAP_NONE)
++
++/** VHT Capabilities Supported Channel Width */
++typedef enum vht_cap_chan_width {
++	VHT_CAP_CHAN_WIDTH_SUPPORT_MANDATORY = 0x00,
++	VHT_CAP_CHAN_WIDTH_SUPPORT_160       = 0x04,
++	VHT_CAP_CHAN_WIDTH_SUPPORT_160_8080  = 0x08
++} vht_cap_chan_width_t;
++
++/** VHT Capabilities Supported max MPDU LEN (sec 8.4.2.160.2) */
++typedef enum vht_cap_max_mpdu_len {
++	VHT_CAP_MPDU_MAX_4K     = 0x00,
++	VHT_CAP_MPDU_MAX_8K     = 0x01,
++	VHT_CAP_MPDU_MAX_11K    = 0x02
++} vht_cap_max_mpdu_len_t;
++
++/* Maximum MPDU Length byte counts for the VHT Capabilities advertised limits */
++#define VHT_MPDU_LIMIT_4K        3895
++#define VHT_MPDU_LIMIT_8K        7991
++#define VHT_MPDU_LIMIT_11K      11454
++
++
++/**
++ * VHT Operation IE (sec 8.4.2.161)
++ */
++
++BWL_PRE_PACKED_STRUCT struct vht_op_ie {
++	uint8	chan_width;
++	uint8	chan1;
++	uint8	chan2;
++	uint16	supp_mcs;  /*  same def as above in vht cap */
++} BWL_POST_PACKED_STRUCT;
++typedef struct vht_op_ie vht_op_ie_t;
++
++/* 3B VHT Op info + 2B Basic MCS */
++#define VHT_OP_IE_LEN 5
++
++typedef enum vht_op_chan_width {
++	VHT_OP_CHAN_WIDTH_20_40	= 0,
++	VHT_OP_CHAN_WIDTH_80	= 1,
++	VHT_OP_CHAN_WIDTH_160	= 2, /* deprecated - IEEE 802.11 REVmc D8.0 Table 11-25 */
++	VHT_OP_CHAN_WIDTH_80_80	= 3  /* deprecated - IEEE 802.11 REVmc D8.0 Table 11-25 */
++} vht_op_chan_width_t;
++
++/* AID length */
++#define AID_IE_LEN		2
++/**
++ * BRCM vht features IE header
++ * The header if the fixed part of the IE
++ * On the 5GHz band this is the entire IE,
++ * on 2.4GHz the VHT IEs as defined in the 802.11ac
++ * specification follows
++ *
++ *
++ * VHT features rates  bitmap.
++ * Bit0:		5G MCS 0-9 BW 160MHz
++ * Bit1:		5G MCS 0-9 support BW 80MHz
++ * Bit2:		5G MCS 0-9 support BW 20MHz
++ * Bit3:		2.4G MCS 0-9 support BW 20MHz
++ * Bits:4-7	Reserved for future use
++ *
++ */
++#define VHT_FEATURES_IE_TYPE	0x4
++BWL_PRE_PACKED_STRUCT struct vht_features_ie_hdr {
++	uint8 oui[3];
++	uint8 type;		/* type of this IE = 4 */
++	uint8 rate_mask;	/* VHT rate mask */
++} BWL_POST_PACKED_STRUCT;
++typedef struct vht_features_ie_hdr vht_features_ie_hdr_t;
++
++/* Def for rx & tx basic mcs maps - ea ss num has 2 bits of info */
++#define VHT_MCS_MAP_GET_SS_IDX(nss) (((nss)-1) * VHT_CAP_MCS_MAP_S)
++#define VHT_MCS_MAP_GET_MCS_PER_SS(nss, mcsMap) \
++	(((mcsMap) >> VHT_MCS_MAP_GET_SS_IDX(nss)) & VHT_CAP_MCS_MAP_M)
++#define VHT_MCS_MAP_SET_MCS_PER_SS(nss, numMcs, mcsMap) \
++	do { \
++	 (mcsMap) &= (~(VHT_CAP_MCS_MAP_M << VHT_MCS_MAP_GET_SS_IDX(nss))); \
++	 (mcsMap) |= (((numMcs) & VHT_CAP_MCS_MAP_M) << VHT_MCS_MAP_GET_SS_IDX(nss)); \
++	} while (0)
++#define VHT_MCS_SS_SUPPORTED(nss, mcsMap) \
++		 (VHT_MCS_MAP_GET_MCS_PER_SS((nss), (mcsMap)) != VHT_CAP_MCS_MAP_NONE)
++
++/* Get the max ss supported from the mcs map */
++#define VHT_MAX_SS_SUPPORTED(mcsMap) \
++	VHT_MCS_SS_SUPPORTED(8, mcsMap) ? 8 : \
++	VHT_MCS_SS_SUPPORTED(7, mcsMap) ? 7 : \
++	VHT_MCS_SS_SUPPORTED(6, mcsMap) ? 6 : \
++	VHT_MCS_SS_SUPPORTED(5, mcsMap) ? 5 : \
++	VHT_MCS_SS_SUPPORTED(4, mcsMap) ? 4 : \
++	VHT_MCS_SS_SUPPORTED(3, mcsMap) ? 3 : \
++	VHT_MCS_SS_SUPPORTED(2, mcsMap) ? 2 : \
++	VHT_MCS_SS_SUPPORTED(1, mcsMap) ? 1 : 0
++
++/* ************* WPA definitions. ************* */
++#define WPA_OUI			"\x00\x50\xF2"	/* WPA OUI */
++#define WPA_OUI_LEN		3		/* WPA OUI length */
++#define WPA_OUI_TYPE		1
++#define WPA_VERSION		1		/* WPA version */
++#define WPA2_OUI		"\x00\x0F\xAC"	/* WPA2 OUI */
++#define WPA2_OUI_LEN		3		/* WPA2 OUI length */
++#define WPA2_VERSION		1		/* WPA2 version */
++#define WPA2_VERSION_LEN	2		/* WAP2 version length */
++
++/* ************* WPS definitions. ************* */
++#define WPS_OUI			"\x00\x50\xF2"	/* WPS OUI */
++#define WPS_OUI_LEN		3		/* WPS OUI length */
++#define WPS_OUI_TYPE		4
++
++/* ************* WFA definitions. ************* */
++#if defined(WL_LEGACY_P2P)
++#define MAC_OUI			"\x00\x17\xF2"	/* MACOSX OUI */
++#define MAC_OUI_TYPE_P2P	5
++#endif 
++
++#ifdef P2P_IE_OVRD
++#define WFA_OUI			MAC_OUI
++#else
++#define WFA_OUI			"\x50\x6F\x9A"	/* WFA OUI */
++#endif /* P2P_IE_OVRD */
++#define WFA_OUI_LEN		3		/* WFA OUI length */
++#ifdef P2P_IE_OVRD
++#define WFA_OUI_TYPE_P2P	MAC_OUI_TYPE_P2P
++#else
++#define WFA_OUI_TYPE_TPC	8
++#define WFA_OUI_TYPE_P2P	9
++#endif
++
++#define WFA_OUI_TYPE_TPC	8
++#ifdef WLTDLS
++#define WFA_OUI_TYPE_TPQ	4	/* WFD Tunneled Probe ReQuest */
++#define WFA_OUI_TYPE_TPS	5	/* WFD Tunneled Probe ReSponse */
++#define WFA_OUI_TYPE_WFD	10
++#endif /* WTDLS */
++#define WFA_OUI_TYPE_HS20	0x10
++#define WFA_OUI_TYPE_OSEN	0x12
++#define WFA_OUI_TYPE_NAN	0x13
++#define WFA_OUI_TYPE_MBO	0x16
++#define WFA_OUI_TYPE_MBO_OCE	0x16
++
++/* RSN authenticated key managment suite */
++#define RSN_AKM_NONE		0	/* None (IBSS) */
++#define RSN_AKM_UNSPECIFIED	1	/* Over 802.1x */
++#define RSN_AKM_PSK		2	/* Pre-shared Key */
++#define RSN_AKM_FBT_1X		3	/* Fast Bss transition using 802.1X */
++#define RSN_AKM_FBT_PSK		4	/* Fast Bss transition using Pre-shared Key */
++/* RSN_AKM_MFP_1X and RSN_AKM_MFP_PSK are not used any more
++ * Just kept here to avoid build issue in BISON/CARIBOU branch
++ */
++#define RSN_AKM_MFP_1X		5	/* SHA256 key derivation, using 802.1X */
++#define RSN_AKM_MFP_PSK		6	/* SHA256 key derivation, using Pre-shared Key */
++#define RSN_AKM_SHA256_1X	5	/* SHA256 key derivation, using 802.1X */
++#define RSN_AKM_SHA256_PSK	6	/* SHA256 key derivation, using Pre-shared Key */
++#define RSN_AKM_TPK		7	/* TPK(TDLS Peer Key) handshake */
++#define RSN_AKM_SAE_PSK         8       /* AKM for SAE with 4-way handshake */
++#define RSN_AKM_SAE_FBT         9       /* AKM for SAE with FBT */
++#define RSN_AKM_FILS_SHA256	14	/* SHA256 key derivation, using FILS */
++#define RSN_AKM_FILS_SHA384	15	/* SHA384 key derivation, using FILS */
++
++/* OSEN authenticated key managment suite */
++#define OSEN_AKM_UNSPECIFIED	RSN_AKM_UNSPECIFIED	/* Over 802.1x */
++
++/* Key related defines */
++#define DOT11_MAX_DEFAULT_KEYS	4	/* number of default keys */
++#define DOT11_MAX_IGTK_KEYS		2
++#define DOT11_MAX_KEY_SIZE	32	/* max size of any key */
++#define DOT11_MAX_IV_SIZE	16	/* max size of any IV */
++#define DOT11_EXT_IV_FLAG	(1<<5)	/* flag to indicate IV is > 4 bytes */
++#define DOT11_WPA_KEY_RSC_LEN   8       /* WPA RSC key len */
++
++#define WEP1_KEY_SIZE		5	/* max size of any WEP key */
++#define WEP1_KEY_HEX_SIZE	10	/* size of WEP key in hex. */
++#define WEP128_KEY_SIZE		13	/* max size of any WEP key */
++#define WEP128_KEY_HEX_SIZE	26	/* size of WEP key in hex. */
++#define TKIP_MIC_SIZE		8	/* size of TKIP MIC */
++#define TKIP_EOM_SIZE		7	/* max size of TKIP EOM */
++#define TKIP_EOM_FLAG		0x5a	/* TKIP EOM flag byte */
++#define TKIP_KEY_SIZE		32	/* size of any TKIP key, includs MIC keys */
++#define TKIP_TK_SIZE		16
++#define TKIP_MIC_KEY_SIZE	8
++#define TKIP_MIC_AUTH_TX	16	/* offset to Authenticator MIC TX key */
++#define TKIP_MIC_AUTH_RX	24	/* offset to Authenticator MIC RX key */
++#define TKIP_MIC_SUP_RX		TKIP_MIC_AUTH_TX	/* offset to Supplicant MIC RX key */
++#define TKIP_MIC_SUP_TX		TKIP_MIC_AUTH_RX	/* offset to Supplicant MIC TX key */
++#define AES_KEY_SIZE		16	/* size of AES key */
++#define AES_MIC_SIZE		8	/* size of AES MIC */
++#define BIP_KEY_SIZE		16	/* size of BIP key */
++#define BIP_MIC_SIZE		8   /* sizeof BIP MIC */
++
++#define AES_GCM_MIC_SIZE	16	/* size of MIC for 128-bit GCM - .11adD9 */
++
++#define AES256_KEY_SIZE		32	/* size of AES 256 key - .11acD5 */
++#define AES256_MIC_SIZE		16	/* size of MIC for 256 bit keys, incl BIP */
++
++/* WCN */
++#define WCN_OUI			"\x00\x50\xf2"	/* WCN OUI */
++#define WCN_TYPE		4	/* WCN type */
++
++#ifdef BCMWAPI_WPI
++#define SMS4_KEY_LEN        16
++#define SMS4_WPI_CBC_MAC_LEN    16
++#endif
++
++/* 802.11r protocol definitions */
++
++/** Mobility Domain IE */
++BWL_PRE_PACKED_STRUCT struct dot11_mdid_ie {
++	uint8 id;
++	uint8 len;
++	uint16 mdid;		/* Mobility Domain Id */
++	uint8 cap;
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_mdid_ie dot11_mdid_ie_t;
++
++#define FBT_MDID_CAP_OVERDS	0x01	/* Fast Bss transition over the DS support */
++#define FBT_MDID_CAP_RRP	0x02	/* Resource request protocol support */
++
++/** Fast Bss Transition IE */
++BWL_PRE_PACKED_STRUCT struct dot11_ft_ie {
++	uint8 id;
++	uint8 len;
++	uint16 mic_control;		/* Mic Control */
++	uint8 mic[16];
++	uint8 anonce[32];
++	uint8 snonce[32];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_ft_ie dot11_ft_ie_t;
++
++#define TIE_TYPE_RESERVED		0
++#define TIE_TYPE_REASSOC_DEADLINE	1
++#define TIE_TYPE_KEY_LIEFTIME		2
++#define TIE_TYPE_ASSOC_COMEBACK		3
++BWL_PRE_PACKED_STRUCT struct dot11_timeout_ie {
++	uint8 id;
++	uint8 len;
++	uint8 type;		/* timeout interval type */
++	uint32 value;		/* timeout interval value */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_timeout_ie dot11_timeout_ie_t;
++
++/** GTK ie */
++BWL_PRE_PACKED_STRUCT struct dot11_gtk_ie {
++	uint8 id;
++	uint8 len;
++	uint16 key_info;
++	uint8 key_len;
++	uint8 rsc[8];
++	uint8 data[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_gtk_ie dot11_gtk_ie_t;
++
++/** Management MIC ie */
++BWL_PRE_PACKED_STRUCT struct mmic_ie {
++	uint8   id;					/* IE ID: DOT11_MNG_MMIE_ID */
++	uint8   len;				/* IE length */
++	uint16  key_id;				/* key id */
++	uint8   ipn[6];				/* ipn */
++	uint8   mic[16];			/* mic */
++} BWL_POST_PACKED_STRUCT;
++typedef struct mmic_ie mmic_ie_t;
++
++/* 802.11r-2008, 11A.10.3 - RRB frame format */
++BWL_PRE_PACKED_STRUCT struct dot11_ft_rrb_frame {
++	uint8  frame_type; /* 1 for RRB */
++	uint8  packet_type; /* 0 for Request 1 for Response */
++	uint16 len;
++	uint8  cur_ap_addr[ETHER_ADDR_LEN];
++	uint8  data[1];	/* IEs Received/Sent in FT Action Req/Resp Frame */
++} BWL_POST_PACKED_STRUCT;
++
++typedef struct dot11_ft_rrb_frame dot11_ft_rrb_frame_t;
++
++#define DOT11_FT_RRB_FIXED_LEN 10
++#define DOT11_FT_REMOTE_FRAME_TYPE 1
++#define DOT11_FT_PACKET_REQ 0
++#define DOT11_FT_PACKET_RESP 1
++
++#define BSSID_INVALID           "\x00\x00\x00\x00\x00\x00"
++#define BSSID_BROADCAST         "\xFF\xFF\xFF\xFF\xFF\xFF"
++
++#ifdef BCMWAPI_WAI
++#define WAPI_IE_MIN_LEN 	20	/* WAPI IE min length */
++#define WAPI_VERSION		1	/* WAPI version */
++#define WAPI_VERSION_LEN	2	/* WAPI version length */
++#define WAPI_OUI		"\x00\x14\x72"	/* WAPI OUI */
++#define WAPI_OUI_LEN		DOT11_OUI_LEN	/* WAPI OUI length */
++#endif /* BCMWAPI_WAI */
++
++/* ************* WMM Parameter definitions. ************* */
++#define WMM_OUI			"\x00\x50\xF2"	/* WNN OUI */
++#define WMM_OUI_LEN		3		/* WMM OUI length */
++#define WMM_OUI_TYPE	2		/* WMM OUT type */
++#define WMM_VERSION		1
++#define WMM_VERSION_LEN	1
++
++/* WMM OUI subtype */
++#define WMM_OUI_SUBTYPE_PARAMETER	1
++#define WMM_PARAMETER_IE_LEN		24
++
++/** Link Identifier Element */
++BWL_PRE_PACKED_STRUCT struct link_id_ie {
++	uint8 id;
++	uint8 len;
++	struct ether_addr	bssid;
++	struct ether_addr	tdls_init_mac;
++	struct ether_addr	tdls_resp_mac;
++} BWL_POST_PACKED_STRUCT;
++typedef struct link_id_ie link_id_ie_t;
++#define TDLS_LINK_ID_IE_LEN		18
++
++/** Link Wakeup Schedule Element */
++BWL_PRE_PACKED_STRUCT struct wakeup_sch_ie {
++	uint8 id;
++	uint8 len;
++	uint32 offset;			/* in ms between TSF0 and start of 1st Awake Window */
++	uint32 interval;		/* in ms bwtween the start of 2 Awake Windows */
++	uint32 awake_win_slots;	/* in backof slots, duration of Awake Window */
++	uint32 max_wake_win;	/* in ms, max duration of Awake Window */
++	uint16 idle_cnt;		/* number of consecutive Awake Windows */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wakeup_sch_ie wakeup_sch_ie_t;
++#define TDLS_WAKEUP_SCH_IE_LEN		18
++
++/** Channel Switch Timing Element */
++BWL_PRE_PACKED_STRUCT struct channel_switch_timing_ie {
++	uint8 id;
++	uint8 len;
++	uint16 switch_time;		/* in ms, time to switch channels */
++	uint16 switch_timeout;	/* in ms */
++} BWL_POST_PACKED_STRUCT;
++typedef struct channel_switch_timing_ie channel_switch_timing_ie_t;
++#define TDLS_CHANNEL_SWITCH_TIMING_IE_LEN		4
++
++/** PTI Control Element */
++BWL_PRE_PACKED_STRUCT struct pti_control_ie {
++	uint8 id;
++	uint8 len;
++	uint8 tid;
++	uint16 seq_control;
++} BWL_POST_PACKED_STRUCT;
++typedef struct pti_control_ie pti_control_ie_t;
++#define TDLS_PTI_CONTROL_IE_LEN		3
++
++/** PU Buffer Status Element */
++BWL_PRE_PACKED_STRUCT struct pu_buffer_status_ie {
++	uint8 id;
++	uint8 len;
++	uint8 status;
++} BWL_POST_PACKED_STRUCT;
++typedef struct pu_buffer_status_ie pu_buffer_status_ie_t;
++#define TDLS_PU_BUFFER_STATUS_IE_LEN	1
++#define TDLS_PU_BUFFER_STATUS_AC_BK		1
++#define TDLS_PU_BUFFER_STATUS_AC_BE		2
++#define TDLS_PU_BUFFER_STATUS_AC_VI		4
++#define TDLS_PU_BUFFER_STATUS_AC_VO		8
++
++/* TDLS Action Field Values */
++#define TDLS_SETUP_REQ				0
++#define TDLS_SETUP_RESP				1
++#define TDLS_SETUP_CONFIRM			2
++#define TDLS_TEARDOWN				3
++#define TDLS_PEER_TRAFFIC_IND			4
++#define TDLS_CHANNEL_SWITCH_REQ			5
++#define TDLS_CHANNEL_SWITCH_RESP		6
++#define TDLS_PEER_PSM_REQ			7
++#define TDLS_PEER_PSM_RESP			8
++#define TDLS_PEER_TRAFFIC_RESP			9
++#define TDLS_DISCOVERY_REQ			10
++
++/* 802.11z TDLS Public Action Frame action field */
++#define TDLS_DISCOVERY_RESP			14
++
++/* 802.11u GAS action frames */
++#define GAS_REQUEST_ACTION_FRAME				10
++#define GAS_RESPONSE_ACTION_FRAME				11
++#define GAS_COMEBACK_REQUEST_ACTION_FRAME		12
++#define GAS_COMEBACK_RESPONSE_ACTION_FRAME		13
++
++/* FTM - fine timing measurement public action frames */
++BWL_PRE_PACKED_STRUCT struct dot11_ftm_req {
++	uint8 category;				/* category of action frame (4) */
++	uint8 action;				/* public action (32) */
++	uint8 trigger;				/* trigger/continue? */
++	/* optional lci, civic loc, ftm params */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_ftm_req dot11_ftm_req_t;
++
++BWL_PRE_PACKED_STRUCT struct dot11_ftm {
++	uint8 category;				/* category of action frame (4) */
++	uint8 action;				/* public action (33) */
++	uint8 dialog;				/* dialog token */
++	uint8 follow_up;			/* follow up dialog token */
++	uint8 tod[6];				/* t1 - last depart timestamp */
++	uint8 toa[6];				/* t4 - last ack arrival timestamp */
++	uint8 tod_err[2];			/* t1 error */
++	uint8 toa_err[2];			/* t4 error */
++	/* optional lci report, civic loc report, ftm params */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_ftm dot11_ftm_t;
++
++
++#define DOT11_FTM_ERR_NOT_CONT_OFFSET 1
++#define DOT11_FTM_ERR_NOT_CONT_MASK 0x80
++#define DOT11_FTM_ERR_NOT_CONT_SHIFT 7
++#define DOT11_FTM_ERR_NOT_CONT(_err) (((_err)[DOT11_FTM_ERR_NOT_CONT_OFFSET] & \
++	DOT11_FTM_ERR_NOT_CONT_MASK) >> DOT11_FTM_ERR_NOT_CONT_SHIFT)
++#define DOT11_FTM_ERR_SET_NOT_CONT(_err, _val) do {\
++	uint8 _err2 = (_err)[DOT11_FTM_ERR_NOT_CONT_OFFSET]; \
++	_err2 &= ~DOT11_FTM_ERR_NOT_CONT_MASK; \
++	_err2 |= ((_val) << DOT11_FTM_ERR_NOT_CONT_SHIFT) & DOT11_FTM_ERR_NOT_CONT_MASK; \
++	(_err)[DOT11_FTM_ERR_NOT_CONT_OFFSET] = _err2; \
++} while (0)
++
++#define DOT11_FTM_ERR_MAX_ERR_OFFSET 0
++#define DOT11_FTM_ERR_MAX_ERR_MASK 0x7fff
++#define DOT11_FTM_ERR_MAX_ERR_SHIFT 0
++#define DOT11_FTM_ERR_MAX_ERR(_err) (((((_err)[1] & 0x7f) << 8) | (_err)[0]))
++#define DOT11_FTM_ERR_SET_MAX_ERR(_err, _val) do {\
++	uint16 _val2; \
++	uint16 _not_cont; \
++	_val2 =  (((_val) & DOT11_FTM_ERR_MAX_ERR_MASK) << DOT11_FTM_ERR_MAX_ERR_SHIFT); \
++	_val2 = (_val2 > 0x3fff) ? 0 : _val2; /* not expecting > 16ns error */ \
++	_not_cont = DOT11_FTM_ERR_NOT_CONT(_err); \
++	(_err)[0] = _val2 & 0xff; \
++	(_err)[1] = (_val2 >> 8) & 0xff; \
++	DOT11_FTM_ERR_SET_NOT_CONT(_err, _not_cont); \
++} while (0)
++
++#if defined(DOT11_FTM_ERR_ROM_COMPAT)
++/* incorrect defs - here for ROM compatibiity */
++#undef DOT11_FTM_ERR_NOT_CONT_OFFSET
++#undef DOT11_FTM_ERR_NOT_CONT_MASK
++#undef DOT11_FTM_ERR_NOT_CONT_SHIFT
++#undef DOT11_FTM_ERR_NOT_CONT
++#undef DOT11_FTM_ERR_SET_NOT_CONT
++
++#define DOT11_FTM_ERR_NOT_CONT_OFFSET 0
++#define DOT11_FTM_ERR_NOT_CONT_MASK 0x0001
++#define DOT11_FTM_ERR_NOT_CONT_SHIFT 0
++#define DOT11_FTM_ERR_NOT_CONT(_err) (((_err)[DOT11_FTM_ERR_NOT_CONT_OFFSET] & \
++	DOT11_FTM_ERR_NOT_CONT_MASK) >> DOT11_FTM_ERR_NOT_CONT_SHIFT)
++#define DOT11_FTM_ERR_SET_NOT_CONT(_err, _val) do {\
++	uint8 _err2 = (_err)[DOT11_FTM_ERR_NOT_CONT_OFFSET]; \
++	_err2 &= ~DOT11_FTM_ERR_NOT_CONT_MASK; \
++	_err2 |= ((_val) << DOT11_FTM_ERR_NOT_CONT_SHIFT) & DOT11_FTM_ERR_NOT_CONT_MASK; \
++	(_err)[DOT11_FTM_ERR_NOT_CONT_OFFSET] = _err2; \
++} while (0)
++
++#undef DOT11_FTM_ERR_MAX_ERR_OFFSET
++#undef DOT11_FTM_ERR_MAX_ERR_MASK
++#undef DOT11_FTM_ERR_MAX_ERR_SHIFT
++#undef DOT11_FTM_ERR_MAX_ERR
++#undef DOT11_FTM_ERR_SET_MAX_ERR
++
++#define DOT11_FTM_ERR_MAX_ERR_OFFSET 0
++#define DOT11_FTM_ERR_MAX_ERR_MASK 0xfff7
++#define DOT11_FTM_ERR_MAX_ERR_SHIFT 1
++#define DOT11_FTM_ERR_MAX_ERR(_err) ((((_err)[1] << 7) | (_err)[0]) >> 1)
++#define DOT11_FTM_ERR_SET_MAX_ERR(_err, _val) do {\
++	uint16 _val2; \
++	_val2 =  (((_val) << DOT11_FTM_ERR_MAX_ERR_SHIFT) |\
++		 ((_err)[DOT11_FTM_ERR_NOT_CONT_OFFSET] & DOT11_FTM_ERR_NOT_CONT_MASK)); \
++	(_err)[0] = _val2 & 0xff; \
++	(_err)[1] = _val2 >> 8 & 0xff; \
++} while (0)
++#endif /* DOT11_FTM_ERR_ROM_COMPAT */
++
++BWL_PRE_PACKED_STRUCT struct dot11_ftm_params {
++	uint8 id;		/* DOT11_MNG_FTM_PARAM_ID 8.4.2.166 11mcd2.6/2014 - revisit */
++	uint8 len;
++	uint8 info[9];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_ftm_params dot11_ftm_params_t;
++#define DOT11_FTM_PARAMS_IE_LEN (sizeof(dot11_ftm_params_t) - 2)
++
++#define FTM_PARAMS_FIELD(_p, _off, _mask, _shift) (((_p)->info[(_off)] & (_mask)) >> (_shift))
++#define FTM_PARAMS_SET_FIELD(_p, _off, _mask, _shift, _val) do {\
++	uint8 _ptmp = (_p)->info[_off] & ~(_mask); \
++	(_p)->info[(_off)] = _ptmp | (((_val) << (_shift)) & (_mask)); \
++} while (0)
++
++#define FTM_PARAMS_STATUS_OFFSET 0
++#define FTM_PARAMS_STATUS_MASK 0x03
++#define FTM_PARAMS_STATUS_SHIFT 0
++#define FTM_PARAMS_STATUS(_p) FTM_PARAMS_FIELD(_p, FTM_PARAMS_STATUS_OFFSET, \
++	FTM_PARAMS_STATUS_MASK, FTM_PARAMS_STATUS_SHIFT)
++#define FTM_PARAMS_SET_STATUS(_p, _status) FTM_PARAMS_SET_FIELD(_p, \
++	FTM_PARAMS_STATUS_OFFSET, FTM_PARAMS_STATUS_MASK, FTM_PARAMS_STATUS_SHIFT, _status)
++
++#define FTM_PARAMS_VALUE_OFFSET 0
++#define FTM_PARAMS_VALUE_MASK 0x7c
++#define FTM_PARAMS_VALUE_SHIFT 2
++#define FTM_PARAMS_VALUE(_p) FTM_PARAMS_FIELD(_p, FTM_PARAMS_VALUE_OFFSET, \
++	FTM_PARAMS_VALUE_MASK, FTM_PARAMS_VALUE_SHIFT)
++#define FTM_PARAMS_SET_VALUE(_p, _value) FTM_PARAMS_SET_FIELD(_p, \
++	FTM_PARAMS_VALUE_OFFSET, FTM_PARAMS_VALUE_MASK, FTM_PARAMS_VALUE_SHIFT, _value)
++#define FTM_PARAMS_MAX_VALUE 32
++
++#define FTM_PARAMS_NBURSTEXP_OFFSET 1
++#define FTM_PARAMS_NBURSTEXP_MASK 0x0f
++#define FTM_PARAMS_NBURSTEXP_SHIFT 0
++#define FTM_PARAMS_NBURSTEXP(_p) FTM_PARAMS_FIELD(_p, FTM_PARAMS_NBURSTEXP_OFFSET, \
++	FTM_PARAMS_NBURSTEXP_MASK, FTM_PARAMS_NBURSTEXP_SHIFT)
++#define FTM_PARAMS_SET_NBURSTEXP(_p, _bexp) FTM_PARAMS_SET_FIELD(_p, \
++	FTM_PARAMS_NBURSTEXP_OFFSET, FTM_PARAMS_NBURSTEXP_MASK, FTM_PARAMS_NBURSTEXP_SHIFT, \
++	_bexp)
++
++#define FTM_PARAMS_NBURST(_p) (1 << FTM_PARAMS_NBURSTEXP(_p))
++
++enum {
++	FTM_PARAMS_NBURSTEXP_NOPREF = 15
++};
++
++enum {
++	FTM_PARAMS_BURSTTMO_NOPREF = 15
++};
++
++#define FTM_PARAMS_BURSTTMO_OFFSET 1
++#define FTM_PARAMS_BURSTTMO_MASK 0xf0
++#define FTM_PARAMS_BURSTTMO_SHIFT 4
++#define FTM_PARAMS_BURSTTMO(_p) FTM_PARAMS_FIELD(_p, FTM_PARAMS_BURSTTMO_OFFSET, \
++	FTM_PARAMS_BURSTTMO_MASK, FTM_PARAMS_BURSTTMO_SHIFT)
++/* set timeout in params using _tmo where timeout = 2^(_tmo) * 250us */
++#define FTM_PARAMS_SET_BURSTTMO(_p, _tmo) FTM_PARAMS_SET_FIELD(_p, \
++	FTM_PARAMS_BURSTTMO_OFFSET, FTM_PARAMS_BURSTTMO_MASK, FTM_PARAMS_BURSTTMO_SHIFT, (_tmo)+2)
++
++#define FTM_PARAMS_BURSTTMO_USEC(_val) ((1 << ((_val)-2)) * 250)
++#define FTM_PARAMS_BURSTTMO_VALID(_val) ((((_val) < 12 && (_val) > 1)) || \
++	(_val) == FTM_PARAMS_BURSTTMO_NOPREF)
++#define FTM_PARAMS_BURSTTMO_MAX_MSEC 128 /* 2^9 * 250us */
++#define FTM_PARAMS_BURSTTMO_MAX_USEC 128000 /* 2^9 * 250us */
++
++#define FTM_PARAMS_MINDELTA_OFFSET 2
++#define FTM_PARAMS_MINDELTA_USEC(_p) ((_p)->info[FTM_PARAMS_MINDELTA_OFFSET] * 100)
++#define FTM_PARAMS_SET_MINDELTA_USEC(_p, _delta) do { \
++	(_p)->info[FTM_PARAMS_MINDELTA_OFFSET] = (_delta) / 100; \
++} while (0)
++
++enum {
++	FTM_PARAMS_MINDELTA_NOPREF = 0
++};
++
++#define FTM_PARAMS_PARTIAL_TSF(_p) ((_p)->info[4] << 8 | (_p)->info[3])
++#define FTM_PARAMS_SET_PARTIAL_TSF(_p, _partial_tsf) do { \
++	(_p)->info[3] = (_partial_tsf) & 0xff; \
++	(_p)->info[4] = ((_partial_tsf) >> 8) & 0xff; \
++} while (0)
++
++#define FTM_PARAMS_PARTIAL_TSF_MASK 0x0000000003fffc00ULL
++#define FTM_PARAMS_PARTIAL_TSF_SHIFT 10
++#define FTM_PARAMS_PARTIAL_TSF_BIT_LEN 16
++#define FTM_PARAMS_PARTIAL_TSF_MAX 0xffff
++
++/* FTM can indicate upto 62k TUs forward and 1k TU backward */
++#define FTM_PARAMS_TSF_FW_HI (63487 << 10)	/* in micro sec */
++#define FTM_PARAMS_TSF_BW_LOW (64512 << 10)	/* in micro sec */
++#define FTM_PARAMS_TSF_BW_HI (65535 << 10)	/* in micro sec */
++#define FTM_PARAMS_TSF_FW_MAX FTM_PARAMS_TSF_FW_HI
++#define FTM_PARAMS_TSF_BW_MAX (FTM_PARAMS_TSF_BW_HI - FTM_PARAMS_TSF_BW_LOW)
++
++#define FTM_PARAMS_PTSFNOPREF_OFFSET 5
++#define FTM_PARAMS_PTSFNOPREF_MASK 0x1
++#define FTM_PARAMS_PTSFNOPREF_SHIFT 0
++#define FTM_PARAMS_PTSFNOPREF(_p) FTM_PARAMS_FIELD(_p, FTM_PARAMS_PTSFNOPREF_OFFSET, \
++	FTM_PARAMS_PTSFNOPREF_MASK, FTM_PARAMS_PTSFNOPREF_SHIFT)
++#define FTM_PARAMS_SET_PTSFNOPREF(_p, _nopref) FTM_PARAMS_SET_FIELD(_p, \
++	FTM_PARAMS_PTSFNOPREF_OFFSET, FTM_PARAMS_PTSFNOPREF_MASK, \
++	FTM_PARAMS_PTSFNOPREF_SHIFT, _nopref)
++
++#define FTM_PARAMS_ASAP_OFFSET 5
++#define FTM_PARAMS_ASAP_MASK 0x4
++#define FTM_PARAMS_ASAP_SHIFT 2
++#define FTM_PARAMS_ASAP(_p) FTM_PARAMS_FIELD(_p, FTM_PARAMS_ASAP_OFFSET, \
++	FTM_PARAMS_ASAP_MASK, FTM_PARAMS_ASAP_SHIFT)
++#define FTM_PARAMS_SET_ASAP(_p, _asap) FTM_PARAMS_SET_FIELD(_p, \
++	FTM_PARAMS_ASAP_OFFSET, FTM_PARAMS_ASAP_MASK, FTM_PARAMS_ASAP_SHIFT, _asap)
++
++/* FTM1 - AKA ASAP Capable */
++#define FTM_PARAMS_FTM1_OFFSET 5
++#define FTM_PARAMS_FTM1_MASK 0x02
++#define FTM_PARAMS_FTM1_SHIFT 1
++#define FTM_PARAMS_FTM1(_p) FTM_PARAMS_FIELD(_p, FTM_PARAMS_FTM1_OFFSET, \
++	FTM_PARAMS_FTM1_MASK, FTM_PARAMS_FTM1_SHIFT)
++#define FTM_PARAMS_SET_FTM1(_p, _ftm1) FTM_PARAMS_SET_FIELD(_p, \
++	FTM_PARAMS_FTM1_OFFSET, FTM_PARAMS_FTM1_MASK, FTM_PARAMS_FTM1_SHIFT, _ftm1)
++
++#define FTM_PARAMS_FTMS_PER_BURST_OFFSET 5
++#define FTM_PARAMS_FTMS_PER_BURST_MASK 0xf8
++#define FTM_PARAMS_FTMS_PER_BURST_SHIFT 3
++#define FTM_PARAMS_FTMS_PER_BURST(_p) FTM_PARAMS_FIELD(_p, FTM_PARAMS_FTMS_PER_BURST_OFFSET, \
++	FTM_PARAMS_FTMS_PER_BURST_MASK, FTM_PARAMS_FTMS_PER_BURST_SHIFT)
++#define FTM_PARAMS_SET_FTMS_PER_BURST(_p, _nftms) FTM_PARAMS_SET_FIELD(_p, \
++	FTM_PARAMS_FTMS_PER_BURST_OFFSET, FTM_PARAMS_FTMS_PER_BURST_MASK, \
++	FTM_PARAMS_FTMS_PER_BURST_SHIFT, _nftms)
++
++enum {
++	FTM_PARAMS_FTMS_PER_BURST_NOPREF = 0
++};
++
++#define FTM_PARAMS_CHAN_INFO_OFFSET 6
++#define FTM_PARAMS_CHAN_INFO_MASK 0xfc
++#define FTM_PARAMS_CHAN_INFO_SHIFT 2
++#define FTM_PARAMS_CHAN_INFO(_p) FTM_PARAMS_FIELD(_p, FTM_PARAMS_CHAN_INFO_OFFSET, \
++	FTM_PARAMS_CHAN_INFO_MASK, FTM_PARAMS_CHAN_INFO_SHIFT)
++#define FTM_PARAMS_SET_CHAN_INFO(_p, _ci) FTM_PARAMS_SET_FIELD(_p, \
++	FTM_PARAMS_CHAN_INFO_OFFSET, FTM_PARAMS_CHAN_INFO_MASK, FTM_PARAMS_CHAN_INFO_SHIFT, _ci)
++
++/* burst period - units of 100ms */
++#define FTM_PARAMS_BURST_PERIOD(_p) (((_p)->info[8] << 8) | (_p)->info[7])
++#define FTM_PARAMS_SET_BURST_PERIOD(_p, _bp) do {\
++	(_p)->info[7] = (_bp) & 0xff; \
++	(_p)->info[8] = ((_bp) >> 8) & 0xff; \
++} while (0)
++
++#define FTM_PARAMS_BURST_PERIOD_MS(_p) (FTM_PARAMS_BURST_PERIOD(_p) * 100)
++
++enum {
++	FTM_PARAMS_BURST_PERIOD_NOPREF = 0
++};
++
++/* FTM status values - last updated from 11mcD4.0 */
++enum {
++	FTM_PARAMS_STATUS_RESERVED	= 0,
++	FTM_PARAMS_STATUS_SUCCESSFUL = 1,
++	FTM_PARAMS_STATUS_INCAPABLE = 2,
++	FTM_PARAMS_STATUS_FAILED = 3,
++	/* Below are obsolte */
++	FTM_PARAMS_STATUS_OVERRIDDEN = 4,
++	FTM_PARAMS_STATUS_ASAP_INCAPABLE = 5,
++	FTM_PARAMS_STATUS_ASAP_FAILED = 6,
++	/* rest are reserved */
++};
++
++enum {
++	FTM_PARAMS_CHAN_INFO_NO_PREF 		= 0,
++	FTM_PARAMS_CHAN_INFO_RESERVE1 		= 1,
++	FTM_PARAMS_CHAN_INFO_RESERVE2 		= 2,
++	FTM_PARAMS_CHAN_INFO_RESERVE3 		= 3,
++	FTM_PARAMS_CHAN_INFO_NON_HT_5 		= 4,
++	FTM_PARAMS_CHAN_INFO_RESERVE5		= 5,
++	FTM_PARAMS_CHAN_INFO_NON_HT_10 		= 6,
++	FTM_PARAMS_CHAN_INFO_RESERVE7		= 7,
++	FTM_PARAMS_CHAN_INFO_NON_HT_20 		= 8, /* excludes 2.4G, and High rate DSSS */
++	FTM_PARAMS_CHAN_INFO_HT_MF_20 		= 9,
++	FTM_PARAMS_CHAN_INFO_VHT_20 		= 10,
++	FTM_PARAMS_CHAN_INFO_HT_MF_40 		= 11,
++	FTM_PARAMS_CHAN_INFO_VHT_40 		= 12,
++	FTM_PARAMS_CHAN_INFO_VHT_80 		= 13,
++	FTM_PARAMS_CHAN_INFO_VHT_80_80 		= 14,
++	FTM_PARAMS_CHAN_INFO_VHT_160_2_RFLOS 	= 15,
++	FTM_PARAMS_CHAN_INFO_VHT_160		= 16,
++	/* Reserved from 17 - 30 */
++	FTM_PARAMS_CHAN_INFO_DMG_2160 		= 31,
++	/* Reserved from 32 - 63 */
++	FTM_PARAMS_CHAN_INFO_MAX		= 63
++};
++
++/* tag_ID/length/value_buffer tuple */
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint8	id;
++	uint8	len;
++	uint8	data[1];
++} BWL_POST_PACKED_STRUCT ftm_vs_tlv_t;
++
++BWL_PRE_PACKED_STRUCT struct dot11_ftm_vs_ie {
++	uint8 id;						/* DOT11_MNG_VS_ID */
++	uint8 len;						/* length following */
++	uint8 oui[3];					/* BRCM_PROP_OUI (or Customer) */
++	uint8 sub_type;					/* BRCM_FTM_IE_TYPE (or Customer) */
++	uint8 version;
++	ftm_vs_tlv_t	tlvs[1];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_ftm_vs_ie dot11_ftm_vs_ie_t;
++
++/* ftm vs api version */
++#define BCM_FTM_VS_PARAMS_VERSION 0x01
++
++/* ftm vendor specific information tlv types */
++enum {
++	FTM_VS_TLV_NONE = 0,
++	FTM_VS_TLV_REQ_PARAMS = 1,		/* additional request params (in FTM_REQ) */
++	FTM_VS_TLV_MEAS_INFO = 2,		/* measurement information (in FTM_MEAS) */
++	FTM_VS_TLV_SEC_PARAMS = 3,		/* security parameters (in either) */
++	FTM_VS_TLV_SEQ_PARAMS = 4,		/* toast parameters (FTM_REQ, BRCM proprietary) */
++	FTM_VS_TLV_MF_BUF = 5,			/* multi frame buffer - may span ftm vs ie's */
++	FTM_VS_TLV_TIMING_PARAMS = 6            /* timing adjustments */
++	/* add additional types above */
++};
++
++/* the following definitions are *DEPRECATED* and moved to implemenetion files. They
++ * are retained here because previous (May 2016) some branches use them
++ */
++#define FTM_TPK_LEN            16
++#define FTM_RI_RR_BUF_LEN      32
++#define FTM_TPK_RI_RR_LEN      13
++#define FTM_TPK_RI_RR_LEN_SECURE_2_0    28
++#define FTM_TPK_DIGEST_LEN     32
++#define FTM_TPK_BUFFER_LEN     128
++#define FTM_TPK_RI_PHY_LEN     7
++#define FTM_TPK_RR_PHY_LEN     7
++#define FTM_TPK_DATA_BUFFER_LEN 88
++#define FTM_TPK_LEN_SECURE_2_0          32
++#define FTM_TPK_RI_PHY_LEN_SECURE_2_0  14
++#define FTM_TPK_RR_PHY_LEN_SECURE_2_0  14
++
++
++BWL_PRE_PACKED_STRUCT struct dot11_ftm_vs_params {
++	uint8 id;                       /* DOT11_MNG_VS_ID */
++	uint8 len;
++	uint8 oui[3];                   /* Proprietary OUI, BRCM_PROP_OUI */
++	uint8 bcm_vs_id;
++	ftm_vs_tlv_t ftm_tpk_ri_rr[1];          /* ftm_TPK_ri_rr place holder */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_ftm_vs_params dot11_ftm_vs_tpk_ri_rr_params_t;
++#define DOT11_FTM_VS_LEN  (sizeof(dot11_ftm_vs_tpk_ri_rr_params_t) - TLV_HDR_LEN)
++/* end *DEPRECATED* ftm definitions */
++
++BWL_PRE_PACKED_STRUCT struct dot11_ftm_sync_info {
++	uint8 id;		/* Extended - 255 11mc D4.3  */
++	uint8 len;
++	uint8 id_ext;
++	uint8 tsf_sync_info[4];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_ftm_sync_info dot11_ftm_sync_info_t;
++
++/* ftm tsf sync info ie len - includes id ext */
++#define DOT11_FTM_SYNC_INFO_IE_LEN (sizeof(dot11_ftm_sync_info_t) - TLV_HDR_LEN)
++
++#define DOT11_FTM_IS_SYNC_INFO_IE(_ie) (\
++	DOT11_MNG_IE_ID_EXT_MATCH(_ie, DOT11_MNG_FTM_SYNC_INFO) && \
++	(_ie)->len == DOT11_FTM_SYNC_INFO_IE_LEN)
++
++/* 802.11u interworking access network options */
++#define IW_ANT_MASK					0x0f
++#define IW_INTERNET_MASK				0x10
++#define IW_ASRA_MASK					0x20
++#define IW_ESR_MASK					0x40
++#define IW_UESA_MASK					0x80
++
++/* 802.11u interworking access network type */
++#define IW_ANT_PRIVATE_NETWORK				0
++#define IW_ANT_PRIVATE_NETWORK_WITH_GUEST		1
++#define IW_ANT_CHARGEABLE_PUBLIC_NETWORK		2
++#define IW_ANT_FREE_PUBLIC_NETWORK			3
++#define IW_ANT_PERSONAL_DEVICE_NETWORK			4
++#define IW_ANT_EMERGENCY_SERVICES_NETWORK		5
++#define IW_ANT_TEST_NETWORK				14
++#define IW_ANT_WILDCARD_NETWORK				15
++
++#define IW_ANT_LEN			1
++#define IW_VENUE_LEN			2
++#define IW_HESSID_LEN			6
++#define IW_HESSID_OFF			(IW_ANT_LEN + IW_VENUE_LEN)
++#define IW_MAX_LEN			(IW_ANT_LEN + IW_VENUE_LEN + IW_HESSID_LEN)
++
++/* 802.11u advertisement protocol */
++#define ADVP_ANQP_PROTOCOL_ID				0
++#define ADVP_MIH_PROTOCOL_ID				1
++
++/* 802.11u advertisement protocol masks */
++#define ADVP_QRL_MASK					0x7f
++#define ADVP_PAME_BI_MASK				0x80
++
++/* 802.11u advertisement protocol values */
++#define ADVP_QRL_REQUEST				0x00
++#define ADVP_QRL_RESPONSE				0x7f
++#define ADVP_PAME_BI_DEPENDENT				0x00
++#define ADVP_PAME_BI_INDEPENDENT			ADVP_PAME_BI_MASK
++
++/* 802.11u ANQP information ID */
++#define ANQP_ID_QUERY_LIST				256
++#define ANQP_ID_CAPABILITY_LIST				257
++#define ANQP_ID_VENUE_NAME_INFO				258
++#define ANQP_ID_EMERGENCY_CALL_NUMBER_INFO		259
++#define ANQP_ID_NETWORK_AUTHENTICATION_TYPE_INFO	260
++#define ANQP_ID_ROAMING_CONSORTIUM_LIST			261
++#define ANQP_ID_IP_ADDRESS_TYPE_AVAILABILITY_INFO	262
++#define ANQP_ID_NAI_REALM_LIST				263
++#define ANQP_ID_G3PP_CELLULAR_NETWORK_INFO		264
++#define ANQP_ID_AP_GEOSPATIAL_LOCATION			265
++#define ANQP_ID_AP_CIVIC_LOCATION			266
++#define ANQP_ID_AP_LOCATION_PUBLIC_ID_URI		267
++#define ANQP_ID_DOMAIN_NAME_LIST			268
++#define ANQP_ID_EMERGENCY_ALERT_ID_URI			269
++#define ANQP_ID_EMERGENCY_NAI				271
++#define ANQP_ID_VENDOR_SPECIFIC_LIST			56797
++
++/* 802.11u ANQP OUI */
++#define ANQP_OUI_SUBTYPE				9
++
++/* 802.11u venue name */
++#define VENUE_LANGUAGE_CODE_SIZE			3
++#define VENUE_NAME_SIZE					255
++
++/* 802.11u venue groups */
++#define VENUE_UNSPECIFIED				0
++#define VENUE_ASSEMBLY					1
++#define VENUE_BUSINESS					2
++#define VENUE_EDUCATIONAL				3
++#define VENUE_FACTORY					4
++#define VENUE_INSTITUTIONAL				5
++#define VENUE_MERCANTILE				6
++#define VENUE_RESIDENTIAL				7
++#define VENUE_STORAGE					8
++#define VENUE_UTILITY					9
++#define VENUE_VEHICULAR					10
++#define VENUE_OUTDOOR					11
++
++/* 802.11u network authentication type indicator */
++#define NATI_UNSPECIFIED				-1
++#define NATI_ACCEPTANCE_OF_TERMS_CONDITIONS		0
++#define NATI_ONLINE_ENROLLMENT_SUPPORTED		1
++#define NATI_HTTP_HTTPS_REDIRECTION			2
++#define NATI_DNS_REDIRECTION				3
++
++/* 802.11u IP address type availability - IPv6 */
++#define IPA_IPV6_SHIFT					0
++#define IPA_IPV6_MASK					(0x03 << IPA_IPV6_SHIFT)
++#define	IPA_IPV6_NOT_AVAILABLE				0x00
++#define IPA_IPV6_AVAILABLE				0x01
++#define IPA_IPV6_UNKNOWN_AVAILABILITY			0x02
++
++/* 802.11u IP address type availability - IPv4 */
++#define IPA_IPV4_SHIFT					2
++#define IPA_IPV4_MASK					(0x3f << IPA_IPV4_SHIFT)
++#define	IPA_IPV4_NOT_AVAILABLE				0x00
++#define IPA_IPV4_PUBLIC					0x01
++#define IPA_IPV4_PORT_RESTRICT				0x02
++#define IPA_IPV4_SINGLE_NAT				0x03
++#define IPA_IPV4_DOUBLE_NAT				0x04
++#define IPA_IPV4_PORT_RESTRICT_SINGLE_NAT		0x05
++#define IPA_IPV4_PORT_RESTRICT_DOUBLE_NAT		0x06
++#define IPA_IPV4_UNKNOWN_AVAILABILITY			0x07
++
++/* 802.11u NAI realm encoding */
++#define REALM_ENCODING_RFC4282				0
++#define REALM_ENCODING_UTF8				1
++
++/* 802.11u IANA EAP method type numbers */
++#define REALM_EAP_TLS					13
++#define REALM_EAP_LEAP					17
++#define REALM_EAP_SIM					18
++#define REALM_EAP_TTLS					21
++#define REALM_EAP_AKA					23
++#define REALM_EAP_PEAP					25
++#define REALM_EAP_FAST					43
++#define REALM_EAP_PSK					47
++#define REALM_EAP_AKAP					50
++#define REALM_EAP_EXPANDED				254
++
++/* 802.11u authentication ID */
++#define REALM_EXPANDED_EAP				1
++#define REALM_NON_EAP_INNER_AUTHENTICATION		2
++#define REALM_INNER_AUTHENTICATION_EAP			3
++#define REALM_EXPANDED_INNER_EAP			4
++#define REALM_CREDENTIAL				5
++#define REALM_TUNNELED_EAP_CREDENTIAL			6
++#define REALM_VENDOR_SPECIFIC_EAP			221
++
++/* 802.11u non-EAP inner authentication type */
++#define REALM_RESERVED_AUTH				0
++#define REALM_PAP					1
++#define REALM_CHAP					2
++#define REALM_MSCHAP					3
++#define REALM_MSCHAPV2					4
++
++/* 802.11u credential type */
++#define REALM_SIM					1
++#define REALM_USIM					2
++#define REALM_NFC					3
++#define REALM_HARDWARE_TOKEN				4
++#define REALM_SOFTOKEN					5
++#define REALM_CERTIFICATE				6
++#define REALM_USERNAME_PASSWORD				7
++#define REALM_SERVER_SIDE				8
++#define REALM_RESERVED_CRED				9
++#define REALM_VENDOR_SPECIFIC_CRED			10
++
++/* 802.11u 3GPP PLMN */
++#define G3PP_GUD_VERSION				0
++#define G3PP_PLMN_LIST_IE				0
++
++/* AP Location Public ID Info encoding */
++#define PUBLIC_ID_URI_FQDN_SE_ID		0
++/* URI/FQDN Descriptor field values */
++#define LOCATION_ENCODING_HELD			1
++#define LOCATION_ENCODING_SUPL			2
++#define URI_FQDN_SIZE					255
++
++/** hotspot2.0 indication element (vendor specific) */
++BWL_PRE_PACKED_STRUCT struct hs20_ie {
++	uint8 oui[3];
++	uint8 type;
++	uint8 config;
++} BWL_POST_PACKED_STRUCT;
++typedef struct hs20_ie hs20_ie_t;
++#define HS20_IE_LEN 5	/* HS20 IE length */
++
++/** IEEE 802.11 Annex E */
++typedef enum {
++	DOT11_2GHZ_20MHZ_CLASS_12	= 81,	/* Ch 1-11 */
++	DOT11_5GHZ_20MHZ_CLASS_1	= 115,	/* Ch 36-48 */
++	DOT11_5GHZ_20MHZ_CLASS_2_DFS	= 118,	/* Ch 52-64 */
++	DOT11_5GHZ_20MHZ_CLASS_3	= 124,	/* Ch 149-161 */
++	DOT11_5GHZ_20MHZ_CLASS_4_DFS	= 121,	/* Ch 100-140 */
++	DOT11_5GHZ_20MHZ_CLASS_5	= 125,	/* Ch 149-165 */
++	DOT11_5GHZ_40MHZ_CLASS_22	= 116,	/* Ch 36-44,   lower */
++	DOT11_5GHZ_40MHZ_CLASS_23_DFS 	= 119,	/* Ch 52-60,   lower */
++	DOT11_5GHZ_40MHZ_CLASS_24_DFS	= 122,	/* Ch 100-132, lower */
++	DOT11_5GHZ_40MHZ_CLASS_25	= 126,	/* Ch 149-157, lower */
++	DOT11_5GHZ_40MHZ_CLASS_27	= 117,	/* Ch 40-48,   upper */
++	DOT11_5GHZ_40MHZ_CLASS_28_DFS	= 120,	/* Ch 56-64,   upper */
++	DOT11_5GHZ_40MHZ_CLASS_29_DFS	= 123,	/* Ch 104-136, upper */
++	DOT11_5GHZ_40MHZ_CLASS_30	= 127,	/* Ch 153-161, upper */
++	DOT11_2GHZ_40MHZ_CLASS_32	= 83,	/* Ch 1-7,     lower */
++	DOT11_2GHZ_40MHZ_CLASS_33	= 84,	/* Ch 5-11,    upper */
++} dot11_op_class_t;
++
++/* QoS map */
++#define QOS_MAP_FIXED_LENGTH	(8 * 2)	/* DSCP ranges fixed with 8 entries */
++
++#define BCM_AIBSS_IE_TYPE 56
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++#endif /* _802_11_H_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/802.11e.h b/module_drivers/drivers/net/wireless/bcmdhd/include/802.11e.h
+new file mode 100644
+index 000000000..f2021e5d4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/802.11e.h
+@@ -0,0 +1,134 @@
++/*
++ * 802.11e protocol header file
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: 802.11e.h 700076 2017-05-17 14:42:22Z $
++ */
++
++#ifndef _802_11e_H_
++#define _802_11e_H_
++
++#ifndef _TYPEDEFS_H_
++#include <typedefs.h>
++#endif
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++
++/* WME Traffic Specification (TSPEC) element */
++#define WME_TSPEC_HDR_LEN           2           /* WME TSPEC header length */
++#define WME_TSPEC_BODY_OFF          2           /* WME TSPEC body offset */
++
++#define WME_CATEGORY_CODE_OFFSET	0		/* WME Category code offset */
++#define WME_ACTION_CODE_OFFSET		1		/* WME Action code offset */
++#define WME_TOKEN_CODE_OFFSET		2		/* WME Token code offset */
++#define WME_STATUS_CODE_OFFSET		3		/* WME Status code offset */
++
++BWL_PRE_PACKED_STRUCT struct tsinfo {
++	uint8 octets[3];
++} BWL_POST_PACKED_STRUCT;
++
++typedef struct tsinfo tsinfo_t;
++
++/* 802.11e TSPEC IE */
++typedef BWL_PRE_PACKED_STRUCT struct tspec {
++	uint8 oui[DOT11_OUI_LEN];	/* WME_OUI */
++	uint8 type;					/* WME_TYPE */
++	uint8 subtype;				/* WME_SUBTYPE_TSPEC */
++	uint8 version;				/* WME_VERSION */
++	tsinfo_t tsinfo;			/* TS Info bit field */
++	uint16 nom_msdu_size;		/* (Nominal or fixed) MSDU Size (bytes) */
++	uint16 max_msdu_size;		/* Maximum MSDU Size (bytes) */
++	uint32 min_srv_interval;	/* Minimum Service Interval (us) */
++	uint32 max_srv_interval;	/* Maximum Service Interval (us) */
++	uint32 inactivity_interval;	/* Inactivity Interval (us) */
++	uint32 suspension_interval; /* Suspension Interval (us) */
++	uint32 srv_start_time;		/* Service Start Time (us) */
++	uint32 min_data_rate;		/* Minimum Data Rate (bps) */
++	uint32 mean_data_rate;		/* Mean Data Rate (bps) */
++	uint32 peak_data_rate;		/* Peak Data Rate (bps) */
++	uint32 max_burst_size;		/* Maximum Burst Size (bytes) */
++	uint32 delay_bound;			/* Delay Bound (us) */
++	uint32 min_phy_rate;		/* Minimum PHY Rate (bps) */
++	uint16 surplus_bw;			/* Surplus Bandwidth Allowance (range 1.0-8.0) */
++	uint16 medium_time;			/* Medium Time (32 us/s periods) */
++} BWL_POST_PACKED_STRUCT tspec_t;
++
++#define WME_TSPEC_LEN	(sizeof(tspec_t))		/* not including 2-bytes of header */
++
++/* ts_info */
++/* 802.1D priority is duplicated - bits 13-11 AND bits 3-1 */
++#define TS_INFO_TID_SHIFT		1	/* TS info. TID shift */
++#define TS_INFO_TID_MASK		(0xf << TS_INFO_TID_SHIFT)	/* TS info. TID mask */
++#define TS_INFO_CONTENTION_SHIFT	7	/* TS info. contention shift */
++#define TS_INFO_CONTENTION_MASK	(0x1 << TS_INFO_CONTENTION_SHIFT) /* TS info. contention mask */
++#define TS_INFO_DIRECTION_SHIFT	5	/* TS info. direction shift */
++#define TS_INFO_DIRECTION_MASK	(0x3 << TS_INFO_DIRECTION_SHIFT) /* TS info. direction mask */
++#define TS_INFO_PSB_SHIFT		2		/* TS info. PSB bit Shift */
++#define TS_INFO_PSB_MASK		(1 << TS_INFO_PSB_SHIFT)	/* TS info. PSB mask */
++#define TS_INFO_UPLINK			(0 << TS_INFO_DIRECTION_SHIFT)	/* TS info. uplink */
++#define TS_INFO_DOWNLINK		(1 << TS_INFO_DIRECTION_SHIFT)	/* TS info. downlink */
++#define TS_INFO_BIDIRECTIONAL	(3 << TS_INFO_DIRECTION_SHIFT)	/* TS info. bidirectional */
++#define TS_INFO_USER_PRIO_SHIFT	3	/* TS info. user priority shift */
++/* TS info. user priority mask */
++#define TS_INFO_USER_PRIO_MASK	(0x7 << TS_INFO_USER_PRIO_SHIFT)
++
++/* Macro to get/set bit(s) field in TSINFO */
++#define WLC_CAC_GET_TID(pt)	((((pt).octets[0]) & TS_INFO_TID_MASK) >> TS_INFO_TID_SHIFT)
++#define WLC_CAC_GET_DIR(pt)	((((pt).octets[0]) & \
++	TS_INFO_DIRECTION_MASK) >> TS_INFO_DIRECTION_SHIFT)
++#define WLC_CAC_GET_PSB(pt)	((((pt).octets[1]) & TS_INFO_PSB_MASK) >> TS_INFO_PSB_SHIFT)
++#define WLC_CAC_GET_USER_PRIO(pt)	((((pt).octets[1]) & \
++	TS_INFO_USER_PRIO_MASK) >> TS_INFO_USER_PRIO_SHIFT)
++
++#define WLC_CAC_SET_TID(pt, id)	((((pt).octets[0]) & (~TS_INFO_TID_MASK)) | \
++	((id) << TS_INFO_TID_SHIFT))
++#define WLC_CAC_SET_USER_PRIO(pt, prio)	((((pt).octets[0]) & (~TS_INFO_USER_PRIO_MASK)) | \
++	((prio) << TS_INFO_USER_PRIO_SHIFT))
++
++/* 802.11e QBSS Load IE */
++#define QBSS_LOAD_IE_LEN		5	/* QBSS Load IE length */
++#define QBSS_LOAD_AAC_OFF		3	/* AAC offset in IE */
++
++#define CAC_ADDTS_RESP_TIMEOUT		1000	/* default ADDTS response timeout in ms */
++						/* DEFVAL dot11ADDTSResponseTimeout = 1s */
++
++/* 802.11e ADDTS status code */
++#define DOT11E_STATUS_ADMISSION_ACCEPTED	0	/* TSPEC Admission accepted status */
++#define DOT11E_STATUS_ADDTS_INVALID_PARAM	1	/* TSPEC invalid parameter status */
++#define DOT11E_STATUS_ADDTS_REFUSED_NSBW	3	/* ADDTS refused (non-sufficient BW) */
++#define DOT11E_STATUS_ADDTS_REFUSED_AWHILE	47	/* ADDTS refused but could retry later */
++
++/* 802.11e DELTS status code */
++#define DOT11E_STATUS_QSTA_LEAVE_QBSS		36	/* STA leave QBSS */
++#define DOT11E_STATUS_END_TS				37	/* END TS */
++#define DOT11E_STATUS_UNKNOWN_TS			38	/* UNKNOWN TS */
++#define DOT11E_STATUS_QSTA_REQ_TIMEOUT		39	/* STA ADDTS request timeout */
++
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++#endif /* _802_11e_CAC_H_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/802.11s.h b/module_drivers/drivers/net/wireless/bcmdhd/include/802.11s.h
+new file mode 100644
+index 000000000..8ad1693a9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/802.11s.h
+@@ -0,0 +1,336 @@
++/*
++ * Fundamental types and constants relating to 802.11s Mesh
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: 802.11s.h 700076 2017-05-17 14:42:22Z $
++ */
++
++#ifndef _802_11s_h_
++#define _802_11s_h_
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++
++#define DOT11_MESH_FLAGS_AE_MASK	0x3
++#define DOT11_MESH_FLAGS_AE_SHIFT	0
++
++#define DOT11_MESH_CONNECTED_AS_SET         7
++#define DOT11_MESH_NUMBER_PEERING_SET       1
++#define DOT11_MESH_MESH_GWSET               0
++
++#define DOT11_MESH_ACTION_LINK_MET_REP      0
++#define DOT11_MESH_ACTION_PATH_SEL          1
++#define DOT11_MESH_ACTION_GATE_ANN          2
++#define DOT11_MESH_ACTION_CONG_CONT_NOTIF   3
++#define DOT11_MESH_ACTION_MCCA_SETUP_REQ    4
++#define DOT11_MESH_ACTION_MCCA_SETUP_REP    5
++#define DOT11_MESH_ACTION_MCCA_ADVT_REQ     6
++#define DOT11_MESH_ACTION_MCCA_ADVT         7
++#define DOT11_MESH_ACTION_MCCA_TEARDOWN     8
++#define DOT11_MESH_ACTION_TBTT_ADJ_REQ      9
++#define DOT11_MESH_ACTION_TBTT_ADJ_RESP     10
++
++/* self-protected action field values: 7-57v24 */
++#define DOT11_SELFPROT_ACTION_MESH_PEER_OPEN    1
++#define DOT11_SELFPROT_ACTION_MESH_PEER_CONFM   2
++#define DOT11_SELFPROT_ACTION_MESH_PEER_CLOSE   3
++#define DOT11_SELFPROT_ACTION_MESH_PEER_GK_INF  4
++#define DOT11_SELFPROT_ACTION_MESH_PEER_GK_ACK  5
++
++#define DOT11_MESH_AUTH_PROTO_NONE        0
++#define DOT11_MESH_AUTH_PROTO_SAE         1
++#define DOT11_MESH_AUTH_PROTO_8021X       2
++#define DOT11_MESH_AUTH_PROTO_VS        255
++
++#define DOT11_MESH_PATHSEL_LEN   2
++#define DOT11_MESH_PERR_LEN1     2   /* Least PERR length fixed */
++#define DOT11_MESH_PERR_LEN2     13  /* Least PERR length variable */
++#define DOT11_MESH_PREP_LEN      31  /* Least PREP length */
++#define DOT11_MESH_PREQ_LEN      37  /* Least PREQ length */
++
++#define DOT11_MESH_PATHSEL_PROTID_HWMP    1
++#define DOT11_MESH_PATHSEL_METRICID_ALM   1 /* Air link metric */
++#define DOT11_MESH_CONGESTCTRL_NONE       0
++#define DOT11_MESH_CONGESTCTRL_SP         1
++#define DOT11_MESH_SYNCMETHOD_NOFFSET     1
++
++BWL_PRE_PACKED_STRUCT struct dot11_meshctrl_hdr {
++	uint8               flags;      /* flag bits such as ae etc */
++	uint8               ttl;        /* time to live */
++	uint32              seq;        /* sequence control */
++	struct ether_addr   a5;         /* optional address 5 */
++	struct ether_addr   a6;         /* optional address 6 */
++} BWL_POST_PACKED_STRUCT;
++
++/* Mesh Path Selection Action Frame */
++BWL_PRE_PACKED_STRUCT struct dot11_mesh_pathsel {
++	uint8   category;
++	uint8   meshaction;
++	uint8   data[];
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_mesh_pathsel dot11_mesh_pathsel_t;
++
++/*  Mesh PREQ IE */
++BWL_PRE_PACKED_STRUCT struct mesh_preq_ie {
++	uint8   id;
++	uint8   len;
++	uint8   flags;
++	uint8   hop_count;
++	uint8   ttl;
++	uint32  pathdis_id;
++	struct  ether_addr  originator_addr;
++	uint32  originator_seq;
++	union {
++		BWL_PRE_PACKED_STRUCT struct {
++			struct ether_addr target_ext_add;
++			uint32  lifetime;
++			uint32  metric;
++			uint8   target_count;
++			uint8   data[];
++		} BWL_POST_PACKED_STRUCT oea;
++
++		BWL_PRE_PACKED_STRUCT struct {
++			uint32  lifetime;
++			uint32  metric;
++			uint8   target_count;
++			uint8   data[];
++		} BWL_POST_PACKED_STRUCT noea;
++	} u;
++} BWL_POST_PACKED_STRUCT;
++typedef struct mesh_preq_ie mesh_preq_ie_t;
++
++/* Target info (part of Mesh PREQ IE) */
++BWL_PRE_PACKED_STRUCT struct mesh_targetinfo {
++	uint8	target_flag;
++	struct	ether_addr	target_addr;
++	uint32	target_seq;
++} BWL_POST_PACKED_STRUCT;
++typedef struct mesh_targetinfo mesh_targetinfo_t;
++
++
++/* Mesh PREP IE */
++BWL_PRE_PACKED_STRUCT struct mesh_prep_ie {
++	uint8	id;
++	uint8	len;
++	uint8	flags;
++	uint8	hop_count;
++	uint8	ttl;
++	struct	ether_addr	target_addr;
++	uint32	target_seq;
++	union {
++		BWL_PRE_PACKED_STRUCT struct {
++			struct ether_addr target_ext_add;
++			uint32  lifetime;
++			uint32  metric;
++			uint8   target_count;
++	                struct	ether_addr	originator_addr;
++	                uint32	originator_seq;
++		} BWL_POST_PACKED_STRUCT oea;
++
++		BWL_PRE_PACKED_STRUCT struct {
++			uint32  lifetime;
++			uint32  metric;
++			uint8   target_count;
++	                struct	ether_addr	originator_addr;
++	                uint32	originator_seq;
++		} BWL_POST_PACKED_STRUCT noea;
++	} u;
++} BWL_POST_PACKED_STRUCT;
++typedef struct mesh_prep_ie mesh_prep_ie_t;
++
++
++/* Mesh PERR IE */
++struct mesh_perr_ie {
++	uint8	id;
++	uint8	len;
++	uint8	ttl;
++	uint8	num_dest;
++	uint8	data[];
++};
++typedef struct mesh_perr_ie mesh_perr_ie_t;
++
++/* Destination info is part of PERR IE */
++BWL_PRE_PACKED_STRUCT struct mesh_perr_destinfo {
++	uint8	flags;
++	struct	ether_addr	destination_addr;
++	uint32	dest_seq;
++	union {
++		BWL_PRE_PACKED_STRUCT struct {
++			struct  ether_addr      dest_ext_addr;
++		} BWL_POST_PACKED_STRUCT dea;
++
++		BWL_PRE_PACKED_STRUCT struct {
++		/* 1 byte reason code to be populated manually in software */
++			uint16	reason_code;
++		} BWL_POST_PACKED_STRUCT nodea;
++	} u;
++} BWL_POST_PACKED_STRUCT;
++typedef struct mesh_perr_destinfo mesh_perr_destinfo_t;
++
++/* Mesh peering action frame hdr */
++BWL_PRE_PACKED_STRUCT struct mesh_peering_frmhdr {
++	uint8	category;
++	uint8	action;
++	union	{
++		struct {
++			uint16	capability;
++		} open;
++		struct {
++			uint16	capability;
++			uint16	AID;
++		} confirm;
++		uint8 data[1];
++	} u;
++} BWL_POST_PACKED_STRUCT;
++typedef struct mesh_peering_frmhdr mesh_peering_frmhdr_t;
++
++/* Mesh peering mgmt IE */
++BWL_PRE_PACKED_STRUCT struct mesh_peer_mgmt_ie_common {
++	uint16	mesh_peer_prot_id;
++	uint16	local_link_id;
++} BWL_POST_PACKED_STRUCT;
++typedef struct mesh_peer_mgmt_ie_common mesh_peer_mgmt_ie_common_t;
++#define MESH_PEER_MGMT_IE_OPEN_LEN	(4)
++
++BWL_PRE_PACKED_STRUCT struct mesh_peer_mgmt_ie_cfm {
++	mesh_peer_mgmt_ie_common_t	common;
++	uint16	peer_link_id;
++} BWL_POST_PACKED_STRUCT;
++typedef struct mesh_peer_mgmt_ie_cfm mesh_peer_mgmt_ie_cfm_t;
++#define MESH_PEER_MGMT_IE_CONF_LEN	(6)
++
++BWL_PRE_PACKED_STRUCT struct mesh_peer_mgmt_ie_close {
++	mesh_peer_mgmt_ie_common_t	common;
++	/* uint16	peer_link_id;
++	* simplicity: not supported, TODO for future
++	*/
++	uint16	reason_code;
++} BWL_POST_PACKED_STRUCT;
++typedef struct mesh_peer_mgmt_ie_close mesh_peer_mgmt_ie_close_t;
++#define MESH_PEER_MGMT_IE_CLOSE_LEN	(6)
++
++struct mesh_config_ie {
++	uint8	activ_path_sel_prot_id;
++	uint8	activ_path_sel_metric_id;
++	uint8	cong_ctl_mode_id;
++	uint8	sync_method_id;
++	uint8	auth_prot_id;
++	uint8	mesh_formation_info;
++	uint8	mesh_cap;
++};
++typedef struct mesh_config_ie mesh_config_ie_t;
++#define MESH_CONFIG_IE_LEN	(7)
++
++/* Mesh peering states */
++#define MESH_PEERING_IDLE               0
++#define MESH_PEERING_OPEN_SNT           1
++#define MESH_PEERING_CNF_RCVD           2
++#define MESH_PEERING_OPEN_RCVD          3
++#define MESH_PEERING_ESTAB              4
++#define MESH_PEERING_HOLDING            5
++#define MESH_PEERING_LAST_STATE         6
++/* for debugging: mapping strings */
++#define MESH_PEERING_STATE_STRINGS \
++	{"IDLE  ", "OPNSNT", "CNFRCV", "OPNRCV", "ESTAB ", "HOLDNG"}
++
++#ifdef WLMESH
++typedef BWL_PRE_PACKED_STRUCT struct mesh_peer_info {
++	/* mesh_peer_instance as given in the spec. Note that, peer address
++	 * is stored in scb
++	 */
++	uint16	mesh_peer_prot_id;
++	uint16	local_link_id;
++	uint16	peer_link_id;
++	/* AID generated by *peer* to self & received in peer_confirm */
++	uint16  peer_aid;
++
++	/* TODO: no mention in spec? possibly used in PS case. Note that aid generated
++	* from self to peer is stored in scb.
++	*/
++	uint8   state;
++	/* TODO: struct mesh_peer_info *next; this field is required
++	 * if multiple peerings per same src is allowed, which is
++	 * true as per spec.
++	 */
++} BWL_POST_PACKED_STRUCT mesh_peer_info_t;
++
++typedef BWL_PRE_PACKED_STRUCT struct mesh_peer_info_ext {
++	mesh_peer_info_t	peer_info;
++	uint16	local_aid;	/* AID generated by *local* to peer */
++	struct ether_addr ea; /* peer ea */
++	uint32	entry_state;	/* see MESH_PEER_ENTRY_STATE_ACTIVE etc; valid
++		* ONLY for internal peering requests
++		*/
++	int rssi;
++} BWL_POST_PACKED_STRUCT mesh_peer_info_ext_t;
++
++/* #ifdef WLMESH */
++typedef BWL_PRE_PACKED_STRUCT struct mesh_peer_info_dump {
++	uint32 buflen;
++	uint32 version;
++	uint32 count;	/* number of results */
++	mesh_peer_info_ext_t	mpi_ext[1];
++} BWL_POST_PACKED_STRUCT mesh_peer_info_dump_t;
++#define WL_MESH_PEER_RES_FIXED_SIZE (sizeof(mesh_peer_info_dump_t) - sizeof(mesh_peer_info_ext_t))
++
++#endif /* WLMESH */
++
++/* once an entry is added into mesh_peer_list, if peering is lost, it will
++* get retried for peering, MAX_MESH_PEER_ENTRY_RETRIES times. after wards, it
++* wont get retried and will be moved to MESH_PEER_ENTRY_STATE_TIMEDOUT state,
++* until user adds it again explicitely, when its entry_state is changed
++* to MESH_PEER_ENTRY_STATE_ACTIVE and tried again.
++*/
++#define MAX_MESH_SELF_PEER_ENTRY_RETRIES	3
++#define MESH_SELF_PEER_ENTRY_STATE_ACTIVE	1
++#define MESH_SELF_PEER_ENTRY_STATE_TIMEDOUT	2
++
++/** Mesh Channel Switch Parameter IE data structure */
++BWL_PRE_PACKED_STRUCT struct dot11_mcsp_body {
++	uint8 ttl;           /* remaining number of hops allowed for this element. */
++	uint8 flags;         /* attributes of this channel switch attempt */
++	uint8 reason;        /* reason for the mesh channel switch */
++	uint16 precedence;    /* random value in the range 0 to 65535 */
++} BWL_POST_PACKED_STRUCT;
++
++#define DOT11_MCSP_TTL_DEFAULT          1
++#define DOT11_MCSP_FLAG_TRANS_RESTRICT	0x1	/* no transmit except frames with mcsp */
++#define DOT11_MCSP_FLAG_INIT		0x2	/* initiates the channel switch attempt */
++#define DOT11_MCSP_FLAG_REASON		0x4	/* validity of reason code field */
++#define DOT11_MCSP_REASON_REGULATORY	0	/* meet regulatory requirements */
++#define DOT11_MCSP_REASON_UNSPECIFIED	1	/* unspecified reason */
++
++BWL_PRE_PACKED_STRUCT struct dot11_mesh_csp {
++	uint8 id; /* id DOT11_MNG_MESH_CSP_ID */
++	uint8 len; /* length of IE */
++	struct dot11_mcsp_body body; /* body of the ie */
++} BWL_POST_PACKED_STRUCT;
++typedef struct dot11_mesh_csp dot11_mesh_csp_ie_t;
++#define DOT11_MESH_CSP_IE_LEN    5       /* length of mesh channel switch parameter IE body */
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++#endif  /* #ifndef _802_11s_H_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/802.1d.h b/module_drivers/drivers/net/wireless/bcmdhd/include/802.1d.h
+new file mode 100644
+index 000000000..1b8dea5b1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/802.1d.h
+@@ -0,0 +1,53 @@
++/*
++ * Fundamental types and constants relating to 802.1D
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: 802.1d.h 700076 2017-05-17 14:42:22Z $
++ */
++
++#ifndef _802_1_D_
++#define _802_1_D_
++
++/* 802.1D priority defines */
++#define	PRIO_8021D_NONE		2	/* None = - */
++#define	PRIO_8021D_BK		1	/* BK - Background */
++#define	PRIO_8021D_BE		0	/* BE - Best-effort */
++#define	PRIO_8021D_EE		3	/* EE - Excellent-effort */
++#define	PRIO_8021D_CL		4	/* CL - Controlled Load */
++#define	PRIO_8021D_VI		5	/* Vi - Video */
++#define	PRIO_8021D_VO		6	/* Vo - Voice */
++#define	PRIO_8021D_NC		7	/* NC - Network Control */
++#define	MAXPRIO			7	/* 0-7 */
++#define NUMPRIO			(MAXPRIO + 1)
++
++#define ALLPRIO		-1	/* All prioirty */
++
++/* Converts prio to precedence since the numerical value of
++ * PRIO_8021D_BE and PRIO_8021D_NONE are swapped.
++ */
++#define PRIO2PREC(prio) \
++	(((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? ((prio^2)) : (prio))
++
++#endif /* _802_1_D__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/802.3.h b/module_drivers/drivers/net/wireless/bcmdhd/include/802.3.h
+new file mode 100644
+index 000000000..6758ac048
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/802.3.h
+@@ -0,0 +1,55 @@
++/*
++ * Fundamental constants relating to 802.3
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: 802.3.h 700076 2017-05-17 14:42:22Z $
++ */
++
++#ifndef _802_3_h_
++#define _802_3_h_
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++
++#define SNAP_HDR_LEN	6	/* 802.3 SNAP header length */
++#define DOT3_OUI_LEN	3	/* 802.3 oui length */
++
++BWL_PRE_PACKED_STRUCT struct dot3_mac_llc_snap_header {
++	uint8	ether_dhost[ETHER_ADDR_LEN];	/* dest mac */
++	uint8	ether_shost[ETHER_ADDR_LEN];	/* src mac */
++	uint16	length;				/* frame length incl header */
++	uint8	dsap;				/* always 0xAA */
++	uint8	ssap;				/* always 0xAA */
++	uint8	ctl;				/* always 0x03 */
++	uint8	oui[DOT3_OUI_LEN];		/* RFC1042: 0x00 0x00 0x00
++						 * Bridge-Tunnel: 0x00 0x00 0xF8
++						 */
++	uint16	type;				/* ethertype */
++} BWL_POST_PACKED_STRUCT;
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++#endif	/* #ifndef _802_3_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/aidmp.h b/module_drivers/drivers/net/wireless/bcmdhd/include/aidmp.h
+new file mode 100644
+index 000000000..10992e763
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/aidmp.h
+@@ -0,0 +1,424 @@
++/*
++ * Broadcom AMBA Interconnect definitions.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: aidmp.h 614820 2016-01-23 17:16:17Z $
++ */
++
++#ifndef	_AIDMP_H
++#define	_AIDMP_H
++
++/* Manufacturer Ids */
++#define	MFGID_ARM		0x43b
++#define	MFGID_BRCM		0x4bf
++#define	MFGID_MIPS		0x4a7
++
++/* Component Classes */
++#define	CC_SIM			0
++#define	CC_EROM			1
++#define	CC_CORESIGHT		9
++#define	CC_VERIF		0xb
++#define	CC_OPTIMO		0xd
++#define	CC_GEN			0xe
++#define	CC_PRIMECELL		0xf
++
++/* Enumeration ROM registers */
++#define	ER_EROMENTRY		0x000
++#define	ER_REMAPCONTROL		0xe00
++#define	ER_REMAPSELECT		0xe04
++#define	ER_MASTERSELECT		0xe10
++#define	ER_ITCR			0xf00
++#define	ER_ITIP			0xf04
++
++/* Erom entries */
++#define	ER_TAG			0xe
++#define	ER_TAG1			0x6
++#define	ER_VALID		1
++#define	ER_CI			0
++#define	ER_MP			2
++#define	ER_ADD			4
++#define	ER_END			0xe
++#define	ER_BAD			0xffffffff
++#define	ER_SZ_MAX		4096 /* 4KB */
++
++/* EROM CompIdentA */
++#define	CIA_MFG_MASK		0xfff00000
++#define	CIA_MFG_SHIFT		20
++#define	CIA_CID_MASK		0x000fff00
++#define	CIA_CID_SHIFT		8
++#define	CIA_CCL_MASK		0x000000f0
++#define	CIA_CCL_SHIFT		4
++
++/* EROM CompIdentB */
++#define	CIB_REV_MASK		0xff000000
++#define	CIB_REV_SHIFT		24
++#define	CIB_NSW_MASK		0x00f80000
++#define	CIB_NSW_SHIFT		19
++#define	CIB_NMW_MASK		0x0007c000
++#define	CIB_NMW_SHIFT		14
++#define	CIB_NSP_MASK		0x00003e00
++#define	CIB_NSP_SHIFT		9
++#define	CIB_NMP_MASK		0x000001f0
++#define	CIB_NMP_SHIFT		4
++
++/* EROM MasterPortDesc */
++#define	MPD_MUI_MASK		0x0000ff00
++#define	MPD_MUI_SHIFT		8
++#define	MPD_MP_MASK		0x000000f0
++#define	MPD_MP_SHIFT		4
++
++/* EROM AddrDesc */
++#define	AD_ADDR_MASK		0xfffff000
++#define	AD_SP_MASK		0x00000f00
++#define	AD_SP_SHIFT		8
++#define	AD_ST_MASK		0x000000c0
++#define	AD_ST_SHIFT		6
++#define	AD_ST_SLAVE		0x00000000
++#define	AD_ST_BRIDGE		0x00000040
++#define	AD_ST_SWRAP		0x00000080
++#define	AD_ST_MWRAP		0x000000c0
++#define	AD_SZ_MASK		0x00000030
++#define	AD_SZ_SHIFT		4
++#define	AD_SZ_4K		0x00000000
++#define	AD_SZ_8K		0x00000010
++#define	AD_SZ_16K		0x00000020
++#define	AD_SZ_SZD		0x00000030
++#define	AD_AG32			0x00000008
++#define	AD_ADDR_ALIGN		0x00000fff
++#define	AD_SZ_BASE		0x00001000	/* 4KB */
++
++/* EROM SizeDesc */
++#define	SD_SZ_MASK		0xfffff000
++#define	SD_SG32			0x00000008
++#define	SD_SZ_ALIGN		0x00000fff
++
++
++#if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__)
++
++typedef volatile struct _aidmp {
++	uint32	oobselina30;	/* 0x000 */
++	uint32	oobselina74;	/* 0x004 */
++	uint32	PAD[6];
++	uint32	oobselinb30;	/* 0x020 */
++	uint32	oobselinb74;	/* 0x024 */
++	uint32	PAD[6];
++	uint32	oobselinc30;	/* 0x040 */
++	uint32	oobselinc74;	/* 0x044 */
++	uint32	PAD[6];
++	uint32	oobselind30;	/* 0x060 */
++	uint32	oobselind74;	/* 0x064 */
++	uint32	PAD[38];
++	uint32	oobselouta30;	/* 0x100 */
++	uint32	oobselouta74;	/* 0x104 */
++	uint32	PAD[6];
++	uint32	oobseloutb30;	/* 0x120 */
++	uint32	oobseloutb74;	/* 0x124 */
++	uint32	PAD[6];
++	uint32	oobseloutc30;	/* 0x140 */
++	uint32	oobseloutc74;	/* 0x144 */
++	uint32	PAD[6];
++	uint32	oobseloutd30;	/* 0x160 */
++	uint32	oobseloutd74;	/* 0x164 */
++	uint32	PAD[38];
++	uint32	oobsynca;	/* 0x200 */
++	uint32	oobseloutaen;	/* 0x204 */
++	uint32	PAD[6];
++	uint32	oobsyncb;	/* 0x220 */
++	uint32	oobseloutben;	/* 0x224 */
++	uint32	PAD[6];
++	uint32	oobsyncc;	/* 0x240 */
++	uint32	oobseloutcen;	/* 0x244 */
++	uint32	PAD[6];
++	uint32	oobsyncd;	/* 0x260 */
++	uint32	oobseloutden;	/* 0x264 */
++	uint32	PAD[38];
++	uint32	oobaextwidth;	/* 0x300 */
++	uint32	oobainwidth;	/* 0x304 */
++	uint32	oobaoutwidth;	/* 0x308 */
++	uint32	PAD[5];
++	uint32	oobbextwidth;	/* 0x320 */
++	uint32	oobbinwidth;	/* 0x324 */
++	uint32	oobboutwidth;	/* 0x328 */
++	uint32	PAD[5];
++	uint32	oobcextwidth;	/* 0x340 */
++	uint32	oobcinwidth;	/* 0x344 */
++	uint32	oobcoutwidth;	/* 0x348 */
++	uint32	PAD[5];
++	uint32	oobdextwidth;	/* 0x360 */
++	uint32	oobdinwidth;	/* 0x364 */
++	uint32	oobdoutwidth;	/* 0x368 */
++	uint32	PAD[37];
++	uint32	ioctrlset;	/* 0x400 */
++	uint32	ioctrlclear;	/* 0x404 */
++	uint32	ioctrl;		/* 0x408 */
++	uint32	PAD[61];
++	uint32	iostatus;	/* 0x500 */
++	uint32	PAD[127];
++	uint32	ioctrlwidth;	/* 0x700 */
++	uint32	iostatuswidth;	/* 0x704 */
++	uint32	PAD[62];
++	uint32	resetctrl;	/* 0x800 */
++	uint32	resetstatus;	/* 0x804 */
++	uint32	resetreadid;	/* 0x808 */
++	uint32	resetwriteid;	/* 0x80c */
++	uint32	PAD[60];
++	uint32	errlogctrl;	/* 0x900 */
++	uint32	errlogdone;	/* 0x904 */
++	uint32	errlogstatus;	/* 0x908 */
++	uint32	errlogaddrlo;	/* 0x90c */
++	uint32	errlogaddrhi;	/* 0x910 */
++	uint32	errlogid;	/* 0x914 */
++	uint32	errloguser;	/* 0x918 */
++	uint32	errlogflags;	/* 0x91c */
++	uint32	PAD[56];
++	uint32	intstatus;	/* 0xa00 */
++	uint32	PAD[255];
++	uint32	config;		/* 0xe00 */
++	uint32	PAD[63];
++	uint32	itcr;		/* 0xf00 */
++	uint32	PAD[3];
++	uint32	itipooba;	/* 0xf10 */
++	uint32	itipoobb;	/* 0xf14 */
++	uint32	itipoobc;	/* 0xf18 */
++	uint32	itipoobd;	/* 0xf1c */
++	uint32	PAD[4];
++	uint32	itipoobaout;	/* 0xf30 */
++	uint32	itipoobbout;	/* 0xf34 */
++	uint32	itipoobcout;	/* 0xf38 */
++	uint32	itipoobdout;	/* 0xf3c */
++	uint32	PAD[4];
++	uint32	itopooba;	/* 0xf50 */
++	uint32	itopoobb;	/* 0xf54 */
++	uint32	itopoobc;	/* 0xf58 */
++	uint32	itopoobd;	/* 0xf5c */
++	uint32	PAD[4];
++	uint32	itopoobain;	/* 0xf70 */
++	uint32	itopoobbin;	/* 0xf74 */
++	uint32	itopoobcin;	/* 0xf78 */
++	uint32	itopoobdin;	/* 0xf7c */
++	uint32	PAD[4];
++	uint32	itopreset;	/* 0xf90 */
++	uint32	PAD[15];
++	uint32	peripherialid4;	/* 0xfd0 */
++	uint32	peripherialid5;	/* 0xfd4 */
++	uint32	peripherialid6;	/* 0xfd8 */
++	uint32	peripherialid7;	/* 0xfdc */
++	uint32	peripherialid0;	/* 0xfe0 */
++	uint32	peripherialid1;	/* 0xfe4 */
++	uint32	peripherialid2;	/* 0xfe8 */
++	uint32	peripherialid3;	/* 0xfec */
++	uint32	componentid0;	/* 0xff0 */
++	uint32	componentid1;	/* 0xff4 */
++	uint32	componentid2;	/* 0xff8 */
++	uint32	componentid3;	/* 0xffc */
++} aidmp_t;
++
++#endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */
++
++/* Out-of-band Router registers */
++#define	OOB_BUSCONFIG		0x020
++#define	OOB_STATUSA		0x100
++#define	OOB_STATUSB		0x104
++#define	OOB_STATUSC		0x108
++#define	OOB_STATUSD		0x10c
++#define	OOB_ENABLEA0		0x200
++#define	OOB_ENABLEA1		0x204
++#define	OOB_ENABLEA2		0x208
++#define	OOB_ENABLEA3		0x20c
++#define	OOB_ENABLEB0		0x280
++#define	OOB_ENABLEB1		0x284
++#define	OOB_ENABLEB2		0x288
++#define	OOB_ENABLEB3		0x28c
++#define	OOB_ENABLEC0		0x300
++#define	OOB_ENABLEC1		0x304
++#define	OOB_ENABLEC2		0x308
++#define	OOB_ENABLEC3		0x30c
++#define	OOB_ENABLED0		0x380
++#define	OOB_ENABLED1		0x384
++#define	OOB_ENABLED2		0x388
++#define	OOB_ENABLED3		0x38c
++#define	OOB_ITCR		0xf00
++#define	OOB_ITIPOOBA		0xf10
++#define	OOB_ITIPOOBB		0xf14
++#define	OOB_ITIPOOBC		0xf18
++#define	OOB_ITIPOOBD		0xf1c
++#define	OOB_ITOPOOBA		0xf30
++#define	OOB_ITOPOOBB		0xf34
++#define	OOB_ITOPOOBC		0xf38
++#define	OOB_ITOPOOBD		0xf3c
++
++/* DMP wrapper registers */
++#define	AI_OOBSELINA30		0x000
++#define	AI_OOBSELINA74		0x004
++#define	AI_OOBSELINB30		0x020
++#define	AI_OOBSELINB74		0x024
++#define	AI_OOBSELINC30		0x040
++#define	AI_OOBSELINC74		0x044
++#define	AI_OOBSELIND30		0x060
++#define	AI_OOBSELIND74		0x064
++#define	AI_OOBSELOUTA30		0x100
++#define	AI_OOBSELOUTA74		0x104
++#define	AI_OOBSELOUTB30		0x120
++#define	AI_OOBSELOUTB74		0x124
++#define	AI_OOBSELOUTC30		0x140
++#define	AI_OOBSELOUTC74		0x144
++#define	AI_OOBSELOUTD30		0x160
++#define	AI_OOBSELOUTD74		0x164
++#define	AI_OOBSYNCA		0x200
++#define	AI_OOBSELOUTAEN		0x204
++#define	AI_OOBSYNCB		0x220
++#define	AI_OOBSELOUTBEN		0x224
++#define	AI_OOBSYNCC		0x240
++#define	AI_OOBSELOUTCEN		0x244
++#define	AI_OOBSYNCD		0x260
++#define	AI_OOBSELOUTDEN		0x264
++#define	AI_OOBAEXTWIDTH		0x300
++#define	AI_OOBAINWIDTH		0x304
++#define	AI_OOBAOUTWIDTH		0x308
++#define	AI_OOBBEXTWIDTH		0x320
++#define	AI_OOBBINWIDTH		0x324
++#define	AI_OOBBOUTWIDTH		0x328
++#define	AI_OOBCEXTWIDTH		0x340
++#define	AI_OOBCINWIDTH		0x344
++#define	AI_OOBCOUTWIDTH		0x348
++#define	AI_OOBDEXTWIDTH		0x360
++#define	AI_OOBDINWIDTH		0x364
++#define	AI_OOBDOUTWIDTH		0x368
++
++
++#define	AI_IOCTRLSET		0x400
++#define	AI_IOCTRLCLEAR		0x404
++#define	AI_IOCTRL		0x408
++#define	AI_IOSTATUS		0x500
++#define	AI_RESETCTRL		0x800
++#define	AI_RESETSTATUS		0x804
++
++#define	AI_IOCTRLWIDTH		0x700
++#define	AI_IOSTATUSWIDTH	0x704
++
++#define	AI_RESETREADID		0x808
++#define	AI_RESETWRITEID		0x80c
++#define	AI_ERRLOGCTRL		0x900
++#define	AI_ERRLOGDONE		0x904
++#define	AI_ERRLOGSTATUS		0x908
++#define	AI_ERRLOGADDRLO		0x90c
++#define	AI_ERRLOGADDRHI		0x910
++#define	AI_ERRLOGID		0x914
++#define	AI_ERRLOGUSER		0x918
++#define	AI_ERRLOGFLAGS		0x91c
++#define	AI_INTSTATUS		0xa00
++#define	AI_CONFIG		0xe00
++#define	AI_ITCR			0xf00
++#define	AI_ITIPOOBA		0xf10
++#define	AI_ITIPOOBB		0xf14
++#define	AI_ITIPOOBC		0xf18
++#define	AI_ITIPOOBD		0xf1c
++#define	AI_ITIPOOBAOUT		0xf30
++#define	AI_ITIPOOBBOUT		0xf34
++#define	AI_ITIPOOBCOUT		0xf38
++#define	AI_ITIPOOBDOUT		0xf3c
++#define	AI_ITOPOOBA		0xf50
++#define	AI_ITOPOOBB		0xf54
++#define	AI_ITOPOOBC		0xf58
++#define	AI_ITOPOOBD		0xf5c
++#define	AI_ITOPOOBAIN		0xf70
++#define	AI_ITOPOOBBIN		0xf74
++#define	AI_ITOPOOBCIN		0xf78
++#define	AI_ITOPOOBDIN		0xf7c
++#define	AI_ITOPRESET		0xf90
++#define	AI_PERIPHERIALID4	0xfd0
++#define	AI_PERIPHERIALID5	0xfd4
++#define	AI_PERIPHERIALID6	0xfd8
++#define	AI_PERIPHERIALID7	0xfdc
++#define	AI_PERIPHERIALID0	0xfe0
++#define	AI_PERIPHERIALID1	0xfe4
++#define	AI_PERIPHERIALID2	0xfe8
++#define	AI_PERIPHERIALID3	0xfec
++#define	AI_COMPONENTID0		0xff0
++#define	AI_COMPONENTID1		0xff4
++#define	AI_COMPONENTID2		0xff8
++#define	AI_COMPONENTID3		0xffc
++
++/* resetctrl */
++#define	AIRC_RESET		1
++
++/* errlogctrl */
++#define AIELC_TO_EXP_MASK	0x0000001f0		/* backplane timeout exponent */
++#define AIELC_TO_EXP_SHIFT	4
++#define AIELC_TO_ENAB_SHIFT	9			/* backplane timeout enable */
++
++/* errlogdone */
++#define AIELD_ERRDONE_MASK	0x3
++
++/* errlogstatus */
++#define AIELS_SLAVE_ERR         0x1
++#define AIELS_TIMEOUT           0x2
++#define AIELS_DECODE            0x3
++#define AIELS_TIMEOUT_MASK      0x3
++
++/* errorlog status bit map, for SW use */
++#define AXI_WRAP_STS_NONE		(0)
++#define AXI_WRAP_STS_TIMEOUT		(1<<0)
++#define AXI_WRAP_STS_SLAVE_ERR		(1<<1)
++#define AXI_WRAP_STS_DECODE_ERR		(1<<2)
++#define AXI_WRAP_STS_PCI_RD_ERR		(1<<3)
++#define AXI_WRAP_STS_WRAP_RD_ERR	(1<<4)
++#define AXI_WRAP_STS_SET_CORE_FAIL	(1<<5)
++
++/* errlogFrags */
++#define AXI_ERRLOG_FLAGS_WRITE_REQ	(1<<24)
++
++/* config */
++#define	AICFG_OOB		0x00000020
++#define	AICFG_IOS		0x00000010
++#define	AICFG_IOC		0x00000008
++#define	AICFG_TO		0x00000004
++#define	AICFG_ERRL		0x00000002
++#define	AICFG_RST		0x00000001
++
++/* bit defines for AI_OOBSELOUTB74 reg */
++#define OOB_SEL_OUTEN_B_5	15
++#define OOB_SEL_OUTEN_B_6	23
++
++/* AI_OOBSEL for A/B/C/D, 0-7 */
++#define AI_OOBSEL_MASK		0x1F
++#define AI_OOBSEL_0_SHIFT	0
++#define AI_OOBSEL_1_SHIFT	8
++#define AI_OOBSEL_2_SHIFT	16
++#define AI_OOBSEL_3_SHIFT	24
++#define AI_OOBSEL_4_SHIFT	0
++#define AI_OOBSEL_5_SHIFT	8
++#define AI_OOBSEL_6_SHIFT	16
++#define AI_OOBSEL_7_SHIFT	24
++#define AI_IOCTRL_ENABLE_D11_PME	(1 << 14)
++
++/* mask for interrupts from each core to wrapper */
++#define AI_OOBSELINA74_CORE_MASK       0x80808080
++#define AI_OOBSELINA30_CORE_MASK       0x80808080
++
++/* axi id mask in the error log id */
++#define AI_ERRLOGID_AXI_ID_MASK 0x07
++
++#endif	/* _AIDMP_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcm_cfg.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcm_cfg.h
+new file mode 100644
+index 000000000..12e3cb2ca
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcm_cfg.h
+@@ -0,0 +1,32 @@
++/*
++ * BCM common config options
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcm_cfg.h 514727 2014-11-12 03:02:48Z $
++ */
++
++#ifndef _bcm_cfg_h_
++#define _bcm_cfg_h_
++#endif /* _bcm_cfg_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcm_mpool_pub.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcm_mpool_pub.h
+new file mode 100644
+index 000000000..f8ce7a78e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcm_mpool_pub.h
+@@ -0,0 +1,364 @@
++/*
++ * Memory pools library, Public interface
++ *
++ * API Overview
++ *
++ * This package provides a memory allocation subsystem based on pools of
++ * homogenous objects.
++ *
++ * Instrumentation is available for reporting memory utilization both
++ * on a per-data-structure basis and system wide.
++ *
++ * There are two main types defined in this API.
++ *
++ *    pool manager: A singleton object that acts as a factory for
++ *                  pool allocators. It also is used for global
++ *                  instrumentation, such as reporting all blocks
++ *                  in use across all data structures. The pool manager
++ *                  creates and provides individual memory pools
++ *                  upon request to application code.
++ *
++ *    memory pool:  An object for allocating homogenous memory blocks.
++ *
++ * Global identifiers in this module use the following prefixes:
++ *    bcm_mpm_*     Memory pool manager
++ *    bcm_mp_*      Memory pool
++ *
++ * There are two main types of memory pools:
++ *
++ *    prealloc: The contiguous memory block of objects can either be supplied
++ *              by the client or malloc'ed by the memory manager. The objects are
++ *              allocated out of a block of memory and freed back to the block.
++ *
++ *    heap:     The memory pool allocator uses the heap (malloc/free) for memory.
++ *              In this case, the pool allocator is just providing statistics
++ *              and instrumentation on top of the heap, without modifying the heap
++ *              allocation implementation.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcm_mpool_pub.h 535090 2015-02-17 04:49:01Z $
++ */
++
++#ifndef _BCM_MPOOL_PUB_H
++#define _BCM_MPOOL_PUB_H 1
++
++#include <typedefs.h> /* needed for uint16 */
++
++
++/*
++**************************************************************************
++*
++* Type definitions, handles
++*
++**************************************************************************
++*/
++
++/* Forward declaration of OSL handle. */
++struct osl_info;
++
++/* Forward declaration of string buffer. */
++struct bcmstrbuf;
++
++/*
++ * Opaque type definition for the pool manager handle. This object is used for global
++ * memory pool operations such as obtaining a new pool, deleting a pool, iterating and
++ * instrumentation/debugging.
++ */
++struct bcm_mpm_mgr;
++typedef struct bcm_mpm_mgr *bcm_mpm_mgr_h;
++
++/*
++ * Opaque type definition for an instance of a pool. This handle is used for allocating
++ * and freeing memory through the pool, as well as management/instrumentation on this
++ * specific pool.
++ */
++struct bcm_mp_pool;
++typedef struct bcm_mp_pool *bcm_mp_pool_h;
++
++
++/*
++ * To make instrumentation more readable, every memory
++ * pool must have a readable name. Pool names are up to
++ * 8 bytes including '\0' termination. (7 printable characters.)
++ */
++#define BCM_MP_NAMELEN 8
++
++
++/*
++ * Type definition for pool statistics.
++ */
++typedef struct bcm_mp_stats {
++	char name[BCM_MP_NAMELEN];  /* Name of this pool. */
++	unsigned int objsz;         /* Object size allocated in this pool */
++	uint16 nobj;                /* Total number of objects in this pool */
++	uint16 num_alloc;           /* Number of objects currently allocated */
++	uint16 high_water;          /* Max number of allocated objects. */
++	uint16 failed_alloc;        /* Failed allocations. */
++} bcm_mp_stats_t;
++
++
++/*
++**************************************************************************
++*
++* API Routines on the pool manager.
++*
++**************************************************************************
++*/
++
++/*
++ * bcm_mpm_init() - initialize the whole memory pool system.
++ *
++ * Parameters:
++ *    osh:       INPUT  Operating system handle. Needed for heap memory allocation.
++ *    max_pools: INPUT Maximum number of mempools supported.
++ *    mgr:       OUTPUT The handle is written with the new pools manager object/handle.
++ *
++ * Returns:
++ *    BCME_OK     Object initialized successfully. May be used.
++ *    BCME_NOMEM  Initialization failed due to no memory. Object must not be used.
++ */
++int bcm_mpm_init(struct osl_info *osh, int max_pools, bcm_mpm_mgr_h *mgrp);
++
++
++/*
++ * bcm_mpm_deinit() - de-initialize the whole memory pool system.
++ *
++ * Parameters:
++ *    mgr:     INPUT  Pointer to pool manager handle.
++ *
++ * Returns:
++ *    BCME_OK  Memory pool manager successfully de-initialized.
++ *    other    Indicated error occured during de-initialization.
++ */
++int bcm_mpm_deinit(bcm_mpm_mgr_h *mgrp);
++
++/*
++ * bcm_mpm_create_prealloc_pool() - Create a new pool for fixed size objects. The
++ *                                  pool uses a contiguous block of pre-alloced
++ *                                  memory. The memory block may either be provided
++ *                                  by the client or dynamically allocated by the
++ *                                  pool manager.
++ *
++ * Parameters:
++ *    mgr:      INPUT  The handle to the pool manager
++ *    obj_sz:   INPUT  Size of objects that will be allocated by the new pool
++ *                     Must be >= sizeof(void *).
++ *    nobj:     INPUT  Maximum number of concurrently existing objects to support
++ *    memstart  INPUT  Pointer to the memory to use, or NULL to malloc()
++ *    memsize   INPUT  Number of bytes referenced from memstart (for error checking).
++ *                     Must be 0 if 'memstart' is NULL.
++ *    poolname  INPUT  For instrumentation, the name of the pool
++ *    newp:     OUTPUT The handle for the new pool, if creation is successful
++ *
++ * Returns:
++ *    BCME_OK   Pool created ok.
++ *    other     Pool not created due to indicated error. newpoolp set to NULL.
++ *
++ *
++ */
++int bcm_mpm_create_prealloc_pool(bcm_mpm_mgr_h mgr,
++                                 unsigned int obj_sz,
++                                 int nobj,
++                                 void *memstart,
++                                 unsigned int memsize,
++                                 const char poolname[BCM_MP_NAMELEN],
++                                 bcm_mp_pool_h *newp);
++
++
++/*
++ * bcm_mpm_delete_prealloc_pool() - Delete a memory pool. This should only be called after
++ *                                  all memory objects have been freed back to the pool.
++ *
++ * Parameters:
++ *    mgr:     INPUT The handle to the pools manager
++ *    pool:    INPUT The handle of the  pool to delete
++ *
++ * Returns:
++ *    BCME_OK   Pool deleted ok.
++ *    other     Pool not deleted due to indicated error.
++ *
++ */
++int bcm_mpm_delete_prealloc_pool(bcm_mpm_mgr_h mgr, bcm_mp_pool_h *poolp);
++
++/*
++ * bcm_mpm_create_heap_pool() - Create a new pool for fixed size objects. The memory
++ *                              pool allocator uses the heap (malloc/free) for memory.
++ *                              In this case, the pool allocator is just providing
++ *                              statistics and instrumentation on top of the heap,
++ *                              without modifying the heap allocation implementation.
++ *
++ * Parameters:
++ *    mgr:      INPUT  The handle to the pool manager
++ *    obj_sz:   INPUT  Size of objects that will be allocated by the new pool
++ *    poolname  INPUT  For instrumentation, the name of the pool
++ *    newp:     OUTPUT The handle for the new pool, if creation is successful
++ *
++ * Returns:
++ *    BCME_OK   Pool created ok.
++ *    other     Pool not created due to indicated error. newpoolp set to NULL.
++ *
++ *
++ */
++int bcm_mpm_create_heap_pool(bcm_mpm_mgr_h mgr, unsigned int obj_sz,
++                             const char poolname[BCM_MP_NAMELEN],
++                             bcm_mp_pool_h *newp);
++
++
++/*
++ * bcm_mpm_delete_heap_pool() - Delete a memory pool. This should only be called after
++ *                              all memory objects have been freed back to the pool.
++ *
++ * Parameters:
++ *    mgr:     INPUT The handle to the pools manager
++ *    pool:    INPUT The handle of the  pool to delete
++ *
++ * Returns:
++ *    BCME_OK   Pool deleted ok.
++ *    other     Pool not deleted due to indicated error.
++ *
++ */
++int bcm_mpm_delete_heap_pool(bcm_mpm_mgr_h mgr, bcm_mp_pool_h *poolp);
++
++
++/*
++ * bcm_mpm_stats() - Return stats for all pools
++ *
++ * Parameters:
++ *    mgr:         INPUT   The handle to the pools manager
++ *    stats:       OUTPUT  Array of pool statistics.
++ *    nentries:    MOD     Max elements in 'stats' array on INPUT. Actual number
++ *                         of array elements copied to 'stats' on OUTPUT.
++ *
++ * Returns:
++ *    BCME_OK   Ok
++ *    other     Error getting stats.
++ *
++ */
++int bcm_mpm_stats(bcm_mpm_mgr_h mgr, bcm_mp_stats_t *stats, int *nentries);
++
++
++/*
++ * bcm_mpm_dump() - Display statistics on all pools
++ *
++ * Parameters:
++ *    mgr:     INPUT  The handle to the pools manager
++ *    b:       OUTPUT Output buffer.
++ *
++ * Returns:
++ *    BCME_OK   Ok
++ *    other     Error during dump.
++ *
++ */
++int bcm_mpm_dump(bcm_mpm_mgr_h mgr, struct bcmstrbuf *b);
++
++
++/*
++ * bcm_mpm_get_obj_size() - The size of memory objects may need to be padded to
++ *                          compensate for alignment requirements of the objects.
++ *                          This function provides the padded object size. If clients
++ *                          pre-allocate a memory slab for a memory pool, the
++ *                          padded object size should be used by the client to allocate
++ *                          the memory slab (in order to provide sufficent space for
++ *                          the maximum number of objects).
++ *
++ * Parameters:
++ *    mgr:            INPUT   The handle to the pools manager.
++ *    obj_sz:         INPUT   Input object size.
++ *    padded_obj_sz:  OUTPUT  Padded object size.
++ *
++ * Returns:
++ *    BCME_OK      Ok
++ *    BCME_BADARG  Bad arguments.
++ *
++ */
++int bcm_mpm_get_obj_size(bcm_mpm_mgr_h mgr, unsigned int obj_sz, unsigned int *padded_obj_sz);
++
++
++/*
++***************************************************************************
++*
++* API Routines on a specific pool.
++*
++***************************************************************************
++*/
++
++
++/*
++ * bcm_mp_alloc() - Allocate a memory pool object.
++ *
++ * Parameters:
++ *    pool:    INPUT    The handle to the pool.
++ *
++ * Returns:
++ *    A pointer to the new object. NULL on error.
++ *
++ */
++void* bcm_mp_alloc(bcm_mp_pool_h pool);
++
++/*
++ * bcm_mp_free() - Free a memory pool object.
++ *
++ * Parameters:
++ *    pool:  INPUT   The handle to the pool.
++ *    objp:  INPUT   A pointer to the object to free.
++ *
++ * Returns:
++ *    BCME_OK   Ok
++ *    other     Error during free.
++ *
++ */
++int bcm_mp_free(bcm_mp_pool_h pool, void *objp);
++
++/*
++ * bcm_mp_stats() - Return stats for this pool
++ *
++ * Parameters:
++ *    pool:     INPUT    The handle to the pool
++ *    stats:    OUTPUT   Pool statistics
++ *
++ * Returns:
++ *    BCME_OK   Ok
++ *    other     Error getting statistics.
++ *
++ */
++void bcm_mp_stats(bcm_mp_pool_h pool, bcm_mp_stats_t *stats);
++
++
++/*
++ * bcm_mp_dump() - Dump a pool
++ *
++ * Parameters:
++ *    pool:    INPUT    The handle to the pool
++ *    b        OUTPUT   Output buffer
++ *
++ * Returns:
++ *    BCME_OK   Ok
++ *    other     Error during dump.
++ *
++ */
++int bcm_mp_dump(bcm_mp_pool_h pool, struct bcmstrbuf *b);
++
++
++#endif /* _BCM_MPOOL_PUB_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcm_ring.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcm_ring.h
+new file mode 100644
+index 000000000..721d7eab6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcm_ring.h
+@@ -0,0 +1,634 @@
++/*
++ * bcm_ring.h : Ring context abstraction
++ * The ring context tracks the WRITE and READ indices where elements may be
++ * produced and consumed respectively. All elements in the ring need to be
++ * fixed size.
++ *
++ * NOTE: A ring of size N, may only hold N-1 elements.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcm_ring.h 596126 2015-10-29 19:53:48Z $
++ */
++#ifndef __bcm_ring_included__
++#define __bcm_ring_included__
++/*
++ * API Notes:
++ *
++ * Ring manipulation API allows for:
++ *  Pending operations: Often before some work can be completed, it may be
++ *  desired that several resources are available, e.g. space for production in
++ *  a ring. Approaches such as, #1) reserve resources one by one and return them
++ *  if another required resource is not available, or #2) employ a two pass
++ *  algorithm of first testing whether all resources are available, have a
++ *  an impact on performance critical code. The approach taken here is more akin
++ *  to approach #2, where a test for resource availability essentially also
++ *  provides the index for production in an un-committed state.
++ *  The same approach is taken for the consumer side.
++ *
++ *  - Pending production: Fetch the next index where a ring element may be
++ *    produced. The caller may not commit the WRITE of the element.
++ *  - Pending consumption: Fetch the next index where a ring element may be
++ *    consumed. The caller may not commut the READ of the element.
++ *
++ *  Producer side API:
++ *  - bcm_ring_is_full  : Test whether ring is full
++ *  - bcm_ring_prod     : Fetch index where an element may be produced (commit)
++ *  - bcm_ring_prod_pend: Fetch index where an element may be produced (pending)
++ *  - bcm_ring_prod_done: Commit a previous pending produce fetch
++ *  - bcm_ring_prod_avail: Fetch total number free slots eligible for production
++ *
++ * Consumer side API:
++ *  - bcm_ring_is_empty : Test whether ring is empty
++ *  - bcm_ring_cons     : Fetch index where an element may be consumed (commit)
++ *  - bcm_ring_cons_pend: Fetch index where an element may be consumed (pending)
++ *  - bcm_ring_cons_done: Commit a previous pending consume fetch
++ *  - bcm_ring_cons_avail: Fetch total number elements eligible for consumption
++ *
++ *  - bcm_ring_sync_read: Sync read offset in peer ring, from local ring
++ *  - bcm_ring_sync_write: Sync write offset in peer ring, from local ring
++ *
++ * +----------------------------------------------------------------------------
++ *
++ * Design Notes:
++ * Following items are not tracked in a ring context (design decision)
++ *  - width of a ring element.
++ *  - depth of the ring.
++ *  - base of the buffer, where the elements are stored.
++ *  - count of number of free slots in the ring
++ *
++ * Implementation Notes:
++ *  - When BCM_RING_DEBUG is enabled, need explicit bcm_ring_init().
++ *  - BCM_RING_EMPTY and BCM_RING_FULL are (-1)
++ *
++ * +----------------------------------------------------------------------------
++ *
++ * Usage Notes:
++ * An application may incarnate a ring of some fixed sized elements, by defining
++ *  - a ring data buffer to store the ring elements.
++ *  - depth of the ring (max number of elements managed by ring context).
++ *    Preferrably, depth may be represented as a constant.
++ *  - width of a ring element: to be used in pointer arithmetic with the ring's
++ *    data buffer base and an index to fetch the ring element.
++ *
++ * Use bcm_workq_t to instantiate a pair of workq constructs, one for the
++ * producer and the other for the consumer, both pointing to the same circular
++ * buffer. The producer may operate on it's own local workq and flush the write
++ * index to the consumer. Likewise the consumer may use its local workq and
++ * flush the read index to the producer. This way we do not repeatedly access
++ * the peer's context. The two peers may reside on different CPU cores with a
++ * private L1 data cache.
++ * +----------------------------------------------------------------------------
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * $Id: bcm_ring.h 596126 2015-10-29 19:53:48Z $
++ *
++ * -*- Mode: C; tab-width: 4; indent-tabs-mode: t; c-basic-offset: 4 -*-
++ * vim: set ts=4 noet sw=4 tw=80:
++ *
++ * +----------------------------------------------------------------------------
++ */
++
++#ifdef ____cacheline_aligned
++#define __ring_aligned                      ____cacheline_aligned
++#else
++#define __ring_aligned
++#endif
++
++/* Conditional compile for debug */
++/* #define BCM_RING_DEBUG */
++
++#define BCM_RING_EMPTY                      (-1)
++#define BCM_RING_FULL                       (-1)
++#define BCM_RING_NULL                       ((bcm_ring_t *)NULL)
++
++#if defined(BCM_RING_DEBUG)
++#define RING_ASSERT(exp)                    ASSERT(exp)
++#define BCM_RING_IS_VALID(ring)             (((ring) != BCM_RING_NULL) && \
++	                                         ((ring)->self == (ring)))
++#else  /* ! BCM_RING_DEBUG */
++#define RING_ASSERT(exp)                    do {} while (0)
++#define BCM_RING_IS_VALID(ring)             ((ring) != BCM_RING_NULL)
++#endif /* ! BCM_RING_DEBUG */
++
++#define BCM_RING_SIZE_IS_VALID(ring_size)   ((ring_size) > 0)
++
++/*
++ * +----------------------------------------------------------------------------
++ * Ring Context
++ * +----------------------------------------------------------------------------
++ */
++typedef struct bcm_ring {     /* Ring context */
++#if defined(BCM_RING_DEBUG)
++	struct bcm_ring *self;    /* ptr to self for IS VALID test */
++#endif /* BCM_RING_DEBUG */
++	int write __ring_aligned; /* WRITE index in a circular ring */
++	int read  __ring_aligned; /* READ index in a circular ring */
++} bcm_ring_t;
++
++
++static INLINE void bcm_ring_init(bcm_ring_t *ring);
++static INLINE void bcm_ring_copy(bcm_ring_t *to, bcm_ring_t *from);
++static INLINE bool bcm_ring_is_empty(bcm_ring_t *ring);
++
++static INLINE int  __bcm_ring_next_write(bcm_ring_t *ring, const int ring_size);
++
++static INLINE bool __bcm_ring_full(bcm_ring_t *ring, int next_write);
++static INLINE bool bcm_ring_is_full(bcm_ring_t *ring, const int ring_size);
++
++static INLINE void bcm_ring_prod_done(bcm_ring_t *ring, int write);
++static INLINE int  bcm_ring_prod_pend(bcm_ring_t *ring, int *pend_write,
++                                      const int ring_size);
++static INLINE int  bcm_ring_prod(bcm_ring_t *ring, const int ring_size);
++
++static INLINE void bcm_ring_cons_done(bcm_ring_t *ring, int read);
++static INLINE int  bcm_ring_cons_pend(bcm_ring_t *ring, int *pend_read,
++                                      const int ring_size);
++static INLINE int  bcm_ring_cons(bcm_ring_t *ring, const int ring_size);
++
++static INLINE void bcm_ring_sync_read(bcm_ring_t *peer, const bcm_ring_t *self);
++static INLINE void bcm_ring_sync_write(bcm_ring_t *peer, const bcm_ring_t *self);
++
++static INLINE int  bcm_ring_prod_avail(const bcm_ring_t *ring,
++                                       const int ring_size);
++static INLINE int  bcm_ring_cons_avail(const bcm_ring_t *ring,
++                                       const int ring_size);
++static INLINE void bcm_ring_cons_all(bcm_ring_t *ring);
++
++
++/**
++ * bcm_ring_init - initialize a ring context.
++ * @ring: pointer to a ring context
++ */
++static INLINE void
++bcm_ring_init(bcm_ring_t *ring)
++{
++	ASSERT(ring != (bcm_ring_t *)NULL);
++#if defined(BCM_RING_DEBUG)
++	ring->self = ring;
++#endif /* BCM_RING_DEBUG */
++	ring->write = 0;
++	ring->read = 0;
++}
++
++/**
++ * bcm_ring_copy - copy construct a ring
++ * @to: pointer to the new ring context
++ * @from: pointer to orig ring context
++ */
++static INLINE void
++bcm_ring_copy(bcm_ring_t *to, bcm_ring_t *from)
++{
++	bcm_ring_init(to);
++
++	to->write = from->write;
++	to->read  = from->read;
++}
++
++/**
++ * bcm_ring_is_empty - "Boolean" test whether ring is empty.
++ * @ring: pointer to a ring context
++ *
++ * PS. does not return BCM_RING_EMPTY value.
++ */
++static INLINE bool
++bcm_ring_is_empty(bcm_ring_t *ring)
++{
++	RING_ASSERT(BCM_RING_IS_VALID(ring));
++	return (ring->read == ring->write);
++}
++
++
++/**
++ * __bcm_ring_next_write - determine the index where the next write may occur
++ *                         (with wrap-around).
++ * @ring: pointer to a ring context
++ * @ring_size: size of the ring
++ *
++ * PRIVATE INTERNAL USE ONLY.
++ */
++static INLINE int
++__bcm_ring_next_write(bcm_ring_t *ring, const int ring_size)
++{
++	RING_ASSERT(BCM_RING_IS_VALID(ring) && BCM_RING_SIZE_IS_VALID(ring_size));
++	return ((ring->write + 1) % ring_size);
++}
++
++
++/**
++ * __bcm_ring_full - support function for ring full test.
++ * @ring: pointer to a ring context
++ * @next_write: next location in ring where an element is to be produced
++ *
++ * PRIVATE INTERNAL USE ONLY.
++ */
++static INLINE bool
++__bcm_ring_full(bcm_ring_t *ring, int next_write)
++{
++	return (next_write == ring->read);
++}
++
++
++/**
++ * bcm_ring_is_full - "Boolean" test whether a ring is full.
++ * @ring: pointer to a ring context
++ * @ring_size: size of the ring
++ *
++ * PS. does not return BCM_RING_FULL value.
++ */
++static INLINE bool
++bcm_ring_is_full(bcm_ring_t *ring, const int ring_size)
++{
++	int next_write;
++	RING_ASSERT(BCM_RING_IS_VALID(ring) && BCM_RING_SIZE_IS_VALID(ring_size));
++	next_write = __bcm_ring_next_write(ring, ring_size);
++	return __bcm_ring_full(ring, next_write);
++}
++
++
++/**
++ * bcm_ring_prod_done - commit a previously pending index where production
++ * was requested.
++ * @ring: pointer to a ring context
++ * @write: index into ring upto where production was done.
++ * +----------------------------------------------------------------------------
++ */
++static INLINE void
++bcm_ring_prod_done(bcm_ring_t *ring, int write)
++{
++	RING_ASSERT(BCM_RING_IS_VALID(ring));
++	ring->write = write;
++}
++
++
++/**
++ * bcm_ring_prod_pend - Fetch in "pend" mode, the index where an element may be
++ * produced.
++ * @ring: pointer to a ring context
++ * @pend_write: next index, after the returned index
++ * @ring_size: size of the ring
++ */
++static INLINE int
++bcm_ring_prod_pend(bcm_ring_t *ring, int *pend_write, const int ring_size)
++{
++	int rtn;
++	RING_ASSERT(BCM_RING_IS_VALID(ring) && BCM_RING_SIZE_IS_VALID(ring_size));
++	*pend_write = __bcm_ring_next_write(ring, ring_size);
++	if (__bcm_ring_full(ring, *pend_write)) {
++		*pend_write = BCM_RING_FULL;
++		rtn = BCM_RING_FULL;
++	} else {
++		/* production is not committed, caller needs to explicitly commit */
++		rtn = ring->write;
++	}
++	return rtn;
++}
++
++
++/**
++ * bcm_ring_prod - Fetch and "commit" the next index where a ring element may
++ * be produced.
++ * @ring: pointer to a ring context
++ * @ring_size: size of the ring
++ */
++static INLINE int
++bcm_ring_prod(bcm_ring_t *ring, const int ring_size)
++{
++	int next_write, prod_write;
++	RING_ASSERT(BCM_RING_IS_VALID(ring) && BCM_RING_SIZE_IS_VALID(ring_size));
++
++	next_write = __bcm_ring_next_write(ring, ring_size);
++	if (__bcm_ring_full(ring, next_write)) {
++		prod_write = BCM_RING_FULL;
++	} else {
++		prod_write = ring->write;
++		bcm_ring_prod_done(ring, next_write); /* "commit" production */
++	}
++	return prod_write;
++}
++
++
++/**
++ * bcm_ring_cons_done - commit a previously pending read
++ * @ring: pointer to a ring context
++ * @read: index upto which elements have been consumed.
++ */
++static INLINE void
++bcm_ring_cons_done(bcm_ring_t *ring, int read)
++{
++	RING_ASSERT(BCM_RING_IS_VALID(ring));
++	ring->read = read;
++}
++
++
++/**
++ * bcm_ring_cons_pend - fetch in "pend" mode, the next index where a ring
++ * element may be consumed.
++ * @ring: pointer to a ring context
++ * @pend_read: index into ring upto which elements may be consumed.
++ * @ring_size: size of the ring
++ */
++static INLINE int
++bcm_ring_cons_pend(bcm_ring_t *ring, int *pend_read, const int ring_size)
++{
++	int rtn;
++	RING_ASSERT(BCM_RING_IS_VALID(ring) && BCM_RING_SIZE_IS_VALID(ring_size));
++	if (bcm_ring_is_empty(ring)) {
++		*pend_read = BCM_RING_EMPTY;
++		rtn = BCM_RING_EMPTY;
++	} else {
++		*pend_read = (ring->read + 1) % ring_size;
++		/* production is not committed, caller needs to explicitly commit */
++		rtn = ring->read;
++	}
++	return rtn;
++}
++
++
++/**
++ * bcm_ring_cons - fetch and "commit" the next index where a ring element may
++ * be consumed.
++ * @ring: pointer to a ring context
++ * @ring_size: size of the ring
++ */
++static INLINE int
++bcm_ring_cons(bcm_ring_t *ring, const int ring_size)
++{
++	int cons_read;
++	RING_ASSERT(BCM_RING_IS_VALID(ring) && BCM_RING_SIZE_IS_VALID(ring_size));
++	if (bcm_ring_is_empty(ring)) {
++		cons_read = BCM_RING_EMPTY;
++	} else {
++		cons_read = ring->read;
++		ring->read = (ring->read + 1) % ring_size; /* read is committed */
++	}
++	return cons_read;
++}
++
++
++/**
++ * bcm_ring_sync_read - on consumption, update peer's read index.
++ * @peer: pointer to peer's producer ring context
++ * @self: pointer to consumer's ring context
++ */
++static INLINE void
++bcm_ring_sync_read(bcm_ring_t *peer, const bcm_ring_t *self)
++{
++	RING_ASSERT(BCM_RING_IS_VALID(peer));
++	RING_ASSERT(BCM_RING_IS_VALID(self));
++	peer->read = self->read; /* flush read update to peer producer */
++}
++
++
++/**
++ * bcm_ring_sync_write - on consumption, update peer's write index.
++ * @peer: pointer to peer's consumer ring context
++ * @self: pointer to producer's ring context
++ */
++static INLINE void
++bcm_ring_sync_write(bcm_ring_t *peer, const bcm_ring_t *self)
++{
++	RING_ASSERT(BCM_RING_IS_VALID(peer));
++	RING_ASSERT(BCM_RING_IS_VALID(self));
++	peer->write = self->write; /* flush write update to peer consumer */
++}
++
++
++/**
++ * bcm_ring_prod_avail - fetch total number of available empty slots in the
++ * ring for production.
++ * @ring: pointer to a ring context
++ * @ring_size: size of the ring
++ */
++static INLINE int
++bcm_ring_prod_avail(const bcm_ring_t *ring, const int ring_size)
++{
++	int prod_avail;
++	RING_ASSERT(BCM_RING_IS_VALID(ring) && BCM_RING_SIZE_IS_VALID(ring_size));
++	if (ring->write >= ring->read) {
++		prod_avail = (ring_size - (ring->write - ring->read) - 1);
++	} else {
++		prod_avail = (ring->read - (ring->write + 1));
++	}
++	ASSERT(prod_avail < ring_size);
++	return prod_avail;
++}
++
++
++/**
++ * bcm_ring_cons_avail - fetch total number of available elements for consumption.
++ * @ring: pointer to a ring context
++ * @ring_size: size of the ring
++ */
++static INLINE int
++bcm_ring_cons_avail(const bcm_ring_t *ring, const int ring_size)
++{
++	int cons_avail;
++	RING_ASSERT(BCM_RING_IS_VALID(ring) && BCM_RING_SIZE_IS_VALID(ring_size));
++	if (ring->read == ring->write) {
++		cons_avail = 0;
++	} else if (ring->read > ring->write) {
++		cons_avail = ((ring_size - ring->read) + ring->write);
++	} else {
++		cons_avail = ring->write - ring->read;
++	}
++	ASSERT(cons_avail < ring_size);
++	return cons_avail;
++}
++
++
++/**
++ * bcm_ring_cons_all - set ring in state where all elements are consumed.
++ * @ring: pointer to a ring context
++ */
++static INLINE void
++bcm_ring_cons_all(bcm_ring_t *ring)
++{
++	ring->read = ring->write;
++}
++
++
++/**
++ * Work Queue
++ * A work Queue is composed of a ring of work items, of a specified depth.
++ * It HAS-A bcm_ring object, comprising of a RD and WR offset, to implement a
++ * producer/consumer circular ring.
++ */
++
++struct bcm_workq {
++	bcm_ring_t ring;        /* Ring context abstraction */
++	struct bcm_workq *peer; /* Peer workq context */
++	void       *buffer;     /* Buffer storage for work items in workQ */
++	int        ring_size;   /* Depth of workQ */
++} __ring_aligned;
++
++typedef struct bcm_workq bcm_workq_t;
++
++
++/* #define BCM_WORKQ_DEBUG */
++#if defined(BCM_WORKQ_DEBUG)
++#define WORKQ_ASSERT(exp)               ASSERT(exp)
++#else  /* ! BCM_WORKQ_DEBUG */
++#define WORKQ_ASSERT(exp)               do {} while (0)
++#endif /* ! BCM_WORKQ_DEBUG */
++
++#define WORKQ_AUDIT(workq) \
++	WORKQ_ASSERT((workq) != BCM_WORKQ_NULL); \
++	WORKQ_ASSERT(WORKQ_PEER(workq) != BCM_WORKQ_NULL); \
++	WORKQ_ASSERT((workq)->buffer == WORKQ_PEER(workq)->buffer); \
++	WORKQ_ASSERT((workq)->ring_size == WORKQ_PEER(workq)->ring_size);
++
++#define BCM_WORKQ_NULL                  ((bcm_workq_t *)NULL)
++
++#define WORKQ_PEER(workq)               ((workq)->peer)
++#define WORKQ_RING(workq)               (&((workq)->ring))
++#define WORKQ_PEER_RING(workq)          (&((workq)->peer->ring))
++
++#define WORKQ_ELEMENT(__elem_type, __workq, __index) ({ \
++	WORKQ_ASSERT((__workq) != BCM_WORKQ_NULL); \
++	WORKQ_ASSERT((__index) < ((__workq)->ring_size)); \
++	((__elem_type *)((__workq)->buffer)) + (__index); \
++})
++
++
++static INLINE void bcm_workq_init(bcm_workq_t *workq, bcm_workq_t *workq_peer,
++                                  void *buffer, int ring_size);
++
++static INLINE bool bcm_workq_is_empty(bcm_workq_t *workq_prod);
++
++static INLINE void bcm_workq_prod_sync(bcm_workq_t *workq_prod);
++static INLINE void bcm_workq_cons_sync(bcm_workq_t *workq_cons);
++
++static INLINE void bcm_workq_prod_refresh(bcm_workq_t *workq_prod);
++static INLINE void bcm_workq_cons_refresh(bcm_workq_t *workq_cons);
++
++/**
++ * bcm_workq_init - initialize a workq
++ * @workq: pointer to a workq context
++ * @buffer: pointer to a pre-allocated circular buffer to serve as a ring
++ * @ring_size: size of the ring in terms of max number of elements.
++ */
++static INLINE void
++bcm_workq_init(bcm_workq_t *workq, bcm_workq_t *workq_peer,
++               void *buffer, int ring_size)
++{
++	ASSERT(workq != BCM_WORKQ_NULL);
++	ASSERT(workq_peer != BCM_WORKQ_NULL);
++	ASSERT(buffer != NULL);
++	ASSERT(ring_size > 0);
++
++	WORKQ_PEER(workq) = workq_peer;
++	WORKQ_PEER(workq_peer) = workq;
++
++	bcm_ring_init(WORKQ_RING(workq));
++	bcm_ring_init(WORKQ_RING(workq_peer));
++
++	workq->buffer = workq_peer->buffer = buffer;
++	workq->ring_size = workq_peer->ring_size = ring_size;
++}
++
++/**
++ * bcm_workq_empty - test whether there is work
++ * @workq_prod: producer's workq
++ */
++static INLINE bool
++bcm_workq_is_empty(bcm_workq_t *workq_prod)
++{
++	return bcm_ring_is_empty(WORKQ_RING(workq_prod));
++}
++
++/**
++ * bcm_workq_prod_sync - Commit the producer write index to peer workq's ring
++ * @workq_prod: producer's workq whose write index must be synced to peer
++ */
++static INLINE void
++bcm_workq_prod_sync(bcm_workq_t *workq_prod)
++{
++	WORKQ_AUDIT(workq_prod);
++
++	/* cons::write <--- prod::write */
++	bcm_ring_sync_write(WORKQ_PEER_RING(workq_prod), WORKQ_RING(workq_prod));
++}
++
++/**
++ * bcm_workq_cons_sync - Commit the consumer read index to the peer workq's ring
++ * @workq_cons: consumer's workq whose read index must be synced to peer
++ */
++static INLINE void
++bcm_workq_cons_sync(bcm_workq_t *workq_cons)
++{
++	WORKQ_AUDIT(workq_cons);
++
++	/* prod::read <--- cons::read */
++	bcm_ring_sync_read(WORKQ_PEER_RING(workq_cons), WORKQ_RING(workq_cons));
++}
++
++
++/**
++ * bcm_workq_prod_refresh - Fetch the updated consumer's read index
++ * @workq_prod: producer's workq whose read index must be refreshed from peer
++ */
++static INLINE void
++bcm_workq_prod_refresh(bcm_workq_t *workq_prod)
++{
++	WORKQ_AUDIT(workq_prod);
++
++	/* prod::read <--- cons::read */
++	bcm_ring_sync_read(WORKQ_RING(workq_prod), WORKQ_PEER_RING(workq_prod));
++}
++
++/**
++ * bcm_workq_cons_refresh - Fetch the updated producer's write index
++ * @workq_cons: consumer's workq whose write index must be refreshed from peer
++ */
++static INLINE void
++bcm_workq_cons_refresh(bcm_workq_t *workq_cons)
++{
++	WORKQ_AUDIT(workq_cons);
++
++	/* cons::write <--- prod::write */
++	bcm_ring_sync_write(WORKQ_RING(workq_cons), WORKQ_PEER_RING(workq_cons));
++}
++
++
++#endif /* ! __bcm_ring_h_included__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmcdc.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmcdc.h
+new file mode 100644
+index 000000000..22fd8a093
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmcdc.h
+@@ -0,0 +1,135 @@
++/*
++ * CDC network driver ioctl/indication encoding
++ * Broadcom 802.11abg Networking Device Driver
++ *
++ * Definitions subject to change without notice.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmcdc.h 676811 2016-12-24 20:48:46Z $
++ */
++#ifndef _bcmcdc_h_
++#define	_bcmcdc_h_
++#include <ethernet.h>
++
++typedef struct cdc_ioctl {
++	uint32 cmd;      /* ioctl command value */
++	uint32 len;      /* lower 16: output buflen; upper 16: input buflen (excludes header) */
++	uint32 flags;    /* flag defns given below */
++	uint32 status;   /* status code returned from the device */
++} cdc_ioctl_t;
++
++/* Max valid buffer size that can be sent to the dongle */
++#define CDC_MAX_MSG_SIZE   ETHER_MAX_LEN
++
++/* len field is divided into input and output buffer lengths */
++#define CDCL_IOC_OUTLEN_MASK   0x0000FFFF  /* maximum or expected response length, */
++					   /* excluding IOCTL header */
++#define CDCL_IOC_OUTLEN_SHIFT  0
++#define CDCL_IOC_INLEN_MASK    0xFFFF0000   /* input buffer length, excluding IOCTL header */
++#define CDCL_IOC_INLEN_SHIFT   16
++
++/* CDC flag definitions */
++#define CDCF_IOC_ERROR		0x01	/* 0=success, 1=ioctl cmd failed */
++#define CDCF_IOC_SET		0x02	/* 0=get, 1=set cmd */
++#define CDCF_IOC_OVL_IDX_MASK	0x3c	/* overlay region index mask */
++#define CDCF_IOC_OVL_RSV	0x40	/* 1=reserve this overlay region */
++#define CDCF_IOC_OVL		0x80	/* 1=this ioctl corresponds to an overlay */
++#define CDCF_IOC_ACTION_MASK	0xfe	/* SET/GET, OVL_IDX, OVL_RSV, OVL mask */
++#define CDCF_IOC_ACTION_SHIFT	1	/* SET/GET, OVL_IDX, OVL_RSV, OVL shift */
++#define CDCF_IOC_IF_MASK	0xF000	/* I/F index */
++#define CDCF_IOC_IF_SHIFT	12
++#define CDCF_IOC_ID_MASK	0xFFFF0000	/* used to uniquely id an ioctl req/resp pairing */
++#define CDCF_IOC_ID_SHIFT	16		/* # of bits of shift for ID Mask */
++
++#define CDC_IOC_IF_IDX(flags)	(((flags) & CDCF_IOC_IF_MASK) >> CDCF_IOC_IF_SHIFT)
++#define CDC_IOC_ID(flags)	(((flags) & CDCF_IOC_ID_MASK) >> CDCF_IOC_ID_SHIFT)
++
++#define CDC_GET_IF_IDX(hdr) \
++	((int)((((hdr)->flags) & CDCF_IOC_IF_MASK) >> CDCF_IOC_IF_SHIFT))
++#define CDC_SET_IF_IDX(hdr, idx) \
++	((hdr)->flags = (((hdr)->flags & ~CDCF_IOC_IF_MASK) | ((idx) << CDCF_IOC_IF_SHIFT)))
++
++/*
++ * BDC header
++ *
++ *   The BDC header is used on data packets to convey priority across USB.
++ */
++
++struct bdc_header {
++	uint8	flags;			/* Flags */
++	uint8	priority;		/* 802.1d Priority 0:2 bits, 4:7 USB flow control info */
++	uint8	flags2;
++	uint8	dataOffset;		/* Offset from end of BDC header to packet data, in
++					 * 4-byte words.  Leaves room for optional headers.
++					 */
++};
++
++#define	BDC_HEADER_LEN		4
++
++/* flags field bitmap */
++#define BDC_FLAG_80211_PKT	0x01	/* Packet is in 802.11 format (dongle -> host) */
++#define BDC_FLAG_SUM_GOOD	0x04	/* Dongle has verified good RX checksums */
++#define BDC_FLAG_SUM_NEEDED	0x08	/* Dongle needs to do TX checksums: host->device */
++#define BDC_FLAG_EVENT_MSG	0x08	/* Payload contains an event msg: device->host */
++#define BDC_FLAG_VER_MASK	0xf0	/* Protocol version mask */
++#define BDC_FLAG_VER_SHIFT	4	/* Protocol version shift */
++
++/* priority field bitmap */
++#define BDC_PRIORITY_MASK	0x07
++#define BDC_PRIORITY_FC_MASK	0xf0	/* flow control info mask */
++#define BDC_PRIORITY_FC_SHIFT	4	/* flow control info shift */
++
++/* flags2 field bitmap */
++#define BDC_FLAG2_IF_MASK	0x0f	/* interface index (host <-> dongle) */
++#define BDC_FLAG2_IF_SHIFT	0
++#define BDC_FLAG2_FC_FLAG	0x10	/* flag to indicate if pkt contains */
++					/* FLOW CONTROL info only */
++
++/* version numbers */
++#define BDC_PROTO_VER_1		1	/* Old Protocol version */
++#define BDC_PROTO_VER		2	/* Protocol version */
++
++/* flags2.if field access macros */
++#define BDC_GET_IF_IDX(hdr) \
++	((int)((((hdr)->flags2) & BDC_FLAG2_IF_MASK) >> BDC_FLAG2_IF_SHIFT))
++#define BDC_SET_IF_IDX(hdr, idx) \
++	((hdr)->flags2 = (((hdr)->flags2 & ~BDC_FLAG2_IF_MASK) | ((idx) << BDC_FLAG2_IF_SHIFT)))
++
++#define BDC_FLAG2_PAD_MASK		0xf0
++#define BDC_FLAG_PAD_MASK		0x03
++#define BDC_FLAG2_PAD_SHIFT		2
++#define BDC_FLAG_PAD_SHIFT		0
++#define BDC_FLAG2_PAD_IDX		0x3c
++#define BDC_FLAG_PAD_IDX		0x03
++#define BDC_GET_PAD_LEN(hdr) \
++	((int)(((((hdr)->flags2) & BDC_FLAG2_PAD_MASK) >> BDC_FLAG2_PAD_SHIFT) | \
++	((((hdr)->flags) & BDC_FLAG_PAD_MASK) >> BDC_FLAG_PAD_SHIFT)))
++#define BDC_SET_PAD_LEN(hdr, idx) \
++	((hdr)->flags2 = (((hdr)->flags2 & ~BDC_FLAG2_PAD_MASK) | \
++	(((idx) & BDC_FLAG2_PAD_IDX) << BDC_FLAG2_PAD_SHIFT))); \
++	((hdr)->flags = (((hdr)->flags & ~BDC_FLAG_PAD_MASK) | \
++	(((idx) & BDC_FLAG_PAD_IDX) << BDC_FLAG_PAD_SHIFT)))
++
++#endif /* _bcmcdc_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmdefs.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmdefs.h
+new file mode 100644
+index 000000000..58cbe5e7a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmdefs.h
+@@ -0,0 +1,462 @@
++/*
++ * Misc system wide definitions
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmdefs.h 657791 2016-09-02 15:14:42Z $
++ */
++
++#ifndef	_bcmdefs_h_
++#define	_bcmdefs_h_
++
++/*
++ * One doesn't need to include this file explicitly, gets included automatically if
++ * typedefs.h is included.
++ */
++
++/* Use BCM_REFERENCE to suppress warnings about intentionally-unused function
++ * arguments or local variables.
++ */
++#define BCM_REFERENCE(data)	((void)(data))
++
++/* Allow for suppressing unused variable warnings. */
++#ifdef __GNUC__
++#define UNUSED_VAR     __attribute__ ((unused))
++#else
++#define UNUSED_VAR
++#endif
++
++/* Compile-time assert can be used in place of ASSERT if the expression evaluates
++ * to a constant at compile time.
++ */
++#define STATIC_ASSERT(expr) { \
++	/* Make sure the expression is constant. */ \
++	typedef enum { _STATIC_ASSERT_NOT_CONSTANT = (expr) } _static_assert_e UNUSED_VAR; \
++	/* Make sure the expression is true. */ \
++	typedef char STATIC_ASSERT_FAIL[(expr) ? 1 : -1] UNUSED_VAR; \
++}
++
++/* Reclaiming text and data :
++ * The following macros specify special linker sections that can be reclaimed
++ * after a system is considered 'up'.
++ * BCMATTACHFN is also used for detach functions (it's not worth having a BCMDETACHFN,
++ * as in most cases, the attach function calls the detach function to clean up on error).
++ */
++#if defined(BCM_RECLAIM)
++
++extern bool bcm_reclaimed;
++extern bool bcm_attach_part_reclaimed;
++extern bool bcm_preattach_part_reclaimed;
++
++#if defined(BCM_RECLAIM_ATTACH_FN_DATA)
++#define _data	__attribute__ ((__section__ (".dataini2." #_data))) _data
++#define _fn	__attribute__ ((__section__ (".textini2." #_fn), noinline)) _fn
++
++/* Relocate attach symbols to save-restore region to increase pre-reclaim heap size. */
++#define BCM_SRM_ATTACH_DATA(_data)    __attribute__ ((__section__ (".datasrm." #_data))) _data
++#define BCM_SRM_ATTACH_FN(_fn)        __attribute__ ((__section__ (".textsrm." #_fn), noinline)) _fn
++
++#ifndef PREATTACH_NORECLAIM
++#define BCMPREATTACHDATA(_data)	__attribute__ ((__section__ (".dataini3." #_data))) _data
++#define BCMPREATTACHFN(_fn)	__attribute__ ((__section__ (".textini3." #_fn), noinline)) _fn
++#else
++#define BCMPREATTACHDATA(_data)	__attribute__ ((__section__ (".dataini2." #_data))) _data
++#define BCMPREATTACHFN(_fn)	__attribute__ ((__section__ (".textini2." #_fn), noinline)) _fn
++#endif /* PREATTACH_NORECLAIM  */
++#else  /* BCM_RECLAIM_ATTACH_FN_DATA  */
++#define _data	_data
++#define _fn	_fn
++#define BCMPREATTACHDATA(_data)	_data
++#define BCMPREATTACHFN(_fn)	_fn
++#endif /* BCM_RECLAIM_ATTACH_FN_DATA  */
++
++#if defined(BCM_RECLAIM_INIT_FN_DATA)
++#define _data	__attribute__ ((__section__ (".dataini1." #_data))) _data
++#define _fn		__attribute__ ((__section__ (".textini1." #_fn), noinline)) _fn
++#define CONST
++#else /* BCM_RECLAIM_INIT_FN_DATA  */
++#define _data	_data
++#define _fn		_fn
++#ifndef CONST
++#define CONST	const
++#endif
++#endif /* BCM_RECLAIM_INIT_FN_DATA  */
++
++/* Non-manufacture or internal attach function/dat */
++#define	BCMNMIATTACHFN(_fn)	_fn
++#define	BCMNMIATTACHDATA(_data)	_data
++
++#ifdef BCMNODOWN
++#define _fn	_fn
++#else
++#define _fn	_fn
++#endif
++
++#else /* BCM_RECLAIM */
++
++#define bcm_reclaimed           	0
++#define _data		_data
++#define _fn		_fn
++#define BCM_SRM_ATTACH_DATA(_data)	_data
++#define BCM_SRM_ATTACH_FN(_fn)		_fn
++#define BCMPREATTACHDATA(_data)		_data
++#define BCMPREATTACHFN(_fn)		_fn
++#define _data		_data
++#define _fn			_fn
++#define _fn		_fn
++#define	BCMNMIATTACHFN(_fn)		_fn
++#define	BCMNMIATTACHDATA(_data)		_data
++#define CONST				const
++
++#endif /* BCM_RECLAIM */
++
++#if !defined STB
++#undef BCM47XX_CA9
++#endif /* STB */
++
++/* BCMFASTPATH Related Macro defines
++*/
++#ifndef BCMFASTPATH
++#if defined(STB)
++#define BCMFASTPATH		__attribute__ ((__section__ (".text.fastpath")))
++#define BCMFASTPATH_HOST	__attribute__ ((__section__ (".text.fastpath_host")))
++#else
++#define BCMFASTPATH
++#define BCMFASTPATH_HOST
++#endif
++#endif /* BCMFASTPATH */
++
++
++/* Use the BCMRAMFN() macro to tag functions in source that must be included in RAM (excluded from
++ * ROM). This should eliminate the need to manually specify these functions in the ROM config file.
++ * It should only be used in special cases where the function must be in RAM for *all* ROM-based
++ * chips.
++ */
++	#define BCMRAMFN(_fn)	_fn
++
++#define STATIC	static
++
++/* Bus types */
++#define	SI_BUS			0	/* SOC Interconnect */
++#define	PCI_BUS			1	/* PCI target */
++#define	PCMCIA_BUS		2	/* PCMCIA target */
++#define SDIO_BUS		3	/* SDIO target */
++#define JTAG_BUS		4	/* JTAG */
++#define USB_BUS			5	/* USB (does not support R/W REG) */
++#define SPI_BUS			6	/* gSPI target */
++#define RPC_BUS			7	/* RPC target */
++
++/* Allows size optimization for single-bus image */
++#ifdef BCMBUSTYPE
++#define BUSTYPE(bus)	(BCMBUSTYPE)
++#else
++#define BUSTYPE(bus)	(bus)
++#endif
++
++#ifdef BCMBUSCORETYPE
++#define BUSCORETYPE(ct)		(BCMBUSCORETYPE)
++#else
++#define BUSCORETYPE(ct)		(ct)
++#endif
++
++/* Allows size optimization for single-backplane image */
++#ifdef BCMCHIPTYPE
++#define CHIPTYPE(bus)	(BCMCHIPTYPE)
++#else
++#define CHIPTYPE(bus)	(bus)
++#endif
++
++
++/* Allows size optimization for SPROM support */
++#if defined(BCMSPROMBUS)
++#define SPROMBUS	(BCMSPROMBUS)
++#elif defined(SI_PCMCIA_SROM)
++#define SPROMBUS	(PCMCIA_BUS)
++#else
++#define SPROMBUS	(PCI_BUS)
++#endif
++
++/* Allows size optimization for single-chip image */
++#ifdef BCMCHIPID
++#define CHIPID(chip)	(BCMCHIPID)
++#else
++#define CHIPID(chip)	(chip)
++#endif
++
++#ifdef BCMCHIPREV
++#define CHIPREV(rev)	(BCMCHIPREV)
++#else
++#define CHIPREV(rev)	(rev)
++#endif
++
++#ifdef BCMPCIEREV
++#define PCIECOREREV(rev)	(BCMPCIEREV)
++#else
++#define PCIECOREREV(rev)	(rev)
++#endif
++
++#ifdef BCMPMUREV
++#define PMUREV(rev)	(BCMPMUREV)
++#else
++#define PMUREV(rev)	(rev)
++#endif
++
++#ifdef BCMCCREV
++#define CCREV(rev)	(BCMCCREV)
++#else
++#define CCREV(rev)	(rev)
++#endif
++
++#ifdef BCMGCIREV
++#define GCIREV(rev)	(BCMGCIREV)
++#else
++#define GCIREV(rev)	(rev)
++#endif
++
++/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
++#define DMADDR_MASK_32 0x0		/* Address mask for 32-bits */
++#define DMADDR_MASK_30 0xc0000000	/* Address mask for 30-bits */
++#define DMADDR_MASK_26 0xFC000000	/* Address maks for 26-bits */
++#define DMADDR_MASK_0  0xffffffff	/* Address mask for 0-bits (hi-part) */
++
++#define	DMADDRWIDTH_26  26 /* 26-bit addressing capability */
++#define	DMADDRWIDTH_30  30 /* 30-bit addressing capability */
++#define	DMADDRWIDTH_32  32 /* 32-bit addressing capability */
++#define	DMADDRWIDTH_63  63 /* 64-bit addressing capability */
++#define	DMADDRWIDTH_64  64 /* 64-bit addressing capability */
++
++typedef struct {
++	uint32 loaddr;
++	uint32 hiaddr;
++} dma64addr_t;
++
++#define PHYSADDR64HI(_pa) ((_pa).hiaddr)
++#define PHYSADDR64HISET(_pa, _val) \
++	do { \
++		(_pa).hiaddr = (_val);		\
++	} while (0)
++#define PHYSADDR64LO(_pa) ((_pa).loaddr)
++#define PHYSADDR64LOSET(_pa, _val) \
++	do { \
++		(_pa).loaddr = (_val);		\
++	} while (0)
++
++#ifdef BCMDMA64OSL
++typedef dma64addr_t dmaaddr_t;
++#define PHYSADDRHI(_pa) PHYSADDR64HI(_pa)
++#define PHYSADDRHISET(_pa, _val) PHYSADDR64HISET(_pa, _val)
++#define PHYSADDRLO(_pa)  PHYSADDR64LO(_pa)
++#define PHYSADDRLOSET(_pa, _val) PHYSADDR64LOSET(_pa, _val)
++#define PHYSADDRTOULONG(_pa, _ulong) \
++	do { \
++		_ulong = ((unsigned long long)(_pa).hiaddr << 32) | ((_pa).loaddr); \
++	} while (0)
++
++#else
++typedef unsigned long dmaaddr_t;
++#define PHYSADDRHI(_pa) (0)
++#define PHYSADDRHISET(_pa, _val)
++#define PHYSADDRLO(_pa) ((_pa))
++#define PHYSADDRLOSET(_pa, _val) \
++	do { \
++		(_pa) = (_val);			\
++	} while (0)
++#endif /* BCMDMA64OSL */
++#define PHYSADDRISZERO(_pa) (PHYSADDRLO(_pa) == 0 && PHYSADDRHI(_pa) == 0)
++
++/* One physical DMA segment */
++typedef struct  {
++	dmaaddr_t addr;
++	uint32	  length;
++} hnddma_seg_t;
++
++#define MAX_DMA_SEGS 8
++
++
++typedef struct {
++	void *oshdmah; /* Opaque handle for OSL to store its information */
++	uint origsize; /* Size of the virtual packet */
++	uint nsegs;
++	hnddma_seg_t segs[MAX_DMA_SEGS];
++} hnddma_seg_map_t;
++
++
++/* packet headroom necessary to accommodate the largest header in the system, (i.e TXOFF).
++ * By doing, we avoid the need  to allocate an extra buffer for the header when bridging to WL.
++ * There is a compile time check in wlc.c which ensure that this value is at least as big
++ * as TXOFF. This value is used in dma_rxfill (hnddma.c).
++ */
++
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RCP_TXNOCOPY)
++/* add 40 bytes to allow for extra RPC header and info  */
++#define BCMEXTRAHDROOM 260
++#else /* BCM_RPC_NOCOPY || BCM_RPC_TXNOCOPY */
++#if defined(STB)
++#if defined(BCM_GMAC3)
++#define BCMEXTRAHDROOM 32 /* For FullDongle, no D11 headroom space required. */
++#else
++#define BCMEXTRAHDROOM 224
++#endif /* ! BCM_GMAC3 */
++#else
++#define BCMEXTRAHDROOM 204
++#endif 
++#endif /* BCM_RPC_NOCOPY || BCM_RPC_TXNOCOPY */
++
++/* Packet alignment for most efficient SDIO (can change based on platform) */
++#ifndef SDALIGN
++#define SDALIGN	32
++#endif
++
++/* Headroom required for dongle-to-host communication.  Packets allocated
++ * locally in the dongle (e.g. for CDC ioctls or RNDIS messages) should
++ * leave this much room in front for low-level message headers which may
++ * be needed to get across the dongle bus to the host.  (These messages
++ * don't go over the network, so room for the full WL header above would
++ * be a waste.).
++*/
++#define BCMDONGLEHDRSZ 12
++#define BCMDONGLEPADSZ 16
++
++#define BCMDONGLEOVERHEAD	(BCMDONGLEHDRSZ + BCMDONGLEPADSZ)
++
++
++#if defined(NO_BCMDBG_ASSERT)
++# undef BCMDBG_ASSERT
++# undef BCMASSERT_LOG
++#endif
++
++#if defined(BCMASSERT_LOG)
++#define BCMASSERT_SUPPORT
++#endif 
++
++/* Macros for doing definition and get/set of bitfields
++ * Usage example, e.g. a three-bit field (bits 4-6):
++ *    #define <NAME>_M	BITFIELD_MASK(3)
++ *    #define <NAME>_S	4
++ * ...
++ *    regval = R_REG(osh, &regs->regfoo);
++ *    field = GFIELD(regval, <NAME>);
++ *    regval = SFIELD(regval, <NAME>, 1);
++ *    W_REG(osh, &regs->regfoo, regval);
++ */
++#define BITFIELD_MASK(width) \
++		(((unsigned)1 << (width)) - 1)
++#define GFIELD(val, field) \
++		(((val) >> field ## _S) & field ## _M)
++#define SFIELD(val, field, bits) \
++		(((val) & (~(field ## _M << field ## _S))) | \
++		 ((unsigned)(bits) << field ## _S))
++
++/* define BCMSMALL to remove misc features for memory-constrained environments */
++#ifdef BCMSMALL
++#undef	BCMSPACE
++#define bcmspace	FALSE	/* if (bcmspace) code is discarded */
++#else
++#define	BCMSPACE
++#define bcmspace	TRUE	/* if (bcmspace) code is retained */
++#endif
++
++/* Max. nvram variable table size */
++#ifndef MAXSZ_NVRAM_VARS
++#ifdef LARGE_NVRAM_MAXSZ
++#define MAXSZ_NVRAM_VARS	LARGE_NVRAM_MAXSZ
++#else
++/* SROM12 changes */
++#define	MAXSZ_NVRAM_VARS	6144
++#endif /* LARGE_NVRAM_MAXSZ */
++#endif /* !MAXSZ_NVRAM_VARS */
++
++
++
++/* WL_ENAB_RUNTIME_CHECK may be set based upon the #define below (for ROM builds). It may also
++ * be defined via makefiles (e.g. ROM auto abandon unoptimized compiles).
++ */
++
++
++#ifdef BCMLFRAG /* BCMLFRAG support enab macros  */
++	extern bool _bcmlfrag;
++	#if defined(WL_ENAB_RUNTIME_CHECK) || !defined(DONGLEBUILD)
++		#define BCMLFRAG_ENAB() (_bcmlfrag)
++	#elif defined(BCMLFRAG_DISABLED)
++		#define BCMLFRAG_ENAB()	(0)
++	#else
++		#define BCMLFRAG_ENAB()	(1)
++	#endif
++#else
++	#define BCMLFRAG_ENAB()		(0)
++#endif /* BCMLFRAG_ENAB */
++
++#ifdef BCMPCIEDEV /* BCMPCIEDEV support enab macros */
++extern bool _pciedevenab;
++	#if defined(WL_ENAB_RUNTIME_CHECK)
++		#define BCMPCIEDEV_ENAB() (_pciedevenab)
++	#elif defined(BCMPCIEDEV_ENABLED)
++		#define BCMPCIEDEV_ENAB()	1
++	#else
++		#define BCMPCIEDEV_ENAB()	0
++	#endif
++#else
++	#define BCMPCIEDEV_ENAB()	0
++#endif /* BCMPCIEDEV */
++
++	#define BCMSDIODEV_ENAB()	0
++
++/* Max size for reclaimable NVRAM array */
++#ifdef DL_NVRAM
++#define NVRAM_ARRAY_MAXSIZE	DL_NVRAM
++#else
++#define NVRAM_ARRAY_MAXSIZE	MAXSZ_NVRAM_VARS
++#endif /* DL_NVRAM */
++
++extern uint32 gFWID;
++
++/* Chip related low power flags (lpflags) */
++#define LPFLAGS_SI_GLOBAL_DISABLE		(1 << 0)
++#define LPFLAGS_SI_MEM_STDBY_DISABLE		(1 << 1)
++#define LPFLAGS_SI_SFLASH_DISABLE		(1 << 2)
++#define LPFLAGS_SI_BTLDO3P3_DISABLE		(1 << 3)
++#define LPFLAGS_SI_GCI_FORCE_REGCLK_DISABLE	(1 << 4)
++#define LPFLAGS_SI_FORCE_PWM_WHEN_RADIO_ON (1 << 5)
++#define LPFLAGS_PHY_GLOBAL_DISABLE		(1 << 16)
++#define LPFLAGS_PHY_LP_DISABLE			(1 << 17)
++#define LPFLAGS_PSM_PHY_CTL			(1 << 18)
++
++/* Chip related Cbuck modes */
++#define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE0 0x00001c03
++#define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE0 0x00492490
++#define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE1 0x00001c03
++#define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE1 0x00490410
++
++/* Chip related dynamic cbuck mode mask */
++
++#define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE_MASK  0xFFFFFC00
++#define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE_MASK  0xFFFFFFFF
++
++#ifndef PAD
++#define _PADLINE(line)  pad ## line
++#define _XSTR(line)     _PADLINE(line)
++#define PAD             _XSTR(__LINE__)
++#endif
++
++#endif /* _bcmdefs_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmdevs.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmdevs.h
+new file mode 100644
+index 000000000..5437c8f2a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmdevs.h
+@@ -0,0 +1,933 @@
++/*
++ * Broadcom device-specific manifest constants.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmdevs.h 625027 2016-03-15 08:20:18Z $
++ */
++
++#ifndef	_BCMDEVS_H
++#define	_BCMDEVS_H
++
++/* PCI vendor IDs */
++#define	VENDOR_EPIGRAM		0xfeda
++#define	VENDOR_BROADCOM		0x14e4
++#define	VENDOR_3COM		0x10b7
++#define	VENDOR_NETGEAR		0x1385
++#define	VENDOR_DIAMOND		0x1092
++#define	VENDOR_INTEL		0x8086
++#define	VENDOR_DELL		0x1028
++#define	VENDOR_HP		0x103c
++#define	VENDOR_HP_COMPAQ	0x0e11
++#define	VENDOR_APPLE		0x106b
++#define VENDOR_SI_IMAGE		0x1095		/* Silicon Image, used by Arasan SDIO Host */
++#define VENDOR_BUFFALO		0x1154		/* Buffalo vendor id */
++#define VENDOR_TI		0x104c		/* Texas Instruments */
++#define VENDOR_RICOH		0x1180		/* Ricoh */
++#define VENDOR_JMICRON		0x197b
++
++
++/* PCMCIA vendor IDs */
++#define	VENDOR_BROADCOM_PCMCIA	0x02d0
++
++/* SDIO vendor IDs */
++#define	VENDOR_BROADCOM_SDIO	0x00BF
++
++/* DONGLE VID/PIDs */
++#define BCM_DNGL_VID		0x0a5c
++#define BCM_DNGL_BL_PID_4328	0xbd12
++#define BCM_DNGL_BL_PID_4322	0xbd13
++#define BCM_DNGL_BL_PID_4319    0xbd16
++#define BCM_DNGL_BL_PID_43236   0xbd17
++#define BCM_DNGL_BL_PID_4332	0xbd18
++#define BCM_DNGL_BL_PID_4330	0xbd19
++#define BCM_DNGL_BL_PID_4334	0xbd1a
++#define BCM_DNGL_BL_PID_43239   0xbd1b
++#define BCM_DNGL_BL_PID_4324	0xbd1c
++#define BCM_DNGL_BL_PID_4360	0xbd1d
++#define BCM_DNGL_BL_PID_43143	0xbd1e
++#define BCM_DNGL_BL_PID_43242	0xbd1f
++#define BCM_DNGL_BL_PID_43342	0xbd21
++#define BCM_DNGL_BL_PID_4335	0xbd20
++#define BCM_DNGL_BL_PID_43341	0xbd22
++#define BCM_DNGL_BL_PID_4350    0xbd23
++#define BCM_DNGL_BL_PID_4345    0xbd24
++#define BCM_DNGL_BL_PID_4349	0xbd25
++#define BCM_DNGL_BL_PID_4354	0xbd26
++#define BCM_DNGL_BL_PID_43569   0xbd27
++#define BCM_DNGL_BL_PID_43909	0xbd28
++#define BCM_DNGL_BL_PID_4373	0xbd29
++
++#define BCM_DNGL_BDC_PID	0x0bdc
++#define BCM_DNGL_JTAG_PID	0x4a44
++
++/* HW USB BLOCK [CPULESS USB] PIDs */
++#define BCM_HWUSB_PID_43239     43239
++
++/* PCI Device IDs */
++#ifdef DEPRECATED /* These products have been deprecated */
++#define	BCM4210_DEVICE_ID	0x1072		/* never used */
++#define	BCM4230_DEVICE_ID	0x1086		/* never used */
++#define	BCM4401_ENET_ID		0x170c		/* 4401b0 production enet cards */
++#define	BCM3352_DEVICE_ID	0x3352		/* bcm3352 device id */
++#define	BCM3360_DEVICE_ID	0x3360		/* bcm3360 device id */
++#define	BCM4211_DEVICE_ID	0x4211
++#define	BCM4231_DEVICE_ID	0x4231
++#define	BCM4303_D11B_ID		0x4303		/* 4303 802.11b */
++#define	BCM4311_D11G_ID		0x4311		/* 4311 802.11b/g id */
++#define	BCM4311_D11DUAL_ID	0x4312		/* 4311 802.11a/b/g id */
++#define	BCM4311_D11A_ID		0x4313		/* 4311 802.11a id */
++#define	BCM4328_D11DUAL_ID	0x4314		/* 4328/4312 802.11a/g id */
++#define	BCM4328_D11G_ID		0x4315		/* 4328/4312 802.11g id */
++#define	BCM4328_D11A_ID		0x4316		/* 4328/4312 802.11a id */
++#define	BCM4318_D11A_ID		0x431a		/* 4318 802.11a id */
++#define	BCM4325_D11DUAL_ID	0x431b		/* 4325 802.11a/g id */
++#define	BCM4325_D11G_ID		0x431c		/* 4325 802.11g id */
++#define	BCM4325_D11A_ID		0x431d		/* 4325 802.11a id */
++#define	BCM4306_UART_ID		0x4322		/* 4306 uart */
++#define	BCM4306_V90_ID		0x4323		/* 4306 v90 codec */
++#define	BCM4306_D11G_ID2	0x4325		/* BCM4306_D11G_ID; INF w/loose binding war */
++#define	BCM4321_D11N_ID		0x4328		/* 4321 802.11n dualband id */
++#define	BCM4321_D11N2G_ID	0x4329		/* 4321 802.11n 2.4Ghz band id */
++#define	BCM4321_D11N5G_ID	0x432a		/* 4321 802.11n 5Ghz band id */
++#define BCM4322_D11N_ID		0x432b		/* 4322 802.11n dualband device */
++#define BCM4322_D11N2G_ID	0x432c		/* 4322 802.11n 2.4GHz device */
++#define BCM4322_D11N5G_ID	0x432d		/* 4322 802.11n 5GHz device */
++#define BCM4329_D11N_ID		0x432e		/* 4329 802.11n dualband device */
++#define BCM4329_D11N2G_ID	0x432f		/* 4329 802.11n 2.4G device */
++#define BCM4329_D11N5G_ID	0x4330		/* 4329 802.11n 5G device */
++#define	BCM4315_D11DUAL_ID	0x4334		/* 4315 802.11a/g id */
++#define	BCM4315_D11G_ID		0x4335		/* 4315 802.11g id */
++#define	BCM4315_D11A_ID		0x4336		/* 4315 802.11a id */
++#define BCM4319_D11N_ID		0x4337		/* 4319 802.11n dualband device */
++#define BCM4319_D11N2G_ID	0x4338		/* 4319 802.11n 2.4G device */
++#define BCM4319_D11N5G_ID	0x4339		/* 4319 802.11n 5G device */
++#define BCM43231_D11N2G_ID	0x4340		/* 43231 802.11n 2.4GHz device */
++#define BCM43221_D11N2G_ID	0x4341		/* 43221 802.11n 2.4GHz device */
++#define BCM43222_D11N_ID	0x4350		/* 43222 802.11n dualband device */
++#define BCM43222_D11N2G_ID	0x4351		/* 43222 802.11n 2.4GHz device */
++#define BCM43222_D11N5G_ID	0x4352		/* 43222 802.11n 5GHz device */
++#define BCM43226_D11N_ID	0x4354		/* 43226 802.11n dualband device */
++#endif /* DEPRECATED */
++/* DEPRECATED but used */
++#define	BCM4306_D11G_ID		0x4320		/* 4306 802.11g */
++#define	BCM4306_D11A_ID		0x4321		/* 4306 802.11a */
++#define	BCM4306_D11DUAL_ID	0x4324		/* 4306 dual A+B */
++#define	BCM4318_D11G_ID		0x4318		/* 4318 802.11b/g id */
++#define	BCM4318_D11DUAL_ID	0x4319		/* 4318 802.11a/b/g id */
++/* DEPRECATED */
++
++#define	BCM53572_D11N2G_ID	0x4329		/* 53572 802.11n 2.4Ghz band id (same as BCM4321) */
++#define BCM43224_D11N_ID	0x4353		/* 43224 802.11n dualband device */
++#define BCM43224_D11N_ID_VEN1	0x0576		/* Vendor specific 43224 802.11n db device */
++#define BCM43236_D11N_ID	0x4346		/* 43236 802.11n dualband device */
++#define BCM43236_D11N2G_ID	0x4347		/* 43236 802.11n 2.4GHz device */
++#define BCM43236_D11N5G_ID	0x4348		/* 43236 802.11n 5GHz device */
++#define BCM43225_D11N2G_ID	0x4357		/* 43225 802.11n 2.4GHz device */
++#define BCM43421_D11N_ID	0xA99D		/* 43421 802.11n dualband device */
++#define BCM4313_D11N2G_ID	0x4727		/* 4313 802.11n 2.4G device */
++#define BCM4330_D11N_ID         0x4360          /* 4330 802.11n dualband device */
++#define BCM4330_D11N2G_ID       0x4361          /* 4330 802.11n 2.4G device */
++#define BCM4330_D11N5G_ID       0x4362          /* 4330 802.11n 5G device */
++#define BCM4336_D11N_ID		0x4343		/* 4336 802.11n 2.4GHz device */
++#define BCM6362_D11N_ID		0x435f		/* 6362 802.11n dualband device */
++#define BCM6362_D11N2G_ID	0x433f		/* 6362 802.11n 2.4Ghz band id */
++#define BCM6362_D11N5G_ID	0x434f		/* 6362 802.11n 5Ghz band id */
++#define BCM4331_D11N_ID		0x4331		/* 4331 802.11n dualband id */
++#define BCM4331_D11N2G_ID	0x4332		/* 4331 802.11n 2.4Ghz band id */
++#define BCM4331_D11N5G_ID	0x4333		/* 4331 802.11n 5Ghz band id */
++#define BCM43237_D11N_ID	0x4355		/* 43237 802.11n dualband device */
++#define BCM43237_D11N5G_ID	0x4356		/* 43237 802.11n 5GHz device */
++#define BCM43227_D11N2G_ID	0x4358		/* 43228 802.11n 2.4GHz device */
++#define BCM43228_D11N_ID	0x4359		/* 43228 802.11n DualBand device */
++#define BCM43228_D11N5G_ID	0x435a		/* 43228 802.11n 5GHz device */
++#define BCM43362_D11N_ID	0x4363		/* 43362 802.11n 2.4GHz device */
++#define BCM43239_D11N_ID	0x4370		/* 43239 802.11n dualband device */
++#define BCM4324_D11N_ID		0x4374		/* 4324 802.11n dualband device */
++#define BCM43217_D11N2G_ID	0x43a9		/* 43217 802.11n 2.4GHz device */
++#define BCM43131_D11N2G_ID	0x43aa		/* 43131 802.11n 2.4GHz device */
++#define BCM4314_D11N2G_ID	0x4364		/* 4314 802.11n 2.4G device */
++#define BCM43142_D11N2G_ID	0x4365		/* 43142 802.11n 2.4G device */
++#define BCM43143_D11N2G_ID	0x4366		/* 43143 802.11n 2.4G device */
++#define BCM4334_D11N_ID		0x4380		/* 4334 802.11n dualband device */
++#define BCM4334_D11N2G_ID	0x4381		/* 4334 802.11n 2.4G device */
++#define BCM4334_D11N5G_ID	0x4382		/* 4334 802.11n 5G device */
++#define BCM43342_D11N_ID	0x4383		/* 43342 802.11n dualband device */
++#define BCM43342_D11N2G_ID	0x4384		/* 43342 802.11n 2.4G device */
++#define BCM43342_D11N5G_ID	0x4385		/* 43342 802.11n 5G device */
++#define BCM43341_D11N_ID	0x4386		/* 43341 802.11n dualband device */
++#define BCM43341_D11N2G_ID	0x4387		/* 43341 802.11n 2.4G device */
++#define BCM43341_D11N5G_ID	0x4388		/* 43341 802.11n 5G device */
++#define BCM4360_D11AC_ID	0x43a0
++#define BCM4360_D11AC2G_ID	0x43a1
++#define BCM4360_D11AC5G_ID	0x43a2
++#define BCM4345_D11AC_ID	0x43ab		/* 4345 802.11ac dualband device */
++#define BCM4345_D11AC2G_ID	0x43ac		/* 4345 802.11ac 2.4G device */
++#define BCM4345_D11AC5G_ID	0x43ad		/* 4345 802.11ac 5G device */
++#define BCM43455_D11AC_ID	0x43e3		/* 43455 802.11ac dualband device */
++#define BCM43455_D11AC2G_ID	0x43e4		/* 43455 802.11ac 2.4G device */
++#define BCM43455_D11AC5G_ID	0x43e5		/* 43455 802.11ac 5G device */
++#define BCM4335_D11AC_ID	0x43ae
++#define BCM4335_D11AC2G_ID	0x43af
++#define BCM4335_D11AC5G_ID	0x43b0
++#define BCM4352_D11AC_ID	0x43b1		/* 4352 802.11ac dualband device */
++#define BCM4352_D11AC2G_ID	0x43b2		/* 4352 802.11ac 2.4G device */
++#define BCM4352_D11AC5G_ID	0x43b3		/* 4352 802.11ac 5G device */
++#define BCM43602_D11AC_ID	0x43ba		/* ac dualband PCI devid SPROM programmed */
++#define BCM43602_D11AC2G_ID	0x43bb		/* 43602 802.11ac 2.4G device */
++#define BCM43602_D11AC5G_ID	0x43bc		/* 43602 802.11ac 5G device */
++#define BCM4349_D11AC_ID	0x4349		/* 4349 802.11ac dualband device */
++#define BCM4349_D11AC2G_ID	0x43dd		/* 4349 802.11ac 2.4G device */
++#define BCM4349_D11AC5G_ID	0x43de		/* 4349 802.11ac 5G device */
++#define BCM53573_D11AC_ID	0x43b4		/* 53573 802.11ac dualband device */
++#define BCM53573_D11AC2G_ID	0x43b5		/* 53573 802.11ac 2.4G device */
++#define BCM53573_D11AC5G_ID	0x43b6		/* 53573 802.11ac 5G device */
++#define BCM47189_D11AC_ID	0x43c6		/* 47189 802.11ac dualband device */
++#define BCM47189_D11AC2G_ID	0x43c7		/* 47189 802.11ac 2.4G device */
++#define BCM47189_D11AC5G_ID	0x43c8		/* 47189 802.11ac 5G device */
++#define BCM4355_D11AC_ID	0x43dc		/* 4355 802.11ac dualband device */
++#define BCM4355_D11AC2G_ID	0x43fc		/* 4355 802.11ac 2.4G device */
++#define BCM4355_D11AC5G_ID	0x43fd		/* 4355 802.11ac 5G device */
++#define BCM4359_D11AC_ID	0x43ef		/* 4359 802.11ac dualband device */
++#define BCM4359_D11AC2G_ID	0x43fe		/* 4359 802.11ac 2.4G device */
++#define BCM4359_D11AC5G_ID	0x43ff		/* 4359 802.11ac 5G device */
++#define BCM43596_D11AC_ID	0x4415		/* 43596 802.11ac dualband device */
++#define BCM43596_D11AC2G_ID	0x4416		/* 43596 802.11ac 2.4G device */
++#define BCM43596_D11AC5G_ID	0x4417		/* 43596 802.11ac 5G device */
++#define BCM43597_D11AC_ID	0x441c		/* 43597 802.11ac dualband device */
++#define BCM43597_D11AC2G_ID	0x441d		/* 43597 802.11ac 2.4G device */
++#define BCM43597_D11AC5G_ID	0x441e		/* 43597 802.11ac 5G device */
++#define BCM43909_D11AC_ID	0x43d0		/* 43909 802.11ac dualband device */
++#define BCM43909_D11AC2G_ID	0x43d1		/* 43909 802.11ac 2.4G device */
++#define BCM43909_D11AC5G_ID	0x43d2		/* 43909 802.11ac 5G device */
++#define BCM43012_D11N_ID	0xA804		/* 43012 802.11n dualband device */
++#define BCM43012_D11N2G_ID	0xA805		/* 43012 802.11n 2.4G device */
++#define BCM43012_D11N5G_ID	0xA806		/* 43012 802.11n 5G device */
++
++/* PCI Subsystem ID */
++#define BCM943228HMB_SSID_VEN1	0x0607
++#define BCM94313HMGBL_SSID_VEN1	0x0608
++#define BCM94313HMG_SSID_VEN1	0x0609
++#define BCM943142HM_SSID_VEN1	0x0611
++
++#define BCM43143_D11N2G_ID	0x4366		/* 43143 802.11n 2.4G device */
++
++#define BCM43242_D11N_ID	0x4367		/* 43242 802.11n dualband device */
++#define BCM43242_D11N2G_ID	0x4368		/* 43242 802.11n 2.4G device */
++#define BCM43242_D11N5G_ID	0x4369		/* 43242 802.11n 5G device */
++
++#define BCM4350_D11AC_ID	0x43a3
++#define BCM4350_D11AC2G_ID	0x43a4
++#define BCM4350_D11AC5G_ID	0x43a5
++
++#define BCM43556_D11AC_ID	0x43b7
++#define BCM43556_D11AC2G_ID	0x43b8
++#define BCM43556_D11AC5G_ID	0x43b9
++
++#define BCM43558_D11AC_ID	0x43c0
++#define BCM43558_D11AC2G_ID	0x43c1
++#define BCM43558_D11AC5G_ID	0x43c2
++
++#define BCM43566_D11AC_ID	0x43d3
++#define BCM43566_D11AC2G_ID	0x43d4
++#define BCM43566_D11AC5G_ID	0x43d5
++
++#define BCM43568_D11AC_ID	0x43d6
++#define BCM43568_D11AC2G_ID	0x43d7
++#define BCM43568_D11AC5G_ID	0x43d8
++
++#define BCM43569_D11AC_ID	0x43d9
++#define BCM43569_D11AC2G_ID	0x43da
++#define BCM43569_D11AC5G_ID	0x43db
++
++#define BCM43570_D11AC_ID	0x43d9
++#define BCM43570_D11AC2G_ID	0x43da
++#define BCM43570_D11AC5G_ID	0x43db
++
++#define BCM4354_D11AC_ID	0x43df		/* 4354 802.11ac dualband device */
++#define BCM4354_D11AC2G_ID	0x43e0		/* 4354 802.11ac 2.4G device */
++#define BCM4354_D11AC5G_ID	0x43e1		/* 4354 802.11ac 5G device */
++#define BCM43430_D11N2G_ID	0x43e2		/* 43430 802.11n 2.4G device */
++#define BCM43018_D11N2G_ID	0x441b		/* 43018 802.11n 2.4G device */
++
++
++#define BCM4347_D11AC_ID	0x440a		/* 4347 802.11ac dualband device */
++#define BCM4347_D11AC2G_ID	0x440b		/* 4347 802.11ac 2.4G device */
++#define BCM4347_D11AC5G_ID	0x440c		/* 4347 802.11ac 5G device */
++
++#define BCM4361_D11AC_ID	0x441f		/* 4361 802.11ac dualband device */
++#define BCM4361_D11AC2G_ID	0x4420		/* 4361 802.11ac 2.4G device */
++#define BCM4361_D11AC5G_ID	0x4421		/* 4361 802.11ac 5G device */
++
++#define BCM4362_D11AX_ID	0x4490		/* 4362 802.11ax dualband device */
++#define BCM4362_D11AX2G_ID	0x4491		/* 4362 802.11ax 2.4G device */
++#define BCM4362_D11AX5G_ID	0x4492		/* 4362 802.11ax 5G device */
++
++#define BCM4364_D11AC_ID	0x4464		/* 4364 802.11ac dualband device */
++#define BCM4364_D11AC2G_ID	0x446a		/* 4364 802.11ac 2.4G device */
++#define BCM4364_D11AC5G_ID	0x446b		/* 4364 802.11ac 5G device */
++
++#define BCM4365_D11AC_ID	0x43ca
++#define BCM4365_D11AC2G_ID	0x43cb
++#define BCM4365_D11AC5G_ID	0x43cc
++
++#define BCM4366_D11AC_ID	0x43c3
++#define BCM4366_D11AC2G_ID	0x43c4
++#define BCM4366_D11AC5G_ID	0x43c5
++
++#define BCM43349_D11N_ID	0x43e6		/* 43349 802.11n dualband id */
++#define BCM43349_D11N2G_ID	0x43e7		/* 43349 802.11n 2.4Ghz band id */
++#define BCM43349_D11N5G_ID	0x43e8		/* 43349 802.11n 5Ghz band id */
++
++#define BCM4358_D11AC_ID        0x43e9          /* 4358 802.11ac dualband device */
++#define BCM4358_D11AC2G_ID      0x43ea          /* 4358 802.11ac 2.4G device */
++#define BCM4358_D11AC5G_ID      0x43eb          /* 4358 802.11ac 5G device */
++
++#define BCM4356_D11AC_ID	0x43ec		/* 4356 802.11ac dualband device */
++#define BCM4356_D11AC2G_ID	0x43ed		/* 4356 802.11ac 2.4G device */
++#define BCM4356_D11AC5G_ID	0x43ee		/* 4356 802.11ac 5G device */
++
++#define BCM4371_D11AC_ID	0x440d		/* 4371 802.11ac dualband device */
++#define BCM4371_D11AC2G_ID	0x440e		/* 4371 802.11ac 2.4G device */
++#define BCM4371_D11AC5G_ID	0x440f		/* 4371 802.11ac 5G device */
++#define BCM7271_D11AC_ID	0x4410		/* 7271 802.11ac dualband device */
++#define BCM7271_D11AC2G_ID	0x4411		/* 7271 802.11ac 2.4G device */
++#define BCM7271_D11AC5G_ID	0x4412		/* 7271 802.11ac 5G device */
++
++#define BCM4373_D11AC_ID	0x4418          /* 4373 802.11ac dualband device */
++#define BCM4373_D11AC2G_ID	0x4419          /* 4373 802.11ac 2.4G device */
++#define BCM4373_D11AC5G_ID	0x441a          /* 4373 802.11ac 5G device */
++
++#define	BCMGPRS_UART_ID		0x4333		/* Uart id used by 4306/gprs card */
++#define	BCMGPRS2_UART_ID	0x4344		/* Uart id used by 4306/gprs card */
++#define FPGA_JTAGM_ID		0x43f0		/* FPGA jtagm device id */
++#define BCM_JTAGM_ID		0x43f1		/* BCM jtagm device id */
++#define SDIOH_FPGA_ID		0x43f2		/* sdio host fpga */
++#define BCM_SDIOH_ID		0x43f3		/* BCM sdio host id */
++#define SDIOD_FPGA_ID		0x43f4		/* sdio device fpga */
++#define SPIH_FPGA_ID		0x43f5		/* PCI SPI Host Controller FPGA */
++#define BCM_SPIH_ID		0x43f6		/* Synopsis SPI Host Controller */
++#define MIMO_FPGA_ID		0x43f8		/* FPGA mimo minimacphy device id */
++#define BCM_JTAGM2_ID		0x43f9		/* BCM alternate jtagm device id */
++#define SDHCI_FPGA_ID		0x43fa		/* Standard SDIO Host Controller FPGA */
++#define	BCM4402_ENET_ID		0x4402		/* 4402 enet */
++#define	BCM4402_V90_ID		0x4403		/* 4402 v90 codec */
++#define	BCM4410_DEVICE_ID	0x4410		/* bcm44xx family pci iline */
++#define	BCM4412_DEVICE_ID	0x4412		/* bcm44xx family pci enet */
++#define	BCM4430_DEVICE_ID	0x4430		/* bcm44xx family cardbus iline */
++#define	BCM4432_DEVICE_ID	0x4432		/* bcm44xx family cardbus enet */
++#define	BCM4704_ENET_ID		0x4706		/* 4704 enet (Use 47XX_ENET_ID instead!) */
++#define	BCM4710_DEVICE_ID	0x4710		/* 4710 primary function 0 */
++#define	BCM47XX_AUDIO_ID	0x4711		/* 47xx audio codec */
++#define	BCM47XX_V90_ID		0x4712		/* 47xx v90 codec */
++#define	BCM47XX_ENET_ID		0x4713		/* 47xx enet */
++#define	BCM47XX_EXT_ID		0x4714		/* 47xx external i/f */
++#define	BCM47XX_GMAC_ID		0x4715		/* 47xx Unimac based GbE */
++#define	BCM47XX_USBH_ID		0x4716		/* 47xx usb host */
++#define	BCM47XX_USBD_ID		0x4717		/* 47xx usb device */
++#define	BCM47XX_IPSEC_ID	0x4718		/* 47xx ipsec */
++#define	BCM47XX_ROBO_ID		0x4719		/* 47xx/53xx roboswitch core */
++#define	BCM47XX_USB20H_ID	0x471a		/* 47xx usb 2.0 host */
++#define	BCM47XX_USB20D_ID	0x471b		/* 47xx usb 2.0 device */
++#define	BCM47XX_ATA100_ID	0x471d		/* 47xx parallel ATA */
++#define	BCM47XX_SATAXOR_ID	0x471e		/* 47xx serial ATA & XOR DMA */
++#define	BCM47XX_GIGETH_ID	0x471f		/* 47xx GbE (5700) */
++#ifdef DEPRECATED /* These products have been deprecated */
++#define	BCM4712_MIPS_ID		0x4720		/* 4712 base devid */
++#define	BCM4716_DEVICE_ID	0x4722		/* 4716 base devid */
++#endif /* DEPRECATED */
++#define	BCM47XX_USB30H_ID	0x472a		/* 47xx usb 3.0 host */
++#define	BCM47XX_USB30D_ID	0x472b		/* 47xx usb 3.0 device */
++#define	BCM47XX_USBHUB_ID	0x472c		/* 47xx usb hub */
++#define BCM47XX_SMBUS_EMU_ID	0x47fe		/* 47xx emulated SMBus device */
++#define	BCM47XX_XOR_EMU_ID	0x47ff		/* 47xx emulated XOR engine */
++#define	EPI41210_DEVICE_ID	0xa0fa		/* bcm4210 */
++#define	EPI41230_DEVICE_ID	0xa10e		/* bcm4230 */
++#define JINVANI_SDIOH_ID	0x4743		/* Jinvani SDIO Gold Host */
++#define BCM27XX_SDIOH_ID	0x2702		/* BCM27xx Standard SDIO Host */
++#define PCIXX21_FLASHMEDIA_ID	0x803b		/* TI PCI xx21 Standard Host Controller */
++#define PCIXX21_SDIOH_ID	0x803c		/* TI PCI xx21 Standard Host Controller */
++#define R5C822_SDIOH_ID		0x0822		/* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host */
++#define JMICRON_SDIOH_ID	0x2381		/* JMicron Standard SDIO Host Controller */
++
++#define BCM43452_D11AC_ID	0x47ab		/* 43452 802.11ac dualband device */
++#define BCM43452_D11AC2G_ID	0x47ac		/* 43452 802.11ac 2.4G device */
++#define BCM43452_D11AC5G_ID	0x47ad		/* 43452 802.11ac 5G device */
++
++/* Chip IDs */
++#ifdef DEPRECATED /* These products have been deprecated */
++#define	BCM4306_CHIP_ID		0x4306		/* 4306 chipcommon chipid */
++#define	BCM4311_CHIP_ID		0x4311		/* 4311 PCIe 802.11a/b/g */
++#define	BCM43111_CHIP_ID	43111		/* 43111 chipcommon chipid (OTP chipid) */
++#define	BCM43112_CHIP_ID	43112		/* 43112 chipcommon chipid (OTP chipid) */
++#define	BCM4312_CHIP_ID		0x4312		/* 4312 chipcommon chipid */
++#define	BCM4315_CHIP_ID		0x4315		/* 4315 chip id */
++#define	BCM4318_CHIP_ID		0x4318		/* 4318 chipcommon chipid */
++#define	BCM4319_CHIP_ID		0x4319		/* 4319 chip id */
++#define	BCM4320_CHIP_ID		0x4320		/* 4320 chipcommon chipid */
++#define	BCM4321_CHIP_ID		0x4321		/* 4321 chipcommon chipid */
++#define	BCM4322_CHIP_ID		0x4322		/* 4322 chipcommon chipid */
++#define	BCM43221_CHIP_ID	43221		/* 43221 chipcommon chipid (OTP chipid) */
++#define	BCM43222_CHIP_ID	43222		/* 43222 chipcommon chipid */
++#define	BCM43226_CHIP_ID	43226		/* 43226 chipcommon chipid */
++#define	BCM43231_CHIP_ID	43231		/* 43231 chipcommon chipid (OTP chipid) */
++#define	BCM4342_CHIP_ID		4342		/* 4342 chipcommon chipid (OTP, RBBU) */
++#define	BCM4325_CHIP_ID		0x4325		/* 4325 chip id */
++#define	BCM4328_CHIP_ID		0x4328		/* 4328 chip id */
++#define	BCM4329_CHIP_ID		0x4329		/* 4329 chipcommon chipid */
++#define	BCM4712_CHIP_ID		0x4712		/* 4712 chipcommon chipid */
++#endif /* DEPRECATED */
++
++/* DEPRECATED but still referenced in components - start */
++#define	BCM4716_CHIP_ID		0x4716		/* 4716 chipcommon chipid */
++#define	BCM4748_CHIP_ID		0x4748		/* 4716 chipcommon chipid (OTP, RBBU) */
++#define	BCM47162_CHIP_ID	47162		/* 47162 chipcommon chipid */
++#define	BCM5354_CHIP_ID		0x5354		/* 5354 chipcommon chipid */
++/* DEPRECATED but still referenced in components - end */
++
++#define	BCM43224_CHIP_ID	43224		/* 43224 chipcommon chipid */
++#define	BCM43225_CHIP_ID	43225		/* 43225 chipcommon chipid */
++#define	BCM43227_CHIP_ID	43227		/* 43227 chipcommon chipid */
++#define	BCM43228_CHIP_ID	43228		/* 43228 chipcommon chipid */
++#define	BCM43217_CHIP_ID	43217		/* 43217 chip id (OTP chipid) */
++#define BCM4313_CHIP_ID		0x4313		/* 4313 chip id */
++#define	BCM43131_CHIP_ID	43131		/* 43131 chip id (OTP chipid) */
++#define	BCM43234_CHIP_ID	43234		/* 43234 chipcommon chipid */
++#define	BCM43235_CHIP_ID	43235		/* 43235 chipcommon chipid */
++#define	BCM43236_CHIP_ID	43236		/* 43236 chipcommon chipid */
++#define	BCM43237_CHIP_ID	43237		/* 43237 chipcommon chipid */
++#define	BCM43238_CHIP_ID	43238		/* 43238 chipcommon chipid */
++#define	BCM43239_CHIP_ID	43239		/* 43239 chipcommon chipid */
++#define	BCM43420_CHIP_ID	43420		/* 43222 chipcommon chipid (OTP, RBBU) */
++#define	BCM43421_CHIP_ID	43421		/* 43224 chipcommon chipid (OTP, RBBU) */
++#define	BCM43428_CHIP_ID	43428		/* 43228 chipcommon chipid (OTP, RBBU) */
++#define	BCM43431_CHIP_ID	43431		/* 4331  chipcommon chipid (OTP, RBBU) */
++#define	BCM43460_CHIP_ID	43460		/* 4360  chipcommon chipid (OTP, RBBU) */
++#define	BCM4331_CHIP_ID		0x4331		/* 4331 chipcommon chipid */
++#define BCM4336_CHIP_ID		0x4336		/* 4336 chipcommon chipid */
++#define BCM43362_CHIP_ID	43362		/* 43362 chipcommon chipid */
++#define BCM4330_CHIP_ID		0x4330		/* 4330 chipcommon chipid */
++#define BCM6362_CHIP_ID		0x6362		/* 6362 chipcommon chipid */
++#define BCM4314_CHIP_ID		0x4314		/* 4314 chipcommon chipid */
++#define BCM43142_CHIP_ID	43142		/* 43142 chipcommon chipid */
++#define BCM43143_CHIP_ID	43143		/* 43143 chipcommon chipid */
++#define	BCM4324_CHIP_ID		0x4324		/* 4324 chipcommon chipid */
++#define	BCM43242_CHIP_ID	43242		/* 43242 chipcommon chipid */
++#define	BCM43243_CHIP_ID	43243		/* 43243 chipcommon chipid */
++#define BCM4334_CHIP_ID		0x4334		/* 4334 chipcommon chipid */
++#define BCM4335_CHIP_ID		0x4335		/* 4335 chipcommon chipid */
++#define BCM4339_CHIP_ID		0x4339		/* 4339 chipcommon chipid */
++#define BCM43349_CHIP_ID	43349			/* 43349(0xA955) chipcommon chipid */
++#define BCM4360_CHIP_ID		0x4360          /* 4360 chipcommon chipid */
++#define BCM4364_CHIP_ID		0x4364			/* 4364 chipcommon chipid */
++#define BCM4352_CHIP_ID		0x4352          /* 4352 chipcommon chipid */
++#define BCM43526_CHIP_ID	0xAA06
++#define BCM43340_CHIP_ID	43340		/* 43340 chipcommon chipid */
++#define BCM43341_CHIP_ID	43341		/* 43341 chipcommon chipid */
++#define BCM43342_CHIP_ID	43342		/* 43342 chipcommon chipid */
++#define BCM4350_CHIP_ID		0x4350          /* 4350 chipcommon chipid */
++#define BCM4354_CHIP_ID		0x4354          /* 4354 chipcommon chipid */
++#define BCM4356_CHIP_ID		0x4356          /* 4356 chipcommon chipid */
++#define BCM4371_CHIP_ID		0x4371          /* 4371 chipcommon chipid */
++#define BCM43556_CHIP_ID	0xAA24          /* 43556 chipcommon chipid */
++#define BCM43558_CHIP_ID	0xAA26          /* 43558 chipcommon chipid */
++#define BCM43562_CHIP_ID	0xAA2A		/* 43562 chipcommon chipid */
++#define BCM43566_CHIP_ID	0xAA2E          /* 43566 chipcommon chipid */
++#define BCM43567_CHIP_ID	0xAA2F          /* 43567 chipcommon chipid */
++#define BCM43568_CHIP_ID	0xAA30          /* 43568 chipcommon chipid */
++#define BCM43569_CHIP_ID	0xAA31          /* 43569 chipcommon chipid */
++#define BCM43570_CHIP_ID	0xAA32          /* 43570 chipcommon chipid */
++#define BCM4358_CHIP_ID		0x4358          /* 4358 chipcommon chipid */
++#define BCM4371_CHIP_ID		0x4371          /* 4371 chipcommon chipid */
++#define	BCM43012_CHIP_ID	0xA804			/* 43012 chipcommon chipid */
++#define BCM4350_CHIP(chipid)	((CHIPID(chipid) == BCM4350_CHIP_ID) || \
++				(CHIPID(chipid) == BCM4354_CHIP_ID) || \
++				(CHIPID(chipid) == BCM43556_CHIP_ID) || \
++				(CHIPID(chipid) == BCM43558_CHIP_ID) || \
++				(CHIPID(chipid) == BCM43566_CHIP_ID) || \
++				(CHIPID(chipid) == BCM43567_CHIP_ID) || \
++				(CHIPID(chipid) == BCM43568_CHIP_ID) || \
++				(CHIPID(chipid) == BCM43569_CHIP_ID) || \
++				(CHIPID(chipid) == BCM43570_CHIP_ID) || \
++				(CHIPID(chipid) == BCM4358_CHIP_ID)) /* 4350 variations */
++
++#define BCM4345_CHIP_ID		0x4345		/* 4345 chipcommon chipid */
++#define BCM43454_CHIP_ID	43454		/* 43454 chipcommon chipid */
++#define BCM43455_CHIP_ID	43455		/* 43455 chipcommon chipid */
++#define BCM43457_CHIP_ID	43457		/* 43457 chipcommon chipid */
++#define BCM43458_CHIP_ID	43458		/* 43458 chipcommon chipid */
++
++#define BCM4345_CHIP(chipid)	(CHIPID(chipid) == BCM4345_CHIP_ID || \
++				 CHIPID(chipid) == BCM43454_CHIP_ID || \
++				 CHIPID(chipid) == BCM43455_CHIP_ID || \
++				 CHIPID(chipid) == BCM43457_CHIP_ID || \
++				 CHIPID(chipid) == BCM43458_CHIP_ID)
++
++#define CASE_BCM4345_CHIP	case BCM4345_CHIP_ID: /* fallthrough */ \
++				case BCM43454_CHIP_ID: /* fallthrough */ \
++				case BCM43455_CHIP_ID: /* fallthrough */ \
++				case BCM43457_CHIP_ID: /* fallthrough */ \
++				case BCM43458_CHIP_ID
++
++#define BCM43430_CHIP_ID	43430		/* 43430 chipcommon chipid */
++#define BCM43018_CHIP_ID	43018		/* 43018 chipcommon chipid */
++#define BCM4349_CHIP_ID		0x4349		/* 4349 chipcommon chipid */
++#define BCM4355_CHIP_ID		0x4355		/* 4355 chipcommon chipid */
++#define BCM4359_CHIP_ID		0x4359		/* 4359 chipcommon chipid */
++#define BCM4349_CHIP(chipid)	((CHIPID(chipid) == BCM4349_CHIP_ID) || \
++				(CHIPID(chipid) == BCM4355_CHIP_ID) || \
++				(CHIPID(chipid) == BCM4359_CHIP_ID))
++#define BCM4349_CHIP_GRPID		BCM4349_CHIP_ID: \
++					case BCM4355_CHIP_ID: \
++					case BCM4359_CHIP_ID
++#define BCM43596_CHIP_ID		43596		/* 43596 chipcommon chipid */
++#define BCM4347_CHIP_ID		0x4347          /* 4347 chipcommon chipid */
++#define BCM4357_CHIP_ID		0x4357          /* 4357 chipcommon chipid */
++#define BCM4361_CHIP_ID		0x4361          /* 4361 chipcommon chipid */
++#define BCM4362_CHIP_ID		0x4362          /* 4362 chipcommon chipid */
++#define BCM4347_CHIP(chipid)	((CHIPID(chipid) == BCM4347_CHIP_ID) || \
++				(CHIPID(chipid) == BCM4357_CHIP_ID) || \
++				(CHIPID(chipid) == BCM4361_CHIP_ID))
++#define BCM4347_CHIP_GRPID		BCM4347_CHIP_ID: \
++					case BCM4357_CHIP_ID: \
++					case BCM4361_CHIP_ID
++
++#define BCM4365_CHIP_ID		0x4365		/* 4365 chipcommon chipid */
++#define BCM4366_CHIP_ID		0x4366		/* 4366 chipcommon chipid */
++#define BCM4365_CHIP(chipid)	((CHIPID(chipid) == BCM4365_CHIP_ID) || \
++				(CHIPID(chipid) == BCM4366_CHIP_ID))
++
++
++#define BCM43909_CHIP_ID	0xab85		/* 43909 chipcommon chipid */
++
++#define BCM43602_CHIP_ID	0xaa52		/* 43602 chipcommon chipid */
++#define BCM43462_CHIP_ID	0xa9c6		/* 43462 chipcommon chipid */
++#define BCM43522_CHIP_ID	0xaa02		/* 43522 chipcommon chipid */
++#define BCM43602_CHIP(chipid)	((CHIPID(chipid) == BCM43602_CHIP_ID) || \
++				(CHIPID(chipid) == BCM43462_CHIP_ID) || \
++				(CHIPID(chipid) == BCM43522_CHIP_ID)) /* 43602 variations */
++#define BCM43012_CHIP(chipid)	(CHIPID(chipid) == BCM43012_CHIP_ID)
++#define CASE_BCM43602_CHIP		case BCM43602_CHIP_ID: /* fallthrough */ \
++				case BCM43462_CHIP_ID: /* fallthrough */ \
++				case BCM43522_CHIP_ID
++
++#define	BCM4402_CHIP_ID		0x4402		/* 4402 chipid */
++#define	BCM4704_CHIP_ID		0x4704		/* 4704 chipcommon chipid */
++#define	BCM4706_CHIP_ID		0x5300		/* 4706 chipcommon chipid */
++#define BCM4707_CHIP_ID		53010		/* 4707 chipcommon chipid */
++#define BCM47094_CHIP_ID	53030		/* 47094 chipcommon chipid */
++#define BCM53018_CHIP_ID	53018		/* 53018 chipcommon chipid */
++#define BCM4707_CHIP(chipid)	(((chipid) == BCM4707_CHIP_ID) || \
++				((chipid) == BCM53018_CHIP_ID) || \
++				((chipid) == BCM47094_CHIP_ID))
++#define	BCM4710_CHIP_ID		0x4710		/* 4710 chipid */
++#define	BCM4749_CHIP_ID		0x4749		/* 5357 chipcommon chipid (OTP, RBBU) */
++#define BCM4785_CHIP_ID		0x4785		/* 4785 chipcommon chipid */
++#define	BCM5350_CHIP_ID		0x5350		/* 5350 chipcommon chipid */
++#define	BCM5352_CHIP_ID		0x5352		/* 5352 chipcommon chipid */
++#define BCM5365_CHIP_ID		0x5365		/* 5365 chipcommon chipid */
++#define	BCM5356_CHIP_ID		0x5356		/* 5356 chipcommon chipid */
++#define	BCM5357_CHIP_ID		0x5357		/* 5357 chipcommon chipid */
++#define	BCM53572_CHIP_ID	53572		/* 53572 chipcommon chipid */
++#define	BCM53573_CHIP_ID	53573		/* 53573 chipcommon chipid */
++#define	BCM53574_CHIP_ID	53574		/* 53574 chipcommon chipid */
++#define BCM53573_CHIP(chipid)	((CHIPID(chipid) == BCM53573_CHIP_ID) || \
++				(CHIPID(chipid) == BCM53574_CHIP_ID))
++#define BCM53573_CHIP_GRPID	BCM53573_CHIP_ID : \
++			        case BCM53574_CHIP_ID
++#define BCM53573_DEVICE(devid)	(((devid) == BCM53573_D11AC_ID) || \
++				((devid) == BCM53573_D11AC2G_ID) || \
++				((devid) == BCM53573_D11AC5G_ID) || \
++				((devid) == BCM47189_D11AC_ID) || \
++				((devid) == BCM47189_D11AC2G_ID) || \
++				((devid) == BCM47189_D11AC5G_ID))
++
++#define	BCM7271_CHIP_ID		0x05c9		/* 7271 chipcommon chipid */
++#define	BCM4373_CHIP_ID		0x4373		/* 4373 chipcommon chipid */
++
++/* Package IDs */
++#ifdef DEPRECATED /* These products have been deprecated */
++#define	BCM4303_PKG_ID		2		/* 4303 package id */
++#define	BCM4309_PKG_ID		1		/* 4309 package id */
++#define	BCM4712LARGE_PKG_ID	0		/* 340pin 4712 package id */
++#define	BCM4712SMALL_PKG_ID	1		/* 200pin 4712 package id */
++#define	BCM4712MID_PKG_ID	2		/* 225pin 4712 package id */
++#define BCM4328USBD11G_PKG_ID	2		/* 4328 802.11g USB package id */
++#define BCM4328USBDUAL_PKG_ID	3		/* 4328 802.11a/g USB package id */
++#define BCM4328SDIOD11G_PKG_ID	4		/* 4328 802.11g SDIO package id */
++#define BCM4328SDIODUAL_PKG_ID	5		/* 4328 802.11a/g SDIO package id */
++#define BCM4329_289PIN_PKG_ID	0		/* 4329 289-pin package id */
++#define BCM4329_182PIN_PKG_ID	1		/* 4329N 182-pin package id */
++#define BCM5354E_PKG_ID		1		/* 5354E package id */
++#define	BCM4716_PKG_ID		8		/* 4716 package id */
++#define	BCM4717_PKG_ID		9		/* 4717 package id */
++#define	BCM4718_PKG_ID		10		/* 4718 package id */
++#endif  /* DEPRECATED */
++#define BCM5356_PKG_NONMODE	1		/* 5356 package without nmode suppport */
++#define BCM5358U_PKG_ID		8		/* 5358U package id */
++#define BCM5358_PKG_ID		9		/* 5358 package id */
++#define BCM47186_PKG_ID		10		/* 47186 package id */
++#define BCM5357_PKG_ID		11		/* 5357 package id */
++#define BCM5356U_PKG_ID		12		/* 5356U package id */
++#define BCM53572_PKG_ID		8		/* 53572 package id */
++#define BCM5357C0_PKG_ID	8		/* 5357c0 package id (the same as 53572) */
++#define BCM47188_PKG_ID		9		/* 47188 package id */
++#define BCM5358C0_PKG_ID	0xa		/* 5358c0 package id */
++#define BCM5356C0_PKG_ID	0xb		/* 5356c0 package id */
++#define BCM4331TT_PKG_ID        8		/* 4331 12x12 package id */
++#define BCM4331TN_PKG_ID        9		/* 4331 12x9 package id */
++#define BCM4331TNA0_PKG_ID     0xb		/* 4331 12x9 package id */
++#define BCM47189_PKG_ID		1		/* 47189 package id */
++#define BCM53573_PKG_ID		0		/* 53573 package id */
++#define	BCM4706L_PKG_ID		1		/* 4706L package id */
++
++#define HDLSIM5350_PKG_ID	1		/* HDL simulator package id for a 5350 */
++#define HDLSIM_PKG_ID		14		/* HDL simulator package id */
++#define HWSIM_PKG_ID		15		/* Hardware simulator package id */
++#define BCM43224_FAB_CSM	0x8		/* the chip is manufactured by CSM */
++#define BCM43224_FAB_SMIC	0xa		/* the chip is manufactured by SMIC */
++#define BCM4336_WLBGA_PKG_ID	0x8
++#define BCM4330_WLBGA_PKG_ID	0x0
++#define BCM4314PCIE_ARM_PKG_ID		(8 | 0)	/* 4314 QFN PCI package id, bit 3 tie high */
++#define BCM4314SDIO_PKG_ID		(8 | 1)	/* 4314 QFN SDIO package id */
++#define BCM4314PCIE_PKG_ID		(8 | 2)	/* 4314 QFN PCI (ARM-less) package id */
++#define BCM4314SDIO_ARM_PKG_ID		(8 | 3)	/* 4314 QFN SDIO (ARM-less) package id */
++#define BCM4314SDIO_FPBGA_PKG_ID	(8 | 4)	/* 4314 FpBGA SDIO package id */
++#define BCM4314DEV_PKG_ID		(8 | 6)	/* 4314 Developement package id */
++
++#define BCM4707_PKG_ID		1		/* 4707 package id */
++#define BCM4708_PKG_ID		2		/* 4708 package id */
++#define BCM4709_PKG_ID		0		/* 4709 package id */
++
++#define PCIXX21_FLASHMEDIA0_ID	0x8033		/* TI PCI xx21 Standard Host Controller */
++#define PCIXX21_SDIOH0_ID	0x8034		/* TI PCI xx21 Standard Host Controller */
++
++#define BCM4335_WLCSP_PKG_ID	(0x0)	/* WLCSP Module/Mobile SDIO/HSIC. */
++#define BCM4335_FCBGA_PKG_ID	(0x1)	/* FCBGA PC/Embeded/Media PCIE/SDIO */
++#define BCM4335_WLBGA_PKG_ID	(0x2)	/* WLBGA COB/Mobile SDIO/HSIC. */
++#define BCM4335_FCBGAD_PKG_ID	(0x3)	/* FCBGA Debug Debug/Dev All if's. */
++#define BCM4335_PKG_MASK	(0x3)
++#define BCM43602_12x12_PKG_ID	(0x1)	/* 12x12 pins package, used for e.g. router designs */
++
++/* boardflags */
++#define	BFL_BTC2WIRE		0x00000001  /* old 2wire Bluetooth coexistence, OBSOLETE */
++#define BFL_BTCOEX      0x00000001      /* Board supports BTCOEX */
++#define	BFL_PACTRL		0x00000002  /* Board has gpio 9 controlling the PA */
++#define BFL_AIRLINEMODE	0x00000004  /* Board implements gpio radio disable indication */
++#define	BFL_ADCDIV		0x00000008  /* Board has the rssi ADC divider */
++#define BFL_DIS_256QAM		0x00000008
++#define	BFL_ENETROBO		0x00000010  /* Board has robo switch or core */
++#define	BFL_TSSIAVG   		0x00000010  /* TSSI averaging for ACPHY chips */
++#define	BFL_NOPLLDOWN		0x00000020  /* Not ok to power down the chip pll and oscillator */
++#define	BFL_CCKHIPWR		0x00000040  /* Can do high-power CCK transmission */
++#define	BFL_ENETADM		0x00000080  /* Board has ADMtek switch */
++#define	BFL_ENETVLAN		0x00000100  /* Board has VLAN capability */
++#define	BFL_LTECOEX		0x00000200  /* LTE Coex enabled */
++#define BFL_NOPCI		0x00000400  /* Board leaves PCI floating */
++#define BFL_FEM			0x00000800  /* Board supports the Front End Module */
++#define BFL_EXTLNA		0x00001000  /* Board has an external LNA in 2.4GHz band */
++#define BFL_HGPA		0x00002000  /* Board has a high gain PA */
++#define	BFL_BTC2WIRE_ALTGPIO	0x00004000  /* Board's BTC 2wire is in the alternate gpios */
++#define	BFL_ALTIQ		0x00008000  /* Alternate I/Q settings */
++#define BFL_NOPA		0x00010000  /* Board has no PA */
++#define BFL_RSSIINV		0x00020000  /* Board's RSSI uses positive slope(not TSSI) */
++#define BFL_PAREF		0x00040000  /* Board uses the PARef LDO */
++#define BFL_3TSWITCH		0x00080000  /* Board uses a triple throw switch shared with BT */
++#define BFL_PHASESHIFT		0x00100000  /* Board can support phase shifter */
++#define BFL_BUCKBOOST		0x00200000  /* Power topology uses BUCKBOOST */
++#define BFL_FEM_BT		0x00400000  /* Board has FEM and switch to share antenna w/ BT */
++#define BFL_NOCBUCK		0x00800000  /* Power topology doesn't use CBUCK */
++#define BFL_CCKFAVOREVM		0x01000000  /* Favor CCK EVM over spectral mask */
++#define BFL_PALDO		0x02000000  /* Power topology uses PALDO */
++#define BFL_LNLDO2_2P5		0x04000000  /* Select 2.5V as LNLDO2 output voltage */
++#define BFL_FASTPWR		0x08000000
++#define BFL_UCPWRCTL_MININDX	0x08000000  /* Enforce min power index to avoid FEM damage */
++#define BFL_EXTLNA_5GHz		0x10000000  /* Board has an external LNA in 5GHz band */
++#define BFL_TRSW_1by2		0x20000000  /* Board has 2 TRSW's in 1by2 designs */
++#define BFL_GAINBOOSTA01        0x20000000  /* 5g Gainboost for core0 and core1 */
++#define BFL_LO_TRSW_R_5GHz	0x40000000  /* In 5G do not throw TRSW to T for clipLO gain */
++#define BFL_ELNA_GAINDEF	0x80000000  /* Backoff InitGain based on elna_2g/5g field
++					     * when this flag is set
++					     */
++#define BFL_EXTLNA_TX	0x20000000	/* Temp boardflag to indicate to */
++
++/* boardflags2 */
++#define BFL2_RXBB_INT_REG_DIS	0x00000001  /* Board has an external rxbb regulator */
++#define BFL2_APLL_WAR		0x00000002  /* Flag to implement alternative A-band PLL settings */
++#define BFL2_TXPWRCTRL_EN	0x00000004  /* Board permits enabling TX Power Control */
++#define BFL2_2X4_DIV		0x00000008  /* Board supports the 2X4 diversity switch */
++#define BFL2_5G_PWRGAIN		0x00000010  /* Board supports 5G band power gain */
++#define BFL2_PCIEWAR_OVR	0x00000020  /* Board overrides ASPM and Clkreq settings */
++#define BFL2_CAESERS_BRD	0x00000040  /* Board is Caesers brd (unused by sw) */
++#define BFL2_BTC3WIRE		0x00000080  /* Board support legacy 3 wire or 4 wire */
++#define BFL2_BTCLEGACY          0x00000080  /* Board support legacy 3/4 wire, to replace
++					     * BFL2_BTC3WIRE
++					     */
++#define BFL2_SKWRKFEM_BRD	0x00000100  /* 4321mcm93 board uses Skyworks FEM */
++#define BFL2_SPUR_WAR		0x00000200  /* Board has a WAR for clock-harmonic spurs */
++#define BFL2_GPLL_WAR		0x00000400  /* Flag to narrow G-band PLL loop b/w */
++#define BFL2_TRISTATE_LED	0x00000800  /* Tri-state the LED */
++#define BFL2_SINGLEANT_CCK	0x00001000  /* Tx CCK pkts on Ant 0 only */
++#define BFL2_2G_SPUR_WAR	0x00002000  /* WAR to reduce and avoid clock-harmonic spurs in 2G */
++#define BFL2_BPHY_ALL_TXCORES	0x00004000  /* Transmit bphy frames using all tx cores */
++#define BFL2_FCC_BANDEDGE_WAR	0x00008000  /* Activates WAR to improve FCC bandedge performance */
++#define BFL2_DAC_SPUR_IMPROVEMENT 0x00008000       /* Reducing DAC Spurs */
++#define BFL2_GPLL_WAR2	        0x00010000  /* Flag to widen G-band PLL loop b/w */
++#define BFL2_REDUCED_PA_TURNONTIME 0x00010000  /* Flag to reduce PA turn on Time */
++#define BFL2_IPALVLSHIFT_3P3    0x00020000
++#define BFL2_INTERNDET_TXIQCAL  0x00040000  /* Use internal envelope detector for TX IQCAL */
++#define BFL2_XTALBUFOUTEN       0x00080000  /* Keep the buffered Xtal output from radio on */
++				/* Most drivers will turn it off without this flag */
++				/* to save power. */
++
++#define BFL2_ANAPACTRL_2G	0x00100000  /* 2G ext PAs are controlled by analog PA ctrl lines */
++#define BFL2_ANAPACTRL_5G	0x00200000  /* 5G ext PAs are controlled by analog PA ctrl lines */
++#define BFL2_ELNACTRL_TRSW_2G	0x00400000  /* AZW4329: 2G gmode_elna_gain controls TR Switch */
++#define BFL2_BT_SHARE_ANT0	0x00800000  /* share core0 antenna with BT */
++#define BFL2_TEMPSENSE_HIGHER	0x01000000  /* The tempsense threshold can sustain higher value
++					     * than programmed. The exact delta is decided by
++					     * driver per chip/boardtype. This can be used
++					     * when tempsense qualification happens after shipment
++					     */
++#define BFL2_BTC3WIREONLY       0x02000000  /* standard 3 wire btc only.  4 wire not supported */
++#define BFL2_PWR_NOMINAL	0x04000000  /* 0: power reduction on, 1: no power reduction */
++#define BFL2_EXTLNA_PWRSAVE	0x08000000  /* boardflag to enable ucode to apply power save */
++						/* ucode control of eLNA during Tx */
++#define BFL2_4313_RADIOREG	0x10000000
++									   /*  board rework */
++#define BFL2_DYNAMIC_VMID	0x10000000  /* enable dynamic Vmid in idle TSSI CAL for 4331 */
++
++#define BFL2_SDR_EN		0x20000000  /* SDR enabled or disabled */
++#define BFL2_DYNAMIC_VMID	0x10000000  /* boardflag to enable dynamic Vmid idle TSSI CAL */
++#define BFL2_LNA1BYPFORTR2G	0x40000000  /* acphy, enable lna1 bypass for clip gain, 2g */
++#define BFL2_LNA1BYPFORTR5G	0x80000000  /* acphy, enable lna1 bypass for clip gain, 5g */
++
++/* SROM 11 - 11ac boardflag definitions */
++#define BFL_SROM11_BTCOEX  0x00000001  /* Board supports BTCOEX */
++#define BFL_SROM11_WLAN_BT_SH_XTL  0x00000002  /* bluetooth and wlan share same crystal */
++#define BFL_SROM11_EXTLNA	0x00001000  /* Board has an external LNA in 2.4GHz band */
++#define BFL_SROM11_EPA_TURNON_TIME     0x00018000  /* 2 bits for different PA turn on times */
++#define BFL_SROM11_EPA_TURNON_TIME_SHIFT  15
++#define BFL_SROM11_PRECAL_TX_IDX	0x00040000  /* Dedicated TX IQLOCAL IDX values */
++				/* per subband, as derived from 43602A1 MCH5 */
++#define BFL_SROM11_EXTLNA_5GHz	0x10000000  /* Board has an external LNA in 5GHz band */
++#define BFL_SROM11_GAINBOOSTA01	0x20000000  /* 5g Gainboost for core0 and core1 */
++#define BFL2_SROM11_APLL_WAR	0x00000002  /* Flag to implement alternative A-band PLL settings */
++#define BFL2_SROM11_ANAPACTRL_2G  0x00100000  /* 2G ext PAs are ctrl-ed by analog PA ctrl lines */
++#define BFL2_SROM11_ANAPACTRL_5G  0x00200000  /* 5G ext PAs are ctrl-ed by analog PA ctrl lines */
++#define BFL2_SROM11_SINGLEANT_CCK	0x00001000  /* Tx CCK pkts on Ant 0 only */
++#define BFL2_SROM11_EPA_ON_DURING_TXIQLOCAL    0x00020000  /* Keep ext. PA's on in TX IQLO CAL */
++
++/* boardflags3 */
++#define BFL3_FEMCTRL_SUB	  0x00000007  /* acphy, subrevs of femctrl on top of srom_femctrl */
++#define BFL3_RCAL_WAR		  0x00000008  /* acphy, rcal war active on this board (4335a0) */
++#define BFL3_TXGAINTBLID	  0x00000070  /* acphy, txgain table id */
++#define BFL3_TXGAINTBLID_SHIFT	  0x4         /* acphy, txgain table id shift bit */
++#define BFL3_TSSI_DIV_WAR	  0x00000080  /* acphy, Seperate paparam for 20/40/80 */
++#define BFL3_TSSI_DIV_WAR_SHIFT	  0x7         /* acphy, Seperate paparam for 20/40/80 shift bit */
++#define BFL3_FEMTBL_FROM_NVRAM    0x00000100  /* acphy, femctrl table is read from nvram */
++#define BFL3_FEMTBL_FROM_NVRAM_SHIFT 0x8         /* acphy, femctrl table is read from nvram */
++#define BFL3_AGC_CFG_2G           0x00000200  /* acphy, gain control configuration for 2G */
++#define BFL3_AGC_CFG_5G           0x00000400  /* acphy, gain control configuration for 5G */
++#define BFL3_PPR_BIT_EXT          0x00000800  /* acphy, bit position for 1bit extension for ppr */
++#define BFL3_PPR_BIT_EXT_SHIFT    11          /* acphy, bit shift for 1bit extension for ppr */
++#define BFL3_BBPLL_SPR_MODE_DIS	  0x00001000  /* acphy, disables bbpll spur modes */
++#define BFL3_RCAL_OTP_VAL_EN      0x00002000  /* acphy, to read rcal_trim value from otp */
++#define BFL3_2GTXGAINTBL_BLANK	  0x00004000  /* acphy, blank the first X ticks of 2g gaintbl */
++#define BFL3_2GTXGAINTBL_BLANK_SHIFT 14       /* acphy, blank the first X ticks of 2g gaintbl */
++#define BFL3_5GTXGAINTBL_BLANK	  0x00008000  /* acphy, blank the first X ticks of 5g gaintbl */
++#define BFL3_5GTXGAINTBL_BLANK_SHIFT 15       /* acphy, blank the first X ticks of 5g gaintbl */
++#define BFL3_PHASETRACK_MAX_ALPHABETA	  0x00010000  /* acphy, to max out alpha,beta to 511 */
++#define BFL3_PHASETRACK_MAX_ALPHABETA_SHIFT 16       /* acphy, to max out alpha,beta to 511 */
++/* acphy, to use backed off gaintbl for lte-coex */
++#define BFL3_LTECOEX_GAINTBL_EN           0x00060000
++/* acphy, to use backed off gaintbl for lte-coex */
++#define BFL3_LTECOEX_GAINTBL_EN_SHIFT 17
++#define BFL3_5G_SPUR_WAR          0x00080000  /* acphy, enable spur WAR in 5G band */
++#define BFL3_1X1_RSDB_ANT	  0x01000000  /* to find if 2-ant RSDB board or 1-ant RSDB board */
++#define BFL3_1X1_RSDB_ANT_SHIFT           24
++
++/* acphy: lpmode2g and lpmode_5g related boardflags */
++#define BFL3_ACPHY_LPMODE_2G	  0x00300000  /* bits 20:21 for lpmode_2g choice */
++#define BFL3_ACPHY_LPMODE_2G_SHIFT	  20
++
++#define BFL3_ACPHY_LPMODE_5G	  0x00C00000  /* bits 22:23 for lpmode_5g choice */
++#define BFL3_ACPHY_LPMODE_5G_SHIFT	  22
++
++#define BFL3_EXT_LPO_ISCLOCK      0x02000000  /* External LPO is clock, not x-tal */
++#define BFL3_FORCE_INT_LPO_SEL    0x04000000  /* Force internal lpo */
++#define BFL3_FORCE_EXT_LPO_SEL    0x08000000  /* Force external lpo */
++
++#define BFL3_EN_BRCM_IMPBF        0x10000000  /* acphy, Allow BRCM Implicit TxBF */
++#define BFL3_AVVMID_FROM_NVRAM    0x40000000  /* Read Av Vmid from NVRAM  */
++#define BFL3_VLIN_EN_FROM_NVRAM    0x80000000  /* Read Vlin En from NVRAM  */
++
++#define BFL3_AVVMID_FROM_NVRAM_SHIFT   30   /* Read Av Vmid from NVRAM  */
++#define BFL3_VLIN_EN_FROM_NVRAM_SHIFT   31   /* Enable Vlin  from NVRAM  */
++
++/* boardflags4 for SROM12 */
++#define BFL4_SROM12_4dBPAD      (1 << 0)   /* To distinguigh between normal and 4dB pad board */
++#define BFL4_SROM12_2G_DETTYPE      (1 << 1)   /* Determine power detector type for 2G */
++#define BFL4_SROM12_5G_DETTYPE      (1 << 2)   /* Determine power detector type for 5G */
++#define BFL4_4364_HARPOON 0x0100   /* Harpoon module 4364 */
++#define BFL4_4364_GODZILLA 0x0200   /* Godzilla module 4364 */
++
++
++/* papd params */
++#define PAPD_TX_ATTN_2G 0xFF
++#define PAPD_TX_ATTN_5G 0xFF00
++#define PAPD_TX_ATTN_5G_SHIFT 8
++#define PAPD_RX_ATTN_2G 0xFF
++#define PAPD_RX_ATTN_5G 0xFF00
++#define PAPD_RX_ATTN_5G_SHIFT 8
++#define PAPD_CAL_IDX_2G 0xFF
++#define PAPD_CAL_IDX_5G 0xFF00
++#define PAPD_CAL_IDX_5G_SHIFT 8
++#define PAPD_BBMULT_2G 0xFF
++#define PAPD_BBMULT_5G 0xFF00
++#define PAPD_BBMULT_5G_SHIFT 8
++#define TIA_GAIN_MODE_2G 0xFF
++#define TIA_GAIN_MODE_5G 0xFF00
++#define TIA_GAIN_MODE_5G_SHIFT 8
++#define PAPD_EPS_OFFSET_2G 0xFFFF
++#define PAPD_EPS_OFFSET_5G 0xFFFF0000
++#define PAPD_EPS_OFFSET_5G_SHIFT 16
++#define PAPD_CALREF_DB_2G 0xFF
++#define PAPD_CALREF_DB_5G 0xFF00
++#define PAPD_CALREF_DB_5G_SHIFT 8
++
++
++/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
++#define	BOARD_GPIO_BTC3W_IN	0x850	/* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */
++#define	BOARD_GPIO_BTC3W_OUT	0x020	/* bit 5 is TX_CONF */
++#define	BOARD_GPIO_BTCMOD_IN	0x010	/* bit 4 is the alternate BT Coexistence Input */
++#define	BOARD_GPIO_BTCMOD_OUT	0x020	/* bit 5 is the alternate BT Coexistence Out */
++#define	BOARD_GPIO_BTC_IN	0x080	/* bit 7 is BT Coexistence Input */
++#define	BOARD_GPIO_BTC_OUT	0x100	/* bit 8 is BT Coexistence Out */
++#define	BOARD_GPIO_PACTRL	0x200	/* bit 9 controls the PA on new 4306 boards */
++#define BOARD_GPIO_12		0x1000	/* gpio 12 */
++#define BOARD_GPIO_13		0x2000	/* gpio 13 */
++#define BOARD_GPIO_BTC4_IN	0x0800	/* gpio 11, coex4, in */
++#define BOARD_GPIO_BTC4_BT	0x2000	/* gpio 12, coex4, bt active */
++#define BOARD_GPIO_BTC4_STAT	0x4000	/* gpio 14, coex4, status */
++#define BOARD_GPIO_BTC4_WLAN	0x8000	/* gpio 15, coex4, wlan active */
++#define	BOARD_GPIO_1_WLAN_PWR	0x02	/* throttle WLAN power on X21 board */
++#define	BOARD_GPIO_2_WLAN_PWR	0x04	/* throttle WLAN power on X29C board */
++#define	BOARD_GPIO_3_WLAN_PWR	0x08	/* throttle WLAN power on X28 board */
++#define	BOARD_GPIO_4_WLAN_PWR	0x10	/* throttle WLAN power on X19 board */
++#define	BOARD_GPIO_13_WLAN_PWR	0x2000	/* throttle WLAN power on X14 board */
++
++#define GPIO_BTC4W_OUT_4312  0x010  /* bit 4 is BT_IODISABLE */
++#define GPIO_BTC4W_OUT_43224  0x020  /* bit 5 is BT_IODISABLE */
++#define GPIO_BTC4W_OUT_43224_SHARED  0x0e0  /* bit 5 is BT_IODISABLE */
++#define GPIO_BTC4W_OUT_43225  0x0e0  /* bit 5 BT_IODISABLE, bit 6 SW_BT, bit 7 SW_WL */
++#define GPIO_BTC4W_OUT_43421  0x020  /* bit 5 is BT_IODISABLE */
++#define GPIO_BTC4W_OUT_4313  0x060  /* bit 5 SW_BT, bit 6 SW_WL */
++#define GPIO_BTC4W_OUT_4331_SHARED  0x010  /* GPIO 4  */
++
++#define	PCI_CFG_GPIO_SCS	0x10	/* PCI config space bit 4 for 4306c0 slow clock source */
++#define PCI_CFG_GPIO_HWRAD	0x20	/* PCI config space GPIO 13 for hw radio disable */
++#define PCI_CFG_GPIO_XTAL	0x40	/* PCI config space GPIO 14 for Xtal power-up */
++#define PCI_CFG_GPIO_PLL	0x80	/* PCI config space GPIO 15 for PLL power-down */
++
++/* power control defines */
++#define PLL_DELAY		150		/* us pll on delay */
++#define FREF_DELAY		200		/* us fref change delay */
++#define MIN_SLOW_CLK		32		/* us Slow clock period */
++#define	XTAL_ON_DELAY		1000		/* us crystal power-on delay */
++
++
++/* 43341 Boards */
++#define BCM943341WLABGS_SSID	0x062d
++
++/* 43342 Boards */
++#define BCM943342FCAGBI_SSID	0x0641
++
++/* 43012 wlbga Board */
++#define BCM943012WLREF_SSID	0x07d7
++
++/* 43012 fcbga Board */
++#define BCM943012FCREF_SSID	0x07d4
++
++/* 43602 Boards, unclear yet what boards will be created. */
++#define BCM943602RSVD1_SSID	0x06a5
++#define BCM943602RSVD2_SSID	0x06a6
++#define BCM943602X87            0X0133
++#define BCM943602X87P2          0X0152
++#define BCM943602X87P3          0X0153
++#define BCM943602X238           0X0132
++#define BCM943602X238D          0X014A
++#define BCM943602X238DP2        0X0155
++#define BCM943602X238DP3        0X0156
++#define BCM943602X100           0x0761
++#define BCM943602X100GS         0x0157
++#define BCM943602X100P2         0x015A
++
++/* # of GPIO pins */
++#define GPIO_NUMPINS		32
++
++/* These values are used by dhd host driver. */
++#define RDL_RAM_BASE_4319 0x60000000
++#define RDL_RAM_BASE_4329 0x60000000
++#define RDL_RAM_SIZE_4319 0x48000
++#define RDL_RAM_SIZE_4329  0x48000
++#define RDL_RAM_SIZE_43236 0x70000
++#define RDL_RAM_BASE_43236 0x60000000
++#define RDL_RAM_SIZE_4328 0x60000
++#define RDL_RAM_BASE_4328 0x80000000
++#define RDL_RAM_SIZE_4322 0x60000
++#define RDL_RAM_BASE_4322 0x60000000
++#define RDL_RAM_SIZE_4360  0xA0000
++#define RDL_RAM_BASE_4360  0x60000000
++#define RDL_RAM_SIZE_43242  0x90000
++#define RDL_RAM_BASE_43242  0x60000000
++#define RDL_RAM_SIZE_43143  0x70000
++#define RDL_RAM_BASE_43143  0x60000000
++#define RDL_RAM_SIZE_4350  0xC0000
++#define RDL_RAM_BASE_4350  0x180800
++
++/* generic defs for nvram "muxenab" bits
++* Note: these differ for 4335a0. refer bcmchipc.h for specific mux options.
++*/
++#define MUXENAB_UART		0x00000001
++#define MUXENAB_GPIO		0x00000002
++#define MUXENAB_ERCX		0x00000004	/* External Radio BT coex */
++#define MUXENAB_JTAG		0x00000008
++#define MUXENAB_HOST_WAKE	0x00000010	/* configure GPIO for SDIO host_wake */
++#define MUXENAB_I2S_EN		0x00000020
++#define MUXENAB_I2S_MASTER	0x00000040
++#define MUXENAB_I2S_FULL	0x00000080
++#define MUXENAB_SFLASH		0x00000100
++#define MUXENAB_RFSWCTRL0	0x00000200
++#define MUXENAB_RFSWCTRL1	0x00000400
++#define MUXENAB_RFSWCTRL2	0x00000800
++#define MUXENAB_SECI		0x00001000
++#define MUXENAB_BT_LEGACY	0x00002000
++#define MUXENAB_HOST_WAKE1	0x00004000	/* configure alternative GPIO for SDIO host_wake */
++
++/* Boot flags */
++#define FLASH_KERNEL_NFLASH	0x00000001
++#define FLASH_BOOT_NFLASH	0x00000002
++
++#endif /* _BCMDEVS_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmdhcp.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmdhcp.h
+new file mode 100644
+index 000000000..f3e1b08ed
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmdhcp.h
+@@ -0,0 +1,92 @@
++/*
++ * Fundamental constants relating to DHCP Protocol
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmdhcp.h 700076 2017-05-17 14:42:22Z $
++ */
++
++#ifndef _bcmdhcp_h_
++#define _bcmdhcp_h_
++
++/* DHCP params */
++#define DHCP_TYPE_OFFSET	0	/* DHCP type (request|reply) offset */
++#define DHCP_TID_OFFSET		4	/* DHCP transition id offset */
++#define DHCP_FLAGS_OFFSET	10	/* DHCP flags offset */
++#define DHCP_CIADDR_OFFSET	12	/* DHCP client IP address offset */
++#define DHCP_YIADDR_OFFSET	16	/* DHCP your IP address offset */
++#define DHCP_GIADDR_OFFSET	24	/* DHCP relay agent IP address offset */
++#define DHCP_CHADDR_OFFSET	28	/* DHCP client h/w address offset */
++#define DHCP_OPT_OFFSET		236	/* DHCP options offset */
++
++#define DHCP_OPT_MSGTYPE	53	/* DHCP message type */
++#define DHCP_OPT_MSGTYPE_REQ	3
++#define DHCP_OPT_MSGTYPE_ACK	5	/* DHCP message type - ACK */
++
++#define DHCP_OPT_CODE_OFFSET	0	/* Option identifier */
++#define DHCP_OPT_LEN_OFFSET	1	/* Option data length */
++#define DHCP_OPT_DATA_OFFSET	2	/* Option data */
++
++#define DHCP_OPT_CODE_CLIENTID	61	/* Option identifier */
++
++#define DHCP_TYPE_REQUEST	1	/* DHCP request (discover|request) */
++#define DHCP_TYPE_REPLY		2	/* DHCP reply (offset|ack) */
++
++#define DHCP_PORT_SERVER	67	/* DHCP server UDP port */
++#define DHCP_PORT_CLIENT	68	/* DHCP client UDP port */
++
++#define DHCP_FLAG_BCAST	0x8000	/* DHCP broadcast flag */
++
++#define DHCP_FLAGS_LEN	2	/* DHCP flags field length */
++
++#define DHCP6_TYPE_SOLICIT	1	/* DHCP6 solicit */
++#define DHCP6_TYPE_ADVERTISE	2	/* DHCP6 advertise */
++#define DHCP6_TYPE_REQUEST	3	/* DHCP6 request */
++#define DHCP6_TYPE_CONFIRM	4	/* DHCP6 confirm */
++#define DHCP6_TYPE_RENEW	5	/* DHCP6 renew */
++#define DHCP6_TYPE_REBIND	6	/* DHCP6 rebind */
++#define DHCP6_TYPE_REPLY	7	/* DHCP6 reply */
++#define DHCP6_TYPE_RELEASE	8	/* DHCP6 release */
++#define DHCP6_TYPE_DECLINE	9	/* DHCP6 decline */
++#define DHCP6_TYPE_RECONFIGURE	10	/* DHCP6 reconfigure */
++#define DHCP6_TYPE_INFOREQ	11	/* DHCP6 information request */
++#define DHCP6_TYPE_RELAYFWD	12	/* DHCP6 relay forward */
++#define DHCP6_TYPE_RELAYREPLY	13	/* DHCP6 relay reply */
++
++#define DHCP6_TYPE_OFFSET	0	/* DHCP6 type offset */
++
++#define	DHCP6_MSG_OPT_OFFSET	4	/* Offset of options in client server messages */
++#define	DHCP6_RELAY_OPT_OFFSET	34	/* Offset of options in relay messages */
++
++#define	DHCP6_OPT_CODE_OFFSET	0	/* Option identifier */
++#define	DHCP6_OPT_LEN_OFFSET	2	/* Option data length */
++#define	DHCP6_OPT_DATA_OFFSET	4	/* Option data */
++
++#define	DHCP6_OPT_CODE_CLIENTID	1	/* DHCP6 CLIENTID option */
++#define	DHCP6_OPT_CODE_SERVERID	2	/* DHCP6 SERVERID option */
++
++#define DHCP6_PORT_SERVER	547	/* DHCP6 server UDP port */
++#define DHCP6_PORT_CLIENT	546	/* DHCP6 client UDP port */
++
++#endif	/* #ifndef _bcmdhcp_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmendian.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmendian.h
+new file mode 100644
+index 000000000..00adedf1c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmendian.h
+@@ -0,0 +1,332 @@
++/*
++ * Byte order utilities
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ *  $Id: bcmendian.h 514727 2014-11-12 03:02:48Z $
++ *
++ * This file by default provides proper behavior on little-endian architectures.
++ * On big-endian architectures, IL_BIGENDIAN should be defined.
++ */
++
++#ifndef _BCMENDIAN_H_
++#define _BCMENDIAN_H_
++
++#include <typedefs.h>
++
++/* Reverse the bytes in a 16-bit value */
++#define BCMSWAP16(val) \
++	((uint16)((((uint16)(val) & (uint16)0x00ffU) << 8) | \
++		  (((uint16)(val) & (uint16)0xff00U) >> 8)))
++
++/* Reverse the bytes in a 32-bit value */
++#define BCMSWAP32(val) \
++	((uint32)((((uint32)(val) & (uint32)0x000000ffU) << 24) | \
++		  (((uint32)(val) & (uint32)0x0000ff00U) <<  8) | \
++		  (((uint32)(val) & (uint32)0x00ff0000U) >>  8) | \
++		  (((uint32)(val) & (uint32)0xff000000U) >> 24)))
++
++/* Reverse the two 16-bit halves of a 32-bit value */
++#define BCMSWAP32BY16(val) \
++	((uint32)((((uint32)(val) & (uint32)0x0000ffffU) << 16) | \
++		  (((uint32)(val) & (uint32)0xffff0000U) >> 16)))
++
++/* Reverse the bytes in a 64-bit value */
++#define BCMSWAP64(val) \
++	((uint64)((((uint64)(val) & 0x00000000000000ffULL) << 56) | \
++	          (((uint64)(val) & 0x000000000000ff00ULL) << 40) | \
++	          (((uint64)(val) & 0x0000000000ff0000ULL) << 24) | \
++	          (((uint64)(val) & 0x00000000ff000000ULL) <<  8) | \
++	          (((uint64)(val) & 0x000000ff00000000ULL) >>  8) | \
++	          (((uint64)(val) & 0x0000ff0000000000ULL) >> 24) | \
++	          (((uint64)(val) & 0x00ff000000000000ULL) >> 40) | \
++	          (((uint64)(val) & 0xff00000000000000ULL) >> 56)))
++
++/* Reverse the two 32-bit halves of a 64-bit value */
++#define BCMSWAP64BY32(val) \
++	((uint64)((((uint64)(val) & 0x00000000ffffffffULL) << 32) | \
++	          (((uint64)(val) & 0xffffffff00000000ULL) >> 32)))
++
++
++/* Byte swapping macros
++ *    Host <=> Network (Big Endian) for 16- and 32-bit values
++ *    Host <=> Little-Endian for 16- and 32-bit values
++ */
++#ifndef hton16
++#define HTON16(i) BCMSWAP16(i)
++#define	hton16(i) bcmswap16(i)
++#define	HTON32(i) BCMSWAP32(i)
++#define	hton32(i) bcmswap32(i)
++#define	NTOH16(i) BCMSWAP16(i)
++#define	ntoh16(i) bcmswap16(i)
++#define	NTOH32(i) BCMSWAP32(i)
++#define	ntoh32(i) bcmswap32(i)
++#define LTOH16(i) (i)
++#define ltoh16(i) (i)
++#define LTOH32(i) (i)
++#define ltoh32(i) (i)
++#define HTOL16(i) (i)
++#define htol16(i) (i)
++#define HTOL32(i) (i)
++#define htol32(i) (i)
++#define HTOL64(i) (i)
++#define htol64(i) (i)
++#endif /* hton16 */
++
++#define ltoh16_buf(buf, i)
++#define htol16_buf(buf, i)
++
++/* Unaligned loads and stores in host byte order */
++#define load32_ua(a)		ltoh32_ua(a)
++#define store32_ua(a, v)	htol32_ua_store(v, a)
++#define load16_ua(a)		ltoh16_ua(a)
++#define store16_ua(a, v)	htol16_ua_store(v, a)
++
++#define _LTOH16_UA(cp)	((cp)[0] | ((cp)[1] << 8))
++#define _LTOH32_UA(cp)	((cp)[0] | ((cp)[1] << 8) | ((cp)[2] << 16) | ((cp)[3] << 24))
++#define _NTOH16_UA(cp)	(((cp)[0] << 8) | (cp)[1])
++#define _NTOH32_UA(cp)	(((cp)[0] << 24) | ((cp)[1] << 16) | ((cp)[2] << 8) | (cp)[3])
++
++#define ltoh_ua(ptr) \
++	(sizeof(*(ptr)) == sizeof(uint8) ? *(const uint8 *)(ptr) : \
++	 sizeof(*(ptr)) == sizeof(uint16) ? _LTOH16_UA((const uint8 *)(ptr)) : \
++	 sizeof(*(ptr)) == sizeof(uint32) ? _LTOH32_UA((const uint8 *)(ptr)) : \
++	 *(uint8 *)0)
++
++#define ntoh_ua(ptr) \
++	(sizeof(*(ptr)) == sizeof(uint8) ? *(const uint8 *)(ptr) : \
++	 sizeof(*(ptr)) == sizeof(uint16) ? _NTOH16_UA((const uint8 *)(ptr)) : \
++	 sizeof(*(ptr)) == sizeof(uint32) ? _NTOH32_UA((const uint8 *)(ptr)) : \
++	 *(uint8 *)0)
++
++#ifdef __GNUC__
++
++/* GNU macro versions avoid referencing the argument multiple times, while also
++ * avoiding the -fno-inline used in ROM builds.
++ */
++
++#define bcmswap16(val) ({ \
++	uint16 _val = (val); \
++	BCMSWAP16(_val); \
++})
++
++#define bcmswap32(val) ({ \
++	uint32 _val = (val); \
++	BCMSWAP32(_val); \
++})
++
++#define bcmswap64(val) ({ \
++	uint64 _val = (val); \
++	BCMSWAP64(_val); \
++})
++
++#define bcmswap32by16(val) ({ \
++	uint32 _val = (val); \
++	BCMSWAP32BY16(_val); \
++})
++
++#define bcmswap16_buf(buf, len) ({ \
++	uint16 *_buf = (uint16 *)(buf); \
++	uint _wds = (len) / 2; \
++	while (_wds--) { \
++		*_buf = bcmswap16(*_buf); \
++		_buf++; \
++	} \
++})
++
++#define htol16_ua_store(val, bytes) ({ \
++	uint16 _val = (val); \
++	uint8 *_bytes = (uint8 *)(bytes); \
++	_bytes[0] = _val & 0xff; \
++	_bytes[1] = _val >> 8; \
++})
++
++#define htol32_ua_store(val, bytes) ({ \
++	uint32 _val = (val); \
++	uint8 *_bytes = (uint8 *)(bytes); \
++	_bytes[0] = _val & 0xff; \
++	_bytes[1] = (_val >> 8) & 0xff; \
++	_bytes[2] = (_val >> 16) & 0xff; \
++	_bytes[3] = _val >> 24; \
++})
++
++#define hton16_ua_store(val, bytes) ({ \
++	uint16 _val = (val); \
++	uint8 *_bytes = (uint8 *)(bytes); \
++	_bytes[0] = _val >> 8; \
++	_bytes[1] = _val & 0xff; \
++})
++
++#define hton32_ua_store(val, bytes) ({ \
++	uint32 _val = (val); \
++	uint8 *_bytes = (uint8 *)(bytes); \
++	_bytes[0] = _val >> 24; \
++	_bytes[1] = (_val >> 16) & 0xff; \
++	_bytes[2] = (_val >> 8) & 0xff; \
++	_bytes[3] = _val & 0xff; \
++})
++
++#define ltoh16_ua(bytes) ({ \
++	const uint8 *_bytes = (const uint8 *)(bytes); \
++	_LTOH16_UA(_bytes); \
++})
++
++#define ltoh32_ua(bytes) ({ \
++	const uint8 *_bytes = (const uint8 *)(bytes); \
++	_LTOH32_UA(_bytes); \
++})
++
++#define ntoh16_ua(bytes) ({ \
++	const uint8 *_bytes = (const uint8 *)(bytes); \
++	_NTOH16_UA(_bytes); \
++})
++
++#define ntoh32_ua(bytes) ({ \
++	const uint8 *_bytes = (const uint8 *)(bytes); \
++	_NTOH32_UA(_bytes); \
++})
++
++#else /* !__GNUC__ */
++
++/* Inline versions avoid referencing the argument multiple times */
++static INLINE uint16
++bcmswap16(uint16 val)
++{
++	return BCMSWAP16(val);
++}
++
++static INLINE uint32
++bcmswap32(uint32 val)
++{
++	return BCMSWAP32(val);
++}
++
++static INLINE uint64
++bcmswap64(uint64 val)
++{
++	return BCMSWAP64(val);
++}
++
++static INLINE uint32
++bcmswap32by16(uint32 val)
++{
++	return BCMSWAP32BY16(val);
++}
++
++/* Reverse pairs of bytes in a buffer (not for high-performance use) */
++/* buf	- start of buffer of shorts to swap */
++/* len  - byte length of buffer */
++static INLINE void
++bcmswap16_buf(uint16 *buf, uint len)
++{
++	len = len / 2;
++
++	while (len--) {
++		*buf = bcmswap16(*buf);
++		buf++;
++	}
++}
++
++/*
++ * Store 16-bit value to unaligned little-endian byte array.
++ */
++static INLINE void
++htol16_ua_store(uint16 val, uint8 *bytes)
++{
++	bytes[0] = val & 0xff;
++	bytes[1] = val >> 8;
++}
++
++/*
++ * Store 32-bit value to unaligned little-endian byte array.
++ */
++static INLINE void
++htol32_ua_store(uint32 val, uint8 *bytes)
++{
++	bytes[0] = val & 0xff;
++	bytes[1] = (val >> 8) & 0xff;
++	bytes[2] = (val >> 16) & 0xff;
++	bytes[3] = val >> 24;
++}
++
++/*
++ * Store 16-bit value to unaligned network-(big-)endian byte array.
++ */
++static INLINE void
++hton16_ua_store(uint16 val, uint8 *bytes)
++{
++	bytes[0] = val >> 8;
++	bytes[1] = val & 0xff;
++}
++
++/*
++ * Store 32-bit value to unaligned network-(big-)endian byte array.
++ */
++static INLINE void
++hton32_ua_store(uint32 val, uint8 *bytes)
++{
++	bytes[0] = val >> 24;
++	bytes[1] = (val >> 16) & 0xff;
++	bytes[2] = (val >> 8) & 0xff;
++	bytes[3] = val & 0xff;
++}
++
++/*
++ * Load 16-bit value from unaligned little-endian byte array.
++ */
++static INLINE uint16
++ltoh16_ua(const void *bytes)
++{
++	return _LTOH16_UA((const uint8 *)bytes);
++}
++
++/*
++ * Load 32-bit value from unaligned little-endian byte array.
++ */
++static INLINE uint32
++ltoh32_ua(const void *bytes)
++{
++	return _LTOH32_UA((const uint8 *)bytes);
++}
++
++/*
++ * Load 16-bit value from unaligned big-(network-)endian byte array.
++ */
++static INLINE uint16
++ntoh16_ua(const void *bytes)
++{
++	return _NTOH16_UA((const uint8 *)bytes);
++}
++
++/*
++ * Load 32-bit value from unaligned big-(network-)endian byte array.
++ */
++static INLINE uint32
++ntoh32_ua(const void *bytes)
++{
++	return _NTOH32_UA((const uint8 *)bytes);
++}
++
++#endif /* !__GNUC__ */
++#endif /* !_BCMENDIAN_H_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmeth.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmeth.h
+new file mode 100644
+index 000000000..e1d2d6669
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmeth.h
+@@ -0,0 +1,117 @@
++/*
++ * Broadcom Ethernettype  protocol definitions
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmeth.h 701825 2017-05-26 16:45:27Z $
++ */
++
++/*
++ * Broadcom Ethernet protocol defines
++ */
++
++#ifndef _BCMETH_H_
++#define _BCMETH_H_
++
++#ifndef _TYPEDEFS_H_
++#include <typedefs.h>
++#endif
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++
++/* ETHER_TYPE_BRCM is defined in ethernet.h */
++
++/*
++ * Following the 2byte BRCM ether_type is a 16bit BRCM subtype field
++ * in one of two formats: (only subtypes 32768-65535 are in use now)
++ *
++ * subtypes 0-32767:
++ *     8 bit subtype (0-127)
++ *     8 bit length in bytes (0-255)
++ *
++ * subtypes 32768-65535:
++ *     16 bit big-endian subtype
++ *     16 bit big-endian length in bytes (0-65535)
++ *
++ * length is the number of additional bytes beyond the 4 or 6 byte header
++ *
++ * Reserved values:
++ * 0 reserved
++ * 5-15 reserved for iLine protocol assignments
++ * 17-126 reserved, assignable
++ * 127 reserved
++ * 32768 reserved
++ * 32769-65534 reserved, assignable
++ * 65535 reserved
++ */
++
++/*
++ * While adding the subtypes and their specific processing code make sure
++ * bcmeth_bcm_hdr_t is the first data structure in the user specific data structure definition
++ */
++
++#define	BCMILCP_SUBTYPE_RATE		1
++#define	BCMILCP_SUBTYPE_LINK		2
++#define	BCMILCP_SUBTYPE_CSA		3
++#define	BCMILCP_SUBTYPE_LARQ		4
++#define BCMILCP_SUBTYPE_VENDOR		5
++#define	BCMILCP_SUBTYPE_FLH		17
++
++#define BCMILCP_SUBTYPE_VENDOR_LONG	32769
++#define BCMILCP_SUBTYPE_CERT		32770
++#define BCMILCP_SUBTYPE_SES		32771
++
++
++#define BCMILCP_BCM_SUBTYPE_RESERVED		0
++#define BCMILCP_BCM_SUBTYPE_EVENT		1
++#define BCMILCP_BCM_SUBTYPE_SES			2
++/*
++ * The EAPOL type is not used anymore. Instead EAPOL messages are now embedded
++ * within BCMILCP_BCM_SUBTYPE_EVENT type messages
++ */
++/* #define BCMILCP_BCM_SUBTYPE_EAPOL		3 */
++#define BCMILCP_BCM_SUBTYPE_DPT                 4
++#define BCMILCP_BCM_SUBTYPE_DNGLEVENT       5
++
++#define BCMILCP_BCM_SUBTYPEHDR_MINLENGTH	8
++#define BCMILCP_BCM_SUBTYPEHDR_VERSION		0
++#define BCMILCP_BCM_SUBTYPE_EVENT_DATA_PAD	2
++
++/* These fields are stored in network order */
++typedef BWL_PRE_PACKED_STRUCT struct bcmeth_hdr
++{
++	uint16	subtype;	/* Vendor specific..32769 */
++	uint16	length;
++	uint8	version;	/* Version is 0 */
++	uint8	oui[3];		/* Broadcom OUI */
++	/* user specific Data */
++	uint16	usr_subtype;
++} BWL_POST_PACKED_STRUCT bcmeth_hdr_t;
++
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++#endif	/*  _BCMETH_H_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmevent.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmevent.h
+new file mode 100644
+index 000000000..27f77a001
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmevent.h
+@@ -0,0 +1,948 @@
++/*
++ * Broadcom Event  protocol definitions
++ *
++ * Dependencies: bcmeth.h
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmevent.h 700076 2017-05-17 14:42:22Z $
++ *
++ */
++
++/*
++ * Broadcom Ethernet Events protocol defines
++ *
++ */
++
++#ifndef _BCMEVENT_H_
++#define _BCMEVENT_H_
++
++#include <typedefs.h>
++/* #include <ethernet.h> -- TODO: req., excluded to overwhelming coupling (break up ethernet.h) */
++#include <bcmeth.h>
++#if defined(DNGL_EVENT_SUPPORT)
++#include <dnglevent.h>
++#endif 
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++
++#define BCM_EVENT_MSG_VERSION		2	/* wl_event_msg_t struct version */
++#define BCM_MSG_IFNAME_MAX		16	/* max length of interface name */
++
++/* flags */
++#define WLC_EVENT_MSG_LINK		0x01	/* link is up */
++#define WLC_EVENT_MSG_FLUSHTXQ		0x02	/* flush tx queue on MIC error */
++#define WLC_EVENT_MSG_GROUP		0x04	/* group MIC error */
++#define WLC_EVENT_MSG_UNKBSS		0x08	/* unknown source bsscfg */
++#define WLC_EVENT_MSG_UNKIF		0x10	/* unknown source OS i/f */
++
++/* these fields are stored in network order */
++
++/* version 1 */
++typedef BWL_PRE_PACKED_STRUCT struct
++{
++	uint16	version;
++	uint16	flags;			/* see flags below */
++	uint32	event_type;		/* Message (see below) */
++	uint32	status;			/* Status code (see below) */
++	uint32	reason;			/* Reason code (if applicable) */
++	uint32	auth_type;		/* WLC_E_AUTH */
++	uint32	datalen;		/* data buf */
++	struct ether_addr	addr;	/* Station address (if applicable) */
++	char	ifname[BCM_MSG_IFNAME_MAX]; /* name of the packet incoming interface */
++} BWL_POST_PACKED_STRUCT wl_event_msg_v1_t;
++
++/* the current version */
++typedef BWL_PRE_PACKED_STRUCT struct
++{
++	uint16	version;
++	uint16	flags;			/* see flags below */
++	uint32	event_type;		/* Message (see below) */
++	uint32	status;			/* Status code (see below) */
++	uint32	reason;			/* Reason code (if applicable) */
++	uint32	auth_type;		/* WLC_E_AUTH */
++	uint32	datalen;		/* data buf */
++	struct ether_addr	addr;	/* Station address (if applicable) */
++	char	ifname[BCM_MSG_IFNAME_MAX]; /* name of the packet incoming interface */
++	uint8	ifidx;			/* destination OS i/f index */
++	uint8	bsscfgidx;		/* source bsscfg index */
++} BWL_POST_PACKED_STRUCT wl_event_msg_t;
++
++/* used by driver msgs */
++typedef BWL_PRE_PACKED_STRUCT struct bcm_event {
++	struct ether_header eth;
++	bcmeth_hdr_t		bcm_hdr;
++	wl_event_msg_t		event;
++	/* data portion follows */
++} BWL_POST_PACKED_STRUCT bcm_event_t;
++
++/*
++ * used by host event
++ * note: if additional event types are added, it should go with is_wlc_event_frame() as well.
++ */
++typedef union bcm_event_msg_u {
++	wl_event_msg_t		event;
++#if defined(DNGL_EVENT_SUPPORT)
++	bcm_dngl_event_msg_t	dngl_event;
++#endif 
++
++	/* add new event here */
++} bcm_event_msg_u_t;
++
++#define BCM_MSG_LEN	(sizeof(bcm_event_t) - sizeof(bcmeth_hdr_t) - sizeof(struct ether_header))
++
++/* Event messages */
++#define WLC_E_SET_SSID		0	/* indicates status of set SSID */
++#define WLC_E_JOIN		1	/* differentiates join IBSS from found (WLC_E_START) IBSS */
++#define WLC_E_START		2	/* STA founded an IBSS or AP started a BSS */
++#define WLC_E_AUTH		3	/* 802.11 AUTH request */
++#define WLC_E_AUTH_IND		4	/* 802.11 AUTH indication */
++#define WLC_E_DEAUTH		5	/* 802.11 DEAUTH request */
++#define WLC_E_DEAUTH_IND	6	/* 802.11 DEAUTH indication */
++#define WLC_E_ASSOC		7	/* 802.11 ASSOC request */
++#define WLC_E_ASSOC_IND		8	/* 802.11 ASSOC indication */
++#define WLC_E_REASSOC		9	/* 802.11 REASSOC request */
++#define WLC_E_REASSOC_IND	10	/* 802.11 REASSOC indication */
++#define WLC_E_DISASSOC		11	/* 802.11 DISASSOC request */
++#define WLC_E_DISASSOC_IND	12	/* 802.11 DISASSOC indication */
++#define WLC_E_QUIET_START	13	/* 802.11h Quiet period started */
++#define WLC_E_QUIET_END		14	/* 802.11h Quiet period ended */
++#define WLC_E_BEACON_RX		15	/* BEACONS received/lost indication */
++#define WLC_E_LINK		16	/* generic link indication */
++#define WLC_E_MIC_ERROR		17	/* TKIP MIC error occurred */
++#define WLC_E_NDIS_LINK		18	/* NDIS style link indication */
++#define WLC_E_ROAM		19	/* roam complete: indicate status & reason */
++#define WLC_E_TXFAIL		20	/* change in dot11FailedCount (txfail) */
++#define WLC_E_PMKID_CACHE	21	/* WPA2 pmkid cache indication */
++#define WLC_E_RETROGRADE_TSF	22	/* current AP's TSF value went backward */
++#define WLC_E_PRUNE		23	/* AP was pruned from join list for reason */
++#define WLC_E_AUTOAUTH		24	/* report AutoAuth table entry match for join attempt */
++#define WLC_E_EAPOL_MSG		25	/* Event encapsulating an EAPOL message */
++#define WLC_E_SCAN_COMPLETE	26	/* Scan results are ready or scan was aborted */
++#define WLC_E_ADDTS_IND		27	/* indicate to host addts fail/success */
++#define WLC_E_DELTS_IND		28	/* indicate to host delts fail/success */
++#define WLC_E_BCNSENT_IND	29	/* indicate to host of beacon transmit */
++#define WLC_E_BCNRX_MSG		30	/* Send the received beacon up to the host */
++#define WLC_E_BCNLOST_MSG	31	/* indicate to host loss of beacon */
++#define WLC_E_ROAM_PREP		32	/* before attempting to roam association */
++#define WLC_E_PFN_NET_FOUND	33	/* PFN network found event */
++#define WLC_E_PFN_NET_LOST	34	/* PFN network lost event */
++#define WLC_E_RESET_COMPLETE	35
++#define WLC_E_JOIN_START	36
++#define WLC_E_ROAM_START	37	/* roam attempt started: indicate reason */
++#define WLC_E_ASSOC_START	38
++#define WLC_E_IBSS_ASSOC	39
++#define WLC_E_RADIO		40
++#define WLC_E_PSM_WATCHDOG	41	/* PSM microcode watchdog fired */
++
++#define WLC_E_PROBREQ_MSG       44      /* probe request received */
++#define WLC_E_SCAN_CONFIRM_IND  45
++#define WLC_E_PSK_SUP		46	/* WPA Handshake fail */
++#define WLC_E_COUNTRY_CODE_CHANGED	47
++#define	WLC_E_EXCEEDED_MEDIUM_TIME	48	/* WMMAC excedded medium time */
++#define WLC_E_ICV_ERROR		49	/* WEP ICV error occurred */
++#define WLC_E_UNICAST_DECODE_ERROR	50	/* Unsupported unicast encrypted frame */
++#define WLC_E_MULTICAST_DECODE_ERROR	51	/* Unsupported multicast encrypted frame */
++#define WLC_E_TRACE		52
++#define WLC_E_IF		54	/* I/F change (for dongle host notification) */
++#define WLC_E_P2P_DISC_LISTEN_COMPLETE	55	/* listen state expires */
++#define WLC_E_RSSI		56	/* indicate RSSI change based on configured levels */
++#define WLC_E_PFN_BEST_BATCHING	57	/* PFN best network batching event */
++#define WLC_E_EXTLOG_MSG	58
++#define WLC_E_ACTION_FRAME      59	/* Action frame Rx */
++#define WLC_E_ACTION_FRAME_COMPLETE	60	/* Action frame Tx complete */
++#define WLC_E_PRE_ASSOC_IND	61	/* assoc request received */
++#define WLC_E_PRE_REASSOC_IND	62	/* re-assoc request received */
++#define WLC_E_CHANNEL_ADOPTED	63
++#define WLC_E_AP_STARTED	64	/* AP started */
++#define WLC_E_DFS_AP_STOP	65	/* AP stopped due to DFS */
++#define WLC_E_DFS_AP_RESUME	66	/* AP resumed due to DFS */
++#define WLC_E_WAI_STA_EVENT	67	/* WAI stations event */
++#define WLC_E_WAI_MSG 		68	/* event encapsulating an WAI message */
++#define WLC_E_ESCAN_RESULT 	69	/* escan result event */
++#define WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE 	70	/* action frame off channel complete */
++#define WLC_E_PROBRESP_MSG	71	/* probe response received */
++#define WLC_E_P2P_PROBREQ_MSG	72	/* P2P Probe request received */
++#define WLC_E_DCS_REQUEST	73
++#define WLC_E_FIFO_CREDIT_MAP	74	/* credits for D11 FIFOs. [AC0,AC1,AC2,AC3,BC_MC,ATIM] */
++#define WLC_E_ACTION_FRAME_RX	75	/* Received action frame event WITH
++					 * wl_event_rx_frame_data_t header
++					 */
++#define WLC_E_WAKE_EVENT	76	/* Wake Event timer fired, used for wake WLAN test mode */
++#define WLC_E_RM_COMPLETE	77	/* Radio measurement complete */
++#define WLC_E_HTSFSYNC		78	/* Synchronize TSF with the host */
++#define WLC_E_OVERLAY_REQ	79	/* request an overlay IOCTL/iovar from the host */
++#define WLC_E_CSA_COMPLETE_IND		80	/* 802.11 CHANNEL SWITCH ACTION completed */
++#define WLC_E_EXCESS_PM_WAKE_EVENT	81	/* excess PM Wake Event to inform host  */
++#define WLC_E_PFN_SCAN_NONE		82	/* no PFN networks around */
++/* PFN BSSID network found event, conflict/share with  WLC_E_PFN_SCAN_NONE */
++#define WLC_E_PFN_BSSID_NET_FOUND	82
++#define WLC_E_PFN_SCAN_ALLGONE		83	/* last found PFN network gets lost */
++/* PFN BSSID network lost event, conflict/share with WLC_E_PFN_SCAN_ALLGONE */
++#define WLC_E_PFN_BSSID_NET_LOST	83
++#define WLC_E_GTK_PLUMBED		84
++#define WLC_E_ASSOC_IND_NDIS		85	/* 802.11 ASSOC indication for NDIS only */
++#define WLC_E_REASSOC_IND_NDIS		86	/* 802.11 REASSOC indication for NDIS only */
++#define WLC_E_ASSOC_REQ_IE		87
++#define WLC_E_ASSOC_RESP_IE		88
++#define WLC_E_ASSOC_RECREATED		89	/* association recreated on resume */
++#define WLC_E_ACTION_FRAME_RX_NDIS	90	/* rx action frame event for NDIS only */
++#define WLC_E_AUTH_REQ			91	/* authentication request received */
++#define WLC_E_TDLS_PEER_EVENT		92	/* discovered peer, connected/disconnected peer */
++#define WLC_E_SPEEDY_RECREATE_FAIL	93	/* fast assoc recreation failed */
++#define WLC_E_NATIVE			94	/* port-specific event and payload (e.g. NDIS) */
++#define WLC_E_PKTDELAY_IND		95	/* event for tx pkt delay suddently jump */
++#define WLC_E_PSTA_PRIMARY_INTF_IND	99	/* psta primary interface indication */
++#define WLC_E_NAN			100     /* NAN event - Reserved for future */
++#define WLC_E_BEACON_FRAME_RX		101
++#define WLC_E_SERVICE_FOUND		102	/* desired service found */
++#define WLC_E_GAS_FRAGMENT_RX		103	/* GAS fragment received */
++#define WLC_E_GAS_COMPLETE		104	/* GAS sessions all complete */
++#define WLC_E_P2PO_ADD_DEVICE		105	/* New device found by p2p offload */
++#define WLC_E_P2PO_DEL_DEVICE		106	/* device has been removed by p2p offload */
++#define WLC_E_WNM_STA_SLEEP		107	/* WNM event to notify STA enter sleep mode */
++#define WLC_E_TXFAIL_THRESH		108	/* Indication of MAC tx failures (exhaustion of
++						 * 802.11 retries) exceeding threshold(s)
++						 */
++#define WLC_E_PROXD			109	/* Proximity Detection event */
++#define WLC_E_IBSS_COALESCE		110	/* IBSS Coalescing */
++#define WLC_E_AIBSS_TXFAIL		110	/* TXFAIL event for AIBSS, re using event 110 */
++#define WLC_E_BSS_LOAD			114	/* Inform host of beacon bss load */
++#define WLC_E_MIMO_PWR_SAVE		115	/* Inform host MIMO PWR SAVE learning events */
++#define WLC_E_LEAKY_AP_STATS	116 /* Inform host leaky Ap stats events */
++#define WLC_E_ALLOW_CREDIT_BORROW 117	/* Allow or disallow wlfc credit borrowing in DHD */
++#define WLC_E_MSCH			120	/* Multiple channel scheduler event */
++#define WLC_E_CSA_START_IND		121
++#define WLC_E_CSA_DONE_IND		122
++#define WLC_E_CSA_FAILURE_IND		123
++#define WLC_E_CCA_CHAN_QUAL		124	/* CCA based channel quality report */
++#define WLC_E_BSSID		125	/* to report change in BSSID while roaming */
++#define WLC_E_TX_STAT_ERROR		126	/* tx error indication */
++#define WLC_E_BCMC_CREDIT_SUPPORT	127	/* credit check for BCMC supported */
++#define WLC_E_PEER_TIMEOUT	128 /* silently drop a STA because of inactivity */
++#define WLC_E_BT_WIFI_HANDOVER_REQ	130	/* Handover Request Initiated */
++#define WLC_E_SPW_TXINHIBIT		131     /* Southpaw TxInhibit notification */
++#define WLC_E_FBT_AUTH_REQ_IND		132	/* FBT Authentication Request Indication */
++#define WLC_E_RSSI_LQM			133	/* Enhancement addition for WLC_E_RSSI */
++#define WLC_E_PFN_GSCAN_FULL_RESULT		134 /* Full probe/beacon (IEs etc) results */
++#define WLC_E_PFN_SWC		135 /* Significant change in rssi of bssids being tracked */
++#define WLC_E_AUTHORIZED	136	/* a STA been authroized for traffic */
++#define WLC_E_PROBREQ_MSG_RX	137 /* probe req with wl_event_rx_frame_data_t header */
++#define WLC_E_PFN_SCAN_COMPLETE	138	/* PFN completed scan of network list */
++#define WLC_E_RMC_EVENT		139	/* RMC Event */
++#define WLC_E_DPSTA_INTF_IND	140	/* DPSTA interface indication */
++#define WLC_E_RRM		141	/* RRM Event */
++#define WLC_E_PFN_SSID_EXT	142	/* SSID EXT event */
++#define WLC_E_ROAM_EXP_EVENT	143	/* Expanded roam event */
++#define WLC_E_ULP			146	/* ULP entered indication */
++#define WLC_E_MACDBG			147	/* Ucode debugging event */
++#define WLC_E_RESERVED			148	/* reserved */
++#define WLC_E_PRE_ASSOC_RSEP_IND	149	/* assoc resp received */
++#define WLC_E_PSK_AUTH			150	/* PSK AUTH WPA2-PSK 4 WAY Handshake failure */
++#define WLC_E_TKO			151     /* TCP keepalive offload */
++#define WLC_E_SDB_TRANSITION            152     /* SDB mode-switch event */
++#define WLC_E_NATOE_NFCT		153     /* natoe event */
++#define WLC_E_TEMP_THROTTLE		154	/* Temperature throttling control event */
++#define WLC_E_LINK_QUALITY		155     /* Link quality measurement complete */
++#define WLC_E_BSSTRANS_RESP		156	/* BSS Transition Response received */
++#define WLC_E_TWT_SETUP			157	/* TWT Setup Complete event */
++#define WLC_E_HE_TWT_SETUP		157	/* TODO:Remove after merging TWT changes to trunk */
++#define WLC_E_NAN_CRITICAL		158	/* NAN Critical Event */
++#define WLC_E_NAN_NON_CRITICAL		159	/* NAN Non-Critical Event */
++#define WLC_E_RADAR_DETECTED		160	/* Radar Detected event */
++#define WLC_E_RANGING_EVENT		161	/* Ranging event */
++#define WLC_E_INVALID_IE		162	/* Received invalid IE */
++#define WLC_E_MODE_SWITCH		163	/* Mode switch event */
++#define WLC_E_PKT_FILTER		164	/* Packet filter event */
++#define WLC_E_DMA_TXFLUSH_COMPLETE		165	/* TxFlush done before changing
++											* tx/rxchain
++											*/
++#define WLC_E_FBT			166	/* FBT event */
++#define WLC_E_PFN_SCAN_BACKOFF	167	/* PFN SCAN Backoff event */
++#define WLC_E_PFN_BSSID_SCAN_BACKOFF	168	/* PFN BSSID SCAN BAckoff event */
++#define WLC_E_AGGR_EVENT		169	/* Aggregated event */
++#define WLC_E_TVPM_MITIGATION		171	/* Change in mitigation applied by TVPM */
++#define WLC_E_LAST			172	/* highest val + 1 for range checking */
++#if (WLC_E_LAST > 172)
++#error "WLC_E_LAST: Invalid value for last event; must be <= 172."
++#endif /* WLC_E_LAST */
++
++/* define an API for getting the string name of an event */
++extern const char *bcmevent_get_name(uint event_type);
++extern void wl_event_to_host_order(wl_event_msg_t * evt);
++extern void wl_event_to_network_order(wl_event_msg_t * evt);
++
++/* validate if the event is proper and if valid copy event header to event */
++extern int is_wlc_event_frame(void *pktdata, uint pktlen, uint16 exp_usr_subtype,
++	bcm_event_msg_u_t *out_event);
++
++/* conversion between host and network order for events */
++void wl_event_to_host_order(wl_event_msg_t * evt);
++void wl_event_to_network_order(wl_event_msg_t * evt);
++
++
++/* Event status codes */
++#define WLC_E_STATUS_SUCCESS		0	/* operation was successful */
++#define WLC_E_STATUS_FAIL		1	/* operation failed */
++#define WLC_E_STATUS_TIMEOUT		2	/* operation timed out */
++#define WLC_E_STATUS_NO_NETWORKS	3	/* failed due to no matching network found */
++#define WLC_E_STATUS_ABORT		4	/* operation was aborted */
++#define WLC_E_STATUS_NO_ACK		5	/* protocol failure: packet not ack'd */
++#define WLC_E_STATUS_UNSOLICITED	6	/* AUTH or ASSOC packet was unsolicited */
++#define WLC_E_STATUS_ATTEMPT		7	/* attempt to assoc to an auto auth configuration */
++#define WLC_E_STATUS_PARTIAL		8	/* scan results are incomplete */
++#define WLC_E_STATUS_NEWSCAN		9	/* scan aborted by another scan */
++#define WLC_E_STATUS_NEWASSOC		10	/* scan aborted due to assoc in progress */
++#define WLC_E_STATUS_11HQUIET		11	/* 802.11h quiet period started */
++#define WLC_E_STATUS_SUPPRESS		12	/* user disabled scanning (WLC_SET_SCANSUPPRESS) */
++#define WLC_E_STATUS_NOCHANS		13	/* no allowable channels to scan */
++#define WLC_E_STATUS_CS_ABORT		15	/* abort channel select */
++#define WLC_E_STATUS_ERROR		16	/* request failed due to error */
++#define WLC_E_STATUS_INVALID 0xff  /* Invalid status code to init variables. */
++
++/* 4-way handshake event type */
++#define WLC_E_PSK_AUTH_SUB_EAPOL_START		1	/* EAPOL start */
++#define WLC_E_PSK_AUTH_SUB_EAPOL_DONE		2	/* EAPOL end */
++/* GTK event type */
++#define	WLC_E_PSK_AUTH_SUB_GTK_DONE		3	/* GTK end */
++
++/* 4-way handshake event status code */
++#define WLC_E_STATUS_PSK_AUTH_WPA_TIMOUT	1	/* operation timed out */
++#define WLC_E_STATUS_PSK_AUTH_MIC_WPA_ERR		2	/* MIC error */
++#define WLC_E_STATUS_PSK_AUTH_IE_MISMATCH_ERR		3	/* IE Missmatch error */
++#define WLC_E_STATUS_PSK_AUTH_REPLAY_COUNT_ERR		4
++#define WLC_E_STATUS_PSK_AUTH_PEER_BLACKISTED	5	/* Blaclisted peer */
++#define WLC_E_STATUS_PSK_AUTH_GTK_REKEY_FAIL	6	/* GTK event status code */
++
++/* SDB transition status code */
++#define WLC_E_STATUS_SDB_START			1
++#define WLC_E_STATUS_SDB_COMPLETE		2
++/* Slice-swap status code */
++#define WLC_E_STATUS_SLICE_SWAP_START		3
++#define WLC_E_STATUS_SLICE_SWAP_COMPLETE	4
++
++
++/* SDB transition reason code */
++#define WLC_E_REASON_HOST_DIRECT	0
++#define WLC_E_REASON_INFRA_ASSOC	1
++#define WLC_E_REASON_INFRA_ROAM		2
++#define WLC_E_REASON_INFRA_DISASSOC	3
++#define WLC_E_REASON_NO_MODE_CHANGE_NEEDED	4
++#define WLC_E_REASON_AWDL_ENABLE	5
++#define WLC_E_REASON_AWDL_DISABLE	6
++
++/* WLC_E_SDB_TRANSITION event data */
++#define WL_MAX_BSSCFG     4
++#define WL_EVENT_SDB_TRANSITION_VER     1
++typedef struct wl_event_sdb_data {
++	uint8 wlunit;           /* Core index */
++	uint8 is_iftype;        /* Interface Type(Station, SoftAP, P2P_GO, P2P_GC */
++	uint16 chanspec;        /* Interface Channel/Chanspec */
++	char ssidbuf[(4 * 32) + 1];	/* SSID_FMT_BUF_LEN: ((4 * DOT11_MAX_SSID_LEN) + 1) */
++} wl_event_sdb_data_t;
++
++typedef struct wl_event_sdb_trans {
++	uint8 version;          /* Event Data Version */
++	uint8 rsdb_mode;
++	uint8 enable_bsscfg;
++	uint8 reserved;
++	struct wl_event_sdb_data values[WL_MAX_BSSCFG];
++} wl_event_sdb_trans_t;
++
++/* roam reason codes */
++#define WLC_E_REASON_INITIAL_ASSOC	0	/* initial assoc */
++#define WLC_E_REASON_LOW_RSSI		1	/* roamed due to low RSSI */
++#define WLC_E_REASON_DEAUTH		2	/* roamed due to DEAUTH indication */
++#define WLC_E_REASON_DISASSOC		3	/* roamed due to DISASSOC indication */
++#define WLC_E_REASON_BCNS_LOST		4	/* roamed due to lost beacons */
++
++#define WLC_E_REASON_FAST_ROAM_FAILED	5	/* roamed due to fast roam failure */
++#define WLC_E_REASON_DIRECTED_ROAM	6	/* roamed due to request by AP */
++#define WLC_E_REASON_TSPEC_REJECTED	7	/* roamed due to TSPEC rejection */
++#define WLC_E_REASON_BETTER_AP		8	/* roamed due to finding better AP */
++#define WLC_E_REASON_MINTXRATE		9	/* roamed because at mintxrate for too long */
++#define WLC_E_REASON_TXFAIL		10	/* We can hear AP, but AP can't hear us */
++/* retained for precommit auto-merging errors; remove once all branches are synced */
++#define WLC_E_REASON_REQUESTED_ROAM	11
++#define WLC_E_REASON_BSSTRANS_REQ	11	/* roamed due to BSS Transition request by AP */
++#define WLC_E_REASON_LOW_RSSI_CU		12 /* roamed due to low RSSI and Channel Usage */
++#define WLC_E_REASON_RADAR_DETECTED	13	/* roamed due to radar detection by STA */
++
++/* prune reason codes */
++#define WLC_E_PRUNE_ENCR_MISMATCH	1	/* encryption mismatch */
++#define WLC_E_PRUNE_BCAST_BSSID		2	/* AP uses a broadcast BSSID */
++#define WLC_E_PRUNE_MAC_DENY		3	/* STA's MAC addr is in AP's MAC deny list */
++#define WLC_E_PRUNE_MAC_NA		4	/* STA's MAC addr is not in AP's MAC allow list */
++#define WLC_E_PRUNE_REG_PASSV		5	/* AP not allowed due to regulatory restriction */
++#define WLC_E_PRUNE_SPCT_MGMT		6	/* AP does not support STA locale spectrum mgmt */
++#define WLC_E_PRUNE_RADAR		7	/* AP is on a radar channel of STA locale */
++#define WLC_E_RSN_MISMATCH		8	/* STA does not support AP's RSN */
++#define WLC_E_PRUNE_NO_COMMON_RATES	9	/* No rates in common with AP */
++#define WLC_E_PRUNE_BASIC_RATES		10	/* STA does not support all basic rates of BSS */
++#define WLC_E_PRUNE_CIPHER_NA		12	/* BSS's cipher not supported */
++#define WLC_E_PRUNE_KNOWN_STA		13	/* AP is already known to us as a STA */
++#define WLC_E_PRUNE_WDS_PEER		15	/* AP is already known to us as a WDS peer */
++#define WLC_E_PRUNE_QBSS_LOAD		16	/* QBSS LOAD - AAC is too low */
++#define WLC_E_PRUNE_HOME_AP		17	/* prune home AP */
++#define WLC_E_PRUNE_AUTH_RESP_MAC	20	/* suppress auth resp by MAC filter */
++
++/* WPA failure reason codes carried in the WLC_E_PSK_SUP event */
++#define WLC_E_SUP_OTHER			0	/* Other reason */
++#define WLC_E_SUP_DECRYPT_KEY_DATA	1	/* Decryption of key data failed */
++#define WLC_E_SUP_BAD_UCAST_WEP128	2	/* Illegal use of ucast WEP128 */
++#define WLC_E_SUP_BAD_UCAST_WEP40	3	/* Illegal use of ucast WEP40 */
++#define WLC_E_SUP_UNSUP_KEY_LEN		4	/* Unsupported key length */
++#define WLC_E_SUP_PW_KEY_CIPHER		5	/* Unicast cipher mismatch in pairwise key */
++#define WLC_E_SUP_MSG3_TOO_MANY_IE	6	/* WPA IE contains > 1 RSN IE in key msg 3 */
++#define WLC_E_SUP_MSG3_IE_MISMATCH	7	/* WPA IE mismatch in key message 3 */
++#define WLC_E_SUP_NO_INSTALL_FLAG	8	/* INSTALL flag unset in 4-way msg */
++#define WLC_E_SUP_MSG3_NO_GTK		9	/* encapsulated GTK missing from msg 3 */
++#define WLC_E_SUP_GRP_KEY_CIPHER	10	/* Multicast cipher mismatch in group key */
++#define WLC_E_SUP_GRP_MSG1_NO_GTK	11	/* encapsulated GTK missing from group msg 1 */
++#define WLC_E_SUP_GTK_DECRYPT_FAIL	12	/* GTK decrypt failure */
++#define WLC_E_SUP_SEND_FAIL		13	/* message send failure */
++#define WLC_E_SUP_DEAUTH		14	/* received FC_DEAUTH */
++#define WLC_E_SUP_WPA_PSK_TMO		15	/* WPA PSK 4-way handshake timeout */
++#define WLC_E_SUP_WPA_PSK_M1_TMO	16	/* WPA PSK 4-way handshake M1 timeout */
++#define WLC_E_SUP_WPA_PSK_M3_TMO	17	/* WPA PSK 4-way handshake M3 timeout */
++
++
++/* Ucode reason codes carried in the WLC_E_MACDBG event */
++#define WLC_E_MACDBG_LIST_PSM		0	/* Dump list update for PSM registers */
++#define WLC_E_MACDBG_LIST_PSMX		1	/* Dump list update for PSMx registers */
++#define WLC_E_MACDBG_REGALL		2	/* Dump all registers */
++
++/* Event data for events that include frames received over the air */
++/* WLC_E_PROBRESP_MSG
++ * WLC_E_P2P_PROBREQ_MSG
++ * WLC_E_ACTION_FRAME_RX
++ */
++typedef BWL_PRE_PACKED_STRUCT struct wl_event_rx_frame_data {
++	uint16	version;
++	uint16	channel;	/* Matches chanspec_t format from bcmwifi_channels.h */
++	int32	rssi;
++	uint32	mactime;
++	uint32	rate;
++} BWL_POST_PACKED_STRUCT wl_event_rx_frame_data_t;
++
++#define BCM_RX_FRAME_DATA_VERSION 1
++
++/* WLC_E_IF event data */
++typedef struct wl_event_data_if {
++	uint8 ifidx;		/* RTE virtual device index (for dongle) */
++	uint8 opcode;		/* see I/F opcode */
++	uint8 reserved;		/* bit mask (WLC_E_IF_FLAGS_XXX ) */
++	uint8 bssidx;		/* bsscfg index */
++	uint8 role;		/* see I/F role */
++} wl_event_data_if_t;
++
++/* WLC_E_NATOE event data */
++typedef struct wl_event_data_natoe {
++	uint32 natoe_active;
++	uint32 sta_ip;
++	uint16 start_port;
++	uint16 end_port;
++} wl_event_data_natoe_t;
++
++/* opcode in WLC_E_IF event */
++#define WLC_E_IF_ADD		1	/* bsscfg add */
++#define WLC_E_IF_DEL		2	/* bsscfg delete */
++#define WLC_E_IF_CHANGE		3	/* bsscfg role change */
++
++/* I/F role code in WLC_E_IF event */
++#define WLC_E_IF_ROLE_STA		0	/* Infra STA */
++#define WLC_E_IF_ROLE_AP		1	/* Access Point */
++#define WLC_E_IF_ROLE_WDS		2	/* WDS link */
++#define WLC_E_IF_ROLE_P2P_GO		3	/* P2P Group Owner */
++#define WLC_E_IF_ROLE_P2P_CLIENT	4	/* P2P Client */
++#define WLC_E_IF_ROLE_IBSS              8       /* IBSS */
++#define WLC_E_IF_ROLE_NAN              9       /* NAN */
++
++/* WLC_E_RSSI event data */
++typedef struct wl_event_data_rssi {
++	int32 rssi;
++	int32 snr;
++	int32 noise;
++} wl_event_data_rssi_t;
++
++/* WLC_E_IF flag */
++#define WLC_E_IF_FLAGS_BSSCFG_NOIF	0x1	/* no host I/F creation needed */
++
++/* Reason codes for LINK */
++#define WLC_E_LINK_BCN_LOSS     1   /* Link down because of beacon loss */
++#define WLC_E_LINK_DISASSOC     2   /* Link down because of disassoc */
++#define WLC_E_LINK_ASSOC_REC    3   /* Link down because assoc recreate failed */
++#define WLC_E_LINK_BSSCFG_DIS   4   /* Link down due to bsscfg down */
++
++
++/* WLC_E_NDIS_LINK event data */
++typedef BWL_PRE_PACKED_STRUCT struct ndis_link_parms {
++	struct ether_addr peer_mac; /* 6 bytes */
++	uint16 chanspec;            /* 2 bytes */
++	uint32 link_speed;          /* current datarate in units of 500 Kbit/s */
++	uint32 max_link_speed;      /* max possible datarate for link in units of 500 Kbit/s  */
++	int32  rssi;                /* average rssi */
++} BWL_POST_PACKED_STRUCT ndis_link_parms_t;
++
++/* reason codes for WLC_E_OVERLAY_REQ event */
++#define WLC_E_OVL_DOWNLOAD		0	/* overlay download request */
++#define WLC_E_OVL_UPDATE_IND	1	/* device indication of host overlay update */
++
++/* reason codes for WLC_E_TDLS_PEER_EVENT event */
++#define WLC_E_TDLS_PEER_DISCOVERED		0	/* peer is ready to establish TDLS */
++#define WLC_E_TDLS_PEER_CONNECTED		1
++#define WLC_E_TDLS_PEER_DISCONNECTED	2
++
++/* reason codes for WLC_E_RMC_EVENT event */
++#define WLC_E_REASON_RMC_NONE		0
++#define WLC_E_REASON_RMC_AR_LOST		1
++#define WLC_E_REASON_RMC_AR_NO_ACK		2
++
++#ifdef WLTDLS
++/* TDLS Action Category code */
++#define TDLS_AF_CATEGORY		12
++/* Wi-Fi Display (WFD) Vendor Specific Category */
++/* used for WFD Tunneled Probe Request and Response */
++#define TDLS_VENDOR_SPECIFIC		127
++/* TDLS Action Field Values */
++#define TDLS_ACTION_SETUP_REQ		0
++#define TDLS_ACTION_SETUP_RESP		1
++#define TDLS_ACTION_SETUP_CONFIRM	2
++#define TDLS_ACTION_TEARDOWN		3
++#define WLAN_TDLS_SET_PROBE_WFD_IE	11
++#define WLAN_TDLS_SET_SETUP_WFD_IE	12
++#define WLAN_TDLS_SET_WFD_ENABLED	13
++#define WLAN_TDLS_SET_WFD_DISABLED	14
++#endif
++
++/* WLC_E_RANGING_EVENT subtypes */
++#define WLC_E_RANGING_RESULTS	0
++
++
++/* GAS event data */
++typedef BWL_PRE_PACKED_STRUCT struct wl_event_gas {
++	uint16	channel;		/* channel of GAS protocol */
++	uint8	dialog_token;	/* GAS dialog token */
++	uint8	fragment_id;	/* fragment id */
++	uint16	status_code;	/* status code on GAS completion */
++	uint16 	data_len;		/* length of data to follow */
++	uint8	data[1];		/* variable length specified by data_len */
++} BWL_POST_PACKED_STRUCT wl_event_gas_t;
++
++/* service discovery TLV */
++typedef BWL_PRE_PACKED_STRUCT struct wl_sd_tlv {
++	uint16	length;			/* length of response_data */
++	uint8	protocol;		/* service protocol type */
++	uint8	transaction_id;		/* service transaction id */
++	uint8	status_code;		/* status code */
++	uint8	data[1];		/* response data */
++} BWL_POST_PACKED_STRUCT wl_sd_tlv_t;
++
++/* service discovery event data */
++typedef BWL_PRE_PACKED_STRUCT struct wl_event_sd {
++	uint16	channel;		/* channel */
++	uint8	count;			/* number of tlvs */
++	wl_sd_tlv_t	tlv[1];		/* service discovery TLV */
++} BWL_POST_PACKED_STRUCT wl_event_sd_t;
++
++/* WLC_E_PKT_FILTER event sub-classification codes */
++#define WLC_E_PKT_FILTER_TIMEOUT	1 /* Matching packet not received in last timeout seconds */
++
++/* Note: proxd has a new API (ver 3.0) deprecates the following */
++
++/* Reason codes for WLC_E_PROXD */
++#define WLC_E_PROXD_FOUND		1	/* Found a proximity device */
++#define WLC_E_PROXD_GONE		2	/* Lost a proximity device */
++#define WLC_E_PROXD_START		3	/* used by: target  */
++#define WLC_E_PROXD_STOP		4	/* used by: target   */
++#define WLC_E_PROXD_COMPLETED		5	/* used by: initiator completed */
++#define WLC_E_PROXD_ERROR		6	/* used by both initiator and target */
++#define WLC_E_PROXD_COLLECT_START	7	/* used by: target & initiator */
++#define WLC_E_PROXD_COLLECT_STOP	8	/* used by: target */
++#define WLC_E_PROXD_COLLECT_COMPLETED	9	/* used by: initiator completed */
++#define WLC_E_PROXD_COLLECT_ERROR	10	/* used by both initiator and target */
++#define WLC_E_PROXD_NAN_EVENT		11	/* used by both initiator and target */
++#define WLC_E_PROXD_TS_RESULTS          12      /* used by: initiator completed */
++
++/*  proxd_event data */
++typedef struct ftm_sample {
++	uint32 value;	/* RTT in ns */
++	int8 rssi;	/* RSSI */
++} ftm_sample_t;
++
++typedef struct ts_sample {
++	uint32 t1;
++	uint32 t2;
++	uint32 t3;
++	uint32 t4;
++} ts_sample_t;
++
++typedef BWL_PRE_PACKED_STRUCT struct proxd_event_data {
++	uint16 ver;			/* version */
++	uint16 mode;			/* mode: target/initiator */
++	uint16 method;			/* method: rssi/TOF/AOA */
++	uint8  err_code;		/* error classification */
++	uint8  TOF_type;		/* one way or two way TOF */
++	uint8  OFDM_frame_type;		/* legacy or VHT */
++	uint8  bandwidth;		/* Bandwidth is 20, 40,80, MHZ */
++	struct ether_addr peer_mac;	/* (e.g for tgt:initiator's */
++	uint32 distance;		/* dst to tgt, units meter */
++	uint32 meanrtt;			/* mean delta */
++	uint32 modertt;			/* Mode delta */
++	uint32 medianrtt;		/* median RTT */
++	uint32 sdrtt;			/* Standard deviation of RTT */
++	int32  gdcalcresult;		/* Software or Hardware Kind of redundant, but if */
++					/* frame type is VHT, then we should do it by hardware */
++	int16  avg_rssi;		/* avg rssi accroos the ftm frames */
++	int16  validfrmcnt;		/* Firmware's valid frame counts */
++	int32  peer_router_info;	/* Peer router information if available in TLV, */
++					/* We will add this field later  */
++	int32 var1;			/* average of group delay */
++	int32 var2;			/* average of threshold crossing */
++	int32 var3;			/* difference between group delay and threshold crossing */
++					/* raw Fine Time Measurements (ftm) data */
++	uint16 ftm_unit;		/* ftm cnt resolution in picoseconds , 6250ps - default */
++	uint16 ftm_cnt;			/*  num of rtd measurments/length in the ftm buffer  */
++	ftm_sample_t ftm_buff[1];	/* 1 ... ftm_cnt  */
++} BWL_POST_PACKED_STRUCT wl_proxd_event_data_t;
++
++typedef BWL_PRE_PACKED_STRUCT struct proxd_event_ts_results {
++	uint16 ver;                     /* version */
++	uint16 mode;                    /* mode: target/initiator */
++	uint16 method;                  /* method: rssi/TOF/AOA */
++	uint8  err_code;                /* error classification */
++	uint8  TOF_type;                /* one way or two way TOF */
++	uint16  ts_cnt;                 /* number of timestamp measurements */
++	ts_sample_t ts_buff[1];         /* Timestamps */
++} BWL_POST_PACKED_STRUCT wl_proxd_event_ts_results_t;
++
++
++/* Video Traffic Interference Monitor Event */
++#define INTFER_EVENT_VERSION		1
++#define INTFER_STREAM_TYPE_NONTCP	1
++#define INTFER_STREAM_TYPE_TCP		2
++#define WLINTFER_STATS_NSMPLS		4
++typedef struct wl_intfer_event {
++	uint16 version;			/* version */
++	uint16 status;			/* status */
++	uint8 txfail_histo[WLINTFER_STATS_NSMPLS]; /* txfail histo */
++} wl_intfer_event_t;
++
++#define RRM_EVENT_VERSION		0
++typedef struct wl_rrm_event {
++	int16 version;
++	int16 len;
++	int16 cat;		/* Category */
++	int16 subevent;
++	char payload[1]; /* Measurement payload */
++} wl_rrm_event_t;
++
++
++/* WLC_E_PSTA_PRIMARY_INTF_IND event data */
++typedef struct wl_psta_primary_intf_event {
++	struct ether_addr prim_ea;	/* primary intf ether addr */
++} wl_psta_primary_intf_event_t;
++
++/* WLC_E_DPSTA_INTF_IND event data */
++typedef enum {
++	WL_INTF_PSTA = 1,
++	WL_INTF_DWDS = 2
++} wl_dpsta_intf_type;
++
++typedef struct wl_dpsta_intf_event {
++	wl_dpsta_intf_type intf_type;    /* dwds/psta intf register */
++} wl_dpsta_intf_event_t;
++
++/*  **********  NAN protocol events/subevents  ********** */
++#define NAN_EVENT_BUFFER_SIZE 512 /* max size */
++/* NAN Events sent by firmware */
++
++/*
++ * If you make changes to this enum, dont forget to update the mask (if need be).
++ */
++typedef enum wl_nan_events {
++	WL_NAN_EVENT_START			= 1,	/* NAN cluster started */
++	WL_NAN_EVENT_JOIN			= 2,	/* To be deprecated */
++	WL_NAN_EVENT_ROLE			= 3,	/* Role changed */
++	WL_NAN_EVENT_SCAN_COMPLETE		= 4,	/* To be deprecated */
++	WL_NAN_EVENT_DISCOVERY_RESULT		= 5,	/* Subscribe Received */
++	WL_NAN_EVENT_REPLIED			= 6,	/* Publish Sent */
++	WL_NAN_EVENT_TERMINATED			= 7,	/* sub / pub is terminated */
++	WL_NAN_EVENT_RECEIVE			= 8,	/* Follow up Received */
++	WL_NAN_EVENT_STATUS_CHG			= 9,	/* change in nan_mac status */
++	WL_NAN_EVENT_MERGE			= 10,	/* Merged to a NAN cluster */
++	WL_NAN_EVENT_STOP			= 11,	/* To be deprecated */
++	WL_NAN_EVENT_P2P			= 12,	/* Unused */
++	WL_NAN_EVENT_WINDOW_BEGIN_P2P		= 13,	/* Unused */
++	WL_NAN_EVENT_WINDOW_BEGIN_MESH		= 14,	/* Unused */
++	WL_NAN_EVENT_WINDOW_BEGIN_IBSS		= 15,	/* Unused */
++	WL_NAN_EVENT_WINDOW_BEGIN_RANGING	= 16,	/* Unused */
++	WL_NAN_EVENT_POST_DISC			= 17,	/* Event for post discovery data */
++	WL_NAN_EVENT_DATA_IF_ADD		= 18,	/* Unused */
++	WL_NAN_EVENT_DATA_PEER_ADD		= 19,	/* Event for peer add */
++	/* nan 2.0 */
++	/* Will be removed after source code is committed. */
++	WL_NAN_EVENT_DATA_IND			= 20,
++	WL_NAN_EVENT_PEER_DATAPATH_IND		= 20,	/* Incoming DP req */
++	/* Will be removed after source code is committed. */
++	WL_NAN_EVENT_DATA_CONF			= 21,
++	WL_NAN_EVENT_DATAPATH_ESTB		= 21,	/* DP Established */
++	WL_NAN_EVENT_SDF_RX			= 22,	/* SDF payload */
++	WL_NAN_EVENT_DATAPATH_END		= 23,	/* DP Terminate recvd */
++	/* Below event needs to be removed after source code is committed. */
++	WL_NAN_EVENT_DATA_END 			= 23,
++	WL_NAN_EVENT_BCN_RX			= 24,	/* received beacon payload */
++	WL_NAN_EVENT_PEER_DATAPATH_RESP		= 25,	/* Peer's DP response */
++	WL_NAN_EVENT_PEER_DATAPATH_CONF		= 26,	/* Peer's DP confirm */
++	WL_NAN_EVENT_RNG_REQ_IND		= 27,	/* Range Request */
++	WL_NAN_EVENT_RNG_RPT_IND		= 28,	/* Range Report */
++	WL_NAN_EVENT_RNG_TERM_IND		= 29,	/* Range Termination */
++	WL_NAN_EVENT_PEER_DATAPATH_SEC_INST	= 30,   /* Peer's DP sec install */
++	WL_NAN_EVENT_TXS			= 31,   /* for tx status of follow-up and SDFs */
++	WL_NAN_EVENT_INVALID				/* delimiter for max value */
++} nan_app_events_e;
++
++#define NAN_EV_MASK(ev) \
++		(1 << (ev - 1))
++#define IS_NAN_EVT_ON(var, evt) ((var & (1 << (evt-1))) != 0)
++/*  ******************* end of NAN section *************** */
++
++/* WLC_E_ULP event data */
++#define WL_ULP_EVENT_VERSION		1
++#define WL_ULP_DISABLE_CONSOLE		1	/* Disable console message on ULP entry */
++#define WL_ULP_UCODE_DOWNLOAD		2       /* Download ULP ucode file */
++
++typedef struct wl_ulp_event {
++	uint16 version;
++	uint16 ulp_dongle_action;
++} wl_ulp_event_t;
++
++/* TCP keepalive event data */
++typedef BWL_PRE_PACKED_STRUCT struct wl_event_tko {
++	uint8 index;		/* TCP connection index, 0 to max-1 */
++	uint8 pad[3];		/* 4-byte struct alignment */
++} BWL_POST_PACKED_STRUCT wl_event_tko_t;
++
++typedef struct {
++	uint8 radar_type;       /* one of RADAR_TYPE_XXX */
++	uint16 min_pw;          /* minimum pulse-width (usec * 20) */
++	uint16 max_pw;          /* maximum pulse-width (usec * 20) */
++	uint16 min_pri;         /* minimum pulse repetition interval (usec) */
++	uint16 max_pri;         /* maximum pulse repetition interval (usec) */
++	uint16 subband;         /* subband/frequency */
++} radar_detected_event_info_t;
++typedef struct wl_event_radar_detect_data {
++
++	uint32 version;
++	uint16 current_chanspec; /* chanspec on which the radar is recieved */
++	uint16 target_chanspec; /*  Target chanspec after detection of radar on current_chanspec */
++	radar_detected_event_info_t radar_info[2];
++} wl_event_radar_detect_data_t;
++
++
++#define WL_EVENT_MODESW_VER_1			1
++#define WL_EVENT_MODESW_VER_CURRENT		WL_EVENT_MODESW_VER_1
++
++#define WL_E_MODESW_FLAG_MASK_DEVICE		0x01u /* mask of device: belongs to local or peer */
++#define WL_E_MODESW_FLAG_MASK_FROM		0x02u /* mask of origin: firmware or user */
++#define WL_E_MODESW_FLAG_MASK_STATE		0x0Cu /* mask of state: modesw progress state */
++
++#define WL_E_MODESW_FLAG_DEVICE_LOCAL		0x00u /* flag - device: info is about self/local */
++#define WL_E_MODESW_FLAG_DEVICE_PEER		0x01u /* flag - device: info is about peer */
++
++#define WL_E_MODESW_FLAG_FROM_FIRMWARE		0x00u /* flag - from: request is from firmware */
++#define WL_E_MODESW_FLAG_FROM_USER		0x02u /* flag - from: request is from user/iov */
++
++#define WL_E_MODESW_FLAG_STATE_REQUESTED	0x00u /* flag - state: mode switch request */
++#define WL_E_MODESW_FLAG_STATE_INITIATED	0x04u /* flag - state: switch initiated */
++#define WL_E_MODESW_FLAG_STATE_COMPLETE		0x08u /* flag - state: switch completed/success */
++#define WL_E_MODESW_FLAG_STATE_FAILURE		0x0Cu /* flag - state: failed to switch */
++
++/* Get sizeof *X including variable data's length where X is pointer to wl_event_mode_switch_t */
++#define WL_E_MODESW_SIZE(X) (sizeof(*(X)) + (X)->length)
++
++/* Get variable data's length where X is pointer to wl_event_mode_switch_t */
++#define WL_E_MODESW_DATA_SIZE(X) (((X)->length > sizeof(*(X))) ? ((X)->length - sizeof(*(X))) : 0)
++
++#define WL_E_MODESW_REASON_UNKNOWN		0u /* reason: UNKNOWN */
++#define WL_E_MODESW_REASON_ACSD			1u /* reason: ACSD (based on events from FW */
++#define WL_E_MODESW_REASON_OBSS_DBS		2u /* reason: OBSS DBS (eg. on interference) */
++#define WL_E_MODESW_REASON_DFS			3u /* reason: DFS (eg. on subband radar) */
++#define WL_E_MODESW_REASON_DYN160		4u /* reason: DYN160 (160/2x2 - 80/4x4) */
++
++/* event structure for WLC_E_MODE_SWITCH */
++typedef struct {
++	uint16 version;
++	uint16 length;	/* size including 'data' field */
++	uint16 opmode_from;
++	uint16 opmode_to;
++	uint32 flags;	/* bit 0: peer(/local==0);
++			 * bit 1: user(/firmware==0);
++			 * bits 3,2: 00==requested, 01==initiated,
++			 *           10==complete, 11==failure;
++			 * rest: reserved
++			 */
++	uint16 reason;	/* value 0: unknown, 1: ACSD, 2: OBSS_DBS,
++			 *       3: DFS, 4: DYN160, rest: reserved
++			 */
++	uint16 data_offset;	/* offset to 'data' from beginning of this struct.
++				 * fields may be added between data_offset and data
++				 */
++	/* ADD NEW FIELDS HERE */
++	uint8 data[];	/* reason specific data; could be empty */
++} wl_event_mode_switch_t;
++
++/* when reason in WLC_E_MODE_SWITCH is DYN160, data will carry the following structure */
++typedef struct {
++	uint16 trigger;		/* value 0: MU to SU, 1: SU to MU, 2: metric_dyn160, 3:re-/assoc,
++				 *       4: disassoc, 5: rssi, 6: traffic, 7: interference,
++				 *       8: chanim_stats
++				 */
++	struct ether_addr sta_addr;	/* causal STA's MAC address when known */
++	uint16 metric_160_80;		/* latest dyn160 metric */
++	uint8 nss;		/* NSS of the STA */
++	uint8 bw;		/* BW of the STA */
++	int8 rssi;		/* RSSI of the STA */
++	uint8 traffic;		/* internal metric of traffic */
++} wl_event_mode_switch_dyn160;
++
++#define WL_EVENT_FBT_VER_1		1
++
++#define WL_E_FBT_TYPE_FBT_OTD_AUTH	1
++#define WL_E_FBT_TYPE_FBT_OTA_AUTH	2
++
++/* event structure for WLC_E_FBT */
++typedef struct {
++	uint16 version;
++	uint16 length;	/* size including 'data' field */
++	uint16 type; /* value 0: unknown, 1: FBT OTD Auth Req */
++	uint16 data_offset;	/* offset to 'data' from beginning of this struct.
++				 * fields may be added between data_offset and data
++				 */
++	/* ADD NEW FIELDS HERE */
++	uint8 data[];	/* type specific data; could be empty */
++} wl_event_fbt_t;
++
++/* TWT Setup Completion is designed to notify the user of TWT Setup process
++ * status. When 'status' field is value of BCME_OK, the user must check the
++ * 'setup_cmd' field value in 'wl_twt_sdesc_t' structure that at the end of
++ * the event data to see the response from the TWT Responding STA; when
++ * 'status' field is value of BCME_ERROR or non BCME_OK, user must not use
++ * anything from 'wl_twt_sdesc_t' structure as it is the TWT Requesting STA's
++ * own TWT parameter.
++ */
++
++#define WL_TWT_SETUP_CPLT_VER	0
++
++/* TWT Setup Completion event data */
++typedef struct wl_twt_setup_cplt {
++	uint16 version;
++	uint16 length;	/* the byte count of fields from 'dialog' onwards */
++	uint8 dialog;	/* the dialog token user supplied to the TWT setup API */
++	uint8 pad[3];
++	int32 status;
++	/* wl_twt_sdesc_t desc; - defined in wlioctl.h */
++} wl_twt_setup_cplt_t;
++
++#define WL_INVALID_IE_EVENT_VERSION	0
++
++/* Invalid IE Event data */
++typedef struct wl_invalid_ie_event {
++	uint16 version;
++	uint16 len;      /* Length of the invalid IE copy */
++	uint16 type;     /* Type/subtype of the frame which contains the invalid IE */
++	uint16 error;    /* error code of the wrong IE, defined in ie_error_code_t */
++	uint8  ie[];     /* Variable length buffer for the invalid IE copy */
++} wl_invalid_ie_event_t;
++
++/* Fixed header portion of Invalid IE Event */
++typedef struct wl_invalid_ie_event_hdr {
++	uint16 version;
++	uint16 len;      /* Length of the invalid IE copy */
++	uint16 type;     /* Type/subtype of the frame which contains the invalid IE */
++	uint16 error;    /* error code of the wrong IE, defined in ie_error_code_t */
++	/* var length IE data follows */
++} wl_invalid_ie_event_hdr_t;
++
++typedef enum ie_error_code {
++	IE_ERROR_OUT_OF_RANGE = 0x01
++} ie_error_code_t;
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++/* reason of channel switch */
++typedef enum {
++	CHANSW_DFS = 10,	/* channel switch due to DFS module */
++	CHANSW_HOMECH_REQ = 14, /* channel switch due to HOME Channel Request */
++	CHANSW_STA = 15,	/* channel switch due to STA */
++	CHANSW_SOFTAP = 16,	/* channel switch due to SodtAP */
++	CHANSW_AIBSS = 17,	/* channel switch due to AIBSS */
++	CHANSW_NAN = 18,	/* channel switch due to NAN */
++	CHANSW_NAN_DISC = 19,	/* channel switch due to NAN Disc */
++	CHANSW_NAN_SCHED = 20,	/* channel switch due to NAN Sched */
++	CHANSW_AWDL_AW = 21,	/* channel switch due to AWDL aw */
++	CHANSW_AWDL_SYNC = 22,	/* channel switch due to AWDL sync */
++	CHANSW_AWDL_CAL = 23,	/* channel switch due to AWDL Cal */
++	CHANSW_AWDL_PSF = 24,	/* channel switch due to AWDL PSF */
++	CHANSW_AWDL_OOB_AF = 25, /* channel switch due to AWDL OOB action frame */
++	CHANSW_TDLS = 26,	/* channel switch due to TDLS */
++	CHANSW_PROXD = 27,	/* channel switch due to PROXD */
++	CHANSW_MAX_NUMBER = 28	/* max channel switch reason */
++} wl_chansw_reason_t;
++
++#define CHANSW_REASON(reason)	(1 << reason)
++
++#define EVENT_AGGR_DATA_HDR_LEN	8
++
++typedef struct event_aggr_data {
++	uint16  num_events; /* No of events aggregated */
++	uint16	len;	/* length of the aggregated events, excludes padding */
++	uint8	pad[4]; /* Padding to make aggr event packet header aligned
++					 * on 64-bit boundary, for a 64-bit host system.
++					 */
++	uint8	data[];	/* Aggregate buffer containing Events */
++} event_aggr_data_t;
++
++
++/* WLC_E_TVPM_MITIGATION event structure version */
++#define WL_TVPM_MITIGATION_VERSION 1
++
++/* TVPM mitigation on/off status bits */
++#define WL_TVPM_MITIGATION_TXDC		0x1
++#define WL_TVPM_MITIGATION_TXPOWER	0x2
++#define WL_TVPM_MITIGATION_TXCHAINS	0x4
++
++/* Event structure for WLC_E_TVPM_MITIGATION */
++typedef struct wl_event_tvpm_mitigation {
++	uint16 version;		/* structure version */
++	uint16 length;		/* length of this structure */
++	uint32 timestamp_ms;	/* millisecond timestamp */
++	uint8 slice;		/* slice number */
++	uint8 pad;
++	uint16 on_off;		/* mitigation status bits */
++} wl_event_tvpm_mitigation_t;
++
++#endif /* _BCMEVENT_H_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmip.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmip.h
+new file mode 100644
+index 000000000..47781a25a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmip.h
+@@ -0,0 +1,264 @@
++/*
++ * Fundamental constants relating to IP Protocol
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmip.h 700076 2017-05-17 14:42:22Z $
++ */
++
++#ifndef _bcmip_h_
++#define _bcmip_h_
++
++#ifndef _TYPEDEFS_H_
++#include <typedefs.h>
++#endif
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++
++
++/* IPV4 and IPV6 common */
++#define IP_VER_OFFSET		0x0	/* offset to version field */
++#define IP_VER_MASK		0xf0	/* version mask */
++#define IP_VER_SHIFT		4	/* version shift */
++#define IP_VER_4		4	/* version number for IPV4 */
++#define IP_VER_6		6	/* version number for IPV6 */
++
++#define IP_VER(ip_body) \
++	((((uint8 *)(ip_body))[IP_VER_OFFSET] & IP_VER_MASK) >> IP_VER_SHIFT)
++
++#define IP_PROT_ICMP		0x1	/* ICMP protocol */
++#define IP_PROT_IGMP		0x2	/* IGMP protocol */
++#define IP_PROT_TCP		0x6	/* TCP protocol */
++#define IP_PROT_UDP		0x11	/* UDP protocol type */
++#define IP_PROT_GRE		0x2f	/* GRE protocol type */
++#define IP_PROT_ICMP6           0x3a    /* ICMPv6 protocol type */
++
++/* IPV4 field offsets */
++#define IPV4_VER_HL_OFFSET      0       /* version and ihl byte offset */
++#define IPV4_TOS_OFFSET         1       /* type of service offset */
++#define IPV4_PKTLEN_OFFSET      2       /* packet length offset */
++#define IPV4_PKTFLAG_OFFSET     6       /* more-frag,dont-frag flag offset */
++#define IPV4_PROT_OFFSET        9       /* protocol type offset */
++#define IPV4_CHKSUM_OFFSET      10      /* IP header checksum offset */
++#define IPV4_SRC_IP_OFFSET      12      /* src IP addr offset */
++#define IPV4_DEST_IP_OFFSET     16      /* dest IP addr offset */
++#define IPV4_OPTIONS_OFFSET     20      /* IP options offset */
++#define IPV4_MIN_HEADER_LEN     20      /* Minimum size for an IP header (no options) */
++
++/* IPV4 field decodes */
++#define IPV4_VER_MASK		0xf0	/* IPV4 version mask */
++#define IPV4_VER_SHIFT		4	/* IPV4 version shift */
++
++#define IPV4_HLEN_MASK		0x0f	/* IPV4 header length mask */
++#define IPV4_HLEN(ipv4_body)	(4 * (((uint8 *)(ipv4_body))[IPV4_VER_HL_OFFSET] & IPV4_HLEN_MASK))
++
++#define IPV4_ADDR_LEN		4	/* IPV4 address length */
++
++#define IPV4_ADDR_NULL(a)	((((uint8 *)(a))[0] | ((uint8 *)(a))[1] | \
++				  ((uint8 *)(a))[2] | ((uint8 *)(a))[3]) == 0)
++
++#define IPV4_ADDR_BCAST(a)	((((uint8 *)(a))[0] & ((uint8 *)(a))[1] & \
++				  ((uint8 *)(a))[2] & ((uint8 *)(a))[3]) == 0xff)
++
++#define	IPV4_TOS_DSCP_MASK	0xfc	/* DiffServ codepoint mask */
++#define	IPV4_TOS_DSCP_SHIFT	2	/* DiffServ codepoint shift */
++
++#define	IPV4_TOS(ipv4_body)	(((uint8 *)(ipv4_body))[IPV4_TOS_OFFSET])
++
++#define	IPV4_TOS_PREC_MASK	0xe0	/* Historical precedence mask */
++#define	IPV4_TOS_PREC_SHIFT	5	/* Historical precedence shift */
++
++#define IPV4_TOS_LOWDELAY	0x10	/* Lowest delay requested */
++#define IPV4_TOS_THROUGHPUT	0x8	/* Best throughput requested */
++#define IPV4_TOS_RELIABILITY	0x4	/* Most reliable delivery requested */
++
++#define IPV4_TOS_ROUTINE        0
++#define IPV4_TOS_PRIORITY       1
++#define IPV4_TOS_IMMEDIATE      2
++#define IPV4_TOS_FLASH          3
++#define IPV4_TOS_FLASHOVERRIDE  4
++#define IPV4_TOS_CRITICAL       5
++#define IPV4_TOS_INETWORK_CTRL  6
++#define IPV4_TOS_NETWORK_CTRL   7
++
++#define IPV4_PROT(ipv4_body)	(((uint8 *)(ipv4_body))[IPV4_PROT_OFFSET])
++
++#define IPV4_FRAG_RESV		0x8000	/* Reserved */
++#define IPV4_FRAG_DONT		0x4000	/* Don't fragment */
++#define IPV4_FRAG_MORE		0x2000	/* More fragments */
++#define IPV4_FRAG_OFFSET_MASK	0x1fff	/* Fragment offset */
++
++#define IPV4_ADDR_STR_LEN	16	/* Max IP address length in string format */
++
++/* IPV4 packet formats */
++BWL_PRE_PACKED_STRUCT struct ipv4_addr {
++	uint8	addr[IPV4_ADDR_LEN];
++} BWL_POST_PACKED_STRUCT;
++
++BWL_PRE_PACKED_STRUCT struct ipv4_hdr {
++	uint8	version_ihl;		/* Version and Internet Header Length */
++	uint8	tos;			/* Type Of Service */
++	uint16	tot_len;		/* Number of bytes in packet (max 65535) */
++	uint16	id;
++	uint16	frag;			/* 3 flag bits and fragment offset */
++	uint8	ttl;			/* Time To Live */
++	uint8	prot;			/* Protocol */
++	uint16	hdr_chksum;		/* IP header checksum */
++	uint8	src_ip[IPV4_ADDR_LEN];	/* Source IP Address */
++	uint8	dst_ip[IPV4_ADDR_LEN];	/* Destination IP Address */
++} BWL_POST_PACKED_STRUCT;
++
++#define HTYPE_ETHERNET		1		/* htype for ethernet */
++#define ARP_OPC_REQUEST		1		/* ARP request */
++#define ARP_OPC_REPLY		2		/* ARP reply */
++BWL_PRE_PACKED_STRUCT struct bcmarp {
++	uint16	htype;				/* Header type (1 = ethernet) */
++	uint16	ptype;				/* Protocol type (0x800 = IP) */
++	uint8	hlen;				/* Hardware address length (Eth = 6) */
++	uint8	plen;				/* Protocol address length (IP = 4) */
++	uint16	oper;				/* ARP_OPC_... */
++	uint8	src_eth[ETHER_ADDR_LEN];	/* Source hardware address */
++	uint8	src_ip[IPV4_ADDR_LEN];		/* Source protocol address (not aligned) */
++	uint8	dst_eth[ETHER_ADDR_LEN];	/* Destination hardware address */
++	uint8	dst_ip[IPV4_ADDR_LEN];		/* Destination protocol address */
++} BWL_POST_PACKED_STRUCT;
++
++/* IPV6 field offsets */
++#define IPV6_PAYLOAD_LEN_OFFSET	4	/* payload length offset */
++#define IPV6_NEXT_HDR_OFFSET	6	/* next header/protocol offset */
++#define IPV6_HOP_LIMIT_OFFSET	7	/* hop limit offset */
++#define IPV6_SRC_IP_OFFSET	8	/* src IP addr offset */
++#define IPV6_DEST_IP_OFFSET	24	/* dst IP addr offset */
++
++/* IPV6 field decodes */
++#define IPV6_TRAFFIC_CLASS(ipv6_body) \
++	(((((uint8 *)(ipv6_body))[0] & 0x0f) << 4) | \
++	 ((((uint8 *)(ipv6_body))[1] & 0xf0) >> 4))
++
++#define IPV6_FLOW_LABEL(ipv6_body) \
++	(((((uint8 *)(ipv6_body))[1] & 0x0f) << 16) | \
++	 (((uint8 *)(ipv6_body))[2] << 8) | \
++	 (((uint8 *)(ipv6_body))[3]))
++
++#define IPV6_PAYLOAD_LEN(ipv6_body) \
++	((((uint8 *)(ipv6_body))[IPV6_PAYLOAD_LEN_OFFSET + 0] << 8) | \
++	 ((uint8 *)(ipv6_body))[IPV6_PAYLOAD_LEN_OFFSET + 1])
++
++#define IPV6_NEXT_HDR(ipv6_body) \
++	(((uint8 *)(ipv6_body))[IPV6_NEXT_HDR_OFFSET])
++
++#define IPV6_PROT(ipv6_body)	IPV6_NEXT_HDR(ipv6_body)
++
++#define IPV6_ADDR_LEN		16	/* IPV6 address length */
++
++/* IPV4 TOS or IPV6 Traffic Classifier or 0 */
++#define IP_TOS46(ip_body) \
++	(IP_VER(ip_body) == IP_VER_4 ? IPV4_TOS(ip_body) : \
++	 IP_VER(ip_body) == IP_VER_6 ? IPV6_TRAFFIC_CLASS(ip_body) : 0)
++
++#define IP_DSCP46(ip_body) (IP_TOS46(ip_body) >> IPV4_TOS_DSCP_SHIFT);
++
++/* IPV4 or IPV6 Protocol Classifier or 0 */
++#define IP_PROT46(ip_body) \
++	(IP_VER(ip_body) == IP_VER_4 ? IPV4_PROT(ip_body) : \
++	 IP_VER(ip_body) == IP_VER_6 ? IPV6_PROT(ip_body) : 0)
++
++/* IPV6 extension headers (options) */
++#define IPV6_EXTHDR_HOP		0
++#define IPV6_EXTHDR_ROUTING	43
++#define IPV6_EXTHDR_FRAGMENT	44
++#define IPV6_EXTHDR_AUTH	51
++#define IPV6_EXTHDR_NONE	59
++#define IPV6_EXTHDR_DEST	60
++
++#define IPV6_EXTHDR(prot)	(((prot) == IPV6_EXTHDR_HOP) || \
++	                         ((prot) == IPV6_EXTHDR_ROUTING) || \
++	                         ((prot) == IPV6_EXTHDR_FRAGMENT) || \
++	                         ((prot) == IPV6_EXTHDR_AUTH) || \
++	                         ((prot) == IPV6_EXTHDR_NONE) || \
++	                         ((prot) == IPV6_EXTHDR_DEST))
++
++#define IPV6_MIN_HLEN 		40
++
++#define IPV6_EXTHDR_LEN(eh)	((((struct ipv6_exthdr *)(eh))->hdrlen + 1) << 3)
++
++BWL_PRE_PACKED_STRUCT struct ipv6_exthdr {
++	uint8	nexthdr;
++	uint8	hdrlen;
++} BWL_POST_PACKED_STRUCT;
++
++BWL_PRE_PACKED_STRUCT struct ipv6_exthdr_frag {
++	uint8	nexthdr;
++	uint8	rsvd;
++	uint16	frag_off;
++	uint32	ident;
++} BWL_POST_PACKED_STRUCT;
++
++static INLINE int32
++ipv6_exthdr_len(uint8 *h, uint8 *proto)
++{
++	uint16 len = 0, hlen;
++	struct ipv6_exthdr *eh = (struct ipv6_exthdr *)h;
++
++	while (IPV6_EXTHDR(eh->nexthdr)) {
++		if (eh->nexthdr == IPV6_EXTHDR_NONE)
++			return -1;
++		else if (eh->nexthdr == IPV6_EXTHDR_FRAGMENT)
++			hlen = 8;
++		else if (eh->nexthdr == IPV6_EXTHDR_AUTH)
++			hlen = (eh->hdrlen + 2) << 2;
++		else
++			hlen = IPV6_EXTHDR_LEN(eh);
++
++		len += hlen;
++		eh = (struct ipv6_exthdr *)(h + len);
++	}
++
++	*proto = eh->nexthdr;
++	return len;
++}
++
++#define IPV4_ISMULTI(a) (((a) & 0xf0000000) == 0xe0000000)
++
++#define IPV4_MCAST_TO_ETHER_MCAST(ipv4, ether) \
++{ \
++	ether[0] = 0x01; \
++	ether[1] = 0x00; \
++	ether[2] = 0x5E; \
++	ether[3] = (ipv4 & 0x7f0000) >> 16; \
++	ether[4] = (ipv4 & 0xff00) >> 8; \
++	ether[5] = (ipv4 & 0xff); \
++}
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++#define IPV4_ADDR_STR "%d.%d.%d.%d"
++#define IPV4_ADDR_TO_STR(addr)	((uint32)addr & 0xff000000) >> 24, \
++								((uint32)addr & 0x00ff0000) >> 16, \
++								((uint32)addr & 0x0000ff00) >> 8, \
++								((uint32)addr & 0x000000ff)
++
++#endif	/* _bcmip_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmipv6.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmipv6.h
+new file mode 100644
+index 000000000..84e2b693b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmipv6.h
+@@ -0,0 +1,163 @@
++/*
++ * Fundamental constants relating to Neighbor Discovery Protocol
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmipv6.h 700076 2017-05-17 14:42:22Z $
++ */
++
++#ifndef _bcmipv6_h_
++#define _bcmipv6_h_
++
++#ifndef _TYPEDEFS_H_
++#include <typedefs.h>
++#endif
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++
++/* Extension headers */
++#define IPV6_EXT_HOP	0
++#define IPV6_EXT_ROUTE	43
++#define IPV6_EXT_FRAG	44
++#define IPV6_EXT_DEST	60
++#define IPV6_EXT_ESEC	50
++#define IPV6_EXT_AUTH	51
++
++/* Minimum size (extension header "word" length) */
++#define IPV6_EXT_WORD	8
++
++/* Offsets for most extension headers */
++#define IPV6_EXT_NEXTHDR	0
++#define IPV6_EXT_HDRLEN		1
++
++/* Constants specific to fragmentation header */
++#define IPV6_FRAG_MORE_MASK	0x0001
++#define IPV6_FRAG_MORE_SHIFT	0
++#define IPV6_FRAG_OFFS_MASK	0xfff8
++#define IPV6_FRAG_OFFS_SHIFT	3
++
++/* For icmpv6 */
++#define ICMPV6_HEADER_TYPE	0x3A
++#define ICMPV6_PKT_TYPE_RA	134
++#define ICMPV6_PKT_TYPE_NS	135
++#define ICMPV6_PKT_TYPE_NA	136
++
++#define ICMPV6_ND_OPT_TYPE_TARGET_MAC	2
++#define ICMPV6_ND_OPT_TYPE_SRC_MAC		1
++
++#define ICMPV6_ND_OPT_LEN_LINKADDR		1
++
++#define ICMPV6_ND_OPT_LEN_LINKADDR		1
++
++#define IPV6_VERSION 	6
++#define IPV6_HOP_LIMIT 	255
++
++#define IPV6_ADDR_NULL(a)	((a[0] | a[1] | a[2] | a[3] | a[4] | \
++							 a[5] | a[6] | a[7] | a[8] | a[9] | \
++							 a[10] | a[11] | a[12] | a[13] | \
++							 a[14] | a[15]) == 0)
++
++#define IPV6_ADDR_LOCAL(a)	(((a[0] == 0xfe) && (a[1] & 0x80))? TRUE: FALSE)
++
++/* IPV6 address */
++BWL_PRE_PACKED_STRUCT struct ipv6_addr {
++		uint8		addr[16];
++} BWL_POST_PACKED_STRUCT;
++
++
++/* ICMPV6 Header */
++BWL_PRE_PACKED_STRUCT struct icmp6_hdr {
++	uint8	icmp6_type;
++	uint8	icmp6_code;
++	uint16	icmp6_cksum;
++	BWL_PRE_PACKED_STRUCT union {
++		uint32 reserved;
++		BWL_PRE_PACKED_STRUCT struct nd_advt {
++			uint32	reserved1:5,
++				override:1,
++				solicited:1,
++				router:1,
++				reserved2:24;
++		} BWL_POST_PACKED_STRUCT nd_advt;
++	} BWL_POST_PACKED_STRUCT opt;
++} BWL_POST_PACKED_STRUCT;
++
++/* Ipv6 Header Format */
++BWL_PRE_PACKED_STRUCT struct ipv6_hdr {
++	uint8	priority:4,
++		version:4;
++	uint8	flow_lbl[3];
++	uint16	payload_len;
++	uint8	nexthdr;
++	uint8 	hop_limit;
++	struct	ipv6_addr	saddr;
++	struct	ipv6_addr	daddr;
++} BWL_POST_PACKED_STRUCT;
++
++/* Neighbor Advertisement/Solicitation Packet Structure */
++BWL_PRE_PACKED_STRUCT struct bcm_nd_msg {
++	struct	icmp6_hdr	icmph;
++	struct	ipv6_addr	target;
++} BWL_POST_PACKED_STRUCT;
++
++
++/* Neighibor Solicitation/Advertisement Optional Structure */
++BWL_PRE_PACKED_STRUCT struct nd_msg_opt {
++	uint8 type;
++	uint8 len;
++	uint8 mac_addr[ETHER_ADDR_LEN];
++} BWL_POST_PACKED_STRUCT;
++
++/* Ipv6 Fragmentation Header */
++BWL_PRE_PACKED_STRUCT struct ipv6_frag {
++	uint8	nexthdr;
++	uint8	reserved;
++	uint16	frag_offset;
++	uint32	ident;
++} BWL_POST_PACKED_STRUCT;
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++static const struct ipv6_addr all_node_ipv6_maddr = {
++									{ 0xff, 0x2, 0, 0,
++									0, 0, 0, 0,
++									0, 0, 0, 0,
++									0, 0, 0, 1
++									}};
++
++#define IPV6_ISMULTI(a) (a[0] == 0xff)
++
++#define IPV6_MCAST_TO_ETHER_MCAST(ipv6, ether) \
++{ \
++	ether[0] = 0x33; \
++	ether[1] = 0x33; \
++	ether[2] = ipv6[12]; \
++	ether[3] = ipv6[13]; \
++	ether[4] = ipv6[14]; \
++	ether[5] = ipv6[15]; \
++}
++
++#endif	/* !defined(_bcmipv6_h_) */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmmsgbuf.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmmsgbuf.h
+new file mode 100644
+index 000000000..08d66930d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmmsgbuf.h
+@@ -0,0 +1,1202 @@
++/*
++ * MSGBUF network driver ioctl/indication encoding
++ * Broadcom 802.11abg Networking Device Driver
++ *
++ * Definitions subject to change without notice.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmmsgbuf.h 676811 2016-12-24 20:48:46Z $
++ */
++#ifndef _bcmmsgbuf_h_
++#define	_bcmmsgbuf_h_
++
++#include <ethernet.h>
++#include <wlioctl.h>
++#include <bcmpcie.h>
++
++#define MSGBUF_MAX_MSG_SIZE   ETHER_MAX_LEN
++
++#define D2H_EPOCH_MODULO		253 /* sequence number wrap */
++#define D2H_EPOCH_INIT_VAL		(D2H_EPOCH_MODULO + 1)
++
++#define H2D_EPOCH_MODULO		253 /* sequence number wrap */
++#define H2D_EPOCH_INIT_VAL		(H2D_EPOCH_MODULO + 1)
++
++#define H2DRING_TXPOST_ITEMSIZE		48
++#define H2DRING_RXPOST_ITEMSIZE		32
++#define H2DRING_CTRL_SUB_ITEMSIZE	40
++
++#define D2HRING_TXCMPLT_ITEMSIZE	24
++#define D2HRING_RXCMPLT_ITEMSIZE	40
++
++#define D2HRING_TXCMPLT_ITEMSIZE_PREREV7	16
++#define D2HRING_RXCMPLT_ITEMSIZE_PREREV7	32
++
++#define D2HRING_CTRL_CMPLT_ITEMSIZE	24
++#define H2DRING_INFO_BUFPOST_ITEMSIZE	H2DRING_CTRL_SUB_ITEMSIZE
++#define D2HRING_INFO_BUFCMPLT_ITEMSIZE	D2HRING_CTRL_CMPLT_ITEMSIZE
++
++#define H2DRING_TXPOST_MAX_ITEM			512
++#define H2DRING_RXPOST_MAX_ITEM			512
++#define H2DRING_CTRL_SUB_MAX_ITEM		64
++#define D2HRING_TXCMPLT_MAX_ITEM		1024
++#define D2HRING_RXCMPLT_MAX_ITEM		512
++
++#define H2DRING_DYNAMIC_INFO_MAX_ITEM          32
++#define D2HRING_DYNAMIC_INFO_MAX_ITEM          32
++
++#define D2HRING_CTRL_CMPLT_MAX_ITEM		64
++
++enum {
++	DNGL_TO_HOST_MSGBUF,
++	HOST_TO_DNGL_MSGBUF
++};
++
++enum {
++	HOST_TO_DNGL_TXP_DATA,
++	HOST_TO_DNGL_RXP_DATA,
++	HOST_TO_DNGL_CTRL,
++	DNGL_TO_HOST_DATA,
++	DNGL_TO_HOST_CTRL
++};
++
++#define MESSAGE_PAYLOAD(a) (a & MSG_TYPE_INTERNAL_USE_START) ? TRUE : FALSE
++#define PCIEDEV_FIRMWARE_TSINFO 0x1
++
++#ifdef PCIE_API_REV1
++
++#define BCMMSGBUF_DUMMY_REF(a, b)	do {BCM_REFERENCE((a));BCM_REFERENCE((b));}  while (0)
++
++#define BCMMSGBUF_API_IFIDX(a)		0
++#define BCMMSGBUF_API_SEQNUM(a)		0
++#define BCMMSGBUF_IOCTL_XTID(a)		0
++#define BCMMSGBUF_IOCTL_PKTID(a)	((a)->cmd_id)
++
++#define BCMMSGBUF_SET_API_IFIDX(a, b)	BCMMSGBUF_DUMMY_REF(a, b)
++#define BCMMSGBUF_SET_API_SEQNUM(a, b)	BCMMSGBUF_DUMMY_REF(a, b)
++#define BCMMSGBUF_IOCTL_SET_PKTID(a, b)	(BCMMSGBUF_IOCTL_PKTID(a) = (b))
++#define BCMMSGBUF_IOCTL_SET_XTID(a, b)	BCMMSGBUF_DUMMY_REF(a, b)
++
++#else /* PCIE_API_REV1 */
++
++#define BCMMSGBUF_API_IFIDX(a)		((a)->if_id)
++#define BCMMSGBUF_IOCTL_PKTID(a)	((a)->pkt_id)
++#define BCMMSGBUF_API_SEQNUM(a)		((a)->u.seq.seq_no)
++#define BCMMSGBUF_IOCTL_XTID(a)		((a)->xt_id)
++
++#define BCMMSGBUF_SET_API_IFIDX(a, b)	(BCMMSGBUF_API_IFIDX((a)) = (b))
++#define BCMMSGBUF_SET_API_SEQNUM(a, b)	(BCMMSGBUF_API_SEQNUM((a)) = (b))
++#define BCMMSGBUF_IOCTL_SET_PKTID(a, b)	(BCMMSGBUF_IOCTL_PKTID((a)) = (b))
++#define BCMMSGBUF_IOCTL_SET_XTID(a, b)	(BCMMSGBUF_IOCTL_XTID((a)) = (b))
++
++#endif /* PCIE_API_REV1 */
++
++/* utility data structures */
++
++union addr64 {
++	struct {
++		uint32 low;
++		uint32 high;
++	};
++	struct {
++		uint32 low_addr;
++		uint32 high_addr;
++	};
++	uint64 u64;
++} DECLSPEC_ALIGN(8);
++
++typedef union addr64 bcm_addr64_t;
++
++/* IOCTL req Hdr */
++/* cmn Msg Hdr */
++typedef struct cmn_msg_hdr {
++	/** message type */
++	uint8 msg_type;
++	/** interface index this is valid for */
++	uint8 if_id;
++	/* flags */
++	uint8 flags;
++	/** sequence number */
++	uint8 epoch;
++	/** packet Identifier for the associated host buffer */
++	uint32 request_id;
++} cmn_msg_hdr_t;
++
++/** message type */
++typedef enum bcmpcie_msgtype {
++	MSG_TYPE_GEN_STATUS		= 0x1,
++	MSG_TYPE_RING_STATUS		= 0x2,
++	MSG_TYPE_FLOW_RING_CREATE	= 0x3,
++	MSG_TYPE_FLOW_RING_CREATE_CMPLT	= 0x4,
++	/* Enum value as copied from BISON 7.15: new generic message */
++	MSG_TYPE_RING_CREATE_CMPLT	= 0x4,
++	MSG_TYPE_FLOW_RING_DELETE	= 0x5,
++	MSG_TYPE_FLOW_RING_DELETE_CMPLT	= 0x6,
++	/* Enum value as copied from BISON 7.15: new generic message */
++	MSG_TYPE_RING_DELETE_CMPLT	= 0x6,
++	MSG_TYPE_FLOW_RING_FLUSH	= 0x7,
++	MSG_TYPE_FLOW_RING_FLUSH_CMPLT	= 0x8,
++	MSG_TYPE_IOCTLPTR_REQ		= 0x9,
++	MSG_TYPE_IOCTLPTR_REQ_ACK	= 0xA,
++	MSG_TYPE_IOCTLRESP_BUF_POST	= 0xB,
++	MSG_TYPE_IOCTL_CMPLT		= 0xC,
++	MSG_TYPE_EVENT_BUF_POST		= 0xD,
++	MSG_TYPE_WL_EVENT		= 0xE,
++	MSG_TYPE_TX_POST		= 0xF,
++	MSG_TYPE_TX_STATUS		= 0x10,
++	MSG_TYPE_RXBUF_POST		= 0x11,
++	MSG_TYPE_RX_CMPLT		= 0x12,
++	MSG_TYPE_LPBK_DMAXFER 		= 0x13,
++	MSG_TYPE_LPBK_DMAXFER_CMPLT	= 0x14,
++	MSG_TYPE_FLOW_RING_RESUME	 = 0x15,
++	MSG_TYPE_FLOW_RING_RESUME_CMPLT	= 0x16,
++	MSG_TYPE_FLOW_RING_SUSPEND	= 0x17,
++	MSG_TYPE_FLOW_RING_SUSPEND_CMPLT	= 0x18,
++	MSG_TYPE_INFO_BUF_POST		= 0x19,
++	MSG_TYPE_INFO_BUF_CMPLT		= 0x1A,
++	MSG_TYPE_H2D_RING_CREATE	= 0x1B,
++	MSG_TYPE_D2H_RING_CREATE	= 0x1C,
++	MSG_TYPE_H2D_RING_CREATE_CMPLT	= 0x1D,
++	MSG_TYPE_D2H_RING_CREATE_CMPLT	= 0x1E,
++	MSG_TYPE_H2D_RING_CONFIG	= 0x1F,
++	MSG_TYPE_D2H_RING_CONFIG	= 0x20,
++	MSG_TYPE_H2D_RING_CONFIG_CMPLT	= 0x21,
++	MSG_TYPE_D2H_RING_CONFIG_CMPLT	= 0x22,
++	MSG_TYPE_H2D_MAILBOX_DATA	= 0x23,
++	MSG_TYPE_D2H_MAILBOX_DATA	= 0x24,
++	MSG_TYPE_TIMSTAMP_BUFPOST	= 0x25,
++	MSG_TYPE_HOSTTIMSTAMP		= 0x26,
++	MSG_TYPE_HOSTTIMSTAMP_CMPLT	= 0x27,
++	MSG_TYPE_FIRMWARE_TIMESTAMP	= 0x28,
++	MSG_TYPE_API_MAX_RSVD		= 0x3F
++} bcmpcie_msg_type_t;
++
++typedef enum bcmpcie_msgtype_int {
++	MSG_TYPE_INTERNAL_USE_START	= 0x40,
++	MSG_TYPE_EVENT_PYLD		= 0x41,
++	MSG_TYPE_IOCT_PYLD		= 0x42,
++	MSG_TYPE_RX_PYLD		= 0x43,
++	MSG_TYPE_HOST_FETCH		= 0x44,
++	MSG_TYPE_LPBK_DMAXFER_PYLD	= 0x45,
++	MSG_TYPE_TXMETADATA_PYLD	= 0x46,
++	MSG_TYPE_INDX_UPDATE		= 0x47,
++	MSG_TYPE_INFO_PYLD		= 0x48,
++	MSG_TYPE_TS_EVENT_PYLD		= 0x49
++} bcmpcie_msgtype_int_t;
++
++typedef enum bcmpcie_msgtype_u {
++	MSG_TYPE_TX_BATCH_POST		= 0x80,
++	MSG_TYPE_IOCTL_REQ		= 0x81,
++	MSG_TYPE_HOST_EVNT		= 0x82, /* console related */
++	MSG_TYPE_LOOPBACK		= 0x83
++} bcmpcie_msgtype_u_t;
++
++/**
++ * D2H ring host wakeup soft doorbell, override the PCIE doorbell.
++ * Host configures an <32bit address,value> tuple, and dongle uses SBTOPCIE
++ * Transl0 to write specified value to host address.
++ *
++ * Use case: 32bit Address mapped to HW Accelerator Core/Thread Wakeup Register
++ * and value is Core/Thread context. Host will ensure routing the 32bit address
++ * offerred to PCIE to the mapped register.
++ *
++ * D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL
++ */
++typedef struct bcmpcie_soft_doorbell {
++	uint32	value;  /* host defined value to be written, eg HW threadid */
++	bcm_addr64_t haddr; /* host address, eg thread wakeup register address */
++	uint16	items;  /* interrupt coalescing: item count before wakeup */
++	uint16	msecs;  /* interrupt coalescing: timeout in millisecs */
++} bcmpcie_soft_doorbell_t;
++
++/**
++ * D2H interrupt using MSI instead of INTX
++ * Host configures MSI vector offset for each D2H interrupt
++ *
++ * D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL
++ */
++typedef enum bcmpcie_msi_intr_idx {
++	MSI_INTR_IDX_CTRL_CMPL_RING,
++	MSI_INTR_IDX_TXP_CMPL_RING,
++	MSI_INTR_IDX_RXP_CMPL_RING,
++	MSI_INTR_IDX_MAILBOX,
++	MSI_INTR_IDX_MAX
++} bcmpcie_msi_intr_idx_t;
++
++typedef enum bcmpcie_msi_offset_type {
++	BCMPCIE_D2H_MSI_OFFSET_MB0 = 2,
++	BCMPCIE_D2H_MSI_OFFSET_MB1,
++	BCMPCIE_D2H_MSI_OFFSET_DB0,
++	BCMPCIE_D2H_MSI_OFFSET_DB1,
++	BCMPCIE_D2H_MSI_OFFSET_MAX
++} bcmpcie_msi_offset_type_t;
++
++typedef struct bcmpcie_msi_offset {
++	uint16	intr_idx;    /* interrupt index */
++	uint16	msi_offset;  /* msi vector offset */
++} bcmpcie_msi_offset_t;
++
++typedef struct bcmpcie_msi_offset_config {
++	uint32	len;
++	bcmpcie_msi_offset_t	bcmpcie_msi_offset[MSI_INTR_IDX_MAX];
++} bcmpcie_msi_offset_config_t;
++
++#define BCMPCIE_D2H_MSI_OFFSET_DEFAULT	BCMPCIE_D2H_MSI_OFFSET_DB1
++
++
++/* if_id */
++#define BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT	5
++#define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX	0x7
++#define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MASK	\
++	(BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT)
++#define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_SHFT	0
++#define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MAX	0x1F
++#define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MASK	\
++	(BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT)
++
++/* flags */
++#define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX		0x1
++#define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX_INTR	0x2
++#define BCMPCIE_CMNHDR_FLAGS_PHASE_BIT		0x80
++#define BCMPCIE_CMNHDR_PHASE_BIT_INIT		0x80
++
++/* IOCTL request message */
++typedef struct ioctl_req_msg {
++	/** common message header */
++	cmn_msg_hdr_t 	cmn_hdr;
++	/** ioctl command type */
++	uint32		cmd;
++	/** ioctl transaction ID, to pair with a ioctl response */
++	uint16		trans_id;
++	/** input arguments buffer len */
++	uint16		input_buf_len;
++	/** expected output len */
++	uint16		output_buf_len;
++	/** to align the host address on 8 byte boundary */
++	uint16		rsvd[3];
++	/** always align on 8 byte boundary */
++	bcm_addr64_t	host_input_buf_addr;
++	/* rsvd */
++	uint32		rsvd1[2];
++} ioctl_req_msg_t;
++
++/** buffer post messages for device to use to return IOCTL responses, Events */
++typedef struct ioctl_resp_evt_buf_post_msg {
++	/** common message header */
++	cmn_msg_hdr_t	cmn_hdr;
++	/** length of the host buffer supplied */
++	uint16		host_buf_len;
++	/** to align the host address on 8 byte boundary */
++	uint16		reserved[3];
++	/** always align on 8 byte boundary */
++	bcm_addr64_t	host_buf_addr;
++	uint32		rsvd[4];
++} ioctl_resp_evt_buf_post_msg_t;
++
++/* buffer post messages for device to use to return dbg buffers */
++typedef ioctl_resp_evt_buf_post_msg_t info_buf_post_msg_t;
++
++
++/* An infobuf host buffer starts with a 32 bit (LE) version. */
++#define PCIE_INFOBUF_V1                1
++/* Infobuf v1 type MSGTRACE's data is exactly the same as the MSGTRACE data that
++ * is wrapped previously/also in a WLC_E_TRACE event.  See structure
++ * msgrace_hdr_t in msgtrace.h.
++*/
++#define PCIE_INFOBUF_V1_TYPE_MSGTRACE  1
++
++/* Infobuf v1 type LOGTRACE data is exactly the same as the LOGTRACE data that
++ * is wrapped previously/also in a WLC_E_TRACE event.  See structure
++ * msgrace_hdr_t in msgtrace.h.  (The only difference between a MSGTRACE
++ * and a LOGTRACE is the "trace type" field.)
++*/
++#define PCIE_INFOBUF_V1_TYPE_LOGTRACE  2
++
++/* An infobuf version 1 host buffer has a single TLV.  The information on the
++ * version 1 types follow this structure definition. (int's LE)
++*/
++typedef struct info_buf_payload_hdr_s {
++	uint16 type;
++	uint16 length;
++} info_buf_payload_hdr_t;
++
++#define PCIE_DMA_XFER_FLG_D11_LPBK_MASK	0x00000001
++#define PCIE_DMA_XFER_FLG_D11_LPBK_SHIFT	0
++
++typedef struct pcie_dma_xfer_params {
++	/** common message header */
++	cmn_msg_hdr_t	cmn_hdr;
++
++	/** always align on 8 byte boundary */
++	bcm_addr64_t	host_input_buf_addr;
++
++	/** always align on 8 byte boundary */
++	bcm_addr64_t	host_ouput_buf_addr;
++
++	/** length of transfer */
++	uint32		xfer_len;
++	/** delay before doing the src txfer */
++	uint32		srcdelay;
++	/** delay before doing the dest txfer */
++	uint32		destdelay;
++	uint8		rsvd[3];
++	uint8		flags;
++} pcie_dma_xfer_params_t;
++
++/** Complete msgbuf hdr for flow ring update from host to dongle */
++typedef struct tx_flowring_create_request {
++	cmn_msg_hdr_t   msg;
++	uint8	da[ETHER_ADDR_LEN];
++	uint8	sa[ETHER_ADDR_LEN];
++	uint8	tid;
++	uint8 	if_flags;
++	uint16	flow_ring_id;
++	uint8 	tc;
++	/* priority_ifrmmask is to define core mask in ifrm mode.
++	 * currently it is not used for priority. so uses solely for ifrm mask
++	 */
++	uint8	priority_ifrmmask;
++	uint16 	int_vector;
++	uint16	max_items;
++	uint16	len_item;
++	bcm_addr64_t flow_ring_ptr;
++} tx_flowring_create_request_t;
++
++typedef struct tx_flowring_delete_request {
++	cmn_msg_hdr_t   msg;
++	uint16	flow_ring_id;
++	uint16 	reason;
++	uint32	rsvd[7];
++} tx_flowring_delete_request_t;
++
++typedef struct tx_flowring_flush_request {
++	cmn_msg_hdr_t   msg;
++	uint16	flow_ring_id;
++	uint16 	reason;
++	uint32	rsvd[7];
++} tx_flowring_flush_request_t;
++
++/** Subtypes for ring_config_req control message */
++typedef enum ring_config_subtype {
++	/** Default D2H PCIE doorbell override using ring_config_req msg */
++	D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL = 1, /* Software doorbell */
++	D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL = 2   /* MSI configuration */
++} ring_config_subtype_t;
++
++typedef struct ring_config_req {
++	cmn_msg_hdr_t	msg;
++	uint16	subtype;
++	uint16	ring_id;
++	uint32	rsvd;
++	union {
++		uint32  data[6];
++		/** D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL */
++		bcmpcie_soft_doorbell_t soft_doorbell;
++		/** D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL */
++		bcmpcie_msi_offset_config_t msi_offset;
++	};
++} ring_config_req_t;
++
++/* data structure to use to create on the fly d2h rings */
++typedef struct d2h_ring_create_req {
++	cmn_msg_hdr_t	msg;
++	uint16	ring_id;
++	uint16	ring_type;
++	uint32	flags;
++	bcm_addr64_t	ring_ptr;
++	uint16	max_items;
++	uint16	len_item;
++	uint32	rsvd[3];
++} d2h_ring_create_req_t;
++
++/* data structure to use to create on the fly h2d rings */
++#define MAX_COMPLETION_RING_IDS_ASSOCIATED	4
++typedef struct h2d_ring_create_req {
++	cmn_msg_hdr_t	msg;
++	uint16	ring_id;
++	uint8	ring_type;
++	uint8	n_completion_ids;
++	uint32	flags;
++	bcm_addr64_t	ring_ptr;
++	uint16	max_items;
++	uint16	len_item;
++	uint16	completion_ring_ids[MAX_COMPLETION_RING_IDS_ASSOCIATED];
++	uint32	rsvd;
++} h2d_ring_create_req_t;
++
++typedef struct d2h_ring_config_req {
++	cmn_msg_hdr_t   msg;
++	uint16	d2h_ring_config_subtype;
++	uint16	d2h_ring_id;
++	uint32  d2h_ring_config_data[4];
++	uint32  rsvd[3];
++} d2h_ring_config_req_t;
++
++typedef struct h2d_ring_config_req {
++	cmn_msg_hdr_t   msg;
++	uint16	h2d_ring_config_subtype;
++	uint16	h2d_ring_id;
++	uint32  h2d_ring_config_data;
++	uint32  rsvd[6];
++} h2d_ring_config_req_t;
++
++typedef struct h2d_mailbox_data {
++	cmn_msg_hdr_t   msg;
++	uint32	mail_box_data;
++	uint32  rsvd[7];
++} h2d_mailbox_data_t;
++typedef struct host_timestamp_msg {
++	cmn_msg_hdr_t	msg;
++	uint16		xt_id; /* transaction ID */
++	uint16		input_data_len; /* data len at the host_buf_addr, data in TLVs */
++	uint16		seqnum; /* number of times host captured the timestamp */
++	uint16		rsvd;
++	/* always align on 8 byte boundary */
++	bcm_addr64_t	host_buf_addr;
++	/* rsvd */
++	uint32      rsvd1[4];
++} host_timestamp_msg_t;
++
++/* buffer post message for timestamp events MSG_TYPE_TIMSTAMP_BUFPOST */
++typedef ioctl_resp_evt_buf_post_msg_t ts_buf_post_msg_t;
++
++typedef union ctrl_submit_item {
++	ioctl_req_msg_t			ioctl_req;
++	ioctl_resp_evt_buf_post_msg_t	resp_buf_post;
++	pcie_dma_xfer_params_t		dma_xfer;
++	tx_flowring_create_request_t	flow_create;
++	tx_flowring_delete_request_t	flow_delete;
++	tx_flowring_flush_request_t	flow_flush;
++	ring_config_req_t		ring_config_req;
++	d2h_ring_create_req_t		d2h_create;
++	h2d_ring_create_req_t		h2d_create;
++	d2h_ring_config_req_t		d2h_config;
++	h2d_ring_config_req_t		h2d_config;
++	h2d_mailbox_data_t		h2d_mailbox_data;
++	host_timestamp_msg_t		host_ts;
++	ts_buf_post_msg_t		ts_buf_post;
++	unsigned char			check[H2DRING_CTRL_SUB_ITEMSIZE];
++} ctrl_submit_item_t;
++
++typedef struct info_ring_submit_item {
++	info_buf_post_msg_t		info_buf_post;
++	unsigned char			check[H2DRING_INFO_BUFPOST_ITEMSIZE];
++} info_sumbit_item_t;
++
++/** Control Completion messages (20 bytes) */
++typedef struct compl_msg_hdr {
++	/** status for the completion */
++	int16	status;
++	/** submisison flow ring id which generated this status */
++	union {
++	    uint16	ring_id;
++	    uint16	flow_ring_id;
++	};
++} compl_msg_hdr_t;
++
++/** XOR checksum or a magic number to audit DMA done */
++typedef uint32 dma_done_t;
++
++#define MAX_CLKSRC_ID	0xF
++
++typedef struct ts_timestamp_srcid {
++	union {
++		uint32	ts_low; /* time stamp low 32 bits */
++		uint32	reserved; /* If timestamp not used */
++	};
++	union {
++		uint32  ts_high; /* time stamp high 28 bits */
++		union {
++			uint32  ts_high_ext :28; /* time stamp high 28 bits */
++			uint32  clk_id_ext :3; /* clock ID source  */
++			uint32  phase :1; /* Phase bit */
++			dma_done_t	marker_ext;
++		};
++	};
++} ts_timestamp_srcid_t;
++
++typedef ts_timestamp_srcid_t ipc_timestamp_t;
++
++typedef struct ts_timestamp {
++	uint32	low;
++	uint32	high;
++} ts_timestamp_t;
++
++typedef ts_timestamp_t tick_count_64_t;
++typedef ts_timestamp_t ts_timestamp_ns_64_t;
++typedef ts_timestamp_t ts_correction_m_t;
++typedef ts_timestamp_t ts_correction_b_t;
++
++/* completion header status codes */
++#define	BCMPCIE_SUCCESS			0
++#define BCMPCIE_NOTFOUND		1
++#define BCMPCIE_NOMEM			2
++#define BCMPCIE_BADOPTION		3
++#define BCMPCIE_RING_IN_USE		4
++#define BCMPCIE_RING_ID_INVALID		5
++#define BCMPCIE_PKT_FLUSH		6
++#define BCMPCIE_NO_EVENT_BUF		7
++#define BCMPCIE_NO_RX_BUF		8
++#define BCMPCIE_NO_IOCTLRESP_BUF	9
++#define BCMPCIE_MAX_IOCTLRESP_BUF	10
++#define BCMPCIE_MAX_EVENT_BUF		11
++#define BCMPCIE_BAD_PHASE		12
++#define BCMPCIE_INVALID_CPL_RINGID	13
++#define BCMPCIE_RING_TYPE_INVALID	14
++#define BCMPCIE_NO_TS_EVENT_BUF		15
++#define BCMPCIE_MAX_TS_EVENT_BUF	16
++
++/** IOCTL completion response */
++typedef struct ioctl_compl_resp_msg {
++	/** common message header */
++	cmn_msg_hdr_t		cmn_hdr;
++	/** completion message header */
++	compl_msg_hdr_t		compl_hdr;
++	/** response buffer len where a host buffer is involved */
++	uint16			resp_len;
++	/** transaction id to pair with a request */
++	uint16			trans_id;
++	/** cmd id */
++	uint32			cmd;
++	/** XOR checksum or a magic number to audit DMA done */
++	dma_done_t		marker;
++} ioctl_comp_resp_msg_t;
++
++/** IOCTL request acknowledgement */
++typedef struct ioctl_req_ack_msg {
++	/** common message header */
++	cmn_msg_hdr_t		cmn_hdr;
++	/** completion message header */
++	compl_msg_hdr_t 	compl_hdr;
++	/** cmd id */
++	uint32			cmd;
++	uint32			rsvd;
++	/** XOR checksum or a magic number to audit DMA done */
++	dma_done_t		marker;
++} ioctl_req_ack_msg_t;
++
++/** WL event message: send from device to host */
++typedef struct wlevent_req_msg {
++	/** common message header */
++	cmn_msg_hdr_t		cmn_hdr;
++	/** completion message header */
++	compl_msg_hdr_t		compl_hdr;
++	/** event data len valid with the event buffer */
++	uint16			event_data_len;
++	/** sequence number */
++	uint16			seqnum;
++	/** rsvd	*/
++	uint32			rsvd;
++	/** XOR checksum or a magic number to audit DMA done */
++	dma_done_t		marker;
++} wlevent_req_msg_t;
++
++/** dma xfer complete message */
++typedef struct pcie_dmaxfer_cmplt {
++	/** common message header */
++	cmn_msg_hdr_t		cmn_hdr;
++	/** completion message header */
++	compl_msg_hdr_t		compl_hdr;
++	uint32			rsvd[2];
++	/** XOR checksum or a magic number to audit DMA done */
++	dma_done_t		marker;
++} pcie_dmaxfer_cmplt_t;
++
++/** general status message */
++typedef struct pcie_gen_status {
++	/** common message header */
++	cmn_msg_hdr_t		cmn_hdr;
++	/** completion message header */
++	compl_msg_hdr_t		compl_hdr;
++	uint32			rsvd[2];
++	/** XOR checksum or a magic number to audit DMA done */
++	dma_done_t		marker;
++} pcie_gen_status_t;
++
++/** ring status message */
++typedef struct pcie_ring_status {
++	/** common message header */
++	cmn_msg_hdr_t		cmn_hdr;
++	/** completion message header */
++	compl_msg_hdr_t		compl_hdr;
++	/** message which firmware couldn't decode */
++	uint16			write_idx;
++	uint16			rsvd[3];
++	/** XOR checksum or a magic number to audit DMA done */
++	dma_done_t		marker;
++} pcie_ring_status_t;
++
++typedef struct ring_create_response {
++	cmn_msg_hdr_t		cmn_hdr;
++	compl_msg_hdr_t 	cmplt;
++	uint32			rsvd[2];
++	/** XOR checksum or a magic number to audit DMA done */
++	dma_done_t		marker;
++} ring_create_response_t;
++
++typedef ring_create_response_t tx_flowring_create_response_t;
++typedef ring_create_response_t h2d_ring_create_response_t;
++typedef ring_create_response_t d2h_ring_create_response_t;
++
++typedef struct tx_flowring_delete_response {
++	cmn_msg_hdr_t		msg;
++	compl_msg_hdr_t 	cmplt;
++	uint32			rsvd[2];
++	/** XOR checksum or a magic number to audit DMA done */
++	dma_done_t		marker;
++} tx_flowring_delete_response_t;
++
++typedef struct tx_flowring_flush_response {
++	cmn_msg_hdr_t		msg;
++	compl_msg_hdr_t 	cmplt;
++	uint32			rsvd[2];
++	/** XOR checksum or a magic number to audit DMA done */
++	dma_done_t		marker;
++} tx_flowring_flush_response_t;
++
++/** Common layout of all d2h control messages */
++typedef struct ctrl_compl_msg {
++	/** common message header */
++	cmn_msg_hdr_t       cmn_hdr;
++	/** completion message header */
++	compl_msg_hdr_t     compl_hdr;
++	uint32          rsvd[2];
++	/** XOR checksum or a magic number to audit DMA done */
++	dma_done_t      marker;
++} ctrl_compl_msg_t;
++
++typedef struct ring_config_resp {
++	/** common message header */
++	cmn_msg_hdr_t       cmn_hdr;
++	/** completion message header */
++	compl_msg_hdr_t     compl_hdr;
++	uint32          rsvd[2];
++	/** XOR checksum or a magic number to audit DMA done */
++	dma_done_t      marker;
++} ring_config_resp_t;
++
++typedef struct d2h_mailbox_data {
++	cmn_msg_hdr_t		msg;
++	compl_msg_hdr_t		cmplt;
++	uint32			d2h_mailbox_data;
++	uint32			rsvd[1];
++	/* XOR checksum or a magic number to audit DMA done */
++	dma_done_t		marker;
++} d2h_mailbox_data_t;
++
++/* dbg buf completion msg: send from device to host */
++typedef struct info_buf_resp {
++	/* common message header */
++	cmn_msg_hdr_t		cmn_hdr;
++	/* completion message header */
++	compl_msg_hdr_t		compl_hdr;
++	/* event data len valid with the event buffer */
++	uint16			info_data_len;
++	/* sequence number */
++	uint16			seqnum;
++	/* rsvd	*/
++	uint32			rsvd;
++	/* XOR checksum or a magic number to audit DMA done */
++	dma_done_t		marker;
++} info_buf_resp_t;
++
++typedef struct info_ring_cpl_item {
++	info_buf_resp_t		info_buf_post;
++	unsigned char		check[D2HRING_INFO_BUFCMPLT_ITEMSIZE];
++} info_cpl_item_t;
++
++typedef struct host_timestamp_msg_cpl {
++	cmn_msg_hdr_t		msg;
++	compl_msg_hdr_t cmplt;
++	uint16			xt_id; /* transaction ID */
++	uint16			rsvd;
++	uint32			rsvd1;
++	/* XOR checksum or a magic number to audit DMA done */
++	dma_done_t      marker;
++} host_timestamp_msg_cpl_t;
++
++typedef struct fw_timestamp_event_msg {
++	cmn_msg_hdr_t		msg;
++	compl_msg_hdr_t cmplt;
++	/* fw captures time stamp info and passed that to host in TLVs */
++	uint16			buf_len; /* length of the time stamp data copied in host buf */
++	uint16			seqnum; /* number of times fw captured time stamp */
++	uint32			rsvd;
++	/* XOR checksum or a magic number to audit DMA done */
++	dma_done_t		marker;
++} fw_timestamp_event_msg_t;
++
++typedef union ctrl_completion_item {
++	ioctl_comp_resp_msg_t		ioctl_resp;
++	wlevent_req_msg_t		event;
++	ioctl_req_ack_msg_t		ioct_ack;
++	pcie_dmaxfer_cmplt_t		pcie_xfer_cmplt;
++	pcie_gen_status_t		pcie_gen_status;
++	pcie_ring_status_t		pcie_ring_status;
++	tx_flowring_create_response_t	txfl_create_resp;
++	tx_flowring_delete_response_t	txfl_delete_resp;
++	tx_flowring_flush_response_t	txfl_flush_resp;
++	ctrl_compl_msg_t		ctrl_compl;
++	ring_config_resp_t		ring_config_resp;
++	d2h_mailbox_data_t		d2h_mailbox_data;
++	info_buf_resp_t			dbg_resp;
++	h2d_ring_create_response_t	h2d_ring_create_resp;
++	d2h_ring_create_response_t	d2h_ring_create_resp;
++	host_timestamp_msg_cpl_t	host_ts_cpl;
++	fw_timestamp_event_msg_t	fw_ts_event;
++	unsigned char			ctrl_response[D2HRING_CTRL_CMPLT_ITEMSIZE];
++} ctrl_completion_item_t;
++
++/** H2D Rxpost ring work items */
++typedef struct host_rxbuf_post {
++	/** common message header */
++	cmn_msg_hdr_t   cmn_hdr;
++	/** provided meta data buffer len */
++	uint16		metadata_buf_len;
++	/** provided data buffer len to receive data */
++	uint16		data_buf_len;
++	/** alignment to make the host buffers start on 8 byte boundary */
++	uint32		rsvd;
++	/** provided meta data buffer */
++	bcm_addr64_t	metadata_buf_addr;
++	/** provided data buffer to receive data */
++	bcm_addr64_t	data_buf_addr;
++} host_rxbuf_post_t;
++
++typedef union rxbuf_submit_item {
++	host_rxbuf_post_t	rxpost;
++	unsigned char		check[H2DRING_RXPOST_ITEMSIZE];
++} rxbuf_submit_item_t;
++
++/* D2H Rxcompletion ring work items for IPC rev7 */
++typedef struct host_rxbuf_cmpl {
++	/** common message header */
++	cmn_msg_hdr_t	cmn_hdr;
++	/** completion message header */
++	compl_msg_hdr_t	compl_hdr;
++	/**  filled up meta data len */
++	uint16		metadata_len;
++	/** filled up buffer len to receive data */
++	uint16		data_len;
++	/** offset in the host rx buffer where the data starts */
++	uint16		data_offset;
++	/** offset in the host rx buffer where the data starts */
++	uint16		flags;
++	/** rx status */
++	uint32		rx_status_0;
++	uint32		rx_status_1;
++	/** XOR checksum or a magic number to audit DMA done */
++	/* This is for rev6 only. For IPC rev7, this is a reserved field */
++	dma_done_t	marker;
++	/* timestamp */
++	ipc_timestamp_t ts;
++} host_rxbuf_cmpl_t;
++
++typedef union rxbuf_complete_item {
++	host_rxbuf_cmpl_t	rxcmpl;
++	unsigned char		check[D2HRING_RXCMPLT_ITEMSIZE];
++} rxbuf_complete_item_t;
++
++
++typedef struct host_txbuf_post {
++	/** common message header */
++	cmn_msg_hdr_t   cmn_hdr;
++	/** eth header */
++	uint8		txhdr[ETHER_HDR_LEN];
++	/** flags */
++	uint8		flags;
++	/** number of segments */
++	uint8		seg_cnt;
++
++	/** provided meta data buffer for txstatus */
++	bcm_addr64_t	metadata_buf_addr;
++	/** provided data buffer to receive data */
++	bcm_addr64_t	data_buf_addr;
++	/** provided meta data buffer len */
++	uint16		metadata_buf_len;
++	/** provided data buffer len to receive data */
++	uint16		data_len;
++	/** XOR checksum or a magic number to audit DMA done */
++	dma_done_t	marker;
++} host_txbuf_post_t;
++
++#define BCMPCIE_PKT_FLAGS_FRAME_802_3	0x01
++#define BCMPCIE_PKT_FLAGS_FRAME_802_11	0x02
++
++#define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_MASK	0x03	/* Exempt uses 2 bits */
++#define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_SHIFT	0x02	/* needs to be shifted past other bits */
++
++
++#define BCMPCIE_PKT_FLAGS_PRIO_SHIFT		5
++#define BCMPCIE_PKT_FLAGS_PRIO_MASK		(7 << BCMPCIE_PKT_FLAGS_PRIO_SHIFT)
++#define BCMPCIE_PKT_FLAGS_MONITOR_NO_AMSDU	0x00
++#define BCMPCIE_PKT_FLAGS_MONITOR_FIRST_PKT	0x01
++#define BCMPCIE_PKT_FLAGS_MONITOR_INTER_PKT	0x02
++#define BCMPCIE_PKT_FLAGS_MONITOR_LAST_PKT	0x03
++#define BCMPCIE_PKT_FLAGS_MONITOR_SHIFT		8
++#define BCMPCIE_PKT_FLAGS_MONITOR_MASK		(3 << BCMPCIE_PKT_FLAGS_MONITOR_SHIFT)
++
++/* These are added to fix up compile issues */
++#define BCMPCIE_TXPOST_FLAGS_FRAME_802_3	BCMPCIE_PKT_FLAGS_FRAME_802_3
++#define BCMPCIE_TXPOST_FLAGS_FRAME_802_11	BCMPCIE_PKT_FLAGS_FRAME_802_11
++#define BCMPCIE_TXPOST_FLAGS_PRIO_SHIFT		BCMPCIE_PKT_FLAGS_PRIO_SHIFT
++#define BCMPCIE_TXPOST_FLAGS_PRIO_MASK		BCMPCIE_PKT_FLAGS_PRIO_MASK
++
++
++/* H2D Txpost ring work items */
++typedef union txbuf_submit_item {
++	host_txbuf_post_t	txpost;
++	unsigned char		check[H2DRING_TXPOST_ITEMSIZE];
++} txbuf_submit_item_t;
++
++/* D2H Txcompletion ring work items - extended for IOC rev7 */
++typedef struct host_txbuf_cmpl {
++	/** common message header */
++	cmn_msg_hdr_t	cmn_hdr;
++	/** completion message header */
++	compl_msg_hdr_t	compl_hdr;
++	union {
++		struct {
++			/** provided meta data len */
++			uint16	metadata_len;
++			/** WLAN side txstatus */
++			uint16	tx_status;
++		};
++		/** XOR checksum or a magic number to audit DMA done */
++		/* This is for rev6 only. For IPC rev7, this is not used */
++		dma_done_t	marker;
++	};
++	/* timestamp */
++	ipc_timestamp_t ts;
++
++} host_txbuf_cmpl_t;
++
++typedef union txbuf_complete_item {
++	host_txbuf_cmpl_t	txcmpl;
++	unsigned char		check[D2HRING_TXCMPLT_ITEMSIZE];
++} txbuf_complete_item_t;
++
++#define BCMPCIE_D2H_METADATA_HDRLEN	4
++#define BCMPCIE_D2H_METADATA_MINLEN	(BCMPCIE_D2H_METADATA_HDRLEN + 4)
++
++/** ret buf struct */
++typedef struct ret_buf_ptr {
++	uint32 low_addr;
++	uint32 high_addr;
++} ret_buf_t;
++
++
++#ifdef PCIE_API_REV1
++
++/* ioctl specific hdr */
++typedef struct ioctl_hdr {
++	uint16 		cmd;
++	uint16		retbuf_len;
++	uint32		cmd_id;
++} ioctl_hdr_t;
++
++typedef struct ioctlptr_hdr {
++	uint16 		cmd;
++	uint16		retbuf_len;
++	uint16 		buflen;
++	uint16		rsvd;
++	uint32		cmd_id;
++} ioctlptr_hdr_t;
++
++#else /* PCIE_API_REV1 */
++
++typedef struct ioctl_req_hdr {
++	uint32		pkt_id;	/**< Packet ID */
++	uint32 		cmd;	/**< IOCTL ID */
++	uint16		retbuf_len;
++	uint16 		buflen;
++	uint16		xt_id;	/**< transaction ID */
++	uint16		rsvd[1];
++} ioctl_req_hdr_t;
++
++#endif /* PCIE_API_REV1 */
++
++
++/** Complete msgbuf hdr for ioctl from host to dongle */
++typedef struct ioct_reqst_hdr {
++	cmn_msg_hdr_t msg;
++#ifdef PCIE_API_REV1
++	ioctl_hdr_t ioct_hdr;
++#else
++	ioctl_req_hdr_t ioct_hdr;
++#endif
++	ret_buf_t ret_buf;
++} ioct_reqst_hdr_t;
++
++typedef struct ioctptr_reqst_hdr {
++	cmn_msg_hdr_t msg;
++#ifdef PCIE_API_REV1
++	ioctlptr_hdr_t ioct_hdr;
++#else
++	ioctl_req_hdr_t ioct_hdr;
++#endif
++	ret_buf_t ret_buf;
++	ret_buf_t ioct_buf;
++} ioctptr_reqst_hdr_t;
++
++/** ioctl response header */
++typedef struct ioct_resp_hdr {
++	cmn_msg_hdr_t   msg;
++#ifdef PCIE_API_REV1
++	uint32	cmd_id;
++#else
++	uint32	pkt_id;
++#endif
++	uint32	status;
++	uint32	ret_len;
++	uint32  inline_data;
++#ifdef PCIE_API_REV1
++#else
++	uint16	xt_id;	/**< transaction ID */
++	uint16	rsvd[1];
++#endif
++} ioct_resp_hdr_t;
++
++/* ioct resp header used in dongle */
++/* ret buf hdr will be stripped off inside dongle itself */
++typedef struct msgbuf_ioctl_resp {
++	ioct_resp_hdr_t	ioct_hdr;
++	ret_buf_t	ret_buf;	/**< ret buf pointers */
++} msgbuf_ioct_resp_t;
++
++/** WL event hdr info */
++typedef struct wl_event_hdr {
++	cmn_msg_hdr_t   msg;
++	uint16 event;
++	uint8 flags;
++	uint8 rsvd;
++	uint16 retbuf_len;
++	uint16 rsvd1;
++	uint32 rxbufid;
++} wl_event_hdr_t;
++
++#define TXDESCR_FLOWID_PCIELPBK_1	0xFF
++#define TXDESCR_FLOWID_PCIELPBK_2	0xFE
++
++typedef struct txbatch_lenptr_tup {
++	uint32 pktid;
++	uint16 pktlen;
++	uint16 rsvd;
++	ret_buf_t	ret_buf;	/**< ret buf pointers */
++} txbatch_lenptr_tup_t;
++
++typedef struct txbatch_cmn_msghdr {
++	cmn_msg_hdr_t   msg;
++	uint8 priority;
++	uint8 hdrlen;
++	uint8 pktcnt;
++	uint8 flowid;
++	uint8 txhdr[ETHER_HDR_LEN];
++	uint16 rsvd;
++} txbatch_cmn_msghdr_t;
++
++typedef struct txbatch_msghdr {
++	txbatch_cmn_msghdr_t txcmn;
++	txbatch_lenptr_tup_t tx_tup[0]; /**< Based on packet count */
++} txbatch_msghdr_t;
++
++/* TX desc posting header */
++typedef struct tx_lenptr_tup {
++	uint16 pktlen;
++	uint16 rsvd;
++	ret_buf_t	ret_buf;	/**< ret buf pointers */
++} tx_lenptr_tup_t;
++
++typedef struct txdescr_cmn_msghdr {
++	cmn_msg_hdr_t   msg;
++	uint8 priority;
++	uint8 hdrlen;
++	uint8 descrcnt;
++	uint8 flowid;
++	uint32 pktid;
++} txdescr_cmn_msghdr_t;
++
++typedef struct txdescr_msghdr {
++	txdescr_cmn_msghdr_t txcmn;
++	uint8 txhdr[ETHER_HDR_LEN];
++	uint16 rsvd;
++	tx_lenptr_tup_t tx_tup[0];	/**< Based on descriptor count */
++} txdescr_msghdr_t;
++
++/** Tx status header info */
++typedef struct txstatus_hdr {
++	cmn_msg_hdr_t   msg;
++	uint32 pktid;
++} txstatus_hdr_t;
++
++/** RX bufid-len-ptr tuple */
++typedef struct rx_lenptr_tup {
++	uint32 rxbufid;
++	uint16 len;
++	uint16 rsvd2;
++	ret_buf_t	ret_buf;	/**< ret buf pointers */
++} rx_lenptr_tup_t;
++
++/** Rx descr Post hdr info */
++typedef struct rxdesc_msghdr {
++	cmn_msg_hdr_t   msg;
++	uint16 rsvd0;
++	uint8 rsvd1;
++	uint8 descnt;
++	rx_lenptr_tup_t rx_tup[0];
++} rxdesc_msghdr_t;
++
++/** RX complete tuples */
++typedef struct rxcmplt_tup {
++	uint16 retbuf_len;
++	uint16 data_offset;
++	uint32 rxstatus0;
++	uint32 rxstatus1;
++	uint32 rxbufid;
++} rxcmplt_tup_t;
++
++/** RX complete messge hdr */
++typedef struct rxcmplt_hdr {
++	cmn_msg_hdr_t   msg;
++	uint16 rsvd0;
++	uint16 rxcmpltcnt;
++	rxcmplt_tup_t rx_tup[0];
++} rxcmplt_hdr_t;
++
++typedef struct hostevent_hdr {
++	cmn_msg_hdr_t   msg;
++	uint32 evnt_pyld;
++} hostevent_hdr_t;
++
++typedef struct dma_xfer_params {
++	uint32 src_physaddr_hi;
++	uint32 src_physaddr_lo;
++	uint32 dest_physaddr_hi;
++	uint32 dest_physaddr_lo;
++	uint32 len;
++	uint32 srcdelay;
++	uint32 destdelay;
++} dma_xfer_params_t;
++
++enum {
++	HOST_EVENT_CONS_CMD = 1
++};
++
++/* defines for flags */
++#define MSGBUF_IOC_ACTION_MASK 0x1
++
++#define MAX_SUSPEND_REQ 15
++
++typedef struct tx_idle_flowring_suspend_request {
++	cmn_msg_hdr_t   msg;
++	uint16	ring_id[MAX_SUSPEND_REQ];      /* ring Id's */
++	uint16	num;	/* number of flowid's to suspend */
++} tx_idle_flowring_suspend_request_t;
++
++typedef struct tx_idle_flowring_suspend_response {
++	cmn_msg_hdr_t		msg;
++	compl_msg_hdr_t		cmplt;
++	uint32			rsvd[2];
++	dma_done_t		marker;
++} tx_idle_flowring_suspend_response_t;
++
++typedef struct tx_idle_flowring_resume_request {
++	cmn_msg_hdr_t   msg;
++	uint16	flow_ring_id;
++	uint16	reason;
++	uint32	rsvd[7];
++} tx_idle_flowring_resume_request_t;
++
++typedef struct tx_idle_flowring_resume_response {
++	cmn_msg_hdr_t		msg;
++	compl_msg_hdr_t		cmplt;
++	uint32			rsvd[2];
++	dma_done_t		marker;
++} tx_idle_flowring_resume_response_t;
++
++/* timesync related additions */
++
++typedef struct _bcm_xtlv {
++	uint16		id; /* TLV idenitifier */
++	uint16		len; /* TLV length in bytes */
++} _bcm_xtlv_t;
++
++#define BCMMSGBUF_FW_CLOCK_INFO_TAG		0
++#define BCMMSGBUF_HOST_CLOCK_INFO_TAG		1
++#define BCMMSGBUF_HOST_CLOCK_SELECT_TAG		2
++#define BCMMSGBUF_D2H_CLOCK_CORRECTION_TAG	3
++#define BCMMSGBUF_HOST_TIMESTAMPING_CONFIG_TAG	4
++#define BCMMSGBUF_MAX_TSYNC_TAG			5
++
++/* Flags in fw clock info TLV */
++#define CAP_DEVICE_TS		(1 << 0)
++#define CAP_CORRECTED_TS	(1 << 1)
++#define TS_CLK_ACTIVE		(1 << 2)
++
++typedef struct ts_fw_clock_info {
++	_bcm_xtlv_t  xtlv; /* BCMMSGBUF_FW_CLOCK_INFO_TAG */
++	ts_timestamp_srcid_t  ts; /* tick count */
++	uchar		clk_src[4]; /* clock source acronym ILP/AVB/TSF */
++	uint32		nominal_clock_freq;
++	uint32		reset_cnt;
++	uint8		flags;
++	uint8		rsvd[3];
++} ts_fw_clock_info_t;
++
++typedef struct ts_host_clock_info {
++	_bcm_xtlv_t  xtlv; /* BCMMSGBUF_HOST_CLOCK_INFO_TAG */
++	tick_count_64_t ticks; /* 64 bit host tick counter */
++	ts_timestamp_ns_64_t ns; /* 64 bit host time in nano seconds */
++} ts_host_clock_info_t;
++
++typedef struct ts_host_clock_sel {
++	_bcm_xtlv_t	xtlv; /* BCMMSGBUF_HOST_CLOCK_SELECT_TAG */
++	uint32		seqnum; /* number of times GPIO time sync toggled */
++	uint8		min_clk_idx; /* clock idenitifer configured for packet tiem stamping */
++	uint8		max_clk_idx; /* clock idenitifer configured for packet tiem stamping */
++	uint16		rsvd[1];
++} ts_host_clock_sel_t;
++
++typedef struct ts_d2h_clock_correction {
++	_bcm_xtlv_t		xtlv; /* BCMMSGBUF_HOST_CLOCK_INFO_TAG */
++	uint8			clk_id; /* clock source in the device */
++	uint8			rsvd[3];
++	ts_correction_m_t	m;	/* y  = 'm' x + b */
++	ts_correction_b_t	b;	/* y  = 'm' x + 'c' */
++} ts_d2h_clock_correction_t;
++
++typedef struct ts_host_timestamping_config {
++	_bcm_xtlv_t		xtlv; /* BCMMSGBUF_HOST_TIMESTAMPING_CONFIG_TAG */
++	/* time period to capture the device time stamp and toggle WLAN_TIME_SYNC_GPIO */
++	uint16			period_ms;
++	uint8			flags;
++	uint8			rsvd;
++	uint32			reset_cnt;
++} ts_host_timestamping_config_t;
++
++/* Flags in host timestamping config TLV */
++#define FLAG_HOST_RESET		(1 << 0)
++
++#endif /* _bcmmsgbuf_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmnvram.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmnvram.h
+new file mode 100644
+index 000000000..15b58568a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmnvram.h
+@@ -0,0 +1,329 @@
++/*
++ * NVRAM variable manipulation
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmnvram.h 613043 2016-01-16 00:24:13Z $
++ */
++
++#ifndef _bcmnvram_h_
++#define _bcmnvram_h_
++
++#ifndef _LANGUAGE_ASSEMBLY
++
++#include <typedefs.h>
++#include <bcmdefs.h>
++
++struct nvram_header {
++	uint32 magic;
++	uint32 len;
++	uint32 crc_ver_init;	/* 0:7 crc, 8:15 ver, 16:31 sdram_init */
++	uint32 config_refresh;	/* 0:15 sdram_config, 16:31 sdram_refresh */
++	uint32 config_ncdl;	/* ncdl values for memc */
++};
++
++struct nvram_tuple {
++	char *name;
++	char *value;
++	struct nvram_tuple *next;
++};
++
++/*
++ * Get default value for an NVRAM variable
++ */
++extern char *nvram_default_get(const char *name);
++/*
++ * validate/restore all per-interface related variables
++ */
++extern void nvram_validate_all(char *prefix, bool restore);
++
++/*
++ * restore specific per-interface variable
++ */
++extern void nvram_restore_var(char *prefix, char *name);
++
++/*
++ * Initialize NVRAM access. May be unnecessary or undefined on certain
++ * platforms.
++ */
++extern int nvram_init(void *sih);
++extern int nvram_deinit(void *sih);
++
++
++/*
++ * Append a chunk of nvram variables to the global list
++ */
++extern int nvram_append(void *si, char *vars, uint varsz);
++
++extern void nvram_get_global_vars(char **varlst, uint *varsz);
++
++
++/*
++ * Check for reset button press for restoring factory defaults.
++ */
++extern int nvram_reset(void *sih);
++
++/*
++ * Disable NVRAM access. May be unnecessary or undefined on certain
++ * platforms.
++ */
++extern void nvram_exit(void *sih);
++
++/*
++ * Get the value of an NVRAM variable. The pointer returned may be
++ * invalid after a set.
++ * @param	name	name of variable to get
++ * @return	value of variable or NULL if undefined
++ */
++extern char * nvram_get(const char *name);
++
++/*
++ * Get the value of an NVRAM variable. The pointer returned may be
++ * invalid after a set.
++ * @param	name	name of variable to get
++ * @param	bit	bit value to get
++ * @return	value of variable or NULL if undefined
++ */
++extern char * nvram_get_bitflag(const char *name, const int bit);
++
++/*
++ * Read the reset GPIO value from the nvram and set the GPIO
++ * as input
++ */
++extern int nvram_resetgpio_init(void *sih);
++
++/*
++ * Get the value of an NVRAM variable.
++ * @param	name	name of variable to get
++ * @return	value of variable or NUL if undefined
++ */
++static INLINE char *
++nvram_safe_get(const char *name)
++{
++	char *p = nvram_get(name);
++	return p ? p : "";
++}
++
++/*
++ * Match an NVRAM variable.
++ * @param	name	name of variable to match
++ * @param	match	value to compare against value of variable
++ * @return	TRUE if variable is defined and its value is string equal
++ *		to match or FALSE otherwise
++ */
++static INLINE int
++nvram_match(const char *name, const char *match)
++{
++	const char *value = nvram_get(name);
++
++	/* In nvramstubs.c builds, nvram_get() is defined as returning zero,
++	* so the return line below never executes the strcmp(),
++	* resulting in 'match' being an unused parameter.
++	* Make a ref to 'match' to quiet the compiler warning.
++	*/
++
++	BCM_REFERENCE(match);
++
++	return (value && !strcmp(value, match));
++}
++
++/*
++ * Match an NVRAM variable.
++ * @param	name	name of variable to match
++ * @param	bit	bit value to get
++ * @param	match	value to compare against value of variable
++ * @return	TRUE if variable is defined and its value is string equal
++ *		to match or FALSE otherwise
++ */
++static INLINE int
++nvram_match_bitflag(const char *name, const int bit, const char *match)
++{
++	const char *value = nvram_get_bitflag(name, bit);
++	BCM_REFERENCE(match);
++	return (value && !strcmp(value, match));
++}
++
++/*
++ * Inversely match an NVRAM variable.
++ * @param	name	name of variable to match
++ * @param	match	value to compare against value of variable
++ * @return	TRUE if variable is defined and its value is not string
++ *		equal to invmatch or FALSE otherwise
++ */
++static INLINE int
++nvram_invmatch(const char *name, const char *invmatch)
++{
++	const char *value = nvram_get(name);
++
++	/* In nvramstubs.c builds, nvram_get() is defined as returning zero,
++	* so the return line below never executes the strcmp(),
++	* resulting in 'invmatch' being an unused parameter.
++	* Make a ref to 'invmatch' to quiet the compiler warning.
++	*/
++
++	BCM_REFERENCE(invmatch);
++
++	return (value && strcmp(value, invmatch));
++}
++
++/*
++ * Set the value of an NVRAM variable. The name and value strings are
++ * copied into private storage. Pointers to previously set values
++ * may become invalid. The new value may be immediately
++ * retrieved but will not be permanently stored until a commit.
++ * @param	name	name of variable to set
++ * @param	value	value of variable
++ * @return	0 on success and errno on failure
++ */
++extern int nvram_set(const char *name, const char *value);
++
++/*
++ * Set the value of an NVRAM variable. The name and value strings are
++ * copied into private storage. Pointers to previously set values
++ * may become invalid. The new value may be immediately
++ * retrieved but will not be permanently stored until a commit.
++ * @param	name	name of variable to set
++ * @param	bit	bit value to set
++ * @param	value	value of variable
++ * @return	0 on success and errno on failure
++ */
++extern int nvram_set_bitflag(const char *name, const int bit, const int value);
++/*
++ * Unset an NVRAM variable. Pointers to previously set values
++ * remain valid until a set.
++ * @param	name	name of variable to unset
++ * @return	0 on success and errno on failure
++ * NOTE: use nvram_commit to commit this change to flash.
++ */
++extern int nvram_unset(const char *name);
++
++/*
++ * Commit NVRAM variables to permanent storage. All pointers to values
++ * may be invalid after a commit.
++ * NVRAM values are undefined after a commit.
++ * @param   nvram_corrupt    true to corrupt nvram, false otherwise.
++ * @return	0 on success and errno on failure
++ */
++extern int nvram_commit_internal(bool nvram_corrupt);
++
++/*
++ * Commit NVRAM variables to permanent storage. All pointers to values
++ * may be invalid after a commit.
++ * NVRAM values are undefined after a commit.
++ * @return	0 on success and errno on failure
++ */
++extern int nvram_commit(void);
++
++/*
++ * Get all NVRAM variables (format name=value\0 ... \0\0).
++ * @param	buf	buffer to store variables
++ * @param	count	size of buffer in bytes
++ * @return	0 on success and errno on failure
++ */
++extern int nvram_getall(char *nvram_buf, int count);
++
++/*
++ * returns the crc value of the nvram
++ * @param	nvh	nvram header pointer
++ */
++uint8 nvram_calc_crc(struct nvram_header * nvh);
++
++extern int nvram_space;
++#endif /* _LANGUAGE_ASSEMBLY */
++
++/* The NVRAM version number stored as an NVRAM variable */
++#define NVRAM_SOFTWARE_VERSION	"1"
++
++#define NVRAM_MAGIC		0x48534C46	/* 'FLSH' */
++#define NVRAM_CLEAR_MAGIC	0x0
++#define NVRAM_INVALID_MAGIC	0xFFFFFFFF
++#define NVRAM_VERSION		1
++#define NVRAM_HEADER_SIZE	20
++/* This definition is for precommit staging, and will be removed */
++#define NVRAM_SPACE		0x8000
++/* For CFE builds this gets passed in thru the makefile */
++#ifndef MAX_NVRAM_SPACE
++#define MAX_NVRAM_SPACE		0x10000
++#endif
++#define DEF_NVRAM_SPACE		0x8000
++#define ROM_ENVRAM_SPACE	0x1000
++#define NVRAM_LZMA_MAGIC	0x4c5a4d41	/* 'LZMA' */
++
++#define NVRAM_MAX_VALUE_LEN 255
++#define NVRAM_MAX_PARAM_LEN 64
++
++#define NVRAM_CRC_START_POSITION	9 /* magic, len, crc8 to be skipped */
++#define NVRAM_CRC_VER_MASK	0xffffff00 /* for crc_ver_init */
++
++/* Offsets to embedded nvram area */
++#define NVRAM_START_COMPRESSED	0x400
++#define NVRAM_START		0x1000
++
++#define BCM_JUMBO_NVRAM_DELIMIT '\n'
++#define BCM_JUMBO_START "Broadcom Jumbo Nvram file"
++
++
++#if (defined(FAILSAFE_UPGRADE) || defined(CONFIG_FAILSAFE_UPGRADE) || \
++	defined(__CONFIG_FAILSAFE_UPGRADE_SUPPORT__))
++#define IMAGE_SIZE "image_size"
++#define BOOTPARTITION "bootpartition"
++#define IMAGE_BOOT BOOTPARTITION
++#define PARTIALBOOTS "partialboots"
++#define MAXPARTIALBOOTS "maxpartialboots"
++#define IMAGE_1ST_FLASH_TRX "flash0.trx"
++#define IMAGE_1ST_FLASH_OS "flash0.os"
++#define IMAGE_2ND_FLASH_TRX "flash0.trx2"
++#define IMAGE_2ND_FLASH_OS "flash0.os2"
++#define IMAGE_FIRST_OFFSET "image_first_offset"
++#define IMAGE_SECOND_OFFSET "image_second_offset"
++#define LINUX_FIRST "linux"
++#define LINUX_SECOND "linux2"
++#endif
++
++#if (defined(DUAL_IMAGE) || defined(CONFIG_DUAL_IMAGE) || \
++	defined(__CONFIG_DUAL_IMAGE_FLASH_SUPPORT__))
++/* Shared by all: CFE, Linux Kernel, and Ap */
++#define IMAGE_BOOT "image_boot"
++#define BOOTPARTITION IMAGE_BOOT
++/* CFE variables */
++#define IMAGE_1ST_FLASH_TRX "flash0.trx"
++#define IMAGE_1ST_FLASH_OS "flash0.os"
++#define IMAGE_2ND_FLASH_TRX "flash0.trx2"
++#define IMAGE_2ND_FLASH_OS "flash0.os2"
++#define IMAGE_SIZE "image_size"
++
++/* CFE and Linux Kernel shared variables */
++#define IMAGE_FIRST_OFFSET "image_first_offset"
++#define IMAGE_SECOND_OFFSET "image_second_offset"
++
++/* Linux application variables */
++#define LINUX_FIRST "linux"
++#define LINUX_SECOND "linux2"
++#define POLICY_TOGGLE "toggle"
++#define LINUX_PART_TO_FLASH "linux_to_flash"
++#define LINUX_FLASH_POLICY "linux_flash_policy"
++
++#endif /* defined(DUAL_IMAGE||CONFIG_DUAL_IMAGE)||__CONFIG_DUAL_IMAGE_FLASH_SUPPORT__ */
++
++#endif /* _bcmnvram_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmpcie.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmpcie.h
+new file mode 100644
+index 000000000..114924cc9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmpcie.h
+@@ -0,0 +1,440 @@
++/*
++ * Broadcom PCIE
++ * Software-specific definitions shared between device and host side
++ * Explains the shared area between host and dongle
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmpcie.h 678914 2017-01-11 15:34:26Z $
++ */
++
++
++#ifndef	_bcmpcie_h_
++#define	_bcmpcie_h_
++
++#include <bcmutils.h>
++
++#define ADDR_64(x)			(x.addr)
++#define HIGH_ADDR_32(x)     ((uint32) (((sh_addr_t) x).high_addr))
++#define LOW_ADDR_32(x)      ((uint32) (((sh_addr_t) x).low_addr))
++
++typedef struct {
++	uint32 low_addr;
++	uint32 high_addr;
++} sh_addr_t;
++
++
++/* May be overridden by 43xxxxx-roml.mk */
++#if !defined(BCMPCIE_MAX_TX_FLOWS)
++#define BCMPCIE_MAX_TX_FLOWS	40
++#endif /* ! BCMPCIE_MAX_TX_FLOWS */
++
++#define PCIE_SHARED_VERSION_7		0x00007
++#define PCIE_SHARED_VERSION_6		0x00006 /* rev6 is compatible with rev 5 */
++#define PCIE_SHARED_VERSION_5		0x00005 /* rev6 is compatible with rev 5 */
++/**
++ * Feature flags enabled in dongle. Advertised by dongle to DHD via the PCIe Shared structure that
++ * is located in device memory.
++ */
++#define PCIE_SHARED_VERSION		PCIE_SHARED_VERSION_7
++#define PCIE_SHARED_VERSION_MASK	0x000FF
++#define PCIE_SHARED_ASSERT_BUILT	0x00100
++#define PCIE_SHARED_ASSERT		0x00200
++#define PCIE_SHARED_TRAP		0x00400
++#define PCIE_SHARED_IN_BRPT		0x00800
++#define PCIE_SHARED_SET_BRPT		0x01000
++#define PCIE_SHARED_PENDING_BRPT	0x02000
++/* BCMPCIE_SUPPORT_TX_PUSH_RING		0x04000 obsolete */
++#define PCIE_SHARED_EVT_SEQNUM		0x08000
++#define PCIE_SHARED_DMA_INDEX		0x10000
++
++/* WAR: D11 txstatus through unused status field of PCIe completion header */
++#define PCIE_SHARED_D2H_D11_TX_STATUS  0x40000000	/* using flags2 in shared area */
++#define PCIE_SHARED_H2D_D11_TX_STATUS  0x80000000	/* using flags2 in shared area */
++
++/**
++ * There are host types where a device interrupt can 'race ahead' of data written by the device into
++ * host memory. The dongle can avoid this condition using a variety of techniques (read barrier,
++ * using PCIe Message Signalled Interrupts, or by using the PCIE_DMA_INDEX feature). Unfortunately
++ * these techniques have drawbacks on router platforms. For these platforms, it was decided to not
++ * avoid the condition, but to detect the condition instead and act on it.
++ * D2H M2M DMA Complete Sync mechanism: Modulo-253-SeqNum or XORCSUM
++ */
++#define PCIE_SHARED_D2H_SYNC_SEQNUM     0x20000
++#define PCIE_SHARED_D2H_SYNC_XORCSUM    0x40000
++#define PCIE_SHARED_D2H_SYNC_MODE_MASK \
++	(PCIE_SHARED_D2H_SYNC_SEQNUM | PCIE_SHARED_D2H_SYNC_XORCSUM)
++#define PCIE_SHARED_IDLE_FLOW_RING		0x80000
++#define PCIE_SHARED_2BYTE_INDICES       0x100000
++
++#define PCIE_SHARED2_EXTENDED_TRAP_DATA	0x00000001	/* using flags2 in shared area */
++
++/* dongle supports fatal buf log collection */
++#define PCIE_SHARED_FATAL_LOGBUG_VALID 0x200000
++
++/* Implicit DMA with corerev 19 and after */
++#define PCIE_SHARED_IDMA		0x400000
++
++/* MSI support */
++#define PCIE_SHARED_D2H_MSI_MULTI_MSG   0x800000
++
++/* IFRM with corerev 19 and after */
++#define PCIE_SHARED_IFRM		0x1000000
++
++/**
++ * From Rev6 and above, suspend/resume can be done using two handshake methods.
++ * 1. Using ctrl post/ctrl cmpl messages (Default rev6)
++ * 2. Using Mailbox data (old method as used in rev5)
++ * This shared flag indicates whether to overide rev6 default method and use mailbox for
++ * suspend/resume.
++ */
++#define PCIE_SHARED_USE_MAILBOX		0x2000000
++
++/* Firmware compiled for mfgbuild purposes */
++#define PCIE_SHARED_MFGBUILD_FW		0x4000000
++
++/* Firmware could use DB0 value as host timestamp */
++#define PCIE_SHARED_TIMESTAMP_DB0	0x8000000
++/* Firmware could use Hostready (IPC rev7) */
++#define PCIE_SHARED_HOSTRDY_SUPPORT	0x10000000
++
++/* When set, Firmwar does not support OOB Device Wake based DS protocol */
++#define PCIE_SHARED_NO_OOB_DW	0x20000000
++
++/* When set, Firmwar supports Inband DS protocol */
++#define PCIE_SHARED_INBAND_DS	0x40000000
++
++/* Implicit DMA WAR for 4347B0 PCIe memory retention */
++#define PCIE_SHARED_IDMA_RETENTION_DS	0x80000000
++
++#define PCIE_SHARED_D2H_MAGIC		0xFEDCBA09
++#define PCIE_SHARED_H2D_MAGIC		0x12345678
++
++/**
++ * Message rings convey messages between host and device. They are unidirectional, and are located
++ * in host memory.
++ *
++ * This is the minimal set of message rings, known as 'common message rings':
++ */
++#define BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT		0
++#define BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT		1
++#define BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE		2
++#define BCMPCIE_D2H_MSGRING_TX_COMPLETE			3
++#define BCMPCIE_D2H_MSGRING_RX_COMPLETE			4
++#define BCMPCIE_COMMON_MSGRING_MAX_ID			4
++
++#define BCMPCIE_H2D_COMMON_MSGRINGS			2
++#define BCMPCIE_D2H_COMMON_MSGRINGS			3
++#define BCMPCIE_COMMON_MSGRINGS				5
++
++#define BCMPCIE_H2D_MSGRINGS(max_tx_flows) \
++	(BCMPCIE_H2D_COMMON_MSGRINGS + (max_tx_flows))
++
++/* different ring types */
++#define BCMPCIE_H2D_RING_TYPE_CTRL_SUBMIT		0x1
++#define BCMPCIE_H2D_RING_TYPE_TXFLOW_RING		0x2
++#define BCMPCIE_H2D_RING_TYPE_RXBUFPOST			0x3
++#define BCMPCIE_H2D_RING_TYPE_TXSUBMIT			0x4
++#define BCMPCIE_H2D_RING_TYPE_DBGBUF_SUBMIT		0x5
++
++#define BCMPCIE_D2H_RING_TYPE_CTRL_CPL			0x1
++#define BCMPCIE_D2H_RING_TYPE_TX_CPL			0x2
++#define BCMPCIE_D2H_RING_TYPE_RX_CPL			0x3
++#define BCMPCIE_D2H_RING_TYPE_DBGBUF_CPL		0x4
++#define BCMPCIE_D2H_RING_TYPE_AC_RX_COMPLETE		0x5
++
++/**
++ * H2D and D2H, WR and RD index, are maintained in the following arrays:
++ * - Array of all H2D WR Indices
++ * - Array of all H2D RD Indices
++ * - Array of all D2H WR Indices
++ * - Array of all D2H RD Indices
++ *
++ * The offset of the WR or RD indexes (for common rings) in these arrays are
++ * listed below. Arrays ARE NOT indexed by a ring's id.
++ *
++ * D2H common rings WR and RD index start from 0, even though their ringids
++ * start from BCMPCIE_H2D_COMMON_MSGRINGS
++ */
++
++#define BCMPCIE_H2D_RING_IDX(h2d_ring_id) (h2d_ring_id)
++
++enum h2dring_idx {
++	/* H2D common rings */
++	BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT_IDX =
++		BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT),
++	BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT_IDX =
++		BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT),
++
++	/* First TxPost's WR or RD index starts after all H2D common rings */
++	BCMPCIE_H2D_MSGRING_TXFLOW_IDX_START =
++		BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_COMMON_MSGRINGS)
++};
++
++#define BCMPCIE_D2H_RING_IDX(d2h_ring_id) \
++	((d2h_ring_id) - BCMPCIE_H2D_COMMON_MSGRINGS)
++
++enum d2hring_idx {
++	/* D2H Common Rings */
++	BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE_IDX =
++		BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE),
++	BCMPCIE_D2H_MSGRING_TX_COMPLETE_IDX =
++		BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_TX_COMPLETE),
++	BCMPCIE_D2H_MSGRING_RX_COMPLETE_IDX =
++		BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_RX_COMPLETE)
++};
++
++/**
++ * Macros for managing arrays of RD WR indices:
++ * rw_index_sz:
++ *    - in dongle, rw_index_sz is known at compile time
++ *    - in host/DHD, rw_index_sz is derived from advertized pci_shared flags
++ *
++ *  ring_idx: See h2dring_idx and d2hring_idx
++ */
++
++/** Offset of a RD or WR index in H2D or D2H indices array */
++#define BCMPCIE_RW_INDEX_OFFSET(rw_index_sz, ring_idx) \
++	((rw_index_sz) * (ring_idx))
++
++/** Fetch the address of RD or WR index in H2D or D2H indices array */
++#define BCMPCIE_RW_INDEX_ADDR(indices_array_base, rw_index_sz, ring_idx) \
++	(void *)((uint32)(indices_array_base) + \
++	BCMPCIE_RW_INDEX_OFFSET((rw_index_sz), (ring_idx)))
++
++/** H2D DMA Indices array size: given max flow rings */
++#define BCMPCIE_H2D_RW_INDEX_ARRAY_SZ(rw_index_sz, max_tx_flows) \
++	((rw_index_sz) * BCMPCIE_H2D_MSGRINGS(max_tx_flows))
++
++/** D2H DMA Indices array size */
++#define BCMPCIE_D2H_RW_INDEX_ARRAY_SZ(rw_index_sz) \
++	((rw_index_sz) * BCMPCIE_D2H_COMMON_MSGRINGS)
++
++/**
++ * This type is used by a 'message buffer' (which is a FIFO for messages). Message buffers are used
++ * for host<->device communication and are instantiated on both sides. ring_mem_t is instantiated
++ * both in host as well as device memory.
++ */
++typedef struct ring_mem {
++	uint16		idx;       /* ring id */
++	uint8		type;
++	uint8		rsvd;
++	uint16		max_item;  /* Max number of items in flow ring */
++	uint16		len_items; /* Items are fixed size. Length in bytes of one item */
++	sh_addr_t	base_addr; /* 64 bits address, either in host or device memory */
++} ring_mem_t;
++
++
++/**
++ * Per flow ring, information is maintained in device memory, eg at what address the ringmem and
++ * ringstate are located. The flow ring itself can be instantiated in either host or device memory.
++ *
++ * Perhaps this type should be renamed to make clear that it resides in device memory only.
++ */
++typedef struct ring_info {
++	uint32		ringmem_ptr; /* ring mem location in dongle memory */
++
++	/* Following arrays are indexed using h2dring_idx and d2hring_idx, and not
++	 * by a ringid.
++	 */
++
++	/* 32bit ptr to arrays of WR or RD indices for all rings in dongle memory */
++	uint32		h2d_w_idx_ptr; /* Array of all H2D ring's WR indices */
++	uint32		h2d_r_idx_ptr; /* Array of all H2D ring's RD indices */
++	uint32		d2h_w_idx_ptr; /* Array of all D2H ring's WR indices */
++	uint32		d2h_r_idx_ptr; /* Array of all D2H ring's RD indices */
++
++	/* PCIE_DMA_INDEX feature: Dongle uses mem2mem DMA to sync arrays in host.
++	 * Host may directly fetch WR and RD indices from these host-side arrays.
++	 *
++	 * 64bit ptr to arrays of WR or RD indices for all rings in host memory.
++	 */
++	sh_addr_t	h2d_w_idx_hostaddr; /* Array of all H2D ring's WR indices */
++	sh_addr_t	h2d_r_idx_hostaddr; /* Array of all H2D ring's RD indices */
++	sh_addr_t	d2h_w_idx_hostaddr; /* Array of all D2H ring's WR indices */
++	sh_addr_t	d2h_r_idx_hostaddr; /* Array of all D2H ring's RD indices */
++
++	uint16		max_tx_flowrings; /* maximum number of H2D rings: common + flow */
++	uint16		max_submission_queues; /* maximum number of H2D rings: common + flow */
++	uint16		max_completion_rings; /* maximum number of H2D rings: common + flow */
++	uint16		max_vdevs; /* max number of virtual interfaces supported */
++
++	sh_addr_t	ifrm_w_idx_hostaddr; /* Array of all H2D ring's WR indices for IFRM */
++} ring_info_t;
++
++/**
++ * A structure located in TCM that is shared between host and device, primarily used during
++ * initialization.
++ */
++typedef struct {
++	/** shared area version captured at flags 7:0 */
++	uint32	flags;
++
++	uint32  trap_addr;
++	uint32  assert_exp_addr;
++	uint32  assert_file_addr;
++	uint32  assert_line;
++	uint32	console_addr;		/**< Address of hnd_cons_t */
++
++	uint32  msgtrace_addr;
++
++	uint32  fwid;
++
++	/* Used for debug/flow control */
++	uint16  total_lfrag_pkt_cnt;
++	uint16  max_host_rxbufs; /* rsvd in spec */
++
++	uint32 dma_rxoffset; /* rsvd in spec */
++
++	/** these will be used for sleep request/ack, d3 req/ack */
++	uint32  h2d_mb_data_ptr;
++	uint32  d2h_mb_data_ptr;
++
++	/* information pertinent to host IPC/msgbuf channels */
++	/** location in the TCM memory which has the ring_info */
++	uint32	rings_info_ptr;
++
++	/** block of host memory for the scratch buffer */
++	uint32		host_dma_scratch_buffer_len;
++	sh_addr_t	host_dma_scratch_buffer;
++
++	/** block of host memory for the dongle to push the status into */
++	uint32		device_rings_stsblk_len;
++	sh_addr_t	device_rings_stsblk;
++
++	uint32	buzz_dbg_ptr;	/* BUZZZ state format strings and trace buffer */
++
++	/* rev6 compatible changes */
++	uint32          flags2;
++	uint32          host_cap;
++
++	/* location in the host address space to write trap indication.
++	* At this point for the current rev of the spec, firmware will
++	* support only indications to 32 bit host addresses.
++	*/
++	sh_addr_t       host_trap_addr;
++
++	/* location for host fatal error log buffer start address */
++	uint32		device_fatal_logbuf_start;
++
++	/* location in host memory for offloaded modules */
++	sh_addr_t   hoffload_addr;
++} pciedev_shared_t;
++
++extern pciedev_shared_t pciedev_shared;
++
++/* host capabilities */
++#define HOSTCAP_PCIEAPI_VERSION_MASK		0x000000FF
++#define HOSTCAP_H2D_VALID_PHASE			0x00000100
++#define HOSTCAP_H2D_ENABLE_TRAP_ON_BADPHASE	0x00000200
++#define HOSTCAP_H2D_ENABLE_HOSTRDY		0x00000400
++#define HOSTCAP_DB0_TIMESTAMP			0x00000800
++#define HOSTCAP_DS_NO_OOB_DW			0x00001000
++#define HOSTCAP_DS_INBAND_DW			0x00002000
++#define HOSTCAP_H2D_IDMA			0x00004000
++#define HOSTCAP_H2D_IFRM			0x00008000
++#define HOSTCAP_H2D_DAR				0x00010000
++#define HOSTCAP_EXTENDED_TRAP_DATA		0x00020000
++#define HOSTCAP_TXSTATUS_METADATA		0x00040000
++
++/**
++ * Mailboxes notify a remote party that an event took place, using interrupts. They use hardware
++ * support.
++ */
++
++/* H2D mail box Data */
++#define H2D_HOST_D3_INFORM	0x00000001
++#define H2D_HOST_DS_ACK		0x00000002
++#define H2D_HOST_DS_NAK		0x00000004
++#define H2D_HOST_CONS_INT	0x80000000	/**< h2d int for console cmds  */
++#define H2D_FW_TRAP		0x20000000	/**< h2d force TRAP */
++#define H2D_HOST_D0_INFORM_IN_USE	0x00000008
++#define H2D_HOST_D0_INFORM	0x00000010
++#define H2D_HOST_IDMA_INITED	0x00000080
++#define H2DMB_DS_HOST_SLEEP_INFORM H2D_HOST_D3_INFORM
++#define H2DMB_DS_DEVICE_SLEEP_ACK  H2D_HOST_DS_ACK
++#define H2DMB_DS_DEVICE_SLEEP_NAK  H2D_HOST_DS_NAK
++#define H2DMB_D0_INFORM_IN_USE     H2D_HOST_D0_INFORM_IN_USE
++#define H2DMB_D0_INFORM            H2D_HOST_D0_INFORM
++#define H2DMB_DS_ACTIVE            0x00000020
++#define H2DMB_DS_DEVICE_WAKE       0x00000040
++#define H2DMB_FW_TRAP              H2D_FW_TRAP
++#define H2DMB_HOST_CONS_INT        H2D_HOST_CONS_INT
++#define H2DMB_DS_DEVICE_WAKE_ASSERT		H2DMB_DS_DEVICE_WAKE
++#define H2DMB_DS_DEVICE_WAKE_DEASSERT	H2DMB_DS_ACTIVE
++
++/* D2H mail box Data */
++#define D2H_DEV_D3_ACK		0x00000001
++#define D2H_DEV_DS_ENTER_REQ	0x00000002
++#define D2H_DEV_DS_EXIT_NOTE	0x00000004
++#define D2H_DEV_FWHALT		0x10000000
++#define D2H_DEV_EXT_TRAP_DATA   0x20000000
++#define D2H_DEV_IDMA_INITED	0x00000010
++#define D2H_FWTRAP_MASK		0x0000001F	/* Adding maskbits for TRAP information */
++#define D2HMB_DS_HOST_SLEEP_ACK         D2H_DEV_D3_ACK
++#define D2HMB_DS_DEVICE_SLEEP_ENTER_REQ D2H_DEV_DS_ENTER_REQ
++#define D2HMB_DS_DEVICE_SLEEP_EXIT      D2H_DEV_DS_EXIT_NOTE
++#define D2HMB_DS_HOST_SLEEP_EXIT_ACK    0x00000008
++#define D2HMB_FWHALT                    D2H_DEV_FWHALT
++#define D2H_DEV_MB_MASK		(D2H_DEV_D3_ACK | D2H_DEV_DS_ENTER_REQ | \
++				D2H_DEV_DS_EXIT_NOTE | D2H_DEV_IDMA_INITED | D2H_DEV_FWHALT | \
++				D2H_FWTRAP_MASK | D2H_DEV_EXT_TRAP_DATA)
++#define D2H_DEV_MB_INVALIDATED(x)	((!x) || (x & ~D2H_DEV_MB_MASK))
++
++
++/** These macro's operate on type 'inuse_lclbuf_pool_t' and are used by firmware only */
++#define NEXTTXP(i, d)           ((((i)+1) >= (d)) ? 0 : ((i)+1))
++#define NTXPACTIVE(r, w, d)     (((r) <= (w)) ? ((w)-(r)) : ((d)-(r)+(w)))
++#define NTXPAVAIL(r, w, d)      (((d) - NTXPACTIVE((r), (w), (d))) > 1)
++
++/* Function can be used to notify host of FW halt */
++#define READ_AVAIL_SPACE(w, r, d)		\
++			((w >= r) ? (w - r) : (d - r))
++
++#define WRITE_SPACE_AVAIL_CONTINUOUS(r, w, d)		((w >= r) ? (d - w) : (r - w))
++#define WRITE_SPACE_AVAIL(r, w, d)	(d - (NTXPACTIVE(r, w, d)) - 1)
++#define CHECK_WRITE_SPACE(r, w, d)	\
++	((r) > (w)) ? ((r) - (w) - 1) : ((r) == 0 || (w) == 0) ? ((d) - (w) - 1) : ((d) - (w))
++#define CHECK_NOWRITE_SPACE(r, w, d)	\
++	(((r) == (w) + 1) || (((r) == 0) && ((w) == ((d) - 1))))
++
++
++#define WRT_PEND(x)	((x)->wr_pending)
++#define DNGL_RING_WPTR(msgbuf)		(*((msgbuf)->tcm_rs_w_ptr)) /**< advanced by producer */
++#define BCMMSGBUF_RING_SET_W_PTR(msgbuf, a)	(DNGL_RING_WPTR(msgbuf) = (a))
++
++#define DNGL_RING_RPTR(msgbuf)		(*((msgbuf)->tcm_rs_r_ptr)) /**< advanced by consumer */
++#define BCMMSGBUF_RING_SET_R_PTR(msgbuf, a)	(DNGL_RING_RPTR(msgbuf) = (a))
++
++#define MODULO_RING_IDX(x, y)	((x) % (y)->bitmap_size)
++
++#define  RING_READ_PTR(x)	((x)->ringstate->r_offset)
++#define  RING_WRITE_PTR(x)	((x)->ringstate->w_offset)
++#define  RING_START_PTR(x)	((x)->ringmem->base_addr.low_addr)
++#define  RING_MAX_ITEM(x)	((x)->ringmem->max_item)
++#define  RING_LEN_ITEMS(x)	((x)->ringmem->len_items)
++#define	 HOST_RING_BASE(x)	((x)->dma_buf.va)
++#define	 HOST_RING_END(x)	((uint8 *)HOST_RING_BASE((x)) + \
++					((RING_MAX_ITEM((x))-1)*RING_LEN_ITEMS((x))))
++#endif	/* _bcmpcie_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmpcispi.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmpcispi.h
+new file mode 100644
+index 000000000..b3502ea7b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmpcispi.h
+@@ -0,0 +1,184 @@
++/*
++ * Broadcom PCI-SPI Host Controller Register Definitions
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmpcispi.h 514727 2014-11-12 03:02:48Z $
++ */
++#ifndef	_BCM_PCI_SPI_H
++#define	_BCM_PCI_SPI_H
++
++/* cpp contortions to concatenate w/arg prescan */
++#ifndef PAD
++#define	_PADLINE(line)	pad ## line
++#define	_XSTR(line)	_PADLINE(line)
++#define	PAD		_XSTR(__LINE__)
++#endif	/* PAD */
++
++
++typedef volatile struct {
++	uint32 spih_ctrl;		/* 0x00 SPI Control Register */
++	uint32 spih_stat;		/* 0x04 SPI Status Register */
++	uint32 spih_data;		/* 0x08 SPI Data Register, 32-bits wide */
++	uint32 spih_ext;		/* 0x0C SPI Extension Register */
++	uint32 PAD[4];			/* 0x10-0x1F PADDING */
++
++	uint32 spih_gpio_ctrl;		/* 0x20 SPI GPIO Control Register */
++	uint32 spih_gpio_data;		/* 0x24 SPI GPIO Data Register */
++	uint32 PAD[6];			/* 0x28-0x3F PADDING */
++
++	uint32 spih_int_edge;		/* 0x40 SPI Interrupt Edge Register (0=Level, 1=Edge) */
++	uint32 spih_int_pol;		/* 0x44 SPI Interrupt Polarity Register (0=Active Low, */
++							/* 1=Active High) */
++	uint32 spih_int_mask;		/* 0x48 SPI Interrupt Mask */
++	uint32 spih_int_status;		/* 0x4C SPI Interrupt Status */
++	uint32 PAD[4];			/* 0x50-0x5F PADDING */
++
++	uint32 spih_hex_disp;		/* 0x60 SPI 4-digit hex display value */
++	uint32 spih_current_ma;		/* 0x64 SPI SD card current consumption in mA */
++	uint32 PAD[1];			/* 0x68 PADDING */
++	uint32 spih_disp_sel;		/* 0x6c SPI 4-digit hex display mode select (1=current) */
++	uint32 PAD[4];			/* 0x70-0x7F PADDING */
++	uint32 PAD[8];			/* 0x80-0x9F PADDING */
++	uint32 PAD[8];			/* 0xA0-0xBF PADDING */
++	uint32 spih_pll_ctrl;	/* 0xC0 PLL Control Register */
++	uint32 spih_pll_status;	/* 0xC4 PLL Status Register */
++	uint32 spih_xtal_freq;	/* 0xC8 External Clock Frequency in units of 10000Hz */
++	uint32 spih_clk_count;	/* 0xCC External Clock Count Register */
++
++} spih_regs_t;
++
++typedef volatile struct {
++	uint32 cfg_space[0x40];		/* 0x000-0x0FF PCI Configuration Space (Read Only) */
++	uint32 P_IMG_CTRL0;		/* 0x100 PCI Image0 Control Register */
++
++	uint32 P_BA0;			/* 0x104 32 R/W PCI Image0 Base Address register */
++	uint32 P_AM0;			/* 0x108 32 R/W PCI Image0 Address Mask register */
++	uint32 P_TA0;			/* 0x10C 32 R/W PCI Image0 Translation Address register */
++	uint32 P_IMG_CTRL1;		/* 0x110 32 R/W PCI Image1 Control register */
++	uint32 P_BA1;			/* 0x114 32 R/W PCI Image1 Base Address register */
++	uint32 P_AM1;			/* 0x118 32 R/W PCI Image1 Address Mask register */
++	uint32 P_TA1;			/* 0x11C 32 R/W PCI Image1 Translation Address register */
++	uint32 P_IMG_CTRL2;		/* 0x120 32 R/W PCI Image2 Control register */
++	uint32 P_BA2;			/* 0x124 32 R/W PCI Image2 Base Address register */
++	uint32 P_AM2;			/* 0x128 32 R/W PCI Image2 Address Mask register */
++	uint32 P_TA2;			/* 0x12C 32 R/W PCI Image2 Translation Address register */
++	uint32 P_IMG_CTRL3;		/* 0x130 32 R/W PCI Image3 Control register */
++	uint32 P_BA3;			/* 0x134 32 R/W PCI Image3 Base Address register */
++	uint32 P_AM3;			/* 0x138 32 R/W PCI Image3 Address Mask register */
++	uint32 P_TA3;			/* 0x13C 32 R/W PCI Image3 Translation Address register */
++	uint32 P_IMG_CTRL4;		/* 0x140 32 R/W PCI Image4 Control register */
++	uint32 P_BA4;			/* 0x144 32 R/W PCI Image4 Base Address register */
++	uint32 P_AM4;			/* 0x148 32 R/W PCI Image4 Address Mask register */
++	uint32 P_TA4;			/* 0x14C 32 R/W PCI Image4 Translation Address register */
++	uint32 P_IMG_CTRL5;		/* 0x150 32 R/W PCI Image5 Control register */
++	uint32 P_BA5;			/* 0x154 32 R/W PCI Image5 Base Address register */
++	uint32 P_AM5;			/* 0x158 32 R/W PCI Image5 Address Mask register */
++	uint32 P_TA5;			/* 0x15C 32 R/W PCI Image5 Translation Address register */
++	uint32 P_ERR_CS;		/* 0x160 32 R/W PCI Error Control and Status register */
++	uint32 P_ERR_ADDR;		/* 0x164 32 R PCI Erroneous Address register */
++	uint32 P_ERR_DATA;		/* 0x168 32 R PCI Erroneous Data register */
++
++	uint32 PAD[5];			/* 0x16C-0x17F PADDING */
++
++	uint32 WB_CONF_SPC_BAR;		/* 0x180 32 R WISHBONE Configuration Space Base Address */
++	uint32 W_IMG_CTRL1;		/* 0x184 32 R/W WISHBONE Image1 Control register */
++	uint32 W_BA1;			/* 0x188 32 R/W WISHBONE Image1 Base Address register */
++	uint32 W_AM1;			/* 0x18C 32 R/W WISHBONE Image1 Address Mask register */
++	uint32 W_TA1;			/* 0x190 32 R/W WISHBONE Image1 Translation Address reg */
++	uint32 W_IMG_CTRL2;		/* 0x194 32 R/W WISHBONE Image2 Control register */
++	uint32 W_BA2;			/* 0x198 32 R/W WISHBONE Image2 Base Address register */
++	uint32 W_AM2;			/* 0x19C 32 R/W WISHBONE Image2 Address Mask register */
++	uint32 W_TA2;			/* 0x1A0 32 R/W WISHBONE Image2 Translation Address reg */
++	uint32 W_IMG_CTRL3;		/* 0x1A4 32 R/W WISHBONE Image3 Control register */
++	uint32 W_BA3;			/* 0x1A8 32 R/W WISHBONE Image3 Base Address register */
++	uint32 W_AM3;			/* 0x1AC 32 R/W WISHBONE Image3 Address Mask register */
++	uint32 W_TA3;			/* 0x1B0 32 R/W WISHBONE Image3 Translation Address reg */
++	uint32 W_IMG_CTRL4;		/* 0x1B4 32 R/W WISHBONE Image4 Control register */
++	uint32 W_BA4;			/* 0x1B8 32 R/W WISHBONE Image4 Base Address register */
++	uint32 W_AM4;			/* 0x1BC 32 R/W WISHBONE Image4 Address Mask register */
++	uint32 W_TA4;			/* 0x1C0 32 R/W WISHBONE Image4 Translation Address reg */
++	uint32 W_IMG_CTRL5;		/* 0x1C4 32 R/W WISHBONE Image5 Control register */
++	uint32 W_BA5;			/* 0x1C8 32 R/W WISHBONE Image5 Base Address register */
++	uint32 W_AM5;			/* 0x1CC 32 R/W WISHBONE Image5 Address Mask register */
++	uint32 W_TA5;			/* 0x1D0 32 R/W WISHBONE Image5 Translation Address reg */
++	uint32 W_ERR_CS;		/* 0x1D4 32 R/W WISHBONE Error Control and Status reg */
++	uint32 W_ERR_ADDR;		/* 0x1D8 32 R WISHBONE Erroneous Address register */
++	uint32 W_ERR_DATA;		/* 0x1DC 32 R WISHBONE Erroneous Data register */
++	uint32 CNF_ADDR;		/* 0x1E0 32 R/W Configuration Cycle register */
++	uint32 CNF_DATA;		/* 0x1E4 32 R/W Configuration Cycle Generation Data reg */
++
++	uint32 INT_ACK;			/* 0x1E8 32 R Interrupt Acknowledge register */
++	uint32 ICR;			/* 0x1EC 32 R/W Interrupt Control register */
++	uint32 ISR;			/* 0x1F0 32 R/W Interrupt Status register */
++} spih_pciregs_t;
++
++/*
++ * PCI Core interrupt enable and status bit definitions.
++ */
++
++/* PCI Core ICR Register bit definitions */
++#define PCI_INT_PROP_EN		(1 << 0)	/* Interrupt Propagation Enable */
++#define PCI_WB_ERR_INT_EN	(1 << 1)	/* Wishbone Error Interrupt Enable */
++#define PCI_PCI_ERR_INT_EN	(1 << 2)	/* PCI Error Interrupt Enable */
++#define PCI_PAR_ERR_INT_EN	(1 << 3)	/* Parity Error Interrupt Enable */
++#define PCI_SYS_ERR_INT_EN	(1 << 4)	/* System Error Interrupt Enable */
++#define PCI_SOFTWARE_RESET	(1U << 31)	/* Software reset of the PCI Core. */
++
++
++/* PCI Core ISR Register bit definitions */
++#define PCI_INT_PROP_ST		(1 << 0)	/* Interrupt Propagation Status */
++#define PCI_WB_ERR_INT_ST	(1 << 1)	/* Wishbone Error Interrupt Status */
++#define PCI_PCI_ERR_INT_ST	(1 << 2)	/* PCI Error Interrupt Status */
++#define PCI_PAR_ERR_INT_ST	(1 << 3)	/* Parity Error Interrupt Status */
++#define PCI_SYS_ERR_INT_ST	(1 << 4)	/* System Error Interrupt Status */
++
++
++/* Registers on the Wishbone bus */
++#define SPIH_CTLR_INTR		(1 << 0)	/* SPI Host Controller Core Interrupt */
++#define SPIH_DEV_INTR		(1 << 1)	/* SPI Device Interrupt */
++#define SPIH_WFIFO_INTR		(1 << 2)	/* SPI Tx FIFO Empty Intr (FPGA Rev >= 8) */
++
++/* GPIO Bit definitions */
++#define SPIH_CS			(1 << 0)	/* SPI Chip Select (active low) */
++#define SPIH_SLOT_POWER		(1 << 1)	/* SD Card Slot Power Enable */
++#define SPIH_CARD_DETECT	(1 << 2)	/* SD Card Detect */
++
++/* SPI Status Register Bit definitions */
++#define SPIH_STATE_MASK		0x30		/* SPI Transfer State Machine state mask */
++#define SPIH_STATE_SHIFT	4		/* SPI Transfer State Machine state shift */
++#define SPIH_WFFULL		(1 << 3)	/* SPI Write FIFO Full */
++#define SPIH_WFEMPTY		(1 << 2)	/* SPI Write FIFO Empty */
++#define SPIH_RFFULL		(1 << 1)	/* SPI Read FIFO Full */
++#define SPIH_RFEMPTY		(1 << 0)	/* SPI Read FIFO Empty */
++
++#define SPIH_EXT_CLK		(1U << 31)	/* Use External Clock as PLL Clock source. */
++
++#define SPIH_PLL_NO_CLK		(1 << 1)	/* Set to 1 if the PLL's input clock is lost. */
++#define SPIH_PLL_LOCKED		(1 << 3)	/* Set to 1 when the PLL is locked. */
++
++/* Spin bit loop bound check */
++#define SPI_SPIN_BOUND		0xf4240		/* 1 million */
++
++#endif /* _BCM_PCI_SPI_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmperf.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmperf.h
+new file mode 100644
+index 000000000..09e607fc9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmperf.h
+@@ -0,0 +1,39 @@
++/*
++ * Performance counters software interface.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmperf.h 514727 2014-11-12 03:02:48Z $
++ */
++/* essai */
++#ifndef _BCMPERF_H_
++#define _BCMPERF_H_
++/* get cache hits and misses */
++#define BCMPERF_ENABLE_INSTRCOUNT()
++#define BCMPERF_ENABLE_ICACHE_MISS()
++#define BCMPERF_ENABLE_ICACHE_HIT()
++#define	BCMPERF_GETICACHE_MISS(x)	((x) = 0)
++#define	BCMPERF_GETICACHE_HIT(x)	((x) = 0)
++#define	BCMPERF_GETINSTRCOUNT(x)	((x) = 0)
++#endif /* _BCMPERF_H_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdbus.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdbus.h
+new file mode 100644
+index 000000000..da835e88a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdbus.h
+@@ -0,0 +1,173 @@
++/*
++ * Definitions for API from sdio common code (bcmsdh) to individual
++ * host controller drivers.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmsdbus.h 644725 2016-06-21 12:26:04Z $
++ */
++
++#ifndef	_sdio_api_h_
++#define	_sdio_api_h_
++
++#if defined(BT_OVER_SDIO)
++#include <linux/mmc/sdio_func.h>
++#endif /* defined (BT_OVER_SDIO) */
++
++
++#define SDIOH_API_RC_SUCCESS                          (0x00)
++#define SDIOH_API_RC_FAIL	                      (0x01)
++#define SDIOH_API_SUCCESS(status) (status == 0)
++
++#define SDIOH_READ              0	/* Read request */
++#define SDIOH_WRITE             1	/* Write request */
++
++#define SDIOH_DATA_FIX          0	/* Fixed addressing */
++#define SDIOH_DATA_INC          1	/* Incremental addressing */
++
++#define SDIOH_CMD_TYPE_NORMAL   0       /* Normal command */
++#define SDIOH_CMD_TYPE_APPEND   1       /* Append command */
++#define SDIOH_CMD_TYPE_CUTTHRU  2       /* Cut-through command */
++
++#define SDIOH_DATA_PIO          0       /* PIO mode */
++#define SDIOH_DATA_DMA          1       /* DMA mode */
++
++/* Max number of glommed pkts */
++#ifdef CUSTOM_MAX_TXGLOM_SIZE
++#define SDPCM_MAXGLOM_SIZE  CUSTOM_MAX_TXGLOM_SIZE
++#else
++#define SDPCM_MAXGLOM_SIZE	36
++#endif /* CUSTOM_MAX_TXGLOM_SIZE */
++
++#define SDPCM_TXGLOM_CPY 0			/* SDIO 2.0 should use copy mode */
++#define SDPCM_TXGLOM_MDESC	1		/* SDIO 3.0 should use multi-desc mode */
++
++#ifdef CUSTOM_DEF_TXGLOM_SIZE
++#define SDPCM_DEFGLOM_SIZE  CUSTOM_DEF_TXGLOM_SIZE
++#else
++#define SDPCM_DEFGLOM_SIZE SDPCM_MAXGLOM_SIZE
++#endif /* CUSTOM_DEF_TXGLOM_SIZE */
++
++#if SDPCM_DEFGLOM_SIZE > SDPCM_MAXGLOM_SIZE
++#warning "SDPCM_DEFGLOM_SIZE cannot be higher than SDPCM_MAXGLOM_SIZE!!"
++#undef SDPCM_DEFGLOM_SIZE
++#define SDPCM_DEFGLOM_SIZE SDPCM_MAXGLOM_SIZE
++#endif
++
++#ifdef PKT_STATICS
++typedef struct pkt_statics {
++	uint16	event_count;
++	uint32	event_size;
++	uint16	ctrl_count;
++	uint32	ctrl_size;
++	uint32	data_count;
++	uint32	data_size;
++	uint32	glom_cnt[SDPCM_MAXGLOM_SIZE];
++	uint16	glom_max;
++	uint16	glom_count;
++	uint32	glom_size;
++	uint16	test_count;
++	uint32	test_size;
++} pkt_statics_t;
++#endif
++
++typedef int SDIOH_API_RC;
++
++/* SDio Host structure */
++typedef struct sdioh_info sdioh_info_t;
++
++/* callback function, taking one arg */
++typedef void (*sdioh_cb_fn_t)(void *);
++#if defined(BT_OVER_SDIO)
++extern
++void sdioh_sdmmc_card_enable_func_f3(sdioh_info_t *sd, struct sdio_func *func);
++#endif /* defined (BT_OVER_SDIO) */
++
++extern SDIOH_API_RC sdioh_interrupt_register(sdioh_info_t *si, sdioh_cb_fn_t fn, void *argh);
++extern SDIOH_API_RC sdioh_interrupt_deregister(sdioh_info_t *si);
++
++/* query whether SD interrupt is enabled or not */
++extern SDIOH_API_RC sdioh_interrupt_query(sdioh_info_t *si, bool *onoff);
++
++/* enable or disable SD interrupt */
++extern SDIOH_API_RC sdioh_interrupt_set(sdioh_info_t *si, bool enable_disable);
++
++#if defined(DHD_DEBUG)
++extern bool sdioh_interrupt_pending(sdioh_info_t *si);
++#endif
++
++/* read or write one byte using cmd52 */
++extern SDIOH_API_RC sdioh_request_byte(sdioh_info_t *si, uint rw, uint fnc, uint addr, uint8 *byte);
++
++/* read or write 2/4 bytes using cmd53 */
++extern SDIOH_API_RC sdioh_request_word(sdioh_info_t *si, uint cmd_type, uint rw, uint fnc,
++	uint addr, uint32 *word, uint nbyte);
++
++/* read or write any buffer using cmd53 */
++extern SDIOH_API_RC sdioh_request_buffer(sdioh_info_t *si, uint pio_dma, uint fix_inc,
++	uint rw, uint fnc_num, uint32 addr, uint regwidth, uint32 buflen, uint8 *buffer,
++	void *pkt);
++
++/* get cis data */
++extern SDIOH_API_RC sdioh_cis_read(sdioh_info_t *si, uint fuc, uint8 *cis, uint32 length);
++extern SDIOH_API_RC sdioh_cisaddr_read(sdioh_info_t *sd, uint func, uint8 *cisd, uint32 offset);
++
++extern SDIOH_API_RC sdioh_cfg_read(sdioh_info_t *si, uint fuc, uint32 addr, uint8 *data);
++extern SDIOH_API_RC sdioh_cfg_write(sdioh_info_t *si, uint fuc, uint32 addr, uint8 *data);
++
++/* query number of io functions */
++extern uint sdioh_query_iofnum(sdioh_info_t *si);
++
++/* handle iovars */
++extern int sdioh_iovar_op(sdioh_info_t *si, const char *name,
++                          void *params, int plen, void *arg, int len, bool set);
++
++/* Issue abort to the specified function and clear controller as needed */
++extern int sdioh_abort(sdioh_info_t *si, uint fnc);
++
++/* Start and Stop SDIO without re-enumerating the SD card. */
++extern int sdioh_start(sdioh_info_t *si, int stage);
++extern int sdioh_stop(sdioh_info_t *si);
++
++/* Wait system lock free */
++extern int sdioh_waitlockfree(sdioh_info_t *si);
++
++/* Reset and re-initialize the device */
++extern int sdioh_sdio_reset(sdioh_info_t *si);
++
++
++
++#if defined(BCMSDIOH_STD)
++	#define SDIOH_SLEEP_ENABLED
++#endif
++extern SDIOH_API_RC sdioh_sleep(sdioh_info_t *si, bool enab);
++
++/* GPIO support */
++extern SDIOH_API_RC sdioh_gpio_init(sdioh_info_t *sd);
++extern bool sdioh_gpioin(sdioh_info_t *sd, uint32 gpio);
++extern SDIOH_API_RC sdioh_gpioouten(sdioh_info_t *sd, uint32 gpio);
++extern SDIOH_API_RC sdioh_gpioout(sdioh_info_t *sd, uint32 gpio, bool enab);
++extern uint sdioh_set_mode(sdioh_info_t *sd, uint mode);
++
++#endif /* _sdio_api_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdh.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdh.h
+new file mode 100644
+index 000000000..7262d0f53
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdh.h
+@@ -0,0 +1,273 @@
++/*
++ * SDIO host client driver interface of Broadcom HNBU
++ *     export functions to client drivers
++ *     abstract OS and BUS specific details of SDIO
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmsdh.h 698895 2017-05-11 02:55:17Z $
++ */
++
++/**
++ * @file bcmsdh.h
++ */
++
++#ifndef	_bcmsdh_h_
++#define	_bcmsdh_h_
++
++#define BCMSDH_ERROR_VAL	0x0001 /* Error */
++#define BCMSDH_INFO_VAL		0x0002 /* Info */
++extern const uint bcmsdh_msglevel;
++
++#define BCMSDH_ERROR(x) printf x
++#define BCMSDH_INFO(x)
++
++#if defined(BCMSDIO) && (defined(BCMSDIOH_STD) || defined(BCMSDIOH_BCM) || \
++	defined(BCMSDIOH_SPI))
++#define BCMSDH_ADAPTER
++#endif /* BCMSDIO && (BCMSDIOH_STD || BCMSDIOH_BCM || BCMSDIOH_SPI) */
++
++/* forward declarations */
++typedef struct bcmsdh_info bcmsdh_info_t;
++typedef void (*bcmsdh_cb_fn_t)(void *);
++
++
++#if defined(BT_OVER_SDIO)
++typedef enum {
++	NO_HANG_STATE		= 0,
++	HANG_START_STATE		= 1,
++	HANG_RECOVERY_STATE	= 2
++} dhd_hang_state_t;
++#endif
++
++extern bcmsdh_info_t *bcmsdh_attach(osl_t *osh, void *sdioh, ulong *regsva);
++/**
++ * BCMSDH API context
++ */
++struct bcmsdh_info
++{
++	bool	init_success;	/* underlying driver successfully attached */
++	void	*sdioh;		/* handler for sdioh */
++	uint32  vendevid;	/* Target Vendor and Device ID on SD bus */
++	osl_t   *osh;
++	bool	regfail;	/* Save status of last reg_read/reg_write call */
++	uint32	sbwad;		/* Save backplane window address */
++	void	*os_cxt;        /* Pointer to per-OS private data */
++	bool	force_sbwad_calc; /* forces calculation of sbwad instead of using cached value */
++#ifdef DHD_WAKE_STATUS
++	unsigned int	total_wake_count;
++	int		pkt_wake;
++#endif /* DHD_WAKE_STATUS */
++};
++
++/* Detach - freeup resources allocated in attach */
++extern int bcmsdh_detach(osl_t *osh, void *sdh);
++
++/* Query if SD device interrupts are enabled */
++extern bool bcmsdh_intr_query(void *sdh);
++
++/* Enable/disable SD interrupt */
++extern int bcmsdh_intr_enable(void *sdh);
++extern int bcmsdh_intr_disable(void *sdh);
++
++/* Register/deregister device interrupt handler. */
++extern int bcmsdh_intr_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh);
++extern int bcmsdh_intr_dereg(void *sdh);
++/* Enable/disable SD card interrupt forward */
++extern void bcmsdh_intr_forward(void *sdh, bool pass);
++
++#if defined(DHD_DEBUG)
++/* Query pending interrupt status from the host controller */
++extern bool bcmsdh_intr_pending(void *sdh);
++#endif
++
++/* Register a callback to be called if and when bcmsdh detects
++ * device removal. No-op in the case of non-removable/hardwired devices.
++ */
++extern int bcmsdh_devremove_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh);
++
++/* Access SDIO address space (e.g. CCCR) using CMD52 (single-byte interface).
++ *   fn:   function number
++ *   addr: unmodified SDIO-space address
++ *   data: data byte to write
++ *   err:  pointer to error code (or NULL)
++ */
++extern uint8 bcmsdh_cfg_read(void *sdh, uint func, uint32 addr, int *err);
++extern void bcmsdh_cfg_write(void *sdh, uint func, uint32 addr, uint8 data, int *err);
++
++/* Read/Write 4bytes from/to cfg space */
++extern uint32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr, int *err);
++extern void bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr, uint32 data, int *err);
++
++/* Read CIS content for specified function.
++ *   fn:     function whose CIS is being requested (0 is common CIS)
++ *   cis:    pointer to memory location to place results
++ *   length: number of bytes to read
++ * Internally, this routine uses the values from the cis base regs (0x9-0xB)
++ * to form an SDIO-space address to read the data from.
++ */
++extern int bcmsdh_cis_read(void *sdh, uint func, uint8 *cis, uint length);
++extern int bcmsdh_cisaddr_read(void *sdh, uint func, uint8 *cisd, uint offset);
++
++/* Synchronous access to device (client) core registers via CMD53 to F1.
++ *   addr: backplane address (i.e. >= regsva from attach)
++ *   size: register width in bytes (2 or 4)
++ *   data: data for register write
++ */
++extern uint32 bcmsdh_reg_read(void *sdh, uintptr addr, uint size);
++extern uint32 bcmsdh_reg_write(void *sdh, uintptr addr, uint size, uint32 data);
++
++/* set sb address window */
++extern int bcmsdhsdio_set_sbaddr_window(void *sdh, uint32 address, bool force_set);
++
++/* Indicate if last reg read/write failed */
++extern bool bcmsdh_regfail(void *sdh);
++
++/* Buffer transfer to/from device (client) core via cmd53.
++ *   fn:       function number
++ *   addr:     backplane address (i.e. >= regsva from attach)
++ *   flags:    backplane width, address increment, sync/async
++ *   buf:      pointer to memory data buffer
++ *   nbytes:   number of bytes to transfer to/from buf
++ *   pkt:      pointer to packet associated with buf (if any)
++ *   complete: callback function for command completion (async only)
++ *   handle:   handle for completion callback (first arg in callback)
++ * Returns 0 or error code.
++ * NOTE: Async operation is not currently supported.
++ */
++typedef void (*bcmsdh_cmplt_fn_t)(void *handle, int status, bool sync_waiting);
++extern int bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags,
++                           uint8 *buf, uint nbytes, void *pkt,
++                           bcmsdh_cmplt_fn_t complete_fn, void *handle);
++extern int bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags,
++                           uint8 *buf, uint nbytes, void *pkt,
++                           bcmsdh_cmplt_fn_t complete_fn, void *handle);
++
++extern void bcmsdh_glom_post(void *sdh, uint8 *frame, void *pkt, uint len);
++extern void bcmsdh_glom_clear(void *sdh);
++extern uint bcmsdh_set_mode(void *sdh, uint mode);
++extern bool bcmsdh_glom_enabled(void);
++/* Flags bits */
++#define SDIO_REQ_4BYTE	0x1	/* Four-byte target (backplane) width (vs. two-byte) */
++#define SDIO_REQ_FIXED	0x2	/* Fixed address (FIFO) (vs. incrementing address) */
++#define SDIO_REQ_ASYNC	0x4	/* Async request (vs. sync request) */
++#define SDIO_BYTE_MODE	0x8	/* Byte mode request(non-block mode) */
++
++/* Pending (non-error) return code */
++#define BCME_PENDING	1
++
++/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
++ *   rw:       read or write (0/1)
++ *   addr:     direct SDIO address
++ *   buf:      pointer to memory data buffer
++ *   nbytes:   number of bytes to transfer to/from buf
++ * Returns 0 or error code.
++ */
++extern int bcmsdh_rwdata(void *sdh, uint rw, uint32 addr, uint8 *buf, uint nbytes);
++
++/* Issue an abort to the specified function */
++extern int bcmsdh_abort(void *sdh, uint fn);
++
++/* Start SDIO Host Controller communication */
++extern int bcmsdh_start(void *sdh, int stage);
++
++/* Stop SDIO Host Controller communication */
++extern int bcmsdh_stop(void *sdh);
++
++/* Wait system lock free */
++extern int bcmsdh_waitlockfree(void *sdh);
++
++/* Returns the "Device ID" of target device on the SDIO bus. */
++extern int bcmsdh_query_device(void *sdh);
++
++/* Returns the number of IO functions reported by the device */
++extern uint bcmsdh_query_iofnum(void *sdh);
++
++/* Miscellaneous knob tweaker. */
++extern int bcmsdh_iovar_op(void *sdh, const char *name,
++                           void *params, int plen, void *arg, int len, bool set);
++
++/* Reset and reinitialize the device */
++extern int bcmsdh_reset(bcmsdh_info_t *sdh);
++
++/* helper functions */
++
++/* callback functions */
++typedef struct {
++	/* probe the device */
++	void *(*probe)(uint16 vend_id, uint16 dev_id, uint16 bus, uint16 slot,
++	                uint16 func, uint bustype, void * regsva, osl_t * osh,
++	                void * param);
++	/* remove the device */
++	void (*remove)(void *context);
++	/* can we suspend now */
++	int (*suspend)(void *context);
++	/* resume from suspend */
++	int (*resume)(void *context);
++} bcmsdh_driver_t;
++
++/* platform specific/high level functions */
++extern int bcmsdh_register(bcmsdh_driver_t *driver);
++extern void bcmsdh_unregister(void);
++extern bool bcmsdh_chipmatch(uint16 vendor, uint16 device);
++extern void bcmsdh_device_remove(void * sdh);
++
++extern int bcmsdh_reg_sdio_notify(void* semaphore);
++extern void bcmsdh_unreg_sdio_notify(void);
++
++#if defined(OOB_INTR_ONLY)
++extern int bcmsdh_oob_intr_register(bcmsdh_info_t *bcmsdh, bcmsdh_cb_fn_t oob_irq_handler,
++	void* oob_irq_handler_context);
++extern void bcmsdh_oob_intr_unregister(bcmsdh_info_t *sdh);
++extern void bcmsdh_oob_intr_set(bcmsdh_info_t *sdh, bool enable);
++#endif 
++extern void bcmsdh_dev_pm_stay_awake(bcmsdh_info_t *sdh);
++extern void bcmsdh_dev_relax(bcmsdh_info_t *sdh);
++extern bool bcmsdh_dev_pm_enabled(bcmsdh_info_t *sdh);
++
++int bcmsdh_suspend(bcmsdh_info_t *bcmsdh);
++int bcmsdh_resume(bcmsdh_info_t *bcmsdh);
++
++/* Function to pass device-status bits to DHD. */
++extern uint32 bcmsdh_get_dstatus(void *sdh);
++
++/* Function to return current window addr */
++extern uint32 bcmsdh_cur_sbwad(void *sdh);
++
++/* function to force sbwad calculation instead of using cached value */
++extern void bcmsdh_force_sbwad_calc(void *sdh, bool force);
++
++/* Function to pass chipid and rev to lower layers for controlling pr's */
++extern void bcmsdh_chipinfo(void *sdh, uint32 chip, uint32 chiprev);
++
++
++extern int bcmsdh_sleep(void *sdh, bool enab);
++
++/* GPIO support */
++extern int bcmsdh_gpio_init(void *sd);
++extern bool bcmsdh_gpioin(void *sd, uint32 gpio);
++extern int bcmsdh_gpioouten(void *sd, uint32 gpio);
++extern int bcmsdh_gpioout(void *sd, uint32 gpio, bool enab);
++
++#endif	/* _bcmsdh_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdh_sdmmc.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdh_sdmmc.h
+new file mode 100644
+index 000000000..1073d97c6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdh_sdmmc.h
+@@ -0,0 +1,129 @@
++/*
++ * BCMSDH Function Driver for the native SDIO/MMC driver in the Linux Kernel
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Proprietary,Open:>>
++ *
++ * $Id: bcmsdh_sdmmc.h 687253 2017-02-28 09:33:36Z $
++ */
++
++#ifndef __BCMSDH_SDMMC_H__
++#define __BCMSDH_SDMMC_H__
++
++#define sd_err(x)	do { if (sd_msglevel & SDH_ERROR_VAL) printf x; } while (0)
++#define sd_trace(x)	do { if (sd_msglevel & SDH_TRACE_VAL) printf x; } while (0)
++#define sd_info(x)	do { if (sd_msglevel & SDH_INFO_VAL) printf x; } while (0)
++#define sd_debug(x)	do { if (sd_msglevel & SDH_DEBUG_VAL) printf x; } while (0)
++#define sd_data(x)	do { if (sd_msglevel & SDH_DATA_VAL) printf x; } while (0)
++#define sd_ctrl(x)	do { if (sd_msglevel & SDH_CTRL_VAL) printf x; } while (0)
++#define sd_cost(x)	do { if (sd_msglevel & SDH_COST_VAL) printf x; } while (0)
++
++#define sd_sync_dma(sd, read, nbytes)
++#define sd_init_dma(sd)
++#define sd_ack_intr(sd)
++#define sd_wakeup(sd);
++
++#define sd_log(x)
++
++#define SDIOH_ASSERT(exp) \
++	do { if (!(exp)) \
++		printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \
++	} while (0)
++
++#define BLOCK_SIZE_4318 64
++#define BLOCK_SIZE_4328 512
++
++/* internal return code */
++#define SUCCESS	0
++#define ERROR	1
++
++/* private bus modes */
++#define SDIOH_MODE_SD4		2
++#define CLIENT_INTR			0x100	/* Get rid of this! */
++#define SDIOH_SDMMC_MAX_SG_ENTRIES	(SDPCM_MAXGLOM_SIZE + 2)
++
++struct sdioh_info {
++	osl_t		*osh;			/* osh handler */
++	void		*bcmsdh;		/* upper layer handle */
++	bool		client_intr_enabled;	/* interrupt connnected flag */
++	bool		intr_handler_valid;	/* client driver interrupt handler valid */
++	sdioh_cb_fn_t	intr_handler;		/* registered interrupt handler */
++	void		*intr_handler_arg;	/* argument to call interrupt handler */
++	uint16		intmask;		/* Current active interrupts */
++
++	int		intrcount;		/* Client interrupts */
++	bool		sd_use_dma;		/* DMA on CMD53 */
++	bool		sd_blockmode;		/* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
++						/*  Must be on for sd_multiblock to be effective */
++	bool		use_client_ints;	/* If this is false, make sure to restore */
++	int		sd_mode;		/* SD1/SD4/SPI */
++	int		client_block_size[SDIOD_MAX_IOFUNCS];		/* Blocksize */
++	uint8		num_funcs;		/* Supported funcs on client */
++	uint32		com_cis_ptr;
++	uint32		func_cis_ptr[SDIOD_MAX_IOFUNCS];
++	bool		use_rxchain;
++	struct scatterlist	sg_list[SDIOH_SDMMC_MAX_SG_ENTRIES];
++	struct sdio_func	fake_func0;
++	struct sdio_func	*func[SDIOD_MAX_IOFUNCS];
++	uint		sd_clk_rate;
++	uint	txglom_mode;		/* Txglom mode: 0 - copy, 1 - multi-descriptor */
++};
++
++/************************************************************
++ * Internal interfaces: per-port references into bcmsdh_sdmmc.c
++ */
++
++/* Global message bits */
++extern uint sd_msglevel;
++
++/* OS-independent interrupt handler */
++extern bool check_client_intr(sdioh_info_t *sd);
++
++/* Core interrupt enable/disable of device interrupts */
++extern void sdioh_sdmmc_devintr_on(sdioh_info_t *sd);
++extern void sdioh_sdmmc_devintr_off(sdioh_info_t *sd);
++
++
++/**************************************************************
++ * Internal interfaces: bcmsdh_sdmmc.c references to per-port code
++ */
++
++/* Register mapping routines */
++extern uint32 *sdioh_sdmmc_reg_map(osl_t *osh, int32 addr, int size);
++extern void sdioh_sdmmc_reg_unmap(osl_t *osh, int32 addr, int size);
++
++/* Interrupt (de)registration routines */
++extern int sdioh_sdmmc_register_irq(sdioh_info_t *sd, uint irq);
++extern void sdioh_sdmmc_free_irq(uint irq, sdioh_info_t *sd);
++
++extern sdioh_info_t *sdioh_attach(osl_t *osh, struct sdio_func *func);
++extern SDIOH_API_RC sdioh_detach(osl_t *osh, sdioh_info_t *sd);
++
++#ifdef GLOBAL_SDMMC_INSTANCE
++typedef struct _BCMSDH_SDMMC_INSTANCE {
++	sdioh_info_t	*sd;
++	struct sdio_func *func[SDIOD_MAX_IOFUNCS];
++} BCMSDH_SDMMC_INSTANCE, *PBCMSDH_SDMMC_INSTANCE;
++#endif
++
++#endif /* __BCMSDH_SDMMC_H__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdpcm.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdpcm.h
+new file mode 100644
+index 000000000..5b9c51b3a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdpcm.h
+@@ -0,0 +1,302 @@
++/*
++ * Broadcom SDIO/PCMCIA
++ * Software-specific definitions shared between device and host side
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmsdpcm.h 614070 2016-01-21 00:55:57Z $
++ */
++
++#ifndef	_bcmsdpcm_h_
++#define	_bcmsdpcm_h_
++
++/*
++ * Software allocation of To SB Mailbox resources
++ */
++
++/* intstatus bits */
++#define I_SMB_NAK	I_SMB_SW0	/* To SB Mailbox Frame NAK */
++#define I_SMB_INT_ACK	I_SMB_SW1	/* To SB Mailbox Host Interrupt ACK */
++#define I_SMB_USE_OOB	I_SMB_SW2	/* To SB Mailbox Use OOB Wakeup */
++#define I_SMB_DEV_INT	I_SMB_SW3	/* To SB Mailbox Miscellaneous Interrupt */
++
++#define I_TOSBMAIL      (I_SMB_NAK | I_SMB_INT_ACK | I_SMB_USE_OOB | I_SMB_DEV_INT)
++
++/* tosbmailbox bits corresponding to intstatus bits */
++#define SMB_NAK		(1 << 0)	/* To SB Mailbox Frame NAK */
++#define SMB_INT_ACK	(1 << 1)	/* To SB Mailbox Host Interrupt ACK */
++#define SMB_USE_OOB	(1 << 2)	/* To SB Mailbox Use OOB Wakeup */
++#define SMB_DEV_INT	(1 << 3)	/* To SB Mailbox Miscellaneous Interrupt */
++#define SMB_MASK	0x0000000f	/* To SB Mailbox Mask */
++
++/* tosbmailboxdata */
++
++#ifdef DS_PROT
++/* Bit msgs for custom deep sleep protocol */
++#define SMB_DATA_D3INFORM	0x100	/* host announcing D3 entry */
++#define SMB_DATA_DSACK		0x200	/* host acking a deepsleep request */
++#define SMB_DATA_DSNACK		0x400	/* host nacking a deepsleep request */
++#endif /* DS_PROT */
++
++#define SMB_DATA_VERSION_MASK	0x00ff0000	/* host protocol version (sent with F2 enable) */
++#define SMB_DATA_VERSION_SHIFT	16		/* host protocol version (sent with F2 enable) */
++
++/*
++ * Software allocation of To Host Mailbox resources
++ */
++
++/* intstatus bits */
++#define I_HMB_INT_ACK	I_HMB_SW0	/* To Host Mailbox Dev Interrupt ACK */
++#define I_HMB_FC_STATE	I_HMB_SW0	/* To Host Mailbox Flow Control State */
++#define I_HMB_FC_CHANGE	I_HMB_SW1	/* To Host Mailbox Flow Control State Changed */
++#define I_HMB_FRAME_IND	I_HMB_SW2	/* To Host Mailbox Frame Indication */
++#define I_HMB_HOST_INT	I_HMB_SW3	/* To Host Mailbox Miscellaneous Interrupt */
++
++#define I_TOHOSTMAIL    (I_HMB_INT_ACK | I_HMB_FRAME_IND | I_HMB_HOST_INT)
++
++/* tohostmailbox bits corresponding to intstatus bits */
++#define HMB_INT_ACK	(1 << 0)	/* To Host Mailbox Dev Interrupt ACK */
++#define HMB_FRAME_IND	(1 << 2)	/* To Host Mailbox Frame Indication */
++#define HMB_HOST_INT	(1 << 3)	/* To Host Mailbox Miscellaneous Interrupt */
++#define HMB_MASK	0x0000000f	/* To Host Mailbox Mask */
++
++/* tohostmailboxdata */
++#define HMB_DATA_NAKHANDLED	0x01	/* we're ready to retransmit NAK'd frame to host */
++#define HMB_DATA_DEVREADY	0x02	/* we're ready to to talk to host after enable */
++#define HMB_DATA_FC		0x04	/* per prio flowcontrol update flag to host */
++#define HMB_DATA_FWREADY	0x08	/* firmware is ready for protocol activity */
++#define HMB_DATA_FWHALT		0x10	/* firmware has halted operation */
++
++#ifdef DS_PROT
++/* Bit msgs for custom deep sleep protocol */
++#define HMB_DATA_DSREQ		0x100	/* firmware requesting deepsleep entry */
++#define HMB_DATA_DSEXIT		0x200	/* firmware announcing deepsleep exit */
++#define HMB_DATA_D3ACK		0x400	/* firmware acking a D3 notice from host */
++#define HMB_DATA_D3EXIT		0x800	/* firmware announcing D3 exit */
++#define HMB_DATA_DSPROT_MASK	0xf00
++#endif /* DS_PROT */
++
++
++#define HMB_DATA_FCDATA_MASK	0xff000000	/* per prio flowcontrol data */
++#define HMB_DATA_FCDATA_SHIFT	24		/* per prio flowcontrol data */
++
++#define HMB_DATA_VERSION_MASK	0x00ff0000	/* device protocol version (with devready) */
++#define HMB_DATA_VERSION_SHIFT	16		/* device protocol version (with devready) */
++
++/*
++ * Software-defined protocol header
++ */
++
++/* Current protocol version */
++#define SDPCM_PROT_VERSION	4
++
++/* SW frame header */
++#define SDPCM_SEQUENCE_MASK		0x000000ff	/* Sequence Number Mask */
++#define SDPCM_PACKET_SEQUENCE(p) (((uint8 *)p)[0] & 0xff) /* p starts w/SW Header */
++
++#define SDPCM_CHANNEL_MASK		0x00000f00	/* Channel Number Mask */
++#define SDPCM_CHANNEL_SHIFT		8		/* Channel Number Shift */
++#define SDPCM_PACKET_CHANNEL(p) (((uint8 *)p)[1] & 0x0f) /* p starts w/SW Header */
++
++#define SDPCM_FLAGS_MASK		0x0000f000	/* Mask of flag bits */
++#define SDPCM_FLAGS_SHIFT		12		/* Flag bits shift */
++#define SDPCM_PACKET_FLAGS(p) ((((uint8 *)p)[1] & 0xf0) >> 4) /* p starts w/SW Header */
++
++/* Next Read Len: lookahead length of next frame, in 16-byte units (rounded up) */
++#define SDPCM_NEXTLEN_MASK		0x00ff0000	/* Next Read Len Mask */
++#define SDPCM_NEXTLEN_SHIFT		16		/* Next Read Len Shift */
++#define SDPCM_NEXTLEN_VALUE(p) ((((uint8 *)p)[2] & 0xff) << 4) /* p starts w/SW Header */
++#define SDPCM_NEXTLEN_OFFSET		2
++
++/* Data Offset from SOF (HW Tag, SW Tag, Pad) */
++#define SDPCM_DOFFSET_OFFSET		3		/* Data Offset */
++#define SDPCM_DOFFSET_VALUE(p) 		(((uint8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
++#define SDPCM_DOFFSET_MASK		0xff000000
++#define SDPCM_DOFFSET_SHIFT		24
++
++#define SDPCM_FCMASK_OFFSET		4		/* Flow control */
++#define SDPCM_FCMASK_VALUE(p)		(((uint8 *)p)[SDPCM_FCMASK_OFFSET ] & 0xff)
++#define SDPCM_WINDOW_OFFSET		5		/* Credit based fc */
++#define SDPCM_WINDOW_VALUE(p)		(((uint8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
++#define SDPCM_VERSION_OFFSET		6		/* Version # */
++#define SDPCM_VERSION_VALUE(p)		(((uint8 *)p)[SDPCM_VERSION_OFFSET] & 0xff)
++#define SDPCM_UNUSED_OFFSET		7		/* Spare */
++#define SDPCM_UNUSED_VALUE(p)		(((uint8 *)p)[SDPCM_UNUSED_OFFSET] & 0xff)
++
++#define SDPCM_SWHEADER_LEN	8	/* SW header is 64 bits */
++
++/* logical channel numbers */
++#define SDPCM_CONTROL_CHANNEL	0	/* Control Request/Response Channel Id */
++#define SDPCM_EVENT_CHANNEL	1	/* Asyc Event Indication Channel Id */
++#define SDPCM_DATA_CHANNEL	2	/* Data Xmit/Recv Channel Id */
++#define SDPCM_GLOM_CHANNEL	3	/* For coalesced packets (superframes) */
++#define SDPCM_TEST_CHANNEL	15	/* Reserved for test/debug packets */
++#define SDPCM_MAX_CHANNEL	15
++
++#define SDPCM_SEQUENCE_WRAP	256	/* wrap-around val for eight-bit frame seq number */
++
++#define SDPCM_FLAG_RESVD0	0x01
++#define SDPCM_FLAG_RESVD1	0x02
++#define SDPCM_FLAG_GSPI_TXENAB	0x04
++#define SDPCM_FLAG_GLOMDESC	0x08	/* Superframe descriptor mask */
++
++/* For GLOM_CHANNEL frames, use a flag to indicate descriptor frame */
++#define SDPCM_GLOMDESC_FLAG	(SDPCM_FLAG_GLOMDESC << SDPCM_FLAGS_SHIFT)
++
++#define SDPCM_GLOMDESC(p)	(((uint8 *)p)[1] & 0x80)
++
++/* For TEST_CHANNEL packets, define another 4-byte header */
++#define SDPCM_TEST_HDRLEN		4	/* Generally: Cmd(1), Ext(1), Len(2);
++						 * Semantics of Ext byte depend on command.
++						 * Len is current or requested frame length, not
++						 * including test header; sent little-endian.
++						 */
++#define SDPCM_TEST_PKT_CNT_FLD_LEN	4	/* Packet count filed legth */
++#define SDPCM_TEST_DISCARD		0x01	/* Receiver discards. Ext is a pattern id. */
++#define SDPCM_TEST_ECHOREQ		0x02	/* Echo request. Ext is a pattern id. */
++#define SDPCM_TEST_ECHORSP		0x03	/* Echo response. Ext is a pattern id. */
++#define SDPCM_TEST_BURST		0x04	/* Receiver to send a burst. Ext is a frame count
++						 * (Backward compatabilty) Set frame count in a
++						 * 4 byte filed adjacent to the HDR
++						 */
++#define SDPCM_TEST_SEND			0x05	/* Receiver sets send mode. Ext is boolean on/off
++						 * Set frame count in a 4 byte filed adjacent to
++						 * the HDR
++						 */
++
++/* Handy macro for filling in datagen packets with a pattern */
++#define SDPCM_TEST_FILL(byteno, id)	((uint8)(id + byteno))
++
++/*
++ * Software counters (first part matches hardware counters)
++ */
++
++typedef volatile struct {
++	uint32 cmd52rd;		/* Cmd52RdCount, SDIO: cmd52 reads */
++	uint32 cmd52wr;		/* Cmd52WrCount, SDIO: cmd52 writes */
++	uint32 cmd53rd;		/* Cmd53RdCount, SDIO: cmd53 reads */
++	uint32 cmd53wr;		/* Cmd53WrCount, SDIO: cmd53 writes */
++	uint32 abort;		/* AbortCount, SDIO: aborts */
++	uint32 datacrcerror;	/* DataCrcErrorCount, SDIO: frames w/CRC error */
++	uint32 rdoutofsync;	/* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */
++	uint32 wroutofsync;	/* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */
++	uint32 writebusy;	/* WriteBusyCount, SDIO: device asserted "busy" */
++	uint32 readwait;	/* ReadWaitCount, SDIO: no data ready for a read cmd */
++	uint32 readterm;	/* ReadTermCount, SDIO: read frame termination cmds */
++	uint32 writeterm;	/* WriteTermCount, SDIO: write frames termination cmds */
++	uint32 rxdescuflo;	/* receive descriptor underflows */
++	uint32 rxfifooflo;	/* receive fifo overflows */
++	uint32 txfifouflo;	/* transmit fifo underflows */
++	uint32 runt;		/* runt (too short) frames recv'd from bus */
++	uint32 badlen;		/* frame's rxh len does not match its hw tag len */
++	uint32 badcksum;	/* frame's hw tag chksum doesn't agree with len value */
++	uint32 seqbreak;	/* break in sequence # space from one rx frame to the next */
++	uint32 rxfcrc;		/* frame rx header indicates crc error */
++	uint32 rxfwoos;		/* frame rx header indicates write out of sync */
++	uint32 rxfwft;		/* frame rx header indicates write frame termination */
++	uint32 rxfabort;	/* frame rx header indicates frame aborted */
++	uint32 woosint;		/* write out of sync interrupt */
++	uint32 roosint;		/* read out of sync interrupt */
++	uint32 rftermint;	/* read frame terminate interrupt */
++	uint32 wftermint;	/* write frame terminate interrupt */
++} sdpcmd_cnt_t;
++
++/*
++ * Register Access Macros
++ */
++
++#define SDIODREV_IS(var, val)	((var) == (val))
++#define SDIODREV_GE(var, val)	((var) >= (val))
++#define SDIODREV_GT(var, val)	((var) > (val))
++#define SDIODREV_LT(var, val)	((var) < (val))
++#define SDIODREV_LE(var, val)	((var) <= (val))
++
++#define SDIODDMAREG32(h, dir, chnl) \
++	((dir) == DMA_TX ? \
++	 (void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].xmt) : \
++	 (void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].rcv))
++
++#define SDIODDMAREG64(h, dir, chnl) \
++	((dir) == DMA_TX ? \
++	 (void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].xmt) : \
++	 (void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].rcv))
++
++#define SDIODDMAREG(h, dir, chnl) \
++	(SDIODREV_LT((h)->corerev, 1) ? \
++	 SDIODDMAREG32((h), (dir), (chnl)) : \
++	 SDIODDMAREG64((h), (dir), (chnl)))
++
++#define PCMDDMAREG(h, dir, chnl) \
++	((dir) == DMA_TX ? \
++	 (void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.xmt) : \
++	 (void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.rcv))
++
++#define SDPCMDMAREG(h, dir, chnl, coreid) \
++	((coreid) == SDIOD_CORE_ID ? \
++	 SDIODDMAREG(h, dir, chnl) : \
++	 PCMDDMAREG(h, dir, chnl))
++
++#define SDIODFIFOREG(h, corerev) \
++	(SDIODREV_LT((corerev), 1) ? \
++	 ((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod32.dmafifo)) : \
++	 ((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod64.dmafifo)))
++
++#define PCMDFIFOREG(h) \
++	((dma32diag_t *)(uintptr)&((h)->regs->dma.pcm32.dmafifo))
++
++#define SDPCMFIFOREG(h, coreid, corerev) \
++	((coreid) == SDIOD_CORE_ID ? \
++	 SDIODFIFOREG(h, corerev) : \
++	 PCMDFIFOREG(h))
++
++/*
++ * Shared structure between dongle and the host.
++ * The structure contains pointers to trap or assert information.
++ */
++#define SDPCM_SHARED_VERSION       0x0001
++#define SDPCM_SHARED_VERSION_MASK  0x00FF
++#define SDPCM_SHARED_ASSERT_BUILT  0x0100
++#define SDPCM_SHARED_ASSERT        0x0200
++#define SDPCM_SHARED_TRAP          0x0400
++#define SDPCM_SHARED_IN_BRPT       0x0800
++#define SDPCM_SHARED_SET_BRPT      0x1000
++#define SDPCM_SHARED_PENDING_BRPT  0x2000
++#define SDPCM_SHARED_FATAL_LOGBUF_VALID	0x100000
++#define SDPCM_SHARED_RXLIM_POST    0x4000
++
++typedef struct {
++	uint32	flags;
++	uint32  trap_addr;
++	uint32  assert_exp_addr;
++	uint32  assert_file_addr;
++	uint32  assert_line;
++	uint32	console_addr;		/* Address of hnd_cons_t */
++	uint32  msgtrace_addr;
++	uint32  fwid;
++	uint32  device_fatal_logbuf_start;
++} sdpcm_shared_t;
++
++extern sdpcm_shared_t sdpcm_shared;
++
++#endif	/* _bcmsdpcm_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdspi.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdspi.h
+new file mode 100644
+index 000000000..537876c36
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdspi.h
+@@ -0,0 +1,138 @@
++/*
++ * SD-SPI Protocol Conversion - BCMSDH->SPI Translation Layer
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmsdspi.h 514727 2014-11-12 03:02:48Z $
++ */
++#ifndef	_BCM_SD_SPI_H
++#define	_BCM_SD_SPI_H
++
++/* global msglevel for debug messages - bitvals come from sdiovar.h */
++
++#define sd_err(x)
++#define sd_trace(x)
++#define sd_info(x)
++#define sd_debug(x)
++#define sd_data(x)
++#define sd_ctrl(x)
++
++#define sd_log(x)
++
++#define SDIOH_ASSERT(exp) \
++	do { if (!(exp)) \
++		printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \
++	} while (0)
++
++#define BLOCK_SIZE_4318 64
++#define BLOCK_SIZE_4328 512
++
++/* internal return code */
++#define SUCCESS	0
++#undef ERROR
++#define ERROR	1
++
++/* private bus modes */
++#define SDIOH_MODE_SPI		0
++
++#define USE_BLOCKMODE		0x2	/* Block mode can be single block or multi */
++#define USE_MULTIBLOCK		0x4
++
++struct sdioh_info {
++	uint cfg_bar;                   	/* pci cfg address for bar */
++	uint32 caps;                    	/* cached value of capabilities reg */
++	uint		bar0;			/* BAR0 for PCI Device */
++	osl_t 		*osh;			/* osh handler */
++	void		*controller;	/* Pointer to SPI Controller's private data struct */
++
++	uint		lockcount; 		/* nest count of sdspi_lock() calls */
++	bool		client_intr_enabled;	/* interrupt connnected flag */
++	bool		intr_handler_valid;	/* client driver interrupt handler valid */
++	sdioh_cb_fn_t	intr_handler;		/* registered interrupt handler */
++	void		*intr_handler_arg;	/* argument to call interrupt handler */
++	bool		initialized;		/* card initialized */
++	uint32		target_dev;		/* Target device ID */
++	uint32		intmask;		/* Current active interrupts */
++	void		*sdos_info;		/* Pointer to per-OS private data */
++
++	uint32		controller_type;	/* Host controller type */
++	uint8		version;		/* Host Controller Spec Compliance Version */
++	uint 		irq;			/* Client irq */
++	uint32 		intrcount;		/* Client interrupts */
++	uint32 		local_intrcount;	/* Controller interrupts */
++	bool 		host_init_done;		/* Controller initted */
++	bool 		card_init_done;		/* Client SDIO interface initted */
++	bool 		polled_mode;		/* polling for command completion */
++
++	bool		sd_use_dma;		/* DMA on CMD53 */
++	bool 		sd_blockmode;		/* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
++						/*  Must be on for sd_multiblock to be effective */
++	bool 		use_client_ints;	/* If this is false, make sure to restore */
++	bool		got_hcint;		/* Host Controller interrupt. */
++						/*  polling hack in wl_linux.c:wl_timer() */
++	int 		adapter_slot;		/* Maybe dealing with multiple slots/controllers */
++	int 		sd_mode;		/* SD1/SD4/SPI */
++	int 		client_block_size[SDIOD_MAX_IOFUNCS];		/* Blocksize */
++	uint32 		data_xfer_count;	/* Current register transfer size */
++	uint32		cmd53_wr_data;		/* Used to pass CMD53 write data */
++	uint32		card_response;		/* Used to pass back response status byte */
++	uint32		card_rsp_data;		/* Used to pass back response data word */
++	uint16 		card_rca;		/* Current Address */
++	uint8 		num_funcs;		/* Supported funcs on client */
++	uint32 		com_cis_ptr;
++	uint32 		func_cis_ptr[SDIOD_MAX_IOFUNCS];
++	void		*dma_buf;
++	ulong		dma_phys;
++	int 		r_cnt;			/* rx count */
++	int 		t_cnt;			/* tx_count */
++};
++
++/************************************************************
++ * Internal interfaces: per-port references into bcmsdspi.c
++ */
++
++/* Global message bits */
++extern uint sd_msglevel;
++
++/**************************************************************
++ * Internal interfaces: bcmsdspi.c references to per-port code
++ */
++
++/* Register mapping routines */
++extern uint32 *spi_reg_map(osl_t *osh, uintptr addr, int size);
++extern void spi_reg_unmap(osl_t *osh, uintptr addr, int size);
++
++/* Interrupt (de)registration routines */
++extern int spi_register_irq(sdioh_info_t *sd, uint irq);
++extern void spi_free_irq(uint irq, sdioh_info_t *sd);
++
++/* OS-specific interrupt wrappers (atomic interrupt enable/disable) */
++extern void spi_lock(sdioh_info_t *sd);
++extern void spi_unlock(sdioh_info_t *sd);
++
++/* Allocate/init/free per-OS private data */
++extern int spi_osinit(sdioh_info_t *sd);
++extern void spi_osfree(sdioh_info_t *sd);
++
++#endif /* _BCM_SD_SPI_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdstd.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdstd.h
+new file mode 100644
+index 000000000..ff3b0d1f2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsdstd.h
+@@ -0,0 +1,285 @@
++/*
++ *  'Standard' SDIO HOST CONTROLLER driver
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmsdstd.h 514727 2014-11-12 03:02:48Z $
++ */
++#ifndef	_BCM_SD_STD_H
++#define	_BCM_SD_STD_H
++
++/* global msglevel for debug messages - bitvals come from sdiovar.h */
++#define sd_err(x)	do { if (sd_msglevel & SDH_ERROR_VAL) printf x; } while (0)
++#define sd_trace(x)
++#define sd_info(x)
++#define sd_debug(x)
++#define sd_data(x)
++#define sd_ctrl(x)
++#define sd_dma(x)
++
++#define sd_sync_dma(sd, read, nbytes)
++#define sd_init_dma(sd)
++#define sd_ack_intr(sd)
++#define sd_wakeup(sd);
++/* Allocate/init/free per-OS private data */
++extern int sdstd_osinit(sdioh_info_t *sd);
++extern void sdstd_osfree(sdioh_info_t *sd);
++
++#define sd_log(x)
++
++#define SDIOH_ASSERT(exp) \
++	do { if (!(exp)) \
++		printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \
++	} while (0)
++
++#define BLOCK_SIZE_4318 64
++#define BLOCK_SIZE_4328 512
++
++/* internal return code */
++#define SUCCESS	0
++#define ERROR	1
++
++/* private bus modes */
++#define SDIOH_MODE_SPI		0
++#define SDIOH_MODE_SD1		1
++#define SDIOH_MODE_SD4		2
++
++#define MAX_SLOTS 6 	/* For PCI: Only 6 BAR entries => 6 slots */
++#define SDIOH_REG_WINSZ	0x100 /* Number of registers in Standard Host Controller */
++
++#define SDIOH_TYPE_ARASAN_HDK	1
++#define SDIOH_TYPE_BCM27XX	2
++#define SDIOH_TYPE_TI_PCIXX21	4	/* TI PCIxx21 Standard Host Controller */
++#define SDIOH_TYPE_RICOH_R5C822	5	/* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter */
++#define SDIOH_TYPE_JMICRON	6	/* JMicron Standard SDIO Host Controller */
++
++/* For linux, allow yielding for dongle */
++#define BCMSDYIELD
++
++/* Expected card status value for CMD7 */
++#define SDIOH_CMD7_EXP_STATUS   0x00001E00
++
++#define RETRIES_LARGE 100000
++#define sdstd_os_yield(sd)	do {} while (0)
++#define RETRIES_SMALL 100
++
++
++#define USE_BLOCKMODE		0x2	/* Block mode can be single block or multi */
++#define USE_MULTIBLOCK		0x4
++
++#define USE_FIFO		0x8	/* Fifo vs non-fifo */
++
++#define CLIENT_INTR 		0x100	/* Get rid of this! */
++
++#define HC_INTR_RETUNING	0x1000
++
++
++#ifdef BCMSDIOH_TXGLOM
++/* Total glom pkt can not exceed 64K
++ * need one more slot for glom padding packet
++ */
++#define SDIOH_MAXGLOM_SIZE	(40+1)
++
++typedef struct glom_buf {
++	uint32 count;				/* Total number of pkts queued */
++	void *dma_buf_arr[SDIOH_MAXGLOM_SIZE];	/* Frame address */
++	ulong dma_phys_arr[SDIOH_MAXGLOM_SIZE]; /* DMA_MAPed address of frames */
++	uint16 nbytes[SDIOH_MAXGLOM_SIZE];	/* Size of each frame */
++} glom_buf_t;
++#endif
++
++struct sdioh_info {
++	uint cfg_bar;                   	/* pci cfg address for bar */
++	uint32 caps;                    	/* cached value of capabilities reg */
++	uint32 curr_caps;                    	/* max current capabilities reg */
++
++	osl_t 		*osh;			/* osh handler */
++	volatile char 	*mem_space;		/* pci device memory va */
++	uint		lockcount; 		/* nest count of sdstd_lock() calls */
++	bool		client_intr_enabled;	/* interrupt connnected flag */
++	bool		intr_handler_valid;	/* client driver interrupt handler valid */
++	sdioh_cb_fn_t	intr_handler;		/* registered interrupt handler */
++	void		*intr_handler_arg;	/* argument to call interrupt handler */
++	bool		initialized;		/* card initialized */
++	uint		target_dev;		/* Target device ID */
++	uint16		intmask;		/* Current active interrupts */
++	void		*sdos_info;		/* Pointer to per-OS private data */
++	void		*bcmsdh;		/* handler to upper layer stack (bcmsdh) */
++
++	uint32		controller_type;	/* Host controller type */
++	uint8		version;		/* Host Controller Spec Compliance Version */
++	uint		irq;			/* Client irq */
++	int		intrcount;		/* Client interrupts */
++	int		local_intrcount;	/* Controller interrupts */
++	bool		host_init_done;		/* Controller initted */
++	bool		card_init_done;		/* Client SDIO interface initted */
++	bool		polled_mode;		/* polling for command completion */
++
++	bool		sd_blockmode;		/* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
++						/*  Must be on for sd_multiblock to be effective */
++	bool		use_client_ints;	/* If this is false, make sure to restore */
++						/*  polling hack in wl_linux.c:wl_timer() */
++	int		adapter_slot;		/* Maybe dealing with multiple slots/controllers */
++	int		sd_mode;		/* SD1/SD4/SPI */
++	int		client_block_size[SDIOD_MAX_IOFUNCS];		/* Blocksize */
++	uint32		data_xfer_count;	/* Current transfer */
++	uint16		card_rca;		/* Current Address */
++	int8		sd_dma_mode;		/* DMA Mode (PIO, SDMA, ... ADMA2) on CMD53 */
++	uint8		num_funcs;		/* Supported funcs on client */
++	uint32		com_cis_ptr;
++	uint32		func_cis_ptr[SDIOD_MAX_IOFUNCS];
++	void		*dma_buf;		/* DMA Buffer virtual address */
++	ulong		dma_phys;		/* DMA Buffer physical address */
++	void		*adma2_dscr_buf;	/* ADMA2 Descriptor Buffer virtual address */
++	ulong		adma2_dscr_phys;	/* ADMA2 Descriptor Buffer physical address */
++
++	/* adjustments needed to make the dma align properly */
++	void		*dma_start_buf;
++	ulong		dma_start_phys;
++	uint		alloced_dma_size;
++	void		*adma2_dscr_start_buf;
++	ulong		adma2_dscr_start_phys;
++	uint		alloced_adma2_dscr_size;
++
++	int 		r_cnt;			/* rx count */
++	int 		t_cnt;			/* tx_count */
++	bool		got_hcint;		/* local interrupt flag */
++	uint16		last_intrstatus;	/* to cache intrstatus */
++	int 	host_UHSISupported;		/* whether UHSI is supported for HC. */
++	int 	card_UHSI_voltage_Supported; 	/* whether UHSI is supported for
++						 * Card in terms of Voltage [1.8 or 3.3].
++						 */
++	int	global_UHSI_Supp;	/* type of UHSI support in both host and card.
++					 * HOST_SDR_UNSUPP: capabilities not supported/matched
++					 * HOST_SDR_12_25: SDR12 and SDR25 supported
++					 * HOST_SDR_50_104_DDR: one of SDR50/SDR104 or DDR50 supptd
++					 */
++	volatile int	sd3_dat_state; 		/* data transfer state used for retuning check */
++	volatile int	sd3_tun_state; 		/* tuning state used for retuning check */
++	bool	sd3_tuning_reqd; 	/* tuning requirement parameter */
++	uint32	caps3;			/* cached value of 32 MSbits capabilities reg (SDIO 3.0) */
++#ifdef BCMSDIOH_TXGLOM
++	glom_buf_t glom_info;		/* pkt information used for glomming */
++	uint	txglom_mode;		/* Txglom mode: 0 - copy, 1 - multi-descriptor */
++#endif
++};
++
++#define DMA_MODE_NONE	0
++#define DMA_MODE_SDMA	1
++#define DMA_MODE_ADMA1	2
++#define DMA_MODE_ADMA2	3
++#define DMA_MODE_ADMA2_64 4
++#define DMA_MODE_AUTO	-1
++
++#define USE_DMA(sd)		((bool)((sd->sd_dma_mode > 0) ? TRUE : FALSE))
++
++/* States for Tuning and corr data */
++#define TUNING_IDLE 			0
++#define TUNING_START 			1
++#define TUNING_START_AFTER_DAT 	2
++#define TUNING_ONGOING 			3
++
++#define DATA_TRANSFER_IDLE 		0
++#define DATA_TRANSFER_ONGOING	1
++
++#define CHECK_TUNING_PRE_DATA	1
++#define CHECK_TUNING_POST_DATA	2
++
++
++#ifdef DHD_DEBUG
++#define SD_DHD_DISABLE_PERIODIC_TUNING 0x01
++#define SD_DHD_ENABLE_PERIODIC_TUNING  0x00
++#endif
++
++
++/************************************************************
++ * Internal interfaces: per-port references into bcmsdstd.c
++ */
++
++/* Global message bits */
++extern uint sd_msglevel;
++
++/* OS-independent interrupt handler */
++extern bool check_client_intr(sdioh_info_t *sd);
++
++/* Core interrupt enable/disable of device interrupts */
++extern void sdstd_devintr_on(sdioh_info_t *sd);
++extern void sdstd_devintr_off(sdioh_info_t *sd);
++
++/* Enable/disable interrupts for local controller events */
++extern void sdstd_intrs_on(sdioh_info_t *sd, uint16 norm, uint16 err);
++extern void sdstd_intrs_off(sdioh_info_t *sd, uint16 norm, uint16 err);
++
++/* Wait for specified interrupt and error bits to be set */
++extern void sdstd_spinbits(sdioh_info_t *sd, uint16 norm, uint16 err);
++
++
++/**************************************************************
++ * Internal interfaces: bcmsdstd.c references to per-port code
++ */
++
++/* Register mapping routines */
++extern uint32 *sdstd_reg_map(osl_t *osh, ulong addr, int size);
++extern void sdstd_reg_unmap(osl_t *osh, ulong addr, int size);
++
++/* Interrupt (de)registration routines */
++extern int sdstd_register_irq(sdioh_info_t *sd, uint irq);
++extern void sdstd_free_irq(uint irq, sdioh_info_t *sd);
++
++/* OS-specific interrupt wrappers (atomic interrupt enable/disable) */
++extern void sdstd_lock(sdioh_info_t *sd);
++extern void sdstd_unlock(sdioh_info_t *sd);
++extern void sdstd_waitlockfree(sdioh_info_t *sd);
++
++/* OS-specific wrappers for safe concurrent register access */
++extern void sdstd_os_lock_irqsave(sdioh_info_t *sd, ulong* flags);
++extern void sdstd_os_unlock_irqrestore(sdioh_info_t *sd, ulong* flags);
++
++/* OS-specific wait-for-interrupt-or-status */
++extern int sdstd_waitbits(sdioh_info_t *sd, uint16 norm, uint16 err, bool yield, uint16 *bits);
++
++/* used by bcmsdstd_linux [implemented in sdstd] */
++extern void sdstd_3_enable_retuning_int(sdioh_info_t *sd);
++extern void sdstd_3_disable_retuning_int(sdioh_info_t *sd);
++extern bool sdstd_3_is_retuning_int_set(sdioh_info_t *sd);
++extern void sdstd_3_check_and_do_tuning(sdioh_info_t *sd, int tuning_param);
++extern bool sdstd_3_check_and_set_retuning(sdioh_info_t *sd);
++extern int sdstd_3_get_tune_state(sdioh_info_t *sd);
++extern int sdstd_3_get_data_state(sdioh_info_t *sd);
++extern void sdstd_3_set_tune_state(sdioh_info_t *sd, int state);
++extern void sdstd_3_set_data_state(sdioh_info_t *sd, int state);
++extern uint8 sdstd_3_get_tuning_exp(sdioh_info_t *sd);
++extern uint32 sdstd_3_get_uhsi_clkmode(sdioh_info_t *sd);
++extern int sdstd_3_clk_tuning(sdioh_info_t *sd, uint32 sd3ClkMode);
++
++/* used by sdstd [implemented in bcmsdstd_linux/ndis] */
++extern void sdstd_3_start_tuning(sdioh_info_t *sd);
++extern void sdstd_3_osinit_tuning(sdioh_info_t *sd);
++extern void sdstd_3_osclean_tuning(sdioh_info_t *sd);
++
++extern void sdstd_enable_disable_periodic_timer(sdioh_info_t * sd, uint val);
++
++extern sdioh_info_t *sdioh_attach(osl_t *osh, void *bar0, uint irq);
++extern SDIOH_API_RC sdioh_detach(osl_t *osh, sdioh_info_t *sd);
++#endif /* _BCM_SD_STD_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmspi.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmspi.h
+new file mode 100644
+index 000000000..9b4bd2d8a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmspi.h
+@@ -0,0 +1,43 @@
++/*
++ * Broadcom SPI Low-Level Hardware Driver API
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmspi.h 514727 2014-11-12 03:02:48Z $
++ */
++#ifndef	_BCM_SPI_H
++#define	_BCM_SPI_H
++
++extern void spi_devintr_off(sdioh_info_t *sd);
++extern void spi_devintr_on(sdioh_info_t *sd);
++extern bool spi_start_clock(sdioh_info_t *sd, uint16 new_sd_divisor);
++extern bool spi_controller_highspeed_mode(sdioh_info_t *sd, bool hsmode);
++extern bool spi_check_client_intr(sdioh_info_t *sd, int *is_dev_intr);
++extern bool spi_hw_attach(sdioh_info_t *sd);
++extern bool spi_hw_detach(sdioh_info_t *sd);
++extern void spi_sendrecv(sdioh_info_t *sd, uint8 *msg_out, uint8 *msg_in, int msglen);
++extern void spi_spinbits(sdioh_info_t *sd);
++extern void spi_waitbits(sdioh_info_t *sd, bool yield);
++
++#endif /* _BCM_SPI_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmspibrcm.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmspibrcm.h
+new file mode 100644
+index 000000000..e9735ffc6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmspibrcm.h
+@@ -0,0 +1,165 @@
++/*
++ * SD-SPI Protocol Conversion - BCMSDH->gSPI Translation Layer
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmspibrcm.h 514727 2014-11-12 03:02:48Z $
++ */
++#ifndef	_BCM_SPI_BRCM_H
++#define	_BCM_SPI_BRCM_H
++
++#ifndef SPI_MAX_IOFUNCS
++/* Maximum number of I/O funcs */
++#define SPI_MAX_IOFUNCS		4
++#endif
++/* global msglevel for debug messages - bitvals come from sdiovar.h */
++
++#if defined(DHD_DEBUG)
++#define sd_err(x)	do { if (sd_msglevel & SDH_ERROR_VAL) printf x; } while (0)
++#define sd_trace(x)	do { if (sd_msglevel & SDH_TRACE_VAL) printf x; } while (0)
++#define sd_info(x)	do { if (sd_msglevel & SDH_INFO_VAL)  printf x; } while (0)
++#define sd_debug(x)	do { if (sd_msglevel & SDH_DEBUG_VAL) printf x; } while (0)
++#define sd_data(x)	do { if (sd_msglevel & SDH_DATA_VAL)  printf x; } while (0)
++#define sd_ctrl(x)	do { if (sd_msglevel & SDH_CTRL_VAL)  printf x; } while (0)
++#else
++#define sd_err(x)
++#define sd_trace(x)
++#define sd_info(x)
++#define sd_debug(x)
++#define sd_data(x)
++#define sd_ctrl(x)
++#endif
++
++#define sd_log(x)
++
++#define SDIOH_ASSERT(exp) \
++	do { if (!(exp)) \
++		printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \
++	} while (0)
++
++#define BLOCK_SIZE_F1		64
++#define BLOCK_SIZE_F2 		2048
++#define BLOCK_SIZE_F3 		2048
++
++/* internal return code */
++#define SUCCESS	0
++#undef ERROR
++#define ERROR	1
++#define ERROR_UF	2
++#define ERROR_OF	3
++
++/* private bus modes */
++#define SDIOH_MODE_SPI		0
++
++#define USE_BLOCKMODE		0x2	/* Block mode can be single block or multi */
++#define USE_MULTIBLOCK		0x4
++
++struct sdioh_info {
++	uint		cfg_bar;		/* pci cfg address for bar */
++	uint32		caps;			/* cached value of capabilities reg */
++	void		*bar0;			/* BAR0 for PCI Device */
++	osl_t		*osh;			/* osh handler */
++	void		*controller;	/* Pointer to SPI Controller's private data struct */
++	uint		lockcount;		/* nest count of spi_lock() calls */
++	bool		client_intr_enabled;	/* interrupt connnected flag */
++	bool		intr_handler_valid;	/* client driver interrupt handler valid */
++	sdioh_cb_fn_t	intr_handler;		/* registered interrupt handler */
++	void		*intr_handler_arg;	/* argument to call interrupt handler */
++	bool		initialized;		/* card initialized */
++	uint32		target_dev;		/* Target device ID */
++	uint32		intmask;		/* Current active interrupts */
++	void		*sdos_info;		/* Pointer to per-OS private data */
++	uint32		controller_type;	/* Host controller type */
++	uint8		version;		/* Host Controller Spec Compliance Version */
++	uint		irq;			/* Client irq */
++	uint32		intrcount;		/* Client interrupts */
++	uint32		local_intrcount;	/* Controller interrupts */
++	bool 		host_init_done;		/* Controller initted */
++	bool 		card_init_done;		/* Client SDIO interface initted */
++	bool 		polled_mode;		/* polling for command completion */
++
++	bool		sd_use_dma;		/* DMA on CMD53 */
++	bool 		sd_blockmode;		/* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
++						/*  Must be on for sd_multiblock to be effective */
++	bool 		use_client_ints;	/* If this is false, make sure to restore */
++						/*  polling hack in wl_linux.c:wl_timer() */
++	int 		adapter_slot;		/* Maybe dealing with multiple slots/controllers */
++	int 		sd_mode;		/* SD1/SD4/SPI */
++	int 		client_block_size[SPI_MAX_IOFUNCS];		/* Blocksize */
++	uint32 		data_xfer_count;	/* Current transfer */
++	uint16 		card_rca;		/* Current Address */
++	uint8 		num_funcs;		/* Supported funcs on client */
++	uint32 		card_dstatus;		/* 32bit device status */
++	uint32 		com_cis_ptr;
++	uint32 		func_cis_ptr[SPI_MAX_IOFUNCS];
++	void		*dma_buf;
++	ulong		dma_phys;
++	int 		r_cnt;			/* rx count */
++	int 		t_cnt;			/* tx_count */
++	uint32		wordlen;			/* host processor 16/32bits */
++	uint32		prev_fun;
++	uint32		chip;
++	uint32		chiprev;
++	bool		resp_delay_all;
++	bool		dwordmode;
++	bool		resp_delay_new;
++
++	struct spierrstats_t spierrstats;
++};
++
++/************************************************************
++ * Internal interfaces: per-port references into bcmspibrcm.c
++ */
++
++/* Global message bits */
++extern uint sd_msglevel;
++
++/**************************************************************
++ * Internal interfaces: bcmspibrcm.c references to per-port code
++ */
++
++/* Interrupt (de)registration routines */
++extern int spi_register_irq(sdioh_info_t *sd, uint irq);
++extern void spi_free_irq(uint irq, sdioh_info_t *sd);
++
++/* OS-specific interrupt wrappers (atomic interrupt enable/disable) */
++extern void spi_lock(sdioh_info_t *sd);
++extern void spi_unlock(sdioh_info_t *sd);
++
++/* Allocate/init/free per-OS private data */
++extern int spi_osinit(sdioh_info_t *sd);
++extern void spi_osfree(sdioh_info_t *sd);
++
++#define SPI_RW_FLAG_M			BITFIELD_MASK(1)	/* Bit [31] - R/W Command Bit */
++#define SPI_RW_FLAG_S			31
++#define SPI_ACCESS_M			BITFIELD_MASK(1)	/* Bit [30] - Fixed/Incr Access */
++#define SPI_ACCESS_S			30
++#define SPI_FUNCTION_M			BITFIELD_MASK(2)	/* Bit [29:28] - Function Number */
++#define SPI_FUNCTION_S			28
++#define SPI_REG_ADDR_M			BITFIELD_MASK(17)	/* Bit [27:11] - Address */
++#define SPI_REG_ADDR_S			11
++#define SPI_LEN_M			BITFIELD_MASK(11)	/* Bit [10:0] - Packet length */
++#define SPI_LEN_S			0
++
++#endif /* _BCM_SPI_BRCM_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsrom_fmt.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsrom_fmt.h
+new file mode 100644
+index 000000000..f1e9bfe7d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsrom_fmt.h
+@@ -0,0 +1,973 @@
++/*
++ * SROM format definition.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmsrom_fmt.h 646789 2016-06-30 19:43:02Z $
++ */
++
++#ifndef	_bcmsrom_fmt_h_
++#define	_bcmsrom_fmt_h_
++
++#define SROM_MAXREV		13	/* max revision supported by driver */
++
++/* Maximum srom: 12 Kilobits == 1536 bytes */
++
++#define	SROM_MAX		1536
++#define SROM_MAXW		594
++
++#ifdef LARGE_NVRAM_MAXSZ
++#define VARS_MAX                LARGE_NVRAM_MAXSZ
++#else
++#define VARS_MAX                4096
++#endif /* LARGE_NVRAM_MAXSZ */
++
++/* PCI fields */
++#define PCI_F0DEVID		48
++
++
++#define	SROM_WORDS		64
++
++#define SROM3_SWRGN_OFF		28	/* s/w region offset in words */
++
++#define	SROM_SSID		2
++#define	SROM_SVID		3
++
++#define	SROM_WL1LHMAXP		29
++
++#define	SROM_WL1LPAB0		30
++#define	SROM_WL1LPAB1		31
++#define	SROM_WL1LPAB2		32
++
++#define	SROM_WL1HPAB0		33
++#define	SROM_WL1HPAB1		34
++#define	SROM_WL1HPAB2		35
++
++#define	SROM_MACHI_IL0		36
++#define	SROM_MACMID_IL0		37
++#define	SROM_MACLO_IL0		38
++#define	SROM_MACHI_ET0		39
++#define	SROM_MACMID_ET0		40
++#define	SROM_MACLO_ET0		41
++#define	SROM_MACHI_ET1		42
++#define	SROM_MACMID_ET1		43
++#define	SROM_MACLO_ET1		44
++#define	SROM3_MACHI		37
++#define	SROM3_MACMID		38
++#define	SROM3_MACLO		39
++
++#define	SROM_BXARSSI2G		40
++#define	SROM_BXARSSI5G		41
++
++#define	SROM_TRI52G		42
++#define	SROM_TRI5GHL		43
++
++#define	SROM_RXPO52G		45
++
++#define	SROM2_ENETPHY		45
++
++#define	SROM_AABREV		46
++/* Fields in AABREV */
++#define	SROM_BR_MASK		0x00ff
++#define	SROM_CC_MASK		0x0f00
++#define	SROM_CC_SHIFT		8
++#define	SROM_AA0_MASK		0x3000
++#define	SROM_AA0_SHIFT		12
++#define	SROM_AA1_MASK		0xc000
++#define	SROM_AA1_SHIFT		14
++
++#define	SROM_WL0PAB0		47
++#define	SROM_WL0PAB1		48
++#define	SROM_WL0PAB2		49
++
++#define	SROM_LEDBH10		50
++#define	SROM_LEDBH32		51
++
++#define	SROM_WL10MAXP		52
++
++#define	SROM_WL1PAB0		53
++#define	SROM_WL1PAB1		54
++#define	SROM_WL1PAB2		55
++
++#define	SROM_ITT		56
++
++#define	SROM_BFL		57
++#define	SROM_BFL2		28
++#define	SROM3_BFL2		61
++
++#define	SROM_AG10		58
++
++#define	SROM_CCODE		59
++
++#define	SROM_OPO		60
++
++#define	SROM3_LEDDC		62
++
++#define	SROM_CRCREV		63
++
++/* SROM Rev 4: Reallocate the software part of the srom to accomodate
++ * MIMO features. It assumes up to two PCIE functions and 440 bytes
++ * of useable srom i.e. the useable storage in chips with OTP that
++ * implements hardware redundancy.
++ */
++
++#define	SROM4_WORDS		220
++
++#define	SROM4_SIGN		32
++#define	SROM4_SIGNATURE		0x5372
++
++#define	SROM4_BREV		33
++
++#define	SROM4_BFL0		34
++#define	SROM4_BFL1		35
++#define	SROM4_BFL2		36
++#define	SROM4_BFL3		37
++#define	SROM5_BFL0		37
++#define	SROM5_BFL1		38
++#define	SROM5_BFL2		39
++#define	SROM5_BFL3		40
++
++#define	SROM4_MACHI		38
++#define	SROM4_MACMID		39
++#define	SROM4_MACLO		40
++#define	SROM5_MACHI		41
++#define	SROM5_MACMID		42
++#define	SROM5_MACLO		43
++
++#define	SROM4_CCODE		41
++#define	SROM4_REGREV		42
++#define	SROM5_CCODE		34
++#define	SROM5_REGREV		35
++
++#define	SROM4_LEDBH10		43
++#define	SROM4_LEDBH32		44
++#define	SROM5_LEDBH10		59
++#define	SROM5_LEDBH32		60
++
++#define	SROM4_LEDDC		45
++#define	SROM5_LEDDC		45
++
++#define	SROM4_AA		46
++#define	SROM4_AA2G_MASK		0x00ff
++#define	SROM4_AA2G_SHIFT	0
++#define	SROM4_AA5G_MASK		0xff00
++#define	SROM4_AA5G_SHIFT	8
++
++#define	SROM4_AG10		47
++#define	SROM4_AG32		48
++
++#define	SROM4_TXPID2G		49
++#define	SROM4_TXPID5G		51
++#define	SROM4_TXPID5GL		53
++#define	SROM4_TXPID5GH		55
++
++#define SROM4_TXRXC		61
++#define SROM4_TXCHAIN_MASK	0x000f
++#define SROM4_TXCHAIN_SHIFT	0
++#define SROM4_RXCHAIN_MASK	0x00f0
++#define SROM4_RXCHAIN_SHIFT	4
++#define SROM4_SWITCH_MASK	0xff00
++#define SROM4_SWITCH_SHIFT	8
++
++
++/* Per-path fields */
++#define	MAX_PATH_SROM		4
++#define	SROM4_PATH0		64
++#define	SROM4_PATH1		87
++#define	SROM4_PATH2		110
++#define	SROM4_PATH3		133
++
++#define	SROM4_2G_ITT_MAXP	0
++#define	SROM4_2G_PA		1
++#define	SROM4_5G_ITT_MAXP	5
++#define	SROM4_5GLH_MAXP		6
++#define	SROM4_5G_PA		7
++#define	SROM4_5GL_PA		11
++#define	SROM4_5GH_PA		15
++
++/* Fields in the ITT_MAXP and 5GLH_MAXP words */
++#define	B2G_MAXP_MASK		0xff
++#define	B2G_ITT_SHIFT		8
++#define	B5G_MAXP_MASK		0xff
++#define	B5G_ITT_SHIFT		8
++#define	B5GH_MAXP_MASK		0xff
++#define	B5GL_MAXP_SHIFT		8
++
++/* All the miriad power offsets */
++#define	SROM4_2G_CCKPO		156
++#define	SROM4_2G_OFDMPO		157
++#define	SROM4_5G_OFDMPO		159
++#define	SROM4_5GL_OFDMPO	161
++#define	SROM4_5GH_OFDMPO	163
++#define	SROM4_2G_MCSPO		165
++#define	SROM4_5G_MCSPO		173
++#define	SROM4_5GL_MCSPO		181
++#define	SROM4_5GH_MCSPO		189
++#define	SROM4_CDDPO		197
++#define	SROM4_STBCPO		198
++#define	SROM4_BW40PO		199
++#define	SROM4_BWDUPPO		200
++
++#define	SROM4_CRCREV		219
++
++
++/* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
++ * This is acombined srom for both MIMO and SISO boards, usable in
++ * the .130 4Kilobit OTP with hardware redundancy.
++ */
++
++#define	SROM8_SIGN		64
++
++#define	SROM8_BREV		65
++
++#define	SROM8_BFL0		66
++#define	SROM8_BFL1		67
++#define	SROM8_BFL2		68
++#define	SROM8_BFL3		69
++
++#define	SROM8_MACHI		70
++#define	SROM8_MACMID		71
++#define	SROM8_MACLO		72
++
++#define	SROM8_CCODE		73
++#define	SROM8_REGREV		74
++
++#define	SROM8_LEDBH10		75
++#define	SROM8_LEDBH32		76
++
++#define	SROM8_LEDDC		77
++
++#define	SROM8_AA		78
++
++#define	SROM8_AG10		79
++#define	SROM8_AG32		80
++
++#define	SROM8_TXRXC		81
++
++#define	SROM8_BXARSSI2G		82
++#define	SROM8_BXARSSI5G		83
++#define	SROM8_TRI52G		84
++#define	SROM8_TRI5GHL		85
++#define	SROM8_RXPO52G		86
++
++#define SROM8_FEM2G		87
++#define SROM8_FEM5G		88
++#define SROM8_FEM_ANTSWLUT_MASK		0xf800
++#define SROM8_FEM_ANTSWLUT_SHIFT	11
++#define SROM8_FEM_TR_ISO_MASK		0x0700
++#define SROM8_FEM_TR_ISO_SHIFT		8
++#define SROM8_FEM_PDET_RANGE_MASK	0x00f8
++#define SROM8_FEM_PDET_RANGE_SHIFT	3
++#define SROM8_FEM_EXTPA_GAIN_MASK	0x0006
++#define SROM8_FEM_EXTPA_GAIN_SHIFT	1
++#define SROM8_FEM_TSSIPOS_MASK		0x0001
++#define SROM8_FEM_TSSIPOS_SHIFT		0
++
++#define SROM8_THERMAL		89
++
++/* Temp sense related entries */
++#define SROM8_MPWR_RAWTS		90
++#define SROM8_TS_SLP_OPT_CORRX	91
++/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
++#define SROM8_FOC_HWIQ_IQSWP	92
++
++#define SROM8_EXTLNAGAIN        93
++
++/* Temperature delta for PHY calibration */
++#define SROM8_PHYCAL_TEMPDELTA	94
++
++/* Measured power 1 & 2, 0-13 bits at offset 95, MSB 2 bits are unused for now. */
++#define SROM8_MPWR_1_AND_2	95
++
++
++/* Per-path offsets & fields */
++#define	SROM8_PATH0		96
++#define	SROM8_PATH1		112
++#define	SROM8_PATH2		128
++#define	SROM8_PATH3		144
++
++#define	SROM8_2G_ITT_MAXP	0
++#define	SROM8_2G_PA		1
++#define	SROM8_5G_ITT_MAXP	4
++#define	SROM8_5GLH_MAXP		5
++#define	SROM8_5G_PA		6
++#define	SROM8_5GL_PA		9
++#define	SROM8_5GH_PA		12
++
++/* All the miriad power offsets */
++#define	SROM8_2G_CCKPO		160
++
++#define	SROM8_2G_OFDMPO		161
++#define	SROM8_5G_OFDMPO		163
++#define	SROM8_5GL_OFDMPO	165
++#define	SROM8_5GH_OFDMPO	167
++
++#define	SROM8_2G_MCSPO		169
++#define	SROM8_5G_MCSPO		177
++#define	SROM8_5GL_MCSPO		185
++#define	SROM8_5GH_MCSPO		193
++
++#define	SROM8_CDDPO		201
++#define	SROM8_STBCPO		202
++#define	SROM8_BW40PO		203
++#define	SROM8_BWDUPPO		204
++
++/* SISO PA parameters are in the path0 spaces */
++#define	SROM8_SISO		96
++
++/* Legacy names for SISO PA paramters */
++#define	SROM8_W0_ITTMAXP	(SROM8_SISO + SROM8_2G_ITT_MAXP)
++#define	SROM8_W0_PAB0		(SROM8_SISO + SROM8_2G_PA)
++#define	SROM8_W0_PAB1		(SROM8_SISO + SROM8_2G_PA + 1)
++#define	SROM8_W0_PAB2		(SROM8_SISO + SROM8_2G_PA + 2)
++#define	SROM8_W1_ITTMAXP	(SROM8_SISO + SROM8_5G_ITT_MAXP)
++#define	SROM8_W1_MAXP_LCHC	(SROM8_SISO + SROM8_5GLH_MAXP)
++#define	SROM8_W1_PAB0		(SROM8_SISO + SROM8_5G_PA)
++#define	SROM8_W1_PAB1		(SROM8_SISO + SROM8_5G_PA + 1)
++#define	SROM8_W1_PAB2		(SROM8_SISO + SROM8_5G_PA + 2)
++#define	SROM8_W1_PAB0_LC	(SROM8_SISO + SROM8_5GL_PA)
++#define	SROM8_W1_PAB1_LC	(SROM8_SISO + SROM8_5GL_PA + 1)
++#define	SROM8_W1_PAB2_LC	(SROM8_SISO + SROM8_5GL_PA + 2)
++#define	SROM8_W1_PAB0_HC	(SROM8_SISO + SROM8_5GH_PA)
++#define	SROM8_W1_PAB1_HC	(SROM8_SISO + SROM8_5GH_PA + 1)
++#define	SROM8_W1_PAB2_HC	(SROM8_SISO + SROM8_5GH_PA + 2)
++
++#define	SROM8_CRCREV		219
++
++/* SROM REV 9 */
++#define SROM9_2GPO_CCKBW20	160
++#define SROM9_2GPO_CCKBW20UL	161
++#define SROM9_2GPO_LOFDMBW20	162
++#define SROM9_2GPO_LOFDMBW20UL	164
++
++#define SROM9_5GLPO_LOFDMBW20	166
++#define SROM9_5GLPO_LOFDMBW20UL	168
++#define SROM9_5GMPO_LOFDMBW20	170
++#define SROM9_5GMPO_LOFDMBW20UL	172
++#define SROM9_5GHPO_LOFDMBW20	174
++#define SROM9_5GHPO_LOFDMBW20UL	176
++
++#define SROM9_2GPO_MCSBW20	178
++#define SROM9_2GPO_MCSBW20UL	180
++#define SROM9_2GPO_MCSBW40	182
++
++#define SROM9_5GLPO_MCSBW20	184
++#define SROM9_5GLPO_MCSBW20UL	186
++#define SROM9_5GLPO_MCSBW40	188
++#define SROM9_5GMPO_MCSBW20	190
++#define SROM9_5GMPO_MCSBW20UL	192
++#define SROM9_5GMPO_MCSBW40	194
++#define SROM9_5GHPO_MCSBW20	196
++#define SROM9_5GHPO_MCSBW20UL	198
++#define SROM9_5GHPO_MCSBW40	200
++
++#define SROM9_PO_MCS32		202
++#define SROM9_PO_LOFDM40DUP	203
++#define SROM9_EU_EDCRSTH	204
++#define SROM10_EU_EDCRSTH	204
++#define SROM8_RXGAINERR_2G	205
++#define SROM8_RXGAINERR_5GL	206
++#define SROM8_RXGAINERR_5GM	207
++#define SROM8_RXGAINERR_5GH	208
++#define SROM8_RXGAINERR_5GU	209
++#define SROM8_SUBBAND_PPR	210
++#define SROM8_PCIEINGRESS_WAR	211
++#define SROM8_EU_EDCRSTH	212
++#define SROM9_SAR		212
++
++#define SROM8_NOISELVL_2G	213
++#define SROM8_NOISELVL_5GL	214
++#define SROM8_NOISELVL_5GM	215
++#define SROM8_NOISELVL_5GH	216
++#define SROM8_NOISELVL_5GU	217
++#define SROM8_NOISECALOFFSET	218
++
++#define SROM9_REV_CRC		219
++
++#define SROM10_CCKPWROFFSET	218
++#define SROM10_SIGN		219
++#define SROM10_SWCTRLMAP_2G	220
++#define SROM10_CRCREV		229
++
++#define	SROM10_WORDS		230
++#define	SROM10_SIGNATURE	SROM4_SIGNATURE
++
++
++/* SROM REV 11 */
++#define SROM11_BREV			65
++
++#define SROM11_BFL0			66
++#define SROM11_BFL1			67
++#define SROM11_BFL2			68
++#define SROM11_BFL3			69
++#define SROM11_BFL4			70
++#define SROM11_BFL5			71
++
++#define SROM11_MACHI			72
++#define SROM11_MACMID			73
++#define SROM11_MACLO			74
++
++#define SROM11_CCODE			75
++#define SROM11_REGREV			76
++
++#define SROM11_LEDBH10			77
++#define SROM11_LEDBH32			78
++
++#define SROM11_LEDDC			79
++
++#define SROM11_AA			80
++
++#define SROM11_AGBG10			81
++#define SROM11_AGBG2A0			82
++#define SROM11_AGA21			83
++
++#define SROM11_TXRXC			84
++
++#define SROM11_FEM_CFG1			85
++#define SROM11_FEM_CFG2			86
++
++/* Masks and offsets for FEM_CFG */
++#define SROM11_FEMCTRL_MASK		0xf800
++#define SROM11_FEMCTRL_SHIFT		11
++#define SROM11_PAPDCAP_MASK		0x0400
++#define SROM11_PAPDCAP_SHIFT		10
++#define SROM11_TWORANGETSSI_MASK	0x0200
++#define SROM11_TWORANGETSSI_SHIFT	9
++#define SROM11_PDGAIN_MASK		0x01f0
++#define SROM11_PDGAIN_SHIFT		4
++#define SROM11_EPAGAIN_MASK		0x000e
++#define SROM11_EPAGAIN_SHIFT		1
++#define SROM11_TSSIPOSSLOPE_MASK	0x0001
++#define SROM11_TSSIPOSSLOPE_SHIFT	0
++#define SROM11_GAINCTRLSPH_MASK		0xf800
++#define SROM11_GAINCTRLSPH_SHIFT	11
++
++#define SROM11_THERMAL			87
++#define SROM11_MPWR_RAWTS		88
++#define SROM11_TS_SLP_OPT_CORRX		89
++#define SROM11_XTAL_FREQ		90
++#define SROM11_5GB0_4080_W0_A1          91
++#define SROM11_PHYCAL_TEMPDELTA  	92
++#define SROM11_MPWR_1_AND_2 		93
++#define SROM11_5GB0_4080_W1_A1          94
++#define SROM11_TSSIFLOOR_2G 		95
++#define SROM11_TSSIFLOOR_5GL 		96
++#define SROM11_TSSIFLOOR_5GM 		97
++#define SROM11_TSSIFLOOR_5GH 		98
++#define SROM11_TSSIFLOOR_5GU 		99
++
++/* Masks and offsets for Thermal parameters */
++#define SROM11_TEMPS_PERIOD_MASK	0xf0
++#define SROM11_TEMPS_PERIOD_SHIFT	4
++#define SROM11_TEMPS_HYSTERESIS_MASK	0x0f
++#define SROM11_TEMPS_HYSTERESIS_SHIFT	0
++#define SROM11_TEMPCORRX_MASK		0xfc
++#define SROM11_TEMPCORRX_SHIFT		2
++#define SROM11_TEMPSENSE_OPTION_MASK	0x3
++#define SROM11_TEMPSENSE_OPTION_SHIFT	0
++
++#define SROM11_PDOFF_2G_40M_A0_MASK     0x000f
++#define SROM11_PDOFF_2G_40M_A0_SHIFT    0
++#define SROM11_PDOFF_2G_40M_A1_MASK     0x00f0
++#define SROM11_PDOFF_2G_40M_A1_SHIFT    4
++#define SROM11_PDOFF_2G_40M_A2_MASK     0x0f00
++#define SROM11_PDOFF_2G_40M_A2_SHIFT    8
++#define SROM11_PDOFF_2G_40M_VALID_MASK  0x8000
++#define SROM11_PDOFF_2G_40M_VALID_SHIFT 15
++
++#define SROM11_PDOFF_2G_40M     	100
++#define SROM11_PDOFF_40M_A0		101
++#define SROM11_PDOFF_40M_A1		102
++#define SROM11_PDOFF_40M_A2		103
++#define SROM11_5GB0_4080_W2_A1          103
++#define SROM11_PDOFF_80M_A0		104
++#define SROM11_PDOFF_80M_A1		105
++#define SROM11_PDOFF_80M_A2		106
++#define SROM11_5GB1_4080_W0_A1          106
++
++#define SROM11_SUBBAND5GVER 		107
++
++/* Per-path fields and offset */
++#define	MAX_PATH_SROM_11		3
++#define SROM11_PATH0			108
++#define SROM11_PATH1			128
++#define SROM11_PATH2			148
++
++#define	SROM11_2G_MAXP			0
++#define SROM11_5GB1_4080_PA             0
++#define	SROM11_2G_PA			1
++#define SROM11_5GB2_4080_PA             2
++#define	SROM11_RXGAINS1			4
++#define	SROM11_RXGAINS			5
++#define SROM11_5GB3_4080_PA             5
++#define	SROM11_5GB1B0_MAXP		6
++#define	SROM11_5GB3B2_MAXP		7
++#define	SROM11_5GB0_PA			8
++#define	SROM11_5GB1_PA			11
++#define	SROM11_5GB2_PA			14
++#define	SROM11_5GB3_PA			17
++
++/* Masks and offsets for rxgains */
++#define SROM11_RXGAINS5GTRELNABYPA_MASK		0x8000
++#define SROM11_RXGAINS5GTRELNABYPA_SHIFT	15
++#define SROM11_RXGAINS5GTRISOA_MASK		0x7800
++#define SROM11_RXGAINS5GTRISOA_SHIFT		11
++#define SROM11_RXGAINS5GELNAGAINA_MASK		0x0700
++#define SROM11_RXGAINS5GELNAGAINA_SHIFT		8
++#define SROM11_RXGAINS2GTRELNABYPA_MASK		0x0080
++#define SROM11_RXGAINS2GTRELNABYPA_SHIFT	7
++#define SROM11_RXGAINS2GTRISOA_MASK		0x0078
++#define SROM11_RXGAINS2GTRISOA_SHIFT		3
++#define SROM11_RXGAINS2GELNAGAINA_MASK		0x0007
++#define SROM11_RXGAINS2GELNAGAINA_SHIFT		0
++#define SROM11_RXGAINS5GHTRELNABYPA_MASK	0x8000
++#define SROM11_RXGAINS5GHTRELNABYPA_SHIFT	15
++#define SROM11_RXGAINS5GHTRISOA_MASK		0x7800
++#define SROM11_RXGAINS5GHTRISOA_SHIFT		11
++#define SROM11_RXGAINS5GHELNAGAINA_MASK		0x0700
++#define SROM11_RXGAINS5GHELNAGAINA_SHIFT	8
++#define SROM11_RXGAINS5GMTRELNABYPA_MASK	0x0080
++#define SROM11_RXGAINS5GMTRELNABYPA_SHIFT	7
++#define SROM11_RXGAINS5GMTRISOA_MASK		0x0078
++#define SROM11_RXGAINS5GMTRISOA_SHIFT		3
++#define SROM11_RXGAINS5GMELNAGAINA_MASK		0x0007
++#define SROM11_RXGAINS5GMELNAGAINA_SHIFT	0
++
++/* Power per rate */
++#define SROM11_CCKBW202GPO		168
++#define SROM11_CCKBW20UL2GPO		169
++#define SROM11_MCSBW202GPO		170
++#define SROM11_MCSBW202GPO_1		171
++#define SROM11_MCSBW402GPO		172
++#define SROM11_MCSBW402GPO_1		173
++#define SROM11_DOT11AGOFDMHRBW202GPO	174
++#define SROM11_OFDMLRBW202GPO		175
++
++#define SROM11_MCSBW205GLPO 		176
++#define SROM11_MCSBW205GLPO_1		177
++#define SROM11_MCSBW405GLPO 		178
++#define SROM11_MCSBW405GLPO_1		179
++#define SROM11_MCSBW805GLPO 		180
++#define SROM11_MCSBW805GLPO_1		181
++#define SROM11_RPCAL_2G			182
++#define SROM11_RPCAL_5GL		183
++#define SROM11_MCSBW205GMPO 		184
++#define SROM11_MCSBW205GMPO_1		185
++#define SROM11_MCSBW405GMPO 		186
++#define SROM11_MCSBW405GMPO_1		187
++#define SROM11_MCSBW805GMPO 		188
++#define SROM11_MCSBW805GMPO_1		189
++#define SROM11_RPCAL_5GM		190
++#define SROM11_RPCAL_5GH		191
++#define SROM11_MCSBW205GHPO 		192
++#define SROM11_MCSBW205GHPO_1		193
++#define SROM11_MCSBW405GHPO 		194
++#define SROM11_MCSBW405GHPO_1		195
++#define SROM11_MCSBW805GHPO 		196
++#define SROM11_MCSBW805GHPO_1		197
++#define SROM11_RPCAL_5GU		198
++#define SROM11_PDOFF_2G_CCK	        199
++#define SROM11_MCSLR5GLPO		200
++#define SROM11_MCSLR5GMPO		201
++#define SROM11_MCSLR5GHPO		202
++
++#define SROM11_SB20IN40HRPO		203
++#define SROM11_SB20IN80AND160HR5GLPO 	204
++#define SROM11_SB40AND80HR5GLPO		205
++#define SROM11_SB20IN80AND160HR5GMPO 	206
++#define SROM11_SB40AND80HR5GMPO		207
++#define SROM11_SB20IN80AND160HR5GHPO 	208
++#define SROM11_SB40AND80HR5GHPO		209
++#define SROM11_SB20IN40LRPO 		210
++#define SROM11_SB20IN80AND160LR5GLPO	211
++#define SROM11_SB40AND80LR5GLPO		212
++#define SROM11_TXIDXCAP2G               212
++#define SROM11_SB20IN80AND160LR5GMPO	213
++#define SROM11_SB40AND80LR5GMPO		214
++#define SROM11_TXIDXCAP5G               214
++#define SROM11_SB20IN80AND160LR5GHPO	215
++#define SROM11_SB40AND80LR5GHPO		216
++
++#define SROM11_DOT11AGDUPHRPO 		217
++#define SROM11_DOT11AGDUPLRPO		218
++
++/* MISC */
++#define SROM11_PCIEINGRESS_WAR		220
++#define SROM11_SAR			221
++
++#define SROM11_NOISELVL_2G		222
++#define SROM11_NOISELVL_5GL 		223
++#define SROM11_NOISELVL_5GM 		224
++#define SROM11_NOISELVL_5GH 		225
++#define SROM11_NOISELVL_5GU 		226
++
++#define SROM11_RXGAINERR_2G		227
++#define SROM11_RXGAINERR_5GL		228
++#define SROM11_RXGAINERR_5GM		229
++#define SROM11_RXGAINERR_5GH		230
++#define SROM11_RXGAINERR_5GU		231
++
++#define SROM11_EU_EDCRSTH	        232
++#define SROM12_EU_EDCRSTH	        232
++
++#define SROM11_SIGN 			64
++#define SROM11_CRCREV 			233
++
++#define	SROM11_WORDS				234
++#define	SROM11_SIGNATURE		0x0634
++
++
++/* SROM REV 12 */
++#define SROM12_SIGN                     64
++#define SROM12_WORDS			512
++#define SROM12_SIGNATURE		0x8888
++#define SROM12_CRCREV			511
++
++#define SROM12_BFL6				486
++#define SROM12_BFL7				487
++
++#define SROM12_MCSBW205GX1PO		234
++#define SROM12_MCSBW205GX1PO_1		235
++#define SROM12_MCSBW405GX1PO		236
++#define SROM12_MCSBW405GX1PO_1		237
++#define SROM12_MCSBW805GX1PO		238
++#define SROM12_MCSBW805GX1PO_1		239
++#define SROM12_MCSLR5GX1PO			240
++#define SROM12_SB40AND80LR5GX1PO		241
++#define SROM12_SB20IN80AND160LR5GX1PO	242
++#define SROM12_SB20IN80AND160HR5GX1PO	243
++#define SROM12_SB40AND80HR5GX1PO		244
++
++#define SROM12_MCSBW205GX2PO		245
++#define SROM12_MCSBW205GX2PO_1		246
++#define SROM12_MCSBW405GX2PO		247
++#define SROM12_MCSBW405GX2PO_1		248
++#define SROM12_MCSBW805GX2PO		249
++#define SROM12_MCSBW805GX2PO_1		250
++#define SROM12_MCSLR5GX2PO			251
++#define SROM12_SB40AND80LR5GX2PO	252
++#define SROM12_SB20IN80AND160LR5GX2PO	253
++#define SROM12_SB20IN80AND160HR5GX2PO	254
++#define SROM12_SB40AND80HR5GX2PO		255
++
++/* MISC */
++#define	SROM12_RXGAINS10			483
++#define	SROM12_RXGAINS11			484
++#define	SROM12_RXGAINS12			485
++
++/* Per-path fields and offset */
++#define	MAX_PATH_SROM_12			3
++#define SROM12_PATH0				256
++#define SROM12_PATH1				328
++#define SROM12_PATH2				400
++
++#define	SROM12_5GB42G_MAXP				0
++#define SROM12_2GB0_PA					1
++#define SROM12_2GB0_PA_W0				1
++#define SROM12_2GB0_PA_W1				2
++#define SROM12_2GB0_PA_W2				3
++#define SROM12_2GB0_PA_W3				4
++
++#define	SROM12_RXGAINS					5
++#define	SROM12_5GB1B0_MAXP				6
++#define	SROM12_5GB3B2_MAXP				7
++
++#define SROM12_5GB0_PA					8
++#define SROM12_5GB0_PA_W0				8
++#define SROM12_5GB0_PA_W1				9
++#define SROM12_5GB0_PA_W2				10
++#define SROM12_5GB0_PA_W3				11
++
++#define SROM12_5GB1_PA					12
++#define SROM12_5GB1_PA_W0				12
++#define SROM12_5GB1_PA_W1				13
++#define SROM12_5GB1_PA_W2				14
++#define SROM12_5GB1_PA_W3				15
++
++#define SROM12_5GB2_PA					16
++#define SROM12_5GB2_PA_W0				16
++#define SROM12_5GB2_PA_W1				17
++#define SROM12_5GB2_PA_W2				18
++#define SROM12_5GB2_PA_W3				19
++
++#define SROM12_5GB3_PA					20
++#define SROM12_5GB3_PA_W0				20
++#define SROM12_5GB3_PA_W1				21
++#define SROM12_5GB3_PA_W2				22
++#define SROM12_5GB3_PA_W3				23
++
++#define SROM12_5GB4_PA					24
++#define SROM12_5GB4_PA_W0				24
++#define SROM12_5GB4_PA_W1				25
++#define SROM12_5GB4_PA_W2				26
++#define SROM12_5GB4_PA_W3				27
++
++#define SROM12_2G40B0_PA				28
++#define SROM12_2G40B0_PA_W0				28
++#define SROM12_2G40B0_PA_W1				29
++#define SROM12_2G40B0_PA_W2				30
++#define SROM12_2G40B0_PA_W3				31
++
++#define SROM12_5G40B0_PA				32
++#define SROM12_5G40B0_PA_W0				32
++#define SROM12_5G40B0_PA_W1				33
++#define SROM12_5G40B0_PA_W2				34
++#define SROM12_5G40B0_PA_W3				35
++
++#define SROM12_5G40B1_PA				36
++#define SROM12_5G40B1_PA_W0				36
++#define SROM12_5G40B1_PA_W1				37
++#define SROM12_5G40B1_PA_W2				38
++#define SROM12_5G40B1_PA_W3				39
++
++#define SROM12_5G40B2_PA				40
++#define SROM12_5G40B2_PA_W0				40
++#define SROM12_5G40B2_PA_W1				41
++#define SROM12_5G40B2_PA_W2				42
++#define SROM12_5G40B2_PA_W3				43
++
++#define SROM12_5G40B3_PA				44
++#define SROM12_5G40B3_PA_W0				44
++#define SROM12_5G40B3_PA_W1				45
++#define SROM12_5G40B3_PA_W2				46
++#define SROM12_5G40B3_PA_W3				47
++
++#define SROM12_5G40B4_PA				48
++#define SROM12_5G40B4_PA_W0				48
++#define SROM12_5G40B4_PA_W1				49
++#define SROM12_5G40B4_PA_W2				50
++#define SROM12_5G40B4_PA_W3				51
++
++#define SROM12_5G80B0_PA				52
++#define SROM12_5G80B0_PA_W0				52
++#define SROM12_5G80B0_PA_W1				53
++#define SROM12_5G80B0_PA_W2				54
++#define SROM12_5G80B0_PA_W3				55
++
++#define SROM12_5G80B1_PA				56
++#define SROM12_5G80B1_PA_W0				56
++#define SROM12_5G80B1_PA_W1				57
++#define SROM12_5G80B1_PA_W2				58
++#define SROM12_5G80B1_PA_W3				59
++
++#define SROM12_5G80B2_PA				60
++#define SROM12_5G80B2_PA_W0				60
++#define SROM12_5G80B2_PA_W1				61
++#define SROM12_5G80B2_PA_W2				62
++#define SROM12_5G80B2_PA_W3				63
++
++#define SROM12_5G80B3_PA				64
++#define SROM12_5G80B3_PA_W0				64
++#define SROM12_5G80B3_PA_W1				65
++#define SROM12_5G80B3_PA_W2				66
++#define SROM12_5G80B3_PA_W3				67
++
++#define SROM12_5G80B4_PA				68
++#define SROM12_5G80B4_PA_W0				68
++#define SROM12_5G80B4_PA_W1				69
++#define SROM12_5G80B4_PA_W2				70
++#define SROM12_5G80B4_PA_W3				71
++
++/* PD offset */
++#define SROM12_PDOFF_2G_CCK				472
++
++#define SROM12_PDOFF_20in40M_5G_B0		473
++#define SROM12_PDOFF_20in40M_5G_B1		474
++#define SROM12_PDOFF_20in40M_5G_B2		475
++#define SROM12_PDOFF_20in40M_5G_B3		476
++#define SROM12_PDOFF_20in40M_5G_B4		477
++
++#define SROM12_PDOFF_40in80M_5G_B0		478
++#define SROM12_PDOFF_40in80M_5G_B1		479
++#define SROM12_PDOFF_40in80M_5G_B2		480
++#define SROM12_PDOFF_40in80M_5G_B3		481
++#define SROM12_PDOFF_40in80M_5G_B4		482
++
++#define SROM12_PDOFF_20in80M_5G_B0		488
++#define SROM12_PDOFF_20in80M_5G_B1		489
++#define SROM12_PDOFF_20in80M_5G_B2		490
++#define SROM12_PDOFF_20in80M_5G_B3		491
++#define SROM12_PDOFF_20in80M_5G_B4		492
++
++#define SROM13_PDOFFSET20IN40M5GCORE3           98
++#define SROM13_PDOFFSET20IN40M5GCORE3_1         99
++#define SROM13_PDOFFSET20IN80M5GCORE3           510
++#define SROM13_PDOFFSET20IN80M5GCORE3_1         511
++#define SROM13_PDOFFSET40IN80M5GCORE3           105
++#define SROM13_PDOFFSET40IN80M5GCORE3_1         106
++
++#define SROM13_PDOFFSET20IN40M2G                94
++#define SROM13_PDOFFSET20IN40M2GCORE3           95
++
++#define SROM12_GPDN_L				91  /* GPIO pull down bits [15:0]  */
++#define SROM12_GPDN_H				233 /* GPIO pull down bits [31:16] */
++
++#define SROM13_SIGN                     64
++#define SROM13_WORDS                    590
++#define SROM13_SIGNATURE                0x4d55
++#define SROM13_CRCREV                   589
++
++
++/* Per-path fields and offset */
++#define MAX_PATH_SROM_13                        4
++#define SROM13_PATH0                            256
++#define SROM13_PATH1                            328
++#define SROM13_PATH2                            400
++#define SROM13_PATH3                            512
++#define SROM13_RXGAINS                         5
++
++#define SROM13_XTALFREQ                 90
++
++#define SROM13_PDOFFSET20IN40M2G        94
++#define SROM13_PDOFFSET20IN40M2GCORE3   95
++#define SROM13_SB20IN40HRLRPOX          96
++
++#define SROM13_RXGAINS1CORE3            97
++
++#define SROM13_PDOFFSET20IN40M5GCORE3   98
++#define SROM13_PDOFFSET20IN40M5GCORE3_1 99
++
++#define SROM13_ANTGAIN_BANDBGA          100
++
++#define SROM13_RXGAINS2CORE0            101
++#define SROM13_RXGAINS2CORE1            102
++#define SROM13_RXGAINS2CORE2            103
++#define SROM13_RXGAINS2CORE3            104
++
++#define SROM13_PDOFFSET40IN80M5GCORE3   105
++#define SROM13_PDOFFSET40IN80M5GCORE3_1 106
++
++/* power per rate */
++#define SROM13_MCS1024QAM2GPO           108
++#define SROM13_MCS1024QAM5GLPO          109
++#define SROM13_MCS1024QAM5GLPO_1        110
++#define SROM13_MCS1024QAM5GMPO          111
++#define SROM13_MCS1024QAM5GMPO_1        112
++#define SROM13_MCS1024QAM5GHPO          113
++#define SROM13_MCS1024QAM5GHPO_1        114
++#define SROM13_MCS1024QAM5GX1PO         115
++#define SROM13_MCS1024QAM5GX1PO_1       116
++#define SROM13_MCS1024QAM5GX2PO         117
++#define SROM13_MCS1024QAM5GX2PO_1       118
++
++#define SROM13_MCSBW1605GLPO            119
++#define SROM13_MCSBW1605GLPO_1          120
++#define SROM13_MCSBW1605GMPO            121
++#define SROM13_MCSBW1605GMPO_1          122
++#define SROM13_MCSBW1605GHPO            123
++#define SROM13_MCSBW1605GHPO_1          124
++
++#define SROM13_MCSBW1605GX1PO           125
++#define SROM13_MCSBW1605GX1PO_1         126
++#define SROM13_MCSBW1605GX2PO           127
++#define SROM13_MCSBW1605GX2PO_1         128
++
++#define SROM13_ULBPPROFFS5GB0		129
++#define SROM13_ULBPPROFFS5GB1           130
++#define SROM13_ULBPPROFFS5GB2           131
++#define SROM13_ULBPPROFFS5GB3           132
++#define SROM13_ULBPPROFFS5GB4           133
++#define SROM13_ULBPPROFFS2G		134
++
++#define SROM13_MCS8POEXP                135
++#define SROM13_MCS8POEXP_1              136
++#define SROM13_MCS9POEXP                137
++#define SROM13_MCS9POEXP_1              138
++#define SROM13_MCS10POEXP               139
++#define SROM13_MCS10POEXP_1             140
++#define SROM13_MCS11POEXP               141
++#define SROM13_MCS11POEXP_1             142
++#define SROM13_ULBPDOFFS5GB0A0		143
++#define SROM13_ULBPDOFFS5GB0A1          144
++#define SROM13_ULBPDOFFS5GB0A2          145
++#define SROM13_ULBPDOFFS5GB0A3          146
++#define SROM13_ULBPDOFFS5GB1A0          147
++#define SROM13_ULBPDOFFS5GB1A1          148
++#define SROM13_ULBPDOFFS5GB1A2          149
++#define SROM13_ULBPDOFFS5GB1A3          150
++#define SROM13_ULBPDOFFS5GB2A0          151
++#define SROM13_ULBPDOFFS5GB2A1          152
++#define SROM13_ULBPDOFFS5GB2A2          153
++#define SROM13_ULBPDOFFS5GB2A3          154
++#define SROM13_ULBPDOFFS5GB3A0          155
++#define SROM13_ULBPDOFFS5GB3A1          156
++#define SROM13_ULBPDOFFS5GB3A2          157
++#define SROM13_ULBPDOFFS5GB3A3          158
++#define SROM13_ULBPDOFFS5GB4A0          159
++#define SROM13_ULBPDOFFS5GB4A1          160
++#define SROM13_ULBPDOFFS5GB4A2          161
++#define SROM13_ULBPDOFFS5GB4A3          162
++#define SROM13_ULBPDOFFS2GA0		163
++#define SROM13_ULBPDOFFS2GA1		164
++#define SROM13_ULBPDOFFS2GA2		165
++#define SROM13_ULBPDOFFS2GA3		166
++
++#define SROM13_RPCAL5GB4                199
++#define SROM13_RPCAL2GCORE3             101
++#define SROM13_RPCAL5GB01CORE3          102
++#define SROM13_RPCAL5GB23CORE3          103
++
++#define SROM13_EU_EDCRSTH               232
++
++#define SROM13_SWCTRLMAP4_CFG			493
++#define SROM13_SWCTRLMAP4_TX2G_FEM3TO0		494
++#define SROM13_SWCTRLMAP4_RX2G_FEM3TO0		495
++#define SROM13_SWCTRLMAP4_RXBYP2G_FEM3TO0	496
++#define SROM13_SWCTRLMAP4_MISC2G_FEM3TO0	497
++#define SROM13_SWCTRLMAP4_TX5G_FEM3TO0		498
++#define SROM13_SWCTRLMAP4_RX5G_FEM3TO0		499
++#define SROM13_SWCTRLMAP4_RXBYP5G_FEM3TO0	500
++#define SROM13_SWCTRLMAP4_MISC5G_FEM3TO0	501
++#define SROM13_SWCTRLMAP4_TX2G_FEM7TO4		502
++#define SROM13_SWCTRLMAP4_RX2G_FEM7TO4		503
++#define SROM13_SWCTRLMAP4_RXBYP2G_FEM7TO4	504
++#define SROM13_SWCTRLMAP4_MISC2G_FEM7TO4	505
++#define SROM13_SWCTRLMAP4_TX5G_FEM7TO4		506
++#define SROM13_SWCTRLMAP4_RX5G_FEM7TO4		507
++#define SROM13_SWCTRLMAP4_RXBYP5G_FEM7TO4	508
++#define SROM13_SWCTRLMAP4_MISC5G_FEM7TO4	509
++
++#define SROM13_PDOFFSET20IN80M5GCORE3   510
++#define SROM13_PDOFFSET20IN80M5GCORE3_1 511
++
++#define SROM13_NOISELVLCORE3            584
++#define SROM13_NOISELVLCORE3_1          585
++#define SROM13_RXGAINERRCORE3           586
++#define SROM13_RXGAINERRCORE3_1         587
++
++
++#define SROM16_SIGN                     104
++#define SROM16_WORDS                    512
++#define SROM16_SIGNATURE                0x4347
++#define SROM16_CRCREV                   511
++
++typedef struct {
++	uint8 tssipos;		/* TSSI positive slope, 1: positive, 0: negative */
++	uint8 extpagain;	/* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */
++	uint8 pdetrange;	/* support 32 combinations of different Pdet dynamic ranges */
++	uint8 triso;		/* TR switch isolation */
++	uint8 antswctrllut;	/* antswctrl lookup table configuration: 32 possible choices */
++} srom_fem_t;
++
++#endif	/* _bcmsrom_fmt_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsrom_tbl.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsrom_tbl.h
+new file mode 100644
+index 000000000..e855186f1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmsrom_tbl.h
+@@ -0,0 +1,1408 @@
++/*
++ * Table that encodes the srom formats for PCI/PCIe NICs.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmsrom_tbl.h 616054 2016-01-29 13:22:24Z $
++ */
++
++#ifndef	_bcmsrom_tbl_h_
++#define	_bcmsrom_tbl_h_
++
++#include "sbpcmcia.h"
++#include "wlioctl.h"
++#include <bcmsrom_fmt.h>
++
++typedef struct {
++	const char *name;
++	uint32	revmask;
++	uint32	flags;
++	uint16	off;
++	uint16	mask;
++} sromvar_t;
++
++#define SRFL_MORE	1		/* value continues as described by the next entry */
++#define	SRFL_NOFFS	2		/* value bits can't be all one's */
++#define	SRFL_PRHEX	4		/* value is in hexdecimal format */
++#define	SRFL_PRSIGN	8		/* value is in signed decimal format */
++#define	SRFL_CCODE	0x10		/* value is in country code format */
++#define	SRFL_ETHADDR	0x20		/* value is an Ethernet address */
++#define SRFL_LEDDC	0x40		/* value is an LED duty cycle */
++#define SRFL_NOVAR	0x80		/* do not generate a nvram param, entry is for mfgc */
++#define SRFL_ARRAY	0x100		/* value is in an array. All elements EXCEPT FOR THE LAST
++					 * ONE in the array should have this flag set.
++					 */
++
++
++#define SROM_DEVID_PCIE	48
++
++/**
++ * Assumptions:
++ * - Ethernet address spans across 3 consecutive words
++ *
++ * Table rules:
++ * - Add multiple entries next to each other if a value spans across multiple words
++ *   (even multiple fields in the same word) with each entry except the last having
++ *   it's SRFL_MORE bit set.
++ * - Ethernet address entry does not follow above rule and must not have SRFL_MORE
++ *   bit set. Its SRFL_ETHADDR bit implies it takes multiple words.
++ * - The last entry's name field must be NULL to indicate the end of the table. Other
++ *   entries must have non-NULL name.
++ */
++static const sromvar_t pci_sromvars[] = {
++/*	name		revmask		flags		off			mask */
++#if defined(CABLECPE)
++	{"devid",	0xffffff00,	SRFL_PRHEX,	PCI_F0DEVID,		0xffff},
++#elif defined(BCMPCIEDEV) && defined(BCMPCIEDEV_ENABLED)
++	{"devid",	0xffffff00,	SRFL_PRHEX, SROM_DEVID_PCIE,		0xffff},
++#else
++	{"devid",	0xffffff00,	SRFL_PRHEX|SRFL_NOVAR,	PCI_F0DEVID,	0xffff},
++#endif 
++	{"boardrev",	0x0000000e,	SRFL_PRHEX,	SROM_AABREV,		SROM_BR_MASK},
++	{"boardrev",	0x000000f0,	SRFL_PRHEX,	SROM4_BREV,		0xffff},
++	{"boardrev",	0xffffff00,	SRFL_PRHEX,	SROM8_BREV,		0xffff},
++	{"boardflags",	0x00000002,	SRFL_PRHEX,	SROM_BFL,		0xffff},
++	{"boardflags",	0x00000004,	SRFL_PRHEX|SRFL_MORE,	SROM_BFL,	0xffff},
++	{"",		0,		0,		SROM_BFL2,		0xffff},
++	{"boardflags",	0x00000008,	SRFL_PRHEX|SRFL_MORE,	SROM_BFL,	0xffff},
++	{"",		0,		0,		SROM3_BFL2,		0xffff},
++	{"boardflags",	0x00000010,	SRFL_PRHEX|SRFL_MORE,	SROM4_BFL0,	0xffff},
++	{"",		0,		0,		SROM4_BFL1,		0xffff},
++	{"boardflags",	0x000000e0,	SRFL_PRHEX|SRFL_MORE,	SROM5_BFL0,	0xffff},
++	{"",		0,		0,		SROM5_BFL1,		0xffff},
++	{"boardflags",	0xffffff00,	SRFL_PRHEX|SRFL_MORE,	SROM8_BFL0,	0xffff},
++	{"",		0,		0,		SROM8_BFL1,		0xffff},
++	{"boardflags2", 0x00000010,	SRFL_PRHEX|SRFL_MORE,	SROM4_BFL2,	0xffff},
++	{"",		0,		0,		SROM4_BFL3,		0xffff},
++	{"boardflags2", 0x000000e0,	SRFL_PRHEX|SRFL_MORE,	SROM5_BFL2,	0xffff},
++	{"",		0,		0,		SROM5_BFL3,		0xffff},
++	{"boardflags2", 0xffffff00,	SRFL_PRHEX|SRFL_MORE,	SROM8_BFL2,	0xffff},
++	{"",		0,		0,		SROM8_BFL3,		0xffff},
++	{"boardtype",	0xfffffffc,	SRFL_PRHEX,	SROM_SSID,		0xffff},
++	{"subvid",	0xfffffffc,	SRFL_PRHEX,	SROM_SVID,		0xffff},
++	{"boardnum",	0x00000006,	0,		SROM_MACLO_IL0,		0xffff},
++	{"boardnum",	0x00000008,	0,		SROM3_MACLO,		0xffff},
++	{"boardnum",	0x00000010,	0,		SROM4_MACLO,		0xffff},
++	{"boardnum",	0x000000e0,	0,		SROM5_MACLO,		0xffff},
++	{"boardnum",	0x00000700,	0,		SROM8_MACLO,		0xffff},
++	{"cc",		0x00000002,	0,		SROM_AABREV,		SROM_CC_MASK},
++	{"regrev",	0x00000008,	0,		SROM_OPO,		0xff00},
++	{"regrev",	0x00000010,	0,		SROM4_REGREV,		0xffff},
++	{"regrev",	0x000000e0,	0,		SROM5_REGREV,		0xffff},
++	{"regrev",	0x00000700,	0,		SROM8_REGREV,		0xffff},
++	{"ledbh0",	0x0000000e,	SRFL_NOFFS,	SROM_LEDBH10,		0x00ff},
++	{"ledbh1",	0x0000000e,	SRFL_NOFFS,	SROM_LEDBH10,		0xff00},
++	{"ledbh2",	0x0000000e,	SRFL_NOFFS,	SROM_LEDBH32,		0x00ff},
++	{"ledbh3",	0x0000000e,	SRFL_NOFFS,	SROM_LEDBH32,		0xff00},
++	{"ledbh0",	0x00000010,	SRFL_NOFFS,	SROM4_LEDBH10,		0x00ff},
++	{"ledbh1",	0x00000010,	SRFL_NOFFS,	SROM4_LEDBH10,		0xff00},
++	{"ledbh2",	0x00000010,	SRFL_NOFFS,	SROM4_LEDBH32,		0x00ff},
++	{"ledbh3",	0x00000010,	SRFL_NOFFS,	SROM4_LEDBH32,		0xff00},
++	{"ledbh0",	0x000000e0,	SRFL_NOFFS,	SROM5_LEDBH10,		0x00ff},
++	{"ledbh1",	0x000000e0,	SRFL_NOFFS,	SROM5_LEDBH10,		0xff00},
++	{"ledbh2",	0x000000e0,	SRFL_NOFFS,	SROM5_LEDBH32,		0x00ff},
++	{"ledbh3",	0x000000e0,	SRFL_NOFFS,	SROM5_LEDBH32,		0xff00},
++	{"ledbh0",	0x00000700,	SRFL_NOFFS,	SROM8_LEDBH10,		0x00ff},
++	{"ledbh1",	0x00000700,	SRFL_NOFFS,	SROM8_LEDBH10,		0xff00},
++	{"ledbh2",	0x00000700,	SRFL_NOFFS,	SROM8_LEDBH32,		0x00ff},
++	{"ledbh3",	0x00000700,	SRFL_NOFFS,	SROM8_LEDBH32,		0xff00},
++	{"pa0b0",	0x0000000e,	SRFL_PRHEX,	SROM_WL0PAB0,		0xffff},
++	{"pa0b1",	0x0000000e,	SRFL_PRHEX,	SROM_WL0PAB1,		0xffff},
++	{"pa0b2",	0x0000000e,	SRFL_PRHEX,	SROM_WL0PAB2,		0xffff},
++	{"pa0itssit",	0x0000000e,	0,		SROM_ITT,		0x00ff},
++	{"pa0maxpwr",	0x0000000e,	0,		SROM_WL10MAXP,		0x00ff},
++	{"pa0b0",	0x00000700,	SRFL_PRHEX,	SROM8_W0_PAB0,		0xffff},
++	{"pa0b1",	0x00000700,	SRFL_PRHEX,	SROM8_W0_PAB1,		0xffff},
++	{"pa0b2",	0x00000700,	SRFL_PRHEX,	SROM8_W0_PAB2,		0xffff},
++	{"pa0itssit",	0x00000700,	0,		SROM8_W0_ITTMAXP,	0xff00},
++	{"pa0maxpwr",	0x00000700,	0,		SROM8_W0_ITTMAXP,	0x00ff},
++	{"opo",		0x0000000c,	0,		SROM_OPO,		0x00ff},
++	{"opo",		0x00000700,	0,		SROM8_2G_OFDMPO,	0x00ff},
++	{"aa2g",	0x0000000e,	0,		SROM_AABREV,		SROM_AA0_MASK},
++	{"aa2g",	0x000000f0,	0,		SROM4_AA,		0x00ff},
++	{"aa2g",	0x00000700,	0,		SROM8_AA,		0x00ff},
++	{"aa5g",	0x0000000e,	0,		SROM_AABREV,		SROM_AA1_MASK},
++	{"aa5g",	0x000000f0,	0,		SROM4_AA,		0xff00},
++	{"aa5g",	0x00000700,	0,		SROM8_AA,		0xff00},
++	{"ag0",		0x0000000e,	0,		SROM_AG10,		0x00ff},
++	{"ag1",		0x0000000e,	0,		SROM_AG10,		0xff00},
++	{"ag0",		0x000000f0,	0,		SROM4_AG10,		0x00ff},
++	{"ag1",		0x000000f0,	0,		SROM4_AG10,		0xff00},
++	{"ag2",		0x000000f0,	0,		SROM4_AG32,		0x00ff},
++	{"ag3",		0x000000f0,	0,		SROM4_AG32,		0xff00},
++	{"ag0",		0x00000700,	0,		SROM8_AG10,		0x00ff},
++	{"ag1",		0x00000700,	0,		SROM8_AG10,		0xff00},
++	{"ag2",		0x00000700,	0,		SROM8_AG32,		0x00ff},
++	{"ag3",		0x00000700,	0,		SROM8_AG32,		0xff00},
++	{"pa1b0",	0x0000000e,	SRFL_PRHEX,	SROM_WL1PAB0,		0xffff},
++	{"pa1b1",	0x0000000e,	SRFL_PRHEX,	SROM_WL1PAB1,		0xffff},
++	{"pa1b2",	0x0000000e,	SRFL_PRHEX,	SROM_WL1PAB2,		0xffff},
++	{"pa1lob0",	0x0000000c,	SRFL_PRHEX,	SROM_WL1LPAB0,		0xffff},
++	{"pa1lob1",	0x0000000c,	SRFL_PRHEX,	SROM_WL1LPAB1,		0xffff},
++	{"pa1lob2",	0x0000000c,	SRFL_PRHEX,	SROM_WL1LPAB2,		0xffff},
++	{"pa1hib0",	0x0000000c,	SRFL_PRHEX,	SROM_WL1HPAB0,		0xffff},
++	{"pa1hib1",	0x0000000c,	SRFL_PRHEX,	SROM_WL1HPAB1,		0xffff},
++	{"pa1hib2",	0x0000000c,	SRFL_PRHEX,	SROM_WL1HPAB2,		0xffff},
++	{"pa1itssit",	0x0000000e,	0,		SROM_ITT,		0xff00},
++	{"pa1maxpwr",	0x0000000e,	0,		SROM_WL10MAXP,		0xff00},
++	{"pa1lomaxpwr",	0x0000000c,	0,		SROM_WL1LHMAXP,		0xff00},
++	{"pa1himaxpwr",	0x0000000c,	0,		SROM_WL1LHMAXP,		0x00ff},
++	{"pa1b0",	0x00000700,	SRFL_PRHEX,	SROM8_W1_PAB0,		0xffff},
++	{"pa1b1",	0x00000700,	SRFL_PRHEX,	SROM8_W1_PAB1,		0xffff},
++	{"pa1b2",	0x00000700,	SRFL_PRHEX,	SROM8_W1_PAB2,		0xffff},
++	{"pa1lob0",	0x00000700,	SRFL_PRHEX,	SROM8_W1_PAB0_LC,	0xffff},
++	{"pa1lob1",	0x00000700,	SRFL_PRHEX,	SROM8_W1_PAB1_LC,	0xffff},
++	{"pa1lob2",	0x00000700,	SRFL_PRHEX,	SROM8_W1_PAB2_LC,	0xffff},
++	{"pa1hib0",	0x00000700,	SRFL_PRHEX,	SROM8_W1_PAB0_HC,	0xffff},
++	{"pa1hib1",	0x00000700,	SRFL_PRHEX,	SROM8_W1_PAB1_HC,	0xffff},
++	{"pa1hib2",	0x00000700,	SRFL_PRHEX,	SROM8_W1_PAB2_HC,	0xffff},
++	{"pa1itssit",	0x00000700,	0,		SROM8_W1_ITTMAXP,	0xff00},
++	{"pa1maxpwr",	0x00000700,	0,		SROM8_W1_ITTMAXP,	0x00ff},
++	{"pa1lomaxpwr",	0x00000700,	0,		SROM8_W1_MAXP_LCHC,	0xff00},
++	{"pa1himaxpwr",	0x00000700,	0,		SROM8_W1_MAXP_LCHC,	0x00ff},
++	{"bxa2g",	0x00000008,	0,		SROM_BXARSSI2G,		0x1800},
++	{"rssisav2g",	0x00000008,	0,		SROM_BXARSSI2G,		0x0700},
++	{"rssismc2g",	0x00000008,	0,		SROM_BXARSSI2G,		0x00f0},
++	{"rssismf2g",	0x00000008,	0,		SROM_BXARSSI2G,		0x000f},
++	{"bxa2g",	0x00000700,	0,		SROM8_BXARSSI2G,	0x1800},
++	{"rssisav2g",	0x00000700,	0,		SROM8_BXARSSI2G,	0x0700},
++	{"rssismc2g",	0x00000700,	0,		SROM8_BXARSSI2G,	0x00f0},
++	{"rssismf2g",	0x00000700,	0,		SROM8_BXARSSI2G,	0x000f},
++	{"bxa5g",	0x00000008,	0,		SROM_BXARSSI5G,		0x1800},
++	{"rssisav5g",	0x00000008,	0,		SROM_BXARSSI5G,		0x0700},
++	{"rssismc5g",	0x00000008,	0,		SROM_BXARSSI5G,		0x00f0},
++	{"rssismf5g",	0x00000008,	0,		SROM_BXARSSI5G,		0x000f},
++	{"bxa5g",	0x00000700,	0,		SROM8_BXARSSI5G,	0x1800},
++	{"rssisav5g",	0x00000700,	0,		SROM8_BXARSSI5G,	0x0700},
++	{"rssismc5g",	0x00000700,	0,		SROM8_BXARSSI5G,	0x00f0},
++	{"rssismf5g",	0x00000700,	0,		SROM8_BXARSSI5G,	0x000f},
++	{"tri2g",	0x00000008,	0,		SROM_TRI52G,		0x00ff},
++	{"tri5g",	0x00000008,	0,		SROM_TRI52G,		0xff00},
++	{"tri5gl",	0x00000008,	0,		SROM_TRI5GHL,		0x00ff},
++	{"tri5gh",	0x00000008,	0,		SROM_TRI5GHL,		0xff00},
++	{"tri2g",	0x00000700,	0,		SROM8_TRI52G,		0x00ff},
++	{"tri5g",	0x00000700,	0,		SROM8_TRI52G,		0xff00},
++	{"tri5gl",	0x00000700,	0,		SROM8_TRI5GHL,		0x00ff},
++	{"tri5gh",	0x00000700,	0,		SROM8_TRI5GHL,		0xff00},
++	{"rxpo2g",	0x00000008,	SRFL_PRSIGN,	SROM_RXPO52G,		0x00ff},
++	{"rxpo5g",	0x00000008,	SRFL_PRSIGN,	SROM_RXPO52G,		0xff00},
++	{"rxpo2g",	0x00000700,	SRFL_PRSIGN,	SROM8_RXPO52G,		0x00ff},
++	{"rxpo5g",	0x00000700,	SRFL_PRSIGN,	SROM8_RXPO52G,		0xff00},
++	{"txchain",	0x000000f0,	SRFL_NOFFS,	SROM4_TXRXC,		SROM4_TXCHAIN_MASK},
++	{"rxchain",	0x000000f0,	SRFL_NOFFS,	SROM4_TXRXC,		SROM4_RXCHAIN_MASK},
++	{"antswitch",	0x000000f0,	SRFL_NOFFS,	SROM4_TXRXC,		SROM4_SWITCH_MASK},
++	{"txchain",	0x00000700,	SRFL_NOFFS,	SROM8_TXRXC,		SROM4_TXCHAIN_MASK},
++	{"rxchain",	0x00000700,	SRFL_NOFFS,	SROM8_TXRXC,		SROM4_RXCHAIN_MASK},
++	{"antswitch",	0x00000700,	SRFL_NOFFS,	SROM8_TXRXC,		SROM4_SWITCH_MASK},
++	{"tssipos2g",	0x00000700,	0,		SROM8_FEM2G,	SROM8_FEM_TSSIPOS_MASK},
++	{"extpagain2g",	0x00000700,	0,		SROM8_FEM2G,	SROM8_FEM_EXTPA_GAIN_MASK},
++	{"pdetrange2g",	0x00000700,	0,		SROM8_FEM2G,	SROM8_FEM_PDET_RANGE_MASK},
++	{"triso2g",	0x00000700,	0,		SROM8_FEM2G,	SROM8_FEM_TR_ISO_MASK},
++	{"antswctl2g",	0x00000700,	0,		SROM8_FEM2G,	SROM8_FEM_ANTSWLUT_MASK},
++	{"tssipos5g",	0x00000700,	0,		SROM8_FEM5G,	SROM8_FEM_TSSIPOS_MASK},
++	{"extpagain5g",	0x00000700,	0,		SROM8_FEM5G,	SROM8_FEM_EXTPA_GAIN_MASK},
++	{"pdetrange5g",	0x00000700,	0,		SROM8_FEM5G,	SROM8_FEM_PDET_RANGE_MASK},
++	{"triso5g",	0x00000700,	0,		SROM8_FEM5G,	SROM8_FEM_TR_ISO_MASK},
++	{"antswctl5g",	0x00000700,	0,		SROM8_FEM5G,	SROM8_FEM_ANTSWLUT_MASK},
++	{"txpid2ga0",	0x000000f0,	0,		SROM4_TXPID2G,		0x00ff},
++	{"txpid2ga1",	0x000000f0,	0,		SROM4_TXPID2G,		0xff00},
++	{"txpid2ga2",	0x000000f0,	0,		SROM4_TXPID2G + 1,	0x00ff},
++	{"txpid2ga3",	0x000000f0,	0,		SROM4_TXPID2G + 1,	0xff00},
++	{"txpid5ga0",	0x000000f0,	0,		SROM4_TXPID5G,		0x00ff},
++	{"txpid5ga1",	0x000000f0,	0,		SROM4_TXPID5G,		0xff00},
++	{"txpid5ga2",	0x000000f0,	0,		SROM4_TXPID5G + 1,	0x00ff},
++	{"txpid5ga3",	0x000000f0,	0,		SROM4_TXPID5G + 1,	0xff00},
++	{"txpid5gla0",	0x000000f0,	0,		SROM4_TXPID5GL,		0x00ff},
++	{"txpid5gla1",	0x000000f0,	0,		SROM4_TXPID5GL,		0xff00},
++	{"txpid5gla2",	0x000000f0,	0,		SROM4_TXPID5GL + 1,	0x00ff},
++	{"txpid5gla3",	0x000000f0,	0,		SROM4_TXPID5GL + 1,	0xff00},
++	{"txpid5gha0",	0x000000f0,	0,		SROM4_TXPID5GH,		0x00ff},
++	{"txpid5gha1",	0x000000f0,	0,		SROM4_TXPID5GH,		0xff00},
++	{"txpid5gha2",	0x000000f0,	0,		SROM4_TXPID5GH + 1,	0x00ff},
++	{"txpid5gha3",	0x000000f0,	0,		SROM4_TXPID5GH + 1,	0xff00},
++
++	{"ccode",	0x0000000f,	SRFL_CCODE,	SROM_CCODE,		0xffff},
++	{"ccode",	0x00000010,	SRFL_CCODE,	SROM4_CCODE,		0xffff},
++	{"ccode",	0x000000e0,	SRFL_CCODE,	SROM5_CCODE,		0xffff},
++	{"ccode",	0x00000700,	SRFL_CCODE,	SROM8_CCODE,		0xffff},
++	{"macaddr",	0x00000700,	SRFL_ETHADDR,	SROM8_MACHI,		0xffff},
++	{"macaddr",	0x000000e0,	SRFL_ETHADDR,	SROM5_MACHI,		0xffff},
++	{"macaddr",	0x00000010,	SRFL_ETHADDR,	SROM4_MACHI,		0xffff},
++	{"macaddr",	0x00000008,	SRFL_ETHADDR,	SROM3_MACHI,		0xffff},
++	{"il0macaddr",	0x00000007,	SRFL_ETHADDR,	SROM_MACHI_IL0,		0xffff},
++	{"et1macaddr",	0x00000007,	SRFL_ETHADDR,	SROM_MACHI_ET1,		0xffff},
++	{"leddc",	0x00000700,	SRFL_NOFFS|SRFL_LEDDC,	SROM8_LEDDC,	0xffff},
++	{"leddc",	0x000000e0,	SRFL_NOFFS|SRFL_LEDDC,	SROM5_LEDDC,	0xffff},
++	{"leddc",	0x00000010,	SRFL_NOFFS|SRFL_LEDDC,	SROM4_LEDDC,	0xffff},
++	{"leddc",	0x00000008,	SRFL_NOFFS|SRFL_LEDDC,	SROM3_LEDDC,	0xffff},
++
++	{"tempthresh",	0x00000700,	0,		SROM8_THERMAL,		0xff00},
++	{"tempoffset",	0x00000700,	0,		SROM8_THERMAL,		0x00ff},
++	{"rawtempsense", 0x00000700,	SRFL_PRHEX,	SROM8_MPWR_RAWTS,	0x01ff},
++	{"measpower",	0x00000700,	SRFL_PRHEX,	SROM8_MPWR_RAWTS,	0xfe00},
++	{"tempsense_slope",	0x00000700,	SRFL_PRHEX, 	SROM8_TS_SLP_OPT_CORRX,	0x00ff},
++	{"tempcorrx",	0x00000700,	SRFL_PRHEX, 	SROM8_TS_SLP_OPT_CORRX,	0xfc00},
++	{"tempsense_option",	0x00000700,	SRFL_PRHEX,	SROM8_TS_SLP_OPT_CORRX,	0x0300},
++	{"freqoffset_corr",	0x00000700,	SRFL_PRHEX,	SROM8_FOC_HWIQ_IQSWP,	0x000f},
++	{"iqcal_swp_dis",	0x00000700,	SRFL_PRHEX,	SROM8_FOC_HWIQ_IQSWP,	0x0010},
++	{"hw_iqcal_en",	0x00000700,	SRFL_PRHEX,	SROM8_FOC_HWIQ_IQSWP,	0x0020},
++	{"elna2g",      0x00000700,     0,              SROM8_EXTLNAGAIN,       0x00ff},
++	{"elna5g",      0x00000700,     0,              SROM8_EXTLNAGAIN,       0xff00},
++	{"phycal_tempdelta",	0x00000700,	0,	SROM8_PHYCAL_TEMPDELTA,	0x00ff},
++	{"temps_period",	0x00000700,	0,	SROM8_PHYCAL_TEMPDELTA,	0x0f00},
++	{"temps_hysteresis",	0x00000700,	0,	SROM8_PHYCAL_TEMPDELTA,	0xf000},
++	{"measpower1", 0x00000700,	SRFL_PRHEX, SROM8_MPWR_1_AND_2, 	0x007f},
++	{"measpower2",	0x00000700, 	SRFL_PRHEX, SROM8_MPWR_1_AND_2, 	0x3f80},
++
++	{"cck2gpo",	0x000000f0,	0,		SROM4_2G_CCKPO,		0xffff},
++	{"cck2gpo",	0x00000100,	0,		SROM8_2G_CCKPO,		0xffff},
++	{"ofdm2gpo",	0x000000f0,	SRFL_MORE,	SROM4_2G_OFDMPO,	0xffff},
++	{"",		0,		0,		SROM4_2G_OFDMPO + 1,	0xffff},
++	{"ofdm5gpo",	0x000000f0,	SRFL_MORE,	SROM4_5G_OFDMPO,	0xffff},
++	{"",		0,		0,		SROM4_5G_OFDMPO + 1,	0xffff},
++	{"ofdm5glpo",	0x000000f0,	SRFL_MORE,	SROM4_5GL_OFDMPO,	0xffff},
++	{"",		0,		0,		SROM4_5GL_OFDMPO + 1,	0xffff},
++	{"ofdm5ghpo",	0x000000f0,	SRFL_MORE,	SROM4_5GH_OFDMPO,	0xffff},
++	{"",		0,		0,		SROM4_5GH_OFDMPO + 1,	0xffff},
++	{"ofdm2gpo",	0x00000100,	SRFL_MORE,	SROM8_2G_OFDMPO,	0xffff},
++	{"",		0,		0,		SROM8_2G_OFDMPO + 1,	0xffff},
++	{"ofdm5gpo",	0x00000100,	SRFL_MORE,	SROM8_5G_OFDMPO,	0xffff},
++	{"",		0,		0,		SROM8_5G_OFDMPO + 1,	0xffff},
++	{"ofdm5glpo",	0x00000100,	SRFL_MORE,	SROM8_5GL_OFDMPO,	0xffff},
++	{"",		0,		0,		SROM8_5GL_OFDMPO + 1,	0xffff},
++	{"ofdm5ghpo",	0x00000100,	SRFL_MORE,	SROM8_5GH_OFDMPO,	0xffff},
++	{"",		0,		0,		SROM8_5GH_OFDMPO + 1,	0xffff},
++	{"mcs2gpo0",	0x000000f0,	0,		SROM4_2G_MCSPO,		0xffff},
++	{"mcs2gpo1",	0x000000f0,	0,		SROM4_2G_MCSPO + 1,	0xffff},
++	{"mcs2gpo2",	0x000000f0,	0,		SROM4_2G_MCSPO + 2,	0xffff},
++	{"mcs2gpo3",	0x000000f0,	0,		SROM4_2G_MCSPO + 3,	0xffff},
++	{"mcs2gpo4",	0x000000f0,	0,		SROM4_2G_MCSPO + 4,	0xffff},
++	{"mcs2gpo5",	0x000000f0,	0,		SROM4_2G_MCSPO + 5,	0xffff},
++	{"mcs2gpo6",	0x000000f0,	0,		SROM4_2G_MCSPO + 6,	0xffff},
++	{"mcs2gpo7",	0x000000f0,	0,		SROM4_2G_MCSPO + 7,	0xffff},
++	{"mcs5gpo0",	0x000000f0,	0,		SROM4_5G_MCSPO,		0xffff},
++	{"mcs5gpo1",	0x000000f0,	0,		SROM4_5G_MCSPO + 1,	0xffff},
++	{"mcs5gpo2",	0x000000f0,	0,		SROM4_5G_MCSPO + 2,	0xffff},
++	{"mcs5gpo3",	0x000000f0,	0,		SROM4_5G_MCSPO + 3,	0xffff},
++	{"mcs5gpo4",	0x000000f0,	0,		SROM4_5G_MCSPO + 4,	0xffff},
++	{"mcs5gpo5",	0x000000f0,	0,		SROM4_5G_MCSPO + 5,	0xffff},
++	{"mcs5gpo6",	0x000000f0,	0,		SROM4_5G_MCSPO + 6,	0xffff},
++	{"mcs5gpo7",	0x000000f0,	0,		SROM4_5G_MCSPO + 7,	0xffff},
++	{"mcs5glpo0",	0x000000f0,	0,		SROM4_5GL_MCSPO,	0xffff},
++	{"mcs5glpo1",	0x000000f0,	0,		SROM4_5GL_MCSPO + 1,	0xffff},
++	{"mcs5glpo2",	0x000000f0,	0,		SROM4_5GL_MCSPO + 2,	0xffff},
++	{"mcs5glpo3",	0x000000f0,	0,		SROM4_5GL_MCSPO + 3,	0xffff},
++	{"mcs5glpo4",	0x000000f0,	0,		SROM4_5GL_MCSPO + 4,	0xffff},
++	{"mcs5glpo5",	0x000000f0,	0,		SROM4_5GL_MCSPO + 5,	0xffff},
++	{"mcs5glpo6",	0x000000f0,	0,		SROM4_5GL_MCSPO + 6,	0xffff},
++	{"mcs5glpo7",	0x000000f0,	0,		SROM4_5GL_MCSPO + 7,	0xffff},
++	{"mcs5ghpo0",	0x000000f0,	0,		SROM4_5GH_MCSPO,	0xffff},
++	{"mcs5ghpo1",	0x000000f0,	0,		SROM4_5GH_MCSPO + 1,	0xffff},
++	{"mcs5ghpo2",	0x000000f0,	0,		SROM4_5GH_MCSPO + 2,	0xffff},
++	{"mcs5ghpo3",	0x000000f0,	0,		SROM4_5GH_MCSPO + 3,	0xffff},
++	{"mcs5ghpo4",	0x000000f0,	0,		SROM4_5GH_MCSPO + 4,	0xffff},
++	{"mcs5ghpo5",	0x000000f0,	0,		SROM4_5GH_MCSPO + 5,	0xffff},
++	{"mcs5ghpo6",	0x000000f0,	0,		SROM4_5GH_MCSPO + 6,	0xffff},
++	{"mcs5ghpo7",	0x000000f0,	0,		SROM4_5GH_MCSPO + 7,	0xffff},
++	{"mcs2gpo0",	0x00000100,	0,		SROM8_2G_MCSPO,		0xffff},
++	{"mcs2gpo1",	0x00000100,	0,		SROM8_2G_MCSPO + 1,	0xffff},
++	{"mcs2gpo2",	0x00000100,	0,		SROM8_2G_MCSPO + 2,	0xffff},
++	{"mcs2gpo3",	0x00000100,	0,		SROM8_2G_MCSPO + 3,	0xffff},
++	{"mcs2gpo4",	0x00000100,	0,		SROM8_2G_MCSPO + 4,	0xffff},
++	{"mcs2gpo5",	0x00000100,	0,		SROM8_2G_MCSPO + 5,	0xffff},
++	{"mcs2gpo6",	0x00000100,	0,		SROM8_2G_MCSPO + 6,	0xffff},
++	{"mcs2gpo7",	0x00000100,	0,		SROM8_2G_MCSPO + 7,	0xffff},
++	{"mcs5gpo0",	0x00000100,	0,		SROM8_5G_MCSPO,		0xffff},
++	{"mcs5gpo1",	0x00000100,	0,		SROM8_5G_MCSPO + 1,	0xffff},
++	{"mcs5gpo2",	0x00000100,	0,		SROM8_5G_MCSPO + 2,	0xffff},
++	{"mcs5gpo3",	0x00000100,	0,		SROM8_5G_MCSPO + 3,	0xffff},
++	{"mcs5gpo4",	0x00000100,	0,		SROM8_5G_MCSPO + 4,	0xffff},
++	{"mcs5gpo5",	0x00000100,	0,		SROM8_5G_MCSPO + 5,	0xffff},
++	{"mcs5gpo6",	0x00000100,	0,		SROM8_5G_MCSPO + 6,	0xffff},
++	{"mcs5gpo7",	0x00000100,	0,		SROM8_5G_MCSPO + 7,	0xffff},
++	{"mcs5glpo0",	0x00000100,	0,		SROM8_5GL_MCSPO,	0xffff},
++	{"mcs5glpo1",	0x00000100,	0,		SROM8_5GL_MCSPO + 1,	0xffff},
++	{"mcs5glpo2",	0x00000100,	0,		SROM8_5GL_MCSPO + 2,	0xffff},
++	{"mcs5glpo3",	0x00000100,	0,		SROM8_5GL_MCSPO + 3,	0xffff},
++	{"mcs5glpo4",	0x00000100,	0,		SROM8_5GL_MCSPO + 4,	0xffff},
++	{"mcs5glpo5",	0x00000100,	0,		SROM8_5GL_MCSPO + 5,	0xffff},
++	{"mcs5glpo6",	0x00000100,	0,		SROM8_5GL_MCSPO + 6,	0xffff},
++	{"mcs5glpo7",	0x00000100,	0,		SROM8_5GL_MCSPO + 7,	0xffff},
++	{"mcs5ghpo0",	0x00000100,	0,		SROM8_5GH_MCSPO,	0xffff},
++	{"mcs5ghpo1",	0x00000100,	0,		SROM8_5GH_MCSPO + 1,	0xffff},
++	{"mcs5ghpo2",	0x00000100,	0,		SROM8_5GH_MCSPO + 2,	0xffff},
++	{"mcs5ghpo3",	0x00000100,	0,		SROM8_5GH_MCSPO + 3,	0xffff},
++	{"mcs5ghpo4",	0x00000100,	0,		SROM8_5GH_MCSPO + 4,	0xffff},
++	{"mcs5ghpo5",	0x00000100,	0,		SROM8_5GH_MCSPO + 5,	0xffff},
++	{"mcs5ghpo6",	0x00000100,	0,		SROM8_5GH_MCSPO + 6,	0xffff},
++	{"mcs5ghpo7",	0x00000100,	0,		SROM8_5GH_MCSPO + 7,	0xffff},
++	{"cddpo",	0x000000f0,	0,		SROM4_CDDPO,		0xffff},
++	{"stbcpo",	0x000000f0,	0,		SROM4_STBCPO,		0xffff},
++	{"bw40po",	0x000000f0,	0,		SROM4_BW40PO,		0xffff},
++	{"bwduppo",	0x000000f0,	0,		SROM4_BWDUPPO,		0xffff},
++	{"cddpo",	0x00000100,	0,		SROM8_CDDPO,		0xffff},
++	{"stbcpo",	0x00000100,	0,		SROM8_STBCPO,		0xffff},
++	{"bw40po",	0x00000100,	0,		SROM8_BW40PO,		0xffff},
++	{"bwduppo",	0x00000100,	0,		SROM8_BWDUPPO,		0xffff},
++
++	/* power per rate from sromrev 9 */
++	{"cckbw202gpo",		0x00000600,	0,	SROM9_2GPO_CCKBW20,		0xffff},
++	{"cckbw20ul2gpo",	0x00000600,	0,	SROM9_2GPO_CCKBW20UL,		0xffff},
++	{"legofdmbw202gpo",	0x00000600,	SRFL_MORE, SROM9_2GPO_LOFDMBW20,	0xffff},
++	{"",			0,		0,	SROM9_2GPO_LOFDMBW20 + 1,	0xffff},
++	{"legofdmbw20ul2gpo",	0x00000600,	SRFL_MORE, SROM9_2GPO_LOFDMBW20UL,	0xffff},
++	{"",			0,		0,	SROM9_2GPO_LOFDMBW20UL + 1,	0xffff},
++	{"legofdmbw205glpo",	0x00000600,	SRFL_MORE, SROM9_5GLPO_LOFDMBW20,	0xffff},
++	{"",			0,		0,	SROM9_5GLPO_LOFDMBW20 + 1,	0xffff},
++	{"legofdmbw20ul5glpo",	0x00000600,	SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL,	0xffff},
++	{"",			0,		0,	SROM9_5GLPO_LOFDMBW20UL + 1,	0xffff},
++	{"legofdmbw205gmpo",	0x00000600,	SRFL_MORE, SROM9_5GMPO_LOFDMBW20,	0xffff},
++	{"",			0,		0,	SROM9_5GMPO_LOFDMBW20 + 1,	0xffff},
++	{"legofdmbw20ul5gmpo",	0x00000600,	SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL,	0xffff},
++	{"",			0,		0,	SROM9_5GMPO_LOFDMBW20UL + 1,	0xffff},
++	{"legofdmbw205ghpo",	0x00000600,	SRFL_MORE, SROM9_5GHPO_LOFDMBW20,	0xffff},
++	{"",			0,		0,	SROM9_5GHPO_LOFDMBW20 + 1,	0xffff},
++	{"legofdmbw20ul5ghpo",	0x00000600,	SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL,	0xffff},
++	{"",			0,		0,	SROM9_5GHPO_LOFDMBW20UL + 1,	0xffff},
++	{"mcsbw202gpo",		0x00000600,	SRFL_MORE, SROM9_2GPO_MCSBW20,		0xffff},
++	{"",			0,		0,	SROM9_2GPO_MCSBW20 + 1,		0xffff},
++	{"mcsbw20ul2gpo",      	0x00000600,	SRFL_MORE, SROM9_2GPO_MCSBW20UL,	0xffff},
++	{"",			0,		0,	SROM9_2GPO_MCSBW20UL + 1,	0xffff},
++	{"mcsbw402gpo",		0x00000600,	SRFL_MORE, SROM9_2GPO_MCSBW40,		0xffff},
++	{"",			0,		0,	SROM9_2GPO_MCSBW40 + 1,		0xffff},
++	{"mcsbw205glpo",	0x00000600,	SRFL_MORE, SROM9_5GLPO_MCSBW20,		0xffff},
++	{"",			0,		0,	SROM9_5GLPO_MCSBW20 + 1,	0xffff},
++	{"mcsbw20ul5glpo",	0x00000600,	SRFL_MORE, SROM9_5GLPO_MCSBW20UL,	0xffff},
++	{"",			0,		0,	SROM9_5GLPO_MCSBW20UL + 1,	0xffff},
++	{"mcsbw405glpo",	0x00000600,	SRFL_MORE, SROM9_5GLPO_MCSBW40,		0xffff},
++	{"",			0,		0,	SROM9_5GLPO_MCSBW40 + 1,	0xffff},
++	{"mcsbw205gmpo",	0x00000600,	SRFL_MORE, SROM9_5GMPO_MCSBW20,		0xffff},
++	{"",			0,		0,	SROM9_5GMPO_MCSBW20 + 1,	0xffff},
++	{"mcsbw20ul5gmpo",	0x00000600,	SRFL_MORE, SROM9_5GMPO_MCSBW20UL,	0xffff},
++	{"",			0,		0,	SROM9_5GMPO_MCSBW20UL + 1,	0xffff},
++	{"mcsbw405gmpo",	0x00000600,	SRFL_MORE, SROM9_5GMPO_MCSBW40,		0xffff},
++	{"",			0,		0,	SROM9_5GMPO_MCSBW40 + 1,	0xffff},
++	{"mcsbw205ghpo",	0x00000600,	SRFL_MORE, SROM9_5GHPO_MCSBW20,		0xffff},
++	{"",			0,		0,	SROM9_5GHPO_MCSBW20 + 1,	0xffff},
++	{"mcsbw20ul5ghpo",	0x00000600,	SRFL_MORE, SROM9_5GHPO_MCSBW20UL,	0xffff},
++	{"",			0,		0,	SROM9_5GHPO_MCSBW20UL + 1,	0xffff},
++	{"mcsbw405ghpo",	0x00000600,	SRFL_MORE, SROM9_5GHPO_MCSBW40,		0xffff},
++	{"",			0,		0,	SROM9_5GHPO_MCSBW40 + 1,	0xffff},
++	{"mcs32po",		0x00000600,	0,	SROM9_PO_MCS32,			0xffff},
++	{"legofdm40duppo",	0x00000600,	0,	SROM9_PO_LOFDM40DUP,	0xffff},
++	{"pcieingress_war",	0x00000700,	0,	SROM8_PCIEINGRESS_WAR,	0xf},
++	{"eu_edthresh2g",	0x00000100,	0,	SROM8_EU_EDCRSTH,		0x00ff},
++	{"eu_edthresh5g",	0x00000100,	0,	SROM8_EU_EDCRSTH,		0xff00},
++	{"eu_edthresh2g",	0x00000200,	0,	SROM9_EU_EDCRSTH,		0x00ff},
++	{"eu_edthresh5g",	0x00000200,	0,	SROM9_EU_EDCRSTH,		0xff00},
++	{"rxgainerr2ga0",	0x00000700,	0,	SROM8_RXGAINERR_2G,		0x003f},
++	{"rxgainerr2ga0",	0x00000700,	0,	SROM8_RXGAINERR_2G,		0x003f},
++	{"rxgainerr2ga1",	0x00000700,	0,	SROM8_RXGAINERR_2G,		0x07c0},
++	{"rxgainerr2ga2",	0x00000700,	0,	SROM8_RXGAINERR_2G,		0xf800},
++	{"rxgainerr5gla0",	0x00000700,	0,	SROM8_RXGAINERR_5GL,	0x003f},
++	{"rxgainerr5gla1",	0x00000700,	0,	SROM8_RXGAINERR_5GL,	0x07c0},
++	{"rxgainerr5gla2",	0x00000700,	0,	SROM8_RXGAINERR_5GL,	0xf800},
++	{"rxgainerr5gma0",	0x00000700,	0,	SROM8_RXGAINERR_5GM,	0x003f},
++	{"rxgainerr5gma1",	0x00000700,	0,	SROM8_RXGAINERR_5GM,	0x07c0},
++	{"rxgainerr5gma2",	0x00000700,	0,	SROM8_RXGAINERR_5GM,	0xf800},
++	{"rxgainerr5gha0",	0x00000700,	0,	SROM8_RXGAINERR_5GH,	0x003f},
++	{"rxgainerr5gha1",	0x00000700,	0,	SROM8_RXGAINERR_5GH,	0x07c0},
++	{"rxgainerr5gha2",	0x00000700,	0,	SROM8_RXGAINERR_5GH,	0xf800},
++	{"rxgainerr5gua0",	0x00000700,	0,	SROM8_RXGAINERR_5GU,	0x003f},
++	{"rxgainerr5gua1",	0x00000700,	0,	SROM8_RXGAINERR_5GU,	0x07c0},
++	{"rxgainerr5gua2",	0x00000700,	0,	SROM8_RXGAINERR_5GU,	0xf800},
++	{"sar2g",       	0x00000600,	0,	SROM9_SAR,          	0x00ff},
++	{"sar5g",           0x00000600,	0,	SROM9_SAR,	            0xff00},
++	{"noiselvl2ga0",	0x00000700,	0,	SROM8_NOISELVL_2G,		0x001f},
++	{"noiselvl2ga1",	0x00000700,	0,	SROM8_NOISELVL_2G,		0x03e0},
++	{"noiselvl2ga2",	0x00000700,	0,	SROM8_NOISELVL_2G,		0x7c00},
++	{"noiselvl5gla0",	0x00000700,	0,	SROM8_NOISELVL_5GL,		0x001f},
++	{"noiselvl5gla1",	0x00000700,	0,	SROM8_NOISELVL_5GL,		0x03e0},
++	{"noiselvl5gla2",	0x00000700,	0,	SROM8_NOISELVL_5GL,		0x7c00},
++	{"noiselvl5gma0",	0x00000700,	0,	SROM8_NOISELVL_5GM,		0x001f},
++	{"noiselvl5gma1",	0x00000700,	0,	SROM8_NOISELVL_5GM,		0x03e0},
++	{"noiselvl5gma2",	0x00000700,	0,	SROM8_NOISELVL_5GM,		0x7c00},
++	{"noiselvl5gha0",	0x00000700,	0,	SROM8_NOISELVL_5GH,		0x001f},
++	{"noiselvl5gha1",	0x00000700,	0,	SROM8_NOISELVL_5GH,		0x03e0},
++	{"noiselvl5gha2",	0x00000700,	0,	SROM8_NOISELVL_5GH,		0x7c00},
++	{"noiselvl5gua0",	0x00000700,	0,	SROM8_NOISELVL_5GU,		0x001f},
++	{"noiselvl5gua1",	0x00000700,	0,	SROM8_NOISELVL_5GU,		0x03e0},
++	{"noiselvl5gua2",	0x00000700,	0,	SROM8_NOISELVL_5GU,		0x7c00},
++	{"noisecaloffset",	0x00000300,	0,	SROM8_NOISECALOFFSET,		0x00ff},
++	{"noisecaloffset5g",	0x00000300,	0,	SROM8_NOISECALOFFSET,		0xff00},
++	{"subband5gver",	0x00000700,	0,	SROM8_SUBBAND_PPR,		0x7},
++
++	{"cckPwrOffset",	0x00000400,	0,	SROM10_CCKPWROFFSET,		0xffff},
++	{"eu_edthresh2g",	0x00000400,	0,	SROM10_EU_EDCRSTH,		0x00ff},
++	{"eu_edthresh5g",	0x00000400,	0,	SROM10_EU_EDCRSTH,		0xff00},
++	/* swctrlmap_2g array, note that the last element doesn't have SRFL_ARRAY flag set */
++	{"swctrlmap_2g", 0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G, 0xffff},
++	{"",	0x00000400, SRFL_ARRAY,	SROM10_SWCTRLMAP_2G + 1,			0xffff},
++	{"",	0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 2, 	0xffff},
++	{"",	0x00000400, SRFL_ARRAY,	SROM10_SWCTRLMAP_2G + 3,			0xffff},
++	{"",	0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 4,	0xffff},
++	{"",	0x00000400, SRFL_ARRAY,	SROM10_SWCTRLMAP_2G + 5,			0xffff},
++	{"",	0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 6,	0xffff},
++	{"",	0x00000400, SRFL_ARRAY,	SROM10_SWCTRLMAP_2G + 7,			0xffff},
++	{"",	0x00000400, SRFL_PRHEX,	SROM10_SWCTRLMAP_2G + 8,			0xffff},
++
++	/* sromrev 11 */
++	{"boardflags3",	0xfffff800,	SRFL_PRHEX|SRFL_MORE,	SROM11_BFL4,	0xffff},
++	{"",		0,		0,			SROM11_BFL5,	0xffff},
++	{"boardnum",	0xfffff800,	0,			SROM11_MACLO,	0xffff},
++	{"macaddr",	0xfffff800,	SRFL_ETHADDR,		SROM11_MACHI,	0xffff},
++	{"ccode",	0xfffff800,	SRFL_CCODE,		SROM11_CCODE,	0xffff},
++	{"regrev",	0xfffff800,	0,			SROM11_REGREV,	0xffff},
++	{"ledbh0",	0xfffff800,	SRFL_NOFFS,		SROM11_LEDBH10,	0x00ff},
++	{"ledbh1",	0xfffff800,	SRFL_NOFFS,		SROM11_LEDBH10,	0xff00},
++	{"ledbh2",	0xfffff800,	SRFL_NOFFS,		SROM11_LEDBH32,	0x00ff},
++	{"ledbh3",	0xfffff800,	SRFL_NOFFS,		SROM11_LEDBH32,	0xff00},
++	{"leddc",	0xfffff800,	SRFL_NOFFS|SRFL_LEDDC,	SROM11_LEDDC,	0xffff},
++	{"aa2g",	0xfffff800,	0,			SROM11_AA,	0x00ff},
++	{"aa5g",	0xfffff800,	0,			SROM11_AA,	0xff00},
++	{"agbg0",	0xfffff800,	0,			SROM11_AGBG10,  0xff00},
++	{"agbg1",	0xfffff800,	0,			SROM11_AGBG10,	0x00ff},
++	{"agbg2",	0xfffff800,	0,			SROM11_AGBG2A0,	0xff00},
++	{"aga0",	0xfffff800,	0,			SROM11_AGBG2A0,	0x00ff},
++	{"aga1",	0xfffff800,	0,			SROM11_AGA21,   0xff00},
++	{"aga2",	0xfffff800,	0,			SROM11_AGA21,	0x00ff},
++	{"txchain",	0xfffff800,	SRFL_NOFFS,	SROM11_TXRXC,	SROM4_TXCHAIN_MASK},
++	{"rxchain",	0xfffff800,	SRFL_NOFFS,	SROM11_TXRXC,	SROM4_RXCHAIN_MASK},
++	{"antswitch",	0xfffff800,	SRFL_NOFFS,	SROM11_TXRXC,	SROM4_SWITCH_MASK},
++
++	{"tssiposslope2g",	0xfffff800,	0,		SROM11_FEM_CFG1, 	0x0001},
++	{"epagain2g",		0xfffff800,	0,		SROM11_FEM_CFG1, 	0x000e},
++	{"pdgain2g",		0xfffff800,	0,		SROM11_FEM_CFG1, 	0x01f0},
++	{"tworangetssi2g",	0xfffff800,	0,		SROM11_FEM_CFG1, 	0x0200},
++	{"papdcap2g",		0xfffff800,	0,		SROM11_FEM_CFG1, 	0x0400},
++	{"femctrl",		0xfffff800,	0,		SROM11_FEM_CFG1, 	0xf800},
++
++	{"tssiposslope5g",	0xfffff800,	0,		SROM11_FEM_CFG2, 	0x0001},
++	{"epagain5g",		0xfffff800,	0,		SROM11_FEM_CFG2, 	0x000e},
++	{"pdgain5g",		0xfffff800,	0,		SROM11_FEM_CFG2, 	0x01f0},
++	{"tworangetssi5g",	0xfffff800,	0,		SROM11_FEM_CFG2, 	0x0200},
++	{"papdcap5g",		0xfffff800,	0,		SROM11_FEM_CFG2, 	0x0400},
++	{"gainctrlsph",		0xfffff800,	0,		SROM11_FEM_CFG2, 	0xf800},
++
++	{"tempthresh",		0xfffff800,	0,		SROM11_THERMAL,		0xff00},
++	{"tempoffset",		0xfffff800,	0,		SROM11_THERMAL,		0x00ff},
++	{"rawtempsense", 	0xfffff800,	SRFL_PRHEX,	SROM11_MPWR_RAWTS,	0x01ff},
++	{"measpower",		0xfffff800,	SRFL_PRHEX,	SROM11_MPWR_RAWTS,	0xfe00},
++	{"tempsense_slope",	0xfffff800,	SRFL_PRHEX, 	SROM11_TS_SLP_OPT_CORRX, 0x00ff},
++	{"tempcorrx",		0xfffff800,	SRFL_PRHEX, 	SROM11_TS_SLP_OPT_CORRX, 0xfc00},
++	{"tempsense_option",	0xfffff800,	SRFL_PRHEX,	SROM11_TS_SLP_OPT_CORRX, 0x0300},
++	{"xtalfreq",		0xfffff800,	0,		SROM11_XTAL_FREQ, 	0xffff},
++	{"txpwrbckof",	0x00000800,	SRFL_PRHEX,	SROM11_PATH0 + SROM11_2G_MAXP,	0xff00},
++	/* Special PA Params for 4350 5G Band, 40/80 MHz BW Ant #1 */
++	{"pa5gbw4080a1", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_4080_W0_A1, 0xffff},
++	{"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_4080_W1_A1,                 0xffff},
++	{"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_4080_W2_A1,                 0xffff},
++	{"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_4080_W0_A1,                 0xffff},
++	{"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_4080_PA,     0xffff},
++	{"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_4080_PA + 1, 0xffff},
++	{"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_4080_PA,     0xffff},
++	{"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_4080_PA + 1, 0xffff},
++	{"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_4080_PA + 2, 0xffff},
++	{"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_4080_PA,     0xffff},
++	{"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_4080_PA + 1, 0xffff},
++	{"", 0xfffff800, SRFL_PRHEX,              SROM11_PATH2 + SROM11_5GB3_4080_PA + 2, 0xffff},
++	{"phycal_tempdelta",	0xfffff800,	0,		SROM11_PHYCAL_TEMPDELTA, 0x00ff},
++	{"temps_period",	0xfffff800,	0,		SROM11_PHYCAL_TEMPDELTA, 0x0f00},
++	{"temps_hysteresis",	0xfffff800,	0,		SROM11_PHYCAL_TEMPDELTA, 0xf000},
++	{"measpower1", 		0xfffff800,	SRFL_PRHEX,	SROM11_MPWR_1_AND_2, 	0x007f},
++	{"measpower2",		0xfffff800, 	SRFL_PRHEX,	SROM11_MPWR_1_AND_2, 	0x3f80},
++	{"tssifloor2g",		0xfffff800,	SRFL_PRHEX,	SROM11_TSSIFLOOR_2G,	0x03ff},
++	{"tssifloor5g",	0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_TSSIFLOOR_5GL,	0x03ff},
++	{"",		0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_TSSIFLOOR_5GM,	0x03ff},
++	{"",		0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_TSSIFLOOR_5GH,	0x03ff},
++	{"",		0xfffff800,	SRFL_PRHEX,		SROM11_TSSIFLOOR_5GU,	0x03ff},
++	{"pdoffset2g40ma0",     0xfffff800, 0,      SROM11_PDOFF_2G_40M,    0x000f},
++	{"pdoffset2g40ma1",     0xfffff800, 0,      SROM11_PDOFF_2G_40M,    0x00f0},
++	{"pdoffset2g40ma2",     0xfffff800, 0,      SROM11_PDOFF_2G_40M,    0x0f00},
++	{"pdoffset2g40mvalid",  0xfffff800, 0,      SROM11_PDOFF_2G_40M,    0x8000},
++	{"pdoffset40ma0",      	0xfffff800,	0,		SROM11_PDOFF_40M_A0,   	0xffff},
++	{"pdoffset40ma1",      	0xfffff800,	0,		SROM11_PDOFF_40M_A1,   	0xffff},
++	{"pdoffset40ma2",      	0xfffff800,	0,		SROM11_PDOFF_40M_A2,   	0xffff},
++	{"pdoffset80ma0",      	0xfffff800,	0,		SROM11_PDOFF_80M_A0,   	0xffff},
++	{"pdoffset80ma1",      	0xfffff800,	0,		SROM11_PDOFF_80M_A1,   	0xffff},
++	{"pdoffset80ma2",      	0xfffff800,	0,		SROM11_PDOFF_80M_A2,   	0xffff},
++
++	{"subband5gver",	0xfffff800, 	SRFL_PRHEX,	SROM11_SUBBAND5GVER, 	0xffff},
++	{"paparambwver",	0xfffff800, 	0,		SROM11_MCSLR5GLPO, 	0xf000},
++	{"rx5ggainwar",         0xfffff800,     0,              SROM11_MCSLR5GMPO,      0x2000},
++	/* Special PA Params for 4350 5G Band, 40/80 MHz BW Ant #0 */
++	{"pa5gbw4080a0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 +SROM11_5GB0_PA, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 1, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 2, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA,     0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 1, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 2, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA,     0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 1, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 2, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA,     0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA + 1, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX,              SROM11_PATH2 + SROM11_5GB3_PA + 2, 0xffff},
++	/* Special PA Params for 4335 5G Band, 40 MHz BW */
++	{"pa5gbw40a0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB0_PA, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB0_PA + 1, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB0_PA + 2, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB1_PA,     0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB1_PA + 1, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB1_PA + 2, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB2_PA,     0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB2_PA + 1, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB2_PA + 2, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB3_PA,     0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB3_PA + 1, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX,              SROM11_PATH1 + SROM11_5GB3_PA + 2, 0xffff},
++	/* Special PA Params for 4335 5G Band, 80 MHz BW */
++	{"pa5gbw80a0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 1, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 2, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA,     0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 1, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 2, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA,     0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 1, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 2, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA,     0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA + 1, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX,              SROM11_PATH2 + SROM11_5GB3_PA + 2, 0xffff},
++	/* Special PA Params for 4335 2G Band, CCK */
++	{"pa2gccka0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_2G_PA, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_2G_PA + 1, 0xffff},
++	{"", 0xfffff800,	SRFL_PRHEX,              SROM11_PATH1 + SROM11_2G_PA + 2, 0xffff},
++
++	/* power per rate */
++	{"cckbw202gpo",		0xfffff800,	0,		SROM11_CCKBW202GPO, 	0xffff},
++	{"cckbw20ul2gpo",	0xfffff800,	0,		SROM11_CCKBW20UL2GPO, 	0xffff},
++	{"mcsbw202gpo",		0xfffff800,	SRFL_MORE,	SROM11_MCSBW202GPO,   	0xffff},
++	{"",            	0xfffff800, 	0,          	SROM11_MCSBW202GPO_1, 	0xffff},
++	{"mcsbw402gpo",		0xfffff800,	SRFL_MORE,	SROM11_MCSBW402GPO,   	0xffff},
++	{"",            	0xfffff800, 	0,   		SROM11_MCSBW402GPO_1, 	0xffff},
++	{"dot11agofdmhrbw202gpo", 0xfffff800, 	0, 	SROM11_DOT11AGOFDMHRBW202GPO, 	0xffff},
++	{"ofdmlrbw202gpo",	0xfffff800, 	0, 		SROM11_OFDMLRBW202GPO,	0xffff},
++	{"mcsbw205glpo",	0xfffff800,	SRFL_MORE,	SROM11_MCSBW205GLPO, 	0xffff},
++	{"",           		0xfffff800, 	0,   		SROM11_MCSBW205GLPO_1, 	0xffff},
++	{"mcsbw405glpo",	0xfffff800,	SRFL_MORE,	SROM11_MCSBW405GLPO, 	0xffff},
++	{"",           		0xfffff800, 	0,     		SROM11_MCSBW405GLPO_1, 	0xffff},
++	{"mcsbw805glpo",	0xfffff800,	SRFL_MORE,	SROM11_MCSBW805GLPO, 	0xffff},
++	{"",           		0xfffff800, 	0,    		SROM11_MCSBW805GLPO_1, 	0xffff},
++	{"mcsbw205gmpo",	0xfffff800,	SRFL_MORE,	SROM11_MCSBW205GMPO, 	0xffff},
++	{"",           		0xfffff800, 	0,     		SROM11_MCSBW205GMPO_1, 	0xffff},
++	{"mcsbw405gmpo",	0xfffff800,	SRFL_MORE,	SROM11_MCSBW405GMPO, 	0xffff},
++	{"",           		0xfffff800, 	0,     		SROM11_MCSBW405GMPO_1, 	0xffff},
++	{"mcsbw805gmpo",	0xfffff800,	SRFL_MORE,	SROM11_MCSBW805GMPO, 	0xffff},
++	{"",           		0xfffff800, 	0,   		SROM11_MCSBW805GMPO_1, 	0xffff},
++	{"mcsbw205ghpo",	0xfffff800,	SRFL_MORE,	SROM11_MCSBW205GHPO, 	0xffff},
++	{"",           		0xfffff800, 	0,  		SROM11_MCSBW205GHPO_1, 	0xffff},
++	{"mcsbw405ghpo",	0xfffff800,	SRFL_MORE,	SROM11_MCSBW405GHPO, 	0xffff},
++	{"",           		0xfffff800, 	0,   		SROM11_MCSBW405GHPO_1, 	0xffff},
++	{"mcsbw805ghpo",	0xfffff800,	SRFL_MORE,	SROM11_MCSBW805GHPO, 	0xffff},
++	{"",           		0xfffff800, 	0,    		SROM11_MCSBW805GHPO_1, 	0xffff},
++	{"mcslr5glpo",		0xfffff800,	0,		SROM11_MCSLR5GLPO, 	0x0fff},
++	{"mcslr5gmpo",		0xfffff800,	0,		SROM11_MCSLR5GMPO, 	0xffff},
++	{"mcslr5ghpo",		0xfffff800,	0,		SROM11_MCSLR5GHPO, 	0xffff},
++	{"sb20in40hrpo", 	0xfffff800,	0,	SROM11_SB20IN40HRPO,		0xffff},
++	{"sb20in80and160hr5glpo", 0xfffff800, 	0, 	SROM11_SB20IN80AND160HR5GLPO, 	0xffff},
++	{"sb40and80hr5glpo",	  0xfffff800, 	0,	SROM11_SB40AND80HR5GLPO,	0xffff},
++	{"sb20in80and160hr5gmpo", 0xfffff800, 	0,	SROM11_SB20IN80AND160HR5GMPO, 	0xffff},
++	{"sb40and80hr5gmpo",	  0xfffff800, 	0,	SROM11_SB40AND80HR5GMPO,	0xffff},
++	{"sb20in80and160hr5ghpo", 0xfffff800, 	0,	SROM11_SB20IN80AND160HR5GHPO, 	0xffff},
++	{"sb40and80hr5ghpo",	  0xfffff800, 	0,	SROM11_SB40AND80HR5GHPO,	0xffff},
++	{"sb20in40lrpo",	  0xfffff800, 	0,	SROM11_SB20IN40LRPO,		0xffff},
++	{"sb20in80and160lr5glpo", 0xfffff800, 	0,	SROM11_SB20IN80AND160LR5GLPO, 	0xffff},
++	{"sb40and80lr5glpo",	  0xfffff800, 	0,	SROM11_SB40AND80LR5GLPO,	0xffff},
++	{"sb20in80and160lr5gmpo", 0xfffff800, 	0,	SROM11_SB20IN80AND160LR5GMPO, 	0xffff},
++	{"sb40and80lr5gmpo",	  0xfffff800, 	0,	SROM11_SB40AND80LR5GMPO,	0xffff},
++	{"sb20in80and160lr5ghpo", 0xfffff800, 	0,	SROM11_SB20IN80AND160LR5GHPO, 	0xffff},
++	{"sb40and80lr5ghpo",	  0xfffff800, 	0,	SROM11_SB40AND80LR5GHPO,	0xffff},
++	{"dot11agduphrpo",	  0xfffff800, 	0,	SROM11_DOT11AGDUPHRPO,		0xffff},
++	{"dot11agduplrpo",	  0xfffff800, 	0,	SROM11_DOT11AGDUPLRPO,		0xffff},
++
++	/* Misc */
++	{"sar2g",       	0xfffff800,	0,	SROM11_SAR,          	0x00ff},
++	{"sar5g",           	0xfffff800,	0,	SROM11_SAR,		0xff00},
++
++	{"noiselvl2ga0",	0xfffff800,	0,		SROM11_NOISELVL_2G,	0x001f},
++	{"noiselvl2ga1",	0xfffff800,	0,		SROM11_NOISELVL_2G,	0x03e0},
++	{"noiselvl2ga2",	0xfffff800,	0,		SROM11_NOISELVL_2G,	0x7c00},
++	{"noiselvl5ga0",	0xfffff800,	SRFL_ARRAY,	SROM11_NOISELVL_5GL,	0x001f},
++	{"",			0xfffff800,	SRFL_ARRAY,	SROM11_NOISELVL_5GM,	0x001f},
++	{"",			0xfffff800,	SRFL_ARRAY,	SROM11_NOISELVL_5GH,	0x001f},
++	{"",			0xfffff800,	0,		SROM11_NOISELVL_5GU,	0x001f},
++	{"noiselvl5ga1",	0xfffff800,	SRFL_ARRAY,	SROM11_NOISELVL_5GL,	0x03e0},
++	{"",			0xfffff800,	SRFL_ARRAY,	SROM11_NOISELVL_5GM,	0x03e0},
++	{"",			0xfffff800,	SRFL_ARRAY,	SROM11_NOISELVL_5GH,	0x03e0},
++	{"",			0xfffff800,	0,		SROM11_NOISELVL_5GU,	0x03e0},
++	{"noiselvl5ga2",	0xfffff800,	SRFL_ARRAY,	SROM11_NOISELVL_5GL,	0x7c00},
++	{"",			0xfffff800,	SRFL_ARRAY,	SROM11_NOISELVL_5GM,	0x7c00},
++	{"",			0xfffff800,	SRFL_ARRAY,	SROM11_NOISELVL_5GH,	0x7c00},
++	{"",			0xfffff800,	0,		SROM11_NOISELVL_5GU,	0x7c00},
++	{"eu_edthresh2g",	0x00000800,	0,	        SROM11_EU_EDCRSTH,	0x00ff},
++	{"eu_edthresh5g",	0x00000800,	0,	        SROM11_EU_EDCRSTH,	0xff00},
++
++	{"rxgainerr2ga0", 	0xfffff800, 	0,    		SROM11_RXGAINERR_2G,    0x003f},
++	{"rxgainerr2ga1", 	0xfffff800, 	0,    		SROM11_RXGAINERR_2G,    0x07c0},
++	{"rxgainerr2ga2", 	0xfffff800, 	0,    		SROM11_RXGAINERR_2G,    0xf800},
++	{"rxgainerr5ga0",      	0xfffff800, 	SRFL_ARRAY,    	SROM11_RXGAINERR_5GL,   0x003f},
++	{"",      		0xfffff800, 	SRFL_ARRAY,    	SROM11_RXGAINERR_5GM,   0x003f},
++	{"",      		0xfffff800, 	SRFL_ARRAY,    	SROM11_RXGAINERR_5GH,   0x003f},
++	{"",      		0xfffff800, 	0,    		SROM11_RXGAINERR_5GU,   0x003f},
++	{"rxgainerr5ga1",      	0xfffff800, 	SRFL_ARRAY,    	SROM11_RXGAINERR_5GL,   0x07c0},
++	{"",      		0xfffff800, 	SRFL_ARRAY,    	SROM11_RXGAINERR_5GM,   0x07c0},
++	{"",      		0xfffff800, 	SRFL_ARRAY,    	SROM11_RXGAINERR_5GH,   0x07c0},
++	{"",      		0xfffff800, 	0,    		SROM11_RXGAINERR_5GU,   0x07c0},
++	{"rxgainerr5ga2",      	0xfffff800, 	SRFL_ARRAY,    	SROM11_RXGAINERR_5GL,   0xf800},
++	{"",      		0xfffff800, 	SRFL_ARRAY,    	SROM11_RXGAINERR_5GM,   0xf800},
++	{"",      		0xfffff800, 	SRFL_ARRAY,    	SROM11_RXGAINERR_5GH,   0xf800},
++	{"",      		0xfffff800, 	0,    		SROM11_RXGAINERR_5GU,   0xf800},
++	{"rpcal2g",      	0xfffff800, 	0,		SROM11_RPCAL_2G,        0xffff},
++	{"rpcal5gb0",      	0xfffff800, 	0,		SROM11_RPCAL_5GL,       0xffff},
++	{"rpcal5gb1",      	0xfffff800, 	0,		SROM11_RPCAL_5GM,       0xffff},
++	{"rpcal5gb2",      	0xfffff800, 	0,		SROM11_RPCAL_5GH,       0xffff},
++	{"rpcal5gb3",      	0xfffff800, 	0,		SROM11_RPCAL_5GU,       0xffff},
++	{"txidxcap2g",      	0xfffff800, 	0,		SROM11_TXIDXCAP2G,      0x0ff0},
++	{"txidxcap5g",      	0xfffff800, 	0,		SROM11_TXIDXCAP5G,      0x0ff0},
++	{"pdoffsetcckma0",      0xfffff800,     0,              SROM11_PDOFF_2G_CCK,    0x000f},
++	{"pdoffsetcckma1",      0xfffff800,     0,              SROM11_PDOFF_2G_CCK,    0x00f0},
++	{"pdoffsetcckma2",      0xfffff800,     0,              SROM11_PDOFF_2G_CCK,    0x0f00},
++
++	/* sromrev 12 */
++	{"boardflags4",		0xfffff000,	SRFL_PRHEX|SRFL_MORE,	SROM12_BFL6,	0xffff},
++	{"",	0,	0,			SROM12_BFL7,	0xffff},
++	{"pdoffsetcck",		0xfffff000,	0,      SROM12_PDOFF_2G_CCK,       0xffff},
++	{"pdoffset20in40m5gb0",	0xfffff000,	0,      SROM12_PDOFF_20in40M_5G_B0,    0xffff},
++	{"pdoffset20in40m5gb1", 0xfffff000,	0,      SROM12_PDOFF_20in40M_5G_B1,    0xffff},
++	{"pdoffset20in40m5gb2", 0xfffff000,	0,      SROM12_PDOFF_20in40M_5G_B2,    0xffff},
++	{"pdoffset20in40m5gb3", 0xfffff000,	0,      SROM12_PDOFF_20in40M_5G_B3,    0xffff},
++	{"pdoffset20in40m5gb4", 0xfffff000,	0,      SROM12_PDOFF_20in40M_5G_B4,    0xffff},
++	{"pdoffset40in80m5gb0", 0xfffff000,	0,      SROM12_PDOFF_40in80M_5G_B0,    0xffff},
++	{"pdoffset40in80m5gb1", 0xfffff000,	0,      SROM12_PDOFF_40in80M_5G_B1,    0xffff},
++	{"pdoffset40in80m5gb2", 0xfffff000,	0,      SROM12_PDOFF_40in80M_5G_B2,    0xffff},
++	{"pdoffset40in80m5gb3", 0xfffff000,	0,      SROM12_PDOFF_40in80M_5G_B3,    0xffff},
++	{"pdoffset40in80m5gb4", 0xfffff000,	0,      SROM12_PDOFF_40in80M_5G_B4,    0xffff},
++	{"pdoffset20in80m5gb0", 0xfffff000,	0,      SROM12_PDOFF_20in80M_5G_B0,    0xffff},
++	{"pdoffset20in80m5gb1", 0xfffff000,	0,      SROM12_PDOFF_20in80M_5G_B1,    0xffff},
++	{"pdoffset20in80m5gb2", 0xfffff000,	0,      SROM12_PDOFF_20in80M_5G_B2,    0xffff},
++	{"pdoffset20in80m5gb3", 0xfffff000,	0,      SROM12_PDOFF_20in80M_5G_B3,    0xffff},
++	{"pdoffset20in80m5gb4", 0xfffff000,	0,      SROM12_PDOFF_20in80M_5G_B4,    0xffff},
++
++	{"pdoffset20in40m5gcore3",   0xffffe000, 0,     SROM13_PDOFFSET20IN40M5GCORE3,   0xffff},
++	{"pdoffset20in40m5gcore3_1", 0xffffe000, 0,     SROM13_PDOFFSET20IN40M5GCORE3_1, 0xffff},
++	{"pdoffset20in80m5gcore3",   0xffffe000, 0,     SROM13_PDOFFSET20IN80M5GCORE3,   0xffff},
++	{"pdoffset20in80m5gcore3_1", 0xffffe000, 0,     SROM13_PDOFFSET20IN80M5GCORE3_1, 0xffff},
++	{"pdoffset40in80m5gcore3",   0xffffe000, 0,     SROM13_PDOFFSET40IN80M5GCORE3,   0xffff},
++	{"pdoffset40in80m5gcore3_1", 0xffffe000, 0,     SROM13_PDOFFSET40IN80M5GCORE3_1, 0xffff},
++
++	{"pdoffset20in40m2g",        0xffffe000, 0,     SROM13_PDOFFSET20IN40M2G,        0xffff},
++	{"pdoffset20in40m2gcore3",   0xffffe000, 0,     SROM13_PDOFFSET20IN40M2GCORE3,   0xffff},
++
++	/* power per rate */
++	{"mcsbw205gx1po",       0xfffff000,     SRFL_MORE,      SROM12_MCSBW205GX1PO,   0xffff},
++	{"",                    0xfffff000,     0,              SROM12_MCSBW205GX1PO_1, 0xffff},
++	{"mcsbw405gx1po",       0xfffff000,     SRFL_MORE,      SROM12_MCSBW405GX1PO,   0xffff},
++	{"",                    0xfffff000,     0,              SROM12_MCSBW405GX1PO_1, 0xffff},
++	{"mcsbw805gx1po",       0xfffff000,     SRFL_MORE,      SROM12_MCSBW805GX1PO,   0xffff},
++	{"",                    0xfffff000,     0,              SROM12_MCSBW805GX1PO_1, 0xffff},
++	{"mcsbw205gx2po",       0xfffff000,     SRFL_MORE,      SROM12_MCSBW205GX2PO,   0xffff},
++	{"",                    0xfffff000,     0,              SROM12_MCSBW205GX2PO_1, 0xffff},
++	{"mcsbw405gx2po",       0xfffff000,     SRFL_MORE,      SROM12_MCSBW405GX2PO,   0xffff},
++	{"",                    0xfffff000,     0,              SROM12_MCSBW405GX2PO_1, 0xffff},
++	{"mcsbw805gx2po",       0xfffff000,     SRFL_MORE,      SROM12_MCSBW805GX2PO,   0xffff},
++	{"",                    0xfffff000,     0,              SROM12_MCSBW805GX2PO_1, 0xffff},
++
++	{"sb20in80and160hr5gx1po", 0xfffff000,  0,      SROM12_SB20IN80AND160HR5GX1PO,  0xffff},
++	{"sb40and80hr5gx1po",     0xfffff000,   0,      SROM12_SB40AND80HR5GX1PO,       0xffff},
++	{"sb20in80and160lr5gx1po", 0xfffff000,  0,      SROM12_SB20IN80AND160LR5GX1PO,  0xffff},
++	{"sb40and80hr5gx1po",     0xfffff000,   0,      SROM12_SB40AND80HR5GX1PO,       0xffff},
++	{"sb20in80and160hr5gx2po", 0xfffff000,  0,      SROM12_SB20IN80AND160HR5GX2PO,  0xffff},
++	{"sb40and80hr5gx2po",     0xfffff000,   0,      SROM12_SB40AND80HR5GX2PO,       0xffff},
++	{"sb20in80and160lr5gx2po", 0xfffff000,  0,      SROM12_SB20IN80AND160LR5GX2PO,  0xffff},
++	{"sb40and80hr5gx2po",     0xfffff000,   0,      SROM12_SB40AND80HR5GX2PO,       0xffff},
++
++	{"rxgains5gmelnagaina0",	0xfffff000,	0,       SROM12_RXGAINS10,	0x0007},
++	{"rxgains5gmelnagaina1",	0xfffff000,	0,       SROM12_RXGAINS11,	0x0007},
++	{"rxgains5gmelnagaina2",	0xfffff000,	0,       SROM12_RXGAINS12,	0x0007},
++	{"rxgains5gmtrisoa0",	0xfffff000,	0,       SROM12_RXGAINS10,	0x0078},
++	{"rxgains5gmtrisoa1",	0xfffff000,	0,       SROM12_RXGAINS11,	0x0078},
++	{"rxgains5gmtrisoa2",	0xfffff000,	0,       SROM12_RXGAINS12,	0x0078},
++	{"rxgains5gmtrelnabypa0", 0xfffff000,	0,       SROM12_RXGAINS10,	0x0080},
++	{"rxgains5gmtrelnabypa1", 0xfffff000,	0,       SROM12_RXGAINS11,	0x0080},
++	{"rxgains5gmtrelnabypa2", 0xfffff000,	0,       SROM12_RXGAINS12,	0x0080},
++	{"rxgains5ghelnagaina0",	0xfffff000,	0,       SROM12_RXGAINS10,	0x0700},
++	{"rxgains5ghelnagaina1",	0xfffff000,	0,       SROM12_RXGAINS11,	0x0700},
++	{"rxgains5ghelnagaina2",	0xfffff000,	0,       SROM12_RXGAINS12,	0x0700},
++	{"rxgains5ghtrisoa0",	0xfffff000,	0,	 SROM12_RXGAINS10,	0x7800},
++	{"rxgains5ghtrisoa1",	0xfffff000,	0,	 SROM12_RXGAINS11,	0x7800},
++	{"rxgains5ghtrisoa2",	0xfffff000,	0,	 SROM12_RXGAINS12,	0x7800},
++	{"rxgains5ghtrelnabypa0", 0xfffff000,	0,	 SROM12_RXGAINS10,	0x8000},
++	{"rxgains5ghtrelnabypa1", 0xfffff000,	0,	 SROM12_RXGAINS11,	0x8000},
++	{"rxgains5ghtrelnabypa2", 0xfffff000,	0,	 SROM12_RXGAINS12,	0x8000},
++	{"eu_edthresh2g",	0x00001000,	0,       SROM12_EU_EDCRSTH,	0x00ff},
++	{"eu_edthresh5g",	0x00001000,	0,       SROM12_EU_EDCRSTH,	0xff00},
++
++	{"gpdn",		0xfffff000,	SRFL_PRHEX|SRFL_MORE,	SROM12_GPDN_L,	0xffff},
++	{"",			0,		0,			SROM12_GPDN_H,	0xffff},
++
++	{"rpcal2gcore3",        0xffffe000, 	0,	SROM13_RPCAL2GCORE3,            0x00ff},
++	{"rpcal5gb0core3",      0xffffe000, 	0,	SROM13_RPCAL5GB01CORE3,         0x00ff},
++	{"rpcal5gb1core3",      0xffffe000, 	0,	SROM13_RPCAL5GB01CORE3,         0xff00},
++	{"rpcal5gb2core3",      0xffffe000, 	0,	SROM13_RPCAL5GB23CORE3,         0x00ff},
++	{"rpcal5gb3core3",      0xffffe000, 	0,	SROM13_RPCAL5GB23CORE3,         0xff00},
++
++	{"eu_edthresh2g",       0x00002000,     0,       SROM13_EU_EDCRSTH,     0x00ff},
++	{"eu_edthresh5g",       0x00002000,     0,       SROM13_EU_EDCRSTH,     0xff00},
++
++	{"agbg3",       0xffffe000,     0,              SROM13_ANTGAIN_BANDBGA, 0xff00},
++	{"aga3",        0xffffe000,     0,              SROM13_ANTGAIN_BANDBGA, 0x00ff},
++	{"noiselvl2ga3",        0xffffe000,     0,              SROM13_NOISELVLCORE3,   0x001f},
++	{"noiselvl5ga3",        0xffffe000,     SRFL_ARRAY,     SROM13_NOISELVLCORE3,   0x03e0},
++	{"",                    0xffffe000,     SRFL_ARRAY,     SROM13_NOISELVLCORE3,   0x7c00},
++	{"",                    0xffffe000,     SRFL_ARRAY,     SROM13_NOISELVLCORE3_1, 0x001f},
++	{"",                    0xffffe000,     0,              SROM13_NOISELVLCORE3_1, 0x03e0},
++	{"rxgainerr2ga3",       0xffffe000,     0,              SROM13_RXGAINERRCORE3,  0x001f},
++	{"rxgainerr5ga3",       0xffffe000,     SRFL_ARRAY,     SROM13_RXGAINERRCORE3,  0x03e0},
++	{"",                    0xffffe000,     SRFL_ARRAY,     SROM13_RXGAINERRCORE3,  0x7c00},
++	{"",                    0xffffe000,     SRFL_ARRAY,     SROM13_RXGAINERRCORE3_1, 0x001f},
++	{"",                    0xffffe000,     0,              SROM13_RXGAINERRCORE3_1, 0x03e0},
++	{"rxgains5gmelnagaina3",        0xffffe000,     0,       SROM13_RXGAINS1CORE3,  0x0007},
++	{"rxgains5gmtrisoa3",   0xffffe000,     0,       SROM13_RXGAINS1CORE3,  0x0078},
++	{"rxgains5gmtrelnabypa3", 0xffffe000,   0,       SROM13_RXGAINS1CORE3,  0x0080},
++	{"rxgains5ghelnagaina3",        0xffffe000,     0,       SROM13_RXGAINS1CORE3,  0x0700},
++	{"rxgains5ghtrisoa3",   0xffffe000,     0,       SROM13_RXGAINS1CORE3,  0x7800},
++	{"rxgains5ghtrelnabypa3", 0xffffe000,   0,       SROM13_RXGAINS1CORE3,  0x8000},
++
++	/* power per rate */
++	{"mcs1024qam2gpo",      0xffffe000,     0,           SROM13_MCS1024QAM2GPO,     0xffff},
++	{"mcs1024qam5glpo",     0xffffe000,     SRFL_MORE,   SROM13_MCS1024QAM5GLPO,    0xffff},
++	{"",                    0xffffe000,     0,           SROM13_MCS1024QAM5GLPO_1,  0xffff},
++	{"mcs1024qam5gmpo",     0xffffe000,     SRFL_MORE,   SROM13_MCS1024QAM5GMPO,    0xffff},
++	{"",                    0xffffe000,     0,           SROM13_MCS1024QAM5GMPO_1,  0xffff},
++	{"mcs1024qam5ghpo",     0xffffe000,     SRFL_MORE,   SROM13_MCS1024QAM5GHPO,    0xffff},
++	{"",                    0xffffe000,     0,           SROM13_MCS1024QAM5GHPO_1,  0xffff},
++	{"mcs1024qam5gx1po",    0xffffe000,     SRFL_MORE,   SROM13_MCS1024QAM5GX1PO,   0xffff},
++	{"",                    0xffffe000,     0,           SROM13_MCS1024QAM5GX1PO_1, 0xffff},
++	{"mcs1024qam5gx2po",    0xffffe000,     SRFL_MORE,   SROM13_MCS1024QAM5GX2PO,   0xffff},
++	{"",                    0xffffe000,     0,           SROM13_MCS1024QAM5GX2PO_1, 0xffff},
++
++	{"mcsbw1605glpo",       0xffffe000,     SRFL_MORE,      SROM13_MCSBW1605GLPO,   0xffff},
++	{"",                    0xffffe000,     0,              SROM13_MCSBW1605GLPO_1, 0xffff},
++	{"mcsbw1605gmpo",       0xffffe000,     SRFL_MORE,      SROM13_MCSBW1605GMPO,   0xffff},
++	{"",                    0xffffe000,     0,              SROM13_MCSBW1605GMPO_1, 0xffff},
++	{"mcsbw1605ghpo",       0xffffe000,     SRFL_MORE,      SROM13_MCSBW1605GHPO,   0xffff},
++	{"",                    0xffffe000,     0,              SROM13_MCSBW1605GHPO_1, 0xffff},
++	{"mcsbw1605gx1po",      0xffffe000,     SRFL_MORE,      SROM13_MCSBW1605GX1PO,  0xffff},
++	{"",                    0xffffe000,     0,      SROM13_MCSBW1605GX1PO_1,        0xffff},
++	{"mcsbw1605gx2po",      0xffffe000,     SRFL_MORE,      SROM13_MCSBW1605GX2PO,  0xffff},
++	{"",                    0xffffe000,     0,      SROM13_MCSBW1605GX2PO_1,        0xffff},
++
++	{"ulbpproffs2g",        0xffffe000,     0,      SROM13_ULBPPROFFS2G,            0xffff},
++
++	{"mcs8poexp",           0xffffe000,     SRFL_MORE,    SROM13_MCS8POEXP,         0xffff},
++	{"",                    0xffffe000,     0,            SROM13_MCS8POEXP_1,       0xffff},
++	{"mcs9poexp",           0xffffe000,     SRFL_MORE,    SROM13_MCS9POEXP,         0xffff},
++	{"",                    0xffffe000,     0,            SROM13_MCS9POEXP_1,       0xffff},
++	{"mcs10poexp",          0xffffe000,     SRFL_MORE,    SROM13_MCS10POEXP,        0xffff},
++	{"",                    0xffffe000,     0,            SROM13_MCS10POEXP_1,      0xffff},
++	{"mcs11poexp",          0xffffe000,     SRFL_MORE,    SROM13_MCS11POEXP,        0xffff},
++	{"",                    0xffffe000,     0,            SROM13_MCS11POEXP_1,      0xffff},
++
++	{"ulbpdoffs5gb0a0",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB0A0,         0xffff},
++	{"ulbpdoffs5gb0a1",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB0A1,         0xffff},
++	{"ulbpdoffs5gb0a2",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB0A2,         0xffff},
++	{"ulbpdoffs5gb0a3",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB0A3,         0xffff},
++	{"ulbpdoffs5gb1a0",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB1A0,         0xffff},
++	{"ulbpdoffs5gb1a1",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB1A1,         0xffff},
++	{"ulbpdoffs5gb1a2",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB1A2,         0xffff},
++	{"ulbpdoffs5gb1a3",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB1A3,         0xffff},
++	{"ulbpdoffs5gb2a0",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB2A0,         0xffff},
++	{"ulbpdoffs5gb2a1",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB2A1,         0xffff},
++	{"ulbpdoffs5gb2a2",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB2A2,         0xffff},
++	{"ulbpdoffs5gb2a3",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB2A3,         0xffff},
++	{"ulbpdoffs5gb3a0",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB3A0,         0xffff},
++	{"ulbpdoffs5gb3a1",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB3A1,         0xffff},
++	{"ulbpdoffs5gb3a2",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB3A2,         0xffff},
++	{"ulbpdoffs5gb3a3",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB3A3,         0xffff},
++	{"ulbpdoffs5gb4a0",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB4A0,         0xffff},
++	{"ulbpdoffs5gb4a1",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB4A1,         0xffff},
++	{"ulbpdoffs5gb4a2",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB4A2,         0xffff},
++	{"ulbpdoffs5gb4a3",     0xffffe000,     0,      SROM13_ULBPDOFFS5GB4A3,         0xffff},
++	{"ulbpdoffs2ga0",       0xffffe000,     0,      SROM13_ULBPDOFFS2GA0,           0xffff},
++	{"ulbpdoffs2ga1",       0xffffe000,     0,      SROM13_ULBPDOFFS2GA1,           0xffff},
++	{"ulbpdoffs2ga2",       0xffffe000,     0,      SROM13_ULBPDOFFS2GA2,           0xffff},
++	{"ulbpdoffs2ga3",       0xffffe000,     0,      SROM13_ULBPDOFFS2GA3,           0xffff},
++
++	{"rpcal5gb4",           0xffffe000,     0,      SROM13_RPCAL5GB4,               0xffff},
++
++	{"sb20in40hrlrpox",     0xffffe000,     0,       SROM13_SB20IN40HRLRPOX,        0xffff},
++
++	{"pdoffset20in40m2g",   0xffffe000,     0,      SROM13_PDOFFSET20IN40M2G,       0xffff},
++	{"pdoffset20in40m2gcore3", 0xffffe000,  0,      SROM13_PDOFFSET20IN40M2GCORE3,  0xffff},
++
++	{"pdoffset20in40m5gcore3", 0xffffe000, SRFL_MORE, SROM13_PDOFFSET20IN40M5GCORE3, 0xffff},
++	{"",                    0xffffe000,     0,  SROM13_PDOFFSET20IN40M5GCORE3_1,   0xffff},
++	{"pdoffset40in80m5gcore3", 0xffffe000, SRFL_MORE, SROM13_PDOFFSET40IN80M5GCORE3, 0xffff},
++	{"",                    0xffffe000,     0,  SROM13_PDOFFSET40IN80M5GCORE3_1,   0xffff},
++	{"pdoffset20in80m5gcore3", 0xffffe000, SRFL_MORE, SROM13_PDOFFSET20IN80M5GCORE3, 0xffff},
++	{"",                    0xffffe000,     0,  SROM13_PDOFFSET20IN80M5GCORE3_1,   0xffff},
++
++	{"swctrlmap4_cfg",      0xffffe000,     0,      SROM13_SWCTRLMAP4_CFG,          0xffff},
++	{"swctrlmap4_TX2g_fem3to0", 0xffffe000, 0,      SROM13_SWCTRLMAP4_TX2G_FEM3TO0, 0xffff},
++	{"swctrlmap4_RX2g_fem3to0", 0xffffe000, 0,      SROM13_SWCTRLMAP4_RX2G_FEM3TO0, 0xffff},
++	{"swctrlmap4_RXByp2g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_RXBYP2G_FEM3TO0, 0xffff},
++	{"swctrlmap4_misc2g_fem3to0", 0xffffe000, 0,  SROM13_SWCTRLMAP4_MISC2G_FEM3TO0, 0xffff},
++	{"swctrlmap4_TX5g_fem3to0", 0xffffe000, 0,      SROM13_SWCTRLMAP4_TX5G_FEM3TO0, 0xffff},
++	{"swctrlmap4_RX5g_fem3to0", 0xffffe000, 0,      SROM13_SWCTRLMAP4_RX5G_FEM3TO0, 0xffff},
++	{"swctrlmap4_RXByp5g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_RXBYP5G_FEM3TO0, 0xffff},
++	{"swctrlmap4_misc5g_fem3to0", 0xffffe000, 0,  SROM13_SWCTRLMAP4_MISC5G_FEM3TO0, 0xffff},
++	{"swctrlmap4_TX2g_fem7to4", 0xffffe000, 0,      SROM13_SWCTRLMAP4_TX2G_FEM7TO4, 0xffff},
++	{"swctrlmap4_RX2g_fem7to4", 0xffffe000, 0,      SROM13_SWCTRLMAP4_RX2G_FEM7TO4, 0xffff},
++	{"swctrlmap4_RXByp2g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_RXBYP2G_FEM7TO4, 0xffff},
++	{"swctrlmap4_misc2g_fem7to4", 0xffffe000, 0,  SROM13_SWCTRLMAP4_MISC2G_FEM7TO4, 0xffff},
++	{"swctrlmap4_TX5g_fem7to4", 0xffffe000, 0,      SROM13_SWCTRLMAP4_TX5G_FEM7TO4, 0xffff},
++	{"swctrlmap4_RX5g_fem7to4", 0xffffe000, 0,      SROM13_SWCTRLMAP4_RX5G_FEM7TO4, 0xffff},
++	{"swctrlmap4_RXByp5g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_RXBYP5G_FEM7TO4, 0xffff},
++	{"swctrlmap4_misc5g_fem7to4", 0xffffe000, 0,  SROM13_SWCTRLMAP4_MISC5G_FEM7TO4, 0xffff},
++	{NULL,		0,		0,		0,			0}
++};
++
++static const sromvar_t perpath_pci_sromvars[] = {
++	{"maxp2ga",	0x000000f0,	0,		SROM4_2G_ITT_MAXP,	0x00ff},
++	{"itt2ga",	0x000000f0,	0,		SROM4_2G_ITT_MAXP,	0xff00},
++	{"itt5ga",	0x000000f0,	0,		SROM4_5G_ITT_MAXP,	0xff00},
++	{"pa2gw0a",	0x000000f0,	SRFL_PRHEX,	SROM4_2G_PA,		0xffff},
++	{"pa2gw1a",	0x000000f0,	SRFL_PRHEX,	SROM4_2G_PA + 1,	0xffff},
++	{"pa2gw2a",	0x000000f0,	SRFL_PRHEX,	SROM4_2G_PA + 2,	0xffff},
++	{"pa2gw3a",	0x000000f0,	SRFL_PRHEX,	SROM4_2G_PA + 3,	0xffff},
++	{"maxp5ga",	0x000000f0,	0,		SROM4_5G_ITT_MAXP,	0x00ff},
++	{"maxp5gha",	0x000000f0,	0,		SROM4_5GLH_MAXP,	0x00ff},
++	{"maxp5gla",	0x000000f0,	0,		SROM4_5GLH_MAXP,	0xff00},
++	{"pa5gw0a",	0x000000f0,	SRFL_PRHEX,	SROM4_5G_PA,		0xffff},
++	{"pa5gw1a",	0x000000f0,	SRFL_PRHEX,	SROM4_5G_PA + 1,	0xffff},
++	{"pa5gw2a",	0x000000f0,	SRFL_PRHEX,	SROM4_5G_PA + 2,	0xffff},
++	{"pa5gw3a",	0x000000f0,	SRFL_PRHEX,	SROM4_5G_PA + 3,	0xffff},
++	{"pa5glw0a",	0x000000f0,	SRFL_PRHEX,	SROM4_5GL_PA,		0xffff},
++	{"pa5glw1a",	0x000000f0,	SRFL_PRHEX,	SROM4_5GL_PA + 1,	0xffff},
++	{"pa5glw2a",	0x000000f0,	SRFL_PRHEX,	SROM4_5GL_PA + 2,	0xffff},
++	{"pa5glw3a",	0x000000f0,	SRFL_PRHEX,	SROM4_5GL_PA + 3,	0xffff},
++	{"pa5ghw0a",	0x000000f0,	SRFL_PRHEX,	SROM4_5GH_PA,		0xffff},
++	{"pa5ghw1a",	0x000000f0,	SRFL_PRHEX,	SROM4_5GH_PA + 1,	0xffff},
++	{"pa5ghw2a",	0x000000f0,	SRFL_PRHEX,	SROM4_5GH_PA + 2,	0xffff},
++	{"pa5ghw3a",	0x000000f0,	SRFL_PRHEX,	SROM4_5GH_PA + 3,	0xffff},
++	{"maxp2ga",	0x00000700,	0,		SROM8_2G_ITT_MAXP,	0x00ff},
++	{"itt2ga",	0x00000700,	0,		SROM8_2G_ITT_MAXP,	0xff00},
++	{"itt5ga",	0x00000700,	0,		SROM8_5G_ITT_MAXP,	0xff00},
++	{"pa2gw0a",	0x00000700,	SRFL_PRHEX,	SROM8_2G_PA,		0xffff},
++	{"pa2gw1a",	0x00000700,	SRFL_PRHEX,	SROM8_2G_PA + 1,	0xffff},
++	{"pa2gw2a",	0x00000700,	SRFL_PRHEX,	SROM8_2G_PA + 2,	0xffff},
++	{"maxp5ga",	0x00000700,	0,		SROM8_5G_ITT_MAXP,	0x00ff},
++	{"maxp5gha",	0x00000700,	0,		SROM8_5GLH_MAXP,	0x00ff},
++	{"maxp5gla",	0x00000700,	0,		SROM8_5GLH_MAXP,	0xff00},
++	{"pa5gw0a",	0x00000700,	SRFL_PRHEX,	SROM8_5G_PA,		0xffff},
++	{"pa5gw1a",	0x00000700,	SRFL_PRHEX,	SROM8_5G_PA + 1,	0xffff},
++	{"pa5gw2a",	0x00000700,	SRFL_PRHEX,	SROM8_5G_PA + 2,	0xffff},
++	{"pa5glw0a",	0x00000700,	SRFL_PRHEX,	SROM8_5GL_PA,		0xffff},
++	{"pa5glw1a",	0x00000700,	SRFL_PRHEX,	SROM8_5GL_PA + 1,	0xffff},
++	{"pa5glw2a",	0x00000700,	SRFL_PRHEX,	SROM8_5GL_PA + 2,	0xffff},
++	{"pa5ghw0a",	0x00000700,	SRFL_PRHEX,	SROM8_5GH_PA,		0xffff},
++	{"pa5ghw1a",	0x00000700,	SRFL_PRHEX,	SROM8_5GH_PA + 1,	0xffff},
++	{"pa5ghw2a",	0x00000700,	SRFL_PRHEX,	SROM8_5GH_PA + 2,	0xffff},
++
++	/* sromrev 11 */
++	{"maxp2ga",	0xfffff800,	0,			 SROM11_2G_MAXP,	0x00ff},
++	{"pa2ga",	0x00000800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_2G_PA,		0xffff},
++	{"",		0x00000800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_2G_PA + 1,	0xffff},
++	{"",		0x00000800,	SRFL_PRHEX,		 SROM11_2G_PA + 2,	0xffff},
++	{"rxgains5gmelnagaina",	0x00000800,	0,		 SROM11_RXGAINS1,	0x0007},
++	{"rxgains5gmtrisoa",	0x00000800,	0,		 SROM11_RXGAINS1,	0x0078},
++	{"rxgains5gmtrelnabypa", 0x00000800,	0,		 SROM11_RXGAINS1,	0x0080},
++	{"rxgains5ghelnagaina",	0x00000800,	0,		 SROM11_RXGAINS1,	0x0700},
++	{"rxgains5ghtrisoa",	0x00000800,	0,		 SROM11_RXGAINS1,	0x7800},
++	{"rxgains5ghtrelnabypa", 0x00000800,	0,		 SROM11_RXGAINS1,	0x8000},
++	{"rxgains2gelnagaina",	0x00000800,	0,		 SROM11_RXGAINS,	0x0007},
++	{"rxgains2gtrisoa",	0x00000800,	0,		 SROM11_RXGAINS,	0x0078},
++	{"rxgains2gtrelnabypa",	0x00000800,	0,		 SROM11_RXGAINS,	0x0080},
++	{"rxgains5gelnagaina",	0x00000800,	0,		 SROM11_RXGAINS,	0x0700},
++	{"rxgains5gtrisoa",	0x00000800,	0,		 SROM11_RXGAINS,	0x7800},
++	{"rxgains5gtrelnabypa",	0x00000800,	0,		 SROM11_RXGAINS,	0x8000},
++	{"maxp5ga",	0x00000800,	SRFL_ARRAY,		 SROM11_5GB1B0_MAXP,	0x00ff},
++	{"",		0x00000800,	SRFL_ARRAY,		 SROM11_5GB1B0_MAXP,	0xff00},
++	{"",		0x00000800,	SRFL_ARRAY,		 SROM11_5GB3B2_MAXP,	0x00ff},
++	{"",		0x00000800,	0,			 SROM11_5GB3B2_MAXP,	0xff00},
++	{"pa5ga",	0x00000800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA,	0xffff},
++	{"",		0x00000800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA + 1,	0xffff},
++	{"",		0x00000800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA + 2,	0xffff},
++	{"",		0x00000800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA,	0xffff},
++	{"",		0x00000800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA + 1,	0xffff},
++	{"",		0x00000800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA + 2,	0xffff},
++	{"",		0x00000800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA,	0xffff},
++	{"",		0x00000800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA + 1,	0xffff},
++	{"",		0x00000800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA + 2,	0xffff},
++	{"",		0x00000800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB3_PA,	0xffff},
++	{"",		0x00000800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB3_PA + 1,	0xffff},
++	{"",		0x00000800,	SRFL_PRHEX,		 SROM11_5GB3_PA + 2,	0xffff},
++
++	/* sromrev 12 */
++	{"maxp5gb4a",	0xfffff000,	0,		 SROM12_5GB42G_MAXP,	0x00ff00},
++	{"pa2ga",	0xfffff000,	SRFL_PRHEX | SRFL_ARRAY,  SROM12_2GB0_PA_W0,	0x00ffff},
++	{"",	0xfffff000,	SRFL_PRHEX | SRFL_ARRAY,	  SROM12_2GB0_PA_W1,	0x00ffff},
++	{"",	0xfffff000,	SRFL_PRHEX | SRFL_ARRAY,	  SROM12_2GB0_PA_W2,	0x00ffff},
++	{"",	0xfffff000,	SRFL_PRHEX,		 SROM12_2GB0_PA_W3,	0x00ffff},
++
++	{"pa2g40a",	0xfffff000,	SRFL_PRHEX | SRFL_ARRAY,  SROM12_2G40B0_PA_W0,	0x00ffff},
++	{"",	0xfffff000,	SRFL_PRHEX | SRFL_ARRAY,	  SROM12_2G40B0_PA_W1,	0x00ffff},
++	{"",	0xfffff000,	SRFL_PRHEX | SRFL_ARRAY,	  SROM12_2G40B0_PA_W2,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX,		 SROM12_2G40B0_PA_W3,	0x00ffff},
++	{"maxp5gb0a",	0xfffff000, 0,	     SROM12_5GB1B0_MAXP,	0x00ff},
++	{"maxp5gb1a",	0xfffff000, 0,       SROM12_5GB1B0_MAXP,	0x00ff00},
++	{"maxp5gb2a",	0xfffff000, 0,	     SROM12_5GB3B2_MAXP,	0x00ff},
++	{"maxp5gb3a",	0xfffff000, 0,	     SROM12_5GB3B2_MAXP,	0x00ff00},
++
++	{"pa5ga",   0xfffff000, SRFL_PRHEX | SRFL_ARRAY,   SROM12_5GB0_PA_W0,		0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5GB0_PA_W1,		0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,         SROM12_5GB0_PA_W2,		0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5GB0_PA_W3,		0x00ffff},
++
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5GB1_PA_W0,		0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5GB1_PA_W1,		0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5GB1_PA_W2,		0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5GB1_PA_W3,		0x00ffff},
++
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5GB2_PA_W0,		0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5GB2_PA_W1,		0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5GB2_PA_W2,		0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5GB2_PA_W3,		0x00ffff},
++
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5GB3_PA_W0,		0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5GB3_PA_W1,		0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,         SROM12_5GB3_PA_W2,		0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5GB3_PA_W3,		0x00ffff},
++
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5GB4_PA_W0,		0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5GB4_PA_W1,		0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5GB4_PA_W2,		0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX,	                   SROM12_5GB4_PA_W3,		0x00ffff},
++
++	{"pa5g40a",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B0_PA_W0,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5G40B0_PA_W1,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5G40B0_PA_W2,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5G40B0_PA_W3,	0x00ffff},
++
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5G40B1_PA_W0,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5G40B1_PA_W1,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5G40B1_PA_W2,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,         SROM12_5G40B1_PA_W3,	0x00ffff},
++
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5G40B2_PA_W0,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5G40B2_PA_W1,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5G40B2_PA_W2,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5G40B2_PA_W3,	0x00ffff},
++
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5G40B3_PA_W0,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5G40B3_PA_W1,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5G40B3_PA_W2,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5G40B3_PA_W3,	0x00ffff},
++
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5G40B4_PA_W0,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5G40B4_PA_W1,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	     SROM12_5G40B4_PA_W2,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX,		             SROM12_5G40B4_PA_W3,	0x00ffff},
++
++	{"pa5g80a",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,	 SROM12_5G80B0_PA_W0,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B0_PA_W1,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B0_PA_W2,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B0_PA_W3,	0x00ffff},
++
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B1_PA_W0,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B1_PA_W1,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B1_PA_W2,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B1_PA_W3,	0x00ffff},
++
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B2_PA_W0,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B2_PA_W1,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B2_PA_W2,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B2_PA_W3,	0x00ffff},
++
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B3_PA_W0,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B3_PA_W1,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B3_PA_W2,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B3_PA_W3,	0x00ffff},
++
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B4_PA_W0,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B4_PA_W1,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX | SRFL_ARRAY,		 SROM12_5G80B4_PA_W2,	0x00ffff},
++	{"",	0xfffff000, SRFL_PRHEX,		                 SROM12_5G80B4_PA_W3,	0x00ffff},
++	/* sromrev 13 */
++	{"rxgains2gelnagaina",   0xffffe000,     0,       SROM13_RXGAINS,  0x0007},
++	{"rxgains2gtrisoa",     0xffffe000,     0,       SROM13_RXGAINS,  0x0078},
++	{"rxgains2gtrelnabypa", 0xffffe000,     0,       SROM13_RXGAINS,  0x0080},
++	{"rxgains5gelnagaina",  0xffffe000,     0,       SROM13_RXGAINS,  0x0700},
++	{"rxgains5gtrisoa",     0xffffe000,     0,       SROM13_RXGAINS,  0x7800},
++	{"rxgains5gtrelnabypa", 0xffffe000,     0,       SROM13_RXGAINS,  0x8000},
++	{NULL,		0,		0,		0, 			0}
++};
++
++#if !(defined(PHY_TYPE_HT) && defined(PHY_TYPE_N))
++#define	PHY_TYPE_HT		7	/* HT-Phy value */
++#define	PHY_TYPE_N		4	/* N-Phy value */
++#endif /* !(defined(PHY_TYPE_HT) && defined(PHY_TYPE_N)) */
++#if !defined(PHY_TYPE_AC)
++#define	PHY_TYPE_AC		11	/* AC-Phy value */
++#endif /* !defined(PHY_TYPE_AC) */
++#if !defined(PHY_TYPE_LCN20)
++#define	PHY_TYPE_LCN20		12	/* LCN20-Phy value */
++#endif /* !defined(PHY_TYPE_LCN20) */
++#if !defined(PHY_TYPE_NULL)
++#define	PHY_TYPE_NULL		0xf	/* Invalid Phy value */
++#endif /* !defined(PHY_TYPE_NULL) */
++
++typedef struct {
++	uint16	phy_type;
++	uint16	bandrange;
++	uint16	chain;
++	const char *vars;
++} pavars_t;
++
++static const pavars_t pavars[] = {
++	/* HTPHY */
++	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_2G,  0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"},
++	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_2G,  1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"},
++	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_2G,  2, "pa2gw0a2 pa2gw1a2 pa2gw2a2"},
++	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND0, 0, "pa5glw0a0 pa5glw1a0 pa5glw2a0"},
++	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND0, 1, "pa5glw0a1 pa5glw1a1 pa5glw2a1"},
++	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND0, 2, "pa5glw0a2 pa5glw1a2 pa5glw2a2"},
++	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND1, 0, "pa5gw0a0 pa5gw1a0 pa5gw2a0"},
++	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND1, 1, "pa5gw0a1 pa5gw1a1 pa5gw2a1"},
++	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND1, 2, "pa5gw0a2 pa5gw1a2 pa5gw2a2"},
++	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND2, 0, "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"},
++	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND2, 1, "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"},
++	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND2, 2, "pa5ghw0a2 pa5ghw1a2 pa5ghw2a2"},
++	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND3, 0, "pa5gw0a3 pa5gw1a3 pa5gw2a3"},
++	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND3, 1,  "pa5glw0a3 pa5glw1a3 pa5glw2a3"},
++	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND3, 2, "pa5ghw0a3 pa5ghw1a3 pa5ghw2a3"},
++	/* NPHY */
++	{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G,  0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"},
++	{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G,  1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"},
++	{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND0, 0, "pa5glw0a0 pa5glw1a0 pa5glw2a0"},
++	{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND0, 1, "pa5glw0a1 pa5glw1a1 pa5glw2a1"},
++	{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND1, 0, "pa5gw0a0 pa5gw1a0 pa5gw2a0"},
++	{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND1, 1, "pa5gw0a1 pa5gw1a1 pa5gw2a1"},
++	{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND2, 0, "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"},
++	{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND2, 1, "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"},
++	/* ACPHY */
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  0, "pa2ga0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  1, "pa2ga1"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  2, "pa2ga2"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND,  0, "pa5ga0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND,  1, "pa5ga1"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND,  2, "pa5ga2"},
++	/* LCN20PHY */
++	{PHY_TYPE_LCN20, WL_CHAN_FREQ_RANGE_2G,  0, "pa2ga0"},
++	{PHY_TYPE_NULL, 0, 0, ""}
++};
++
++
++static const pavars_t pavars_SROM12[] = {
++	/* ACPHY */
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  0, "pa2ga0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  1, "pa2ga1"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  2, "pa2ga2"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40,  0, "pa2g40a0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40,  1, "pa2g40a1"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40,  2, "pa2g40a2"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND,  0, "pa5ga0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND,  1, "pa5ga1"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND,  2, "pa5ga2"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40,  0, "pa5g40a0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40,  1, "pa5g40a1"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40,  2, "pa5g40a2"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80,  0, "pa5g80a0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80,  1, "pa5g80a1"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80,  2, "pa5g80a2"},
++	{PHY_TYPE_NULL, 0, 0, ""}
++};
++
++static const pavars_t pavars_SROM13[] = {
++	/* ACPHY */
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  0, "pa2ga0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  1, "pa2ga1"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  2, "pa2ga2"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  3, "pa2ga3"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40,  0, "pa2g40a0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40,  1, "pa2g40a1"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40,  2, "pa2g40a2"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40,  3, "pa2g40a3"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND,  0, "pa5ga0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND,  1, "pa5ga1"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND,  2, "pa5ga2"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND,  3, "pa5ga3"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40,  0, "pa5g40a0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40,  1, "pa5g40a1"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40,  2, "pa5g40a2"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40,  3, "pa5g40a3"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80,  0, "pa5g80a0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80,  1, "pa5g80a1"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80,  2, "pa5g80a2"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80,  3, "pa5g80a3"},
++	{PHY_TYPE_NULL, 0, 0, ""}
++};
++
++/* pavars table when paparambwver is 1 */
++static const pavars_t pavars_bwver_1[] = {
++	/* ACPHY */
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  0, "pa2ga0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  1, "pa2gccka0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  1, "pa2ga2"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND,  0, "pa5ga0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND,  1, "pa5gbw40a0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND,  2, "pa5gbw80a0"},
++	{PHY_TYPE_NULL, 0, 0, ""}
++};
++
++/* pavars table when paparambwver is 2 */
++static const pavars_t pavars_bwver_2[] = {
++	/* ACPHY */
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  0, "pa2ga0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  1, "pa2ga1"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND,  0, "pa5ga0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND,  1, "pa5ga1"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND,  2, "pa5gbw4080a0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND,  3, "pa5gbw4080a1"},
++	{PHY_TYPE_NULL, 0, 0, ""}
++};
++
++/* pavars table when paparambwver is 3 */
++static const pavars_t pavars_bwver_3[] = {
++	/* ACPHY */
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  0, "pa2ga0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  1, "pa2ga1"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  2, "pa2gccka0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G,  3, "pa2gccka1"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND,  0, "pa5ga0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND,  1, "pa5ga1"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND,  2, "pa5gbw4080a0"},
++	{PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND,  3, "pa5gbw4080a1"},
++	{PHY_TYPE_NULL, 0, 0, ""}
++};
++
++typedef struct {
++	uint16	phy_type;
++	uint16	bandrange;
++	const char *vars;
++} povars_t;
++
++static const povars_t povars[] = {
++	/* NPHY */
++	{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G,  "mcs2gpo0 mcs2gpo1 mcs2gpo2 mcs2gpo3 "
++	"mcs2gpo4 mcs2gpo5 mcs2gpo6 mcs2gpo7"},
++	{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, "mcs5glpo0 mcs5glpo1 mcs5glpo2 mcs5glpo3 "
++	"mcs5glpo4 mcs5glpo5 mcs5glpo6 mcs5glpo7"},
++	{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, "mcs5gpo0 mcs5gpo1 mcs5gpo2 mcs5gpo3 "
++	"mcs5gpo4 mcs5gpo5 mcs5gpo6 mcs5gpo7"},
++	{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, "mcs5ghpo0 mcs5ghpo1 mcs5ghpo2 mcs5ghpo3 "
++	"mcs5ghpo4 mcs5ghpo5 mcs5ghpo6 mcs5ghpo7"},
++	{PHY_TYPE_NULL, 0, ""}
++};
++
++typedef struct {
++	uint8	tag;		/* Broadcom subtag name */
++	uint32	revmask;	/* Supported cis_sromrev bitmask. Some of the parameters in
++				 * different tuples have the same name. Therefore, the MFGc tool
++				 * needs to know which tuple to generate when seeing these
++				 * parameters (given that we know sromrev from user input, like the
++				 * nvram file).
++				 */
++	uint8	len;		/* Length field of the tuple, note that it includes the
++				 * subtag name (1 byte): 1 + tuple content length
++				 */
++	const char *params;
++} cis_tuple_t;
++
++#define OTP_RAW		(0xff - 1)	/* Reserved tuple number for wrvar Raw input */
++#define OTP_VERS_1	(0xff - 2)	/* CISTPL_VERS_1 */
++#define OTP_MANFID	(0xff - 3)	/* CISTPL_MANFID */
++#define OTP_RAW1	(0xff - 4)	/* Like RAW, but comes first */
++
++/** this array is used by CIS creating/writing applications */
++static const cis_tuple_t cis_hnbuvars[] = {
++/*       tag			revmask   len  params */
++	{OTP_RAW1,		0xffffffff, 0, ""},	/* special case */
++	{OTP_VERS_1,	0xffffffff, 0, "smanf sproductname"},	/* special case (non BRCM tuple) */
++	{OTP_MANFID,	0xffffffff, 4, "2manfid 2prodid"},	/* special case (non BRCM tuple) */
++	/* Unified OTP: tupple to embed USB manfid inside SDIO CIS */
++	{HNBU_UMANFID,		0xffffffff, 8, "8usbmanfid"},
++	{HNBU_SROMREV,		0xffffffff, 2, "1sromrev"},
++	/* NOTE: subdevid is also written to boardtype.
++	 *       Need to write HNBU_BOARDTYPE to change it if it is different.
++	 */
++	{HNBU_CHIPID,		0xffffffff, 11, "2vendid 2devid 2chiprev 2subvendid 2subdevid"},
++	{HNBU_BOARDREV,		0xffffffff, 3, "2boardrev"},
++	{HNBU_PAPARMS,		0xffffffff, 10, "2pa0b0 2pa0b1 2pa0b2 1pa0itssit 1pa0maxpwr 1opo"},
++	{HNBU_AA,		0xffffffff, 3, "1aa2g 1aa5g"},
++	{HNBU_AA,		0xffffffff, 3, "1aa0 1aa1"}, /* backward compatibility */
++	{HNBU_AG,		0xffffffff, 5, "1ag0 1ag1 1ag2 1ag3"},
++	{HNBU_BOARDFLAGS,	0xffffffff, 21, "4boardflags 4boardflags2 4boardflags3 "
++	"4boardflags4 4boardflags5 "},
++	{HNBU_LEDS,		0xffffffff, 17, "1ledbh0 1ledbh1 1ledbh2 1ledbh3 1ledbh4 1ledbh5 "
++	"1ledbh6 1ledbh7 1ledbh8 1ledbh9 1ledbh10 1ledbh11 1ledbh12 1ledbh13 1ledbh14 1ledbh15"},
++	{HNBU_CCODE,		0xffffffff, 4, "2ccode 1cctl"},
++	{HNBU_CCKPO,		0xffffffff, 3, "2cckpo"},
++	{HNBU_OFDMPO,		0xffffffff, 5, "4ofdmpo"},
++	{HNBU_PAPARMS5G,	0xffffffff, 23, "2pa1b0 2pa1b1 2pa1b2 2pa1lob0 2pa1lob1 2pa1lob2 "
++	"2pa1hib0 2pa1hib1 2pa1hib2 1pa1itssit "
++	"1pa1maxpwr 1pa1lomaxpwr 1pa1himaxpwr"},
++	{HNBU_RDLID,		0xffffffff, 3, "2rdlid"},
++	{HNBU_RSSISMBXA2G, 0xffffffff, 3, "0rssismf2g 0rssismc2g "
++	"0rssisav2g 0bxa2g"}, /* special case */
++	{HNBU_RSSISMBXA5G, 0xffffffff, 3, "0rssismf5g 0rssismc5g "
++	"0rssisav5g 0bxa5g"}, /* special case */
++	{HNBU_XTALFREQ,		0xffffffff, 5, "4xtalfreq"},
++	{HNBU_TRI2G,		0xffffffff, 2, "1tri2g"},
++	{HNBU_TRI5G,		0xffffffff, 4, "1tri5gl 1tri5g 1tri5gh"},
++	{HNBU_RXPO2G,		0xffffffff, 2, "1rxpo2g"},
++	{HNBU_RXPO5G,		0xffffffff, 2, "1rxpo5g"},
++	{HNBU_BOARDNUM,		0xffffffff, 3, "2boardnum"},
++	{HNBU_MACADDR,		0xffffffff, 7, "6macaddr"},	/* special case */
++	{HNBU_RDLSN,		0xffffffff, 3, "2rdlsn"},
++	{HNBU_BOARDTYPE,	0xffffffff, 3, "2boardtype"},
++	{HNBU_LEDDC,		0xffffffff, 3, "2leddc"},
++	{HNBU_RDLRNDIS,		0xffffffff, 2, "1rdlndis"},
++	{HNBU_CHAINSWITCH,	0xffffffff, 5, "1txchain 1rxchain 2antswitch"},
++	{HNBU_REGREV,		0xffffffff, 3, "2regrev"},
++	{HNBU_FEM,		0x000007fe, 5, "0antswctl2g 0triso2g 0pdetrange2g 0extpagain2g "
++	"0tssipos2g 0antswctl5g 0triso5g 0pdetrange5g 0extpagain5g 0tssipos5g"}, /* special case */
++	{HNBU_PAPARMS_C0,	0x000007fe, 31, "1maxp2ga0 1itt2ga0 2pa2gw0a0 2pa2gw1a0 "
++	"2pa2gw2a0 1maxp5ga0 1itt5ga0 1maxp5gha0 1maxp5gla0 2pa5gw0a0 2pa5gw1a0 2pa5gw2a0 "
++	"2pa5glw0a0 2pa5glw1a0 2pa5glw2a0 2pa5ghw0a0 2pa5ghw1a0 2pa5ghw2a0"},
++	{HNBU_PAPARMS_C1,	0x000007fe, 31, "1maxp2ga1 1itt2ga1 2pa2gw0a1 2pa2gw1a1 "
++	"2pa2gw2a1 1maxp5ga1 1itt5ga1 1maxp5gha1 1maxp5gla1 2pa5gw0a1 2pa5gw1a1 2pa5gw2a1 "
++	"2pa5glw0a1 2pa5glw1a1 2pa5glw2a1 2pa5ghw0a1 2pa5ghw1a1 2pa5ghw2a1"},
++	{HNBU_PO_CCKOFDM,	0xffffffff, 19, "2cck2gpo 4ofdm2gpo 4ofdm5gpo 4ofdm5glpo "
++	"4ofdm5ghpo"},
++	{HNBU_PO_MCS2G,		0xffffffff, 17, "2mcs2gpo0 2mcs2gpo1 2mcs2gpo2 2mcs2gpo3 "
++	"2mcs2gpo4 2mcs2gpo5 2mcs2gpo6 2mcs2gpo7"},
++	{HNBU_PO_MCS5GM,	0xffffffff, 17, "2mcs5gpo0 2mcs5gpo1 2mcs5gpo2 2mcs5gpo3 "
++	"2mcs5gpo4 2mcs5gpo5 2mcs5gpo6 2mcs5gpo7"},
++	{HNBU_PO_MCS5GLH,	0xffffffff, 33, "2mcs5glpo0 2mcs5glpo1 2mcs5glpo2 2mcs5glpo3 "
++	"2mcs5glpo4 2mcs5glpo5 2mcs5glpo6 2mcs5glpo7 "
++	"2mcs5ghpo0 2mcs5ghpo1 2mcs5ghpo2 2mcs5ghpo3 "
++	"2mcs5ghpo4 2mcs5ghpo5 2mcs5ghpo6 2mcs5ghpo7"},
++	{HNBU_CCKFILTTYPE,	0xffffffff, 2, "1cckdigfilttype"},
++	{HNBU_PO_CDD,		0xffffffff, 3, "2cddpo"},
++	{HNBU_PO_STBC,		0xffffffff, 3, "2stbcpo"},
++	{HNBU_PO_40M,		0xffffffff, 3, "2bw40po"},
++	{HNBU_PO_40MDUP,	0xffffffff, 3, "2bwduppo"},
++	{HNBU_RDLRWU,		0xffffffff, 2, "1rdlrwu"},
++	{HNBU_WPS,		0xffffffff, 3, "1wpsgpio 1wpsled"},
++	{HNBU_USBFS,		0xffffffff, 2, "1usbfs"},
++	{HNBU_ELNA2G,           0xffffffff, 2, "1elna2g"},
++	{HNBU_ELNA5G,           0xffffffff, 2, "1elna5g"},
++	{HNBU_CUSTOM1,		0xffffffff, 5, "4customvar1"},
++	{OTP_RAW,		0xffffffff, 0, ""},	/* special case */
++	{HNBU_OFDMPO5G,		0xffffffff, 13, "4ofdm5gpo 4ofdm5glpo 4ofdm5ghpo"},
++	{HNBU_USBEPNUM,		0xffffffff, 3, "2usbepnum"},
++	{HNBU_CCKBW202GPO,	0xffffffff, 7, "2cckbw202gpo 2cckbw20ul2gpo 2cckbw20in802gpo"},
++	{HNBU_LEGOFDMBW202GPO,	0xffffffff, 9, "4legofdmbw202gpo 4legofdmbw20ul2gpo"},
++	{HNBU_LEGOFDMBW205GPO,	0xffffffff, 25, "4legofdmbw205glpo 4legofdmbw20ul5glpo "
++	"4legofdmbw205gmpo 4legofdmbw20ul5gmpo 4legofdmbw205ghpo 4legofdmbw20ul5ghpo"},
++	{HNBU_MCS2GPO,	0xffffffff, 17,	"4mcsbw202gpo 4mcsbw20ul2gpo 4mcsbw402gpo 4mcsbw802gpo"},
++	{HNBU_MCS5GLPO,	0xffffffff, 13,	"4mcsbw205glpo 4mcsbw20ul5glpo 4mcsbw405glpo"},
++	{HNBU_MCS5GMPO,	0xffffffff, 13,	"4mcsbw205gmpo 4mcsbw20ul5gmpo 4mcsbw405gmpo"},
++	{HNBU_MCS5GHPO,	0xffffffff, 13,	"4mcsbw205ghpo 4mcsbw20ul5ghpo 4mcsbw405ghpo"},
++	{HNBU_MCS32PO,	0xffffffff, 3,	"2mcs32po"},
++	{HNBU_LEG40DUPPO,	0xffffffff, 3,	"2legofdm40duppo"},
++	{HNBU_TEMPTHRESH,	0xffffffff, 7,	"1tempthresh 0temps_period 0temps_hysteresis "
++	"1tempoffset 1tempsense_slope 0tempcorrx 0tempsense_option "
++	"1phycal_tempdelta"}, /* special case */
++	{HNBU_MUXENAB,		0xffffffff, 2,	"1muxenab"},
++	{HNBU_FEM_CFG,		0xfffff800, 5,	"0femctrl 0papdcap2g 0tworangetssi2g 0pdgain2g "
++	"0epagain2g 0tssiposslope2g 0gainctrlsph 0papdcap5g 0tworangetssi5g 0pdgain5g 0epagain5g "
++	"0tssiposslope5g"}, /* special case */
++	{HNBU_ACPA_C0,		0xfffff800, 39,	"2subband5gver 2maxp2ga0 2*3pa2ga0 "
++	"1*4maxp5ga0 2*12pa5ga0"},
++	{HNBU_ACPA_C1,		0xfffff800, 37,	"2maxp2ga1 2*3pa2ga1 1*4maxp5ga1 2*12pa5ga1"},
++	{HNBU_ACPA_C2,		0xfffff800, 37,	"2maxp2ga2 2*3pa2ga2 1*4maxp5ga2 2*12pa5ga2"},
++	{HNBU_MEAS_PWR,		0xfffff800, 5,	"1measpower 1measpower1 1measpower2 2rawtempsense"},
++	{HNBU_PDOFF,		0xfffff800, 13,	"2pdoffset40ma0 2pdoffset40ma1 2pdoffset40ma2 "
++	"2pdoffset80ma0 2pdoffset80ma1 2pdoffset80ma2"},
++	{HNBU_ACPPR_2GPO,	0xfffff800, 13,	"2dot11agofdmhrbw202gpo 2ofdmlrbw202gpo "
++	"2sb20in40dot11agofdm2gpo 2sb20in80dot11agofdm2gpo 2sb20in40ofdmlrbw202gpo "
++	"2sb20in80ofdmlrbw202gpo"},
++	{HNBU_ACPPR_5GPO,	0xfffff800, 59,	"4mcsbw805glpo 4mcsbw1605glpo 4mcsbw805gmpo "
++	"4mcsbw1605gmpo 4mcsbw805ghpo 4mcsbw1605ghpo 2mcslr5glpo 2mcslr5gmpo 2mcslr5ghpo "
++	"4mcsbw80p805glpo 4mcsbw80p805gmpo 4mcsbw80p805ghpo 4mcsbw80p805gx1po 2mcslr5gx1po "
++	"2mcslr5g80p80po 4mcsbw805gx1po 4mcsbw1605gx1po"},
++	{HNBU_MCS5Gx1PO,	0xfffff800, 9,	"4mcsbw205gx1po 4mcsbw405gx1po"},
++	{HNBU_ACPPR_SBPO,	0xfffff800, 49,	"2sb20in40hrpo 2sb20in80and160hr5glpo "
++	"2sb40and80hr5glpo 2sb20in80and160hr5gmpo 2sb40and80hr5gmpo 2sb20in80and160hr5ghpo "
++	"2sb40and80hr5ghpo 2sb20in40lrpo 2sb20in80and160lr5glpo 2sb40and80lr5glpo "
++	"2sb20in80and160lr5gmpo 2sb40and80lr5gmpo 2sb20in80and160lr5ghpo 2sb40and80lr5ghpo "
++	"4dot11agduphrpo 4dot11agduplrpo 2sb20in40and80hrpo 2sb20in40and80lrpo "
++	"2sb20in80and160hr5gx1po 2sb20in80and160lr5gx1po 2sb40and80hr5gx1po 2sb40and80lr5gx1po "
++	},
++	{HNBU_ACPPR_SB8080_PO, 0xfffff800, 23, "2sb2040and80in80p80hr5glpo "
++	"2sb2040and80in80p80lr5glpo 2sb2040and80in80p80hr5gmpo "
++	"2sb2040and80in80p80lr5gmpo 2sb2040and80in80p80hr5ghpo 2sb2040and80in80p80lr5ghpo "
++	"2sb2040and80in80p80hr5gx1po 2sb2040and80in80p80lr5gx1po 2sb20in80p80hr5gpo "
++	"2sb20in80p80lr5gpo 2dot11agduppo"},
++	{HNBU_NOISELVL,		0xfffff800, 16, "1noiselvl2ga0 1noiselvl2ga1 1noiselvl2ga2 "
++	"1*4noiselvl5ga0 1*4noiselvl5ga1 1*4noiselvl5ga2"},
++	{HNBU_RXGAIN_ERR,	0xfffff800, 16, "1rxgainerr2ga0 1rxgainerr2ga1 1rxgainerr2ga2 "
++	"1*4rxgainerr5ga0 1*4rxgainerr5ga1 1*4rxgainerr5ga2"},
++	{HNBU_AGBGA,		0xfffff800, 7, "1agbg0 1agbg1 1agbg2 1aga0 1aga1 1aga2"},
++	{HNBU_USBDESC_COMPOSITE, 0xffffffff, 3, "2usbdesc_composite"},
++	{HNBU_UUID, 		0xffffffff, 17,	"16uuid"},
++	{HNBU_WOWLGPIO,		0xffffffff, 2,  "1wowl_gpio"},
++	{HNBU_ACRXGAINS_C0,	0xfffff800, 5, "0rxgains5gtrelnabypa0 0rxgains5gtrisoa0 "
++	"0rxgains5gelnagaina0 0rxgains2gtrelnabypa0 0rxgains2gtrisoa0 0rxgains2gelnagaina0 "
++	"0rxgains5ghtrelnabypa0 0rxgains5ghtrisoa0 0rxgains5ghelnagaina0 0rxgains5gmtrelnabypa0 "
++	"0rxgains5gmtrisoa0 0rxgains5gmelnagaina0"},	/* special case */
++	{HNBU_ACRXGAINS_C1,	0xfffff800, 5, "0rxgains5gtrelnabypa1 0rxgains5gtrisoa1 "
++	"0rxgains5gelnagaina1 0rxgains2gtrelnabypa1 0rxgains2gtrisoa1 0rxgains2gelnagaina1 "
++	"0rxgains5ghtrelnabypa1 0rxgains5ghtrisoa1 0rxgains5ghelnagaina1 0rxgains5gmtrelnabypa1 "
++	"0rxgains5gmtrisoa1 0rxgains5gmelnagaina1"},	/* special case */
++	{HNBU_ACRXGAINS_C2,	0xfffff800, 5, "0rxgains5gtrelnabypa2 0rxgains5gtrisoa2 "
++	"0rxgains5gelnagaina2 0rxgains2gtrelnabypa2 0rxgains2gtrisoa2 0rxgains2gelnagaina2 "
++	"0rxgains5ghtrelnabypa2 0rxgains5ghtrisoa2 0rxgains5ghelnagaina2 0rxgains5gmtrelnabypa2 "
++	"0rxgains5gmtrisoa2 0rxgains5gmelnagaina2"},	/* special case */
++	{HNBU_TXDUTY, 		0xfffff800, 9,	"2tx_duty_cycle_ofdm_40_5g "
++	"2tx_duty_cycle_thresh_40_5g 2tx_duty_cycle_ofdm_80_5g 2tx_duty_cycle_thresh_80_5g"},
++	{HNBU_PDOFF_2G,		0xfffff800, 3,	"0pdoffset2g40ma0 0pdoffset2g40ma1 "
++	"0pdoffset2g40ma2 0pdoffset2g40mvalid"},
++	{HNBU_ACPA_CCK,		0xfffff800, 7,	"2*3pa2gccka0"},
++	{HNBU_ACPA_40,		0xfffff800, 25,	"2*12pa5gbw40a0"},
++	{HNBU_ACPA_80,		0xfffff800, 25,	"2*12pa5gbw80a0"},
++	{HNBU_ACPA_4080,	0xfffff800, 49,	"2*12pa5gbw4080a0 2*12pa5gbw4080a1"},
++	{HNBU_SUBBAND5GVER,	0xfffff800, 3,	"2subband5gver"},
++	{HNBU_PAPARAMBWVER,	0xfffff800, 2,	"1paparambwver"},
++	{HNBU_TXBFRPCALS,  0xfffff800, 11,
++	"2rpcal2g 2rpcal5gb0 2rpcal5gb1 2rpcal5gb2 2rpcal5gb3"}, /* txbf rpcalvars */
++	{HNBU_GPIO_PULL_DOWN,	0xffffffff, 5, "4gpdn"},
++	{HNBU_MACADDR2,		0xffffffff, 7, "6macaddr2"},	/* special case */
++	{0xFF,			0xffffffff, 0, ""}
++};
++
++#endif /* _bcmsrom_tbl_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmtcp.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmtcp.h
+new file mode 100644
+index 000000000..4d4094875
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmtcp.h
+@@ -0,0 +1,93 @@
++/*
++ * Fundamental constants relating to TCP Protocol
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmtcp.h 700076 2017-05-17 14:42:22Z $
++ */
++
++#ifndef _bcmtcp_h_
++#define _bcmtcp_h_
++
++#ifndef _TYPEDEFS_H_
++#include <typedefs.h>
++#endif
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++
++
++#define TCP_SRC_PORT_OFFSET	0	/* TCP source port offset */
++#define TCP_DEST_PORT_OFFSET	2	/* TCP dest port offset */
++#define TCP_SEQ_NUM_OFFSET	4	/* TCP sequence number offset */
++#define TCP_ACK_NUM_OFFSET	8	/* TCP acknowledgement number offset */
++#define TCP_HLEN_OFFSET		12	/* HLEN and reserved bits offset */
++#define TCP_FLAGS_OFFSET	13	/* FLAGS and reserved bits offset */
++#define TCP_CHKSUM_OFFSET	16	/* TCP body checksum offset */
++
++#define TCP_PORT_LEN		2	/* TCP port field length */
++
++/* 8bit TCP flag field */
++#define TCP_FLAG_URG            0x20
++#define TCP_FLAG_ACK            0x10
++#define TCP_FLAG_PSH            0x08
++#define TCP_FLAG_RST            0x04
++#define TCP_FLAG_SYN            0x02
++#define TCP_FLAG_FIN            0x01
++
++#define TCP_HLEN_MASK           0xf000
++#define TCP_HLEN_SHIFT          12
++
++/* These fields are stored in network order */
++BWL_PRE_PACKED_STRUCT struct bcmtcp_hdr
++{
++	uint16	src_port;	/* Source Port Address */
++	uint16	dst_port;	/* Destination Port Address */
++	uint32	seq_num;	/* TCP Sequence Number */
++	uint32	ack_num;	/* TCP Sequence Number */
++	uint16	hdrlen_rsvd_flags;	/* Header length, reserved bits and flags */
++	uint16	tcpwin;		/* TCP window */
++	uint16	chksum;		/* Segment checksum with pseudoheader */
++	uint16	urg_ptr;	/* Points to seq-num of byte following urg data */
++} BWL_POST_PACKED_STRUCT;
++
++#define TCP_MIN_HEADER_LEN 20
++
++#define TCP_HDRLEN_MASK 0xf0
++#define TCP_HDRLEN_SHIFT 4
++#define TCP_HDRLEN(hdrlen) (((hdrlen) & TCP_HDRLEN_MASK) >> TCP_HDRLEN_SHIFT)
++
++#define TCP_FLAGS_MASK  0x1f
++#define TCP_FLAGS(hdrlen) ((hdrlen) & TCP_FLAGS_MASK)
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++/* To address round up by 32bit. */
++#define IS_TCPSEQ_GE(a, b) ((a - b) < NBITVAL(31))		/* a >= b */
++#define IS_TCPSEQ_LE(a, b) ((b - a) < NBITVAL(31))		/* a =< b */
++#define IS_TCPSEQ_GT(a, b) !IS_TCPSEQ_LE(a, b)		/* a > b */
++#define IS_TCPSEQ_LT(a, b) !IS_TCPSEQ_GE(a, b)		/* a < b */
++
++#endif	/* #ifndef _bcmtcp_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmudp.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmudp.h
+new file mode 100644
+index 000000000..e55813482
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmudp.h
+@@ -0,0 +1,61 @@
++/*
++ * Fundamental constants relating to UDP Protocol
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmudp.h 700076 2017-05-17 14:42:22Z $
++ */
++
++#ifndef _bcmudp_h_
++#define _bcmudp_h_
++
++#ifndef _TYPEDEFS_H_
++#include <typedefs.h>
++#endif
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++
++
++/* UDP header */
++#define UDP_DEST_PORT_OFFSET	2	/* UDP dest port offset */
++#define UDP_LEN_OFFSET		4	/* UDP length offset */
++#define UDP_CHKSUM_OFFSET	6	/* UDP body checksum offset */
++
++#define UDP_HDR_LEN	8	/* UDP header length */
++#define UDP_PORT_LEN	2	/* UDP port length */
++
++/* These fields are stored in network order */
++BWL_PRE_PACKED_STRUCT struct bcmudp_hdr
++{
++	uint16	src_port;	/* Source Port Address */
++	uint16	dst_port;	/* Destination Port Address */
++	uint16	len;		/* Number of bytes in datagram including header */
++	uint16	chksum;		/* entire datagram checksum with pseudoheader */
++} BWL_POST_PACKED_STRUCT;
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++#endif	/* #ifndef _bcmudp_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/bcmutils.h b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmutils.h
+new file mode 100644
+index 000000000..3c061b8bf
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/bcmutils.h
+@@ -0,0 +1,1355 @@
++/*
++ * Misc useful os-independent macros and functions.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmutils.h 701785 2017-05-26 11:08:50Z $
++ */
++
++#ifndef	_bcmutils_h_
++#define	_bcmutils_h_
++
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++
++#define bcm_strncpy_s(dst, noOfElements, src, count)    strncpy((dst), (src), (count))
++#define bcm_strncat_s(dst, noOfElements, src, count)    strncat((dst), (src), (count))
++#define bcm_snprintf_s snprintf
++#define bcm_sprintf_s snprintf
++
++/*
++ * #define bcm_strcpy_s(dst, count, src)            strncpy((dst), (src), (count))
++ * Use bcm_strcpy_s instead as it is a safer option
++ * bcm_strcat_s: Use bcm_strncat_s as a safer option
++ *
++ */
++
++#define BCM_BIT(x)		(1 << (x))
++
++/* ctype replacement */
++#define _BCM_U	0x01	/* upper */
++#define _BCM_L	0x02	/* lower */
++#define _BCM_D	0x04	/* digit */
++#define _BCM_C	0x08	/* cntrl */
++#define _BCM_P	0x10	/* punct */
++#define _BCM_S	0x20	/* white space (space/lf/tab) */
++#define _BCM_X	0x40	/* hex digit */
++#define _BCM_SP	0x80	/* hard space (0x20) */
++
++extern const unsigned char bcm_ctype[];
++#define bcm_ismask(x)	(bcm_ctype[(int)(unsigned char)(x)])
++
++#define bcm_isalnum(c)	((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
++#define bcm_isalpha(c)	((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
++#define bcm_iscntrl(c)	((bcm_ismask(c)&(_BCM_C)) != 0)
++#define bcm_isdigit(c)	((bcm_ismask(c)&(_BCM_D)) != 0)
++#define bcm_isgraph(c)	((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
++#define bcm_islower(c)	((bcm_ismask(c)&(_BCM_L)) != 0)
++#define bcm_isprint(c)	((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
++#define bcm_ispunct(c)	((bcm_ismask(c)&(_BCM_P)) != 0)
++#define bcm_isspace(c)	((bcm_ismask(c)&(_BCM_S)) != 0)
++#define bcm_isupper(c)	((bcm_ismask(c)&(_BCM_U)) != 0)
++#define bcm_isxdigit(c)	((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
++#define bcm_tolower(c)	(bcm_isupper((c)) ? ((c) + 'a' - 'A') : (c))
++#define bcm_toupper(c)	(bcm_islower((c)) ? ((c) + 'A' - 'a') : (c))
++
++#define CIRCULAR_ARRAY_FULL(rd_idx, wr_idx, max) ((wr_idx + 1)%max == rd_idx)
++
++#define KB(bytes)	(((bytes) + 1023) / 1024)
++
++/* Buffer structure for collecting string-formatted data
++* using bcm_bprintf() API.
++* Use bcm_binit() to initialize before use
++*/
++
++struct bcmstrbuf {
++	char *buf;	/* pointer to current position in origbuf */
++	unsigned int size;	/* current (residual) size in bytes */
++	char *origbuf;	/* unmodified pointer to orignal buffer */
++	unsigned int origsize;	/* unmodified orignal buffer size in bytes */
++};
++
++#define BCMSTRBUF_LEN(b)	(b->size)
++#define BCMSTRBUF_BUF(b)	(b->buf)
++
++/* ** driver-only section ** */
++#ifdef BCMDRIVER
++#include <osl.h>
++#include <hnd_pktq.h>
++#include <hnd_pktpool.h>
++
++#define GPIO_PIN_NOTDEFINED 	0x20	/* Pin not defined */
++
++/*
++ * Spin at most 'us' microseconds while 'exp' is true.
++ * Caller should explicitly test 'exp' when this completes
++ * and take appropriate error action if 'exp' is still true.
++ */
++#ifndef SPINWAIT_POLL_PERIOD
++#define SPINWAIT_POLL_PERIOD	10
++#endif
++
++#define SPINWAIT(exp, us) { \
++	uint countdown = (us) + (SPINWAIT_POLL_PERIOD - 1); \
++	while ((exp) && (countdown >= SPINWAIT_POLL_PERIOD)) { \
++		OSL_DELAY(SPINWAIT_POLL_PERIOD); \
++		countdown -= SPINWAIT_POLL_PERIOD; \
++	} \
++}
++
++/* forward definition of ether_addr structure used by some function prototypes */
++
++struct ether_addr;
++
++extern int ether_isbcast(const void *ea);
++extern int ether_isnulladdr(const void *ea);
++
++#define UP_TABLE_MAX	((IPV4_TOS_DSCP_MASK >> IPV4_TOS_DSCP_SHIFT) + 1)	/* 64 max */
++
++/* externs */
++/* packet */
++extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
++extern uint pktfrombuf(osl_t *osh, void *p, uint offset, int len, uchar *buf);
++extern uint pkttotlen(osl_t *osh, void *p);
++extern void *pktlast(osl_t *osh, void *p);
++extern uint pktsegcnt(osl_t *osh, void *p);
++extern uint pktsegcnt_war(osl_t *osh, void *p);
++extern uint8 *pktdataoffset(osl_t *osh, void *p,  uint offset);
++extern void *pktoffset(osl_t *osh, void *p,  uint offset);
++/* Add to adjust 802.1x priority */
++extern void pktset8021xprio(void *pkt, int prio);
++
++/* Get priority from a packet and pass it back in scb (or equiv) */
++#define	PKTPRIO_VDSCP	0x100		/* DSCP prio found af	ter VLAN tag */
++#define	PKTPRIO_VLAN	0x200		/* VLAN prio found */
++#define	PKTPRIO_UPD	0x400		/* DSCP used to update VLAN prio */
++#define	PKTPRIO_DSCP	0x800		/* DSCP prio found */
++
++/* DSCP type definitions (RFC4594) */
++/* AF1x: High-Throughput Data (RFC2597) */
++#define DSCP_AF11	0x0A
++#define DSCP_AF12	0x0C
++#define DSCP_AF13	0x0E
++/* AF2x: Low-Latency Data (RFC2597) */
++#define DSCP_AF21	0x12
++#define DSCP_AF22	0x14
++#define DSCP_AF23	0x16
++/* AF3x: Multimedia Streaming (RFC2597) */
++#define DSCP_AF31	0x1A
++#define DSCP_AF32	0x1C
++#define DSCP_AF33	0x1E
++/* EF: Telephony (RFC3246) */
++#define DSCP_EF		0x2E
++
++extern uint pktsetprio(void *pkt, bool update_vtag);
++extern uint pktsetprio_qms(void *pkt, uint8* up_table, bool update_vtag);
++extern bool pktgetdscp(uint8 *pktdata, uint pktlen, uint8 *dscp);
++
++/* ethernet address */
++extern char *bcm_ether_ntoa(const struct ether_addr *ea, char *buf);
++extern int bcm_ether_atoe(const char *p, struct ether_addr *ea);
++
++/* ip address */
++struct ipv4_addr;
++extern char *bcm_ip_ntoa(struct ipv4_addr *ia, char *buf);
++extern char *bcm_ipv6_ntoa(void *ipv6, char *buf);
++extern int bcm_atoipv4(const char *p, struct ipv4_addr *ip);
++
++/* delay */
++extern void bcm_mdelay(uint ms);
++/* variable access */
++#if defined(BCM_RECLAIM)
++#define NVRAM_RECLAIM_CHECK(name)							\
++	if (bcm_attach_part_reclaimed == TRUE) {						\
++		*(char*) 0 = 0; /* TRAP */						\
++		return NULL;								\
++	}
++#else /* BCM_RECLAIM */
++#define NVRAM_RECLAIM_CHECK(name)
++#endif /* BCM_RECLAIM */
++
++extern char *getvar(char *vars, const char *name);
++extern int getintvar(char *vars, const char *name);
++extern int getintvararray(char *vars, const char *name, int index);
++extern int getintvararraysize(char *vars, const char *name);
++extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
++#define bcm_perf_enable()
++#define bcmstats(fmt)
++#define	bcmlog(fmt, a1, a2)
++#define	bcmdumplog(buf, size)	*buf = '\0'
++#define	bcmdumplogent(buf, idx)	-1
++
++#define TSF_TICKS_PER_MS	1000
++#define TS_ENTER		0xdeadbeef	/* Timestamp profiling enter */
++#define TS_EXIT			0xbeefcafe	/* Timestamp profiling exit */
++
++#define bcmtslog(tstamp, fmt, a1, a2)
++#define bcmprinttslogs()
++#define bcmprinttstamp(us)
++#define bcmdumptslog(b)
++
++extern char *bcm_nvram_vars(uint *length);
++extern int bcm_nvram_cache(void *sih);
++
++/* Support for sharing code across in-driver iovar implementations.
++ * The intent is that a driver use this structure to map iovar names
++ * to its (private) iovar identifiers, and the lookup function to
++ * find the entry.  Macros are provided to map ids and get/set actions
++ * into a single number space for a switch statement.
++ */
++
++/* iovar structure */
++typedef struct bcm_iovar {
++	const char *name;	/* name for lookup and display */
++	uint16 varid;		/* id for switch */
++	uint16 flags;		/* driver-specific flag bits */
++	uint8 flags2;		 /* driver-specific flag bits */
++	uint8 type;		/* base type of argument */
++	uint16 minlen;		/* min length for buffer vars */
++} bcm_iovar_t;
++
++/* varid definitions are per-driver, may use these get/set bits */
++
++/* IOVar action bits for id mapping */
++#define IOV_GET 0 /* Get an iovar */
++#define IOV_SET 1 /* Set an iovar */
++
++/* Varid to actionid mapping */
++#define IOV_GVAL(id)		((id) * 2)
++#define IOV_SVAL(id)		((id) * 2 + IOV_SET)
++#define IOV_ISSET(actionid)	((actionid & IOV_SET) == IOV_SET)
++#define IOV_ID(actionid)	(actionid >> 1)
++
++/* flags are per-driver based on driver attributes */
++
++extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name);
++extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set);
++
++/* ioctl structure */
++typedef struct wlc_ioctl_cmd {
++	uint16 cmd;			/**< IOCTL command */
++	uint16 flags;			/**< IOCTL command flags */
++	int16 min_len;			/**< IOCTL command minimum argument len (in bytes) */
++} wlc_ioctl_cmd_t;
++
++#if defined(WLTINYDUMP) || defined(WLMSG_INFORM) || defined(WLMSG_ASSOC) || \
++	defined(WLMSG_PRPKT) || defined(WLMSG_WSEC)
++extern int bcm_format_ssid(char* buf, const uchar ssid[], uint ssid_len);
++#endif 
++#endif	/* BCMDRIVER */
++
++/* string */
++extern int bcm_atoi(const char *s);
++extern ulong bcm_strtoul(const char *cp, char **endp, uint base);
++extern char *bcmstrstr(const char *haystack, const char *needle);
++extern char *bcmstrnstr(const char *s, uint s_len, const char *substr, uint substr_len);
++extern char *bcmstrcat(char *dest, const char *src);
++extern char *bcmstrncat(char *dest, const char *src, uint size);
++extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
++char* bcmstrtok(char **string, const char *delimiters, char *tokdelim);
++int bcmstricmp(const char *s1, const char *s2);
++int bcmstrnicmp(const char* s1, const char* s2, int cnt);
++
++/* Base type definitions */
++#define IOVT_VOID	0	/* no value (implictly set only) */
++#define IOVT_BOOL	1	/* any value ok (zero/nonzero) */
++#define IOVT_INT8	2	/* integer values are range-checked */
++#define IOVT_UINT8	3	/* unsigned int 8 bits */
++#define IOVT_INT16	4	/* int 16 bits */
++#define IOVT_UINT16	5	/* unsigned int 16 bits */
++#define IOVT_INT32	6	/* int 32 bits */
++#define IOVT_UINT32	7	/* unsigned int 32 bits */
++#define IOVT_BUFFER	8	/* buffer is size-checked as per minlen */
++#define BCM_IOVT_VALID(type) (((unsigned int)(type)) <= IOVT_BUFFER)
++
++/* Initializer for IOV type strings */
++#define BCM_IOV_TYPE_INIT { \
++	"void", \
++	"bool", \
++	"int8", \
++	"uint8", \
++	"int16", \
++	"uint16", \
++	"int32", \
++	"uint32", \
++	"buffer", \
++	"" }
++
++#define BCM_IOVT_IS_INT(type) (\
++	(type == IOVT_BOOL) || \
++	(type == IOVT_INT8) || \
++	(type == IOVT_UINT8) || \
++	(type == IOVT_INT16) || \
++	(type == IOVT_UINT16) || \
++	(type == IOVT_INT32) || \
++	(type == IOVT_UINT32))
++
++/* ** driver/apps-shared section ** */
++
++#define BCME_STRLEN 		64	/* Max string length for BCM errors */
++#define VALID_BCMERROR(e)  ((e <= 0) && (e >= BCME_LAST))
++
++
++/*
++ * error codes could be added but the defined ones shouldn't be changed/deleted
++ * these error codes are exposed to the user code
++ * when ever a new error code is added to this list
++ * please update errorstring table with the related error string and
++ * update osl files with os specific errorcode map
++*/
++
++#define BCME_OK				0	/* Success */
++#define BCME_ERROR			-1	/* Error generic */
++#define BCME_BADARG			-2	/* Bad Argument */
++#define BCME_BADOPTION			-3	/* Bad option */
++#define BCME_NOTUP			-4	/* Not up */
++#define BCME_NOTDOWN			-5	/* Not down */
++#define BCME_NOTAP			-6	/* Not AP */
++#define BCME_NOTSTA			-7	/* Not STA  */
++#define BCME_BADKEYIDX			-8	/* BAD Key Index */
++#define BCME_RADIOOFF 			-9	/* Radio Off */
++#define BCME_NOTBANDLOCKED		-10	/* Not  band locked */
++#define BCME_NOCLK			-11	/* No Clock */
++#define BCME_BADRATESET			-12	/* BAD Rate valueset */
++#define BCME_BADBAND			-13	/* BAD Band */
++#define BCME_BUFTOOSHORT		-14	/* Buffer too short */
++#define BCME_BUFTOOLONG			-15	/* Buffer too long */
++#define BCME_BUSY			-16	/* Busy */
++#define BCME_NOTASSOCIATED		-17	/* Not Associated */
++#define BCME_BADSSIDLEN			-18	/* Bad SSID len */
++#define BCME_OUTOFRANGECHAN		-19	/* Out of Range Channel */
++#define BCME_BADCHAN			-20	/* Bad Channel */
++#define BCME_BADADDR			-21	/* Bad Address */
++#define BCME_NORESOURCE			-22	/* Not Enough Resources */
++#define BCME_UNSUPPORTED		-23	/* Unsupported */
++#define BCME_BADLEN			-24	/* Bad length */
++#define BCME_NOTREADY			-25	/* Not Ready */
++#define BCME_EPERM			-26	/* Not Permitted */
++#define BCME_NOMEM			-27	/* No Memory */
++#define BCME_ASSOCIATED			-28	/* Associated */
++#define BCME_RANGE			-29	/* Not In Range */
++#define BCME_NOTFOUND			-30	/* Not Found */
++#define BCME_WME_NOT_ENABLED		-31	/* WME Not Enabled */
++#define BCME_TSPEC_NOTFOUND		-32	/* TSPEC Not Found */
++#define BCME_ACM_NOTSUPPORTED		-33	/* ACM Not Supported */
++#define BCME_NOT_WME_ASSOCIATION	-34	/* Not WME Association */
++#define BCME_SDIO_ERROR			-35	/* SDIO Bus Error */
++#define BCME_DONGLE_DOWN		-36	/* Dongle Not Accessible */
++#define BCME_VERSION			-37 	/* Incorrect version */
++#define BCME_TXFAIL			-38 	/* TX failure */
++#define BCME_RXFAIL			-39	/* RX failure */
++#define BCME_NODEVICE			-40 	/* Device not present */
++#define BCME_NMODE_DISABLED		-41 	/* NMODE disabled */
++#define BCME_NONRESIDENT		-42 /* access to nonresident overlay */
++#define BCME_SCANREJECT			-43 	/* reject scan request */
++#define BCME_USAGE_ERROR                -44     /* WLCMD usage error */
++#define BCME_IOCTL_ERROR                -45     /* WLCMD ioctl error */
++#define BCME_SERIAL_PORT_ERR            -46     /* RWL serial port error */
++#define BCME_DISABLED			-47     /* Disabled in this build */
++#define BCME_DECERR				-48		/* Decrypt error */
++#define BCME_ENCERR				-49		/* Encrypt error */
++#define BCME_MICERR				-50		/* Integrity/MIC error */
++#define BCME_REPLAY				-51		/* Replay */
++#define BCME_IE_NOTFOUND		-52		/* IE not found */
++#define BCME_DATA_NOTFOUND		-53		/* Complete data not found in buffer */
++#define BCME_NOT_GC			-54     /* expecting a group client */
++#define BCME_PRS_REQ_FAILED		-55     /* GC presence req failed to sent */
++#define BCME_NO_P2P_SE			-56      /* Could not find P2P-Subelement */
++#define BCME_NOA_PND			-57      /* NoA pending, CB shuld be NULL */
++#define BCME_FRAG_Q_FAILED		-58      /* queueing 80211 frag failedi */
++#define BCME_GET_AF_FAILED		-59      /* Get p2p AF pkt failed */
++#define BCME_MSCH_NOTREADY		-60		/* scheduler not ready */
++#define BCME_LAST   BCME_MSCH_NOTREADY
++
++#define BCME_NOTENABLED BCME_DISABLED
++
++/* This error code is *internal* to the driver, and is not propogated to users. It should
++ * only be used by IOCTL patch handlers as an indication that it did not handle the IOCTL.
++ * (Since the error code is internal, an entry in 'BCMERRSTRINGTABLE' is not required,
++ * nor does it need to be part of any OSL driver-to-OS error code mapping).
++ */
++#define BCME_IOCTL_PATCH_UNSUPPORTED	-9999
++#if (BCME_LAST <= BCME_IOCTL_PATCH_UNSUPPORTED)
++	#error "BCME_LAST <= BCME_IOCTL_PATCH_UNSUPPORTED"
++#endif
++
++/* These are collection of BCME Error strings */
++#define BCMERRSTRINGTABLE {		\
++	"OK",				\
++	"Undefined error",		\
++	"Bad Argument",			\
++	"Bad Option",			\
++	"Not up",			\
++	"Not down",			\
++	"Not AP",			\
++	"Not STA",			\
++	"Bad Key Index",		\
++	"Radio Off",			\
++	"Not band locked",		\
++	"No clock",			\
++	"Bad Rate valueset",		\
++	"Bad Band",			\
++	"Buffer too short",		\
++	"Buffer too long",		\
++	"Busy",				\
++	"Not Associated",		\
++	"Bad SSID len",			\
++	"Out of Range Channel",		\
++	"Bad Channel",			\
++	"Bad Address",			\
++	"Not Enough Resources",		\
++	"Unsupported",			\
++	"Bad length",			\
++	"Not Ready",			\
++	"Not Permitted",		\
++	"No Memory",			\
++	"Associated",			\
++	"Not In Range",			\
++	"Not Found",			\
++	"WME Not Enabled",		\
++	"TSPEC Not Found",		\
++	"ACM Not Supported",		\
++	"Not WME Association",		\
++	"SDIO Bus Error",		\
++	"Dongle Not Accessible",	\
++	"Incorrect version",		\
++	"TX Failure",			\
++	"RX Failure",			\
++	"Device Not Present",		\
++	"NMODE Disabled",		\
++	"Nonresident overlay access", \
++	"Scan Rejected",		\
++	"WLCMD usage error",		\
++	"WLCMD ioctl error",		\
++	"RWL serial port error", 	\
++	"Disabled",			\
++	"Decrypt error", \
++	"Encrypt error", \
++	"MIC error", \
++	"Replay", \
++	"IE not found", \
++	"Data not found", \
++	"NOT GC", \
++	"PRS REQ FAILED", \
++	"NO P2P SubElement", \
++	"NOA Pending", \
++	"FRAG Q FAILED", \
++	"GET ActionFrame failed", \
++	"scheduler not ready", \
++}
++
++#ifndef ABS
++#define	ABS(a)			(((a) < 0) ? -(a) : (a))
++#endif /* ABS */
++
++#ifndef MIN
++#define	MIN(a, b)		(((a) < (b)) ? (a) : (b))
++#endif /* MIN */
++
++#ifndef MAX
++#define	MAX(a, b)		(((a) > (b)) ? (a) : (b))
++#endif /* MAX */
++
++/* limit to [min, max] */
++#ifndef LIMIT_TO_RANGE
++#define LIMIT_TO_RANGE(x, min, max) \
++	((x) < (min) ? (min) : ((x) > (max) ? (max) : (x)))
++#endif /* LIMIT_TO_RANGE */
++
++/* limit to  max */
++#ifndef LIMIT_TO_MAX
++#define LIMIT_TO_MAX(x, max) \
++	(((x) > (max) ? (max) : (x)))
++#endif /* LIMIT_TO_MAX */
++
++/* limit to min */
++#ifndef LIMIT_TO_MIN
++#define LIMIT_TO_MIN(x, min) \
++	(((x) < (min) ? (min) : (x)))
++#endif /* LIMIT_TO_MIN */
++
++#define DELTA(curr, prev) ((curr) > (prev) ? ((curr) - (prev)) : \
++	(0xffffffff - (prev) + (curr) + 1))
++#define CEIL(x, y)		(((x) + ((y) - 1)) / (y))
++#define ROUNDUP(x, y)		((((x) + ((y) - 1)) / (y)) * (y))
++#define ROUNDDN(p, align)	((p) & ~((align) - 1))
++#define	ISALIGNED(a, x)		(((uintptr)(a) & ((x) - 1)) == 0)
++#define ALIGN_ADDR(addr, boundary) (void *)(((uintptr)(addr) + (boundary) - 1) \
++	                                         & ~((boundary) - 1))
++#define ALIGN_SIZE(size, boundary) (((size) + (boundary) - 1) \
++	                                         & ~((boundary) - 1))
++#define	ISPOWEROF2(x)		((((x) - 1) & (x)) == 0)
++#define VALID_MASK(mask)	!((mask) & ((mask) + 1))
++
++#ifndef OFFSETOF
++#ifdef __ARMCC_VERSION
++/*
++ * The ARM RVCT compiler complains when using OFFSETOF where a constant
++ * expression is expected, such as an initializer for a static object.
++ * offsetof from the runtime library doesn't have that problem.
++ */
++#include <stddef.h>
++#define	OFFSETOF(type, member)	offsetof(type, member)
++#else
++#  if ((__GNUC__ >= 4) && (__GNUC_MINOR__ >= 8))
++/* GCC 4.8+ complains when using our OFFSETOF macro in array length declarations. */
++#    define	OFFSETOF(type, member)	__builtin_offsetof(type, member)
++#  else
++#    define	OFFSETOF(type, member)	((uint)(uintptr)&((type *)0)->member)
++#  endif /* GCC 4.8 or newer */
++#endif /* __ARMCC_VERSION */
++#endif /* OFFSETOF */
++
++#ifndef CONTAINEROF
++#define CONTAINEROF(ptr, type, member) ((type *)((char *)(ptr) - OFFSETOF(type, member)))
++#endif /* CONTAINEROF */
++
++#ifndef ARRAYSIZE
++#define ARRAYSIZE(a)		(sizeof(a) / sizeof(a[0]))
++#endif
++
++#ifndef ARRAYLAST /* returns pointer to last array element */
++#define ARRAYLAST(a)		(&a[ARRAYSIZE(a)-1])
++#endif
++
++/* Reference a function; used to prevent a static function from being optimized out */
++extern void *_bcmutils_dummy_fn;
++#define REFERENCE_FUNCTION(f)	(_bcmutils_dummy_fn = (void *)(f))
++
++/* bit map related macros */
++#ifndef setbit
++#ifndef NBBY		/* the BSD family defines NBBY */
++#define	NBBY	8	/* 8 bits per byte */
++#endif /* #ifndef NBBY */
++#ifdef BCMUTILS_BIT_MACROS_USE_FUNCS
++extern void setbit(void *array, uint bit);
++extern void clrbit(void *array, uint bit);
++extern bool isset(const void *array, uint bit);
++extern bool isclr(const void *array, uint bit);
++#else
++#define	setbit(a, i)	(((uint8 *)a)[(i) / NBBY] |= 1 << ((i) % NBBY))
++#define	clrbit(a, i)	(((uint8 *)a)[(i) / NBBY] &= ~(1 << ((i) % NBBY)))
++#define	isset(a, i)	(((const uint8 *)a)[(i) / NBBY] & (1 << ((i) % NBBY)))
++#define	isclr(a, i)	((((const uint8 *)a)[(i) / NBBY] & (1 << ((i) % NBBY))) == 0)
++#endif
++#endif /* setbit */
++extern void set_bitrange(void *array, uint start, uint end, uint maxbit);
++
++#define	isbitset(a, i)	(((a) & (1 << (i))) != 0)
++
++#define	NBITS(type)	(sizeof(type) * 8)
++#define NBITVAL(nbits)	(1 << (nbits))
++#define MAXBITVAL(nbits)	((1 << (nbits)) - 1)
++#define	NBITMASK(nbits)	MAXBITVAL(nbits)
++#define MAXNBVAL(nbyte)	MAXBITVAL((nbyte) * 8)
++
++extern void bcm_bitprint32(const uint32 u32);
++
++/*
++ * ----------------------------------------------------------------------------
++ * Multiword map of 2bits, nibbles
++ * setbit2 setbit4 (void *ptr, uint32 ix, uint32 val)
++ * getbit2 getbit4 (void *ptr, uint32 ix)
++ * ----------------------------------------------------------------------------
++ */
++
++#define DECLARE_MAP_API(NB, RSH, LSH, OFF, MSK)                     \
++static INLINE void setbit##NB(void *ptr, uint32 ix, uint32 val)     \
++{                                                                   \
++	uint32 *addr = (uint32 *)ptr;                                   \
++	uint32 *a = addr + (ix >> RSH); /* (ix / 2^RSH) */              \
++	uint32 pos = (ix & OFF) << LSH; /* (ix % 2^RSH) * 2^LSH */      \
++	uint32 mask = (MSK << pos);                                     \
++	uint32 tmp = *a & ~mask;                                        \
++	*a = tmp | (val << pos);                                        \
++}                                                                   \
++static INLINE uint32 getbit##NB(void *ptr, uint32 ix)               \
++{                                                                   \
++	uint32 *addr = (uint32 *)ptr;                                   \
++	uint32 *a = addr + (ix >> RSH);                                 \
++	uint32 pos = (ix & OFF) << LSH;                                 \
++	return ((*a >> pos) & MSK);                                     \
++}
++
++DECLARE_MAP_API(2, 4, 1, 15U, 0x0003) /* setbit2() and getbit2() */
++DECLARE_MAP_API(4, 3, 2, 7U, 0x000F) /* setbit4() and getbit4() */
++DECLARE_MAP_API(8, 2, 3, 3U, 0x00FF) /* setbit8() and getbit8() */
++
++/* basic mux operation - can be optimized on several architectures */
++#define MUX(pred, true, false) ((pred) ? (true) : (false))
++
++/* modulo inc/dec - assumes x E [0, bound - 1] */
++#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1)
++#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
++
++/* modulo inc/dec, bound = 2^k */
++#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
++#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
++
++/* modulo add/sub - assumes x, y E [0, bound - 1] */
++#define MODADD(x, y, bound) \
++    MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y))
++#define MODSUB(x, y, bound) \
++    MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y))
++
++/* module add/sub, bound = 2^k */
++#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
++#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
++
++/* crc defines */
++#define CRC8_INIT_VALUE  0xff		/* Initial CRC8 checksum value */
++#define CRC8_GOOD_VALUE  0x9f		/* Good final CRC8 checksum value */
++#define CRC16_INIT_VALUE 0xffff		/* Initial CRC16 checksum value */
++#define CRC16_GOOD_VALUE 0xf0b8		/* Good final CRC16 checksum value */
++#define CRC32_INIT_VALUE 0xffffffff	/* Initial CRC32 checksum value */
++#define CRC32_GOOD_VALUE 0xdebb20e3	/* Good final CRC32 checksum value */
++
++/* use for direct output of MAC address in printf etc */
++#define MACF				"%02x:%02x:%02x:%02x:%02x:%02x"
++#define ETHERP_TO_MACF(ea)	((struct ether_addr *) (ea))->octet[0], \
++							((struct ether_addr *) (ea))->octet[1], \
++							((struct ether_addr *) (ea))->octet[2], \
++							((struct ether_addr *) (ea))->octet[3], \
++							((struct ether_addr *) (ea))->octet[4], \
++							((struct ether_addr *) (ea))->octet[5]
++
++#define CONST_ETHERP_TO_MACF(ea) ((const struct ether_addr *) (ea))->octet[0], \
++						 ((const struct ether_addr *) (ea))->octet[1], \
++						 ((const struct ether_addr *) (ea))->octet[2], \
++						 ((const struct ether_addr *) (ea))->octet[3], \
++						 ((const struct ether_addr *) (ea))->octet[4], \
++						 ((const struct ether_addr *) (ea))->octet[5]
++#define ETHER_TO_MACF(ea) (ea).octet[0], \
++							(ea).octet[1], \
++							(ea).octet[2], \
++							(ea).octet[3], \
++							(ea).octet[4], \
++							(ea).octet[5]
++#if !defined(SIMPLE_MAC_PRINT)
++#define MACDBG "%02x:%02x:%02x:%02x:%02x:%02x"
++#define MAC2STRDBG(ea) (ea)[0], (ea)[1], (ea)[2], (ea)[3], (ea)[4], (ea)[5]
++#else
++#define MACDBG				"%02x:%02x:%02x"
++#define MAC2STRDBG(ea) (ea)[0], (ea)[4], (ea)[5]
++#endif /* SIMPLE_MAC_PRINT */
++
++/* bcm_format_flags() bit description structure */
++typedef struct bcm_bit_desc {
++	uint32	bit;
++	const char* name;
++} bcm_bit_desc_t;
++
++/* bcm_format_field */
++typedef struct bcm_bit_desc_ex {
++	uint32 mask;
++	const bcm_bit_desc_t *bitfield;
++} bcm_bit_desc_ex_t;
++
++/* buffer length for ethernet address from bcm_ether_ntoa() */
++#define ETHER_ADDR_STR_LEN	18	/* 18-bytes of Ethernet address buffer length */
++
++static INLINE uint32 /* 32bit word aligned xor-32 */
++bcm_compute_xor32(volatile uint32 *u32_val, int num_u32)
++{
++	int idx;
++	uint32 xor32 = 0;
++	for (idx = 0; idx < num_u32; idx++)
++		xor32 ^= *(u32_val + idx);
++	return xor32;
++}
++
++/* crypto utility function */
++/* 128-bit xor: *dst = *src1 xor *src2. dst1, src1 and src2 may have any alignment */
++static INLINE void
++xor_128bit_block(const uint8 *src1, const uint8 *src2, uint8 *dst)
++{
++	if (
++#ifdef __i386__
++	    1 ||
++#endif
++	    (((uintptr)src1 | (uintptr)src2 | (uintptr)dst) & 3) == 0) {
++		/* ARM CM3 rel time: 1229 (727 if alignment check could be omitted) */
++		/* x86 supports unaligned.  This version runs 6x-9x faster on x86. */
++		((uint32 *)dst)[0] = ((const uint32 *)src1)[0] ^ ((const uint32 *)src2)[0];
++		((uint32 *)dst)[1] = ((const uint32 *)src1)[1] ^ ((const uint32 *)src2)[1];
++		((uint32 *)dst)[2] = ((const uint32 *)src1)[2] ^ ((const uint32 *)src2)[2];
++		((uint32 *)dst)[3] = ((const uint32 *)src1)[3] ^ ((const uint32 *)src2)[3];
++	} else {
++		/* ARM CM3 rel time: 4668 (4191 if alignment check could be omitted) */
++		int k;
++		for (k = 0; k < 16; k++)
++			dst[k] = src1[k] ^ src2[k];
++	}
++}
++
++/* externs */
++/* crc */
++extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
++extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
++extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
++
++/* format/print */
++#if defined(DHD_DEBUG) || defined(WLMSG_PRHDRS) || defined(WLMSG_PRPKT) || \
++	defined(WLMSG_ASSOC)
++/* print out the value a field has: fields may have 1-32 bits and may hold any value */
++extern int bcm_format_field(const bcm_bit_desc_ex_t *bd, uint32 field, char* buf, int len);
++/* print out which bits in flags are set */
++extern int bcm_format_flags(const bcm_bit_desc_t *bd, uint32 flags, char* buf, int len);
++#endif
++
++extern int bcm_format_hex(char *str, const void *bytes, int len);
++
++extern const char *bcm_crypto_algo_name(uint algo);
++extern char *bcm_chipname(uint chipid, char *buf, uint len);
++extern char *bcm_brev_str(uint32 brev, char *buf);
++extern void printbig(char *buf);
++extern void prhex(const char *msg, volatile uchar *buf, uint len);
++
++/* IE parsing */
++
++/* packing is required if struct is passed across the bus */
++#include <packed_section_start.h>
++/* tag_ID/length/value_buffer tuple */
++typedef struct bcm_tlv {
++	uint8	id;
++	uint8	len;
++	uint8	data[1];
++} bcm_tlv_t;
++
++#define BCM_TLV_SIZE(_tlv) ((_tlv) ? (OFFSETOF(bcm_tlv_t, data) + (_tlv)->len) : 0)
++
++#define BCM_XTLV_TAG_LEN_SIZE		4
++
++/* bcm tlv w/ 16 bit id/len */
++typedef BWL_PRE_PACKED_STRUCT struct bcm_xtlv {
++	uint16	id;
++	uint16	len;
++	uint8	data[1];
++} BWL_POST_PACKED_STRUCT bcm_xtlv_t;
++#include <packed_section_end.h>
++
++
++/* descriptor of xtlv data src or dst  */
++typedef struct {
++	uint16	type;
++	uint16	len;
++	void	*ptr; /* ptr to memory location */
++} xtlv_desc_t;
++
++/* xtlv options */
++#define BCM_XTLV_OPTION_NONE	0x0000
++#define BCM_XTLV_OPTION_ALIGN32	0x0001
++
++typedef uint16 bcm_xtlv_opts_t;
++struct bcm_xtlvbuf {
++	bcm_xtlv_opts_t opts;
++	uint16 size;
++	uint8 *head; /* point to head of buffer */
++	uint8 *buf; /* current position of buffer */
++	/* allocated buffer may follow, but not necessarily */
++};
++typedef struct bcm_xtlvbuf bcm_xtlvbuf_t;
++
++#define BCM_TLV_MAX_DATA_SIZE (255)
++#define BCM_XTLV_MAX_DATA_SIZE (65535)
++#define BCM_TLV_HDR_SIZE (OFFSETOF(bcm_tlv_t, data))
++
++#define BCM_XTLV_HDR_SIZE (OFFSETOF(bcm_xtlv_t, data))
++/* LEN only stores the value's length without padding */
++#define BCM_XTLV_LEN(elt) ltoh16_ua(&(elt->len))
++#define BCM_XTLV_ID(elt) ltoh16_ua(&(elt->id))
++/* entire size of the XTLV including header, data, and optional padding */
++#define BCM_XTLV_SIZE(elt, opts) bcm_xtlv_size(elt, opts)
++#define bcm_valid_xtlv(elt, buflen, opts) (elt && ((int)(buflen) >= (int)BCM_XTLV_SIZE(elt, opts)))
++
++/* Check that bcm_tlv_t fits into the given buflen */
++#define bcm_valid_tlv(elt, buflen) (\
++	 ((int)(buflen) >= (int)BCM_TLV_HDR_SIZE) && \
++	 ((int)(buflen) >= (int)(BCM_TLV_HDR_SIZE + (elt)->len)))
++
++
++extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
++extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
++extern bcm_tlv_t *bcm_parse_tlvs_min_bodylen(void *buf, int buflen, uint key, int min_bodylen);
++extern bcm_tlv_t *bcm_parse_tlvs_dot11(void *buf, int buflen, uint key, bool id_ext);
++
++extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
++
++extern bcm_tlv_t *bcm_find_vendor_ie(void *tlvs, int tlvs_len, const char *voui, uint8 *type,
++	int type_len);
++
++extern uint8 *bcm_write_tlv(int type, const void *data, int datalen, uint8 *dst);
++extern uint8 *bcm_write_tlv_safe(int type, const void *data, int datalen, uint8 *dst,
++	int dst_maxlen);
++
++extern uint8 *bcm_copy_tlv(const void *src, uint8 *dst);
++extern uint8 *bcm_copy_tlv_safe(const void *src, uint8 *dst, int dst_maxlen);
++
++/* xtlv */
++
++/* return the next xtlv element, and update buffer len (remaining). Buffer length
++ * updated includes padding as specified by options
++ */
++extern bcm_xtlv_t *bcm_next_xtlv(bcm_xtlv_t *elt, int *buflen, bcm_xtlv_opts_t opts);
++
++/* initialize an xtlv buffer. Use options specified for packing/unpacking using
++ * the buffer. Caller is responsible for allocating both buffers.
++ */
++extern int bcm_xtlv_buf_init(bcm_xtlvbuf_t *tlv_buf, uint8 *buf, uint16 len,
++	bcm_xtlv_opts_t opts);
++
++extern uint16 bcm_xtlv_buf_len(struct bcm_xtlvbuf *tbuf);
++extern uint16 bcm_xtlv_buf_rlen(struct bcm_xtlvbuf *tbuf);
++extern uint8 *bcm_xtlv_buf(struct bcm_xtlvbuf *tbuf);
++extern uint8 *bcm_xtlv_head(struct bcm_xtlvbuf *tbuf);
++extern int bcm_xtlv_put_data(bcm_xtlvbuf_t *tbuf, uint16 type, const void *data, uint16 dlen);
++extern int bcm_xtlv_put_8(bcm_xtlvbuf_t *tbuf, uint16 type, const int8 data);
++extern int bcm_xtlv_put_16(bcm_xtlvbuf_t *tbuf, uint16 type, const int16 data);
++extern int bcm_xtlv_put_32(bcm_xtlvbuf_t *tbuf, uint16 type, const int32 data);
++extern int bcm_unpack_xtlv_entry(uint8 **buf, uint16 xpct_type, uint16 xpct_len,
++	void *dst, bcm_xtlv_opts_t opts);
++extern int bcm_pack_xtlv_entry(uint8 **buf, uint16 *buflen, uint16 type, uint16 len,
++	void *src, bcm_xtlv_opts_t opts);
++extern int bcm_xtlv_size(const bcm_xtlv_t *elt, bcm_xtlv_opts_t opts);
++
++/* callback for unpacking xtlv from a buffer into context. */
++typedef int (bcm_xtlv_unpack_cbfn_t)(void *ctx, uint8 *buf, uint16 type, uint16 len);
++
++/* unpack a tlv buffer using buffer, options, and callback */
++extern int bcm_unpack_xtlv_buf(void *ctx, uint8 *buf, uint16 buflen,
++	bcm_xtlv_opts_t opts, bcm_xtlv_unpack_cbfn_t *cbfn);
++
++/* unpack a set of tlvs from the buffer using provided xtlv desc */
++extern int bcm_unpack_xtlv_buf_to_mem(void *buf, int *buflen, xtlv_desc_t *items,
++	bcm_xtlv_opts_t opts);
++
++/* pack a set of tlvs into buffer using provided xtlv desc */
++extern int bcm_pack_xtlv_buf_from_mem(void **buf, uint16 *buflen, xtlv_desc_t *items,
++	bcm_xtlv_opts_t opts);
++
++/* return data pointer of a given ID from xtlv buffer
++ * xtlv data length is given to *datalen_out, if the pointer is valid
++ */
++extern void *bcm_get_data_from_xtlv_buf(uint8 *tlv_buf, uint16 buflen, uint16 id,
++	uint16 *datalen_out, bcm_xtlv_opts_t opts);
++
++/* callback to return next tlv id and len to pack, if there is more tlvs to come and
++ * options e.g. alignment
++ */
++typedef bool (*bcm_pack_xtlv_next_info_cbfn_t)(void *ctx, uint16 *tlv_id, uint16 *tlv_len);
++
++/* callback to pack the tlv into length validated buffer */
++typedef void (*bcm_pack_xtlv_pack_next_cbfn_t)(void *ctx,
++	uint16 tlv_id, uint16 tlv_len, uint8* buf);
++
++/* pack a set of tlvs into buffer using get_next to interate */
++int bcm_pack_xtlv_buf(void *ctx, void *tlv_buf, uint16 buflen,
++	bcm_xtlv_opts_t opts, bcm_pack_xtlv_next_info_cbfn_t get_next,
++	bcm_pack_xtlv_pack_next_cbfn_t pack_next, int *outlen);
++
++/* bcmerror */
++extern const char *bcmerrorstr(int bcmerror);
++
++extern int wl_set_up_table(uint8 *up_table, bcm_tlv_t *qos_map_ie);
++
++/* multi-bool data type: set of bools, mbool is true if any is set */
++typedef uint32 mbool;
++#define mboolset(mb, bit)		((mb) |= (bit))		/* set one bool */
++#define mboolclr(mb, bit)		((mb) &= ~(bit))	/* clear one bool */
++#define mboolisset(mb, bit)		(((mb) & (bit)) != 0)	/* TRUE if one bool is set */
++#define	mboolmaskset(mb, mask, val)	((mb) = (((mb) & ~(mask)) | (val)))
++
++/* generic datastruct to help dump routines */
++struct fielddesc {
++	const char *nameandfmt;
++	uint32 offset;
++	uint32 len;
++};
++
++extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size);
++extern void bcm_bprhex(struct bcmstrbuf *b, const char *msg, bool newline,
++	const uint8 *buf, int len);
++
++extern void bcm_inc_bytes(uchar *num, int num_bytes, uint8 amount);
++extern int bcm_cmp_bytes(const uchar *arg1, const uchar *arg2, uint8 nbytes);
++extern void bcm_print_bytes(const char *name, const uchar *cdata, int len);
++
++typedef  uint32 (*bcmutl_rdreg_rtn)(void *arg0, uint arg1, uint32 offset);
++extern uint bcmdumpfields(bcmutl_rdreg_rtn func_ptr, void *arg0, uint arg1, struct fielddesc *str,
++                          char *buf, uint32 bufsize);
++extern uint bcm_bitcount(uint8 *bitmap, uint bytelength);
++
++extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...);
++
++/* power conversion */
++extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
++extern uint8 bcm_mw_to_qdbm(uint16 mw);
++extern uint bcm_mkiovar(const char *name, const char *data, uint datalen, char *buf, uint len);
++
++unsigned int process_nvram_vars(char *varbuf, unsigned int len);
++
++/* trace any object allocation / free, with / without features (flags) set to the object */
++
++#define BCM_OBJDBG_ADD           1
++#define BCM_OBJDBG_REMOVE        2
++#define BCM_OBJDBG_ADD_PKT       3
++
++/* object feature: set or clear flags */
++#define BCM_OBJECT_FEATURE_FLAG       1
++#define BCM_OBJECT_FEATURE_PKT_STATE  2
++/* object feature: flag bits */
++#define BCM_OBJECT_FEATURE_0     (1 << 0)
++#define BCM_OBJECT_FEATURE_1     (1 << 1)
++#define BCM_OBJECT_FEATURE_2     (1 << 2)
++/* object feature: clear flag bits field set with this flag */
++#define BCM_OBJECT_FEATURE_CLEAR (1 << 31)
++#ifdef BCM_OBJECT_TRACE
++#define bcm_pkt_validate_chk(obj)	do { \
++	void * pkttag; \
++	bcm_object_trace_chk(obj, 0, 0, \
++		__FUNCTION__, __LINE__); \
++	if ((pkttag = PKTTAG(obj))) { \
++		bcm_object_trace_chk(obj, 1, DHD_PKTTAG_SN(pkttag), \
++			__FUNCTION__, __LINE__); \
++	} \
++} while (0)
++extern void bcm_object_trace_opr(void *obj, uint32 opt, const char *caller, int line);
++extern void bcm_object_trace_upd(void *obj, void *obj_new);
++extern void bcm_object_trace_chk(void *obj, uint32 chksn, uint32 sn,
++	const char *caller, int line);
++extern void bcm_object_feature_set(void *obj, uint32 type, uint32 value);
++extern int  bcm_object_feature_get(void *obj, uint32 type, uint32 value);
++extern void bcm_object_trace_init(void);
++extern void bcm_object_trace_deinit(void);
++#else
++#define bcm_pkt_validate_chk(obj)
++#define bcm_object_trace_opr(a, b, c, d)
++#define bcm_object_trace_upd(a, b)
++#define bcm_object_trace_chk(a, b, c, d, e)
++#define bcm_object_feature_set(a, b, c)
++#define bcm_object_feature_get(a, b, c)
++#define bcm_object_trace_init()
++#define bcm_object_trace_deinit()
++#endif /* BCM_OBJECT_TRACE */
++
++/* calculate a * b + c */
++extern void bcm_uint64_multiple_add(uint32* r_high, uint32* r_low, uint32 a, uint32 b, uint32 c);
++/* calculate a / b */
++extern void bcm_uint64_divide(uint32* r, uint32 a_high, uint32 a_low, uint32 b);
++
++
++/* Public domain bit twiddling hacks/utilities: Sean Eron Anderson */
++
++/* Table driven count set bits. */
++static const uint8 /* Table only for use by bcm_cntsetbits */
++_CSBTBL[256] =
++{
++#	define B2(n)    n,     n + 1,     n + 1,     n + 2
++#	define B4(n) B2(n), B2(n + 1), B2(n + 1), B2(n + 2)
++#	define B6(n) B4(n), B4(n + 1), B4(n + 1), B4(n + 2)
++	B6(0), B6(0 + 1), B6(0 + 1), B6(0 + 2)
++};
++
++static INLINE uint32 /* Uses table _CSBTBL for fast counting of 1's in a u32 */
++bcm_cntsetbits(const uint32 u32arg)
++{
++	/* function local scope declaration of const _CSBTBL[] */
++	const uint8 * p = (const uint8 *)&u32arg;
++	return (_CSBTBL[p[0]] + _CSBTBL[p[1]] + _CSBTBL[p[2]] + _CSBTBL[p[3]]);
++}
++
++
++static INLINE int /* C equivalent count of leading 0's in a u32 */
++C_bcm_count_leading_zeros(uint32 u32arg)
++{
++	int shifts = 0;
++	while (u32arg) {
++		shifts++; u32arg >>= 1;
++	}
++	return (32U - shifts);
++}
++
++#ifdef BCM_ASLR_HEAP
++
++#define BCM_NVRAM_OFFSET_TCM	4
++#define BCM_NVRAM_IMG_COMPRS_FACTOR	4
++#define BCM_RNG_SIGNATURE	0xFEEDC0DE
++
++typedef struct bcm_rand_metadata {
++	uint32 signature;	/* host fills it in, FW verfies before reading rand */
++	uint32 count;	/* number of 4byte wide random numbers */
++} bcm_rand_metadata_t;
++#endif /* BCM_ASLR_HEAP */
++
++#ifdef BCMDRIVER
++/*
++ * Assembly instructions: Count Leading Zeros
++ * "clz"	: MIPS, ARM
++ * "cntlzw"	: PowerPC
++ * "BSF"	: x86
++ * "lzcnt"	: AMD, SPARC
++ */
++
++#if defined(__arm__)
++#if defined(__ARM_ARCH_7M__) /* Cortex M3 */
++#define __USE_ASM_CLZ__
++#endif /* __ARM_ARCH_7M__ */
++#if defined(__ARM_ARCH_7R__) /* Cortex R4 */
++#define __USE_ASM_CLZ__
++#endif /* __ARM_ARCH_7R__ */
++#endif /* __arm__ */
++
++static INLINE int
++bcm_count_leading_zeros(uint32 u32arg)
++{
++#if defined(__USE_ASM_CLZ__)
++	int zeros;
++	__asm__ volatile("clz    %0, %1 \n" : "=r" (zeros) : "r"  (u32arg));
++	return zeros;
++#else	/* C equivalent */
++	return C_bcm_count_leading_zeros(u32arg);
++#endif  /* C equivalent */
++}
++
++/*
++ * Macro to count leading zeroes
++ *
++ */
++#if defined(__GNUC__)
++#define CLZ(x) __builtin_clzl(x)
++#elif defined(__arm__)
++#define CLZ(x) __clz(x)
++#else
++#define CLZ(x) bcm_count_leading_zeros(x)
++#endif /* __GNUC__ */
++
++/* INTERFACE: Multiword bitmap based small id allocator. */
++struct bcm_mwbmap;	/* forward declaration for use as an opaque mwbmap handle */
++
++#define BCM_MWBMAP_INVALID_HDL	((struct bcm_mwbmap *)NULL)
++#define BCM_MWBMAP_INVALID_IDX	((uint32)(~0U))
++
++/* Incarnate a multiword bitmap based small index allocator */
++extern struct bcm_mwbmap * bcm_mwbmap_init(osl_t * osh, uint32 items_max);
++
++/* Free up the multiword bitmap index allocator */
++extern void bcm_mwbmap_fini(osl_t * osh, struct bcm_mwbmap * mwbmap_hdl);
++
++/* Allocate a unique small index using a multiword bitmap index allocator */
++extern uint32 bcm_mwbmap_alloc(struct bcm_mwbmap * mwbmap_hdl);
++
++/* Force an index at a specified position to be in use */
++extern void bcm_mwbmap_force(struct bcm_mwbmap * mwbmap_hdl, uint32 bitix);
++
++/* Free a previously allocated index back into the multiword bitmap allocator */
++extern void bcm_mwbmap_free(struct bcm_mwbmap * mwbmap_hdl, uint32 bitix);
++
++/* Fetch the toal number of free indices in the multiword bitmap allocator */
++extern uint32 bcm_mwbmap_free_cnt(struct bcm_mwbmap * mwbmap_hdl);
++
++/* Determine whether an index is inuse or free */
++extern bool bcm_mwbmap_isfree(struct bcm_mwbmap * mwbmap_hdl, uint32 bitix);
++
++/* Debug dump a multiword bitmap allocator */
++extern void bcm_mwbmap_show(struct bcm_mwbmap * mwbmap_hdl);
++
++extern void bcm_mwbmap_audit(struct bcm_mwbmap * mwbmap_hdl);
++/* End - Multiword bitmap based small Id allocator. */
++
++
++/* INTERFACE: Simple unique 16bit Id Allocator using a stack implementation. */
++
++#define ID8_INVALID     0xFFu
++#define ID16_INVALID    0xFFFFu
++#define ID32_INVALID    0xFFFFFFFFu
++#define ID16_UNDEFINED              ID16_INVALID
++
++/*
++ * Construct a 16bit id allocator, managing 16bit ids in the range:
++ *    [start_val16 .. start_val16+total_ids)
++ * Note: start_val16 is inclusive.
++ * Returns an opaque handle to the 16bit id allocator.
++ */
++extern void * id16_map_init(osl_t *osh, uint16 total_ids, uint16 start_val16);
++extern void * id16_map_fini(osl_t *osh, void * id16_map_hndl);
++extern void id16_map_clear(void * id16_map_hndl, uint16 total_ids, uint16 start_val16);
++
++/* Allocate a unique 16bit id */
++extern uint16 id16_map_alloc(void * id16_map_hndl);
++
++/* Free a 16bit id value into the id16 allocator */
++extern void id16_map_free(void * id16_map_hndl, uint16 val16);
++
++/* Get the number of failures encountered during id allocation. */
++extern uint32 id16_map_failures(void * id16_map_hndl);
++
++/* Audit the 16bit id allocator state. */
++extern bool id16_map_audit(void * id16_map_hndl);
++/* End - Simple 16bit Id Allocator. */
++#endif /* BCMDRIVER */
++
++extern void bcm_uint64_right_shift(uint32* r, uint32 a_high, uint32 a_low, uint32 b);
++
++void bcm_add_64(uint32* r_hi, uint32* r_lo, uint32 offset);
++void bcm_sub_64(uint32* r_hi, uint32* r_lo, uint32 offset);
++
++uint64 fp_mult_64(uint64 val1, uint64 val2, uint8 nf1, uint8 nf2, uint8 nf_res);
++uint8 fp_div_64(uint64 num, uint32 den, uint8 nf_num, uint8 nf_den, uint32 *div_out);
++uint8 fp_calc_head_room_64(uint64 num);
++uint8 fp_calc_head_room_32(uint32 num);
++uint32 fp_round_64(uint64 num, uint8 rnd_pos);
++uint32 fp_round_32(uint32 num, uint8 rnd_pos);
++uint32 fp_floor_64(uint64 num, uint8 floor_pos);
++uint32 fp_floor_32(uint32 num, uint8 floor_pos);
++uint32 fp_ceil_64(uint64 num, uint8 ceil_pos);
++uint64 bcm_shl_64(uint64 input, uint8 shift_amt);
++uint64 bcm_shr_64(uint64 input, uint8 shift_amt);
++
++#define MASK_32_BITS	(~0)
++#define MASK_8_BITS	((1 << 8) - 1)
++
++#define EXTRACT_LOW32(num)	(uint32)(num & MASK_32BITS)
++#define EXTRACT_HIGH32(num)	(uint32)(((uint64)num >> 32) & MASK_32BITS)
++
++#define MAXIMUM(a, b) ((a > b) ? a : b)
++#define MINIMUM(a, b) ((a < b) ? a : b)
++#define LIMIT(x, min, max) ((x) < (min) ? (min) : ((x) > (max) ? (max) : (x)))
++
++/* calculate checksum for ip header, tcp / udp header / data */
++uint16 bcm_ip_cksum(uint8 *buf, uint32 len, uint32 sum);
++
++#ifndef _dll_t_
++#define _dll_t_
++/*
++ * -----------------------------------------------------------------------------
++ *                      Double Linked List Macros
++ * -----------------------------------------------------------------------------
++ *
++ * All dll operations must be performed on a pre-initialized node.
++ * Inserting an uninitialized node into a list effectively initialized it.
++ *
++ * When a node is deleted from a list, you may initialize it to avoid corruption
++ * incurred by double deletion. You may skip initialization if the node is
++ * immediately inserted into another list.
++ *
++ * By placing a dll_t element at the start of a struct, you may cast a dll_t *
++ * to the struct or vice versa.
++ *
++ * Example of declaring an initializing someList and inserting nodeA, nodeB
++ *
++ *     typedef struct item {
++ *         dll_t node;
++ *         int someData;
++ *     } Item_t;
++ *     Item_t nodeA, nodeB, nodeC;
++ *     nodeA.someData = 11111, nodeB.someData = 22222, nodeC.someData = 33333;
++ *
++ *     dll_t someList;
++ *     dll_init(&someList);
++ *
++ *     dll_append(&someList, (dll_t *) &nodeA);
++ *     dll_prepend(&someList, &nodeB.node);
++ *     dll_insert((dll_t *)&nodeC, &nodeA.node);
++ *
++ *     dll_delete((dll_t *) &nodeB);
++ *
++ * Example of a for loop to walk someList of node_p
++ *
++ *   extern void mydisplay(Item_t * item_p);
++ *
++ *   dll_t * item_p, * next_p;
++ *   for (item_p = dll_head_p(&someList); ! dll_end(&someList, item_p);
++ *        item_p = next_p)
++ *   {
++ *       next_p = dll_next_p(item_p);
++ *       ... use item_p at will, including removing it from list ...
++ *       mydisplay((PItem_t)item_p);
++ *   }
++ *
++ * -----------------------------------------------------------------------------
++ */
++typedef struct dll {
++	struct dll * next_p;
++	struct dll * prev_p;
++} dll_t;
++
++static INLINE void
++dll_init(dll_t *node_p)
++{
++	node_p->next_p = node_p;
++	node_p->prev_p = node_p;
++}
++/* dll macros returing a pointer to dll_t */
++
++static INLINE dll_t *
++dll_head_p(dll_t *list_p)
++{
++	return list_p->next_p;
++}
++
++
++static INLINE dll_t *
++dll_tail_p(dll_t *list_p)
++{
++	return (list_p)->prev_p;
++}
++
++
++static INLINE dll_t *
++dll_next_p(dll_t *node_p)
++{
++	return (node_p)->next_p;
++}
++
++
++static INLINE dll_t *
++dll_prev_p(dll_t *node_p)
++{
++	return (node_p)->prev_p;
++}
++
++
++static INLINE bool
++dll_empty(dll_t *list_p)
++{
++	return ((list_p)->next_p == (list_p));
++}
++
++
++static INLINE bool
++dll_end(dll_t *list_p, dll_t * node_p)
++{
++	return (list_p == node_p);
++}
++
++
++/* inserts the node new_p "after" the node at_p */
++static INLINE void
++dll_insert(dll_t *new_p, dll_t * at_p)
++{
++	new_p->next_p = at_p->next_p;
++	new_p->prev_p = at_p;
++	at_p->next_p = new_p;
++	(new_p->next_p)->prev_p = new_p;
++}
++
++static INLINE void
++dll_append(dll_t *list_p, dll_t *node_p)
++{
++	dll_insert(node_p, dll_tail_p(list_p));
++}
++
++static INLINE void
++dll_prepend(dll_t *list_p, dll_t *node_p)
++{
++	dll_insert(node_p, list_p);
++}
++
++
++/* deletes a node from any list that it "may" be in, if at all. */
++static INLINE void
++dll_delete(dll_t *node_p)
++{
++	node_p->prev_p->next_p = node_p->next_p;
++	node_p->next_p->prev_p = node_p->prev_p;
++}
++#endif  /* ! defined(_dll_t_) */
++
++/* Elements managed in a double linked list */
++
++typedef struct dll_pool {
++	dll_t       free_list;
++	uint16      free_count;
++	uint16      elems_max;
++	uint16      elem_size;
++	dll_t       elements[1];
++} dll_pool_t;
++
++dll_pool_t * dll_pool_init(void * osh, uint16 elems_max, uint16 elem_size);
++void * dll_pool_alloc(dll_pool_t * dll_pool_p);
++void dll_pool_free(dll_pool_t * dll_pool_p, void * elem_p);
++void dll_pool_free_tail(dll_pool_t * dll_pool_p, void * elem_p);
++typedef void (* dll_elem_dump)(void * elem_p);
++void dll_pool_detach(void * osh, dll_pool_t * pool, uint16 elems_max, uint16 elem_size);
++
++/* calculate IPv4 header checksum
++ * - input ip points to IP header in network order
++ * - output cksum is in network order
++ */
++uint16 ipv4_hdr_cksum(uint8 *ip, int ip_len);
++
++/* calculate IPv4 TCP header checksum
++ * - input ip and tcp points to IP and TCP header in network order
++ * - output cksum is in network order
++ */
++uint16 ipv4_tcp_hdr_cksum(uint8 *ip, uint8 *tcp, uint16 tcp_len);
++
++/* calculate IPv6 TCP header checksum
++ * - input ipv6 and tcp points to IPv6 and TCP header in network order
++ * - output cksum is in network order
++ */
++uint16 ipv6_tcp_hdr_cksum(uint8 *ipv6, uint8 *tcp, uint16 tcp_len);
++
++#ifdef __cplusplus
++	}
++#endif
++
++/* #define DEBUG_COUNTER */
++#ifdef DEBUG_COUNTER
++#define CNTR_TBL_MAX 10
++typedef struct _counter_tbl_t {
++	char name[16];				/* name of this counter table */
++	uint32 prev_log_print;		/* Internal use. Timestamp of the previous log print */
++	uint log_print_interval;	/* Desired interval to print logs in ms */
++	uint needed_cnt;			/* How many counters need to be used */
++	uint32 cnt[CNTR_TBL_MAX];		/* Counting entries to increase at desired places */
++	bool enabled;				/* Whether to enable printing log */
++} counter_tbl_t;
++
++
++void counter_printlog(counter_tbl_t *ctr_tbl);
++#endif /* DEBUG_COUNTER */
++
++#if defined(__GNUC__)
++#define CALL_SITE __builtin_return_address(0)
++#else
++#define CALL_SITE ((void*) 0)
++#endif
++#ifdef SHOW_LOGTRACE
++#define TRACE_LOG_BUF_MAX_SIZE 1500
++#define BUF_NOT_AVAILABLE	0
++#define NEXT_BUF_NOT_AVAIL	1
++#define NEXT_BUF_AVAIL		2
++
++typedef struct trace_buf_info {
++	int availability;
++	int size;
++	char buf[TRACE_LOG_BUF_MAX_SIZE];
++} trace_buf_info_t;
++#endif /* SHOW_LOGTRACE */
++
++#endif	/* _bcmutils_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/brcm_nl80211.h b/module_drivers/drivers/net/wireless/bcmdhd/include/brcm_nl80211.h
+new file mode 100644
+index 000000000..cca207bdd
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/brcm_nl80211.h
+@@ -0,0 +1,73 @@
++/*
++ * Definitions for nl80211 vendor command/event access to host driver
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: brcm_nl80211.h 601873 2015-11-24 11:04:28Z $
++ *
++ */
++
++#ifndef _brcm_nl80211_h_
++#define _brcm_nl80211_h_
++
++#define OUI_BRCM  0x001018
++#define OUI_GOOGLE  0x001A11
++
++enum wl_vendor_subcmd {
++	BRCM_VENDOR_SCMD_UNSPEC		= 0,
++	BRCM_VENDOR_SCMD_PRIV_STR	= 1,
++	BRCM_VENDOR_SCMD_BCM_STR	= 2,
++	BRCM_VENDOR_SCMD_BCM_PSK	= 3,
++	BRCM_VENDOR_SCMD_SET_PMK	= 4,
++	BRCM_VENDOR_SCMD_GET_FEATURES	= 5,
++	BRCM_VENDOR_SCMD_MAX		= 6
++};
++
++
++struct bcm_nlmsg_hdr {
++	uint cmd;	/* common ioctl definition */
++	int len;	/* expected return buffer length */
++	uint offset;	/* user buffer offset */
++	uint set;	/* get or set request optional */
++	uint magic;	/* magic number for verification */
++};
++
++enum bcmnl_attrs {
++	BCM_NLATTR_UNSPEC,
++
++	BCM_NLATTR_LEN,
++	BCM_NLATTR_DATA,
++
++	__BCM_NLATTR_AFTER_LAST,
++	BCM_NLATTR_MAX = __BCM_NLATTR_AFTER_LAST - 1
++};
++
++struct nl_prv_data {
++	int err;			/* return result */
++	void *data;			/* ioctl return buffer pointer */
++	uint len;			/* ioctl return buffer length */
++	struct bcm_nlmsg_hdr *nlioc;	/* bcm_nlmsg_hdr header pointer */
++};
++
++#endif /* _brcm_nl80211_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/dbus.h b/module_drivers/drivers/net/wireless/bcmdhd/include/dbus.h
+new file mode 100644
+index 000000000..4c31c1201
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/dbus.h
+@@ -0,0 +1,600 @@
++/*
++ * Dongle BUS interface Abstraction layer
++ *   target serial buses like USB, SDIO, SPI, etc.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dbus.h 596371 2015-10-30 22:43:47Z $
++ */
++
++#ifndef __DBUS_H__
++#define __DBUS_H__
++
++#include "typedefs.h"
++#include <dhd_linux.h>
++
++extern uint dbus_msglevel;
++#define DBUS_ERROR_VAL	0x0001
++#define DBUS_TRACE_VAL	0x0002
++#define DBUS_INFO_VAL	0x0004
++
++#if defined(DHD_DEBUG)
++#define DBUSERR(args)		do {if (dbus_msglevel & DBUS_ERROR_VAL) printf args;} while (0)
++#define DBUSTRACE(args)		do {if (dbus_msglevel & DBUS_TRACE_VAL) printf args;} while (0)
++#define DBUSINFO(args)		do {if (dbus_msglevel & DBUS_INFO_VAL) printf args;} while (0)
++#else /* defined(DHD_DEBUG) */
++#define DBUSERR(args)
++#define DBUSTRACE(args)
++#define DBUSINFO(args)
++#endif
++
++enum {
++	DBUS_OK = 0,
++	DBUS_ERR = -200,
++	DBUS_ERR_TIMEOUT,
++	DBUS_ERR_DISCONNECT,
++	DBUS_ERR_NODEVICE,
++	DBUS_ERR_UNSUPPORTED,
++	DBUS_ERR_PENDING,
++	DBUS_ERR_NOMEM,
++	DBUS_ERR_TXFAIL,
++	DBUS_ERR_TXTIMEOUT,
++	DBUS_ERR_TXDROP,
++	DBUS_ERR_RXFAIL,
++	DBUS_ERR_RXDROP,
++	DBUS_ERR_TXCTLFAIL,
++	DBUS_ERR_RXCTLFAIL,
++	DBUS_ERR_REG_PARAM,
++	DBUS_STATUS_CANCELLED,
++	DBUS_ERR_NVRAM,
++	DBUS_JUMBO_NOMATCH,
++	DBUS_JUMBO_BAD_FORMAT,
++	DBUS_NVRAM_NONTXT,
++	DBUS_ERR_RXZLP
++};
++
++#define BCM_OTP_SIZE_43236  84	/* number of 16 bit values */
++#define BCM_OTP_SW_RGN_43236	24  /* start offset of SW config region */
++#define BCM_OTP_ADDR_43236 0x18000800 /* address of otp base */
++
++#define ERR_CBMASK_TXFAIL		0x00000001
++#define ERR_CBMASK_RXFAIL		0x00000002
++#define ERR_CBMASK_ALL			0xFFFFFFFF
++
++#define DBUS_CBCTL_WRITE			0
++#define DBUS_CBCTL_READ				1
++#if defined(INTR_EP_ENABLE)
++#define DBUS_CBINTR_POLL			2
++#endif /* defined(INTR_EP_ENABLE) */
++
++#define DBUS_TX_RETRY_LIMIT		3		/* retries for failed txirb */
++#define DBUS_TX_TIMEOUT_INTERVAL	250		/* timeout for txirb complete, in ms */
++
++#define DBUS_BUFFER_SIZE_TX	32000
++#define DBUS_BUFFER_SIZE_RX	24000
++
++#define DBUS_BUFFER_SIZE_TX_NOAGG	2048
++#define DBUS_BUFFER_SIZE_RX_NOAGG	2048
++
++/** DBUS types */
++enum {
++	DBUS_USB,
++	DBUS_SDIO,
++	DBUS_SPI,
++	DBUS_UNKNOWN
++};
++
++enum dbus_state {
++	DBUS_STATE_DL_PENDING,
++	DBUS_STATE_DL_DONE,
++	DBUS_STATE_UP,
++	DBUS_STATE_DOWN,
++	DBUS_STATE_PNP_FWDL,
++	DBUS_STATE_DISCONNECT,
++	DBUS_STATE_SLEEP,
++	DBUS_STATE_DL_NEEDED
++};
++
++enum dbus_pnp_state {
++	DBUS_PNP_DISCONNECT,
++	DBUS_PNP_SLEEP,
++	DBUS_PNP_RESUME
++};
++
++enum dbus_file {
++    DBUS_FIRMWARE,
++    DBUS_NVFILE
++};
++
++typedef enum _DEVICE_SPEED {
++	INVALID_SPEED = -1,
++	LOW_SPEED     =  1,	/**< USB 1.1: 1.5 Mbps */
++	FULL_SPEED,     	/**< USB 1.1: 12  Mbps */
++	HIGH_SPEED,		/**< USB 2.0: 480 Mbps */
++	SUPER_SPEED,		/**< USB 3.0: 4.8 Gbps */
++} DEVICE_SPEED;
++
++typedef struct {
++	int bustype;
++	int vid;
++	int pid;
++	int devid;
++	int chiprev; /**< chip revsion number */
++	int mtu;
++	int nchan; /**< Data Channels */
++	int has_2nd_bulk_in_ep;
++} dbus_attrib_t;
++
++/* FIX: Account for errors related to DBUS;
++ * Let upper layer account for packets/bytes
++ */
++typedef struct {
++	uint32 rx_errors;
++	uint32 tx_errors;
++	uint32 rx_dropped;
++	uint32 tx_dropped;
++} dbus_stats_t;
++
++/**
++ * Configurable BUS parameters
++ */
++enum {
++	DBUS_CONFIG_ID_RXCTL_DEFERRES = 1,
++	DBUS_CONFIG_ID_AGGR_LIMIT,
++	DBUS_CONFIG_ID_KEEPIF_ON_DEVRESET
++};
++
++typedef struct {
++	uint32 config_id;
++	union {
++		uint32 general_param;
++		bool rxctl_deferrespok;
++		struct {
++			int maxrxsf;
++			int maxrxsize;
++			int maxtxsf;
++			int maxtxsize;
++		} aggr_param;
++	};
++} dbus_config_t;
++
++/**
++ * External Download Info
++ */
++typedef struct dbus_extdl {
++	uint8 *fw;
++	int fwlen;
++	uint8 *vars;
++	int varslen;
++} dbus_extdl_t;
++
++struct dbus_callbacks;
++struct exec_parms;
++
++typedef void *(*probe_cb_t)(void *arg, const char *desc, uint32 bustype,
++	uint16 bus_no, uint16 slot, uint32 hdrlen);
++typedef void (*disconnect_cb_t)(void *arg);
++typedef void *(*exec_cb_t)(struct exec_parms *args);
++
++/** Client callbacks registered during dbus_attach() */
++typedef struct dbus_callbacks {
++	void (*send_complete)(void *cbarg, void *info, int status);
++	void (*recv_buf)(void *cbarg, uint8 *buf, int len);
++	void (*recv_pkt)(void *cbarg, void *pkt);
++	void (*txflowcontrol)(void *cbarg, bool onoff);
++	void (*errhandler)(void *cbarg, int err);
++	void (*ctl_complete)(void *cbarg, int type, int status);
++	void (*state_change)(void *cbarg, int state);
++	void *(*pktget)(void *cbarg, uint len, bool send);
++	void (*pktfree)(void *cbarg, void *p, bool send);
++} dbus_callbacks_t;
++
++struct dbus_pub;
++struct bcmstrbuf;
++struct dbus_irb;
++struct dbus_irb_rx;
++struct dbus_irb_tx;
++struct dbus_intf_callbacks;
++
++typedef struct {
++	void* (*attach)(struct dbus_pub *pub, void *cbarg, struct dbus_intf_callbacks *cbs);
++	void (*detach)(struct dbus_pub *pub, void *bus);
++
++	int (*up)(void *bus);
++	int (*down)(void *bus);
++	int (*send_irb)(void *bus, struct dbus_irb_tx *txirb);
++	int (*recv_irb)(void *bus, struct dbus_irb_rx *rxirb);
++	int (*cancel_irb)(void *bus, struct dbus_irb_tx *txirb);
++	int (*send_ctl)(void *bus, uint8 *buf, int len);
++	int (*recv_ctl)(void *bus, uint8 *buf, int len);
++	int (*get_stats)(void *bus, dbus_stats_t *stats);
++	int (*get_attrib)(void *bus, dbus_attrib_t *attrib);
++
++	int (*pnp)(void *bus, int evnt);
++	int (*remove)(void *bus);
++	int (*resume)(void *bus);
++	int (*suspend)(void *bus);
++	int (*stop)(void *bus);
++	int (*reset)(void *bus);
++
++	/* Access to bus buffers directly */
++	void *(*pktget)(void *bus, int len);
++	void (*pktfree)(void *bus, void *pkt);
++
++	int  (*iovar_op)(void *bus, const char *name, void *params, int plen, void *arg, int len,
++		bool set);
++	void (*dump)(void *bus, struct bcmstrbuf *strbuf);
++	int  (*set_config)(void *bus, dbus_config_t *config);
++	int  (*get_config)(void *bus, dbus_config_t *config);
++
++	bool (*device_exists)(void *bus);
++	int (*dlneeded)(void *bus);
++	int  (*dlstart)(void *bus, uint8 *fw, int len);
++	int  (*dlrun)(void *bus);
++	bool (*recv_needed)(void *bus);
++
++	void *(*exec_rxlock)(void *bus, exec_cb_t func, struct exec_parms *args);
++	void *(*exec_txlock)(void *bus, exec_cb_t func, struct exec_parms *args);
++
++	int (*tx_timer_init)(void *bus);
++	int (*tx_timer_start)(void *bus, uint timeout);
++	int (*tx_timer_stop)(void *bus);
++
++	int (*sched_dpc)(void *bus);
++	int (*lock)(void *bus);
++	int (*unlock)(void *bus);
++	int (*sched_probe_cb)(void *bus);
++
++	int (*shutdown)(void *bus);
++
++	int (*recv_stop)(void *bus);
++	int (*recv_resume)(void *bus);
++
++	int (*recv_irb_from_ep)(void *bus, struct dbus_irb_rx *rxirb, uint ep_idx);
++
++	int (*readreg)(void *bus, uint32 regaddr, int datalen, uint32 *value);
++
++	/* Add from the bottom */
++} dbus_intf_t;
++
++typedef struct dbus_pub {
++	struct osl_info *osh;
++	dbus_stats_t stats;
++	dbus_attrib_t attrib;
++	enum dbus_state busstate;
++	DEVICE_SPEED device_speed;
++	int ntxq, nrxq, rxsize;
++	void *bus;
++	struct shared_info *sh;
++	void *dev_info;
++} dbus_pub_t;
++
++#define BUS_INFO(bus, type) (((type *) bus)->pub->bus)
++
++#define	ALIGNED_LOCAL_VARIABLE(var, align)					\
++	uint8	buffer[SDALIGN+64];						\
++	uint8	*var = (uint8 *)(((uintptr)&buffer[0]) & ~(align-1)) + align;
++
++/*
++ * Public Bus Function Interface
++ */
++
++/*
++ * FIX: Is there better way to pass OS/Host handles to DBUS but still
++ *      maintain common interface for all OS??
++ * Under NDIS, param1 needs to be MiniportHandle
++ *  For NDIS60, param2 is WdfDevice
++ * Under Linux, param1 and param2 are NULL;
++ */
++extern int dbus_register(int vid, int pid, probe_cb_t prcb, disconnect_cb_t discb, void *prarg,
++	void *param1, void *param2);
++extern int dbus_deregister(void);
++
++//extern int dbus_download_firmware(dbus_pub_t *pub);
++//extern int dbus_up(struct dhd_bus *pub);
++extern int dbus_down(dbus_pub_t *pub);
++//extern int dbus_stop(struct dhd_bus *pub);
++extern int dbus_shutdown(dbus_pub_t *pub);
++extern void dbus_flowctrl_rx(dbus_pub_t *pub, bool on);
++
++extern int dbus_send_txdata(dbus_pub_t *dbus, void *pktbuf);
++extern int dbus_send_buf(dbus_pub_t *pub, uint8 *buf, int len, void *info);
++extern int dbus_send_pkt(dbus_pub_t *pub, void *pkt, void *info);
++//extern int dbus_send_ctl(struct dhd_bus *pub, uint8 *buf, int len);
++//extern int dbus_recv_ctl(struct dhd_bus *pub, uint8 *buf, int len);
++extern int dbus_recv_bulk(dbus_pub_t *pub, uint32 ep_idx);
++extern int dbus_poll_intr(dbus_pub_t *pub);
++extern int dbus_get_stats(dbus_pub_t *pub, dbus_stats_t *stats);
++extern int dbus_get_device_speed(dbus_pub_t *pub);
++extern int dbus_set_config(dbus_pub_t *pub, dbus_config_t *config);
++extern int dbus_get_config(dbus_pub_t *pub, dbus_config_t *config);
++extern void * dbus_get_devinfo(dbus_pub_t *pub);
++
++extern void *dbus_pktget(dbus_pub_t *pub, int len);
++extern void dbus_pktfree(dbus_pub_t *pub, void* pkt);
++
++extern int dbus_set_errmask(dbus_pub_t *pub, uint32 mask);
++extern int dbus_pnp_sleep(dbus_pub_t *pub);
++extern int dbus_pnp_resume(dbus_pub_t *pub, int *fw_reload);
++extern int dbus_pnp_disconnect(dbus_pub_t *pub);
++
++//extern int dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
++//	void *params, int plen, void *arg, int len, bool set);
++
++extern void *dhd_dbus_txq(const dbus_pub_t *pub);
++extern uint dhd_dbus_hdrlen(const dbus_pub_t *pub);
++
++/*
++ * Private Common Bus Interface
++ */
++
++/** IO Request Block (IRB) */
++typedef struct dbus_irb {
++	struct dbus_irb *next;	/**< it's casted from dbus_irb_tx or dbus_irb_rx struct */
++} dbus_irb_t;
++
++typedef struct dbus_irb_rx {
++	struct dbus_irb irb; /* Must be first */
++	uint8 *buf;
++	int buf_len;
++	int actual_len;
++	void *pkt;
++	void *info;
++	void *arg;
++} dbus_irb_rx_t;
++
++typedef struct dbus_irb_tx {
++	struct dbus_irb irb; 	/** Must be first */
++	uint8 *buf;		/** mutually exclusive with struct member 'pkt' */
++	int len;		/** length of field 'buf' */
++	void *pkt;		/** mutually exclusive with struct member 'buf' */
++	int retry_count;
++	void *info;
++	void *arg;
++	void *send_buf;		/**< linear  bufffer for LINUX when aggreagtion is enabled */
++} dbus_irb_tx_t;
++
++/**
++ * DBUS interface callbacks are different from user callbacks
++ * so, internally, different info can be passed to upper layer
++ */
++typedef struct dbus_intf_callbacks {
++	void (*send_irb_timeout)(void *cbarg, dbus_irb_tx_t *txirb);
++	void (*send_irb_complete)(void *cbarg, dbus_irb_tx_t *txirb, int status);
++	void (*recv_irb_complete)(void *cbarg, dbus_irb_rx_t *rxirb, int status);
++	void (*errhandler)(void *cbarg, int err);
++	void (*ctl_complete)(void *cbarg, int type, int status);
++	void (*state_change)(void *cbarg, int state);
++	bool (*isr)(void *cbarg, bool *wantdpc);
++	bool (*dpc)(void *cbarg, bool bounded);
++	void (*watchdog)(void *cbarg);
++	void *(*pktget)(void *cbarg, uint len, bool send);
++	void (*pktfree)(void *cbarg, void *p, bool send);
++	struct dbus_irb* (*getirb)(void *cbarg, bool send);
++	void (*rxerr_indicate)(void *cbarg, bool on);
++} dbus_intf_callbacks_t;
++
++/*
++ * Porting: To support new bus, port these functions below
++ */
++
++/*
++ * Bus specific Interface
++ * Implemented by dbus_usb.c/dbus_sdio.c
++ */
++extern int dbus_bus_register(int vid, int pid, probe_cb_t prcb, disconnect_cb_t discb, void *prarg,
++	dbus_intf_t **intf, void *param1, void *param2);
++extern int dbus_bus_deregister(void);
++extern void dbus_bus_fw_get(void *bus, uint8 **fw, int *fwlen, int *decomp);
++
++/*
++ * Bus-specific and OS-specific Interface
++ * Implemented by dbus_usb_[linux/ndis].c/dbus_sdio_[linux/ndis].c
++ */
++extern int dbus_bus_osl_register(int vid, int pid, probe_cb_t prcb, disconnect_cb_t discb,
++	void *prarg, dbus_intf_t **intf, void *param1, void *param2);
++extern int dbus_bus_osl_deregister(void);
++
++/*
++ * Bus-specific, OS-specific, HW-specific Interface
++ * Mainly for SDIO Host HW controller
++ */
++extern int dbus_bus_osl_hw_register(int vid, int pid, probe_cb_t prcb, disconnect_cb_t discb,
++	void *prarg, dbus_intf_t **intf);
++extern int dbus_bus_osl_hw_deregister(void);
++
++extern uint usbdev_bulkin_eps(void);
++#if defined(BCM_REQUEST_FW)
++extern void *dbus_get_fw_nvfile(int devid, int chiprev, uint8 **fw, int *fwlen, int type,
++  uint16 boardtype, uint16 boardrev);
++extern void dbus_release_fw_nvfile(void *firmware);
++#endif  /* #if defined(BCM_REQUEST_FW) */
++
++
++#if defined(EHCI_FASTPATH_TX) || defined(EHCI_FASTPATH_RX)
++
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
++	/* Backward compatibility */
++	typedef unsigned int gfp_t;
++
++	#define dma_pool pci_pool
++	#define dma_pool_create(name, dev, size, align, alloc) \
++		pci_pool_create(name, dev, size, align, alloc, GFP_DMA | GFP_ATOMIC)
++	#define dma_pool_destroy(pool) pci_pool_destroy(pool)
++	#define dma_pool_alloc(pool, flags, handle) pci_pool_alloc(pool, flags, handle)
++	#define dma_pool_free(pool, vaddr, addr) pci_pool_free(pool, vaddr, addr)
++
++	#define dma_map_single(dev, addr, size, dir)	pci_map_single(dev, addr, size, dir)
++	#define dma_unmap_single(dev, hnd, size, dir)	pci_unmap_single(dev, hnd, size, dir)
++	#define DMA_FROM_DEVICE PCI_DMA_FROMDEVICE
++	#define DMA_TO_DEVICE PCI_DMA_TODEVICE
++#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)) */
++
++/* Availability of these functions varies (when present, they have two arguments) */
++#ifndef hc32_to_cpu
++	#define hc32_to_cpu(x)	le32_to_cpu(x)
++	#define cpu_to_hc32(x)	cpu_to_le32(x)
++	typedef unsigned int __hc32;
++#else
++	#error Two-argument functions needed
++#endif
++
++/* Private USB opcode base */
++#define EHCI_FASTPATH		0x31
++#define	EHCI_SET_EP_BYPASS	EHCI_FASTPATH
++#define	EHCI_SET_BYPASS_CB	(EHCI_FASTPATH + 1)
++#define	EHCI_SET_BYPASS_DEV	(EHCI_FASTPATH + 2)
++#define	EHCI_DUMP_STATE		(EHCI_FASTPATH + 3)
++#define	EHCI_SET_BYPASS_POOL	(EHCI_FASTPATH + 4)
++#define	EHCI_CLR_EP_BYPASS	(EHCI_FASTPATH + 5)
++
++/*
++ * EHCI QTD structure (hardware and extension)
++ * NOTE that is does not need to (and does not) match its kernel counterpart
++ */
++#define EHCI_QTD_NBUFFERS       5
++#define EHCI_QTD_ALIGN  	32
++#define EHCI_BULK_PACKET_SIZE	512
++#define EHCI_QTD_XACTERR_MAX	32
++
++struct ehci_qtd {
++	/* Hardware map */
++	volatile uint32_t	qtd_next;
++	volatile uint32_t	qtd_altnext;
++	volatile uint32_t	qtd_status;
++#define	EHCI_QTD_GET_BYTES(x)	(((x)>>16) & 0x7fff)
++#define	EHCI_QTD_IOC            0x00008000
++#define	EHCI_QTD_GET_CERR(x)	(((x)>>10) & 0x3)
++#define EHCI_QTD_SET_CERR(x)    ((x) << 10)
++#define	EHCI_QTD_GET_PID(x)	(((x)>>8) & 0x3)
++#define EHCI_QTD_SET_PID(x)     ((x) <<  8)
++#define EHCI_QTD_ACTIVE         0x80
++#define EHCI_QTD_HALTED         0x40
++#define EHCI_QTD_BUFERR         0x20
++#define EHCI_QTD_BABBLE         0x10
++#define EHCI_QTD_XACTERR        0x08
++#define EHCI_QTD_MISSEDMICRO    0x04
++	volatile uint32_t 	qtd_buffer[EHCI_QTD_NBUFFERS];
++	volatile uint32_t 	qtd_buffer_hi[EHCI_QTD_NBUFFERS];
++
++	/* Implementation extension */
++	dma_addr_t		qtd_self;		/**< own hardware address */
++	struct ehci_qtd		*obj_next;		/**< software link to the next QTD */
++	void			*rpc;			/**< pointer to the rpc buffer */
++	size_t			length;			/**< length of the data in the buffer */
++	void			*buff;			/**< pointer to the reassembly buffer */
++	int			xacterrs;		/**< retry counter for qtd xact error */
++} __attribute__ ((aligned(EHCI_QTD_ALIGN)));
++
++#define	EHCI_NULL	__constant_cpu_to_le32(1) /* HW null pointer shall be odd */
++
++#define SHORT_READ_Q(token) (EHCI_QTD_GET_BYTES(token) != 0 && EHCI_QTD_GET_PID(token) == 1)
++
++/**
++ * Queue Head
++ * NOTE This structure is slightly different from the one in the kernel; but needs to stay
++ * compatible.
++ */
++struct ehci_qh {
++	/* Hardware map */
++	volatile uint32_t 	qh_link;
++	volatile uint32_t 	qh_endp;
++	volatile uint32_t 	qh_endphub;
++	volatile uint32_t 	qh_curqtd;
++
++	/* QTD overlay */
++	volatile uint32_t	ow_next;
++	volatile uint32_t	ow_altnext;
++	volatile uint32_t	ow_status;
++	volatile uint32_t	ow_buffer [EHCI_QTD_NBUFFERS];
++	volatile uint32_t	ow_buffer_hi [EHCI_QTD_NBUFFERS];
++
++	/* Extension (should match the kernel layout) */
++	dma_addr_t		unused0;
++	void 			*unused1;
++	struct list_head	unused2;
++	struct ehci_qtd		*dummy;
++	struct ehci_qh		*unused3;
++
++	struct ehci_hcd		*unused4;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++	struct kref		unused5;
++	unsigned		unused6;
++
++	uint8_t			unused7;
++
++	/* periodic schedule info */
++	uint8_t			unused8;
++	uint8_t			unused9;
++	uint8_t			unused10;
++	uint16_t		unused11;
++	uint16_t		unused12;
++	uint16_t		unused13;
++	struct usb_device	*unused14;
++#else
++	unsigned		unused5;
++
++	u8			unused6;
++
++	/* periodic schedule info */
++	u8			unused7;
++	u8			unused8;
++	u8			unused9;
++	unsigned short		unused10;
++	unsigned short		unused11;
++#define NO_FRAME ((unsigned short)~0)
++#ifdef EHCI_QUIRK_FIX
++	struct usb_device	*unused12;
++#endif /* EHCI_QUIRK_FIX */
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)) */
++	struct ehci_qtd		*first_qtd;
++		/* Link to the first QTD; this is an optimized equivalent of the qtd_list field */
++		/* NOTE that ehci_qh in ehci.h shall reserve this word */
++} __attribute__ ((aligned(EHCI_QTD_ALIGN)));
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
++/** The corresponding structure in the kernel is used to get the QH */
++struct hcd_dev {	/* usb_device.hcpriv points to this */
++	struct list_head	unused0;
++	struct list_head	unused1;
++
++	/* array of QH pointers */
++	void			*ep[32];
++};
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)) */
++
++int optimize_qtd_fill_with_rpc(const dbus_pub_t *pub,  int epn, struct ehci_qtd *qtd, void *rpc,
++	int token, int len);
++int optimize_qtd_fill_with_data(const dbus_pub_t *pub, int epn, struct ehci_qtd *qtd, void *data,
++	int token, int len);
++int optimize_submit_async(struct ehci_qtd *qtd, int epn);
++void inline optimize_ehci_qtd_init(struct ehci_qtd *qtd, dma_addr_t dma);
++struct ehci_qtd *optimize_ehci_qtd_alloc(gfp_t flags);
++void optimize_ehci_qtd_free(struct ehci_qtd *qtd);
++void optimize_submit_rx_request(const dbus_pub_t *pub, int epn, struct ehci_qtd *qtd_in, void *buf);
++#endif /* EHCI_FASTPATH_TX || EHCI_FASTPATH_RX */
++
++void  dbus_flowctrl_tx(void *dbi, bool on);
++#endif /* __DBUS_H__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/dhd_daemon.h b/module_drivers/drivers/net/wireless/bcmdhd/include/dhd_daemon.h
+new file mode 100644
+index 000000000..3a5141ab2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/dhd_daemon.h
+@@ -0,0 +1,62 @@
++/*
++ * Header file for DHD daemon to handle timeouts
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_daemon.h 671464 2016-11-22 06:15:32Z $
++ */
++
++#ifndef __BCM_DHDD_H__
++#define __BCM_DHDD_H__
++
++/**
++ * To maintain compatabily when dhd driver and dhd daemon is taken from different branches,
++ * make sure to keep this file same across dhd driver branch and dhd apps branch.
++ * TODO: Make this file as shared between apps and dhd.ko
++ */
++
++#define BCM_TO_MAGIC 0x600DB055
++#define NO_TRAP 0
++#define DO_TRAP	1
++
++#define BCM_NL_USER 31
++
++typedef enum notify_dhd_daemon_reason {
++	REASON_COMMAND_TO,
++	REASON_OQS_TO,
++	REASON_SCAN_TO,
++	REASON_JOIN_TO,
++	REASON_DAEMON_STARTED,
++	REASON_DEVICE_TX_STUCK_WARNING,
++	REASON_DEVICE_TX_STUCK,
++	REASON_UNKOWN
++} notify_dhd_daemon_reason_t;
++
++typedef struct bcm_to_info {
++	int magic;
++	int reason;
++	int trap;
++} bcm_to_info_t;
++
++#endif /* __BCM_DHDD_H__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/dhdioctl.h b/module_drivers/drivers/net/wireless/bcmdhd/include/dhdioctl.h
+new file mode 100644
+index 000000000..dd32fdb55
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/dhdioctl.h
+@@ -0,0 +1,159 @@
++/*
++ * Definitions for ioctls to access DHD iovars.
++ * Based on wlioctl.h (for Broadcom 802.11abg driver).
++ * (Moves towards generic ioctls for BCM drivers/iovars.)
++ *
++ * Definitions subject to change without notice.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhdioctl.h 675190 2016-12-14 15:27:52Z $
++ */
++
++#ifndef _dhdioctl_h_
++#define	_dhdioctl_h_
++
++#include <typedefs.h>
++
++
++/* Linux network driver ioctl encoding */
++typedef struct dhd_ioctl {
++	uint32 cmd;	/* common ioctl definition */
++	void *buf;	/* pointer to user buffer */
++	uint32 len;	/* length of user buffer */
++	uint32 set;	/* get or set request boolean (optional) */
++	uint32 used;	/* bytes read or written (optional) */
++	uint32 needed;	/* bytes needed (optional) */
++	uint32 driver;	/* to identify target driver */
++} dhd_ioctl_t;
++
++/* Underlying BUS definition */
++enum {
++	BUS_TYPE_USB = 0, /* for USB dongles */
++	BUS_TYPE_SDIO, /* for SDIO dongles */
++	BUS_TYPE_PCIE /* for PCIE dongles */
++};
++
++
++/* per-driver magic numbers */
++#define DHD_IOCTL_MAGIC		0x00444944
++
++/* bump this number if you change the ioctl interface */
++#define DHD_IOCTL_VERSION	1
++
++/*
++ * Increase the DHD_IOCTL_MAXLEN to 16K for supporting download of NVRAM files of size
++ * > 8K. In the existing implementation when NVRAM is to be downloaded via the "vars"
++ * DHD IOVAR, the NVRAM is copied to the DHD Driver memory. Later on when "dwnldstate" is
++ * invoked with FALSE option, the NVRAM gets copied from the DHD driver to the Dongle
++ * memory. The simple way to support this feature without modifying the DHD application,
++ * driver logic is to increase the DHD_IOCTL_MAXLEN size. This macro defines the "size"
++ * of the buffer in which data is exchanged between the DHD App and DHD driver.
++ */
++#define	DHD_IOCTL_MAXLEN	(16384)	/* max length ioctl buffer required */
++#define	DHD_IOCTL_SMLEN		256		/* "small" length ioctl buffer required */
++
++/* common ioctl definitions */
++#define DHD_GET_MAGIC				0
++#define DHD_GET_VERSION				1
++#define DHD_GET_VAR				2
++#define DHD_SET_VAR				3
++
++/* message levels */
++#define DHD_ERROR_VAL	0x0001
++#define DHD_TRACE_VAL	0x0002
++#define DHD_INFO_VAL	0x0004
++#define DHD_DATA_VAL	0x0008
++#define DHD_CTL_VAL	0x0010
++#define DHD_TIMER_VAL	0x0020
++#define DHD_HDRS_VAL	0x0040
++#define DHD_BYTES_VAL	0x0080
++#define DHD_INTR_VAL	0x0100
++#define DHD_LOG_VAL	0x0200
++#define DHD_GLOM_VAL	0x0400
++#define DHD_EVENT_VAL	0x0800
++#define DHD_BTA_VAL	0x1000
++#define DHD_ISCAN_VAL	0x2000
++#define DHD_ARPOE_VAL	0x4000
++#define DHD_REORDER_VAL	0x8000
++#define DHD_NOCHECKDIED_VAL		0x20000 /* UTF WAR */
++#define DHD_PNO_VAL		0x80000
++#define DHD_RTT_VAL		0x100000
++#define DHD_MSGTRACE_VAL	0x200000
++#define DHD_FWLOG_VAL		0x400000
++#define DHD_DBGIF_VAL		0x800000
++#ifdef DHD_PCIE_NATIVE_RUNTIMEPM
++#define DHD_RPM_VAL		0x1000000
++#endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
++#define DHD_PKT_MON_VAL		0x2000000
++#define DHD_PKT_MON_DUMP_VAL	0x4000000
++#define DHD_ERROR_MEM_VAL	0x8000000
++#define DHD_ANDROID_VAL	0x10000
++#define DHD_IW_VAL	0x20000
++#define DHD_CFG_VAL	0x40000
++#define DHD_CONFIG_VAL	0x80000
++#define DUMP_EAPOL_VAL	0x0001
++#define DUMP_ARP_VAL	0x0002
++#define DUMP_DHCP_VAL	0x0004
++#define DUMP_ICMP_VAL	0x0008
++#define DUMP_DNS_VAL	0x0010
++#define DUMP_TRX_VAL	0x0080
++
++#ifdef SDTEST
++/* For pktgen iovar */
++typedef struct dhd_pktgen {
++	uint32 version;		/* To allow structure change tracking */
++	uint32 freq;		/* Max ticks between tx/rx attempts */
++	uint32 count;		/* Test packets to send/rcv each attempt */
++	uint32 print;		/* Print counts every <print> attempts */
++	uint32 total;		/* Total packets (or bursts) */
++	uint32 minlen;		/* Minimum length of packets to send */
++	uint32 maxlen;		/* Maximum length of packets to send */
++	uint32 numsent;		/* Count of test packets sent */
++	uint32 numrcvd;		/* Count of test packets received */
++	uint32 numfail;		/* Count of test send failures */
++	uint32 mode;		/* Test mode (type of test packets) */
++	uint32 stop;		/* Stop after this many tx failures */
++} dhd_pktgen_t;
++
++/* Version in case structure changes */
++#define DHD_PKTGEN_VERSION 2
++
++/* Type of test packets to use */
++#define DHD_PKTGEN_ECHO		1 /* Send echo requests */
++#define DHD_PKTGEN_SEND 	2 /* Send discard packets */
++#define DHD_PKTGEN_RXBURST	3 /* Request dongle send N packets */
++#define DHD_PKTGEN_RECV		4 /* Continuous rx from continuous tx dongle */
++#endif /* SDTEST */
++
++/* Enter idle immediately (no timeout) */
++#define DHD_IDLE_IMMEDIATE	(-1)
++
++/* Values for idleclock iovar: other values are the sd_divisor to use when idle */
++#define DHD_IDLE_ACTIVE	0	/* Do not request any SD clock change when idle */
++#define DHD_IDLE_STOP   (-1)	/* Request SD clock be stopped (and use SD1 mode) */
++
++
++
++#endif /* _dhdioctl_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/dnglevent.h b/module_drivers/drivers/net/wireless/bcmdhd/include/dnglevent.h
+new file mode 100644
+index 000000000..40a0047a6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/dnglevent.h
+@@ -0,0 +1,120 @@
++/*
++ * Broadcom Event  protocol definitions
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * Dependencies: bcmeth.h
++ *
++ * $Id: dnglevent.h $
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * -----------------------------------------------------------------------------
++ *
++ */
++
++/*
++ * Broadcom dngl Ethernet Events protocol defines
++ *
++ */
++
++#ifndef _DNGLEVENT_H_
++#define _DNGLEVENT_H_
++
++#ifndef _TYPEDEFS_H_
++#include <typedefs.h>
++#endif
++#include <bcmeth.h>
++#include <ethernet.h>
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++#define BCM_DNGL_EVENT_MSG_VERSION		1
++#define DNGL_E_RSRVD_1				0x0
++#define DNGL_E_RSRVD_2				0x1
++#define DNGL_E_SOCRAM_IND			0x2
++typedef BWL_PRE_PACKED_STRUCT struct
++{
++	uint16  version; /* Current version is 1 */
++	uint16  reserved; /* reserved for any future extension */
++	uint16  event_type; /* DNGL_E_SOCRAM_IND */
++	uint16  datalen; /* Length of the event payload */
++} BWL_POST_PACKED_STRUCT bcm_dngl_event_msg_t;
++
++typedef BWL_PRE_PACKED_STRUCT struct bcm_dngl_event {
++	struct ether_header eth;
++	bcmeth_hdr_t        bcm_hdr;
++	bcm_dngl_event_msg_t      dngl_event;
++	/* data portion follows */
++} BWL_POST_PACKED_STRUCT bcm_dngl_event_t;
++
++typedef BWL_PRE_PACKED_STRUCT struct bcm_dngl_socramind {
++	uint16			tag;	/* data tag */
++	uint16			length; /* data length */
++	uint8			value[1]; /* data value with variable length specified by length */
++} BWL_POST_PACKED_STRUCT bcm_dngl_socramind_t;
++
++/* SOCRAM_IND type tags */
++#define SOCRAM_IND_ASSERT_TAG		0x1
++#define SOCRAM_IND_TAG_HEALTH_CHECK	0x2
++/* Health check top level module tags */
++typedef BWL_PRE_PACKED_STRUCT struct bcm_dngl_healthcheck {
++	uint16			top_module_tag;	/* top level module tag */
++	uint16			top_module_len; /* Type of PCIE issue indication */
++	uint8			value[1]; /* data value with variable length specified by length */
++} BWL_POST_PACKED_STRUCT bcm_dngl_healthcheck_t;
++
++/* Health check top level module tags */
++#define HEALTH_CHECK_TOP_LEVEL_MODULE_PCIEDEV_RTE 1
++#define HEALTH_CHECK_PCIEDEV_VERSION_1	1
++#define HEALTH_CHECK_PCIEDEV_FLAG_IN_D3_SHIFT	0
++#define HEALTH_CHECK_PCIEDEV_FLAG_AER_SHIFT		1
++#define HEALTH_CHECK_PCIEDEV_FLAG_LINKDOWN_SHIFT		2
++#define HEALTH_CHECK_PCIEDEV_FLAG_MSI_INT_SHIFT			3
++#define HEALTH_CHECK_PCIEDEV_FLAG_NODS_SHIFT			4
++#define HEALTH_CHECK_PCIEDEV_FLAG_IN_D3	1 << HEALTH_CHECK_PCIEDEV_FLAG_IN_D3_SHIFT
++#define HEALTH_CHECK_PCIEDEV_FLAG_AER	1 << HEALTH_CHECK_PCIEDEV_FLAG_AER_SHIFT
++#define HEALTH_CHECK_PCIEDEV_FLAG_LINKDOWN	1 << HEALTH_CHECK_PCIEDEV_FLAG_LINKDOWN_SHIFT
++#define HEALTH_CHECK_PCIEDEV_FLAG_MSI_INT	1 << HEALTH_CHECK_PCIEDEV_FLAG_MSI_INT_SHIFT
++#define HEALTH_CHECK_PCIEDEV_FLAG_NODS	1 << HEALTH_CHECK_PCIEDEV_FLAG_NODS_SHIFT
++/* PCIE Module TAGs */
++#define HEALTH_CHECK_PCIEDEV_INDUCED_IND	0x1
++#define HEALTH_CHECK_PCIEDEV_H2D_DMA_IND	0x2
++#define HEALTH_CHECK_PCIEDEV_D2H_DMA_IND	0x3
++#define HEALTH_CHECK_PCIEDEV_IOCTL_STALL_IND	0x4
++#define HEALTH_CHECK_PCIEDEV_D3ACK_STALL_IND	0x5
++#define HEALTH_CHECK_PCIEDEV_NODS_IND	0x6
++#define HEALTH_CHECK_PCIEDEV_LINKSPEED_FALLBACK_IND	0x7
++
++#define HC_PCIEDEV_CONFIG_REGLIST_MAX	20
++typedef BWL_PRE_PACKED_STRUCT struct bcm_dngl_pcie_hc {
++	uint16			version; /* HEALTH_CHECK_PCIEDEV_VERSION_1 */
++	uint16			reserved;
++	uint16			pcie_err_ind_type; /* PCIE Module TAGs */
++	uint16			pcie_flag;
++	uint32			pcie_control_reg;
++	uint32			pcie_config_regs[HC_PCIEDEV_CONFIG_REGLIST_MAX];
++} BWL_POST_PACKED_STRUCT bcm_dngl_pcie_hc_t;
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++#endif /* _DNGLEVENT_H_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/eapol.h b/module_drivers/drivers/net/wireless/bcmdhd/include/eapol.h
+new file mode 100644
+index 000000000..ef917abc0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/eapol.h
+@@ -0,0 +1,218 @@
++/*
++ * 802.1x EAPOL definitions
++ *
++ * See
++ * IEEE Std 802.1X-2001
++ * IEEE 802.1X RADIUS Usage Guidelines
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: eapol.h 700076 2017-05-17 14:42:22Z $
++ */
++
++#ifndef _eapol_h_
++#define _eapol_h_
++
++#ifndef _TYPEDEFS_H_
++#include <typedefs.h>
++#endif
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++
++#if !defined(BCMCRYPTO_COMPONENT)
++#include <bcmcrypto/aeskeywrap.h>
++#endif /* !BCMCRYPTO_COMPONENT */
++
++/* EAPOL for 802.3/Ethernet */
++typedef BWL_PRE_PACKED_STRUCT struct {
++	struct ether_header eth;	/* 802.3/Ethernet header */
++	unsigned char version;		/* EAPOL protocol version */
++	unsigned char type;		/* EAPOL type */
++	unsigned short length;		/* Length of body */
++	unsigned char body[1];		/* Body (optional) */
++} BWL_POST_PACKED_STRUCT eapol_header_t;
++
++#define EAPOL_HEADER_LEN 18
++
++typedef struct {
++	unsigned char version;		/* EAPOL protocol version */
++	unsigned char type;		/* EAPOL type */
++	unsigned short length;		/* Length of body */
++} eapol_hdr_t;
++
++#define EAPOL_HDR_LEN 4
++
++/* EAPOL version */
++#define WPA2_EAPOL_VERSION	2
++#define WPA_EAPOL_VERSION	1
++#define LEAP_EAPOL_VERSION	1
++#define SES_EAPOL_VERSION	1
++
++/* EAPOL types */
++#define EAP_PACKET		0
++#define EAPOL_START		1
++#define EAPOL_LOGOFF		2
++#define EAPOL_KEY		3
++#define EAPOL_ASF		4
++
++/* EAPOL-Key types */
++#define EAPOL_RC4_KEY		1
++#define EAPOL_WPA2_KEY		2	/* 802.11i/WPA2 */
++#define EAPOL_WPA_KEY		254	/* WPA */
++
++/* RC4 EAPOL-Key header field sizes */
++#define EAPOL_KEY_REPLAY_LEN	8
++#define EAPOL_KEY_IV_LEN	16
++#define EAPOL_KEY_SIG_LEN	16
++
++/* RC4 EAPOL-Key */
++typedef BWL_PRE_PACKED_STRUCT struct {
++	unsigned char type;			/* Key Descriptor Type */
++	unsigned short length;			/* Key Length (unaligned) */
++	unsigned char replay[EAPOL_KEY_REPLAY_LEN];	/* Replay Counter */
++	unsigned char iv[EAPOL_KEY_IV_LEN];		/* Key IV */
++	unsigned char index;				/* Key Flags & Index */
++	unsigned char signature[EAPOL_KEY_SIG_LEN];	/* Key Signature */
++	unsigned char key[1];				/* Key (optional) */
++} BWL_POST_PACKED_STRUCT eapol_key_header_t;
++
++#define EAPOL_KEY_HEADER_LEN 	44
++
++/* RC4 EAPOL-Key flags */
++#define EAPOL_KEY_FLAGS_MASK	0x80
++#define EAPOL_KEY_BROADCAST	0
++#define EAPOL_KEY_UNICAST	0x80
++
++/* RC4 EAPOL-Key index */
++#define EAPOL_KEY_INDEX_MASK	0x7f
++
++/* WPA/802.11i/WPA2 EAPOL-Key header field sizes */
++#define EAPOL_AKW_BLOCK_LEN 8
++#define EAPOL_WPA_KEY_REPLAY_LEN	8
++#define EAPOL_WPA_KEY_NONCE_LEN		32
++#define EAPOL_WPA_KEY_IV_LEN		16
++#define EAPOL_WPA_KEY_RSC_LEN		8
++#define EAPOL_WPA_KEY_ID_LEN		8
++#define EAPOL_WPA_KEY_MIC_LEN		16
++#define EAPOL_WPA_KEY_DATA_LEN		(EAPOL_WPA_MAX_KEY_SIZE + EAPOL_AKW_BLOCK_LEN)
++#define EAPOL_WPA_MAX_KEY_SIZE		32
++
++/* WPA EAPOL-Key */
++typedef BWL_PRE_PACKED_STRUCT struct {
++	unsigned char type;		/* Key Descriptor Type */
++	unsigned short key_info;	/* Key Information (unaligned) */
++	unsigned short key_len;		/* Key Length (unaligned) */
++	unsigned char replay[EAPOL_WPA_KEY_REPLAY_LEN];	/* Replay Counter */
++	unsigned char nonce[EAPOL_WPA_KEY_NONCE_LEN];	/* Nonce */
++	unsigned char iv[EAPOL_WPA_KEY_IV_LEN];		/* Key IV */
++	unsigned char rsc[EAPOL_WPA_KEY_RSC_LEN];	/* Key RSC */
++	unsigned char id[EAPOL_WPA_KEY_ID_LEN];		/* WPA:Key ID, 802.11i/WPA2: Reserved */
++	unsigned char mic[EAPOL_WPA_KEY_MIC_LEN];	/* Key MIC */
++	unsigned short data_len;			/* Key Data Length */
++	unsigned char data[EAPOL_WPA_KEY_DATA_LEN];	/* Key data */
++} BWL_POST_PACKED_STRUCT eapol_wpa_key_header_t;
++
++#define EAPOL_WPA_KEY_LEN 		95
++
++/* WPA/802.11i/WPA2 KEY KEY_INFO bits */
++#define WPA_KEY_DESC_OSEN	0x0
++#define WPA_KEY_DESC_V1		0x01
++#define WPA_KEY_DESC_V2		0x02
++#define WPA_KEY_DESC_V3		0x03
++#define WPA_KEY_PAIRWISE	0x08
++#define WPA_KEY_INSTALL		0x40
++#define WPA_KEY_ACK		0x80
++#define WPA_KEY_MIC		0x100
++#define WPA_KEY_SECURE		0x200
++#define WPA_KEY_ERROR		0x400
++#define WPA_KEY_REQ		0x800
++
++#define WPA_KEY_DESC_V2_OR_V3 WPA_KEY_DESC_V2
++
++/* WPA-only KEY KEY_INFO bits */
++#define WPA_KEY_INDEX_0		0x00
++#define WPA_KEY_INDEX_1		0x10
++#define WPA_KEY_INDEX_2		0x20
++#define WPA_KEY_INDEX_3		0x30
++#define WPA_KEY_INDEX_MASK	0x30
++#define WPA_KEY_INDEX_SHIFT	0x04
++
++/* 802.11i/WPA2-only KEY KEY_INFO bits */
++#define WPA_KEY_ENCRYPTED_DATA	0x1000
++
++/* Key Data encapsulation */
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint8 type;
++	uint8 length;
++	uint8 oui[3];
++	uint8 subtype;
++	uint8 data[1];
++} BWL_POST_PACKED_STRUCT eapol_wpa2_encap_data_t;
++
++#define EAPOL_WPA2_ENCAP_DATA_HDR_LEN 	6
++
++#define WPA2_KEY_DATA_SUBTYPE_GTK	1
++#define WPA2_KEY_DATA_SUBTYPE_STAKEY	2
++#define WPA2_KEY_DATA_SUBTYPE_MAC	3
++#define WPA2_KEY_DATA_SUBTYPE_PMKID	4
++#define WPA2_KEY_DATA_SUBTYPE_IGTK	9
++
++/* GTK encapsulation */
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint8	flags;
++	uint8	reserved;
++	uint8	gtk[EAPOL_WPA_MAX_KEY_SIZE];
++} BWL_POST_PACKED_STRUCT eapol_wpa2_key_gtk_encap_t;
++
++#define EAPOL_WPA2_KEY_GTK_ENCAP_HDR_LEN 	2
++
++#define WPA2_GTK_INDEX_MASK	0x03
++#define WPA2_GTK_INDEX_SHIFT	0x00
++
++#define WPA2_GTK_TRANSMIT	0x04
++
++/* IGTK encapsulation */
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint16	key_id;
++	uint8	ipn[6];
++	uint8	key[EAPOL_WPA_MAX_KEY_SIZE];
++} BWL_POST_PACKED_STRUCT eapol_wpa2_key_igtk_encap_t;
++
++#define EAPOL_WPA2_KEY_IGTK_ENCAP_HDR_LEN 	8
++
++/* STAKey encapsulation */
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint8	reserved[2];
++	uint8	mac[ETHER_ADDR_LEN];
++	uint8	stakey[EAPOL_WPA_MAX_KEY_SIZE];
++} BWL_POST_PACKED_STRUCT eapol_wpa2_key_stakey_encap_t;
++
++#define WPA2_KEY_DATA_PAD	0xdd
++
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++#endif /* _eapol_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/epivers.h b/module_drivers/drivers/net/wireless/bcmdhd/include/epivers.h
+new file mode 100644
+index 000000000..c90d5adb4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/epivers.h
+@@ -0,0 +1,51 @@
++/*
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: epivers.h.in 596126 2015-10-29 19:53:48Z $
++ *
++*/
++
++#ifndef _epivers_h_
++#define _epivers_h_
++
++#define	EPI_MAJOR_VERSION	1
++
++#define	EPI_MINOR_VERSION	579
++
++#define	EPI_RC_NUMBER		77
++
++#define	EPI_INCREMENTAL_NUMBER	41
++
++#define	EPI_BUILD_NUMBER	0
++
++#define	EPI_VERSION		1, 579, 77, 41
++
++#define	EPI_VERSION_NUM		0x012434d29
++
++#define EPI_VERSION_DEV		1.579.77.41
++
++/* Driver Version String, ASCII, 32 chars max */
++#define	EPI_VERSION_STR		"1.579.77.41.26 (r-20200429-2)"
++
++#endif /* _epivers_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/ethernet.h b/module_drivers/drivers/net/wireless/bcmdhd/include/ethernet.h
+new file mode 100644
+index 000000000..2e338676a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/ethernet.h
+@@ -0,0 +1,227 @@
++/*
++ * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: ethernet.h 700076 2017-05-17 14:42:22Z $
++ */
++
++#ifndef _NET_ETHERNET_H_	/* use native BSD ethernet.h when available */
++#define _NET_ETHERNET_H_
++
++#ifndef _TYPEDEFS_H_
++#include "typedefs.h"
++#endif
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++
++
++/*
++ * The number of bytes in an ethernet (MAC) address.
++ */
++#define	ETHER_ADDR_LEN		6
++
++/*
++ * The number of bytes in the type field.
++ */
++#define	ETHER_TYPE_LEN		2
++
++/*
++ * The number of bytes in the trailing CRC field.
++ */
++#define	ETHER_CRC_LEN		4
++
++/*
++ * The length of the combined header.
++ */
++#define	ETHER_HDR_LEN		(ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
++
++/*
++ * The minimum packet length.
++ */
++#define	ETHER_MIN_LEN		64
++
++/*
++ * The minimum packet user data length.
++ */
++#define	ETHER_MIN_DATA		46
++
++/*
++ * The maximum packet length.
++ */
++#define	ETHER_MAX_LEN		1518
++
++/*
++ * The maximum packet user data length.
++ */
++#define	ETHER_MAX_DATA		1500
++
++/* ether types */
++#define ETHER_TYPE_MIN		0x0600		/* Anything less than MIN is a length */
++#define	ETHER_TYPE_IP		0x0800		/* IP */
++#define ETHER_TYPE_ARP		0x0806		/* ARP */
++#define ETHER_TYPE_8021Q	0x8100		/* 802.1Q */
++#define	ETHER_TYPE_IPV6		0x86dd		/* IPv6 */
++#define	ETHER_TYPE_BRCM		0x886c		/* Broadcom Corp. */
++#define	ETHER_TYPE_802_1X	0x888e		/* 802.1x */
++#define	ETHER_TYPE_802_1X_PREAUTH 0x88c7	/* 802.1x preauthentication */
++#define ETHER_TYPE_WAI		0x88b4		/* WAI */
++#define ETHER_TYPE_89_0D	0x890d		/* 89-0d frame for TDLS */
++#define ETHER_TYPE_RRB		ETHER_TYPE_89_0D  /* RRB 802.11r 2008 */
++
++#define ETHER_TYPE_PPP_SES	0x8864		/* PPPoE Session */
++
++#define ETHER_TYPE_IAPP_L2_UPDATE	0x6	/* IAPP L2 update frame */
++
++/* Broadcom subtype follows ethertype;  First 2 bytes are reserved; Next 2 are subtype; */
++#define	ETHER_BRCM_SUBTYPE_LEN	4	/* Broadcom 4 byte subtype */
++
++/* ether header */
++#define ETHER_DEST_OFFSET	(0 * ETHER_ADDR_LEN)	/* dest address offset */
++#define ETHER_SRC_OFFSET	(1 * ETHER_ADDR_LEN)	/* src address offset */
++#define ETHER_TYPE_OFFSET	(2 * ETHER_ADDR_LEN)	/* ether type offset */
++
++/*
++ * A macro to validate a length with
++ */
++#define	ETHER_IS_VALID_LEN(foo)	\
++	((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
++
++#define ETHER_FILL_MCAST_ADDR_FROM_IP(ea, mgrp_ip) {		\
++		((uint8 *)ea)[0] = 0x01;			\
++		((uint8 *)ea)[1] = 0x00;			\
++		((uint8 *)ea)[2] = 0x5e;			\
++		((uint8 *)ea)[3] = ((mgrp_ip) >> 16) & 0x7f;	\
++		((uint8 *)ea)[4] = ((mgrp_ip) >>  8) & 0xff;	\
++		((uint8 *)ea)[5] = ((mgrp_ip) >>  0) & 0xff;	\
++}
++
++#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
++/*
++ * Structure of a 10Mb/s Ethernet header.
++ */
++BWL_PRE_PACKED_STRUCT struct ether_header {
++	uint8	ether_dhost[ETHER_ADDR_LEN];
++	uint8	ether_shost[ETHER_ADDR_LEN];
++	uint16	ether_type;
++} BWL_POST_PACKED_STRUCT;
++
++/*
++ * Structure of a 48-bit Ethernet address.
++ */
++BWL_PRE_PACKED_STRUCT struct	ether_addr {
++	uint8 octet[ETHER_ADDR_LEN];
++} BWL_POST_PACKED_STRUCT;
++#endif	/* !__INCif_etherh Quick and ugly hack for VxWorks */
++
++/*
++ * Takes a pointer, set, test, clear, toggle locally admininistered
++ * address bit in the 48-bit Ethernet address.
++ */
++#define ETHER_SET_LOCALADDR(ea)	(((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] | 2))
++#define ETHER_IS_LOCALADDR(ea) 	(((uint8 *)(ea))[0] & 2)
++#define ETHER_CLR_LOCALADDR(ea)	(((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] & 0xfd))
++#define ETHER_TOGGLE_LOCALADDR(ea)	(((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] ^ 2))
++
++/* Takes a pointer, marks unicast address bit in the MAC address */
++#define ETHER_SET_UNICAST(ea)	(((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] & ~1))
++
++/*
++ * Takes a pointer, returns true if a 48-bit multicast address
++ * (including broadcast, since it is all ones)
++ */
++#define ETHER_ISMULTI(ea) (((const uint8 *)(ea))[0] & 1)
++
++
++/* compare two ethernet addresses - assumes the pointers can be referenced as shorts */
++#define eacmp(a, b)	((((const uint16 *)(a))[0] ^ ((const uint16 *)(b))[0]) | \
++	                 (((const uint16 *)(a))[1] ^ ((const uint16 *)(b))[1]) | \
++	                 (((const uint16 *)(a))[2] ^ ((const uint16 *)(b))[2]))
++
++#define	ether_cmp(a, b)	eacmp(a, b)
++
++/* copy an ethernet address - assumes the pointers can be referenced as shorts */
++#define eacopy(s, d) \
++do { \
++	((uint16 *)(d))[0] = ((const uint16 *)(s))[0]; \
++	((uint16 *)(d))[1] = ((const uint16 *)(s))[1]; \
++	((uint16 *)(d))[2] = ((const uint16 *)(s))[2]; \
++} while (0)
++
++#define	ether_copy(s, d) eacopy(s, d)
++
++/* Copy an ethernet address in reverse order */
++#define	ether_rcopy(s, d) \
++do { \
++	((uint16 *)(d))[2] = ((uint16 *)(s))[2]; \
++	((uint16 *)(d))[1] = ((uint16 *)(s))[1]; \
++	((uint16 *)(d))[0] = ((uint16 *)(s))[0]; \
++} while (0)
++
++/* Copy 14B ethernet header: 32bit aligned source and destination. */
++#define ehcopy32(s, d) \
++do { \
++	((uint32 *)(d))[0] = ((const uint32 *)(s))[0]; \
++	((uint32 *)(d))[1] = ((const uint32 *)(s))[1]; \
++	((uint32 *)(d))[2] = ((const uint32 *)(s))[2]; \
++	((uint16 *)(d))[6] = ((const uint16 *)(s))[6]; \
++} while (0)
++
++
++static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
++static const struct ether_addr ether_null = {{0, 0, 0, 0, 0, 0}};
++static const struct ether_addr ether_ipv6_mcast = {{0x33, 0x33, 0x00, 0x00, 0x00, 0x01}};
++
++#define ETHER_ISBCAST(ea)	((((const uint8 *)(ea))[0] &		\
++	                          ((const uint8 *)(ea))[1] &		\
++				  ((const uint8 *)(ea))[2] &		\
++				  ((const uint8 *)(ea))[3] &		\
++				  ((const uint8 *)(ea))[4] &		\
++				  ((const uint8 *)(ea))[5]) == 0xff)
++#define ETHER_ISNULLADDR(ea)	((((const uint8 *)(ea))[0] |		\
++				  ((const uint8 *)(ea))[1] |		\
++				  ((const uint8 *)(ea))[2] |		\
++				  ((const uint8 *)(ea))[3] |		\
++				  ((const uint8 *)(ea))[4] |		\
++				  ((const uint8 *)(ea))[5]) == 0)
++
++#define ETHER_ISNULLDEST(da)	((((const uint16 *)(da))[0] |           \
++				  ((const uint16 *)(da))[1] |           \
++				  ((const uint16 *)(da))[2]) == 0)
++#define ETHER_ISNULLSRC(sa)	ETHER_ISNULLDEST(sa)
++
++#define ETHER_MOVE_HDR(d, s) \
++do { \
++	struct ether_header t; \
++	t = *(struct ether_header *)(s); \
++	*(struct ether_header *)(d) = t; \
++} while (0)
++
++#define  ETHER_ISUCAST(ea) ((((uint8 *)(ea))[0] & 0x01) == 0)
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++#endif /* _NET_ETHERNET_H_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/event_log.h b/module_drivers/drivers/net/wireless/bcmdhd/include/event_log.h
+new file mode 100644
+index 000000000..0c2120e19
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/event_log.h
+@@ -0,0 +1,388 @@
++/*
++ * EVENT_LOG system definitions
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: event_log.h 711908 2017-07-20 10:37:34Z $
++ */
++
++#ifndef _EVENT_LOG_H_
++#define _EVENT_LOG_H_
++
++#include <typedefs.h>
++#include <event_log_set.h>
++#include <event_log_tag.h>
++#include <event_log_payload.h>
++#include <osl_decl.h>
++
++/* logstrs header */
++#define LOGSTRS_MAGIC   0x4C4F4753
++#define LOGSTRS_VERSION 0x1
++
++/* We make sure that the block size will fit in a single packet
++ *  (allowing for a bit of overhead on each packet
++ */
++#define EVENT_LOG_MAX_BLOCK_SIZE	1400
++#define EVENT_LOG_WL_BLOCK_SIZE		0x200
++#define EVENT_LOG_PSM_BLOCK_SIZE	0x200
++#define EVENT_LOG_BUS_BLOCK_SIZE	0x200
++#define EVENT_LOG_ERROR_BLOCK_SIZE	0x200
++/* Maximum event log record payload size = 1024 bytes or 256 words. */
++#define EVENT_LOG_MAX_RECORD_PAYLOAD_SIZE	256
++
++/*
++ * There are multiple levels of objects define here:
++ *   event_log_set - a set of buffers
++ *   event log groups - every event log call is part of just one.  All
++ *                      event log calls in a group are handled the
++ *                      same way.  Each event log group is associated
++ *                      with an event log set or is off.
++ */
++
++#ifndef __ASSEMBLER__
++
++/* On the external system where the dumper is we need to make sure
++ * that these types are the same size as they are on the ARM the
++ * produced them
++ */
++#ifdef EVENT_LOG_DUMPER
++#define _EL_BLOCK_PTR uint32
++#define _EL_TYPE_PTR uint32
++#define _EL_SET_PTR uint32
++#define _EL_TOP_PTR uint32
++#else
++#define _EL_BLOCK_PTR struct event_log_block *
++#define _EL_TYPE_PTR uint32 *
++#define _EL_SET_PTR struct event_log_set **
++#define _EL_TOP_PTR struct event_log_top *
++#endif /* EVENT_LOG_DUMPER */
++
++/* Event log sets (a logical circurlar buffer) consist of one or more
++ * event_log_blocks.  The blocks themselves form a logical circular
++ * list.  The log entries are placed in each event_log_block until it
++ * is full.  Logging continues with the next event_log_block in the
++ * event_set until the last event_log_block is reached and then
++ * logging starts over with the first event_log_block in the
++ * event_set.
++ */
++typedef struct event_log_block {
++	_EL_BLOCK_PTR next_block;
++	_EL_BLOCK_PTR prev_block;
++	_EL_TYPE_PTR end_ptr;
++
++	/* Start of packet sent for log tracing */
++	uint16 pktlen;			/* Size of rest of block */
++	uint16 count;			/* Logtrace counter */
++	uint32 extra_hdr_info;		/* LSB: 6 bits set id. MSB 24 bits reserved */
++	uint32 event_logs;
++} event_log_block_t;
++#define EVENT_LOG_BLOCK_HDRLEN		8 /* pktlen 2 + count 2 + extra_hdr_info 4 */
++#define NAN_EVENT_LOG_MIN_LENGTH	2 /* Minimum length of Nan event */
++
++typedef enum {
++	SET_DESTINATION_INVALID = -1,
++	SET_DESTINATION_HOST = 0,
++	SET_DESTINATION_NONE = 1,
++	SET_DESTINATION_MAX
++} event_log_set_destination_t;
++
++/* There can be multiple event_sets with each logging a set of
++ * associated events (i.e, "fast" and "slow" events).
++ */
++typedef struct event_log_set {
++	_EL_BLOCK_PTR first_block; 	/* Pointer to first event_log block */
++	_EL_BLOCK_PTR last_block; 	/* Pointer to last event_log block */
++	_EL_BLOCK_PTR logtrace_block;	/* next block traced */
++	_EL_BLOCK_PTR cur_block;   	/* Pointer to current event_log block */
++	_EL_TYPE_PTR cur_ptr;      	/* Current event_log pointer */
++	uint32 blockcount;		/* Number of blocks */
++	uint16 logtrace_count;		/* Last count for logtrace */
++	uint16 blockfill_count;		/* Fill count for logtrace */
++	uint32 timestamp;		/* Last timestamp event */
++	uint32 cyclecount;		/* Cycles at last timestamp event */
++	event_log_set_destination_t destination;
++	uint16 size;			/* same size for all buffers in one  set */
++} event_log_set_t;
++
++/* Top data structure for access to everything else */
++typedef struct event_log_top {
++	uint32 magic;
++#define EVENT_LOG_TOP_MAGIC 0x474C8669 /* 'EVLG' */
++	uint32 version;
++#define EVENT_LOG_VERSION 1
++	uint32 num_sets;
++	uint32 logstrs_size;		/* Size of lognums + logstrs area */
++	uint32 timestamp;		/* Last timestamp event */
++	uint32 cyclecount;		/* Cycles at last timestamp event */
++	_EL_SET_PTR sets; 		/* Ptr to array of <num_sets> set ptrs */
++} event_log_top_t;
++
++/* Data structure of Keeping the Header from logstrs.bin */
++typedef struct {
++	uint32 logstrs_size;    /* Size of the file */
++	uint32 rom_lognums_offset; /* Offset to the ROM lognum */
++	uint32 ram_lognums_offset; /* Offset to the RAM lognum */
++	uint32 rom_logstrs_offset; /* Offset to the ROM logstr */
++	uint32 ram_logstrs_offset; /* Offset to the RAM logstr */
++	/* Keep version and magic last since "header" is appended to the end of logstrs file. */
++	uint32 version;            /* Header version */
++	uint32 log_magic;       /* MAGIC number for verification 'LOGS' */
++} logstr_header_t;
++
++/*
++ * Use the following macros for generating log events.
++ *
++ * The FAST versions check the enable of the tag before evaluating the arguments and calling the
++ * event_log function.  This adds 5 instructions.  The COMPACT versions evaluate the arguments
++ * and call the event_log function unconditionally.  The event_log function will then skip logging
++ * if this tag is disabled.
++ *
++ * To support easy usage of existing debugging (e.g. msglevel) via macro re-definition there are
++ * two variants of these macros to help.
++ *
++ * First there are the CAST versions.  The event_log function normally logs uint32 values or else
++ * they have to be cast to uint32.  The CAST versions blindly cast for you so you don't have to edit
++ * any existing code.
++ *
++ * Second there are the PAREN_ARGS versions.  These expect the logging format string and arguments
++ * to be enclosed in parentheses.  This allows us to make the following mapping of an existing
++ * msglevel macro:
++ *  #define WL_ERROR(args)   EVENT_LOG_CAST_PAREN_ARGS(EVENT_LOG_TAG_WL_ERROR, args)
++ *
++ * The versions of the macros without FAST or COMPACT in their name are just synonyms for the
++ * COMPACT versions.
++ *
++ * You should use the COMPACT macro (or its synonym) in cases where there is some preceding logic
++ * that prevents the execution of the macro, e.g. WL_ERROR by definition rarely gets executed.
++ * Use the FAST macro in performance sensitive paths. The key concept here is that you should be
++ * assuming that your macro usage is compiled into ROM and can't be changed ... so choose wisely.
++ *
++ */
++
++#if !defined(EVENT_LOG_DUMPER) && !defined(DHD_EFI)
++
++#ifndef EVENT_LOG_COMPILE
++
++/* Null define if no tracing */
++#define EVENT_LOG(format, ...)
++#define EVENT_LOG_FAST(tag, fmt, ...)
++#define EVENT_LOG_COMPACT(tag, fmt, ...)
++
++#define EVENT_LOG_CAST(tag, fmt, ...)
++#define EVENT_LOG_FAST_CAST(tag, fmt, ...)
++#define EVENT_LOG_COMPACT_CAST(tag, fmt, ...)
++
++#define EVENT_LOG_CAST_PAREN_ARGS(tag, pargs)
++#define EVENT_LOG_FAST_CAST_PAREN_ARGS(tag, pargs)
++#define EVENT_LOG_COMPACT_CAST_PAREN_ARGS(tag, pargs)
++
++#define EVENT_LOG_IS_ON(tag)		0
++#define EVENT_LOG_IS_LOG_ON(tag)	0
++
++#define EVENT_LOG_BUFFER(tag, buf, size)
++
++#else  /* EVENT_LOG_COMPILE */
++
++/* The first few are special because they can be done more efficiently
++ * this way and they are the common case.  Once there are too many
++ * parameters the code size starts to be an issue and a loop is better
++ */
++#define _EVENT_LOG0(tag, fmt_num) 			\
++	event_log0(tag, fmt_num)
++#define _EVENT_LOG1(tag, fmt_num, t1) 			\
++	event_log1(tag, fmt_num, t1)
++#define _EVENT_LOG2(tag, fmt_num, t1, t2) 		\
++	event_log2(tag, fmt_num, t1, t2)
++#define _EVENT_LOG3(tag, fmt_num, t1, t2, t3) 		\
++	event_log3(tag, fmt_num, t1, t2, t3)
++#define _EVENT_LOG4(tag, fmt_num, t1, t2, t3, t4) 	\
++	event_log4(tag, fmt_num, t1, t2, t3, t4)
++
++/* The rest call the generic routine that takes a count */
++#define _EVENT_LOG5(tag, fmt_num, ...) event_logn(5, tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOG6(tag, fmt_num, ...) event_logn(6, tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOG7(tag, fmt_num, ...) event_logn(7, tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOG8(tag, fmt_num, ...) event_logn(8, tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOG9(tag, fmt_num, ...) event_logn(9, tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOGA(tag, fmt_num, ...) event_logn(10, tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOGB(tag, fmt_num, ...) event_logn(11, tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOGC(tag, fmt_num, ...) event_logn(12, tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOGD(tag, fmt_num, ...) event_logn(13, tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOGE(tag, fmt_num, ...) event_logn(14, tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOGF(tag, fmt_num, ...) event_logn(15, tag, fmt_num, __VA_ARGS__)
++
++
++/* Casting  low level macros */
++#define _EVENT_LOG_CAST0(tag, fmt_num)			\
++	event_log0(tag, fmt_num)
++#define _EVENT_LOG_CAST1(tag, fmt_num, t1)		\
++	event_log1(tag, fmt_num, (uint32)(t1))
++#define _EVENT_LOG_CAST2(tag, fmt_num, t1, t2)		\
++	event_log2(tag, fmt_num, (uint32)(t1), (uint32)(t2))
++#define _EVENT_LOG_CAST3(tag, fmt_num, t1, t2, t3)	\
++	event_log3(tag, fmt_num, (uint32)(t1), (uint32)(t2), (uint32)(t3))
++#define _EVENT_LOG_CAST4(tag, fmt_num, t1, t2, t3, t4)	\
++	event_log4(tag, fmt_num, (uint32)(t1), (uint32)(t2), (uint32)(t3), (uint32)(t4))
++
++/* The rest call the generic routine that takes a count */
++#define _EVENT_LOG_CAST5(tag, fmt_num, ...) _EVENT_LOG5(tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOG_CAST6(tag, fmt_num, ...) _EVENT_LOG6(tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOG_CAST7(tag, fmt_num, ...) _EVENT_LOG7(tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOG_CAST8(tag, fmt_num, ...) _EVENT_LOG8(tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOG_CAST9(tag, fmt_num, ...) _EVENT_LOG9(tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOG_CASTA(tag, fmt_num, ...) _EVENT_LOGA(tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOG_CASTB(tag, fmt_num, ...) _EVENT_LOGB(tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOG_CASTC(tag, fmt_num, ...) _EVENT_LOGC(tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOG_CASTD(tag, fmt_num, ...) _EVENT_LOGD(tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOG_CASTE(tag, fmt_num, ...) _EVENT_LOGE(tag, fmt_num, __VA_ARGS__)
++#define _EVENT_LOG_CASTF(tag, fmt_num, ...) _EVENT_LOGF(tag, fmt_num, __VA_ARGS__)
++
++/* Hack to make the proper routine call when variadic macros get
++ * passed.  Note the max of 15 arguments.  More than that can't be
++ * handled by the event_log entries anyways so best to catch it at compile
++ * time
++ */
++
++#define _EVENT_LOG_VA_NUM_ARGS(F, _1, _2, _3, _4, _5, _6, _7, _8, _9,	\
++			       _A, _B, _C, _D, _E, _F, N, ...) F ## N
++
++/* cast = _EVENT_LOG for no casting
++ * cast = _EVENT_LOG_CAST for casting of fmt arguments to uint32.
++ *        Only first 4 arguments are casted to uint32. event_logn() is called
++ *        if more than 4 arguments are present. This function internally assumes
++ *        all arguments are uint32
++ */
++#define _EVENT_LOG(cast, tag, fmt, ...)					\
++	static char logstr[] __attribute__ ((section(".logstrs"))) = fmt; \
++	static uint32 fmtnum __attribute__ ((section(".lognums"))) = (uint32) &logstr; \
++	_EVENT_LOG_VA_NUM_ARGS(cast, ##__VA_ARGS__,			\
++			       F, E, D, C, B, A, 9, 8,			\
++			       7, 6, 5, 4, 3, 2, 1, 0)			\
++	(tag, (int) &fmtnum , ## __VA_ARGS__)
++
++
++#define EVENT_LOG_FAST(tag, fmt, ...)					\
++	do {								\
++		if (event_log_tag_sets != NULL) {			\
++			uint8 tag_flag = *(event_log_tag_sets + tag);	\
++			if ((tag_flag & ~EVENT_LOG_TAG_FLAG_SET_MASK) != 0) {		\
++				_EVENT_LOG(_EVENT_LOG, tag, fmt , ## __VA_ARGS__);	\
++			}						\
++		}							\
++	} while (0)
++
++#define EVENT_LOG_COMPACT(tag, fmt, ...)				\
++	do {								\
++		_EVENT_LOG(_EVENT_LOG, tag, fmt , ## __VA_ARGS__);	\
++	} while (0)
++
++/* Event log macro with casting to uint32 of arguments */
++#define EVENT_LOG_FAST_CAST(tag, fmt, ...)				\
++	do {								\
++		if (event_log_tag_sets != NULL) {			\
++			uint8 tag_flag = *(event_log_tag_sets + tag);	\
++			if ((tag_flag & ~EVENT_LOG_TAG_FLAG_SET_MASK) != 0) {		\
++				_EVENT_LOG(_EVENT_LOG_CAST, tag, fmt , ## __VA_ARGS__);	\
++			}						\
++		}							\
++	} while (0)
++
++#define EVENT_LOG_COMPACT_CAST(tag, fmt, ...)				\
++	do {								\
++		_EVENT_LOG(_EVENT_LOG_CAST, tag, fmt , ## __VA_ARGS__);	\
++	} while (0)
++
++
++#define EVENT_LOG(tag, fmt, ...) EVENT_LOG_COMPACT(tag, fmt , ## __VA_ARGS__)
++
++#define EVENT_LOG_CAST(tag, fmt, ...) EVENT_LOG_COMPACT_CAST(tag, fmt , ## __VA_ARGS__)
++
++#define _EVENT_LOG_REMOVE_PAREN(...) __VA_ARGS__
++#define EVENT_LOG_REMOVE_PAREN(args) _EVENT_LOG_REMOVE_PAREN args
++
++#define EVENT_LOG_CAST_PAREN_ARGS(tag, pargs)				\
++		EVENT_LOG_CAST(tag, EVENT_LOG_REMOVE_PAREN(pargs))
++
++#define EVENT_LOG_FAST_CAST_PAREN_ARGS(tag, pargs)			\
++		EVENT_LOG_FAST_CAST(tag, EVENT_LOG_REMOVE_PAREN(pargs))
++
++#define EVENT_LOG_COMPACT_CAST_PAREN_ARGS(tag, pargs)			\
++		EVENT_LOG_COMPACT_CAST(tag, EVENT_LOG_REMOVE_PAREN(pargs))
++
++/* Minimal event logging. Event log internally calls event_logx()
++ * log return address in caller.
++ * Note that the if(0){..} below is to avoid compiler warnings
++ * due to unused variables caused by this macro
++ */
++#define EVENT_LOG_RA(tag, args)						\
++	do {								\
++		if (0) {						\
++			EVENT_LOG_COMPACT_CAST_PAREN_ARGS(tag, args);	\
++		}							\
++		event_log_caller_return_address(tag);			\
++	} while (0)
++
++#define EVENT_LOG_IS_LOG_ON(tag) (*(event_log_tag_sets + (tag)) & EVENT_LOG_TAG_FLAG_LOG)
++
++#define EVENT_DUMP	event_log_buffer
++
++extern uint8 *event_log_tag_sets;
++
++extern int event_log_init(osl_t *osh);
++extern int event_log_set_init(osl_t *osh, int set_num, int size);
++extern int event_log_set_expand(osl_t *osh, int set_num, int size);
++extern int event_log_set_shrink(osl_t *osh, int set_num, int size);
++
++extern int event_log_tag_start(int tag, int set_num, int flags);
++extern int event_log_tag_stop(int tag);
++
++typedef void (*event_log_logtrace_trigger_fn_t)(void *ctx);
++void event_log_set_logtrace_trigger_fn(event_log_logtrace_trigger_fn_t fn, void *ctx);
++
++event_log_top_t *event_log_get_top(void);
++
++extern int event_log_get(int set_num, int buflen, void *buf);
++
++extern uint8 *event_log_next_logtrace(int set_num);
++
++extern void event_log0(int tag, int fmtNum);
++extern void event_log1(int tag, int fmtNum, uint32 t1);
++extern void event_log2(int tag, int fmtNum, uint32 t1, uint32 t2);
++extern void event_log3(int tag, int fmtNum, uint32 t1, uint32 t2, uint32 t3);
++extern void event_log4(int tag, int fmtNum, uint32 t1, uint32 t2, uint32 t3, uint32 t4);
++extern void event_logn(int num_args, int tag, int fmtNum, ...);
++
++extern void event_log_time_sync(uint32 ms);
++extern void event_log_buffer(int tag, uint8 *buf, int size);
++extern void event_log_caller_return_address(int tag);
++extern int event_log_set_destination_set(int set, event_log_set_destination_t dest);
++extern event_log_set_destination_t event_log_set_destination_get(int set);
++
++#endif /* EVENT_LOG_DUMPER */
++
++#endif /* EVENT_LOG_COMPILE */
++
++#endif /* __ASSEMBLER__ */
++
++#endif /* _EVENT_LOG_H_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/event_log_payload.h b/module_drivers/drivers/net/wireless/bcmdhd/include/event_log_payload.h
+new file mode 100644
+index 000000000..d01264c5b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/event_log_payload.h
+@@ -0,0 +1,673 @@
++/*
++ * EVENT_LOG System Definitions
++ *
++ * This file describes the payloads of event log entries that are data buffers
++ * rather than formatted string entries. The contents are generally XTLVs.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: event_log_payload.h 700076 2017-05-17 14:42:22Z $
++ */
++
++#ifndef _EVENT_LOG_PAYLOAD_H_
++#define _EVENT_LOG_PAYLOAD_H_
++
++#include <typedefs.h>
++#include <bcmutils.h>
++#include <ethernet.h>
++#include <event_log_tag.h>
++
++#define EVENT_LOG_XTLV_ID_STR                   0  /**< XTLV ID for a string */
++#define EVENT_LOG_XTLV_ID_TXQ_SUM               1  /**< XTLV ID for txq_summary_t */
++#define EVENT_LOG_XTLV_ID_SCBDATA_SUM           2  /**< XTLV ID for cb_subq_summary_t */
++#define EVENT_LOG_XTLV_ID_SCBDATA_AMPDU_TX_SUM  3  /**< XTLV ID for scb_ampdu_tx_summary_t */
++#define EVENT_LOG_XTLV_ID_BSSCFGDATA_SUM        4  /**< XTLV ID for bsscfg_q_summary_t */
++#define EVENT_LOG_XTLV_ID_UCTXSTATUS            5  /**< XTLV ID for ucode TxStatus array */
++#define EVENT_LOG_XTLV_ID_TXQ_SUM_V2            6  /**< XTLV ID for txq_summary_v2_t */
++
++/**
++ * An XTLV holding a string
++ * String is not null terminated, length is the XTLV len.
++ */
++typedef struct xtlv_string {
++	uint16 id;              /* XTLV ID: EVENT_LOG_XTLV_ID_STR */
++	uint16 len;             /* XTLV Len (String length) */
++	char   str[1];          /* var len array characters */
++} xtlv_string_t;
++
++#define XTLV_STRING_FULL_LEN(str_len)     (BCM_XTLV_HDR_SIZE + (str_len) * sizeof(char))
++
++/**
++ * Summary for a single TxQ context
++ * Two of these will be used per TxQ context---one for the high TxQ, and one for
++ * the low txq that contains DMA prepared pkts. The high TxQ is a full multi-precidence
++ * queue and also has a BSSCFG map to identify the BSSCFGS associated with the queue context.
++ * The low txq counterpart does not populate the BSSCFG map.
++ * The excursion queue will have no bsscfgs associated and is the first queue dumped.
++ */
++typedef struct txq_summary {
++	uint16 id;              /* XTLV ID: EVENT_LOG_XTLV_ID_TXQ_SUM */
++	uint16 len;             /* XTLV Len */
++	uint32 bsscfg_map;      /* bitmap of bsscfg indexes associated with this queue */
++	uint32 stopped;         /* flow control bitmap */
++	uint8  prec_count;      /* count of precedences/fifos and len of following array */
++	uint8  pad;
++	uint16 plen[1];         /* var len array of lengths of each prec/fifo in the queue */
++} txq_summary_t;
++
++#define TXQ_SUMMARY_LEN                   (OFFSETOF(txq_summary_t, plen))
++#define TXQ_SUMMARY_FULL_LEN(num_q)       (TXQ_SUMMARY_LEN + (num_q) * sizeof(uint16))
++
++typedef struct txq_summary_v2 {
++	uint16 id;              /* XTLV ID: EVENT_LOG_XTLV_ID_TXQ_SUM_V2 */
++	uint16 len;             /* XTLV Len */
++	uint32 bsscfg_map;      /* bitmap of bsscfg indexes associated with this queue */
++	uint32 stopped;         /* flow control bitmap */
++	uint32 hw_stopped;      /* flow control bitmap */
++	uint8  prec_count;      /* count of precedences/fifos and len of following array */
++	uint8  pad;
++	uint16 plen[1];         /* var len array of lengths of each prec/fifo in the queue */
++} txq_summary_v2_t;
++
++#define TXQ_SUMMARY_V2_LEN                (OFFSETOF(txq_summary_v2_t, plen))
++#define TXQ_SUMMARY_V2_FULL_LEN(num_q)    (TXQ_SUMMARY_V2_LEN + (num_q) * sizeof(uint16))
++
++/**
++ * Summary for tx datapath of an SCB cubby
++ * This is a generic summary structure (one size fits all) with
++ * a cubby ID and sub-ID to differentiate SCB cubby types and possible sub-queues.
++ */
++typedef struct scb_subq_summary {
++	uint16 id;             /* XTLV ID: EVENT_LOG_XTLV_ID_SCBDATA_SUM */
++	uint16 len;            /* XTLV Len */
++	uint32 flags;          /* cubby specficic flags */
++	uint8  cubby_id;       /* ID registered for cubby */
++	uint8  sub_id;         /* sub ID if a cubby has more than one queue */
++	uint8  prec_count;     /* count of precedences/fifos and len of following array */
++	uint8  pad;
++	uint16 plen[1];        /* var len array of lengths of each prec/fifo in the queue */
++} scb_subq_summary_t;
++
++#define SCB_SUBQ_SUMMARY_LEN              (OFFSETOF(scb_subq_summary_t, plen))
++#define SCB_SUBQ_SUMMARY_FULL_LEN(num_q)  (SCB_SUBQ_SUMMARY_LEN + (num_q) * sizeof(uint16))
++
++/* scb_subq_summary_t.flags for APPS */
++#define SCBDATA_APPS_F_PS               0x00000001
++#define SCBDATA_APPS_F_PSPEND           0x00000002
++#define SCBDATA_APPS_F_INPVB            0x00000004
++#define SCBDATA_APPS_F_APSD_USP         0x00000008
++#define SCBDATA_APPS_F_TXBLOCK          0x00000010
++#define SCBDATA_APPS_F_APSD_HPKT_TMR    0x00000020
++#define SCBDATA_APPS_F_APSD_TX_PEND     0x00000040
++#define SCBDATA_APPS_F_INTRANS          0x00000080
++#define SCBDATA_APPS_F_OFF_PEND         0x00000100
++#define SCBDATA_APPS_F_OFF_BLOCKED      0x00000200
++#define SCBDATA_APPS_F_OFF_IN_PROG      0x00000400
++
++
++/**
++ * Summary for tx datapath AMPDU SCB cubby
++ * This is a specific data structure to describe the AMPDU datapath state for an SCB
++ * used instead of scb_subq_summary_t.
++ * Info is for one TID, so one will be dumped per BA TID active for an SCB.
++ */
++typedef struct scb_ampdu_tx_summary {
++	uint16 id;              /* XTLV ID: EVENT_LOG_XTLV_ID_SCBDATA_AMPDU_TX_SUM */
++	uint16 len;             /* XTLV Len */
++	uint32 flags;           /* misc flags */
++	uint8  tid;             /* initiator TID (priority) */
++	uint8  ba_state;        /* internal BA state */
++	uint8  bar_cnt;         /* number of bars sent with no progress */
++	uint8  retry_bar;       /* reason code if bar to be retried at watchdog */
++	uint16 barpending_seq;  /* seqnum for bar */
++	uint16 bar_ackpending_seq; /* seqnum of bar for which ack is pending */
++	uint16 start_seq;       /* seqnum of the first unacknowledged packet */
++	uint16 max_seq;         /* max unacknowledged seqnum sent */
++	uint32 released_bytes_inflight; /* Number of bytes pending in bytes */
++	uint32 released_bytes_target;
++} scb_ampdu_tx_summary_t;
++
++/* scb_ampdu_tx_summary.flags defs */
++#define SCBDATA_AMPDU_TX_F_BAR_ACKPEND          0x00000001 /* bar_ackpending */
++
++/** XTLV stuct to summarize a BSSCFG's packet queue */
++typedef struct bsscfg_q_summary {
++	uint16 id;               /* XTLV ID: EVENT_LOG_XTLV_ID_BSSCFGDATA_SUM */
++	uint16 len;              /* XTLV Len */
++	struct ether_addr BSSID; /* BSSID */
++	uint8  bsscfg_idx;       /* bsscfg index */
++	uint8  type;             /* bsscfg type enumeration: BSSCFG_TYPE_XXX */
++	uint8  subtype;          /* bsscfg subtype enumeration: BSSCFG_SUBTYPE_XXX */
++	uint8  prec_count;       /* count of precedences/fifos and len of following array */
++	uint16 plen[1];          /* var len array of lengths of each prec/fifo in the queue */
++} bsscfg_q_summary_t;
++
++#define BSSCFG_Q_SUMMARY_LEN              (OFFSETOF(bsscfg_q_summary_t, plen))
++#define BSSCFG_Q_SUMMARY_FULL_LEN(num_q)  (BSSCFG_Q_SUMMARY_LEN + (num_q) * sizeof(uint16))
++
++/**
++ * An XTLV holding a TxStats array
++ * TxStatus entries are 8 or 16 bytes, size in words (2 or 4) givent in
++ * entry_size field.
++ * Array is uint32 words
++ */
++typedef struct xtlv_uc_txs {
++	uint16 id;              /* XTLV ID: EVENT_LOG_XTLV_ID_UCTXSTATUS */
++	uint16 len;             /* XTLV Len */
++	uint8  entry_size;      /* num uint32 words per entry */
++	uint8  pad[3];          /* reserved, zero */
++	uint32 w[1];            /* var len array of words */
++} xtlv_uc_txs_t;
++
++#define XTLV_UCTXSTATUS_LEN                (OFFSETOF(xtlv_uc_txs_t, w))
++#define XTLV_UCTXSTATUS_FULL_LEN(words)    (XTLV_UCTXSTATUS_LEN + (words) * sizeof(uint32))
++
++#define SCAN_SUMMARY_VERSION	1
++/* Scan flags */
++#define SCAN_SUM_CHAN_INFO	0x1
++/* Scan_sum flags */
++#define BAND5G_SIB_ENAB	0x2
++#define BAND2G_SIB_ENAB	0x4
++#define PARALLEL_SCAN	0x8
++#define SCAN_ABORT	0x10
++
++/* scan_channel_info flags */
++#define ACTIVE_SCAN_SCN_SUM	0x2
++#define SCAN_SUM_WLC_CORE0	0x4
++#define SCAN_SUM_WLC_CORE1	0x8
++#define HOME_CHAN	0x10
++
++typedef struct wl_scan_ssid_info
++{
++	uint8		ssid_len;	/* the length of SSID */
++	uint8		ssid[32];	/* SSID string */
++} wl_scan_ssid_info_t;
++
++typedef struct wl_scan_channel_info {
++	uint16 chanspec;	/* chanspec scanned */
++	uint16 reserv;
++	uint32 start_time;		/* Scan start time in
++				* milliseconds for the chanspec
++				* or home_dwell time start
++				*/
++	uint32 end_time;		/* Scan end time in
++				* milliseconds for the chanspec
++				* or home_dwell time end
++				*/
++	uint16 probe_count;	/* No of probes sent out. For future use
++				*/
++	uint16 scn_res_count;	/* Count of scan_results found per
++				* channel. For future use
++				*/
++} wl_scan_channel_info_t;
++
++typedef struct wl_scan_summary_info {
++	uint32 total_chan_num;	/* Total number of channels scanned */
++	uint32 scan_start_time;	/* Scan start time in milliseconds */
++	uint32 scan_end_time;	/* Scan end time in milliseconds */
++	wl_scan_ssid_info_t ssid[1];	/* SSID being scanned in current
++				* channel. For future use
++				*/
++} wl_scan_summary_info_t;
++
++struct wl_scan_summary {
++	uint8 version;		/* Version */
++	uint8 reserved;
++	uint16 len;		/* Length of the data buffer including SSID
++				 * list.
++				 */
++	uint16 sync_id;		/* Scan Sync ID */
++	uint16 scan_flags;		/* flags [0] or SCAN_SUM_CHAN_INFO = */
++				/* channel_info, if not set */
++				/* it is scan_summary_info */
++				/* when channel_info is used, */
++				/* the following flag bits are overridden: */
++				/* flags[1] or ACTIVE_SCAN_SCN_SUM = active channel if set */
++				/* passive if not set */
++				/* flags[2] or WLC_CORE0 = if set, represents wlc_core0 */
++				/* flags[3] or WLC_CORE1 = if set, represents wlc_core1 */
++				/* flags[4] or HOME_CHAN = if set, represents home-channel */
++				/* flags[5:15] = reserved */
++				/* when scan_summary_info is used, */
++				/* the following flag bits are used: */
++				/* flags[1] or BAND5G_SIB_ENAB = */
++				/* allowSIBParallelPassiveScan on 5G band */
++				/* flags[2] or BAND2G_SIB_ENAB = */
++				/* allowSIBParallelPassiveScan on 2G band */
++				/* flags[3] or PARALLEL_SCAN = Parallel scan enabled or not */
++				/* flags[4] or SCAN_ABORT = SCAN_ABORTED scenario */
++				/* flags[5:15] = reserved */
++	union {
++		wl_scan_channel_info_t scan_chan_info;	/* scan related information
++							* for each channel scanned
++							*/
++		wl_scan_summary_info_t scan_sum_info;	/* Cumulative scan related
++							* information.
++							*/
++	} u;
++};
++
++/* Channel switch log record structure
++ * Host may map the following structure on channel switch event log record
++ * received from dongle. Note that all payload entries in event log record are
++ * uint32/int32.
++ */
++typedef struct wl_chansw_event_log_record {
++	uint32 time;			/* Time in us */
++	uint32 old_chanspec;		/* Old channel spec */
++	uint32 new_chanspec;		/* New channel spec */
++	uint32 chansw_reason;		/* Reason for channel change */
++	int32 dwell_time;
++} wl_chansw_event_log_record_t;
++
++/* Sub-block type for EVENT_LOG_TAG_AMPDU_DUMP */
++#define WL_AMPDU_STATS_TYPE_RXMCSx1	0	/* RX MCS rate (Nss = 1) */
++#define WL_AMPDU_STATS_TYPE_RXMCSx2	1
++#define WL_AMPDU_STATS_TYPE_RXMCSx3	2
++#define WL_AMPDU_STATS_TYPE_RXMCSx4	3
++#define WL_AMPDU_STATS_TYPE_RXVHTx1	4	/* RX VHT rate (Nss = 1) */
++#define WL_AMPDU_STATS_TYPE_RXVHTx2	5
++#define WL_AMPDU_STATS_TYPE_RXVHTx3	6
++#define WL_AMPDU_STATS_TYPE_RXVHTx4	7
++#define WL_AMPDU_STATS_TYPE_TXMCSx1	8	/* TX MCS rate (Nss = 1) */
++#define WL_AMPDU_STATS_TYPE_TXMCSx2	9
++#define WL_AMPDU_STATS_TYPE_TXMCSx3	10
++#define WL_AMPDU_STATS_TYPE_TXMCSx4	11
++#define WL_AMPDU_STATS_TYPE_TXVHTx1	12	/* TX VHT rate (Nss = 1) */
++#define WL_AMPDU_STATS_TYPE_TXVHTx2	13
++#define WL_AMPDU_STATS_TYPE_TXVHTx3	14
++#define WL_AMPDU_STATS_TYPE_TXVHTx4	15
++#define WL_AMPDU_STATS_TYPE_RXMCSSGI	16	/* RX SGI usage (for all MCS rates) */
++#define WL_AMPDU_STATS_TYPE_TXMCSSGI	17	/* TX SGI usage (for all MCS rates) */
++#define WL_AMPDU_STATS_TYPE_RXVHTSGI	18	/* RX SGI usage (for all VHT rates) */
++#define WL_AMPDU_STATS_TYPE_TXVHTSGI	19	/* TX SGI usage (for all VHT rates) */
++#define WL_AMPDU_STATS_TYPE_RXMCSPER	20	/* RX PER (for all MCS rates) */
++#define WL_AMPDU_STATS_TYPE_TXMCSPER	21	/* TX PER (for all MCS rates) */
++#define WL_AMPDU_STATS_TYPE_RXVHTPER	22	/* RX PER (for all VHT rates) */
++#define WL_AMPDU_STATS_TYPE_TXVHTPER	23	/* TX PER (for all VHT rates) */
++#define WL_AMPDU_STATS_TYPE_RXDENS	24	/* RX AMPDU density */
++#define WL_AMPDU_STATS_TYPE_TXDENS	25	/* TX AMPDU density */
++#define WL_AMPDU_STATS_TYPE_RXMCSOK	26	/* RX all MCS rates */
++#define WL_AMPDU_STATS_TYPE_RXVHTOK	27	/* RX all VHT rates */
++#define WL_AMPDU_STATS_TYPE_TXMCSALL	28	/* TX all MCS rates */
++#define WL_AMPDU_STATS_TYPE_TXVHTALL	29	/* TX all VHT rates */
++#define WL_AMPDU_STATS_TYPE_TXMCSOK	30	/* TX all MCS rates */
++#define WL_AMPDU_STATS_TYPE_TXVHTOK	31	/* TX all VHT rates */
++
++#define WL_AMPDU_STATS_MAX_CNTS		64
++
++typedef struct {
++	uint16	type;		/* AMPDU statistics sub-type */
++	uint16	len;		/* Number of 32-bit counters */
++	uint32	counters[WL_AMPDU_STATS_MAX_CNTS];
++} wl_ampdu_stats_generic_t;
++
++typedef struct {
++	uint16	type;		/* AMPDU statistics sub-type */
++	uint16	len;		/* Number of 32-bit counters + 2 */
++	uint32	total_ampdu;
++	uint32	total_mpdu;
++	uint32	aggr_dist[WL_AMPDU_STATS_MAX_CNTS + 1];
++} wl_ampdu_stats_aggrsz_t;
++
++/* Sub-block type for EVENT_LOG_TAG_MSCHPROFILE */
++#define WL_MSCH_PROFILER_START		0	/* start event check */
++#define WL_MSCH_PROFILER_EXIT		1	/* exit event check */
++#define WL_MSCH_PROFILER_REQ		2	/* request event */
++#define WL_MSCH_PROFILER_CALLBACK	3	/* call back event */
++#define WL_MSCH_PROFILER_MESSAGE	4	/* message event */
++#define WL_MSCH_PROFILER_PROFILE_START	5
++#define WL_MSCH_PROFILER_PROFILE_END	6
++#define WL_MSCH_PROFILER_REQ_HANDLE	7
++#define WL_MSCH_PROFILER_REQ_ENTITY	8
++#define WL_MSCH_PROFILER_CHAN_CTXT	9
++#define WL_MSCH_PROFILER_EVENT_LOG	10
++#define WL_MSCH_PROFILER_REQ_TIMING	11
++#define WL_MSCH_PROFILER_TYPE_MASK	0x00ff
++#define WL_MSCH_PROFILER_WLINDEX_SHIFT	8
++#define WL_MSCH_PROFILER_WLINDEX_MASK	0x0f00
++#define WL_MSCH_PROFILER_VER_SHIFT	12
++#define WL_MSCH_PROFILER_VER_MASK	0xf000
++
++/* MSCH Event data current verion */
++#define WL_MSCH_PROFILER_VER		2
++
++/* msch version history */
++#define WL_MSCH_PROFILER_RSDB_VER	1
++#define WL_MSCH_PROFILER_REPORT_VER	2
++
++/* msch collect header size */
++#define WL_MSCH_PROFILE_HEAD_SIZE	OFFSETOF(msch_collect_tlv_t, value)
++
++/* msch event log header size */
++#define WL_MSCH_EVENT_LOG_HEAD_SIZE	OFFSETOF(msch_event_log_profiler_event_data_t, data)
++
++/* MSCH data buffer size */
++#define WL_MSCH_PROFILER_BUFFER_SIZE	512
++
++/* request type used in wlc_msch_req_param_t struct */
++#define WL_MSCH_RT_BOTH_FIXED	0	/* both start and end time is fixed */
++#define WL_MSCH_RT_START_FLEX	1	/* start time is flexible and duration is fixed */
++#define WL_MSCH_RT_DUR_FLEX	2	/* start time is fixed and end time is flexible */
++#define WL_MSCH_RT_BOTH_FLEX	3	/* Both start and duration is flexible */
++
++/* Flags used in wlc_msch_req_param_t struct */
++#define WL_MSCH_REQ_FLAGS_CHAN_CONTIGUOUS  (1 << 0) /* Don't break up channels in chanspec_list */
++#define WL_MSCH_REQ_FLAGS_MERGE_CONT_SLOTS (1 << 1)  /* No slot end if slots are continous */
++#define WL_MSCH_REQ_FLAGS_PREMTABLE        (1 << 2) /* Req can be pre-empted by PREMT_CURTS req */
++#define WL_MSCH_REQ_FLAGS_PREMT_CURTS      (1 << 3) /* Pre-empt request at the end of curts */
++#define WL_MSCH_REQ_FLAGS_PREMT_IMMEDIATE  (1 << 4) /* Pre-empt cur_ts immediately */
++
++/* Requested slot Callback states
++ * req->pend_slot/cur_slot->flags
++ */
++#define WL_MSCH_RC_FLAGS_ONCHAN_FIRE		(1 << 0)
++#define WL_MSCH_RC_FLAGS_START_FIRE_DONE	(1 << 1)
++#define WL_MSCH_RC_FLAGS_END_FIRE_DONE		(1 << 2)
++#define WL_MSCH_RC_FLAGS_ONFIRE_DONE		(1 << 3)
++#define WL_MSCH_RC_FLAGS_SPLIT_SLOT_START	(1 << 4)
++#define WL_MSCH_RC_FLAGS_SPLIT_SLOT_END		(1 << 5)
++#define WL_MSCH_RC_FLAGS_PRE_ONFIRE_DONE	(1 << 6)
++
++/* Request entity flags */
++#define WL_MSCH_ENTITY_FLAG_MULTI_INSTANCE	(1 << 0)
++
++/* Request Handle flags */
++#define WL_MSCH_REQ_HDL_FLAGS_NEW_REQ		(1 << 0) /* req_start callback */
++
++/* MSCH state flags (msch_info->flags) */
++#define	WL_MSCH_STATE_IN_TIEMR_CTXT		0x1
++#define WL_MSCH_STATE_SCHD_PENDING		0x2
++
++/* MSCH callback type */
++#define	WL_MSCH_CT_REQ_START		0x1
++#define	WL_MSCH_CT_ON_CHAN		0x2
++#define	WL_MSCH_CT_SLOT_START		0x4
++#define	WL_MSCH_CT_SLOT_END		0x8
++#define	WL_MSCH_CT_SLOT_SKIP		0x10
++#define	WL_MSCH_CT_OFF_CHAN		0x20
++#define WL_MSCH_CT_OFF_CHAN_DONE	0x40
++#define	WL_MSCH_CT_REQ_END		0x80
++#define	WL_MSCH_CT_PARTIAL		0x100
++#define	WL_MSCH_CT_PRE_ONCHAN		0x200
++#define	WL_MSCH_CT_PRE_REQ_START	0x400
++
++/* MSCH command bits */
++#define WL_MSCH_CMD_ENABLE_BIT		0x01
++#define WL_MSCH_CMD_PROFILE_BIT		0x02
++#define WL_MSCH_CMD_CALLBACK_BIT	0x04
++#define WL_MSCH_CMD_REGISTER_BIT	0x08
++#define WL_MSCH_CMD_ERROR_BIT		0x10
++#define WL_MSCH_CMD_DEBUG_BIT		0x20
++#define WL_MSCH_CMD_INFOM_BIT		0x40
++#define WL_MSCH_CMD_TRACE_BIT		0x80
++#define WL_MSCH_CMD_ALL_BITS		0xfe
++#define WL_MSCH_CMD_SIZE_MASK		0x00ff0000
++#define WL_MSCH_CMD_SIZE_SHIFT		16
++#define WL_MSCH_CMD_VER_MASK		0xff000000
++#define WL_MSCH_CMD_VER_SHIFT		24
++
++/* maximum channels returned by the get valid channels iovar */
++#define WL_MSCH_NUMCHANNELS		64
++
++typedef struct msch_collect_tlv {
++	uint16	type;
++	uint16	size;
++	char	value[1];
++} msch_collect_tlv_t;
++
++typedef struct msch_profiler_event_data {
++	uint32	time_lo;		/* Request time */
++	uint32	time_hi;
++} msch_profiler_event_data_t;
++
++typedef struct msch_start_profiler_event_data {
++	uint32	time_lo;		/* Request time */
++	uint32	time_hi;
++	uint32	status;
++} msch_start_profiler_event_data_t;
++
++typedef struct msch_message_profiler_event_data {
++	uint32	time_lo;		/* Request time */
++	uint32	time_hi;
++	char	message[1];		/* message */
++} msch_message_profiler_event_data_t;
++
++typedef struct msch_event_log_profiler_event_data {
++	uint32	time_lo;		/* Request time */
++	uint32	time_hi;
++	event_log_hdr_t hdr;		/* event log header */
++	uint32	data[9];		/* event data */
++} msch_event_log_profiler_event_data_t;
++
++typedef struct msch_req_param_profiler_event_data {
++	uint16  flags;			/* Describe various request properties */
++	uint8	req_type;		/* Describe start and end time flexiblilty */
++	uint8	priority;		/* Define the request priority */
++	uint32	start_time_l;		/* Requested start time offset in us unit */
++	uint32	start_time_h;
++	uint32	duration;		/* Requested duration in us unit */
++	uint32	interval;		/* Requested periodic interval in us unit,
++					 * 0 means non-periodic
++					 */
++	union {
++		uint32	dur_flex;	/* MSCH_REG_DUR_FLEX, min_dur = duration - dur_flex */
++		struct {
++			uint32 min_dur;	/* min duration for traffic, maps to home_time */
++			uint32 max_away_dur; /* max acceptable away dur, maps to home_away_time */
++			uint32 hi_prio_time_l;
++			uint32 hi_prio_time_h;
++			uint32 hi_prio_interval; /* repeated high priority interval */
++		} bf;
++	} flex;
++} msch_req_param_profiler_event_data_t;
++
++typedef struct msch_req_timing_profiler_event_data {
++	uint32 p_req_timing;
++	uint32 p_prev;
++	uint32 p_next;
++	uint16 flags;
++	uint16 timeslot_ptr;
++	uint32 fire_time_l;
++	uint32 fire_time_h;
++	uint32 pre_start_time_l;
++	uint32 pre_start_time_h;
++	uint32 start_time_l;
++	uint32 start_time_h;
++	uint32 end_time_l;
++	uint32 end_time_h;
++	uint32 p_timeslot;
++} msch_req_timing_profiler_event_data_t;
++
++typedef struct msch_chan_ctxt_profiler_event_data {
++	uint32 p_chan_ctxt;
++	uint32 p_prev;
++	uint32 p_next;
++	uint16 chanspec;
++	uint16 bf_sch_pending;
++	uint32 bf_link_prev;
++	uint32 bf_link_next;
++	uint32 onchan_time_l;
++	uint32 onchan_time_h;
++	uint32 actual_onchan_dur_l;
++	uint32 actual_onchan_dur_h;
++	uint32 pend_onchan_dur_l;
++	uint32 pend_onchan_dur_h;
++	uint16 req_entity_list_cnt;
++	uint16 req_entity_list_ptr;
++	uint16 bf_entity_list_cnt;
++	uint16 bf_entity_list_ptr;
++	uint32 bf_skipped_count;
++} msch_chan_ctxt_profiler_event_data_t;
++
++typedef struct msch_req_entity_profiler_event_data {
++	uint32 p_req_entity;
++	uint32 req_hdl_link_prev;
++	uint32 req_hdl_link_next;
++	uint32 chan_ctxt_link_prev;
++	uint32 chan_ctxt_link_next;
++	uint32 rt_specific_link_prev;
++	uint32 rt_specific_link_next;
++	uint32 start_fixed_link_prev;
++	uint32 start_fixed_link_next;
++	uint32 both_flex_list_prev;
++	uint32 both_flex_list_next;
++	uint16 chanspec;
++	uint16 priority;
++	uint16 cur_slot_ptr;
++	uint16 pend_slot_ptr;
++	uint16 pad;
++	uint16 chan_ctxt_ptr;
++	uint32 p_chan_ctxt;
++	uint32 p_req_hdl;
++	uint32 bf_last_serv_time_l;
++	uint32 bf_last_serv_time_h;
++	uint16 onchan_chn_idx;
++	uint16 cur_chn_idx;
++	uint32 flags;
++	uint32 actual_start_time_l;
++	uint32 actual_start_time_h;
++	uint32 curts_fire_time_l;
++	uint32 curts_fire_time_h;
++} msch_req_entity_profiler_event_data_t;
++
++typedef struct msch_req_handle_profiler_event_data {
++	uint32 p_req_handle;
++	uint32 p_prev;
++	uint32 p_next;
++	uint32 cb_func;
++	uint32 cb_ctxt;
++	uint16 req_param_ptr;
++	uint16 req_entity_list_cnt;
++	uint16 req_entity_list_ptr;
++	uint16 chan_cnt;
++	uint32 flags;
++	uint16 chanspec_list;
++	uint16 chanspec_cnt;
++	uint16 chan_idx;
++	uint16 last_chan_idx;
++	uint32 req_time_l;
++	uint32 req_time_h;
++} msch_req_handle_profiler_event_data_t;
++
++typedef struct msch_profiler_profiler_event_data {
++	uint32 time_lo;			/* Request time */
++	uint32 time_hi;
++	uint32 free_req_hdl_list;
++	uint32 free_req_entity_list;
++	uint32 free_chan_ctxt_list;
++	uint32 free_chanspec_list;
++	uint16 cur_msch_timeslot_ptr;
++	uint16 next_timeslot_ptr;
++	uint32 p_cur_msch_timeslot;
++	uint32 p_next_timeslot;
++	uint32 cur_armed_timeslot;
++	uint32 flags;
++	uint32 ts_id;
++	uint32 service_interval;
++	uint32 max_lo_prio_interval;
++	uint16 flex_list_cnt;
++	uint16 msch_chanspec_alloc_cnt;
++	uint16 msch_req_entity_alloc_cnt;
++	uint16 msch_req_hdl_alloc_cnt;
++	uint16 msch_chan_ctxt_alloc_cnt;
++	uint16 msch_timeslot_alloc_cnt;
++	uint16 msch_req_hdl_list_cnt;
++	uint16 msch_req_hdl_list_ptr;
++	uint16 msch_chan_ctxt_list_cnt;
++	uint16 msch_chan_ctxt_list_ptr;
++	uint16 msch_req_timing_list_cnt;
++	uint16 msch_req_timing_list_ptr;
++	uint16 msch_start_fixed_list_cnt;
++	uint16 msch_start_fixed_list_ptr;
++	uint16 msch_both_flex_req_entity_list_cnt;
++	uint16 msch_both_flex_req_entity_list_ptr;
++	uint16 msch_start_flex_list_cnt;
++	uint16 msch_start_flex_list_ptr;
++	uint16 msch_both_flex_list_cnt;
++	uint16 msch_both_flex_list_ptr;
++	uint32 slotskip_flag;
++} msch_profiler_profiler_event_data_t;
++
++typedef struct msch_req_profiler_event_data {
++	uint32 time_lo;			/* Request time */
++	uint32 time_hi;
++	uint16 chanspec_cnt;
++	uint16 chanspec_ptr;
++	uint16 req_param_ptr;
++	uint16 pad;
++} msch_req_profiler_event_data_t;
++
++typedef struct msch_callback_profiler_event_data {
++	uint32 time_lo;			/* Request time */
++	uint32 time_hi;
++	uint16 type;			/* callback type */
++	uint16 chanspec;		/* actual chanspec, may different with requested one */
++	uint32 start_time_l;		/* time slot start time low 32bit */
++	uint32 start_time_h;		/* time slot start time high 32bit */
++	uint32 end_time_l;		/* time slot end time low 32 bit */
++	uint32 end_time_h;		/* time slot end time high 32 bit */
++	uint32 timeslot_id;		/* unique time slot id */
++	uint32 p_req_hdl;
++	uint32 onchan_idx;		/* Current channel index */
++	uint32 cur_chan_seq_start_time_l; /* start time of current sequence */
++	uint32 cur_chan_seq_start_time_h;
++} msch_callback_profiler_event_data_t;
++
++typedef struct msch_timeslot_profiler_event_data {
++	uint32 p_timeslot;
++	uint32 timeslot_id;
++	uint32 pre_start_time_l;
++	uint32 pre_start_time_h;
++	uint32 end_time_l;
++	uint32 end_time_h;
++	uint32 sch_dur_l;
++	uint32 sch_dur_h;
++	uint32 p_chan_ctxt;
++	uint32 fire_time_l;
++	uint32 fire_time_h;
++	uint32 state;
++} msch_timeslot_profiler_event_data_t;
++
++typedef struct msch_register_params	{
++	uint16 wlc_index;		/* Optional wlc index */
++	uint16 flags;			/* Describe various request properties */
++	uint32 req_type;		/* Describe start and end time flexiblilty */
++	uint16 id;			/* register id */
++	uint16 priority;		/* Define the request priority */
++	uint32 start_time;		/* Requested start time offset in ms unit */
++	uint32 duration;		/* Requested duration in ms unit */
++	uint32 interval;		/* Requested periodic interval in ms unit,
++					 * 0 means non-periodic
++					 */
++	uint32 dur_flex;		/* MSCH_REG_DUR_FLEX, min_dur = duration - dur_flex */
++	uint32 min_dur;			/* min duration for traffic, maps to home_time */
++	uint32 max_away_dur;		/* max acceptable away dur, maps to home_away_time */
++	uint32 hi_prio_time;
++	uint32 hi_prio_interval;	/* repeated high priority interval */
++	uint32 chanspec_cnt;
++	uint16 chanspec_list[WL_MSCH_NUMCHANNELS];
++} msch_register_params_t;
++
++#endif /* _EVENT_LOG_PAYLOAD_H_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/event_log_set.h b/module_drivers/drivers/net/wireless/bcmdhd/include/event_log_set.h
+new file mode 100644
+index 000000000..db28360ea
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/event_log_set.h
+@@ -0,0 +1,53 @@
++/*
++ * EVENT_LOG system definitions
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: event_log_set.h 700076 2017-05-17 14:42:22Z $
++ */
++
++#ifndef _EVENT_LOG_SET_H_
++#define _EVENT_LOG_SET_H_
++
++/* Set a maximum number of sets here.  It is not dynamic for
++ *  efficiency of the EVENT_LOG calls.
++ */
++#define NUM_EVENT_LOG_SETS 8
++
++/* Define new event log sets here */
++#define EVENT_LOG_SET_BUS	0
++#define EVENT_LOG_SET_WL	1
++#define EVENT_LOG_SET_PSM	2
++#define EVENT_LOG_SET_ERROR	3
++#define EVENT_LOG_SET_MEM_API	4
++/* Share the set with MEM_API for now to limit ROM invalidation.
++ * The above set is used in dingo only
++ * On trunk, MSCH should move to a different set.
++ */
++#define EVENT_LOG_SET_MSCH_PROFILER	4
++#define EVENT_LOG_SET_ECOUNTERS 5	/* Host to instantiate this for ecounters. */
++#define EVENT_LOG_SET_6	6	/* Instantiated by host for channel switch logs */
++#define EVENT_LOG_SET_7	7	/* Instantiated by host for AMPDU stats */
++
++#endif /* _EVENT_LOG_SET_H_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/event_log_tag.h b/module_drivers/drivers/net/wireless/bcmdhd/include/event_log_tag.h
+new file mode 100644
+index 000000000..41332e7aa
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/event_log_tag.h
+@@ -0,0 +1,222 @@
++/*
++ * EVENT_LOG system definitions
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: event_log_tag.h 700681 2017-05-20 16:37:38Z $
++ */
++
++#ifndef _EVENT_LOG_TAG_H_
++#define _EVENT_LOG_TAG_H_
++
++#include <typedefs.h>
++
++/* Define new event log tags here */
++#define EVENT_LOG_TAG_NULL	0	/* Special null tag */
++#define EVENT_LOG_TAG_TS	1	/* Special timestamp tag */
++#define EVENT_LOG_TAG_BUS_OOB	2
++#define EVENT_LOG_TAG_BUS_STATE	3
++#define EVENT_LOG_TAG_BUS_PROTO	4
++#define EVENT_LOG_TAG_BUS_CTL	5
++#define EVENT_LOG_TAG_BUS_EVENT	6
++#define EVENT_LOG_TAG_BUS_PKT	7
++#define EVENT_LOG_TAG_BUS_FRAME	8
++#define EVENT_LOG_TAG_BUS_DESC	9
++#define EVENT_LOG_TAG_BUS_SETUP	10
++#define EVENT_LOG_TAG_BUS_MISC	11
++#define EVENT_LOG_TAG_SRSCAN		22
++#define EVENT_LOG_TAG_PWRSTATS_INFO	23
++#define EVENT_LOG_TAG_UCODE_WATCHDOG 26
++#define EVENT_LOG_TAG_UCODE_FIFO 27
++#define EVENT_LOG_TAG_SCAN_TRACE_LOW	28
++#define EVENT_LOG_TAG_SCAN_TRACE_HIGH	29
++#define EVENT_LOG_TAG_SCAN_ERROR	30
++#define EVENT_LOG_TAG_SCAN_WARN	31
++#define EVENT_LOG_TAG_MPF_ERR	32
++#define EVENT_LOG_TAG_MPF_WARN	33
++#define EVENT_LOG_TAG_MPF_INFO	34
++#define EVENT_LOG_TAG_MPF_DEBUG	35
++#define EVENT_LOG_TAG_EVENT_INFO	36
++#define EVENT_LOG_TAG_EVENT_ERR	37
++#define EVENT_LOG_TAG_PWRSTATS_ERROR	38
++#define EVENT_LOG_TAG_EXCESS_PM_ERROR	39
++#define EVENT_LOG_TAG_IOCTL_LOG			40
++#define EVENT_LOG_TAG_PFN_ERR	41
++#define EVENT_LOG_TAG_PFN_WARN	42
++#define EVENT_LOG_TAG_PFN_INFO	43
++#define EVENT_LOG_TAG_PFN_DEBUG	44
++#define EVENT_LOG_TAG_BEACON_LOG	45
++#define EVENT_LOG_TAG_WNM_BSSTRANS_INFO 46
++#define EVENT_LOG_TAG_TRACE_CHANSW 47
++#define EVENT_LOG_TAG_PCI_ERROR	48
++#define EVENT_LOG_TAG_PCI_TRACE	49
++#define EVENT_LOG_TAG_PCI_WARN	50
++#define EVENT_LOG_TAG_PCI_INFO	51
++#define EVENT_LOG_TAG_PCI_DBG	52
++#define EVENT_LOG_TAG_PCI_DATA  53
++#define EVENT_LOG_TAG_PCI_RING	54
++/* EVENT_LOG_TAG_AWDL_TRACE_RANGING will be removed after wlc_ranging merge from IGUANA
++ * keeping it here to avoid compilation error on trunk
++ */
++#define EVENT_LOG_TAG_AWDL_TRACE_RANGING	55
++#define EVENT_LOG_TAG_RANGING_TRACE	55
++#define EVENT_LOG_TAG_WL_ERROR		56
++#define EVENT_LOG_TAG_PHY_ERROR		57
++#define EVENT_LOG_TAG_OTP_ERROR		58
++#define EVENT_LOG_TAG_NOTIF_ERROR	59
++#define EVENT_LOG_TAG_MPOOL_ERROR	60
++#define EVENT_LOG_TAG_OBJR_ERROR	61
++#define EVENT_LOG_TAG_DMA_ERROR		62
++#define EVENT_LOG_TAG_PMU_ERROR		63
++#define EVENT_LOG_TAG_BSROM_ERROR	64
++#define EVENT_LOG_TAG_SI_ERROR		65
++#define EVENT_LOG_TAG_ROM_PRINTF	66
++#define EVENT_LOG_TAG_RATE_CNT		67
++#define EVENT_LOG_TAG_CTL_MGT_CNT	68
++#define EVENT_LOG_TAG_AMPDU_DUMP	69
++#define EVENT_LOG_TAG_MEM_ALLOC_SUCC	70
++#define EVENT_LOG_TAG_MEM_ALLOC_FAIL	71
++#define EVENT_LOG_TAG_MEM_FREE		72
++#define EVENT_LOG_TAG_WL_ASSOC_LOG	73
++#define EVENT_LOG_TAG_WL_PS_LOG		74
++#define EVENT_LOG_TAG_WL_ROAM_LOG	75
++#define EVENT_LOG_TAG_WL_MPC_LOG	76
++#define EVENT_LOG_TAG_WL_WSEC_LOG	77
++#define EVENT_LOG_TAG_WL_WSEC_DUMP	78
++#define EVENT_LOG_TAG_WL_MCNX_LOG	79
++#define EVENT_LOG_TAG_HEALTH_CHECK_ERROR 80
++#define EVENT_LOG_TAG_HNDRTE_EVENT_ERROR 81
++#define EVENT_LOG_TAG_ECOUNTERS_ERROR	82
++#define EVENT_LOG_TAG_WL_COUNTERS	83
++#define EVENT_LOG_TAG_ECOUNTERS_IPCSTATS	84
++#define EVENT_LOG_TAG_WL_P2P_LOG            85
++#define EVENT_LOG_TAG_SDIO_ERROR		86
++#define EVENT_LOG_TAG_SDIO_TRACE		87
++#define EVENT_LOG_TAG_SDIO_DBG          88
++#define EVENT_LOG_TAG_SDIO_PRHDRS		89
++#define EVENT_LOG_TAG_SDIO_PRPKT		90
++#define EVENT_LOG_TAG_SDIO_INFORM		91
++#define EVENT_LOG_TAG_MIMO_PS_ERROR	92
++#define EVENT_LOG_TAG_MIMO_PS_TRACE	93
++#define EVENT_LOG_TAG_MIMO_PS_INFO	94
++#define EVENT_LOG_TAG_BTCX_STATS	95
++#define EVENT_LOG_TAG_LEAKY_AP_STATS	96
++#define EVENT_LOG_TAG_AWDL_TRACE_ELECTION	97
++#define EVENT_LOG_TAG_MIMO_PS_STATS	98
++#define EVENT_LOG_TAG_PWRSTATS_PHY	99
++#define EVENT_LOG_TAG_PWRSTATS_SCAN	100
++#define EVENT_LOG_TAG_PWRSTATS_AWDL	101
++#define EVENT_LOG_TAG_PWRSTATS_WAKE_V2	102
++#define EVENT_LOG_TAG_LQM		103
++#define EVENT_LOG_TAG_TRACE_WL_INFO	104
++#define EVENT_LOG_TAG_TRACE_BTCOEX_INFO	105
++#define EVENT_LOG_TAG_ECOUNTERS_TIME_DATA	106
++#define EVENT_LOG_TAG_NAN_ERROR		107
++#define EVENT_LOG_TAG_NAN_INFO		108
++#define EVENT_LOG_TAG_NAN_DBG		109
++#define EVENT_LOG_TAG_STF_ARBITRATOR_ERROR	110
++#define EVENT_LOG_TAG_STF_ARBITRATOR_TRACE	111
++#define EVENT_LOG_TAG_STF_ARBITRATOR_WARN	112
++#define EVENT_LOG_TAG_SCAN_SUMMARY		113
++#define EVENT_LOG_TAG_PROXD_SAMPLE_COLLECT	114
++#define EVENT_LOG_TAG_OCL_INFO			115
++#define EVENT_LOG_TAG_RSDB_PMGR_DEBUG		116
++#define EVENT_LOG_TAG_RSDB_PMGR_ERR		117
++#define EVENT_LOG_TAG_NAT_ERR                   118
++#define EVENT_LOG_TAG_NAT_WARN                  119
++#define EVENT_LOG_TAG_NAT_INFO                  120
++#define EVENT_LOG_TAG_NAT_DEBUG                 121
++#define EVENT_LOG_TAG_STA_INFO			122
++#define EVENT_LOG_TAG_PROXD_ERROR		123
++#define EVENT_LOG_TAG_PROXD_TRACE		124
++#define EVENT_LOG_TAG_PROXD_INFO		125
++#define EVENT_LOG_TAG_IE_ERROR			126
++#define EVENT_LOG_TAG_ASSOC_ERROR		127
++#define EVENT_LOG_TAG_SCAN_ERR			128
++#define EVENT_LOG_TAG_AMSDU_ERROR		129
++#define EVENT_LOG_TAG_AMPDU_ERROR		130
++#define EVENT_LOG_TAG_KM_ERROR			131
++#define EVENT_LOG_TAG_DFS			132
++#define EVENT_LOG_TAG_REGULATORY		133
++#define EVENT_LOG_TAG_CSA			134
++#define EVENT_LOG_TAG_WNM_BSSTRANS_ERR		135
++#define EVENT_LOG_TAG_SUP_INFO			136
++#define EVENT_LOG_TAG_SUP_ERROR			137
++#define EVENT_LOG_TAG_CHANCTXT_TRACE		138
++#define EVENT_LOG_TAG_CHANCTXT_INFO		139
++#define EVENT_LOG_TAG_CHANCTXT_ERROR		140
++#define EVENT_LOG_TAG_CHANCTXT_WARN		141
++#define EVENT_LOG_TAG_MSCHPROFILE		142
++#define EVENT_LOG_TAG_4WAYHANDSHAKE		143
++#define EVENT_LOG_TAG_MSCHPROFILE_TLV		144
++#define EVENT_LOG_TAG_ADPS			145
++#define EVENT_LOG_TAG_MBO_DBG			146
++#define EVENT_LOG_TAG_MBO_INFO			147
++#define EVENT_LOG_TAG_MBO_ERR			148
++#define EVENT_LOG_TAG_TXDELAY			149
++#define EVENT_LOG_TAG_BCNTRIM_INFO		150
++#define EVENT_LOG_TAG_BCNTRIM_TRACE		151
++#define EVENT_LOG_TAG_OPS_INFO			152
++#define EVENT_LOG_TAG_STATS			153
++#define EVENT_LOG_TAG_BAM			154
++#define EVENT_LOG_TAG_TXFAIL			155
++#define EVENT_LOG_TAG_AWDL_CONFIG_DBG		156
++#define EVENT_LOG_TAG_AWDL_SYNC_DBG		157
++#define EVENT_LOG_TAG_AWDL_PEER_DBG		158
++#define EVENT_LOG_TAG_RANDMAC_INFO		159
++#define EVENT_LOG_TAG_RANDMAC_DBG		160
++#define EVENT_LOG_TAG_RANDMAC_ERR		161
++#define EVENT_LOG_TAG_AWDL_DFSP_DBG		162
++#define EVENT_LOG_TAG_TPA_ERR			163
++#define EVENT_LOG_TAG_TPA_INFO			164
++
++/* EVENT_LOG_TAG_MAX	= Set to the same value of last tag, not last tag + 1 */
++#define EVENT_LOG_TAG_MAX			164
++/* Note: New event should be added/reserved in trunk before adding it to branches */
++
++
++#define	SD_PRHDRS(i, s, h, p, n, l)
++#define	SD_PRPKT(m, b, n)
++#define	SD_INFORM(args)
++
++/* Flags for tag control */
++#define EVENT_LOG_TAG_FLAG_NONE		0
++#define EVENT_LOG_TAG_FLAG_LOG		0x80
++#define EVENT_LOG_TAG_FLAG_PRINT	0x40
++#define EVENT_LOG_TAG_FLAG_SET_MASK	0x3f
++
++/* Each event log entry has a type.  The type is the LAST word of the
++ * event log.  The printing code walks the event entries in reverse
++ * order to find the first entry.
++ */
++typedef union event_log_hdr {
++	struct {
++		uint8 tag;		/* Event_log entry tag */
++		uint8 count;		/* Count of 4-byte entries */
++		uint16 fmt_num;		/* Format number */
++	};
++	uint32 t;			/* Type cheat */
++} event_log_hdr_t;
++
++#endif /* _EVENT_LOG_TAG_H_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/event_trace.h b/module_drivers/drivers/net/wireless/bcmdhd/include/event_trace.h
+new file mode 100644
+index 000000000..cd24bdf28
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/event_trace.h
+@@ -0,0 +1,123 @@
++/*
++ * Trace log blocks sent over HBUS
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: event_trace.h 645268 2016-06-23 08:39:17Z $
++ */
++
++/**
++ * @file
++ * @brief
++ * Define the trace event ID and tag ID
++ */
++
++#ifndef	_WL_DIAG_H
++#define	_WL_DIAG_H
++
++#define DIAG_MAJOR_VERSION      1	/* 4 bits */
++#define DIAG_MINOR_VERSION      0	/* 4 bits */
++#define DIAG_MICRO_VERSION      0	/* 4 bits */
++
++#define DIAG_VERSION		\
++	((DIAG_MICRO_VERSION&0xF) | (DIAG_MINOR_VERSION&0xF)<<4 | \
++	(DIAG_MAJOR_VERSION&0xF)<<8)
++					/* bit[11:8] major ver */
++					/* bit[7:4] minor ver */
++					/* bit[3:0] micro ver */
++
++/* event ID for trace purpose only, to avoid the conflict with future new
++* WLC_E_ , starting from 0x8000
++*/
++#define TRACE_FW_AUTH_STARTED			0x8000
++#define TRACE_FW_ASSOC_STARTED			0x8001
++#define TRACE_FW_RE_ASSOC_STARTED		0x8002
++#define TRACE_G_SCAN_STARTED			0x8003
++#define TRACE_ROAM_SCAN_STARTED			0x8004
++#define TRACE_ROAM_SCAN_COMPLETE		0x8005
++#define TRACE_FW_EAPOL_FRAME_TRANSMIT_START	0x8006
++#define TRACE_FW_EAPOL_FRAME_TRANSMIT_STOP	0x8007
++#define TRACE_BLOCK_ACK_NEGOTIATION_COMPLETE	0x8008	/* protocol status */
++#define TRACE_BT_COEX_BT_SCO_START		0x8009
++#define TRACE_BT_COEX_BT_SCO_STOP		0x800a
++#define TRACE_BT_COEX_BT_SCAN_START		0x800b
++#define TRACE_BT_COEX_BT_SCAN_STOP		0x800c
++#define TRACE_BT_COEX_BT_HID_START		0x800d
++#define TRACE_BT_COEX_BT_HID_STOP		0x800e
++#define TRACE_ROAM_AUTH_STARTED			0x800f
++/* Event ID for NAN, start from 0x9000 */
++#define TRACE_NAN_CLUSTER_STARTED               0x9000
++#define TRACE_NAN_CLUSTER_JOINED                0x9001
++#define TRACE_NAN_CLUSTER_MERGED                0x9002
++#define TRACE_NAN_ROLE_CHANGED                  0x9003
++#define TRACE_NAN_SCAN_COMPLETE                 0x9004
++#define TRACE_NAN_STATUS_CHNG                   0x9005
++
++/* Parameters of wifi logger events are TLVs */
++/* Event parameters tags are defined as: */
++#define TRACE_TAG_VENDOR_SPECIFIC	0 /* take a byte stream as parameter */
++#define TRACE_TAG_BSSID			1 /* takes a 6 bytes MAC address as parameter */
++#define TRACE_TAG_ADDR			2 /* takes a 6 bytes MAC address as parameter */
++#define TRACE_TAG_SSID			3 /* takes a 32 bytes SSID address as parameter */
++#define TRACE_TAG_STATUS		4 /* takes an integer as parameter */
++#define TRACE_TAG_CHANNEL_SPEC		5 /* takes one or more wifi_channel_spec as */
++					  /* parameter */
++#define TRACE_TAG_WAKE_LOCK_EVENT	6 /* takes a wake_lock_event struct as parameter */
++#define TRACE_TAG_ADDR1			7 /* takes a 6 bytes MAC address as parameter */
++#define TRACE_TAG_ADDR2			8 /* takes a 6 bytes MAC address as parameter */
++#define TRACE_TAG_ADDR3			9 /* takes a 6 bytes MAC address as parameter */
++#define TRACE_TAG_ADDR4			10 /* takes a 6 bytes MAC address as parameter */
++#define TRACE_TAG_TSF			11 /* take a 64 bits TSF value as parameter */
++#define TRACE_TAG_IE			12 /* take one or more specific 802.11 IEs */
++					   /* parameter, IEs are in turn indicated in */
++					   /* TLV format as per 802.11 spec */
++#define TRACE_TAG_INTERFACE		13 /* take interface name as parameter */
++#define TRACE_TAG_REASON_CODE		14 /* take a reason code as per 802.11 */
++					   /* as parameter */
++#define TRACE_TAG_RATE_MBPS		15 /* take a wifi rate in 0.5 mbps */
++#define TRACE_TAG_REQUEST_ID		16 /* take an integer as parameter */
++#define TRACE_TAG_BUCKET_ID		17 /* take an integer as parameter */
++#define TRACE_TAG_GSCAN_PARAMS		18 /* takes a wifi_scan_cmd_params struct as parameter */
++#define TRACE_TAG_GSCAN_CAPABILITIES	19 /* takes a wifi_gscan_capabilities struct as parameter */
++#define TRACE_TAG_SCAN_ID		20 /* take an integer as parameter */
++#define TRACE_TAG_RSSI			21 /* take an integer as parameter */
++#define TRACE_TAG_CHANNEL		22 /* take an integer as parameter */
++#define TRACE_TAG_LINK_ID		23 /* take an integer as parameter */
++#define TRACE_TAG_LINK_ROLE		24 /* take an integer as parameter */
++#define TRACE_TAG_LINK_STATE		25 /* take an integer as parameter */
++#define TRACE_TAG_LINK_TYPE		26 /* take an integer as parameter */
++#define TRACE_TAG_TSCO			27 /* take an integer as parameter */
++#define TRACE_TAG_RSCO			28 /* take an integer as parameter */
++#define TRACE_TAG_EAPOL_MESSAGE_TYPE	29 /* take an integer as parameter */
++					   /* M1-1, M2-2, M3-3, M4-4 */
++
++typedef union {
++	struct {
++		uint16 event:	16;
++		uint16 version:	16;
++	};
++	uint32 t;
++} wl_event_log_id_ver_t;
++
++#endif	/* _WL_DIAG_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/hnd_armtrap.h b/module_drivers/drivers/net/wireless/bcmdhd/include/hnd_armtrap.h
+new file mode 100644
+index 000000000..e7c005c6f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/hnd_armtrap.h
+@@ -0,0 +1,90 @@
++/*
++ * HND arm trap handling.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: hnd_armtrap.h 545867 2015-04-01 22:45:19Z $
++ */
++
++#ifndef	_hnd_armtrap_h_
++#define	_hnd_armtrap_h_
++
++
++/* ARM trap handling */
++
++/* Trap types defined by ARM (see arminc.h) */
++
++/* Trap locations in lo memory */
++#define	TRAP_STRIDE	4
++#define FIRST_TRAP	TR_RST
++#define LAST_TRAP	(TR_FIQ * TRAP_STRIDE)
++
++#if defined(__ARM_ARCH_7M__)
++#define	MAX_TRAP_TYPE	(TR_ISR + ARMCM3_NUMINTS)
++#endif	/* __ARM_ARCH_7M__ */
++
++/* The trap structure is defined here as offsets for assembly */
++#define	TR_TYPE		0x00
++#define	TR_EPC		0x04
++#define	TR_CPSR		0x08
++#define	TR_SPSR		0x0c
++#define	TR_REGS		0x10
++#define	TR_REG(n)	(TR_REGS + (n) * 4)
++#define	TR_SP		TR_REG(13)
++#define	TR_LR		TR_REG(14)
++#define	TR_PC		TR_REG(15)
++
++#define	TRAP_T_SIZE	80
++#define ASSERT_TRAP_SVC_NUMBER	255
++
++#ifndef	_LANGUAGE_ASSEMBLY
++
++#include <typedefs.h>
++
++typedef struct _trap_struct {
++	uint32		type;
++	uint32		epc;
++	uint32		cpsr;
++	uint32		spsr;
++	uint32		r0;	/* a1 */
++	uint32		r1;	/* a2 */
++	uint32		r2;	/* a3 */
++	uint32		r3;	/* a4 */
++	uint32		r4;	/* v1 */
++	uint32		r5;	/* v2 */
++	uint32		r6;	/* v3 */
++	uint32		r7;	/* v4 */
++	uint32		r8;	/* v5 */
++	uint32		r9;	/* sb/v6 */
++	uint32		r10;	/* sl/v7 */
++	uint32		r11;	/* fp/v8 */
++	uint32		r12;	/* ip */
++	uint32		r13;	/* sp */
++	uint32		r14;	/* lr */
++	uint32		pc;	/* r15 */
++} trap_t;
++
++#endif	/* !_LANGUAGE_ASSEMBLY */
++
++#endif	/* _hnd_armtrap_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/hnd_cons.h b/module_drivers/drivers/net/wireless/bcmdhd/include/hnd_cons.h
+new file mode 100644
+index 000000000..3470d6a91
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/hnd_cons.h
+@@ -0,0 +1,84 @@
++/*
++ * Console support for RTE - for host use only.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: hnd_cons.h 568961 2015-07-06 18:14:49Z $
++ */
++#ifndef	_hnd_cons_h_
++#define	_hnd_cons_h_
++
++#include <typedefs.h>
++#include <siutils.h>
++
++#define CBUF_LEN	(128)
++
++#if defined(BCM_BIG_LOG)
++#define LOG_BUF_LEN	(16 * 1024)
++#else
++#define LOG_BUF_LEN	1024
++#endif
++
++#ifdef BOOTLOADER_CONSOLE_OUTPUT
++#undef RWL_MAX_DATA_LEN
++#undef CBUF_LEN
++#undef LOG_BUF_LEN
++#define RWL_MAX_DATA_LEN (4 * 1024 + 8)
++#define CBUF_LEN	(RWL_MAX_DATA_LEN + 64)
++#define LOG_BUF_LEN (16 * 1024)
++#endif
++
++typedef struct {
++	uint32		buf;		/* Can't be pointer on (64-bit) hosts */
++	uint		buf_size;
++	uint		idx;
++	uint		out_idx;	/* output index */
++} hnd_log_t;
++
++typedef struct {
++	/* Virtual UART
++	 *   When there is no UART (e.g. Quickturn), the host should write a complete
++	 *   input line directly into cbuf and then write the length into vcons_in.
++	 *   This may also be used when there is a real UART (at risk of conflicting with
++	 *   the real UART).  vcons_out is currently unused.
++	 */
++	volatile uint	vcons_in;
++	volatile uint	vcons_out;
++
++	/* Output (logging) buffer
++	 *   Console output is written to a ring buffer log_buf at index log_idx.
++	 *   The host may read the output when it sees log_idx advance.
++	 *   Output will be lost if the output wraps around faster than the host polls.
++	 */
++	hnd_log_t	log;
++
++	/* Console input line buffer
++	 *   Characters are read one at a time into cbuf until <CR> is received, then
++	 *   the buffer is processed as a command line.  Also used for virtual UART.
++	 */
++	uint		cbuf_idx;
++	char		cbuf[CBUF_LEN];
++} hnd_cons_t;
++
++#endif /* _hnd_cons_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/hnd_debug.h b/module_drivers/drivers/net/wireless/bcmdhd/include/hnd_debug.h
+new file mode 100644
+index 000000000..239e596e9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/hnd_debug.h
+@@ -0,0 +1,206 @@
++/*
++ * HND Run Time Environment debug info area
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: hnd_debug.h 678890 2017-01-11 11:48:36Z $
++ */
++
++#ifndef	_HND_DEBUG_H
++#define	_HND_DEBUG_H
++
++/* Magic number at a magic location to find HND_DEBUG pointers */
++#define HND_DEBUG_PTR_PTR_MAGIC 0x50504244  	/* DBPP */
++
++/* Magic number at a magic location to find RAM size */
++#define HND_RAMSIZE_PTR_MAGIC	0x534d4152	/* RAMS */
++
++#ifndef _LANGUAGE_ASSEMBLY
++
++/* Includes only when building dongle code */
++
++
++/* We use explicit sizes here since this gets included from different
++ * systems.  The sizes must be the size of the creating system
++ * (currently 32 bit ARM) since this is gleaned from  dump.
++ */
++
++#ifdef FWID
++extern uint32 gFWID;
++#endif
++
++/* Define pointers for use on other systems */
++#define _HD_EVLOG_P	uint32
++#define _HD_CONS_P	uint32
++#define _HD_TRAP_P	uint32
++
++/* This struct is placed at a well-defined location, and contains a pointer to hnd_debug. */
++typedef struct hnd_debug_ptr {
++	uint32	magic;
++
++	/* RAM address of 'hnd_debug'. For legacy versions of this struct, it is a 0-indexed
++	 * offset instead.
++	 */
++	uint32	hnd_debug_addr;
++
++	/* Base address of RAM. This field does not exist for legacy versions of this struct.  */
++	uint32	ram_base_addr;
++
++} hnd_debug_ptr_t;
++
++/* This struct is placed at a well-defined location. */
++typedef struct hnd_ramsize_ptr {
++	uint32	magic;			/* 'RAMS' */
++
++	/* RAM size information. */
++	uint32	ram_size;
++} hnd_ramsize_ptr_t;
++
++#define  HND_DEBUG_EPIVERS_MAX_STR_LEN	32
++#define  HND_DEBUG_BUILD_SIGNATURE_FWID_LEN	17
++#define  HND_DEBUG_BUILD_SIGNATURE_VER_LEN	22
++typedef struct hnd_debug {
++	uint32	magic;
++#define HND_DEBUG_MAGIC 0x47424544	/* 'DEBG' */
++
++	uint32	version;		/* Debug struct version */
++#define HND_DEBUG_VERSION 1
++
++	uint32	fwid;			/* 4 bytes of fw info */
++	char	epivers[HND_DEBUG_EPIVERS_MAX_STR_LEN];
++
++	_HD_TRAP_P trap_ptr;		/* trap_t data struct */
++	_HD_CONS_P console;		/* Console  */
++
++	uint32	ram_base;
++	uint32	ram_size;
++
++	uint32	rom_base;
++	uint32	rom_size;
++
++	_HD_EVLOG_P event_log_top;
++
++	/* To populated fields below,
++	 * INCLUDE_BUILD_SIGNATURE_IN_SOCRAM needs to be enabled
++	 */
++	char fwid_signature[HND_DEBUG_BUILD_SIGNATURE_FWID_LEN]; /* fwid=<FWID> */
++	char ver_signature[HND_DEBUG_BUILD_SIGNATURE_VER_LEN]; /* ver=abc.abc.abc.abc */
++
++} hnd_debug_t;
++
++/*
++ * timeval_t and prstatus_t are copies of the Linux structures.
++ * Included here because we need the definitions for the target processor
++ * (32 bits) and not the definition on the host this is running on
++ * (which could be 64 bits).
++ */
++
++typedef struct             {    /* Time value with microsecond resolution    */
++	uint32 tv_sec;	/* Seconds                                   */
++	uint32 tv_usec;	/* Microseconds                              */
++} timeval_t;
++
++
++/* Linux/ARM 32 prstatus for notes section */
++typedef struct prstatus {
++	  int32 si_signo; 	/* Signal number */
++	  int32 si_code; 	/* Extra code */
++	  int32 si_errno; 	/* Errno */
++	  uint16 pr_cursig; 	/* Current signal.  */
++	  uint16 unused;
++	  uint32 pr_sigpend;	/* Set of pending signals.  */
++	  uint32 pr_sighold;	/* Set of held signals.  */
++	  uint32 pr_pid;
++	  uint32 pr_ppid;
++	  uint32 pr_pgrp;
++	  uint32 pr_sid;
++	  timeval_t pr_utime;	/* User time.  */
++	  timeval_t pr_stime;	/* System time.  */
++	  timeval_t pr_cutime;	/* Cumulative user time.  */
++	  timeval_t pr_cstime;	/* Cumulative system time.  */
++	  uint32 uregs[18];
++	  int32 pr_fpvalid;	/* True if math copro being used.  */
++} prstatus_t;
++
++/* for mkcore and other utilities use */
++#define DUMP_INFO_PTR_PTR_0   0x74
++#define DUMP_INFO_PTR_PTR_1   0x78
++#define DUMP_INFO_PTR_PTR_2   0xf0
++#define DUMP_INFO_PTR_PTR_3   0xf8
++#define DUMP_INFO_PTR_PTR_4   0x874
++#define DUMP_INFO_PTR_PTR_5   0x878
++#define DUMP_INFO_PTR_PTR_END 0xffffffff
++#define DUMP_INFO_PTR_PTR_LIST	DUMP_INFO_PTR_PTR_0, \
++		DUMP_INFO_PTR_PTR_1,					\
++		DUMP_INFO_PTR_PTR_2,					\
++		DUMP_INFO_PTR_PTR_3,					\
++		DUMP_INFO_PTR_PTR_4,					\
++		DUMP_INFO_PTR_PTR_5,					\
++		DUMP_INFO_PTR_PTR_END
++
++/* for DHD driver to get dongle ram size info. */
++#define RAMSIZE_PTR_PTR_0	0x6c
++#define RAMSIZE_PTR_PTR_END	0xffffffff
++#define RAMSIZE_PTR_PTR_LIST	RAMSIZE_PTR_PTR_0, \
++				RAMSIZE_PTR_PTR_END
++
++typedef struct hnd_ext_trap_hdr {
++	uint8 version;    /* Extended trap version info */
++	uint8 reserved;   /* currently unused */
++	uint16 len;       /* Length of data excluding this header */
++	uint8 data[];     /* TLV data */
++} hnd_ext_trap_hdr_t;
++
++#define TAG_TRAP_SIGNATURE       1  /* Processor register dumps */
++#define TAG_TRAP_STACK           2  /* Processor stack dump (possible code locations) */
++#define TAG_TRAP_MEMORY          3  /* Memory subsystem dump */
++#define TAG_TRAP_DEEPSLEEP       4  /* Deep sleep health check failures */
++#define TAG_TRAP_PSM_WD          5  /* PSM watchdog information */
++#define TAG_TRAP_PHY             6  /* Phy related issues */
++#define TAG_TRAP_BUS             7  /* Bus level issues */
++#define TAG_TRAP_MAC             8  /* Mac level issues */
++#define TAG_TRAP_BACKPLANE       9  /* Backplane related errors */
++
++typedef struct hnd_ext_trap_bp_err
++{
++	uint32 error;
++	uint32 coreid;
++	uint32 baseaddr;
++	uint32 ioctrl;
++	uint32 iostatus;
++	uint32 resetctrl;
++	uint32 resetstatus;
++	uint32 errlogctrl;
++	uint32 errlogdone;
++	uint32 errlogstatus;
++	uint32 errlogaddrlo;
++	uint32 errlogaddrhi;
++	uint32 errlogid;
++	uint32 errloguser;
++	uint32 errlogflags;
++} hnd_ext_trap_bp_err_t;
++
++#endif /* !LANGUAGE_ASSEMBLY */
++
++#endif /* _HND_DEBUG_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/hnd_pktpool.h b/module_drivers/drivers/net/wireless/bcmdhd/include/hnd_pktpool.h
+new file mode 100644
+index 000000000..e5d0eaa65
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/hnd_pktpool.h
+@@ -0,0 +1,225 @@
++/*
++ * HND generic packet pool operation primitives
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: hnd_pktpool.h 613891 2016-01-20 10:05:44Z $
++ */
++
++#ifndef _hnd_pktpool_h_
++#define _hnd_pktpool_h_
++
++#include <osl_ext.h>
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* mutex macros for thread safe */
++#ifdef HND_PKTPOOL_THREAD_SAFE
++#define HND_PKTPOOL_MUTEX_DECL(mutex)		OSL_EXT_MUTEX_DECL(mutex)
++#else
++#define HND_PKTPOOL_MUTEX_DECL(mutex)
++#endif
++
++#ifdef BCMPKTPOOL
++#define POOL_ENAB(pool)		((pool) && (pool)->inited)
++#else /* BCMPKTPOOL */
++#define POOL_ENAB(bus)		0
++#endif /* BCMPKTPOOL */
++
++#ifndef PKTPOOL_LEN_MAX
++#define PKTPOOL_LEN_MAX		40
++#endif /* PKTPOOL_LEN_MAX */
++#define PKTPOOL_CB_MAX		3
++#define PKTPOOL_CB_MAX_AVL	4
++
++
++/* forward declaration */
++struct pktpool;
++
++typedef void (*pktpool_cb_t)(struct pktpool *pool, void *arg);
++typedef struct {
++	pktpool_cb_t cb;
++	void *arg;
++} pktpool_cbinfo_t;
++
++/** PCIe SPLITRX related: call back fn extension to populate host address in pool pkt */
++typedef int (*pktpool_cb_extn_t)(struct pktpool *pool, void *arg1, void* pkt, bool arg2);
++typedef struct {
++	pktpool_cb_extn_t cb;
++	void *arg;
++} pktpool_cbextn_info_t;
++
++
++#ifdef BCMDBG_POOL
++/* pkt pool debug states */
++#define POOL_IDLE	0
++#define POOL_RXFILL	1
++#define POOL_RXDH	2
++#define POOL_RXD11	3
++#define POOL_TXDH	4
++#define POOL_TXD11	5
++#define POOL_AMPDU	6
++#define POOL_TXENQ	7
++
++typedef struct {
++	void *p;
++	uint32 cycles;
++	uint32 dur;
++} pktpool_dbg_t;
++
++typedef struct {
++	uint8 txdh;	/* tx to host */
++	uint8 txd11;	/* tx to d11 */
++	uint8 enq;	/* waiting in q */
++	uint8 rxdh;	/* rx from host */
++	uint8 rxd11;	/* rx from d11 */
++	uint8 rxfill;	/* dma_rxfill */
++	uint8 idle;	/* avail in pool */
++} pktpool_stats_t;
++#endif /* BCMDBG_POOL */
++
++typedef struct pktpool {
++	bool inited;            /**< pktpool_init was successful */
++	uint8 type;             /**< type of lbuf: basic, frag, etc */
++	uint8 id;               /**< pktpool ID:  index in registry */
++	bool istx;              /**< direction: transmit or receive data path */
++	HND_PKTPOOL_MUTEX_DECL(mutex)	/**< thread-safe mutex */
++
++	void * freelist;        /**< free list: see PKTNEXTFREE(), PKTSETNEXTFREE() */
++	uint16 avail;           /**< number of packets in pool's free list */
++	uint16 len;             /**< number of packets managed by pool */
++	uint16 maxlen;          /**< maximum size of pool <= PKTPOOL_LEN_MAX */
++	uint16 plen;            /**< size of pkt buffer in [bytes], excluding lbuf|lbuf_frag */
++
++	bool empty;
++	uint8 cbtoggle;
++	uint8 cbcnt;
++	uint8 ecbcnt;
++	uint8 emptycb_disable;	/**< Value of type enum pktpool_empty_cb_state */
++	pktpool_cbinfo_t *availcb_excl;
++	pktpool_cbinfo_t cbs[PKTPOOL_CB_MAX_AVL];
++	pktpool_cbinfo_t ecbs[PKTPOOL_CB_MAX];
++	pktpool_cbextn_info_t cbext;	/**< PCIe SPLITRX related */
++	pktpool_cbextn_info_t rxcplidfn;
++#ifdef BCMDBG_POOL
++	uint8 dbg_cbcnt;
++	pktpool_cbinfo_t dbg_cbs[PKTPOOL_CB_MAX];
++	uint16 dbg_qlen;
++	pktpool_dbg_t dbg_q[PKTPOOL_LEN_MAX + 1];
++#endif
++	pktpool_cbinfo_t dmarxfill;
++} pktpool_t;
++
++
++pktpool_t *get_pktpools_registry(int id);
++
++/* Incarnate a pktpool registry. On success returns total_pools. */
++extern int pktpool_attach(osl_t *osh, uint32 total_pools);
++extern int pktpool_dettach(osl_t *osh); /* Relinquish registry */
++
++extern int pktpool_init(osl_t *osh, pktpool_t *pktp, int *pktplen, int plen, bool istx, uint8 type);
++extern int pktpool_deinit(osl_t *osh, pktpool_t *pktp);
++extern int pktpool_fill(osl_t *osh, pktpool_t *pktp, bool minimal);
++extern void* pktpool_get(pktpool_t *pktp);
++extern void pktpool_free(pktpool_t *pktp, void *p);
++extern int pktpool_add(pktpool_t *pktp, void *p);
++extern int pktpool_avail_notify_normal(osl_t *osh, pktpool_t *pktp);
++extern int pktpool_avail_notify_exclusive(osl_t *osh, pktpool_t *pktp, pktpool_cb_t cb);
++extern int pktpool_avail_register(pktpool_t *pktp, pktpool_cb_t cb, void *arg);
++extern int pktpool_empty_register(pktpool_t *pktp, pktpool_cb_t cb, void *arg);
++extern int pktpool_setmaxlen(pktpool_t *pktp, uint16 maxlen);
++extern int pktpool_setmaxlen_strict(osl_t *osh, pktpool_t *pktp, uint16 maxlen);
++extern void pktpool_emptycb_disable(pktpool_t *pktp, bool disable);
++extern bool pktpool_emptycb_disabled(pktpool_t *pktp);
++extern int pktpool_hostaddr_fill_register(pktpool_t *pktp, pktpool_cb_extn_t cb, void *arg1);
++extern int pktpool_rxcplid_fill_register(pktpool_t *pktp, pktpool_cb_extn_t cb, void *arg);
++extern void pktpool_invoke_dmarxfill(pktpool_t *pktp);
++extern int pkpool_haddr_avail_register_cb(pktpool_t *pktp, pktpool_cb_t cb, void *arg);
++
++#define POOLPTR(pp)         ((pktpool_t *)(pp))
++#define POOLID(pp)          (POOLPTR(pp)->id)
++
++#define POOLSETID(pp, ppid) (POOLPTR(pp)->id = (ppid))
++
++#define pktpool_len(pp)     (POOLPTR(pp)->len)   /**< returns packet length in [bytes] */
++#define pktpool_avail(pp)   (POOLPTR(pp)->avail)
++#define pktpool_plen(pp)    (POOLPTR(pp)->plen)
++#define pktpool_maxlen(pp)  (POOLPTR(pp)->maxlen)
++
++
++/*
++ * ----------------------------------------------------------------------------
++ * A pool ID is assigned with a pkt pool during pool initialization. This is
++ * done by maintaining a registry of all initialized pools, and the registry
++ * index at which the pool is registered is used as the pool's unique ID.
++ * ID 0 is reserved and is used to signify an invalid pool ID.
++ * All packets henceforth allocated from a pool will be tagged with the pool's
++ * unique ID. Packets allocated from the heap will use the reserved ID = 0.
++ * Packets with non-zero pool id signify that they were allocated from a pool.
++ * A maximum of 15 pools are supported, allowing a 4bit pool ID to be used
++ * in place of a 32bit pool pointer in each packet.
++ * ----------------------------------------------------------------------------
++ */
++#define PKTPOOL_INVALID_ID          (0)
++#define PKTPOOL_MAXIMUM_ID          (15)
++
++/* Registry of pktpool(s) */
++/* Pool ID to/from Pool Pointer converters */
++#define PKTPOOL_ID2PTR(id)          (get_pktpools_registry(id))
++#define PKTPOOL_PTR2ID(pp)          (POOLID(pp))
++
++#ifdef BCMDBG_POOL
++extern int pktpool_dbg_register(pktpool_t *pktp, pktpool_cb_t cb, void *arg);
++extern int pktpool_start_trigger(pktpool_t *pktp, void *p);
++extern int pktpool_dbg_dump(pktpool_t *pktp);
++extern int pktpool_dbg_notify(pktpool_t *pktp);
++extern int pktpool_stats_dump(pktpool_t *pktp, pktpool_stats_t *stats);
++#endif /* BCMDBG_POOL */
++
++#ifdef BCMPKTPOOL
++#define SHARED_POOL		(pktpool_shared)
++extern pktpool_t *pktpool_shared;
++#ifdef BCMFRAGPOOL
++#define SHARED_FRAG_POOL	(pktpool_shared_lfrag)
++extern pktpool_t *pktpool_shared_lfrag;
++#endif
++
++/** PCIe SPLITRX related */
++#define SHARED_RXFRAG_POOL	(pktpool_shared_rxlfrag)
++extern pktpool_t *pktpool_shared_rxlfrag;
++
++int hnd_pktpool_init(osl_t *osh);
++int hnd_pktpool_fill(pktpool_t *pktpool, bool minimal);
++void hnd_pktpool_refill(bool minimal);
++#else /* BCMPKTPOOL */
++#define SHARED_POOL		((struct pktpool *)NULL)
++#endif /* BCMPKTPOOL */
++
++#ifdef __cplusplus
++	}
++#endif
++
++#endif /* _hnd_pktpool_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/hnd_pktq.h b/module_drivers/drivers/net/wireless/bcmdhd/include/hnd_pktq.h
+new file mode 100644
+index 000000000..ad778da89
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/hnd_pktq.h
+@@ -0,0 +1,284 @@
++/*
++ * HND generic pktq operation primitives
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: hnd_pktq.h 641285 2016-06-02 02:33:55Z $
++ */
++
++#ifndef _hnd_pktq_h_
++#define _hnd_pktq_h_
++
++#include <osl_ext.h>
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* mutex macros for thread safe */
++#ifdef HND_PKTQ_THREAD_SAFE
++#define HND_PKTQ_MUTEX_DECL(mutex)		OSL_EXT_MUTEX_DECL(mutex)
++#else
++#define HND_PKTQ_MUTEX_DECL(mutex)
++#endif
++
++/* osl multi-precedence packet queue */
++#define PKTQ_LEN_MAX            0xFFFF  /* Max uint16 65535 packets */
++#ifndef PKTQ_LEN_DEFAULT
++#define PKTQ_LEN_DEFAULT        128	/* Max 128 packets */
++#endif
++#ifndef PKTQ_MAX_PREC
++#define PKTQ_MAX_PREC           16	/* Maximum precedence levels */
++#endif
++
++typedef struct pktq_prec {
++	void *head;     /**< first packet to dequeue */
++	void *tail;     /**< last packet to dequeue */
++	uint16 len;     /**< number of queued packets */
++	uint16 max;     /**< maximum number of queued packets */
++} pktq_prec_t;
++
++#ifdef PKTQ_LOG
++typedef struct {
++	uint32 requested;    /**< packets requested to be stored */
++	uint32 stored;	     /**< packets stored */
++	uint32 saved;	     /**< packets saved,
++	                            because a lowest priority queue has given away one packet
++	                      */
++	uint32 selfsaved;    /**< packets saved,
++	                            because an older packet from the same queue has been dropped
++	                      */
++	uint32 full_dropped; /**< packets dropped,
++	                            because pktq is full with higher precedence packets
++	                      */
++	uint32 dropped;      /**< packets dropped because pktq per that precedence is full */
++	uint32 sacrificed;   /**< packets dropped,
++	                            in order to save one from a queue of a highest priority
++	                      */
++	uint32 busy;         /**< packets droped because of hardware/transmission error */
++	uint32 retry;        /**< packets re-sent because they were not received */
++	uint32 ps_retry;     /**< packets retried again prior to moving power save mode */
++	uint32 suppress;     /**< packets which were suppressed and not transmitted */
++	uint32 retry_drop;   /**< packets finally dropped after retry limit */
++	uint32 max_avail;    /**< the high-water mark of the queue capacity for packets -
++	                            goes to zero as queue fills
++	                      */
++	uint32 max_used;     /**< the high-water mark of the queue utilisation for packets -
++						        increases with use ('inverse' of max_avail)
++				          */
++	uint32 queue_capacity; /**< the maximum capacity of the queue */
++	uint32 rtsfail;        /**< count of rts attempts that failed to receive cts */
++	uint32 acked;          /**< count of packets sent (acked) successfully */
++	uint32 txrate_succ;    /**< running total of phy rate of packets sent successfully */
++	uint32 txrate_main;    /**< running totoal of primary phy rate of all packets */
++	uint32 throughput;     /**< actual data transferred successfully */
++	uint32 airtime;        /**< cumulative total medium access delay in useconds */
++	uint32  _logtime;      /**< timestamp of last counter clear  */
++} pktq_counters_t;
++
++#define PKTQ_LOG_COMMON \
++	uint32			pps_time;	/**< time spent in ps pretend state */ \
++	uint32                  _prec_log;
++
++typedef struct {
++	PKTQ_LOG_COMMON
++	pktq_counters_t*        _prec_cnt[PKTQ_MAX_PREC];     /**< Counters per queue  */
++} pktq_log_t;
++#else
++typedef struct pktq_log pktq_log_t;
++#endif /* PKTQ_LOG */
++
++
++#define PKTQ_COMMON	\
++	HND_PKTQ_MUTEX_DECL(mutex)							\
++	pktq_log_t *pktqlog;								\
++	uint16 num_prec;        /**< number of precedences in use */			\
++	uint16 hi_prec;         /**< rapid dequeue hint (>= highest non-empty prec) */	\
++	uint16 max;             /**< total max packets */				\
++	uint16 len;             /**< total number of packets */
++
++/* multi-priority pkt queue */
++struct pktq {
++	PKTQ_COMMON
++	/* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */
++	struct pktq_prec q[PKTQ_MAX_PREC];
++};
++
++/* simple, non-priority pkt queue */
++struct spktq {
++	PKTQ_COMMON
++	/* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */
++	struct pktq_prec q[1];
++};
++
++#define PKTQ_PREC_ITER(pq, prec)        for (prec = (pq)->num_prec - 1; prec >= 0; prec--)
++
++/* fn(pkt, arg).  return true if pkt belongs to bsscfg */
++typedef bool (*ifpkt_cb_t)(void*, int);
++
++/*
++ * pktq filter support
++ */
++
++/* filter function return values */
++typedef enum {
++	PKT_FILTER_NOACTION = 0,    /**< restore the pkt to its position in the queue */
++	PKT_FILTER_DELETE = 1,      /**< delete the pkt */
++	PKT_FILTER_REMOVE = 2,      /**< do not restore the pkt to the queue,
++	                             *   filter fn has taken ownership of the pkt
++	                             */
++} pktq_filter_result_t;
++
++/**
++ * Caller supplied filter function to pktq_pfilter(), pktq_filter().
++ * Function filter(ctx, pkt) is called with its ctx pointer on each pkt in the
++ * pktq.  When the filter function is called, the supplied pkt will have been
++ * unlinked from the pktq.  The filter function returns a pktq_filter_result_t
++ * result specifying the action pktq_filter()/pktq_pfilter() should take for
++ * the pkt.
++ * Here are the actions taken by pktq_filter/pfilter() based on the supplied
++ * filter function's return value:
++ *
++ * PKT_FILTER_NOACTION - The filter will re-link the pkt at its
++ *     previous location.
++ *
++ * PKT_FILTER_DELETE - The filter will not relink the pkt and will
++ *     call the user supplied defer_free_pkt fn on the packet.
++ *
++ * PKT_FILTER_REMOVE - The filter will not relink the pkt. The supplied
++ *     filter fn took ownership (or deleted) the pkt.
++ *
++ * WARNING: pkts inserted by the user (in pkt_filter and/or flush callbacks
++ * and chains) in the prec queue will not be seen by the filter, and the prec
++ * queue will be temporarily be removed from the queue hence there're side
++ * effects including pktq_len() on the queue won't reflect the correct number
++ * of packets in the queue.
++ */
++typedef pktq_filter_result_t (*pktq_filter_t)(void* ctx, void* pkt);
++
++/* The defer_free_pkt callback is invoked when the the pktq_filter callback
++ * returns PKT_FILTER_DELETE decision, which allows the user to deposite
++ * the packet appropriately based on the situation (free the packet or
++ * save it in a temporary queue etc.).
++ */
++typedef void (*defer_free_pkt_fn_t)(void *ctx, void *pkt);
++
++/* The flush_free_pkt callback is invoked when all packets in the pktq
++ * are processed.
++ */
++typedef void (*flush_free_pkt_fn_t)(void *ctx);
++
++/* filter a pktq, using the caller supplied filter/deposition/flush functions */
++extern void  pktq_filter(struct pktq *pq, pktq_filter_t fn, void* arg,
++	defer_free_pkt_fn_t defer, void *defer_ctx, flush_free_pkt_fn_t flush, void *flush_ctx);
++/* filter a particular precedence in pktq, using the caller supplied filter function */
++extern void  pktq_pfilter(struct pktq *pq, int prec, pktq_filter_t fn, void* arg,
++	defer_free_pkt_fn_t defer, void *defer_ctx, flush_free_pkt_fn_t flush, void *flush_ctx);
++
++/* operations on a specific precedence in packet queue */
++
++#define pktq_psetmax(pq, prec, _max)	((pq)->q[prec].max = (_max))
++#define pktq_pmax(pq, prec)		((pq)->q[prec].max)
++#define pktq_plen(pq, prec)		((pq)->q[prec].len)
++#define pktq_pempty(pq, prec)		((pq)->q[prec].len == 0)
++#define pktq_ppeek(pq, prec)		((pq)->q[prec].head)
++#define pktq_ppeek_tail(pq, prec)	((pq)->q[prec].tail)
++#ifdef HND_PKTQ_THREAD_SAFE
++extern int pktq_pavail(struct pktq *pq, int prec);
++extern bool pktq_pfull(struct pktq *pq, int prec);
++#else
++#define pktq_pavail(pq, prec)	((pq)->q[prec].max - (pq)->q[prec].len)
++#define pktq_pfull(pq, prec)	((pq)->q[prec].len >= (pq)->q[prec].max)
++#endif	/* HND_PKTQ_THREAD_SAFE */
++
++extern void  pktq_append(struct pktq *pq, int prec, struct spktq *list);
++extern void  pktq_prepend(struct pktq *pq, int prec, struct spktq *list);
++
++extern void *pktq_penq(struct pktq *pq, int prec, void *p);
++extern void *pktq_penq_head(struct pktq *pq, int prec, void *p);
++extern void *pktq_pdeq(struct pktq *pq, int prec);
++extern void *pktq_pdeq_prev(struct pktq *pq, int prec, void *prev_p);
++extern void *pktq_pdeq_with_fn(struct pktq *pq, int prec, ifpkt_cb_t fn, int arg);
++extern void *pktq_pdeq_tail(struct pktq *pq, int prec);
++/* Remove a specified packet from its queue */
++extern bool pktq_pdel(struct pktq *pq, void *p, int prec);
++
++/* operations on a set of precedences in packet queue */
++
++extern int pktq_mlen(struct pktq *pq, uint prec_bmp);
++extern void *pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out);
++extern void *pktq_mpeek(struct pktq *pq, uint prec_bmp, int *prec_out);
++
++/* operations on packet queue as a whole */
++
++#define pktq_len(pq)		((int)(pq)->len)
++#define pktq_max(pq)		((int)(pq)->max)
++#define pktq_empty(pq)		((pq)->len == 0)
++#ifdef HND_PKTQ_THREAD_SAFE
++extern int pktq_avail(struct pktq *pq);
++extern bool pktq_full(struct pktq *pq);
++#else
++#define pktq_avail(pq)		((int)((pq)->max - (pq)->len))
++#define pktq_full(pq)		((pq)->len >= (pq)->max)
++#endif	/* HND_PKTQ_THREAD_SAFE */
++
++/* operations for single precedence queues */
++#define pktenq(pq, p)		pktq_penq(((struct pktq *)(void *)pq), 0, (p))
++#define pktenq_head(pq, p)	pktq_penq_head(((struct pktq *)(void *)pq), 0, (p))
++#define pktdeq(pq)		pktq_pdeq(((struct pktq *)(void *)pq), 0)
++#define pktdeq_tail(pq)		pktq_pdeq_tail(((struct pktq *)(void *)pq), 0)
++#define pktqflush(osh, pq, dir)	pktq_pflush(osh, ((struct pktq *)(void *)pq), 0, dir)
++#define pktqinit(pq, len)	pktq_init(((struct pktq *)(void *)pq), 1, len)
++#define pktqdeinit(pq)		pktq_deinit((struct pktq *)(void *)pq)
++#define pktqavail(pq)		pktq_avail((struct pktq *)(void *)pq)
++#define pktqfull(pq)		pktq_full((struct pktq *)(void *)pq)
++#define pktqfilter(pq, fltr, fltr_ctx, defer, defer_ctx, flush, flush_ctx) \
++	pktq_pfilter((struct pktq *)pq, 0, fltr, fltr_ctx, defer, defer_ctx, flush, flush_ctx)
++
++/* wrap macros for modules in components use */
++#define spktqinit(pq, max_pkts) pktqinit(pq, max_pkts)
++#define spktenq(pq, p)          pktenq(pq, p)
++#define spktdeq(pq)             pktdeq(pq)
++
++extern bool pktq_init(struct pktq *pq, int num_prec, int max_len);
++extern bool pktq_deinit(struct pktq *pq);
++
++extern void pktq_set_max_plen(struct pktq *pq, int prec, int max_len);
++
++/* prec_out may be NULL if caller is not interested in return value */
++extern void *pktq_deq(struct pktq *pq, int *prec_out);
++extern void *pktq_deq_tail(struct pktq *pq, int *prec_out);
++extern void *pktq_peek(struct pktq *pq, int *prec_out);
++extern void *pktq_peek_tail(struct pktq *pq, int *prec_out);
++
++/* flush pktq */
++extern void pktq_flush(osl_t *osh, struct pktq *pq, bool dir);
++/* Empty the queue at particular precedence level */
++extern void pktq_pflush(osl_t *osh, struct pktq *pq, int prec, bool dir);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _hnd_pktq_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/hndpmu.h b/module_drivers/drivers/net/wireless/bcmdhd/include/hndpmu.h
+new file mode 100644
+index 000000000..bfc916693
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/hndpmu.h
+@@ -0,0 +1,56 @@
++/*
++ * HND SiliconBackplane PMU support.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: hndpmu.h 657872 2016-09-02 22:17:34Z $
++ */
++
++#ifndef _hndpmu_h_
++#define _hndpmu_h_
++
++#include <typedefs.h>
++#include <osl_decl.h>
++#include <siutils.h>
++#include <sbchipc.h>
++
++
++extern void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on, uint32* min_res_mask);
++extern void si_sdiod_drive_strength_init(si_t *sih, osl_t *osh, uint32 drivestrength);
++
++extern void si_pmu_minresmask_htavail_set(si_t *sih, osl_t *osh, bool set_clear);
++extern void si_pmu_slow_clk_reinit(si_t *sih, osl_t *osh);
++extern void si_pmu_avbtimer_enable(si_t *sih, osl_t *osh, bool set_flag);
++extern uint32 si_pmu_dump_pmucap_binary(si_t *sih, uchar *p);
++extern uint32 si_pmu_dump_buf_size_pmucap(si_t *sih);
++extern int si_pmu_wait_for_steady_state(si_t *sih, osl_t *osh, pmuregs_t *pmu);
++#if defined(BCMULP)
++int si_pmu_ulp_register(si_t *sih);
++extern void si_pmu_ulp_ilp_config(si_t *sih, osl_t *osh, uint32 ilp_period);
++#endif /* BCMULP */
++extern uint32 si_pmu_get_pmutimer(si_t *sih);
++extern void si_pmu_set_min_res_mask(si_t *sih, osl_t *osh, uint min_res_mask);
++extern bool si_pmu_cap_fast_lpo(si_t *sih);
++extern int si_pmu_fast_lpo_disable(si_t *sih);
++#endif /* _hndpmu_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/hndsoc.h b/module_drivers/drivers/net/wireless/bcmdhd/include/hndsoc.h
+new file mode 100644
+index 000000000..b35380ad5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/hndsoc.h
+@@ -0,0 +1,327 @@
++/*
++ * Broadcom HND chip & on-chip-interconnect-related definitions.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: hndsoc.h 613129 2016-01-17 09:25:52Z $
++ */
++
++#ifndef	_HNDSOC_H
++#define	_HNDSOC_H
++
++/* Include the soci specific files */
++#include <sbconfig.h>
++#include <aidmp.h>
++
++/*
++ * SOC Interconnect Address Map.
++ * All regions may not exist on all chips.
++ */
++#define SI_SDRAM_BASE		0x00000000	/* Physical SDRAM */
++#define SI_PCI_MEM		0x08000000	/* Host Mode sb2pcitranslation0 (64 MB) */
++#define SI_PCI_MEM_SZ		(64 * 1024 * 1024)
++#define SI_PCI_CFG		0x0c000000	/* Host Mode sb2pcitranslation1 (64 MB) */
++#define	SI_SDRAM_SWAPPED	0x10000000	/* Byteswapped Physical SDRAM */
++#define SI_SDRAM_R2		0x80000000	/* Region 2 for sdram (512 MB) */
++
++#define SI_ENUM_BASE		0x18000000	/* Enumeration space base */
++#define SI_WRAP_BASE		0x18100000	/* Wrapper space base */
++#define SI_CORE_SIZE		0x1000		/* each core gets 4Kbytes for registers */
++
++#ifndef SI_MAXCORES
++#define	SI_MAXCORES		32		/* NorthStar has more cores */
++#endif /* SI_MAXCORES */
++
++#define	SI_MAXBR		4		/* Max bridges (this is arbitrary, for software
++					 * convenience and could be changed if we
++					 * make any larger chips
++					 */
++
++#define	SI_FASTRAM		0x19000000	/* On-chip RAM on chips that also have DDR */
++#define	SI_FASTRAM_SWAPPED	0x19800000
++
++#define	SI_FLASH2		0x1c000000	/* Flash Region 2 (region 1 shadowed here) */
++#define	SI_FLASH2_SZ		0x02000000	/* Size of Flash Region 2 */
++#define	SI_ARMCM3_ROM		0x1e000000	/* ARM Cortex-M3 ROM */
++#define	SI_FLASH1		0x1fc00000	/* MIPS Flash Region 1 */
++#define	SI_FLASH1_SZ		0x00400000	/* MIPS Size of Flash Region 1 */
++#define	SI_FLASH_WINDOW		0x01000000	/* Flash XIP Window */
++
++#define SI_NS_NANDFLASH		0x1c000000	/* NorthStar NAND flash base */
++#define SI_NS_NORFLASH		0x1e000000	/* NorthStar NOR flash base */
++#define SI_NS_ROM		0xfffd0000	/* NorthStar ROM */
++#define	SI_NS_FLASH_WINDOW	0x02000000	/* Flash XIP Window */
++
++#define	SI_ARM7S_ROM		0x20000000	/* ARM7TDMI-S ROM */
++#define	SI_ARMCR4_ROM		0x000f0000	/* ARM Cortex-R4 ROM */
++#define	SI_ARMCM3_SRAM2		0x60000000	/* ARM Cortex-M3 SRAM Region 2 */
++#define	SI_ARM7S_SRAM2		0x80000000	/* ARM7TDMI-S SRAM Region 2 */
++#define	SI_ARMCA7_ROM		0x00000000	/* ARM Cortex-A7 ROM */
++#define	SI_ARMCA7_RAM		0x00200000	/* ARM Cortex-A7 RAM */
++#define	SI_ARM_FLASH1		0xffff0000	/* ARM Flash Region 1 */
++#define	SI_ARM_FLASH1_SZ	0x00010000	/* ARM Size of Flash Region 1 */
++
++#define SI_SFLASH		0x14000000
++#define SI_PCI_DMA		0x40000000	/* Client Mode sb2pcitranslation2 (1 GB) */
++#define SI_PCI_DMA2		0x80000000	/* Client Mode sb2pcitranslation2 (1 GB) */
++#define SI_PCI_DMA_SZ		0x40000000	/* Client Mode sb2pcitranslation2 size in bytes */
++#define SI_PCIE_DMA_L32		0x00000000	/* PCIE Client Mode sb2pcitranslation2
++						 * (2 ZettaBytes), low 32 bits
++						 */
++#define SI_PCIE_DMA_H32		0x80000000	/* PCIE Client Mode sb2pcitranslation2
++						 * (2 ZettaBytes), high 32 bits
++						 */
++
++#define SI_BCM53573_NANDFLASH	0x30000000	/* 53573 NAND flash base */
++#define SI_BCM53573_NORFLASH	0x1c000000	/* 53573 NOR flash base */
++#define SI_BCM53573_FLASH2_SZ	0x04000000	/* 53573 NOR flash2 size */
++
++#define	SI_BCM53573_NORFLASH_WINDOW	0x01000000	/* only support 16M direct access for
++							 * 3-byte address modes in spi flash
++							 */
++#define	SI_BCM53573_BOOTDEV_MASK	0x3
++#define	SI_BCM53573_BOOTDEV_NOR		0x0
++
++#define SI_BCM53573_NAND_PRE_MASK	0x100	/* 53573 NAND present mask */
++
++#define	SI_BCM53573_DDRTYPE_MASK	0x10
++#define	SI_BCM53573_DDRTYPE_DDR3	0x10
++
++#define	SI_BCM47189_RGMII_VDD_MASK	0x3
++#define	SI_BCM47189_RGMII_VDD_SHIFT	21
++#define	SI_BCM47189_RGMII_VDD_3_3V	0
++#define	SI_BCM47189_RGMII_VDD_2_5V	1
++#define	SI_BCM47189_RGMII_VDD_1_5V	1
++
++#define	SI_BCM53573_LOCKED_CPUPLL	0x1
++
++/* APB bridge code */
++#define	APB_BRIDGE_ID		0x135		/* APB Bridge 0, 1, etc. */
++
++/* core codes */
++#define	NODEV_CORE_ID		0x700		/* Invalid coreid */
++#define	CC_CORE_ID		0x800		/* chipcommon core */
++#define	ILINE20_CORE_ID		0x801		/* iline20 core */
++#define	SRAM_CORE_ID		0x802		/* sram core */
++#define	SDRAM_CORE_ID		0x803		/* sdram core */
++#define	PCI_CORE_ID		0x804		/* pci core */
++#define	MIPS_CORE_ID		0x805		/* mips core */
++#define	ENET_CORE_ID		0x806		/* enet mac core */
++#define	CODEC_CORE_ID		0x807		/* v90 codec core */
++#define	USB_CORE_ID		0x808		/* usb 1.1 host/device core */
++#define	ADSL_CORE_ID		0x809		/* ADSL core */
++#define	ILINE100_CORE_ID	0x80a		/* iline100 core */
++#define	IPSEC_CORE_ID		0x80b		/* ipsec core */
++#define	UTOPIA_CORE_ID		0x80c		/* utopia core */
++#define	PCMCIA_CORE_ID		0x80d		/* pcmcia core */
++#define	SOCRAM_CORE_ID		0x80e		/* internal memory core */
++#define	MEMC_CORE_ID		0x80f		/* memc sdram core */
++#define	OFDM_CORE_ID		0x810		/* OFDM phy core */
++#define	EXTIF_CORE_ID		0x811		/* external interface core */
++#define	D11_CORE_ID		0x812		/* 802.11 MAC core */
++#define	APHY_CORE_ID		0x813		/* 802.11a phy core */
++#define	BPHY_CORE_ID		0x814		/* 802.11b phy core */
++#define	GPHY_CORE_ID		0x815		/* 802.11g phy core */
++#define	MIPS33_CORE_ID		0x816		/* mips3302 core */
++#define	USB11H_CORE_ID		0x817		/* usb 1.1 host core */
++#define	USB11D_CORE_ID		0x818		/* usb 1.1 device core */
++#define	USB20H_CORE_ID		0x819		/* usb 2.0 host core */
++#define	USB20D_CORE_ID		0x81a		/* usb 2.0 device core */
++#define	SDIOH_CORE_ID		0x81b		/* sdio host core */
++#define	ROBO_CORE_ID		0x81c		/* roboswitch core */
++#define	ATA100_CORE_ID		0x81d		/* parallel ATA core */
++#define	SATAXOR_CORE_ID		0x81e		/* serial ATA & XOR DMA core */
++#define	GIGETH_CORE_ID		0x81f		/* gigabit ethernet core */
++#define	PCIE_CORE_ID		0x820		/* pci express core */
++#define	NPHY_CORE_ID		0x821		/* 802.11n 2x2 phy core */
++#define	SRAMC_CORE_ID		0x822		/* SRAM controller core */
++#define	MINIMAC_CORE_ID		0x823		/* MINI MAC/phy core */
++#define	ARM11_CORE_ID		0x824		/* ARM 1176 core */
++#define	ARM7S_CORE_ID		0x825		/* ARM7tdmi-s core */
++#define	LPPHY_CORE_ID		0x826		/* 802.11a/b/g phy core */
++#define	PMU_CORE_ID		0x827		/* PMU core */
++#define	SSNPHY_CORE_ID		0x828		/* 802.11n single-stream phy core */
++#define	SDIOD_CORE_ID		0x829		/* SDIO device core */
++#define	ARMCM3_CORE_ID		0x82a		/* ARM Cortex M3 core */
++#define	HTPHY_CORE_ID		0x82b		/* 802.11n 4x4 phy core */
++#define	MIPS74K_CORE_ID		0x82c		/* mips 74k core */
++#define	GMAC_CORE_ID		0x82d		/* Gigabit MAC core */
++#define	DMEMC_CORE_ID		0x82e		/* DDR1/2 memory controller core */
++#define	PCIERC_CORE_ID		0x82f		/* PCIE Root Complex core */
++#define	OCP_CORE_ID		0x830		/* OCP2OCP bridge core */
++#define	SC_CORE_ID		0x831		/* shared common core */
++#define	AHB_CORE_ID		0x832		/* OCP2AHB bridge core */
++#define	SPIH_CORE_ID		0x833		/* SPI host core */
++#define	I2S_CORE_ID		0x834		/* I2S core */
++#define	DMEMS_CORE_ID		0x835		/* SDR/DDR1 memory controller core */
++#define	DEF_SHIM_COMP		0x837		/* SHIM component in ubus/6362 */
++
++#define ACPHY_CORE_ID		0x83b		/* Dot11 ACPHY */
++#define PCIE2_CORE_ID		0x83c		/* pci express Gen2 core */
++#define USB30D_CORE_ID		0x83d		/* usb 3.0 device core */
++#define ARMCR4_CORE_ID		0x83e		/* ARM CR4 CPU */
++#define GCI_CORE_ID		0x840		/* GCI Core */
++#define M2MDMA_CORE_ID          0x844           /* memory to memory dma */
++#define CMEM_CORE_ID		0x846		/* CNDS DDR2/3 memory controller */
++#define ARMCA7_CORE_ID		0x847		/* ARM CA7 CPU */
++#define SYSMEM_CORE_ID		0x849		/* System memory core */
++#define APB_BRIDGE_CORE_ID	0x135		/* APB bridge core ID */
++#define AXI_CORE_ID		0x301		/* AXI/GPV core ID */
++#define EROM_CORE_ID		0x366		/* EROM core ID */
++#define OOB_ROUTER_CORE_ID	0x367		/* OOB router core ID */
++#define DEF_AI_COMP		0xfff		/* Default component, in ai chips it maps all
++						 * unused address ranges
++						 */
++
++#define CC_4706_CORE_ID		0x500		/* chipcommon core */
++#define NS_PCIEG2_CORE_ID	0x501		/* PCIE Gen 2 core */
++#define NS_DMA_CORE_ID		0x502		/* DMA core */
++#define NS_SDIO3_CORE_ID	0x503		/* SDIO3 core */
++#define NS_USB20_CORE_ID	0x504		/* USB2.0 core */
++#define NS_USB30_CORE_ID	0x505		/* USB3.0 core */
++#define NS_A9JTAG_CORE_ID	0x506		/* ARM Cortex A9 JTAG core */
++#define NS_DDR23_CORE_ID	0x507		/* Denali DDR2/DDR3 memory controller */
++#define NS_ROM_CORE_ID		0x508		/* ROM core */
++#define NS_NAND_CORE_ID		0x509		/* NAND flash controller core */
++#define NS_QSPI_CORE_ID		0x50a		/* SPI flash controller core */
++#define NS_CCB_CORE_ID		0x50b		/* ChipcommonB core */
++#define SOCRAM_4706_CORE_ID	0x50e		/* internal memory core */
++#define NS_SOCRAM_CORE_ID	SOCRAM_4706_CORE_ID
++#define	ARMCA9_CORE_ID		0x510		/* ARM Cortex A9 core (ihost) */
++#define	NS_IHOST_CORE_ID	ARMCA9_CORE_ID	/* ARM Cortex A9 core (ihost) */
++#define GMAC_COMMON_4706_CORE_ID	0x5dc		/* Gigabit MAC core */
++#define GMAC_4706_CORE_ID	0x52d		/* Gigabit MAC core */
++#define AMEMC_CORE_ID		0x52e		/* DDR1/2 memory controller core */
++#define ALTA_CORE_ID		0x534		/* I2S core */
++#define DDR23_PHY_CORE_ID	0x5dd
++
++#define SI_PCI1_MEM     0x40000000  /* Host Mode sb2pcitranslation0 (64 MB) */
++#define SI_PCI1_CFG     0x44000000  /* Host Mode sb2pcitranslation1 (64 MB) */
++#define SI_PCIE1_DMA_H32		0xc0000000	/* PCIE Client Mode sb2pcitranslation2
++						 * (2 ZettaBytes), high 32 bits
++						 */
++#define CC_4706B0_CORE_REV	0x8000001f		/* chipcommon core */
++#define SOCRAM_4706B0_CORE_REV	0x80000005		/* internal memory core */
++#define GMAC_4706B0_CORE_REV	0x80000000		/* Gigabit MAC core */
++#define NS_PCIEG2_CORE_REV_B0	0x7		/* NS-B0 PCIE Gen 2 core rev */
++
++/* There are TWO constants on all HND chips: SI_ENUM_BASE above,
++ * and chipcommon being the first core:
++ */
++#define	SI_CC_IDX		0
++/* SOC Interconnect types (aka chip types) */
++#define	SOCI_SB			0
++#define	SOCI_AI			1
++#define	SOCI_UBUS		2
++#define	SOCI_NAI		3
++
++/* Common core control flags */
++#define	SICF_BIST_EN		0x8000
++#define	SICF_PME_EN		0x4000
++#define	SICF_CORE_BITS		0x3ffc
++#define	SICF_FGC		0x0002
++#define	SICF_CLOCK_EN		0x0001
++
++/* Common core status flags */
++#define	SISF_BIST_DONE		0x8000
++#define	SISF_BIST_ERROR		0x4000
++#define	SISF_GATED_CLK		0x2000
++#define	SISF_DMA64		0x1000
++#define	SISF_CORE_BITS		0x0fff
++
++/* Norstar core status flags */
++#define SISF_NS_BOOTDEV_MASK	0x0003	/* ROM core */
++#define SISF_NS_BOOTDEV_NOR	0x0000	/* ROM core */
++#define SISF_NS_BOOTDEV_NAND	0x0001	/* ROM core */
++#define SISF_NS_BOOTDEV_ROM	0x0002	/* ROM core */
++#define SISF_NS_BOOTDEV_OFFLOAD	0x0003	/* ROM core */
++#define SISF_NS_SKUVEC_MASK	0x000c	/* ROM core */
++
++/* A register that is common to all cores to
++ * communicate w/PMU regarding clock control.
++ */
++#define SI_CLK_CTL_ST		0x1e0		/* clock control and status */
++#define SI_PWR_CTL_ST		0x1e8		/* For memory clock gating */
++
++/* clk_ctl_st register */
++#define	CCS_FORCEALP		0x00000001	/* force ALP request */
++#define	CCS_FORCEHT		0x00000002	/* force HT request */
++#define	CCS_FORCEILP		0x00000004	/* force ILP request */
++#define	CCS_ALPAREQ		0x00000008	/* ALP Avail Request */
++#define	CCS_HTAREQ		0x00000010	/* HT Avail Request */
++#define	CCS_FORCEHWREQOFF	0x00000020	/* Force HW Clock Request Off */
++#define CCS_HQCLKREQ		0x00000040	/* HQ Clock Required */
++#define CCS_USBCLKREQ		0x00000100	/* USB Clock Req */
++#define CCS_SECICLKREQ		0x00000100	/* SECI Clock Req */
++#define CCS_ARMFASTCLOCKREQ	0x00000100	/* ARM CR4/CA7 fast clock request */
++#define CCS_AVBCLKREQ		0x00000400	/* AVB Clock enable request */
++#define CCS_ERSRC_REQ_MASK	0x00000700	/* external resource requests */
++#define CCS_ERSRC_REQ_SHIFT	8
++#define	CCS_ALPAVAIL		0x00010000	/* ALP is available */
++#define	CCS_HTAVAIL		0x00020000	/* HT is available */
++#define CCS_BP_ON_APL		0x00040000	/* RO: Backplane is running on ALP clock */
++#define CCS_BP_ON_HT		0x00080000	/* RO: Backplane is running on HT clock */
++#define CCS_ARMFASTCLOCKSTATUS	0x01000000	/* Fast CPU clock is running */
++#define CCS_ERSRC_STS_MASK	0x07000000	/* external resource status */
++#define CCS_ERSRC_STS_SHIFT	24
++#define CCS_SECI_AVAIL		0x01000000	/* RO: SECI is available  */
++
++#define	CCS0_HTAVAIL		0x00010000	/* HT avail in chipc and pcmcia on 4328a0 */
++#define	CCS0_ALPAVAIL		0x00020000	/* ALP avail in chipc and pcmcia on 4328a0 */
++
++/* Not really related to SOC Interconnect, but a couple of software
++ * conventions for the use the flash space:
++ */
++
++/* Minumum amount of flash we support */
++#define FLASH_MIN		0x00020000	/* Minimum flash size */
++
++/* A boot/binary may have an embedded block that describes its size  */
++#define	BISZ_OFFSET		0x3e0		/* At this offset into the binary */
++#define	BISZ_MAGIC		0x4249535a	/* Marked with this value: 'BISZ' */
++#define	BISZ_MAGIC_IDX		0		/* Word 0: magic */
++#define	BISZ_TXTST_IDX		1		/*	1: text start */
++#define	BISZ_TXTEND_IDX		2		/*	2: text end */
++#define	BISZ_DATAST_IDX		3		/*	3: data start */
++#define	BISZ_DATAEND_IDX	4		/*	4: data end */
++#define	BISZ_BSSST_IDX		5		/*	5: bss start */
++#define	BISZ_BSSEND_IDX		6		/*	6: bss end */
++#define BISZ_SIZE		7		/* descriptor size in 32-bit integers */
++
++/* Boot/Kernel related defintion and functions */
++#define	SOC_BOOTDEV_ROM		0x00000001
++#define	SOC_BOOTDEV_PFLASH	0x00000002
++#define	SOC_BOOTDEV_SFLASH	0x00000004
++#define	SOC_BOOTDEV_NANDFLASH	0x00000008
++
++#define	SOC_KNLDEV_NORFLASH	0x00000002
++#define	SOC_KNLDEV_NANDFLASH	0x00000004
++
++#if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__)
++int soc_boot_dev(void *sih);
++int soc_knl_dev(void *sih);
++#endif	/* !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) */
++
++#define PMU_BASE_OFFSET	0x00012000	/* PMU offset is changed for ccrev >= 56 */
++#endif /* _HNDSOC_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/linux_osl.h b/module_drivers/drivers/net/wireless/bcmdhd/include/linux_osl.h
+new file mode 100644
+index 000000000..8dcfec148
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/linux_osl.h
+@@ -0,0 +1,1170 @@
++/*
++ * Linux OS Independent Layer
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: linux_osl.h 672413 2016-11-28 11:13:23Z $
++ */
++
++#ifndef _linux_osl_h_
++#define _linux_osl_h_
++
++#include <typedefs.h>
++#define DECLSPEC_ALIGN(x)	__attribute__ ((aligned(x)))
++
++/* Linux Kernel: File Operations: start */
++extern void * osl_os_open_image(char * filename);
++extern int osl_os_get_image_block(char * buf, int len, void * image);
++extern void osl_os_close_image(void * image);
++extern int osl_os_image_size(void *image);
++/* Linux Kernel: File Operations: end */
++
++#ifdef BCMDRIVER
++
++/* OSL initialization */
++#ifdef SHARED_OSL_CMN
++extern osl_t *osl_attach(void *pdev, uint bustype, bool pkttag, void **osh_cmn);
++#else
++extern osl_t *osl_attach(void *pdev, uint bustype, bool pkttag);
++#endif /* SHARED_OSL_CMN */
++
++extern void osl_detach(osl_t *osh);
++extern int osl_static_mem_init(osl_t *osh, void *adapter);
++extern int osl_static_mem_deinit(osl_t *osh, void *adapter);
++extern void osl_set_bus_handle(osl_t *osh, void *bus_handle);
++extern void* osl_get_bus_handle(osl_t *osh);
++
++/* Global ASSERT type */
++extern uint32 g_assert_type;
++
++#ifdef CONFIG_PHYS_ADDR_T_64BIT
++#define PRI_FMT_x       "llx"
++#define PRI_FMT_X       "llX"
++#define PRI_FMT_o       "llo"
++#define PRI_FMT_d       "lld"
++#else
++#define PRI_FMT_x       "x"
++#define PRI_FMT_X       "X"
++#define PRI_FMT_o       "o"
++#define PRI_FMT_d       "d"
++#endif /* CONFIG_PHYS_ADDR_T_64BIT */
++/* ASSERT */
++#if defined(BCMASSERT_LOG)
++	#define ASSERT(exp) \
++	  do { if (!(exp)) osl_assert(#exp, __FILE__, __LINE__); } while (0)
++extern void osl_assert(const char *exp, const char *file, int line);
++#else
++	#ifdef __GNUC__
++		#define GCC_VERSION \
++			(__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
++		#if GCC_VERSION > 30100
++			#define ASSERT(exp)	do {} while (0)
++		#else
++			/* ASSERT could cause segmentation fault on GCC3.1, use empty instead */
++			#define ASSERT(exp)
++		#endif /* GCC_VERSION > 30100 */
++	#endif /* __GNUC__ */
++#endif 
++
++/* bcm_prefetch_32B */
++static inline void bcm_prefetch_32B(const uint8 *addr, const int cachelines_32B)
++{
++#if (defined(STB) && defined(__arm__)) && (__LINUX_ARM_ARCH__ >= 5)
++	switch (cachelines_32B) {
++		case 4: __asm__ __volatile__("pld\t%a0" :: "p"(addr + 96) : "cc");
++		case 3: __asm__ __volatile__("pld\t%a0" :: "p"(addr + 64) : "cc");
++		case 2: __asm__ __volatile__("pld\t%a0" :: "p"(addr + 32) : "cc");
++		case 1: __asm__ __volatile__("pld\t%a0" :: "p"(addr +  0) : "cc");
++	}
++#endif 
++}
++
++/* microsecond delay */
++#define	OSL_DELAY(usec)		osl_delay(usec)
++extern void osl_delay(uint usec);
++
++#define OSL_SLEEP(ms)			osl_sleep(ms)
++extern void osl_sleep(uint ms);
++
++#define	OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
++	osl_pcmcia_read_attr((osh), (offset), (buf), (size))
++#define	OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
++	osl_pcmcia_write_attr((osh), (offset), (buf), (size))
++extern void osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size);
++extern void osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size);
++
++/* PCI configuration space access macros */
++#define	OSL_PCI_READ_CONFIG(osh, offset, size) \
++	osl_pci_read_config((osh), (offset), (size))
++#define	OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
++	osl_pci_write_config((osh), (offset), (size), (val))
++extern uint32 osl_pci_read_config(osl_t *osh, uint offset, uint size);
++extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
++
++/* PCI device bus # and slot # */
++#define OSL_PCI_BUS(osh)	osl_pci_bus(osh)
++#define OSL_PCI_SLOT(osh)	osl_pci_slot(osh)
++#define OSL_PCIE_DOMAIN(osh)	osl_pcie_domain(osh)
++#define OSL_PCIE_BUS(osh)	osl_pcie_bus(osh)
++extern uint osl_pci_bus(osl_t *osh);
++extern uint osl_pci_slot(osl_t *osh);
++extern uint osl_pcie_domain(osl_t *osh);
++extern uint osl_pcie_bus(osl_t *osh);
++extern struct pci_dev *osl_pci_device(osl_t *osh);
++
++#define OSL_ACP_COHERENCE		(1<<1L)
++#define OSL_FWDERBUF			(1<<2L)
++
++/* Pkttag flag should be part of public information */
++typedef struct {
++	bool pkttag;
++	bool mmbus;		/**< Bus supports memory-mapped register accesses */
++	pktfree_cb_fn_t tx_fn;  /**< Callback function for PKTFREE */
++	void *tx_ctx;		/**< Context to the callback function */
++	void	*unused[3];
++} osl_pubinfo_t;
++
++extern void osl_flag_set(osl_t *osh, uint32 mask);
++extern void osl_flag_clr(osl_t *osh, uint32 mask);
++extern bool osl_is_flag_set(osl_t *osh, uint32 mask);
++
++#define PKTFREESETCB(osh, _tx_fn, _tx_ctx)		\
++	do {						\
++	   ((osl_pubinfo_t*)osh)->tx_fn = _tx_fn;	\
++	   ((osl_pubinfo_t*)osh)->tx_ctx = _tx_ctx;	\
++	} while (0)
++
++
++/* host/bus architecture-specific byte swap */
++#define BUS_SWAP32(v)		(v)
++	#define MALLOC(osh, size)	osl_malloc((osh), (size))
++	#define MALLOCZ(osh, size)	osl_mallocz((osh), (size))
++	#define MFREE(osh, addr, size)	osl_mfree((osh), (addr), (size))
++	#define VMALLOC(osh, size)	osl_vmalloc((osh), (size))
++	#define VMALLOCZ(osh, size)	osl_vmallocz((osh), (size))
++	#define VMFREE(osh, addr, size)	osl_vmfree((osh), (addr), (size))
++	#define MALLOCED(osh)		osl_malloced((osh))
++	#define MEMORY_LEFTOVER(osh) osl_check_memleak(osh)
++	extern void *osl_malloc(osl_t *osh, uint size);
++	extern void *osl_mallocz(osl_t *osh, uint size);
++	extern void osl_mfree(osl_t *osh, void *addr, uint size);
++	extern void *osl_vmalloc(osl_t *osh, uint size);
++	extern void *osl_vmallocz(osl_t *osh, uint size);
++	extern void osl_vmfree(osl_t *osh, void *addr, uint size);
++	extern uint osl_malloced(osl_t *osh);
++	extern uint osl_check_memleak(osl_t *osh);
++
++#define	MALLOC_FAILED(osh)	osl_malloc_failed((osh))
++extern uint osl_malloc_failed(osl_t *osh);
++
++/* allocate/free shared (dma-able) consistent memory */
++#define	DMA_CONSISTENT_ALIGN	osl_dma_consistent_align()
++#define	DMA_ALLOC_CONSISTENT(osh, size, align, tot, pap, dmah) \
++	osl_dma_alloc_consistent((osh), (size), (align), (tot), (pap))
++#define	DMA_FREE_CONSISTENT(osh, va, size, pa, dmah) \
++	osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
++
++#define	DMA_ALLOC_CONSISTENT_FORCE32(osh, size, align, tot, pap, dmah) \
++	osl_dma_alloc_consistent((osh), (size), (align), (tot), (pap))
++#define	DMA_FREE_CONSISTENT_FORCE32(osh, va, size, pa, dmah) \
++	osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
++
++extern uint osl_dma_consistent_align(void);
++extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, uint16 align,
++	uint *tot, dmaaddr_t *pap);
++extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, dmaaddr_t pa);
++
++/* map/unmap direction */
++#define DMA_NO	0	/* Used to skip cache op */
++#define	DMA_TX	1	/* TX direction for DMA */
++#define	DMA_RX	2	/* RX direction for DMA */
++
++/* map/unmap shared (dma-able) memory */
++#define	DMA_UNMAP(osh, pa, size, direction, p, dmah) \
++	osl_dma_unmap((osh), (pa), (size), (direction))
++extern dmaaddr_t osl_dma_map(osl_t *osh, void *va, uint size, int direction, void *p,
++	hnddma_seg_map_t *txp_dmah);
++extern void osl_dma_unmap(osl_t *osh, dmaaddr_t pa, uint size, int direction);
++
++/* API for DMA addressing capability */
++#define OSL_DMADDRWIDTH(osh, addrwidth) ({BCM_REFERENCE(osh); BCM_REFERENCE(addrwidth);})
++
++#define OSL_SMP_WMB()	smp_wmb()
++
++/* API for CPU relax */
++extern void osl_cpu_relax(void);
++#define OSL_CPU_RELAX() osl_cpu_relax()
++
++extern void osl_preempt_disable(osl_t *osh);
++extern void osl_preempt_enable(osl_t *osh);
++#define OSL_DISABLE_PREEMPTION(osh)	osl_preempt_disable(osh)
++#define OSL_ENABLE_PREEMPTION(osh)	osl_preempt_enable(osh)
++
++#if (!defined(DHD_USE_COHERENT_MEM_FOR_RING) && defined(__ARM_ARCH_7A__)) || \
++	(defined(STBLINUX) && defined(__ARM_ARCH_7A__))
++	extern void osl_cache_flush(void *va, uint size);
++	extern void osl_cache_inv(void *va, uint size);
++	extern void osl_prefetch(const void *ptr);
++	#define OSL_CACHE_FLUSH(va, len)	osl_cache_flush((void *)(va), len)
++	#define OSL_CACHE_INV(va, len)		osl_cache_inv((void *)(va), len)
++	#define OSL_PREFETCH(ptr)			osl_prefetch(ptr)
++#if defined(__ARM_ARCH_7A__)
++	extern int osl_arch_is_coherent(void);
++	#define OSL_ARCH_IS_COHERENT()		osl_arch_is_coherent()
++	extern int osl_acp_war_enab(void);
++	#define OSL_ACP_WAR_ENAB()			osl_acp_war_enab()
++#else  /* !__ARM_ARCH_7A__ */
++	#define OSL_ARCH_IS_COHERENT()		NULL
++	#define OSL_ACP_WAR_ENAB()			NULL
++#endif /* !__ARM_ARCH_7A__ */
++#else  /* !__mips__ && !__ARM_ARCH_7A__ */
++	#define OSL_CACHE_FLUSH(va, len)	BCM_REFERENCE(va)
++	#define OSL_CACHE_INV(va, len)		BCM_REFERENCE(va)
++	#define OSL_PREFETCH(ptr)		BCM_REFERENCE(ptr)
++
++	#define OSL_ARCH_IS_COHERENT()		NULL
++	#define OSL_ACP_WAR_ENAB()			NULL
++#endif 
++
++/* register access macros */
++#if defined(BCMSDIO)
++	#include <bcmsdh.h>
++	#define OSL_WRITE_REG(osh, r, v) (bcmsdh_reg_write(osl_get_bus_handle(osh), \
++		(uintptr)(r), sizeof(*(r)), (v)))
++	#define OSL_READ_REG(osh, r) (bcmsdh_reg_read(osl_get_bus_handle(osh), \
++		(uintptr)(r), sizeof(*(r))))
++#elif (defined(STB) && defined(__arm__))
++extern void osl_pcie_rreg(osl_t *osh, ulong addr, void *v, uint size);
++
++#define OSL_READ_REG(osh, r) \
++	({\
++		__typeof(*(r)) __osl_v; \
++		osl_pcie_rreg(osh, (uintptr)(r), (void *)&__osl_v, sizeof(*(r))); \
++		__osl_v; \
++	})
++#endif 
++
++#if (defined(STB) && defined(__arm__))
++	#define SELECT_BUS_WRITE(osh, mmap_op, bus_op) ({BCM_REFERENCE(osh); mmap_op;})
++	#define SELECT_BUS_READ(osh, mmap_op, bus_op) ({BCM_REFERENCE(osh); bus_op;})
++#else /* !BCM47XX_CA9 */
++#if defined(BCMSDIO)
++	#define SELECT_BUS_WRITE(osh, mmap_op, bus_op) if (((osl_pubinfo_t*)(osh))->mmbus) \
++		mmap_op else bus_op
++	#define SELECT_BUS_READ(osh, mmap_op, bus_op) (((osl_pubinfo_t*)(osh))->mmbus) ? \
++		mmap_op : bus_op
++#else
++	#define SELECT_BUS_WRITE(osh, mmap_op, bus_op) ({BCM_REFERENCE(osh); mmap_op;})
++	#define SELECT_BUS_READ(osh, mmap_op, bus_op) ({BCM_REFERENCE(osh); mmap_op;})
++#endif 
++#endif 
++
++#define OSL_ERROR(bcmerror)	osl_error(bcmerror)
++extern int osl_error(int bcmerror);
++
++/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
++#define	PKTBUFSZ	2048   /* largest reasonable packet buffer, driver uses for ethernet MTU */
++
++#define OSH_NULL   NULL
++
++/*
++ * BINOSL selects the slightly slower function-call-based binary compatible osl.
++ * Macros expand to calls to functions defined in linux_osl.c .
++ */
++#include <linuxver.h>           /* use current 2.4.x calling conventions */
++#include <linux/kernel.h>       /* for vsn/printf's */
++#include <linux/string.h>       /* for mem*, str* */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 4, 29)
++extern uint64 osl_sysuptime_us(void);
++#define OSL_SYSUPTIME()		((uint32)jiffies_to_msecs(jiffies))
++#define OSL_SYSUPTIME_US()	osl_sysuptime_us()
++#else
++#define OSL_SYSUPTIME()		((uint32)jiffies * (1000 / HZ))
++#error "OSL_SYSUPTIME_US() may need to be defined"
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 4, 29) */
++#define	printf(fmt, args...)	printk(fmt , ## args)
++#include <linux/kernel.h>	/* for vsn/printf's */
++#include <linux/string.h>	/* for mem*, str* */
++/* bcopy's: Linux kernel doesn't provide these (anymore) */
++#define	bcopy(src, dst, len)	memcpy((dst), (src), (len))
++#define	bcmp(b1, b2, len)	memcmp((b1), (b2), (len))
++#define	bzero(b, len)		memset((b), '\0', (len))
++
++/* register access macros */
++
++#ifdef CONFIG_64BIT
++/* readq is defined only for 64 bit platform */
++#define R_REG(osh, r) (\
++	SELECT_BUS_READ(osh, \
++		({ \
++			__typeof(*(r)) __osl_v = 0; \
++			switch (sizeof(*(r))) { \
++				case sizeof(uint8):	__osl_v = \
++					readb((volatile uint8*)(r)); break; \
++				case sizeof(uint16):	__osl_v = \
++					readw((volatile uint16*)(r)); break; \
++				case sizeof(uint32):	__osl_v = \
++					readl((volatile uint32*)(r)); break; \
++				case sizeof(uint64):	__osl_v = \
++					readq((volatile uint64*)(r)); break; \
++			} \
++			__osl_v; \
++		}), \
++		OSL_READ_REG(osh, r)) \
++)
++#else /* !CONFIG_64BIT */
++#define R_REG(osh, r) (\
++	SELECT_BUS_READ(osh, \
++		({ \
++			__typeof(*(r)) __osl_v = 0; \
++			switch (sizeof(*(r))) { \
++				case sizeof(uint8):	__osl_v = \
++					readb((volatile uint8*)(r)); break; \
++				case sizeof(uint16):	__osl_v = \
++					readw((volatile uint16*)(r)); break; \
++				case sizeof(uint32):	__osl_v = \
++					readl((volatile uint32*)(r)); break; \
++			} \
++			__osl_v; \
++		}), \
++		OSL_READ_REG(osh, r)) \
++)
++#endif /* CONFIG_64BIT */
++
++#ifdef CONFIG_64BIT
++/* writeq is defined only for 64 bit platform */
++#define W_REG(osh, r, v) do { \
++	SELECT_BUS_WRITE(osh, \
++		switch (sizeof(*(r))) { \
++			case sizeof(uint8):	writeb((uint8)(v), (volatile uint8*)(r)); break; \
++			case sizeof(uint16):	writew((uint16)(v), (volatile uint16*)(r)); break; \
++			case sizeof(uint32):	writel((uint32)(v), (volatile uint32*)(r)); break; \
++			case sizeof(uint64):	writeq((uint64)(v), (volatile uint64*)(r)); break; \
++		}, \
++		(OSL_WRITE_REG(osh, r, v))); \
++	} while (0)
++
++#else /* !CONFIG_64BIT */
++#define W_REG(osh, r, v) do { \
++	SELECT_BUS_WRITE(osh, \
++		switch (sizeof(*(r))) { \
++			case sizeof(uint8):	writeb((uint8)(v), (volatile uint8*)(r)); break; \
++			case sizeof(uint16):	writew((uint16)(v), (volatile uint16*)(r)); break; \
++			case sizeof(uint32):	writel((uint32)(v), (volatile uint32*)(r)); break; \
++		}, \
++		(OSL_WRITE_REG(osh, r, v))); \
++	} while (0)
++#endif /* CONFIG_64BIT */
++
++#define	AND_REG(osh, r, v)		W_REG(osh, (r), R_REG(osh, r) & (v))
++#define	OR_REG(osh, r, v)		W_REG(osh, (r), R_REG(osh, r) | (v))
++
++/* bcopy, bcmp, and bzero functions */
++#define	bcopy(src, dst, len)	memcpy((dst), (src), (len))
++#define	bcmp(b1, b2, len)	memcmp((b1), (b2), (len))
++#define	bzero(b, len)		memset((b), '\0', (len))
++
++/* uncached/cached virtual address */
++#define OSL_UNCACHED(va)	((void *)va)
++#define OSL_CACHED(va)		((void *)va)
++
++#define OSL_PREF_RANGE_LD(va, sz) BCM_REFERENCE(va)
++#define OSL_PREF_RANGE_ST(va, sz) BCM_REFERENCE(va)
++
++/* get processor cycle count */
++#if defined(__i386__)
++#define	OSL_GETCYCLES(x)	rdtscl((x))
++#else
++#define OSL_GETCYCLES(x)	((x) = 0)
++#endif 
++
++/* dereference an address that may cause a bus exception */
++#define	BUSPROBE(val, addr)	({ (val) = R_REG(NULL, (addr)); 0; })
++
++/* map/unmap physical to virtual I/O */
++#if !defined(CONFIG_MMC_MSM7X00A)
++#define	REG_MAP(pa, size)	ioremap((unsigned long)(pa), (unsigned long)(size))
++#else
++#define REG_MAP(pa, size)       (void *)(0)
++#endif /* !defined(CONFIG_MMC_MSM7X00A */
++#define	REG_UNMAP(va)		iounmap((va))
++
++/* shared (dma-able) memory access macros */
++#define	R_SM(r)			*(r)
++#define	W_SM(r, v)		(*(r) = (v))
++#define	BZERO_SM(r, len)	memset((r), '\0', (len))
++
++/* Because the non BINOSL implemenation of the PKT OSL routines are macros (for
++ * performance reasons),  we need the Linux headers.
++ */
++#include <linuxver.h>		/* use current 2.4.x calling conventions */
++
++/* packet primitives */
++#ifdef BCMDBG_CTRACE
++#define	PKTGET(osh, len, send)		osl_pktget((osh), (len), __LINE__, __FILE__)
++#define	PKTDUP(osh, skb)		osl_pktdup((osh), (skb), __LINE__, __FILE__)
++#else
++#ifdef BCM_OBJECT_TRACE
++#define	PKTGET(osh, len, send)		osl_pktget((osh), (len), __LINE__, __FUNCTION__)
++#define	PKTDUP(osh, skb)		osl_pktdup((osh), (skb), __LINE__, __FUNCTION__)
++#else
++#define	PKTGET(osh, len, send)		osl_pktget((osh), (len))
++#define	PKTDUP(osh, skb)		osl_pktdup((osh), (skb))
++#endif /* BCM_OBJECT_TRACE */
++#endif /* BCMDBG_CTRACE */
++#define PKTLIST_DUMP(osh, buf)		BCM_REFERENCE(osh)
++#define PKTDBG_TRACE(osh, pkt, bit)	BCM_REFERENCE(osh)
++#if defined(BCM_OBJECT_TRACE)
++#define	PKTFREE(osh, skb, send)		osl_pktfree((osh), (skb), (send), __LINE__, __FUNCTION__)
++#else
++#define	PKTFREE(osh, skb, send)		osl_pktfree((osh), (skb), (send))
++#endif /* BCM_OBJECT_TRACE */
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++#define	PKTGET_STATIC(osh, len, send)		osl_pktget_static((osh), (len))
++#define	PKTFREE_STATIC(osh, skb, send)		osl_pktfree_static((osh), (skb), (send))
++#else
++#define	PKTGET_STATIC	PKTGET
++#define	PKTFREE_STATIC	PKTFREE
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++#define	PKTDATA(osh, skb)		({BCM_REFERENCE(osh); (((struct sk_buff*)(skb))->data);})
++#define	PKTLEN(osh, skb)		({BCM_REFERENCE(osh); (((struct sk_buff*)(skb))->len);})
++#define PKTHEADROOM(osh, skb)		(PKTDATA(osh, skb)-(((struct sk_buff*)(skb))->head))
++#define PKTEXPHEADROOM(osh, skb, b)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 skb_realloc_headroom((struct sk_buff*)(skb), (b)); \
++	 })
++#define PKTTAILROOM(osh, skb)		\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 skb_tailroom((struct sk_buff*)(skb)); \
++	 })
++#define PKTPADTAILROOM(osh, skb, padlen) \
++	({ \
++	 BCM_REFERENCE(osh); \
++	 skb_pad((struct sk_buff*)(skb), (padlen)); \
++	 })
++#define	PKTNEXT(osh, skb)		({BCM_REFERENCE(osh); (((struct sk_buff*)(skb))->next);})
++#define	PKTSETNEXT(osh, skb, x)		\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x)); \
++	 })
++#define	PKTSETLEN(osh, skb, len)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 __skb_trim((struct sk_buff*)(skb), (len)); \
++	 })
++#define	PKTPUSH(osh, skb, bytes)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 skb_push((struct sk_buff*)(skb), (bytes)); \
++	 })
++#define	PKTPULL(osh, skb, bytes)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 skb_pull((struct sk_buff*)(skb), (bytes)); \
++	 })
++#define	PKTTAG(skb)			((void*)(((struct sk_buff*)(skb))->cb))
++#define PKTSETPOOL(osh, skb, x, y)	BCM_REFERENCE(osh)
++#define	PKTPOOL(osh, skb)		({BCM_REFERENCE(osh); BCM_REFERENCE(skb); FALSE;})
++#define PKTFREELIST(skb)        PKTLINK(skb)
++#define PKTSETFREELIST(skb, x)  PKTSETLINK((skb), (x))
++#define PKTPTR(skb)             (skb)
++#define PKTID(skb)              ({BCM_REFERENCE(skb); 0;})
++#define PKTSETID(skb, id)       ({BCM_REFERENCE(skb); BCM_REFERENCE(id);})
++#define PKTSHRINK(osh, m)		({BCM_REFERENCE(osh); m;})
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) && defined(TSQ_MULTIPLIER)
++#define PKTORPHAN(skb, tsq)          osl_pkt_orphan_partial(skb, tsq)
++extern void osl_pkt_orphan_partial(struct sk_buff *skb, int tsq);
++#else
++#define PKTORPHAN(skb, tsq)          ({BCM_REFERENCE(skb); 0;})
++#endif /* LINUX VERSION >= 3.6 */
++
++
++#ifdef BCMDBG_CTRACE
++#define	DEL_CTRACE(zosh, zskb) { \
++	unsigned long zflags; \
++	spin_lock_irqsave(&(zosh)->ctrace_lock, zflags); \
++	list_del(&(zskb)->ctrace_list); \
++	(zosh)->ctrace_num--; \
++	(zskb)->ctrace_start = 0; \
++	(zskb)->ctrace_count = 0; \
++	spin_unlock_irqrestore(&(zosh)->ctrace_lock, zflags); \
++}
++
++#define	UPDATE_CTRACE(zskb, zfile, zline) { \
++	struct sk_buff *_zskb = (struct sk_buff *)(zskb); \
++	if (_zskb->ctrace_count < CTRACE_NUM) { \
++		_zskb->func[_zskb->ctrace_count] = zfile; \
++		_zskb->line[_zskb->ctrace_count] = zline; \
++		_zskb->ctrace_count++; \
++	} \
++	else { \
++		_zskb->func[_zskb->ctrace_start] = zfile; \
++		_zskb->line[_zskb->ctrace_start] = zline; \
++		_zskb->ctrace_start++; \
++		if (_zskb->ctrace_start >= CTRACE_NUM) \
++			_zskb->ctrace_start = 0; \
++	} \
++}
++
++#define	ADD_CTRACE(zosh, zskb, zfile, zline) { \
++	unsigned long zflags; \
++	spin_lock_irqsave(&(zosh)->ctrace_lock, zflags); \
++	list_add(&(zskb)->ctrace_list, &(zosh)->ctrace_list); \
++	(zosh)->ctrace_num++; \
++	UPDATE_CTRACE(zskb, zfile, zline); \
++	spin_unlock_irqrestore(&(zosh)->ctrace_lock, zflags); \
++}
++
++#define PKTCALLER(zskb)	UPDATE_CTRACE((struct sk_buff *)zskb, (char *)__FUNCTION__, __LINE__)
++#endif /* BCMDBG_CTRACE */
++
++#ifdef CTFPOOL
++#define	CTFPOOL_REFILL_THRESH	3
++typedef struct ctfpool {
++	void		*head;
++	spinlock_t	lock;
++	osl_t		*osh;
++	uint		max_obj;
++	uint		curr_obj;
++	uint		obj_size;
++	uint		refills;
++	uint		fast_allocs;
++	uint 		fast_frees;
++	uint 		slow_allocs;
++} ctfpool_t;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
++#define	FASTBUF	(1 << 0)
++#define	PKTSETFAST(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 ((((struct sk_buff*)(skb))->pktc_flags) |= FASTBUF); \
++	 })
++#define	PKTCLRFAST(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 ((((struct sk_buff*)(skb))->pktc_flags) &= (~FASTBUF)); \
++	 })
++#define	PKTISFAST(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 ((((struct sk_buff*)(skb))->pktc_flags) & FASTBUF); \
++	 })
++#define	PKTFAST(osh, skb)	(((struct sk_buff*)(skb))->pktc_flags)
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
++#define	FASTBUF	(1 << 16)
++#define	PKTSETFAST(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 ((((struct sk_buff*)(skb))->mac_len) |= FASTBUF); \
++	 })
++#define	PKTCLRFAST(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 ((((struct sk_buff*)(skb))->mac_len) &= (~FASTBUF)); \
++	 })
++#define	PKTISFAST(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 ((((struct sk_buff*)(skb))->mac_len) & FASTBUF); \
++	 })
++#define	PKTFAST(osh, skb)	(((struct sk_buff*)(skb))->mac_len)
++#else
++#define	FASTBUF	(1 << 0)
++#define	PKTSETFAST(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 ((((struct sk_buff*)(skb))->__unused) |= FASTBUF); \
++	 })
++#define	PKTCLRFAST(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 ((((struct sk_buff*)(skb))->__unused) &= (~FASTBUF)); \
++	 })
++#define	PKTISFAST(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 ((((struct sk_buff*)(skb))->__unused) & FASTBUF); \
++	 })
++#define	PKTFAST(osh, skb)	(((struct sk_buff*)(skb))->__unused)
++#endif /* 2.6.22 */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
++#define	CTFPOOLPTR(osh, skb)	(((struct sk_buff*)(skb))->ctfpool)
++#define	CTFPOOLHEAD(osh, skb)	(((ctfpool_t *)((struct sk_buff*)(skb))->ctfpool)->head)
++#else
++#define	CTFPOOLPTR(osh, skb)	(((struct sk_buff*)(skb))->sk)
++#define	CTFPOOLHEAD(osh, skb)	(((ctfpool_t *)((struct sk_buff*)(skb))->sk)->head)
++#endif
++
++extern void *osl_ctfpool_add(osl_t *osh);
++extern void osl_ctfpool_replenish(osl_t *osh, uint thresh);
++extern int32 osl_ctfpool_init(osl_t *osh, uint numobj, uint size);
++extern void osl_ctfpool_cleanup(osl_t *osh);
++extern void osl_ctfpool_stats(osl_t *osh, void *b);
++#else /* CTFPOOL */
++#define	PKTSETFAST(osh, skb)	({BCM_REFERENCE(osh); BCM_REFERENCE(skb);})
++#define	PKTCLRFAST(osh, skb)	({BCM_REFERENCE(osh); BCM_REFERENCE(skb);})
++#define	PKTISFAST(osh, skb)	({BCM_REFERENCE(osh); BCM_REFERENCE(skb); FALSE;})
++#endif /* CTFPOOL */
++
++#define	PKTSETCTF(osh, skb)	({BCM_REFERENCE(osh); BCM_REFERENCE(skb);})
++#define	PKTCLRCTF(osh, skb)	({BCM_REFERENCE(osh); BCM_REFERENCE(skb);})
++#define	PKTISCTF(osh, skb)	({BCM_REFERENCE(osh); BCM_REFERENCE(skb); FALSE;})
++
++#ifdef HNDCTF
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
++#define	SKIPCT	(1 << 2)
++#define	CHAINED	(1 << 3)
++#define	PKTSETSKIPCT(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->pktc_flags |= SKIPCT); \
++	 })
++#define	PKTCLRSKIPCT(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->pktc_flags &= (~SKIPCT)); \
++	 })
++#define	PKTSKIPCT(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->pktc_flags & SKIPCT); \
++	 })
++#define	PKTSETCHAINED(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->pktc_flags |= CHAINED); \
++	 })
++#define	PKTCLRCHAINED(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->pktc_flags &= (~CHAINED)); \
++	 })
++#define	PKTISCHAINED(skb)	(((struct sk_buff*)(skb))->pktc_flags & CHAINED)
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
++#define	SKIPCT	(1 << 18)
++#define	CHAINED	(1 << 19)
++#define	PKTSETSKIPCT(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->mac_len |= SKIPCT); \
++	 })
++#define	PKTCLRSKIPCT(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->mac_len &= (~SKIPCT)); \
++	 })
++#define	PKTSKIPCT(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->mac_len & SKIPCT); \
++	 })
++#define	PKTSETCHAINED(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->mac_len |= CHAINED); \
++	 })
++#define	PKTCLRCHAINED(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->mac_len &= (~CHAINED)); \
++	 })
++#define	PKTISCHAINED(skb)	(((struct sk_buff*)(skb))->mac_len & CHAINED)
++#else /* 2.6.22 */
++#define	SKIPCT	(1 << 2)
++#define	CHAINED	(1 << 3)
++#define	PKTSETSKIPCT(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->__unused |= SKIPCT); \
++	 })
++#define	PKTCLRSKIPCT(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->__unused &= (~SKIPCT)); \
++	 })
++#define	PKTSKIPCT(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->__unused & SKIPCT); \
++	 })
++#define	PKTSETCHAINED(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->__unused |= CHAINED); \
++	 })
++#define	PKTCLRCHAINED(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->__unused &= (~CHAINED)); \
++	 })
++#define	PKTISCHAINED(skb)	(((struct sk_buff*)(skb))->__unused & CHAINED)
++#endif /* 2.6.22 */
++typedef struct ctf_mark {
++	uint32	value;
++}	ctf_mark_t;
++#define CTF_MARK(m)				(m.value)
++#else /* HNDCTF */
++#define	PKTSETSKIPCT(osh, skb)	({BCM_REFERENCE(osh); BCM_REFERENCE(skb);})
++#define	PKTCLRSKIPCT(osh, skb)	({BCM_REFERENCE(osh); BCM_REFERENCE(skb);})
++#define	PKTSKIPCT(osh, skb)	({BCM_REFERENCE(osh); BCM_REFERENCE(skb);})
++#define CTF_MARK(m)		({BCM_REFERENCE(m); 0;})
++#endif /* HNDCTF */
++
++#if defined(BCM_GMAC3)
++
++/** pktalloced accounting in devices using GMAC Bulk Forwarding to DHD */
++
++/* Account for packets delivered to downstream forwarder by GMAC interface. */
++extern void osl_pkt_tofwder(osl_t *osh, void *skbs, int skb_cnt);
++#define PKTTOFWDER(osh, skbs, skb_cnt)  \
++	osl_pkt_tofwder(((osl_t *)osh), (void *)(skbs), (skb_cnt))
++
++/* Account for packets received from downstream forwarder. */
++#if defined(BCMDBG_CTRACE) /* pkt logging */
++extern void osl_pkt_frmfwder(osl_t *osh, void *skbs, int skb_cnt,
++                             int line, char *file);
++#define PKTFRMFWDER(osh, skbs, skb_cnt) \
++	osl_pkt_frmfwder(((osl_t *)osh), (void *)(skbs), (skb_cnt), \
++	                 __LINE__, __FILE__)
++#else  /* ! (BCMDBG_PKT || BCMDBG_CTRACE) */
++extern void osl_pkt_frmfwder(osl_t *osh, void *skbs, int skb_cnt);
++#define PKTFRMFWDER(osh, skbs, skb_cnt) \
++	osl_pkt_frmfwder(((osl_t *)osh), (void *)(skbs), (skb_cnt))
++#endif 
++
++
++/** GMAC Forwarded packet tagging for reduced cache flush/invalidate.
++ * In FWDERBUF tagged packet, only FWDER_PKTMAPSZ amount of data would have
++ * been accessed in the GMAC forwarder. This may be used to limit the number of
++ * cachelines that need to be flushed or invalidated.
++ * Packets sent to the DHD from a GMAC forwarder will be tagged w/ FWDERBUF.
++ * DHD may clear the FWDERBUF tag, if more than FWDER_PKTMAPSZ was accessed.
++ * Likewise, a debug print of a packet payload in say the ethernet driver needs
++ * to be accompanied with a clear of the FWDERBUF tag.
++ */
++
++/** Forwarded packets, have a GMAC_FWDER_HWRXOFF sized rx header (etc.h) */
++#define FWDER_HWRXOFF       (18)
++
++/** Maximum amount of a pkt data that a downstream forwarder (GMAC) may have
++ * read into the L1 cache (not dirty). This may be used in reduced cache ops.
++ *
++ * Max 44: ET HWRXOFF[18] + BRCMHdr[4] + EtherHdr[14] + VlanHdr[4] + IP[4]
++ * Min 32: GMAC_FWDER_HWRXOFF[18] + EtherHdr[14]
++ */
++#define FWDER_MINMAPSZ      (FWDER_HWRXOFF + 14)
++#define FWDER_MAXMAPSZ      (FWDER_HWRXOFF + 4 + 14 + 4 + 4)
++#define FWDER_PKTMAPSZ      (FWDER_MINMAPSZ)
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
++
++#define FWDERBUF            (1 << 4)
++#define PKTSETFWDERBUF(osh, skb) \
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->pktc_flags |= FWDERBUF); \
++	 })
++#define PKTCLRFWDERBUF(osh, skb) \
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->pktc_flags &= (~FWDERBUF)); \
++	 })
++#define PKTISFWDERBUF(osh, skb) \
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->pktc_flags & FWDERBUF); \
++	 })
++
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
++
++#define FWDERBUF	        (1 << 20)
++#define PKTSETFWDERBUF(osh, skb) \
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->mac_len |= FWDERBUF); \
++	 })
++#define PKTCLRFWDERBUF(osh, skb)  \
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->mac_len &= (~FWDERBUF)); \
++	 })
++#define PKTISFWDERBUF(osh, skb) \
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->mac_len & FWDERBUF); \
++	 })
++
++#else /* 2.6.22 */
++
++#define FWDERBUF            (1 << 4)
++#define PKTSETFWDERBUF(osh, skb)  \
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->__unused |= FWDERBUF); \
++	 })
++#define PKTCLRFWDERBUF(osh, skb)  \
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->__unused &= (~FWDERBUF)); \
++	 })
++#define PKTISFWDERBUF(osh, skb) \
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->__unused & FWDERBUF); \
++	 })
++
++#endif /* 2.6.22 */
++
++#else  /* ! BCM_GMAC3 */
++
++#define PKTSETFWDERBUF(osh, skb)  ({ BCM_REFERENCE(osh); BCM_REFERENCE(skb); })
++#define PKTCLRFWDERBUF(osh, skb)  ({ BCM_REFERENCE(osh); BCM_REFERENCE(skb); })
++#define PKTISFWDERBUF(osh, skb)   ({ BCM_REFERENCE(osh); BCM_REFERENCE(skb); FALSE;})
++
++#endif /* ! BCM_GMAC3 */
++
++
++#ifdef HNDCTF
++/* For broadstream iqos */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
++#define	TOBR		(1 << 5)
++#define	PKTSETTOBR(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->pktc_flags |= TOBR); \
++	 })
++#define	PKTCLRTOBR(osh, skb)	\
++	({ \
++	 BCM_REFERENCE(osh); \
++	 (((struct sk_buff*)(skb))->pktc_flags &= (~TOBR)); \
++	 })
++#define	PKTISTOBR(skb)	(((struct sk_buff*)(skb))->pktc_flags & TOBR)
++#define	PKTSETCTFIPCTXIF(skb, ifp)	(((struct sk_buff*)(skb))->ctf_ipc_txif = ifp)
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
++#define	PKTSETTOBR(osh, skb)	({BCM_REFERENCE(osh); BCM_REFERENCE(skb);})
++#define	PKTCLRTOBR(osh, skb)	({BCM_REFERENCE(osh); BCM_REFERENCE(skb);})
++#define	PKTISTOBR(skb)	({BCM_REFERENCE(skb); FALSE;})
++#define	PKTSETCTFIPCTXIF(skb, ifp)	({BCM_REFERENCE(skb); BCM_REFERENCE(ifp);})
++#else /* 2.6.22 */
++#define	PKTSETTOBR(osh, skb)	({BCM_REFERENCE(osh); BCM_REFERENCE(skb);})
++#define	PKTCLRTOBR(osh, skb)	({BCM_REFERENCE(osh); BCM_REFERENCE(skb);})
++#define	PKTISTOBR(skb)	({BCM_REFERENCE(skb); FALSE;})
++#define	PKTSETCTFIPCTXIF(skb, ifp)	({BCM_REFERENCE(skb); BCM_REFERENCE(ifp);})
++#endif /* 2.6.22 */
++#else /* HNDCTF */
++#define	PKTSETTOBR(osh, skb)	({BCM_REFERENCE(osh); BCM_REFERENCE(skb);})
++#define	PKTCLRTOBR(osh, skb)	({BCM_REFERENCE(osh); BCM_REFERENCE(skb);})
++#define	PKTISTOBR(skb)	({BCM_REFERENCE(skb); FALSE;})
++#endif /* HNDCTF */
++
++
++#ifdef BCMFA
++#ifdef BCMFA_HW_HASH
++#define PKTSETFAHIDX(skb, idx)	(((struct sk_buff*)(skb))->napt_idx = idx)
++#else
++#define PKTSETFAHIDX(skb, idx)	({BCM_REFERENCE(skb); BCM_REFERENCE(idx);})
++#endif /* BCMFA_SW_HASH */
++#define PKTGETFAHIDX(skb)	(((struct sk_buff*)(skb))->napt_idx)
++#define PKTSETFADEV(skb, imp)	(((struct sk_buff*)(skb))->dev = imp)
++#define PKTSETRXDEV(skb)	(((struct sk_buff*)(skb))->rxdev = ((struct sk_buff*)(skb))->dev)
++
++#define	AUX_TCP_FIN_RST	(1 << 0)
++#define	AUX_FREED	(1 << 1)
++#define PKTSETFAAUX(skb)	(((struct sk_buff*)(skb))->napt_flags |= AUX_TCP_FIN_RST)
++#define	PKTCLRFAAUX(skb)	(((struct sk_buff*)(skb))->napt_flags &= (~AUX_TCP_FIN_RST))
++#define	PKTISFAAUX(skb)		(((struct sk_buff*)(skb))->napt_flags & AUX_TCP_FIN_RST)
++#define PKTSETFAFREED(skb)	(((struct sk_buff*)(skb))->napt_flags |= AUX_FREED)
++#define	PKTCLRFAFREED(skb)	(((struct sk_buff*)(skb))->napt_flags &= (~AUX_FREED))
++#define	PKTISFAFREED(skb)	(((struct sk_buff*)(skb))->napt_flags & AUX_FREED)
++#define	PKTISFABRIDGED(skb)	PKTISFAAUX(skb)
++#else
++#define	PKTISFAAUX(skb)		({BCM_REFERENCE(skb); FALSE;})
++#define	PKTISFABRIDGED(skb)	({BCM_REFERENCE(skb); FALSE;})
++#define	PKTISFAFREED(skb)	({BCM_REFERENCE(skb); FALSE;})
++
++#define	PKTCLRFAAUX(skb)	BCM_REFERENCE(skb)
++#define PKTSETFAFREED(skb)	BCM_REFERENCE(skb)
++#define	PKTCLRFAFREED(skb)	BCM_REFERENCE(skb)
++#endif /* BCMFA */
++
++#if defined(BCM_OBJECT_TRACE)
++extern void osl_pktfree(osl_t *osh, void *skb, bool send, int line, const char *caller);
++#else
++extern void osl_pktfree(osl_t *osh, void *skb, bool send);
++#endif /* BCM_OBJECT_TRACE */
++extern void *osl_pktget_static(osl_t *osh, uint len);
++extern void osl_pktfree_static(osl_t *osh, void *skb, bool send);
++extern void osl_pktclone(osl_t *osh, void **pkt);
++
++#ifdef BCMDBG_CTRACE
++#define PKT_CTRACE_DUMP(osh, b)	osl_ctrace_dump((osh), (b))
++extern void *osl_pktget(osl_t *osh, uint len, int line, char *file);
++extern void *osl_pkt_frmnative(osl_t *osh, void *skb, int line, char *file);
++extern int osl_pkt_is_frmnative(osl_t *osh, struct sk_buff *pkt);
++extern void *osl_pktdup(osl_t *osh, void *skb, int line, char *file);
++struct bcmstrbuf;
++extern void osl_ctrace_dump(osl_t *osh, struct bcmstrbuf *b);
++#else
++#ifdef BCM_OBJECT_TRACE
++extern void *osl_pktget(osl_t *osh, uint len, int line, const char *caller);
++extern void *osl_pktdup(osl_t *osh, void *skb, int line, const char *caller);
++#else
++extern void *osl_pktget(osl_t *osh, uint len);
++extern void *osl_pktdup(osl_t *osh, void *skb);
++#endif /* BCM_OBJECT_TRACE */
++extern void *osl_pkt_frmnative(osl_t *osh, void *skb);
++#endif /* BCMDBG_CTRACE */
++extern struct sk_buff *osl_pkt_tonative(osl_t *osh, void *pkt);
++#ifdef BCMDBG_CTRACE
++#define PKTFRMNATIVE(osh, skb)  osl_pkt_frmnative(((osl_t *)osh), \
++				(struct sk_buff*)(skb), __LINE__, __FILE__)
++#define	PKTISFRMNATIVE(osh, skb) osl_pkt_is_frmnative((osl_t *)(osh), (struct sk_buff *)(skb))
++#else
++#define PKTFRMNATIVE(osh, skb)	osl_pkt_frmnative(((osl_t *)osh), (struct sk_buff*)(skb))
++#endif /* BCMDBG_CTRACE */
++#define PKTTONATIVE(osh, pkt)		osl_pkt_tonative((osl_t *)(osh), (pkt))
++
++#define	PKTLINK(skb)			(((struct sk_buff*)(skb))->prev)
++#define	PKTSETLINK(skb, x)		(((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
++#define	PKTPRIO(skb)			(((struct sk_buff*)(skb))->priority)
++#define	PKTSETPRIO(skb, x)		(((struct sk_buff*)(skb))->priority = (x))
++#define PKTSUMNEEDED(skb)		(((struct sk_buff*)(skb))->ip_summed == CHECKSUM_HW)
++#define PKTSETSUMGOOD(skb, x)		(((struct sk_buff*)(skb))->ip_summed = \
++						((x) ? CHECKSUM_UNNECESSARY : CHECKSUM_NONE))
++/* PKTSETSUMNEEDED and PKTSUMGOOD are not possible because skb->ip_summed is overloaded */
++#define PKTSHARED(skb)                  (((struct sk_buff*)(skb))->cloned)
++
++#ifdef CONFIG_NF_CONNTRACK_MARK
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++#define PKTMARK(p)                     (((struct sk_buff *)(p))->mark)
++#define PKTSETMARK(p, m)               ((struct sk_buff *)(p))->mark = (m)
++#else /* !2.6.0 */
++#define PKTMARK(p)                     (((struct sk_buff *)(p))->nfmark)
++#define PKTSETMARK(p, m)               ((struct sk_buff *)(p))->nfmark = (m)
++#endif /* 2.6.0 */
++#else /* CONFIG_NF_CONNTRACK_MARK */
++#define PKTMARK(p)                     0
++#define PKTSETMARK(p, m)
++#endif /* CONFIG_NF_CONNTRACK_MARK */
++
++#define PKTALLOCED(osh)		osl_pktalloced(osh)
++extern uint osl_pktalloced(osl_t *osh);
++
++#define OSL_RAND()		osl_rand()
++extern uint32 osl_rand(void);
++
++#if !defined(BCM_SECURE_DMA)
++#define	DMA_MAP(osh, va, size, direction, p, dmah) \
++	osl_dma_map((osh), (va), (size), (direction), (p), (dmah))
++#endif /* !(defined(BCM_SECURE_DMA)) */
++
++#ifdef PKTC
++/* Use 8 bytes of skb tstamp field to store below info */
++struct chain_node {
++	struct sk_buff	*link;
++	unsigned int	flags:3, pkts:9, bytes:20;
++};
++
++#define CHAIN_NODE(skb)		((struct chain_node*)(((struct sk_buff*)skb)->pktc_cb))
++
++#define	PKTCSETATTR(s, f, p, b)	({CHAIN_NODE(s)->flags = (f); CHAIN_NODE(s)->pkts = (p); \
++	                         CHAIN_NODE(s)->bytes = (b);})
++#define	PKTCCLRATTR(s)		({CHAIN_NODE(s)->flags = CHAIN_NODE(s)->pkts = \
++	                         CHAIN_NODE(s)->bytes = 0;})
++#define	PKTCGETATTR(s)		(CHAIN_NODE(s)->flags << 29 | CHAIN_NODE(s)->pkts << 20 | \
++	                         CHAIN_NODE(s)->bytes)
++#define	PKTCCNT(skb)		(CHAIN_NODE(skb)->pkts)
++#define	PKTCLEN(skb)		(CHAIN_NODE(skb)->bytes)
++#define	PKTCGETFLAGS(skb)	(CHAIN_NODE(skb)->flags)
++#define	PKTCSETFLAGS(skb, f)	(CHAIN_NODE(skb)->flags = (f))
++#define	PKTCCLRFLAGS(skb)	(CHAIN_NODE(skb)->flags = 0)
++#define	PKTCFLAGS(skb)		(CHAIN_NODE(skb)->flags)
++#define	PKTCSETCNT(skb, c)	(CHAIN_NODE(skb)->pkts = (c))
++#define	PKTCINCRCNT(skb)	(CHAIN_NODE(skb)->pkts++)
++#define	PKTCADDCNT(skb, c)	(CHAIN_NODE(skb)->pkts += (c))
++#define	PKTCSETLEN(skb, l)	(CHAIN_NODE(skb)->bytes = (l))
++#define	PKTCADDLEN(skb, l)	(CHAIN_NODE(skb)->bytes += (l))
++#define	PKTCSETFLAG(skb, fb)	(CHAIN_NODE(skb)->flags |= (fb))
++#define	PKTCCLRFLAG(skb, fb)	(CHAIN_NODE(skb)->flags &= ~(fb))
++#define	PKTCLINK(skb)		(CHAIN_NODE(skb)->link)
++#define	PKTSETCLINK(skb, x)	(CHAIN_NODE(skb)->link = (struct sk_buff*)(x))
++#define FOREACH_CHAINED_PKT(skb, nskb) \
++	for (; (skb) != NULL; (skb) = (nskb)) \
++		if ((nskb) = (PKTISCHAINED(skb) ? PKTCLINK(skb) : NULL), \
++		    PKTSETCLINK((skb), NULL), 1)
++#define	PKTCFREE(osh, skb, send) \
++do { \
++	void *nskb; \
++	ASSERT((skb) != NULL); \
++	FOREACH_CHAINED_PKT((skb), nskb) { \
++		PKTCLRCHAINED((osh), (skb)); \
++		PKTCCLRFLAGS((skb)); \
++		PKTFREE((osh), (skb), (send)); \
++	} \
++} while (0)
++#define PKTCENQTAIL(h, t, p) \
++do { \
++	if ((t) == NULL) { \
++		(h) = (t) = (p); \
++	} else { \
++		PKTSETCLINK((t), (p)); \
++		(t) = (p); \
++	} \
++} while (0)
++#endif /* PKTC */
++
++#else /* ! BCMDRIVER */
++
++
++/* ASSERT */
++	#define ASSERT(exp)	do {} while (0)
++
++/* MALLOC and MFREE */
++#define MALLOC(o, l) malloc(l)
++#define MFREE(o, p, l) free(p)
++#include <stdlib.h>
++
++/* str* and mem* functions */
++#include <string.h>
++
++/* *printf functions */
++#include <stdio.h>
++
++/* bcopy, bcmp, and bzero */
++extern void bcopy(const void *src, void *dst, size_t len);
++extern int bcmp(const void *b1, const void *b2, size_t len);
++extern void bzero(void *b, size_t len);
++#endif /* ! BCMDRIVER */
++
++/* Current STB 7445D1 doesn't use ACP and it is non-coherrent.
++ * Adding these dummy values for build apss only
++ * When we revisit need to change these.
++ */
++#if defined(STBLINUX)
++
++#if defined(__ARM_ARCH_7A__)
++#define ACP_WAR_ENAB() 0
++#define ACP_WIN_LIMIT 1
++#define arch_is_coherent() 0
++#endif /* __ARM_ARCH_7A__ */
++
++#endif /* STBLINUX */
++
++#ifdef BCM_SECURE_DMA
++
++#define	SECURE_DMA_MAP(osh, va, size, direction, p, dmah, pcma, offset) \
++	osl_sec_dma_map((osh), (va), (size), (direction), (p), (dmah), (pcma), (offset))
++#define	SECURE_DMA_DD_MAP(osh, va, size, direction, p, dmah) \
++	osl_sec_dma_dd_map((osh), (va), (size), (direction), (p), (dmah))
++#define	SECURE_DMA_MAP_TXMETA(osh, va, size, direction, p, dmah, pcma) \
++	osl_sec_dma_map_txmeta((osh), (va), (size), (direction), (p), (dmah), (pcma))
++#define	SECURE_DMA_UNMAP(osh, pa, size, direction, p, dmah, pcma, offset) \
++	osl_sec_dma_unmap((osh), (pa), (size), (direction), (p), (dmah), (pcma), (offset))
++#define	SECURE_DMA_UNMAP_ALL(osh, pcma) \
++	osl_sec_dma_unmap_all((osh), (pcma))
++
++#define DMA_MAP(osh, va, size, direction, p, dmah)
++
++typedef struct sec_cma_info {
++	struct sec_mem_elem *sec_alloc_list;
++	struct sec_mem_elem *sec_alloc_list_tail;
++} sec_cma_info_t;
++
++#if defined(__ARM_ARCH_7A__)
++#define CMA_BUFSIZE_4K	4096
++#define CMA_BUFSIZE_2K	2048
++#define CMA_BUFSIZE_512	512
++
++#define	CMA_BUFNUM		2048
++#define SEC_CMA_COHERENT_BLK 0x8000 /* 32768 */
++#define SEC_CMA_COHERENT_MAX 278
++#define CMA_DMA_DESC_MEMBLOCK	(SEC_CMA_COHERENT_BLK * SEC_CMA_COHERENT_MAX)
++#define CMA_DMA_DATA_MEMBLOCK	(CMA_BUFSIZE_4K*CMA_BUFNUM)
++#define	CMA_MEMBLOCK		(CMA_DMA_DESC_MEMBLOCK + CMA_DMA_DATA_MEMBLOCK)
++#define CONT_REGION	0x02		/* Region CMA */
++#else
++#define CONT_REGION	0x00		/* To access the MIPs mem, Not yet... */
++#endif /* !defined __ARM_ARCH_7A__ */
++
++#define SEC_DMA_ALIGN	(1<<16)
++typedef struct sec_mem_elem {
++	size_t			size;
++	int				direction;
++	phys_addr_t		pa_cma;     /**< physical  address */
++	void			*va;        /**< virtual address of driver pkt */
++	dma_addr_t		dma_handle; /**< bus address assign by linux */
++	void			*vac;       /**< virtual address of cma buffer */
++	struct page *pa_cma_page;	/* phys to page address */
++	struct	sec_mem_elem	*next;
++} sec_mem_elem_t;
++
++extern dma_addr_t osl_sec_dma_map(osl_t *osh, void *va, uint size, int direction, void *p,
++	hnddma_seg_map_t *dmah, void *ptr_cma_info, uint offset);
++extern dma_addr_t osl_sec_dma_dd_map(osl_t *osh, void *va, uint size, int direction, void *p,
++	hnddma_seg_map_t *dmah);
++extern dma_addr_t osl_sec_dma_map_txmeta(osl_t *osh, void *va, uint size,
++  int direction, void *p, hnddma_seg_map_t *dmah, void *ptr_cma_info);
++extern void osl_sec_dma_unmap(osl_t *osh, dma_addr_t dma_handle, uint size, int direction,
++	void *p, hnddma_seg_map_t *map, void *ptr_cma_info, uint offset);
++extern void osl_sec_dma_unmap_all(osl_t *osh, void *ptr_cma_info);
++
++#endif /* BCM_SECURE_DMA */
++
++typedef struct sk_buff_head PKT_LIST;
++#define PKTLIST_INIT(x)		skb_queue_head_init((x))
++#define PKTLIST_ENQ(x, y)	skb_queue_head((struct sk_buff_head *)(x), (struct sk_buff *)(y))
++#define PKTLIST_DEQ(x)		skb_dequeue((struct sk_buff_head *)(x))
++#define PKTLIST_UNLINK(x, y)	skb_unlink((struct sk_buff *)(y), (struct sk_buff_head *)(x))
++#define PKTLIST_FINI(x)		skb_queue_purge((struct sk_buff_head *)(x))
++
++#ifdef REPORT_FATAL_TIMEOUTS
++typedef struct osl_timer {
++	struct timer_list *timer;
++	bool   set;
++} osl_timer_t;
++
++typedef void (*linux_timer_fn)(ulong arg);
++
++extern osl_timer_t * osl_timer_init(osl_t *osh, const char *name, void (*fn)(void *arg), void *arg);
++extern void osl_timer_add(osl_t *osh, osl_timer_t *t, uint32 ms, bool periodic);
++extern void osl_timer_update(osl_t *osh, osl_timer_t *t, uint32 ms, bool periodic);
++extern bool osl_timer_del(osl_t *osh, osl_timer_t *t);
++#endif
++
++typedef struct osl_timespec {
++	time64_t	tv_sec;			/* seconds */
++	__kernel_suseconds_t	tv_usec;	/* microseconds */
++	long		tv_nsec;		/* nanoseconds */
++} osl_timespec_t;
++extern void osl_do_gettimeofday(struct osl_timespec *ts);
++extern void osl_get_monotonic_boottime(struct osl_timespec *ts);
++
++#endif	/* _linux_osl_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/linuxver.h b/module_drivers/drivers/net/wireless/bcmdhd/include/linuxver.h
+new file mode 100644
+index 000000000..d96d09365
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/linuxver.h
+@@ -0,0 +1,812 @@
++/*
++ * Linux-specific abstractions to gain some independence from linux kernel versions.
++ * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: linuxver.h 646721 2016-06-30 12:36:41Z $
++ */
++
++#ifndef _linuxver_h_
++#define _linuxver_h_
++
++#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wunused-but-set-variable"
++#pragma GCC diagnostic ignored "-Wunused-but-set-parameter"
++#endif
++
++#include <typedefs.h>
++#include <linux/version.h>
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
++#include <linux/config.h>
++#else
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33))
++#include <generated/autoconf.h>
++#else
++#include <linux/autoconf.h>
++#endif
++#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
++#include <linux/kconfig.h>
++#endif
++#include <linux/module.h>
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0))
++/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
++#ifdef __UNDEF_NO_VERSION__
++#undef __NO_VERSION__
++#else
++#define __NO_VERSION__
++#endif
++#endif	/* LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0) */
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)
++#define module_param(_name_, _type_, _perm_)	MODULE_PARM(_name_, "i")
++#define module_param_string(_name_, _string_, _size_, _perm_) \
++		MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
++#endif
++
++/* linux/malloc.h is deprecated, use linux/slab.h instead. */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 9))
++#include <linux/malloc.h>
++#else
++#include <linux/slab.h>
++#endif
++
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/mm.h>
++#include <linux/string.h>
++#include <linux/pci.h>
++#include <linux/interrupt.h>
++#include <linux/kthread.h>
++#include <linux/netdevice.h>
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++#include <linux/semaphore.h>
++#else
++#include <asm/semaphore.h>
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28))
++#undef IP_TOS
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)) */
++#include <asm/io.h>
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
++#include <linux/workqueue.h>
++#else
++#include <linux/tqueue.h>
++#ifndef work_struct
++#define work_struct tq_struct
++#endif
++#ifndef INIT_WORK
++#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
++#endif
++#ifndef schedule_work
++#define schedule_work(_work) schedule_task((_work))
++#endif
++#ifndef flush_scheduled_work
++#define flush_scheduled_work() flush_scheduled_tasks()
++#endif
++#endif	/* LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++#define DAEMONIZE(a)	do { \
++		allow_signal(SIGKILL);	\
++		allow_signal(SIGTERM);	\
++	} while (0)
++#elif ((LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) && \
++	(LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)))
++#define DAEMONIZE(a) daemonize(a); \
++	allow_signal(SIGKILL); \
++	allow_signal(SIGTERM);
++#else /* Linux 2.4 (w/o preemption patch) */
++#define RAISE_RX_SOFTIRQ() \
++	cpu_raise_softirq(smp_processor_id(), NET_RX_SOFTIRQ)
++#define DAEMONIZE(a) daemonize(); \
++	do { if (a) \
++		strncpy(current->comm, a, MIN(sizeof(current->comm), (strlen(a)))); \
++	} while (0);
++#endif /* LINUX_VERSION_CODE  */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
++#define	MY_INIT_WORK(_work, _func)	INIT_WORK(_work, _func)
++#else
++#define	MY_INIT_WORK(_work, _func)	INIT_WORK(_work, _func, _work)
++#if !(LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 18) && defined(RHEL_MAJOR) && \
++	(RHEL_MAJOR == 5))
++/* Exclude RHEL 5 */
++typedef void (*work_func_t)(void *work);
++#endif
++#endif	/* >= 2.6.20 */
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
++/* Some distributions have their own 2.6.x compatibility layers */
++#ifndef IRQ_NONE
++typedef void irqreturn_t;
++#define IRQ_NONE
++#define IRQ_HANDLED
++#define IRQ_RETVAL(x)
++#endif
++#else
++typedef irqreturn_t(*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
++#endif	/* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0) */
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)
++#define IRQF_SHARED	SA_SHIRQ
++#endif /* < 2.6.18 */
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 17)
++#ifdef	CONFIG_NET_RADIO
++#define	CONFIG_WIRELESS_EXT
++#endif
++#endif	/* < 2.6.17 */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 67)
++#define MOD_INC_USE_COUNT
++#define MOD_DEC_USE_COUNT
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 67) */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)
++#include <linux/sched.h>
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++#include <linux/sched/rt.h>
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)
++#include <net/lib80211.h>
++#endif
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)
++#include <linux/ieee80211.h>
++#else
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 14)
++#include <net/ieee80211.h>
++#endif
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30) */
++
++
++#ifndef __exit
++#define __exit
++#endif
++#ifndef __devexit
++#define __devexit
++#endif
++#ifndef __devinit
++#  if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
++#    define __devinit	__init
++#  else
++/* All devices are hotpluggable since linux 3.8.0 */
++#    define __devinit
++#  endif
++#endif /* !__devinit */
++#ifndef __devinitdata
++#define __devinitdata
++#endif
++#ifndef __devexit_p
++#define __devexit_p(x)	x
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))
++
++#define pci_get_drvdata(dev)		(dev)->sysdata
++#define pci_set_drvdata(dev, value)	(dev)->sysdata = (value)
++
++/*
++ * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
++ */
++
++struct pci_device_id {
++	unsigned int vendor, device;		/* Vendor and device ID or PCI_ANY_ID */
++	unsigned int subvendor, subdevice;	/* Subsystem ID's or PCI_ANY_ID */
++	unsigned int class, class_mask;		/* (class,subclass,prog-if) triplet */
++	unsigned long driver_data;		/* Data private to the driver */
++};
++
++struct pci_driver {
++	struct list_head node;
++	char *name;
++	const struct pci_device_id *id_table;	/* NULL if wants all devices */
++	int (*probe)(struct pci_dev *dev,
++	             const struct pci_device_id *id); /* New device inserted */
++	void (*remove)(struct pci_dev *dev);	/* Device removed (NULL if not a hot-plug
++						 * capable driver)
++						 */
++	void (*suspend)(struct pci_dev *dev);	/* Device suspended */
++	void (*resume)(struct pci_dev *dev);	/* Device woken up */
++};
++
++#define MODULE_DEVICE_TABLE(type, name)
++#define PCI_ANY_ID (~0)
++
++/* compatpci.c */
++#define pci_module_init pci_register_driver
++extern int pci_register_driver(struct pci_driver *drv);
++extern void pci_unregister_driver(struct pci_driver *drv);
++
++#endif /* PCI registration */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18))
++#define pci_module_init pci_register_driver
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18))
++#ifdef MODULE
++#define module_init(x) int init_module(void) { return x(); }
++#define module_exit(x) void cleanup_module(void) { x(); }
++#else
++#define module_init(x)	__initcall(x);
++#define module_exit(x)	__exitcall(x);
++#endif
++#endif	/* LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18) */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31)
++#define WL_USE_NETDEV_OPS
++#else
++#undef WL_USE_NETDEV_OPS
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31)) && defined(CONFIG_RFKILL)
++#define WL_CONFIG_RFKILL
++#else
++#undef WL_CONFIG_RFKILL
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 48))
++#define list_for_each(pos, head) \
++	for (pos = (head)->next; pos != (head); pos = pos->next)
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 13))
++#define pci_resource_start(dev, bar)	((dev)->base_address[(bar)])
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 44))
++#define pci_resource_start(dev, bar)	((dev)->resource[(bar)].start)
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 23))
++#define pci_enable_device(dev) do { } while (0)
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 14))
++#define net_device device
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 42))
++
++/*
++ * DMA mapping
++ *
++ * See linux/Documentation/DMA-mapping.txt
++ */
++
++#ifndef PCI_DMA_TODEVICE
++#define	PCI_DMA_TODEVICE	1
++#define	PCI_DMA_FROMDEVICE	2
++#endif
++
++typedef u32 dma_addr_t;
++
++/* Pure 2^n version of get_order */
++static inline int get_order(unsigned long size)
++{
++	int order;
++
++	size = (size-1) >> (PAGE_SHIFT-1);
++	order = -1;
++	do {
++		size >>= 1;
++		order++;
++	} while (size);
++	return order;
++}
++
++static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
++                                         dma_addr_t *dma_handle)
++{
++	void *ret;
++	int gfp = GFP_ATOMIC | GFP_DMA;
++
++	ret = (void *)__get_free_pages(gfp, get_order(size));
++
++	if (ret != NULL) {
++		memset(ret, 0, size);
++		*dma_handle = virt_to_bus(ret);
++	}
++	return ret;
++}
++static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
++                                       void *vaddr, dma_addr_t dma_handle)
++{
++	free_pages((unsigned long)vaddr, get_order(size));
++}
++#define pci_map_single(cookie, address, size, dir)	virt_to_bus(address)
++#define pci_unmap_single(cookie, address, size, dir)
++
++#endif /* DMA mapping */
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0)
++
++typedef struct timer_list timer_list_compat_t;
++
++#define init_timer_compat(timer_compat, cb, priv) \
++	init_timer(timer_compat); \
++	(timer_compat)->data = (ulong)priv; \
++	(timer_compat)->function = cb
++#define timer_set_private(timer_compat, priv) (timer_compat)->data = (ulong)priv
++#define timer_expires(timer_compat) (timer_compat)->expires
++
++#else /* LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0) */
++
++typedef struct timer_list_compat {
++	struct timer_list timer;
++	void *arg;
++	void (*callback)(ulong arg);
++} timer_list_compat_t;
++
++extern void timer_cb_compat(struct timer_list *tl);
++
++#define init_timer_compat(timer_compat, cb, priv) \
++	(timer_compat)->arg = priv; \
++	(timer_compat)->callback = cb; \
++	timer_setup(&(timer_compat)->timer, timer_cb_compat, 0);
++#define timer_set_private(timer_compat, priv) (timer_compat)->arg = priv
++#define timer_expires(timer_compat) (timer_compat)->timer.expires
++
++#define _del_timer_sync(t) del_timer_sync(&((t)->timer))
++#define _del_timer(t) del_timer(&((t)->timer))
++#define timer_pending(t) timer_pending(&((t)->timer))
++#define add_timer(t) add_timer(&((t)->timer))
++#define mod_timer(t, j) mod_timer(&((t)->timer), j)
++
++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0) */
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 43))
++
++#define dev_kfree_skb_any(a)		dev_kfree_skb(a)
++#define netif_down(dev)			do { (dev)->start = 0; } while (0)
++
++/* pcmcia-cs provides its own netdevice compatibility layer */
++#ifndef _COMPAT_NETDEVICE_H
++
++/*
++ * SoftNet
++ *
++ * For pre-softnet kernels we need to tell the upper layer not to
++ * re-enter start_xmit() while we are in there. However softnet
++ * guarantees not to enter while we are in there so there is no need
++ * to do the netif_stop_queue() dance unless the transmit queue really
++ * gets stuck. This should also improve performance according to tests
++ * done by Aman Singla.
++ */
++
++#define dev_kfree_skb_irq(a)	dev_kfree_skb(a)
++#define netif_wake_queue(dev) \
++		do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while (0)
++#define netif_stop_queue(dev)	set_bit(0, &(dev)->tbusy)
++
++static inline void netif_start_queue(struct net_device *dev)
++{
++	dev->tbusy = 0;
++	dev->interrupt = 0;
++	dev->start = 1;
++}
++
++#define netif_queue_stopped(dev)	(dev)->tbusy
++#define netif_running(dev)		(dev)->start
++
++#endif /* _COMPAT_NETDEVICE_H */
++
++#define netif_device_attach(dev)	netif_start_queue(dev)
++#define netif_device_detach(dev)	netif_stop_queue(dev)
++
++/* 2.4.x renamed bottom halves to tasklets */
++#define tasklet_struct				tq_struct
++static inline void tasklet_schedule(struct tasklet_struct *tasklet)
++{
++	queue_task(tasklet, &tq_immediate);
++	mark_bh(IMMEDIATE_BH);
++}
++
++static inline void tasklet_init(struct tasklet_struct *tasklet,
++                                void (*func)(unsigned long),
++                                unsigned long data)
++{
++	tasklet->next = NULL;
++	tasklet->sync = 0;
++	tasklet->routine = (void (*)(void *))func;
++	tasklet->data = (void *)data;
++}
++#define tasklet_kill(tasklet)	{ do {} while (0); }
++
++/* 2.4.x introduced del_timer_sync() */
++#define del_timer_sync(timer) del_timer(timer)
++
++#else
++
++#define netif_down(dev)
++
++#endif /* SoftNet */
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3))
++
++/*
++ * Emit code to initialise a tq_struct's routine and data pointers
++ */
++#define PREPARE_TQUEUE(_tq, _routine, _data)			\
++	do {							\
++		(_tq)->routine = _routine;			\
++		(_tq)->data = _data;				\
++	} while (0)
++
++/*
++ * Emit code to initialise all of a tq_struct
++ */
++#define INIT_TQUEUE(_tq, _routine, _data)			\
++	do {							\
++		INIT_LIST_HEAD(&(_tq)->list);			\
++		(_tq)->sync = 0;				\
++		PREPARE_TQUEUE((_tq), (_routine), (_data));	\
++	} while (0)
++
++#endif	/* LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3) */
++
++/* Power management related macro & routines */
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 9)
++#define	PCI_SAVE_STATE(a, b)	pci_save_state(a)
++#define	PCI_RESTORE_STATE(a, b)	pci_restore_state(a)
++#else
++#define	PCI_SAVE_STATE(a, b)	pci_save_state(a, b)
++#define	PCI_RESTORE_STATE(a, b)	pci_restore_state(a, b)
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 6))
++static inline int
++pci_save_state(struct pci_dev *dev, u32 *buffer)
++{
++	int i;
++	if (buffer) {
++		for (i = 0; i < 16; i++)
++			pci_read_config_dword(dev, i * 4, &buffer[i]);
++	}
++	return 0;
++}
++
++static inline int
++pci_restore_state(struct pci_dev *dev, u32 *buffer)
++{
++	int i;
++
++	if (buffer) {
++		for (i = 0; i < 16; i++)
++			pci_write_config_dword(dev, i * 4, buffer[i]);
++	}
++	/*
++	 * otherwise, write the context information we know from bootup.
++	 * This works around a problem where warm-booting from Windows
++	 * combined with a D3(hot)->D0 transition causes PCI config
++	 * header data to be forgotten.
++	 */
++	else {
++		for (i = 0; i < 6; i ++)
++			pci_write_config_dword(dev,
++			                       PCI_BASE_ADDRESS_0 + (i * 4),
++			                       pci_resource_start(dev, i));
++		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
++	}
++	return 0;
++}
++#endif /* PCI power management */
++
++/* Old cp0 access macros deprecated in 2.4.19 */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 19))
++#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
++#endif
++
++/* Module refcount handled internally in 2.6.x */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
++#ifndef SET_MODULE_OWNER
++#define SET_MODULE_OWNER(dev)		do {} while (0)
++#define OLD_MOD_INC_USE_COUNT		MOD_INC_USE_COUNT
++#define OLD_MOD_DEC_USE_COUNT		MOD_DEC_USE_COUNT
++#else
++#define OLD_MOD_INC_USE_COUNT		do {} while (0)
++#define OLD_MOD_DEC_USE_COUNT		do {} while (0)
++#endif
++#else /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24) */
++#ifndef SET_MODULE_OWNER
++#define SET_MODULE_OWNER(dev)		do {} while (0)
++#endif
++#ifndef MOD_INC_USE_COUNT
++#define MOD_INC_USE_COUNT			do {} while (0)
++#endif
++#ifndef MOD_DEC_USE_COUNT
++#define MOD_DEC_USE_COUNT			do {} while (0)
++#endif
++#define OLD_MOD_INC_USE_COUNT		MOD_INC_USE_COUNT
++#define OLD_MOD_DEC_USE_COUNT		MOD_DEC_USE_COUNT
++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24) */
++
++#ifndef SET_NETDEV_DEV
++#define SET_NETDEV_DEV(net, pdev)	do {} while (0)
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))
++#ifndef HAVE_FREE_NETDEV
++#define free_netdev(dev)		kfree(dev)
++#endif
++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0) */
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
++/* struct packet_type redefined in 2.6.x */
++#define af_packet_priv			data
++#endif
++
++/* suspend args */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 11)
++#define DRV_SUSPEND_STATE_TYPE pm_message_t
++#else
++#define DRV_SUSPEND_STATE_TYPE uint32
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
++#define CHECKSUM_HW	CHECKSUM_PARTIAL
++#endif
++
++typedef struct {
++	void	*parent;  /* some external entity that the thread supposed to work for */
++	char	*proc_name;
++	struct	task_struct *p_task;
++	long	thr_pid;
++	int		prio; /* priority */
++	struct	semaphore sema;
++	int	terminated;
++	struct	completion completed;
++	spinlock_t	spinlock;
++	int		up_cnt;
++} tsk_ctl_t;
++
++
++/* requires  tsk_ctl_t tsk  argument, the caller's priv data is passed in owner ptr */
++/* note this macro assumes there may be only one context waiting on thread's completion */
++#ifdef DHD_DEBUG
++#define DBG_THR(x) printk x
++#else
++#define DBG_THR(x)
++#endif
++
++static inline bool binary_sema_down(tsk_ctl_t *tsk)
++{
++	if (down_interruptible(&tsk->sema) == 0) {
++		unsigned long flags = 0;
++		spin_lock_irqsave(&tsk->spinlock, flags);
++		if (tsk->up_cnt == 1)
++			tsk->up_cnt--;
++		else {
++			DBG_THR(("dhd_dpc_thread: Unexpected up_cnt %d\n", tsk->up_cnt));
++		}
++		spin_unlock_irqrestore(&tsk->spinlock, flags);
++		return false;
++	} else
++		return true;
++}
++
++static inline bool binary_sema_up(tsk_ctl_t *tsk)
++{
++	bool sem_up = false;
++	unsigned long flags = 0;
++
++	spin_lock_irqsave(&tsk->spinlock, flags);
++	if (tsk->up_cnt == 0) {
++		tsk->up_cnt++;
++		sem_up = true;
++	} else if (tsk->up_cnt == 1) {
++		/* dhd_sched_dpc: dpc is alread up! */
++	} else
++		DBG_THR(("dhd_sched_dpc: unexpected up cnt %d!\n", tsk->up_cnt));
++
++	spin_unlock_irqrestore(&tsk->spinlock, flags);
++
++	if (sem_up)
++		up(&tsk->sema);
++
++	return sem_up;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++#define smp_read_barrier_depends() do {} while(0)
++#define SMP_RD_BARRIER_DEPENDS(x) smp_read_barrier_depends(x)
++#else
++#define SMP_RD_BARRIER_DEPENDS(x) smp_rmb(x)
++#endif
++
++#define PROC_START(thread_func, owner, tsk_ctl, flags, name) \
++{ \
++	sema_init(&((tsk_ctl)->sema), 0); \
++	init_completion(&((tsk_ctl)->completed)); \
++	(tsk_ctl)->parent = owner; \
++	(tsk_ctl)->proc_name = name;  \
++	(tsk_ctl)->terminated = FALSE; \
++	(tsk_ctl)->p_task  = kthread_run(thread_func, tsk_ctl, (char*)name); \
++	if (IS_ERR((tsk_ctl)->p_task)) { \
++		(tsk_ctl)->thr_pid = DHD_PID_KT_INVALID; \
++		DBG_THR(("%s(): thread:%s:%lx failed\n", __FUNCTION__, \
++			(tsk_ctl)->proc_name, (tsk_ctl)->thr_pid)); \
++	} else { \
++		(tsk_ctl)->thr_pid = (tsk_ctl)->p_task->pid; \
++		spin_lock_init(&((tsk_ctl)->spinlock)); \
++		DBG_THR(("%s(): thread:%s:%lx started\n", __FUNCTION__, \
++			(tsk_ctl)->proc_name, (tsk_ctl)->thr_pid)); \
++	}; \
++}
++
++#define PROC_STOP(tsk_ctl) \
++{ \
++	(tsk_ctl)->terminated = TRUE; \
++	smp_wmb(); \
++	up(&((tsk_ctl)->sema));	\
++	wait_for_completion(&((tsk_ctl)->completed)); \
++	DBG_THR(("%s(): thread:%s:%lx terminated OK\n", __FUNCTION__, \
++			 (tsk_ctl)->proc_name, (tsk_ctl)->thr_pid)); \
++	(tsk_ctl)->thr_pid = -1; \
++}
++
++/*  ----------------------- */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
++#define KILL_PROC(nr, sig) \
++{ \
++struct task_struct *tsk; \
++struct pid *pid;    \
++pid = find_get_pid((pid_t)nr);    \
++tsk = pid_task(pid, PIDTYPE_PID);    \
++if (tsk) send_sig(sig, tsk, 1); \
++}
++#else
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && (LINUX_VERSION_CODE <= \
++	KERNEL_VERSION(2, 6, 30))
++#define KILL_PROC(pid, sig) \
++{ \
++	struct task_struct *tsk; \
++	tsk = find_task_by_vpid(pid); \
++	if (tsk) send_sig(sig, tsk, 1); \
++}
++#else
++#define KILL_PROC(pid, sig) \
++{ \
++	kill_proc(pid, sig, 1); \
++}
++#endif
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++#include <linux/time.h>
++#include <linux/wait.h>
++#else
++#include <linux/sched.h>
++
++#define __wait_event_interruptible_timeout(wq, condition, ret)		\
++do {									\
++	wait_queue_t __wait;						\
++	init_waitqueue_entry(&__wait, current);				\
++									\
++	add_wait_queue(&wq, &__wait);					\
++	for (;;) {							\
++		set_current_state(TASK_INTERRUPTIBLE);			\
++		if (condition)						\
++			break;						\
++		if (!signal_pending(current)) {				\
++			ret = schedule_timeout(ret);			\
++			if (!ret)					\
++				break;					\
++			continue;					\
++		}							\
++		ret = -ERESTARTSYS;					\
++		break;							\
++	}								\
++	current->state = TASK_RUNNING;					\
++	remove_wait_queue(&wq, &__wait);				\
++} while (0)
++
++#define wait_event_interruptible_timeout(wq, condition, timeout)	\
++({									\
++	long __ret = timeout;						\
++	if (!(condition))						\
++		__wait_event_interruptible_timeout(wq, condition, __ret); \
++	__ret;								\
++})
++
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)) */
++
++/*
++For < 2.6.24, wl creates its own netdev but doesn't
++align the priv area like the genuine alloc_netdev().
++Since netdev_priv() always gives us the aligned address, it will
++not match our unaligned address for < 2.6.24
++*/
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
++#define DEV_PRIV(dev)	(dev->priv)
++#else
++#define DEV_PRIV(dev)	netdev_priv(dev)
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20)
++#define WL_ISR(i, d, p)         wl_isr((i), (d))
++#else
++#define WL_ISR(i, d, p)         wl_isr((i), (d), (p))
++#endif  /* < 2.6.20 */
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
++#define netdev_priv(dev) dev->priv
++#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++#define CAN_SLEEP()	((!in_atomic() && !irqs_disabled()))
++#else
++#define CAN_SLEEP()	(FALSE)
++#endif
++
++#define KMALLOC_FLAG (CAN_SLEEP() ? GFP_KERNEL: GFP_ATOMIC)
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++#define RANDOM32	prandom_u32
++#else
++#define RANDOM32	random32
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++#define SRANDOM32(entropy)	prandom_seed(entropy)
++#else
++#define SRANDOM32(entropy)	srandom32(entropy)
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0) */
++
++/*
++ * Overide latest kfifo functions with
++ * older version to work on older kernels
++ */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33))
++#define kfifo_in_spinlocked(a, b, c, d)		kfifo_put(a, (u8 *)b, c)
++#define kfifo_out_spinlocked(a, b, c, d)	kfifo_get(a, (u8 *)b, c)
++#define kfifo_esize(a)				1
++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 32)) && \
++	(LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36)) &&	!defined(WL_COMPAT_WIRELESS)
++#define kfifo_in_spinlocked(a, b, c, d)		kfifo_in_locked(a, b, c, d)
++#define kfifo_out_spinlocked(a, b, c, d)	kfifo_out_locked(a, b, c, d)
++#define kfifo_esize(a)				1
++#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33)) */
++
++#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6)
++#pragma GCC diagnostic pop
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
++#include <linux/fs.h>
++static inline struct inode *file_inode(const struct file *f)
++{
++	return f->f_dentry->d_inode;
++}
++#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0)) */
++
++#endif /* _linuxver_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/miniopt.h b/module_drivers/drivers/net/wireless/bcmdhd/include/miniopt.h
+new file mode 100644
+index 000000000..672235143
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/miniopt.h
+@@ -0,0 +1,83 @@
++/*
++ * Command line options parser.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: miniopt.h 514727 2014-11-12 03:02:48Z $
++ */
++
++
++#ifndef MINI_OPT_H
++#define MINI_OPT_H
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* ---- Include Files ---------------------------------------------------- */
++
++
++/* ---- Constants and Types ---------------------------------------------- */
++
++#define MINIOPT_MAXKEY	128	/* Max options */
++typedef struct miniopt {
++
++	/* These are persistent after miniopt_init() */
++	const char* name;		/* name for prompt in error strings */
++	const char* flags;		/* option chars that take no args */
++	bool longflags;		/* long options may be flags */
++	bool opt_end;		/* at end of options (passed a "--") */
++
++	/* These are per-call to miniopt() */
++
++	int consumed;		/* number of argv entries cosumed in
++				 * the most recent call to miniopt()
++				 */
++	bool positional;
++	bool good_int;		/* 'val' member is the result of a sucessful
++				 * strtol conversion of the option value
++				 */
++	char opt;
++	char key[MINIOPT_MAXKEY];
++	char* valstr;		/* positional param, or value for the option,
++				 * or null if the option had
++				 * no accompanying value
++				 */
++	uint uval;		/* strtol translation of valstr */
++	int  val;		/* strtol translation of valstr */
++} miniopt_t;
++
++void miniopt_init(miniopt_t *t, const char* name, const char* flags, bool longflags);
++int miniopt(miniopt_t *t, char **argv);
++
++
++/* ---- Variable Externs ------------------------------------------------- */
++/* ---- Function Prototypes ---------------------------------------------- */
++
++
++#ifdef __cplusplus
++	}
++#endif
++
++#endif  /* MINI_OPT_H  */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/msgtrace.h b/module_drivers/drivers/net/wireless/bcmdhd/include/msgtrace.h
+new file mode 100644
+index 000000000..a2da1d3c7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/msgtrace.h
+@@ -0,0 +1,62 @@
++/*
++ * Trace messages sent over HBUS
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: msgtrace.h 542902 2015-03-22 23:29:48Z $
++ */
++
++#ifndef	_MSGTRACE_H
++#define	_MSGTRACE_H
++
++#ifndef _TYPEDEFS_H_
++#include <typedefs.h>
++#endif
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++
++#define MSGTRACE_VERSION 1
++
++/* Message trace header */
++typedef BWL_PRE_PACKED_STRUCT struct msgtrace_hdr {
++	uint8	version;
++	uint8   trace_type;
++#define MSGTRACE_HDR_TYPE_MSG 0
++#define MSGTRACE_HDR_TYPE_LOG 1
++	uint16	len;	/* Len of the trace */
++	uint32	seqnum;	/* Sequence number of message. Useful if the messsage has been lost
++			 * because of DMA error or a bus reset (ex: SDIO Func2)
++			 */
++	/* Msgtrace type  only */
++	uint32  discarded_bytes;  /* Number of discarded bytes because of trace overflow  */
++	uint32  discarded_printf; /* Number of discarded printf because of trace overflow */
++} BWL_POST_PACKED_STRUCT msgtrace_hdr_t;
++
++#define MSGTRACE_HDRLEN 	sizeof(msgtrace_hdr_t)
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++#endif	/* _MSGTRACE_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/nan.h b/module_drivers/drivers/net/wireless/bcmdhd/include/nan.h
+new file mode 100644
+index 000000000..4534414fb
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/nan.h
+@@ -0,0 +1,1468 @@
++/*
++ * Fundamental types and constants relating to WFA NAN
++ * (Neighbor Awareness Networking)
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: nan.h 700076 2017-05-17 14:42:22Z $
++ */
++#ifndef _NAN_H_
++#define _NAN_H_
++
++#include <typedefs.h>
++#include <802.11.h>
++
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++
++/* WiFi NAN OUI values */
++#define NAN_OUI			WFA_OUI     /* WiFi OUI */
++/* For oui_type field identifying the type and version of the NAN IE. */
++#define NAN_OUI_TYPE		0x13        /* Type/Version */
++#define NAN_AF_OUI_TYPE		0x18        /* Type/Version */
++/* IEEE 802.11 vendor specific information element. (Same as P2P_IE_ID.) */
++#define NAN_IE_ID		0xdd
++
++/* Same as P2P_PUB_AF_CATEGORY and DOT11_ACTION_CAT_PUBLIC */
++#define NAN_PUB_AF_CATEGORY	DOT11_ACTION_CAT_PUBLIC
++/* Protected dual public action frame category */
++#define NAN_PROT_DUAL_PUB_AF_CATEGORY	DOT11_ACTION_CAT_PDPA
++/* IEEE 802.11 Public Action Frame Vendor Specific. (Same as P2P_PUB_AF_ACTION.) */
++#define NAN_PUB_AF_ACTION	DOT11_PUB_ACTION_VENDOR_SPEC
++/* Number of octents in hash of service name. (Same as P2P_WFDS_HASH_LEN.) */
++#define NAN_SVC_HASH_LEN	6
++/* Size of fixed length part of nan_pub_act_frame_t before attributes. */
++#define NAN_PUB_ACT_FRAME_FIXED_LEN 6
++/* Number of octents in master rank value. */
++#define NAN_MASTER_RANK_LEN     8
++/* NAN public action frame header size */
++#define NAN_PUB_ACT_FRAME_HDR_SIZE (OFFSETOF(nan_pub_act_frame_t, data))
++/* NAN network ID */
++#define NAN_NETWORK_ID		"\x51\x6F\x9A\x01\x00\x00"
++/* Service Control Type length */
++#define NAN_SVC_CONTROL_TYPE_LEN	2
++/* Binding Bitmap length */
++#define NAN_BINDING_BITMAP_LEN		2
++/* Service Response Filter (SRF) control field masks */
++#define NAN_SRF_BLOOM_MASK		0x01
++#define NAN_SRF_INCLUDE_MASK		0x02
++#define NAN_SRF_INDEX_MASK		0x0C
++/* SRF Bloom Filter index shift */
++#define NAN_SRF_BLOOM_SHIFT	2
++#define NAN_SRF_INCLUDE_SHIFT	1
++/* Mask for CRC32 output, used in hash function for NAN bloom filter */
++#define NAN_BLOOM_CRC32_MASK	0xFFFF
++
++/* Attribute TLV header size */
++#define NAN_ATTR_ID_OFF		0
++#define NAN_ATTR_LEN_OFF	1
++#define NAN_ATTR_DATA_OFF	3
++
++#define NAN_ATTR_ID_LEN		 1u	/* ID field length */
++#define NAN_ATTR_LEN_LEN	 2u	/* Length field length */
++#define NAN_ATTR_HDR_LEN	 (NAN_ATTR_ID_LEN + NAN_ATTR_LEN_LEN)
++#define NAN_ENTRY_CTRL_LEN       1      /* Entry control field length from FAM attribute */
++#define NAN_MAP_ID_LEN           1	/* MAP ID length to signify band */
++#define NAN_OPERATING_CLASS_LEN  1	/* operating class field length from NAN FAM */
++#define NAN_CHANNEL_NUM_LEN      1	/* channel number field length 1 byte */
++
++/* NAN slot duration / period */
++#define NAN_MIN_TU		16
++#define NAN_TU_PER_DW		512
++#define NAN_MAX_DW		16
++#define NAN_MAX_TU		(NAN_MAX_DW * NAN_TU_PER_DW)
++
++#define NAN_SLOT_DUR_0TU	0
++#define NAN_SLOT_DUR_16TU	16
++#define NAN_SLOT_DUR_32TU	32
++#define NAN_SLOT_DUR_64TU	64
++#define NAN_SLOT_DUR_128TU	128
++#define NAN_SLOT_DUR_256TU	256
++#define NAN_SLOT_DUR_512TU	512
++#define NAN_SLOT_DUR_1024TU	1024
++#define NAN_SLOT_DUR_2048TU	2048
++#define NAN_SLOT_DUR_4096TU	4096
++#define NAN_SLOT_DUR_8192TU	8192
++
++#define NAN_MAP_ID_2G   2  /* NAN Further Avail Map ID for band 2.4G */
++#define NAN_MAP_ID_5G   5  /* NAN Further Avail Map ID for band 5G */
++#define NAN_MAP_NUM_IDS 2  /* Max number of NAN Further Avail Map IDs supported */
++
++/* size of ndc id */
++#define NAN_DATA_NDC_ID_SIZE 6
++
++#define NAN_AVAIL_ENTRY_LEN_RES0 7      /* Avail entry len in FAM attribute for resolution 16TU */
++#define NAN_AVAIL_ENTRY_LEN_RES1 5      /* Avail entry len in FAM attribute for resolution 32TU */
++#define NAN_AVAIL_ENTRY_LEN_RES2 4      /* Avail entry len in FAM attribute for resolution 64TU */
++
++/* Vendor-specific public action frame for NAN */
++typedef BWL_PRE_PACKED_STRUCT struct nan_pub_act_frame_s {
++	/* NAN_PUB_AF_CATEGORY 0x04 */
++	uint8 category_id;
++	/* NAN_PUB_AF_ACTION 0x09 */
++	uint8 action_field;
++	/* NAN_OUI 0x50-6F-9A */
++	uint8 oui[DOT11_OUI_LEN];
++	/* NAN_OUI_TYPE 0x13 */
++	uint8 oui_type;
++	/* One or more NAN Attributes follow */
++	uint8 data[];
++} BWL_POST_PACKED_STRUCT nan_pub_act_frame_t;
++
++/* NAN attributes as defined in the nan spec */
++enum {
++	NAN_ATTR_MASTER_IND	= 0,
++	NAN_ATTR_CLUSTER	= 1,
++	NAN_ATTR_SVC_ID_LIST    = 2,
++	NAN_ATTR_SVC_DESCRIPTOR = 3,
++	NAN_ATTR_CONN_CAP       = 4,
++	NAN_ATTR_INFRA		= 5,
++	NAN_ATTR_P2P		= 6,
++	NAN_ATTR_IBSS		= 7,
++	NAN_ATTR_MESH		= 8,
++	NAN_ATTR_FURTHER_NAN_SD = 9,
++	NAN_ATTR_FURTHER_AVAIL	= 10,
++	NAN_ATTR_COUNTRY_CODE	= 11,
++	NAN_ATTR_RANGING	= 12,
++	NAN_ATTR_CLUSTER_DISC	= 13,
++	/* nan 2.0 */
++	NAN_ATTR_SVC_DESC_EXTENSION = 14,
++	NAN_ATTR_NAN_DEV_CAP = 15,
++	NAN_ATTR_NAN_NDP = 16,
++	NAN_ATTR_NAN_NMSG = 17,
++	NAN_ATTR_NAN_AVAIL = 18,
++	NAN_ATTR_NAN_NDC = 19,
++	NAN_ATTR_NAN_NDL = 20,
++	NAN_ATTR_NAN_NDL_QOS = 21,
++	NAN_ATTR_MCAST_SCHED = 22,
++	NAN_ATTR_UNALIGN_SCHED = 23,
++	NAN_ATTR_PAGING_UCAST = 24,
++	NAN_ATTR_PAGING_MCAST = 25,
++	NAN_ATTR_RANGING_INFO = 26,
++	NAN_ATTR_RANGING_SETUP = 27,
++	NAN_ATTR_FTM_RANGE_REPORT = 28,
++	NAN_ATTR_ELEMENT_CONTAINER = 29,
++	NAN_ATTR_WLAN_INFRA_EXT = 30,
++	NAN_ATTR_EXT_P2P_OPER = 31,
++	NAN_ATTR_EXT_IBSS = 32,
++	NAN_ATTR_EXT_MESH = 33,
++	NAN_ATTR_CIPHER_SUITE_INFO = 34,
++	NAN_ATTR_SEC_CTX_ID_INFO = 35,
++	NAN_ATTR_SHARED_KEY_DESC = 36,
++	NAN_ATTR_MCAST_SCHED_CHANGE = 37,
++	NAN_ATTR_MCAST_SCHED_OWNER_CHANGE = 38,
++	NAN_ATTR_PUBLIC_AVAILABILITY = 39,
++	NAN_ATTR_SUB_SVC_ID_LIST = 40,
++	/* change NAN_ATTR_MAX_ID to max ids + 1, excluding NAN_ATTR_VENDOR_SPECIFIC.
++	 * This is used in nan_parse.c
++	 */
++	NAN_ATTR_MAX_ID		= NAN_ATTR_SUB_SVC_ID_LIST + 1,
++
++	NAN_ATTR_VENDOR_SPECIFIC = 221
++};
++
++enum wifi_nan_avail_resolution {
++	NAN_AVAIL_RES_16_TU = 0,
++	NAN_AVAIL_RES_32_TU = 1,
++	NAN_AVAIL_RES_64_TU = 2,
++	NAN_AVAIL_RES_INVALID = 255
++};
++
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_ie_s {
++	uint8	id;		/* IE ID: NAN_IE_ID 0xDD */
++	uint8	len;		/* IE length */
++	uint8	oui[DOT11_OUI_LEN]; /* NAN_OUI 50:6F:9A */
++	uint8	oui_type;	/* NAN_OUI_TYPE 0x13 */
++	uint8	attr[];	/* var len attributes */
++} BWL_POST_PACKED_STRUCT wifi_nan_ie_t;
++
++#define NAN_IE_HDR_SIZE	(OFFSETOF(wifi_nan_ie_t, attr))
++
++/* master indication record  */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_master_ind_attr_s {
++	uint8	id;
++	uint16	len;
++	uint8	master_preference;
++	uint8	random_factor;
++} BWL_POST_PACKED_STRUCT wifi_nan_master_ind_attr_t;
++
++/* cluster attr record  */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_cluster_attr_s {
++	uint8	id;
++	uint16	len;
++	uint8   amr[NAN_MASTER_RANK_LEN];
++	uint8   hop_count;
++	/* Anchor Master Beacon Transmission Time */
++	uint32  ambtt;
++} BWL_POST_PACKED_STRUCT wifi_nan_cluster_attr_t;
++
++/*  container for service ID records  */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_svc_id_attr_s {
++	uint8	id;
++	uint16	len;
++	uint8	svcid[0]; /* 6*len of srvc IDs */
++} BWL_POST_PACKED_STRUCT wifi_nan_svc_id_attr_t;
++
++/* service_control bitmap for wifi_nan_svc_descriptor_attr_t below */
++#define NAN_SC_PUBLISH 0x0
++#define NAN_SC_SUBSCRIBE 0x1
++#define NAN_SC_FOLLOWUP 0x2
++/* Set to 1 if a Matching Filter field is included in descriptors. */
++#define NAN_SC_MATCHING_FILTER_PRESENT 0x4
++/* Set to 1 if a Service Response Filter field is included in descriptors. */
++#define NAN_SC_SR_FILTER_PRESENT 0x8
++/* Set to 1 if a Service Info field is included in descriptors. */
++#define NAN_SC_SVC_INFO_PRESENT 0x10
++/* range is close proximity only */
++#define NAN_SC_RANGE_LIMITED 0x20
++/* Set to 1 if binding bitamp is present in descriptors */
++#define NAN_SC_BINDING_BITMAP_PRESENT 0x40
++
++/* Service descriptor */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_svc_descriptor_attr_s {
++	/* Attribute ID - 0x03. */
++	uint8 id;
++	/* Length of the following fields in the attribute */
++	uint16 len;
++	/* Hash of the Service Name */
++	uint8 svc_hash[NAN_SVC_HASH_LEN];
++	/* Publish or subscribe instance id */
++	uint8 instance_id;
++	/* Requestor Instance ID */
++	uint8 requestor_id;
++	/* Service Control Bitmask. Also determines what data follows. */
++	uint8 svc_control;
++	/* Optional fields follow */
++} BWL_POST_PACKED_STRUCT wifi_nan_svc_descriptor_attr_t;
++
++/* IBSS attribute */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_ibss_attr_s {
++	/* Attribute ID - 0x07. */
++	uint8 id;
++	/* Length of the following fields in the attribute */
++	uint16 len;
++	/* BSSID of the ibss */
++	struct ether_addr bssid;
++	/*
++	 map control:, bits:
++	[0-3]: Id for associated further avail map attribute
++	[4-5]: avail interval duration: 0:16ms; 1:32ms; 2:64ms; 3:reserved
++	[6] : repeat : 0 - applies to next DW, 1: 16 intervals max? wtf?
++	[7] : reserved
++	*/
++	uint8 map_ctrl;
++	/* avail. intervals bitmap, var len  */
++	uint8 avail_bmp[1];
++} BWL_POST_PACKED_STRUCT wifi_nan_ibss_attr_t;
++
++/* Further Availability MAP attr  */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_favail_attr_s {
++	/* Attribute ID - 0x0A. */
++	uint8 id;
++	/* Length of the following fields in the attribute */
++	uint16 len;
++	/* MAP id: val [0..15], values[16-255] reserved */
++	uint8 map_id;
++	/*  availibility entry, var len */
++	uint8 avil_entry[1];
++} BWL_POST_PACKED_STRUCT wifi_nan_favail_attr_t;
++
++/* Further Availability MAP attr  */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_avail_entry_s {
++	/*
++	 entry control
++	 [0-1]: avail interval duration: 0:16ms; 1:32ms; 2:64ms;
++	 [2:7] reserved
++	*/
++	uint8 entry_ctrl;
++	/* operating class: freq band etc IEEE 802.11 */
++	uint8 opclass;
++	/* channel number */
++	uint8 chan;
++	/*  avail bmp, var len */
++	uint8 avail_bmp[1];
++} BWL_POST_PACKED_STRUCT wifi_nan_avail_entry_t;
++
++/* Map control Field */
++#define NAN_MAPCTRL_IDMASK	0x7
++#define NAN_MAPCTRL_DURSHIFT	4
++#define NAN_MAPCTRL_DURMASK	0x30
++#define NAN_MAPCTRL_REPEAT	0x40
++#define NAN_MAPCTRL_REPEATSHIFT	6
++
++#define NAN_VENDOR_TYPE_RTT	0
++#define NAN_VENDOR_TYPE_P2P	1
++
++/* Vendor Specific Attribute */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_vendor_attr_s {
++	uint8	id;			/* 0xDD */
++	uint16	len;		/* IE length */
++	uint8	oui[DOT11_OUI_LEN]; /* 00-90-4C */
++	uint8	type;		/* attribute type */
++	uint8	attr[1];	/* var len attributes */
++} BWL_POST_PACKED_STRUCT wifi_nan_vendor_attr_t;
++
++#define NAN_VENDOR_HDR_SIZE	(OFFSETOF(wifi_nan_vendor_attr_t, attr))
++
++/* p2p operation attribute */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_p2p_op_attr_s {
++	/* Attribute ID - 0x06. */
++	uint8 id;
++	/* Length of the following fields in the attribute */
++	uint16 len;
++	/* P2P device role */
++	uint8 dev_role;
++	/* BSSID of the ibss */
++	struct ether_addr p2p_dev_addr;
++	/*
++	map control:, bits:
++	[0-3]: Id for associated further avail map attribute
++	[4-5]: avail interval duration: 0:16ms; 1:32ms; 2:64ms; 3:reserved
++	[6] : repeat : 0 - applies to next DW, 1: 16 intervals max? wtf?
++	[7] : reserved
++	*/
++	uint8 map_ctrl;
++	/* avail. intervals bitmap */
++	uint8 avail_bmp[1];
++} BWL_POST_PACKED_STRUCT wifi_nan_p2p_op_attr_t;
++
++/* ranging attribute */
++#define NAN_RANGING_MAP_CTRL_ID_SHIFT 0
++#define NAN_RANGING_MAP_CTRL_ID_MASK 0x0F
++#define NAN_RANGING_MAP_CTRL_DUR_SHIFT 4
++#define NAN_RANGING_MAP_CTRL_DUR_MASK 0x30
++#define NAN_RANGING_MAP_CTRL_REPEAT_SHIFT 6
++#define NAN_RANGING_MAP_CTRL_REPEAT_MASK 0x40
++#define NAN_RANGING_MAP_CTRL_REPEAT_DW(_ctrl) (((_ctrl) & \
++	NAN_RANGING_MAP_CTRL_DUR_MASK) ? 16 : 1)
++#define NAN_RANGING_MAP_CTRL(_id, _dur, _repeat) (\
++	(((_id) << NAN_RANGING_MAP_CTRL_ID_SHIFT) & \
++		 NAN_RANGING_MAP_CTRL_ID_MASK) | \
++	(((_dur) << NAN_RANGING_MAP_CTRL_DUR_SHIFT) & \
++		NAN_RANGING_MAP_CTRL_DUR_MASK) | \
++	(((_repeat) << NAN_RANGING_MAP_CTRL_REPEAT_SHIFT) & \
++		 NAN_RANGING_MAP_CTRL_REPEAT_MASK))
++
++enum {
++	NAN_RANGING_PROTO_FTM = 0
++};
++
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_ranging_attr_s {
++	uint8 id;			/* 0x0C */
++	uint16 len;			/* length that follows */
++	struct ether_addr dev_addr;	/* device mac address */
++
++	/*
++	map control:, bits:
++	[0-3]: Id for associated further avail map attribute
++	[4-5]: avail interval duration: 0:16ms; 1:32ms; 2:64ms; 3:reserved
++	[6] : repeat : 0 - applies to next DW, 1: 16 intervals max? wtf?
++	[7] : reserved
++	*/
++	uint8 map_ctrl;
++
++	uint8 protocol;					/* FTM = 0 */
++	uint32 avail_bmp;				/* avail interval bitmap */
++} BWL_POST_PACKED_STRUCT wifi_nan_ranging_attr_t;
++
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_ranging_info_attr_s {
++	uint8 id;			/* 0x1A */
++	uint16 len;			/* length that follows */
++	/*
++	location info availability bit map
++	0: LCI Local Coordinates
++	1: Geospatial LCI WGS84
++	2: Civi Location
++	3: Last Movement Indication
++	[4-7]: reserved
++	*/
++	uint8 lc_info_avail;
++	/*
++	Last movement indication
++	present if bit 3 is set in lc_info_avail
++	cluster TSF[29:14] at the last detected platform movement
++	*/
++	uint16 last_movement;
++
++} BWL_POST_PACKED_STRUCT wifi_nan_ranging_info_attr_t;
++
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_ranging_setup_attr_hdr_s {
++	uint8 id;			/* 0x1B */
++	uint16 len;			/* length that follows */
++	uint8 dialog_token;	/* Identify req and resp */
++	uint8 type_status;	/* bits 0-3 type, 4-7 status */
++	/* reason code
++	i. when frm type = response & status = reject
++	ii. frm type = termination
++	*/
++	uint8 reason;
++} BWL_POST_PACKED_STRUCT wifi_nan_ranging_setup_attr_hdr_t;
++
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_ranging_setup_attr_s {
++
++	wifi_nan_ranging_setup_attr_hdr_t setup_attr_hdr;
++	/* Below fields not required when frm type = termination */
++	uint8 ranging_ctrl; /* Bit 0: ranging report required or not */
++	uint8 ftm_params[3];
++	uint8 data[];	/* schedule entry list */
++} BWL_POST_PACKED_STRUCT wifi_nan_ranging_setup_attr_t;
++
++#define NAN_RANGE_SETUP_ATTR_OFFSET_TBM_INFO (OFFSETOF(wifi_nan_ranging_setup_attr_t, data))
++
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_ranging_report_attr_s {
++	uint8 id;			/* 0x1C */
++	uint16 len;			/* length that follows */
++	/* FTM report format in spec.
++	See definition in 9.4.2.22.18 in 802.11mc D5.0
++	*/
++	uint8 entry_count;
++	uint8 data[2]; /* includes pad */
++	/*
++	dot11_ftm_range_entry_t entries[entry_count];
++	uint8 error_count;
++	dot11_ftm_error_entry_t errors[error_count];
++	 */
++} BWL_POST_PACKED_STRUCT wifi_nan_ranging_report_attr_t;
++
++/* Ranging control flags */
++#define NAN_RNG_REPORT_REQUIRED		0x01
++#define NAN_RNG_FTM_PARAMS_PRESENT	0x02
++#define NAN_RNG_SCHED_ENTRY_PRESENT	0X04
++
++/* Location info flags */
++#define NAN_RNG_LOCATION_FLAGS_LOCAL_CORD		0x1
++#define NAN_RNG_LOCATION_FLAGS_GEO_SPATIAL		0x2
++#define NAN_RNG_LOCATION_FLAGS_CIVIC			0x4
++#define NAN_RNG_LOCATION_FLAGS_LAST_MVMT		0x8
++
++/* Last movement mask and shift value */
++#define NAN_RNG_LOCATION_MASK_LAST_MVT_TSF	0x3FFFC000
++#define NAN_RNG_LOCATION_SHIFT_LAST_MVT_TSF	14
++
++/* FTM params shift values  */
++#define NAN_FTM_MAX_BURST_DUR_SHIFT	0
++#define NAN_FTM_MIN_FTM_DELTA_SHIFT	4
++#define NAN_FTM_NUM_FTM_SHIFT		10
++#define NAN_FTM_FORMAT_BW_SHIFT		15
++
++/* FTM params mask  */
++#define NAN_FTM_MAX_BURST_DUR_MASK	0x00000F
++#define NAN_FTM_MIN_FTM_DELTA_MASK	0x00003F
++#define NAN_FTM_NUM_FTM_MASK		0x00001F
++#define NAN_FTM_FORMAT_BW_MASK		0x00003F
++
++#define FTM_PARAMS_BURSTTMO_FACTOR 250
++
++/* set to value to uint32 */
++#define NAN_FTM_SET_BURST_DUR(ftm, dur) (ftm |= (((dur + 2) & NAN_FTM_MAX_BURST_DUR_MASK) <<\
++	NAN_FTM_MAX_BURST_DUR_SHIFT))
++#define NAN_FTM_SET_FTM_DELTA(ftm, delta) (ftm |= (((delta/100) & NAN_FTM_MIN_FTM_DELTA_MASK) <<\
++	NAN_FTM_MIN_FTM_DELTA_SHIFT))
++#define NAN_FTM_SET_NUM_FTM(ftm, delta) (ftm |= ((delta & NAN_FTM_NUM_FTM_MASK) <<\
++	NAN_FTM_NUM_FTM_SHIFT))
++#define NAN_FTM_SET_FORMAT_BW(ftm, delta) (ftm |= ((delta & NAN_FTM_FORMAT_BW_MASK) <<\
++	NAN_FTM_FORMAT_BW_SHIFT))
++/* set uint32 to attribute */
++#define NAN_FTM_PARAMS_UINT32_TO_ATTR(ftm_u32, ftm_attr) {ftm_attr[0] = ftm_u32 & 0xFF; \
++			ftm_attr[1] = (ftm_u32 >> 8) & 0xFF; ftm_attr[2] = (ftm_u32 >> 16) & 0xFF;}
++
++/* get atrribute to uint32 */
++#define NAN_FTM_PARAMS_ATTR_TO_UINT32(ftm_p, ftm_u32) (ftm_u32 = ftm_p[0] | ftm_p[1] << 8 | \
++	ftm_p[2] << 16)
++/* get param values from uint32 */
++#define NAN_FTM_GET_BURST_DUR(ftm) (((ftm >> NAN_FTM_MAX_BURST_DUR_SHIFT) &\
++	NAN_FTM_MAX_BURST_DUR_MASK))
++#define NAN_FTM_GET_BURST_DUR_USEC(_val) ((1 << ((_val)-2)) * FTM_PARAMS_BURSTTMO_FACTOR)
++#define NAN_FTM_GET_FTM_DELTA(ftm) (((ftm >> NAN_FTM_MIN_FTM_DELTA_SHIFT) &\
++	NAN_FTM_MIN_FTM_DELTA_MASK)*100)
++#define NAN_FTM_GET_NUM_FTM(ftm) ((ftm >> NAN_FTM_NUM_FTM_SHIFT) &\
++	NAN_FTM_NUM_FTM_MASK)
++#define NAN_FTM_GET_FORMAT_BW(ftm) ((ftm >> NAN_FTM_FORMAT_BW_SHIFT) &\
++	NAN_FTM_FORMAT_BW_MASK)
++
++#define NAN_CONN_CAPABILITY_WFD		0x0001
++#define NAN_CONN_CAPABILITY_WFDS	0x0002
++#define NAN_CONN_CAPABILITY_TDLS	0x0004
++#define NAN_CONN_CAPABILITY_INFRA	0x0008
++#define NAN_CONN_CAPABILITY_IBSS	0x0010
++#define NAN_CONN_CAPABILITY_MESH	0x0020
++
++#define NAN_DEFAULT_MAP_ID		0	/* nan default map id */
++#define NAN_DEFAULT_MAP_CTRL		0	/* nan default map control */
++
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_conn_cap_attr_s {
++	/* Attribute ID - 0x04. */
++	uint8 id;
++	/* Length of the following fields in the attribute */
++	uint16	len;
++	uint16	conn_cap_bmp;	/* Connection capability bitmap */
++} BWL_POST_PACKED_STRUCT wifi_nan_conn_cap_attr_t;
++
++/* NAN Element container Attribute */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_container_attr_s {
++	uint8 id;	/* id - 0x20 */
++	uint16 len;	/* Total length of following IEs */
++	uint8 map_id;	/* map id */
++	uint8 data[1];	/* Data pointing to one or more IEs */
++} BWL_POST_PACKED_STRUCT wifi_nan_container_attr_t;
++
++/* NAN 2.0 NAN avail attribute */
++
++/* Availability Attribute */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_avail_attr_s {
++	uint8 id;	/* id - 0x12 */
++	uint16 len;	/* total length */
++	uint8 seqid;	/* sequence id */
++	uint16 ctrl;	/* attribute control */
++	uint8 entry[1];	/* availability entry list */
++} BWL_POST_PACKED_STRUCT wifi_nan_avail_attr_t;
++
++/* for processing/building time bitmap info in nan_avail_entry */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_time_bitmap_s {
++	uint16 ctrl;		/* Time bitmap control */
++	uint8 len;		/* Time bitmap length */
++	uint8 bitmap[];	/* Time bitmap */
++} BWL_POST_PACKED_STRUCT wifi_nan_time_bitmap_t;
++
++/* Availability Entry format */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_avail_entry_attr_s {
++	uint16 len;		/* Length */
++	uint16 entry_cntrl;	/* Entry Control */
++	uint8 var[];		/* Time bitmap and channel entry list */
++} BWL_POST_PACKED_STRUCT wifi_nan_avail_entry_attr_t;
++
++/* FAC Channel Entry  (section 10.7.19.1.5) */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_chan_entry_s {
++	uint8 oper_class;		/* Operating Class */
++	uint16 chan_bitmap;		/* Channel Bitmap */
++	uint8 primary_chan_bmp;		/* Primary Channel Bitmap */
++	uint8 aux_chan[0];			/* Auxiliary Channel bitmap */
++} BWL_POST_PACKED_STRUCT wifi_nan_chan_entry_t;
++
++/* Channel entry */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_channel_entry_s {
++	uint8 opclass;		/* Operating class */
++	uint16 chan_bitmap;	/* Channel bitmap */
++	uint8 prim_bitmap;	/* Primary channel bitmap */
++	uint16 aux_bitmap;	/* Time bitmap length */
++} BWL_POST_PACKED_STRUCT wifi_nan_channel_entry_t;
++
++/* Type of  Availability: committed */
++#define NAN_ENTRY_CNTRL_TYPE_COMM_AVAIL_MASK	0x1
++/* Type of  Availability: potential */
++#define NAN_ENTRY_CNTRL_TYPE_POTEN_AVAIL_MASK	0x2
++/* Type of  Availability: conditional */
++#define NAN_ENTRY_CNTRL_TYPE_COND_AVAIL_MASK	0x4
++
++#define NAN_AVAIL_CTRL_MAP_ID_MASK		0x000F
++#define NAN_AVAIL_CTRL_MAP_ID(_ctrl)		((_ctrl) & NAN_AVAIL_CTRL_MAP_ID_MASK)
++#define NAN_AVAIL_CTRL_COMM_CHANGED_MASK	0x0010
++#define NAN_AVAIL_CTRL_COMM_CHANGED(_ctrl)	((_ctrl) & NAN_AVAIL_CTRL_COMM_CHANGED_MASK)
++#define NAN_AVAIL_CTRL_POTEN_CHANGED_MASK	0x0020
++#define NAN_AVAIL_CTRL_POTEN_CHANGED(_ctrl)	((_ctrl) & NAN_AVAIL_CTRL_POTEN_CHANGED_MASK)
++#define NAN_AVAIL_CTRL_PUBLIC_CHANGED_MASK	0x0040
++#define NAN_AVAIL_CTRL_PUBLIC_CHANGED(_ctrl)	((_ctrl) & NAN_AVAIL_CTRL_PUBLIC_CHANGED_MASK)
++#define NAN_AVAIL_CTRL_NDC_CHANGED_MASK		0x0080
++#define NAN_AVAIL_CTRL_NDC_CHANGED(_ctrl)	((_ctrl) & NAN_AVAIL_CTRL_NDC_CHANGED_MASK)
++#define NAN_AVAIL_CTRL_MCAST_CHANGED_MASK	0x0100
++#define NAN_AVAIL_CTRL_MCAST_CHANGED(_ctrl)	((_ctrl) & NAN_AVAIL_CTRL_MCAST_CHANGED_MASK)
++#define NAN_AVAIL_CTRL_MCAST_CHG_CHANGED_MASK	0x0200
++#define NAN_AVAIL_CTRL_MCAST_CHG_CHANGED(_ctrl)	((_ctrl) & NAN_AVAIL_CTRL_MCAST_CHG_CHANGED_MASK)
++#define NAN_AVAIL_CTRL_CHANGED_FLAGS_MASK	0x03f0
++
++#define NAN_AVAIL_ENTRY_CTRL_AVAIL_TYPE_MASK 0x07
++#define NAN_AVAIL_ENTRY_CTRL_AVAIL_TYPE(_flags) ((_flags) & NAN_AVAIL_ENTRY_CTRL_AVAIL_TYPE_MASK)
++#define NAN_AVAIL_ENTRY_CTRL_USAGE_MASK 0x18
++#define NAN_AVAIL_ENTRY_CTRL_USAGE_SHIFT 3
++#define NAN_AVAIL_ENTRY_CTRL_USAGE(_flags) (((_flags) & NAN_AVAIL_ENTRY_CTRL_USAGE_MASK) \
++	>> NAN_AVAIL_ENTRY_CTRL_USAGE_SHIFT)
++#define NAN_AVAIL_ENTRY_CTRL_UTIL_MASK 0x1E0
++#define NAN_AVAIL_ENTRY_CTRL_UTIL_SHIFT 5
++#define NAN_AVAIL_ENTRY_CTRL_UTIL(_flags) (((_flags) & NAN_AVAIL_ENTRY_CTRL_UTIL_MASK) \
++	>> NAN_AVAIL_ENTRY_CTRL_UTIL_SHIFT)
++#define NAN_AVAIL_ENTRY_CTRL_RX_NSS_MASK 0xF00
++#define NAN_AVAIL_ENTRY_CTRL_RX_NSS_SHIFT 8
++#define NAN_AVAIL_ENTRY_CTRL_RX_NSS(_flags) (((_flags) & NAN_AVAIL_ENTRY_CTRL_RX_NSS_MASK) \
++	>> NAN_AVAIL_ENTRY_CTRL_RX_NSS_SHIFT)
++#define NAN_AVAIL_ENTRY_CTRL_BITMAP_PRESENT_MASK 0x1000
++#define NAN_AVAIL_ENTRY_CTRL_BITMAP_PRESENT_SHIFT 12
++#define NAN_AVAIL_ENTRY_CTRL_BITMAP_PRESENT(_flags) (((_flags) & \
++	NAN_AVAIL_ENTRY_CTRL_BITMAP_PRESENT_MASK) >> NAN_AVAIL_ENTRY_CTRL_BITMAP_PRESENT_SHIFT)
++
++#define NAN_TIME_BMAP_CTRL_BITDUR_MASK 0x07
++#define NAN_TIME_BMAP_CTRL_BITDUR(_flags) ((_flags) & NAN_TIME_BMAP_CTRL_BITDUR_MASK)
++#define NAN_TIME_BMAP_CTRL_PERIOD_MASK 0x38
++#define NAN_TIME_BMAP_CTRL_PERIOD_SHIFT 3
++#define NAN_TIME_BMAP_CTRL_PERIOD(_flags) (((_flags) & NAN_TIME_BMAP_CTRL_PERIOD_MASK) \
++	>> NAN_TIME_BMAP_CTRL_PERIOD_SHIFT)
++#define NAN_TIME_BMAP_CTRL_OFFSET_MASK 0x7FC0
++#define NAN_TIME_BMAP_CTRL_OFFSET_SHIFT 6
++#define NAN_TIME_BMAP_CTRL_OFFSET(_flags) (((_flags) & NAN_TIME_BMAP_CTRL_OFFSET_MASK) \
++	>> NAN_TIME_BMAP_CTRL_OFFSET_SHIFT)
++#define NAN_TIME_BMAP_LEN(avail_entry)	\
++	(*(uint8 *)(((wifi_nan_avail_entry_attr_t *)avail_entry)->var + 2))
++
++#define NAN_AVAIL_CHAN_LIST_HDR_LEN 1
++#define NAN_AVAIL_CHAN_LIST_TYPE_CHANNEL	0x01
++#define NAN_AVAIL_CHAN_LIST_NON_CONTIG_BW	0x02
++#define NAN_AVAIL_CHAN_LIST_NUM_ENTRIES_MASK	0xF0
++#define NAN_AVAIL_CHAN_LIST_NUM_ENTRIES_SHIFT	4
++#define NAN_AVAIL_CHAN_LIST_NUM_ENTRIES(_ctrl) (((_ctrl) & NAN_AVAIL_CHAN_LIST_NUM_ENTRIES_MASK) \
++	>> NAN_AVAIL_CHAN_LIST_NUM_ENTRIES_SHIFT)
++
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_channel_entry_list_s {
++	uint8 chan_info;
++	uint8 var[0];
++} BWL_POST_PACKED_STRUCT wifi_nan_channel_entry_list_t;
++
++/* define for chan_info */
++#define NAN_CHAN_OP_CLASS_MASK 0x01
++#define NAN_CHAN_NON_CONT_BW_MASK 0x02
++#define NAN_CHAN_RSVD_MASK 0x03
++#define NAN_CHAN_NUM_ENTRIES_MASK 0xF0
++
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_band_entry_s {
++	uint8 band[0];
++} BWL_POST_PACKED_STRUCT wifi_nan_band_entry_t;
++
++/* Type of  Availability: committed */
++#define NAN_ENTRY_CNTRL_TYPE_COMM_AVAIL	        0x1
++/* Type of  Availability: potential */
++#define NAN_ENTRY_CNTRL_TYPE_POTEN_AVAIL	0x2
++/* Type of  Availability: conditional */
++#define NAN_ENTRY_CNTRL_TYPE_COND_AVAIL	        0x4
++/* Committed + Potential */
++#define NAN_ENTRY_CNTRL_TYPE_COMM_POTEN \
++	(NAN_ENTRY_CNTRL_TYPE_COMM_AVAIL | NAN_ENTRY_CNTRL_TYPE_POTEN_AVAIL)
++/* Conditional + Potential */
++#define NAN_ENTRY_CNTRL_TYPE_COND_POTEN \
++	(NAN_ENTRY_CNTRL_TYPE_COND_AVAIL | NAN_ENTRY_CNTRL_TYPE_POTEN_AVAIL)
++
++/* Type of  Availability */
++#define NAN_ENTRY_CNTRL_TYPE_OF_AVAIL_MASK	0x07
++#define NAN_ENTRY_CNTRL_TYPE_OF_AVAIL_SHIFT	0
++/* Usage Preference */
++#define NAN_ENTRY_CNTRL_USAGE_PREF_MASK		0x18
++#define NAN_ENTRY_CNTRL_USAGE_PREF_SHIFT	3
++/* Utilization */
++#define NAN_ENTRY_CNTRL_UTIL_MASK		0x1E0
++#define NAN_ENTRY_CNTRL_UTIL_SHIFT		5
++
++/* Time Bitmap Control field (section 5.7.18.2.3) */
++
++/* Reserved */
++#define NAN_TIME_BMP_CNTRL_RSVD_MASK	0x01
++#define NAN_TIME_BMP_CNTRL_RSVD_SHIFT	0
++/* Bitmap Len */
++#define NAN_TIME_BMP_CNTRL_BMP_LEN_MASK	0x7E
++#define NAN_TIME_BMP_CNTRL_BMP_LEN_SHIFT 1
++/* Bit Duration */
++#define NAN_TIME_BMP_CNTRL_BIT_DUR_MASK	0x380
++#define NAN_TIME_BMP_CNTRL_BIT_DUR_SHIFT	7
++/* Bitmap Len */
++#define NAN_TIME_BMP_CNTRL_PERIOD_MASK	0x1C00
++#define NAN_TIME_BMP_CNTRL_PERIOD_SHIFT	10
++/* Start Offset */
++#define NAN_TIME_BMP_CNTRL_START_OFFSET_MASK	0x3FE000
++#define NAN_TIME_BMP_CNTRL_START_OFFSET_SHIFT	13
++/* Reserved */
++#define NAN_TIME_BMP_CNTRL_RESERVED_MASK	0xC00000
++#define NAN_TIME_BMP_CNTRL_RESERVED_SHIFT	22
++
++/* Time Bitmap Control field: Period */
++typedef enum
++{
++	NAN_TIME_BMP_CTRL_PERIOD_128TU = 1,
++	NAN_TIME_BMP_CTRL_PERIOD_256TU = 2,
++	NAN_TIME_BMP_CTRL_PERIOD_512TU = 3,
++	NAN_TIME_BMP_CTRL_PERIOD_1024TU = 4,
++	NAN_TIME_BMP_CTRL_PERIOD_2048U = 5,
++	NAN_TIME_BMP_CTRL_PERIOD_4096U = 6,
++	NAN_TIME_BMP_CTRL_PERIOD_8192U = 7
++} nan_time_bmp_ctrl_repeat_interval_t;
++
++enum
++{
++	NAN_TIME_BMP_BIT_DUR_16TU_IDX = 0,
++	NAN_TIME_BMP_BIT_DUR_32TU_IDX = 1,
++	NAN_TIME_BMP_BIT_DUR_64TU_IDX = 2,
++	NAN_TIME_BMP_BIT_DUR_128TU_IDX = 3
++};
++
++enum
++{
++	NAN_TIME_BMP_BIT_DUR_IDX_0 = 16,
++	NAN_TIME_BMP_BIT_DUR_IDX_1 = 32,
++	NAN_TIME_BMP_BIT_DUR_IDX_2 = 64,
++	NAN_TIME_BMP_BIT_DUR_IDX_3 = 128
++};
++
++enum
++{
++	NAN_TIME_BMP_CTRL_PERIOD_IDX_1 = 128,
++	NAN_TIME_BMP_CTRL_PERIOD_IDX_2 = 256,
++	NAN_TIME_BMP_CTRL_PERIOD_IDX_3 = 512,
++	NAN_TIME_BMP_CTRL_PERIOD_IDX_4 = 1024,
++	NAN_TIME_BMP_CTRL_PERIOD_IDX_5 = 2048,
++	NAN_TIME_BMP_CTRL_PERIOD_IDX_6 = 4096,
++	NAN_TIME_BMP_CTRL_PERIOD_IDX_7 = 8192
++};
++
++/* Channel Entries List field */
++
++/* Type */
++#define NAN_CHAN_ENTRY_TYPE_MASK	0x01
++#define NAN_CHAN_ENTRY_TYPE_SHIFT	0
++/* Channel Entry Length Indication */
++#define NAN_CHAN_ENTRY_LEN_IND_MASK	0x02
++#define NAN_CHAN_ENTRY_LEN_IND_SHIFT	1
++/* Reserved */
++#define NAN_CHAN_ENTRY_RESERVED_MASK	0x0C
++#define NAN_CHAN_ENTRY_RESERVED_SHIFT	2
++/* Number of FAC Band or Channel Entries  */
++#define NAN_CHAN_ENTRY_NO_OF_CHAN_ENTRY_MASK	0xF0
++#define NAN_CHAN_ENTRY_NO_OF_CHAN_ENTRY_SHIFT	4
++
++#define NAN_CHAN_ENTRY_TYPE_BANDS	0
++#define NAN_CHAN_ENTRY_TYPE_OPCLASS_CHANS	1
++
++#define NAN_CHAN_ENTRY_BW_LT_80MHZ	0
++#define NAN_CHAN_ENTRY_BW_EQ_160MHZ	1
++
++/*
++ * NDL Attribute WFA Tech. Spec ver 1.0.r12 (section 10.7.19.2)
++ */
++#define NDL_ATTR_IM_MAP_ID_LEN		1
++#define NDL_ATTR_IM_TIME_BMP_CTRL_LEN	2
++#define NDL_ATTR_IM_TIME_BMP_LEN_LEN	1
++
++/*
++ * NDL Control field - Table xx
++ */
++#define NDL_ATTR_CTRL_PEER_ID_PRESENT_MASK		0x01
++#define NDL_ATTR_CTRL_PEER_ID_PRESENT_SHIFT		0
++#define NDL_ATTR_CTRL_IM_SCHED_PRESENT_MASK		0x02
++#define NDL_ATTR_CTRL_IM_SCHED_PRESENT_SHIFT	1
++#define NDL_ATTR_CTRL_NDC_ATTR_PRESENT_MASK		0x04
++#define NDL_ATTR_CTRL_NDC_ATTR_PRESENT_SHIFT	2
++#define NDL_ATTR_CTRL_QOS_ATTR_PRESENT_MASK		0x08
++#define NDL_ATTR_CTRL_QOS_ATTR_PRESENT_SHIFT	3
++#define NDL_ATTR_CTRL_MAX_IDLE_PER_PRESENT_MASK		0x10	/* max idle period */
++#define NDL_ATTR_CTRL_MAX_IDLE_PER_PRESENT_SHIFT	4
++#define NDL_ATTR_CTRL_NDL_TYPE_MASK				0x20	/* NDL type */
++#define NDL_ATTR_CTRL_NDL_TYPE_SHIFT			5
++#define NDL_ATTR_CTRL_NDL_SETUP_REASON_MASK		0xC0	/* NDL Setup Reason */
++#define NDL_ATTR_CTRL_NDL_SETUP_REASON_SHIFT	6
++
++/* NDL setup Reason */
++#define NDL_ATTR_CTRL_NDL_TYPE_S_NDL	0x0	/* S-NDL */
++#define NDL_ATTR_CTRL_NDL_TYPE_P_NDL	0x1	/* P-NDL */
++
++/* NDL setup Reason */
++#define NDL_ATTR_CTRL_NDL_SETUP_REASON_NDP_RANG	0x0	/* NDP or Ranging */
++#define NDL_ATTR_CTRL_NDL_SETUP_REASON_FSD_GAS	0x1	/* FSD using GAS */
++
++#define NAN_NDL_TYPE_MASK				0x0F
++#define NDL_ATTR_TYPE_STATUS_REQUEST	0x00
++#define NDL_ATTR_TYPE_STATUS_RESPONSE	0x01
++#define NDL_ATTR_TYPE_STATUS_CONFIRM	0x02
++#define NDL_ATTR_TYPE_STATUS_CONTINUED	0x00
++#define NDL_ATTR_TYPE_STATUS_ACCEPTED	0x10
++#define NDL_ATTR_TYPE_STATUS_REJECTED	0x20
++
++#define NAN_NDL_TYPE_CHECK(_ndl, x)	(((_ndl)->type_status & NAN_NDL_TYPE_MASK) == (x))
++#define NAN_NDL_REQUEST(_ndl)		(((_ndl)->type_status & NAN_NDL_TYPE_MASK) == \
++								NDL_ATTR_TYPE_STATUS_REQUEST)
++#define NAN_NDL_RESPONSE(_ndl)		(((_ndl)->type_status & NAN_NDL_TYPE_MASK) == \
++								NDL_ATTR_TYPE_STATUS_RESPONSE)
++#define NAN_NDL_CONFIRM(_ndl)		(((_ndl)->type_status & NAN_NDL_TYPE_MASK) == \
++								NDL_ATTR_TYPE_STATUS_CONFIRM)
++
++
++#define NAN_NDL_STATUS_SHIFT	4
++#define NAN_NDL_STATUS_MASK	0xF0
++#define NAN_NDL_CONT(_ndl)	(((_ndl)->type_status & NAN_NDL_STATUS_MASK) == \
++								NDL_ATTR_TYPE_STATUS_CONTINUED)
++#define NAN_NDL_ACCEPT(_ndl)	(((_ndl)->type_status & NAN_NDL_STATUS_MASK) == \
++								NDL_ATTR_TYPE_STATUS_ACCEPTED)
++#define NAN_NDL_REJECT(_ndl)	(((_ndl)->type_status & NAN_NDL_STATUS_MASK) == \
++								NDL_ATTR_TYPE_STATUS_REJECTED)
++
++#define NDL_ATTR_CTRL_NONE				0
++#define NDL_ATTR_CTRL_PEER_ID_PRESENT	(1 << NDL_ATTR_CTRL_PEER_ID_PRESENT_SHIFT)
++#define NDL_ATTR_CTRL_IMSCHED_PRESENT	(1 << NDL_ATTR_CTRL_IM_SCHED_PRESENT_SHIFT)
++#define NDL_ATTR_CTRL_NDC_PRESENT		(1 << NDL_ATTR_CTRL_NDC_ATTR_PRESENT_SHIFT)
++#define NDL_ATTR_CTRL_NDL_QOS_PRESENT	(1 << NDL_ATTR_CTRL_QOS_ATTR_PRESENT_SHIFT)
++#define NDL_ATTR_CTRL_MAX_IDLE_PER_PRESENT	(1 << NDL_ATTR_CTRL_MAX_IDLE_PER_PRESENT_SHIFT)
++
++#define NA_NDL_IS_IMMUT_PRESENT(ndl) (((ndl)->ndl_ctrl) & NDL_ATTR_CTRL_IMSCHED_PRESENT)
++#define NA_NDL_IS_PEER_ID_PRESENT(ndl) (((ndl)->ndl_ctrl) & NDL_ATTR_CTRL_PEER_ID_PRESENT)
++#define NA_NDL_IS_MAX_IDLE_PER_PRESENT(ndl) (((ndl)->ndl_ctrl) & NDL_ATTR_CTRL_MAX_IDLE_PER_PRESENT)
++
++#define NDL_ATTR_PEERID_LEN				1
++#define NDL_ATTR_MAX_IDLE_PERIOD_LEN	2
++
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_ndl_attr_s {
++	uint8 id;		/* NAN_ATTR_NAN_NDL = 0x17 */
++	uint16 len;		/* Length of the fields in the attribute */
++	uint8 dialog_token;	/* Identify req and resp */
++	uint8 type_status;		/* Bits[3-0] type subfield, Bits[7-4] status subfield */
++	uint8 reason;		/* Identifies reject reason */
++	uint8 ndl_ctrl;		/* NDL control field */
++	uint8 var[];		/* Optional fields follow */
++} BWL_POST_PACKED_STRUCT wifi_nan_ndl_attr_t;
++
++/*
++ * NDL QoS Attribute  WFA Tech. Spec ver r26
++ */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_ndl_qos_attr_s {
++	uint8 id;		/* NAN_ATTR_NAN_NDL_QOS = 24 */
++	uint16 len;		/* Length of the attribute field following */
++	uint8 min_slots;	/* Min. number of FAW slots needed per DW interval */
++	uint16 max_latency;  /* Max interval between non-cont FAW */
++} BWL_POST_PACKED_STRUCT wifi_nan_ndl_qos_attr_t;
++
++/* no preference to min time slots */
++#define NAN_NDL_QOS_MIN_SLOT_NO_PREF	0
++/* no preference to no. of slots between two non-contiguous slots */
++#define NAN_NDL_QOS_MAX_LAT_NO_PREF		0xFFFF
++
++/* Device Capability Attribute */
++
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_dev_cap_s {
++	uint8 id;		/* 0x0F */
++	uint16 len;		/* Length */
++	uint8 map_id;		/* map id */
++	uint16 commit_dw_info;	/* Committed DW Info */
++	uint8 bands_supported;	/* Supported Bands */
++	uint8 op_mode;		/* Operation Mode */
++	uint8 num_antennas;	/* Bit 0-3 tx, 4-7 rx */
++	uint16 chan_switch_time;	/* Max channel switch time in us */
++	uint8 capabilities;	/* DFS Master, Extended key id etc */
++} BWL_POST_PACKED_STRUCT wifi_nan_dev_cap_t;
++
++/* Awake DW Info field format */
++
++/* 2.4GHz DW */
++#define NAN_DEV_CAP_AWAKE_DW_2G_MASK	0x07
++/* 5GHz DW */
++#define NAN_DEV_CAP_AWAKE_DW_5G_MASK	0x38
++/* Reserved */
++#define NAN_DEV_CAP_AWAKE_DW_RSVD_MASK	0xC0
++
++/* bit shift for dev cap */
++#define NAN_DEV_CAP_AWAKE_DW_2G_SHIFT	0
++#define NAN_DEV_CAP_AWAKE_DW_5G_SHIFT	3
++
++/* Device Capability Attribute Format */
++
++/* Committed DW Info field format */
++/* 2.4GHz DW */
++#define NAN_DEV_CAP_COMMIT_DW_2G_MASK	0x07
++#define NAN_DEV_CAP_COMMIT_DW_2G_OVERWRITE_MASK	0x3C0
++/* 5GHz DW */
++#define NAN_DEV_CAP_COMMIT_DW_5G_MASK	0x38
++#define NAN_DEV_CAP_COMMIT_DW_5G_OVERWRITE_MASK 0x3C00
++/* Reserved */
++#define NAN_DEV_CAP_COMMIT_DW_RSVD_MASK	0xC000
++/* Committed DW bit shift for dev cap */
++#define NAN_DEV_CAP_COMMIT_DW_2G_SHIFT	0
++#define NAN_DEV_CAP_COMMIT_DW_5G_SHIFT	3
++#define NAN_DEV_CAP_COMMIT_DW_2G_OVERWRITE_SHIFT	6
++#define NAN_DEV_CAP_COMMIT_DW_5G_OVERWRITE_SHIFT	10
++/* Operation Mode */
++#define NAN_DEV_CAP_OP_PHY_MODE_HT_ONLY		0x00
++#define NAN_DEV_CAP_OP_PHY_MODE_VHT		0x01
++#define NAN_DEV_CAP_OP_PHY_MODE_VHT_8080	0x02
++#define NAN_DEV_CAP_OP_PHY_MODE_VHT_160		0x04
++#define NAN_DEV_CAP_OP_PAGING_NDL		0x08
++
++#define NAN_DEV_CAP_OP_MODE_VHT_MASK		0x01
++#define NAN_DEV_CAP_OP_MODE_VHT8080_MASK	0x03
++#define NAN_DEV_CAP_OP_MODE_VHT160_MASK		0x05
++#define NAN_DEV_CAP_OP_MODE_PAGING_NDL_MASK	0x08
++
++#define NAN_DEV_CAP_RX_ANT_SHIFT		4
++#define NAN_DEV_CAP_TX_ANT_MASK			0x0F
++#define NAN_DEV_CAP_RX_ANT_MASK			0xF0
++
++/* Device capabilities */
++
++/* DFS master capability */
++#define NAN_DEV_CAP_DFS_MASTER_MASK		0x01
++#define NAN_DEV_CAP_DFS_MASTER_SHIFT	0
++/* extended iv cap */
++#define NAN_DEV_CAP_EXT_KEYID_MASK		0x02
++#define NAN_DEV_CAP_EXT_KEYID_SHIFT		1
++
++/* Band IDs */
++enum {
++	NAN_BAND_ID_TVWS		= 0,
++	NAN_BAND_ID_SIG			= 1,	/* Sub 1 GHz */
++	NAN_BAND_ID_2G			= 2,	/* 2.4 GHz */
++	NAN_BAND_ID_3G			= 3,	/* 3.6 GHz */
++	NAN_BAND_ID_5G			= 4,	/* 4.9 & 5 GHz */
++	NAN_BAND_ID_60G			= 5
++};
++typedef uint8 nan_band_id_t;
++
++/*
++ * Unaligned schedule attribute section 10.7.19.6 spec. ver r15
++ */
++#define NAN_ULW_ATTR_CTRL_SCHED_ID_MASK 0x000F
++#define NAN_ULW_ATTR_CTRL_SCHED_ID_SHIFT 0
++#define NAN_ULW_ATTR_CTRL_SEQ_ID_MASK 0xFF00
++#define NAN_ULW_ATTR_CTRL_SEQ_ID_SHIFT 8
++
++#define NAN_ULW_OVWR_ALL_MASK 0x01
++#define NAN_ULW_OVWR_ALL_SHIFT 0
++#define NAN_ULW_OVWR_MAP_ID_MASK 0x1E
++#define NAN_ULW_OVWR_MAP_ID_SHIFT 1
++
++#define NAN_ULW_CTRL_TYPE_MASK 0x03
++#define NAN_ULW_CTRL_TYPE_SHIFT 0
++#define NAN_ULW_CTRL_TYPE(ctrl)	(ctrl & NAN_ULW_CTRL_TYPE_MASK)
++#define NAN_ULW_CTRL_CHAN_AVAIL_MASK 0x04
++#define NAN_ULW_CTRL_CHAN_AVAIL_SHIFT 2
++#define NAN_ULW_CTRL_CHAN_AVAIL(ctrl)	((ctrl & NAN_ULW_CTRL_CHAN_AVAIL_MASK) \
++	>> NAN_ULW_CTRL_CHAN_AVAIL_SHIFT)
++#define NAN_ULW_CTRL_RX_NSS_MASK 0x78
++#define NAN_ULW_CTRL_RX_NSS_SHIFT 3
++
++#define NAN_ULW_CTRL_TYPE_BAND		0
++#define NAN_ULW_CTRL_TYPE_CHAN_NOAUX	1
++#define NAN_ULW_CTRL_TYPE_CHAN_AUX	2
++
++#define NAN_ULW_CNT_DOWN_NO_EXPIRE	0xFF	/* ULWs doen't end until next sched update */
++#define NAN_ULW_CNT_DOWN_CANCEL		0x0		/* cancel remaining ulws */
++
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_ulw_attr_s {
++	uint8 id;
++	uint16 len;
++	uint16 ctrl;
++	uint32 start; /* low 32 bits of tsf */
++	uint32 dur;
++	uint32 period;
++	uint8 count_down;
++	uint8 overwrite;
++	/*
++	 * ulw[0] == optional field ULW control when present.
++	 * band ID or channel follows
++	 */
++	uint8 ulw_entry[];
++} BWL_POST_PACKED_STRUCT wifi_nan_ulw_attr_t;
++
++/* NAN2 Management Frame (section 5.6) */
++
++/* Public action frame for NAN2 */
++typedef BWL_PRE_PACKED_STRUCT struct nan2_pub_act_frame_s {
++	/* NAN_PUB_AF_CATEGORY 0x04 */
++	uint8 category_id;
++	/* NAN_PUB_AF_ACTION 0x09 */
++	uint8 action_field;
++	/* NAN_OUI 0x50-6F-9A */
++	uint8 oui[DOT11_OUI_LEN];
++	/* NAN_OUI_TYPE TBD */
++	uint8 oui_type;
++	/* NAN_OUI_SUB_TYPE TBD */
++	uint8 oui_sub_type;
++	/* One or more NAN Attributes follow */
++	uint8 data[];
++} BWL_POST_PACKED_STRUCT nan2_pub_act_frame_t;
++
++#define NAN2_PUB_ACT_FRM_SIZE	(OFFSETOF(nan2_pub_act_frame_t, data))
++
++/* NAN Action Frame Subtypes */
++/* Subtype-0 is Reserved */
++#define NAN_MGMT_FRM_SUBTYPE_RESERVED		0
++/* NAN Ranging Request */
++#define NAN_MGMT_FRM_SUBTYPE_RANGING_REQ	1
++/* NAN Ranging Response */
++#define NAN_MGMT_FRM_SUBTYPE_RANGING_RESP	2
++/* NAN Ranging Termination */
++#define NAN_MGMT_FRM_SUBTYPE_RANGING_TERM	3
++/* NAN Ranging Report */
++#define NAN_MGMT_FRM_SUBTYPE_RANGING_RPT	4
++/* NDP Request */
++#define NAN_MGMT_FRM_SUBTYPE_NDP_REQ		5
++/* NDP Response */
++#define NAN_MGMT_FRM_SUBTYPE_NDP_RESP		6
++/* NDP Confirm */
++#define NAN_MGMT_FRM_SUBTYPE_NDP_CONFIRM	7
++/* NDP Key Installment */
++#define NAN_MGMT_FRM_SUBTYPE_NDP_KEY_INST	8
++/* NDP Termination */
++#define NAN_MGMT_FRM_SUBTYPE_NDP_END		9
++/* Schedule Request */
++#define NAN_MGMT_FRM_SUBTYPE_SCHED_REQ		10
++/* Schedule Response */
++#define NAN_MGMT_FRM_SUBTYPE_SCHED_RESP		11
++/* Schedule Confirm */
++#define NAN_MGMT_FRM_SUBTYPE_SCHED_CONF		12
++/* Schedule Update */
++#define NAN_MGMT_FRM_SUBTYPE_SCHED_UPD		13
++
++/* Reason code defines */
++#define NAN_REASON_RESERVED			0x0
++#define NAN_REASON_UNSPECIFIED			0x1
++#define NAN_REASON_RESOURCE_LIMIT		0x2
++#define NAN_REASON_INVALID_PARAMS		0x3
++#define NAN_REASON_FTM_PARAM_INCAP		0x4
++#define NAN_REASON_NO_MOVEMENT			0x5
++#define NAN_REASON_INVALID_AVAIL		0x6
++#define NAN_REASON_IMMUT_UNACCEPT		0x7
++#define NAN_REASON_SEC_POLICY			0x8
++#define NAN_REASON_QOS_UNACCEPT			0x9
++#define NAN_REASON_NDP_REJECT			0xa
++#define NAN_REASON_NDL_UNACCEPTABLE		0xb
++
++/* nan 2.0 qos (not attribute) */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_ndp_qos_s {
++	uint8 tid;		/* traffic identifier */
++	uint16 pkt_size;	/* service data pkt size */
++	uint8 data_rate;	/* mean data rate */
++	uint8 svc_interval;	/* max service interval */
++} BWL_POST_PACKED_STRUCT wifi_nan_ndp_qos_t;
++
++/* NDP control bitmap defines */
++#define NAN_NDP_CTRL_CONFIRM_REQUIRED		0x01
++#define NAN_NDP_CTRL_SECURTIY_PRESENT		0x04
++#define NAN_NDP_CTRL_PUB_ID_PRESENT		0x08
++#define NAN_NDP_CTRL_RESP_NDI_PRESENT		0x10
++#define NAN_NDP_CTRL_SPEC_INFO_PRESENT		0x20
++#define NAN_NDP_CTRL_RESERVED			0xA0
++
++/* NDP Attribute */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_ndp_attr_s {
++	uint8 id;		/* 0x10 */
++	uint16 len;		/* length */
++	uint8 dialog_token;	/* dialog token */
++	uint8 type_status;	/* bits 0-3 type, 4-7 status */
++	uint8 reason;		/* reason code */
++	struct ether_addr init_ndi;	/* ndp initiator's data interface address */
++	uint8 ndp_id;		/* ndp identifier (created by initiator */
++	uint8 control;		/* ndp control field */
++	uint8 var[];		/* Optional fields follow */
++} BWL_POST_PACKED_STRUCT wifi_nan_ndp_attr_t;
++/* NDP attribute type and status macros */
++#define NAN_NDP_TYPE_MASK	0x0F
++#define NAN_NDP_TYPE_REQUEST	0x0
++#define NAN_NDP_TYPE_RESPONSE	0x1
++#define NAN_NDP_TYPE_CONFIRM	0x2
++#define NAN_NDP_TYPE_SECURITY	0x3
++#define NAN_NDP_TYPE_TERMINATE	0x4
++#define NAN_NDP_REQUEST(_ndp)	(((_ndp)->type_status & NAN_NDP_TYPE_MASK) == NAN_NDP_TYPE_REQUEST)
++#define NAN_NDP_RESPONSE(_ndp)	(((_ndp)->type_status & NAN_NDP_TYPE_MASK) == NAN_NDP_TYPE_RESPONSE)
++#define NAN_NDP_CONFIRM(_ndp)	(((_ndp)->type_status & NAN_NDP_TYPE_MASK) == NAN_NDP_TYPE_CONFIRM)
++#define NAN_NDP_SECURITY_INST(_ndp)	(((_ndp)->type_status & NAN_NDP_TYPE_MASK) == \
++									NAN_NDP_TYPE_SECURITY)
++#define NAN_NDP_TERMINATE(_ndp) (((_ndp)->type_status & NAN_NDP_TYPE_MASK) == \
++									NAN_NDP_TYPE_TERMINATE)
++#define NAN_NDP_STATUS_SHIFT	4
++#define NAN_NDP_STATUS_MASK	0xF0
++#define NAN_NDP_STATUS_CONT	(0 << NAN_NDP_STATUS_SHIFT)
++#define NAN_NDP_STATUS_ACCEPT	(1 << NAN_NDP_STATUS_SHIFT)
++#define NAN_NDP_STATUS_REJECT	(2 << NAN_NDP_STATUS_SHIFT)
++#define NAN_NDP_CONT(_ndp)	(((_ndp)->type_status & NAN_NDP_STATUS_MASK) == NAN_NDP_STATUS_CONT)
++#define NAN_NDP_ACCEPT(_ndp)	(((_ndp)->type_status & NAN_NDP_STATUS_MASK) == \
++									NAN_NDP_STATUS_ACCEPT)
++#define NAN_NDP_REJECT(_ndp)	(((_ndp)->type_status & NAN_NDP_STATUS_MASK) == \
++									NAN_NDP_STATUS_REJECT)
++/* NDP Setup Status */
++#define NAN_NDP_SETUP_STATUS_OK		1
++#define NAN_NDP_SETUP_STATUS_FAIL	0
++#define NAN_NDP_SETUP_STATUS_REJECT	2
++
++/* Rng setup attribute type and status macros */
++#define NAN_RNG_TYPE_MASK	0x0F
++#define NAN_RNG_TYPE_REQUEST	0x0
++#define NAN_RNG_TYPE_RESPONSE	0x1
++#define NAN_RNG_TYPE_TERMINATE	0x2
++
++#define NAN_RNG_STATUS_SHIFT	4
++#define NAN_RNG_STATUS_MASK	0xF0
++#define NAN_RNG_STATUS_ACCEPT	(0 << NAN_RNG_STATUS_SHIFT)
++#define NAN_RNG_STATUS_REJECT	(1 << NAN_RNG_STATUS_SHIFT)
++
++#define NAN_RNG_ACCEPT(_rsua)	(((_rsua)->type_status & NAN_RNG_STATUS_MASK) == \
++									NAN_RNG_STATUS_ACCEPT)
++#define NAN_RNG_REJECT(_rsua)	(((_rsua)->type_status & NAN_RNG_STATUS_MASK) == \
++									NAN_RNG_STATUS_REJECT)
++
++/* schedule entry */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_sched_entry_s {
++	uint8 map_id;		/* map id */
++	uint16 tbmp_ctrl;	/* time bitmap control */
++	uint8 tbmp_len;		/* time bitmap len */
++	uint8 tbmp[];		/* time bitmap - Optional */
++} BWL_POST_PACKED_STRUCT wifi_nan_sched_entry_t;
++
++#define NAN_SCHED_ENTRY_MIN_SIZE	OFFSETOF(wifi_nan_sched_entry_t, tbmp)
++#define NAN_SCHED_ENTRY_SIZE(_entry)	(NAN_SCHED_ENTRY_MIN_SIZE + (_entry)->tbmp_len)
++
++/* for dev cap, element container etc. */
++#define NAN_DEV_ELE_MAPID_CTRL_MASK		0x1
++#define NAN_DEV_ELE_MAPID_CTRL_SHIFT	0
++#define NAN_DEV_ELE_MAPID_MASK		0x1E
++#define NAN_DEV_ELE_MAPID_SHIFT		1
++
++#define NAN_DEV_ELE_MAPID_CTRL_SET(_mapid_field, value) \
++	do {(_mapid_field) &= ~NAN_DEV_ELE_MAPID_CTRL_MASK; \
++		(_mapid_field) |= ((value << NAN_DEV_ELE_MAPID_CTRL_SHIFT) & \
++		NAN_DEV_ELE_MAPID_CTRL_MASK); \
++	} while (0);
++
++#define NAN_DEV_ELE_MAPID_CTRL_GET(_mapid_field) \
++	(((_mapid_field) & NAN_DEV_ELE_MAPID_CTRL_MASK) >> \
++	NAN_DEV_ELE_MAPID_CTRL_SHIFT)
++
++#define NAN_DEV_ELE_MAPID_SET(_mapid_field, value) \
++	do {(_mapid_field) &= ~NAN_DEV_ELE_MAPID_MASK; \
++		(_mapid_field) |= ((value << NAN_DEV_ELE_MAPID_SHIFT) & \
++		NAN_DEV_ELE_MAPID_MASK); \
++	} while (0);
++
++#define NAN_DEV_ELE_MAPID_GET(_mapid_field) \
++	(((_mapid_field) & NAN_DEV_ELE_MAPID_MASK) >> \
++	NAN_DEV_ELE_MAPID_SHIFT)
++
++/* schedule entry map id handling */
++#define NAN_SCHED_ENTRY_MAPID_MASK		0x0F
++#define NAN_SCHED_ENTRY_MAPID_SHIFT		0
++
++#define NAN_SCHED_ENTRY_MAPID_SET(_mapid_field, value) \
++	do {(_mapid_field) &= ~NAN_SCHED_ENTRY_MAPID_MASK; \
++		(_mapid_field) |= ((value << NAN_SCHED_ENTRY_MAPID_SHIFT) & \
++		NAN_SCHED_ENTRY_MAPID_MASK); \
++	} while (0);
++
++#define NAN_SCHED_ENTRY_MAPID_GET(_mapid_field) \
++	(((_mapid_field) & NAN_SCHED_ENTRY_MAPID_MASK) >> \
++	NAN_SCHED_ENTRY_MAPID_SHIFT)
++
++/* NDC attribute */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_ndc_attr_s {
++	uint8 id;
++	uint16 len;
++	uint8 ndc_id[NAN_DATA_NDC_ID_SIZE];
++	uint8 attr_cntrl;
++	uint8 var[];
++} BWL_POST_PACKED_STRUCT wifi_nan_ndc_attr_t;
++
++/* Attribute control subfield of NDC attr */
++/* Proposed NDC */
++#define NAN_NDC_ATTR_PROPOSED_NDC_MASK	0x1
++#define NAN_NDC_ATTR_PROPOSED_NDC_SHIFT 0
++
++/* get & set */
++#define NAN_NDC_GET_PROPOSED_FLAG(_attr)	\
++	(((_attr)->attr_cntrl & NAN_NDC_ATTR_PROPOSED_NDC_MASK) >>	\
++	NAN_NDC_ATTR_PROPOSED_NDC_SHIFT)
++#define NAN_NDC_SET_PROPOSED_FLAG(_attr, value) \
++	do {((_attr)->attr_cntrl &= ~NAN_NDC_ATTR_PROPOSED_NDC_MASK); \
++		((_attr)->attr_cntrl |=	\
++		(((value) << NAN_NDC_ATTR_PROPOSED_NDC_SHIFT) & NAN_NDC_ATTR_PROPOSED_NDC_MASK)); \
++	} while (0)
++
++/* Service descriptor extension attribute */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_svc_desc_ext_attr_s {
++	/* Attribute ID - 0x11 */
++	uint8 id;
++	/* Length of the following fields in the attribute */
++	uint16 len;
++	/* Instance id of associated service descriptor attribute */
++	uint8 instance_id;
++	/* SDE control field */
++	uint16 control;
++	/* range limit, svc upd indicator etc. */
++	uint8 var[];
++} BWL_POST_PACKED_STRUCT wifi_nan_svc_desc_ext_attr_t;
++
++#define NAN_SDE_ATTR_MIN_LEN OFFSETOF(wifi_nan_svc_desc_ext_attr_t, var)
++
++/* SDEA control field bit definitions and access macros */
++#define NAN_SDE_CF_FSD_REQUIRED		(1 << 0)
++#define NAN_SDE_CF_FSD_GAS		(1 << 1)
++#define NAN_SDE_CF_DP_REQUIRED		(1 << 2)
++#define NAN_SDE_CF_DP_TYPE		(1 << 3)
++#define NAN_SDE_CF_MULTICAST_TYPE	(1 << 4)
++#define NAN_SDE_CF_QOS_REQUIRED		(1 << 5)
++#define NAN_SDE_CF_SECURITY_REQUIRED	(1 << 6)
++#define NAN_SDE_CF_RANGING_REQUIRED	(1 << 7)
++#define NAN_SDE_CF_RANGE_PRESENT	(1 << 8)
++#define NAN_SDE_CF_SVC_UPD_IND_PRESENT	(1 << 9)
++#define NAN_SDE_FSD_REQUIRED(_sde)	((_sde)->control & NAN_SDE_CF_FSD_REQUIRED)
++#define NAN_SDE_FSD_GAS(_sde)		((_sde)->control & NAN_SDE_CF_FSD_GAS)
++#define NAN_SDE_DP_REQUIRED(_sde)	((_sde)->control & NAN_SDE_CF_DP_REQUIRED)
++#define NAN_SDE_DP_MULTICAST(_sde)	((_sde)->control & NAN_SDE_CF_DP_TYPE)
++#define NAN_SDE_MULTICAST_M_TO_M(_sde)	((_sde)->control & NAN_SDE_CF_MULTICAST_TYPE)
++#define NAN_SDE_QOS_REQUIRED(_sde)	((_sde)->control & NAN_SDE_CF_QOS_REQUIRED)
++#define NAN_SDE_SECURITY_REQUIRED(_sde)	((_sde)->control & NAN_SDE_CF_SECURITY_REQUIRED)
++#define NAN_SDE_RANGING_REQUIRED(_sde)	((_sde)->control & NAN_SDE_CF_RANGING_REQUIRED)
++#define NAN_SDE_RANGE_PRESENT(_sde)	((_sde)->control & NAN_SDE_CF_RANGE_PRESENT)
++#define NAN_SDE_SVC_UPD_IND_PRESENT(_sde)	((_sde)->control & NAN_SDE_CF_SVC_UPD_IND_PRESENT)
++
++/* nan2 security */
++
++/*
++ * Cipher suite information Attribute.
++ * WFA Tech. Spec ver 1.0.r21 (section 10.7.24.2)
++ */
++#define NAN_SEC_CIPHER_SUITE_CAP_REPLAY_4     0
++#define NAN_SEC_CIPHER_SUITE_CAP_REPLAY_16    (1 << 0)
++
++/* enum security algo.
++*/
++enum nan_sec_csid {
++	NAN_SEC_ALGO_NONE = 0,
++	NAN_SEC_ALGO_NCS_SK_CCM_128 = 1,     /* CCMP 128 */
++	NAN_SEC_ALGO_NCS_SK_GCM_256 = 2,     /* GCMP 256 */
++	NAN_SEC_ALGO_LAST = 3
++};
++typedef int8 nan_sec_csid_e;
++
++/* nan2 cipher suite attribute field */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_sec_cipher_suite_field_s {
++	uint8 cipher_suite_id;
++	uint8 inst_id;	/* Instance Id */
++} BWL_POST_PACKED_STRUCT wifi_nan_sec_cipher_suite_field_t;
++
++/* nan2 cipher suite information attribute field */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_sec_cipher_suite_info_attr_s {
++	uint8 attr_id;	/* 0x22 - NAN_ATTR_CIPHER_SUITE_INFO */
++	uint16 len;
++	uint8 capabilities;
++	uint8 var[];	/* cipher suite list */
++} BWL_POST_PACKED_STRUCT wifi_nan_sec_cipher_suite_info_attr_t;
++
++/*
++ * Security context identifier attribute
++ * WFA Tech. Spec ver 1.0.r21 (section 10.7.24.4)
++ */
++
++#define NAN_SEC_CTX_ID_TYPE_PMKID   (1 << 0)
++
++/* nan2 security context identifier attribute field */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_sec_ctx_id_field_s {
++	uint16 sec_ctx_id_type_len;	/* length of security ctx identifier */
++	uint8 sec_ctx_id_type;
++	uint8 inst_id;	/* Instance Id */
++	uint8 var[];	/* security ctx identifier */
++} BWL_POST_PACKED_STRUCT wifi_nan_sec_ctx_id_field_t;
++
++/* nan2 security context identifier info attribute field */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_sec_ctx_id_info_attr_s {
++	uint8 attr_id;	/* 0x23 - NAN_ATTR_SEC_CTX_ID_INFO */
++	uint16 len;
++	uint8 var[];	/* security context identifier  list */
++} BWL_POST_PACKED_STRUCT wifi_nan_sec_ctx_id_info_attr_t;
++
++/*
++ * Nan shared key descriptor attribute
++ * WFA Tech. Spec ver 23
++ */
++
++#define NAN_SEC_NCSSK_DESC_REPLAY_CNT_LEN	8
++#define NAN_SEC_NCSSK_DESC_KEY_NONCE_LEN	32
++
++/* nan shared key descriptor attr field */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_sec_ncssk_key_desc_attr_s {
++	uint8 attr_id;	/* 0x24 - NAN_ATTR_SHARED_KEY_DESC */
++	uint16 len;
++	uint8 inst_id;  /* Publish service instance ID */
++	uint8 desc_type;
++	uint16 key_info;
++	uint16 key_len;
++	uint8 key_replay_cntr[NAN_SEC_NCSSK_DESC_REPLAY_CNT_LEN];
++	uint8 key_nonce[NAN_SEC_NCSSK_DESC_KEY_NONCE_LEN];
++	uint8 reserved[32];	/* EAPOL IV + Key RSC + Rsvd fields in EAPOL Key */
++	uint8 mic[];  /* mic + key data len + key data */
++} BWL_POST_PACKED_STRUCT wifi_nan_sec_ncssk_key_desc_attr_t;
++
++/* Key Info fields */
++#define NAN_SEC_NCSSK_DESC_MASK			0x7
++#define NAN_SEC_NCSSK_DESC_SHIFT		0
++#define NAN_SEC_NCSSK_DESC_KEY_TYPE_MASK	0x8
++#define NAN_SEC_NCSSK_DESC_KEY_TYPE_SHIFT	3
++#define NAN_SEC_NCSSK_DESC_KEY_INSTALL_MASK	0x40
++#define NAN_SEC_NCSSK_DESC_KEY_INSTALL_SHIFT	6
++#define NAN_SEC_NCSSK_DESC_KEY_ACK_MASK		0x80
++#define NAN_SEC_NCSSK_DESC_KEY_ACK_SHIFT	7
++#define NAN_SEC_NCSSK_DESC_KEY_MIC_MASK		0x100
++#define NAN_SEC_NCSSK_DESC_KEY_MIC_SHIFT	8
++#define NAN_SEC_NCSSK_DESC_KEY_SEC_MASK		0x200
++#define NAN_SEC_NCSSK_DESC_KEY_SEC_SHIFT	9
++#define NAN_SEC_NCSSK_DESC_KEY_ERR_MASK		0x400
++#define NAN_SEC_NCSSK_DESC_KEY_ERR_SHIFT	10
++#define NAN_SEC_NCSSK_DESC_KEY_REQ_MASK		0x800
++#define NAN_SEC_NCSSK_DESC_KEY_REQ_SHIFT	11
++#define NAN_SEC_NCSSK_DESC_KEY_ENC_KEY_MASK	0x1000
++#define NAN_SEC_NCSSK_DESC_KEY_ENC_KEY_SHIFT	12
++#define NAN_SEC_NCSSK_DESC_KEY_SMK_MSG_MASK	0x2000
++#define NAN_SEC_NCSSK_DESC_KEY_SMK_MSG_SHIFT	13
++
++/* Key Info get & set macros */
++#define NAN_SEC_NCSSK_KEY_DESC_VER_GET(_key_info)	\
++	(((_key_info) & NAN_SEC_NCSSK_DESC_MASK) >> NAN_SEC_NCSSK_DESC_SHIFT)
++#define NAN_SEC_NCSSK_KEY_DESC_VER_SET(_val, _key_info)	\
++	do {(_key_info) &= ~NAN_SEC_NCSSK_DESC_MASK; \
++		(_key_info) |= (((_val) << NAN_SEC_NCSSK_DESC_SHIFT) & \
++		NAN_SEC_NCSSK_DESC_MASK);} while (0)
++#define NAN_SEC_NCSSK_DESC_KEY_TYPE_GET(_key_info)	\
++	(((_key_info) & NAN_SEC_NCSSK_DESC_KEY_TYPE_MASK) >> NAN_SEC_NCSSK_DESC_KEY_TYPE_SHIFT)
++#define NAN_SEC_NCSSK_DESC_KEY_TYPE_SET(_val, _key_info)	\
++	do {(_key_info) &= ~NAN_SEC_NCSSK_DESC_KEY_TYPE_MASK; \
++		(_key_info) |= (((_val) << NAN_SEC_NCSSK_DESC_KEY_TYPE_SHIFT) & \
++		NAN_SEC_NCSSK_DESC_KEY_TYPE_MASK);} while (0)
++#define NAN_SEC_NCSSK_DESC_KEY_INSTALL_GET(_key_info)	\
++	(((_key_info) & NAN_SEC_NCSSK_DESC_KEY_INSTALL_MASK) >> \
++	NAN_SEC_NCSSK_DESC_KEY_INSTALL_SHIFT)
++#define NAN_SEC_NCSSK_DESC_KEY_INSTALL_SET(_val, _key_info)	\
++	do {(_key_info) &= ~NAN_SEC_NCSSK_DESC_KEY_INSTALL_MASK; \
++		(_key_info) |= (((_val) << NAN_SEC_NCSSK_DESC_KEY_INSTALL_SHIFT) & \
++		NAN_SEC_NCSSK_DESC_KEY_INSTALL_MASK);} while (0)
++#define NAN_SEC_NCSSK_DESC_KEY_ACK_GET(_key_info)	\
++	(((_key_info) & NAN_SEC_NCSSK_DESC_KEY_ACK_MASK) >> NAN_SEC_NCSSK_DESC_KEY_ACK_SHIFT)
++#define NAN_SEC_NCSSK_DESC_KEY_ACK_SET(_val, _key_info)	\
++	do {(_key_info) &= ~NAN_SEC_NCSSK_DESC_KEY_ACK_MASK; \
++		(_key_info) |= (((_val) << NAN_SEC_NCSSK_DESC_KEY_ACK_SHIFT) & \
++		NAN_SEC_NCSSK_DESC_KEY_ACK_MASK);} while (0)
++#define NAN_SEC_NCSSK_DESC_KEY_MIC_GET(_key_info)	\
++	(((_key_info) & NAN_SEC_NCSSK_DESC_KEY_MIC_MASK) >> NAN_SEC_NCSSK_DESC_KEY_MIC_SHIFT)
++#define NAN_SEC_NCSSK_DESC_KEY_MIC_SET(_val, _key_info)	\
++	do {(_key_info) &= ~NAN_SEC_NCSSK_DESC_KEY_MIC_MASK; \
++		(_key_info) |= (((_val) << NAN_SEC_NCSSK_DESC_KEY_MIC_SHIFT) & \
++		NAN_SEC_NCSSK_DESC_KEY_MIC_MASK);} while (0)
++#define NAN_SEC_NCSSK_DESC_KEY_SEC_GET(_key_info)	\
++	(((_key_info) & NAN_SEC_NCSSK_DESC_KEY_SEC_MASK) >> NAN_SEC_NCSSK_DESC_KEY_SEC_SHIFT)
++#define NAN_SEC_NCSSK_DESC_KEY_SEC_SET(_val, _key_info)	\
++	do {(_key_info) &= ~NAN_SEC_NCSSK_DESC_KEY_SEC_MASK; \
++		(_key_info) |= (((_val) << NAN_SEC_NCSSK_DESC_KEY_SEC_SHIFT) & \
++		NAN_SEC_NCSSK_DESC_KEY_SEC_MASK);} while (0)
++#define NAN_SEC_NCSSK_DESC_KEY_ERR_GET(_key_info)	\
++	(((_key_info) & NAN_SEC_NCSSK_DESC_KEY_ERR_MASK) >> NAN_SEC_NCSSK_DESC_KEY_ERR_SHIFT)
++#define NAN_SEC_NCSSK_DESC_KEY_ERR_SET(_val, _key_info)	\
++	do {(_key_info) &= ~NAN_SEC_NCSSK_DESC_KEY_ERR_MASK; \
++		(_key_info) |= (((_val) << NAN_SEC_NCSSK_DESC_KEY_ERR_SHIFT) & \
++		NAN_SEC_NCSSK_DESC_KEY_ERR_MASK);} while (0)
++#define NAN_SEC_NCSSK_DESC_KEY_REQ_GET(_key_info)	\
++	(((_key_info) & NAN_SEC_NCSSK_DESC_KEY_REQ_MASK) >> NAN_SEC_NCSSK_DESC_KEY_REQ_SHIFT)
++#define NAN_SEC_NCSSK_DESC_KEY_REQ_SET(_val, _key_info)	\
++	do {(_key_info) &= ~NAN_SEC_NCSSK_DESC_KEY_REQ_MASK; \
++		(_key_info) |= (((_val) << NAN_SEC_NCSSK_DESC_KEY_REQ_SHIFT) & \
++		NAN_SEC_NCSSK_DESC_KEY_REQ_MASK);} while (0)
++#define NAN_SEC_NCSSK_DESC_KEY_ENC_KEY_GET(_key_info)	\
++	(((_key_info) & NAN_SEC_NCSSK_DESC_KEY_ENC_KEY_MASK) >> \
++	NAN_SEC_NCSSK_DESC_KEY_ENC_KEY_SHIFT)
++#define NAN_SEC_NCSSK_DESC_KEY_ENC_KEY_SET(_val, _key_info)	\
++	do {(_key_info) &= ~NAN_SEC_NCSSK_DESC_KEY_ENC_KEY_MASK; \
++		(_key_info) |= (((_val) << NAN_SEC_NCSSK_DESC_KEY_ENC_KEY_SHIFT) & \
++		NAN_SEC_NCSSK_DESC_KEY_ENC_KEY_MASK);} while (0)
++#define NAN_SEC_NCSSK_DESC_KEY_SMK_MSG_GET(_key_info)	\
++	(((_key_info) & NAN_SEC_NCSSK_DESC_KEY_SMK_MSG_MASK) >> \
++	NAN_SEC_NCSSK_DESC_KEY_SMK_MSG_SHIFT)
++#define NAN_SEC_NCSSK_DESC_KEY_SMK_MSG_SET(_val, _key_info)	\
++	do {(_key_info) &= ~NAN_SEC_NCSSK_DESC_KEY_SMK_MSG_MASK; \
++		(_key_info) |= (((_val) << NAN_SEC_NCSSK_DESC_KEY_SMK_MSG_SHIFT) & \
++		NAN_SEC_NCSSK_DESC_KEY_SMK_MSG_MASK);} while (0)
++
++#define NAN_SEC_NCSSK_IEEE80211_KDESC_TYPE	2	/* IEEE 802.11 Key Descriptor Type */
++#define NAN_SEC_NCSSK_KEY_DESC_VER			0	/* NCSSK-128/256 */
++#define NAN_SEC_NCSSK_KEY_TYPE_PAIRWISE		1	/* Pairwise */
++#define NAN_SEC_NCSSK_LIFETIME_KDE			7	/* Lifetime KDE type */
++
++/* TODO include MTK related attributes */
++
++/* NAN Multicast service group(NMSG) definitions */
++/* Length of NMSG_ID -- (NDI * 2^16 + pub_id * 2^8 + Random_factor) */
++#define NAN_NMSG_ID_LEN                         8
++
++#define NAN_NMSG_TYPE_MASK			0x0F
++#define NMSG_ATTR_TYPE_STATUS_REQUEST		0x00
++#define NMSG_ATTR_TYPE_STATUS_RESPONSE		0x01
++#define NMSG_ATTR_TYPE_STATUS_CONFIRM		0x02
++#define NMSG_ATTR_TYPE_STATUS_SEC_INSTALL	0x03
++#define NMSG_ATTR_TYPE_STATUS_TERMINATE		0x04
++#define NMSG_ATTR_TYPE_STATUS_IMPLICIT_ENROL	0x05
++
++#define NMSG_ATTR_TYPE_STATUS_CONTINUED	        0x00
++#define NMSG_ATTR_TYPE_STATUS_ACCEPTED	        0x10
++#define NMSG_ATTR_TYPE_STATUS_REJECTED	        0x20
++
++#define NMSG_CTRL_PUB_ID_PRESENT                0x0001
++#define NMSG_CTRL_NMSG_ID_PRESENT               0x0002
++#define NMSG_CTRL_SECURITY_PRESENT              0x0004
++#define NMSG_CTRL_MANY_TO_MANY_PRESENT          0x0008
++#define NMSG_CTRL_SVC_INFO_PRESENT              0x0010
++
++/* NMSG attribute */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_nmsg_attr_s {
++	uint8 id; /* Attribute ID - 0x11 */
++	uint16 len; /* Length including pubid, NMSGID and svc info */
++	uint8 dialog_token;
++	uint8 type_status; /* Type and Status field byte */
++	uint8 reason_code;
++	uint8 mc_id; /* Multicast id similar to NDPID */
++	uint8 nmsg_ctrl; /* NMSG control field */
++	/* Optional publish id, NMSGID and svc info are included in var[] */
++	uint8 var[0];
++} BWL_POST_PACKED_STRUCT wifi_nan_nmsg_attr_t;
++
++#define NMSG_ATTR_MCAST_SCHED_MAP_ID_MASK     0x1E
++#define NMSG_ATTR_MCAST_SCHED_MAP_ID_SHIFT    1
++#define NMSG_ATTR_MCAST_SCHED_TIME_MAP_MASK   0x20
++#define NMSG_ATTR_MCAST_SCHED_TIME_MAP_SHIFT  5
++
++/* NAN Multicast Schedule atribute structure */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_mcast_sched_attr_s {
++	uint8 id; /* 0x16 */
++	uint16 len;
++	uint8 nmsg_id[NAN_NMSG_ID_LEN];
++	uint8 attr_cntrl;
++	uint8 sched_own[ETHER_ADDR_LEN];
++	uint8 var[]; /* multicast sched entry list (schedule_entry_list) */
++} BWL_POST_PACKED_STRUCT wifi_nan_mcast_sched_attr_t;
++
++
++/* FAC Channel Entry  (section 10.7.19.1.5) */
++typedef BWL_PRE_PACKED_STRUCT struct wifi_nan_fac_chan_entry_s {
++	uint8 oper_class;		/* Operating Class */
++	uint16 chan_bitmap;		/* Channel Bitmap */
++	uint8 primary_chan_bmp;		/* Primary Channel Bitmap */
++	uint16 aux_chan;			/* Auxiliary Channel bitmap */
++} BWL_POST_PACKED_STRUCT wifi_nan_fac_chan_entry_t;
++
++/* TODO move this from nan.h */
++#define NAN_ALL_NAN_MGMT_FRAMES (NAN_FRM_SCHED_AF | \
++	NAN_FRM_NDP_AF | NAN_FRM_NDL_AF | \
++	NAN_FRM_DISC_BCN | NAN_FRM_SYNC_BCN | \
++	NAN_FRM_SVC_DISC | NAN_FRM_RNG_REQ_AF | \
++	NAN_FRM_RNG_RESP_AF | NAN_FRM_RNG_REPORT_AF | \
++	NAN_FRM_RNG_TERM_AF)
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++#endif /* _NAN_H_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/osl.h b/module_drivers/drivers/net/wireless/bcmdhd/include/osl.h
+new file mode 100644
+index 000000000..082b30152
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/osl.h
+@@ -0,0 +1,260 @@
++/*
++ * OS Abstraction Layer
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: osl.h 642189 2016-06-07 21:12:50Z $
++ */
++
++#ifndef _osl_h_
++#define _osl_h_
++
++#include <osl_decl.h>
++
++#define OSL_PKTTAG_SZ	32 /* Size of PktTag */
++
++/* Drivers use PKTFREESETCB to register a callback function when a packet is freed by OSL */
++typedef void (*pktfree_cb_fn_t)(void *ctx, void *pkt, unsigned int status);
++
++/* Drivers use REGOPSSET() to register register read/write funcitons */
++typedef unsigned int (*osl_rreg_fn_t)(void *ctx, volatile void *reg, unsigned int size);
++typedef void  (*osl_wreg_fn_t)(void *ctx, volatile void *reg, unsigned int val, unsigned int size);
++
++
++#if defined(WL_UNITTEST)
++#include <utest_osl.h>
++#else
++#include <linux_osl.h>
++#endif 
++
++#ifndef PKTDBG_TRACE
++#define PKTDBG_TRACE(osh, pkt, bit)	BCM_REFERENCE(osh)
++#endif
++
++#define PKTCTFMAP(osh, p)		BCM_REFERENCE(osh)
++
++/* --------------------------------------------------------------------------
++** Register manipulation macros.
++*/
++
++#define	SET_REG(osh, r, mask, val)	W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val)))
++
++#ifndef AND_REG
++#define AND_REG(osh, r, v)		W_REG(osh, (r), R_REG(osh, r) & (v))
++#endif   /* !AND_REG */
++
++#ifndef OR_REG
++#define OR_REG(osh, r, v)		W_REG(osh, (r), R_REG(osh, r) | (v))
++#endif   /* !OR_REG */
++
++#if !defined(OSL_SYSUPTIME)
++#define OSL_SYSUPTIME() (0)
++#define OSL_SYSUPTIME_SUPPORT FALSE
++#else
++#define OSL_SYSUPTIME_SUPPORT TRUE
++#endif /* OSL_SYSUPTIME */
++
++#if !defined(OSL_SYSUPTIME_US)
++#define OSL_SYSUPTIME_US() (0)
++#endif /* OSL_SYSUPTIME */
++
++#ifndef OSL_SYS_HALT
++#define OSL_SYS_HALT()	do {} while (0)
++#endif
++
++#ifndef OSL_MEM_AVAIL
++#define OSL_MEM_AVAIL()	(0xffffffff)
++#endif
++
++#if !(defined(PKTC) || defined(PKTC_DONGLE))
++
++#ifndef OSL_OBFUSCATE_BUF
++/* For security reasons printing pointers is not allowed.
++ * Some OSLs implement OSL_OBFUSCATE_BUF to OS specific obfuscate API.
++ * If OSL_OBFUSCATE_BUF() is not implemented in OSL, then default to
++ * printing the input pointer
++ */
++#define OSL_OBFUSCATE_BUF(x) (x)
++#endif /* OSL_OBFUSCATE_BUF */
++
++#define	PKTCGETATTR(skb)	(0)
++#define	PKTCSETATTR(skb, f, p, b) BCM_REFERENCE(skb)
++#define	PKTCCLRATTR(skb)	BCM_REFERENCE(skb)
++#define	PKTCCNT(skb)		(1)
++#define	PKTCLEN(skb)		PKTLEN(NULL, skb)
++#define	PKTCGETFLAGS(skb)	(0)
++#define	PKTCSETFLAGS(skb, f)	BCM_REFERENCE(skb)
++#define	PKTCCLRFLAGS(skb)	BCM_REFERENCE(skb)
++#define	PKTCFLAGS(skb)		(0)
++#define	PKTCSETCNT(skb, c)	BCM_REFERENCE(skb)
++#define	PKTCINCRCNT(skb)	BCM_REFERENCE(skb)
++#define	PKTCADDCNT(skb, c)	BCM_REFERENCE(skb)
++#define	PKTCSETLEN(skb, l)	BCM_REFERENCE(skb)
++#define	PKTCADDLEN(skb, l)	BCM_REFERENCE(skb)
++#define	PKTCSETFLAG(skb, fb)	BCM_REFERENCE(skb)
++#define	PKTCCLRFLAG(skb, fb)	BCM_REFERENCE(skb)
++#define	PKTCLINK(skb)		NULL
++#define	PKTSETCLINK(skb, x)	BCM_REFERENCE(skb)
++#define FOREACH_CHAINED_PKT(skb, nskb) \
++	for ((nskb) = NULL; (skb) != NULL; (skb) = (nskb))
++#define	PKTCFREE		PKTFREE
++#define PKTCENQTAIL(h, t, p) \
++do { \
++	if ((t) == NULL) { \
++		(h) = (t) = (p); \
++	} \
++} while (0)
++#endif /* !linux || !PKTC */
++
++#if !(defined(HNDCTF) || defined(PKTC_TX_DONGLE) || defined(PKTC))
++#define PKTSETCHAINED(osh, skb)		BCM_REFERENCE(osh)
++#define PKTCLRCHAINED(osh, skb)		BCM_REFERENCE(osh)
++#define PKTISCHAINED(skb)		FALSE
++#endif
++
++/* Lbuf with fraglist */
++#ifndef PKTFRAGPKTID
++#define PKTFRAGPKTID(osh, lb)		(0)
++#endif
++#ifndef PKTSETFRAGPKTID
++#define PKTSETFRAGPKTID(osh, lb, id)	BCM_REFERENCE(osh)
++#endif
++#ifndef PKTFRAGTOTNUM
++#define PKTFRAGTOTNUM(osh, lb)		(0)
++#endif
++#ifndef PKTSETFRAGTOTNUM
++#define PKTSETFRAGTOTNUM(osh, lb, tot)	BCM_REFERENCE(osh)
++#endif
++#ifndef PKTFRAGTOTLEN
++#define PKTFRAGTOTLEN(osh, lb)		(0)
++#endif
++#ifndef PKTSETFRAGTOTLEN
++#define PKTSETFRAGTOTLEN(osh, lb, len)	BCM_REFERENCE(osh)
++#endif
++#ifndef PKTIFINDEX
++#define PKTIFINDEX(osh, lb)		(0)
++#endif
++#ifndef PKTSETIFINDEX
++#define PKTSETIFINDEX(osh, lb, idx)	BCM_REFERENCE(osh)
++#endif
++#ifndef PKTGETLF
++#define	PKTGETLF(osh, len, send, lbuf_type)	(0)
++#endif
++
++/* in rx path, reuse totlen as used len */
++#ifndef PKTFRAGUSEDLEN
++#define PKTFRAGUSEDLEN(osh, lb)			(0)
++#endif
++#ifndef PKTSETFRAGUSEDLEN
++#define PKTSETFRAGUSEDLEN(osh, lb, len)		BCM_REFERENCE(osh)
++#endif
++#ifndef PKTFRAGLEN
++#define PKTFRAGLEN(osh, lb, ix)			(0)
++#endif
++#ifndef PKTSETFRAGLEN
++#define PKTSETFRAGLEN(osh, lb, ix, len)		BCM_REFERENCE(osh)
++#endif
++#ifndef PKTFRAGDATA_LO
++#define PKTFRAGDATA_LO(osh, lb, ix)		(0)
++#endif
++#ifndef PKTSETFRAGDATA_LO
++#define PKTSETFRAGDATA_LO(osh, lb, ix, addr)	BCM_REFERENCE(osh)
++#endif
++#ifndef PKTFRAGDATA_HI
++#define PKTFRAGDATA_HI(osh, lb, ix)		(0)
++#endif
++#ifndef PKTSETFRAGDATA_HI
++#define PKTSETFRAGDATA_HI(osh, lb, ix, addr)	BCM_REFERENCE(osh)
++#endif
++
++/* RX FRAG */
++#ifndef PKTISRXFRAG
++#define PKTISRXFRAG(osh, lb)    	(0)
++#endif
++#ifndef PKTSETRXFRAG
++#define PKTSETRXFRAG(osh, lb)		BCM_REFERENCE(osh)
++#endif
++#ifndef PKTRESETRXFRAG
++#define PKTRESETRXFRAG(osh, lb)		BCM_REFERENCE(osh)
++#endif
++
++/* TX FRAG */
++#ifndef PKTISTXFRAG
++#define PKTISTXFRAG(osh, lb)		(0)
++#endif
++#ifndef PKTSETTXFRAG
++#define PKTSETTXFRAG(osh, lb)		BCM_REFERENCE(osh)
++#endif
++
++/* Need Rx completion used for AMPDU reordering */
++#ifndef PKTNEEDRXCPL
++#define PKTNEEDRXCPL(osh, lb)           (TRUE)
++#endif
++#ifndef PKTSETNORXCPL
++#define PKTSETNORXCPL(osh, lb)          BCM_REFERENCE(osh)
++#endif
++#ifndef PKTRESETNORXCPL
++#define PKTRESETNORXCPL(osh, lb)        BCM_REFERENCE(osh)
++#endif
++#ifndef PKTISFRAG
++#define PKTISFRAG(osh, lb)		(0)
++#endif
++#ifndef PKTFRAGISCHAINED
++#define PKTFRAGISCHAINED(osh, i)	(0)
++#endif
++/* TRIM Tail bytes from lfrag */
++#ifndef PKTFRAG_TRIM_TAILBYTES
++#define PKTFRAG_TRIM_TAILBYTES(osh, p, len, type)	PKTSETLEN(osh, p, PKTLEN(osh, p) - len)
++#endif
++#ifndef PKTISHDRCONVTD
++#define PKTISHDRCONVTD(osh, lb)		(0)
++#endif
++
++#ifdef BCM_SECURE_DMA
++#define SECURE_DMA_ENAB(osh) (1)
++#else
++
++#define SECURE_DMA_ENAB(osh) (0)
++#ifndef BCMDMA64OSL
++#define	SECURE_DMA_MAP(osh, va, size, direction, p, dmah, pcma, offset) ((dmaaddr_t) ((0)))
++#else
++#define	SECURE_DMA_MAP(osh, va, size, direction, p, dmah, pcma, offset) ((dmaaddr_t) {(0)})
++#endif
++#define	SECURE_DMA_DD_MAP(osh, va, size, direction, p, dmah) 0
++#ifndef BCMDMA64OSL
++#define	SECURE_DMA_MAP_TXMETA(osh, va, size, direction, p, dmah, pcma) ((dmaaddr_t) ((0)))
++#else
++#define	SECURE_DMA_MAP_TXMETA(osh, va, size, direction, p, dmah, pcma) ((dmaaddr_t) {(0)})
++#endif
++#define	SECURE_DMA_UNMAP(osh, pa, size, direction, p, dmah, pcma, offset)
++#define	SECURE_DMA_UNMAP_ALL(osh, pcma)
++
++#endif /* BCMDMA64OSL */
++
++
++#ifndef ROMMABLE_ASSERT
++#define ROMMABLE_ASSERT(exp) ASSERT(exp)
++#endif /* ROMMABLE_ASSERT */
++
++#endif	/* _osl_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/osl_decl.h b/module_drivers/drivers/net/wireless/bcmdhd/include/osl_decl.h
+new file mode 100644
+index 000000000..977a1ca46
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/osl_decl.h
+@@ -0,0 +1,37 @@
++/*
++ * osl forward declarations
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: osl_decl.h 596126 2015-10-29 19:53:48Z $
++ */
++
++#ifndef _osl_decl_h_
++#define _osl_decl_h_
++
++/* osl handle type forward declaration */
++typedef struct osl_info osl_t;
++typedef struct osl_dmainfo osldma_t;
++extern unsigned int lmtest; /* low memory test */
++#endif
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/osl_ext.h b/module_drivers/drivers/net/wireless/bcmdhd/include/osl_ext.h
+new file mode 100644
+index 000000000..2503f6a37
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/osl_ext.h
+@@ -0,0 +1,697 @@
++/*
++ * OS Abstraction Layer Extension - the APIs defined by the "extension" API
++ * are only supported by a subset of all operating systems.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: osl_ext.h 611959 2016-01-12 15:23:56Z $
++ */
++
++#ifndef _osl_ext_h_
++#define _osl_ext_h_
++
++
++/* ---- Include Files ---------------------------------------------------- */
++
++#if defined(TARGETOS_symbian)
++	#include <e32def.h>
++	#include <symbian_osl_ext.h>
++#elif defined(THREADX)
++	#include <threadx_osl_ext.h>
++#else
++	#define OSL_EXT_DISABLED
++#endif
++
++/* Include base operating system abstraction. */
++#include <osl.h>
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* ---- Constants and Types ---------------------------------------------- */
++
++/* -----------------------------------------------------------------------
++ * Generic OS types.
++ */
++typedef enum osl_ext_status_t
++{
++	OSL_EXT_SUCCESS,
++	OSL_EXT_ERROR,
++	OSL_EXT_TIMEOUT
++
++} osl_ext_status_t;
++#define OSL_EXT_STATUS_DECL(status)	osl_ext_status_t status;
++
++#define OSL_EXT_TIME_FOREVER ((osl_ext_time_ms_t)(-1))
++typedef unsigned int osl_ext_time_ms_t;
++
++typedef unsigned int osl_ext_event_bits_t;
++
++typedef unsigned int osl_ext_interrupt_state_t;
++
++/* -----------------------------------------------------------------------
++ * Timers.
++ */
++typedef enum
++{
++	/* One-shot timer. */
++	OSL_EXT_TIMER_MODE_ONCE,
++
++	/* Periodic timer. */
++	OSL_EXT_TIMER_MODE_REPEAT
++
++} osl_ext_timer_mode_t;
++
++/* User registered callback and parameter to invoke when timer expires. */
++typedef void* osl_ext_timer_arg_t;
++typedef void (*osl_ext_timer_callback)(osl_ext_timer_arg_t arg);
++
++
++/* -----------------------------------------------------------------------
++ * Tasks.
++ */
++
++/* Task entry argument. */
++typedef void* osl_ext_task_arg_t;
++
++/* Task entry function. */
++typedef void (*osl_ext_task_entry)(osl_ext_task_arg_t arg);
++
++/* Abstract task priority levels. */
++typedef enum
++{
++	OSL_EXT_TASK_IDLE_PRIORITY,
++	OSL_EXT_TASK_LOW_PRIORITY,
++	OSL_EXT_TASK_LOW_NORMAL_PRIORITY,
++	OSL_EXT_TASK_NORMAL_PRIORITY,
++	OSL_EXT_TASK_HIGH_NORMAL_PRIORITY,
++	OSL_EXT_TASK_HIGHEST_PRIORITY,
++	OSL_EXT_TASK_TIME_CRITICAL_PRIORITY,
++
++	/* This must be last. */
++	OSL_EXT_TASK_NUM_PRIORITES
++} osl_ext_task_priority_t;
++
++
++#ifndef OSL_EXT_DISABLED
++
++/* ---- Variable Externs ------------------------------------------------- */
++/* ---- Function Prototypes ---------------------------------------------- */
++
++
++/* --------------------------------------------------------------------------
++** Semaphore
++*/
++
++/****************************************************************************
++* Function:   osl_ext_sem_create
++*
++* Purpose:    Creates a counting semaphore object, which can subsequently be
++*             used for thread notification.
++*
++* Parameters: name     (in)  Name to assign to the semaphore (must be unique).
++*             init_cnt (in)  Initial count that the semaphore should have.
++*             sem      (out) Newly created semaphore.
++*
++* Returns:    OSL_EXT_SUCCESS if the semaphore was created successfully, or an
++*             error code if the semaphore could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_sem_create(char *name, int init_cnt, osl_ext_sem_t *sem);
++
++/****************************************************************************
++* Function:   osl_ext_sem_delete
++*
++* Purpose:    Destroys a previously created semaphore object.
++*
++* Parameters: sem (mod) Semaphore object to destroy.
++*
++* Returns:    OSL_EXT_SUCCESS if the semaphore was deleted successfully, or an
++*             error code if the semaphore could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_sem_delete(osl_ext_sem_t *sem);
++
++/****************************************************************************
++* Function:   osl_ext_sem_give
++*
++* Purpose:    Increments the count associated with the semaphore. This will
++*             cause one thread blocked on a take to wake up.
++*
++* Parameters: sem (mod) Semaphore object to give.
++*
++* Returns:    OSL_EXT_SUCCESS if the semaphore was given successfully, or an
++*             error code if the semaphore could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_sem_give(osl_ext_sem_t *sem);
++
++/****************************************************************************
++* Function:   osl_ext_sem_take
++*
++* Purpose:    Decrements the count associated with the semaphore. If the count
++*             is less than zero, then the calling task will become blocked until
++*             another thread does a give on the semaphore. This function will only
++*             block the calling thread for timeout_msec milliseconds, before
++*             returning with OSL_EXT_TIMEOUT.
++*
++* Parameters: sem          (mod) Semaphore object to take.
++*             timeout_msec (in)  Number of milliseconds to wait for the
++*                                semaphore to enter a state where it can be
++*                                taken.
++*
++* Returns:    OSL_EXT_SUCCESS if the semaphore was taken successfully, or an
++*             error code if the semaphore could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_sem_take(osl_ext_sem_t *sem, osl_ext_time_ms_t timeout_msec);
++
++
++/* --------------------------------------------------------------------------
++** Mutex
++*/
++
++/****************************************************************************
++* Function:   osl_ext_mutex_create
++*
++* Purpose:    Creates a mutex object, which can subsequently be used to control
++*             mutually exclusion of resources.
++*
++* Parameters: name  (in)  Name to assign to the mutex (must be unique).
++*             mutex (out) Mutex object to initialize.
++*
++* Returns:    OSL_EXT_SUCCESS if the mutex was created successfully, or an
++*             error code if the mutex could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_mutex_create(char *name, osl_ext_mutex_t *mutex);
++
++/****************************************************************************
++* Function:   osl_ext_mutex_delete
++*
++* Purpose:    Destroys a previously created mutex object.
++*
++* Parameters: mutex (mod) Mutex object to destroy.
++*
++* Returns:    OSL_EXT_SUCCESS if the mutex was deleted successfully, or an
++*             error code if the mutex could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_mutex_delete(osl_ext_mutex_t *mutex);
++
++/****************************************************************************
++* Function:   osl_ext_mutex_acquire
++*
++* Purpose:    Acquires the indicated mutual exclusion object. If the object is
++*             currently acquired by another task, then this function will wait
++*             for timeout_msec milli-seconds before returning with OSL_EXT_TIMEOUT.
++*
++* Parameters: mutex        (mod) Mutex object to acquire.
++*             timeout_msec (in)  Number of milliseconds to wait for the mutex.
++*
++* Returns:    OSL_EXT_SUCCESS if the mutex was acquired successfully, or an
++*             error code if the mutex could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_mutex_acquire(osl_ext_mutex_t *mutex, osl_ext_time_ms_t timeout_msec);
++
++/****************************************************************************
++* Function:   osl_ext_mutex_release
++*
++* Purpose:    Releases the indicated mutual exclusion object. This makes it
++*             available for another task to acquire.
++*
++* Parameters: mutex (mod) Mutex object to release.
++*
++* Returns:    OSL_EXT_SUCCESS if the mutex was released successfully, or an
++*             error code if the mutex could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_mutex_release(osl_ext_mutex_t *mutex);
++
++
++/* --------------------------------------------------------------------------
++** Timers
++*/
++
++/****************************************************************************
++* Function:   osl_ext_timer_create
++*
++* Purpose:    Creates a timer object.
++*
++* Parameters: name (in)         Name of timer.
++*             timeout_msec (in) Invoke callback after this number of milliseconds.
++*             mode (in)         One-shot or periodic timer.
++*             func (in)         Callback function to invoke on timer expiry.
++*             arg (in)          Argument to callback function.
++*             timer (out)       Timer object to create.
++*
++* Note: The function callback occurs in interrupt context. The application is
++*       required to provide context switch for the callback if required.
++*
++* Returns:    OSL_EXT_SUCCESS if the timer was created successfully, or an
++*             error code if the timer could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t
++osl_ext_timer_create(char *name, osl_ext_time_ms_t timeout_msec, osl_ext_timer_mode_t mode,
++                 osl_ext_timer_callback func, osl_ext_timer_arg_t arg, osl_ext_timer_t *timer);
++
++/****************************************************************************
++* Function:   osl_ext_timer_delete
++*
++* Purpose:    Destroys a previously created timer object.
++*
++* Parameters: timer (mod) Timer object to destroy.
++*
++* Returns:    OSL_EXT_SUCCESS if the timer was created successfully, or an
++*             error code if the timer could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_timer_delete(osl_ext_timer_t *timer);
++
++/****************************************************************************
++* Function:   osl_ext_timer_start
++*
++* Purpose:    Start a previously created timer object.
++*
++* Parameters: timer (in)        Timer object.
++*             timeout_msec (in) Invoke callback after this number of milliseconds.
++*             mode (in)         One-shot or periodic timer.
++*
++* Returns:    OSL_EXT_SUCCESS if the timer was created successfully, or an
++*             error code if the timer could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t
++osl_ext_timer_start(osl_ext_timer_t *timer,
++	osl_ext_time_ms_t timeout_msec, osl_ext_timer_mode_t mode);
++
++/****************************************************************************
++* Function:   osl_ext_timer_stop
++*
++* Purpose:    Stop a previously created timer object.
++*
++* Parameters: timer (in)        Timer object.
++*
++* Returns:    OSL_EXT_SUCCESS if the timer was created successfully, or an
++*             error code if the timer could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t
++osl_ext_timer_stop(osl_ext_timer_t *timer);
++
++/****************************************************************************
++* Function:   osl_ext_time_get
++*
++* Purpose:    Returns incrementing time counter.
++*
++* Parameters: None.
++*
++* Returns:    Returns incrementing time counter in msec.
++*****************************************************************************
++*/
++osl_ext_time_ms_t osl_ext_time_get(void);
++
++/* --------------------------------------------------------------------------
++** Tasks
++*/
++
++/****************************************************************************
++* Function:   osl_ext_task_create
++*
++* Purpose:    Create a task.
++*
++* Parameters: name       (in)  Pointer to task string descriptor.
++*             stack      (in)  Pointer to stack. NULL to allocate.
++*             stack_size (in)  Stack size - in bytes.
++*             priority   (in)  Abstract task priority.
++*             func       (in)  A pointer to the task entry point function.
++*             arg        (in)  Value passed into task entry point function.
++*             task       (out) Task to create.
++*
++* Returns:    OSL_EXT_SUCCESS if the task was created successfully, or an
++*             error code if the task could not be created.
++*****************************************************************************
++*/
++
++#define osl_ext_task_create(name, stack, stack_size, priority, func, arg, task) \
++	   osl_ext_task_create_ex((name), (stack), (stack_size), (priority), 0, (func), \
++	   (arg), (task))
++
++osl_ext_status_t osl_ext_task_create_ex(char* name,
++	void *stack, unsigned int stack_size, osl_ext_task_priority_t priority,
++	osl_ext_time_ms_t timslice_msec, osl_ext_task_entry func, osl_ext_task_arg_t arg,
++	osl_ext_task_t *task);
++
++/****************************************************************************
++* Function:   osl_ext_task_delete
++*
++* Purpose:    Destroy a task.
++*
++* Parameters: task (mod) Task to destroy.
++*
++* Returns:    OSL_EXT_SUCCESS if the task was created successfully, or an
++*             error code if the task could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_task_delete(osl_ext_task_t *task);
++
++
++/****************************************************************************
++* Function:   osl_ext_task_is_running
++*
++* Purpose:    Returns current running task.
++*
++* Parameters: None.
++*
++* Returns:    osl_ext_task_t of current running task.
++*****************************************************************************
++*/
++osl_ext_task_t *osl_ext_task_current(void);
++
++
++/****************************************************************************
++* Function:   osl_ext_task_yield
++*
++* Purpose:    Yield the CPU to other tasks of the same priority that are
++*             ready-to-run.
++*
++* Parameters: None.
++*
++* Returns:    OSL_EXT_SUCCESS if successful, else error code.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_task_yield(void);
++
++
++/****************************************************************************
++* Function:   osl_ext_task_enable_stack_check
++*
++* Purpose:    Enable task stack checking.
++*
++* Parameters: None.
++*
++* Returns:    OSL_EXT_SUCCESS if successful, else error code.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_task_enable_stack_check(void);
++
++
++/* --------------------------------------------------------------------------
++** Queue
++*/
++
++/****************************************************************************
++* Function:   osl_ext_queue_create
++*
++* Purpose:    Create a queue.
++*
++* Parameters: name     (in)  Name to assign to the queue (must be unique).
++*             buffer   (in)  Queue buffer. NULL to allocate.
++*             size     (in)  Size of the queue.
++*             queue    (out) Newly created queue.
++*
++* Returns:    OSL_EXT_SUCCESS if the queue was created successfully, or an
++*             error code if the queue could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_queue_create(char *name,
++	void *queue_buffer, unsigned int queue_size,
++	osl_ext_queue_t *queue);
++
++/****************************************************************************
++* Function:   osl_ext_queue_delete
++*
++* Purpose:    Destroys a previously created queue object.
++*
++* Parameters: queue    (mod) Queue object to destroy.
++*
++* Returns:    OSL_EXT_SUCCESS if the queue was deleted successfully, or an
++*             error code if the queue could not be deleteed.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_queue_delete(osl_ext_queue_t *queue);
++
++/****************************************************************************
++* Function:   osl_ext_queue_send
++*
++* Purpose:    Send/add data to the queue. This function will not block the
++*             calling thread if the queue is full.
++*
++* Parameters: queue    (mod) Queue object.
++*             data     (in)  Data pointer to be queued.
++*
++* Returns:    OSL_EXT_SUCCESS if the data was queued successfully, or an
++*             error code if the data could not be queued.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_queue_send(osl_ext_queue_t *queue, void *data);
++
++/****************************************************************************
++* Function:   osl_ext_queue_send_synchronous
++*
++* Purpose:    Send/add data to the queue. This function will block the
++*             calling thread until the data is dequeued.
++*
++* Parameters: queue    (mod) Queue object.
++*             data     (in)  Data pointer to be queued.
++*
++* Returns:    OSL_EXT_SUCCESS if the data was queued successfully, or an
++*             error code if the data could not be queued.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_queue_send_synchronous(osl_ext_queue_t *queue, void *data);
++
++/****************************************************************************
++* Function:   osl_ext_queue_receive
++*
++* Purpose:    Receive/remove data from the queue. This function will only
++*             block the calling thread for timeout_msec milliseconds, before
++*             returning with OSL_EXT_TIMEOUT.
++*
++* Parameters: queue        (mod) Queue object.
++*             timeout_msec (in)  Number of milliseconds to wait for the
++*                                data from the queue.
++*             data         (out) Data pointer received/removed from the queue.
++*
++* Returns:    OSL_EXT_SUCCESS if the data was dequeued successfully, or an
++*             error code if the data could not be dequeued.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_queue_receive(osl_ext_queue_t *queue,
++                 osl_ext_time_ms_t timeout_msec, void **data);
++
++/****************************************************************************
++* Function:   osl_ext_queue_count
++*
++* Purpose:    Returns the number of items in the queue.
++*
++* Parameters: queue        (mod) Queue object.
++*             count        (out) Data pointer received/removed from the queue.
++*
++* Returns:    OSL_EXT_SUCCESS if the count was returned successfully, or an
++*             error code if the count is invalid.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_queue_count(osl_ext_queue_t *queue, int *count);
++
++
++/* --------------------------------------------------------------------------
++** Event
++*/
++
++/****************************************************************************
++* Function:   osl_ext_event_create
++*
++* Purpose:    Creates a event object, which can subsequently be used to
++*             notify and trigger tasks.
++*
++* Parameters: name  (in)  Name to assign to the event (must be unique).
++*             event (out) Event object to initialize.
++*
++* Returns:    OSL_EXT_SUCCESS if the event was created successfully, or an
++*             error code if the event could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_event_create(char *name, osl_ext_event_t *event);
++
++/****************************************************************************
++* Function:   osl_ext_event_delete
++*
++* Purpose:    Destroys a previously created event object.
++*
++* Parameters: event (mod) Event object to destroy.
++*
++* Returns:    OSL_EXT_SUCCESS if the event was created successfully, or an
++*             error code if the event could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_event_delete(osl_ext_event_t *event);
++
++/****************************************************************************
++* Function:   osl_ext_event_get
++*
++* Purpose:    Get event from specified event object.
++*
++* Parameters: event        (mod) Event object to get.
++*             requested    (in)  Requested event to get.
++*             timeout_msec (in)  Number of milliseconds to wait for the event.
++*             event_bits   (out) Event bits retrieved.
++*
++* Returns:    OSL_EXT_SUCCESS if the event was created successfully, or an
++*             error code if the event could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_event_get(osl_ext_event_t *event,
++	osl_ext_event_bits_t requested,	osl_ext_time_ms_t timeout_msec,
++	osl_ext_event_bits_t *event_bits);
++
++/****************************************************************************
++* Function:   osl_ext_event_set
++*
++* Purpose:    Set event of specified event object.
++*
++* Parameters: event      (mod) Event object to set.
++*             event_bits (in)  Event bits to set.
++*
++* Returns:    OSL_EXT_SUCCESS if the event was created successfully, or an
++*             error code if the event could not be created.
++*****************************************************************************
++*/
++osl_ext_status_t osl_ext_event_set(osl_ext_event_t *event,
++	osl_ext_event_bits_t event_bits);
++
++
++/* --------------------------------------------------------------------------
++** Interrupt
++*/
++
++/****************************************************************************
++* Function:   osl_ext_interrupt_disable
++*
++* Purpose:    Disable CPU interrupt.
++*
++* Parameters: None.
++*
++* Returns:    The interrupt state before disable for restoring interrupt.
++*****************************************************************************
++*/
++osl_ext_interrupt_state_t osl_ext_interrupt_disable(void);
++
++
++/****************************************************************************
++* Function:   osl_ext_interrupt_restore
++*
++* Purpose:    Restore CPU interrupt state.
++*
++* Parameters: state (in)  Interrupt state to restore returned from
++*                         osl_ext_interrupt_disable().
++*
++* Returns:   None.
++*****************************************************************************
++*/
++void osl_ext_interrupt_restore(osl_ext_interrupt_state_t state);
++
++#else
++
++/* ---- Constants and Types ---------------------------------------------- */
++
++/* Semaphore. */
++#define osl_ext_sem_t
++#define OSL_EXT_SEM_DECL(sem)
++
++/* Mutex. */
++#define osl_ext_mutex_t
++#define OSL_EXT_MUTEX_DECL(mutex)
++
++/* Timer. */
++#define osl_ext_timer_t
++#define OSL_EXT_TIMER_DECL(timer)
++
++/* Task. */
++#define osl_ext_task_t void
++#define OSL_EXT_TASK_DECL(task)
++
++/* Queue. */
++#define osl_ext_queue_t
++#define OSL_EXT_QUEUE_DECL(queue)
++
++/* Event. */
++#define osl_ext_event_t
++#define OSL_EXT_EVENT_DECL(event)
++
++/* ---- Variable Externs ------------------------------------------------- */
++/* ---- Function Prototypes ---------------------------------------------- */
++
++#define osl_ext_sem_create(name, init_cnt, sem)		(OSL_EXT_SUCCESS)
++#define osl_ext_sem_delete(sem)				(OSL_EXT_SUCCESS)
++#define osl_ext_sem_give(sem)				(OSL_EXT_SUCCESS)
++#define osl_ext_sem_take(sem, timeout_msec)		(OSL_EXT_SUCCESS)
++
++#define osl_ext_mutex_create(name, mutex)		(OSL_EXT_SUCCESS)
++#define osl_ext_mutex_delete(mutex)			(OSL_EXT_SUCCESS)
++#define osl_ext_mutex_acquire(mutex, timeout_msec)	(OSL_EXT_SUCCESS)
++#define osl_ext_mutex_release(mutex)			(OSL_EXT_SUCCESS)
++
++#define osl_ext_timer_create(name, timeout_msec, mode, func, arg, timer) \
++	(OSL_EXT_SUCCESS)
++#define osl_ext_timer_delete(timer)			(OSL_EXT_SUCCESS)
++#define osl_ext_timer_start(timer, timeout_msec, mode)	(OSL_EXT_SUCCESS)
++#define osl_ext_timer_stop(timer)			(OSL_EXT_SUCCESS)
++#define osl_ext_time_get()				(0)
++
++#define osl_ext_task_create(name, stack, stack_size, priority, func, arg, task) \
++	(OSL_EXT_SUCCESS)
++#define osl_ext_task_delete(task)			(OSL_EXT_SUCCESS)
++#define osl_ext_task_current()				(NULL)
++#define osl_ext_task_yield()				(OSL_EXT_SUCCESS)
++#define osl_ext_task_enable_stack_check()		(OSL_EXT_SUCCESS)
++
++#define osl_ext_queue_create(name, queue_buffer, queue_size, queue) \
++	(OSL_EXT_SUCCESS)
++#define osl_ext_queue_delete(queue)			(OSL_EXT_SUCCESS)
++#define osl_ext_queue_send(queue, data)			(OSL_EXT_SUCCESS)
++#define osl_ext_queue_send_synchronous(queue, data)	(OSL_EXT_SUCCESS)
++#define osl_ext_queue_receive(queue, timeout_msec, data) \
++	(OSL_EXT_SUCCESS)
++#define osl_ext_queue_count(queue, count)		(OSL_EXT_SUCCESS)
++
++#define osl_ext_event_create(name, event)		(OSL_EXT_SUCCESS)
++#define osl_ext_event_delete(event)			(OSL_EXT_SUCCESS)
++#define osl_ext_event_get(event, requested, timeout_msec, event_bits) \
++	(OSL_EXT_SUCCESS)
++#define osl_ext_event_set(event, event_bits)		(OSL_EXT_SUCCESS)
++
++#define osl_ext_interrupt_disable(void)
++#define osl_ext_interrupt_restore(state)
++
++#endif	/* OSL_EXT_DISABLED */
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif	/* _osl_ext_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/p2p.h b/module_drivers/drivers/net/wireless/bcmdhd/include/p2p.h
+new file mode 100644
+index 000000000..cc7aa686e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/p2p.h
+@@ -0,0 +1,713 @@
++/*
++ * Fundamental types and constants relating to WFA P2P (aka WiFi Direct)
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: p2p.h 700076 2017-05-17 14:42:22Z $
++ */
++
++#ifndef _P2P_H_
++#define _P2P_H_
++
++#ifndef _TYPEDEFS_H_
++#include <typedefs.h>
++#endif
++#include <wlioctl.h>
++#include <802.11.h>
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++
++
++/* WiFi P2P OUI values */
++#define P2P_OUI			WFA_OUI			/* WiFi P2P OUI */
++#define P2P_VER			WFA_OUI_TYPE_P2P	/* P2P version: 9=WiFi P2P v1.0 */
++
++#define P2P_IE_ID		0xdd			/* P2P IE element ID */
++
++/* WiFi P2P IE */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_ie {
++	uint8	id;		/* IE ID: 0xDD */
++	uint8	len;		/* IE length */
++	uint8	OUI[3];		/* WiFi P2P specific OUI: P2P_OUI */
++	uint8	oui_type;	/* Identifies P2P version: P2P_VER */
++	uint8	subelts[1];	/* variable length subelements */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_ie wifi_p2p_ie_t;
++
++#define P2P_IE_FIXED_LEN	6
++
++#define P2P_ATTR_ID_OFF		0
++#define P2P_ATTR_LEN_OFF	1
++#define P2P_ATTR_DATA_OFF	3
++
++#define P2P_ATTR_ID_LEN		1	/* ID filed length */
++#define P2P_ATTR_LEN_LEN	2	/* length field length */
++#define P2P_ATTR_HDR_LEN	3 /* ID + 2-byte length field spec 1.02 */
++
++#define P2P_WFDS_HASH_LEN		6
++#define P2P_WFDS_MAX_SVC_NAME_LEN	32
++
++/* P2P IE Subelement IDs from WiFi P2P Technical Spec 1.00 */
++#define P2P_SEID_STATUS			0	/* Status */
++#define P2P_SEID_MINOR_RC		1	/* Minor Reason Code */
++#define P2P_SEID_P2P_INFO		2	/* P2P Capability (capabilities info) */
++#define P2P_SEID_DEV_ID			3	/* P2P Device ID */
++#define P2P_SEID_INTENT			4	/* Group Owner Intent */
++#define P2P_SEID_CFG_TIMEOUT		5	/* Configuration Timeout */
++#define P2P_SEID_CHANNEL		6	/* Listen channel */
++#define P2P_SEID_GRP_BSSID		7	/* P2P Group BSSID */
++#define P2P_SEID_XT_TIMING		8	/* Extended Listen Timing */
++#define P2P_SEID_INTINTADDR		9	/* Intended P2P Interface Address */
++#define P2P_SEID_P2P_MGBTY		10	/* P2P Manageability */
++#define P2P_SEID_CHAN_LIST		11	/* Channel List */
++#define P2P_SEID_ABSENCE		12	/* Notice of Absence */
++#define P2P_SEID_DEV_INFO		13	/* Device Info */
++#define P2P_SEID_GROUP_INFO		14	/* Group Info */
++#define P2P_SEID_GROUP_ID		15	/* Group ID */
++#define P2P_SEID_P2P_IF			16	/* P2P Interface */
++#define P2P_SEID_OP_CHANNEL		17	/* Operating Channel */
++#define P2P_SEID_INVITE_FLAGS		18	/* Invitation Flags */
++#define P2P_SEID_SERVICE_HASH		21	/* Service hash */
++#define P2P_SEID_SESSION		22	/* Session information */
++#define P2P_SEID_CONNECT_CAP		23	/* Connection capability */
++#define P2P_SEID_ADVERTISE_ID		24	/* Advertisement ID */
++#define P2P_SEID_ADVERTISE_SERVICE	25	/* Advertised service */
++#define P2P_SEID_SESSION_ID		26	/* Session ID */
++#define P2P_SEID_FEATURE_CAP		27	/* Feature capability */
++#define	P2P_SEID_PERSISTENT_GROUP	28	/* Persistent group */
++#define P2P_SEID_SESSION_INFO_RESP	29	/* Session Information Response */
++#define P2P_SEID_VNDR			221	/* Vendor-specific subelement */
++
++#define P2P_SE_VS_ID_SERVICES	0x1b
++
++
++/* WiFi P2P IE subelement: P2P Capability (capabilities info) */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_info_se_s {
++	uint8	eltId;		/* SE ID: P2P_SEID_P2P_INFO */
++	uint8	len[2];		/* SE length not including eltId, len fields */
++	uint8	dev;		/* Device Capability Bitmap */
++	uint8	group;		/* Group Capability Bitmap */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_info_se_s wifi_p2p_info_se_t;
++
++/* P2P Capability subelement's Device Capability Bitmap bit values */
++#define P2P_CAPSE_DEV_SERVICE_DIS	0x1 /* Service Discovery */
++#define P2P_CAPSE_DEV_CLIENT_DIS	0x2 /* Client Discoverability */
++#define P2P_CAPSE_DEV_CONCURRENT	0x4 /* Concurrent Operation */
++#define P2P_CAPSE_DEV_INFRA_MAN		0x8 /* P2P Infrastructure Managed */
++#define P2P_CAPSE_DEV_LIMIT			0x10 /* P2P Device Limit */
++#define P2P_CAPSE_INVITE_PROC		0x20 /* P2P Invitation Procedure */
++
++/* P2P Capability subelement's Group Capability Bitmap bit values */
++#define P2P_CAPSE_GRP_OWNER			0x1 /* P2P Group Owner */
++#define P2P_CAPSE_PERSIST_GRP		0x2 /* Persistent P2P Group */
++#define P2P_CAPSE_GRP_LIMIT			0x4 /* P2P Group Limit */
++#define P2P_CAPSE_GRP_INTRA_BSS		0x8 /* Intra-BSS Distribution */
++#define P2P_CAPSE_GRP_X_CONNECT		0x10 /* Cross Connection */
++#define P2P_CAPSE_GRP_PERSISTENT	0x20 /* Persistent Reconnect */
++#define P2P_CAPSE_GRP_FORMATION		0x40 /* Group Formation */
++
++
++/* WiFi P2P IE subelement: Group Owner Intent */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_intent_se_s {
++	uint8	eltId;		/* SE ID: P2P_SEID_INTENT */
++	uint8	len[2];		/* SE length not including eltId, len fields */
++	uint8	intent;		/* Intent Value 0...15 (0=legacy 15=master only) */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_intent_se_s wifi_p2p_intent_se_t;
++
++/* WiFi P2P IE subelement: Configuration Timeout */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_cfg_tmo_se_s {
++	uint8	eltId;		/* SE ID: P2P_SEID_CFG_TIMEOUT */
++	uint8	len[2];		/* SE length not including eltId, len fields */
++	uint8	go_tmo;		/* GO config timeout in units of 10 ms */
++	uint8	client_tmo;	/* Client config timeout in units of 10 ms */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_cfg_tmo_se_s wifi_p2p_cfg_tmo_se_t;
++
++/* WiFi P2P IE subelement: Listen Channel */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_listen_channel_se_s {
++	uint8	eltId;		/* SE ID: P2P_SEID_CHANNEL */
++	uint8	len[2];		/* SE length not including eltId, len fields */
++	uint8	country[3];	/* Country String */
++	uint8	op_class;	/* Operating Class */
++	uint8	channel;	/* Channel */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_listen_channel_se_s wifi_p2p_listen_channel_se_t;
++
++/* WiFi P2P IE subelement: P2P Group BSSID */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_grp_bssid_se_s {
++	uint8	eltId;		/* SE ID: P2P_SEID_GRP_BSSID */
++	uint8	len[2];		/* SE length not including eltId, len fields */
++	uint8	mac[6];		/* P2P group bssid */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_grp_bssid_se_s wifi_p2p_grp_bssid_se_t;
++
++/* WiFi P2P IE subelement: P2P Group ID */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_grp_id_se_s {
++	uint8	eltId;		/* SE ID: P2P_SEID_GROUP_ID */
++	uint8	len[2];		/* SE length not including eltId, len fields */
++	uint8	mac[6];		/* P2P device address */
++	uint8	ssid[1];	/* ssid. device id. variable length */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_grp_id_se_s wifi_p2p_grp_id_se_t;
++
++/* WiFi P2P IE subelement: P2P Interface */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_intf_se_s {
++	uint8	eltId;		/* SE ID: P2P_SEID_P2P_IF */
++	uint8	len[2];		/* SE length not including eltId, len fields */
++	uint8	mac[6];		/* P2P device address */
++	uint8	ifaddrs;	/* P2P Interface Address count */
++	uint8	ifaddr[1][6];	/* P2P Interface Address list */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_intf_se_s wifi_p2p_intf_se_t;
++
++/* WiFi P2P IE subelement: Status */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_status_se_s {
++	uint8	eltId;		/* SE ID: P2P_SEID_STATUS */
++	uint8	len[2];		/* SE length not including eltId, len fields */
++	uint8	status;		/* Status Code: P2P_STATSE_* */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_status_se_s wifi_p2p_status_se_t;
++
++/* Status subelement Status Code definitions */
++#define P2P_STATSE_SUCCESS			0
++				/* Success */
++#define P2P_STATSE_FAIL_INFO_CURR_UNAVAIL	1
++				/* Failed, information currently unavailable */
++#define P2P_STATSE_PASSED_UP			P2P_STATSE_FAIL_INFO_CURR_UNAVAIL
++				/* Old name for above in P2P spec 1.08 and older */
++#define P2P_STATSE_FAIL_INCOMPAT_PARAMS		2
++				/* Failed, incompatible parameters */
++#define P2P_STATSE_FAIL_LIMIT_REACHED		3
++				/* Failed, limit reached */
++#define P2P_STATSE_FAIL_INVALID_PARAMS		4
++				/* Failed, invalid parameters */
++#define P2P_STATSE_FAIL_UNABLE_TO_ACCOM		5
++				/* Failed, unable to accomodate request */
++#define P2P_STATSE_FAIL_PROTO_ERROR		6
++				/* Failed, previous protocol error or disruptive behaviour */
++#define P2P_STATSE_FAIL_NO_COMMON_CHAN		7
++				/* Failed, no common channels */
++#define P2P_STATSE_FAIL_UNKNOWN_GROUP		8
++				/* Failed, unknown P2P Group */
++#define P2P_STATSE_FAIL_INTENT			9
++				/* Failed, both peers indicated Intent 15 in GO Negotiation */
++#define P2P_STATSE_FAIL_INCOMPAT_PROVIS		10
++				/* Failed, incompatible provisioning method */
++#define P2P_STATSE_FAIL_USER_REJECT		11
++				/* Failed, rejected by user */
++#define P2P_STATSE_SUCCESS_USER_ACCEPT		12
++				/* Success, accepted by user */
++
++/* WiFi P2P IE attribute: Extended Listen Timing */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_ext_se_s {
++	uint8	eltId;		/* ID: P2P_SEID_EXT_TIMING */
++	uint8	len[2];		/* length not including eltId, len fields */
++	uint8	avail[2];	/* availibility period */
++	uint8	interval[2];	/* availibility interval */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_ext_se_s wifi_p2p_ext_se_t;
++
++#define P2P_EXT_MIN	10	/* minimum 10ms */
++
++/* WiFi P2P IE subelement: Intended P2P Interface Address */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_intintad_se_s {
++	uint8	eltId;		/* SE ID: P2P_SEID_INTINTADDR */
++	uint8	len[2];		/* SE length not including eltId, len fields */
++	uint8	mac[6];		/* intended P2P interface MAC address */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_intintad_se_s wifi_p2p_intintad_se_t;
++
++/* WiFi P2P IE subelement: Channel */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_channel_se_s {
++	uint8	eltId;		/* SE ID: P2P_SEID_STATUS */
++	uint8	len[2];		/* SE length not including eltId, len fields */
++	uint8	band;		/* Regulatory Class (band) */
++	uint8	channel;	/* Channel */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_channel_se_s wifi_p2p_channel_se_t;
++
++
++/* Channel Entry structure within the Channel List SE */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_chanlist_entry_s {
++	uint8	band;						/* Regulatory Class (band) */
++	uint8	num_channels;				/* # of channels in the channel list */
++	uint8	channels[WL_NUMCHANNELS];	/* Channel List */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_chanlist_entry_s wifi_p2p_chanlist_entry_t;
++#define WIFI_P2P_CHANLIST_SE_MAX_ENTRIES 2
++
++/* WiFi P2P IE subelement: Channel List */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_chanlist_se_s {
++	uint8	eltId;		/* SE ID: P2P_SEID_CHAN_LIST */
++	uint8	len[2];		/* SE length not including eltId, len fields */
++	uint8	country[3];	/* Country String */
++	uint8	num_entries;	/* # of channel entries */
++	wifi_p2p_chanlist_entry_t	entries[WIFI_P2P_CHANLIST_SE_MAX_ENTRIES];
++						/* Channel Entry List */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_chanlist_se_s wifi_p2p_chanlist_se_t;
++
++/* WiFi Primary Device Type structure */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_pri_devtype_s {
++	uint16	cat_id;		/* Category ID */
++	uint8	OUI[3];		/* WFA OUI: 0x0050F2 */
++	uint8	oui_type;	/* WPS_OUI_TYPE */
++	uint16	sub_cat_id;	/* Sub Category ID */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_pri_devtype_s wifi_p2p_pri_devtype_t;
++
++/* WiFi P2P Device Info Sub Element Primary Device Type Sub Category
++ * maximum values for each category
++ */
++#define P2P_DISE_SUBCATEGORY_MINVAL		1
++#define P2P_DISE_CATEGORY_COMPUTER		1
++#define P2P_DISE_SUBCATEGORY_COMPUTER_MAXVAL		8
++#define P2P_DISE_CATEGORY_INPUT_DEVICE		2
++#define P2P_DISE_SUBCATEGORY_INPUT_DEVICE_MAXVAL	9
++#define P2P_DISE_CATEGORY_PRINTER		3
++#define P2P_DISE_SUBCATEGORY_PRINTER_MAXVAL		5
++#define P2P_DISE_CATEGORY_CAMERA		4
++#define P2P_DISE_SUBCATEGORY_CAMERA_MAXVAL		4
++#define P2P_DISE_CATEGORY_STORAGE		5
++#define P2P_DISE_SUBCATEGORY_STORAGE_MAXVAL		1
++#define P2P_DISE_CATEGORY_NETWORK_INFRA		6
++#define P2P_DISE_SUBCATEGORY_NETWORK_INFRA_MAXVAL	4
++#define P2P_DISE_CATEGORY_DISPLAY		7
++#define P2P_DISE_SUBCATEGORY_DISPLAY_MAXVAL		4
++#define P2P_DISE_CATEGORY_MULTIMEDIA		8
++#define P2P_DISE_SUBCATEGORY_MULTIMEDIA_MAXVAL		6
++#define P2P_DISE_CATEGORY_GAMING		9
++#define P2P_DISE_SUBCATEGORY_GAMING_MAXVAL		5
++#define P2P_DISE_CATEGORY_TELEPHONE		10
++#define P2P_DISE_SUBCATEGORY_TELEPHONE_MAXVAL		5
++#define P2P_DISE_CATEGORY_AUDIO			11
++#define P2P_DISE_SUBCATEGORY_AUDIO_MAXVAL		6
++
++/* WiFi P2P IE's Device Info subelement */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_devinfo_se_s {
++	uint8	eltId;			/* SE ID: P2P_SEID_DEVINFO */
++	uint8	len[2];			/* SE length not including eltId, len fields */
++	uint8	mac[6];			/* P2P Device MAC address */
++	uint16	wps_cfg_meths;		/* Config Methods: reg_prototlv.h WPS_CONFMET_* */
++	uint8	pri_devtype[8];		/* Primary Device Type */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_devinfo_se_s wifi_p2p_devinfo_se_t;
++
++#define P2P_DEV_TYPE_LEN	8
++
++/* WiFi P2P IE's Group Info subelement Client Info Descriptor */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_cid_fixed_s {
++	uint8	len;
++	uint8	devaddr[ETHER_ADDR_LEN];	/* P2P Device Address */
++	uint8	ifaddr[ETHER_ADDR_LEN];		/* P2P Interface Address */
++	uint8	devcap;				/* Device Capability */
++	uint8	cfg_meths[2];			/* Config Methods: reg_prototlv.h WPS_CONFMET_* */
++	uint8	pridt[P2P_DEV_TYPE_LEN];	/* Primary Device Type */
++	uint8	secdts;				/* Number of Secondary Device Types */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_cid_fixed_s wifi_p2p_cid_fixed_t;
++
++/* WiFi P2P IE's Device ID subelement */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_devid_se_s {
++	uint8	eltId;
++	uint8	len[2];
++	struct ether_addr	addr;			/* P2P Device MAC address */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_devid_se_s wifi_p2p_devid_se_t;
++
++/* WiFi P2P IE subelement: P2P Manageability */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_mgbt_se_s {
++	uint8	eltId;		/* SE ID: P2P_SEID_P2P_MGBTY */
++	uint8	len[2];		/* SE length not including eltId, len fields */
++	uint8	mg_bitmap;	/* manageability bitmap */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_mgbt_se_s wifi_p2p_mgbt_se_t;
++/* mg_bitmap field bit values */
++#define P2P_MGBTSE_P2PDEVMGMT_FLAG   0x1 /* AP supports Managed P2P Device */
++
++/* WiFi P2P IE subelement: Group Info */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_grpinfo_se_s {
++	uint8	eltId;			/* SE ID: P2P_SEID_GROUP_INFO */
++	uint8	len[2];			/* SE length not including eltId, len fields */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_grpinfo_se_s wifi_p2p_grpinfo_se_t;
++
++/* WiFi IE subelement: Operating Channel */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_op_channel_se_s {
++	uint8	eltId;		/* SE ID: P2P_SEID_OP_CHANNEL */
++	uint8	len[2];		/* SE length not including eltId, len fields */
++	uint8	country[3];	/* Country String */
++	uint8	op_class;	/* Operating Class */
++	uint8	channel;	/* Channel */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_op_channel_se_s wifi_p2p_op_channel_se_t;
++
++/* WiFi IE subelement: INVITATION FLAGS */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_invite_flags_se_s {
++	uint8	eltId;		/* SE ID: P2P_SEID_INVITE_FLAGS */
++	uint8	len[2];		/* SE length not including eltId, len fields */
++	uint8	flags;		/* Flags */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_invite_flags_se_s wifi_p2p_invite_flags_se_t;
++
++/* WiFi P2P IE subelement: Service Hash */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_serv_hash_se_s {
++	uint8	eltId;			/* SE ID: P2P_SEID_SERVICE_HASH */
++	uint8	len[2];			/* SE length not including eltId, len fields
++					 * in multiple of 6 Bytes
++					*/
++	uint8	hash[1];		/* Variable length - SHA256 hash of
++					 * service names (can be more than one hashes)
++					*/
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_serv_hash_se_s wifi_p2p_serv_hash_se_t;
++
++/* WiFi P2P IE subelement: Service Instance Data */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_serv_inst_data_se_s {
++	uint8	eltId;			/* SE ID: P2P_SEID_SESSION */
++	uint8	len[2];			/* SE length not including eltId, len */
++	uint8	ssn_info[1];		/* Variable length - Session information as specified by
++					 * the service layer, type matches serv. name
++					*/
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_serv_inst_data_se_s wifi_p2p_serv_inst_data_se_t;
++
++
++/* WiFi P2P IE subelement: Connection capability */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_conn_cap_data_se_s {
++	uint8	eltId;			/* SE ID: P2P_SEID_CONNECT_CAP */
++	uint8	len[2];			/* SE length not including eltId, len */
++	uint8	conn_cap;		/* 1byte capability as specified by the
++					 * service layer, valid bitmask/values
++					*/
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_conn_cap_data_se_s wifi_p2p_conn_cap_data_se_t;
++
++
++/* WiFi P2P IE subelement: Advertisement ID */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_advt_id_se_s {
++	uint8	eltId;			/* SE ID: P2P_SEID_ADVERTISE_ID */
++	uint8	len[2];			/* SE length not including eltId, len fixed 4 Bytes */
++	uint8	advt_id[4];		/* 4byte Advertisement ID of the peer device sent in
++					 * PROV Disc in Network byte order
++					*/
++	uint8	advt_mac[6];			/* P2P device address of the service advertiser */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_advt_id_se_s wifi_p2p_advt_id_se_t;
++
++
++/* WiFi P2P IE subelement: Advertise Service Hash */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_adv_serv_info_s {
++	uint8	advt_id[4];		/* SE Advertise ID for the service */
++	uint16	nw_cfg_method;	/* SE Network Config method for the service */
++	uint8	serv_name_len;	/* SE length of the service name */
++	uint8	serv_name[1];	/* Variable length service name field */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_adv_serv_info_s wifi_p2p_adv_serv_info_t;
++
++
++/* WiFi P2P IE subelement: Advertise Service Hash */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_advt_serv_se_s {
++	uint8	eltId;			/* SE ID: P2P_SEID_ADVERTISE_SERVICE */
++	uint8	len[2];			/* SE length not including eltId, len fields mutiple len of
++					 * wifi_p2p_adv_serv_info_t entries
++					*/
++	wifi_p2p_adv_serv_info_t	p_advt_serv_info[1]; /* Variable length
++								of multiple instances
++								of the advertise service info
++								*/
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_advt_serv_se_s wifi_p2p_advt_serv_se_t;
++
++
++/* WiFi P2P IE subelement: Session ID */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_ssn_id_se_s {
++	uint8	eltId;			/* SE ID: P2P_SEID_SESSION_ID */
++	uint8	len[2];			/* SE length not including eltId, len fixed 4 Bytes */
++	uint8	ssn_id[4];		/* 4byte Session ID of the peer device sent in
++							 * PROV Disc in Network byte order
++							 */
++	uint8	ssn_mac[6];		/* P2P device address of the seeker - session mac */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_ssn_id_se_s wifi_p2p_ssn_id_se_t;
++
++
++#define P2P_ADVT_SERV_SE_FIXED_LEN	3	/* Includes only the element ID and len */
++#define P2P_ADVT_SERV_INFO_FIXED_LEN	7	/* Per ADV Service Instance advt_id +
++						 * nw_config_method + serv_name_len
++						 */
++
++/* WiFi P2P Action Frame */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_action_frame {
++	uint8	category;	/* P2P_AF_CATEGORY */
++	uint8	OUI[3];		/* OUI - P2P_OUI */
++	uint8	type;		/* OUI Type - P2P_VER */
++	uint8	subtype;	/* OUI Subtype - P2P_AF_* */
++	uint8	dialog_token;	/* nonzero, identifies req/resp tranaction */
++	uint8	elts[1];	/* Variable length information elements.  Max size =
++				 * ACTION_FRAME_SIZE - sizeof(this structure) - 1
++				 */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_action_frame wifi_p2p_action_frame_t;
++#define P2P_AF_CATEGORY		0x7f
++
++#define P2P_AF_FIXED_LEN	7
++
++/* WiFi P2P Action Frame OUI Subtypes */
++#define P2P_AF_NOTICE_OF_ABSENCE	0	/* Notice of Absence */
++#define P2P_AF_PRESENCE_REQ		1	/* P2P Presence Request */
++#define P2P_AF_PRESENCE_RSP		2	/* P2P Presence Response */
++#define P2P_AF_GO_DISC_REQ		3	/* GO Discoverability Request */
++
++
++/* WiFi P2P Public Action Frame */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_pub_act_frame {
++	uint8	category;	/* P2P_PUB_AF_CATEGORY */
++	uint8	action;		/* P2P_PUB_AF_ACTION */
++	uint8	oui[3];		/* P2P_OUI */
++	uint8	oui_type;	/* OUI type - P2P_VER */
++	uint8	subtype;	/* OUI subtype - P2P_TYPE_* */
++	uint8	dialog_token;	/* nonzero, identifies req/rsp transaction */
++	uint8	elts[1];	/* Variable length information elements.  Max size =
++				 * ACTION_FRAME_SIZE - sizeof(this structure) - 1
++				 */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_pub_act_frame wifi_p2p_pub_act_frame_t;
++#define P2P_PUB_AF_FIXED_LEN	8
++#define P2P_PUB_AF_CATEGORY	0x04
++#define P2P_PUB_AF_ACTION	0x09
++
++/* WiFi P2P Public Action Frame OUI Subtypes */
++#define P2P_PAF_GON_REQ		0	/* Group Owner Negotiation Req */
++#define P2P_PAF_GON_RSP		1	/* Group Owner Negotiation Rsp */
++#define P2P_PAF_GON_CONF	2	/* Group Owner Negotiation Confirm */
++#define P2P_PAF_INVITE_REQ	3	/* P2P Invitation Request */
++#define P2P_PAF_INVITE_RSP	4	/* P2P Invitation Response */
++#define P2P_PAF_DEVDIS_REQ	5	/* Device Discoverability Request */
++#define P2P_PAF_DEVDIS_RSP	6	/* Device Discoverability Response */
++#define P2P_PAF_PROVDIS_REQ	7	/* Provision Discovery Request */
++#define P2P_PAF_PROVDIS_RSP	8	/* Provision Discovery Response */
++#define P2P_PAF_SUBTYPE_INVALID	255	/* Invalid Subtype */
++
++/* TODO: Stop using these obsolete aliases for P2P_PAF_GON_* */
++#define P2P_TYPE_MNREQ		P2P_PAF_GON_REQ
++#define P2P_TYPE_MNRSP		P2P_PAF_GON_RSP
++#define P2P_TYPE_MNCONF		P2P_PAF_GON_CONF
++
++/* WiFi P2P IE subelement: Notice of Absence */
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_noa_desc {
++	uint8	cnt_type;	/* Count/Type */
++	uint32	duration;	/* Duration */
++	uint32	interval;	/* Interval */
++	uint32	start;		/* Start Time */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_noa_desc wifi_p2p_noa_desc_t;
++
++BWL_PRE_PACKED_STRUCT struct wifi_p2p_noa_se {
++	uint8	eltId;		/* Subelement ID */
++	uint8	len[2];		/* Length */
++	uint8	index;		/* Index */
++	uint8	ops_ctw_parms;	/* CTWindow and OppPS Parameters */
++	wifi_p2p_noa_desc_t	desc[1];	/* Notice of Absence Descriptor(s) */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2p_noa_se wifi_p2p_noa_se_t;
++
++#define P2P_NOA_SE_FIXED_LEN	5
++
++#define P2P_NOA_SE_MAX_DESC	2	/* max NoA descriptors in presence request */
++
++/* cnt_type field values */
++#define P2P_NOA_DESC_CNT_RESERVED	0	/* reserved and should not be used */
++#define P2P_NOA_DESC_CNT_REPEAT		255	/* continuous schedule */
++#define P2P_NOA_DESC_TYPE_PREFERRED	1	/* preferred values */
++#define P2P_NOA_DESC_TYPE_ACCEPTABLE	2	/* acceptable limits */
++
++/* ctw_ops_parms field values */
++#define P2P_NOA_CTW_MASK	0x7f
++#define P2P_NOA_OPS_MASK	0x80
++#define P2P_NOA_OPS_SHIFT	7
++
++#define P2P_CTW_MIN	10	/* minimum 10TU */
++
++/*
++ * P2P Service Discovery related
++ */
++#define	P2PSD_ACTION_CATEGORY		0x04
++				/* Public action frame */
++#define	P2PSD_ACTION_ID_GAS_IREQ	0x0a
++				/* Action value for GAS Initial Request AF */
++#define	P2PSD_ACTION_ID_GAS_IRESP	0x0b
++				/* Action value for GAS Initial Response AF */
++#define	P2PSD_ACTION_ID_GAS_CREQ	0x0c
++				/* Action value for GAS Comeback Request AF */
++#define	P2PSD_ACTION_ID_GAS_CRESP	0x0d
++				/* Action value for GAS Comeback Response AF */
++#define P2PSD_AD_EID				0x6c
++				/* Advertisement Protocol IE ID */
++#define P2PSD_ADP_TUPLE_QLMT_PAMEBI	0x00
++				/* Query Response Length Limit 7 bits plus PAME-BI 1 bit */
++#define P2PSD_ADP_PROTO_ID			0x00
++				/* Advertisement Protocol ID. Always 0 for P2P SD */
++#define P2PSD_GAS_OUI				P2P_OUI
++				/* WFA OUI */
++#define P2PSD_GAS_OUI_SUBTYPE		P2P_VER
++				/* OUI Subtype for GAS IE */
++#define P2PSD_GAS_NQP_INFOID		0xDDDD
++				/* NQP Query Info ID: 56797 */
++#define P2PSD_GAS_COMEBACKDEALY		0x00
++				/* Not used in the Native GAS protocol */
++
++/* Service Protocol Type */
++typedef enum p2psd_svc_protype {
++	SVC_RPOTYPE_ALL = 0,
++	SVC_RPOTYPE_BONJOUR = 1,
++	SVC_RPOTYPE_UPNP = 2,
++	SVC_RPOTYPE_WSD = 3,
++	SVC_RPOTYPE_WFDS = 11,
++	SVC_RPOTYPE_VENDOR = 255
++} p2psd_svc_protype_t;
++
++/* Service Discovery response status code */
++typedef enum {
++	P2PSD_RESP_STATUS_SUCCESS = 0,
++	P2PSD_RESP_STATUS_PROTYPE_NA = 1,
++	P2PSD_RESP_STATUS_DATA_NA = 2,
++	P2PSD_RESP_STATUS_BAD_REQUEST = 3
++} p2psd_resp_status_t;
++
++/* Advertisement Protocol IE tuple field */
++BWL_PRE_PACKED_STRUCT struct wifi_p2psd_adp_tpl {
++	uint8	llm_pamebi;	/* Query Response Length Limit bit 0-6, set to 0 plus
++				* Pre-Associated Message Exchange BSSID Independent bit 7, set to 0
++				*/
++	uint8	adp_id;		/* Advertisement Protocol ID: 0 for NQP Native Query Protocol */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2psd_adp_tpl wifi_p2psd_adp_tpl_t;
++
++/* Advertisement Protocol IE */
++BWL_PRE_PACKED_STRUCT struct wifi_p2psd_adp_ie {
++	uint8	id;		/* IE ID: 0x6c - 108 */
++	uint8	len;	/* IE length */
++	wifi_p2psd_adp_tpl_t adp_tpl;  /* Advertisement Protocol Tuple field. Only one
++				* tuple is defined for P2P Service Discovery
++				*/
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2psd_adp_ie wifi_p2psd_adp_ie_t;
++
++/* NQP Vendor-specific Content */
++BWL_PRE_PACKED_STRUCT struct wifi_p2psd_nqp_query_vsc {
++	uint8	oui_subtype;	/* OUI Subtype: 0x09 */
++	uint16	svc_updi;		/* Service Update Indicator */
++	uint8	svc_tlvs[1];	/* wifi_p2psd_qreq_tlv_t type for service request,
++				* wifi_p2psd_qresp_tlv_t type for service response
++				*/
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2psd_nqp_query_vsc wifi_p2psd_nqp_query_vsc_t;
++
++/* Service Request TLV */
++BWL_PRE_PACKED_STRUCT struct wifi_p2psd_qreq_tlv {
++	uint16	len;			/* Length: 5 plus size of Query Data */
++	uint8	svc_prot;		/* Service Protocol Type */
++	uint8	svc_tscid;		/* Service Transaction ID */
++	uint8	query_data[1];	/* Query Data, passed in from above Layer 2 */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2psd_qreq_tlv wifi_p2psd_qreq_tlv_t;
++
++/* Query Request Frame, defined in generic format, instead of NQP specific */
++BWL_PRE_PACKED_STRUCT struct wifi_p2psd_qreq_frame {
++	uint16	info_id;	/* Info ID: 0xDDDD */
++	uint16	len;		/* Length of service request TLV, 5 plus the size of request data */
++	uint8	oui[3];		/* WFA OUI: 0x0050F2 */
++	uint8	qreq_vsc[1]; /* Vendor-specific Content: wifi_p2psd_nqp_query_vsc_t type for NQP */
++
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2psd_qreq_frame wifi_p2psd_qreq_frame_t;
++
++/* GAS Initial Request AF body, "elts" in wifi_p2p_pub_act_frame */
++BWL_PRE_PACKED_STRUCT struct wifi_p2psd_gas_ireq_frame {
++	wifi_p2psd_adp_ie_t		adp_ie;		/* Advertisement Protocol IE */
++	uint16					qreq_len;	/* Query Request Length */
++	uint8	qreq_frm[1];	/* Query Request Frame wifi_p2psd_qreq_frame_t */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2psd_gas_ireq_frame wifi_p2psd_gas_ireq_frame_t;
++
++/* Service Response TLV */
++BWL_PRE_PACKED_STRUCT struct wifi_p2psd_qresp_tlv {
++	uint16	len;				/* Length: 5 plus size of Query Data */
++	uint8	svc_prot;			/* Service Protocol Type */
++	uint8	svc_tscid;			/* Service Transaction ID */
++	uint8	status;				/* Value defined in Table 57 of P2P spec. */
++	uint8	query_data[1];		/* Response Data, passed in from above Layer 2 */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2psd_qresp_tlv wifi_p2psd_qresp_tlv_t;
++
++/* Query Response Frame, defined in generic format, instead of NQP specific */
++BWL_PRE_PACKED_STRUCT struct wifi_p2psd_qresp_frame {
++	uint16	info_id;	/* Info ID: 0xDDDD */
++	uint16	len;		/* Lenth of service response TLV, 6 plus the size of resp data */
++	uint8	oui[3];		/* WFA OUI: 0x0050F2 */
++	uint8	qresp_vsc[1]; /* Vendor-specific Content: wifi_p2psd_qresp_tlv_t type for NQP */
++
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2psd_qresp_frame wifi_p2psd_qresp_frame_t;
++
++/* GAS Initial Response AF body, "elts" in wifi_p2p_pub_act_frame */
++BWL_PRE_PACKED_STRUCT struct wifi_p2psd_gas_iresp_frame {
++	uint16	status;			/* Value defined in Table 7-23 of IEEE P802.11u */
++	uint16	cb_delay;		/* GAS Comeback Delay */
++	wifi_p2psd_adp_ie_t	adp_ie;		/* Advertisement Protocol IE */
++	uint16		qresp_len;	/* Query Response Length */
++	uint8	qresp_frm[1];	/* Query Response Frame wifi_p2psd_qresp_frame_t */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2psd_gas_iresp_frame wifi_p2psd_gas_iresp_frame_t;
++
++/* GAS Comeback Response AF body, "elts" in wifi_p2p_pub_act_frame */
++BWL_PRE_PACKED_STRUCT struct wifi_p2psd_gas_cresp_frame {
++	uint16	status;			/* Value defined in Table 7-23 of IEEE P802.11u */
++	uint8	fragment_id;	/* Fragmentation ID */
++	uint16	cb_delay;		/* GAS Comeback Delay */
++	wifi_p2psd_adp_ie_t	adp_ie;		/* Advertisement Protocol IE */
++	uint16	qresp_len;		/* Query Response Length */
++	uint8	qresp_frm[1];	/* Query Response Frame wifi_p2psd_qresp_frame_t */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2psd_gas_cresp_frame wifi_p2psd_gas_cresp_frame_t;
++
++/* Wi-Fi GAS Public Action Frame */
++BWL_PRE_PACKED_STRUCT struct wifi_p2psd_gas_pub_act_frame {
++	uint8	category;		/* 0x04 Public Action Frame */
++	uint8	action;			/* 0x6c Advertisement Protocol */
++	uint8	dialog_token;	/* nonzero, identifies req/rsp transaction */
++	uint8	query_data[1];	/* Query Data. wifi_p2psd_gas_ireq_frame_t
++					 * or wifi_p2psd_gas_iresp_frame_t format
++					 */
++} BWL_POST_PACKED_STRUCT;
++typedef struct wifi_p2psd_gas_pub_act_frame wifi_p2psd_gas_pub_act_frame_t;
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++#endif /* _P2P_H_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/packed_section_end.h b/module_drivers/drivers/net/wireless/bcmdhd/include/packed_section_end.h
+new file mode 100644
+index 000000000..4827c709a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/packed_section_end.h
+@@ -0,0 +1,63 @@
++/*
++ * Declare directives for structure packing. No padding will be provided
++ * between the members of packed structures, and therefore, there is no
++ * guarantee that structure members will be aligned.
++ *
++ * Declaring packed structures is compiler specific. In order to handle all
++ * cases, packed structures should be delared as:
++ *
++ * #include <packed_section_start.h>
++ *
++ * typedef BWL_PRE_PACKED_STRUCT struct foobar_t {
++ *    some_struct_members;
++ * } BWL_POST_PACKED_STRUCT foobar_t;
++ *
++ * #include <packed_section_end.h>
++ *
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: packed_section_end.h 514727 2014-11-12 03:02:48Z $
++ */
++
++
++/* Error check - BWL_PACKED_SECTION is defined in packed_section_start.h
++ * and undefined in packed_section_end.h. If it is NOT defined at this
++ * point, then there is a missing include of packed_section_start.h.
++ */
++#ifdef BWL_PACKED_SECTION
++	#undef BWL_PACKED_SECTION
++#else
++	#error "BWL_PACKED_SECTION is NOT defined!"
++#endif
++
++
++
++
++/* Compiler-specific directives for structure packing are declared in
++ * packed_section_start.h. This marks the end of the structure packing section,
++ * so, undef them here.
++ */
++#undef	BWL_PRE_PACKED_STRUCT
++#undef	BWL_POST_PACKED_STRUCT
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/packed_section_start.h b/module_drivers/drivers/net/wireless/bcmdhd/include/packed_section_start.h
+new file mode 100644
+index 000000000..9beb45d5e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/packed_section_start.h
+@@ -0,0 +1,67 @@
++/*
++ * Declare directives for structure packing. No padding will be provided
++ * between the members of packed structures, and therefore, there is no
++ * guarantee that structure members will be aligned.
++ *
++ * Declaring packed structures is compiler specific. In order to handle all
++ * cases, packed structures should be delared as:
++ *
++ * #include <packed_section_start.h>
++ *
++ * typedef BWL_PRE_PACKED_STRUCT struct foobar_t {
++ *    some_struct_members;
++ * } BWL_POST_PACKED_STRUCT foobar_t;
++ *
++ * #include <packed_section_end.h>
++ *
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: packed_section_start.h 514727 2014-11-12 03:02:48Z $
++ */
++
++
++/* Error check - BWL_PACKED_SECTION is defined in packed_section_start.h
++ * and undefined in packed_section_end.h. If it is already defined at this
++ * point, then there is a missing include of packed_section_end.h.
++ */
++#ifdef BWL_PACKED_SECTION
++	#error "BWL_PACKED_SECTION is already defined!"
++#else
++	#define BWL_PACKED_SECTION
++#endif
++
++
++
++
++/* Declare compiler-specific directives for structure packing. */
++#if defined(__GNUC__) || defined(__lint)
++	#define	BWL_PRE_PACKED_STRUCT
++	#define	BWL_POST_PACKED_STRUCT	__attribute__ ((packed))
++#elif defined(__CC_ARM)
++	#define	BWL_PRE_PACKED_STRUCT	__packed
++	#define	BWL_POST_PACKED_STRUCT
++#else
++	#error "Unknown compiler!"
++#endif
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/pcicfg.h b/module_drivers/drivers/net/wireless/bcmdhd/include/pcicfg.h
+new file mode 100644
+index 000000000..98f22c3df
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/pcicfg.h
+@@ -0,0 +1,330 @@
++/*
++ * pcicfg.h: PCI configuration constants and structures.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: pcicfg.h 621340 2016-02-25 12:26:40Z $
++ */
++
++#ifndef	_h_pcicfg_
++#define	_h_pcicfg_
++
++
++/* pci config status reg has a bit to indicate that capability ptr is present */
++
++#define PCI_CAPPTR_PRESENT	0x0010
++
++/* A structure for the config registers is nice, but in most
++ * systems the config space is not memory mapped, so we need
++ * field offsetts. :-(
++ */
++#define	PCI_CFG_VID		0
++#define	PCI_CFG_DID		2
++#define	PCI_CFG_CMD		4
++#define	PCI_CFG_STAT		6
++#define	PCI_CFG_REV		8
++#define	PCI_CFG_PROGIF		9
++#define	PCI_CFG_SUBCL		0xa
++#define	PCI_CFG_BASECL		0xb
++#define	PCI_CFG_CLSZ		0xc
++#define	PCI_CFG_LATTIM		0xd
++#define	PCI_CFG_HDR		0xe
++#define	PCI_CFG_BIST		0xf
++#define	PCI_CFG_BAR0		0x10
++/*
++* TODO: PCI_CFG_BAR1 is wrongly defined to be 0x14 whereas it should be
++* 0x18 as per the PCIe full dongle spec. Need to modify the values below
++* correctly at a later point of time
++*/
++#ifdef DHD_EFI
++#define	PCI_CFG_BAR1		0x18
++#else
++#define	PCI_CFG_BAR1		0x14
++#endif /* DHD_EFI */
++#define	PCI_CFG_BAR2		0x18
++#define	PCI_CFG_BAR3		0x1c
++#define	PCI_CFG_BAR4		0x20
++#define	PCI_CFG_BAR5		0x24
++#define	PCI_CFG_CIS		0x28
++#define	PCI_CFG_SVID		0x2c
++#define	PCI_CFG_SSID		0x2e
++#define	PCI_CFG_ROMBAR		0x30
++#define PCI_CFG_CAPPTR		0x34
++#define	PCI_CFG_INT		0x3c
++#define	PCI_CFG_PIN		0x3d
++#define	PCI_CFG_MINGNT		0x3e
++#define	PCI_CFG_MAXLAT		0x3f
++#define	PCI_CFG_DEVCTRL		0xd8
++#define PCI_CFG_TLCNTRL_5	0x814
++
++
++/* PCI CAPABILITY DEFINES */
++#define PCI_CAP_POWERMGMTCAP_ID		0x01
++#define PCI_CAP_MSICAP_ID		0x05
++#define PCI_CAP_VENDSPEC_ID		0x09
++#define PCI_CAP_PCIECAP_ID		0x10
++
++/* Data structure to define the Message Signalled Interrupt facility
++ * Valid for PCI and PCIE configurations
++ */
++typedef struct _pciconfig_cap_msi {
++	uint8	capID;
++	uint8	nextptr;
++	uint16	msgctrl;
++	uint32	msgaddr;
++} pciconfig_cap_msi;
++#define MSI_ENABLE	0x1		/* bit 0 of msgctrl */
++
++/* Data structure to define the Power managment facility
++ * Valid for PCI and PCIE configurations
++ */
++typedef struct _pciconfig_cap_pwrmgmt {
++	uint8	capID;
++	uint8	nextptr;
++	uint16	pme_cap;
++	uint16	pme_sts_ctrl;
++	uint8	pme_bridge_ext;
++	uint8	data;
++} pciconfig_cap_pwrmgmt;
++
++#define PME_CAP_PM_STATES (0x1f << 27)	/* Bits 31:27 states that can generate PME */
++#define PME_CSR_OFFSET	    0x4		/* 4-bytes offset */
++#define PME_CSR_PME_EN	  (1 << 8)	/* Bit 8 Enable generating of PME */
++#define PME_CSR_PME_STAT  (1 << 15)	/* Bit 15 PME got asserted */
++
++/* Data structure to define the PCIE capability */
++typedef struct _pciconfig_cap_pcie {
++	uint8	capID;
++	uint8	nextptr;
++	uint16	pcie_cap;
++	uint32	dev_cap;
++	uint16	dev_ctrl;
++	uint16	dev_status;
++	uint32	link_cap;
++	uint16	link_ctrl;
++	uint16	link_status;
++	uint32	slot_cap;
++	uint16	slot_ctrl;
++	uint16	slot_status;
++	uint16	root_ctrl;
++	uint16	root_cap;
++	uint32	root_status;
++} pciconfig_cap_pcie;
++
++/* PCIE Enhanced CAPABILITY DEFINES */
++#define PCIE_EXTCFG_OFFSET	0x100
++#define PCIE_ADVERRREP_CAPID	0x0001
++#define PCIE_VC_CAPID		0x0002
++#define PCIE_DEVSNUM_CAPID	0x0003
++#define PCIE_PWRBUDGET_CAPID	0x0004
++
++/* PCIE Extended configuration */
++#define PCIE_ADV_CORR_ERR_MASK	0x114
++#define CORR_ERR_RE	(1 << 0) /* Receiver  */
++#define CORR_ERR_BT 	(1 << 6) /* Bad TLP  */
++#define CORR_ERR_BD	(1 << 7) /* Bad DLLP */
++#define CORR_ERR_RR	(1 << 8) /* REPLAY_NUM rollover */
++#define CORR_ERR_RT	(1 << 12) /* Reply timer timeout */
++#define ALL_CORR_ERRORS (CORR_ERR_RE | CORR_ERR_BT | CORR_ERR_BD | \
++			 CORR_ERR_RR | CORR_ERR_RT)
++
++/* PCIE Root Control Register bits (Host mode only) */
++#define	PCIE_RC_CORR_SERR_EN		0x0001
++#define	PCIE_RC_NONFATAL_SERR_EN	0x0002
++#define	PCIE_RC_FATAL_SERR_EN		0x0004
++#define	PCIE_RC_PME_INT_EN		0x0008
++#define	PCIE_RC_CRS_EN			0x0010
++
++/* PCIE Root Capability Register bits (Host mode only) */
++#define	PCIE_RC_CRS_VISIBILITY		0x0001
++
++/* Header to define the PCIE specific capabilities in the extended config space */
++typedef struct _pcie_enhanced_caphdr {
++	uint16	capID;
++	uint16	cap_ver : 4;
++	uint16	next_ptr : 12;
++} pcie_enhanced_caphdr;
++
++
++#define	PCI_BAR0_WIN		0x80	/* backplane addres space accessed by BAR0 */
++#define	PCI_BAR1_WIN		0x84	/* backplane addres space accessed by BAR1 */
++#define	PCI_SPROM_CONTROL	0x88	/* sprom property control */
++#define	PCI_BAR1_CONTROL	0x8c	/* BAR1 region burst control */
++#define	PCI_INT_STATUS		0x90	/* PCI and other cores interrupts */
++#define	PCI_INT_MASK		0x94	/* mask of PCI and other cores interrupts */
++#define PCI_TO_SB_MB		0x98	/* signal backplane interrupts */
++#define PCI_BACKPLANE_ADDR	0xa0	/* address an arbitrary location on the system backplane */
++#define PCI_BACKPLANE_DATA	0xa4	/* data at the location specified by above address */
++#define	PCI_CLK_CTL_ST		0xa8	/* pci config space clock control/status (>=rev14) */
++#define	PCI_BAR0_WIN2		0xac	/* backplane addres space accessed by second 4KB of BAR0 */
++#define	PCI_GPIO_IN		0xb0	/* pci config space gpio input (>=rev3) */
++#define	PCI_GPIO_OUT		0xb4	/* pci config space gpio output (>=rev3) */
++#define PCIE_CFG_DEVICE_CONTROL 0xb4    /* 0xb4 is used as device control in PCIE devices */
++#define PCIE_DC_AER_CORR_EN		(1u << 0u)
++#define PCIE_DC_AER_NON_FATAL_EN	(1u << 1u)
++#define PCIE_DC_AER_FATAL_EN		(1u << 2u)
++#define PCIE_DC_AER_UNSUP_EN		(1u << 3u)
++
++#define PCI_BAR0_WIN2_OFFSET		0x1000u
++#define PCIE2_BAR0_CORE2_WIN2_OFFSET	0x5000u
++
++#define	PCI_GPIO_OUTEN		0xb8	/* pci config space gpio output enable (>=rev3) */
++#define	PCI_L1SS_CTRL2		0x24c	/* The L1 PM Substates Control register */
++
++/* Private Registers */
++#define	PCI_STAT_CTRL		0xa80
++#define	PCI_L0_EVENTCNT		0xa84
++#define	PCI_L0_STATETMR		0xa88
++#define	PCI_L1_EVENTCNT		0xa8c
++#define	PCI_L1_STATETMR		0xa90
++#define	PCI_L1_1_EVENTCNT	0xa94
++#define	PCI_L1_1_STATETMR	0xa98
++#define	PCI_L1_2_EVENTCNT	0xa9c
++#define	PCI_L1_2_STATETMR	0xaa0
++#define	PCI_L2_EVENTCNT		0xaa4
++#define	PCI_L2_STATETMR		0xaa8
++
++#define	PCI_LINK_STATUS		0x4dc
++#define	PCI_LINK_SPEED_MASK	(15u << 0u)
++#define	PCI_LINK_SPEED_SHIFT	(0)
++#define PCIE_LNK_SPEED_GEN1		0x1
++#define PCIE_LNK_SPEED_GEN2		0x2
++#define PCIE_LNK_SPEED_GEN3		0x3
++
++#define	PCI_PL_SPARE	0x1808	/* Config to Increase external clkreq deasserted minimum time */
++#define	PCI_CONFIG_EXT_CLK_MIN_TIME_MASK	(1u << 31u)
++#define	PCI_CONFIG_EXT_CLK_MIN_TIME_SHIFT	(31)
++
++#define	PCI_PMCR_REFUP		0x1814	/* Trefup time */
++#define	PCI_PMCR_REFUP_EXT	0x1818	/* Trefup extend Max */
++#define PCI_TPOWER_SCALE_MASK 0x3
++#define PCI_TPOWER_SCALE_SHIFT 3 /* 0:1 is scale and 2 is rsvd */
++
++
++#define	PCI_BAR0_SHADOW_OFFSET	(2 * 1024)	/* bar0 + 2K accesses sprom shadow (in pci core) */
++#define	PCI_BAR0_SPROM_OFFSET	(4 * 1024)	/* bar0 + 4K accesses external sprom */
++#define	PCI_BAR0_PCIREGS_OFFSET	(6 * 1024)	/* bar0 + 6K accesses pci core registers */
++#define	PCI_BAR0_PCISBR_OFFSET	(4 * 1024)	/* pci core SB registers are at the end of the
++						 * 8KB window, so their address is the "regular"
++						 * address plus 4K
++						 */
++/*
++ * PCIE GEN2 changed some of the above locations for
++ * Bar0WrapperBase, SecondaryBAR0Window and SecondaryBAR0WrapperBase
++ * BAR0 maps 32K of register space
++*/
++#define PCIE2_BAR0_WIN2		0x70 /* backplane addres space accessed by second 4KB of BAR0 */
++#define PCIE2_BAR0_CORE2_WIN	0x74 /* backplane addres space accessed by second 4KB of BAR0 */
++#define PCIE2_BAR0_CORE2_WIN2	0x78 /* backplane addres space accessed by second 4KB of BAR0 */
++
++#define PCI_BAR0_WIN2_OFFSET		0x1000u
++#define PCI_CORE_ENUM_OFFSET		0x2000u
++#define PCI_CC_CORE_ENUM_OFFSET		0x3000u
++#define PCI_SEC_BAR0_WIN_OFFSET		0x4000u
++#define PCI_SEC_BAR0_WRAP_OFFSET	0x5000u
++#define PCI_CORE_ENUM2_OFFSET		0x6000u
++#define PCI_CC_CORE_ENUM2_OFFSET	0x7000u
++#define PCI_LAST_OFFSET			0x8000u
++
++#define PCI_BAR0_WINSZ		(16 * 1024)	/* bar0 window size Match with corerev 13 */
++/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
++#define	PCI_16KB0_PCIREGS_OFFSET (8 * 1024)	/* bar0 + 8K accesses pci/pcie core registers */
++#define	PCI_16KB0_CCREGS_OFFSET	(12 * 1024)	/* bar0 + 12K accesses chipc core registers */
++#define PCI_16KBB0_WINSZ	(16 * 1024)	/* bar0 window size */
++#define PCI_SECOND_BAR0_OFFSET	(16 * 1024)	/* secondary  bar 0 window */
++
++/* On AI chips we have a second window to map DMP regs are mapped: */
++#define	PCI_16KB0_WIN2_OFFSET	(4 * 1024)	/* bar0 + 4K is "Window 2" */
++
++/* PCI_INT_STATUS */
++#define	PCI_SBIM_STATUS_SERR	0x4	/* backplane SBErr interrupt status */
++
++/* PCI_INT_MASK */
++#define	PCI_SBIM_SHIFT		8	/* backplane core interrupt mask bits offset */
++#define	PCI_SBIM_MASK		0xff00	/* backplane core interrupt mask */
++#define	PCI_SBIM_MASK_SERR	0x4	/* backplane SBErr interrupt mask */
++#define	PCI_CTO_INT_SHIFT	16	/* backplane SBErr interrupt mask */
++#define	PCI_CTO_INT_MASK	(1 << PCI_CTO_INT_SHIFT)	/* backplane SBErr interrupt mask */
++
++/* PCI_SPROM_CONTROL */
++#define SPROM_SZ_MSK		0x02	/* SPROM Size Mask */
++#define SPROM_LOCKED		0x08	/* SPROM Locked */
++#define	SPROM_BLANK		0x04	/* indicating a blank SPROM */
++#define SPROM_WRITEEN		0x10	/* SPROM write enable */
++#define SPROM_BOOTROM_WE	0x20	/* external bootrom write enable */
++#define SPROM_BACKPLANE_EN	0x40	/* Enable indirect backplane access */
++#define SPROM_OTPIN_USE		0x80	/* device OTP In use */
++#define SPROM_CFG_TO_SB_RST	0x400	/* backplane reset */
++
++/* Bits in PCI command and status regs */
++#define PCI_CMD_IO		0x00000001	/* I/O enable */
++#define PCI_CMD_MEMORY		0x00000002	/* Memory enable */
++#define PCI_CMD_MASTER		0x00000004	/* Master enable */
++#define PCI_CMD_SPECIAL		0x00000008	/* Special cycles enable */
++#define PCI_CMD_INVALIDATE	0x00000010	/* Invalidate? */
++#define PCI_CMD_VGA_PAL		0x00000040	/* VGA Palate */
++#define PCI_STAT_TA		0x08000000	/* target abort status */
++
++/* Header types */
++#define	PCI_HEADER_MULTI	0x80
++#define	PCI_HEADER_MASK		0x7f
++typedef enum {
++	PCI_HEADER_NORMAL,
++	PCI_HEADER_BRIDGE,
++	PCI_HEADER_CARDBUS
++} pci_header_types;
++
++#define PCI_CONFIG_SPACE_SIZE	256
++
++#define DWORD_ALIGN(x)  (x & ~(0x03))
++#define BYTE_POS(x) (x & 0x3)
++#define WORD_POS(x) (x & 0x1)
++
++#define BYTE_SHIFT(x)  (8 * BYTE_POS(x))
++#define WORD_SHIFT(x)  (16 * WORD_POS(x))
++
++#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
++#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
++
++#define read_pci_cfg_byte(a) \
++	(BYTE_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xff)
++
++#define read_pci_cfg_word(a) \
++	(WORD_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xffff)
++
++#define write_pci_cfg_byte(a, val) do { \
++	uint32 tmpval; \
++	tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFF << BYTE_POS(a)) | \
++	        val << BYTE_POS(a); \
++	OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \
++	} while (0)
++
++#define write_pci_cfg_word(a, val) do { \
++	uint32 tmpval; \
++	tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFFFF << WORD_POS(a)) | \
++	        val << WORD_POS(a); \
++	OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \
++	} while (0)
++
++#endif	/* _h_pcicfg_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/pcie_core.h b/module_drivers/drivers/net/wireless/bcmdhd/include/pcie_core.h
+new file mode 100644
+index 000000000..463561d08
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/pcie_core.h
+@@ -0,0 +1,959 @@
++/*
++ * BCM43XX PCIE core hardware definitions.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: pcie_core.h 673814 2016-12-05 06:10:24Z $
++ */
++#ifndef	_PCIE_CORE_H
++#define	_PCIE_CORE_H
++
++#include <sbhnddma.h>
++#include <siutils.h>
++
++/* cpp contortions to concatenate w/arg prescan */
++#ifndef PAD
++#define	_PADLINE(line)	pad ## line
++#define	_XSTR(line)	_PADLINE(line)
++#define	PAD		_XSTR(__LINE__)
++#endif
++
++/* PCIE Enumeration space offsets */
++#define  PCIE_CORE_CONFIG_OFFSET	0x0
++#define  PCIE_FUNC0_CONFIG_OFFSET	0x400
++#define  PCIE_FUNC1_CONFIG_OFFSET	0x500
++#define  PCIE_FUNC2_CONFIG_OFFSET	0x600
++#define  PCIE_FUNC3_CONFIG_OFFSET	0x700
++#define  PCIE_SPROM_SHADOW_OFFSET	0x800
++#define  PCIE_SBCONFIG_OFFSET		0xE00
++
++
++#define PCIEDEV_MAX_DMAS			4
++
++/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
++#define PCIE_DEV_BAR0_SIZE		0x4000
++#define PCIE_BAR0_WINMAPCORE_OFFSET	0x0
++#define PCIE_BAR0_EXTSPROM_OFFSET	0x1000
++#define PCIE_BAR0_PCIECORE_OFFSET	0x2000
++#define PCIE_BAR0_CCCOREREG_OFFSET	0x3000
++
++/* different register spaces to access thr'u pcie indirect access */
++#define PCIE_CONFIGREGS		1		/* Access to config space */
++#define PCIE_PCIEREGS		2		/* Access to pcie registers */
++
++#define PCIEDEV_HOSTADDR_MAP_BASE     0x8000000
++#define PCIEDEV_HOSTADDR_MAP_WIN_MASK 0xFC000000
++
++/* dma regs to control the flow between host2dev and dev2host  */
++typedef volatile struct pcie_devdmaregs {
++	dma64regs_t	tx;
++	uint32		PAD[2];
++	dma64regs_t	rx;
++	uint32		PAD[2];
++} pcie_devdmaregs_t;
++
++#define PCIE_DB_HOST2DEV_0		0x1
++#define PCIE_DB_HOST2DEV_1		0x2
++#define PCIE_DB_DEV2HOST_0		0x3
++#define PCIE_DB_DEV2HOST_1		0x4
++
++/* door bell register sets */
++typedef struct pcie_doorbell {
++	uint32		host2dev_0;
++	uint32		host2dev_1;
++	uint32		dev2host_0;
++	uint32		dev2host_1;
++} pcie_doorbell_t;
++
++/* Flow Ring Manager */
++#define IFRM_FR_IDX_MAX	256
++#define IFRM_FR_GID_MAX 4
++#define IFRM_FR_DEV_MAX 8
++#define IFRM_FR_TID_MAX 8
++#define IFRM_FR_DEV_VALID 2
++
++#define IFRM_VEC_REG_BITS	32
++
++#define IFRM_FR_PER_VECREG			4
++#define IFRM_FR_PER_VECREG_SHIFT	2
++#define IFRM_FR_PER_VECREG_MASK		((0x1 << IFRM_FR_PER_VECREG_SHIFT) - 1)
++
++#define IFRM_VEC_BITS_PER_FR	(IFRM_VEC_REG_BITS/IFRM_FR_PER_VECREG)
++
++/* IFRM_DEV_0 : d11AC, IFRM_DEV_1 : d11AD */
++#define IFRM_DEV_0	0
++#define IFRM_DEV_1	1
++
++#define IFRM_FR_GID_0 0
++#define IFRM_FR_GID_1 1
++#define IFRM_FR_GID_2 2
++#define IFRM_FR_GID_3 3
++
++#define IFRM_TIDMASK 0xffffffff
++
++/* ifrm_ctrlst register */
++#define IFRM_EN (1<<0)
++#define IFRM_BUFF_INIT_DONE (1<<1)
++#define IFRM_COMPARE_EN0 (1<<4)
++#define IFRM_COMPARE_EN1 (1<<5)
++#define IFRM_COMPARE_EN2 (1<<6)
++#define IFRM_COMPARE_EN3 (1<<7)
++#define IFRM_INIT_DV0 (1<<8)
++#define IFRM_INIT_DV1 (1<<9)
++#define IFRM_INIT_DV2 (1<<10)
++#define IFRM_INIT_DV3 (1<<11)
++
++/* ifrm_msk_arr.addr, ifrm_tid_arr.addr register */
++#define IFRM_ADDR_SHIFT 0
++#define IFRM_FRG_ID_SHIFT 8
++
++/* ifrm_vec.diff_lat register */
++#define IFRM_DV_LAT			(1<<0)
++#define IFRM_DV_LAT_DONE	(1<<1)
++#define IFRM_SDV_OFFSET_SHIFT	4
++#define IFRM_SDV_FRGID_SHIFT	8
++#define IFRM_VECSTAT_MASK		0x3
++#define IFRM_VEC_MASK			0xff
++
++/* idma frm array */
++typedef struct pcie_ifrm_array {
++	uint32		addr;
++	uint32		data;
++} pcie_ifrm_array_t;
++
++/* idma frm vector */
++typedef struct pcie_ifrm_vector {
++	uint32		diff_lat;
++	uint32		sav_tid;
++	uint32		sav_diff;
++	uint32		PAD[1];
++} pcie_ifrm_vector_t;
++
++/* idma frm interrupt */
++typedef struct pcie_ifrm_intr {
++	uint32		intstat;
++	uint32		intmask;
++} pcie_ifrm_intr_t;
++
++/* SB side: PCIE core and host control registers */
++typedef volatile struct sbpcieregs {
++	uint32 control;		/* host mode only */
++	uint32 iocstatus;	/* PCIE2: iostatus */
++	uint32 PAD[1];
++	uint32 biststatus;	/* bist Status: 0x00C */
++	uint32 gpiosel;		/* PCIE gpio sel: 0x010 */
++	uint32 gpioouten;	/* PCIE gpio outen: 0x14 */
++	uint32 PAD[2];
++	uint32 intstatus;	/* Interrupt status: 0x20 */
++	uint32 intmask;		/* Interrupt mask: 0x24 */
++	uint32 sbtopcimailbox;	/* sb to pcie mailbox: 0x028 */
++	uint32 obffcontrol;	/* PCIE2: 0x2C */
++	uint32 obffintstatus;	/* PCIE2: 0x30 */
++	uint32 obffdatastatus;	/* PCIE2: 0x34 */
++	uint32 PAD[1];
++	uint32 ctoctrl;		/* PCIE2: 0x3C */
++	uint32 errlog;		/* PCIE2: 0x40 */
++	uint32 errlogaddr;	/* PCIE2: 0x44 */
++	uint32 mailboxint;	/* PCIE2: 0x48 */
++	uint32 mailboxintmsk; /* PCIE2: 0x4c */
++	uint32 ltrspacing;	/* PCIE2: 0x50 */
++	uint32 ltrhysteresiscnt;	/* PCIE2: 0x54 */
++	uint32 msivectorassign;	/* PCIE2: 0x58 */
++	uint32 intmask2;	/* PCIE2: 0x5C */
++	uint32 PAD[40];
++	uint32 sbtopcie0;	/* sb to pcie translation 0: 0x100 */
++	uint32 sbtopcie1;	/* sb to pcie translation 1: 0x104 */
++	uint32 sbtopcie2;	/* sb to pcie translation 2: 0x108 */
++	uint32 PAD[5];
++
++	/* pcie core supports in direct access to config space */
++	uint32 configaddr;	/* pcie config space access: Address field: 0x120 */
++	uint32 configdata;	/* pcie config space access: Data field: 0x124 */
++	union {
++		struct {
++			/* mdio access to serdes */
++			uint32 mdiocontrol;	/* controls the mdio access: 0x128 */
++			uint32 mdiodata;	/* Data to the mdio access: 0x12c */
++			/* pcie protocol phy/dllp/tlp register indirect access mechanism */
++			uint32 pcieindaddr; /* indirect access to the internal register: 0x130 */
++			uint32 pcieinddata;	/* Data to/from the internal regsiter: 0x134 */
++			uint32 clkreqenctrl;	/* >= rev 6, Clkreq rdma control : 0x138 */
++			uint32 PAD[177];
++			/* 0x400 - 0x7FF, PCIE Cfg Space, note: not used anymore in PcieGen2 */
++			uint32 pciecfg[4][64];
++		} pcie1;
++		struct {
++			/* mdio access to serdes */
++			uint32 mdiocontrol;	/* controls the mdio access: 0x128 */
++			uint32 mdiowrdata;	/* write data to mdio 0x12C */
++			uint32 mdiorddata;	/* read data to mdio 0x130 */
++			uint32	PAD[3]; 	/* 0x134-0x138-0x13c */
++			/* door bell registers available from gen2 rev5 onwards */
++			pcie_doorbell_t	   dbls[PCIEDEV_MAX_DMAS]; /* 0x140 - 0x17F */
++			uint32	dataintf;	/* 0x180 */
++			uint32  PAD[1];		/* 0x184 */
++			uint32	d2h_intrlazy_0; /* 0x188 */
++			uint32	h2d_intrlazy_0; /* 0x18c */
++			uint32  h2d_intstat_0;  /* 0x190 */
++			uint32  h2d_intmask_0;	/* 0x194 */
++			uint32  d2h_intstat_0;  /* 0x198 */
++			uint32  d2h_intmask_0;  /* 0x19c */
++			uint32	ltr_state;	/* 0x1A0 */
++			uint32	pwr_int_status;	/* 0x1A4 */
++			uint32	pwr_int_mask;	/* 0x1A8 */
++			uint32	pme_source; /* 0x1AC */
++			uint32	err_hdr_logreg1; /* 0x1B0 */
++			uint32	err_hdr_logreg2; /* 0x1B4 */
++			uint32	err_hdr_logreg3; /* 0x1B8 */
++			uint32	err_hdr_logreg4; /* 0x1BC */
++			uint32	err_code_logreg; /* 0x1C0 */
++			uint32  PAD[7]; /* 0x1C4 - 0x1DF */
++			uint32  clk_ctl_st;	/* 0x1E0 */
++			uint32  PAD[1];		/* 0x1E4 */
++			uint32	powerctl;	/* 0x1E8 */
++			uint32  PAD[5];		/* 0x1EC - 0x1FF */
++			pcie_devdmaregs_t  h2d0_dmaregs; /* 0x200 - 0x23c */
++			pcie_devdmaregs_t  d2h0_dmaregs; /* 0x240 - 0x27c */
++			pcie_devdmaregs_t  h2d1_dmaregs; /* 0x280 - 0x2bc */
++			pcie_devdmaregs_t  d2h1_dmaregs; /* 0x2c0 - 0x2fc */
++			pcie_devdmaregs_t  h2d2_dmaregs; /* 0x300 - 0x33c */
++			pcie_devdmaregs_t  d2h2_dmaregs; /* 0x340 - 0x37c */
++			pcie_devdmaregs_t  h2d3_dmaregs; /* 0x380 - 0x3bc */
++			pcie_devdmaregs_t  d2h3_dmaregs; /* 0x3c0 - 0x3fc */
++			uint32	d2h_intrlazy_1; /* 0x400 */
++			uint32	h2d_intrlazy_1; /* 0x404 */
++			uint32	h2d_intstat_1;	/* 0x408 */
++			uint32	h2d_intmask_1;	/* 0x40c */
++			uint32	d2h_intstat_1;	/* 0x410 */
++			uint32	d2h_intmask_1;	/* 0x414 */
++			uint32	PAD[2];			/* 0x418 - 0x41C */
++			uint32	d2h_intrlazy_2; /* 0x420 */
++			uint32	h2d_intrlazy_2; /* 0x424 */
++			uint32	h2d_intstat_2;	/* 0x428 */
++			uint32	h2d_intmask_2;	/* 0x42c */
++			uint32	d2h_intstat_2;	/* 0x430 */
++			uint32	d2h_intmask_2;	/* 0x434 */
++			uint32	PAD[10];		/* 0x438 - 0x45F */
++			uint32	ifrm_ctrlst;	/* 0x460 */
++			uint32	PAD[1];			/* 0x464 */
++			pcie_ifrm_array_t	ifrm_msk_arr;		/* 0x468 - 0x46F */
++			pcie_ifrm_array_t	ifrm_tid_arr[IFRM_FR_DEV_VALID];
++				/* 0x470 - 0x47F */
++			pcie_ifrm_vector_t	ifrm_vec[IFRM_FR_DEV_MAX];
++				/* 0x480 - 0x4FF */
++			pcie_ifrm_intr_t	ifrm_intr[IFRM_FR_DEV_MAX];
++				/* 0x500 - 0x53F */
++			uint32	PAD[48];		/* 0x540 - 0x5FF */
++			uint32	PAD[2][64];		/* 0x600 - 0x7FF */
++		} pcie2;
++	} u;
++	uint16	sprom[64];		/* SPROM shadow Area : 0x800 - 0x880 */
++	uint32	PAD[96];		/* 0x880 - 0x9FF */
++	/* direct memory access (pcie2 rev19 and after) : 0xA00 - 0xAFF */
++	uint32		PAD[16];	/* 0xA00 - 0xA3F */
++	uint32		dm_errlog;	/* 0xA40 */
++	uint32		dm_erraddr;	/* 0xA44 */
++	uint32		PAD[37];	/* 0xA48 - 0xADC */
++	uint32		dm_clk_ctl_st;	/* 0xAE0 */
++	uint32		PAD[1];		/* 0xAE4 */
++	uint32		dm_powerctl;	/* 0xAE8 */
++} sbpcieregs_t;
++
++#define PCIE_CFG_DA_OFFSET 0x400	/* direct access register offset for configuration space */
++
++/* PCI control */
++#define PCIE_RST_OE	0x01	/* When set, drives PCI_RESET out to pin */
++#define PCIE_RST	0x02	/* Value driven out to pin */
++#define PCIE_SPERST	0x04	/* SurvivePeRst */
++#define PCIE_FORCECFGCLKON_ALP	0x08
++#define PCIE_DISABLE_L1CLK_GATING	0x10
++#define PCIE_DLYPERST	0x100	/* Delay PeRst to CoE Core */
++#define PCIE_DISSPROMLD	0x200	/* DisableSpromLoadOnPerst */
++#define PCIE_WakeModeL2	0x1000	/* Wake on L2 */
++#define PCIE_MULTIMSI_EN		0x2000	/* enable multi-vector MSI messages */
++#define PCIE_PipeIddqDisable0	0x8000	/* Disable assertion of pcie_pipe_iddq during L1.2 and L2 */
++#define PCIE_PipeIddqDisable1	0x10000	/* Disable assertion of pcie_pipe_iddq during L2 */
++#define PCIE_MSI_B2B_EN		0x100000	/* enable back-to-back MSI messages */
++#define PCIE_MSI_FIFO_CLEAR	0x200000	/* reset MSI FIFO */
++#define PCIE_IDMA_MODE_EN		0x800000	/* implicit M2M DMA mode */
++
++#define	PCIE_CFGADDR	0x120	/* offsetof(configaddr) */
++#define	PCIE_CFGDATA	0x124	/* offsetof(configdata) */
++#define PCIE_SWPME_FN0	0x10000
++#define PCIE_SWPME_FN0_SHF 16
++
++/* Interrupt status/mask */
++#define PCIE_INTA	0x01	/* PCIE INTA message is received */
++#define PCIE_INTB	0x02	/* PCIE INTB message is received */
++#define PCIE_INTFATAL	0x04	/* PCIE INTFATAL message is received */
++#define PCIE_INTNFATAL	0x08	/* PCIE INTNONFATAL message is received */
++#define PCIE_INTCORR	0x10	/* PCIE INTCORR message is received */
++#define PCIE_INTPME	0x20	/* PCIE INTPME message is received */
++#define PCIE_PERST	0x40	/* PCIE Reset Interrupt */
++
++#define PCIE_INT_MB_FN0_0 0x0100 /* PCIE to SB Mailbox int Fn0.0 is received */
++#define PCIE_INT_MB_FN0_1 0x0200 /* PCIE to SB Mailbox int Fn0.1 is received */
++#define PCIE_INT_MB_FN1_0 0x0400 /* PCIE to SB Mailbox int Fn1.0 is received */
++#define PCIE_INT_MB_FN1_1 0x0800 /* PCIE to SB Mailbox int Fn1.1 is received */
++#define PCIE_INT_MB_FN2_0 0x1000 /* PCIE to SB Mailbox int Fn2.0 is received */
++#define PCIE_INT_MB_FN2_1 0x2000 /* PCIE to SB Mailbox int Fn2.1 is received */
++#define PCIE_INT_MB_FN3_0 0x4000 /* PCIE to SB Mailbox int Fn3.0 is received */
++#define PCIE_INT_MB_FN3_1 0x8000 /* PCIE to SB Mailbox int Fn3.1 is received */
++
++/* PCIE MSI Vector Assignment register */
++#define MSIVEC_MB_0	(0x1 << 1) /* MSI Vector offset for mailbox0 is 2 */
++#define MSIVEC_MB_1	(0x1 << 2) /* MSI Vector offset for mailbox1 is 3 */
++#define MSIVEC_D2H0_DB0	(0x1 << 3) /* MSI Vector offset for interface0 door bell 0 is 4 */
++#define MSIVEC_D2H0_DB1	(0x1 << 4) /* MSI Vector offset for interface0 door bell 1 is 5 */
++
++/* PCIE MailboxInt/MailboxIntMask register */
++#define PCIE_MB_TOSB_FN0_0   	0x0001 /* write to assert PCIEtoSB Mailbox interrupt */
++#define PCIE_MB_TOSB_FN0_1   	0x0002
++#define PCIE_MB_TOSB_FN1_0   	0x0004
++#define PCIE_MB_TOSB_FN1_1   	0x0008
++#define PCIE_MB_TOSB_FN2_0   	0x0010
++#define PCIE_MB_TOSB_FN2_1   	0x0020
++#define PCIE_MB_TOSB_FN3_0   	0x0040
++#define PCIE_MB_TOSB_FN3_1   	0x0080
++#define PCIE_MB_TOPCIE_FN0_0 	0x0100 /* int status/mask for SBtoPCIE Mailbox interrupts */
++#define PCIE_MB_TOPCIE_FN0_1 	0x0200
++#define PCIE_MB_TOPCIE_FN1_0 	0x0400
++#define PCIE_MB_TOPCIE_FN1_1 	0x0800
++#define PCIE_MB_TOPCIE_FN2_0 	0x1000
++#define PCIE_MB_TOPCIE_FN2_1 	0x2000
++#define PCIE_MB_TOPCIE_FN3_0 	0x4000
++#define PCIE_MB_TOPCIE_FN3_1 	0x8000
++#define	PCIE_MB_TOPCIE_D2H0_DB0	0x10000
++#define	PCIE_MB_TOPCIE_D2H0_DB1	0x20000
++#define	PCIE_MB_TOPCIE_D2H1_DB0	0x40000
++#define	PCIE_MB_TOPCIE_D2H1_DB1	0x80000
++#define	PCIE_MB_TOPCIE_D2H2_DB0	0x100000
++#define	PCIE_MB_TOPCIE_D2H2_DB1	0x200000
++#define	PCIE_MB_TOPCIE_D2H3_DB0	0x400000
++#define	PCIE_MB_TOPCIE_D2H3_DB1	0x800000
++
++#define PCIE_MB_D2H_MB_MASK		\
++	(PCIE_MB_TOPCIE_D2H0_DB0 | PCIE_MB_TOPCIE_D2H0_DB1 |	\
++	PCIE_MB_TOPCIE_D2H1_DB0  | PCIE_MB_TOPCIE_D2H1_DB1 |	\
++	PCIE_MB_TOPCIE_D2H2_DB0  | PCIE_MB_TOPCIE_D2H2_DB1 |	\
++	PCIE_MB_TOPCIE_D2H3_DB0  | PCIE_MB_TOPCIE_D2H3_DB1)
++
++#define SBTOPCIE0_BASE 0x08000000
++#define SBTOPCIE1_BASE 0x0c000000
++
++/* On chips with CCI-400, the small pcie 128 MB region base has shifted */
++#define CCI400_SBTOPCIE0_BASE  0x20000000
++#define CCI400_SBTOPCIE1_BASE  0x24000000
++
++/* SB to PCIE translation masks */
++#define SBTOPCIE0_MASK	0xfc000000
++#define SBTOPCIE1_MASK	0xfc000000
++#define SBTOPCIE2_MASK	0xc0000000
++
++/* Access type bits (0:1) */
++#define SBTOPCIE_MEM	0
++#define SBTOPCIE_IO	1
++#define SBTOPCIE_CFG0	2
++#define SBTOPCIE_CFG1	3
++
++/* Prefetch enable bit 2 */
++#define SBTOPCIE_PF		4
++
++/* Write Burst enable for memory write bit 3 */
++#define SBTOPCIE_WR_BURST	8
++
++/* config access */
++#define CONFIGADDR_FUNC_MASK	0x7000
++#define CONFIGADDR_FUNC_SHF	12
++#define CONFIGADDR_REG_MASK	0x0FFF
++#define CONFIGADDR_REG_SHF	0
++
++#define PCIE_CONFIG_INDADDR(f, r)	((((f) & CONFIGADDR_FUNC_MASK) << CONFIGADDR_FUNC_SHF) | \
++			                 (((r) & CONFIGADDR_REG_MASK) << CONFIGADDR_REG_SHF))
++
++/* PCIE protocol regs Indirect Address */
++#define PCIEADDR_PROT_MASK	0x300
++#define PCIEADDR_PROT_SHF	8
++#define PCIEADDR_PL_TLP		0
++#define PCIEADDR_PL_DLLP	1
++#define PCIEADDR_PL_PLP		2
++
++#define	PCIE_CORE_REG_CONTROL		0x00u   /* Control     */
++#define	PCIE_CORE_REG_IOSTATUS		0x04u   /* IO status   */
++#define	PCIE_CORE_REG_BITSTATUS		0x0Cu   /* bitstatus   */
++#define	PCIE_CORE_REG_GPIO_SEL		0x10u   /* gpio sel    */
++#define	PCIE_CORE_REG_GPIO_OUT_EN	0x14u   /* gpio out en */
++#define	PCIE_CORE_REG_INT_STATUS	0x20u   /* int status  */
++#define	PCIE_CORE_REG_INT_MASK		0x24u   /* int mask    */
++#define	PCIE_CORE_REG_SB_PCIE_MB	0x28u   /* sbpcie mb   */
++#define	PCIE_CORE_REG_ERRLOG		0x40u   /* errlog      */
++#define	PCIE_CORE_REG_ERR_ADDR		0x44u   /* errlog addr */
++#define	PCIE_CORE_REG_MB_INTR		0x48u   /* MB intr     */
++#define	PCIE_CORE_REG_SB_PCIE_0		0x100u  /* sbpcie0 map */
++#define	PCIE_CORE_REG_SB_PCIE_1		0x104u  /* sbpcie1 map */
++#define	PCIE_CORE_REG_SB_PCIE_2		0x108u  /* sbpcie2 map */
++
++/* PCIE Config registers */
++#define	PCIE_CFG_DEV_STS_CTRL_2		0x0d4u	/* "dev_sts_control_2  */
++#define	PCIE_CFG_ADV_ERR_CAP		0x100u	/* adv_err_cap         */
++#define	PCIE_CFG_UC_ERR_STS		0x104u	/* uc_err_status       */
++#define	PCIE_CFG_UC_ERR_MASK		0x108u	/* ucorr_err_mask      */
++#define	PCIE_CFG_UNCOR_ERR_SERV		0x10cu	/* ucorr_err_sevr      */
++#define	PCIE_CFG_CORR_ERR_STS		0x110u	/* corr_err_status     */
++#define	PCIE_CFG_CORR_ERR_MASK		0x114u	/* corr_err_mask       */
++#define	PCIE_CFG_ADV_ERR_CTRL		0x118u	/* adv_err_cap_control */
++#define	PCIE_CFG_HDR_LOG1		0x11Cu	/* header_log1         */
++#define	PCIE_CFG_HDR_LOG2		0x120u	/* header_log2         */
++#define	PCIE_CFG_HDR_LOG3		0x124u	/* header_log3         */
++#define	PCIE_CFG_HDR_LOG4		0x128u	/* header_log4         */
++#define	PCIE_CFG_PML1_SUB_CAP_ID	0x240u	/* PML1sub_capID       */
++#define	PCIE_CFG_PML1_SUB_CAP_REG	0x244u	/* PML1_sub_Cap_reg    */
++#define	PCIE_CFG_PML1_SUB_CTRL1		0x248u	/* PML1_sub_control1   */
++#define	PCIE_CFG_PML1_SUB_CTRL3		0x24Cu	/* PML1_sub_control2   */
++#define	PCIE_CFG_TL_CTRL_5		0x814u	/* tl_control_5        */
++#define	PCIE_CFG_PHY_ERR_ATT_VEC	0x1820u	/* phy_err_attn_vec    */
++#define	PCIE_CFG_PHY_ERR_ATT_MASK	0x1824u	/* phy_err_attn_mask   */
++
++/* PCIE protocol PHY diagnostic registers */
++#define	PCIE_PLP_MODEREG		0x200u /* Mode */
++#define	PCIE_PLP_STATUSREG		0x204u /* Status */
++#define PCIE_PLP_LTSSMCTRLREG		0x208u /* LTSSM control */
++#define PCIE_PLP_LTLINKNUMREG		0x20cu /* Link Training Link number */
++#define PCIE_PLP_LTLANENUMREG		0x210u /* Link Training Lane number */
++#define PCIE_PLP_LTNFTSREG		0x214u /* Link Training N_FTS */
++#define PCIE_PLP_ATTNREG		0x218u /* Attention */
++#define PCIE_PLP_ATTNMASKREG		0x21Cu /* Attention Mask */
++#define PCIE_PLP_RXERRCTR		0x220u /* Rx Error */
++#define PCIE_PLP_RXFRMERRCTR		0x224u /* Rx Framing Error */
++#define PCIE_PLP_RXERRTHRESHREG		0x228u /* Rx Error threshold */
++#define PCIE_PLP_TESTCTRLREG		0x22Cu /* Test Control reg */
++#define PCIE_PLP_SERDESCTRLOVRDREG	0x230u /* SERDES Control Override */
++#define PCIE_PLP_TIMINGOVRDREG		0x234u /* Timing param override */
++#define PCIE_PLP_RXTXSMDIAGREG		0x238u /* RXTX State Machine Diag */
++#define PCIE_PLP_LTSSMDIAGREG		0x23Cu /* LTSSM State Machine Diag */
++
++/* PCIE protocol DLLP diagnostic registers */
++#define PCIE_DLLP_LCREG			0x100u /* Link Control */
++#define PCIE_DLLP_LSREG			0x104u /* Link Status */
++#define PCIE_DLLP_LAREG			0x108u /* Link Attention */
++#define PCIE_DLLP_LAMASKREG		0x10Cu /* Link Attention Mask */
++#define PCIE_DLLP_NEXTTXSEQNUMREG	0x110u /* Next Tx Seq Num */
++#define PCIE_DLLP_ACKEDTXSEQNUMREG	0x114u /* Acked Tx Seq Num */
++#define PCIE_DLLP_PURGEDTXSEQNUMREG	0x118u /* Purged Tx Seq Num */
++#define PCIE_DLLP_RXSEQNUMREG		0x11Cu /* Rx Sequence Number */
++#define PCIE_DLLP_LRREG			0x120u /* Link Replay */
++#define PCIE_DLLP_LACKTOREG		0x124u /* Link Ack Timeout */
++#define PCIE_DLLP_PMTHRESHREG		0x128u /* Power Management Threshold */
++#define PCIE_DLLP_RTRYWPREG		0x12Cu /* Retry buffer write ptr */
++#define PCIE_DLLP_RTRYRPREG		0x130u /* Retry buffer Read ptr */
++#define PCIE_DLLP_RTRYPPREG		0x134u /* Retry buffer Purged ptr */
++#define PCIE_DLLP_RTRRWREG		0x138u /* Retry buffer Read/Write */
++#define PCIE_DLLP_ECTHRESHREG		0x13Cu /* Error Count Threshold */
++#define PCIE_DLLP_TLPERRCTRREG		0x140u /* TLP Error Counter */
++#define PCIE_DLLP_ERRCTRREG		0x144u /* Error Counter */
++#define PCIE_DLLP_NAKRXCTRREG		0x148u /* NAK Received Counter */
++#define PCIE_DLLP_TESTREG		0x14Cu /* Test */
++#define PCIE_DLLP_PKTBIST		0x150u /* Packet BIST */
++#define PCIE_DLLP_PCIE11		0x154u /* DLLP PCIE 1.1 reg */
++
++#define PCIE_DLLP_LSREG_LINKUP		(1u << 16u)
++
++/* PCIE protocol TLP diagnostic registers */
++#define PCIE_TLP_CONFIGREG		0x000u /* Configuration */
++#define PCIE_TLP_WORKAROUNDSREG		0x004u /* TLP Workarounds */
++#define PCIE_TLP_WRDMAUPPER		0x010u /* Write DMA Upper Address */
++#define PCIE_TLP_WRDMALOWER		0x014u /* Write DMA Lower Address */
++#define PCIE_TLP_WRDMAREQ_LBEREG	0x018u /* Write DMA Len/ByteEn Req */
++#define PCIE_TLP_RDDMAUPPER		0x01Cu /* Read DMA Upper Address */
++#define PCIE_TLP_RDDMALOWER		0x020u /* Read DMA Lower Address */
++#define PCIE_TLP_RDDMALENREG		0x024u /* Read DMA Len Req */
++#define PCIE_TLP_MSIDMAUPPER		0x028u /* MSI DMA Upper Address */
++#define PCIE_TLP_MSIDMALOWER		0x02Cu /* MSI DMA Lower Address */
++#define PCIE_TLP_MSIDMALENREG		0x030u /* MSI DMA Len Req */
++#define PCIE_TLP_SLVREQLENREG		0x034u /* Slave Request Len */
++#define PCIE_TLP_FCINPUTSREQ		0x038u /* Flow Control Inputs */
++#define PCIE_TLP_TXSMGRSREQ		0x03Cu /* Tx StateMachine and Gated Req */
++#define PCIE_TLP_ADRACKCNTARBLEN	0x040u /* Address Ack XferCnt and ARB Len */
++#define PCIE_TLP_DMACPLHDR0		0x044u /* DMA Completion Hdr 0 */
++#define PCIE_TLP_DMACPLHDR1		0x048u /* DMA Completion Hdr 1 */
++#define PCIE_TLP_DMACPLHDR2		0x04Cu /* DMA Completion Hdr 2 */
++#define PCIE_TLP_DMACPLMISC0		0x050u /* DMA Completion Misc0 */
++#define PCIE_TLP_DMACPLMISC1		0x054u /* DMA Completion Misc1 */
++#define PCIE_TLP_DMACPLMISC2		0x058u /* DMA Completion Misc2 */
++#define PCIE_TLP_SPTCTRLLEN		0x05Cu /* Split Controller Req len */
++#define PCIE_TLP_SPTCTRLMSIC0		0x060u /* Split Controller Misc 0 */
++#define PCIE_TLP_SPTCTRLMSIC1		0x064u /* Split Controller Misc 1 */
++#define PCIE_TLP_BUSDEVFUNC		0x068u /* Bus/Device/Func */
++#define PCIE_TLP_RESETCTR		0x06Cu /* Reset Counter */
++#define PCIE_TLP_RTRYBUF		0x070u /* Retry Buffer value */
++#define PCIE_TLP_TGTDEBUG1		0x074u /* Target Debug Reg1 */
++#define PCIE_TLP_TGTDEBUG2		0x078u /* Target Debug Reg2 */
++#define PCIE_TLP_TGTDEBUG3		0x07Cu /* Target Debug Reg3 */
++#define PCIE_TLP_TGTDEBUG4		0x080u /* Target Debug Reg4 */
++
++/* PCIE2 MDIO register offsets */
++#define PCIE2_MDIO_CONTROL    0x128
++#define PCIE2_MDIO_WR_DATA    0x12C
++#define PCIE2_MDIO_RD_DATA    0x130
++
++
++/* MDIO control */
++#define MDIOCTL_DIVISOR_MASK		0x7fu	/* clock to be used on MDIO */
++#define MDIOCTL_DIVISOR_VAL		0x2u
++#define MDIOCTL_PREAM_EN		0x80u	/* Enable preamble sequnce */
++#define MDIOCTL_ACCESS_DONE		0x100u   /* Tranaction complete */
++
++/* MDIO Data */
++#define MDIODATA_MASK			0x0000ffff	/* data 2 bytes */
++#define MDIODATA_TA			0x00020000	/* Turnaround */
++#define MDIODATA_REGADDR_SHF_OLD	18		/* Regaddr shift (rev < 10) */
++#define MDIODATA_REGADDR_MASK_OLD	0x003c0000	/* Regaddr Mask (rev < 10) */
++#define MDIODATA_DEVADDR_SHF_OLD	22		/* Physmedia devaddr shift (rev < 10) */
++#define MDIODATA_DEVADDR_MASK_OLD	0x0fc00000	/* Physmedia devaddr Mask (rev < 10) */
++#define MDIODATA_REGADDR_SHF		18		/* Regaddr shift */
++#define MDIODATA_REGADDR_MASK		0x007c0000	/* Regaddr Mask */
++#define MDIODATA_DEVADDR_SHF		23		/* Physmedia devaddr shift */
++#define MDIODATA_DEVADDR_MASK		0x0f800000	/* Physmedia devaddr Mask */
++#define MDIODATA_WRITE			0x10000000	/* write Transaction */
++#define MDIODATA_READ			0x20000000	/* Read Transaction */
++#define MDIODATA_START			0x40000000	/* start of Transaction */
++
++#define MDIODATA_DEV_ADDR		0x0		/* dev address for serdes */
++#define	MDIODATA_BLK_ADDR		0x1F		/* blk address for serdes */
++
++/* MDIO control/wrData/rdData register defines for PCIE Gen 2 */
++#define MDIOCTL2_DIVISOR_MASK		0x7f	/* clock to be used on MDIO */
++#define MDIOCTL2_DIVISOR_VAL		0x2
++#define MDIOCTL2_REGADDR_SHF		8		/* Regaddr shift */
++#define MDIOCTL2_REGADDR_MASK		0x00FFFF00	/* Regaddr Mask */
++#define MDIOCTL2_DEVADDR_SHF		24		/* Physmedia devaddr shift */
++#define MDIOCTL2_DEVADDR_MASK		0x0f000000	/* Physmedia devaddr Mask */
++#define MDIOCTL2_SLAVE_BYPASS		0x10000000	/* IP slave bypass */
++#define MDIOCTL2_READ			0x20000000	/* IP slave bypass */
++
++#define MDIODATA2_DONE			0x80000000u	/* rd/wr transaction done */
++#define MDIODATA2_MASK			0x7FFFFFFF	/* rd/wr transaction data */
++#define MDIODATA2_DEVADDR_SHF		4		/* Physmedia devaddr shift */
++
++
++/* MDIO devices (SERDES modules)
++ *  unlike old pcie cores (rev < 10), rev10 pcie serde organizes registers into a few blocks.
++ *  two layers mapping (blockidx, register offset) is required
++ */
++#define MDIO_DEV_IEEE0		0x000
++#define MDIO_DEV_IEEE1		0x001
++#define MDIO_DEV_BLK0		0x800
++#define MDIO_DEV_BLK1		0x801
++#define MDIO_DEV_BLK2		0x802
++#define MDIO_DEV_BLK3		0x803
++#define MDIO_DEV_BLK4		0x804
++#define MDIO_DEV_TXPLL		0x808	/* TXPLL register block idx */
++#define MDIO_DEV_TXCTRL0	0x820
++#define MDIO_DEV_SERDESID	0x831
++#define MDIO_DEV_RXCTRL0	0x840
++
++
++/* XgxsBlk1_A Register Offsets */
++#define BLK1_PWR_MGMT0		0x16
++#define BLK1_PWR_MGMT1		0x17
++#define BLK1_PWR_MGMT2		0x18
++#define BLK1_PWR_MGMT3		0x19
++#define BLK1_PWR_MGMT4		0x1A
++
++/* serdes regs (rev < 10) */
++#define MDIODATA_DEV_PLL       		0x1d	/* SERDES PLL Dev */
++#define MDIODATA_DEV_TX        		0x1e	/* SERDES TX Dev */
++#define MDIODATA_DEV_RX        		0x1f	/* SERDES RX Dev */
++	/* SERDES RX registers */
++#define SERDES_RX_CTRL			1	/* Rx cntrl */
++#define SERDES_RX_TIMER1		2	/* Rx Timer1 */
++#define SERDES_RX_CDR			6	/* CDR */
++#define SERDES_RX_CDRBW			7	/* CDR BW */
++
++	/* SERDES RX control register */
++#define SERDES_RX_CTRL_FORCE		0x80	/* rxpolarity_force */
++#define SERDES_RX_CTRL_POLARITY		0x40	/* rxpolarity_value */
++
++	/* SERDES PLL registers */
++#define SERDES_PLL_CTRL                 1       /* PLL control reg */
++#define PLL_CTRL_FREQDET_EN             0x4000  /* bit 14 is FREQDET on */
++
++/* Power management threshold */
++#define PCIE_L0THRESHOLDTIME_MASK       0xFF00u	/* bits 0 - 7 */
++#define PCIE_L1THRESHOLDTIME_MASK       0xFF00u	/* bits 8 - 15 */
++#define PCIE_L1THRESHOLDTIME_SHIFT      8	/* PCIE_L1THRESHOLDTIME_SHIFT */
++#define PCIE_L1THRESHOLD_WARVAL         0x72	/* WAR value */
++#define PCIE_ASPMTIMER_EXTEND		0x01000000	/* > rev7: enable extend ASPM timer */
++
++/* SPROM offsets */
++#define SRSH_ASPM_OFFSET		4	/* word 4 */
++#define SRSH_ASPM_ENB			0x18	/* bit 3, 4 */
++#define SRSH_ASPM_L1_ENB		0x10	/* bit 4 */
++#define SRSH_ASPM_L0s_ENB		0x8	/* bit 3 */
++#define SRSH_PCIE_MISC_CONFIG		5	/* word 5 */
++#define SRSH_L23READY_EXIT_NOPERST	0x8000u	/* bit 15 */
++#define SRSH_CLKREQ_OFFSET_REV5		20	/* word 20 for srom rev <= 5 */
++#define SRSH_CLKREQ_OFFSET_REV8		52	/* word 52 for srom rev 8 */
++#define SRSH_CLKREQ_ENB			0x0800	/* bit 11 */
++#define SRSH_BD_OFFSET                  6       /* word 6 */
++#define SRSH_AUTOINIT_OFFSET            18      /* auto initialization enable */
++
++/* PCI Capability ID's
++ * Reference include/linux/pci_regs.h
++ * #define  PCI_CAP_LIST_ID	0       // Capability ID
++ * #define  PCI_CAP_ID_PM		0x01    // Power Management
++ * #define  PCI_CAP_ID_AGP		0x02    // Accelerated Graphics Port
++ * #define  PCI_CAP_ID_VPD		0x03    // Vital Product Data
++ * #define  PCI_CAP_ID_SLOTID	0x04    // Slot Identification
++ * #define  PCI_CAP_ID_MSI		0x05    // Message Signalled Interrupts
++ * #define  PCI_CAP_ID_CHSWP       0x06    // CompactPCI HotSwap
++ * #define  PCI_CAP_ID_PCIX        0x07    // PCI-X
++ * #define  PCI_CAP_ID_HT          0x08    // HyperTransport
++ * #define  PCI_CAP_ID_VNDR        0x09    // Vendor-Specific
++ * #define  PCI_CAP_ID_DBG         0x0A    // Debug port
++ * #define  PCI_CAP_ID_CCRC        0x0B    // CompactPCI Central Resource Control
++ * #define  PCI_CAP_ID_SHPC        0x0C    // PCI Standard Hot-Plug Controller
++ * #define  PCI_CAP_ID_SSVID       0x0D    // Bridge subsystem vendor/device ID
++ * #define  PCI_CAP_ID_AGP3        0x0E    // AGP Target PCI-PCI bridge
++ * #define  PCI_CAP_ID_SECDEV      0x0F    // Secure Device
++ * #define  PCI_CAP_ID_MSIX        0x11    // MSI-X
++ * #define  PCI_CAP_ID_SATA        0x12    // SATA Data/Index Conf.
++ * #define  PCI_CAP_ID_AF          0x13    // PCI Advanced Features
++ * #define  PCI_CAP_ID_EA          0x14    // PCI Enhanced Allocation
++ * #define  PCI_CAP_ID_MAX         PCI_CAP_ID_EA
++ */
++
++#define  PCIE_CAP_ID_EXP         0x10    // PCI Express
++
++/* PCIe Capabilities Offsets
++ * Reference include/linux/pci_regs.h
++ * #define PCIE_CAP_FLAGS           2       // Capabilities register
++ * #define PCIE_CAP_DEVCAP          4       // Device capabilities
++ * #define PCIE_CAP_DEVCTL          8       // Device Control
++ * #define PCIE_CAP_DEVSTA          10      // Device Status
++ * #define PCIE_CAP_LNKCAP          12      // Link Capabilities
++ * #define PCIE_CAP_LNKCTL          16      // Link Control
++ * #define PCIE_CAP_LNKSTA          18      // Link Status
++ * #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1  20      // v1 endpoints end here
++ * #define PCIE_CAP_SLTCAP          20      // Slot Capabilities
++ * #define PCIE_CAP_SLTCTL          24      // Slot Control
++ * #define PCIE_CAP_SLTSTA          26      // Slot Status
++ * #define PCIE_CAP_RTCTL           28      // Root Control
++ * #define PCIE_CAP_RTCAP           30      // Root Capabilities
++ * #define PCIE_CAP_RTSTA           32      // Root Status
++ */
++
++
++/* Linkcapability reg offset in PCIE Cap */
++#define PCIE_CAP_LINKCAP_OFFSET         12      /* linkcap offset in pcie cap */
++#define PCIE_CAP_LINKCAP_LNKSPEED_MASK	0xf     /* Supported Link Speeds */
++#define PCIE_CAP_LINKCAP_GEN2           0x2     /* Value for GEN2 */
++
++/* Uc_Err reg offset in AER Cap */
++#define PCIE_EXTCAP_ID_ERR		0x01	/* Advanced Error Reporting */
++#define PCIE_EXTCAP_AER_UCERR_OFFSET	4	/* Uc_Err reg offset in AER Cap */
++
++/* Linkcontrol reg offset in PCIE Cap */
++#define PCIE_CAP_LINKCTRL_OFFSET	16	/* linkctrl offset in pcie cap */
++#define PCIE_CAP_LCREG_ASPML0s		0x01	/* ASPM L0s in linkctrl */
++#define PCIE_CAP_LCREG_ASPML1		0x02	/* ASPM L1 in linkctrl */
++#define PCIE_CLKREQ_ENAB		0x100	/* CLKREQ Enab in linkctrl */
++#define PCIE_LINKSPEED_MASK		0xF0000u	/* bits 0 - 3 of high word */
++#define PCIE_LINKSPEED_SHIFT		16	/* PCIE_LINKSPEED_SHIFT */
++
++/* Devcontrol reg offset in PCIE Cap */
++#define PCIE_CAP_DEVCTRL_OFFSET		8	/* devctrl offset in pcie cap */
++#define PCIE_CAP_DEVCTRL_MRRS_MASK	0x7000	/* Max read request size mask */
++#define PCIE_CAP_DEVCTRL_MRRS_SHIFT	12	/* Max read request size shift */
++#define PCIE_CAP_DEVCTRL_MRRS_128B	0	/* 128 Byte */
++#define PCIE_CAP_DEVCTRL_MRRS_256B	1	/* 256 Byte */
++#define PCIE_CAP_DEVCTRL_MRRS_512B	2	/* 512 Byte */
++#define PCIE_CAP_DEVCTRL_MRRS_1024B	3	/* 1024 Byte */
++#define PCIE_CAP_DEVCTRL_MPS_MASK	0x00e0	/* Max payload size mask */
++#define PCIE_CAP_DEVCTRL_MPS_SHIFT	5	/* Max payload size shift */
++#define PCIE_CAP_DEVCTRL_MPS_128B	0	/* 128 Byte */
++#define PCIE_CAP_DEVCTRL_MPS_256B	1	/* 256 Byte */
++#define PCIE_CAP_DEVCTRL_MPS_512B	2	/* 512 Byte */
++#define PCIE_CAP_DEVCTRL_MPS_1024B	3	/* 1024 Byte */
++
++#define PCIE_ASPM_ENAB			3	/* ASPM L0s & L1 in linkctrl */
++#define PCIE_ASPM_L1_ENAB		2	/* ASPM L0s & L1 in linkctrl */
++#define PCIE_ASPM_L0s_ENAB		1	/* ASPM L0s & L1 in linkctrl */
++#define PCIE_ASPM_DISAB			0	/* ASPM L0s & L1 in linkctrl */
++
++#define PCIE_ASPM_L11_ENAB		8	/* ASPM L1.1 in PML1_sub_control2 */
++#define PCIE_ASPM_L12_ENAB		4	/* ASPM L1.2 in PML1_sub_control2 */
++
++/* NumMsg and NumMsgEn in PCIE MSI Cap */
++#define MSICAP_NUM_MSG_SHF		17
++#define MSICAP_NUM_MSG_MASK		(0x7 << MSICAP_NUM_MSG_SHF)
++#define MSICAP_NUM_MSG_EN_SHF	20
++#define MSICAP_NUM_MSG_EN_MASK	(0x7 << MSICAP_NUM_MSG_EN_SHF)
++
++/* Devcontrol2 reg offset in PCIE Cap */
++#define PCIE_CAP_DEVCTRL2_OFFSET	0x28	/* devctrl2 offset in pcie cap */
++#define PCIE_CAP_DEVCTRL2_LTR_ENAB_MASK	0x400	/* Latency Tolerance Reporting Enable */
++#define PCIE_CAP_DEVCTRL2_OBFF_ENAB_SHIFT 13	/* Enable OBFF mechanism, select signaling method */
++#define PCIE_CAP_DEVCTRL2_OBFF_ENAB_MASK 0x6000	/* Enable OBFF mechanism, select signaling method */
++
++/* LTR registers in PCIE Cap */
++#define PCIE_LTR0_REG_OFFSET	0x844u	/* ltr0_reg offset in pcie cap */
++#define PCIE_LTR1_REG_OFFSET	0x848u	/* ltr1_reg offset in pcie cap */
++#define PCIE_LTR2_REG_OFFSET	0x84cu	/* ltr2_reg offset in pcie cap */
++#define PCIE_LTR0_REG_DEFAULT_60	0x883c883cu	/* active latency default to 60usec */
++#define PCIE_LTR0_REG_DEFAULT_150	0x88968896u	/* active latency default to 150usec */
++#define PCIE_LTR1_REG_DEFAULT		0x88648864u	/* idle latency default to 100usec */
++#define PCIE_LTR2_REG_DEFAULT		0x90039003u	/* sleep latency default to 3msec */
++
++/* Status reg PCIE_PLP_STATUSREG */
++#define PCIE_PLP_POLARITYINV_STAT	0x10
++
++
++/* PCIE BRCM Vendor CAP REVID reg  bits */
++#define BRCMCAP_PCIEREV_CT_MASK			0xF00u
++#define BRCMCAP_PCIEREV_CT_SHIFT		8u
++#define BRCMCAP_PCIEREV_REVID_MASK		0xFFu
++#define BRCMCAP_PCIEREV_REVID_SHIFT		0
++
++#define PCIE_REVREG_CT_PCIE1		0
++#define PCIE_REVREG_CT_PCIE2		1
++
++/* PCIE GEN2 specific defines */
++/* PCIE BRCM Vendor Cap offsets w.r.t to vendor cap ptr */
++#define PCIE2R0_BRCMCAP_REVID_OFFSET		4
++#define PCIE2R0_BRCMCAP_BAR0_WIN0_WRAP_OFFSET	8
++#define PCIE2R0_BRCMCAP_BAR0_WIN2_OFFSET	12
++#define PCIE2R0_BRCMCAP_BAR0_WIN2_WRAP_OFFSET	16
++#define PCIE2R0_BRCMCAP_BAR0_WIN_OFFSET		20
++#define PCIE2R0_BRCMCAP_BAR1_WIN_OFFSET		24
++#define PCIE2R0_BRCMCAP_SPROM_CTRL_OFFSET	28
++#define PCIE2R0_BRCMCAP_BAR2_WIN_OFFSET		32
++#define PCIE2R0_BRCMCAP_INTSTATUS_OFFSET	36
++#define PCIE2R0_BRCMCAP_INTMASK_OFFSET		40
++#define PCIE2R0_BRCMCAP_PCIE2SB_MB_OFFSET	44
++#define PCIE2R0_BRCMCAP_BPADDR_OFFSET		48
++#define PCIE2R0_BRCMCAP_BPDATA_OFFSET		52
++#define PCIE2R0_BRCMCAP_CLKCTLSTS_OFFSET	56
++
++/* definition of configuration space registers of PCIe gen2
++ * http://hwnbu-twiki.sj.broadcom.com/twiki/pub/Mwgroup/CurrentPcieGen2ProgramGuide/pcie_ep.htm
++ */
++#define PCIECFGREG_STATUS_CMD		0x4
++#define PCIECFGREG_PM_CSR		0x4C
++#define PCIECFGREG_MSI_CAP		0x58
++#define PCIECFGREG_MSI_ADDR_L		0x5C
++#define PCIECFGREG_MSI_ADDR_H		0x60
++#define PCIECFGREG_MSI_DATA		0x64
++#define PCIECFGREG_LINK_STATUS_CTRL	0xBCu
++#define PCIECFGREG_DEV_STATUS_CTRL 0xB4u
++#define PCIECFGGEN_DEV_STATUS_CTRL2	0xD4
++#define PCIECFGREG_LINK_STATUS_CTRL2	0xDCu
++#define PCIECFGREG_RBAR_CTRL		0x228
++#define PCIECFGREG_PML1_SUB_CTRL1	0x248
++#define PCIECFGREG_PML1_SUB_CTRL2	0x24C
++#define PCIECFGREG_REG_BAR2_CONFIG	0x4E0
++#define PCIECFGREG_REG_BAR3_CONFIG	0x4F4
++#define PCIECFGREG_PDL_CTRL1		0x1004
++#define PCIECFGREG_PDL_IDDQ		0x1814
++#define PCIECFGREG_REG_PHY_CTL7		0x181c
++#define PCIECFGREG_PHY_DBG_CLKREQ0		0x1E10
++#define PCIECFGREG_PHY_DBG_CLKREQ1		0x1E14
++#define PCIECFGREG_PHY_DBG_CLKREQ2		0x1E18
++#define PCIECFGREG_PHY_DBG_CLKREQ3		0x1E1C
++
++/* PCIECFGREG_PML1_SUB_CTRL1 Bit Definition */
++#define PCI_PM_L1_2_ENA_MASK		0x00000001	/* PCI-PM L1.2 Enabled */
++#define PCI_PM_L1_1_ENA_MASK		0x00000002	/* PCI-PM L1.1 Enabled */
++#define ASPM_L1_2_ENA_MASK		0x00000004	/* ASPM L1.2 Enabled */
++#define ASPM_L1_1_ENA_MASK		0x00000008	/* ASPM L1.1 Enabled */
++
++/* PCIe gen2 mailbox interrupt masks */
++#define I_MB    0x3
++#define I_BIT0  0x1
++#define I_BIT1  0x2
++
++/* PCIE gen2 config regs */
++#define PCIIntstatus	0x090
++#define PCIIntmask	0x094
++#define PCISBMbx	0x98
++
++/* enumeration Core regs */
++#define PCIH2D_MailBox  0x140
++#define PCIH2D_DB1		0x144
++#define PCID2H_MailBox  0x148
++#define PCIH2D_MailBox_1	0x150  /* for dma channel1 */
++#define PCIH2D_DB1_1		0x154
++#define PCID2H_MailBox_1	0x158
++#define PCIH2D_MailBox_2	0x160  /* for dma channel2 which will be used for Implicit DMA */
++#define PCIH2D_DB1_2		0x164
++#define PCID2H_MailBox_2	0x168
++
++#define PCIMailBoxInt	0x48
++#define PCIMailBoxMask	0x4C
++#define PCIMSIVecAssign	0x58
++
++#define I_F0_B0         (0x1 << 8) /* Mail box interrupt Function 0 interrupt, bit 0 */
++#define I_F0_B1         (0x1 << 9) /* Mail box interrupt Function 0 interrupt, bit 1 */
++
++#define PCIECFGREG_DEVCONTROL	0xB4
++#define PCIECFGREG_BASEADDR0	0x10
++#define PCIECFGREG_DEVCONTROL_MRRS_SHFT	12
++#define PCIECFGREG_DEVCONTROL_MRRS_MASK	(0x7 << PCIECFGREG_DEVCONTROL_MRRS_SHFT)
++#define PCIECFGREG_DEVCTRL_MPS_SHFT	5
++#define PCIECFGREG_DEVCTRL_MPS_MASK (0x7 << PCIECFGREG_DEVCTRL_MPS_SHFT)
++#define PCIECFGREG_PM_CSR_STATE_MASK 0x00000003
++#define PCIECFGREG_PM_CSR_STATE_D0 0
++#define PCIECFGREG_PM_CSR_STATE_D1 1
++#define PCIECFGREG_PM_CSR_STATE_D2 2
++#define PCIECFGREG_PM_CSR_STATE_D3_HOT 3
++#define PCIECFGREG_PM_CSR_STATE_D3_COLD 4
++
++
++/* SROM hardware region */
++#define SROM_OFFSET_BAR1_CTRL  52
++
++#define BAR1_ENC_SIZE_MASK	0x000e
++#define BAR1_ENC_SIZE_SHIFT	1
++
++#define BAR1_ENC_SIZE_1M	0
++#define BAR1_ENC_SIZE_2M	1
++#define BAR1_ENC_SIZE_4M	2
++
++#define PCIEGEN2_CAP_DEVSTSCTRL2_OFFSET		0xD4
++#define PCIEGEN2_CAP_DEVSTSCTRL2_LTRENAB	0x400
++
++/*
++ * Latency Tolerance Reporting (LTR) states
++ * Active has the least tolerant latency requirement
++ * Sleep is most tolerant
++ */
++#define LTR_ACTIVE				2
++#define LTR_ACTIVE_IDLE				1
++#define LTR_SLEEP				0
++#define LTR_FINAL_MASK				0x300
++#define LTR_FINAL_SHIFT				8
++
++/* pwrinstatus, pwrintmask regs */
++#define PCIEGEN2_PWRINT_D0_STATE_SHIFT		0
++#define PCIEGEN2_PWRINT_D1_STATE_SHIFT		1
++#define PCIEGEN2_PWRINT_D2_STATE_SHIFT		2
++#define PCIEGEN2_PWRINT_D3_STATE_SHIFT		3
++#define PCIEGEN2_PWRINT_L0_LINK_SHIFT		4
++#define PCIEGEN2_PWRINT_L0s_LINK_SHIFT		5
++#define PCIEGEN2_PWRINT_L1_LINK_SHIFT		6
++#define PCIEGEN2_PWRINT_L2_L3_LINK_SHIFT	7
++#define PCIEGEN2_PWRINT_OBFF_CHANGE_SHIFT	8
++
++#define PCIEGEN2_PWRINT_D0_STATE_MASK		(1 << PCIEGEN2_PWRINT_D0_STATE_SHIFT)
++#define PCIEGEN2_PWRINT_D1_STATE_MASK		(1 << PCIEGEN2_PWRINT_D1_STATE_SHIFT)
++#define PCIEGEN2_PWRINT_D2_STATE_MASK		(1 << PCIEGEN2_PWRINT_D2_STATE_SHIFT)
++#define PCIEGEN2_PWRINT_D3_STATE_MASK		(1 << PCIEGEN2_PWRINT_D3_STATE_SHIFT)
++#define PCIEGEN2_PWRINT_L0_LINK_MASK		(1 << PCIEGEN2_PWRINT_L0_LINK_SHIFT)
++#define PCIEGEN2_PWRINT_L0s_LINK_MASK		(1 << PCIEGEN2_PWRINT_L0s_LINK_SHIFT)
++#define PCIEGEN2_PWRINT_L1_LINK_MASK		(1 << PCIEGEN2_PWRINT_L1_LINK_SHIFT)
++#define PCIEGEN2_PWRINT_L2_L3_LINK_MASK		(1 << PCIEGEN2_PWRINT_L2_L3_LINK_SHIFT)
++#define PCIEGEN2_PWRINT_OBFF_CHANGE_MASK	(1 << PCIEGEN2_PWRINT_OBFF_CHANGE_SHIFT)
++
++/* sbtopcie mail box */
++#define SBTOPCIE_MB_FUNC0_SHIFT 8
++#define SBTOPCIE_MB_FUNC1_SHIFT 10
++#define SBTOPCIE_MB_FUNC2_SHIFT 12
++#define SBTOPCIE_MB_FUNC3_SHIFT 14
++
++#define SBTOPCIE_MB1_FUNC0_SHIFT 9
++#define SBTOPCIE_MB1_FUNC1_SHIFT 11
++#define SBTOPCIE_MB1_FUNC2_SHIFT 13
++#define SBTOPCIE_MB1_FUNC3_SHIFT 15
++
++/* pcieiocstatus */
++#define PCIEGEN2_IOC_D0_STATE_SHIFT		8
++#define PCIEGEN2_IOC_D1_STATE_SHIFT		9
++#define PCIEGEN2_IOC_D2_STATE_SHIFT		10
++#define PCIEGEN2_IOC_D3_STATE_SHIFT		11
++#define PCIEGEN2_IOC_L0_LINK_SHIFT		12
++#define PCIEGEN2_IOC_L1_LINK_SHIFT		13
++#define PCIEGEN2_IOC_L1L2_LINK_SHIFT		14
++#define PCIEGEN2_IOC_L2_L3_LINK_SHIFT		15
++
++#define PCIEGEN2_IOC_D0_STATE_MASK		(1 << PCIEGEN2_IOC_D0_STATE_SHIFT)
++#define PCIEGEN2_IOC_D1_STATE_MASK		(1 << PCIEGEN2_IOC_D1_STATE_SHIFT)
++#define PCIEGEN2_IOC_D2_STATE_MASK		(1 << PCIEGEN2_IOC_D2_STATE_SHIFT)
++#define PCIEGEN2_IOC_D3_STATE_MASK		(1 << PCIEGEN2_IOC_D3_STATE_SHIFT)
++#define PCIEGEN2_IOC_L0_LINK_MASK		(1 << PCIEGEN2_IOC_L0_LINK_SHIFT)
++#define PCIEGEN2_IOC_L1_LINK_MASK		(1 << PCIEGEN2_IOC_L1_LINK_SHIFT)
++#define PCIEGEN2_IOC_L1L2_LINK_MASK		(1 << PCIEGEN2_IOC_L1L2_LINK_SHIFT)
++#define PCIEGEN2_IOC_L2_L3_LINK_MASK		(1 << PCIEGEN2_IOC_L2_L3_LINK_SHIFT)
++
++/* stat_ctrl */
++#define PCIE_STAT_CTRL_RESET		0x1
++#define PCIE_STAT_CTRL_ENABLE		0x2
++#define PCIE_STAT_CTRL_INTENABLE	0x4
++#define PCIE_STAT_CTRL_INTSTATUS	0x8
++
++/* cpl_timeout_ctrl_reg */
++#define PCIE_CTO_TO_THRESHOLD_SHIFT	0
++#define PCIE_CTO_TO_THRESHHOLD_MASK	(0xfffff << PCIE_CTO_TO_THRESHOLD_SHIFT)
++
++#define PCIE_CTO_CLKCHKCNT_SHIFT		24
++#define PCIE_CTO_CLKCHKCNT_MASK		(0xf << PCIE_CTO_CLKCHKCNT_SHIFT)
++
++#define PCIE_CTO_ENAB_SHIFT			31
++#define PCIE_CTO_ENAB_MASK			(0x1 << PCIE_CTO_ENAB_SHIFT)
++
++#define PCIE_CTO_TO_THRESH_DEFAULT	0x58000
++#define PCIE_CTO_CLKCHKCNT_VAL		0xA
++
++/* ErrLog */
++#define PCIE_SROMRD_ERR_SHIFT			5
++#define PCIE_SROMRD_ERR_MASK			(0x1 << PCIE_SROMRD_ERR_SHIFT)
++
++#define PCIE_CTO_ERR_SHIFT			8
++#define PCIE_CTO_ERR_MASK				(0x1 << PCIE_CTO_ERR_SHIFT)
++
++#define PCIE_CTO_ERR_CODE_SHIFT		9
++#define PCIE_CTO_ERR_CODE_MASK		(0x3 << PCIE_CTO_ERR_CODE_SHIFT)
++
++#define PCIE_BP_CLK_OFF_ERR_SHIFT		12
++#define PCIE_BP_CLK_OFF_ERR_MASK		(0x1 << PCIE_BP_CLK_OFF_ERR_SHIFT)
++
++#define PCIE_BP_IN_RESET_ERR_SHIFT	13
++#define PCIE_BP_IN_RESET_ERR_MASK		(0x1 << PCIE_BP_IN_RESET_ERR_SHIFT)
++
++#ifdef BCMDRIVER
++void pcie_watchdog_reset(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs);
++void pcie_serdes_iddqdisable(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs);
++void pcie_set_trefup_time_100us(si_t *sih);
++#endif /* BCMDRIVER */
++
++/* DMA intstatus and intmask */
++#define	I_PC		(1 << 10)	/* pci descriptor error */
++#define	I_PD		(1 << 11)	/* pci data error */
++#define	I_DE		(1 << 12)	/* descriptor protocol error */
++#define	I_RU		(1 << 13)	/* receive descriptor underflow */
++#define	I_RO		(1 << 14)	/* receive fifo overflow */
++#define	I_XU		(1 << 15)	/* transmit fifo underflow */
++#define	I_RI		(1 << 16)	/* receive interrupt */
++#define	I_XI		(1 << 24)	/* transmit interrupt */
++
++#endif	/* _PCIE_CORE_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/rte_ioctl.h b/module_drivers/drivers/net/wireless/bcmdhd/include/rte_ioctl.h
+new file mode 100644
+index 000000000..f4c8c803c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/rte_ioctl.h
+@@ -0,0 +1,87 @@
++/*
++ * HND Run Time Environment ioctl.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: rte_ioctl.h 615249 2016-01-27 02:04:07Z $
++ */
++
++#ifndef _rte_ioctl_h_
++#define _rte_ioctl_h_
++
++/* RTE IOCTL definitions for generic ether devices */
++#define RTEGHWADDR		0x8901
++#define RTESHWADDR		0x8902
++#define RTEGMTU			0x8903
++#define RTEGSTATS		0x8904
++#define RTEGALLMULTI		0x8905
++#define RTESALLMULTI		0x8906
++#define RTEGPROMISC		0x8907
++#define RTESPROMISC		0x8908
++#define RTESMULTILIST	0x8909
++#define RTEGUP			0x890A
++#define RTEGPERMADDR		0x890B
++#define RTEDEVPWRSTCHG		0x890C	/* Device pwr state change for PCIedev */
++#define RTEDEVPMETOGGLE		0x890D	/* Toggle PME# to wake up the host */
++
++#define RTE_IOCTL_QUERY			0x00
++#define RTE_IOCTL_SET			0x01
++#define RTE_IOCTL_OVL_IDX_MASK	0x1e
++#define RTE_IOCTL_OVL_RSV		0x20
++#define RTE_IOCTL_OVL			0x40
++#define RTE_IOCTL_OVL_IDX_SHIFT	1
++
++enum hnd_ioctl_cmd {
++	HND_RTE_DNGL_IS_SS = 1, /* true if device connected at super speed */
++
++	/* PCIEDEV specific wl <--> bus ioctls */
++	BUS_GET_VAR = 2,
++	BUS_SET_VAR = 3,
++	BUS_FLUSH_RXREORDER_Q = 4,
++	BUS_SET_LTR_STATE = 5,
++	BUS_FLUSH_CHAINED_PKTS = 6,
++	BUS_SET_COPY_COUNT = 7,
++	BUS_UPDATE_FLOW_PKTS_MAX = 8,
++	BUS_UPDATE_EXTRA_TXLFRAGS = 9
++};
++
++#define SDPCMDEV_SET_MAXTXPKTGLOM	1
++
++typedef struct memuse_info {
++	uint16 ver;			/* version of this struct */
++	uint16 len;			/* length in bytes of this structure */
++	uint32 tot;			/* Total memory */
++	uint32 text_len;	/* Size of Text segment memory */
++	uint32 data_len;	/* Size of Data segment memory */
++	uint32 bss_len;		/* Size of BSS segment memory */
++
++	uint32 arena_size;	/* Total Heap size */
++	uint32 arena_free;	/* Heap memory available or free */
++	uint32 inuse_size;	/* Heap memory currently in use */
++	uint32 inuse_hwm;	/* High watermark of memory - reclaimed memory */
++	uint32 inuse_overhead;	/* tally of allocated mem_t blocks */
++	uint32 inuse_total;	/* Heap in-use + Heap overhead memory  */
++} memuse_info_t;
++
++#endif /* _rte_ioctl_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/sbchipc.h b/module_drivers/drivers/net/wireless/bcmdhd/include/sbchipc.h
+new file mode 100644
+index 000000000..cbc75b2f5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/sbchipc.h
+@@ -0,0 +1,4417 @@
++/*
++ * SiliconBackplane Chipcommon core hardware definitions.
++ *
++ * The chipcommon core provides chip identification, SB control,
++ * JTAG, 0/1/2 UARTs, clock frequency control, a watchdog interrupt timer,
++ * GPIO interface, extbus, and support for serial and parallel flashes.
++ *
++ * $Id: sbchipc.h 657872 2016-09-02 22:17:34Z $
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ */
++
++#ifndef	_SBCHIPC_H
++#define	_SBCHIPC_H
++
++#if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__)
++
++/* cpp contortions to concatenate w/arg prescan */
++#ifndef PAD
++#define	_PADLINE(line)	pad ## line
++#define	_XSTR(line)	_PADLINE(line)
++#define	PAD		_XSTR(__LINE__)
++#endif	/* PAD */
++
++/**
++ * In chipcommon rev 49 the pmu registers have been moved from chipc to the pmu core if the
++ * 'AOBPresent' bit of 'CoreCapabilitiesExt' is set. If this field is set, the traditional chipc to
++ * [pmu|gci|sreng] register interface is deprecated and removed. These register blocks would instead
++ * be assigned their respective chipc-specific address space and connected to the Always On
++ * Backplane via the APB interface.
++ */
++typedef volatile struct {
++	uint32  PAD[384];
++	uint32	pmucontrol;		/* 0x600 */
++	uint32	pmucapabilities; /* 0x604 */
++	uint32	pmustatus;	/* 0x608 */
++	uint32	res_state;	/* 0x60C */
++	uint32	res_pending;	/* 0x610 */
++	uint32	pmutimer;	/* 0x614 */
++	uint32	min_res_mask;	/* 0x618 */
++	uint32	max_res_mask;	/* 0x61C */
++	uint32	res_table_sel;	/* 0x620 */
++	uint32	res_dep_mask;
++	uint32	res_updn_timer;
++	uint32	res_timer;
++	uint32	clkstretch;
++	uint32	pmuwatchdog;
++	uint32	gpiosel;		/* 0x638, rev >= 1 */
++	uint32	gpioenable;		/* 0x63c, rev >= 1 */
++	uint32	res_req_timer_sel;	/* 0x640 */
++	uint32	res_req_timer;		/* 0x644 */
++	uint32	res_req_mask;		/* 0x648 */
++	uint32	core_cap_ext;		/* 0x64C */
++	uint32	chipcontrol_addr;	/* 0x650 */
++	uint32	chipcontrol_data;	/* 0x654 */
++	uint32	regcontrol_addr;
++	uint32	regcontrol_data;
++	uint32	pllcontrol_addr;
++	uint32	pllcontrol_data;
++	uint32	pmustrapopt;		/* 0x668, corerev >= 28 */
++	uint32	pmu_xtalfreq;		/* 0x66C, pmurev >= 10 */
++	uint32  retention_ctl;		/* 0x670 */
++	uint32	ILPPeriod;		/* 0x674 */
++	uint32  PAD[2];
++	uint32  retention_grpidx;	/* 0x680 */
++	uint32  retention_grpctl;	/* 0x684 */
++	uint32  mac_res_req_timer;	/* 0x688 */
++	uint32  mac_res_req_mask;	/* 0x68c */
++	uint32  PAD[18];
++	uint32	pmucontrol_ext;		/* 0x6d8 */
++	uint32	slowclkperiod;		/* 0x6dc */
++	uint32	PAD[8];
++	uint32	pmuintmask0;		/* 0x700 */
++	uint32	pmuintmask1;		/* 0x704 */
++	uint32  PAD[14];
++	uint32  pmuintstatus;		/* 0x740 */
++	uint32	extwakeupstatus;	/* 0x744 */
++	uint32  watchdog_res_mask;	/* 0x748 */
++	uint32	PAD[1];		/* 0x74C */
++	uint32	swscratch;		/* 0x750 */
++	uint32	PAD[3];		/* 0x754-0x75C */
++	uint32	extwakemask[2]; /* 0x760-0x764 */
++	uint32	PAD[2];		/* 0x768-0x76C */
++	uint32	extwakereqmask[2]; /* 0x770-0x774 */
++	uint32	PAD[2];		/* 0x778-0x77C */
++	uint32	pmuintctrl0;	/* 0x780 */
++	uint32	pmuintctrl1;	/* 0x784 */
++	uint32	PAD[2];
++	uint32	extwakectrl[2] ;   /* 0x790 */
++} pmuregs_t;
++
++typedef struct eci_prerev35 {
++	uint32	eci_output;
++	uint32	eci_control;
++	uint32	eci_inputlo;
++	uint32	eci_inputmi;
++	uint32	eci_inputhi;
++	uint32	eci_inputintpolaritylo;
++	uint32	eci_inputintpolaritymi;
++	uint32	eci_inputintpolarityhi;
++	uint32	eci_intmasklo;
++	uint32	eci_intmaskmi;
++	uint32	eci_intmaskhi;
++	uint32	eci_eventlo;
++	uint32	eci_eventmi;
++	uint32	eci_eventhi;
++	uint32	eci_eventmasklo;
++	uint32	eci_eventmaskmi;
++	uint32	eci_eventmaskhi;
++	uint32	PAD[3];
++} eci_prerev35_t;
++
++typedef struct eci_rev35 {
++	uint32	eci_outputlo;
++	uint32	eci_outputhi;
++	uint32	eci_controllo;
++	uint32	eci_controlhi;
++	uint32	eci_inputlo;
++	uint32	eci_inputhi;
++	uint32	eci_inputintpolaritylo;
++	uint32	eci_inputintpolarityhi;
++	uint32	eci_intmasklo;
++	uint32	eci_intmaskhi;
++	uint32	eci_eventlo;
++	uint32	eci_eventhi;
++	uint32	eci_eventmasklo;
++	uint32	eci_eventmaskhi;
++	uint32	eci_auxtx;
++	uint32	eci_auxrx;
++	uint32	eci_datatag;
++	uint32	eci_uartescvalue;
++	uint32	eci_autobaudctr;
++	uint32	eci_uartfifolevel;
++} eci_rev35_t;
++
++typedef struct flash_config {
++	uint32	PAD[19];
++	/* Flash struct configuration registers (0x18c) for BCM4706 (corerev = 31) */
++	uint32 flashstrconfig;
++} flash_config_t;
++
++typedef volatile struct {
++	uint32	chipid;			/* 0x0 */
++	uint32	capabilities;
++	uint32	corecontrol;		/* corerev >= 1 */
++	uint32	bist;
++
++	/* OTP */
++	uint32	otpstatus;		/* 0x10, corerev >= 10 */
++	uint32	otpcontrol;
++	uint32	otpprog;
++	uint32	otplayout;		/* corerev >= 23 */
++
++	/* Interrupt control */
++	uint32	intstatus;		/* 0x20 */
++	uint32	intmask;
++
++	/* Chip specific regs */
++	uint32	chipcontrol;		/* 0x28, rev >= 11 */
++	uint32	chipstatus;		/* 0x2c, rev >= 11 */
++
++	/* Jtag Master */
++	uint32	jtagcmd;		/* 0x30, rev >= 10 */
++	uint32	jtagir;
++	uint32	jtagdr;
++	uint32	jtagctrl;
++
++	/* serial flash interface registers */
++	uint32	flashcontrol;		/* 0x40 */
++	uint32	flashaddress;
++	uint32	flashdata;
++	uint32	otplayoutextension;	/* rev >= 35 */
++
++	/* Silicon backplane configuration broadcast control */
++	uint32	broadcastaddress;	/* 0x50 */
++	uint32	broadcastdata;
++
++	/* gpio - cleared only by power-on-reset */
++	uint32	gpiopullup;		/* 0x58, corerev >= 20 */
++	uint32	gpiopulldown;		/* 0x5c, corerev >= 20 */
++	uint32	gpioin;			/* 0x60 */
++	uint32	gpioout;		/* 0x64 */
++	uint32	gpioouten;		/* 0x68 */
++	uint32	gpiocontrol;		/* 0x6C */
++	uint32	gpiointpolarity;	/* 0x70 */
++	uint32	gpiointmask;		/* 0x74 */
++
++	/* GPIO events corerev >= 11 */
++	uint32	gpioevent;
++	uint32	gpioeventintmask;
++
++	/* Watchdog timer */
++	uint32	watchdog;		/* 0x80 */
++
++	/* GPIO events corerev >= 11 */
++	uint32	gpioeventintpolarity;
++
++	/* GPIO based LED powersave registers corerev >= 16 */
++	uint32  gpiotimerval;		/* 0x88 */
++	uint32  gpiotimeroutmask;
++
++	/* clock control */
++	uint32	clockcontrol_n;		/* 0x90 */
++	uint32	clockcontrol_sb;	/* aka m0 */
++	uint32	clockcontrol_pci;	/* aka m1 */
++	uint32	clockcontrol_m2;	/* mii/uart/mipsref */
++	uint32	clockcontrol_m3;	/* cpu */
++	uint32	clkdiv;			/* corerev >= 3 */
++	uint32	gpiodebugsel;		/* corerev >= 28 */
++	uint32	capabilities_ext;               	/* 0xac  */
++
++	/* pll delay registers (corerev >= 4) */
++	uint32	pll_on_delay;		/* 0xb0 */
++	uint32	fref_sel_delay;
++	uint32	slow_clk_ctl;		/* 5 < corerev < 10 */
++	uint32	PAD;
++
++	/* Instaclock registers (corerev >= 10) */
++	uint32	system_clk_ctl;		/* 0xc0 */
++	uint32	clkstatestretch;
++	uint32	PAD[2];
++
++	/* Indirect backplane access (corerev >= 22) */
++	uint32	bp_addrlow;		/* 0xd0 */
++	uint32	bp_addrhigh;
++	uint32	bp_data;
++	uint32	PAD;
++	uint32	bp_indaccess;
++	/* SPI registers, corerev >= 37 */
++	uint32	gsioctrl;
++	uint32	gsioaddress;
++	uint32	gsiodata;
++
++	/* More clock dividers (corerev >= 32) */
++	uint32	clkdiv2;
++	/* FAB ID (corerev >= 40) */
++	uint32	otpcontrol1;
++	uint32	fabid;			/* 0xf8 */
++
++	/* In AI chips, pointer to erom */
++	uint32	eromptr;		/* 0xfc */
++
++	/* ExtBus control registers (corerev >= 3) */
++	uint32	pcmcia_config;		/* 0x100 */
++	uint32	pcmcia_memwait;
++	uint32	pcmcia_attrwait;
++	uint32	pcmcia_iowait;
++	uint32	ide_config;
++	uint32	ide_memwait;
++	uint32	ide_attrwait;
++	uint32	ide_iowait;
++	uint32	prog_config;
++	uint32	prog_waitcount;
++	uint32	flash_config;
++	uint32	flash_waitcount;
++	uint32  SECI_config;		/* 0x130 SECI configuration */
++	uint32	SECI_status;
++	uint32	SECI_statusmask;
++	uint32	SECI_rxnibchanged;
++
++	uint32	PAD[20];
++
++	/* SROM interface (corerev >= 32) */
++	uint32	sromcontrol;		/* 0x190 */
++	uint32	sromaddress;
++	uint32	sromdata;
++	uint32	PAD[1];				/* 0x19C */
++	/* NAND flash registers for BCM4706 (corerev = 31) */
++	uint32  nflashctrl;         /* 0x1a0 */
++	uint32  nflashconf;
++	uint32  nflashcoladdr;
++	uint32  nflashrowaddr;
++	uint32  nflashdata;
++	uint32  nflashwaitcnt0;		/* 0x1b4 */
++	uint32  PAD[2];
++
++	uint32  seci_uart_data;		/* 0x1C0 */
++	uint32  seci_uart_bauddiv;
++	uint32  seci_uart_fcr;
++	uint32  seci_uart_lcr;
++	uint32  seci_uart_mcr;
++	uint32  seci_uart_lsr;
++	uint32  seci_uart_msr;
++	uint32  seci_uart_baudadj;
++	/* Clock control and hardware workarounds (corerev >= 20) */
++	uint32	clk_ctl_st;		/* 0x1e0 */
++	uint32	hw_war;
++	uint32  powerctl;		/* 0x1e8 */
++	uint32  PAD[69];
++
++	/* UARTs */
++	uint8	uart0data;		/* 0x300 */
++	uint8	uart0imr;
++	uint8	uart0fcr;
++	uint8	uart0lcr;
++	uint8	uart0mcr;
++	uint8	uart0lsr;
++	uint8	uart0msr;
++	uint8	uart0scratch;
++	uint8	PAD[248];		/* corerev >= 1 */
++
++	uint8	uart1data;		/* 0x400 */
++	uint8	uart1imr;
++	uint8	uart1fcr;
++	uint8	uart1lcr;
++	uint8	uart1mcr;
++	uint8	uart1lsr;
++	uint8	uart1msr;
++	uint8	uart1scratch;		/* 0x407 */
++	uint32	PAD[62];
++
++	/* save/restore, corerev >= 48 */
++	uint32	sr_capability;		/* 0x500 */
++	uint32	sr_control0;		/* 0x504 */
++	uint32	sr_control1;		/* 0x508 */
++	uint32  gpio_control;		/* 0x50C */
++	uint32	PAD[29];
++	/* 2 SR engines case */
++	uint32	sr1_control0;		/* 0x584 */
++	uint32	sr1_control1;		/* 0x588 */
++	uint32	PAD[29];
++	/* PMU registers (corerev >= 20) */
++	/* Note: all timers driven by ILP clock are updated asynchronously to HT/ALP.
++	 * The CPU must read them twice, compare, and retry if different.
++	 */
++	uint32	pmucontrol;		/* 0x600 */
++	uint32	pmucapabilities;
++	uint32	pmustatus;
++	uint32	res_state;
++	uint32	res_pending;
++	uint32	pmutimer;
++	uint32	min_res_mask;
++	uint32	max_res_mask;
++	uint32	res_table_sel;
++	uint32	res_dep_mask;
++	uint32	res_updn_timer;
++	uint32	res_timer;
++	uint32	clkstretch;
++	uint32	pmuwatchdog;
++	uint32	gpiosel;		/* 0x638, rev >= 1 */
++	uint32	gpioenable;		/* 0x63c, rev >= 1 */
++	uint32	res_req_timer_sel;
++	uint32	res_req_timer;
++	uint32	res_req_mask;
++	uint32	core_cap_ext;		/* 0x64c */
++	uint32	chipcontrol_addr;	/* 0x650 */
++	uint32	chipcontrol_data;	/* 0x654 */
++	uint32	regcontrol_addr;
++	uint32	regcontrol_data;
++	uint32	pllcontrol_addr;
++	uint32	pllcontrol_data;
++	uint32	pmustrapopt;		/* 0x668, corerev >= 28 */
++	uint32	pmu_xtalfreq;		/* 0x66C, pmurev >= 10 */
++	uint32  retention_ctl;		/* 0x670 */
++	uint32  PAD[3];
++	uint32  retention_grpidx;	/* 0x680 */
++	uint32  retention_grpctl;	/* 0x684 */
++	uint32  PAD[20];
++	uint32	pmucontrol_ext;		/* 0x6d8 */
++	uint32	slowclkperiod;		/* 0x6dc */
++	uint32	PAD[8];
++	uint32	pmuintmask0;		/* 0x700 */
++	uint32	pmuintmask1;		/* 0x704 */
++	uint32  PAD[14];
++	uint32  pmuintstatus;		/* 0x740 */
++	uint32	PAD[15];
++	uint32  pmuintctrl0;		/* 0x780 */
++	uint32  PAD[31];
++	uint16	sromotp[512];		/* 0x800 */
++#ifdef CCNFLASH_SUPPORT
++	/* Nand flash MLC controller registers (corerev >= 38) */
++	uint32	nand_revision;		/* 0xC00 */
++	uint32	nand_cmd_start;
++	uint32	nand_cmd_addr_x;
++	uint32	nand_cmd_addr;
++	uint32	nand_cmd_end_addr;
++	uint32	nand_cs_nand_select;
++	uint32	nand_cs_nand_xor;
++	uint32	PAD;
++	uint32	nand_spare_rd0;
++	uint32	nand_spare_rd4;
++	uint32	nand_spare_rd8;
++	uint32	nand_spare_rd12;
++	uint32	nand_spare_wr0;
++	uint32	nand_spare_wr4;
++	uint32	nand_spare_wr8;
++	uint32	nand_spare_wr12;
++	uint32	nand_acc_control;
++	uint32	PAD;
++	uint32	nand_config;
++	uint32	PAD;
++	uint32	nand_timing_1;
++	uint32	nand_timing_2;
++	uint32	nand_semaphore;
++	uint32	PAD;
++	uint32	nand_devid;
++	uint32	nand_devid_x;
++	uint32	nand_block_lock_status;
++	uint32	nand_intfc_status;
++	uint32	nand_ecc_corr_addr_x;
++	uint32	nand_ecc_corr_addr;
++	uint32	nand_ecc_unc_addr_x;
++	uint32	nand_ecc_unc_addr;
++	uint32	nand_read_error_count;
++	uint32	nand_corr_stat_threshold;
++	uint32	PAD[2];
++	uint32	nand_read_addr_x;
++	uint32	nand_read_addr;
++	uint32	nand_page_program_addr_x;
++	uint32	nand_page_program_addr;
++	uint32	nand_copy_back_addr_x;
++	uint32	nand_copy_back_addr;
++	uint32	nand_block_erase_addr_x;
++	uint32	nand_block_erase_addr;
++	uint32	nand_inv_read_addr_x;
++	uint32	nand_inv_read_addr;
++	uint32	PAD[2];
++	uint32	nand_blk_wr_protect;
++	uint32	PAD[3];
++	uint32	nand_acc_control_cs1;
++	uint32	nand_config_cs1;
++	uint32	nand_timing_1_cs1;
++	uint32	nand_timing_2_cs1;
++	uint32	PAD[20];
++	uint32	nand_spare_rd16;
++	uint32	nand_spare_rd20;
++	uint32	nand_spare_rd24;
++	uint32	nand_spare_rd28;
++	uint32	nand_cache_addr;
++	uint32	nand_cache_data;
++	uint32	nand_ctrl_config;
++	uint32	nand_ctrl_status;
++#endif /* CCNFLASH_SUPPORT */
++	uint32  gci_corecaps0; /* GCI starting at 0xC00 */
++	uint32  gci_corecaps1;
++	uint32  gci_corecaps2;
++	uint32  gci_corectrl;
++	uint32  gci_corestat; /* 0xC10 */
++	uint32  gci_intstat; /* 0xC14 */
++	uint32  gci_intmask; /* 0xC18 */
++	uint32  gci_wakemask; /* 0xC1C */
++	uint32  gci_levelintstat; /* 0xC20 */
++	uint32  gci_eventintstat; /* 0xC24 */
++	uint32  PAD[6];
++	uint32  gci_indirect_addr; /* 0xC40 */
++	uint32  gci_gpioctl; /* 0xC44 */
++	uint32	gci_gpiostatus;
++	uint32  gci_gpiomask; /* 0xC4C */
++	uint32  PAD;
++	uint32  gci_miscctl; /* 0xC54 */
++	uint32	gci_gpiointmask;
++	uint32	gci_gpiowakemask;
++	uint32  gci_input[32]; /* C60 */
++	uint32  gci_event[32]; /* CE0 */
++	uint32  gci_output[4]; /* D60 */
++	uint32  gci_control_0; /* 0xD70 */
++	uint32  gci_control_1; /* 0xD74 */
++	uint32  gci_intpolreg; /* 0xD78 */
++	uint32  gci_levelintmask; /* 0xD7C */
++	uint32  gci_eventintmask; /* 0xD80 */
++	uint32  PAD[3];
++	uint32  gci_inbandlevelintmask; /* 0xD90 */
++	uint32  gci_inbandeventintmask; /* 0xD94 */
++	uint32  PAD[2];
++	uint32  gci_seciauxtx; /* 0xDA0 */
++	uint32  gci_seciauxrx; /* 0xDA4 */
++	uint32  gci_secitx_datatag; /* 0xDA8 */
++	uint32  gci_secirx_datatag; /* 0xDAC */
++	uint32  gci_secitx_datamask; /* 0xDB0 */
++	uint32  gci_seciusef0tx_reg; /* 0xDB4 */
++	uint32  gci_secif0tx_offset; /* 0xDB8 */
++	uint32  gci_secif0rx_offset; /* 0xDBC */
++	uint32  gci_secif1tx_offset; /* 0xDC0 */
++	uint32	gci_rxfifo_common_ctrl; /* 0xDC4 */
++	uint32	gci_rxfifoctrl; /* 0xDC8 */
++	uint32	gci_uartreadid; /* DCC */
++	uint32  gci_seciuartescval; /* DD0 */
++	uint32	PAD;
++	uint32	gci_secififolevel; /* DD8 */
++	uint32	gci_seciuartdata; /* DDC */
++	uint32  gci_secibauddiv; /* DE0 */
++	uint32  gci_secifcr; /* DE4 */
++	uint32  gci_secilcr; /* DE8 */
++	uint32  gci_secimcr; /* DEC */
++	uint32	gci_secilsr; /* DF0 */
++	uint32	gci_secimsr; /* DF4 */
++	uint32  gci_baudadj; /* DF8 */
++	uint32  PAD;
++	uint32  gci_chipctrl; /* 0xE00 */
++	uint32  gci_chipsts; /* 0xE04 */
++	uint32	gci_gpioout; /* 0xE08 */
++	uint32	gci_gpioout_read; /* 0xE0C */
++	uint32	gci_mpwaketx; /* 0xE10 */
++	uint32	gci_mpwakedetect; /* 0xE14 */
++	uint32	gci_seciin_ctrl; /* 0xE18 */
++	uint32	gci_seciout_ctrl; /* 0xE1C */
++	uint32	gci_seciin_auxfifo_en; /* 0xE20 */
++	uint32	gci_seciout_txen_txbr; /* 0xE24 */
++	uint32	gci_seciin_rxbrstatus; /* 0xE28 */
++	uint32	gci_seciin_rxerrstatus; /* 0xE2C */
++	uint32	gci_seciin_fcstatus; /* 0xE30 */
++	uint32	gci_seciout_txstatus; /* 0xE34 */
++	uint32	gci_seciout_txbrstatus; /* 0xE38 */
++} chipcregs_t;
++
++#endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */
++
++
++#define	CC_CHIPID		0
++#define	CC_CAPABILITIES		4
++#define	CC_CHIPST		0x2c
++#define	CC_EROMPTR		0xfc
++
++#define	CC_OTPST		0x10
++#define	CC_INTSTATUS		0x20
++#define	CC_INTMASK		0x24
++#define	CC_JTAGCMD		0x30
++#define	CC_JTAGIR		0x34
++#define	CC_JTAGDR		0x38
++#define	CC_JTAGCTRL		0x3c
++#define	CC_GPIOPU		0x58
++#define	CC_GPIOPD		0x5c
++#define	CC_GPIOIN		0x60
++#define	CC_GPIOOUT		0x64
++#define	CC_GPIOOUTEN		0x68
++#define	CC_GPIOCTRL		0x6c
++#define	CC_GPIOPOL		0x70
++#define	CC_GPIOINTM		0x74
++#define	CC_GPIOEVENT		0x78
++#define	CC_GPIOEVENTMASK	0x7c
++#define	CC_WATCHDOG		0x80
++#define	CC_GPIOEVENTPOL		0x84
++#define	CC_CLKC_N		0x90
++#define	CC_CLKC_M0		0x94
++#define	CC_CLKC_M1		0x98
++#define	CC_CLKC_M2		0x9c
++#define	CC_CLKC_M3		0xa0
++#define	CC_CLKDIV		0xa4
++#define	CC_CAP_EXT		0xac
++#define	CC_SYS_CLK_CTL		0xc0
++#define	CC_CLKDIV2		0xf0
++#define	CC_CLK_CTL_ST		SI_CLK_CTL_ST
++#define	PMU_CTL			0x600
++#define	PMU_CAP			0x604
++#define	PMU_ST			0x608
++#define PMU_RES_STATE		0x60c
++#define PMU_RES_PENDING		0x610
++#define PMU_TIMER		0x614
++#define	PMU_MIN_RES_MASK	0x618
++#define	PMU_MAX_RES_MASK	0x61c
++#define CC_CHIPCTL_ADDR         0x650
++#define CC_CHIPCTL_DATA         0x654
++#define PMU_REG_CONTROL_ADDR	0x658
++#define PMU_REG_CONTROL_DATA	0x65C
++#define PMU_PLL_CONTROL_ADDR	0x660
++#define PMU_PLL_CONTROL_DATA	0x664
++
++#define CC_SROM_CTRL		0x190
++#ifdef SROM16K_4364_ADDRSPACE
++#define	CC_SROM_OTP		0xa000		/* SROM/OTP address space */
++#else
++#define	CC_SROM_OTP		0x0800
++#endif
++#define CC_GCI_INDIRECT_ADDR_REG	0xC40
++#define CC_GCI_CHIP_CTRL_REG	0xE00
++#define CC_GCI_CC_OFFSET_2	2
++#define CC_GCI_CC_OFFSET_5	5
++#define CC_SWD_CTRL		0x380
++#define CC_SWD_REQACK		0x384
++#define CC_SWD_DATA		0x388
++
++#define CHIPCTRLREG0 0x0
++#define CHIPCTRLREG1 0x1
++#define CHIPCTRLREG2 0x2
++#define CHIPCTRLREG3 0x3
++#define CHIPCTRLREG4 0x4
++#define CHIPCTRLREG5 0x5
++#define CHIPCTRLREG6 0x6
++#define REGCTRLREG4 0x4
++#define REGCTRLREG5 0x5
++#define REGCTRLREG6 0x6
++#define MINRESMASKREG 0x618
++#define MAXRESMASKREG 0x61c
++#define CHIPCTRLADDR 0x650
++#define CHIPCTRLDATA 0x654
++#define RSRCTABLEADDR 0x620
++#define PMU_RES_DEP_MASK 0x624
++#define RSRCUPDWNTIME 0x628
++#define PMUREG_RESREQ_MASK 0x68c
++#define PMUREG_RESREQ_TIMER 0x688
++#define PMUREG_RESREQ_MASK1 0x6f4
++#define PMUREG_RESREQ_TIMER1 0x6f0
++#define EXT_LPO_AVAIL 0x100
++#define LPO_SEL					(1 << 0)
++#define CC_EXT_LPO_PU 0x200000
++#define GC_EXT_LPO_PU 0x2
++#define CC_INT_LPO_PU 0x100000
++#define GC_INT_LPO_PU 0x1
++#define EXT_LPO_SEL 0x8
++#define INT_LPO_SEL 0x4
++#define ENABLE_FINE_CBUCK_CTRL 			(1 << 30)
++#define REGCTRL5_PWM_AUTO_CTRL_MASK 		0x007e0000
++#define REGCTRL5_PWM_AUTO_CTRL_SHIFT		17
++#define REGCTRL6_PWM_AUTO_CTRL_MASK 		0x3fff0000
++#define REGCTRL6_PWM_AUTO_CTRL_SHIFT		16
++#define CC_BP_IND_ACCESS_START_SHIFT		9
++#define CC_BP_IND_ACCESS_START_MASK		(1 << CC_BP_IND_ACCESS_START_SHIFT)
++#define CC_BP_IND_ACCESS_RDWR_SHIFT		8
++#define CC_BP_IND_ACCESS_RDWR_MASK		(1 << CC_BP_IND_ACCESS_RDWR_SHIFT)
++#define CC_BP_IND_ACCESS_ERROR_SHIFT		10
++#define CC_BP_IND_ACCESS_ERROR_MASK		(1 << CC_BP_IND_ACCESS_ERROR_SHIFT)
++
++#ifdef SR_DEBUG
++#define SUBCORE_POWER_ON 0x0001
++#define PHY_POWER_ON 0x0010
++#define VDDM_POWER_ON 0x0100
++#define MEMLPLDO_POWER_ON 0x1000
++#define SUBCORE_POWER_ON_CHK 0x00040000
++#define PHY_POWER_ON_CHK 0x00080000
++#define VDDM_POWER_ON_CHK 0x00100000
++#define MEMLPLDO_POWER_ON_CHK 0x00200000
++#endif /* SR_DEBUG */
++
++#ifdef CCNFLASH_SUPPORT
++/* NAND flash support */
++#define CC_NAND_REVISION	0xC00
++#define CC_NAND_CMD_START	0xC04
++#define CC_NAND_CMD_ADDR	0xC0C
++#define CC_NAND_SPARE_RD_0	0xC20
++#define CC_NAND_SPARE_RD_4	0xC24
++#define CC_NAND_SPARE_RD_8	0xC28
++#define CC_NAND_SPARE_RD_C	0xC2C
++#define CC_NAND_CONFIG		0xC48
++#define CC_NAND_DEVID		0xC60
++#define CC_NAND_DEVID_EXT	0xC64
++#define CC_NAND_INTFC_STATUS	0xC6C
++#endif /* CCNFLASH_SUPPORT */
++
++/* chipid */
++#define	CID_ID_MASK		0x0000ffff	/**< Chip Id mask */
++#define	CID_REV_MASK		0x000f0000	/**< Chip Revision mask */
++#define	CID_REV_SHIFT		16		/**< Chip Revision shift */
++#define	CID_PKG_MASK		0x00f00000	/**< Package Option mask */
++#define	CID_PKG_SHIFT		20		/**< Package Option shift */
++#define	CID_CC_MASK		0x0f000000	/**< CoreCount (corerev >= 4) */
++#define CID_CC_SHIFT		24
++#define	CID_TYPE_MASK		0xf0000000	/**< Chip Type */
++#define CID_TYPE_SHIFT		28
++
++/* capabilities */
++#define	CC_CAP_UARTS_MASK	0x00000003	/**< Number of UARTs */
++#define CC_CAP_MIPSEB		0x00000004	/**< MIPS is in big-endian mode */
++#define CC_CAP_UCLKSEL		0x00000018	/**< UARTs clock select */
++#define CC_CAP_UINTCLK		0x00000008	/**< UARTs are driven by internal divided clock */
++#define CC_CAP_UARTGPIO		0x00000020	/**< UARTs own GPIOs 15:12 */
++#define CC_CAP_EXTBUS_MASK	0x000000c0	/**< External bus mask */
++#define CC_CAP_EXTBUS_NONE	0x00000000	/**< No ExtBus present */
++#define CC_CAP_EXTBUS_FULL	0x00000040	/**< ExtBus: PCMCIA, IDE & Prog */
++#define CC_CAP_EXTBUS_PROG	0x00000080	/**< ExtBus: ProgIf only */
++#define	CC_CAP_FLASH_MASK	0x00000700	/**< Type of flash */
++#define	CC_CAP_PLL_MASK		0x00038000	/**< Type of PLL */
++#define CC_CAP_PWR_CTL		0x00040000	/**< Power control */
++#define CC_CAP_OTPSIZE		0x00380000	/**< OTP Size (0 = none) */
++#define CC_CAP_OTPSIZE_SHIFT	19		/**< OTP Size shift */
++#define CC_CAP_OTPSIZE_BASE	5		/**< OTP Size base */
++#define CC_CAP_JTAGP		0x00400000	/**< JTAG Master Present */
++#define CC_CAP_ROM		0x00800000	/**< Internal boot rom active */
++#define CC_CAP_BKPLN64		0x08000000	/**< 64-bit backplane */
++#define	CC_CAP_PMU		0x10000000	/**< PMU Present, rev >= 20 */
++#define	CC_CAP_ECI		0x20000000	/**< ECI Present, rev >= 21 */
++#define	CC_CAP_SROM		0x40000000	/**< Srom Present, rev >= 32 */
++#define	CC_CAP_NFLASH		0x80000000	/**< Nand flash present, rev >= 35 */
++
++#define	CC_CAP2_SECI		0x00000001	/**< SECI Present, rev >= 36 */
++#define	CC_CAP2_GSIO		0x00000002	/**< GSIO (spi/i2c) present, rev >= 37 */
++
++/* capabilities extension */
++#define CC_CAP_EXT_SECI_PRESENT				0x00000001	/**< SECI present */
++#define CC_CAP_EXT_GSIO_PRESENT				0x00000002	/**< GSIO present */
++#define CC_CAP_EXT_GCI_PRESENT  			0x00000004	/**< GCI present */
++#define CC_CAP_EXT_SECI_PUART_PRESENT		0x00000008  /**< UART present */
++#define CC_CAP_EXT_AOB_PRESENT  			0x00000040	/**< AOB present */
++#define CC_CAP_EXT_SWD_PRESENT  			0x00000400	/**< SWD present */
++
++/* WL Channel Info to BT via GCI - bits 40 - 47 */
++#define GCI_WL_CHN_INFO_MASK	(0xFF00)
++/* WL indication of MCHAN enabled/disabled to BT in awdl mode- bit 36 */
++#define GCI_WL_MCHAN_BIT_MASK	(0x0010)
++/* WL Strobe to BT */
++#define GCI_WL_STROBE_BIT_MASK	(0x0020)
++/* bits [51:48] - reserved for wlan TX pwr index */
++/* bits [55:52] btc mode indication */
++#define GCI_WL_BTC_MODE_SHIFT	(20)
++#define GCI_WL_BTC_MODE_MASK	(0xF << GCI_WL_BTC_MODE_SHIFT)
++#define GCI_WL_ANT_BIT_MASK	(0x00c0)
++#define GCI_WL_ANT_SHIFT_BITS	(6)
++/* PLL type */
++#define PLL_NONE		0x00000000
++#define PLL_TYPE1		0x00010000	/**< 48MHz base, 3 dividers */
++#define PLL_TYPE2		0x00020000	/**< 48MHz, 4 dividers */
++#define PLL_TYPE3		0x00030000	/**< 25MHz, 2 dividers */
++#define PLL_TYPE4		0x00008000	/**< 48MHz, 4 dividers */
++#define PLL_TYPE5		0x00018000	/**< 25MHz, 4 dividers */
++#define PLL_TYPE6		0x00028000	/**< 100/200 or 120/240 only */
++#define PLL_TYPE7		0x00038000	/**< 25MHz, 4 dividers */
++
++/* ILP clock */
++#define	ILP_CLOCK		32000
++
++/* ALP clock on pre-PMU chips */
++#define	ALP_CLOCK		20000000
++
++#ifdef CFG_SIM
++#define NS_ALP_CLOCK		84922
++#define NS_SLOW_ALP_CLOCK	84922
++#define NS_CPU_CLOCK		534500
++#define NS_SLOW_CPU_CLOCK	534500
++#define NS_SI_CLOCK		271750
++#define NS_SLOW_SI_CLOCK	271750
++#define NS_FAST_MEM_CLOCK	271750
++#define NS_MEM_CLOCK		271750
++#define NS_SLOW_MEM_CLOCK	271750
++#else
++#define NS_ALP_CLOCK		125000000
++#define NS_SLOW_ALP_CLOCK	100000000
++#define NS_CPU_CLOCK		1000000000
++#define NS_SLOW_CPU_CLOCK	800000000
++#define NS_SI_CLOCK		250000000
++#define NS_SLOW_SI_CLOCK	200000000
++#define NS_FAST_MEM_CLOCK	800000000
++#define NS_MEM_CLOCK		533000000
++#define NS_SLOW_MEM_CLOCK	400000000
++#endif /* CFG_SIM */
++
++#define ALP_CLOCK_53573		40000000
++
++/* HT clock */
++#define	HT_CLOCK		80000000
++
++/* corecontrol */
++#define CC_UARTCLKO		0x00000001	/**< Drive UART with internal clock */
++#define	CC_SE			0x00000002	/**< sync clk out enable (corerev >= 3) */
++#define CC_ASYNCGPIO	0x00000004	/**< 1=generate GPIO interrupt without backplane clock */
++#define CC_UARTCLKEN		0x00000008	/**< enable UART Clock (corerev > = 21 */
++
++/* retention_ctl */
++#define RCTL_MEM_RET_SLEEP_LOG_SHIFT	29
++#define RCTL_MEM_RET_SLEEP_LOG_MASK	(1 << RCTL_MEM_RET_SLEEP_LOG_SHIFT)
++
++/* 4321 chipcontrol */
++#define CHIPCTRL_4321A0_DEFAULT	0x3a4
++#define CHIPCTRL_4321A1_DEFAULT	0x0a4
++#define CHIPCTRL_4321_PLL_DOWN	0x800000	/**< serdes PLL down override */
++
++/* Fields in the otpstatus register in rev >= 21 */
++#define OTPS_OL_MASK		0x000000ff
++#define OTPS_OL_MFG		0x00000001	/**< manuf row is locked */
++#define OTPS_OL_OR1		0x00000002	/**< otp redundancy row 1 is locked */
++#define OTPS_OL_OR2		0x00000004	/**< otp redundancy row 2 is locked */
++#define OTPS_OL_GU		0x00000008	/**< general use region is locked */
++#define OTPS_GUP_MASK		0x00000f00
++#define OTPS_GUP_SHIFT		8
++#define OTPS_GUP_HW		0x00000100	/**< h/w subregion is programmed */
++#define OTPS_GUP_SW		0x00000200	/**< s/w subregion is programmed */
++#define OTPS_GUP_CI		0x00000400	/**< chipid/pkgopt subregion is programmed */
++#define OTPS_GUP_FUSE		0x00000800	/**< fuse subregion is programmed */
++#define OTPS_READY		0x00001000
++#define OTPS_RV(x)		(1 << (16 + (x)))	/**< redundancy entry valid */
++#define OTPS_RV_MASK		0x0fff0000
++#define OTPS_PROGOK     0x40000000
++
++/* Fields in the otpcontrol register in rev >= 21 */
++#define OTPC_PROGSEL		0x00000001
++#define OTPC_PCOUNT_MASK	0x0000000e
++#define OTPC_PCOUNT_SHIFT	1
++#define OTPC_VSEL_MASK		0x000000f0
++#define OTPC_VSEL_SHIFT		4
++#define OTPC_TMM_MASK		0x00000700
++#define OTPC_TMM_SHIFT		8
++#define OTPC_ODM		0x00000800
++#define OTPC_PROGEN		0x80000000
++
++/* Fields in the 40nm otpcontrol register in rev >= 40 */
++#define OTPC_40NM_PROGSEL_SHIFT	0
++#define OTPC_40NM_PCOUNT_SHIFT	1
++#define OTPC_40NM_PCOUNT_WR	0xA
++#define OTPC_40NM_PCOUNT_V1X	0xB
++#define OTPC_40NM_REGCSEL_SHIFT	5
++#define OTPC_40NM_REGCSEL_DEF	0x4
++#define OTPC_40NM_PROGIN_SHIFT	8
++#define OTPC_40NM_R2X_SHIFT	10
++#define OTPC_40NM_ODM_SHIFT	11
++#define OTPC_40NM_DF_SHIFT	15
++#define OTPC_40NM_VSEL_SHIFT	16
++#define OTPC_40NM_VSEL_WR	0xA
++#define OTPC_40NM_VSEL_V1X	0xA
++#define OTPC_40NM_VSEL_R1X	0x5
++#define OTPC_40NM_COFAIL_SHIFT	30
++
++#define OTPC1_CPCSEL_SHIFT	0
++#define OTPC1_CPCSEL_DEF	6
++#define OTPC1_TM_SHIFT		8
++#define OTPC1_TM_WR		0x84
++#define OTPC1_TM_V1X		0x84
++#define OTPC1_TM_R1X		0x4
++#define OTPC1_CLK_EN_MASK	0x00020000
++#define OTPC1_CLK_DIV_MASK	0x00FC0000
++
++/* Fields in otpprog in rev >= 21 and HND OTP */
++#define OTPP_COL_MASK		0x000000ff
++#define OTPP_COL_SHIFT		0
++#define OTPP_ROW_MASK		0x0000ff00
++#define OTPP_ROW_MASK9		0x0001ff00		/* for ccrev >= 49 */
++#define OTPP_ROW_SHIFT		8
++#define OTPP_OC_MASK		0x0f000000
++#define OTPP_OC_SHIFT		24
++#define OTPP_READERR		0x10000000
++#define OTPP_VALUE_MASK		0x20000000
++#define OTPP_VALUE_SHIFT	29
++#define OTPP_START_BUSY		0x80000000
++#define	OTPP_READ		0x40000000	/* HND OTP */
++
++/* Fields in otplayout register */
++#define OTPL_HWRGN_OFF_MASK	0x00000FFF
++#define OTPL_HWRGN_OFF_SHIFT	0
++#define OTPL_WRAP_REVID_MASK	0x00F80000
++#define OTPL_WRAP_REVID_SHIFT	19
++#define OTPL_WRAP_TYPE_MASK	0x00070000
++#define OTPL_WRAP_TYPE_SHIFT	16
++#define OTPL_WRAP_TYPE_65NM	0
++#define OTPL_WRAP_TYPE_40NM	1
++#define OTPL_WRAP_TYPE_28NM	2
++#define OTPL_ROW_SIZE_MASK	0x0000F000
++#define OTPL_ROW_SIZE_SHIFT	12
++
++/* otplayout reg corerev >= 36 */
++#define OTP_CISFORMAT_NEW	0x80000000
++
++/* Opcodes for OTPP_OC field */
++#define OTPPOC_READ		0
++#define OTPPOC_BIT_PROG		1
++#define OTPPOC_VERIFY		3
++#define OTPPOC_INIT		4
++#define OTPPOC_SET		5
++#define OTPPOC_RESET		6
++#define OTPPOC_OCST		7
++#define OTPPOC_ROW_LOCK		8
++#define OTPPOC_PRESCN_TEST	9
++
++/* Opcodes for OTPP_OC field (40NM) */
++#define OTPPOC_READ_40NM	0
++#define OTPPOC_PROG_ENABLE_40NM 1
++#define OTPPOC_PROG_DISABLE_40NM	2
++#define OTPPOC_VERIFY_40NM	3
++#define OTPPOC_WORD_VERIFY_1_40NM	4
++#define OTPPOC_ROW_LOCK_40NM	5
++#define OTPPOC_STBY_40NM	6
++#define OTPPOC_WAKEUP_40NM	7
++#define OTPPOC_WORD_VERIFY_0_40NM	8
++#define OTPPOC_PRESCN_TEST_40NM 9
++#define OTPPOC_BIT_PROG_40NM	10
++#define OTPPOC_WORDPROG_40NM	11
++#define OTPPOC_BURNIN_40NM	12
++#define OTPPOC_AUTORELOAD_40NM	13
++#define OTPPOC_OVST_READ_40NM	14
++#define OTPPOC_OVST_PROG_40NM	15
++
++/* Opcodes for OTPP_OC field (28NM) */
++#define OTPPOC_READ_28NM	0
++#define OTPPOC_READBURST_28NM	1
++#define OTPPOC_PROG_ENABLE_28NM 2
++#define OTPPOC_PROG_DISABLE_28NM	3
++#define OTPPOC_PRESCREEN_28NM	4
++#define OTPPOC_PRESCREEN_RP_28NM	5
++#define OTPPOC_FLUSH_28NM	6
++#define OTPPOC_NOP_28NM	7
++#define OTPPOC_PROG_ECC_28NM	8
++#define OTPPOC_PROG_ECC_READ_28NM	9
++#define OTPPOC_PROG_28NM	10
++#define OTPPOC_PROGRAM_RP_28NM	11
++#define OTPPOC_PROGRAM_OVST_28NM	12
++#define OTPPOC_RELOAD_28NM	13
++#define OTPPOC_ERASE_28NM	14
++#define OTPPOC_LOAD_RF_28NM	15
++#define OTPPOC_CTRL_WR_28NM 16
++#define OTPPOC_CTRL_RD_28NM	17
++#define OTPPOC_READ_HP_28NM	18
++#define OTPPOC_READ_OVST_28NM	19
++#define OTPPOC_READ_VERIFY0_28NM	20
++#define OTPPOC_READ_VERIFY1_28NM	21
++#define OTPPOC_READ_FORCE0_28NM	22
++#define OTPPOC_READ_FORCE1_28NM	23
++#define OTPPOC_BURNIN_28NM	24
++#define OTPPOC_PROGRAM_LOCK_28NM	25
++#define OTPPOC_PROGRAM_TESTCOL_28NM	26
++#define OTPPOC_READ_TESTCOL_28NM	27
++#define OTPPOC_READ_FOUT_28NM	28
++#define OTPPOC_SFT_RESET_28NM	29
++
++#define OTPP_OC_MASK_28NM		0x0f800000
++#define OTPP_OC_SHIFT_28NM		23
++#define OTPC_PROGEN_28NM		0x8
++#define OTPC_DBLERRCLR		0x20
++#define OTPC_CLK_EN_MASK	0x00000040
++#define OTPC_CLK_DIV_MASK	0x00000F80
++
++/* Fields in otplayoutextension */
++#define OTPLAYOUTEXT_FUSE_MASK	0x3FF
++
++
++/* Jtagm characteristics that appeared at a given corerev */
++#define	JTAGM_CREV_OLD		10	/**< Old command set, 16bit max IR */
++#define	JTAGM_CREV_IRP		22	/**< Able to do pause-ir */
++#define	JTAGM_CREV_RTI		28	/**< Able to do return-to-idle */
++
++/* jtagcmd */
++#define JCMD_START		0x80000000
++#define JCMD_BUSY		0x80000000
++#define JCMD_STATE_MASK		0x60000000
++#define JCMD_STATE_TLR		0x00000000	/**< Test-logic-reset */
++#define JCMD_STATE_PIR		0x20000000	/**< Pause IR */
++#define JCMD_STATE_PDR		0x40000000	/**< Pause DR */
++#define JCMD_STATE_RTI		0x60000000	/**< Run-test-idle */
++#define JCMD0_ACC_MASK		0x0000f000
++#define JCMD0_ACC_IRDR		0x00000000
++#define JCMD0_ACC_DR		0x00001000
++#define JCMD0_ACC_IR		0x00002000
++#define JCMD0_ACC_RESET		0x00003000
++#define JCMD0_ACC_IRPDR		0x00004000
++#define JCMD0_ACC_PDR		0x00005000
++#define JCMD0_IRW_MASK		0x00000f00
++#define JCMD_ACC_MASK		0x000f0000	/**< Changes for corerev 11 */
++#define JCMD_ACC_IRDR		0x00000000
++#define JCMD_ACC_DR		0x00010000
++#define JCMD_ACC_IR		0x00020000
++#define JCMD_ACC_RESET		0x00030000
++#define JCMD_ACC_IRPDR		0x00040000
++#define JCMD_ACC_PDR		0x00050000
++#define JCMD_ACC_PIR		0x00060000
++#define JCMD_ACC_IRDR_I		0x00070000	/**< rev 28: return to run-test-idle */
++#define JCMD_ACC_DR_I		0x00080000	/**< rev 28: return to run-test-idle */
++#define JCMD_IRW_MASK		0x00001f00
++#define JCMD_IRW_SHIFT		8
++#define JCMD_DRW_MASK		0x0000003f
++
++/* jtagctrl */
++#define JCTRL_FORCE_CLK		4		/**< Force clock */
++#define JCTRL_EXT_EN		2		/**< Enable external targets */
++#define JCTRL_EN		1		/**< Enable Jtag master */
++#define JCTRL_TAPSEL_BIT	0x00000008	/**< JtagMasterCtrl tap_sel bit */
++
++/* swdmasterctrl */
++#define SWDCTRL_INT_EN		8		/**< Enable internal targets */
++#define SWDCTRL_FORCE_CLK	4		/**< Force clock */
++#define SWDCTRL_OVJTAG		2		/**< Enable shared SWD/JTAG pins */
++#define SWDCTRL_EN		1		/**< Enable Jtag master */
++
++/* Fields in clkdiv */
++#define	CLKD_SFLASH		0x1f000000
++#define	CLKD_SFLASH_SHIFT	24
++#define	CLKD_OTP		0x000f0000
++#define	CLKD_OTP_SHIFT		16
++#define	CLKD_JTAG		0x00000f00
++#define	CLKD_JTAG_SHIFT		8
++#define	CLKD_UART		0x000000ff
++
++#define	CLKD2_SROM		0x00000003
++#define	CLKD2_SWD		0xf8000000
++#define	CLKD2_SWD_SHIFT		27
++
++/* intstatus/intmask */
++#define	CI_GPIO			0x00000001	/**< gpio intr */
++#define	CI_EI			0x00000002	/**< extif intr (corerev >= 3) */
++#define	CI_TEMP			0x00000004	/**< temp. ctrl intr (corerev >= 15) */
++#define	CI_SIRQ			0x00000008	/**< serial IRQ intr (corerev >= 15) */
++#define	CI_ECI			0x00000010	/**< eci intr (corerev >= 21) */
++#define	CI_PMU			0x00000020	/**< pmu intr (corerev >= 21) */
++#define	CI_UART			0x00000040	/**< uart intr (corerev >= 21) */
++#define	CI_WDRESET		0x80000000	/**< watchdog reset occurred */
++
++/* slow_clk_ctl */
++#define SCC_SS_MASK		0x00000007	/**< slow clock source mask */
++#define	SCC_SS_LPO		0x00000000	/**< source of slow clock is LPO */
++#define	SCC_SS_XTAL		0x00000001	/**< source of slow clock is crystal */
++#define	SCC_SS_PCI		0x00000002	/**< source of slow clock is PCI */
++#define SCC_LF			0x00000200	/**< LPOFreqSel, 1: 160Khz, 0: 32KHz */
++#define SCC_LP			0x00000400	/**< LPOPowerDown, 1: LPO is disabled,
++						 * 0: LPO is enabled
++						 */
++#define SCC_FS			0x00000800 /**< ForceSlowClk, 1: sb/cores running on slow clock,
++						 * 0: power logic control
++						 */
++#define SCC_IP			0x00001000 /**< IgnorePllOffReq, 1/0: power logic ignores/honors
++						 * PLL clock disable requests from core
++						 */
++#define SCC_XC			0x00002000	/**< XtalControlEn, 1/0: power logic does/doesn't
++						 * disable crystal when appropriate
++						 */
++#define SCC_XP			0x00004000	/**< XtalPU (RO), 1/0: crystal running/disabled */
++#define SCC_CD_MASK		0xffff0000	/**< ClockDivider (SlowClk = 1/(4+divisor)) */
++#define SCC_CD_SHIFT		16
++
++/* system_clk_ctl */
++#define	SYCC_IE			0x00000001	/**< ILPen: Enable Idle Low Power */
++#define	SYCC_AE			0x00000002	/**< ALPen: Enable Active Low Power */
++#define	SYCC_FP			0x00000004	/**< ForcePLLOn */
++#define	SYCC_AR			0x00000008	/**< Force ALP (or HT if ALPen is not set */
++#define	SYCC_HR			0x00000010	/**< Force HT */
++#define SYCC_CD_MASK		0xffff0000	/**< ClkDiv  (ILP = 1/(4 * (divisor + 1)) */
++#define SYCC_CD_SHIFT		16
++
++/* Indirect backplane access */
++#define	BPIA_BYTEEN		0x0000000f
++#define	BPIA_SZ1		0x00000001
++#define	BPIA_SZ2		0x00000003
++#define	BPIA_SZ4		0x00000007
++#define	BPIA_SZ8		0x0000000f
++#define	BPIA_WRITE		0x00000100
++#define	BPIA_START		0x00000200
++#define	BPIA_BUSY		0x00000200
++#define	BPIA_ERROR		0x00000400
++
++/* pcmcia/prog/flash_config */
++#define	CF_EN			0x00000001	/**< enable */
++#define	CF_EM_MASK		0x0000000e	/**< mode */
++#define	CF_EM_SHIFT		1
++#define	CF_EM_FLASH		0		/**< flash/asynchronous mode */
++#define	CF_EM_SYNC		2		/**< synchronous mode */
++#define	CF_EM_PCMCIA		4		/**< pcmcia mode */
++#define	CF_DS			0x00000010	/**< destsize:  0=8bit, 1=16bit */
++#define	CF_BS			0x00000020	/**< byteswap */
++#define	CF_CD_MASK		0x000000c0	/**< clock divider */
++#define	CF_CD_SHIFT		6
++#define	CF_CD_DIV2		0x00000000	/**< backplane/2 */
++#define	CF_CD_DIV3		0x00000040	/**< backplane/3 */
++#define	CF_CD_DIV4		0x00000080	/**< backplane/4 */
++#define	CF_CE			0x00000100	/**< clock enable */
++#define	CF_SB			0x00000200	/**< size/bytestrobe (synch only) */
++
++/* pcmcia_memwait */
++#define	PM_W0_MASK		0x0000003f	/**< waitcount0 */
++#define	PM_W1_MASK		0x00001f00	/**< waitcount1 */
++#define	PM_W1_SHIFT		8
++#define	PM_W2_MASK		0x001f0000	/**< waitcount2 */
++#define	PM_W2_SHIFT		16
++#define	PM_W3_MASK		0x1f000000	/**< waitcount3 */
++#define	PM_W3_SHIFT		24
++
++/* pcmcia_attrwait */
++#define	PA_W0_MASK		0x0000003f	/**< waitcount0 */
++#define	PA_W1_MASK		0x00001f00	/**< waitcount1 */
++#define	PA_W1_SHIFT		8
++#define	PA_W2_MASK		0x001f0000	/**< waitcount2 */
++#define	PA_W2_SHIFT		16
++#define	PA_W3_MASK		0x1f000000	/**< waitcount3 */
++#define	PA_W3_SHIFT		24
++
++/* pcmcia_iowait */
++#define	PI_W0_MASK		0x0000003f	/**< waitcount0 */
++#define	PI_W1_MASK		0x00001f00	/**< waitcount1 */
++#define	PI_W1_SHIFT		8
++#define	PI_W2_MASK		0x001f0000	/**< waitcount2 */
++#define	PI_W2_SHIFT		16
++#define	PI_W3_MASK		0x1f000000	/**< waitcount3 */
++#define	PI_W3_SHIFT		24
++
++/* prog_waitcount */
++#define	PW_W0_MASK		0x0000001f	/**< waitcount0 */
++#define	PW_W1_MASK		0x00001f00	/**< waitcount1 */
++#define	PW_W1_SHIFT		8
++#define	PW_W2_MASK		0x001f0000	/**< waitcount2 */
++#define	PW_W2_SHIFT		16
++#define	PW_W3_MASK		0x1f000000	/**< waitcount3 */
++#define	PW_W3_SHIFT		24
++
++#define PW_W0       		0x0000000c
++#define PW_W1       		0x00000a00
++#define PW_W2       		0x00020000
++#define PW_W3       		0x01000000
++
++/* flash_waitcount */
++#define	FW_W0_MASK		0x0000003f	/**< waitcount0 */
++#define	FW_W1_MASK		0x00001f00	/**< waitcount1 */
++#define	FW_W1_SHIFT		8
++#define	FW_W2_MASK		0x001f0000	/**< waitcount2 */
++#define	FW_W2_SHIFT		16
++#define	FW_W3_MASK		0x1f000000	/**< waitcount3 */
++#define	FW_W3_SHIFT		24
++
++/* When Srom support present, fields in sromcontrol */
++#define	SRC_START		0x80000000
++#define	SRC_BUSY		0x80000000
++#define	SRC_OPCODE		0x60000000
++#define	SRC_OP_READ		0x00000000
++#define	SRC_OP_WRITE		0x20000000
++#define	SRC_OP_WRDIS		0x40000000
++#define	SRC_OP_WREN		0x60000000
++#define	SRC_OTPSEL		0x00000010
++#define SRC_OTPPRESENT		0x00000020
++#define	SRC_LOCK		0x00000008
++#define	SRC_SIZE_MASK		0x00000006
++#define	SRC_SIZE_1K		0x00000000
++#define	SRC_SIZE_4K		0x00000002
++#define	SRC_SIZE_16K		0x00000004
++#define	SRC_SIZE_SHIFT		1
++#define	SRC_PRESENT		0x00000001
++
++/* Fields in pmucontrol */
++#define	PCTL_ILP_DIV_MASK	0xffff0000
++#define	PCTL_ILP_DIV_SHIFT	16
++#define PCTL_LQ_REQ_EN		0x00008000
++#define PCTL_PLL_PLLCTL_UPD	0x00000400	/**< rev 2 */
++#define PCTL_NOILP_ON_WAIT	0x00000200	/**< rev 1 */
++#define	PCTL_HT_REQ_EN		0x00000100
++#define	PCTL_ALP_REQ_EN		0x00000080
++#define	PCTL_XTALFREQ_MASK	0x0000007c
++#define	PCTL_XTALFREQ_SHIFT	2
++#define	PCTL_ILP_DIV_EN		0x00000002
++#define	PCTL_LPO_SEL		0x00000001
++
++/* Fields in pmucontrol_ext */
++#define PCTL_EXT_FASTLPO_ENAB		0x00000080
++#define PCTL_EXT_FASTLPO_SWENAB	0x00000200
++#define PCTL_EXT_FASTLPO_PCIE_SWENAB	0x00004000  /**< rev33 for FLL1M */
++
++#define DEFAULT_43012_MIN_RES_MASK		0x0f8bfe77
++
++/*  Retention Control */
++#define PMU_RCTL_CLK_DIV_SHIFT		0
++#define PMU_RCTL_CHAIN_LEN_SHIFT	12
++#define PMU_RCTL_MACPHY_DISABLE_SHIFT	26
++#define PMU_RCTL_MACPHY_DISABLE_MASK	(1 << 26)
++#define PMU_RCTL_LOGIC_DISABLE_SHIFT	27
++#define PMU_RCTL_LOGIC_DISABLE_MASK	(1 << 27)
++#define PMU_RCTL_MEMSLP_LOG_SHIFT	28
++#define PMU_RCTL_MEMSLP_LOG_MASK	(1 << 28)
++#define PMU_RCTL_MEMRETSLP_LOG_SHIFT	29
++#define PMU_RCTL_MEMRETSLP_LOG_MASK	(1 << 29)
++
++/*  Retention Group Control */
++#define PMU_RCTLGRP_CHAIN_LEN_SHIFT	0
++#define PMU_RCTLGRP_RMODE_ENABLE_SHIFT	14
++#define PMU_RCTLGRP_RMODE_ENABLE_MASK	(1 << 14)
++#define PMU_RCTLGRP_DFT_ENABLE_SHIFT	15
++#define PMU_RCTLGRP_DFT_ENABLE_MASK	(1 << 15)
++#define PMU_RCTLGRP_NSRST_DISABLE_SHIFT	16
++#define PMU_RCTLGRP_NSRST_DISABLE_MASK	(1 << 16)
++/*  Retention Group Control special for 4334 */
++#define PMU4334_RCTLGRP_CHAIN_LEN_GRP0	338
++#define PMU4334_RCTLGRP_CHAIN_LEN_GRP1	315
++/*  Retention Group Control special for 43341 */
++#define PMU43341_RCTLGRP_CHAIN_LEN_GRP0	366
++#define PMU43341_RCTLGRP_CHAIN_LEN_GRP1	330
++
++/* Fields in clkstretch */
++#define CSTRETCH_HT		0xffff0000
++#define CSTRETCH_ALP		0x0000ffff
++
++/* gpiotimerval */
++#define GPIO_ONTIME_SHIFT	16
++
++/* clockcontrol_n */
++#define	CN_N1_MASK		0x3f		/**< n1 control */
++#define	CN_N2_MASK		0x3f00		/**< n2 control */
++#define	CN_N2_SHIFT		8
++#define	CN_PLLC_MASK		0xf0000		/**< pll control */
++#define	CN_PLLC_SHIFT		16
++
++/* clockcontrol_sb/pci/uart */
++#define	CC_M1_MASK		0x3f		/**< m1 control */
++#define	CC_M2_MASK		0x3f00		/**< m2 control */
++#define	CC_M2_SHIFT		8
++#define	CC_M3_MASK		0x3f0000	/**< m3 control */
++#define	CC_M3_SHIFT		16
++#define	CC_MC_MASK		0x1f000000	/**< mux control */
++#define	CC_MC_SHIFT		24
++
++/* N3M Clock control magic field values */
++#define	CC_F6_2			0x02		/**< A factor of 2 in */
++#define	CC_F6_3			0x03		/**< 6-bit fields like */
++#define	CC_F6_4			0x05		/**< N1, M1 or M3 */
++#define	CC_F6_5			0x09
++#define	CC_F6_6			0x11
++#define	CC_F6_7			0x21
++
++#define	CC_F5_BIAS		5		/**< 5-bit fields get this added */
++
++#define	CC_MC_BYPASS		0x08
++#define	CC_MC_M1		0x04
++#define	CC_MC_M1M2		0x02
++#define	CC_MC_M1M2M3		0x01
++#define	CC_MC_M1M3		0x11
++
++/* Type 2 Clock control magic field values */
++#define	CC_T2_BIAS		2		/**< n1, n2, m1 & m3 bias */
++#define	CC_T2M2_BIAS		3		/**< m2 bias */
++
++#define	CC_T2MC_M1BYP		1
++#define	CC_T2MC_M2BYP		2
++#define	CC_T2MC_M3BYP		4
++
++/* Type 6 Clock control magic field values */
++#define	CC_T6_MMASK		1		/**< bits of interest in m */
++#define	CC_T6_M0		120000000	/**< sb clock for m = 0 */
++#define	CC_T6_M1		100000000	/**< sb clock for m = 1 */
++#define	SB2MIPS_T6(sb)		(2 * (sb))
++
++/* Common clock base */
++#define	CC_CLOCK_BASE1		24000000	/**< Half the clock freq */
++#define CC_CLOCK_BASE2		12500000	/**< Alternate crystal on some PLLs */
++
++/* Clock control values for 200MHz in 5350 */
++#define	CLKC_5350_N		0x0311
++#define	CLKC_5350_M		0x04020009
++
++/* Flash types in the chipcommon capabilities register */
++#define FLASH_NONE		0x000		/**< No flash */
++#define SFLASH_ST		0x100		/**< ST serial flash */
++#define SFLASH_AT		0x200		/**< Atmel serial flash */
++#define NFLASH			0x300
++#define	PFLASH			0x700		/**< Parallel flash */
++#define QSPIFLASH_ST		0x800
++#define QSPIFLASH_AT		0x900
++
++/* Bits in the ExtBus config registers */
++#define	CC_CFG_EN		0x0001		/**< Enable */
++#define	CC_CFG_EM_MASK		0x000e		/**< Extif Mode */
++#define	CC_CFG_EM_ASYNC		0x0000		/**<   Async/Parallel flash */
++#define	CC_CFG_EM_SYNC		0x0002		/**<   Synchronous */
++#define	CC_CFG_EM_PCMCIA	0x0004		/**<   PCMCIA */
++#define	CC_CFG_EM_IDE		0x0006		/**<   IDE */
++#define	CC_CFG_DS		0x0010		/**< Data size, 0=8bit, 1=16bit */
++#define	CC_CFG_CD_MASK		0x00e0		/**< Sync: Clock divisor, rev >= 20 */
++#define	CC_CFG_CE		0x0100		/**< Sync: Clock enable, rev >= 20 */
++#define	CC_CFG_SB		0x0200		/**< Sync: Size/Bytestrobe, rev >= 20 */
++#define	CC_CFG_IS		0x0400		/**< Extif Sync Clk Select, rev >= 20 */
++
++/* ExtBus address space */
++#define	CC_EB_BASE		0x1a000000	/**< Chipc ExtBus base address */
++#define	CC_EB_PCMCIA_MEM	0x1a000000	/**< PCMCIA 0 memory base address */
++#define	CC_EB_PCMCIA_IO		0x1a200000	/**< PCMCIA 0 I/O base address */
++#define	CC_EB_PCMCIA_CFG	0x1a400000	/**< PCMCIA 0 config base address */
++#define	CC_EB_IDE		0x1a800000	/**< IDE memory base */
++#define	CC_EB_PCMCIA1_MEM	0x1a800000	/**< PCMCIA 1 memory base address */
++#define	CC_EB_PCMCIA1_IO	0x1aa00000	/**< PCMCIA 1 I/O base address */
++#define	CC_EB_PCMCIA1_CFG	0x1ac00000	/**< PCMCIA 1 config base address */
++#define	CC_EB_PROGIF		0x1b000000	/**< ProgIF Async/Sync base address */
++
++
++/* Start/busy bit in flashcontrol */
++#define SFLASH_OPCODE		0x000000ff
++#define SFLASH_ACTION		0x00000700
++#define	SFLASH_CS_ACTIVE	0x00001000	/**< Chip Select Active, rev >= 20 */
++#define SFLASH_START		0x80000000
++#define SFLASH_BUSY		SFLASH_START
++
++/* flashcontrol action codes */
++#define	SFLASH_ACT_OPONLY	0x0000		/**< Issue opcode only */
++#define	SFLASH_ACT_OP1D		0x0100		/**< opcode + 1 data byte */
++#define	SFLASH_ACT_OP3A		0x0200		/**< opcode + 3 addr bytes */
++#define	SFLASH_ACT_OP3A1D	0x0300		/**< opcode + 3 addr & 1 data bytes */
++#define	SFLASH_ACT_OP3A4D	0x0400		/**< opcode + 3 addr & 4 data bytes */
++#define	SFLASH_ACT_OP3A4X4D	0x0500		/**< opcode + 3 addr, 4 don't care & 4 data bytes */
++#define	SFLASH_ACT_OP3A1X4D	0x0700		/**< opcode + 3 addr, 1 don't care & 4 data bytes */
++
++/* flashcontrol action+opcodes for ST flashes */
++#define SFLASH_ST_WREN		0x0006		/**< Write Enable */
++#define SFLASH_ST_WRDIS		0x0004		/**< Write Disable */
++#define SFLASH_ST_RDSR		0x0105		/**< Read Status Register */
++#define SFLASH_ST_WRSR		0x0101		/**< Write Status Register */
++#define SFLASH_ST_READ		0x0303		/**< Read Data Bytes */
++#define SFLASH_ST_PP		0x0302		/**< Page Program */
++#define SFLASH_ST_SE		0x02d8		/**< Sector Erase */
++#define SFLASH_ST_BE		0x00c7		/**< Bulk Erase */
++#define SFLASH_ST_DP		0x00b9		/**< Deep Power-down */
++#define SFLASH_ST_RES		0x03ab		/**< Read Electronic Signature */
++#define SFLASH_ST_CSA		0x1000		/**< Keep chip select asserted */
++#define SFLASH_ST_SSE		0x0220		/**< Sub-sector Erase */
++
++#define SFLASH_ST_READ4B	0x6313		/* Read Data Bytes in 4Byte address */
++#define SFLASH_ST_PP4B		0x6312		/* Page Program in 4Byte address */
++#define SFLASH_ST_SE4B		0x62dc		/* Sector Erase in 4Byte address */
++#define SFLASH_ST_SSE4B		0x6221		/* Sub-sector Erase */
++
++#define SFLASH_MXIC_RDID	0x0390		/* Read Manufacture ID */
++#define SFLASH_MXIC_MFID	0xc2		/* MXIC Manufacture ID */
++
++/* Status register bits for ST flashes */
++#define SFLASH_ST_WIP		0x01		/**< Write In Progress */
++#define SFLASH_ST_WEL		0x02		/**< Write Enable Latch */
++#define SFLASH_ST_BP_MASK	0x1c		/**< Block Protect */
++#define SFLASH_ST_BP_SHIFT	2
++#define SFLASH_ST_SRWD		0x80		/**< Status Register Write Disable */
++
++/* flashcontrol action+opcodes for Atmel flashes */
++#define SFLASH_AT_READ				0x07e8
++#define SFLASH_AT_PAGE_READ			0x07d2
++#define SFLASH_AT_BUF1_READ
++#define SFLASH_AT_BUF2_READ
++#define SFLASH_AT_STATUS			0x01d7
++#define SFLASH_AT_BUF1_WRITE			0x0384
++#define SFLASH_AT_BUF2_WRITE			0x0387
++#define SFLASH_AT_BUF1_ERASE_PROGRAM		0x0283
++#define SFLASH_AT_BUF2_ERASE_PROGRAM		0x0286
++#define SFLASH_AT_BUF1_PROGRAM			0x0288
++#define SFLASH_AT_BUF2_PROGRAM			0x0289
++#define SFLASH_AT_PAGE_ERASE			0x0281
++#define SFLASH_AT_BLOCK_ERASE			0x0250
++#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM	0x0382
++#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM	0x0385
++#define SFLASH_AT_BUF1_LOAD			0x0253
++#define SFLASH_AT_BUF2_LOAD			0x0255
++#define SFLASH_AT_BUF1_COMPARE			0x0260
++#define SFLASH_AT_BUF2_COMPARE			0x0261
++#define SFLASH_AT_BUF1_REPROGRAM		0x0258
++#define SFLASH_AT_BUF2_REPROGRAM		0x0259
++
++/* Status register bits for Atmel flashes */
++#define SFLASH_AT_READY				0x80
++#define SFLASH_AT_MISMATCH			0x40
++#define SFLASH_AT_ID_MASK			0x38
++#define SFLASH_AT_ID_SHIFT			3
++
++/* SPI register bits, corerev >= 37 */
++#define GSIO_START			0x80000000
++#define GSIO_BUSY			GSIO_START
++
++/*
++ * These are the UART port assignments, expressed as offsets from the base
++ * register.  These assignments should hold for any serial port based on
++ * a 8250, 16450, or 16550(A).
++ */
++
++#define UART_RX		0	/**< In:  Receive buffer (DLAB=0) */
++#define UART_TX		0	/**< Out: Transmit buffer (DLAB=0) */
++#define UART_DLL	0	/**< Out: Divisor Latch Low (DLAB=1) */
++#define UART_IER	1	/**< In/Out: Interrupt Enable Register (DLAB=0) */
++#define UART_DLM	1	/**< Out: Divisor Latch High (DLAB=1) */
++#define UART_IIR	2	/**< In: Interrupt Identity Register  */
++#define UART_FCR	2	/**< Out: FIFO Control Register */
++#define UART_LCR	3	/**< Out: Line Control Register */
++#define UART_MCR	4	/**< Out: Modem Control Register */
++#define UART_LSR	5	/**< In:  Line Status Register */
++#define UART_MSR	6	/**< In:  Modem Status Register */
++#define UART_SCR	7	/**< I/O: Scratch Register */
++#define UART_LCR_DLAB	0x80	/**< Divisor latch access bit */
++#define UART_LCR_WLEN8	0x03	/**< Word length: 8 bits */
++#define UART_MCR_OUT2	0x08	/**< MCR GPIO out 2 */
++#define UART_MCR_LOOP	0x10	/**< Enable loopback test mode */
++#define UART_LSR_RX_FIFO 	0x80	/**< Receive FIFO error */
++#define UART_LSR_TDHR		0x40	/**< Data-hold-register empty */
++#define UART_LSR_THRE		0x20	/**< Transmit-hold-register empty */
++#define UART_LSR_BREAK		0x10	/**< Break interrupt */
++#define UART_LSR_FRAMING	0x08	/**< Framing error */
++#define UART_LSR_PARITY		0x04	/**< Parity error */
++#define UART_LSR_OVERRUN	0x02	/**< Overrun error */
++#define UART_LSR_RXRDY		0x01	/**< Receiver ready */
++#define UART_FCR_FIFO_ENABLE 1	/**< FIFO control register bit controlling FIFO enable/disable */
++
++/* Interrupt Identity Register (IIR) bits */
++#define UART_IIR_FIFO_MASK	0xc0	/**< IIR FIFO disable/enabled mask */
++#define UART_IIR_INT_MASK	0xf	/**< IIR interrupt ID source */
++#define UART_IIR_MDM_CHG	0x0	/**< Modem status changed */
++#define UART_IIR_NOINT		0x1	/**< No interrupt pending */
++#define UART_IIR_THRE		0x2	/**< THR empty */
++#define UART_IIR_RCVD_DATA	0x4	/**< Received data available */
++#define UART_IIR_RCVR_STATUS 	0x6	/**< Receiver status */
++#define UART_IIR_CHAR_TIME 	0xc	/**< Character time */
++
++/* Interrupt Enable Register (IER) bits */
++#define UART_IER_PTIME	128	/**< Programmable THRE Interrupt Mode Enable */
++#define UART_IER_EDSSI	8	/**< enable modem status interrupt */
++#define UART_IER_ELSI	4	/**< enable receiver line status interrupt */
++#define UART_IER_ETBEI  2	/**< enable transmitter holding register empty interrupt */
++#define UART_IER_ERBFI	1	/**< enable data available interrupt */
++
++/* pmustatus */
++#define PST_SLOW_WR_PENDING 0x0400
++#define PST_EXTLPOAVAIL	0x0100
++#define PST_WDRESET	0x0080
++#define	PST_INTPEND	0x0040
++#define	PST_SBCLKST	0x0030
++#define	PST_SBCLKST_ILP	0x0010
++#define	PST_SBCLKST_ALP	0x0020
++#define	PST_SBCLKST_HT	0x0030
++#define	PST_ALPAVAIL	0x0008
++#define	PST_HTAVAIL	0x0004
++#define	PST_RESINIT	0x0003
++#define	PST_ILPFASTLPO	0x00010000
++
++/* pmucapabilities */
++#define PCAP_REV_MASK	0x000000ff
++#define PCAP_RC_MASK	0x00001f00
++#define PCAP_RC_SHIFT	8
++#define PCAP_TC_MASK	0x0001e000
++#define PCAP_TC_SHIFT	13
++#define PCAP_PC_MASK	0x001e0000
++#define PCAP_PC_SHIFT	17
++#define PCAP_VC_MASK	0x01e00000
++#define PCAP_VC_SHIFT	21
++#define PCAP_CC_MASK	0x1e000000
++#define PCAP_CC_SHIFT	25
++#define PCAP5_PC_MASK	0x003e0000	/**< PMU corerev >= 5 */
++#define PCAP5_PC_SHIFT	17
++#define PCAP5_VC_MASK	0x07c00000
++#define PCAP5_VC_SHIFT	22
++#define PCAP5_CC_MASK	0xf8000000
++#define PCAP5_CC_SHIFT	27
++
++/* CoreCapabilitiesExtension */
++#define PCAP_EXT_USE_MUXED_ILP_CLK_MASK	0x04000000
++
++/* PMU Resource Request Timer registers */
++/* This is based on PmuRev0 */
++#define	PRRT_TIME_MASK	0x03ff
++#define	PRRT_INTEN	0x0400
++#define	PRRT_REQ_ACTIVE	0x0800
++#define	PRRT_ALP_REQ	0x1000
++#define	PRRT_HT_REQ	0x2000
++#define PRRT_HQ_REQ 0x4000
++
++/* PMU Int Control register bits */
++#define PMU_INTC_ALP_REQ	0x1
++#define PMU_INTC_HT_REQ		0x2
++#define PMU_INTC_HQ_REQ		0x4
++
++/* bit 0 of the PMU interrupt vector is asserted if this mask is enabled */
++#define RSRC_INTR_MASK_TIMER_INT_0 1
++
++/* PMU resource bit position */
++#define PMURES_BIT(bit)	(1 << (bit))
++
++/* PMU resource number limit */
++#define PMURES_MAX_RESNUM	30
++
++/* PMU chip control0 register */
++#define	PMU_CHIPCTL0		0
++#define PMU43143_CC0_SDIO_DRSTR_OVR	(1 << 31) /* sdio drive strength override enable */
++
++/* clock req types */
++#define PMU_CC1_CLKREQ_TYPE_SHIFT	19
++#define PMU_CC1_CLKREQ_TYPE_MASK	(1 << PMU_CC1_CLKREQ_TYPE_SHIFT)
++
++#define CLKREQ_TYPE_CONFIG_OPENDRAIN		0
++#define CLKREQ_TYPE_CONFIG_PUSHPULL		1
++
++/* PMU chip control1 register */
++#define	PMU_CHIPCTL1			1
++#define	PMU_CC1_RXC_DLL_BYPASS		0x00010000
++#define PMU_CC1_ENABLE_BBPLL_PWR_DOWN	0x00000010
++
++#define PMU_CC1_IF_TYPE_MASK   		0x00000030
++#define PMU_CC1_IF_TYPE_RMII    	0x00000000
++#define PMU_CC1_IF_TYPE_MII     	0x00000010
++#define PMU_CC1_IF_TYPE_RGMII   	0x00000020
++
++#define PMU_CC1_SW_TYPE_MASK    	0x000000c0
++#define PMU_CC1_SW_TYPE_EPHY    	0x00000000
++#define PMU_CC1_SW_TYPE_EPHYMII 	0x00000040
++#define PMU_CC1_SW_TYPE_EPHYRMII	0x00000080
++#define PMU_CC1_SW_TYPE_RGMII   	0x000000c0
++
++#define PMU_CC1_ENABLE_CLOSED_LOOP_MASK 0x00000080
++#define PMU_CC1_ENABLE_CLOSED_LOOP      0x00000000
++
++/* PMU chip control2 register */
++#define PMU_CC2_RFLDO3P3_PU_FORCE_ON		(1 << 15)
++#define PMU_CC2_RFLDO3P3_PU_CLEAR		0x00000000
++
++#define PMU_CC2_WL2CDIG_I_PMU_SLEEP		(1 << 16)
++#define	PMU_CHIPCTL2		2
++#define PMU_CC2_FORCE_SUBCORE_PWR_SWITCH_ON	(1 << 18)
++#define PMU_CC2_FORCE_PHY_PWR_SWITCH_ON		(1 << 19)
++#define PMU_CC2_FORCE_VDDM_PWR_SWITCH_ON	(1 << 20)
++#define PMU_CC2_FORCE_MEMLPLDO_PWR_SWITCH_ON	(1 << 21)
++#define PMU_CC2_MASK_WL_DEV_WAKE             (1 << 22)
++#define PMU_CC2_INV_GPIO_POLARITY_PMU_WAKE   (1 << 25)
++#define PMU_CC2_GCI2_WAKE                    (1 << 31)
++
++/* PMU chip control3 register */
++#define	PMU_CHIPCTL3		3
++#define PMU_CC3_ENABLE_SDIO_WAKEUP_SHIFT  19
++#define PMU_CC3_ENABLE_RF_SHIFT           22
++#define PMU_CC3_RF_DISABLE_IVALUE_SHIFT   23
++
++/* PMU chip control4 register */
++#define PMU_CHIPCTL4                    4
++
++/* 53537 series moved switch_type and gmac_if_type to CC4 [15:14] and [13:12] */
++#define PMU_CC4_IF_TYPE_MASK		0x00003000
++#define PMU_CC4_IF_TYPE_RMII		0x00000000
++#define PMU_CC4_IF_TYPE_MII		0x00001000
++#define PMU_CC4_IF_TYPE_RGMII		0x00002000
++
++#define PMU_CC4_SW_TYPE_MASK		0x0000c000
++#define PMU_CC4_SW_TYPE_EPHY		0x00000000
++#define PMU_CC4_SW_TYPE_EPHYMII		0x00004000
++#define PMU_CC4_SW_TYPE_EPHYRMII	0x00008000
++#define PMU_CC4_SW_TYPE_RGMII		0x0000c000
++#define PMU_CC4_DISABLE_LQ_AVAIL	(1<<27)
++
++/* PMU chip control5 register */
++#define PMU_CHIPCTL5                    5
++
++/* PMU chip control6 register */
++#define PMU_CHIPCTL6                    6
++#define PMU_CC6_ENABLE_CLKREQ_WAKEUP    (1 << 4)
++#define PMU_CC6_ENABLE_PMU_WAKEUP_ALP   (1 << 6)
++
++/* PMU chip control7 register */
++#define PMU_CHIPCTL7				7
++#define PMU_CC7_ENABLE_L2REFCLKPAD_PWRDWN	(1 << 25)
++#define PMU_CC7_ENABLE_MDIO_RESET_WAR		(1 << 27)
++/* 53537 series have gmca1 gmac_if_type in cc7 [7:6](defalut 0b01) */
++#define PMU_CC7_IF_TYPE_MASK		0x000000c0
++#define PMU_CC7_IF_TYPE_RMII		0x00000000
++#define PMU_CC7_IF_TYPE_MII		0x00000040
++#define PMU_CC7_IF_TYPE_RGMII		0x00000080
++
++#define PMU_CHIPCTL8			8
++#define PMU_CHIPCTL9			9
++
++/* PMU corerev and chip specific PLL controls.
++ * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number
++ * to differentiate different PLLs controlled by the same PMU rev.
++ */
++/* pllcontrol registers */
++/* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */
++#define	PMU0_PLL0_PLLCTL0		0
++#define	PMU0_PLL0_PC0_PDIV_MASK		1
++#define	PMU0_PLL0_PC0_PDIV_FREQ		25000
++#define PMU0_PLL0_PC0_DIV_ARM_MASK	0x00000038
++#define PMU0_PLL0_PC0_DIV_ARM_SHIFT	3
++#define PMU0_PLL0_PC0_DIV_ARM_BASE	8
++
++/* PC0_DIV_ARM for PLLOUT_ARM */
++#define PMU0_PLL0_PC0_DIV_ARM_110MHZ	0
++#define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ	1
++#define PMU0_PLL0_PC0_DIV_ARM_88MHZ	2
++#define PMU0_PLL0_PC0_DIV_ARM_80MHZ	3 /* Default */
++#define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ	4
++#define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ	5
++#define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ	6
++#define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ	7
++
++/* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */
++#define	PMU0_PLL0_PLLCTL1		1
++#define	PMU0_PLL0_PC1_WILD_INT_MASK	0xf0000000
++#define	PMU0_PLL0_PC1_WILD_INT_SHIFT	28
++#define	PMU0_PLL0_PC1_WILD_FRAC_MASK	0x0fffff00
++#define	PMU0_PLL0_PC1_WILD_FRAC_SHIFT	8
++#define	PMU0_PLL0_PC1_STOP_MOD		0x00000040
++
++/* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */
++#define	PMU0_PLL0_PLLCTL2		2
++#define	PMU0_PLL0_PC2_WILD_INT_MASK	0xf
++#define	PMU0_PLL0_PC2_WILD_INT_SHIFT	4
++
++/* pllcontrol registers */
++/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */
++#define PMU1_PLL0_PLLCTL0		0
++#define PMU1_PLL0_PC0_P1DIV_MASK	0x00f00000
++#define PMU1_PLL0_PC0_P1DIV_SHIFT	20
++#define PMU1_PLL0_PC0_P2DIV_MASK	0x0f000000
++#define PMU1_PLL0_PC0_P2DIV_SHIFT	24
++
++/* m<x>div */
++#define PMU1_PLL0_PLLCTL1		1
++#define PMU1_PLL0_PC1_M1DIV_MASK	0x000000ff
++#define PMU1_PLL0_PC1_M1DIV_SHIFT	0
++#define PMU1_PLL0_PC1_M2DIV_MASK	0x0000ff00
++#define PMU1_PLL0_PC1_M2DIV_SHIFT	8
++#define PMU1_PLL0_PC1_M3DIV_MASK	0x00ff0000
++#define PMU1_PLL0_PC1_M3DIV_SHIFT	16
++#define PMU1_PLL0_PC1_M4DIV_MASK	0xff000000
++#define PMU1_PLL0_PC1_M4DIV_SHIFT	24
++#define PMU1_PLL0_PC1_M4DIV_BY_9	9
++#define PMU1_PLL0_PC1_M4DIV_BY_18	0x12
++#define PMU1_PLL0_PC1_M4DIV_BY_36	0x24
++#define PMU1_PLL0_PC1_M4DIV_BY_60	0x3C
++
++#define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8
++#define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
++#define DOT11MAC_880MHZ_CLK_DIVISOR_VAL  (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
++
++/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
++#define PMU1_PLL0_PLLCTL2		2
++#define PMU1_PLL0_PC2_M5DIV_MASK	0x000000ff
++#define PMU1_PLL0_PC2_M5DIV_SHIFT	0
++#define PMU1_PLL0_PC2_M5DIV_BY_12	0xc
++#define PMU1_PLL0_PC2_M5DIV_BY_18	0x12
++#define PMU1_PLL0_PC2_M5DIV_BY_31	0x1f
++#define PMU1_PLL0_PC2_M5DIV_BY_36	0x24
++#define PMU1_PLL0_PC2_M5DIV_BY_42	0x2a
++#define PMU1_PLL0_PC2_M5DIV_BY_60	0x3c
++#define PMU1_PLL0_PC2_M6DIV_MASK	0x0000ff00
++#define PMU1_PLL0_PC2_M6DIV_SHIFT	8
++#define PMU1_PLL0_PC2_M6DIV_BY_18	0x12
++#define PMU1_PLL0_PC2_M6DIV_BY_36	0x24
++#define PMU1_PLL0_PC2_NDIV_MODE_MASK	0x000e0000
++#define PMU1_PLL0_PC2_NDIV_MODE_SHIFT	17
++#define PMU1_PLL0_PC2_NDIV_MODE_MASH	1
++#define PMU1_PLL0_PC2_NDIV_MODE_MFB	2	/**< recommended for 4319 */
++#define PMU1_PLL0_PC2_NDIV_INT_MASK	0x1ff00000
++#define PMU1_PLL0_PC2_NDIV_INT_SHIFT	20
++
++/* ndiv_frac */
++#define PMU1_PLL0_PLLCTL3		3
++#define PMU1_PLL0_PC3_NDIV_FRAC_MASK	0x00ffffff
++#define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT	0
++
++/* pll_ctrl */
++#define PMU1_PLL0_PLLCTL4		4
++
++/* pll_ctrl, vco_rng, clkdrive_ch<x> */
++#define PMU1_PLL0_PLLCTL5		5
++#define PMU1_PLL0_PC5_CLK_DRV_MASK 	0xffffff00
++#define PMU1_PLL0_PC5_CLK_DRV_SHIFT 	8
++#define PMU1_PLL0_PC5_ASSERT_CH_MASK 	0x3f000000
++#define PMU1_PLL0_PC5_ASSERT_CH_SHIFT 	24
++#define PMU1_PLL0_PC5_DEASSERT_CH_MASK 	0xff000000
++
++#define PMU1_PLL0_PLLCTL6		6
++#define PMU1_PLL0_PLLCTL7		7
++#define PMU1_PLL0_PLLCTL8		8
++
++#define PMU1_PLLCTL8_OPENLOOP_MASK	(1 << 1)
++#define PMU_PLL4350_OPENLOOP_MASK	(1 << 7)
++
++#define PMU1_PLL0_PLLCTL9		9
++
++#define PMU1_PLL0_PLLCTL10		10
++
++/* PMU rev 2 control words */
++#define PMU2_PHY_PLL_PLLCTL		4
++#define PMU2_SI_PLL_PLLCTL		10
++
++/* PMU rev 2 */
++/* pllcontrol registers */
++/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */
++#define PMU2_PLL_PLLCTL0		0
++#define PMU2_PLL_PC0_P1DIV_MASK 	0x00f00000
++#define PMU2_PLL_PC0_P1DIV_SHIFT	20
++#define PMU2_PLL_PC0_P2DIV_MASK 	0x0f000000
++#define PMU2_PLL_PC0_P2DIV_SHIFT	24
++
++/* m<x>div */
++#define PMU2_PLL_PLLCTL1		1
++#define PMU2_PLL_PC1_M1DIV_MASK 	0x000000ff
++#define PMU2_PLL_PC1_M1DIV_SHIFT	0
++#define PMU2_PLL_PC1_M2DIV_MASK 	0x0000ff00
++#define PMU2_PLL_PC1_M2DIV_SHIFT	8
++#define PMU2_PLL_PC1_M3DIV_MASK 	0x00ff0000
++#define PMU2_PLL_PC1_M3DIV_SHIFT	16
++#define PMU2_PLL_PC1_M4DIV_MASK 	0xff000000
++#define PMU2_PLL_PC1_M4DIV_SHIFT	24
++
++/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
++#define PMU2_PLL_PLLCTL2		2
++#define PMU2_PLL_PC2_M5DIV_MASK 	0x000000ff
++#define PMU2_PLL_PC2_M5DIV_SHIFT	0
++#define PMU2_PLL_PC2_M6DIV_MASK 	0x0000ff00
++#define PMU2_PLL_PC2_M6DIV_SHIFT	8
++#define PMU2_PLL_PC2_NDIV_MODE_MASK	0x000e0000
++#define PMU2_PLL_PC2_NDIV_MODE_SHIFT	17
++#define PMU2_PLL_PC2_NDIV_INT_MASK	0x1ff00000
++#define PMU2_PLL_PC2_NDIV_INT_SHIFT	20
++
++/* ndiv_frac */
++#define PMU2_PLL_PLLCTL3		3
++#define PMU2_PLL_PC3_NDIV_FRAC_MASK	0x00ffffff
++#define PMU2_PLL_PC3_NDIV_FRAC_SHIFT	0
++
++/* pll_ctrl */
++#define PMU2_PLL_PLLCTL4		4
++
++/* pll_ctrl, vco_rng, clkdrive_ch<x> */
++#define PMU2_PLL_PLLCTL5		5
++#define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK	0x00000f00
++#define PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT	8
++#define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK	0x0000f000
++#define PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT	12
++#define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK	0x000f0000
++#define PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT	16
++#define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK	0x00f00000
++#define PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT	20
++#define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK	0x0f000000
++#define PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT	24
++#define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK	0xf0000000
++#define PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT	28
++
++/* PMU rev 5 (& 6) */
++#define	PMU5_PLL_P1P2_OFF		0
++#define	PMU5_PLL_P1_MASK		0x0f000000
++#define	PMU5_PLL_P1_SHIFT		24
++#define	PMU5_PLL_P2_MASK		0x00f00000
++#define	PMU5_PLL_P2_SHIFT		20
++#define	PMU5_PLL_M14_OFF		1
++#define	PMU5_PLL_MDIV_MASK		0x000000ff
++#define	PMU5_PLL_MDIV_WIDTH		8
++#define	PMU5_PLL_NM5_OFF		2
++#define	PMU5_PLL_NDIV_MASK		0xfff00000
++#define	PMU5_PLL_NDIV_SHIFT		20
++#define	PMU5_PLL_NDIV_MODE_MASK		0x000e0000
++#define	PMU5_PLL_NDIV_MODE_SHIFT	17
++#define	PMU5_PLL_FMAB_OFF		3
++#define	PMU5_PLL_MRAT_MASK		0xf0000000
++#define	PMU5_PLL_MRAT_SHIFT		28
++#define	PMU5_PLL_ABRAT_MASK		0x08000000
++#define	PMU5_PLL_ABRAT_SHIFT		27
++#define	PMU5_PLL_FDIV_MASK		0x07ffffff
++#define	PMU5_PLL_PLLCTL_OFF		4
++#define	PMU5_PLL_PCHI_OFF		5
++#define	PMU5_PLL_PCHI_MASK		0x0000003f
++
++/* pmu XtalFreqRatio */
++#define	PMU_XTALFREQ_REG_ILPCTR_MASK	0x00001FFF
++#define	PMU_XTALFREQ_REG_MEASURE_MASK	0x80000000
++#define	PMU_XTALFREQ_REG_MEASURE_SHIFT	31
++
++/* Divider allocation in 4716/47162/5356/5357 */
++#define	PMU5_MAINPLL_CPU		1
++#define	PMU5_MAINPLL_MEM		2
++#define	PMU5_MAINPLL_SI			3
++
++/* 4706 PMU */
++#define PMU4706_MAINPLL_PLL0	0
++#define PMU6_4706_PROCPLL_OFF	4	/**< The CPU PLL */
++#define PMU6_4706_PROC_P2DIV_MASK		0x000f0000
++#define PMU6_4706_PROC_P2DIV_SHIFT	16
++#define PMU6_4706_PROC_P1DIV_MASK		0x0000f000
++#define PMU6_4706_PROC_P1DIV_SHIFT	12
++#define PMU6_4706_PROC_NDIV_INT_MASK	0x00000ff8
++#define PMU6_4706_PROC_NDIV_INT_SHIFT	3
++#define PMU6_4706_PROC_NDIV_MODE_MASK		0x00000007
++#define PMU6_4706_PROC_NDIV_MODE_SHIFT	0
++
++#define PMU7_PLL_PLLCTL7                7
++#define PMU7_PLL_CTL7_M4DIV_MASK	0xff000000
++#define PMU7_PLL_CTL7_M4DIV_SHIFT 	24
++#define PMU7_PLL_CTL7_M4DIV_BY_6	6
++#define PMU7_PLL_CTL7_M4DIV_BY_12	0xc
++#define PMU7_PLL_CTL7_M4DIV_BY_24	0x18
++#define PMU7_PLL_PLLCTL8                8
++#define PMU7_PLL_CTL8_M5DIV_MASK	0x000000ff
++#define PMU7_PLL_CTL8_M5DIV_SHIFT	0
++#define PMU7_PLL_CTL8_M5DIV_BY_8	8
++#define PMU7_PLL_CTL8_M5DIV_BY_12	0xc
++#define PMU7_PLL_CTL8_M5DIV_BY_24	0x18
++#define PMU7_PLL_CTL8_M6DIV_MASK	0x0000ff00
++#define PMU7_PLL_CTL8_M6DIV_SHIFT	8
++#define PMU7_PLL_CTL8_M6DIV_BY_12	0xc
++#define PMU7_PLL_CTL8_M6DIV_BY_24	0x18
++#define PMU7_PLL_PLLCTL11		11
++#define PMU7_PLL_PLLCTL11_MASK		0xffffff00
++#define PMU7_PLL_PLLCTL11_VAL		0x22222200
++
++/* PMU rev 15 */
++#define PMU15_PLL_PLLCTL0		0
++#define PMU15_PLL_PC0_CLKSEL_MASK	0x00000003
++#define PMU15_PLL_PC0_CLKSEL_SHIFT	0
++#define PMU15_PLL_PC0_FREQTGT_MASK	0x003FFFFC
++#define PMU15_PLL_PC0_FREQTGT_SHIFT	2
++#define PMU15_PLL_PC0_PRESCALE_MASK	0x00C00000
++#define PMU15_PLL_PC0_PRESCALE_SHIFT	22
++#define PMU15_PLL_PC0_KPCTRL_MASK	0x07000000
++#define PMU15_PLL_PC0_KPCTRL_SHIFT	24
++#define PMU15_PLL_PC0_FCNTCTRL_MASK	0x38000000
++#define PMU15_PLL_PC0_FCNTCTRL_SHIFT	27
++#define PMU15_PLL_PC0_FDCMODE_MASK	0x40000000
++#define PMU15_PLL_PC0_FDCMODE_SHIFT	30
++#define PMU15_PLL_PC0_CTRLBIAS_MASK	0x80000000
++#define PMU15_PLL_PC0_CTRLBIAS_SHIFT	31
++
++#define PMU15_PLL_PLLCTL1			1
++#define PMU15_PLL_PC1_BIAS_CTLM_MASK		0x00000060
++#define PMU15_PLL_PC1_BIAS_CTLM_SHIFT		5
++#define PMU15_PLL_PC1_BIAS_CTLM_RST_MASK	0x00000040
++#define PMU15_PLL_PC1_BIAS_CTLM_RST_SHIFT	6
++#define PMU15_PLL_PC1_BIAS_SS_DIVR_MASK		0x0001FF80
++#define PMU15_PLL_PC1_BIAS_SS_DIVR_SHIFT	7
++#define PMU15_PLL_PC1_BIAS_SS_RSTVAL_MASK	0x03FE0000
++#define PMU15_PLL_PC1_BIAS_SS_RSTVAL_SHIFT	17
++#define PMU15_PLL_PC1_BIAS_INTG_BW_MASK		0x0C000000
++#define PMU15_PLL_PC1_BIAS_INTG_BW_SHIFT	26
++#define PMU15_PLL_PC1_BIAS_INTG_BYP_MASK	0x10000000
++#define PMU15_PLL_PC1_BIAS_INTG_BYP_SHIFT	28
++#define PMU15_PLL_PC1_OPENLP_EN_MASK		0x40000000
++#define PMU15_PLL_PC1_OPENLP_EN_SHIFT		30
++
++#define PMU15_PLL_PLLCTL2			2
++#define PMU15_PLL_PC2_CTEN_MASK			0x00000001
++#define PMU15_PLL_PC2_CTEN_SHIFT		0
++
++#define PMU15_PLL_PLLCTL3			3
++#define PMU15_PLL_PC3_DITHER_EN_MASK		0x00000001
++#define PMU15_PLL_PC3_DITHER_EN_SHIFT		0
++#define PMU15_PLL_PC3_DCOCTLSP_MASK		0xFE000000
++#define PMU15_PLL_PC3_DCOCTLSP_SHIFT		25
++#define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_MASK	0x01
++#define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_SHIFT	0
++#define PMU15_PLL_PC3_DCOCTLSP_CH0EN_MASK	0x02
++#define PMU15_PLL_PC3_DCOCTLSP_CH0EN_SHIFT	1
++#define PMU15_PLL_PC3_DCOCTLSP_CH1EN_MASK	0x04
++#define PMU15_PLL_PC3_DCOCTLSP_CH1EN_SHIFT	2
++#define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_MASK	0x18
++#define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_SHIFT	3
++#define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_MASK	0x60
++#define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_SHIFT	5
++#define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV1	0
++#define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV2	1
++#define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV3	2
++#define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV5	3
++
++#define PMU15_PLL_PLLCTL4			4
++#define PMU15_PLL_PC4_FLLCLK1_DIV_MASK		0x00000007
++#define PMU15_PLL_PC4_FLLCLK1_DIV_SHIFT		0
++#define PMU15_PLL_PC4_FLLCLK2_DIV_MASK		0x00000038
++#define PMU15_PLL_PC4_FLLCLK2_DIV_SHIFT		3
++#define PMU15_PLL_PC4_FLLCLK3_DIV_MASK		0x000001C0
++#define PMU15_PLL_PC4_FLLCLK3_DIV_SHIFT		6
++#define PMU15_PLL_PC4_DBGMODE_MASK		0x00000E00
++#define PMU15_PLL_PC4_DBGMODE_SHIFT		9
++#define PMU15_PLL_PC4_FLL480_CTLSP_LK_MASK	0x00001000
++#define PMU15_PLL_PC4_FLL480_CTLSP_LK_SHIFT	12
++#define PMU15_PLL_PC4_FLL480_CTLSP_MASK		0x000FE000
++#define PMU15_PLL_PC4_FLL480_CTLSP_SHIFT	13
++#define PMU15_PLL_PC4_DINPOL_MASK		0x00100000
++#define PMU15_PLL_PC4_DINPOL_SHIFT		20
++#define PMU15_PLL_PC4_CLKOUT_PD_MASK		0x00200000
++#define PMU15_PLL_PC4_CLKOUT_PD_SHIFT		21
++#define PMU15_PLL_PC4_CLKDIV2_PD_MASK		0x00400000
++#define PMU15_PLL_PC4_CLKDIV2_PD_SHIFT		22
++#define PMU15_PLL_PC4_CLKDIV4_PD_MASK		0x00800000
++#define PMU15_PLL_PC4_CLKDIV4_PD_SHIFT		23
++#define PMU15_PLL_PC4_CLKDIV8_PD_MASK		0x01000000
++#define PMU15_PLL_PC4_CLKDIV8_PD_SHIFT		24
++#define PMU15_PLL_PC4_CLKDIV16_PD_MASK		0x02000000
++#define PMU15_PLL_PC4_CLKDIV16_PD_SHIFT		25
++#define PMU15_PLL_PC4_TEST_EN_MASK		0x04000000
++#define PMU15_PLL_PC4_TEST_EN_SHIFT		26
++
++#define PMU15_PLL_PLLCTL5			5
++#define PMU15_PLL_PC5_FREQTGT_MASK		0x000FFFFF
++#define PMU15_PLL_PC5_FREQTGT_SHIFT		0
++#define PMU15_PLL_PC5_DCOCTLSP_MASK		0x07F00000
++#define PMU15_PLL_PC5_DCOCTLSP_SHIFT		20
++#define PMU15_PLL_PC5_PRESCALE_MASK		0x18000000
++#define PMU15_PLL_PC5_PRESCALE_SHIFT		27
++
++#define PMU15_PLL_PLLCTL6		6
++#define PMU15_PLL_PC6_FREQTGT_MASK	0x000FFFFF
++#define PMU15_PLL_PC6_FREQTGT_SHIFT	0
++#define PMU15_PLL_PC6_DCOCTLSP_MASK	0x07F00000
++#define PMU15_PLL_PC6_DCOCTLSP_SHIFT	20
++#define PMU15_PLL_PC6_PRESCALE_MASK	0x18000000
++#define PMU15_PLL_PC6_PRESCALE_SHIFT	27
++
++#define PMU15_FREQTGT_480_DEFAULT	0x19AB1
++#define PMU15_FREQTGT_492_DEFAULT	0x1A4F5
++#define PMU15_ARM_96MHZ			96000000	/**< 96 Mhz */
++#define PMU15_ARM_98MHZ			98400000	/**< 98.4 Mhz */
++#define PMU15_ARM_97MHZ			97000000	/**< 97 Mhz */
++
++
++#define PMU17_PLLCTL2_NDIVTYPE_MASK		0x00000070
++#define PMU17_PLLCTL2_NDIVTYPE_SHIFT		4
++
++#define PMU17_PLLCTL2_NDIV_MODE_INT		0
++#define PMU17_PLLCTL2_NDIV_MODE_INT1B8		1
++#define PMU17_PLLCTL2_NDIV_MODE_MASH111		2
++#define PMU17_PLLCTL2_NDIV_MODE_MASH111B8	3
++
++#define PMU17_PLLCTL0_BBPLL_PWRDWN		0
++#define PMU17_PLLCTL0_BBPLL_DRST		3
++#define PMU17_PLLCTL0_BBPLL_DISBL_CLK		8
++
++/* PLL usage in 4716/47162 */
++#define	PMU4716_MAINPLL_PLL0		12
++
++/* PLL usage in 4335 */
++#define PMU4335_PLL0_PC2_P1DIV_MASK			0x000f0000
++#define PMU4335_PLL0_PC2_P1DIV_SHIFT		16
++#define PMU4335_PLL0_PC2_NDIV_INT_MASK		0xff800000
++#define PMU4335_PLL0_PC2_NDIV_INT_SHIFT		23
++#define PMU4335_PLL0_PC1_MDIV2_MASK			0x0000ff00
++#define PMU4335_PLL0_PC1_MDIV2_SHIFT		8
++
++/* PLL usage in 4347 */
++#define PMU4347_PLL0_PC2_P1DIV_MASK		0x000f0000
++#define PMU4347_PLL0_PC2_P1DIV_SHIFT		16
++#define PMU4347_PLL0_PC2_NDIV_INT_MASK		0x3ff00000
++#define PMU4347_PLL0_PC2_NDIV_INT_SHIFT		20
++#define PMU4347_PLL0_PC3_NDIV_FRAC_MASK		0x000fffff
++#define PMU4347_PLL0_PC3_NDIV_FRAC_SHIFT		0
++#define PMU4347_PLL1_PC5_P1DIV_MASK		0xc0000000
++#define PMU4347_PLL1_PC5_P1DIV_SHIFT		30
++#define PMU4347_PLL1_PC6_P1DIV_MASK		0x00000003
++#define PMU4347_PLL1_PC6_P1DIV_SHIFT		0
++#define PMU4347_PLL1_PC6_NDIV_INT_MASK		0x00000ffc
++#define PMU4347_PLL1_PC6_NDIV_INT_SHIFT		2
++#define PMU4347_PLL1_PC6_NDIV_FRAC_MASK		0xfffff000
++#define PMU4347_PLL1_PC6_NDIV_FRAC_SHIFT	12
++
++/* PLL usage in 5356/5357 */
++#define	PMU5356_MAINPLL_PLL0		0
++#define	PMU5357_MAINPLL_PLL0		0
++
++/* 4716/47162 resources */
++#define RES4716_PROC_PLL_ON		0x00000040
++#define RES4716_PROC_HT_AVAIL		0x00000080
++
++/* 4716/4717/4718 Chip specific ChipControl register bits */
++#define CCTRL_471X_I2S_PINS_ENABLE	0x0080 /* I2S pins off by default, shared w/ pflash */
++
++/* 5357 Chip specific ChipControl register bits */
++/* 2nd - 32-bit reg */
++#define CCTRL_5357_I2S_PINS_ENABLE	0x00040000 /* I2S pins enable */
++#define CCTRL_5357_I2CSPI_PINS_ENABLE	0x00080000 /* I2C/SPI pins enable */
++
++/* 5354 resources */
++#define RES5354_EXT_SWITCHER_PWM	0	/**< 0x00001 */
++#define RES5354_BB_SWITCHER_PWM		1	/**< 0x00002 */
++#define RES5354_BB_SWITCHER_BURST	2	/**< 0x00004 */
++#define RES5354_BB_EXT_SWITCHER_BURST	3	/**< 0x00008 */
++#define RES5354_ILP_REQUEST		4	/**< 0x00010 */
++#define RES5354_RADIO_SWITCHER_PWM	5	/**< 0x00020 */
++#define RES5354_RADIO_SWITCHER_BURST	6	/**< 0x00040 */
++#define RES5354_ROM_SWITCH		7	/**< 0x00080 */
++#define RES5354_PA_REF_LDO		8	/**< 0x00100 */
++#define RES5354_RADIO_LDO		9	/**< 0x00200 */
++#define RES5354_AFE_LDO			10	/**< 0x00400 */
++#define RES5354_PLL_LDO			11	/**< 0x00800 */
++#define RES5354_BG_FILTBYP		12	/**< 0x01000 */
++#define RES5354_TX_FILTBYP		13	/**< 0x02000 */
++#define RES5354_RX_FILTBYP		14	/**< 0x04000 */
++#define RES5354_XTAL_PU			15	/**< 0x08000 */
++#define RES5354_XTAL_EN			16	/**< 0x10000 */
++#define RES5354_BB_PLL_FILTBYP		17	/**< 0x20000 */
++#define RES5354_RF_PLL_FILTBYP		18	/**< 0x40000 */
++#define RES5354_BB_PLL_PU		19	/**< 0x80000 */
++
++/* 5357 Chip specific ChipControl register bits */
++#define CCTRL5357_EXTPA                 (1<<14) /* extPA in ChipControl 1, bit 14 */
++#define CCTRL5357_ANT_MUX_2o3		(1<<15) /* 2o3 in ChipControl 1, bit 15 */
++#define CCTRL5357_NFLASH		(1<<16) /* Nandflash in ChipControl 1, bit 16 */
++
++/* 43217 Chip specific ChipControl register bits */
++#define CCTRL43217_EXTPA_C0             (1<<13) /* core0 extPA in ChipControl 1, bit 13 */
++#define CCTRL43217_EXTPA_C1             (1<<8)  /* core1 extPA in ChipControl 1, bit 8 */
++
++/* 43228 Chip specific ChipControl register bits */
++#define CCTRL43228_EXTPA_C0             (1<<14) /* core1 extPA in ChipControl 1, bit 14 */
++#define CCTRL43228_EXTPA_C1             (1<<9)  /* core0 extPA in ChipControl 1, bit 1 */
++
++/* 4328 resources */
++#define RES4328_EXT_SWITCHER_PWM	0	/**< 0x00001 */
++#define RES4328_BB_SWITCHER_PWM		1	/**< 0x00002 */
++#define RES4328_BB_SWITCHER_BURST	2	/**< 0x00004 */
++#define RES4328_BB_EXT_SWITCHER_BURST	3	/**< 0x00008 */
++#define RES4328_ILP_REQUEST		4	/**< 0x00010 */
++#define RES4328_RADIO_SWITCHER_PWM	5	/**< 0x00020 */
++#define RES4328_RADIO_SWITCHER_BURST	6	/**< 0x00040 */
++#define RES4328_ROM_SWITCH		7	/**< 0x00080 */
++#define RES4328_PA_REF_LDO		8	/**< 0x00100 */
++#define RES4328_RADIO_LDO		9	/**< 0x00200 */
++#define RES4328_AFE_LDO			10	/**< 0x00400 */
++#define RES4328_PLL_LDO			11	/**< 0x00800 */
++#define RES4328_BG_FILTBYP		12	/**< 0x01000 */
++#define RES4328_TX_FILTBYP		13	/**< 0x02000 */
++#define RES4328_RX_FILTBYP		14	/**< 0x04000 */
++#define RES4328_XTAL_PU			15	/**< 0x08000 */
++#define RES4328_XTAL_EN			16	/**< 0x10000 */
++#define RES4328_BB_PLL_FILTBYP		17	/**< 0x20000 */
++#define RES4328_RF_PLL_FILTBYP		18	/**< 0x40000 */
++#define RES4328_BB_PLL_PU		19	/**< 0x80000 */
++
++/* 4325 A0/A1 resources */
++#define RES4325_BUCK_BOOST_BURST	0	/**< 0x00000001 */
++#define RES4325_CBUCK_BURST		1	/**< 0x00000002 */
++#define RES4325_CBUCK_PWM		2	/**< 0x00000004 */
++#define RES4325_CLDO_CBUCK_BURST	3	/**< 0x00000008 */
++#define RES4325_CLDO_CBUCK_PWM		4	/**< 0x00000010 */
++#define RES4325_BUCK_BOOST_PWM		5	/**< 0x00000020 */
++#define RES4325_ILP_REQUEST		6	/**< 0x00000040 */
++#define RES4325_ABUCK_BURST		7	/**< 0x00000080 */
++#define RES4325_ABUCK_PWM		8	/**< 0x00000100 */
++#define RES4325_LNLDO1_PU		9	/**< 0x00000200 */
++#define RES4325_OTP_PU			10	/**< 0x00000400 */
++#define RES4325_LNLDO3_PU		11	/**< 0x00000800 */
++#define RES4325_LNLDO4_PU		12	/**< 0x00001000 */
++#define RES4325_XTAL_PU			13	/**< 0x00002000 */
++#define RES4325_ALP_AVAIL		14	/**< 0x00004000 */
++#define RES4325_RX_PWRSW_PU		15	/**< 0x00008000 */
++#define RES4325_TX_PWRSW_PU		16	/**< 0x00010000 */
++#define RES4325_RFPLL_PWRSW_PU		17	/**< 0x00020000 */
++#define RES4325_LOGEN_PWRSW_PU		18	/**< 0x00040000 */
++#define RES4325_AFE_PWRSW_PU		19	/**< 0x00080000 */
++#define RES4325_BBPLL_PWRSW_PU		20	/**< 0x00100000 */
++#define RES4325_HT_AVAIL		21	/**< 0x00200000 */
++
++/* 4325 B0/C0 resources */
++#define RES4325B0_CBUCK_LPOM		1	/**< 0x00000002 */
++#define RES4325B0_CBUCK_BURST		2	/**< 0x00000004 */
++#define RES4325B0_CBUCK_PWM		3	/**< 0x00000008 */
++#define RES4325B0_CLDO_PU		4	/**< 0x00000010 */
++
++/* 4325 C1 resources */
++#define RES4325C1_LNLDO2_PU		12	/**< 0x00001000 */
++
++/* 4325 chip-specific ChipStatus register bits */
++#define CST4325_SPROM_OTP_SEL_MASK	0x00000003
++#define CST4325_DEFCIS_SEL		0	/**< OTP is powered up, use def. CIS, no SPROM */
++#define CST4325_SPROM_SEL		1	/**< OTP is powered up, SPROM is present */
++#define CST4325_OTP_SEL			2	/**< OTP is powered up, no SPROM */
++#define CST4325_OTP_PWRDN		3	/**< OTP is powered down, SPROM is present */
++#define CST4325_SDIO_USB_MODE_MASK	0x00000004
++#define CST4325_SDIO_USB_MODE_SHIFT	2
++#define CST4325_RCAL_VALID_MASK		0x00000008
++#define CST4325_RCAL_VALID_SHIFT	3
++#define CST4325_RCAL_VALUE_MASK		0x000001f0
++#define CST4325_RCAL_VALUE_SHIFT	4
++#define CST4325_PMUTOP_2B_MASK 		0x00000200	/**< 1 for 2b, 0 for to 2a */
++#define CST4325_PMUTOP_2B_SHIFT   	9
++
++#define RES4329_RESERVED0		0	/**< 0x00000001 */
++#define RES4329_CBUCK_LPOM		1	/**< 0x00000002 */
++#define RES4329_CBUCK_BURST		2	/**< 0x00000004 */
++#define RES4329_CBUCK_PWM		3	/**< 0x00000008 */
++#define RES4329_CLDO_PU			4	/**< 0x00000010 */
++#define RES4329_PALDO_PU		5	/**< 0x00000020 */
++#define RES4329_ILP_REQUEST		6	/**< 0x00000040 */
++#define RES4329_RESERVED7		7	/**< 0x00000080 */
++#define RES4329_RESERVED8		8	/**< 0x00000100 */
++#define RES4329_LNLDO1_PU		9	/**< 0x00000200 */
++#define RES4329_OTP_PU			10	/**< 0x00000400 */
++#define RES4329_RESERVED11		11	/**< 0x00000800 */
++#define RES4329_LNLDO2_PU		12	/**< 0x00001000 */
++#define RES4329_XTAL_PU			13	/**< 0x00002000 */
++#define RES4329_ALP_AVAIL		14	/**< 0x00004000 */
++#define RES4329_RX_PWRSW_PU		15	/**< 0x00008000 */
++#define RES4329_TX_PWRSW_PU		16	/**< 0x00010000 */
++#define RES4329_RFPLL_PWRSW_PU		17	/**< 0x00020000 */
++#define RES4329_LOGEN_PWRSW_PU		18	/**< 0x00040000 */
++#define RES4329_AFE_PWRSW_PU		19	/**< 0x00080000 */
++#define RES4329_BBPLL_PWRSW_PU		20	/**< 0x00100000 */
++#define RES4329_HT_AVAIL		21	/**< 0x00200000 */
++
++#define CST4329_SPROM_OTP_SEL_MASK	0x00000003
++#define CST4329_DEFCIS_SEL		0	/**< OTP is powered up, use def. CIS, no SPROM */
++#define CST4329_SPROM_SEL		1	/**< OTP is powered up, SPROM is present */
++#define CST4329_OTP_SEL			2	/**< OTP is powered up, no SPROM */
++#define CST4329_OTP_PWRDN		3	/**< OTP is powered down, SPROM is present */
++#define CST4329_SPI_SDIO_MODE_MASK	0x00000004
++#define CST4329_SPI_SDIO_MODE_SHIFT	2
++
++/* 4312 chip-specific ChipStatus register bits */
++#define CST4312_SPROM_OTP_SEL_MASK	0x00000003
++#define CST4312_DEFCIS_SEL		0	/**< OTP is powered up, use def. CIS, no SPROM */
++#define CST4312_SPROM_SEL		1	/**< OTP is powered up, SPROM is present */
++#define CST4312_OTP_SEL			2	/**< OTP is powered up, no SPROM */
++#define CST4312_OTP_BAD			3	/**< OTP is broken, SPROM is present */
++
++/* 4312 resources (all PMU chips with little memory constraint) */
++#define RES4312_SWITCHER_BURST		0	/**< 0x00000001 */
++#define RES4312_SWITCHER_PWM    	1	/**< 0x00000002 */
++#define RES4312_PA_REF_LDO		2	/**< 0x00000004 */
++#define RES4312_CORE_LDO_BURST		3	/**< 0x00000008 */
++#define RES4312_CORE_LDO_PWM		4	/**< 0x00000010 */
++#define RES4312_RADIO_LDO		5	/**< 0x00000020 */
++#define RES4312_ILP_REQUEST		6	/**< 0x00000040 */
++#define RES4312_BG_FILTBYP		7	/**< 0x00000080 */
++#define RES4312_TX_FILTBYP		8	/**< 0x00000100 */
++#define RES4312_RX_FILTBYP		9	/**< 0x00000200 */
++#define RES4312_XTAL_PU			10	/**< 0x00000400 */
++#define RES4312_ALP_AVAIL		11	/**< 0x00000800 */
++#define RES4312_BB_PLL_FILTBYP		12	/**< 0x00001000 */
++#define RES4312_RF_PLL_FILTBYP		13	/**< 0x00002000 */
++#define RES4312_HT_AVAIL		14	/**< 0x00004000 */
++
++/* 4322 resources */
++#define RES4322_RF_LDO			0
++#define RES4322_ILP_REQUEST		1
++#define RES4322_XTAL_PU			2
++#define RES4322_ALP_AVAIL		3
++#define RES4322_SI_PLL_ON		4
++#define RES4322_HT_SI_AVAIL		5
++#define RES4322_PHY_PLL_ON		6
++#define RES4322_HT_PHY_AVAIL		7
++#define RES4322_OTP_PU			8
++
++/* 4322 chip-specific ChipStatus register bits */
++#define CST4322_XTAL_FREQ_20_40MHZ	0x00000020
++#define CST4322_SPROM_OTP_SEL_MASK	0x000000c0
++#define CST4322_SPROM_OTP_SEL_SHIFT	6
++#define CST4322_NO_SPROM_OTP		0	/**< no OTP, no SPROM */
++#define CST4322_SPROM_PRESENT		1	/**< SPROM is present */
++#define CST4322_OTP_PRESENT		2	/**< OTP is present */
++#define CST4322_PCI_OR_USB		0x00000100
++#define CST4322_BOOT_MASK		0x00000600
++#define CST4322_BOOT_SHIFT		9
++#define CST4322_BOOT_FROM_SRAM		0	/**< boot from SRAM, ARM in reset */
++#define CST4322_BOOT_FROM_ROM		1	/**< boot from ROM */
++#define CST4322_BOOT_FROM_FLASH		2	/**< boot from FLASH */
++#define CST4322_BOOT_FROM_INVALID	3
++#define CST4322_ILP_DIV_EN		0x00000800
++#define CST4322_FLASH_TYPE_MASK		0x00001000
++#define CST4322_FLASH_TYPE_SHIFT	12
++#define CST4322_FLASH_TYPE_SHIFT_ST	0	/**< ST serial FLASH */
++#define CST4322_FLASH_TYPE_SHIFT_ATMEL	1	/**< ATMEL flash */
++#define CST4322_ARM_TAP_SEL		0x00002000
++#define CST4322_RES_INIT_MODE_MASK	0x0000c000
++#define CST4322_RES_INIT_MODE_SHIFT	14
++#define CST4322_RES_INIT_MODE_ILPAVAIL	0	/**< resinitmode: ILP available */
++#define CST4322_RES_INIT_MODE_ILPREQ	1	/**< resinitmode: ILP request */
++#define CST4322_RES_INIT_MODE_ALPAVAIL	2	/**< resinitmode: ALP available */
++#define CST4322_RES_INIT_MODE_HTAVAIL	3	/**< resinitmode: HT available */
++#define CST4322_PCIPLLCLK_GATING	0x00010000
++#define CST4322_CLK_SWITCH_PCI_TO_ALP	0x00020000
++#define CST4322_PCI_CARDBUS_MODE	0x00040000
++
++/* 43224 chip-specific ChipControl register bits */
++#define CCTRL43224_GPIO_TOGGLE          0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */
++#define CCTRL_43224A0_12MA_LED_DRIVE    0x00F000F0 /* 12 mA drive strength */
++#define CCTRL_43224B0_12MA_LED_DRIVE    0xF0    /* 12 mA drive strength for later 43224s */
++
++/* 43236 resources */
++#define RES43236_REGULATOR		0
++#define RES43236_ILP_REQUEST		1
++#define RES43236_XTAL_PU		2
++#define RES43236_ALP_AVAIL		3
++#define RES43236_SI_PLL_ON		4
++#define RES43236_HT_SI_AVAIL		5
++
++/* 43236 chip-specific ChipControl register bits */
++#define CCTRL43236_BT_COEXIST		(1<<0)	/**< 0 disable */
++#define CCTRL43236_SECI			(1<<1)	/**< 0 SECI is disabled (JATG functional) */
++#define CCTRL43236_EXT_LNA		(1<<2)	/**< 0 disable */
++#define CCTRL43236_ANT_MUX_2o3          (1<<3)	/**< 2o3 mux, chipcontrol bit 3 */
++#define CCTRL43236_GSIO			(1<<4)	/**< 0 disable */
++
++/* 43236 Chip specific ChipStatus register bits */
++#define CST43236_SFLASH_MASK		0x00000040
++#define CST43236_OTP_SEL_MASK		0x00000080
++#define CST43236_OTP_SEL_SHIFT		7
++#define CST43236_HSIC_MASK		0x00000100	/**< USB/HSIC */
++#define CST43236_BP_CLK			0x00000200	/**< 120/96Mbps */
++#define CST43236_BOOT_MASK		0x00001800
++#define CST43236_BOOT_SHIFT		11
++#define CST43236_BOOT_FROM_SRAM		0	/**< boot from SRAM, ARM in reset */
++#define CST43236_BOOT_FROM_ROM		1	/**< boot from ROM */
++#define CST43236_BOOT_FROM_FLASH	2	/**< boot from FLASH */
++#define CST43236_BOOT_FROM_INVALID	3
++
++/* 43237 resources */
++#define RES43237_REGULATOR		0
++#define RES43237_ILP_REQUEST		1
++#define RES43237_XTAL_PU		2
++#define RES43237_ALP_AVAIL		3
++#define RES43237_SI_PLL_ON		4
++#define RES43237_HT_SI_AVAIL		5
++
++/* 43237 chip-specific ChipControl register bits */
++#define CCTRL43237_BT_COEXIST		(1<<0)	/**< 0 disable */
++#define CCTRL43237_SECI			(1<<1)	/**< 0 SECI is disabled (JATG functional) */
++#define CCTRL43237_EXT_LNA		(1<<2)	/**< 0 disable */
++#define CCTRL43237_ANT_MUX_2o3          (1<<3)	/**< 2o3 mux, chipcontrol bit 3 */
++#define CCTRL43237_GSIO			(1<<4)	/**< 0 disable */
++
++/* 43237 Chip specific ChipStatus register bits */
++#define CST43237_SFLASH_MASK		0x00000040
++#define CST43237_OTP_SEL_MASK		0x00000080
++#define CST43237_OTP_SEL_SHIFT		7
++#define CST43237_HSIC_MASK		0x00000100	/**< USB/HSIC */
++#define CST43237_BP_CLK			0x00000200	/**< 120/96Mbps */
++#define CST43237_BOOT_MASK		0x00001800
++#define CST43237_BOOT_SHIFT		11
++#define CST43237_BOOT_FROM_SRAM		0	/**< boot from SRAM, ARM in reset */
++#define CST43237_BOOT_FROM_ROM		1	/**< boot from ROM */
++#define CST43237_BOOT_FROM_FLASH	2	/**< boot from FLASH */
++#define CST43237_BOOT_FROM_INVALID	3
++
++/* 43239 resources */
++#define RES43239_OTP_PU			9
++#define RES43239_MACPHY_CLKAVAIL	23
++#define RES43239_HT_AVAIL		24
++
++/* 43239 Chip specific ChipStatus register bits */
++#define CST43239_SPROM_MASK			0x00000002
++#define CST43239_SFLASH_MASK		0x00000004
++#define	CST43239_RES_INIT_MODE_SHIFT	7
++#define	CST43239_RES_INIT_MODE_MASK		0x000001f0
++#define CST43239_CHIPMODE_SDIOD(cs)	((cs) & (1 << 15))	/**< SDIO || gSPI */
++#define CST43239_CHIPMODE_USB20D(cs)	(~(cs) & (1 << 15))	/**< USB || USBDA */
++#define CST43239_CHIPMODE_SDIO(cs)	(((cs) & (1 << 0)) == 0)	/**< SDIO */
++#define CST43239_CHIPMODE_GSPI(cs)	(((cs) & (1 << 0)) == (1 << 0))	/**< gSPI */
++
++/* 4324 resources */
++/* 43242 use same PMU as 4324 */
++#define RES4324_LPLDO_PU			0
++#define RES4324_RESET_PULLDN_DIS		1
++#define RES4324_PMU_BG_PU			2
++#define RES4324_HSIC_LDO_PU			3
++#define RES4324_CBUCK_LPOM_PU			4
++#define RES4324_CBUCK_PFM_PU			5
++#define RES4324_CLDO_PU				6
++#define RES4324_LPLDO2_LVM			7
++#define RES4324_LNLDO1_PU			8
++#define RES4324_LNLDO2_PU			9
++#define RES4324_LDO3P3_PU			10
++#define RES4324_OTP_PU				11
++#define RES4324_XTAL_PU				12
++#define RES4324_BBPLL_PU			13
++#define RES4324_LQ_AVAIL			14
++#define RES4324_WL_CORE_READY			17
++#define RES4324_ILP_REQ				18
++#define RES4324_ALP_AVAIL			19
++#define RES4324_PALDO_PU			20
++#define RES4324_RADIO_PU			21
++#define RES4324_SR_CLK_STABLE			22
++#define RES4324_SR_SAVE_RESTORE			23
++#define RES4324_SR_PHY_PWRSW			24
++#define RES4324_SR_PHY_PIC			25
++#define RES4324_SR_SUBCORE_PWRSW		26
++#define RES4324_SR_SUBCORE_PIC			27
++#define RES4324_SR_MEM_PM0			28
++#define RES4324_HT_AVAIL			29
++#define RES4324_MACPHY_CLKAVAIL			30
++
++/* 4324 Chip specific ChipStatus register bits */
++#define CST4324_SPROM_MASK			0x00000080
++#define CST4324_SFLASH_MASK			0x00400000
++#define	CST4324_RES_INIT_MODE_SHIFT	10
++#define	CST4324_RES_INIT_MODE_MASK	0x00000c00
++#define CST4324_CHIPMODE_MASK		0x7
++#define CST4324_CHIPMODE_SDIOD(cs)	((~(cs)) & (1 << 2))	/**< SDIO || gSPI */
++#define CST4324_CHIPMODE_USB20D(cs)	(((cs) & CST4324_CHIPMODE_MASK) == 0x6)	/**< USB || USBDA */
++
++/* 43242 Chip specific ChipStatus register bits */
++#define CST43242_SFLASH_MASK                    0x00000008
++#define CST43242_SR_HALT			(1<<25)
++#define CST43242_SR_CHIP_STATUS_2		27 /* bit 27 */
++
++/* 4331 resources */
++#define RES4331_REGULATOR		0
++#define RES4331_ILP_REQUEST		1
++#define RES4331_XTAL_PU			2
++#define RES4331_ALP_AVAIL		3
++#define RES4331_SI_PLL_ON		4
++#define RES4331_HT_SI_AVAIL		5
++
++/* 4331 chip-specific ChipControl register bits */
++#define CCTRL4331_BT_COEXIST		(1<<0)	/**< 0 disable */
++#define CCTRL4331_SECI			(1<<1)	/**< 0 SECI is disabled (JATG functional) */
++#define CCTRL4331_EXT_LNA_G		(1<<2)	/**< 0 disable */
++#define CCTRL4331_SPROM_GPIO13_15       (1<<3)	/**< sprom/gpio13-15 mux */
++#define CCTRL4331_EXTPA_EN		(1<<4)	/**< 0 ext pa disable, 1 ext pa enabled */
++#define CCTRL4331_GPIOCLK_ON_SPROMCS	(1<<5)	/**< set drive out GPIO_CLK on sprom_cs pin */
++#define CCTRL4331_PCIE_MDIO_ON_SPROMCS	(1<<6)	/**< use sprom_cs pin as PCIE mdio interface */
++#define CCTRL4331_EXTPA_ON_GPIO2_5	(1<<7)	/* aband extpa will be at gpio2/5 and sprom_dout */
++#define CCTRL4331_OVR_PIPEAUXCLKEN	(1<<8)	/**< override core control on pipe_AuxClkEnable */
++#define CCTRL4331_OVR_PIPEAUXPWRDOWN	(1<<9)	/**< override core control on pipe_AuxPowerDown */
++#define CCTRL4331_PCIE_AUXCLKEN		(1<<10)	/**< pcie_auxclkenable */
++#define CCTRL4331_PCIE_PIPE_PLLDOWN	(1<<11)	/**< pcie_pipe_pllpowerdown */
++#define CCTRL4331_EXTPA_EN2		(1<<12)	/**< 0 ext pa disable, 1 ext pa enabled */
++#define CCTRL4331_EXT_LNA_A		(1<<13)	/**< 0 disable */
++#define CCTRL4331_BT_SHD0_ON_GPIO4	(1<<16)	/**< enable bt_shd0 at gpio4 */
++#define CCTRL4331_BT_SHD1_ON_GPIO5	(1<<17)	/**< enable bt_shd1 at gpio5 */
++#define CCTRL4331_EXTPA_ANA_EN		(1<<24)	/**< 0 ext pa disable, 1 ext pa enabled */
++
++/* 4331 Chip specific ChipStatus register bits */
++#define	CST4331_XTAL_FREQ		0x00000001	/**< crystal frequency 20/40Mhz */
++#define	CST4331_SPROM_OTP_SEL_MASK	0x00000006
++#define	CST4331_SPROM_OTP_SEL_SHIFT	1
++#define	CST4331_SPROM_PRESENT		0x00000002
++#define	CST4331_OTP_PRESENT		0x00000004
++#define	CST4331_LDO_RF			0x00000008
++#define	CST4331_LDO_PAR			0x00000010
++
++/* 4315 resource */
++#define RES4315_CBUCK_LPOM		1	/**< 0x00000002 */
++#define RES4315_CBUCK_BURST		2	/**< 0x00000004 */
++#define RES4315_CBUCK_PWM		3	/**< 0x00000008 */
++#define RES4315_CLDO_PU			4	/**< 0x00000010 */
++#define RES4315_PALDO_PU		5	/**< 0x00000020 */
++#define RES4315_ILP_REQUEST		6	/**< 0x00000040 */
++#define RES4315_LNLDO1_PU		9	/**< 0x00000200 */
++#define RES4315_OTP_PU			10	/**< 0x00000400 */
++#define RES4315_LNLDO2_PU		12	/**< 0x00001000 */
++#define RES4315_XTAL_PU			13	/**< 0x00002000 */
++#define RES4315_ALP_AVAIL		14	/**< 0x00004000 */
++#define RES4315_RX_PWRSW_PU		15	/**< 0x00008000 */
++#define RES4315_TX_PWRSW_PU		16	/**< 0x00010000 */
++#define RES4315_RFPLL_PWRSW_PU		17	/**< 0x00020000 */
++#define RES4315_LOGEN_PWRSW_PU		18	/**< 0x00040000 */
++#define RES4315_AFE_PWRSW_PU		19	/**< 0x00080000 */
++#define RES4315_BBPLL_PWRSW_PU		20	/**< 0x00100000 */
++#define RES4315_HT_AVAIL		21	/**< 0x00200000 */
++
++/* 4315 chip-specific ChipStatus register bits */
++#define CST4315_SPROM_OTP_SEL_MASK	0x00000003	/**< gpio [7:6], SDIO CIS selection */
++#define CST4315_DEFCIS_SEL		0x00000000	/**< use default CIS, OTP is powered up */
++#define CST4315_SPROM_SEL		0x00000001	/**< use SPROM, OTP is powered up */
++#define CST4315_OTP_SEL			0x00000002	/**< use OTP, OTP is powered up */
++#define CST4315_OTP_PWRDN		0x00000003	/**< use SPROM, OTP is powered down */
++#define CST4315_SDIO_MODE		0x00000004	/**< gpio [8], sdio/usb mode */
++#define CST4315_RCAL_VALID		0x00000008
++#define CST4315_RCAL_VALUE_MASK		0x000001f0
++#define CST4315_RCAL_VALUE_SHIFT	4
++#define CST4315_PALDO_EXTPNP		0x00000200 /**< PALDO is configured with external PNP */
++#define CST4315_CBUCK_MODE_MASK		0x00000c00
++#define CST4315_CBUCK_MODE_BURST	0x00000400
++#define CST4315_CBUCK_MODE_LPBURST	0x00000c00
++
++/* 4319 resources */
++#define RES4319_CBUCK_LPOM		1	/**< 0x00000002 */
++#define RES4319_CBUCK_BURST		2	/**< 0x00000004 */
++#define RES4319_CBUCK_PWM		3	/**< 0x00000008 */
++#define RES4319_CLDO_PU			4	/**< 0x00000010 */
++#define RES4319_PALDO_PU		5	/**< 0x00000020 */
++#define RES4319_ILP_REQUEST		6	/**< 0x00000040 */
++#define RES4319_LNLDO1_PU		9	/**< 0x00000200 */
++#define RES4319_OTP_PU			10	/**< 0x00000400 */
++#define RES4319_LNLDO2_PU		12	/**< 0x00001000 */
++#define RES4319_XTAL_PU			13	/**< 0x00002000 */
++#define RES4319_ALP_AVAIL		14	/**< 0x00004000 */
++#define RES4319_RX_PWRSW_PU		15	/**< 0x00008000 */
++#define RES4319_TX_PWRSW_PU		16	/**< 0x00010000 */
++#define RES4319_RFPLL_PWRSW_PU		17	/**< 0x00020000 */
++#define RES4319_LOGEN_PWRSW_PU		18	/**< 0x00040000 */
++#define RES4319_AFE_PWRSW_PU		19	/**< 0x00080000 */
++#define RES4319_BBPLL_PWRSW_PU		20	/**< 0x00100000 */
++#define RES4319_HT_AVAIL		21	/**< 0x00200000 */
++
++/* 4319 chip-specific ChipStatus register bits */
++#define	CST4319_SPI_CPULESSUSB		0x00000001
++#define	CST4319_SPI_CLK_POL		0x00000002
++#define	CST4319_SPI_CLK_PH		0x00000008
++#define	CST4319_SPROM_OTP_SEL_MASK	0x000000c0	/**< gpio [7:6], SDIO CIS selection */
++#define	CST4319_SPROM_OTP_SEL_SHIFT	6
++#define	CST4319_DEFCIS_SEL		0x00000000	/**< use default CIS, OTP is powered up */
++#define	CST4319_SPROM_SEL		0x00000040	/**< use SPROM, OTP is powered up */
++#define	CST4319_OTP_SEL			0x00000080      /* use OTP, OTP is powered up */
++#define	CST4319_OTP_PWRDN		0x000000c0      /* use SPROM, OTP is powered down */
++#define	CST4319_SDIO_USB_MODE		0x00000100	/**< gpio [8], sdio/usb mode */
++#define	CST4319_REMAP_SEL_MASK		0x00000600
++#define	CST4319_ILPDIV_EN		0x00000800
++#define	CST4319_XTAL_PD_POL		0x00001000
++#define	CST4319_LPO_SEL			0x00002000
++#define	CST4319_RES_INIT_MODE		0x0000c000
++#define	CST4319_PALDO_EXTPNP		0x00010000 /**< PALDO is configured with external PNP */
++#define	CST4319_CBUCK_MODE_MASK		0x00060000
++#define CST4319_CBUCK_MODE_BURST	0x00020000
++#define CST4319_CBUCK_MODE_LPBURST	0x00060000
++#define	CST4319_RCAL_VALID		0x01000000
++#define	CST4319_RCAL_VALUE_MASK		0x3e000000
++#define	CST4319_RCAL_VALUE_SHIFT	25
++
++#define PMU1_PLL0_CHIPCTL0		0
++#define PMU1_PLL0_CHIPCTL1		1
++#define PMU1_PLL0_CHIPCTL2		2
++#define CCTL_4319USB_XTAL_SEL_MASK	0x00180000
++#define CCTL_4319USB_XTAL_SEL_SHIFT	19
++#define CCTL_4319USB_48MHZ_PLL_SEL	1
++#define CCTL_4319USB_24MHZ_PLL_SEL	2
++
++/* PMU resources for 4336 */
++#define	RES4336_CBUCK_LPOM		0
++#define	RES4336_CBUCK_BURST		1
++#define	RES4336_CBUCK_LP_PWM		2
++#define	RES4336_CBUCK_PWM		3
++#define	RES4336_CLDO_PU			4
++#define	RES4336_DIS_INT_RESET_PD	5
++#define	RES4336_ILP_REQUEST		6
++#define	RES4336_LNLDO_PU		7
++#define	RES4336_LDO3P3_PU		8
++#define	RES4336_OTP_PU			9
++#define	RES4336_XTAL_PU			10
++#define	RES4336_ALP_AVAIL		11
++#define	RES4336_RADIO_PU		12
++#define	RES4336_BG_PU			13
++#define	RES4336_VREG1p4_PU_PU		14
++#define	RES4336_AFE_PWRSW_PU		15
++#define	RES4336_RX_PWRSW_PU		16
++#define	RES4336_TX_PWRSW_PU		17
++#define	RES4336_BB_PWRSW_PU		18
++#define	RES4336_SYNTH_PWRSW_PU		19
++#define	RES4336_MISC_PWRSW_PU		20
++#define	RES4336_LOGEN_PWRSW_PU		21
++#define	RES4336_BBPLL_PWRSW_PU		22
++#define	RES4336_MACPHY_CLKAVAIL		23
++#define	RES4336_HT_AVAIL		24
++#define	RES4336_RSVD			25
++
++/* 4336 chip-specific ChipStatus register bits */
++#define	CST4336_SPI_MODE_MASK		0x00000001
++#define	CST4336_SPROM_PRESENT		0x00000002
++#define	CST4336_OTP_PRESENT		0x00000004
++#define	CST4336_ARMREMAP_0		0x00000008
++#define	CST4336_ILPDIV_EN_MASK		0x00000010
++#define	CST4336_ILPDIV_EN_SHIFT		4
++#define	CST4336_XTAL_PD_POL_MASK	0x00000020
++#define	CST4336_XTAL_PD_POL_SHIFT	5
++#define	CST4336_LPO_SEL_MASK		0x00000040
++#define	CST4336_LPO_SEL_SHIFT		6
++#define	CST4336_RES_INIT_MODE_MASK	0x00000180
++#define	CST4336_RES_INIT_MODE_SHIFT	7
++#define	CST4336_CBUCK_MODE_MASK		0x00000600
++#define	CST4336_CBUCK_MODE_SHIFT	9
++
++/* 4336 Chip specific PMU ChipControl register bits */
++#define PCTL_4336_SERIAL_ENAB	(1  << 24)
++
++/* 4330 resources */
++#define	RES4330_CBUCK_LPOM		0
++#define	RES4330_CBUCK_BURST		1
++#define	RES4330_CBUCK_LP_PWM		2
++#define	RES4330_CBUCK_PWM		3
++#define	RES4330_CLDO_PU			4
++#define	RES4330_DIS_INT_RESET_PD	5
++#define	RES4330_ILP_REQUEST		6
++#define	RES4330_LNLDO_PU		7
++#define	RES4330_LDO3P3_PU		8
++#define	RES4330_OTP_PU			9
++#define	RES4330_XTAL_PU			10
++#define	RES4330_ALP_AVAIL		11
++#define	RES4330_RADIO_PU		12
++#define	RES4330_BG_PU			13
++#define	RES4330_VREG1p4_PU_PU		14
++#define	RES4330_AFE_PWRSW_PU		15
++#define	RES4330_RX_PWRSW_PU		16
++#define	RES4330_TX_PWRSW_PU		17
++#define	RES4330_BB_PWRSW_PU		18
++#define	RES4330_SYNTH_PWRSW_PU		19
++#define	RES4330_MISC_PWRSW_PU		20
++#define	RES4330_LOGEN_PWRSW_PU		21
++#define	RES4330_BBPLL_PWRSW_PU		22
++#define	RES4330_MACPHY_CLKAVAIL		23
++#define	RES4330_HT_AVAIL		24
++#define	RES4330_5gRX_PWRSW_PU		25
++#define	RES4330_5gTX_PWRSW_PU		26
++#define	RES4330_5g_LOGEN_PWRSW_PU	27
++
++/* 4330 chip-specific ChipStatus register bits */
++#define CST4330_CHIPMODE_SDIOD(cs)	(((cs) & 0x7) < 6)	/**< SDIO || gSPI */
++#define CST4330_CHIPMODE_USB20D(cs)	(((cs) & 0x7) >= 6)	/**< USB || USBDA */
++#define CST4330_CHIPMODE_SDIO(cs)	(((cs) & 0x4) == 0)	/**< SDIO */
++#define CST4330_CHIPMODE_GSPI(cs)	(((cs) & 0x6) == 4)	/**< gSPI */
++#define CST4330_CHIPMODE_USB(cs)	(((cs) & 0x7) == 6)	/**< USB packet-oriented */
++#define CST4330_CHIPMODE_USBDA(cs)	(((cs) & 0x7) == 7)	/**< USB Direct Access */
++#define	CST4330_OTP_PRESENT		0x00000010
++#define	CST4330_LPO_AUTODET_EN		0x00000020
++#define	CST4330_ARMREMAP_0		0x00000040
++#define	CST4330_SPROM_PRESENT		0x00000080	/**< takes priority over OTP if both set */
++#define	CST4330_ILPDIV_EN		0x00000100
++#define	CST4330_LPO_SEL			0x00000200
++#define	CST4330_RES_INIT_MODE_SHIFT	10
++#define	CST4330_RES_INIT_MODE_MASK	0x00000c00
++#define CST4330_CBUCK_MODE_SHIFT	12
++#define CST4330_CBUCK_MODE_MASK		0x00003000
++#define	CST4330_CBUCK_POWER_OK		0x00004000
++#define	CST4330_BB_PLL_LOCKED		0x00008000
++#define SOCDEVRAM_BP_ADDR		0x1E000000
++#define SOCDEVRAM_ARM_ADDR		0x00800000
++
++/* 4330 Chip specific PMU ChipControl register bits */
++#define PCTL_4330_SERIAL_ENAB	(1  << 24)
++
++/* 4330 Chip specific ChipControl register bits */
++#define CCTRL_4330_GPIO_SEL		0x00000001    /* 1=select GPIOs to be muxed out */
++#define CCTRL_4330_ERCX_SEL		0x00000002    /* 1=select ERCX BT coex to be muxed out */
++#define CCTRL_4330_SDIO_HOST_WAKE	0x00000004    /* SDIO: 1=configure GPIO0 for host wake */
++#define CCTRL_4330_JTAG_DISABLE	0x00000008    /* 1=disable JTAG interface on mux'd pins */
++
++#define PMU_VREG0_ADDR				0
++#define PMU_VREG0_I_SR_CNTL_EN_SHIFT		0
++#define PMU_VREG0_DISABLE_PULLD_BT_SHIFT	2
++#define PMU_VREG0_DISABLE_PULLD_WL_SHIFT	3
++#define PMU_VREG0_CBUCKFSW_ADJ_SHIFT		7
++#define PMU_VREG0_CBUCKFSW_ADJ_MASK			0x1F
++#define PMU_VREG0_RAMP_SEL_SHIFT			13
++#define PMU_VREG0_RAMP_SEL_MASK				0x7
++#define PMU_VREG0_VFB_RSEL_SHIFT			17
++#define PMU_VREG0_VFB_RSEL_MASK				3
++
++#define PMU_VREG4_ADDR			4
++
++#define PMU_VREG4_CLDO_PWM_SHIFT	4
++#define PMU_VREG4_CLDO_PWM_MASK		0x7
++
++#define PMU_VREG4_LPLDO1_SHIFT		15
++#define PMU_VREG4_LPLDO1_MASK		0x7
++#define PMU_VREG4_LPLDO1_1p20V		0
++#define PMU_VREG4_LPLDO1_1p15V		1
++#define PMU_VREG4_LPLDO1_1p10V		2
++#define PMU_VREG4_LPLDO1_1p25V		3
++#define PMU_VREG4_LPLDO1_1p05V		4
++#define PMU_VREG4_LPLDO1_1p00V		5
++#define PMU_VREG4_LPLDO1_0p95V		6
++#define PMU_VREG4_LPLDO1_0p90V		7
++
++/* 4350/4345 VREG4 settings */
++#define PMU4350_VREG4_LPLDO1_1p10V	0
++#define PMU4350_VREG4_LPLDO1_1p15V	1
++#define PMU4350_VREG4_LPLDO1_1p21V	2
++#define PMU4350_VREG4_LPLDO1_1p24V	3
++#define PMU4350_VREG4_LPLDO1_0p90V	4
++#define PMU4350_VREG4_LPLDO1_0p96V	5
++#define PMU4350_VREG4_LPLDO1_1p01V	6
++#define PMU4350_VREG4_LPLDO1_1p04V	7
++
++#define PMU_VREG4_LPLDO2_LVM_SHIFT	18
++#define PMU_VREG4_LPLDO2_LVM_MASK	0x7
++#define PMU_VREG4_LPLDO2_HVM_SHIFT	21
++#define PMU_VREG4_LPLDO2_HVM_MASK	0x7
++#define PMU_VREG4_LPLDO2_LVM_HVM_MASK	0x3f
++#define PMU_VREG4_LPLDO2_1p00V		0
++#define PMU_VREG4_LPLDO2_1p15V		1
++#define PMU_VREG4_LPLDO2_1p20V		2
++#define PMU_VREG4_LPLDO2_1p10V		3
++#define PMU_VREG4_LPLDO2_0p90V		4	/**< 4 - 7 is 0.90V */
++
++#define PMU_VREG4_HSICLDO_BYPASS_SHIFT	27
++#define PMU_VREG4_HSICLDO_BYPASS_MASK	0x1
++
++#define PMU_VREG5_ADDR			5
++#define PMU_VREG5_HSICAVDD_PD_SHIFT	6
++#define PMU_VREG5_HSICAVDD_PD_MASK	0x1
++#define PMU_VREG5_HSICDVDD_PD_SHIFT	11
++#define PMU_VREG5_HSICDVDD_PD_MASK	0x1
++
++/* 4334 resources */
++#define RES4334_LPLDO_PU		0
++#define RES4334_RESET_PULLDN_DIS	1
++#define RES4334_PMU_BG_PU		2
++#define RES4334_HSIC_LDO_PU		3
++#define RES4334_CBUCK_LPOM_PU		4
++#define RES4334_CBUCK_PFM_PU		5
++#define RES4334_CLDO_PU			6
++#define RES4334_LPLDO2_LVM		7
++#define RES4334_LNLDO_PU		8
++#define RES4334_LDO3P3_PU		9
++#define RES4334_OTP_PU			10
++#define RES4334_XTAL_PU			11
++#define RES4334_WL_PWRSW_PU		12
++#define RES4334_LQ_AVAIL		13
++#define RES4334_LOGIC_RET		14
++#define RES4334_MEM_SLEEP		15
++#define RES4334_MACPHY_RET		16
++#define RES4334_WL_CORE_READY		17
++#define RES4334_ILP_REQ			18
++#define RES4334_ALP_AVAIL		19
++#define RES4334_MISC_PWRSW_PU		20
++#define RES4334_SYNTH_PWRSW_PU		21
++#define RES4334_RX_PWRSW_PU		22
++#define RES4334_RADIO_PU		23
++#define RES4334_WL_PMU_PU		24
++#define RES4334_VCO_LDO_PU		25
++#define RES4334_AFE_LDO_PU		26
++#define RES4334_RX_LDO_PU		27
++#define RES4334_TX_LDO_PU		28
++#define RES4334_HT_AVAIL		29
++#define RES4334_MACPHY_CLK_AVAIL	30
++
++/* 4334 chip-specific ChipStatus register bits */
++#define CST4334_CHIPMODE_MASK		7
++#define CST4334_SDIO_MODE		0x00000000
++#define CST4334_SPI_MODE		0x00000004
++#define CST4334_HSIC_MODE		0x00000006
++#define CST4334_BLUSB_MODE		0x00000007
++#define CST4334_CHIPMODE_HSIC(cs)	(((cs) & CST4334_CHIPMODE_MASK) == CST4334_HSIC_MODE)
++#define CST4334_OTP_PRESENT		0x00000010
++#define CST4334_LPO_AUTODET_EN		0x00000020
++#define CST4334_ARMREMAP_0		0x00000040
++#define CST4334_SPROM_PRESENT		0x00000080
++#define CST4334_ILPDIV_EN_MASK		0x00000100
++#define CST4334_ILPDIV_EN_SHIFT		8
++#define CST4334_LPO_SEL_MASK		0x00000200
++#define CST4334_LPO_SEL_SHIFT		9
++#define CST4334_RES_INIT_MODE_MASK	0x00000C00
++#define CST4334_RES_INIT_MODE_SHIFT	10
++
++/* 4334 Chip specific PMU ChipControl register bits */
++#define PCTL_4334_GPIO3_ENAB    (1  << 3)
++
++/* 4334 Chip control */
++#define CCTRL4334_PMU_WAKEUP_GPIO1	(1  << 0)
++#define CCTRL4334_PMU_WAKEUP_HSIC	(1  << 1)
++#define CCTRL4334_PMU_WAKEUP_AOS	(1  << 2)
++#define CCTRL4334_HSIC_WAKE_MODE	(1  << 3)
++#define CCTRL4334_HSIC_INBAND_GPIO1	(1  << 4)
++#define CCTRL4334_HSIC_LDO_PU		(1  << 23)
++
++/* 4334 Chip control 3 */
++#define CCTRL4334_BLOCK_EXTRNL_WAKE		(1  << 4)
++#define CCTRL4334_SAVERESTORE_FIX		(1  << 5)
++
++/* 43341 Chip control 3 */
++#define CCTRL43341_BLOCK_EXTRNL_WAKE		(1  << 13)
++#define CCTRL43341_SAVERESTORE_FIX		(1  << 14)
++#define CCTRL43341_BT_ISO_SEL			(1  << 16)
++
++/* 4334 Chip specific ChipControl1 register bits */
++#define CCTRL1_4334_GPIO_SEL		(1 << 0)    /* 1=select GPIOs to be muxed out */
++#define CCTRL1_4334_ERCX_SEL		(1 << 1)    /* 1=select ERCX BT coex to be muxed out */
++#define CCTRL1_4334_SDIO_HOST_WAKE (1 << 2)  /* SDIO: 1=configure GPIO0 for host wake */
++#define CCTRL1_4334_JTAG_DISABLE	(1 << 3)    /* 1=disable JTAG interface on mux'd pins */
++#define CCTRL1_4334_UART_ON_4_5	(1 << 28) /**< 1=UART_TX/UART_RX muxed on GPIO_4/5 (4334B0/1) */
++
++/* 4324 Chip specific ChipControl1 register bits */
++#define CCTRL1_4324_GPIO_SEL            (1 << 0)    /* 1=select GPIOs to be muxed out */
++#define CCTRL1_4324_SDIO_HOST_WAKE (1 << 2)  /* SDIO: 1=configure GPIO0 for host wake */
++
++/* 43143 chip-specific ChipStatus register bits based on Confluence documentation */
++/* register contains strap values sampled during POR */
++#define CST43143_REMAP_TO_ROM	 (3 << 0)    /* 00=Boot SRAM, 01=Boot ROM, 10=Boot SFLASH */
++#define CST43143_SDIO_EN	 (1 << 2)    /* 0 = USB Enab, SDIO pins are GPIO or I2S */
++#define CST43143_SDIO_ISO	 (1 << 3)    /* 1 = SDIO isolated */
++#define CST43143_USB_CPU_LESS	 (1 << 4)   /* 1 = CPULess mode Enabled */
++#define CST43143_CBUCK_MODE	 (3 << 6)   /* Indicates what controller mode CBUCK is in */
++#define CST43143_POK_CBUCK	 (1 << 8)   /* 1 = 1.2V CBUCK voltage ready */
++#define CST43143_PMU_OVRSPIKE	 (1 << 9)
++#define CST43143_PMU_OVRTEMP	 (0xF << 10)
++#define CST43143_SR_FLL_CAL_DONE (1 << 14)
++#define CST43143_USB_PLL_LOCKDET (1 << 15)
++#define CST43143_PMU_PLL_LOCKDET (1 << 16)
++#define CST43143_CHIPMODE_SDIOD(cs)	(((cs) & CST43143_SDIO_EN) != 0) /* SDIO */
++
++/* 43143 Chip specific ChipControl register bits */
++/* 00: SECI is disabled (JATG functional), 01: 2 wire, 10: 4 wire  */
++#define CCTRL_43143_SECI		(1<<0)
++#define CCTRL_43143_BT_LEGACY		(1<<1)
++#define CCTRL_43143_I2S_MODE		(1<<2)	/**< 0: SDIO enabled */
++#define CCTRL_43143_I2S_MASTER		(1<<3)	/**< 0: I2S MCLK input disabled */
++#define CCTRL_43143_I2S_FULL		(1<<4)	/**< 0: I2S SDIN and SPDIF_TX inputs disabled */
++#define CCTRL_43143_GSIO		(1<<5)	/**< 0: sFlash enabled */
++#define CCTRL_43143_RF_SWCTRL_MASK	(7<<6)	/**< 0: disabled */
++#define CCTRL_43143_RF_SWCTRL_0		(1<<6)
++#define CCTRL_43143_RF_SWCTRL_1		(2<<6)
++#define CCTRL_43143_RF_SWCTRL_2		(4<<6)
++#define CCTRL_43143_RF_XSWCTRL		(1<<9)	/**< 0: UART enabled */
++#define CCTRL_43143_HOST_WAKE0		(1<<11)	/**< 1: SDIO separate interrupt output from GPIO4 */
++#define CCTRL_43143_HOST_WAKE1		(1<<12)	/* 1: SDIO separate interrupt output from GPIO16 */
++
++/* 43143 resources, based on pmu_params.xls V1.19 */
++#define RES43143_EXT_SWITCHER_PWM	0	/**< 0x00001 */
++#define RES43143_XTAL_PU		1	/**< 0x00002 */
++#define RES43143_ILP_REQUEST		2	/**< 0x00004 */
++#define RES43143_ALP_AVAIL		3	/**< 0x00008 */
++#define RES43143_WL_CORE_READY		4	/**< 0x00010 */
++#define RES43143_BBPLL_PWRSW_PU		5	/**< 0x00020 */
++#define RES43143_HT_AVAIL		6	/**< 0x00040 */
++#define RES43143_RADIO_PU		7	/**< 0x00080 */
++#define RES43143_MACPHY_CLK_AVAIL	8	/**< 0x00100 */
++#define RES43143_OTP_PU			9	/**< 0x00200 */
++#define RES43143_LQ_AVAIL		10	/**< 0x00400 */
++
++#define PMU43143_XTAL_CORE_SIZE_MASK	0x3F
++
++/* 4313 resources */
++#define	RES4313_BB_PU_RSRC		0
++#define	RES4313_ILP_REQ_RSRC		1
++#define	RES4313_XTAL_PU_RSRC		2
++#define	RES4313_ALP_AVAIL_RSRC		3
++#define	RES4313_RADIO_PU_RSRC		4
++#define	RES4313_BG_PU_RSRC		5
++#define	RES4313_VREG1P4_PU_RSRC		6
++#define	RES4313_AFE_PWRSW_RSRC		7
++#define	RES4313_RX_PWRSW_RSRC		8
++#define	RES4313_TX_PWRSW_RSRC		9
++#define	RES4313_BB_PWRSW_RSRC		10
++#define	RES4313_SYNTH_PWRSW_RSRC	11
++#define	RES4313_MISC_PWRSW_RSRC		12
++#define	RES4313_BB_PLL_PWRSW_RSRC	13
++#define	RES4313_HT_AVAIL_RSRC		14
++#define	RES4313_MACPHY_CLK_AVAIL_RSRC	15
++
++/* 4313 chip-specific ChipStatus register bits */
++#define	CST4313_SPROM_PRESENT			1
++#define	CST4313_OTP_PRESENT			2
++#define	CST4313_SPROM_OTP_SEL_MASK		0x00000002
++#define	CST4313_SPROM_OTP_SEL_SHIFT		0
++
++/* 4313 Chip specific ChipControl register bits */
++#define CCTRL_4313_12MA_LED_DRIVE    0x00000007    /* 12 mA drive strengh for later 4313 */
++
++/* PMU respources for 4314 */
++#define RES4314_LPLDO_PU		0
++#define RES4314_PMU_SLEEP_DIS		1
++#define RES4314_PMU_BG_PU		2
++#define RES4314_CBUCK_LPOM_PU		3
++#define RES4314_CBUCK_PFM_PU		4
++#define RES4314_CLDO_PU			5
++#define RES4314_LPLDO2_LVM		6
++#define RES4314_WL_PMU_PU		7
++#define RES4314_LNLDO_PU		8
++#define RES4314_LDO3P3_PU		9
++#define RES4314_OTP_PU			10
++#define RES4314_XTAL_PU			11
++#define RES4314_WL_PWRSW_PU		12
++#define RES4314_LQ_AVAIL		13
++#define RES4314_LOGIC_RET		14
++#define RES4314_MEM_SLEEP		15
++#define RES4314_MACPHY_RET		16
++#define RES4314_WL_CORE_READY		17
++#define RES4314_ILP_REQ			18
++#define RES4314_ALP_AVAIL		19
++#define RES4314_MISC_PWRSW_PU		20
++#define RES4314_SYNTH_PWRSW_PU		21
++#define RES4314_RX_PWRSW_PU		22
++#define RES4314_RADIO_PU		23
++#define RES4314_VCO_LDO_PU		24
++#define RES4314_AFE_LDO_PU		25
++#define RES4314_RX_LDO_PU		26
++#define RES4314_TX_LDO_PU		27
++#define RES4314_HT_AVAIL		28
++#define RES4314_MACPHY_CLK_AVAIL	29
++
++/* 4314 chip-specific ChipStatus register bits */
++#define CST4314_OTP_ENABLED		0x00200000
++
++/* 43228 resources */
++#define RES43228_NOT_USED		0
++#define RES43228_ILP_REQUEST		1
++#define RES43228_XTAL_PU		2
++#define RES43228_ALP_AVAIL		3
++#define RES43228_PLL_EN			4
++#define RES43228_HT_PHY_AVAIL		5
++
++/* 43228 chipstatus  reg bits */
++#define CST43228_ILP_DIV_EN		0x1
++#define	CST43228_OTP_PRESENT		0x2
++#define	CST43228_SERDES_REFCLK_PADSEL	0x4
++#define	CST43228_SDIO_MODE		0x8
++#define	CST43228_SDIO_OTP_PRESENT	0x10
++#define	CST43228_SDIO_RESET		0x20
++
++/* 4706 chipstatus reg bits */
++#define	CST4706_PKG_OPTION		(1<<0) /* 0: full-featured package 1: low-cost package */
++#define	CST4706_SFLASH_PRESENT	(1<<1) /* 0: parallel, 1: serial flash is present */
++#define	CST4706_SFLASH_TYPE		(1<<2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
++#define	CST4706_MIPS_BENDIAN	(1<<3) /* 0: little,  1: big endian */
++#define	CST4706_PCIE1_DISABLE	(1<<5) /* PCIE1 enable strap pin */
++
++/* 4706 flashstrconfig reg bits */
++#define FLSTRCF4706_MASK		0x000000ff
++#define FLSTRCF4706_SF1			0x00000001	/**< 2nd serial flash present */
++#define FLSTRCF4706_PF1			0x00000002	/**< 2nd parallel flash present */
++#define FLSTRCF4706_SF1_TYPE	0x00000004	/**< 2nd serial flash type : 0 : ST, 1 : Atmel */
++#define FLSTRCF4706_NF1			0x00000008	/**< 2nd NAND flash present */
++#define FLSTRCF4706_1ST_MADDR_SEG_MASK		0x000000f0	/**< Valid value mask */
++#define FLSTRCF4706_1ST_MADDR_SEG_4MB		0x00000010	/**< 4MB */
++#define FLSTRCF4706_1ST_MADDR_SEG_8MB		0x00000020	/**< 8MB */
++#define FLSTRCF4706_1ST_MADDR_SEG_16MB		0x00000030	/**< 16MB */
++#define FLSTRCF4706_1ST_MADDR_SEG_32MB		0x00000040	/**< 32MB */
++#define FLSTRCF4706_1ST_MADDR_SEG_64MB		0x00000050	/**< 64MB */
++#define FLSTRCF4706_1ST_MADDR_SEG_128MB		0x00000060	/**< 128MB */
++#define FLSTRCF4706_1ST_MADDR_SEG_256MB		0x00000070	/**< 256MB */
++
++/* 4360 Chip specific ChipControl register bits */
++#define CCTRL4360_I2C_MODE			(1 << 0)
++#define CCTRL4360_UART_MODE			(1 << 1)
++#define CCTRL4360_SECI_MODE			(1 << 2)
++#define CCTRL4360_BTSWCTRL_MODE			(1 << 3)
++#define CCTRL4360_DISCRETE_FEMCTRL_MODE		(1 << 4)
++#define CCTRL4360_DIGITAL_PACTRL_MODE		(1 << 5)
++#define CCTRL4360_BTSWCTRL_AND_DIGPA_PRESENT	(1 << 6)
++#define CCTRL4360_EXTRA_GPIO_MODE		(1 << 7)
++#define CCTRL4360_EXTRA_FEMCTRL_MODE		(1 << 8)
++#define CCTRL4360_BT_LGCY_MODE			(1 << 9)
++#define CCTRL4360_CORE2FEMCTRL4_ON		(1 << 21)
++#define CCTRL4360_SECI_ON_GPIO01		(1 << 24)
++
++/* 4360 Chip specific Regulator Control register bits */
++#define RCTRL4360_RFLDO_PWR_DOWN		(1 << 1)
++
++/* 4360 PMU resources and chip status bits */
++#define RES4360_REGULATOR          0
++#define RES4360_ILP_AVAIL          1
++#define RES4360_ILP_REQ            2
++#define RES4360_XTAL_LDO_PU        3
++#define RES4360_XTAL_PU            4
++#define RES4360_ALP_AVAIL          5
++#define RES4360_BBPLLPWRSW_PU      6
++#define RES4360_HT_AVAIL           7
++#define RES4360_OTP_PU             8
++#define RES4360_AVB_PLL_PWRSW_PU   9
++#define RES4360_PCIE_TL_CLK_AVAIL  10
++
++#define CST4360_XTAL_40MZ                  0x00000001
++#define CST4360_SFLASH                     0x00000002
++#define CST4360_SPROM_PRESENT              0x00000004
++#define CST4360_SFLASH_TYPE                0x00000004
++#define CST4360_OTP_ENABLED                0x00000008
++#define CST4360_REMAP_ROM                  0x00000010
++#define CST4360_RSRC_INIT_MODE_MASK        0x00000060
++#define CST4360_RSRC_INIT_MODE_SHIFT       5
++#define CST4360_ILP_DIVEN                  0x00000080
++#define CST4360_MODE_USB                   0x00000100
++#define CST4360_SPROM_SIZE_MASK            0x00000600
++#define CST4360_SPROM_SIZE_SHIFT           9
++#define CST4360_BBPLL_LOCK                 0x00000800
++#define CST4360_AVBBPLL_LOCK               0x00001000
++#define CST4360_USBBBPLL_LOCK              0x00002000
++#define CST4360_RSRC_INIT_MODE(cs)	((cs & CST4360_RSRC_INIT_MODE_MASK) >> \
++					CST4360_RSRC_INIT_MODE_SHIFT)
++
++#define CCTRL_4360_UART_SEL	0x2
++#define CST4360_RSRC_INIT_MODE(cs)	((cs & CST4360_RSRC_INIT_MODE_MASK) >> \
++					CST4360_RSRC_INIT_MODE_SHIFT)
++
++#define PMU4360_CC1_GPIO7_OVRD	           (1<<23) /* GPIO7 override */
++
++
++/* 43602 PMU resources based on pmu_params.xls version v0.95 */
++#define RES43602_LPLDO_PU		0
++#define RES43602_REGULATOR		1
++#define RES43602_PMU_SLEEP		2
++#define RES43602_RSVD_3			3
++#define RES43602_XTALLDO_PU		4
++#define RES43602_SERDES_PU		5
++#define RES43602_BBPLL_PWRSW_PU		6
++#define RES43602_SR_CLK_START		7
++#define RES43602_SR_PHY_PWRSW		8
++#define RES43602_SR_SUBCORE_PWRSW	9
++#define RES43602_XTAL_PU		10
++#define	RES43602_PERST_OVR		11
++#define RES43602_SR_CLK_STABLE		12
++#define RES43602_SR_SAVE_RESTORE	13
++#define RES43602_SR_SLEEP		14
++#define RES43602_LQ_START		15
++#define RES43602_LQ_AVAIL		16
++#define RES43602_WL_CORE_RDY		17
++#define RES43602_ILP_REQ		18
++#define RES43602_ALP_AVAIL		19
++#define RES43602_RADIO_PU		20
++#define RES43602_RFLDO_PU		21
++#define RES43602_HT_START		22
++#define RES43602_HT_AVAIL		23
++#define RES43602_MACPHY_CLKAVAIL	24
++#define RES43602_PARLDO_PU		25
++#define RES43602_RSVD_26		26
++
++/* 43602 chip status bits */
++#define CST43602_SPROM_PRESENT             (1<<1)
++#define CST43602_SPROM_SIZE                (1<<10) /* 0 = 16K, 1 = 4K */
++#define CST43602_BBPLL_LOCK                (1<<11)
++#define CST43602_RF_LDO_OUT_OK             (1<<15) /* RF LDO output OK */
++
++#define PMU43602_CC1_GPIO12_OVRD           (1<<28) /* GPIO12 override */
++
++#define PMU43602_CC2_PCIE_CLKREQ_L_WAKE_EN (1<<1)  /* creates gated_pcie_wake, pmu_wakeup logic */
++#define PMU43602_CC2_PCIE_PERST_L_WAKE_EN  (1<<2)  /* creates gated_pcie_wake, pmu_wakeup logic */
++#define PMU43602_CC2_ENABLE_L2REFCLKPAD_PWRDWN (1<<3)
++#define PMU43602_CC2_PMU_WAKE_ALP_AVAIL_EN (1<<5)  /* enable pmu_wakeup to request for ALP_AVAIL */
++#define PMU43602_CC2_PERST_L_EXTEND_EN     (1<<9)  /* extend perst_l until rsc PERST_OVR comes up */
++#define PMU43602_CC2_FORCE_EXT_LPO         (1<<19) /* 1=ext LPO clock is the final LPO clock */
++#define PMU43602_CC2_XTAL32_SEL            (1<<30) /* 0=ext_clock, 1=xtal */
++
++#define CC_SR1_43602_SR_ASM_ADDR	(0x0)
++
++/* PLL CTL register values for open loop, used during S/R operation */
++#define PMU43602_PLL_CTL6_VAL		0x68000528
++#define PMU43602_PLL_CTL7_VAL		0x6
++
++#define PMU43602_CC3_ARMCR4_DBG_CLK	(1 << 29)
++
++/* 4365 PMU resources */
++#define RES4365_REGULATOR_PU			0
++#define RES4365_XTALLDO_PU			1
++#define RES4365_XTAL_PU				2
++#define RES4365_CPU_PLLLDO_PU			3
++#define RES4365_CPU_PLL_PU			4
++#define RES4365_WL_CORE_RDY			5
++#define RES4365_ILP_REQ				6
++#define RES4365_ALP_AVAIL			7
++#define RES4365_HT_AVAIL			8
++#define RES4365_BB_PLLLDO_PU			9
++#define RES4365_BB_PLL_PU			10
++#define RES4365_MINIMU_PU			11
++#define RES4365_RADIO_PU			12
++#define RES4365_MACPHY_CLK_AVAIL		13
++
++/* 4349 related */
++#define RES4349_LPLDO_PU			0
++#define RES4349_BG_PU				1
++#define RES4349_PMU_SLEEP			2
++#define RES4349_PALDO3P3_PU			3
++#define RES4349_CBUCK_LPOM_PU		4
++#define RES4349_CBUCK_PFM_PU		5
++#define RES4349_COLD_START_WAIT		6
++#define RES4349_RSVD_7				7
++#define RES4349_LNLDO_PU			8
++#define RES4349_XTALLDO_PU			9
++#define RES4349_LDO3P3_PU			10
++#define RES4349_OTP_PU				11
++#define RES4349_XTAL_PU				12
++#define RES4349_SR_CLK_START		13
++#define RES4349_LQ_AVAIL			14
++#define RES4349_LQ_START			15
++#define RES4349_PERST_OVR			16
++#define RES4349_WL_CORE_RDY			17
++#define RES4349_ILP_REQ				18
++#define RES4349_ALP_AVAIL			19
++#define RES4349_MINI_PMU			20
++#define RES4349_RADIO_PU			21
++#define RES4349_SR_CLK_STABLE		22
++#define RES4349_SR_SAVE_RESTORE		23
++#define RES4349_SR_PHY_PWRSW		24
++#define RES4349_SR_VDDM_PWRSW		25
++#define RES4349_SR_SUBCORE_PWRSW	26
++#define RES4349_SR_SLEEP			27
++#define RES4349_HT_START			28
++#define RES4349_HT_AVAIL			29
++#define RES4349_MACPHY_CLKAVAIL		30
++
++/* SR Control0 bits */
++#define CC_SR0_4349_SR_ENG_EN_MASK             	0x1
++#define CC_SR0_4349_SR_ENG_EN_SHIFT             0
++#define CC_SR0_4349_SR_ENG_CLK_EN		(1 << 1)
++#define CC_SR0_4349_SR_RSRC_TRIGGER		(0xC << 2)
++#define CC_SR0_4349_SR_WD_MEM_MIN_DIV		(0x3 << 6)
++#define CC_SR0_4349_SR_MEM_STBY_ALLOW_MSK	(1 << 16)
++#define CC_SR0_4349_SR_MEM_STBY_ALLOW_SHIFT	16
++#define CC_SR0_4349_SR_ENABLE_ILP		(1 << 17)
++#define CC_SR0_4349_SR_ENABLE_ALP		(1 << 18)
++#define CC_SR0_4349_SR_ENABLE_HT		(1 << 19)
++#define CC_SR0_4349_SR_ALLOW_PIC		(3 << 20)
++#define CC_SR0_4349_SR_PMU_MEM_DISABLE		(1 << 30)
++
++/* SR Control0 bits */
++#define CC_SR0_4349_SR_ENG_EN_MASK             	0x1
++#define CC_SR0_4349_SR_ENG_EN_SHIFT             0
++#define CC_SR0_4349_SR_ENG_CLK_EN		(1 << 1)
++#define CC_SR0_4349_SR_RSRC_TRIGGER		(0xC << 2)
++#define CC_SR0_4349_SR_WD_MEM_MIN_DIV		(0x3 << 6)
++#define CC_SR0_4349_SR_MEM_STBY_ALLOW		(1 << 16)
++#define CC_SR0_4349_SR_ENABLE_ILP		(1 << 17)
++#define CC_SR0_4349_SR_ENABLE_ALP		(1 << 18)
++#define CC_SR0_4349_SR_ENABLE_HT		(1 << 19)
++#define CC_SR0_4349_SR_ALLOW_PIC		(3 << 20)
++#define CC_SR0_4349_SR_PMU_MEM_DISABLE		(1 << 30)
++
++/* SR binary offset is at 8K */
++#define CC_SR1_4349_SR_ASM_ADDR		(0x10)
++
++#define CST4349_CHIPMODE_SDIOD(cs)	(((cs) & (1 << 6)) != 0)	/* SDIO */
++#define CST4349_CHIPMODE_PCIE(cs)	(((cs) & (1 << 7)) != 0)	/* PCIE */
++
++#define CST4349_SPROM_PRESENT		0x00000010
++
++#define	VREG4_4349_MEMLPLDO_PWRUP_MASK		(1 << 31)
++#define	VREG4_4349_MEMLPLDO_PWRUP_SHIFT		(31)
++#define VREG4_4349_LPLDO1_OUTPUT_VOLT_ADJ_MASK	(0x7 << 15)
++#define VREG4_4349_LPLDO1_OUTPUT_VOLT_ADJ_SHIFT	(15)
++#define CC2_4349_PHY_PWRSE_RST_CNT_MASK		(0xF << 0)
++#define CC2_4349_PHY_PWRSE_RST_CNT_SHIFT	(0)
++#define CC2_4349_VDDM_PWRSW_EN_MASK		(1 << 20)
++#define CC2_4349_VDDM_PWRSW_EN_SHIFT		(20)
++#define CC2_4349_MEMLPLDO_PWRSW_EN_MASK		(1 << 21)
++#define CC2_4349_MEMLPLDO_PWRSW_EN_SHIFT	(21)
++#define CC2_4349_SDIO_AOS_WAKEUP_MASK		(1 << 24)
++#define CC2_4349_SDIO_AOS_WAKEUP_SHIFT		(24)
++#define CC2_4349_PMUWAKE_EN_MASK		(1 << 31)
++#define CC2_4349_PMUWAKE_EN_SHIFT		(31)
++
++#define CC5_4349_MAC_PHY_CLK_8_DIV              (1 << 27)
++
++#define CC6_4349_PCIE_CLKREQ_WAKEUP_MASK	(1 << 4)
++#define CC6_4349_PCIE_CLKREQ_WAKEUP_SHIFT	(4)
++#define CC6_4349_PMU_WAKEUP_ALPAVAIL_MASK	(1 << 6)
++#define CC6_4349_PMU_WAKEUP_ALPAVAIL_SHIFT	(6)
++#define CC6_4349_PMU_EN_EXT_PERST_MASK		(1 << 13)
++#define CC6_4349_PMU_EN_L2_DEASSERT_MASK	(1 << 14)
++#define CC6_4349_PMU_EN_L2_DEASSERT_SHIF	(14)
++#define CC6_4349_PMU_ENABLE_L2REFCLKPAD_PWRDWN	(1 << 15)
++#define CC6_4349_PMU_EN_MDIO_MASK		(1 << 16)
++#define CC6_4349_PMU_EN_ASSERT_L2_MASK		(1 << 25)
++
++
++/* 4349 GCI function sel values */
++/*
++ * Reference
++ * http://hwnbu-twiki.sj.broadcom.com/bin/view/Mwgroup/ToplevelArchitecture4349B0#Function_Sel
++ */
++#define CC4349_FNSEL_HWDEF		(0)
++#define CC4349_FNSEL_SAMEASPIN		(1)
++#define CC4349_FNSEL_GPIO		(2)
++#define CC4349_FNSEL_FAST_UART		(3)
++#define CC4349_FNSEL_GCI0		(4)
++#define CC4349_FNSEL_GCI1		(5)
++#define CC4349_FNSEL_DGB_UART		(6)
++#define CC4349_FNSEL_I2C		(7)
++#define CC4349_FNSEL_SPROM		(8)
++#define CC4349_FNSEL_MISC0		(9)
++#define CC4349_FNSEL_MISC1		(10)
++#define CC4349_FNSEL_MISC2		(11)
++#define CC4349_FNSEL_IND		(12)
++#define CC4349_FNSEL_PDN		(13)
++#define CC4349_FNSEL_PUP		(14)
++#define CC4349_FNSEL_TRISTATE		(15)
++
++/* 4364 related */
++#define RES4364_LPLDO_PU				0
++#define RES4364_BG_PU					1
++#define RES4364_MEMLPLDO_PU				2
++#define RES4364_PALDO3P3_PU				3
++#define RES4364_CBUCK_1P2				4
++#define RES4364_CBUCK_1V8				5
++#define RES4364_COLD_START_WAIT				6
++#define RES4364_SR_3x3_VDDM_PWRSW			7
++#define RES4364_3x3_MACPHY_CLKAVAIL			8
++#define RES4364_XTALLDO_PU				9
++#define RES4364_LDO3P3_PU				10
++#define RES4364_OTP_PU					11
++#define RES4364_XTAL_PU					12
++#define RES4364_SR_CLK_START				13
++#define RES4364_3x3_RADIO_PU				14
++#define RES4364_RF_LDO					15
++#define RES4364_PERST_OVR				16
++#define RES4364_WL_CORE_RDY				17
++#define RES4364_ILP_REQ					18
++#define RES4364_ALP_AVAIL				19
++#define RES4364_1x1_MINI_PMU				20
++#define RES4364_1x1_RADIO_PU				21
++#define RES4364_SR_CLK_STABLE				22
++#define RES4364_SR_SAVE_RESTORE				23
++#define RES4364_SR_PHY_PWRSW				24
++#define RES4364_SR_VDDM_PWRSW				25
++#define RES4364_SR_SUBCORE_PWRSW			26
++#define RES4364_SR_SLEEP				27
++#define RES4364_HT_START				28
++#define RES4364_HT_AVAIL				29
++#define RES4364_MACPHY_CLKAVAIL				30
++
++/* 4349 GPIO */
++#define CC4349_PIN_GPIO_00		(0)
++#define CC4349_PIN_GPIO_01		(1)
++#define CC4349_PIN_GPIO_02		(2)
++#define CC4349_PIN_GPIO_03		(3)
++#define CC4349_PIN_GPIO_04		(4)
++#define CC4349_PIN_GPIO_05		(5)
++#define CC4349_PIN_GPIO_06		(6)
++#define CC4349_PIN_GPIO_07		(7)
++#define CC4349_PIN_GPIO_08		(8)
++#define CC4349_PIN_GPIO_09		(9)
++#define CC4349_PIN_GPIO_10		(10)
++#define CC4349_PIN_GPIO_11		(11)
++#define CC4349_PIN_GPIO_12		(12)
++#define CC4349_PIN_GPIO_13		(13)
++#define CC4349_PIN_GPIO_14		(14)
++#define CC4349_PIN_GPIO_15		(15)
++#define CC4349_PIN_GPIO_16		(16)
++#define CC4349_PIN_GPIO_17		(17)
++#define CC4349_PIN_GPIO_18		(18)
++#define CC4349_PIN_GPIO_19		(19)
++
++/* Mask used to decide whether HOSTWAKE MUX to be performed or not */
++#define MUXENAB4349_HOSTWAKE_MASK	(0x000000f0) /* configure GPIO for SDIO host_wake */
++#define MUXENAB4349_HOSTWAKE_SHIFT	4
++#define MUXENAB4349_GETIX(val, name) \
++	((((val) & MUXENAB4349_ ## name ## _MASK) >> MUXENAB4349_ ## name ## _SHIFT) - 1)
++
++#define CR4_4364_RAM_BASE			(0x160000)
++
++/* SR binary offset is at 8K */
++#define CC_SR1_4364_SR_CORE0_ASM_ADDR			(0x10)
++#define CC_SR1_4364_SR_CORE1_ASM_ADDR			(0x10)
++
++#define CC_SR0_4364_SR_ENG_EN_MASK			0x1
++#define CC_SR0_4364_SR_ENG_EN_SHIFT			0
++#define CC_SR0_4364_SR_ENG_CLK_EN			(1 << 1)
++#define CC_SR0_4364_SR_RSRC_TRIGGER			(0xC << 2)
++#define CC_SR0_4364_SR_WD_MEM_MIN_DIV			(0x3 << 6)
++#define CC_SR0_4364_SR_MEM_STBY_ALLOW_MSK		(1 << 16)
++#define CC_SR0_4364_SR_MEM_STBY_ALLOW_SHIFT		16
++#define CC_SR0_4364_SR_ENABLE_ILP			(1 << 17)
++#define CC_SR0_4364_SR_ENABLE_ALP			(1 << 18)
++#define CC_SR0_4364_SR_ENABLE_HT			(1 << 19)
++#define CC_SR0_4364_SR_ALLOW_PIC			(3 << 20)
++#define CC_SR0_4364_SR_PMU_MEM_DISABLE			(1 << 30)
++
++#define PMU_4364_CC1_ENABLE_BBPLL_PWR_DWN		(0x1 << 4)
++#define PMU_4364_CC1_BBPLL_ARESET_LQ_TIME		(0x1 << 8)
++#define PMU_4364_CC1_BBPLL_ARESET_HT_UPTIME		(0x1 << 10)
++#define PMU_4364_CC1_BBPLL_DRESET_LQ_UPTIME		(0x1 << 12)
++#define PMU_4364_CC1_BBPLL_DRESET_HT_UPTIME		(0x4 << 16)
++#define PMU_4364_CC1_SUBCORE_PWRSW_UP_DELAY		(0x8 << 20)
++#define PMU_4364_CC1_SUBCORE_PWRSW_RESET_CNT		(0x4 << 24)
++
++#define PMU_4364_CC2_PHY_PWRSW_RESET_CNT		(0x2 << 0)
++#define PMU_4364_CC2_PHY_PWRSW_RESET_MASK		(0x7)
++#define PMU_4364_CC2_SEL_CHIPC_IF_FOR_SR		(1 << 21)
++
++#define PMU_4364_CC3_MEMLPLDO3x3_PWRSW_FORCE_MASK	(1 << 23)
++#define PMU_4364_CC3_MEMLPLDO1x1_PWRSW_FORCE_MASK	(1 << 24)
++#define PMU_4364_CC3_CBUCK1P2_PU_SR_VDDM_REQ_ON		(1 << 25)
++#define PMU_4364_CC3_MEMLPLDO3x3_PWRSW_FORCE_OFF	(0)
++#define PMU_4364_CC3_MEMLPLDO1x1_PWRSW_FORCE_OFF	(0)
++
++
++#define PMU_4364_CC5_DISABLE_BBPLL_CLKOUT6_DIV2_MASK	(1 << 26)
++#define PMU_4364_CC5_ENABLE_ARMCR4_DEBUG_CLK_MASK	(1 << 4)
++#define PMU_4364_CC5_DISABLE_BBPLL_CLKOUT6_DIV2		(1 << 26)
++#define PMU_4364_CC5_ENABLE_ARMCR4_DEBUG_CLK_OFF	(0)
++
++#define PMU_4364_CC6_MDI_RESET_MASK			(1 << 16)
++#define PMU_4364_CC6_USE_CLK_REQ_MASK			(1 << 18)
++#define PMU_4364_CC6_HIGHER_CLK_REQ_ALP_MASK		(1 << 20)
++#define PMU_4364_CC6_HT_AVAIL_REQ_ALP_AVAIL_MASK	(1 << 21)
++#define PMU_4364_CC6_PHY_CLK_REQUESTS_ALP_AVAIL_MASK	(1 << 22)
++#define PMU_4364_CC6_MDI_RESET				(1 << 16)
++#define PMU_4364_CC6_USE_CLK_REQ			(1 << 18)
++
++#define PMU_4364_CC6_HIGHER_CLK_REQ_ALP			(1 << 20)
++#define PMU_4364_CC6_HT_AVAIL_REQ_ALP_AVAIL		(1 << 21)
++#define PMU_4364_CC6_PHY_CLK_REQUESTS_ALP_AVAIL		(1 << 22)
++
++#define PMU_4364_VREG0_DISABLE_BT_PULL_DOWN		(1 << 2)
++#define PMU_4364_VREG1_DISABLE_WL_PULL_DOWN		(1 << 2)
++
++#define PMU_VREG_0					(0x0)
++#define PMU_VREG_1					(0x1)
++#define PMU_VREG_3					(0x3)
++#define PMU_VREG_4					(0x4)
++#define PMU_VREG_5					(0x5)
++#define PMU_VREG_6					(0x6)
++
++#define PMU_4364_VREG3_DISABLE_WPT_REG_ON_PULL_DOWN	(1 << 11)
++
++#define PMU_4364_VREG4_MEMLPLDO_PU_ON			(1 << 31)
++#define PMU_4364_VREG4_LPLPDO_ADJ			(3 << 16)
++#define PMU_4364_VREG4_LPLPDO_ADJ_MASK			(3 << 16)
++#define PMU_4364_VREG5_MAC_CLK_1x1_AUTO			(0x1 << 18)
++#define PMU_4364_VREG5_SR_AUTO				(0x1 << 20)
++#define PMU_4364_VREG5_BT_PWM_MASK			(0x1 << 21)
++#define PMU_4364_VREG5_BT_AUTO				(0x1 << 22)
++#define PMU_4364_VREG5_WL2CLB_DVFS_EN_MASK		(0x1 << 23)
++#define PMU_4364_VREG5_BT_PWMK				(0)
++#define PMU_4364_VREG5_WL2CLB_DVFS_EN			(0)
++
++#define PMU_4364_VREG6_BBPLL_AUTO			(0x1 << 17)
++#define PMU_4364_VREG6_MINI_PMU_PWM			(0x1 << 18)
++#define PMU_4364_VREG6_LNLDO_AUTO			(0x1 << 21)
++#define PMU_4364_VREG6_PCIE_PWRDN_0_AUTO		(0x1 << 23)
++#define PMU_4364_VREG6_PCIE_PWRDN_1_AUTO		(0x1 << 25)
++#define PMU_4364_VREG6_MAC_CLK_3x3_PWM			(0x1 << 27)
++#define PMU_4364_VREG6_ENABLE_FINE_CTRL			(0x1 << 30)
++
++#define PMU_4364_PLL0_DISABLE_CHANNEL6			(0x1 << 18)
++
++#define CC_GCI1_REG					(0x1)
++#define CC_GCI1_4364_IND_STATE_FOR_GPIO9_11		(0x0ccccccc)
++#define CC2_4364_SDIO_AOS_WAKEUP_MASK			(1 << 24)
++#define CC2_4364_SDIO_AOS_WAKEUP_SHIFT			(24)
++
++#define CC6_4364_PCIE_CLKREQ_WAKEUP_MASK		(1 << 4)
++#define CC6_4364_PCIE_CLKREQ_WAKEUP_SHIFT		(4)
++#define CC6_4364_PMU_WAKEUP_ALPAVAIL_MASK		(1 << 6)
++#define CC6_4364_PMU_WAKEUP_ALPAVAIL_SHIFT		(6)
++
++#define CST4364_CHIPMODE_SDIOD(cs)	(((cs) & (1 << 6)) != 0)	/* SDIO */
++#define CST4364_CHIPMODE_PCIE(cs)	(((cs) & (1 << 7)) != 0)	/* PCIE */
++#define CST4364_SPROM_PRESENT		0x00000010
++
++#define PMU_4364_MACCORE_0_RES_REQ_MASK			0x3FCBF7FF
++#define PMU_4364_MACCORE_1_RES_REQ_MASK			0x7FFB3647
++
++
++#define PMU1_PLL0_SWITCH_MACCLOCK_120MHZ			(0)
++#define PMU1_PLL0_SWITCH_MACCLOCK_160MHZ			(1)
++#define TSF_CLK_FRAC_L_4364_120MHZ					0x8889
++#define TSF_CLK_FRAC_H_4364_120MHZ					0x8
++#define TSF_CLK_FRAC_L_4364_160MHZ					0x6666
++#define TSF_CLK_FRAC_H_4364_160MHZ					0x6
++#define PMU1_PLL0_PC1_M2DIV_VALUE_120MHZ			8
++#define PMU1_PLL0_PC1_M2DIV_VALUE_160MHZ			6
++
++#define CST4347_CHIPMODE_SDIOD(cs)	(((cs) & (1 << 6)) != 0)	/* SDIO */
++#define CST4347_CHIPMODE_PCIE(cs)	(((cs) & (1 << 7)) != 0)	/* PCIE */
++#define CST4347_SPROM_PRESENT		0x00000010
++
++/* 43430 PMU resources based on pmu_params.xls */
++#define RES43430_LPLDO_PU				0
++#define RES43430_BG_PU					1
++#define RES43430_PMU_SLEEP				2
++#define RES43430_RSVD_3					3
++#define RES43430_CBUCK_LPOM_PU			4
++#define RES43430_CBUCK_PFM_PU			5
++#define RES43430_COLD_START_WAIT		6
++#define RES43430_RSVD_7					7
++#define RES43430_LNLDO_PU				8
++#define RES43430_RSVD_9					9
++#define RES43430_LDO3P3_PU				10
++#define RES43430_OTP_PU					11
++#define RES43430_XTAL_PU				12
++#define RES43430_SR_CLK_START			13
++#define RES43430_LQ_AVAIL				14
++#define RES43430_LQ_START				15
++#define RES43430_RSVD_16				16
++#define RES43430_WL_CORE_RDY			17
++#define RES43430_ILP_REQ				18
++#define RES43430_ALP_AVAIL				19
++#define RES43430_MINI_PMU				20
++#define RES43430_RADIO_PU				21
++#define RES43430_SR_CLK_STABLE			22
++#define RES43430_SR_SAVE_RESTORE		23
++#define RES43430_SR_PHY_PWRSW			24
++#define RES43430_SR_VDDM_PWRSW			25
++#define RES43430_SR_SUBCORE_PWRSW		26
++#define RES43430_SR_SLEEP				27
++#define RES43430_HT_START				28
++#define RES43430_HT_AVAIL				29
++#define RES43430_MACPHY_CLK_AVAIL		30
++
++/* 43430 chip status bits */
++#define CST43430_SDIO_MODE				0x00000001
++#define CST43430_GSPI_MODE				0x00000002
++#define CST43430_RSRC_INIT_MODE_0		0x00000080
++#define CST43430_RSRC_INIT_MODE_1		0x00000100
++#define CST43430_SEL0_SDIO				0x00000200
++#define CST43430_SEL1_SDIO				0x00000400
++#define CST43430_SEL2_SDIO				0x00000800
++#define CST43430_BBPLL_LOCKED			0x00001000
++#define CST43430_DBG_INST_DETECT		0x00004000
++#define CST43430_CLB2WL_BT_READY		0x00020000
++#define CST43430_JTAG_MODE				0x00100000
++#define CST43430_HOST_IFACE				0x00400000
++#define CST43430_TRIM_EN				0x00800000
++#define CST43430_DIN_PACKAGE_OPTION		0x10000000
++
++#define PMU43430_PLL0_PC2_P1DIV_MASK	0x0000000f
++#define PMU43430_PLL0_PC2_P1DIV_SHIFT	0
++#define PMU43430_PLL0_PC2_NDIV_INT_MASK	0x0000ff80
++#define PMU43430_PLL0_PC2_NDIV_INT_SHIFT	7
++#define PMU43430_PLL0_PC4_MDIV2_MASK	0x0000ff00
++#define PMU43430_PLL0_PC4_MDIV2_SHIFT	8
++
++/* 43430 chip SR definitions */
++#define SRAM_43430_SR_ASM_ADDR			0x7f800
++#define CC_SR1_43430_SR_ASM_ADDR		((SRAM_43430_SR_ASM_ADDR - 0x60000) >> 8)
++
++/* 43430 PMU Chip Control bits */
++#define CC2_43430_SDIO_AOS_WAKEUP_MASK			(1 << 24)
++#define CC2_43430_SDIO_AOS_WAKEUP_SHIFT			(24)
++
++
++#define PMU_MACCORE_0_RES_REQ_TIMER		0x1d000000
++#define PMU_MACCORE_0_RES_REQ_MASK		0x5FF2364F
++
++#define PMU_MACCORE_1_RES_REQ_TIMER		0x1d000000
++#define PMU_MACCORE_1_RES_REQ_MASK		0x5FF2364F
++
++/* defines to detect active host interface in use */
++#define CHIP_HOSTIF_PCIEMODE	0x1
++#define CHIP_HOSTIF_USBMODE	0x2
++#define CHIP_HOSTIF_SDIOMODE	0x4
++#define CHIP_HOSTIF_PCIE(sih)	(si_chip_hostif(sih) == CHIP_HOSTIF_PCIEMODE)
++#define CHIP_HOSTIF_USB(sih)	(si_chip_hostif(sih) == CHIP_HOSTIF_USBMODE)
++#define CHIP_HOSTIF_SDIO(sih)	(si_chip_hostif(sih) == CHIP_HOSTIF_SDIOMODE)
++
++/* 4335 resources */
++#define RES4335_LPLDO_PO           0
++#define RES4335_PMU_BG_PU          1
++#define RES4335_PMU_SLEEP          2
++#define RES4335_RSVD_3             3
++#define RES4335_CBUCK_LPOM_PU		4
++#define RES4335_CBUCK_PFM_PU		5
++#define RES4335_RSVD_6             6
++#define RES4335_RSVD_7             7
++#define RES4335_LNLDO_PU           8
++#define RES4335_XTALLDO_PU         9
++#define RES4335_LDO3P3_PU			10
++#define RES4335_OTP_PU				11
++#define RES4335_XTAL_PU				12
++#define RES4335_SR_CLK_START       13
++#define RES4335_LQ_AVAIL			14
++#define RES4335_LQ_START           15
++#define RES4335_RSVD_16            16
++#define RES4335_WL_CORE_RDY        17
++#define RES4335_ILP_REQ				18
++#define RES4335_ALP_AVAIL			19
++#define RES4335_MINI_PMU           20
++#define RES4335_RADIO_PU			21
++#define RES4335_SR_CLK_STABLE		22
++#define RES4335_SR_SAVE_RESTORE		23
++#define RES4335_SR_PHY_PWRSW		24
++#define RES4335_SR_VDDM_PWRSW      25
++#define RES4335_SR_SUBCORE_PWRSW	26
++#define RES4335_SR_SLEEP           27
++#define RES4335_HT_START           28
++#define RES4335_HT_AVAIL			29
++#define RES4335_MACPHY_CLKAVAIL		30
++
++/* 4335 Chip specific ChipStatus register bits */
++#define CST4335_SPROM_MASK			0x00000020
++#define CST4335_SFLASH_MASK			0x00000040
++#define	CST4335_RES_INIT_MODE_SHIFT	7
++#define	CST4335_RES_INIT_MODE_MASK	0x00000180
++#define CST4335_CHIPMODE_MASK		0xF
++#define CST4335_CHIPMODE_SDIOD(cs)	(((cs) & (1 << 0)) != 0)	/* SDIO */
++#define CST4335_CHIPMODE_GSPI(cs)	(((cs) & (1 << 1)) != 0)	/* gSPI */
++#define CST4335_CHIPMODE_USB20D(cs)	(((cs) & (1 << 2)) != 0)	/**< HSIC || USBDA */
++#define CST4335_CHIPMODE_PCIE(cs)	(((cs) & (1 << 3)) != 0)	/* PCIE */
++
++/* 4335 Chip specific ChipControl1 register bits */
++#define CCTRL1_4335_GPIO_SEL		(1 << 0)    /* 1=select GPIOs to be muxed out */
++#define CCTRL1_4335_SDIO_HOST_WAKE (1 << 2)  /* SDIO: 1=configure GPIO0 for host wake */
++
++/* 4335 Chip specific ChipControl2 register bits */
++#define CCTRL2_4335_AOSBLOCK		(1 << 30)
++#define CCTRL2_4335_PMUWAKE		(1 << 31)
++#define PATCHTBL_SIZE			(0x800)
++#define CR4_4335_RAM_BASE                    (0x180000)
++#define CR4_4345_LT_C0_RAM_BASE              (0x1b0000)
++#define CR4_4345_GE_C0_RAM_BASE              (0x198000)
++#define CR4_4349_RAM_BASE                    (0x180000)
++#define CR4_4349_RAM_BASE_FROM_REV_9         (0x160000)
++#define CR4_4350_RAM_BASE                    (0x180000)
++#define CR4_4360_RAM_BASE                    (0x0)
++#define CR4_43602_RAM_BASE                   (0x180000)
++#define CA7_4365_RAM_BASE                    (0x200000)
++
++#define CR4_4347_RAM_BASE                    (0x170000)
++#define CR4_4362_RAM_BASE                    (0x170000)
++
++/* 4335 chip OTP present & OTP select bits. */
++#define SPROM4335_OTP_SELECT	0x00000010
++#define SPROM4335_OTP_PRESENT	0x00000020
++
++/* 4335 GCI specific bits. */
++#define CC4335_GCI_STRAP_OVERRIDE_SFLASH_PRESENT	(1 << 24)
++#define CC4335_GCI_STRAP_OVERRIDE_SFLASH_TYPE	25
++#define CC4335_GCI_FUNC_SEL_PAD_SDIO	0x00707770
++
++/* SFLASH clkdev specific bits. */
++#define CC4335_SFLASH_CLKDIV_MASK	0x1F000000
++#define CC4335_SFLASH_CLKDIV_SHIFT	25
++
++/* 4335 OTP bits for SFLASH. */
++#define CC4335_SROM_OTP_SFLASH	40
++#define CC4335_SROM_OTP_SFLASH_PRESENT	0x1
++#define CC4335_SROM_OTP_SFLASH_TYPE	0x2
++#define CC4335_SROM_OTP_SFLASH_CLKDIV_MASK	0x003C
++#define CC4335_SROM_OTP_SFLASH_CLKDIV_SHIFT	2
++
++
++/* 4335 chip OTP present & OTP select bits. */
++#define SPROM4335_OTP_SELECT	0x00000010
++#define SPROM4335_OTP_PRESENT	0x00000020
++
++/* 4335 GCI specific bits. */
++#define CC4335_GCI_STRAP_OVERRIDE_SFLASH_PRESENT	(1 << 24)
++#define CC4335_GCI_STRAP_OVERRIDE_SFLASH_TYPE	25
++#define CC4335_GCI_FUNC_SEL_PAD_SDIO	0x00707770
++
++/* SFLASH clkdev specific bits. */
++#define CC4335_SFLASH_CLKDIV_MASK	0x1F000000
++#define CC4335_SFLASH_CLKDIV_SHIFT	25
++
++/* 4335 OTP bits for SFLASH. */
++#define CC4335_SROM_OTP_SFLASH	40
++#define CC4335_SROM_OTP_SFLASH_PRESENT	0x1
++#define CC4335_SROM_OTP_SFLASH_TYPE	0x2
++#define CC4335_SROM_OTP_SFLASH_CLKDIV_MASK	0x003C
++#define CC4335_SROM_OTP_SFLASH_CLKDIV_SHIFT	2
++
++/* 4335 resources--END */
++
++/* 43012 PMU resources based on pmu_params.xls  - Start */
++#define RES43012_MEMLPLDO_PU			0
++#define RES43012_PMU_SLEEP			1
++#define RES43012_FAST_LPO			2
++#define RES43012_BTLPO_3P3			3
++#define RES43012_SR_POK				4
++#define RES43012_DUMMY_PWRSW			5
++#define RES43012_DUMMY_LDO3P3			6
++#define RES43012_DUMMY_BT_LDO3P3		7
++#define RES43012_DUMMY_RADIO			8
++#define RES43012_VDDB_VDDRET			9
++#define RES43012_HV_LDO3P3			10
++#define RES43012_OTP_PU				11
++#define RES43012_XTAL_PU			12
++#define RES43012_SR_CLK_START			13
++#define RES43012_XTAL_STABLE			14
++#define RES43012_FCBS				15
++#define RES43012_CBUCK_MODE			16
++#define RES43012_WL_CORE_RDY			17
++#define RES43012_ILP_REQ			18
++#define RES43012_ALP_AVAIL			19
++#define RES43012_RADIO_LDO			20
++#define RES43012_MINI_PMU			21
++#define RES43012_DUMMY				22
++#define RES43012_SR_SAVE_RESTORE		23
++#define RES43012_SR_PHY_PWRSW			24
++#define RES43012_SR_VDDB_CLDO			25
++#define RES43012_SR_SUBCORE_PWRSW		26
++#define RES43012_SR_SLEEP			27
++#define RES43012_HT_START			28
++#define RES43012_HT_AVAIL			29
++#define RES43012_MACPHY_CLK_AVAIL		30
++#define CST43012_SPROM_PRESENT        0x00000010
++
++/* PLL usage in 43012 */
++#define PMU43012_PLL0_PC0_NDIV_INT_MASK			0x0000003f
++#define PMU43012_PLL0_PC0_NDIV_INT_SHIFT		0
++#define PMU43012_PLL0_PC0_NDIV_FRAC_MASK		0xfffffc00
++#define PMU43012_PLL0_PC0_NDIV_FRAC_SHIFT		10
++#define PMU43012_PLL0_PC3_PDIV_MASK			0x00003c00
++#define PMU43012_PLL0_PC3_PDIV_SHIFT			10
++#define PMU43012_PLL_NDIV_FRAC_BITS			20
++#define PMU43012_PLL_P_DIV_SCALE_BITS			10
++
++#define CCTL_43012_ARM_OFFCOUNT_MASK			0x00000003
++#define CCTL_43012_ARM_OFFCOUNT_SHIFT			0
++#define CCTL_43012_ARM_ONCOUNT_MASK			0x0000000c
++#define CCTL_43012_ARM_ONCOUNT_SHIFT			2
++
++/* PMU Rev >= 30 */
++#define PMU30_ALPCLK_ONEMHZ_ENAB			0x80000000
++
++/* 43012 PMU Chip Control Registers */
++#define PMUCCTL02_43012_SUBCORE_PWRSW_FORCE_ON		0x00000010
++#define PMUCCTL02_43012_PHY_PWRSW_FORCE_ON		0x00000040
++#define PMUCCTL02_43012_LHL_TIMER_SELECT		0x00000800
++#define PMUCCTL02_43012_RFLDO3P3_PU_FORCE_ON		0x00008000
++#define PMUCCTL02_43012_WL2CDIG_I_PMU_SLEEP_ENAB	0x00010000
++
++#define PMUCCTL04_43012_BBPLL_ENABLE_PWRDN			0x00100000
++#define PMUCCTL04_43012_BBPLL_ENABLE_PWROFF			0x00200000
++#define PMUCCTL04_43012_FORCE_BBPLL_ARESET			0x00400000
++#define PMUCCTL04_43012_FORCE_BBPLL_DRESET			0x00800000
++#define PMUCCTL04_43012_FORCE_BBPLL_PWRDN			0x01000000
++#define PMUCCTL04_43012_FORCE_BBPLL_ISOONHIGH			0x02000000
++#define PMUCCTL04_43012_FORCE_BBPLL_PWROFF			0x04000000
++#define PMUCCTL04_43012_DISABLE_LQ_AVAIL			0x08000000
++#define PMUCCTL04_43012_DISABLE_HT_AVAIL			0x10000000
++#define PMUCCTL04_43012_USE_LOCK				0x20000000
++#define PMUCCTL04_43012_OPEN_LOOP_ENABLE			0x40000000
++#define PMUCCTL04_43012_FORCE_OPEN_LOOP				0x80000000
++#define PMUCCTL08_43012_XTAL_CORE_SIZE_PMOS_NORMAL_MASK		0x00000FC0
++#define PMUCCTL08_43012_XTAL_CORE_SIZE_PMOS_NORMAL_SHIFT	6
++#define PMUCCTL08_43012_XTAL_CORE_SIZE_NMOS_NORMAL_MASK		0x00FC0000
++#define PMUCCTL08_43012_XTAL_CORE_SIZE_NMOS_NORMAL_SHIFT	18
++#define PMUCCTL08_43012_XTAL_SEL_BIAS_RES_NORMAL_MASK		0x07000000
++#define PMUCCTL08_43012_XTAL_SEL_BIAS_RES_NORMAL_SHIFT		24
++#define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_NORMAL_MASK	0x0003F000
++#define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_NORMAL_SHIFT	12
++#define PMUCCTL09_43012_XTAL_CORESIZE_RES_BYPASS_NORMAL_MASK	0x00000038
++#define PMUCCTL09_43012_XTAL_CORESIZE_RES_BYPASS_NORMAL_SHIFT	3
++#define PMUCCTL13_43012_FCBS_UP_TRIG_EN			0x00000400
++
++#define PMUCCTL14_43012_ARMCM3_RESET_INITVAL		0x00000001
++#define PMUCCTL14_43012_DOT11MAC_CLKEN_INITVAL		0x00000020
++#define PMUCCTL14_43012_SDIOD_RESET_INIVAL		0x00000400
++#define PMUCCTL14_43012_SDIO_CLK_DMN_RESET_INITVAL	0x00001000
++#define PMUCCTL14_43012_SOCRAM_CLKEN_INITVAL		0x00004000
++#define PMUCCTL14_43012_M2MDMA_RESET_INITVAL		0x00008000
++#define PMUCCTL14_43012_DISABLE_LQ_AVAIL		0x08000000
++
++
++/* 4345 Chip specific ChipStatus register bits */
++#define CST4345_SPROM_MASK		0x00000020
++#define CST4345_SFLASH_MASK		0x00000040
++#define CST4345_RES_INIT_MODE_SHIFT	7
++#define CST4345_RES_INIT_MODE_MASK	0x00000180
++#define CST4345_CHIPMODE_MASK		0x4000F
++#define CST4345_CHIPMODE_SDIOD(cs)	(((cs) & (1 << 0)) != 0)	/* SDIO */
++#define CST4345_CHIPMODE_GSPI(cs)	(((cs) & (1 << 1)) != 0)	/* gSPI */
++#define CST4345_CHIPMODE_HSIC(cs)	(((cs) & (1 << 2)) != 0)	/* HSIC */
++#define CST4345_CHIPMODE_PCIE(cs)	(((cs) & (1 << 3)) != 0)	/* PCIE */
++#define CST4345_CHIPMODE_USB20D(cs)	(((cs) & (1 << 18)) != 0)	/* USBDA */
++
++/* 4350 Chipcommon ChipStatus bits */
++#define CST4350_SDIO_MODE		0x00000001
++#define CST4350_HSIC20D_MODE		0x00000002
++#define CST4350_BP_ON_HSIC_CLK		0x00000004
++#define CST4350_PCIE_MODE		0x00000008
++#define CST4350_USB20D_MODE		0x00000010
++#define CST4350_USB30D_MODE		0x00000020
++#define CST4350_SPROM_PRESENT		0x00000040
++#define CST4350_RSRC_INIT_MODE_0	0x00000080
++#define CST4350_RSRC_INIT_MODE_1	0x00000100
++#define CST4350_SEL0_SDIO		0x00000200
++#define CST4350_SEL1_SDIO		0x00000400
++#define CST4350_SDIO_PAD_MODE		0x00000800
++#define CST4350_BBPLL_LOCKED		0x00001000
++#define CST4350_USBPLL_LOCKED		0x00002000
++#define CST4350_LINE_STATE		0x0000C000
++#define CST4350_SERDES_PIPE_PLLLOCK	0x00010000
++#define CST4350_BT_READY		0x00020000
++#define CST4350_SFLASH_PRESENT		0x00040000
++#define CST4350_CPULESS_ENABLE		0x00080000
++#define CST4350_STRAP_HOST_IFC_1	0x00100000
++#define CST4350_STRAP_HOST_IFC_2	0x00200000
++#define CST4350_STRAP_HOST_IFC_3	0x00400000
++#define CST4350_RAW_SPROM_PRESENT	0x00800000
++#define CST4350_APP_CLK_SWITCH_SEL_RDBACK	0x01000000
++#define CST4350_RAW_RSRC_INIT_MODE_0	0x02000000
++#define CST4350_SDIO_PAD_VDDIO		0x04000000
++#define CST4350_GSPI_MODE		0x08000000
++#define CST4350_PACKAGE_OPTION		0xF0000000
++#define CST4350_PACKAGE_SHIFT		28
++
++/* package option for 4350 */
++#define CST4350_PACKAGE_WLCSP		0x0
++#define CST4350_PACKAGE_PCIE		0x1
++#define CST4350_PACKAGE_WLBGA		0x2
++#define CST4350_PACKAGE_DBG		0x3
++#define CST4350_PACKAGE_USB		0x4
++#define CST4350_PACKAGE_USB_HSIC	0x4
++
++#define CST4350_PKG_MODE(cs)	((cs & CST4350_PACKAGE_OPTION) >> CST4350_PACKAGE_SHIFT)
++
++#define CST4350_PKG_WLCSP(cs)		(CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_WLCSP))
++#define CST4350_PKG_PCIE(cs)		(CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_PCIE))
++#define CST4350_PKG_WLBGA(cs)		(CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_WLBGA))
++#define CST4350_PKG_USB(cs)		(CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_USB))
++#define CST4350_PKG_USB_HSIC(cs)	(CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_USB_HSIC))
++
++/* 4350C0 USB PACKAGE using raw_sprom_present to indicate 40mHz xtal */
++#define CST4350_PKG_USB_40M(cs)		(cs & CST4350_RAW_SPROM_PRESENT)
++
++#define CST4350_CHIPMODE_SDIOD(cs)	(CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_SDIOD))
++#define CST4350_CHIPMODE_USB20D(cs)	((CST4350_IFC_MODE(cs)) == (CST4350_IFC_MODE_USB20D))
++#define CST4350_CHIPMODE_HSIC20D(cs)	(CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_HSIC20D))
++#define CST4350_CHIPMODE_HSIC30D(cs)	(CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_HSIC30D))
++#define CST4350_CHIPMODE_USB30D(cs)	(CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_USB30D))
++#define CST4350_CHIPMODE_USB30D_WL(cs)	(CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_USB30D_WL))
++#define CST4350_CHIPMODE_PCIE(cs)	(CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_PCIE))
++
++/* strap_host_ifc strap value */
++#define CST4350_HOST_IFC_MASK		0x00700000
++#define CST4350_HOST_IFC_SHIFT		20
++
++/* host_ifc raw mode */
++#define CST4350_IFC_MODE_SDIOD			0x0
++#define CST4350_IFC_MODE_HSIC20D		0x1
++#define CST4350_IFC_MODE_HSIC30D		0x2
++#define CST4350_IFC_MODE_PCIE			0x3
++#define CST4350_IFC_MODE_USB20D			0x4
++#define CST4350_IFC_MODE_USB30D			0x5
++#define CST4350_IFC_MODE_USB30D_WL		0x6
++#define CST4350_IFC_MODE_USB30D_BT		0x7
++
++#define CST4350_IFC_MODE(cs)	((cs & CST4350_HOST_IFC_MASK) >> CST4350_HOST_IFC_SHIFT)
++
++/* 4350 PMU resources */
++#define RES4350_LPLDO_PU	0
++#define RES4350_PMU_BG_PU	1
++#define RES4350_PMU_SLEEP	2
++#define RES4350_RSVD_3		3
++#define RES4350_CBUCK_LPOM_PU	4
++#define RES4350_CBUCK_PFM_PU	5
++#define RES4350_COLD_START_WAIT	6
++#define RES4350_RSVD_7		7
++#define RES4350_LNLDO_PU	8
++#define RES4350_XTALLDO_PU	9
++#define RES4350_LDO3P3_PU	10
++#define RES4350_OTP_PU		11
++#define RES4350_XTAL_PU		12
++#define RES4350_SR_CLK_START	13
++#define RES4350_LQ_AVAIL	14
++#define RES4350_LQ_START	15
++#define RES4350_PERST_OVR	16
++#define RES4350_WL_CORE_RDY	17
++#define RES4350_ILP_REQ		18
++#define RES4350_ALP_AVAIL	19
++#define RES4350_MINI_PMU	20
++#define RES4350_RADIO_PU	21
++#define RES4350_SR_CLK_STABLE	22
++#define RES4350_SR_SAVE_RESTORE	23
++#define RES4350_SR_PHY_PWRSW	24
++#define RES4350_SR_VDDM_PWRSW	25
++#define RES4350_SR_SUBCORE_PWRSW	26
++#define RES4350_SR_SLEEP	27
++#define RES4350_HT_START	28
++#define RES4350_HT_AVAIL	29
++#define RES4350_MACPHY_CLKAVAIL	30
++
++#define MUXENAB4350_UART_MASK		(0x0000000f)
++#define MUXENAB4350_UART_SHIFT		0
++#define MUXENAB4350_HOSTWAKE_MASK	(0x000000f0)	/**< configure GPIO for host_wake */
++#define MUXENAB4350_HOSTWAKE_SHIFT	4
++#define MUXENAB4349_UART_MASK           (0xf)
++
++
++#define CC4350_GPIO_COUNT		16
++
++/* 4350 GCI function sel values */
++#define CC4350_FNSEL_HWDEF		(0)
++#define CC4350_FNSEL_SAMEASPIN		(1)
++#define CC4350_FNSEL_UART		(2)
++#define CC4350_FNSEL_SFLASH		(3)
++#define CC4350_FNSEL_SPROM		(4)
++#define CC4350_FNSEL_I2C		(5)
++#define CC4350_FNSEL_MISC0		(6)
++#define CC4350_FNSEL_GCI		(7)
++#define CC4350_FNSEL_MISC1		(8)
++#define CC4350_FNSEL_MISC2		(9)
++#define CC4350_FNSEL_PWDOG 		(10)
++#define CC4350_FNSEL_IND		(12)
++#define CC4350_FNSEL_PDN		(13)
++#define CC4350_FNSEL_PUP		(14)
++#define CC4350_FNSEL_TRISTATE		(15)
++#define CC4350C_FNSEL_UART		(3)
++
++
++/* 4350 GPIO */
++#define CC4350_PIN_GPIO_00		(0)
++#define CC4350_PIN_GPIO_01		(1)
++#define CC4350_PIN_GPIO_02		(2)
++#define CC4350_PIN_GPIO_03		(3)
++#define CC4350_PIN_GPIO_04		(4)
++#define CC4350_PIN_GPIO_05		(5)
++#define CC4350_PIN_GPIO_06		(6)
++#define CC4350_PIN_GPIO_07		(7)
++#define CC4350_PIN_GPIO_08		(8)
++#define CC4350_PIN_GPIO_09		(9)
++#define CC4350_PIN_GPIO_10		(10)
++#define CC4350_PIN_GPIO_11		(11)
++#define CC4350_PIN_GPIO_12		(12)
++#define CC4350_PIN_GPIO_13		(13)
++#define CC4350_PIN_GPIO_14		(14)
++#define CC4350_PIN_GPIO_15		(15)
++
++#define CC4350_RSVD_16_SHIFT		16
++
++#define CC2_4350_PHY_PWRSW_UPTIME_MASK		(0xf << 0)
++#define CC2_4350_PHY_PWRSW_UPTIME_SHIFT		(0)
++#define CC2_4350_VDDM_PWRSW_UPDELAY_MASK	(0xf << 4)
++#define CC2_4350_VDDM_PWRSW_UPDELAY_SHIFT	(4)
++#define CC2_4350_VDDM_PWRSW_UPTIME_MASK		(0xf << 8)
++#define CC2_4350_VDDM_PWRSW_UPTIME_SHIFT	(8)
++#define CC2_4350_SBC_PWRSW_DNDELAY_MASK		(0x3 << 12)
++#define CC2_4350_SBC_PWRSW_DNDELAY_SHIFT	(12)
++#define CC2_4350_PHY_PWRSW_DNDELAY_MASK		(0x3 << 14)
++#define CC2_4350_PHY_PWRSW_DNDELAY_SHIFT	(14)
++#define CC2_4350_VDDM_PWRSW_DNDELAY_MASK	(0x3 << 16)
++#define CC2_4350_VDDM_PWRSW_DNDELAY_SHIFT	(16)
++#define CC2_4350_VDDM_PWRSW_EN_MASK		(1 << 20)
++#define CC2_4350_VDDM_PWRSW_EN_SHIFT		(20)
++#define CC2_4350_MEMLPLDO_PWRSW_EN_MASK		(1 << 21)
++#define CC2_4350_MEMLPLDO_PWRSW_EN_SHIFT	(21)
++#define CC2_4350_SDIO_AOS_WAKEUP_MASK		(1 << 24)
++#define CC2_4350_SDIO_AOS_WAKEUP_SHIFT		(24)
++
++/* Applies to 4335/4350/4345 */
++#define CC3_SR_CLK_SR_MEM_MASK			(1 << 0)
++#define CC3_SR_CLK_SR_MEM_SHIFT			(0)
++#define CC3_SR_BIT1_TBD_MASK			(1 << 1)
++#define CC3_SR_BIT1_TBD_SHIFT			(1)
++#define CC3_SR_ENGINE_ENABLE_MASK		(1 << 2)
++#define CC3_SR_ENGINE_ENABLE_SHIFT		(2)
++#define CC3_SR_BIT3_TBD_MASK			(1 << 3)
++#define CC3_SR_BIT3_TBD_SHIFT			(3)
++#define CC3_SR_MINDIV_FAST_CLK_MASK		(0xF << 4)
++#define CC3_SR_MINDIV_FAST_CLK_SHIFT		(4)
++#define CC3_SR_R23_SR2_RISE_EDGE_TRIG_MASK	(1 << 8)
++#define CC3_SR_R23_SR2_RISE_EDGE_TRIG_SHIFT	(8)
++#define CC3_SR_R23_SR2_FALL_EDGE_TRIG_MASK	(1 << 9)
++#define CC3_SR_R23_SR2_FALL_EDGE_TRIG_SHIFT	(9)
++#define CC3_SR_R23_SR_RISE_EDGE_TRIG_MASK	(1 << 10)
++#define CC3_SR_R23_SR_RISE_EDGE_TRIG_SHIFT	(10)
++#define CC3_SR_R23_SR_FALL_EDGE_TRIG_MASK	(1 << 11)
++#define CC3_SR_R23_SR_FALL_EDGE_TRIG_SHIFT	(11)
++#define CC3_SR_NUM_CLK_HIGH_MASK		(0x7 << 12)
++#define CC3_SR_NUM_CLK_HIGH_SHIFT		(12)
++#define CC3_SR_BIT15_TBD_MASK			(1 << 15)
++#define CC3_SR_BIT15_TBD_SHIFT			(15)
++#define CC3_SR_PHY_FUNC_PIC_MASK		(1 << 16)
++#define CC3_SR_PHY_FUNC_PIC_SHIFT		(16)
++#define CC3_SR_BIT17_19_TBD_MASK		(0x7 << 17)
++#define CC3_SR_BIT17_19_TBD_SHIFT		(17)
++#define CC3_SR_CHIP_TRIGGER_1_MASK		(1 << 20)
++#define CC3_SR_CHIP_TRIGGER_1_SHIFT		(20)
++#define CC3_SR_CHIP_TRIGGER_2_MASK		(1 << 21)
++#define CC3_SR_CHIP_TRIGGER_2_SHIFT		(21)
++#define CC3_SR_CHIP_TRIGGER_3_MASK		(1 << 22)
++#define CC3_SR_CHIP_TRIGGER_3_SHIFT		(22)
++#define CC3_SR_CHIP_TRIGGER_4_MASK		(1 << 23)
++#define CC3_SR_CHIP_TRIGGER_4_SHIFT		(23)
++#define CC3_SR_ALLOW_SBC_FUNC_PIC_MASK		(1 << 24)
++#define CC3_SR_ALLOW_SBC_FUNC_PIC_SHIFT		(24)
++#define CC3_SR_BIT25_26_TBD_MASK		(0x3 << 25)
++#define CC3_SR_BIT25_26_TBD_SHIFT		(25)
++#define CC3_SR_ALLOW_SBC_STBY_MASK		(1 << 27)
++#define CC3_SR_ALLOW_SBC_STBY_SHIFT		(27)
++#define CC3_SR_GPIO_MUX_MASK			(0xF << 28)
++#define CC3_SR_GPIO_MUX_SHIFT			(28)
++
++/* Applies to 4335/4350/4345 */
++#define CC4_SR_INIT_ADDR_MASK		(0x3FF0000)
++#define 	CC4_4350_SR_ASM_ADDR	(0x30)
++#define CC4_4350_C0_SR_ASM_ADDR		(0x0)
++#define 	CC4_4335_SR_ASM_ADDR	(0x48)
++#define 	CC4_4345_SR_ASM_ADDR	(0x48)
++#define CC4_SR_INIT_ADDR_SHIFT		(16)
++
++#define CC4_4350_EN_SR_CLK_ALP_MASK	(1 << 30)
++#define CC4_4350_EN_SR_CLK_ALP_SHIFT	(30)
++#define CC4_4350_EN_SR_CLK_HT_MASK	(1 << 31)
++#define CC4_4350_EN_SR_CLK_HT_SHIFT	(31)
++
++#define VREG4_4350_MEMLPDO_PU_MASK	(1 << 31)
++#define VREG4_4350_MEMLPDO_PU_SHIFT	31
++
++#define VREG6_4350_SR_EXT_CLKDIR_MASK	(1 << 20)
++#define VREG6_4350_SR_EXT_CLKDIR_SHIFT	20
++#define VREG6_4350_SR_EXT_CLKDIV_MASK	(0x3 << 21)
++#define VREG6_4350_SR_EXT_CLKDIV_SHIFT	21
++#define VREG6_4350_SR_EXT_CLKEN_MASK	(1 << 23)
++#define VREG6_4350_SR_EXT_CLKEN_SHIFT	23
++
++#define CC5_4350_PMU_EN_ASSERT_MASK	(1 << 13)
++#define CC5_4350_PMU_EN_ASSERT_SHIFT	(13)
++
++#define CC6_4350_PCIE_CLKREQ_WAKEUP_MASK	(1 << 4)
++#define CC6_4350_PCIE_CLKREQ_WAKEUP_SHIFT	(4)
++#define CC6_4350_PMU_WAKEUP_ALPAVAIL_MASK	(1 << 6)
++#define CC6_4350_PMU_WAKEUP_ALPAVAIL_SHIFT	(6)
++#define CC6_4350_PMU_EN_EXT_PERST_MASK		(1 << 17)
++#define CC6_4350_PMU_EN_EXT_PERST_SHIFT		(17)
++#define CC6_4350_PMU_EN_WAKEUP_MASK		(1 << 18)
++#define CC6_4350_PMU_EN_WAKEUP_SHIFT		(18)
++
++#define CC7_4350_PMU_EN_ASSERT_L2_MASK	(1 << 26)
++#define CC7_4350_PMU_EN_ASSERT_L2_SHIFT	(26)
++#define CC7_4350_PMU_EN_MDIO_MASK	(1 << 27)
++#define CC7_4350_PMU_EN_MDIO_SHIFT	(27)
++
++#define CC6_4345_PMU_EN_PERST_DEASSERT_MASK		(1 << 13)
++#define CC6_4345_PMU_EN_PERST_DEASSERT_SHIF		(13)
++#define CC6_4345_PMU_EN_L2_DEASSERT_MASK		(1 << 14)
++#define CC6_4345_PMU_EN_L2_DEASSERT_SHIF		(14)
++#define CC6_4345_PMU_EN_ASSERT_L2_MASK		(1 << 15)
++#define CC6_4345_PMU_EN_ASSERT_L2_SHIFT		(15)
++#define CC6_4345_PMU_EN_MDIO_MASK		(1 << 24)
++#define CC6_4345_PMU_EN_MDIO_SHIFT		(24)
++
++/* GCI chipcontrol register indices */
++#define CC_GCI_CHIPCTRL_00	(0)
++#define CC_GCI_CHIPCTRL_01	(1)
++#define CC_GCI_CHIPCTRL_02	(2)
++#define CC_GCI_CHIPCTRL_03	(3)
++#define CC_GCI_CHIPCTRL_04	(4)
++#define CC_GCI_CHIPCTRL_05	(5)
++#define CC_GCI_CHIPCTRL_06	(6)
++#define CC_GCI_CHIPCTRL_07	(7)
++#define CC_GCI_CHIPCTRL_08	(8)
++#define CC_GCI_CHIPCTRL_09	(9)
++#define CC_GCI_CHIPCTRL_10	(10)
++#define CC_GCI_CHIPCTRL_10	(10)
++#define CC_GCI_CHIPCTRL_11	(11)
++#define CC_GCI_XTAL_BUFSTRG_NFC (0xff << 12)
++
++#define CC_GCI_06_JTAG_SEL_SHIFT	4
++#define CC_GCI_06_JTAG_SEL_MASK		(1 << 4)
++
++#define CC_GCI_NUMCHIPCTRLREGS(cap1)	((cap1 & 0xF00) >> 8)
++
++/* GCI chipstatus register indices */
++#define GCI_CHIPSTATUS_00	(0)
++#define GCI_CHIPSTATUS_01	(1)
++#define GCI_CHIPSTATUS_02	(2)
++#define GCI_CHIPSTATUS_03	(3)
++#define GCI_CHIPSTATUS_04	(4)
++#define GCI_CHIPSTATUS_05	(5)
++#define GCI_CHIPSTATUS_06	(6)
++#define GCI_CHIPSTATUS_07	(7)
++#define GCI_CHIPSTATUS_08	(8)
++
++/* 43021 GCI chipstatus registers */
++#define GCI43012_CHIPSTATUS_07_BBPLL_LOCK_MASK	(1 << 3)
++
++/* 4345 PMU resources */
++#define RES4345_LPLDO_PU		0
++#define RES4345_PMU_BG_PU		1
++#define RES4345_PMU_SLEEP		2
++#define RES4345_HSICLDO_PU		3
++#define RES4345_CBUCK_LPOM_PU		4
++#define RES4345_CBUCK_PFM_PU		5
++#define RES4345_COLD_START_WAIT		6
++#define RES4345_RSVD_7			7
++#define RES4345_LNLDO_PU		8
++#define RES4345_XTALLDO_PU		9
++#define RES4345_LDO3P3_PU		10
++#define RES4345_OTP_PU			11
++#define RES4345_XTAL_PU			12
++#define RES4345_SR_CLK_START		13
++#define RES4345_LQ_AVAIL		14
++#define RES4345_LQ_START		15
++#define RES4345_PERST_OVR		16
++#define RES4345_WL_CORE_RDY		17
++#define RES4345_ILP_REQ			18
++#define RES4345_ALP_AVAIL		19
++#define RES4345_MINI_PMU		20
++#define RES4345_RADIO_PU		21
++#define RES4345_SR_CLK_STABLE		22
++#define RES4345_SR_SAVE_RESTORE		23
++#define RES4345_SR_PHY_PWRSW		24
++#define RES4345_SR_VDDM_PWRSW		25
++#define RES4345_SR_SUBCORE_PWRSW	26
++#define RES4345_SR_SLEEP		27
++#define RES4345_HT_START		28
++#define RES4345_HT_AVAIL		29
++#define RES4345_MACPHY_CLK_AVAIL	30
++
++/* 43012 pins
++ * note: only the values set as default/used are added here.
++ */
++#define CC43012_PIN_GPIO_00		(0)
++#define CC43012_PIN_GPIO_01		(1)
++#define CC43012_PIN_GPIO_02		(2)
++#define CC43012_PIN_GPIO_03		(3)
++#define CC43012_PIN_GPIO_04		(4)
++#define CC43012_PIN_GPIO_05		(5)
++#define CC43012_PIN_GPIO_06		(6)
++#define CC43012_PIN_GPIO_07		(7)
++#define CC43012_PIN_GPIO_08		(8)
++#define CC43012_PIN_GPIO_09		(9)
++#define CC43012_PIN_GPIO_10		(10)
++#define CC43012_PIN_GPIO_11		(11)
++#define CC43012_PIN_GPIO_12		(12)
++#define CC43012_PIN_GPIO_13		(13)
++#define CC43012_PIN_GPIO_14		(14)
++#define CC43012_PIN_GPIO_15		(15)
++
++/* 43012 GCI function sel values */
++#define CC43012_FNSEL_HWDEF		(0)
++#define CC43012_FNSEL_SAMEASPIN	(1)
++#define CC43012_FNSEL_GPIO0		(2)
++#define CC43012_FNSEL_GPIO1		(3)
++#define CC43012_FNSEL_GCI0		(4)
++#define CC43012_FNSEL_GCI1		(5)
++#define CC43012_FNSEL_DBG_UART	(6)
++#define CC43012_FNSEL_I2C		(7)
++#define CC43012_FNSEL_BT_SFLASH	(8)
++#define CC43012_FNSEL_MISC0		(9)
++#define CC43012_FNSEL_MISC1		(10)
++#define CC43012_FNSEL_MISC2		(11)
++#define CC43012_FNSEL_IND		(12)
++#define CC43012_FNSEL_PDN		(13)
++#define CC43012_FNSEL_PUP		(14)
++#define CC43012_FNSEL_TRI		(15)
++
++/* 4335 pins
++* note: only the values set as default/used are added here.
++*/
++#define CC4335_PIN_GPIO_00		(0)
++#define CC4335_PIN_GPIO_01		(1)
++#define CC4335_PIN_GPIO_02		(2)
++#define CC4335_PIN_GPIO_03		(3)
++#define CC4335_PIN_GPIO_04		(4)
++#define CC4335_PIN_GPIO_05		(5)
++#define CC4335_PIN_GPIO_06		(6)
++#define CC4335_PIN_GPIO_07		(7)
++#define CC4335_PIN_GPIO_08		(8)
++#define CC4335_PIN_GPIO_09		(9)
++#define CC4335_PIN_GPIO_10		(10)
++#define CC4335_PIN_GPIO_11		(11)
++#define CC4335_PIN_GPIO_12		(12)
++#define CC4335_PIN_GPIO_13		(13)
++#define CC4335_PIN_GPIO_14		(14)
++#define CC4335_PIN_GPIO_15		(15)
++#define CC4335_PIN_SDIO_CLK		(16)
++#define CC4335_PIN_SDIO_CMD		(17)
++#define CC4335_PIN_SDIO_DATA0	(18)
++#define CC4335_PIN_SDIO_DATA1	(19)
++#define CC4335_PIN_SDIO_DATA2	(20)
++#define CC4335_PIN_SDIO_DATA3	(21)
++#define CC4335_PIN_RF_SW_CTRL_6	(22)
++#define CC4335_PIN_RF_SW_CTRL_7	(23)
++#define CC4335_PIN_RF_SW_CTRL_8	(24)
++#define CC4335_PIN_RF_SW_CTRL_9	(25)
++/* Last GPIO Pad */
++#define CC4335_PIN_GPIO_LAST	(31)
++
++/* 4335 GCI function sel values
++*/
++#define CC4335_FNSEL_HWDEF		(0)
++#define CC4335_FNSEL_SAMEASPIN	(1)
++#define CC4335_FNSEL_GPIO0		(2)
++#define CC4335_FNSEL_GPIO1		(3)
++#define CC4335_FNSEL_GCI0		(4)
++#define CC4335_FNSEL_GCI1		(5)
++#define CC4335_FNSEL_UART		(6)
++#define CC4335_FNSEL_SFLASH		(7)
++#define CC4335_FNSEL_SPROM		(8)
++#define CC4335_FNSEL_MISC0		(9)
++#define CC4335_FNSEL_MISC1		(10)
++#define CC4335_FNSEL_MISC2		(11)
++#define CC4335_FNSEL_IND		(12)
++#define CC4335_FNSEL_PDN		(13)
++#define CC4335_FNSEL_PUP		(14)
++#define CC4335_FNSEL_TRI		(15)
++
++/* GCI Core Control Reg */
++#define	GCI_CORECTRL_SR_MASK	(1 << 0)	/**< SECI block Reset */
++#define	GCI_CORECTRL_RSL_MASK	(1 << 1)	/**< ResetSECILogic */
++#define	GCI_CORECTRL_ES_MASK	(1 << 2)	/**< EnableSECI */
++#define	GCI_CORECTRL_FSL_MASK	(1 << 3)	/**< Force SECI Out Low */
++#define	GCI_CORECTRL_SOM_MASK	(7 << 4)	/**< SECI Op Mode */
++#define	GCI_CORECTRL_US_MASK	(1 << 7)	/**< Update SECI */
++#define	GCI_CORECTRL_BOS_MASK	(1 << 8)	/**< Break On Sleep */
++
++/* 4345 pins
++* note: only the values set as default/used are added here.
++*/
++#define CC4345_PIN_GPIO_00		(0)
++#define CC4345_PIN_GPIO_01		(1)
++#define CC4345_PIN_GPIO_02		(2)
++#define CC4345_PIN_GPIO_03		(3)
++#define CC4345_PIN_GPIO_04		(4)
++#define CC4345_PIN_GPIO_05		(5)
++#define CC4345_PIN_GPIO_06		(6)
++#define CC4345_PIN_GPIO_07		(7)
++#define CC4345_PIN_GPIO_08		(8)
++#define CC4345_PIN_GPIO_09		(9)
++#define CC4345_PIN_GPIO_10		(10)
++#define CC4345_PIN_GPIO_11		(11)
++#define CC4345_PIN_GPIO_12		(12)
++#define CC4345_PIN_GPIO_13		(13)
++#define CC4345_PIN_GPIO_14		(14)
++#define CC4345_PIN_GPIO_15		(15)
++#define CC4345_PIN_GPIO_16		(16)
++#define CC4345_PIN_SDIO_CLK		(17)
++#define CC4345_PIN_SDIO_CMD		(18)
++#define CC4345_PIN_SDIO_DATA0	(19)
++#define CC4345_PIN_SDIO_DATA1	(20)
++#define CC4345_PIN_SDIO_DATA2	(21)
++#define CC4345_PIN_SDIO_DATA3	(22)
++#define CC4345_PIN_RF_SW_CTRL_0	(23)
++#define CC4345_PIN_RF_SW_CTRL_1	(24)
++#define CC4345_PIN_RF_SW_CTRL_2	(25)
++#define CC4345_PIN_RF_SW_CTRL_3	(26)
++#define CC4345_PIN_RF_SW_CTRL_4	(27)
++#define CC4345_PIN_RF_SW_CTRL_5	(28)
++#define CC4345_PIN_RF_SW_CTRL_6	(29)
++#define CC4345_PIN_RF_SW_CTRL_7	(30)
++#define CC4345_PIN_RF_SW_CTRL_8	(31)
++#define CC4345_PIN_RF_SW_CTRL_9	(32)
++
++/* 4345 GCI function sel values
++*/
++#define CC4345_FNSEL_HWDEF		(0)
++#define CC4345_FNSEL_SAMEASPIN		(1)
++#define CC4345_FNSEL_GPIO0		(2)
++#define CC4345_FNSEL_GPIO1		(3)
++#define CC4345_FNSEL_GCI0		(4)
++#define CC4345_FNSEL_GCI1		(5)
++#define CC4345_FNSEL_UART		(6)
++#define CC4345_FNSEL_SFLASH		(7)
++#define CC4345_FNSEL_SPROM		(8)
++#define CC4345_FNSEL_MISC0		(9)
++#define CC4345_FNSEL_MISC1		(10)
++#define CC4345_FNSEL_MISC2		(11)
++#define CC4345_FNSEL_IND		(12)
++#define CC4345_FNSEL_PDN		(13)
++#define CC4345_FNSEL_PUP		(14)
++#define CC4345_FNSEL_TRI		(15)
++
++#define MUXENAB4345_UART_MASK		(0x0000000f)
++#define MUXENAB4345_UART_SHIFT		0
++#define MUXENAB4345_HOSTWAKE_MASK	(0x000000f0)
++#define MUXENAB4345_HOSTWAKE_SHIFT	4
++
++/* 4349 Group (4349, 4355, 4359) GCI AVS function sel values */
++#define CC4349_GRP_GCI_AVS_CTRL_MASK   (0xffe00000)
++#define CC4349_GRP_GCI_AVS_CTRL_SHIFT  (21)
++#define CC4349_GRP_GCI_AVS_CTRL_ENAB   (1 << 5)
++
++/* 4345 GCI AVS function sel values */
++#define CC4345_GCI_AVS_CTRL_MASK   (0xfc)
++#define CC4345_GCI_AVS_CTRL_SHIFT  (2)
++#define CC4345_GCI_AVS_CTRL_ENAB   (1 << 5)
++
++/* 43430 Pin */
++#define CC43430_PIN_GPIO_00		(0)
++#define CC43430_PIN_GPIO_01		(1)
++#define CC43430_PIN_GPIO_02		(2)
++#define CC43430_PIN_GPIO_07		(7)
++#define CC43430_PIN_GPIO_08		(8)
++#define CC43430_PIN_GPIO_09		(9)
++#define CC43430_PIN_GPIO_10		(10)
++
++#define CC43430_FNSEL_SDIO_INT		(2)
++#define CC43430_FNSEL_6_FAST_UART	(6)
++#define CC43430_FNSEL_10_FAST_UART	(10)
++
++#define MUXENAB43430_UART_MASK		(0x0000000f)
++#define MUXENAB43430_UART_SHIFT		0
++#define MUXENAB43430_HOSTWAKE_MASK	(0x000000f0)	/* configure GPIO for SDIO host_wake */
++#define MUXENAB43430_HOSTWAKE_SHIFT	4
++
++#define CC43430_FNSEL_SAMEASPIN		(1)
++#define CC43430_RFSWCTRL_EN_MASK   (0x7f8)
++#define CC43430_RFSWCTRL_EN_SHIFT  (3)
++
++/* GCI GPIO for function sel GCI-0/GCI-1 */
++#define CC_GCI_GPIO_0			(0)
++#define CC_GCI_GPIO_1			(1)
++#define CC_GCI_GPIO_2			(2)
++#define CC_GCI_GPIO_3			(3)
++#define CC_GCI_GPIO_4			(4)
++#define CC_GCI_GPIO_5			(5)
++#define CC_GCI_GPIO_6			(6)
++#define CC_GCI_GPIO_7			(7)
++#define CC_GCI_GPIO_8			(8)
++#define CC_GCI_GPIO_9			(9)
++#define CC_GCI_GPIO_10			(10)
++#define CC_GCI_GPIO_11			(11)
++#define CC_GCI_GPIO_12			(12)
++#define CC_GCI_GPIO_13			(13)
++#define CC_GCI_GPIO_14			(14)
++#define CC_GCI_GPIO_15			(15)
++
++
++/* indicates Invalid GPIO, e.g. when PAD GPIO doesn't map to GCI GPIO */
++#define CC_GCI_GPIO_INVALID		0xFF
++
++/* find the 4 bit mask given the bit position */
++#define GCIMASK(pos)  (((uint32)0xF) << pos)
++/* get the value which can be used to directly OR with chipcontrol reg */
++#define GCIPOSVAL(val, pos)  ((((uint32)val) << pos) & GCIMASK(pos))
++/* Extract nibble from a given position */
++#define GCIGETNBL(val, pos)	((val >> pos) & 0xF)
++
++
++/* find the 8 bit mask given the bit position */
++#define GCIMASK_8B(pos)  (((uint32)0xFF) << pos)
++/* get the value which can be used to directly OR with chipcontrol reg */
++#define GCIPOSVAL_8B(val, pos)  ((((uint32)val) << pos) & GCIMASK_8B(pos))
++/* Extract nibble from a given position */
++#define GCIGETNBL_8B(val, pos)	((val >> pos) & 0xFF)
++
++/* find the 4 bit mask given the bit position */
++#define GCIMASK_4B(pos)  (((uint32)0xF) << pos)
++/* get the value which can be used to directly OR with chipcontrol reg */
++#define GCIPOSVAL_4B(val, pos)  ((((uint32)val) << pos) & GCIMASK_4B(pos))
++/* Extract nibble from a given position */
++#define GCIGETNBL_4B(val, pos)	((val >> pos) & 0xF)
++
++
++/* 4335 GCI Intstatus(Mask)/WakeMask Register bits. */
++#define GCI_INTSTATUS_RBI	(1 << 0)	/**< Rx Break Interrupt */
++#define GCI_INTSTATUS_UB	(1 << 1)	/**< UART Break Interrupt */
++#define GCI_INTSTATUS_SPE	(1 << 2)	/**< SECI Parity Error Interrupt */
++#define GCI_INTSTATUS_SFE	(1 << 3)	/**< SECI Framing Error Interrupt */
++#define GCI_INTSTATUS_SRITI	(1 << 9)	/**< SECI Rx Idle Timer Interrupt */
++#define GCI_INTSTATUS_STFF	(1 << 10)	/**< SECI Tx FIFO Full Interrupt */
++#define GCI_INTSTATUS_STFAE	(1 << 11)	/**< SECI Tx FIFO Almost Empty Intr */
++#define GCI_INTSTATUS_SRFAF	(1 << 12)	/**< SECI Rx FIFO Almost Full */
++#define GCI_INTSTATUS_SRFNE	(1 << 14)	/**< SECI Rx FIFO Not Empty */
++#define GCI_INTSTATUS_SRFOF	(1 << 15)	/**< SECI Rx FIFO Not Empty Timeout */
++#define GCI_INTSTATUS_GPIOINT	(1 << 25)	/**< GCIGpioInt */
++#define GCI_INTSTATUS_GPIOWAKE	(1 << 26)	/**< GCIGpioWake */
++
++/* 4335 GCI IntMask Register bits. */
++#define GCI_INTMASK_RBI		(1 << 0)	/**< Rx Break Interrupt */
++#define GCI_INTMASK_UB		(1 << 1)	/**< UART Break Interrupt */
++#define GCI_INTMASK_SPE		(1 << 2)	/**< SECI Parity Error Interrupt */
++#define GCI_INTMASK_SFE		(1 << 3)	/**< SECI Framing Error Interrupt */
++#define GCI_INTMASK_SRITI	(1 << 9)	/**< SECI Rx Idle Timer Interrupt */
++#define GCI_INTMASK_STFF	(1 << 10)	/**< SECI Tx FIFO Full Interrupt */
++#define GCI_INTMASK_STFAE	(1 << 11)	/**< SECI Tx FIFO Almost Empty Intr */
++#define GCI_INTMASK_SRFAF	(1 << 12)	/**< SECI Rx FIFO Almost Full */
++#define GCI_INTMASK_SRFNE	(1 << 14)	/**< SECI Rx FIFO Not Empty */
++#define GCI_INTMASK_SRFOF	(1 << 15)	/**< SECI Rx FIFO Not Empty Timeout */
++#define GCI_INTMASK_GPIOINT	(1 << 25)	/**< GCIGpioInt */
++#define GCI_INTMASK_GPIOWAKE	(1 << 26)	/**< GCIGpioWake */
++
++/* 4335 GCI WakeMask Register bits. */
++#define GCI_WAKEMASK_RBI	(1 << 0)	/**< Rx Break Interrupt */
++#define GCI_WAKEMASK_UB		(1 << 1)	/**< UART Break Interrupt */
++#define GCI_WAKEMASK_SPE	(1 << 2)	/**< SECI Parity Error Interrupt */
++#define GCI_WAKEMASK_SFE	(1 << 3)	/**< SECI Framing Error Interrupt */
++#define GCI_WAKE_SRITI		(1 << 9)	/**< SECI Rx Idle Timer Interrupt */
++#define GCI_WAKEMASK_STFF	(1 << 10)	/**< SECI Tx FIFO Full Interrupt */
++#define GCI_WAKEMASK_STFAE	(1 << 11)	/**< SECI Tx FIFO Almost Empty Intr */
++#define GCI_WAKEMASK_SRFAF	(1 << 12)	/**< SECI Rx FIFO Almost Full */
++#define GCI_WAKEMASK_SRFNE	(1 << 14)	/**< SECI Rx FIFO Not Empty */
++#define GCI_WAKEMASK_SRFOF	(1 << 15)	/**< SECI Rx FIFO Not Empty Timeout */
++#define GCI_WAKEMASK_GPIOINT	(1 << 25)	/**< GCIGpioInt */
++#define GCI_WAKEMASK_GPIOWAKE	(1 << 26)	/**< GCIGpioWake */
++
++#define	GCI_WAKE_ON_GCI_GPIO1	1
++#define	GCI_WAKE_ON_GCI_GPIO2	2
++#define	GCI_WAKE_ON_GCI_GPIO3	3
++#define	GCI_WAKE_ON_GCI_GPIO4	4
++#define	GCI_WAKE_ON_GCI_GPIO5	5
++#define	GCI_WAKE_ON_GCI_GPIO6	6
++#define	GCI_WAKE_ON_GCI_GPIO7	7
++#define	GCI_WAKE_ON_GCI_GPIO8	8
++#define	GCI_WAKE_ON_GCI_SECI_IN	9
++
++/* 43012 ULB dividers */
++#define PMU43012_CC0_ULB_DIVMASK		0xfffffc00
++#define PMU43012_10MHZ_ULB_DIV			((1 << 0) | (1 << 5))
++#define PMU43012_5MHZ_ULB_DIV			((3 << 0) | (3 << 5))
++#define PMU43012_2P5MHZ_ULB_DIV			((7 << 0) | (7 << 5))
++#define PMU43012_ULB_NO_DIV				0
++
++/* 4335 MUX options. each nibble belongs to a setting. Non-zero value specifies a logic
++* for now only UART for bootloader.
++*/
++#define MUXENAB4335_UART_MASK		(0x0000000f)
++
++#define MUXENAB4335_UART_SHIFT		0
++#define MUXENAB4335_HOSTWAKE_MASK	(0x000000f0)	/**< configure GPIO for SDIO host_wake */
++#define MUXENAB4335_HOSTWAKE_SHIFT	4
++#define MUXENAB4335_GETIX(val, name) \
++	((((val) & MUXENAB4335_ ## name ## _MASK) >> MUXENAB4335_ ## name ## _SHIFT) - 1)
++
++/* 43012 MUX options */
++#define MUXENAB43012_HOSTWAKE_MASK	(0x00000001)
++#define MUXENAB43012_GETIX(val, name) (val - 1)
++
++/*
++* Maximum delay for the PMU state transition in us.
++* This is an upper bound intended for spinwaits etc.
++*/
++#define PMU_MAX_TRANSITION_DLY	15000
++
++/* PMU resource up transition time in ILP cycles */
++#define PMURES_UP_TRANSITION	2
++
++/* 53573 PMU Resource */
++#define RES53573_REGULATOR_PU     0
++#define RES53573_XTALLDO_PU       1
++#define RES53573_XTAL_PU          2
++#define RES53573_MINI_PMU         3
++#define RES53573_RADIO_PU         4
++#define RES53573_ILP_REQ          5
++#define RES53573_ALP_AVAIL        6
++#define RES53573_CPUPLL_LDO_PU    7
++#define RES53573_CPU_PLL_PU       8
++#define RES53573_WLAN_BB_PLL_PU   9
++#define RES53573_MISCPLL_LDO_PU    10
++#define RES53573_MISCPLL_PU       11
++#define RES53573_AUDIOPLL_PU      12
++#define RES53573_PCIEPLL_LDO_PU   13
++#define RES53573_PCIEPLL_PU       14
++#define RES53573_DDRPLL_LDO_PU    15
++#define RES53573_DDRPLL_PU        16
++#define RES53573_HT_AVAIL         17
++#define RES53573_MACPHY_CLK_AVAIL 18
++#define RES53573_OTP_PU           19
++#define RES53573_RSVD20           20
++
++/* 53573 Chip status registers */
++#define CST53573_LOCK_CPUPLL          0x00000001
++#define CST53573_LOCK_MISCPLL         0x00000002
++#define CST53573_LOCK_DDRPLL          0x00000004
++#define CST53573_LOCK_PCIEPLL         0x00000008
++#define CST53573_EPHY_ENERGY_DET      0x00001f00
++#define CST53573_RAW_ENERGY           0x0003e000
++#define CST53573_BBPLL_LOCKED_O       0x00040000
++#define CST53573_SERDES_PIPE_PLLLOCK  0x00080000
++#define CST53573_STRAP_PCIE_EP_MODE   0x00100000
++#define CST53573_EPHY_PLL_LOCK        0x00200000
++#define CST53573_AUDIO_PLL_LOCKED_O   0x00400000
++#define CST53573_PCIE_LINK_IN_L11     0x01000000
++#define CST53573_PCIE_LINK_IN_L12     0x02000000
++#define CST53573_DIN_PACKAGEOPTION    0xf0000000
++
++/* 53573 Chip control registers macro definitions */
++#define PMU_53573_CHIPCTL1                      1
++#define PMU_53573_CC1_HT_CLK_REQ_CTRL_MASK      0x00000010
++#define PMU_53573_CC1_HT_CLK_REQ_CTRL           0x00000010
++
++#define PMU_53573_CHIPCTL3                      3
++#define PMU_53573_CC3_ENABLE_CLOSED_LOOP_MASK   0x00000010
++#define PMU_53573_CC3_ENABLE_CLOSED_LOOP        0x00000000
++#define PMU_53573_CC3_ENABLE_BBPLL_PWRDOWN_MASK 0x00000002
++#define PMU_53573_CC3_ENABLE_BBPLL_PWRDOWN      0x00000002
++
++#define CST53573_CHIPMODE_PCIE(cs)		FALSE
++
++
++/* SECI Status (0x134) & Mask (0x138) bits - Rev 35 */
++#define SECI_STAT_BI	(1 << 0)	/* Break Interrupt */
++#define SECI_STAT_SPE	(1 << 1)	/* Parity Error */
++#define SECI_STAT_SFE	(1 << 2)	/* Parity Error */
++#define SECI_STAT_SDU	(1 << 3)	/* Data Updated */
++#define SECI_STAT_SADU	(1 << 4)	/* Auxiliary Data Updated */
++#define SECI_STAT_SAS	(1 << 6)	/* AUX State */
++#define SECI_STAT_SAS2	(1 << 7)	/* AUX2 State */
++#define SECI_STAT_SRITI	(1 << 8)	/* Idle Timer Interrupt */
++#define SECI_STAT_STFF	(1 << 9)	/* Tx FIFO Full */
++#define SECI_STAT_STFAE	(1 << 10)	/* Tx FIFO Almost Empty */
++#define SECI_STAT_SRFE	(1 << 11)	/* Rx FIFO Empty */
++#define SECI_STAT_SRFAF	(1 << 12)	/* Rx FIFO Almost Full */
++#define SECI_STAT_SFCE	(1 << 13)	/* Flow Control Event */
++
++/* SECI configuration */
++#define SECI_MODE_UART			0x0
++#define SECI_MODE_SECI			0x1
++#define SECI_MODE_LEGACY_3WIRE_BT	0x2
++#define SECI_MODE_LEGACY_3WIRE_WLAN	0x3
++#define SECI_MODE_HALF_SECI		0x4
++
++#define SECI_RESET		(1 << 0)
++#define SECI_RESET_BAR_UART	(1 << 1)
++#define SECI_ENAB_SECI_ECI	(1 << 2)
++#define SECI_ENAB_SECIOUT_DIS	(1 << 3)
++#define SECI_MODE_MASK		0x7
++#define SECI_MODE_SHIFT		4 /* (bits 5, 6, 7) */
++#define SECI_UPD_SECI		(1 << 7)
++
++#define SECI_SLIP_ESC_CHAR	0xDB
++#define SECI_SIGNOFF_0		SECI_SLIP_ESC_CHAR
++#define SECI_SIGNOFF_1     0
++#define SECI_REFRESH_REQ	0xDA
++
++/* seci clk_ctl_st bits */
++#define CLKCTL_STS_HT_AVAIL_REQ		(1 << 4)
++#define CLKCTL_STS_SECI_CLK_REQ		(1 << 8)
++#define CLKCTL_STS_SECI_CLK_AVAIL	(1 << 24)
++
++#define SECI_UART_MSR_CTS_STATE		(1 << 0)
++#define SECI_UART_MSR_RTS_STATE		(1 << 1)
++#define SECI_UART_SECI_IN_STATE		(1 << 2)
++#define SECI_UART_SECI_IN2_STATE	(1 << 3)
++
++/* GCI RX FIFO Control Register */
++#define	GCI_RXF_LVL_MASK	(0xFF << 0)
++#define	GCI_RXF_TIMEOUT_MASK	(0xFF << 8)
++
++/* GCI UART Registers' Bit definitions */
++/* Seci Fifo Level Register */
++#define	SECI_TXF_LVL_MASK	(0x3F << 8)
++#define	TXF_AE_LVL_DEFAULT	0x4
++#define	SECI_RXF_LVL_FC_MASK	(0x3F << 16)
++
++/* SeciUARTFCR Bit definitions */
++#define	SECI_UART_FCR_RFR		(1 << 0)
++#define	SECI_UART_FCR_TFR		(1 << 1)
++#define	SECI_UART_FCR_SR		(1 << 2)
++#define	SECI_UART_FCR_THP		(1 << 3)
++#define	SECI_UART_FCR_AB		(1 << 4)
++#define	SECI_UART_FCR_ATOE		(1 << 5)
++#define	SECI_UART_FCR_ARTSOE		(1 << 6)
++#define	SECI_UART_FCR_ABV		(1 << 7)
++#define	SECI_UART_FCR_ALM		(1 << 8)
++
++/* SECI UART LCR register bits */
++#define SECI_UART_LCR_STOP_BITS		(1 << 0) /* 0 - 1bit, 1 - 2bits */
++#define SECI_UART_LCR_PARITY_EN		(1 << 1)
++#define SECI_UART_LCR_PARITY		(1 << 2) /* 0 - odd, 1 - even */
++#define SECI_UART_LCR_RX_EN		(1 << 3)
++#define SECI_UART_LCR_LBRK_CTRL		(1 << 4) /* 1 => SECI_OUT held low */
++#define SECI_UART_LCR_TXO_EN		(1 << 5)
++#define SECI_UART_LCR_RTSO_EN		(1 << 6)
++#define SECI_UART_LCR_SLIPMODE_EN	(1 << 7)
++#define SECI_UART_LCR_RXCRC_CHK		(1 << 8)
++#define SECI_UART_LCR_TXCRC_INV		(1 << 9)
++#define SECI_UART_LCR_TXCRC_LSBF	(1 << 10)
++#define SECI_UART_LCR_TXCRC_EN		(1 << 11)
++#define	SECI_UART_LCR_RXSYNC_EN		(1 << 12)
++
++#define SECI_UART_MCR_TX_EN		(1 << 0)
++#define SECI_UART_MCR_PRTS		(1 << 1)
++#define SECI_UART_MCR_SWFLCTRL_EN	(1 << 2)
++#define SECI_UART_MCR_HIGHRATE_EN	(1 << 3)
++#define SECI_UART_MCR_LOOPBK_EN		(1 << 4)
++#define SECI_UART_MCR_AUTO_RTS		(1 << 5)
++#define SECI_UART_MCR_AUTO_TX_DIS	(1 << 6)
++#define SECI_UART_MCR_BAUD_ADJ_EN	(1 << 7)
++#define SECI_UART_MCR_XONOFF_RPT	(1 << 9)
++
++/* SeciUARTLSR Bit Mask */
++#define	SECI_UART_LSR_RXOVR_MASK	(1 << 0)
++#define	SECI_UART_LSR_RFF_MASK		(1 << 1)
++#define	SECI_UART_LSR_TFNE_MASK		(1 << 2)
++#define	SECI_UART_LSR_TI_MASK		(1 << 3)
++#define	SECI_UART_LSR_TPR_MASK		(1 << 4)
++#define	SECI_UART_LSR_TXHALT_MASK	(1 << 5)
++
++/* SeciUARTMSR Bit Mask */
++#define	SECI_UART_MSR_CTSS_MASK		(1 << 0)
++#define	SECI_UART_MSR_RTSS_MASK		(1 << 1)
++#define	SECI_UART_MSR_SIS_MASK		(1 << 2)
++#define	SECI_UART_MSR_SIS2_MASK		(1 << 3)
++
++/* SeciUARTData Bits */
++#define SECI_UART_DATA_RF_NOT_EMPTY_BIT	(1 << 12)
++#define SECI_UART_DATA_RF_FULL_BIT	(1 << 13)
++#define SECI_UART_DATA_RF_OVRFLOW_BIT	(1 << 14)
++#define	SECI_UART_DATA_FIFO_PTR_MASK	0xFF
++#define	SECI_UART_DATA_RF_RD_PTR_SHIFT	16
++#define	SECI_UART_DATA_RF_WR_PTR_SHIFT	24
++
++/* LTECX: ltecxmux */
++#define LTECX_EXTRACT_MUX(val, idx)	(getbit4(&(val), (idx)))
++
++/* LTECX: ltecxmux MODE */
++#define LTECX_MUX_MODE_IDX		0
++#define LTECX_MUX_MODE_WCI2		0x0
++#define LTECX_MUX_MODE_GPIO		0x1
++
++
++/* LTECX GPIO Information Index */
++#define LTECX_NVRAM_FSYNC_IDX	0
++#define LTECX_NVRAM_LTERX_IDX	1
++#define LTECX_NVRAM_LTETX_IDX	2
++#define LTECX_NVRAM_WLPRIO_IDX	3
++
++/* LTECX WCI2 Information Index */
++#define LTECX_NVRAM_WCI2IN_IDX	0
++#define LTECX_NVRAM_WCI2OUT_IDX	1
++
++/* LTECX: Macros to get GPIO/FNSEL/GCIGPIO */
++#define LTECX_EXTRACT_PADNUM(val, idx)	(getbit8(&(val), (idx)))
++#define LTECX_EXTRACT_FNSEL(val, idx)	(getbit4(&(val), (idx)))
++#define LTECX_EXTRACT_GCIGPIO(val, idx)	(getbit4(&(val), (idx)))
++
++/* WLAN channel numbers - used from wifi.h */
++
++/* WLAN BW */
++#define ECI_BW_20   0x0
++#define ECI_BW_25   0x1
++#define ECI_BW_30   0x2
++#define ECI_BW_35   0x3
++#define ECI_BW_40   0x4
++#define ECI_BW_45   0x5
++#define ECI_BW_50   0x6
++#define ECI_BW_ALL  0x7
++
++/* WLAN - number of antenna */
++#define WLAN_NUM_ANT1 TXANT_0
++#define WLAN_NUM_ANT2 TXANT_1
++
++/* otpctrl1 0xF4 */
++#define OTPC_FORCE_PWR_OFF	0x02000000
++/* chipcommon s/r registers introduced with cc rev >= 48 */
++#define CC_SR_CTL0_ENABLE_MASK             0x1
++#define CC_SR_CTL0_ENABLE_SHIFT              0
++#define CC_SR_CTL0_EN_SR_ENG_CLK_SHIFT       1 /* sr_clk to sr_memory enable */
++#define CC_SR_CTL0_RSRC_TRIGGER_SHIFT        2 /* Rising edge resource trigger 0 to sr_engine  */
++#define CC_SR_CTL0_MIN_DIV_SHIFT             6 /* Min division value for fast clk in sr_engine */
++#define CC_SR_CTL0_EN_SBC_STBY_SHIFT        16 /* Allow Subcore mem StandBy? */
++#define CC_SR_CTL0_EN_SR_ALP_CLK_MASK_SHIFT 18
++#define CC_SR_CTL0_EN_SR_HT_CLK_SHIFT       19
++#define CC_SR_CTL0_ALLOW_PIC_SHIFT          20 /* Allow pic to separate power domains */
++#define CC_SR_CTL0_MAX_SR_LQ_CLK_CNT_SHIFT  25
++#define CC_SR_CTL0_EN_MEM_DISABLE_FOR_SLEEP 30
++
++#define CC_SR_CTL1_SR_INIT_MASK             0x3FF
++#define CC_SR_CTL1_SR_INIT_SHIFT            0
++
++#define	ECI_INLO_PKTDUR_MASK	0x000000f0 /* [7:4] - 4 bits */
++#define ECI_INLO_PKTDUR_SHIFT	4
++
++/* gci chip control bits */
++#define GCI_GPIO_CHIPCTRL_ENAB_IN_BIT		0
++#define GCI_GPIO_CHIPCTRL_ENAB_OP_BIT		1
++#define GCI_GPIO_CHIPCTRL_INVERT_BIT		2
++#define GCI_GPIO_CHIPCTRL_PULLUP_BIT		3
++#define GCI_GPIO_CHIPCTRL_PULLDN_BIT		4
++#define GCI_GPIO_CHIPCTRL_ENAB_BTSIG_BIT	5
++#define GCI_GPIO_CHIPCTRL_ENAB_OD_OP_BIT	6
++#define GCI_GPIO_CHIPCTRL_ENAB_EXT_GPIO_BIT	7
++
++/* gci GPIO input status bits */
++#define GCI_GPIO_STS_VALUE_BIT			0
++#define GCI_GPIO_STS_POS_EDGE_BIT		1
++#define GCI_GPIO_STS_NEG_EDGE_BIT		2
++#define GCI_GPIO_STS_FAST_EDGE_BIT		3
++#define GCI_GPIO_STS_CLEAR			0xF
++
++#define GCI_GPIO_STS_VALUE	(1 << GCI_GPIO_STS_VALUE_BIT)
++
++/* SR Power Control */
++#define SRPWR_DMN0_PCIE			(0)				/* PCIE */
++#define SRPWR_DMN0_PCIE_SHIFT		(SRPWR_DMN0_PCIE)		/* PCIE */
++#define SRPWR_DMN0_PCIE_MASK		(1 << SRPWR_DMN0_PCIE_SHIFT)	/* PCIE */
++#define SRPWR_DMN1_ARMBPSD		(1)				/* ARM/BP/SDIO */
++#define SRPWR_DMN1_ARMBPSD_SHIFT	(SRPWR_DMN1_ARMBPSD)		/* ARM/BP/SDIO */
++#define SRPWR_DMN1_ARMBPSD_MASK		(1 << SRPWR_DMN1_ARMBPSD_SHIFT)	/* ARM/BP/SDIO */
++#define SRPWR_DMN2_MACAUX		(2)				/* MAC/Phy Aux */
++#define SRPWR_DMN2_MACAUX_SHIFT		(SRPWR_DMN2_MACAUX)		/* MAC/Phy Aux */
++#define SRPWR_DMN2_MACAUX_MASK		(1 << SRPWR_DMN2_MACAUX_SHIFT)	/* MAC/Phy Aux */
++#define SRPWR_DMN3_MACMAIN		(3)				/* MAC/Phy Main */
++#define SRPWR_DMN3_MACMAIN_SHIFT	(SRPWR_DMN3_MACMAIN)	/* MAC/Phy Main */
++#define SRPWR_DMN3_MACMAIN_MASK		(1 << SRPWR_DMN3_MACMAIN_SHIFT)	/* MAC/Phy Main */
++#define SRPWR_DMN_ALL_MASK		(0xF)
++
++#define SRPWR_REQON_SHIFT		(8)	/* PowerOnRequest[11:8] */
++#define SRPWR_REQON_MASK		(SRPWR_DMN_ALL_MASK << SRPWR_REQON_SHIFT)
++#define SRPWR_STATUS_SHIFT		(16)	/* ExtPwrStatus[19:16], RO */
++#define SRPWR_STATUS_MASK		(SRPWR_DMN_ALL_MASK << SRPWR_STATUS_SHIFT)
++#define SRPWR_DMN_SHIFT			(28)	/* PowerDomain[31:28], RO */
++#define SRPWR_DMN_MASK			(SRPWR_DMN_ALL_MASK << SRPWR_DMN_SHIFT)
++
++#endif	/* _SBCHIPC_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/sbconfig.h b/module_drivers/drivers/net/wireless/bcmdhd/include/sbconfig.h
+new file mode 100644
+index 000000000..ad9c408cd
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/sbconfig.h
+@@ -0,0 +1,285 @@
++/*
++ * Broadcom SiliconBackplane hardware register definitions.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: sbconfig.h 530150 2015-01-29 08:43:40Z $
++ */
++
++#ifndef	_SBCONFIG_H
++#define	_SBCONFIG_H
++
++/* cpp contortions to concatenate w/arg prescan */
++#ifndef PAD
++#define	_PADLINE(line)	pad ## line
++#define	_XSTR(line)	_PADLINE(line)
++#define	PAD		_XSTR(__LINE__)
++#endif
++
++/* enumeration in SB is based on the premise that cores are contiguos in the
++ * enumeration space.
++ */
++#define SB_BUS_SIZE		0x10000		/**< Each bus gets 64Kbytes for cores */
++#define SB_BUS_BASE(b)		(SI_ENUM_BASE + (b) * SB_BUS_SIZE)
++#define	SB_BUS_MAXCORES		(SB_BUS_SIZE / SI_CORE_SIZE)	/**< Max cores per bus */
++
++/*
++ * Sonics Configuration Space Registers.
++ */
++#define	SBCONFIGOFF		0xf00		/**< core sbconfig regs are top 256bytes of regs */
++#define	SBCONFIGSIZE		256		/**< sizeof (sbconfig_t) */
++
++#define SBIPSFLAG		0x08
++#define SBTPSFLAG		0x18
++#define	SBTMERRLOGA		0x48		/**< sonics >= 2.3 */
++#define	SBTMERRLOG		0x50		/**< sonics >= 2.3 */
++#define SBADMATCH3		0x60
++#define SBADMATCH2		0x68
++#define SBADMATCH1		0x70
++#define SBIMSTATE		0x90
++#define SBINTVEC		0x94
++#define SBTMSTATELOW		0x98
++#define SBTMSTATEHIGH		0x9c
++#define SBBWA0			0xa0
++#define SBIMCONFIGLOW		0xa8
++#define SBIMCONFIGHIGH		0xac
++#define SBADMATCH0		0xb0
++#define SBTMCONFIGLOW		0xb8
++#define SBTMCONFIGHIGH		0xbc
++#define SBBCONFIG		0xc0
++#define SBBSTATE		0xc8
++#define SBACTCNFG		0xd8
++#define	SBFLAGST		0xe8
++#define SBIDLOW			0xf8
++#define SBIDHIGH		0xfc
++
++/* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
++ * a few registers *below* that line. I think it would be very confusing to try
++ * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
++ */
++
++#define SBIMERRLOGA		0xea8
++#define SBIMERRLOG		0xeb0
++#define SBTMPORTCONNID0		0xed8
++#define SBTMPORTLOCK0		0xef8
++
++#if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__)
++
++typedef volatile struct _sbconfig {
++	uint32	PAD[2];
++	uint32	sbipsflag;		/**< initiator port ocp slave flag */
++	uint32	PAD[3];
++	uint32	sbtpsflag;		/**< target port ocp slave flag */
++	uint32	PAD[11];
++	uint32	sbtmerrloga;		/**< (sonics >= 2.3) */
++	uint32	PAD;
++	uint32	sbtmerrlog;		/**< (sonics >= 2.3) */
++	uint32	PAD[3];
++	uint32	sbadmatch3;		/**< address match3 */
++	uint32	PAD;
++	uint32	sbadmatch2;		/**< address match2 */
++	uint32	PAD;
++	uint32	sbadmatch1;		/**< address match1 */
++	uint32	PAD[7];
++	uint32	sbimstate;		/**< initiator agent state */
++	uint32	sbintvec;		/**< interrupt mask */
++	uint32	sbtmstatelow;		/**< target state */
++	uint32	sbtmstatehigh;		/**< target state */
++	uint32	sbbwa0;			/**< bandwidth allocation table0 */
++	uint32	PAD;
++	uint32	sbimconfiglow;		/**< initiator configuration */
++	uint32	sbimconfighigh;		/**< initiator configuration */
++	uint32	sbadmatch0;		/**< address match0 */
++	uint32	PAD;
++	uint32	sbtmconfiglow;		/**< target configuration */
++	uint32	sbtmconfighigh;		/**< target configuration */
++	uint32	sbbconfig;		/**< broadcast configuration */
++	uint32	PAD;
++	uint32	sbbstate;		/**< broadcast state */
++	uint32	PAD[3];
++	uint32	sbactcnfg;		/**< activate configuration */
++	uint32	PAD[3];
++	uint32	sbflagst;		/**< current sbflags */
++	uint32	PAD[3];
++	uint32	sbidlow;		/**< identification */
++	uint32	sbidhigh;		/**< identification */
++} sbconfig_t;
++
++#endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */
++
++/* sbipsflag */
++#define	SBIPS_INT1_MASK		0x3f		/**< which sbflags get routed to mips interrupt 1 */
++#define	SBIPS_INT1_SHIFT	0
++#define	SBIPS_INT2_MASK		0x3f00		/**< which sbflags get routed to mips interrupt 2 */
++#define	SBIPS_INT2_SHIFT	8
++#define	SBIPS_INT3_MASK		0x3f0000	/**< which sbflags get routed to mips interrupt 3 */
++#define	SBIPS_INT3_SHIFT	16
++#define	SBIPS_INT4_MASK		0x3f000000	/**< which sbflags get routed to mips interrupt 4 */
++#define	SBIPS_INT4_SHIFT	24
++
++/* sbtpsflag */
++#define	SBTPS_NUM0_MASK		0x3f		/**< interrupt sbFlag # generated by this core */
++#define	SBTPS_F0EN0		0x40		/**< interrupt is always sent on the backplane */
++
++/* sbtmerrlog */
++#define	SBTMEL_CM		0x00000007	/**< command */
++#define	SBTMEL_CI		0x0000ff00	/**< connection id */
++#define	SBTMEL_EC		0x0f000000	/**< error code */
++#define	SBTMEL_ME		0x80000000	/**< multiple error */
++
++/* sbimstate */
++#define	SBIM_PC			0xf		/**< pipecount */
++#define	SBIM_AP_MASK		0x30		/**< arbitration policy */
++#define	SBIM_AP_BOTH		0x00		/**< use both timeslaces and token */
++#define	SBIM_AP_TS		0x10		/**< use timesliaces only */
++#define	SBIM_AP_TK		0x20		/**< use token only */
++#define	SBIM_AP_RSV		0x30		/**< reserved */
++#define	SBIM_IBE		0x20000		/**< inbanderror */
++#define	SBIM_TO			0x40000		/**< timeout */
++#define	SBIM_BY			0x01800000	/**< busy (sonics >= 2.3) */
++#define	SBIM_RJ			0x02000000	/**< reject (sonics >= 2.3) */
++
++/* sbtmstatelow */
++#define	SBTML_RESET		0x0001		/**< reset */
++#define	SBTML_REJ_MASK		0x0006		/**< reject field */
++#define	SBTML_REJ		0x0002		/**< reject */
++#define	SBTML_TMPREJ		0x0004		/**< temporary reject, for error recovery */
++
++#define	SBTML_SICF_SHIFT	16	/**< Shift to locate the SI control flags in sbtml */
++
++/* sbtmstatehigh */
++#define	SBTMH_SERR		0x0001		/**< serror */
++#define	SBTMH_INT		0x0002		/**< interrupt */
++#define	SBTMH_BUSY		0x0004		/**< busy */
++#define	SBTMH_TO		0x0020		/**< timeout (sonics >= 2.3) */
++
++#define	SBTMH_SISF_SHIFT	16		/**< Shift to locate the SI status flags in sbtmh */
++
++/* sbbwa0 */
++#define	SBBWA_TAB0_MASK		0xffff		/**< lookup table 0 */
++#define	SBBWA_TAB1_MASK		0xffff		/**< lookup table 1 */
++#define	SBBWA_TAB1_SHIFT	16
++
++/* sbimconfiglow */
++#define	SBIMCL_STO_MASK		0x7		/**< service timeout */
++#define	SBIMCL_RTO_MASK		0x70		/**< request timeout */
++#define	SBIMCL_RTO_SHIFT	4
++#define	SBIMCL_CID_MASK		0xff0000	/**< connection id */
++#define	SBIMCL_CID_SHIFT	16
++
++/* sbimconfighigh */
++#define	SBIMCH_IEM_MASK		0xc		/**< inband error mode */
++#define	SBIMCH_TEM_MASK		0x30		/**< timeout error mode */
++#define	SBIMCH_TEM_SHIFT	4
++#define	SBIMCH_BEM_MASK		0xc0		/**< bus error mode */
++#define	SBIMCH_BEM_SHIFT	6
++
++/* sbadmatch0 */
++#define	SBAM_TYPE_MASK		0x3		/**< address type */
++#define	SBAM_AD64		0x4		/**< reserved */
++#define	SBAM_ADINT0_MASK	0xf8		/**< type0 size */
++#define	SBAM_ADINT0_SHIFT	3
++#define	SBAM_ADINT1_MASK	0x1f8		/**< type1 size */
++#define	SBAM_ADINT1_SHIFT	3
++#define	SBAM_ADINT2_MASK	0x1f8		/**< type2 size */
++#define	SBAM_ADINT2_SHIFT	3
++#define	SBAM_ADEN		0x400		/**< enable */
++#define	SBAM_ADNEG		0x800		/**< negative decode */
++#define	SBAM_BASE0_MASK		0xffffff00	/**< type0 base address */
++#define	SBAM_BASE0_SHIFT	8
++#define	SBAM_BASE1_MASK		0xfffff000	/**< type1 base address for the core */
++#define	SBAM_BASE1_SHIFT	12
++#define	SBAM_BASE2_MASK		0xffff0000	/**< type2 base address for the core */
++#define	SBAM_BASE2_SHIFT	16
++
++/* sbtmconfiglow */
++#define	SBTMCL_CD_MASK		0xff		/**< clock divide */
++#define	SBTMCL_CO_MASK		0xf800		/**< clock offset */
++#define	SBTMCL_CO_SHIFT		11
++#define	SBTMCL_IF_MASK		0xfc0000	/**< interrupt flags */
++#define	SBTMCL_IF_SHIFT		18
++#define	SBTMCL_IM_MASK		0x3000000	/**< interrupt mode */
++#define	SBTMCL_IM_SHIFT		24
++
++/* sbtmconfighigh */
++#define	SBTMCH_BM_MASK		0x3		/**< busy mode */
++#define	SBTMCH_RM_MASK		0x3		/**< retry mode */
++#define	SBTMCH_RM_SHIFT		2
++#define	SBTMCH_SM_MASK		0x30		/**< stop mode */
++#define	SBTMCH_SM_SHIFT		4
++#define	SBTMCH_EM_MASK		0x300		/**< sb error mode */
++#define	SBTMCH_EM_SHIFT		8
++#define	SBTMCH_IM_MASK		0xc00		/**< int mode */
++#define	SBTMCH_IM_SHIFT		10
++
++/* sbbconfig */
++#define	SBBC_LAT_MASK		0x3		/**< sb latency */
++#define	SBBC_MAX0_MASK		0xf0000		/**< maxccntr0 */
++#define	SBBC_MAX0_SHIFT		16
++#define	SBBC_MAX1_MASK		0xf00000	/**< maxccntr1 */
++#define	SBBC_MAX1_SHIFT		20
++
++/* sbbstate */
++#define	SBBS_SRD		0x1		/**< st reg disable */
++#define	SBBS_HRD		0x2		/**< hold reg disable */
++
++/* sbidlow */
++#define	SBIDL_CS_MASK		0x3		/**< config space */
++#define	SBIDL_AR_MASK		0x38		/**< # address ranges supported */
++#define	SBIDL_AR_SHIFT		3
++#define	SBIDL_SYNCH		0x40		/**< sync */
++#define	SBIDL_INIT		0x80		/**< initiator */
++#define	SBIDL_MINLAT_MASK	0xf00		/**< minimum backplane latency */
++#define	SBIDL_MINLAT_SHIFT	8
++#define	SBIDL_MAXLAT		0xf000		/**< maximum backplane latency */
++#define	SBIDL_MAXLAT_SHIFT	12
++#define	SBIDL_FIRST		0x10000		/**< this initiator is first */
++#define	SBIDL_CW_MASK		0xc0000		/**< cycle counter width */
++#define	SBIDL_CW_SHIFT		18
++#define	SBIDL_TP_MASK		0xf00000	/**< target ports */
++#define	SBIDL_TP_SHIFT		20
++#define	SBIDL_IP_MASK		0xf000000	/**< initiator ports */
++#define	SBIDL_IP_SHIFT		24
++#define	SBIDL_RV_MASK		0xf0000000	/**< sonics backplane revision code */
++#define	SBIDL_RV_SHIFT		28
++#define	SBIDL_RV_2_2		0x00000000	/**< version 2.2 or earlier */
++#define	SBIDL_RV_2_3		0x10000000	/**< version 2.3 */
++
++/* sbidhigh */
++#define	SBIDH_RC_MASK		0x000f		/**< revision code */
++#define	SBIDH_RCE_MASK		0x7000		/**< revision code extension field */
++#define	SBIDH_RCE_SHIFT		8
++#define	SBCOREREV(sbidh) \
++	((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
++#define	SBIDH_CC_MASK		0x8ff0		/**< core code */
++#define	SBIDH_CC_SHIFT		4
++#define	SBIDH_VC_MASK		0xffff0000	/**< vendor code */
++#define	SBIDH_VC_SHIFT		16
++
++#define	SB_COMMIT		0xfd8		/**< update buffered registers value */
++
++/* vendor codes */
++#define	SB_VEND_BCM		0x4243		/**< Broadcom's SB vendor code */
++
++#endif	/* _SBCONFIG_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/sbgci.h b/module_drivers/drivers/net/wireless/bcmdhd/include/sbgci.h
+new file mode 100644
+index 000000000..f04232dac
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/sbgci.h
+@@ -0,0 +1,248 @@
++/*
++ * SiliconBackplane GCI core hardware definitions
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: sbgci.h 612498 2016-01-14 05:09:09Z $
++ */
++
++#ifndef _SBGCI_H
++#define _SBGCI_H
++
++#if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__)
++
++/* cpp contortions to concatenate w/arg prescan */
++#ifndef PAD
++#define	_PADLINE(line)	pad ## line
++#define	_XSTR(line)	_PADLINE(line)
++#define	PAD		_XSTR(__LINE__)
++#endif	/* PAD */
++
++#define GCI_OFFSETOF(sih, reg) \
++	(AOB_ENAB(sih) ? OFFSETOF(gciregs_t, reg) : OFFSETOF(chipcregs_t, reg))
++#define GCI_CORE_IDX(sih) (AOB_ENAB(sih) ? si_findcoreidx(sih, GCI_CORE_ID, 0) : SI_CC_IDX)
++
++typedef volatile struct {
++	uint32	gci_corecaps0;		/* 0x000 */
++	uint32	gci_corecaps1;		/* 0x004 */
++	uint32	gci_corecaps2;		/* 0x008 */
++	uint32	gci_corectrl;		/* 0x00c */
++	uint32	gci_corestat;		/* 0x010 */
++	uint32	gci_intstat;		/* 0x014 */
++	uint32	gci_intmask;		/* 0x018 */
++	uint32	gci_wakemask;		/* 0x01c */
++	uint32	gci_levelintstat;	/* 0x020 */
++	uint32	gci_eventintstat;	/* 0x024 */
++	uint32	gci_wakelevelintstat;	/* 0x028 */
++	uint32	gci_wakeeventintstat;	/* 0x02c */
++	uint32	semaphoreintstatus;	/* 0x030 */
++	uint32	semaphoreintmask;	/* 0x034 */
++	uint32	semaphorerequest;	/* 0x038 */
++	uint32	semaphorereserve;	/* 0x03c */
++	uint32	gci_indirect_addr;	/* 0x040 */
++	uint32	gci_gpioctl;		/* 0x044 */
++	uint32	gci_gpiostatus;		/* 0x048 */
++	uint32	gci_gpiomask;		/* 0x04c */
++	uint32	eventsummary;		/* 0x050 */
++	uint32	gci_miscctl;		/* 0x054 */
++	uint32	gci_gpiointmask;	/* 0x058 */
++	uint32	gci_gpiowakemask;	/* 0x05c */
++	uint32	gci_input[32];		/* 0x060 */
++	uint32	gci_event[32];		/* 0x0e0 */
++	uint32	gci_output[4];		/* 0x160 */
++	uint32	gci_control_0;		/* 0x170 */
++	uint32	gci_control_1;		/* 0x174 */
++	uint32	gci_intpolreg;		/* 0x178 */
++	uint32	gci_levelintmask;	/* 0x17c */
++	uint32	gci_eventintmask;	/* 0x180 */
++	uint32	wakelevelintmask;	/* 0x184 */
++	uint32	wakeeventintmask;	/* 0x188 */
++	uint32	hwmask;			/* 0x18c */
++	uint32	PAD;
++	uint32	gci_inbandeventintmask;	/* 0x194 */
++	uint32	PAD;
++	uint32	gci_inbandeventstatus;	/* 0x19c */
++	uint32	gci_seciauxtx;		/* 0x1a0 */
++	uint32	gci_seciauxrx;		/* 0x1a4 */
++	uint32	gci_secitx_datatag;	/* 0x1a8 */
++	uint32	gci_secirx_datatag;	/* 0x1ac */
++	uint32	gci_secitx_datamask;	/* 0x1b0 */
++	uint32	gci_seciusef0tx_reg;	/* 0x1b4 */
++	uint32	gci_secif0tx_offset;	/* 0x1b8 */
++	uint32	gci_secif0rx_offset;	/* 0x1bc */
++	uint32	gci_secif1tx_offset;	/* 0x1c0 */
++	uint32	gci_rxfifo_common_ctrl;	/* 0x1c4 */
++	uint32	gci_rxfifoctrl;		/* 0x1c8 */
++	uint32	gci_hw_sema_status;	/* 0x1cc */
++	uint32	gci_seciuartescval;	/* 0x1d0 */
++	uint32	gic_seciuartautobaudctr;	/* 0x1d4 */
++	uint32	gci_secififolevel;	/* 0x1d8 */
++	uint32	gci_seciuartdata;	/* 0x1dc */
++	uint32	gci_secibauddiv;	/* 0x1e0 */
++	uint32	gci_secifcr;		/* 0x1e4 */
++	uint32	gci_secilcr;		/* 0x1e8 */
++	uint32	gci_secimcr;		/* 0x1ec */
++	uint32	gci_secilsr;		/* 0x1f0 */
++	uint32	gci_secimsr;		/* 0x1f4 */
++	uint32	gci_baudadj;		/* 0x1f8 */
++	uint32	gci_inbandintmask;	/* 0x1fc */
++	uint32  gci_chipctrl;		/* 0x200 */
++	uint32  gci_chipsts; 		/* 0x204 */
++	uint32	gci_gpioout; 		/* 0x208 */
++	uint32	gci_gpioout_read; 	/* 0x20C */
++	uint32	gci_mpwaketx; 		/* 0x210 */
++	uint32	gci_mpwakedetect; 	/* 0x214 */
++	uint32	gci_seciin_ctrl; 	/* 0x218 */
++	uint32	gci_seciout_ctrl; 	/* 0x21C */
++	uint32	gci_seciin_auxfifo_en; 	/* 0x220 */
++	uint32	gci_seciout_txen_txbr; 	/* 0x224 */
++	uint32	gci_seciin_rxbrstatus; 	/* 0x228 */
++	uint32	gci_seciin_rxerrstatus; /* 0x22C */
++	uint32	gci_seciin_fcstatus; 	/* 0x230 */
++	uint32	gci_seciout_txstatus; 	/* 0x234 */
++	uint32	gci_seciout_txbrstatus; /* 0x238 */
++	uint32	wlan_mem_info;				/* 0x23C */
++	uint32	wlan_bankxinfo;				/* 0x240 */
++	uint32	bt_smem_select;				/* 0x244 */
++	uint32	bt_smem_stby;				/* 0x248 */
++	uint32	bt_smem_status;				/* 0x24C */
++	uint32	wlan_bankxactivepda;			/* 0x250 */
++	uint32	wlan_bankxsleeppda;			/* 0x254 */
++	uint32	wlan_bankxkill;				/* 0x258 */
++	uint32	PAD[41];
++	uint32	gci_chipid;		/* 0x300 */
++	uint32	PAD[3];
++	uint32	otpstatus;		/* 0x310 */
++	uint32	otpcontrol;		/* 0x314 */
++	uint32	otpprog;		/* 0x318 */
++	uint32	otplayout;		/* 0x31c */
++	uint32	otplayoutextension;	/* 0x320 */
++	uint32	otpcontrol1;		/* 0x324 */
++	uint32	otpprogdata;		/* 0x328 */
++	uint32	PAD[52];
++	uint32	otpECCstatus;		/* 0x3FC */
++	uint32	PAD[512];
++	uint32	lhl_core_capab_adr;			/* 0xC00 */
++	uint32	lhl_main_ctl_adr;			/* 0xC04 */
++	uint32	lhl_pmu_ctl_adr;			/* 0xC08 */
++	uint32	lhl_extlpo_ctl_adr;			/* 0xC0C */
++	uint32	lpo_ctl_adr;				/* 0xC10 */
++	uint32	lhl_lpo2_ctl_adr;			/* 0xC14 */
++	uint32	lhl_osc32k_ctl_adr;			/* 0xC18 */
++	uint32	lhl_clk_status_adr;			/* 0xC1C */
++	uint32	lhl_clk_det_ctl_adr;			/* 0xC20 */
++	uint32	lhl_clk_sel_adr;			/* 0xC24 */
++	uint32	hidoff_cnt_adr[2];			/* 0xC28-0xC2C */
++	uint32	lhl_autoclk_ctl_adr;			/* 0xC30 */
++	uint32	PAD;					/* reserved */
++	uint32	lhl_hibtim_adr;				/* 0xC38 */
++	uint32	lhl_wl_ilp_val_adr;			/* 0xC3C */
++	uint32	lhl_wl_armtim0_intrp_adr;		/* 0xC40 */
++	uint32	lhl_wl_armtim0_st_adr;			/* 0xC44 */
++	uint32	lhl_wl_armtim0_adr;			/* 0xC48 */
++	uint32	PAD[9];					/* 0xC4C-0xC6C */
++	uint32 lhl_wl_mactim0_intrp_adr;		/* 0xC70 */
++	uint32 lhl_wl_mactim0_st_adr;			/* 0xC74 */
++	uint32 lhl_wl_mactim_int0_adr;			/* 0xC78 */
++	uint32 lhl_wl_mactim_frac0_adr;			/* 0xC7C */
++	uint32 lhl_wl_mactim1_intrp_adr;		/* 0xC80 */
++	uint32 lhl_wl_mactim1_st_adr;			/* 0xC84 */
++	uint32 lhl_wl_mactim_int1_adr;			/* 0xC88 */
++	uint32 lhl_wl_mactim_frac1_adr;			/* 0xC8C */
++	uint32	PAD[8];					/* 0xC90-0xCAC */
++	uint32	gpio_int_en_port_adr[4];		/* 0xCB0-0xCBC */
++	uint32	gpio_int_st_port_adr[4];		/* 0xCC0-0xCCC */
++	uint32	gpio_ctrl_iocfg_p_adr[64];		/* 0xCD0-0xDCC */
++	uint32	gpio_gctrl_iocfg_p0_p39_adr;		/* 0xDD0 */
++	uint32	gpio_gdsctrl_iocfg_p0_p25_p30_p39_adr;	/* 0xDD4 */
++	uint32	gpio_gdsctrl_iocfg_p26_p29_adr;		/* 0xDD8 */
++	uint32	PAD[8];					/* 0xDDC-0xDF8 */
++	uint32	lhl_gpio_din0_adr;			/* 0xDFC */
++	uint32	lhl_gpio_din1_adr;			/* 0xE00 */
++	uint32	lhl_wkup_status_adr;			/* 0xE04 */
++	uint32	lhl_ctl_adr;				/* 0xE08 */
++	uint32	lhl_adc_ctl_adr;			/* 0xE0C */
++	uint32	lhl_qdxyz_in_dly_adr;			/* 0xE10 */
++	uint32	lhl_optctl_adr;				/* 0xE14 */
++	uint32	lhl_optct2_adr;				/* 0xE18 */
++	uint32	lhl_scanp_cntr_init_val_adr;		/* 0xE1C */
++	uint32	lhl_opt_togg_val_adr[6];		/* 0xE20-0xE34 */
++	uint32	lhl_optx_smp_val_adr;			/* 0xE38 */
++	uint32	lhl_opty_smp_val_adr;			/* 0xE3C */
++	uint32	lhl_optz_smp_val_adr;			/* 0xE40 */
++	uint32	lhl_hidoff_keepstate_adr[3];		/* 0xE44-0xE4C */
++	uint32	lhl_bt_slmboot_ctl0_adr[4];		/* 0xE50-0xE5C */
++	uint32	lhl_wl_fw_ctl;				/* 0xE60 */
++	uint32	lhl_wl_hw_ctl_adr[2];			/* 0xE64-0xE68 */
++	uint32	lhl_bt_hw_ctl_adr;			/* 0xE6C */
++	uint32	lhl_top_pwrseq_en_adr;			/* 0xE70 */
++	uint32	lhl_top_pwrdn_ctl_adr;			/* 0xE74 */
++	uint32	lhl_top_pwrup_ctl_adr;			/* 0xE78 */
++	uint32	lhl_top_pwrseq_ctl_adr;			/* 0xE7C */
++	uint32	lhl_top_pwrdn2_ctl_adr;			/* 0xE80 */
++	uint32	lhl_top_pwrup2_ctl_adr;			/* 0xE84 */
++	uint32	wpt_regon_intrp_cfg_adr;		/* 0xE88 */
++	uint32	bt_regon_intrp_cfg_adr;			/* 0xE8C */
++	uint32	wl_regon_intrp_cfg_adr;			/* 0xE90 */
++	uint32	regon_intrp_st_adr;			/* 0xE94 */
++	uint32	regon_intrp_en_adr;			/* 0xE98 */
++} gciregs_t;
++
++#define	GCI_CAP0_REV_MASK	0x000000ff
++
++/* GCI Capabilities registers */
++#define GCI_CORE_CAP_0_COREREV_MASK			0xFF
++#define GCI_CORE_CAP_0_COREREV_SHIFT			0
++
++#define GCI_INDIRECT_ADDRESS_REG_REGINDEX_MASK		0x3F
++#define GCI_INDIRECT_ADDRESS_REG_REGINDEX_SHIFT		0
++#define GCI_INDIRECT_ADDRESS_REG_GPIOINDEX_MASK		0xF
++#define GCI_INDIRECT_ADDRESS_REG_GPIOINDEX_SHIFT	16
++
++#define WLAN_BANKX_SLEEPPDA_REG_SLEEPPDA_MASK		0xFFFF
++
++#define WLAN_BANKX_PKILL_REG_SLEEPPDA_MASK		0x1
++
++/* WLAN BankXInfo Register */
++#define WLAN_BANKXINFO_BANK_SIZE_MASK			0x00FFF000
++#define WLAN_BANKXINFO_BANK_SIZE_SHIFT			12
++
++/* WLAN Mem Info Register */
++#define WLAN_MEM_INFO_REG_NUMSOCRAMBANKS_MASK		0x000000FF
++#define WLAN_MEM_INFO_REG_NUMSOCRAMBANKS_SHIFT		0
++
++#define WLAN_MEM_INFO_REG_NUMD11MACBM_MASK		0x0000FF00
++#define WLAN_MEM_INFO_REG_NUMD11MACBM_SHIFT		8
++
++#define WLAN_MEM_INFO_REG_NUMD11MACUCM_MASK		0x00FF0000
++#define WLAN_MEM_INFO_REG_NUMD11MACUCM_SHIFT		16
++
++#define WLAN_MEM_INFO_REG_NUMD11MACSHM_MASK		0xFF000000
++#define WLAN_MEM_INFO_REG_NUMD11MACSHM_SHIFT		24
++
++
++#endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */
++
++
++#endif	/* _SBGCI_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/sbhnddma.h b/module_drivers/drivers/net/wireless/bcmdhd/include/sbhnddma.h
+new file mode 100644
+index 000000000..6d10d6ad3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/sbhnddma.h
+@@ -0,0 +1,429 @@
++/*
++ * Generic Broadcom Home Networking Division (HND) DMA engine HW interface
++ * This supports the following chips: BCM42xx, 44xx, 47xx .
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: sbhnddma.h 615537 2016-01-28 00:46:34Z $
++ */
++
++#ifndef	_sbhnddma_h_
++#define	_sbhnddma_h_
++
++/* DMA structure:
++ *  support two DMA engines: 32 bits address or 64 bit addressing
++ *  basic DMA register set is per channel(transmit or receive)
++ *  a pair of channels is defined for convenience
++ */
++
++
++/* 32 bits addressing */
++
++/** dma registers per channel(xmt or rcv) */
++typedef volatile struct {
++	uint32	control;		/**< enable, et al */
++	uint32	addr;			/**< descriptor ring base address (4K aligned) */
++	uint32	ptr;			/**< last descriptor posted to chip */
++	uint32	status;			/**< current active descriptor, et al */
++} dma32regs_t;
++
++typedef volatile struct {
++	dma32regs_t	xmt;		/**< dma tx channel */
++	dma32regs_t	rcv;		/**< dma rx channel */
++} dma32regp_t;
++
++typedef volatile struct {	/* diag access */
++	uint32	fifoaddr;		/**< diag address */
++	uint32	fifodatalow;		/**< low 32bits of data */
++	uint32	fifodatahigh;		/**< high 32bits of data */
++	uint32	pad;			/**< reserved */
++} dma32diag_t;
++
++/**
++ * DMA Descriptor
++ * Descriptors are only read by the hardware, never written back.
++ */
++typedef volatile struct {
++	uint32	ctrl;		/**< misc control bits & bufcount */
++	uint32	addr;		/**< data buffer address */
++} dma32dd_t;
++
++/** Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page. */
++#define	D32RINGALIGN_BITS	12
++#define	D32MAXRINGSZ		(1 << D32RINGALIGN_BITS)
++#define	D32RINGALIGN		(1 << D32RINGALIGN_BITS)
++
++#define	D32MAXDD	(D32MAXRINGSZ / sizeof (dma32dd_t))
++
++/* transmit channel control */
++#define	XC_XE		((uint32)1 << 0)	/**< transmit enable */
++#define	XC_SE		((uint32)1 << 1)	/**< transmit suspend request */
++#define	XC_LE		((uint32)1 << 2)	/**< loopback enable */
++#define	XC_FL		((uint32)1 << 4)	/**< flush request */
++#define XC_MR_MASK	0x000001C0		/**< Multiple outstanding reads */
++#define XC_MR_SHIFT	6
++#define	XC_PD		((uint32)1 << 11)	/**< parity check disable */
++#define	XC_AE		((uint32)3 << 16)	/**< address extension bits */
++#define	XC_AE_SHIFT	16
++#define XC_BL_MASK	0x001C0000		/**< BurstLen bits */
++#define XC_BL_SHIFT	18
++#define XC_PC_MASK	0x00E00000		/**< Prefetch control */
++#define XC_PC_SHIFT	21
++#define XC_PT_MASK	0x03000000		/**< Prefetch threshold */
++#define XC_PT_SHIFT	24
++
++/** Multiple outstanding reads */
++#define DMA_MR_1	0
++#define DMA_MR_2	1
++#define DMA_MR_4	2
++#define DMA_MR_8	3
++#define DMA_MR_12	4
++#define DMA_MR_16	5
++#define DMA_MR_20	6
++#define DMA_MR_32	7
++
++/** DMA Burst Length in bytes */
++#define DMA_BL_16	0
++#define DMA_BL_32	1
++#define DMA_BL_64	2
++#define DMA_BL_128	3
++#define DMA_BL_256	4
++#define DMA_BL_512	5
++#define DMA_BL_1024	6
++
++/** Prefetch control */
++#define DMA_PC_0	0
++#define DMA_PC_4	1
++#define DMA_PC_8	2
++#define DMA_PC_16	3
++/* others: reserved */
++
++/** Prefetch threshold */
++#define DMA_PT_1	0
++#define DMA_PT_2	1
++#define DMA_PT_4	2
++#define DMA_PT_8	3
++
++/** Channel Switch */
++#define DMA_CS_OFF	0
++#define DMA_CS_ON	1
++
++/* transmit descriptor table pointer */
++#define	XP_LD_MASK	0xfff			/**< last valid descriptor */
++
++/* transmit channel status */
++#define	XS_CD_MASK	0x0fff			/**< current descriptor pointer */
++#define	XS_XS_MASK	0xf000			/**< transmit state */
++#define	XS_XS_SHIFT	12
++#define	XS_XS_DISABLED	0x0000			/**< disabled */
++#define	XS_XS_ACTIVE	0x1000			/**< active */
++#define	XS_XS_IDLE	0x2000			/**< idle wait */
++#define	XS_XS_STOPPED	0x3000			/**< stopped */
++#define	XS_XS_SUSP	0x4000			/**< suspend pending */
++#define	XS_XE_MASK	0xf0000			/**< transmit errors */
++#define	XS_XE_SHIFT	16
++#define	XS_XE_NOERR	0x00000			/**< no error */
++#define	XS_XE_DPE	0x10000			/**< descriptor protocol error */
++#define	XS_XE_DFU	0x20000			/**< data fifo underrun */
++#define	XS_XE_BEBR	0x30000			/**< bus error on buffer read */
++#define	XS_XE_BEDA	0x40000			/**< bus error on descriptor access */
++#define	XS_AD_MASK	0xfff00000		/**< active descriptor */
++#define	XS_AD_SHIFT	20
++
++/* receive channel control */
++#define	RC_RE		((uint32)1 << 0)	/**< receive enable */
++#define	RC_RO_MASK	0xfe			/**< receive frame offset */
++#define	RC_RO_SHIFT	1
++#define	RC_FM		((uint32)1 << 8)	/**< direct fifo receive (pio) mode */
++#define	RC_SH		((uint32)1 << 9)	/**< separate rx header descriptor enable */
++#define	RC_OC		((uint32)1 << 10)	/**< overflow continue */
++#define	RC_PD		((uint32)1 << 11)	/**< parity check disable */
++#define	RC_AE		((uint32)3 << 16)	/**< address extension bits */
++#define	RC_AE_SHIFT	16
++#define RC_BL_MASK	0x001C0000		/**< BurstLen bits */
++#define RC_BL_SHIFT	18
++#define RC_PC_MASK	0x00E00000		/**< Prefetch control */
++#define RC_PC_SHIFT	21
++#define RC_PT_MASK	0x03000000		/**< Prefetch threshold */
++#define RC_PT_SHIFT	24
++#define RC_WAITCMP_MASK 0x00001000
++#define RC_WAITCMP_SHIFT 12
++/* receive descriptor table pointer */
++#define	RP_LD_MASK	0xfff			/**< last valid descriptor */
++
++/* receive channel status */
++#define	RS_CD_MASK	0x0fff			/**< current descriptor pointer */
++#define	RS_RS_MASK	0xf000			/**< receive state */
++#define	RS_RS_SHIFT	12
++#define	RS_RS_DISABLED	0x0000			/**< disabled */
++#define	RS_RS_ACTIVE	0x1000			/**< active */
++#define	RS_RS_IDLE	0x2000			/**< idle wait */
++#define	RS_RS_STOPPED	0x3000			/**< reserved */
++#define	RS_RE_MASK	0xf0000			/**< receive errors */
++#define	RS_RE_SHIFT	16
++#define	RS_RE_NOERR	0x00000			/**< no error */
++#define	RS_RE_DPE	0x10000			/**< descriptor protocol error */
++#define	RS_RE_DFO	0x20000			/**< data fifo overflow */
++#define	RS_RE_BEBW	0x30000			/**< bus error on buffer write */
++#define	RS_RE_BEDA	0x40000			/**< bus error on descriptor access */
++#define	RS_AD_MASK	0xfff00000		/**< active descriptor */
++#define	RS_AD_SHIFT	20
++
++/* fifoaddr */
++#define	FA_OFF_MASK	0xffff			/**< offset */
++#define	FA_SEL_MASK	0xf0000			/**< select */
++#define	FA_SEL_SHIFT	16
++#define	FA_SEL_XDD	0x00000			/**< transmit dma data */
++#define	FA_SEL_XDP	0x10000			/**< transmit dma pointers */
++#define	FA_SEL_RDD	0x40000			/**< receive dma data */
++#define	FA_SEL_RDP	0x50000			/**< receive dma pointers */
++#define	FA_SEL_XFD	0x80000			/**< transmit fifo data */
++#define	FA_SEL_XFP	0x90000			/**< transmit fifo pointers */
++#define	FA_SEL_RFD	0xc0000			/**< receive fifo data */
++#define	FA_SEL_RFP	0xd0000			/**< receive fifo pointers */
++#define	FA_SEL_RSD	0xe0000			/**< receive frame status data */
++#define	FA_SEL_RSP	0xf0000			/**< receive frame status pointers */
++
++/* descriptor control flags */
++#define	CTRL_BC_MASK	0x00001fff		/**< buffer byte count, real data len must <= 4KB */
++#define	CTRL_AE		((uint32)3 << 16)	/**< address extension bits */
++#define	CTRL_AE_SHIFT	16
++#define	CTRL_PARITY	((uint32)3 << 18)	/**< parity bit */
++#define	CTRL_EOT	((uint32)1 << 28)	/**< end of descriptor table */
++#define	CTRL_IOC	((uint32)1 << 29)	/**< interrupt on completion */
++#define	CTRL_EOF	((uint32)1 << 30)	/**< end of frame */
++#define	CTRL_SOF	((uint32)1 << 31)	/**< start of frame */
++
++/** control flags in the range [27:20] are core-specific and not defined here */
++#define	CTRL_CORE_MASK	0x0ff00000
++
++/* 64 bits addressing */
++
++/** dma registers per channel(xmt or rcv) */
++typedef volatile struct {
++	uint32	control;	/**< enable, et al */
++	uint32	ptr;		/**< last descriptor posted to chip */
++	uint32	addrlow;	/**< descriptor ring base address low 32-bits (8K aligned) */
++	uint32	addrhigh;	/**< descriptor ring base address bits 63:32 (8K aligned) */
++	uint32	status0;	/**< current descriptor, xmt state */
++	uint32	status1;	/**< active descriptor, xmt error */
++} dma64regs_t;
++
++typedef volatile struct {
++	dma64regs_t	tx;		/**< dma64 tx channel */
++	dma64regs_t	rx;		/**< dma64 rx channel */
++} dma64regp_t;
++
++typedef volatile struct {		/**< diag access */
++	uint32	fifoaddr;		/**< diag address */
++	uint32	fifodatalow;		/**< low 32bits of data */
++	uint32	fifodatahigh;		/**< high 32bits of data */
++	uint32	pad;			/**< reserved */
++} dma64diag_t;
++
++/**
++ * DMA Descriptor
++ * Descriptors are only read by the hardware, never written back.
++ */
++typedef volatile struct {
++	uint32	ctrl1;		/**< misc control bits */
++	uint32	ctrl2;		/**< buffer count and address extension */
++	uint32	addrlow;	/**< memory address of the date buffer, bits 31:0 */
++	uint32	addrhigh;	/**< memory address of the date buffer, bits 63:32 */
++} dma64dd_t;
++
++/**
++ * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss.
++ */
++#define D64RINGALIGN_BITS	13
++#define	D64MAXRINGSZ		(1 << D64RINGALIGN_BITS)
++#define	D64RINGBOUNDARY		(1 << D64RINGALIGN_BITS)
++
++#define	D64MAXDD	(D64MAXRINGSZ / sizeof (dma64dd_t))
++
++/** for cores with large descriptor ring support, descriptor ring size can be up to 4096 */
++#define	D64MAXDD_LARGE		((1 << 16) / sizeof (dma64dd_t))
++
++/**
++ * for cores with large descriptor ring support (4k descriptors), descriptor ring cannot cross
++ * 64K boundary
++ */
++#define	D64RINGBOUNDARY_LARGE	(1 << 16)
++
++/*
++ * Default DMA Burstlen values for USBRev >= 12 and SDIORev >= 11.
++ * When this field contains the value N, the burst length is 2**(N + 4) bytes.
++ */
++#define D64_DEF_USBBURSTLEN     2
++#define D64_DEF_SDIOBURSTLEN    1
++
++
++#ifndef D64_USBBURSTLEN
++#define D64_USBBURSTLEN	DMA_BL_64
++#endif
++#ifndef D64_SDIOBURSTLEN
++#define D64_SDIOBURSTLEN	DMA_BL_32
++#endif
++
++/* transmit channel control */
++#define	D64_XC_XE		0x00000001	/**< transmit enable */
++#define	D64_XC_SE		0x00000002	/**< transmit suspend request */
++#define	D64_XC_LE		0x00000004	/**< loopback enable */
++#define	D64_XC_FL		0x00000010	/**< flush request */
++#define D64_XC_MR_MASK		0x000001C0	/**< Multiple outstanding reads */
++#define D64_XC_MR_SHIFT		6
++#define D64_XC_CS_SHIFT		9		/**< channel switch enable */
++#define D64_XC_CS_MASK		0x00000200      /**< channel switch enable */
++#define	D64_XC_PD		0x00000800	/**< parity check disable */
++#define	D64_XC_AE		0x00030000	/**< address extension bits */
++#define	D64_XC_AE_SHIFT		16
++#define D64_XC_BL_MASK		0x001C0000	/**< BurstLen bits */
++#define D64_XC_BL_SHIFT		18
++#define D64_XC_PC_MASK		0x00E00000		/**< Prefetch control */
++#define D64_XC_PC_SHIFT		21
++#define D64_XC_PT_MASK		0x03000000		/**< Prefetch threshold */
++#define D64_XC_PT_SHIFT		24
++
++/* transmit descriptor table pointer */
++#define	D64_XP_LD_MASK		0x00001fff	/**< last valid descriptor */
++
++/* transmit channel status */
++#define	D64_XS0_CD_MASK		(di->d64_xs0_cd_mask)	/**< current descriptor pointer */
++#define	D64_XS0_XS_MASK		0xf0000000     	/**< transmit state */
++#define	D64_XS0_XS_SHIFT		28
++#define	D64_XS0_XS_DISABLED	0x00000000	/**< disabled */
++#define	D64_XS0_XS_ACTIVE	0x10000000	/**< active */
++#define	D64_XS0_XS_IDLE		0x20000000	/**< idle wait */
++#define	D64_XS0_XS_STOPPED	0x30000000	/**< stopped */
++#define	D64_XS0_XS_SUSP		0x40000000	/**< suspend pending */
++
++#define	D64_XS1_AD_MASK		(di->d64_xs1_ad_mask)	/**< active descriptor */
++#define	D64_XS1_XE_MASK		0xf0000000     	/**< transmit errors */
++#define	D64_XS1_XE_SHIFT		28
++#define	D64_XS1_XE_NOERR	0x00000000	/**< no error */
++#define	D64_XS1_XE_DPE		0x10000000	/**< descriptor protocol error */
++#define	D64_XS1_XE_DFU		0x20000000	/**< data fifo underrun */
++#define	D64_XS1_XE_DTE		0x30000000	/**< data transfer error */
++#define	D64_XS1_XE_DESRE	0x40000000	/**< descriptor read error */
++#define	D64_XS1_XE_COREE	0x50000000	/**< core error */
++
++/* receive channel control */
++#define	D64_RC_RE		0x00000001	/**< receive enable */
++#define	D64_RC_RO_MASK		0x000000fe	/**< receive frame offset */
++#define	D64_RC_RO_SHIFT		1
++#define	D64_RC_FM		0x00000100	/**< direct fifo receive (pio) mode */
++#define	D64_RC_SH		0x00000200	/**< separate rx header descriptor enable */
++#define	D64_RC_SHIFT		9	/**< separate rx header descriptor enable */
++#define	D64_RC_OC		0x00000400	/**< overflow continue */
++#define	D64_RC_PD		0x00000800	/**< parity check disable */
++#define D64_RC_SA		0x00002000	/**< select active */
++#define D64_RC_GE		0x00004000	/**< Glom enable */
++#define	D64_RC_AE		0x00030000	/**< address extension bits */
++#define	D64_RC_AE_SHIFT		16
++#define D64_RC_BL_MASK		0x001C0000	/**< BurstLen bits */
++#define D64_RC_BL_SHIFT		18
++#define D64_RC_PC_MASK		0x00E00000	/**< Prefetch control */
++#define D64_RC_PC_SHIFT		21
++#define D64_RC_PT_MASK		0x03000000	/**< Prefetch threshold */
++#define D64_RC_PT_SHIFT		24
++#define D64_RC_WAITCMP_MASK	0x00001000
++#define D64_RC_WAITCMP_SHIFT	12
++
++/* flags for dma controller */
++#define DMA_CTRL_PEN		(1 << 0)	/**< partity enable */
++#define DMA_CTRL_ROC		(1 << 1)	/**< rx overflow continue */
++#define DMA_CTRL_RXMULTI	(1 << 2)	/**< allow rx scatter to multiple descriptors */
++#define DMA_CTRL_UNFRAMED	(1 << 3)	/**< Unframed Rx/Tx data */
++#define DMA_CTRL_USB_BOUNDRY4KB_WAR (1 << 4)
++#define DMA_CTRL_DMA_AVOIDANCE_WAR (1 << 5)	/**< DMA avoidance WAR for 4331 */
++#define DMA_CTRL_RXSINGLE	(1 << 6)	/**< always single buffer */
++#define DMA_CTRL_SDIO_RXGLOM	(1 << 7)	/**< DMA Rx glome is enabled */
++
++/* receive descriptor table pointer */
++#define	D64_RP_LD_MASK		0x00001fff	/**< last valid descriptor */
++
++/* receive channel status */
++#define	D64_RS0_CD_MASK		(di->d64_rs0_cd_mask)	/**< current descriptor pointer */
++#define	D64_RS0_RS_MASK		0xf0000000     	/**< receive state */
++#define	D64_RS0_RS_SHIFT		28
++#define	D64_RS0_RS_DISABLED	0x00000000	/**< disabled */
++#define	D64_RS0_RS_ACTIVE	0x10000000	/**< active */
++#define	D64_RS0_RS_IDLE		0x20000000	/**< idle wait */
++#define	D64_RS0_RS_STOPPED	0x30000000	/**< stopped */
++#define	D64_RS0_RS_SUSP		0x40000000	/**< suspend pending */
++
++#define	D64_RS1_AD_MASK		(di->d64_rs1_ad_mask)	/* active descriptor pointer */
++#define	D64_RS1_RE_MASK		0xf0000000	/* receive errors */
++#define	D64_RS1_RE_SHIFT		28
++#define	D64_RS1_RE_NOERR	0x00000000	/**< no error */
++#define	D64_RS1_RE_DPO		0x10000000	/**< descriptor protocol error */
++#define	D64_RS1_RE_DFU		0x20000000	/**< data fifo overflow */
++#define	D64_RS1_RE_DTE		0x30000000	/**< data transfer error */
++#define	D64_RS1_RE_DESRE	0x40000000	/**< descriptor read error */
++#define	D64_RS1_RE_COREE	0x50000000	/**< core error */
++
++/* fifoaddr */
++#define	D64_FA_OFF_MASK		0xffff		/**< offset */
++#define	D64_FA_SEL_MASK		0xf0000		/**< select */
++#define	D64_FA_SEL_SHIFT	16
++#define	D64_FA_SEL_XDD		0x00000		/**< transmit dma data */
++#define	D64_FA_SEL_XDP		0x10000		/**< transmit dma pointers */
++#define	D64_FA_SEL_RDD		0x40000		/**< receive dma data */
++#define	D64_FA_SEL_RDP		0x50000		/**< receive dma pointers */
++#define	D64_FA_SEL_XFD		0x80000		/**< transmit fifo data */
++#define	D64_FA_SEL_XFP		0x90000		/**< transmit fifo pointers */
++#define	D64_FA_SEL_RFD		0xc0000		/**< receive fifo data */
++#define	D64_FA_SEL_RFP		0xd0000		/**< receive fifo pointers */
++#define	D64_FA_SEL_RSD		0xe0000		/**< receive frame status data */
++#define	D64_FA_SEL_RSP		0xf0000		/**< receive frame status pointers */
++
++/* descriptor control flags 1 */
++#define D64_CTRL_COREFLAGS	0x0ff00000		/**< core specific flags */
++#define	D64_CTRL1_NOTPCIE	((uint32)1 << 18)	/**< buirst size control */
++#define	D64_CTRL1_EOT		((uint32)1 << 28)	/**< end of descriptor table */
++#define	D64_CTRL1_IOC		((uint32)1 << 29)	/**< interrupt on completion */
++#define	D64_CTRL1_EOF		((uint32)1 << 30)	/**< end of frame */
++#define	D64_CTRL1_SOF		((uint32)1 << 31)	/**< start of frame */
++
++/* descriptor control flags 2 */
++#define	D64_CTRL2_BC_MASK	0x00007fff /**< buffer byte count. real data len must <= 16KB */
++#define	D64_CTRL2_AE		0x00030000 /**< address extension bits */
++#define	D64_CTRL2_AE_SHIFT	16
++#define D64_CTRL2_PARITY	0x00040000      /* parity bit */
++
++/** control flags in the range [27:20] are core-specific and not defined here */
++#define	D64_CTRL_CORE_MASK	0x0ff00000
++
++#define D64_RX_FRM_STS_LEN	0x0000ffff	/**< frame length mask */
++#define D64_RX_FRM_STS_OVFL	0x00800000	/**< RxOverFlow */
++#define D64_RX_FRM_STS_DSCRCNT	0x0f000000 /**< no. of descriptors used - 1, d11corerev >= 22 */
++#define D64_RX_FRM_STS_DATATYPE	0xf0000000	/**< core-dependent data type */
++
++/** receive frame status */
++typedef volatile struct {
++	uint16 len;
++	uint16 flags;
++} dma_rxh_t;
++
++#endif	/* _sbhnddma_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/sbpcmcia.h b/module_drivers/drivers/net/wireless/bcmdhd/include/sbpcmcia.h
+new file mode 100644
+index 000000000..0ffc97be1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/sbpcmcia.h
+@@ -0,0 +1,139 @@
++/*
++ * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: sbpcmcia.h 616054 2016-01-29 13:22:24Z $
++ */
++
++#ifndef	_SBPCMCIA_H
++#define	_SBPCMCIA_H
++
++/* All the addresses that are offsets in attribute space are divided
++ * by two to account for the fact that odd bytes are invalid in
++ * attribute space and our read/write routines make the space appear
++ * as if they didn't exist. Still we want to show the original numbers
++ * as documented in the hnd_pcmcia core manual.
++ */
++
++/* PCMCIA Function Configuration Registers */
++#define	PCMCIA_FCR		(0x700 / 2)
++
++#define	FCR0_OFF		0
++#define	FCR1_OFF		(0x40 / 2)
++#define	FCR2_OFF		(0x80 / 2)
++#define	FCR3_OFF		(0xc0 / 2)
++
++#define	PCMCIA_FCR0		(0x700 / 2)
++#define	PCMCIA_FCR1		(0x740 / 2)
++#define	PCMCIA_FCR2		(0x780 / 2)
++#define	PCMCIA_FCR3		(0x7c0 / 2)
++
++/* Standard PCMCIA FCR registers */
++
++#define	PCMCIA_COR		0
++
++#define	COR_RST			0x80
++#define	COR_LEV			0x40
++#define	COR_IRQEN		0x04
++#define	COR_BLREN		0x01
++#define	COR_FUNEN		0x01
++
++
++#define	PCICIA_FCSR		(2 / 2)
++#define	PCICIA_PRR		(4 / 2)
++#define	PCICIA_SCR		(6 / 2)
++#define	PCICIA_ESR		(8 / 2)
++
++
++#define PCM_MEMOFF		0x0000
++#define F0_MEMOFF		0x1000
++#define F1_MEMOFF		0x2000
++#define F2_MEMOFF		0x3000
++#define F3_MEMOFF		0x4000
++
++/* Memory base in the function fcr's */
++#define MEM_ADDR0		(0x728 / 2)
++#define MEM_ADDR1		(0x72a / 2)
++#define MEM_ADDR2		(0x72c / 2)
++
++/* PCMCIA base plus Srom access in fcr0: */
++#define PCMCIA_ADDR0		(0x072e / 2)
++#define PCMCIA_ADDR1		(0x0730 / 2)
++#define PCMCIA_ADDR2		(0x0732 / 2)
++
++#define MEM_SEG			(0x0734 / 2)
++#define SROM_CS			(0x0736 / 2)
++#define SROM_DATAL		(0x0738 / 2)
++#define SROM_DATAH		(0x073a / 2)
++#define SROM_ADDRL		(0x073c / 2)
++#define SROM_ADDRH		(0x073e / 2)
++#define	SROM_INFO2		(0x0772 / 2)	/* Corerev >= 2 && <= 5 */
++#define	SROM_INFO		(0x07be / 2)	/* Corerev >= 6 */
++
++/*  Values for srom_cs: */
++#define SROM_IDLE		0
++#define SROM_WRITE		1
++#define SROM_READ		2
++#define SROM_WEN		4
++#define SROM_WDS		7
++#define SROM_DONE		8
++
++/* Fields in srom_info: */
++#define	SRI_SZ_MASK		0x03
++#define	SRI_BLANK		0x04
++#define	SRI_OTP			0x80
++
++
++#define SROM16K_BANK_SEL_MASK		(3 << 11)
++#define SROM16K_BANK_SHFT_MASK		11
++#define SROM16K_ADDR_SEL_MASK	((1 << SROM16K_BANK_SHFT_MASK) - 1)
++
++
++
++/* Standard tuples we know about */
++
++#define CISTPL_NULL		0x00
++#define	CISTPL_END		0xff		/* End of the CIS tuple chain */
++
++
++#define	CISTPL_BRCM_HNBU	0x80
++
++
++#define HNBU_BOARDREV		0x02	/* One byte board revision */
++
++
++#define HNBU_BOARDTYPE		0x1b	/* 2 bytes; boardtype */
++
++
++#define HNBU_HNBUCIS		0x1d	/* what follows is proprietary HNBU CIS format */
++
++
++/* sbtmstatelow */
++#define SBTML_INT_ACK		0x40000		/* ack the sb interrupt */
++#define SBTML_INT_EN		0x20000		/* enable sb interrupt */
++
++/* sbtmstatehigh */
++#define SBTMH_INT_STATUS	0x40000		/* sb interrupt status */
++#endif	/* _SBPCMCIA_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/sbsdio.h b/module_drivers/drivers/net/wireless/bcmdhd/include/sbsdio.h
+new file mode 100644
+index 000000000..68707c4d4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/sbsdio.h
+@@ -0,0 +1,189 @@
++/*
++ * SDIO device core hardware definitions.
++ * sdio is a portion of the pcmcia core in core rev 3 - rev 8
++ *
++ * SDIO core support 1bit, 4 bit SDIO mode as well as SPI mode.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: sbsdio.h 514727 2014-11-12 03:02:48Z $
++ */
++
++#ifndef	_SBSDIO_H
++#define	_SBSDIO_H
++
++#define SBSDIO_NUM_FUNCTION		3	/* as of sdiod rev 0, supports 3 functions */
++
++/* function 1 miscellaneous registers */
++#define SBSDIO_SPROM_CS			0x10000		/* sprom command and status */
++#define SBSDIO_SPROM_INFO		0x10001		/* sprom info register */
++#define SBSDIO_SPROM_DATA_LOW		0x10002		/* sprom indirect access data byte 0 */
++#define SBSDIO_SPROM_DATA_HIGH		0x10003 	/* sprom indirect access data byte 1 */
++#define SBSDIO_SPROM_ADDR_LOW		0x10004		/* sprom indirect access addr byte 0 */
++#define SBSDIO_SPROM_ADDR_HIGH		0x10005		/* sprom indirect access addr byte 0 */
++#define SBSDIO_CHIP_CTRL_DATA		0x10006		/* xtal_pu (gpio) output */
++#define SBSDIO_CHIP_CTRL_EN		0x10007		/* xtal_pu (gpio) enable */
++#define SBSDIO_WATERMARK		0x10008		/* rev < 7, watermark for sdio device */
++#define SBSDIO_DEVICE_CTL		0x10009		/* control busy signal generation */
++
++/* registers introduced in rev 8, some content (mask/bits) defs in sbsdpcmdev.h */
++#define SBSDIO_FUNC1_SBADDRLOW		0x1000A		/* SB Address Window Low (b15) */
++#define SBSDIO_FUNC1_SBADDRMID		0x1000B		/* SB Address Window Mid (b23:b16) */
++#define SBSDIO_FUNC1_SBADDRHIGH		0x1000C		/* SB Address Window High (b31:b24)    */
++#define SBSDIO_FUNC1_FRAMECTRL		0x1000D		/* Frame Control (frame term/abort) */
++#define SBSDIO_FUNC1_CHIPCLKCSR		0x1000E		/* ChipClockCSR (ALP/HT ctl/status) */
++#define SBSDIO_FUNC1_SDIOPULLUP 	0x1000F		/* SdioPullUp (on cmd, d0-d2) */
++#define SBSDIO_FUNC1_WFRAMEBCLO		0x10019		/* Write Frame Byte Count Low */
++#define SBSDIO_FUNC1_WFRAMEBCHI		0x1001A		/* Write Frame Byte Count High */
++#define SBSDIO_FUNC1_RFRAMEBCLO		0x1001B		/* Read Frame Byte Count Low */
++#define SBSDIO_FUNC1_RFRAMEBCHI		0x1001C		/* Read Frame Byte Count High */
++#define SBSDIO_FUNC1_MESBUSYCTRL	0x1001D		/* MesBusyCtl at 0x1001D (rev 11) */
++
++#define SBSDIO_FUNC1_MISC_REG_START	0x10000 	/* f1 misc register start */
++#define SBSDIO_FUNC1_MISC_REG_LIMIT	0x1001C 	/* f1 misc register end */
++
++/* Sdio Core Rev 12 */
++#define SBSDIO_FUNC1_WAKEUPCTRL			0x1001E
++#define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK		0x1
++#define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT	0
++#define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK		0x2
++#define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT		1
++#define SBSDIO_FUNC1_SLEEPCSR			0x1001F
++#define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK		0x1
++#define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT		0
++#define SBSDIO_FUNC1_SLEEPCSR_KSO_EN		1
++#define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK	0x2
++#define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT	1
++
++/* SBSDIO_SPROM_CS */
++#define SBSDIO_SPROM_IDLE		0
++#define SBSDIO_SPROM_WRITE		1
++#define SBSDIO_SPROM_READ		2
++#define SBSDIO_SPROM_WEN		4
++#define SBSDIO_SPROM_WDS		7
++#define SBSDIO_SPROM_DONE		8
++
++/* SBSDIO_SPROM_INFO */
++#define SROM_SZ_MASK			0x03		/* SROM size, 1: 4k, 2: 16k */
++#define SROM_BLANK			0x04		/* depreciated in corerev 6 */
++#define	SROM_OTP			0x80		/* OTP present */
++
++/* SBSDIO_CHIP_CTRL */
++#define SBSDIO_CHIP_CTRL_XTAL		0x01		/* or'd with onchip xtal_pu,
++							 * 1: power on oscillator
++							 * (for 4318 only)
++							 */
++/* SBSDIO_WATERMARK */
++#define SBSDIO_WATERMARK_MASK		0x7f		/* number of words - 1 for sd device
++							 * to wait before sending data to host
++							 */
++
++/* SBSDIO_MESBUSYCTRL */
++/* When RX FIFO has less entries than this & MBE is set
++ * => busy signal is asserted between data blocks.
++*/
++#define SBSDIO_MESBUSYCTRL_MASK		0x7f
++#define SBSDIO_MESBUSYCTRL_ENAB		0x80		/* Enable busy capability for MES access */
++
++/* SBSDIO_DEVICE_CTL */
++#define SBSDIO_DEVCTL_SETBUSY		0x01		/* 1: device will assert busy signal when
++							 * receiving CMD53
++							 */
++#define SBSDIO_DEVCTL_SPI_INTR_SYNC	0x02		/* 1: assertion of sdio interrupt is
++							 * synchronous to the sdio clock
++							 */
++#define SBSDIO_DEVCTL_CA_INT_ONLY	0x04		/* 1: mask all interrupts to host
++							 * except the chipActive (rev 8)
++							 */
++#define SBSDIO_DEVCTL_PADS_ISO		0x08		/* 1: isolate internal sdio signals, put
++							 * external pads in tri-state; requires
++							 * sdio bus power cycle to clear (rev 9)
++							 */
++#define SBSDIO_DEVCTL_EN_F2_BLK_WATERMARK 0x10  /* Enable function 2 tx for each block */
++#define SBSDIO_DEVCTL_F2WM_ENAB		0x10		/* Enable F2 Watermark */
++#define SBSDIO_DEVCTL_NONDAT_PADS_ISO 	0x20		/* Isolate sdio clk and cmd (non-data) */
++
++/* SBSDIO_FUNC1_CHIPCLKCSR */
++#define SBSDIO_FORCE_ALP		0x01		/* Force ALP request to backplane */
++#define SBSDIO_FORCE_HT			0x02		/* Force HT request to backplane */
++#define SBSDIO_FORCE_ILP		0x04		/* Force ILP request to backplane */
++#define SBSDIO_ALP_AVAIL_REQ		0x08		/* Make ALP ready (power up xtal) */
++#define SBSDIO_HT_AVAIL_REQ		0x10		/* Make HT ready (power up PLL) */
++#define SBSDIO_FORCE_HW_CLKREQ_OFF	0x20		/* Squelch clock requests from HW */
++#define SBSDIO_ALP_AVAIL		0x40		/* Status: ALP is ready */
++#define SBSDIO_HT_AVAIL			0x80		/* Status: HT is ready */
++/* In rev8, actual avail bits followed original docs */
++#define SBSDIO_Rev8_HT_AVAIL		0x40
++#define SBSDIO_Rev8_ALP_AVAIL		0x80
++#define SBSDIO_CSR_MASK			0x1F
++
++#define SBSDIO_AVBITS			(SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
++#define SBSDIO_ALPAV(regval)		((regval) & SBSDIO_AVBITS)
++#define SBSDIO_HTAV(regval)		(((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
++#define SBSDIO_ALPONLY(regval)		(SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
++#define SBSDIO_CLKAV(regval, alponly)	(SBSDIO_ALPAV(regval) && \
++					(alponly ? 1 : SBSDIO_HTAV(regval)))
++
++/* SBSDIO_FUNC1_SDIOPULLUP */
++#define SBSDIO_PULLUP_D0		0x01		/* Enable D0/MISO pullup */
++#define SBSDIO_PULLUP_D1		0x02		/* Enable D1/INT# pullup */
++#define SBSDIO_PULLUP_D2		0x04		/* Enable D2 pullup */
++#define SBSDIO_PULLUP_CMD		0x08		/* Enable CMD/MOSI pullup */
++#define SBSDIO_PULLUP_ALL		0x0f		/* All valid bits */
++
++/* function 1 OCP space */
++#define SBSDIO_SB_OFT_ADDR_MASK		0x07FFF		/* sb offset addr is <= 15 bits, 32k */
++#define SBSDIO_SB_OFT_ADDR_LIMIT	0x08000
++#define SBSDIO_SB_ACCESS_2_4B_FLAG	0x08000		/* with b15, maps to 32-bit SB access */
++
++/* some duplication with sbsdpcmdev.h here */
++/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
++#define SBSDIO_SBADDRLOW_MASK		0x80		/* Valid bits in SBADDRLOW */
++#define SBSDIO_SBADDRMID_MASK		0xff		/* Valid bits in SBADDRMID */
++#define SBSDIO_SBADDRHIGH_MASK		0xffU		/* Valid bits in SBADDRHIGH */
++#define SBSDIO_SBWINDOW_MASK		0xffff8000	/* Address bits from SBADDR regs */
++
++/* direct(mapped) cis space */
++#define SBSDIO_CIS_BASE_COMMON		0x1000		/* MAPPED common CIS address */
++#define SBSDIO_CIS_SIZE_LIMIT		0x200		/* maximum bytes in one CIS */
++#define SBSDIO_OTP_CIS_SIZE_LIMIT       0x078           /* maximum bytes OTP CIS */
++
++#define SBSDIO_CIS_OFT_ADDR_MASK	0x1FFFF		/* cis offset addr is < 17 bits */
++
++#define SBSDIO_CIS_MANFID_TUPLE_LEN	6		/* manfid tuple length, include tuple,
++							 * link bytes
++							 */
++
++/* indirect cis access (in sprom) */
++#define SBSDIO_SPROM_CIS_OFFSET		0x8		/* 8 control bytes first, CIS starts from
++							 * 8th byte
++							 */
++
++#define SBSDIO_BYTEMODE_DATALEN_MAX	64		/* sdio byte mode: maximum length of one
++							 * data comamnd
++							 */
++
++#define SBSDIO_CORE_ADDR_MASK		0x1FFFF		/* sdio core function one address mask */
++
++#endif	/* _SBSDIO_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/sbsdpcmdev.h b/module_drivers/drivers/net/wireless/bcmdhd/include/sbsdpcmdev.h
+new file mode 100644
+index 000000000..8607d6357
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/sbsdpcmdev.h
+@@ -0,0 +1,300 @@
++/*
++ * Broadcom SiliconBackplane SDIO/PCMCIA hardware-specific
++ * device core support
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: sbsdpcmdev.h 610395 2016-01-06 22:52:57Z $
++ */
++
++#ifndef	_sbsdpcmdev_h_
++#define	_sbsdpcmdev_h_
++
++/* cpp contortions to concatenate w/arg prescan */
++#ifndef PAD
++#define	_PADLINE(line)	pad ## line
++#define	_XSTR(line)	_PADLINE(line)
++#define	PAD		_XSTR(__LINE__)
++#endif	/* PAD */
++
++
++typedef volatile struct {
++	dma64regs_t	xmt;		/* dma tx */
++	uint32 PAD[2];
++	dma64regs_t	rcv;		/* dma rx */
++	uint32 PAD[2];
++} dma64p_t;
++
++/* dma64 sdiod corerev >= 1 */
++typedef volatile struct {
++	dma64p_t dma64regs[2];
++	dma64diag_t dmafifo;		/* DMA Diagnostic Regs, 0x280-0x28c */
++	uint32 PAD[92];
++} sdiodma64_t;
++
++/* dma32 sdiod corerev == 0 */
++typedef volatile struct {
++	dma32regp_t dma32regs[2];	/* dma tx & rx, 0x200-0x23c */
++	dma32diag_t dmafifo;		/* DMA Diagnostic Regs, 0x240-0x24c */
++	uint32 PAD[108];
++} sdiodma32_t;
++
++/* dma32 regs for pcmcia core */
++typedef volatile struct {
++	dma32regp_t dmaregs;		/* DMA Regs, 0x200-0x21c, rev8 */
++	dma32diag_t dmafifo;		/* DMA Diagnostic Regs, 0x220-0x22c */
++	uint32 PAD[116];
++} pcmdma32_t;
++
++/* core registers */
++typedef volatile struct {
++	uint32 corecontrol;		/* CoreControl, 0x000, rev8 */
++	uint32 corestatus;		/* CoreStatus, 0x004, rev8  */
++	uint32 PAD[1];
++	uint32 biststatus;		/* BistStatus, 0x00c, rev8  */
++
++	/* PCMCIA access */
++	uint16 pcmciamesportaladdr;	/* PcmciaMesPortalAddr, 0x010, rev8   */
++	uint16 PAD[1];
++	uint16 pcmciamesportalmask;	/* PcmciaMesPortalMask, 0x014, rev8   */
++	uint16 PAD[1];
++	uint16 pcmciawrframebc;		/* PcmciaWrFrameBC, 0x018, rev8   */
++	uint16 PAD[1];
++	uint16 pcmciaunderflowtimer;	/* PcmciaUnderflowTimer, 0x01c, rev8   */
++	uint16 PAD[1];
++
++	/* interrupt */
++	uint32 intstatus;		/* IntStatus, 0x020, rev8   */
++	uint32 hostintmask;		/* IntHostMask, 0x024, rev8   */
++	uint32 intmask;			/* IntSbMask, 0x028, rev8   */
++	uint32 sbintstatus;		/* SBIntStatus, 0x02c, rev8   */
++	uint32 sbintmask;		/* SBIntMask, 0x030, rev8   */
++	uint32 funcintmask;		/* SDIO Function Interrupt Mask, SDIO rev4 */
++	uint32 PAD[2];
++	uint32 tosbmailbox;		/* ToSBMailbox, 0x040, rev8   */
++	uint32 tohostmailbox;		/* ToHostMailbox, 0x044, rev8   */
++	uint32 tosbmailboxdata;		/* ToSbMailboxData, 0x048, rev8   */
++	uint32 tohostmailboxdata;	/* ToHostMailboxData, 0x04c, rev8   */
++
++	/* synchronized access to registers in SDIO clock domain */
++	uint32 sdioaccess;		/* SdioAccess, 0x050, rev8   */
++	uint32 PAD[3];
++
++	/* PCMCIA frame control */
++	uint8 pcmciaframectrl;		/* pcmciaFrameCtrl, 0x060, rev8   */
++	uint8 PAD[3];
++	uint8 pcmciawatermark;		/* pcmciaWaterMark, 0x064, rev8   */
++	uint8 PAD[155];
++
++	/* interrupt batching control */
++	uint32 intrcvlazy;		/* IntRcvLazy, 0x100, rev8 */
++	uint32 PAD[3];
++
++	/* counters */
++	uint32 cmd52rd;			/* Cmd52RdCount, 0x110, rev8, SDIO: cmd52 reads */
++	uint32 cmd52wr;			/* Cmd52WrCount, 0x114, rev8, SDIO: cmd52 writes */
++	uint32 cmd53rd;			/* Cmd53RdCount, 0x118, rev8, SDIO: cmd53 reads */
++	uint32 cmd53wr;			/* Cmd53WrCount, 0x11c, rev8, SDIO: cmd53 writes */
++	uint32 abort;			/* AbortCount, 0x120, rev8, SDIO: aborts */
++	uint32 datacrcerror;		/* DataCrcErrorCount, 0x124, rev8, SDIO: frames w/bad CRC */
++	uint32 rdoutofsync;		/* RdOutOfSyncCount, 0x128, rev8, SDIO/PCMCIA: Rd Frm OOS */
++	uint32 wroutofsync;		/* RdOutOfSyncCount, 0x12c, rev8, SDIO/PCMCIA: Wr Frm OOS */
++	uint32 writebusy;		/* WriteBusyCount, 0x130, rev8, SDIO: dev asserted "busy" */
++	uint32 readwait;		/* ReadWaitCount, 0x134, rev8, SDIO: read: no data avail */
++	uint32 readterm;		/* ReadTermCount, 0x138, rev8, SDIO: rd frm terminates */
++	uint32 writeterm;		/* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */
++	uint32 PAD[40];
++	uint32 clockctlstatus;		/* ClockCtlStatus, 0x1e0, rev8 */
++	uint32 PAD[1];
++	uint32 powerctl;		/* 0x1e8 */
++	uint32 PAD[5];
++
++	/* DMA engines */
++	volatile union {
++		pcmdma32_t pcm32;
++		sdiodma32_t sdiod32;
++		sdiodma64_t sdiod64;
++	} dma;
++
++	/* SDIO/PCMCIA CIS region */
++	char cis[512];			/* 512 byte CIS, 0x400-0x5ff, rev6 */
++
++	/* PCMCIA function control registers */
++	char pcmciafcr[256];		/* PCMCIA FCR, 0x600-6ff, rev6 */
++	uint16 PAD[55];
++
++	/* PCMCIA backplane access */
++	uint16 backplanecsr;		/* BackplaneCSR, 0x76E, rev6 */
++	uint16 backplaneaddr0;		/* BackplaneAddr0, 0x770, rev6 */
++	uint16 backplaneaddr1;		/* BackplaneAddr1, 0x772, rev6 */
++	uint16 backplaneaddr2;		/* BackplaneAddr2, 0x774, rev6 */
++	uint16 backplaneaddr3;		/* BackplaneAddr3, 0x776, rev6 */
++	uint16 backplanedata0;		/* BackplaneData0, 0x778, rev6 */
++	uint16 backplanedata1;		/* BackplaneData1, 0x77a, rev6 */
++	uint16 backplanedata2;		/* BackplaneData2, 0x77c, rev6 */
++	uint16 backplanedata3;		/* BackplaneData3, 0x77e, rev6 */
++	uint16 PAD[31];
++
++	/* sprom "size" & "blank" info */
++	uint16 spromstatus;		/* SPROMStatus, 0x7BE, rev2 */
++	uint32 PAD[464];
++
++	/* Sonics SiliconBackplane registers */
++	sbconfig_t sbconfig;		/* SbConfig Regs, 0xf00-0xfff, rev8 */
++} sdpcmd_regs_t;
++
++/* corecontrol */
++#define CC_CISRDY		(1 << 0)	/* CIS Ready */
++#define CC_BPRESEN		(1 << 1)	/* CCCR RES signal causes backplane reset */
++#define CC_F2RDY		(1 << 2)	/* set CCCR IOR2 bit */
++#define CC_CLRPADSISO		(1 << 3)	/* clear SDIO pads isolation bit (rev 11) */
++#define CC_XMTDATAAVAIL_MODE	(1 << 4)	/* data avail generates an interrupt */
++#define CC_XMTDATAAVAIL_CTRL	(1 << 5)	/* data avail interrupt ctrl */
++
++/* corestatus */
++#define CS_PCMCIAMODE	(1 << 0)	/* Device Mode; 0=SDIO, 1=PCMCIA */
++#define CS_SMARTDEV	(1 << 1)	/* 1=smartDev enabled */
++#define CS_F2ENABLED	(1 << 2)	/* 1=host has enabled the device */
++
++#define PCMCIA_MES_PA_MASK	0x7fff	/* PCMCIA Message Portal Address Mask */
++#define PCMCIA_MES_PM_MASK	0x7fff	/* PCMCIA Message Portal Mask Mask */
++#define PCMCIA_WFBC_MASK	0xffff	/* PCMCIA Write Frame Byte Count Mask */
++#define PCMCIA_UT_MASK		0x07ff	/* PCMCIA Underflow Timer Mask */
++
++/* intstatus */
++#define I_SMB_SW0	(1 << 0)	/* To SB Mail S/W interrupt 0 */
++#define I_SMB_SW1	(1 << 1)	/* To SB Mail S/W interrupt 1 */
++#define I_SMB_SW2	(1 << 2)	/* To SB Mail S/W interrupt 2 */
++#define I_SMB_SW3	(1 << 3)	/* To SB Mail S/W interrupt 3 */
++#define I_SMB_SW_MASK	0x0000000f	/* To SB Mail S/W interrupts mask */
++#define I_SMB_SW_SHIFT	0		/* To SB Mail S/W interrupts shift */
++#define I_HMB_SW0	(1 << 4)	/* To Host Mail S/W interrupt 0 */
++#define I_HMB_SW1	(1 << 5)	/* To Host Mail S/W interrupt 1 */
++#define I_HMB_SW2	(1 << 6)	/* To Host Mail S/W interrupt 2 */
++#define I_HMB_SW3	(1 << 7)	/* To Host Mail S/W interrupt 3 */
++#define I_HMB_SW_MASK	0x000000f0	/* To Host Mail S/W interrupts mask */
++#define I_HMB_SW_SHIFT	4		/* To Host Mail S/W interrupts shift */
++#define I_WR_OOSYNC	(1 << 8)	/* Write Frame Out Of Sync */
++#define I_RD_OOSYNC	(1 << 9)	/* Read Frame Out Of Sync */
++#define	I_PC		(1 << 10)	/* descriptor error */
++#define	I_PD		(1 << 11)	/* data error */
++#define	I_DE		(1 << 12)	/* Descriptor protocol Error */
++#define	I_RU		(1 << 13)	/* Receive descriptor Underflow */
++#define	I_RO		(1 << 14)	/* Receive fifo Overflow */
++#define	I_XU		(1 << 15)	/* Transmit fifo Underflow */
++#define	I_RI		(1 << 16)	/* Receive Interrupt */
++#define I_BUSPWR	(1 << 17)	/* SDIO Bus Power Change (rev 9) */
++#define I_XMTDATA_AVAIL (1 << 23)	/* bits in fifo */
++#define	I_XI		(1 << 24)	/* Transmit Interrupt */
++#define I_RF_TERM	(1 << 25)	/* Read Frame Terminate */
++#define I_WF_TERM	(1 << 26)	/* Write Frame Terminate */
++#define I_PCMCIA_XU	(1 << 27)	/* PCMCIA Transmit FIFO Underflow */
++#define I_SBINT		(1 << 28)	/* sbintstatus Interrupt */
++#define I_CHIPACTIVE	(1 << 29)	/* chip transitioned from doze to active state */
++#define I_SRESET	(1 << 30)	/* CCCR RES interrupt */
++#define I_IOE2		(1U << 31)	/* CCCR IOE2 Bit Changed */
++#define	I_ERRORS	(I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)	/* DMA Errors */
++#define I_DMA		(I_RI | I_XI | I_ERRORS)
++
++/* sbintstatus */
++#define I_SB_SERR	(1 << 8)	/* Backplane SError (write) */
++#define I_SB_RESPERR	(1 << 9)	/* Backplane Response Error (read) */
++#define I_SB_SPROMERR	(1 << 10)	/* Error accessing the sprom */
++
++/* sdioaccess */
++#define SDA_DATA_MASK	0x000000ff	/* Read/Write Data Mask */
++#define SDA_ADDR_MASK	0x000fff00	/* Read/Write Address Mask */
++#define SDA_ADDR_SHIFT	8		/* Read/Write Address Shift */
++#define SDA_WRITE	0x01000000	/* Write bit  */
++#define SDA_READ	0x00000000	/* Write bit cleared for Read */
++#define SDA_BUSY	0x80000000	/* Busy bit */
++
++/* sdioaccess-accessible register address spaces */
++#define SDA_CCCR_SPACE		0x000	/* sdioAccess CCCR register space */
++#define SDA_F1_FBR_SPACE	0x100	/* sdioAccess F1 FBR register space */
++#define SDA_F2_FBR_SPACE	0x200	/* sdioAccess F2 FBR register space */
++#define SDA_F1_REG_SPACE	0x300	/* sdioAccess F1 core-specific register space */
++
++/* SDA_F1_REG_SPACE sdioaccess-accessible F1 reg space register offsets */
++#define SDA_CHIPCONTROLDATA	0x006	/* ChipControlData */
++#define SDA_CHIPCONTROLENAB	0x007	/* ChipControlEnable */
++#define SDA_F2WATERMARK		0x008	/* Function 2 Watermark */
++#define SDA_DEVICECONTROL	0x009	/* DeviceControl */
++#define SDA_SBADDRLOW		0x00a	/* SbAddrLow */
++#define SDA_SBADDRMID		0x00b	/* SbAddrMid */
++#define SDA_SBADDRHIGH		0x00c	/* SbAddrHigh */
++#define SDA_FRAMECTRL		0x00d	/* FrameCtrl */
++#define SDA_CHIPCLOCKCSR	0x00e	/* ChipClockCSR */
++#define SDA_SDIOPULLUP		0x00f	/* SdioPullUp */
++#define SDA_SDIOWRFRAMEBCLOW	0x019	/* SdioWrFrameBCLow */
++#define SDA_SDIOWRFRAMEBCHIGH	0x01a	/* SdioWrFrameBCHigh */
++#define SDA_SDIORDFRAMEBCLOW	0x01b	/* SdioRdFrameBCLow */
++#define SDA_SDIORDFRAMEBCHIGH	0x01c	/* SdioRdFrameBCHigh */
++
++/* SDA_F2WATERMARK */
++#define SDA_F2WATERMARK_MASK	0x7f	/* F2Watermark Mask */
++
++/* SDA_SBADDRLOW */
++#define SDA_SBADDRLOW_MASK	0x80	/* SbAddrLow Mask */
++
++/* SDA_SBADDRMID */
++#define SDA_SBADDRMID_MASK	0xff	/* SbAddrMid Mask */
++
++/* SDA_SBADDRHIGH */
++#define SDA_SBADDRHIGH_MASK	0xff	/* SbAddrHigh Mask */
++
++/* SDA_FRAMECTRL */
++#define SFC_RF_TERM	(1 << 0)	/* Read Frame Terminate */
++#define SFC_WF_TERM	(1 << 1)	/* Write Frame Terminate */
++#define SFC_CRC4WOOS	(1 << 2)	/* HW reports CRC error for write out of sync */
++#define SFC_ABORTALL	(1 << 3)	/* Abort cancels all in-progress frames */
++
++/* pcmciaframectrl */
++#define PFC_RF_TERM	(1 << 0)	/* Read Frame Terminate */
++#define PFC_WF_TERM	(1 << 1)	/* Write Frame Terminate */
++
++/* intrcvlazy */
++#define	IRL_TO_MASK	0x00ffffff	/* timeout */
++#define	IRL_FC_MASK	0xff000000	/* frame count */
++#define	IRL_FC_SHIFT	24		/* frame count */
++
++/* rx header */
++typedef volatile struct {
++	uint16 len;
++	uint16 flags;
++} sdpcmd_rxh_t;
++
++/* rx header flags */
++#define RXF_CRC		0x0001		/* CRC error detected */
++#define RXF_WOOS	0x0002		/* write frame out of sync */
++#define RXF_WF_TERM	0x0004		/* write frame terminated */
++#define RXF_ABORT	0x0008		/* write frame aborted */
++#define RXF_DISCARD	(RXF_CRC | RXF_WOOS | RXF_WF_TERM | RXF_ABORT)	/* bad frame */
++
++/* HW frame tag */
++#define SDPCM_FRAMETAG_LEN	4	/* HW frametag: 2 bytes len, 2 bytes check val */
++
++#define SDPCM_HWEXT_LEN	8
++
++#endif	/* _sbsdpcmdev_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/sbsocram.h b/module_drivers/drivers/net/wireless/bcmdhd/include/sbsocram.h
+new file mode 100644
+index 000000000..b2c018839
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/sbsocram.h
+@@ -0,0 +1,205 @@
++/*
++ * BCM47XX Sonics SiliconBackplane embedded ram core
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: sbsocram.h 604712 2015-12-08 08:05:42Z $
++ */
++
++#ifndef	_SBSOCRAM_H
++#define	_SBSOCRAM_H
++
++#ifndef _LANGUAGE_ASSEMBLY
++
++/* cpp contortions to concatenate w/arg prescan */
++#ifndef PAD
++#define	_PADLINE(line)	pad ## line
++#define	_XSTR(line)	_PADLINE(line)
++#define	PAD		_XSTR(__LINE__)
++#endif	/* PAD */
++
++/* Memcsocram core registers */
++typedef volatile struct sbsocramregs {
++	uint32	coreinfo;
++	uint32	bwalloc;
++	uint32	extracoreinfo;
++	uint32	biststat;
++	uint32	bankidx;
++	uint32	standbyctrl;
++
++	uint32	errlogstatus;	/* rev 6 */
++	uint32	errlogaddr;	/* rev 6 */
++	/* used for patching rev 3 & 5 */
++	uint32	cambankidx;
++	uint32	cambankstandbyctrl;
++	uint32	cambankpatchctrl;
++	uint32	cambankpatchtblbaseaddr;
++	uint32	cambankcmdreg;
++	uint32	cambankdatareg;
++	uint32	cambankmaskreg;
++	uint32	PAD[1];
++	uint32	bankinfo;	/* corev 8 */
++	uint32	bankpda;
++	uint32	PAD[14];
++	uint32	extmemconfig;
++	uint32	extmemparitycsr;
++	uint32	extmemparityerrdata;
++	uint32	extmemparityerrcnt;
++	uint32	extmemwrctrlandsize;
++	uint32	PAD[84];
++	uint32	workaround;
++	uint32	pwrctl;		/* corerev >= 2 */
++	uint32	PAD[133];
++	uint32  sr_control;     /* corerev >= 15 */
++	uint32  sr_status;      /* corerev >= 15 */
++	uint32  sr_address;     /* corerev >= 15 */
++	uint32  sr_data;        /* corerev >= 15 */
++} sbsocramregs_t;
++
++#endif	/* _LANGUAGE_ASSEMBLY */
++
++/* Register offsets */
++#define	SR_COREINFO		0x00
++#define	SR_BWALLOC		0x04
++#define	SR_BISTSTAT		0x0c
++#define	SR_BANKINDEX		0x10
++#define	SR_BANKSTBYCTL		0x14
++#define SR_PWRCTL		0x1e8
++
++/* Coreinfo register */
++#define	SRCI_PT_MASK		0x00070000	/* corerev >= 6; port type[18:16] */
++#define	SRCI_PT_SHIFT		16
++/* port types : SRCI_PT_<processorPT>_<backplanePT> */
++#define SRCI_PT_OCP_OCP		0
++#define SRCI_PT_AXI_OCP		1
++#define SRCI_PT_ARM7AHB_OCP	2
++#define SRCI_PT_CM3AHB_OCP	3
++#define SRCI_PT_AXI_AXI		4
++#define SRCI_PT_AHB_AXI		5
++/* corerev >= 3 */
++#define SRCI_LSS_MASK		0x00f00000
++#define SRCI_LSS_SHIFT		20
++#define SRCI_LRS_MASK		0x0f000000
++#define SRCI_LRS_SHIFT		24
++
++/* In corerev 0, the memory size is 2 to the power of the
++ * base plus 16 plus to the contents of the memsize field plus 1.
++ */
++#define	SRCI_MS0_MASK		0xf
++#define SR_MS0_BASE		16
++
++/*
++ * In corerev 1 the bank size is 2 ^ the bank size field plus 14,
++ * the memory size is number of banks times bank size.
++ * The same applies to rom size.
++ */
++#define	SRCI_ROMNB_MASK		0xf000
++#define	SRCI_ROMNB_SHIFT	12
++#define	SRCI_ROMBSZ_MASK	0xf00
++#define	SRCI_ROMBSZ_SHIFT	8
++#define	SRCI_SRNB_MASK		0xf0
++#define	SRCI_SRNB_SHIFT		4
++#define	SRCI_SRBSZ_MASK		0xf
++#define	SRCI_SRBSZ_SHIFT	0
++
++#define	SRCI_SRNB_MASK_EXT	0x100
++
++#define SR_BSZ_BASE		14
++
++/* Standby control register */
++#define	SRSC_SBYOVR_MASK	0x80000000
++#define	SRSC_SBYOVR_SHIFT	31
++#define	SRSC_SBYOVRVAL_MASK	0x60000000
++#define	SRSC_SBYOVRVAL_SHIFT	29
++#define	SRSC_SBYEN_MASK		0x01000000	/* rev >= 3 */
++#define	SRSC_SBYEN_SHIFT	24
++
++/* Power control register */
++#define SRPC_PMU_STBYDIS_MASK	0x00000010	/* rev >= 3 */
++#define SRPC_PMU_STBYDIS_SHIFT	4
++#define SRPC_STBYOVRVAL_MASK	0x00000008
++#define SRPC_STBYOVRVAL_SHIFT	3
++#define SRPC_STBYOVR_MASK	0x00000007
++#define SRPC_STBYOVR_SHIFT	0
++
++/* Extra core capability register */
++#define SRECC_NUM_BANKS_MASK   0x000000F0
++#define SRECC_NUM_BANKS_SHIFT  4
++#define SRECC_BANKSIZE_MASK    0x0000000F
++#define SRECC_BANKSIZE_SHIFT   0
++
++#define SRECC_BANKSIZE(value)	 (1 << (value))
++
++/* CAM bank patch control */
++#define SRCBPC_PATCHENABLE 0x80000000
++
++#define SRP_ADDRESS   0x0001FFFC
++#define SRP_VALID     0x8000
++
++/* CAM bank command reg */
++#define SRCMD_WRITE  0x00020000
++#define SRCMD_READ   0x00010000
++#define SRCMD_DONE   0x80000000
++
++#define SRCMD_DONE_DLY	1000
++
++/* bankidx and bankinfo reg defines corerev >= 8 */
++#define SOCRAM_BANKINFO_SZMASK		0x7f
++#define SOCRAM_BANKIDX_ROM_MASK		0x100
++
++#define SOCRAM_BANKIDX_MEMTYPE_SHIFT	8
++/* socram bankinfo memtype */
++#define SOCRAM_MEMTYPE_RAM		0
++#define SOCRAM_MEMTYPE_R0M		1
++#define SOCRAM_MEMTYPE_DEVRAM		2
++
++#define	SOCRAM_BANKINFO_REG		0x40
++#define	SOCRAM_BANKIDX_REG		0x10
++#define	SOCRAM_BANKINFO_STDBY_MASK	0x400
++#define	SOCRAM_BANKINFO_STDBY_TIMER	0x800
++
++/* bankinfo rev >= 10 */
++#define SOCRAM_BANKINFO_DEVRAMSEL_SHIFT		13
++#define SOCRAM_BANKINFO_DEVRAMSEL_MASK		0x2000
++#define SOCRAM_BANKINFO_DEVRAMPRO_SHIFT		14
++#define SOCRAM_BANKINFO_DEVRAMPRO_MASK		0x4000
++#define SOCRAM_BANKINFO_SLPSUPP_SHIFT		15
++#define SOCRAM_BANKINFO_SLPSUPP_MASK		0x8000
++#define SOCRAM_BANKINFO_RETNTRAM_SHIFT		16
++#define SOCRAM_BANKINFO_RETNTRAM_MASK		0x00010000
++#define SOCRAM_BANKINFO_PDASZ_SHIFT		17
++#define SOCRAM_BANKINFO_PDASZ_MASK		0x003E0000
++#define SOCRAM_BANKINFO_DEVRAMREMAP_SHIFT	24
++#define SOCRAM_BANKINFO_DEVRAMREMAP_MASK	0x01000000
++
++/* extracoreinfo register */
++#define SOCRAM_DEVRAMBANK_MASK		0xF000
++#define SOCRAM_DEVRAMBANK_SHIFT		12
++
++/* bank info to calculate bank size */
++#define   SOCRAM_BANKINFO_SZBASE          8192
++#define SOCRAM_BANKSIZE_SHIFT         13      /* SOCRAM_BANKINFO_SZBASE */
++
++
++#endif	/* _SBSOCRAM_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/sbsysmem.h b/module_drivers/drivers/net/wireless/bcmdhd/include/sbsysmem.h
+new file mode 100644
+index 000000000..df26399b2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/sbsysmem.h
+@@ -0,0 +1,180 @@
++/*
++ * SiliconBackplane System Memory core
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: sbsysmem.h 563229 2015-06-12 04:50:06Z $
++ */
++
++#ifndef	_SBSYSMEM_H
++#define	_SBSYSMEM_H
++
++#ifndef _LANGUAGE_ASSEMBLY
++
++/* cpp contortions to concatenate w/arg prescan */
++#ifndef PAD
++#define	_PADLINE(line)	pad ## line
++#define	_XSTR(line)	_PADLINE(line)
++#define	PAD		_XSTR(__LINE__)
++#endif	/* PAD */
++
++/* sysmem core registers */
++typedef volatile struct sysmemregs {
++	uint32	coreinfo;
++	uint32	bwalloc;
++	uint32	extracoreinfo;
++	uint32	biststat;
++	uint32	bankidx;
++	uint32	standbyctrl;
++
++	uint32	errlogstatus;
++	uint32	errlogaddr;
++
++	uint32	cambankidx;
++	uint32	cambankstandbyctrl;
++	uint32	cambankpatchctrl;
++	uint32	cambankpatchtblbaseaddr;
++	uint32	cambankcmdreg;
++	uint32	cambankdatareg;
++	uint32	cambankmaskreg;
++	uint32	PAD[1];
++	uint32	bankinfo;
++	uint32	PAD[15];
++	uint32	extmemconfig;
++	uint32	extmemparitycsr;
++	uint32	extmemparityerrdata;
++	uint32	extmemparityerrcnt;
++	uint32	extmemwrctrlandsize;
++	uint32	PAD[84];
++	uint32	workaround;
++	uint32	pwrctl;
++	uint32	PAD[133];
++	uint32  sr_control;
++	uint32  sr_status;
++	uint32  sr_address;
++	uint32  sr_data;
++} sysmemregs_t;
++
++#endif	/* _LANGUAGE_ASSEMBLY */
++
++/* Register offsets */
++#define	SR_COREINFO		0x00
++#define	SR_BWALLOC		0x04
++#define	SR_BISTSTAT		0x0c
++#define	SR_BANKINDEX		0x10
++#define	SR_BANKSTBYCTL		0x14
++#define SR_PWRCTL		0x1e8
++
++/* Coreinfo register */
++#define	SRCI_PT_MASK		0x00070000	/* port type[18:16] */
++#define	SRCI_PT_SHIFT		16
++/* port types : SRCI_PT_<processorPT>_<backplanePT> */
++#define SRCI_PT_OCP_OCP		0
++#define SRCI_PT_AXI_OCP		1
++#define SRCI_PT_ARM7AHB_OCP	2
++#define SRCI_PT_CM3AHB_OCP	3
++#define SRCI_PT_AXI_AXI		4
++#define SRCI_PT_AHB_AXI		5
++
++#define SRCI_LSS_MASK		0x00f00000
++#define SRCI_LSS_SHIFT		20
++#define SRCI_LRS_MASK		0x0f000000
++#define SRCI_LRS_SHIFT		24
++
++/* In corerev 0, the memory size is 2 to the power of the
++ * base plus 16 plus to the contents of the memsize field plus 1.
++ */
++#define	SRCI_MS0_MASK		0xf
++#define SR_MS0_BASE		16
++
++/*
++ * In corerev 1 the bank size is 2 ^ the bank size field plus 14,
++ * the memory size is number of banks times bank size.
++ * The same applies to rom size.
++ */
++#define	SYSMEM_SRCI_ROMNB_MASK	0x3e0
++#define	SYSMEM_SRCI_ROMNB_SHIFT	5
++#define	SYSMEM_SRCI_SRNB_MASK	0x1f
++#define	SYSMEM_SRCI_SRNB_SHIFT	0
++
++/* Standby control register */
++#define	SRSC_SBYOVR_MASK	0x80000000
++#define	SRSC_SBYOVR_SHIFT	31
++#define	SRSC_SBYOVRVAL_MASK	0x60000000
++#define	SRSC_SBYOVRVAL_SHIFT	29
++#define	SRSC_SBYEN_MASK		0x01000000
++#define	SRSC_SBYEN_SHIFT	24
++
++/* Power control register */
++#define SRPC_PMU_STBYDIS_MASK	0x00000010
++#define SRPC_PMU_STBYDIS_SHIFT	4
++#define SRPC_STBYOVRVAL_MASK	0x00000008
++#define SRPC_STBYOVRVAL_SHIFT	3
++#define SRPC_STBYOVR_MASK	0x00000007
++#define SRPC_STBYOVR_SHIFT	0
++
++/* Extra core capability register */
++#define SRECC_NUM_BANKS_MASK   0x000000F0
++#define SRECC_NUM_BANKS_SHIFT  4
++#define SRECC_BANKSIZE_MASK    0x0000000F
++#define SRECC_BANKSIZE_SHIFT   0
++
++#define SRECC_BANKSIZE(value)	 (1 << (value))
++
++/* CAM bank patch control */
++#define SRCBPC_PATCHENABLE 0x80000000
++
++#define SRP_ADDRESS   0x0001FFFC
++#define SRP_VALID     0x8000
++
++/* CAM bank command reg */
++#define SRCMD_WRITE  0x00020000
++#define SRCMD_READ   0x00010000
++#define SRCMD_DONE   0x80000000
++
++#define SRCMD_DONE_DLY	1000
++
++/* bankidx and bankinfo reg defines */
++#define SYSMEM_BANKINFO_SZMASK		0x7f
++#define SYSMEM_BANKIDX_ROM_MASK		0x80
++
++#define	SYSMEM_BANKINFO_REG		0x40
++#define	SYSMEM_BANKIDX_REG		0x10
++#define	SYSMEM_BANKINFO_STDBY_MASK	0x200
++#define	SYSMEM_BANKINFO_STDBY_TIMER	0x400
++
++#define SYSMEM_BANKINFO_SLPSUPP_SHIFT		14
++#define SYSMEM_BANKINFO_SLPSUPP_MASK		0x4000
++#define SYSMEM_BANKINFO_PDASZ_SHIFT		16
++#define SYSMEM_BANKINFO_PDASZ_MASK		0x001F0000
++
++/* extracoreinfo register */
++#define SYSMEM_DEVRAMBANK_MASK		0xF000
++#define SYSMEM_DEVRAMBANK_SHIFT		12
++
++/* bank info to calculate bank size */
++#define	SYSMEM_BANKINFO_SZBASE          8192
++#define SYSMEM_BANKSIZE_SHIFT		13      /* SYSMEM_BANKINFO_SZBASE */
++
++#endif	/* _SBSYSMEM_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/sdio.h b/module_drivers/drivers/net/wireless/bcmdhd/include/sdio.h
+new file mode 100644
+index 000000000..8f77e4150
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/sdio.h
+@@ -0,0 +1,630 @@
++/*
++ * SDIO spec header file
++ * Protocol and standard (common) device definitions
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: sdio.h 644725 2016-06-21 12:26:04Z $
++ */
++
++#ifndef	_SDIO_H
++#define	_SDIO_H
++
++#ifdef BCMSDIO
++
++/* CCCR structure for function 0 */
++typedef volatile struct {
++	uint8	cccr_sdio_rev;		/* RO, cccr and sdio revision */
++	uint8	sd_rev;			/* RO, sd spec revision */
++	uint8	io_en;			/* I/O enable */
++	uint8	io_rdy;			/* I/O ready reg */
++	uint8	intr_ctl;		/* Master and per function interrupt enable control */
++	uint8	intr_status;		/* RO, interrupt pending status */
++	uint8	io_abort;		/* read/write abort or reset all functions */
++	uint8	bus_inter;		/* bus interface control */
++	uint8	capability;		/* RO, card capability */
++
++	uint8	cis_base_low;		/* 0x9 RO, common CIS base address, LSB */
++	uint8	cis_base_mid;
++	uint8	cis_base_high;		/* 0xB RO, common CIS base address, MSB */
++
++	/* suspend/resume registers */
++	uint8	bus_suspend;		/* 0xC */
++	uint8	func_select;		/* 0xD */
++	uint8	exec_flag;		/* 0xE */
++	uint8	ready_flag;		/* 0xF */
++
++	uint8	fn0_blk_size[2];	/* 0x10(LSB), 0x11(MSB) */
++
++	uint8	power_control;		/* 0x12 (SDIO version 1.10) */
++
++	uint8	speed_control;		/* 0x13 */
++} sdio_regs_t;
++
++/* SDIO Device CCCR offsets */
++#define SDIOD_CCCR_REV			0x00
++#define SDIOD_CCCR_SDREV		0x01
++#define SDIOD_CCCR_IOEN			0x02
++#define SDIOD_CCCR_IORDY		0x03
++#define SDIOD_CCCR_INTEN		0x04
++#define SDIOD_CCCR_INTPEND		0x05
++#define SDIOD_CCCR_IOABORT		0x06
++#define SDIOD_CCCR_BICTRL		0x07
++#define SDIOD_CCCR_CAPABLITIES		0x08
++#define SDIOD_CCCR_CISPTR_0		0x09
++#define SDIOD_CCCR_CISPTR_1		0x0A
++#define SDIOD_CCCR_CISPTR_2		0x0B
++#define SDIOD_CCCR_BUSSUSP		0x0C
++#define SDIOD_CCCR_FUNCSEL		0x0D
++#define SDIOD_CCCR_EXECFLAGS		0x0E
++#define SDIOD_CCCR_RDYFLAGS		0x0F
++#define SDIOD_CCCR_BLKSIZE_0		0x10
++#define SDIOD_CCCR_BLKSIZE_1		0x11
++#define SDIOD_CCCR_POWER_CONTROL	0x12
++#define SDIOD_CCCR_SPEED_CONTROL	0x13
++#define SDIOD_CCCR_UHSI_SUPPORT		0x14
++#define SDIOD_CCCR_DRIVER_STRENGTH	0x15
++#define SDIOD_CCCR_INTR_EXTN		0x16
++
++/* Broadcom extensions (corerev >= 1) */
++#define SDIOD_CCCR_BRCM_CARDCAP		0xf0
++#define SDIOD_CCCR_BRCM_CARDCAP_CMD14_SUPPORT	0x02
++#define SDIOD_CCCR_BRCM_CARDCAP_CMD14_EXT	0x04
++#define SDIOD_CCCR_BRCM_CARDCAP_CMD_NODEC	0x08
++#define SDIOD_CCCR_BRCM_CARDCTL			0xf1
++#define SDIOD_CCCR_BRCM_SEPINT			0xf2
++
++/* cccr_sdio_rev */
++#define SDIO_REV_SDIOID_MASK	0xf0	/* SDIO spec revision number */
++#define SDIO_REV_CCCRID_MASK	0x0f	/* CCCR format version number */
++#define SDIO_SPEC_VERSION_3_0	0x40	/* SDIO spec version 3.0 */
++
++/* sd_rev */
++#define SD_REV_PHY_MASK		0x0f	/* SD format version number */
++
++/* io_en */
++#define SDIO_FUNC_ENABLE_1	0x02	/* function 1 I/O enable */
++#define SDIO_FUNC_ENABLE_2	0x04	/* function 2 I/O enable */
++#if defined(BT_OVER_SDIO)
++#define SDIO_FUNC_ENABLE_3	0x08	/* function 2 I/O enable */
++#define SDIO_FUNC_DISABLE_3	0xF0	/* function 2 I/O enable */
++#endif /* defined (BT_OVER_SDIO) */
++
++/* io_rdys */
++#define SDIO_FUNC_READY_1	0x02	/* function 1 I/O ready */
++#define SDIO_FUNC_READY_2	0x04	/* function 2 I/O ready */
++
++/* intr_ctl */
++#define INTR_CTL_MASTER_EN	0x1	/* interrupt enable master */
++#define INTR_CTL_FUNC1_EN	0x2	/* interrupt enable for function 1 */
++#define INTR_CTL_FUNC2_EN	0x4	/* interrupt enable for function 2 */
++#if defined(BT_OVER_SDIO)
++#define INTR_CTL_FUNC3_EN	0x8	/* interrupt enable for function 3 */
++#endif /* defined (BT_OVER_SDIO) */
++/* intr_status */
++#define INTR_STATUS_FUNC1	0x2	/* interrupt pending for function 1 */
++#define INTR_STATUS_FUNC2	0x4	/* interrupt pending for function 2 */
++
++/* io_abort */
++#define IO_ABORT_RESET_ALL	0x08	/* I/O card reset */
++#define IO_ABORT_FUNC_MASK	0x07	/* abort selction: function x */
++
++/* bus_inter */
++#define BUS_CARD_DETECT_DIS	0x80	/* Card Detect disable */
++#define BUS_SPI_CONT_INTR_CAP	0x40	/* support continuous SPI interrupt */
++#define BUS_SPI_CONT_INTR_EN	0x20	/* continuous SPI interrupt enable */
++#define BUS_SD_DATA_WIDTH_MASK	0x03	/* bus width mask */
++#define BUS_SD_DATA_WIDTH_4BIT	0x02	/* bus width 4-bit mode */
++#define BUS_SD_DATA_WIDTH_1BIT	0x00	/* bus width 1-bit mode */
++
++/* capability */
++#define SDIO_CAP_4BLS		0x80	/* 4-bit support for low speed card */
++#define SDIO_CAP_LSC		0x40	/* low speed card */
++#define SDIO_CAP_E4MI		0x20	/* enable interrupt between block of data in 4-bit mode */
++#define SDIO_CAP_S4MI		0x10	/* support interrupt between block of data in 4-bit mode */
++#define SDIO_CAP_SBS		0x08	/* support suspend/resume */
++#define SDIO_CAP_SRW		0x04	/* support read wait */
++#define SDIO_CAP_SMB		0x02	/* support multi-block transfer */
++#define SDIO_CAP_SDC		0x01	/* Support Direct commands during multi-byte transfer */
++
++/* power_control */
++#define SDIO_POWER_SMPC		0x01	/* supports master power control (RO) */
++#define SDIO_POWER_EMPC		0x02	/* enable master power control (allow > 200mA) (RW) */
++
++/* speed_control (control device entry into high-speed clocking mode) */
++#define SDIO_SPEED_SHS		0x01	/* supports high-speed [clocking] mode (RO) */
++#define SDIO_SPEED_EHS		0x02	/* enable high-speed [clocking] mode (RW) */
++#define SDIO_SPEED_UHSI_DDR50	   0x08
++
++/* for setting bus speed in card: 0x13h */
++#define SDIO_BUS_SPEED_UHSISEL_M	BITFIELD_MASK(3)
++#define SDIO_BUS_SPEED_UHSISEL_S	1
++
++/* for getting bus speed cap in card: 0x14h */
++#define SDIO_BUS_SPEED_UHSICAP_M	BITFIELD_MASK(3)
++#define SDIO_BUS_SPEED_UHSICAP_S	0
++
++/* for getting driver type CAP in card: 0x15h */
++#define SDIO_BUS_DRVR_TYPE_CAP_M	BITFIELD_MASK(3)
++#define SDIO_BUS_DRVR_TYPE_CAP_S	0
++
++/* for setting driver type selection in card: 0x15h */
++#define SDIO_BUS_DRVR_TYPE_SEL_M	BITFIELD_MASK(2)
++#define SDIO_BUS_DRVR_TYPE_SEL_S	4
++
++/* for getting async int support in card: 0x16h */
++#define SDIO_BUS_ASYNCINT_CAP_M	BITFIELD_MASK(1)
++#define SDIO_BUS_ASYNCINT_CAP_S	0
++
++/* for setting async int selection in card: 0x16h */
++#define SDIO_BUS_ASYNCINT_SEL_M	BITFIELD_MASK(1)
++#define SDIO_BUS_ASYNCINT_SEL_S	1
++
++/* brcm sepint */
++#define SDIO_SEPINT_MASK	0x01	/* route sdpcmdev intr onto separate pad (chip-specific) */
++#define SDIO_SEPINT_OE		0x02	/* 1 asserts output enable for above pad */
++#define SDIO_SEPINT_ACT_HI	0x04	/* use active high interrupt level instead of active low */
++
++/* FBR structure for function 1-7, FBR addresses and register offsets */
++typedef volatile struct {
++	uint8	devctr;			/* device interface, CSA control */
++	uint8	ext_dev;		/* extended standard I/O device type code */
++	uint8	pwr_sel;		/* power selection support */
++	uint8	PAD[6];			/* reserved */
++
++	uint8	cis_low;		/* CIS LSB */
++	uint8	cis_mid;
++	uint8	cis_high;		/* CIS MSB */
++	uint8	csa_low;		/* code storage area, LSB */
++	uint8	csa_mid;
++	uint8	csa_high;		/* code storage area, MSB */
++	uint8	csa_dat_win;		/* data access window to function */
++
++	uint8	fnx_blk_size[2];	/* block size, little endian */
++} sdio_fbr_t;
++
++/* Maximum number of I/O funcs */
++#define SDIOD_MAX_FUNCS			8
++#define SDIOD_MAX_IOFUNCS		7
++
++/* SDIO Device FBR Start Address  */
++#define SDIOD_FBR_STARTADDR		0x100
++
++/* SDIO Device FBR Size */
++#define SDIOD_FBR_SIZE			0x100
++
++/* Macro to calculate FBR register base */
++#define SDIOD_FBR_BASE(n)		((n) * 0x100)
++
++/* Function register offsets */
++#define SDIOD_FBR_DEVCTR		0x00	/* basic info for function */
++#define SDIOD_FBR_EXT_DEV		0x01	/* extended I/O device code */
++#define SDIOD_FBR_PWR_SEL		0x02	/* power selection bits */
++
++/* SDIO Function CIS ptr offset */
++#define SDIOD_FBR_CISPTR_0		0x09
++#define SDIOD_FBR_CISPTR_1		0x0A
++#define SDIOD_FBR_CISPTR_2		0x0B
++
++/* Code Storage Area pointer */
++#define SDIOD_FBR_CSA_ADDR_0		0x0C
++#define SDIOD_FBR_CSA_ADDR_1		0x0D
++#define SDIOD_FBR_CSA_ADDR_2		0x0E
++#define SDIOD_FBR_CSA_DATA		0x0F
++
++/* SDIO Function I/O Block Size */
++#define SDIOD_FBR_BLKSIZE_0		0x10
++#define SDIOD_FBR_BLKSIZE_1		0x11
++
++/* devctr */
++#define SDIOD_FBR_DEVCTR_DIC	0x0f	/* device interface code */
++#define SDIOD_FBR_DECVTR_CSA	0x40	/* CSA support flag */
++#define SDIOD_FBR_DEVCTR_CSA_EN	0x80	/* CSA enabled */
++/* interface codes */
++#define SDIOD_DIC_NONE		0	/* SDIO standard interface is not supported */
++#define SDIOD_DIC_UART		1
++#define SDIOD_DIC_BLUETOOTH_A	2
++#define SDIOD_DIC_BLUETOOTH_B	3
++#define SDIOD_DIC_GPS		4
++#define SDIOD_DIC_CAMERA	5
++#define SDIOD_DIC_PHS		6
++#define SDIOD_DIC_WLAN		7
++#define SDIOD_DIC_EXT		0xf	/* extended device interface, read ext_dev register */
++
++/* pwr_sel */
++#define SDIOD_PWR_SEL_SPS	0x01	/* supports power selection */
++#define SDIOD_PWR_SEL_EPS	0x02	/* enable power selection (low-current mode) */
++
++/* misc defines */
++#define SDIO_FUNC_0		0
++#define SDIO_FUNC_1		1
++#define SDIO_FUNC_2		2
++#define SDIO_FUNC_4		4
++#define SDIO_FUNC_5		5
++#define SDIO_FUNC_6		6
++#define SDIO_FUNC_7		7
++
++#define SD_CARD_TYPE_UNKNOWN	0	/* bad type or unrecognized */
++#define SD_CARD_TYPE_IO		1	/* IO only card */
++#define SD_CARD_TYPE_MEMORY	2	/* memory only card */
++#define SD_CARD_TYPE_COMBO	3	/* IO and memory combo card */
++
++#define SDIO_MAX_BLOCK_SIZE	2048	/* maximum block size for block mode operation */
++#define SDIO_MIN_BLOCK_SIZE	1	/* minimum block size for block mode operation */
++
++/* Card registers: status bit position */
++#define CARDREG_STATUS_BIT_OUTOFRANGE		31
++#define CARDREG_STATUS_BIT_COMCRCERROR		23
++#define CARDREG_STATUS_BIT_ILLEGALCOMMAND	22
++#define CARDREG_STATUS_BIT_ERROR		19
++#define CARDREG_STATUS_BIT_IOCURRENTSTATE3	12
++#define CARDREG_STATUS_BIT_IOCURRENTSTATE2	11
++#define CARDREG_STATUS_BIT_IOCURRENTSTATE1	10
++#define CARDREG_STATUS_BIT_IOCURRENTSTATE0	9
++#define CARDREG_STATUS_BIT_FUN_NUM_ERROR	4
++
++
++
++#define SD_CMD_GO_IDLE_STATE		0	/* mandatory for SDIO */
++#define SD_CMD_SEND_OPCOND		1
++#define SD_CMD_MMC_SET_RCA		3
++#define SD_CMD_IO_SEND_OP_COND		5	/* mandatory for SDIO */
++#define SD_CMD_SELECT_DESELECT_CARD	7
++#define SD_CMD_SEND_CSD			9
++#define SD_CMD_SEND_CID			10
++#define SD_CMD_STOP_TRANSMISSION	12
++#define SD_CMD_SEND_STATUS		13
++#define SD_CMD_GO_INACTIVE_STATE	15
++#define SD_CMD_SET_BLOCKLEN		16
++#define SD_CMD_READ_SINGLE_BLOCK	17
++#define SD_CMD_READ_MULTIPLE_BLOCK	18
++#define SD_CMD_WRITE_BLOCK		24
++#define SD_CMD_WRITE_MULTIPLE_BLOCK	25
++#define SD_CMD_PROGRAM_CSD		27
++#define SD_CMD_SET_WRITE_PROT		28
++#define SD_CMD_CLR_WRITE_PROT		29
++#define SD_CMD_SEND_WRITE_PROT		30
++#define SD_CMD_ERASE_WR_BLK_START	32
++#define SD_CMD_ERASE_WR_BLK_END		33
++#define SD_CMD_ERASE			38
++#define SD_CMD_LOCK_UNLOCK		42
++#define SD_CMD_IO_RW_DIRECT		52	/* mandatory for SDIO */
++#define SD_CMD_IO_RW_EXTENDED		53	/* mandatory for SDIO */
++#define SD_CMD_APP_CMD			55
++#define SD_CMD_GEN_CMD			56
++#define SD_CMD_READ_OCR			58
++#define SD_CMD_CRC_ON_OFF		59	/* mandatory for SDIO */
++#define SD_ACMD_SD_STATUS		13
++#define SD_ACMD_SEND_NUM_WR_BLOCKS	22
++#define SD_ACMD_SET_WR_BLOCK_ERASE_CNT	23
++#define SD_ACMD_SD_SEND_OP_COND		41
++#define SD_ACMD_SET_CLR_CARD_DETECT	42
++#define SD_ACMD_SEND_SCR		51
++
++/* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */
++#define SD_IO_OP_READ		0   /* Read_Write: Read */
++#define SD_IO_OP_WRITE		1   /* Read_Write: Write */
++#define SD_IO_RW_NORMAL		0   /* no RAW */
++#define SD_IO_RW_RAW		1   /* RAW */
++#define SD_IO_BYTE_MODE		0   /* Byte Mode */
++#define SD_IO_BLOCK_MODE	1   /* BlockMode */
++#define SD_IO_FIXED_ADDRESS	0   /* fix Address */
++#define SD_IO_INCREMENT_ADDRESS	1   /* IncrementAddress */
++
++/* build SD_CMD_IO_RW_DIRECT Argument */
++#define SDIO_IO_RW_DIRECT_ARG(rw, raw, func, addr, data) \
++	((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((raw) & 1) << 27) | \
++	 (((addr) & 0x1FFFF) << 9) | ((data) & 0xFF))
++
++/* build SD_CMD_IO_RW_EXTENDED Argument */
++#define SDIO_IO_RW_EXTENDED_ARG(rw, blk, func, addr, inc_addr, count) \
++	((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((blk) & 1) << 27) | \
++	 (((inc_addr) & 1) << 26) | (((addr) & 0x1FFFF) << 9) | ((count) & 0x1FF))
++
++/* SDIO response parameters */
++#define SD_RSP_NO_NONE			0
++#define SD_RSP_NO_1			1
++#define SD_RSP_NO_2			2
++#define SD_RSP_NO_3			3
++#define SD_RSP_NO_4			4
++#define SD_RSP_NO_5			5
++#define SD_RSP_NO_6			6
++
++	/* Modified R6 response (to CMD3) */
++#define SD_RSP_MR6_COM_CRC_ERROR	0x8000
++#define SD_RSP_MR6_ILLEGAL_COMMAND	0x4000
++#define SD_RSP_MR6_ERROR		0x2000
++
++	/* Modified R1 in R4 Response (to CMD5) */
++#define SD_RSP_MR1_SBIT			0x80
++#define SD_RSP_MR1_PARAMETER_ERROR	0x40
++#define SD_RSP_MR1_RFU5			0x20
++#define SD_RSP_MR1_FUNC_NUM_ERROR	0x10
++#define SD_RSP_MR1_COM_CRC_ERROR	0x08
++#define SD_RSP_MR1_ILLEGAL_COMMAND	0x04
++#define SD_RSP_MR1_RFU1			0x02
++#define SD_RSP_MR1_IDLE_STATE		0x01
++
++	/* R5 response (to CMD52 and CMD53) */
++#define SD_RSP_R5_COM_CRC_ERROR		0x80
++#define SD_RSP_R5_ILLEGAL_COMMAND	0x40
++#define SD_RSP_R5_IO_CURRENTSTATE1	0x20
++#define SD_RSP_R5_IO_CURRENTSTATE0	0x10
++#define SD_RSP_R5_ERROR			0x08
++#define SD_RSP_R5_RFU			0x04
++#define SD_RSP_R5_FUNC_NUM_ERROR	0x02
++#define SD_RSP_R5_OUT_OF_RANGE		0x01
++
++#define SD_RSP_R5_ERRBITS		0xCB
++
++
++/* ------------------------------------------------
++ *  SDIO Commands and responses
++ *
++ *  I/O only commands are:
++ *      CMD0, CMD3, CMD5, CMD7, CMD14, CMD15, CMD52, CMD53
++ * ------------------------------------------------
++ */
++
++/* SDIO Commands */
++#define SDIOH_CMD_0		0
++#define SDIOH_CMD_3		3
++#define SDIOH_CMD_5		5
++#define SDIOH_CMD_7		7
++#define SDIOH_CMD_11		11
++#define SDIOH_CMD_14		14
++#define SDIOH_CMD_15		15
++#define SDIOH_CMD_19		19
++#define SDIOH_CMD_52		52
++#define SDIOH_CMD_53		53
++#define SDIOH_CMD_59		59
++
++/* SDIO Command Responses */
++#define SDIOH_RSP_NONE		0
++#define SDIOH_RSP_R1		1
++#define SDIOH_RSP_R2		2
++#define SDIOH_RSP_R3		3
++#define SDIOH_RSP_R4		4
++#define SDIOH_RSP_R5		5
++#define SDIOH_RSP_R6		6
++
++/*
++ *  SDIO Response Error flags
++ */
++#define SDIOH_RSP5_ERROR_FLAGS	0xCB
++
++/* ------------------------------------------------
++ * SDIO Command structures. I/O only commands are:
++ *
++ * 	CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53
++ * ------------------------------------------------
++ */
++
++#define CMD5_OCR_M		BITFIELD_MASK(24)
++#define CMD5_OCR_S		0
++
++#define CMD5_S18R_M		BITFIELD_MASK(1)
++#define CMD5_S18R_S		24
++
++#define CMD7_RCA_M		BITFIELD_MASK(16)
++#define CMD7_RCA_S		16
++
++#define CMD14_RCA_M		BITFIELD_MASK(16)
++#define CMD14_RCA_S		16
++#define CMD14_SLEEP_M		BITFIELD_MASK(1)
++#define CMD14_SLEEP_S		15
++
++#define CMD_15_RCA_M		BITFIELD_MASK(16)
++#define CMD_15_RCA_S		16
++
++#define CMD52_DATA_M		BITFIELD_MASK(8)  /* Bits [7:0]    - Write Data/Stuff bits of CMD52
++						   */
++#define CMD52_DATA_S		0
++#define CMD52_REG_ADDR_M	BITFIELD_MASK(17) /* Bits [25:9]   - register address */
++#define CMD52_REG_ADDR_S	9
++#define CMD52_RAW_M		BITFIELD_MASK(1)  /* Bit  27       - Read after Write flag */
++#define CMD52_RAW_S		27
++#define CMD52_FUNCTION_M	BITFIELD_MASK(3)  /* Bits [30:28]  - Function number */
++#define CMD52_FUNCTION_S	28
++#define CMD52_RW_FLAG_M		BITFIELD_MASK(1)  /* Bit  31       - R/W flag */
++#define CMD52_RW_FLAG_S		31
++
++
++#define CMD53_BYTE_BLK_CNT_M	BITFIELD_MASK(9) /* Bits [8:0]     - Byte/Block Count of CMD53 */
++#define CMD53_BYTE_BLK_CNT_S	0
++#define CMD53_REG_ADDR_M	BITFIELD_MASK(17) /* Bits [25:9]   - register address */
++#define CMD53_REG_ADDR_S	9
++#define CMD53_OP_CODE_M		BITFIELD_MASK(1)  /* Bit  26       - R/W Operation Code */
++#define CMD53_OP_CODE_S		26
++#define CMD53_BLK_MODE_M	BITFIELD_MASK(1)  /* Bit  27       - Block Mode */
++#define CMD53_BLK_MODE_S	27
++#define CMD53_FUNCTION_M	BITFIELD_MASK(3)  /* Bits [30:28]  - Function number */
++#define CMD53_FUNCTION_S	28
++#define CMD53_RW_FLAG_M		BITFIELD_MASK(1)  /* Bit  31       - R/W flag */
++#define CMD53_RW_FLAG_S		31
++
++/* ------------------------------------------------------
++ * SDIO Command Response structures for SD1 and SD4 modes
++ *  -----------------------------------------------------
++ */
++#define RSP4_IO_OCR_M		BITFIELD_MASK(24) /* Bits [23:0]  - Card's OCR Bits [23:0] */
++#define RSP4_IO_OCR_S		0
++
++#define RSP4_S18A_M			BITFIELD_MASK(1) /* Bits [23:0]  - Card's OCR Bits [23:0] */
++#define RSP4_S18A_S			24
++
++#define RSP4_STUFF_M		BITFIELD_MASK(3)  /* Bits [26:24] - Stuff bits */
++#define RSP4_STUFF_S		24
++#define RSP4_MEM_PRESENT_M	BITFIELD_MASK(1)  /* Bit  27      - Memory present */
++#define RSP4_MEM_PRESENT_S	27
++#define RSP4_NUM_FUNCS_M	BITFIELD_MASK(3)  /* Bits [30:28] - Number of I/O funcs */
++#define RSP4_NUM_FUNCS_S	28
++#define RSP4_CARD_READY_M	BITFIELD_MASK(1)  /* Bit  31      - SDIO card ready */
++#define RSP4_CARD_READY_S	31
++
++#define RSP6_STATUS_M		BITFIELD_MASK(16) /* Bits [15:0]  - Card status bits [19,22,23,12:0]
++						   */
++#define RSP6_STATUS_S		0
++#define RSP6_IO_RCA_M		BITFIELD_MASK(16) /* Bits [31:16] - RCA bits[31-16] */
++#define RSP6_IO_RCA_S		16
++
++#define RSP1_AKE_SEQ_ERROR_M	BITFIELD_MASK(1)  /* Bit 3       - Authentication seq error */
++#define RSP1_AKE_SEQ_ERROR_S	3
++#define RSP1_APP_CMD_M		BITFIELD_MASK(1)  /* Bit 5       - Card expects ACMD */
++#define RSP1_APP_CMD_S		5
++#define RSP1_READY_FOR_DATA_M	BITFIELD_MASK(1)  /* Bit 8       - Ready for data (buff empty) */
++#define RSP1_READY_FOR_DATA_S	8
++#define RSP1_CURR_STATE_M	BITFIELD_MASK(4)  /* Bits [12:9] - State of card
++						   * when Cmd was received
++						   */
++#define RSP1_CURR_STATE_S	9
++#define RSP1_EARSE_RESET_M	BITFIELD_MASK(1)  /* Bit 13   - Erase seq cleared */
++#define RSP1_EARSE_RESET_S	13
++#define RSP1_CARD_ECC_DISABLE_M	BITFIELD_MASK(1)  /* Bit 14   - Card ECC disabled */
++#define RSP1_CARD_ECC_DISABLE_S	14
++#define RSP1_WP_ERASE_SKIP_M	BITFIELD_MASK(1)  /* Bit 15   - Partial blocks erased due to W/P */
++#define RSP1_WP_ERASE_SKIP_S	15
++#define RSP1_CID_CSD_OVERW_M	BITFIELD_MASK(1)  /* Bit 16   - Illegal write to CID or R/O bits
++						   * of CSD
++						   */
++#define RSP1_CID_CSD_OVERW_S	16
++#define RSP1_ERROR_M		BITFIELD_MASK(1)  /* Bit 19   - General/Unknown error */
++#define RSP1_ERROR_S		19
++#define RSP1_CC_ERROR_M		BITFIELD_MASK(1)  /* Bit 20   - Internal Card Control error */
++#define RSP1_CC_ERROR_S		20
++#define RSP1_CARD_ECC_FAILED_M	BITFIELD_MASK(1)  /* Bit 21   - Card internal ECC failed
++						   * to correct data
++						   */
++#define RSP1_CARD_ECC_FAILED_S	21
++#define RSP1_ILLEGAL_CMD_M	BITFIELD_MASK(1)  /* Bit 22   - Cmd not legal for the card state */
++#define RSP1_ILLEGAL_CMD_S	22
++#define RSP1_COM_CRC_ERROR_M	BITFIELD_MASK(1)  /* Bit 23   - CRC check of previous command failed
++						   */
++#define RSP1_COM_CRC_ERROR_S	23
++#define RSP1_LOCK_UNLOCK_FAIL_M	BITFIELD_MASK(1)  /* Bit 24   - Card lock-unlock Cmd Seq error */
++#define RSP1_LOCK_UNLOCK_FAIL_S	24
++#define RSP1_CARD_LOCKED_M	BITFIELD_MASK(1)  /* Bit 25   - Card locked by the host */
++#define RSP1_CARD_LOCKED_S	25
++#define RSP1_WP_VIOLATION_M	BITFIELD_MASK(1)  /* Bit 26   - Attempt to program
++						   * write-protected blocks
++						   */
++#define RSP1_WP_VIOLATION_S	26
++#define RSP1_ERASE_PARAM_M	BITFIELD_MASK(1)  /* Bit 27   - Invalid erase blocks */
++#define RSP1_ERASE_PARAM_S	27
++#define RSP1_ERASE_SEQ_ERR_M	BITFIELD_MASK(1)  /* Bit 28   - Erase Cmd seq error */
++#define RSP1_ERASE_SEQ_ERR_S	28
++#define RSP1_BLK_LEN_ERR_M	BITFIELD_MASK(1)  /* Bit 29   - Block length error */
++#define RSP1_BLK_LEN_ERR_S	29
++#define RSP1_ADDR_ERR_M		BITFIELD_MASK(1)  /* Bit 30   - Misaligned address */
++#define RSP1_ADDR_ERR_S		30
++#define RSP1_OUT_OF_RANGE_M	BITFIELD_MASK(1)  /* Bit 31   - Cmd arg was out of range */
++#define RSP1_OUT_OF_RANGE_S	31
++
++
++#define RSP5_DATA_M		BITFIELD_MASK(8)  /* Bits [0:7]   - data */
++#define RSP5_DATA_S		0
++#define RSP5_FLAGS_M		BITFIELD_MASK(8)  /* Bit  [15:8]  - Rsp flags */
++#define RSP5_FLAGS_S		8
++#define RSP5_STUFF_M		BITFIELD_MASK(16) /* Bits [31:16] - Stuff bits */
++#define RSP5_STUFF_S		16
++
++/* ----------------------------------------------
++ * SDIO Command Response structures for SPI mode
++ * ----------------------------------------------
++ */
++#define SPIRSP4_IO_OCR_M	BITFIELD_MASK(16) /* Bits [15:0]    - Card's OCR Bits [23:8] */
++#define SPIRSP4_IO_OCR_S	0
++#define SPIRSP4_STUFF_M		BITFIELD_MASK(3)  /* Bits [18:16]   - Stuff bits */
++#define SPIRSP4_STUFF_S		16
++#define SPIRSP4_MEM_PRESENT_M	BITFIELD_MASK(1)  /* Bit  19        - Memory present */
++#define SPIRSP4_MEM_PRESENT_S	19
++#define SPIRSP4_NUM_FUNCS_M	BITFIELD_MASK(3)  /* Bits [22:20]   - Number of I/O funcs */
++#define SPIRSP4_NUM_FUNCS_S	20
++#define SPIRSP4_CARD_READY_M	BITFIELD_MASK(1)  /* Bit  23        - SDIO card ready */
++#define SPIRSP4_CARD_READY_S	23
++#define SPIRSP4_IDLE_STATE_M	BITFIELD_MASK(1)  /* Bit  24        - idle state */
++#define SPIRSP4_IDLE_STATE_S	24
++#define SPIRSP4_ILLEGAL_CMD_M	BITFIELD_MASK(1)  /* Bit  26        - Illegal Cmd error */
++#define SPIRSP4_ILLEGAL_CMD_S	26
++#define SPIRSP4_COM_CRC_ERROR_M	BITFIELD_MASK(1)  /* Bit  27        - COM CRC error */
++#define SPIRSP4_COM_CRC_ERROR_S	27
++#define SPIRSP4_FUNC_NUM_ERROR_M	BITFIELD_MASK(1)  /* Bit  28        - Function number error
++							   */
++#define SPIRSP4_FUNC_NUM_ERROR_S	28
++#define SPIRSP4_PARAM_ERROR_M	BITFIELD_MASK(1)  /* Bit  30        - Parameter Error Bit */
++#define SPIRSP4_PARAM_ERROR_S	30
++#define SPIRSP4_START_BIT_M	BITFIELD_MASK(1)  /* Bit  31        - Start Bit */
++#define SPIRSP4_START_BIT_S	31
++
++#define SPIRSP5_DATA_M			BITFIELD_MASK(8)  /* Bits [23:16]   - R/W Data */
++#define SPIRSP5_DATA_S			16
++#define SPIRSP5_IDLE_STATE_M		BITFIELD_MASK(1)  /* Bit  24        - Idle state */
++#define SPIRSP5_IDLE_STATE_S		24
++#define SPIRSP5_ILLEGAL_CMD_M		BITFIELD_MASK(1)  /* Bit  26        - Illegal Cmd error */
++#define SPIRSP5_ILLEGAL_CMD_S		26
++#define SPIRSP5_COM_CRC_ERROR_M		BITFIELD_MASK(1)  /* Bit  27        - COM CRC error */
++#define SPIRSP5_COM_CRC_ERROR_S		27
++#define SPIRSP5_FUNC_NUM_ERROR_M	BITFIELD_MASK(1)  /* Bit  28        - Function number error
++							   */
++#define SPIRSP5_FUNC_NUM_ERROR_S	28
++#define SPIRSP5_PARAM_ERROR_M		BITFIELD_MASK(1)  /* Bit  30        - Parameter Error Bit */
++#define SPIRSP5_PARAM_ERROR_S		30
++#define SPIRSP5_START_BIT_M		BITFIELD_MASK(1)  /* Bit  31        - Start Bit */
++#define SPIRSP5_START_BIT_S		31
++
++/* RSP6 card status format; Pg 68 Physical Layer spec v 1.10 */
++#define RSP6STAT_AKE_SEQ_ERROR_M	BITFIELD_MASK(1)  /* Bit 3	- Authentication seq error
++							   */
++#define RSP6STAT_AKE_SEQ_ERROR_S	3
++#define RSP6STAT_APP_CMD_M		BITFIELD_MASK(1)  /* Bit 5	- Card expects ACMD */
++#define RSP6STAT_APP_CMD_S		5
++#define RSP6STAT_READY_FOR_DATA_M	BITFIELD_MASK(1)  /* Bit 8	- Ready for data
++							   * (buff empty)
++							   */
++#define RSP6STAT_READY_FOR_DATA_S	8
++#define RSP6STAT_CURR_STATE_M		BITFIELD_MASK(4)  /* Bits [12:9] - Card state at
++							   * Cmd reception
++							   */
++#define RSP6STAT_CURR_STATE_S		9
++#define RSP6STAT_ERROR_M		BITFIELD_MASK(1)  /* Bit 13  - General/Unknown error Bit 19
++							   */
++#define RSP6STAT_ERROR_S		13
++#define RSP6STAT_ILLEGAL_CMD_M		BITFIELD_MASK(1)  /* Bit 14  - Illegal cmd for
++							   * card state Bit 22
++							   */
++#define RSP6STAT_ILLEGAL_CMD_S		14
++#define RSP6STAT_COM_CRC_ERROR_M	BITFIELD_MASK(1)  /* Bit 15  - CRC previous command
++							   * failed Bit 23
++							   */
++#define RSP6STAT_COM_CRC_ERROR_S	15
++
++#define SDIOH_XFER_TYPE_READ    SD_IO_OP_READ
++#define SDIOH_XFER_TYPE_WRITE   SD_IO_OP_WRITE
++
++/* command issue options */
++#define CMD_OPTION_DEFAULT	0
++#define CMD_OPTION_TUNING	1
++
++#endif /* def BCMSDIO */
++#endif /* _SDIO_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/sdioh.h b/module_drivers/drivers/net/wireless/bcmdhd/include/sdioh.h
+new file mode 100644
+index 000000000..f37c5f62a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/sdioh.h
+@@ -0,0 +1,448 @@
++/*
++ * SDIO Host Controller Spec header file
++ * Register map and definitions for the Standard Host Controller
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: sdioh.h 514727 2014-11-12 03:02:48Z $
++ */
++
++#ifndef	_SDIOH_H
++#define	_SDIOH_H
++
++#define SD_SysAddr			0x000
++#define SD_BlockSize			0x004
++#define SD_BlockCount 			0x006
++#define SD_Arg0				0x008
++#define SD_Arg1 			0x00A
++#define SD_TransferMode			0x00C
++#define SD_Command 			0x00E
++#define SD_Response0			0x010
++#define SD_Response1 			0x012
++#define SD_Response2			0x014
++#define SD_Response3 			0x016
++#define SD_Response4			0x018
++#define SD_Response5 			0x01A
++#define SD_Response6			0x01C
++#define SD_Response7 			0x01E
++#define SD_BufferDataPort0		0x020
++#define SD_BufferDataPort1 		0x022
++#define SD_PresentState			0x024
++#define SD_HostCntrl			0x028
++#define SD_PwrCntrl			0x029
++#define SD_BlockGapCntrl 		0x02A
++#define SD_WakeupCntrl 			0x02B
++#define SD_ClockCntrl			0x02C
++#define SD_TimeoutCntrl 		0x02E
++#define SD_SoftwareReset		0x02F
++#define SD_IntrStatus			0x030
++#define SD_ErrorIntrStatus 		0x032
++#define SD_IntrStatusEnable		0x034
++#define SD_ErrorIntrStatusEnable 	0x036
++#define SD_IntrSignalEnable		0x038
++#define SD_ErrorIntrSignalEnable 	0x03A
++#define SD_CMD12ErrorStatus		0x03C
++#define SD_Capabilities			0x040
++#define SD_Capabilities3		0x044
++#define SD_MaxCurCap			0x048
++#define SD_MaxCurCap_Reserved		0x04C
++#define SD_ADMA_ErrStatus		0x054
++#define SD_ADMA_SysAddr			0x58
++#define SD_SlotInterruptStatus		0x0FC
++#define SD_HostControllerVersion 	0x0FE
++#define	SD_GPIO_Reg			0x100
++#define	SD_GPIO_OE			0x104
++#define	SD_GPIO_Enable			0x108
++
++/* SD specific registers in PCI config space */
++#define SD_SlotInfo	0x40
++
++/* HC 3.0 specific registers and offsets */
++#define SD3_HostCntrl2			0x03E
++/* preset regsstart and count */
++#define SD3_PresetValStart		0x060
++#define SD3_PresetValCount		8
++/* preset-indiv regs */
++#define SD3_PresetVal_init		0x060
++#define SD3_PresetVal_default	0x062
++#define SD3_PresetVal_HS		0x064
++#define SD3_PresetVal_SDR12		0x066
++#define SD3_PresetVal_SDR25		0x068
++#define SD3_PresetVal_SDR50		0x06a
++#define SD3_PresetVal_SDR104	0x06c
++#define SD3_PresetVal_DDR50		0x06e
++/* SDIO3.0 Revx specific Registers */
++#define SD3_Tuning_Info_Register 0x0EC
++#define SD3_WL_BT_reset_register 0x0F0
++
++
++/* preset value indices */
++#define SD3_PRESETVAL_INITIAL_IX	0
++#define SD3_PRESETVAL_DESPEED_IX	1
++#define SD3_PRESETVAL_HISPEED_IX	2
++#define SD3_PRESETVAL_SDR12_IX		3
++#define SD3_PRESETVAL_SDR25_IX		4
++#define SD3_PRESETVAL_SDR50_IX		5
++#define SD3_PRESETVAL_SDR104_IX		6
++#define SD3_PRESETVAL_DDR50_IX		7
++
++/* SD_Capabilities reg (0x040) */
++#define CAP_TO_CLKFREQ_M 	BITFIELD_MASK(6)
++#define CAP_TO_CLKFREQ_S 	0
++#define CAP_TO_CLKUNIT_M  	BITFIELD_MASK(1)
++#define CAP_TO_CLKUNIT_S 	7
++/* Note: for sdio-2.0 case, this mask has to be 6 bits, but msb 2
++	bits are reserved. going ahead with 8 bits, as it is req for 3.0
++*/
++#define CAP_BASECLK_M 		BITFIELD_MASK(8)
++#define CAP_BASECLK_S 		8
++#define CAP_MAXBLOCK_M 		BITFIELD_MASK(2)
++#define CAP_MAXBLOCK_S		16
++#define CAP_ADMA2_M		BITFIELD_MASK(1)
++#define CAP_ADMA2_S		19
++#define CAP_ADMA1_M		BITFIELD_MASK(1)
++#define CAP_ADMA1_S		20
++#define CAP_HIGHSPEED_M		BITFIELD_MASK(1)
++#define CAP_HIGHSPEED_S		21
++#define CAP_DMA_M		BITFIELD_MASK(1)
++#define CAP_DMA_S		22
++#define CAP_SUSPEND_M		BITFIELD_MASK(1)
++#define CAP_SUSPEND_S		23
++#define CAP_VOLT_3_3_M		BITFIELD_MASK(1)
++#define CAP_VOLT_3_3_S		24
++#define CAP_VOLT_3_0_M		BITFIELD_MASK(1)
++#define CAP_VOLT_3_0_S		25
++#define CAP_VOLT_1_8_M		BITFIELD_MASK(1)
++#define CAP_VOLT_1_8_S		26
++#define CAP_64BIT_HOST_M	BITFIELD_MASK(1)
++#define CAP_64BIT_HOST_S	28
++
++#define SDIO_OCR_READ_FAIL	(2)
++
++
++#define CAP_ASYNCINT_SUP_M	BITFIELD_MASK(1)
++#define CAP_ASYNCINT_SUP_S	29
++
++#define CAP_SLOTTYPE_M		BITFIELD_MASK(2)
++#define CAP_SLOTTYPE_S		30
++
++#define CAP3_MSBits_OFFSET	(32)
++/* note: following are caps MSB32 bits.
++	So the bits start from 0, instead of 32. that is why
++	CAP3_MSBits_OFFSET is subtracted.
++*/
++#define CAP3_SDR50_SUP_M		BITFIELD_MASK(1)
++#define CAP3_SDR50_SUP_S		(32 - CAP3_MSBits_OFFSET)
++
++#define CAP3_SDR104_SUP_M	BITFIELD_MASK(1)
++#define CAP3_SDR104_SUP_S	(33 - CAP3_MSBits_OFFSET)
++
++#define CAP3_DDR50_SUP_M	BITFIELD_MASK(1)
++#define CAP3_DDR50_SUP_S	(34 - CAP3_MSBits_OFFSET)
++
++/* for knowing the clk caps in a single read */
++#define CAP3_30CLKCAP_M		BITFIELD_MASK(3)
++#define CAP3_30CLKCAP_S		(32 - CAP3_MSBits_OFFSET)
++
++#define CAP3_DRIVTYPE_A_M	BITFIELD_MASK(1)
++#define CAP3_DRIVTYPE_A_S	(36 - CAP3_MSBits_OFFSET)
++
++#define CAP3_DRIVTYPE_C_M	BITFIELD_MASK(1)
++#define CAP3_DRIVTYPE_C_S	(37 - CAP3_MSBits_OFFSET)
++
++#define CAP3_DRIVTYPE_D_M	BITFIELD_MASK(1)
++#define CAP3_DRIVTYPE_D_S	(38 - CAP3_MSBits_OFFSET)
++
++#define CAP3_RETUNING_TC_M	BITFIELD_MASK(4)
++#define CAP3_RETUNING_TC_S	(40 - CAP3_MSBits_OFFSET)
++
++#define CAP3_TUNING_SDR50_M	BITFIELD_MASK(1)
++#define CAP3_TUNING_SDR50_S	(45 - CAP3_MSBits_OFFSET)
++
++#define CAP3_RETUNING_MODES_M	BITFIELD_MASK(2)
++#define CAP3_RETUNING_MODES_S	(46 - CAP3_MSBits_OFFSET)
++
++#define CAP3_CLK_MULT_M		BITFIELD_MASK(8)
++#define CAP3_CLK_MULT_S		(48 - CAP3_MSBits_OFFSET)
++
++#define PRESET_DRIVR_SELECT_M	BITFIELD_MASK(2)
++#define PRESET_DRIVR_SELECT_S	14
++
++#define PRESET_CLK_DIV_M	BITFIELD_MASK(10)
++#define PRESET_CLK_DIV_S	0
++
++/* SD_MaxCurCap reg (0x048) */
++#define CAP_CURR_3_3_M		BITFIELD_MASK(8)
++#define CAP_CURR_3_3_S		0
++#define CAP_CURR_3_0_M		BITFIELD_MASK(8)
++#define CAP_CURR_3_0_S		8
++#define CAP_CURR_1_8_M		BITFIELD_MASK(8)
++#define CAP_CURR_1_8_S		16
++
++/* SD_SysAddr: Offset 0x0000, Size 4 bytes */
++
++/* SD_BlockSize: Offset 0x004, Size 2 bytes */
++#define BLKSZ_BLKSZ_M		BITFIELD_MASK(12)
++#define BLKSZ_BLKSZ_S		0
++#define BLKSZ_BNDRY_M		BITFIELD_MASK(3)
++#define BLKSZ_BNDRY_S		12
++
++/* SD_BlockCount: Offset 0x006, size 2 bytes */
++
++/* SD_Arg0: Offset 0x008, size = 4 bytes  */
++/* SD_TransferMode Offset 0x00C, size = 2 bytes */
++#define XFER_DMA_ENABLE_M   	BITFIELD_MASK(1)
++#define XFER_DMA_ENABLE_S	0
++#define XFER_BLK_COUNT_EN_M 	BITFIELD_MASK(1)
++#define XFER_BLK_COUNT_EN_S	1
++#define XFER_CMD_12_EN_M    	BITFIELD_MASK(1)
++#define XFER_CMD_12_EN_S 	2
++#define XFER_DATA_DIRECTION_M	BITFIELD_MASK(1)
++#define XFER_DATA_DIRECTION_S	4
++#define XFER_MULTI_BLOCK_M	BITFIELD_MASK(1)
++#define XFER_MULTI_BLOCK_S	5
++
++/* SD_Command: Offset 0x00E, size = 2 bytes */
++/* resp_type field */
++#define RESP_TYPE_NONE 		0
++#define RESP_TYPE_136  		1
++#define RESP_TYPE_48   		2
++#define RESP_TYPE_48_BUSY	3
++/* type field */
++#define CMD_TYPE_NORMAL		0
++#define CMD_TYPE_SUSPEND	1
++#define CMD_TYPE_RESUME		2
++#define CMD_TYPE_ABORT		3
++
++#define CMD_RESP_TYPE_M		BITFIELD_MASK(2)	/* Bits [0-1] 	- Response type */
++#define CMD_RESP_TYPE_S		0
++#define CMD_CRC_EN_M		BITFIELD_MASK(1)	/* Bit 3 	- CRC enable */
++#define CMD_CRC_EN_S		3
++#define CMD_INDEX_EN_M		BITFIELD_MASK(1)	/* Bit 4 	- Enable index checking */
++#define CMD_INDEX_EN_S		4
++#define CMD_DATA_EN_M		BITFIELD_MASK(1)	/* Bit 5 	- Using DAT line */
++#define CMD_DATA_EN_S		5
++#define CMD_TYPE_M		BITFIELD_MASK(2)	/* Bit [6-7] 	- Normal, abort, resume, etc
++							 */
++#define CMD_TYPE_S		6
++#define CMD_INDEX_M		BITFIELD_MASK(6)	/* Bits [8-13] 	- Command number */
++#define CMD_INDEX_S		8
++
++/* SD_BufferDataPort0	: Offset 0x020, size = 2 or 4 bytes */
++/* SD_BufferDataPort1 	: Offset 0x022, size = 2 bytes */
++/* SD_PresentState	: Offset 0x024, size = 4 bytes */
++#define PRES_CMD_INHIBIT_M	BITFIELD_MASK(1)	/* Bit 0	May use CMD */
++#define PRES_CMD_INHIBIT_S	0
++#define PRES_DAT_INHIBIT_M	BITFIELD_MASK(1)	/* Bit 1	May use DAT */
++#define PRES_DAT_INHIBIT_S	1
++#define PRES_DAT_BUSY_M		BITFIELD_MASK(1)	/* Bit 2	DAT is busy */
++#define PRES_DAT_BUSY_S		2
++#define PRES_PRESENT_RSVD_M	BITFIELD_MASK(5)	/* Bit [3-7]	rsvd */
++#define PRES_PRESENT_RSVD_S	3
++#define PRES_WRITE_ACTIVE_M	BITFIELD_MASK(1)	/* Bit 8	Write is active */
++#define PRES_WRITE_ACTIVE_S	8
++#define PRES_READ_ACTIVE_M	BITFIELD_MASK(1)	/* Bit 9	Read is active */
++#define PRES_READ_ACTIVE_S	9
++#define PRES_WRITE_DATA_RDY_M	BITFIELD_MASK(1)	/* Bit 10	Write buf is avail */
++#define PRES_WRITE_DATA_RDY_S	10
++#define PRES_READ_DATA_RDY_M	BITFIELD_MASK(1)	/* Bit 11	Read buf data avail */
++#define PRES_READ_DATA_RDY_S	11
++#define PRES_CARD_PRESENT_M	BITFIELD_MASK(1)	/* Bit 16	Card present - debounced */
++#define PRES_CARD_PRESENT_S	16
++#define PRES_CARD_STABLE_M	BITFIELD_MASK(1)	/* Bit 17	Debugging */
++#define PRES_CARD_STABLE_S	17
++#define PRES_CARD_PRESENT_RAW_M	BITFIELD_MASK(1)	/* Bit 18	Not debounced */
++#define PRES_CARD_PRESENT_RAW_S	18
++#define PRES_WRITE_ENABLED_M	BITFIELD_MASK(1)	/* Bit 19	Write protected? */
++#define PRES_WRITE_ENABLED_S	19
++#define PRES_DAT_SIGNAL_M	BITFIELD_MASK(4)	/* Bit [20-23]	Debugging */
++#define PRES_DAT_SIGNAL_S	20
++#define PRES_CMD_SIGNAL_M	BITFIELD_MASK(1)	/* Bit 24	Debugging */
++#define PRES_CMD_SIGNAL_S	24
++
++/* SD_HostCntrl: Offset 0x028, size = 1 bytes */
++#define HOST_LED_M		BITFIELD_MASK(1)	/* Bit 0	LED On/Off */
++#define HOST_LED_S		0
++#define HOST_DATA_WIDTH_M	BITFIELD_MASK(1)	/* Bit 1	4 bit enable */
++#define HOST_DATA_WIDTH_S	1
++#define HOST_HI_SPEED_EN_M	BITFIELD_MASK(1)	/* Bit 2	High speed vs low speed */
++#define HOST_DMA_SEL_S		3
++#define HOST_DMA_SEL_M		BITFIELD_MASK(2)	/* Bit 4:3	DMA Select */
++#define HOST_HI_SPEED_EN_S	2
++
++/* Host Control2: */
++#define HOSTCtrl2_PRESVAL_EN_M	BITFIELD_MASK(1)	/* 1 bit */
++#define HOSTCtrl2_PRESVAL_EN_S	15					/* bit# */
++
++#define HOSTCtrl2_ASYINT_EN_M	BITFIELD_MASK(1)	/* 1 bit */
++#define HOSTCtrl2_ASYINT_EN_S	14					/* bit# */
++
++#define HOSTCtrl2_SAMPCLK_SEL_M	BITFIELD_MASK(1)	/* 1 bit */
++#define HOSTCtrl2_SAMPCLK_SEL_S	7					/* bit# */
++
++#define HOSTCtrl2_EXEC_TUNING_M	BITFIELD_MASK(1)	/* 1 bit */
++#define HOSTCtrl2_EXEC_TUNING_S	6					/* bit# */
++
++#define HOSTCtrl2_DRIVSTRENGTH_SEL_M	BITFIELD_MASK(2)	/* 2 bit */
++#define HOSTCtrl2_DRIVSTRENGTH_SEL_S	4					/* bit# */
++
++#define HOSTCtrl2_1_8SIG_EN_M	BITFIELD_MASK(1)	/* 1 bit */
++#define HOSTCtrl2_1_8SIG_EN_S	3					/* bit# */
++
++#define HOSTCtrl2_UHSMODE_SEL_M	BITFIELD_MASK(3)	/* 3 bit */
++#define HOSTCtrl2_UHSMODE_SEL_S	0					/* bit# */
++
++#define HOST_CONTR_VER_2		(1)
++#define HOST_CONTR_VER_3		(2)
++
++/* misc defines */
++#define SD1_MODE 		0x1	/* SD Host Cntrlr Spec */
++#define SD4_MODE 		0x2	/* SD Host Cntrlr Spec */
++
++/* SD_PwrCntrl: Offset 0x029, size = 1 bytes */
++#define PWR_BUS_EN_M		BITFIELD_MASK(1)	/* Bit 0	Power the bus */
++#define PWR_BUS_EN_S		0
++#define PWR_VOLTS_M		BITFIELD_MASK(3)	/* Bit [1-3]	Voltage Select */
++#define PWR_VOLTS_S		1
++
++/* SD_SoftwareReset: Offset 0x02F, size = 1 byte */
++#define SW_RESET_ALL_M		BITFIELD_MASK(1)	/* Bit 0	Reset All */
++#define SW_RESET_ALL_S		0
++#define SW_RESET_CMD_M		BITFIELD_MASK(1)	/* Bit 1	CMD Line Reset */
++#define SW_RESET_CMD_S		1
++#define SW_RESET_DAT_M		BITFIELD_MASK(1)	/* Bit 2	DAT Line Reset */
++#define SW_RESET_DAT_S		2
++
++/* SD_IntrStatus: Offset 0x030, size = 2 bytes */
++/* Defs also serve SD_IntrStatusEnable and SD_IntrSignalEnable */
++#define INTSTAT_CMD_COMPLETE_M		BITFIELD_MASK(1)	/* Bit 0 */
++#define INTSTAT_CMD_COMPLETE_S		0
++#define INTSTAT_XFER_COMPLETE_M		BITFIELD_MASK(1)
++#define INTSTAT_XFER_COMPLETE_S		1
++#define INTSTAT_BLOCK_GAP_EVENT_M	BITFIELD_MASK(1)
++#define INTSTAT_BLOCK_GAP_EVENT_S	2
++#define INTSTAT_DMA_INT_M		BITFIELD_MASK(1)
++#define INTSTAT_DMA_INT_S		3
++#define INTSTAT_BUF_WRITE_READY_M	BITFIELD_MASK(1)
++#define INTSTAT_BUF_WRITE_READY_S	4
++#define INTSTAT_BUF_READ_READY_M	BITFIELD_MASK(1)
++#define INTSTAT_BUF_READ_READY_S	5
++#define INTSTAT_CARD_INSERTION_M	BITFIELD_MASK(1)
++#define INTSTAT_CARD_INSERTION_S	6
++#define INTSTAT_CARD_REMOVAL_M		BITFIELD_MASK(1)
++#define INTSTAT_CARD_REMOVAL_S		7
++#define INTSTAT_CARD_INT_M		BITFIELD_MASK(1)
++#define INTSTAT_CARD_INT_S		8
++#define INTSTAT_RETUNING_INT_M		BITFIELD_MASK(1)	/* Bit 12 */
++#define INTSTAT_RETUNING_INT_S		12
++#define INTSTAT_ERROR_INT_M		BITFIELD_MASK(1)	/* Bit 15 */
++#define INTSTAT_ERROR_INT_S		15
++
++/* SD_ErrorIntrStatus: Offset 0x032, size = 2 bytes */
++/* Defs also serve SD_ErrorIntrStatusEnable and SD_ErrorIntrSignalEnable */
++#define ERRINT_CMD_TIMEOUT_M		BITFIELD_MASK(1)
++#define ERRINT_CMD_TIMEOUT_S		0
++#define ERRINT_CMD_CRC_M		BITFIELD_MASK(1)
++#define ERRINT_CMD_CRC_S		1
++#define ERRINT_CMD_ENDBIT_M		BITFIELD_MASK(1)
++#define ERRINT_CMD_ENDBIT_S		2
++#define ERRINT_CMD_INDEX_M		BITFIELD_MASK(1)
++#define ERRINT_CMD_INDEX_S		3
++#define ERRINT_DATA_TIMEOUT_M		BITFIELD_MASK(1)
++#define ERRINT_DATA_TIMEOUT_S		4
++#define ERRINT_DATA_CRC_M		BITFIELD_MASK(1)
++#define ERRINT_DATA_CRC_S		5
++#define ERRINT_DATA_ENDBIT_M		BITFIELD_MASK(1)
++#define ERRINT_DATA_ENDBIT_S		6
++#define ERRINT_CURRENT_LIMIT_M		BITFIELD_MASK(1)
++#define ERRINT_CURRENT_LIMIT_S		7
++#define ERRINT_AUTO_CMD12_M		BITFIELD_MASK(1)
++#define ERRINT_AUTO_CMD12_S		8
++#define ERRINT_VENDOR_M			BITFIELD_MASK(4)
++#define ERRINT_VENDOR_S			12
++#define ERRINT_ADMA_M			BITFIELD_MASK(1)
++#define ERRINT_ADMA_S			9
++
++/* Also provide definitions in "normal" form to allow combined masks */
++#define ERRINT_CMD_TIMEOUT_BIT		0x0001
++#define ERRINT_CMD_CRC_BIT		0x0002
++#define ERRINT_CMD_ENDBIT_BIT		0x0004
++#define ERRINT_CMD_INDEX_BIT		0x0008
++#define ERRINT_DATA_TIMEOUT_BIT		0x0010
++#define ERRINT_DATA_CRC_BIT		0x0020
++#define ERRINT_DATA_ENDBIT_BIT		0x0040
++#define ERRINT_CURRENT_LIMIT_BIT	0x0080
++#define ERRINT_AUTO_CMD12_BIT		0x0100
++#define ERRINT_ADMA_BIT		0x0200
++
++/* Masks to select CMD vs. DATA errors */
++#define ERRINT_CMD_ERRS		(ERRINT_CMD_TIMEOUT_BIT | ERRINT_CMD_CRC_BIT |\
++				 ERRINT_CMD_ENDBIT_BIT | ERRINT_CMD_INDEX_BIT)
++#define ERRINT_DATA_ERRS	(ERRINT_DATA_TIMEOUT_BIT | ERRINT_DATA_CRC_BIT |\
++				 ERRINT_DATA_ENDBIT_BIT | ERRINT_ADMA_BIT)
++#define ERRINT_TRANSFER_ERRS	(ERRINT_CMD_ERRS | ERRINT_DATA_ERRS)
++
++/* SD_WakeupCntr_BlockGapCntrl : Offset 0x02A , size = bytes */
++/* SD_ClockCntrl	: Offset 0x02C , size = bytes */
++/* SD_SoftwareReset_TimeoutCntrl 	: Offset 0x02E , size = bytes */
++/* SD_IntrStatus	: Offset 0x030 , size = bytes */
++/* SD_ErrorIntrStatus 	: Offset 0x032 , size = bytes */
++/* SD_IntrStatusEnable	: Offset 0x034 , size = bytes */
++/* SD_ErrorIntrStatusEnable : Offset 0x036 , size = bytes */
++/* SD_IntrSignalEnable	: Offset 0x038 , size = bytes */
++/* SD_ErrorIntrSignalEnable : Offset 0x03A , size = bytes */
++/* SD_CMD12ErrorStatus	: Offset 0x03C , size = bytes */
++/* SD_Capabilities	: Offset 0x040 , size = bytes */
++/* SD_MaxCurCap		: Offset 0x048 , size = bytes */
++/* SD_MaxCurCap_Reserved: Offset 0x04C , size = bytes */
++/* SD_SlotInterruptStatus: Offset 0x0FC , size = bytes */
++/* SD_HostControllerVersion : Offset 0x0FE , size = bytes */
++
++/* SDIO Host Control Register DMA Mode Definitions */
++#define SDIOH_SDMA_MODE			0
++#define SDIOH_ADMA1_MODE		1
++#define SDIOH_ADMA2_MODE		2
++#define SDIOH_ADMA2_64_MODE		3
++
++#define ADMA2_ATTRIBUTE_VALID		(1 << 0)	/* ADMA Descriptor line valid */
++#define ADMA2_ATTRIBUTE_END			(1 << 1)	/* End of Descriptor */
++#define ADMA2_ATTRIBUTE_INT			(1 << 2)	/* Interrupt when line is done */
++#define ADMA2_ATTRIBUTE_ACT_NOP		(0 << 4)	/* Skip current line, go to next. */
++#define ADMA2_ATTRIBUTE_ACT_RSV		(1 << 4)	/* Same as NOP */
++#define ADMA1_ATTRIBUTE_ACT_SET		(1 << 4)	/* ADMA1 Only - set transfer length */
++#define ADMA2_ATTRIBUTE_ACT_TRAN	(2 << 4)	/* Transfer Data of one descriptor line. */
++#define ADMA2_ATTRIBUTE_ACT_LINK	(3 << 4)	/* Link Descriptor */
++
++/* ADMA2 Descriptor Table Entry for 32-bit Address */
++typedef struct adma2_dscr_32b {
++	uint32 len_attr;
++	uint32 phys_addr;
++} adma2_dscr_32b_t;
++
++/* ADMA1 Descriptor Table Entry */
++typedef struct adma1_dscr {
++	uint32 phys_addr_attr;
++} adma1_dscr_t;
++
++#endif /* _SDIOH_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/sdiovar.h b/module_drivers/drivers/net/wireless/bcmdhd/include/sdiovar.h
+new file mode 100644
+index 000000000..719eeb106
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/sdiovar.h
+@@ -0,0 +1,107 @@
++/*
++ * Structure used by apps whose drivers access SDIO drivers.
++ * Pulled out separately so dhdu and wlu can both use it.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: sdiovar.h 610006 2016-01-06 01:38:47Z $
++ */
++
++#ifndef _sdiovar_h_
++#define _sdiovar_h_
++
++#include <typedefs.h>
++
++/* require default structure packing */
++#define BWL_DEFAULT_PACKING
++#include <packed_section_start.h>
++
++typedef struct sdreg {
++	int func;
++	int offset;
++	int value;
++} sdreg_t;
++
++/* Common msglevel constants */
++#define SDH_ERROR_VAL		0x0001	/* Error */
++#define SDH_TRACE_VAL		0x0002	/* Trace */
++#define SDH_INFO_VAL		0x0004	/* Info */
++#define SDH_DEBUG_VAL		0x0008	/* Debug */
++#define SDH_DATA_VAL		0x0010	/* Data */
++#define SDH_CTRL_VAL		0x0020	/* Control Regs */
++#define SDH_LOG_VAL		0x0040	/* Enable bcmlog */
++#define SDH_DMA_VAL		0x0080	/* DMA */
++#define SDH_COST_VAL		0x8000	/* Control Regs */
++
++#define NUM_PREV_TRANSACTIONS	16
++
++
++typedef struct sdio_bus_metrics {
++	uint32 active_dur;	/* msecs */
++
++	/* Generic */
++	uint32 data_intr_cnt;	/* data interrupt counter */
++	uint32 mb_intr_cnt;	/* mailbox interrupt counter */
++	uint32 error_intr_cnt;	/* error interrupt counter */
++	uint32 wakehost_cnt;	/* counter for OOB wakehost */
++
++	/* DS forcewake */
++	uint32 ds_wake_on_cnt;	/* counter for (clock) ON   */
++	uint32 ds_wake_on_dur;	/* duration for (clock) ON) */
++	uint32 ds_wake_off_cnt;	/* counter for (clock) OFF  */
++	uint32 ds_wake_off_dur;	/* duration for (clock) OFF */
++
++	/* DS_D0 state */
++	uint32 ds_d0_cnt;	/* counter for DS_D0 state */
++	uint32 ds_d0_dur;	/* duration for DS_D0 state */
++
++	/* DS_D3 state */
++	uint32 ds_d3_cnt;	/* counter for DS_D3 state */
++	uint32 ds_d3_dur;	/* duration for DS_D3 state */
++
++	/* DS DEV_WAKE */
++	uint32 ds_dw_assrt_cnt;		/* counter for DW_ASSERT */
++	uint32 ds_dw_dassrt_cnt;	/* counter for DW_DASSERT */
++
++	/* DS mailbox signals */
++	uint32 ds_tx_dsreq_cnt;		/* counter for tx HMB_DATA_DSREQ */
++	uint32 ds_tx_dsexit_cnt;	/* counter for tx HMB_DATA_DSEXIT */
++	uint32 ds_tx_d3ack_cnt;		/* counter for tx HMB_DATA_D3ACK */
++	uint32 ds_tx_d3exit_cnt;	/* counter for tx HMB_DATA_D3EXIT */
++	uint32 ds_rx_dsack_cnt;		/* counter for rx SMB_DATA_DSACK */
++	uint32 ds_rx_dsnack_cnt;	/* counter for rx SMB_DATA_DSNACK */
++	uint32 ds_rx_d3inform_cnt;	/* counter for rx SMB_DATA_D3INFORM */
++} sdio_bus_metrics_t;
++
++/* Bus interface info for SDIO */
++typedef struct wl_pwr_sdio_stats {
++	uint16 type;	     /* WL_PWRSTATS_TYPE_SDIO */
++	uint16 len;	     /* Up to 4K-1, top 4 bits are reserved */
++
++	sdio_bus_metrics_t sdio;	/* stats from SDIO bus driver */
++} wl_pwr_sdio_stats_t;
++
++#include <packed_section_end.h>
++
++#endif /* _sdiovar_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/sdspi.h b/module_drivers/drivers/net/wireless/bcmdhd/include/sdspi.h
+new file mode 100644
+index 000000000..c5b8aff22
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/sdspi.h
+@@ -0,0 +1,78 @@
++/*
++ * SD-SPI Protocol Standard
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: sdspi.h 700076 2017-05-17 14:42:22Z $
++ */
++#ifndef	_SD_SPI_H
++#define	_SD_SPI_H
++
++#define SPI_START_M		BITFIELD_MASK(1)	/* Bit [31] 	- Start Bit */
++#define SPI_START_S		31
++#define SPI_DIR_M		BITFIELD_MASK(1)	/* Bit [30] 	- Direction */
++#define SPI_DIR_S		30
++#define SPI_CMD_INDEX_M		BITFIELD_MASK(6)	/* Bits [29:24] - Command number */
++#define SPI_CMD_INDEX_S		24
++#define SPI_RW_M		BITFIELD_MASK(1)	/* Bit [23] 	- Read=0, Write=1 */
++#define SPI_RW_S		23
++#define SPI_FUNC_M		BITFIELD_MASK(3)	/* Bits [22:20]	- Function Number */
++#define SPI_FUNC_S		20
++#define SPI_RAW_M		BITFIELD_MASK(1)	/* Bit [19] 	- Read After Wr */
++#define SPI_RAW_S		19
++#define SPI_STUFF_M		BITFIELD_MASK(1)	/* Bit [18] 	- Stuff bit */
++#define SPI_STUFF_S		18
++#define SPI_BLKMODE_M		BITFIELD_MASK(1)	/* Bit [19] 	- Blockmode 1=blk */
++#define SPI_BLKMODE_S		19
++#define SPI_OPCODE_M		BITFIELD_MASK(1)	/* Bit [18] 	- OP Code */
++#define SPI_OPCODE_S		18
++#define SPI_ADDR_M		BITFIELD_MASK(17)	/* Bits [17:1] 	- Address */
++#define SPI_ADDR_S		1
++#define SPI_STUFF0_M		BITFIELD_MASK(1)	/* Bit [0] 	- Stuff bit */
++#define SPI_STUFF0_S		0
++
++#define SPI_RSP_START_M		BITFIELD_MASK(1)	/* Bit [7] 	- Start Bit (always 0) */
++#define SPI_RSP_START_S		7
++#define SPI_RSP_PARAM_ERR_M	BITFIELD_MASK(1)	/* Bit [6] 	- Parameter Error */
++#define SPI_RSP_PARAM_ERR_S	6
++#define SPI_RSP_RFU5_M		BITFIELD_MASK(1)	/* Bit [5] 	- RFU (Always 0) */
++#define SPI_RSP_RFU5_S		5
++#define SPI_RSP_FUNC_ERR_M	BITFIELD_MASK(1)	/* Bit [4] 	- Function number error */
++#define SPI_RSP_FUNC_ERR_S	4
++#define SPI_RSP_CRC_ERR_M	BITFIELD_MASK(1)	/* Bit [3] 	- COM CRC Error */
++#define SPI_RSP_CRC_ERR_S	3
++#define SPI_RSP_ILL_CMD_M	BITFIELD_MASK(1)	/* Bit [2] 	- Illegal Command error */
++#define SPI_RSP_ILL_CMD_S	2
++#define SPI_RSP_RFU1_M		BITFIELD_MASK(1)	/* Bit [1] 	- RFU (Always 0) */
++#define SPI_RSP_RFU1_S		1
++#define SPI_RSP_IDLE_M		BITFIELD_MASK(1)	/* Bit [0] 	- In idle state */
++#define SPI_RSP_IDLE_S		0
++
++/* SD-SPI Protocol Definitions */
++#define SDSPI_COMMAND_LEN	6	/* Number of bytes in an SD command */
++#define SDSPI_START_BLOCK	0xFE	/* SD Start Block Token */
++#define SDSPI_IDLE_PAD		0xFF	/* SD-SPI idle value for MOSI */
++#define SDSPI_START_BIT_MASK	0x80
++
++#endif /* _SD_SPI_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/siutils.h b/module_drivers/drivers/net/wireless/bcmdhd/include/siutils.h
+new file mode 100644
+index 000000000..2afca2549
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/siutils.h
+@@ -0,0 +1,729 @@
++/*
++ * Misc utility routines for accessing the SOC Interconnects
++ * of Broadcom HNBU chips.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: siutils.h 668442 2016-11-03 08:42:43Z $
++ */
++
++#ifndef	_siutils_h_
++#define	_siutils_h_
++
++#ifdef SR_DEBUG
++#include "wlioctl.h"
++#endif /* SR_DEBUG */
++
++
++#define WARM_BOOT	0xA0B0C0D0
++
++#ifdef BCM_BACKPLANE_TIMEOUT
++
++#define SI_MAX_ERRLOG_SIZE	4
++typedef struct si_axi_error
++{
++	uint32 error;
++	uint32 coreid;
++	uint32 errlog_lo;
++	uint32 errlog_hi;
++	uint32 errlog_id;
++	uint32 errlog_flags;
++	uint32 errlog_status;
++} si_axi_error_t;
++
++typedef struct si_axi_error_info
++{
++	uint32 count;
++	si_axi_error_t axi_error[SI_MAX_ERRLOG_SIZE];
++} si_axi_error_info_t;
++#endif /* BCM_BACKPLANE_TIMEOUT */
++
++/**
++ * Data structure to export all chip specific common variables
++ *   public (read-only) portion of siutils handle returned by si_attach()/si_kattach()
++ */
++struct si_pub {
++	uint	socitype;		/**< SOCI_SB, SOCI_AI */
++
++	uint	bustype;		/**< SI_BUS, PCI_BUS */
++	uint	buscoretype;		/**< PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
++	uint	buscorerev;		/**< buscore rev */
++	uint	buscoreidx;		/**< buscore index */
++	int	ccrev;			/**< chip common core rev */
++	uint32	cccaps;			/**< chip common capabilities */
++	uint32  cccaps_ext;			/**< chip common capabilities extension */
++	int	pmurev;			/**< pmu core rev */
++	uint32	pmucaps;		/**< pmu capabilities */
++	uint	boardtype;		/**< board type */
++	uint    boardrev;               /* board rev */
++	uint	boardvendor;		/**< board vendor */
++	uint	boardflags;		/**< board flags */
++	uint	boardflags2;		/**< board flags2 */
++	uint	chip;			/**< chip number */
++	uint	chiprev;		/**< chip revision */
++	uint	chippkg;		/**< chip package option */
++	uint32	chipst;			/**< chip status */
++	bool	issim;			/**< chip is in simulation or emulation */
++	uint    socirev;		/**< SOC interconnect rev */
++	bool	pci_pr32414;
++	int	gcirev;			/**< gci core rev */
++#ifdef BCM_BACKPLANE_TIMEOUT
++	si_axi_error_info_t * err_info;
++#endif /* BCM_BACKPLANE_TIMEOUT */
++};
++
++/* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
++ * for monolithic driver, it is readonly to prevent accident change
++ */
++typedef const struct si_pub si_t;
++
++/*
++ * Many of the routines below take an 'sih' handle as their first arg.
++ * Allocate this by calling si_attach().  Free it by calling si_detach().
++ * At any one time, the sih is logically focused on one particular si core
++ * (the "current core").
++ * Use si_setcore() or si_setcoreidx() to change the association to another core.
++ */
++#define	SI_OSH		NULL	/**< Use for si_kattach when no osh is available */
++
++#define	BADIDX		(SI_MAXCORES + 1)
++
++/* clkctl xtal what flags */
++#define	XTAL			0x1	/**< primary crystal oscillator (2050) */
++#define	PLL			0x2	/**< main chip pll */
++
++/* clkctl clk mode */
++#define	CLK_FAST		0	/**< force fast (pll) clock */
++#define	CLK_DYNAMIC		2	/**< enable dynamic clock control */
++
++/* GPIO usage priorities */
++#define GPIO_DRV_PRIORITY	0	/**< Driver */
++#define GPIO_APP_PRIORITY	1	/**< Application */
++#define GPIO_HI_PRIORITY	2	/**< Highest priority. Ignore GPIO reservation */
++
++/* GPIO pull up/down */
++#define GPIO_PULLUP		0
++#define GPIO_PULLDN		1
++
++/* GPIO event regtype */
++#define GPIO_REGEVT		0	/**< GPIO register event */
++#define GPIO_REGEVT_INTMSK	1	/**< GPIO register event int mask */
++#define GPIO_REGEVT_INTPOL	2	/**< GPIO register event int polarity */
++
++/* device path */
++#define SI_DEVPATH_BUFSZ	16	/**< min buffer size in bytes */
++
++/* SI routine enumeration: to be used by update function with multiple hooks */
++#define	SI_DOATTACH	1
++#define SI_PCIDOWN	2	/**< wireless interface is down */
++#define SI_PCIUP	3	/**< wireless interface is up */
++
++#ifdef SR_DEBUG
++#define PMU_RES		31
++#endif /* SR_DEBUG */
++
++/* "access" param defines for si_seci_access() below */
++#define SECI_ACCESS_STATUSMASK_SET	0
++#define SECI_ACCESS_INTRS			1
++#define SECI_ACCESS_UART_CTS		2
++#define SECI_ACCESS_UART_RTS		3
++#define SECI_ACCESS_UART_RXEMPTY	4
++#define SECI_ACCESS_UART_GETC		5
++#define SECI_ACCESS_UART_TXFULL		6
++#define SECI_ACCESS_UART_PUTC		7
++#define SECI_ACCESS_STATUSMASK_GET	8
++
++#define	ISSIM_ENAB(sih)	FALSE
++
++#define INVALID_ADDR (~0)
++
++/* PMU clock/power control */
++#if defined(BCMPMUCTL)
++#define PMUCTL_ENAB(sih)	(BCMPMUCTL)
++#else
++#define PMUCTL_ENAB(sih)	((sih)->cccaps & CC_CAP_PMU)
++#endif
++
++#if defined(BCMAOBENAB)
++#define AOB_ENAB(sih)  (BCMAOBENAB)
++#else
++#define AOB_ENAB(sih)	((sih)->ccrev >= 35 ? \
++			((sih)->cccaps_ext & CC_CAP_EXT_AOB_PRESENT) : 0)
++#endif /* BCMAOBENAB */
++
++/* chipcommon clock/power control (exclusive with PMU's) */
++#if defined(BCMPMUCTL) && BCMPMUCTL
++#define CCCTL_ENAB(sih)		(0)
++#define CCPLL_ENAB(sih)		(0)
++#else
++#define CCCTL_ENAB(sih)		((sih)->cccaps & CC_CAP_PWR_CTL)
++#define CCPLL_ENAB(sih)		((sih)->cccaps & CC_CAP_PLL_MASK)
++#endif
++
++typedef void (*gci_gpio_handler_t)(uint32 stat, void *arg);
++
++/* External BT Coex enable mask */
++#define CC_BTCOEX_EN_MASK  0x01
++/* External PA enable mask */
++#define GPIO_CTRL_EPA_EN_MASK 0x40
++/* WL/BT control enable mask */
++#define GPIO_CTRL_5_6_EN_MASK 0x60
++#define GPIO_CTRL_7_6_EN_MASK 0xC0
++#define GPIO_OUT_7_EN_MASK 0x80
++
++
++
++/* CR4 specific defines used by the host driver */
++#define SI_CR4_CAP			(0x04)
++#define SI_CR4_BANKIDX		(0x40)
++#define SI_CR4_BANKINFO		(0x44)
++#define SI_CR4_BANKPDA		(0x4C)
++
++#define	ARMCR4_TCBBNB_MASK	0xf0
++#define	ARMCR4_TCBBNB_SHIFT	4
++#define	ARMCR4_TCBANB_MASK	0xf
++#define	ARMCR4_TCBANB_SHIFT	0
++
++#define	SICF_CPUHALT		(0x0020)
++#define	ARMCR4_BSZ_MASK		0x3f
++#define	ARMCR4_BSZ_MULT		8192
++#define	SI_BPIND_1BYTE		0x1
++#define	SI_BPIND_2BYTE		0x3
++#define	SI_BPIND_4BYTE		0xF
++#include <osl_decl.h>
++/* === exported functions === */
++extern si_t *si_attach(uint pcidev, osl_t *osh, volatile void *regs, uint bustype,
++                       void *sdh, char **vars, uint *varsz);
++extern si_t *si_kattach(osl_t *osh);
++extern void si_detach(si_t *sih);
++extern bool si_pci_war16165(si_t *sih);
++extern volatile void *
++si_d11_switch_addrbase(si_t *sih, uint coreunit);
++extern uint si_corelist(si_t *sih, uint coreid[]);
++extern uint si_coreid(si_t *sih);
++extern uint si_flag(si_t *sih);
++extern uint si_flag_alt(si_t *sih);
++extern uint si_intflag(si_t *sih);
++extern uint si_coreidx(si_t *sih);
++extern uint si_coreunit(si_t *sih);
++extern uint si_corevendor(si_t *sih);
++extern uint si_corerev(si_t *sih);
++extern void *si_osh(si_t *sih);
++extern void si_setosh(si_t *sih, osl_t *osh);
++extern uint si_backplane_access(si_t *sih, uint addr, uint size,
++	uint *val, bool read);
++extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
++extern uint si_pmu_corereg(si_t *sih, uint32 idx, uint regoff, uint mask, uint val);
++extern volatile uint32 *si_corereg_addr(si_t *sih, uint coreidx, uint regoff);
++extern volatile void *si_coreregs(si_t *sih);
++extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
++extern uint si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val);
++extern void *si_wrapperregs(si_t *sih);
++extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val);
++extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
++extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val);
++extern void si_commit(si_t *sih);
++extern bool si_iscoreup(si_t *sih);
++extern uint si_numcoreunits(si_t *sih, uint coreid);
++extern uint si_numd11coreunits(si_t *sih);
++extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
++extern volatile void *si_setcoreidx(si_t *sih, uint coreidx);
++extern volatile void *si_setcore(si_t *sih, uint coreid, uint coreunit);
++extern volatile void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val);
++extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
++extern int si_numaddrspaces(si_t *sih);
++extern uint32 si_addrspace(si_t *sih, uint asidx);
++extern uint32 si_addrspacesize(si_t *sih, uint asidx);
++extern void si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size);
++extern int si_corebist(si_t *sih);
++extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
++extern void si_core_disable(si_t *sih, uint32 bits);
++extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m);
++extern uint si_chip_hostif(si_t *sih);
++extern bool si_read_pmu_autopll(si_t *sih);
++extern uint32 si_clock(si_t *sih);
++extern uint32 si_alp_clock(si_t *sih); /* returns [Hz] units */
++extern uint32 si_ilp_clock(si_t *sih); /* returns [Hz] units */
++extern void si_pci_setup(si_t *sih, uint coremask);
++extern void si_pcmcia_init(si_t *sih);
++extern void si_setint(si_t *sih, int siflag);
++extern bool si_backplane64(si_t *sih);
++extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
++	void *intrsenabled_fn, void *intr_arg);
++extern void si_deregister_intr_callback(si_t *sih);
++extern void si_clkctl_init(si_t *sih);
++extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih);
++extern bool si_clkctl_cc(si_t *sih, uint mode);
++extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
++extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val);
++extern void si_btcgpiowar(si_t *sih);
++extern bool si_deviceremoved(si_t *sih);
++extern void si_set_device_removed(si_t *sih, bool status);
++extern uint32 si_sysmem_size(si_t *sih);
++extern uint32 si_socram_size(si_t *sih);
++extern uint32 si_socdevram_size(si_t *sih);
++extern uint32 si_socram_srmem_size(si_t *sih);
++extern void si_socram_set_bankpda(si_t *sih, uint32 bankidx, uint32 bankpda);
++extern void si_socdevram(si_t *sih, bool set, uint8 *ennable, uint8 *protect, uint8 *remap);
++extern bool si_socdevram_pkg(si_t *sih);
++extern bool si_socdevram_remap_isenb(si_t *sih);
++extern uint32 si_socdevram_remap_size(si_t *sih);
++
++extern void si_watchdog(si_t *sih, uint ticks);
++extern void si_watchdog_ms(si_t *sih, uint32 ms);
++extern uint32 si_watchdog_msticks(void);
++extern volatile void *si_gpiosetcore(si_t *sih);
++extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority);
++extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority);
++extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority);
++extern uint32 si_gpioin(si_t *sih);
++extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority);
++extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority);
++extern uint32 si_gpioeventintmask(si_t *sih, uint32 mask, uint32 val, uint8 priority);
++extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val);
++extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, uint8 priority);
++extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, uint8 priority);
++extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val);
++extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val);
++extern uint32 si_gpio_int_enable(si_t *sih, bool enable);
++extern void si_gci_uart_init(si_t *sih, osl_t *osh, uint8 seci_mode);
++extern void si_gci_enable_gpio(si_t *sih, uint8 gpio, uint32 mask, uint32 value);
++extern uint8 si_gci_host_wake_gpio_init(si_t *sih);
++extern void si_gci_host_wake_gpio_enable(si_t *sih, uint8 gpio, bool state);
++
++extern void si_invalidate_second_bar0win(si_t *sih);
++
++/* GCI interrupt handlers */
++extern void si_gci_handler_process(si_t *sih);
++
++/* GCI GPIO event handlers */
++extern void *si_gci_gpioint_handler_register(si_t *sih, uint8 gpio, uint8 sts,
++	gci_gpio_handler_t cb, void *arg);
++extern void si_gci_gpioint_handler_unregister(si_t *sih, void* gci_i);
++extern uint8 si_gci_gpio_status(si_t *sih, uint8 gci_gpio, uint8 mask, uint8 value);
++
++/* Wake-on-wireless-LAN (WOWL) */
++extern bool si_pci_pmecap(si_t *sih);
++extern bool si_pci_fastpmecap(struct osl_info *osh);
++extern bool si_pci_pmestat(si_t *sih);
++extern void si_pci_pmeclr(si_t *sih);
++extern void si_pci_pmeen(si_t *sih);
++extern void si_pci_pmestatclr(si_t *sih);
++extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset);
++extern uint si_pcie_writereg(void *sih, uint addrtype, uint offset, uint val);
++extern void si_deepsleep_count(si_t *sih, bool arm_wakeup);
++
++
++#ifdef BCMSDIO
++extern void si_sdio_init(si_t *sih);
++#endif
++
++extern uint16 si_d11_devid(si_t *sih);
++extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice,
++	uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, uint8 *pciheader);
++
++extern uint32 si_seci_access(si_t *sih, uint32 val, int access);
++extern volatile void* si_seci_init(si_t *sih, uint8 seci_mode);
++extern void si_seci_clk_force(si_t *sih, bool val);
++extern bool si_seci_clk_force_status(si_t *sih);
++
++#define si_eci(sih) 0
++static INLINE void * si_eci_init(si_t *sih) {return NULL;}
++#define si_eci_notify_bt(sih, type, val)  (0)
++#define si_seci(sih) 0
++#define si_seci_upd(sih, a)	do {} while (0)
++static INLINE void * si_gci_init(si_t *sih) {return NULL;}
++#define si_seci_down(sih) do {} while (0)
++#define si_gci(sih) 0
++
++/* OTP status */
++extern bool si_is_otp_disabled(si_t *sih);
++extern bool si_is_otp_powered(si_t *sih);
++extern void si_otp_power(si_t *sih, bool on, uint32* min_res_mask);
++
++/* SPROM availability */
++extern bool si_is_sprom_available(si_t *sih);
++
++/* OTP/SROM CIS stuff */
++extern int si_cis_source(si_t *sih);
++#define CIS_DEFAULT	0
++#define CIS_SROM	1
++#define CIS_OTP		2
++
++/* Fab-id information */
++#define	DEFAULT_FAB	0x0	/**< Original/first fab used for this chip */
++#define	CSM_FAB7	0x1	/**< CSM Fab7 chip */
++#define	TSMC_FAB12	0x2	/**< TSMC Fab12/Fab14 chip */
++#define	SMIC_FAB4	0x3	/**< SMIC Fab4 chip */
++
++extern int si_otp_fabid(si_t *sih, uint16 *fabid, bool rw);
++extern uint16 si_fabid(si_t *sih);
++extern uint16 si_chipid(si_t *sih);
++
++/*
++ * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
++ * The returned path is NULL terminated and has trailing '/'.
++ * Return 0 on success, nonzero otherwise.
++ */
++extern int si_devpath(si_t *sih, char *path, int size);
++extern int si_devpath_pcie(si_t *sih, char *path, int size);
++/* Read variable with prepending the devpath to the name */
++extern char *si_getdevpathvar(si_t *sih, const char *name);
++extern int si_getdevpathintvar(si_t *sih, const char *name);
++extern char *si_coded_devpathvar(si_t *sih, char *varname, int var_len, const char *name);
++
++
++extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val);
++extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val);
++extern uint8 si_pcieltrenable(si_t *sih, uint32 mask, uint32 val);
++extern uint8 si_pcieobffenable(si_t *sih, uint32 mask, uint32 val);
++extern uint32 si_pcieltr_reg(si_t *sih, uint32 reg, uint32 mask, uint32 val);
++extern uint32 si_pcieltrspacing_reg(si_t *sih, uint32 mask, uint32 val);
++extern uint32 si_pcieltrhysteresiscnt_reg(si_t *sih, uint32 mask, uint32 val);
++extern void si_pcie_set_error_injection(si_t *sih, uint32 mode);
++extern void si_pcie_set_L1substate(si_t *sih, uint32 substate);
++extern uint32 si_pcie_get_L1substate(si_t *sih);
++extern void si_war42780_clkreq(si_t *sih, bool clkreq);
++extern void si_pci_down(si_t *sih);
++extern void si_pci_up(si_t *sih);
++extern void si_pci_sleep(si_t *sih);
++extern void si_pcie_war_ovr_update(si_t *sih, uint8 aspm);
++extern void si_pcie_power_save_enable(si_t *sih, bool enable);
++extern void si_pcie_extendL1timer(si_t *sih, bool extend);
++extern int si_pci_fixcfg(si_t *sih);
++extern void si_chippkg_set(si_t *sih, uint);
++extern bool si_is_warmboot(void);
++
++extern void si_chipcontrl_btshd0_4331(si_t *sih, bool on);
++extern void si_chipcontrl_restore(si_t *sih, uint32 val);
++extern uint32 si_chipcontrl_read(si_t *sih);
++extern void si_chipcontrl_epa4331(si_t *sih, bool on);
++extern void si_chipcontrl_epa4331_wowl(si_t *sih, bool enter_wowl);
++extern void si_chipcontrl_srom4360(si_t *sih, bool on);
++extern void si_clk_srom4365(si_t *sih);
++/* Enable BT-COEX & Ex-PA for 4313 */
++extern void si_epa_4313war(si_t *sih);
++extern void si_btc_enable_chipcontrol(si_t *sih);
++/* BT/WL selection for 4313 bt combo >= P250 boards */
++extern void si_btcombo_p250_4313_war(si_t *sih);
++extern void si_btcombo_43228_war(si_t *sih);
++extern void si_clk_pmu_htavail_set(si_t *sih, bool set_clear);
++extern void si_pmu_avb_clk_set(si_t *sih, osl_t *osh, bool set_flag);
++extern void si_pmu_synth_pwrsw_4313_war(si_t *sih);
++extern uint si_pll_reset(si_t *sih);
++/* === debug routines === */
++
++extern bool si_taclear(si_t *sih, bool details);
++
++#if defined(BCMDBG_PHYDUMP)
++struct bcmstrbuf;
++extern int si_dump_pcieinfo(si_t *sih, struct bcmstrbuf *b);
++extern void si_dump_pmuregs(si_t *sih, struct bcmstrbuf *b);
++extern int si_dump_pcieregs(si_t *sih, struct bcmstrbuf *b);
++#endif 
++
++#if defined(BCMDBG_PHYDUMP)
++extern void si_dumpregs(si_t *sih, struct bcmstrbuf *b);
++#endif 
++
++extern uint32 si_ccreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
++extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type);
++extern int si_bpind_access(si_t *sih, uint32 addr_high, uint32 addr_low,
++	int32* data, bool read);
++#ifdef SR_DEBUG
++extern void si_dump_pmu(si_t *sih, void *pmu_var);
++extern void si_pmu_keep_on(si_t *sih, int32 int_val);
++extern uint32 si_pmu_keep_on_get(si_t *sih);
++extern uint32 si_power_island_set(si_t *sih, uint32 int_val);
++extern uint32 si_power_island_get(si_t *sih);
++#endif /* SR_DEBUG */
++extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val);
++extern void si_pcie_set_request_size(si_t *sih, uint16 size);
++extern uint16 si_pcie_get_request_size(si_t *sih);
++extern void si_pcie_set_maxpayload_size(si_t *sih, uint16 size);
++extern uint16 si_pcie_get_maxpayload_size(si_t *sih);
++extern uint16 si_pcie_get_ssid(si_t *sih);
++extern uint32 si_pcie_get_bar0(si_t *sih);
++extern int si_pcie_configspace_cache(si_t *sih);
++extern int si_pcie_configspace_restore(si_t *sih);
++extern int si_pcie_configspace_get(si_t *sih, uint8 *buf, uint size);
++
++
++#ifdef BCM_BACKPLANE_TIMEOUT
++extern const si_axi_error_info_t * si_get_axi_errlog_info(si_t *sih);
++extern void si_reset_axi_errlog_info(si_t * sih);
++#endif /* BCM_BACKPLANE_TIMEOUT */
++
++extern uint32 si_tcm_size(si_t *sih);
++extern bool si_has_flops(si_t *sih);
++
++extern int si_set_sromctl(si_t *sih, uint32 value);
++extern uint32 si_get_sromctl(si_t *sih);
++
++extern uint32 si_gci_direct(si_t *sih, uint offset, uint32 mask, uint32 val);
++extern uint32 si_gci_indirect(si_t *sih, uint regidx, uint offset, uint32 mask, uint32 val);
++extern uint32 si_gci_output(si_t *sih, uint reg, uint32 mask, uint32 val);
++extern uint32 si_gci_input(si_t *sih, uint reg);
++extern uint32 si_gci_int_enable(si_t *sih, bool enable);
++extern void si_gci_reset(si_t *sih);
++#ifdef BCMLTECOEX
++extern void si_gci_seci_init(si_t *sih);
++extern void si_ercx_init(si_t *sih, uint32 ltecx_mux, uint32 ltecx_padnum,
++	uint32 ltecx_fnsel, uint32 ltecx_gcigpio);
++#endif /* BCMLTECOEX */
++extern void si_wci2_init(si_t *sih, uint8 baudrate, uint32 ltecx_mux, uint32 ltecx_padnum,
++	uint32 ltecx_fnsel, uint32 ltecx_gcigpio);
++
++extern bool si_btcx_wci2_init(si_t *sih);
++
++extern void si_gci_set_functionsel(si_t *sih, uint32 pin, uint8 fnsel);
++extern uint32 si_gci_get_functionsel(si_t *sih, uint32 pin);
++extern void si_gci_clear_functionsel(si_t *sih, uint8 fnsel);
++extern uint8 si_gci_get_chipctrlreg_idx(uint32 pin, uint32 *regidx, uint32 *pos);
++extern uint32 si_gci_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val);
++extern uint32 si_gci_chipstatus(si_t *sih, uint reg);
++extern uint8 si_enable_device_wake(si_t *sih, uint8 *wake_status, uint8 *cur_status);
++extern void si_swdenable(si_t *sih, uint32 swdflag);
++extern uint8 si_enable_perst_wake(si_t *sih, uint8 *perst_wake_mask, uint8 *perst_cur_status);
++
++extern uint32 si_get_pmu_reg_addr(si_t *sih, uint32 offset);
++#define CHIPCTRLREG1 0x1
++#define CHIPCTRLREG2 0x2
++#define CHIPCTRLREG3 0x3
++#define CHIPCTRLREG4 0x4
++#define CHIPCTRLREG5 0x5
++#define MINRESMASKREG 0x618
++#define MAXRESMASKREG 0x61c
++#define CHIPCTRLADDR 0x650
++#define CHIPCTRLDATA 0x654
++#define RSRCTABLEADDR 0x620
++#define RSRCUPDWNTIME 0x628
++#define PMUREG_RESREQ_MASK 0x68c
++
++void si_update_masks(si_t *sih);
++void si_force_islanding(si_t *sih, bool enable);
++extern uint32 si_pmu_res_req_timer_clr(si_t *sih);
++extern void si_pmu_rfldo(si_t *sih, bool on);
++extern void si_survive_perst_war(si_t *sih, bool reset, uint32 sperst_mask, uint32 spert_val);
++extern uint32 si_pcie_set_ctrlreg(si_t *sih, uint32 sperst_mask, uint32 spert_val);
++extern void si_pcie_ltr_war(si_t *sih);
++extern void si_pcie_hw_LTR_war(si_t *sih);
++extern void si_pcie_hw_L1SS_war(si_t *sih);
++extern void si_pciedev_crwlpciegen2(si_t *sih);
++extern void si_pcie_prep_D3(si_t *sih, bool enter_D3);
++extern void si_pciedev_reg_pm_clk_period(si_t *sih);
++extern void si_d11rsdb_core1_alt_reg_clk_dis(si_t *sih);
++extern void si_d11rsdb_core1_alt_reg_clk_en(si_t *sih);
++extern void si_pcie_disable_oobselltr(si_t *sih);
++extern uint32 si_raw_reg(si_t *sih, uint32 reg, uint32 val, uint32 wrire_req);
++
++#ifdef WLRSDB
++extern void si_d11rsdb_core_disable(si_t *sih, uint32 bits);
++extern void si_d11rsdb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
++extern void set_secondary_d11_core(si_t *sih, void **secmap, void **secwrap);
++#endif
++
++
++/* Macro to enable clock gating changes in different cores */
++#define MEM_CLK_GATE_BIT 	5
++#define GCI_CLK_GATE_BIT 	18
++
++#define USBAPP_CLK_BIT		0
++#define PCIE_CLK_BIT		3
++#define ARMCR4_DBG_CLK_BIT	4
++#define SAMPLE_SYNC_CLK_BIT 	17
++#define PCIE_TL_CLK_BIT		18
++#define HQ_REQ_BIT		24
++#define PLL_DIV2_BIT_START	9
++#define PLL_DIV2_MASK		(0x37 << PLL_DIV2_BIT_START)
++#define PLL_DIV2_DIS_OP		(0x37 << PLL_DIV2_BIT_START)
++
++#define pmu_corereg(si, cc_idx, member, mask, val) \
++	(AOB_ENAB(si) ? \
++		si_pmu_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
++			       OFFSETOF(pmuregs_t, member), mask, val): \
++		si_pmu_corereg(si, cc_idx, OFFSETOF(chipcregs_t, member), mask, val))
++
++/* Used only for the regs present in the pmu core and not present in the old cc core */
++#define PMU_REG_NEW(si, member, mask, val) \
++		si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
++			OFFSETOF(pmuregs_t, member), mask, val)
++
++#define PMU_REG(si, member, mask, val) \
++	(AOB_ENAB(si) ? \
++		si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
++			OFFSETOF(pmuregs_t, member), mask, val): \
++		si_corereg(si, SI_CC_IDX, OFFSETOF(chipcregs_t, member), mask, val))
++
++#define LHL_REG(si, member, mask, val) \
++		si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \
++			OFFSETOF(gciregs_t, member), mask, val)
++
++#define CHIPC_REG(si, member, mask, val) \
++		si_corereg(si, SI_CC_IDX, OFFSETOF(chipcregs_t, member), mask, val)
++
++/* GCI Macros */
++#define ALLONES_32				0xFFFFFFFF
++#define GCI_CCTL_SECIRST_OFFSET			0 /**< SeciReset */
++#define GCI_CCTL_RSTSL_OFFSET			1 /**< ResetSeciLogic */
++#define GCI_CCTL_SECIEN_OFFSET			2 /**< EnableSeci  */
++#define GCI_CCTL_FSL_OFFSET			3 /**< ForceSeciOutLow */
++#define GCI_CCTL_SMODE_OFFSET			4 /**< SeciOpMode, 6:4 */
++#define GCI_CCTL_US_OFFSET			7 /**< UpdateSeci */
++#define GCI_CCTL_BRKONSLP_OFFSET		8 /**< BreakOnSleep */
++#define GCI_CCTL_SILOWTOUT_OFFSET		9 /**< SeciInLowTimeout, 10:9 */
++#define GCI_CCTL_RSTOCC_OFFSET			11 /**< ResetOffChipCoex */
++#define GCI_CCTL_ARESEND_OFFSET			12 /**< AutoBTSigResend */
++#define GCI_CCTL_FGCR_OFFSET			16 /**< ForceGciClkReq */
++#define GCI_CCTL_FHCRO_OFFSET			17 /**< ForceHWClockReqOff */
++#define GCI_CCTL_FREGCLK_OFFSET			18 /**< ForceRegClk */
++#define GCI_CCTL_FSECICLK_OFFSET		19 /**< ForceSeciClk */
++#define GCI_CCTL_FGCA_OFFSET			20 /**< ForceGciClkAvail */
++#define GCI_CCTL_FGCAV_OFFSET			21 /**< ForceGciClkAvailValue */
++#define GCI_CCTL_SCS_OFFSET			24 /**< SeciClkStretch, 31:24 */
++
++#define GCI_MODE_UART				0x0
++#define GCI_MODE_SECI				0x1
++#define GCI_MODE_BTSIG				0x2
++#define GCI_MODE_GPIO				0x3
++#define GCI_MODE_MASK				0x7
++
++#define GCI_CCTL_LOWTOUT_DIS			0x0
++#define GCI_CCTL_LOWTOUT_10BIT			0x1
++#define GCI_CCTL_LOWTOUT_20BIT			0x2
++#define GCI_CCTL_LOWTOUT_30BIT			0x3
++#define GCI_CCTL_LOWTOUT_MASK			0x3
++
++#define GCI_CCTL_SCS_DEF			0x19
++#define GCI_CCTL_SCS_MASK			0xFF
++
++#define GCI_SECIIN_MODE_OFFSET			0
++#define GCI_SECIIN_GCIGPIO_OFFSET		4
++#define GCI_SECIIN_RXID2IP_OFFSET		8
++
++#define GCI_SECIOUT_MODE_OFFSET			0
++#define GCI_SECIOUT_GCIGPIO_OFFSET		4
++#define	GCI_SECIOUT_LOOPBACK_OFFSET		8
++#define GCI_SECIOUT_SECIINRELATED_OFFSET	16
++
++#define GCI_SECIAUX_RXENABLE_OFFSET		0
++#define GCI_SECIFIFO_RXENABLE_OFFSET		16
++
++#define GCI_SECITX_ENABLE_OFFSET		0
++
++#define GCI_GPIOCTL_INEN_OFFSET			0
++#define GCI_GPIOCTL_OUTEN_OFFSET		1
++#define GCI_GPIOCTL_PDN_OFFSET			4
++
++#define GCI_GPIOIDX_OFFSET			16
++
++#define GCI_LTECX_SECI_ID			0 /**< SECI port for LTECX */
++
++/* To access per GCI bit registers */
++#define GCI_REG_WIDTH				32
++
++/* GCI bit positions */
++/* GCI [127:000] = WLAN [127:0] */
++#define GCI_WLAN_IP_ID				0
++#define GCI_WLAN_BEGIN				0
++#define GCI_WLAN_PRIO_POS			(GCI_WLAN_BEGIN + 4)
++#define GCI_WLAN_PERST_POS			(GCI_WLAN_BEGIN + 15)
++
++/* GCI [639:512] = LTE [127:0] */
++#define GCI_LTE_IP_ID				4
++#define GCI_LTE_BEGIN				512
++#define GCI_LTE_FRAMESYNC_POS			(GCI_LTE_BEGIN + 0)
++#define GCI_LTE_RX_POS				(GCI_LTE_BEGIN + 1)
++#define GCI_LTE_TX_POS				(GCI_LTE_BEGIN + 2)
++#define GCI_LTE_WCI2TYPE_POS			(GCI_LTE_BEGIN + 48)
++#define GCI_LTE_WCI2TYPE_MASK			7
++#define GCI_LTE_AUXRXDVALID_POS			(GCI_LTE_BEGIN + 56)
++
++/* Reg Index corresponding to ECI bit no x of ECI space */
++#define GCI_REGIDX(x)				((x)/GCI_REG_WIDTH)
++/* Bit offset of ECI bit no x in 32-bit words */
++#define GCI_BITOFFSET(x)			((x)%GCI_REG_WIDTH)
++
++/* End - GCI Macros */
++
++#ifdef REROUTE_OOBINT
++#define CC_OOB          0x0
++#define M2MDMA_OOB      0x1
++#define PMU_OOB         0x2
++#define D11_OOB         0x3
++#define SDIOD_OOB       0x4
++#define WLAN_OOB	0x5
++#define PMU_OOB_BIT     0x12
++#endif /* REROUTE_OOBINT */
++
++#define GCI_REG(si, offset, mask, val) \
++		(AOB_ENAB(si) ? \
++			si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \
++				offset, mask, val): \
++			si_corereg(si, SI_CC_IDX, offset, mask, val))
++
++extern void si_pll_sr_reinit(si_t *sih);
++extern void si_pll_closeloop(si_t *sih);
++void si_config_4364_d11_oob(si_t *sih, uint coreid);
++extern void si_update_macclk_mul_fact(si_t *sih, uint mul_fact);
++extern uint32 si_get_macclk_mul_fact(si_t *sih);
++extern void si_gci_set_femctrl(si_t *sih, osl_t *osh, bool set);
++extern void si_gci_set_femctrl_mask_ant01(si_t *sih, osl_t *osh, bool set);
++extern uint si_num_slaveports(si_t *sih, uint coreid);
++extern uint32 si_get_slaveport_addr(si_t *sih, uint asidx, uint core_id, uint coreunit);
++extern uint32 si_get_d11_slaveport_addr(si_t *sih, uint asidx, uint coreunit);
++uint si_introff(si_t *sih);
++void si_intrrestore(si_t *sih, uint intr_val);
++void si_nvram_res_masks(si_t *sih, uint32 *min_mask, uint32 *max_mask);
++uint32 si_xtalfreq(si_t *sih);
++extern uint32 si_wrapper_dump_buf_size(si_t *sih);
++extern uint32 si_wrapper_dump_binary(si_t *sih, uchar *p);
++
++/* SR Power Control */
++extern uint32 si_srpwr_request(si_t *sih, uint32 mask, uint32 val);
++extern uint32 si_srpwr_stat_spinwait(si_t *sih, uint32 mask, uint32 val);
++extern uint32 si_srpwr_stat(si_t *sih);
++extern uint32 si_srpwr_domain(si_t *sih);
++
++/* SR Power Control */
++#ifdef BCMSRPWR
++	/* No capabilities bit so using chipid for now */
++	#define SRPWR_CAP(sih)  (\
++		(CHIPID(sih->chip) == BCM4347_CHIP_ID) || \
++		(0))
++
++	extern bool _bcmsrpwr;
++	#if defined(WL_ENAB_RUNTIME_CHECK) || !defined(DONGLEBUILD)
++		#define SRPWR_ENAB()    (_bcmsrpwr)
++	#elif defined(BCMSRPWR_DISABLED)
++		#define SRPWR_ENAB()    (0)
++	#else
++		#define SRPWR_ENAB()    (1)
++	#endif
++#else
++	#define SRPWR_CAP(sih)          (0)
++	#define SRPWR_ENAB()            (0)
++#endif /* BCMSRPWR */
++
++#endif	/* _siutils_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/spid.h b/module_drivers/drivers/net/wireless/bcmdhd/include/spid.h
+new file mode 100644
+index 000000000..8fdefa437
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/spid.h
+@@ -0,0 +1,168 @@
++/*
++ * SPI device spec header file
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: spid.h 514727 2014-11-12 03:02:48Z $
++ */
++
++#ifndef	_SPI_H
++#define	_SPI_H
++
++/*
++ * Brcm SPI Device Register Map.
++ *
++ */
++
++typedef volatile struct {
++	uint8	config;			/* 0x00, len, endian, clock, speed, polarity, wakeup */
++	uint8	response_delay;		/* 0x01, read response delay in bytes (corerev < 3) */
++	uint8	status_enable;		/* 0x02, status-enable, intr with status, response_delay
++					 * function selection, command/data error check
++					 */
++	uint8	reset_bp;		/* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */
++	uint16	intr_reg;		/* 0x04, Intr status register */
++	uint16	intr_en_reg;		/* 0x06, Intr mask register */
++	uint32	status_reg;		/* 0x08, RO, Status bits of last spi transfer */
++	uint16	f1_info_reg;		/* 0x0c, RO, enabled, ready for data transfer, blocksize */
++	uint16	f2_info_reg;		/* 0x0e, RO, enabled, ready for data transfer, blocksize */
++	uint16	f3_info_reg;		/* 0x10, RO, enabled, ready for data transfer, blocksize */
++	uint32	test_read;		/* 0x14, RO 0xfeedbead signature */
++	uint32	test_rw;		/* 0x18, RW */
++	uint8	resp_delay_f0;		/* 0x1c, read resp delay bytes for F0 (corerev >= 3) */
++	uint8	resp_delay_f1;		/* 0x1d, read resp delay bytes for F1 (corerev >= 3) */
++	uint8	resp_delay_f2;		/* 0x1e, read resp delay bytes for F2 (corerev >= 3) */
++	uint8	resp_delay_f3;		/* 0x1f, read resp delay bytes for F3 (corerev >= 3) */
++} spi_regs_t;
++
++/* SPI device register offsets */
++#define SPID_CONFIG			0x00
++#define SPID_RESPONSE_DELAY		0x01
++#define SPID_STATUS_ENABLE		0x02
++#define SPID_RESET_BP			0x03	/* (corerev >= 1) */
++#define SPID_INTR_REG			0x04	/* 16 bits - Interrupt status */
++#define SPID_INTR_EN_REG		0x06	/* 16 bits - Interrupt mask */
++#define SPID_STATUS_REG			0x08	/* 32 bits */
++#define SPID_F1_INFO_REG		0x0C	/* 16 bits */
++#define SPID_F2_INFO_REG		0x0E	/* 16 bits */
++#define SPID_F3_INFO_REG		0x10	/* 16 bits */
++#define SPID_TEST_READ			0x14	/* 32 bits */
++#define SPID_TEST_RW			0x18	/* 32 bits */
++#define SPID_RESP_DELAY_F0		0x1c	/* 8 bits (corerev >= 3) */
++#define SPID_RESP_DELAY_F1		0x1d	/* 8 bits (corerev >= 3) */
++#define SPID_RESP_DELAY_F2		0x1e	/* 8 bits (corerev >= 3) */
++#define SPID_RESP_DELAY_F3		0x1f	/* 8 bits (corerev >= 3) */
++
++/* Bit masks for SPID_CONFIG device register */
++#define WORD_LENGTH_32	0x1	/* 0/1 16/32 bit word length */
++#define ENDIAN_BIG	0x2	/* 0/1 Little/Big Endian */
++#define CLOCK_PHASE	0x4	/* 0/1 clock phase delay */
++#define CLOCK_POLARITY	0x8	/* 0/1 Idle state clock polarity is low/high */
++#define HIGH_SPEED_MODE	0x10	/* 1/0 High Speed mode / Normal mode */
++#define INTR_POLARITY	0x20	/* 1/0 Interrupt active polarity is high/low */
++#define WAKE_UP		0x80	/* 0/1 Wake-up command from Host to WLAN */
++
++/* Bit mask for SPID_RESPONSE_DELAY device register */
++#define RESPONSE_DELAY_MASK	0xFF	/* Configurable rd response delay in multiples of 8 bits */
++
++/* Bit mask for SPID_STATUS_ENABLE device register */
++#define STATUS_ENABLE		0x1	/* 1/0 Status sent/not sent to host after read/write */
++#define INTR_WITH_STATUS	0x2	/* 0/1 Do-not / do-interrupt if status is sent */
++#define RESP_DELAY_ALL		0x4	/* Applicability of resp delay to F1 or all func's read */
++#define DWORD_PKT_LEN_EN	0x8	/* Packet len denoted in dwords instead of bytes */
++#define CMD_ERR_CHK_EN		0x20	/* Command error check enable */
++#define DATA_ERR_CHK_EN		0x40	/* Data error check enable */
++
++/* Bit mask for SPID_RESET_BP device register */
++#define RESET_ON_WLAN_BP_RESET	0x4	/* enable reset for WLAN backplane */
++#define RESET_ON_BT_BP_RESET	0x8	/* enable reset for BT backplane */
++#define RESET_SPI		0x80	/* reset the above enabled logic */
++
++/* Bit mask for SPID_INTR_REG device register */
++#define DATA_UNAVAILABLE	0x0001	/* Requested data not available; Clear by writing a "1" */
++#define F2_F3_FIFO_RD_UNDERFLOW	0x0002
++#define F2_F3_FIFO_WR_OVERFLOW	0x0004
++#define COMMAND_ERROR		0x0008	/* Cleared by writing 1 */
++#define DATA_ERROR		0x0010	/* Cleared by writing 1 */
++#define F2_PACKET_AVAILABLE	0x0020
++#define F3_PACKET_AVAILABLE	0x0040
++#define F1_OVERFLOW		0x0080	/* Due to last write. Bkplane has pending write requests */
++#define MISC_INTR0		0x0100
++#define MISC_INTR1		0x0200
++#define MISC_INTR2		0x0400
++#define MISC_INTR3		0x0800
++#define MISC_INTR4		0x1000
++#define F1_INTR			0x2000
++#define F2_INTR			0x4000
++#define F3_INTR			0x8000
++
++/* Bit mask for 32bit SPID_STATUS_REG device register */
++#define STATUS_DATA_NOT_AVAILABLE	0x00000001
++#define STATUS_UNDERFLOW		0x00000002
++#define STATUS_OVERFLOW			0x00000004
++#define STATUS_F2_INTR			0x00000008
++#define STATUS_F3_INTR			0x00000010
++#define STATUS_F2_RX_READY		0x00000020
++#define STATUS_F3_RX_READY		0x00000040
++#define STATUS_HOST_CMD_DATA_ERR	0x00000080
++#define STATUS_F2_PKT_AVAILABLE		0x00000100
++#define STATUS_F2_PKT_LEN_MASK		0x000FFE00
++#define STATUS_F2_PKT_LEN_SHIFT		9
++#define STATUS_F3_PKT_AVAILABLE		0x00100000
++#define STATUS_F3_PKT_LEN_MASK		0xFFE00000
++#define STATUS_F3_PKT_LEN_SHIFT		21
++
++/* Bit mask for 16 bits SPID_F1_INFO_REG device register */
++#define F1_ENABLED 			0x0001
++#define F1_RDY_FOR_DATA_TRANSFER	0x0002
++#define F1_MAX_PKT_SIZE			0x01FC
++
++/* Bit mask for 16 bits SPID_F2_INFO_REG device register */
++#define F2_ENABLED 			0x0001
++#define F2_RDY_FOR_DATA_TRANSFER	0x0002
++#define F2_MAX_PKT_SIZE			0x3FFC
++
++/* Bit mask for 16 bits SPID_F3_INFO_REG device register */
++#define F3_ENABLED 			0x0001
++#define F3_RDY_FOR_DATA_TRANSFER	0x0002
++#define F3_MAX_PKT_SIZE			0x3FFC
++
++/* Bit mask for 32 bits SPID_TEST_READ device register read in 16bit LE mode */
++#define TEST_RO_DATA_32BIT_LE		0xFEEDBEAD
++
++/* Maximum number of I/O funcs */
++#define SPI_MAX_IOFUNCS		4
++
++#define SPI_MAX_PKT_LEN		(2048*4)
++
++/* Misc defines */
++#define SPI_FUNC_0		0
++#define SPI_FUNC_1		1
++#define SPI_FUNC_2		2
++#define SPI_FUNC_3		3
++
++#define WAIT_F2RXFIFORDY	100
++#define WAIT_F2RXFIFORDY_DELAY	20
++
++#endif /* _SPI_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/trxhdr.h b/module_drivers/drivers/net/wireless/bcmdhd/include/trxhdr.h
+new file mode 100644
+index 000000000..50cd3c1ac
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/trxhdr.h
+@@ -0,0 +1,95 @@
++/*
++ * TRX image file header format.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: trxhdr.h 520026 2014-12-10 01:29:40Z $
++ */
++
++#ifndef _TRX_HDR_H
++#define _TRX_HDR_H
++
++#include <typedefs.h>
++
++#define TRX_MAGIC	0x30524448	/* "HDR0" */
++#define TRX_MAX_LEN	0x3B0000	/* Max length */
++#define TRX_NO_HEADER	1		/* Do not write TRX header */
++#define TRX_GZ_FILES	0x2     /* Contains up to TRX_MAX_OFFSET individual gzip files */
++#define TRX_EMBED_UCODE	0x8	/* Trx contains embedded ucode image */
++#define TRX_ROMSIM_IMAGE	0x10	/* Trx contains ROM simulation image */
++#define TRX_UNCOMP_IMAGE	0x20	/* Trx contains uncompressed rtecdc.bin image */
++#define TRX_BOOTLOADER		0x40	/* the image is a bootloader */
++
++#define TRX_V1		1
++#define TRX_V1_MAX_OFFSETS	3		/* V1: Max number of individual files */
++
++#ifndef BCMTRXV2
++#define TRX_VERSION	TRX_V1		/* Version 1 */
++#define TRX_MAX_OFFSET TRX_V1_MAX_OFFSETS
++#endif
++
++/* BMAC Host driver/application like bcmdl need to support both Ver 1 as well as
++ * Ver 2 of trx header. To make it generic, trx_header is structure is modified
++ * as below where size of "offsets" field will vary as per the TRX version.
++ * Currently, BMAC host driver and bcmdl are modified to support TRXV2 as well.
++ * To make sure, other applications like "dhdl" which are yet to be enhanced to support
++ * TRXV2 are not broken, new macro and structure defintion take effect only when BCMTRXV2
++ * is defined.
++ */
++struct trx_header {
++	uint32 magic;		/* "HDR0" */
++	uint32 len;		/* Length of file including header */
++	uint32 crc32;		/* 32-bit CRC from flag_version to end of file */
++	uint32 flag_version;	/* 0:15 flags, 16:31 version */
++#ifndef BCMTRXV2
++	uint32 offsets[TRX_MAX_OFFSET];	/* Offsets of partitions from start of header */
++#else
++	uint32 offsets[1];	/* Offsets of partitions from start of header */
++#endif
++};
++
++#ifdef BCMTRXV2
++#define TRX_VERSION		TRX_V2		/* Version 2 */
++#define TRX_MAX_OFFSET  TRX_V2_MAX_OFFSETS
++
++#define TRX_V2		2
++/* V2: Max number of individual files
++ * To support SDR signature + Config data region
++ */
++#define TRX_V2_MAX_OFFSETS	5
++#define SIZEOF_TRXHDR_V1	(sizeof(struct trx_header)+(TRX_V1_MAX_OFFSETS-1)*sizeof(uint32))
++#define SIZEOF_TRXHDR_V2	(sizeof(struct trx_header)+(TRX_V2_MAX_OFFSETS-1)*sizeof(uint32))
++#define TRX_VER(trx)		((trx)->flag_version>>16)
++#define ISTRX_V1(trx)		(TRX_VER(trx) == TRX_V1)
++#define ISTRX_V2(trx)		(TRX_VER(trx) == TRX_V2)
++/* For V2, return size of V2 size: others, return V1 size */
++#define SIZEOF_TRX(trx)	    (ISTRX_V2(trx) ? SIZEOF_TRXHDR_V2: SIZEOF_TRXHDR_V1)
++#else
++#define SIZEOF_TRX(trx)	    (sizeof(struct trx_header))
++#endif /* BCMTRXV2 */
++
++/* Compatibility */
++typedef struct trx_header TRXHDR, *PTRXHDR;
++
++#endif /* _TRX_HDR_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/typedefs.h b/module_drivers/drivers/net/wireless/bcmdhd/include/typedefs.h
+new file mode 100644
+index 000000000..aed3ace91
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/typedefs.h
+@@ -0,0 +1,386 @@
++/*
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: typedefs.h 639587 2016-05-24 06:44:44Z $
++ */
++
++#ifndef _TYPEDEFS_H_
++#define _TYPEDEFS_H_
++
++#if (!defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)) || \
++	!defined(BWL_NO_INTERNAL_STDLIB_SUPPORT)
++
++#ifdef SITE_TYPEDEFS
++
++/*
++ * Define SITE_TYPEDEFS in the compile to include a site-specific
++ * typedef file "site_typedefs.h".
++ *
++ * If SITE_TYPEDEFS is not defined, then the code section below makes
++ * inferences about the compile environment based on defined symbols and
++ * possibly compiler pragmas.
++ *
++ * Following these two sections is the Default Typedefs section.
++ * This section is only processed if USE_TYPEDEF_DEFAULTS is
++ * defined. This section has a default set of typedefs and a few
++ * preprocessor symbols (TRUE, FALSE, NULL, ...).
++ */
++
++#include "site_typedefs.h"
++
++#else
++
++/*
++ * Infer the compile environment based on preprocessor symbols and pragmas.
++ * Override type definitions as needed, and include configuration-dependent
++ * header files to define types.
++ */
++
++#ifdef __cplusplus
++
++#define TYPEDEF_BOOL
++#ifndef FALSE
++#define FALSE	false
++#endif
++#ifndef TRUE
++#define TRUE	true
++#endif
++
++#else	/* ! __cplusplus */
++
++
++#endif	/* ! __cplusplus */
++
++#if defined(__LP64__)
++#define TYPEDEF_UINTPTR
++typedef unsigned long long int uintptr;
++#endif
++
++
++
++
++/* float_t types conflict with the same typedefs from the standard ANSI-C
++** math.h header file. Don't re-typedef them here.
++*/
++
++#if defined(_NEED_SIZE_T_)
++typedef long unsigned int size_t;
++#endif
++
++
++
++
++
++#if defined(__sparc__)
++#define TYPEDEF_ULONG
++#endif
++
++/*
++ * If this is either a Linux hybrid build or the per-port code of a hybrid build
++ * then use the Linux header files to get some of the typedefs.  Otherwise, define
++ * them entirely in this file.  We can't always define the types because we get
++ * a duplicate typedef error; there is no way to "undefine" a typedef.
++ * We know when it's per-port code because each file defines LINUX_PORT at the top.
++ */
++#define TYPEDEF_UINT
++#ifndef TARGETENV_android
++#define TYPEDEF_USHORT
++#define TYPEDEF_ULONG
++#endif /* TARGETENV_android */
++#ifdef __KERNEL__
++#include <linux/version.h>
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19))
++#define TYPEDEF_BOOL
++#endif	/* >= 2.6.19 */
++/* special detection for 2.6.18-128.7.1.0.1.el5 */
++#if (LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 18))
++#include <linux/compiler.h>
++#ifdef noinline_for_stack
++#define TYPEDEF_BOOL
++#endif
++#endif	/* == 2.6.18 */
++#endif	/* __KERNEL__ */
++
++
++/* Do not support the (u)int64 types with strict ansi for GNU C */
++#if defined(__GNUC__) && defined(__STRICT_ANSI__)
++#define TYPEDEF_INT64
++#define TYPEDEF_UINT64
++#endif /* defined(__GNUC__) && defined(__STRICT_ANSI__) */
++
++/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
++ * for signed or unsigned
++ */
++#if defined(__ICL)
++
++#define TYPEDEF_INT64
++
++#if defined(__STDC__)
++#define TYPEDEF_UINT64
++#endif
++
++#endif /* __ICL */
++
++#if !defined(__DJGPP__)
++
++/* pick up ushort & uint from standard types.h */
++#if defined(__KERNEL__)
++
++/* See note above */
++#include <linux/types.h>	/* sys/types.h and linux/types.h are oil and water */
++
++#else
++
++#include <sys/types.h>
++
++#endif /* linux && __KERNEL__ */
++
++#endif 
++
++
++/* use the default typedefs in the next section of this file */
++#define USE_TYPEDEF_DEFAULTS
++
++#endif /* SITE_TYPEDEFS */
++
++
++/*
++ * Default Typedefs
++ */
++
++#ifdef USE_TYPEDEF_DEFAULTS
++#undef USE_TYPEDEF_DEFAULTS
++
++#ifndef TYPEDEF_BOOL
++typedef	/* @abstract@ */ unsigned char	bool;
++#endif /* endif TYPEDEF_BOOL */
++
++/* define uchar, ushort, uint, ulong */
++
++#ifndef TYPEDEF_UCHAR
++typedef unsigned char	uchar;
++#endif
++
++#ifndef TYPEDEF_USHORT
++typedef unsigned short	ushort;
++#endif
++
++#ifndef TYPEDEF_UINT
++typedef unsigned int	uint;
++#endif
++
++#ifndef TYPEDEF_ULONG
++typedef unsigned long	ulong;
++#endif
++
++/* define [u]int8/16/32/64, uintptr */
++
++#ifndef TYPEDEF_UINT8
++typedef unsigned char	uint8;
++#endif
++
++#ifndef TYPEDEF_UINT16
++typedef unsigned short	uint16;
++#endif
++
++#ifndef TYPEDEF_UINT32
++typedef unsigned int	uint32;
++#endif
++
++#ifndef TYPEDEF_UINT64
++typedef unsigned long long uint64;
++#endif
++
++#ifndef TYPEDEF_UINTPTR
++typedef unsigned int	uintptr;
++#endif
++
++#ifndef TYPEDEF_INT8
++typedef signed char	int8;
++#endif
++
++#ifndef TYPEDEF_INT16
++typedef signed short	int16;
++#endif
++
++#ifndef TYPEDEF_INT32
++typedef signed int	int32;
++#endif
++
++#ifndef TYPEDEF_INT64
++typedef signed long long int64;
++#endif
++
++/* define float32/64, float_t */
++
++#ifndef TYPEDEF_FLOAT32
++typedef float		float32;
++#endif
++
++#ifndef TYPEDEF_FLOAT64
++typedef double		float64;
++#endif
++
++/*
++ * abstracted floating point type allows for compile time selection of
++ * single or double precision arithmetic.  Compiling with -DFLOAT32
++ * selects single precision; the default is double precision.
++ */
++
++#ifndef TYPEDEF_FLOAT_T
++
++#if defined(FLOAT32)
++typedef float32 float_t;
++#else /* default to double precision floating point */
++typedef float64 float_t;
++#endif
++
++#endif /* TYPEDEF_FLOAT_T */
++
++/* define macro values */
++
++#ifndef FALSE
++#define FALSE	0
++#endif
++
++#ifndef TRUE
++#define TRUE	1  /* TRUE */
++#endif
++
++#ifndef NULL
++#define	NULL	0
++#endif
++
++#ifndef OFF
++#define	OFF	0
++#endif
++
++#ifndef ON
++#define	ON	1  /* ON = 1 */
++#endif
++
++#define	AUTO	(-1) /* Auto = -1 */
++
++/* define PTRSZ, INLINE */
++
++#ifndef PTRSZ
++#define	PTRSZ	sizeof(char*)
++#endif
++
++
++/* Detect compiler type. */
++#if defined(__GNUC__) || defined(__lint)
++	#define BWL_COMPILER_GNU
++#elif defined(__CC_ARM) && __CC_ARM
++	#define BWL_COMPILER_ARMCC
++#else
++	#error "Unknown compiler!"
++#endif 
++
++
++#ifndef INLINE
++	#if defined(BWL_COMPILER_MICROSOFT)
++		#define INLINE __inline
++	#elif defined(BWL_COMPILER_GNU)
++		#define INLINE __inline__
++	#elif defined(BWL_COMPILER_ARMCC)
++		#define INLINE	__inline
++	#else
++		#define INLINE
++	#endif 
++#endif /* INLINE */
++
++#undef TYPEDEF_BOOL
++#undef TYPEDEF_UCHAR
++#undef TYPEDEF_USHORT
++#undef TYPEDEF_UINT
++#undef TYPEDEF_ULONG
++#undef TYPEDEF_UINT8
++#undef TYPEDEF_UINT16
++#undef TYPEDEF_UINT32
++#undef TYPEDEF_UINT64
++#undef TYPEDEF_UINTPTR
++#undef TYPEDEF_INT8
++#undef TYPEDEF_INT16
++#undef TYPEDEF_INT32
++#undef TYPEDEF_INT64
++#undef TYPEDEF_FLOAT32
++#undef TYPEDEF_FLOAT64
++#undef TYPEDEF_FLOAT_T
++
++#endif /* USE_TYPEDEF_DEFAULTS */
++
++/* Suppress unused parameter warning */
++#define UNUSED_PARAMETER(x) (void)(x)
++
++/* Avoid warning for discarded const or volatile qualifier in special cases (-Wcast-qual) */
++#define DISCARD_QUAL(ptr, type) ((type *)(uintptr)(ptr))
++
++#else
++
++#include <sys/types.h>
++#include <strings.h>
++#include <stdlib.h>
++
++#ifdef stderr
++#undef stderr
++#define stderr stdout
++#endif
++
++typedef UINT32  uint;
++typedef UINT64  ulong;
++typedef UINT16  ushort;
++typedef UINT8   uint8;
++typedef UINT16  uint16;
++typedef UINT32  uint32;
++typedef UINT64  uint64;
++typedef INT8    int8;
++typedef INT16   int16;
++typedef INT32   int32;
++typedef INT64   int64;
++
++typedef BOOLEAN       bool;
++typedef unsigned char uchar;
++typedef UINTN         uintptr;
++
++typedef UINT8   u_char;
++typedef UINT16  u_short;
++typedef UINTN   u_int;
++typedef ULONGN  u_long;
++
++#define UNUSED_PARAMETER(x) (void)(x)
++#define DISCARD_QUAL(ptr, type) ((type *)(uintptr)(ptr))
++#define INLINE
++#define	AUTO	(-1) /* Auto = -1 */
++#define	ON	1  /* ON = 1 */
++#define	OFF	0
++
++#endif /* !EDK_RELEASE_VERSION || (EDK_RELEASE_VERSION < 0x00020000) */
++
++/*
++ * Including the bcmdefs.h here, to make sure everyone including typedefs.h
++ * gets this automatically
++*/
++#include <bcmdefs.h>
++#endif /* _TYPEDEFS_H_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/usbrdl.h b/module_drivers/drivers/net/wireless/bcmdhd/include/usbrdl.h
+new file mode 100644
+index 000000000..be5bd6923
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/usbrdl.h
+@@ -0,0 +1,134 @@
++/*
++ * Broadcom USB remote download definitions
++ *
++ * Copyright (C) 1999-2016, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: usbrdl.h 597933 2015-11-06 18:52:06Z $
++ */
++
++#ifndef _USB_RDL_H
++#define _USB_RDL_H
++
++/* Control messages: bRequest values */
++#define DL_GETSTATE		0	/* returns the rdl_state_t struct */
++#define DL_CHECK_CRC		1	/* currently unused */
++#define DL_GO			2	/* execute downloaded image */
++#define DL_START		3	/* initialize dl state */
++#define DL_REBOOT		4	/* reboot the device in 2 seconds */
++#define DL_GETVER		5	/* returns the bootrom_id_t struct */
++#define DL_GO_PROTECTED		6	/* execute the downloaded code and set reset event
++					 * to occur in 2 seconds.  It is the responsibility
++					 * of the downloaded code to clear this event
++					 */
++#define DL_EXEC			7	/* jump to a supplied address */
++#define DL_RESETCFG		8	/* To support single enum on dongle
++					 * - Not used by bootloader
++					 */
++#define DL_DEFER_RESP_OK	9	/* Potentially defer the response to setup
++					 * if resp unavailable
++					 */
++#define DL_CHGSPD		0x0A
++
++#define	DL_HWCMD_MASK		0xfc	/* Mask for hardware read commands: */
++#define	DL_RDHW			0x10	/* Read a hardware address (Ctl-in) */
++#define	DL_RDHW32		0x10	/* Read a 32 bit word */
++#define	DL_RDHW16		0x11	/* Read 16 bits */
++#define	DL_RDHW8		0x12	/* Read an 8 bit byte */
++#define	DL_WRHW			0x14	/* Write a hardware address (Ctl-out) */
++#define DL_WRHW_BLK		0x13	/* Block write to hardware access */
++
++#define DL_CMD_WRHW		2
++
++
++/* states */
++#define DL_WAITING	0	/* waiting to rx first pkt that includes the hdr info */
++#define DL_READY	1	/* hdr was good, waiting for more of the compressed image */
++#define DL_BAD_HDR	2	/* hdr was corrupted */
++#define DL_BAD_CRC	3	/* compressed image was corrupted */
++#define DL_RUNNABLE	4	/* download was successful, waiting for go cmd */
++#define DL_START_FAIL	5	/* failed to initialize correctly */
++#define DL_NVRAM_TOOBIG	6	/* host specified nvram data exceeds DL_NVRAM value */
++#define DL_IMAGE_TOOBIG	7	/* download image too big (exceeds DATA_START for rdl) */
++
++#define TIMEOUT		5000	/* Timeout for usb commands */
++
++struct bcm_device_id {
++	char	*name;
++	uint32	vend;
++	uint32	prod;
++};
++
++typedef struct {
++	uint32	state;
++	uint32	bytes;
++} rdl_state_t;
++
++typedef struct {
++	uint32	chip;		/* Chip id */
++	uint32	chiprev;	/* Chip rev */
++	uint32  ramsize;    /* Size of RAM */
++	uint32  remapbase;   /* Current remap base address */
++	uint32  boardtype;   /* Type of board */
++	uint32  boardrev;    /* Board revision */
++} bootrom_id_t;
++
++/* struct for backplane & jtag accesses */
++typedef struct {
++	uint32	cmd;		/* tag to identify the cmd */
++	uint32	addr;		/* backplane address for write */
++	uint32	len;		/* length of data: 1, 2, 4 bytes */
++	uint32	data;		/* data to write */
++} hwacc_t;
++
++
++/* struct for querying nvram params from bootloader */
++#define QUERY_STRING_MAX 32
++typedef struct {
++	uint32  cmd;                    /* tag to identify the cmd */
++	char    var[QUERY_STRING_MAX];  /* param name */
++} nvparam_t;
++
++typedef void (*exec_fn_t)(void *sih);
++
++#define USB_CTRL_IN (USB_TYPE_VENDOR | 0x80 | USB_RECIP_INTERFACE)
++#define USB_CTRL_OUT (USB_TYPE_VENDOR | 0 | USB_RECIP_INTERFACE)
++
++#define USB_CTRL_EP_TIMEOUT 500 /* Timeout used in USB control_msg transactions. */
++#define USB_BULK_EP_TIMEOUT 500 /* Timeout used in USB bulk transactions. */
++
++#define RDL_CHUNK_MAX	(64 * 1024)  /* max size of each dl transfer */
++#define RDL_CHUNK	1500  /* size of each dl transfer */
++
++/* bootloader makes special use of trx header "offsets" array */
++#define TRX_OFFSETS_DLFWLEN_IDX	0	/* Size of the fw; used in uncompressed case */
++#define TRX_OFFSETS_JUMPTO_IDX	1	/* RAM address for jumpto after download */
++#define TRX_OFFSETS_NVM_LEN_IDX	2	/* Length of appended NVRAM data */
++#ifdef BCMTRXV2
++#define TRX_OFFSETS_DSG_LEN_IDX	3	/* Length of digital signature for the first image */
++#define TRX_OFFSETS_CFG_LEN_IDX	4	/* Length of config region, which is not digitally signed */
++#endif /* BCMTRXV2 */
++
++#define TRX_OFFSETS_DLBASE_IDX  0       /* RAM start address for download */
++
++#endif  /* _USB_RDL_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/vlan.h b/module_drivers/drivers/net/wireless/bcmdhd/include/vlan.h
+new file mode 100644
+index 000000000..4879eae58
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/vlan.h
+@@ -0,0 +1,98 @@
++/*
++ * 802.1Q VLAN protocol definitions
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: vlan.h 700076 2017-05-17 14:42:22Z $
++ */
++
++#ifndef _vlan_h_
++#define _vlan_h_
++
++#ifndef _TYPEDEFS_H_
++#include <typedefs.h>
++#endif
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++
++#ifndef	 VLAN_VID_MASK
++#define VLAN_VID_MASK		0xfff	/* low 12 bits are vlan id */
++#endif
++
++#define	VLAN_CFI_SHIFT		12	/* canonical format indicator bit */
++#define VLAN_PRI_SHIFT		13	/* user priority */
++
++#define VLAN_PRI_MASK		7	/* 3 bits of priority */
++
++#define	VLAN_TPID_OFFSET	12	/* offset of tag protocol id field */
++#define	VLAN_TCI_OFFSET		14	/* offset of tag ctrl info field */
++
++#define	VLAN_TAG_LEN		4
++#define	VLAN_TAG_OFFSET		(2 * ETHER_ADDR_LEN)	/* offset in Ethernet II packet only */
++
++#define VLAN_TPID		0x8100	/* VLAN ethertype/Tag Protocol ID */
++
++struct vlan_header {
++	uint16	vlan_type;		/* 0x8100 */
++	uint16	vlan_tag;		/* priority, cfi and vid */
++};
++
++struct ethervlan_header {
++	uint8	ether_dhost[ETHER_ADDR_LEN];
++	uint8	ether_shost[ETHER_ADDR_LEN];
++	uint16	vlan_type;		/* 0x8100 */
++	uint16	vlan_tag;		/* priority, cfi and vid */
++	uint16	ether_type;
++};
++
++struct dot3_mac_llc_snapvlan_header {
++	uint8	ether_dhost[ETHER_ADDR_LEN];	/* dest mac */
++	uint8	ether_shost[ETHER_ADDR_LEN];	/* src mac */
++	uint16	length;				/* frame length incl header */
++	uint8	dsap;				/* always 0xAA */
++	uint8	ssap;				/* always 0xAA */
++	uint8	ctl;				/* always 0x03 */
++	uint8	oui[3];				/* RFC1042: 0x00 0x00 0x00
++						 * Bridge-Tunnel: 0x00 0x00 0xF8
++						 */
++	uint16	vlan_type;			/* 0x8100 */
++	uint16	vlan_tag;			/* priority, cfi and vid */
++	uint16	ether_type;			/* ethertype */
++};
++
++#define	ETHERVLAN_HDR_LEN	(ETHER_HDR_LEN + VLAN_TAG_LEN)
++
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++#define ETHERVLAN_MOVE_HDR(d, s) \
++do { \
++	struct ethervlan_header t; \
++	t = *(struct ethervlan_header *)(s); \
++	*(struct ethervlan_header *)(d) = t; \
++} while (0)
++
++#endif /* _vlan_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/wlfc_proto.h b/module_drivers/drivers/net/wireless/bcmdhd/include/wlfc_proto.h
+new file mode 100644
+index 000000000..121af90b6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/wlfc_proto.h
+@@ -0,0 +1,376 @@
++/*
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wlfc_proto.h 675983 2016-12-19 23:18:49Z $
++ *
++ */
++
++/** WL flow control for PROP_TXSTATUS. Related to host AMPDU reordering. */
++
++
++#ifndef __wlfc_proto_definitions_h__
++#define __wlfc_proto_definitions_h__
++
++	/* Use TLV to convey WLFC information.
++	 ---------------------------------------------------------------------------
++	| Type |  Len | value                    | Description
++	 ---------------------------------------------------------------------------
++	|  1   |   1  | (handle)                 | MAC OPEN
++	 ---------------------------------------------------------------------------
++	|  2   |   1  | (handle)                 | MAC CLOSE
++	 ---------------------------------------------------------------------------
++	|  3   |   2  | (count, handle, prec_bmp)| Set the credit depth for a MAC dstn
++	 ---------------------------------------------------------------------------
++	|  4   |   4+ | see pkttag comments      | TXSTATUS
++	|      |   12 | TX status & timestamps   | Present only when pkt timestamp is enabled
++	 ---------------------------------------------------------------------------
++	|  5   |   4  | see pkttag comments      | PKKTTAG [host->firmware]
++	 ---------------------------------------------------------------------------
++	|  6   |   8  | (handle, ifid, MAC)      | MAC ADD
++	 ---------------------------------------------------------------------------
++	|  7   |   8  | (handle, ifid, MAC)      | MAC DEL
++	 ---------------------------------------------------------------------------
++	|  8   |   1  | (rssi)                   | RSSI - RSSI value for the packet.
++	 ---------------------------------------------------------------------------
++	|  9   |   1  | (interface ID)           | Interface OPEN
++	 ---------------------------------------------------------------------------
++	|  10  |   1  | (interface ID)           | Interface CLOSE
++	 ---------------------------------------------------------------------------
++	|  11  |   8  | fifo credit returns map  | FIFO credits back to the host
++	|      |      |                          |
++	|      |      |                          | --------------------------------------
++	|      |      |                          | | ac0 | ac1 | ac2 | ac3 | bcmc | atim |
++	|      |      |                          | --------------------------------------
++	|      |      |                          |
++	 ---------------------------------------------------------------------------
++	|  12  |   2  | MAC handle,              | Host provides a bitmap of pending
++	|      |      | AC[0-3] traffic bitmap   | unicast traffic for MAC-handle dstn.
++	|      |      |                          | [host->firmware]
++	 ---------------------------------------------------------------------------
++	|  13  |   3  | (count, handle, prec_bmp)| One time request for packet to a specific
++	|      |      |                          | MAC destination.
++	 ---------------------------------------------------------------------------
++	|  15  |  12  | (pkttag, timestamps)     | Send TX timestamp at reception from host
++	 ---------------------------------------------------------------------------
++	|  16  |  12  | (pkttag, timestamps)     | Send WLAN RX timestamp along with RX frame
++	 ---------------------------------------------------------------------------
++	| 255  |  N/A |  N/A                     | FILLER - This is a special type
++	|      |      |                          | that has no length or value.
++	|      |      |                          | Typically used for padding.
++	 ---------------------------------------------------------------------------
++	*/
++
++#define WLFC_CTL_TYPE_MAC_OPEN			1
++#define WLFC_CTL_TYPE_MAC_CLOSE			2
++#define WLFC_CTL_TYPE_MAC_REQUEST_CREDIT	3
++#define WLFC_CTL_TYPE_TXSTATUS			4
++#define WLFC_CTL_TYPE_PKTTAG			5	/** host<->dongle */
++
++#define WLFC_CTL_TYPE_MACDESC_ADD		6
++#define WLFC_CTL_TYPE_MACDESC_DEL		7
++#define WLFC_CTL_TYPE_RSSI			8
++
++#define WLFC_CTL_TYPE_INTERFACE_OPEN		9
++#define WLFC_CTL_TYPE_INTERFACE_CLOSE		10
++
++#define WLFC_CTL_TYPE_FIFO_CREDITBACK		11
++
++#define WLFC_CTL_TYPE_PENDING_TRAFFIC_BMP	12	/** host->dongle */
++#define WLFC_CTL_TYPE_MAC_REQUEST_PACKET	13
++#define WLFC_CTL_TYPE_HOST_REORDER_RXPKTS	14
++
++#define WLFC_CTL_TYPE_TX_ENTRY_STAMP		15
++#define WLFC_CTL_TYPE_RX_STAMP			16
++#define WLFC_CTL_TYPE_TX_STATUS_STAMP		17	/** obsolete */
++
++#define WLFC_CTL_TYPE_TRANS_ID			18
++#define WLFC_CTL_TYPE_COMP_TXSTATUS		19
++
++#define WLFC_CTL_TYPE_TID_OPEN			20
++#define WLFC_CTL_TYPE_TID_CLOSE			21
++
++
++#define WLFC_CTL_TYPE_FILLER			255
++
++#define WLFC_CTL_VALUE_LEN_MACDESC		8	/** handle, interface, MAC */
++
++#define WLFC_CTL_VALUE_LEN_MAC			1	/** MAC-handle */
++#define WLFC_CTL_VALUE_LEN_RSSI			1
++
++#define WLFC_CTL_VALUE_LEN_INTERFACE		1
++#define WLFC_CTL_VALUE_LEN_PENDING_TRAFFIC_BMP	2
++
++#define WLFC_CTL_VALUE_LEN_TXSTATUS		4
++#define WLFC_CTL_VALUE_LEN_PKTTAG		4
++#define WLFC_CTL_VALUE_LEN_TIMESTAMP		12	/** 4-byte rate info + 2 TSF */
++
++#define WLFC_CTL_VALUE_LEN_SEQ			2
++
++/* The high bits of ratespec report in timestamp are used for various status */
++#define WLFC_TSFLAGS_RX_RETRY		(1 << 31)
++#define WLFC_TSFLAGS_PM_ENABLED		(1 << 30)
++#define WLFC_TSFLAGS_MASK		(WLFC_TSFLAGS_RX_RETRY | WLFC_TSFLAGS_PM_ENABLED)
++
++/* enough space to host all 4 ACs, bc/mc and atim fifo credit */
++#define WLFC_CTL_VALUE_LEN_FIFO_CREDITBACK	6
++
++#define WLFC_CTL_VALUE_LEN_REQUEST_CREDIT	3	/* credit, MAC-handle, prec_bitmap */
++#define WLFC_CTL_VALUE_LEN_REQUEST_PACKET	3	/* credit, MAC-handle, prec_bitmap */
++
++
++#define WLFC_PKTFLAG_PKTFROMHOST	0x01
++#define WLFC_PKTFLAG_PKT_REQUESTED	0x02
++
++#define WL_TXSTATUS_STATUS_MASK			0xff /* allow 8 bits */
++#define WL_TXSTATUS_STATUS_SHIFT		24
++
++#define WL_TXSTATUS_SET_STATUS(x, status)	((x)  = \
++	((x) & ~(WL_TXSTATUS_STATUS_MASK << WL_TXSTATUS_STATUS_SHIFT)) | \
++	(((status) & WL_TXSTATUS_STATUS_MASK) << WL_TXSTATUS_STATUS_SHIFT))
++#define WL_TXSTATUS_GET_STATUS(x)	(((x) >> WL_TXSTATUS_STATUS_SHIFT) & \
++	WL_TXSTATUS_STATUS_MASK)
++
++/**
++ * Bit 31 of the 32-bit packet tag is defined as 'generation ID'. It is set by the host to the
++ * "current" generation, and by the firmware to the "expected" generation, toggling on suppress. The
++ * firmware accepts a packet when the generation matches; on reset (startup) both "current" and
++ * "expected" are set to 0.
++ */
++#define WL_TXSTATUS_GENERATION_MASK		1 /* allow 1 bit */
++#define WL_TXSTATUS_GENERATION_SHIFT		31
++
++#define WL_TXSTATUS_SET_GENERATION(x, gen)	((x) = \
++	((x) & ~(WL_TXSTATUS_GENERATION_MASK << WL_TXSTATUS_GENERATION_SHIFT)) | \
++	(((gen) & WL_TXSTATUS_GENERATION_MASK) << WL_TXSTATUS_GENERATION_SHIFT))
++
++#define WL_TXSTATUS_GET_GENERATION(x)	(((x) >> WL_TXSTATUS_GENERATION_SHIFT) & \
++	WL_TXSTATUS_GENERATION_MASK)
++
++#define WL_TXSTATUS_FLAGS_MASK			0xf /* allow 4 bits only */
++#define WL_TXSTATUS_FLAGS_SHIFT			27
++
++#define WL_TXSTATUS_SET_FLAGS(x, flags)	((x)  = \
++	((x) & ~(WL_TXSTATUS_FLAGS_MASK << WL_TXSTATUS_FLAGS_SHIFT)) | \
++	(((flags) & WL_TXSTATUS_FLAGS_MASK) << WL_TXSTATUS_FLAGS_SHIFT))
++#define WL_TXSTATUS_GET_FLAGS(x)		(((x) >> WL_TXSTATUS_FLAGS_SHIFT) & \
++	WL_TXSTATUS_FLAGS_MASK)
++
++#define WL_TXSTATUS_FIFO_MASK			0x7 /* allow 3 bits for FIFO ID */
++#define WL_TXSTATUS_FIFO_SHIFT			24
++
++#define WL_TXSTATUS_SET_FIFO(x, flags)	((x)  = \
++	((x) & ~(WL_TXSTATUS_FIFO_MASK << WL_TXSTATUS_FIFO_SHIFT)) | \
++	(((flags) & WL_TXSTATUS_FIFO_MASK) << WL_TXSTATUS_FIFO_SHIFT))
++#define WL_TXSTATUS_GET_FIFO(x)		(((x) >> WL_TXSTATUS_FIFO_SHIFT) & WL_TXSTATUS_FIFO_MASK)
++
++#define WL_TXSTATUS_PKTID_MASK			0xffffff /* allow 24 bits */
++#define WL_TXSTATUS_SET_PKTID(x, num)	((x) = \
++	((x) & ~WL_TXSTATUS_PKTID_MASK) | (num))
++#define WL_TXSTATUS_GET_PKTID(x)		((x) & WL_TXSTATUS_PKTID_MASK)
++
++#define WL_TXSTATUS_HSLOT_MASK			0xffff /* allow 16 bits */
++#define WL_TXSTATUS_HSLOT_SHIFT			8
++
++#define WL_TXSTATUS_SET_HSLOT(x, hslot)	((x)  = \
++	((x) & ~(WL_TXSTATUS_HSLOT_MASK << WL_TXSTATUS_HSLOT_SHIFT)) | \
++	(((hslot) & WL_TXSTATUS_HSLOT_MASK) << WL_TXSTATUS_HSLOT_SHIFT))
++#define WL_TXSTATUS_GET_HSLOT(x)	(((x) >> WL_TXSTATUS_HSLOT_SHIFT)& \
++	WL_TXSTATUS_HSLOT_MASK)
++
++#define WL_TXSTATUS_FREERUNCTR_MASK		0xff /* allow 8 bits */
++
++#define WL_TXSTATUS_SET_FREERUNCTR(x, ctr)	((x)  = \
++	((x) & ~(WL_TXSTATUS_FREERUNCTR_MASK)) | \
++	((ctr) & WL_TXSTATUS_FREERUNCTR_MASK))
++#define WL_TXSTATUS_GET_FREERUNCTR(x)		((x)& WL_TXSTATUS_FREERUNCTR_MASK)
++
++/* AMSDU part of d11 seq number */
++#define WL_SEQ_AMSDU_MASK             0x1 /* allow 1 bit */
++#define WL_SEQ_AMSDU_SHIFT            14
++#define WL_SEQ_SET_AMSDU(x, val)      ((x) = \
++	((x) & ~(WL_SEQ_AMSDU_MASK << WL_SEQ_AMSDU_SHIFT)) | \
++	(((val) & WL_SEQ_AMSDU_MASK) << WL_SEQ_AMSDU_SHIFT)) /**< sets a single AMSDU bit */
++/** returns TRUE if ring item is AMSDU (seq = d11 seq nr) */
++#define WL_SEQ_IS_AMSDU(x)   (((x) >> WL_SEQ_AMSDU_SHIFT) & \
++	WL_SEQ_AMSDU_MASK)
++
++#define WL_SEQ_FROMFW_MASK		0x1 /* allow 1 bit */
++#define WL_SEQ_FROMFW_SHIFT		13
++#define WL_SEQ_SET_FROMFW(x, val)	((x) = \
++	((x) & ~(WL_SEQ_FROMFW_MASK << WL_SEQ_FROMFW_SHIFT)) | \
++	(((val) & WL_SEQ_FROMFW_MASK) << WL_SEQ_FROMFW_SHIFT))
++/** Set when firmware assigns D11 sequence number to packet */
++#define SET_WL_HAS_ASSIGNED_SEQ(x)	WL_SEQ_SET_FROMFW((x), 1)
++
++/** returns TRUE if packet has been assigned a d11 seq number by the WL firmware layer */
++#define GET_WL_HAS_ASSIGNED_SEQ(x)	(((x) >> WL_SEQ_FROMFW_SHIFT) & WL_SEQ_FROMFW_MASK)
++
++/**
++ * Proptxstatus related.
++ *
++ * When a packet is suppressed by WL or the D11 core, the packet has to be retried. Assigning
++ * a new d11 sequence number for the packet when retrying would cause the peer to be unable to
++ * reorder the packets within an AMPDU. So, suppressed packet from bus layer (DHD for SDIO and
++ * pciedev for PCIE) is re-using d11 seq number, so FW should not assign a new one.
++ */
++#define WL_SEQ_FROMDRV_MASK		0x1 /* allow 1 bit */
++#define WL_SEQ_FROMDRV_SHIFT		12
++
++/**
++ * Proptxstatus, host or fw PCIe layer requests WL layer to reuse d11 seq no. Bit is reset by WL
++ * subsystem when it reuses the seq number.
++ */
++#define WL_SEQ_SET_REUSE(x, val)	((x) = \
++	((x) & ~(WL_SEQ_FROMDRV_MASK << WL_SEQ_FROMDRV_SHIFT)) | \
++	(((val) & WL_SEQ_FROMDRV_MASK) << WL_SEQ_FROMDRV_SHIFT))
++#define SET_WL_TO_REUSE_SEQ(x)   WL_SEQ_SET_REUSE((x), 1)
++#define RESET_WL_TO_REUSE_SEQ(x) WL_SEQ_SET_REUSE((x), 0)
++
++/** Proptxstatus, related to reuse of d11 seq numbers when retransmitting */
++#define IS_WL_TO_REUSE_SEQ(x)	(((x) >> WL_SEQ_FROMDRV_SHIFT) & \
++	WL_SEQ_FROMDRV_MASK)
++
++#define WL_SEQ_NUM_MASK			0xfff /* allow 12 bit */
++#define WL_SEQ_NUM_SHIFT		0
++/** Proptxstatus, sets d11seq no in pkt tag, related to reuse of d11seq no when retransmitting */
++#define WL_SEQ_SET_NUM(x, val)	((x) = \
++	((x) & ~(WL_SEQ_NUM_MASK << WL_SEQ_NUM_SHIFT)) | \
++	(((val) & WL_SEQ_NUM_MASK) << WL_SEQ_NUM_SHIFT))
++/** Proptxstatus, gets d11seq no from pkt tag, related to reuse of d11seq no when retransmitting */
++#define WL_SEQ_GET_NUM(x)	(((x) >> WL_SEQ_NUM_SHIFT) & \
++	WL_SEQ_NUM_MASK)
++
++#define WL_SEQ_AMSDU_SUPPR_MASK	((WL_SEQ_FROMDRV_MASK << WL_SEQ_FROMDRV_SHIFT) | \
++				(WL_SEQ_AMSDU_MASK << WL_SEQ_AMSDU_SHIFT) | \
++				(WL_SEQ_NUM_MASK << WL_SEQ_NUM_SHIFT))
++
++/* 32 STA should be enough??, 6 bits; Must be power of 2 */
++#define WLFC_MAC_DESC_TABLE_SIZE	32
++#define WLFC_MAX_IFNUM				16
++#define WLFC_MAC_DESC_ID_INVALID	0xff
++
++/* b[7:5] -reuse guard, b[4:0] -value */
++#define WLFC_MAC_DESC_GET_LOOKUP_INDEX(x) ((x) & 0x1f)
++
++#define WLFC_PKTFLAG_SET_PKTREQUESTED(x)	(x) |= \
++	(WLFC_PKTFLAG_PKT_REQUESTED << WL_TXSTATUS_FLAGS_SHIFT)
++
++#define WLFC_PKTFLAG_CLR_PKTREQUESTED(x)	(x) &= \
++	~(WLFC_PKTFLAG_PKT_REQUESTED << WL_TXSTATUS_FLAGS_SHIFT)
++
++
++#define WLFC_MAX_PENDING_DATALEN	120
++
++/* host is free to discard the packet */
++#define WLFC_CTL_PKTFLAG_DISCARD	0
++/* D11 suppressed a packet */
++#define WLFC_CTL_PKTFLAG_D11SUPPRESS	1
++/* WL firmware suppressed a packet because MAC is
++	already in PSMode (short time window)
++*/
++#define WLFC_CTL_PKTFLAG_WLSUPPRESS	2
++/* Firmware tossed this packet */
++#define WLFC_CTL_PKTFLAG_TOSSED_BYWLC	3
++/* Firmware tossed after retries */
++#define WLFC_CTL_PKTFLAG_DISCARD_NOACK	4
++/* Firmware wrongly reported suppressed previously,now fixing to acked */
++#define WLFC_CTL_PKTFLAG_SUPPRESS_ACKED	5
++#define WLFC_CTL_PKTFLAG_MASK		(0x0f)	/* For 4-bit mask with one extra bit */
++
++#ifdef PROP_TXSTATUS_DEBUG
++#define WLFC_DBGMESG(x) printf x
++/* wlfc-breadcrumb */
++#define WLFC_BREADCRUMB(x) do {if ((x) == NULL) \
++	{printf("WLFC: %s():%d:caller:%p\n", \
++	__FUNCTION__, __LINE__, CALL_SITE);}} while (0)
++#define WLFC_PRINTMAC(banner, ea) do {printf("%s MAC: [%02x:%02x:%02x:%02x:%02x:%02x]\n", \
++	banner, ea[0], 	ea[1], 	ea[2], 	ea[3], 	ea[4], 	ea[5]); } while (0)
++#define WLFC_WHEREIS(s) printf("WLFC: at %s():%d, %s\n", __FUNCTION__, __LINE__, (s))
++#else
++#define WLFC_DBGMESG(x)
++#define WLFC_BREADCRUMB(x)
++#define WLFC_PRINTMAC(banner, ea)
++#define WLFC_WHEREIS(s)
++#endif
++
++/* AMPDU host reorder packet flags */
++#define WLHOST_REORDERDATA_MAXFLOWS		256
++#define WLHOST_REORDERDATA_LEN		 10
++#define WLHOST_REORDERDATA_TOTLEN	(WLHOST_REORDERDATA_LEN + 1 + 1) /* +tag +len */
++
++#define WLHOST_REORDERDATA_FLOWID_OFFSET		0
++#define WLHOST_REORDERDATA_MAXIDX_OFFSET		2
++#define WLHOST_REORDERDATA_FLAGS_OFFSET			4
++#define WLHOST_REORDERDATA_CURIDX_OFFSET		6
++#define WLHOST_REORDERDATA_EXPIDX_OFFSET		8
++
++#define WLHOST_REORDERDATA_DEL_FLOW		0x01
++#define WLHOST_REORDERDATA_FLUSH_ALL		0x02
++#define WLHOST_REORDERDATA_CURIDX_VALID		0x04
++#define WLHOST_REORDERDATA_EXPIDX_VALID		0x08
++#define WLHOST_REORDERDATA_NEW_HOLE		0x10
++
++/* transaction id data len byte 0: rsvd, byte 1: seqnumber, byte 2-5 will be used for timestampe */
++#define WLFC_CTL_TRANS_ID_LEN			6
++#define WLFC_TYPE_TRANS_ID_LEN			6
++
++#define WLFC_MODE_HANGER	1 /* use hanger */
++#define WLFC_MODE_AFQ		2 /* use afq (At Firmware Queue) */
++#define WLFC_IS_OLD_DEF(x) ((x & 1) || (x & 2))
++
++#define WLFC_MODE_AFQ_SHIFT		2	/* afq bit */
++#define WLFC_SET_AFQ(x, val)	((x) = \
++	((x) & ~(1 << WLFC_MODE_AFQ_SHIFT)) | \
++	(((val) & 1) << WLFC_MODE_AFQ_SHIFT))
++/** returns TRUE if firmware supports 'at firmware queue' feature */
++#define WLFC_GET_AFQ(x)	(((x) >> WLFC_MODE_AFQ_SHIFT) & 1)
++
++#define WLFC_MODE_REUSESEQ_SHIFT	3	/* seq reuse bit */
++#define WLFC_SET_REUSESEQ(x, val)	((x) = \
++	((x) & ~(1 << WLFC_MODE_REUSESEQ_SHIFT)) | \
++	(((val) & 1) << WLFC_MODE_REUSESEQ_SHIFT))
++/** returns TRUE if 'd11 sequence reuse' has been agreed upon between host and dongle */
++#define WLFC_GET_REUSESEQ(x)	(((x) >> WLFC_MODE_REUSESEQ_SHIFT) & 1)
++
++#define WLFC_MODE_REORDERSUPP_SHIFT	4	/* host reorder suppress pkt bit */
++#define WLFC_SET_REORDERSUPP(x, val)	((x) = \
++	((x) & ~(1 << WLFC_MODE_REORDERSUPP_SHIFT)) | \
++	(((val) & 1) << WLFC_MODE_REORDERSUPP_SHIFT))
++/** returns TRUE if 'reorder suppress' has been agreed upon between host and dongle */
++#define WLFC_GET_REORDERSUPP(x)	(((x) >> WLFC_MODE_REORDERSUPP_SHIFT) & 1)
++
++#define FLOW_RING_CREATE	1
++#define FLOW_RING_DELETE	2
++#define FLOW_RING_FLUSH		3
++#define FLOW_RING_OPEN		4
++#define FLOW_RING_CLOSED	5
++#define FLOW_RING_FLUSHED	6
++#define FLOW_RING_TIM_SET	7
++#define FLOW_RING_TIM_RESET	8
++#define FLOW_RING_FLUSH_TXFIFO	9
++
++/* bit 7, indicating if is TID(1) or AC(0) mapped info in tid field) */
++#define PCIEDEV_IS_AC_TID_MAP_MASK	0x80
++
++#endif /* __wlfc_proto_definitions_h__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/wlioctl.h b/module_drivers/drivers/net/wireless/bcmdhd/include/wlioctl.h
+new file mode 100644
+index 000000000..444cb0021
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/wlioctl.h
+@@ -0,0 +1,13828 @@
++/*
++ * Custom OID/ioctl definitions for
++ *
++ *
++ * Broadcom 802.11abg Networking Device Driver
++ *
++ * Definitions subject to change without notice.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wlioctl.h 677952 2017-01-05 23:25:28Z $
++ */
++
++#ifndef _wlioctl_h_
++#define	_wlioctl_h_
++
++#include <typedefs.h>
++#include <ethernet.h>
++#include <bcmip.h>
++#include <bcmeth.h>
++#include <bcmip.h>
++#include <bcmipv6.h>
++#include <bcmevent.h>
++#include <802.11.h>
++#include <802.11s.h>
++#include <802.1d.h>
++#include <bcmwifi_channels.h>
++#include <bcmwifi_rates.h>
++#include <wlioctl_defs.h>
++#include <bcmipv6.h>
++
++#include <bcm_mpool_pub.h>
++#include <bcmcdc.h>
++
++
++typedef struct {
++	uint32 num;
++	chanspec_t list[1];
++} chanspec_list_t;
++
++#define RSN_KCK_LENGTH	16
++#define RSN_KEK_LENGTH	16
++#define TPK_FTM_LEN		16
++#ifndef INTF_NAME_SIZ
++#define INTF_NAME_SIZ	16
++#endif
++
++/**Used to send ioctls over the transport pipe */
++typedef struct remote_ioctl {
++	cdc_ioctl_t	msg;
++	uint32		data_len;
++	char           intf_name[INTF_NAME_SIZ];
++} rem_ioctl_t;
++#define REMOTE_SIZE	sizeof(rem_ioctl_t)
++
++#define BCM_IOV_XTLV_VERSION 0
++
++#define MAX_NUM_D11CORES 2
++
++/**DFS Forced param */
++typedef struct wl_dfs_forced_params {
++	chanspec_t chspec;
++	uint16 version;
++	chanspec_list_t chspec_list;
++} wl_dfs_forced_t;
++
++#define DFS_PREFCHANLIST_VER 0x01
++#define WL_CHSPEC_LIST_FIXED_SIZE	OFFSETOF(chanspec_list_t, list)
++/* size of dfs forced param size given n channels are in the list */
++#define WL_DFS_FORCED_PARAMS_SIZE(n) \
++	(sizeof(wl_dfs_forced_t) + (((n) < 1) ? (0) : (((n) - 1)* sizeof(chanspec_t))))
++#define WL_DFS_FORCED_PARAMS_FIXED_SIZE \
++	(WL_CHSPEC_LIST_FIXED_SIZE + OFFSETOF(wl_dfs_forced_t, chspec_list))
++#define WL_DFS_FORCED_PARAMS_MAX_SIZE \
++	WL_DFS_FORCED_PARAMS_FIXED_SIZE + (WL_NUMCHANNELS * sizeof(chanspec_t))
++
++/**association decision information */
++typedef struct {
++	uint8		assoc_approved;		/**< (re)association approved */
++	uint8		pad;
++	uint16		reject_reason;		/**< reason code for rejecting association */
++	struct		ether_addr   da;
++	uint8		pad1[6];
++	int64		sys_time;		/**< current system time */
++} assoc_decision_t;
++
++#define DFS_SCAN_S_IDLE		-1
++#define DFS_SCAN_S_RADAR_FREE 0
++#define DFS_SCAN_S_RADAR_FOUND 1
++#define DFS_SCAN_S_INPROGESS 2
++#define DFS_SCAN_S_SCAN_ABORTED 3
++#define DFS_SCAN_S_SCAN_MODESW_INPROGRESS 4
++#define DFS_SCAN_S_MAX 5
++
++
++#define ACTION_FRAME_SIZE 1800
++
++typedef struct wl_action_frame {
++	struct ether_addr 	da;
++	uint16 			len;
++	uint32 			packetId;
++	uint8			data[ACTION_FRAME_SIZE];
++} wl_action_frame_t;
++
++#define WL_WIFI_ACTION_FRAME_SIZE sizeof(struct wl_action_frame)
++
++typedef struct ssid_info
++{
++	uint8		ssid_len;	/**< the length of SSID */
++	uint8		ssid[32];	/**< SSID string */
++} ssid_info_t;
++
++typedef struct wl_af_params {
++	uint32			channel;
++	int32			dwell_time;
++	struct ether_addr	BSSID;
++	uint8 PAD[2];
++	wl_action_frame_t	action_frame;
++} wl_af_params_t;
++
++#define WL_WIFI_AF_PARAMS_SIZE sizeof(struct wl_af_params)
++
++#define MFP_TEST_FLAG_NORMAL	0
++#define MFP_TEST_FLAG_ANY_KEY	1
++typedef struct wl_sa_query {
++	uint32 flag;
++	uint8  action;
++	uint8  PAD;
++	uint16 id;
++	struct ether_addr da;
++	uint16  PAD;
++} wl_sa_query_t;
++
++/* EXT_STA */
++/**association information */
++typedef struct {
++	uint32		assoc_req;	/**< offset to association request frame */
++	uint32		assoc_req_len;	/**< association request frame length */
++	uint32		assoc_rsp;	/**< offset to association response frame */
++	uint32		assoc_rsp_len;	/**< association response frame length */
++	uint32		bcn;		/**< offset to AP beacon */
++	uint32		bcn_len;	/**< AP beacon length */
++	uint32		wsec;		/**< ucast security algo */
++	uint32		wpaie;		/**< offset to WPA ie */
++	uint8		auth_alg;	/**< 802.11 authentication mode */
++	uint8		WPA_auth;	/**< WPA: authenticated key management */
++	uint8		ewc_cap;	/**< EWC (MIMO) capable */
++	uint8		ofdm;		/**< OFDM */
++} assoc_info_t;
++/* defined(EXT_STA) */
++
++/* Flags for OBSS IOVAR Parameters */
++#define WL_OBSS_DYN_BWSW_FLAG_ACTIVITY_PERIOD        (0x01)
++#define WL_OBSS_DYN_BWSW_FLAG_NOACTIVITY_PERIOD      (0x02)
++#define WL_OBSS_DYN_BWSW_FLAG_NOACTIVITY_INCR_PERIOD (0x04)
++#define WL_OBSS_DYN_BWSW_FLAG_PSEUDO_SENSE_PERIOD    (0x08)
++#define WL_OBSS_DYN_BWSW_FLAG_RX_CRS_PERIOD          (0x10)
++#define WL_OBSS_DYN_BWSW_FLAG_DUR_THRESHOLD          (0x20)
++#define WL_OBSS_DYN_BWSW_FLAG_TXOP_PERIOD            (0x40)
++
++/* OBSS IOVAR Version information */
++#define WL_PROT_OBSS_CONFIG_PARAMS_VERSION 1
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint8 obss_bwsw_activity_cfm_count_cfg; /**< configurable count in
++		* seconds before we confirm that OBSS is present and
++		* dynamically activate dynamic bwswitch.
++		*/
++	uint8 obss_bwsw_no_activity_cfm_count_cfg; /**< configurable count in
++		* seconds before we confirm that OBSS is GONE and
++		* dynamically start pseudo upgrade. If in pseudo sense time, we
++		* will see OBSS, [means that, we false detected that OBSS-is-gone
++		* in watchdog] this count will be incremented in steps of
++		* obss_bwsw_no_activity_cfm_count_incr_cfg for confirming OBSS
++		* detection again. Note that, at present, max 30seconds is
++		* allowed like this. [OBSS_BWSW_NO_ACTIVITY_MAX_INCR_DEFAULT]
++		*/
++	uint8 obss_bwsw_no_activity_cfm_count_incr_cfg; /* see above
++		*/
++	uint16 obss_bwsw_pseudo_sense_count_cfg; /**< number of msecs/cnt to be in
++		* pseudo state. This is used to sense/measure the stats from lq.
++		*/
++	uint8 obss_bwsw_rx_crs_threshold_cfg; /**< RX CRS default threshold */
++	uint8 obss_bwsw_dur_thres; /**< OBSS dyn bwsw trigger/RX CRS Sec */
++	uint8 obss_bwsw_txop_threshold_cfg; /**< TXOP default threshold */
++} BWL_POST_PACKED_STRUCT wlc_obss_dynbwsw_config_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint32 version;	/**< version field */
++	uint32 config_mask;
++	uint32 reset_mask;
++	wlc_obss_dynbwsw_config_t config_params;
++} BWL_POST_PACKED_STRUCT obss_config_params_t;
++#include <packed_section_end.h>
++
++/**bsscfg type */
++typedef enum bsscfg_type {
++	BSSCFG_TYPE_GENERIC = 0,	/**< Generic AP/STA/IBSS BSS */
++	BSSCFG_TYPE_P2P = 1,		/**< P2P BSS */
++	/* index 2 earlier used for BTAMP */
++	BSSCFG_TYPE_PSTA = 3,
++	BSSCFG_TYPE_TDLS = 4,
++	BSSCFG_TYPE_SLOTTED_BSS = 5,
++	BSSCFG_TYPE_PROXD = 6,
++	BSSCFG_TYPE_NAN = 7,
++	BSSCFG_TYPE_MESH = 8,
++	BSSCFG_TYPE_AIBSS = 9
++} bsscfg_type_t;
++
++/* bsscfg subtype */
++typedef enum bsscfg_subtype {
++	BSSCFG_SUBTYPE_NONE = 0,
++	BSSCFG_GENERIC_STA = 1,		/* GENERIC */
++	BSSCFG_GENERIC_AP = 2,
++	BSSCFG_GENERIC_IBSS = 6,
++	BSSCFG_P2P_GC = 3,		/* P2P */
++	BSSCFG_P2P_GO = 4,
++	BSSCFG_P2P_DISC = 5,
++	/* Index 7 & 8 earlier used for BTAMP */
++	BSSCFG_SUBTYPE_AWDL = 9, /* SLOTTED_BSS_TYPE */
++	BSSCFG_SUBTYPE_NAN_MGMT = 10,
++	BSSCFG_SUBTYPE_NAN_DATA = 11,
++	BSSCFG_SUBTYPE_NAN_MGMT_DATA = 12
++} bsscfg_subtype_t;
++
++typedef struct wlc_bsscfg_info {
++	uint32 type;
++	uint32 subtype;
++} wlc_bsscfg_info_t;
++
++/* ULP SHM Offsets info */
++typedef struct ulp_shm_info {
++	uint32 m_ulp_ctrl_sdio;
++	uint32 m_ulp_wakeevt_ind;
++	uint32 m_ulp_wakeind;
++} ulp_shm_info_t;
++
++
++/* Legacy structure to help keep backward compatible wl tool and tray app */
++
++#define	LEGACY_WL_BSS_INFO_VERSION	107	/**< older version of wl_bss_info struct */
++
++typedef struct wl_bss_info_107 {
++	uint32		version;		/**< version field */
++	uint32		length;			/**< byte length of data in this record,
++						 * starting at version and including IEs
++						 */
++	struct ether_addr BSSID;
++	uint16		beacon_period;		/**< units are Kusec */
++	uint16		capability;		/**< Capability information */
++	uint8		SSID_len;
++	uint8		SSID[32];
++	uint8		PAD;
++	struct {
++		uint32	count;			/**< # rates in this set */
++		uint8	rates[16];		/**< rates in 500kbps units w/hi bit set if basic */
++	} rateset;				/**< supported rates */
++	uint8		channel;		/**< Channel no. */
++	uint8		PAD;
++	uint16		atim_window;		/**< units are Kusec */
++	uint8		dtim_period;		/**< DTIM period */
++	uint8		PAD;
++	int16		RSSI;			/**< receive signal strength (in dBm) */
++	int8		phy_noise;		/**< noise (in dBm) */
++	uint8		PAD[3];
++	uint32		ie_length;		/**< byte length of Information Elements */
++	/* variable length Information Elements */
++} wl_bss_info_107_t;
++
++/*
++ * Per-BSS information structure.
++ */
++
++#define	LEGACY2_WL_BSS_INFO_VERSION	108		/**< old version of wl_bss_info struct */
++
++/**
++ * BSS info structure
++ * Applications MUST CHECK ie_offset field and length field to access IEs and
++ * next bss_info structure in a vector (in wl_scan_results_t)
++ */
++typedef struct wl_bss_info_108 {
++	uint32		version;		/**< version field */
++	uint32		length;			/**< byte length of data in this record,
++						 * starting at version and including IEs
++						 */
++	struct ether_addr BSSID;
++	uint16		beacon_period;		/**< units are Kusec */
++	uint16		capability;		/**< Capability information */
++	uint8		SSID_len;
++	uint8		SSID[32];
++	uint8		PAD[1];
++	struct {
++		uint32	count;			/**< # rates in this set */
++		uint8	rates[16];		/**< rates in 500kbps units w/hi bit set if basic */
++	} rateset;				/**< supported rates */
++	chanspec_t	chanspec;		/**< chanspec for bss */
++	uint16		atim_window;		/**< units are Kusec */
++	uint8		dtim_period;		/**< DTIM period */
++	uint8		PAD;
++	int16		RSSI;			/**< receive signal strength (in dBm) */
++	int8		phy_noise;		/**< noise (in dBm) */
++
++	uint8		n_cap;			/**< BSS is 802.11N Capable */
++	uint8		PAD[2];
++	uint32		nbss_cap;		/**< 802.11N BSS Capabilities (based on HT_CAP_*) */
++	uint8		ctl_ch;			/**< 802.11N BSS control channel number */
++	uint8		PAD[3];
++	uint32		reserved32[1];		/**< Reserved for expansion of BSS properties */
++	uint8		flags;			/**< flags */
++	uint8		reserved[3];		/**< Reserved for expansion of BSS properties */
++	uint8		basic_mcs[MCSSET_LEN];	/**< 802.11N BSS required MCS set */
++
++	uint16		ie_offset;		/**< offset at which IEs start, from beginning */
++	uint8		PAD[2];
++	uint32		ie_length;		/**< byte length of Information Elements */
++	/* Add new fields here */
++	/* variable length Information Elements */
++} wl_bss_info_108_t;
++
++
++#define	WL_BSS_INFO_VERSION	109		/**< current version of wl_bss_info struct */
++
++/**
++ * BSS info structure
++ * Applications MUST CHECK ie_offset field and length field to access IEs and
++ * next bss_info structure in a vector (in wl_scan_results_t)
++ */
++typedef struct wl_bss_info {
++	uint32		version;		/**< version field */
++	uint32		length;			/**< byte length of data in this record,
++						 * starting at version and including IEs
++						 */
++	struct ether_addr BSSID;
++	uint16		beacon_period;		/**< units are Kusec */
++	uint16		capability;		/**< Capability information */
++	uint8		SSID_len;
++	uint8		SSID[32];
++	uint8		bcnflags;		/* additional flags w.r.t. beacon */
++	struct {
++		uint32	count;			/**< # rates in this set */
++		uint8	rates[16];		/**< rates in 500kbps units w/hi bit set if basic */
++	} rateset;				/**< supported rates */
++	chanspec_t	chanspec;		/**< chanspec for bss */
++	uint16		atim_window;		/**< units are Kusec */
++	uint8		dtim_period;		/**< DTIM period */
++	uint8		accessnet;		/* from beacon interwork IE (if bcnflags) */
++	int16		RSSI;			/**< receive signal strength (in dBm) */
++	int8		phy_noise;		/**< noise (in dBm) */
++	uint8		n_cap;			/**< BSS is 802.11N Capable */
++	uint16		freespace1;		/* make implicit padding explicit */
++	uint32		nbss_cap;		/**< 802.11N+AC BSS Capabilities */
++	uint8		ctl_ch;			/**< 802.11N BSS control channel number */
++	uint8		padding1[3];		/**< explicit struct alignment padding */
++	uint16		vht_rxmcsmap;	/**< VHT rx mcs map (802.11ac IE, VHT_CAP_MCS_MAP_*) */
++	uint16		vht_txmcsmap;	/**< VHT tx mcs map (802.11ac IE, VHT_CAP_MCS_MAP_*) */
++	uint8		flags;			/**< flags */
++	uint8		vht_cap;		/**< BSS is vht capable */
++	uint8		reserved[2];		/**< Reserved for expansion of BSS properties */
++	uint8		basic_mcs[MCSSET_LEN];	/**< 802.11N BSS required MCS set */
++
++	uint16		ie_offset;		/**< offset at which IEs start, from beginning */
++	uint16		freespace2;		/* making implicit padding explicit */
++	uint32		ie_length;		/**< byte length of Information Elements */
++	int16		SNR;			/**< average SNR of during frame reception */
++	uint16		vht_mcsmap;		/**< STA's Associated vhtmcsmap */
++	uint16		vht_mcsmap_prop;	/**< STA's Associated prop vhtmcsmap */
++	uint16		vht_txmcsmap_prop;	/**< prop VHT tx mcs prop */
++	/* Add new fields here */
++	/* variable length Information Elements */
++} wl_bss_info_t;
++
++#define	WL_GSCAN_FULL_RESULT_VERSION	2	/* current version of wl_gscan_result_t struct */
++#define WL_GSCAN_INFO_FIXED_FIELD_SIZE   (sizeof(wl_gscan_bss_info_t) - sizeof(wl_bss_info_t))
++
++typedef struct wl_gscan_bss_info {
++	uint32      timestamp[2];
++	wl_bss_info_t info;
++	/* Do not add any more members below, fixed  */
++	/* and variable length Information Elements to follow */
++} wl_gscan_bss_info_t;
++
++
++typedef struct wl_bsscfg {
++	uint32  bsscfg_idx;
++	uint32  wsec;
++	uint32  WPA_auth;
++	uint32  wsec_index;
++	uint32  associated;
++	uint32  BSS;
++	uint32  phytest_on;
++	struct ether_addr   prev_BSSID;
++	struct ether_addr   BSSID;
++	uint32  targetbss_wpa2_flags;
++	uint32 assoc_type;
++	uint32 assoc_state;
++} wl_bsscfg_t;
++
++typedef struct wl_if_add {
++	uint32  bsscfg_flags;
++	uint32  if_flags;
++	uint32  ap;
++	struct ether_addr   mac_addr;
++	uint16  PAD;
++	uint32  wlc_index;
++} wl_if_add_t;
++
++typedef struct wl_bss_config {
++	uint32	atim_window;
++	uint32	beacon_period;
++	uint32	chanspec;
++} wl_bss_config_t;
++
++#define WL_BSS_USER_RADAR_CHAN_SELECT	0x1	/**< User application will randomly select
++						 * radar channel.
++						 */
++
++#define DLOAD_HANDLER_VER		1	/**< Downloader version */
++#define DLOAD_FLAG_VER_MASK		0xf000	/**< Downloader version mask */
++#define DLOAD_FLAG_VER_SHIFT		12	/**< Downloader version shift */
++
++#define DL_CRC_NOT_INUSE	0x0001
++#define DL_BEGIN		0x0002
++#define DL_END			0x0004
++
++/* Flags for Major/Minor/Date number shift and mask */
++#define EPI_VER_SHIFT     16
++#define EPI_VER_MASK      0xFFFF
++/** generic download types & flags */
++enum {
++	DL_TYPE_UCODE = 1,
++	DL_TYPE_CLM = 2
++};
++
++/** ucode type values */
++enum {
++	UCODE_FW,
++	INIT_VALS,
++	BS_INIT_VALS
++};
++
++struct wl_dload_data {
++	uint16 flag;
++	uint16 dload_type;
++	uint32 len;
++	uint32 crc;
++	uint8  data[1];
++};
++typedef struct wl_dload_data wl_dload_data_t;
++
++struct wl_ucode_info {
++	uint32 ucode_type;
++	uint32 num_chunks;
++	uint32 chunk_len;
++	uint32 chunk_num;
++	uint8  data_chunk[1];
++};
++typedef struct wl_ucode_info wl_ucode_info_t;
++
++struct wl_clm_dload_info {
++	uint32 ds_id;
++	uint32 clm_total_len;
++	uint32 num_chunks;
++	uint32 chunk_len;
++	uint32 chunk_offset;
++	uint8  data_chunk[1];
++};
++typedef struct wl_clm_dload_info wl_clm_dload_info_t;
++
++
++typedef struct wlc_ssid {
++	uint32		SSID_len;
++	uint8		SSID[DOT11_MAX_SSID_LEN];
++} wlc_ssid_t;
++
++typedef struct wlc_ssid_ext {
++	uint8      hidden;
++	uint8      PAD;
++	uint16     flags;
++	uint8      SSID_len;
++	int8       rssi_thresh;
++	uint8      SSID[DOT11_MAX_SSID_LEN];
++} wlc_ssid_ext_t;
++
++#define MAX_PREFERRED_AP_NUM     5
++typedef struct wlc_fastssidinfo {
++	uint32			SSID_channel[MAX_PREFERRED_AP_NUM];
++	wlc_ssid_t		SSID_info[MAX_PREFERRED_AP_NUM];
++} wlc_fastssidinfo_t;
++
++typedef struct wnm_url {
++	uint8   len;
++	uint8   data[1];
++} wnm_url_t;
++
++typedef struct chan_scandata {
++	uint8		txpower;
++	uint8		pad;
++	chanspec_t	channel;		/**< Channel num, bw, ctrl_sb and band */
++	uint32		channel_mintime;
++	uint32		channel_maxtime;
++} chan_scandata_t;
++
++typedef enum wl_scan_type {
++	EXTDSCAN_FOREGROUND_SCAN,
++	EXTDSCAN_BACKGROUND_SCAN,
++	EXTDSCAN_FORCEDBACKGROUND_SCAN
++} wl_scan_type_t;
++
++#define WLC_EXTDSCAN_MAX_SSID		5
++
++typedef struct wl_extdscan_params {
++	int8 		nprobes;		/**< 0, passive, otherwise active */
++	int8    	split_scan;		/**< split scan */
++	int8		band;			/**< band */
++	int8		pad;
++	wlc_ssid_t 	ssid[WLC_EXTDSCAN_MAX_SSID]; /**< ssid list */
++	uint32		tx_rate;		/**< in 500ksec units */
++	wl_scan_type_t	scan_type;		/**< enum */
++	int32 		channel_num;
++	chan_scandata_t channel_list[1];	/**< list of chandata structs */
++} wl_extdscan_params_t;
++
++#define WL_EXTDSCAN_PARAMS_FIXED_SIZE 	(sizeof(wl_extdscan_params_t) - sizeof(chan_scandata_t))
++
++#define WL_SCAN_PARAMS_SSID_MAX 	10
++
++typedef struct wl_scan_params {
++	wlc_ssid_t ssid;		/**< default: {0, ""} */
++	struct ether_addr bssid;	/**< default: bcast */
++	int8 bss_type;			/**< default: any,
++					 * DOT11_BSSTYPE_ANY/INFRASTRUCTURE/INDEPENDENT
++					 */
++	uint8 scan_type;		/**< flags, 0 use default */
++	int32 nprobes;			/**< -1 use default, number of probes per channel */
++	int32 active_time;		/**< -1 use default, dwell time per channel for
++					 * active scanning
++					 */
++	int32 passive_time;		/**< -1 use default, dwell time per channel
++					 * for passive scanning
++					 */
++	int32 home_time;		/**< -1 use default, dwell time for the home channel
++					 * between channel scans
++					 */
++	int32 channel_num;		/**< count of channels and ssids that follow
++					 *
++					 * low half is count of channels in channel_list, 0
++					 * means default (use all available channels)
++					 *
++					 * high half is entries in wlc_ssid_t array that
++					 * follows channel_list, aligned for int32 (4 bytes)
++					 * meaning an odd channel count implies a 2-byte pad
++					 * between end of channel_list and first ssid
++					 *
++					 * if ssid count is zero, single ssid in the fixed
++					 * parameter portion is assumed, otherwise ssid in
++					 * the fixed portion is ignored
++					 */
++	uint16 channel_list[1];		/**< list of chanspecs */
++} wl_scan_params_t;
++
++/** size of wl_scan_params not including variable length array */
++#define WL_SCAN_PARAMS_FIXED_SIZE 64
++#define WL_MAX_ROAMSCAN_DATSZ	(WL_SCAN_PARAMS_FIXED_SIZE + (WL_NUMCHANNELS * sizeof(uint16)))
++
++#define ISCAN_REQ_VERSION 1
++
++/** incremental scan struct */
++typedef struct wl_iscan_params {
++	uint32 version;
++	uint16 action;
++	uint16 scan_duration;
++	wl_scan_params_t params;
++} wl_iscan_params_t;
++
++/** 3 fields + size of wl_scan_params, not including variable length array */
++#define WL_ISCAN_PARAMS_FIXED_SIZE (OFFSETOF(wl_iscan_params_t, params) + sizeof(wlc_ssid_t))
++
++typedef struct wl_scan_results {
++	uint32 buflen;
++	uint32 version;
++	uint32 count;
++	wl_bss_info_t bss_info[1];
++} wl_scan_results_t;
++
++/** size of wl_scan_results not including variable length array */
++#define WL_SCAN_RESULTS_FIXED_SIZE (sizeof(wl_scan_results_t) - sizeof(wl_bss_info_t))
++#define ESCAN_REQ_VERSION 1
++
++/** event scan reduces amount of SOC memory needed to store scan results */
++typedef struct wl_escan_params {
++	uint32 version;
++	uint16 action;
++	uint16 sync_id;
++	wl_scan_params_t params;
++} wl_escan_params_t;
++
++#define WL_ESCAN_PARAMS_FIXED_SIZE (OFFSETOF(wl_escan_params_t, params) + sizeof(wlc_ssid_t))
++
++/** event scan reduces amount of SOC memory needed to store scan results */
++typedef struct wl_escan_result {
++	uint32 buflen;
++	uint32 version;
++	uint16 sync_id;
++	uint16 bss_count;
++	wl_bss_info_t bss_info[1];
++} wl_escan_result_t;
++
++#define WL_ESCAN_RESULTS_FIXED_SIZE (sizeof(wl_escan_result_t) - sizeof(wl_bss_info_t))
++typedef struct wl_gscan_result {
++	uint32 buflen;
++	uint32 version;
++	uint32 scan_ch_bucket;
++	wl_gscan_bss_info_t bss_info[1];
++} wl_gscan_result_t;
++
++#define WL_GSCAN_RESULTS_FIXED_SIZE (sizeof(wl_gscan_result_t) - sizeof(wl_gscan_bss_info_t))
++/** incremental scan results struct */
++typedef struct wl_iscan_results {
++	uint32 status;
++	wl_scan_results_t results;
++} wl_iscan_results_t;
++
++/** size of wl_iscan_results not including variable length array */
++#define WL_ISCAN_RESULTS_FIXED_SIZE \
++	(WL_SCAN_RESULTS_FIXED_SIZE + OFFSETOF(wl_iscan_results_t, results))
++
++typedef struct wl_probe_params {
++	wlc_ssid_t ssid;
++	struct ether_addr bssid;
++	struct ether_addr mac;
++} wl_probe_params_t;
++
++#define WL_MAXRATES_IN_SET		16	/**< max # of rates in a rateset */
++typedef struct wl_rateset {
++	uint32	count;				/**< # rates in this set */
++	uint8	rates[WL_MAXRATES_IN_SET];	/**< rates in 500kbps units w/hi bit set if basic */
++} wl_rateset_t;
++
++typedef struct wl_rateset_args {
++	uint32	count;				/**< # rates in this set */
++	uint8	rates[WL_MAXRATES_IN_SET];	/**< rates in 500kbps units w/hi bit set if basic */
++	uint8   mcs[MCSSET_LEN];        	/**< supported mcs index bit map */
++	uint16 vht_mcs[VHT_CAP_MCS_MAP_NSS_MAX]; /**< supported mcs index bit map per nss */
++} wl_rateset_args_t;
++
++#define TXBF_RATE_MCS_ALL		4
++#define TXBF_RATE_VHT_ALL		4
++#define TXBF_RATE_OFDM_ALL		8
++
++typedef struct wl_txbf_rateset {
++	uint8	txbf_rate_mcs[TXBF_RATE_MCS_ALL];	/**< one for each stream */
++	uint8	txbf_rate_mcs_bcm[TXBF_RATE_MCS_ALL];	/**< one for each stream */
++	uint16	txbf_rate_vht[TXBF_RATE_VHT_ALL];	/**< one for each stream */
++	uint16	txbf_rate_vht_bcm[TXBF_RATE_VHT_ALL];	/**< one for each stream */
++	uint8	txbf_rate_ofdm[TXBF_RATE_OFDM_ALL]; /**< bitmap of ofdm rates that enables txbf */
++	uint8	txbf_rate_ofdm_bcm[TXBF_RATE_OFDM_ALL]; /* bitmap of ofdm rates that enables txbf */
++	uint8	txbf_rate_ofdm_cnt;
++	uint8	txbf_rate_ofdm_cnt_bcm;
++} wl_txbf_rateset_t;
++
++#define NUM_BFGAIN_ARRAY_1RX	2
++#define NUM_BFGAIN_ARRAY_2RX	3
++#define NUM_BFGAIN_ARRAY_3RX	4
++#define NUM_BFGAIN_ARRAY_4RX	5
++
++typedef struct wl_txbf_expgainset {
++	/* bitmap for each element: B[4:0]=>c0, B[9:5]=>c1, B[14:10]=>c2, B[19:15]=>c[3-7]
++	 * B[24:20]=>c[8-9], B[29:25]=>c[10-11]
++	 */
++	uint32	bfgain_2x1[NUM_BFGAIN_ARRAY_1RX]; /* exp     1ss, imp 1ss */
++	uint32	bfgain_2x2[NUM_BFGAIN_ARRAY_2RX]; /* exp [1-2]ss, imp 1ss */
++	uint32	bfgain_3x1[NUM_BFGAIN_ARRAY_1RX];
++	uint32	bfgain_3x2[NUM_BFGAIN_ARRAY_2RX];
++	uint32	bfgain_3x3[NUM_BFGAIN_ARRAY_3RX]; /* exp [1-3]ss, imp 1ss */
++	uint32	bfgain_4x1[NUM_BFGAIN_ARRAY_1RX];
++	uint32	bfgain_4x2[NUM_BFGAIN_ARRAY_2RX];
++	uint32	bfgain_4x3[NUM_BFGAIN_ARRAY_3RX];
++	uint32	bfgain_4x4[NUM_BFGAIN_ARRAY_4RX]; /* exp [1-4]ss, imp 1ss */
++} wl_txbf_expgainset_t;
++
++#define OFDM_RATE_MASK			0x0000007f
++typedef uint8 ofdm_rates_t;
++
++typedef struct wl_rates_info {
++	wl_rateset_t rs_tgt;
++	uint32 phy_type;
++	int32 bandtype;
++	uint8 cck_only;
++	uint8 rate_mask;
++	uint8 mcsallow;
++	uint8 bw;
++	uint8 txstreams;
++	uint8 PAD[3];
++} wl_rates_info_t;
++
++/**uint32 list */
++typedef struct wl_uint32_list {
++	/** in - # of elements, out - # of entries */
++	uint32 count;
++	/** variable length uint32 list */
++	uint32 element[1];
++} wl_uint32_list_t;
++
++/* WLC_SET_ALLOW_MODE values */
++#define ALLOW_MODE_ANY_BSSID		0
++#define ALLOW_MODE_ONLY_DESIRED_BSSID	1
++#define ALLOW_MODE_NO_BSSID		2
++
++/** used for association with a specific BSSID and chanspec list */
++typedef struct wl_assoc_params {
++	struct ether_addr bssid;	/**< 00:00:00:00:00:00: broadcast scan */
++	uint16 bssid_cnt;		/**< 0: use chanspec_num, and the single bssid,
++					* otherwise count of chanspecs in chanspec_list
++					* AND paired bssids following chanspec_list
++					* also, chanspec_num has to be set to zero
++					* for bssid list to be used
++					*/
++	int32 chanspec_num;		/**< 0: all available channels,
++					* otherwise count of chanspecs in chanspec_list
++					*/
++	chanspec_t chanspec_list[1];	/**< list of chanspecs */
++} wl_assoc_params_t;
++
++#define WL_ASSOC_PARAMS_FIXED_SIZE 	OFFSETOF(wl_assoc_params_t, chanspec_list)
++
++/** used for reassociation/roam to a specific BSSID and channel */
++typedef wl_assoc_params_t wl_reassoc_params_t;
++#define WL_REASSOC_PARAMS_FIXED_SIZE	WL_ASSOC_PARAMS_FIXED_SIZE
++
++/** used for association to a specific BSSID and channel */
++typedef wl_assoc_params_t wl_join_assoc_params_t;
++#define WL_JOIN_ASSOC_PARAMS_FIXED_SIZE	WL_ASSOC_PARAMS_FIXED_SIZE
++
++/** used for join with or without a specific bssid and channel list */
++typedef struct wl_join_params {
++	wlc_ssid_t ssid;
++	wl_assoc_params_t params;	/**< optional field, but it must include the fixed portion
++					 * of the wl_assoc_params_t struct when it does present.
++					 */
++} wl_join_params_t;
++
++#define WL_JOIN_PARAMS_FIXED_SIZE 	(OFFSETOF(wl_join_params_t, params) + \
++					 WL_ASSOC_PARAMS_FIXED_SIZE)
++
++typedef struct wlc_roam_exp_params {
++	int8 a_band_boost_threshold;
++	int8 a_band_penalty_threshold;
++	int8 a_band_boost_factor;
++	int8 a_band_penalty_factor;
++	int8 cur_bssid_boost;
++	int8 alert_roam_trigger_threshold;
++	int16 a_band_max_boost;
++} wlc_roam_exp_params_t;
++
++#define ROAM_EXP_CFG_VERSION     1
++
++#define ROAM_EXP_ENABLE_FLAG             (1 << 0)
++
++#define ROAM_EXP_CFG_PRESENT             (1 << 1)
++
++typedef struct wl_roam_exp_cfg {
++	uint16 version;
++	uint16 flags;
++	wlc_roam_exp_params_t params;
++} wl_roam_exp_cfg_t;
++
++typedef struct wl_bssid_pref_list {
++	struct ether_addr bssid;
++	/* Add this to modify rssi */
++	int8 rssi_factor;
++	int8 flags;
++} wl_bssid_pref_list_t;
++
++#define BSSID_PREF_LIST_VERSION        1
++#define ROAM_EXP_CLEAR_BSSID_PREF        (1 << 0)
++
++typedef struct wl_bssid_pref_cfg {
++	uint16 version;
++	uint16 flags;
++	uint16 count;
++	uint16 reserved;
++	wl_bssid_pref_list_t bssids[];
++} wl_bssid_pref_cfg_t;
++
++#define SSID_WHITELIST_VERSION         1
++
++#define ROAM_EXP_CLEAR_SSID_WHITELIST    (1 << 0)
++
++/* Roam SSID whitelist, ssids in this list are ok to  */
++/* be considered as targets to join when considering a roam */
++
++typedef struct wl_ssid_whitelist {
++
++	uint16 version;
++	uint16 flags;
++
++	uint8 ssid_count;
++	uint8 reserved[3];
++	wlc_ssid_t ssids[];
++} wl_ssid_whitelist_t;
++
++#define ROAM_EXP_EVENT_VERSION       1
++
++typedef struct wl_roam_exp_event {
++
++	uint16 version;
++	uint16 flags;
++	wlc_ssid_t cur_ssid;
++} wl_roam_exp_event_t;
++
++/** scan params for extended join */
++typedef struct wl_join_scan_params {
++	uint8 scan_type;		/**< 0 use default, active or passive scan */
++	uint8 PAD[3];
++	int32 nprobes;			/**< -1 use default, number of probes per channel */
++	int32 active_time;		/**< -1 use default, dwell time per channel for
++					 * active scanning
++					 */
++	int32 passive_time;		/**< -1 use default, dwell time per channel
++					 * for passive scanning
++					 */
++	int32 home_time;		/**< -1 use default, dwell time for the home channel
++					 * between channel scans
++					 */
++} wl_join_scan_params_t;
++
++/** extended join params */
++typedef struct wl_extjoin_params {
++	wlc_ssid_t ssid;		/**< {0, ""}: wildcard scan */
++	wl_join_scan_params_t scan;
++	wl_join_assoc_params_t assoc;	/**< optional field, but it must include the fixed portion
++					 * of the wl_join_assoc_params_t struct when it does
++					 * present.
++					 */
++} wl_extjoin_params_t;
++#define WL_EXTJOIN_PARAMS_FIXED_SIZE 	(OFFSETOF(wl_extjoin_params_t, assoc) + \
++					 WL_JOIN_ASSOC_PARAMS_FIXED_SIZE)
++
++#define ANT_SELCFG_MAX		4	/**< max number of antenna configurations */
++#define MAX_STREAMS_SUPPORTED	4	/**< max number of streams supported */
++typedef struct {
++	uint8 ant_config[ANT_SELCFG_MAX];	/**< antenna configuration */
++	uint8 num_antcfg;			/**< number of available antenna configurations */
++} wlc_antselcfg_t;
++
++typedef struct {
++	uint32 duration;	/**< millisecs spent sampling this channel */
++	uint32 congest_ibss;	/**< millisecs in our bss (presumably this traffic will */
++				/**<  move if cur bss moves channels) */
++	uint32 congest_obss;	/**< traffic not in our bss */
++	uint32 interference;	/**< millisecs detecting a non 802.11 interferer. */
++	uint32 timestamp;	/**< second timestamp */
++} cca_congest_t;
++
++typedef struct {
++	chanspec_t chanspec;	/**< Which channel? */
++	uint16 num_secs;	/**< How many secs worth of data */
++	cca_congest_t  secs[1];	/**< Data */
++} cca_congest_channel_req_t;
++typedef struct {
++	uint32 duration;	/**< millisecs spent sampling this channel */
++	uint32 congest;		/**< millisecs detecting busy CCA */
++	uint32 timestamp;	/**< second timestamp */
++} cca_congest_simple_t;
++
++typedef struct {
++	uint16 status;
++	uint16 id;
++	chanspec_t chanspec;			/**< Which channel? */
++	uint16 len;
++	union {
++		cca_congest_simple_t  cca_busy;	/**< CCA busy */
++		int32 noise;			/**< noise floor */
++	};
++} cca_chan_qual_event_t;
++
++typedef struct {
++	uint32 msrmnt_time;	/**< Time for Measurement (msec) */
++	uint32 msrmnt_done;	/**< flag set when measurement complete */
++	char buf[];
++} cca_stats_n_flags;
++
++typedef struct {
++	uint32 msrmnt_query;    /* host to driver query for measurement done */
++	uint32 time_req;        /* time required for measurement */
++	uint8 report_opt;       /* option to print different stats in report */
++	uint8 PAD[3];
++} cca_msrmnt_query;
++
++/* interference sources */
++enum interference_source {
++	ITFR_NONE = 0,			/**< interference */
++	ITFR_PHONE,			/**< wireless phone */
++	ITFR_VIDEO_CAMERA,		/**< wireless video camera */
++	ITFR_MICROWAVE_OVEN,		/**< microwave oven */
++	ITFR_BABY_MONITOR,		/**< wireless baby monitor */
++	ITFR_BLUETOOTH,			/**< bluetooth */
++	ITFR_VIDEO_CAMERA_OR_BABY_MONITOR,	/**< wireless camera or baby monitor */
++	ITFR_BLUETOOTH_OR_BABY_MONITOR,	/**< bluetooth or baby monitor */
++	ITFR_VIDEO_CAMERA_OR_PHONE,	/**< video camera or phone */
++	ITFR_UNIDENTIFIED		/**< interference from unidentified source */
++};
++
++/** structure for interference source report */
++typedef struct {
++	uint32 flags;		/**< flags.  bit definitions below */
++	uint32 source;		/**< last detected interference source */
++	uint32 timestamp;	/**< second timestamp on interferenced flag change */
++} interference_source_rep_t;
++
++#define WLC_CNTRY_BUF_SZ	4		/**< Country string is 3 bytes + NUL */
++
++typedef struct wl_country {
++	char country_abbrev[WLC_CNTRY_BUF_SZ];	/**< nul-terminated country code used in
++						 * the Country IE
++						 */
++	int32 rev;				/**< revision specifier for ccode
++						 * on set, -1 indicates unspecified.
++						 * on get, rev >= 0
++						 */
++	char ccode[WLC_CNTRY_BUF_SZ];		/**< nul-terminated built-in country code.
++						 * variable length, but fixed size in
++						 * struct allows simple allocation for
++						 * expected country strings <= 3 chars.
++						 */
++} wl_country_t;
++
++
++#define CCODE_INFO_VERSION 1
++
++typedef enum wl_ccode_role {
++	WLC_CCODE_ROLE_ACTIVE = 0,
++	WLC_CCODE_ROLE_HOST,
++	WLC_CCODE_ROLE_80211D_ASSOC,
++	WLC_CCODE_ROLE_80211D_SCAN,
++	WLC_CCODE_ROLE_DEFAULT,
++	WLC_CCODE_LAST
++} wl_ccode_role_t;
++#define WLC_NUM_CCODE_INFO WLC_CCODE_LAST
++
++typedef struct wl_ccode_entry {
++	uint16 reserved;
++	uint8 band;
++	uint8 role;
++	char	ccode[WLC_CNTRY_BUF_SZ];
++} wl_ccode_entry_t;
++
++typedef struct wl_ccode_info {
++	uint16 version;
++	uint16 count;   /**< Number of ccodes entries in the set */
++	wl_ccode_entry_t ccodelist[1];
++} wl_ccode_info_t;
++#define WL_CCODE_INFO_FIXED_LEN	OFFSETOF(wl_ccode_info_t, ccodelist)
++typedef struct wl_channels_in_country {
++	uint32 buflen;
++	uint32 band;
++	char country_abbrev[WLC_CNTRY_BUF_SZ];
++	uint32 count;
++	uint32 channel[1];
++} wl_channels_in_country_t;
++
++typedef struct wl_country_list {
++	uint32 buflen;
++	uint32 band_set;
++	uint32 band;
++	uint32 count;
++	char country_abbrev[1];
++} wl_country_list_t;
++
++typedef struct wl_rm_req_elt {
++	int8	type;
++	int8	flags;
++	chanspec_t	chanspec;
++	uint32	token;		/**< token for this measurement */
++	uint32	tsf_h;		/**< TSF high 32-bits of Measurement start time */
++	uint32	tsf_l;		/**< TSF low 32-bits */
++	uint32	dur;		/**< TUs */
++} wl_rm_req_elt_t;
++
++typedef struct wl_rm_req {
++	uint32	token;		/**< overall measurement set token */
++	uint32	count;		/**< number of measurement requests */
++	void	*cb;		/**< completion callback function: may be NULL */
++	void	*cb_arg;	/**< arg to completion callback function */
++	wl_rm_req_elt_t	req[1];	/**< variable length block of requests */
++} wl_rm_req_t;
++#define WL_RM_REQ_FIXED_LEN	OFFSETOF(wl_rm_req_t, req)
++
++typedef struct wl_rm_rep_elt {
++	int8	type;
++	int8	flags;
++	chanspec_t	chanspec;
++	uint32	token;		/**< token for this measurement */
++	uint32	tsf_h;		/**< TSF high 32-bits of Measurement start time */
++	uint32	tsf_l;		/**< TSF low 32-bits */
++	uint32	dur;		/**< TUs */
++	uint32	len;		/**< byte length of data block */
++	uint8	data[1];	/**< variable length data block */
++} wl_rm_rep_elt_t;
++#define WL_RM_REP_ELT_FIXED_LEN	24	/**< length excluding data block */
++
++#define WL_RPI_REP_BIN_NUM 8
++typedef struct wl_rm_rpi_rep {
++	uint8	rpi[WL_RPI_REP_BIN_NUM];
++	int8	rpi_max[WL_RPI_REP_BIN_NUM];
++} wl_rm_rpi_rep_t;
++
++typedef struct wl_rm_rep {
++	uint32	token;		/**< overall measurement set token */
++	uint32	len;		/**< length of measurement report block */
++	wl_rm_rep_elt_t	rep[1];	/**< variable length block of reports */
++} wl_rm_rep_t;
++#define WL_RM_REP_FIXED_LEN	8
++typedef enum sup_auth_status {
++	/* Basic supplicant authentication states */
++	WLC_SUP_DISCONNECTED = 0,
++	WLC_SUP_CONNECTING,
++	WLC_SUP_IDREQUIRED,
++	WLC_SUP_AUTHENTICATING,
++	WLC_SUP_AUTHENTICATED,
++	WLC_SUP_KEYXCHANGE,
++	WLC_SUP_KEYED,
++	WLC_SUP_TIMEOUT,
++	WLC_SUP_LAST_BASIC_STATE,
++
++	/* Extended supplicant authentication states */
++	/** Waiting to receive handshake msg M1 */
++	WLC_SUP_KEYXCHANGE_WAIT_M1 = WLC_SUP_AUTHENTICATED,
++	/** Preparing to send handshake msg M2 */
++	WLC_SUP_KEYXCHANGE_PREP_M2 = WLC_SUP_KEYXCHANGE,
++	/* Waiting to receive handshake msg M3 */
++	WLC_SUP_KEYXCHANGE_WAIT_M3 = WLC_SUP_LAST_BASIC_STATE,
++	WLC_SUP_KEYXCHANGE_PREP_M4,	/**< Preparing to send handshake msg M4 */
++	WLC_SUP_KEYXCHANGE_WAIT_G1,	/**< Waiting to receive handshake msg G1 */
++	WLC_SUP_KEYXCHANGE_PREP_G2	/**< Preparing to send handshake msg G2 */
++} sup_auth_status_t;
++
++typedef struct wl_wsec_key {
++	uint32		index;		/**< key index */
++	uint32		len;		/**< key length */
++	uint8		data[DOT11_MAX_KEY_SIZE];	/**< key data */
++	uint32		pad_1[18];
++	uint32		algo;		/**< CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
++	uint32		flags;		/**< misc flags */
++	uint32		pad_2[2];
++	int32		pad_3;
++	int32		iv_initialized;	/**< has IV been initialized already? */
++	int32		pad_4;
++	/* Rx IV */
++	struct {
++		uint32	hi;		/**< upper 32 bits of IV */
++		uint16	lo;		/**< lower 16 bits of IV */
++		uint16	PAD;
++	} rxiv;
++	uint32		pad_5[2];
++	struct ether_addr ea;		/**< per station */
++	uint16	PAD;
++} wl_wsec_key_t;
++
++#define WSEC_MIN_PSK_LEN	8
++#define WSEC_MAX_PSK_LEN	64
++/* Max length of supported passphrases for SAE */
++#define WSEC_MAX_PASSPHRASE_LEN 256u
++
++/** Flag for key material needing passhash'ing */
++#define WSEC_PASSPHRASE		(1<<0)
++
++/**receptacle for WLC_SET_WSEC_PMK parameter */
++typedef struct wsec_pmk {
++	ushort	key_len;		/**< octets in key material */
++	ushort	flags;			/**< key handling qualification */
++	uint8	key[WSEC_MAX_PSK_LEN];	/**< PMK material */
++} wsec_pmk_t;
++
++#define WL_AUTH_EVENT_DATA_V1		0x1
++
++/* tlv ids for auth event */
++#define WL_AUTH_PMK_TLV_ID	1
++#define WL_AUTH_PMKID_TLV_ID	2
++/* AUTH event data
++* pmk and pmkid in case of SAE auth
++* xtlvs will be 32 bit alligned
++*/
++typedef struct wl_auth_event {
++	uint16 version;
++	uint16 length;
++	uint8 xtlvs[];
++} wl_auth_event_t;
++
++#define WL_AUTH_EVENT_FIXED_LEN_V1	OFFSETOF(wl_auth_event_t, xtlvs)
++
++typedef struct _pmkid {
++	struct ether_addr	BSSID;
++	uint8			PMKID[WPA2_PMKID_LEN];
++} pmkid_t;
++
++typedef struct _pmkid_list {
++	uint32	npmkid;
++	pmkid_t	pmkid[1];
++} pmkid_list_t;
++
++typedef struct _pmkid_cand {
++	struct ether_addr	BSSID;
++	uint8			preauth;
++} pmkid_cand_t;
++
++typedef struct _pmkid_cand_list {
++	uint32	npmkid_cand;
++	pmkid_cand_t	pmkid_cand[1];
++} pmkid_cand_list_t;
++
++#define WL_STA_ANT_MAX		4	/**< max possible rx antennas */
++
++typedef struct wl_assoc_info {
++	uint32		req_len;
++	uint32		resp_len;
++	uint32		flags;
++	struct dot11_assoc_req req;
++	struct ether_addr reassoc_bssid; /**< used in reassoc's */
++	struct dot11_assoc_resp resp;
++} wl_assoc_info_t;
++
++typedef struct wl_led_info {
++	uint32      index;      /**< led index */
++	uint32      behavior;
++	uint8       activehi;
++	uint8       PAD[3];
++} wl_led_info_t;
++
++
++/** srom read/write struct passed through ioctl */
++typedef struct {
++	uint32	byteoff;	/**< byte offset */
++	uint32	nbytes;		/**< number of bytes */
++	uint16	buf[];
++} srom_rw_t;
++
++#define CISH_FLAG_PCIECIS	(1 << 15)	/**< write CIS format bit for PCIe CIS */
++
++/** similar cis (srom or otp) struct [iovar: may not be aligned] */
++typedef struct {
++	uint16	source;		/**< cis source */
++	uint16	flags;		/**< flags */
++	uint32	byteoff;	/**< byte offset */
++	uint32	nbytes;		/**< number of bytes */
++	/* data follows here */
++} cis_rw_t;
++
++/** R_REG and W_REG struct passed through ioctl */
++typedef struct {
++	uint32	byteoff;	/**< byte offset of the field in d11regs_t */
++	uint32	val;		/**< read/write value of the field */
++	uint32	size;		/**< sizeof the field */
++	uint32	band;		/**< band (optional) */
++} rw_reg_t;
++
++/**
++ * Structure used by GET/SET_ATTEN ioctls - it controls power in b/g-band
++ * PCL - Power Control Loop
++ */
++typedef struct {
++	uint16	auto_ctrl;	/**< WL_ATTEN_XX */
++	uint16	bb;		/**< Baseband attenuation */
++	uint16	radio;		/**< Radio attenuation */
++	uint16	txctl1;		/**< Radio TX_CTL1 value */
++} atten_t;
++
++/** Per-AC retry parameters */
++struct wme_tx_params_s {
++	uint8  short_retry;
++	uint8  short_fallback;
++	uint8  long_retry;
++	uint8  long_fallback;
++	uint16 max_rate;  /**< In units of 512 Kbps */
++};
++
++typedef struct wme_tx_params_s wme_tx_params_t;
++
++#define WL_WME_TX_PARAMS_IO_BYTES (sizeof(wme_tx_params_t) * AC_COUNT)
++
++/**Used to get specific link/ac parameters */
++typedef struct {
++	int32 ac;
++	uint8 val;
++	struct ether_addr ea;
++	uint8 PAD;
++} link_val_t;
++
++
++#define WL_PM_MUTE_TX_VER 1
++
++typedef struct wl_pm_mute_tx {
++	uint16 version;		/**< version */
++	uint16 len;		/**< length */
++	uint16 deadline;	/**< deadline timer (in milliseconds) */
++	uint8  enable;		/**< set to 1 to enable mode; set to 0 to disable it */
++	uint8 PAD;
++} wl_pm_mute_tx_t;
++
++
++/* sta_info_t version 4 */
++typedef struct {
++	uint16			ver;		/**< version of this struct */
++	uint16			len;		/**< length in bytes of this structure */
++	uint16			cap;		/**< sta's advertised capabilities */
++	uint16			PAD;
++	uint32			flags;		/**< flags defined below */
++	uint32			idle;		/**< time since data pkt rx'd from sta */
++	struct ether_addr	ea;		/**< Station address */
++	uint16			PAD;
++	wl_rateset_t	rateset;	/**< rateset in use */
++	uint32			in;		/**< seconds elapsed since associated */
++	uint32			listen_interval_inms; /**< Min Listen interval in ms for this STA */
++	uint32			tx_pkts;	/**< # of user packets transmitted (unicast) */
++	uint32			tx_failures;	/**< # of user packets failed */
++	uint32			rx_ucast_pkts;	/**< # of unicast packets received */
++	uint32			rx_mcast_pkts;	/**< # of multicast packets received */
++	uint32			tx_rate;	/**< Rate used by last tx frame */
++	uint32			rx_rate;	/**< Rate of last successful rx frame */
++	uint32			rx_decrypt_succeeds;	/**< # of packet decrypted successfully */
++	uint32			rx_decrypt_failures;	/**< # of packet decrypted unsuccessfully */
++	uint32			tx_tot_pkts;	/**< # of user tx pkts (ucast + mcast) */
++	uint32			rx_tot_pkts;	/**< # of data packets recvd (uni + mcast) */
++	uint32			tx_mcast_pkts;	/**< # of mcast pkts txed */
++	uint64			tx_tot_bytes;	/**< data bytes txed (ucast + mcast) */
++	uint64			rx_tot_bytes;	/**< data bytes recvd (ucast + mcast) */
++	uint64			tx_ucast_bytes;	/**< data bytes txed (ucast) */
++	uint64			tx_mcast_bytes;	/**< # data bytes txed (mcast) */
++	uint64			rx_ucast_bytes;	/**< data bytes recvd (ucast) */
++	uint64			rx_mcast_bytes;	/**< data bytes recvd (mcast) */
++	int8			rssi[WL_STA_ANT_MAX]; /**< average rssi per antenna
++							* of data frames
++							*/
++	int8			nf[WL_STA_ANT_MAX];	/**< per antenna noise floor */
++	uint16			aid;			/**< association ID */
++	uint16			ht_capabilities;	/**< advertised ht caps */
++	uint16			vht_flags;		/**< converted vht flags */
++	uint16			PAD;
++	uint32			tx_pkts_retried;	/**< # of frames where a retry was
++							 * necessary
++							 */
++	uint32			tx_pkts_retry_exhausted; /**< # of user frames where a retry
++							  * was exhausted
++							  */
++	int8			rx_lastpkt_rssi[WL_STA_ANT_MAX]; /**< Per antenna RSSI of last
++								  * received data frame.
++								  */
++	/* TX WLAN retry/failure statistics:
++	 * Separated for host requested frames and WLAN locally generated frames.
++	 * Include unicast frame only where the retries/failures can be counted.
++	 */
++	uint32			tx_pkts_total;		/**< # user frames sent successfully */
++	uint32			tx_pkts_retries;	/**< # user frames retries */
++	uint32			tx_pkts_fw_total;	/**< # FW generated sent successfully */
++	uint32			tx_pkts_fw_retries;	/**< # retries for FW generated frames */
++	uint32			tx_pkts_fw_retry_exhausted;	/**< # FW generated where a retry
++								 * was exhausted
++								 */
++	uint32			rx_pkts_retried;	/**< # rx with retry bit set */
++	uint32			tx_rate_fallback;	/**< lowest fallback TX rate */
++	/* Fields above this line are common to sta_info_t versions 4 and 5 */
++
++	uint32			rx_dur_total;	/* total user RX duration (estimated) */
++
++	chanspec_t		chanspec;       /** chanspec this sta is on */
++	uint16			PAD;
++	wl_rateset_args_t	rateset_adv;	/* rateset along with mcs index bitmap */
++	uint32			PAD;
++} sta_info_v4_t;
++
++/* Note: Version 4 is the latest version of sta_info_t.  Version 5 is abandoned.
++ * Please add new fields to version 4, not version 5.
++ */
++/* sta_info_t version 5 */
++typedef struct {
++	uint16			ver;		/**< version of this struct */
++	uint16			len;		/**< length in bytes of this structure */
++	uint16			cap;		/**< sta's advertised capabilities */
++	uint16			PAD;
++	uint32			flags;		/**< flags defined below */
++	uint32			idle;		/**< time since data pkt rx'd from sta */
++	struct ether_addr	ea;		/**< Station address */
++	uint16			PAD;
++	wl_rateset_t		rateset;	/**< rateset in use */
++	uint32			in;		/**< seconds elapsed since associated */
++	uint32			listen_interval_inms; /**< Min Listen interval in ms for this STA */
++	uint32			tx_pkts;	/**< # of user packets transmitted (unicast) */
++	uint32			tx_failures;	/**< # of user packets failed */
++	uint32			rx_ucast_pkts;	/**< # of unicast packets received */
++	uint32			rx_mcast_pkts;	/**< # of multicast packets received */
++	uint32			tx_rate;	/**< Rate used by last tx frame */
++	uint32			rx_rate;	/**< Rate of last successful rx frame */
++	uint32			rx_decrypt_succeeds;	/**< # of packet decrypted successfully */
++	uint32			rx_decrypt_failures;	/**< # of packet decrypted unsuccessfully */
++	uint32			tx_tot_pkts;	/**< # of user tx pkts (ucast + mcast) */
++	uint32			rx_tot_pkts;	/**< # of data packets recvd (uni + mcast) */
++	uint32			tx_mcast_pkts;	/**< # of mcast pkts txed */
++	uint64			tx_tot_bytes;	/**< data bytes txed (ucast + mcast) */
++	uint64			rx_tot_bytes;	/**< data bytes recvd (ucast + mcast) */
++	uint64			tx_ucast_bytes;	/**< data bytes txed (ucast) */
++	uint64			tx_mcast_bytes;	/**< # data bytes txed (mcast) */
++	uint64			rx_ucast_bytes;	/**< data bytes recvd (ucast) */
++	uint64			rx_mcast_bytes;	/**< data bytes recvd (mcast) */
++	int8			rssi[WL_STA_ANT_MAX]; /**< average rssi per antenna
++							* of data frames
++							*/
++	int8			nf[WL_STA_ANT_MAX];	/**< per antenna noise floor */
++	uint16			aid;			/**< association ID */
++	uint16			ht_capabilities;	/**< advertised ht caps */
++	uint16			vht_flags;		/**< converted vht flags */
++	uint16			PAD;
++	uint32			tx_pkts_retried;	/**< # of frames where a retry was
++							 * necessary
++							 */
++	uint32			tx_pkts_retry_exhausted; /**< # of user frames where a retry
++							  * was exhausted
++							  */
++	int8			rx_lastpkt_rssi[WL_STA_ANT_MAX]; /**< Per antenna RSSI of last
++								  * received data frame.
++								  */
++	/* TX WLAN retry/failure statistics:
++	 * Separated for host requested frames and WLAN locally generated frames.
++	 * Include unicast frame only where the retries/failures can be counted.
++	 */
++	uint32			tx_pkts_total;		/**< # user frames sent successfully */
++	uint32			tx_pkts_retries;	/**< # user frames retries */
++	uint32			tx_pkts_fw_total;	/**< # FW generated sent successfully */
++	uint32			tx_pkts_fw_retries;	/**< # retries for FW generated frames */
++	uint32			tx_pkts_fw_retry_exhausted;	/**< # FW generated where a retry
++								 * was exhausted
++								 */
++	uint32			rx_pkts_retried;	/**< # rx with retry bit set */
++	uint32			tx_rate_fallback;	/**< lowest fallback TX rate */
++	/* Fields above this line are common to sta_info_t versions 4 and 5 */
++
++	chanspec_t		chanspec;       /** chanspec this sta is on */
++	uint16			PAD;
++	wl_rateset_args_t	rateset_adv;	/* rateset along with mcs index bitmap */
++} sta_info_v5_t;
++
++#define WL_OLD_STAINFO_SIZE	OFFSETOF(sta_info_t, tx_tot_pkts)
++
++#define WL_STA_VER_4		4
++#define WL_STA_VER_5		5
++#define WL_STA_VER		WL_STA_VER_4
++
++#define SWDIV_STATS_VERSION_2 2
++#define SWDIV_STATS_CURRENT_VERSION SWDIV_STATS_VERSION_2
++
++struct wlc_swdiv_stats_v1 {
++	uint32 auto_en;
++	uint32 active_ant;
++	uint32 rxcount;
++	int32 avg_snr_per_ant0;
++	int32 avg_snr_per_ant1;
++	int32 avg_snr_per_ant2;
++	uint32 swap_ge_rxcount0;
++	uint32 swap_ge_rxcount1;
++	uint32 swap_ge_snrthresh0;
++	uint32 swap_ge_snrthresh1;
++	uint32 swap_txfail0;
++	uint32 swap_txfail1;
++	uint32 swap_timer0;
++	uint32 swap_timer1;
++	uint32 swap_alivecheck0;
++	uint32 swap_alivecheck1;
++	uint32 rxcount_per_ant0;
++	uint32 rxcount_per_ant1;
++	uint32 acc_rxcount;
++	uint32 acc_rxcount_per_ant0;
++	uint32 acc_rxcount_per_ant1;
++	uint32 tx_auto_en;
++	uint32 tx_active_ant;
++	uint32 rx_policy;
++	uint32 tx_policy;
++	uint32 cell_policy;
++	uint32 swap_snrdrop0;
++	uint32 swap_snrdrop1;
++	uint32 mws_antsel_ovr_tx;
++	uint32 mws_antsel_ovr_rx;
++	uint8 swap_trig_event_id;
++};
++
++struct wlc_swdiv_stats_v2 {
++	uint16	version;	/* version of the structure
++						* as defined by SWDIV_STATS_CURRENT_VERSION
++						*/
++	uint16	length;		/* length of the entire structure */
++	uint32 auto_en;
++	uint32 active_ant;
++	uint32 rxcount;
++	int32 avg_snr_per_ant0;
++	int32 avg_snr_per_ant1;
++	int32 avg_snr_per_ant2;
++	uint32 swap_ge_rxcount0;
++	uint32 swap_ge_rxcount1;
++	uint32 swap_ge_snrthresh0;
++	uint32 swap_ge_snrthresh1;
++	uint32 swap_txfail0;
++	uint32 swap_txfail1;
++	uint32 swap_timer0;
++	uint32 swap_timer1;
++	uint32 swap_alivecheck0;
++	uint32 swap_alivecheck1;
++	uint32 rxcount_per_ant0;
++	uint32 rxcount_per_ant1;
++	uint32 acc_rxcount;
++	uint32 acc_rxcount_per_ant0;
++	uint32 acc_rxcount_per_ant1;
++	uint32 tx_auto_en;
++	uint32 tx_active_ant;
++	uint32 rx_policy;
++	uint32 tx_policy;
++	uint32 cell_policy;
++	uint32 swap_snrdrop0;
++	uint32 swap_snrdrop1;
++	uint32 mws_antsel_ovr_tx;
++	uint32 mws_antsel_ovr_rx;
++	uint32 swap_trig_event_id;
++};
++
++#define	WLC_NUMRATES	16	/**< max # of rates in a rateset */
++
++/**Used to get specific STA parameters */
++typedef struct {
++	uint32	val;
++	struct ether_addr ea;
++	uint16	PAD;
++} scb_val_t;
++
++/**Used by iovar versions of some ioctls, i.e. WLC_SCB_AUTHORIZE et al */
++typedef struct {
++	uint32 code;
++	scb_val_t ioctl_args;
++} authops_t;
++
++/** channel encoding */
++typedef struct channel_info {
++	int32 hw_channel;
++	int32 target_channel;
++	int32 scan_channel;
++} channel_info_t;
++
++/** For ioctls that take a list of MAC addresses */
++typedef struct maclist {
++	uint32 count;			/**< number of MAC addresses */
++	struct ether_addr ea[1];	/**< variable length array of MAC addresses */
++} maclist_t;
++
++/**get pkt count struct passed through ioctl */
++typedef struct get_pktcnt {
++	uint32 rx_good_pkt;
++	uint32 rx_bad_pkt;
++	uint32 tx_good_pkt;
++	uint32 tx_bad_pkt;
++	uint32 rx_ocast_good_pkt; /**< unicast packets destined for others */
++} get_pktcnt_t;
++
++/* NINTENDO2 */
++#define LQ_IDX_MIN              0
++#define LQ_IDX_MAX              1
++#define LQ_IDX_AVG              2
++#define LQ_IDX_SUM              2
++#define LQ_IDX_LAST             3
++#define LQ_STOP_MONITOR         0
++#define LQ_START_MONITOR        1
++
++/** Get averages RSSI, Rx PHY rate and SNR values */
++/* Link Quality */
++typedef struct {
++	int32 rssi[LQ_IDX_LAST];  /**< Array to keep min, max, avg rssi */
++	int32 snr[LQ_IDX_LAST];   /**< Array to keep min, max, avg snr */
++	int32 isvalid;            /**< Flag indicating whether above data is valid */
++} wl_lq_t;
++
++typedef enum wl_wakeup_reason_type {
++	LCD_ON = 1,
++	LCD_OFF,
++	DRC1_WAKE,
++	DRC2_WAKE,
++	REASON_LAST
++} wl_wr_type_t;
++
++typedef struct {
++	/** Unique filter id */
++	uint32	id;
++	/** stores the reason for the last wake up */
++	uint8	reason;
++	uint8	PAD[3];
++} wl_wr_t;
++
++/** Get MAC specific rate histogram command */
++typedef struct {
++	struct	ether_addr ea;	/**< MAC Address */
++	uint8	ac_cat;	/**< Access Category */
++	uint8	num_pkts;	/**< Number of packet entries to be averaged */
++} wl_mac_ratehisto_cmd_t;
++/** Get MAC rate histogram response */
++typedef struct {
++	uint32	rate[DOT11_RATE_MAX + 1];	/**< Rates */
++	uint32	mcs[WL_RATESET_SZ_HT_IOCTL * WL_TX_CHAINS_MAX];	/**< MCS counts */
++	uint32	vht[WL_RATESET_SZ_VHT_MCS][WL_TX_CHAINS_MAX];	/**< VHT counts */
++	uint32	tsf_timer[2][2];	/**< Start and End time for 8bytes value */
++	uint32	prop11n_mcs[WLC_11N_LAST_PROP_MCS - WLC_11N_FIRST_PROP_MCS + 1]; /** MCS counts */
++} wl_mac_ratehisto_res_t;
++
++/* sta_info ecounters */
++typedef struct {
++	struct ether_addr   ea;				/* Station MAC addr */
++	struct ether_addr   BSSID;			/* BSSID of the BSS */
++	uint32              tx_pkts_fw_total;		/* # FW generated sent successfully */
++	uint32              tx_pkts_fw_retries;		/* # retries for FW generated frames */
++	uint32              tx_pkts_fw_retry_exhausted;	/* # FW generated which
++							 * failed after retry
++							 */
++} sta_info_ecounters_t;
++
++#define STAMON_MODULE_VER		1
++
++/**Linux network driver ioctl encoding */
++typedef struct wl_ioctl {
++	uint32 cmd;	/**< common ioctl definition */
++	void *buf;	/**< pointer to user buffer */
++	uint32 len;	/**< length of user buffer */
++	uint8 set;		/**< 1=set IOCTL; 0=query IOCTL */
++	uint32 used;	/**< bytes read or written (optional) */
++	uint32 needed;	/**< bytes needed (optional) */
++} wl_ioctl_t;
++
++#ifdef CONFIG_COMPAT
++typedef struct compat_wl_ioctl {
++	uint32 cmd;	/**< common ioctl definition */
++	uint32 buf;	/**< pointer to user buffer */
++	uint32 len;	/**< length of user buffer */
++	uint8 set;		/**< 1=set IOCTL; 0=query IOCTL */
++	uint32 used;	/**< bytes read or written (optional) */
++	uint32 needed;	/**< bytes needed (optional) */
++} compat_wl_ioctl_t;
++#endif /* CONFIG_COMPAT */
++
++#define WL_NUM_RATES_CCK		4 /**< 1, 2, 5.5, 11 Mbps */
++#define WL_NUM_RATES_OFDM		8 /**< 6, 9, 12, 18, 24, 36, 48, 54 Mbps SISO/CDD */
++#define WL_NUM_RATES_MCS_1STREAM	8 /**< MCS 0-7 1-stream rates - SISO/CDD/STBC/MCS */
++#define WL_NUM_RATES_EXTRA_VHT		2 /**< Additional VHT 11AC rates */
++#define WL_NUM_RATES_VHT		10
++#define WL_NUM_RATES_MCS32		1
++
++
++/*
++ * Structure for passing hardware and software
++ * revision info up from the driver.
++ */
++typedef struct wlc_rev_info {
++	uint32		vendorid;	/**< PCI vendor id */
++	uint32		deviceid;	/**< device id of chip */
++	uint32		radiorev;	/**< radio revision */
++	uint32		chiprev;	/**< chip revision */
++	uint32		corerev;	/**< core revision */
++	uint32		boardid;	/**< board identifier (usu. PCI sub-device id) */
++	uint32		boardvendor;	/**< board vendor (usu. PCI sub-vendor id) */
++	uint32		boardrev;	/**< board revision */
++	uint32		driverrev;	/**< driver version */
++	uint32		ucoderev;	/**< microcode version */
++	uint32		bus;		/**< bus type */
++	uint32		chipnum;	/**< chip number */
++	uint32		phytype;	/**< phy type */
++	uint32		phyrev;		/**< phy revision */
++	uint32		anarev;		/**< anacore rev */
++	uint32		chippkg;	/**< chip package info */
++	uint32		nvramrev;	/**< nvram revision number */
++	uint32		phyminorrev;	/**< phy minor rev */
++	uint32		coreminorrev;	/**< core minor rev */
++	uint32		drvrev_major;	/**< driver version: major */
++	uint32		drvrev_minor;	/**< driver version: minor */
++	uint32		drvrev_rc;	/**< driver version: rc */
++	uint32		drvrev_rc_inc;	/**< driver version: rc incremental */
++} wlc_rev_info_t;
++
++#define WL_REV_INFO_LEGACY_LENGTH	48
++
++#define WL_BRAND_MAX 10
++typedef struct wl_instance_info {
++	uint32 instance;
++	int8 brand[WL_BRAND_MAX];
++	int8 PAD[4-(WL_BRAND_MAX%4)];
++} wl_instance_info_t;
++
++/** structure to change size of tx fifo */
++typedef struct wl_txfifo_sz {
++	uint16	magic;
++	uint16	fifo;
++	uint16	size;
++} wl_txfifo_sz_t;
++
++/* Transfer info about an IOVar from the driver */
++/**Max supported IOV name size in bytes, + 1 for nul termination */
++#define WLC_IOV_NAME_LEN	(32 + 1)
++
++typedef struct wlc_iov_trx_s {
++	uint8 module;
++	uint8 type;
++	char name[WLC_IOV_NAME_LEN];
++} wlc_iov_trx_t;
++
++/** bump this number if you change the ioctl interface */
++#define WLC_IOCTL_VERSION	2
++#define WLC_IOCTL_VERSION_LEGACY_IOTYPES	1
++/* ifdef EXT_STA */
++typedef struct _wl_assoc_result {
++	ulong associated;
++	ulong NDIS_auth;
++	ulong NDIS_infra;
++} wl_assoc_result_t;
++/* EXT_STA */
++
++#define WL_PHY_PAVARS_LEN	32	/**< Phytype, Bandrange, chain, a[0], b[0], c[0], d[0] .. */
++
++
++#define WL_PHY_PAVAR_VER	1	/**< pavars version */
++#define WL_PHY_PAVARS2_NUM	3	/**< a1, b0, b1 */
++typedef struct wl_pavars2 {
++	uint16 ver;		/**< version of this struct */
++	uint16 len;		/**< len of this structure */
++	uint16 inuse;		/**< driver return 1 for a1,b0,b1 in current band range */
++	uint16 phy_type;	/**< phy type */
++	uint16 bandrange;
++	uint16 chain;
++	uint16 inpa[WL_PHY_PAVARS2_NUM];	/**< phy pavars for one band range */
++} wl_pavars2_t;
++
++typedef struct wl_po {
++	uint16	phy_type;	/**< Phy type */
++	uint16	band;
++	uint16	cckpo;
++	uint16	PAD;
++	uint32	ofdmpo;
++	uint16	mcspo[8];
++} wl_po_t;
++
++#define WL_NUM_RPCALVARS 5	/**< number of rpcal vars */
++
++typedef struct wl_rpcal {
++	uint16 value;
++	uint16 update;
++} wl_rpcal_t;
++
++#define WL_NUM_RPCALPHASEVARS 5	/* number of rpcal phase vars */
++
++typedef struct wl_rpcal_phase {
++	uint16 value;
++	uint16 update;
++} wl_rpcal_phase_t;
++
++typedef struct wl_aci_args {
++	int32 enter_aci_thresh; /* Trigger level to start detecting ACI */
++	int32 exit_aci_thresh; /* Trigger level to exit ACI mode */
++	int32 usec_spin; /* microsecs to delay between rssi samples */
++	int32 glitch_delay; /* interval between ACI scans when glitch count is consistently high */
++	uint16 nphy_adcpwr_enter_thresh;	/**< ADC power to enter ACI mitigation mode */
++	uint16 nphy_adcpwr_exit_thresh;	/**< ADC power to exit ACI mitigation mode */
++	uint16 nphy_repeat_ctr;		/**< Number of tries per channel to compute power */
++	uint16 nphy_num_samples;	/**< Number of samples to compute power on one channel */
++	uint16 nphy_undetect_window_sz;	/**< num of undetects to exit ACI Mitigation mode */
++	uint16 nphy_b_energy_lo_aci;	/**< low ACI power energy threshold for bphy */
++	uint16 nphy_b_energy_md_aci;	/**< mid ACI power energy threshold for bphy */
++	uint16 nphy_b_energy_hi_aci;	/**< high ACI power energy threshold for bphy */
++	uint16 nphy_noise_noassoc_glitch_th_up; /**< wl interference 4 */
++	uint16 nphy_noise_noassoc_glitch_th_dn;
++	uint16 nphy_noise_assoc_glitch_th_up;
++	uint16 nphy_noise_assoc_glitch_th_dn;
++	uint16 nphy_noise_assoc_aci_glitch_th_up;
++	uint16 nphy_noise_assoc_aci_glitch_th_dn;
++	uint16 nphy_noise_assoc_enter_th;
++	uint16 nphy_noise_noassoc_enter_th;
++	uint16 nphy_noise_assoc_rx_glitch_badplcp_enter_th;
++	uint16 nphy_noise_noassoc_crsidx_incr;
++	uint16 nphy_noise_assoc_crsidx_incr;
++	uint16 nphy_noise_crsidx_decr;
++} wl_aci_args_t;
++
++#define WL_ACI_ARGS_LEGACY_LENGTH	16	/**< bytes of pre NPHY aci args */
++#define	WL_SAMPLECOLLECT_T_VERSION	2	/**< version of wl_samplecollect_args_t struct */
++typedef struct wl_samplecollect_args {
++	/* version 0 fields */
++	uint8 coll_us;
++	uint8 PAD[3];
++	int32 cores;
++	/* add'l version 1 fields */
++	uint16 version;     /**< see definition of WL_SAMPLECOLLECT_T_VERSION */
++	uint16 length;      /**< length of entire structure */
++	int8 trigger;
++	uint8 PAD;
++	uint16 timeout;
++	uint16 mode;
++	uint16 PAD;
++	uint32 pre_dur;
++	uint32 post_dur;
++	uint8 gpio_sel;
++	uint8 downsamp;
++	uint8 be_deaf;
++	uint8 agc;		/**< loop from init gain and going down */
++	uint8 filter;		/**< override high pass corners to lowest */
++	/* add'l version 2 fields */
++	uint8 trigger_state;
++	uint8 module_sel1;
++	uint8 module_sel2;
++	uint16 nsamps;
++	uint16 PAD;
++	int32 bitStart;
++	uint32 gpioCapMask;
++	uint8 gpio_collection;
++	uint8 PAD[3];
++} wl_samplecollect_args_t;
++
++#define	WL_SAMPLEDATA_T_VERSION		1	/**< version of wl_samplecollect_args_t struct */
++/* version for unpacked sample data, int16 {(I,Q),Core(0..N)} */
++#define	WL_SAMPLEDATA_T_VERSION_SPEC_AN 2
++
++typedef struct wl_sampledata {
++	uint16 version;	/**< structure version */
++	uint16 size;	/**< size of structure */
++	uint16 tag;	/**< Header/Data */
++	uint16 length;	/**< data length */
++	uint32 flag;	/**< bit def */
++} wl_sampledata_t;
++
++
++/* WL_OTA START */
++/* OTA Test Status */
++enum {
++	WL_OTA_TEST_IDLE = 0,		/**< Default Idle state */
++	WL_OTA_TEST_ACTIVE = 1,		/**< Test Running */
++	WL_OTA_TEST_SUCCESS = 2,	/**< Successfully Finished Test */
++	WL_OTA_TEST_FAIL = 3		/**< Test Failed in the Middle */
++};
++
++/* OTA SYNC Status */
++enum {
++	WL_OTA_SYNC_IDLE = 0,	/**< Idle state */
++	WL_OTA_SYNC_ACTIVE = 1,	/**< Waiting for Sync */
++	WL_OTA_SYNC_FAIL = 2	/**< Sync pkt not recieved */
++};
++
++/* Various error states dut can get stuck during test */
++enum {
++	WL_OTA_SKIP_TEST_CAL_FAIL = 1,		/**< Phy calibration failed */
++	WL_OTA_SKIP_TEST_SYNCH_FAIL = 2,	/**< Sync Packet not recieved */
++	WL_OTA_SKIP_TEST_FILE_DWNLD_FAIL = 3,	/**< Cmd flow file download failed */
++	WL_OTA_SKIP_TEST_NO_TEST_FOUND = 4,	/**< No test found in Flow file */
++	WL_OTA_SKIP_TEST_WL_NOT_UP = 5,		/**< WL UP failed */
++	WL_OTA_SKIP_TEST_UNKNOWN_CALL		/**< Unintentional scheduling on ota test */
++};
++
++/* Differentiator for ota_tx and ota_rx */
++enum {
++	WL_OTA_TEST_TX = 0,		/**< ota_tx */
++	WL_OTA_TEST_RX = 1,		/**< ota_rx */
++};
++
++/* Catch 3 modes of operation: 20Mhz, 40Mhz, 20 in 40 Mhz */
++enum {
++	WL_OTA_TEST_BW_20_IN_40MHZ = 0,		/**< 20 in 40 operation */
++	WL_OTA_TEST_BW_20MHZ = 1,		/**< 20 Mhz operation */
++	WL_OTA_TEST_BW_40MHZ = 2,		/**< full 40Mhz operation */
++	WL_OTA_TEST_BW_80MHZ = 3		/* full 80Mhz operation */
++};
++#define HT_MCS_INUSE	0x00000080	/* HT MCS in use,indicates b0-6 holds an mcs */
++#define VHT_MCS_INUSE	0x00000100	/* VHT MCS in use,indicates b0-6 holds an mcs */
++#define OTA_RATE_MASK 0x0000007f	/* rate/mcs value */
++#define OTA_STF_SISO	0
++#define OTA_STF_CDD		1
++#define OTA_STF_STBC	2
++#define OTA_STF_SDM		3
++
++typedef struct ota_rate_info {
++	uint8 rate_cnt;					/**< Total number of rates */
++	uint8 PAD;
++	uint16 rate_val_mbps[WL_OTA_TEST_MAX_NUM_RATE];	/**< array of rates from 1mbps to 130mbps */
++							/**< for legacy rates : ratein mbps * 2 */
++							/**< for HT rates : mcs index */
++} ota_rate_info_t;
++
++typedef struct ota_power_info {
++	int8 pwr_ctrl_on;	/**< power control on/off */
++	int8 start_pwr;		/**< starting power/index */
++	int8 delta_pwr;		/**< delta power/index */
++	int8 end_pwr;		/**< end power/index */
++} ota_power_info_t;
++
++typedef struct ota_packetengine {
++	uint16 delay;           /**< Inter-packet delay */
++				/**< for ota_tx, delay is tx ifs in micro seconds */
++				/* for ota_rx, delay is wait time in milliseconds */
++	uint16 nframes;         /**< Number of frames */
++	uint16 length;          /**< Packet length */
++} ota_packetengine_t;
++
++/*
++ * OTA txant/rxant parameter
++ *    bit7-4: 4 bits swdiv_tx/rx_policy bitmask, specify antenna-policy for SW diversity
++ *    bit3-0: 4 bits TxCore bitmask, specify cores used for transmit frames
++ *            (maximum spatial expansion)
++ */
++#define WL_OTA_TEST_ANT_MASK	0xF0
++#define WL_OTA_TEST_CORE_MASK	0x0F
++
++/* OTA txant/rxant 'ant_mask' field; map to Tx/Rx antenna policy for SW diversity */
++enum {
++	WL_OTA_TEST_FORCE_ANT0 = 0x10,	/* force antenna to Ant 0 */
++	WL_OTA_TEST_FORCE_ANT1 = 0x20,	/* force antenna to Ant 1 */
++};
++
++/* antenna/core fields access */
++#define WL_OTA_TEST_GET_ANT(_txant) ((_txant) & WL_OTA_TEST_ANT_MASK)
++#define WL_OTA_TEST_GET_CORE(_txant) ((_txant) & WL_OTA_TEST_CORE_MASK)
++
++/** Test info vector */
++typedef struct wl_ota_test_args {
++	uint8 cur_test;			/**< test phase */
++	uint8 chan;			/**< channel */
++	uint8 bw;			/**< bandwidth */
++	uint8 control_band;		/**< control band */
++	uint8 stf_mode;			/**< stf mode */
++	uint8 PAD;
++	ota_rate_info_t rt_info;	/**< Rate info */
++	ota_packetengine_t pkteng;	/**< packeteng info */
++	uint8 txant;			/**< tx antenna */
++	uint8 rxant;			/**< rx antenna */
++	ota_power_info_t pwr_info;	/**< power sweep info */
++	uint8 wait_for_sync;		/**< wait for sync or not */
++	uint8 ldpc;
++	uint8 sgi;
++	uint8 PAD;
++	/* Update WL_OTA_TESTVEC_T_VERSION for adding new members to this structure */
++} wl_ota_test_args_t;
++
++#define WL_OTA_TESTVEC_T_VERSION		1	/* version of wl_ota_test_vector_t struct */
++typedef struct wl_ota_test_vector {
++	uint16 version;
++	wl_ota_test_args_t test_arg[WL_OTA_TEST_MAX_NUM_SEQ];	/**< Test argument struct */
++	uint16 test_cnt;					/**< Total no of test */
++	uint8 file_dwnld_valid;					/**< File successfully downloaded */
++	uint8 sync_timeout;					/**< sync packet timeout */
++	int8 sync_fail_action;					/**< sync fail action */
++	struct ether_addr sync_mac;				/**< macaddress for sync pkt */
++	struct ether_addr tx_mac;				/**< macaddress for tx */
++	struct ether_addr rx_mac;				/**< macaddress for rx */
++	int8 loop_test;					/**< dbg feature to loop the test */
++	uint16 test_rxcnt;
++	/* Update WL_OTA_TESTVEC_T_VERSION for adding new members to this structure */
++} wl_ota_test_vector_t;
++
++
++/** struct copied back form dongle to host to query the status */
++typedef struct wl_ota_test_status {
++	int16 cur_test_cnt;		/**< test phase */
++	int8 skip_test_reason;		/**< skip test reasoin */
++	uint8 PAD;
++	wl_ota_test_args_t test_arg;	/**< cur test arg details */
++	uint16 test_cnt;		/**< total no of test downloaded */
++	uint8 file_dwnld_valid;		/**< file successfully downloaded ? */
++	uint8 sync_timeout;		/**< sync timeout */
++	int8 sync_fail_action;		/**< sync fail action */
++	struct ether_addr sync_mac;	/**< macaddress for sync pkt */
++	struct ether_addr tx_mac;	/**< tx mac address */
++	struct ether_addr rx_mac;	/**< rx mac address */
++	uint8  test_stage;		/**< check the test status */
++	int8 loop_test;			/**< Debug feature to puts test enfine in a loop */
++	uint8 sync_status;		/**< sync status */
++} wl_ota_test_status_t;
++
++/* FOR ioctl that take the sta monitor information */
++typedef struct stamon_data {
++	struct ether_addr  ea;
++	uint8 PAD[2];
++	int32 rssi;
++} stamon_data_t;
++
++typedef struct stamon_info {
++	int32 version;
++	uint32 count;
++	stamon_data_t sta_data[1];
++} stamon_info_t;
++
++typedef struct wl_ota_rx_rssi {
++	uint16	pktcnt;		/* Pkt count used for this rx test */
++	chanspec_t chanspec;	/* Channel info on which the packets are received */
++	int16	rssi;		/* Average RSSI of the first 50% packets received */
++} wl_ota_rx_rssi_t;
++
++#define	WL_OTARSSI_T_VERSION		1	/* version of wl_ota_test_rssi_t struct */
++#define WL_OTA_TEST_RSSI_FIXED_SIZE	OFFSETOF(wl_ota_test_rssi_t, rx_rssi)
++
++typedef struct wl_ota_test_rssi {
++	uint8 version;
++	uint8	testcnt;		/* total measured RSSI values, valid on output only */
++	wl_ota_rx_rssi_t rx_rssi[1]; /* Variable length array of wl_ota_rx_rssi_t */
++} wl_ota_test_rssi_t;
++
++/* WL_OTA END */
++
++/**wl_radar_args_t */
++typedef struct {
++	int32 npulses;	/**< required number of pulses at n * t_int */
++	int32 ncontig;	/**< required number of pulses at t_int */
++	int32 min_pw;	/**< minimum pulse width (20 MHz clocks) */
++	int32 max_pw;	/**< maximum pulse width (20 MHz clocks) */
++	uint16 thresh0;	/**< Radar detection, thresh 0 */
++	uint16 thresh1;	/**< Radar detection, thresh 1 */
++	uint16 blank;	/**< Radar detection, blank control */
++	uint16 fmdemodcfg;	/**< Radar detection, fmdemod config */
++	int32 npulses_lp;  /**< Radar detection, minimum long pulses */
++	int32 min_pw_lp; /**< Minimum pulsewidth for long pulses */
++	int32 max_pw_lp; /**< Maximum pulsewidth for long pulses */
++	int32 min_fm_lp; /**< Minimum fm for long pulses */
++	int32 max_span_lp;  /**< Maximum deltat for long pulses */
++	int32 min_deltat; /**< Minimum spacing between pulses */
++	int32 max_deltat; /**< Maximum spacing between pulses */
++	uint16 autocorr;	/**< Radar detection, autocorr on or off */
++	uint16 st_level_time;	/**< Radar detection, start_timing level */
++	uint16 t2_min; /**< minimum clocks needed to remain in state 2 */
++	uint8 PAD[2];
++	uint32 version; /**< version */
++	uint32 fra_pulse_err;	/**< sample error margin for detecting French radar pulsed */
++	int32 npulses_fra;  /**< Radar detection, minimum French pulses set */
++	int32 npulses_stg2;  /**< Radar detection, minimum staggered-2 pulses set */
++	int32 npulses_stg3;  /**< Radar detection, minimum staggered-3 pulses set */
++	uint16 percal_mask;	/**< defines which period cal is masked from radar detection */
++	uint8 PAD[2];
++	int32 quant;	/**< quantization resolution to pulse positions */
++	uint32 min_burst_intv_lp;	/**< minimum burst to burst interval for bin3 radar */
++	uint32 max_burst_intv_lp;	/**< maximum burst to burst interval for bin3 radar */
++	int32 nskip_rst_lp;	/**< number of skipped pulses before resetting lp buffer */
++	int32 max_pw_tol; /* maximum tolerance allowd in detected pulse width for radar detection */
++	uint16 feature_mask; /**< 16-bit mask to specify enabled features */
++	uint16 thresh0_sc;	/**< Radar detection, thresh 0 */
++	uint16 thresh1_sc;	/**< Radar detection, thresh 1 */
++	uint8 PAD[2];
++} wl_radar_args_t;
++
++#define WL_RADAR_ARGS_VERSION 2
++
++typedef struct {
++	uint32 version; /**< version */
++	uint16 thresh0_20_lo;	/**< Radar detection, thresh 0 (range 5250-5350MHz) for BW 20MHz */
++	uint16 thresh1_20_lo;	/**< Radar detection, thresh 1 (range 5250-5350MHz) for BW 20MHz */
++	uint16 thresh0_40_lo;	/**< Radar detection, thresh 0 (range 5250-5350MHz) for BW 40MHz */
++	uint16 thresh1_40_lo;	/**< Radar detection, thresh 1 (range 5250-5350MHz) for BW 40MHz */
++	uint16 thresh0_80_lo;	/**< Radar detection, thresh 0 (range 5250-5350MHz) for BW 80MHz */
++	uint16 thresh1_80_lo;	/**< Radar detection, thresh 1 (range 5250-5350MHz) for BW 80MHz */
++	uint16 thresh0_20_hi;	/**< Radar detection, thresh 0 (range 5470-5725MHz) for BW 20MHz */
++	uint16 thresh1_20_hi;	/**< Radar detection, thresh 1 (range 5470-5725MHz) for BW 20MHz */
++	uint16 thresh0_40_hi;	/**< Radar detection, thresh 0 (range 5470-5725MHz) for BW 40MHz */
++	uint16 thresh1_40_hi;	/**< Radar detection, thresh 1 (range 5470-5725MHz) for BW 40MHz */
++	uint16 thresh0_80_hi;	/**< Radar detection, thresh 0 (range 5470-5725MHz) for BW 80MHz */
++	uint16 thresh1_80_hi;	/**< Radar detection, thresh 1 (range 5470-5725MHz) for BW 80MHz */
++	uint16 thresh0_160_lo;	/**< Radar detection, thresh 0 (range 5250-5350MHz) for BW 160MHz */
++	uint16 thresh1_160_lo;	/**< Radar detection, thresh 1 (range 5250-5350MHz) for BW 160MHz */
++	uint16 thresh0_160_hi;	/**< Radar detection, thresh 0 (range 5470-5725MHz) for BW 160MHz */
++	uint16 thresh1_160_hi;	/**< Radar detection, thresh 1 (range 5470-5725MHz) for BW 160MHz */
++} wl_radar_thr_t;
++
++typedef struct {
++	uint32 version; /* version */
++	uint16 thresh0_sc_20_lo;
++	uint16 thresh1_sc_20_lo;
++	uint16 thresh0_sc_40_lo;
++	uint16 thresh1_sc_40_lo;
++	uint16 thresh0_sc_80_lo;
++	uint16 thresh1_sc_80_lo;
++	uint16 thresh0_sc_20_hi;
++	uint16 thresh1_sc_20_hi;
++	uint16 thresh0_sc_40_hi;
++	uint16 thresh1_sc_40_hi;
++	uint16 thresh0_sc_80_hi;
++	uint16 thresh1_sc_80_hi;
++	uint16 fc_varth_sb;
++	uint16 fc_varth_bin5_sb;
++	uint16 notradar_enb;
++	uint16 max_notradar_lp;
++	uint16 max_notradar;
++	uint16 max_notradar_lp_sc;
++	uint16 max_notradar_sc;
++	uint16 highpow_war_enb;
++	uint16 highpow_sp_ratio;	//unit is 0.5
++} wl_radar_thr2_t;
++
++#define WL_RADAR_THR_VERSION	2
++
++typedef struct {
++	uint32 ver;
++	uint32 len;
++	int32  rssi_th[3];
++	uint8  rssi_gain_80[4];
++	uint8  rssi_gain_160[4];
++} wl_dyn_switch_th_t;
++
++#define WL_PHY_DYN_SWITCH_TH_VERSION	1
++
++/** RSSI per antenna */
++typedef struct {
++	uint32	version;		/**< version field */
++	uint32	count;			/**< number of valid antenna rssi */
++	int8 rssi_ant[WL_RSSI_ANT_MAX];	/**< rssi per antenna */
++} wl_rssi_ant_t;
++
++/* SNR per antenna */
++typedef struct {
++	uint32  version;				/* version field */
++	uint32  count;					/* number of valid antenna snr */
++	int8 snr_ant[WL_RSSI_ANT_MAX];	/* snr per antenna */
++} wl_snr_ant_t;
++
++
++/** data structure used in 'dfs_status' wl interface, which is used to query dfs status */
++typedef struct {
++	uint32 state;		/**< noted by WL_DFS_CACSTATE_XX. */
++	uint32 duration;		/**< time spent in ms in state. */
++	/**
++	 * as dfs enters ISM state, it removes the operational channel from quiet channel
++	 * list and notes the channel in channel_cleared. set to 0 if no channel is cleared
++	 */
++	chanspec_t chanspec_cleared;
++	/** chanspec cleared used to be a uint32, add another to uint16 to maintain size */
++	uint16 pad;
++} wl_dfs_status_t;
++
++typedef struct {
++	uint32 state;		/* noted by WL_DFS_CACSTATE_XX */
++	uint32 duration;		/* time spent in ms in state */
++	chanspec_t chanspec;	/* chanspec of this core */
++	chanspec_t chanspec_last_cleared; /* chanspec last cleared for operation by scanning */
++	uint16 sub_type;	/* currently just the index of the core or the respective PLL */
++	uint16 pad;
++} wl_dfs_sub_status_t;
++
++#define WL_DFS_STATUS_ALL_VERSION	(1)
++typedef struct {
++	uint16 version;		/* version field; current max version 1 */
++	uint16 num_sub_status;
++	wl_dfs_sub_status_t  dfs_sub_status[1]; /* struct array of length num_sub_status */
++} wl_dfs_status_all_t;
++
++#define WL_DFS_AP_MOVE_VERSION	(1)
++
++struct wl_dfs_ap_move_status_v1 {
++	int16 dfs_status;	/* DFS scan status */
++	chanspec_t chanspec;	/* New AP Chanspec */
++	wl_dfs_status_t cac_status;	/* CAC status */
++};
++
++typedef struct wl_dfs_ap_move_status_v2 {
++	int8 version;            /* version field; current max version 1 */
++	int8 move_status;        /* DFS move status */
++	chanspec_t chanspec;     /* New AP Chanspec */
++	wl_dfs_status_all_t scan_status; /* status; see dfs_status_all for wl_dfs_status_all_t */
++} wl_dfs_ap_move_status_v2_t;
++
++#define WL_DFS_AP_MOVE_ABORT -1		/* Abort any dfs_ap_move in progress immediately */
++#define WL_DFS_AP_MOVE_STUNT -2		/* Stunt move but continue background CSA if in progress */
++
++
++/** data structure used in 'radar_status' wl interface, which is use to query radar det status */
++typedef struct {
++	uint8 detected;
++	uint8 PAD[3];
++	int32 count;
++	uint8 pretended;
++	uint8 PAD[3];
++	uint32 radartype;
++	uint32 timenow;
++	uint32 timefromL;
++	int32  lp_csect_single;
++	int32  detected_pulse_index;
++	int32  nconsecq_pulses;
++	chanspec_t ch;
++	uint8 PAD[2];
++	int32  pw[10];
++	int32  intv[10];
++	int32  fm[10];
++} wl_radar_status_t;
++
++#define NUM_PWRCTRL_RATES 12
++
++typedef struct {
++	uint8 txpwr_band_max[NUM_PWRCTRL_RATES];	/**< User set target */
++	uint8 txpwr_limit[NUM_PWRCTRL_RATES];		/**< reg and local power limit */
++	uint8 txpwr_local_max;				/**< local max according to the AP */
++	uint8 txpwr_local_constraint;			/**< local constraint according to the AP */
++	uint8 txpwr_chan_reg_max;			/**< Regulatory max for this channel */
++	uint8 txpwr_target[2][NUM_PWRCTRL_RATES];	/**< Latest target for 2.4 and 5 Ghz */
++	uint8 txpwr_est_Pout[2];			/**< Latest estimate for 2.4 and 5 Ghz */
++	uint8 txpwr_opo[NUM_PWRCTRL_RATES];		/**< On G phy, OFDM power offset */
++	uint8 txpwr_bphy_cck_max[NUM_PWRCTRL_RATES];	/**< Max CCK power for this band (SROM) */
++	uint8 txpwr_bphy_ofdm_max;			/**< Max OFDM power for this band (SROM) */
++	uint8 txpwr_aphy_max[NUM_PWRCTRL_RATES];	/**< Max power for A band (SROM) */
++	int8  txpwr_antgain[2];				/**< Ant gain for each band - from SROM */
++	uint8 txpwr_est_Pout_gofdm;			/**< Pwr estimate for 2.4 OFDM */
++} tx_power_legacy_t;
++
++#define WL_TX_POWER_RATES_LEGACY    45
++#define WL_TX_POWER_MCS20_FIRST         12
++#define WL_TX_POWER_MCS20_NUM           16
++#define WL_TX_POWER_MCS40_FIRST         28
++#define WL_TX_POWER_MCS40_NUM           17
++
++typedef struct {
++	uint32 flags;
++	chanspec_t chanspec;                 /**< txpwr report for this channel */
++	chanspec_t local_chanspec;           /**< channel on which we are associated */
++	uint8 local_max;                 /**< local max according to the AP */
++	uint8 local_constraint;              /**< local constraint according to the AP */
++	int8  antgain[2];                /**< Ant gain for each band - from SROM */
++	uint8 rf_cores;                  /**< count of RF Cores being reported */
++	uint8 est_Pout[4];                           /**< Latest tx power out estimate per RF
++							  * chain without adjustment
++							  */
++	uint8 est_Pout_cck;                          /**< Latest CCK tx power out estimate */
++	uint8 user_limit[WL_TX_POWER_RATES_LEGACY];  /**< User limit */
++	uint8 reg_limit[WL_TX_POWER_RATES_LEGACY];   /**< Regulatory power limit */
++	uint8 board_limit[WL_TX_POWER_RATES_LEGACY]; /**< Max power board can support (SROM) */
++	uint8 target[WL_TX_POWER_RATES_LEGACY];      /**< Latest target power */
++	uint8 PAD[2];
++} tx_power_legacy2_t;
++
++#define WL_NUM_2x2_ELEMENTS		4
++#define WL_NUM_3x3_ELEMENTS		6
++#define WL_NUM_4x4_ELEMENTS		10
++
++typedef struct {
++	uint16 ver;				/**< version of this struct */
++	uint16 len;				/**< length in bytes of this structure */
++	uint32 flags;
++	chanspec_t chanspec;			/**< txpwr report for this channel */
++	chanspec_t local_chanspec;		/**< channel on which we are associated */
++	uint32     buflen;			/**< ppr buffer length */
++	uint8      pprbuf[1];			/**< Latest target power buffer */
++} wl_txppr_t;
++
++#define WL_TXPPR_VERSION	1
++#define WL_TXPPR_LENGTH	(sizeof(wl_txppr_t))
++#define TX_POWER_T_VERSION	45
++/** number of ppr serialization buffers, it should be reg, board and target */
++#define WL_TXPPR_SER_BUF_NUM	(3)
++
++typedef struct chanspec_txpwr_max {
++	chanspec_t chanspec;   /**< chanspec */
++	uint8 txpwr_max;       /**< max txpwr in all the rates */
++	uint8 padding;
++} chanspec_txpwr_max_t;
++
++typedef struct  wl_chanspec_txpwr_max {
++	uint16 ver;			/**< version of this struct */
++	uint16 len;			/**< length in bytes of this structure */
++	uint32 count;		/**< number of elements of (chanspec, txpwr_max) pair */
++	chanspec_txpwr_max_t txpwr[1];	/**< array of (chanspec, max_txpwr) pair */
++} wl_chanspec_txpwr_max_t;
++
++#define WL_CHANSPEC_TXPWR_MAX_VER	1
++#define WL_CHANSPEC_TXPWR_MAX_LEN	(sizeof(wl_chanspec_txpwr_max_t))
++
++typedef struct tx_inst_power {
++	uint8 txpwr_est_Pout[2];			/**< Latest estimate for 2.4 and 5 Ghz */
++	uint8 txpwr_est_Pout_gofdm;			/**< Pwr estimate for 2.4 OFDM */
++} tx_inst_power_t;
++
++#define WL_NUM_TXCHAIN_MAX	4
++typedef struct wl_txchain_pwr_offsets {
++	int8 offset[WL_NUM_TXCHAIN_MAX];	/**< quarter dBm signed offset for each chain */
++} wl_txchain_pwr_offsets_t;
++
++/** maximum channels returned by the get valid channels iovar */
++#define WL_NUMCHANNELS		64
++#define WL_NUMCHANNELS_MANY_CHAN 10
++#define WL_ITER_LIMIT_MANY_CHAN 5
++
++#define WL_MIMO_PS_CFG_VERSION_1 1
++
++typedef struct wl_mimops_cfg {
++	uint8 version;
++	/* active_chains: 0 for all, 1 for 1 chain. */
++	uint8 active_chains;
++	/* static (0) or dynamic (1).or disabled (3) Mode applies only when active_chains = 0. */
++	uint8 mode;
++	/* bandwidth = Full (0), 20M (1), 40M (2), 80M (3). */
++	uint8 bandwidth;
++	uint8 applychangesafterlearning;
++	uint8 pad[3];
++} wl_mimops_cfg_t;
++
++/* This event is for tracing MIMO PS metrics snapshot calls.
++ * It is helpful to debug out-of-sync issue between
++ * ucode SHM values and FW snapshot calculation.
++ * It is part of the EVENT_LOG_TAG_MIMO_PS_TRACE.
++ */
++#define WL_MIMO_PS_METRICS_SNAPSHOT_TRACE_TYPE	0
++typedef struct wl_mimo_ps_metrics_snapshot_trace {
++	/* type field for this TLV: */
++	uint16  type;
++	/* length field for this TLV */
++	uint16  len;
++	uint32  idle_slotcnt_mimo;	/* MIMO idle slotcnt raw SHM value */
++	uint32  last_idle_slotcnt_mimo;	/* stored value snapshot */
++	uint32  idle_slotcnt_siso;	/* SISO idle slotcnt raw SHM value */
++	uint32  last_idle_slotcnt_siso;	/* stored value snapshot */
++	uint32	rx_time_mimo;		/* Rx MIMO raw SHM value */
++	uint32	last_rx_time_mimo;	/* stored value snapshot */
++	uint32	rx_time_siso;		/* RX SISO raw SHM value */
++	uint32	last_rx_time_siso;	/* stored value snapshot */
++	uint32  tx_time_1chain;		/* Tx 1-chain raw SHM value */
++	uint32  last_tx_time_1chain;	/* stored value snapshot */
++	uint32	tx_time_2chain;		/* Tx 2-chain raw SHM value */
++	uint32	last_tx_time_2chain;	/* stored value snapshot */
++	uint32  tx_time_3chain;		/* Tx 3-chain raw SHM value */
++	uint32  last_tx_time_3chain;	/* stored value snapshot */
++	uint16	reason;			/* reason for snapshot call, see below */
++	/* Does the call reset last values after delta calculation */
++	uint16	reset_last;
++} wl_mimo_ps_metrics_snapshot_trace_t;
++/* reason codes for mimo ps metrics snapshot function calls */
++#define WL_MIMOPS_METRICS_SNAPSHOT_REPORT		1
++#define WL_MIMOPS_METRICS_SNAPSHOT_RXCHAIN_SET		2
++#define WL_MIMOPS_METRICS_SNAPSHOT_ARBI			3
++#define WL_MIMOPS_METRICS_SNAPSHOT_SLOTUPD		4
++#define WL_MIMOPS_METRICS_SNAPSHOT_PMBCNRX		5
++#define WL_MIMOPS_METRICS_SNAPSHOT_BMACINIT		6
++#define WL_MIMOPS_METRICS_SNAPSHOT_HT_COMPLETE		7
++#define WL_MIMOPS_METRICS_SNAPSHOT_OCL                  8
++
++#define WL_MIMO_PS_STATUS_VERSION_2	2
++typedef struct wl_mimo_ps_status {
++	uint8 version;
++	uint8 ap_cap;			/* The associated AP's capability (BW, MIMO/SISO). */
++	uint8 association_status;	/* How we are associated to the AP (MIMO/SISO). */
++	uint8 mimo_ps_state;		/* mimo_ps_cfg states: [0-5]. See below for values */
++	uint8 mrc_state;		/* MRC state: NONE (0), ACTIVE(1) */
++	uint8 bss_rxchain;		/* bss rxchain bitmask */
++	uint8 bss_txchain;		/* bss txchain bitmask */
++	uint8 bss_bw;			/* bandwidth: Full (0), 20M (1), 40M (2), 80M (3), etc */
++	uint16 hw_state;		/* bitmask of hw state. See below for values */
++	uint8 hw_rxchain;		/* actual HW rxchain bitmask */
++	uint8 hw_txchain;		/* actual HW txchain bitmask */
++	uint8 hw_bw;			/* bandwidth: Full (0), 20M (1), 40M (2), 80M (3), etc */
++	uint8 pm_bcnrx_state;		/* actual state of ucode flag */
++	uint8 basic_rates_present;	/* internal flag to trigger siso bcmc rx */
++	uint8 siso_bcmc_rx_state;	/* actual state of ucode flag */
++} wl_mimo_ps_status_t;
++
++#define WL_MIMO_PS_STATUS_VERSION_1	1
++typedef struct wl_mimo_ps_status_v1 {
++	uint8 version;
++	uint8 ap_cap;			/* The associated AP's capability (BW, MIMO/SISO). */
++	uint8 association_status;	/* How we are associated to the AP (MIMO/SISO). */
++	uint8 mimo_ps_state;		/* mimo_ps_cfg states: [0-5]. See below for values */
++	uint8 mrc_state;		/* MRC state: NONE (0), ACTIVE(1) */
++	uint8 bss_rxchain;		/* bss rxchain bitmask */
++	uint8 bss_txchain;		/* bss txchain bitmask */
++	uint8 bss_bw;			/* bandwidth: Full (0), 20M (1), 40M (2), 80M (3), etc */
++	uint16 hw_state;		/* bitmask of hw state. See below for values */
++	uint8 hw_rxchain;		/* actual HW rxchain bitmask */
++	uint8 hw_txchain;		/* actual HW txchain bitmask */
++	uint8 hw_bw;			/* bandwidth: Full (0), 20M (1), 40M (2), 80M (3), etc */
++	uint8 pad[3];
++} wl_mimo_ps_status_v1_t;
++
++#define WL_MIMO_PS_STATUS_AP_CAP(ap_cap)	(ap_cap & 0x0F)
++#define WL_MIMO_PS_STATUS_AP_CAP_BW(ap_cap)	(ap_cap >> 4)
++#define WL_MIMO_PS_STATUS_ASSOC_BW_SHIFT 4
++
++/* version 3: assoc status: low nibble is status enum, high other flags */
++#define WL_MIMO_PS_STATUS_VERSION_3			3
++#define WL_MIMO_PS_STATUS_ASSOC_STATUS_MASK		0x0F
++#define WL_MIMO_PS_STATUS_ASSOC_STATUS_VHT_WITHOUT_OMN	0x80
++
++/* mimo_ps_status: ap_cap/association status */
++enum {
++	WL_MIMO_PS_STATUS_ASSOC_NONE	= 0,
++	WL_MIMO_PS_STATUS_ASSOC_SISO	= 1,
++	WL_MIMO_PS_STATUS_ASSOC_MIMO	= 2,
++	WL_MIMO_PS_STATUS_ASSOC_LEGACY	= 3
++};
++
++/* mimo_ps_status: mimo_ps_cfg states */
++enum {
++	WL_MIMO_PS_CFG_STATE_NONE			= 0,
++	WL_MIMO_PS_CFG_STATE_INFORM_AP_INPROGRESS	= 1,
++	WL_MIMO_PS_CFG_STATE_INFORM_AP_DONE		= 2,
++	WL_MIMO_PS_CFG_STATE_LEARNING			= 3,
++	WL_MIMO_PS_CFG_STATE_HW_CONFIGURE		= 4,
++	WL_MIMO_PS_CFG_STATE_INFORM_AP_PENDING		= 5
++};
++
++/* mimo_ps_status: hw_state values */
++#define WL_MIMO_PS_STATUS_HW_STATE_NONE			0
++#define WL_MIMO_PS_STATUS_HW_STATE_LTECOEX		(0x1 << 0)
++#define WL_MIMO_PS_STATUS_HW_STATE_MIMOPS_BSS		(0x1 << 1)
++#define WL_MIMO_PS_STATUS_HW_STATE_AWDL_BSS		(0x1 << 2)
++#define WL_MIMO_PS_STATUS_HW_STATE_SCAN			(0x1 << 3)
++#define WL_MIMO_PS_STATUS_HW_STATE_TXPPR		(0x1 << 4)
++#define WL_MIMO_PS_STATUS_HW_STATE_PWRTHOTTLE		(0x1 << 5)
++#define WL_MIMO_PS_STATUS_HW_STATE_TMPSENSE		(0x1 << 6)
++#define WL_MIMO_PS_STATUS_HW_STATE_IOVAR		(0x1 << 7)
++#define WL_MIMO_PS_STATUS_HW_STATE_AP_BSS		(0x1 << 8)
++
++/* mimo_ps_status: mrc states */
++#define WL_MIMO_PS_STATUS_MRC_NONE	0
++#define WL_MIMO_PS_STATUS_MRC_ACTIVE	1
++
++/* mimo_ps_status: core flag states for single-core beacon and siso-bcmc rx */
++#define WL_MIMO_PS_STATUS_MHF_FLAG_NONE		0
++#define WL_MIMO_PS_STATUS_MHF_FLAG_ACTIVE	1
++#define WL_MIMO_PS_STATUS_MHF_FLAG_COREDOWN	2
++#define WL_MIMO_PS_STATUS_MHF_FLAG_INVALID	3
++
++/* Type values for the REASON */
++#define WL_MIMO_PS_PS_LEARNING_ABORTED          (1 << 0)
++#define WL_MIMO_PS_PS_LEARNING_COMPLETED        (1 << 1)
++#define WL_MIMO_PS_PS_LEARNING_ONGOING          (1 << 2)
++
++typedef struct wl_mimo_ps_learning_event_data {
++	uint32 startTimeStamp;
++	uint32 endTimeStamp;
++	uint16 reason;
++	struct ether_addr BSSID;
++	uint32 totalSISO_below_rssi_threshold;
++	uint32 totalMIMO_below_rssi_threshold;
++	uint32 totalSISO_above_rssi_threshold;
++	uint32 totalMIMO_above_rssi_threshold;
++} wl_mimo_ps_learning_event_data_t;
++
++#define WL_MIMO_PS_PS_LEARNING_CFG_ABORT	(1 << 0)
++#define WL_MIMO_PS_PS_LEARNING_CFG_STATUS	(1 << 1)
++#define WL_MIMO_PS_PS_LEARNING_CFG_CONFIG	(1 << 2)
++
++#define WL_MIMO_PS_PS_LEARNING_CFG_V1 1
++
++typedef struct wl_mimops_learning_cfg {
++	/* flag:  bit 0 for abort */
++	/* flag:  bit 1 for status */
++	/* flag:  bit 2 for configuring no of packets and rssi */
++	uint8                  flag;
++	/* mimo ps learning version, compatible version is 0 */
++	uint8                  version;
++	/* if version is 0 or rssi is 0, ignored */
++	int8                   learning_rssi_threshold;
++	uint8                  reserved;
++	uint32                 no_of_packets_for_learning;
++	wl_mimo_ps_learning_event_data_t mimops_learning_data;
++} wl_mimops_learning_cfg_t;
++
++
++#define WL_OCL_STATUS_VERSION 1
++typedef struct ocl_status_info {
++	uint8  version;
++	uint8  len;
++	uint16 fw_status;     /* Bits representing FW disable reasons */
++	uint8  hw_status;     /* Bits for actual HW config and SISO/MIMO coremask */
++	uint8  coremask;      /* The ocl core mask (indicating listening core) */
++} ocl_status_info_t;
++
++/* MWS OCL map */
++#define WL_MWS_OCL_OVERRIDE_VERSION 1
++typedef struct wl_mws_ocl_override {
++	uint16  version;    /* Structure version */
++	uint16	bitmap_2g; /* bitmap for 2.4G channels bits 1-13 */
++	uint16	bitmap_5g_lo;  /* bitmap for 5G low channels by 2:
++				*34-48, 52-56, 60-64, 100-102
++				*/
++	uint16	bitmap_5g_mid; /* bitmap for 5G mid channels by 2:
++				* 104, 108-112, 116-120, 124-128,
++				* 132-136, 140, 149-151
++				*/
++	uint16	bitmap_5g_high; /* bitmap for 5G high channels by 2
++				* 153, 157-161, 165
++				*/
++} wl_mws_ocl_override_t;
++
++/* Bits for fw_status */
++#define OCL_DISABLED_HOST		0x01   /* Host has disabled through ocl_enable */
++#define OCL_DISABLED_RSSI		0x02   /* Disabled because of ocl_rssi_threshold */
++#define OCL_DISABLED_LTEC		0x04   /* Disabled due to LTE Coex activity */
++#define OCL_DISABLED_SISO		0x08   /* Disabled while in SISO mode */
++#define OCL_DISABLED_CAL		0x10   /* Disabled during active calibration */
++#define OCL_DISABLED_CHANSWITCH		0x20   /* Disabled during active channel switch */
++#define OCL_DISABLED_ASPEND     0x40   /* Disabled due to assoc pending */
++
++/* Bits for hw_status */
++#define OCL_HWCFG			0x01   /* State of OCL config bit in phy HW */
++#define OCL_HWMIMO			0x02   /* Set if current coremask is > 1 bit */
++#define OCL_COREDOWN			0x80   /* Set if core is currently down */
++
++
++/*
++ * Join preference iovar value is an array of tuples. Each tuple has a one-byte type,
++ * a one-byte length, and a variable length value.  RSSI type tuple must be present
++ * in the array.
++ *
++ * Types are defined in "join preference types" section.
++ *
++ * Length is the value size in octets. It is reserved for WL_JOIN_PREF_WPA type tuple
++ * and must be set to zero.
++ *
++ * Values are defined below.
++ *
++ * 1. RSSI - 2 octets
++ * offset 0: reserved
++ * offset 1: reserved
++ *
++ * 2. WPA - 2 + 12 * n octets (n is # tuples defined below)
++ * offset 0: reserved
++ * offset 1: # of tuples
++ * offset 2: tuple 1
++ * offset 14: tuple 2
++ * ...
++ * offset 2 + 12 * (n - 1) octets: tuple n
++ *
++ * struct wpa_cfg_tuple {
++ *   uint8 akm[DOT11_OUI_LEN+1];     akm suite
++ *   uint8 ucipher[DOT11_OUI_LEN+1]; unicast cipher suite
++ *   uint8 mcipher[DOT11_OUI_LEN+1]; multicast cipher suite
++ * };
++ *
++ * multicast cipher suite can be specified as a specific cipher suite or WL_WPA_ACP_MCS_ANY.
++ *
++ * 3. BAND - 2 octets
++ * offset 0: reserved
++ * offset 1: see "band preference" and "band types"
++ *
++ * 4. BAND RSSI - 2 octets
++ * offset 0: band types
++ * offset 1: +ve RSSI boost value in dB
++ */
++
++struct tsinfo_arg {
++	uint8 octets[3];
++};
++
++#define RATE_CCK_1MBPS 0
++#define RATE_CCK_2MBPS 1
++#define RATE_CCK_5_5MBPS 2
++#define RATE_CCK_11MBPS 3
++
++#define RATE_LEGACY_OFDM_6MBPS 0
++#define RATE_LEGACY_OFDM_9MBPS 1
++#define RATE_LEGACY_OFDM_12MBPS 2
++#define RATE_LEGACY_OFDM_18MBPS 3
++#define RATE_LEGACY_OFDM_24MBPS 4
++#define RATE_LEGACY_OFDM_36MBPS 5
++#define RATE_LEGACY_OFDM_48MBPS 6
++#define RATE_LEGACY_OFDM_54MBPS 7
++
++#define WL_BSSTRANS_RSSI_RATE_MAP_VERSION 1
++
++typedef struct wl_bsstrans_rssi {
++	int8 rssi_2g;	/**< RSSI in dbm for 2.4 G */
++	int8 rssi_5g;	/**< RSSI in dbm for 5G, unused for cck */
++} wl_bsstrans_rssi_t;
++
++#define RSSI_RATE_MAP_MAX_STREAMS 4	/**< max streams supported */
++
++/** RSSI to rate mapping, all 20Mhz, no SGI */
++typedef struct wl_bsstrans_rssi_rate_map {
++	uint16 ver;
++	uint16 len; /**< length of entire structure */
++	wl_bsstrans_rssi_t cck[WL_NUM_RATES_CCK]; /**< 2.4G only */
++	wl_bsstrans_rssi_t ofdm[WL_NUM_RATES_OFDM]; /**< 6 to 54mbps */
++	wl_bsstrans_rssi_t phy_n[RSSI_RATE_MAP_MAX_STREAMS][WL_NUM_RATES_MCS_1STREAM]; /* MCS0-7 */
++	wl_bsstrans_rssi_t phy_ac[RSSI_RATE_MAP_MAX_STREAMS][WL_NUM_RATES_VHT]; /**< MCS0-9 */
++} wl_bsstrans_rssi_rate_map_t;
++
++#define WL_BSSTRANS_ROAMTHROTTLE_VERSION 1
++
++/** Configure number of scans allowed per throttle period */
++typedef struct wl_bsstrans_roamthrottle {
++	uint16 ver;
++	uint16 period;
++	uint16 scans_allowed;
++} wl_bsstrans_roamthrottle_t;
++
++#define	NFIFO			6	/**< # tx/rx fifopairs */
++
++#if defined(BCM_DMA_CT) && !defined(BCM_DMA_CT_DISABLED)
++#define NFIFO_EXT		32		/* 6 traditional FIFOs + 2 rsvd + 24 MU FIFOs */
++#elif defined(WL11AX) && defined(WL11AX_TRIGGERQ_ENABLED)
++#define NFIFO_EXT		10
++#else
++#define NFIFO_EXT		NFIFO
++#endif
++
++/* Reinit reason codes */
++enum {
++	WL_REINIT_RC_NONE             = 0,
++	WL_REINIT_RC_PS_SYNC          = 1,
++	WL_REINIT_RC_PSM_WD           = 2,
++	WL_REINIT_RC_MAC_WAKE         = 3,
++	WL_REINIT_RC_MAC_SUSPEND      = 4,
++	WL_REINIT_RC_MAC_SPIN_WAIT    = 5,
++	WL_REINIT_RC_AXI_BUS_ERROR    = 6,
++	WL_REINIT_RC_DEVICE_REMOVED   = 7,
++	WL_REINIT_RC_PCIE_FATAL_ERROR = 8,
++	WL_REINIT_RC_OL_FW_TRAP       = 9,
++	WL_REINIT_RC_FIFO_ERR         = 10,
++	WL_REINIT_RC_INV_TX_STATUS    = 11,
++	WL_REINIT_RC_MQ_ERROR         = 12,
++	WL_REINIT_RC_PHYTXERR_THRESH  = 13,
++	WL_REINIT_RC_USER_FORCED      = 14,
++	WL_REINIT_RC_FULL_RESET       = 15,
++	WL_REINIT_RC_AP_BEACON        = 16,
++	WL_REINIT_RC_PM_EXCESSED      = 17,
++	WL_REINIT_RC_NO_CLK           = 18,
++	WL_REINIT_RC_SW_ASSERT        = 19,
++	WL_REINIT_RC_PSM_JMP0         = 20,
++	WL_REINIT_RC_PSM_RUN          = 21,
++	WL_REINIT_RC_ENABLE_MAC       = 22,
++	WL_REINIT_RC_SCAN_TIMEOUT     = 23,
++	WL_REINIT_RC_JOIN_TIMEOUT     = 24,
++	/* Below error codes are generated during D3 exit validation */
++	WL_REINIT_RC_LINK_NOT_ACTIVE  = 25,
++	WL_REINIT_RC_PCI_CFG_RD_FAIL  = 26,
++	WL_REINIT_RC_INV_VEN_ID       = 27,
++	WL_REINIT_RC_INV_DEV_ID       = 28,
++	WL_REINIT_RC_INV_BAR0         = 29,
++	WL_REINIT_RC_INV_BAR2         = 30,
++	WL_REINIT_RC_AER_UC_FATAL     = 31,
++	WL_REINIT_RC_AER_UC_NON_FATAL = 32,
++	WL_REINIT_RC_AER_CORR         = 33,
++	WL_REINIT_RC_AER_DEV_STS      = 34,
++	WL_REINIT_RC_PCIe_STS         = 35,
++	WL_REINIT_RC_MMIO_RD_FAIL     = 36,
++	WL_REINIT_RC_MMIO_RD_INVAL    = 37,
++	WL_REINIT_RC_MMIO_ARM_MEM_RD_FAIL = 38,
++	WL_REINIT_RC_MMIO_ARM_MEM_INVAL   = 39,
++	WL_REINIT_RC_SROM_LOAD_FAILED     = 40,
++	WL_REINIT_RC_PHY_CRASH            = 41,
++	WL_REINIT_TX_STALL                = 42,
++	WL_REINIT_RC_TX_FLOW_CONTROL_BLOCKED	= 43,
++	WL_REINIT_RC_RX_HC_FAIL           = 44,
++	WL_REINIT_RC_RX_DMA_STALL         = 45,
++	WL_REINIT_UTRACE_BUF_OVERLAP_SR	  = 46,
++	WL_REINIT_UTRACE_TPL_OUT_BOUNDS   = 47,
++	WL_REINIT_UTRACE_TPL_OSET_STRT0   = 48,
++	WL_REINIT_RC_PHYTXERR             = 49,
++	WL_REINIT_RC_PSM_FATAL_SUSP       = 50,
++	WL_REINIT_RC_TX_FIFO_SUSP         = 51,
++	WL_REINIT_RC_MAC_ENABLE           = 52,
++	WL_REINIT_RC_SCAN_STALLED         = 53,
++	WL_REINIT_RC_LAST	/* This must be the last entry */
++};
++
++#define NREINITREASONCOUNT	8
++
++#define REINITRSNIDX(_x)	(((_x) < WL_REINIT_RC_LAST) ? (_x) : 0)
++
++#define	WL_CNT_T_VERSION	30	/**< current version of wl_cnt_t struct */
++#define WL_CNT_VERSION_6	6
++#define WL_CNT_VERSION_11	11
++#define WL_CNT_VERSION_XTLV	30
++
++#define WL_COUNTERS_IOV_VERSION_1	1
++#define WL_SUBCNTR_IOV_VER		WL_COUNTERS_IOV_VERSION_1
++/* First two uint16 are version and lenght fields. So offset of the first counter will be 4 */
++#define FIRST_COUNTER_OFFSET		0x04
++
++#define WLC_WITH_XTLV_CNT
++
++/**
++ * tlv IDs uniquely identifies counter component
++ * packed into wl_cmd_t container
++ */
++enum wl_cnt_xtlv_id {
++	WL_CNT_XTLV_SLICE_IDX = 0x1,		/**< Slice index */
++	WL_CNT_XTLV_WLC = 0x100,		/**< WLC layer counters */
++	WL_CNT_XTLV_WLC_RINIT_RSN = 0x101,	/**< WLC layer reinitreason extension */
++	WL_CNT_XTLV_CNTV_LE10_UCODE = 0x200,	/**< wl counter ver < 11 UCODE MACSTAT */
++	WL_CNT_XTLV_LT40_UCODE_V1 = 0x300,	/**< corerev < 40 UCODE MACSTAT */
++	WL_CNT_XTLV_GE40_UCODE_V1 = 0x400,	/**< corerev >= 40 UCODE MACSTAT */
++	WL_CNT_XTLV_GE64_UCODEX_V1 = 0x800	/* corerev >= 64 UCODEX MACSTAT */
++};
++
++/**
++ * The number of variables in wl macstat cnt struct.
++ * (wl_cnt_ge40mcst_v1_t, wl_cnt_lt40mcst_v1_t, wl_cnt_v_le10_mcst_t)
++ */
++#define WL_CNT_MCST_VAR_NUM 64
++/* sizeof(wl_cnt_ge40mcst_v1_t), sizeof(wl_cnt_lt40mcst_v1_t), and sizeof(wl_cnt_v_le10_mcst_t) */
++#define WL_CNT_MCST_STRUCT_SZ ((uint32)sizeof(uint32) * WL_CNT_MCST_VAR_NUM)
++
++#define WL_CNT_MCXST_STRUCT_SZ ((uint32)sizeof(wl_cnt_ge64mcxst_v1_t))
++#define INVALID_CNT_VAL (uint32)(-1)
++
++#define WL_XTLV_CNTBUF_MAX_SIZE ((uint32)(OFFSETOF(wl_cnt_info_t, data)) +	\
++		(uint32)BCM_XTLV_HDR_SIZE + (uint32)sizeof(wl_cnt_wlc_t) +		\
++		(uint32)BCM_XTLV_HDR_SIZE + WL_CNT_MCST_STRUCT_SZ +              \
++		(uint32)BCM_XTLV_HDR_SIZE + WL_CNT_MCXST_STRUCT_SZ)
++
++#define WL_CNTBUF_MAX_SIZE MAX(WL_XTLV_CNTBUF_MAX_SIZE, (uint32)sizeof(wl_cnt_ver_11_t))
++
++
++/** Top structure of counters IOVar buffer */
++typedef struct {
++	uint16	version;	/**< see definition of WL_CNT_T_VERSION */
++	uint16	datalen;	/**< length of data including all paddings. */
++	uint8   data [];	/**< variable length payload:
++				 * 1 or more bcm_xtlv_t type of tuples.
++				 * each tuple is padded to multiple of 4 bytes.
++				 * 'datalen' field of this structure includes all paddings.
++				 */
++} wl_cnt_info_t;
++
++/* Top structure of subcounters IOVar buffer
++ * Whenever we make any change in this structure
++ * WL_SUBCNTR_IOV_VER should be updated accordingly
++ * The structure definition should remain consistant b/w
++ * FW and wl/WLM app.
++ */
++typedef struct {
++	uint16	version;	  /* Version of IOVAR structure. Used for backward
++				   * compatibility in future. Whenever we make any
++				   * changes to this structure then value of WL_SUBCNTR_IOV_VER
++				   * needs to be updated properly.
++				   */
++	uint16	length;		  /* length in bytes of this structure */
++	uint16	counters_version; /* see definition of WL_CNT_T_VERSION
++				   * wl app will send the version of counters
++				   * which is used to calculate the offset of counters.
++				   * It must match the version of counters FW is using
++				   * else FW will return error with his version of counters
++				   * set in this field.
++				   */
++	uint16	num_subcounters;  /* Number of counter offset passed by wl app to FW. */
++	uint32	data[1];	  /* variable length payload:
++				   * Offsets to the counters will be passed to FW
++				   * throught this data field. FW will return the value of counters
++				   * at the offsets passed by wl app in this fiels itself.
++				   */
++} wl_subcnt_info_t;
++
++/** wlc layer counters */
++typedef struct {
++	/* transmit stat counters */
++	uint32	txframe;	/**< tx data frames */
++	uint32	txbyte;		/**< tx data bytes */
++	uint32	txretrans;	/**< tx mac retransmits */
++	uint32	txerror;	/**< tx data errors (derived: sum of others) */
++	uint32	txctl;		/**< tx management frames */
++	uint32	txprshort;	/**< tx short preamble frames */
++	uint32	txserr;		/**< tx status errors */
++	uint32	txnobuf;	/**< tx out of buffers errors */
++	uint32	txnoassoc;	/**< tx discard because we're not associated */
++	uint32	txrunt;		/**< tx runt frames */
++	uint32	txchit;		/**< tx header cache hit (fastpath) */
++	uint32	txcmiss;	/**< tx header cache miss (slowpath) */
++
++	/* transmit chip error counters */
++	uint32	txuflo;		/**< tx fifo underflows */
++	uint32	txphyerr;	/**< tx phy errors (indicated in tx status) */
++	uint32	txphycrs;
++
++	/* receive stat counters */
++	uint32	rxframe;	/**< rx data frames */
++	uint32	rxbyte;		/**< rx data bytes */
++	uint32	rxerror;	/**< rx data errors (derived: sum of others) */
++	uint32	rxctl;		/**< rx management frames */
++	uint32	rxnobuf;	/**< rx out of buffers errors */
++	uint32	rxnondata;	/**< rx non data frames in the data channel errors */
++	uint32	rxbadds;	/**< rx bad DS errors */
++	uint32	rxbadcm;	/**< rx bad control or management frames */
++	uint32	rxfragerr;	/**< rx fragmentation errors */
++	uint32	rxrunt;		/**< rx runt frames */
++	uint32	rxgiant;	/**< rx giant frames */
++	uint32	rxnoscb;	/**< rx no scb error */
++	uint32	rxbadproto;	/**< rx invalid frames */
++	uint32	rxbadsrcmac;	/**< rx frames with Invalid Src Mac */
++	uint32	rxbadda;	/**< rx frames tossed for invalid da */
++	uint32	rxfilter;	/**< rx frames filtered out */
++
++	/* receive chip error counters */
++	uint32	rxoflo;		/**< rx fifo overflow errors */
++	uint32	rxuflo[NFIFO];	/**< rx dma descriptor underflow errors */
++
++	uint32	d11cnt_txrts_off;	/**< d11cnt txrts value when reset d11cnt */
++	uint32	d11cnt_rxcrc_off;	/**< d11cnt rxcrc value when reset d11cnt */
++	uint32	d11cnt_txnocts_off;	/**< d11cnt txnocts value when reset d11cnt */
++
++	/* misc counters */
++	uint32	dmade;		/**< tx/rx dma descriptor errors */
++	uint32	dmada;		/**< tx/rx dma data errors */
++	uint32	dmape;		/**< tx/rx dma descriptor protocol errors */
++	uint32	reset;		/**< reset count */
++	uint32	tbtt;		/**< cnts the TBTT int's */
++	uint32	txdmawar;
++	uint32	pkt_callback_reg_fail;	/**< callbacks register failure */
++
++	/* 802.11 MIB counters, pp. 614 of 802.11 reaff doc. */
++	uint32	txfrag;		/**< dot11TransmittedFragmentCount */
++	uint32	txmulti;	/**< dot11MulticastTransmittedFrameCount */
++	uint32	txfail;		/**< dot11FailedCount */
++	uint32	txretry;	/**< dot11RetryCount */
++	uint32	txretrie;	/**< dot11MultipleRetryCount */
++	uint32	rxdup;		/**< dot11FrameduplicateCount */
++	uint32	txrts;		/**< dot11RTSSuccessCount */
++	uint32	txnocts;	/**< dot11RTSFailureCount */
++	uint32	txnoack;	/**< dot11ACKFailureCount */
++	uint32	rxfrag;		/**< dot11ReceivedFragmentCount */
++	uint32	rxmulti;	/**< dot11MulticastReceivedFrameCount */
++	uint32	rxcrc;		/**< dot11FCSErrorCount */
++	uint32	txfrmsnt;	/**< dot11TransmittedFrameCount (bogus MIB?) */
++	uint32	rxundec;	/**< dot11WEPUndecryptableCount */
++
++	/* WPA2 counters (see rxundec for DecryptFailureCount) */
++	uint32	tkipmicfaill;	/**< TKIPLocalMICFailures */
++	uint32	tkipcntrmsr;	/**< TKIPCounterMeasuresInvoked */
++	uint32	tkipreplay;	/**< TKIPReplays */
++	uint32	ccmpfmterr;	/**< CCMPFormatErrors */
++	uint32	ccmpreplay;	/**< CCMPReplays */
++	uint32	ccmpundec;	/**< CCMPDecryptErrors */
++	uint32	fourwayfail;	/**< FourWayHandshakeFailures */
++	uint32	wepundec;	/**< dot11WEPUndecryptableCount */
++	uint32	wepicverr;	/**< dot11WEPICVErrorCount */
++	uint32	decsuccess;	/**< DecryptSuccessCount */
++	uint32	tkipicverr;	/**< TKIPICVErrorCount */
++	uint32	wepexcluded;	/**< dot11WEPExcludedCount */
++
++	uint32	txchanrej;	/**< Tx frames suppressed due to channel rejection */
++	uint32	psmwds;		/**< Count PSM watchdogs */
++	uint32	phywatchdog;	/**< Count Phy watchdogs (triggered by ucode) */
++
++	/* MBSS counters, AP only */
++	uint32	prq_entries_handled;	/**< PRQ entries read in */
++	uint32	prq_undirected_entries;	/**<    which were bcast bss & ssid */
++	uint32	prq_bad_entries;	/**<    which could not be translated to info */
++	uint32	atim_suppress_count;	/**< TX suppressions on ATIM fifo */
++	uint32	bcn_template_not_ready;	/**< Template marked in use on send bcn ... */
++	uint32	bcn_template_not_ready_done; /**< ...but "DMA done" interrupt rcvd */
++	uint32	late_tbtt_dpc;	/**< TBTT DPC did not happen in time */
++
++	/* per-rate receive stat counters */
++	uint32  rx1mbps;	/**< packets rx at 1Mbps */
++	uint32  rx2mbps;	/**< packets rx at 2Mbps */
++	uint32  rx5mbps5;	/**< packets rx at 5.5Mbps */
++	uint32  rx6mbps;	/**< packets rx at 6Mbps */
++	uint32  rx9mbps;	/**< packets rx at 9Mbps */
++	uint32  rx11mbps;	/**< packets rx at 11Mbps */
++	uint32  rx12mbps;	/**< packets rx at 12Mbps */
++	uint32  rx18mbps;	/**< packets rx at 18Mbps */
++	uint32  rx24mbps;	/**< packets rx at 24Mbps */
++	uint32  rx36mbps;	/**< packets rx at 36Mbps */
++	uint32  rx48mbps;	/**< packets rx at 48Mbps */
++	uint32  rx54mbps;	/**< packets rx at 54Mbps */
++	uint32  rx108mbps;	/**< packets rx at 108mbps */
++	uint32  rx162mbps;	/**< packets rx at 162mbps */
++	uint32  rx216mbps;	/**< packets rx at 216 mbps */
++	uint32  rx270mbps;	/**< packets rx at 270 mbps */
++	uint32  rx324mbps;	/**< packets rx at 324 mbps */
++	uint32  rx378mbps;	/**< packets rx at 378 mbps */
++	uint32  rx432mbps;	/**< packets rx at 432 mbps */
++	uint32  rx486mbps;	/**< packets rx at 486 mbps */
++	uint32  rx540mbps;	/**< packets rx at 540 mbps */
++
++	uint32	rfdisable;	/**< count of radio disables */
++
++	uint32	txexptime;	/**< Tx frames suppressed due to timer expiration */
++
++	uint32	txmpdu_sgi;	/**< count for sgi transmit */
++	uint32	rxmpdu_sgi;	/**< count for sgi received */
++	uint32	txmpdu_stbc;	/**< count for stbc transmit */
++	uint32	rxmpdu_stbc;	/**< count for stbc received */
++
++	uint32	rxundec_mcst;	/**< dot11WEPUndecryptableCount */
++
++	/* WPA2 counters (see rxundec for DecryptFailureCount) */
++	uint32	tkipmicfaill_mcst;	/**< TKIPLocalMICFailures */
++	uint32	tkipcntrmsr_mcst;	/**< TKIPCounterMeasuresInvoked */
++	uint32	tkipreplay_mcst;	/**< TKIPReplays */
++	uint32	ccmpfmterr_mcst;	/**< CCMPFormatErrors */
++	uint32	ccmpreplay_mcst;	/**< CCMPReplays */
++	uint32	ccmpundec_mcst;	/**< CCMPDecryptErrors */
++	uint32	fourwayfail_mcst;	/**< FourWayHandshakeFailures */
++	uint32	wepundec_mcst;	/**< dot11WEPUndecryptableCount */
++	uint32	wepicverr_mcst;	/**< dot11WEPICVErrorCount */
++	uint32	decsuccess_mcst;	/**< DecryptSuccessCount */
++	uint32	tkipicverr_mcst;	/**< TKIPICVErrorCount */
++	uint32	wepexcluded_mcst;	/**< dot11WEPExcludedCount */
++
++	uint32	dma_hang;	/**< count for dma hang */
++	uint32	reinit;		/**< count for reinit */
++
++	uint32  pstatxucast;	/**< count of ucast frames xmitted on all psta assoc */
++	uint32  pstatxnoassoc;	/**< count of txnoassoc frames xmitted on all psta assoc */
++	uint32  pstarxucast;	/**< count of ucast frames received on all psta assoc */
++	uint32  pstarxbcmc;	/**< count of bcmc frames received on all psta */
++	uint32  pstatxbcmc;	/**< count of bcmc frames transmitted on all psta */
++
++	uint32  cso_passthrough; /**< hw cso required but passthrough */
++	uint32	cso_normal;	/**< hw cso hdr for normal process */
++	uint32	chained;	/**< number of frames chained */
++	uint32	chainedsz1;	/**< number of chain size 1 frames */
++	uint32	unchained;	/**< number of frames not chained */
++	uint32	maxchainsz;	/**< max chain size so far */
++	uint32	currchainsz;	/**< current chain size */
++	uint32	pciereset;	/**< Secondary Bus Reset issued by driver */
++	uint32	cfgrestore;	/**< configspace restore by driver */
++	uint32	reinitreason[NREINITREASONCOUNT]; /**< reinitreason counters; 0: Unknown reason */
++	uint32	rxrtry;
++	uint32  rxmpdu_mu;      /**< Number of MU MPDUs received */
++
++	/* detailed control/management frames */
++	uint32	txbar;		/**< Number of TX BAR */
++	uint32	rxbar;		/**< Number of RX BAR */
++	uint32	txpspoll;	/**< Number of TX PS-poll */
++	uint32	rxpspoll;	/**< Number of RX PS-poll */
++	uint32	txnull;		/**< Number of TX NULL_DATA */
++	uint32	rxnull;		/**< Number of RX NULL_DATA */
++	uint32	txqosnull;	/**< Number of TX NULL_QoSDATA */
++	uint32	rxqosnull;	/**< Number of RX NULL_QoSDATA */
++	uint32	txassocreq;	/**< Number of TX ASSOC request */
++	uint32	rxassocreq;	/**< Number of RX ASSOC request */
++	uint32	txreassocreq;	/**< Number of TX REASSOC request */
++	uint32	rxreassocreq;	/**< Number of RX REASSOC request */
++	uint32	txdisassoc;	/**< Number of TX DISASSOC */
++	uint32	rxdisassoc;	/**< Number of RX DISASSOC */
++	uint32	txassocrsp;	/**< Number of TX ASSOC response */
++	uint32	rxassocrsp;	/**< Number of RX ASSOC response */
++	uint32	txreassocrsp;	/**< Number of TX REASSOC response */
++	uint32	rxreassocrsp;	/**< Number of RX REASSOC response */
++	uint32	txauth;		/**< Number of TX AUTH */
++	uint32	rxauth;		/**< Number of RX AUTH */
++	uint32	txdeauth;	/**< Number of TX DEAUTH */
++	uint32	rxdeauth;	/**< Number of RX DEAUTH */
++	uint32	txprobereq;	/**< Number of TX probe request */
++	uint32	rxprobereq;	/**< Number of RX probe request */
++	uint32	txprobersp;	/**< Number of TX probe response */
++	uint32	rxprobersp;	/**< Number of RX probe response */
++	uint32	txaction;	/**< Number of TX action frame */
++	uint32	rxaction;	/**< Number of RX action frame */
++	uint32  ampdu_wds;	/**< Number of AMPDU watchdogs */
++	uint32  txlost;		/**< Number of lost packets reported in txs */
++	uint32	txdatamcast;	/**< Number of TX multicast data packets */
++	uint32	txdatabcast;	/**< Number of TX broadcast data packets */
++	uint32	psmxwds;	/**< Number of PSMx watchdogs */
++	uint32  rxback;
++	uint32  txback;
++	uint32  p2p_tbtt;	/**< Number of P2P TBTT Events */
++	uint32  p2p_tbtt_miss;	/**< Number of P2P TBTT Events Miss */
++	uint32	txqueue_start;
++	uint32	txqueue_end;
++	uint32  txbcast;        /* Broadcast TransmittedFrameCount */
++	uint32  txdropped;      /* tx dropped pkts */
++	uint32  rxbcast;        /* BroadcastReceivedFrameCount */
++	uint32  rxdropped;      /* rx dropped pkts (derived: sum of others) */
++} wl_cnt_wlc_t;
++
++/* Reinit reasons - do not put anything else other than reinit reasons here */
++typedef struct {
++	uint32 rsn[WL_REINIT_RC_LAST];
++} reinit_rsns_t;
++
++/* MACXSTAT counters for ucodex (corerev >= 64) */
++typedef struct {
++	uint32 macxsusp;
++	uint32 m2vmsg;
++	uint32 v2mmsg;
++	uint32 mboxout;
++	uint32 musnd;
++	uint32 sfb2v;
++} wl_cnt_ge64mcxst_v1_t;
++
++/** MACSTAT counters for ucode (corerev >= 40) */
++typedef struct {
++	/* MAC counters: 32-bit version of d11.h's macstat_t */
++	uint32	txallfrm;	/**< total number of frames sent, incl. Data, ACK, RTS, CTS,
++				 * Control Management (includes retransmissions)
++				 */
++	uint32	txrtsfrm;	/**< number of RTS sent out by the MAC */
++	uint32	txctsfrm;	/**< number of CTS sent out by the MAC */
++	uint32	txackfrm;	/**< number of ACK frames sent out */
++	uint32	txdnlfrm;	/**< number of Null-Data transmission generated from template  */
++	uint32	txbcnfrm;	/**< beacons transmitted */
++	uint32	txfunfl[6];	/**< per-fifo tx underflows */
++	uint32	txampdu;	/**< number of AMPDUs transmitted */
++	uint32	txmpdu;		/**< number of MPDUs transmitted */
++	uint32	txtplunfl;	/**< Template underflows (mac was too slow to transmit ACK/CTS
++				 * or BCN)
++				 */
++	uint32	txphyerror;	/**< Transmit phy error, type of error is reported in tx-status for
++				 * driver enqueued frames
++				 */
++	uint32  pktengrxducast; /**< unicast frames rxed by the pkteng code */
++	uint32  pktengrxdmcast; /**< multicast frames rxed by the pkteng code */
++	uint32	rxfrmtoolong;	/**< Received frame longer than legal limit (2346 bytes) */
++	uint32	rxfrmtooshrt; /**< Received frame did not contain enough bytes for its frame type */
++	uint32	rxanyerr;	/**< Any RX error that is not counted by other counters. */
++	uint32	rxbadfcs;	/**< number of frames for which the CRC check failed in the MAC */
++	uint32	rxbadplcp;	/**< parity check of the PLCP header failed */
++	uint32	rxcrsglitch;	/**< PHY was able to correlate the preamble but not the header */
++	uint32	rxstrt;		/**< Number of received frames with a good PLCP
++				 * (i.e. passing parity check)
++				 */
++	uint32	rxdtucastmbss; /**< number of received DATA frames with good FCS and matching RA */
++	uint32	rxmgucastmbss; /**< number of received mgmt frames with good FCS and matching RA */
++	uint32	rxctlucast; /**< number of received CNTRL frames with good FCS and matching RA */
++	uint32	rxrtsucast;	/**< number of unicast RTS addressed to the MAC (good FCS) */
++	uint32	rxctsucast;	/**< number of unicast CTS addressed to the MAC (good FCS) */
++	uint32	rxackucast;	/**< number of ucast ACKS received (good FCS) */
++	uint32	rxdtocast; /**< number of received DATA frames (good FCS and not matching RA) */
++	uint32	rxmgocast; /**< number of received MGMT frames (good FCS and not matching RA) */
++	uint32	rxctlocast; /**< number of received CNTRL frame (good FCS and not matching RA) */
++	uint32	rxrtsocast;	/**< number of received RTS not addressed to the MAC */
++	uint32	rxctsocast;	/**< number of received CTS not addressed to the MAC */
++	uint32	rxdtmcast;	/**< number of RX Data multicast frames received by the MAC */
++	uint32	rxmgmcast;	/**< number of RX Management multicast frames received by the MAC */
++	uint32	rxctlmcast;	/**< number of RX Control multicast frames received by the MAC
++				 * (unlikely to see these)
++				 */
++	uint32	rxbeaconmbss;	/**< beacons received from member of BSS */
++	uint32	rxdtucastobss; /**< number of unicast frames addressed to the MAC from
++				  * other BSS (WDS FRAME)
++				  */
++	uint32	rxbeaconobss;	/**< beacons received from other BSS */
++	uint32	rxrsptmout;	/**< number of response timeouts for transmitted frames
++				 * expecting a response
++				 */
++	uint32	bcntxcancl;	/**< transmit beacons canceled due to receipt of beacon (IBSS) */
++	uint32	rxnodelim;	/**< number of no valid delimiter detected by ampdu parser */
++	uint32	rxf0ovfl;	/**< number of receive fifo 0 overflows */
++	uint32	rxf1ovfl;	/**< number of receive fifo 1 overflows */
++	uint32	rxhlovfl;	/**< number of length / header fifo overflows */
++	uint32	missbcn_dbg;	/**< number of beacon missed to receive */
++	uint32	pmqovfl;	/**< number of PMQ overflows */
++	uint32	rxcgprqfrm;	/**< number of received Probe requests that made it into
++				 * the PRQ fifo
++				 */
++	uint32	rxcgprsqovfl;	/**< Rx Probe Request Que overflow in the AP */
++	uint32	txcgprsfail;	/**< Tx Probe Response Fail. AP sent probe response but did
++				 * not get ACK
++				 */
++	uint32	txcgprssuc;	/**< Tx Probe Response Success (ACK was received) */
++	uint32	prs_timeout;	/**< number of probe requests that were dropped from the PRQ
++				 * fifo because a probe response could not be sent out within
++				 * the time limit defined in M_PRS_MAXTIME
++				 */
++	uint32	txrtsfail;	/**< number of rts transmission failure that reach retry limit */
++	uint32	txucast;	/**< number of unicast tx expecting response other than cts/cwcts */
++	uint32  txinrtstxop;	/**< number of data frame transmissions during rts txop */
++	uint32	rxback;		/**< blockack rxcnt */
++	uint32	txback;		/**< blockack txcnt */
++	uint32	bphy_rxcrsglitch;	/**< PHY count of bphy glitches */
++	uint32	rxdrop20s;	/**< drop secondary cnt */
++	uint32	rxtoolate;	/**< receive too late */
++	uint32  bphy_badplcp;	/**< number of bad PLCP reception on BPHY rate */
++} wl_cnt_ge40mcst_v1_t;
++
++/** MACSTAT counters for ucode (corerev < 40) */
++typedef struct {
++	/* MAC counters: 32-bit version of d11.h's macstat_t */
++	uint32	txallfrm;	/**< total number of frames sent, incl. Data, ACK, RTS, CTS,
++				 * Control Management (includes retransmissions)
++				 */
++	uint32	txrtsfrm;	/**< number of RTS sent out by the MAC */
++	uint32	txctsfrm;	/**< number of CTS sent out by the MAC */
++	uint32	txackfrm;	/**< number of ACK frames sent out */
++	uint32	txdnlfrm;	/**< number of Null-Data transmission generated from template  */
++	uint32	txbcnfrm;	/**< beacons transmitted */
++	uint32	txfunfl[6];	/**< per-fifo tx underflows */
++	uint32	txampdu;	/**< number of AMPDUs transmitted */
++	uint32	txmpdu;		/**< number of MPDUs transmitted */
++	uint32	txtplunfl;	/**< Template underflows (mac was too slow to transmit ACK/CTS
++				 * or BCN)
++				 */
++	uint32	txphyerror;	/**< Transmit phy error, type of error is reported in tx-status for
++				 * driver enqueued frames
++				 */
++	uint32  pktengrxducast; /**< unicast frames rxed by the pkteng code */
++	uint32  pktengrxdmcast; /**< multicast frames rxed by the pkteng code */
++	uint32	rxfrmtoolong;	/**< Received frame longer than legal limit (2346 bytes) */
++	uint32	rxfrmtooshrt; /**< Received frame did not contain enough bytes for its frame type */
++	uint32	rxanyerr;	/**< Any RX error that is not counted by other counters. */
++	uint32	rxbadfcs;	/**< number of frames for which the CRC check failed in the MAC */
++	uint32	rxbadplcp;	/**< parity check of the PLCP header failed */
++	uint32	rxcrsglitch;	/**< PHY was able to correlate the preamble but not the header */
++	uint32	rxstrt;		/**< Number of received frames with a good PLCP
++				 * (i.e. passing parity check)
++				 */
++	uint32	rxdtucastmbss; /**< number of received DATA frames with good FCS and matching RA */
++	uint32	rxmgucastmbss; /**< number of received mgmt frames with good FCS and matching RA */
++	uint32	rxctlucast; /**< number of received CNTRL frames with good FCS and matching RA */
++	uint32	rxrtsucast;	/**< number of unicast RTS addressed to the MAC (good FCS) */
++	uint32	rxctsucast;	/**< number of unicast CTS addressed to the MAC (good FCS) */
++	uint32	rxackucast;	/**< number of ucast ACKS received (good FCS) */
++	uint32	rxdtocast;  /**< number of received DATA frames (good FCS and not matching RA) */
++	uint32	rxmgocast;  /**< number of received MGMT frames (good FCS and not matching RA) */
++	uint32	rxctlocast; /**< number of received CNTRL frame (good FCS and not matching RA) */
++	uint32	rxrtsocast;	/**< number of received RTS not addressed to the MAC */
++	uint32	rxctsocast;	/**< number of received CTS not addressed to the MAC */
++	uint32	rxdtmcast;	/**< number of RX Data multicast frames received by the MAC */
++	uint32	rxmgmcast;	/**< number of RX Management multicast frames received by the MAC */
++	uint32	rxctlmcast;	/**< number of RX Control multicast frames received by the MAC
++				 * (unlikely to see these)
++				 */
++	uint32	rxbeaconmbss;	/**< beacons received from member of BSS */
++	uint32	rxdtucastobss; /**< number of unicast frames addressed to the MAC from
++				  * other BSS (WDS FRAME)
++				  */
++	uint32	rxbeaconobss;	/**< beacons received from other BSS */
++	uint32	rxrsptmout;	/**< number of response timeouts for transmitted frames
++				 * expecting a response
++				 */
++	uint32	bcntxcancl;	/**< transmit beacons canceled due to receipt of beacon (IBSS) */
++	uint32	rxnodelim;	/**< number of no valid delimiter detected by ampdu parser */
++	uint32	rxf0ovfl;	/**< number of receive fifo 0 overflows */
++	uint32	dbgoff46;
++	uint32	dbgoff47;
++	uint32	dbgoff48;	/**< Used for counting txstatus queue overflow (corerev <= 4)  */
++	uint32	pmqovfl;	/**< number of PMQ overflows */
++	uint32	rxcgprqfrm;	/**< number of received Probe requests that made it into
++				 * the PRQ fifo
++				 */
++	uint32	rxcgprsqovfl;	/**< Rx Probe Request Que overflow in the AP */
++	uint32	txcgprsfail;	/**< Tx Probe Response Fail. AP sent probe response but did
++				 * not get ACK
++				 */
++	uint32	txcgprssuc;	/**< Tx Probe Response Success (ACK was received) */
++	uint32	prs_timeout;	/**< number of probe requests that were dropped from the PRQ
++				 * fifo because a probe response could not be sent out within
++				 * the time limit defined in M_PRS_MAXTIME
++				 */
++	uint32	txrtsfail;	/**< number of rts transmission failure that reach retry limit */
++	uint32	txucast;	/**< number of unicast tx expecting response other than cts/cwcts */
++	uint32  txinrtstxop;	/**< number of data frame transmissions during rts txop */
++	uint32	rxback;		/**< blockack rxcnt */
++	uint32	txback;		/**< blockack txcnt */
++	uint32	bphy_rxcrsglitch;	/**< PHY count of bphy glitches */
++	uint32	phywatch;
++	uint32	rxtoolate;	/**< receive too late */
++	uint32  bphy_badplcp;	/**< number of bad PLCP reception on BPHY rate */
++} wl_cnt_lt40mcst_v1_t;
++
++/** MACSTAT counters for "wl counter" version <= 10 */
++typedef struct {
++	/* MAC counters: 32-bit version of d11.h's macstat_t */
++	uint32	txallfrm;	/**< total number of frames sent, incl. Data, ACK, RTS, CTS,
++				 * Control Management (includes retransmissions)
++				 */
++	uint32	txrtsfrm;	/**< number of RTS sent out by the MAC */
++	uint32	txctsfrm;	/**< number of CTS sent out by the MAC */
++	uint32	txackfrm;	/**< number of ACK frames sent out */
++	uint32	txdnlfrm;	/**< number of Null-Data transmission generated from template  */
++	uint32	txbcnfrm;	/**< beacons transmitted */
++	uint32	txfunfl[6];	/**< per-fifo tx underflows */
++	uint32	txfbw;		/**< transmit at fallback bw (dynamic bw) */
++	uint32	PAD0;		/**< number of MPDUs transmitted */
++	uint32	txtplunfl;	/**< Template underflows (mac was too slow to transmit ACK/CTS
++				 * or BCN)
++				 */
++	uint32	txphyerror;	/**< Transmit phy error, type of error is reported in tx-status for
++				 * driver enqueued frames
++				 */
++	uint32  pktengrxducast; /**< unicast frames rxed by the pkteng code */
++	uint32  pktengrxdmcast; /**< multicast frames rxed by the pkteng code */
++	uint32	rxfrmtoolong;	/**< Received frame longer than legal limit (2346 bytes) */
++	uint32	rxfrmtooshrt; /**< Received frame did not contain enough bytes for its frame type */
++	uint32	rxinvmachdr;	/**< Either the protocol version != 0 or frame type not
++				 * data/control/management
++				 */
++	uint32	rxbadfcs;	/**< number of frames for which the CRC check failed in the MAC */
++	uint32	rxbadplcp;	/**< parity check of the PLCP header failed */
++	uint32	rxcrsglitch;	/**< PHY was able to correlate the preamble but not the header */
++	uint32	rxstrt;		/**< Number of received frames with a good PLCP
++				 * (i.e. passing parity check)
++				 */
++	uint32	rxdfrmucastmbss; /* number of received DATA frames with good FCS and matching RA */
++	uint32	rxmfrmucastmbss; /* number of received mgmt frames with good FCS and matching RA */
++	uint32	rxcfrmucast; /**< number of received CNTRL frames with good FCS and matching RA */
++	uint32	rxrtsucast;  /**< number of unicast RTS addressed to the MAC (good FCS) */
++	uint32	rxctsucast;  /**< number of unicast CTS addressed to the MAC (good FCS) */
++	uint32	rxackucast;	/**< number of ucast ACKS received (good FCS) */
++	uint32	rxdfrmocast; /**< number of received DATA frames (good FCS and not matching RA) */
++	uint32	rxmfrmocast; /**< number of received MGMT frames (good FCS and not matching RA) */
++	uint32	rxcfrmocast; /**< number of received CNTRL frame (good FCS and not matching RA) */
++	uint32	rxrtsocast;	/**< number of received RTS not addressed to the MAC */
++	uint32	rxctsocast;	/**< number of received CTS not addressed to the MAC */
++	uint32	rxdfrmmcast;	/**< number of RX Data multicast frames received by the MAC */
++	uint32	rxmfrmmcast;	/**< number of RX Management multicast frames received by the MAC */
++	uint32	rxcfrmmcast;	/**< number of RX Control multicast frames received by the MAC
++				 * (unlikely to see these)
++				 */
++	uint32	rxbeaconmbss;	/**< beacons received from member of BSS */
++	uint32	rxdfrmucastobss; /**< number of unicast frames addressed to the MAC from
++				  * other BSS (WDS FRAME)
++				  */
++	uint32	rxbeaconobss;	/**< beacons received from other BSS */
++	uint32	rxrsptmout;	/**< number of response timeouts for transmitted frames
++				 * expecting a response
++				 */
++	uint32	bcntxcancl;	/**< transmit beacons canceled due to receipt of beacon (IBSS) */
++	uint32	PAD1;
++	uint32	rxf0ovfl;	/**< number of receive fifo 0 overflows */
++	uint32	rxf1ovfl;	/**< Number of receive fifo 1 overflows (obsolete) */
++	uint32	rxf2ovfl;	/**< Number of receive fifo 2 overflows (obsolete) */
++	uint32	txsfovfl;	/**< Number of transmit status fifo overflows (obsolete) */
++	uint32	pmqovfl;	/**< number of PMQ overflows */
++	uint32	rxcgprqfrm;	/**< number of received Probe requests that made it into
++				 * the PRQ fifo
++				 */
++	uint32	rxcgprsqovfl;	/**< Rx Probe Request Que overflow in the AP */
++	uint32	txcgprsfail;	/**< Tx Probe Response Fail. AP sent probe response but did
++				 * not get ACK
++				 */
++	uint32	txcgprssuc;	/**< Tx Probe Response Success (ACK was received) */
++	uint32	prs_timeout;	/**< number of probe requests that were dropped from the PRQ
++				 * fifo because a probe response could not be sent out within
++				 * the time limit defined in M_PRS_MAXTIME
++				 */
++	uint32	rxnack;		/**< obsolete */
++	uint32	frmscons;	/**< obsolete */
++	uint32  txnack;		/**< obsolete */
++	uint32	rxback;		/**< blockack rxcnt */
++	uint32	txback;		/**< blockack txcnt */
++	uint32	bphy_rxcrsglitch;	/**< PHY count of bphy glitches */
++	uint32	rxdrop20s;	/**< drop secondary cnt */
++	uint32	rxtoolate;	/**< receive too late */
++	uint32  bphy_badplcp;	/**< number of bad PLCP reception on BPHY rate */
++} wl_cnt_v_le10_mcst_t;
++
++#define MAX_RX_FIFO 3
++#define WL_RXFIFO_CNT_VERSION  1   /* current version of wl_rxfifo_cnt_t */
++typedef struct {
++	/* Counters for frames received from rx fifos */
++	uint16	version;
++	uint16	length;		/* length of entire structure */
++	uint32	rxf_data[MAX_RX_FIFO];		/* data frames from rx fifo */
++	uint32	rxf_mgmtctl[MAX_RX_FIFO];	/* mgmt/ctl frames from rx fifo */
++} wl_rxfifo_cnt_t;
++
++typedef struct {
++	uint16	version;	/**< see definition of WL_CNT_T_VERSION */
++	uint16	length;		/**< length of entire structure */
++
++	/* transmit stat counters */
++	uint32	txframe;	/**< tx data frames */
++	uint32	txbyte;		/**< tx data bytes */
++	uint32	txretrans;	/**< tx mac retransmits */
++	uint32	txerror;	/**< tx data errors (derived: sum of others) */
++	uint32	txctl;		/**< tx management frames */
++	uint32	txprshort;	/**< tx short preamble frames */
++	uint32	txserr;		/**< tx status errors */
++	uint32	txnobuf;	/**< tx out of buffers errors */
++	uint32	txnoassoc;	/**< tx discard because we're not associated */
++	uint32	txrunt;		/**< tx runt frames */
++	uint32	txchit;		/**< tx header cache hit (fastpath) */
++	uint32	txcmiss;	/**< tx header cache miss (slowpath) */
++
++	/* transmit chip error counters */
++	uint32	txuflo;		/**< tx fifo underflows */
++	uint32	txphyerr;	/**< tx phy errors (indicated in tx status) */
++	uint32	txphycrs;
++
++	/* receive stat counters */
++	uint32	rxframe;	/**< rx data frames */
++	uint32	rxbyte;		/**< rx data bytes */
++	uint32	rxerror;	/**< rx data errors (derived: sum of others) */
++	uint32	rxctl;		/**< rx management frames */
++	uint32	rxnobuf;	/**< rx out of buffers errors */
++	uint32	rxnondata;	/**< rx non data frames in the data channel errors */
++	uint32	rxbadds;	/**< rx bad DS errors */
++	uint32	rxbadcm;	/**< rx bad control or management frames */
++	uint32	rxfragerr;	/**< rx fragmentation errors */
++	uint32	rxrunt;		/**< rx runt frames */
++	uint32	rxgiant;	/**< rx giant frames */
++	uint32	rxnoscb;	/**< rx no scb error */
++	uint32	rxbadproto;	/**< rx invalid frames */
++	uint32	rxbadsrcmac;	/**< rx frames with Invalid Src Mac */
++	uint32	rxbadda;	/**< rx frames tossed for invalid da */
++	uint32	rxfilter;	/**< rx frames filtered out */
++
++	/* receive chip error counters */
++	uint32	rxoflo;		/**< rx fifo overflow errors */
++	uint32	rxuflo[NFIFO];	/**< rx dma descriptor underflow errors */
++
++	uint32	d11cnt_txrts_off;	/**< d11cnt txrts value when reset d11cnt */
++	uint32	d11cnt_rxcrc_off;	/**< d11cnt rxcrc value when reset d11cnt */
++	uint32	d11cnt_txnocts_off;	/**< d11cnt txnocts value when reset d11cnt */
++
++	/* misc counters */
++	uint32	dmade;		/**< tx/rx dma descriptor errors */
++	uint32	dmada;		/**< tx/rx dma data errors */
++	uint32	dmape;		/**< tx/rx dma descriptor protocol errors */
++	uint32	reset;		/**< reset count */
++	uint32	tbtt;		/**< cnts the TBTT int's */
++	uint32	txdmawar;
++	uint32	pkt_callback_reg_fail;	/**< callbacks register failure */
++
++	/* MAC counters: 32-bit version of d11.h's macstat_t */
++	uint32	txallfrm;	/**< total number of frames sent, incl. Data, ACK, RTS, CTS,
++				 * Control Management (includes retransmissions)
++				 */
++	uint32	txrtsfrm;	/**< number of RTS sent out by the MAC */
++	uint32	txctsfrm;	/**< number of CTS sent out by the MAC */
++	uint32	txackfrm;	/**< number of ACK frames sent out */
++	uint32	txdnlfrm;	/**< Not used */
++	uint32	txbcnfrm;	/**< beacons transmitted */
++	uint32	txfunfl[6];	/**< per-fifo tx underflows */
++	uint32	rxtoolate;	/**< receive too late */
++	uint32  txfbw;		/**< transmit at fallback bw (dynamic bw) */
++	uint32	txtplunfl;	/**< Template underflows (mac was too slow to transmit ACK/CTS
++				 * or BCN)
++				 */
++	uint32	txphyerror;	/**< Transmit phy error, type of error is reported in tx-status for
++				 * driver enqueued frames
++				 */
++	uint32	rxfrmtoolong;	/**< Received frame longer than legal limit (2346 bytes) */
++	uint32	rxfrmtooshrt; /**< Received frame did not contain enough bytes for its frame type */
++	uint32	rxinvmachdr;	/**< Either the protocol version != 0 or frame type not
++				 * data/control/management
++				 */
++	uint32	rxbadfcs;	/**< number of frames for which the CRC check failed in the MAC */
++	uint32	rxbadplcp;	/**< parity check of the PLCP header failed */
++	uint32	rxcrsglitch;	/**< PHY was able to correlate the preamble but not the header */
++	uint32	rxstrt;		/**< Number of received frames with a good PLCP
++				 * (i.e. passing parity check)
++				 */
++	uint32	rxdfrmucastmbss; /* Number of received DATA frames with good FCS and matching RA */
++	uint32	rxmfrmucastmbss; /* number of received mgmt frames with good FCS and matching RA */
++	uint32	rxcfrmucast; /**< number of received CNTRL frames with good FCS and matching RA */
++	uint32	rxrtsucast;	/**< number of unicast RTS addressed to the MAC (good FCS) */
++	uint32	rxctsucast;	/**< number of unicast CTS addressed to the MAC (good FCS) */
++	uint32	rxackucast;	/**< number of ucast ACKS received (good FCS) */
++	uint32	rxdfrmocast; /**< number of received DATA frames (good FCS and not matching RA) */
++	uint32	rxmfrmocast; /**< number of received MGMT frames (good FCS and not matching RA) */
++	uint32	rxcfrmocast; /**< number of received CNTRL frame (good FCS and not matching RA) */
++	uint32	rxrtsocast;	/**< number of received RTS not addressed to the MAC */
++	uint32	rxctsocast;	/**< number of received CTS not addressed to the MAC */
++	uint32	rxdfrmmcast;	/**< number of RX Data multicast frames received by the MAC */
++	uint32	rxmfrmmcast;	/**< number of RX Management multicast frames received by the MAC */
++	uint32	rxcfrmmcast;	/**< number of RX Control multicast frames received by the MAC
++				 * (unlikely to see these)
++				 */
++	uint32	rxbeaconmbss;	/**< beacons received from member of BSS */
++	uint32	rxdfrmucastobss; /**< number of unicast frames addressed to the MAC from
++				  * other BSS (WDS FRAME)
++				  */
++	uint32	rxbeaconobss;	/**< beacons received from other BSS */
++	uint32	rxrsptmout;	/**< Number of response timeouts for transmitted frames
++				 * expecting a response
++				 */
++	uint32	bcntxcancl;	/**< transmit beacons canceled due to receipt of beacon (IBSS) */
++	uint32	rxf0ovfl;	/**< Number of receive fifo 0 overflows */
++	uint32	rxf1ovfl;	/**< Number of receive fifo 1 overflows (obsolete) */
++	uint32	rxf2ovfl;	/**< Number of receive fifo 2 overflows (obsolete) */
++	uint32	txsfovfl;	/**< Number of transmit status fifo overflows (obsolete) */
++	uint32	pmqovfl;	/**< Number of PMQ overflows */
++	uint32	rxcgprqfrm;	/**< Number of received Probe requests that made it into
++				 * the PRQ fifo
++				 */
++	uint32	rxcgprsqovfl;	/**< Rx Probe Request Que overflow in the AP */
++	uint32	txcgprsfail;	/**< Tx Probe Response Fail. AP sent probe response but did
++				 * not get ACK
++				 */
++	uint32	txcgprssuc;	/**< Tx Probe Response Success (ACK was received) */
++	uint32	prs_timeout;	/**< Number of probe requests that were dropped from the PRQ
++				 * fifo because a probe response could not be sent out within
++				 * the time limit defined in M_PRS_MAXTIME
++				 */
++	uint32	rxnack;		/**< obsolete */
++	uint32	frmscons;	/**< obsolete */
++	uint32  txnack;		/**< obsolete */
++	uint32	rxback;		/**< blockack rxcnt */
++	uint32	txback;		/**< blockack txcnt */
++
++	/* 802.11 MIB counters, pp. 614 of 802.11 reaff doc. */
++	uint32	txfrag;		/**< dot11TransmittedFragmentCount */
++	uint32	txmulti;	/**< dot11MulticastTransmittedFrameCount */
++	uint32	txfail;		/**< dot11FailedCount */
++	uint32	txretry;	/**< dot11RetryCount */
++	uint32	txretrie;	/**< dot11MultipleRetryCount */
++	uint32	rxdup;		/**< dot11FrameduplicateCount */
++	uint32	txrts;		/**< dot11RTSSuccessCount */
++	uint32	txnocts;	/**< dot11RTSFailureCount */
++	uint32	txnoack;	/**< dot11ACKFailureCount */
++	uint32	rxfrag;		/**< dot11ReceivedFragmentCount */
++	uint32	rxmulti;	/**< dot11MulticastReceivedFrameCount */
++	uint32	rxcrc;		/**< dot11FCSErrorCount */
++	uint32	txfrmsnt;	/**< dot11TransmittedFrameCount (bogus MIB?) */
++	uint32	rxundec;	/**< dot11WEPUndecryptableCount */
++
++	/* WPA2 counters (see rxundec for DecryptFailureCount) */
++	uint32	tkipmicfaill;	/**< TKIPLocalMICFailures */
++	uint32	tkipcntrmsr;	/**< TKIPCounterMeasuresInvoked */
++	uint32	tkipreplay;	/**< TKIPReplays */
++	uint32	ccmpfmterr;	/**< CCMPFormatErrors */
++	uint32	ccmpreplay;	/**< CCMPReplays */
++	uint32	ccmpundec;	/**< CCMPDecryptErrors */
++	uint32	fourwayfail;	/**< FourWayHandshakeFailures */
++	uint32	wepundec;	/**< dot11WEPUndecryptableCount */
++	uint32	wepicverr;	/**< dot11WEPICVErrorCount */
++	uint32	decsuccess;	/**< DecryptSuccessCount */
++	uint32	tkipicverr;	/**< TKIPICVErrorCount */
++	uint32	wepexcluded;	/**< dot11WEPExcludedCount */
++
++	uint32	txchanrej;	/**< Tx frames suppressed due to channel rejection */
++	uint32	psmwds;		/**< Count PSM watchdogs */
++	uint32	phywatchdog;	/**< Count Phy watchdogs (triggered by ucode) */
++
++	/* MBSS counters, AP only */
++	uint32	prq_entries_handled;	/**< PRQ entries read in */
++	uint32	prq_undirected_entries;	/**<    which were bcast bss & ssid */
++	uint32	prq_bad_entries;	/**<    which could not be translated to info */
++	uint32	atim_suppress_count;	/**< TX suppressions on ATIM fifo */
++	uint32	bcn_template_not_ready;	/**< Template marked in use on send bcn ... */
++	uint32	bcn_template_not_ready_done; /**< ...but "DMA done" interrupt rcvd */
++	uint32	late_tbtt_dpc;	/**< TBTT DPC did not happen in time */
++
++	/* per-rate receive stat counters */
++	uint32  rx1mbps;	/**< packets rx at 1Mbps */
++	uint32  rx2mbps;	/**< packets rx at 2Mbps */
++	uint32  rx5mbps5;	/**< packets rx at 5.5Mbps */
++	uint32  rx6mbps;	/**< packets rx at 6Mbps */
++	uint32  rx9mbps;	/**< packets rx at 9Mbps */
++	uint32  rx11mbps;	/**< packets rx at 11Mbps */
++	uint32  rx12mbps;	/**< packets rx at 12Mbps */
++	uint32  rx18mbps;	/**< packets rx at 18Mbps */
++	uint32  rx24mbps;	/**< packets rx at 24Mbps */
++	uint32  rx36mbps;	/**< packets rx at 36Mbps */
++	uint32  rx48mbps;	/**< packets rx at 48Mbps */
++	uint32  rx54mbps;	/**< packets rx at 54Mbps */
++	uint32  rx108mbps;	/**< packets rx at 108mbps */
++	uint32  rx162mbps;	/**< packets rx at 162mbps */
++	uint32  rx216mbps;	/**< packets rx at 216 mbps */
++	uint32  rx270mbps;	/**< packets rx at 270 mbps */
++	uint32  rx324mbps;	/**< packets rx at 324 mbps */
++	uint32  rx378mbps;	/**< packets rx at 378 mbps */
++	uint32  rx432mbps;	/**< packets rx at 432 mbps */
++	uint32  rx486mbps;	/**< packets rx at 486 mbps */
++	uint32  rx540mbps;	/**< packets rx at 540 mbps */
++
++	/* pkteng rx frame stats */
++	uint32	pktengrxducast; /**< unicast frames rxed by the pkteng code */
++	uint32	pktengrxdmcast; /**< multicast frames rxed by the pkteng code */
++
++	uint32	rfdisable;	/**< count of radio disables */
++	uint32	bphy_rxcrsglitch;	/**< PHY count of bphy glitches */
++	uint32  bphy_badplcp;
++
++	uint32	txexptime;	/**< Tx frames suppressed due to timer expiration */
++
++	uint32	txmpdu_sgi;	/**< count for sgi transmit */
++	uint32	rxmpdu_sgi;	/**< count for sgi received */
++	uint32	txmpdu_stbc;	/**< count for stbc transmit */
++	uint32	rxmpdu_stbc;	/**< count for stbc received */
++
++	uint32	rxundec_mcst;	/**< dot11WEPUndecryptableCount */
++
++	/* WPA2 counters (see rxundec for DecryptFailureCount) */
++	uint32	tkipmicfaill_mcst;	/**< TKIPLocalMICFailures */
++	uint32	tkipcntrmsr_mcst;	/**< TKIPCounterMeasuresInvoked */
++	uint32	tkipreplay_mcst;	/**< TKIPReplays */
++	uint32	ccmpfmterr_mcst;	/**< CCMPFormatErrors */
++	uint32	ccmpreplay_mcst;	/**< CCMPReplays */
++	uint32	ccmpundec_mcst;	/**< CCMPDecryptErrors */
++	uint32	fourwayfail_mcst;	/**< FourWayHandshakeFailures */
++	uint32	wepundec_mcst;	/**< dot11WEPUndecryptableCount */
++	uint32	wepicverr_mcst;	/**< dot11WEPICVErrorCount */
++	uint32	decsuccess_mcst;	/**< DecryptSuccessCount */
++	uint32	tkipicverr_mcst;	/**< TKIPICVErrorCount */
++	uint32	wepexcluded_mcst;	/**< dot11WEPExcludedCount */
++
++	uint32	dma_hang;	/**< count for dma hang */
++	uint32	reinit;		/**< count for reinit */
++
++	uint32  pstatxucast;	/**< count of ucast frames xmitted on all psta assoc */
++	uint32  pstatxnoassoc;	/**< count of txnoassoc frames xmitted on all psta assoc */
++	uint32  pstarxucast;	/**< count of ucast frames received on all psta assoc */
++	uint32  pstarxbcmc;	/**< count of bcmc frames received on all psta */
++	uint32  pstatxbcmc;	/**< count of bcmc frames transmitted on all psta */
++
++	uint32  cso_passthrough; /**< hw cso required but passthrough */
++	uint32	cso_normal;	/**< hw cso hdr for normal process */
++	uint32	chained;	/**< number of frames chained */
++	uint32	chainedsz1;	/**< number of chain size 1 frames */
++	uint32	unchained;	/**< number of frames not chained */
++	uint32	maxchainsz;	/**< max chain size so far */
++	uint32	currchainsz;	/**< current chain size */
++	uint32	rxdrop20s;	/**< drop secondary cnt */
++	uint32	pciereset;	/**< Secondary Bus Reset issued by driver */
++	uint32	cfgrestore;	/**< configspace restore by driver */
++	uint32	reinitreason[NREINITREASONCOUNT]; /**< reinitreason counters; 0: Unknown reason */
++	uint32  rxrtry;		/**< num of received packets with retry bit on */
++	uint32	txmpdu;		/**< macstat cnt only valid in ver 11. number of MPDUs txed.  */
++	uint32	rxnodelim;	/**< macstat cnt only valid in ver 11.
++				 * number of occasions that no valid delimiter is detected
++				 * by ampdu parser.
++				 */
++	uint32  rxmpdu_mu;      /**< Number of MU MPDUs received */
++
++	/* detailed control/management frames */
++	uint32	txbar;		/**< Number of TX BAR */
++	uint32	rxbar;		/**< Number of RX BAR */
++	uint32	txpspoll;	/**< Number of TX PS-poll */
++	uint32	rxpspoll;	/**< Number of RX PS-poll */
++	uint32	txnull;		/**< Number of TX NULL_DATA */
++	uint32	rxnull;		/**< Number of RX NULL_DATA */
++	uint32	txqosnull;	/**< Number of TX NULL_QoSDATA */
++	uint32	rxqosnull;	/**< Number of RX NULL_QoSDATA */
++	uint32	txassocreq;	/**< Number of TX ASSOC request */
++	uint32	rxassocreq;	/**< Number of RX ASSOC request */
++	uint32	txreassocreq;	/**< Number of TX REASSOC request */
++	uint32	rxreassocreq;	/**< Number of RX REASSOC request */
++	uint32	txdisassoc;	/**< Number of TX DISASSOC */
++	uint32	rxdisassoc;	/**< Number of RX DISASSOC */
++	uint32	txassocrsp;	/**< Number of TX ASSOC response */
++	uint32	rxassocrsp;	/**< Number of RX ASSOC response */
++	uint32	txreassocrsp;	/**< Number of TX REASSOC response */
++	uint32	rxreassocrsp;	/**< Number of RX REASSOC response */
++	uint32	txauth;		/**< Number of TX AUTH */
++	uint32	rxauth;		/**< Number of RX AUTH */
++	uint32	txdeauth;	/**< Number of TX DEAUTH */
++	uint32	rxdeauth;	/**< Number of RX DEAUTH */
++	uint32	txprobereq;	/**< Number of TX probe request */
++	uint32	rxprobereq;	/**< Number of RX probe request */
++	uint32	txprobersp;	/**< Number of TX probe response */
++	uint32	rxprobersp;	/**< Number of RX probe response */
++	uint32	txaction;	/**< Number of TX action frame */
++	uint32	rxaction;	/**< Number of RX action frame */
++	uint32  ampdu_wds;      /**< Number of AMPDU watchdogs */
++	uint32  txlost;         /**< Number of lost packets reported in txs */
++	uint32  txdatamcast;	/**< Number of TX multicast data packets */
++	uint32  txdatabcast;	/**< Number of TX broadcast data packets */
++	uint32  txbcast;        /* Broadcast TransmittedFrameCount */
++	uint32  txdropped;      /* tx dropped pkts */
++	uint32  rxbcast;        /* BroadcastReceivedFrameCount */
++	uint32  rxdropped;      /* rx dropped pkts (derived: sum of others) */
++
++} wl_cnt_ver_11_t;
++
++typedef struct {
++	uint16  version;    /**< see definition of WL_CNT_T_VERSION */
++	uint16  length;     /**< length of entire structure */
++
++	/* transmit stat counters */
++	uint32  txframe;    /**< tx data frames */
++	uint32  txbyte;     /**< tx data bytes */
++	uint32  txretrans;  /**< tx mac retransmits */
++	uint32  txerror;    /**< tx data errors (derived: sum of others) */
++	uint32  txctl;      /**< tx management frames */
++	uint32  txprshort;  /**< tx short preamble frames */
++	uint32  txserr;     /**< tx status errors */
++	uint32  txnobuf;    /**< tx out of buffers errors */
++	uint32  txnoassoc;  /**< tx discard because we're not associated */
++	uint32  txrunt;     /**< tx runt frames */
++	uint32  txchit;     /**< tx header cache hit (fastpath) */
++	uint32  txcmiss;    /**< tx header cache miss (slowpath) */
++
++	/* transmit chip error counters */
++	uint32  txuflo;     /**< tx fifo underflows */
++	uint32  txphyerr;   /**< tx phy errors (indicated in tx status) */
++	uint32  txphycrs;
++
++	/* receive stat counters */
++	uint32  rxframe;    /**< rx data frames */
++	uint32  rxbyte;     /**< rx data bytes */
++	uint32  rxerror;    /**< rx data errors (derived: sum of others) */
++	uint32  rxctl;      /**< rx management frames */
++	uint32  rxnobuf;    /**< rx out of buffers errors */
++	uint32  rxnondata;  /**< rx non data frames in the data channel errors */
++	uint32  rxbadds;    /**< rx bad DS errors */
++	uint32  rxbadcm;    /**< rx bad control or management frames */
++	uint32  rxfragerr;  /**< rx fragmentation errors */
++	uint32  rxrunt;     /**< rx runt frames */
++	uint32  rxgiant;    /**< rx giant frames */
++	uint32  rxnoscb;    /**< rx no scb error */
++	uint32  rxbadproto; /**< rx invalid frames */
++	uint32  rxbadsrcmac;    /**< rx frames with Invalid Src Mac */
++	uint32  rxbadda;    /**< rx frames tossed for invalid da */
++	uint32  rxfilter;   /**< rx frames filtered out */
++
++	/* receive chip error counters */
++	uint32  rxoflo;     /**< rx fifo overflow errors */
++	uint32  rxuflo[NFIFO];  /**< rx dma descriptor underflow errors */
++
++	uint32  d11cnt_txrts_off;   /**< d11cnt txrts value when reset d11cnt */
++	uint32  d11cnt_rxcrc_off;   /**< d11cnt rxcrc value when reset d11cnt */
++	uint32  d11cnt_txnocts_off; /**< d11cnt txnocts value when reset d11cnt */
++
++	/* misc counters */
++	uint32  dmade;      /**< tx/rx dma descriptor errors */
++	uint32  dmada;      /**< tx/rx dma data errors */
++	uint32  dmape;      /**< tx/rx dma descriptor protocol errors */
++	uint32  reset;      /**< reset count */
++	uint32  tbtt;       /**< cnts the TBTT int's */
++	uint32  txdmawar;
++	uint32  pkt_callback_reg_fail;  /**< callbacks register failure */
++
++	/* MAC counters: 32-bit version of d11.h's macstat_t */
++	uint32  txallfrm;   /**< total number of frames sent, incl. Data, ACK, RTS, CTS,
++			     * Control Management (includes retransmissions)
++			     */
++	uint32  txrtsfrm;   /**< number of RTS sent out by the MAC */
++	uint32  txctsfrm;   /**< number of CTS sent out by the MAC */
++	uint32  txackfrm;   /**< number of ACK frames sent out */
++	uint32  txdnlfrm;   /**< Not used */
++	uint32  txbcnfrm;   /**< beacons transmitted */
++	uint32  txfunfl[6]; /**< per-fifo tx underflows */
++	uint32	rxtoolate;	/**< receive too late */
++	uint32  txfbw;	    /**< transmit at fallback bw (dynamic bw) */
++	uint32  txtplunfl;  /**< Template underflows (mac was too slow to transmit ACK/CTS
++			     * or BCN)
++			     */
++	uint32  txphyerror; /**< Transmit phy error, type of error is reported in tx-status for
++			     * driver enqueued frames
++			     */
++	uint32  rxfrmtoolong;   /**< Received frame longer than legal limit (2346 bytes) */
++	uint32  rxfrmtooshrt; /**< Received frame did not contain enough bytes for its frame type */
++	uint32  rxinvmachdr;    /**< Either the protocol version != 0 or frame type not
++				 * data/control/management
++			   */
++	uint32  rxbadfcs;   /**< number of frames for which the CRC check failed in the MAC */
++	uint32  rxbadplcp;  /**< parity check of the PLCP header failed */
++	uint32  rxcrsglitch;    /**< PHY was able to correlate the preamble but not the header */
++	uint32  rxstrt;     /**< Number of received frames with a good PLCP
++			     * (i.e. passing parity check)
++			     */
++	uint32  rxdfrmucastmbss; /**< # of received DATA frames with good FCS and matching RA */
++	uint32  rxmfrmucastmbss; /**< # of received mgmt frames with good FCS and matching RA */
++	uint32  rxcfrmucast;     /**< # of received CNTRL frames with good FCS and matching RA */
++	uint32  rxrtsucast; /**< number of unicast RTS addressed to the MAC (good FCS) */
++	uint32  rxctsucast; /**< number of unicast CTS addressed to the MAC (good FCS) */
++	uint32  rxackucast; /**< number of ucast ACKS received (good FCS) */
++	uint32  rxdfrmocast;    /**< # of received DATA frames (good FCS and not matching RA) */
++	uint32  rxmfrmocast;    /**< # of received MGMT frames (good FCS and not matching RA) */
++	uint32  rxcfrmocast;    /**< # of received CNTRL frame (good FCS and not matching RA) */
++	uint32  rxrtsocast; /**< number of received RTS not addressed to the MAC */
++	uint32  rxctsocast; /**< number of received CTS not addressed to the MAC */
++	uint32  rxdfrmmcast;    /**< number of RX Data multicast frames received by the MAC */
++	uint32  rxmfrmmcast;    /**< number of RX Management multicast frames received by the MAC */
++	uint32  rxcfrmmcast;    /**< number of RX Control multicast frames received by the MAC
++				 * (unlikely to see these)
++				 */
++	uint32  rxbeaconmbss;   /**< beacons received from member of BSS */
++	uint32  rxdfrmucastobss; /**< number of unicast frames addressed to the MAC from
++				  * other BSS (WDS FRAME)
++				  */
++	uint32  rxbeaconobss;   /**< beacons received from other BSS */
++	uint32  rxrsptmout; /**< Number of response timeouts for transmitted frames
++			     * expecting a response
++			     */
++	uint32  bcntxcancl; /**< transmit beacons canceled due to receipt of beacon (IBSS) */
++	uint32  rxf0ovfl;   /**< Number of receive fifo 0 overflows */
++	uint32  rxf1ovfl;   /**< Number of receive fifo 1 overflows (obsolete) */
++	uint32  rxf2ovfl;   /**< Number of receive fifo 2 overflows (obsolete) */
++	uint32  txsfovfl;   /**< Number of transmit status fifo overflows (obsolete) */
++	uint32  pmqovfl;    /**< Number of PMQ overflows */
++	uint32  rxcgprqfrm; /**< Number of received Probe requests that made it into
++			     * the PRQ fifo
++			     */
++	uint32  rxcgprsqovfl;   /**< Rx Probe Request Que overflow in the AP */
++	uint32  txcgprsfail;    /**< Tx Probe Response Fail. AP sent probe response but did
++				 * not get ACK
++				 */
++	uint32  txcgprssuc; /**< Tx Probe Response Success (ACK was received) */
++	uint32  prs_timeout;    /**< Number of probe requests that were dropped from the PRQ
++				 * fifo because a probe response could not be sent out within
++				 * the time limit defined in M_PRS_MAXTIME
++				 */
++	uint32  rxnack;
++	uint32  frmscons;
++	uint32  txnack;		/**< obsolete */
++	uint32	rxback;		/**< blockack rxcnt */
++	uint32	txback;		/**< blockack txcnt */
++
++	/* 802.11 MIB counters, pp. 614 of 802.11 reaff doc. */
++	uint32  txfrag;     /**< dot11TransmittedFragmentCount */
++	uint32  txmulti;    /**< dot11MulticastTransmittedFrameCount */
++	uint32  txfail;     /**< dot11FailedCount */
++	uint32  txretry;    /**< dot11RetryCount */
++	uint32  txretrie;   /**< dot11MultipleRetryCount */
++	uint32  rxdup;      /**< dot11FrameduplicateCount */
++	uint32  txrts;      /**< dot11RTSSuccessCount */
++	uint32  txnocts;    /**< dot11RTSFailureCount */
++	uint32  txnoack;    /**< dot11ACKFailureCount */
++	uint32  rxfrag;     /**< dot11ReceivedFragmentCount */
++	uint32  rxmulti;    /**< dot11MulticastReceivedFrameCount */
++	uint32  rxcrc;      /**< dot11FCSErrorCount */
++	uint32  txfrmsnt;   /**< dot11TransmittedFrameCount (bogus MIB?) */
++	uint32  rxundec;    /**< dot11WEPUndecryptableCount */
++
++	/* WPA2 counters (see rxundec for DecryptFailureCount) */
++	uint32  tkipmicfaill;   /**< TKIPLocalMICFailures */
++	uint32  tkipcntrmsr;    /**< TKIPCounterMeasuresInvoked */
++	uint32  tkipreplay; /**< TKIPReplays */
++	uint32  ccmpfmterr; /**< CCMPFormatErrors */
++	uint32  ccmpreplay; /**< CCMPReplays */
++	uint32  ccmpundec;  /**< CCMPDecryptErrors */
++	uint32  fourwayfail;    /**< FourWayHandshakeFailures */
++	uint32  wepundec;   /**< dot11WEPUndecryptableCount */
++	uint32  wepicverr;  /**< dot11WEPICVErrorCount */
++	uint32  decsuccess; /**< DecryptSuccessCount */
++	uint32  tkipicverr; /**< TKIPICVErrorCount */
++	uint32  wepexcluded;    /**< dot11WEPExcludedCount */
++
++	uint32  rxundec_mcst;   /**< dot11WEPUndecryptableCount */
++
++	/* WPA2 counters (see rxundec for DecryptFailureCount) */
++	uint32  tkipmicfaill_mcst;  /**< TKIPLocalMICFailures */
++	uint32  tkipcntrmsr_mcst;   /**< TKIPCounterMeasuresInvoked */
++	uint32  tkipreplay_mcst;    /**< TKIPReplays */
++	uint32  ccmpfmterr_mcst;    /**< CCMPFormatErrors */
++	uint32  ccmpreplay_mcst;    /**< CCMPReplays */
++	uint32  ccmpundec_mcst; /**< CCMPDecryptErrors */
++	uint32  fourwayfail_mcst;   /**< FourWayHandshakeFailures */
++	uint32  wepundec_mcst;  /**< dot11WEPUndecryptableCount */
++	uint32  wepicverr_mcst; /**< dot11WEPICVErrorCount */
++	uint32  decsuccess_mcst;    /**< DecryptSuccessCount */
++	uint32  tkipicverr_mcst;    /**< TKIPICVErrorCount */
++	uint32  wepexcluded_mcst;   /**< dot11WEPExcludedCount */
++
++	uint32  txchanrej;  /**< Tx frames suppressed due to channel rejection */
++	uint32  txexptime;  /**< Tx frames suppressed due to timer expiration */
++	uint32  psmwds;     /**< Count PSM watchdogs */
++	uint32  phywatchdog;    /**< Count Phy watchdogs (triggered by ucode) */
++
++	/* MBSS counters, AP only */
++	uint32  prq_entries_handled;    /**< PRQ entries read in */
++	uint32  prq_undirected_entries; /**<    which were bcast bss & ssid */
++	uint32  prq_bad_entries;    /**<    which could not be translated to info */
++	uint32  atim_suppress_count;    /**< TX suppressions on ATIM fifo */
++	uint32  bcn_template_not_ready; /**< Template marked in use on send bcn ... */
++	uint32  bcn_template_not_ready_done; /**< ...but "DMA done" interrupt rcvd */
++	uint32  late_tbtt_dpc;  /**< TBTT DPC did not happen in time */
++
++	/* per-rate receive stat counters */
++	uint32  rx1mbps;    /**< packets rx at 1Mbps */
++	uint32  rx2mbps;    /**< packets rx at 2Mbps */
++	uint32  rx5mbps5;   /**< packets rx at 5.5Mbps */
++	uint32  rx6mbps;    /**< packets rx at 6Mbps */
++	uint32  rx9mbps;    /**< packets rx at 9Mbps */
++	uint32  rx11mbps;   /**< packets rx at 11Mbps */
++	uint32  rx12mbps;   /**< packets rx at 12Mbps */
++	uint32  rx18mbps;   /**< packets rx at 18Mbps */
++	uint32  rx24mbps;   /**< packets rx at 24Mbps */
++	uint32  rx36mbps;   /**< packets rx at 36Mbps */
++	uint32  rx48mbps;   /**< packets rx at 48Mbps */
++	uint32  rx54mbps;   /**< packets rx at 54Mbps */
++	uint32  rx108mbps;  /**< packets rx at 108mbps */
++	uint32  rx162mbps;  /**< packets rx at 162mbps */
++	uint32  rx216mbps;  /**< packets rx at 216 mbps */
++	uint32  rx270mbps;  /**< packets rx at 270 mbps */
++	uint32  rx324mbps;  /**< packets rx at 324 mbps */
++	uint32  rx378mbps;  /**< packets rx at 378 mbps */
++	uint32  rx432mbps;  /**< packets rx at 432 mbps */
++	uint32  rx486mbps;  /**< packets rx at 486 mbps */
++	uint32  rx540mbps;  /**< packets rx at 540 mbps */
++
++	/* pkteng rx frame stats */
++	uint32  pktengrxducast; /**< unicast frames rxed by the pkteng code */
++	uint32  pktengrxdmcast; /**< multicast frames rxed by the pkteng code */
++
++	uint32  rfdisable;  /**< count of radio disables */
++	uint32  bphy_rxcrsglitch;   /**< PHY count of bphy glitches */
++	uint32  bphy_badplcp;
++
++	uint32  txmpdu_sgi; /**< count for sgi transmit */
++	uint32  rxmpdu_sgi; /**< count for sgi received */
++	uint32  txmpdu_stbc;    /**< count for stbc transmit */
++	uint32  rxmpdu_stbc;    /**< count for stbc received */
++
++	uint32	rxdrop20s;	/**< drop secondary cnt */
++} wl_cnt_ver_6_t;
++
++#define	WL_DELTA_STATS_T_VERSION	2	/**< current version of wl_delta_stats_t struct */
++
++typedef struct {
++	uint16 version;     /**< see definition of WL_DELTA_STATS_T_VERSION */
++	uint16 length;      /**< length of entire structure */
++
++	/* transmit stat counters */
++	uint32 txframe;     /**< tx data frames */
++	uint32 txbyte;      /**< tx data bytes */
++	uint32 txretrans;   /**< tx mac retransmits */
++	uint32 txfail;      /**< tx failures */
++
++	/* receive stat counters */
++	uint32 rxframe;     /**< rx data frames */
++	uint32 rxbyte;      /**< rx data bytes */
++
++	/* per-rate receive stat counters */
++	uint32  rx1mbps;	/**< packets rx at 1Mbps */
++	uint32  rx2mbps;	/**< packets rx at 2Mbps */
++	uint32  rx5mbps5;	/**< packets rx at 5.5Mbps */
++	uint32  rx6mbps;	/**< packets rx at 6Mbps */
++	uint32  rx9mbps;	/**< packets rx at 9Mbps */
++	uint32  rx11mbps;	/**< packets rx at 11Mbps */
++	uint32  rx12mbps;	/**< packets rx at 12Mbps */
++	uint32  rx18mbps;	/**< packets rx at 18Mbps */
++	uint32  rx24mbps;	/**< packets rx at 24Mbps */
++	uint32  rx36mbps;	/**< packets rx at 36Mbps */
++	uint32  rx48mbps;	/**< packets rx at 48Mbps */
++	uint32  rx54mbps;	/**< packets rx at 54Mbps */
++	uint32  rx108mbps;	/**< packets rx at 108mbps */
++	uint32  rx162mbps;	/**< packets rx at 162mbps */
++	uint32  rx216mbps;	/**< packets rx at 216 mbps */
++	uint32  rx270mbps;	/**< packets rx at 270 mbps */
++	uint32  rx324mbps;	/**< packets rx at 324 mbps */
++	uint32  rx378mbps;	/**< packets rx at 378 mbps */
++	uint32  rx432mbps;	/**< packets rx at 432 mbps */
++	uint32  rx486mbps;	/**< packets rx at 486 mbps */
++	uint32  rx540mbps;	/**< packets rx at 540 mbps */
++
++	/* phy stats */
++	uint32 rxbadplcp;
++	uint32 rxcrsglitch;
++	uint32 bphy_rxcrsglitch;
++	uint32 bphy_badplcp;
++
++} wl_delta_stats_t;
++
++/* Partial statistics counter report */
++#define WL_CNT_CTL_MGT_FRAMES	0
++
++typedef struct {
++	uint16	type;
++	uint16	len;
++
++	/* detailed control/management frames */
++	uint32	txnull;
++	uint32	rxnull;
++	uint32	txqosnull;
++	uint32	rxqosnull;
++	uint32	txassocreq;
++	uint32	rxassocreq;
++	uint32	txreassocreq;
++	uint32	rxreassocreq;
++	uint32	txdisassoc;
++	uint32	rxdisassoc;
++	uint32	txassocrsp;
++	uint32	rxassocrsp;
++	uint32	txreassocrsp;
++	uint32	rxreassocrsp;
++	uint32	txauth;
++	uint32	rxauth;
++	uint32	txdeauth;
++	uint32	rxdeauth;
++	uint32	txprobereq;
++	uint32	rxprobereq;
++	uint32	txprobersp;
++	uint32	rxprobersp;
++	uint32	txaction;
++	uint32	rxaction;
++	uint32	txrts;
++	uint32	rxrts;
++	uint32	txcts;
++	uint32	rxcts;
++	uint32	txack;
++	uint32	rxack;
++	uint32	txbar;
++	uint32	rxbar;
++	uint32	txback;
++	uint32	rxback;
++	uint32	txpspoll;
++	uint32	rxpspoll;
++} wl_ctl_mgt_cnt_t;
++
++typedef struct {
++	uint32 packets;
++	uint32 bytes;
++} wl_traffic_stats_t;
++
++typedef struct {
++	uint16	version;	/**< see definition of WL_WME_CNT_VERSION */
++	uint16	length;		/**< length of entire structure */
++
++	wl_traffic_stats_t tx[AC_COUNT];	/**< Packets transmitted */
++	wl_traffic_stats_t tx_failed[AC_COUNT];	/**< Packets dropped or failed to transmit */
++	wl_traffic_stats_t rx[AC_COUNT];	/**< Packets received */
++	wl_traffic_stats_t rx_failed[AC_COUNT];	/**< Packets failed to receive */
++
++	wl_traffic_stats_t forward[AC_COUNT];	/**< Packets forwarded by AP */
++
++	wl_traffic_stats_t tx_expired[AC_COUNT]; /**< packets dropped due to lifetime expiry */
++
++} wl_wme_cnt_t;
++
++struct wl_msglevel2 {
++	uint32 low;
++	uint32 high;
++};
++
++#define WL_ICMP_IPV6_CFG_VERSION         1
++#define WL_ICMP_IPV6_CLEAR_ALL           (1 << 0)
++
++typedef struct wl_icmp_ipv6_cfg {
++	uint16 version;
++	uint16 length;
++	uint16 fixed_length;
++	uint16 flags;
++	uint32 num_ipv6;
++	/* num_ipv6 to follow */
++	struct ipv6_addr host_ipv6[];
++} wl_icmp_ipv6_cfg_t;
++
++#define WL_ICMP_CFG_IPV6_FIXED_LEN      OFFSETOF(wl_icmp_ipv6_cfg_t, host_ipv6)
++#define WL_ICMP_CFG_IPV6_LEN(count)    (WL_ICMP_CFG_IPV6_FIXED_LEN + \
++					((count) * sizeof(struct ipv6_addr)))
++
++typedef struct wl_mkeep_alive_pkt {
++	uint16	version; /* Version for mkeep_alive */
++	uint16	length; /* length of fixed parameters in the structure */
++	uint32	period_msec; /* high bit on means immediate send */
++	uint16	len_bytes;
++	uint8	keep_alive_id; /* 0 - 3 for N = 4 */
++	uint8	data[1];
++} wl_mkeep_alive_pkt_t;
++
++#define WL_MKEEP_ALIVE_VERSION		1
++#define WL_MKEEP_ALIVE_FIXED_LEN	OFFSETOF(wl_mkeep_alive_pkt_t, data)
++#define WL_MKEEP_ALIVE_PRECISION	500
++#define WL_MKEEP_ALIVE_PERIOD_MASK  0x7FFFFFFF
++#define WL_MKEEP_ALIVE_IMMEDIATE    0x80000000
++
++/** TCP Keep-Alive conn struct */
++typedef struct wl_mtcpkeep_alive_conn_pkt {
++	struct ether_addr saddr;		/**< src mac address */
++	struct ether_addr daddr;		/**< dst mac address */
++	struct ipv4_addr sipaddr;		/**< source IP addr */
++	struct ipv4_addr dipaddr;		/**< dest IP addr */
++	uint16 sport;				/**< src port */
++	uint16 dport;				/**< dest port */
++	uint32 seq;				/**< seq number */
++	uint32 ack;				/**< ACK number */
++	uint16 tcpwin;				/**< TCP window */
++	uint16 PAD;
++} wl_mtcpkeep_alive_conn_pkt_t;
++
++/** TCP Keep-Alive interval struct */
++typedef struct wl_mtcpkeep_alive_timers_pkt {
++	uint16 interval;		/**< interval timer */
++	uint16 retry_interval;		/**< retry_interval timer */
++	uint16 retry_count;		/**< retry_count */
++} wl_mtcpkeep_alive_timers_pkt_t;
++
++typedef struct wake_info {
++	uint32 wake_reason;
++	uint32 wake_info_len;		/**< size of packet */
++	uint8  packet[];
++} wake_info_t;
++
++typedef struct wake_pkt {
++	uint32 wake_pkt_len;		/**< size of packet */
++	uint8  packet[];
++} wake_pkt_t;
++
++
++#define WL_MTCPKEEP_ALIVE_VERSION		1
++
++/* #ifdef WLBA */
++
++#define WLC_BA_CNT_VERSION  1   /**< current version of wlc_ba_cnt_t */
++
++/** block ack related stats */
++typedef struct wlc_ba_cnt {
++	uint16  version;    /**< WLC_BA_CNT_VERSION */
++	uint16  length;     /**< length of entire structure */
++
++	/* transmit stat counters */
++	uint32 txpdu;       /**< pdus sent */
++	uint32 txsdu;       /**< sdus sent */
++	uint32 txfc;        /**< tx side flow controlled packets */
++	uint32 txfci;       /**< tx side flow control initiated */
++	uint32 txretrans;   /**< retransmitted pdus */
++	uint32 txbatimer;   /**< ba resend due to timer */
++	uint32 txdrop;      /**< dropped packets */
++	uint32 txaddbareq;  /**< addba req sent */
++	uint32 txaddbaresp; /**< addba resp sent */
++	uint32 txdelba;     /**< delba sent */
++	uint32 txba;        /**< ba sent */
++	uint32 txbar;       /**< bar sent */
++	uint32 txpad[4];    /**< future */
++
++	/* receive side counters */
++	uint32 rxpdu;       /**< pdus recd */
++	uint32 rxqed;       /**< pdus buffered before sending up */
++	uint32 rxdup;       /**< duplicate pdus */
++	uint32 rxnobuf;     /**< pdus discarded due to no buf */
++	uint32 rxaddbareq;  /**< addba req recd */
++	uint32 rxaddbaresp; /**< addba resp recd */
++	uint32 rxdelba;     /**< delba recd */
++	uint32 rxba;        /**< ba recd */
++	uint32 rxbar;       /**< bar recd */
++	uint32 rxinvba;     /**< invalid ba recd */
++	uint32 rxbaholes;   /**< ba recd with holes */
++	uint32 rxunexp;     /**< unexpected packets */
++	uint32 rxpad[4];    /**< future */
++} wlc_ba_cnt_t;
++/* #endif  WLBA */
++
++/** structure for per-tid ampdu control */
++struct ampdu_tid_control {
++	uint8 tid;			/* tid */
++	uint8 enable;			/* enable/disable */
++};
++
++/** struct for ampdu tx/rx aggregation control */
++struct ampdu_aggr {
++	int8 aggr_override;	/**< aggr overrided by dongle. Not to be set by host. */
++	uint16 conf_TID_bmap;	/**< bitmap of TIDs to configure */
++	uint16 enab_TID_bmap;	/**< enable/disable per TID */
++};
++
++/** structure for identifying ea/tid for sending addba/delba */
++struct ampdu_ea_tid {
++	struct ether_addr ea;		/**< Station address */
++	uint8 tid;			/**< tid */
++	uint8 initiator;	/**< 0 is recipient, 1 is originator */
++};
++
++/** structure for identifying retry/tid for retry_limit_tid/rr_retry_limit_tid */
++struct ampdu_retry_tid {
++	uint8 tid;	/**< tid */
++	uint8 retry;	/**< retry value */
++};
++
++#define BDD_FNAME_LEN       32  /**< Max length of friendly name */
++typedef struct bdd_fname {
++	uint8 len;          /**< length of friendly name */
++	uchar name[BDD_FNAME_LEN];  /**< friendly name */
++} bdd_fname_t;
++
++/* structure for addts arguments */
++/** For ioctls that take a list of TSPEC */
++struct tslist {
++	int32 count;			/**< number of tspecs */
++	struct tsinfo_arg tsinfo[];	/**< variable length array of tsinfo */
++};
++
++/* WLTDLS */
++/**structure for tdls iovars */
++typedef struct tdls_iovar {
++	struct ether_addr ea;		/**< Station address */
++	uint8 mode;			/**< mode: depends on iovar */
++	uint8 PAD;
++	chanspec_t chanspec;
++	uint16 PAD;
++	uint32 pad;			/**< future */
++} tdls_iovar_t;
++
++#define TDLS_WFD_IE_SIZE		512
++/**structure for tdls wfd ie */
++typedef struct tdls_wfd_ie_iovar {
++	struct ether_addr ea;		/**< Station address */
++	uint8 mode;
++	uint8 PAD;
++	uint16 length;
++	uint8 data[TDLS_WFD_IE_SIZE];
++} tdls_wfd_ie_iovar_t;
++/* #endif WLTDLS */
++
++/** structure for addts/delts arguments */
++typedef struct tspec_arg {
++	uint16 version;			/**< see definition of TSPEC_ARG_VERSION */
++	uint16 length;			/**< length of entire structure */
++	uint32 flag;			/**< bit field */
++	/* TSPEC Arguments */
++	struct tsinfo_arg tsinfo;	/**< TS Info bit field */
++	uint8  PAD;
++	uint16 nom_msdu_size;		/**< (Nominal or fixed) MSDU Size (bytes) */
++	uint16 max_msdu_size;		/**< Maximum MSDU Size (bytes) */
++	uint32 min_srv_interval;		/**< Minimum Service Interval (us) */
++	uint32 max_srv_interval;		/**< Maximum Service Interval (us) */
++	uint32 inactivity_interval;	/**< Inactivity Interval (us) */
++	uint32 suspension_interval;	/**< Suspension Interval (us) */
++	uint32 srv_start_time;		/**< Service Start Time (us) */
++	uint32 min_data_rate;		/**< Minimum Data Rate (bps) */
++	uint32 mean_data_rate;		/**< Mean Data Rate (bps) */
++	uint32 peak_data_rate;		/**< Peak Data Rate (bps) */
++	uint32 max_burst_size;		/**< Maximum Burst Size (bytes) */
++	uint32 delay_bound;		/**< Delay Bound (us) */
++	uint32 min_phy_rate;		/**< Minimum PHY Rate (bps) */
++	uint16 surplus_bw;		/**< Surplus Bandwidth Allowance (range 1.0 to 8.0) */
++	uint16 medium_time;		/**< Medium Time (32 us/s periods) */
++	uint8 dialog_token;		/**< dialog token */
++	uint8  PAD[3];
++} tspec_arg_t;
++
++/** tspec arg for desired station */
++typedef	struct tspec_per_sta_arg {
++	struct ether_addr ea;
++	uint8  PAD[2];
++	struct tspec_arg ts;
++} tspec_per_sta_arg_t;
++
++/** structure for max bandwidth for each access category */
++typedef	struct wme_max_bandwidth {
++	uint32	ac[AC_COUNT];	/**< max bandwidth for each access category */
++} wme_max_bandwidth_t;
++
++#define WL_WME_MBW_PARAMS_IO_BYTES (sizeof(wme_max_bandwidth_t))
++
++/* current version of wl_tspec_arg_t struct */
++#define	TSPEC_ARG_VERSION		2	/**< current version of wl_tspec_arg_t struct */
++#define TSPEC_ARG_LENGTH		55	/**< argument length from tsinfo to medium_time */
++#define TSPEC_DEFAULT_DIALOG_TOKEN	42	/**< default dialog token */
++#define TSPEC_DEFAULT_SBW_FACTOR	0x3000	/**< default surplus bw */
++
++
++#define WL_WOWL_KEEPALIVE_MAX_PACKET_SIZE  80
++#define WLC_WOWL_MAX_KEEPALIVE	2
++
++/** Packet lifetime configuration per ac */
++typedef struct wl_lifetime {
++	uint32 ac;	        /**< access class */
++	uint32 lifetime;    /**< Packet lifetime value in ms */
++} wl_lifetime_t;
++
++/** Management time configuration */
++typedef struct wl_lifetime_mg {
++	uint32 mgmt_bitmap;	/**< Mgmt subtype */
++	uint32 lifetime;    /**< Packet lifetime value in us */
++} wl_lifetime_mg_t;
++
++/* MAC Sample Capture related */
++#define	WL_MACCAPTR_DEFSTART_PTR	0xA00
++#define	WL_MACCAPTR_DEFSTOP_PTR		0xA3F
++#define	WL_MACCAPTR_DEFSZ		0x3F
++
++#define WL_MACCAPTR_DEF_MASK		0xFFFFFFFF
++
++typedef enum {
++	WL_MACCAPT_TRIG		= 0,
++	WL_MACCAPT_STORE	= 1,
++	WL_MACCAPT_TRANS	= 2,
++	WL_MACCAPT_MATCH	= 3
++} maccaptr_optn;
++
++typedef enum {
++	WL_MACCAPT_STRT	= 1,
++	WL_MACCAPT_STOP	= 2,
++	WL_MACCAPT_RST	= 3
++} maccaptr_cmd_t;
++
++/* MAC Sample Capture Set-up Paramters */
++typedef struct wl_maccapture_params {
++	uint8	gpio_sel;
++	uint8	la_mode;	/* TRUE: GPIO Out Enabled */
++	uint8 	PAD[2];
++	uint32	start_ptr;	/* Start address to store */
++	uint32	stop_ptr;	/* Stop address to store */
++	uint8	optn_bmp;	/* Options */
++	uint8 	PAD[3];
++	uint32	tr_mask;	/* Trigger Mask */
++	uint32	tr_val;		/* Trigger Value */
++	uint32	s_mask;		/* Store Mode Mask */
++	uint32	x_mask;		/* Trans. Mode Mask */
++	uint32	m_mask;		/* Match Mode Mask */
++	uint32	m_val;		/* Match Value */
++	maccaptr_cmd_t cmd;	/* Start / Stop */
++} wl_maccapture_params_t;
++
++/** Channel Switch Announcement param */
++typedef struct wl_chan_switch {
++	uint8 mode;		/**< value 0 or 1 */
++	uint8 count;		/**< count # of beacons before switching */
++	chanspec_t chspec;	/**< chanspec */
++	uint8 reg;		/**< regulatory class */
++	uint8 frame_type;		/**< csa frame type, unicast or broadcast */
++} wl_chan_switch_t;
++
++enum {
++	PFN_LIST_ORDER,
++	PFN_RSSI
++};
++
++enum {
++	DISABLE,
++	ENABLE
++};
++
++enum {
++	OFF_ADAPT,
++	SMART_ADAPT,
++	STRICT_ADAPT,
++	SLOW_ADAPT
++};
++
++#define SORT_CRITERIA_BIT		0
++#define AUTO_NET_SWITCH_BIT		1
++#define ENABLE_BKGRD_SCAN_BIT		2
++#define IMMEDIATE_SCAN_BIT		3
++#define	AUTO_CONNECT_BIT		4
++#define	ENABLE_BD_SCAN_BIT		5
++#define ENABLE_ADAPTSCAN_BIT		6
++#define IMMEDIATE_EVENT_BIT		8
++#define SUPPRESS_SSID_BIT		9
++#define ENABLE_NET_OFFLOAD_BIT		10
++/** report found/lost events for SSID and BSSID networks seperately */
++#define REPORT_SEPERATELY_BIT		11
++
++#define SORT_CRITERIA_MASK	0x0001
++#define AUTO_NET_SWITCH_MASK	0x0002
++#define ENABLE_BKGRD_SCAN_MASK	0x0004
++#define IMMEDIATE_SCAN_MASK	0x0008
++#define AUTO_CONNECT_MASK	0x0010
++
++#define ENABLE_BD_SCAN_MASK	0x0020
++#define ENABLE_ADAPTSCAN_MASK	0x00c0
++#define IMMEDIATE_EVENT_MASK	0x0100
++#define SUPPRESS_SSID_MASK	0x0200
++#define ENABLE_NET_OFFLOAD_MASK	0x0400
++/** report found/lost events for SSID and BSSID networks seperately */
++#define REPORT_SEPERATELY_MASK	0x0800
++
++#define PFN_VERSION			2
++
++#define PFN_COMPLETE			1
++#define PFN_INCOMPLETE			0
++
++#define DEFAULT_BESTN			2
++#define DEFAULT_MSCAN			0
++#define DEFAULT_REPEAT			10
++#define DEFAULT_EXP			2
++
++#define PFN_PARTIAL_SCAN_BIT		0
++#define PFN_PARTIAL_SCAN_MASK		1
++
++#define PFN_SWC_RSSI_WINDOW_MAX   8
++#define PFN_SWC_MAX_NUM_APS       16
++#define PFN_HOTLIST_MAX_NUM_APS   64
++
++#define MAX_EPNO_HIDDEN_SSID    8
++#define MAX_WHITELIST_SSID      2
++
++/* Version 1 and 2 for various scan results structures defined below */
++#define PFN_SCANRESULTS_VERSION_V1	1
++#define PFN_SCANRESULTS_VERSION_V2	2
++
++/** PFN network info structure */
++typedef struct wl_pfn_subnet_info_v1 {
++	struct ether_addr BSSID;
++	uint8	channel; /**< channel number only */
++	uint8	SSID_len;
++	uint8	SSID[32];
++} wl_pfn_subnet_info_v1_t;
++
++typedef struct wl_pfn_subnet_info_v2 {
++	struct ether_addr BSSID;
++	uint8   channel; /**< channel number only */
++	uint8   SSID_len;
++	union {
++		uint8   SSID[32];
++		uint16 index;
++	} u;
++} wl_pfn_subnet_info_v2_t;
++
++typedef struct wl_pfn_net_info_v1 {
++	wl_pfn_subnet_info_v1_t pfnsubnet;
++	int16	RSSI; /**< receive signal strength (in dBm) */
++	uint16	timestamp; /**< age in seconds */
++} wl_pfn_net_info_v1_t;
++
++typedef struct wl_pfn_net_info_v2 {
++	wl_pfn_subnet_info_v2_t pfnsubnet;
++	int16   RSSI; /**< receive signal strength (in dBm) */
++	uint16  timestamp; /**< age in seconds */
++} wl_pfn_net_info_v2_t;
++
++/* Version 1 and 2 for various lbest scan results structures below */
++#define PFN_LBEST_SCAN_RESULT_VERSION_V1 1
++#define PFN_LBEST_SCAN_RESULT_VERSION_V2 2
++
++#define MAX_CHBKT_PER_RESULT		4
++
++typedef struct wl_pfn_lnet_info_v1 {
++	wl_pfn_subnet_info_v1_t pfnsubnet; /**< BSSID + channel + SSID len + SSID */
++	uint16	flags; /**< partial scan, etc */
++	int16	RSSI; /**< receive signal strength (in dBm) */
++	uint32	timestamp; /**< age in miliseconds */
++	uint16	rtt0; /**< estimated distance to this AP in centimeters */
++	uint16	rtt1; /**< standard deviation of the distance to this AP in centimeters */
++} wl_pfn_lnet_info_v1_t;
++
++typedef struct wl_pfn_lnet_info_v2 {
++	wl_pfn_subnet_info_v2_t pfnsubnet; /**< BSSID + channel + SSID len + SSID */
++	uint16  flags; /**< partial scan, etc */
++	int16   RSSI; /**< receive signal strength (in dBm) */
++	uint32  timestamp; /**< age in miliseconds */
++	uint16  rtt0; /**< estimated distance to this AP in centimeters */
++	uint16  rtt1; /**< standard deviation of the distance to this AP in centimeters */
++} wl_pfn_lnet_info_v2_t;
++
++typedef struct wl_pfn_lscanresults_v1 {
++	uint32 version;
++	uint32 status;
++	uint32 count;
++	wl_pfn_lnet_info_v1_t netinfo[1];
++} wl_pfn_lscanresults_v1_t;
++
++typedef struct wl_pfn_lscanresults_v2 {
++	uint32 version;
++	uint16 status;
++	uint16 count;
++	uint32 scan_ch_buckets[MAX_CHBKT_PER_RESULT];
++	wl_pfn_lnet_info_v2_t netinfo[1];
++} wl_pfn_lscanresults_v2_t;
++
++/**this is used to report on 1-* pfn scan results */
++typedef struct wl_pfn_scanresults_v1 {
++	uint32 version;
++	uint32 status;
++	uint32 count;
++	wl_pfn_net_info_v1_t netinfo[1];
++} wl_pfn_scanresults_v1_t;
++
++typedef struct wl_pfn_scanresults_v2 {
++	uint32 version;
++	uint32 status;
++	uint32 count;
++	uint32 scan_ch_bucket;
++	wl_pfn_net_info_v2_t netinfo[1];
++} wl_pfn_scanresults_v2_t;
++
++typedef struct wl_pfn_significant_net {
++	uint16 flags;
++	uint16 channel;
++	struct ether_addr BSSID;
++	int8 rssi[PFN_SWC_RSSI_WINDOW_MAX];
++} wl_pfn_significant_net_t;
++
++#define PFN_SWC_SCANRESULT_VERSION     1
++
++typedef struct wl_pfn_swc_results {
++	uint32 version;
++	uint32 pkt_count;   /**< No. of results in current frame */
++	uint32 total_count; /**< Total expected results */
++	wl_pfn_significant_net_t list[];
++} wl_pfn_swc_results_t;
++typedef struct wl_pfn_net_info_bssid {
++	struct ether_addr BSSID;
++	uint8 channel;	/**< channel number only */
++	int8  RSSI;	/**< receive signal strength (in dBm) */
++	uint16 flags;	/**< (e.g. partial scan, off channel) */
++	uint16 timestamp; /**< age in seconds */
++} wl_pfn_net_info_bssid_t;
++
++typedef struct wl_pfn_scanhist_bssid {
++	uint32 version;
++	uint32 status;
++	uint32 count;
++	wl_pfn_net_info_bssid_t netinfo[1];
++} wl_pfn_scanhist_bssid_t;
++
++/* Version 1 and 2 for various single scan result */
++#define PFN_SCANRESULT_VERSION_V1	1
++#define PFN_SCANRESULT_VERSION_V2	2
++
++/* used to report exactly one scan result */
++/* plus reports detailed scan info in bss_info */
++typedef struct wl_pfn_scanresult_v1 {
++	uint32 version;
++	uint32 status;
++	uint32 count;
++	wl_pfn_net_info_v1_t netinfo;
++	wl_bss_info_t bss_info;
++} wl_pfn_scanresult_v1_t;
++
++typedef struct wl_pfn_scanresult_v2 {
++	uint32 version;
++	uint32 status;
++	uint32 count;
++	wl_pfn_net_info_v2_t netinfo;
++	wl_bss_info_t bss_info;
++} wl_pfn_scanresult_v2_t;
++
++/**PFN data structure */
++typedef struct wl_pfn_param {
++	int32 version;			/**< PNO parameters version */
++	int32 scan_freq;		/**< Scan frequency */
++	int32 lost_network_timeout;	/**< Timeout in sec. to declare
++								* discovered network as lost
++								*/
++	int16 flags;			/**< Bit field to control features
++							* of PFN such as sort criteria auto
++							* enable switch and background scan
++							*/
++	int16 rssi_margin;		/**< Margin to avoid jitter for choosing a
++							* PFN based on RSSI sort criteria
++							*/
++	uint8 bestn; /**< number of best networks in each scan */
++	uint8 mscan; /**< number of scans recorded */
++	uint8 repeat; /**< Minimum number of scan intervals
++				     *before scan frequency changes in adaptive scan
++				     */
++	uint8 exp; /**< Exponent of 2 for maximum scan interval */
++	int32 slow_freq; /**< slow scan period */
++} wl_pfn_param_t;
++
++typedef struct wl_pfn_bssid {
++	struct ether_addr  macaddr;
++	/* Bit4: suppress_lost, Bit3: suppress_found */
++	uint16             flags;
++} wl_pfn_bssid_t;
++typedef struct wl_pfn_significant_bssid {
++	struct ether_addr	macaddr;
++	int8    rssi_low_threshold;
++	int8    rssi_high_threshold;
++} wl_pfn_significant_bssid_t;
++#define WL_PFN_SUPPRESSFOUND_MASK	0x08
++#define WL_PFN_SUPPRESSLOST_MASK	0x10
++#define WL_PFN_SSID_IMPRECISE_MATCH	0x80
++#define WL_PFN_SSID_SAME_NETWORK	0x10000
++#define WL_PFN_SUPPRESS_AGING_MASK	0x20000
++#define WL_PFN_FLUSH_ALL_SSIDS		0x40000
++
++#define WL_PFN_IOVAR_FLAG_MASK		0xFFFF00FF
++#define WL_PFN_RSSI_MASK		0xff00
++#define WL_PFN_RSSI_SHIFT		8
++
++typedef struct wl_pfn_cfg {
++	uint32	reporttype;
++	int32	channel_num;
++	uint16	channel_list[WL_NUMCHANNELS];
++	uint32	flags;
++} wl_pfn_cfg_t;
++
++#define WL_PFN_SSID_CFG_VERSION		1
++#define WL_PFN_SSID_CFG_CLEAR		0x1
++
++typedef struct wl_pfn_ssid_params {
++	int8 min5G_rssi;           /* minimum 5GHz RSSI for a BSSID to be considered      */
++	int8 min2G_rssi;           /* minimum 2.4GHz RSSI for a BSSID to be considered   */
++	int16 init_score_max;     /* The maximum score that a network can have before bonuses  */
++
++	int16 cur_bssid_bonus;    /* Add to current bssid                                      */
++	int16 same_ssid_bonus;    /* score bonus for all networks with the same network flag   */
++	int16 secure_bonus;       /* score bonus for networks that are not open          */
++	int16 band_5g_bonus;
++} wl_pfn_ssid_params_t;
++
++typedef struct wl_ssid_ext_params {
++	int8 min5G_rssi;	/* minimum 5GHz RSSI for a BSSID to be considered      */
++	int8 min2G_rssi;	/* minimum 2.4GHz RSSI for a BSSID to be considered   */
++	int16 init_score_max;	/* The maximum score that a network can have before bonuses  */
++	int16 cur_bssid_bonus;	/* Add to current bssid                                      */
++	int16 same_ssid_bonus;	/* score bonus for all networks with the same network flag   */
++	int16 secure_bonus;	/* score bonus for networks that are not open                */
++	int16 band_5g_bonus;
++} wl_ssid_ext_params_t;
++
++typedef struct wl_pfn_ssid_cfg {
++	uint16 version;
++	uint16 flags;
++	wl_ssid_ext_params_t params;
++} wl_pfn_ssid_cfg_t;
++
++#define CH_BUCKET_REPORT_NONE                   0
++#define CH_BUCKET_REPORT_SCAN_COMPLETE_ONLY     1
++#define CH_BUCKET_REPORT_FULL_RESULT            2
++#define CH_BUCKET_REPORT_SCAN_COMPLETE    (CH_BUCKET_REPORT_SCAN_COMPLETE_ONLY | \
++								CH_BUCKET_REPORT_FULL_RESULT)
++#define CH_BUCKET_REPORT_REGULAR            0
++#define CH_BUCKET_GSCAN                     4
++
++typedef struct wl_pfn_gscan_ch_bucket_cfg {
++	uint8 bucket_end_index;
++	uint8 bucket_freq_multiple;
++	uint8 flag;
++	uint8 reserved;
++	uint16 repeat;
++	uint16 max_freq_multiple;
++} wl_pfn_gscan_ch_bucket_cfg_t;
++
++typedef struct wl_pfn_capabilities {
++	uint16 max_mscan;
++	uint16 max_bestn;
++	uint16 max_swc_bssid;
++	uint16 max_hotlist_bssid;
++} wl_pfn_capabilities_t;
++
++#define GSCAN_SEND_ALL_RESULTS_MASK          (1 << 0)
++#define GSCAN_ALL_BUCKETS_IN_FIRST_SCAN_MASK (1 << 3)
++#define GSCAN_CFG_FLAGS_ONLY_MASK            (1 << 7)
++#define WL_GSCAN_CFG_VERSION                     1
++typedef struct wl_pfn_gscan_cfg {
++	uint16 version;
++	/**
++	 * BIT0 1 = send probes/beacons to HOST
++	 * BIT1 Reserved
++	 * BIT2 Reserved
++	 * Add any future flags here
++	 * BIT7 1 = no other useful cfg sent
++	 */
++	uint8  flags;
++	/** Buffer filled threshold in % to generate an event */
++	uint8   buffer_threshold;
++	/**
++	 * No. of BSSIDs with "change" to generate an evt
++	 * change - crosses rssi threshold/lost
++	 */
++	uint8   swc_nbssid_threshold;
++	/* Max=8 (for now) Size of rssi cache buffer */
++	uint8  swc_rssi_window_size;
++	uint8  count_of_channel_buckets;
++	uint8  retry_threshold;
++	uint16  lost_ap_window;
++	wl_pfn_gscan_ch_bucket_cfg_t channel_bucket[1];
++} wl_pfn_gscan_cfg_t;
++
++#define WL_PFN_REPORT_ALLNET    0
++#define WL_PFN_REPORT_SSIDNET   1
++#define WL_PFN_REPORT_BSSIDNET  2
++
++#define WL_PFN_CFG_FLAGS_PROHIBITED	0x00000001	/* Accept and use prohibited channels */
++#define WL_PFN_CFG_FLAGS_RESERVED	0xfffffffe	/**< Remaining reserved for future use */
++
++typedef struct wl_pfn {
++	wlc_ssid_t		ssid;			/**< ssid name and its length */
++	int32			flags;			/**< bit2: hidden */
++	int32			infra;			/**< BSS Vs IBSS */
++	int32			auth;			/**< Open Vs Closed */
++	int32			wpa_auth;		/**< WPA type */
++	int32			wsec;			/**< wsec value */
++} wl_pfn_t;
++
++typedef struct wl_pfn_list {
++	uint32		version;
++	uint32		enabled;
++	uint32		count;
++	wl_pfn_t	pfn[1];
++} wl_pfn_list_t;
++
++#define PFN_SSID_EXT_VERSION   1
++
++typedef struct wl_pfn_ext {
++	uint8 flags;
++	int8 rssi_thresh; /* RSSI threshold, track only if RSSI > threshold */
++	uint16 wpa_auth; /* Match the wpa auth type defined in wlioctl_defs.h */
++	uint8 ssid[DOT11_MAX_SSID_LEN];
++	uint8 ssid_len;
++	uint8 pad;
++} wl_pfn_ext_t;
++typedef struct wl_pfn_ext_list {
++	uint16 version;
++	uint16 count;
++	wl_pfn_ext_t pfn_ext[1];
++} wl_pfn_ext_list_t;
++
++#define WL_PFN_SSID_EXT_FOUND   0x1
++#define WL_PFN_SSID_EXT_LOST    0x2
++typedef struct wl_pfn_result_ssid {
++	uint8 flags;
++	int8 rssi;
++	/* channel number */
++	uint16 channel;
++	/* Assume idx in order of cfg */
++	uint32 index;
++} wl_pfn_result_ssid_crc32_t;
++
++typedef struct wl_pfn_ssid_ext_result {
++	uint16 version;
++	uint16 count;
++	wl_pfn_result_ssid_crc32_t net[1];
++} wl_pfn_ssid_ext_result_t;
++
++#define PFN_EXT_AUTH_CODE_OPEN   1 /* open */
++#define PFN_EXT_AUTH_CODE_PSK   2 /* WPA_PSK or WPA2PSK */
++#define PFN_EXT_AUTH_CODE_EAPOL 4 /* any EAPOL  */
++
++#define WL_PFN_HIDDEN_BIT		2
++#define WL_PFN_HIDDEN_MASK		0x4
++
++#ifndef BESTN_MAX
++#define BESTN_MAX			10
++#endif
++
++#ifndef MSCAN_MAX
++#define MSCAN_MAX			90
++#endif
++
++/* Dynamic scan configuration for motion profiles */
++
++#define WL_PFN_MPF_VERSION 1
++
++/* Valid group IDs, may be expanded in the future */
++#define WL_PFN_MPF_GROUP_SSID 0
++#define WL_PFN_MPF_GROUP_BSSID 1
++#define WL_PFN_MPF_MAX_GROUPS 2
++
++/* Max number of MPF states supported in this time */
++#define WL_PFN_MPF_STATES_MAX 4
++
++/* Flags for the mpf-specific stuff */
++#define WL_PFN_MPF_ADAPT_ON_BIT		0
++#define WL_PFN_MPF_ADAPTSCAN_BIT	1
++
++#define WL_PFN_MPF_ADAPT_ON_MASK	0x0001
++#define WL_PFN_MPF_ADAPTSCAN_MASK 	0x0006
++
++/* Per-state timing values */
++typedef struct wl_pfn_mpf_state_params {
++	int32  scan_freq;	/* Scan frequency (secs) */
++	int32  lost_network_timeout; /* Timeout to declare net lost (secs) */
++	int16  flags;		/* Space for flags: ADAPT etc */
++	uint8  exp;		/* Exponent of 2 for max interval for SMART/STRICT_ADAPT */
++	uint8  repeat;		/* Number of scans before changing adaptation level */
++	int32  slow_freq;	/* Slow scan period for SLOW_ADAPT */
++} wl_pfn_mpf_state_params_t;
++
++typedef struct wl_pfn_mpf_param {
++	uint16 version;		/* Structure version */
++	uint16 groupid;		/* Group ID: 0 (SSID), 1 (BSSID), other: reserved */
++	wl_pfn_mpf_state_params_t state[WL_PFN_MPF_STATES_MAX];
++} wl_pfn_mpf_param_t;
++
++/* Structure for setting pfn_override iovar */
++typedef struct wl_pfn_override_param {
++	uint16 version;         /* Structure version */
++	uint16 start_offset;    /* Seconds from now to apply new params */
++	uint16 duration;        /* Seconds to keep new params applied */
++	uint16 reserved;
++	wl_pfn_mpf_state_params_t override;
++} wl_pfn_override_param_t;
++#define WL_PFN_OVERRIDE_VERSION	1
++
++/*
++ * Definitions for base MPF configuration
++ */
++
++#define WL_MPF_VERSION 1
++#define WL_MPF_MAX_BITS 3
++#define WL_MPF_MAX_STATES (1 << WL_MPF_MAX_BITS)
++
++#define WL_MPF_STATE_NAME_MAX 12
++
++typedef struct wl_mpf_val {
++	uint16 val;		/* Value of GPIO bits */
++	uint16 state;		/* State identifier */
++	char name[WL_MPF_STATE_NAME_MAX]; /* Optional name */
++} wl_mpf_val_t;
++
++typedef struct wl_mpf_map {
++	uint16 version;
++	uint16 type;
++	uint16 mask;		/* Which GPIO bits to use */
++	uint8  count;		/* Count of state/value mappings */
++	uint8  PAD;
++	wl_mpf_val_t vals[WL_MPF_MAX_STATES];
++} wl_mpf_map_t;
++
++#define WL_MPF_STATE_AUTO (0xFFFF) /* (uint16)-1) */
++
++typedef struct wl_mpf_state {
++	uint16 version;
++	uint16 type;
++	uint16 state;		/* Get/Set */
++	uint8 force;		/* 0 - auto (HW) state, 1 - forced state */
++	char name[WL_MPF_STATE_NAME_MAX]; /* Get/Set: Optional/actual name */
++	uint8  PAD;
++} wl_mpf_state_t;
++/*
++ * WLFCTS definition
++ */
++typedef struct wl_txstatus_additional_info {
++	uint32 rspec;
++	uint32 enq_ts;
++	uint32 last_ts;
++	uint32 entry_ts;
++	uint16 seq;
++	uint8  rts_cnt;
++	uint8  tx_cnt;
++} wl_txstatus_additional_info_t;
++
++/** Service discovery */
++typedef struct {
++	uint8	transaction_id;	/**< Transaction id */
++	uint8	protocol;	/**< Service protocol type */
++	uint16	query_len;	/**< Length of query */
++	uint16	response_len;	/**< Length of response */
++	uint8	qrbuf[];
++} wl_p2po_qr_t;
++
++typedef struct {
++	uint16			period;			/**< extended listen period */
++	uint16			interval;		/**< extended listen interval */
++	uint16                  count;                  /* count to repeat */
++	uint16                  pad;                    /* pad for 32bit align */
++} wl_p2po_listen_t;
++
++/** GAS state machine tunable parameters.  Structure field values of 0 means use the default. */
++typedef struct wl_gas_config {
++	uint16 max_retransmit;		/**< Max # of firmware/driver retransmits on no Ack
++					 * from peer (on top of the ucode retries).
++					 */
++	uint16 response_timeout;	/**< Max time to wait for a GAS-level response
++					 * after sending a packet.
++					 */
++	uint16 max_comeback_delay;	/**< Max GAS response comeback delay.
++					 * Exceeding this fails the GAS exchange.
++					 */
++	uint16 max_retries;		/**< Max # of GAS state machine retries on failure
++					 * of a GAS frame exchange.
++					 */
++} wl_gas_config_t;
++
++/** P2P Find Offload parameters */
++typedef struct wl_p2po_find_config {
++	uint16 version;			/**< Version of this struct */
++	uint16 length;			/**< sizeof(wl_p2po_find_config_t) */
++	int32 search_home_time;		/**< P2P search state home time when concurrent
++					 * connection exists.  -1 for default.
++					 */
++	uint8 num_social_channels;
++			/**< Number of social channels up to WL_P2P_SOCIAL_CHANNELS_MAX.
++			 * 0 means use default social channels.
++			 */
++	uint8 flags;
++	uint16 social_channels[1];	/**< Variable length array of social channels */
++} wl_p2po_find_config_t;
++#define WL_P2PO_FIND_CONFIG_VERSION 2	/**< value for version field */
++
++/** wl_p2po_find_config_t flags */
++#define P2PO_FIND_FLAG_SCAN_ALL_APS 0x01	/**< Whether to scan for all APs in the p2po_find
++						 * periodic scans of all channels.
++						 * 0 means scan for only P2P devices.
++						 * 1 means scan for P2P devices plus non-P2P APs.
++						 */
++
++
++/** For adding a WFDS service to seek */
++typedef struct {
++	uint32 seek_hdl;		/**< unique id chosen by host */
++	uint8 addr[6];			/**< Seek service from a specific device with this
++					 * MAC address, all 1's for any device.
++					 */
++	uint8 service_hash[P2P_WFDS_HASH_LEN];
++	uint8 service_name_len;
++	uint8 service_name[MAX_WFDS_SEEK_SVC_NAME_LEN];
++					/**< Service name to seek, not null terminated */
++	uint8 service_info_req_len;
++	uint8 service_info_req[1];	/**< Service info request, not null terminated.
++					 * Variable length specified by service_info_req_len.
++					 * Maximum length is MAX_WFDS_SEEK_SVC_INFO_LEN.
++					 */
++} wl_p2po_wfds_seek_add_t;
++
++/** For deleting a WFDS service to seek */
++typedef struct {
++	uint32 seek_hdl;		/**< delete service specified by id */
++} wl_p2po_wfds_seek_del_t;
++
++
++/** For adding a WFDS service to advertise */
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint32 advertise_hdl;		/**< unique id chosen by host */
++	uint8 service_hash[P2P_WFDS_HASH_LEN];
++	uint32 advertisement_id;
++	uint16 service_config_method;
++	uint8 service_name_len;
++	uint8 service_name[MAX_WFDS_SVC_NAME_LEN];
++					/**< Service name , not null terminated */
++	uint8 service_status;
++	uint16 service_info_len;
++	uint8 service_info[1];		/**< Service info, not null terminated.
++					 * Variable length specified by service_info_len.
++					 * Maximum length is MAX_WFDS_ADV_SVC_INFO_LEN.
++					 */
++} BWL_POST_PACKED_STRUCT wl_p2po_wfds_advertise_add_t;
++#include <packed_section_end.h>
++
++/** For deleting a WFDS service to advertise */
++typedef struct {
++	uint32 advertise_hdl;	/**< delete service specified by hdl */
++} wl_p2po_wfds_advertise_del_t;
++
++/** P2P Offload discovery mode for the p2po_state iovar */
++typedef enum {
++	WL_P2PO_DISC_STOP,
++	WL_P2PO_DISC_LISTEN,
++	WL_P2PO_DISC_DISCOVERY
++} disc_mode_t;
++
++/* ANQP offload */
++
++#define ANQPO_MAX_QUERY_SIZE		256
++typedef struct {
++	uint16 max_retransmit;		/**< ~0 use default, max retransmit on no ACK from peer */
++	uint16 response_timeout; /**< ~0 use default, msec to wait for resp after tx packet */
++	uint16 max_comeback_delay;	/**< ~0 use default, max comeback delay in resp else fail */
++	uint16 max_retries;		/**< ~0 use default, max retries on failure */
++	uint16 query_len;		/**< length of ANQP query */
++	uint8 query_data[1];		/**< ANQP encoded query (max ANQPO_MAX_QUERY_SIZE) */
++} wl_anqpo_set_t;
++
++typedef struct {
++	uint16 channel;			/**< channel of the peer */
++	struct ether_addr addr;		/**< addr of the peer */
++} wl_anqpo_peer_t;
++
++#define ANQPO_MAX_PEER_LIST			64
++typedef struct {
++	uint16 count;				/**< number of peers in list */
++	wl_anqpo_peer_t peer[1];	/**< max ANQPO_MAX_PEER_LIST */
++} wl_anqpo_peer_list_t;
++
++#define ANQPO_MAX_IGNORE_SSID		64
++typedef struct {
++	uint8 is_clear;				/**< set to clear list (not used on GET) */
++	uint8 PAD;
++	uint16 count;				/**< number of SSID in list */
++	wlc_ssid_t ssid[1];			/**< max ANQPO_MAX_IGNORE_SSID */
++} wl_anqpo_ignore_ssid_list_t;
++
++#define ANQPO_MAX_IGNORE_BSSID		64
++typedef struct {
++	uint8 is_clear;				/**< set to clear list (not used on GET) */
++	uint8 PAD;
++	uint16 count;				/**< number of addr in list */
++	struct ether_addr bssid[];	/**< max ANQPO_MAX_IGNORE_BSSID */
++} wl_anqpo_ignore_bssid_list_t;
++
++
++struct toe_ol_stats_t {
++	/** Num of tx packets that don't need to be checksummed */
++	uint32 tx_summed;
++
++	/* Num of tx packets where checksum is filled by offload engine */
++	uint32 tx_iph_fill;
++	uint32 tx_tcp_fill;
++	uint32 tx_udp_fill;
++	uint32 tx_icmp_fill;
++
++	/*  Num of rx packets where toe finds out if checksum is good or bad */
++	uint32 rx_iph_good;
++	uint32 rx_iph_bad;
++	uint32 rx_tcp_good;
++	uint32 rx_tcp_bad;
++	uint32 rx_udp_good;
++	uint32 rx_udp_bad;
++	uint32 rx_icmp_good;
++	uint32 rx_icmp_bad;
++
++	/* Num of tx packets in which csum error is injected */
++	uint32 tx_tcp_errinj;
++	uint32 tx_udp_errinj;
++	uint32 tx_icmp_errinj;
++
++	/* Num of rx packets in which csum error is injected */
++	uint32 rx_tcp_errinj;
++	uint32 rx_udp_errinj;
++	uint32 rx_icmp_errinj;
++};
++
++/** Arp offload statistic counts */
++struct arp_ol_stats_t {
++	uint32  host_ip_entries; /**< Host IP table addresses (more than one if multihomed) */
++	uint32  host_ip_overflow;	/**< Host IP table additions skipped due to overflow */
++
++	uint32  arp_table_entries;	/**< ARP table entries */
++	uint32  arp_table_overflow;	/**< ARP table additions skipped due to overflow */
++
++	uint32  host_request;		/**< ARP requests from host */
++	uint32  host_reply;		/**< ARP replies from host */
++	uint32  host_service;		/**< ARP requests from host serviced by ARP Agent */
++
++	uint32  peer_request;		/**< ARP requests received from network */
++	uint32  peer_request_drop;	/**< ARP requests from network that were dropped */
++	uint32  peer_reply;		/**< ARP replies received from network */
++	uint32  peer_reply_drop;	/**< ARP replies from network that were dropped */
++	uint32  peer_service;		/**< ARP request from host serviced by ARP Agent */
++};
++
++/** NS offload statistic counts */
++struct nd_ol_stats_t {
++	uint32  host_ip_entries;    /**< Host IP table addresses (more than one if multihomed) */
++	uint32  host_ip_overflow;   /**< Host IP table additions skipped due to overflow */
++	uint32  peer_request;       /**< NS requests received from network */
++	uint32  peer_request_drop;  /**< NS requests from network that were dropped */
++	uint32  peer_reply_drop;    /**< NA replies from network that were dropped */
++	uint32  peer_service;       /**< NS request from host serviced by firmware */
++};
++
++/*
++ * Neighbor Discovery Offloading
++ */
++enum {
++	WL_ND_IPV6_ADDR_TYPE_UNICAST = 0,
++	WL_ND_IPV6_ADDR_TYPE_ANYCAST
++};
++
++typedef struct wl_nd_host_ip_addr {
++	struct ipv6_addr ip_addr;	/* host ip address */
++	uint8 type;			/* type of address */
++	uint8 pad[3];
++} wl_nd_host_ip_addr_t;
++
++typedef struct wl_nd_host_ip_list {
++	uint32 count;
++	wl_nd_host_ip_addr_t host_ip[1];
++} wl_nd_host_ip_list_t;
++
++#define WL_ND_HOSTIP_IOV_VER    1
++
++enum {
++	WL_ND_HOSTIP_OP_VER = 0,	/* get version */
++	WL_ND_HOSTIP_OP_ADD,		/* add address */
++	WL_ND_HOSTIP_OP_DEL,		/* delete specified address */
++	WL_ND_HOSTIP_OP_DEL_UC,		/* delete all unicast address */
++	WL_ND_HOSTIP_OP_DEL_AC,		/* delete all anycast address */
++	WL_ND_HOSTIP_OP_DEL_ALL,	/* delete all addresses */
++	WL_ND_HOSTIP_OP_LIST,		/* get list of host ip address */
++	WL_ND_HOSTIP_OP_MAX
++};
++
++typedef struct wl_nd_hostip {
++	uint16 version;				/* version of iovar buf */
++	uint16 op_type;				/* operation type */
++	uint32 length;				/* length of entire structure */
++	union {
++		wl_nd_host_ip_addr_t host_ip;	/* set param for add */
++		uint16 version;			/* get return for ver */
++	} u;
++} wl_nd_hostip_t;
++
++#define WL_ND_HOSTIP_FIXED_LEN		OFFSETOF(wl_nd_hostip_t, u)
++#define WL_ND_HOSTIP_WITH_ADDR_LEN	(WL_ND_HOSTIP_FIXED_LEN + sizeof(wl_nd_host_ip_addr_t))
++
++/*
++ * Keep-alive packet offloading.
++ */
++
++/**
++ * NAT keep-alive packets format: specifies the re-transmission period, the packet
++ * length, and packet contents.
++ */
++typedef struct wl_keep_alive_pkt {
++	uint32	period_msec;	/** Retransmission period (0 to disable packet re-transmits) */
++	uint16	len_bytes;	/* Size of packet to transmit (0 to disable packet re-transmits) */
++	uint8	data[1];	/** Variable length packet to transmit.  Contents should include
++				 * entire ethernet packet (enet header, IP header, UDP header,
++				 * and UDP payload) in network byte order.
++				 */
++} wl_keep_alive_pkt_t;
++
++#define WL_KEEP_ALIVE_FIXED_LEN		OFFSETOF(wl_keep_alive_pkt_t, data)
++
++#define MAX_RSSI_COUNT			8
++typedef struct rssi_struct {
++	int8	val[MAX_RSSI_COUNT];	/**< rssi values in AFs */
++	int16	sum;			/**< total rssi sum */
++	uint8	cnt;			/**< number rssi samples */
++	uint8	idx;			/**< next rssi location */
++} rssi_struct_t;
++
++
++/*
++ * ptk_start: iovar to start 4-way handshake for secured ranging
++*/
++
++/* ptk negotiation security type - determines negotiation parameters */
++typedef enum {
++	WL_PTK_START_SEC_TYPE_PMK = 1
++} wl_ptk_start_sec_type_t;
++
++/* ptk negotiation role */
++typedef enum {
++	ROLE_NONE	= 0x0,
++	ROLE_AUTH	= 0x1,
++	ROLE_SUP	= 0x2,
++	ROLE_STATIC	= 0x3,
++	ROLE_INVALID	= 0xff,
++	WL_PTK_START_ROLE_NONE = ROLE_NONE,
++	WL_PTK_START_ROLE_AUTH = ROLE_AUTH,
++	WL_PTK_START_ROLE_SUP = ROLE_SUP,
++	WL_PTK_START_ROLE_STATIC = ROLE_STATIC,
++	WL_PTK_START_ROLE_INVALID = ROLE_INVALID
++} wl_ptk_start_role_t;
++
++typedef struct wl_ptk_start_tlv {
++	uint16 id;
++	uint16 len;
++	uint8 data[1];
++} wl_ptk_start_tlv_t;
++
++typedef enum {
++	WL_PTK_START_TLV_PMK	= 1	/* uint8[] */
++} wl_ptk_start_tlv_type;
++
++typedef enum {
++	WL_PTK_START_FLAG_NO_DATA_PROT	= 1,	/* data frame protection disabled */
++	WL_PTK_START_FLAG_GEN_FTM_TPK	= 2	/* Generate FTM Toast/Seq Protection Key */
++} wl_ptk_start_flags_t;
++
++typedef struct wl_ptk_start_iov {
++	uint16 version;
++	uint16 len;				/* length of entire iov from version */
++	wl_ptk_start_flags_t flags;
++	wl_ptk_start_sec_type_t sec_type;
++	wl_ptk_start_role_t role;
++	struct ether_addr peer_addr;
++	uint16 pad;				/* reserved/32 bit alignment */
++	wl_ptk_start_tlv_t tlvs[1];
++} wl_ptk_start_iov_t;
++
++/*
++ * Dongle pattern matching filter.
++ */
++
++#define MAX_WAKE_PACKET_CACHE_BYTES 128 /**< Maximum cached wake packet */
++
++#define MAX_WAKE_PACKET_BYTES	    (DOT11_A3_HDR_LEN +			    \
++				     DOT11_QOS_LEN +			    \
++				     sizeof(struct dot11_llc_snap_header) + \
++				     ETHER_MAX_DATA)
++
++typedef struct pm_wake_packet {
++	uint32	status;		/**< Is the wake reason a packet (if all the other field's valid) */
++	uint32	pattern_id;	/**< Pattern ID that matched */
++	uint32	original_packet_size;
++	uint32	saved_packet_size;
++	uint8	packet[MAX_WAKE_PACKET_CACHE_BYTES];
++} pm_wake_packet_t;
++
++/* Packet filter types. Currently, only pattern matching is supported. */
++typedef enum wl_pkt_filter_type {
++	WL_PKT_FILTER_TYPE_PATTERN_MATCH=0,       /**< Pattern matching filter */
++	WL_PKT_FILTER_TYPE_MAGIC_PATTERN_MATCH=1, /**< Magic packet match */
++	WL_PKT_FILTER_TYPE_PATTERN_LIST_MATCH=2,  /**< A pattern list (match all to match filter) */
++	WL_PKT_FILTER_TYPE_ENCRYPTED_PATTERN_MATCH=3, /**< SECURE WOWL magic / net pattern match */
++	WL_PKT_FILTER_TYPE_APF_MATCH=4, /* Android packet filter match */
++	WL_PKT_FILTER_TYPE_PATTERN_MATCH_TIMEOUT=5, /* Pattern matching filter with timeout event */
++	WL_PKT_FILTER_TYPE_IMMEDIATE_PATTERN_MATCH=6, /* Immediately pattern matching filter */
++	WL_PKT_FILTYER_TYPE_MAX = 7,	/* Pkt filter type MAX */
++} wl_pkt_filter_type_t;
++
++#define WL_PKT_FILTER_TYPE wl_pkt_filter_type_t
++
++/* String mapping for types that may be used by applications or debug */
++#define WL_PKT_FILTER_TYPE_NAMES \
++	{ "PATTERN", WL_PKT_FILTER_TYPE_PATTERN_MATCH },	\
++	{ "MAGIC",   WL_PKT_FILTER_TYPE_MAGIC_PATTERN_MATCH },	\
++	{ "PATLIST", WL_PKT_FILTER_TYPE_PATTERN_LIST_MATCH },	\
++	{ "SECURE WOWL", WL_PKT_FILTER_TYPE_ENCRYPTED_PATTERN_MATCH },	\
++	{ "APF", WL_PKT_FILTER_TYPE_APF_MATCH }, \
++	{ "PATTERN TIMEOUT", WL_PKT_FILTER_TYPE_PATTERN_MATCH_TIMEOUT }, \
++	{ "IMMEDIATE", WL_PKT_FILTER_TYPE_IMMEDIATE_PATTERN_MATCH }
++
++/** Secured WOWL packet was encrypted, need decrypted before check filter match */
++typedef struct wl_pkt_decrypter {
++	uint8* (*dec_cb)(void* dec_ctx, const void *sdu, int sending);
++	void*  dec_ctx;
++} wl_pkt_decrypter_t;
++
++/**
++ * Pattern matching filter. Specifies an offset within received packets to
++ * start matching, the pattern to match, the size of the pattern, and a bitmask
++ * that indicates which bits within the pattern should be matched.
++ */
++typedef struct wl_pkt_filter_pattern {
++	uint32	offset;		/**< Offset within received packet to start pattern matching.
++				 * Offset '0' is the first byte of the ethernet header.
++				 */
++	uint32	size_bytes;	/**< Size of the pattern.  Bitmask must be the same size. */
++	uint8   mask_and_pattern[]; /**< Variable length mask and pattern data.  mask starts
++				      * at offset 0.  Pattern immediately follows mask. for
++				      * secured pattern, put the descrypter pointer to the
++				      * beginning, mask and pattern postponed correspondingly
++				      */
++} wl_pkt_filter_pattern_t;
++
++/** A pattern list is a numerically specified list of modified pattern structures. */
++typedef struct wl_pkt_filter_pattern_listel {
++	uint16 rel_offs;	/**< Offset to begin match (relative to 'base' below) */
++	uint16 base_offs;	/**< Base for offset (defined below) */
++	uint16 size_bytes;	/**< Size of mask/pattern */
++	uint16 match_flags;	/**< Addition flags controlling the match */
++	uint8  mask_and_data[1]; /**< Variable length mask followed by data, each size_bytes */
++} wl_pkt_filter_pattern_listel_t;
++
++typedef struct wl_pkt_filter_pattern_list {
++	uint8 list_cnt;		/**< Number of elements in the list */
++	uint8 PAD1[1];		/**< Reserved (possible version: reserved) */
++	uint16 totsize;		/**< Total size of this pattern list (includes this struct) */
++	wl_pkt_filter_pattern_listel_t patterns[]; /**< Variable number of list elements */
++} wl_pkt_filter_pattern_list_t;
++
++typedef struct wl_apf_program {
++	uint16 version;
++	uint16 instr_len;	/* number of instruction blocks */
++	uint32 inst_ts;		/* program installation timestamp */
++	uint8 instrs[];	/* variable length instructions */
++} wl_apf_program_t;
++
++typedef struct wl_pkt_filter_pattern_timeout {
++	uint32	offset;	/* Offset within received packet to start pattern matching.
++					 * Offset '0' is the first byte of the ethernet header.
++					 */
++	uint32	size_bytes;	/* Size of the pattern. Bitmask must be the same size. */
++	uint32	timeout;	/* Timeout(seconds) */
++	uint8	mask_and_pattern[1]; /* Variable length mask and pattern data.
++								 * mask starts at offset 0. Pattern
++								 * immediately follows mask.
++								*/
++} wl_pkt_filter_pattern_timeout_t;
++
++/** IOVAR "pkt_filter_add" parameter. Used to install packet filters. */
++typedef struct wl_pkt_filter {
++	uint32	id;		/**< Unique filter id, specified by app. */
++	uint32	type;		/**< Filter type (WL_PKT_FILTER_TYPE_xxx). */
++	uint32	negate_match;	/**< Negate the result of filter matches */
++	union {			/* Filter definitions */
++		wl_pkt_filter_pattern_t pattern;	/**< Pattern matching filter */
++		wl_pkt_filter_pattern_list_t patlist; /**< List of patterns to match */
++		wl_apf_program_t apf_program; /* apf program */
++		wl_pkt_filter_pattern_timeout_t pattern_timeout; /* Pattern timeout event filter */
++	} u;
++} wl_pkt_filter_t;
++
++/** IOVAR "tcp_keep_set" parameter. Used to install tcp keep_alive stuff. */
++typedef struct wl_tcp_keep_set {
++	uint32	val1;
++	uint32	val2;
++} wl_tcp_keep_set_t;
++
++#define WL_PKT_FILTER_FIXED_LEN		  OFFSETOF(wl_pkt_filter_t, u)
++#define WL_PKT_FILTER_PATTERN_FIXED_LEN	  OFFSETOF(wl_pkt_filter_pattern_t, mask_and_pattern)
++#define WL_PKT_FILTER_PATTERN_LIST_FIXED_LEN OFFSETOF(wl_pkt_filter_pattern_list_t, patterns)
++#define WL_PKT_FILTER_PATTERN_LISTEL_FIXED_LEN	\
++			OFFSETOF(wl_pkt_filter_pattern_listel_t, mask_and_data)
++#define WL_PKT_FILTER_PATTERN_TIMEOUT_FIXED_LEN	\
++			OFFSETOF(wl_pkt_filter_pattern_timeout_t, mask_and_pattern)
++
++#define WL_APF_INTERNAL_VERSION	1
++#define WL_APF_PROGRAM_MAX_SIZE (2 * 1024)
++#define WL_APF_PROGRAM_FIXED_LEN	OFFSETOF(wl_apf_program_t, instrs)
++#define WL_APF_PROGRAM_LEN(apf_program)	\
++	((apf_program)->instr_len * sizeof((apf_program)->instrs[0]))
++#define WL_APF_PROGRAM_TOTAL_LEN(apf_program)	\
++	(WL_APF_PROGRAM_FIXED_LEN + WL_APF_PROGRAM_LEN(apf_program))
++
++/** IOVAR "pkt_filter_enable" parameter. */
++typedef struct wl_pkt_filter_enable {
++	uint32	id;		/**< Unique filter id */
++	uint32	enable;		/**< Enable/disable bool */
++} wl_pkt_filter_enable_t;
++
++/** IOVAR "pkt_filter_list" parameter. Used to retrieve a list of installed filters. */
++typedef struct wl_pkt_filter_list {
++	uint32	num;		/**< Number of installed packet filters */
++	wl_pkt_filter_t	filter[1];	/**< Variable array of packet filters. */
++} wl_pkt_filter_list_t;
++
++#define WL_PKT_FILTER_LIST_FIXED_LEN	  OFFSETOF(wl_pkt_filter_list_t, filter)
++
++/** IOVAR "pkt_filter_stats" parameter. Used to retrieve debug statistics. */
++typedef struct wl_pkt_filter_stats {
++	uint32	num_pkts_matched;	/**< # filter matches for specified filter id */
++	uint32	num_pkts_forwarded;	/**< # packets fwded from dongle to host for all filters */
++	uint32	num_pkts_discarded;	/**< # packets discarded by dongle for all filters */
++} wl_pkt_filter_stats_t;
++
++/** IOVAR "pkt_filter_ports" parameter.  Configure TCP/UDP port filters. */
++typedef struct wl_pkt_filter_ports {
++	uint8 version;		/**< Be proper */
++	uint8 reserved;		/**< Be really proper */
++	uint16 count;		/**< Number of ports following */
++	/* End of fixed data */
++	uint16 ports[1];	/**< Placeholder for ports[<count>] */
++} wl_pkt_filter_ports_t;
++
++#define WL_PKT_FILTER_PORTS_FIXED_LEN	OFFSETOF(wl_pkt_filter_ports_t, ports)
++
++#define WL_PKT_FILTER_PORTS_VERSION	0
++#define WL_PKT_FILTER_PORTS_MAX		128
++
++#define RSN_REPLAY_LEN 8
++typedef struct _gtkrefresh {
++	uint8	KCK[RSN_KCK_LENGTH];
++	uint8	KEK[RSN_KEK_LENGTH];
++	uint8	ReplayCounter[RSN_REPLAY_LEN];
++} gtk_keyinfo_t, *pgtk_keyinfo_t;
++
++/** Sequential Commands ioctl */
++typedef struct wl_seq_cmd_ioctl {
++	uint32 cmd;		/**< common ioctl definition */
++	uint32 len;		/**< length of user buffer */
++} wl_seq_cmd_ioctl_t;
++
++#define WL_SEQ_CMD_ALIGN_BYTES	4
++
++/**
++ * These are the set of get IOCTLs that should be allowed when using
++ * IOCTL sequence commands. These are issued implicitly by wl.exe each time
++ * it is invoked. We never want to buffer these, or else wl.exe will stop working.
++ */
++#define WL_SEQ_CMDS_GET_IOCTL_FILTER(cmd) \
++	(((cmd) == WLC_GET_MAGIC)		|| \
++	 ((cmd) == WLC_GET_VERSION)		|| \
++	 ((cmd) == WLC_GET_AP)			|| \
++	 ((cmd) == WLC_GET_INSTANCE))
++
++typedef struct wl_pkteng {
++	uint32 flags;
++	uint32 delay;			/**< Inter-packet delay */
++	uint32 nframes;			/**< Number of frames */
++	uint32 length;			/**< Packet length */
++	uint8  seqno;			/**< Enable/disable sequence no. */
++	struct ether_addr dest;		/**< Destination address */
++	struct ether_addr src;		/**< Source address */
++	uint8  PAD[3];
++} wl_pkteng_t;
++
++#define WL_PKTENG_RU_FILL_VER_1		1
++// struct for ru packet engine
++typedef struct wl_pkteng_ru {
++	uint16 version;		/* ver is 1 */
++	uint16 length;		/* size of complete structure */
++	uint8 bw;			/* bandwidth info */
++	uint8 ru_alloc_val;		/* ru allocation index number */
++	uint8 mcs_val;			/* mcs allocated value */
++	uint8 nss_val;			/* num of spatial streams */
++	uint32 num_bytes;		/* approx num of bytes to calculate other required params */
++	uint8 cp_ltf_val ;		/* GI and LTF symbol size */
++	uint8 he_ltf_symb ;		/* num of HE-LTF symbols */
++	uint8 stbc;			/* STBC support */
++	uint8 coding_val;		/* BCC/LDPC coding support */
++	uint8 pe_category;	/* PE duration 0/8/16usecs  */
++	uint8 dcm;			/* dual carrier modulation */
++	uint8 mumimo_ltfmode; /* ltf mode */
++	uint8 PAD[1];		/* pad bytes to make structure occupy 4 byte aligned */
++} wl_pkteng_ru_fill_t;
++
++typedef struct wl_pkteng_stats {
++	uint32 lostfrmcnt;		/**< RX PER test: no of frames lost (skip seqno) */
++	int32 rssi;			/**< RSSI */
++	int32 snr;			/**< signal to noise ratio */
++	uint16 rxpktcnt[NUM_80211_RATES+1];
++	uint8 rssi_qdb;			/**< qdB portion of the computed rssi */
++	uint8  PAD;
++} wl_pkteng_stats_t;
++
++typedef struct wl_txcal_params {
++	wl_pkteng_t pkteng;
++	uint8 gidx_start;
++	int8 gidx_step;
++	uint8 gidx_stop;
++	uint8  PAD;
++} wl_txcal_params_t;
++
++
++typedef struct wl_sslpnphy_papd_debug_data {
++	uint8 psat_pwr;
++	uint8 psat_indx;
++	uint8 final_idx;
++	uint8 start_idx;
++	int32 min_phase;
++	int32 voltage;
++	int8 temperature;
++	uint8  PAD[3];
++} wl_sslpnphy_papd_debug_data_t;
++typedef struct wl_sslpnphy_debug_data {
++	int16 papdcompRe [64];
++	int16 papdcompIm [64];
++} wl_sslpnphy_debug_data_t;
++typedef struct wl_sslpnphy_spbdump_data {
++	uint16 tbl_length;
++	int16 spbreal[256];
++	int16 spbimg[256];
++} wl_sslpnphy_spbdump_data_t;
++typedef struct wl_sslpnphy_percal_debug_data {
++	uint32 cur_idx;
++	uint32 tx_drift;
++	uint8 prev_cal_idx;
++	uint8  PAD[3];
++	uint32 percal_ctr;
++	int32 nxt_cal_idx;
++	uint32 force_1idxcal;
++	uint32 onedxacl_req;
++	int32 last_cal_volt;
++	int8 last_cal_temp;
++	uint8  PAD[3];
++	uint32 vbat_ripple;
++	uint32 exit_route;
++	int32 volt_winner;
++} wl_sslpnphy_percal_debug_data_t;
++
++typedef enum {
++	wowl_pattern_type_bitmap = 0,
++	wowl_pattern_type_arp,
++	wowl_pattern_type_na
++} wowl_pattern_type_t;
++
++typedef struct wl_wowl_pattern {
++	uint32		    masksize;		/**< Size of the mask in #of bytes */
++	uint32		    offset;		/**< Pattern byte offset in packet */
++	uint32		    patternoffset;	/**< Offset of start of pattern in the structure */
++	uint32		    patternsize;	/**< Size of the pattern itself in #of bytes */
++	uint32		    id;			/**< id */
++	uint32		    reasonsize;		/**< Size of the wakeup reason code */
++	wowl_pattern_type_t type;		/**< Type of pattern */
++	/* Mask follows the structure above */
++	/* Pattern follows the mask is at 'patternoffset' from the start */
++} wl_wowl_pattern_t;
++
++typedef struct wl_wowl_pattern_list {
++	uint32			count;
++	wl_wowl_pattern_t	pattern[1];
++} wl_wowl_pattern_list_t;
++
++typedef struct wl_wowl_wakeind {
++	uint8	pci_wakeind;	/**< Whether PCI PMECSR PMEStatus bit was set */
++	uint32	ucode_wakeind;	/**< What wakeup-event indication was set by ucode */
++} wl_wowl_wakeind_t;
++
++/** per AC rate control related data structure */
++typedef struct wl_txrate_class {
++	uint8		init_rate;
++	uint8		min_rate;
++	uint8		max_rate;
++} wl_txrate_class_t;
++
++/** structure for Overlap BSS scan arguments */
++typedef struct wl_obss_scan_arg {
++	int16	passive_dwell;
++	int16	active_dwell;
++	int16	bss_widthscan_interval;
++	int16	passive_total;
++	int16	active_total;
++	int16	chanwidth_transition_delay;
++	int16	activity_threshold;
++} wl_obss_scan_arg_t;
++
++#define WL_OBSS_SCAN_PARAM_LEN	sizeof(wl_obss_scan_arg_t)
++
++/** RSSI event notification configuration. */
++typedef struct wl_rssi_event {
++	uint32 rate_limit_msec;		/**< # of events posted to application will be limited to
++					 * one per specified period (0 to disable rate limit).
++					 */
++	uint8 num_rssi_levels;		/**< Number of entries in rssi_levels[] below */
++	int8 rssi_levels[MAX_RSSI_LEVELS];	/**< Variable number of RSSI levels. An event
++						 * will be posted each time the RSSI of received
++						 * beacons/packets crosses a level.
++						 */
++	int8 pad[3];
++} wl_rssi_event_t;
++
++#define RSSI_MONITOR_VERSION    1
++#define RSSI_MONITOR_STOP       (1 << 0)
++typedef struct wl_rssi_monitor_cfg {
++	uint8 version;
++	uint8 flags;
++	int8 max_rssi;
++	int8 min_rssi;
++} wl_rssi_monitor_cfg_t;
++
++typedef struct wl_rssi_monitor_evt {
++	uint8 version;
++	int8 cur_rssi;
++	uint16 pad;
++} wl_rssi_monitor_evt_t;
++
++/* CCA based channel quality event configuration */
++#define WL_CHAN_QUAL_CCA	0
++#define WL_CHAN_QUAL_NF		1
++#define WL_CHAN_QUAL_NF_LTE	2
++#define WL_CHAN_QUAL_TOTAL	3
++
++#define MAX_CHAN_QUAL_LEVELS	8
++
++typedef struct wl_chan_qual_metric {
++	uint8 id;				/**< metric ID */
++	uint8 num_levels;               	/**< Number of entries in rssi_levels[] below */
++	uint16 flags;
++	int16 htol[MAX_CHAN_QUAL_LEVELS];	/**< threshold level array: hi-to-lo */
++	int16 ltoh[MAX_CHAN_QUAL_LEVELS];	/**< threshold level array: lo-to-hi */
++} wl_chan_qual_metric_t;
++
++typedef struct wl_chan_qual_event {
++	uint32 rate_limit_msec;		/**< # of events posted to application will be limited to
++					 * one per specified period (0 to disable rate limit).
++					 */
++	uint16 flags;
++	uint16 num_metrics;
++	wl_chan_qual_metric_t metric[WL_CHAN_QUAL_TOTAL];	/**< metric array */
++} wl_chan_qual_event_t;
++typedef struct wl_action_obss_coex_req {
++	uint8 info;
++	uint8 num;
++	uint8 ch_list[1];
++} wl_action_obss_coex_req_t;
++
++
++/** IOVar parameter block for small MAC address array with type indicator */
++#define WL_IOV_MAC_PARAM_LEN  4
++
++#define WL_IOV_PKTQ_LOG_PRECS 16
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint32 num_addrs;
++	uint8   addr_type[WL_IOV_MAC_PARAM_LEN];
++	struct ether_addr ea[WL_IOV_MAC_PARAM_LEN];
++} BWL_POST_PACKED_STRUCT wl_iov_mac_params_t;
++#include <packed_section_end.h>
++
++/** This is extra info that follows wl_iov_mac_params_t */
++typedef struct {
++	uint32 addr_info[WL_IOV_MAC_PARAM_LEN];
++} wl_iov_mac_extra_params_t;
++
++/** Combined structure */
++typedef struct {
++	wl_iov_mac_params_t params;
++	wl_iov_mac_extra_params_t extra_params;
++} wl_iov_mac_full_params_t;
++
++/** Parameter block for PKTQ_LOG statistics */
++#define PKTQ_LOG_COUNTERS_V4 \
++	/* packets requested to be stored */ \
++	uint32 requested; \
++	/* packets stored */ \
++	uint32 stored; \
++	/* packets saved, because a lowest priority queue has given away one packet */ \
++	uint32 saved; \
++	/* packets saved, because an older packet from the same queue has been dropped */ \
++	uint32 selfsaved; \
++	/* packets dropped, because pktq is full with higher precedence packets */ \
++	uint32 full_dropped; \
++	 /* packets dropped because pktq per that precedence is full */ \
++	uint32 dropped; \
++	/* packets dropped, in order to save one from a queue of a highest priority */ \
++	uint32 sacrificed; \
++	/* packets droped because of hardware/transmission error */ \
++	uint32 busy; \
++	/* packets re-sent because they were not received */ \
++	uint32 retry; \
++	/* packets retried again (ps pretend) prior to moving power save mode */ \
++	uint32 ps_retry; \
++	 /* suppressed packet count */ \
++	uint32 suppress; \
++	/* packets finally dropped after retry limit */ \
++	uint32 retry_drop; \
++	/* the high-water mark of the queue capacity for packets - goes to zero as queue fills */ \
++	uint32 max_avail; \
++	/* the high-water mark of the queue utilisation for packets - ('inverse' of max_avail) */ \
++	uint32 max_used; \
++	 /* the maximum capacity of the queue */ \
++	uint32 queue_capacity; \
++	/* count of rts attempts that failed to receive cts */ \
++	uint32 rtsfail; \
++	/* count of packets sent (acked) successfully */ \
++	uint32 acked; \
++	/* running total of phy rate of packets sent successfully */ \
++	uint32 txrate_succ; \
++	/* running total of phy 'main' rate */ \
++	uint32 txrate_main; \
++	/* actual data transferred successfully */ \
++	uint32 throughput; \
++	/* time difference since last pktq_stats */ \
++	uint32 time_delta;
++
++typedef struct {
++	PKTQ_LOG_COUNTERS_V4
++} pktq_log_counters_v04_t;
++
++/** v5 is the same as V4 with extra parameter */
++typedef struct {
++	PKTQ_LOG_COUNTERS_V4
++	/** cumulative time to transmit */
++	uint32 airtime;
++} pktq_log_counters_v05_t;
++
++typedef struct {
++	uint8                num_prec[WL_IOV_MAC_PARAM_LEN];
++	pktq_log_counters_v04_t  counters[WL_IOV_MAC_PARAM_LEN][WL_IOV_PKTQ_LOG_PRECS];
++	uint32               counter_info[WL_IOV_MAC_PARAM_LEN];
++	uint32               pspretend_time_delta[WL_IOV_MAC_PARAM_LEN];
++	char                 headings[];
++} pktq_log_format_v04_t;
++
++typedef struct {
++	uint8                num_prec[WL_IOV_MAC_PARAM_LEN];
++	pktq_log_counters_v05_t  counters[WL_IOV_MAC_PARAM_LEN][WL_IOV_PKTQ_LOG_PRECS];
++	uint32               counter_info[WL_IOV_MAC_PARAM_LEN];
++	uint32               pspretend_time_delta[WL_IOV_MAC_PARAM_LEN];
++	char                 headings[];
++} pktq_log_format_v05_t;
++
++
++typedef struct {
++	uint32               version;
++	wl_iov_mac_params_t  params;
++	union {
++		pktq_log_format_v04_t v04;
++		pktq_log_format_v05_t v05;
++	} pktq_log;
++} wl_iov_pktq_log_t;
++
++/* PKTQ_LOG_AUTO, PKTQ_LOG_DEF_PREC flags introduced in v05, they are ignored by v04 */
++#define PKTQ_LOG_AUTO     (1 << 31)
++#define PKTQ_LOG_DEF_PREC (1 << 30)
++
++typedef struct wl_pfn_macaddr_cfg_0 {
++	uint8 version;
++	uint8 reserved;
++	struct ether_addr macaddr;
++} wl_pfn_macaddr_cfg_0_t;
++#define LEGACY1_WL_PFN_MACADDR_CFG_VER 0
++#define WL_PFN_MAC_OUI_ONLY_MASK      1
++#define WL_PFN_SET_MAC_UNASSOC_MASK   2
++#define WL_PFN_RESTRICT_LA_MAC_MASK   4
++#define WL_PFN_MACADDR_FLAG_MASK     0x7
++/** To configure pfn_macaddr */
++typedef struct wl_pfn_macaddr_cfg {
++	uint8 version;
++	uint8 flags;
++	struct ether_addr macaddr;
++} wl_pfn_macaddr_cfg_t;
++#define WL_PFN_MACADDR_CFG_VER 1
++
++/*
++ * SCB_BS_DATA iovar definitions start.
++ */
++#define SCB_BS_DATA_STRUCT_VERSION	1
++
++/** The actual counters maintained for each station */
++typedef struct {
++	/* The following counters are a subset of what pktq_stats provides per precedence. */
++	uint32 retry;          /**< packets re-sent because they were not received */
++	uint32 retry_drop;     /**< packets finally dropped after retry limit */
++	uint32 rtsfail;        /**< count of rts attempts that failed to receive cts */
++	uint32 acked;          /**< count of packets sent (acked) successfully */
++	uint32 txrate_succ;    /**< running total of phy rate of packets sent successfully */
++	uint32 txrate_main;    /**< running total of phy 'main' rate */
++	uint32 throughput;     /**< actual data transferred successfully */
++	uint32 time_delta;     /**< time difference since last pktq_stats */
++	uint32 airtime;        /**< cumulative total medium access delay in useconds */
++} iov_bs_data_counters_t;
++
++/** The structure for individual station information. */
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	struct ether_addr	station_address;	/**< The station MAC address */
++	uint16			station_flags;		/**< Bit mask of flags, for future use. */
++	iov_bs_data_counters_t	station_counters;	/**< The actual counter values */
++} BWL_POST_PACKED_STRUCT iov_bs_data_record_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint16	structure_version;	/**< Structure version number (for wl/wlu matching) */
++	uint16	structure_count;	/**< Number of iov_bs_data_record_t records following */
++	iov_bs_data_record_t	structure_record[1];	/**< 0 - structure_count records */
++} BWL_POST_PACKED_STRUCT iov_bs_data_struct_t;
++#include <packed_section_end.h>
++
++/* Bitmask of options that can be passed in to the iovar. */
++enum {
++	SCB_BS_DATA_FLAG_NO_RESET = (1<<0)	/**< Do not clear the counters after reading */
++};
++/*
++ * SCB_BS_DATA iovar definitions end.
++ */
++
++typedef struct wlc_extlog_cfg {
++	int32 max_number;
++	uint16 module;	/**< bitmap */
++	uint8 level;
++	uint8 flag;
++	uint16 version;
++	uint16 PAD;
++} wlc_extlog_cfg_t;
++
++typedef struct log_record {
++	uint32 time;
++	uint16 module;
++	uint16 id;
++	uint8 level;
++	uint8 sub_unit;
++	uint8 seq_num;
++	uint8 pad;
++	int32 arg;
++	char  str[MAX_ARGSTR_LEN];
++	char  PAD[4-MAX_ARGSTR_LEN%4];
++} log_record_t;
++
++typedef struct wlc_extlog_req {
++	uint32 from_last;
++	uint32 num;
++} wlc_extlog_req_t;
++
++typedef struct wlc_extlog_results {
++	uint16 version;
++	uint16 record_len;
++	uint32 num;
++	log_record_t logs[1];
++} wlc_extlog_results_t;
++
++typedef struct log_idstr {
++	uint16	id;
++	uint16	flag;
++	uint8	arg_type;
++	const char	*fmt_str;
++} log_idstr_t;
++
++#define FMTSTRF_USER		1
++
++/* flat ID definitions
++ * New definitions HAVE TO BE ADDED at the end of the table. Otherwise, it will
++ * affect backward compatibility with pre-existing apps
++ */
++typedef enum {
++	FMTSTR_DRIVER_UP_ID = 0,
++	FMTSTR_DRIVER_DOWN_ID = 1,
++	FMTSTR_SUSPEND_MAC_FAIL_ID = 2,
++	FMTSTR_NO_PROGRESS_ID = 3,
++	FMTSTR_RFDISABLE_ID = 4,
++	FMTSTR_REG_PRINT_ID = 5,
++	FMTSTR_EXPTIME_ID = 6,
++	FMTSTR_JOIN_START_ID = 7,
++	FMTSTR_JOIN_COMPLETE_ID = 8,
++	FMTSTR_NO_NETWORKS_ID = 9,
++	FMTSTR_SECURITY_MISMATCH_ID = 10,
++	FMTSTR_RATE_MISMATCH_ID = 11,
++	FMTSTR_AP_PRUNED_ID = 12,
++	FMTSTR_KEY_INSERTED_ID = 13,
++	FMTSTR_DEAUTH_ID = 14,
++	FMTSTR_DISASSOC_ID = 15,
++	FMTSTR_LINK_UP_ID = 16,
++	FMTSTR_LINK_DOWN_ID = 17,
++	FMTSTR_RADIO_HW_OFF_ID = 18,
++	FMTSTR_RADIO_HW_ON_ID = 19,
++	FMTSTR_EVENT_DESC_ID = 20,
++	FMTSTR_PNP_SET_POWER_ID = 21,
++	FMTSTR_RADIO_SW_OFF_ID = 22,
++	FMTSTR_RADIO_SW_ON_ID = 23,
++	FMTSTR_PWD_MISMATCH_ID = 24,
++	FMTSTR_FATAL_ERROR_ID = 25,
++	FMTSTR_AUTH_FAIL_ID = 26,
++	FMTSTR_ASSOC_FAIL_ID = 27,
++	FMTSTR_IBSS_FAIL_ID = 28,
++	FMTSTR_EXTAP_FAIL_ID = 29,
++	FMTSTR_MAX_ID
++} log_fmtstr_id_t;
++
++/** 11k Neighbor Report element (unversioned, deprecated) */
++typedef struct nbr_element {
++	uint8 id;
++	uint8 len;
++	struct ether_addr bssid;
++	uint32 bssid_info;
++	uint8 reg;
++	uint8 channel;
++	uint8 phytype;
++	uint8 pad;
++} nbr_element_t;
++
++#define WL_RRM_NBR_RPT_VER		1
++/** 11k Neighbor Report element */
++typedef struct nbr_rpt_elem {
++	uint8 version;
++	uint8 id;
++	uint8 len;
++	uint8 pad;
++	struct ether_addr bssid;
++	uint8 pad_1[2];
++	uint32 bssid_info;
++	uint8 reg;
++	uint8 channel;
++	uint8 phytype;
++	uint8 pad_2;
++	wlc_ssid_t ssid;
++	chanspec_t chanspec;
++	uint8 bss_trans_preference;
++	uint8 flags;
++} nbr_rpt_elem_t;
++
++typedef enum event_msgs_ext_command {
++	EVENTMSGS_NONE		=	0,
++	EVENTMSGS_SET_BIT	=	1,
++	EVENTMSGS_RESET_BIT	=	2,
++	EVENTMSGS_SET_MASK	=	3
++} event_msgs_ext_command_t;
++
++#define EVENTMSGS_VER 1
++#define EVENTMSGS_EXT_STRUCT_SIZE	OFFSETOF(eventmsgs_ext_t, mask[0])
++
++/* len-	for SET it would be mask size from the application to the firmware */
++/*		for GET it would be actual firmware mask size */
++/* maxgetsize -	is only used for GET. indicate max mask size that the */
++/*				application can read from the firmware */
++typedef struct eventmsgs_ext
++{
++	uint8	ver;
++	uint8	command;
++	uint8	len;
++	uint8	maxgetsize;
++	uint8	mask[1];
++} eventmsgs_ext_t;
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct pcie_bus_tput_params {
++	/** no of host dma descriptors programmed by the firmware before a commit */
++	uint16		max_dma_descriptors;
++
++	uint16		host_buf_len; /**< length of host buffer */
++	dmaaddr_t	host_buf_addr; /**< physical address for bus_throughput_buf */
++} BWL_POST_PACKED_STRUCT pcie_bus_tput_params_t;
++#include <packed_section_end.h>
++
++typedef struct pcie_bus_tput_stats {
++	uint16		time_taken; /**< no of secs the test is run */
++	uint16		nbytes_per_descriptor; /**< no of bytes of data dma ed per descriptor */
++
++	/** no of desciptors for which dma is sucessfully completed within the test time */
++	uint32		count;
++} pcie_bus_tput_stats_t;
++
++typedef struct keepalives_max_idle {
++	uint16  keepalive_count;        /**< nmbr of keepalives per bss_max_idle period */
++	uint8   mkeepalive_index;       /**< mkeepalive_index for keepalive frame to be used */
++	uint8   PAD;			/**< to align next field */
++	uint16  max_interval;           /**< seconds */
++} keepalives_max_idle_t;
++
++#define PM_IGNORE_BCMC_PROXY_ARP (1 << 0)
++#define PM_IGNORE_BCMC_ALL_DMS_ACCEPTED (1 << 1)
++
++/* ##### Power Stats section ##### */
++
++#define WL_PWRSTATS_VERSION	2
++
++/** Input structure for pwrstats IOVAR */
++typedef struct wl_pwrstats_query {
++	uint16 length;		/**< Number of entries in type array. */
++	uint16 type[1];		/**< Types (tags) to retrieve.
++				 * Length 0 (no types) means get all.
++				 */
++} wl_pwrstats_query_t;
++
++/** This structure is for version 2; version 1 will be deprecated in by FW */
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct wl_pwrstats {
++	uint16 version;		      /**< Version = 2 is TLV format */
++	uint16 length;		      /**< Length of entire structure */
++	uint8 data[1];		      /**< TLV data, a series of structures,
++				       * each starting with type and length.
++				       *
++				       * Padded as necessary so each section
++				       * starts on a 4-byte boundary.
++				       *
++				       * Both type and len are uint16, but the
++				       * upper nibble of length is reserved so
++				       * valid len values are 0-4095.
++				       */
++} BWL_POST_PACKED_STRUCT wl_pwrstats_t;
++#include <packed_section_end.h>
++#define WL_PWR_STATS_HDRLEN	OFFSETOF(wl_pwrstats_t, data)
++
++/* Bits for wake reasons */
++#define WLC_PMD_WAKE_SET		0x1
++#define WLC_PMD_PM_AWAKE_BCN		0x2
++/* BIT:3 is no longer being used */
++#define WLC_PMD_SCAN_IN_PROGRESS	0x8
++#define WLC_PMD_RM_IN_PROGRESS		0x10
++#define WLC_PMD_AS_IN_PROGRESS		0x20
++#define WLC_PMD_PM_PEND			0x40
++#define WLC_PMD_PS_POLL			0x80
++#define WLC_PMD_CHK_UNALIGN_TBTT	0x100
++#define WLC_PMD_APSD_STA_UP		0x200
++#define WLC_PMD_TX_PEND_WAR		0x400   /* obsolete, can be reused */
++#define WLC_PMD_GPTIMER_STAY_AWAKE	0x800
++#define WLC_PMD_PM2_RADIO_SOFF_PEND	0x2000
++#define WLC_PMD_NON_PRIM_STA_UP		0x4000
++#define WLC_PMD_AP_UP			0x8000
++
++typedef struct wlc_pm_debug {
++	uint32 timestamp;	     /**< timestamp in millisecond */
++	uint32 reason;		     /**< reason(s) for staying awake */
++} wlc_pm_debug_t;
++
++/** WL_PWRSTATS_TYPE_PM_AWAKE1 structures (for 6.25 firmware) */
++#define WLC_STA_AWAKE_STATES_MAX_V1	30
++#define WLC_PMD_EVENT_MAX_V1		32
++/** Data sent as part of pwrstats IOVAR (and EXCESS_PM_WAKE event) */
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct pm_awake_data_v1 {
++	uint32 curr_time;	/**< ms */
++	uint32 hw_macc;		/**< HW maccontrol */
++	uint32 sw_macc;		/**< SW maccontrol */
++	uint32 pm_dur;		/**< Total sleep time in PM, msecs */
++	uint32 mpc_dur;		/**< Total sleep time in MPC, msecs */
++
++	/* int32 drifts = remote - local; +ve drift => local-clk slow */
++	int32 last_drift;	/**< Most recent TSF drift from beacon */
++	int32 min_drift;	/**< Min TSF drift from beacon in magnitude */
++	int32 max_drift;	/**< Max TSF drift from beacon in magnitude */
++
++	uint32 avg_drift;	/**< Avg TSF drift from beacon */
++
++	/* Wake history tracking */
++	uint8  pmwake_idx;				   /**< for stepping through pm_state */
++	wlc_pm_debug_t pm_state[WLC_STA_AWAKE_STATES_MAX_V1]; /**< timestamped wake bits */
++	uint32 pmd_event_wake_dur[WLC_PMD_EVENT_MAX_V1];   /**< cumulative usecs per wake reason */
++	uint32 drift_cnt;	/**< Count of drift readings over which avg_drift was computed */
++} BWL_POST_PACKED_STRUCT pm_awake_data_v1_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct wl_pwr_pm_awake_stats_v1 {
++	uint16 type;	     /**< WL_PWRSTATS_TYPE_PM_AWAKE */
++	uint16 len;	     /**< Up to 4K-1, top 4 bits are reserved */
++
++	pm_awake_data_v1_t awake_data;
++	uint32 frts_time;	/**< Cumulative ms spent in frts since driver load */
++	uint32 frts_end_cnt;	/**< No of times frts ended since driver load */
++} BWL_POST_PACKED_STRUCT wl_pwr_pm_awake_stats_v1_t;
++#include <packed_section_end.h>
++
++/** WL_PWRSTATS_TYPE_PM_AWAKE2 structures. Data sent as part of pwrstats IOVAR */
++typedef struct pm_awake_data_v2 {
++	uint32 curr_time;	/**< ms */
++	uint32 hw_macc;		/**< HW maccontrol */
++	uint32 sw_macc;		/**< SW maccontrol */
++	uint32 pm_dur;		/**< Total sleep time in PM, msecs */
++	uint32 mpc_dur;		/**< Total sleep time in MPC, msecs */
++
++	/* int32 drifts = remote - local; +ve drift => local-clk slow */
++	int32 last_drift;	/**< Most recent TSF drift from beacon */
++	int32 min_drift;	/**< Min TSF drift from beacon in magnitude */
++	int32 max_drift;	/**< Max TSF drift from beacon in magnitude */
++
++	uint32 avg_drift;	/**< Avg TSF drift from beacon */
++
++	/* Wake history tracking */
++
++	/* pmstate array (type wlc_pm_debug_t) start offset */
++	uint16 pm_state_offset;
++	/** pmstate number of array entries */
++	uint16 pm_state_len;
++
++	/** array (type uint32) start offset */
++	uint16 pmd_event_wake_dur_offset;
++	/** pmd_event_wake_dur number of array entries */
++	uint16 pmd_event_wake_dur_len;
++
++	uint32 drift_cnt;	/**< Count of drift readings over which avg_drift was computed */
++	uint8  pmwake_idx;	/**< for stepping through pm_state */
++	uint8  flags;		/**< bit0: 1-sleep, 0- wake. bit1: 0-bit0 invlid, 1-bit0 valid */
++	uint8  pad[2];
++	uint32 frts_time;	/**< Cumulative ms spent in frts since driver load */
++	uint32 frts_end_cnt;	/**< No of times frts ended since driver load */
++} pm_awake_data_v2_t;
++
++typedef struct wl_pwr_pm_awake_stats_v2 {
++	uint16 type;	     /**< WL_PWRSTATS_TYPE_PM_AWAKE */
++	uint16 len;	     /**< Up to 4K-1, top 4 bits are reserved */
++
++	pm_awake_data_v2_t awake_data;
++} wl_pwr_pm_awake_stats_v2_t;
++
++/* bit0: 1-sleep, 0- wake. bit1: 0-bit0 invlid, 1-bit0 valid */
++#define WL_PWR_PM_AWAKE_STATS_WAKE      0x02
++#define WL_PWR_PM_AWAKE_STATS_ASLEEP    0x03
++#define WL_PWR_PM_AWAKE_STATS_WAKE_MASK 0x03
++
++/* WL_PWRSTATS_TYPE_PM_AWAKE Version 2 structures taken from 4324/43342 */
++/* These structures are only to be used with 4324/43342 devices */
++
++#define WL_STA_AWAKE_STATES_MAX_V2	30
++#define WL_PMD_EVENT_MAX_V2		32
++#define MAX_P2P_BSS_DTIM_PRD		4
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct ucode_dbg_v2 {
++	uint32 macctrl;
++	uint16 m_p2p_hps;
++	uint16 m_p2p_bss_dtim_prd[MAX_P2P_BSS_DTIM_PRD];
++	uint32 psmdebug[20];
++	uint32 phydebug[20];
++	uint32 psm_brc;
++	uint32 ifsstat;
++} BWL_POST_PACKED_STRUCT ucode_dbg_v2_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct pmalert_awake_data_v2 {
++	uint32 curr_time;	/* ms */
++	uint32 hw_macc;		/* HW maccontrol */
++	uint32 sw_macc;		/* SW maccontrol */
++	uint32 pm_dur;		/* Total sleep time in PM, msecs */
++	uint32 mpc_dur;		/* Total sleep time in MPC, msecs */
++
++	/* int32 drifts = remote - local; +ve drift => local-clk slow */
++	int32 last_drift;	/* Most recent TSF drift from beacon */
++	int32 min_drift;	/* Min TSF drift from beacon in magnitude */
++	int32 max_drift;	/* Max TSF drift from beacon in magnitude */
++
++	uint32 avg_drift;	/* Avg TSF drift from beacon */
++
++	/* Wake history tracking */
++	uint8  pmwake_idx;				   /* for stepping through pm_state */
++	wlc_pm_debug_t pm_state[WL_STA_AWAKE_STATES_MAX_V2]; /* timestamped wake bits */
++	uint32 pmd_event_wake_dur[WL_PMD_EVENT_MAX_V2];      /* cumulative usecs per wake reason */
++	uint32 drift_cnt;	/* Count of drift readings over which avg_drift was computed */
++	uint32	start_event_dur[WL_PMD_EVENT_MAX_V2]; /* start event-duration */
++	ucode_dbg_v2_t ud;
++	uint32 frts_time;	/* Cumulative ms spent in frts since driver load */
++	uint32 frts_end_cnt;	/* No of times frts ended since driver load */
++} BWL_POST_PACKED_STRUCT pmalert_awake_data_v2_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct pm_alert_data_v2 {
++	uint32 version;
++	uint32 length; /* Length of entire structure */
++	uint32 reasons; /* reason(s) for pm_alert */
++	/* Following fields are present only for reasons
++	 * PM_DUR_EXCEEDED, MPC_DUR_EXCEEDED & CONST_AWAKE_DUR_EXCEEDED
++	 */
++	uint32 prev_stats_time;	/* msecs */
++	uint32 prev_pm_dur;	/* msecs */
++	uint32 prev_mpc_dur;	/* msecs */
++	pmalert_awake_data_v2_t awake_data;
++} BWL_POST_PACKED_STRUCT pm_alert_data_v2_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct wl_pwr_pm_awake_status_v2 {
++	uint16 type;	     /* WL_PWRSTATS_TYPE_PM_AWAKE */
++	uint16 len;	     /* Up to 4K-1, top 4 bits are reserved */
++
++	pmalert_awake_data_v2_t awake_data;
++	uint32 frts_time;	/* Cumulative ms spent in frts since driver load */
++	uint32 frts_end_cnt;	/* No of times frts ended since driver load */
++} BWL_POST_PACKED_STRUCT wl_pwr_pm_awake_status_v2_t;
++#include <packed_section_end.h>
++
++/* Below are latest definitions from PHO25178RC100_BRANCH_6_50 */
++/* wl_pwr_pm_awake_stats_v1_t is used for WL_PWRSTATS_TYPE_PM_AWAKE */
++/* (at least) the chip independent registers */
++typedef struct ucode_dbg_ext {
++	uint32 x120;
++	uint32 x124;
++	uint32 x154;
++	uint32 x158;
++	uint32 x15c;
++	uint32 x180;
++	uint32 x184;
++	uint32 x188;
++	uint32 x18c;
++	uint32 x1a0;
++	uint32 x1a8;
++	uint32 x1e0;
++	uint32 scr_x14;
++	uint32 scr_x2b;
++	uint32 scr_x2c;
++	uint32 scr_x2d;
++	uint32 scr_x2e;
++
++	uint16 x40a;
++	uint16 x480;
++	uint16 x490;
++	uint16 x492;
++	uint16 x4d8;
++	uint16 x4b8;
++	uint16 x4ba;
++	uint16 x4bc;
++	uint16 x4be;
++	uint16 x500;
++	uint16 x50e;
++	uint16 x522;
++	uint16 x546;
++	uint16 x578;
++	uint16 x602;
++	uint16 x646;
++	uint16 x648;
++	uint16 x666;
++	uint16 x670;
++	uint16 x690;
++	uint16 x692;
++	uint16 x6a0;
++	uint16 x6a2;
++	uint16 x6a4;
++	uint16 x6b2;
++	uint16 x7c0;
++
++	uint16 shm_x20;
++	uint16 shm_x4a;
++	uint16 shm_x5e;
++	uint16 shm_x5f;
++	uint16 shm_xaab;
++	uint16 shm_x74a;
++	uint16 shm_x74b;
++	uint16 shm_x74c;
++	uint16 shm_x74e;
++	uint16 shm_x756;
++	uint16 shm_x75b;
++	uint16 shm_x7b9;
++	uint16 shm_x7d4;
++
++	uint16 shm_P2P_HPS;
++	uint16 shm_P2P_intr[16];
++	uint16 shm_P2P_perbss[48];
++} ucode_dbg_ext_t;
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct pm_alert_data_v1 {
++	uint32 version;
++	uint32 length; /**< Length of entire structure */
++	uint32 reasons; /**< reason(s) for pm_alert */
++	/* Following fields are present only for reasons
++	 * PM_DUR_EXCEEDED, MPC_DUR_EXCEEDED & CONST_AWAKE_DUR_EXCEEDED
++	 */
++	uint32 prev_stats_time;	/**< msecs */
++	uint32 prev_pm_dur;	/**< msecs */
++	uint32 prev_mpc_dur;	/**< msecs */
++	pm_awake_data_v1_t awake_data;
++	uint32	start_event_dur[WLC_PMD_EVENT_MAX_V1]; /**< start event-duration */
++	ucode_dbg_v2_t ud;
++	uint32 frts_time;	/**< Cumulative ms spent in frts since driver load */
++	uint32 frts_end_cnt;	/**< No of times frts ended since driver load */
++	ucode_dbg_ext_t ud_ext;
++	uint32 prev_frts_dur; /**< ms */
++} BWL_POST_PACKED_STRUCT pm_alert_data_v1_t;
++#include <packed_section_end.h>
++
++/* End of 43342/4324 v2 structure definitions */
++
++/* Original bus structure is for HSIC */
++
++typedef struct bus_metrics {
++	uint32 suspend_ct;	/**< suspend count */
++	uint32 resume_ct;	/**< resume count */
++	uint32 disconnect_ct;	/**< disconnect count */
++	uint32 reconnect_ct;	/**< reconnect count */
++	uint32 active_dur;	/**< msecs in bus, usecs for user */
++	uint32 suspend_dur;	/**< msecs in bus, usecs for user */
++	uint32 disconnect_dur;	/**< msecs in bus, usecs for user */
++} bus_metrics_t;
++
++/** Bus interface info for USB/HSIC */
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct wl_pwr_usb_hsic_stats {
++	uint16 type;	     /**< WL_PWRSTATS_TYPE_USB_HSIC */
++	uint16 len;	     /**< Up to 4K-1, top 4 bits are reserved */
++
++	bus_metrics_t hsic;	/**< stats from hsic bus driver */
++} BWL_POST_PACKED_STRUCT wl_pwr_usb_hsic_stats_t;
++#include <packed_section_end.h>
++
++typedef struct pcie_bus_metrics {
++	uint32 d3_suspend_ct;	/**< suspend count */
++	uint32 d0_resume_ct;	/**< resume count */
++	uint32 perst_assrt_ct;	/**< PERST# assert count */
++	uint32 perst_deassrt_ct;	/**< PERST# de-assert count */
++	uint32 active_dur;	/**< msecs */
++	uint32 d3_suspend_dur;	/**< msecs */
++	uint32 perst_dur;	/**< msecs */
++	uint32 l0_cnt;		/**< L0 entry count */
++	uint32 l0_usecs;	/**< L0 duration in usecs */
++	uint32 l1_cnt;		/**< L1 entry count */
++	uint32 l1_usecs;	/**< L1 duration in usecs */
++	uint32 l1_1_cnt;	/**< L1_1ss entry count */
++	uint32 l1_1_usecs;	/**< L1_1ss duration in usecs */
++	uint32 l1_2_cnt;	/**< L1_2ss entry count */
++	uint32 l1_2_usecs;	/**< L1_2ss duration in usecs */
++	uint32 l2_cnt;		/**< L2 entry count */
++	uint32 l2_usecs;	/**< L2 duration in usecs */
++	uint32 timestamp;	/**< Timestamp on when stats are collected */
++	uint32 num_h2d_doorbell;	/**< # of doorbell interrupts - h2d */
++	uint32 num_d2h_doorbell;	/**< # of doorbell interrupts - d2h */
++	uint32 num_submissions; /**< # of submissions */
++	uint32 num_completions; /**< # of completions */
++	uint32 num_rxcmplt;	/**< # of rx completions */
++	uint32 num_rxcmplt_drbl;	/**< of drbl interrupts for rx complt. */
++	uint32 num_txstatus;	/**< # of tx completions */
++	uint32 num_txstatus_drbl;	/**< of drbl interrupts for tx complt. */
++	uint32 deepsleep_count; /**< # of times chip went to deepsleep */
++	uint32 deepsleep_dur;   /**< # of msecs chip was in deepsleep */
++	uint32 ltr_active_ct;	/**< # of times chip went to LTR ACTIVE */
++	uint32 ltr_active_dur;	/**< # of msecs chip was in LTR ACTIVE */
++	uint32 ltr_sleep_ct;	/**< # of times chip went to LTR SLEEP */
++	uint32 ltr_sleep_dur;	/**< # of msecs chip was in LTR SLEEP */
++} pcie_bus_metrics_t;
++
++/** Bus interface info for PCIE */
++typedef struct wl_pwr_pcie_stats {
++	uint16 type;	     /**< WL_PWRSTATS_TYPE_PCIE */
++	uint16 len;	     /**< Up to 4K-1, top 4 bits are reserved */
++	pcie_bus_metrics_t pcie;	/**< stats from pcie bus driver */
++} wl_pwr_pcie_stats_t;
++
++/** Scan information history per category */
++typedef struct scan_data {
++	uint32 count;		/**< Number of scans performed */
++	uint32 dur;		/**< Total time (in us) used */
++} scan_data_t;
++
++typedef struct wl_pwr_scan_stats {
++	uint16 type;	     /**< WL_PWRSTATS_TYPE_SCAN */
++	uint16 len;	     /**< Up to 4K-1, top 4 bits are reserved */
++
++	/* Scan history */
++	scan_data_t user_scans;	  /**< User-requested scans: (i/e/p)scan */
++	scan_data_t assoc_scans;  /**< Scans initiated by association requests */
++	scan_data_t roam_scans;	  /**< Scans initiated by the roam engine */
++	scan_data_t pno_scans[8]; /**< For future PNO bucketing (BSSID, SSID, etc) */
++	scan_data_t other_scans;  /**< Scan engine usage not assigned to the above */
++} wl_pwr_scan_stats_t;
++
++typedef struct wl_pwr_connect_stats {
++	uint16 type;	     /**< WL_PWRSTATS_TYPE_SCAN */
++	uint16 len;	     /**< Up to 4K-1, top 4 bits are reserved */
++
++	/* Connection (Association + Key exchange) data */
++	uint32 count;	/**< Number of connections performed */
++	uint32 dur;		/**< Total time (in ms) used */
++} wl_pwr_connect_stats_t;
++
++typedef struct wl_pwr_phy_stats {
++	uint16 type;	    /**< WL_PWRSTATS_TYPE_PHY */
++	uint16 len;	    /**< Up to 4K-1, top 4 bits are reserved */
++	uint32 tx_dur;	    /**< TX Active duration in us */
++	uint32 rx_dur;	    /**< RX Active duration in us */
++} wl_pwr_phy_stats_t;
++
++
++typedef struct wl_mimo_meas_metrics_v1 {
++	uint16 type;
++	uint16 len;
++	/* Total time(us) idle in MIMO RX chain configuration */
++	uint32 total_idle_time_mimo;
++	/* Total time(us) idle in SISO  RX chain configuration */
++	uint32 total_idle_time_siso;
++	/* Total receive time (us) in SISO RX chain configuration */
++	uint32 total_rx_time_siso;
++	/* Total receive time (us) in MIMO RX chain configuration */
++	uint32 total_rx_time_mimo;
++	/* Total 1-chain transmit time(us) */
++	uint32 total_tx_time_1chain;
++	/* Total 2-chain transmit time(us) */
++	uint32 total_tx_time_2chain;
++	/* Total 3-chain transmit time(us) */
++	uint32 total_tx_time_3chain;
++} wl_mimo_meas_metrics_v1_t;
++
++typedef struct wl_mimo_meas_metrics {
++	uint16 type;
++	uint16 len;
++	/* Total time(us) idle in MIMO RX chain configuration */
++	uint32 total_idle_time_mimo;
++	/* Total time(us) idle in SISO  RX chain configuration */
++	uint32 total_idle_time_siso;
++	/* Total receive time (us) in SISO RX chain configuration */
++	uint32 total_rx_time_siso;
++	/* Total receive time (us) in MIMO RX chain configuration */
++	uint32 total_rx_time_mimo;
++	/* Total 1-chain transmit time(us) */
++	uint32 total_tx_time_1chain;
++	/* Total 2-chain transmit time(us) */
++	uint32 total_tx_time_2chain;
++	/* Total 3-chain transmit time(us) */
++	uint32 total_tx_time_3chain;
++	/* End of original, OCL fields start here */
++	/* Total time(us) idle in ocl mode */
++	uint32 total_idle_time_ocl;
++	/* Total receive time (us) in ocl mode */
++	uint32 total_rx_time_ocl;
++	/* End of OCL fields, internal adjustment fields here */
++	/* Total SIFS idle time in MIMO mode */
++	uint32 total_sifs_time_mimo;
++	/* Total SIFS idle time in SISO mode */
++	uint32 total_sifs_time_siso;
++} wl_mimo_meas_metrics_t;
++/* ##### End of Power Stats section ##### */
++
++/** IPV4 Arp offloads for ndis context */
++#include <packed_section_start.h>
++BWL_PRE_PACKED_STRUCT struct hostip_id {
++	struct ipv4_addr ipa;
++	uint8 id;
++} BWL_POST_PACKED_STRUCT;
++#include <packed_section_end.h>
++
++/* Return values */
++#define ND_REPLY_PEER		0x1	/**< Reply was sent to service NS request from peer */
++#define ND_REQ_SINK		0x2	/**< Input packet should be discarded */
++#define ND_FORCE_FORWARD	0X3	/**< For the dongle to forward req to HOST */
++
++/** Neighbor Solicitation Response Offload IOVAR param */
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct nd_param {
++	struct ipv6_addr	host_ip[2];
++	struct ipv6_addr	solicit_ip;
++	struct ipv6_addr	remote_ip;
++	uint8	host_mac[ETHER_ADDR_LEN];
++	uint32	offload_id;
++} BWL_POST_PACKED_STRUCT nd_param_t;
++#include <packed_section_end.h>
++
++typedef struct wl_pfn_roam_thresh {
++	uint32 pfn_alert_thresh; /**< time in ms */
++	uint32 roam_alert_thresh; /**< time in ms */
++} wl_pfn_roam_thresh_t;
++
++
++/* Reasons for wl_pmalert_t */
++#define PM_DUR_EXCEEDED			(1<<0)
++#define MPC_DUR_EXCEEDED		(1<<1)
++#define ROAM_ALERT_THRESH_EXCEEDED	(1<<2)
++#define PFN_ALERT_THRESH_EXCEEDED	(1<<3)
++#define CONST_AWAKE_DUR_ALERT		(1<<4)
++#define CONST_AWAKE_DUR_RECOVERY	(1<<5)
++
++#define MIN_PM_ALERT_LEN 9
++
++/** Data sent in EXCESS_PM_WAKE event */
++#define WL_PM_ALERT_VERSION 3
++
++/** This structure is for version 3; version 2 will be deprecated in by FW */
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct wl_pmalert {
++	uint16 version;		/**< Version = 3 is TLV format */
++	uint16 length;		/**< Length of entire structure */
++	uint32 reasons;		/**< reason(s) for pm_alert */
++	uint8 data[1];		/**< TLV data, a series of structures,
++				 * each starting with type and length.
++				 *
++				 * Padded as necessary so each section
++				 * starts on a 4-byte boundary.
++				 *
++				 * Both type and len are uint16, but the
++				 * upper nibble of length is reserved so
++				 * valid len values are 0-4095.
++				*/
++} BWL_POST_PACKED_STRUCT wl_pmalert_t;
++#include <packed_section_end.h>
++
++/* Type values for the data section */
++#define WL_PMALERT_FIXED	0	/**< struct wl_pmalert_fixed_t, fixed fields */
++#define WL_PMALERT_PMSTATE	1	/**< struct wl_pmalert_pmstate_t, variable */
++#define WL_PMALERT_EVENT_DUR	2	/**< struct wl_pmalert_event_dur_t, variable */
++#define WL_PMALERT_UCODE_DBG	3	/**< struct wl_pmalert_ucode_dbg_v1, variable */
++#define WL_PMALERT_PS_ALLOWED_HIST	4 /**< struct wl_pmalert_ps_allowed_history, variable */
++#define WL_PMALERT_EXT_UCODE_DBG	5 /**< struct wl_pmalert_ext_ucode_dbg_t, variable */
++#define WL_PMALERT_EPM_START_EVENT_DUR	6 /**< struct wl_pmalert_event_dur_t, variable */
++#define WL_PMALERT_UCODE_DBG_V2		7 /**< struct wl_pmalert_ucode_dbg_v2, variable */
++
++typedef struct wl_pmalert_fixed {
++	uint16 type;		/**< WL_PMALERT_FIXED */
++	uint16 len;		/**< Up to 4K-1, top 4 bits are reserved */
++	uint32 prev_stats_time;	/**< msecs */
++	uint32 curr_time;	/**< ms */
++	uint32 prev_pm_dur;	/**< msecs */
++	uint32 pm_dur;		/**< Total sleep time in PM, msecs */
++	uint32 prev_mpc_dur;	/**< msecs */
++	uint32 mpc_dur;		/**< Total sleep time in MPC, msecs */
++	uint32 hw_macc;		/**< HW maccontrol */
++	uint32 sw_macc;		/**< SW maccontrol */
++
++	/* int32 drifts = remote - local; +ve drift -> local-clk slow */
++	int32 last_drift;	/**< Most recent TSF drift from beacon */
++	int32 min_drift;	/**< Min TSF drift from beacon in magnitude */
++	int32 max_drift;	/**< Max TSF drift from beacon in magnitude */
++
++	uint32 avg_drift;	/**< Avg TSF drift from beacon */
++	uint32 drift_cnt;	/**< Count of drift readings over which avg_drift was computed */
++	uint32 frts_time;	/**< Cumulative ms spent in data frts since driver load */
++	uint32 frts_end_cnt;	/**< No of times frts ended since driver load */
++	uint32 prev_frts_dur;	/**< Data frts duration at start of pm-period */
++	uint32 cal_dur;		/**< Cumulative ms spent in calibration */
++	uint32 prev_cal_dur;	/**< cal duration at start of pm-period */
++} wl_pmalert_fixed_t;
++
++typedef struct wl_pmalert_pmstate {
++	uint16 type;	     /**< WL_PMALERT_PMSTATE */
++	uint16 len;	     /**< Up to 4K-1, top 4 bits are reserved */
++
++	uint8 pmwake_idx;   /**< for stepping through pm_state */
++	uint8 pad[3];
++	/* Array of pmstate; len of array is based on tlv len */
++	wlc_pm_debug_t pmstate[1];
++} wl_pmalert_pmstate_t;
++
++typedef struct wl_pmalert_event_dur {
++	uint16 type;	     /**< WL_PMALERT_EVENT_DUR */
++	uint16 len;	     /**< Up to 4K-1, top 4 bits are reserved */
++
++	/* Array of event_dur, len of array is based on tlv len */
++	uint32 event_dur[1];
++} wl_pmalert_event_dur_t;
++
++#include <packed_section_start.h>
++BWL_PRE_PACKED_STRUCT struct wl_pmalert_ucode_dbg_v1 {
++	uint16 type;         /* WL_PMALERT_UCODE_DBG */
++	uint16 len;      /* Up to 4K-1, top 4 bits are reserved */
++	uint32 macctrl;
++	uint16 m_p2p_hps;
++	uint32 psm_brc;
++	uint32 ifsstat;
++	uint16 m_p2p_bss_dtim_prd[MAX_P2P_BSS_DTIM_PRD];
++	uint32 psmdebug[20];
++	uint32 phydebug[20];
++	uint16 M_P2P_BSS[3][12];
++	uint16 M_P2P_PRE_TBTT[3];
++
++	/* Following is valid only for corerevs<40 */
++	uint16 xmtfifordy;
++
++	/* Following 3 are valid only for 11ac corerevs (>=40) */
++	uint16 psm_maccommand;
++	uint16 txe_status1;
++	uint16 AQMFifoReady;
++} BWL_POST_PACKED_STRUCT;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++BWL_PRE_PACKED_STRUCT struct wl_pmalert_ucode_dbg_v2 {
++	uint16 type;	     /**< WL_PMALERT_UCODE_DBG_V2 */
++	uint16 len;	     /**< Up to 4K-1, top 4 bits are reserved */
++	uint32 macctrl;
++	uint16 m_p2p_hps;
++	uint32 psm_brc;
++	uint32 ifsstat;
++	uint16 m_p2p_bss_dtim_prd[MAX_P2P_BSS_DTIM_PRD];
++	uint32 psmdebug[20];
++	uint32 phydebug[20];
++	uint16 M_P2P_BSS[3][12];
++	uint16 M_P2P_PRE_TBTT[3];
++
++	/* Following is valid only for corerevs<40 */
++	uint16 xmtfifordy;
++
++	/* Following 3 are valid only for 11ac corerevs (>=40) */
++	uint16 psm_maccommand;
++	uint16 txe_status1;
++	uint32 AQMFifoReady;
++} BWL_POST_PACKED_STRUCT;
++#include <packed_section_end.h>
++
++typedef struct wlc_ps_debug {
++	uint32 timestamp;	     /**< timestamp in millisecond */
++	uint32 ps_mask;		     /**< reason(s) for disallowing ps */
++} wlc_ps_debug_t;
++
++typedef struct wl_pmalert_ps_allowed_hist {
++	uint16 type;	     /**< WL_PMALERT_PS_ALLOWED_HIST */
++	uint16 len;	     /**< Up to 4K-1, top 4 bits are reserved */
++	uint32 ps_allowed_start_idx;
++	/* Array of ps_debug, len of array is based on tlv len */
++	wlc_ps_debug_t ps_debug[1];
++} wl_pmalert_ps_allowed_hist_t;
++
++/* Structures and constants used for "vndr_ie" IOVar interface */
++#define VNDR_IE_CMD_LEN		4	/**< length of the set command string:
++					 * "add", "del" (+ NUL)
++					 */
++
++#define VNDR_IE_INFO_HDR_LEN	(sizeof(uint32))
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint32 pktflag;			/**< bitmask indicating which packet(s) contain this IE */
++	vndr_ie_t vndr_ie_data;		/**< vendor IE data */
++} BWL_POST_PACKED_STRUCT vndr_ie_info_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	int32 iecount;			/**< number of entries in the vndr_ie_list[] array */
++	vndr_ie_info_t vndr_ie_list[1];	/**< variable size list of vndr_ie_info_t structs */
++} BWL_POST_PACKED_STRUCT vndr_ie_buf_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	char cmd[VNDR_IE_CMD_LEN];	/**< vndr_ie IOVar set command : "add", "del" + NUL */
++	vndr_ie_buf_t vndr_ie_buffer;	/**< buffer containing Vendor IE list information */
++} BWL_POST_PACKED_STRUCT vndr_ie_setbuf_t;
++#include <packed_section_end.h>
++
++/** tag_ID/length/value_buffer tuple */
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint8	id;
++	uint8	len;
++	uint8	data[1];
++} BWL_POST_PACKED_STRUCT tlv_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint32 pktflag;			/**< bitmask indicating which packet(s) contain this IE */
++	tlv_t ie_data;		/**< IE data */
++} BWL_POST_PACKED_STRUCT ie_info_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	int32 iecount;			/**< number of entries in the ie_list[] array */
++	ie_info_t ie_list[1];	/**< variable size list of ie_info_t structs */
++} BWL_POST_PACKED_STRUCT ie_buf_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	char cmd[VNDR_IE_CMD_LEN];	/**< ie IOVar set command : "add" + NUL */
++	ie_buf_t ie_buffer;	/**< buffer containing IE list information */
++} BWL_POST_PACKED_STRUCT ie_setbuf_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint32 pktflag;		/**< bitmask indicating which packet(s) contain this IE */
++	uint8 id;		/**< IE type */
++} BWL_POST_PACKED_STRUCT ie_getbuf_t;
++#include <packed_section_end.h>
++
++/* structures used to define format of wps ie data from probe requests */
++/* passed up to applications via iovar "prbreq_wpsie" */
++typedef struct sta_prbreq_wps_ie_hdr {
++	struct ether_addr staAddr;
++	uint16 ieLen;
++} sta_prbreq_wps_ie_hdr_t;
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct sta_prbreq_wps_ie_data {
++	sta_prbreq_wps_ie_hdr_t hdr;
++	uint8 ieData[1];
++} BWL_POST_PACKED_STRUCT sta_prbreq_wps_ie_data_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct sta_prbreq_wps_ie_list {
++	uint32 totLen;
++	uint8 ieDataList[1];
++} BWL_POST_PACKED_STRUCT sta_prbreq_wps_ie_list_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint32 flags;
++	chanspec_t chanspec;			/**< txpwr report for this channel */
++	chanspec_t local_chanspec;		/**< channel on which we are associated */
++	uint8 local_max;			/**< local max according to the AP */
++	uint8 local_constraint;			/**< local constraint according to the AP */
++	int8  antgain[2];			/**< Ant gain for each band - from SROM */
++	uint8 rf_cores;				/**< count of RF Cores being reported */
++	uint8 est_Pout[4];			/**< Latest tx power out estimate per RF chain */
++	uint8 est_Pout_act[4]; /**< Latest tx power out estimate per RF chain w/o adjustment */
++	uint8 est_Pout_cck;			/**< Latest CCK tx power out estimate */
++	uint8 tx_power_max[4];			/**< Maximum target power among all rates */
++	uint32 tx_power_max_rate_ind[4];  /**< Index of the rate with the max target power */
++	int8 sar;				/**< SAR limit for display by wl executable */
++	int8 channel_bandwidth;		/**< 20, 40 or 80 MHz bandwidth? */
++	uint8 version;				/**< Version of the data format wlu <--> driver */
++	uint8 display_core;			/**< Displayed curpower core */
++	int8 target_offsets[4];		/**< Target power offsets for current rate per core */
++	uint32 last_tx_ratespec;	/**< Ratespec for last transmition */
++	uint32 user_target;		/**< user limit */
++	uint32 ppr_len;		/**< length of each ppr serialization buffer */
++	int8 SARLIMIT[MAX_STREAMS_SUPPORTED];
++	uint8  pprdata[1];		/**< ppr serialization buffer */
++} BWL_POST_PACKED_STRUCT tx_pwr_rpt_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	struct ipv4_addr	ipv4_addr;
++	struct ether_addr nexthop;
++} BWL_POST_PACKED_STRUCT ibss_route_entry_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint32 num_entry;
++	ibss_route_entry_t route_entry[1];
++} BWL_POST_PACKED_STRUCT ibss_route_tbl_t;
++#include <packed_section_end.h>
++
++#define MAX_IBSS_ROUTE_TBL_ENTRY	64
++
++#define TXPWR_TARGET_VERSION  0
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	int32 version;		/**< version number */
++	chanspec_t chanspec;	/**< txpwr report for this channel */
++	int8 txpwr[WL_STA_ANT_MAX]; /**< Max tx target power, in qdb */
++	uint8 rf_cores;		/**< count of RF Cores being reported */
++} BWL_POST_PACKED_STRUCT txpwr_target_max_t;
++#include <packed_section_end.h>
++
++#define BSS_PEER_INFO_PARAM_CUR_VER	0
++/** Input structure for IOV_BSS_PEER_INFO */
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT	struct {
++	uint16			version;
++	struct	ether_addr ea;	/**< peer MAC address */
++} BWL_POST_PACKED_STRUCT bss_peer_info_param_t;
++#include <packed_section_end.h>
++
++#define BSS_PEER_INFO_CUR_VER		0
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint16			version;
++	struct ether_addr	ea;
++	int32			rssi;
++	uint32			tx_rate;	/**< current tx rate */
++	uint32			rx_rate;	/**< current rx rate */
++	wl_rateset_t		rateset;	/**< rateset in use */
++	uint32			age;		/**< age in seconds */
++} BWL_POST_PACKED_STRUCT bss_peer_info_t;
++#include <packed_section_end.h>
++
++#define BSS_PEER_LIST_INFO_CUR_VER	0
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint16			version;
++	uint16			bss_peer_info_len;	/**< length of bss_peer_info_t */
++	uint32			count;			/**< number of peer info */
++	bss_peer_info_t		peer_info[1];		/**< peer info */
++} BWL_POST_PACKED_STRUCT bss_peer_list_info_t;
++#include <packed_section_end.h>
++
++#define BSS_PEER_LIST_INFO_FIXED_LEN OFFSETOF(bss_peer_list_info_t, peer_info)
++
++#define AIBSS_BCN_FORCE_CONFIG_VER_0	0
++
++/** structure used to configure AIBSS beacon force xmit */
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint16  version;
++	uint16	len;
++	uint32 initial_min_bcn_dur;	/**< dur in ms to check a bcn in bcn_flood period */
++	uint32 min_bcn_dur;	/**< dur in ms to check a bcn after bcn_flood period */
++	uint32 bcn_flood_dur; /**< Initial bcn xmit period in ms */
++} BWL_POST_PACKED_STRUCT aibss_bcn_force_config_t;
++#include <packed_section_end.h>
++
++#define AIBSS_TXFAIL_CONFIG_VER_0    0
++#define AIBSS_TXFAIL_CONFIG_VER_1    1
++#define AIBSS_TXFAIL_CONFIG_CUR_VER		AIBSS_TXFAIL_CONFIG_VER_1
++
++/** structure used to configure aibss tx fail event */
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint16  version;
++	uint16  len;
++	uint32 bcn_timeout;     /**< dur in seconds to receive 1 bcn */
++	uint32 max_tx_retry;     /**< no of consecutive no acks to send txfail event */
++	uint32 max_atim_failure; /**< no of consecutive atim failure */
++} BWL_POST_PACKED_STRUCT aibss_txfail_config_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct wl_aibss_if {
++	uint16 version;
++	uint16 len;
++	uint32 flags;
++	struct ether_addr addr;
++	chanspec_t chspec;
++} BWL_POST_PACKED_STRUCT wl_aibss_if_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct wlc_ipfo_route_entry {
++	struct ipv4_addr ip_addr;
++	struct ether_addr nexthop;
++} BWL_POST_PACKED_STRUCT wlc_ipfo_route_entry_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct wlc_ipfo_route_tbl {
++	uint32 num_entry;
++	wlc_ipfo_route_entry_t route_entry[1];
++} BWL_POST_PACKED_STRUCT wlc_ipfo_route_tbl_t;
++#include <packed_section_end.h>
++
++/* Version of wlc_btc_stats_t structure.
++ * Increment whenever a change is made to wlc_btc_stats_t
++ */
++#define BTCX_STATS_VER   2
++
++typedef struct wlc_btc_stats {
++	uint16 version; /* version number of struct */
++	uint16 valid; /* Size of this struct */
++	uint32 stats_update_timestamp;	/* tStamp when data is updated. */
++	uint32 btc_status; /* Hybrid/TDM indicator: Bit2:Hybrid, Bit1:TDM,Bit0:CoexEnabled */
++	uint32 bt_req_type_map; /* BT Antenna Req types since last stats sample */
++	uint32 bt_req_cnt; /* #BT antenna requests since last stats sampl */
++	uint32 bt_gnt_cnt; /* #BT antenna grants since last stats sample */
++	uint32 bt_gnt_dur; /* usec BT owns antenna since last stats sample */
++	uint16 bt_abort_cnt; /* #Times WL was preempted due to BT since WL up */
++	uint16 bt_rxf1ovfl_cnt; /* #Time PSNULL retry count exceeded since WL up */
++	uint16 bt_latency_cnt; /* #Time ucode high latency detected since WL up */
++	uint16 rsvd; /* pad to align struct to 32bit bndry	 */
++} wlc_btc_stats_t;
++
++#define WL_IPFO_ROUTE_TBL_FIXED_LEN 4
++#define WL_MAX_IPFO_ROUTE_TBL_ENTRY	64
++
++	/* Global ASSERT Logging */
++#define ASSERTLOG_CUR_VER	0x0100
++#define MAX_ASSRTSTR_LEN	64
++
++	typedef struct assert_record {
++		uint32 time;
++		uint8 seq_num;
++		int8 str[MAX_ASSRTSTR_LEN];
++	} assert_record_t;
++
++	typedef struct assertlog_results {
++		uint16 version;
++		uint16 record_len;
++		uint32 num;
++		assert_record_t logs[1];
++	} assertlog_results_t;
++
++#define LOGRRC_FIX_LEN	8
++#define IOBUF_ALLOWED_NUM_OF_LOGREC(type, len) ((len - LOGRRC_FIX_LEN)/sizeof(type))
++#ifdef BCMWAPI_WAI
++/* BCMWAPI_WAI */
++#define IV_LEN 16
++	struct wapi_sta_msg_t
++	{
++		uint16	msg_type;
++		uint16	datalen;
++		uint8	vap_mac[6];
++		uint8	reserve_data1[2];
++		uint8	sta_mac[6];
++		uint8	reserve_data2[2];
++		uint8	gsn[IV_LEN];
++		uint8	wie[256];
++	};
++#endif /* BCMWAPI_WAI */
++	/* chanim acs record */
++	typedef struct {
++		uint8 valid;
++		uint8 trigger;
++		chanspec_t selected_chspc;
++		int8 bgnoise;
++		uint32 glitch_cnt;
++		uint8 ccastats;
++		uint8 chan_idle;
++		uint32 timestamp;
++	} chanim_acs_record_t;
++
++	typedef struct {
++		chanim_acs_record_t acs_record[CHANIM_ACS_RECORD];
++		uint8 count;
++		uint32 timestamp;
++	} wl_acs_record_t;
++
++#define WL_CHANIM_STATS_V2 2
++#define CCASTATS_V2_MAX 9
++typedef struct chanim_stats_v2 {
++	uint32 glitchcnt;               /**< normalized as per second count */
++	uint32 badplcp;                 /**< normalized as per second count */
++	uint8 ccastats[CCASTATS_V2_MAX];   /**< normalized as 0-255 */
++	int8 bgnoise;                   /**< background noise level (in dBm) */
++	chanspec_t chanspec;            /**< ctrl chanspec of the interface */
++	uint32 timestamp;               /**< time stamp at which the stats are collected */
++	uint32 bphy_glitchcnt;          /**< normalized as per second count */
++	uint32 bphy_badplcp;            /**< normalized as per second count */
++	uint8 chan_idle;                /**< normalized as 0~255 */
++	uint8 PAD[3];
++} chanim_stats_v2_t;
++
++typedef struct chanim_stats {
++	uint32 glitchcnt;               /**< normalized as per second count */
++	uint32 badplcp;                 /**< normalized as per second count */
++	uint8 ccastats[CCASTATS_MAX];   /**< normalized as 0-255 */
++	int8 bgnoise;                   /**< background noise level (in dBm) */
++	uint8 pad_1[11 - CCASTATS_MAX];
++	chanspec_t chanspec;            /**< ctrl chanspec of the interface */
++	uint8 pad_2[2];
++	uint32 timestamp;               /**< time stamp at which the stats are collected */
++	uint32 bphy_glitchcnt;          /**< normalized as per second count */
++	uint32 bphy_badplcp;            /**< normalized as per second count */
++	uint8 chan_idle;                /**< normalized as 0~255 */
++	uint8 PAD[3];
++} chanim_stats_t;
++
++#define WL_CHANIM_STATS_VERSION 3
++typedef struct {
++	uint32 buflen;
++	uint32 version;
++	uint32 count;
++	chanim_stats_t stats[1];
++} wl_chanim_stats_t;
++
++#define WL_CHANIM_STATS_FIXED_LEN OFFSETOF(wl_chanim_stats_t, stats)
++
++/** Noise measurement metrics. */
++#define NOISE_MEASURE_KNOISE	0x1
++
++/** scb probe parameter */
++typedef struct {
++	uint32 scb_timeout;
++	uint32 scb_activity_time;
++	uint32 scb_max_probe;
++} wl_scb_probe_t;
++
++/* structure/defines for selective mgmt frame (smf) stats support */
++
++#define SMFS_VERSION 1
++/** selected mgmt frame (smf) stats element */
++typedef struct wl_smfs_elem {
++	uint32 count;
++	uint16 code;  /**< SC or RC code */
++	uint8 PAD[2];
++} wl_smfs_elem_t;
++
++typedef struct wl_smf_stats {
++	uint32 version;
++	uint16 length;	/**< reserved for future usage */
++	uint8 type;
++	uint8 codetype;
++	uint32 ignored_cnt;
++	uint32 malformed_cnt;
++	uint32 count_total; /**< count included the interested group */
++	wl_smfs_elem_t elem[1];
++} wl_smf_stats_t;
++
++#define WL_SMFSTATS_FIXED_LEN OFFSETOF(wl_smf_stats_t, elem);
++
++enum {
++	SMFS_CODETYPE_SC,
++	SMFS_CODETYPE_RC
++};
++
++typedef enum smfs_type {
++	SMFS_TYPE_AUTH,
++	SMFS_TYPE_ASSOC,
++	SMFS_TYPE_REASSOC,
++	SMFS_TYPE_DISASSOC_TX,
++	SMFS_TYPE_DISASSOC_RX,
++	SMFS_TYPE_DEAUTH_TX,
++	SMFS_TYPE_DEAUTH_RX,
++	SMFS_TYPE_MAX
++} smfs_type_t;
++
++/* #ifdef PHYMON */
++
++#define PHYMON_VERSION 1
++
++typedef struct wl_phycal_core_state {
++	/* Tx IQ/LO calibration coeffs */
++	int16 tx_iqlocal_a;
++	int16 tx_iqlocal_b;
++	int8 tx_iqlocal_ci;
++	int8 tx_iqlocal_cq;
++	int8 tx_iqlocal_di;
++	int8 tx_iqlocal_dq;
++	int8 tx_iqlocal_ei;
++	int8 tx_iqlocal_eq;
++	int8 tx_iqlocal_fi;
++	int8 tx_iqlocal_fq;
++
++	/** Rx IQ calibration coeffs */
++	int16 rx_iqcal_a;
++	int16 rx_iqcal_b;
++
++	uint8 tx_iqlocal_pwridx; /**< Tx Power Index for Tx IQ/LO calibration */
++	uint8 PAD[3];
++	uint32 papd_epsilon_table[64]; /**< PAPD epsilon table */
++	int16 papd_epsilon_offset; /**< PAPD epsilon offset */
++	uint8 curr_tx_pwrindex; /**< Tx power index */
++	int8 idle_tssi; /**< Idle TSSI */
++	int8 est_tx_pwr; /**< Estimated Tx Power (dB) */
++	int8 est_rx_pwr; /**< Estimated Rx Power (dB) from RSSI */
++	uint16 rx_gaininfo; /**< Rx gain applied on last Rx pkt */
++	uint16 init_gaincode; /**< initgain required for ACI */
++	int8 estirr_tx;
++	int8 estirr_rx;
++} wl_phycal_core_state_t;
++
++typedef struct wl_phycal_state {
++	int32 version;
++	int8 num_phy_cores; /**< number of cores */
++	int8 curr_temperature; /**< on-chip temperature sensor reading */
++	chanspec_t chspec; /**< channspec for this state */
++	uint8 aci_state; /**< ACI state: ON/OFF */
++	uint8 PAD;
++	uint16 crsminpower; /**< crsminpower required for ACI */
++	uint16 crsminpowerl; /**< crsminpowerl required for ACI */
++	uint16 crsminpoweru; /**< crsminpoweru required for ACI */
++	wl_phycal_core_state_t phycal_core[1];
++} wl_phycal_state_t;
++
++#define WL_PHYCAL_STAT_FIXED_LEN OFFSETOF(wl_phycal_state_t, phycal_core)
++/* endif PHYMON */
++
++/** discovery state */
++typedef struct wl_p2p_disc_st {
++	uint8 state;	/**< see state */
++	uint8 PAD;
++	chanspec_t chspec;	/**< valid in listen state */
++	uint16 dwell;	/**< valid in listen state, in ms */
++} wl_p2p_disc_st_t;
++
++/** scan request */
++typedef struct wl_p2p_scan {
++	uint8 type;		/**< 'S' for WLC_SCAN, 'E' for "escan" */
++	uint8 reserved[3];
++	/* scan or escan parms... */
++} wl_p2p_scan_t;
++
++/** i/f request */
++typedef struct wl_p2p_if {
++	struct ether_addr addr;
++	uint8 type;	/**< see i/f type */
++	uint8 PAD;
++	chanspec_t chspec;	/**< for p2p_ifadd GO */
++} wl_p2p_if_t;
++
++/** i/f query */
++typedef struct wl_p2p_ifq {
++	uint32 bsscfgidx;
++	char ifname[BCM_MSG_IFNAME_MAX];
++} wl_p2p_ifq_t;
++
++/** OppPS & CTWindow */
++typedef struct wl_p2p_ops {
++	uint8 ops;	/**< 0: disable 1: enable */
++	uint8 ctw;	/**< >= 10 */
++} wl_p2p_ops_t;
++
++/** absence and presence request */
++typedef struct wl_p2p_sched_desc {
++	uint32 start;
++	uint32 interval;
++	uint32 duration;
++	uint32 count;	/**< see count */
++} wl_p2p_sched_desc_t;
++
++typedef struct wl_p2p_sched {
++	uint8 type;	/**< see schedule type */
++	uint8 action;	/**< see schedule action */
++	uint8 option;	/**< see schedule option */
++	uint8 PAD;
++	wl_p2p_sched_desc_t desc[1];
++} wl_p2p_sched_t;
++
++typedef struct wl_p2p_wfds_hash {
++	uint32	advt_id;
++	uint16	nw_cfg_method;
++	uint8	wfds_hash[6];
++	uint8	name_len;
++	uint8	service_name[MAX_WFDS_SVC_NAME_LEN];
++	uint8	PAD[3];
++} wl_p2p_wfds_hash_t;
++
++typedef struct wl_bcmdcs_data {
++	uint32 reason;
++	chanspec_t chspec;
++	uint8	PAD[2];
++} wl_bcmdcs_data_t;
++/* ifdef EXT_STA */
++/**
++ * Format of IHV data passed to OID_DOT11_NIC_SPECIFIC_EXTENSION.
++ */
++typedef struct _IHV_NIC_SPECIFIC_EXTENSION {
++	uint8			oui[4];     /**< vendor specific OUI value */
++	uint32			event;      /**< event code */
++	uint8			ihvData[1];    /**< ihv data */
++} IHV_NIC_SPECIFIC_EXTENSION, *PIHV_NIC_SPECIFIC_EXTENSION;
++#define IHV_NIC_SPECIFIC_EXTENTION_HEADER	OFFSETOF(IHV_NIC_SPECIFIC_EXTENSION, ihvData[0])
++/* EXT_STA */
++/** NAT configuration */
++typedef struct {
++	uint32 ipaddr;		/**< interface ip address */
++	uint32 ipaddr_mask;	/**< interface ip address mask */
++	uint32 ipaddr_gateway;	/**< gateway ip address */
++	uint8 mac_gateway[6];	/**< gateway mac address */
++	uint8	PAD[2];
++	uint32 ipaddr_dns;	/**< DNS server ip address, valid only for public if */
++	uint8 mac_dns[6];	/**< DNS server mac address,  valid only for public if */
++	uint8 GUID[38];		/**< interface GUID */
++} nat_if_info_t;
++
++typedef struct {
++	uint32 op;		/**< operation code */
++	uint8 pub_if;		/**< set for public if, clear for private if */
++	uint8	PAD[3];
++	nat_if_info_t if_info;	/**< interface info */
++} nat_cfg_t;
++
++typedef struct {
++	int32 state;	/**< NAT state returned */
++} nat_state_t;
++
++typedef struct flush_txfifo {
++	uint32 txfifobmp;
++	uint32 hwtxfifoflush;
++	struct ether_addr ea;
++	uint8	PAD[2];
++} flush_txfifo_t;
++
++enum {
++	SPATIAL_MODE_2G_IDX = 0,
++	SPATIAL_MODE_5G_LOW_IDX,
++	SPATIAL_MODE_5G_MID_IDX,
++	SPATIAL_MODE_5G_HIGH_IDX,
++	SPATIAL_MODE_5G_UPPER_IDX,
++	SPATIAL_MODE_MAX_IDX
++};
++
++#define WLC_TXCORE_MAX		4	/**< max number of txcore supports */
++#define WLC_TXCORE_MAX_OLD	2	/**< backward compatibilty for TXCAL */
++#define WLC_SUBBAND_MAX		4	/**< max number of sub-band supports */
++typedef struct {
++	uint8	band2g[WLC_TXCORE_MAX];
++	uint8	band5g[WLC_SUBBAND_MAX][WLC_TXCORE_MAX];
++} sar_limit_t;
++
++#define MAX_NUM_TXCAL_MEAS 128
++#define MAX_NUM_PWR_STEP 40
++#define TXCAL_IOVAR_VERSION	0x1
++typedef struct wl_txcal_meas_percore {
++	uint16 tssi[MAX_NUM_TXCAL_MEAS];
++	int16 pwr[MAX_NUM_TXCAL_MEAS];
++} wl_txcal_meas_percore_t;
++
++typedef struct wl_txcal_meas_ncore {
++	uint16 version;
++	uint8 valid_cnt;
++	uint8 num_core;
++	wl_txcal_meas_percore_t txcal_percore[1];
++} wl_txcal_meas_ncore_t;
++
++typedef struct wl_txcal_power_tssi_percore {
++	int16 tempsense;
++	int16 pwr_start;
++	uint8 pwr_start_idx;
++	uint8 num_entries;
++	uint16 pad;
++	uint8 tssi[MAX_NUM_PWR_STEP];
++} wl_txcal_power_tssi_percore_t;
++
++typedef struct wl_txcal_power_tssi_ncore {
++	uint16 version;
++	uint8 set_core;
++	uint8 channel;
++	uint8 num_core;
++	uint8 gen_tbl;
++	uint16 pad;
++	wl_txcal_power_tssi_percore_t tssi_percore[1];
++} wl_txcal_power_tssi_ncore_t;
++
++typedef struct wl_txcal_meas {
++	uint16 tssi[WLC_TXCORE_MAX][MAX_NUM_TXCAL_MEAS];
++	int16 pwr[WLC_TXCORE_MAX][MAX_NUM_TXCAL_MEAS];
++	uint8 valid_cnt;
++	uint8 PAD;
++} wl_txcal_meas_t;
++
++typedef struct wl_txcal_meas_old {
++	uint16 tssi[WLC_TXCORE_MAX_OLD][MAX_NUM_TXCAL_MEAS];
++	int16 pwr[WLC_TXCORE_MAX_OLD][MAX_NUM_TXCAL_MEAS];
++	uint8 valid_cnt;
++	uint8 PAD;
++} wl_txcal_meas_old_t;
++
++typedef struct wl_txcal_power_tssi {
++	uint8 set_core;
++	uint8 channel;
++	int16 tempsense[WLC_TXCORE_MAX];
++	int16 pwr_start[WLC_TXCORE_MAX];
++	uint8 pwr_start_idx[WLC_TXCORE_MAX];
++	uint8 num_entries[WLC_TXCORE_MAX];
++	uint8 tssi[WLC_TXCORE_MAX][MAX_NUM_PWR_STEP];
++	uint8 gen_tbl;
++	uint8 PAD;
++} wl_txcal_power_tssi_t;
++
++typedef struct wl_txcal_power_tssi_old {
++	uint8 set_core;
++	uint8 channel;
++	int16 tempsense[WLC_TXCORE_MAX_OLD];
++	int16 pwr_start[WLC_TXCORE_MAX_OLD];
++	uint8 pwr_start_idx[WLC_TXCORE_MAX_OLD];
++	uint8 num_entries[WLC_TXCORE_MAX_OLD];
++	uint8 tssi[WLC_TXCORE_MAX_OLD][MAX_NUM_PWR_STEP];
++	uint8 gen_tbl;
++	uint8 PAD;
++} wl_txcal_power_tssi_old_t;
++
++typedef struct wl_olpc_pwr {
++	uint16 version;
++	uint8 core;
++	uint8 channel;
++	int16 tempsense;
++	uint8 olpc_idx;
++	uint8 pad;
++} wl_olpc_pwr_t;
++
++/** IOVAR "mempool" parameter. Used to retrieve a list of memory pool statistics. */
++typedef struct wl_mempool_stats {
++	int32 num;		/**< Number of memory pools */
++	bcm_mp_stats_t s[1];	/**< Variable array of memory pool stats. */
++} wl_mempool_stats_t;
++
++typedef struct {
++	uint32 ipaddr;
++	uint32 ipaddr_netmask;
++	uint32 ipaddr_gateway;
++} nwoe_ifconfig_t;
++
++/** Traffic management priority classes */
++typedef enum trf_mgmt_priority_class {
++	trf_mgmt_priority_low           = 0,        /**< Maps to 802.1p BK */
++	trf_mgmt_priority_medium        = 1,        /**< Maps to 802.1p BE */
++	trf_mgmt_priority_high          = 2,        /**< Maps to 802.1p VI */
++	trf_mgmt_priority_nochange	= 3,	    /**< do not update the priority */
++	trf_mgmt_priority_invalid       = (trf_mgmt_priority_nochange + 1)
++} trf_mgmt_priority_class_t;
++
++/** Traffic management configuration parameters */
++typedef struct trf_mgmt_config {
++	uint32  trf_mgmt_enabled;                           /**< 0 - disabled, 1 - enabled */
++	uint32  flags;                                      /**< See TRF_MGMT_FLAG_xxx defines */
++	uint32  host_ip_addr;                              /**< My IP address to determine subnet */
++	uint32  host_subnet_mask;                           /**< My subnet mask */
++	uint32  downlink_bandwidth;                         /**< In units of kbps */
++	uint32  uplink_bandwidth;                           /**< In units of kbps */
++	uint32  min_tx_bandwidth[TRF_MGMT_MAX_PRIORITIES];  /**< Minimum guaranteed tx bandwidth */
++	uint32  min_rx_bandwidth[TRF_MGMT_MAX_PRIORITIES];  /**< Minimum guaranteed rx bandwidth */
++} trf_mgmt_config_t;
++
++/** Traffic management filter */
++typedef struct trf_mgmt_filter {
++	struct ether_addr           dst_ether_addr;         /**< His L2 address */
++	uint8						PAD[2];
++	uint32                      dst_ip_addr;            /**< His IP address */
++	uint16                      dst_port;               /**< His L4 port */
++	uint16                      src_port;               /**< My L4 port */
++	uint16                      prot;                   /**< L4 protocol (only TCP or UDP) */
++	uint16                      flags;                  /**< TBD. For now, this must be zero. */
++	trf_mgmt_priority_class_t   priority;               /**< Priority for filtered packets */
++	uint32                      dscp;                   /**< DSCP */
++} trf_mgmt_filter_t;
++
++/** Traffic management filter list (variable length) */
++typedef struct trf_mgmt_filter_list     {
++	uint32              num_filters;
++	trf_mgmt_filter_t   filter[1];
++} trf_mgmt_filter_list_t;
++
++/** Traffic management global info used for all queues */
++typedef struct trf_mgmt_global_info {
++	uint32  maximum_bytes_per_second;
++	uint32  maximum_bytes_per_sampling_period;
++	uint32  total_bytes_consumed_per_second;
++	uint32  total_bytes_consumed_per_sampling_period;
++	uint32  total_unused_bytes_per_sampling_period;
++} trf_mgmt_global_info_t;
++
++/** Traffic management shaping info per priority queue */
++typedef struct trf_mgmt_shaping_info {
++	uint32  gauranteed_bandwidth_percentage;
++	uint32  guaranteed_bytes_per_second;
++	uint32  guaranteed_bytes_per_sampling_period;
++	uint32  num_bytes_produced_per_second;
++	uint32  num_bytes_consumed_per_second;
++	uint32  num_queued_packets;                         /**< Number of packets in queue */
++	uint32  num_queued_bytes;                           /**< Number of bytes in queue */
++} trf_mgmt_shaping_info_t;
++
++/** Traffic management shaping info array */
++typedef struct trf_mgmt_shaping_info_array {
++	trf_mgmt_global_info_t   tx_global_shaping_info;
++	trf_mgmt_shaping_info_t  tx_queue_shaping_info[TRF_MGMT_MAX_PRIORITIES];
++	trf_mgmt_global_info_t   rx_global_shaping_info;
++	trf_mgmt_shaping_info_t  rx_queue_shaping_info[TRF_MGMT_MAX_PRIORITIES];
++} trf_mgmt_shaping_info_array_t;
++
++
++/** Traffic management statistical counters */
++typedef struct trf_mgmt_stats {
++	uint32  num_processed_packets;      /**< Number of packets processed */
++	uint32  num_processed_bytes;        /**< Number of bytes processed */
++	uint32  num_discarded_packets;      /**< Number of packets discarded from queue */
++} trf_mgmt_stats_t;
++
++/** Traffic management statistics array */
++typedef struct trf_mgmt_stats_array {
++	trf_mgmt_stats_t  tx_queue_stats[TRF_MGMT_MAX_PRIORITIES];
++	trf_mgmt_stats_t  rx_queue_stats[TRF_MGMT_MAX_PRIORITIES];
++} trf_mgmt_stats_array_t;
++
++/* Both powersel_params and lpc_params are used by IOVAR lpc_params.
++ * The powersel_params is replaced by lpc_params in later WLC versions.
++ */
++typedef struct powersel_params {
++	/* LPC Params exposed via IOVAR */
++	int32		tp_ratio_thresh;  /**< Throughput ratio threshold */
++	uint8		rate_stab_thresh; /**< Thresh for rate stability based on nupd */
++	uint8		pwr_stab_thresh; /**< Number of successes before power step down */
++	uint8		pwr_sel_exp_time; /**< Time lapse for expiry of database */
++	uint8		PAD;
++} powersel_params_t;
++
++#define WL_LPC_PARAMS_VER_2	2
++#define WL_LPC_PARAMS_CURRENT_VERSION WL_LPC_PARAMS_VER_2
++
++typedef struct lpc_params {
++	uint16		version;
++	uint16		length;
++	/* LPC Params exposed via IOVAR */
++	uint8		rate_stab_thresh; /**< Thresh for rate stability based on nupd */
++	uint8		pwr_stab_thresh; /**< Number of successes before power step down */
++	uint8		lpc_exp_time; /**< Time lapse for expiry of database */
++	uint8		pwrup_slow_step; /**< Step size for slow step up */
++	uint8		pwrup_fast_step; /**< Step size for fast step up */
++	uint8		pwrdn_slow_step; /**< Step size for slow step down */
++} lpc_params_t;
++
++/* tx pkt delay statistics */
++#define	SCB_RETRY_SHORT_DEF	7	/**< Default Short retry Limit */
++#define WLPKTDLY_HIST_NBINS	16	/**< number of bins used in the Delay histogram */
++
++/** structure to store per-AC delay statistics */
++typedef struct scb_delay_stats {
++	uint32 txmpdu_lost;	/**< number of MPDUs lost */
++	uint32 txmpdu_cnt[SCB_RETRY_SHORT_DEF]; /**< retry times histogram */
++	uint32 delay_sum[SCB_RETRY_SHORT_DEF]; /**< cumulative packet latency */
++	uint32 delay_min;	/**< minimum packet latency observed */
++	uint32 delay_max;	/**< maximum packet latency observed */
++	uint32 delay_avg;	/**< packet latency average */
++	uint32 delay_hist[WLPKTDLY_HIST_NBINS];	/**< delay histogram */
++	uint32 delay_count;	/**< minimum number of time period units before
++				consequent packet delay events can be generated
++				*/
++	uint32 prev_txmpdu_cnt;	/**< Previous value of txmpdu_cnt[] during last iteration */
++	uint32 prev_delay_sum;	/**< Previous value of delay_sum[] during last iteration */
++} scb_delay_stats_t;
++
++/** structure for txdelay event */
++typedef struct txdelay_event {
++	uint8				status;
++	uint8				PAD[3];
++	int32				rssi;
++	chanim_stats_t		chanim_stats;
++	scb_delay_stats_t	delay_stats[AC_COUNT];
++} txdelay_event_t;
++
++/** structure for txdelay parameters */
++typedef struct txdelay_params {
++	uint16	ratio;	/**< Avg Txdelay Delta */
++	uint8	cnt;	/**< Sample cnt */
++	uint8	period;	/**< Sample period */
++	uint8	tune;	/**< Debug */
++	uint8	PAD;
++} txdelay_params_t;
++#define MAX_TXDELAY_STATS_SCBS 6
++#define TXDELAY_STATS_VERSION 1
++
++enum {
++	TXDELAY_STATS_PARTIAL_RESULT = 0,
++	TXDELAY_STATS_FULL_RESULT = 1
++};
++
++typedef struct scb_total_delay_stats {
++	struct  ether_addr ea;
++	uint8   pad[2];
++	scb_delay_stats_t dlystats[AC_COUNT];
++} scb_total_delay_stats_t;
++
++typedef struct txdelay_stats {
++	uint32  version;
++	uint32  full_result;    /* 0:Partial, 1:full */
++	uint32  scb_cnt;        /* in:requested, out:returned */
++	scb_total_delay_stats_t scb_delay_stats[1];
++} txdelay_stats_t;
++
++#define WL_TXDELAY_STATS_FIXED_SIZE \
++	(sizeof(txdelay_stats_t)+(MAX_TXDELAY_STATS_SCBS-1)*sizeof(scb_total_delay_stats_t))
++enum {
++	WNM_SERVICE_DMS = 1,
++	WNM_SERVICE_FMS = 2,
++	WNM_SERVICE_TFS = 3
++};
++
++/** Definitions for WNM/NPS TCLAS */
++typedef struct wl_tclas {
++	uint8 user_priority;
++	uint8 fc_len;
++	dot11_tclas_fc_t fc;
++} wl_tclas_t;
++
++#define WL_TCLAS_FIXED_SIZE	OFFSETOF(wl_tclas_t, fc)
++
++typedef struct wl_tclas_list {
++	uint32 num;
++	wl_tclas_t tclas[];
++} wl_tclas_list_t;
++
++/** Definitions for WNM/NPS Traffic Filter Service */
++typedef struct wl_tfs_req {
++	uint8 tfs_id;
++	uint8 tfs_actcode;
++	uint8 tfs_subelem_id;
++	uint8 send;
++} wl_tfs_req_t;
++
++typedef struct wl_tfs_filter {
++	uint8 status;			/**< Status returned by the AP */
++	uint8 tclas_proc;		/**< TCLAS processing value (0:and, 1:or)  */
++	uint8 tclas_cnt;		/**< count of all wl_tclas_t in tclas array */
++	uint8 tclas[1];			/**< VLA of wl_tclas_t */
++} wl_tfs_filter_t;
++#define WL_TFS_FILTER_FIXED_SIZE	OFFSETOF(wl_tfs_filter_t, tclas)
++
++typedef struct wl_tfs_fset {
++	struct ether_addr ea;		/**< Address of AP/STA involved with this filter set */
++	uint8 tfs_id;			/**< TFS ID field chosen by STA host */
++	uint8 status;			/**< Internal status TFS_STATUS_xxx */
++	uint8 actcode;			/**< Action code DOT11_TFS_ACTCODE_xxx */
++	uint8 token;			/**< Token used in last request frame */
++	uint8 notify;			/**< Notify frame sent/received because of this set */
++	uint8 filter_cnt;		/**< count of all wl_tfs_filter_t in filter array */
++	uint8 filter[1];		/**< VLA of wl_tfs_filter_t */
++} wl_tfs_fset_t;
++#define WL_TFS_FSET_FIXED_SIZE		OFFSETOF(wl_tfs_fset_t, filter)
++
++enum {
++	TFS_STATUS_DISABLED = 0,	/**< TFS filter set disabled by user */
++	TFS_STATUS_DISABLING = 1,	/**< Empty request just sent to AP */
++	TFS_STATUS_VALIDATED = 2,	/**< Filter set validated by AP (but maybe not enabled!) */
++	TFS_STATUS_VALIDATING = 3,	/**< Filter set just sent to AP */
++	TFS_STATUS_NOT_ASSOC = 4,	/**< STA not associated */
++	TFS_STATUS_NOT_SUPPORT = 5,	/**< TFS not supported by AP */
++	TFS_STATUS_DENIED = 6,		/**< Filter set refused by AP (=> all sets are disabled!) */
++};
++
++typedef struct wl_tfs_status {
++	uint8 fset_cnt;			/**< count of all wl_tfs_fset_t in fset array */
++	wl_tfs_fset_t fset[1];		/**< VLA of wl_tfs_fset_t */
++} wl_tfs_status_t;
++
++typedef struct wl_tfs_set {
++	uint8 send;		/**< Immediatly register registered sets on AP side */
++	uint8 tfs_id;		/**< ID of a specific set (existing or new), or nul for all */
++	uint8 actcode;		/**< Action code for this filter set */
++	uint8 tclas_proc;	/**< TCLAS processing operator for this filter set */
++} wl_tfs_set_t;
++
++typedef struct wl_tfs_term {
++	uint8 del;			/**< Delete internal set once confirmation received */
++	uint8 tfs_id;			/**< ID of a specific set (existing), or nul for all */
++} wl_tfs_term_t;
++
++
++#define DMS_DEP_PROXY_ARP (1 << 0)
++
++/* Definitions for WNM/NPS Directed Multicast Service */
++enum {
++	DMS_STATUS_DISABLED = 0,	/**< DMS desc disabled by user */
++	DMS_STATUS_ACCEPTED = 1,	/**< Request accepted by AP */
++	DMS_STATUS_NOT_ASSOC = 2,	/**< STA not associated */
++	DMS_STATUS_NOT_SUPPORT = 3,	/**< DMS not supported by AP */
++	DMS_STATUS_DENIED = 4,		/**< Request denied by AP */
++	DMS_STATUS_TERM = 5,		/**< Request terminated by AP */
++	DMS_STATUS_REMOVING = 6,	/**< Remove request just sent */
++	DMS_STATUS_ADDING = 7,		/**< Add request just sent */
++	DMS_STATUS_ERROR = 8,		/**< Non compliant AP behvior */
++	DMS_STATUS_IN_PROGRESS = 9,	/**< Request just sent */
++	DMS_STATUS_REQ_MISMATCH = 10	/**< Conditions for sending DMS req not met */
++};
++
++typedef struct wl_dms_desc {
++	uint8 user_id;
++	uint8 status;
++	uint8 token;
++	uint8 dms_id;
++	uint8 tclas_proc;
++	uint8 mac_len;		/**< length of all ether_addr in data array, 0 if STA */
++	uint8 tclas_len;	/**< length of all wl_tclas_t in data array */
++	uint8 data[1];		/**< VLA of 'ether_addr' and 'wl_tclas_t' (in this order ) */
++} wl_dms_desc_t;
++
++#define WL_DMS_DESC_FIXED_SIZE	OFFSETOF(wl_dms_desc_t, data)
++
++typedef struct wl_dms_status {
++	uint32 cnt;
++	wl_dms_desc_t desc[1];
++} wl_dms_status_t;
++
++typedef struct wl_dms_set {
++	uint8 send;
++	uint8 user_id;
++	uint8 tclas_proc;
++} wl_dms_set_t;
++
++typedef struct wl_dms_term {
++	uint8 del;
++	uint8 user_id;
++} wl_dms_term_t;
++
++typedef struct wl_service_term {
++	uint8 service;
++	union {
++		wl_dms_term_t dms;
++	} u;
++} wl_service_term_t;
++
++/** Definitions for WNM/NPS BSS Transistion */
++typedef struct wl_bsstrans_req {
++	uint16 tbtt;			/**< time of BSS to end of life, in unit of TBTT */
++	uint16 dur;			/**< time of BSS to keep off, in unit of minute */
++	uint8 reqmode;			/**< request mode of BSS transition request */
++	uint8 unicast;			/**< request by unicast or by broadcast */
++} wl_bsstrans_req_t;
++
++enum {
++	BSSTRANS_RESP_AUTO = 0,		/**< Currently equivalent to ENABLE */
++	BSSTRANS_RESP_DISABLE = 1,	/**< Never answer BSS Trans Req frames */
++	BSSTRANS_RESP_ENABLE = 2,	/**< Always answer Req frames with preset data */
++	BSSTRANS_RESP_WAIT = 3,		/**< Send ind, wait and/or send preset data (NOT IMPL) */
++	BSSTRANS_RESP_IMMEDIATE = 4	/**< After an ind, set data and send resp (NOT IMPL) */
++};
++
++typedef struct wl_bsstrans_resp {
++	uint8 policy;
++	uint8 status;
++	uint8 delay;
++	struct ether_addr target;
++} wl_bsstrans_resp_t;
++
++/* "wnm_bsstrans_policy" argument programs behavior after BSSTRANS Req reception.
++ * BSS-Transition feature is used by multiple programs such as NPS-PF, VE-PF,
++ * Band-steering, Hotspot 2.0 and customer requirements. Each PF and its test plan
++ * mandates different behavior on receiving BSS-transition request. To accomodate
++ * such divergent behaviors these policies have been created.
++ */
++typedef enum {
++	WL_BSSTRANS_POLICY_ROAM_ALWAYS = 0,	/**< Roam (or disassociate) in all cases */
++	WL_BSSTRANS_POLICY_ROAM_IF_MODE = 1,	/**< Roam only if requested by Request Mode field */
++	WL_BSSTRANS_POLICY_ROAM_IF_PREF = 2,	/**< Roam only if Preferred BSS provided */
++	WL_BSSTRANS_POLICY_WAIT = 3,		/**< Wait for deauth and send Accepted status */
++	WL_BSSTRANS_POLICY_PRODUCT = 4,	/**< Policy for real product use cases (Olympic) */
++	WL_BSSTRANS_POLICY_PRODUCT_WBTEXT = 5,	/**< Policy for real product use cases (SS) */
++	WL_BSSTRANS_POLICY_MAX = 6
++} wnm_bsstrans_policy_type_t;
++
++/** Definitions for WNM/NPS TIM Broadcast */
++typedef struct wl_timbc_offset {
++	int16 offset;		/**< offset in us */
++	uint16 fix_intv;	/**< override interval sent from STA */
++	uint16 rate_override;	/**< use rate override to send high rate TIM broadcast frame */
++	uint8 tsf_present;	/**< show timestamp in TIM broadcast frame */
++	uint8 PAD;
++} wl_timbc_offset_t;
++
++typedef struct wl_timbc_set {
++	uint8 interval;		/**< Interval in DTIM wished or required. */
++	uint8 flags;		/**< Bitfield described below */
++	uint16 rate_min;	/**< Minimum rate required for High/Low TIM frames. Optionnal */
++	uint16 rate_max;	/**< Maximum rate required for High/Low TIM frames. Optionnal */
++} wl_timbc_set_t;
++
++enum {
++	WL_TIMBC_SET_TSF_REQUIRED = 1,	/**< Enable TIMBC only if TSF in TIM frames */
++	WL_TIMBC_SET_NO_OVERRIDE = 2,	/**< ... if AP does not override interval */
++	WL_TIMBC_SET_PROXY_ARP = 4,	/**< ... if AP support Proxy ARP */
++	WL_TIMBC_SET_DMS_ACCEPTED = 8	/**< ... if all DMS desc have been accepted */
++};
++
++typedef struct wl_timbc_status {
++	uint8 status_sta;		/**< Status from internal state machine (check below) */
++	uint8 status_ap;		/**< From AP response frame (check 8.4.2.86 from 802.11) */
++	uint8 interval;
++	uint8 pad;
++	int32 offset;
++	uint16 rate_high;
++	uint16 rate_low;
++} wl_timbc_status_t;
++
++enum {
++	WL_TIMBC_STATUS_DISABLE = 0,		/**< TIMBC disabled by user */
++	WL_TIMBC_STATUS_REQ_MISMATCH = 1,	/**< AP settings do no match user requirements */
++	WL_TIMBC_STATUS_NOT_ASSOC = 2,		/**< STA not associated */
++	WL_TIMBC_STATUS_NOT_SUPPORT = 3,	/**< TIMBC not supported by AP */
++	WL_TIMBC_STATUS_DENIED = 4,		/**< Req to disable TIMBC sent to AP */
++	WL_TIMBC_STATUS_ENABLE = 5		/**< TIMBC enabled */
++};
++
++/** Definitions for PM2 Dynamic Fast Return To Sleep */
++typedef struct wl_pm2_sleep_ret_ext {
++	uint8  logic;			/**< DFRTS logic: see WL_DFRTS_LOGIC_* below */
++	uint8  PAD;
++	uint16 low_ms;			/**< Low FRTS timeout */
++	uint16 high_ms;			/**< High FRTS timeout */
++	uint16 rx_pkts_threshold;	/**< switching threshold: # rx pkts */
++	uint16 tx_pkts_threshold;	/**< switching threshold: # tx pkts */
++	uint16 txrx_pkts_threshold;	/**< switching threshold: # (tx+rx) pkts */
++	uint32 rx_bytes_threshold;	/**< switching threshold: # rx bytes */
++	uint32 tx_bytes_threshold;	/**< switching threshold: # tx bytes */
++	uint32 txrx_bytes_threshold;	/**< switching threshold: # (tx+rx) bytes */
++} wl_pm2_sleep_ret_ext_t;
++
++#define WL_DFRTS_LOGIC_OFF	0	/**< Feature is disabled */
++#define WL_DFRTS_LOGIC_OR	1	/**< OR all non-zero threshold conditions */
++#define WL_DFRTS_LOGIC_AND	2	/**< AND all non-zero threshold conditions */
++
++/* Values for the passive_on_restricted_mode iovar.  When set to non-zero, this iovar
++ * disables automatic conversions of a channel from passively scanned to
++ * actively scanned.  These values only have an effect for country codes such
++ * as XZ where some 5 GHz channels are defined to be passively scanned.
++ */
++#define WL_PASSACTCONV_DISABLE_NONE	0	/**< Enable permanent and temporary conversions */
++#define WL_PASSACTCONV_DISABLE_ALL	1	/**< Disable permanent and temporary conversions */
++#define WL_PASSACTCONV_DISABLE_PERM	2	/**< Disable only permanent conversions */
++
++/* Definitions for Reliable Multicast */
++#define WL_RMC_CNT_VERSION	   1
++#define WL_RMC_TR_VERSION	   1
++#define WL_RMC_MAX_CLIENT	   32
++#define WL_RMC_FLAG_INBLACKLIST	   1
++#define WL_RMC_FLAG_ACTIVEACKER	   2
++#define WL_RMC_FLAG_RELMCAST	   4
++#define WL_RMC_MAX_TABLE_ENTRY     4
++
++#define WL_RMC_VER		   1
++#define WL_RMC_INDEX_ACK_ALL       255
++#define WL_RMC_NUM_OF_MC_STREAMS   4
++#define WL_RMC_MAX_TRS_PER_GROUP   1
++#define WL_RMC_MAX_TRS_IN_ACKALL   1
++#define WL_RMC_ACK_MCAST0          0x02
++#define WL_RMC_ACK_MCAST_ALL       0x01
++#define WL_RMC_ACTF_TIME_MIN       300		/**< time in ms */
++#define WL_RMC_ACTF_TIME_MAX       20000	/**< time in ms */
++#define WL_RMC_MAX_NUM_TRS	   32		/**< maximun transmitters allowed */
++#define WL_RMC_ARTMO_MIN           350		/**< time in ms */
++#define WL_RMC_ARTMO_MAX           40000	/**< time in ms */
++
++/* RMC events in action frames */
++enum rmc_opcodes {
++	RELMCAST_ENTRY_OP_DISABLE = 0,   /**< Disable multi-cast group */
++	RELMCAST_ENTRY_OP_DELETE  = 1,   /**< Delete multi-cast group */
++	RELMCAST_ENTRY_OP_ENABLE  = 2,   /**< Enable multi-cast group */
++	RELMCAST_ENTRY_OP_ACK_ALL = 3    /**< Enable ACK ALL bit in AMT */
++};
++
++/* RMC operational modes */
++enum rmc_modes {
++	WL_RMC_MODE_RECEIVER    = 0,	 /**< Receiver mode by default */
++	WL_RMC_MODE_TRANSMITTER = 1,	 /**< Transmitter mode using wl ackreq */
++	WL_RMC_MODE_INITIATOR   = 2	 /**< Initiator mode using wl ackreq */
++};
++
++/** Each RMC mcast client info */
++typedef struct wl_relmcast_client {
++	uint8 flag;			/**< status of client such as AR, R, or blacklisted */
++	uint8 PAD;
++	int16 rssi;			/**< rssi value of RMC client */
++	struct ether_addr addr;		/**< mac address of RMC client */
++} wl_relmcast_client_t;
++
++/** RMC Counters */
++typedef struct wl_rmc_cnts {
++	uint16  version;		/**< see definition of WL_CNT_T_VERSION */
++	uint16  length;			/**< length of entire structure */
++	uint16	dupcnt;			/**< counter for duplicate rmc MPDU */
++	uint16	ackreq_err;		/**< counter for wl ackreq error    */
++	uint16	af_tx_err;		/**< error count for action frame transmit   */
++	uint16	null_tx_err;		/**< error count for rmc null frame transmit */
++	uint16	af_unicast_tx_err;	/**< error count for rmc unicast frame transmit */
++	uint16	mc_no_amt_slot;		/**< No mcast AMT entry available */
++	/* Unused. Keep for rom compatibility */
++	uint16	mc_no_glb_slot;		/**< No mcast entry available in global table */
++	uint16	mc_not_mirrored;	/**< mcast group is not mirrored */
++	uint16	mc_existing_tr;		/**< mcast group is already taken by transmitter */
++	uint16	mc_exist_in_amt;	/**< mcast group is already programmed in amt */
++	/* Unused. Keep for rom compatibility */
++	uint16	mc_not_exist_in_gbl;	/**< mcast group is not in global table */
++	uint16	mc_not_exist_in_amt;	/**< mcast group is not in AMT table */
++	uint16	mc_utilized;		/**< mcast addressed is already taken */
++	uint16	mc_taken_other_tr;	/**< multi-cast addressed is already taken */
++	uint32	rmc_rx_frames_mac;      /**< no of mc frames received from mac */
++	uint32	rmc_tx_frames_mac;      /**< no of mc frames transmitted to mac */
++	uint32	mc_null_ar_cnt;         /**< no. of times NULL AR is received */
++	uint32	mc_ar_role_selected;	/**< no. of times took AR role */
++	uint32	mc_ar_role_deleted;	/**< no. of times AR role cancelled */
++	uint32	mc_noacktimer_expired;  /**< no. of times noack timer expired */
++	uint16  mc_no_wl_clk;           /**< no wl clk detected when trying to access amt */
++	uint16  mc_tr_cnt_exceeded;     /**< No of transmitters in the network exceeded */
++} wl_rmc_cnts_t;
++
++/** RMC Status */
++typedef struct wl_relmcast_st {
++	uint8         ver;		/**< version of RMC */
++	uint8         num;		/**< number of clients detected by transmitter */
++	wl_relmcast_client_t clients[WL_RMC_MAX_CLIENT];
++	uint16        err;		/**< error status (used in infra) */
++	uint16        actf_time;	/**< action frame time period */
++} wl_relmcast_status_t;
++
++/** Entry for each STA/node */
++typedef struct wl_rmc_entry {
++	/* operation on multi-cast entry such add,
++	 * delete, ack-all
++	 */
++	int8    flag;
++	struct ether_addr addr;		/**< multi-cast group mac address */
++} wl_rmc_entry_t;
++
++/** RMC table */
++typedef struct wl_rmc_entry_table {
++	uint8   index;			/**< index to a particular mac entry in table */
++	uint8   opcode;			/**< opcodes or operation on entry */
++	wl_rmc_entry_t entry[WL_RMC_MAX_TABLE_ENTRY];
++} wl_rmc_entry_table_t;
++
++typedef struct wl_rmc_trans_elem {
++	struct ether_addr tr_mac;	/**< transmitter mac */
++	struct ether_addr ar_mac;	/**< ar mac */
++	uint16 artmo;			/**< AR timeout */
++	uint8 amt_idx;			/**< amt table entry */
++	uint8 PAD;
++	uint16 flag;			/**< entry will be acked, not acked, programmed, full etc */
++} wl_rmc_trans_elem_t;
++
++/** RMC transmitters */
++typedef struct wl_rmc_trans_in_network {
++	uint8         ver;		/**< version of RMC */
++	uint8         num_tr;		/**< number of transmitters in the network */
++	wl_rmc_trans_elem_t trs[WL_RMC_MAX_NUM_TRS];
++} wl_rmc_trans_in_network_t;
++
++/** To update vendor specific ie for RMC */
++typedef struct wl_rmc_vsie {
++	uint8	oui[DOT11_OUI_LEN];
++	uint8	PAD;
++	uint16	payload;	/**< IE Data Payload */
++} wl_rmc_vsie_t;
++
++
++/* structures  & defines for proximity detection  */
++enum proxd_method {
++	PROXD_UNDEFINED_METHOD = 0,
++	PROXD_RSSI_METHOD = 1,
++	PROXD_TOF_METHOD = 2
++};
++
++/* structures for proximity detection device role */
++#define WL_PROXD_MODE_DISABLE	0
++#define WL_PROXD_MODE_NEUTRAL	1
++#define WL_PROXD_MODE_INITIATOR	2
++#define WL_PROXD_MODE_TARGET	3
++
++#define WL_PROXD_ACTION_STOP		0
++#define WL_PROXD_ACTION_START		1
++
++#define WL_PROXD_FLAG_TARGET_REPORT	0x1
++#define WL_PROXD_FLAG_REPORT_FAILURE	0x2
++#define WL_PROXD_FLAG_INITIATOR_REPORT	0x4
++#define WL_PROXD_FLAG_NOCHANSWT		0x8
++#define WL_PROXD_FLAG_NETRUAL		0x10
++#define WL_PROXD_FLAG_INITIATOR_RPTRTT	0x20
++#define WL_PROXD_FLAG_ONEWAY		0x40
++#define WL_PROXD_FLAG_SEQ_EN		0x80
++
++#define WL_PROXD_SETFLAG_K		0x1
++#define WL_PROXD_SETFLAG_N		0x2
++#define WL_PROXD_SETFLAG_S		0x4
++
++#define WL_PROXD_SETFLAG_K		0x1
++#define WL_PROXD_SETFLAG_N		0x2
++#define WL_PROXD_SETFLAG_S		0x4
++
++#define WL_PROXD_RANDOM_WAKEUP	0x8000
++#define WL_PROXD_MAXREPORT	8
++
++typedef struct wl_proxd_iovar {
++	uint16	method;		/**< Proximity Detection method */
++	uint16	mode;		/**< Mode (neutral, initiator, target) */
++} wl_proxd_iovar_t;
++
++/*
++ * structures for proximity detection parameters
++ * consists of two parts, common and method specific params
++ * common params should be placed at the beginning
++ */
++
++typedef struct wl_proxd_params_common	{
++	chanspec_t	chanspec;	/**< channel spec */
++	int16		tx_power;	/**< tx power of Proximity Detection(PD) frames (in dBm) */
++	uint16		tx_rate;	/**< tx rate of PD rames  (in 500kbps units) */
++	uint16		timeout;	/**< timeout value */
++	uint16		interval;	/**< interval between neighbor finding attempts (in TU) */
++	uint16		duration;	/**< duration of neighbor finding attempts (in ms) */
++} wl_proxd_params_common_t;
++
++typedef struct wl_proxd_params_rssi_method {
++	chanspec_t	chanspec;	/**< chanspec for home channel */
++	int16		tx_power;	/**< tx power of Proximity Detection frames (in dBm) */
++	uint16		tx_rate;	/**< tx rate of PD frames, 500kbps units */
++	uint16		timeout;	/**< state machine wait timeout of the frames (in ms) */
++	uint16		interval;	/**< interval between neighbor finding attempts (in TU) */
++	uint16		duration;	/**< duration of neighbor finding attempts (in ms) */
++					/* method specific ones go after this line */
++	int16		rssi_thresh;	/**< RSSI threshold (in dBm) */
++	uint16		maxconvergtmo;	/**< max wait converge timeout (in ms) */
++} wl_proxd_params_rssi_method_t;
++
++#define Q1_NS			25	/**< Q1 time units */
++
++#define TOF_BW_NUM		3	/**< number of bandwidth that the TOF can support */
++#define TOF_BW_SEQ_NUM		(TOF_BW_NUM+2)	/* number of total index */
++enum tof_bw_index {
++	TOF_BW_20MHZ_INDEX = 0,
++	TOF_BW_40MHZ_INDEX = 1,
++	TOF_BW_80MHZ_INDEX = 2,
++	TOF_BW_SEQTX_INDEX = 3,
++	TOF_BW_SEQRX_INDEX = 4
++};
++
++#define BANDWIDTH_BASE	20	/**< base value of bandwidth */
++#define TOF_BW_20MHZ    (BANDWIDTH_BASE << TOF_BW_20MHZ_INDEX)
++#define TOF_BW_40MHZ    (BANDWIDTH_BASE << TOF_BW_40MHZ_INDEX)
++#define TOF_BW_80MHZ    (BANDWIDTH_BASE << TOF_BW_80MHZ_INDEX)
++#define TOF_BW_10MHZ    10
++
++#define NFFT_BASE		64	/**< base size of fft */
++#define TOF_NFFT_20MHZ  (NFFT_BASE << TOF_BW_20MHZ_INDEX)
++#define TOF_NFFT_40MHZ  (NFFT_BASE << TOF_BW_40MHZ_INDEX)
++#define TOF_NFFT_80MHZ  (NFFT_BASE << TOF_BW_80MHZ_INDEX)
++
++typedef struct wl_proxd_params_tof_method {
++	chanspec_t	chanspec;	/**< chanspec for home channel */
++	int16		tx_power;	/**< tx power of Proximity Detection(PD) frames (in dBm) */
++	uint16		tx_rate;	/**< tx rate of PD rames  (in 500kbps units) */
++	uint16		timeout;	/**< state machine wait timeout of the frames (in ms) */
++	uint16		interval;	/**< interval between neighbor finding attempts (in TU) */
++	uint16		duration;	/**< duration of neighbor finding attempts (in ms) */
++	/* specific for the method go after this line */
++	struct ether_addr tgt_mac;	/**< target mac addr for TOF method */
++	uint16		ftm_cnt;	/**< number of the frames txed by initiator */
++	uint16		retry_cnt;	/**< number of retransmit attampts for ftm frames */
++	int16		vht_rate;	/**< ht or vht rate */
++	/* add more params required for other methods can be added here  */
++} wl_proxd_params_tof_method_t;
++
++typedef struct wl_proxd_seq_config
++{
++	int16 N_tx_log2;
++	int16 N_rx_log2;
++	int16 N_tx_scale;
++	int16 N_rx_scale;
++	int16 w_len;
++	int16 w_offset;
++} wl_proxd_seq_config_t;
++
++#define WL_PROXD_TUNE_VERSION_1		1
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct wl_proxd_params_tof_tune {
++	uint32		version;
++	uint32		Ki;			/**< h/w delay K factor for initiator */
++	uint32		Kt;			/**< h/w delay K factor for target */
++	int16		vhtack;			/**< enable/disable VHT ACK */
++	int16		N_log2[TOF_BW_SEQ_NUM]; /**< simple threshold crossing */
++	int16		w_offset[TOF_BW_NUM];	/**< offset of threshold crossing window(per BW) */
++	int16		w_len[TOF_BW_NUM];	/**< length of threshold crossing window(per BW) */
++	int32		maxDT;			/**< max time difference of T4/T1 or T3/T2 */
++	int32		minDT;			/**< min time difference of T4/T1 or T3/T2 */
++	uint8		totalfrmcnt;	/**< total count of transfered measurement frames */
++	uint16		rsv_media;		/**< reserve media value for TOF */
++	uint32		flags;			/**< flags */
++	uint8		core;			/**< core to use for tx */
++	uint8		setflags;		/* set flags of K, N. S values  */
++	int16		N_scale[TOF_BW_SEQ_NUM]; /**< simple threshold crossing */
++	uint8		sw_adj;			/**< enable sw assisted timestamp adjustment */
++	uint8		hw_adj;			/**< enable hw assisted timestamp adjustment */
++	uint8		seq_en;			/**< enable ranging sequence */
++	uint8		ftm_cnt[TOF_BW_SEQ_NUM]; /**< number of ftm frames based on bandwidth */
++	int16		N_log2_2g;		/**< simple threshold crossing for 2g channel */
++	int16		N_scale_2g;		/**< simple threshold crossing for 2g channel */
++	wl_proxd_seq_config_t seq_5g20;
++	wl_proxd_seq_config_t seq_2g20;		/* Thresh crossing params for 2G Sequence */
++	uint16          bitflip_thresh;		/* bitflip threshold */
++	uint16          snr_thresh;		/* SNR threshold */
++	int8            recv_2g_thresh;		/* 2g recieve sensitivity threshold */
++	uint32          acs_gdv_thresh;
++	int8            acs_rssi_thresh;
++	uint8           smooth_win_en;
++	int32		acs_gdmm_thresh;
++	int8		acs_delta_rssi_thresh;
++	int32		emu_delay;
++} BWL_POST_PACKED_STRUCT wl_proxd_params_tof_tune_t;
++#include <packed_section_end.h>
++
++typedef struct wl_proxd_params_iovar {
++	uint16	method;			/**< Proximity Detection method */
++	union {
++		/* common params for pdsvc */
++		wl_proxd_params_common_t	cmn_params;	/**< common parameters */
++		/*  method specific */
++		wl_proxd_params_rssi_method_t	rssi_params;	/**< RSSI method parameters */
++		wl_proxd_params_tof_method_t	tof_params;	/**< TOF method parameters */
++		/* tune parameters */
++		wl_proxd_params_tof_tune_t	tof_tune;	/**< TOF tune parameters */
++		uint8	PAD[sizeof(wl_proxd_params_tof_tune_t)+1];
++	} u;				/**< Method specific optional parameters */
++} wl_proxd_params_iovar_t;
++
++#define PROXD_COLLECT_GET_STATUS	0
++#define PROXD_COLLECT_SET_STATUS	1
++#define PROXD_COLLECT_QUERY_HEADER	2
++#define PROXD_COLLECT_QUERY_DATA	3
++#define PROXD_COLLECT_QUERY_DEBUG	4
++#define PROXD_COLLECT_REMOTE_REQUEST	5
++#define PROXD_COLLECT_DONE		6
++
++typedef enum {
++	WL_PROXD_COLLECT_METHOD_TYPE_DISABLE		= 0x0,
++	WL_PROXD_COLLECT_METHOD_TYPE_IOVAR		= 0x1,
++	WL_PROXD_COLLECT_METHOD_TYPE_EVENT		= 0x2,
++	WL_PROXD_COLLECT_METHOD_TYPE_EVENT_LOG		= 0x4
++} wl_proxd_collect_method_type_t;
++
++typedef uint16 wl_proxd_collect_method_t;	/* query status: method to send proxd collect */
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct wl_proxd_collect_query {
++	uint32		method;		/**< method */
++	uint8		request;	/**< Query request. */
++	uint8		status;		/**< bitmask 0 -- disable, 0x1 -- enable collection, */
++					/* 0x2 -- Use generic event, 0x4 -- use event log */
++	uint16		index;		/**< The current frame index [0 to total_frames - 1]. */
++	uint16		mode;		/**< Initiator or Target */
++	uint8		busy;		/**< tof sm is busy */
++	uint8		remote;		/**< Remote collect data */
++} BWL_POST_PACKED_STRUCT wl_proxd_collect_query_t;
++#include <packed_section_end.h>
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct wl_proxd_collect_header {
++	uint16		total_frames;			/**< The total frames for this collect. */
++	uint16		nfft;				/**< nfft value */
++	uint16		bandwidth;			/**< bandwidth */
++	uint16		channel;			/**< channel number */
++	uint32		chanspec;			/**< channel spec */
++	uint32		fpfactor;			/**< avb timer value factor */
++	uint16		fpfactor_shift;			/**< avb timer value shift bits */
++	int32		distance;			/**< distance calculated by fw */
++	uint32		meanrtt;			/**< mean of RTTs */
++	uint32		modertt;			/**< mode of RTTs */
++	uint32		medianrtt;			/**< median of RTTs */
++	uint32		sdrtt;				/**< standard deviation of RTTs */
++	uint32		clkdivisor;			/**< clock divisor */
++	uint16		chipnum;			/**< chip type */
++	uint8		chiprev;			/**< chip revision */
++	uint8		phyver;				/**< phy version */
++	struct ether_addr	localMacAddr;		/**< local mac address */
++	struct ether_addr	remoteMacAddr;		/**< remote mac address */
++	wl_proxd_params_tof_tune_t params;
++} BWL_POST_PACKED_STRUCT wl_proxd_collect_header_t;
++#include <packed_section_end.h>
++
++
++/* ifdef WL_NAN */
++/*  ********************** NAN wl interface struct types and defs ******************** */
++/*
++ * Uses new common IOVAR batch processing mechanism
++ */
++
++/*
++ * NAN config control
++ * Bits 0 - 23 can be set by host
++ * Bits 24 - 31 - Internal use for firmware, host cannot set it
++ */
++
++/*
++ * Bit 0 : If set to 1, means event uses nan bsscfg,
++ * otherwise uses infra bsscfg. Default is using infra bsscfg
++ */
++#define WL_NAN_CTRL_ROUTE_EVENT_VIA_NAN_BSSCFG	0x1
++/* If set, discovery beacons are transmitted on 2G band */
++#define WL_NAN_CTRL_DISC_BEACON_TX_2G		0x2
++/* If set, sync beacons are transmitted on 2G band */
++#define WL_NAN_CTRL_SYNC_BEACON_TX_2G		0x4
++/* If set, discovery beacons are transmitted on 5G band */
++#define WL_NAN_CTRL_DISC_BEACON_TX_5G		0x8
++/* If set, sync beacons are transmitted on 5G band */
++#define WL_NAN_CTRL_SYNC_BEACON_TX_5G		0x10
++/* If set, auto datapath responses will be sent by FW */
++#define WL_NAN_CTRL_AUTO_DPRESP			0x20
++/* If set, auto datapath confirms will be sent by FW */
++#define WL_NAN_CTRL_AUTO_DPCONF			0x40
++
++/* Value when all host-configurable bits set */
++#define WL_NAN_CTRL_MAX_MASK			0xFFFFFF
++#define WL_NAN_CFG_CTRL_FW_BITS			8
++
++/* Bit 31:
++ * If set - indicates that NAN initialization is successful
++ * NOTE: This is a ready-only bit. All sets to this are masked off
++ */
++#define WL_NAN_PROTO_INIT_DONE		0x80000000
++#define WL_NAN_GET_PROTO_INIT_STATUS(x) \
++		(((x) >> 31) & 1)
++#define WL_NAN_CLEAR_PROTO_INIT_STATUS(x) \
++		((x) &= ~WL_NAN_PROTO_INIT_DONE)
++#define WL_NAN_SET_PROTO_INIT_STATUS(x) \
++		((x) |= (1 << 31))
++
++#define WL_NAN_IOCTL_VERSION			0x2
++/* < some sufficient ioc buff size for our module */
++#define WL_NAN_IOC_BUFSZ			256
++/* some sufficient ioc buff size for dump commands */
++#define WL_NAN_IOC_BUFSZ_EXT			1024
++#define WL_NAN_MAX_SIDS_IN_BEACONS		127 /* Max allowed SIDs */
++#define WL_NAN_MASTER_RANK_LEN			8
++#define WL_NAN_RANGE_LIMITED			0x0040 /* Publish/Subscribe flags */
++
++/** The service hash (service id) is exactly this many bytes. */
++#define WL_NAN_SVC_HASH_LEN			6
++#define WL_NAN_HASHES_PER_BLOOM			4 /** Number of hash functions per bloom filter */
++
++/* no. of max last disc results */
++#define WL_NAN_MAX_DISC_RESULTS			3
++
++/* Max len of Rx and Tx filters */
++#define WL_NAN_MAX_SVC_MATCH_FILTER_LEN	255
++
++/* Max service name len */
++#define WL_NAN_MAX_SVC_NAME_LEN	32
++
++/* Type of Data path connection */
++#define WL_NAN_DP_TYPE_UNICAST			0
++#define WL_NAN_DP_TYPE_MULTICAST		1
++
++/* MAX security params length PMK field */
++#define WL_NAN_NCS_SK_PMK_LEN 32
++
++/* Post disc attr ID type */
++typedef uint8 wl_nan_post_disc_attr_id_t;
++
++/*
++ * Component IDs
++ */
++typedef enum {
++	WL_NAN_COMPID_CONFIG = 1,
++	WL_NAN_COMPID_ELECTION = 2,
++	WL_NAN_COMPID_SD = 3,
++	WL_NAN_COMPID_TIMESYNC = 4,
++	WL_NAN_COMPID_DATA_PATH = 5,
++	WL_NAN_COMPID_DEBUG = 15 /* Keep this at the end */
++} wl_nan_comp_id_t;
++
++#define WL_NAN_COMP_SHIFT	8
++#define WL_NAN_COMP_MASK(_c)	(0x0F & ((uint8)(_c)))
++#define WL_NAN_COMP_ID(_c)	(WL_NAN_COMP_MASK(_c) << WL_NAN_COMP_SHIFT)
++
++/* NAN Events */
++
++/** Instance ID type (unique identifier) */
++typedef uint8 wl_nan_instance_id_t;
++
++/* Publish sent for a subscribe */
++/* WL_NAN_EVENT_REPLIED */
++
++typedef struct wl_nan_ev_replied {
++	struct ether_addr	sub_mac; /* Subscriber MAC */
++	wl_nan_instance_id_t	pub_id; /* Publisher Instance ID */
++	uint8			sub_id; /* Subscriber ID */
++	int8			sub_rssi; /* Subscriber RSSI */
++	uint8			pad[3];
++} wl_nan_ev_replied_t;
++
++typedef struct wl_nan_event_replied {
++	struct ether_addr	sub_mac; /* Subscriber MAC */
++	wl_nan_instance_id_t	pub_id; /* Publisher Instance ID */
++	uint8			sub_id; /* Subscriber ID */
++	int8			sub_rssi; /* Subscriber RSSI */
++	uint8		attr_num;
++	uint16		attr_list_len;  /* sizeof attributes attached to payload */
++	uint8		attr_list[0];   /* attributes payload */
++} wl_nan_event_replied_t;
++
++/* Subscribe or Publish instance Terminated */
++
++/* WL_NAN_EVENT_TERMINATED */
++
++#define	NAN_SD_TERM_REASON_TIMEOUT	1
++#define	NAN_SD_TERM_REASON_HOSTREQ	2
++#define	NAN_SD_TERM_REASON_FWTERM	3
++#define	NAN_SD_TERM_REASON_FAIL		4
++
++typedef struct wl_nan_ev_terminated {
++	uint8 instance_id;	/* publish / subscribe instance id */
++	uint8 reason;		/* 1=timeout, 2=Host/IOVAR, 3=FW Terminated 4=Failure */
++	uint8 svctype;		/* 0 - Publish, 0x1 - Subscribe */
++	uint8 pad;		/* Align */
++} wl_nan_ev_terminated_t;
++
++/* Follow up received against a pub / subscr */
++/* WL_NAN_EVENT_RECEIVE */
++
++typedef struct wl_nan_ev_receive {
++	struct ether_addr remote_addr;	/* Peer NAN device MAC */
++	uint8	local_id;		/* Local subscribe or publish ID */
++	uint8	remote_id;		/* Remote subscribe or publish ID */
++	int8	fup_rssi;
++	uint8	attr_num;
++	uint16	attr_list_len;  /* sizeof attributes attached to payload */
++	uint8	attr_list[0];   /* attributes payload */
++} wl_nan_ev_receive_t;
++
++/*
++ * TLVs - Below XTLV definitions will be deprecated
++ * in due course (soon as all other branches update
++ * to the comp ID based XTLVs listed below).
++ */
++enum wl_nan_cmd_xtlv_id {
++	WL_NAN_XTLV_MAC_ADDR = 0x120,
++	WL_NAN_XTLV_MATCH_RX = 0x121,
++	WL_NAN_XTLV_MATCH_TX = 0x122,
++	WL_NAN_XTLV_SVC_INFO = 0x123,
++	WL_NAN_XTLV_SVC_NAME = 0x124,
++	WL_NAN_XTLV_SR_FILTER = 0x125,
++	WL_NAN_XTLV_FOLLOWUP = 0x126,
++	WL_NAN_XTLV_SVC_LIFE_COUNT = 0x127,
++	WL_NAN_XTLV_AVAIL = 0x128,
++	WL_NAN_XTLV_SDF_RX = 0x129,
++	WL_NAN_XTLV_SDE_CONTROL = 0x12a,
++	WL_NAN_XTLV_SDE_RANGE_LIMIT = 0x12b,
++	WL_NAN_XTLV_NAN_AF = 0x12c,
++	WL_NAN_XTLV_SD_TERMINATE = 0x12d,
++	WL_NAN_XTLV_CLUSTER_ID = 0x12e,
++	WL_NAN_XTLV_PEER_RSSI = 0x12f,
++	WL_NAN_XTLV_BCN_RX = 0x130,
++	WL_NAN_XTLV_REPLIED = 0x131, /* Publish sent for a subscribe */
++	WL_NAN_XTLV_RECEIVED = 0x132, /* FUP Received */
++	WL_NAN_XTLV_DISC_RESULTS = 0x133 /* Discovery results */
++};
++
++#define WL_NAN_CMD_GLOBAL		0x00
++#define WL_NAN_CMD_CFG_COMP_ID		0x01
++#define WL_NAN_CMD_ELECTION_COMP_ID	0x02
++#define WL_NAN_CMD_SD_COMP_ID		0x03
++#define WL_NAN_CMD_SYNC_COMP_ID		0x04
++#define WL_NAN_CMD_DATA_COMP_ID		0x05
++#define WL_NAN_CMD_DAM_COMP_ID		0x06
++#define WL_NAN_CMD_RANGE_COMP_ID	0x07
++#define WL_NAN_CMD_DBG_COMP_ID		0x0f
++
++#define WL_NAN_CMD_COMP_SHIFT		8
++#define NAN_CMD(x, y)  (((x) << WL_NAN_CMD_COMP_SHIFT) | (y))
++
++/*
++ * Module based NAN TLV IDs
++ */
++typedef enum wl_nan_tlv {
++
++	WL_NAN_XTLV_CFG_MATCH_RX	= NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x01),
++	WL_NAN_XTLV_CFG_MATCH_TX	= NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x02),
++	WL_NAN_XTLV_CFG_SR_FILTER	= NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x03),
++	WL_NAN_XTLV_CFG_SVC_NAME	= NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x04),
++	WL_NAN_XTLV_CFG_NAN_STATUS	= NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x05),
++	WL_NAN_XTLV_CFG_SVC_LIFE_COUNT	= NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x06),
++	WL_NAN_XTLV_CFG_SVC_HASH	= NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x07),
++	WL_NAN_XTLV_CFG_SEC_CSID	= NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x08), /* Security CSID */
++	WL_NAN_XTLV_CFG_SEC_PMK		= NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x09), /* Security PMK */
++	WL_NAN_XTLV_CFG_SEC_PMKID	= NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x0A),
++
++	WL_NAN_XTLV_SD_SVC_INFO		= NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x01),
++	WL_NAN_XTLV_SD_FOLLOWUP		= NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x02),
++	WL_NAN_XTLV_SD_SDF_RX		= NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x03),
++	WL_NAN_XTLV_SD_SDE_CONTROL	= NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x04),
++	WL_NAN_XTLV_SD_SDE_RANGE_LIMIT	= NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x05),
++	WL_NAN_XTLV_SD_NAN_AF		= NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x06),
++	WL_NAN_XTLV_SD_TERM		= NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x07),
++	WL_NAN_XTLV_SD_REPLIED		= NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x08), /* Pub sent */
++	WL_NAN_XTLV_SD_FUP_RECEIVED	= NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x09), /* FUP Received */
++	WL_NAN_XTLV_SD_DISC_RESULTS	= NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x0A), /* Pub RX */
++
++	WL_NAN_XTLV_SYNC_BCN_RX		= NAN_CMD(WL_NAN_CMD_SYNC_COMP_ID, 0x01),
++
++	WL_NAN_XTLV_DATA_DP_END		= NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x01),
++	WL_NAN_XTLV_DATA_DP_INFO	= NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x02),
++	WL_NAN_XTLV_DATA_DP_SEC_INST	= NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x03),
++
++	WL_NAN_XTLV_RANGE_INFO		= NAN_CMD(WL_NAN_CMD_RANGE_COMP_ID, 0x01)
++} wl_nan_tlv_t;
++
++enum wl_nan_sub_cmd_xtlv_id {
++
++	/* Special command - Tag zero */
++	WL_NAN_CMD_GLB_NAN_VER = NAN_CMD(WL_NAN_CMD_GLOBAL, 0x00),
++
++	 /* nan cfg sub-commands */
++
++	WL_NAN_CMD_CFG_NAN_INIT = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x01),
++	WL_NAN_CMD_CFG_ROLE = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x02),
++	WL_NAN_CMD_CFG_HOP_CNT = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x03),
++	WL_NAN_CMD_CFG_HOP_LIMIT = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x04),
++	WL_NAN_CMD_CFG_WARMUP_TIME = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x05),
++	WL_NAN_CMD_CFG_STATUS = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x06),
++	WL_NAN_CMD_CFG_OUI = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x07),
++	WL_NAN_CMD_CFG_COUNT = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x08),
++	WL_NAN_CMD_CFG_CLEARCOUNT = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x09),
++	WL_NAN_CMD_CFG_CHANNEL = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x0A),
++	WL_NAN_CMD_CFG_BAND = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x0B),
++	WL_NAN_CMD_CFG_CID = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x0C),
++	WL_NAN_CMD_CFG_IF_ADDR = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x0D),
++	WL_NAN_CMD_CFG_BCN_INTERVAL = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x0E),
++	WL_NAN_CMD_CFG_SDF_TXTIME = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x0F),
++	WL_NAN_CMD_CFG_SID_BEACON = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x10),
++	WL_NAN_CMD_CFG_DW_LEN = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x11),
++	WL_NAN_CMD_CFG_AVAIL = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x12),
++	WL_NAN_CMD_CFG_WFA_TM = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x13),
++	WL_NAN_CMD_CFG_EVENT_MASK =  NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x14),
++	WL_NAN_CMD_CFG_NAN_CONFIG = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x15),
++	WL_NAN_CMD_CFG_NAN_ENAB = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x16),
++	WL_NAN_CMD_CFG_ULW = NAN_CMD(WL_NAN_CMD_CFG_COMP_ID, 0x17),
++	WL_NAN_CMD_CFG_MAX = WL_NAN_CMD_CFG_NAN_ENAB,
++	/* Add new commands before and update */
++
++	/* nan election sub-commands */
++	WL_NAN_CMD_ELECTION_JOIN = NAN_CMD(WL_NAN_CMD_ELECTION_COMP_ID, 0x04), /* Deprecated */
++	WL_NAN_CMD_ELECTION_STOP = NAN_CMD(WL_NAN_CMD_ELECTION_COMP_ID, 0x07), /* Deprecate */
++
++	WL_NAN_CMD_ELECTION_HOST_ENABLE = NAN_CMD(WL_NAN_CMD_ELECTION_COMP_ID, 0x01),
++	WL_NAN_CMD_ELECTION_METRICS_CONFIG = NAN_CMD(WL_NAN_CMD_ELECTION_COMP_ID, 0x02),
++	WL_NAN_CMD_ELECTION_METRICS_STATE = NAN_CMD(WL_NAN_CMD_ELECTION_COMP_ID, 0x03),
++	WL_NAN_CMD_ELECTION_LEAVE = NAN_CMD(WL_NAN_CMD_ELECTION_COMP_ID, 0x03),
++	WL_NAN_CMD_ELECTION_MERGE = NAN_CMD(WL_NAN_CMD_ELECTION_COMP_ID, 0x04),
++	WL_NAN_CMD_ELECTION_ADVERTISERS = NAN_CMD(WL_NAN_CMD_ELECTION_COMP_ID, 0x05),
++	WL_NAN_CMD_ELECTION_RSSI_THRESHOLD = NAN_CMD(WL_NAN_CMD_ELECTION_COMP_ID, 0x06),
++	WL_NAN_CMD_ELECTION_MAX = WL_NAN_CMD_ELECTION_RSSI_THRESHOLD,
++	/* New commands go before and update */
++
++	/* nan SD sub-commands */
++	WL_NAN_CMD_SD_PARAMS = NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x01),
++	WL_NAN_CMD_SD_PUBLISH = NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x02),
++	WL_NAN_CMD_SD_PUBLISH_LIST = NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x03),
++	WL_NAN_CMD_SD_CANCEL_PUBLISH = NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x04),
++	WL_NAN_CMD_SD_SUBSCRIBE = NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x05),
++	WL_NAN_CMD_SD_SUBSCRIBE_LIST = NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x06),
++	WL_NAN_CMD_SD_CANCEL_SUBSCRIBE = NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x07),
++	WL_NAN_CMD_SD_VND_INFO = NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x08),
++	WL_NAN_CMD_SD_STATS = NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x09),
++	WL_NAN_CMD_SD_TRANSMIT = NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x0A),
++	WL_NAN_CMD_SD_FUP_TRANSMIT = NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x0B),
++	WL_NAN_CMD_SD_CONNECTION = NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x0C),
++	WL_NAN_CMD_SD_SHOW = NAN_CMD(WL_NAN_CMD_SD_COMP_ID, 0x0D),
++	WL_NAN_CMD_SD_MAX = WL_NAN_CMD_SD_SHOW,
++
++	/* nan time sync sub-commands */
++
++	WL_NAN_CMD_SYNC_SOCIAL_CHAN = NAN_CMD(WL_NAN_CMD_SYNC_COMP_ID, 0x01),
++	WL_NAN_CMD_SYNC_AWAKE_DWS = NAN_CMD(WL_NAN_CMD_SYNC_COMP_ID, 0x02),
++	WL_NAN_CMD_SYNC_BCN_RSSI_NOTIF_THRESHOLD = NAN_CMD(WL_NAN_CMD_SYNC_COMP_ID, 0x03),
++	WL_NAN_CMD_SYNC_MAX = WL_NAN_CMD_SYNC_BCN_RSSI_NOTIF_THRESHOLD,
++
++	/* nan2 commands */
++	WL_NAN_CMD_DATA_CONFIG = NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x01),
++	WL_NAN_CMD_DATA_RSVD02 = NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x02),
++	WL_NAN_CMD_DATA_RSVD03 = NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x03),
++	WL_NAN_CMD_DATA_DATAREQ = NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x04),
++	WL_NAN_CMD_DATA_DATARESP = NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x05),
++	WL_NAN_CMD_DATA_DATAEND = NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x06),
++	WL_NAN_CMD_DATA_SCHEDUPD = NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x07),
++	WL_NAN_CMD_DATA_RSVD08 = NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x08),
++	WL_NAN_CMD_DATA_CAP = NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x9),
++	WL_NAN_CMD_DATA_STATUS = NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x0A),
++	WL_NAN_CMD_DATA_STATS = NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x0B),
++	WL_NAN_CMD_DATA_RSVD0C = NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x0C),
++	WL_NAN_CMD_DATA_NDP_SHOW = NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x0D),
++	WL_NAN_CMD_DATA_DATACONF = NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x0E),
++	WL_NAN_CMD_DATA_MIN_TX_RATE = NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x0F),
++	WL_NAN_CMD_DATA_MAX_PEERS = NAN_CMD(WL_NAN_CMD_DATA_COMP_ID, 0x10),
++	WL_NAN_CMD_DATA_PATH_MAX = WL_NAN_CMD_DATA_MAX_PEERS, /* New ones before and update */
++
++	/* nan dam sub-commands */
++	WL_NAN_CMD_DAM_CFG = NAN_CMD(WL_NAN_CMD_DAM_COMP_ID, 0x01),
++	WL_NAN_CMD_DAM_MAX = WL_NAN_CMD_DAM_CFG,  /* New ones before and update */
++
++	/* nan2.0 ranging commands */
++	WL_NAN_CMD_RANGE_REQUEST = NAN_CMD(WL_NAN_CMD_RANGE_COMP_ID, 0x01),
++	WL_NAN_CMD_RANGE_AUTO = NAN_CMD(WL_NAN_CMD_RANGE_COMP_ID, 0x02),
++	WL_NAN_CMD_RANGE_RESPONSE = NAN_CMD(WL_NAN_CMD_RANGE_COMP_ID, 0x03),
++	WL_NAN_CMD_RANGE_CANCEL = NAN_CMD(WL_NAN_CMD_RANGE_COMP_ID, 0x04),
++
++	/*  nan debug sub-commands  */
++	WL_NAN_CMD_DBG_SCAN_PARAMS = NAN_CMD(WL_NAN_CMD_DBG_COMP_ID, 0x01),
++	WL_NAN_CMD_DBG_SCAN = NAN_CMD(WL_NAN_CMD_DBG_COMP_ID, 0x02),
++	WL_NAN_CMD_DBG_SCAN_RESULTS =  NAN_CMD(WL_NAN_CMD_DBG_COMP_ID, 0x03),
++	/* This is now moved under CFG */
++	WL_NAN_CMD_DBG_EVENT_MASK =  NAN_CMD(WL_NAN_CMD_DBG_COMP_ID, 0x04),
++	WL_NAN_CMD_DBG_EVENT_CHECK =  NAN_CMD(WL_NAN_CMD_DBG_COMP_ID, 0x05),
++	WL_NAN_CMD_DBG_DUMP =  NAN_CMD(WL_NAN_CMD_DBG_COMP_ID, 0x06),
++	WL_NAN_CMD_DBG_CLEAR =  NAN_CMD(WL_NAN_CMD_DBG_COMP_ID, 0x07),
++	WL_NAN_CMD_DBG_RSSI =  NAN_CMD(WL_NAN_CMD_DBG_COMP_ID, 0x08),
++	WL_NAN_CMD_DBG_DEBUG =  NAN_CMD(WL_NAN_CMD_DBG_COMP_ID, 0x09),
++	WL_NAN_CMD_DBG_TEST1 =  NAN_CMD(WL_NAN_CMD_DBG_COMP_ID, 0x0A),
++	WL_NAN_CMD_DBG_TEST2 =  NAN_CMD(WL_NAN_CMD_DBG_COMP_ID, 0x0B),
++	WL_NAN_CMD_DBG_TEST3 =  NAN_CMD(WL_NAN_CMD_DBG_COMP_ID, 0x0C),
++	WL_NAN_CMD_DBG_DISC_RESULTS =  NAN_CMD(WL_NAN_CMD_DBG_COMP_ID, 0x0D),
++	WL_NAN_CMD_DBG_STATS =  NAN_CMD(WL_NAN_CMD_DBG_COMP_ID, 0x0E),
++	WL_NAN_CMD_DBG_LEVEL =  NAN_CMD(WL_NAN_CMD_DBG_COMP_ID, 0x0F),
++	WL_NAN_CMD_DBG_MAX = WL_NAN_CMD_DBG_LEVEL /* New ones before and update */
++};
++
++/** status - TBD BCME_ vs NAN status - range reserved for BCME_ */
++enum {
++	/* add new status here... */
++	WL_NAN_E_SEC_SA_NOTFOUND	= -2076,
++	WL_NAN_E_BSSCFG_NOTFOUND	= -2075,
++	WL_NAN_E_SCB_NOTFOUND		= -2074,
++	WL_NAN_E_NCS_SK_KDESC_TYPE      = -2073,
++	WL_NAN_E_NCS_SK_KEY_DESC_VER    = -2072,	/* key descr ver */
++	WL_NAN_E_NCS_SK_KEY_TYPE        = -2071,	/* key descr type */
++	WL_NAN_E_NCS_SK_KEYINFO_FAIL    = -2070,	/* key info (generic) */
++	WL_NAN_E_NCS_SK_KEY_LEN         = -2069,	/* key len */
++	WL_NAN_E_NCS_SK_KDESC_NOT_FOUND = -2068,	/* key desc not found */
++	WL_NAN_E_NCS_SK_INVALID_PARAMS  = -2067,	/* invalid args */
++	WL_NAN_E_NCS_SK_KDESC_INVALID   = -2066,	/* key descr is not valid */
++	WL_NAN_E_NCS_SK_NONCE_MISMATCH  = -2065,
++	WL_NAN_E_NCS_SK_KDATA_SAVE_FAIL = -2064,	/* not able to save key data */
++	WL_NAN_E_NCS_SK_AUTH_TOKEN_CALC_FAIL = -2063,
++	WL_NAN_E_NCS_SK_PTK_CALC_FAIL   = -2062,
++	WL_NAN_E_INVALID_STARTOFFSET	= -2061,
++	WL_NAN_E_BAD_NA_ENTRY_TYPE	= -2060,
++	WL_NAN_E_INVALID_CHANBMP	= -2059,
++	WL_NAN_E_INVALID_OP_CLASS	= -2058,
++	WL_NAN_E_NO_IES			= -2057,
++	WL_NAN_E_NO_PEER_ENTRY_AVAIL	= -2056,
++	WL_NAN_E_INVALID_PEER		= -2055,
++	WL_NAN_E_PEER_EXISTS		= -2054,
++	WL_NAN_E_PEER_NOTFOUND		= -2053,
++	WL_NAN_E_NO_MEM			= -2052,
++	WL_NAN_E_INVALID_OPTION		= -2051,
++	WL_NAN_E_INVALID_BAND		= -2050,
++	WL_NAN_E_INVALID_MAC		= -2049,
++	WL_NAN_E_BAD_INSTANCE		= -2048,
++	WL_NAN_E_NDC_EXISTS		= -2047,
++	WL_NAN_E_NO_NDC_ENTRY_AVAIL	= -2046,
++	WL_NAN_E_INVALID_NDC_ENTRY      = -2045,
++	WL_NAN_E_ERROR			= -1,
++	WL_NAN_E_OK			= 0
++};
++
++typedef int32 wl_nan_status_t;
++
++/** nan cmd list entry  */
++enum wl_nan_sub_cmd_input_flags {
++	WL_NAN_SUB_CMD_FLAG_NONE = 0,
++	WL_NAN_SUB_CMD_FLAG_SKIP = 1, /* Skip to next sub-command on error */
++	WL_NAN_SUB_CMD_FLAG_TERMINATE = 2, /* Terminate processing and return */
++	WL_NAN_SUB_CMD_FLAG_LAST /* Keep this at the end */
++};
++
++/** container for nan events */
++typedef struct wl_nan_ioc {
++	uint16	version;	/**< interface command or event version */
++	uint16	id;			/**< nan ioctl cmd  ID  */
++	uint16	len;		/**< total length of all tlv records in data[]  */
++	uint16	pad;		/**< pad to be 32 bit aligment */
++	uint8	data [];	/**< var len payload of bcm_xtlv_t type */
++} wl_nan_ioc_t;
++
++/*
++ * NAN sub-command data structures
++ */
++
++/*
++ * Config component WL_NAN_CMD_CFG_XXXX sub-commands
++ * WL_NAN_CMD_CFG_ENABLE
++ */
++enum wl_nan_config_state {
++	WL_NAN_CONFIG_STATE_DISABLE = 0,
++	WL_NAN_CONFIG_STATE_ENABLE = 1
++};
++
++typedef int8 wl_nan_config_state_t;
++
++/* WL_NAN_CMD_CFG_NAN_INIT */
++
++typedef uint8 wl_nan_init_t;
++
++/* WL_NAN_CMD_CFG_NAN_VERSION */
++typedef uint16 wl_nan_ver_t;
++
++/* WL_NAN_CMD_CFG_NAN_CONFIG  */
++typedef uint32 wl_nan_cfg_ctrl_t;
++
++/*
++ * WL_NAN_CMD_CFG_BAND, WL_NAN_CMD_CFG_RSSI_THRESHOLD(Get only)
++ */
++typedef uint8 wl_nan_band_t;
++
++/*
++ * WL_NAN_CMD_CFG_ROLE
++ */
++enum wl_nan_role {
++	WL_NAN_ROLE_AUTO = 0,
++	WL_NAN_ROLE_NON_MASTER_NON_SYNC = 1,
++	WL_NAN_ROLE_NON_MASTER_SYNC = 2,
++	WL_NAN_ROLE_MASTER = 3,
++	WL_NAN_ROLE_ANCHOR_MASTER = 4
++};
++
++typedef uint8 wl_nan_role_t;
++
++typedef struct wl_nan_device_state
++{
++	wl_nan_role_t role;		/* Sync Master, Non-Sync Master */
++	uint8 state;	/* TBD  */
++	uint8 hopcount;	/* Hops to the Anchor Master */
++	struct ether_addr immediate_master; /* Master MAC */
++	struct ether_addr anchor_master;	/* Anchor Master MAC */
++	struct ether_addr cluster_id; /* Cluster ID to which this device belongs to */
++	uint8 PAD[3];
++	uint32 tsf_high;  /* NAN Cluster TSFs */
++	uint32 tsf_low;
++} wl_nan_device_state_t;
++
++/*
++ * WL_NAN_CMD_CFG_HOP_CNT, WL_NAN_CMD_CFG_HOP_LIMIT
++ */
++typedef uint8 wl_nan_hop_count_t;
++
++/*
++ * WL_NAN_CMD_CFG_WARMUP_TIME
++ */
++typedef uint32 wl_nan_warmup_time_ticks_t;
++
++/*
++ * WL_NAN_CMD_CFG_RSSI_THRESHOLD
++ * rssi_close and rssi_mid are used to transition master to non-master
++ * role by NAN state machine. rssi thresholds corresponding to the band
++ * will be updated.
++ */
++/* To be deprecated */
++typedef struct wl_nan_rssi_threshold {
++	wl_nan_band_t band;
++	int8 rssi_close;
++	int8 rssi_mid;
++	uint8 pad;
++} wl_nan_rssi_threshold_t;
++
++/* WL_NAN_CMD_ELECTION_RSSI_THRESHOLD */
++
++typedef struct wl_nan_rssi_thld {
++	int8 rssi_close_2g;
++	int8 rssi_mid_2g;
++	int8 rssi_close_5g;
++	int8 rssi_mid_5g;
++} wl_nan_rssi_thld_t;
++
++/* WL_NAN_CMD_DATA_MAX_PEERS */
++
++typedef uint8 wl_nan_max_peers_t;
++
++#define NAN_MAX_BANDS 2
++/*
++ * WL_NAN_CMD_CFG_STATUS
++ */
++/* Deprecated - Begin */
++typedef struct wl_nan_cfg_status {
++	uint8 enabled;
++	uint8 inited;
++	uint8 joined;
++	uint8 merged;
++	uint8 role;
++	uint8 PAD[3];
++	uint32 chspec[2];
++	uint8 mr[8];                    /**< Master Rank */
++	uint8 amr[8];			/**< Anchor Master Rank */
++	uint32 cnt_pend_txfrm;		/**< pending TX frames */
++	uint32 cnt_bcn_tx;		/**< TX disc/sync beacon count */
++	uint32 cnt_bcn_rx;		/**< RX disc/sync beacon count */
++	uint32 cnt_svc_disc_tx;		/**< TX svc disc frame count */
++	uint32 cnt_svc_disc_rx;		/**< RX svc disc frame count */
++	uint32 ambtt;                   /**< Anchor master beacon target time */
++	struct ether_addr cid;          /**< Cluster id */
++	uint8 hop_count;                /**< Hop count */
++	uint8 PAD;
++} wl_nan_cfg_status_t;
++
++typedef struct wl_nan_config_status {
++	struct ether_addr	def_cid;	/* Default Cluster id */
++	uint8			inited;		/* NAN Initialized successfully */
++	uint8			enabled;	/* NAN Enabled */
++	struct ether_addr	cur_cid;	/* Default Cluster id */
++	uint8			joined;		/* Joined or started own cluster */
++	uint8			role;		/* Master, Non Master, NM Sync & Non-Sync */
++	chanspec_t		chspec[NAN_MAX_BANDS]; /* Channel Spec 2.4G followed by 5G */
++	uint8			mr[WL_NAN_MASTER_RANK_LEN]; /* Master Rank */
++	uint8			amr[WL_NAN_MASTER_RANK_LEN]; /* Anchor Master Rank */
++	uint32			cnt_pend_txfrm;	/* Pending Tx Frames */
++	uint32			cnt_bcn_tx;	/* TX disc/sync beacon count */
++	uint32			cnt_bcn_rx;	/* RX disc/sync beacon count */
++	uint32			cnt_svc_disc_tx; /* TX svc disc frame count */
++	uint32			cnt_svc_disc_rx; /* RX svc disc frame count */
++	uint32			ambtt;	/* Anchor master beacon target time */
++	uint8			hop_count; /* Hop count */
++	uint8			pad[3];	/* Align */
++} wl_nan_config_status_t;
++/* Deprecated - End */
++
++typedef enum wl_nan_election_mode {
++	WL_NAN_ELECTION_RUN_BY_HOST = 1,
++	WL_NAN_ELECTION_RUN_BY_FW = 2
++} wl_nan_election_mode_t;
++
++typedef struct wl_nan_conf_status {
++	struct ether_addr	nmi;		/*  NAN mgmt interface address */
++	uint8			enabled;	/* NAN is enabled */
++	uint8			role;		/* Current nan sync role */
++	struct ether_addr	cid;		/*  Current Cluster id */
++	uint8			social_chans[2];	/* Social channels */
++	uint8			mr[8];		/* Master Rank */
++	uint8			amr[8];		/* Anchor Master Rank */
++	uint32			ambtt;		/* Anchor master beacon target time */
++	uint32			cluster_tsf_h;	/* Current Cluster TSF High */
++	uint32			cluster_tsf_l;	/* Current Cluster TSF Low */
++	uint8			election_mode; /* Election mode, host or firmware */
++	uint8			hop_count;	/* Current Hop count */
++	uint8			pad[2];
++} wl_nan_conf_status_t;
++
++/*
++ * WL_NAN_CMD_CFG_OUI
++ */
++typedef struct wl_nan_oui_type {
++	uint8 nan_oui[DOT11_OUI_LEN];
++	uint8 type;
++} wl_nan_oui_type_t;
++
++/*
++ * WL_NAN_CMD_CFG_COUNT
++ */
++typedef struct wl_nan_count {
++	uint32 cnt_bcn_tx;		/**< TX disc/sync beacon count */
++	uint32 cnt_bcn_rx;		/**< RX disc/sync beacon count */
++	uint32 cnt_svc_disc_tx;		/**< TX svc disc frame count */
++	uint32 cnt_svc_disc_rx;		/**< RX svc disc frame count */
++} wl_nan_count_t;
++/*
++ * Election component WL_NAN_CMD_ELECTION_XXXX sub-commands
++ * WL_NAN_CMD_ELECTION_HOST_ENABLE
++ */
++enum wl_nan_enable_flags {
++	WL_NAN_DISABLE_FLAG_HOST_ELECTION = 0,
++	WL_NAN_ENABLE_FLAG_HOST_ELECTION = 1
++};
++
++/*
++ * 0 - disable host based election
++ * 1 - enable host based election
++ */
++typedef uint8 wl_nan_host_enable_t;
++
++/*
++ * WL_NAN_CMD_ELECTION_METRICS_CONFIG
++ */
++/* Set only */
++typedef struct wl_nan_election_metric_config {
++	uint8 random_factor; /* Configured random factor */
++	uint8 master_pref;	/* configured master preference */
++	uint8 pad[2];
++} wl_nan_election_metric_config_t;
++
++/*
++ * WL_NAN_CMD_ELECTION_METRICS_STATE
++ */
++/* Get only */
++typedef struct wl_nan_election_metric_state {
++	uint8 random_factor; /* random factor used in MIs */
++	uint8 master_pref;	 /* Master advertised in MIs */
++	uint8 pad[2];
++} wl_nan_election_metric_state_t;
++
++/*
++ * WL_NAN_CMD_ELECTION_LEAVE
++ * WL_NAN_CMD_ELECTION_STOP
++ */
++typedef struct ether_addr wl_nan_cluster_id_t;
++
++/*
++ * WL_NAN_CMD_ELECTION_JOIN
++ */
++typedef struct wl_nan_join {
++	uint8 start_cluster;	/* Start a cluster */
++	uint8 pad[3];
++	wl_nan_cluster_id_t cluster_id;	/* Cluster ID to join */
++} wl_nan_join_t;
++
++/*
++ * WL_NAN_CMD_ELECTION_MERGE
++ * 0 - disable cluster merge
++ * 1 - enable cluster merge
++ */
++typedef uint8 wl_nan_merge_enable_t;
++
++/*
++ * WL_NAN_CMD_CFG_ROLE
++ * role = 0 means configuration by firmware; otherwise by host
++ * when host configures role, also need target master address to sync to
++ */
++#define NAN_SYNC_MASTER_SELF	0
++#define NAN_SYNC_MASTER_AM		1
++#define NAN_SYNC_MASTER_INTERMEDIATE	2
++/* 	ltsf_h, ltsf_l:
++	The local TSF timestamp filled in by FW in the WL_NAN_EVENT_BCN_RX event;
++	rtsf_h, rtsf_l:
++	The timestamp in the Rx beacon frame, filled in by host
++	uint32 ambtt:
++	the amtt in the cluster ID attribute in the Rx beacon frame
++*/
++typedef struct nan_sync_master {
++	uint8 flag;	/* 0: self, 1: anchor-master, 2: intermediate master */
++	uint8  hop_count;
++	struct ether_addr addr;
++	struct ether_addr cluster_id;
++	chanspec_t channel; /* bcn reception channel */
++	uint32 ltsf_h;
++	uint32 ltsf_l;
++	uint32 rtsf_h;
++	uint32 rtsf_l;
++	uint8 amr[WL_NAN_MASTER_RANK_LEN];
++	uint32 ambtt;
++} nan_sync_master_t;
++
++/* NAN advertiser structure */
++/* TODO RSDB: add chspec to indicates core corresponds correct core */
++typedef struct nan_adv_entry {
++	uint8 age;	/* used to remove stale entries */
++	uint8 hop_count;
++	struct ether_addr addr;
++	struct ether_addr cluster_id;
++	chanspec_t channel; /* bcn reception channel */
++	uint32 ltsf_h;
++	uint32 ltsf_l;
++	uint32 rtsf_h;
++	uint32 rtsf_l;
++	uint8 amr[WL_NAN_MASTER_RANK_LEN];
++	uint32 ambtt;
++	int8	rssi[NAN_MAX_BANDS];		/* rssi last af was received at */
++	int8	last_rssi[NAN_MAX_BANDS];	/* rssi in the last AF */
++} nan_adv_entry_t;
++
++typedef struct nan_adv_table {
++	uint8  num_adv;
++	uint8	adv_size;
++	uint8	pad[2];
++	nan_adv_entry_t adv_nodes[0];
++} nan_adv_table_t;
++
++typedef struct wl_nan_role_cfg {
++	wl_nan_role_t cfg_role;
++	wl_nan_role_t cur_role;
++	uint8 pad[2];
++	nan_sync_master_t target_master;
++} wl_nan_role_cfg_t;
++
++typedef struct wl_nan_role_config {
++	wl_nan_role_t role;
++	struct ether_addr target_master;
++	uint8 pad;
++} wl_nan_role_config_t;
++
++typedef int8 wl_nan_sd_optional_field_types_t;
++
++/* Flag bits for Publish and Subscribe (wl_nan_sd_params_t flags) */
++
++#define WL_NAN_RANGE_LIMITED		0x0040
++
++/* Event generation indicator (default is continuous) */
++
++#define WL_NAN_MATCH_ONCE		0x100000
++#define WL_NAN_MATCH_NEVER		0x200000
++
++/* Bits specific to Publish */
++
++#define WL_NAN_PUB_UNSOLICIT	0x1000	/* Unsolicited Tx */
++#define WL_NAN_PUB_SOLICIT		0x2000	/* Solicited Tx */
++#define WL_NAN_PUB_BOTH			0x3000	/* Both the above */
++
++#define WL_NAN_PUB_BCAST		0x4000	/* bcast solicited Tx only */
++#define WL_NAN_PUB_EVENT		0x8000	/* Event on each solicited Tx */
++#define WL_NAN_PUB_SOLICIT_PENDING	0x10000 /* Used for one-time solicited Publish */
++
++#define WL_NAN_FOLLOWUP			0x20000 /* Follow-up frames */
++
++/* Bits specific to Subscribe */
++
++#define WL_NAN_SUB_ACTIVE		0x1000 /* Active subscribe mode */
++#define WL_NAN_SUB_MATCH_IF_SVC_INFO	0x2000 /* Service info in publish */
++
++#define WL_NAN_TTL_UNTIL_CANCEL	0xFFFFFFFF /* Special values for time to live (ttl) parameter */
++
++/*
++ * Publish -  runs until first transmission
++ * Subscribe - runs until first  DiscoveryResult event
++ */
++#define WL_NAN_TTL_FIRST	0
++
++/*
++ * WL_NAN_CMD_SD_PARAMS
++ */
++typedef struct wl_nan_sd_params
++{
++	uint16	length; /* length including options */
++	uint8	period; /* period of the unsolicited SDF xmission in DWs */
++	uint8   pad;
++	uint8	svc_hash[WL_NAN_SVC_HASH_LEN]; /* Hash for the service name */
++	uint8	instance_id; /* Instance of the current service */
++	int8	proximity_rssi; /* RSSI limit to Rx subscribe or pub SDF 0 no effect */
++	uint32	flags; /* bitmap representing aforesaid optional flags */
++	int32	ttl; /* TTL for this instance id, -1 will run till cancelled */
++	tlv_t	optional[1]; /* optional fields in the SDF  as appropriate */
++} wl_nan_sd_params_t;
++
++/*
++ * WL_NAN_CMD_SD_PUBLISH_LIST
++ * WL_NAN_CMD_SD_SUBSCRIBE_LIST
++ */
++typedef struct wl_nan_service_info
++{
++	uint8 instance_id;	/* Publish instance ID */
++	uint8 service_hash[WL_NAN_SVC_HASH_LEN]; /* Hash for service name */
++} wl_nan_service_info_t;
++
++typedef struct wl_nan_service_list
++{
++	uint16 id_count; /* Number of registered publish/subscribe services */
++	wl_nan_service_info_t list[1]; /* service info defined by nan_service instance */
++} wl_nan_service_list_t;
++
++/*
++ * WL_NAN_CMD_CFG_BCN_INTERVAL
++ */
++typedef uint16 wl_nan_disc_bcn_interval_t;
++
++/*
++ * WL_NAN_CMD_CFG_SDF_TXTIME
++ */
++typedef uint16 wl_nan_svc_disc_txtime_t;
++
++/*
++ * WL_NAN_CMD_CFG_STOP_BCN_TX
++ */
++typedef uint16 wl_nan_stop_bcn_tx_t;
++
++/*
++ * WL_NAN_CMD_CFG_SID_BEACON
++ */
++typedef struct wl_nan_sid_beacon_control {
++	uint8 sid_enable;	/* Flag to indicate the inclusion of Service IDs in Beacons */
++	uint8 sid_count;	/* Limit for number of SIDs to be included in Beacons */
++	uint8 pad[2];
++} wl_nan_sid_beacon_control_t;
++
++/*
++ * WL_NAN_CMD_CFG_DW_LEN
++ */
++typedef uint16 wl_nan_dw_len_t;
++
++/*
++ * WL_NAN_CMD_CFG_AWAKE_DW   Will be deprecated.
++ */
++typedef struct wl_nan_awake_dw {
++	wl_nan_band_t band;	/* 0 - b mode 1- a mode */
++	uint8 interval;		/* 1 or 2 or 4 or 8 or 16 */
++	uint16 pad;
++} wl_nan_awake_dw_t;
++
++/*
++ * WL_NAN_CMD_CFG_AWAKE_DWS
++ */
++typedef struct wl_nan_awake_dws {
++	uint8 dw_interval_2g;	/* 2G DW interval */
++	uint8 dw_interval_5g;	/* 5G DW interval */
++	uint16 pad;
++} wl_nan_awake_dws_t;
++
++/* WL_NAN_CMD_SYNC_BCN_RSSI_NOTIF_THRESHOLD */
++
++typedef struct wl_nan_rssi_notif_thld {
++	int8 bcn_rssi_2g;
++	int8 bcn_rssi_5g;
++	int16 pad;
++} wl_nan_rssi_notif_thld_t;
++
++/*
++ * WL_NAN_CMD_CFG_SOCIAL_CHAN
++ */
++typedef struct wl_nan_social_channels {
++	uint8 soc_chan_2g;	/* 2G social channel */
++	uint8 soc_chan_5g;	/* 5G social channel */
++	uint16 pad;
++} wl_nan_social_channels_t;
++
++/*
++ * WL_NAN_CMD_SD_CANCEL_PUBLISH
++ * WL_NAN_CMD_SD_CANCEL_SUBSCRIBE
++ */
++typedef uint8 wl_nan_instance_id; /* Instance ID of an active publish instance */
++
++/*
++ * WL_NAN_CMD_SD_VND_INFO
++ */
++typedef struct wl_nan_sd_vendor_info
++{
++	uint16 length; /* Size in bytes of the payload following this field */
++	uint8 data[];	/* Vendor Information */
++} wl_nan_sd_vendor_info_t;
++
++/*
++ * WL_NAN_CMD_SD_STATS
++ */
++typedef struct wl_nan_sd_stats {
++	uint32  sdftx;
++	uint32  sdfrx;
++	uint32  sdsrffail;
++	uint32  sdrejrssi;
++	uint32  sdfollowuprx;
++	uint32  sdsubmatch;
++	uint32  sdpubreplied;
++	uint32  sdmftfail1;
++	uint32  sdmftfail2;
++	uint32  sdmftfail3;
++	uint32  sdmftfail4;
++}  wl_nan_sd_stats_t;
++
++/*
++ * WL_NAN_CMD_SD_TRANSMIT
++ * WL_NAN_CMD_SD_FUP_TRANSMIT
++ */
++typedef struct wl_nan_sd_transmit {
++	uint8 local_service_id; /* Sender Service ID */
++	uint8 requestor_service_id; /* Destination Service ID */
++	struct ether_addr destination_addr; /* Destination MAC */
++	uint16 token; /* follow_up_token when a follow-up msg is queued successfully */
++	uint8 priority; /* requested relative prio */
++	uint8 service_info_len; /* size in bytes of the service info payload */
++	uint8 service_info[]; /* Service Info payload */
++} wl_nan_sd_transmit_t;
++
++/*
++ * WL_NAN_CMD_SYNC_TSRESERVE
++ */
++/** time slot */
++#define NAN_MAX_TIMESLOT	32
++typedef struct wl_nan_timeslot {
++	uint32	abitmap; /**< available bitmap */
++	uint32 chanlist[NAN_MAX_TIMESLOT];
++} wl_nan_timeslot_t;
++
++/*
++ * Deprecated
++ *
++ * WL_NAN_CMD_SYNC_TSRELEASE
++ */
++typedef uint32 wl_nan_ts_bitmap_t;
++
++/* nan passive scan params */
++#define NAN_SCAN_MAX_CHCNT 8
++typedef struct wl_nan_scan_params {
++	uint16 scan_time;
++	uint16 home_time;
++	uint16 ms_intvl; /**< interval between merge scan */
++	uint16 ms_dur;  /**< duration of merge scan */
++	uint16 chspec_num;
++	uint8 pad[2];
++	chanspec_t chspec_list[NAN_SCAN_MAX_CHCNT]; /**< act. used 3, 5 rfu */
++} wl_nan_scan_params_t;
++
++/*
++ * WL_NAN_CMD_DBG_SCAN
++ */
++typedef struct wl_nan_dbg_scan {
++	struct ether_addr cid;
++	uint8 pad[2];
++} wl_nan_dbg_scan_t;
++
++/* NAN_DBG_LEVEL */
++typedef struct wl_nan_dbg_level {
++	uint32 nan_err_level; /* for Error levels */
++	uint32 nan_dbg_level; /* for bebug logs and trace */
++	uint32 nan_info_level; /* for dumps like prhex */
++} wl_nan_dbg_level_t;
++
++/*
++ * WL_NAN_CMD_DBG_EVENT_MASK
++ */
++typedef uint32 wl_nan_event_mask_t;
++
++/*
++ * WL_NAN_CMD_DBG_EVENT_CHECK
++ */
++typedef uint8 wl_nan_dbg_ifname[BCM_MSG_IFNAME_MAX];
++
++/*
++ * WL_NAN_CMD_DBG_DUMP
++ * WL_NAN_CMD_DBG_CLEAR
++ */
++enum wl_nan_dbg_dump_type {
++	WL_NAN_DBG_DT_RSSI_DATA = 1,
++	WL_NAN_DBG_DT_STATS_DATA = 2,
++	/*
++	 * Additional enums before this line
++	 */
++	WL_NAN_DBG_DT_INVALID
++};
++typedef int8 wl_nan_dbg_dump_type_t;
++
++/** various params and ctl swithce for nan_debug instance  */
++/*
++ * WL_NAN_CMD_DBG_DEBUG
++ */
++typedef struct wl_nan_debug_params {
++	uint16	cmd;	/**< debug cmd to perform a debug action */
++	uint16	status;
++	uint32	msglevel; /**< msg level if enabled */
++	uint8	enabled; /**< runtime debuging enabled */
++	uint8 collect;
++	uint8 PAD[2];
++} wl_nan_debug_params_t;
++
++
++typedef struct wl_nan_sched_svc_timeslot_s {
++	uint32 abitmap; /* availability bitmap */
++	uint32 chanlist[NAN_MAX_TIMESLOT];
++	uint8  res; /* resolution: 0 = 16ms, 1 = 32ms, 2 = 64ms 3 = reserved. REfer NAN spec */
++	uint8  mapid; /* mapid from NAN spec. Used to differentiate 2G Vs 5G band */
++	uint8 PAD[2];
++} wl_nan_sched_svc_timeslot_t;
++
++
++/* nan passive scan params */
++#define NAN_SCAN_MAX_CHCNT 8
++typedef struct nan_scan_params {
++	uint16 scan_time;
++	uint16 home_time;
++	uint16 ms_intvl; /**< interval between merge scan */
++	uint16 ms_dur;  /**< duration of merge scan */
++	uint16 chspec_num;
++	uint8 pad[2];
++	chanspec_t chspec_list[NAN_SCAN_MAX_CHCNT]; /**< act. used 3, 5 rfu */
++} nan_scan_params_t;
++
++/* nan cmd IDs */
++enum wl_nan_cmds {
++	 /* nan cfg /disc & dbg ioctls */
++	WL_NAN_CMD_ENABLE = 1,
++	WL_NAN_CMD_ATTR = 2,
++	WL_NAN_CMD_NAN_JOIN = 3,
++	WL_NAN_CMD_LEAVE = 4,
++	WL_NAN_CMD_MERGE = 5,
++	WL_NAN_CMD_STATUS = 6,
++	WL_NAN_CMD_TSRESERVE = 7,
++	WL_NAN_CMD_TSSCHEDULE = 8,
++	WL_NAN_CMD_TSRELEASE = 9,
++	WL_NAN_CMD_OUI = 10,
++	WL_NAN_CMD_OOB_AF = 11,
++
++	WL_NAN_CMD_COUNT = 15,
++	WL_NAN_CMD_CLEARCOUNT = 16,
++
++	/*  discovery engine commands */
++	WL_NAN_CMD_PUBLISH = 20,
++	WL_NAN_CMD_SUBSCRIBE = 21,
++	WL_NAN_CMD_CANCEL_PUBLISH = 22,
++	WL_NAN_CMD_CANCEL_SUBSCRIBE = 23,
++	WL_NAN_CMD_TRANSMIT = 24,
++	WL_NAN_CMD_CONNECTION = 25,
++	WL_NAN_CMD_SHOW = 26,
++	WL_NAN_CMD_STOP = 27,	/* stop nan for a given cluster ID  */
++	/*  nan debug iovars & cmds  */
++	WL_NAN_CMD_SCAN_PARAMS = 46,
++	WL_NAN_CMD_SCAN = 47,
++	WL_NAN_CMD_SCAN_RESULTS = 48,
++	WL_NAN_CMD_EVENT_MASK = 49,
++	WL_NAN_CMD_EVENT_CHECK = 50,
++	WL_NAN_CMD_DUMP = 51,
++	WL_NAN_CMD_CLEAR = 52,
++	WL_NAN_CMD_RSSI = 53,
++
++	WL_NAN_CMD_DEBUG = 60,
++	WL_NAN_CMD_TEST1 = 61,
++	WL_NAN_CMD_TEST2 = 62,
++	WL_NAN_CMD_TEST3 = 63,
++	WL_NAN_CMD_DISC_RESULTS = 64,
++	/* nan 2.0 data path commands */
++	WL_NAN_CMD_DATAPATH = 65
++};
++
++/*   NAN DP interface commands  */
++enum wl_nan_dp_cmds {
++	/* nan 2.0 ioctls */
++	WL_NAN_CMD_DP_CAP = 1000,
++	WL_NAN_CMD_DP_CONFIG = 1001,
++	WL_NAN_CMD_DP_CREATE = 1002,
++	WL_NAN_CMD_DP_AUTO_CONNECT = 1003,
++	WL_NAN_CMD_DP_DATA_REQ = 1004,
++	WL_NAN_CMD_DP_DATA_RESP = 1005,
++	WL_NAN_CMD_DP_SCHED_UPD = 1006,
++	WL_NAN_CMD_DP_END = 1007,
++	WL_NAN_CMD_DP_CONNECT = 1008,
++	WL_NAN_CMD_DP_STATUS = 1009
++};
++
++/* TODO Should remove this fixed length */
++#define WL_NAN_DATA_SVC_SPEC_INFO_LEN 32 /* arbitrary */
++#define WL_NAN_DP_MAX_SVC_INFO	      0xFF
++#define WL_NAN_DATA_NDP_INST_SUPPORT 16
++
++/* Nan flags */
++#define WL_NAN_DP_FLAG_SVC_INFO	      (1 << 0)
++#define WL_NAN_DP_FLAG_CONFIRM	      (1 << 1)
++#define WL_NAN_DP_FLAG_EXPLICIT_CFM   (1 << 2)
++#define WL_NAN_DP_FLAG_SECURITY	      (1 << 3)
++
++/* NAN Datapath host status */
++#define WL_NAN_DP_STATUS_ACCEPTED     1
++#define WL_NAN_DP_STATUS_REJECTED     0
++
++/* to be done */
++typedef struct wl_nan_dp_cap {
++	uint8 tbd;
++} wl_nan_dp_cap_t;
++
++
++/** The service hash (service id) is exactly this many bytes. */
++#define WL_NAN_SVC_HASH_LEN	6
++/** Number of hash functions per bloom filter */
++#define WL_NAN_HASHES_PER_BLOOM 4
++/* no. of max last disc results */
++#define WL_NAN_MAX_DISC_RESULTS	3
++
++/* NAN security related defines */
++/* NCS-SK related */
++#define WL_NAN_NCS_SK_PMK_LEN	32
++#define WL_NAN_NCS_SK_PMKID_LEN	16
++
++/* recent discovery results */
++typedef struct wl_nan_disc_result_s
++{
++	wl_nan_instance_id_t instance_id;	/* instance id of pub/sub req */
++	wl_nan_instance_id_t peer_instance_id;	/* peer instance id of pub/sub req/resp */
++	uint8 svc_hash[WL_NAN_SVC_HASH_LEN];	/* service descp string */
++	struct ether_addr peer_mac;	/* peer mac address */
++} wl_nan_disc_result_t;
++
++/* list of recent discovery results */
++typedef struct wl_nan_disc_results_s
++{
++	wl_nan_disc_result_t disc_result[WL_NAN_MAX_DISC_RESULTS];
++} wl_nan_disc_results_list_t;
++
++/* nan 1.0 events */
++/* To be deprecated - will be replaced by event_disc_result */
++typedef struct wl_nan_ev_disc_result {
++	wl_nan_instance_id_t pub_id;
++	wl_nan_instance_id_t sub_id;
++	struct ether_addr pub_mac;
++	uint8 opt_tlvs[0];
++} wl_nan_ev_disc_result_t;
++
++typedef struct wl_nan_event_disc_result {
++	wl_nan_instance_id_t pub_id;
++	wl_nan_instance_id_t sub_id;
++	struct ether_addr pub_mac;
++	int8		publish_rssi;		/* publisher RSSI */
++	uint8		attr_num;
++	uint16		attr_list_len;	/* length of the all the attributes in the SDF */
++	uint8		attr_list[0];	/* list of NAN attributes */
++} wl_nan_event_disc_result_t;
++
++typedef struct wl_nan_ev_p2p_avail {
++	struct ether_addr sender;
++	struct ether_addr p2p_dev_addr;
++	uint8 dev_role;
++	uint8 resolution;
++	uint8 repeat;
++	uint8 pad[3];
++	chanspec_t chanspec;
++	uint32 avail_bmap;
++} wl_nan_ev_p2p_avail_t;
++
++/*
++* discovery interface event structures *
++*/
++
++/* mandatory parameters for OOB action frame */
++/* single-shot when bitmap and offset are set to 0; periodic otherwise */
++typedef struct wl_nan_oob_af_params_s
++{
++	/* bitmap for the 32 timeslots in 512TU dw interval */
++	uint32 ts_map;
++	/* offset from start of dw, in us */
++	uint32 tx_offset;
++	struct ether_addr bssid;
++	struct ether_addr dest;
++	uint32 pkt_lifetime;
++	uint16 payload_len;
++	uint8 payload[1];
++} wl_nan_oob_af_params_t;
++
++/* NAN Ranging */
++
++/* Bit defines for global flags */
++#define WL_NAN_RANGING_ENABLE		1 /**< enable RTT */
++#define WL_NAN_RANGING_RANGED		2 /**< Report to host if ranged as target */
++typedef struct nan_ranging_config {
++	uint32 chanspec;		/**< Ranging chanspec */
++	uint16 timeslot;		/**< NAN RTT start time slot  1-511 */
++	uint16 duration;		/**< NAN RTT duration in ms */
++	struct ether_addr allow_mac;	/**< peer initiated ranging: the allowed peer mac
++					 * address, a unicast (for one peer) or
++					 * a broadcast for all. Setting it to all zeros
++					 * means responding to none,same as not setting
++					 * the flag bit NAN_RANGING_RESPOND
++					 */
++	uint16 flags;
++} wl_nan_ranging_config_t;
++
++/** list of peers for self initiated ranging */
++/** Bit defines for per peer flags */
++#define WL_NAN_RANGING_REPORT (1<<0)	/**< Enable reporting range to target */
++typedef struct nan_ranging_peer {
++	uint32 chanspec;		/**< desired chanspec for this peer */
++	uint32 abitmap;			/**< available bitmap */
++	struct ether_addr ea;		/**< peer MAC address */
++	uint8 frmcnt;			/**< frame count */
++	uint8 retrycnt;			/**< retry count */
++	uint16 flags;			/**< per peer flags, report or not */
++	uint16 PAD;
++} wl_nan_ranging_peer_t;
++typedef struct nan_ranging_list {
++	uint8 count;			/**< number of MAC addresses */
++	uint8 num_peers_done;		/**< host set to 0, when read, shows number of peers
++					 * completed, success or fail
++					 */
++	uint8 num_dws;			/**< time period to do the ranging, specified in dws */
++	uint8 reserve;			/**< reserved field */
++	wl_nan_ranging_peer_t rp[1];	/**< variable length array of peers */
++} wl_nan_ranging_list_t;
++
++/* ranging results, a list for self initiated ranging and one for peer initiated ranging */
++/* There will be one structure for each peer */
++#define WL_NAN_RANGING_STATUS_SUCCESS		1
++#define WL_NAN_RANGING_STATUS_FAIL		2
++#define WL_NAN_RANGING_STATUS_TIMEOUT		3
++#define WL_NAN_RANGING_STATUS_ABORT		4 /**< with partial results if sounding count > 0 */
++typedef struct nan_ranging_result {
++	uint8 status;			/**< 1: Success, 2: Fail 3: Timeout 4: Aborted */
++	uint8 sounding_count;		/**< number of measurements completed (0 = failure) */
++	struct ether_addr ea;		/**< initiator MAC address */
++	uint32 chanspec;		/**< Chanspec where the ranging was done */
++	uint32 timestamp;		/**< 32bits of the TSF timestamp ranging was completed at */
++	uint32 distance;		/**< mean distance in meters expressed as Q4 number.
++					 * Only valid when sounding_count > 0. Examples:
++					 * 0x08 = 0.5m
++					 * 0x10 = 1m
++					 * 0x18 = 1.5m
++					 * set to 0xffffffff to indicate invalid number
++					 */
++	int32 rtt_var;			/**< standard deviation in 10th of ns of RTTs measured.
++					 * Only valid when sounding_count > 0
++					 */
++	struct ether_addr tgtea;	/**< target MAC address */
++	uint8 PAD[2];
++} wl_nan_ranging_result_t;
++typedef struct nan_ranging_event_data {
++	uint8 mode;			/**< 1: Result of host initiated ranging */
++					/* 2: Result of peer initiated ranging */
++	uint8 reserved;
++	uint8 success_count;		/**< number of peers completed successfully */
++	uint8 count;			/**< number of peers in the list */
++	wl_nan_ranging_result_t rr[1];	/**< variable array of ranging peers */
++} wl_nan_ranging_event_data_t;
++
++enum {
++	WL_NAN_STATS_RSSI = 1,
++	WL_NAN_STATS_DATA = 2,
++	WL_NAN_STATS_DP = 3,
++/*
++ * ***** ADD before this line ****
++ */
++	WL_NAN_STATS_INVALID
++};
++typedef struct wl_nan_dp_stats {
++	uint32 tbd; /* TBD */
++} wl_nan_dp_stats_t;
++
++typedef struct wl_nan_stats {
++	/* general */
++	uint32 cnt_dw; /* DW slots */
++	uint32 cnt_disc_bcn_sch; /* disc beacon slots */
++	uint32 cnt_amr_exp; /* count of ambtt expiries resetting roles */
++	uint32 cnt_bcn_upd; /* count of beacon template updates */
++	uint32 cnt_bcn_tx; /* count of sync & disc bcn tx */
++	uint32 cnt_bcn_rx; /* count of sync & disc bcn rx */
++	uint32 cnt_sync_bcn_tx; /* count of sync bcn tx within DW */
++	uint32 cnt_disc_bcn_tx; /* count of disc bcn tx */
++	uint32 cnt_sdftx_bcmc; /* count of bcast/mcast sdf tx */
++	uint32 cnt_sdftx_uc; /* count of unicast sdf tx */
++	uint32 cnt_sdftx_fail; /* count of unicast sdf tx fails */
++	uint32 cnt_sdf_rx; /* count of  sdf rx */
++	/* NAN roles */
++	uint32 cnt_am; /* anchor master */
++	uint32 cnt_master; /* master */
++	uint32 cnt_nms; /* non master sync */
++	uint32 cnt_nmns; /* non master non sync */
++	/* TX */
++	uint32 cnt_err_txtime; /* txtime in sync bcn frame not a multiple of dw intv */
++	uint32 cnt_err_unsch_tx; /* tx while not in DW/ disc bcn slot */
++	uint32 cnt_err_bcn_tx; /*  beacon tx error */
++	uint32 cnt_sync_bcn_tx_miss; /* no. of times time delta between 2 cosequetive
++						* sync beacons is more than expected
++						*/
++	/* MSCH */
++	uint32 cnt_err_msch_reg; /* error is Dw/disc reg with msch */
++	uint32 cnt_err_wrong_ch_cb; /* count of msch calbacks in wrong channel */
++	uint32 cnt_dw_skip;	/* count of DW rejected */
++	uint32 cnt_disc_skip; /* count of disc bcn rejected */
++	uint32 cnt_dw_start_early; /* msch cb not at registered time */
++	uint32 cnt_dw_start_late; /* no. of delays in slot start */
++	/* SCANS */
++	uint32 cnt_mrg_scan; /* count of merge scans completed */
++	uint32 cnt_err_ms_rej; /* number of merge scan failed */
++	uint32 cnt_scan_results; /* no. of nan beacons scanned */
++	uint32 cnt_join_scan_rej; /* no. of join scans rejected */
++	uint32 cnt_nan_scan_abort; /* no. of join scans rejected */
++	/* enable/disable */
++	uint32 cnt_nan_enab; /* no. of times nan feature got enabled */
++	uint32 cnt_nan_disab; /* no. of times nan feature got disabled */
++	uint32 cnt_sync_bcn_rx; /* count of sync bcn rx within DW */
++} wl_nan_stats_t;
++
++#define WL_NAN_MAC_MAX_NAN_PEERS 6
++#define WL_NAN_MAC_MAX_RSSI_DATA_PER_PEER  10
++
++typedef struct wl_nan_nbr_rssi {
++	uint8 rx_chan; /* channel number on which bcn rcvd */
++	uint8 PAD[3];
++	int32 rssi_raw;  /* received rssi value */
++	int32 rssi_avg;  /* normalized rssi value */
++} wl_nan_peer_rssi_t;
++
++typedef struct wl_nan_peer_rssi_entry {
++	struct ether_addr mac;  /* peer mac address */
++	uint8 flags;   /* TODO:rssi data order: latest first, oldest first etc */
++	uint8 rssi_cnt;   /* rssi data sample present */
++	wl_nan_peer_rssi_t rssi[WL_NAN_MAC_MAX_RSSI_DATA_PER_PEER]; /* RSSI data frm peer */
++} wl_nan_peer_rssi_entry_t;
++
++#define WL_NAN_PEER_RSSI      0x1
++#define WL_NAN_PEER_RSSI_LIST 0x2
++
++typedef struct wl_nan_nbr_rssi_data {
++	uint8 flags;   /* this is a list or single rssi data */
++	uint8 peer_cnt; /* number of peers */
++	uint16 pad; /* padding */
++	wl_nan_peer_rssi_entry_t peers[1]; /* peers data list */
++} wl_nan_peer_rssi_data_t;
++
++/* WL_NAN_CMD_DBG_DUMP, GET Resp */
++typedef struct wl_nan_dbg_dump_rsp {
++	wl_nan_dbg_dump_type_t dump_type; /* dump data type */
++	uint8 pad[3];
++	union {
++		wl_nan_peer_rssi_data_t peer_rssi;
++		wl_nan_stats_t		nan_stats;
++	} u;
++} wl_nan_dbg_dump_rsp_t;
++
++enum nan_termination_status {
++	NAN_TERM_REASON_INVALID = 1,
++	NAN_TERM_REASON_TIMEOUT = 2,
++	NAN_TERM_REASON_USER_REQ = 3,
++	NAN_TERM_REASON_FAILURE = 4,
++	NAN_TERM_REASON_COUNT_REACHED = 5,
++	NAN_TERM_REASON_DE_SHUTDOWN = 6,
++	NAN_TERM_REASON_DISABLE_IN_PROGRESS = 7
++};
++
++/* nan2 data iovar */
++/* nan2 qos */
++typedef struct wl_nan_dp_qos
++{
++	uint8 tid;
++	uint8 pad;
++	uint16 pkt_size;
++	uint16 mean_rate;
++	uint16 svc_interval;
++} wl_nan_dp_qos_t;
++/* ndp config */
++typedef struct wl_nan_ndp_config
++{
++	uint8 ndp_id;
++	uint8 pub_id;
++	struct ether_addr pub_addr;
++	struct ether_addr data_addr;	/* configure local data addr */
++	struct ether_addr init_data_addr;	/* initiator data addr */
++	uint8 svc_spec_info[WL_NAN_DATA_SVC_SPEC_INFO_LEN];
++	wl_nan_dp_qos_t qos;
++	uint16 avail_len;
++	uint8 pad[3];
++	uint8 data[1];
++} wl_nan_ndp_config_t;
++
++/* nan2 device capabilities */
++typedef struct wl_nan_ndp_oper_cfg {
++	uint8 awake_dw_2g;
++	uint8 awake_dw_5g;
++	uint8 bands_supported;
++	uint8 op_mode;
++} wl_nan_ndp_oper_cfg_t;
++
++typedef uint8 wl_nan_ndp_ndpid_t;
++typedef uint8 wl_nan_ndp_conn_t;
++
++typedef struct wl_nan_dp_req {
++	uint8 type;		    /* 0- unicast 1 - multicast */
++	uint8 pub_id;		    /* Publisher ID */
++	uint16 flags;
++	struct ether_addr peer_mac; /* Peer's NMI addr */
++	struct ether_addr mcast_mac; /* Multicast addr */
++	wl_nan_dp_qos_t qos;
++	uint8 tlv_params[];	/* xtlv parameters for command */
++} wl_nan_dp_req_t;
++
++/* TODO  Need to replace ndp_id with lndp_id */
++/* Return structure to data req IOVAR */
++typedef struct wl_nan_dp_req_ret {
++	struct ether_addr indi;	    /* Initiators data mac addr */
++	uint8 ndp_id;		    /* Initiators ndpid */
++	uint8 pad;
++} wl_nan_dp_req_ret_t;
++
++typedef struct wl_nan_dp_resp {
++	uint8 type;		    /* 0- unicast 1 - multicast */
++	uint8 status;		    /* Accepted or Rejected */
++	uint8 reason_code;
++	/* Local NDP ID for unicast, mc_id for multicast, 0 for implicit NMSG */
++	uint8 ndp_id;
++	wl_nan_dp_qos_t qos;
++	/* Initiator data address for unicast or multicast address for multicast */
++	struct ether_addr mac_addr;
++	uint16 flags;
++	uint8 tlv_params[];	/* xtlv parameters for command */
++} wl_nan_dp_resp_t;
++
++/* Return structure to data resp IOVAR */
++typedef struct wl_nan_dp_resp_ret {
++	uint8 nmsgid;		    /* NMSG ID or for multicast else 0 */
++	uint8 pad[3];
++} wl_nan_dp_resp_ret_t;
++
++typedef struct wl_nan_dp_conf {
++	uint8 lndp_id;
++	uint8 status;		    /* Accepted or Rejected */
++	uint8 pad[2];
++} wl_nan_dp_conf_t;
++
++typedef struct wl_nan_dp_end
++{
++	uint8 lndp_id;
++	uint8 status;
++	uint8 pad[2];
++} wl_nan_dp_end_t;
++
++typedef struct wl_nan_dp_schedupd {
++	uint8 type;		/* 0: unicast, 1: multicast */
++	uint8 flags;
++	struct ether_addr addr;	/* peer NMI or multicast addr */
++	wl_nan_dp_qos_t qos;
++	uint8 map_id;
++	uint8 pad[3];
++} wl_nan_dp_schedupd_t;
++
++/* set: update with notification, unset: NDL setup handshake */
++#define WL_NAN_DP_SCHEDUPD_NOTIF (1 << 0)
++
++/* list ndp ids */
++typedef struct wl_nan_ndp_id_list {
++	uint16 ndp_count;
++	uint8 lndp_id[];
++} wl_nan_ndp_id_list_t;
++
++/* nan2 status */
++typedef struct ndp_session {
++	uint8 lndp_id;
++	uint8 state;
++	uint8 pub_id;
++	uint8 pad;
++} ndp_session_t;
++
++typedef struct wl_nan_ndp_status {
++	struct ether_addr peer_nmi;
++	struct ether_addr peer_ndi;
++	ndp_session_t session;
++	uint8 pad;
++} wl_nan_ndp_status_t;
++
++/* events */
++#define NAN_DP_SESSION_UNICAST         0
++#define NAN_DP_SESSION_MULTICAST       1
++#define NAN_DP_SECURITY_NONE           0
++#define NAN_DP_SECURITY_CSID           1
++#define NAN_DP_SECURITY_MK             2
++#define WL_NAN_DATA_NMSGID_LEN    8 /* 8 bytes as per nan spec */
++
++/* Common event structure for Nan Datapath
++ * Used for sending NDP Indication, Response, Confirmation, Securty Install and Establish events
++ */
++typedef struct wl_nan_ev_datapath_cmn {
++	uint8 type;
++	/* ndp_id is valid only if type is unicast */
++	uint8 ndp_id;
++	uint8 pub_id;
++	uint8 security;
++	/* Following two fields are valid only if type is unicast */
++	struct ether_addr initiator_ndi;
++	struct ether_addr responder_ndi;
++	struct ether_addr peer_nmi;
++	uint8 status;
++	uint8 role;
++	/* Following two fields are valid only if type is multicast */
++	uint8 nmsg_id[WL_NAN_DATA_NMSGID_LEN];
++	uint8 mc_id;
++	uint8 pad[1];
++	uint16 opt_tlv_len;
++	uint8 opt_tlvs[];
++} wl_nan_ev_datapath_cmn_t;
++
++typedef struct wl_nan_ev_datapath_end {
++	uint8 ndp_id;
++	uint8 status;
++	uint8 pad[2];
++	struct ether_addr peer_nmi;
++	struct ether_addr peer_ndi;
++} wl_nan_ev_datapath_end_t;
++
++/* NAN2.0 Ranging definitions */
++
++/* result indication bit map */
++#define NAN_RANGE_INDICATION_CONT		(1<<0)
++#define NAN_RANGE_INDICATION_INGRESS		(1<<1)
++#define NAN_RANGE_INIDICATION_EGRESS		(1<<2)
++
++/* responder flags */
++#define NAN_RANGE_FLAG_AUTO_ACCEPT	(1 << 0)
++#define NAN_RANGE_FLAG_RESULT_REQUIRED	(1 << 1)
++
++typedef struct wl_nan_range_req {
++	struct ether_addr peer;
++	uint8 publisher_id;
++	uint8 indication; /* bit map for result event */
++	uint32 resolution; /* default millimeters */
++	uint32 ingress; /* ingress limit in mm */
++	uint32 egress; /* egress limit in mm */
++	uint32 interval; /* max interval(in TU) b/w two ranging measurements */
++} wl_nan_range_req_t;
++
++#define NAN_RNG_REQ_IOV_LEN	24
++
++typedef uint8 wl_nan_range_id;
++
++typedef struct wl_nan_range_resp {
++	wl_nan_range_id range_id;
++	uint8 flags; /* auto response, range result required */
++	uint8 status; /* accept, reject */
++	uint8 indication; /* bit map for result event */
++	uint32 resolution; /* default millimeters */
++	uint32 ingress; /* ingress limit in mm */
++	uint32 egress; /* egress limit in mm */
++	uint32 interval; /* max interval(in TU) b/w two ranging measurements */
++} wl_nan_range_resp_t;
++
++#define NAN_RNG_RESP_IOV_LEN	20
++
++#define NAN_RNG_MAX_IOV_LEN	255
++
++typedef struct wl_nan_ev_rng_req_ind {
++	struct ether_addr peer_m_addr;
++	uint8 rng_id;
++	/* ftm parameters */
++	uint8 max_burst_dur;
++	uint8 min_ftm_delta;
++	uint8 max_num_ftm;
++	uint8 ftm_format_bw;
++	/* location info availability bit map */
++	uint8 lc_info_avail;
++	/* Last movement indication */
++	uint16 last_movement;
++	uint8 pad[2];
++} wl_nan_ev_rng_req_ind_t;
++
++#define NAN_RNG_REQ_IND_SIZE 14
++
++typedef struct wl_nan_ev_rng_rpt_ind {
++	uint32 dist_mm; /* in millimeter */
++	struct ether_addr peer_m_addr;
++	uint8 indication; /* indication definitions mentioned above */
++	uint8 pad;
++} wl_nan_ev_rng_rpt_ind_t;
++
++#define NAN_RNG_RPT_IND_SIZE 11
++
++typedef struct wl_nan_ev_rng_term_ind {
++	struct ether_addr peer_m_addr;
++	uint8 reason_code;
++	uint8 pad;
++} wl_nan_ev_rng_term_ind_t;
++
++#define NAN_RNG_TERM_IND_SIZE 7
++
++
++/* ********************* end of NAN section ******************************** */
++/* endif WL_NAN */
++
++#define P2P_NAN_IOC_BUFSZ  512 /* some sufficient ioc buff size */
++#define WL_P2P_NAN_IOCTL_VERSION    0x1
++
++/* container for p2p nan iovtls & events */
++typedef struct wl_p2p_nan_ioc {
++	uint16  version;    /* interface command or event version */
++	uint16  id;     /* p2p nan ioctl cmd  ID  */
++	uint16  len;        /* total length of data[]  */
++	uint16  pad;        /* padding */
++	uint8   data [];   /* var len payload of bcm_xtlv_t type */
++} wl_p2p_nan_ioc_t;
++
++/* p2p nan cmd IDs */
++enum wl_p2p_nan_cmds {
++	/* p2p nan cfg ioctls */
++	WL_P2P_NAN_CMD_ENABLE = 1,
++	WL_P2P_NAN_CMD_CONFIG = 2,
++	WL_P2P_NAN_CMD_DEL_CONFIG = 3,
++	WL_P2P_NAN_CMD_GET_INSTS = 4
++};
++
++#define WL_P2P_NAN_CONFIG_VERSION       1
++
++#define WL_P2P_NAN_DEVICE_P2P  0x0
++#define WL_P2P_NAN_DEVICE_GO   0x1
++#define WL_P2P_NAN_DEVICE_GC   0x2
++#define WL_P2P_NAN_DEVICE_INVAL   0xFF
++
++/* NAN P2P operation */
++typedef struct p2p_nan_config {
++	uint16 version;            /* wl_p2p_nan_config_t structure version */
++	uint16 len;                /* total length including version and variable IE */
++	uint32 flags;              /* 0x1 to NEW, 0x2 to ADD, 0x4 to DEL */
++	uint8  inst_id;            /* publisher/subscriber id */
++	uint8  inst_type;          /* publisher/subscriber */
++	uint8  dev_role;           /* P2P device role: 'P2P','GO' or 'GC' */
++	uint8  pad1;               /* padding */
++	uint8  resolution;         /* Availability bitmap resolution */
++	uint8  repeat;             /* Whether Availabilty repeat across DW */
++	uint16 ie_len;             /* variable ie len */
++	struct ether_addr dev_mac; /* P2P device addres */
++	uint16 pad2;               /* Padding */
++	uint32 avail_bmap;         /* availability interval bitmap */
++	uint32 chanspec;           /* Chanspec */
++	uint8  ie[];              /* hex ie data */
++} wl_p2p_nan_config_t;
++
++#define WL_P2P_NAN_SERVICE_LIST_VERSION 1
++typedef enum wl_nan_service_type {
++	WL_NAN_SVC_INST_PUBLISHER = 1,
++	WL_NAN_SVC_INST_SUBSCRIBER = 2
++} wl_nan_service_type_t;
++
++#define WL_P2P_NAN_CONFIG_NEW   0x1
++#define WL_P2P_NAN_CONFIG_ADD   0x2
++#define WL_P2P_NAN_CONFIG_DEL   0x4
++
++typedef struct wl_nan_svc_inst {
++	uint8  inst_id;      /* publisher/subscriber id */
++	uint8  inst_type;    /* publisher/subscriber */
++} wl_nan_svc_inst_t;
++
++typedef struct wl_nan_svc_inst_list {
++	uint16 version;           /* this structure version */
++	uint16 len;               /* total length including version and variable svc list */
++	uint16 count;             /* service instance count */
++	uint16 pad;               /* padding */
++	wl_nan_svc_inst_t svc[1]; /* service instance list */
++} wl_nan_svc_inst_list_t;
++
++#define NAN_POST_DISC_P2P_DATA_VER  1
++/* This structure will be used send peer p2p data with
++ * NAN discovery result
++ */
++typedef struct nan_post_disc_p2p_data {
++	uint8 ver;                 /* this structure version */
++	uint8 dev_role;            /* P2P Device role */
++	uint8 resolution;          /* Availability bitmap resolution */
++	uint8 repeat;              /* Whether Availabilty repeat across DW */
++	struct ether_addr dev_mac; /* P2P device addres */
++	uint16 pad1;               /* Padding */
++	uint32 chanspec;           /* Chanspec */
++	uint32 avl_bmp;				/* availability interval bitmap */
++} nan_post_disc_p2p_data_t;
++
++/* timeslot etc for NAN */
++enum {
++	WL_TMU_TU            = 0,
++	WL_TMU_SEC           = 1,
++	WL_TMU_MILLI_SEC     = 2,
++	WL_TMU_MICRO_SEC     = 3,
++	WL_TMU_NANO_SEC      = 4,
++	WL_TMU_PICO_SEC      = 5
++};
++typedef int16 wl_tmu_t;
++
++typedef struct {
++	uint32   intvl;               /* time interval */
++	wl_tmu_t tmu;                 /* time unit */
++	uint8    pad[2];              /* padding */
++} wl_time_interval_t;
++
++/* availabiloty slot flags */
++enum {
++	WL_AVAIL_SLOT_NONE		= 0x0000,
++	WL_AVAIL_SLOT_COM		= 0x0001,		/* committed */
++	WL_AVAIL_SLOT_POT		= 0x0002,		/* potential */
++	WL_AVAIL_SLOT_PROP		= 0x0004,	/* proposed -  note: not configurable */
++	WL_AVAIL_SLOT_PAGED		= 0x0008	/* P-NDL */
++	/* 0x0030 - resrved for NDC index */
++	/* 0x00c0 - resrved for usage preference */
++};
++typedef int16 wl_avail_slot_flags_t;
++
++#define WL_AVAIL_SLOT_NDC_MASK 0x0030 /* up to 4 NDCs */
++#define WL_AVAIL_SLOT_NDC_SHIFT 4
++#define WL_AVAIL_SLOT_NDC(_flags)  (((_flags) & WL_AVAIL_SLOT_NDC_MASK) \
++	 >> WL_AVAIL_SLOT_NDC_SHIFT)
++#define WL_AVAIL_SLOT_SET_NDC(_flags, _ndc_idx) (((_flags) & ~WL_AVAIL_SLOT_NDC_MASK) |\
++	((_ndc_idx) << WL_AVAIL_SLOT_NDC_SHIFT))
++
++#define WL_AVAIL_SLOT_UPREF_MASK 0x00c0 /* up to 4 usage preferences */
++#define WL_AVAIL_SLOT_UPREF_SHIFT 6
++#define WL_AVAIL_SLOT_UPREF(_flags)  (((_flags) & WL_AVAIL_SLOT_UPREF_MASK) \
++	 >> WL_AVAIL_SLOT_UPREF_SHIFT)
++#define WL_AVAIL_SLOT_SET_UPREF(_flags, _pref) (((_flags) & ~WL_AVAIL_SLOT_UPREF_MASK) |\
++	((_pref) << WL_AVAIL_SLOT_UPREF_SHIFT))
++
++typedef struct wl_avail_slot {
++	wl_avail_slot_flags_t flags;
++	uint16                PAD;
++	wl_time_interval_t    start;        /* from time ref */
++	wl_time_interval_t    duration;     /* from start */
++	uint32                chanspec;     /* channel spec */
++} wl_avail_slot_t;
++
++/* time reference */
++enum {
++	WL_TIME_REF_NONE        = 0,
++	WL_TIME_REF_DEV_TSF     = 1,
++	WL_TIME_REF_NAN_DW      = 2,
++	WL_TIME_REF_TBTT        = 3,
++	WL_TIME_REF_NAN_DW0     = 4
++};
++typedef int16 wl_time_ref_t;
++
++enum {
++	WL_AVAIL_NONE		= 0x0000,
++	WL_AVAIL_LOCAL		= 0x0001,
++	WL_AVAIL_PEER		= 0x0002,
++	WL_AVAIL_NDC		= 0x0003,
++	WL_AVAIL_IMMUTABLE	= 0x0004,
++	WL_AVAIL_RESPONSE	= 0x0005,
++	WL_AVAIL_COUNTER	= 0x0006,
++	WL_AVAIL_RANGING	= 0x0007,
++	WL_AVAIL_TYPE_MAX	= WL_AVAIL_RANGING	/* New ones before and update */
++};
++#define WL_AVAIL_TYPE_MASK	0x000F
++#define WL_AVAIL_FLAG_RAW_MODE	0x8000
++typedef int16 wl_avail_flags_t;
++
++/* availability entry flags */
++enum {
++	WL_AVAIL_ENTRY_NONE		= 0x0000,
++	WL_AVAIL_ENTRY_COM		= 0x0001,		/* committed */
++	WL_AVAIL_ENTRY_POT		= 0x0002,		/* potential */
++	WL_AVAIL_ENTRY_COND		= 0x0004,	/* conditional */
++	WL_AVAIL_ENTRY_PAGED		= 0x0008,	/* P-NDL */
++	WL_AVAIL_ENTRY_USAGE		= 0x0030,	/* usage preference */
++	WL_AVAIL_ENTRY_BIT_DUR		= 0x00c0,	/* bit duration */
++	WL_AVAIL_ENTRY_BAND_PRESENT	= 0x0100,	/* band present */
++	WL_AVAIL_ENTRY_CHAN_PRESENT	= 0x0200,	/* channel information present */
++	WL_AVAIL_ENTRY_CHAN_ENTRY_PRESENT	= 0x0400,	/* channel entry (opclass+bitmap) */
++};
++
++/* bit duration */
++enum {
++	WL_AVAIL_BIT_DUR_16	= 0,	/* 16TU */
++	WL_AVAIL_BIT_DUR_32	= 1,	/* 32TU */
++	WL_AVAIL_BIT_DUR_64	= 2,	/* 64TU */
++	WL_AVAIL_BIT_DUR_128	= 3,	/* 128TU */
++};
++
++/* period */
++enum {
++	WL_AVAIL_PERIOD_0	= 0,	/* 0TU */
++	WL_AVAIL_PERIOD_128	= 1,	/* 128TU */
++	WL_AVAIL_PERIOD_256	= 2,	/* 256TU */
++	WL_AVAIL_PERIOD_512	= 3,	/* 512TU */
++	WL_AVAIL_PERIOD_1024	= 4,	/* 1024TU */
++	WL_AVAIL_PERIOD_2048	= 5,	/* 2048TU */
++	WL_AVAIL_PERIOD_4096	= 6,	/* 4096TU */
++	WL_AVAIL_PERIOD_8192	= 7,	/* 8192TU */
++};
++
++/* band */
++enum {
++	WL_AVAIL_BAND_NONE	= 0,	/* reserved */
++	WL_AVAIL_BAND_SUB1G	= 1,	/* sub-1 GHz */
++	WL_AVAIL_BAND_2G	= 2,	/* 2.4 GHz */
++	WL_AVAIL_BAND_3G	= 3,	/* reserved (for 3.6 GHz) */
++	WL_AVAIL_BAND_5G	= 4,	/* 4.9 and 5 GHz */
++	WL_AVAIL_BAND_60G	= 5,	/* reserved (for 60 GHz) */
++};
++
++#define WL_AVAIL_ENTRY_TYPE_MASK 0x0F
++#define WL_AVAIL_ENTRY_USAGE_MASK 0x0030 /* up to 4 usage preferences */
++#define WL_AVAIL_ENTRY_USAGE_SHIFT 4
++#define WL_AVAIL_ENTRY_USAGE_VAL(_flags)  (((_flags) & WL_AVAIL_ENTRY_USAGE_MASK) \
++	>> WL_AVAIL_ENTRY_USAGE_SHIFT)
++
++#define WL_AVAIL_ENTRY_BIT_DUR_MASK 0x00c0 /* 0:16TU, 1:32TU, 2:64TU, 3:128TU */
++#define WL_AVAIL_ENTRY_BIT_DUR_SHIFT 6
++#define WL_AVAIL_ENTRY_BIT_DUR_VAL(_flags)  (((_flags) & WL_AVAIL_ENTRY_BIT_DUR_MASK) \
++	>> WL_AVAIL_ENTRY_BIT_DUR_SHIFT)
++
++#define WL_AVAIL_ENTRY_BAND_MASK 0x0100 /* 0=band not present, 1=present */
++#define WL_AVAIL_ENTRY_BAND_SHIFT 8
++
++#define WL_AVAIL_ENTRY_CHAN_MASK 0x0200 /* 0=channel info not present, 1=present */
++#define WL_AVAIL_ENTRY_CHAN_SHIFT 9
++
++#define WL_AVAIL_ENTRY_CHAN_ENTRY_MASK 0x0400 /* 0=chanspec, 1=hex channel entry */
++#define WL_AVAIL_ENTRY_CHAN_ENTRY_SHIFT 10
++
++#define WL_AVAIL_ENTRY_OPCLASS_MASK 0xFF
++#define WL_AVAIL_ENTRY_CHAN_BITMAP_MASK 0xFF00
++#define WL_AVAIL_ENTRY_CHAN_BITMAP_SHIFT 8
++#define WL_AVAIL_ENTRY_CHAN_BITMAP_VAL(_info) (((_info) & WL_AVAIL_ENTRY_CHAN_BITMAP_MASK) \
++	>> WL_AVAIL_ENTRY_CHAN_BITMAP_SHIFT)
++
++/* Used for raw channel entry field input */
++#define	MAX_CHAN_ENTRY_LEN 6
++
++typedef struct wl_avail_entry {
++	uint16		length;		/* total length */
++	uint16		start_offset;	/* in TUs, multiply by 16 for total offset */
++	union {
++		uint32 channel_info;	/* either chanspec or hex channel entry (opclass +
++					 * bitmap per NAN spec), as indicated by setting
++					 * WL_AVAIL_ENTRY_HEX_CHAN_ENTRY flag
++					 */
++		uint32 band;		/* defined by WL_BAND enum, 2=2.4GHz, 4=5GHz */
++		uint8	channel_entry[MAX_CHAN_ENTRY_LEN];
++	} u;				/* band or channel value, 0=all band/channels */
++	uint8		pad[2];
++	uint8		period;		/* in TUs, defined by WL_AVAIL_PERIOD enum
++					 * 1:128, 2:256, 3:512, 4:1024, 5:2048, 6:4096,
++					 * 7:8192
++					 */
++	uint8		bitmap_len;
++	uint16		flags;		/* defined by avail entry flags enum:
++					 * type, usage pref, bit duration, band, channel
++					 */
++	uint8		bitmap[];	/* time bitmap */
++} wl_avail_entry_t;
++
++typedef struct wl_avail {
++	uint16		length;		/* total length */
++	uint16		flags;		/* defined by WL_AVAIL enum
++					 * 1=local, 2=peer, 3=ndc, 4=immutable,
++					 * 5=response, 6=counter
++					 */
++	uint8		id;		/* id used for multiple maps/avail */
++	uint8		pad[3];
++	struct ether_addr addr;	/* peer mac address or ndc id */
++	uint8		num_entries;
++	uint8		entry_offset;
++	/* add additional fields above this line */
++	uint8		entry[];
++} wl_avail_t;
++
++#define WL_AVAIL_MIN_LEN(n) ((n) ? OFFSETOF(wl_avail_t, entry) + \
++		((n) * OFFSETOF(wl_avail_entry_t, bitmap)) : 0)
++
++/* unaligned schedule (window) */
++typedef struct wl_avail_ulw {
++	uint8	id;		/* schedule ID */
++	uint8	overwrite;	/* bit 0: overwrite all
++				 * 1-4: map ID if overwrite all is 0
++				 */
++	uint16	flags;
++	uint32	start;		/* start time of first ULW, in us */
++	uint32	dur;		/* duration of ULW, in us */
++	uint32	period;		/* time between consecutive ULWs, in us */
++	union {
++		uint32 chanspec;
++		uint32 band;
++		uint8 chan_entry[MAX_CHAN_ENTRY_LEN];
++		uint8 pad[8];
++	} u;
++	uint8	cntdwn;		/* remaining ULWs before schedule ends */
++	uint8	pad[3];
++} wl_avail_ulw_t;
++
++/* unset: NAN is not available during ULW, set: NAN is avail depending on ctrl flags */
++#define WL_NAN_ULW_CTRL_PRESENT		(1 << 0)
++/* unset: band, set: channel */
++#define WL_NAN_ULW_CTRL_TYPE		(1 << 1)
++/* set: NAN is availabile on specified band/channel */
++#define WL_NAN_ULW_CTRL_AVAIL		(1 << 2)
++/* channel is provided in raw attribute format */
++#define WL_NAN_ULW_CTRL_RAW_CHAN	(1 << 3)
++
++/* nan wfa testmode operations */
++enum {
++	WL_NAN_WFA_TM_IGNORE_TERMINATE_NAF		= 0x00000001,
++	WL_NAN_WFA_TM_IGNORE_RX_DATA_OUTSIDE_CRB	= 0x00000002,
++	WL_NAN_WFA_TM_ALLOW_TX_DATA_OUTSIDE_CRB		= 0x00000004,
++	WL_NAN_WFA_TM_ENFORCE_NDL_COUNTER		= 0x00000008,
++	WL_NAN_WFA_TM_BYPASS_NDL_PROPOSAL_VALIDATION	= 0x00000010,
++	/* allow data(pings) tx while ndp sec negotiation */
++	WL_NAN_WFA_TM_SEC_SEND_PINGS_BYPASS_NDP_SM	= 0x00000020,
++	/* generate and insert incorrect mic */
++	WL_NAN_WFA_TM_SEC_INCORRECT_MIC		        = 0x00000040,
++	/* send m4 reject deliberately */
++	WL_NAN_WFA_TM_SEC_REJECT_STATUS4M4		= 0x00000080,
++	/* send mgmt frame (for eg. ndp terminate) in clear txt (bypass security) */
++	WL_NAN_WFA_TM_SEC_SEND_MGMT_CLEAR	        = 0x00000100,
++	WL_NAN_WFA_TM_FLAG_MASK				= 0x000001ff /* add above & update mask */
++};
++typedef uint32 wl_nan_wfa_testmode_t;
++
++#define RSSI_THRESHOLD_SIZE 16
++#define MAX_IMP_RESP_SIZE 256
++
++typedef struct wl_proxd_rssi_bias {
++	int32		version;			/**< version */
++	int32		threshold[RSSI_THRESHOLD_SIZE];	/**< threshold */
++	int32		peak_offset;			/**< peak offset */
++	int32		bias;				/**< rssi bias */
++	int32		gd_delta;			/**< GD - GD_ADJ */
++	int32		imp_resp[MAX_IMP_RESP_SIZE];	/**< (Hi*Hi)+(Hr*Hr) */
++} wl_proxd_rssi_bias_t;
++
++typedef struct wl_proxd_rssi_bias_avg {
++	int32		avg_threshold[RSSI_THRESHOLD_SIZE];	/**< avg threshold */
++	int32		avg_peak_offset;			/**< avg peak offset */
++	int32		avg_rssi;				/**< avg rssi */
++	int32		avg_bias;				/**< avg bias */
++} wl_proxd_rssi_bias_avg_t;
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct wl_proxd_collect_info {
++	uint16		type;  /**< type: 0 channel table, 1 channel smoothing table, 2 and 3 seq */
++	uint16		index;		/**< The current frame index, from 1 to total_frames. */
++	uint16		tof_cmd;	/**< M_TOF_CMD      */
++	uint16		tof_rsp;	/**< M_TOF_RSP      */
++	uint16		tof_avb_rxl;	/**< M_TOF_AVB_RX_L */
++	uint16		tof_avb_rxh;	/**< M_TOF_AVB_RX_H */
++	uint16		tof_avb_txl;	/**< M_TOF_AVB_TX_L */
++	uint16		tof_avb_txh;	/**< M_TOF_AVB_TX_H */
++	uint16		tof_id;		/**< M_TOF_ID */
++	uint8		tof_frame_type;
++	uint8		tof_frame_bw;
++	int8		tof_rssi;
++	int32		tof_cfo;
++	int32		gd_adj_ns;	/**< gound delay */
++	int32		gd_h_adj_ns;	/**< group delay + threshold crossing */
++	int16		nfft;		/**< number of samples stored in H */
++	uint8		num_max_cores;
++
++} BWL_POST_PACKED_STRUCT wl_proxd_collect_info_t;
++#include <packed_section_end.h>
++
++#define K_TOF_COLLECT_H_PAD 1
++#define K_TOF_COLLECT_SC_20MHZ (64)
++/* Maximum possible size of sample capture */
++#define K_TOF_COLLECT_SC_80MHZ (2*K_TOF_COLLECT_SC_20MHZ)
++/* Maximum possible size of channel dump */
++#define K_TOF_COLLECT_CHAN_SIZE (2*K_TOF_COLLECT_SC_80MHZ)
++
++/*
++A few extra samples are required to estimate frequency offset
++Right now 16 samples are being used. Can be changed in future.
++*/
++#define K_TOF_COLLECT_SAMP_SIZE_20MHZ (2*(K_TOF_COLLECT_SC_20MHZ)+16+K_TOF_COLLECT_H_PAD)
++#define K_TOF_COLLECT_RAW_SAMP_SIZE_20MHZ (2*K_TOF_COLLECT_SAMP_SIZE_20MHZ)
++#define K_TOF_COLLECT_H_SIZE_20MHZ (K_TOF_COLLECT_SAMP_SIZE_20MHZ)
++#define K_TOF_COLLECT_HRAW_SIZE_20MHZ (K_TOF_COLLECT_RAW_SAMP_SIZE_20MHZ)
++
++#define K_TOF_COLLECT_SAMP_SIZE_80MHZ (2*(K_TOF_COLLECT_SC_80MHZ)+16+K_TOF_COLLECT_H_PAD)
++#define K_TOF_COLLECT_RAW_SAMP_SIZE_80MHZ (2*K_TOF_COLLECT_SAMP_SIZE_80MHZ)
++#define K_TOF_COLLECT_H_SIZE_80MHZ (K_TOF_COLLECT_SAMP_SIZE_80MHZ)
++#define K_TOF_COLLECT_HRAW_SIZE_80MHZ (K_TOF_COLLECT_RAW_SAMP_SIZE_80MHZ)
++
++#define WL_PROXD_COLLECT_DATA_VERSION_1		1
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct wl_proxd_collect_data_v1 {
++	wl_proxd_collect_info_t  info;
++	uint8	ri_rr[FTM_TPK_RI_RR_LEN];
++	/**< raw data read from phy used to adjust timestamps */
++	uint32	H[K_TOF_COLLECT_H_SIZE_20MHZ];
++} BWL_POST_PACKED_STRUCT wl_proxd_collect_data_t_v1;
++#include <packed_section_end.h>
++
++#define WL_PROXD_COLLECT_DATA_VERSION_2		2
++typedef struct wl_proxd_collect_data_v2 {
++	uint16			version;
++	uint16			len;
++	wl_proxd_collect_info_t	info;
++	uint8			ri_rr[FTM_TPK_RI_RR_LEN];
++	uint8			pad[3]; /* should be based on FTM_TPK_RI_RR_LEN */
++	/**< raw data read from phy used to adjust timestamps */
++	uint32			H[K_TOF_COLLECT_H_SIZE_20MHZ];
++	uint32			chan[4 * K_TOF_COLLECT_CHAN_SIZE];
++} wl_proxd_collect_data_t_v2;
++#define WL_PROXD_COLLECT_DATA_VERSION_MAX	WL_PROXD_COLLECT_DATA_VERSION_2
++
++typedef struct wl_proxd_debug_data {
++	uint8		count;		/**< number of packets */
++	uint8		stage;		/**< state machone stage */
++	uint8		received;	/**< received or txed */
++	uint8		paket_type;	/**< packet type */
++	uint8		category;	/**< category field */
++	uint8		action;		/**< action field */
++	uint8		token;		/**< token number */
++	uint8		follow_token;	/**< following token number */
++	uint16		index;		/**< index of the packet */
++	uint16		tof_cmd;	/**< M_TOF_CMD */
++	uint16		tof_rsp;	/**< M_TOF_RSP */
++	uint16		tof_avb_rxl;	/**< M_TOF_AVB_RX_L */
++	uint16		tof_avb_rxh;	/**< M_TOF_AVB_RX_H */
++	uint16		tof_avb_txl;	/**< M_TOF_AVB_TX_L */
++	uint16		tof_avb_txh;	/**< M_TOF_AVB_TX_H */
++	uint16		tof_id;		/**< M_TOF_ID */
++	uint16		tof_status0;	/**< M_TOF_STATUS_0 */
++	uint16		tof_status2;	/**< M_TOF_STATUS_2 */
++	uint16		tof_chsm0;	/**< M_TOF_CHNSM_0 */
++	uint16		tof_phyctl0;	/**< M_TOF_PHYCTL0 */
++	uint16		tof_phyctl1;	/**< M_TOF_PHYCTL1 */
++	uint16		tof_phyctl2;	/**< M_TOF_PHYCTL2 */
++	uint16		tof_lsig;	/**< M_TOF_LSIG */
++	uint16		tof_vhta0;	/**< M_TOF_VHTA0 */
++	uint16		tof_vhta1;	/**< M_TOF_VHTA1 */
++	uint16		tof_vhta2;	/**< M_TOF_VHTA2 */
++	uint16		tof_vhtb0;	/**< M_TOF_VHTB0 */
++	uint16		tof_vhtb1;	/**< M_TOF_VHTB1 */
++	uint16		tof_apmductl;	/**< M_TOF_AMPDU_CTL */
++	uint16		tof_apmdudlim;	/**< M_TOF_AMPDU_DLIM */
++	uint16		tof_apmdulen;	/**< M_TOF_AMPDU_LEN */
++} wl_proxd_debug_data_t;
++
++/** version of the wl_wsec_info structure */
++#define WL_WSEC_INFO_VERSION 0x01
++
++/** start enum value for BSS properties */
++#define WL_WSEC_INFO_BSS_BASE 0x0100
++
++/** size of len and type fields of wl_wsec_info_tlv_t struct */
++#define WL_WSEC_INFO_TLV_HDR_LEN OFFSETOF(wl_wsec_info_tlv_t, data)
++
++/** Allowed wl_wsec_info properties; not all of them may be supported. */
++typedef enum {
++	WL_WSEC_INFO_NONE = 0,
++	WL_WSEC_INFO_MAX_KEYS = 1,
++	WL_WSEC_INFO_NUM_KEYS = 2,
++	WL_WSEC_INFO_NUM_HW_KEYS = 3,
++	WL_WSEC_INFO_MAX_KEY_IDX = 4,
++	WL_WSEC_INFO_NUM_REPLAY_CNTRS = 5,
++	WL_WSEC_INFO_SUPPORTED_ALGOS = 6,
++	WL_WSEC_INFO_MAX_KEY_LEN = 7,
++	WL_WSEC_INFO_FLAGS = 8,
++	/* add global/per-wlc properties above */
++	WL_WSEC_INFO_BSS_FLAGS = (WL_WSEC_INFO_BSS_BASE + 1),
++	WL_WSEC_INFO_BSS_WSEC = (WL_WSEC_INFO_BSS_BASE + 2),
++	WL_WSEC_INFO_BSS_TX_KEY_ID = (WL_WSEC_INFO_BSS_BASE + 3),
++	WL_WSEC_INFO_BSS_ALGO = (WL_WSEC_INFO_BSS_BASE + 4),
++	WL_WSEC_INFO_BSS_KEY_LEN = (WL_WSEC_INFO_BSS_BASE + 5),
++	WL_WSEC_INFO_BSS_ALGOS = (WL_WSEC_INFO_BSS_BASE + 6),
++	/* add per-BSS properties above */
++	WL_WSEC_INFO_MAX = 0xffff
++} wl_wsec_info_type_t;
++
++typedef struct {
++	uint32 algos; /* set algos to be enabled/disabled */
++	uint32 mask; /* algos outside mask unaltered */
++} wl_wsec_info_algos_t;
++
++/** tlv used to return wl_wsec_info properties */
++typedef struct {
++	uint16 type;
++	uint16 len;		/**< data length */
++	uint8 data[1];	/**< data follows */
++} wl_wsec_info_tlv_t;
++
++/** input/output data type for wsec_info iovar */
++typedef struct wl_wsec_info {
++	uint8 version; /**< structure version */
++	uint8 pad[2];
++	uint8 num_tlvs;
++	wl_wsec_info_tlv_t tlvs[1]; /**< tlv data follows */
++} wl_wsec_info_t;
++
++/*
++ * randmac definitions
++ */
++#define WL_RANDMAC_MODULE			"randmac"
++#define WL_RANDMAC_API_VERSION		0x0100 /**< version 1.0 */
++#define WL_RANDMAC_API_MIN_VERSION	0x0100 /**< version 1.0 */
++
++/** subcommands that can apply to randmac */
++enum {
++	WL_RANDMAC_SUBCMD_NONE				= 0,
++	WL_RANDMAC_SUBCMD_GET_VERSION			= 1,
++	WL_RANDMAC_SUBCMD_ENABLE			= 2,
++	WL_RANDMAC_SUBCMD_DISABLE			= 3,
++	WL_RANDMAC_SUBCMD_CONFIG			= 4,
++	WL_RANDMAC_SUBCMD_STATS				= 5,
++	WL_RANDMAC_SUBCMD_CLEAR_STATS			= 6,
++
++	WL_RANDMAC_SUBCMD_MAX
++};
++typedef int16 wl_randmac_subcmd_t;
++
++/* Common IOVAR struct */
++typedef struct wl_randmac {
++	uint16 version;
++	uint16 len;			/* total length */
++	wl_randmac_subcmd_t subcmd_id;	/* subcommand id */
++	uint8 data[0];			/* subcommand data */
++} wl_randmac_t;
++
++#define WL_RANDMAC_IOV_HDR_SIZE OFFSETOF(wl_randmac_t, data)
++
++/* randmac version subcommand */
++typedef struct wl_randmac_version {
++	uint16 version;  /* Randmac method version info */
++	uint8 pad[2];    /* Align on 4 byte boundary */
++} wl_randmac_version_t;
++
++/*
++ * Bitmask for methods supporting MAC randomization feature
++ */
++#define WL_RANDMAC_USER_NONE		0x0000
++#define WL_RANDMAC_USER_FTM		0x0001
++#define WL_RANDMAC_USER_NAN		0x0002
++#define WL_RANDMAC_USER_SCAN		0x0004
++#define WL_RANDMAC_USER_ALL		0xFFFF
++typedef uint16 wl_randmac_method_t;
++
++enum {
++	WL_RANDMAC_FLAGS_NONE	= 0x00,
++	WL_RANDMAC_FLAGS_ADDR	= 0x01,
++	WL_RANDMAC_FLAGS_MASK	= 0x02,
++	WL_RANDMAC_FLAGS_METHOD	= 0x04,
++	WL_RANDMAC_FLAGS_ALL	= 0xFF
++};
++typedef uint8 wl_randmac_flags_t;
++
++/* randmac statistics subcommand */
++typedef struct wl_randmac_stats {
++	uint32 set_ok;		/* Set random addr success count */
++	uint32 set_fail;	/* Set random addr failed count */
++	uint32 set_reqs;	/* Set random addr count */
++	uint32 reset_reqs;	/* Restore random addr count */
++	uint32 restore_ok;	/* Restore random addr succes count */
++	uint32 restore_fail;	/* Restore random addr failed count */
++	uint32 events_sent;	/* randmac module events count */
++	uint32 events_rcvd;	/* randmac events received count */
++} wl_randmac_stats_t;
++
++/* randmac config subcommand */
++typedef struct wl_randmac_config {
++	struct ether_addr addr;			/* Randomized MAC address */
++	struct ether_addr addr_mask;		/* bitmask for randomization */
++	wl_randmac_method_t method;		/* Enabled methods */
++	wl_randmac_flags_t flags;		/* What config info changed */
++	uint8	PAD;
++} wl_randmac_config_t;
++
++enum {
++	WL_RANDMAC_EVENT_NONE			= 0,	/**< not an event, reserved */
++	WL_RANDMAC_EVENT_BSSCFG_ADDR_SET	= 1,	/* bsscfg addr randomized */
++	WL_RANDMAC_EVENT_BSSCFG_ADDR_RESTORE	= 2,	/* bsscfg addr restored */
++	WL_RANDMAC_EVENT_ENABLED		= 3,	/* randmac module enabled */
++	WL_RANDMAC_EVENT_DISABLE		= 4,	/* randmac module disabled */
++	WL_RANDMAC_EVENT_BSSCFG_STATUS	= 5,	/* bsscfg enable/disable */
++
++	WL_RANDMAC_EVENT_MAX
++};
++typedef int16 wl_randmac_event_type_t;
++typedef int32 wl_randmac_status_t;
++typedef uint32 wl_randmac_event_mask_t;
++
++#define WL_RANDMAC_EVENT_MASK_ALL 0xfffffffe
++#define WL_RANDMAC_EVENT_MASK_EVENT(_event_type) (1 << (_event_type))
++#define WL_RANDMAC_EVENT_ENABLED(_mask, _event_type) (\
++	((_mask) & WL_RANDMAC_EVENT_MASK_EVENT(_event_type)) != 0)
++
++/** tlv IDs - data length 4 bytes unless overridden by type, alignment 32 bits */
++enum {
++	WL_RANDMAC_TLV_NONE		= 0,
++	WL_RANDMAC_TLV_METHOD		= 1,
++	WL_RANDMAC_TLV_ADDR		= 2,
++	WL_RANDMAC_TLV_MASK		= 3
++};
++typedef uint16 wl_randmac_tlv_id_t;
++
++typedef struct wl_randmac_tlv {
++	wl_randmac_tlv_id_t id;
++	uint16 len;		/* Length of variable */
++	uint8  data[1];
++} wl_randmac_tlv_t;
++
++/** randmac event */
++typedef struct wl_randmac_event {
++	uint16					version;
++	uint16					len;	/* Length of all variables */
++	wl_randmac_event_type_t			type;
++	wl_randmac_method_t			method;
++	uint8					pad[2];
++	wl_randmac_tlv_t			tlvs[1];	/**< variable */
++} wl_randmac_event_t;
++
++/*
++ * scan MAC definitions
++ */
++
++/** common iovar struct */
++typedef struct wl_scanmac {
++	uint16 subcmd_id;	/**< subcommand id */
++	uint16 len;		/**< total length of data[] */
++	uint8 data[];		/**< subcommand data */
++} wl_scanmac_t;
++
++/* subcommand ids */
++#define WL_SCANMAC_SUBCMD_ENABLE   0
++#define WL_SCANMAC_SUBCMD_BSSCFG   1   /**< only GET supported */
++#define WL_SCANMAC_SUBCMD_CONFIG   2
++
++/** scanmac enable data struct */
++typedef struct wl_scanmac_enable {
++	uint8 enable;	/**< 1 - enable, 0 - disable */
++	uint8 pad[3];	/**< 4-byte struct alignment */
++} wl_scanmac_enable_t;
++
++/** scanmac bsscfg data struct */
++typedef struct wl_scanmac_bsscfg {
++	uint32 bsscfg;	/**< bsscfg index */
++} wl_scanmac_bsscfg_t;
++
++/** scanmac config data struct */
++typedef struct wl_scanmac_config {
++	struct ether_addr mac;	/**< 6 bytes of MAC address or MAC prefix (i.e. OUI) */
++	struct ether_addr random_mask;	/**< randomized bits on each scan */
++	uint16 scan_bitmap;	/**< scans to use this MAC address */
++	uint8 pad[2];	/**< 4-byte struct alignment */
++} wl_scanmac_config_t;
++
++/* scan bitmap */
++#define WL_SCANMAC_SCAN_UNASSOC		(0x01 << 0)	/**< unassociated scans */
++#define WL_SCANMAC_SCAN_ASSOC_ROAM	(0x01 << 1)	/**< associated roam scans */
++#define WL_SCANMAC_SCAN_ASSOC_PNO	(0x01 << 2)	/**< associated PNO scans */
++#define WL_SCANMAC_SCAN_ASSOC_HOST	(0x01 << 3)	/**< associated host scans */
++/*
++ * bonjour dongle offload definitions
++ */
++
++/* common iovar struct */
++typedef struct wl_bdo {
++	uint16 subcmd_id;	/* subcommand id */
++	uint16 len;		/* total length of data[] */
++	uint8 data[];		/* subcommand data */
++} wl_bdo_t;
++
++/* subcommand ids */
++#define WL_BDO_SUBCMD_DOWNLOAD		0	/* Download flattened database  */
++#define WL_BDO_SUBCMD_ENABLE		1	/* Start bonjour after download */
++#define WL_BDO_SUBCMD_MAX_DOWNLOAD	2	/* Get the max download size    */
++
++/* maximum fragment size */
++#define BDO_MAX_FRAGMENT_SIZE	1024
++
++/* download flattened database
++ *
++ * BDO must be disabled before database download else fail.
++ *
++ * If database size is within BDO_MAX_FRAGMENT_SIZE then only a single fragment
++ * is required (i.e. frag_num = 0, total_size = frag_size).
++ * If database size exceeds BDO_MAX_FRAGMENT_SIZE then multiple fragments are required.
++ */
++typedef struct wl_bdo_download {
++	uint16 total_size;	/* total database size */
++	uint16 frag_num;	/* fragment number, 0 for first fragment, N-1 for last fragment */
++	uint16 frag_size;	/* size of fragment (max BDO_MAX_FRAGMENT_SIZE) */
++	uint8 pad[2];		/* 4-byte struct alignment */
++	uint8 fragment[BDO_MAX_FRAGMENT_SIZE];  /* fragment data */
++} wl_bdo_download_t;
++
++/* enable
++ *
++ * Enable requires a downloaded database else fail.
++ */
++typedef struct wl_bdo_enable {
++	uint8 enable;	/* 1 - enable, 0 - disable */
++	uint8 pad[3];	/* 4-byte struct alignment */
++} wl_bdo_enable_t;
++
++/*
++ * Get the max download size for Bonjour Offload.
++ */
++typedef struct wl_bdo_max_download {
++	uint16 size;	/* Max download size in bytes */
++	uint8 pad[2];	/* 4-byte struct alignment    */
++} wl_bdo_max_download_t;
++
++/*
++ * TCP keepalive offload definitions
++ */
++
++/* common iovar struct */
++typedef struct wl_tko {
++	uint16 subcmd_id;	/* subcommand id */
++	uint16 len;		/* total length of data[] */
++	uint8 data[];		/* subcommand data */
++} wl_tko_t;
++
++/* subcommand ids */
++#define WL_TKO_SUBCMD_MAX_TCP		0	/* max TCP connections supported */
++#define WL_TKO_SUBCMD_PARAM		1	/* configure offload common parameters  */
++#define WL_TKO_SUBCMD_CONNECT		2	/* TCP connection info */
++#define WL_TKO_SUBCMD_ENABLE		3	/* enable/disable */
++#define WL_TKO_SUBCMD_STATUS		4	/* TCP connection status */
++
++/* WL_TKO_SUBCMD_MAX_CONNECT subcommand data */
++typedef struct wl_tko_max_tcp {
++	uint8 max;	/* max TCP connections supported */
++	uint8 pad[3];	/* 4-byte struct alignment */
++} wl_tko_max_tcp_t;
++
++/* WL_TKO_SUBCMD_PARAM subcommand data */
++typedef struct wl_tko_param {
++	uint16 interval;	/* keepalive tx interval (secs) */
++	uint16 retry_interval;	/* keepalive retry interval (secs) */
++	uint16 retry_count;	/* retry_count */
++	uint8 pad[2];		/* 4-byte struct alignment */
++} wl_tko_param_t;
++
++/* WL_TKO_SUBCMD_CONNECT subcommand data
++ * invoke with unique 'index' for each TCP connection
++ */
++typedef struct wl_tko_connect {
++	uint8 index;		/* TCP connection index, 0 to max-1 */
++	uint8 ip_addr_type;	/* 0 - IPv4, 1 - IPv6 */
++	uint16 local_port;	/* local port */
++	uint16 remote_port;	/* remote port */
++	uint16 PAD;
++	uint32 local_seq;	/* local sequence number */
++	uint32 remote_seq;	/* remote sequence number */
++	uint16 request_len;	/* TCP keepalive request packet length */
++	uint16 response_len;	/* TCP keepalive response packet length */
++	uint8 data[];		/* variable length field containing local/remote IPv4/IPv6,
++				 * TCP keepalive request packet, TCP keepalive response packet
++				 *    For IPv4, length is 4 * 2 + request_length + response_length
++				 *       offset 0 - local IPv4
++				 *       offset 4 - remote IPv4
++				 *       offset 8 - TCP keepalive request packet
++				 *       offset 8+request_length - TCP keepalive response packet
++				 *    For IPv6, length is 16 * 2 + request_length + response_length
++				 *       offset 0 - local IPv6
++				 *       offset 16 - remote IPv6
++				 *       offset 32 - TCP keepalive request packet
++				 *       offset 32+request_length - TCP keepalive response packet
++				 */
++} wl_tko_connect_t;
++
++/* WL_TKO_SUBCMD_CONNECT subcommand data to GET configured info for specific index */
++typedef struct wl_tko_get_connect {
++	uint8 index;		/* TCP connection index, 0 to max-1 */
++	uint8 pad[3];		/* 4-byte struct alignment */
++} wl_tko_get_connect_t;
++
++typedef struct wl_tko_enable {
++	uint8 enable;	/* 1 - enable, 0 - disable */
++	uint8 pad[3];	/* 4-byte struct alignment */
++} wl_tko_enable_t;
++
++/* WL_TKO_SUBCMD_STATUS subcommand data */
++/* must be invoked before tko is disabled else status is unavailable */
++typedef struct wl_tko_status {
++	uint8 count;		/* number of status entries (i.e. equals
++				 * max TCP connections supported)
++	                         */
++	uint8 status[1];	/* variable length field contain status for
++				 * each TCP connection index
++				 */
++} wl_tko_status_t;
++
++typedef enum {
++	TKO_STATUS_NORMAL			= 0,	/* TCP connection normal, no error */
++	TKO_STATUS_NO_RESPONSE			= 1,	/* no response to TCP keepalive */
++	TKO_STATUS_NO_TCP_ACK_FLAG		= 2,	/* TCP ACK flag not set */
++	TKO_STATUS_UNEXPECT_TCP_FLAG		= 3,	/* unexpect TCP flags set other than ACK */
++	TKO_STATUS_SEQ_NUM_INVALID		= 4,	/* ACK != sequence number */
++	TKO_STATUS_REMOTE_SEQ_NUM_INVALID	= 5,	/* SEQ > remote sequence number */
++	TKO_STATUS_TCP_DATA			= 6,	/* TCP data available */
++	TKO_STATUS_UNAVAILABLE			= 255,	/* not used/configured */
++} tko_status_t;
++
++enum rssi_reason {
++	RSSI_REASON_UNKNOW = 0,
++	RSSI_REASON_LOWRSSI = 1,
++	RSSI_REASON_NSYC = 2,
++	RSSI_REASON_TIMEOUT = 3
++};
++
++enum tof_reason {
++	TOF_REASON_OK = 0,
++	TOF_REASON_REQEND = 1,
++	TOF_REASON_TIMEOUT = 2,
++	TOF_REASON_NOACK = 3,
++	TOF_REASON_INVALIDAVB = 4,
++	TOF_REASON_INITIAL = 5,
++	TOF_REASON_ABORT = 6
++};
++
++enum rssi_state {
++	RSSI_STATE_POLL = 0,
++	RSSI_STATE_TPAIRING = 1,
++	RSSI_STATE_IPAIRING = 2,
++	RSSI_STATE_THANDSHAKE = 3,
++	RSSI_STATE_IHANDSHAKE = 4,
++	RSSI_STATE_CONFIRMED = 5,
++	RSSI_STATE_PIPELINE = 6,
++	RSSI_STATE_NEGMODE = 7,
++	RSSI_STATE_MONITOR = 8,
++	RSSI_STATE_LAST = 9
++};
++
++enum tof_state {
++	TOF_STATE_IDLE	 = 0,
++	TOF_STATE_IWAITM = 1,
++	TOF_STATE_TWAITM = 2,
++	TOF_STATE_ILEGACY = 3,
++	TOF_STATE_IWAITCL = 4,
++	TOF_STATE_TWAITCL = 5,
++	TOF_STATE_ICONFIRM = 6,
++	TOF_STATE_IREPORT = 7
++};
++
++enum tof_mode_type {
++	TOF_LEGACY_UNKNOWN	= 0,
++	TOF_LEGACY_AP		= 1,
++	TOF_NONLEGACY_AP	= 2
++};
++
++enum tof_way_type {
++	TOF_TYPE_ONE_WAY = 0,
++	TOF_TYPE_TWO_WAY = 1,
++	TOF_TYPE_REPORT = 2
++};
++
++enum tof_rate_type {
++	TOF_FRAME_RATE_VHT = 0,
++	TOF_FRAME_RATE_LEGACY = 1
++};
++
++#define TOF_ADJ_TYPE_NUM	4	/**< number of assisted timestamp adjustment */
++enum tof_adj_mode {
++	TOF_ADJ_SOFTWARE = 0,
++	TOF_ADJ_HARDWARE = 1,
++	TOF_ADJ_SEQ = 2,
++	TOF_ADJ_NONE = 3
++};
++
++#define FRAME_TYPE_NUM		4	/**< number of frame type */
++enum frame_type {
++	FRAME_TYPE_CCK	= 0,
++	FRAME_TYPE_OFDM	= 1,
++	FRAME_TYPE_11N	= 2,
++	FRAME_TYPE_11AC	= 3
++};
++
++typedef struct wl_proxd_status_iovar {
++	uint16			method;				/**< method */
++	uint8			mode;				/**< mode */
++	uint8			peermode;			/**< peer mode */
++	uint8			state;				/**< state */
++	uint8			reason;				/**< reason code */
++	uint8			PAD[2];
++	uint32			distance;			/**< distance */
++	uint32			txcnt;				/**< tx pkt counter */
++	uint32			rxcnt;				/**< rx pkt counter */
++	struct ether_addr	peer;				/**< peer mac address */
++	int8			avg_rssi;			/**< average rssi */
++	int8			hi_rssi;			/**< highest rssi */
++	int8			low_rssi;			/**< lowest rssi */
++	uint8			PAD[3];
++	uint32			dbgstatus;			/**< debug status */
++	uint16			frame_type_cnt[FRAME_TYPE_NUM];	/**< frame types */
++	uint8			adj_type_cnt[TOF_ADJ_TYPE_NUM];	/**< adj types HW/SW */
++} wl_proxd_status_iovar_t;
++
++/* ifdef NET_DETECT */
++typedef struct net_detect_adapter_features {
++	uint8	wowl_enabled;
++	uint8	net_detect_enabled;
++	uint8	nlo_enabled;
++} net_detect_adapter_features_t;
++
++typedef enum net_detect_bss_type {
++	nd_bss_any = 0,
++	nd_ibss,
++	nd_ess
++} net_detect_bss_type_t;
++
++typedef struct net_detect_profile {
++	wlc_ssid_t		ssid;
++	net_detect_bss_type_t   bss_type;	/**< Ignore for now since Phase 1 is only for ESS */
++	uint32			cipher_type;	/**< DOT11_CIPHER_ALGORITHM enumeration values */
++	uint32			auth_type;	/**< DOT11_AUTH_ALGORITHM enumeration values */
++} net_detect_profile_t;
++
++typedef struct net_detect_profile_list {
++	uint32			num_nd_profiles;
++	net_detect_profile_t	nd_profile[];
++} net_detect_profile_list_t;
++
++typedef struct net_detect_config {
++	uint8			    nd_enabled;
++	uint8				PAD[3];
++	uint32			    scan_interval;
++	uint32			    wait_period;
++	uint8			    wake_if_connected;
++	uint8			    wake_if_disconnected;
++	uint8				PAD[2];
++	net_detect_profile_list_t   nd_profile_list;
++} net_detect_config_t;
++
++typedef enum net_detect_wake_reason {
++	nd_reason_unknown,
++	nd_net_detected,
++	nd_wowl_event,
++	nd_ucode_error
++} net_detect_wake_reason_t;
++
++typedef struct net_detect_wake_data {
++	net_detect_wake_reason_t    nd_wake_reason;
++	uint32			    nd_wake_date_length;
++	uint8			    nd_wake_data[0];	    /**< Wake data (currently unused) */
++} net_detect_wake_data_t;
++
++/* endif NET_DETECT */
++
++/* (unversioned, deprecated) */
++typedef struct bcnreq {
++	uint8 bcn_mode;
++	uint8 PAD[3];
++	int32 dur;
++	int32 channel;
++	struct ether_addr da;
++	uint16 random_int;
++	wlc_ssid_t ssid;
++	uint16 reps;
++	uint8 PAD[2];
++} bcnreq_t;
++
++#define WL_RRM_BCN_REQ_VER		1
++typedef struct bcn_req {
++	uint8 version;
++	uint8 bcn_mode;
++	uint8 pad_1[2];
++	int32 dur;
++	int32 channel;
++	struct ether_addr da;
++	uint16 random_int;
++	wlc_ssid_t ssid;
++	uint16 reps;
++	uint8 req_elements;
++	uint8 pad_2;
++	chanspec_list_t chspec_list;
++} bcn_req_t;
++
++typedef struct rrmreq {
++	struct ether_addr da;
++	uint8 reg;
++	uint8 chan;
++	uint16 random_int;
++	uint16 dur;
++	uint16 reps;
++} rrmreq_t;
++
++typedef struct framereq {
++	struct ether_addr da;
++	uint8 reg;
++	uint8 chan;
++	uint16 random_int;
++	uint16 dur;
++	struct ether_addr ta;
++	uint16 reps;
++} framereq_t;
++
++typedef struct statreq {
++	struct ether_addr da;
++	struct ether_addr peer;
++	uint16 random_int;
++	uint16 dur;
++	uint8 group_id;
++	uint8 PAD;
++	uint16 reps;
++} statreq_t;
++
++typedef struct wl_rrm_config_ioc {
++	uint16 version; /* command version */
++	uint16 id;      /* subiovar cmd ID */
++	uint16 len;     /* total length of all bytes in data[] */
++	uint16 pad;     /* 4-byte boundary padding */
++	uint8 data[1];  /* payload */
++} wl_rrm_config_ioc_t;
++
++enum {
++	WL_RRM_CONFIG_NONE	= 0,	/* reserved */
++	WL_RRM_CONFIG_GET_LCI	= 1,	/* get LCI */
++	WL_RRM_CONFIG_SET_LCI	= 2,	/* set LCI */
++	WL_RRM_CONFIG_GET_CIVIC	= 3,	/* get civic location */
++	WL_RRM_CONFIG_SET_CIVIC	= 4,	/* set civic location */
++	WL_RRM_CONFIG_MAX		= 5
++};
++
++#define WL_RRM_CONFIG_NAME "rrm_config"
++#define WL_RRM_CONFIG_MIN_LENGTH OFFSETOF(wl_rrm_config_ioc_t, data)
++
++enum {
++	WL_RRM_EVENT_NONE		= 0,	/* not an event, reserved */
++	WL_RRM_EVENT_FRNG_REQ	= 1,	/* Receipt of FRNG request frame */
++	WL_RRM_EVENT_FRNG_REP	= 2,	/* Receipt of FRNG report frame */
++
++	WL_RRM_EVENT_MAX
++};
++typedef int16 wl_rrm_event_type_t;
++
++typedef struct frngreq_target {
++	uint32 bssid_info;
++	uint8 channel;
++	uint8 phytype;
++	uint8 reg;
++	uint8 pad;
++	struct ether_addr bssid;
++	chanspec_t chanspec;
++	uint32 sid;
++} frngreq_target_t;
++
++typedef struct frngreq {
++	wl_rrm_event_type_t event;			/* RRM event type */
++	struct ether_addr da;
++	uint16 max_init_delay;	/* Upper bound of random delay, in TUs */
++	uint8 min_ap_count;		/* Min FTM ranges requested (1-15) */
++	uint8 num_aps;			/* Number of APs to range, at least min_ap_count */
++	uint16 max_age;			/* Max elapsed time before FTM request, 0xFFFF = any */
++	uint16 reps;			/* Number of repetitions of this measurement type */
++	frngreq_target_t targets[1];	/* Target BSSIDs to range */
++} frngreq_t;
++
++typedef struct frngrep_range {
++	uint32 start_tsf;		/* 4 lsb of tsf */
++	struct ether_addr bssid;
++	uint8 pad[2];
++	uint32 range;
++	uint32 max_err;
++	uint8  rsvd;
++	uint8 pad2[3];
++} frngrep_range_t;
++
++typedef struct frngrep_error {
++	uint32 start_tsf;		/* 4 lsb of tsf */
++	struct ether_addr bssid;
++	uint8  code;
++	uint8 pad[1];
++} frngrep_error_t;
++
++typedef struct frngrep {
++	wl_rrm_event_type_t event;			/* RRM event type */
++	struct ether_addr da;
++	uint8 range_entry_count;
++	uint8 error_entry_count;
++	uint16 dialog_token;				/* dialog token */
++	frngrep_range_t range_entries[DOT11_FTM_RANGE_ENTRY_MAX_COUNT];
++	frngrep_error_t error_entries[DOT11_FTM_RANGE_ERROR_ENTRY_MAX_COUNT];
++} frngrep_t;
++
++typedef struct wl_rrm_frng_ioc {
++	uint16 version; /* command version */
++	uint16 id;      /* subiovar cmd ID */
++	uint16 len;     /* total length of all bytes in data[] */
++	uint16 pad;     /* 4-byte boundary padding */
++	uint8 data[];  /* payload */
++} wl_rrm_frng_ioc_t;
++
++enum {
++	WL_RRM_FRNG_NONE	= 0,	/* reserved */
++	WL_RRM_FRNG_SET_REQ	= 1,	/* send ftm ranging request */
++	WL_RRM_FRNG_MAX		= 2
++};
++
++#define WL_RRM_FRNG_NAME "rrm_frng"
++#define WL_RRM_FRNG_MIN_LENGTH OFFSETOF(wl_rrm_frng_ioc_t, data)
++
++#define WL_RRM_RPT_VER		0
++#define WL_RRM_RPT_MAX_PAYLOAD	256
++#define WL_RRM_RPT_MIN_PAYLOAD	7
++#define WL_RRM_RPT_FALG_ERR	0
++#define WL_RRM_RPT_FALG_GRP_ID_PROPR	(1 << 0)
++#define WL_RRM_RPT_FALG_GRP_ID_0	(1 << 1)
++typedef struct {
++	uint16 ver;		/**< version */
++	struct ether_addr addr;	/**< STA MAC addr */
++	uint32 timestamp;	/**< timestamp of the report */
++	uint16 flag;		/**< flag */
++	uint16 len;		/**< length of payload data */
++	uint8 data[WL_RRM_RPT_MAX_PAYLOAD];
++} statrpt_t;
++
++typedef struct wlc_dwds_config {
++	uint32		enable;
++	uint32		mode; /**< STA/AP interface */
++	struct ether_addr ea;
++	uint8  PAD[2];
++} wlc_dwds_config_t;
++
++typedef struct wl_el_set_params_s {
++	uint8 set;	/**< Set number */
++	uint8  PAD[3];
++	uint32 size;	/**< Size to make/expand */
++} wl_el_set_params_t;
++
++typedef struct wl_el_tag_params_s {
++	uint16 tag;
++	uint8 set;
++	uint8 flags;
++} wl_el_tag_params_t;
++
++/** Video Traffic Interference Monitor config */
++#define INTFER_VERSION		1
++typedef struct wl_intfer_params {
++	uint16 version;			/**< version */
++	uint8 period;			/**< sample period */
++	uint8 cnt;			/**< sample cnt */
++	uint8 txfail_thresh;	/**< non-TCP txfail threshold */
++	uint8 tcptxfail_thresh;	/**< tcptxfail threshold */
++} wl_intfer_params_t;
++
++typedef struct wl_staprio_cfg {
++	struct ether_addr ea;	/**< mac addr */
++	uint8 prio;		/**< scb priority */
++} wl_staprio_cfg_t;
++
++typedef enum wl_stamon_cfg_cmd_type {
++	STAMON_CFG_CMD_DEL = 0,
++	STAMON_CFG_CMD_ADD = 1,
++	STAMON_CFG_CMD_ENB = 2,
++	STAMON_CFG_CMD_DSB = 3,
++	STAMON_CFG_CMD_CNT = 4,
++	STAMON_CFG_CMD_RSTCNT = 5,
++	STAMON_CFG_CMD_GET_STATS = 6
++} wl_stamon_cfg_cmd_type_t;
++
++typedef struct wlc_stamon_sta_config {
++	wl_stamon_cfg_cmd_type_t cmd; /**< 0 - delete, 1 - add */
++	struct ether_addr ea;
++	uint8  PAD[2];
++} wlc_stamon_sta_config_t;
++
++/* ifdef SR_DEBUG */
++typedef struct /* pmu_reg */{
++	uint32  pmu_control;
++	uint32  pmu_capabilities;
++	uint32  pmu_status;
++	uint32  res_state;
++	uint32  res_pending;
++	uint32  pmu_timer1;
++	uint32  min_res_mask;
++	uint32  max_res_mask;
++	uint32  pmu_chipcontrol1[4];
++	uint32  pmu_regcontrol[5];
++	uint32  pmu_pllcontrol[5];
++	uint32  pmu_rsrc_up_down_timer[31];
++	uint32  rsrc_dep_mask[31];
++} pmu_reg_t;
++/* endif SR_DEBUG */
++
++typedef struct wl_taf_define {
++	struct ether_addr ea;	/**< STA MAC or 0xFF... */
++	uint16 version;         /**< version */
++	uint32 sch;             /**< method index */
++	uint32 prio;            /**< priority */
++	uint32 misc;            /**< used for return value */
++	uint8  text[];         /**< used to pass and return ascii text */
++} wl_taf_define_t;
++
++/** Received Beacons lengths information */
++#define WL_LAST_BCNS_INFO_FIXED_LEN		OFFSETOF(wlc_bcn_len_hist_t, bcnlen_ring)
++typedef struct wlc_bcn_len_hist {
++	uint16	ver;				/**< version field */
++	uint16	cur_index;			/**< current pointed index in ring buffer */
++	uint32	max_bcnlen;		/**< Max beacon length received */
++	uint32	min_bcnlen;		/**< Min beacon length received */
++	uint32	ringbuff_len;		/**< Length of the ring buffer 'bcnlen_ring' */
++	uint32	bcnlen_ring[1];	/**< ring buffer storing received beacon lengths */
++} wlc_bcn_len_hist_t;
++
++/* WDS net interface types */
++#define WL_WDSIFTYPE_NONE  0x0 /**< The interface type is neither WDS nor DWDS. */
++#define WL_WDSIFTYPE_WDS   0x1 /**< The interface is WDS type. */
++#define WL_WDSIFTYPE_DWDS  0x2 /**< The interface is DWDS type. */
++
++typedef struct wl_bssload_static {
++	uint8 is_static;
++	uint8  PAD;
++	uint16 sta_count;
++	uint8 chan_util;
++	uint8  PAD;
++	uint16 aac;
++} wl_bssload_static_t;
++
++/* Buffer of size WLC_SAMPLECOLLECT_MAXLEN (=10240 for 4345a0 ACPHY)
++ * gets copied to this, multiple times
++ */
++typedef enum wl_gpaio_option {
++	GPAIO_PMU_AFELDO,
++	GPAIO_PMU_TXLDO,
++	GPAIO_PMU_VCOLDO,
++	GPAIO_PMU_LNALDO,
++	GPAIO_PMU_ADCLDO,
++	GPAIO_ICTAT_CAL,
++	GPAIO_PMU_CLEAR,
++	GPAIO_OFF,
++	GPAIO_PMU_LOGENLDO,
++	GPAIO_PMU_RXLDO2G,
++	GPAIO_PMU_RXLDO5G
++} wl_gpaio_option_t;
++
++/** IO Var Operations - the Value of iov_op In wlc_ap_doiovar */
++typedef enum wlc_ap_iov_bss_operation {
++	WLC_AP_IOV_OP_DELETE                   = -1,
++	WLC_AP_IOV_OP_DISABLE                  = 0,
++	WLC_AP_IOV_OP_ENABLE                   = 1,
++	WLC_AP_IOV_OP_MANUAL_AP_BSSCFG_CREATE  = 2,
++	WLC_AP_IOV_OP_MANUAL_STA_BSSCFG_CREATE = 3,
++	WLC_AP_IOV_OP_MOVE                     = 4
++} wlc_ap_iov_bss_oper_t;
++
++/* LTE coex info */
++/* Analogue of HCI Set MWS Signaling cmd */
++typedef struct {
++	int16	mws_rx_assert_offset;
++	int16	mws_rx_assert_jitter;
++	int16	mws_rx_deassert_offset;
++	int16	mws_rx_deassert_jitter;
++	int16	mws_tx_assert_offset;
++	int16	mws_tx_assert_jitter;
++	int16	mws_tx_deassert_offset;
++	int16	mws_tx_deassert_jitter;
++	int16	mws_pattern_assert_offset;
++	int16	mws_pattern_assert_jitter;
++	int16	mws_inact_dur_assert_offset;
++	int16	mws_inact_dur_assert_jitter;
++	int16	mws_scan_freq_assert_offset;
++	int16	mws_scan_freq_assert_jitter;
++	int16	mws_prio_assert_offset_req;
++} wci2_config_t;
++
++/** Analogue of HCI MWS Channel Params */
++typedef struct {
++	uint16	mws_rx_center_freq; /**< MHz */
++	uint16	mws_tx_center_freq;
++	uint16	mws_rx_channel_bw;  /**< KHz */
++	uint16	mws_tx_channel_bw;
++	uint8	mws_channel_en;
++	uint8	mws_channel_type;   /**< Don't care for WLAN? */
++} mws_params_t;
++
++#define LTECX_MAX_NUM_PERIOD_TYPES	7
++
++/* LTE Frame params */
++typedef struct {
++	uint16	mws_frame_dur;
++	int16	mws_framesync_assert_offset;
++	uint16	mws_framesync_assert_jitter;
++	uint16  mws_period_dur[LTECX_MAX_NUM_PERIOD_TYPES];
++	uint8	mws_period_type[LTECX_MAX_NUM_PERIOD_TYPES];
++	uint8	mws_num_periods;
++} mws_frame_config_t;
++
++/** MWS wci2 message */
++typedef struct {
++	uint8	mws_wci2_data; /**< BT-SIG msg */
++	uint8	PAD;
++	uint16	mws_wci2_interval; /**< Interval in us */
++	uint16	mws_wci2_repeat; /**< No of msgs to send */
++} mws_wci2_msg_t;
++/* MWS ANT map */
++typedef struct {
++	uint16	combo1; /* mws ant selection 1 */
++	uint16	combo2; /* mws ant selection 2 */
++	uint16	combo3; /* mws ant selection 3 */
++	uint16	combo4; /* mws ant selection 4 */
++} mws_ant_map_t;
++
++/* MWS SCAN_REQ Bitmap */
++typedef struct mws_scanreq_params {
++	uint16 idx;
++	uint16 bm_2g;
++	uint16 bm_5g_lo;
++	uint16 bm_5g_mid;
++	uint16 bm_5g_hi;
++} mws_scanreq_params_t;
++
++typedef struct {
++	uint32 config;	/**< MODE: AUTO (-1), Disable (0), Enable (1) */
++	uint32 status;	/**< Current state: Disabled (0), Enabled (1) */
++} wl_config_t;
++
++#define WLC_RSDB_MODE_AUTO_MASK 0x80
++#define WLC_RSDB_EXTRACT_MODE(val) ((int8)((val) & (~(WLC_RSDB_MODE_AUTO_MASK))))
++
++typedef struct {
++	uint16  request; /* type of sensor hub request */
++	uint16  enable; /* enable/disable response for specified request */
++	uint16  interval; /* interval between responses to the request */
++} shub_req_t;
++
++#define	WL_IF_STATS_T_VERSION 1	/**< current version of wl_if_stats structure */
++
++/** per interface counters */
++typedef struct wl_if_stats {
++	uint16	version;		/**< version of the structure */
++	uint16	length;			/**< length of the entire structure */
++	uint32	PAD;			/**< padding */
++
++	/* transmit stat counters */
++	uint64	txframe;		/**< tx data frames */
++	uint64	txbyte;			/**< tx data bytes */
++	uint64	txerror;		/**< tx data errors (derived: sum of others) */
++	uint64  txnobuf;		/**< tx out of buffer errors */
++	uint64  txrunt;			/**< tx runt frames */
++	uint64  txfail;			/**< tx failed frames */
++	uint64	txretry;		/**< tx retry frames */
++	uint64	txretrie;		/**< tx multiple retry frames */
++	uint64	txfrmsnt;		/**< tx sent frames */
++	uint64	txmulti;		/**< tx mulitcast sent frames */
++	uint64	txfrag;			/**< tx fragments sent */
++
++	/* receive stat counters */
++	uint64	rxframe;		/**< rx data frames */
++	uint64	rxbyte;			/**< rx data bytes */
++	uint64	rxerror;		/**< rx data errors (derived: sum of others) */
++	uint64	rxnobuf;		/**< rx out of buffer errors */
++	uint64  rxrunt;			/**< rx runt frames */
++	uint64  rxfragerr;		/**< rx fragment errors */
++	uint64	rxmulti;		/**< rx multicast frames */
++
++	uint64	txexptime;		/* DATA Tx frames suppressed due to timer expiration */
++	uint64	txrts;			/* RTS/CTS succeeeded count */
++	uint64	txnocts;		/* RTS/CTS faled count */
++
++	uint64	txretrans;		/* Number of frame retransmissions */
++}
++wl_if_stats_t;
++
++typedef struct wl_band {
++	uint16		bandtype;		/**< WL_BAND_2G, WL_BAND_5G */
++	uint16		bandunit;		/**< bandstate[] index */
++	uint16		phytype;		/**< phytype */
++	uint16		phyrev;
++}
++wl_band_t;
++
++#define	WL_WLC_VERSION_T_VERSION 1 /**< current version of wlc_version structure */
++
++/** wlc interface version */
++typedef struct wl_wlc_version {
++	uint16	version;		/**< version of the structure */
++	uint16	length;			/**< length of the entire structure */
++
++	/* epi version numbers */
++	uint16	epi_ver_major;		/**< epi major version number */
++	uint16	epi_ver_minor;		/**< epi minor version number */
++	uint16	epi_rc_num;		/**< epi RC number */
++	uint16	epi_incr_num;		/**< epi increment number */
++
++	/* wlc interface version numbers */
++	uint16	wlc_ver_major;		/**< wlc interface major version number */
++	uint16	wlc_ver_minor;		/**< wlc interface minor version number */
++}
++wl_wlc_version_t;
++
++/* Highest version of WLC_API_VERSION supported */
++#define WLC_API_VERSION_MAJOR_MAX	8
++#define WLC_API_VERSION_MINOR_MAX	0
++
++/* begin proxd definitions */
++#include <packed_section_start.h>
++
++#define WL_PROXD_API_VERSION 0x0300	/**< version 3.0 */
++
++/** Minimum supported API version */
++#define WL_PROXD_API_MIN_VERSION 0x0300
++
++/** proximity detection methods */
++enum {
++	WL_PROXD_METHOD_NONE	= 0,
++	WL_PROXD_METHOD_RSVD1	= 1, /**< backward compatibility - RSSI, not supported */
++	WL_PROXD_METHOD_TOF	= 2,
++	WL_PROXD_METHOD_RSVD2	= 3, /**< 11v only - if needed */
++	WL_PROXD_METHOD_FTM	= 4, /**< IEEE rev mc/2014 */
++	WL_PROXD_METHOD_MAX
++};
++typedef int16 wl_proxd_method_t;
++
++/** global and method configuration flags */
++enum {
++	WL_PROXD_FLAG_NONE			= 0x00000000,
++	WL_PROXD_FLAG_RX_ENABLED		= 0x00000001, /**< respond to requests, per bss */
++	WL_PROXD_FLAG_RX_RANGE_REQ		= 0x00000002, /**< 11mc range requests enabled */
++	WL_PROXD_FLAG_TX_LCI			= 0x00000004, /**< tx lci, if known */
++	WL_PROXD_FLAG_TX_CIVIC			= 0x00000008, /**< tx civic, if known */
++	WL_PROXD_FLAG_RX_AUTO_BURST		= 0x00000010, /**< auto respond w/o host action */
++	WL_PROXD_FLAG_TX_AUTO_BURST		= 0x00000020, /**< continue tx w/o host action */
++	WL_PROXD_FLAG_AVAIL_PUBLISH		= 0x00000040,     /**< publish availability */
++	WL_PROXD_FLAG_AVAIL_SCHEDULE		= 0x00000080,    /**< schedule using availability */
++	WL_PROXD_FLAG_ASAP_CAPABLE		= 0x00000100, /* ASAP capable */
++	WL_PROXD_FLAG_MBURST_FOLLOWUP		= 0x00000200, /* new multi-burst algorithm */
++	WL_PROXD_FLAG_SECURE			= 0x00000400, /* per bsscfg option */
++	WL_PROXD_FLAG_NO_TSF_SYNC		= 0x00000800, /* disable tsf sync */
++	WL_PROXD_FLAG_ALL			= 0xffffffff
++};
++typedef uint32 wl_proxd_flags_t;
++
++#define WL_PROXD_FLAGS_AVAIL (WL_PROXD_FLAG_AVAIL_PUBLISH | \
++	WL_PROXD_FLAG_AVAIL_SCHEDULE)
++
++/** session flags */
++enum {
++	WL_PROXD_SESSION_FLAG_NONE 		= 0x00000000,  /**< no flags */
++	WL_PROXD_SESSION_FLAG_INITIATOR 	= 0x00000001,  /**< local device is initiator */
++	WL_PROXD_SESSION_FLAG_TARGET 		= 0x00000002,  /**< local device is target */
++	WL_PROXD_SESSION_FLAG_ONE_WAY		= 0x00000004,  /**< (initiated) 1-way rtt */
++	WL_PROXD_SESSION_FLAG_AUTO_BURST	= 0x00000008,  /**< created w/ rx_auto_burst */
++	WL_PROXD_SESSION_FLAG_PERSIST		= 0x00000010,  /**< good until cancelled */
++	WL_PROXD_SESSION_FLAG_RTT_DETAIL	= 0x00000020,  /**< rtt detail in results */
++	WL_PROXD_SESSION_FLAG_SECURE		= 0x00000040,  /**< sessionis secure */
++	WL_PROXD_SESSION_FLAG_AOA		= 0x00000080,  /**< AOA along w/ RTT */
++	WL_PROXD_SESSION_FLAG_RX_AUTO_BURST	= 0x00000100,  /**< Same as proxd flags above */
++	WL_PROXD_SESSION_FLAG_TX_AUTO_BURST	= 0x00000200,  /**< Same as proxd flags above */
++	WL_PROXD_SESSION_FLAG_NAN_BSS		= 0x00000400,  /**< Use NAN BSS, if applicable */
++	WL_PROXD_SESSION_FLAG_TS1		= 0x00000800,  /**< e.g. FTM1 - ASAP-capable */
++	WL_PROXD_SESSION_FLAG_REPORT_FAILURE	= 0x00002000, /**< report failure to target */
++	WL_PROXD_SESSION_FLAG_INITIATOR_RPT	= 0x00004000, /**< report distance to target */
++	WL_PROXD_SESSION_FLAG_NOCHANSWT		= 0x00008000,
++	WL_PROXD_SESSION_FLAG_NETRUAL		= 0x00010000, /**< netrual mode */
++	WL_PROXD_SESSION_FLAG_SEQ_EN		= 0x00020000, /**< Toast */
++	WL_PROXD_SESSION_FLAG_NO_PARAM_OVRD	= 0x00040000, /**< no param override from target */
++	WL_PROXD_SESSION_FLAG_ASAP		= 0x00080000, /**< ASAP session */
++	WL_PROXD_SESSION_FLAG_REQ_LCI		= 0x00100000, /**< transmit LCI req */
++	WL_PROXD_SESSION_FLAG_REQ_CIV		= 0x00200000, /**< transmit civic loc req */
++	WL_PROXD_SESSION_FLAG_PRE_SCAN		= 0x00400000, /* enable pre-scan for asap=1 */
++	WL_PROXD_SESSION_FLAG_AUTO_VHTACK	= 0x00800000, /* use vhtack based on brcm ie */
++	WL_PROXD_SESSION_FLAG_VHTACK		= 0x01000000, /* vht ack is in use - output only */
++	WL_PROXD_SESSION_FLAG_BDUR_NOPREF	= 0x02000000, /* burst-duration: no preference */
++	WL_PROXD_SESSION_FLAG_NUM_FTM_NOPREF	= 0x04000000, /* num of FTM frames: no preference */
++	WL_PROXD_SESSION_FLAG_FTM_SEP_NOPREF	= 0x08000000, /* time btw FTM frams: no pref */
++	WL_PROXD_SESSION_FLAG_NUM_BURST_NOPREF	= 0x10000000, /* num of bursts: no pref */
++	WL_PROXD_SESSION_FLAG_BURST_PERIOD_NOPREF = 0x20000000, /* burst period: no pref */
++	WL_PROXD_SESSION_FLAG_MBURST_FOLLOWUP	= 0x40000000, /* new mburst algo  - reserved */
++	WL_PROXD_SESSION_FLAG_MBURST_NODELAY	= 0x80000000, /**< good until cancelled */
++	WL_PROXD_SESSION_FLAG_ALL		= 0xffffffff
++
++};
++typedef uint32 wl_proxd_session_flags_t;
++
++/** time units - mc supports up to 0.1ns resolution */
++enum {
++	WL_PROXD_TMU_TU			= 0,		/**< 1024us */
++	WL_PROXD_TMU_SEC		= 1,
++	WL_PROXD_TMU_MILLI_SEC	= 2,
++	WL_PROXD_TMU_MICRO_SEC	= 3,
++	WL_PROXD_TMU_NANO_SEC	= 4,
++	WL_PROXD_TMU_PICO_SEC	= 5
++};
++typedef int16 wl_proxd_tmu_t;
++
++/** time interval e.g. 10ns */
++typedef struct wl_proxd_intvl {
++	uint32 intvl;
++	wl_proxd_tmu_t tmu;
++	uint8	pad[2];
++} wl_proxd_intvl_t;
++
++/** commands that can apply to proxd, method or a session */
++enum {
++	WL_PROXD_CMD_NONE				= 0,
++	WL_PROXD_CMD_GET_VERSION		= 1,
++	WL_PROXD_CMD_ENABLE 			= 2,
++	WL_PROXD_CMD_DISABLE 			= 3,
++	WL_PROXD_CMD_CONFIG 			= 4,
++	WL_PROXD_CMD_START_SESSION 		= 5,
++	WL_PROXD_CMD_BURST_REQUEST 		= 6,
++	WL_PROXD_CMD_STOP_SESSION 		= 7,
++	WL_PROXD_CMD_DELETE_SESSION 	= 8,
++	WL_PROXD_CMD_GET_RESULT 		= 9,
++	WL_PROXD_CMD_GET_INFO 			= 10,
++	WL_PROXD_CMD_GET_STATUS 		= 11,
++	WL_PROXD_CMD_GET_SESSIONS 		= 12,
++	WL_PROXD_CMD_GET_COUNTERS 		= 13,
++	WL_PROXD_CMD_CLEAR_COUNTERS 	= 14,
++	WL_PROXD_CMD_COLLECT 			= 15,	/* not supported, see 'wl proxd_collect' */
++	WL_PROXD_CMD_TUNE 			= 16,	/* not supported, see 'wl proxd_tune' */
++	WL_PROXD_CMD_DUMP 				= 17,
++	WL_PROXD_CMD_START_RANGING		= 18,
++	WL_PROXD_CMD_STOP_RANGING		= 19,
++	WL_PROXD_CMD_GET_RANGING_INFO	= 20,
++	WL_PROXD_CMD_IS_TLV_SUPPORTED	= 21,
++
++	WL_PROXD_CMD_MAX
++};
++typedef int16 wl_proxd_cmd_t;
++
++/* session ids:
++ * id 0 is reserved
++ * ids 1..0x7fff - allocated by host/app
++ * 0x8000-0xffff - allocated by firmware, used for auto/rx
++ */
++enum {
++	 WL_PROXD_SESSION_ID_GLOBAL = 0
++};
++
++/* Externally allocated sids */
++#define WL_PROXD_SID_EXT_MAX 0x7fff
++#define WL_PROXD_SID_EXT_ALLOC(_sid) ((_sid) > 0 && (_sid) <= WL_PROXD_SID_EXT_MAX)
++
++/* block size for reserved sid blocks */
++#define WL_PROXD_SID_EXT_BLKSZ 256
++#define WL_PROXD_SID_EXT_BLK_START(_i) (WL_PROXD_SID_EXT_MAX - (_i) * WL_PROXD_SID_EXT_BLKSZ + 1)
++#define WL_PROXD_SID_EXT_BLK_END(_start) ((_start) + WL_PROXD_SID_EXT_BLKSZ - 1)
++
++/* rrm block */
++#define WL_PROXD_SID_RRM_START WL_PROXD_SID_EXT_BLK_START(1)
++#define WL_PROXD_SID_RRM_END WL_PROXD_SID_EXT_BLK_END(WL_PROXD_SID_RRM_START)
++
++/* nan block */
++#define WL_PROXD_SID_NAN_START WL_PROXD_SID_EXT_BLK_START(2)
++#define WL_PROXD_SID_NAN_END WL_PROXD_SID_EXT_BLK_END(WL_PROXD_SID_NAN_START)
++
++/** maximum number sessions that can be allocated, may be less if tunable */
++#define WL_PROXD_MAX_SESSIONS 16
++
++typedef uint16 wl_proxd_session_id_t;
++
++/** status - TBD BCME_ vs proxd status - range reserved for BCME_ */
++enum {
++	WL_PROXD_E_NOAVAIL		= -1056,
++	WL_PROXD_E_EXT_SCHED		= -1055,
++	WL_PROXD_E_NOT_BCM			= -1054,
++	WL_PROXD_E_FRAME_TYPE		= -1053,
++	WL_PROXD_E_VERNOSUPPORT		= -1052,
++	WL_PROXD_E_SEC_NOKEY		= -1051,
++	WL_PROXD_E_SEC_POLICY		= -1050,
++	WL_PROXD_E_SCAN_INPROCESS	= -1049,
++	WL_PROXD_E_BAD_PARTIAL_TSF	= -1048,
++	WL_PROXD_E_SCANFAIL			= -1047,
++	WL_PROXD_E_NOTSF			= -1046,
++	WL_PROXD_E_POLICY			= -1045,
++	WL_PROXD_E_INCOMPLETE		= -1044,
++	WL_PROXD_E_OVERRIDDEN		= -1043,
++	WL_PROXD_E_ASAP_FAILED		= -1042,
++	WL_PROXD_E_NOTSTARTED		= -1041,
++	WL_PROXD_E_INVALIDMEAS		= -1040,
++	WL_PROXD_E_INCAPABLE		= -1039,
++	WL_PROXD_E_MISMATCH			= -1038,
++	WL_PROXD_E_DUP_SESSION		= -1037,
++	WL_PROXD_E_REMOTE_FAIL		= -1036,
++	WL_PROXD_E_REMOTE_INCAPABLE = -1035,
++	WL_PROXD_E_SCHED_FAIL		= -1034,
++	WL_PROXD_E_PROTO			= -1033,
++	WL_PROXD_E_EXPIRED			= -1032,
++	WL_PROXD_E_TIMEOUT			= -1031,
++	WL_PROXD_E_NOACK			= -1030,
++	WL_PROXD_E_DEFERRED			= -1029,
++	WL_PROXD_E_INVALID_SID		= -1028,
++	WL_PROXD_E_REMOTE_CANCEL 	= -1027,
++	WL_PROXD_E_CANCELED			= -1026,	/**< local */
++	WL_PROXD_E_INVALID_SESSION	= -1025,
++	WL_PROXD_E_BAD_STATE		= -1024,
++	WL_PROXD_E_ERROR			= -1,
++	WL_PROXD_E_OK				= 0
++};
++typedef int32 wl_proxd_status_t;
++
++/* proxd errors from phy */
++#define PROXD_TOF_INIT_ERR_BITS 16
++
++enum {
++	WL_PROXD_PHY_ERR_LB_CORR_THRESH    = (1 << 0), /* Loopback Correlation threshold */
++	WL_PROXD_PHY_ERR_RX_CORR_THRESH    = (1 << 1), /* Received Correlation threshold */
++	WL_PROXD_PHY_ERR_LB_PEAK_POWER     = (1 << 2), /* Loopback Peak power   */
++	WL_PROXD_PHY_ERR_RX_PEAK_POWER     = (1 << 3), /* Received Peak power   */
++	WL_PROXD_PHY_ERR_BITFLIP           = (1 << 4), /* Bitflips */
++	WL_PROXD_PHY_ERR_SNR               = (1 << 5), /* SNR */
++	WL_PROXD_PHY_RX_STRT_WIN_OFF       = (1 << 6), /* Receive start window is off */
++	WL_PROXD_PHY_RX_END_WIN_OFF        = (1 << 7), /* Receive End window is off */
++	WL_PROXD_PHY_ERR_LOW_CONFIDENCE    = (1 << 15), /* Low confidence on meas distance */
++};
++typedef uint32 wl_proxd_phy_error_t;
++
++/** session states */
++enum {
++	WL_PROXD_SESSION_STATE_NONE				= 0,
++	WL_PROXD_SESSION_STATE_CREATED			= 1,
++	WL_PROXD_SESSION_STATE_CONFIGURED		= 2,
++	WL_PROXD_SESSION_STATE_STARTED			= 3,
++	WL_PROXD_SESSION_STATE_DELAY			= 4,
++	WL_PROXD_SESSION_STATE_USER_WAIT		= 5,
++	WL_PROXD_SESSION_STATE_SCHED_WAIT		= 6,
++	WL_PROXD_SESSION_STATE_BURST			= 7,
++	WL_PROXD_SESSION_STATE_STOPPING			= 8,
++	WL_PROXD_SESSION_STATE_ENDED			= 9,
++	WL_PROXD_SESSION_STATE_START_WAIT		= 10,
++	WL_PROXD_SESSION_STATE_DESTROYING		= -1
++};
++typedef int16 wl_proxd_session_state_t;
++
++/** RTT sample flags */
++enum {
++	WL_PROXD_RTT_SAMPLE_NONE = 0x00,
++	WL_PROXD_RTT_SAMPLE_DISCARD	= 0x01
++};
++typedef uint8 wl_proxd_rtt_sample_flags_t;
++typedef int16 wl_proxd_rssi_t;
++typedef uint16 wl_proxd_snr_t;
++typedef uint16 wl_proxd_bitflips_t;
++
++typedef struct wl_proxd_rtt_sample {
++	uint8				id;			/**< id for the sample - non-zero */
++	wl_proxd_rtt_sample_flags_t	flags;
++	wl_proxd_rssi_t			rssi;
++	wl_proxd_intvl_t			rtt;		/**< round trip time */
++	uint32				ratespec;
++	wl_proxd_snr_t                  snr;
++	wl_proxd_bitflips_t             bitflips;
++	wl_proxd_status_t               status;
++	int32                           distance;
++	wl_proxd_phy_error_t		tof_phy_error;
++	wl_proxd_phy_error_t		tof_tgt_phy_error; /* target phy error bit map */
++	wl_proxd_snr_t                  tof_tgt_snr;
++	wl_proxd_bitflips_t             tof_tgt_bitflips;
++	uint8                           coreid;
++	uint8                           pad[3];
++} wl_proxd_rtt_sample_t;
++
++/** result flags */
++enum {
++	WL_PRXOD_RESULT_FLAG_NONE	= 0x0000,
++	WL_PROXD_RESULT_FLAG_NLOS	= 0x0001,	/**< LOS - if available */
++	WL_PROXD_RESULT_FLAG_LOS	= 0x0002,	/**< NLOS - if available */
++	WL_PROXD_RESULT_FLAG_FATAL	= 0x0004,	/**< Fatal error during burst */
++	WL_PROXD_RESULT_FLAG_VHTACK	= 0x0008,	/* VHTACK or Legacy ACK used */
++	WL_PROXD_REQUEST_SENT		= 0x0010,	/* FTM request was sent */
++	WL_PROXD_REQUEST_ACKED		= 0x0020,	/* FTM request was acked */
++	WL_PROXD_LTFSEQ_STARTED		= 0x0040,	/* LTF sequence started */
++	WL_PROXD_RESULT_FLAG_ALL 	= 0xffff
++};
++typedef int16 wl_proxd_result_flags_t;
++
++/** rtt measurement result */
++typedef struct wl_proxd_rtt_result {
++	wl_proxd_session_id_t		sid;
++	wl_proxd_result_flags_t		flags;
++	wl_proxd_status_t		status;
++	struct ether_addr		peer;
++	wl_proxd_session_state_t	state;		/**< current state */
++	union {
++		wl_proxd_intvl_t		retry_after;	/* hint for errors */
++		wl_proxd_intvl_t		burst_duration; /* burst duration */
++	} u;
++	wl_proxd_rtt_sample_t		avg_rtt;
++	uint32				avg_dist;	/* 1/256m units */
++	uint16				sd_rtt;		/* RTT standard deviation */
++	uint8				num_valid_rtt;	/* valid rtt cnt */
++	uint8				num_ftm;	/* actual num of ftm cnt (Configured) */
++	uint16				burst_num;	/* in a session */
++	uint16				num_rtt;	/* 0 if no detail */
++	uint16				num_meas;	/* number of ftm frames seen OTA */
++	uint8                           pad[2];
++	wl_proxd_rtt_sample_t		rtt[1];		/* variable */
++} wl_proxd_rtt_result_t;
++
++/** aoa measurement result */
++typedef struct wl_proxd_aoa_result {
++	wl_proxd_session_id_t			sid;
++	wl_proxd_result_flags_t			flags;
++	wl_proxd_status_t				status;
++	struct ether_addr				peer;
++	wl_proxd_session_state_t		state;
++	uint16							burst_num;
++	uint8							pad[2];
++	/* wl_proxd_aoa_sample_t sample_avg; TBD */
++} BWL_POST_PACKED_STRUCT wl_proxd_aoa_result_t;
++#include <packed_section_end.h>
++
++/** global stats */
++typedef struct wl_proxd_counters {
++	uint32 tx;					/**< tx frame count */
++	uint32 rx;					/**< rx frame count */
++	uint32 burst;				/**< total number of burst */
++	uint32 sessions;			/**< total number of sessions */
++	uint32 max_sessions;		/**< max concurrency */
++	uint32 sched_fail;			/**< scheduling failures */
++	uint32 timeouts;			/**< timeouts */
++	uint32 protoerr;			/**< protocol errors */
++	uint32 noack;				/**< tx w/o ack */
++	uint32 txfail;				/**< any tx falure */
++	uint32 lci_req_tx;			/**< tx LCI requests */
++	uint32 lci_req_rx;			/**< rx LCI requests */
++	uint32 lci_rep_tx;			/**< tx LCI reports */
++	uint32 lci_rep_rx;			/**< rx LCI reports */
++	uint32 civic_req_tx;		/**< tx civic requests */
++	uint32 civic_req_rx;		/**< rx civic requests */
++	uint32 civic_rep_tx;		/**< tx civic reports */
++	uint32 civic_rep_rx;		/**< rx civic reports */
++	uint32 rctx;				/**< ranging contexts created */
++	uint32 rctx_done;			/**< count of ranging done */
++	uint32 publish_err;     /**< availability publishing errors */
++	uint32 on_chan;         /**< count of scheduler onchan */
++	uint32 off_chan;        /**< count of scheduler offchan */
++	uint32 tsf_lo;          /* local tsf or session tsf */
++	uint32 tsf_hi;
++	uint32 num_meas;
++} wl_proxd_counters_t;
++
++typedef struct wl_proxd_counters wl_proxd_session_counters_t;
++
++enum {
++	WL_PROXD_CAP_NONE 		= 0x0000,
++	WL_PROXD_CAP_ALL 		= 0xffff
++};
++typedef int16 wl_proxd_caps_t;
++
++/** method capabilities */
++enum {
++	WL_PROXD_FTM_CAP_NONE = 0x0000,
++	WL_PROXD_FTM_CAP_FTM1 = 0x0001
++};
++typedef uint16 wl_proxd_ftm_caps_t;
++
++typedef struct wl_proxd_tlv_id_list {
++	uint16			num_ids;
++	uint16			ids[1];
++} wl_proxd_tlv_id_list_t;
++
++typedef struct wl_proxd_session_id_list {
++	uint16 num_ids;
++	wl_proxd_session_id_t ids[1];
++} wl_proxd_session_id_list_t;
++
++typedef struct wl_proxd_tpk {
++	struct ether_addr	peer;
++	uint8 tpk[TPK_FTM_LEN];
++} wl_proxd_tpk_t;
++
++/* tlvs returned for get_info on ftm method
++ *	configuration:
++ *	proxd flags
++ *	event mask
++ *	debug mask
++ *	session defaults (session tlvs)
++ * status tlv - not supported for ftm method
++ * info tlv
++ */
++typedef struct wl_proxd_ftm_info {
++	wl_proxd_ftm_caps_t caps;
++	uint16 max_sessions;
++	uint16 num_sessions;
++	uint16 rx_max_burst;
++} wl_proxd_ftm_info_t;
++
++enum {
++	WL_PROXD_WAIT_NONE  = 0x0000,
++	WL_PROXD_WAIT_KEY	= 0x0001,
++	WL_PROXD_WAIT_SCHED	= 0x0002,
++	WL_PROXD_WAIT_TSF	= 0x0004
++};
++typedef int16 wl_proxd_wait_reason_t;
++
++/* tlvs returned for get_info on session
++ * session config (tlvs)
++ * session info tlv
++ */
++typedef struct wl_proxd_ftm_session_info {
++	uint16 sid;
++	uint8 bss_index;
++	uint8 pad;
++	struct ether_addr bssid;
++	wl_proxd_session_state_t state;
++	wl_proxd_status_t status;
++	uint16	burst_num;
++	wl_proxd_wait_reason_t wait_reason;
++	uint32	meas_start_lo; /* sn tsf of 1st meas for cur/prev burst */
++	uint32	meas_start_hi;
++} wl_proxd_ftm_session_info_t;
++
++typedef struct wl_proxd_ftm_session_status {
++	uint16 sid;
++	wl_proxd_session_state_t state;
++	wl_proxd_status_t status;
++	uint16	burst_num;
++	uint16	pad;
++} wl_proxd_ftm_session_status_t;
++
++/** rrm range request */
++typedef struct wl_proxd_range_req {
++	uint16 			num_repeat;
++	uint16			init_delay_range;	/**< in TUs */
++	uint8			pad;
++	uint8			num_nbr;		/**< number of (possible) neighbors */
++	nbr_element_t		nbr[1];
++} wl_proxd_range_req_t;
++
++#define WL_PROXD_LCI_LAT_OFF 	0
++#define WL_PROXD_LCI_LONG_OFF 	5
++#define WL_PROXD_LCI_ALT_OFF 	10
++
++#define WL_PROXD_LCI_GET_LAT(_lci, _lat, _lat_err) { \
++	unsigned _off = WL_PROXD_LCI_LAT_OFF; \
++	_lat_err = (_lci)->data[(_off)] & 0x3f; \
++	_lat = (_lci)->data[(_off)+1]; \
++	_lat |= (_lci)->data[(_off)+2] << 8; \
++	_lat |= (_lci)->data[_(_off)+3] << 16; \
++	_lat |= (_lci)->data[(_off)+4] << 24; \
++	_lat <<= 2; \
++	_lat |= (_lci)->data[(_off)] >> 6; \
++}
++
++#define WL_PROXD_LCI_GET_LONG(_lci, _lcilong, _long_err) { \
++	unsigned _off = WL_PROXD_LCI_LONG_OFF; \
++	_long_err = (_lci)->data[(_off)] & 0x3f; \
++	_lcilong = (_lci)->data[(_off)+1]; \
++	_lcilong |= (_lci)->data[(_off)+2] << 8; \
++	_lcilong |= (_lci)->data[_(_off)+3] << 16; \
++	_lcilong |= (_lci)->data[(_off)+4] << 24; \
++	__lcilong <<= 2; \
++	_lcilong |= (_lci)->data[(_off)] >> 6; \
++}
++
++#define WL_PROXD_LCI_GET_ALT(_lci, _alt_type, _alt, _alt_err) { \
++	unsigned _off = WL_PROXD_LCI_ALT_OFF; \
++	_alt_type = (_lci)->data[_off] & 0x0f; \
++	_alt_err = (_lci)->data[(_off)] >> 4; \
++	_alt_err |= ((_lci)->data[(_off)+1] & 0x03) << 4; \
++	_alt = (_lci)->data[(_off)+2]; \
++	_alt |= (_lci)->data[(_off)+3] << 8; \
++	_alt |= (_lci)->data[_(_off)+4] << 16; \
++	_alt <<= 6; \
++	_alt |= (_lci)->data[(_off) + 1] >> 2; \
++}
++
++#define WL_PROXD_LCI_VERSION(_lci) ((_lci)->data[15] >> 6)
++
++/* availability. advertising mechanism bss specific */
++/** availablity flags */
++enum {
++	WL_PROXD_AVAIL_NONE = 0,
++	WL_PROXD_AVAIL_NAN_PUBLISHED = 0x0001,
++	WL_PROXD_AVAIL_SCHEDULED = 0x0002        /**< scheduled by proxd */
++};
++typedef int16 wl_proxd_avail_flags_t;
++
++/** time reference */
++enum {
++	WL_PROXD_TREF_NONE = 0,
++	WL_PROXD_TREF_DEV_TSF = 1,
++	WL_PROXD_TREF_NAN_DW = 2,
++	WL_PROXD_TREF_TBTT = 3,
++	WL_PROXD_TREF_MAX		/* last entry */
++};
++typedef int16 wl_proxd_time_ref_t;
++
++/** proxd channel-time slot */
++typedef struct {
++	wl_proxd_intvl_t start;         /**< from ref */
++	wl_proxd_intvl_t duration;      /**< from start */
++	uint32  chanspec;
++} wl_proxd_time_slot_t;
++
++typedef struct wl_proxd_avail24 {
++	wl_proxd_avail_flags_t flags; /**< for query only */
++	wl_proxd_time_ref_t time_ref;
++	uint16	max_slots; /**< for query only */
++	uint16  num_slots;
++	wl_proxd_time_slot_t slots[1];	/**< ROM compat - not used */
++	wl_proxd_intvl_t 	repeat;
++	wl_proxd_time_slot_t ts0[1];
++} wl_proxd_avail24_t;
++#define WL_PROXD_AVAIL24_TIMESLOT(_avail24, _i) (&(_avail24)->ts0[(_i)])
++#define WL_PROXD_AVAIL24_TIMESLOT_OFFSET(_avail24) OFFSETOF(wl_proxd_avail24_t, ts0)
++#define WL_PROXD_AVAIL24_TIMESLOTS(_avail24) WL_PROXD_AVAIL24_TIMESLOT(_avail24, 0)
++#define WL_PROXD_AVAIL24_SIZE(_avail24, _num_slots) (\
++	WL_PROXD_AVAIL24_TIMESLOT_OFFSET(_avail24) + \
++	(_num_slots) * sizeof(*WL_PROXD_AVAIL24_TIMESLOT(_avail24, 0)))
++
++typedef struct wl_proxd_avail {
++	wl_proxd_avail_flags_t flags; /**< for query only */
++	wl_proxd_time_ref_t time_ref;
++	uint16	max_slots; /**< for query only */
++	uint16  num_slots;
++	wl_proxd_intvl_t 	repeat;
++	wl_proxd_time_slot_t slots[1];
++} wl_proxd_avail_t;
++#define WL_PROXD_AVAIL_TIMESLOT(_avail, _i) (&(_avail)->slots[(_i)])
++#define WL_PROXD_AVAIL_TIMESLOT_OFFSET(_avail) OFFSETOF(wl_proxd_avail_t, slots)
++
++#define WL_PROXD_AVAIL_TIMESLOTS(_avail) WL_PROXD_AVAIL_TIMESLOT(_avail, 0)
++#define WL_PROXD_AVAIL_SIZE(_avail, _num_slots) (\
++	WL_PROXD_AVAIL_TIMESLOT_OFFSET(_avail) + \
++	(_num_slots) * sizeof(*WL_PROXD_AVAIL_TIMESLOT(_avail, 0)))
++
++/* collect support TBD */
++
++/** debugging */
++enum {
++	WL_PROXD_DEBUG_NONE		= 0x00000000,
++	WL_PROXD_DEBUG_LOG		= 0x00000001,
++	WL_PROXD_DEBUG_IOV		= 0x00000002,
++	WL_PROXD_DEBUG_EVENT		= 0x00000004,
++	WL_PROXD_DEBUG_SESSION		= 0x00000008,
++	WL_PROXD_DEBUG_PROTO		= 0x00000010,
++	WL_PROXD_DEBUG_SCHED		= 0x00000020,
++	WL_PROXD_DEBUG_RANGING		= 0x00000040,
++	WL_PROXD_DEBUG_NAN		= 0x00000080,
++	WL_PROXD_DEBUG_PKT		= 0x00000100,
++	WL_PROXD_DEBUG_SEC		= 0x00000200,
++	WL_PROXD_DEBUG_EVENTLOG		= 0x80000000,	/* map/enable EVNET_LOG_TAG_PROXD_INFO */
++	WL_PROXD_DEBUG_ALL		= 0xffffffff
++};
++typedef uint32 wl_proxd_debug_mask_t;
++
++/** tlv IDs - data length 4 bytes unless overridden by type, alignment 32 bits */
++enum {
++	WL_PROXD_TLV_ID_NONE			= 0,
++	WL_PROXD_TLV_ID_METHOD			= 1,
++	WL_PROXD_TLV_ID_FLAGS			= 2,
++	WL_PROXD_TLV_ID_CHANSPEC		= 3,	/**< note: uint32 */
++	WL_PROXD_TLV_ID_TX_POWER		= 4,
++	WL_PROXD_TLV_ID_RATESPEC		= 5,
++	WL_PROXD_TLV_ID_BURST_DURATION		= 6,	/**< intvl - length of burst */
++	WL_PROXD_TLV_ID_BURST_PERIOD		= 7,	/**< intvl - between bursts */
++	WL_PROXD_TLV_ID_BURST_FTM_SEP		= 8,	/**< intvl - between FTMs */
++	WL_PROXD_TLV_ID_BURST_NUM_FTM		= 9,	/**< uint16 - per burst */
++	WL_PROXD_TLV_ID_NUM_BURST		= 10,	/**< uint16 */
++	WL_PROXD_TLV_ID_FTM_RETRIES		= 11,	/**< uint16 at FTM level */
++	WL_PROXD_TLV_ID_BSS_INDEX		= 12,	/**< uint8 */
++	WL_PROXD_TLV_ID_BSSID			= 13,
++	WL_PROXD_TLV_ID_INIT_DELAY		= 14,	/**< intvl - optional,non-standalone only */
++	WL_PROXD_TLV_ID_BURST_TIMEOUT		= 15,	/**< expect response within - intvl */
++	WL_PROXD_TLV_ID_EVENT_MASK		= 16,	/**< interested events - in/out */
++	WL_PROXD_TLV_ID_FLAGS_MASK		= 17,	/**< interested flags - in only */
++	WL_PROXD_TLV_ID_PEER_MAC		= 18,	/**< mac address of peer */
++	WL_PROXD_TLV_ID_FTM_REQ			= 19,	/**< dot11_ftm_req */
++	WL_PROXD_TLV_ID_LCI_REQ			= 20,
++	WL_PROXD_TLV_ID_LCI			= 21,
++	WL_PROXD_TLV_ID_CIVIC_REQ		= 22,
++	WL_PROXD_TLV_ID_CIVIC			= 23,
++	WL_PROXD_TLV_ID_AVAIL24			= 24,	/**< ROM compatibility */
++	WL_PROXD_TLV_ID_SESSION_FLAGS		= 25,
++	WL_PROXD_TLV_ID_SESSION_FLAGS_MASK	= 26,	/**< in only */
++	WL_PROXD_TLV_ID_RX_MAX_BURST		= 27,	/**< uint16 - limit bursts per session */
++	WL_PROXD_TLV_ID_RANGING_INFO		= 28,	/**< ranging info */
++	WL_PROXD_TLV_ID_RANGING_FLAGS		= 29,	/**< uint16 */
++	WL_PROXD_TLV_ID_RANGING_FLAGS_MASK	= 30,	/**< uint16, in only */
++	WL_PROXD_TLV_ID_NAN_MAP_ID		= 31,
++	WL_PROXD_TLV_ID_DEV_ADDR		= 32,
++	WL_PROXD_TLV_ID_AVAIL			= 33,	/**< wl_proxd_avail_t  */
++	WL_PROXD_TLV_ID_TLV_ID			= 34,	/* uint16 tlv-id */
++	WL_PROXD_TLV_ID_FTM_REQ_RETRIES		= 35,	/* uint16 FTM request retries */
++	WL_PROXD_TLV_ID_TPK			= 36,	/* 32byte TPK  */
++	WL_PROXD_TLV_ID_RI_RR			= 36,	/* RI_RR */
++	WL_PROXD_TLV_ID_TUNE			= 37,	/* wl_proxd_pararms_tof_tune_t */
++
++	/* output - 512 + x */
++	WL_PROXD_TLV_ID_STATUS			= 512,
++	WL_PROXD_TLV_ID_COUNTERS		= 513,
++	WL_PROXD_TLV_ID_INFO			= 514,
++	WL_PROXD_TLV_ID_RTT_RESULT		= 515,
++	WL_PROXD_TLV_ID_AOA_RESULT		= 516,
++	WL_PROXD_TLV_ID_SESSION_INFO		= 517,
++	WL_PROXD_TLV_ID_SESSION_STATUS		= 518,
++	WL_PROXD_TLV_ID_SESSION_ID_LIST		= 519,
++
++	/* debug tlvs can be added starting 1024 */
++	WL_PROXD_TLV_ID_DEBUG_MASK		= 1024,
++	WL_PROXD_TLV_ID_COLLECT			= 1025,	/**< output only */
++	WL_PROXD_TLV_ID_STRBUF			= 1026,
++
++	WL_PROXD_TLV_ID_COLLECT_HEADER		= 1025,	/* wl_proxd_collect_header_t */
++	WL_PROXD_TLV_ID_COLLECT_INFO		= 1028,	/* wl_proxd_collect_info_t */
++	WL_PROXD_TLV_ID_COLLECT_DATA		= 1029,	/* wl_proxd_collect_data_t */
++	WL_PROXD_TLV_ID_COLLECT_CHAN_DATA	= 1030,	/* wl_proxd_collect_data_t */
++
++	WL_PROXD_TLV_ID_MAX
++};
++
++typedef struct wl_proxd_tlv {
++	uint16 id;
++	uint16 len;
++	uint8  data[1];
++} wl_proxd_tlv_t;
++
++/** proxd iovar - applies to proxd, method or session */
++typedef struct wl_proxd_iov {
++	uint16                  version;
++	uint16                  len;
++	wl_proxd_cmd_t          cmd;
++	wl_proxd_method_t       method;
++	wl_proxd_session_id_t   sid;
++	uint8                   PAD[2];
++	wl_proxd_tlv_t          tlvs[1];	/**< variable */
++} wl_proxd_iov_t;
++
++#define WL_PROXD_IOV_HDR_SIZE OFFSETOF(wl_proxd_iov_t, tlvs)
++
++/* The following event definitions may move to bcmevent.h, but sharing proxd types
++ * across needs more invasive changes unrelated to proxd
++ */
++enum {
++	WL_PROXD_EVENT_NONE			= 0,	/**< not an event, reserved */
++	WL_PROXD_EVENT_SESSION_CREATE		= 1,
++	WL_PROXD_EVENT_SESSION_START		= 2,
++	WL_PROXD_EVENT_FTM_REQ			= 3,
++	WL_PROXD_EVENT_BURST_START		= 4,
++	WL_PROXD_EVENT_BURST_END		= 5,
++	WL_PROXD_EVENT_SESSION_END		= 6,
++	WL_PROXD_EVENT_SESSION_RESTART		= 7,
++	WL_PROXD_EVENT_BURST_RESCHED		= 8,	/**< burst rescheduled-e.g. partial TSF */
++	WL_PROXD_EVENT_SESSION_DESTROY		= 9,
++	WL_PROXD_EVENT_RANGE_REQ		= 10,
++	WL_PROXD_EVENT_FTM_FRAME		= 11,
++	WL_PROXD_EVENT_DELAY			= 12,
++	WL_PROXD_EVENT_VS_INITIATOR_RPT		= 13,	/**< (target) rx initiator-report */
++	WL_PROXD_EVENT_RANGING			= 14,
++	WL_PROXD_EVENT_LCI_MEAS_REP		= 15,	/* LCI measurement report */
++	WL_PROXD_EVENT_CIVIC_MEAS_REP		= 16,	/* civic measurement report */
++	WL_PROXD_EVENT_COLLECT			= 17,
++	WL_PROXD_EVENT_START_WAIT		= 18,	/* waiting to start */
++
++	WL_PROXD_EVENT_MAX
++};
++typedef int16 wl_proxd_event_type_t;
++
++/** proxd event mask - upto 32 events for now */
++typedef uint32 wl_proxd_event_mask_t;
++
++#define WL_PROXD_EVENT_MASK_ALL 0xfffffffe
++#define WL_PROXD_EVENT_MASK_EVENT(_event_type) (1 << (_event_type))
++#define WL_PROXD_EVENT_ENABLED(_mask, _event_type) (\
++	((_mask) & WL_PROXD_EVENT_MASK_EVENT(_event_type)) != 0)
++
++/** proxd event - applies to proxd, method or session */
++typedef struct wl_proxd_event {
++	uint16					version;
++	uint16					len;
++	wl_proxd_event_type_t 	type;
++	wl_proxd_method_t 		method;
++	wl_proxd_session_id_t 	sid;
++	uint8					pad[2];
++	wl_proxd_tlv_t 			tlvs[1];	/**< variable */
++} wl_proxd_event_t;
++
++enum {
++	WL_PROXD_RANGING_STATE_NONE = 0,
++	WL_PROXD_RANGING_STATE_NOTSTARTED = 1,
++	WL_PROXD_RANGING_STATE_INPROGRESS = 2,
++	WL_PROXD_RANGING_STATE_DONE = 3
++};
++typedef int16 wl_proxd_ranging_state_t;
++
++/** proxd ranging flags */
++enum {
++	WL_PROXD_RANGING_FLAG_NONE = 0x0000,  /**< no flags */
++	WL_PROXD_RANGING_FLAG_DEL_SESSIONS_ON_STOP = 0x0001,
++	WL_PROXD_RANGING_FLAG_ALL = 0xffff
++};
++typedef uint16 wl_proxd_ranging_flags_t;
++
++struct wl_proxd_ranging_info {
++	wl_proxd_status_t   status;
++	wl_proxd_ranging_state_t state;
++	wl_proxd_ranging_flags_t flags;
++	uint16	num_sids;
++	uint16	num_done;
++};
++typedef struct wl_proxd_ranging_info wl_proxd_ranging_info_t;
++
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct wl_proxd_collect_event_data {
++	uint32                  H_LB[K_TOF_COLLECT_H_SIZE_20MHZ];
++	uint32                  H_RX[K_TOF_COLLECT_H_SIZE_20MHZ];
++	uint8                   ri_rr[FTM_TPK_LEN];
++	wl_proxd_phy_error_t    phy_err_mask;
++} BWL_POST_PACKED_STRUCT wl_proxd_collect_event_data_t;
++#include <packed_section_end.h>
++
++/** Data returned by the bssload_report iovar. This is also the WLC_E_BSS_LOAD event data */
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct wl_bssload {
++	uint16 sta_count;		/**< station count */
++	uint16 aac;			/**< available admission capacity */
++	uint8 chan_util;		/**< channel utilization */
++} BWL_POST_PACKED_STRUCT wl_bssload_t;
++#include <packed_section_end.h>
++
++/**
++ * Maximum number of configurable BSS Load levels.  The number of BSS Load
++ * ranges is always 1 more than the number of configured levels.  eg. if
++ * 3 levels of 10, 20, 30 are configured then this defines 4 load ranges:
++ * 0-10, 11-20, 21-30, 31-255.  A WLC_E_BSS_LOAD event is generated each time
++ * the utilization level crosses into another range, subject to the rate limit.
++ */
++#define MAX_BSSLOAD_LEVELS 8
++#define MAX_BSSLOAD_RANGES (MAX_BSSLOAD_LEVELS + 1)
++
++/** BSS Load event notification configuration. */
++typedef struct wl_bssload_cfg {
++	uint32 rate_limit_msec;	/**< # of events posted to application will be limited to
++				 * one per specified period (0 to disable rate limit).
++				 */
++	uint8 num_util_levels;	/**< Number of entries in util_levels[] below */
++	uint8 util_levels[MAX_BSSLOAD_LEVELS];
++				/**< Variable number of BSS Load utilization levels in
++				 * low to high order.  An event will be posted each time
++				 * a received beacon's BSS Load IE channel utilization
++				 * value crosses a level.
++				 */
++	uint8 PAD[3];
++} wl_bssload_cfg_t;
++
++/** Multiple roaming profile suport */
++#define WL_MAX_ROAM_PROF_BRACKETS	4
++
++#define WL_ROAM_PROF_VER_0	0
++#define WL_ROAM_PROF_VER_1	1
++#define WL_MAX_ROAM_PROF_VER	WL_ROAM_PROF_VER_1
++
++#define WL_ROAM_PROF_NONE	(0 << 0)
++#define WL_ROAM_PROF_LAZY	(1 << 0)
++#define WL_ROAM_PROF_NO_CI	(1 << 1)
++#define WL_ROAM_PROF_SUSPEND	(1 << 2)
++#define WL_ROAM_PROF_SYNC_DTIM	(1 << 6)
++#define WL_ROAM_PROF_DEFAULT	(1 << 7)	/**< backward compatible single default profile */
++
++#define WL_FACTOR_TABLE_MAX_LIMIT 5
++
++#define WL_CU_2G_ROAM_TRIGGER (-60)
++#define WL_CU_5G_ROAM_TRIGGER (-70)
++
++#define WL_CU_SCORE_DELTA_DEFAULT 20
++
++#define WL_MAX_CHANNEL_USAGE 0x0FF
++#define WL_CU_PERCENTAGE_DISABLE 0
++#define WL_CU_PERCENTAGE_DEFAULT 70
++#define WL_CU_PERCENTAGE_MAX 100
++#define WL_CU_CALC_DURATION_DEFAULT 10 /* seconds */
++#define WL_CU_CALC_DURATION_MAX 60 /* seconds */
++
++typedef struct wl_roam_prof_v2 {
++	int8	roam_flags;		/**< bit flags */
++	int8	roam_trigger;		/**< RSSI trigger level per profile/RSSI bracket */
++	int8	rssi_lower;
++	int8	roam_delta;
++
++	/* if channel_usage if zero, roam_delta is rssi delta required for new AP */
++	/* if channel_usage if non-zero, roam_delta is score delta(%) required for new AP */
++	int8	rssi_boost_thresh;	/**< Min RSSI to qualify for RSSI boost */
++	int8	rssi_boost_delta;	/**< RSSI boost for AP in the other band */
++	uint16	nfscan;			/**< number of full scan to start with */
++	uint16	fullscan_period;
++	uint16	init_scan_period;
++	uint16	backoff_multiplier;
++	uint16	max_scan_period;
++	uint8	channel_usage;
++	uint8	cu_avg_calc_dur;
++	uint8	pad[2];
++} wl_roam_prof_v2_t;
++
++typedef struct wl_roam_prof_v1 {
++	int8	roam_flags;		/**< bit flags */
++	int8	roam_trigger;		/**< RSSI trigger level per profile/RSSI bracket */
++	int8	rssi_lower;
++	int8	roam_delta;
++
++	/* if channel_usage if zero, roam_delta is rssi delta required for new AP */
++	/* if channel_usage if non-zero, roam_delta is score delta(%) required for new AP */
++	int8	rssi_boost_thresh;	/**< Min RSSI to qualify for RSSI boost */
++	int8	rssi_boost_delta;	/**< RSSI boost for AP in the other band */
++	uint16	nfscan;			/**< number of full scan to start with */
++	uint16	fullscan_period;
++	uint16	init_scan_period;
++	uint16	backoff_multiplier;
++	uint16	max_scan_period;
++} wl_roam_prof_v1_t;
++
++typedef struct wl_roam_prof_band_v2 {
++	uint32	band;			/**< Must be just one band */
++	uint16	ver;			/**< version of this struct */
++	uint16	len;			/**< length in bytes of this structure */
++	wl_roam_prof_v2_t roam_prof[WL_MAX_ROAM_PROF_BRACKETS];
++} wl_roam_prof_band_v2_t;
++
++typedef struct wl_roam_prof_band_v1 {
++	uint32	band;			/**< Must be just one band */
++	uint16	ver;			/**< version of this struct */
++	uint16	len;			/**< length in bytes of this structure */
++	wl_roam_prof_v1_t roam_prof[WL_MAX_ROAM_PROF_BRACKETS];
++} wl_roam_prof_band_v1_t;
++
++#define BSS_MAXTABLE_SIZE 10
++#define WNM_BSS_SELECT_FACTOR_VERSION   1
++typedef struct wnm_bss_select_factor_params {
++	uint8 low;
++	uint8 high;
++	uint8 factor;
++	uint8 pad;
++} wnm_bss_select_factor_params_t;
++
++#define WNM_BSS_SELECT_FIXED_SIZE OFFSETOF(wnm_bss_select_factor_cfg_t, params)
++typedef struct wnm_bss_select_factor_cfg {
++	uint8 version;
++	uint8 band;
++	uint16 type;
++	uint16 pad;
++	uint16 count;
++	wnm_bss_select_factor_params_t params[1];
++} wnm_bss_select_factor_cfg_t;
++
++#define WNM_BSS_SELECT_WEIGHT_VERSION   1
++typedef struct wnm_bss_select_weight_cfg {
++	uint8 version;
++	uint8 band;
++	uint16 type;
++	uint16 weight; /* weightage for each type between 0 to 100 */
++} wnm_bss_select_weight_cfg_t;
++
++#define WNM_BSS_SELECT_TYPE_RSSI   0
++#define WNM_BSS_SELECT_TYPE_CU   1
++
++#define WNM_BSSLOAD_MONITOR_VERSION   1
++typedef struct wnm_bssload_monitor_cfg {
++	uint8 version;
++	uint8 band;
++	uint8 duration; /* duration between 1 to 20sec */
++} wnm_bssload_monitor_cfg_t;
++
++#define WNM_ROAM_TRIGGER_VERSION   1
++typedef struct wnm_roam_trigger_cfg {
++	uint8 version;
++	uint8 band;
++	uint16 type;
++	int16 trigger; /* trigger for each type in new roam algorithm */
++} wnm_roam_trigger_cfg_t;
++
++/* Data structures for Interface Create/Remove  */
++
++#define WL_INTERFACE_CREATE_VER	(0)
++#define WL_INTERFACE_CREATE_VER_1	1
++#define WL_INTERFACE_CREATE_VER_2	2
++#define WL_INTERFACE_CREATE_VER_3	3
++
++/*
++ * The flags filed of the wl_interface_create is designed to be
++ * a Bit Mask. As of now only Bit 0 and Bit 1 are used as mentioned below.
++ * The rest of the bits can be used, incase we have to provide
++ * more information to the dongle
++ */
++
++/*
++ * Bit 0 of flags field is used to inform whether the interface requested to
++ * be created is STA or AP.
++ * 0 - Create a STA interface
++ * 1 - Create an AP interface
++ * NOTE: This Bit 0 is applicable for the WL_INTERFACE_CREATE_VER < 2
++ */
++#define WL_INTERFACE_CREATE_STA	(0 << 0)
++#define WL_INTERFACE_CREATE_AP	(1 << 0)
++
++/*
++ * From revision >= 2 Bit 0 of flags field will not used be for STA or AP interface creation.
++ * "iftype" field shall be used for identifying the interface type.
++ */
++typedef enum wl_interface_type {
++	WL_INTERFACE_TYPE_STA = 0,
++	WL_INTERFACE_TYPE_AP = 1,
++	WL_INTERFACE_TYPE_AWDL = 2,
++	WL_INTERFACE_TYPE_NAN = 3,
++	WL_INTERFACE_TYPE_MAX
++} wl_interface_type_t;
++
++/*
++ * Bit 1 of flags field is used to inform whether MAC is present in the
++ * data structure or not.
++ * 0 - Ignore mac_addr field
++ * 1 - Use the mac_addr field
++ */
++#define WL_INTERFACE_MAC_DONT_USE	(0 << 1)
++#define WL_INTERFACE_MAC_USE		(1 << 1)
++
++/*
++ * Bit 2 of flags field is used to inform whether core or wlc index
++ * is present in the data structure or not.
++ * 0 - Ignore wlc_index field
++ * 1 - Use the wlc_index field
++ */
++#define WL_INTERFACE_WLC_INDEX_DONT_USE	(0 << 2)
++#define WL_INTERFACE_WLC_INDEX_USE	(1 << 2)
++
++/*
++ * Bit 3 of flags field is used to create interface on the host requested interface index
++ * 0 - Ignore if_index field
++ * 1 - Use the if_index field
++ */
++#define WL_INTERFACE_IF_INDEX_USE       (1 << 3)
++
++/*
++ * Bit 4 of flags field is used to assign BSSID
++ * 0 - Ignore bssid field
++ * 1 - Use the bssid field
++ */
++#define WL_INTERFACE_BSSID_INDEX_USE	(1 << 4)
++
++#ifdef WLMESH
++typedef struct wl_interface_info {
++    uint16  ver;            /* version of this struct */
++    struct ether_addr    mac_addr;  /* MAC address of the interface */
++    char    ifname[BCM_MSG_IFNAME_MAX]; /* name of interface */
++    uint8   bsscfgidx;      /* source bsscfg index */
++} wl_interface_info_t;
++#endif
++
++typedef struct wl_interface_create {
++	uint16	ver;			/* version of this struct */
++	uint32  flags;			/* flags that defines the operation */
++	struct	ether_addr   mac_addr;	/* Optional Mac address */
++} wl_interface_create_t;
++
++typedef struct wl_interface_create_v1 {
++	uint16  ver;                    /**< version of this struct */
++	uint8   pad1[2];                /**< Padding bytes */
++	uint32  flags;                  /**< flags that defines the operation */
++	struct  ether_addr   mac_addr;  /**< Optional Mac address */
++	uint8   pad2[2];                /**< Padding bytes */
++	uint32  wlc_index;              /**< Optional wlc index */
++} wl_interface_create_v1_t;
++
++typedef struct wl_interface_create_v2 {
++	uint16  ver;                    /**< version of this struct */
++	uint8   pad1[2];                /**< Padding bytes */
++	uint32  flags;                  /**< flags that defines the operation */
++	struct  ether_addr   mac_addr;  /**< Optional Mac address */
++	uint8   iftype;                 /**< Type of interface created */
++	uint8   pad2;                   /**< Padding bytes */
++	uint32  wlc_index;              /**< Optional wlc index */
++} wl_interface_create_v2_t;
++
++typedef struct wl_interface_create_v3 {
++	uint16	ver;			/**< version of this struct */
++	uint16	len;			/**< length of whole structure including variable length */
++	uint16	fixed_len;		/**< Fixed length of this structure excluding data[] */
++	uint8	iftype;			/**< Type of interface created */
++	uint8	wlc_index;		/**< Optional wlc index */
++	uint32  flags;			/**< flags that defines the operation */
++	struct	ether_addr   mac_addr;	/**< Optional Mac address */
++	struct	ether_addr   bssid;	/**< Optional BSSID */
++	uint8	if_index;		/**< interface index requested by Host */
++	uint8	pad[3];			/**< Padding bytes to ensure data[] is at 32 bit aligned */
++	uint8	data[];			/**< Optional application/Module specific data */
++} wl_interface_create_v3_t;
++
++#define WL_INTERFACE_INFO_VER_1		1
++#define WL_INTERFACE_INFO_VER_2		2
++
++typedef struct wl_interface_info_v1 {
++	uint16  ver;                    /**< version of this struct */
++	struct ether_addr    mac_addr;  /**< MAC address of the interface */
++	char    ifname[BCM_MSG_IFNAME_MAX]; /**< name of interface */
++	uint8   bsscfgidx;              /**< source bsscfg index */
++	uint8	PAD;
++} wl_interface_info_v1_t;
++
++typedef struct wl_interface_info_v2 {
++	uint16                  ver;                    /**< version of this struct */
++	uint16                  length;                 /**< length of the whole structure */
++	struct  ether_addr      mac_addr;               /**< MAC address of the interface */
++	uint8                   bsscfgidx;              /**< source bsscfg index */
++	uint8                   if_index;               /**< Interface index allocated by FW */
++	char                    ifname[BCM_MSG_IFNAME_MAX]; /**< name of interface */
++} wl_interface_info_v2_t;
++
++#define PHY_RXIQEST_AVERAGING_DELAY 10
++
++typedef struct wl_iqest_params {
++	uint32 rxiq;
++	uint8 niter;
++	uint8 delay;
++	uint8 PAD[2];
++} wl_iqest_params_t;
++
++typedef struct wl_iqest_sweep_params {
++	wl_iqest_params_t params;
++	uint8 nchannels;
++	uint8 channel[3];	/** variable */
++} wl_iqest_sweep_params_t;
++
++typedef struct wl_iqest_value {
++	uint8 channel;
++	uint8 PAD[3];
++	uint32 rxiq;
++} wl_iqest_value_t;
++
++typedef struct wl_iqest_result {
++	uint8 nvalues;
++	uint8 PAD[3];
++	wl_iqest_value_t value[1];
++} wl_iqest_result_t;
++
++/* BTCX AIBSS (Oxygen) Status */
++typedef struct wlc_btc_aibss_info {
++	uint32	prev_tsf_l;		// Lower 32 bits of last read of TSF
++	uint32	prev_tsf_h;		// Higher 32 bits of last read of TSF
++	uint32	last_btinfo;		// Last read of BT info
++	uint32	local_btinfo;		// Local BT INFO BitMap
++	uint8	bt_out_of_sync_cnt;	// BT not in sync with strobe
++	uint8	esco_off_cnt;		// Count incremented when ESCO is off
++	uint8	strobe_enabled;		// Set only in AIBSS mode
++	uint8	strobe_on;		// strobe to BT is on for Oxygen
++	uint8	local_bt_in_sync;	// Sync status of local BT when strobe is on
++	uint8	other_bt_in_sync;	// Sync state of BT in other devices in AIBSS
++	uint8	local_bt_is_master;	// Local BT is master
++	uint8	sco_prot_on;		// eSCO Protection on in local device
++	uint8	other_esco_present;	// eSCO status in other devices in AIBSS
++	uint8	rx_agg_change;		// Indicates Rx Agg size needs to change
++	uint8	rx_agg_modified;	// Rx Agg size modified
++	uint8	acl_grant_set;		// ACL grants on for speeding up sync
++	uint8	write_ie_err_cnt;	// BTCX Ie write error cnt
++	uint8	parse_ie_err_cnt;	// BTCX IE parse error cnt
++	uint8	wci2_fail_cnt;		// WCI2 init failure cnt
++	uint8	strobe_enable_err_cnt;	// Strobe enable err cnt
++	uint8	strobe_init_err_cnt;	// Strobe init err cnt
++	uint8	tsf_jump_cnt;		// TSF jump cnt
++	uint8	acl_grant_cnt;		// ALC grant cnt
++	uint8	pad1;
++	uint16	ibss_tsf_shm;		// SHM address of strobe TSF
++	uint16	pad2;
++} wlc_btc_aibss_info_t;
++
++#define WLC_BTC_AIBSS_STATUS_VER	1
++#define WLC_BTC_AIBSS_STATUS_LEN	(sizeof(wlc_btc_aibss_status_t) - 2 * (sizeof(uint16)))
++
++typedef struct wlc_btc_aibss_status {
++	uint16	version;		// Version #
++	uint16	len;			// Length of the structure(excluding len & version)
++	int32	mode;			// Current value of btc_mode
++	uint16	bth_period;             // bt coex period. read from shm.
++	uint16	agg_off_bm;		// AGG OFF BM read from SHM
++	uint8	bth_active;             // bt active session
++	uint8	pad[3];
++	wlc_btc_aibss_info_t aibss_info;	// Structure definition above
++} wlc_btc_aibss_status_t;
++
++typedef enum {
++	STATE_NONE = 0,
++
++	/* WLAN -> BT */
++	W2B_DATA_SET = 21,
++	B2W_ACK_SET = 22,
++	W2B_DATA_CLEAR = 23,
++	B2W_ACK_CLEAR = 24,
++
++	/* BT -> WLAN */
++	B2W_DATA_SET = 31,
++	W2B_ACK_SET = 32,
++	B2W_DATA_CLEAR = 33,
++	W2B_ACK_CLEAR = 34
++} bwte_gci_intstate_t;
++
++#define WL_BWTE_STATS_VERSION 1 /* version of bwte_stats_t */
++typedef struct {
++	uint32 version;
++
++	bwte_gci_intstate_t inttobt;
++	bwte_gci_intstate_t intfrombt;
++
++	uint32 bt2wl_intrcnt; /* bt->wlan interrrupt count */
++	uint32 wl2bt_intrcnt; /* wlan->bt interrupt count  */
++
++	uint32 wl2bt_dset_cnt;
++	uint32 wl2bt_dclear_cnt;
++	uint32 wl2bt_aset_cnt;
++	uint32 wl2bt_aclear_cnt;
++
++	uint32 bt2wl_dset_cnt;
++	uint32 bt2wl_dclear_cnt;
++	uint32 bt2wl_aset_cnt;
++	uint32 bt2wl_aclear_cnt;
++
++	uint32 state_error_1;
++	uint32 state_error_2;
++	uint32 state_error_3;
++	uint32 state_error_4;
++} bwte_stats_t;
++
++#define TBOW_MAX_SSID_LEN        32
++#define TBOW_MAX_PASSPHRASE_LEN  63
++
++#define WL_TBOW_SETUPINFO_T_VERSION 1 /* version of tbow_setup_netinfo_t */
++typedef struct tbow_setup_netinfo {
++	uint32 version;
++	uint8 opmode;
++	uint8 pad;
++	uint8 macaddr[ETHER_ADDR_LEN];
++	uint32 ssid_len;
++	uint8 ssid[TBOW_MAX_SSID_LEN];
++	uint8 passphrase_len;
++	uint8 passphrase[TBOW_MAX_PASSPHRASE_LEN];
++	chanspec_t chanspec;
++	uint8 PAD[2];
++	uint32 channel;
++} tbow_setup_netinfo_t;
++
++typedef enum tbow_ho_opmode {
++	TBOW_HO_MODE_START_GO = 0,
++	TBOW_HO_MODE_START_STA,
++	TBOW_HO_MODE_START_GC,
++	TBOW_HO_MODE_TEST_GO,
++	TBOW_HO_MODE_STOP_GO = 0x10,
++	TBOW_HO_MODE_STOP_STA,
++	TBOW_HO_MODE_STOP_GC,
++	TBOW_HO_MODE_TEARDOWN
++} tbow_ho_opmode_t;
++
++/* Beacon trim feature statistics */
++/* configuration */
++#define BCNTRIMST_PER			0	/* Number of beacons to trim (0: disable) */
++#define BCNTRIMST_TIMEND		1	/* Number of bytes till TIM IE */
++#define BCNTRIMST_TSFLMT		2	/* TSF tolerance value (usecs) */
++/* internal use */
++#define BCNTRIMST_CUR			3	/* PSM's local beacon trim counter */
++#define BCNTRIMST_PREVLEN		4	/* Beacon length excluding the TIM IE */
++#define BCNTRIMST_TIMLEN		5	/* TIM IE Length */
++#define BCNTRIMST_RSSI			6	/* Partial beacon RSSI */
++#define BCNTRIMST_CHAN			7	/* Partial beacon channel */
++/* debug stat (off by default) */
++#define BCNTRIMST_DUR			8	/* RX duration until beacon trimmed */
++#define BCNTRIMST_RXMBSS		9	/* MYBSSID beacon received */
++#define BCNTRIMST_CANTRIM		10	/* # beacons which were trimmed */
++#define BCNTRIMST_LENCHG		11	/* # beacons not trimmed due to length change */
++#define BCNTRIMST_TSFDRF		12	/* # beacons not trimmed due to large TSF delta */
++#define BCNTRIMST_NOTIM			13	/* # beacons not trimmed due to TIM missing */
++
++#define BCNTRIMST_NUM			14
++
++#define WL_BCNTRIM_STATUS_VERSION_1 1
++typedef struct wl_bcntrim_status_query_v1 {
++	uint16  version;
++	uint16  len;     /* Total length includes fixed fields */
++	uint8   reset;   /* reset after reading the stats */
++	uint8   pad[3];  /* 4-byte alignment */
++} wl_bcntrim_status_query_v1_t;
++
++typedef struct wl_bcntrim_status_v1 {
++	uint16  version;
++	uint16  len;            /* Total length includes fixed fields and variable data[] */
++	uint8   curr_slice_id;  /* slice index of the interface */
++	uint8   applied_cfg;    /* applied bcntrim N threshold */
++	uint8   pad[2];         /* 4-byte alignment */
++	uint32  fw_status;      /* Bits representing bcntrim disable reason in FW */
++	uint32  total_disable_dur;    /* total duration (msec) bcntrim remains
++	                                 disabled due to FW disable reasons
++	                               */
++	uint32  data[];         /* variable length data containing stats */
++} wl_bcntrim_status_v1_t;
++
++#define BCNTRIM_STATS_MAX            10      /* Total stats part of the status data[] */
++
++/* Bits for FW status */
++#define WL_BCNTRIM_DISABLE_HOST      0x1  /* Host disabled bcntrim through bcntrim IOVar */
++#define WL_BCNTRIM_DISABLE_PHY_RATE  0x2  /* bcntrim disabled because beacon rx rate is
++	                                     higher than phy_rate_thresh
++	                                   */
++#define WL_BCNTRIM_DISABLE_QUIET_IE  0x4  /* bcntrim disable when Quiet IE present */
++
++#define WL_BCNTRIM_CFG_VERSION_1     1
++/* Common IOVAR struct */
++typedef struct wl_bcntrim_cfg_v1 {
++	uint16  version;
++	uint16 len;          /* Total length includes fixed fields and variable data[] */
++	uint16 subcmd_id;    /* subcommand id */
++	uint16 pad;          /* pad/reserved */
++	uint8 data[];        /* subcommand data; could be empty */
++} wl_bcntrim_cfg_v1_t;
++
++/* subcommands ids */
++enum {
++	WL_BCNTRIM_CFG_SUBCMD_PHY_RATE_THRESH =       0,   /* PHY rate threshold above
++	                                                      which bcntrim is not applied
++	                                                    */
++	WL_BCNTRIM_CFG_SUBCMD_OVERRIDE_DISABLE_MASK = 1,   /* Override bcntrim disable reasons */
++	WL_BCNTRIM_CFG_SUBCMD_TSF_DRIFT_LIMIT =       2    /* TSF drift limit to consider bcntrim */
++};
++
++#define BCNTRIM_MAX_PHY_RATE	48     /* in 500Kbps */
++#define BCNTRIM_MAX_TSF_DRIFT   65535  /* in usec */
++#define WL_BCNTRIM_OVERRIDE_DISABLE_MASK  (WL_BCNTRIM_DISABLE_QUIET_IE)
++
++/* WL_BCNTRIM_CFG_SUBCMD_PHY_RATE_TRESH */
++typedef struct wl_bcntrim_cfg_phy_rate_thresh {
++	uint32 rate;      /* beacon rate (in 500kbps units)  */
++} wl_bcntrim_cfg_phy_rate_thresh_t;
++
++/* WL_BCNTRIM_CFG_SUBCMD_OVERRIDE_DISABLE_MASK */
++typedef struct wl_bcntrim_cfg_override_disable_mask {
++	uint32  mask;     /* bits representing individual disable reason to override */
++} wl_bcntrim_cfg_override_disable_mask_t;
++
++/* WL_BCNTRIM_CFG_SUBCMD_TSF_DRIFT_LIMIT */
++typedef struct wl_bcntrim_cfg_tsf_drift_limit {
++	uint16   drift;   /* tsf drift limit specified in usec */
++	uint8    pad[2];  /* 4-byte alignment */
++} wl_bcntrim_cfg_tsf_drift_limit_t;
++
++
++/* --------------  TX Power Cap --------------- */
++#define TXPWRCAP_MAX_NUM_CORES 8
++#define TXPWRCAP_MAX_NUM_ANTENNAS (TXPWRCAP_MAX_NUM_CORES * 2)
++
++#define TXPWRCAP_NUM_SUBBANDS 5
++
++/* IOVAR txcapconfig enum's */
++#define TXPWRCAPCONFIG_WCI2 0
++#define TXPWRCAPCONFIG_HOST 1
++#define TXPWRCAPCONFIG_WCI2_AND_HOST 2
++
++/* IOVAR txcapstate enum's */
++#define TXPWRCAPSTATE_LOW_CAP  0
++#define TXPWRCAPSTATE_HIGH_CAP 1
++#define TXPWRCAPSTATE_HOST_LOW_WCI2_LOW_CAP	0
++#define TXPWRCAPSTATE_HOST_LOW_WCI2_HIGH_CAP	1
++#define TXPWRCAPSTATE_HOST_HIGH_WCI2_LOW_CAP	2
++#define TXPWRCAPSTATE_HOST_HIGH_WCI2_HIGH_CAP	3
++
++/* IOVAR txcapconfig and txcapstate structure is shared: SET and GET */
++#define TXPWRCAPCTL_VERSION 2
++typedef struct wl_txpwrcap_ctl {
++	uint8   version;
++	uint8   ctl[TXPWRCAP_NUM_SUBBANDS];
++} wl_txpwrcap_ctl_t;
++
++/* IOVAR txcapdump structure: GET only */
++#define TXPWRCAP_DUMP_VERSION 2
++typedef struct wl_txpwrcap_dump {
++	uint8   version;
++	uint8	pad0;
++	uint8   current_country[2];
++	uint32	current_channel;
++	uint8   config[TXPWRCAP_NUM_SUBBANDS];
++	uint8   state[TXPWRCAP_NUM_SUBBANDS];
++	uint8	high_cap_state_enabled;
++	uint8	wci2_cell_status_last;
++	uint8   download_present;
++	uint8	num_subbands;
++	uint8	num_antennas;
++	uint8   num_antennas_per_core[TXPWRCAP_MAX_NUM_CORES];
++	uint8	num_cc_groups;
++	uint8   current_country_cc_group_info_index;
++	int8    low_cap[TXPWRCAP_MAX_NUM_ANTENNAS*TXPWRCAP_NUM_SUBBANDS];
++	int8    high_cap[TXPWRCAP_MAX_NUM_ANTENNAS*TXPWRCAP_NUM_SUBBANDS];
++	uint8	PAD[3];
++} wl_txpwrcap_dump_t;
++
++typedef struct wl_txpwrcap_dump_v3 {
++	uint8   version;
++	uint8	pad0;
++	uint8   current_country[2];
++	uint32	current_channel;
++	uint8   config[TXPWRCAP_NUM_SUBBANDS];
++	uint8   state[TXPWRCAP_NUM_SUBBANDS];
++	uint8	high_cap_state_enabled;
++	uint8	wci2_cell_status_last;
++	uint8   download_present;
++	uint8	num_subbands;
++	uint8	num_antennas;
++	uint8   num_antennas_per_core[TXPWRCAP_MAX_NUM_CORES];
++	uint8	num_cc_groups;
++	uint8   current_country_cc_group_info_index;
++	uint8	cap_states_per_cc_group;
++	int8    host_low_wci2_low_cap[TXPWRCAP_MAX_NUM_ANTENNAS*TXPWRCAP_NUM_SUBBANDS];
++	int8    host_low_wci2_high_cap[TXPWRCAP_MAX_NUM_ANTENNAS*TXPWRCAP_NUM_SUBBANDS];
++	int8    host_high_wci2_low_cap[TXPWRCAP_MAX_NUM_ANTENNAS*TXPWRCAP_NUM_SUBBANDS];
++	int8    host_high_wci2_high_cap[TXPWRCAP_MAX_NUM_ANTENNAS*TXPWRCAP_NUM_SUBBANDS];
++	uint8	PAD[2];
++} wl_txpwrcap_dump_v3_t;
++
++typedef struct wl_txpwrcap_tbl {
++	uint8 num_antennas_per_core[TXPWRCAP_MAX_NUM_CORES];
++	/* Stores values for valid antennas */
++	int8 pwrcap_cell_on[TXPWRCAP_MAX_NUM_ANTENNAS]; /* qdBm units */
++	int8 pwrcap_cell_off[TXPWRCAP_MAX_NUM_ANTENNAS]; /* qdBm units */
++} wl_txpwrcap_tbl_t;
++
++/* ##### Ecounters section ##### */
++#define ECOUNTERS_VERSION_1	1
++
++/* Input structure for ecounters IOVAR */
++typedef struct ecounters_config_request {
++	uint16 version;		/* config version */
++	uint16 set;		/* Set where data will go. */
++	uint16 size;		/* Size of the set. */
++	uint16 timeout;		/* timeout in seconds. */
++	uint16 num_events;	/* Number of events to report. */
++	uint16 ntypes;		/* Number of entries in type array. */
++	uint16 type[1];		/* Statistics Types (tags) to retrieve. */
++} ecounters_config_request_t;
++
++#define ECOUNTERS_EVENTMSGS_VERSION_1		1
++#define ECOUNTERS_TRIGGER_CONFIG_VERSION_1	1
++
++#define ECOUNTERS_EVENTMSGS_EXT_MASK_OFFSET	\
++		OFFSETOF(ecounters_eventmsgs_ext_t, mask[0])
++
++#define ECOUNTERS_TRIG_CONFIG_TYPE_OFFSET	\
++		OFFSETOF(ecounters_trigger_config_t, type[0])
++
++typedef struct ecounters_eventmsgs_ext {
++	uint8 version;
++	uint8 len;
++	uint8 mask[1];
++} ecounters_eventmsgs_ext_t;
++
++typedef struct ecounters_trigger_config {
++	uint16 version;		/* version */
++	uint16 set;		/* set where data should go */
++	uint16 rsvd;		/* reserved */
++	uint16 pad;		/* pad/reserved */
++	uint16 ntypes;		/* number of types/tags */
++	uint16 type[1];		/* list of types */
++} ecounters_trigger_config_t;
++
++#define ECOUNTERS_TRIGGER_REASON_VERSION_1	1
++/* Triggered due to timer based ecounters */
++#define ECOUNTERS_TRIGGER_REASON_TIMER		0
++/* Triggered due to event based configuration */
++#define ECOUNTERS_TRIGGER_REASON_EVENTS		1
++#define ECOUNTERS_TRIGGER_REASON_MAX		1
++
++typedef struct ecounters_trigger_reason {
++	uint16 version;			/* version */
++	uint16 trigger_reason;		/* trigger reason */
++	uint32 sub_reason_code;		/* sub reason code */
++	uint32 trigger_time_now;	/* time in ms  at trigger */
++	uint32 host_ref_time;		/* host ref time */
++} ecounters_trigger_reason_t;
++
++#define WL_LQM_VERSION_1 1
++
++/* For wl_lqm_t flags field */
++#define WL_LQM_CURRENT_BSS_VALID 0x1
++#define WL_LQM_TARGET_BSS_VALID 0x2
++
++typedef struct {
++	struct ether_addr BSSID;
++	chanspec_t chanspec;
++	int32 rssi;
++	int32 snr;
++} wl_rx_signal_metric_t;
++
++typedef struct {
++	uint8 version;
++	uint8 flags;
++	uint16 pad;
++	int32 noise_level; /* current noise level */
++	wl_rx_signal_metric_t current_bss;
++	wl_rx_signal_metric_t target_bss;
++} wl_lqm_t;
++
++/* ##### Ecounters v2 section ##### */
++
++#define ECOUNTERS_VERSION_2	2
++
++/* Enumeration of various ecounters request types. This namespace is different from
++ * global reportable stats namespace.
++*/
++enum {
++	WL_ECOUNTERS_XTLV_REPORT_REQ = 1
++};
++
++/* Input structure for ecounters IOVAR */
++typedef struct ecounters_config_request_v2 {
++	uint16 version;		/* config version */
++	uint16 len;		/* Length of this struct including variable len */
++	uint16 logset;		/* Set where data will go. */
++	uint16 reporting_period;	/* reporting_period */
++	uint16 num_reports;	/* Number of timer expirations to report on */
++	uint8 pad[2];		/* Reserved for future use */
++	uint8 ecounters_xtlvs[];	/* Statistics Types (tags) to retrieve. */
++} ecounters_config_request_v2_t;
++
++#define ECOUNTERS_STATS_TYPES_FLAG_SLICE	0x1
++#define ECOUNTERS_STATS_TYPES_FLAG_IFACE	0x2
++#define ECOUNTERS_STATS_TYPES_FLAG_GLOBAL	0x4
++
++/* Slice mask bits */
++#define ECOUNTERS_STATS_TYPES_SLICE_MASK_SLICE0	0x1
++#define ECOUNTERS_STATS_TYPES_SLICE_MASK_SLICE1	0x2
++
++typedef struct ecounters_stats_types_report_req {
++	/* flags: bit0 = slice, bit1 = iface, bit2 = global,
++	 * rest reserved
++	 */
++	uint16 flags;
++	uint16 if_index;	/* host interface index */
++	uint16 slice_mask;	/* bit0 = slice0, bit1=slice1, rest reserved */
++	uint8 pad[2];	/* padding */
++	uint8 stats_types_req[]; /* XTLVs of requested types */
++} ecounters_stats_types_report_req_t;
++
++/* -------------- dynamic BTCOEX --------------- */
++#define DCTL_TROWS	2			/**< currently practical number of rows  */
++#define DCTL_TROWS_MAX	4			/**<  2 extra rows RFU */
++/* DYNCTL profile flags */
++#define DCTL_FLAGS_DISABLED	0		/**< default value: all features disabled */
++#define DCTL_FLAGS_DYNCTL	(1 << 0)	/**<  1 - enabled, 0 - legacy only */
++#define DCTL_FLAGS_DESENSE	(1 << 1)	/**< auto desense is enabled */
++#define DCTL_FLAGS_MSWITCH	(1 << 2)	/**< mode switching is enabled */
++#define DCTL_FLAGS_PWRCTRL	(1 << 3)	/**< Tx power control is enabled */
++/* for now AGG on/off is handled separately  */
++#define DCTL_FLAGS_TX_AGG_OFF	(1 << 4)	/**< TBD: allow TX agg Off */
++#define DCTL_FLAGS_RX_AGG_OFF	(1 << 5)	/**< TBD: allow RX agg Off */
++/* used for dry run testing only */
++#define DCTL_FLAGS_DRYRUN	(1 << 7)	/**< Enables dynctl dry run mode  */
++#define IS_DYNCTL_ON(prof)	((prof->flags & DCTL_FLAGS_DYNCTL) != 0)
++#define IS_DESENSE_ON(prof)	((prof->flags & DCTL_FLAGS_DESENSE) != 0)
++#define IS_MSWITCH_ON(prof)	((prof->flags & DCTL_FLAGS_MSWITCH) != 0)
++#define IS_PWRCTRL_ON(prof)	((prof->flags & DCTL_FLAGS_PWRCTRL) != 0)
++/* desense level currently in use */
++#define DESENSE_OFF	0
++#define DFLT_DESENSE_MID	12
++#define DFLT_DESENSE_HIGH	2
++
++/**
++ * dynctl data points(a set of btpwr & wlrssi thresholds)
++ * for mode & desense switching
++ */
++typedef struct btc_thr_data {
++	int8	mode;	/**< used by desense sw */
++	int8	bt_pwr;	/**< BT tx power threshold */
++	int8	bt_rssi;	/**< BT rssi threshold */
++	/* wl rssi range when mode or desense change may be needed */
++	int8	wl_rssi_high;
++	int8	wl_rssi_low;
++} btc_thr_data_t;
++
++/* dynctl. profile data structure  */
++#define DCTL_PROFILE_VER 0x01
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct  dctl_prof {
++	uint8 version;  /**< dynctl profile version */
++	/* dynctl profile flags bit:0 - dynctl On, bit:1 dsns On, bit:2 mode sw On, */
++	uint8 flags;  /**< bit[6:3] reserved, bit7 - Dryrun (sim) - On */
++	/**  wl desense levels to apply */
++	uint8	dflt_dsns_level;
++	uint8	low_dsns_level;
++	uint8	mid_dsns_level;
++	uint8	high_dsns_level;
++	/** mode switching hysteresis in dBm */
++	int8	msw_btrssi_hyster;
++	/** default btcoex mode */
++	uint8	default_btc_mode;
++	/** num of active rows in mode switching table */
++	uint8	msw_rows;
++	/** num of rows in desense table */
++	uint8	dsns_rows;
++	/** dynctl mode switching data table  */
++	btc_thr_data_t msw_data[DCTL_TROWS_MAX];
++	/** dynctl desense switching data table */
++	btc_thr_data_t dsns_data[DCTL_TROWS_MAX];
++} BWL_POST_PACKED_STRUCT dctl_prof_t;
++#include <packed_section_end.h>
++
++/**  dynctl status info */
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct  dynctl_status {
++	uint8 sim_on;	/**< true if simulation is On */
++	uint16	bt_pwr_shm; /**< BT per/task power as read from ucode  */
++	int8	bt_pwr;		/**< BT pwr extracted & converted to dBm */
++	int8	bt_rssi;	/**< BT rssi in dBm */
++	int8	wl_rssi;	/**< last wl rssi reading used by btcoex */
++	uint8	dsns_level; /**< current desense level */
++	uint8	btc_mode;   /**< current btcoex mode */
++	/* add more status items if needed,  pad to 4 BB if needed */
++} BWL_POST_PACKED_STRUCT dynctl_status_t;
++#include <packed_section_end.h>
++
++/**  dynctl simulation (dryrun data) */
++#include <packed_section_start.h>
++typedef BWL_PRE_PACKED_STRUCT struct  dynctl_sim {
++	uint8 sim_on;	/**< simulation mode on/off */
++	int8 btpwr;		/**< simulated BT power in dBm */
++	int8 btrssi;	/**< simulated BT rssi in dBm */
++	int8 wlrssi;	/**< simulated WL rssi in dBm */
++} BWL_POST_PACKED_STRUCT dynctl_sim_t;
++/* no default structure packing */
++#include <packed_section_end.h>
++
++/** PTK key maintained per SCB */
++#define RSN_TEMP_ENCR_KEY_LEN 16
++typedef struct wpa_ptk {
++	uint8 kck[RSN_KCK_LENGTH]; /**< EAPOL-Key Key Confirmation Key (KCK) */
++	uint8 kek[RSN_KEK_LENGTH]; /**< EAPOL-Key Key Encryption Key (KEK) */
++	uint8 tk1[RSN_TEMP_ENCR_KEY_LEN]; /**< Temporal Key 1 (TK1) */
++	uint8 tk2[RSN_TEMP_ENCR_KEY_LEN]; /**< Temporal Key 2 (TK2) */
++} wpa_ptk_t;
++
++/** GTK key maintained per SCB */
++typedef struct wpa_gtk {
++	uint32 idx;
++	uint32 key_len;
++	uint8  key[DOT11_MAX_KEY_SIZE];
++} wpa_gtk_t;
++
++/** FBT Auth Response Data structure */
++typedef struct wlc_fbt_auth_resp {
++	uint8 macaddr[ETHER_ADDR_LEN]; /**< station mac address */
++	uint8 pad[2];
++	uint8 pmk_r1_name[WPA2_PMKID_LEN];
++	wpa_ptk_t ptk; /**< pairwise key */
++	wpa_gtk_t gtk; /**< group key */
++	uint32 ie_len;
++	uint8 status;  /**< Status of parsing FBT authentication
++					Request in application
++					*/
++	uint8 ies[1]; /**< IEs contains MDIE, RSNIE,
++					FBTIE (ANonce, SNonce,R0KH-ID, R1KH-ID)
++					*/
++} wlc_fbt_auth_resp_t;
++
++/** FBT Action Response frame */
++typedef struct wlc_fbt_action_resp {
++	uint16 version; /**< structure version */
++	uint16 length; /**< length of structure */
++	uint8 macaddr[ETHER_ADDR_LEN]; /**< station mac address */
++	uint8 data_len;  /**< len of ie from Category */
++	uint8 data[1]; /**< data contains category, action, sta address, target ap,
++						status code,fbt response frame body
++						*/
++} wlc_fbt_action_resp_t;
++
++#define MACDBG_PMAC_ADDR_INPUT_MAXNUM 16
++#define MACDBG_PMAC_OBJ_TYPE_LEN 8
++
++typedef struct _wl_macdbg_pmac_param_t {
++	char type[MACDBG_PMAC_OBJ_TYPE_LEN];
++	uint8 step;
++	uint8 w_en;
++	uint16 num;
++	uint32 bitmap;
++	uint8 addr_raw;
++	uint8 addr_num;
++	uint16 addr[MACDBG_PMAC_ADDR_INPUT_MAXNUM];
++	uint8 pad0[2];
++	uint32 w_val;
++} wl_macdbg_pmac_param_t;
++
++/** IOVAR 'svmp_sampcol' parameter. Used to set and read SVMP_SAMPLE_COLLECT's setting */
++typedef struct wl_svmp_sampcol_param {
++	uint32 version;           /* version */
++	uint8  enable;
++	uint8  trigger_mode;      /* SVMP_SAMPCOL_TRIGGER */
++	uint8  trigger_mode_s[2]; /* SVMP_SAMPCOL_PKTPROC */
++	uint8  data_samplerate;   /* SVMP_SAMPCOL_SAMPLERATE */
++	uint8  data_sel_phy1;     /* SVMP_SAMPCOL_PHY1MUX */
++	uint8  data_sel_rx1;      /* SVMP_SAMPCOL_RX1MUX without iqCompOut */
++	uint8  data_sel_dualcap;  /* SVMP_SAMPCOL_RX1MUX */
++	uint8  pack_mode;         /* SVMP_SAMPCOL_PACK */
++	uint8  pack_order;
++	uint8  pack_cfix_fmt;
++	uint8  pack_1core_sel;
++	uint16 waitcnt;
++	uint16 caplen;
++	uint32 buff_addr_start;   /* in word-size (2-bytes) */
++	uint32 buff_addr_end;     /* note: Tcl in byte-size, HW in vector-size (8-bytes) */
++	uint8  int2vasip;
++	uint8  PAD;
++	uint16 status;
++} wl_svmp_sampcol_t;
++
++#define WL_SVMP_SAMPCOL_PARAMS_VERSION	1
++
++enum {
++	SVMP_SAMPCOL_TRIGGER_PKTPROC_TRANSITION = 0,
++	SVMP_SAMPCOL_TRIGGER_FORCE_IMMEDIATE,
++	SVMP_SAMPCOL_TRIGGER_RADAR_DET
++};
++
++enum {
++	SVMP_SAMPCOL_PHY1MUX_GPIOOUT = 0,
++	SVMP_SAMPCOL_PHY1MUX_FFT,
++	SVMP_SAMPCOL_PHY1MUX_DBGHX,
++	SVMP_SAMPCOL_PHY1MUX_RX1MUX
++};
++
++enum {
++	SVMP_SAMPCOL_RX1MUX_FARROWOUT = 4,
++	SVMP_SAMPCOL_RX1MUX_IQCOMPOUT,
++	SVMP_SAMPCOL_RX1MUX_DCFILTEROUT,
++	SVMP_SAMPCOL_RX1MUX_RXFILTEROUT,
++	SVMP_SAMPCOL_RX1MUX_ACIFILTEROUT
++};
++
++enum {
++	SVMP_SAMPCOL_SAMPLERATE_1XBW = 0,
++	SVMP_SAMPCOL_SAMPLERATE_2XBW
++};
++
++enum {
++	SVMP_SAMPCOL_PACK_DUALCAP = 0,
++	SVMP_SAMPCOL_PACK_4CORE,
++	SVMP_SAMPCOL_PACK_2CORE,
++	SVMP_SAMPCOL_PACK_1CORE
++};
++
++enum {
++	SVMP_SAMPCOL_PKTPROC_RESET = 0,
++	SVMP_SAMPCOL_PKTPROC_CARRIER_SEARCH,
++	SVMP_SAMPCOL_PKTPROC_WAIT_FOR_NB_PWR,
++	SVMP_SAMPCOL_PKTPROC_WAIT_FOR_W1_PWR,
++	SVMP_SAMPCOL_PKTPROC_WAIT_FOR_W2_PWR,
++	SVMP_SAMPCOL_PKTPROC_OFDM_PHY,
++	SVMP_SAMPCOL_PKTPROC_TIMING_SEARCH,
++	SVMP_SAMPCOL_PKTPROC_CHAN_EST_1,
++	SVMP_SAMPCOL_PKTPROC_LEG_SIG_DEC,
++	SVMP_SAMPCOL_PKTPROC_SIG_DECODE_1,
++	SVMP_SAMPCOL_PKTPROC_SIG_DECODE_2,
++	SVMP_SAMPCOL_PKTPROC_HT_AGC,
++	SVMP_SAMPCOL_PKTPROC_CHAN_EST_2,
++	SVMP_SAMPCOL_PKTPROC_PAY_DECODE,
++	SVMP_SAMPCOL_PKTPROC_DSSS_CCK_PHY,
++	SVMP_SAMPCOL_PKTPROC_WAIT_ENERGY_DROP,
++	SVMP_SAMPCOL_PKTPROC_WAIT_NCLKS,
++	SVMP_SAMPCOL_PKTPROC_PAY_DEC_EXT,
++	SVMP_SAMPCOL_PKTPROC_SIG_FAIL_DELAY,
++	SVMP_SAMPCOL_PKTPROC_RIFS_SEARCH,
++	SVMP_SAMPCOL_PKTPROC_BOARD_SWITCH_DIV_SEARCH,
++	SVMP_SAMPCOL_PKTPROC_DSSS_CCK_BOARD_SWITCH_DIV_SEARCH,
++	SVMP_SAMPCOL_PKTPROC_CHAN_EST_3,
++	SVMP_SAMPCOL_PKTPROC_CHAN_EST_4,
++	SVMP_SAMPCOL_PKTPROC_FINE_TIMING_SEARCH,
++	SVMP_SAMPCOL_PKTPROC_SET_CLIP_GAIN,
++	SVMP_SAMPCOL_PKTPROC_NAP,
++	SVMP_SAMPCOL_PKTPROC_VHT_SIGA_DEC,
++	SVMP_SAMPCOL_PKTPROC_VHT_SIGB_DEC,
++	SVMP_SAMPCOL_PKTPROC_PKT_ABORT,
++	SVMP_SAMPCOL_PKTPROC_DCCAL
++};
++
++/** IOVAR 'svmp_mem' parameter. Used to read/clear svmp memory */
++typedef struct svmp_mem {
++	uint32 addr;	/**< offset to read svmp memory from vasip base address */
++	uint16 len;	/**< length in count of uint16's */
++	uint16 val;	/**< set the range of addr/len with a value */
++} svmp_mem_t;
++
++/** IOVAR 'mu_rate' parameter. read/set mu rate for upto four users */
++#define MU_RATE_CFG_VERSION	1
++typedef struct mu_rate {
++	uint16	version;	/**< version of the structure as defined by MU_RATE_CFG_VERSION */
++	uint16	length;		/**< length of entire structure */
++	uint8	auto_rate;	/**< enable/disable auto rate */
++	uint8	PAD;
++	uint16	rate_user[4];	/**< rate per each of four users, set to -1 for no change */
++} mu_rate_t;
++
++/** IOVAR 'mu_group' parameter. Used to set and read MU group recommendation setting */
++#define WL_MU_GROUP_AUTO_COMMAND      -1
++#define WL_MU_GROUP_PARAMS_VERSION     3
++#define WL_MU_GROUP_METHOD_NAMELEN    64
++#define WL_MU_GROUP_NGROUP_MAX        15
++#define WL_MU_GROUP_NUSER_MAX          4
++#define WL_MU_GROUP_METHOD_MIN         0
++#define WL_MU_GROUP_NUMBER_AUTO_MIN    1
++#define WL_MU_GROUP_NUMBER_AUTO_MAX   15
++#define WL_MU_GROUP_NUMBER_FORCED_MAX  8
++#define WL_MU_GROUP_METHOD_OLD         0
++#define WL_MU_GROUP_MODE_AUTO          0
++#define WL_MU_GROUP_MODE_FORCED        1
++#define WL_MU_GROUP_FORCED_1GROUP      1
++#define WL_MU_GROUP_ENTRY_EMPTY       -1
++typedef struct mu_group {
++	uint32 version;          /* version */
++	int16  forced;           /* forced group recommendation */
++	int16  forced_group_mcs; /* forced group with mcs */
++	int16  forced_group_num; /* forced group number */
++	int16  group_option[WL_MU_GROUP_NGROUP_MAX][WL_MU_GROUP_NUSER_MAX];
++	                         /* set mode for forced grouping and read mode for auto grouping */
++	int16  group_GID[WL_MU_GROUP_NGROUP_MAX];
++	int16  group_method;     /* methof for VASIP group recommendation */
++	int16  group_number;     /* requested number for VASIP group recommendation */
++	int16  auto_group_num;   /* exact number from VASIP group recommendation */
++	int8   group_method_name[WL_MU_GROUP_METHOD_NAMELEN];
++	uint8  PAD[2];
++} mu_group_t;
++
++typedef struct mupkteng_sta {
++    struct ether_addr ea;
++	uint8  PAD[2];
++    int32 nrxchain;
++    int32 idx;
++} mupkteng_sta_t;
++
++typedef struct mupkteng_client {
++    int32 rspec;
++    int32 idx;
++    int32 flen;
++    int32 nframes;
++} mupkteng_client_t;
++
++typedef struct mupkteng_tx {
++    mupkteng_client_t client[8];
++    int32 nclients;
++    int32 ntx;
++} mupkteng_tx_t;
++
++/*
++ * MU Packet engine interface.
++ * The following two definitions will go into
++ * wlioctl_defs.h
++ * when wl utility changes are merged to EAGLE TOB & Trunk
++ */
++
++#define WL_MUPKTENG_PER_TX_START		0x10
++#define WL_MUPKTENG_PER_TX_STOP		        0x20
++
++/** IOVAR 'mu_policy' parameter. Used to configure MU admission control policies */
++#define WL_MU_POLICY_PARAMS_VERSION     1
++#define WL_MU_POLICY_SCHED_DEFAULT	60
++#define WL_MU_POLICY_DISABLED		0
++#define WL_MU_POLICY_ENABLED		1
++#define WL_MU_POLICY_NRX_MIN		1
++#define WL_MU_POLICY_NRX_MAX		2
++typedef struct mu_policy {
++	uint16 version;
++	uint16 length;
++	uint32 sched_timer;
++	uint32 pfmon;
++	uint32 pfmon_gpos;
++	uint32 samebw;
++	uint32 nrx;
++	uint32 max_muclients;
++} mu_policy_t;
++
++#define WL_NAN_BAND_STR_SIZE 5       /* sizeof ("auto") */
++
++/** Definitions of different NAN Bands */
++/* do not change the order */
++enum {
++		NAN_BAND_B = 0,
++		NAN_BAND_A,
++		NAN_BAND_AUTO,
++		NAN_BAND_INVALID = 0xFF
++};
++
++/* ifdef WL11ULB */
++/* ULB Mode configured via "ulb_mode" IOVAR */
++enum {
++    ULB_MODE_DISABLED = 0,
++    ULB_MODE_STD_ALONE_MODE = 1,    /* Standalone ULB Mode */
++    ULB_MODE_DYN_MODE = 2,      /* Dynamic ULB Mode */
++	/* Add all other enums before this */
++    MAX_SUPP_ULB_MODES
++};
++
++/* ULB BWs configured via "ulb_bw" IOVAR during Standalone Mode Only.
++ * Values of this enumeration are also used to specify 'Current Operational Bandwidth'
++ * and 'Primary Operational Bandwidth' sub-fields in 'ULB Operations' field (used in
++ * 'ULB Operations' Attribute or 'ULB Mode Switch' Attribute)
++ */
++typedef enum {
++    ULB_BW_DISABLED = 0,
++    ULB_BW_10MHZ    = 1,    /* Standalone ULB BW in 10 MHz BW */
++    ULB_BW_5MHZ = 2,    /* Standalone ULB BW in 5 MHz BW */
++    ULB_BW_2P5MHZ   = 3,    /* Standalone ULB BW in 2.5 MHz BW */
++	/* Add all other enums before this */
++    MAX_SUPP_ULB_BW
++} ulb_bw_type_t;
++/* endif WL11ULB */
++
++
++#define WL_MESH_IOCTL_VERSION     1
++#define MESH_IOC_BUFSZ            512 /* sufficient ioc buff size for mesh */
++/* container for mesh iovtls & events */
++typedef struct wl_mesh_ioc {
++	uint16  version;        /* interface command or event version */
++	uint16  id;             /* mesh ioctl cmd  ID  */
++	uint16  len;            /* total length of all tlv records in data[]  */
++	uint16  pad;            /* pad to be 32 bit aligment */
++	uint8   data[];       /* var len payload of bcm_xtlv_t type */
++} wl_mesh_ioc_t;
++
++enum wl_mesh_cmds {
++	WL_MESH_CMD_ENABLE = 1,
++	WL_MESH_CMD_JOIN = 2,
++	WL_MESH_CMD_PEER_STATUS = 3,
++	WL_MESH_CMD_ADD_ROUTE = 4,
++	WL_MESH_CMD_DEL_ROUTE = 5,
++	WL_MESH_CMD_ADD_FILTER = 6,
++	WL_MESH_CMD_ENAB_AL_METRIC = 7
++};
++
++enum wl_mesh_cmd_xtlv_id {
++	WL_MESH_XTLV_ENABLE = 1,
++	WL_MESH_XTLV_JOIN = 2,
++	WL_MESH_XTLV_STATUS = 3,
++	WL_MESH_XTLV_ADD_ROUTE = 4,
++	WL_MESH_XTLV_DEL_ROUTE = 5,
++	WL_MESH_XTLV_ADD_FILTER = 6,
++	WL_MESH_XTLV_ENAB_AIRLINK = 7
++};
++/* endif WLMESH */
++
++#ifdef WLMESH
++#ifndef SAE_MAX_PASSWD_LEN
++#define SAE_MAX_PASSWD_LEN	32
++#endif
++#endif
++
++/* Fast BSS Transition parameter configuration */
++#define FBT_PARAM_CURRENT_VERSION 0
++
++typedef struct _wl_fbt_params {
++	uint16	version;		/* version of the structure
++					* as defined by FBT_PARAM_CURRENT_VERSION
++					*/
++	uint16	length;			/* length of the entire structure */
++
++	uint16 param_type;		/* type of parameter defined below */
++	uint16 param_len;		/* length of the param_value */
++	uint8 param_value[1];		/* variable length */
++} wl_fbt_params_t;
++
++#define WL_FBT_PARAM_TYPE_RSNIE			0
++#define WL_FBT_PARAM_TYPE_FTIE			0x1
++#define WL_FBT_PARAM_TYPE_SNONCE		0x2
++#define WL_FBT_PARAM_TYPE_MDE			0x3
++#define WL_FBT_PARAM_TYPE_PMK_R0_NAME		0x4
++#define WL_FBT_PARAM_TYPE_R0_KHID		0x5
++#define WL_FBT_PARAM_TYPE_R1_KHID		0x6
++#define WL_FBT_PARAM_TYPE_FIRST_INVALID		0x7
++
++/* Assoc Mgr commands for fine control of assoc */
++#define WL_ASSOC_MGR_CURRENT_VERSION  0x0
++
++typedef struct {
++	uint16	version;		/* version of the structure as
++					 * defined by WL_ASSOC_MGR_CURRENT_VERSION
++					 */
++	uint16	length;			/* length of the entire structure */
++
++	uint16 cmd;
++	uint16 params;
++} wl_assoc_mgr_cmd_t;
++
++#define WL_ASSOC_MGR_CMD_PAUSE_ON_EVT		0 /* have assoc pause on certain events */
++#define WL_ASSOC_MGR_CMD_ABORT_ASSOC		1
++
++#define WL_ASSOC_MGR_PARAMS_EVENT_NONE			0 /* use this to resume as well as clear */
++#define WL_ASSOC_MGR_PARAMS_PAUSE_EVENT_AUTH_RESP	1
++
++#define WL_WINVER_STRUCT_VER_1 (1)
++
++typedef struct wl_winver {
++
++	/* Version and length of this structure. Length includes all fields in wl_winver_t */
++	uint16 struct_version;
++	uint16 struct_length;
++
++	/* Windows operating system version info (Microsoft provided) */
++	struct {
++		uint32 major_ver;
++		uint32 minor_ver;
++		uint32 build;
++	} os_runtime;
++
++	/* NDIS runtime version (Microsoft provided) */
++	struct {
++		uint16 major_ver;
++		uint16 minor_ver;
++	} ndis_runtime;
++
++	/* NDIS Driver version (Broadcom provided) */
++	struct {
++		uint16 major_ver;
++		uint16 minor_ver;
++	} ndis_driver;
++
++	/* WDI Upper Edge (UE) Driver version (Microsoft provided) */
++	struct {
++		uint8 major_ver;
++		uint8 minor_ver;
++		uint8 suffix;
++	} wdi_ue;
++
++	/* WDI Lower Edge (LE) Driver version (Broadcom provided) */
++	struct {
++		uint8 major_ver;
++		uint8 minor_ver;
++		uint8 suffix;
++	} wdi_le;
++	uint8 PAD[2];
++} wl_winver_t;
++
++/* defined(WLRCC) || defined(ROAM_CHANNEL_CACHE) */
++#define MAX_ROAM_CHANNEL      20
++typedef struct {
++	int32 n;
++	chanspec_t channels[MAX_ROAM_CHANNEL];
++} wl_roam_channel_list_t;
++/* endif RCC || ROAM_CHANNEL_CACHE */
++
++/* values for IOV_MFP arg */
++enum {
++    WL_MFP_NONE = 0,
++    WL_MFP_CAPABLE,
++    WL_MFP_REQUIRED
++};
++
++typedef enum {
++	CHANSW_UNKNOWN = 0,	/* channel switch due to unknown reason */
++	CHANSW_SCAN = 1,	/* channel switch due to scan */
++	CHANSW_PHYCAL = 2,	/* channel switch due to phy calibration */
++	CHANSW_INIT = 3,	/* channel set at WLC up time */
++	CHANSW_ASSOC = 4,	/* channel switch due to association */
++	CHANSW_ROAM = 5,	/* channel switch due to roam */
++	CHANSW_MCHAN = 6,	/* channel switch triggered by mchan module */
++	CHANSW_IOVAR = 7,	/* channel switch due to IOVAR */
++	CHANSW_CSA_DFS = 8,	/* channel switch due to chan switch  announcement from AP */
++	CHANSW_APCS = 9,	/* Channel switch from AP channel select module */
++	CHANSW_AWDL = 10,	/* channel switch due to AWDL */
++	CHANSW_FBT = 11,	/* Channel switch from FBT module for action frame response */
++	CHANSW_UPDBW = 12,	/* channel switch at update bandwidth */
++	CHANSW_ULB = 13,	/* channel switch at ULB */
++	CHANSW_LAST = 14	/* last channel switch reason */
++} chansw_reason_t;
++
++/*
++ * WOWL unassociated mode power svae pattern.
++ */
++typedef struct wowl_radio_duty_cycle {
++	uint16 wake_interval;
++	uint16  sleep_interval;
++} wowl_radio_duty_cycle_t;
++
++typedef struct nd_ra_ol_limits {
++	uint16 version;         /* version of the iovar buffer */
++	uint16 type;            /* type of data provided */
++	uint16 length;          /* length of the entire structure */
++	uint16 pad1;            /* pad union to 4 byte boundary */
++	union {
++		struct {
++			uint16 min_time;         /* seconds, min time for RA offload hold */
++			uint16 lifetime_percent;
++			/* percent, lifetime percentage for offload hold time */
++		} lifetime_relative;
++		struct {
++			uint16 hold_time;        /* seconds, RA offload hold time */
++			uint16 pad2;             /* unused */
++		} fixed;
++	} limits;
++} nd_ra_ol_limits_t;
++
++#define ND_RA_OL_LIMITS_VER 1
++
++/* nd_ra_ol_limits sub-types */
++#define ND_RA_OL_LIMITS_REL_TYPE   0     /* relative, percent of RA lifetime */
++#define ND_RA_OL_LIMITS_FIXED_TYPE 1     /* fixed time */
++
++/* buffer lengths for the different nd_ra_ol_limits types */
++#define ND_RA_OL_LIMITS_REL_TYPE_LEN   12
++#define ND_RA_OL_LIMITS_FIXED_TYPE_LEN  10
++
++/*
++ * Temperature Throttling control mode
++ */
++typedef struct wl_temp_control {
++	uint8 enable;
++	uint8 PAD;
++	uint16 control_bit;
++} wl_temp_control_t;
++
++/* SensorHub Interworking mode */
++
++#define SHUB_CONTROL_VERSION    1
++#define SHUB_CONTROL_LEN    12
++
++typedef struct {
++	uint16  verison;
++	uint16  length;
++	uint16  cmd;
++	uint16  op_mode;
++	uint16  interval;
++	uint16  enable;
++} shub_control_t;
++
++/* WLC_MAJOR_VER <= 5 */
++/* Data structures for non-TLV format */
++
++/* Data structures for rsdb caps */
++/*
++ * The flags field of the rsdb_caps_response is designed to be
++ * a Bit Mask. As of now only Bit 0 is used as mentioned below.
++ */
++
++/* Bit-0 in flags is used to indicate if the cores can operate synchronously
++* i.e either as 2x2 MIMO or 2(1x1 SISO). This is true only for 4349 variants
++* 0 - device can operate only in rsdb mode (eg: 4364)
++* 1 - device can operate in both rsdb and mimo (eg : 4359 variants)
++*/
++
++#define WL_RSDB_CAPS_VER 2
++#define SYNCHRONOUS_OPERATION_TRUE	(1 << 0)
++#define WL_RSDB_CAPS_FIXED_LEN  OFFSETOF(rsdb_caps_response_t, num_chains)
++
++typedef struct rsdb_caps_response {
++	uint8 ver;		/* Version */
++	uint8 len;		/* length of this structure excluding ver and len */
++	uint8 rsdb;		/* TRUE for rsdb chip */
++	uint8 num_of_cores;	/* no of d11 cores */
++	uint16 flags;		/* Flags to indicate various capabilities */
++	uint8 num_chains[1];	/* Tx/Rx chains for each core */
++} rsdb_caps_response_t;
++
++/* Data structures for rsdb bands */
++
++#define WL_RSDB_BANDS_VER       2
++#define WL_RSDB_BANDS_FIXED_LEN  OFFSETOF(rsdb_bands_t, band)
++
++typedef struct rsdb_bands
++{
++	uint8 ver;
++	uint8 len;
++	uint16 num_cores;	/* num of D11 cores */
++	int16 band[1];		/* The band operating on each of the d11 cores */
++} rsdb_bands_t;
++
++/* rsdb config */
++
++#define WL_RSDB_CONFIG_VER 3
++#define ALLOW_SIB_PARALLEL_SCAN	(1 << 0)
++#define MAX_BANDS 2
++
++#define WL_RSDB_CONFIG_LEN sizeof(rsdb_config_t)
++
++
++typedef uint8 rsdb_opmode_t;
++typedef uint32 rsdb_flags_t;
++
++typedef enum rsdb_modes {
++	WLC_SDB_MODE_NOSDB_MAIN = 1, /* 2X2 or MIMO mode (applicable only for 4355) */
++	WLC_SDB_MODE_NOSDB_AUX = 2,
++	WLC_SDB_MODE_SDB_MAIN = 3, /* This is RSDB mode(default) applicable only for 4364 */
++	WLC_SDB_MODE_SDB_AUX = 4,
++	WLC_SDB_MODE_SDB_AUTO = 5, /* Same as WLC_RSDB_MODE_RSDB(1+1) mode above */
++} rsdb_modes_t;
++
++typedef struct rsdb_config {
++	uint8 ver;
++	uint8 len;
++	uint16 reserved;
++	rsdb_opmode_t non_infra_mode;
++	rsdb_opmode_t infra_mode[MAX_BANDS];
++	rsdb_flags_t flags[MAX_BANDS];
++	rsdb_opmode_t current_mode;   /* Valid only in GET, returns the current mode */
++	uint8  pad[3];
++} rsdb_config_t;
++
++/* WLC_MAJOR_VER > =5 */
++/* TLV definitions and data structures for rsdb subcmds */
++
++enum wl_rsdb_cmd_ids {
++	/* RSDB ioctls */
++	WL_RSDB_CMD_VER = 0,
++	WL_RSDB_CMD_CAPS = 1,
++	WL_RSDB_CMD_BANDS = 2,
++	WL_RSDB_CMD_CONFIG = 3,
++	/* Add before this !! */
++	WL_RSDB_CMD_LAST
++};
++#define WL_RSDB_IOV_VERSION	0x1
++
++typedef struct rsdb_caps_response_v1 {
++	uint8 rsdb;		/* TRUE for rsdb chip */
++	uint8 num_of_cores;	/* no of d11 cores */
++	uint16 flags;		/* Flags to indicate various capabilities */
++	uint8 num_chains[MAX_NUM_D11CORES];	/* Tx/Rx chains for each core */
++	uint8 band_cap[MAX_NUM_D11CORES]; /* band cap bitmask per slice */
++} rsdb_caps_response_v1_t;
++
++typedef struct rsdb_bands_v1
++{
++	uint8 num_cores;		/* num of D11 cores */
++	uint8 pad;			/* padding bytes for 4 byte alignment */
++	int8 band[MAX_NUM_D11CORES];	/* The band operating on each of the d11 cores */
++} rsdb_bands_v1_t;
++
++typedef struct rsdb_config_xtlv {
++	rsdb_opmode_t reserved1;	/* Non_infra mode is no more applicable */
++	rsdb_opmode_t infra_mode[MAX_BANDS]; /* Target mode for Infra association */
++	uint8 pad;	/* pad bytes for 4 byte alignment */
++	rsdb_flags_t  flags[MAX_BANDS];
++	rsdb_opmode_t current_mode; /* GET only; has current mode of operation */
++	uint8 pad1[3];
++} rsdb_config_xtlv_t;
++
++/* Definitions for slot_bss chanseq iovar */
++#define WL_SLOT_BSS_VERSION 1
++
++enum wl_slotted_bss_cmd_id {
++	WL_SLOTTED_BSS_CMD_VER = 0,
++	WL_SLOTTED_BSS_CMD_CHANSEQ = 1
++};
++typedef uint16 chan_seq_type_t;
++enum chan_seq_type {
++	CHAN_SEQ_TYPE_AWDL = 1,
++	CHAN_SEQ_TYPE_SLICE = 2,
++	CHAN_SEQ_TYPE_NAN = 3
++};
++typedef uint8 sched_flag_t;
++enum sched_flag {
++	NO_SDB_SCHED = 0x1,
++	SDB_TDM_SCHED = 0x2,
++	SDB_SPLIT_BAND_SCHED = 0x4, /* default mode for 4357 */
++	MAIN_ONLY = 0x8,
++	AUX_ONLY = 0x10,
++	SDB_DUAL_TIME = (MAIN_ONLY | AUX_ONLY),
++	NO_SDB_MAIN_ONLY = (NO_SDB_SCHED | MAIN_ONLY), /* default mode for 4364 */
++	SDB_TDM_SCHED_MAIN = (SDB_TDM_SCHED | MAIN_ONLY),
++	SDB_TDM_SCHED_AUX = (SDB_TDM_SCHED | AUX_ONLY),
++	SDB_TDM_SCHED_DUAL_TIME = (SDB_TDM_SCHED | SDB_DUAL_TIME),
++	SDB_SPLIT_BAND_SCHED_DUAL_TIME = (SDB_SPLIT_BAND_SCHED | SDB_DUAL_TIME)
++};
++
++typedef struct chan_seq_tlv_data {
++	uint32 flags;
++	uint8 data[1];
++} chan_seq_tlv_data_t;
++
++typedef struct chan_seq_tlv {
++	chan_seq_type_t type;
++	uint16 len;
++	chan_seq_tlv_data_t chanseq_data[1];
++} chan_seq_tlv_t;
++
++typedef struct sb_channel_sequence {
++	sched_flag_t sched_flags; /* (sdb-tdm or sdb-sb or Dual-Time) */
++	uint8 num_seq; /* number of chan_seq_tlv following */
++	uint16 pad;
++	chan_seq_tlv_t seq[1];
++} sb_channel_sequence_t;
++
++typedef struct slice_chan_seq {
++	uint8 slice_index;  /* 0(Main) or 1 (Aux) */
++	uint8 num_chanspecs;
++	uint16 pad;
++	chanspec_t chanspecs[1];
++} slice_chan_seq_t;
++
++#define WL_SLICE_CHAN_SEQ_FIXED_LEN   OFFSETOF(slice_chan_seq_t, chanspecs)
++
++typedef struct sim_pm_params {
++	uint32 enabled;
++	uint16 cycle;
++	uint16 up;
++} sim_pm_params_t;
++
++/* Bits for fw_status */
++#define NAP_DISABLED_HOST		0x01   /* Host has disabled through nap_enable */
++#define NAP_DISABLED_RSSI		0x02   /* Disabled because of nap_rssi_threshold */
++
++/* Bits for hw_status */
++#define NAP_HWCFG			0x01   /* State of NAP config bit in phy HW */
++
++/* ifdef WL_NATOE */
++#define WL_NATOE_IOCTL_VERSION		1
++#define WL_NATOE_IOC_BUFSZ		512	/* sufficient ioc buff size for natoe */
++#define WL_NATOE_DBG_STATS_BUFSZ	2048
++
++/* config natoe STA and AP IP's structure */
++typedef struct {
++	uint32 sta_ip;
++	uint32 sta_netmask;
++	uint32 sta_router_ip;
++	uint32 sta_dnsip;
++	uint32 ap_ip;
++	uint32 ap_netmask;
++} wl_natoe_config_ips_t;
++
++/* natoe ports config structure */
++typedef struct {
++	uint16 start_port_num;
++	uint16 no_of_ports;
++} wl_natoe_ports_config_t;
++
++/* natoe ports exception info */
++typedef struct {
++	uint16 sta_port_num;
++	uint16 dst_port_num;    /* for SIP type protocol, dst_port_num info can be ignored by FW */
++	uint32 ip;              /* for SIP ip is APcli_ip and for port clash it is dst_ip */
++	uint8  entry_type;      /* Create/Destroy */
++	uint8  pad[3];
++} wl_natoe_exception_port_t;
++
++/* container for natoe ioctls & events */
++typedef struct wl_natoe_ioc {
++	uint16  version;        /* interface command or event version */
++	uint16  id;             /* natoe ioctl cmd  ID  */
++	uint16  len;            /* total length of all tlv records in data[]  */
++	uint16  pad;            /* pad to be 32 bit aligment */
++	uint8   data[];       /* var len payload of bcm_xtlv_t type */
++} wl_natoe_ioc_t;
++
++enum wl_natoe_cmds {
++	WL_NATOE_CMD_ENABLE = 1,
++	WL_NATOE_CMD_CONFIG_IPS = 2,
++	WL_NATOE_CMD_CONFIG_PORTS = 3,
++	WL_NATOE_CMD_DBG_STATS = 4,
++	WL_NATOE_CMD_EXCEPTION_PORT = 5,
++	WL_NATOE_CMD_SKIP_PORT = 6,
++	WL_NATOE_CMD_TBL_CNT = 7
++};
++
++enum wl_natoe_cmd_xtlv_id {
++	WL_NATOE_XTLV_ENABLE = 1,
++	WL_NATOE_XTLV_CONFIG_IPS = 2,
++	WL_NATOE_XTLV_CONFIG_PORTS = 3,
++	WL_NATOE_XTLV_DBG_STATS = 4,
++	WL_NATOE_XTLV_EXCEPTION_PORT = 5,
++	WL_NATOE_XTLV_SKIP_PORT = 6,
++	WL_NATOE_XTLV_TBL_CNT = 7
++};
++
++/* endif WL_NATOE */
++
++enum wl_idauth_cmd_ids {
++	WL_IDAUTH_CMD_CONFIG				= 1,
++	WL_IDAUTH_CMD_PEER_INFO				= 2,
++	WL_IDAUTH_CMD_COUNTERS				= 3,
++	WL_IDAUTH_CMD_LAST
++};
++enum wl_idauth_xtlv_id {
++	WL_IDAUTH_XTLV_AUTH_ENAB			= 0x1,
++	WL_IDAUTH_XTLV_GTK_ROTATION			= 0x2,
++	WL_IDAUTH_XTLV_EAPOL_COUNT			= 0x3,
++	WL_IDAUTH_XTLV_EAPOL_INTRVL			= 0x4,
++	WL_IDAUTH_XTLV_BLKLIST_COUNT			= 0x5,
++	WL_IDAUTH_XTLV_BLKLIST_AGE			= 0x6,
++	WL_IDAUTH_XTLV_PEERS_INFO			= 0x7,
++	WL_IDAUTH_XTLV_COUNTERS				= 0x8
++};
++enum wl_idauth_stats {
++	WL_AUTH_PEER_STATE_AUTHORISED			= 0x01,
++	WL_AUTH_PEER_STATE_BLACKLISTED			= 0x02,
++	WL_AUTH_PEER_STATE_4WAY_HS_ONGOING		= 0x03,
++	WL_AUTH_PEER_STATE_LAST
++};
++typedef struct {
++	uint16 state;				/* Peer State: Authorised or Blacklisted */
++	struct ether_addr peer_addr;		/* peer Address */
++	uint32 blklist_end_time;		/* Time of blacklist end */
++} auth_peer_t;
++typedef struct wl_idauth_counters {
++	uint32 auth_reqs;			/* No of auth req recvd */
++	uint32 mic_fail;			/* No of mic fails */
++	uint32 four_way_hs_fail;		/* No of 4-way handshake fails */
++} wl_idauth_counters_t;
++
++#define WLC_UTRACE_LEN  512
++#define WLC_UTRACE_READ_END 0
++#define WLC_UTRACE_MORE_DATA 1
++typedef struct wl_utrace_capture_args_v1 {
++	uint32 length;
++	uint32 flag;
++} wl_utrace_capture_args_v1_t;
++
++#define UTRACE_CAPTURE_VER_2	2
++typedef struct wl_utrace_capture_args_v2 {
++	/* structure control */
++	uint16 version;		/**< structure version */
++	uint16 length;		/**< length of the response */
++	uint32 flag;		/* Indicates if there is more data or not */
++} wl_utrace_capture_args_v2_t;
++
++/* XTLV IDs for the Health Check "hc" iovar top level container */
++enum {
++	WL_HC_XTLV_ID_CAT_HC = 1,		/* category for HC as a whole */
++	WL_HC_XTLV_ID_CAT_DATAPATH_TX = 2,	/* Datapath Tx */
++	WL_HC_XTLV_ID_CAT_DATAPATH_RX = 3,	/* Datapath Rx */
++	WL_HC_XTLV_ID_CAT_SCAN	= 4,		/* Scan */
++};
++
++/* Health Check: Common XTLV IDs for sub-elements in the top level container
++ * Number starts at 0x8000 to be out of the way for category specific IDs.
++ */
++enum {
++	WL_HC_XTLV_ID_ERR       = 0x8000,       /* for sub-command  err return */
++	WL_HC_XTLV_ID_IDLIST    = 0x8001,       /* container for uint16 IDs */
++};
++
++/* Health Check: Datapath TX IDs */
++enum {
++	WL_HC_TX_XTLV_ID_VAL_STALL_THRESHOLD   = 1,     /* stall_threshold */
++	WL_HC_TX_XTLV_ID_VAL_STALL_SAMPLE_SIZE = 2,     /* stall_sample_size */
++	WL_HC_TX_XTLV_ID_VAL_STALL_TIMEOUT     = 3,     /* stall_timeout */
++	WL_HC_TX_XTLV_ID_VAL_STALL_FORCE       = 4,     /* stall_force */
++	WL_HC_TX_XTLV_ID_VAL_STALL_EXCLUDE     = 5,     /* stall_exclude */
++	WL_HC_TX_XTLV_ID_VAL_FC_TIMEOUT        = 6,     /* flow ctl timeout */
++	WL_HC_TX_XTLV_ID_VAL_FC_FORCE          = 7,     /* flow ctl force failure */
++	WL_HC_TX_XTLV_ID_VAL_DELAY_TO_TRAP     = 8,     /* delay threshold for forced trap */
++	WL_HC_TX_XTLV_ID_VAL_DELAY_TO_RPT      = 9,     /* delay threshold for event log report */
++};
++
++/* Health Check: Datapath RX IDs */
++enum {
++	WL_HC_RX_XTLV_ID_VAL_DMA_STALL_TIMEOUT = 1,     /* dma_stall_timeout */
++	WL_HC_RX_XTLV_ID_VAL_DMA_STALL_FORCE   = 2,     /* dma_stall test trigger */
++	WL_HC_RX_XTLV_ID_VAL_STALL_THRESHOLD   = 3,     /* stall_threshold */
++	WL_HC_RX_XTLV_ID_VAL_STALL_SAMPLE_SIZE = 4,     /* stall_sample_size */
++	WL_HC_RX_XTLV_ID_VAL_STALL_FORCE       = 5,     /* stall test trigger */
++};
++
++/* Health Check: Datapath SCAN IDs */
++enum {
++	WL_HC_XTLV_ID_VAL_SCAN_STALL_THRESHOLD	= 1,	/* scan stall threshold */
++};
++
++/* IDs of Health Check report structures for sub types of health checks within WL */
++enum {
++	WL_HC_DD_UNDEFINED = 0,		/* Undefined */
++	WL_HC_DD_RX_DMA_STALL = 1,	/* RX DMA stall check */
++	WL_HC_DD_RX_STALL = 2,		/* RX stall check */
++	WL_HC_DD_TX_STALL = 3,		/* TX stall check */
++	WL_HC_DD_SCAN_STALL = 4,	/* SCAN stall check */
++	WL_HC_DD_MAX
++};
++
++/*
++ * Health Check report structures for sub types of health checks within WL
++ */
++
++/* Health Check report structure for Rx DMA Stall check */
++typedef struct {
++	uint16 type;
++	uint16 length;
++	uint16 timeout;
++	uint16 stalled_dma_bitmap;
++} wl_rx_dma_hc_info_t;
++
++/* Health Check report structure for Tx packet failure check */
++typedef struct {
++	uint16 type;
++	uint16 length;
++	uint32 stall_bitmap;
++	uint32 stall_bitmap1;
++	uint32 failure_ac;
++	uint32 threshold;
++	uint32 tx_all;
++	uint32 tx_failure_all;
++} wl_tx_hc_info_t;
++
++/* Health Check report structure for Rx dropped packet failure check */
++typedef struct {
++	uint16 type;
++	uint16 length;
++	uint32 bsscfg_idx;
++	uint32 rx_hc_pkts;
++	uint32 rx_hc_dropped_all;
++	uint32 rx_hc_alert_th;
++} wl_rx_hc_info_t;
++
++/* HE top level command IDs */
++enum {
++	WL_HE_CMD_ENAB = 0,
++	WL_HE_CMD_FEATURES = 1,
++	WL_HE_CMD_TWT_SETUP = 2,
++	WL_HE_CMD_TWT_TEARDOWN = 3,
++	WL_HE_CMD_TWT_INFO = 4,
++	WL_HE_CMD_BSSCOLOR = 5,
++	WL_HE_CMD_PARTIAL_BSSCOLOR = 6,
++	WL_HE_CMD_LAST
++};
++
++#define WL_HEB_VERSION	0
++
++/* HEB top level command IDs */
++enum {
++	WL_HEB_CMD_ENAB = 0,
++	WL_HEB_CMD_NUM_HEB = 1,
++	WL_HEB_CMD_COUNTERS = 1,
++	WL_HEB_CMD_CLEAR_COUNTERS = 2,
++	WL_HEB_CMD_LAST
++};
++
++/* HEB counters structures */
++typedef struct {
++	uint16 pre_event;
++	uint16 start_event;
++	uint16 end_event;
++	uint16 missed;
++} wl_heb_int_cnt_t;
++
++typedef struct {
++	/* structure control */
++	uint16 version;	/* structure version */
++	uint16 length;	/* data length (starting after this field) */
++	wl_heb_int_cnt_t heb_int_cnt[1];
++} wl_heb_cnt_t;
++
++
++/* TWT Setup descriptor */
++typedef struct {
++	/* Setup Command. */
++	uint8 setup_cmd;	/* See TWT_SETUP_CMD_XXXX in 802.11ah.h,
++				 * valid when bcast_twt is FALSE.
++				 */
++	/* Flow attributes */
++	uint8 flow_flags;	/* See WL_TWT_FLOW_FLAG_XXXX below */
++	uint8 flow_id;		/* must be between 0 and 7 */
++	/* Target Wake Time */
++	uint8 wake_type;	/* See WL_TWT_TIME_TYPE_XXXX below */
++	uint32 wake_time_h;	/* target wake time - BSS TSF (us) */
++	uint32 wake_time_l;
++	uint32 wake_dur;	/* target wake duration in us units */
++	uint32 wake_int;	/* target wake interval */
++} wl_twt_sdesc_t;
++
++/* Flow flags */
++#define WL_TWT_FLOW_FLAG_BROADCAST	(1<<0)
++#define WL_TWT_FLOW_FLAG_IMPLICIT	(1<<1)
++#define WL_TWT_FLOW_FLAG_UNANNOUNCED	(1<<2)
++#define WL_TWT_FLOW_FLAG_TRIGGER	(1<<3)
++
++/* Flow id */
++#define WL_TWT_FLOW_ID_FID	0x07	/* flow id */
++#define WL_TWT_FLOW_ID_GID_MASK	0x70	/* group id - broadcast TWT only */
++#define WL_TWT_FLOW_ID_GID_SHIFT 4
++
++/* Wake type */
++/* TODO: not yet finalized */
++#define WL_TWT_TIME_TYPE_BSS	0	/* The time specified in wake_time_h/l is
++					 * the BSS TSF time.
++					 */
++#define WL_TWT_TIME_TYPE_OFFSET	1	/* The time specified in wake_time_h/l is an offset
++					 * of the TSF time when the iovar is processed.
++					 */
++
++#define WL_TWT_SETUP_VER	0
++
++/* HE TWT Setup command */
++typedef struct {
++	/* structure control */
++	uint16 version;	/* structure version */
++	uint16 length;	/* data length (starting after this field) */
++	/* peer address */
++	struct ether_addr peer;	/* leave it all 0s' for AP */
++	/* session id */
++	uint8 dialog;	/* an arbitrary number to identify the seesion */
++	uint8 pad;
++	/* setup descriptor */
++	wl_twt_sdesc_t desc;
++} wl_twt_setup_t;
++
++#define WL_TWT_TEARDOWN_VER	0
++
++/* HE TWT Teardown command */
++typedef struct {
++	/* structure control */
++	uint16 version;	/* structure version */
++	uint16 length;	/* data length (starting after this field) */
++	/* peer address */
++	struct ether_addr peer;	/* leave it all 0s' for AP */
++	/* flow attributes */
++	uint8 flow_flags;	/* See WL_TWT_FLOW_FLAG_XXXX above.
++				 * (only BORADCAST) is applicable)
++				 */
++	uint8 flow_id;		/* must be between 0 and 7 */
++} wl_twt_teardown_t;
++
++/* twt information descriptor */
++typedef struct {
++	uint8 flow_flags;	/* See WL_TWT_INFO_FLAG_XXX below */
++	uint8 flow_id;
++	uint8 pad[2];
++	uint32 next_twt_h;
++	uint32 next_twt_l;
++} wl_twt_idesc_t;
++
++/* Flow flags */
++#define WL_TWT_INFO_FLAG_RESP_REQ	(1<<0)	/* Request response */
++
++#define WL_TWT_INFO_VER	0
++
++/* HE TWT Information command */
++typedef struct {
++	/* structure control */
++	uint16 version;	/* structure version */
++	uint16 length;	/* data length (starting after this field) */
++	/* peer address */
++	struct ether_addr peer;	/* leave it all 0s' for AP */
++	uint8 pad[2];
++	/* information descriptor */
++	wl_twt_idesc_t desc;
++} wl_twt_info_t;
++
++/* Current version for wlc_clm_power_limits_req_t structure and flags */
++#define WLC_CLM_POWER_LIMITS_REQ_VERSION 1
++/* "clm_power_limits" iovar request structure */
++typedef struct wlc_clm_power_limits_req {
++	/* Input. Structure and flags version */
++	uint32 version;
++	/* Full length of buffer (includes this structure and space for TLV-encoded PPR) */
++	uint32 buflen;
++	/* Input. Flags (see WLC_CLM_POWER_LIMITS_INPUT_FLAG_... below) */
++	uint32 input_flags;
++	/* Input. CC of region whose data is being requested */
++	char cc[WLC_CNTRY_BUF_SZ];
++	/* Input. Channel/subchannel in chanspec_t format */
++	uint32 chanspec;
++	/* Subchannel encoded as clm_limits_type_t */
++	uint32 clm_subchannel;
++	/* Input. 0-based antenna index */
++	uint32 antenna_idx;
++	/* Output. General flags (see WLC_CLM_POWER_LIMITS_OUTPUT_FLAG_... below) */
++	uint32 output_flags;
++	/* Output. 2.4G country flags, encoded as clm_flags_t enum */
++	uint32 clm_country_flags_2g;
++	/* Output. 5G country flags, encoded as clm_flags_t enum */
++	uint32 clm_country_flags_5g;
++	/* Output. Length of TLV-encoded PPR data that follows this structure */
++	uint32 ppr_tlv_size;
++	/* Output. Beginning of buffer for TLV-encoded PPR data */
++	uint8 ppr_tlv[1];
++} wlc_clm_power_limits_req_t;
++
++/* Input. Do not apply SAR limits */
++#define WLC_CLM_POWER_LIMITS_INPUT_FLAG_NO_SAR				0x00000001
++/* Input. Do not apply board limits */
++#define WLC_CLM_POWER_LIMITS_INPUT_FLAG_NO_BOARD			0x00000002
++/* Output. Limits taken from product-specific country data */
++#define WLC_CLM_POWER_LIMITS_OUTPUT_FLAG_PRODUCT_LIMITS			0x00000001
++/* Output. Limits taken from product-specific worldwide data */
++#define WLC_CLM_POWER_LIMITS_OUTPUT_FLAG_WORLDWIDE_LIMITS		0x00000002
++/* Output. Limits taken from country-default (all-product) data */
++#define WLC_CLM_POWER_LIMITS_OUTPUT_FLAG_DEFAULT_COUNTRY_LIMITS		0x00000004
++
++/*
++ * WOG (Wake On Googlecast)
++ */
++
++#define MAX_GCAST_APPID_CNT_LIMIT 50
++#define MAX_DNS_LABEL 63
++
++typedef struct wog_appid {
++	uint8 appID[MAX_DNS_LABEL+1];
++} wog_appid_t;
++
++enum {
++	WOG_APPID_ADD,
++	WOG_APPID_DEL,
++	WOG_APPID_CLEAR,
++	WOG_APPID_LIST,
++	WOG_MAX_APPID_CNT
++};
++
++#define WOG_APPID_IOV_VER 1
++typedef struct wog_appid_iov {
++	/* version for iovar */
++	uint32 ver;
++	/* add/del/clear/list operation */
++	uint32 operation;
++	/* for adding or deleting multiple items */
++	/* for WOG_MAX_APPID_CNT, this value is used for max count for AppID */
++	uint32 cnt;
++	/* Application IDs */
++	/* If FW found an AppID from this list, FW will respond to discovery */
++	/* without wake up the host */
++	wog_appid_t appids[1];
++} wog_appid_iov_t;
++
++/* dns service record */
++/* service name : _googlecast */
++typedef struct wog_srv_record {
++	uint32 ttl;
++	uint16 port; /* tcp 8008 or 8009 */
++	uint8 PAD[2];
++} wog_srv_record_t;
++
++#define GCAST_MAX_MODEL_NAME_LEN 16
++#define GCAST_MAX_FNAME_LEN 64
++#define GCAST_MAX_RS_LEN 60
++
++#define GCAST_UUID_LEN 32
++#define GCAST_PUBLICKEY_ID_LEN 64
++#define GCAST_VER_LEN 2
++typedef struct wog_txt_record {
++	uint32 ttl;
++	/* id : UUID for the receiver */
++	char id[GCAST_UUID_LEN+1];
++
++	/* Cast protocol version supported. Begins at 2 */
++	/* and is incremented by 1 with each version */
++	char ver[GCAST_VER_LEN+1];
++
++	/* 256bit receiver Subject Public Key Identifier from the SSL cert */
++	char public_key[GCAST_PUBLICKEY_ID_LEN+1];
++
++	/* A bitfield of device capabilities. */
++	/* bit 0 : video_out (1:has video out, 0:no video) */
++	/* bit 1 : video_in */
++	/* bit 2 : audio_out */
++	/* bit 3 : audio_in */
++	/* bit 4 : dev_mode */
++	/*	 (1:dev mode enabled, 0: not enabled) */
++	char capability;
++
++	/* Receiver status flag 0:IDLE, 1(BUSY/JOIN) */
++	/* IDLE : The receiver is idle */
++	/*	   and doesn't need to be connected now. */
++	/* BUSY/JOIN : The receiver is hosting an activity */
++	/*	 and invites the sender to join */
++	char receiver_status_flag;
++
++	uint8 PAD0[1];
++
++	char friendly_name[GCAST_MAX_FNAME_LEN+1];
++	uint8 PAD1[3];
++
++	char model_name[GCAST_MAX_MODEL_NAME_LEN+1];
++	uint8 PAD2[3];
++
++	/* Receiver Status text for Cast Protocol v2 */
++	/* Spec says that if the status text exceeds 60 characters in length, */
++	/* it is truncated at 60 caracters and */
++	/* a UTF-8 ellipsis character is appended to indicate trucation. */
++	/* But our dongle won't use UTF-8 ellipsis. It's not a big deal. */
++	char receiver_status[GCAST_MAX_RS_LEN+1];
++	uint8 PAD3[3];
++} wog_txt_record_t;
++
++/* ip will be taken from the ip of wog_info_t */
++typedef struct wog_a_record {
++	uint32 ttl;
++} wog_a_record_t;
++
++/* Google Cast protocl uses mDNS SD for its discovery */
++#define WOG_SD_RESP_VER 1
++typedef struct wog_sd_resp {
++	/* version for iovar */
++	int32 ver;
++	/* device name of Google Cast receiver */
++	char device_name[MAX_DNS_LABEL+1];
++	/* IP address of Google Cast receiver */
++	uint8 ip[4];
++	/* ttl of PTR response */
++	uint32 ptr_ttl;
++	/* DNS TXT record */
++	wog_txt_record_t txt;
++	/* DNS SRV record */
++	wog_srv_record_t srv;
++	/* DNS A record */
++	wog_a_record_t a;
++} wog_sd_resp_t;
++
++enum wl_mbo_cmd_ids {
++	WL_MBO_CMD_ADD_CHAN_PREF = 1,
++	WL_MBO_CMD_DEL_CHAN_PREF = 2,
++	WL_MBO_CMD_LIST_CHAN_PREF = 3,
++	WL_MBO_CMD_CELLULAR_DATA_CAP = 4,
++	WL_MBO_CMD_DUMP_COUNTERS = 5,
++	WL_MBO_CMD_CLEAR_COUNTERS = 6,
++	WL_MBO_CMD_FORCE_ASSOC = 7,
++	WL_MBO_CMD_BSSTRANS_REJECT = 8,
++	WL_MBO_CMD_SEND_NOTIF = 9,
++	/* Add before this !! */
++	WL_MBO_CMD_LAST
++};
++
++enum wl_mbo_xtlv_id {
++	WL_MBO_XTLV_OPCLASS            = 0x1,
++	WL_MBO_XTLV_CHAN               = 0x2,
++	WL_MBO_XTLV_PREFERENCE         = 0x3,
++	WL_MBO_XTLV_REASON_CODE        = 0x4,
++	WL_MBO_XTLV_CELL_DATA_CAP      = 0x5,
++	WL_MBO_XTLV_COUNTERS           = 0x6,
++	WL_MBO_XTLV_ENABLE             = 0x7,
++	WL_MBO_XTLV_SUB_ELEM_TYPE      = 0x8
++};
++
++typedef struct wl_mbo_counters {
++	/* No of transition req recvd */
++	uint16 trans_req_rcvd;
++	/* No of transition req with disassoc imminent */
++	uint16 trans_req_disassoc;
++	/* No of transition req with BSS Termination */
++	uint16 trans_req_bss_term;
++	/* No of trans req w/ unspecified reason */
++	uint16 trans_resn_unspec;
++	/* No of trans req w/ reason frame loss */
++	uint16 trans_resn_frm_loss;
++	/* No of trans req w/ reason traffic delay */
++	uint16 trans_resn_traffic_delay;
++	/* No of trans req w/ reason insufficient buffer */
++	uint16 trans_resn_insuff_bw;
++	/* No of trans req w/ reason load balance */
++	uint16 trans_resn_load_bal;
++	/* No of trans req w/ reason low rssi */
++	uint16 trans_resn_low_rssi;
++	/* No of trans req w/ reason excessive retransmission */
++	uint16 trans_resn_xcess_retransmn;
++	/* No of trans req w/ reason gray zone */
++	uint16 trans_resn_gray_zone;
++	/* No of trans req w/ reason switch to premium AP */
++	uint16 trans_resn_prem_ap_sw;
++	/* No of transition rejection sent */
++	uint16 trans_rejn_sent;
++	/* No of trans rejn reason excessive frame loss */
++	uint16 trans_rejn_xcess_frm_loss;
++	/* No of trans rejn reason excessive traffic delay */
++	uint16 trans_rejn_xcess_traffic_delay;
++	/* No of trans rejn reason insufficient QoS capability */
++	uint16 trans_rejn_insuffic_qos_cap;
++	/* No of trans rejn reason low RSSI */
++	uint16 trans_rejn_low_rssi;
++	/* No of trans rejn reason high interference */
++	uint16 trans_rejn_high_interference;
++	/* No of trans rejn reason service unavilable */
++	uint16 trans_rejn_service_unavail;
++	/* No of beacon request rcvd */
++	uint16 bcn_req_rcvd;
++	/* No of beacon report sent */
++	uint16 bcn_rep_sent;
++	/* No of null beacon report sent */
++	uint16 null_bcn_rep_sent;
++	/* No of wifi to cell switch */
++	uint16 wifi_to_cell;
++} wl_mbo_counters_t;
++
++/* otpread command */
++#define WL_OTPREAD_VER 1
++
++typedef struct {
++	uint16 version;		/* cmd structure version */
++	uint16 cmd_len;		/* cmd struct len */
++	uint32 rdmode;		/* otp read mode */
++	uint32 rdoffset;	/* byte offset into otp to start read */
++	uint32 rdsize;		/* number of bytes to read */
++} wl_otpread_cmd_t;
++
++/* "otpecc_rows" command */
++typedef struct {
++	uint16 version;		/* version of this structure */
++	uint16 len;			/* len in bytes of this structure */
++	uint32 cmdtype;		/* command type : 0 : read row data, 1 : ECC lock  */
++	uint32 rowoffset;	/* start row offset */
++	uint32 numrows;		/* number of rows */
++	uint8  rowdata[];	/* read rows data */
++} wl_otpecc_rows_t;
++
++#define WL_OTPECC_ROWS_VER  1
++
++#define WL_OTPECC_ROWS_CMD_READ  0
++#define WL_OTPECC_ROWS_CMD_LOCK  1
++
++#define WL_OTPECC_ARGIDX_CMDTYPE		0	/* command type */
++#define WL_OTPECC_ARGIDX_ROWOFFSET		1	/* start row offset */
++#define WL_OTPECC_ARGIDX_NUMROWS		2	/* number of rows */
++
++/* "otpeccrows" raw data size per row */
++#define WL_ECCDUMP_ROW_SIZE_BYTE	6 /* 4 bytes row data + 2 bytes ECC status */
++#define WL_ECCDUMP_ROW_SIZE_WORD	3
++
++/* otpECCstatus */
++#define OTP_ECC_ENAB_SHIFT		13
++#define OTP_ECC_ENAB_MASK		0x7
++#define OTP_ECC_CORR_ST_SHIFT	12
++#define OTP_ECC_CORR_ST_MASK	0x1
++#define OTP_ECC_DBL_ERR_SHIFT	11
++#define OTP_ECC_DBL_ERR_MASK	0x1
++#define OTP_ECC_DED_ST_SHIFT	10
++#define OTP_ECC_DED_ST_MASK		0x1
++#define OTP_ECC_SEC_ST_SHIFT	9
++#define OTP_ECC_SEC_ST_MASK		0x1
++#define OTP_ECC_DATA_SHIFT		0
++#define OTP_ECC_DATA_MASK		0x7f
++
++/* OTP_ECC_CORR_ST field */
++#define OTP_ECC_MODE		1
++#define OTP_NO_ECC_MODE		0
++
++/* OTP_ECC_ENAB field (bit15:13) :
++ * When 2 or 3 bits are set,
++ * it indicates that OTP ECC is enabled on the last row read.
++ * Otherwise, ECC is disabled
++ */
++#define OTP_ECC_ENAB(val) \
++	(bcm_bitcount((uint8 *)&(val), sizeof(uint8)) > 1)
++
++#define WL_LEAKY_AP_STATS_GT_TYPE	0
++#define WL_LEAKY_AP_STATS_PKT_TYPE	1
++typedef struct wlc_leaked_infra_guard_marker {
++	/* type field for this TLV: WL_LEAKY_AP_STATS_GT_TYPE */
++	uint16  type;
++	/* length field for this TLV */
++	uint16  len;
++	/* guard sample sequence number; Updated by 1 on every guard sample */
++	uint32  seq_number;
++	/* Guard time start time (tsf; PS indicated and acked) */
++	uint32  start_time;
++	/* tsf timestamp for the GT end event */
++	uint32  gt_tsf_l;
++	/* Guard time period in ms */
++	uint16  guard_duration;
++	/* Number PPDUs in the notification */
++	uint16  num_pkts;
++	/* Flags to indicate some states see below */
++	uint8   flag;
++	/* pad for 32-bit alignment */
++	uint8   reserved[3];
++} wlc_leaked_infra_guard_marker_t;
++
++/* Flag information */
++#define WL_LEAKED_GUARD_TIME_NONE	0               /* Not in any guard time */
++#define WL_LEAKED_GUARD_TIME_FRTS	(0x01 << 0)     /* Normal FRTS power save */
++#define WL_LEAKED_GUARD_TIME_SCAN	(0x01 << 1)     /* Channel switch due to scanning */
++#define WL_LEAKED_GUARD_TIME_AWDL_PSF	(0x01 << 2)     /* Channel switch due to AWDL PSF */
++#define WL_LEAKED_GUARD_TIME_AWDL_AW	(0x01 << 3)     /* Channel switch due to AWDL AW */
++#define WL_LEAKED_GUARD_TIME_INFRA_STA	(0x01 << 4)	/* generic type infra sta channel switch */
++#define WL_LEAKED_GUARD_TIME_TERMINATED (0x01 << 7)     /* indicate a GT is terminated early */
++
++typedef struct wlc_leaked_infra_packet_stat {
++	uint16  type;			/* type field for this TLV: WL_LEAKY_AP_STATS_PKT_TYPE */
++	uint16  len;			/* length field for this TLV */
++	uint16  ppdu_len_bytes;		/* PPDU packet length in bytes */
++	uint16  num_mpdus;		/* number of the MPDUs in the PPDU */
++	uint32  ppdu_time;		/* PPDU arrival time at the begining of the guard time */
++	uint32  rate;			/* PPDU packet rate; Received packet's data rate */
++	uint16  seq_number;		/* sequence number */
++	int8    rssi;			/* RSSI */
++	uint8   tid;			/* tid */
++} wlc_leaked_infra_packet_stat_t;
++
++/* Wake timer structure definition */
++#define WAKE_TIMER_VERSION 1
++#define WAKE_TIMER_NOLIMIT 0xFFFF
++
++typedef struct wake_timer {
++	uint16 ver;
++	uint16 len;
++	uint16 limit;   /* number of events to deliver
++			* 0-disable, 0xffff-indefinite, num_events otherwise
++			*/
++	uint16 count;	/* number of events delivered since enable (get only) */
++	uint16 period;	/* timeout/period in milliseconds */
++} wake_timer_t;
++
++typedef struct wl_desense_restage_gain {
++	uint16 version;
++	uint16 length;
++	uint32 band;
++	uint8 num_cores;
++	uint8 desense_array[WL_TX_CHAINS_MAX];
++	uint8 PAD[3];
++} wl_desense_restage_gain_t;
++
++#define MAX_UCM_CHAINS 5
++#define MAX_UCM_PROFILES 4
++#define UCM_PROFILE_VERSION_1 1
++
++/* UCM per chain attribute struct */
++typedef struct wlc_btcx_chain_attr {
++	uint16 length;			/* chain attr length, version is same as profile version */
++	int8 desense_level;		/* per chain desense level */
++	int8 ack_pwr_strong_rssi;	/* per chain ack power at strong rssi */
++	int8 ack_pwr_weak_rssi;		/* per chain ack power at weak rssi */
++	int8 tx_pwr_strong_rssi;	/* per chain tx power at strong rssi */
++	int8 tx_pwr_weak_rssi;		/* per chain tx power at weak rssi */
++	uint8 PAD[1];			/* additional bytes for alignment */
++} wlc_btcx_chain_attr_t;
++
++typedef struct wlc_btcx_profile_v1 {
++	uint16 version;			/* UCM profile version */
++	uint16 length;			/* profile size */
++	uint16 fixed_length;		/* size of the fixed portion of the profile */
++	uint8 init;			/* profile initialized or not */
++	uint8 chain_attr_count;		/* Number of elements in chain_attr array */
++	uint8 profile_index;		/* profile index */
++	uint8 mode_strong_wl_bt;	/* Mode under strong WLAN and BT RSSI */
++	uint8 mode_weak_wl;		/* Mode under weak WLAN RSSI */
++	uint8 mode_weak_bt;		/* Mode under weak BT RSSI */
++	uint8 mode_weak_wl_bt;		/* Mode under weak BT and WLAN RSSI */
++	int8 mode_wl_hi_lo_rssi_thresh;	/* Strong to weak WLAN RSSI threshold for mode selection */
++	int8 mode_wl_lo_hi_rssi_thresh;	/* Weak to strong WLAN RSSI threshold for mode selection */
++	int8 mode_bt_hi_lo_rssi_thresh;	/* Strong to weak BT RSSI threshold for mode selection */
++	int8 mode_bt_lo_hi_rssi_thresh;	/* Weak to strong BT RSSI threshold for mode selection */
++	int8 desense_wl_hi_lo_rssi_thresh;	/* Strong to weak RSSI threshold for desense */
++	int8 desense_wl_lo_hi_rssi_thresh;	/* Weak to strong RSSI threshold for desense */
++	int8 ack_pwr_wl_hi_lo_rssi_thresh;	/* Strong to weak RSSI threshold for ACK power */
++	int8 ack_pwr_wl_lo_hi_rssi_thresh;	/* Weak to strong RSSI threshold for ACK power */
++	int8 tx_pwr_wl_hi_lo_rssi_thresh;	/* Strong to weak RSSI threshold for Tx power */
++	int8 tx_pwr_wl_lo_hi_rssi_thresh;	/* Weak to strong RSSI threshold for Tx power */
++	uint8 PAD[1];				/* additional bytes for 4 byte alignment */
++	wlc_btcx_chain_attr_t chain_attr[];	/* variable length array with chain attributes */
++} wlc_btcx_profile_v1_t;
++
++#define SSSR_D11_RESET_SEQ_STEPS   5
++#define SSSR_REG_INFO_VER   0
++
++typedef struct sssr_reg_info {
++	uint16 version;
++	uint16 length;  /* length of the structure validated at host */
++	struct {
++		struct {
++			uint32 pmuintmask0;
++			uint32 pmuintmask1;
++			uint32 resreqtimer;
++			uint32 macresreqtimer;
++			uint32 macresreqtimer1;
++		} base_regs;
++	} pmu_regs;
++	struct {
++		struct {
++			uint32 intmask;
++			uint32 powerctrl;
++			uint32 clockcontrolstatus;
++			uint32 powerctrl_mask;
++		} base_regs;
++	} chipcommon_regs;
++	struct {
++		struct {
++			uint32 clockcontrolstatus;
++			uint32 clockcontrolstatus_val;
++		} base_regs;
++		struct {
++			uint32 resetctrl;
++			uint32 itopoobb;
++		} wrapper_regs;
++	} arm_regs;
++	struct {
++		struct {
++			uint32 ltrstate;
++			uint32 clockcontrolstatus;
++			uint32 clockcontrolstatus_val;
++		} base_regs;
++		struct {
++			uint32 itopoobb;
++		} wrapper_regs;
++	} pcie_regs;
++	struct {
++		struct {
++			uint32 ioctrl;
++		} wrapper_regs;
++		uint32 vasip_sr_addr;
++		uint32 vasip_sr_size;
++	} vasip_regs;
++	struct {
++		struct {
++			uint32 xmtaddress;
++			uint32 xmtdata;
++			uint32 clockcontrolstatus;
++			uint32 clockcontrolstatus_val;
++		} base_regs;
++		struct {
++			uint32 resetctrl;
++			uint32 itopoobb;
++			uint32 ioctrl;
++			uint32 ioctrl_resetseq_val[SSSR_D11_RESET_SEQ_STEPS];
++		} wrapper_regs;
++		uint32 sr_size;
++	} mac_regs[MAX_NUM_D11CORES];
++} sssr_reg_info_t;
++
++/* ADaptive Power Save(ADPS) structure definition */
++#define WL_ADPS_IOV_MAJOR_VER	1
++#define WL_ADPS_IOV_MINOR_VER	0
++#define WL_ADPS_IOV_MAJOR_VER_SHIFT	8
++#define WL_ADPS_IOV_VER \
++	((WL_ADPS_IOV_MAJOR_VER << WL_ADPS_IOV_MAJOR_VER_SHIFT) | WL_ADPS_IOV_MINOR_VER)
++
++#define ADPS_NUM_DIR	2
++#define ADPS_RX		0
++#define ADPS_TX		1
++
++#define WL_ADPS_IOV_MODE	0x0001
++#define WL_ADPS_IOV_RSSI	0x0002
++#define WL_ADPS_IOV_DUMP	0x0003
++#define WL_ADPS_IOV_DUMP_CLEAR	0x0004
++
++#define ADPS_SUMMARY_STEP_NUM   2
++#define ADPS_SUMMARY_STEP_LOW	0
++#define ADPS_SUMMARY_STEP_HIGH	1
++
++#define ADPS_SUB_IOV_VERSION_1	1
++#define ADPS_SUB_IOV_VERSION_2	2
++
++typedef struct wl_adps_params_v1 {
++	uint16 version;
++	uint16 length;
++	uint8 band;		/* band - 2G or 5G */
++	uint8 mode;		/* operation mode, default = 0 (ADPS disable) */
++	uint16 padding;
++} wl_adps_params_v1_t;
++
++typedef struct wl_adps_rssi {
++	int32 thresh_hi;	/* rssi threshold to resume ADPS operation */
++	int32 thresh_lo;	/* rssi threshold to suspend ADPS operation */
++} wl_adps_rssi_t;
++
++typedef struct wl_adps_rssi_params_v1 {
++	uint16 version;
++	uint16 length;
++	uint8 band;
++	uint8 padding[3];
++	wl_adps_rssi_t rssi;
++} wl_adps_rssi_params_v1_t;
++
++typedef struct adps_stat_elem {
++	uint32 duration;	/* each step duration time (mSec) */
++	uint32 counts;		/* each step hit count number */
++} adps_stat_elem_t;
++
++typedef struct wl_adps_dump_summary_v1 {
++	uint16 version;
++	uint16 length;
++	uint8 mode;					/* operation mode: On/Off */
++	uint8 flags;					/* restrict flags */
++	uint8 current_step;				/* current step */
++	uint8 padding;
++	adps_stat_elem_t stat[ADPS_SUMMARY_STEP_NUM];	/* statistics */
++} wl_adps_dump_summary_v1_t;
++
++typedef struct wlc_btc_2gchain_dis {
++	uint16 ver;
++	uint16 len;
++	uint8 chain_dis;
++	uint8 flag;
++} wlc_btc_2gchain_dis_t;
++
++#define WLC_BTC_2GCHAIN_DIS_REASSOC	0x1
++#define WLC_BTC_2GCHAIN_DIS_VER1	0x1
++#define WLC_BTC_2GCHAIN_DIS_VER1_LEN	6
++
++enum wl_rpsnoa_cmd_ids {
++	WL_RPSNOA_CMD_ENABLE = 1,
++	WL_RPSNOA_CMD_STATUS,
++	WL_RPSNOA_CMD_PARAMS,
++	WL_RPSNOA_CMD_LAST
++};
++
++typedef struct rpsnoa_cmnhdr {
++	uint16 ver;		/* cmd structure version */
++	uint16 len;		/* cmd structure len */
++	uint32 subcmd;
++	uint32 cnt;
++} rpsnoa_cmnhdr_t;
++
++typedef struct rpsnoa_data {
++	int16 band;
++	int16 value;
++} rpsnoa_data_t;
++
++typedef struct rpsnoa_param {
++	uint16 band;
++	uint8 level;
++	uint8 stas_assoc_check;
++	uint32 pps;
++	uint32 quiet_time;
++} rpsnoa_param_t;
++
++typedef struct rpsnoa_iovar {
++	rpsnoa_cmnhdr_t hdr;
++	rpsnoa_data_t data[1];
++} rpsnoa_iovar_t;
++
++typedef struct rpsnoa_iovar_params {
++	rpsnoa_cmnhdr_t hdr;
++	rpsnoa_param_t param[1];
++} rpsnoa_iovar_params_t;
++
++/* Per-interface reportable stats types */
++enum wl_ifstats_xtlv_id {
++	/* global */
++	WL_IFSTATS_XTLV_SLICE_INDEX = 1,
++	WL_IFSTATS_XTLV_IF_INDEX = 2,
++	WL_IFSTATS_XTLV_MAC_ADDR = 3,
++	WL_IFSTATS_XTLV_REPORT_CMD = 4,	/* Comes in an iovar */
++	WL_IFSTATS_XTLV_BUS_PCIE = 5,
++
++	/* Report data across all SCBs using ecounters */
++	WL_IFSTATS_XTLV_WL_STA_INFO_ECOUNTERS = 0x100,
++
++	/* Per-slice information
++	 * Per-interface reporting could also include slice specific data
++	 */
++	/* xtlv container for reporting */
++	WL_IFSTATS_XTLV_WL_SLICE = 0x301,
++	/* Per-slice AMPDU stats */
++	WL_IFSTATS_XTLV_WL_SLICE_AMPDU_DUMP = 0x302,
++	/* Per-slice BTCOEX stats */
++	WL_IFSTATS_XTLV_WL_SLICE_BTCOEX = 0x303,
++	/* V11_WLCNTRS used in ecounters */
++	WL_IFSTATS_XTLV_WL_SLICE_V11_WLCNTRS = 0x304,
++	/* V30_WLCNTRS Used in ecounters */
++	WL_IFSTATS_XTLV_WL_SLICE_V30_WLCNTRS = 0x305,
++
++	/* Per-interface */
++	/* XTLV container for reporting */
++	WL_IFSTATS_XTLV_IF = 0x501,
++	/* Generic stats applicable to all IFs */
++	WL_IFSTATS_XTLV_GENERIC = 0x502,
++	/* Infra specific */
++	WL_IFSTATS_XTLV_INFRA_SPECIFIC = 0x503,
++	/* MGT counters infra and softAP */
++	WL_IFSTATS_XTLV_MGT_CNT = 0x504,
++	/* AMPDU stats on per-IF */
++	WL_IFSTATS_XTLV_AMPDU_DUMP = 0x505,
++	WL_IFSTATS_XTLV_IF_SPECIFIC = 0x506
++};
++
++/* interface specific mgt count */
++#define WL_MGT_STATS_VERSION_V1	1
++/* Associated stats type: WL_IFSTATS_MGT_CNT */
++typedef struct {
++	uint16	version;
++	uint8   pad[2];
++
++	/* detailed control/management frames */
++	uint32	txnull;
++	uint32	rxnull;
++	uint32	txqosnull;
++	uint32	rxqosnull;
++	uint32	txassocreq;
++	uint32	rxassocreq;
++	uint32	txreassocreq;
++	uint32	rxreassocreq;
++	uint32	txdisassoc;
++	uint32	rxdisassoc;
++	uint32	txassocrsp;
++	uint32	rxassocrsp;
++	uint32	txreassocrsp;
++	uint32	rxreassocrsp;
++	uint32	txauth;
++	uint32	rxauth;
++	uint32	txdeauth;
++	uint32	rxdeauth;
++	uint32	txprobereq;
++	uint32	rxprobereq;
++	uint32	txprobersp;
++	uint32	rxprobersp;
++	uint32	txaction;
++	uint32	rxaction;
++	uint32	txpspoll;
++	uint32	rxpspoll;
++} wl_if_mgt_stats_t;
++
++#define WL_INFRA_STATS_VERSION_V1	1
++/* Associated stats type: WL_IFSTATS_INFRA_SPECIFIC */
++typedef struct wl_infra_stats {
++	uint16 version;             /**< version of the structure */
++	uint8  pad[2];
++	uint32 rxbeaconmbss;
++	uint32 tbtt;
++} wl_if_infra_stats_t;
++
++typedef struct csa_event_data {
++	chanspec_t chan_old;
++	dot11_ext_csa_ie_t ecsa;
++	dot11_mesh_csp_ie_t mcsp;
++	dot11_wide_bw_chan_switch_ie_t wbcs;
++	uint8 PAD;
++} csa_event_data_t;
++
++#endif /* _wlioctl_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/wlioctl_defs.h b/module_drivers/drivers/net/wireless/bcmdhd/include/wlioctl_defs.h
+new file mode 100644
+index 000000000..de0fb1d3e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/wlioctl_defs.h
+@@ -0,0 +1,2243 @@
++/*
++ * Custom OID/ioctl definitions for
++ * Broadcom 802.11abg Networking Device Driver
++ *
++ * Definitions subject to change without notice.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wlioctl_defs.h 677667 2017-01-04 07:43:05Z $
++ */
++
++
++#ifndef wlioctl_defs_h
++#define wlioctl_defs_h
++
++
++
++
++/* All builds use the new 11ac ratespec/chanspec */
++#undef  D11AC_IOTYPES
++#define D11AC_IOTYPES
++
++#ifndef USE_NEW_RSPEC_DEFS
++/* WL_RSPEC defines for rate information */
++#define WL_RSPEC_RATE_MASK		0x000000FF      /* rate or HT MCS value */
++#define WL_RSPEC_HE_MCS_MASK		0x0000000F      /* HE MCS value */
++#define WL_RSPEC_HE_NSS_MASK		0x000000F0      /* HE Nss value */
++#define WL_RSPEC_HE_NSS_SHIFT		4               /* HE Nss value shift */
++#define WL_RSPEC_VHT_MCS_MASK		0x0000000F      /* VHT MCS value */
++#define WL_RSPEC_VHT_NSS_MASK		0x000000F0      /* VHT Nss value */
++#define WL_RSPEC_VHT_NSS_SHIFT		4               /* VHT Nss value shift */
++#define WL_RSPEC_TXEXP_MASK		0x00000300
++#define WL_RSPEC_TXEXP_SHIFT		8
++#define WL_RSPEC_BW_MASK		0x00070000      /* bandwidth mask */
++#define WL_RSPEC_BW_SHIFT		16              /* bandwidth shift */
++#define WL_RSPEC_STBC			0x00100000      /* STBC encoding, Nsts = 2 x Nss */
++#define WL_RSPEC_TXBF			0x00200000      /* bit indicates TXBF mode */
++#define WL_RSPEC_LDPC			0x00400000      /* bit indicates adv coding in use */
++#define WL_RSPEC_SGI			0x00800000      /* Short GI mode */
++#define WL_RSPEC_ENCODING_MASK		0x03000000      /* Encoding of Rate/MCS field */
++#define WL_RSPEC_OVERRIDE_RATE		0x40000000      /* bit indicate to override mcs only */
++#define WL_RSPEC_OVERRIDE_MODE		0x80000000      /* bit indicates override rate & mode */
++
++/* WL_RSPEC_ENCODING field defs */
++#define WL_RSPEC_ENCODE_RATE	0x00000000      /* Legacy rate is stored in RSPEC_RATE_MASK */
++#define WL_RSPEC_ENCODE_HT	0x01000000      /* HT MCS is stored in RSPEC_RATE_MASK */
++#define WL_RSPEC_ENCODE_VHT	0x02000000      /* VHT MCS and Nss is stored in RSPEC_RATE_MASK */
++#define WL_RSPEC_ENCODE_HE	0x03000000      /* HE MCS and Nss is stored in RSPEC_RATE_MASK */
++
++/* WL_RSPEC_BW field defs */
++#define WL_RSPEC_BW_UNSPECIFIED 0
++#define WL_RSPEC_BW_20MHZ       0x00010000
++#define WL_RSPEC_BW_40MHZ       0x00020000
++#define WL_RSPEC_BW_80MHZ       0x00030000
++#define WL_RSPEC_BW_160MHZ      0x00040000
++#define WL_RSPEC_BW_10MHZ	0x00050000
++#define WL_RSPEC_BW_5MHZ	0x00060000
++#define WL_RSPEC_BW_2P5MHZ      0x00070000
++
++#define HIGHEST_SINGLE_STREAM_MCS	7 /* MCS values greater than this enable multiple streams */
++
++#endif /* !USE_NEW_RSPEC_DEFS */
++
++/* Legacy defines for the nrate iovar */
++#define OLD_NRATE_MCS_INUSE         0x00000080 /* MSC in use,indicates b0-6 holds an mcs */
++#define OLD_NRATE_RATE_MASK         0x0000007f /* rate/mcs value */
++#define OLD_NRATE_STF_MASK          0x0000ff00 /* stf mode mask: siso, cdd, stbc, sdm */
++#define OLD_NRATE_STF_SHIFT         8          /* stf mode shift */
++#define OLD_NRATE_OVERRIDE          0x80000000 /* bit indicates override both rate & mode */
++#define OLD_NRATE_OVERRIDE_MCS_ONLY 0x40000000 /* bit indicate to override mcs only */
++#define OLD_NRATE_SGI               0x00800000 /* sgi mode */
++#define OLD_NRATE_LDPC_CODING       0x00400000 /* bit indicates adv coding in use */
++
++#define OLD_NRATE_STF_SISO	0		/* stf mode SISO */
++#define OLD_NRATE_STF_CDD	1		/* stf mode CDD */
++#define OLD_NRATE_STF_STBC	2		/* stf mode STBC */
++#define OLD_NRATE_STF_SDM	3		/* stf mode SDM */
++
++#define WLC_11N_N_PROP_MCS	6
++#define WLC_11N_FIRST_PROP_MCS	87
++#define WLC_11N_LAST_PROP_MCS	102
++
++#define MAX_CCA_CHANNELS 38	/* Max number of 20 Mhz wide channels */
++#define MAX_CCA_SECS	60	/* CCA keeps this many seconds history */
++
++#define IBSS_MED        15	/* Mediom in-bss congestion percentage */
++#define IBSS_HI         25	/* Hi in-bss congestion percentage */
++#define OBSS_MED        12
++#define OBSS_HI         25
++#define INTERFER_MED    5
++#define INTERFER_HI     10
++
++#define  CCA_FLAG_2G_ONLY		0x01	/* Return a channel from 2.4 Ghz band */
++#define  CCA_FLAG_5G_ONLY		0x02	/* Return a channel from 2.4 Ghz band */
++#define  CCA_FLAG_IGNORE_DURATION	0x04	/* Ignore dwell time for each channel */
++#define  CCA_FLAGS_PREFER_1_6_11	0x10
++#define  CCA_FLAG_IGNORE_INTERFER 	0x20 /* do not exlude channel based on interfer level */
++
++#define CCA_ERRNO_BAND 		1	/* After filtering for band pref, no choices left */
++#define CCA_ERRNO_DURATION	2	/* After filtering for duration, no choices left */
++#define CCA_ERRNO_PREF_CHAN	3	/* After filtering for chan pref, no choices left */
++#define CCA_ERRNO_INTERFER	4	/* After filtering for interference, no choices left */
++#define CCA_ERRNO_TOO_FEW	5	/* Only 1 channel was input */
++
++#define WL_STA_AID(a)		((a) &~ 0xc000)
++
++/* Flags for sta_info_t indicating properties of STA */
++#define WL_STA_BRCM		0x00000001	/* Running a Broadcom driver */
++#define WL_STA_WME		0x00000002	/* WMM association */
++#define WL_STA_NONERP		0x00000004	/* No ERP */
++#define WL_STA_AUTHE		0x00000008	/* Authenticated */
++#define WL_STA_ASSOC		0x00000010	/* Associated */
++#define WL_STA_AUTHO		0x00000020	/* Authorized */
++#define WL_STA_WDS		0x00000040	/* Wireless Distribution System */
++#define WL_STA_WDS_LINKUP	0x00000080	/* WDS traffic/probes flowing properly */
++#define WL_STA_PS		0x00000100	/* STA is in power save mode from AP's viewpoint */
++#define WL_STA_APSD_BE		0x00000200	/* APSD delv/trigger for AC_BE is default enabled */
++#define WL_STA_APSD_BK		0x00000400	/* APSD delv/trigger for AC_BK is default enabled */
++#define WL_STA_APSD_VI		0x00000800	/* APSD delv/trigger for AC_VI is default enabled */
++#define WL_STA_APSD_VO		0x00001000	/* APSD delv/trigger for AC_VO is default enabled */
++#define WL_STA_N_CAP		0x00002000	/* STA 802.11n capable */
++#define WL_STA_SCBSTATS		0x00004000	/* Per STA debug stats */
++#define WL_STA_AMPDU_CAP	0x00008000	/* STA AMPDU capable */
++#define WL_STA_AMSDU_CAP	0x00010000	/* STA AMSDU capable */
++#define WL_STA_MIMO_PS		0x00020000	/* mimo ps mode is enabled */
++#define WL_STA_MIMO_RTS		0x00040000	/* send rts in mimo ps mode */
++#define WL_STA_RIFS_CAP		0x00080000	/* rifs enabled */
++#define WL_STA_VHT_CAP		0x00100000	/* STA VHT(11ac) capable */
++#define WL_STA_WPS		0x00200000	/* WPS state */
++#define WL_STA_DWDS_CAP		0x01000000	/* DWDS CAP */
++#define WL_STA_DWDS		0x02000000	/* DWDS active */
++#define WL_WDS_LINKUP		WL_STA_WDS_LINKUP	/* deprecated */
++
++/* STA HT cap fields */
++#define WL_STA_CAP_LDPC_CODING		0x0001	/* Support for rx of LDPC coded pkts */
++#define WL_STA_CAP_40MHZ		0x0002  /* FALSE:20Mhz, TRUE:20/40MHZ supported */
++#define WL_STA_CAP_MIMO_PS_MASK		0x000C  /* Mimo PS mask */
++#define WL_STA_CAP_MIMO_PS_SHIFT	0x0002	/* Mimo PS shift */
++#define WL_STA_CAP_MIMO_PS_OFF		0x0003	/* Mimo PS, no restriction */
++#define WL_STA_CAP_MIMO_PS_RTS		0x0001	/* Mimo PS, send RTS/CTS around MIMO frames */
++#define WL_STA_CAP_MIMO_PS_ON		0x0000	/* Mimo PS, MIMO disallowed */
++#define WL_STA_CAP_GF			0x0010	/* Greenfield preamble support */
++#define WL_STA_CAP_SHORT_GI_20		0x0020	/* 20MHZ short guard interval support */
++#define WL_STA_CAP_SHORT_GI_40		0x0040	/* 40Mhz short guard interval support */
++#define WL_STA_CAP_TX_STBC		0x0080	/* Tx STBC support */
++#define WL_STA_CAP_RX_STBC_MASK		0x0300	/* Rx STBC mask */
++#define WL_STA_CAP_RX_STBC_SHIFT	8	/* Rx STBC shift */
++#define WL_STA_CAP_DELAYED_BA		0x0400	/* delayed BA support */
++#define WL_STA_CAP_MAX_AMSDU		0x0800	/* Max AMSDU size in bytes , 0=3839, 1=7935 */
++#define WL_STA_CAP_DSSS_CCK		0x1000	/* DSSS/CCK supported by the BSS */
++#define WL_STA_CAP_PSMP			0x2000	/* Power Save Multi Poll support */
++#define WL_STA_CAP_40MHZ_INTOLERANT	0x4000	/* 40MHz Intolerant */
++#define WL_STA_CAP_LSIG_TXOP		0x8000	/* L-SIG TXOP protection support */
++
++#define WL_STA_CAP_RX_STBC_NO		0x0	/* no rx STBC support */
++#define WL_STA_CAP_RX_STBC_ONE_STREAM	0x1	/* rx STBC support of 1 spatial stream */
++#define WL_STA_CAP_RX_STBC_TWO_STREAM	0x2	/* rx STBC support of 1-2 spatial streams */
++#define WL_STA_CAP_RX_STBC_THREE_STREAM	0x3	/* rx STBC support of 1-3 spatial streams */
++
++/* scb vht flags */
++#define WL_STA_VHT_LDPCCAP	0x0001
++#define WL_STA_SGI80		0x0002
++#define WL_STA_SGI160		0x0004
++#define WL_STA_VHT_TX_STBCCAP	0x0008
++#define WL_STA_VHT_RX_STBCCAP	0x0010
++#define WL_STA_SU_BEAMFORMER	0x0020
++#define WL_STA_SU_BEAMFORMEE	0x0040
++#define WL_STA_MU_BEAMFORMER	0x0080
++#define WL_STA_MU_BEAMFORMEE	0x0100
++#define WL_STA_VHT_TXOP_PS	0x0200
++#define WL_STA_HTC_VHT_CAP	0x0400
++
++/* Values for TX Filter override mode */
++#define WLC_TXFILTER_OVERRIDE_DISABLED  0
++#define WLC_TXFILTER_OVERRIDE_ENABLED   1
++
++#define WL_IOCTL_ACTION_GET		0x0
++#define WL_IOCTL_ACTION_SET		0x1
++#define WL_IOCTL_ACTION_OVL_IDX_MASK	0x1e
++#define WL_IOCTL_ACTION_OVL_RSV		0x20
++#define WL_IOCTL_ACTION_OVL		0x40
++#define WL_IOCTL_ACTION_MASK		0x7e
++#define WL_IOCTL_ACTION_OVL_SHIFT	1
++
++/* For WLC_SET_INFRA ioctl & infra_configuration iovar SET/GET operations */
++#define WL_BSSTYPE_INDEP 0
++#define WL_BSSTYPE_INFRA 1
++#define WL_BSSTYPE_ANY   2	/* deprecated */
++#define WL_BSSTYPE_MESH  3
++/* Bitmask for scan_type */
++#define WL_SCANFLAGS_PASSIVE	0x01	/* force passive scan */
++#define WL_SCANFLAGS_RESERVED	0x02	/* Reserved */
++#define WL_SCANFLAGS_PROHIBITED	0x04	/* allow scanning prohibited channels */
++#define WL_SCANFLAGS_OFFCHAN	0x08	/* allow scanning/reporting off-channel APs */
++#define WL_SCANFLAGS_HOTSPOT	0x10	/* automatic ANQP to hotspot APs */
++#define WL_SCANFLAGS_SWTCHAN	0x20	/* Force channel switch for differerent bandwidth */
++#define WL_SCANFLAGS_FORCE_PARALLEL 0x40 /* Force parallel scan even when actcb_fn_t is on.
++					  * by default parallel scan will be disabled if actcb_fn_t
++					  * is provided.
++					  */
++#define WL_SCANFLAGS_SISO	0x40	/* Use 1 RX chain for scanning */
++#define WL_SCANFLAGS_MIMO	0x80	/* Force MIMO scanning */
++
++/* wl_iscan_results status values */
++#define WL_SCAN_RESULTS_SUCCESS	0
++#define WL_SCAN_RESULTS_PARTIAL	1
++#define WL_SCAN_RESULTS_PENDING	2
++#define WL_SCAN_RESULTS_ABORTED	3
++#define WL_SCAN_RESULTS_NO_MEM  4
++
++#define SCANOL_ENABLED			(1 << 0)
++#define SCANOL_BCAST_SSID		(1 << 1)
++#define SCANOL_NOTIFY_BCAST_SSID	(1 << 2)
++#define SCANOL_RESULTS_PER_CYCLE	(1 << 3)
++
++/* scan times in milliseconds */
++#define SCANOL_HOME_TIME		45	/* for home channel processing */
++#define SCANOL_ASSOC_TIME		20	/* dwell on a channel while associated */
++#define SCANOL_UNASSOC_TIME		40	/* dwell on a channel while unassociated */
++#define SCANOL_PASSIVE_TIME		110	/* listen on a channelfor passive scan */
++#define SCANOL_AWAY_LIMIT		100	/* max time to be away from home channel */
++#define SCANOL_IDLE_REST_TIME		40
++#define SCANOL_IDLE_REST_MULTIPLIER	0
++#define SCANOL_ACTIVE_REST_TIME		20
++#define SCANOL_ACTIVE_REST_MULTIPLIER	0
++#define SCANOL_CYCLE_IDLE_REST_TIME	300000	/* Idle Rest Time between Scan Cycle (msec) */
++#define SCANOL_CYCLE_IDLE_REST_MULTIPLIER	0	/* Idle Rest Time Multiplier */
++#define SCANOL_CYCLE_ACTIVE_REST_TIME	200
++#define SCANOL_CYCLE_ACTIVE_REST_MULTIPLIER	0
++#define SCANOL_MAX_REST_TIME		3600000	/* max rest time between scan cycle (msec) */
++#define SCANOL_CYCLE_DEFAULT		0	/* default for Max Scan Cycle, 0 = forever */
++#define SCANOL_CYCLE_MAX		864000	/* Max Scan Cycle */
++						/* 10 sec/scan cycle => 100 days */
++#define SCANOL_NPROBES			2	/* for Active scan; send n probes on each channel */
++#define SCANOL_NPROBES_MAX		5	/* for Active scan; send n probes on each channel */
++#define SCANOL_SCAN_START_DLY		10	/* delay start of offload scan (sec) */
++#define SCANOL_SCAN_START_DLY_MAX	240	/* delay start of offload scan (sec) */
++#define SCANOL_MULTIPLIER_MAX		10	/* Max Multiplier */
++#define SCANOL_UNASSOC_TIME_MAX		100	/* max dwell on a channel while unassociated */
++#define SCANOL_PASSIVE_TIME_MAX		500	/* max listen on a channel for passive scan */
++#define SCANOL_SSID_MAX			16	/* max supported preferred SSID */
++
++/* masks for channel and ssid count */
++#define WL_SCAN_PARAMS_COUNT_MASK 0x0000ffff
++#define WL_SCAN_PARAMS_NSSID_SHIFT 16
++
++#define WL_SCAN_ACTION_START      1
++#define WL_SCAN_ACTION_CONTINUE   2
++#define WL_SCAN_ACTION_ABORT      3
++
++#define ANTENNA_NUM_1	1		/* total number of antennas to be used */
++#define ANTENNA_NUM_2	2
++#define ANTENNA_NUM_3	3
++#define ANTENNA_NUM_4	4
++
++#define ANT_SELCFG_AUTO		0x80	/* bit indicates antenna sel AUTO */
++#define ANT_SELCFG_MASK		0x33	/* antenna configuration mask */
++#define ANT_SELCFG_TX_UNICAST	0	/* unicast tx antenna configuration */
++#define ANT_SELCFG_RX_UNICAST	1	/* unicast rx antenna configuration */
++#define ANT_SELCFG_TX_DEF	2	/* default tx antenna configuration */
++#define ANT_SELCFG_RX_DEF	3	/* default rx antenna configuration */
++
++/* interference source detection and identification mode */
++#define ITFR_MODE_DISABLE	0	/* disable feature */
++#define ITFR_MODE_MANUAL_ENABLE	1	/* enable manual detection */
++#define ITFR_MODE_AUTO_ENABLE	2	/* enable auto detection */
++
++/* bit definitions for flags in interference source report */
++#define ITFR_INTERFERENCED	1	/* interference detected */
++#define ITFR_HOME_CHANNEL	2	/* home channel has interference */
++#define ITFR_NOISY_ENVIRONMENT	4	/* noisy environemnt so feature stopped */
++
++#define WL_NUM_RPI_BINS		8
++#define WL_RM_TYPE_BASIC	1
++#define WL_RM_TYPE_CCA		2
++#define WL_RM_TYPE_RPI		3
++#define WL_RM_TYPE_ABORT	-1	/* ABORT any in-progress RM request */
++
++#define WL_RM_FLAG_PARALLEL	(1<<0)
++
++#define WL_RM_FLAG_LATE		(1<<1)
++#define WL_RM_FLAG_INCAPABLE	(1<<2)
++#define WL_RM_FLAG_REFUSED	(1<<3)
++
++/* flags */
++#define WLC_ASSOC_REQ_IS_REASSOC 0x01 /* assoc req was actually a reassoc */
++
++#define WLC_CIS_DEFAULT	0	/* built-in default */
++#define WLC_CIS_SROM	1	/* source is sprom */
++#define WLC_CIS_OTP	2	/* source is otp */
++
++/* PCL - Power Control Loop */
++/* current gain setting is replaced by user input */
++#define WL_ATTEN_APP_INPUT_PCL_OFF	0	/* turn off PCL, apply supplied input */
++#define WL_ATTEN_PCL_ON			1	/* turn on PCL */
++/* current gain setting is maintained */
++#define WL_ATTEN_PCL_OFF		2	/* turn off PCL. */
++
++/* defines used by poweridx iovar - it controls power in a-band */
++/* current gain setting is maintained */
++#define WL_PWRIDX_PCL_OFF	-2	/* turn off PCL.  */
++#define WL_PWRIDX_PCL_ON	-1	/* turn on PCL */
++#define WL_PWRIDX_LOWER_LIMIT	-2	/* lower limit */
++#define WL_PWRIDX_UPPER_LIMIT	63	/* upper limit */
++/* value >= 0 causes
++ *	- input to be set to that value
++ *	- PCL to be off
++ */
++
++#define BCM_MAC_STATUS_INDICATION	(0x40010200L)
++
++/* Values for TX Filter override mode */
++#define WLC_TXFILTER_OVERRIDE_DISABLED  0
++#define WLC_TXFILTER_OVERRIDE_ENABLED   1
++
++/* magic pattern used for mismatch driver and wl */
++#define WL_TXFIFO_SZ_MAGIC	0xa5a5
++
++/* check this magic number */
++#define WLC_IOCTL_MAGIC		0x14e46c77
++
++
++/* bss_info_cap_t flags */
++#define WL_BSS_FLAGS_FROM_BEACON	0x01	/* bss_info derived from beacon */
++#define WL_BSS_FLAGS_FROM_CACHE		0x02	/* bss_info collected from cache */
++#define WL_BSS_FLAGS_RSSI_ONCHANNEL	0x04	/* rssi info received on channel (vs offchannel) */
++#define WL_BSS_FLAGS_HS20		0x08	/* hotspot 2.0 capable */
++#define WL_BSS_FLAGS_RSSI_INVALID	0x10	/* BSS contains invalid RSSI */
++#define WL_BSS_FLAGS_RSSI_INACCURATE	0x20	/* BSS contains inaccurate RSSI */
++#define WL_BSS_FLAGS_SNR_INVALID	0x40	/* BSS contains invalid SNR */
++#define WL_BSS_FLAGS_NF_INVALID		0x80	/* BSS contains invalid noise floor */
++
++/* bit definitions for bcnflags in wl_bss_info */
++#define WL_BSS_BCNFLAGS_INTERWORK_PRESENT	0x01 /* beacon had IE, accessnet valid */
++#define WL_BSS_BCNFLAGS_INTERWORK_PRESENT_VALID 0x02 /* on indicates support for this API */
++
++/* bssinfo flag for nbss_cap */
++#define VHT_BI_SGI_80MHZ			0x00000100
++#define VHT_BI_80MHZ			    0x00000200
++#define VHT_BI_160MHZ			    0x00000400
++#define VHT_BI_8080MHZ			    0x00000800
++
++/* reference to wl_ioctl_t struct used by usermode driver */
++#define ioctl_subtype	set		/* subtype param */
++#define ioctl_pid	used		/* pid param */
++#define ioctl_status	needed		/* status param */
++
++
++/* Enumerate crypto algorithms */
++#define	CRYPTO_ALGO_OFF			0
++#define	CRYPTO_ALGO_WEP1		1
++#define	CRYPTO_ALGO_TKIP		2
++#define	CRYPTO_ALGO_WEP128		3
++#define CRYPTO_ALGO_AES_CCM		4
++#define CRYPTO_ALGO_AES_OCB_MSDU	5
++#define CRYPTO_ALGO_AES_OCB_MPDU	6
++#if !defined(BCMEXTCCX)
++#define CRYPTO_ALGO_NALG		7
++#else
++#define CRYPTO_ALGO_CKIP		7
++#define CRYPTO_ALGO_CKIP_MMH	8
++#define CRYPTO_ALGO_WEP_MMH		9
++#define CRYPTO_ALGO_NALG		10
++#endif 
++
++#define CRYPTO_ALGO_SMS4		11
++#define CRYPTO_ALGO_PMK			12	/* for 802.1x supp to set PMK before 4-way */
++#define CRYPTO_ALGO_BIP			13  /* 802.11w BIP (aes cmac) */
++
++#define CRYPTO_ALGO_AES_GCM     14  /* 128 bit GCM */
++#define CRYPTO_ALGO_AES_CCM256  15  /* 256 bit CCM */
++#define CRYPTO_ALGO_AES_GCM256  16  /* 256 bit GCM */
++#define CRYPTO_ALGO_BIP_CMAC256 17  /* 256 bit BIP CMAC */
++#define CRYPTO_ALGO_BIP_GMAC    18  /* 128 bit BIP GMAC */
++#define CRYPTO_ALGO_BIP_GMAC256 19  /* 256 bit BIP GMAC */
++
++#define CRYPTO_ALGO_NONE        CRYPTO_ALGO_OFF
++
++/* algo bit vector */
++#define KEY_ALGO_MASK(_algo)	(1 << _algo)
++
++#if defined(BCMEXTCCX)
++#define KEY_ALGO_MASK_CCX		(KEY_ALGO_MASK(CRYPTO_ALGO_CKIP) | \
++					KEY_ALGO_MASK(CRYPTO_ALGO_CKIP_MMH) | \
++					KEY_ALGO_MASK(CRYPTO_ALGO_WEP_MMH))
++#endif 
++
++#define KEY_ALGO_MASK_WEP		(KEY_ALGO_MASK(CRYPTO_ALGO_WEP1) | \
++					KEY_ALGO_MASK(CRYPTO_ALGO_WEP128) | \
++					KEY_ALGO_MASK(CRYPTO_ALGO_NALG))
++
++#define KEY_ALGO_MASK_AES		(KEY_ALGO_MASK(CRYPTO_ALGO_AES_CCM) | \
++					KEY_ALGO_MASK(CRYPTO_ALGO_AES_CCM256) | \
++					KEY_ALGO_MASK(CRYPTO_ALGO_AES_GCM) | \
++					KEY_ALGO_MASK(CRYPTO_ALGO_AES_GCM256))
++#define KEY_ALGO_MASK_TKIP		(KEY_ALGO_MASK(CRYPTO_ALGO_TKIP))
++#define KEY_ALGO_MASK_WAPI		(KEY_ALGO_MASK(CRYPTO_ALGO_SMS4))
++
++#define WSEC_GEN_MIC_ERROR	0x0001
++#define WSEC_GEN_REPLAY		0x0002
++#define WSEC_GEN_ICV_ERROR	0x0004
++#define WSEC_GEN_MFP_ACT_ERROR	0x0008
++#define WSEC_GEN_MFP_DISASSOC_ERROR	0x0010
++#define WSEC_GEN_MFP_DEAUTH_ERROR	0x0020
++
++#define WL_SOFT_KEY	(1 << 0)	/* Indicates this key is using soft encrypt */
++#define WL_PRIMARY_KEY	(1 << 1)	/* Indicates this key is the primary (ie tx) key */
++#if defined(BCMEXTCCX)
++#define WL_CKIP_KP	(1 << 4)	/* CMIC */
++#define WL_CKIP_MMH	(1 << 5)	/* CKIP */
++#else
++#define WL_KF_RES_4	(1 << 4)	/* Reserved for backward compat */
++#define WL_KF_RES_5	(1 << 5)	/* Reserved for backward compat */
++#endif 
++#define WL_IBSS_PEER_GROUP_KEY	(1 << 6)	/* Indicates a group key for a IBSS PEER */
++
++/* wireless security bitvec */
++#define WSEC_NONE		0x0
++#define WEP_ENABLED		0x0001
++#define TKIP_ENABLED		0x0002
++#define AES_ENABLED		0x0004
++#define WSEC_SWFLAG		0x0008
++#define SES_OW_ENABLED		0x0040	/* to go into transition mode without setting wep */
++#ifdef BCMWAPI_WPI
++#define SMS4_ENABLED		0x0100
++#endif /* BCMWAPI_WPI */
++
++#define WSEC_WEP_ENABLED(wsec)	((wsec) & WEP_ENABLED)
++#define WSEC_TKIP_ENABLED(wsec)	((wsec) & TKIP_ENABLED)
++#define WSEC_AES_ENABLED(wsec)	((wsec) & AES_ENABLED)
++
++#ifdef BCMCCX
++#define WSEC_CKIP_KP_ENABLED(wsec)	((wsec) & CKIP_KP_ENABLED)
++#define WSEC_CKIP_MIC_ENABLED(wsec)	((wsec) & CKIP_MIC_ENABLED)
++#define WSEC_CKIP_ENABLED(wsec)	((wsec) & (CKIP_KP_ENABLED|CKIP_MIC_ENABLED))
++
++#ifdef BCMWAPI_WPI
++#define WSEC_ENABLED(wsec) \
++	((wsec) & (WEP_ENABLED | TKIP_ENABLED | AES_ENABLED | CKIP_KP_ENABLED |	\
++	  CKIP_MIC_ENABLED | SMS4_ENABLED))
++#else /* BCMWAPI_WPI */
++#define WSEC_ENABLED(wsec) \
++		((wsec) & \
++		 (WEP_ENABLED | TKIP_ENABLED | AES_ENABLED | CKIP_KP_ENABLED | CKIP_MIC_ENABLED))
++#endif /* BCMWAPI_WPI */
++#else /* defined BCMCCX */
++#ifdef BCMWAPI_WPI
++#define WSEC_ENABLED(wsec)	((wsec) & (WEP_ENABLED | TKIP_ENABLED | AES_ENABLED | SMS4_ENABLED))
++#else /* BCMWAPI_WPI */
++#define WSEC_ENABLED(wsec)	((wsec) & (WEP_ENABLED | TKIP_ENABLED | AES_ENABLED))
++#endif /* BCMWAPI_WPI */
++#endif /* BCMCCX */
++
++#define WSEC_SES_OW_ENABLED(wsec)	((wsec) & SES_OW_ENABLED)
++#ifdef BCMWAPI_WAI
++#define WSEC_SMS4_ENABLED(wsec)	((wsec) & SMS4_ENABLED)
++#endif /* BCMWAPI_WAI */
++
++/* Following macros are not used any more. Just kept here to
++ * avoid build issue in BISON/CARIBOU branch
++ */
++#define MFP_CAPABLE		0x0200
++#define MFP_REQUIRED	0x0400
++#define MFP_SHA256		0x0800 /* a special configuration for STA for WIFI test tool */
++
++/* WPA authentication mode bitvec */
++#define WPA_AUTH_DISABLED	0x0000	/* Legacy (i.e., non-WPA) */
++#define WPA_AUTH_NONE		0x0001	/* none (IBSS) */
++#define WPA_AUTH_UNSPECIFIED	0x0002	/* over 802.1x */
++#define WPA_AUTH_PSK		0x0004	/* Pre-shared key */
++#if defined(BCMEXTCCX)
++#define WPA_AUTH_CCKM		0x0008	/* CCKM */
++#define WPA2_AUTH_CCKM		0x0010	/* CCKM2 */
++#endif	
++/* #define WPA_AUTH_8021X 0x0020 */	/* 802.1x, reserved */
++#define WPA2_AUTH_UNSPECIFIED	0x0040	/* over 802.1x */
++#define WPA2_AUTH_PSK		0x0080	/* Pre-shared key */
++#define BRCM_AUTH_PSK           0x0100  /* BRCM specific PSK */
++#define BRCM_AUTH_DPT		0x0200	/* DPT PSK without group keys */
++#if defined(BCMWAPI_WAI) || defined(BCMWAPI_WPI)
++#define WPA_AUTH_WAPI           0x0400
++#define WAPI_AUTH_NONE		WPA_AUTH_NONE	/* none (IBSS) */
++#define WAPI_AUTH_UNSPECIFIED	0x0400	/* over AS */
++#define WAPI_AUTH_PSK		0x0800	/* Pre-shared key */
++#endif /* BCMWAPI_WAI || BCMWAPI_WPI */
++#define WPA2_AUTH_1X_SHA256	0x1000  /* 1X with SHA256 key derivation */
++#define WPA2_AUTH_TPK		0x2000	/* TDLS Peer Key */
++#define WPA2_AUTH_FT		0x4000	/* Fast Transition. */
++#define WPA2_AUTH_PSK_SHA256	0x8000	/* PSK with SHA256 key derivation */
++#define WPA3_AUTH_SAE_PSK	0x40000 /* SAE with 4-way handshake */
++/* WPA2_AUTH_SHA256 not used anymore. Just kept here to avoid build issue in DINGO */
++#define WPA2_AUTH_SHA256	0x8000
++#define WPA_AUTH_PFN_ANY	0xffffffff	/* for PFN, match only ssid */
++
++/* pmkid */
++#define	MAXPMKID		16
++
++/* SROM12 changes */
++#define	WLC_IOCTL_MAXLEN		8192	/* max length ioctl buffer required */
++
++
++#define	WLC_IOCTL_SMLEN			256	/* "small" length ioctl buffer required */
++#define WLC_IOCTL_MEDLEN		1536    /* "med" length ioctl buffer required */
++#if defined(LCNCONF) || defined(LCN40CONF) || defined(LCN20CONF)
++#define WLC_SAMPLECOLLECT_MAXLEN	8192	/* Max Sample Collect buffer */
++#else
++#define WLC_SAMPLECOLLECT_MAXLEN	10240	/* Max Sample Collect buffer for two cores */
++#endif
++#define WLC_SAMPLECOLLECT_MAXLEN_LCN40  8192
++
++/* common ioctl definitions */
++#define WLC_GET_MAGIC				0
++#define WLC_GET_VERSION				1
++#define WLC_UP					2
++#define WLC_DOWN				3
++#define WLC_GET_LOOP				4
++#define WLC_SET_LOOP				5
++#define WLC_DUMP				6
++#define WLC_GET_MSGLEVEL			7
++#define WLC_SET_MSGLEVEL			8
++#define WLC_GET_PROMISC				9
++#define WLC_SET_PROMISC				10
++/* #define WLC_OVERLAY_IOCTL			11 */ /* not supported */
++#define WLC_GET_RATE				12
++#define WLC_GET_MAX_RATE			13
++#define WLC_GET_INSTANCE			14
++/* #define WLC_GET_FRAG				15 */ /* no longer supported */
++/* #define WLC_SET_FRAG				16 */ /* no longer supported */
++/* #define WLC_GET_RTS				17 */ /* no longer supported */
++/* #define WLC_SET_RTS				18 */ /* no longer supported */
++#define WLC_GET_INFRA				19
++#define WLC_SET_INFRA				20
++#define WLC_GET_AUTH				21
++#define WLC_SET_AUTH				22
++#define WLC_GET_BSSID				23
++#define WLC_SET_BSSID				24
++#define WLC_GET_SSID				25
++#define WLC_SET_SSID				26
++#define WLC_RESTART				27
++#define WLC_TERMINATED				28
++/* #define WLC_DUMP_SCB				28 */ /* no longer supported */
++#define WLC_GET_CHANNEL				29
++#define WLC_SET_CHANNEL				30
++#define WLC_GET_SRL				31
++#define WLC_SET_SRL				32
++#define WLC_GET_LRL				33
++#define WLC_SET_LRL				34
++#define WLC_GET_PLCPHDR				35
++#define WLC_SET_PLCPHDR				36
++#define WLC_GET_RADIO				37
++#define WLC_SET_RADIO				38
++#define WLC_GET_PHYTYPE				39
++#define WLC_DUMP_RATE				40
++#define WLC_SET_RATE_PARAMS			41
++#define WLC_GET_FIXRATE				42
++#define WLC_SET_FIXRATE				43
++/* #define WLC_GET_WEP				42 */ /* no longer supported */
++/* #define WLC_SET_WEP				43 */ /* no longer supported */
++#define WLC_GET_KEY				44
++#define WLC_SET_KEY				45
++#define WLC_GET_REGULATORY			46
++#define WLC_SET_REGULATORY			47
++#define WLC_GET_PASSIVE_SCAN			48
++#define WLC_SET_PASSIVE_SCAN			49
++#define WLC_SCAN				50
++#define WLC_SCAN_RESULTS			51
++#define WLC_DISASSOC				52
++#define WLC_REASSOC				53
++#define WLC_GET_ROAM_TRIGGER			54
++#define WLC_SET_ROAM_TRIGGER			55
++#define WLC_GET_ROAM_DELTA			56
++#define WLC_SET_ROAM_DELTA			57
++#define WLC_GET_ROAM_SCAN_PERIOD		58
++#define WLC_SET_ROAM_SCAN_PERIOD		59
++#define WLC_EVM					60	/* diag */
++#define WLC_GET_TXANT				61
++#define WLC_SET_TXANT				62
++#define WLC_GET_ANTDIV				63
++#define WLC_SET_ANTDIV				64
++/* #define WLC_GET_TXPWR			65 */ /* no longer supported */
++/* #define WLC_SET_TXPWR			66 */ /* no longer supported */
++#define WLC_GET_CLOSED				67
++#define WLC_SET_CLOSED				68
++#define WLC_GET_MACLIST				69
++#define WLC_SET_MACLIST				70
++#define WLC_GET_RATESET				71
++#define WLC_SET_RATESET				72
++/* #define WLC_GET_LOCALE			73 */ /* no longer supported */
++#define WLC_LONGTRAIN				74
++#define WLC_GET_BCNPRD				75
++#define WLC_SET_BCNPRD				76
++#define WLC_GET_DTIMPRD				77
++#define WLC_SET_DTIMPRD				78
++#define WLC_GET_SROM				79
++#define WLC_SET_SROM				80
++#define WLC_GET_WEP_RESTRICT			81
++#define WLC_SET_WEP_RESTRICT			82
++#define WLC_GET_COUNTRY				83
++#define WLC_SET_COUNTRY				84
++#define WLC_GET_PM				85
++#define WLC_SET_PM				86
++#define WLC_GET_WAKE				87
++#define WLC_SET_WAKE				88
++/* #define WLC_GET_D11CNTS			89 */ /* -> "counters" iovar */
++#define WLC_GET_FORCELINK			90	/* ndis only */
++#define WLC_SET_FORCELINK			91	/* ndis only */
++#define WLC_FREQ_ACCURACY			92	/* diag */
++#define WLC_CARRIER_SUPPRESS			93	/* diag */
++#define WLC_GET_PHYREG				94
++#define WLC_SET_PHYREG				95
++#define WLC_GET_RADIOREG			96
++#define WLC_SET_RADIOREG			97
++#define WLC_GET_REVINFO				98
++#define WLC_GET_UCANTDIV			99
++#define WLC_SET_UCANTDIV			100
++#define WLC_R_REG				101
++#define WLC_W_REG				102
++/* #define WLC_DIAG_LOOPBACK			103	old tray diag */
++/* #define WLC_RESET_D11CNTS			104 */ /* -> "reset_d11cnts" iovar */
++#define WLC_GET_MACMODE				105
++#define WLC_SET_MACMODE				106
++#define WLC_GET_MONITOR				107
++#define WLC_SET_MONITOR				108
++#define WLC_GET_GMODE				109
++#define WLC_SET_GMODE				110
++#define WLC_GET_LEGACY_ERP			111
++#define WLC_SET_LEGACY_ERP			112
++#define WLC_GET_RX_ANT				113
++#define WLC_GET_CURR_RATESET			114	/* current rateset */
++#define WLC_GET_SCANSUPPRESS			115
++#define WLC_SET_SCANSUPPRESS			116
++#define WLC_GET_AP				117
++#define WLC_SET_AP				118
++#define WLC_GET_EAP_RESTRICT			119
++#define WLC_SET_EAP_RESTRICT			120
++#define WLC_SCB_AUTHORIZE			121
++#define WLC_SCB_DEAUTHORIZE			122
++#define WLC_GET_WDSLIST				123
++#define WLC_SET_WDSLIST				124
++#define WLC_GET_ATIM				125
++#define WLC_SET_ATIM				126
++#define WLC_GET_RSSI				127
++#define WLC_GET_PHYANTDIV			128
++#define WLC_SET_PHYANTDIV			129
++#define WLC_AP_RX_ONLY				130
++#define WLC_GET_TX_PATH_PWR			131
++#define WLC_SET_TX_PATH_PWR			132
++#define WLC_GET_WSEC				133
++#define WLC_SET_WSEC				134
++#define WLC_GET_PHY_NOISE			135
++#define WLC_GET_BSS_INFO			136
++#define WLC_GET_PKTCNTS				137
++#define WLC_GET_LAZYWDS				138
++#define WLC_SET_LAZYWDS				139
++#define WLC_GET_BANDLIST			140
++
++#define WLC_GET_BAND				141
++#define WLC_SET_BAND				142
++#define WLC_SCB_DEAUTHENTICATE			143
++#define WLC_GET_SHORTSLOT			144
++#define WLC_GET_SHORTSLOT_OVERRIDE		145
++#define WLC_SET_SHORTSLOT_OVERRIDE		146
++#define WLC_GET_SHORTSLOT_RESTRICT		147
++#define WLC_SET_SHORTSLOT_RESTRICT		148
++#define WLC_GET_GMODE_PROTECTION		149
++#define WLC_GET_GMODE_PROTECTION_OVERRIDE	150
++#define WLC_SET_GMODE_PROTECTION_OVERRIDE	151
++#define WLC_UPGRADE				152
++/* #define WLC_GET_MRATE			153 */ /* no longer supported */
++/* #define WLC_SET_MRATE			154 */ /* no longer supported */
++#define WLC_GET_IGNORE_BCNS			155
++#define WLC_SET_IGNORE_BCNS			156
++#define WLC_GET_SCB_TIMEOUT			157
++#define WLC_SET_SCB_TIMEOUT			158
++#define WLC_GET_ASSOCLIST			159
++#define WLC_GET_CLK				160
++#define WLC_SET_CLK				161
++#define WLC_GET_UP				162
++#define WLC_OUT					163
++#define WLC_GET_WPA_AUTH			164
++#define WLC_SET_WPA_AUTH			165
++#define WLC_GET_UCFLAGS				166
++#define WLC_SET_UCFLAGS				167
++#define WLC_GET_PWRIDX				168
++#define WLC_SET_PWRIDX				169
++#define WLC_GET_TSSI				170
++#define WLC_GET_SUP_RATESET_OVERRIDE		171
++#define WLC_SET_SUP_RATESET_OVERRIDE		172
++/* #define WLC_SET_FAST_TIMER			173 */ /* no longer supported */
++/* #define WLC_GET_FAST_TIMER			174 */ /* no longer supported */
++/* #define WLC_SET_SLOW_TIMER			175 */ /* no longer supported */
++/* #define WLC_GET_SLOW_TIMER			176 */ /* no longer supported */
++/* #define WLC_DUMP_PHYREGS			177 */ /* no longer supported */
++#define WLC_GET_PROTECTION_CONTROL		178
++#define WLC_SET_PROTECTION_CONTROL		179
++#define WLC_GET_PHYLIST				180
++#define WLC_ENCRYPT_STRENGTH			181	/* ndis only */
++#define WLC_DECRYPT_STATUS			182	/* ndis only */
++#define WLC_GET_KEY_SEQ				183
++#define WLC_GET_SCAN_CHANNEL_TIME		184
++#define WLC_SET_SCAN_CHANNEL_TIME		185
++#define WLC_GET_SCAN_UNASSOC_TIME		186
++#define WLC_SET_SCAN_UNASSOC_TIME		187
++#define WLC_GET_SCAN_HOME_TIME			188
++#define WLC_SET_SCAN_HOME_TIME			189
++#define WLC_GET_SCAN_NPROBES			190
++#define WLC_SET_SCAN_NPROBES			191
++#define WLC_GET_PRB_RESP_TIMEOUT		192
++#define WLC_SET_PRB_RESP_TIMEOUT		193
++#define WLC_GET_ATTEN				194
++#define WLC_SET_ATTEN				195
++#define WLC_GET_SHMEM				196	/* diag */
++#define WLC_SET_SHMEM				197	/* diag */
++/* #define WLC_GET_GMODE_PROTECTION_CTS		198 */ /* no longer supported */
++/* #define WLC_SET_GMODE_PROTECTION_CTS		199 */ /* no longer supported */
++#define WLC_SET_WSEC_TEST			200
++#define WLC_SCB_DEAUTHENTICATE_FOR_REASON	201
++#define WLC_TKIP_COUNTERMEASURES		202
++#define WLC_GET_PIOMODE				203
++#define WLC_SET_PIOMODE				204
++#define WLC_SET_ASSOC_PREFER			205
++#define WLC_GET_ASSOC_PREFER			206
++#define WLC_SET_ROAM_PREFER			207
++#define WLC_GET_ROAM_PREFER			208
++#define WLC_SET_LED				209
++#define WLC_GET_LED				210
++#define WLC_GET_INTERFERENCE_MODE		211
++#define WLC_SET_INTERFERENCE_MODE		212
++#define WLC_GET_CHANNEL_QA			213
++#define WLC_START_CHANNEL_QA			214
++#define WLC_GET_CHANNEL_SEL			215
++#define WLC_START_CHANNEL_SEL			216
++#define WLC_GET_VALID_CHANNELS			217
++#define WLC_GET_FAKEFRAG			218
++#define WLC_SET_FAKEFRAG			219
++#define WLC_GET_PWROUT_PERCENTAGE		220
++#define WLC_SET_PWROUT_PERCENTAGE		221
++#define WLC_SET_BAD_FRAME_PREEMPT		222
++#define WLC_GET_BAD_FRAME_PREEMPT		223
++#define WLC_SET_LEAP_LIST			224
++#define WLC_GET_LEAP_LIST			225
++#define WLC_GET_CWMIN				226
++#define WLC_SET_CWMIN				227
++#define WLC_GET_CWMAX				228
++#define WLC_SET_CWMAX				229
++#define WLC_GET_WET				230
++#define WLC_SET_WET				231
++#define WLC_GET_PUB				232
++/* #define WLC_SET_GLACIAL_TIMER		233 */ /* no longer supported */
++/* #define WLC_GET_GLACIAL_TIMER		234 */ /* no longer supported */
++#define WLC_GET_KEY_PRIMARY			235
++#define WLC_SET_KEY_PRIMARY			236
++
++
++/* #define WLC_DUMP_RADIOREGS			237 */ /* no longer supported */
++#define WLC_GET_ACI_ARGS			238
++#define WLC_SET_ACI_ARGS			239
++#define WLC_UNSET_CALLBACK			240
++#define WLC_SET_CALLBACK			241
++#define WLC_GET_RADAR				242
++#define WLC_SET_RADAR				243
++#define WLC_SET_SPECT_MANAGMENT			244
++#define WLC_GET_SPECT_MANAGMENT			245
++#define WLC_WDS_GET_REMOTE_HWADDR		246	/* handled in wl_linux.c/wl_vx.c */
++#define WLC_WDS_GET_WPA_SUP			247
++#define WLC_SET_CS_SCAN_TIMER			248
++#define WLC_GET_CS_SCAN_TIMER			249
++#define WLC_MEASURE_REQUEST			250
++#define WLC_INIT				251
++#define WLC_SEND_QUIET				252
++#define WLC_KEEPALIVE			253
++#define WLC_SEND_PWR_CONSTRAINT			254
++#define WLC_UPGRADE_STATUS			255
++#define WLC_CURRENT_PWR				256
++#define WLC_GET_SCAN_PASSIVE_TIME		257
++#define WLC_SET_SCAN_PASSIVE_TIME		258
++#define WLC_LEGACY_LINK_BEHAVIOR		259
++#define WLC_GET_CHANNELS_IN_COUNTRY		260
++#define WLC_GET_COUNTRY_LIST			261
++#define WLC_GET_VAR				262	/* get value of named variable */
++#define WLC_SET_VAR				263	/* set named variable to value */
++#define WLC_NVRAM_GET				264	/* deprecated */
++#define WLC_NVRAM_SET				265
++#define WLC_NVRAM_DUMP				266
++#define WLC_REBOOT				267
++#define WLC_SET_WSEC_PMK			268
++#define WLC_GET_AUTH_MODE			269
++#define WLC_SET_AUTH_MODE			270
++#define WLC_GET_WAKEENTRY			271
++#define WLC_SET_WAKEENTRY			272
++#define WLC_NDCONFIG_ITEM			273	/* currently handled in wl_oid.c */
++#define WLC_NVOTPW				274
++#define WLC_OTPW				275
++#define WLC_IOV_BLOCK_GET			276
++#define WLC_IOV_MODULES_GET			277
++#define WLC_SOFT_RESET				278
++#define WLC_GET_ALLOW_MODE			279
++#define WLC_SET_ALLOW_MODE			280
++#define WLC_GET_DESIRED_BSSID			281
++#define WLC_SET_DESIRED_BSSID			282
++#define	WLC_DISASSOC_MYAP			283
++#define WLC_GET_NBANDS				284	/* for Dongle EXT_STA support */
++#define WLC_GET_BANDSTATES			285	/* for Dongle EXT_STA support */
++#define WLC_GET_WLC_BSS_INFO			286	/* for Dongle EXT_STA support */
++#define WLC_GET_ASSOC_INFO			287	/* for Dongle EXT_STA support */
++#define WLC_GET_OID_PHY				288	/* for Dongle EXT_STA support */
++#define WLC_SET_OID_PHY				289	/* for Dongle EXT_STA support */
++#define WLC_SET_ASSOC_TIME			290	/* for Dongle EXT_STA support */
++#define WLC_GET_DESIRED_SSID			291	/* for Dongle EXT_STA support */
++#define WLC_GET_CHANSPEC			292	/* for Dongle EXT_STA support */
++#define WLC_GET_ASSOC_STATE			293	/* for Dongle EXT_STA support */
++#define WLC_SET_PHY_STATE			294	/* for Dongle EXT_STA support */
++#define WLC_GET_SCAN_PENDING			295	/* for Dongle EXT_STA support */
++#define WLC_GET_SCANREQ_PENDING			296	/* for Dongle EXT_STA support */
++#define WLC_GET_PREV_ROAM_REASON		297	/* for Dongle EXT_STA support */
++#define WLC_SET_PREV_ROAM_REASON		298	/* for Dongle EXT_STA support */
++#define WLC_GET_BANDSTATES_PI			299	/* for Dongle EXT_STA support */
++#define WLC_GET_PHY_STATE			300	/* for Dongle EXT_STA support */
++#define WLC_GET_BSS_WPA_RSN			301	/* for Dongle EXT_STA support */
++#define WLC_GET_BSS_WPA2_RSN			302	/* for Dongle EXT_STA support */
++#define WLC_GET_BSS_BCN_TS			303	/* for Dongle EXT_STA support */
++#define WLC_GET_INT_DISASSOC			304	/* for Dongle EXT_STA support */
++#define WLC_SET_NUM_PEERS			305     /* for Dongle EXT_STA support */
++#define WLC_GET_NUM_BSS				306	/* for Dongle EXT_STA support */
++#define WLC_PHY_SAMPLE_COLLECT			307	/* phy sample collect mode */
++/* #define WLC_UM_PRIV				308 */	/* Deprecated: usermode driver */
++#define WLC_GET_CMD				309
++/* #define WLC_LAST				310 */	/* Never used - can be reused */
++#define WLC_SET_INTERFERENCE_OVERRIDE_MODE	311	/* set inter mode override */
++#define WLC_GET_INTERFERENCE_OVERRIDE_MODE	312	/* get inter mode override */
++/* #define WLC_GET_WAI_RESTRICT	313 */
++/* #define WLC_SET_WAI_RESTRICT	314 */
++/* #define WLC_SET_WAI_REKEY	315 */
++#define WLC_SET_NAT_CONFIG			316	/* for configuring NAT filter driver */
++#define WLC_GET_NAT_STATE			317
++#define WLC_GET_TXBF_RATESET			318
++#define WLC_SET_TXBF_RATESET			319
++#define WLC_SCAN_CQ				320
++#define WLC_GET_RSSI_QDB			321 /* qdB portion of the RSSI */
++#define WLC_DUMP_RATESET			322
++#define WLC_ECHO				323
++#define WLC_LAST				324
++#define WLC_SPEC_FLAG			0x80000000 /* For some special IOCTL */
++#ifndef EPICTRL_COOKIE
++#define EPICTRL_COOKIE		0xABADCEDE
++#endif
++
++/* vx wlc ioctl's offset */
++#define CMN_IOCTL_OFF 0x180
++
++/*
++ * custom OID support
++ *
++ * 0xFF - implementation specific OID
++ * 0xE4 - first byte of Broadcom PCI vendor ID
++ * 0x14 - second byte of Broadcom PCI vendor ID
++ * 0xXX - the custom OID number
++ */
++
++/* begin 0x1f values beyond the start of the ET driver range. */
++#define WL_OID_BASE		0xFFE41420
++
++/* NDIS overrides */
++#define OID_WL_GETINSTANCE	(WL_OID_BASE + WLC_GET_INSTANCE)
++#define OID_WL_GET_FORCELINK	(WL_OID_BASE + WLC_GET_FORCELINK)
++#define OID_WL_SET_FORCELINK	(WL_OID_BASE + WLC_SET_FORCELINK)
++#define	OID_WL_ENCRYPT_STRENGTH	(WL_OID_BASE + WLC_ENCRYPT_STRENGTH)
++#define OID_WL_DECRYPT_STATUS	(WL_OID_BASE + WLC_DECRYPT_STATUS)
++#define OID_LEGACY_LINK_BEHAVIOR (WL_OID_BASE + WLC_LEGACY_LINK_BEHAVIOR)
++#define OID_WL_NDCONFIG_ITEM	(WL_OID_BASE + WLC_NDCONFIG_ITEM)
++
++/* EXT_STA Dongle suuport */
++#define OID_STA_CHANSPEC	(WL_OID_BASE + WLC_GET_CHANSPEC)
++#define OID_STA_NBANDS		(WL_OID_BASE + WLC_GET_NBANDS)
++#define OID_STA_GET_PHY		(WL_OID_BASE + WLC_GET_OID_PHY)
++#define OID_STA_SET_PHY		(WL_OID_BASE + WLC_SET_OID_PHY)
++#define OID_STA_ASSOC_TIME	(WL_OID_BASE + WLC_SET_ASSOC_TIME)
++#define OID_STA_DESIRED_SSID	(WL_OID_BASE + WLC_GET_DESIRED_SSID)
++#define OID_STA_SET_PHY_STATE	(WL_OID_BASE + WLC_SET_PHY_STATE)
++#define OID_STA_SCAN_PENDING	(WL_OID_BASE + WLC_GET_SCAN_PENDING)
++#define OID_STA_SCANREQ_PENDING (WL_OID_BASE + WLC_GET_SCANREQ_PENDING)
++#define OID_STA_GET_ROAM_REASON (WL_OID_BASE + WLC_GET_PREV_ROAM_REASON)
++#define OID_STA_SET_ROAM_REASON (WL_OID_BASE + WLC_SET_PREV_ROAM_REASON)
++#define OID_STA_GET_PHY_STATE	(WL_OID_BASE + WLC_GET_PHY_STATE)
++#define OID_STA_INT_DISASSOC	(WL_OID_BASE + WLC_GET_INT_DISASSOC)
++#define OID_STA_SET_NUM_PEERS	(WL_OID_BASE + WLC_SET_NUM_PEERS)
++#define OID_STA_GET_NUM_BSS	(WL_OID_BASE + WLC_GET_NUM_BSS)
++
++/* NAT filter driver support */
++#define OID_NAT_SET_CONFIG	(WL_OID_BASE + WLC_SET_NAT_CONFIG)
++#define OID_NAT_GET_STATE	(WL_OID_BASE + WLC_GET_NAT_STATE)
++
++#define WL_DECRYPT_STATUS_SUCCESS	1
++#define WL_DECRYPT_STATUS_FAILURE	2
++#define WL_DECRYPT_STATUS_UNKNOWN	3
++
++/* allows user-mode app to poll the status of USB image upgrade */
++#define WLC_UPGRADE_SUCCESS			0
++#define WLC_UPGRADE_PENDING			1
++
++/* WLC_GET_AUTH, WLC_SET_AUTH values */
++#define WL_AUTH_OPEN_SYSTEM		0	/* d11 open authentication */
++#define WL_AUTH_SHARED_KEY		1	/* d11 shared authentication */
++#define WL_AUTH_OPEN_SHARED		2	/* try open, then shared if open failed w/rc 13 */
++
++/* a large TX Power as an init value to factor out of MIN() calculations,
++ * keep low enough to fit in an int8, units are .25 dBm
++ */
++#define WLC_TXPWR_MAX		(127)	/* ~32 dBm = 1,500 mW */
++
++/* "diag" iovar argument and error code */
++#define WL_DIAG_INTERRUPT			1	/* d11 loopback interrupt test */
++#define WL_DIAG_LOOPBACK			2	/* d11 loopback data test */
++#define WL_DIAG_MEMORY				3	/* d11 memory test */
++#define WL_DIAG_LED				4	/* LED test */
++#define WL_DIAG_REG				5	/* d11/phy register test */
++#define WL_DIAG_SROM				6	/* srom read/crc test */
++#define WL_DIAG_DMA				7	/* DMA test */
++#define WL_DIAG_LOOPBACK_EXT			8	/* enhenced d11 loopback data test */
++
++#define WL_DIAGERR_SUCCESS			0
++#define WL_DIAGERR_FAIL_TO_RUN			1	/* unable to run requested diag */
++#define WL_DIAGERR_NOT_SUPPORTED		2	/* diag requested is not supported */
++#define WL_DIAGERR_INTERRUPT_FAIL		3	/* loopback interrupt test failed */
++#define WL_DIAGERR_LOOPBACK_FAIL		4	/* loopback data test failed */
++#define WL_DIAGERR_SROM_FAIL			5	/* srom read failed */
++#define WL_DIAGERR_SROM_BADCRC			6	/* srom crc failed */
++#define WL_DIAGERR_REG_FAIL			7	/* d11/phy register test failed */
++#define WL_DIAGERR_MEMORY_FAIL			8	/* d11 memory test failed */
++#define WL_DIAGERR_NOMEM			9	/* diag test failed due to no memory */
++#define WL_DIAGERR_DMA_FAIL			10	/* DMA test failed */
++
++#define WL_DIAGERR_MEMORY_TIMEOUT		11	/* d11 memory test didn't finish in time */
++#define WL_DIAGERR_MEMORY_BADPATTERN		12	/* d11 memory test result in bad pattern */
++
++/* band types */
++#define	WLC_BAND_AUTO		0	/* auto-select */
++#define	WLC_BAND_5G		1	/* 5 Ghz */
++#define	WLC_BAND_2G		2	/* 2.4 Ghz */
++#define	WLC_BAND_ALL		3	/* all bands */
++#define WLC_BAND_INVALID	-1	/* Invalid band */
++
++/* band range returned by band_range iovar */
++#define WL_CHAN_FREQ_RANGE_2G      0
++#define WL_CHAN_FREQ_RANGE_5GL     1
++#define WL_CHAN_FREQ_RANGE_5GM     2
++#define WL_CHAN_FREQ_RANGE_5GH     3
++
++#define WL_CHAN_FREQ_RANGE_5GLL_5BAND    4
++#define WL_CHAN_FREQ_RANGE_5GLH_5BAND    5
++#define WL_CHAN_FREQ_RANGE_5GML_5BAND    6
++#define WL_CHAN_FREQ_RANGE_5GMH_5BAND    7
++#define WL_CHAN_FREQ_RANGE_5GH_5BAND     8
++
++#define WL_CHAN_FREQ_RANGE_5G_BAND0     1
++#define WL_CHAN_FREQ_RANGE_5G_BAND1     2
++#define WL_CHAN_FREQ_RANGE_5G_BAND2     3
++#define WL_CHAN_FREQ_RANGE_5G_BAND3     4
++#define WL_CHAN_FREQ_RANGE_5G_4BAND     5
++
++/* SROM12 */
++#define WL_CHAN_FREQ_RANGE_5G_BAND4 5
++#define WL_CHAN_FREQ_RANGE_2G_40 6
++#define WL_CHAN_FREQ_RANGE_5G_BAND0_40 7
++#define WL_CHAN_FREQ_RANGE_5G_BAND1_40 8
++#define WL_CHAN_FREQ_RANGE_5G_BAND2_40 9
++#define WL_CHAN_FREQ_RANGE_5G_BAND3_40 10
++#define WL_CHAN_FREQ_RANGE_5G_BAND4_40 11
++#define WL_CHAN_FREQ_RANGE_5G_BAND0_80 12
++#define WL_CHAN_FREQ_RANGE_5G_BAND1_80 13
++#define WL_CHAN_FREQ_RANGE_5G_BAND2_80 14
++#define WL_CHAN_FREQ_RANGE_5G_BAND3_80 15
++#define WL_CHAN_FREQ_RANGE_5G_BAND4_80 16
++
++#define WL_CHAN_FREQ_RANGE_5G_5BAND	18
++#define WL_CHAN_FREQ_RANGE_5G_5BAND_40	19
++#define WL_CHAN_FREQ_RANGE_5G_5BAND_80	20
++
++#define WLC_MACMODE_DISABLED	0	/* MAC list disabled */
++#define WLC_MACMODE_DENY	1	/* Deny specified (i.e. allow unspecified) */
++#define WLC_MACMODE_ALLOW	2	/* Allow specified (i.e. deny unspecified) */
++
++/*
++ * 54g modes (basic bits may still be overridden)
++ *
++ * GMODE_LEGACY_B			Rateset: 1b, 2b, 5.5, 11
++ *					Preamble: Long
++ *					Shortslot: Off
++ * GMODE_AUTO				Rateset: 1b, 2b, 5.5b, 11b, 18, 24, 36, 54
++ *					Extended Rateset: 6, 9, 12, 48
++ *					Preamble: Long
++ *					Shortslot: Auto
++ * GMODE_ONLY				Rateset: 1b, 2b, 5.5b, 11b, 18, 24b, 36, 54
++ *					Extended Rateset: 6b, 9, 12b, 48
++ *					Preamble: Short required
++ *					Shortslot: Auto
++ * GMODE_B_DEFERRED			Rateset: 1b, 2b, 5.5b, 11b, 18, 24, 36, 54
++ *					Extended Rateset: 6, 9, 12, 48
++ *					Preamble: Long
++ *					Shortslot: On
++ * GMODE_PERFORMANCE			Rateset: 1b, 2b, 5.5b, 6b, 9, 11b, 12b, 18, 24b, 36, 48, 54
++ *					Preamble: Short required
++ *					Shortslot: On and required
++ * GMODE_LRS				Rateset: 1b, 2b, 5.5b, 11b
++ *					Extended Rateset: 6, 9, 12, 18, 24, 36, 48, 54
++ *					Preamble: Long
++ *					Shortslot: Auto
++ */
++#define GMODE_LEGACY_B		0
++#define GMODE_AUTO		1
++#define GMODE_ONLY		2
++#define GMODE_B_DEFERRED	3
++#define GMODE_PERFORMANCE	4
++#define GMODE_LRS		5
++#define GMODE_MAX		6
++
++/* values for PLCPHdr_override */
++#define WLC_PLCP_AUTO	-1
++#define WLC_PLCP_SHORT	0
++#define WLC_PLCP_LONG	1
++
++/* values for g_protection_override and n_protection_override */
++#define WLC_PROTECTION_AUTO		-1
++#define WLC_PROTECTION_OFF		0
++#define WLC_PROTECTION_ON		1
++#define WLC_PROTECTION_MMHDR_ONLY	2
++#define WLC_PROTECTION_CTS_ONLY		3
++
++/* values for g_protection_control and n_protection_control */
++#define WLC_PROTECTION_CTL_OFF		0
++#define WLC_PROTECTION_CTL_LOCAL	1
++#define WLC_PROTECTION_CTL_OVERLAP	2
++
++/* values for n_protection */
++#define WLC_N_PROTECTION_OFF		0
++#define WLC_N_PROTECTION_OPTIONAL	1
++#define WLC_N_PROTECTION_20IN40		2
++#define WLC_N_PROTECTION_MIXEDMODE	3
++
++/* values for n_preamble_type */
++#define WLC_N_PREAMBLE_MIXEDMODE	0
++#define WLC_N_PREAMBLE_GF		1
++#define WLC_N_PREAMBLE_GF_BRCM          2
++
++/* values for band specific 40MHz capabilities (deprecated) */
++#define WLC_N_BW_20ALL			0
++#define WLC_N_BW_40ALL			1
++#define WLC_N_BW_20IN2G_40IN5G		2
++
++#define WLC_BW_20MHZ_BIT		(1<<0)
++#define WLC_BW_40MHZ_BIT		(1<<1)
++#define WLC_BW_80MHZ_BIT		(1<<2)
++#define WLC_BW_160MHZ_BIT		(1<<3)
++#define WLC_BW_10MHZ_BIT		(1<<4)
++#define WLC_BW_5MHZ_BIT			(1<<5)
++#define WLC_BW_2P5MHZ_BIT		(1<<6)
++/* Bandwidth capabilities */
++#define WLC_BW_CAP_20MHZ		(WLC_BW_20MHZ_BIT)
++#define WLC_BW_CAP_40MHZ		(WLC_BW_40MHZ_BIT|WLC_BW_20MHZ_BIT)
++#define WLC_BW_CAP_80MHZ		(WLC_BW_80MHZ_BIT|WLC_BW_40MHZ_BIT|WLC_BW_20MHZ_BIT)
++#define WLC_BW_CAP_160MHZ		(WLC_BW_160MHZ_BIT|WLC_BW_80MHZ_BIT| \
++	WLC_BW_40MHZ_BIT|WLC_BW_20MHZ_BIT)
++#define WLC_BW_CAP_2P5MHZ		(WLC_BW_2P5MHZ_BIT)
++#define WLC_BW_CAP_5MHZ			(WLC_BW_5MHZ_BIT)
++#define WLC_BW_CAP_10MHZ		(WLC_BW_10MHZ_BIT)
++#define WLC_BW_CAP_UNRESTRICTED		0xFF
++
++#define WL_BW_CAP_20MHZ(bw_cap)	(((bw_cap) & WLC_BW_20MHZ_BIT) ? TRUE : FALSE)
++#define WL_BW_CAP_40MHZ(bw_cap)	(((bw_cap) & WLC_BW_40MHZ_BIT) ? TRUE : FALSE)
++#define WL_BW_CAP_80MHZ(bw_cap)	(((bw_cap) & WLC_BW_80MHZ_BIT) ? TRUE : FALSE)
++#define WL_BW_CAP_160MHZ(bw_cap)(((bw_cap) & WLC_BW_160MHZ_BIT) ? TRUE : FALSE)
++#define WL_BW_CAP_2P5MHZ(bw_cap)(((bw_cap) & WLC_BW_2P5MHZ_BIT) ? TRUE : FALSE)
++#define WL_BW_CAP_5MHZ(bw_cap)	(((bw_cap) & WLC_BW_5MHZ_BIT) ? TRUE : FALSE)
++#define WL_BW_CAP_10MHZ(bw_cap)	(((bw_cap) & WLC_BW_10MHZ_BIT) ? TRUE : FALSE)
++/* values to force tx/rx chain */
++#define WLC_N_TXRX_CHAIN0		0
++#define WLC_N_TXRX_CHAIN1		1
++
++/* bitflags for SGI support (sgi_rx iovar) */
++#define WLC_N_SGI_20			0x01
++#define WLC_N_SGI_40			0x02
++#define WLC_VHT_SGI_80			0x04
++#define WLC_VHT_SGI_160			0x08
++
++/* when sgi_tx==WLC_SGI_ALL, bypass rate selection, enable sgi for all mcs */
++#define WLC_SGI_ALL				0x02
++
++#define LISTEN_INTERVAL			10
++/* interference mitigation options */
++#define	INTERFERE_OVRRIDE_OFF	-1	/* interference override off */
++#define	INTERFERE_NONE	0	/* off */
++#define	NON_WLAN	1	/* foreign/non 802.11 interference, no auto detect */
++#define	WLAN_MANUAL	2	/* ACI: no auto detection */
++#define	WLAN_AUTO	3	/* ACI: auto detect */
++#define	WLAN_AUTO_W_NOISE	4	/* ACI: auto - detect and non 802.11 interference */
++#define AUTO_ACTIVE	(1 << 7) /* Auto is currently active */
++
++/* interfernece mode bit-masks (ACPHY) */
++#define ACPHY_ACI_GLITCHBASED_DESENSE 1   /* bit 0 */
++#define ACPHY_ACI_HWACI_PKTGAINLMT 2      /* bit 1 */
++#define ACPHY_ACI_W2NB_PKTGAINLMT 4       /* bit 2 */
++#define ACPHY_ACI_PREEMPTION 8            /* bit 3 */
++#define ACPHY_HWACI_MITIGATION 16         /* bit 4 */
++#define ACPHY_LPD_PREEMPTION 32           /* bit 5 */
++#define ACPHY_HWOBSS_MITIGATION 64        /* bit 6 */
++#define ACPHY_ACI_MAX_MODE 127
++
++/* AP environment */
++#define AP_ENV_DETECT_NOT_USED		0 /* We aren't using AP environment detection */
++#define AP_ENV_DENSE			1 /* "Corporate" or other AP dense environment */
++#define AP_ENV_SPARSE			2 /* "Home" or other sparse environment */
++#define AP_ENV_INDETERMINATE		3 /* AP environment hasn't been identified */
++
++#define TRIGGER_NOW				0
++#define TRIGGER_CRS				0x01
++#define TRIGGER_CRSDEASSERT			0x02
++#define TRIGGER_GOODFCS				0x04
++#define TRIGGER_BADFCS				0x08
++#define TRIGGER_BADPLCP				0x10
++#define TRIGGER_CRSGLITCH			0x20
++
++#define	WL_SAMPLEDATA_HEADER_TYPE	1
++#define WL_SAMPLEDATA_HEADER_SIZE	80	/* sample collect header size (bytes) */
++#define	WL_SAMPLEDATA_TYPE		2
++#define	WL_SAMPLEDATA_SEQ		0xff	/* sequence # */
++#define	WL_SAMPLEDATA_MORE_DATA		0x100	/* more data mask */
++
++/* WL_OTA START */
++#define WL_OTA_ARG_PARSE_BLK_SIZE	1200
++#define WL_OTA_TEST_MAX_NUM_RATE	30
++#define WL_OTA_TEST_MAX_NUM_SEQ		100
++#define WL_OTA_TEST_MAX_NUM_RSSI	85
++#define WL_THRESHOLD_LO_BAND	70	/* range from 5250MHz - 5350MHz */
++
++/* radar iovar SET defines */
++#define WL_RADAR_DETECTOR_OFF		0	/* radar detector off */
++#define WL_RADAR_DETECTOR_ON		1	/* radar detector on */
++#define WL_RADAR_SIMULATED		2	/* force radar detector to declare
++						 * detection once
++						 */
++#define WL_RADAR_SIMULATED_SC		3	/* force radar detector to declare
++						 * detection once on scan core
++						 * if available and active
++						 */
++#define WL_RSSI_ANT_VERSION	1	/* current version of wl_rssi_ant_t */
++#define WL_ANT_RX_MAX		2	/* max 2 receive antennas */
++#define WL_ANT_HT_RX_MAX	4	/* max 4 receive antennas/cores */
++#define WL_ANT_IDX_1		0	/* antenna index 1 */
++#define WL_ANT_IDX_2		1	/* antenna index 2 */
++
++#ifndef WL_RSSI_ANT_MAX
++#define WL_RSSI_ANT_MAX		4	/* max possible rx antennas */
++#elif WL_RSSI_ANT_MAX != 4
++#error "WL_RSSI_ANT_MAX does not match"
++#endif
++
++/* dfs_status iovar-related defines */
++
++/* cac - channel availability check,
++ * ism - in-service monitoring
++ * csa - channel switching announcement
++ */
++
++/* cac state values */
++#define WL_DFS_CACSTATE_IDLE		0	/* state for operating in non-radar channel */
++#define	WL_DFS_CACSTATE_PREISM_CAC	1	/* CAC in progress */
++#define WL_DFS_CACSTATE_ISM		2	/* ISM in progress */
++#define WL_DFS_CACSTATE_CSA		3	/* csa */
++#define WL_DFS_CACSTATE_POSTISM_CAC	4	/* ISM CAC */
++#define WL_DFS_CACSTATE_PREISM_OOC	5	/* PREISM OOC */
++#define WL_DFS_CACSTATE_POSTISM_OOC	6	/* POSTISM OOC */
++#define WL_DFS_CACSTATES		7	/* this many states exist */
++
++/* Defines used with channel_bandwidth for curpower */
++#define WL_BW_20MHZ		0
++#define WL_BW_40MHZ		1
++#define WL_BW_80MHZ		2
++#define WL_BW_160MHZ		3
++#define WL_BW_8080MHZ		4
++#define WL_BW_2P5MHZ		5
++#define WL_BW_5MHZ		6
++#define WL_BW_10MHZ		7
++
++/* tx_power_t.flags bits */
++#define WL_TX_POWER_F_ENABLED	1
++#define WL_TX_POWER_F_HW		2
++#define WL_TX_POWER_F_MIMO		4
++#define WL_TX_POWER_F_SISO		8
++#define WL_TX_POWER_F_HT		0x10
++#define WL_TX_POWER_F_VHT		0x20
++#define WL_TX_POWER_F_OPENLOOP		0x40
++#define WL_TX_POWER_F_PROP11NRATES	0x80
++#define WL_TX_POWER_F_UNIT_QDBM		0x100
++/* Message levels */
++#define WL_ERROR_VAL		0x00000001
++#define WL_TRACE_VAL		0x00000002
++#define WL_PRHDRS_VAL		0x00000004
++#define WL_PRPKT_VAL		0x00000008
++#define WL_INFORM_VAL		0x00000010
++#define WL_TMP_VAL		0x00000020
++#define WL_OID_VAL		0x00000040
++#define WL_RATE_VAL		0x00000080
++#define WL_ASSOC_VAL		0x00000100
++#define WL_PRUSR_VAL		0x00000200
++#define WL_PS_VAL		0x00000400
++#define WL_TXPWR_VAL		0x00000000	/* retired in TOT on 6/10/2009 */
++#define WL_MODE_SWITCH_VAL	0x00000800 /* Using retired TXPWR val */
++#define WL_PORT_VAL		0x00001000
++#define WL_DUAL_VAL		0x00002000
++#define WL_WSEC_VAL		0x00004000
++#define WL_WSEC_DUMP_VAL	0x00008000
++#define WL_LOG_VAL		0x00010000
++#define WL_NRSSI_VAL		0x00000000	/* retired in TOT on 6/10/2009 */
++#define WL_BCNTRIM_VAL		0x00020000	/* Using retired NRSSI VAL */
++#define WL_LOFT_VAL		0x00000000	/* retired in TOT on 6/10/2009 */
++#define WL_PFN_VAL		0x00040000 /* Using retired LOFT_VAL */
++#define WL_REGULATORY_VAL	0x00080000
++#define WL_CSA_VAL		0x00080000  /* Reusing REGULATORY_VAL due to lackof bits */
++#define WL_TAF_VAL		0x00100000
++#define WL_RADAR_VAL		0x00000000	/* retired in TOT on 6/10/2009 */
++#define WL_WDI_VAL		0x00200000	/* Using retired WL_RADAR_VAL VAL */
++#define WL_MPC_VAL		0x00400000
++#define WL_APSTA_VAL		0x00800000
++#define WL_DFS_VAL		0x01000000
++#define WL_BA_VAL		0x00000000	/* retired in TOT on 6/14/2010 */
++#define WL_MUMIMO_VAL		0x02000000      /* Using retired WL_BA_VAL */
++#define WL_ACI_VAL		0x04000000
++#define WL_PRMAC_VAL		0x04000000
++#define WL_MBSS_VAL		0x04000000
++#define WL_CAC_VAL		0x08000000
++#define WL_AMSDU_VAL		0x10000000
++#define WL_AMPDU_VAL		0x20000000
++#define WL_FFPLD_VAL		0x40000000
++#define WL_ROAM_EXP_VAL		0x80000000
++
++/* wl_msg_level is full. For new bits take the next one and AND with
++ * wl_msg_level2 in wl_dbg.h
++ */
++#define WL_DPT_VAL		0x00000001
++/* re-using WL_DPT_VAL */
++/* re-using WL_MESH_VAL */
++#define WL_NATOE_VAL		0x00000001
++#define WL_MESH_VAL		0x00000001
++#define WL_SCAN_VAL		0x00000002
++#define WL_WOWL_VAL		0x00000004
++#define WL_COEX_VAL		0x00000008
++#define WL_RTDC_VAL		0x00000010
++#define WL_PROTO_VAL		0x00000020
++#define WL_SWDIV_VAL		0x00000040
++#define WL_CHANINT_VAL		0x00000080
++#define WL_WMF_VAL		0x00000100
++#define WL_P2P_VAL		0x00000200
++#define WL_ITFR_VAL		0x00000400
++#define WL_MCHAN_VAL		0x00000800
++#define WL_TDLS_VAL		0x00001000
++#define WL_MCNX_VAL		0x00002000
++#define WL_PROT_VAL		0x00004000
++#define WL_PSTA_VAL		0x00008000
++#define WL_TSO_VAL		0x00010000
++#define WL_TRF_MGMT_VAL		0x00020000
++#define WL_LPC_VAL	        0x00040000
++#define WL_L2FILTER_VAL		0x00080000
++#define WL_TXBF_VAL		0x00100000
++#define WL_P2PO_VAL		0x00200000
++#define WL_TBTT_VAL		0x00400000
++#define WL_FBT_VAL		0x00800000
++#define WL_RRM_VAL		0x00800000 /* reuse */
++#define WL_MQ_VAL		0x01000000
++
++/* This level is currently used in Phoenix2 only */
++#define WL_SRSCAN_VAL		0x02000000
++
++#define WL_WNM_VAL		0x04000000
++/* re-using WL_WNM_VAL for MBO */
++#define WL_MBO_VAL		0x04000000
++#define WL_PWRSEL_VAL		0x10000000
++#define WL_NET_DETECT_VAL	0x20000000
++#define WL_OCE_VAL  0x20000000 /* reuse */
++#define WL_PCIE_VAL		0x40000000
++#define WL_PMDUR_VAL	0x80000000
++
++
++/* use top-bit for WL_TIME_STAMP_VAL because this is a modifier
++ * rather than a message-type of its own
++ */
++#define WL_TIMESTAMP_VAL        0x80000000
++
++/* max # of leds supported by GPIO (gpio pin# == led index#) */
++#define	WL_LED_NUMGPIO		32	/* gpio 0-31 */
++
++/* led per-pin behaviors */
++#define	WL_LED_OFF		0		/* always off */
++#define	WL_LED_ON		1		/* always on */
++#define	WL_LED_ACTIVITY		2		/* activity */
++#define	WL_LED_RADIO		3		/* radio enabled */
++#define	WL_LED_ARADIO		4		/* 5  Ghz radio enabled */
++#define	WL_LED_BRADIO		5		/* 2.4Ghz radio enabled */
++#define	WL_LED_BGMODE		6		/* on if gmode, off if bmode */
++#define	WL_LED_WI1		7
++#define	WL_LED_WI2		8
++#define	WL_LED_WI3		9
++#define	WL_LED_ASSOC		10		/* associated state indicator */
++#define	WL_LED_INACTIVE		11		/* null behavior (clears default behavior) */
++#define	WL_LED_ASSOCACT		12		/* on when associated; blink fast for activity */
++#define WL_LED_WI4		13
++#define WL_LED_WI5		14
++#define	WL_LED_BLINKSLOW	15		/* blink slow */
++#define	WL_LED_BLINKMED		16		/* blink med */
++#define	WL_LED_BLINKFAST	17		/* blink fast */
++#define	WL_LED_BLINKCUSTOM	18		/* blink custom */
++#define	WL_LED_BLINKPERIODIC	19		/* blink periodic (custom 1000ms / off 400ms) */
++#define WL_LED_ASSOC_WITH_SEC	20		/* when connected with security */
++						/* keep on for 300 sec */
++#define WL_LED_START_OFF	21		/* off upon boot, could be turned on later */
++#define WL_LED_WI6		22
++#define WL_LED_WI7		23
++#define WL_LED_WI8		24
++#define	WL_LED_NUMBEHAVIOR	25
++
++/* led behavior numeric value format */
++#define	WL_LED_BEH_MASK		0x3f		/* behavior mask */
++#define	WL_LED_PMU_OVERRIDE	0x40		/* need to set PMU Override bit for the GPIO */
++#define	WL_LED_AL_MASK		0x80		/* activelow (polarity) bit */
++
++/* number of bytes needed to define a proper bit mask for MAC event reporting */
++#define BCMIO_ROUNDUP(x, y)	((((x) + ((y) - 1)) / (y)) * (y))
++#define BCMIO_NBBY		8
++#define WL_EVENTING_MASK_LEN	(16+4)
++
++#define WL_EVENTING_MASK_EXT_LEN \
++    MAX(WL_EVENTING_MASK_LEN, (ROUNDUP(WLC_E_LAST, NBBY)/NBBY))
++
++/* join preference types */
++#define WL_JOIN_PREF_RSSI	1	/* by RSSI */
++#define WL_JOIN_PREF_WPA	2	/* by akm and ciphers */
++#define WL_JOIN_PREF_BAND	3	/* by 802.11 band */
++#define WL_JOIN_PREF_RSSI_DELTA	4	/* by 802.11 band only if RSSI delta condition matches */
++#define WL_JOIN_PREF_TRANS_PREF	5	/* defined by requesting AP */
++
++/* band preference */
++#define WLJP_BAND_ASSOC_PREF	255	/* use what WLC_SET_ASSOC_PREFER ioctl specifies */
++
++/* any multicast cipher suite */
++#define WL_WPA_ACP_MCS_ANY	"\x00\x00\x00\x00"
++
++/* 802.11h measurement types */
++#define WLC_MEASURE_TPC			1
++#define WLC_MEASURE_CHANNEL_BASIC	2
++#define WLC_MEASURE_CHANNEL_CCA		3
++#define WLC_MEASURE_CHANNEL_RPI		4
++
++/* regulatory enforcement levels */
++#define SPECT_MNGMT_OFF			0		/* both 11h and 11d disabled */
++#define SPECT_MNGMT_LOOSE_11H		1		/* allow non-11h APs in scan lists */
++#define SPECT_MNGMT_STRICT_11H		2		/* prune out non-11h APs from scan list */
++#define SPECT_MNGMT_STRICT_11D		3		/* switch to 802.11D mode */
++/* SPECT_MNGMT_LOOSE_11H_D - same as SPECT_MNGMT_LOOSE with the exception that Country IE
++ * adoption is done regardless of capability spectrum_management
++ */
++#define SPECT_MNGMT_LOOSE_11H_D		4		/* operation defined above */
++
++/* bit position in per_chan_info; these depend on current country/regulatory domain */
++#define WL_CHAN_VALID_HW		(1 << 0)	/* valid with current HW */
++#define WL_CHAN_VALID_SW		(1 << 1)	/* valid with current country setting */
++#define WL_CHAN_BAND_5G			(1 << 2)	/* 5GHz-band channel */
++#define WL_CHAN_RADAR			(1 << 3)	/* radar sensitive channel */
++#define WL_CHAN_INACTIVE		(1 << 4)	/* temporarily inactive due to radar */
++#define WL_CHAN_PASSIVE			(1 << 5)	/* channel is in passive mode */
++#define WL_CHAN_RESTRICTED		(1 << 6)	/* restricted use channel */
++#define WL_CHAN_RADAR_EU_WEATHER	(1 << 7)	/* EU Radar weather channel. Implies an
++							 * EU Radar channel.
++							 */
++#define WL_CHAN_CLM_RESTRICTED		(1 << 8)	/* channel restricted in CLM
++							 * (i.e. by default)
++							 */
++
++/* following definition is for precommit; will be removed once wl, acsd switch to the new def */
++#define WL_CHAN_WEATHER_RADAR		WL_CHAN_RADAR_EU_WEATHER
++
++/* BTC mode used by "btc_mode" iovar */
++#define	WL_BTC_DISABLE		0	/* disable BT coexistence */
++#define WL_BTC_FULLTDM      1	/* full TDM COEX */
++#define WL_BTC_ENABLE       1	/* full TDM COEX to maintain backward compatiblity */
++#define WL_BTC_PREMPT      2    /* full TDM COEX with preemption */
++#define WL_BTC_LITE        3	/* light weight coex for large isolation platform */
++#define WL_BTC_PARALLEL		4   /* BT and WLAN run in parallel with separate antenna  */
++#define WL_BTC_HYBRID		5   /* hybrid coex, only ack is allowed to transmit in BT slot */
++#define WL_BTC_DEFAULT		8	/* set the default mode for the device */
++#define WL_INF_BTC_DISABLE      0
++#define WL_INF_BTC_ENABLE       1
++#define WL_INF_BTC_AUTO         3
++
++/* BTC wire used by "btc_wire" iovar */
++#define	WL_BTC_DEFWIRE		0	/* use default wire setting */
++#define WL_BTC_2WIRE		2	/* use 2-wire BTC */
++#define WL_BTC_3WIRE		3	/* use 3-wire BTC */
++#define WL_BTC_4WIRE		4	/* use 4-wire BTC */
++
++/* BTC flags: BTC configuration that can be set by host */
++#define WL_BTC_FLAG_PREMPT               (1 << 0)
++#define WL_BTC_FLAG_BT_DEF               (1 << 1)
++#define WL_BTC_FLAG_ACTIVE_PROT          (1 << 2)
++#define WL_BTC_FLAG_SIM_RSP              (1 << 3)
++#define WL_BTC_FLAG_PS_PROTECT           (1 << 4)
++#define WL_BTC_FLAG_SIM_TX_LP	         (1 << 5)
++#define WL_BTC_FLAG_ECI                  (1 << 6)
++#define WL_BTC_FLAG_LIGHT                (1 << 7)
++#define WL_BTC_FLAG_PARALLEL             (1 << 8)
++
++/* maximum channels returned by the get valid channels iovar */
++#define WL_NUMCHANNELS		64
++
++/* max number of chanspecs (used by the iovar to calc. buf space) */
++#ifdef WL11AC_80P80
++#define WL_NUMCHANSPECS 206
++#else
++#define WL_NUMCHANSPECS 110
++#endif
++
++/* WDS link local endpoint WPA role */
++#define WL_WDS_WPA_ROLE_AUTH	0	/* authenticator */
++#define WL_WDS_WPA_ROLE_SUP	1	/* supplicant */
++#define WL_WDS_WPA_ROLE_AUTO	255	/* auto, based on mac addr value */
++
++/* Base offset values */
++#define WL_PKT_FILTER_BASE_PKT   0
++#define WL_PKT_FILTER_BASE_END   1
++#define WL_PKT_FILTER_BASE_D11_H 2 /* May be removed */
++#define WL_PKT_FILTER_BASE_D11_D 3 /* May be removed */
++#define WL_PKT_FILTER_BASE_ETH_H 4
++#define WL_PKT_FILTER_BASE_ETH_D 5
++#define WL_PKT_FILTER_BASE_ARP_H 6
++#define WL_PKT_FILTER_BASE_ARP_D 7 /* May be removed */
++#define WL_PKT_FILTER_BASE_IP4_H 8
++#define WL_PKT_FILTER_BASE_IP4_D 9
++#define WL_PKT_FILTER_BASE_IP6_H 10
++#define WL_PKT_FILTER_BASE_IP6_D 11
++#define WL_PKT_FILTER_BASE_TCP_H 12
++#define WL_PKT_FILTER_BASE_TCP_D 13 /* May be removed */
++#define WL_PKT_FILTER_BASE_UDP_H 14
++#define WL_PKT_FILTER_BASE_UDP_D 15
++#define WL_PKT_FILTER_BASE_IP6_P 16
++#define WL_PKT_FILTER_BASE_COUNT 17 /* May be removed */
++
++/* String mapping for bases that may be used by applications or debug */
++#define WL_PKT_FILTER_BASE_NAMES \
++	{ "START", WL_PKT_FILTER_BASE_PKT },   \
++	{ "END",   WL_PKT_FILTER_BASE_END },   \
++	{ "ETH_H", WL_PKT_FILTER_BASE_ETH_H }, \
++	{ "ETH_D", WL_PKT_FILTER_BASE_ETH_D }, \
++	{ "D11_H", WL_PKT_FILTER_BASE_D11_H }, \
++	{ "D11_D", WL_PKT_FILTER_BASE_D11_D }, \
++	{ "ARP_H", WL_PKT_FILTER_BASE_ARP_H }, \
++	{ "IP4_H", WL_PKT_FILTER_BASE_IP4_H }, \
++	{ "IP4_D", WL_PKT_FILTER_BASE_IP4_D }, \
++	{ "IP6_H", WL_PKT_FILTER_BASE_IP6_H }, \
++	{ "IP6_D", WL_PKT_FILTER_BASE_IP6_D }, \
++	{ "IP6_P", WL_PKT_FILTER_BASE_IP6_P }, \
++	{ "TCP_H", WL_PKT_FILTER_BASE_TCP_H }, \
++	{ "TCP_D", WL_PKT_FILTER_BASE_TCP_D }, \
++	{ "UDP_H", WL_PKT_FILTER_BASE_UDP_H }, \
++	{ "UDP_D", WL_PKT_FILTER_BASE_UDP_D }
++
++/* Flags for a pattern list element */
++#define WL_PKT_FILTER_MFLAG_NEG 0x0001
++
++/*
++ * Packet engine interface
++ */
++
++#define WL_PKTENG_PER_TX_START			0x01
++#define WL_PKTENG_PER_TX_STOP			0x02
++#define WL_PKTENG_PER_RX_START			0x04
++#define WL_PKTENG_PER_RX_WITH_ACK_START		0x05
++#define WL_PKTENG_PER_TX_WITH_ACK_START		0x06
++#define WL_PKTENG_PER_RX_STOP			0x08
++#define WL_PKTENG_PER_RU_TX_START		0x09
++#define WL_PKTENG_PER_MASK			0xff
++
++#define WL_PKTENG_SYNCHRONOUS			0x100	/* synchronous flag */
++#define WL_PKTENG_SYNCHRONOUS_UNBLK		0x200	/* synchronous unblock flag */
++#ifdef PKTENG_LONGPKTSZ
++/* max pktsz limit for pkteng */
++#define WL_PKTENG_MAXPKTSZ				PKTENG_LONGPKTSZ
++#else
++#define WL_PKTENG_MAXPKTSZ				16384
++#endif
++
++#define NUM_80211b_RATES	4
++#define NUM_80211ag_RATES	8
++#define NUM_80211n_RATES	32
++#define NUM_80211_RATES		(NUM_80211b_RATES+NUM_80211ag_RATES+NUM_80211n_RATES)
++
++/*
++ * WOWL capability/override settings
++ */
++#define WL_WOWL_MAGIC           (1 << 0)    /* Wakeup on Magic packet */
++#define WL_WOWL_NET             (1 << 1)    /* Wakeup on Netpattern */
++#define WL_WOWL_DIS             (1 << 2)    /* Wakeup on loss-of-link due to Disassoc/Deauth */
++#define WL_WOWL_RETR            (1 << 3)    /* Wakeup on retrograde TSF */
++#define WL_WOWL_BCN             (1 << 4)    /* Wakeup on loss of beacon */
++#define WL_WOWL_TST             (1 << 5)    /* Wakeup after test */
++#define WL_WOWL_M1              (1 << 6)    /* Wakeup after PTK refresh */
++#define WL_WOWL_EAPID           (1 << 7)    /* Wakeup after receipt of EAP-Identity Req */
++#define WL_WOWL_PME_GPIO        (1 << 8)    /* Wakeind via PME(0) or GPIO(1) */
++#define WL_WOWL_ULP_BAILOUT     (1 << 8)    /* wakeind via unknown pkt by basic ULP-offloads -
++ * WL_WOWL_ULP_BAILOUT - same as WL_WOWL_PME_GPIO used only for DONGLE BUILDS
++ */
++#define WL_WOWL_NEEDTKIP1       (1 << 9)    /* need tkip phase 1 key to be updated by the driver */
++#define WL_WOWL_GTK_FAILURE     (1 << 10)   /* enable wakeup if GTK fails */
++#define WL_WOWL_EXTMAGPAT       (1 << 11)   /* support extended magic packets */
++#define WL_WOWL_ARPOFFLOAD      (1 << 12)   /* support ARP/NS/keepalive offloading */
++#define WL_WOWL_WPA2            (1 << 13)   /* read protocol version for EAPOL frames */
++#define WL_WOWL_KEYROT          (1 << 14)   /* If the bit is set, use key rotaton */
++#define WL_WOWL_BCAST           (1 << 15)   /* If the bit is set, frm received was bcast frame */
++#define WL_WOWL_SCANOL          (1 << 16)   /* If the bit is set, scan offload is enabled */
++#define WL_WOWL_TCPKEEP_TIME    (1 << 17)   /* Wakeup on tcpkeep alive timeout */
++#define WL_WOWL_MDNS_CONFLICT   (1 << 18)   /* Wakeup on mDNS Conflict Resolution */
++#define WL_WOWL_MDNS_SERVICE    (1 << 19)   /* Wakeup on mDNS Service Connect */
++#define WL_WOWL_TCPKEEP_DATA    (1 << 20)   /* tcp keepalive got data */
++#define WL_WOWL_FW_HALT         (1 << 21)   /* Firmware died in wowl mode */
++#define WL_WOWL_ENAB_HWRADIO    (1 << 22)   /* Enable detection of radio button changes */
++#define WL_WOWL_MIC_FAIL        (1 << 23)   /* Offloads detected MIC failure(s) */
++#define WL_WOWL_UNASSOC         (1 << 24)   /* Wakeup in Unassociated state (Net/Magic Pattern) */
++#define WL_WOWL_SECURE          (1 << 25)   /* Wakeup if received matched secured pattern */
++#define WL_WOWL_EXCESS_WAKE     (1 << 26)   /* Excess wake */
++#define WL_WOWL_LINKDOWN        (1 << 31)   /* Link Down indication in WoWL mode */
++
++#define WL_WOWL_TCPKEEP         (1 << 20)   /* temp copy to satisfy automerger */
++#define MAGIC_PKT_MINLEN 102    /* Magic pkt min length is 6 * 0xFF + 16 * ETHER_ADDR_LEN */
++
++#define WOWL_PATTEN_TYPE_ARP	(1 << 0)	/* ARP offload Pattern */
++#define WOWL_PATTEN_TYPE_NA	(1 << 1)	/* NA offload Pattern */
++
++#define MAGIC_PKT_MINLEN	102    /* Magic pkt min length is 6 * 0xFF + 16 * ETHER_ADDR_LEN */
++#define MAGIC_PKT_NUM_MAC_ADDRS	16
++
++/* Overlap BSS Scan parameters default, minimum, maximum */
++#define WLC_OBSS_SCAN_PASSIVE_DWELL_DEFAULT		20	/* unit TU */
++#define WLC_OBSS_SCAN_PASSIVE_DWELL_MIN			5	/* unit TU */
++#define WLC_OBSS_SCAN_PASSIVE_DWELL_MAX			1000	/* unit TU */
++#define WLC_OBSS_SCAN_ACTIVE_DWELL_DEFAULT		10	/* unit TU */
++#define WLC_OBSS_SCAN_ACTIVE_DWELL_MIN			10	/* unit TU */
++#define WLC_OBSS_SCAN_ACTIVE_DWELL_MAX			1000	/* unit TU */
++#define WLC_OBSS_SCAN_WIDTHSCAN_INTERVAL_DEFAULT	300	/* unit Sec */
++#define WLC_OBSS_SCAN_WIDTHSCAN_INTERVAL_MIN		10	/* unit Sec */
++#define WLC_OBSS_SCAN_WIDTHSCAN_INTERVAL_MAX		900	/* unit Sec */
++#define WLC_OBSS_SCAN_CHANWIDTH_TRANSITION_DLY_DEFAULT	5
++#define WLC_OBSS_SCAN_CHANWIDTH_TRANSITION_DLY_MIN	5
++#define WLC_OBSS_SCAN_CHANWIDTH_TRANSITION_DLY_MAX	100
++#define WLC_OBSS_SCAN_PASSIVE_TOTAL_PER_CHANNEL_DEFAULT	200	/* unit TU */
++#define WLC_OBSS_SCAN_PASSIVE_TOTAL_PER_CHANNEL_MIN	200	/* unit TU */
++#define WLC_OBSS_SCAN_PASSIVE_TOTAL_PER_CHANNEL_MAX	10000	/* unit TU */
++#define WLC_OBSS_SCAN_ACTIVE_TOTAL_PER_CHANNEL_DEFAULT	20	/* unit TU */
++#define WLC_OBSS_SCAN_ACTIVE_TOTAL_PER_CHANNEL_MIN	20	/* unit TU */
++#define WLC_OBSS_SCAN_ACTIVE_TOTAL_PER_CHANNEL_MAX	10000	/* unit TU */
++#define WLC_OBSS_SCAN_ACTIVITY_THRESHOLD_DEFAULT	25	/* unit percent */
++#define WLC_OBSS_SCAN_ACTIVITY_THRESHOLD_MIN		0	/* unit percent */
++#define WLC_OBSS_SCAN_ACTIVITY_THRESHOLD_MAX		100	/* unit percent */
++
++#define WL_MIN_NUM_OBSS_SCAN_ARG 7	/* minimum number of arguments required for OBSS Scan */
++
++#define WL_COEX_INFO_MASK		0x07
++#define WL_COEX_INFO_REQ		0x01
++#define	WL_COEX_40MHZ_INTOLERANT	0x02
++#define	WL_COEX_WIDTH20			0x04
++
++#define	WLC_RSSI_INVALID	 0	/* invalid RSSI value */
++
++#define MAX_RSSI_LEVELS 8
++
++/* **** EXTLOG **** */
++#define EXTLOG_CUR_VER		0x0100
++
++#define MAX_ARGSTR_LEN		18 /* At least big enough for storing ETHER_ADDR_STR_LEN */
++
++/* log modules (bitmap) */
++#define LOG_MODULE_COMMON	0x0001
++#define LOG_MODULE_ASSOC	0x0002
++#define LOG_MODULE_EVENT	0x0004
++#define LOG_MODULE_MAX		3			/* Update when adding module */
++
++/* log levels */
++#define WL_LOG_LEVEL_DISABLE	0
++#define WL_LOG_LEVEL_ERR	1
++#define WL_LOG_LEVEL_WARN	2
++#define WL_LOG_LEVEL_INFO	3
++#define WL_LOG_LEVEL_MAX	WL_LOG_LEVEL_INFO	/* Update when adding level */
++
++/* flag */
++#define LOG_FLAG_EVENT		1
++
++/* log arg_type */
++#define LOG_ARGTYPE_NULL	0
++#define LOG_ARGTYPE_STR		1	/* %s */
++#define LOG_ARGTYPE_INT		2	/* %d */
++#define LOG_ARGTYPE_INT_STR	3	/* %d...%s */
++#define LOG_ARGTYPE_STR_INT	4	/* %s...%d */
++
++/* 802.11 Mgmt Packet flags */
++#define VNDR_IE_BEACON_FLAG	0x1
++#define VNDR_IE_PRBRSP_FLAG	0x2
++#define VNDR_IE_ASSOCRSP_FLAG	0x4
++#define VNDR_IE_AUTHRSP_FLAG	0x8
++#define VNDR_IE_PRBREQ_FLAG	0x10
++#define VNDR_IE_ASSOCREQ_FLAG	0x20
++#define VNDR_IE_IWAPID_FLAG	0x40 /* vendor IE in IW advertisement protocol ID field */
++#define VNDR_IE_AUTHREQ_FLAG	0x80
++#define VNDR_IE_CUSTOM_FLAG	0x100 /* allow custom IE id */
++#define VNDR_IE_DISASSOC_FLAG	0x200
++
++#if defined(WLP2P)
++/* P2P Action Frames flags (spec ordered) */
++#define VNDR_IE_GONREQ_FLAG     0x001000
++#define VNDR_IE_GONRSP_FLAG     0x002000
++#define VNDR_IE_GONCFM_FLAG     0x004000
++#define VNDR_IE_INVREQ_FLAG     0x008000
++#define VNDR_IE_INVRSP_FLAG     0x010000
++#define VNDR_IE_DISREQ_FLAG     0x020000
++#define VNDR_IE_DISRSP_FLAG     0x040000
++#define VNDR_IE_PRDREQ_FLAG     0x080000
++#define VNDR_IE_PRDRSP_FLAG     0x100000
++
++#define VNDR_IE_P2PAF_SHIFT	12
++#endif /* WLP2P */
++
++/* channel interference measurement (chanim) related defines */
++
++/* chanim mode */
++#define CHANIM_DISABLE	0	/* disabled */
++#define CHANIM_DETECT	1	/* detection only */
++#define CHANIM_EXT		2	/* external state machine */
++#define CHANIM_ACT		3	/* full internal state machine, detect + act */
++#define CHANIM_MODE_MAX 4
++
++/* define for apcs reason code */
++#define APCS_INIT		0
++#define APCS_IOCTL		1
++#define APCS_CHANIM		2
++#define APCS_CSTIMER		3
++#define APCS_TXDLY		5
++#define APCS_NONACSD		6
++#define APCS_DFS_REENTRY	7
++#define APCS_TXFAIL		8
++#define APCS_MAX		9
++
++/* number of ACS record entries */
++#define CHANIM_ACS_RECORD			10
++
++/* CHANIM */
++#define CCASTATS_TXDUR  0
++#define CCASTATS_INBSS  1
++#define CCASTATS_OBSS   2
++#define CCASTATS_NOCTG  3
++#define CCASTATS_NOPKT  4
++#define CCASTATS_DOZE   5
++#define CCASTATS_TXOP	6
++#define CCASTATS_GDTXDUR        7
++#define CCASTATS_BDTXDUR        8
++
++#ifndef WLCHANIM_V2
++#define CCASTATS_MAX    9
++#else /* WLCHANIM_V2 */
++#define CCASTATS_MYRX      9
++#define CCASTATS_MAX    10
++#endif /* WLCHANIM_V2 */
++
++#define WL_CHANIM_COUNT_ALL	0xff
++#define WL_CHANIM_COUNT_ONE	0x1
++
++/* ap tpc modes */
++#define	AP_TPC_OFF		0
++#define	AP_TPC_BSS_PWR		1	/* BSS power control */
++#define AP_TPC_AP_PWR		2	/* AP power control */
++#define	AP_TPC_AP_BSS_PWR	3	/* Both AP and BSS power control */
++#define AP_TPC_MAX_LINK_MARGIN	127
++
++/* ap tpc modes */
++#define	AP_TPC_OFF		0
++#define	AP_TPC_BSS_PWR		1	/* BSS power control */
++#define AP_TPC_AP_PWR		2	/* AP power control */
++#define	AP_TPC_AP_BSS_PWR	3	/* Both AP and BSS power control */
++#define AP_TPC_MAX_LINK_MARGIN	127
++
++/* state */
++#define WL_P2P_DISC_ST_SCAN	0
++#define WL_P2P_DISC_ST_LISTEN	1
++#define WL_P2P_DISC_ST_SEARCH	2
++
++/* i/f type */
++#define WL_P2P_IF_CLIENT	0
++#define WL_P2P_IF_GO		1
++#define WL_P2P_IF_DYNBCN_GO	2
++#define WL_P2P_IF_DEV		3
++
++/* count */
++#define WL_P2P_SCHED_RSVD	0
++#define WL_P2P_SCHED_REPEAT	255	/* anything > 255 will be treated as 255 */
++
++#define WL_P2P_SCHED_FIXED_LEN		3
++
++/* schedule type */
++#define WL_P2P_SCHED_TYPE_ABS		0	/* Scheduled Absence */
++#define WL_P2P_SCHED_TYPE_REQ_ABS	1	/* Requested Absence */
++
++/* schedule action during absence periods (for WL_P2P_SCHED_ABS type) */
++#define WL_P2P_SCHED_ACTION_NONE	0	/* no action */
++#define WL_P2P_SCHED_ACTION_DOZE	1	/* doze */
++/* schedule option - WL_P2P_SCHED_TYPE_REQ_ABS */
++#define WL_P2P_SCHED_ACTION_GOOFF	2	/* turn off GO beacon/prbrsp functions */
++/* schedule option - WL_P2P_SCHED_TYPE_XXX */
++#define WL_P2P_SCHED_ACTION_RESET	255	/* reset */
++
++/* schedule option - WL_P2P_SCHED_TYPE_ABS */
++#define WL_P2P_SCHED_OPTION_NORMAL	0	/* normal start/interval/duration/count */
++#define WL_P2P_SCHED_OPTION_BCNPCT	1	/* percentage of beacon interval */
++/* schedule option - WL_P2P_SCHED_TYPE_REQ_ABS */
++#define WL_P2P_SCHED_OPTION_TSFOFS	2	/* normal start/internal/duration/count with
++						 * start being an offset of the 'current' TSF
++						 */
++
++/* feature flags */
++#define WL_P2P_FEAT_GO_CSA	(1 << 0)	/* GO moves with the STA using CSA method */
++#define WL_P2P_FEAT_GO_NOLEGACY	(1 << 1)	/* GO does not probe respond to non-p2p probe
++						 * requests
++						 */
++#define WL_P2P_FEAT_RESTRICT_DEV_RESP (1 << 2)	/* Restrict p2p dev interface from responding */
++
++/* n-mode support capability */
++/* 2x2 includes both 1x1 & 2x2 devices
++ * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
++ * control it independently
++ */
++#define WL_11N_2x2			1
++#define WL_11N_3x3			3
++#define WL_11N_4x4			4
++
++/* define 11n feature disable flags */
++#define WLFEATURE_DISABLE_11N		0x00000001
++#define WLFEATURE_DISABLE_11N_STBC_TX	0x00000002
++#define WLFEATURE_DISABLE_11N_STBC_RX	0x00000004
++#define WLFEATURE_DISABLE_11N_SGI_TX	0x00000008
++#define WLFEATURE_DISABLE_11N_SGI_RX	0x00000010
++#define WLFEATURE_DISABLE_11N_AMPDU_TX	0x00000020
++#define WLFEATURE_DISABLE_11N_AMPDU_RX	0x00000040
++#define WLFEATURE_DISABLE_11N_GF	0x00000080
++
++/* Proxy STA modes */
++#define PSTA_MODE_DISABLED		0
++#define PSTA_MODE_PROXY			1
++#define PSTA_MODE_REPEATER		2
++
++/* op code in nat_cfg */
++#define NAT_OP_ENABLE		1	/* enable NAT on given interface */
++#define NAT_OP_DISABLE		2	/* disable NAT on given interface */
++#define NAT_OP_DISABLE_ALL	3	/* disable NAT on all interfaces */
++
++/* NAT state */
++#define NAT_STATE_ENABLED	1	/* NAT is enabled */
++#define NAT_STATE_DISABLED	2	/* NAT is disabled */
++
++#define CHANNEL_5G_LOW_START	36	/* 5G low (36..48) CDD enable/disable bit mask */
++#define CHANNEL_5G_MID_START	52	/* 5G mid (52..64) CDD enable/disable bit mask */
++#define CHANNEL_5G_HIGH_START	100	/* 5G high (100..140) CDD enable/disable bit mask */
++#define CHANNEL_5G_UPPER_START	149	/* 5G upper (149..161) CDD enable/disable bit mask */
++
++/* D0 Coalescing */
++#define IPV4_ARP_FILTER		0x0001
++#define IPV4_NETBT_FILTER	0x0002
++#define IPV4_LLMNR_FILTER	0x0004
++#define IPV4_SSDP_FILTER	0x0008
++#define IPV4_WSD_FILTER		0x0010
++#define IPV6_NETBT_FILTER	0x0200
++#define IPV6_LLMNR_FILTER	0x0400
++#define IPV6_SSDP_FILTER	0x0800
++#define IPV6_WSD_FILTER		0x1000
++
++/* Network Offload Engine */
++#define NWOE_OL_ENABLE		0x00000001
++
++/*
++ * Traffic management structures/defines.
++ */
++
++/* Traffic management bandwidth parameters */
++#define TRF_MGMT_MAX_PRIORITIES                 3
++
++#define TRF_MGMT_FLAG_ADD_DSCP                  0x0001  /* Add DSCP to IP TOS field */
++#define TRF_MGMT_FLAG_DISABLE_SHAPING           0x0002  /* Don't shape traffic */
++#define TRF_MGMT_FLAG_MANAGE_LOCAL_TRAFFIC      0x0008  /* Manage traffic over our local subnet */
++#define TRF_MGMT_FLAG_FILTER_ON_MACADDR         0x0010  /* filter on MAC address */
++#define TRF_MGMT_FLAG_NO_RX                     0x0020  /* do not apply fiters to rx packets */
++
++#define TRF_FILTER_MAC_ADDR              0x0001 /* L2 filter use dst mac address for filtering */
++#define TRF_FILTER_IP_ADDR               0x0002 /* L3 filter use ip ddress for filtering */
++#define TRF_FILTER_L4                    0x0004 /* L4 filter use tcp/udp for filtering */
++#define TRF_FILTER_DWM                   0x0008 /* L3 filter use DSCP for filtering */
++#define TRF_FILTER_FAVORED               0x0010 /* Tag the packet FAVORED */
++
++/* WNM/NPS subfeatures mask */
++#define WL_WNM_BSSTRANS		0x00000001
++#define WL_WNM_PROXYARP		0x00000002
++#define WL_WNM_MAXIDLE		0x00000004
++#define WL_WNM_TIMBC		0x00000008
++#define WL_WNM_TFS		0x00000010
++#define WL_WNM_SLEEP		0x00000020
++#define WL_WNM_DMS		0x00000040
++#define WL_WNM_FMS		0x00000080
++#define WL_WNM_NOTIF		0x00000100
++#define WL_WNM_WBTEXT	0x00000200
++#define WL_WNM_MAX		0x00000400
++#ifdef WLWNM_BRCM
++#define BRCM_WNM_FEATURE_SET\
++					(WL_WNM_PROXYARP | \
++					WL_WNM_SLEEP | \
++					WL_WNM_FMS | \
++					WL_WNM_TFS | \
++					WL_WNM_TIMBC | \
++					WL_WNM_BSSTRANS | \
++					WL_WNM_DMS | \
++					WL_WNM_NOTIF | \
++					0)
++#endif /* WLWNM_BRCM */
++#ifndef ETHER_MAX_DATA
++#define ETHER_MAX_DATA	1500
++#endif /* ETHER_MAX_DATA */
++
++/* Different discovery modes for dpt */
++#define	DPT_DISCOVERY_MANUAL	0x01	/* manual discovery mode */
++#define	DPT_DISCOVERY_AUTO	0x02	/* auto discovery mode */
++#define	DPT_DISCOVERY_SCAN	0x04	/* scan-based discovery mode */
++
++/* different path selection values */
++#define DPT_PATHSEL_AUTO	0	/* auto mode for path selection */
++#define DPT_PATHSEL_DIRECT	1	/* always use direct DPT path */
++#define DPT_PATHSEL_APPATH	2	/* always use AP path */
++
++/* different ops for deny list */
++#define DPT_DENY_LIST_ADD	1	/* add to dpt deny list */
++#define DPT_DENY_LIST_REMOVE	2	/* remove from dpt deny list */
++
++/* different ops for manual end point */
++#define DPT_MANUAL_EP_CREATE	1	/* create manual dpt endpoint */
++#define DPT_MANUAL_EP_MODIFY	2	/* modify manual dpt endpoint */
++#define DPT_MANUAL_EP_DELETE	3	/* delete manual dpt endpoint */
++
++/* flags to indicate DPT status */
++#define	DPT_STATUS_ACTIVE	0x01	/* link active (though may be suspended) */
++#define	DPT_STATUS_AES		0x02	/* link secured through AES encryption */
++#define	DPT_STATUS_FAILED	0x04	/* DPT link failed */
++
++#ifdef WLTDLS
++/* different ops for manual end point */
++#define TDLS_MANUAL_EP_CREATE	1	/* create manual dpt endpoint */
++#define TDLS_MANUAL_EP_MODIFY	2	/* modify manual dpt endpoint */
++#define TDLS_MANUAL_EP_DELETE	3	/* delete manual dpt endpoint */
++#define TDLS_MANUAL_EP_PM		4	/*  put dpt endpoint in PM mode */
++#define TDLS_MANUAL_EP_WAKE		5	/* wake up dpt endpoint from PM */
++#define TDLS_MANUAL_EP_DISCOVERY	6	/* discover if endpoint is TDLS capable */
++#define TDLS_MANUAL_EP_CHSW		7	/* channel switch */
++#define TDLS_MANUAL_EP_WFD_TPQ	8	/* WiFi-Display Tunneled Probe reQuest */
++
++/* modes */
++#define TDLS_WFD_IE_TX			0
++#define TDLS_WFD_IE_RX			1
++#define TDLS_WFD_PROBE_IE_TX	2
++#define TDLS_WFD_PROBE_IE_RX	3
++#endif /* WLTDLS */
++
++/* define for flag */
++#define TSPEC_PENDING		0	/* TSPEC pending */
++#define TSPEC_ACCEPTED		1	/* TSPEC accepted */
++#define TSPEC_REJECTED		2	/* TSPEC rejected */
++#define TSPEC_UNKNOWN		3	/* TSPEC unknown */
++#define TSPEC_STATUS_MASK	7	/* TSPEC status mask */
++
++
++/* Software feature flag defines used by wlfeatureflag */
++#ifdef WLAFTERBURNER
++#define WL_SWFL_ABBFL       0x0001 /* Allow Afterburner on systems w/o hardware BFL */
++#define WL_SWFL_ABENCORE    0x0002 /* Allow AB on non-4318E chips */
++#endif /* WLAFTERBURNER */
++#define WL_SWFL_NOHWRADIO	0x0004
++#define WL_SWFL_FLOWCONTROL     0x0008 /* Enable backpressure to OS stack */
++#define WL_SWFL_WLBSSSORT	0x0010 /* Per-port supports sorting of BSS */
++
++#define WL_LIFETIME_MAX 0xFFFF /* Max value in ms */
++
++#define CSA_BROADCAST_ACTION_FRAME	0	/* csa broadcast action frame */
++#define CSA_UNICAST_ACTION_FRAME	  1 /* csa unicast action frame */
++
++/* Roaming trigger definitions for WLC_SET_ROAM_TRIGGER.
++ *
++ * (-100 < value < 0)   value is used directly as a roaming trigger in dBm
++ * (0 <= value) value specifies a logical roaming trigger level from
++ *                      the list below
++ *
++ * WLC_GET_ROAM_TRIGGER always returns roaming trigger value in dBm, never
++ * the logical roam trigger value.
++ */
++#define WLC_ROAM_TRIGGER_DEFAULT	0 /* default roaming trigger */
++#define WLC_ROAM_TRIGGER_BANDWIDTH	1 /* optimize for bandwidth roaming trigger */
++#define WLC_ROAM_TRIGGER_DISTANCE	2 /* optimize for distance roaming trigger */
++#define WLC_ROAM_TRIGGER_AUTO		3 /* auto-detect environment */
++#define WLC_ROAM_TRIGGER_MAX_VALUE	3 /* max. valid value */
++
++#define WLC_ROAM_NEVER_ROAM_TRIGGER	(-100) /* Avoid Roaming by setting a large value */
++
++/* Preferred Network Offload (PNO, formerly PFN) defines */
++#define WPA_AUTH_PFN_ANY	0xffffffff	/* for PFN, match only ssid */
++
++#define SORT_CRITERIA_BIT		0
++#define AUTO_NET_SWITCH_BIT		1
++#define ENABLE_BKGRD_SCAN_BIT		2
++#define IMMEDIATE_SCAN_BIT		3
++#define	AUTO_CONNECT_BIT		4
++#define	ENABLE_BD_SCAN_BIT		5
++#define ENABLE_ADAPTSCAN_BIT		6
++#define IMMEDIATE_EVENT_BIT		8
++#define SUPPRESS_SSID_BIT		9
++#define ENABLE_NET_OFFLOAD_BIT		10
++/* report found/lost events for SSID and BSSID networks seperately */
++#define REPORT_SEPERATELY_BIT		11
++#define BESTN_BSSID_ONLY_BIT		12
++
++#define SORT_CRITERIA_MASK		0x0001
++#define AUTO_NET_SWITCH_MASK		0x0002
++#define ENABLE_BKGRD_SCAN_MASK		0x0004
++#define IMMEDIATE_SCAN_MASK		0x0008
++#define	AUTO_CONNECT_MASK		0x0010
++
++#define ENABLE_BD_SCAN_MASK		0x0020
++#define ENABLE_ADAPTSCAN_MASK		0x00c0
++#define IMMEDIATE_EVENT_MASK		0x0100
++#define SUPPRESS_SSID_MASK		0x0200
++#define ENABLE_NET_OFFLOAD_MASK		0x0400
++/* report found/lost events for SSID and BSSID networks seperately */
++#define REPORT_SEPERATELY_MASK		0x0800
++#define BESTN_BSSID_ONLY_MASK		0x1000
++
++#define PFN_VERSION			2
++#ifdef PFN_SCANRESULT_2
++#define PFN_SCANRESULT_VERSION		2
++#else
++#define PFN_SCANRESULT_VERSION		1
++#endif /* PFN_SCANRESULT_2 */
++#ifndef MAX_PFN_LIST_COUNT
++#define MAX_PFN_LIST_COUNT		16
++#endif /* MAX_PFN_LIST_COUNT */
++
++#define PFN_COMPLETE			1
++#define PFN_INCOMPLETE			0
++
++#define DEFAULT_BESTN			2
++#define DEFAULT_MSCAN			0
++#define DEFAULT_REPEAT			10
++#define DEFAULT_EXP				2
++
++#define PFN_PARTIAL_SCAN_BIT		0
++#define PFN_PARTIAL_SCAN_MASK		1
++
++#define WL_PFN_SUPPRESSFOUND_MASK	0x08
++#define WL_PFN_SUPPRESSLOST_MASK	0x10
++#define WL_PFN_SSID_A_BAND_TRIG		0x20
++#define WL_PFN_SSID_BG_BAND_TRIG	0x40
++#define WL_PFN_SSID_IMPRECISE_MATCH	0x80
++#define WL_PFN_SSID_SAME_NETWORK	0x10000
++#define WL_PFN_SUPPRESS_AGING_MASK	0x20000
++#define WL_PFN_FLUSH_ALL_SSIDS		0x40000
++#define WL_PFN_RSSI_MASK		0xff00
++#define WL_PFN_RSSI_SHIFT		8
++
++#define WL_PFN_REPORT_ALLNET    0
++#define WL_PFN_REPORT_SSIDNET   1
++#define WL_PFN_REPORT_BSSIDNET  2
++
++#define WL_PFN_CFG_FLAGS_PROHIBITED	0x00000001	/* Accept and use prohibited channels */
++#define WL_PFN_CFG_FLAGS_HISTORY_OFF	0x00000002	/* Scan history suppressed */
++
++#define WL_PFN_HIDDEN_BIT		2
++#define PNO_SCAN_MAX_FW			508*1000	/* max time scan time in msec */
++#define PNO_SCAN_MAX_FW_SEC		PNO_SCAN_MAX_FW/1000 /* max time scan time in SEC */
++#define PNO_SCAN_MIN_FW_SEC		10			/* min time scan time in SEC */
++#define WL_PFN_HIDDEN_MASK		0x4
++#define MAX_SSID_WHITELIST_NUM         4
++#define MAX_BSSID_PREF_LIST_NUM        32
++#define MAX_BSSID_BLACKLIST_NUM        32
++
++#ifndef BESTN_MAX
++#define BESTN_MAX			10
++#endif
++
++#ifndef MSCAN_MAX
++#define MSCAN_MAX			32
++#endif
++
++/* TCP Checksum Offload error injection for testing */
++#define TOE_ERRTEST_TX_CSUM	0x00000001
++#define TOE_ERRTEST_RX_CSUM	0x00000002
++#define TOE_ERRTEST_RX_CSUM2	0x00000004
++
++/* ARP Offload feature flags for arp_ol iovar */
++#define ARP_OL_AGENT		0x00000001
++#define ARP_OL_SNOOP		0x00000002
++#define ARP_OL_HOST_AUTO_REPLY	0x00000004
++#define ARP_OL_PEER_AUTO_REPLY	0x00000008
++
++/* ARP Offload error injection */
++#define ARP_ERRTEST_REPLY_PEER	0x1
++#define ARP_ERRTEST_REPLY_HOST	0x2
++
++#define ARP_MULTIHOMING_MAX	8	/* Maximum local host IP addresses */
++#define ND_MULTIHOMING_MAX 10	/* Maximum local host IP addresses */
++#define ND_REQUEST_MAX		5	/* Max set of offload params */
++/* AOAC wake event flag */
++#define WAKE_EVENT_NLO_DISCOVERY_BIT		1
++#define WAKE_EVENT_AP_ASSOCIATION_LOST_BIT	2
++#define WAKE_EVENT_GTK_HANDSHAKE_ERROR_BIT 4
++#define WAKE_EVENT_4WAY_HANDSHAKE_REQUEST_BIT 8
++#define WAKE_EVENT_NET_PACKET_BIT 0x10
++
++#define MAX_NUM_WOL_PATTERN	22 /* LOGO requirements min 22 */
++
++
++/* Packet filter operation mode */
++/* True: 1; False: 0 */
++#define PKT_FILTER_MODE_FORWARD_ON_MATCH		1
++/* Enable and disable pkt_filter as a whole */
++#define PKT_FILTER_MODE_DISABLE					2
++/* Cache first matched rx pkt(be queried by host later) */
++#define PKT_FILTER_MODE_PKT_CACHE_ON_MATCH		4
++/* If pkt_filter is enabled and no filter is set, don't forward anything */
++#define PKT_FILTER_MODE_PKT_FORWARD_OFF_DEFAULT 8
++
++#ifdef DONGLEOVERLAYS
++#define OVERLAY_IDX_MASK		0x000000ff
++#define OVERLAY_IDX_SHIFT		0
++#define OVERLAY_FLAGS_MASK		0xffffff00
++#define OVERLAY_FLAGS_SHIFT		8
++/* overlay written to device memory immediately after loading the base image */
++#define OVERLAY_FLAG_POSTLOAD	0x100
++/* defer overlay download until the device responds w/WLC_E_OVL_DOWNLOAD event */
++#define OVERLAY_FLAG_DEFER_DL	0x200
++/* overlay downloaded prior to the host going to sleep */
++#define OVERLAY_FLAG_PRESLEEP	0x400
++#define OVERLAY_DOWNLOAD_CHUNKSIZE	1024
++#endif /* DONGLEOVERLAYS */
++
++/* reuse two number in the sc/rc space */
++#define	SMFS_CODE_MALFORMED 0xFFFE
++#define SMFS_CODE_IGNORED	0xFFFD
++
++/* RFAWARE def */
++#define BCM_ACTION_RFAWARE		0x77
++#define BCM_ACTION_RFAWARE_DCS  0x01
++
++/* DCS reason code define */
++#define BCM_DCS_IOVAR		0x1
++#define BCM_DCS_UNKNOWN		0xFF
++
++#ifdef PROP_TXSTATUS
++/* Bit definitions for tlv iovar */
++/*
++ * enable RSSI signals:
++ * WLFC_CTL_TYPE_RSSI
++ */
++#define WLFC_FLAGS_RSSI_SIGNALS			0x0001
++
++/* enable (if/mac_open, if/mac_close,, mac_add, mac_del) signals:
++ *
++ * WLFC_CTL_TYPE_MAC_OPEN
++ * WLFC_CTL_TYPE_MAC_CLOSE
++ *
++ * WLFC_CTL_TYPE_INTERFACE_OPEN
++ * WLFC_CTL_TYPE_INTERFACE_CLOSE
++ *
++ * WLFC_CTL_TYPE_MACDESC_ADD
++ * WLFC_CTL_TYPE_MACDESC_DEL
++ *
++ */
++#define WLFC_FLAGS_XONXOFF_SIGNALS		0x0002
++
++/* enable (status, fifo_credit, mac_credit) signals
++ * WLFC_CTL_TYPE_MAC_REQUEST_CREDIT
++ * WLFC_CTL_TYPE_TXSTATUS
++ * WLFC_CTL_TYPE_FIFO_CREDITBACK
++ */
++#define WLFC_FLAGS_CREDIT_STATUS_SIGNALS	0x0004
++
++#define WLFC_FLAGS_HOST_PROPTXSTATUS_ACTIVE	0x0008
++#define WLFC_FLAGS_PSQ_GENERATIONFSM_ENABLE	0x0010
++#define WLFC_FLAGS_PSQ_ZERO_BUFFER_ENABLE	0x0020
++#define WLFC_FLAGS_HOST_RXRERODER_ACTIVE	0x0040
++#define WLFC_FLAGS_PKT_STAMP_SIGNALS		0x0080
++
++#endif /* PROP_TXSTATUS */
++
++#define WL_TIMBC_STATUS_AP_UNKNOWN	255	/* AP status for internal use only */
++
++#define WL_DFRTS_LOGIC_OFF	0	/* Feature is disabled */
++#define WL_DFRTS_LOGIC_OR	1	/* OR all non-zero threshold conditions */
++#define WL_DFRTS_LOGIC_AND	2	/* AND all non-zero threshold conditions */
++
++/* Definitions for Reliable Multicast */
++#define WL_RELMCAST_MAX_CLIENT		32
++#define WL_RELMCAST_FLAG_INBLACKLIST	1
++#define WL_RELMCAST_FLAG_ACTIVEACKER	2
++#define WL_RELMCAST_FLAG_RELMCAST	4
++
++/* structures for proximity detection device role */
++#define WL_PROXD_MODE_DISABLE	0
++#define WL_PROXD_MODE_NEUTRAL	1
++#define WL_PROXD_MODE_INITIATOR	2
++#define WL_PROXD_MODE_TARGET	3
++#define WL_PROXD_RANDOM_WAKEUP	0x8000
++
++
++#ifdef NET_DETECT
++#define NET_DETECT_MAX_WAKE_DATA_SIZE	2048
++#define NET_DETECT_MAX_PROFILES		16
++#define NET_DETECT_MAX_CHANNELS		50
++#endif /* NET_DETECT */
++
++
++/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
++#define WL_RADIO_SW_DISABLE		(1<<0)
++#define WL_RADIO_HW_DISABLE		(1<<1)
++#define WL_RADIO_MPC_DISABLE		(1<<2)
++#define WL_RADIO_COUNTRY_DISABLE	(1<<3)	/* some countries don't support any channel */
++#define WL_RADIO_PERCORE_DISABLE	(1<<4)	/* Radio diable per core for DVT */
++
++#define	WL_SPURAVOID_OFF	0
++#define	WL_SPURAVOID_ON1	1
++#define	WL_SPURAVOID_ON2	2
++
++
++#define WL_4335_SPURAVOID_ON1	1
++#define WL_4335_SPURAVOID_ON2	2
++#define WL_4335_SPURAVOID_ON3	3
++#define WL_4335_SPURAVOID_ON4	4
++#define WL_4335_SPURAVOID_ON5	5
++#define WL_4335_SPURAVOID_ON6	6
++#define WL_4335_SPURAVOID_ON7	7
++#define WL_4335_SPURAVOID_ON8	8
++#define WL_4335_SPURAVOID_ON9	9
++
++/* Override bit for WLC_SET_TXPWR.  if set, ignore other level limits */
++#define WL_TXPWR_OVERRIDE	(1U<<31)
++#define WL_TXPWR_2G		(1U<<30)
++#define WL_TXPWR_5G		(1U<<29)
++#define WL_TXPWR_NEG   (1U<<28)
++
++#define WL_TXPWR_MASK		(~(0x7<<29))
++#define WL_TXPWR_CORE_MAX	(3)
++#define WL_TXPWR_CORE0_MASK	(0x000000FF)
++#define WL_TXPWR_CORE0_SHIFT	(0)
++#define WL_TXPWR_CORE1_MASK	(0x0000FF00)
++#define WL_TXPWR_CORE1_SHIFT	(8)
++#define WL_TXPWR_CORE2_MASK	(0x00FF0000)
++#define WL_TXPWR_CORE2_SHIFT	(16)
++
++/* phy types (returned by WLC_GET_PHYTPE) */
++#define	WLC_PHY_TYPE_A		0
++#define	WLC_PHY_TYPE_B		1
++#define	WLC_PHY_TYPE_G		2
++#define	WLC_PHY_TYPE_N		4
++#define	WLC_PHY_TYPE_LP		5
++#define	WLC_PHY_TYPE_SSN	6
++#define	WLC_PHY_TYPE_HT		7
++#define	WLC_PHY_TYPE_LCN	8
++#define	WLC_PHY_TYPE_LCN40	10
++#define WLC_PHY_TYPE_AC		11
++#define	WLC_PHY_TYPE_LCN20	12
++#define	WLC_PHY_TYPE_NULL	0xf
++
++/* Values for PM */
++#define PM_OFF	0
++#define PM_MAX	1
++#define PM_FAST 2
++#define PM_FORCE_OFF 3		/* use this bit to force PM off even bt is active */
++
++#define WL_WME_CNT_VERSION	1	/* current version of wl_wme_cnt_t */
++
++/* fbt_cap: FBT assoc / reassoc modes. */
++#define WLC_FBT_CAP_DRV_4WAY_AND_REASSOC  1 /* Driver 4-way handshake & reassoc (WLFBT). */
++
++/* monitor_promisc_level bits */
++#define WL_MONPROMISC_PROMISC 0x0001
++#define WL_MONPROMISC_CTRL 0x0002
++#define WL_MONPROMISC_FCS 0x0004
++
++/* TCP Checksum Offload defines */
++#define TOE_TX_CSUM_OL		0x00000001
++#define TOE_RX_CSUM_OL		0x00000002
++
++/* Wi-Fi Display Services (WFDS) */
++#define WL_P2P_SOCIAL_CHANNELS_MAX  WL_NUMCHANNELS
++#define MAX_WFDS_SEEK_SVC 4	/* Max # of wfds services to seek */
++#define MAX_WFDS_ADVERT_SVC 4	/* Max # of wfds services to advertise */
++#define MAX_WFDS_SVC_NAME_LEN 200	/* maximum service_name length */
++#define MAX_WFDS_ADV_SVC_INFO_LEN 65000	/* maximum adv service_info length */
++#define P2P_WFDS_HASH_LEN 6		/* Length of a WFDS service hash */
++#define MAX_WFDS_SEEK_SVC_INFO_LEN 255	/* maximum seek service_info req length */
++#define MAX_WFDS_SEEK_SVC_NAME_LEN 200	/* maximum service_name length */
++
++/* ap_isolate bitmaps */
++#define AP_ISOLATE_DISABLED		0x0
++#define AP_ISOLATE_SENDUP_ALL		0x01
++#define AP_ISOLATE_SENDUP_MCAST		0x02
++
++/* Type values for the wl_pwrstats_t data field */
++#define WL_PWRSTATS_TYPE_PHY		0 /**< struct wl_pwr_phy_stats */
++#define WL_PWRSTATS_TYPE_SCAN		1 /**< struct wl_pwr_scan_stats */
++#define WL_PWRSTATS_TYPE_USB_HSIC	2 /**< struct wl_pwr_usb_hsic_stats */
++#define WL_PWRSTATS_TYPE_PM_AWAKE1	3 /**< struct wl_pwr_pm_awake_stats_v1 */
++#define WL_PWRSTATS_TYPE_CONNECTION	4 /* struct wl_pwr_connect_stats; assoc and key-exch time */
++#define WL_PWRSTATS_TYPE_PCIE		6 /**< struct wl_pwr_pcie_stats */
++#define WL_PWRSTATS_TYPE_PM_AWAKE2	7 /**< struct wl_pwr_pm_awake_stats_v2 */
++#define WL_PWRSTATS_TYPE_SDIO		8 /* struct wl_pwr_sdio_stats */
++#define WL_PWRSTATS_TYPE_MIMO_PS_METRICS 9 /* struct wl_mimo_meas_metrics_t */
++
++#endif /* wlioctl_defs_h */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/wlioctl_utils.h b/module_drivers/drivers/net/wireless/bcmdhd/include/wlioctl_utils.h
+new file mode 100644
+index 000000000..797531cfa
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/wlioctl_utils.h
+@@ -0,0 +1,61 @@
++/*
++ * Custom OID/ioctl related helper functions.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wlioctl_utils.h 614820 2016-01-23 17:16:17Z $
++ */
++
++#ifndef _wlioctl_utils_h_
++#define _wlioctl_utils_h_
++
++#include <wlioctl.h>
++
++#ifndef BCMDRIVER
++#define CCA_THRESH_MILLI	14
++#define CCA_THRESH_INTERFERE	6
++
++extern cca_congest_channel_req_t * cca_per_chan_summary(cca_congest_channel_req_t *input,
++	cca_congest_channel_req_t *avg, bool percent);
++
++extern int cca_analyze(cca_congest_channel_req_t *input[], int num_chans,
++	uint flags, chanspec_t *answer);
++#endif /* BCMDRIVER */
++
++extern int wl_cntbuf_to_xtlv_format(void *ctx, void *cntbuf,
++	int buflen, uint32 corerev);
++
++extern const char * wl_get_reinit_rc_name(int rc);
++
++/* Get data pointer of wlc layer counters tuple from xtlv formatted counters IOVar buffer. */
++#define GET_WLCCNT_FROM_CNTBUF(cntbuf)						\
++		bcm_get_data_from_xtlv_buf(((wl_cnt_info_t *)cntbuf)->data,	\
++		((wl_cnt_info_t *)cntbuf)->datalen, WL_CNT_XTLV_WLC,		\
++		NULL, BCM_XTLV_OPTION_ALIGN32)
++
++#define CHK_CNTBUF_DATALEN(cntbuf, ioctl_buflen) do {					\
++	if (((wl_cnt_info_t *)cntbuf)->datalen +			\
++		OFFSETOF(wl_cnt_info_t, data) > ioctl_buflen)	\
++		printf("%s: IOVAR buffer short!\n", __FUNCTION__);	\
++} while (0)
++
++#endif /* _wlioctl_utils_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/wpa.h b/module_drivers/drivers/net/wireless/bcmdhd/include/wpa.h
+new file mode 100644
+index 000000000..fbb9c29e6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/wpa.h
+@@ -0,0 +1,217 @@
++/*
++ * Fundamental types and constants relating to WPA
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wpa.h 700076 2017-05-17 14:42:22Z $
++ */
++
++#ifndef _proto_wpa_h_
++#define _proto_wpa_h_
++
++#include <typedefs.h>
++#include <ethernet.h>
++
++
++/* This marks the start of a packed structure section. */
++#include <packed_section_start.h>
++
++/* Reason Codes */
++
++/* 13 through 23 taken from IEEE Std 802.11i-2004 */
++#define DOT11_RC_INVALID_WPA_IE		13	/* Invalid info. element */
++#define DOT11_RC_MIC_FAILURE		14	/* Michael failure */
++#define DOT11_RC_4WH_TIMEOUT		15	/* 4-way handshake timeout */
++#define DOT11_RC_GTK_UPDATE_TIMEOUT	16	/* Group key update timeout */
++#define DOT11_RC_WPA_IE_MISMATCH	17	/* WPA IE in 4-way handshake differs from
++						 * (re-)assoc. request/probe response
++						 */
++#define DOT11_RC_INVALID_MC_CIPHER	18	/* Invalid multicast cipher */
++#define DOT11_RC_INVALID_UC_CIPHER	19	/* Invalid unicast cipher */
++#define DOT11_RC_INVALID_AKMP		20	/* Invalid authenticated key management protocol */
++#define DOT11_RC_BAD_WPA_VERSION	21	/* Unsupported WPA version */
++#define DOT11_RC_INVALID_WPA_CAP	22	/* Invalid WPA IE capabilities */
++#define DOT11_RC_8021X_AUTH_FAIL	23	/* 802.1X authentication failure */
++
++#define WPA2_PMKID_LEN	16
++
++/* WPA IE fixed portion */
++typedef BWL_PRE_PACKED_STRUCT struct
++{
++	uint8 tag;	/* TAG */
++	uint8 length;	/* TAG length */
++	uint8 oui[3];	/* IE OUI */
++	uint8 oui_type;	/* OUI type */
++	BWL_PRE_PACKED_STRUCT struct {
++		uint8 low;
++		uint8 high;
++	} BWL_POST_PACKED_STRUCT version;	/* IE version */
++} BWL_POST_PACKED_STRUCT wpa_ie_fixed_t;
++#define WPA_IE_OUITYPE_LEN	4
++#define WPA_IE_FIXED_LEN	8
++#define WPA_IE_TAG_FIXED_LEN	6
++
++#define BIP_OUI_TYPE WPA2_OUI "\x06"
++
++typedef BWL_PRE_PACKED_STRUCT struct {
++	uint8 tag;	/* TAG */
++	uint8 length;	/* TAG length */
++	BWL_PRE_PACKED_STRUCT struct {
++		uint8 low;
++		uint8 high;
++	} BWL_POST_PACKED_STRUCT version;	/* IE version */
++} BWL_POST_PACKED_STRUCT wpa_rsn_ie_fixed_t;
++#define WPA_RSN_IE_FIXED_LEN	4
++#define WPA_RSN_IE_TAG_FIXED_LEN	2
++typedef uint8 wpa_pmkid_t[WPA2_PMKID_LEN];
++
++#define WFA_OSEN_IE_FIXED_LEN	6
++
++/* WPA suite/multicast suite */
++typedef BWL_PRE_PACKED_STRUCT struct
++{
++	uint8 oui[3];
++	uint8 type;
++} BWL_POST_PACKED_STRUCT wpa_suite_t, wpa_suite_mcast_t;
++#define WPA_SUITE_LEN	4
++
++/* WPA unicast suite list/key management suite list */
++typedef BWL_PRE_PACKED_STRUCT struct
++{
++	BWL_PRE_PACKED_STRUCT struct {
++		uint8 low;
++		uint8 high;
++	} BWL_POST_PACKED_STRUCT count;
++	wpa_suite_t list[1];
++} BWL_POST_PACKED_STRUCT wpa_suite_ucast_t, wpa_suite_auth_key_mgmt_t;
++#define WPA_IE_SUITE_COUNT_LEN	2
++typedef BWL_PRE_PACKED_STRUCT struct
++{
++	BWL_PRE_PACKED_STRUCT struct {
++		uint8 low;
++		uint8 high;
++	} BWL_POST_PACKED_STRUCT count;
++	wpa_pmkid_t list[1];
++} BWL_POST_PACKED_STRUCT wpa_pmkid_list_t;
++
++/* WPA cipher suites */
++#define WPA_CIPHER_NONE		0	/* None */
++#define WPA_CIPHER_WEP_40	1	/* WEP (40-bit) */
++#define WPA_CIPHER_TKIP		2	/* TKIP: default for WPA */
++#define WPA_CIPHER_AES_OCB	3	/* AES (OCB) */
++#define WPA_CIPHER_AES_CCM	4	/* AES (CCM) */
++#define WPA_CIPHER_WEP_104	5	/* WEP (104-bit) */
++#define WPA_CIPHER_BIP		6	/* WEP (104-bit) */
++#define WPA_CIPHER_TPK		7	/* Group addressed traffic not allowed */
++
++#define WPA_CIPHER_AES_GCM	8	/* AES (GCM) */
++#define WPA_CIPHER_AES_GCM256	9	/* AES (GCM256) */
++
++#ifdef BCMWAPI_WAI
++#define WAPI_CIPHER_NONE	WPA_CIPHER_NONE
++#define WAPI_CIPHER_SMS4	11
++
++#define WAPI_CSE_WPI_SMS4	1
++#endif /* BCMWAPI_WAI */
++
++#define IS_WPA_CIPHER(cipher)	((cipher) == WPA_CIPHER_NONE || \
++				 (cipher) == WPA_CIPHER_WEP_40 || \
++				 (cipher) == WPA_CIPHER_WEP_104 || \
++				 (cipher) == WPA_CIPHER_TKIP || \
++				 (cipher) == WPA_CIPHER_AES_OCB || \
++				 (cipher) == WPA_CIPHER_AES_CCM || \
++				 (cipher) == WPA_CIPHER_AES_GCM || \
++				 (cipher) == WPA_CIPHER_AES_GCM256 || \
++				 (cipher) == WPA_CIPHER_TPK)
++
++#ifdef BCMWAPI_WAI
++#define IS_WAPI_CIPHER(cipher)	((cipher) == WAPI_CIPHER_NONE || \
++				 (cipher) == WAPI_CSE_WPI_SMS4)
++
++/* convert WAPI_CSE_WPI_XXX to WAPI_CIPHER_XXX */
++#define WAPI_CSE_WPI_2_CIPHER(cse) ((cse) == WAPI_CSE_WPI_SMS4 ? \
++				WAPI_CIPHER_SMS4 : WAPI_CIPHER_NONE)
++
++#define WAPI_CIPHER_2_CSE_WPI(cipher) ((cipher) == WAPI_CIPHER_SMS4 ? \
++				WAPI_CSE_WPI_SMS4 : WAPI_CIPHER_NONE)
++#endif /* BCMWAPI_WAI */
++
++/* WPA TKIP countermeasures parameters */
++#define WPA_TKIP_CM_DETECT	60	/* multiple MIC failure window (seconds) */
++#define WPA_TKIP_CM_BLOCK	60	/* countermeasures active window (seconds) */
++
++/* RSN IE defines */
++#define RSN_CAP_LEN		2	/* Length of RSN capabilities field (2 octets) */
++
++/* RSN Capabilities defined in 802.11i */
++#define RSN_CAP_PREAUTH			0x0001
++#define RSN_CAP_NOPAIRWISE		0x0002
++#define RSN_CAP_PTK_REPLAY_CNTR_MASK	0x000C
++#define RSN_CAP_PTK_REPLAY_CNTR_SHIFT	2
++#define RSN_CAP_GTK_REPLAY_CNTR_MASK	0x0030
++#define RSN_CAP_GTK_REPLAY_CNTR_SHIFT	4
++#define RSN_CAP_1_REPLAY_CNTR		0
++#define RSN_CAP_2_REPLAY_CNTRS		1
++#define RSN_CAP_4_REPLAY_CNTRS		2
++#define RSN_CAP_16_REPLAY_CNTRS		3
++#define RSN_CAP_MFPR			0x0040
++#define RSN_CAP_MFPC			0x0080
++#define RSN_CAP_SPPC			0x0400
++#define RSN_CAP_SPPR			0x0800
++
++/* WPA capabilities defined in 802.11i */
++#define WPA_CAP_4_REPLAY_CNTRS		RSN_CAP_4_REPLAY_CNTRS
++#define WPA_CAP_16_REPLAY_CNTRS		RSN_CAP_16_REPLAY_CNTRS
++#define WPA_CAP_REPLAY_CNTR_SHIFT	RSN_CAP_PTK_REPLAY_CNTR_SHIFT
++#define WPA_CAP_REPLAY_CNTR_MASK	RSN_CAP_PTK_REPLAY_CNTR_MASK
++
++/* WPA capabilities defined in 802.11zD9.0 */
++#define WPA_CAP_PEER_KEY_ENABLE		(0x1 << 1)	/* bit 9 */
++
++/* WPA Specific defines */
++#define WPA_CAP_LEN	RSN_CAP_LEN	/* Length of RSN capabilities in RSN IE (2 octets) */
++#define WPA_PMKID_CNT_LEN	2 	/* Length of RSN PMKID count (2 octests) */
++
++#define	WPA_CAP_WPA2_PREAUTH		RSN_CAP_PREAUTH
++
++#define WPA2_PMKID_COUNT_LEN	2
++
++#ifdef BCMWAPI_WAI
++#define WAPI_CAP_PREAUTH		RSN_CAP_PREAUTH
++
++/* Other WAI definition */
++#define WAPI_WAI_REQUEST		0x00F1
++#define WAPI_UNICAST_REKEY		0x00F2
++#define WAPI_STA_AGING			0x00F3
++#define WAPI_MUTIL_REKEY		0x00F4
++#define WAPI_STA_STATS			0x00F5
++
++#define WAPI_USK_REKEY_COUNT		0x4000000 /* 0xA00000 */
++#define WAPI_MSK_REKEY_COUNT		0x4000000 /* 0xA00000 */
++#endif /* BCMWAPI_WAI */
++
++/* This marks the end of a packed structure section. */
++#include <packed_section_end.h>
++
++#endif /* _proto_wpa_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/include/wps.h b/module_drivers/drivers/net/wireless/bcmdhd/include/wps.h
+new file mode 100644
+index 000000000..aa4cc1b9f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/include/wps.h
+@@ -0,0 +1,389 @@
++/*
++ * WPS IE definitions
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id$
++ */
++
++#ifndef _WPS_
++#define _WPS_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* Data Element Definitions */
++#define WPS_ID_AP_CHANNEL         0x1001
++#define WPS_ID_ASSOC_STATE        0x1002
++#define WPS_ID_AUTH_TYPE          0x1003
++#define WPS_ID_AUTH_TYPE_FLAGS    0x1004
++#define WPS_ID_AUTHENTICATOR      0x1005
++#define WPS_ID_CONFIG_METHODS     0x1008
++#define WPS_ID_CONFIG_ERROR       0x1009
++#define WPS_ID_CONF_URL4          0x100A
++#define WPS_ID_CONF_URL6          0x100B
++#define WPS_ID_CONN_TYPE          0x100C
++#define WPS_ID_CONN_TYPE_FLAGS    0x100D
++#define WPS_ID_CREDENTIAL         0x100E
++#define WPS_ID_DEVICE_NAME        0x1011
++#define WPS_ID_DEVICE_PWD_ID      0x1012
++#define WPS_ID_E_HASH1            0x1014
++#define WPS_ID_E_HASH2            0x1015
++#define WPS_ID_E_SNONCE1          0x1016
++#define WPS_ID_E_SNONCE2          0x1017
++#define WPS_ID_ENCR_SETTINGS      0x1018
++#define WPS_ID_ENCR_TYPE          0x100F
++#define WPS_ID_ENCR_TYPE_FLAGS    0x1010
++#define WPS_ID_ENROLLEE_NONCE     0x101A
++#define WPS_ID_FEATURE_ID         0x101B
++#define WPS_ID_IDENTITY           0x101C
++#define WPS_ID_IDENTITY_PROOF     0x101D
++#define WPS_ID_KEY_WRAP_AUTH      0x101E
++#define WPS_ID_KEY_IDENTIFIER     0x101F
++#define WPS_ID_MAC_ADDR           0x1020
++#define WPS_ID_MANUFACTURER       0x1021
++#define WPS_ID_MSG_TYPE           0x1022
++#define WPS_ID_MODEL_NAME         0x1023
++#define WPS_ID_MODEL_NUMBER       0x1024
++#define WPS_ID_NW_INDEX           0x1026
++#define WPS_ID_NW_KEY             0x1027
++#define WPS_ID_NW_KEY_INDEX       0x1028
++#define WPS_ID_NEW_DEVICE_NAME    0x1029
++#define WPS_ID_NEW_PWD            0x102A
++#define WPS_ID_OOB_DEV_PWD        0x102C
++#define WPS_ID_OS_VERSION         0x102D
++#define WPS_ID_POWER_LEVEL        0x102F
++#define WPS_ID_PSK_CURRENT        0x1030
++#define WPS_ID_PSK_MAX            0x1031
++#define WPS_ID_PUBLIC_KEY         0x1032
++#define WPS_ID_RADIO_ENABLED      0x1033
++#define WPS_ID_REBOOT             0x1034
++#define WPS_ID_REGISTRAR_CURRENT  0x1035
++#define WPS_ID_REGISTRAR_ESTBLSHD 0x1036
++#define WPS_ID_REGISTRAR_LIST     0x1037
++#define WPS_ID_REGISTRAR_MAX      0x1038
++#define WPS_ID_REGISTRAR_NONCE    0x1039
++#define WPS_ID_REQ_TYPE           0x103A
++#define WPS_ID_RESP_TYPE          0x103B
++#define WPS_ID_RF_BAND            0x103C
++#define WPS_ID_R_HASH1            0x103D
++#define WPS_ID_R_HASH2            0x103E
++#define WPS_ID_R_SNONCE1          0x103F
++#define WPS_ID_R_SNONCE2          0x1040
++#define WPS_ID_SEL_REGISTRAR      0x1041
++#define WPS_ID_SERIAL_NUM         0x1042
++#define WPS_ID_SC_STATE           0x1044
++#define WPS_ID_SSID               0x1045
++#define WPS_ID_TOT_NETWORKS       0x1046
++#define WPS_ID_UUID_E             0x1047
++#define WPS_ID_UUID_R             0x1048
++#define WPS_ID_VENDOR_EXT         0x1049
++#define WPS_ID_VERSION            0x104A
++#define WPS_ID_X509_CERT_REQ      0x104B
++#define WPS_ID_X509_CERT          0x104C
++#define WPS_ID_EAP_IDENTITY       0x104D
++#define WPS_ID_MSG_COUNTER        0x104E
++#define WPS_ID_PUBKEY_HASH        0x104F
++#define WPS_ID_REKEY_KEY          0x1050
++#define WPS_ID_KEY_LIFETIME       0x1051
++#define WPS_ID_PERM_CFG_METHODS   0x1052
++#define WPS_ID_SEL_REG_CFG_METHODS 0x1053
++#define WPS_ID_PRIM_DEV_TYPE      0x1054
++#define WPS_ID_SEC_DEV_TYPE_LIST  0x1055
++#define WPS_ID_PORTABLE_DEVICE    0x1056
++#define WPS_ID_AP_SETUP_LOCKED    0x1057
++#define WPS_ID_APP_LIST           0x1058
++#define WPS_ID_EAP_TYPE           0x1059
++#define WPS_ID_INIT_VECTOR        0x1060
++#define WPS_ID_KEY_PROVIDED_AUTO  0x1061
++#define WPS_ID_8021X_ENABLED      0x1062
++#define WPS_ID_WEP_TRANSMIT_KEY   0x1064
++#define WPS_ID_REQ_DEV_TYPE       0x106A
++
++/* WSC 2.0, WFA Vendor Extension Subelements */
++#define WFA_VENDOR_EXT_ID                 "\x00\x37\x2A"
++#define WPS_WFA_SUBID_VERSION2            0x00
++#define WPS_WFA_SUBID_AUTHORIZED_MACS     0x01
++#define WPS_WFA_SUBID_NW_KEY_SHAREABLE    0x02
++#define WPS_WFA_SUBID_REQ_TO_ENROLL       0x03
++#define WPS_WFA_SUBID_SETTINGS_DELAY_TIME 0x04
++#define WPS_WFA_SUBID_REG_CFG_METHODS     0x05
++
++
++/* WCN-NET Windows Rally Vertical Pairing Vendor Extensions */
++#define MS_VENDOR_EXT_ID           "\x00\x01\x37"
++#define WPS_MS_ID_VPI               0x1001	/* Vertical Pairing Identifier TLV */
++#define WPS_MS_ID_TRANSPORT_UUID    0x1002      /* Transport UUID TLV */
++
++/* Vertical Pairing Identifier TLV Definitions */
++#define WPS_MS_VPI_TRANSPORT_NONE   0x00        /* None */
++#define WPS_MS_VPI_TRANSPORT_DPWS   0x01        /* Devices Profile for Web Services */
++#define WPS_MS_VPI_TRANSPORT_UPNP   0x02        /* uPnP */
++#define WPS_MS_VPI_TRANSPORT_SDNWS  0x03        /* Secure Devices Profile for Web Services */
++#define WPS_MS_VPI_NO_PROFILE_REQ   0x00        /* Wi-Fi profile not requested.
++						 * Not supported in Windows 7
++						 */
++#define WPS_MS_VPI_PROFILE_REQ      0x01        /* Wi-Fi profile requested.  */
++
++/* sizes of the fixed size elements */
++#define WPS_ID_AP_CHANNEL_S       2
++#define WPS_ID_ASSOC_STATE_S      2
++#define WPS_ID_AUTH_TYPE_S        2
++#define WPS_ID_AUTH_TYPE_FLAGS_S  2
++#define WPS_ID_AUTHENTICATOR_S    8
++#define WPS_ID_CONFIG_METHODS_S   2
++#define WPS_ID_CONFIG_ERROR_S     2
++#define WPS_ID_CONN_TYPE_S          1
++#define WPS_ID_CONN_TYPE_FLAGS_S    1
++#define WPS_ID_DEVICE_PWD_ID_S      2
++#define WPS_ID_ENCR_TYPE_S          2
++#define WPS_ID_ENCR_TYPE_FLAGS_S    2
++#define WPS_ID_FEATURE_ID_S         4
++#define WPS_ID_MAC_ADDR_S           6
++#define WPS_ID_MSG_TYPE_S           1
++#define WPS_ID_SC_STATE_S           1
++#define WPS_ID_RF_BAND_S            1
++#define WPS_ID_OS_VERSION_S         4
++#define WPS_ID_VERSION_S            1
++#define WPS_ID_SEL_REGISTRAR_S      1
++#define WPS_ID_SEL_REG_CFG_METHODS_S 2
++#define WPS_ID_REQ_TYPE_S           1
++#define WPS_ID_RESP_TYPE_S          1
++#define WPS_ID_AP_SETUP_LOCKED_S    1
++
++/* WSC 2.0, WFA Vendor Extension Subelements */
++#define WPS_WFA_SUBID_VERSION2_S            1
++#define WPS_WFA_SUBID_NW_KEY_SHAREABLE_S    1
++#define WPS_WFA_SUBID_REQ_TO_ENROLL_S       1
++#define WPS_WFA_SUBID_SETTINGS_DELAY_TIME_S 1
++#define WPS_WFA_SUBID_REG_CFG_METHODS_S     2
++
++/* Association states */
++#define WPS_ASSOC_NOT_ASSOCIATED  0
++#define WPS_ASSOC_CONN_SUCCESS    1
++#define WPS_ASSOC_CONFIG_FAIL     2
++#define WPS_ASSOC_ASSOC_FAIL      3
++#define WPS_ASSOC_IP_FAIL         4
++
++/* Authentication types */
++#define WPS_AUTHTYPE_OPEN        0x0001
++#define WPS_AUTHTYPE_WPAPSK      0x0002	/* Deprecated in WSC 2.0 */
++#define WPS_AUTHTYPE_SHARED      0x0004	/* Deprecated in WSC 2.0 */
++#define WPS_AUTHTYPE_WPA         0x0008	/* Deprecated in WSC 2.0 */
++#define WPS_AUTHTYPE_WPA2        0x0010
++#define WPS_AUTHTYPE_WPA2PSK     0x0020
++
++/* Config methods */
++#define WPS_CONFMET_USBA            0x0001	/* Deprecated in WSC 2.0 */
++#define WPS_CONFMET_ETHERNET        0x0002	/* Deprecated in WSC 2.0 */
++#define WPS_CONFMET_LABEL           0x0004
++#define WPS_CONFMET_DISPLAY         0x0008
++#define WPS_CONFMET_EXT_NFC_TOK     0x0010
++#define WPS_CONFMET_INT_NFC_TOK     0x0020
++#define WPS_CONFMET_NFC_INTF        0x0040
++#define WPS_CONFMET_PBC             0x0080
++#define WPS_CONFMET_KEYPAD          0x0100
++/* WSC 2.0 */
++#define WPS_CONFMET_VIRT_PBC        0x0280
++#define WPS_CONFMET_PHY_PBC         0x0480
++#define WPS_CONFMET_VIRT_DISPLAY    0x2008
++#define WPS_CONFMET_PHY_DISPLAY     0x4008
++
++/* WPS error messages */
++#define WPS_ERROR_NO_ERROR                0
++#define WPS_ERROR_OOB_INT_READ_ERR        1
++#define WPS_ERROR_DECRYPT_CRC_FAIL        2
++#define WPS_ERROR_CHAN24_NOT_SUPP         3
++#define WPS_ERROR_CHAN50_NOT_SUPP         4
++#define WPS_ERROR_SIGNAL_WEAK             5	/* Deprecated in WSC 2.0 */
++#define WPS_ERROR_NW_AUTH_FAIL            6	/* Deprecated in WSC 2.0 */
++#define WPS_ERROR_NW_ASSOC_FAIL           7	/* Deprecated in WSC 2.0 */
++#define WPS_ERROR_NO_DHCP_RESP            8	/* Deprecated in WSC 2.0 */
++#define WPS_ERROR_FAILED_DHCP_CONF        9	/* Deprecated in WSC 2.0 */
++#define WPS_ERROR_IP_ADDR_CONFLICT        10	/* Deprecated in WSC 2.0 */
++#define WPS_ERROR_FAIL_CONN_REGISTRAR     11
++#define WPS_ERROR_MULTI_PBC_DETECTED      12
++#define WPS_ERROR_ROGUE_SUSPECTED         13
++#define WPS_ERROR_DEVICE_BUSY             14
++#define WPS_ERROR_SETUP_LOCKED            15
++#define WPS_ERROR_MSG_TIMEOUT             16	/* Deprecated in WSC 2.0 */
++#define WPS_ERROR_REG_SESSION_TIMEOUT     17	/* Deprecated in WSC 2.0 */
++#define WPS_ERROR_DEV_PWD_AUTH_FAIL       18
++#define WPS_ERROR_60GHZ_NOT_SUPPORT       19
++#define WPS_ERROR_PKH_MISMATCH            20	/* Public Key Hash Mismatch */
++
++/* Connection types */
++#define WPS_CONNTYPE_ESS    0x01
++#define WPS_CONNTYPE_IBSS   0x02
++
++/* Device password ID */
++#define WPS_DEVICEPWDID_DEFAULT          0x0000
++#define WPS_DEVICEPWDID_USER_SPEC        0x0001
++#define WPS_DEVICEPWDID_MACHINE_SPEC     0x0002
++#define WPS_DEVICEPWDID_REKEY            0x0003
++#define WPS_DEVICEPWDID_PUSH_BTN         0x0004
++#define WPS_DEVICEPWDID_REG_SPEC         0x0005
++#define WPS_DEVICEPWDID_IBSS             0x0006
++#define WPS_DEVICEPWDID_NFC_CHO          0x0007	/* NFC-Connection-Handover */
++#define WPS_DEVICEPWDID_WFDS             0x0008	/* Wi-Fi Direct Services Specification */
++
++/* Encryption type */
++#define WPS_ENCRTYPE_NONE    0x0001
++#define WPS_ENCRTYPE_WEP     0x0002	/* Deprecated in WSC 2.0 */
++#define WPS_ENCRTYPE_TKIP    0x0004	/* Deprecated in version 2.0. TKIP can only
++					  * be advertised on the AP when Mixed Mode
++					  * is enabled (Encryption Type is 0x000c).
++					  */
++#define WPS_ENCRTYPE_AES     0x0008
++
++
++/* WPS Message Types */
++#define WPS_ID_BEACON            0x01
++#define WPS_ID_PROBE_REQ         0x02
++#define WPS_ID_PROBE_RESP        0x03
++#define WPS_ID_MESSAGE_M1        0x04
++#define WPS_ID_MESSAGE_M2        0x05
++#define WPS_ID_MESSAGE_M2D       0x06
++#define WPS_ID_MESSAGE_M3        0x07
++#define WPS_ID_MESSAGE_M4        0x08
++#define WPS_ID_MESSAGE_M5        0x09
++#define WPS_ID_MESSAGE_M6        0x0A
++#define WPS_ID_MESSAGE_M7        0x0B
++#define WPS_ID_MESSAGE_M8        0x0C
++#define WPS_ID_MESSAGE_ACK       0x0D
++#define WPS_ID_MESSAGE_NACK      0x0E
++#define WPS_ID_MESSAGE_DONE      0x0F
++
++/* WSP private ID for local use */
++#define WPS_PRIVATE_ID_IDENTITY		(WPS_ID_MESSAGE_DONE + 1)
++#define WPS_PRIVATE_ID_WPS_START	(WPS_ID_MESSAGE_DONE + 2)
++#define WPS_PRIVATE_ID_FAILURE		(WPS_ID_MESSAGE_DONE + 3)
++#define WPS_PRIVATE_ID_FRAG		(WPS_ID_MESSAGE_DONE + 4)
++#define WPS_PRIVATE_ID_FRAG_ACK		(WPS_ID_MESSAGE_DONE + 5)
++#define WPS_PRIVATE_ID_EAPOL_START	(WPS_ID_MESSAGE_DONE + 6)
++
++
++/* Device Type categories for primary and secondary device types */
++#define WPS_DEVICE_TYPE_CAT_COMPUTER        1
++#define WPS_DEVICE_TYPE_CAT_INPUT_DEVICE    2
++#define WPS_DEVICE_TYPE_CAT_PRINTER         3
++#define WPS_DEVICE_TYPE_CAT_CAMERA          4
++#define WPS_DEVICE_TYPE_CAT_STORAGE         5
++#define WPS_DEVICE_TYPE_CAT_NW_INFRA        6
++#define WPS_DEVICE_TYPE_CAT_DISPLAYS        7
++#define WPS_DEVICE_TYPE_CAT_MM_DEVICES      8
++#define WPS_DEVICE_TYPE_CAT_GAME_DEVICES    9
++#define WPS_DEVICE_TYPE_CAT_TELEPHONE       10
++#define WPS_DEVICE_TYPE_CAT_AUDIO_DEVICES   11	/* WSC 2.0 */
++
++/* Device Type sub categories for primary and secondary device types */
++#define WPS_DEVICE_TYPE_SUB_CAT_COMP_PC         1
++#define WPS_DEVICE_TYPE_SUB_CAT_COMP_SERVER     2
++#define WPS_DEVICE_TYPE_SUB_CAT_COMP_MEDIA_CTR  3
++#define WPS_DEVICE_TYPE_SUB_CAT_COMP_UM_PC      4	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_COMP_NOTEBOOK   5	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_COMP_DESKTOP    6	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_COMP_MID        7	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_COMP_NETBOOK    8	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_INP_Keyboard    1	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_INP_MOUSE       2	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_INP_JOYSTICK    3	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_INP_TRACKBALL   4	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_INP_GAM_CTRL    5	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_INP_REMOTE      6	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_INP_TOUCHSCREEN 7	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_INP_BIO_READER  8	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_INP_BAR_READER  9	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_PRTR_PRINTER    1
++#define WPS_DEVICE_TYPE_SUB_CAT_PRTR_SCANNER    2
++#define WPS_DEVICE_TYPE_SUB_CAT_PRTR_FAX        3	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_PRTR_COPIER     4	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_PRTR_ALLINONE   5	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_CAM_DGTL_STILL  1
++#define WPS_DEVICE_TYPE_SUB_CAT_CAM_VIDEO_CAM   2	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_CAM_WEB_CAM     3	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_CAM_SECU_CAM    4	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_STOR_NAS        1
++#define WPS_DEVICE_TYPE_SUB_CAT_NW_AP           1
++#define WPS_DEVICE_TYPE_SUB_CAT_NW_ROUTER       2
++#define WPS_DEVICE_TYPE_SUB_CAT_NW_SWITCH       3
++#define WPS_DEVICE_TYPE_SUB_CAT_NW_GATEWAY      4	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_NW_BRIDGE       5	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_DISP_TV         1
++#define WPS_DEVICE_TYPE_SUB_CAT_DISP_PIC_FRAME  2
++#define WPS_DEVICE_TYPE_SUB_CAT_DISP_PROJECTOR  3
++#define WPS_DEVICE_TYPE_SUB_CAT_DISP_MONITOR    4	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_MM_DAR          1
++#define WPS_DEVICE_TYPE_SUB_CAT_MM_PVR          2
++#define WPS_DEVICE_TYPE_SUB_CAT_MM_MCX          3
++#define WPS_DEVICE_TYPE_SUB_CAT_MM_STB          4	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_MM_MS_ME        5	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_MM_PVP          6	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_GAM_XBOX        1
++#define WPS_DEVICE_TYPE_SUB_CAT_GAM_XBOX_360    2
++#define WPS_DEVICE_TYPE_SUB_CAT_GAM_PS          3
++#define WPS_DEVICE_TYPE_SUB_CAT_GAM_GC          4	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_GAM_PGD         5	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_PHONE_WM        1
++#define WPS_DEVICE_TYPE_SUB_CAT_PHONE_PSM       2	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_PHONE_PDM       3	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_PHONE_SSM       4	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_PHONE_SDM       5	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_AUDIO_TUNER     1	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_AUDIO_SPEAKERS  2	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_AUDIO_PMP       3	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_AUDIO_HEADSET   4	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_AUDIO_HPHONE    5	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_AUDIO_MPHONE    6	/* WSC 2.0 */
++#define WPS_DEVICE_TYPE_SUB_CAT_AUDIO_HTS       7	/* WSC 2.0 */
++
++
++/* Device request/response type */
++#define WPS_MSGTYPE_ENROLLEE_INFO_ONLY    0x00
++#define WPS_MSGTYPE_ENROLLEE_OPEN_8021X   0x01
++#define WPS_MSGTYPE_REGISTRAR             0x02
++#define WPS_MSGTYPE_AP_WLAN_MGR           0x03
++
++/* RF Band */
++#define WPS_RFBAND_24GHZ    0x01
++#define WPS_RFBAND_50GHZ    0x02
++
++/* Simple Config state */
++#define WPS_SCSTATE_UNCONFIGURED    0x01
++#define WPS_SCSTATE_CONFIGURED      0x02
++#define WPS_SCSTATE_OFF 11
++
++/* WPS Vendor extension key */
++#define WPS_OUI_HEADER_LEN 2
++#define WPS_OUI_HEADER_SIZE 4
++#define WPS_OUI_FIXED_HEADER_OFF 16
++#define WPS_WFA_SUBID_V2_OFF 3
++#define WPS_WFA_V2_OFF 5
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _WPS_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/linux_osl.c b/module_drivers/drivers/net/wireless/bcmdhd/linux_osl.c
+new file mode 100644
+index 000000000..5c4cc8bf5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/linux_osl.c
+@@ -0,0 +1,2842 @@
++/*
++ * Linux OS Independent Layer
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: linux_osl.c 680580 2017-01-20 11:49:58Z $
++ */
++
++#define LINUX_PORT
++
++#include <typedefs.h>
++#include <bcmendian.h>
++#include <linuxver.h>
++#include <bcmdefs.h>
++
++
++#if !defined(STBLINUX)
++#if defined(__ARM_ARCH_7A__) && !defined(DHD_USE_COHERENT_MEM_FOR_RING)
++#include <asm/cacheflush.h>
++#endif /* __ARM_ARCH_7A__ && !DHD_USE_COHERENT_MEM_FOR_RING */
++#endif /* STBLINUX */
++
++#include <linux/random.h>
++
++#include <osl.h>
++#include <bcmutils.h>
++#include <linux/delay.h>
++#include <linux/vmalloc.h>
++#include <pcicfg.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 8, 0))
++#include <asm-generic/pci-dma-compat.h>
++#endif
++
++
++#ifdef BCM_SECURE_DMA
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/printk.h>
++#include <linux/errno.h>
++#include <linux/mm.h>
++#include <linux/moduleparam.h>
++#include <asm/io.h>
++#include <linux/skbuff.h>
++#include <stbutils.h>
++#include <linux/highmem.h>
++#include <linux/dma-mapping.h>
++#include <asm/memory.h>
++#endif /* BCM_SECURE_DMA */
++
++#include <linux/fs.h>
++
++#if defined(STB)
++#include <linux/spinlock.h>
++extern spinlock_t l2x0_reg_lock;
++#endif 
++
++#ifdef BCM_OBJECT_TRACE
++#include <bcmutils.h>
++#endif /* BCM_OBJECT_TRACE */
++
++#define PCI_CFG_RETRY		10
++
++#define OS_HANDLE_MAGIC		0x1234abcd	/* Magic # to recognize osh */
++#define BCM_MEM_FILENAME_LEN	24		/* Mem. filename length */
++#define DUMPBUFSZ 1024
++
++/* dependancy check */
++#if !defined(BCMPCIE) && defined(DHD_USE_STATIC_CTRLBUF)
++#error "DHD_USE_STATIC_CTRLBUF suppored PCIE target only"
++#endif /* !BCMPCIE && DHD_USE_STATIC_CTRLBUF */
++
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++#ifdef DHD_USE_STATIC_CTRLBUF
++#define DHD_SKB_1PAGE_BUFSIZE	(PAGE_SIZE*1)
++#define DHD_SKB_2PAGE_BUFSIZE	(PAGE_SIZE*2)
++#define DHD_SKB_4PAGE_BUFSIZE	(PAGE_SIZE*4)
++
++#define PREALLOC_FREE_MAGIC	0xFEDC
++#define PREALLOC_USED_MAGIC	0xFCDE
++#else
++#define DHD_SKB_HDRSIZE		336
++#define DHD_SKB_1PAGE_BUFSIZE	((PAGE_SIZE*1)-DHD_SKB_HDRSIZE)
++#define DHD_SKB_2PAGE_BUFSIZE	((PAGE_SIZE*2)-DHD_SKB_HDRSIZE)
++#define DHD_SKB_4PAGE_BUFSIZE	((PAGE_SIZE*4)-DHD_SKB_HDRSIZE)
++#endif /* DHD_USE_STATIC_CTRLBUF */
++
++#define STATIC_BUF_MAX_NUM	16
++#define STATIC_BUF_SIZE	(PAGE_SIZE*2)
++#define STATIC_BUF_TOTAL_LEN	(STATIC_BUF_MAX_NUM * STATIC_BUF_SIZE)
++
++typedef struct bcm_static_buf {
++	spinlock_t static_lock;
++	unsigned char *buf_ptr;
++	unsigned char buf_use[STATIC_BUF_MAX_NUM];
++} bcm_static_buf_t;
++
++static bcm_static_buf_t *bcm_static_buf = 0;
++
++#ifdef DHD_USE_STATIC_CTRLBUF
++#define STATIC_PKT_4PAGE_NUM	0
++#define DHD_SKB_MAX_BUFSIZE	DHD_SKB_2PAGE_BUFSIZE
++#elif defined(ENHANCED_STATIC_BUF)
++#define STATIC_PKT_4PAGE_NUM	1
++#define DHD_SKB_MAX_BUFSIZE	DHD_SKB_4PAGE_BUFSIZE
++#else
++#define STATIC_PKT_4PAGE_NUM	0
++#define DHD_SKB_MAX_BUFSIZE	DHD_SKB_2PAGE_BUFSIZE
++#endif /* DHD_USE_STATIC_CTRLBUF */
++
++#ifdef DHD_USE_STATIC_CTRLBUF
++#define STATIC_PKT_1PAGE_NUM	0
++#define STATIC_PKT_2PAGE_NUM	128
++#else
++#define STATIC_PKT_1PAGE_NUM	8
++#define STATIC_PKT_2PAGE_NUM	8
++#endif /* DHD_USE_STATIC_CTRLBUF */
++
++#define STATIC_PKT_1_2PAGE_NUM	\
++	((STATIC_PKT_1PAGE_NUM) + (STATIC_PKT_2PAGE_NUM))
++#define STATIC_PKT_MAX_NUM	\
++	((STATIC_PKT_1_2PAGE_NUM) + (STATIC_PKT_4PAGE_NUM))
++
++typedef struct bcm_static_pkt {
++#ifdef DHD_USE_STATIC_CTRLBUF
++	struct sk_buff *skb_8k[STATIC_PKT_2PAGE_NUM];
++	unsigned char pkt_invalid[STATIC_PKT_2PAGE_NUM];
++	spinlock_t osl_pkt_lock;
++	uint32 last_allocated_index;
++#else
++	struct sk_buff *skb_4k[STATIC_PKT_1PAGE_NUM];
++	struct sk_buff *skb_8k[STATIC_PKT_2PAGE_NUM];
++#ifdef ENHANCED_STATIC_BUF
++	struct sk_buff *skb_16k;
++#endif /* ENHANCED_STATIC_BUF */
++	struct semaphore osl_pkt_sem;
++#endif /* DHD_USE_STATIC_CTRLBUF */
++	unsigned char pkt_use[STATIC_PKT_MAX_NUM];
++} bcm_static_pkt_t;
++
++static bcm_static_pkt_t *bcm_static_skb = 0;
++
++void* wifi_platform_prealloc(void *adapter, int section, unsigned long size);
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++
++typedef struct bcm_mem_link {
++	struct bcm_mem_link *prev;
++	struct bcm_mem_link *next;
++	uint	size;
++	int	line;
++	void 	*osh;
++	char	file[BCM_MEM_FILENAME_LEN];
++} bcm_mem_link_t;
++
++struct osl_cmn_info {
++	atomic_t malloced;
++	atomic_t pktalloced;    /* Number of allocated packet buffers */
++	spinlock_t dbgmem_lock;
++	bcm_mem_link_t *dbgmem_list;
++	bcm_mem_link_t *dbgvmem_list;
++	spinlock_t pktalloc_lock;
++	atomic_t refcount; /* Number of references to this shared structure. */
++};
++typedef struct osl_cmn_info osl_cmn_t;
++
++struct osl_info {
++	osl_pubinfo_t pub;
++	uint32  flags;		/* If specific cases to be handled in the OSL */
++#ifdef CTFPOOL
++	ctfpool_t *ctfpool;
++#endif /* CTFPOOL */
++	uint magic;
++	void *pdev;
++	uint failed;
++	uint bustype;
++	osl_cmn_t *cmn; /* Common OSL related data shred between two OSH's */
++
++	void *bus_handle;
++#ifdef BCMDBG_CTRACE
++	spinlock_t ctrace_lock;
++	struct list_head ctrace_list;
++	int ctrace_num;
++#endif /* BCMDBG_CTRACE */
++#ifdef	BCM_SECURE_DMA
++	struct sec_mem_elem *sec_list_4096;
++	struct sec_mem_elem *sec_list_base_4096;
++	phys_addr_t  contig_base;
++	void *contig_base_va;
++	phys_addr_t  contig_base_alloc;
++	void *contig_base_alloc_va;
++	phys_addr_t contig_base_alloc_coherent;
++	void *contig_base_alloc_coherent_va;
++	void *contig_base_coherent_va;
++	void *contig_delta_va_pa;
++	struct {
++		phys_addr_t pa;
++		void *va;
++		bool avail;
++	} sec_cma_coherent[SEC_CMA_COHERENT_MAX];
++	int stb_ext_params;
++#endif /* BCM_SECURE_DMA */
++};
++#ifdef BCM_SECURE_DMA
++static void * osl_sec_dma_ioremap(osl_t *osh, struct page *page, size_t size,
++	bool iscache, bool isdecr);
++static void osl_sec_dma_iounmap(osl_t *osh, void *contig_base_va, size_t size);
++static int osl_sec_dma_init_elem_mem_block(osl_t *osh, size_t mbsize, int max,
++	sec_mem_elem_t **list);
++static void osl_sec_dma_deinit_elem_mem_block(osl_t *osh, size_t mbsize, int max,
++	void *sec_list_base);
++static sec_mem_elem_t * osl_sec_dma_alloc_mem_elem(osl_t *osh, void *va, uint size,
++	int direction, struct sec_cma_info *ptr_cma_info, uint offset);
++static void osl_sec_dma_free_mem_elem(osl_t *osh, sec_mem_elem_t *sec_mem_elem);
++static void osl_sec_dma_init_consistent(osl_t *osh);
++static void *osl_sec_dma_alloc_consistent(osl_t *osh, uint size, uint16 align_bits,
++	ulong *pap);
++static void osl_sec_dma_free_consistent(osl_t *osh, void *va, uint size, dmaaddr_t pa);
++#endif /* BCM_SECURE_DMA */
++
++#ifdef BCM_OBJECT_TRACE
++/* don't clear the first 4 byte that is the pkt sn */
++#define OSL_PKTTAG_CLEAR(p) \
++do { \
++	struct sk_buff *s = (struct sk_buff *)(p); \
++	ASSERT(OSL_PKTTAG_SZ == 32); \
++	*(uint32 *)(&s->cb[4]) = 0; \
++	*(uint32 *)(&s->cb[8]) = 0; *(uint32 *)(&s->cb[12]) = 0; \
++	*(uint32 *)(&s->cb[16]) = 0; *(uint32 *)(&s->cb[20]) = 0; \
++	*(uint32 *)(&s->cb[24]) = 0; *(uint32 *)(&s->cb[28]) = 0; \
++} while (0)
++#else
++#define OSL_PKTTAG_CLEAR(p) \
++do { \
++	struct sk_buff *s = (struct sk_buff *)(p); \
++	ASSERT(OSL_PKTTAG_SZ == 32); \
++	*(uint32 *)(&s->cb[0]) = 0; *(uint32 *)(&s->cb[4]) = 0; \
++	*(uint32 *)(&s->cb[8]) = 0; *(uint32 *)(&s->cb[12]) = 0; \
++	*(uint32 *)(&s->cb[16]) = 0; *(uint32 *)(&s->cb[20]) = 0; \
++	*(uint32 *)(&s->cb[24]) = 0; *(uint32 *)(&s->cb[28]) = 0; \
++} while (0)
++#endif /* BCM_OBJECT_TRACE */
++
++/* PCMCIA attribute space access macros */
++
++uint32 g_assert_type = 0; /* By Default Kernel Panic */
++
++module_param(g_assert_type, int, 0);
++#ifdef	BCM_SECURE_DMA
++#define	SECDMA_MODULE_PARAMS	0
++#define	SECDMA_EXT_FILE	1
++unsigned long secdma_addr = 0;
++unsigned long secdma_addr2 = 0;
++u32 secdma_size = 0;
++u32 secdma_size2 = 0;
++module_param(secdma_addr, ulong, 0);
++module_param(secdma_size, int, 0);
++module_param(secdma_addr2, ulong, 0);
++module_param(secdma_size2, int, 0);
++static int secdma_found = 0;
++#endif /* BCM_SECURE_DMA */
++
++static int16 linuxbcmerrormap[] =
++{	0,				/* 0 */
++	-EINVAL,		/* BCME_ERROR */
++	-EINVAL,		/* BCME_BADARG */
++	-EINVAL,		/* BCME_BADOPTION */
++	-EINVAL,		/* BCME_NOTUP */
++	-EINVAL,		/* BCME_NOTDOWN */
++	-EINVAL,		/* BCME_NOTAP */
++	-EINVAL,		/* BCME_NOTSTA */
++	-EINVAL,		/* BCME_BADKEYIDX */
++	-EINVAL,		/* BCME_RADIOOFF */
++	-EINVAL,		/* BCME_NOTBANDLOCKED */
++	-EINVAL, 		/* BCME_NOCLK */
++	-EINVAL, 		/* BCME_BADRATESET */
++	-EINVAL, 		/* BCME_BADBAND */
++	-E2BIG,			/* BCME_BUFTOOSHORT */
++	-E2BIG,			/* BCME_BUFTOOLONG */
++	-EBUSY, 		/* BCME_BUSY */
++	-EINVAL, 		/* BCME_NOTASSOCIATED */
++	-EINVAL, 		/* BCME_BADSSIDLEN */
++	-EINVAL, 		/* BCME_OUTOFRANGECHAN */
++	-EINVAL, 		/* BCME_BADCHAN */
++	-EFAULT, 		/* BCME_BADADDR */
++	-ENOMEM, 		/* BCME_NORESOURCE */
++	-EOPNOTSUPP,		/* BCME_UNSUPPORTED */
++	-EMSGSIZE,		/* BCME_BADLENGTH */
++	-EINVAL,		/* BCME_NOTREADY */
++	-EPERM,			/* BCME_EPERM */
++	-ENOMEM, 		/* BCME_NOMEM */
++	-EINVAL, 		/* BCME_ASSOCIATED */
++	-ERANGE, 		/* BCME_RANGE */
++	-EINVAL, 		/* BCME_NOTFOUND */
++	-EINVAL, 		/* BCME_WME_NOT_ENABLED */
++	-EINVAL, 		/* BCME_TSPEC_NOTFOUND */
++	-EINVAL, 		/* BCME_ACM_NOTSUPPORTED */
++	-EINVAL,		/* BCME_NOT_WME_ASSOCIATION */
++	-EIO,			/* BCME_SDIO_ERROR */
++	-ENODEV,		/* BCME_DONGLE_DOWN */
++	-EINVAL,		/* BCME_VERSION */
++	-EIO,			/* BCME_TXFAIL */
++	-EIO,			/* BCME_RXFAIL */
++	-ENODEV,		/* BCME_NODEVICE */
++	-EINVAL,		/* BCME_NMODE_DISABLED */
++	-ENODATA,		/* BCME_NONRESIDENT */
++	-EINVAL,		/* BCME_SCANREJECT */
++	-EINVAL,		/* BCME_USAGE_ERROR */
++	-EIO,     		/* BCME_IOCTL_ERROR */
++	-EIO,			/* BCME_SERIAL_PORT_ERR */
++	-EOPNOTSUPP,	/* BCME_DISABLED, BCME_NOTENABLED */
++	-EIO,			/* BCME_DECERR */
++	-EIO,			/* BCME_ENCERR */
++	-EIO,			/* BCME_MICERR */
++	-ERANGE,		/* BCME_REPLAY */
++	-EINVAL,		/* BCME_IE_NOTFOUND */
++	-EINVAL,		/* BCME_DATA_NOTFOUND */
++	-EINVAL,        /* BCME_NOT_GC */
++	-EINVAL,        /* BCME_PRS_REQ_FAILED */
++	-EINVAL,        /* BCME_NO_P2P_SE */
++	-EINVAL,        /* BCME_NOA_PND */
++	-EINVAL,        /* BCME_FRAG_Q_FAILED */
++	-EINVAL,        /* BCME_GET_AF_FAILED */
++	-EINVAL,		/* BCME_MSCH_NOTREADY */
++
++/* When an new error code is added to bcmutils.h, add os
++ * specific error translation here as well
++ */
++/* check if BCME_LAST changed since the last time this function was updated */
++#if BCME_LAST != -60
++#error "You need to add a OS error translation in the linuxbcmerrormap \
++	for new error code defined in bcmutils.h"
++#endif
++};
++uint lmtest = FALSE;
++
++/* translate bcmerrors into linux errors */
++int
++osl_error(int bcmerror)
++{
++	if (bcmerror > 0)
++		bcmerror = 0;
++	else if (bcmerror < BCME_LAST)
++		bcmerror = BCME_ERROR;
++
++	/* Array bounds covered by ASSERT in osl_attach */
++	return linuxbcmerrormap[-bcmerror];
++}
++
++osl_t *
++#ifdef SHARED_OSL_CMN
++osl_attach(void *pdev, uint bustype, bool pkttag, void **osl_cmn)
++#else
++osl_attach(void *pdev, uint bustype, bool pkttag)
++#endif /* SHARED_OSL_CMN */
++{
++#ifndef SHARED_OSL_CMN
++	void **osl_cmn = NULL;
++#endif /* SHARED_OSL_CMN */
++	osl_t *osh;
++	gfp_t flags;
++#ifdef BCM_SECURE_DMA
++	u32 secdma_memsize;
++#endif
++
++	flags = CAN_SLEEP() ? GFP_KERNEL: GFP_ATOMIC;
++	if (!(osh = kmalloc(sizeof(osl_t), flags)))
++		return osh;
++
++	ASSERT(osh);
++
++	bzero(osh, sizeof(osl_t));
++
++	if (osl_cmn == NULL || *osl_cmn == NULL) {
++		if (!(osh->cmn = kmalloc(sizeof(osl_cmn_t), flags))) {
++			kfree(osh);
++			return NULL;
++		}
++		bzero(osh->cmn, sizeof(osl_cmn_t));
++		if (osl_cmn)
++			*osl_cmn = osh->cmn;
++		atomic_set(&osh->cmn->malloced, 0);
++		osh->cmn->dbgmem_list = NULL;
++		spin_lock_init(&(osh->cmn->dbgmem_lock));
++
++		spin_lock_init(&(osh->cmn->pktalloc_lock));
++
++	} else {
++		osh->cmn = *osl_cmn;
++	}
++	atomic_add(1, &osh->cmn->refcount);
++
++	bcm_object_trace_init();
++
++	/* Check that error map has the right number of entries in it */
++	ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(linuxbcmerrormap) - 1));
++
++	osh->failed = 0;
++	osh->pdev = pdev;
++	osh->pub.pkttag = pkttag;
++	osh->bustype = bustype;
++	osh->magic = OS_HANDLE_MAGIC;
++#ifdef BCM_SECURE_DMA
++
++	if ((secdma_addr != 0) && (secdma_size != 0)) {
++		printk("linux_osl.c: Buffer info passed via module params, using it.\n");
++		if (secdma_found == 0) {
++			osh->contig_base_alloc = (phys_addr_t)secdma_addr;
++			secdma_memsize = secdma_size;
++		} else if (secdma_found == 1) {
++			osh->contig_base_alloc = (phys_addr_t)secdma_addr2;
++			secdma_memsize = secdma_size2;
++		} else {
++			printk("linux_osl.c secdma: secDMA instances %d \n", secdma_found);
++			kfree(osh);
++			return NULL;
++		}
++		osh->contig_base = (phys_addr_t)osh->contig_base_alloc;
++		printf("linux_osl.c: secdma_cma_size = 0x%x\n", secdma_memsize);
++		printf("linux_osl.c: secdma_cma_addr = 0x%x \n",
++			(unsigned int)osh->contig_base_alloc);
++		osh->stb_ext_params = SECDMA_MODULE_PARAMS;
++	}
++	else if (stbpriv_init(osh) == 0) {
++		printk("linux_osl.c: stbpriv.txt found. Get buffer info.\n");
++		if (secdma_found == 0) {
++			osh->contig_base_alloc =
++				(phys_addr_t)bcm_strtoul(stbparam_get("secdma_cma_addr"), NULL, 0);
++			secdma_memsize = bcm_strtoul(stbparam_get("secdma_cma_size"), NULL, 0);
++		} else if (secdma_found == 1) {
++			osh->contig_base_alloc =
++				(phys_addr_t)bcm_strtoul(stbparam_get("secdma_cma_addr2"), NULL, 0);
++			secdma_memsize = bcm_strtoul(stbparam_get("secdma_cma_size2"), NULL, 0);
++		} else {
++			printk("linux_osl.c secdma: secDMA instances %d \n", secdma_found);
++			kfree(osh);
++			return NULL;
++		}
++		osh->contig_base = (phys_addr_t)osh->contig_base_alloc;
++		printf("linux_osl.c: secdma_cma_size = 0x%x\n", secdma_memsize);
++		printf("linux_osl.c: secdma_cma_addr = 0x%x \n",
++			(unsigned int)osh->contig_base_alloc);
++		osh->stb_ext_params = SECDMA_EXT_FILE;
++	}
++	else {
++		printk("linux_osl.c: secDMA no longer supports internal buffer allocation.\n");
++		kfree(osh);
++		return NULL;
++	}
++	secdma_found++;
++	osh->contig_base_alloc_coherent_va = osl_sec_dma_ioremap(osh,
++		phys_to_page((u32)osh->contig_base_alloc),
++		CMA_DMA_DESC_MEMBLOCK, FALSE, TRUE);
++
++	if (osh->contig_base_alloc_coherent_va == NULL) {
++		if (osh->cmn)
++			kfree(osh->cmn);
++	    kfree(osh);
++	    return NULL;
++	}
++	osh->contig_base_coherent_va = osh->contig_base_alloc_coherent_va;
++	osh->contig_base_alloc_coherent = osh->contig_base_alloc;
++	osl_sec_dma_init_consistent(osh);
++
++	osh->contig_base_alloc += CMA_DMA_DESC_MEMBLOCK;
++
++	osh->contig_base_alloc_va = osl_sec_dma_ioremap(osh,
++		phys_to_page((u32)osh->contig_base_alloc), CMA_DMA_DATA_MEMBLOCK, TRUE, FALSE);
++	if (osh->contig_base_alloc_va == NULL) {
++		osl_sec_dma_iounmap(osh, osh->contig_base_coherent_va, CMA_DMA_DESC_MEMBLOCK);
++		if (osh->cmn)
++			kfree(osh->cmn);
++		kfree(osh);
++		return NULL;
++	}
++	osh->contig_base_va = osh->contig_base_alloc_va;
++
++	if (BCME_OK != osl_sec_dma_init_elem_mem_block(osh,
++		CMA_BUFSIZE_4K, CMA_BUFNUM, &osh->sec_list_4096)) {
++	    osl_sec_dma_iounmap(osh, osh->contig_base_coherent_va, CMA_DMA_DESC_MEMBLOCK);
++	    osl_sec_dma_iounmap(osh, osh->contig_base_va, CMA_DMA_DATA_MEMBLOCK);
++		if (osh->cmn)
++			kfree(osh->cmn);
++		kfree(osh);
++		return NULL;
++	}
++	osh->sec_list_base_4096 = osh->sec_list_4096;
++
++#endif /* BCM_SECURE_DMA */
++
++	switch (bustype) {
++		case PCI_BUS:
++		case SI_BUS:
++		case PCMCIA_BUS:
++			osh->pub.mmbus = TRUE;
++			break;
++		case JTAG_BUS:
++		case SDIO_BUS:
++		case USB_BUS:
++		case SPI_BUS:
++		case RPC_BUS:
++			osh->pub.mmbus = FALSE;
++			break;
++		default:
++			ASSERT(FALSE);
++			break;
++	}
++
++#ifdef BCMDBG_CTRACE
++	spin_lock_init(&osh->ctrace_lock);
++	INIT_LIST_HEAD(&osh->ctrace_list);
++	osh->ctrace_num = 0;
++#endif /* BCMDBG_CTRACE */
++
++
++	return osh;
++}
++
++int osl_static_mem_init(osl_t *osh, void *adapter)
++{
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++		if (!bcm_static_buf && adapter) {
++			if (!(bcm_static_buf = (bcm_static_buf_t *)wifi_platform_prealloc(adapter,
++				DHD_PREALLOC_OSL_BUF, STATIC_BUF_SIZE + STATIC_BUF_TOTAL_LEN))) {
++				printk("can not alloc static buf!\n");
++				bcm_static_skb = NULL;
++				ASSERT(osh->magic == OS_HANDLE_MAGIC);
++				return -ENOMEM;
++			} else {
++				printk("alloc static buf at %p!\n", bcm_static_buf);
++			}
++
++			spin_lock_init(&bcm_static_buf->static_lock);
++
++			bcm_static_buf->buf_ptr = (unsigned char *)bcm_static_buf + STATIC_BUF_SIZE;
++		}
++
++#if defined(BCMSDIO) || defined(DHD_USE_STATIC_CTRLBUF)
++		if (!bcm_static_skb && adapter) {
++			int i;
++			void *skb_buff_ptr = 0;
++			bcm_static_skb = (bcm_static_pkt_t *)((char *)bcm_static_buf + 2048);
++			skb_buff_ptr = wifi_platform_prealloc(adapter, DHD_PREALLOC_SKB_BUF, 0);
++			if (!skb_buff_ptr) {
++				printk("cannot alloc static buf!\n");
++				bcm_static_buf = NULL;
++				bcm_static_skb = NULL;
++				ASSERT(osh->magic == OS_HANDLE_MAGIC);
++				return -ENOMEM;
++			}
++
++			bcopy(skb_buff_ptr, bcm_static_skb, sizeof(struct sk_buff *) *
++				(STATIC_PKT_MAX_NUM));
++			for (i = 0; i < STATIC_PKT_MAX_NUM; i++) {
++				bcm_static_skb->pkt_use[i] = 0;
++			}
++
++#ifdef DHD_USE_STATIC_CTRLBUF
++			spin_lock_init(&bcm_static_skb->osl_pkt_lock);
++			bcm_static_skb->last_allocated_index = 0;
++#else
++			sema_init(&bcm_static_skb->osl_pkt_sem, 1);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++		}
++#endif /* BCMSDIO || DHD_USE_STATIC_CTRLBUF */
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++
++	return 0;
++}
++
++void osl_set_bus_handle(osl_t *osh, void *bus_handle)
++{
++	osh->bus_handle = bus_handle;
++}
++
++void* osl_get_bus_handle(osl_t *osh)
++{
++	return osh->bus_handle;
++}
++
++void
++osl_detach(osl_t *osh)
++{
++	if (osh == NULL)
++		return;
++
++#ifdef BCM_SECURE_DMA
++	if (osh->stb_ext_params == SECDMA_EXT_FILE)
++		stbpriv_exit(osh);
++	osl_sec_dma_deinit_elem_mem_block(osh, CMA_BUFSIZE_4K, CMA_BUFNUM, osh->sec_list_base_4096);
++	osl_sec_dma_iounmap(osh, osh->contig_base_coherent_va, CMA_DMA_DESC_MEMBLOCK);
++	osl_sec_dma_iounmap(osh, osh->contig_base_va, CMA_DMA_DATA_MEMBLOCK);
++	secdma_found--;
++#endif /* BCM_SECURE_DMA */
++
++
++	bcm_object_trace_deinit();
++
++	ASSERT(osh->magic == OS_HANDLE_MAGIC);
++	atomic_sub(1, &osh->cmn->refcount);
++	if (atomic_read(&osh->cmn->refcount) == 0) {
++			kfree(osh->cmn);
++	}
++	kfree(osh);
++}
++
++int osl_static_mem_deinit(osl_t *osh, void *adapter)
++{
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++	if (bcm_static_buf) {
++		bcm_static_buf = 0;
++	}
++#ifdef BCMSDIO
++	if (bcm_static_skb) {
++		bcm_static_skb = 0;
++	}
++#endif /* BCMSDIO */
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++	return 0;
++}
++
++/* APIs to set/get specific quirks in OSL layer */
++void BCMFASTPATH
++osl_flag_set(osl_t *osh, uint32 mask)
++{
++	osh->flags |= mask;
++}
++
++void
++osl_flag_clr(osl_t *osh, uint32 mask)
++{
++	osh->flags &= ~mask;
++}
++
++#if defined(STB)
++inline bool BCMFASTPATH
++#else
++bool
++#endif 
++osl_is_flag_set(osl_t *osh, uint32 mask)
++{
++	return (osh->flags & mask);
++}
++
++
++#if (defined(__ARM_ARCH_7A__) && !defined(DHD_USE_COHERENT_MEM_FOR_RING))
++
++inline int BCMFASTPATH
++osl_arch_is_coherent(void)
++{
++	return 0;
++}
++
++inline int BCMFASTPATH
++osl_acp_war_enab(void)
++{
++	return 0;
++}
++
++inline void BCMFASTPATH
++osl_cache_flush(void *va, uint size)
++{
++
++	if (size > 0)
++	dma_sync_single_for_device(OSH_NULL, virt_to_dma(OSH_NULL, va), size, DMA_TO_DEVICE);
++}
++
++inline void BCMFASTPATH
++osl_cache_inv(void *va, uint size)
++{
++
++	dma_sync_single_for_cpu(OSH_NULL, virt_to_dma(OSH_NULL, va), size, DMA_FROM_DEVICE);
++}
++
++inline void BCMFASTPATH
++osl_prefetch(const void *ptr)
++{
++	__asm__ __volatile__("pld\t%0" :: "o"(*(char *)ptr) : "cc");
++}
++
++#endif 
++
++/*
++ * To avoid ACP latency, a fwder buf will be sent directly to DDR using
++ * DDR aliasing into non-ACP address space. Such Fwder buffers must be
++ * explicitly managed from a coherency perspective.
++ */
++static inline void BCMFASTPATH
++osl_fwderbuf_reset(osl_t *osh, struct sk_buff *skb)
++{
++}
++
++static struct sk_buff *osl_alloc_skb(osl_t *osh, unsigned int len)
++{
++	struct sk_buff *skb;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25)
++	gfp_t flags = (in_atomic() || irqs_disabled()) ? GFP_ATOMIC : GFP_KERNEL;
++#ifdef DHD_USE_ATOMIC_PKTGET
++	flags = GFP_ATOMIC;
++#endif /* DHD_USE_ATOMIC_PKTGET */
++	skb = __dev_alloc_skb(len, flags);
++#else
++	skb = dev_alloc_skb(len);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25) */
++	return skb;
++}
++
++#ifdef CTFPOOL
++
++#ifdef CTFPOOL_SPINLOCK
++#define CTFPOOL_LOCK(ctfpool, flags)	spin_lock_irqsave(&(ctfpool)->lock, flags)
++#define CTFPOOL_UNLOCK(ctfpool, flags)	spin_unlock_irqrestore(&(ctfpool)->lock, flags)
++#else
++#define CTFPOOL_LOCK(ctfpool, flags)	spin_lock_bh(&(ctfpool)->lock)
++#define CTFPOOL_UNLOCK(ctfpool, flags)	spin_unlock_bh(&(ctfpool)->lock)
++#endif /* CTFPOOL_SPINLOCK */
++/*
++ * Allocate and add an object to packet pool.
++ */
++void *
++osl_ctfpool_add(osl_t *osh)
++{
++	struct sk_buff *skb;
++#ifdef CTFPOOL_SPINLOCK
++	unsigned long flags;
++#endif /* CTFPOOL_SPINLOCK */
++
++	if ((osh == NULL) || (osh->ctfpool == NULL))
++		return NULL;
++
++	CTFPOOL_LOCK(osh->ctfpool, flags);
++	ASSERT(osh->ctfpool->curr_obj <= osh->ctfpool->max_obj);
++
++	/* No need to allocate more objects */
++	if (osh->ctfpool->curr_obj == osh->ctfpool->max_obj) {
++		CTFPOOL_UNLOCK(osh->ctfpool, flags);
++		return NULL;
++	}
++
++	/* Allocate a new skb and add it to the ctfpool */
++	skb = osl_alloc_skb(osh, osh->ctfpool->obj_size);
++	if (skb == NULL) {
++		printf("%s: skb alloc of len %d failed\n", __FUNCTION__,
++		       osh->ctfpool->obj_size);
++		CTFPOOL_UNLOCK(osh->ctfpool, flags);
++		return NULL;
++	}
++
++	/* Add to ctfpool */
++	skb->next = (struct sk_buff *)osh->ctfpool->head;
++	osh->ctfpool->head = skb;
++	osh->ctfpool->fast_frees++;
++	osh->ctfpool->curr_obj++;
++
++	/* Hijack a skb member to store ptr to ctfpool */
++	CTFPOOLPTR(osh, skb) = (void *)osh->ctfpool;
++
++	/* Use bit flag to indicate skb from fast ctfpool */
++	PKTFAST(osh, skb) = FASTBUF;
++
++	/* If ctfpool's osh is a fwder osh, reset the fwder buf */
++	osl_fwderbuf_reset(osh->ctfpool->osh, skb);
++
++	CTFPOOL_UNLOCK(osh->ctfpool, flags);
++
++	return skb;
++}
++
++/*
++ * Add new objects to the pool.
++ */
++void
++osl_ctfpool_replenish(osl_t *osh, uint thresh)
++{
++	if ((osh == NULL) || (osh->ctfpool == NULL))
++		return;
++
++	/* Do nothing if no refills are required */
++	while ((osh->ctfpool->refills > 0) && (thresh--)) {
++		osl_ctfpool_add(osh);
++		osh->ctfpool->refills--;
++	}
++}
++
++/*
++ * Initialize the packet pool with specified number of objects.
++ */
++int32
++osl_ctfpool_init(osl_t *osh, uint numobj, uint size)
++{
++	gfp_t flags;
++
++	flags = CAN_SLEEP() ? GFP_KERNEL: GFP_ATOMIC;
++	osh->ctfpool = kzalloc(sizeof(ctfpool_t), flags);
++	ASSERT(osh->ctfpool);
++
++	osh->ctfpool->osh = osh;
++
++	osh->ctfpool->max_obj = numobj;
++	osh->ctfpool->obj_size = size;
++
++	spin_lock_init(&osh->ctfpool->lock);
++
++	while (numobj--) {
++		if (!osl_ctfpool_add(osh))
++			return -1;
++		osh->ctfpool->fast_frees--;
++	}
++
++	return 0;
++}
++
++/*
++ * Cleanup the packet pool objects.
++ */
++void
++osl_ctfpool_cleanup(osl_t *osh)
++{
++	struct sk_buff *skb, *nskb;
++#ifdef CTFPOOL_SPINLOCK
++	unsigned long flags;
++#endif /* CTFPOOL_SPINLOCK */
++
++	if ((osh == NULL) || (osh->ctfpool == NULL))
++		return;
++
++	CTFPOOL_LOCK(osh->ctfpool, flags);
++
++	skb = osh->ctfpool->head;
++
++	while (skb != NULL) {
++		nskb = skb->next;
++		dev_kfree_skb(skb);
++		skb = nskb;
++		osh->ctfpool->curr_obj--;
++	}
++
++	ASSERT(osh->ctfpool->curr_obj == 0);
++	osh->ctfpool->head = NULL;
++	CTFPOOL_UNLOCK(osh->ctfpool, flags);
++
++	kfree(osh->ctfpool);
++	osh->ctfpool = NULL;
++}
++
++void
++osl_ctfpool_stats(osl_t *osh, void *b)
++{
++	struct bcmstrbuf *bb;
++
++	if ((osh == NULL) || (osh->ctfpool == NULL))
++		return;
++
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++	if (bcm_static_buf) {
++		bcm_static_buf = 0;
++	}
++#ifdef BCMSDIO
++	if (bcm_static_skb) {
++		bcm_static_skb = 0;
++	}
++#endif /* BCMSDIO */
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++
++	bb = b;
++
++	ASSERT((osh != NULL) && (bb != NULL));
++
++	bcm_bprintf(bb, "max_obj %d obj_size %d curr_obj %d refills %d\n",
++	            osh->ctfpool->max_obj, osh->ctfpool->obj_size,
++	            osh->ctfpool->curr_obj, osh->ctfpool->refills);
++	bcm_bprintf(bb, "fast_allocs %d fast_frees %d slow_allocs %d\n",
++	            osh->ctfpool->fast_allocs, osh->ctfpool->fast_frees,
++	            osh->ctfpool->slow_allocs);
++}
++
++static inline struct sk_buff *
++osl_pktfastget(osl_t *osh, uint len)
++{
++	struct sk_buff *skb;
++#ifdef CTFPOOL_SPINLOCK
++	unsigned long flags;
++#endif /* CTFPOOL_SPINLOCK */
++
++	/* Try to do fast allocate. Return null if ctfpool is not in use
++	 * or if there are no items in the ctfpool.
++	 */
++	if (osh->ctfpool == NULL)
++		return NULL;
++
++	CTFPOOL_LOCK(osh->ctfpool, flags);
++	if (osh->ctfpool->head == NULL) {
++		ASSERT(osh->ctfpool->curr_obj == 0);
++		osh->ctfpool->slow_allocs++;
++		CTFPOOL_UNLOCK(osh->ctfpool, flags);
++		return NULL;
++	}
++
++	if (len > osh->ctfpool->obj_size) {
++		CTFPOOL_UNLOCK(osh->ctfpool, flags);
++		return NULL;
++	}
++
++	ASSERT(len <= osh->ctfpool->obj_size);
++
++	/* Get an object from ctfpool */
++	skb = (struct sk_buff *)osh->ctfpool->head;
++	osh->ctfpool->head = (void *)skb->next;
++
++	osh->ctfpool->fast_allocs++;
++	osh->ctfpool->curr_obj--;
++	ASSERT(CTFPOOLHEAD(osh, skb) == (struct sock *)osh->ctfpool->head);
++	CTFPOOL_UNLOCK(osh->ctfpool, flags);
++
++	/* Init skb struct */
++	skb->next = skb->prev = NULL;
++#if defined(__ARM_ARCH_7A__)
++	skb->data = skb->head + NET_SKB_PAD;
++	skb->tail = skb->head + NET_SKB_PAD;
++#else
++	skb->data = skb->head + 16;
++	skb->tail = skb->head + 16;
++#endif /* __ARM_ARCH_7A__ */
++	skb->len = 0;
++	skb->cloned = 0;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 14)
++	skb->list = NULL;
++#endif
++	atomic_set(&skb->users, 1);
++
++	PKTSETCLINK(skb, NULL);
++	PKTCCLRATTR(skb);
++	PKTFAST(osh, skb) &= ~(CTFBUF | SKIPCT | CHAINED);
++
++	return skb;
++}
++#endif /* CTFPOOL */
++
++#if defined(BCM_GMAC3)
++/* Account for a packet delivered to downstream forwarder.
++ * Decrement a GMAC forwarder interface's pktalloced count.
++ */
++void BCMFASTPATH
++osl_pkt_tofwder(osl_t *osh, void *skbs, int skb_cnt)
++{
++
++	atomic_sub(skb_cnt, &osh->cmn->pktalloced);
++}
++
++/* Account for a downstream forwarder delivered packet to a WL/DHD driver.
++ * Increment a GMAC forwarder interface's pktalloced count.
++ */
++void BCMFASTPATH
++#ifdef BCMDBG_CTRACE
++osl_pkt_frmfwder(osl_t *osh, void *skbs, int skb_cnt, int line, char *file)
++#else
++osl_pkt_frmfwder(osl_t *osh, void *skbs, int skb_cnt)
++#endif /* BCMDBG_CTRACE */
++{
++#if defined(BCMDBG_CTRACE)
++	int i;
++	struct sk_buff *skb;
++#endif 
++
++#if defined(BCMDBG_CTRACE)
++	if (skb_cnt > 1) {
++		struct sk_buff **skb_array = (struct sk_buff **)skbs;
++		for (i = 0; i < skb_cnt; i++) {
++			skb = skb_array[i];
++#if defined(BCMDBG_CTRACE)
++			ASSERT(!PKTISCHAINED(skb));
++			ADD_CTRACE(osh, skb, file, line);
++#endif /* BCMDBG_CTRACE */
++		}
++	} else {
++		skb = (struct sk_buff *)skbs;
++#if defined(BCMDBG_CTRACE)
++		ASSERT(!PKTISCHAINED(skb));
++		ADD_CTRACE(osh, skb, file, line);
++#endif /* BCMDBG_CTRACE */
++	}
++#endif 
++
++	atomic_add(skb_cnt, &osh->cmn->pktalloced);
++}
++
++#endif /* BCM_GMAC3 */
++
++/* Convert a driver packet to native(OS) packet
++ * In the process, packettag is zeroed out before sending up
++ * IP code depends on skb->cb to be setup correctly with various options
++ * In our case, that means it should be 0
++ */
++struct sk_buff * BCMFASTPATH
++osl_pkt_tonative(osl_t *osh, void *pkt)
++{
++	struct sk_buff *nskb;
++#ifdef BCMDBG_CTRACE
++	struct sk_buff *nskb1, *nskb2;
++#endif
++
++	if (osh->pub.pkttag)
++		OSL_PKTTAG_CLEAR(pkt);
++
++	/* Decrement the packet counter */
++	for (nskb = (struct sk_buff *)pkt; nskb; nskb = nskb->next) {
++		atomic_sub(PKTISCHAINED(nskb) ? PKTCCNT(nskb) : 1, &osh->cmn->pktalloced);
++
++#ifdef BCMDBG_CTRACE
++		for (nskb1 = nskb; nskb1 != NULL; nskb1 = nskb2) {
++			if (PKTISCHAINED(nskb1)) {
++				nskb2 = PKTCLINK(nskb1);
++			} else {
++				nskb2 = NULL;
++			}
++
++			DEL_CTRACE(osh, nskb1);
++		}
++#endif /* BCMDBG_CTRACE */
++	}
++	return (struct sk_buff *)pkt;
++}
++
++/* Convert a native(OS) packet to driver packet.
++ * In the process, native packet is destroyed, there is no copying
++ * Also, a packettag is zeroed out
++ */
++void * BCMFASTPATH
++#ifdef BCMDBG_CTRACE
++osl_pkt_frmnative(osl_t *osh, void *pkt, int line, char *file)
++#else
++osl_pkt_frmnative(osl_t *osh, void *pkt)
++#endif /* BCMDBG_CTRACE */
++{
++	struct sk_buff *cskb;
++	struct sk_buff *nskb;
++	unsigned long pktalloced = 0;
++
++	if (osh->pub.pkttag)
++		OSL_PKTTAG_CLEAR(pkt);
++
++	/* walk the PKTCLINK() list */
++	for (cskb = (struct sk_buff *)pkt;
++	     cskb != NULL;
++	     cskb = PKTISCHAINED(cskb) ? PKTCLINK(cskb) : NULL) {
++
++		/* walk the pkt buffer list */
++		for (nskb = cskb; nskb; nskb = nskb->next) {
++
++			/* Increment the packet counter */
++			pktalloced++;
++
++			/* clean the 'prev' pointer
++			 * Kernel 3.18 is leaving skb->prev pointer set to skb
++			 * to indicate a non-fragmented skb
++			 */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
++			nskb->prev = NULL;
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) */
++
++
++#ifdef BCMDBG_CTRACE
++			ADD_CTRACE(osh, nskb, file, line);
++#endif /* BCMDBG_CTRACE */
++		}
++	}
++
++	/* Increment the packet counter */
++	atomic_add(pktalloced, &osh->cmn->pktalloced);
++
++	return (void *)pkt;
++}
++
++/* Return a new packet. zero out pkttag */
++void * BCMFASTPATH
++#ifdef BCMDBG_CTRACE
++osl_pktget(osl_t *osh, uint len, int line, char *file)
++#else
++#ifdef BCM_OBJECT_TRACE
++osl_pktget(osl_t *osh, uint len, int line, const char *caller)
++#else
++osl_pktget(osl_t *osh, uint len)
++#endif /* BCM_OBJECT_TRACE */
++#endif /* BCMDBG_CTRACE */
++{
++	struct sk_buff *skb;
++	uchar num = 0;
++	if (lmtest != FALSE) {
++		get_random_bytes(&num, sizeof(uchar));
++		if ((num + 1) <= (256 * lmtest / 100))
++			return NULL;
++	}
++
++#ifdef CTFPOOL
++	/* Allocate from local pool */
++	skb = osl_pktfastget(osh, len);
++	if ((skb != NULL) || ((skb = osl_alloc_skb(osh, len)) != NULL))
++#else /* CTFPOOL */
++	if ((skb = osl_alloc_skb(osh, len)))
++#endif /* CTFPOOL */
++	{
++		skb->tail += len;
++		skb->len  += len;
++		skb->priority = 0;
++
++#ifdef BCMDBG_CTRACE
++		ADD_CTRACE(osh, skb, file, line);
++#endif
++		atomic_inc(&osh->cmn->pktalloced);
++#ifdef BCM_OBJECT_TRACE
++		bcm_object_trace_opr(skb, BCM_OBJDBG_ADD_PKT, caller, line);
++#endif /* BCM_OBJECT_TRACE */
++	}
++
++	return ((void*) skb);
++}
++
++#ifdef CTFPOOL
++static inline void
++osl_pktfastfree(osl_t *osh, struct sk_buff *skb)
++{
++	ctfpool_t *ctfpool;
++#ifdef CTFPOOL_SPINLOCK
++	unsigned long flags;
++#endif /* CTFPOOL_SPINLOCK */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 14)
++	skb->tstamp.tv.sec = 0;
++#else
++	skb->stamp.tv_sec = 0;
++#endif
++
++	/* We only need to init the fields that we change */
++	skb->dev = NULL;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36)
++	skb->dst = NULL;
++#endif
++	OSL_PKTTAG_CLEAR(skb);
++	skb->ip_summed = 0;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
++	skb_orphan(skb);
++#else
++	skb->destructor = NULL;
++#endif
++
++	ctfpool = (ctfpool_t *)CTFPOOLPTR(osh, skb);
++	ASSERT(ctfpool != NULL);
++
++	/* if osh is a fwder osh, reset the fwder buf */
++	osl_fwderbuf_reset(ctfpool->osh, skb);
++
++	/* Add object to the ctfpool */
++	CTFPOOL_LOCK(ctfpool, flags);
++	skb->next = (struct sk_buff *)ctfpool->head;
++	ctfpool->head = (void *)skb;
++
++	ctfpool->fast_frees++;
++	ctfpool->curr_obj++;
++
++	ASSERT(ctfpool->curr_obj <= ctfpool->max_obj);
++	CTFPOOL_UNLOCK(ctfpool, flags);
++}
++#endif /* CTFPOOL */
++
++/* Free the driver packet. Free the tag if present */
++void BCMFASTPATH
++#ifdef BCM_OBJECT_TRACE
++osl_pktfree(osl_t *osh, void *p, bool send, int line, const char *caller)
++#else
++osl_pktfree(osl_t *osh, void *p, bool send)
++#endif /* BCM_OBJECT_TRACE */
++{
++	struct sk_buff *skb, *nskb;
++	if (osh == NULL)
++		return;
++
++	skb = (struct sk_buff*) p;
++
++	if (send && osh->pub.tx_fn)
++		osh->pub.tx_fn(osh->pub.tx_ctx, p, 0);
++
++	PKTDBG_TRACE(osh, (void *) skb, PKTLIST_PKTFREE);
++
++#if defined(CONFIG_DHD_USE_STATIC_BUF) && defined(DHD_USE_STATIC_CTRLBUF)
++	if (skb && (skb->mac_len == PREALLOC_USED_MAGIC)) {
++		printk("%s: pkt %p is from static pool\n",
++			__FUNCTION__, p);
++		dump_stack();
++		return;
++	}
++
++	if (skb && (skb->mac_len == PREALLOC_FREE_MAGIC)) {
++		printk("%s: pkt %p is from static pool and not in used\n",
++			__FUNCTION__, p);
++		dump_stack();
++		return;
++	}
++#endif /* CONFIG_DHD_USE_STATIC_BUF && DHD_USE_STATIC_CTRLBUF */
++
++	/* perversion: we use skb->next to chain multi-skb packets */
++	while (skb) {
++		nskb = skb->next;
++		skb->next = NULL;
++
++#ifdef BCMDBG_CTRACE
++		DEL_CTRACE(osh, skb);
++#endif
++
++
++#ifdef BCM_OBJECT_TRACE
++		bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE, caller, line);
++#endif /* BCM_OBJECT_TRACE */
++
++#ifdef CTFPOOL
++		if (PKTISFAST(osh, skb)) {
++			if (atomic_read(&skb->users) == 1)
++				smp_rmb();
++			else if (!atomic_dec_and_test(&skb->users))
++				goto next_skb;
++			osl_pktfastfree(osh, skb);
++		} else
++#endif
++		{
++			dev_kfree_skb_any(skb);
++		}
++#ifdef CTFPOOL
++next_skb:
++#endif
++		atomic_dec(&osh->cmn->pktalloced);
++		skb = nskb;
++	}
++}
++
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++void*
++osl_pktget_static(osl_t *osh, uint len)
++{
++	int i = 0;
++	struct sk_buff *skb;
++#ifdef DHD_USE_STATIC_CTRLBUF
++	unsigned long flags;
++#endif /* DHD_USE_STATIC_CTRLBUF */
++
++	if (!bcm_static_skb)
++		return osl_pktget(osh, len);
++
++	if (len > DHD_SKB_MAX_BUFSIZE) {
++		printk("%s: attempt to allocate huge packet (0x%x)\n", __FUNCTION__, len);
++		return osl_pktget(osh, len);
++	}
++
++#ifdef DHD_USE_STATIC_CTRLBUF
++	spin_lock_irqsave(&bcm_static_skb->osl_pkt_lock, flags);
++
++	if (len <= DHD_SKB_2PAGE_BUFSIZE) {
++		uint32 index;
++		for (i = 0; i < STATIC_PKT_2PAGE_NUM; i++) {
++			index = bcm_static_skb->last_allocated_index % STATIC_PKT_2PAGE_NUM;
++			bcm_static_skb->last_allocated_index++;
++			if (bcm_static_skb->skb_8k[index] &&
++				bcm_static_skb->pkt_use[index] == 0) {
++				break;
++			}
++		}
++
++		if ((i != STATIC_PKT_2PAGE_NUM) &&
++			(index >= 0) && (index < STATIC_PKT_2PAGE_NUM)) {
++			bcm_static_skb->pkt_use[index] = 1;
++			skb = bcm_static_skb->skb_8k[index];
++			skb->data = skb->head;
++#ifdef NET_SKBUFF_DATA_USES_OFFSET
++			skb_set_tail_pointer(skb, NET_SKB_PAD);
++#else
++			skb->tail = skb->data + NET_SKB_PAD;
++#endif /* NET_SKBUFF_DATA_USES_OFFSET */
++			skb->data += NET_SKB_PAD;
++			skb->cloned = 0;
++			skb->priority = 0;
++#ifdef NET_SKBUFF_DATA_USES_OFFSET
++			skb_set_tail_pointer(skb, len);
++#else
++			skb->tail = skb->data + len;
++#endif /* NET_SKBUFF_DATA_USES_OFFSET */
++			skb->len = len;
++			skb->mac_len = PREALLOC_USED_MAGIC;
++			spin_unlock_irqrestore(&bcm_static_skb->osl_pkt_lock, flags);
++			return skb;
++		}
++	}
++
++	spin_unlock_irqrestore(&bcm_static_skb->osl_pkt_lock, flags);
++	printk("%s: all static pkt in use!\n", __FUNCTION__);
++	return NULL;
++#else
++	down(&bcm_static_skb->osl_pkt_sem);
++
++	if (len <= DHD_SKB_1PAGE_BUFSIZE) {
++		for (i = 0; i < STATIC_PKT_1PAGE_NUM; i++) {
++			if (bcm_static_skb->skb_4k[i] &&
++				bcm_static_skb->pkt_use[i] == 0) {
++				break;
++			}
++		}
++
++		if (i != STATIC_PKT_1PAGE_NUM) {
++			bcm_static_skb->pkt_use[i] = 1;
++
++			skb = bcm_static_skb->skb_4k[i];
++#ifdef NET_SKBUFF_DATA_USES_OFFSET
++			skb_set_tail_pointer(skb, len);
++#else
++			skb->tail = skb->data + len;
++#endif /* NET_SKBUFF_DATA_USES_OFFSET */
++			skb->len = len;
++
++			up(&bcm_static_skb->osl_pkt_sem);
++			return skb;
++		}
++	}
++
++	if (len <= DHD_SKB_2PAGE_BUFSIZE) {
++		for (i = STATIC_PKT_1PAGE_NUM; i < STATIC_PKT_1_2PAGE_NUM; i++) {
++			if (bcm_static_skb->skb_8k[i - STATIC_PKT_1PAGE_NUM] &&
++				bcm_static_skb->pkt_use[i] == 0) {
++				break;
++			}
++		}
++
++		if ((i >= STATIC_PKT_1PAGE_NUM) && (i < STATIC_PKT_1_2PAGE_NUM)) {
++			bcm_static_skb->pkt_use[i] = 1;
++			skb = bcm_static_skb->skb_8k[i - STATIC_PKT_1PAGE_NUM];
++#ifdef NET_SKBUFF_DATA_USES_OFFSET
++			skb_set_tail_pointer(skb, len);
++#else
++			skb->tail = skb->data + len;
++#endif /* NET_SKBUFF_DATA_USES_OFFSET */
++			skb->len = len;
++
++			up(&bcm_static_skb->osl_pkt_sem);
++			return skb;
++		}
++	}
++
++#if defined(ENHANCED_STATIC_BUF)
++	if (bcm_static_skb->skb_16k &&
++		bcm_static_skb->pkt_use[STATIC_PKT_MAX_NUM - 1] == 0) {
++		bcm_static_skb->pkt_use[STATIC_PKT_MAX_NUM - 1] = 1;
++
++		skb = bcm_static_skb->skb_16k;
++#ifdef NET_SKBUFF_DATA_USES_OFFSET
++		skb_set_tail_pointer(skb, len);
++#else
++		skb->tail = skb->data + len;
++#endif /* NET_SKBUFF_DATA_USES_OFFSET */
++		skb->len = len;
++
++		up(&bcm_static_skb->osl_pkt_sem);
++		return skb;
++	}
++#endif /* ENHANCED_STATIC_BUF */
++
++	up(&bcm_static_skb->osl_pkt_sem);
++	printk("%s: all static pkt in use!\n", __FUNCTION__);
++	return osl_pktget(osh, len);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++}
++
++void
++osl_pktfree_static(osl_t *osh, void *p, bool send)
++{
++	int i;
++#ifdef DHD_USE_STATIC_CTRLBUF
++	struct sk_buff *skb = (struct sk_buff *)p;
++	unsigned long flags;
++#endif /* DHD_USE_STATIC_CTRLBUF */
++
++	if (!p) {
++		return;
++	}
++
++	if (!bcm_static_skb) {
++		osl_pktfree(osh, p, send);
++		return;
++	}
++
++#ifdef DHD_USE_STATIC_CTRLBUF
++	spin_lock_irqsave(&bcm_static_skb->osl_pkt_lock, flags);
++
++	for (i = 0; i < STATIC_PKT_2PAGE_NUM; i++) {
++		if (p == bcm_static_skb->skb_8k[i]) {
++			if (bcm_static_skb->pkt_use[i] == 0) {
++				printk("%s: static pkt idx %d(%p) is double free\n",
++					__FUNCTION__, i, p);
++			} else {
++				bcm_static_skb->pkt_use[i] = 0;
++			}
++
++			if (skb->mac_len != PREALLOC_USED_MAGIC) {
++				printk("%s: static pkt idx %d(%p) is not in used\n",
++					__FUNCTION__, i, p);
++			}
++
++			skb->mac_len = PREALLOC_FREE_MAGIC;
++			spin_unlock_irqrestore(&bcm_static_skb->osl_pkt_lock, flags);
++			return;
++		}
++	}
++
++	spin_unlock_irqrestore(&bcm_static_skb->osl_pkt_lock, flags);
++	printk("%s: packet %p does not exist in the pool\n", __FUNCTION__, p);
++#else
++	down(&bcm_static_skb->osl_pkt_sem);
++	for (i = 0; i < STATIC_PKT_1PAGE_NUM; i++) {
++		if (p == bcm_static_skb->skb_4k[i]) {
++			bcm_static_skb->pkt_use[i] = 0;
++			up(&bcm_static_skb->osl_pkt_sem);
++			return;
++		}
++	}
++
++	for (i = STATIC_PKT_1PAGE_NUM; i < STATIC_PKT_1_2PAGE_NUM; i++) {
++		if (p == bcm_static_skb->skb_8k[i - STATIC_PKT_1PAGE_NUM]) {
++			bcm_static_skb->pkt_use[i] = 0;
++			up(&bcm_static_skb->osl_pkt_sem);
++			return;
++		}
++	}
++#ifdef ENHANCED_STATIC_BUF
++	if (p == bcm_static_skb->skb_16k) {
++		bcm_static_skb->pkt_use[STATIC_PKT_MAX_NUM - 1] = 0;
++		up(&bcm_static_skb->osl_pkt_sem);
++		return;
++	}
++#endif
++	up(&bcm_static_skb->osl_pkt_sem);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++	osl_pktfree(osh, p, send);
++}
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++
++uint32
++osl_pci_read_config(osl_t *osh, uint offset, uint size)
++{
++	uint val = 0;
++	uint retry = PCI_CFG_RETRY;
++
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++	/* only 4byte access supported */
++	ASSERT(size == 4);
++
++	do {
++		pci_read_config_dword(osh->pdev, offset, &val);
++		if (val != 0xffffffff)
++			break;
++	} while (retry--);
++
++
++	return (val);
++}
++
++void
++osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
++{
++	uint retry = PCI_CFG_RETRY;
++
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++	/* only 4byte access supported */
++	ASSERT(size == 4);
++
++	do {
++		pci_write_config_dword(osh->pdev, offset, val);
++		if (offset != PCI_BAR0_WIN)
++			break;
++		if (osl_pci_read_config(osh, offset, size) == val)
++			break;
++	} while (retry--);
++
++}
++
++/* return bus # for the pci device pointed by osh->pdev */
++uint
++osl_pci_bus(osl_t *osh)
++{
++	ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
++
++#if defined(__ARM_ARCH_7A__) && LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)
++	return pci_domain_nr(((struct pci_dev *)osh->pdev)->bus);
++#else
++	return ((struct pci_dev *)osh->pdev)->bus->number;
++#endif
++}
++
++/* return slot # for the pci device pointed by osh->pdev */
++uint
++osl_pci_slot(osl_t *osh)
++{
++	ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
++
++#if defined(__ARM_ARCH_7A__) && LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)
++	return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn) + 1;
++#else
++	return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
++#endif
++}
++
++/* return domain # for the pci device pointed by osh->pdev */
++uint
++osl_pcie_domain(osl_t *osh)
++{
++	ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
++
++	return pci_domain_nr(((struct pci_dev *)osh->pdev)->bus);
++}
++
++/* return bus # for the pci device pointed by osh->pdev */
++uint
++osl_pcie_bus(osl_t *osh)
++{
++	ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
++
++	return ((struct pci_dev *)osh->pdev)->bus->number;
++}
++
++/* return the pci device pointed by osh->pdev */
++struct pci_dev *
++osl_pci_device(osl_t *osh)
++{
++	ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
++
++	return osh->pdev;
++}
++
++static void
++osl_pcmcia_attr(osl_t *osh, uint offset, char *buf, int size, bool write)
++{
++}
++
++void
++osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size)
++{
++	osl_pcmcia_attr(osh, offset, (char *) buf, size, FALSE);
++}
++
++void
++osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size)
++{
++	osl_pcmcia_attr(osh, offset, (char *) buf, size, TRUE);
++}
++
++void *
++osl_malloc(osl_t *osh, uint size)
++{
++	void *addr;
++	gfp_t flags;
++
++	/* only ASSERT if osh is defined */
++	if (osh)
++		ASSERT(osh->magic == OS_HANDLE_MAGIC);
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++	if (bcm_static_buf)
++	{
++		unsigned long irq_flags;
++		int i = 0;
++		if ((size >= PAGE_SIZE)&&(size <= STATIC_BUF_SIZE))
++		{
++			spin_lock_irqsave(&bcm_static_buf->static_lock, irq_flags);
++
++			for (i = 0; i < STATIC_BUF_MAX_NUM; i++)
++			{
++				if (bcm_static_buf->buf_use[i] == 0)
++					break;
++			}
++
++			if (i == STATIC_BUF_MAX_NUM)
++			{
++				spin_unlock_irqrestore(&bcm_static_buf->static_lock, irq_flags);
++				printk("all static buff in use!\n");
++				goto original;
++			}
++
++			bcm_static_buf->buf_use[i] = 1;
++			spin_unlock_irqrestore(&bcm_static_buf->static_lock, irq_flags);
++
++			bzero(bcm_static_buf->buf_ptr+STATIC_BUF_SIZE*i, size);
++			if (osh)
++				atomic_add(size, &osh->cmn->malloced);
++
++			return ((void *)(bcm_static_buf->buf_ptr+STATIC_BUF_SIZE*i));
++		}
++	}
++original:
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++
++	flags = CAN_SLEEP() ? GFP_KERNEL: GFP_ATOMIC;
++	if ((addr = kmalloc(size, flags)) == NULL) {
++		if (osh)
++			osh->failed++;
++		return (NULL);
++	}
++	if (osh && osh->cmn)
++		atomic_add(size, &osh->cmn->malloced);
++
++	return (addr);
++}
++
++void *
++osl_mallocz(osl_t *osh, uint size)
++{
++	void *ptr;
++
++	ptr = osl_malloc(osh, size);
++
++	if (ptr != NULL) {
++		bzero(ptr, size);
++	}
++
++	return ptr;
++}
++
++void
++osl_mfree(osl_t *osh, void *addr, uint size)
++{
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++	unsigned long flags;
++
++	if (bcm_static_buf)
++	{
++		if ((addr > (void *)bcm_static_buf) && ((unsigned char *)addr
++			<= ((unsigned char *)bcm_static_buf + STATIC_BUF_TOTAL_LEN)))
++		{
++			int buf_idx = 0;
++
++			buf_idx = ((unsigned char *)addr - bcm_static_buf->buf_ptr)/STATIC_BUF_SIZE;
++
++			spin_lock_irqsave(&bcm_static_buf->static_lock, flags);
++			bcm_static_buf->buf_use[buf_idx] = 0;
++			spin_unlock_irqrestore(&bcm_static_buf->static_lock, flags);
++
++			if (osh && osh->cmn) {
++				ASSERT(osh->magic == OS_HANDLE_MAGIC);
++				atomic_sub(size, &osh->cmn->malloced);
++			}
++			return;
++		}
++	}
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++	if (osh && osh->cmn) {
++		ASSERT(osh->magic == OS_HANDLE_MAGIC);
++
++		ASSERT(size <= osl_malloced(osh));
++
++		atomic_sub(size, &osh->cmn->malloced);
++	}
++	kfree(addr);
++}
++
++void *
++osl_vmalloc(osl_t *osh, uint size)
++{
++	void *addr;
++
++	/* only ASSERT if osh is defined */
++	if (osh)
++		ASSERT(osh->magic == OS_HANDLE_MAGIC);
++	if ((addr = vmalloc(size)) == NULL) {
++		if (osh)
++			osh->failed++;
++		return (NULL);
++	}
++	if (osh && osh->cmn)
++		atomic_add(size, &osh->cmn->malloced);
++
++	return (addr);
++}
++
++void *
++osl_vmallocz(osl_t *osh, uint size)
++{
++	void *ptr;
++
++	ptr = osl_vmalloc(osh, size);
++
++	if (ptr != NULL) {
++		bzero(ptr, size);
++	}
++
++	return ptr;
++}
++
++void
++osl_vmfree(osl_t *osh, void *addr, uint size)
++{
++	if (osh && osh->cmn) {
++		ASSERT(osh->magic == OS_HANDLE_MAGIC);
++
++		ASSERT(size <= osl_malloced(osh));
++
++		atomic_sub(size, &osh->cmn->malloced);
++	}
++	vfree(addr);
++}
++
++uint
++osl_check_memleak(osl_t *osh)
++{
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++	if (atomic_read(&osh->cmn->refcount) == 1)
++		return (atomic_read(&osh->cmn->malloced));
++	else
++		return 0;
++}
++
++uint
++osl_malloced(osl_t *osh)
++{
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++	return (atomic_read(&osh->cmn->malloced));
++}
++
++uint
++osl_malloc_failed(osl_t *osh)
++{
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++	return (osh->failed);
++}
++
++
++uint
++osl_dma_consistent_align(void)
++{
++	return (PAGE_SIZE);
++}
++
++void*
++osl_dma_alloc_consistent(osl_t *osh, uint size, uint16 align_bits, uint *alloced, dmaaddr_t *pap)
++{
++	void *va;
++	uint16 align = (1 << align_bits);
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++	if (!ISALIGNED(DMA_CONSISTENT_ALIGN, align))
++		size += align;
++	*alloced = size;
++
++#ifndef	BCM_SECURE_DMA
++#if defined(__ARM_ARCH_7A__) && !defined(DHD_USE_COHERENT_MEM_FOR_RING)
++	va = kmalloc(size, GFP_ATOMIC | __GFP_ZERO);
++	if (va)
++		*pap = (ulong)__virt_to_phys((ulong)va);
++#else
++	{
++		dma_addr_t pap_lin;
++		struct pci_dev *hwdev = osh->pdev;
++		gfp_t flags;
++#ifdef DHD_ALLOC_COHERENT_MEM_FROM_ATOMIC_POOL
++		flags = GFP_ATOMIC;
++#else
++		flags = CAN_SLEEP() ? GFP_KERNEL: GFP_ATOMIC;
++#endif /* DHD_ALLOC_COHERENT_MEM_FROM_ATOMIC_POOL */
++		va = dma_alloc_coherent(&hwdev->dev, size, &pap_lin, flags);
++#ifdef BCMDMA64OSL
++		PHYSADDRLOSET(*pap, pap_lin & 0xffffffff);
++		PHYSADDRHISET(*pap, (pap_lin >> 32) & 0xffffffff);
++#else
++		*pap = (dmaaddr_t)pap_lin;
++#endif /* BCMDMA64OSL */
++	}
++#endif /* __ARM_ARCH_7A__ && !DHD_USE_COHERENT_MEM_FOR_RING */
++#else
++	va = osl_sec_dma_alloc_consistent(osh, size, align_bits, pap);
++#endif /* BCM_SECURE_DMA */
++	return va;
++}
++
++void
++osl_dma_free_consistent(osl_t *osh, void *va, uint size, dmaaddr_t pa)
++{
++#ifdef BCMDMA64OSL
++	dma_addr_t paddr;
++#endif /* BCMDMA64OSL */
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++#ifndef BCM_SECURE_DMA
++#if defined(__ARM_ARCH_7A__) && !defined(DHD_USE_COHERENT_MEM_FOR_RING)
++	kfree(va);
++#else
++#ifdef BCMDMA64OSL
++	PHYSADDRTOULONG(pa, paddr);
++	pci_free_consistent(osh->pdev, size, va, paddr);
++#else
++	pci_free_consistent(osh->pdev, size, va, (dma_addr_t)pa);
++#endif /* BCMDMA64OSL */
++#endif /* __ARM_ARCH_7A__ && !DHD_USE_COHERENT_MEM_FOR_RING */
++#else
++	osl_sec_dma_free_consistent(osh, va, size, pa);
++#endif /* BCM_SECURE_DMA */
++}
++
++dmaaddr_t BCMFASTPATH
++osl_dma_map(osl_t *osh, void *va, uint size, int direction, void *p, hnddma_seg_map_t *dmah)
++{
++	int dir;
++	dmaaddr_t ret_addr;
++	dma_addr_t map_addr;
++	int ret;
++
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++	dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
++
++
++
++
++	map_addr = pci_map_single(osh->pdev, va, size, dir);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++	ret = pci_dma_mapping_error(osh->pdev, map_addr);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 5))
++	ret = pci_dma_mapping_error(map_addr);
++#else
++	ret = 0;
++#endif
++	if (ret) {
++		printk("%s: Failed to map memory\n", __FUNCTION__);
++		PHYSADDRLOSET(ret_addr, 0);
++		PHYSADDRHISET(ret_addr, 0);
++	} else {
++		PHYSADDRLOSET(ret_addr, map_addr & 0xffffffff);
++		PHYSADDRHISET(ret_addr, (map_addr >> 32) & 0xffffffff);
++	}
++
++	return ret_addr;
++}
++
++void BCMFASTPATH
++osl_dma_unmap(osl_t *osh, dmaaddr_t pa, uint size, int direction)
++{
++	int dir;
++#ifdef BCMDMA64OSL
++	dma_addr_t paddr;
++#endif /* BCMDMA64OSL */
++
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++
++	dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
++#ifdef BCMDMA64OSL
++	PHYSADDRTOULONG(pa, paddr);
++	pci_unmap_single(osh->pdev, paddr, size, dir);
++#else
++	pci_unmap_single(osh->pdev, (uint32)pa, size, dir);
++#endif /* BCMDMA64OSL */
++}
++
++/* OSL function for CPU relax */
++inline void BCMFASTPATH
++osl_cpu_relax(void)
++{
++	cpu_relax();
++}
++
++extern void osl_preempt_disable(osl_t *osh)
++{
++	preempt_disable();
++}
++
++extern void osl_preempt_enable(osl_t *osh)
++{
++	preempt_enable();
++}
++
++#if defined(BCMASSERT_LOG)
++void
++osl_assert(const char *exp, const char *file, int line)
++{
++	char tempbuf[256];
++	const char *basename;
++
++	basename = strrchr(file, '/');
++	/* skip the '/' */
++	if (basename)
++		basename++;
++
++	if (!basename)
++		basename = file;
++
++#ifdef BCMASSERT_LOG
++	snprintf(tempbuf, 64, "\"%s\": file \"%s\", line %d\n",
++		exp, basename, line);
++#endif /* BCMASSERT_LOG */
++
++
++	switch (g_assert_type) {
++	case 0:
++		panic("%s", tempbuf);
++		break;
++	case 1:
++		/* fall through */
++	case 3:
++		printk("%s", tempbuf);
++		break;
++	case 2:
++		printk("%s", tempbuf);
++		BUG();
++		break;
++	default:
++		break;
++	}
++}
++#endif 
++
++void
++osl_delay(uint usec)
++{
++	uint d;
++
++	while (usec > 0) {
++		d = MIN(usec, 1000);
++		udelay(d);
++		usec -= d;
++	}
++}
++
++void
++osl_sleep(uint ms)
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
++	if (ms < 20)
++		usleep_range(ms*1000, ms*1000 + 1000);
++	else
++#endif
++	msleep(ms);
++}
++
++uint64
++osl_sysuptime_us(void)
++{
++	struct osl_timespec tv;
++	uint64 usec;
++
++	osl_do_gettimeofday(&tv);
++	/* tv_usec content is fraction of a second */
++	usec = (uint64)tv.tv_sec * 1000000ul + tv.tv_usec;
++	return usec;
++}
++
++
++/* Clone a packet.
++ * The pkttag contents are NOT cloned.
++ */
++void *
++#ifdef BCMDBG_CTRACE
++osl_pktdup(osl_t *osh, void *skb, int line, char *file)
++#else
++#ifdef BCM_OBJECT_TRACE
++osl_pktdup(osl_t *osh, void *skb, int line, const char *caller)
++#else
++osl_pktdup(osl_t *osh, void *skb)
++#endif /* BCM_OBJECT_TRACE */
++#endif /* BCMDBG_CTRACE */
++{
++	void * p;
++
++	ASSERT(!PKTISCHAINED(skb));
++
++	/* clear the CTFBUF flag if set and map the rest of the buffer
++	 * before cloning.
++	 */
++	PKTCTFMAP(osh, skb);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
++	if ((p = pskb_copy((struct sk_buff *)skb, GFP_ATOMIC)) == NULL)
++#else
++	if ((p = skb_clone((struct sk_buff *)skb, GFP_ATOMIC)) == NULL)
++#endif
++		return NULL;
++
++#ifdef CTFPOOL
++	if (PKTISFAST(osh, skb)) {
++		ctfpool_t *ctfpool;
++
++		/* if the buffer allocated from ctfpool is cloned then
++		 * we can't be sure when it will be freed. since there
++		 * is a chance that we will be losing a buffer
++		 * from our pool, we increment the refill count for the
++		 * object to be alloced later.
++		 */
++		ctfpool = (ctfpool_t *)CTFPOOLPTR(osh, skb);
++		ASSERT(ctfpool != NULL);
++		PKTCLRFAST(osh, p);
++		PKTCLRFAST(osh, skb);
++		ctfpool->refills++;
++	}
++#endif /* CTFPOOL */
++
++	/* Clear PKTC  context */
++	PKTSETCLINK(p, NULL);
++	PKTCCLRFLAGS(p);
++	PKTCSETCNT(p, 1);
++	PKTCSETLEN(p, PKTLEN(osh, skb));
++
++	/* skb_clone copies skb->cb.. we don't want that */
++	if (osh->pub.pkttag)
++		OSL_PKTTAG_CLEAR(p);
++
++	/* Increment the packet counter */
++	atomic_inc(&osh->cmn->pktalloced);
++#ifdef BCM_OBJECT_TRACE
++	bcm_object_trace_opr(p, BCM_OBJDBG_ADD_PKT, caller, line);
++#endif /* BCM_OBJECT_TRACE */
++
++#ifdef BCMDBG_CTRACE
++	ADD_CTRACE(osh, (struct sk_buff *)p, file, line);
++#endif
++	return (p);
++}
++
++#ifdef BCMDBG_CTRACE
++int osl_pkt_is_frmnative(osl_t *osh, struct sk_buff *pkt)
++{
++	unsigned long flags;
++	struct sk_buff *skb;
++	int ck = FALSE;
++
++	spin_lock_irqsave(&osh->ctrace_lock, flags);
++
++	list_for_each_entry(skb, &osh->ctrace_list, ctrace_list) {
++		if (pkt == skb) {
++			ck = TRUE;
++			break;
++		}
++	}
++
++	spin_unlock_irqrestore(&osh->ctrace_lock, flags);
++	return ck;
++}
++
++void osl_ctrace_dump(osl_t *osh, struct bcmstrbuf *b)
++{
++	unsigned long flags;
++	struct sk_buff *skb;
++	int idx = 0;
++	int i, j;
++
++	spin_lock_irqsave(&osh->ctrace_lock, flags);
++
++	if (b != NULL)
++		bcm_bprintf(b, " Total %d sbk not free\n", osh->ctrace_num);
++	else
++		printk(" Total %d sbk not free\n", osh->ctrace_num);
++
++	list_for_each_entry(skb, &osh->ctrace_list, ctrace_list) {
++		if (b != NULL)
++			bcm_bprintf(b, "[%d] skb %p:\n", ++idx, skb);
++		else
++			printk("[%d] skb %p:\n", ++idx, skb);
++
++		for (i = 0; i < skb->ctrace_count; i++) {
++			j = (skb->ctrace_start + i) % CTRACE_NUM;
++			if (b != NULL)
++				bcm_bprintf(b, "    [%s(%d)]\n", skb->func[j], skb->line[j]);
++			else
++				printk("    [%s(%d)]\n", skb->func[j], skb->line[j]);
++		}
++		if (b != NULL)
++			bcm_bprintf(b, "\n");
++		else
++			printk("\n");
++	}
++
++	spin_unlock_irqrestore(&osh->ctrace_lock, flags);
++
++	return;
++}
++#endif /* BCMDBG_CTRACE */
++
++
++/*
++ * OSLREGOPS specifies the use of osl_XXX routines to be used for register access
++ */
++
++/*
++ * BINOSL selects the slightly slower function-call-based binary compatible osl.
++ */
++
++uint
++osl_pktalloced(osl_t *osh)
++{
++	if (atomic_read(&osh->cmn->refcount) == 1)
++		return (atomic_read(&osh->cmn->pktalloced));
++	else
++		return 0;
++}
++
++uint32
++osl_rand(void)
++{
++	uint32 rand;
++
++	get_random_bytes(&rand, sizeof(rand));
++
++	return rand;
++}
++
++/* Linux Kernel: File Operations: start */
++void *
++osl_os_open_image(char *filename)
++{
++	struct file *fp;
++
++	fp = filp_open(filename, O_RDONLY, 0);
++	/*
++	 * 2.6.11 (FC4) supports filp_open() but later revs don't?
++	 * Alternative:
++	 * fp = open_namei(AT_FDCWD, filename, O_RD, 0);
++	 * ???
++	 */
++	 if (IS_ERR(fp))
++		 fp = NULL;
++
++	 return fp;
++}
++
++int
++osl_os_get_image_block(char *buf, int len, void *image)
++{
++	struct file *fp = (struct file *)image;
++	int rdlen;
++
++	if (!image)
++		return 0;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++	rdlen = kernel_read(fp, buf, len, &fp->f_pos);
++#else
++	rdlen = kernel_read(fp, fp->f_pos, buf, len);
++	if (rdlen > 0)
++		fp->f_pos += rdlen;
++#endif
++
++	return rdlen;
++}
++
++void
++osl_os_close_image(void *image)
++{
++	if (image)
++		filp_close((struct file *)image, NULL);
++}
++
++int
++osl_os_image_size(void *image)
++{
++	int len = 0, curroffset;
++
++	if (image) {
++		/* store the current offset */
++		curroffset = generic_file_llseek(image, 0, 1);
++		/* goto end of file to get length */
++		len = generic_file_llseek(image, 0, 2);
++		/* restore back the offset */
++		generic_file_llseek(image, curroffset, 0);
++	}
++	return len;
++}
++
++/* Linux Kernel: File Operations: end */
++
++#if (defined(STB) && defined(__arm__))
++inline void osl_pcie_rreg(osl_t *osh, ulong addr, void *v, uint size)
++{
++	unsigned long flags = 0;
++	int pci_access = 0;
++#if defined(BCM_GMAC3)
++	const int acp_war_enab = 1;
++#else  /* !BCM_GMAC3 */
++	int acp_war_enab = ACP_WAR_ENAB();
++#endif /* !BCM_GMAC3 */
++
++	if (osh && BUSTYPE(osh->bustype) == PCI_BUS)
++		pci_access = 1;
++
++	if (pci_access && acp_war_enab)
++		spin_lock_irqsave(&l2x0_reg_lock, flags);
++
++	switch (size) {
++	case sizeof(uint8):
++		*(uint8*)v = readb((volatile uint8*)(addr));
++		break;
++	case sizeof(uint16):
++		*(uint16*)v = readw((volatile uint16*)(addr));
++		break;
++	case sizeof(uint32):
++		*(uint32*)v = readl((volatile uint32*)(addr));
++		break;
++	case sizeof(uint64):
++		*(uint64*)v = *((volatile uint64*)(addr));
++		break;
++	}
++
++	if (pci_access && acp_war_enab)
++		spin_unlock_irqrestore(&l2x0_reg_lock, flags);
++}
++#endif 
++
++#ifdef BCM_SECURE_DMA
++static void *
++osl_sec_dma_ioremap(osl_t *osh, struct page *page, size_t size, bool iscache, bool isdecr)
++{
++
++	struct page **map;
++	int order, i;
++	void *addr = NULL;
++
++	size = PAGE_ALIGN(size);
++	order = get_order(size);
++
++	map = kmalloc(sizeof(struct page *) << order, GFP_ATOMIC);
++
++	if (map == NULL)
++		return NULL;
++
++	for (i = 0; i < (size >> PAGE_SHIFT); i++)
++		map[i] = page + i;
++
++	if (iscache) {
++		addr = vmap(map, size >> PAGE_SHIFT, VM_MAP, __pgprot(PAGE_KERNEL));
++		if (isdecr) {
++			osh->contig_delta_va_pa = ((uint8 *)addr - page_to_phys(page));
++		}
++	} else {
++
++#if defined(__ARM_ARCH_7A__)
++		addr = vmap(map, size >> PAGE_SHIFT, VM_MAP,
++			pgprot_noncached(__pgprot(PAGE_KERNEL)));
++#endif
++		if (isdecr) {
++			osh->contig_delta_va_pa = ((uint8 *)addr - page_to_phys(page));
++		}
++	}
++
++	kfree(map);
++	return (void *)addr;
++}
++
++static void
++osl_sec_dma_iounmap(osl_t *osh, void *contig_base_va, size_t size)
++{
++	vunmap(contig_base_va);
++}
++
++static int
++osl_sec_dma_init_elem_mem_block(osl_t *osh, size_t mbsize, int max, sec_mem_elem_t **list)
++{
++	int i;
++	int ret = BCME_OK;
++	sec_mem_elem_t *sec_mem_elem;
++
++	if ((sec_mem_elem = kmalloc(sizeof(sec_mem_elem_t)*(max), GFP_ATOMIC)) != NULL) {
++
++		*list = sec_mem_elem;
++		bzero(sec_mem_elem, sizeof(sec_mem_elem_t)*(max));
++		for (i = 0; i < max-1; i++) {
++			sec_mem_elem->next = (sec_mem_elem + 1);
++			sec_mem_elem->size = mbsize;
++			sec_mem_elem->pa_cma = osh->contig_base_alloc;
++			sec_mem_elem->vac = osh->contig_base_alloc_va;
++
++			sec_mem_elem->pa_cma_page = phys_to_page(sec_mem_elem->pa_cma);
++			osh->contig_base_alloc += mbsize;
++			osh->contig_base_alloc_va = ((uint8 *)osh->contig_base_alloc_va +  mbsize);
++
++			sec_mem_elem = sec_mem_elem + 1;
++		}
++		sec_mem_elem->next = NULL;
++		sec_mem_elem->size = mbsize;
++		sec_mem_elem->pa_cma = osh->contig_base_alloc;
++		sec_mem_elem->vac = osh->contig_base_alloc_va;
++
++		sec_mem_elem->pa_cma_page = phys_to_page(sec_mem_elem->pa_cma);
++		osh->contig_base_alloc += mbsize;
++		osh->contig_base_alloc_va = ((uint8 *)osh->contig_base_alloc_va +  mbsize);
++
++	} else {
++		printf("%s sec mem elem kmalloc failed\n", __FUNCTION__);
++		ret = BCME_ERROR;
++	}
++	return ret;
++}
++
++
++static void
++osl_sec_dma_deinit_elem_mem_block(osl_t *osh, size_t mbsize, int max, void *sec_list_base)
++{
++	if (sec_list_base)
++		kfree(sec_list_base);
++}
++
++static sec_mem_elem_t * BCMFASTPATH
++osl_sec_dma_alloc_mem_elem(osl_t *osh, void *va, uint size, int direction,
++	struct sec_cma_info *ptr_cma_info, uint offset)
++{
++	sec_mem_elem_t *sec_mem_elem = NULL;
++
++		ASSERT(osh->sec_list_4096);
++		sec_mem_elem = osh->sec_list_4096;
++		osh->sec_list_4096 = sec_mem_elem->next;
++
++		sec_mem_elem->next = NULL;
++
++	if (ptr_cma_info->sec_alloc_list_tail) {
++		ptr_cma_info->sec_alloc_list_tail->next = sec_mem_elem;
++		ptr_cma_info->sec_alloc_list_tail = sec_mem_elem;
++	}
++	else {
++		/* First allocation: If tail is NULL, sec_alloc_list MUST also be NULL */
++		ASSERT(ptr_cma_info->sec_alloc_list == NULL);
++		ptr_cma_info->sec_alloc_list = sec_mem_elem;
++		ptr_cma_info->sec_alloc_list_tail = sec_mem_elem;
++	}
++	return sec_mem_elem;
++}
++
++static void BCMFASTPATH
++osl_sec_dma_free_mem_elem(osl_t *osh, sec_mem_elem_t *sec_mem_elem)
++{
++	sec_mem_elem->dma_handle = 0x0;
++	sec_mem_elem->va = NULL;
++		sec_mem_elem->next = osh->sec_list_4096;
++		osh->sec_list_4096 = sec_mem_elem;
++}
++
++static sec_mem_elem_t * BCMFASTPATH
++osl_sec_dma_find_rem_elem(osl_t *osh, struct sec_cma_info *ptr_cma_info, dma_addr_t dma_handle)
++{
++	sec_mem_elem_t *sec_mem_elem = ptr_cma_info->sec_alloc_list;
++	sec_mem_elem_t *sec_prv_elem = ptr_cma_info->sec_alloc_list;
++
++	if (sec_mem_elem->dma_handle == dma_handle) {
++
++		ptr_cma_info->sec_alloc_list = sec_mem_elem->next;
++
++		if (sec_mem_elem == ptr_cma_info->sec_alloc_list_tail) {
++			ptr_cma_info->sec_alloc_list_tail = NULL;
++			ASSERT(ptr_cma_info->sec_alloc_list == NULL);
++		}
++
++		return sec_mem_elem;
++	}
++	sec_mem_elem = sec_mem_elem->next;
++
++	while (sec_mem_elem != NULL) {
++
++		if (sec_mem_elem->dma_handle == dma_handle) {
++
++			sec_prv_elem->next = sec_mem_elem->next;
++			if (sec_mem_elem == ptr_cma_info->sec_alloc_list_tail)
++				ptr_cma_info->sec_alloc_list_tail = sec_prv_elem;
++
++			return sec_mem_elem;
++		}
++		sec_prv_elem = sec_mem_elem;
++		sec_mem_elem = sec_mem_elem->next;
++	}
++	return NULL;
++}
++
++static sec_mem_elem_t *
++osl_sec_dma_rem_first_elem(osl_t *osh, struct sec_cma_info *ptr_cma_info)
++{
++	sec_mem_elem_t *sec_mem_elem = ptr_cma_info->sec_alloc_list;
++
++	if (sec_mem_elem) {
++
++		ptr_cma_info->sec_alloc_list = sec_mem_elem->next;
++
++		if (ptr_cma_info->sec_alloc_list == NULL)
++			ptr_cma_info->sec_alloc_list_tail = NULL;
++
++		return sec_mem_elem;
++
++	} else
++		return NULL;
++}
++
++static void * BCMFASTPATH
++osl_sec_dma_last_elem(osl_t *osh, struct sec_cma_info *ptr_cma_info)
++{
++	return ptr_cma_info->sec_alloc_list_tail;
++}
++
++dma_addr_t BCMFASTPATH
++osl_sec_dma_map_txmeta(osl_t *osh, void *va, uint size, int direction, void *p,
++	hnddma_seg_map_t *dmah, void *ptr_cma_info)
++{
++	sec_mem_elem_t *sec_mem_elem;
++	struct page *pa_cma_page;
++	uint loffset;
++	void *vaorig = ((uint8 *)va + size);
++	dma_addr_t dma_handle = 0x0;
++	/* packet will be the one added with osl_sec_dma_map() just before this call */
++
++	sec_mem_elem = osl_sec_dma_last_elem(osh, ptr_cma_info);
++
++	if (sec_mem_elem && sec_mem_elem->va == vaorig) {
++
++		pa_cma_page = phys_to_page(sec_mem_elem->pa_cma);
++		loffset = sec_mem_elem->pa_cma -(sec_mem_elem->pa_cma & ~(PAGE_SIZE-1));
++
++		dma_handle = dma_map_page(OSH_NULL, pa_cma_page, loffset, size,
++			(direction == DMA_TX ? DMA_TO_DEVICE:DMA_FROM_DEVICE));
++
++	} else {
++		printf("%s: error orig va not found va = 0x%p \n",
++			__FUNCTION__, vaorig);
++	}
++	return dma_handle;
++}
++
++dma_addr_t BCMFASTPATH
++osl_sec_dma_map(osl_t *osh, void *va, uint size, int direction, void *p,
++	hnddma_seg_map_t *dmah, void *ptr_cma_info, uint offset)
++{
++
++	sec_mem_elem_t *sec_mem_elem;
++	struct page *pa_cma_page;
++	void *pa_cma_kmap_va = NULL;
++	uint buflen = 0;
++	dma_addr_t dma_handle = 0x0;
++	uint loffset;
++
++	ASSERT((direction == DMA_RX) || (direction == DMA_TX));
++	sec_mem_elem = osl_sec_dma_alloc_mem_elem(osh, va, size, direction, ptr_cma_info, offset);
++
++	sec_mem_elem->va = va;
++	sec_mem_elem->direction = direction;
++	pa_cma_page = sec_mem_elem->pa_cma_page;
++
++	loffset = sec_mem_elem->pa_cma -(sec_mem_elem->pa_cma & ~(PAGE_SIZE-1));
++	/* pa_cma_kmap_va = kmap_atomic(pa_cma_page);
++	* pa_cma_kmap_va += loffset;
++	*/
++
++	pa_cma_kmap_va = sec_mem_elem->vac;
++	pa_cma_kmap_va = ((uint8 *)pa_cma_kmap_va + offset);
++	buflen = size;
++
++	if (direction == DMA_TX) {
++		memcpy((uint8*)pa_cma_kmap_va+offset, va, size);
++
++		if (dmah) {
++			dmah->nsegs = 1;
++			dmah->origsize = buflen;
++		}
++	}
++	else
++	{
++		if ((p != NULL) && (dmah != NULL)) {
++			dmah->nsegs = 1;
++			dmah->origsize = buflen;
++		}
++		*(uint32 *)(pa_cma_kmap_va) = 0x0;
++	}
++
++	if (direction == DMA_RX) {
++		flush_kernel_vmap_range(pa_cma_kmap_va, sizeof(int));
++	}
++		dma_handle = dma_map_page(OSH_NULL, pa_cma_page, loffset+offset, buflen,
++			(direction == DMA_TX ? DMA_TO_DEVICE:DMA_FROM_DEVICE));
++	if (dmah) {
++		dmah->segs[0].addr = dma_handle;
++		dmah->segs[0].length = buflen;
++	}
++	sec_mem_elem->dma_handle = dma_handle;
++	/* kunmap_atomic(pa_cma_kmap_va-loffset); */
++	return dma_handle;
++}
++
++dma_addr_t BCMFASTPATH
++osl_sec_dma_dd_map(osl_t *osh, void *va, uint size, int direction, void *p, hnddma_seg_map_t *map)
++{
++
++	struct page *pa_cma_page;
++	phys_addr_t pa_cma;
++	dma_addr_t dma_handle = 0x0;
++	uint loffset;
++
++	pa_cma = ((uint8 *)va - (uint8 *)osh->contig_delta_va_pa);
++	pa_cma_page = phys_to_page(pa_cma);
++	loffset = pa_cma -(pa_cma & ~(PAGE_SIZE-1));
++
++	dma_handle = dma_map_page(OSH_NULL, pa_cma_page, loffset, size,
++		(direction == DMA_TX ? DMA_TO_DEVICE:DMA_FROM_DEVICE));
++
++	return dma_handle;
++}
++
++void BCMFASTPATH
++osl_sec_dma_unmap(osl_t *osh, dma_addr_t dma_handle, uint size, int direction,
++void *p, hnddma_seg_map_t *map,	void *ptr_cma_info, uint offset)
++{
++	sec_mem_elem_t *sec_mem_elem;
++	void *pa_cma_kmap_va = NULL;
++	uint buflen = 0;
++	dma_addr_t pa_cma;
++	void *va;
++	int read_count = 0;
++	BCM_REFERENCE(buflen);
++	BCM_REFERENCE(read_count);
++
++	sec_mem_elem = osl_sec_dma_find_rem_elem(osh, ptr_cma_info, dma_handle);
++	ASSERT(sec_mem_elem);
++
++	va = sec_mem_elem->va;
++	va = (uint8 *)va - offset;
++	pa_cma = sec_mem_elem->pa_cma;
++
++
++	if (direction == DMA_RX) {
++
++		if (p == NULL) {
++
++			/* pa_cma_kmap_va = kmap_atomic(pa_cma_page);
++			* pa_cma_kmap_va += loffset;
++			*/
++
++			pa_cma_kmap_va = sec_mem_elem->vac;
++
++			do {
++				invalidate_kernel_vmap_range(pa_cma_kmap_va, sizeof(int));
++
++				buflen = *(uint *)(pa_cma_kmap_va);
++				if (buflen)
++					break;
++
++				OSL_DELAY(1);
++				read_count++;
++			} while (read_count < 200);
++			dma_unmap_page(OSH_NULL, pa_cma, size, DMA_FROM_DEVICE);
++			memcpy(va, pa_cma_kmap_va, size);
++			/* kunmap_atomic(pa_cma_kmap_va); */
++		}
++	} else {
++		dma_unmap_page(OSH_NULL, pa_cma, size+offset, DMA_TO_DEVICE);
++	}
++
++	osl_sec_dma_free_mem_elem(osh, sec_mem_elem);
++}
++
++void
++osl_sec_dma_unmap_all(osl_t *osh, void *ptr_cma_info)
++{
++
++	sec_mem_elem_t *sec_mem_elem;
++
++	sec_mem_elem = osl_sec_dma_rem_first_elem(osh, ptr_cma_info);
++
++	while (sec_mem_elem != NULL) {
++
++		dma_unmap_page(OSH_NULL, sec_mem_elem->pa_cma, sec_mem_elem->size,
++			sec_mem_elem->direction == DMA_TX ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
++		osl_sec_dma_free_mem_elem(osh, sec_mem_elem);
++
++		sec_mem_elem = osl_sec_dma_rem_first_elem(osh, ptr_cma_info);
++	}
++}
++
++static void
++osl_sec_dma_init_consistent(osl_t *osh)
++{
++	int i;
++	void *temp_va = osh->contig_base_alloc_coherent_va;
++	phys_addr_t temp_pa = osh->contig_base_alloc_coherent;
++
++	for (i = 0; i < SEC_CMA_COHERENT_MAX; i++) {
++		osh->sec_cma_coherent[i].avail = TRUE;
++		osh->sec_cma_coherent[i].va = temp_va;
++		osh->sec_cma_coherent[i].pa = temp_pa;
++		temp_va = ((uint8 *)temp_va)+SEC_CMA_COHERENT_BLK;
++		temp_pa += SEC_CMA_COHERENT_BLK;
++	}
++}
++
++static void *
++osl_sec_dma_alloc_consistent(osl_t *osh, uint size, uint16 align_bits, ulong *pap)
++{
++
++	void *temp_va = NULL;
++	ulong temp_pa = 0;
++	int i;
++
++	if (size > SEC_CMA_COHERENT_BLK) {
++		printf("%s unsupported size\n", __FUNCTION__);
++		return NULL;
++	}
++
++	for (i = 0; i < SEC_CMA_COHERENT_MAX; i++) {
++		if (osh->sec_cma_coherent[i].avail == TRUE) {
++			temp_va = osh->sec_cma_coherent[i].va;
++			temp_pa = osh->sec_cma_coherent[i].pa;
++			osh->sec_cma_coherent[i].avail = FALSE;
++			break;
++		}
++	}
++
++	if (i == SEC_CMA_COHERENT_MAX)
++		printf("%s:No coherent mem: va = 0x%p pa = 0x%lx size = %d\n", __FUNCTION__,
++			temp_va, (ulong)temp_pa, size);
++
++	*pap = (unsigned long)temp_pa;
++	return temp_va;
++}
++
++static void
++osl_sec_dma_free_consistent(osl_t *osh, void *va, uint size, dmaaddr_t pa)
++{
++	int i = 0;
++
++	for (i = 0; i < SEC_CMA_COHERENT_MAX; i++) {
++		if (osh->sec_cma_coherent[i].va == va) {
++			osh->sec_cma_coherent[i].avail = TRUE;
++			break;
++		}
++	}
++	if (i == SEC_CMA_COHERENT_MAX)
++		printf("%s:Error: va = 0x%p pa = 0x%lx size = %d\n", __FUNCTION__,
++			va, (ulong)pa, size);
++}
++
++#endif /* BCM_SECURE_DMA */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0) && defined(TSQ_MULTIPLIER)
++#include <linux/kallsyms.h>
++#include <net/sock.h>
++void
++osl_pkt_orphan_partial(struct sk_buff *skb, int tsq)
++{
++	uint32 fraction;
++	static void *p_tcp_wfree = NULL;
++
++	if (tsq <= 0)
++		return;
++
++	if (!skb->destructor || skb->destructor == sock_wfree)
++		return;
++
++	if (unlikely(!p_tcp_wfree)) {
++		char sym[KSYM_SYMBOL_LEN];
++		sprint_symbol(sym, (unsigned long)skb->destructor);
++		sym[9] = 0;
++		if (!strcmp(sym, "tcp_wfree"))
++			p_tcp_wfree = skb->destructor;
++		else
++			return;
++	}
++
++	if (unlikely(skb->destructor != p_tcp_wfree || !skb->sk))
++		return;
++
++	/* abstract a certain portion of skb truesize from the socket
++	 * sk_wmem_alloc to allow more skb can be allocated for this
++	 * socket for better cusion meeting WiFi device requirement
++	 */
++	fraction = skb->truesize * (tsq - 1) / tsq;
++	skb->truesize -= fraction;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 13, 0)
++	atomic_sub(fraction, &skb->sk->sk_wmem_alloc.refs);
++#else
++	atomic_sub(fraction, &skb->sk->sk_wmem_alloc);
++#endif /* LINUX_VERSION >= 4.13.0 */
++	skb_orphan(skb);
++}
++#endif /* LINUX_VERSION >= 3.6.0 && TSQ_MULTIPLIER */
++
++/* timer apis */
++/* Note: All timer api's are thread unsafe and should be protected with locks by caller */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)
++void
++timer_cb_compat(struct timer_list *tl)
++{
++	timer_list_compat_t *t = container_of(tl, timer_list_compat_t, timer);
++	t->callback((ulong)t->arg);
++}
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0) */
++
++#ifdef REPORT_FATAL_TIMEOUTS
++osl_timer_t *
++osl_timer_init(osl_t *osh, const char *name, void (*fn)(void *arg), void *arg)
++{
++	osl_timer_t *t;
++	BCM_REFERENCE(fn);
++	if ((t = MALLOCZ(NULL, sizeof(osl_timer_t))) == NULL) {
++		printk(KERN_ERR "osl_timer_init: malloced failed for osl_timer_t\n");
++		return (NULL);
++	}
++	bzero(t, sizeof(osl_timer_t));
++	if ((t->timer = MALLOCZ(NULL, sizeof(struct timer_list))) == NULL) {
++		printk(KERN_ERR "osl_timer_init: malloc failed\n");
++		MFREE(NULL, t, sizeof(osl_timer_t));
++		return (NULL);
++	}
++	t->timer->data = (ulong)arg;
++	t->timer->function = (linux_timer_fn)fn;
++	t->set = TRUE;
++
++	init_timer(t->timer);
++
++	return (t);
++}
++
++void
++osl_timer_add(osl_t *osh, osl_timer_t *t, uint32 ms, bool periodic)
++{
++
++	if (t == NULL) {
++		printf("%s: Timer handle is NULL\n", __FUNCTION__);
++		return;
++	}
++	ASSERT(!t->set);
++
++	t->set = TRUE;
++	if (periodic) {
++		printf("Periodic timers are not supported by Linux timer apis\n");
++	}
++	t->timer->expires = jiffies + ms*HZ/1000;
++
++	add_timer(t->timer);
++
++	return;
++}
++
++void
++osl_timer_update(osl_t *osh, osl_timer_t *t, uint32 ms, bool periodic)
++{
++
++	if (t == NULL) {
++		printf("%s: Timer handle is NULL\n", __FUNCTION__);
++		return;
++	}
++	if (periodic) {
++		printf("Periodic timers are not supported by Linux timer apis\n");
++	}
++	t->set = TRUE;
++	t->timer->expires = jiffies + ms*HZ/1000;
++
++	mod_timer(t->timer, t->timer->expires);
++
++	return;
++}
++
++/*
++ * Return TRUE if timer successfully deleted, FALSE if still pending
++ */
++bool
++osl_timer_del(osl_t *osh, osl_timer_t *t)
++{
++	if (t == NULL) {
++		printf("%s: Timer handle is NULL\n", __FUNCTION__);
++		return (FALSE);
++	}
++	if (t->set) {
++		t->set = FALSE;
++		if (t->timer) {
++			del_timer(t->timer);
++			MFREE(NULL, t->timer, sizeof(struct timer_list));
++		}
++		MFREE(NULL, t, sizeof(osl_timer_t));
++	}
++	return (TRUE);
++}
++#endif
++
++void
++osl_do_gettimeofday(struct osl_timespec *ts)
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0)
++	struct timespec64 curtime;
++#else
++	struct timeval curtime;
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0)
++	ktime_get_real_ts64(&curtime);
++	ts->tv_nsec = curtime.tv_nsec;
++	ts->tv_usec = curtime.tv_nsec / 1000;
++#else
++	do_gettimeofday(&curtime);
++	ts->tv_usec = curtime.tv_usec;
++	ts->tv_nsec = curtime.tv_usec * 1000;
++#endif
++	ts->tv_sec = curtime.tv_sec;
++}
++
++void
++osl_get_monotonic_boottime(struct osl_timespec *ts)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39))
++	struct timespec64 curtime;
++#else
++	struct timeval curtime;
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39))
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)
++	ktime_get_boottime_ts64(&curtime);
++#else
++	get_monotonic_boottime(&curtime);
++#endif
++	ts->tv_sec = curtime.tv_sec;
++	ts->tv_usec = curtime.tv_nsec / 1000;
++	ts->tv_nsec = curtime.tv_nsec;
++#else
++	do_gettimeofday(&curtime);
++	ts->tv_sec = curtime.tv_sec;
++	ts->tv_usec = curtime.tv_usec;
++	ts->tv_nsec = curtime.tv_usec * 1000;
++#endif
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/pcie_core.c b/module_drivers/drivers/net/wireless/bcmdhd/pcie_core.c
+new file mode 100644
+index 000000000..63f955cb6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/pcie_core.c
+@@ -0,0 +1,135 @@
++/** @file pcie_core.c
++ *
++ * Contains PCIe related functions that are shared between different driver models (e.g. firmware
++ * builds, DHD builds, BMAC builds), in order to avoid code duplication.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: pcie_core.c 658668 2016-09-09 00:42:11Z $
++ */
++
++#include <bcm_cfg.h>
++#include <typedefs.h>
++#include <bcmutils.h>
++#include <bcmdefs.h>
++#include <osl.h>
++#include <siutils.h>
++#include <hndsoc.h>
++#include <sbchipc.h>
++#include <pcicfg.h>
++
++#include "pcie_core.h"
++
++/* local prototypes */
++
++/* local variables */
++
++/* function definitions */
++
++#ifdef BCMDRIVER
++
++void pcie_watchdog_reset(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs)
++{
++	uint32 val, i, lsc;
++	uint16 cfg_offset[] = {PCIECFGREG_STATUS_CMD, PCIECFGREG_PM_CSR,
++		PCIECFGREG_MSI_CAP, PCIECFGREG_MSI_ADDR_L,
++		PCIECFGREG_MSI_ADDR_H, PCIECFGREG_MSI_DATA,
++		PCIECFGREG_LINK_STATUS_CTRL2, PCIECFGREG_RBAR_CTRL,
++		PCIECFGREG_PML1_SUB_CTRL1, PCIECFGREG_REG_BAR2_CONFIG,
++		PCIECFGREG_REG_BAR3_CONFIG};
++	sbpcieregs_t *pcie = NULL;
++	uint32 origidx = si_coreidx(sih);
++
++	/* Switch to PCIE2 core */
++	pcie = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0);
++	BCM_REFERENCE(pcie);
++	ASSERT(pcie != NULL);
++
++	/* Disable/restore ASPM Control to protect the watchdog reset */
++	W_REG(osh, &sbpcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL);
++	lsc = R_REG(osh, &sbpcieregs->configdata);
++	val = lsc & (~PCIE_ASPM_ENAB);
++	W_REG(osh, &sbpcieregs->configdata, val);
++
++	si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, 4);
++	OSL_DELAY(100000);
++
++	W_REG(osh, &sbpcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL);
++	W_REG(osh, &sbpcieregs->configdata, lsc);
++
++	if (sih->buscorerev <= 13) {
++		/* Write configuration registers back to the shadow registers
++		 * cause shadow registers are cleared out after watchdog reset.
++		 */
++		for (i = 0; i < ARRAYSIZE(cfg_offset); i++) {
++			W_REG(osh, &sbpcieregs->configaddr, cfg_offset[i]);
++			val = R_REG(osh, &sbpcieregs->configdata);
++			W_REG(osh, &sbpcieregs->configdata, val);
++		}
++	}
++	si_setcoreidx(sih, origidx);
++}
++
++
++/* CRWLPCIEGEN2-117 pcie_pipe_Iddq should be controlled
++ * by the L12 state from MAC to save power by putting the
++ * SerDes analog in IDDQ mode
++ */
++void  pcie_serdes_iddqdisable(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs)
++{
++	sbpcieregs_t *pcie = NULL;
++	uint crwlpciegen2_117_disable = 0;
++	uint32 origidx = si_coreidx(sih);
++
++	crwlpciegen2_117_disable = PCIE_PipeIddqDisable0 | PCIE_PipeIddqDisable1;
++	/* Switch to PCIE2 core */
++	pcie = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0);
++	BCM_REFERENCE(pcie);
++	ASSERT(pcie != NULL);
++
++	OR_REG(osh, &sbpcieregs->control,
++		crwlpciegen2_117_disable);
++
++	si_setcoreidx(sih, origidx);
++}
++
++#define PCIE_PMCR_REFUP_MASK 0x3f0001e0
++#define PCIE_PMCR_REFEXT_MASK 0x400000
++#define PCIE_PMCR_REFUP_100US 0x38000080
++#define PCIE_PMCR_REFEXT_100US 0x400000
++
++/* Set PCIE TRefUp time to 100us */
++void pcie_set_trefup_time_100us(si_t *sih)
++{
++	si_corereg(sih, sih->buscoreidx,
++		OFFSETOF(sbpcieregs_t, configaddr), ~0, PCI_PMCR_REFUP);
++	si_corereg(sih, sih->buscoreidx,
++		OFFSETOF(sbpcieregs_t, configdata), PCIE_PMCR_REFUP_MASK, PCIE_PMCR_REFUP_100US);
++
++	si_corereg(sih, sih->buscoreidx,
++		OFFSETOF(sbpcieregs_t, configaddr), ~0, PCI_PMCR_REFUP_EXT);
++	si_corereg(sih, sih->buscoreidx,
++		OFFSETOF(sbpcieregs_t, configdata), PCIE_PMCR_REFEXT_MASK, PCIE_PMCR_REFEXT_100US);
++}
++#endif /* BCMDRIVER */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/sbutils.c b/module_drivers/drivers/net/wireless/bcmdhd/sbutils.c
+new file mode 100644
+index 000000000..975ee6afa
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/sbutils.c
+@@ -0,0 +1,1101 @@
++/*
++ * Misc utility routines for accessing chip-specific features
++ * of the SiliconBackplane-based Broadcom chips.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: sbutils.c 599296 2015-11-13 06:36:13Z $
++ */
++
++#include <bcm_cfg.h>
++#include <typedefs.h>
++#include <bcmdefs.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <siutils.h>
++#include <bcmdevs.h>
++#include <hndsoc.h>
++#include <sbchipc.h>
++#include <pcicfg.h>
++#include <sbpcmcia.h>
++
++#include "siutils_priv.h"
++
++
++/* local prototypes */
++static uint _sb_coreidx(si_info_t *sii, uint32 sba);
++static uint _sb_scan(si_info_t *sii, uint32 sba, volatile void *regs, uint bus, uint32 sbba,
++                     uint ncores);
++static uint32 _sb_coresba(si_info_t *sii);
++static volatile void *_sb_setcoreidx(si_info_t *sii, uint coreidx);
++#define	SET_SBREG(sii, r, mask, val)	\
++		W_SBREG((sii), (r), ((R_SBREG((sii), (r)) & ~(mask)) | (val)))
++#define	REGS2SB(va)	(sbconfig_t*) ((volatile int8*)(va) + SBCONFIGOFF)
++
++/* sonicsrev */
++#define	SONICS_2_2	(SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
++#define	SONICS_2_3	(SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
++
++#define	R_SBREG(sii, sbr)	sb_read_sbreg((sii), (sbr))
++#define	W_SBREG(sii, sbr, v)	sb_write_sbreg((sii), (sbr), (v))
++#define	AND_SBREG(sii, sbr, v)	W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) & (v)))
++#define	OR_SBREG(sii, sbr, v)	W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) | (v)))
++
++static uint32
++sb_read_sbreg(si_info_t *sii, volatile uint32 *sbr)
++{
++	uint8 tmp;
++	uint32 val, intr_val = 0;
++
++
++	/*
++	 * compact flash only has 11 bits address, while we needs 12 bits address.
++	 * MEM_SEG will be OR'd with other 11 bits address in hardware,
++	 * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
++	 * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
++	 */
++	if (PCMCIA(sii)) {
++		INTR_OFF(sii, intr_val);
++		tmp = 1;
++		OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
++		sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
++	}
++
++	val = R_REG(sii->osh, sbr);
++
++	if (PCMCIA(sii)) {
++		tmp = 0;
++		OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
++		INTR_RESTORE(sii, intr_val);
++	}
++
++	return (val);
++}
++
++static void
++sb_write_sbreg(si_info_t *sii, volatile uint32 *sbr, uint32 v)
++{
++	uint8 tmp;
++	volatile uint32 dummy;
++	uint32 intr_val = 0;
++
++
++	/*
++	 * compact flash only has 11 bits address, while we needs 12 bits address.
++	 * MEM_SEG will be OR'd with other 11 bits address in hardware,
++	 * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
++	 * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
++	 */
++	if (PCMCIA(sii)) {
++		INTR_OFF(sii, intr_val);
++		tmp = 1;
++		OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
++		sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
++	}
++
++	if (BUSTYPE(sii->pub.bustype) == PCMCIA_BUS) {
++		dummy = R_REG(sii->osh, sbr);
++		BCM_REFERENCE(dummy);
++		W_REG(sii->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
++		dummy = R_REG(sii->osh, sbr);
++		BCM_REFERENCE(dummy);
++		W_REG(sii->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
++	} else
++		W_REG(sii->osh, sbr, v);
++
++	if (PCMCIA(sii)) {
++		tmp = 0;
++		OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
++		INTR_RESTORE(sii, intr_val);
++	}
++}
++
++uint
++sb_coreid(si_t *sih)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	return ((R_SBREG(sii, &sb->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
++}
++
++uint
++sb_intflag(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	volatile void *corereg;
++	sbconfig_t *sb;
++	uint origidx, intflag, intr_val = 0;
++
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++	corereg = si_setcore(sih, CC_CORE_ID, 0);
++	ASSERT(corereg != NULL);
++	sb = REGS2SB(corereg);
++	intflag = R_SBREG(sii, &sb->sbflagst);
++	sb_setcoreidx(sih, origidx);
++	INTR_RESTORE(sii, intr_val);
++
++	return intflag;
++}
++
++uint
++sb_flag(si_t *sih)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	return R_SBREG(sii, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
++}
++
++void
++sb_setint(si_t *sih, int siflag)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++	uint32 vec;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	if (siflag == -1)
++		vec = 0;
++	else
++		vec = 1 << siflag;
++	W_SBREG(sii, &sb->sbintvec, vec);
++}
++
++/* return core index of the core with address 'sba' */
++static uint
++_sb_coreidx(si_info_t *sii, uint32 sba)
++{
++	uint i;
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	for (i = 0; i < sii->numcores; i ++)
++		if (sba == cores_info->coresba[i])
++			return i;
++	return BADIDX;
++}
++
++/* return core address of the current core */
++static uint32
++_sb_coresba(si_info_t *sii)
++{
++	uint32 sbaddr;
++
++
++	switch (BUSTYPE(sii->pub.bustype)) {
++	case SI_BUS: {
++		sbconfig_t *sb = REGS2SB(sii->curmap);
++		sbaddr = sb_base(R_SBREG(sii, &sb->sbadmatch0));
++		break;
++	}
++
++	case PCI_BUS:
++		sbaddr = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
++		break;
++
++	case PCMCIA_BUS: {
++		uint8 tmp = 0;
++		OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR0, &tmp, 1);
++		sbaddr  = (uint32)tmp << 12;
++		OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR1, &tmp, 1);
++		sbaddr |= (uint32)tmp << 16;
++		OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR2, &tmp, 1);
++		sbaddr |= (uint32)tmp << 24;
++		break;
++	}
++
++#ifdef BCMSDIO
++	case SPI_BUS:
++	case SDIO_BUS:
++		sbaddr = (uint32)(uintptr)sii->curmap;
++		break;
++#endif
++
++
++	default:
++		sbaddr = BADCOREADDR;
++		break;
++	}
++
++	return sbaddr;
++}
++
++uint
++sb_corevendor(si_t *sih)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	return ((R_SBREG(sii, &sb->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
++}
++
++uint
++sb_corerev(si_t *sih)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++	uint sbidh;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++	sbidh = R_SBREG(sii, &sb->sbidhigh);
++
++	return (SBCOREREV(sbidh));
++}
++
++/* set core-specific control flags */
++void
++sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++	uint32 w;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	ASSERT((val & ~mask) == 0);
++
++	/* mask and set */
++	w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) |
++	        (val << SBTML_SICF_SHIFT);
++	W_SBREG(sii, &sb->sbtmstatelow, w);
++}
++
++/* set/clear core-specific control flags */
++uint32
++sb_core_cflags(si_t *sih, uint32 mask, uint32 val)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++	uint32 w;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	ASSERT((val & ~mask) == 0);
++
++	/* mask and set */
++	if (mask || val) {
++		w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) |
++		        (val << SBTML_SICF_SHIFT);
++		W_SBREG(sii, &sb->sbtmstatelow, w);
++	}
++
++	/* return the new value
++	 * for write operation, the following readback ensures the completion of write opration.
++	 */
++	return (R_SBREG(sii, &sb->sbtmstatelow) >> SBTML_SICF_SHIFT);
++}
++
++/* set/clear core-specific status flags */
++uint32
++sb_core_sflags(si_t *sih, uint32 mask, uint32 val)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++	uint32 w;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	ASSERT((val & ~mask) == 0);
++	ASSERT((mask & ~SISF_CORE_BITS) == 0);
++
++	/* mask and set */
++	if (mask || val) {
++		w = (R_SBREG(sii, &sb->sbtmstatehigh) & ~(mask << SBTMH_SISF_SHIFT)) |
++		        (val << SBTMH_SISF_SHIFT);
++		W_SBREG(sii, &sb->sbtmstatehigh, w);
++	}
++
++	/* return the new value */
++	return (R_SBREG(sii, &sb->sbtmstatehigh) >> SBTMH_SISF_SHIFT);
++}
++
++bool
++sb_iscoreup(si_t *sih)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	return ((R_SBREG(sii, &sb->sbtmstatelow) &
++	         (SBTML_RESET | SBTML_REJ_MASK | (SICF_CLOCK_EN << SBTML_SICF_SHIFT))) ==
++	        (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
++}
++
++/*
++ * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
++ * switch back to the original core, and return the new value.
++ *
++ * When using the silicon backplane, no fidleing with interrupts or core switches are needed.
++ *
++ * Also, when using pci/pcie, we can optimize away the core switching for pci registers
++ * and (on newer pci cores) chipcommon registers.
++ */
++uint
++sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
++{
++	uint origidx = 0;
++	volatile uint32 *r = NULL;
++	uint w;
++	uint intr_val = 0;
++	bool fast = FALSE;
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	ASSERT(GOODIDX(coreidx));
++	ASSERT(regoff < SI_CORE_SIZE);
++	ASSERT((val & ~mask) == 0);
++
++	if (coreidx >= SI_MAXCORES)
++		return 0;
++
++	if (BUSTYPE(sii->pub.bustype) == SI_BUS) {
++		/* If internal bus, we can always get at everything */
++		fast = TRUE;
++		/* map if does not exist */
++		if (!cores_info->regs[coreidx]) {
++			cores_info->regs[coreidx] = REG_MAP(cores_info->coresba[coreidx],
++			                            SI_CORE_SIZE);
++			ASSERT(GOODREGS(cores_info->regs[coreidx]));
++		}
++		r = (volatile uint32 *)((volatile uchar *)cores_info->regs[coreidx] + regoff);
++	} else if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
++		/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
++
++		if ((cores_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
++			/* Chipc registers are mapped at 12KB */
++
++			fast = TRUE;
++			r = (volatile uint32 *)((volatile char *)sii->curmap +
++			               PCI_16KB0_CCREGS_OFFSET + regoff);
++		} else if (sii->pub.buscoreidx == coreidx) {
++			/* pci registers are at either in the last 2KB of an 8KB window
++			 * or, in pcie and pci rev 13 at 8KB
++			 */
++			fast = TRUE;
++			if (SI_FAST(sii))
++				r = (volatile uint32 *)((volatile char *)sii->curmap +
++				               PCI_16KB0_PCIREGS_OFFSET + regoff);
++			else
++				r = (volatile uint32 *)((volatile char *)sii->curmap +
++				               ((regoff >= SBCONFIGOFF) ?
++				                PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
++				               regoff);
++		}
++	}
++
++	if (!fast) {
++		INTR_OFF(sii, intr_val);
++
++		/* save current core index */
++		origidx = si_coreidx(&sii->pub);
++
++		/* switch core */
++		r = (volatile uint32*) ((volatile uchar*)sb_setcoreidx(&sii->pub, coreidx) +
++		               regoff);
++	}
++	ASSERT(r != NULL);
++
++	/* mask and set */
++	if (mask || val) {
++		if (regoff >= SBCONFIGOFF) {
++			w = (R_SBREG(sii, r) & ~mask) | val;
++			W_SBREG(sii, r, w);
++		} else {
++			w = (R_REG(sii->osh, r) & ~mask) | val;
++			W_REG(sii->osh, r, w);
++		}
++	}
++
++	/* readback */
++	if (regoff >= SBCONFIGOFF)
++		w = R_SBREG(sii, r);
++	else {
++		w = R_REG(sii->osh, r);
++	}
++
++	if (!fast) {
++		/* restore core index */
++		if (origidx != coreidx)
++			sb_setcoreidx(&sii->pub, origidx);
++
++		INTR_RESTORE(sii, intr_val);
++	}
++
++	return (w);
++}
++
++/*
++ * If there is no need for fiddling with interrupts or core switches (typically silicon
++ * back plane registers, pci registers and chipcommon registers), this function
++ * returns the register offset on this core to a mapped address. This address can
++ * be used for W_REG/R_REG directly.
++ *
++ * For accessing registers that would need a core switch, this function will return
++ * NULL.
++ */
++volatile uint32 *
++sb_corereg_addr(si_t *sih, uint coreidx, uint regoff)
++{
++	volatile uint32 *r = NULL;
++	bool fast = FALSE;
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	ASSERT(GOODIDX(coreidx));
++	ASSERT(regoff < SI_CORE_SIZE);
++
++	if (coreidx >= SI_MAXCORES)
++		return 0;
++
++	if (BUSTYPE(sii->pub.bustype) == SI_BUS) {
++		/* If internal bus, we can always get at everything */
++		fast = TRUE;
++		/* map if does not exist */
++		if (!cores_info->regs[coreidx]) {
++			cores_info->regs[coreidx] = REG_MAP(cores_info->coresba[coreidx],
++			                            SI_CORE_SIZE);
++			ASSERT(GOODREGS(cores_info->regs[coreidx]));
++		}
++		r = (volatile uint32 *)((volatile uchar *)cores_info->regs[coreidx] + regoff);
++	} else if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
++		/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
++
++		if ((cores_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
++			/* Chipc registers are mapped at 12KB */
++
++			fast = TRUE;
++			r = (volatile uint32 *)((volatile char *)sii->curmap +
++			               PCI_16KB0_CCREGS_OFFSET + regoff);
++		} else if (sii->pub.buscoreidx == coreidx) {
++			/* pci registers are at either in the last 2KB of an 8KB window
++			 * or, in pcie and pci rev 13 at 8KB
++			 */
++			fast = TRUE;
++			if (SI_FAST(sii))
++				r = (volatile uint32 *)((volatile char *)sii->curmap +
++				               PCI_16KB0_PCIREGS_OFFSET + regoff);
++			else
++				r = (volatile uint32 *)((volatile char *)sii->curmap +
++				               ((regoff >= SBCONFIGOFF) ?
++				                PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
++				               regoff);
++		}
++	}
++
++	if (!fast)
++		return 0;
++
++	return (r);
++}
++
++/* Scan the enumeration space to find all cores starting from the given
++ * bus 'sbba'. Append coreid and other info to the lists in 'si'. 'sba'
++ * is the default core address at chip POR time and 'regs' is the virtual
++ * address that the default core is mapped at. 'ncores' is the number of
++ * cores expected on bus 'sbba'. It returns the total number of cores
++ * starting from bus 'sbba', inclusive.
++ */
++#define SB_MAXBUSES	2
++static uint
++_sb_scan(si_info_t *sii, uint32 sba, volatile void *regs, uint bus,
++	uint32 sbba, uint numcores)
++{
++	uint next;
++	uint ncc = 0;
++	uint i;
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	if (bus >= SB_MAXBUSES) {
++		SI_ERROR(("_sb_scan: bus 0x%08x at level %d is too deep to scan\n", sbba, bus));
++		return 0;
++	}
++	SI_MSG(("_sb_scan: scan bus 0x%08x assume %u cores\n", sbba, numcores));
++
++	/* Scan all cores on the bus starting from core 0.
++	 * Core addresses must be contiguous on each bus.
++	 */
++	for (i = 0, next = sii->numcores; i < numcores && next < SB_BUS_MAXCORES; i++, next++) {
++		cores_info->coresba[next] = sbba + (i * SI_CORE_SIZE);
++
++		/* keep and reuse the initial register mapping */
++		if ((BUSTYPE(sii->pub.bustype) == SI_BUS) && (cores_info->coresba[next] == sba)) {
++			SI_VMSG(("_sb_scan: reuse mapped regs %p for core %u\n", regs, next));
++			cores_info->regs[next] = regs;
++		}
++
++		/* change core to 'next' and read its coreid */
++		sii->curmap = _sb_setcoreidx(sii, next);
++		sii->curidx = next;
++
++		cores_info->coreid[next] = sb_coreid(&sii->pub);
++
++		/* core specific processing... */
++		/* chipc provides # cores */
++		if (cores_info->coreid[next] == CC_CORE_ID) {
++			chipcregs_t *cc = (chipcregs_t *)sii->curmap;
++			uint32 ccrev = sb_corerev(&sii->pub);
++
++			/* determine numcores - this is the total # cores in the chip */
++			if (((ccrev == 4) || (ccrev >= 6))) {
++				ASSERT(cc);
++				numcores = (R_REG(sii->osh, &cc->chipid) & CID_CC_MASK) >>
++				        CID_CC_SHIFT;
++			} else {
++				/* Older chips */
++				uint chip = CHIPID(sii->pub.chip);
++
++				if (chip == BCM4704_CHIP_ID)
++					numcores = 9;
++				else if (chip == BCM5365_CHIP_ID)
++					numcores = 7;
++				else {
++					SI_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n",
++					          chip));
++					ASSERT(0);
++					numcores = 1;
++				}
++			}
++			SI_VMSG(("_sb_scan: there are %u cores in the chip %s\n", numcores,
++				sii->pub.issim ? "QT" : ""));
++		}
++		/* scan bridged SB(s) and add results to the end of the list */
++		else if (cores_info->coreid[next] == OCP_CORE_ID) {
++			sbconfig_t *sb = REGS2SB(sii->curmap);
++			uint32 nsbba = R_SBREG(sii, &sb->sbadmatch1);
++			uint nsbcc;
++
++			sii->numcores = next + 1;
++
++			if ((nsbba & 0xfff00000) != SI_ENUM_BASE)
++				continue;
++			nsbba &= 0xfffff000;
++			if (_sb_coreidx(sii, nsbba) != BADIDX)
++				continue;
++
++			nsbcc = (R_SBREG(sii, &sb->sbtmstatehigh) & 0x000f0000) >> 16;
++			nsbcc = _sb_scan(sii, sba, regs, bus + 1, nsbba, nsbcc);
++			if (sbba == SI_ENUM_BASE)
++				numcores -= nsbcc;
++			ncc += nsbcc;
++		}
++	}
++
++	SI_MSG(("_sb_scan: found %u cores on bus 0x%08x\n", i, sbba));
++
++	sii->numcores = i + ncc;
++	return sii->numcores;
++}
++
++/* scan the sb enumerated space to identify all cores */
++void
++sb_scan(si_t *sih, volatile void *regs, uint devid)
++{
++	uint32 origsba;
++	sbconfig_t *sb;
++	si_info_t *sii = SI_INFO(sih);
++	BCM_REFERENCE(devid);
++
++	sb = REGS2SB(sii->curmap);
++
++	sii->pub.socirev = (R_SBREG(sii, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
++
++	/* Save the current core info and validate it later till we know
++	 * for sure what is good and what is bad.
++	 */
++	origsba = _sb_coresba(sii);
++
++	/* scan all SB(s) starting from SI_ENUM_BASE */
++	sii->numcores = _sb_scan(sii, origsba, regs, 0, SI_ENUM_BASE, 1);
++}
++
++/*
++ * This function changes logical "focus" to the indicated core;
++ * must be called with interrupts off.
++ * Moreover, callers should keep interrupts off during switching out of and back to d11 core
++ */
++volatile void *
++sb_setcoreidx(si_t *sih, uint coreidx)
++{
++	si_info_t *sii = SI_INFO(sih);
++
++	if (coreidx >= sii->numcores)
++		return (NULL);
++
++	/*
++	 * If the user has provided an interrupt mask enabled function,
++	 * then assert interrupts are disabled before switching the core.
++	 */
++	ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg));
++
++	sii->curmap = _sb_setcoreidx(sii, coreidx);
++	sii->curidx = coreidx;
++
++	return (sii->curmap);
++}
++
++/* This function changes the logical "focus" to the indicated core.
++ * Return the current core's virtual address.
++ */
++static volatile void *
++_sb_setcoreidx(si_info_t *sii, uint coreidx)
++{
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint32 sbaddr = cores_info->coresba[coreidx];
++	volatile void *regs;
++
++	switch (BUSTYPE(sii->pub.bustype)) {
++	case SI_BUS:
++		/* map new one */
++		if (!cores_info->regs[coreidx]) {
++			cores_info->regs[coreidx] = REG_MAP(sbaddr, SI_CORE_SIZE);
++			ASSERT(GOODREGS(cores_info->regs[coreidx]));
++		}
++		regs = cores_info->regs[coreidx];
++		break;
++
++	case PCI_BUS:
++		/* point bar0 window */
++		OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, sbaddr);
++		regs = sii->curmap;
++		break;
++
++	case PCMCIA_BUS: {
++		uint8 tmp = (sbaddr >> 12) & 0x0f;
++		OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR0, &tmp, 1);
++		tmp = (sbaddr >> 16) & 0xff;
++		OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR1, &tmp, 1);
++		tmp = (sbaddr >> 24) & 0xff;
++		OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR2, &tmp, 1);
++		regs = sii->curmap;
++		break;
++	}
++#ifdef BCMSDIO
++	case SPI_BUS:
++	case SDIO_BUS:
++		/* map new one */
++		if (!cores_info->regs[coreidx]) {
++			cores_info->regs[coreidx] = (void *)(uintptr)sbaddr;
++			ASSERT(GOODREGS(cores_info->regs[coreidx]));
++		}
++		regs = cores_info->regs[coreidx];
++		break;
++#endif	/* BCMSDIO */
++
++
++	default:
++		ASSERT(0);
++		regs = NULL;
++		break;
++	}
++
++	return regs;
++}
++
++/* Return the address of sbadmatch0/1/2/3 register */
++static volatile uint32 *
++sb_admatch(si_info_t *sii, uint asidx)
++{
++	sbconfig_t *sb;
++	volatile uint32 *addrm;
++
++	sb = REGS2SB(sii->curmap);
++
++	switch (asidx) {
++	case 0:
++		addrm =  &sb->sbadmatch0;
++		break;
++
++	case 1:
++		addrm =  &sb->sbadmatch1;
++		break;
++
++	case 2:
++		addrm =  &sb->sbadmatch2;
++		break;
++
++	case 3:
++		addrm =  &sb->sbadmatch3;
++		break;
++
++	default:
++		SI_ERROR(("%s: Address space index (%d) out of range\n", __FUNCTION__, asidx));
++		return 0;
++	}
++
++	return (addrm);
++}
++
++/* Return the number of address spaces in current core */
++int
++sb_numaddrspaces(si_t *sih)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	/* + 1 because of enumeration space */
++	return ((R_SBREG(sii, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT) + 1;
++}
++
++/* Return the address of the nth address space in the current core */
++uint32
++sb_addrspace(si_t *sih, uint asidx)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++
++	return (sb_base(R_SBREG(sii, sb_admatch(sii, asidx))));
++}
++
++/* Return the size of the nth address space in the current core */
++uint32
++sb_addrspacesize(si_t *sih, uint asidx)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++
++	return (sb_size(R_SBREG(sii, sb_admatch(sii, asidx))));
++}
++
++
++/* do buffered registers update */
++void
++sb_commit(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint origidx;
++	uint intr_val = 0;
++
++	origidx = sii->curidx;
++	ASSERT(GOODIDX(origidx));
++
++	INTR_OFF(sii, intr_val);
++
++	/* switch over to chipcommon core if there is one, else use pci */
++	if (sii->pub.ccrev != NOREV) {
++		chipcregs_t *ccregs = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
++		ASSERT(ccregs != NULL);
++
++		/* do the buffer registers update */
++		W_REG(sii->osh, &ccregs->broadcastaddress, SB_COMMIT);
++		W_REG(sii->osh, &ccregs->broadcastdata, 0x0);
++	} else
++		ASSERT(0);
++
++	/* restore core index */
++	sb_setcoreidx(sih, origidx);
++	INTR_RESTORE(sii, intr_val);
++}
++
++void
++sb_core_disable(si_t *sih, uint32 bits)
++{
++	si_info_t *sii;
++	volatile uint32 dummy;
++	sbconfig_t *sb;
++
++	sii = SI_INFO(sih);
++
++	ASSERT(GOODREGS(sii->curmap));
++	sb = REGS2SB(sii->curmap);
++
++	/* if core is already in reset, just return */
++	if (R_SBREG(sii, &sb->sbtmstatelow) & SBTML_RESET)
++		return;
++
++	/* if clocks are not enabled, put into reset and return */
++	if ((R_SBREG(sii, &sb->sbtmstatelow) & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) == 0)
++		goto disable;
++
++	/* set target reject and spin until busy is clear (preserve core-specific bits) */
++	OR_SBREG(sii, &sb->sbtmstatelow, SBTML_REJ);
++	dummy = R_SBREG(sii, &sb->sbtmstatelow);
++	BCM_REFERENCE(dummy);
++	OSL_DELAY(1);
++	SPINWAIT((R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
++	if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY)
++		SI_ERROR(("%s: target state still busy\n", __FUNCTION__));
++
++	if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT) {
++		OR_SBREG(sii, &sb->sbimstate, SBIM_RJ);
++		dummy = R_SBREG(sii, &sb->sbimstate);
++		BCM_REFERENCE(dummy);
++		OSL_DELAY(1);
++		SPINWAIT((R_SBREG(sii, &sb->sbimstate) & SBIM_BY), 100000);
++	}
++
++	/* set reset and reject while enabling the clocks */
++	W_SBREG(sii, &sb->sbtmstatelow,
++	        (((bits | SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
++	         SBTML_REJ | SBTML_RESET));
++	dummy = R_SBREG(sii, &sb->sbtmstatelow);
++	BCM_REFERENCE(dummy);
++	OSL_DELAY(10);
++
++	/* don't forget to clear the initiator reject bit */
++	if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT)
++		AND_SBREG(sii, &sb->sbimstate, ~SBIM_RJ);
++
++disable:
++	/* leave reset and reject asserted */
++	W_SBREG(sii, &sb->sbtmstatelow, ((bits << SBTML_SICF_SHIFT) | SBTML_REJ | SBTML_RESET));
++	OSL_DELAY(1);
++}
++
++/* reset and re-enable a core
++ * inputs:
++ * bits - core specific bits that are set during and after reset sequence
++ * resetbits - core specific bits that are set only during reset sequence
++ */
++void
++sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++	volatile uint32 dummy;
++
++	sii = SI_INFO(sih);
++	ASSERT(GOODREGS(sii->curmap));
++	sb = REGS2SB(sii->curmap);
++
++	/*
++	 * Must do the disable sequence first to work for arbitrary current core state.
++	 */
++	sb_core_disable(sih, (bits | resetbits));
++
++	/*
++	 * Now do the initialization sequence.
++	 */
++
++	/* set reset while enabling the clock and forcing them on throughout the core */
++	W_SBREG(sii, &sb->sbtmstatelow,
++	        (((bits | resetbits | SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
++	         SBTML_RESET));
++	dummy = R_SBREG(sii, &sb->sbtmstatelow);
++	BCM_REFERENCE(dummy);
++	OSL_DELAY(1);
++
++	if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_SERR) {
++		W_SBREG(sii, &sb->sbtmstatehigh, 0);
++	}
++	if ((dummy = R_SBREG(sii, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
++		AND_SBREG(sii, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
++	}
++
++	/* clear reset and allow it to propagate throughout the core */
++	W_SBREG(sii, &sb->sbtmstatelow,
++	        ((bits | resetbits | SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT));
++	dummy = R_SBREG(sii, &sb->sbtmstatelow);
++	BCM_REFERENCE(dummy);
++	OSL_DELAY(1);
++
++	/* leave clock enabled */
++	W_SBREG(sii, &sb->sbtmstatelow, ((bits | SICF_CLOCK_EN) << SBTML_SICF_SHIFT));
++	dummy = R_SBREG(sii, &sb->sbtmstatelow);
++	BCM_REFERENCE(dummy);
++	OSL_DELAY(1);
++}
++
++/*
++ * Set the initiator timeout for the "master core".
++ * The master core is defined to be the core in control
++ * of the chip and so it issues accesses to non-memory
++ * locations (Because of dma *any* core can access memeory).
++ *
++ * The routine uses the bus to decide who is the master:
++ *	SI_BUS => mips
++ *	JTAG_BUS => chipc
++ *	PCI_BUS => pci or pcie
++ *	PCMCIA_BUS => pcmcia
++ *	SDIO_BUS => pcmcia
++ *
++ * This routine exists so callers can disable initiator
++ * timeouts so accesses to very slow devices like otp
++ * won't cause an abort. The routine allows arbitrary
++ * settings of the service and request timeouts, though.
++ *
++ * Returns the timeout state before changing it or -1
++ * on error.
++ */
++
++#define	TO_MASK	(SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
++
++uint32
++sb_set_initiator_to(si_t *sih, uint32 to, uint idx)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint origidx;
++	uint intr_val = 0;
++	uint32 tmp, ret = 0xffffffff;
++	sbconfig_t *sb;
++
++
++	if ((to & ~TO_MASK) != 0)
++		return ret;
++
++	/* Figure out the master core */
++	if (idx == BADIDX) {
++		switch (BUSTYPE(sii->pub.bustype)) {
++		case PCI_BUS:
++			idx = sii->pub.buscoreidx;
++			break;
++		case JTAG_BUS:
++			idx = SI_CC_IDX;
++			break;
++		case PCMCIA_BUS:
++#ifdef BCMSDIO
++		case SDIO_BUS:
++#endif
++			idx = si_findcoreidx(sih, PCMCIA_CORE_ID, 0);
++			break;
++		case SI_BUS:
++			idx = si_findcoreidx(sih, MIPS33_CORE_ID, 0);
++			break;
++		default:
++			ASSERT(0);
++		}
++		if (idx == BADIDX)
++			return ret;
++	}
++
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	sb = REGS2SB(sb_setcoreidx(sih, idx));
++
++	tmp = R_SBREG(sii, &sb->sbimconfiglow);
++	ret = tmp & TO_MASK;
++	W_SBREG(sii, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
++
++	sb_commit(sih);
++	sb_setcoreidx(sih, origidx);
++	INTR_RESTORE(sii, intr_val);
++	return ret;
++}
++
++uint32
++sb_base(uint32 admatch)
++{
++	uint32 base;
++	uint type;
++
++	type = admatch & SBAM_TYPE_MASK;
++	ASSERT(type < 3);
++
++	base = 0;
++
++	if (type == 0) {
++		base = admatch & SBAM_BASE0_MASK;
++	} else if (type == 1) {
++		ASSERT(!(admatch & SBAM_ADNEG));	/* neg not supported */
++		base = admatch & SBAM_BASE1_MASK;
++	} else if (type == 2) {
++		ASSERT(!(admatch & SBAM_ADNEG));	/* neg not supported */
++		base = admatch & SBAM_BASE2_MASK;
++	}
++
++	return (base);
++}
++
++uint32
++sb_size(uint32 admatch)
++{
++	uint32 size;
++	uint type;
++
++	type = admatch & SBAM_TYPE_MASK;
++	ASSERT(type < 3);
++
++	size = 0;
++
++	if (type == 0) {
++		size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
++	} else if (type == 1) {
++		ASSERT(!(admatch & SBAM_ADNEG));	/* neg not supported */
++		size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
++	} else if (type == 2) {
++		ASSERT(!(admatch & SBAM_ADNEG));	/* neg not supported */
++		size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
++	}
++
++	return (size);
++}
++
++#if defined(BCMDBG_PHYDUMP)
++/* print interesting sbconfig registers */
++void
++sb_dumpregs(si_t *sih, struct bcmstrbuf *b)
++{
++	sbconfig_t *sb;
++	uint origidx, i, intr_val = 0;
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	origidx = sii->curidx;
++
++	INTR_OFF(sii, intr_val);
++
++	for (i = 0; i < sii->numcores; i++) {
++		sb = REGS2SB(sb_setcoreidx(sih, i));
++
++		bcm_bprintf(b, "core 0x%x: \n", cores_info->coreid[i]);
++
++		if (sii->pub.socirev > SONICS_2_2)
++			bcm_bprintf(b, "sbimerrlog 0x%x sbimerrloga 0x%x\n",
++			          sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOG, 0, 0),
++			          sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOGA, 0, 0));
++
++		bcm_bprintf(b, "sbtmstatelow 0x%x sbtmstatehigh 0x%x sbidhigh 0x%x "
++		            "sbimstate 0x%x\n sbimconfiglow 0x%x sbimconfighigh 0x%x\n",
++		            R_SBREG(sii, &sb->sbtmstatelow), R_SBREG(sii, &sb->sbtmstatehigh),
++		            R_SBREG(sii, &sb->sbidhigh), R_SBREG(sii, &sb->sbimstate),
++		            R_SBREG(sii, &sb->sbimconfiglow), R_SBREG(sii, &sb->sbimconfighigh));
++	}
++
++	sb_setcoreidx(sih, origidx);
++	INTR_RESTORE(sii, intr_val);
++}
++#endif	
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/siutils.c b/module_drivers/drivers/net/wireless/bcmdhd/siutils.c
+new file mode 100644
+index 000000000..3d8ec54a7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/siutils.c
+@@ -0,0 +1,3727 @@
++/*
++ * Misc utility routines for accessing chip-specific features
++ * of the SiliconBackplane-based Broadcom chips.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: siutils.c 668442 2016-11-03 08:42:43Z $
++ */
++
++#include <bcm_cfg.h>
++#include <typedefs.h>
++#include <bcmdefs.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <siutils.h>
++#include <bcmdevs.h>
++#include <hndsoc.h>
++#include <sbchipc.h>
++#include <sbgci.h>
++#ifdef BCMPCIEDEV
++#include <pciedev.h>
++#endif /* BCMPCIEDEV */
++#include <pcicfg.h>
++#include <sbpcmcia.h>
++#include <sbsysmem.h>
++#include <sbsocram.h>
++#ifdef BCMSDIO
++#include <bcmsdh.h>
++#include <sdio.h>
++#include <sbsdio.h>
++#include <sbhnddma.h>
++#include <sbsdpcmdev.h>
++#include <bcmsdpcm.h>
++#endif /* BCMSDIO */
++#include <hndpmu.h>
++#include <dhd_config.h>
++
++#ifdef BCM_SDRBL
++#include <hndcpu.h>
++#endif /* BCM_SDRBL */
++#ifdef HNDGCI
++#include <hndgci.h>
++#endif /* HNDGCI */
++#ifdef BCMULP
++#include <ulp.h>
++#endif /* BCMULP */
++
++
++#include "siutils_priv.h"
++#ifdef SECI_UART
++/* Defines the set of GPIOs to be used for SECI UART if not specified in NVRAM */
++#define DEFAULT_SECI_UART_PINMUX_43430	0x0102
++static bool force_seci_clk = 0;
++#endif /* SECI_UART */
++
++/**
++ * A set of PMU registers is clocked in the ILP domain, which has an implication on register write
++ * behavior: if such a register is written, it takes multiple ILP clocks for the PMU block to absorb
++ * the write. During that time the 'SlowWritePending' bit in the PMUStatus register is set.
++ */
++#define PMUREGS_ILP_SENSITIVE(regoff) \
++	((regoff) == OFFSETOF(pmuregs_t, pmutimer) || \
++	 (regoff) == OFFSETOF(pmuregs_t, pmuwatchdog) || \
++	 (regoff) == OFFSETOF(pmuregs_t, res_req_timer))
++
++#define CHIPCREGS_ILP_SENSITIVE(regoff) \
++	((regoff) == OFFSETOF(chipcregs_t, pmutimer) || \
++	 (regoff) == OFFSETOF(chipcregs_t, pmuwatchdog) || \
++	 (regoff) == OFFSETOF(chipcregs_t, res_req_timer))
++
++#define GCI_FEM_CTRL_WAR 0x11111111
++
++/* local prototypes */
++static si_info_t *si_doattach(si_info_t *sii, uint devid, osl_t *osh, volatile void *regs,
++                              uint bustype, void *sdh, char **vars, uint *varsz);
++static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid, void *sdh);
++static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin,
++	uint *origidx, volatile void *regs);
++
++
++static bool si_pmu_is_ilp_sensitive(uint32 idx, uint regoff);
++
++
++
++/* global variable to indicate reservation/release of gpio's */
++static uint32 si_gpioreservation = 0;
++
++/* global flag to prevent shared resources from being initialized multiple times in si_attach() */
++static bool si_onetimeinit = FALSE;
++
++#ifdef SR_DEBUG
++static const uint32 si_power_island_test_array[] = {
++	0x0000, 0x0001, 0x0010, 0x0011,
++	0x0100, 0x0101, 0x0110, 0x0111,
++	0x1000, 0x1001, 0x1010, 0x1011,
++	0x1100, 0x1101, 0x1110, 0x1111
++};
++#endif /* SR_DEBUG */
++
++int do_4360_pcie2_war = 0;
++
++#ifdef BCMULP
++/* Variable to store boot_type: warm_boot/cold_boot/etc. */
++static int boot_type = 0;
++#endif
++
++/* global kernel resource */
++static si_info_t ksii;
++static si_cores_info_t ksii_cores_info;
++
++static const char rstr_rmin[] = "rmin";
++static const char rstr_rmax[] = "rmax";
++
++/**
++ * Allocate an si handle. This function may be called multiple times.
++ *
++ * devid - pci device id (used to determine chip#)
++ * osh - opaque OS handle
++ * regs - virtual address of initial core registers
++ * bustype - pci/pcmcia/sb/sdio/etc
++ * vars - pointer to a to-be created pointer area for "environment" variables. Some callers of this
++ *        function set 'vars' to NULL, making dereferencing of this parameter undesired.
++ * varsz - pointer to int to return the size of the vars
++ */
++si_t *
++si_attach(uint devid, osl_t *osh, volatile void *regs,
++                       uint bustype, void *sdh, char **vars, uint *varsz)
++{
++	si_info_t *sii;
++	si_cores_info_t *cores_info;
++	/* alloc si_info_t */
++	if ((sii = MALLOCZ(osh, sizeof (si_info_t))) == NULL) {
++		SI_ERROR(("si_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
++		return (NULL);
++	}
++
++	/* alloc si_cores_info_t */
++	if ((cores_info = (si_cores_info_t *)MALLOCZ(osh, sizeof (si_cores_info_t))) == NULL) {
++		SI_ERROR(("si_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
++		MFREE(osh, sii, sizeof(si_info_t));
++		return (NULL);
++	}
++	sii->cores_info = cores_info;
++
++	if (si_doattach(sii, devid, osh, regs, bustype, sdh, vars, varsz) == NULL) {
++		MFREE(osh, sii, sizeof(si_info_t));
++		MFREE(osh, cores_info, sizeof(si_cores_info_t));
++		return (NULL);
++	}
++	sii->vars = vars ? *vars : NULL;
++	sii->varsz = varsz ? *varsz : 0;
++
++	return (si_t *)sii;
++}
++
++
++static uint32	wd_msticks;		/**< watchdog timer ticks normalized to ms */
++
++/** generic kernel variant of si_attach() */
++si_t *
++si_kattach(osl_t *osh)
++{
++	static bool ksii_attached = FALSE;
++	si_cores_info_t *cores_info;
++
++	if (!ksii_attached) {
++		void *regs = NULL;
++		regs = REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
++		cores_info = (si_cores_info_t *)&ksii_cores_info;
++		ksii.cores_info = cores_info;
++
++		ASSERT(osh);
++		if (si_doattach(&ksii, BCM4710_DEVICE_ID, osh, regs,
++		                SI_BUS, NULL,
++		                osh != SI_OSH ? &(ksii.vars) : NULL,
++		                osh != SI_OSH ? &(ksii.varsz) : NULL) == NULL) {
++			SI_ERROR(("si_kattach: si_doattach failed\n"));
++			REG_UNMAP(regs);
++			return NULL;
++		}
++		REG_UNMAP(regs);
++
++		/* save ticks normalized to ms for si_watchdog_ms() */
++		if (PMUCTL_ENAB(&ksii.pub)) {
++			{
++				/* based on 32KHz ILP clock */
++				wd_msticks = 32;
++			}
++		} else {
++			wd_msticks = ALP_CLOCK / 1000;
++		}
++
++		ksii_attached = TRUE;
++		SI_MSG(("si_kattach done. ccrev = %d, wd_msticks = %d\n",
++		        CCREV(ksii.pub.ccrev), wd_msticks));
++	}
++
++	return &ksii.pub;
++}
++
++static bool
++si_buscore_prep(si_info_t *sii, uint bustype, uint devid, void *sdh)
++{
++	BCM_REFERENCE(sdh);
++	BCM_REFERENCE(devid);
++	/* need to set memseg flag for CF card first before any sb registers access */
++	if (BUSTYPE(bustype) == PCMCIA_BUS)
++		sii->memseg = TRUE;
++
++
++#if defined(BCMSDIO)
++	if (BUSTYPE(bustype) == SDIO_BUS) {
++		int err;
++		uint8 clkset;
++
++		/* Try forcing SDIO core to do ALPAvail request only */
++		clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
++		bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
++		if (!err) {
++			uint8 clkval;
++
++			/* If register supported, wait for ALPAvail and then force ALP */
++			clkval = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, NULL);
++			if ((clkval & ~SBSDIO_AVBITS) == clkset) {
++				SPINWAIT(((clkval = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
++					SBSDIO_FUNC1_CHIPCLKCSR, NULL)), !SBSDIO_ALPAV(clkval)),
++					PMU_MAX_TRANSITION_DLY);
++				if (!SBSDIO_ALPAV(clkval)) {
++					SI_ERROR(("timeout on ALPAV wait, clkval 0x%02x\n",
++						clkval));
++					return FALSE;
++				}
++				clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
++				bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
++					clkset, &err);
++				OSL_DELAY(65);
++			}
++		}
++
++		/* Also, disable the extra SDIO pull-ups */
++		bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
++	}
++
++#endif /* BCMSDIO && BCMDONGLEHOST */
++
++	return TRUE;
++}
++
++uint32
++si_get_pmu_reg_addr(si_t *sih, uint32 offset)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint32 pmuaddr = INVALID_ADDR;
++	uint origidx = 0;
++
++	SI_MSG(("%s: pmu access, offset: %x\n", __FUNCTION__, offset));
++	if (!(sii->pub.cccaps & CC_CAP_PMU)) {
++		goto done;
++	}
++	if (AOB_ENAB(&sii->pub)) {
++		uint pmucoreidx;
++		pmuregs_t *pmu;
++		SI_MSG(("%s: AOBENAB: %x\n", __FUNCTION__, offset));
++		origidx = sii->curidx;
++		pmucoreidx = si_findcoreidx(&sii->pub, PMU_CORE_ID, 0);
++		pmu = si_setcoreidx(&sii->pub, pmucoreidx);
++		pmuaddr = (uint32)(uintptr)((volatile uint8*)pmu + offset);
++		si_setcoreidx(sih, origidx);
++	} else
++		pmuaddr = SI_ENUM_BASE + offset;
++
++done:
++	SI_MSG(("%s: addrRET: %x\n", __FUNCTION__, pmuaddr));
++	return pmuaddr;
++}
++
++static bool
++si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin,
++	uint *origidx, volatile void *regs)
++{
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	bool pci, pcie, pcie_gen2 = FALSE;
++	uint i;
++	uint pciidx, pcieidx, pcirev, pcierev;
++
++#if defined(BCM_BACKPLANE_TIMEOUT) || defined(AXI_TIMEOUTS)
++	/* first, enable backplane timeouts */
++	si_slave_wrapper_add(&sii->pub);
++#endif
++	sii->curidx = 0;
++
++	cc = si_setcoreidx(&sii->pub, SI_CC_IDX);
++	ASSERT((uintptr)cc);
++
++	/* get chipcommon rev */
++	sii->pub.ccrev = (int)si_corerev(&sii->pub);
++
++	/* get chipcommon chipstatus */
++	if (CCREV(sii->pub.ccrev) >= 11)
++		sii->pub.chipst = R_REG(sii->osh, &cc->chipstatus);
++
++	/* get chipcommon capabilites */
++	sii->pub.cccaps = R_REG(sii->osh, &cc->capabilities);
++	/* get chipcommon extended capabilities */
++
++	if (CCREV(sii->pub.ccrev) >= 35)
++		sii->pub.cccaps_ext = R_REG(sii->osh, &cc->capabilities_ext);
++
++	/* get pmu rev and caps */
++	if (sii->pub.cccaps & CC_CAP_PMU) {
++		if (AOB_ENAB(&sii->pub)) {
++			uint pmucoreidx;
++			pmuregs_t *pmu;
++			struct si_pub *sih = &sii->pub;
++
++			pmucoreidx = si_findcoreidx(&sii->pub, PMU_CORE_ID, 0);
++			if (!GOODIDX(pmucoreidx)) {
++				SI_ERROR(("si_buscore_setup: si_findcoreidx failed\n"));
++				return FALSE;
++			}
++
++			pmu = si_setcoreidx(&sii->pub, pmucoreidx);
++			sii->pub.pmucaps = R_REG(sii->osh, &pmu->pmucapabilities);
++			si_setcoreidx(&sii->pub, SI_CC_IDX);
++
++			sii->pub.gcirev = si_corereg(sih,
++					GCI_CORE_IDX(sih),
++					GCI_OFFSETOF(sih, gci_corecaps0), 0, 0) & GCI_CAP0_REV_MASK;
++		} else
++			sii->pub.pmucaps = R_REG(sii->osh, &cc->pmucapabilities);
++
++		sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
++	}
++
++	SI_MSG(("Chipc: rev %d, caps 0x%x, chipst 0x%x pmurev %d, pmucaps 0x%x\n",
++		CCREV(sii->pub.ccrev), sii->pub.cccaps, sii->pub.chipst, sii->pub.pmurev,
++		sii->pub.pmucaps));
++
++	/* figure out bus/orignal core idx */
++	sii->pub.buscoretype = NODEV_CORE_ID;
++	sii->pub.buscorerev = (uint)NOREV;
++	sii->pub.buscoreidx = BADIDX;
++
++	pci = pcie = FALSE;
++	pcirev = pcierev = (uint)NOREV;
++	pciidx = pcieidx = BADIDX;
++
++	for (i = 0; i < sii->numcores; i++) {
++		uint cid, crev;
++
++		si_setcoreidx(&sii->pub, i);
++		cid = si_coreid(&sii->pub);
++		crev = si_corerev(&sii->pub);
++
++		/* Display cores found */
++		SI_VMSG(("CORE[%d]: id 0x%x rev %d base 0x%x regs 0x%p\n",
++			i, cid, crev, cores_info->coresba[i], cores_info->regs[i]));
++
++		if (BUSTYPE(bustype) == SI_BUS) {
++			/* now look at the chipstatus register to figure the pacakge */
++			/* for SDIO but downloaded on PCIE dev */
++			if (cid == PCIE2_CORE_ID) {
++				if (BCM43602_CHIP(sii->pub.chip) ||
++					(CHIPID(sii->pub.chip) == BCM4365_CHIP_ID) ||
++					(CHIPID(sii->pub.chip) == BCM4347_CHIP_ID) ||
++					(CHIPID(sii->pub.chip) == BCM4366_CHIP_ID) ||
++					((BCM4345_CHIP(sii->pub.chip) ||
++					BCM4349_CHIP(sii->pub.chip)) &&
++					CST4345_CHIPMODE_PCIE(sii->pub.chipst))) {
++					pcieidx = i;
++					pcierev = crev;
++					pcie = TRUE;
++					pcie_gen2 = TRUE;
++				}
++			}
++
++		} else if (BUSTYPE(bustype) == PCI_BUS) {
++			if (cid == PCI_CORE_ID) {
++				pciidx = i;
++				pcirev = crev;
++				pci = TRUE;
++			} else if ((cid == PCIE_CORE_ID) || (cid == PCIE2_CORE_ID)) {
++				pcieidx = i;
++				pcierev = crev;
++				pcie = TRUE;
++				if (cid == PCIE2_CORE_ID)
++					pcie_gen2 = TRUE;
++			}
++		} else if ((BUSTYPE(bustype) == PCMCIA_BUS) &&
++		           (cid == PCMCIA_CORE_ID)) {
++			sii->pub.buscorerev = crev;
++			sii->pub.buscoretype = cid;
++			sii->pub.buscoreidx = i;
++		}
++#ifdef BCMSDIO
++		else if (((BUSTYPE(bustype) == SDIO_BUS) ||
++		          (BUSTYPE(bustype) == SPI_BUS)) &&
++		         ((cid == PCMCIA_CORE_ID) ||
++		          (cid == SDIOD_CORE_ID))) {
++			sii->pub.buscorerev = crev;
++			sii->pub.buscoretype = cid;
++			sii->pub.buscoreidx = i;
++		}
++#endif /* BCMSDIO */
++
++		/* find the core idx before entering this func. */
++		if ((savewin && (savewin == cores_info->coresba[i])) ||
++		    (regs == cores_info->regs[i]))
++			*origidx = i;
++	}
++
++
++#if defined(PCIE_FULL_DONGLE)
++	if (pcie) {
++		if (pcie_gen2)
++			sii->pub.buscoretype = PCIE2_CORE_ID;
++		else
++			sii->pub.buscoretype = PCIE_CORE_ID;
++		sii->pub.buscorerev = pcierev;
++		sii->pub.buscoreidx = pcieidx;
++	}
++	BCM_REFERENCE(pci);
++	BCM_REFERENCE(pcirev);
++	BCM_REFERENCE(pciidx);
++#else
++	if (pci) {
++		sii->pub.buscoretype = PCI_CORE_ID;
++		sii->pub.buscorerev = pcirev;
++		sii->pub.buscoreidx = pciidx;
++	} else if (pcie) {
++		if (pcie_gen2)
++			sii->pub.buscoretype = PCIE2_CORE_ID;
++		else
++			sii->pub.buscoretype = PCIE_CORE_ID;
++		sii->pub.buscorerev = pcierev;
++		sii->pub.buscoreidx = pcieidx;
++	}
++#endif /* defined(PCIE_FULL_DONGLE) */
++
++	SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx, sii->pub.buscoretype,
++	         sii->pub.buscorerev));
++
++
++#if defined(BCMSDIO)
++	/* Make sure any on-chip ARM is off (in case strapping is wrong), or downloaded code was
++	 * already running.
++	 */
++	if ((BUSTYPE(bustype) == SDIO_BUS) || (BUSTYPE(bustype) == SPI_BUS)) {
++		if (si_setcore(&sii->pub, ARM7S_CORE_ID, 0) ||
++		    si_setcore(&sii->pub, ARMCM3_CORE_ID, 0))
++			si_core_disable(&sii->pub, 0);
++	}
++#endif /* BCMSDIO && BCMDONGLEHOST */
++
++	/* return to the original core */
++	si_setcoreidx(&sii->pub, *origidx);
++
++	return TRUE;
++}
++
++
++
++
++
++uint16
++si_chipid(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++
++	return (sii->chipnew) ? sii->chipnew : sih->chip;
++}
++
++/* CHIP_ID's being mapped here should not be used anywhere else in the code */
++static void
++si_chipid_fixup(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++
++	ASSERT(sii->chipnew == 0);
++	switch (sih->chip) {
++		case BCM43567_CHIP_ID:
++			sii->chipnew = sih->chip; /* save it */
++			sii->pub.chip = BCM43570_CHIP_ID; /* chip class */
++		break;
++		case BCM43562_CHIP_ID:
++		case BCM4358_CHIP_ID:
++		case BCM43566_CHIP_ID:
++			sii->chipnew = sih->chip; /* save it */
++			sii->pub.chip = BCM43569_CHIP_ID; /* chip class */
++		break;
++		case BCM4356_CHIP_ID:
++		case BCM4371_CHIP_ID:
++			sii->chipnew = sih->chip; /* save it */
++			sii->pub.chip = BCM4354_CHIP_ID; /* chip class */
++		break;
++		case BCM4357_CHIP_ID:
++		case BCM4361_CHIP_ID:
++			sii->chipnew = sih->chip; /* save it */
++			sii->pub.chip = BCM4347_CHIP_ID; /* chip class */
++		break;
++		default:
++		break;
++	}
++}
++
++#ifdef BCMULP
++static void
++si_check_boot_type(si_t *sih, osl_t *osh)
++{
++	if (sih->pmurev >= 30) {
++		boot_type = PMU_REG_NEW(sih, swscratch, 0, 0);
++	} else {
++		boot_type = CHIPC_REG(sih, flashdata, 0, 0);
++	}
++
++	SI_ERROR(("%s: boot_type: 0x%08x\n", __func__, boot_type));
++}
++#endif /* BCMULP */
++
++/**
++ * Allocate an si handle. This function may be called multiple times.
++ *
++ * vars - pointer to a to-be created pointer area for "environment" variables. Some callers of this
++ *        function set 'vars' to NULL.
++ */
++static si_info_t *
++si_doattach(si_info_t *sii, uint devid, osl_t *osh, volatile void *regs,
++                       uint bustype, void *sdh, char **vars, uint *varsz)
++{
++	struct si_pub *sih = &sii->pub;
++	uint32 w, savewin;
++	chipcregs_t *cc;
++	char *pvars = NULL;
++	uint origidx;
++#if !defined(_CFEZ_) || defined(CFG_WL)
++#endif 
++
++	ASSERT(GOODREGS(regs));
++
++	savewin = 0;
++
++	sih->buscoreidx = BADIDX;
++	sii->device_removed = FALSE;
++
++	sii->curmap = regs;
++	sii->sdh = sdh;
++	sii->osh = osh;
++	sii->second_bar0win = ~0x0;
++
++#if defined(BCM_BACKPLANE_TIMEOUT)
++	sih->err_info = MALLOCZ(osh, sizeof(si_axi_error_info_t));
++	if (sih->err_info == NULL) {
++		SI_ERROR(("%s: %d bytes MALLOC FAILED",
++			__FUNCTION__, sizeof(si_axi_error_info_t)));
++		return NULL;
++	}
++#endif /* BCM_BACKPLANE_TIMEOUT */
++
++
++	/* check to see if we are a si core mimic'ing a pci core */
++	if ((bustype == PCI_BUS) &&
++	    (OSL_PCI_READ_CONFIG(sii->osh, PCI_SPROM_CONTROL, sizeof(uint32)) == 0xffffffff)) {
++		SI_ERROR(("%s: incoming bus is PCI but it's a lie, switching to SI "
++		          "devid:0x%x\n", __FUNCTION__, devid));
++		bustype = SI_BUS;
++	}
++
++	/* find Chipcommon address */
++	if (bustype == PCI_BUS) {
++		savewin = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
++		if (!GOODCOREADDR(savewin, SI_ENUM_BASE))
++			savewin = SI_ENUM_BASE;
++		OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, SI_ENUM_BASE);
++		if (!regs)
++			return NULL;
++		cc = (chipcregs_t *)regs;
++#ifdef BCMSDIO
++	} else if ((bustype == SDIO_BUS) || (bustype == SPI_BUS)) {
++		cc = (chipcregs_t *)sii->curmap;
++#endif
++	} else {
++		cc = (chipcregs_t *)REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
++	}
++
++	sih->bustype = bustype;
++#ifdef BCMBUSTYPE
++	if (bustype != BUSTYPE(bustype)) {
++		SI_ERROR(("si_doattach: bus type %d does not match configured bus type %d\n",
++			bustype, BUSTYPE(bustype)));
++		return NULL;
++	}
++#endif
++
++	/* bus/core/clk setup for register access */
++	if (!si_buscore_prep(sii, bustype, devid, sdh)) {
++		SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n", bustype));
++		return NULL;
++	}
++
++	/* ChipID recognition.
++	*   We assume we can read chipid at offset 0 from the regs arg.
++	*   If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon),
++	*   some way of recognizing them needs to be added here.
++	*/
++	if (!cc) {
++		SI_ERROR(("%s: chipcommon register space is null \n", __FUNCTION__));
++		return NULL;
++	}
++	w = R_REG(osh, &cc->chipid);
++	if ((w & 0xfffff) == 148277) w -= 65532;
++	sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
++	/* Might as wll fill in chip id rev & pkg */
++	sih->chip = w & CID_ID_MASK;
++	sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;
++	sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;
++
++#if defined(BCMSDIO) && (defined(HW_OOB) || defined(FORCE_WOWLAN))
++	dhd_conf_set_hw_oob_intr(sdh, sih->chip);
++#endif
++
++	si_chipid_fixup(sih);
++
++	sih->issim = IS_SIM(sih->chippkg);
++
++	/* scan for cores */
++	if (CHIPTYPE(sii->pub.socitype) == SOCI_SB) {
++		SI_MSG(("Found chip type SB (0x%08x)\n", w));
++		sb_scan(&sii->pub, regs, devid);
++	} else if ((CHIPTYPE(sii->pub.socitype) == SOCI_AI) ||
++		(CHIPTYPE(sii->pub.socitype) == SOCI_NAI)) {
++		if (CHIPTYPE(sii->pub.socitype) == SOCI_AI)
++			SI_MSG(("Found chip type AI (0x%08x)\n", w));
++		else
++			SI_MSG(("Found chip type NAI (0x%08x)\n", w));
++		/* pass chipc address instead of original core base */
++
++		sii->axi_wrapper = (axi_wrapper_t *)MALLOCZ(sii->osh,
++			(sizeof(axi_wrapper_t) * SI_MAX_AXI_WRAPPERS));
++
++		if (sii->axi_wrapper == NULL) {
++			SI_ERROR(("%s: %zu  bytes MALLOC Failed", __FUNCTION__,
++				(sizeof(axi_wrapper_t) * SI_MAX_AXI_WRAPPERS)));
++			return NULL;
++		}
++
++		ai_scan(&sii->pub, (void *)(uintptr)cc, devid);
++	} else if (CHIPTYPE(sii->pub.socitype) == SOCI_UBUS) {
++		SI_MSG(("Found chip type UBUS (0x%08x), chip id = 0x%4x\n", w, sih->chip));
++		/* pass chipc address instead of original core base */
++		ub_scan(&sii->pub, (void *)(uintptr)cc, devid);
++	} else {
++		SI_ERROR(("Found chip of unknown type (0x%08x)\n", w));
++		return NULL;
++	}
++	/* no cores found, bail out */
++	if (sii->numcores == 0) {
++		SI_ERROR(("si_doattach: could not find any cores\n"));
++		return NULL;
++	}
++	/* bus/core/clk setup */
++	origidx = SI_CC_IDX;
++	if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) {
++		SI_ERROR(("si_doattach: si_buscore_setup failed\n"));
++		goto exit;
++	}
++#ifdef BCMULP
++	si_check_boot_type(sih, osh);
++
++	if (ulp_module_init(osh, sih) != BCME_OK) {
++		ULP_ERR(("%s: err in ulp_module_init\n", __FUNCTION__));
++		goto exit;
++	}
++#endif /* BCMULP */
++
++#if !defined(_CFEZ_) || defined(CFG_WL)
++	/* assume current core is CC */
++	if ((CCREV(sii->pub.ccrev) == 0x25) && ((CHIPID(sih->chip) == BCM43236_CHIP_ID ||
++	                                  CHIPID(sih->chip) == BCM43235_CHIP_ID ||
++	                                  CHIPID(sih->chip) == BCM43234_CHIP_ID ||
++	                                  CHIPID(sih->chip) == BCM43238_CHIP_ID) &&
++	                                 (CHIPREV(sii->pub.chiprev) <= 2))) {
++
++		if ((cc->chipstatus & CST43236_BP_CLK) != 0) {
++			uint clkdiv;
++			clkdiv = R_REG(osh, &cc->clkdiv);
++			/* otp_clk_div is even number, 120/14 < 9mhz */
++			clkdiv = (clkdiv & ~CLKD_OTP) | (14 << CLKD_OTP_SHIFT);
++			W_REG(osh, &cc->clkdiv, clkdiv);
++			SI_ERROR(("%s: set clkdiv to %x\n", __FUNCTION__, clkdiv));
++		}
++		OSL_DELAY(10);
++	}
++
++	if (bustype == PCI_BUS) {
++
++	}
++#endif 
++#ifdef BCM_SDRBL
++	/* 4360 rom bootloader in PCIE case, if the SDR is enabled, But preotection is
++	 * not turned on, then we want to hold arm in reset.
++	 * Bottomline: In sdrenable case, we allow arm to boot only when protection is
++	 * turned on.
++	 */
++	if (CHIP_HOSTIF_PCIE(&(sii->pub))) {
++		uint32 sflags = si_arm_sflags(&(sii->pub));
++
++		/* If SDR is enabled but protection is not turned on
++		* then we want to force arm to WFI.
++		*/
++		if ((sflags & (SISF_SDRENABLE | SISF_TCMPROT)) == SISF_SDRENABLE) {
++			disable_arm_irq();
++			while (1) {
++				hnd_cpu_wait(sih);
++			}
++		}
++	}
++#endif /* BCM_SDRBL */
++
++	pvars = NULL;
++	BCM_REFERENCE(pvars);
++
++	if (!si_onetimeinit) {
++
++
++		if (CCREV(sii->pub.ccrev) >= 20) {
++			uint32 gpiopullup = 0, gpiopulldown = 0;
++			cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
++			ASSERT(cc != NULL);
++
++			/* 4314/43142 has pin muxing, don't clear gpio bits */
++			if ((CHIPID(sih->chip) == BCM4314_CHIP_ID) ||
++				(CHIPID(sih->chip) == BCM43142_CHIP_ID)) {
++				gpiopullup |= 0x402e0;
++				gpiopulldown |= 0x20500;
++			}
++
++
++			W_REG(osh, &cc->gpiopullup, gpiopullup);
++			W_REG(osh, &cc->gpiopulldown, gpiopulldown);
++			si_setcoreidx(sih, origidx);
++		}
++
++	}
++
++	/* clear any previous epidiag-induced target abort */
++	ASSERT(!si_taclear(sih, FALSE));
++
++
++#ifdef BOOTLOADER_CONSOLE_OUTPUT
++	/* Enable console prints */
++	si_muxenab(sii, 3);
++#endif
++
++	return (sii);
++
++exit:
++
++	return NULL;
++}
++
++/** may be called with core in reset */
++void
++si_detach(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint idx;
++
++
++	if (BUSTYPE(sih->bustype) == SI_BUS)
++		for (idx = 0; idx < SI_MAXCORES; idx++)
++			if (cores_info->regs[idx]) {
++				REG_UNMAP(cores_info->regs[idx]);
++				cores_info->regs[idx] = NULL;
++			}
++
++
++#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SI_BUS)
++	if (cores_info != &ksii_cores_info)
++#endif	/* !BCMBUSTYPE || (BCMBUSTYPE == SI_BUS) */
++		MFREE(sii->osh, cores_info, sizeof(si_cores_info_t));
++
++#if defined(BCM_BACKPLANE_TIMEOUT)
++	if (sih->err_info) {
++		MFREE(sii->osh, sih->err_info, sizeof(si_axi_error_info_t));
++		sii->pub.err_info = NULL;
++	}
++#endif /* BCM_BACKPLANE_TIMEOUT */
++
++	if (sii->axi_wrapper) {
++		MFREE(sii->osh, sii->axi_wrapper,
++			(sizeof(axi_wrapper_t) * SI_MAX_AXI_WRAPPERS));
++		sii->axi_wrapper = NULL;
++	}
++
++#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SI_BUS)
++	if (sii != &ksii)
++#endif	/* !BCMBUSTYPE || (BCMBUSTYPE == SI_BUS) */
++		MFREE(sii->osh, sii, sizeof(si_info_t));
++}
++
++void *
++si_osh(si_t *sih)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++	return sii->osh;
++}
++
++void
++si_setosh(si_t *sih, osl_t *osh)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++	if (sii->osh != NULL) {
++		SI_ERROR(("osh is already set....\n"));
++		ASSERT(!sii->osh);
++	}
++	sii->osh = osh;
++}
++
++/** register driver interrupt disabling and restoring callback functions */
++void
++si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
++                          void *intrsenabled_fn, void *intr_arg)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	sii->intr_arg = intr_arg;
++	sii->intrsoff_fn = (si_intrsoff_t)intrsoff_fn;
++	sii->intrsrestore_fn = (si_intrsrestore_t)intrsrestore_fn;
++	sii->intrsenabled_fn = (si_intrsenabled_t)intrsenabled_fn;
++	/* save current core id.  when this function called, the current core
++	 * must be the core which provides driver functions(il, et, wl, etc.)
++	 */
++	sii->dev_coreid = cores_info->coreid[sii->curidx];
++}
++
++void
++si_deregister_intr_callback(si_t *sih)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++	sii->intrsoff_fn = NULL;
++	sii->intrsrestore_fn = NULL;
++	sii->intrsenabled_fn = NULL;
++}
++
++uint
++si_intflag(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_intflag(sih);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return R_REG(sii->osh, ((uint32 *)(uintptr)
++			    (sii->oob_router + OOB_STATUSA)));
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++uint
++si_flag(si_t *sih)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_flag(sih);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_flag(sih);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_flag(sih);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++uint
++si_flag_alt(si_t *sih)
++{
++	if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_flag_alt(sih);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++void
++si_setint(si_t *sih, int siflag)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		sb_setint(sih, siflag);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		ai_setint(sih, siflag);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		ub_setint(sih, siflag);
++	else
++		ASSERT(0);
++}
++
++uint
++si_coreid(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	return cores_info->coreid[sii->curidx];
++}
++
++uint
++si_coreidx(si_t *sih)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++	return sii->curidx;
++}
++
++volatile void *
++si_d11_switch_addrbase(si_t *sih, uint coreunit)
++{
++	return si_setcore(sih,  D11_CORE_ID, coreunit);
++}
++
++/** return the core-type instantiation # of the current core */
++uint
++si_coreunit(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint idx;
++	uint coreid;
++	uint coreunit;
++	uint i;
++
++	coreunit = 0;
++
++	idx = sii->curidx;
++
++	ASSERT(GOODREGS(sii->curmap));
++	coreid = si_coreid(sih);
++
++	/* count the cores of our type */
++	for (i = 0; i < idx; i++)
++		if (cores_info->coreid[i] == coreid)
++			coreunit++;
++
++	return (coreunit);
++}
++
++uint
++si_corevendor(si_t *sih)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_corevendor(sih);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_corevendor(sih);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_corevendor(sih);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++bool
++si_backplane64(si_t *sih)
++{
++	return ((sih->cccaps & CC_CAP_BKPLN64) != 0);
++}
++
++uint
++si_corerev(si_t *sih)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_corerev(sih);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_corerev(sih);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_corerev(sih);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++/* return index of coreid or BADIDX if not found */
++uint
++si_findcoreidx(si_t *sih, uint coreid, uint coreunit)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint found;
++	uint i;
++
++
++	found = 0;
++
++	for (i = 0; i < sii->numcores; i++)
++		if (cores_info->coreid[i] == coreid) {
++			if (found == coreunit)
++				return (i);
++			found++;
++		}
++
++	return (BADIDX);
++}
++
++/** return total coreunit of coreid or zero if not found */
++uint
++si_numcoreunits(si_t *sih, uint coreid)
++{
++	if ((CHIPID(sih->chip) == BCM4347_CHIP_ID) &&
++		(CHIPREV(sih->chiprev) == 0)) {
++		/*
++		  * 4347TC2 does not have Aux core.
++		  * fixed to 1 here because EROM (using 4349 EROM) has two entries
++		  */
++		return 1;
++	} else	{
++		si_info_t *sii = SI_INFO(sih);
++		si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++		uint found = 0;
++		uint i;
++
++		for (i = 0; i < sii->numcores; i++) {
++			if (cores_info->coreid[i] == coreid) {
++				found++;
++			}
++		}
++
++		return found;
++	}
++}
++
++/** return total D11 coreunits */
++uint
++BCMRAMFN(si_numd11coreunits)(si_t *sih)
++{
++	uint found = 0;
++
++	found = si_numcoreunits(sih, D11_CORE_ID);
++
++#if defined(WLRSDB) && defined(WLRSDB_DISABLED)
++	/* If RSDB functionality is compiled out,
++	 * then ignore any D11 cores beyond the first
++	 * Used in norsdb dongle build variants for rsdb chip.
++	 */
++	found = 1;
++#endif /* defined(WLRSDB) && !defined(WLRSDB_DISABLED) */
++
++	return found;
++}
++
++/** return list of found cores */
++uint
++si_corelist(si_t *sih, uint coreid[])
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	bcopy((uchar*)cores_info->coreid, (uchar*)coreid, (sii->numcores * sizeof(uint)));
++	return (sii->numcores);
++}
++
++/** return current wrapper mapping */
++void *
++si_wrapperregs(si_t *sih)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++	ASSERT(GOODREGS(sii->curwrap));
++
++	return (sii->curwrap);
++}
++
++/** return current register mapping */
++volatile void *
++si_coreregs(si_t *sih)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++	ASSERT(GOODREGS(sii->curmap));
++
++	return (sii->curmap);
++}
++
++
++/**
++ * This function changes logical "focus" to the indicated core;
++ * must be called with interrupts off.
++ * Moreover, callers should keep interrupts off during switching out of and back to d11 core
++ */
++volatile void *
++si_setcore(si_t *sih, uint coreid, uint coreunit)
++{
++	uint idx;
++
++	idx = si_findcoreidx(sih, coreid, coreunit);
++	if (!GOODIDX(idx))
++		return (NULL);
++
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_setcoreidx(sih, idx);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_setcoreidx(sih, idx);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_setcoreidx(sih, idx);
++	else {
++		ASSERT(0);
++		return NULL;
++	}
++}
++
++volatile void *
++si_setcoreidx(si_t *sih, uint coreidx)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_setcoreidx(sih, coreidx);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_setcoreidx(sih, coreidx);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_setcoreidx(sih, coreidx);
++	else {
++		ASSERT(0);
++		return NULL;
++	}
++}
++
++/** Turn off interrupt as required by sb_setcore, before switch core */
++volatile void *
++si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val)
++{
++	volatile void *cc;
++	si_info_t *sii = SI_INFO(sih);
++
++	if (SI_FAST(sii)) {
++		/* Overloading the origidx variable to remember the coreid,
++		 * this works because the core ids cannot be confused with
++		 * core indices.
++		 */
++		*origidx = coreid;
++		if (coreid == CC_CORE_ID)
++			return (volatile void *)CCREGS_FAST(sii);
++		else if (coreid == BUSCORETYPE(sih->buscoretype))
++			return (volatile void *)PCIEREGS(sii);
++	}
++	INTR_OFF(sii, *intr_val);
++	*origidx = sii->curidx;
++	cc = si_setcore(sih, coreid, 0);
++	ASSERT(cc != NULL);
++
++	return cc;
++}
++
++/* restore coreidx and restore interrupt */
++void
++si_restore_core(si_t *sih, uint coreid, uint intr_val)
++{
++	si_info_t *sii = SI_INFO(sih);
++
++	if (SI_FAST(sii) && ((coreid == CC_CORE_ID) || (coreid == BUSCORETYPE(sih->buscoretype))))
++		return;
++
++	si_setcoreidx(sih, coreid);
++	INTR_RESTORE(sii, intr_val);
++}
++
++int
++si_numaddrspaces(si_t *sih)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_numaddrspaces(sih);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_numaddrspaces(sih);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_numaddrspaces(sih);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++uint32
++si_addrspace(si_t *sih, uint asidx)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_addrspace(sih, asidx);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_addrspace(sih, asidx);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_addrspace(sih, asidx);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++uint32
++si_addrspacesize(si_t *sih, uint asidx)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_addrspacesize(sih, asidx);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_addrspacesize(sih, asidx);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_addrspacesize(sih, asidx);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++void
++si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size)
++{
++	/* Only supported for SOCI_AI */
++	if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		ai_coreaddrspaceX(sih, asidx, addr, size);
++	else
++		*size = 0;
++}
++
++uint32
++si_core_cflags(si_t *sih, uint32 mask, uint32 val)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_core_cflags(sih, mask, val);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_core_cflags(sih, mask, val);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_core_cflags(sih, mask, val);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++void
++si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		sb_core_cflags_wo(sih, mask, val);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		ai_core_cflags_wo(sih, mask, val);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		ub_core_cflags_wo(sih, mask, val);
++	else
++		ASSERT(0);
++}
++
++uint32
++si_core_sflags(si_t *sih, uint32 mask, uint32 val)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_core_sflags(sih, mask, val);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_core_sflags(sih, mask, val);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_core_sflags(sih, mask, val);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++void
++si_commit(si_t *sih)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		sb_commit(sih);
++	else if (CHIPTYPE(sih->socitype) == SOCI_AI || CHIPTYPE(sih->socitype) == SOCI_NAI)
++		;
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		;
++	else {
++		ASSERT(0);
++	}
++}
++
++bool
++si_iscoreup(si_t *sih)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_iscoreup(sih);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_iscoreup(sih);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_iscoreup(sih);
++	else {
++		ASSERT(0);
++		return FALSE;
++	}
++}
++
++uint
++si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val)
++{
++	/* only for AI back plane chips */
++	if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return (ai_wrap_reg(sih, offset, mask, val));
++	return 0;
++}
++/* si_backplane_access is used to read full backplane address from host for PCIE FD
++ * it uses secondary bar-0 window which lies at an offset of 16K from primary bar-0
++ * Provides support for read/write of 1/2/4 bytes of backplane address
++ * Can be used to read/write
++ *	1. core regs
++ *	2. Wrapper regs
++ *	3. memory
++ *	4. BT area
++ * For accessing any 32 bit backplane address, [31 : 12] of backplane should be given in "region"
++ * [11 : 0] should be the "regoff"
++ * for reading  4 bytes from reg 0x200 of d11 core use it like below
++ * : si_backplane_access(sih, 0x18001000, 0x200, 4, 0, TRUE)
++ */
++static int si_backplane_addr_sane(uint addr, uint size)
++{
++	int bcmerror = BCME_OK;
++
++	/* For 2 byte access, address has to be 2 byte aligned */
++	if (size == 2) {
++		if (addr & 0x1) {
++			bcmerror = BCME_ERROR;
++		}
++	}
++	/* For 4 byte access, address has to be 4 byte aligned */
++	if (size == 4) {
++		if (addr & 0x3) {
++			bcmerror = BCME_ERROR;
++		}
++	}
++	return bcmerror;
++}
++
++void
++si_invalidate_second_bar0win(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	sii->second_bar0win = ~0x0;
++}
++
++uint
++si_backplane_access(si_t *sih, uint addr, uint size, uint *val, bool read)
++{
++	volatile uint32 *r = NULL;
++	uint32 region = 0;
++	si_info_t *sii = SI_INFO(sih);
++
++	/* Valid only for pcie bus */
++	if (BUSTYPE(sih->bustype) != PCI_BUS) {
++		SI_ERROR(("Valid only for pcie bus \n"));
++		return BCME_ERROR;
++	}
++
++	/* Split adrr into region and address offset */
++	region = (addr & (0xFFFFF << 12));
++	addr = addr & 0xFFF;
++
++	/* check for address and size sanity */
++	if (si_backplane_addr_sane(addr, size) != BCME_OK)
++		return BCME_ERROR;
++
++	/* Update window if required */
++	if (sii->second_bar0win != region) {
++		OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_CORE2_WIN, 4, region);
++		sii->second_bar0win = region;
++	}
++
++	/* Estimate effective address
++	 * sii->curmap   : bar-0 virtual address
++	 * PCI_SECOND_BAR0_OFFSET  : secondar bar-0 offset
++	 * regoff : actual reg offset
++	 */
++	r = (volatile uint32 *)((volatile char *)sii->curmap + PCI_SECOND_BAR0_OFFSET + addr);
++
++	SI_VMSG(("si curmap %p  region %x regaddr %x effective addr %p READ %d\n",
++		(volatile char*)sii->curmap, region, addr, r, read));
++
++	switch (size) {
++		case sizeof(uint8) :
++			if (read)
++				*val = R_REG(sii->osh, (volatile uint8*)r);
++			else
++				W_REG(sii->osh, (volatile uint8*)r, *val);
++			break;
++		case sizeof(uint16) :
++			if (read)
++				*val = R_REG(sii->osh, (volatile uint16*)r);
++			else
++				W_REG(sii->osh, (volatile uint16*)r, *val);
++			break;
++		case sizeof(uint32) :
++			if (read)
++				*val = R_REG(sii->osh, (volatile uint32*)r);
++			else
++				W_REG(sii->osh, (volatile uint32*)r, *val);
++			break;
++		default :
++			SI_ERROR(("Invalid  size %d \n", size));
++			return (BCME_ERROR);
++			break;
++	}
++
++	return (BCME_OK);
++}
++uint
++si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_corereg(sih, coreidx, regoff, mask, val);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_corereg(sih, coreidx, regoff, mask, val);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_corereg(sih, coreidx, regoff, mask, val);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++/** ILP sensitive register access needs special treatment to avoid backplane stalls */
++bool si_pmu_is_ilp_sensitive(uint32 idx, uint regoff)
++{
++	if (idx == SI_CC_IDX) {
++		if (CHIPCREGS_ILP_SENSITIVE(regoff))
++			return TRUE;
++	} else if (PMUREGS_ILP_SENSITIVE(regoff)) {
++		return TRUE;
++	}
++
++	return FALSE;
++}
++
++/** 'idx' should refer either to the chipcommon core or the PMU core */
++uint
++si_pmu_corereg(si_t *sih, uint32 idx, uint regoff, uint mask, uint val)
++{
++	int pmustatus_offset;
++
++	/* prevent backplane stall on double write to 'ILP domain' registers in the PMU */
++	if (mask != 0 && PMUREV(sih->pmurev) >= 22 &&
++	    si_pmu_is_ilp_sensitive(idx, regoff)) {
++		pmustatus_offset = AOB_ENAB(sih) ? OFFSETOF(pmuregs_t, pmustatus) :
++			OFFSETOF(chipcregs_t, pmustatus);
++
++		while (si_corereg(sih, idx, pmustatus_offset, 0, 0) & PST_SLOW_WR_PENDING)
++			{};
++	}
++
++	return si_corereg(sih, idx, regoff, mask, val);
++}
++
++/*
++ * If there is no need for fiddling with interrupts or core switches (typically silicon
++ * back plane registers, pci registers and chipcommon registers), this function
++ * returns the register offset on this core to a mapped address. This address can
++ * be used for W_REG/R_REG directly.
++ *
++ * For accessing registers that would need a core switch, this function will return
++ * NULL.
++ */
++volatile uint32 *
++si_corereg_addr(si_t *sih, uint coreidx, uint regoff)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_corereg_addr(sih, coreidx, regoff);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_corereg_addr(sih, coreidx, regoff);
++	else {
++		return 0;
++	}
++}
++
++void
++si_core_disable(si_t *sih, uint32 bits)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		sb_core_disable(sih, bits);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		ai_core_disable(sih, bits);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		ub_core_disable(sih, bits);
++}
++
++void
++si_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		sb_core_reset(sih, bits, resetbits);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		ai_core_reset(sih, bits, resetbits);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		ub_core_reset(sih, bits, resetbits);
++}
++
++/** Run bist on current core. Caller needs to take care of core-specific bist hazards */
++int
++si_corebist(si_t *sih)
++{
++	uint32 cflags;
++	int result = 0;
++
++	/* Read core control flags */
++	cflags = si_core_cflags(sih, 0, 0);
++
++	/* Set bist & fgc */
++	si_core_cflags(sih, ~0, (SICF_BIST_EN | SICF_FGC));
++
++	/* Wait for bist done */
++	SPINWAIT(((si_core_sflags(sih, 0, 0) & SISF_BIST_DONE) == 0), 100000);
++
++	if (si_core_sflags(sih, 0, 0) & SISF_BIST_ERROR)
++		result = BCME_ERROR;
++
++	/* Reset core control flags */
++	si_core_cflags(sih, 0xffff, cflags);
++
++	return result;
++}
++
++uint
++si_num_slaveports(si_t *sih, uint coreid)
++{
++	uint idx = si_findcoreidx(sih, coreid, 0);
++	uint num = 0;
++
++	if ((CHIPTYPE(sih->socitype) == SOCI_AI))
++		num = ai_num_slaveports(sih, idx);
++
++	return num;
++}
++
++uint32
++si_get_slaveport_addr(si_t *sih, uint asidx, uint core_id, uint coreunit)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint origidx = sii->curidx;
++	uint32 addr = 0x0;
++
++	if (!((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI)))
++		goto done;
++
++	si_setcore(sih, core_id, coreunit);
++
++	addr = ai_addrspace(sih, asidx);
++
++	si_setcoreidx(sih, origidx);
++
++done:
++	return addr;
++}
++
++uint32
++si_get_d11_slaveport_addr(si_t *sih, uint asidx, uint coreunit)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint origidx = sii->curidx;
++	uint32 addr = 0x0;
++
++	if (!((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI)))
++		goto done;
++
++	si_setcore(sih, D11_CORE_ID, coreunit);
++
++	addr = ai_addrspace(sih, asidx);
++
++	si_setcoreidx(sih, origidx);
++
++done:
++	return addr;
++}
++
++static uint32
++factor6(uint32 x)
++{
++	switch (x) {
++	case CC_F6_2:	return 2;
++	case CC_F6_3:	return 3;
++	case CC_F6_4:	return 4;
++	case CC_F6_5:	return 5;
++	case CC_F6_6:	return 6;
++	case CC_F6_7:	return 7;
++	default:	return 0;
++	}
++}
++
++/*
++ * Divide the clock by the divisor with protection for
++ * a zero divisor.
++ */
++static uint32
++divide_clock(uint32 clock, uint32 div)
++{
++	return div ? clock / div : 0;
++}
++
++
++/** calculate the speed the SI would run at given a set of clockcontrol values */
++uint32
++si_clock_rate(uint32 pll_type, uint32 n, uint32 m)
++{
++	uint32 n1, n2, clock, m1, m2, m3, mc;
++
++	n1 = n & CN_N1_MASK;
++	n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
++
++	if (pll_type == PLL_TYPE6) {
++		if (m & CC_T6_MMASK)
++			return CC_T6_M1;
++		else
++			return CC_T6_M0;
++	} else if ((pll_type == PLL_TYPE1) ||
++	           (pll_type == PLL_TYPE3) ||
++	           (pll_type == PLL_TYPE4) ||
++	           (pll_type == PLL_TYPE7)) {
++		n1 = factor6(n1);
++		n2 += CC_F5_BIAS;
++	} else if (pll_type == PLL_TYPE2) {
++		n1 += CC_T2_BIAS;
++		n2 += CC_T2_BIAS;
++		ASSERT((n1 >= 2) && (n1 <= 7));
++		ASSERT((n2 >= 5) && (n2 <= 23));
++	} else if (pll_type == PLL_TYPE5) {
++		return (100000000);
++	} else
++		ASSERT(0);
++	/* PLL types 3 and 7 use BASE2 (25Mhz) */
++	if ((pll_type == PLL_TYPE3) ||
++	    (pll_type == PLL_TYPE7)) {
++		clock = CC_CLOCK_BASE2 * n1 * n2;
++	} else
++		clock = CC_CLOCK_BASE1 * n1 * n2;
++
++	if (clock == 0)
++		return 0;
++
++	m1 = m & CC_M1_MASK;
++	m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
++	m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
++	mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
++
++	if ((pll_type == PLL_TYPE1) ||
++	    (pll_type == PLL_TYPE3) ||
++	    (pll_type == PLL_TYPE4) ||
++	    (pll_type == PLL_TYPE7)) {
++		m1 = factor6(m1);
++		if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
++			m2 += CC_F5_BIAS;
++		else
++			m2 = factor6(m2);
++		m3 = factor6(m3);
++
++		switch (mc) {
++		case CC_MC_BYPASS:	return (clock);
++		case CC_MC_M1:		return divide_clock(clock, m1);
++		case CC_MC_M1M2:	return divide_clock(clock, m1 * m2);
++		case CC_MC_M1M2M3:	return divide_clock(clock, m1 * m2 * m3);
++		case CC_MC_M1M3:	return divide_clock(clock, m1 * m3);
++		default:		return (0);
++		}
++	} else {
++		ASSERT(pll_type == PLL_TYPE2);
++
++		m1 += CC_T2_BIAS;
++		m2 += CC_T2M2_BIAS;
++		m3 += CC_T2_BIAS;
++		ASSERT((m1 >= 2) && (m1 <= 7));
++		ASSERT((m2 >= 3) && (m2 <= 10));
++		ASSERT((m3 >= 2) && (m3 <= 7));
++
++		if ((mc & CC_T2MC_M1BYP) == 0)
++			clock /= m1;
++		if ((mc & CC_T2MC_M2BYP) == 0)
++			clock /= m2;
++		if ((mc & CC_T2MC_M3BYP) == 0)
++			clock /= m3;
++
++		return (clock);
++	}
++}
++
++/**
++ * Some chips could have multiple host interfaces, however only one will be active.
++ * For a given chip. Depending pkgopt and cc_chipst return the active host interface.
++ */
++uint
++si_chip_hostif(si_t *sih)
++{
++	uint hosti = 0;
++
++	switch (CHIPID(sih->chip)) {
++	case BCM43018_CHIP_ID:
++	case BCM43430_CHIP_ID:
++		hosti = CHIP_HOSTIF_SDIOMODE;
++		break;
++	case BCM43012_CHIP_ID:
++		hosti = CHIP_HOSTIF_SDIOMODE;
++		break;
++	CASE_BCM43602_CHIP:
++		hosti = CHIP_HOSTIF_PCIEMODE;
++		break;
++
++	case BCM4360_CHIP_ID:
++		/* chippkg bit-0 == 0 is PCIE only pkgs
++		 * chippkg bit-0 == 1 has both PCIE and USB cores enabled
++		 */
++		if ((sih->chippkg & 0x1) && (sih->chipst & CST4360_MODE_USB))
++			hosti = CHIP_HOSTIF_USBMODE;
++		else
++			hosti = CHIP_HOSTIF_PCIEMODE;
++
++		break;
++
++	case BCM4335_CHIP_ID:
++		/* TBD: like in 4360, do we need to check pkg? */
++		if (CST4335_CHIPMODE_USB20D(sih->chipst))
++			hosti = CHIP_HOSTIF_USBMODE;
++		else if (CST4335_CHIPMODE_SDIOD(sih->chipst))
++			hosti = CHIP_HOSTIF_SDIOMODE;
++		else
++			hosti = CHIP_HOSTIF_PCIEMODE;
++		break;
++
++	CASE_BCM4345_CHIP:
++		if (CST4345_CHIPMODE_USB20D(sih->chipst) || CST4345_CHIPMODE_HSIC(sih->chipst))
++			hosti = CHIP_HOSTIF_USBMODE;
++		else if (CST4345_CHIPMODE_SDIOD(sih->chipst))
++			hosti = CHIP_HOSTIF_SDIOMODE;
++		else if (CST4345_CHIPMODE_PCIE(sih->chipst))
++			hosti = CHIP_HOSTIF_PCIEMODE;
++		break;
++
++	case BCM4349_CHIP_GRPID:
++	case BCM53573_CHIP_GRPID:
++		if (CST4349_CHIPMODE_SDIOD(sih->chipst))
++			hosti = CHIP_HOSTIF_SDIOMODE;
++		else if (CST4349_CHIPMODE_PCIE(sih->chipst))
++			hosti = CHIP_HOSTIF_PCIEMODE;
++		break;
++	case BCM4347_CHIP_ID:
++		 if (CST4347_CHIPMODE_SDIOD(sih->chipst))
++			 hosti = CHIP_HOSTIF_SDIOMODE;
++		 else if (CST4347_CHIPMODE_PCIE(sih->chipst))
++			 hosti = CHIP_HOSTIF_PCIEMODE;
++		 break;
++
++	case BCM4350_CHIP_ID:
++	case BCM4354_CHIP_ID:
++	case BCM43556_CHIP_ID:
++	case BCM43558_CHIP_ID:
++	case BCM43566_CHIP_ID:
++	case BCM43568_CHIP_ID:
++	case BCM43569_CHIP_ID:
++	case BCM43570_CHIP_ID:
++	case BCM4358_CHIP_ID:
++		if (CST4350_CHIPMODE_USB20D(sih->chipst) ||
++		    CST4350_CHIPMODE_HSIC20D(sih->chipst) ||
++		    CST4350_CHIPMODE_USB30D(sih->chipst) ||
++		    CST4350_CHIPMODE_USB30D_WL(sih->chipst) ||
++		    CST4350_CHIPMODE_HSIC30D(sih->chipst))
++			hosti = CHIP_HOSTIF_USBMODE;
++		else if (CST4350_CHIPMODE_SDIOD(sih->chipst))
++			hosti = CHIP_HOSTIF_SDIOMODE;
++		else if (CST4350_CHIPMODE_PCIE(sih->chipst))
++			hosti = CHIP_HOSTIF_PCIEMODE;
++		break;
++
++	default:
++		break;
++	}
++
++	return hosti;
++}
++
++
++/** set chip watchdog reset timer to fire in 'ticks' */
++void
++si_watchdog(si_t *sih, uint ticks)
++{
++	uint nb, maxt;
++	uint pmu_wdt = 1;
++
++
++	if (PMUCTL_ENAB(sih) && pmu_wdt) {
++			nb = (CCREV(sih->ccrev) < 26) ? 16 : ((CCREV(sih->ccrev) >= 37) ? 32 : 24);
++		/* The mips compiler uses the sllv instruction,
++		 * so we specially handle the 32-bit case.
++		 */
++		if (nb == 32)
++			maxt = 0xffffffff;
++		else
++			maxt = ((1 << nb) - 1);
++
++		if (ticks == 1)
++			ticks = 2;
++		else if (ticks > maxt)
++			ticks = maxt;
++		if (CHIPID(sih->chip) == BCM43012_CHIP_ID) {
++			PMU_REG_NEW(sih, min_res_mask, ~0, DEFAULT_43012_MIN_RES_MASK);
++			PMU_REG_NEW(sih, watchdog_res_mask, ~0, DEFAULT_43012_MIN_RES_MASK);
++			PMU_REG_NEW(sih, pmustatus, PST_WDRESET, PST_WDRESET);
++			PMU_REG_NEW(sih, pmucontrol_ext, PCTL_EXT_FASTLPO_SWENAB, 0);
++			SPINWAIT((PMU_REG(sih, pmustatus, 0, 0) & PST_ILPFASTLPO),
++				PMU_MAX_TRANSITION_DLY);
++		}
++
++		pmu_corereg(sih, SI_CC_IDX, pmuwatchdog, ~0, ticks);
++	} else {
++		maxt = (1 << 28) - 1;
++		if (ticks > maxt)
++			ticks = maxt;
++
++		si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
++	}
++}
++
++/** trigger watchdog reset after ms milliseconds */
++void
++si_watchdog_ms(si_t *sih, uint32 ms)
++{
++	si_watchdog(sih, wd_msticks * ms);
++}
++
++uint32 si_watchdog_msticks(void)
++{
++	return wd_msticks;
++}
++
++bool
++si_taclear(si_t *sih, bool details)
++{
++	return FALSE;
++}
++
++
++
++/** return the slow clock source - LPO, XTAL, or PCI */
++static uint
++si_slowclk_src(si_info_t *sii)
++{
++	chipcregs_t *cc;
++
++	ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
++
++	if (CCREV(sii->pub.ccrev) < 6) {
++		if ((BUSTYPE(sii->pub.bustype) == PCI_BUS) &&
++		    (OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32)) &
++		     PCI_CFG_GPIO_SCS))
++			return (SCC_SS_PCI);
++		else
++			return (SCC_SS_XTAL);
++	} else if (CCREV(sii->pub.ccrev) < 10) {
++		cc = (chipcregs_t *)si_setcoreidx(&sii->pub, sii->curidx);
++		ASSERT(cc);
++		return (R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK);
++	} else	/* Insta-clock */
++		return (SCC_SS_XTAL);
++}
++
++/** return the ILP (slowclock) min or max frequency */
++static uint
++si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
++{
++	uint32 slowclk;
++	uint div;
++
++	ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
++
++	/* shouldn't be here unless we've established the chip has dynamic clk control */
++	ASSERT(R_REG(sii->osh, &cc->capabilities) & CC_CAP_PWR_CTL);
++
++	slowclk = si_slowclk_src(sii);
++	if (CCREV(sii->pub.ccrev) < 6) {
++		if (slowclk == SCC_SS_PCI)
++			return (max_freq ? (PCIMAXFREQ / 64) : (PCIMINFREQ / 64));
++		else
++			return (max_freq ? (XTALMAXFREQ / 32) : (XTALMINFREQ / 32));
++	} else if (CCREV(sii->pub.ccrev) < 10) {
++		div = 4 *
++		        (((R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
++		if (slowclk == SCC_SS_LPO)
++			return (max_freq ? LPOMAXFREQ : LPOMINFREQ);
++		else if (slowclk == SCC_SS_XTAL)
++			return (max_freq ? (XTALMAXFREQ / div) : (XTALMINFREQ / div));
++		else if (slowclk == SCC_SS_PCI)
++			return (max_freq ? (PCIMAXFREQ / div) : (PCIMINFREQ / div));
++		else
++			ASSERT(0);
++	} else {
++		/* Chipc rev 10 is InstaClock */
++		div = R_REG(sii->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;
++		div = 4 * (div + 1);
++		return (max_freq ? XTALMAXFREQ : (XTALMINFREQ / div));
++	}
++	return (0);
++}
++
++static void
++si_clkctl_setdelay(si_info_t *sii, void *chipcregs)
++{
++	chipcregs_t *cc = (chipcregs_t *)chipcregs;
++	uint slowmaxfreq, pll_delay, slowclk;
++	uint pll_on_delay, fref_sel_delay;
++
++	pll_delay = PLL_DELAY;
++
++	/* If the slow clock is not sourced by the xtal then add the xtal_on_delay
++	 * since the xtal will also be powered down by dynamic clk control logic.
++	 */
++
++	slowclk = si_slowclk_src(sii);
++	if (slowclk != SCC_SS_XTAL)
++		pll_delay += XTAL_ON_DELAY;
++
++	/* Starting with 4318 it is ILP that is used for the delays */
++	slowmaxfreq = si_slowclk_freq(sii, (CCREV(sii->pub.ccrev) >= 10) ? FALSE : TRUE, cc);
++
++	pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
++	fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
++
++	W_REG(sii->osh, &cc->pll_on_delay, pll_on_delay);
++	W_REG(sii->osh, &cc->fref_sel_delay, fref_sel_delay);
++}
++
++/** initialize power control delay registers */
++void
++si_clkctl_init(si_t *sih)
++{
++	si_info_t *sii;
++	uint origidx = 0;
++	chipcregs_t *cc;
++	bool fast;
++
++	if (!CCCTL_ENAB(sih))
++		return;
++
++	sii = SI_INFO(sih);
++	fast = SI_FAST(sii);
++	if (!fast) {
++		origidx = sii->curidx;
++		if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL)
++			return;
++	} else if ((cc = (chipcregs_t *)CCREGS_FAST(sii)) == NULL)
++		return;
++	ASSERT(cc != NULL);
++
++	/* set all Instaclk chip ILP to 1 MHz */
++	if (CCREV(sih->ccrev) >= 10)
++		SET_REG(sii->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
++		        (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
++
++	si_clkctl_setdelay(sii, (void *)(uintptr)cc);
++
++	OSL_DELAY(20000);
++
++	if (!fast)
++		si_setcoreidx(sih, origidx);
++}
++
++
++/** change logical "focus" to the gpio core for optimized access */
++volatile void *
++si_gpiosetcore(si_t *sih)
++{
++	return (si_setcoreidx(sih, SI_CC_IDX));
++}
++
++/**
++ * mask & set gpiocontrol bits.
++ * If a gpiocontrol bit is set to 0, chipcommon controls the corresponding GPIO pin.
++ * If a gpiocontrol bit is set to 1, the GPIO pin is no longer a GPIO and becomes dedicated
++ *   to some chip-specific purpose.
++ */
++uint32
++si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority)
++{
++	uint regoff;
++
++	regoff = 0;
++
++	/* gpios could be shared on router platforms
++	 * ignore reservation if it's high priority (e.g., test apps)
++	 */
++	if ((priority != GPIO_HI_PRIORITY) &&
++	    (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
++		mask = priority ? (si_gpioreservation & mask) :
++			((si_gpioreservation | mask) & ~(si_gpioreservation));
++		val &= mask;
++	}
++
++	regoff = OFFSETOF(chipcregs_t, gpiocontrol);
++	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
++}
++
++/** mask&set gpio output enable bits */
++uint32
++si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority)
++{
++	uint regoff;
++
++	regoff = 0;
++
++	/* gpios could be shared on router platforms
++	 * ignore reservation if it's high priority (e.g., test apps)
++	 */
++	if ((priority != GPIO_HI_PRIORITY) &&
++	    (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
++		mask = priority ? (si_gpioreservation & mask) :
++			((si_gpioreservation | mask) & ~(si_gpioreservation));
++		val &= mask;
++	}
++
++	regoff = OFFSETOF(chipcregs_t, gpioouten);
++	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
++}
++
++/** mask&set gpio output bits */
++uint32
++si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority)
++{
++	uint regoff;
++
++	regoff = 0;
++
++	/* gpios could be shared on router platforms
++	 * ignore reservation if it's high priority (e.g., test apps)
++	 */
++	if ((priority != GPIO_HI_PRIORITY) &&
++	    (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
++		mask = priority ? (si_gpioreservation & mask) :
++			((si_gpioreservation | mask) & ~(si_gpioreservation));
++		val &= mask;
++	}
++
++	regoff = OFFSETOF(chipcregs_t, gpioout);
++	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
++}
++
++/** reserve one gpio */
++uint32
++si_gpioreserve(si_t *sih, uint32 gpio_bitmask, uint8 priority)
++{
++	/* only cores on SI_BUS share GPIO's and only applcation users need to
++	 * reserve/release GPIO
++	 */
++	if ((BUSTYPE(sih->bustype) != SI_BUS) || (!priority)) {
++		ASSERT((BUSTYPE(sih->bustype) == SI_BUS) && (priority));
++		return 0xffffffff;
++	}
++	/* make sure only one bit is set */
++	if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
++		ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
++		return 0xffffffff;
++	}
++
++	/* already reserved */
++	if (si_gpioreservation & gpio_bitmask)
++		return 0xffffffff;
++	/* set reservation */
++	si_gpioreservation |= gpio_bitmask;
++
++	return si_gpioreservation;
++}
++
++/**
++ * release one gpio.
++ *
++ * releasing the gpio doesn't change the current value on the GPIO last write value
++ * persists till someone overwrites it.
++ */
++uint32
++si_gpiorelease(si_t *sih, uint32 gpio_bitmask, uint8 priority)
++{
++	/* only cores on SI_BUS share GPIO's and only applcation users need to
++	 * reserve/release GPIO
++	 */
++	if ((BUSTYPE(sih->bustype) != SI_BUS) || (!priority)) {
++		ASSERT((BUSTYPE(sih->bustype) == SI_BUS) && (priority));
++		return 0xffffffff;
++	}
++	/* make sure only one bit is set */
++	if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
++		ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
++		return 0xffffffff;
++	}
++
++	/* already released */
++	if (!(si_gpioreservation & gpio_bitmask))
++		return 0xffffffff;
++
++	/* clear reservation */
++	si_gpioreservation &= ~gpio_bitmask;
++
++	return si_gpioreservation;
++}
++
++/* return the current gpioin register value */
++uint32
++si_gpioin(si_t *sih)
++{
++	uint regoff;
++
++	regoff = OFFSETOF(chipcregs_t, gpioin);
++	return (si_corereg(sih, SI_CC_IDX, regoff, 0, 0));
++}
++
++/* mask&set gpio interrupt polarity bits */
++uint32
++si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority)
++{
++	uint regoff;
++
++	/* gpios could be shared on router platforms */
++	if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
++		mask = priority ? (si_gpioreservation & mask) :
++			((si_gpioreservation | mask) & ~(si_gpioreservation));
++		val &= mask;
++	}
++
++	regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
++	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
++}
++
++/* mask&set gpio interrupt mask bits */
++uint32
++si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority)
++{
++	uint regoff;
++
++	/* gpios could be shared on router platforms */
++	if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
++		mask = priority ? (si_gpioreservation & mask) :
++			((si_gpioreservation | mask) & ~(si_gpioreservation));
++		val &= mask;
++	}
++
++	regoff = OFFSETOF(chipcregs_t, gpiointmask);
++	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
++}
++
++uint32
++si_gpioeventintmask(si_t *sih, uint32 mask, uint32 val, uint8 priority)
++{
++	uint regoff;
++	/* gpios could be shared on router platforms */
++	if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
++		mask = priority ? (si_gpioreservation & mask) :
++			((si_gpioreservation | mask) & ~(si_gpioreservation));
++		val &= mask;
++	}
++	regoff = OFFSETOF(chipcregs_t, gpioeventintmask);
++	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
++}
++
++/* assign the gpio to an led */
++uint32
++si_gpioled(si_t *sih, uint32 mask, uint32 val)
++{
++	if (CCREV(sih->ccrev) < 16)
++		return 0xffffffff;
++
++	/* gpio led powersave reg */
++	return (si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
++}
++
++/* mask&set gpio timer val */
++uint32
++si_gpiotimerval(si_t *sih, uint32 mask, uint32 gpiotimerval)
++{
++	if (CCREV(sih->ccrev) < 16)
++		return 0xffffffff;
++
++	return (si_corereg(sih, SI_CC_IDX,
++		OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
++}
++
++uint32
++si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val)
++{
++	uint offs;
++
++	if (CCREV(sih->ccrev) < 20)
++		return 0xffffffff;
++
++	offs = (updown ? OFFSETOF(chipcregs_t, gpiopulldown) : OFFSETOF(chipcregs_t, gpiopullup));
++	return (si_corereg(sih, SI_CC_IDX, offs, mask, val));
++}
++
++uint32
++si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val)
++{
++	uint offs;
++
++	if (CCREV(sih->ccrev) < 11)
++		return 0xffffffff;
++
++	if (regtype == GPIO_REGEVT)
++		offs = OFFSETOF(chipcregs_t, gpioevent);
++	else if (regtype == GPIO_REGEVT_INTMSK)
++		offs = OFFSETOF(chipcregs_t, gpioeventintmask);
++	else if (regtype == GPIO_REGEVT_INTPOL)
++		offs = OFFSETOF(chipcregs_t, gpioeventintpolarity);
++	else
++		return 0xffffffff;
++
++	return (si_corereg(sih, SI_CC_IDX, offs, mask, val));
++}
++
++uint32
++si_gpio_int_enable(si_t *sih, bool enable)
++{
++	uint offs;
++
++	if (CCREV(sih->ccrev) < 11)
++		return 0xffffffff;
++
++	offs = OFFSETOF(chipcregs_t, intmask);
++	return (si_corereg(sih, SI_CC_IDX, offs, CI_GPIO, (enable ? CI_GPIO : 0)));
++}
++
++/** Return the size of the specified SYSMEM bank */
++static uint
++sysmem_banksize(si_info_t *sii, sysmemregs_t *regs, uint8 idx)
++{
++	uint banksize, bankinfo;
++	uint bankidx = idx;
++
++	W_REG(sii->osh, &regs->bankidx, bankidx);
++	bankinfo = R_REG(sii->osh, &regs->bankinfo);
++	banksize = SYSMEM_BANKINFO_SZBASE * ((bankinfo & SYSMEM_BANKINFO_SZMASK) + 1);
++	return banksize;
++}
++
++/** Return the RAM size of the SYSMEM core */
++uint32
++si_sysmem_size(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint origidx;
++	uint intr_val = 0;
++
++	sysmemregs_t *regs;
++	bool wasup;
++	uint32 coreinfo;
++	uint memsize = 0;
++	uint8 i;
++	uint nb, nrb;
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	/* Switch to SYSMEM core */
++	if (!(regs = si_setcore(sih, SYSMEM_CORE_ID, 0)))
++		goto done;
++
++	/* Get info for determining size */
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, 0, 0);
++	coreinfo = R_REG(sii->osh, &regs->coreinfo);
++
++	/* Number of ROM banks, SW need to skip the ROM banks. */
++	nrb = (coreinfo & SYSMEM_SRCI_ROMNB_MASK) >> SYSMEM_SRCI_ROMNB_SHIFT;
++
++	nb = (coreinfo & SYSMEM_SRCI_SRNB_MASK) >> SYSMEM_SRCI_SRNB_SHIFT;
++	for (i = 0; i < nb; i++)
++		memsize += sysmem_banksize(sii, regs, i + nrb);
++
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++
++	return memsize;
++}
++
++/** Return the size of the specified SOCRAM bank */
++static uint
++socram_banksize(si_info_t *sii, sbsocramregs_t *regs, uint8 idx, uint8 mem_type)
++{
++	uint banksize, bankinfo;
++	uint bankidx = idx | (mem_type << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
++
++	ASSERT(mem_type <= SOCRAM_MEMTYPE_DEVRAM);
++
++	W_REG(sii->osh, &regs->bankidx, bankidx);
++	bankinfo = R_REG(sii->osh, &regs->bankinfo);
++	banksize = SOCRAM_BANKINFO_SZBASE * ((bankinfo & SOCRAM_BANKINFO_SZMASK) + 1);
++	return banksize;
++}
++
++void si_socram_set_bankpda(si_t *sih, uint32 bankidx, uint32 bankpda)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint origidx;
++	uint intr_val = 0;
++	sbsocramregs_t *regs;
++	bool wasup;
++	uint corerev;
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	/* Switch to SOCRAM core */
++	if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
++		goto done;
++
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, 0, 0);
++
++	corerev = si_corerev(sih);
++	if (corerev >= 16) {
++		W_REG(sii->osh, &regs->bankidx, bankidx);
++		W_REG(sii->osh, &regs->bankpda, bankpda);
++	}
++
++	/* Return to previous state and core */
++	if (!wasup)
++		si_core_disable(sih, 0);
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++}
++
++void
++si_socdevram(si_t *sih, bool set, uint8 *enable, uint8 *protect, uint8 *remap)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint origidx;
++	uint intr_val = 0;
++	sbsocramregs_t *regs;
++	bool wasup;
++	uint corerev;
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	if (!set)
++		*enable = *protect = *remap = 0;
++
++	/* Switch to SOCRAM core */
++	if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
++		goto done;
++
++	/* Get info for determining size */
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, 0, 0);
++
++	corerev = si_corerev(sih);
++	if (corerev >= 10) {
++		uint32 extcinfo;
++		uint8 nb;
++		uint8 i;
++		uint32 bankidx, bankinfo;
++
++		extcinfo = R_REG(sii->osh, &regs->extracoreinfo);
++		nb = ((extcinfo & SOCRAM_DEVRAMBANK_MASK) >> SOCRAM_DEVRAMBANK_SHIFT);
++		for (i = 0; i < nb; i++) {
++			bankidx = i | (SOCRAM_MEMTYPE_DEVRAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
++			W_REG(sii->osh, &regs->bankidx, bankidx);
++			bankinfo = R_REG(sii->osh, &regs->bankinfo);
++			if (set) {
++				bankinfo &= ~SOCRAM_BANKINFO_DEVRAMSEL_MASK;
++				bankinfo &= ~SOCRAM_BANKINFO_DEVRAMPRO_MASK;
++				bankinfo &= ~SOCRAM_BANKINFO_DEVRAMREMAP_MASK;
++				if (*enable) {
++					bankinfo |= (1 << SOCRAM_BANKINFO_DEVRAMSEL_SHIFT);
++					if (*protect)
++						bankinfo |= (1 << SOCRAM_BANKINFO_DEVRAMPRO_SHIFT);
++					if ((corerev >= 16) && *remap)
++						bankinfo |=
++							(1 << SOCRAM_BANKINFO_DEVRAMREMAP_SHIFT);
++				}
++				W_REG(sii->osh, &regs->bankinfo, bankinfo);
++			} else if (i == 0) {
++				if (bankinfo & SOCRAM_BANKINFO_DEVRAMSEL_MASK) {
++					*enable = 1;
++					if (bankinfo & SOCRAM_BANKINFO_DEVRAMPRO_MASK)
++						*protect = 1;
++					if (bankinfo & SOCRAM_BANKINFO_DEVRAMREMAP_MASK)
++						*remap = 1;
++				}
++			}
++		}
++	}
++
++	/* Return to previous state and core */
++	if (!wasup)
++		si_core_disable(sih, 0);
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++}
++
++bool
++si_socdevram_remap_isenb(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint origidx;
++	uint intr_val = 0;
++	sbsocramregs_t *regs;
++	bool wasup, remap = FALSE;
++	uint corerev;
++	uint32 extcinfo;
++	uint8 nb;
++	uint8 i;
++	uint32 bankidx, bankinfo;
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	/* Switch to SOCRAM core */
++	if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
++		goto done;
++
++	/* Get info for determining size */
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, 0, 0);
++
++	corerev = si_corerev(sih);
++	if (corerev >= 16) {
++		extcinfo = R_REG(sii->osh, &regs->extracoreinfo);
++		nb = ((extcinfo & SOCRAM_DEVRAMBANK_MASK) >> SOCRAM_DEVRAMBANK_SHIFT);
++		for (i = 0; i < nb; i++) {
++			bankidx = i | (SOCRAM_MEMTYPE_DEVRAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
++			W_REG(sii->osh, &regs->bankidx, bankidx);
++			bankinfo = R_REG(sii->osh, &regs->bankinfo);
++			if (bankinfo & SOCRAM_BANKINFO_DEVRAMREMAP_MASK) {
++				remap = TRUE;
++				break;
++			}
++		}
++	}
++
++	/* Return to previous state and core */
++	if (!wasup)
++		si_core_disable(sih, 0);
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++	return remap;
++}
++
++bool
++si_socdevram_pkg(si_t *sih)
++{
++	if (si_socdevram_size(sih) > 0)
++		return TRUE;
++	else
++		return FALSE;
++}
++
++uint32
++si_socdevram_size(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint origidx;
++	uint intr_val = 0;
++	uint32 memsize = 0;
++	sbsocramregs_t *regs;
++	bool wasup;
++	uint corerev;
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	/* Switch to SOCRAM core */
++	if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
++		goto done;
++
++	/* Get info for determining size */
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, 0, 0);
++
++	corerev = si_corerev(sih);
++	if (corerev >= 10) {
++		uint32 extcinfo;
++		uint8 nb;
++		uint8 i;
++
++		extcinfo = R_REG(sii->osh, &regs->extracoreinfo);
++		nb = (((extcinfo & SOCRAM_DEVRAMBANK_MASK) >> SOCRAM_DEVRAMBANK_SHIFT));
++		for (i = 0; i < nb; i++)
++			memsize += socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_DEVRAM);
++	}
++
++	/* Return to previous state and core */
++	if (!wasup)
++		si_core_disable(sih, 0);
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++
++	return memsize;
++}
++
++uint32
++si_socdevram_remap_size(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint origidx;
++	uint intr_val = 0;
++	uint32 memsize = 0, banksz;
++	sbsocramregs_t *regs;
++	bool wasup;
++	uint corerev;
++	uint32 extcinfo;
++	uint8 nb;
++	uint8 i;
++	uint32 bankidx, bankinfo;
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	/* Switch to SOCRAM core */
++	if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
++		goto done;
++
++	/* Get info for determining size */
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, 0, 0);
++
++	corerev = si_corerev(sih);
++	if (corerev >= 16) {
++		extcinfo = R_REG(sii->osh, &regs->extracoreinfo);
++		nb = (((extcinfo & SOCRAM_DEVRAMBANK_MASK) >> SOCRAM_DEVRAMBANK_SHIFT));
++
++		/*
++		 * FIX: A0 Issue: Max addressable is 512KB, instead 640KB
++		 * Only four banks are accessible to ARM
++		 */
++		if ((corerev == 16) && (nb == 5))
++			nb = 4;
++
++		for (i = 0; i < nb; i++) {
++			bankidx = i | (SOCRAM_MEMTYPE_DEVRAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
++			W_REG(sii->osh, &regs->bankidx, bankidx);
++			bankinfo = R_REG(sii->osh, &regs->bankinfo);
++			if (bankinfo & SOCRAM_BANKINFO_DEVRAMREMAP_MASK) {
++				banksz = socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_DEVRAM);
++				memsize += banksz;
++			} else {
++				/* Account only consecutive banks for now */
++				break;
++			}
++		}
++	}
++
++	/* Return to previous state and core */
++	if (!wasup)
++		si_core_disable(sih, 0);
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++
++	return memsize;
++}
++
++/** Return the RAM size of the SOCRAM core */
++uint32
++si_socram_size(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint origidx;
++	uint intr_val = 0;
++
++	sbsocramregs_t *regs;
++	bool wasup;
++	uint corerev;
++	uint32 coreinfo;
++	uint memsize = 0;
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	/* Switch to SOCRAM core */
++	if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
++		goto done;
++
++	/* Get info for determining size */
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, 0, 0);
++	corerev = si_corerev(sih);
++	coreinfo = R_REG(sii->osh, &regs->coreinfo);
++
++	/* Calculate size from coreinfo based on rev */
++	if (corerev == 0)
++		memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK));
++	else if (corerev < 3) {
++		memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK));
++		memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
++	} else if ((corerev <= 7) || (corerev == 12)) {
++		uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
++		uint bsz = (coreinfo & SRCI_SRBSZ_MASK);
++		uint lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT;
++		if (lss != 0)
++			nb --;
++		memsize = nb * (1 << (bsz + SR_BSZ_BASE));
++		if (lss != 0)
++			memsize += (1 << ((lss - 1) + SR_BSZ_BASE));
++	} else {
++		uint8 i;
++		uint nb;
++		/* length of SRAM Banks increased for corerev greater than 23 */
++		if (corerev >= 23) {
++			nb = (coreinfo & (SRCI_SRNB_MASK | SRCI_SRNB_MASK_EXT)) >> SRCI_SRNB_SHIFT;
++		} else {
++			nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
++		}
++		for (i = 0; i < nb; i++)
++			memsize += socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM);
++	}
++
++	/* Return to previous state and core */
++	if (!wasup)
++		si_core_disable(sih, 0);
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++
++	return memsize;
++}
++
++
++/** Return the TCM-RAM size of the ARMCR4 core. */
++uint32
++si_tcm_size(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint origidx;
++	uint intr_val = 0;
++	volatile uint8 *regs;
++	bool wasup;
++	uint32 corecap;
++	uint memsize = 0;
++	uint32 nab = 0;
++	uint32 nbb = 0;
++	uint32 totb = 0;
++	uint32 bxinfo = 0;
++	uint32 idx = 0;
++	volatile uint32 *arm_cap_reg;
++	volatile uint32 *arm_bidx;
++	volatile uint32 *arm_binfo;
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	/* Switch to CR4 core */
++	if (!(regs = si_setcore(sih, ARMCR4_CORE_ID, 0)))
++		goto done;
++
++	/* Get info for determining size. If in reset, come out of reset,
++	 * but remain in halt
++	 */
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, SICF_CPUHALT, SICF_CPUHALT);
++
++	arm_cap_reg = (volatile uint32 *)(regs + SI_CR4_CAP);
++	corecap = R_REG(sii->osh, arm_cap_reg);
++
++	nab = (corecap & ARMCR4_TCBANB_MASK) >> ARMCR4_TCBANB_SHIFT;
++	nbb = (corecap & ARMCR4_TCBBNB_MASK) >> ARMCR4_TCBBNB_SHIFT;
++	totb = nab + nbb;
++
++	arm_bidx = (volatile uint32 *)(regs + SI_CR4_BANKIDX);
++	arm_binfo = (volatile uint32 *)(regs + SI_CR4_BANKINFO);
++	for (idx = 0; idx < totb; idx++) {
++		W_REG(sii->osh, arm_bidx, idx);
++
++		bxinfo = R_REG(sii->osh, arm_binfo);
++		memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * ARMCR4_BSZ_MULT;
++	}
++
++	/* Return to previous state and core */
++	if (!wasup)
++		si_core_disable(sih, 0);
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++
++	return memsize;
++}
++
++bool
++si_has_flops(si_t *sih)
++{
++	uint origidx, cr4_rev;
++
++	/* Find out CR4 core revision */
++	origidx = si_coreidx(sih);
++	if (si_setcore(sih, ARMCR4_CORE_ID, 0)) {
++		cr4_rev = si_corerev(sih);
++		si_setcoreidx(sih, origidx);
++
++		if (cr4_rev == 1 || cr4_rev >= 3)
++			return TRUE;
++	}
++	return FALSE;
++}
++
++uint32
++si_socram_srmem_size(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint origidx;
++	uint intr_val = 0;
++
++	sbsocramregs_t *regs;
++	bool wasup;
++	uint corerev;
++	uint32 coreinfo;
++	uint memsize = 0;
++
++	if ((CHIPID(sih->chip) == BCM4334_CHIP_ID) && (CHIPREV(sih->chiprev) < 2)) {
++		return (32 * 1024);
++	}
++
++	if (CHIPID(sih->chip) == BCM43430_CHIP_ID ||
++		CHIPID(sih->chip) == BCM43018_CHIP_ID) {
++		return (64 * 1024);
++	}
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	/* Switch to SOCRAM core */
++	if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
++		goto done;
++
++	/* Get info for determining size */
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, 0, 0);
++	corerev = si_corerev(sih);
++	coreinfo = R_REG(sii->osh, &regs->coreinfo);
++
++	/* Calculate size from coreinfo based on rev */
++	if (corerev >= 16) {
++		uint8 i;
++		uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
++		for (i = 0; i < nb; i++) {
++			W_REG(sii->osh, &regs->bankidx, i);
++			if (R_REG(sii->osh, &regs->bankinfo) & SOCRAM_BANKINFO_RETNTRAM_MASK)
++				memsize += socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM);
++		}
++	}
++
++	/* Return to previous state and core */
++	if (!wasup)
++		si_core_disable(sih, 0);
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++
++	return memsize;
++}
++
++
++#if !defined(_CFEZ_) || defined(CFG_WL)
++void
++si_btcgpiowar(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint origidx;
++	uint intr_val = 0;
++	chipcregs_t *cc;
++
++	/* Make sure that there is ChipCommon core present &&
++	 * UART_TX is strapped to 1
++	 */
++	if (!(sih->cccaps & CC_CAP_UARTGPIO))
++		return;
++
++	/* si_corereg cannot be used as we have to guarantee 8-bit read/writes */
++	INTR_OFF(sii, intr_val);
++
++	origidx = si_coreidx(sih);
++
++	cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
++	ASSERT(cc != NULL);
++
++	W_REG(sii->osh, &cc->uart0mcr, R_REG(sii->osh, &cc->uart0mcr) | 0x04);
++
++	/* restore the original index */
++	si_setcoreidx(sih, origidx);
++
++	INTR_RESTORE(sii, intr_val);
++}
++
++void
++si_chipcontrl_btshd0_4331(si_t *sih, bool on)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx;
++	uint32 val;
++	uint intr_val = 0;
++
++	INTR_OFF(sii, intr_val);
++
++	origidx = si_coreidx(sih);
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++
++	val = R_REG(sii->osh, &cc->chipcontrol);
++
++	/* bt_shd0 controls are same for 4331 chiprevs 0 and 1, packages 12x9 and 12x12 */
++	if (on) {
++		/* Enable bt_shd0 on gpio4: */
++		val |= (CCTRL4331_BT_SHD0_ON_GPIO4);
++		W_REG(sii->osh, &cc->chipcontrol, val);
++	} else {
++		val &= ~(CCTRL4331_BT_SHD0_ON_GPIO4);
++		W_REG(sii->osh, &cc->chipcontrol, val);
++	}
++
++	/* restore the original index */
++	si_setcoreidx(sih, origidx);
++
++	INTR_RESTORE(sii, intr_val);
++}
++
++void
++si_chipcontrl_restore(si_t *sih, uint32 val)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++	W_REG(sii->osh, &cc->chipcontrol, val);
++	si_setcoreidx(sih, origidx);
++}
++
++uint32
++si_chipcontrl_read(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++	uint32 val;
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return -1;
++	}
++	val = R_REG(sii->osh, &cc->chipcontrol);
++	si_setcoreidx(sih, origidx);
++	return val;
++}
++
++void
++si_chipcontrl_epa4331(si_t *sih, bool on)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++	uint32 val;
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++	val = R_REG(sii->osh, &cc->chipcontrol);
++
++	if (on) {
++		if (sih->chippkg == 9 || sih->chippkg == 0xb) {
++			val |= (CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
++			/* Ext PA Controls for 4331 12x9 Package */
++			W_REG(sii->osh, &cc->chipcontrol, val);
++		} else {
++			/* Ext PA Controls for 4331 12x12 Package */
++			if (CHIPREV(sih->chiprev) > 0) {
++				W_REG(sii->osh, &cc->chipcontrol, val |
++				      (CCTRL4331_EXTPA_EN) | (CCTRL4331_EXTPA_EN2));
++			} else {
++				W_REG(sii->osh, &cc->chipcontrol, val | (CCTRL4331_EXTPA_EN));
++			}
++		}
++	} else {
++		val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_EN2 | CCTRL4331_EXTPA_ON_GPIO2_5);
++		W_REG(sii->osh, &cc->chipcontrol, val);
++	}
++
++	si_setcoreidx(sih, origidx);
++}
++
++/** switch muxed pins, on: SROM, off: FEMCTRL. Called for a family of ac chips, not just 4360. */
++void
++si_chipcontrl_srom4360(si_t *sih, bool on)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++	uint32 val;
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++	val = R_REG(sii->osh, &cc->chipcontrol);
++
++	if (on) {
++		val &= ~(CCTRL4360_SECI_MODE |
++			CCTRL4360_BTSWCTRL_MODE |
++			CCTRL4360_EXTRA_FEMCTRL_MODE |
++			CCTRL4360_BT_LGCY_MODE |
++			CCTRL4360_CORE2FEMCTRL4_ON);
++
++		W_REG(sii->osh, &cc->chipcontrol, val);
++	} else {
++	}
++
++	si_setcoreidx(sih, origidx);
++}
++
++void
++si_clk_srom4365(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++	uint32 val;
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++	val = R_REG(sii->osh, &cc->clkdiv2);
++	W_REG(sii->osh, &cc->clkdiv2, ((val&~0xf) | 0x4));
++
++	si_setcoreidx(sih, origidx);
++}
++
++void
++si_chipcontrl_epa4331_wowl(si_t *sih, bool enter_wowl)
++{
++	si_info_t *sii;
++	chipcregs_t *cc;
++	uint origidx;
++	uint32 val;
++	bool sel_chip;
++
++	sel_chip = (CHIPID(sih->chip) == BCM4331_CHIP_ID) ||
++		(CHIPID(sih->chip) == BCM43431_CHIP_ID);
++	sel_chip &= ((sih->chippkg == 9 || sih->chippkg == 0xb));
++
++	if (!sel_chip)
++		return;
++
++	sii = SI_INFO(sih);
++	origidx = si_coreidx(sih);
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++
++	val = R_REG(sii->osh, &cc->chipcontrol);
++
++	if (enter_wowl) {
++		val |= CCTRL4331_EXTPA_EN;
++		W_REG(sii->osh, &cc->chipcontrol, val);
++	} else {
++		val |= (CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
++		W_REG(sii->osh, &cc->chipcontrol, val);
++	}
++	si_setcoreidx(sih, origidx);
++}
++#endif 
++
++uint
++si_pll_reset(si_t *sih)
++{
++	uint err = 0;
++
++	return (err);
++}
++
++/** Enable BT-COEX & Ex-PA for 4313 */
++void
++si_epa_4313war(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++
++	/* EPA Fix */
++	W_REG(sii->osh, &cc->gpiocontrol,
++	R_REG(sii->osh, &cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK);
++
++	si_setcoreidx(sih, origidx);
++}
++
++void
++si_clk_pmu_htavail_set(si_t *sih, bool set_clear)
++{
++}
++
++void
++si_pmu_avb_clk_set(si_t *sih, osl_t *osh, bool set_flag)
++{
++}
++
++/** Re-enable synth_pwrsw resource in min_res_mask for 4313 */
++void
++si_pmu_synth_pwrsw_4313_war(si_t *sih)
++{
++}
++
++/** WL/BT control for 4313 btcombo boards >= P250 */
++void
++si_btcombo_p250_4313_war(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++	W_REG(sii->osh, &cc->gpiocontrol,
++		R_REG(sii->osh, &cc->gpiocontrol) | GPIO_CTRL_5_6_EN_MASK);
++
++	W_REG(sii->osh, &cc->gpioouten,
++		R_REG(sii->osh, &cc->gpioouten) | GPIO_CTRL_5_6_EN_MASK);
++
++	si_setcoreidx(sih, origidx);
++}
++void
++si_btc_enable_chipcontrol(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++
++	/* BT fix */
++	W_REG(sii->osh, &cc->chipcontrol,
++		R_REG(sii->osh, &cc->chipcontrol) | CC_BTCOEX_EN_MASK);
++
++	si_setcoreidx(sih, origidx);
++}
++void
++si_btcombo_43228_war(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++
++	W_REG(sii->osh, &cc->gpioouten, GPIO_CTRL_7_6_EN_MASK);
++	W_REG(sii->osh, &cc->gpioout, GPIO_OUT_7_EN_MASK);
++
++	si_setcoreidx(sih, origidx);
++}
++
++/** cache device removed state */
++void si_set_device_removed(si_t *sih, bool status)
++{
++	si_info_t *sii = SI_INFO(sih);
++
++	sii->device_removed = status;
++}
++
++/** check if the device is removed */
++bool
++si_deviceremoved(si_t *sih)
++{
++	uint32 w;
++	si_info_t *sii = SI_INFO(sih);
++
++	if (sii->device_removed) {
++		return TRUE;
++	}
++
++	switch (BUSTYPE(sih->bustype)) {
++	case PCI_BUS:
++		ASSERT(SI_INFO(sih)->osh != NULL);
++		w = OSL_PCI_READ_CONFIG(SI_INFO(sih)->osh, PCI_CFG_VID, sizeof(uint32));
++		if ((w & 0xFFFF) != VENDOR_BROADCOM)
++			return TRUE;
++		break;
++	}
++	return FALSE;
++}
++
++bool
++si_is_warmboot(void)
++{
++
++#ifdef BCMULP
++	return (boot_type == WARM_BOOT);
++#else
++	return FALSE;
++#endif
++}
++
++bool
++si_is_sprom_available(si_t *sih)
++{
++	if (CCREV(sih->ccrev) >= 31) {
++		si_info_t *sii;
++		uint origidx;
++		chipcregs_t *cc;
++		uint32 sromctrl;
++
++		if ((sih->cccaps & CC_CAP_SROM) == 0)
++			return FALSE;
++
++		sii = SI_INFO(sih);
++		origidx = sii->curidx;
++		cc = si_setcoreidx(sih, SI_CC_IDX);
++		ASSERT(cc);
++		sromctrl = R_REG(sii->osh, &cc->sromcontrol);
++		si_setcoreidx(sih, origidx);
++		return (sromctrl & SRC_PRESENT);
++	}
++
++	switch (CHIPID(sih->chip)) {
++	case BCM43018_CHIP_ID:
++	case BCM43430_CHIP_ID:
++		return FALSE;
++	case BCM4336_CHIP_ID:
++	case BCM43362_CHIP_ID:
++		return (sih->chipst & CST4336_SPROM_PRESENT) != 0;
++	case BCM4330_CHIP_ID:
++		return (sih->chipst & CST4330_SPROM_PRESENT) != 0;
++	case BCM4313_CHIP_ID:
++		return (sih->chipst & CST4313_SPROM_PRESENT) != 0;
++	case BCM4331_CHIP_ID:
++	case BCM43431_CHIP_ID:
++		return (sih->chipst & CST4331_SPROM_PRESENT) != 0;
++	case BCM43239_CHIP_ID:
++		return ((sih->chipst & CST43239_SPROM_MASK) &&
++			!(sih->chipst & CST43239_SFLASH_MASK));
++	case BCM4324_CHIP_ID:
++	case BCM43242_CHIP_ID:
++		return ((sih->chipst & CST4324_SPROM_MASK) &&
++			!(sih->chipst & CST4324_SFLASH_MASK));
++	case BCM4335_CHIP_ID:
++	CASE_BCM4345_CHIP:
++		return ((sih->chipst & CST4335_SPROM_MASK) &&
++			!(sih->chipst & CST4335_SFLASH_MASK));
++	case BCM4349_CHIP_GRPID:
++		return (sih->chipst & CST4349_SPROM_PRESENT) != 0;
++	case BCM53573_CHIP_GRPID:
++		return FALSE; /* SPROM PRESENT is not defined for 53573 as of now */
++	case BCM4347_CHIP_ID:
++		return (sih->chipst & CST4347_SPROM_PRESENT) != 0;
++		break;
++	case BCM4350_CHIP_ID:
++	case BCM4354_CHIP_ID:
++	case BCM43556_CHIP_ID:
++	case BCM43558_CHIP_ID:
++	case BCM43566_CHIP_ID:
++	case BCM43568_CHIP_ID:
++	case BCM43569_CHIP_ID:
++	case BCM43570_CHIP_ID:
++	case BCM4358_CHIP_ID:
++		return (sih->chipst & CST4350_SPROM_PRESENT) != 0;
++	CASE_BCM43602_CHIP:
++		return (sih->chipst & CST43602_SPROM_PRESENT) != 0;
++	case BCM43131_CHIP_ID:
++	case BCM43217_CHIP_ID:
++	case BCM43227_CHIP_ID:
++	case BCM43228_CHIP_ID:
++	case BCM43428_CHIP_ID:
++		return (sih->chipst & CST43228_OTP_PRESENT) != CST43228_OTP_PRESENT;
++	case BCM43012_CHIP_ID:
++		return FALSE;
++	default:
++		return TRUE;
++	}
++}
++
++
++uint32 si_get_sromctl(si_t *sih)
++{
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++	uint32 sromctl;
++	osl_t *osh = si_osh(sih);
++
++	cc = si_setcoreidx(sih, SI_CC_IDX);
++	ASSERT((uintptr)cc);
++
++	sromctl = R_REG(osh, &cc->sromcontrol);
++
++	/* return to the original core */
++	si_setcoreidx(sih, origidx);
++	return sromctl;
++}
++
++int si_set_sromctl(si_t *sih, uint32 value)
++{
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++	osl_t *osh = si_osh(sih);
++	int ret = BCME_OK;
++
++	cc = si_setcoreidx(sih, SI_CC_IDX);
++	ASSERT((uintptr)cc);
++
++	/* get chipcommon rev */
++	if (si_corerev(sih) >= 32) {
++		/* SpromCtrl is only accessible if CoreCapabilities.SpromSupported and
++		 * SpromPresent is 1.
++		 */
++		if ((R_REG(osh, &cc->capabilities) & CC_CAP_SROM) != 0 &&
++		     (R_REG(osh, &cc->sromcontrol) & SRC_PRESENT)) {
++			W_REG(osh, &cc->sromcontrol, value);
++		} else {
++			ret = BCME_NODEVICE;
++		}
++	} else {
++		ret = BCME_UNSUPPORTED;
++	}
++
++	/* return to the original core */
++	si_setcoreidx(sih, origidx);
++
++	return ret;
++}
++
++uint
++si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val)
++{
++	uint origidx, intr_val = 0;
++	uint ret_val;
++	si_info_t *sii = SI_INFO(sih);
++
++	origidx = si_coreidx(sih);
++
++	INTR_OFF(sii, intr_val);
++	si_setcoreidx(sih, coreidx);
++
++	ret_val = si_wrapperreg(sih, offset, mask, val);
++
++	/* return to the original core */
++	si_setcoreidx(sih, origidx);
++	INTR_RESTORE(sii, intr_val);
++	return ret_val;
++}
++
++
++/* cleanup the timer from the host when ARM is been halted
++ * without a chance for ARM cleanup its resources
++ * If left not cleanup, Intr from a software timer can still
++ * request HT clk when ARM is halted.
++ */
++uint32
++si_pmu_res_req_timer_clr(si_t *sih)
++{
++	uint32 mask;
++
++	mask = PRRT_REQ_ACTIVE | PRRT_INTEN | PRRT_HT_REQ;
++	mask <<= 14;
++	/* clear mask bits */
++	pmu_corereg(sih, SI_CC_IDX, res_req_timer, mask, 0);
++	/* readback to ensure write completes */
++	return pmu_corereg(sih, SI_CC_IDX, res_req_timer, 0, 0);
++}
++
++/** turn on/off rfldo */
++void
++si_pmu_rfldo(si_t *sih, bool on)
++{
++}
++
++
++#ifdef SURVIVE_PERST_ENAB
++static uint32
++si_pcie_survive_perst(si_t *sih, uint32 mask, uint32 val)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++
++	if (!PCIE(sii))
++		return (0);
++
++	return pcie_survive_perst(sii->pch, mask, val);
++}
++
++static void
++si_watchdog_reset(si_t *sih)
++{
++	uint32 i;
++
++	/* issue a watchdog reset */
++	pmu_corereg(sih, SI_CC_IDX, pmuwatchdog, 2, 2);
++	/* do busy wait for 20ms */
++	for (i = 0; i < 2000; i++) {
++		OSL_DELAY(10);
++	}
++}
++#endif /* SURVIVE_PERST_ENAB */
++
++void
++si_survive_perst_war(si_t *sih, bool reset, uint32 sperst_mask, uint32 sperst_val)
++{
++#ifdef SURVIVE_PERST_ENAB
++	if (BUSTYPE(sih->bustype) != PCI_BUS)
++		  return;
++
++	if ((CHIPID(sih->chip) != BCM4360_CHIP_ID && CHIPID(sih->chip) != BCM4352_CHIP_ID) ||
++	    (CHIPREV(sih->chiprev) >= 4))
++		return;
++
++	if (reset) {
++		si_info_t *sii = SI_INFO(sih);
++		uint32 bar0win, bar0win_after;
++
++		/* save the bar0win */
++		bar0win = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
++
++		si_watchdog_reset(sih);
++
++		bar0win_after = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
++		if (bar0win_after != bar0win) {
++			SI_ERROR(("%s: bar0win before %08x, bar0win after %08x\n",
++				__FUNCTION__, bar0win, bar0win_after));
++			OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32), bar0win);
++		}
++	}
++	if (sperst_mask) {
++		/* enable survive perst */
++		si_pcie_survive_perst(sih, sperst_mask, sperst_val);
++	}
++#endif /* SURVIVE_PERST_ENAB */
++}
++
++/* Caller of this function should make sure is on PCIE core
++ * Used in pciedev.c.
++ */
++void
++si_pcie_disable_oobselltr(si_t *sih)
++{
++	ASSERT(si_coreid(sih) == PCIE2_CORE_ID);
++	si_wrapperreg(sih, AI_OOBSELIND30, ~0, 0);
++}
++
++void
++si_pcie_ltr_war(si_t *sih)
++{
++}
++
++void
++si_pcie_hw_LTR_war(si_t *sih)
++{
++}
++
++void
++si_pciedev_reg_pm_clk_period(si_t *sih)
++{
++}
++
++void
++si_pciedev_crwlpciegen2(si_t *sih)
++{
++}
++
++void
++si_pcie_prep_D3(si_t *sih, bool enter_D3)
++{
++}
++
++
++#ifdef BCM_BACKPLANE_TIMEOUT
++uint32
++si_clear_backplane_to_fast(si_t *sih, void * addr)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_AI) {
++		return ai_clear_backplane_to_fast(sih, addr);
++	}
++
++	return 0;
++}
++
++const si_axi_error_info_t * si_get_axi_errlog_info(si_t * sih)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_AI) {
++		return (const si_axi_error_info_t *)sih->err_info;
++	}
++
++	return NULL;
++}
++
++void si_reset_axi_errlog_info(si_t * sih)
++{
++	sih->err_info->count = 0;
++}
++#endif /* BCM_BACKPLANE_TIMEOUT */
++
++#if defined(AXI_TIMEOUTS) || defined(BCM_BACKPLANE_TIMEOUT)
++uint32
++si_clear_backplane_to_per_core(si_t *sih, uint coreid, uint coreunit, void * wrap)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_AI) {
++		return ai_clear_backplane_to_per_core(sih, coreid, coreunit, wrap);
++	}
++
++	return AXI_WRAP_STS_NONE;
++}
++#endif /* AXI_TIMEOUTS || BCM_BACKPLANE_TIMEOUT */
++
++uint32
++si_clear_backplane_to(si_t *sih)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_AI) {
++		return ai_clear_backplane_to(sih);
++	}
++
++	return 0;
++}
++
++/*
++ * This routine adds the AXI timeouts for
++ * chipcommon, pcie and ARM slave wrappers
++ */
++void
++si_slave_wrapper_add(si_t *sih)
++{
++#if defined(AXI_TIMEOUTS) || defined(BCM_BACKPLANE_TIMEOUT)
++	/* Enable only for AXI */
++	if (CHIPTYPE(sih->socitype) != SOCI_AI) {
++		return;
++	}
++
++	if (CHIPID(sih->chip) == BCM4345_CHIP_ID && CHIPREV(sih->chiprev) >= 6) {
++		si_info_t *sii = SI_INFO(sih);
++
++		int wrapper_idx = (int)sii->axi_num_wrappers - 1;
++
++		ASSERT(wrapper_idx >= 0);		/* axi_wrapper[] not initialised */
++		do {
++			if (sii->axi_wrapper[wrapper_idx].wrapper_type == AI_SLAVE_WRAPPER &&
++				sii->axi_wrapper[wrapper_idx].cid == 0xfff) {
++				sii->axi_wrapper[wrapper_idx].wrapper_addr = 0x1810b000;
++				break;
++			}
++		} while (wrapper_idx-- > 0);
++		ASSERT(wrapper_idx >= 0);	/* all addresses valid for the chiprev under test */
++	}
++
++	/* All required slave wrappers are added in ai_scan */
++	ai_enable_backplane_timeouts(sih);
++#endif /* AXI_TIMEOUTS  || BCM_BACKPLANE_TIMEOUT */
++}
++
++
++void
++si_pll_sr_reinit(si_t *sih)
++{
++}
++
++
++/* Programming d11 core oob  settings for 4364
++ * WARs for HW4364-237 and HW4364-166
++*/
++void
++si_config_4364_d11_oob(si_t *sih, uint coreid)
++{
++	uint save_idx;
++
++	save_idx = si_coreidx(sih);
++	si_setcore(sih, coreid, 0);
++	si_wrapperreg(sih, AI_OOBSELINC30, ~0, 0x81828180);
++	si_wrapperreg(sih, AI_OOBSELINC74, ~0, 0x87868183);
++	si_wrapperreg(sih, AI_OOBSELOUTB74, ~0, 0x84858484);
++	si_setcore(sih, coreid, 1);
++	si_wrapperreg(sih, AI_OOBSELINC30, ~0, 0x81828180);
++	si_wrapperreg(sih, AI_OOBSELINC74, ~0, 0x87868184);
++	si_wrapperreg(sih, AI_OOBSELOUTB74, ~0, 0x84868484);
++	si_setcoreidx(sih, save_idx);
++}
++
++void
++si_pll_closeloop(si_t *sih)
++{
++#if defined(SAVERESTORE)
++	uint32 data;
++
++	/* disable PLL open loop operation */
++	switch (CHIPID(sih->chip)) {
++#ifdef SAVERESTORE
++		case BCM43018_CHIP_ID:
++		case BCM43430_CHIP_ID:
++			if (SR_ENAB() && sr_isenab(sih)) {
++				/* read back the pll openloop state */
++				data = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL8, 0, 0);
++				/* current mode is openloop (possible POR) */
++				if ((data & PMU1_PLLCTL8_OPENLOOP_MASK) != 0) {
++					si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL8,
++						PMU1_PLLCTL8_OPENLOOP_MASK, 0);
++					si_pmu_pllupd(sih);
++				}
++			}
++			break;
++#endif /* SAVERESTORE */
++		default:
++			/* any unsupported chip bail */
++			return;
++	}
++#endif 
++}
++
++void
++si_update_macclk_mul_fact(si_t *sih, uint32 mul_fact)
++{
++	si_info_t *sii = SI_INFO(sih);
++	sii->macclk_mul_fact = mul_fact;
++}
++
++uint32
++si_get_macclk_mul_fact(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	return sii->macclk_mul_fact;
++}
++
++
++#if defined(BCMSRPWR) && !defined(BCMSRPWR_DISABLED)
++bool _bcmsrpwr = TRUE;
++#else
++bool _bcmsrpwr = FALSE;
++#endif
++
++uint32
++si_srpwr_request(si_t *sih, uint32 mask, uint32 val)
++{
++	uint32 r, offset = OFFSETOF(chipcregs_t, powerctl); /* Same 0x1e8 per core */
++	uint cidx = (BUSTYPE(sih->bustype) == SI_BUS) ? SI_CC_IDX : sih->buscoreidx;
++
++	if (mask || val) {
++		mask <<= SRPWR_REQON_SHIFT;
++		val  <<= SRPWR_REQON_SHIFT;
++
++		r = ((si_corereg(sih, cidx, offset, 0, 0) & ~mask) | val);
++		r = si_corereg(sih, cidx, offset, ~0, r);
++	} else {
++		r = si_corereg(sih, cidx, offset, 0, 0);
++	}
++
++	return r;
++}
++
++uint32
++si_srpwr_stat_spinwait(si_t *sih, uint32 mask, uint32 val)
++{
++	uint32 r, offset = OFFSETOF(chipcregs_t, powerctl); /* Same 0x1e8 per core */
++	uint cidx = (BUSTYPE(sih->bustype) == SI_BUS) ? SI_CC_IDX : sih->buscoreidx;
++
++	ASSERT(mask);
++	ASSERT(val);
++
++	/* spinwait on pwrstatus */
++	mask <<= SRPWR_STATUS_SHIFT;
++	val <<= SRPWR_STATUS_SHIFT;
++
++	SPINWAIT(((si_corereg(sih, cidx, offset, 0, 0) & mask) != val),
++		PMU_MAX_TRANSITION_DLY);
++	ASSERT((si_corereg(sih, cidx, offset, 0, 0) & mask) == val);
++
++	r = si_corereg(sih, cidx, offset, 0, 0) & mask;
++	r = (r >> SRPWR_STATUS_SHIFT) & SRPWR_DMN_ALL_MASK;
++
++	return r;
++}
++
++uint32
++si_srpwr_stat(si_t *sih)
++{
++	uint32 r, offset = OFFSETOF(chipcregs_t, powerctl); /* Same 0x1e8 per core */
++	uint cidx = (BUSTYPE(sih->bustype) == SI_BUS) ? SI_CC_IDX : sih->buscoreidx;
++
++	r = si_corereg(sih, cidx, offset, 0, 0);
++	r = (r >> SRPWR_STATUS_SHIFT) & SRPWR_DMN_ALL_MASK;
++
++	return r;
++}
++
++uint32
++si_srpwr_domain(si_t *sih)
++{
++	uint32 r, offset = OFFSETOF(chipcregs_t, powerctl); /* Same 0x1e8 per core */
++	uint cidx = (BUSTYPE(sih->bustype) == SI_BUS) ? SI_CC_IDX : sih->buscoreidx;
++
++	r = si_corereg(sih, cidx, offset, 0, 0);
++	r = (r >> SRPWR_DMN_SHIFT) & SRPWR_DMN_ALL_MASK;
++
++	return r;
++}
++
++/* Utility API to read/write the raw registers with absolute address.
++ * This function can be invoked from either FW or host driver.
++ */
++uint32
++si_raw_reg(si_t *sih, uint32 reg, uint32 val, uint32 wrire_req)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint32 address_space = reg & ~0xFFF;
++	volatile uint32 * addr = (void*)(uintptr)(reg);
++	uint32 prev_value = 0;
++	uint32 cfg_reg = 0;
++
++	if (sii == NULL) {
++		return 0;
++	}
++
++	/* No need to translate the absolute address on SI bus */
++	if (BUSTYPE(sih->bustype) == SI_BUS) {
++		goto skip_cfg;
++	}
++
++	/* This API supports only the PCI host interface */
++	if (BUSTYPE(sih->bustype) != PCI_BUS) {
++		return ID32_INVALID;
++	}
++
++	if (PCIE_GEN2(sii)) {
++		/* Use BAR0 Secondary window is PCIe Gen2.
++		 * Set the secondary BAR0 Window to current register of interest
++		 */
++		addr = (volatile uint32*)(((volatile uint8*)sii->curmap) +
++			PCI_SEC_BAR0_WIN_OFFSET + (reg & 0xfff));
++		cfg_reg = PCIE2_BAR0_CORE2_WIN;
++
++	} else {
++		/* PCIe Gen1 do not have secondary BAR0 window.
++		 * reuse the BAR0 WIN2
++		 */
++		addr = (volatile uint32*)(((volatile uint8*)sii->curmap) +
++			PCI_BAR0_WIN2_OFFSET + (reg & 0xfff));
++		cfg_reg = PCI_BAR0_WIN2;
++	}
++
++	prev_value = OSL_PCI_READ_CONFIG(sii->osh, cfg_reg, 4);
++
++	if (prev_value != address_space) {
++		OSL_PCI_WRITE_CONFIG(sii->osh, cfg_reg,
++			sizeof(uint32), address_space);
++	} else {
++		prev_value = 0;
++	}
++
++skip_cfg:
++	if (wrire_req) {
++		W_REG(sii->osh, addr, val);
++	} else {
++		val = R_REG(sii->osh, addr);
++	}
++
++	if (prev_value) {
++		/* Restore BAR0 WIN2 for PCIE GEN1 devices */
++		OSL_PCI_WRITE_CONFIG(sii->osh,
++			cfg_reg, sizeof(uint32), prev_value);
++	}
++
++	return val;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/siutils_priv.h b/module_drivers/drivers/net/wireless/bcmdhd/siutils_priv.h
+new file mode 100644
+index 000000000..4b887df6a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/siutils_priv.h
+@@ -0,0 +1,333 @@
++/*
++ * Include file private to the SOC Interconnect support files.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: siutils_priv.h 625739 2016-03-17 12:28:03Z $
++ */
++
++#ifndef	_siutils_priv_h_
++#define	_siutils_priv_h_
++
++#if defined(SI_ERROR_ENFORCE)
++#define	SI_ERROR(args)	printf args
++#else
++#define	SI_ERROR(args) printf args
++#endif	
++
++#if defined(ENABLE_CORECAPTURE)
++
++#define	SI_PRINT(args)	osl_wificc_logDebug args
++
++#else
++
++#define	SI_PRINT(args)	printf args
++
++#endif /* ENABLE_CORECAPTURE */
++
++
++#define	SI_MSG(args)
++
++#ifdef BCMDBG_SI
++#define	SI_VMSG(args)	printf args
++#else
++#define	SI_VMSG(args)
++#endif
++
++#define	IS_SIM(chippkg)	((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
++
++typedef uint32 (*si_intrsoff_t)(void *intr_arg);
++typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg);
++typedef bool (*si_intrsenabled_t)(void *intr_arg);
++
++
++#define SI_GPIO_MAX		16
++
++typedef struct gci_gpio_item {
++	void			*arg;
++	uint8			gci_gpio;
++	uint8			status;
++	gci_gpio_handler_t	handler;
++	struct gci_gpio_item	*next;
++} gci_gpio_item_t;
++
++#define AI_SLAVE_WRAPPER        0
++#define AI_MASTER_WRAPPER       1
++
++typedef struct axi_wrapper {
++	uint32  mfg;
++	uint32  cid;
++	uint32  rev;
++	uint32  wrapper_type;
++	uint32  wrapper_addr;
++	uint32  wrapper_size;
++} axi_wrapper_t;
++
++#define SI_MAX_AXI_WRAPPERS		32
++#define AI_REG_READ_TIMEOUT		300 /* in msec */
++
++/* for some combo chips, BT side accesses chipcommon->0x190, as a 16 byte addr */
++/* register at 0x19C doesn't exist, so error is logged at the slave wrapper */
++#define BT_CC_SPROM_BADREG_LO   0x18000190
++#define BT_CC_SPROM_BADREG_HI   0
++#define BCM4350_BT_AXI_ID       6
++#define BCM4345_BT_AXI_ID       6
++
++typedef struct si_cores_info {
++	volatile void	*regs[SI_MAXCORES];	/* other regs va */
++
++	uint	coreid[SI_MAXCORES];	/**< id of each core */
++	uint32	coresba[SI_MAXCORES];	/**< backplane address of each core */
++	void	*regs2[SI_MAXCORES];	/**< va of each core second register set (usbh20) */
++	uint32	coresba2[SI_MAXCORES];	/**< address of each core second register set (usbh20) */
++	uint32	coresba_size[SI_MAXCORES]; /**< backplane address space size */
++	uint32	coresba2_size[SI_MAXCORES]; /**< second address space size */
++
++	void	*wrappers[SI_MAXCORES];	/**< other cores wrapper va */
++	uint32	wrapba[SI_MAXCORES];	/**< address of controlling wrapper */
++
++	void	*wrappers2[SI_MAXCORES];	/**< other cores wrapper va */
++	uint32	wrapba2[SI_MAXCORES];	/**< address of controlling wrapper */
++
++	uint32	cia[SI_MAXCORES];	/**< erom cia entry for each core */
++	uint32	cib[SI_MAXCORES];	/**< erom cia entry for each core */
++} si_cores_info_t;
++
++/** misc si info needed by some of the routines */
++typedef struct si_info {
++	struct si_pub pub;		/**< back plane public state (must be first field) */
++
++	void	*osh;			/**< osl os handle */
++	void	*sdh;			/**< bcmsdh handle */
++
++	uint	dev_coreid;		/**< the core provides driver functions */
++	void	*intr_arg;		/**< interrupt callback function arg */
++	si_intrsoff_t intrsoff_fn;	/**< turns chip interrupts off */
++	si_intrsrestore_t intrsrestore_fn; /**< restore chip interrupts */
++	si_intrsenabled_t intrsenabled_fn; /**< check if interrupts are enabled */
++
++	void *pch;			/**< PCI/E core handle */
++
++	bool	memseg;			/**< flag to toggle MEM_SEG register */
++
++	char *vars;
++	uint varsz;
++
++	volatile void	*curmap;		/* current regs va */
++
++	uint	curidx;			/**< current core index */
++	uint	numcores;		/**< # discovered cores */
++
++	void	*curwrap;		/**< current wrapper va */
++
++	uint32	oob_router;		/**< oob router registers for axi */
++
++	si_cores_info_t *cores_info;
++	gci_gpio_item_t	*gci_gpio_head;	/**< gci gpio interrupts head */
++	uint	chipnew;		/**< new chip number */
++	uint second_bar0win;		/**< Backplane region */
++	uint	num_br;		/**< # discovered bridges */
++	uint32	br_wrapba[SI_MAXBR];	/**< address of bridge controlling wrapper */
++	uint32	xtalfreq;
++	uint32	macclk_mul_fact;	/* Multiplication factor necessary to adjust MAC Clock
++	* during ULB Mode operation. One instance where this is used is configuring TSF L-frac
++	* register
++	*/
++	bool	device_removed;
++	uint	axi_num_wrappers;
++	axi_wrapper_t   * axi_wrapper;
++} si_info_t;
++
++
++#define	SI_INFO(sih)	((si_info_t *)(uintptr)sih)
++
++#define	GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
++		ISALIGNED((x), SI_CORE_SIZE))
++#define	GOODREGS(regs)	((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
++#define BADCOREADDR	0
++#define	GOODIDX(idx)	(((uint)idx) < SI_MAXCORES)
++#define	NOREV		-1		/**< Invalid rev */
++
++#define PCI(si)		((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&	\
++			 ((si)->pub.buscoretype == PCI_CORE_ID))
++
++#define PCIE_GEN1(si)	((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&	\
++			 ((si)->pub.buscoretype == PCIE_CORE_ID))
++
++#define PCIE_GEN2(si)	((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&	\
++			 ((si)->pub.buscoretype == PCIE2_CORE_ID))
++
++#define PCIE(si)	(PCIE_GEN1(si) || PCIE_GEN2(si))
++
++#define PCMCIA(si)	((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE))
++
++/** Newer chips can access PCI/PCIE and CC core without requiring to change PCI BAR0 WIN */
++#define SI_FAST(si) (PCIE(si) || (PCI(si) && ((si)->pub.buscorerev >= 13)))
++
++#define CCREGS_FAST(si) \
++	(((si)->curmap == NULL) ? NULL : \
++	    ((volatile char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
++#define PCIEREGS(si) (((volatile char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
++
++/*
++ * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
++ * after core switching to avoid invalid register accesss inside ISR.
++ */
++#define INTR_OFF(si, intr_val) \
++	if ((si)->intrsoff_fn && (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \
++		intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
++#define INTR_RESTORE(si, intr_val) \
++	if ((si)->intrsrestore_fn && (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \
++		(*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
++
++/* dynamic clock control defines */
++#define	LPOMINFREQ		25000		/**< low power oscillator min */
++#define	LPOMAXFREQ		43000		/**< low power oscillator max */
++#define	XTALMINFREQ		19800000	/**< 20 MHz - 1% */
++#define	XTALMAXFREQ		20200000	/**< 20 MHz + 1% */
++#define	PCIMINFREQ		25000000	/**< 25 MHz */
++#define	PCIMAXFREQ		34000000	/**< 33 MHz + fudge */
++
++#define	ILP_DIV_5MHZ		0		/**< ILP = 5 MHz */
++#define	ILP_DIV_1MHZ		4		/**< ILP = 1 MHz */
++
++/* GPIO Based LED powersave defines */
++#define DEFAULT_GPIO_ONTIME	10		/**< Default: 10% on */
++#define DEFAULT_GPIO_OFFTIME	90		/**< Default: 10% on */
++
++#ifndef DEFAULT_GPIOTIMERVAL
++#define DEFAULT_GPIOTIMERVAL  ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
++#endif
++
++/* Silicon Backplane externs */
++extern void sb_scan(si_t *sih, volatile void *regs, uint devid);
++extern uint sb_coreid(si_t *sih);
++extern uint sb_intflag(si_t *sih);
++extern uint sb_flag(si_t *sih);
++extern void sb_setint(si_t *sih, int siflag);
++extern uint sb_corevendor(si_t *sih);
++extern uint sb_corerev(si_t *sih);
++extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
++extern volatile uint32 *sb_corereg_addr(si_t *sih, uint coreidx, uint regoff);
++extern bool sb_iscoreup(si_t *sih);
++extern volatile void *sb_setcoreidx(si_t *sih, uint coreidx);
++extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val);
++extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
++extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val);
++extern void sb_commit(si_t *sih);
++extern uint32 sb_base(uint32 admatch);
++extern uint32 sb_size(uint32 admatch);
++extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
++extern void sb_core_disable(si_t *sih, uint32 bits);
++extern uint32 sb_addrspace(si_t *sih, uint asidx);
++extern uint32 sb_addrspacesize(si_t *sih, uint asidx);
++extern int sb_numaddrspaces(si_t *sih);
++
++extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx);
++
++extern bool sb_taclear(si_t *sih, bool details);
++
++#if defined(BCMDBG_PHYDUMP)
++extern void sb_dumpregs(si_t *sih, struct bcmstrbuf *b);
++#endif 
++
++/* Wake-on-wireless-LAN (WOWL) */
++extern bool sb_pci_pmecap(si_t *sih);
++struct osl_info;
++extern bool sb_pci_fastpmecap(struct osl_info *osh);
++extern bool sb_pci_pmeclr(si_t *sih);
++extern void sb_pci_pmeen(si_t *sih);
++extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset);
++
++/* AMBA Interconnect exported externs */
++extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
++                       void *sdh, char **vars, uint *varsz);
++extern si_t *ai_kattach(osl_t *osh);
++extern void ai_scan(si_t *sih, void *regs, uint devid);
++
++extern uint ai_flag(si_t *sih);
++extern uint ai_flag_alt(si_t *sih);
++extern void ai_setint(si_t *sih, int siflag);
++extern uint ai_coreidx(si_t *sih);
++extern uint ai_corevendor(si_t *sih);
++extern uint ai_corerev(si_t *sih);
++extern volatile uint32 *ai_corereg_addr(si_t *sih, uint coreidx, uint regoff);
++extern bool ai_iscoreup(si_t *sih);
++extern volatile void *ai_setcoreidx(si_t *sih, uint coreidx);
++extern volatile void *ai_setcoreidx_2ndwrap(si_t *sih, uint coreidx);
++extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val);
++extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
++extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val);
++extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
++extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
++extern void ai_d11rsdb_core_reset(si_t *sih, uint32 bits,
++	uint32 resetbits, void *p, void *s);
++extern void ai_core_disable(si_t *sih, uint32 bits);
++extern void ai_d11rsdb_core_disable(const si_info_t *sii, uint32 bits,
++	aidmp_t *pmacai, aidmp_t *smacai);
++extern int ai_numaddrspaces(si_t *sih);
++extern uint32 ai_addrspace(si_t *sih, uint asidx);
++extern uint32 ai_addrspacesize(si_t *sih, uint asidx);
++extern void ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size);
++extern uint ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
++extern void ai_enable_backplane_timeouts(si_t *sih);
++extern uint32 ai_clear_backplane_to(si_t *sih);
++extern uint ai_num_slaveports(si_t *sih, uint coreidx);
++
++#ifdef BCM_BACKPLANE_TIMEOUT
++uint32 ai_clear_backplane_to_fast(si_t *sih, void * addr);
++#endif /* BCM_BACKPLANE_TIMEOUT */
++
++#if defined(AXI_TIMEOUTS) || defined(BCM_BACKPLANE_TIMEOUT)
++extern uint32 ai_clear_backplane_to_per_core(si_t *sih, uint coreid, uint coreunit, void * wrap);
++#endif /* AXI_TIMEOUTS || BCM_BACKPLANE_TIMEOUT */
++
++#if defined(BCMDBG_PHYDUMP)
++extern void ai_dumpregs(si_t *sih, struct bcmstrbuf *b);
++#endif 
++
++extern uint32 ai_wrapper_dump_buf_size(si_t *sih);
++extern uint32 ai_wrapper_dump_binary(si_t *sih, uchar *p);
++
++#define ub_scan(a, b, c) do {} while (0)
++#define ub_flag(a) (0)
++#define ub_setint(a, b) do {} while (0)
++#define ub_coreidx(a) (0)
++#define ub_corevendor(a) (0)
++#define ub_corerev(a) (0)
++#define ub_iscoreup(a) (0)
++#define ub_setcoreidx(a, b) (0)
++#define ub_core_cflags(a, b, c) (0)
++#define ub_core_cflags_wo(a, b, c) do {} while (0)
++#define ub_core_sflags(a, b, c) (0)
++#define ub_corereg(a, b, c, d, e) (0)
++#define ub_core_reset(a, b, c) do {} while (0)
++#define ub_core_disable(a, b) do {} while (0)
++#define ub_numaddrspaces(a) (0)
++#define ub_addrspace(a, b)  (0)
++#define ub_addrspacesize(a, b) (0)
++#define ub_view(a, b) do {} while (0)
++#define ub_dumpregs(a, b) do {} while (0)
++
++#endif	/* _siutils_priv_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_android.c b/module_drivers/drivers/net/wireless/bcmdhd/wl_android.c
+new file mode 100644
+index 000000000..7cce0e574
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_android.c
+@@ -0,0 +1,5511 @@
++/*
++ * Linux cfg80211 driver - Android related functions
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_android.c 710862 2017-07-14 07:43:59Z $
++ */
++
++#include <linux/module.h>
++#include <linux/netdevice.h>
++#include <net/netlink.h>
++#ifdef CONFIG_COMPAT
++#include <linux/compat.h>
++#endif
++
++#include <wl_android.h>
++#include <wldev_common.h>
++#include <wlc_types.h>
++#include <wlioctl.h>
++#include <wlioctl_utils.h>
++#include <bcmutils.h>
++#include <linux_osl.h>
++#include <dhd_dbg.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_config.h>
++#include <bcmip.h>
++#ifdef PNO_SUPPORT
++#include <dhd_pno.h>
++#endif
++#ifdef BCMSDIO
++#include <bcmsdbus.h>
++#endif
++#ifdef WL_CFG80211
++#include <wl_cfg80211.h>
++#endif
++#ifdef DHDTCPACK_SUPPRESS
++#include <dhd_ip.h>
++#endif /* DHDTCPACK_SUPPRESS */
++#include <dhd_linux.h>
++#ifdef DHD_PKT_LOGGING
++#include <dhd_pktlog.h>
++#endif /* DHD_PKT_LOGGING */
++
++#if defined(STAT_REPORT)
++#include <wl_statreport.h>
++#endif /* STAT_REPORT */
++#ifdef WL_ESCAN
++#include <wl_escan.h>
++#endif
++
++#ifndef WL_CFG80211
++#define htod32(i) i
++#define htod16(i) i
++#define dtoh32(i) i
++#define dtoh16(i) i
++#define htodchanspec(i) i
++#define dtohchanspec(i) i
++#endif
++
++uint android_msg_level = ANDROID_ERROR_LEVEL | ANDROID_MSG_LEVEL;
++
++#define ANDROID_ERROR_MSG(x, args...) \
++	do { \
++		if (android_msg_level & ANDROID_ERROR_LEVEL) { \
++			printk(KERN_ERR "[dhd] ANDROID-ERROR) " x, ## args); \
++		} \
++	} while (0)
++#define ANDROID_TRACE_MSG(x, args...) \
++	do { \
++		if (android_msg_level & ANDROID_TRACE_LEVEL) { \
++			printk(KERN_INFO "[dhd] ANDROID-TRACE) " x, ## args); \
++		} \
++	} while (0)
++#define ANDROID_INFO_MSG(x, args...) \
++	do { \
++		if (android_msg_level & ANDROID_INFO_LEVEL) { \
++			printk(KERN_INFO "[dhd] ANDROID-INFO) " x, ## args); \
++		} \
++	} while (0)
++#define ANDROID_ERROR(x) ANDROID_ERROR_MSG x
++#define ANDROID_TRACE(x) ANDROID_TRACE_MSG x
++#define ANDROID_INFO(x) ANDROID_INFO_MSG x
++
++/*
++ * Android private command strings, PLEASE define new private commands here
++ * so they can be updated easily in the future (if needed)
++ */
++
++#define CMD_START		"START"
++#define CMD_STOP		"STOP"
++#define	CMD_SCAN_ACTIVE		"SCAN-ACTIVE"
++#define	CMD_SCAN_PASSIVE	"SCAN-PASSIVE"
++#define CMD_RSSI		"RSSI"
++#define CMD_LINKSPEED		"LINKSPEED"
++#define CMD_RXFILTER_START	"RXFILTER-START"
++#define CMD_RXFILTER_STOP	"RXFILTER-STOP"
++#define CMD_RXFILTER_ADD	"RXFILTER-ADD"
++#define CMD_RXFILTER_REMOVE	"RXFILTER-REMOVE"
++#define CMD_BTCOEXSCAN_START	"BTCOEXSCAN-START"
++#define CMD_BTCOEXSCAN_STOP	"BTCOEXSCAN-STOP"
++#define CMD_BTCOEXMODE		"BTCOEXMODE"
++#define CMD_SETSUSPENDOPT	"SETSUSPENDOPT"
++#define CMD_SETSUSPENDMODE      "SETSUSPENDMODE"
++#define CMD_MAXDTIM_IN_SUSPEND  "MAX_DTIM_IN_SUSPEND"
++#define CMD_P2P_DEV_ADDR	"P2P_DEV_ADDR"
++#define CMD_SETFWPATH		"SETFWPATH"
++#define CMD_SETBAND		"SETBAND"
++#define CMD_GETBAND		"GETBAND"
++#define CMD_COUNTRY		"COUNTRY"
++#ifdef WLMESH_CFG80211
++#define CMD_SAE_SET_PASSWORD "SAE_SET_PASSWORD"
++#define CMD_SET_RSDB_MODE "RSDB_MODE"
++#endif
++#define CMD_P2P_SET_NOA		"P2P_SET_NOA"
++#if !defined WL_ENABLE_P2P_IF
++#define CMD_P2P_GET_NOA			"P2P_GET_NOA"
++#endif /* WL_ENABLE_P2P_IF */
++#define CMD_P2P_SD_OFFLOAD		"P2P_SD_"
++#define CMD_P2P_LISTEN_OFFLOAD		"P2P_LO_"
++#define CMD_P2P_SET_PS		"P2P_SET_PS"
++#define CMD_P2P_ECSA		"P2P_ECSA"
++#define CMD_P2P_INC_BW		"P2P_INCREASE_BW"
++#define CMD_SET_AP_WPS_P2P_IE 		"SET_AP_WPS_P2P_IE"
++#define CMD_SETROAMMODE 	"SETROAMMODE"
++#define CMD_SETIBSSBEACONOUIDATA	"SETIBSSBEACONOUIDATA"
++#define CMD_MIRACAST		"MIRACAST"
++#define CMD_COUNTRY_DELIMITER "/"
++#ifdef WL11ULB
++#define CMD_ULB_MODE "ULB_MODE"
++#define CMD_ULB_BW "ULB_BW"
++#endif /* WL11ULB */
++#ifdef WLFBT
++#define CMD_GET_FTKEY      "GET_FTKEY"
++#endif
++
++#if defined(WL_SUPPORT_AUTO_CHANNEL)
++#define CMD_GET_BEST_CHANNELS	"GET_BEST_CHANNELS"
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++
++#define CMD_80211_MODE    "MODE"  /* 802.11 mode a/b/g/n/ac */
++#define CMD_CHANSPEC      "CHANSPEC"
++#define CMD_DATARATE      "DATARATE"
++#define CMD_ASSOC_CLIENTS "ASSOCLIST"
++#define CMD_SET_CSA       "SETCSA"
++#ifdef WL_SUPPORT_AUTO_CHANNEL
++#define CMD_SET_HAPD_AUTO_CHANNEL	"HAPD_AUTO_CHANNEL"
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++#ifdef CUSTOMER_HW4_PRIVATE_CMD
++#ifdef SUPPORT_SET_LPC
++#define CMD_HAPD_LPC_ENABLED		"HAPD_LPC_ENABLED"
++#endif /* SUPPORT_SET_LPC */
++#ifdef SUPPORT_TRIGGER_HANG_EVENT
++#define CMD_TEST_FORCE_HANG		"TEST_FORCE_HANG"
++#endif /* SUPPORT_TRIGGER_HANG_EVENT */
++#ifdef TEST_TX_POWER_CONTROL
++#define CMD_TEST_SET_TX_POWER		"TEST_SET_TX_POWER"
++#define CMD_TEST_GET_TX_POWER		"TEST_GET_TX_POWER"
++#endif /* TEST_TX_POWER_CONTROL */
++#define CMD_SARLIMIT_TX_CONTROL		"SET_TX_POWER_CALLING"
++#endif /* CUSTOMER_HW4_PRIVATE_CMD */
++#define CMD_KEEP_ALIVE		"KEEPALIVE"
++
++
++#ifdef PNO_SUPPORT
++#define CMD_PNOSSIDCLR_SET	"PNOSSIDCLR"
++#define CMD_PNOSETUP_SET	"PNOSETUP "
++#define CMD_PNOENABLE_SET	"PNOFORCE"
++#define CMD_PNODEBUG_SET	"PNODEBUG"
++#define CMD_WLS_BATCHING	"WLS_BATCHING"
++#endif /* PNO_SUPPORT */
++
++#define	CMD_HAPD_MAC_FILTER	"HAPD_MAC_FILTER"
++
++#ifdef CUSTOMER_HW4_PRIVATE_CMD
++
++
++#if defined(SUPPORT_RANDOM_MAC_SCAN)
++#define ENABLE_RANDOM_MAC "ENABLE_RANDOM_MAC"
++#define DISABLE_RANDOM_MAC "DISABLE_RANDOM_MAC"
++#endif /* SUPPORT_RANDOM_MAC_SCAN */
++
++
++#define CMD_CHANGE_RL 	"CHANGE_RL"
++#define CMD_RESTORE_RL  "RESTORE_RL"
++
++#define CMD_SET_RMC_ENABLE			"SETRMCENABLE"
++#define CMD_SET_RMC_TXRATE			"SETRMCTXRATE"
++#define CMD_SET_RMC_ACTPERIOD		"SETRMCACTIONPERIOD"
++#define CMD_SET_RMC_IDLEPERIOD		"SETRMCIDLEPERIOD"
++#define CMD_SET_RMC_LEADER			"SETRMCLEADER"
++#define CMD_SET_RMC_EVENT			"SETRMCEVENT"
++
++#define CMD_SET_SCSCAN		"SETSINGLEANT"
++#define CMD_GET_SCSCAN		"GETSINGLEANT"
++#ifdef WLTDLS
++#define CMD_TDLS_RESET "TDLS_RESET"
++#endif /* WLTDLS */
++
++#ifdef FCC_PWR_LIMIT_2G
++#define CMD_GET_FCC_PWR_LIMIT_2G "GET_FCC_CHANNEL"
++#define CMD_SET_FCC_PWR_LIMIT_2G "SET_FCC_CHANNEL"
++/* CUSTOMER_HW4's value differs from BRCM FW value for enable/disable */
++#define CUSTOMER_HW4_ENABLE		0
++#define CUSTOMER_HW4_DISABLE	-1
++#define CUSTOMER_HW4_EN_CONVERT(i)	(i += 1)
++#endif /* FCC_PWR_LIMIT_2G */
++
++#endif /* CUSTOMER_HW4_PRIVATE_CMD */
++
++
++
++#define CMD_ROAM_OFFLOAD			"SETROAMOFFLOAD"
++#define CMD_INTERFACE_CREATE			"INTERFACE_CREATE"
++#define CMD_INTERFACE_DELETE			"INTERFACE_DELETE"
++#define CMD_GET_LINK_STATUS			"GETLINKSTATUS"
++
++#if defined(DHD_ENABLE_BIGDATA_LOGGING)
++#define CMD_GET_BSS_INFO            "GETBSSINFO"
++#define CMD_GET_ASSOC_REJECT_INFO   "GETASSOCREJECTINFO"
++#endif /* DHD_ENABLE_BIGDATA_LOGGING */
++#define CMD_GET_STA_INFO   "GETSTAINFO"
++
++/* related with CMD_GET_LINK_STATUS */
++#define WL_ANDROID_LINK_VHT					0x01
++#define WL_ANDROID_LINK_MIMO					0x02
++#define WL_ANDROID_LINK_AP_VHT_SUPPORT		0x04
++#define WL_ANDROID_LINK_AP_MIMO_SUPPORT	0x08
++
++#ifdef P2PRESP_WFDIE_SRC
++#define CMD_P2P_SET_WFDIE_RESP      "P2P_SET_WFDIE_RESP"
++#define CMD_P2P_GET_WFDIE_RESP      "P2P_GET_WFDIE_RESP"
++#endif /* P2PRESP_WFDIE_SRC */
++
++#define CMD_DFS_AP_MOVE			"DFS_AP_MOVE"
++#define CMD_WBTEXT_ENABLE		"WBTEXT_ENABLE"
++#define CMD_WBTEXT_PROFILE_CONFIG	"WBTEXT_PROFILE_CONFIG"
++#define CMD_WBTEXT_WEIGHT_CONFIG	"WBTEXT_WEIGHT_CONFIG"
++#define CMD_WBTEXT_TABLE_CONFIG		"WBTEXT_TABLE_CONFIG"
++#define CMD_WBTEXT_DELTA_CONFIG		"WBTEXT_DELTA_CONFIG"
++#define CMD_WBTEXT_BTM_TIMER_THRESHOLD	"WBTEXT_BTM_TIMER_THRESHOLD"
++#define CMD_WBTEXT_BTM_DELTA		"WBTEXT_BTM_DELTA"
++
++#ifdef WLWFDS
++#define CMD_ADD_WFDS_HASH	"ADD_WFDS_HASH"
++#define CMD_DEL_WFDS_HASH	"DEL_WFDS_HASH"
++#endif /* WLWFDS */
++
++#ifdef SET_RPS_CPUS
++#define CMD_RPSMODE  "RPSMODE"
++#endif /* SET_RPS_CPUS */
++
++#ifdef BT_WIFI_HANDOVER
++#define CMD_TBOW_TEARDOWN "TBOW_TEARDOWN"
++#endif /* BT_WIFI_HANDOVER */
++
++#define CMD_MURX_BFE_CAP "MURX_BFE_CAP"
++
++#ifdef SUPPORT_AP_HIGHER_BEACONRATE
++#define CMD_SET_AP_BEACONRATE				"SET_AP_BEACONRATE"
++#define CMD_GET_AP_BASICRATE				"GET_AP_BASICRATE"
++#endif /* SUPPORT_AP_HIGHER_BEACONRATE */
++
++#ifdef SUPPORT_AP_RADIO_PWRSAVE
++#define CMD_SET_AP_RPS						"SET_AP_RPS"
++#define CMD_GET_AP_RPS						"GET_AP_RPS"
++#define CMD_SET_AP_RPS_PARAMS				"SET_AP_RPS_PARAMS"
++#endif /* SUPPORT_AP_RADIO_PWRSAVE */
++
++#ifdef SUPPORT_RSSI_LOGGING
++#define CMD_SET_RSSI_LOGGING				"SET_RSSI_LOGGING"
++#define CMD_GET_RSSI_LOGGING				"GET_RSSI_LOGGING"
++#define CMD_GET_RSSI_PER_ANT				"GET_RSSI_PER_ANT"
++#endif /* SUPPORT_RSSI_LOGGING */
++
++#define CMD_GET_SNR							"GET_SNR"
++
++/* miracast related definition */
++#define MIRACAST_MODE_OFF	0
++#define MIRACAST_MODE_SOURCE	1
++#define MIRACAST_MODE_SINK	2
++
++#ifndef MIRACAST_AMPDU_SIZE
++#define MIRACAST_AMPDU_SIZE	8
++#endif
++
++#ifndef MIRACAST_MCHAN_ALGO
++#define MIRACAST_MCHAN_ALGO     1
++#endif
++
++#ifndef MIRACAST_MCHAN_BW
++#define MIRACAST_MCHAN_BW       25
++#endif
++
++#ifdef CONNECTION_STATISTICS
++#define CMD_GET_CONNECTION_STATS	"GET_CONNECTION_STATS"
++
++struct connection_stats {
++	u32 txframe;
++	u32 txbyte;
++	u32 txerror;
++	u32 rxframe;
++	u32 rxbyte;
++	u32 txfail;
++	u32 txretry;
++	u32 txretrie;
++	u32 txrts;
++	u32 txnocts;
++	u32 txexptime;
++	u32 txrate;
++	u8	chan_idle;
++};
++#endif /* CONNECTION_STATISTICS */
++
++#ifdef SUPPORT_LQCM
++#define CMD_SET_LQCM_ENABLE			"SET_LQCM_ENABLE"
++#define CMD_GET_LQCM_REPORT			"GET_LQCM_REPORT"
++#endif
++
++static LIST_HEAD(miracast_resume_list);
++#ifdef WL_CFG80211
++static u8 miracast_cur_mode;
++#endif
++
++#ifdef DHD_LOG_DUMP
++#define CMD_NEW_DEBUG_PRINT_DUMP			"DEBUG_DUMP"
++extern void dhd_schedule_log_dump(dhd_pub_t *dhdp);
++extern int dhd_bus_mem_dump(dhd_pub_t *dhd);
++#endif /* DHD_LOG_DUMP */
++
++#ifdef DHD_HANG_SEND_UP_TEST
++#define CMD_MAKE_HANG  "MAKE_HANG"
++#endif /* CMD_DHD_HANG_SEND_UP_TEST */
++#ifdef DHD_DEBUG_UART
++extern bool dhd_debug_uart_is_running(struct net_device *dev);
++#endif	/* DHD_DEBUG_UART */
++
++struct io_cfg {
++	s8 *iovar;
++	s32 param;
++	u32 ioctl;
++	void *arg;
++	u32 len;
++	struct list_head list;
++};
++
++#if defined(BCMFW_ROAM_ENABLE)
++#define CMD_SET_ROAMPREF	"SET_ROAMPREF"
++
++#define MAX_NUM_SUITES		10
++#define WIDTH_AKM_SUITE		8
++#define JOIN_PREF_RSSI_LEN		0x02
++#define JOIN_PREF_RSSI_SIZE		4	/* RSSI pref header size in bytes */
++#define JOIN_PREF_WPA_HDR_SIZE		4 /* WPA pref header size in bytes */
++#define JOIN_PREF_WPA_TUPLE_SIZE	12	/* Tuple size in bytes */
++#define JOIN_PREF_MAX_WPA_TUPLES	16
++#define MAX_BUF_SIZE		(JOIN_PREF_RSSI_SIZE + JOIN_PREF_WPA_HDR_SIZE +	\
++				           (JOIN_PREF_WPA_TUPLE_SIZE * JOIN_PREF_MAX_WPA_TUPLES))
++#endif /* BCMFW_ROAM_ENABLE */
++
++#ifdef WL_NATOE
++
++#define CMD_NATOE		"NATOE"
++
++#define NATOE_MAX_PORT_NUM	65535
++
++/* natoe command info structure */
++typedef struct wl_natoe_cmd_info {
++	uint8  *command;        /* pointer to the actual command */
++	uint16 tot_len;        /* total length of the command */
++	uint16 bytes_written;  /* Bytes written for get response */
++} wl_natoe_cmd_info_t;
++
++typedef struct wl_natoe_sub_cmd wl_natoe_sub_cmd_t;
++typedef int (natoe_cmd_handler_t)(struct net_device *dev,
++		const wl_natoe_sub_cmd_t *cmd, char *command, wl_natoe_cmd_info_t *cmd_info);
++
++struct wl_natoe_sub_cmd {
++	char *name;
++	uint8  version;              /* cmd  version */
++	uint16 id;                   /* id for the dongle f/w switch/case */
++	uint16 type;                 /* base type of argument */
++	natoe_cmd_handler_t *handler; /* cmd handler  */
++};
++
++#define WL_ANDROID_NATOE_FUNC(suffix) wl_android_natoe_subcmd_ ##suffix
++static int wl_android_process_natoe_cmd(struct net_device *dev,
++		char *command, int total_len);
++static int wl_android_natoe_subcmd_enable(struct net_device *dev,
++		const wl_natoe_sub_cmd_t *cmd, char *command, wl_natoe_cmd_info_t *cmd_info);
++static int wl_android_natoe_subcmd_config_ips(struct net_device *dev,
++		const wl_natoe_sub_cmd_t *cmd, char *command, wl_natoe_cmd_info_t *cmd_info);
++static int wl_android_natoe_subcmd_config_ports(struct net_device *dev,
++		const wl_natoe_sub_cmd_t *cmd, char *command, wl_natoe_cmd_info_t *cmd_info);
++static int wl_android_natoe_subcmd_dbg_stats(struct net_device *dev,
++		const wl_natoe_sub_cmd_t *cmd, char *command, wl_natoe_cmd_info_t *cmd_info);
++static int wl_android_natoe_subcmd_tbl_cnt(struct net_device *dev,
++		const wl_natoe_sub_cmd_t *cmd, char *command, wl_natoe_cmd_info_t *cmd_info);
++
++static const wl_natoe_sub_cmd_t natoe_cmd_list[] = {
++	/* wl natoe enable [0/1] or new: "wl natoe [0/1]" */
++	{"enable", 0x01, WL_NATOE_CMD_ENABLE,
++	IOVT_BUFFER, WL_ANDROID_NATOE_FUNC(enable)
++	},
++	{"config_ips", 0x01, WL_NATOE_CMD_CONFIG_IPS,
++	IOVT_BUFFER, WL_ANDROID_NATOE_FUNC(config_ips)
++	},
++	{"config_ports", 0x01, WL_NATOE_CMD_CONFIG_PORTS,
++	IOVT_BUFFER, WL_ANDROID_NATOE_FUNC(config_ports)
++	},
++	{"stats", 0x01, WL_NATOE_CMD_DBG_STATS,
++	IOVT_BUFFER, WL_ANDROID_NATOE_FUNC(dbg_stats)
++	},
++	{"tbl_cnt", 0x01, WL_NATOE_CMD_TBL_CNT,
++	IOVT_BUFFER, WL_ANDROID_NATOE_FUNC(tbl_cnt)
++	},
++	{NULL, 0, 0, 0, NULL}
++};
++
++#endif /* WL_NATOE */
++
++#ifdef SET_PCIE_IRQ_CPU_CORE
++#define CMD_PCIE_IRQ_CORE	"PCIE_IRQ_CORE"
++#endif /* SET_PCIE_IRQ_CPU_CORE */
++
++#ifdef WLADPS_PRIVATE_CMD
++#define CMD_SET_ADPS	"SET_ADPS"
++#define CMD_GET_ADPS	"GET_ADPS"
++#endif /* WLADPS_PRIVATE_CMD */
++
++#ifdef DHD_PKT_LOGGING
++#define CMD_PKTLOG_FILTER_ENABLE	"PKTLOG_FILTER_ENABLE"
++#define CMD_PKTLOG_FILTER_DISABLE	"PKTLOG_FILTER_DISABLE"
++#define CMD_PKTLOG_FILTER_PATTERN_ENABLE	"PKTLOG_FILTER_PATTERN_ENABLE"
++#define CMD_PKTLOG_FILTER_PATTERN_DISABLE	"PKTLOG_FILTER_PATTERN_DISABLE"
++#define CMD_PKTLOG_FILTER_ADD	"PKTLOG_FILTER_ADD"
++#define CMD_PKTLOG_FILTER_INFO	"PKTLOG_FILTER_INFO"
++#define CMD_PKTLOG_START	"PKTLOG_START"
++#define CMD_PKTLOG_STOP		"PKTLOG_STOP"
++#define CMD_PKTLOG_FILTER_EXIST "PKTLOG_FILTER_EXIST"
++#endif /* DHD_PKT_LOGGING */
++
++#if defined(STAT_REPORT)
++#define CMD_STAT_REPORT_GET_START	"STAT_REPORT_GET_START"
++#define CMD_STAT_REPORT_GET_NEXT	"STAT_REPORT_GET_NEXT"
++#endif /* STAT_REPORT */
++
++
++#ifdef SUPPORT_LQCM
++#define LQCM_ENAB_MASK			0x000000FF	/* LQCM enable flag mask */
++#define LQCM_TX_INDEX_MASK		0x0000FF00	/* LQCM tx index mask */
++#define LQCM_RX_INDEX_MASK		0x00FF0000	/* LQCM rx index mask */
++
++#define LQCM_TX_INDEX_SHIFT		8	/* LQCM tx index shift */
++#define LQCM_RX_INDEX_SHIFT		16	/* LQCM rx index shift */
++#endif /* SUPPORT_LQCM */
++
++/**
++ * Extern function declarations (TODO: move them to dhd_linux.h)
++ */
++int dhd_net_bus_devreset(struct net_device *dev, uint8 flag);
++int dhd_dev_init_ioctl(struct net_device *dev);
++#ifdef WL_CFG80211
++int wl_cfg80211_get_p2p_dev_addr(struct net_device *net, struct ether_addr *p2pdev_addr);
++int wl_cfg80211_set_btcoex_dhcp(struct net_device *dev, dhd_pub_t *dhd, char *command);
++#else
++int wl_cfg80211_get_p2p_dev_addr(struct net_device *net, struct ether_addr *p2pdev_addr)
++{ return 0; }
++int wl_cfg80211_set_p2p_noa(struct net_device *net, char* buf, int len)
++{ return 0; }
++int wl_cfg80211_get_p2p_noa(struct net_device *net, char* buf, int len)
++{ return 0; }
++int wl_cfg80211_set_p2p_ps(struct net_device *net, char* buf, int len)
++{ return 0; }
++int wl_cfg80211_set_p2p_ecsa(struct net_device *net, char* buf, int len)
++{ return 0; }
++int wl_cfg80211_increase_p2p_bw(struct net_device *net, char* buf, int len)
++{ return 0; }
++#endif /* WL_CFG80211 */
++#ifdef WBTEXT
++static int wl_android_wbtext(struct net_device *dev, char *command, int total_len);
++static int wl_cfg80211_wbtext_btm_timer_threshold(struct net_device *dev,
++	char *command, int total_len);
++static int wl_cfg80211_wbtext_btm_delta(struct net_device *dev,
++	char *command, int total_len);
++#endif /* WBTEXT */
++
++#ifdef ENABLE_4335BT_WAR
++extern int bcm_bt_lock(int cookie);
++extern void bcm_bt_unlock(int cookie);
++static int lock_cookie_wifi = 'W' | 'i'<<8 | 'F'<<16 | 'i'<<24;	/* cookie is "WiFi" */
++#endif /* ENABLE_4335BT_WAR */
++
++extern bool ap_fw_loaded;
++extern char iface_name[IFNAMSIZ];
++
++/**
++ * Local (static) functions and variables
++ */
++
++/* Initialize g_wifi_on to 1 so dhd_bus_start will be called for the first
++ * time (only) in dhd_open, subsequential wifi on will be handled by
++ * wl_android_wifi_on
++ */
++int g_wifi_on = TRUE;
++
++/**
++ * Local (static) function definitions
++ */
++
++#ifdef WLWFDS
++static int wl_android_set_wfds_hash(
++	struct net_device *dev, char *command, int total_len, bool enable)
++{
++	int error = 0;
++	wl_p2p_wfds_hash_t *wfds_hash = NULL;
++	char *smbuf = NULL;
++	smbuf = kmalloc(WLC_IOCTL_MAXLEN, GFP_KERNEL);
++
++	if (smbuf == NULL) {
++		ANDROID_ERROR(("%s: failed to allocated memory %d bytes\n",
++			__FUNCTION__, WLC_IOCTL_MAXLEN));
++		return -ENOMEM;
++	}
++
++	if (enable) {
++		wfds_hash = (wl_p2p_wfds_hash_t *)(command + strlen(CMD_ADD_WFDS_HASH) + 1);
++		error = wldev_iovar_setbuf(dev, "p2p_add_wfds_hash", wfds_hash,
++			sizeof(wl_p2p_wfds_hash_t), smbuf, WLC_IOCTL_MAXLEN, NULL);
++	}
++	else {
++		wfds_hash = (wl_p2p_wfds_hash_t *)(command + strlen(CMD_DEL_WFDS_HASH) + 1);
++		error = wldev_iovar_setbuf(dev, "p2p_del_wfds_hash", wfds_hash,
++			sizeof(wl_p2p_wfds_hash_t), smbuf, WLC_IOCTL_MAXLEN, NULL);
++	}
++
++	if (error) {
++		ANDROID_ERROR(("%s: failed to %s, error=%d\n", __FUNCTION__, command, error));
++	}
++
++	if (smbuf)
++		kfree(smbuf);
++	return error;
++}
++#endif /* WLWFDS */
++
++static int wl_android_get_link_speed(struct net_device *net, char *command, int total_len)
++{
++	int link_speed;
++	int bytes_written;
++	int error;
++
++	error = wldev_get_link_speed(net, &link_speed);
++	if (error) {
++		ANDROID_ERROR(("Get linkspeed failed \n"));
++		return -1;
++	}
++
++	/* Convert Kbps to Android Mbps */
++	link_speed = link_speed / 1000;
++	bytes_written = snprintf(command, total_len, "LinkSpeed %d", link_speed);
++	ANDROID_INFO(("%s: command result is %s\n", __FUNCTION__, command));
++	return bytes_written;
++}
++
++static int wl_android_get_rssi(struct net_device *net, char *command, int total_len)
++{
++	wlc_ssid_t ssid = {0, {0}};
++	int bytes_written = 0;
++	int error = 0;
++	scb_val_t scbval;
++	char *delim = NULL;
++	struct net_device *target_ndev = net;
++#ifdef WL_VIRTUAL_APSTA
++	char *pos = NULL;
++	struct bcm_cfg80211 *cfg;
++#endif /* WL_VIRTUAL_APSTA */
++
++	delim = strchr(command, ' ');
++	/* For Ap mode rssi command would be
++	 * driver rssi <sta_mac_addr>
++	 * for STA/GC mode
++	 * driver rssi
++	*/
++	if (delim) {
++		/* Ap/GO mode
++		* driver rssi <sta_mac_addr>
++		*/
++		ANDROID_TRACE(("%s: cmd:%s\n", __FUNCTION__, delim));
++		/* skip space from delim after finding char */
++		delim++;
++		if (!(bcm_ether_atoe((delim), &scbval.ea)))
++		{
++			ANDROID_ERROR(("%s:address err\n", __FUNCTION__));
++			return -1;
++		}
++	        scbval.val = htod32(0);
++		ANDROID_TRACE(("%s: address:"MACDBG, __FUNCTION__, MAC2STRDBG(scbval.ea.octet)));
++#ifdef WL_VIRTUAL_APSTA
++		/* RSDB AP may have another virtual interface
++		 * In this case, format of private command is as following,
++		 * DRIVER rssi <sta_mac_addr> <AP interface name>
++		 */
++
++		/* Current position is start of MAC address string */
++		pos = delim;
++		delim = strchr(pos, ' ');
++		if (delim) {
++			/* skip space from delim after finding char */
++			delim++;
++			if (strnlen(delim, IFNAMSIZ)) {
++				cfg = wl_get_cfg(net);
++				target_ndev = wl_get_ap_netdev(cfg, delim);
++				if (target_ndev == NULL)
++					target_ndev = net;
++			}
++		}
++#endif /* WL_VIRTUAL_APSTA */
++	}
++	else {
++		/* STA/GC mode */
++		memset(&scbval, 0, sizeof(scb_val_t));
++	}
++
++	error = wldev_get_rssi(target_ndev, &scbval);
++	if (error)
++		return -1;
++#if defined(RSSIOFFSET)
++	scbval.val = wl_update_rssi_offset(net, scbval.val);
++#endif
++
++	error = wldev_get_ssid(target_ndev, &ssid);
++	if (error)
++		return -1;
++	if ((ssid.SSID_len == 0) || (ssid.SSID_len > DOT11_MAX_SSID_LEN)) {
++		ANDROID_ERROR(("%s: wldev_get_ssid failed\n", __FUNCTION__));
++	} else if (total_len <= ssid.SSID_len) {
++		return -ENOMEM;
++	} else {
++		memcpy(command, ssid.SSID, ssid.SSID_len);
++		bytes_written = ssid.SSID_len;
++	}
++	if ((total_len - bytes_written) < (strlen(" rssi -XXX") + 1))
++		return -ENOMEM;
++
++	bytes_written += scnprintf(&command[bytes_written], total_len - bytes_written,
++		" rssi %d", scbval.val);
++	command[bytes_written] = '\0';
++
++	ANDROID_TRACE(("%s: command result is %s (%d)\n", __FUNCTION__, command, bytes_written));
++	return bytes_written;
++}
++
++static int wl_android_set_suspendopt(struct net_device *dev, char *command, int total_len)
++{
++	int suspend_flag;
++	int ret_now;
++	int ret = 0;
++
++	suspend_flag = *(command + strlen(CMD_SETSUSPENDOPT) + 1) - '0';
++
++	if (suspend_flag != 0) {
++		suspend_flag = 1;
++	}
++	ret_now = net_os_set_suspend_disable(dev, suspend_flag);
++
++	if (ret_now != suspend_flag) {
++		if (!(ret = net_os_set_suspend(dev, ret_now, 1))) {
++			ANDROID_INFO(("%s: Suspend Flag %d -> %d\n",
++				__FUNCTION__, ret_now, suspend_flag));
++		} else {
++			ANDROID_ERROR(("%s: failed %d\n", __FUNCTION__, ret));
++		}
++	}
++
++	return ret;
++}
++
++static int wl_android_set_suspendmode(struct net_device *dev, char *command, int total_len)
++{
++	int ret = 0;
++
++#if !defined(CONFIG_HAS_EARLYSUSPEND) || !defined(DHD_USE_EARLYSUSPEND)
++	int suspend_flag;
++
++	suspend_flag = *(command + strlen(CMD_SETSUSPENDMODE) + 1) - '0';
++	if (suspend_flag != 0)
++		suspend_flag = 1;
++
++	if (!(ret = net_os_set_suspend(dev, suspend_flag, 0)))
++		ANDROID_INFO(("%s: Suspend Mode %d\n", __FUNCTION__, suspend_flag));
++	else
++		ANDROID_ERROR(("%s: failed %d\n", __FUNCTION__, ret));
++#endif
++
++	return ret;
++}
++
++#ifdef WL_CFG80211
++int wl_android_get_80211_mode(struct net_device *dev, char *command, int total_len)
++{
++	uint8 mode[5];
++	int  error = 0;
++	int bytes_written = 0;
++
++	error = wldev_get_mode(dev, mode, sizeof(mode));
++	if (error)
++		return -1;
++
++	ANDROID_INFO(("%s: mode:%s\n", __FUNCTION__, mode));
++	bytes_written = snprintf(command, total_len, "%s %s", CMD_80211_MODE, mode);
++	ANDROID_INFO(("%s: command:%s EXIT\n", __FUNCTION__, command));
++	return bytes_written;
++
++}
++
++extern chanspec_t
++wl_chspec_driver_to_host(chanspec_t chanspec);
++int wl_android_get_chanspec(struct net_device *dev, char *command, int total_len)
++{
++	int error = 0;
++	int bytes_written = 0;
++	int chsp = {0};
++	uint16 band = 0;
++	uint16 bw = 0;
++	uint16 channel = 0;
++	u32 sb = 0;
++	chanspec_t chanspec;
++
++	/* command is
++	 * driver chanspec
++	 */
++	error = wldev_iovar_getint(dev, "chanspec", &chsp);
++	if (error)
++		return -1;
++
++	chanspec = wl_chspec_driver_to_host(chsp);
++	ANDROID_INFO(("%s:return value of chanspec:%x\n", __FUNCTION__, chanspec));
++
++	channel = chanspec & WL_CHANSPEC_CHAN_MASK;
++	band = chanspec & WL_CHANSPEC_BAND_MASK;
++	bw = chanspec & WL_CHANSPEC_BW_MASK;
++
++	ANDROID_INFO(("%s:channel:%d band:%d bandwidth:%d\n", __FUNCTION__, channel, band, bw));
++
++	if (bw == WL_CHANSPEC_BW_80)
++		bw = WL_CH_BANDWIDTH_80MHZ;
++	else if (bw == WL_CHANSPEC_BW_40)
++		bw = WL_CH_BANDWIDTH_40MHZ;
++	else if	(bw == WL_CHANSPEC_BW_20)
++		bw = WL_CH_BANDWIDTH_20MHZ;
++	else
++		bw = WL_CH_BANDWIDTH_20MHZ;
++
++	if (bw == WL_CH_BANDWIDTH_40MHZ) {
++		if (CHSPEC_SB_UPPER(chanspec)) {
++			channel += CH_10MHZ_APART;
++		} else {
++			channel -= CH_10MHZ_APART;
++		}
++	}
++	else if (bw == WL_CH_BANDWIDTH_80MHZ) {
++		sb = chanspec & WL_CHANSPEC_CTL_SB_MASK;
++		if (sb == WL_CHANSPEC_CTL_SB_LL) {
++			channel -= (CH_10MHZ_APART + CH_20MHZ_APART);
++		} else if (sb == WL_CHANSPEC_CTL_SB_LU) {
++			channel -= CH_10MHZ_APART;
++		} else if (sb == WL_CHANSPEC_CTL_SB_UL) {
++			channel += CH_10MHZ_APART;
++		} else {
++			/* WL_CHANSPEC_CTL_SB_UU */
++			channel += (CH_10MHZ_APART + CH_20MHZ_APART);
++		}
++	}
++	bytes_written = snprintf(command, total_len, "%s channel %d band %s bw %d", CMD_CHANSPEC,
++		channel, band == WL_CHANSPEC_BAND_5G ? "5G":"2G", bw);
++
++	ANDROID_INFO(("%s: command:%s EXIT\n", __FUNCTION__, command));
++	return bytes_written;
++
++}
++#endif
++
++/* returns current datarate datarate returned from firmware are in 500kbps */
++int wl_android_get_datarate(struct net_device *dev, char *command, int total_len)
++{
++	int  error = 0;
++	int datarate = 0;
++	int bytes_written = 0;
++
++	error = wldev_get_datarate(dev, &datarate);
++	if (error)
++		return -1;
++
++	ANDROID_INFO(("%s:datarate:%d\n", __FUNCTION__, datarate));
++
++	bytes_written = snprintf(command, total_len, "%s %d", CMD_DATARATE, (datarate/2));
++	return bytes_written;
++}
++int wl_android_get_assoclist(struct net_device *dev, char *command, int total_len)
++{
++	int  error = 0;
++	int bytes_written = 0;
++	uint i;
++	char mac_buf[MAX_NUM_OF_ASSOCLIST *
++		sizeof(struct ether_addr) + sizeof(uint)] = {0};
++	struct maclist *assoc_maclist = (struct maclist *)mac_buf;
++
++	ANDROID_TRACE(("%s: ENTER\n", __FUNCTION__));
++
++	assoc_maclist->count = htod32(MAX_NUM_OF_ASSOCLIST);
++
++	error = wldev_ioctl_get(dev, WLC_GET_ASSOCLIST, assoc_maclist, sizeof(mac_buf));
++	if (error)
++		return -1;
++
++	assoc_maclist->count = dtoh32(assoc_maclist->count);
++	bytes_written = snprintf(command, total_len, "%s listcount: %d Stations:",
++		CMD_ASSOC_CLIENTS, assoc_maclist->count);
++
++	for (i = 0; i < assoc_maclist->count; i++) {
++		bytes_written += snprintf(command + bytes_written, total_len, " " MACDBG,
++			MAC2STRDBG(assoc_maclist->ea[i].octet));
++	}
++	return bytes_written;
++
++}
++
++#ifdef WL_CFG80211
++extern chanspec_t
++wl_chspec_host_to_driver(chanspec_t chanspec);
++static int wl_android_set_csa(struct net_device *dev, char *command, int total_len)
++{
++	int error = 0;
++	char smbuf[WLC_IOCTL_SMLEN];
++	wl_chan_switch_t csa_arg;
++	u32 chnsp = 0;
++	int err = 0;
++
++	ANDROID_INFO(("%s: command:%s\n", __FUNCTION__, command));
++
++	command = (command + strlen(CMD_SET_CSA));
++	/* Order is mode, count channel */
++	if (!*++command) {
++		ANDROID_ERROR(("%s:error missing arguments\n", __FUNCTION__));
++		return -1;
++	}
++	csa_arg.mode = bcm_atoi(command);
++
++	if (csa_arg.mode != 0 && csa_arg.mode != 1) {
++		ANDROID_ERROR(("Invalid mode\n"));
++		return -1;
++	}
++
++	if (!*++command) {
++		ANDROID_ERROR(("%s:error missing count\n", __FUNCTION__));
++		return -1;
++	}
++	command++;
++	csa_arg.count = bcm_atoi(command);
++
++	csa_arg.reg = 0;
++	csa_arg.chspec = 0;
++	command += 2;
++	if (!*command) {
++		ANDROID_ERROR(("%s:error missing channel\n", __FUNCTION__));
++		return -1;
++	}
++
++	chnsp = wf_chspec_aton(command);
++	if (chnsp == 0)	{
++		ANDROID_ERROR(("%s:chsp is not correct\n", __FUNCTION__));
++		return -1;
++	}
++	chnsp = wl_chspec_host_to_driver(chnsp);
++	csa_arg.chspec = chnsp;
++
++	if (chnsp & WL_CHANSPEC_BAND_5G) {
++		u32 chanspec = chnsp;
++		err = wldev_iovar_getint(dev, "per_chan_info", &chanspec);
++		if (!err) {
++			if ((chanspec & WL_CHAN_RADAR) || (chanspec & WL_CHAN_PASSIVE)) {
++				ANDROID_ERROR(("Channel is radar sensitive\n"));
++				return -1;
++			}
++			if (chanspec == 0) {
++				ANDROID_ERROR(("Invalid hw channel\n"));
++				return -1;
++			}
++		} else  {
++			ANDROID_ERROR(("does not support per_chan_info\n"));
++			return -1;
++		}
++		ANDROID_INFO(("non radar sensitivity\n"));
++	}
++	error = wldev_iovar_setbuf(dev, "csa", &csa_arg, sizeof(csa_arg),
++		smbuf, sizeof(smbuf), NULL);
++	if (error) {
++		ANDROID_ERROR(("%s:set csa failed:%d\n", __FUNCTION__, error));
++		return -1;
++	}
++	return 0;
++}
++#endif
++
++static int
++wl_android_set_max_dtim(struct net_device *dev, char *command, int total_len)
++{
++	int ret = 0;
++	int dtim_flag;
++
++	dtim_flag = *(command + strlen(CMD_MAXDTIM_IN_SUSPEND) + 1) - '0';
++
++	if (!(ret = net_os_set_max_dtim_enable(dev, dtim_flag))) {
++		ANDROID_TRACE(("%s: use Max bcn_li_dtim in suspend %s\n",
++			__FUNCTION__, (dtim_flag ? "Enable" : "Disable")));
++	} else {
++		ANDROID_ERROR(("%s: failed %d\n", __FUNCTION__, ret));
++	}
++
++	return ret;
++}
++
++static int wl_android_get_band(struct net_device *dev, char *command, int total_len)
++{
++	uint band;
++	int bytes_written;
++	int error;
++
++	error = wldev_get_band(dev, &band);
++	if (error)
++		return -1;
++	bytes_written = snprintf(command, total_len, "Band %d", band);
++	return bytes_written;
++}
++
++#ifdef CUSTOMER_HW4_PRIVATE_CMD
++
++#ifdef WLTDLS
++int wl_android_tdls_reset(struct net_device *dev)
++{
++	int ret = 0;
++	ret = dhd_tdls_enable(dev, false, false, NULL);
++	if (ret < 0) {
++		ANDROID_ERROR(("Disable tdls failed. %d\n", ret));
++		return ret;
++	}
++	ret = dhd_tdls_enable(dev, true, true, NULL);
++	if (ret < 0) {
++		ANDROID_ERROR(("enable tdls failed. %d\n", ret));
++		return ret;
++	}
++	return 0;
++}
++#endif /* WLTDLS */
++#ifdef FCC_PWR_LIMIT_2G
++int
++wl_android_set_fcc_pwr_limit_2g(struct net_device *dev, char *command, int total_len)
++{
++	int error = 0;
++	int enable = 0;
++
++	sscanf(command+sizeof("SET_FCC_CHANNEL"), "%d", &enable);
++
++	if ((enable != CUSTOMER_HW4_ENABLE) && (enable != CUSTOMER_HW4_DISABLE)) {
++		ANDROID_ERROR(("%s: Invalid data\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	CUSTOMER_HW4_EN_CONVERT(enable);
++
++	ANDROID_ERROR(("%s: fccpwrlimit2g set (%d)\n", __FUNCTION__, enable));
++	error = wldev_iovar_setint(dev, "fccpwrlimit2g", enable);
++	if (error) {
++		ANDROID_ERROR(("%s: fccpwrlimit2g set returned (%d)\n", __FUNCTION__, error));
++		return BCME_ERROR;
++	}
++
++	return error;
++}
++
++int
++wl_android_get_fcc_pwr_limit_2g(struct net_device *dev, char *command, int total_len)
++{
++	int error = 0;
++	int enable = 0;
++	int bytes_written = 0;
++
++	error = wldev_iovar_getint(dev, "fccpwrlimit2g", &enable);
++	if (error) {
++		ANDROID_ERROR(("%s: fccpwrlimit2g get error (%d)\n", __FUNCTION__, error));
++		return BCME_ERROR;
++	}
++	ANDROID_ERROR(("%s: fccpwrlimit2g get (%d)\n", __FUNCTION__, enable));
++
++	bytes_written = snprintf(command, total_len, "%s %d", CMD_GET_FCC_PWR_LIMIT_2G, enable);
++
++	return bytes_written;
++}
++#endif /* FCC_PWR_LIMIT_2G */
++
++s32
++wl_cfg80211_get_sta_info(struct net_device *dev, char* command, int total_len)
++{
++	static char iovar_buf[WLC_IOCTL_MAXLEN];
++	int bytes_written = -1, ret = 0;
++	char *pcmd = command;
++	char *str;
++	sta_info_t *sta = NULL;
++	wl_cnt_wlc_t* wlc_cnt = NULL;
++	struct ether_addr mac;
++
++	/* Client information */
++	uint16 cap = 0;
++	uint32 rxrtry = 0;
++	uint32 rxmulti = 0;
++
++	ANDROID_TRACE(("%s\n", command));
++	str = bcmstrtok(&pcmd, " ", NULL);
++	if (str) {
++		str = bcmstrtok(&pcmd, " ", NULL);
++		/* If GETSTAINFO subcmd name is not provided, return error */
++		if (str == NULL) {
++			ANDROID_ERROR(("GETSTAINFO subcmd not provided %s\n", __FUNCTION__));
++			goto error;
++		}
++
++		memset(&mac, 0, ETHER_ADDR_LEN);
++		if ((bcm_ether_atoe((str), &mac))) {
++			/* get the sta info */
++			ret = wldev_iovar_getbuf(dev, "sta_info",
++				(struct ether_addr *)mac.octet,
++				ETHER_ADDR_LEN, iovar_buf, WLC_IOCTL_SMLEN, NULL);
++			if (ret < 0) {
++				ANDROID_ERROR(("Get sta_info ERR %d\n", ret));
++				goto error;
++			}
++
++			sta = (sta_info_t *)iovar_buf;
++			cap = dtoh16(sta->cap);
++			rxrtry = dtoh32(sta->rx_pkts_retried);
++			rxmulti = dtoh32(sta->rx_mcast_pkts);
++		} else if ((!strncmp(str, "all", 3)) || (!strncmp(str, "ALL", 3))) {
++			/* get counters info */
++			ret = wldev_iovar_getbuf(dev, "counters", NULL, 0,
++				iovar_buf, WLC_IOCTL_MAXLEN, NULL);
++			if (unlikely(ret)) {
++				ANDROID_ERROR(("counters error (%d) - size = %zu\n",
++					ret, sizeof(wl_cnt_wlc_t)));
++				goto error;
++			}
++			ret = wl_cntbuf_to_xtlv_format(NULL, iovar_buf, WL_CNTBUF_MAX_SIZE, 0);
++			if (ret != BCME_OK) {
++				ANDROID_ERROR(("wl_cntbuf_to_xtlv_format ERR %d\n", ret));
++				goto error;
++			}
++			if (!(wlc_cnt = GET_WLCCNT_FROM_CNTBUF(iovar_buf))) {
++				ANDROID_ERROR(("wlc_cnt NULL!\n"));
++				goto error;
++			}
++
++			rxrtry = dtoh32(wlc_cnt->rxrtry);
++			rxmulti = dtoh32(wlc_cnt->rxmulti);
++		} else {
++			ANDROID_ERROR(("Get address fail\n"));
++			goto error;
++		}
++	} else {
++		ANDROID_ERROR(("Command ERR\n"));
++		goto error;
++	}
++
++	bytes_written = snprintf(command, total_len,
++		"%s %s Rx_Retry_Pkts=%d Rx_BcMc_Pkts=%d CAP=%04x\n",
++		CMD_GET_STA_INFO, str, rxrtry, rxmulti, cap);
++
++	ANDROID_TRACE(("%s", command));
++
++error:
++	return bytes_written;
++}
++#endif
++
++#ifdef WBTEXT
++static int wl_android_wbtext(struct net_device *dev, char *command, int total_len)
++{
++	int error = BCME_OK, argc = 0;
++	int data, bytes_written;
++	int roam_trigger[2];
++	dhd_pub_t *dhdp = wl_cfg80211_get_dhdp(dev);
++
++	argc = sscanf(command+sizeof(CMD_WBTEXT_ENABLE), "%d", &data);
++	if (!argc) {
++		error = wldev_iovar_getint(dev, "wnm_bsstrans_resp", &data);
++		if (error) {
++			ANDROID_ERROR(("%s: Failed to set wbtext error = %d\n",
++				__FUNCTION__, error));
++			return error;
++		}
++		bytes_written = snprintf(command, total_len, "WBTEXT %s\n",
++				(data == WL_BSSTRANS_POLICY_PRODUCT_WBTEXT)?
++				"ENABLED" : "DISABLED");
++		return bytes_written;
++	} else {
++		if (data) {
++			data = WL_BSSTRANS_POLICY_PRODUCT_WBTEXT;
++		}
++
++		if ((error = wldev_iovar_setint(dev, "wnm_bsstrans_resp", data)) != BCME_OK) {
++			ANDROID_ERROR(("%s: Failed to set wbtext error = %d\n",
++				__FUNCTION__, error));
++			return error;
++		}
++
++		if (data) {
++			/* reset roam_prof when wbtext is on */
++			if ((error = wl_cfg80211_wbtext_set_default(dev)) != BCME_OK) {
++				return error;
++			}
++			dhdp->wbtext_support = TRUE;
++		} else {
++			/* reset legacy roam trigger when wbtext is off */
++			roam_trigger[0] = DEFAULT_ROAM_TRIGGER_VALUE;
++			roam_trigger[1] = WLC_BAND_ALL;
++			if ((error = wldev_ioctl_set(dev, WLC_SET_ROAM_TRIGGER, roam_trigger,
++					sizeof(roam_trigger))) != BCME_OK) {
++				ANDROID_ERROR(("%s: Failed to reset roam trigger = %d\n",
++					__FUNCTION__, error));
++				return error;
++			}
++			dhdp->wbtext_support = FALSE;
++		}
++	}
++	return error;
++}
++
++static int wl_cfg80211_wbtext_btm_timer_threshold(struct net_device *dev,
++	char *command, int total_len)
++{
++	int error = BCME_OK, argc = 0;
++	int data, bytes_written;
++
++	argc = sscanf(command, CMD_WBTEXT_BTM_TIMER_THRESHOLD " %d\n", &data);
++	if (!argc) {
++		error = wldev_iovar_getint(dev, "wnm_bsstrans_timer_threshold", &data);
++		if (error) {
++			ANDROID_ERROR(("Failed to get wnm_bsstrans_timer_threshold (%d)\n", error));
++			return error;
++		}
++		bytes_written = snprintf(command, total_len, "%d\n", data);
++		return bytes_written;
++	} else {
++		if ((error = wldev_iovar_setint(dev, "wnm_bsstrans_timer_threshold",
++				data)) != BCME_OK) {
++			ANDROID_ERROR(("Failed to set wnm_bsstrans_timer_threshold (%d)\n", error));
++			return error;
++		}
++	}
++	return error;
++}
++
++static int wl_cfg80211_wbtext_btm_delta(struct net_device *dev,
++	char *command, int total_len)
++{
++	int error = BCME_OK, argc = 0;
++	int data = 0, bytes_written;
++
++	argc = sscanf(command, CMD_WBTEXT_BTM_DELTA " %d\n", &data);
++	if (!argc) {
++		error = wldev_iovar_getint(dev, "wnm_btmdelta", &data);
++		if (error) {
++			ANDROID_ERROR(("Failed to get wnm_btmdelta (%d)\n", error));
++			return error;
++		}
++		bytes_written = snprintf(command, total_len, "%d\n", data);
++		return bytes_written;
++	} else {
++		if ((error = wldev_iovar_setint(dev, "wnm_btmdelta",
++				data)) != BCME_OK) {
++			ANDROID_ERROR(("Failed to set wnm_btmdelta (%d)\n", error));
++			return error;
++		}
++	}
++	return error;
++}
++
++#endif /* WBTEXT */
++
++#ifdef PNO_SUPPORT
++#define PNO_PARAM_SIZE 50
++#define VALUE_SIZE 50
++#define LIMIT_STR_FMT  ("%50s %50s")
++
++static int
++wls_parse_batching_cmd(struct net_device *dev, char *command, int total_len)
++{
++	int err = BCME_OK;
++	uint i, tokens;
++	char *pos, *pos2, *token, *token2, *delim;
++	char param[PNO_PARAM_SIZE+1], value[VALUE_SIZE+1];
++	struct dhd_pno_batch_params batch_params;
++
++	ANDROID_INFO(("%s: command=%s, len=%d\n", __FUNCTION__, command, total_len));
++	if (total_len < strlen(CMD_WLS_BATCHING)) {
++		ANDROID_ERROR(("%s argument=%d less min size\n", __FUNCTION__, total_len));
++		err = BCME_ERROR;
++		goto exit;
++	}
++	pos = command + strlen(CMD_WLS_BATCHING) + 1;
++	memset(&batch_params, 0, sizeof(struct dhd_pno_batch_params));
++
++	if (!strncmp(pos, PNO_BATCHING_SET, strlen(PNO_BATCHING_SET))) {
++		pos += strlen(PNO_BATCHING_SET) + 1;
++		while ((token = strsep(&pos, PNO_PARAMS_DELIMETER)) != NULL) {
++			memset(param, 0, sizeof(param));
++			memset(value, 0, sizeof(value));
++			if (token == NULL || !*token)
++				break;
++			if (*token == '\0')
++				continue;
++			delim = strchr(token, PNO_PARAM_VALUE_DELLIMETER);
++			if (delim != NULL)
++				*delim = ' ';
++
++			tokens = sscanf(token, LIMIT_STR_FMT, param, value);
++			if (!strncmp(param, PNO_PARAM_SCANFREQ, strlen(PNO_PARAM_SCANFREQ))) {
++				batch_params.scan_fr = simple_strtol(value, NULL, 0);
++				ANDROID_INFO(("scan_freq : %d\n", batch_params.scan_fr));
++			} else if (!strncmp(param, PNO_PARAM_BESTN, strlen(PNO_PARAM_BESTN))) {
++				batch_params.bestn = simple_strtol(value, NULL, 0);
++				ANDROID_INFO(("bestn : %d\n", batch_params.bestn));
++			} else if (!strncmp(param, PNO_PARAM_MSCAN, strlen(PNO_PARAM_MSCAN))) {
++				batch_params.mscan = simple_strtol(value, NULL, 0);
++				ANDROID_INFO(("mscan : %d\n", batch_params.mscan));
++			} else if (!strncmp(param, PNO_PARAM_CHANNEL, strlen(PNO_PARAM_CHANNEL))) {
++				i = 0;
++				pos2 = value;
++				tokens = sscanf(value, "<%s>", value);
++				if (tokens != 1) {
++					err = BCME_ERROR;
++					ANDROID_ERROR(("%s : invalid format for channel"
++					" <> params\n", __FUNCTION__));
++					goto exit;
++				}
++				while ((token2 = strsep(&pos2,
++						PNO_PARAM_CHANNEL_DELIMETER)) != NULL) {
++					if (token2 == NULL || !*token2)
++						break;
++					if (*token2 == '\0')
++						continue;
++					if (*token2 == 'A' || *token2 == 'B') {
++						batch_params.band = (*token2 == 'A')?
++							WLC_BAND_5G : WLC_BAND_2G;
++						ANDROID_INFO(("band : %s\n",
++							(*token2 == 'A')? "A" : "B"));
++					} else {
++						if ((batch_params.nchan >= WL_NUMCHANNELS) ||
++							(i >= WL_NUMCHANNELS)) {
++							ANDROID_ERROR(("Too many nchan %d\n",
++								batch_params.nchan));
++							err = BCME_BUFTOOSHORT;
++							goto exit;
++						}
++						batch_params.chan_list[i++] =
++							simple_strtol(token2, NULL, 0);
++						batch_params.nchan++;
++						ANDROID_INFO(("channel :%d\n",
++							batch_params.chan_list[i-1]));
++					}
++				 }
++			} else if (!strncmp(param, PNO_PARAM_RTT, strlen(PNO_PARAM_RTT))) {
++				batch_params.rtt = simple_strtol(value, NULL, 0);
++				ANDROID_INFO(("rtt : %d\n", batch_params.rtt));
++			} else {
++				ANDROID_ERROR(("%s : unknown param: %s\n", __FUNCTION__, param));
++				err = BCME_ERROR;
++				goto exit;
++			}
++		}
++		err = dhd_dev_pno_set_for_batch(dev, &batch_params);
++		if (err < 0) {
++			ANDROID_ERROR(("failed to configure batch scan\n"));
++		} else {
++			memset(command, 0, total_len);
++			err = snprintf(command, total_len, "%d", err);
++		}
++	} else if (!strncmp(pos, PNO_BATCHING_GET, strlen(PNO_BATCHING_GET))) {
++		err = dhd_dev_pno_get_for_batch(dev, command, total_len);
++		if (err < 0) {
++			ANDROID_ERROR(("failed to getting batching results\n"));
++		} else {
++			err = strlen(command);
++		}
++	} else if (!strncmp(pos, PNO_BATCHING_STOP, strlen(PNO_BATCHING_STOP))) {
++		err = dhd_dev_pno_stop_for_batch(dev);
++		if (err < 0) {
++			ANDROID_ERROR(("failed to stop batching scan\n"));
++		} else {
++			memset(command, 0, total_len);
++			err = snprintf(command, total_len, "OK");
++		}
++	} else {
++		ANDROID_ERROR(("%s : unknown command\n", __FUNCTION__));
++		err = BCME_ERROR;
++		goto exit;
++	}
++exit:
++	return err;
++}
++
++#ifndef WL_SCHED_SCAN
++static int wl_android_set_pno_setup(struct net_device *dev, char *command, int total_len)
++{
++	wlc_ssid_ext_t ssids_local[MAX_PFN_LIST_COUNT];
++	int res = -1;
++	int nssid = 0;
++	cmd_tlv_t *cmd_tlv_temp;
++	char *str_ptr;
++	int tlv_size_left;
++	int pno_time = 0;
++	int pno_repeat = 0;
++	int pno_freq_expo_max = 0;
++
++#ifdef PNO_SET_DEBUG
++	int i;
++	char pno_in_example[] = {
++		'P', 'N', 'O', 'S', 'E', 'T', 'U', 'P', ' ',
++		'S', '1', '2', '0',
++		'S',
++		0x05,
++		'd', 'l', 'i', 'n', 'k',
++		'S',
++		0x04,
++		'G', 'O', 'O', 'G',
++		'T',
++		'0', 'B',
++		'R',
++		'2',
++		'M',
++		'2',
++		0x00
++		};
++#endif /* PNO_SET_DEBUG */
++	ANDROID_INFO(("%s: command=%s, len=%d\n", __FUNCTION__, command, total_len));
++
++	if (total_len < (strlen(CMD_PNOSETUP_SET) + sizeof(cmd_tlv_t))) {
++		ANDROID_ERROR(("%s argument=%d less min size\n", __FUNCTION__, total_len));
++		goto exit_proc;
++	}
++#ifdef PNO_SET_DEBUG
++	memcpy(command, pno_in_example, sizeof(pno_in_example));
++	total_len = sizeof(pno_in_example);
++#endif
++	str_ptr = command + strlen(CMD_PNOSETUP_SET);
++	tlv_size_left = total_len - strlen(CMD_PNOSETUP_SET);
++
++	cmd_tlv_temp = (cmd_tlv_t *)str_ptr;
++	memset(ssids_local, 0, sizeof(ssids_local));
++
++	if ((cmd_tlv_temp->prefix == PNO_TLV_PREFIX) &&
++		(cmd_tlv_temp->version == PNO_TLV_VERSION) &&
++		(cmd_tlv_temp->subtype == PNO_TLV_SUBTYPE_LEGACY_PNO)) {
++
++		str_ptr += sizeof(cmd_tlv_t);
++		tlv_size_left -= sizeof(cmd_tlv_t);
++
++		if ((nssid = wl_parse_ssid_list_tlv(&str_ptr, ssids_local,
++			MAX_PFN_LIST_COUNT, &tlv_size_left)) <= 0) {
++			ANDROID_ERROR(("SSID is not presented or corrupted ret=%d\n", nssid));
++			goto exit_proc;
++		} else {
++			if ((str_ptr[0] != PNO_TLV_TYPE_TIME) || (tlv_size_left <= 1)) {
++				ANDROID_ERROR(("%s scan duration corrupted field size %d\n",
++					__FUNCTION__, tlv_size_left));
++				goto exit_proc;
++			}
++			str_ptr++;
++			pno_time = simple_strtoul(str_ptr, &str_ptr, 16);
++			ANDROID_INFO(("%s: pno_time=%d\n", __FUNCTION__, pno_time));
++
++			if (str_ptr[0] != 0) {
++				if ((str_ptr[0] != PNO_TLV_FREQ_REPEAT)) {
++					ANDROID_ERROR(("%s pno repeat : corrupted field\n",
++						__FUNCTION__));
++					goto exit_proc;
++				}
++				str_ptr++;
++				pno_repeat = simple_strtoul(str_ptr, &str_ptr, 16);
++				ANDROID_INFO(("%s :got pno_repeat=%d\n", __FUNCTION__, pno_repeat));
++				if (str_ptr[0] != PNO_TLV_FREQ_EXPO_MAX) {
++					ANDROID_ERROR(("%s FREQ_EXPO_MAX corrupted field size\n",
++						__FUNCTION__));
++					goto exit_proc;
++				}
++				str_ptr++;
++				pno_freq_expo_max = simple_strtoul(str_ptr, &str_ptr, 16);
++				ANDROID_INFO(("%s: pno_freq_expo_max=%d\n",
++					__FUNCTION__, pno_freq_expo_max));
++			}
++		}
++	} else {
++		ANDROID_ERROR(("%s get wrong TLV command\n", __FUNCTION__));
++		goto exit_proc;
++	}
++
++	res = dhd_dev_pno_set_for_ssid(dev, ssids_local, nssid, pno_time, pno_repeat,
++		pno_freq_expo_max, NULL, 0);
++exit_proc:
++	return res;
++}
++#endif /* !WL_SCHED_SCAN */
++#endif /* PNO_SUPPORT  */
++
++static int wl_android_get_p2p_dev_addr(struct net_device *ndev, char *command, int total_len)
++{
++	int ret;
++	int bytes_written = 0;
++
++	ret = wl_cfg80211_get_p2p_dev_addr(ndev, (struct ether_addr*)command);
++	if (ret)
++		return 0;
++	bytes_written = sizeof(struct ether_addr);
++	return bytes_written;
++}
++
++
++int
++wl_android_set_ap_mac_list(struct net_device *dev, int macmode, struct maclist *maclist)
++{
++	int i, j, match;
++	int ret	= 0;
++	char mac_buf[MAX_NUM_OF_ASSOCLIST *
++		sizeof(struct ether_addr) + sizeof(uint)] = {0};
++	struct maclist *assoc_maclist = (struct maclist *)mac_buf;
++
++	/* set filtering mode */
++	if ((ret = wldev_ioctl_set(dev, WLC_SET_MACMODE, &macmode, sizeof(macmode)) != 0)) {
++		ANDROID_ERROR(("%s : WLC_SET_MACMODE error=%d\n", __FUNCTION__, ret));
++		return ret;
++	}
++	if (macmode != MACLIST_MODE_DISABLED) {
++		/* set the MAC filter list */
++		if ((ret = wldev_ioctl_set(dev, WLC_SET_MACLIST, maclist,
++			sizeof(int) + sizeof(struct ether_addr) * maclist->count)) != 0) {
++			ANDROID_ERROR(("%s : WLC_SET_MACLIST error=%d\n", __FUNCTION__, ret));
++			return ret;
++		}
++		/* get the current list of associated STAs */
++		assoc_maclist->count = MAX_NUM_OF_ASSOCLIST;
++		if ((ret = wldev_ioctl_get(dev, WLC_GET_ASSOCLIST, assoc_maclist,
++			sizeof(mac_buf))) != 0) {
++			ANDROID_ERROR(("%s : WLC_GET_ASSOCLIST error=%d\n", __FUNCTION__, ret));
++			return ret;
++		}
++		/* do we have any STA associated?  */
++		if (assoc_maclist->count) {
++			/* iterate each associated STA */
++			for (i = 0; i < assoc_maclist->count; i++) {
++				match = 0;
++				/* compare with each entry */
++				for (j = 0; j < maclist->count; j++) {
++					ANDROID_INFO(("%s : associated="MACDBG " list="MACDBG "\n",
++					__FUNCTION__, MAC2STRDBG(assoc_maclist->ea[i].octet),
++					MAC2STRDBG(maclist->ea[j].octet)));
++					if (memcmp(assoc_maclist->ea[i].octet,
++						maclist->ea[j].octet, ETHER_ADDR_LEN) == 0) {
++						match = 1;
++						break;
++					}
++				}
++				/* do conditional deauth */
++				/*   "if not in the allow list" or "if in the deny list" */
++				if ((macmode == MACLIST_MODE_ALLOW && !match) ||
++					(macmode == MACLIST_MODE_DENY && match)) {
++					scb_val_t scbval;
++
++					scbval.val = htod32(1);
++					memcpy(&scbval.ea, &assoc_maclist->ea[i],
++						ETHER_ADDR_LEN);
++					if ((ret = wldev_ioctl_set(dev,
++						WLC_SCB_DEAUTHENTICATE_FOR_REASON,
++						&scbval, sizeof(scb_val_t))) != 0)
++						ANDROID_ERROR(("%s WLC_SCB_DEAUTHENTICATE error=%d\n",
++							__FUNCTION__, ret));
++				}
++			}
++		}
++	}
++	return ret;
++}
++
++/*
++ * HAPD_MAC_FILTER mac_mode mac_cnt mac_addr1 mac_addr2
++ *
++ */
++static int
++wl_android_set_mac_address_filter(struct net_device *dev, char* str)
++{
++	int i;
++	int ret = 0;
++	int macnum = 0;
++	int macmode = MACLIST_MODE_DISABLED;
++	struct maclist *list;
++	char eabuf[ETHER_ADDR_STR_LEN];
++	const char *token;
++
++	/* string should look like below (macmode/macnum/maclist) */
++	/*   1 2 00:11:22:33:44:55 00:11:22:33:44:ff  */
++
++	/* get the MAC filter mode */
++	token = strsep((char**)&str, " ");
++	if (!token) {
++		return -1;
++	}
++	macmode = bcm_atoi(token);
++
++	if (macmode < MACLIST_MODE_DISABLED || macmode > MACLIST_MODE_ALLOW) {
++		ANDROID_ERROR(("%s : invalid macmode %d\n", __FUNCTION__, macmode));
++		return -1;
++	}
++
++	token = strsep((char**)&str, " ");
++	if (!token) {
++		return -1;
++	}
++	macnum = bcm_atoi(token);
++	if (macnum < 0 || macnum > MAX_NUM_MAC_FILT) {
++		ANDROID_ERROR(("%s : invalid number of MAC address entries %d\n",
++			__FUNCTION__, macnum));
++		return -1;
++	}
++	/* allocate memory for the MAC list */
++	list = (struct maclist*)kmalloc(sizeof(int) +
++		sizeof(struct ether_addr) * macnum, GFP_KERNEL);
++	if (!list) {
++		ANDROID_ERROR(("%s : failed to allocate memory\n", __FUNCTION__));
++		return -1;
++	}
++	/* prepare the MAC list */
++	list->count = htod32(macnum);
++	bzero((char *)eabuf, ETHER_ADDR_STR_LEN);
++	for (i = 0; i < list->count; i++) {
++		strncpy(eabuf, strsep((char**)&str, " "), ETHER_ADDR_STR_LEN - 1);
++		if (!(ret = bcm_ether_atoe(eabuf, &list->ea[i]))) {
++			ANDROID_ERROR(("%s : mac parsing err index=%d, addr=%s\n",
++				__FUNCTION__, i, eabuf));
++			list->count--;
++			break;
++		}
++		ANDROID_INFO(("%s : %d/%d MACADDR=%s", __FUNCTION__, i, list->count, eabuf));
++	}
++	/* set the list */
++	if ((ret = wl_android_set_ap_mac_list(dev, macmode, list)) != 0)
++		ANDROID_ERROR(("%s : Setting MAC list failed error=%d\n", __FUNCTION__, ret));
++
++	kfree(list);
++
++	return 0;
++}
++
++/**
++ * Global function definitions (declared in wl_android.h)
++ */
++
++int wl_android_wifi_on(struct net_device *dev)
++{
++	int ret = 0;
++	int retry = POWERUP_MAX_RETRY;
++
++	if (!dev) {
++		ANDROID_ERROR(("%s: dev is null\n", __FUNCTION__));
++		return -EINVAL;
++	}
++
++	dhd_net_if_lock(dev);
++	WL_MSG(dev->name, "in g_wifi_on=%d\n", g_wifi_on);
++	if (!g_wifi_on) {
++		do {
++			if (!dhd_net_wifi_platform_set_power(dev, TRUE, WIFI_TURNON_DELAY)) {
++#ifdef BCMSDIO
++			ret = dhd_net_bus_resume(dev, 0);
++#endif /* BCMSDIO */
++			}
++#ifdef BCMPCIE
++			ret = dhd_net_bus_devreset(dev, FALSE);
++#endif /* BCMPCIE */
++			if (ret == 0) {
++				break;
++			}
++			ANDROID_ERROR(("\nfailed to power up wifi chip, retry again (%d left) **\n\n",
++				retry));
++#ifdef BCMPCIE
++			dhd_net_bus_devreset(dev, TRUE);
++#endif /* BCMPCIE */
++			dhd_net_wifi_platform_set_power(dev, FALSE, WIFI_TURNOFF_DELAY);
++		} while (retry-- > 0);
++		if (ret != 0) {
++			ANDROID_ERROR(("\nfailed to power up wifi chip, max retry reached **\n\n"));
++			goto exit;
++		}
++#if defined(BCMSDIO) || defined(BCMDBUS)
++		ret = dhd_net_bus_devreset(dev, FALSE);
++		if (ret)
++			goto err;
++#ifdef BCMSDIO
++		dhd_net_bus_resume(dev, 1);
++#endif /* BCMSDIO */
++#endif /* BCMSDIO || BCMDBUS */
++#if defined(BCMSDIO) || defined(BCMDBUS)
++		if (!ret) {
++			if (dhd_dev_init_ioctl(dev) < 0) {
++				ret = -EFAULT;
++				goto err;
++			}
++		}
++#endif /* BCMSDIO || BCMDBUS */
++		g_wifi_on = TRUE;
++	}
++
++exit:
++	WL_MSG(dev->name, "Success\n");
++	dhd_net_if_unlock(dev);
++	return ret;
++
++#if defined(BCMSDIO) || defined(BCMDBUS)
++err:
++	dhd_net_bus_devreset(dev, TRUE);
++#ifdef BCMSDIO
++	dhd_net_bus_suspend(dev);
++#endif /* BCMSDIO */
++	dhd_net_wifi_platform_set_power(dev, FALSE, WIFI_TURNOFF_DELAY);
++	WL_MSG(dev->name, "Failed\n");
++	dhd_net_if_unlock(dev);
++	return ret;
++#endif /* BCMSDIO || BCMDBUS */
++}
++
++int wl_android_wifi_off(struct net_device *dev, bool on_failure)
++{
++	int ret = 0;
++
++	if (!dev) {
++		ANDROID_ERROR(("%s: dev is null\n", __FUNCTION__));
++		return -EINVAL;
++	}
++
++#if defined(BCMPCIE) && defined(DHD_DEBUG_UART)
++	ret = dhd_debug_uart_is_running(dev);
++	if (ret) {
++		ANDROID_ERROR(("%s - Debug UART App is running\n", __FUNCTION__));
++		return -EBUSY;
++	}
++#endif	/* BCMPCIE && DHD_DEBUG_UART */
++	dhd_net_if_lock(dev);
++	WL_MSG(dev->name, "in g_wifi_on=%d, on_failure=%d\n", g_wifi_on, on_failure);
++	if (g_wifi_on || on_failure) {
++#if defined(BCMSDIO) || defined(BCMPCIE) || defined(BCMDBUS)
++		ret = dhd_net_bus_devreset(dev, TRUE);
++#if  defined(BCMSDIO)
++		dhd_net_bus_suspend(dev);
++#endif /* BCMSDIO */
++#endif /* BCMSDIO || BCMPCIE || BCMDBUS */
++		dhd_net_wifi_platform_set_power(dev, FALSE, WIFI_TURNOFF_DELAY);
++		g_wifi_on = FALSE;
++	}
++	WL_MSG(dev->name, "out\n");
++	dhd_net_if_unlock(dev);
++
++	return ret;
++}
++
++static int wl_android_set_fwpath(struct net_device *net, char *command, int total_len)
++{
++	if ((strlen(command) - strlen(CMD_SETFWPATH)) > MOD_PARAM_PATHLEN)
++		return -1;
++	return dhd_net_set_fw_path(net, command + strlen(CMD_SETFWPATH) + 1);
++}
++
++#ifdef CONNECTION_STATISTICS
++static int
++wl_chanim_stats(struct net_device *dev, u8 *chan_idle)
++{
++	int err;
++	wl_chanim_stats_t *list;
++	/* Parameter _and_ returned buffer of chanim_stats. */
++	wl_chanim_stats_t param;
++	u8 result[WLC_IOCTL_SMLEN];
++	chanim_stats_t *stats;
++
++	memset(&param, 0, sizeof(param));
++
++	param.buflen = htod32(sizeof(wl_chanim_stats_t));
++	param.count = htod32(WL_CHANIM_COUNT_ONE);
++
++	if ((err = wldev_iovar_getbuf(dev, "chanim_stats", (char*)&param, sizeof(wl_chanim_stats_t),
++		(char*)result, sizeof(result), 0)) < 0) {
++		ANDROID_ERROR(("Failed to get chanim results %d \n", err));
++		return err;
++	}
++
++	list = (wl_chanim_stats_t*)result;
++
++	list->buflen = dtoh32(list->buflen);
++	list->version = dtoh32(list->version);
++	list->count = dtoh32(list->count);
++
++	if (list->buflen == 0) {
++		list->version = 0;
++		list->count = 0;
++	} else if (list->version != WL_CHANIM_STATS_VERSION) {
++		ANDROID_ERROR(("Sorry, firmware has wl_chanim_stats version %d "
++			"but driver supports only version %d.\n",
++				list->version, WL_CHANIM_STATS_VERSION));
++		list->buflen = 0;
++		list->count = 0;
++	}
++
++	stats = list->stats;
++	stats->glitchcnt = dtoh32(stats->glitchcnt);
++	stats->badplcp = dtoh32(stats->badplcp);
++	stats->chanspec = dtoh16(stats->chanspec);
++	stats->timestamp = dtoh32(stats->timestamp);
++	stats->chan_idle = dtoh32(stats->chan_idle);
++
++	ANDROID_INFO(("chanspec: 0x%4x glitch: %d badplcp: %d idle: %d timestamp: %d\n",
++		stats->chanspec, stats->glitchcnt, stats->badplcp, stats->chan_idle,
++		stats->timestamp));
++
++	*chan_idle = stats->chan_idle;
++
++	return (err);
++}
++
++static int
++wl_android_get_connection_stats(struct net_device *dev, char *command, int total_len)
++{
++	static char iovar_buf[WLC_IOCTL_MAXLEN];
++	wl_cnt_wlc_t* wlc_cnt = NULL;
++#ifndef DISABLE_IF_COUNTERS
++	wl_if_stats_t* if_stats = NULL;
++#endif /* DISABLE_IF_COUNTERS */
++
++	int link_speed = 0;
++	struct connection_stats *output;
++	unsigned int bufsize = 0;
++	int bytes_written = -1;
++	int ret = 0;
++
++	ANDROID_INFO(("%s: enter Get Connection Stats\n", __FUNCTION__));
++
++	if (total_len <= 0) {
++		ANDROID_ERROR(("%s: invalid buffer size %d\n", __FUNCTION__, total_len));
++		goto error;
++	}
++
++	bufsize = total_len;
++	if (bufsize < sizeof(struct connection_stats)) {
++		ANDROID_ERROR(("%s: not enough buffer size, provided=%u, requires=%zu\n",
++			__FUNCTION__, bufsize,
++			sizeof(struct connection_stats)));
++		goto error;
++	}
++
++	output = (struct connection_stats *)command;
++
++#ifndef DISABLE_IF_COUNTERS
++	if ((if_stats = kmalloc(sizeof(*if_stats), GFP_KERNEL)) == NULL) {
++		ANDROID_ERROR(("%s(%d): kmalloc failed\n", __FUNCTION__, __LINE__));
++		goto error;
++	}
++	memset(if_stats, 0, sizeof(*if_stats));
++
++	ret = wldev_iovar_getbuf(dev, "if_counters", NULL, 0,
++		(char *)if_stats, sizeof(*if_stats), NULL);
++	if (ret) {
++		ANDROID_ERROR(("%s: if_counters not supported ret=%d\n",
++			__FUNCTION__, ret));
++
++		/* In case if_stats IOVAR is not supported, get information from counters. */
++#endif /* DISABLE_IF_COUNTERS */
++		ret = wldev_iovar_getbuf(dev, "counters", NULL, 0,
++			iovar_buf, WLC_IOCTL_MAXLEN, NULL);
++		if (unlikely(ret)) {
++			ANDROID_ERROR(("counters error (%d) - size = %zu\n", ret, sizeof(wl_cnt_wlc_t)));
++			goto error;
++		}
++		ret = wl_cntbuf_to_xtlv_format(NULL, iovar_buf, WL_CNTBUF_MAX_SIZE, 0);
++		if (ret != BCME_OK) {
++			ANDROID_ERROR(("%s wl_cntbuf_to_xtlv_format ERR %d\n",
++			__FUNCTION__, ret));
++			goto error;
++		}
++
++		if (!(wlc_cnt = GET_WLCCNT_FROM_CNTBUF(iovar_buf))) {
++			ANDROID_ERROR(("%s wlc_cnt NULL!\n", __FUNCTION__));
++			goto error;
++		}
++
++		output->txframe   = dtoh32(wlc_cnt->txframe);
++		output->txbyte    = dtoh32(wlc_cnt->txbyte);
++		output->txerror   = dtoh32(wlc_cnt->txerror);
++		output->rxframe   = dtoh32(wlc_cnt->rxframe);
++		output->rxbyte    = dtoh32(wlc_cnt->rxbyte);
++		output->txfail    = dtoh32(wlc_cnt->txfail);
++		output->txretry   = dtoh32(wlc_cnt->txretry);
++		output->txretrie  = dtoh32(wlc_cnt->txretrie);
++		output->txrts     = dtoh32(wlc_cnt->txrts);
++		output->txnocts   = dtoh32(wlc_cnt->txnocts);
++		output->txexptime = dtoh32(wlc_cnt->txexptime);
++#ifndef DISABLE_IF_COUNTERS
++	} else {
++		/* Populate from if_stats. */
++		if (dtoh16(if_stats->version) > WL_IF_STATS_T_VERSION) {
++			ANDROID_ERROR(("%s: incorrect version of wl_if_stats_t, expected=%u got=%u\n",
++				__FUNCTION__,  WL_IF_STATS_T_VERSION, if_stats->version));
++			goto error;
++		}
++
++		output->txframe   = (uint32)dtoh64(if_stats->txframe);
++		output->txbyte    = (uint32)dtoh64(if_stats->txbyte);
++		output->txerror   = (uint32)dtoh64(if_stats->txerror);
++		output->rxframe   = (uint32)dtoh64(if_stats->rxframe);
++		output->rxbyte    = (uint32)dtoh64(if_stats->rxbyte);
++		output->txfail    = (uint32)dtoh64(if_stats->txfail);
++		output->txretry   = (uint32)dtoh64(if_stats->txretry);
++		output->txretrie  = (uint32)dtoh64(if_stats->txretrie);
++		if (dtoh16(if_stats->length) > OFFSETOF(wl_if_stats_t, txexptime)) {
++			output->txexptime = (uint32)dtoh64(if_stats->txexptime);
++			output->txrts     = (uint32)dtoh64(if_stats->txrts);
++			output->txnocts   = (uint32)dtoh64(if_stats->txnocts);
++		} else {
++			output->txexptime = 0;
++			output->txrts     = 0;
++			output->txnocts   = 0;
++		}
++	}
++#endif /* DISABLE_IF_COUNTERS */
++
++	/* link_speed is in kbps */
++	ret = wldev_get_link_speed(dev, &link_speed);
++	if (ret || link_speed < 0) {
++		ANDROID_ERROR(("%s: wldev_get_link_speed() failed, ret=%d, speed=%d\n",
++			__FUNCTION__, ret, link_speed));
++		goto error;
++	}
++
++	output->txrate    = link_speed;
++
++	/* Channel idle ratio. */
++	if (wl_chanim_stats(dev, &(output->chan_idle)) < 0) {
++		output->chan_idle = 0;
++	};
++
++	bytes_written = sizeof(struct connection_stats);
++
++error:
++#ifndef DISABLE_IF_COUNTERS
++	if (if_stats) {
++		kfree(if_stats);
++	}
++#endif /* DISABLE_IF_COUNTERS */
++
++	return bytes_written;
++}
++#endif /* CONNECTION_STATISTICS */
++
++#ifdef WL_NATOE
++static int
++wl_android_process_natoe_cmd(struct net_device *dev, char *command, int total_len)
++{
++	int ret = BCME_ERROR;
++	char *pcmd = command;
++	char *str = NULL;
++	wl_natoe_cmd_info_t cmd_info;
++	const wl_natoe_sub_cmd_t *natoe_cmd = &natoe_cmd_list[0];
++
++	/* skip to cmd name after "natoe" */
++	str = bcmstrtok(&pcmd, " ", NULL);
++
++	/* If natoe subcmd name is not provided, return error */
++	if (*pcmd == '\0') {
++		ANDROID_ERROR(("natoe subcmd not provided %s\n", __FUNCTION__));
++		ret = -EINVAL;
++		return ret;
++	}
++
++	/* get the natoe command name to str */
++	str = bcmstrtok(&pcmd, " ", NULL);
++
++	while (natoe_cmd->name != NULL) {
++		if (strcmp(natoe_cmd->name, str) == 0)  {
++			/* dispacth cmd to appropriate handler */
++			if (natoe_cmd->handler) {
++				cmd_info.command = command;
++				cmd_info.tot_len = total_len;
++				ret = natoe_cmd->handler(dev, natoe_cmd, pcmd, &cmd_info);
++			}
++			return ret;
++		}
++		natoe_cmd++;
++	}
++	return ret;
++}
++
++static int
++wlu_natoe_set_vars_cbfn(void *ctx, uint8 *data, uint16 type, uint16 len)
++{
++	int res = BCME_OK;
++	wl_natoe_cmd_info_t *cmd_info = (wl_natoe_cmd_info_t *)ctx;
++	uint8 *command = cmd_info->command;
++	uint16 total_len = cmd_info->tot_len;
++	uint16 bytes_written = 0;
++
++	UNUSED_PARAMETER(len);
++
++	switch (type) {
++
++	case WL_NATOE_XTLV_ENABLE:
++	{
++		bytes_written = snprintf(command, total_len, "natoe: %s\n",
++				*data?"enabled":"disabled");
++		cmd_info->bytes_written = bytes_written;
++		break;
++	}
++
++	case WL_NATOE_XTLV_CONFIG_IPS:
++	{
++		wl_natoe_config_ips_t *config_ips;
++		uint8 buf[16];
++
++		config_ips = (wl_natoe_config_ips_t *)data;
++		bcm_ip_ntoa((struct ipv4_addr *)&config_ips->sta_ip, buf);
++		bytes_written = snprintf(command, total_len, "sta ip: %s\n", buf);
++		bcm_ip_ntoa((struct ipv4_addr *)&config_ips->sta_netmask, buf);
++		bytes_written += snprintf(command + bytes_written, total_len,
++				"sta netmask: %s\n", buf);
++		bcm_ip_ntoa((struct ipv4_addr *)&config_ips->sta_router_ip, buf);
++		bytes_written += snprintf(command + bytes_written, total_len,
++				"sta router ip: %s\n", buf);
++		bcm_ip_ntoa((struct ipv4_addr *)&config_ips->sta_dnsip, buf);
++		bytes_written += snprintf(command + bytes_written, total_len,
++				"sta dns ip: %s\n", buf);
++		bcm_ip_ntoa((struct ipv4_addr *)&config_ips->ap_ip, buf);
++		bytes_written += snprintf(command + bytes_written, total_len,
++				"ap ip: %s\n", buf);
++		bcm_ip_ntoa((struct ipv4_addr *)&config_ips->ap_netmask, buf);
++		bytes_written += snprintf(command + bytes_written, total_len,
++				"ap netmask: %s\n", buf);
++		cmd_info->bytes_written = bytes_written;
++		break;
++	}
++
++	case WL_NATOE_XTLV_CONFIG_PORTS:
++	{
++		wl_natoe_ports_config_t *ports_config;
++
++		ports_config = (wl_natoe_ports_config_t *)data;
++		bytes_written = snprintf(command, total_len, "starting port num: %d\n",
++				dtoh16(ports_config->start_port_num));
++		bytes_written += snprintf(command + bytes_written, total_len,
++				"number of ports: %d\n", dtoh16(ports_config->no_of_ports));
++		cmd_info->bytes_written = bytes_written;
++		break;
++	}
++
++	case WL_NATOE_XTLV_DBG_STATS:
++	{
++		char *stats_dump = (char *)data;
++
++		bytes_written = snprintf(command, total_len, "%s\n", stats_dump);
++		cmd_info->bytes_written = bytes_written;
++		break;
++	}
++
++	case WL_NATOE_XTLV_TBL_CNT:
++	{
++		bytes_written = snprintf(command, total_len, "natoe max tbl entries: %d\n",
++				dtoh32(*(uint32 *)data));
++		cmd_info->bytes_written = bytes_written;
++		break;
++	}
++
++	default:
++		/* ignore */
++		break;
++	}
++
++	return res;
++}
++
++/*
++ *   --- common for all natoe get commands ----
++ */
++static int
++wl_natoe_get_ioctl(struct net_device *dev, wl_natoe_ioc_t *natoe_ioc,
++		uint16 iocsz, uint8 *buf, uint16 buflen, wl_natoe_cmd_info_t *cmd_info)
++{
++	/* for gets we only need to pass ioc header */
++	wl_natoe_ioc_t *iocresp = (wl_natoe_ioc_t *)buf;
++	int res;
++
++	/*  send getbuf natoe iovar */
++	res = wldev_iovar_getbuf(dev, "natoe", natoe_ioc, iocsz, buf,
++			buflen, NULL);
++
++	/*  check the response buff  */
++	if ((res == BCME_OK)) {
++		/* scans ioctl tlvbuf f& invokes the cbfn for processing  */
++		res = bcm_unpack_xtlv_buf(cmd_info, iocresp->data, iocresp->len,
++				BCM_XTLV_OPTION_ALIGN32, wlu_natoe_set_vars_cbfn);
++
++		if (res == BCME_OK) {
++			res = cmd_info->bytes_written;
++		}
++	}
++	else
++	{
++		ANDROID_ERROR(("%s: get command failed code %d\n", __FUNCTION__, res));
++		res = BCME_ERROR;
++	}
++
++	return res;
++}
++
++static int
++wl_android_natoe_subcmd_enable(struct net_device *dev, const wl_natoe_sub_cmd_t *cmd,
++		char *command, wl_natoe_cmd_info_t *cmd_info)
++{
++	int ret = BCME_OK;
++	wl_natoe_ioc_t *natoe_ioc;
++	char *pcmd = command;
++	uint16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	uint16 iocsz = sizeof(*natoe_ioc) + WL_NATOE_IOC_BUFSZ;
++	uint16 buflen = WL_NATOE_IOC_BUFSZ;
++	bcm_xtlv_t *pxtlv = NULL;
++	char *ioctl_buf = NULL;
++
++	ioctl_buf = kzalloc(WLC_IOCTL_MEDLEN, kflags);
++	if (!ioctl_buf) {
++		ANDROID_ERROR(("ioctl memory alloc failed\n"));
++		return -ENOMEM;
++	}
++
++	/* alloc mem for ioctl headr + tlv data */
++	natoe_ioc = kzalloc(iocsz, kflags);
++	if (!natoe_ioc) {
++		ANDROID_ERROR(("ioctl header memory alloc failed\n"));
++		kfree(ioctl_buf);
++		return -ENOMEM;
++	}
++
++	/* make up natoe cmd ioctl header */
++	natoe_ioc->version = htod16(WL_NATOE_IOCTL_VERSION);
++	natoe_ioc->id = htod16(cmd->id);
++	natoe_ioc->len = htod16(WL_NATOE_IOC_BUFSZ);
++	pxtlv = (bcm_xtlv_t *)natoe_ioc->data;
++
++	if(*pcmd == WL_IOCTL_ACTION_GET) { /* get */
++		iocsz = sizeof(*natoe_ioc) + sizeof(*pxtlv);
++		ret = wl_natoe_get_ioctl(dev, natoe_ioc, iocsz, ioctl_buf,
++				WLC_IOCTL_MEDLEN, cmd_info);
++		if (ret != BCME_OK) {
++			ANDROID_ERROR(("Fail to get iovar %s\n", __FUNCTION__));
++			ret = -EINVAL;
++		}
++	} else {	/* set */
++		uint8 val = bcm_atoi(pcmd);
++
++		/* buflen is max tlv data we can write, it will be decremented as we pack */
++		/* save buflen at start */
++		uint16 buflen_at_start = buflen;
++
++		/* we'll adjust final ioc size at the end */
++		ret = bcm_pack_xtlv_entry((uint8**)&pxtlv, &buflen, WL_NATOE_XTLV_ENABLE,
++			sizeof(uint8), &val, BCM_XTLV_OPTION_ALIGN32);
++
++		if (ret != BCME_OK) {
++			ret = -EINVAL;
++			goto exit;
++		}
++
++		/* adjust iocsz to the end of last data record */
++		natoe_ioc->len = (buflen_at_start - buflen);
++		iocsz = sizeof(*natoe_ioc) + natoe_ioc->len;
++
++		ret = wldev_iovar_setbuf(dev, "natoe",
++				natoe_ioc, iocsz, ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++		if (ret != BCME_OK) {
++			ANDROID_ERROR(("Fail to set iovar %d\n", ret));
++			ret = -EINVAL;
++		}
++	}
++
++exit:
++	kfree(ioctl_buf);
++	kfree(natoe_ioc);
++
++	return ret;
++}
++
++static int
++wl_android_natoe_subcmd_config_ips(struct net_device *dev,
++		const wl_natoe_sub_cmd_t *cmd, char *command, wl_natoe_cmd_info_t *cmd_info)
++{
++	int ret = BCME_OK;
++	wl_natoe_config_ips_t config_ips;
++	wl_natoe_ioc_t *natoe_ioc;
++	char *pcmd = command;
++	char *str;
++	uint16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	uint16 iocsz = sizeof(*natoe_ioc) + WL_NATOE_IOC_BUFSZ;
++	uint16 buflen = WL_NATOE_IOC_BUFSZ;
++	bcm_xtlv_t *pxtlv = NULL;
++	char *ioctl_buf = NULL;
++
++	ioctl_buf = kzalloc(WLC_IOCTL_MEDLEN, kflags);
++	if (!ioctl_buf) {
++		ANDROID_ERROR(("ioctl memory alloc failed\n"));
++		return -ENOMEM;
++	}
++
++	/* alloc mem for ioctl headr + tlv data */
++	natoe_ioc = kzalloc(iocsz, kflags);
++	if (!natoe_ioc) {
++		ANDROID_ERROR(("ioctl header memory alloc failed\n"));
++		kfree(ioctl_buf);
++		return -ENOMEM;
++	}
++
++	/* make up natoe cmd ioctl header */
++	natoe_ioc->version = htod16(WL_NATOE_IOCTL_VERSION);
++	natoe_ioc->id = htod16(cmd->id);
++	natoe_ioc->len = htod16(WL_NATOE_IOC_BUFSZ);
++	pxtlv = (bcm_xtlv_t *)natoe_ioc->data;
++
++	if(*pcmd == WL_IOCTL_ACTION_GET) { /* get */
++		iocsz = sizeof(*natoe_ioc) + sizeof(*pxtlv);
++		ret = wl_natoe_get_ioctl(dev, natoe_ioc, iocsz, ioctl_buf,
++				WLC_IOCTL_MEDLEN, cmd_info);
++		if (ret != BCME_OK) {
++			ANDROID_ERROR(("Fail to get iovar %s\n", __FUNCTION__));
++			ret = -EINVAL;
++		}
++	} else {	/* set */
++		/* buflen is max tlv data we can write, it will be decremented as we pack */
++		/* save buflen at start */
++		uint16 buflen_at_start = buflen;
++
++		memset(&config_ips, 0, sizeof(config_ips));
++
++		str = bcmstrtok(&pcmd, " ", NULL);
++		if (!str || !bcm_atoipv4(str, (struct ipv4_addr *)&config_ips.sta_ip)) {
++			ANDROID_ERROR(("Invalid STA IP addr %s\n", str));
++			ret = -EINVAL;
++			goto exit;
++		}
++
++		str = bcmstrtok(&pcmd, " ", NULL);
++		if (!str || !bcm_atoipv4(str, (struct ipv4_addr *)&config_ips.sta_netmask)) {
++			ANDROID_ERROR(("Invalid STA netmask %s\n", str));
++			ret = -EINVAL;
++			goto exit;
++		}
++
++		str = bcmstrtok(&pcmd, " ", NULL);
++		if (!str || !bcm_atoipv4(str, (struct ipv4_addr *)&config_ips.sta_router_ip)) {
++			ANDROID_ERROR(("Invalid STA router IP addr %s\n", str));
++			ret = -EINVAL;
++			goto exit;
++		}
++
++		str = bcmstrtok(&pcmd, " ", NULL);
++		if (!str || !bcm_atoipv4(str, (struct ipv4_addr *)&config_ips.sta_dnsip)) {
++			ANDROID_ERROR(("Invalid STA DNS IP addr %s\n", str));
++			ret = -EINVAL;
++			goto exit;
++		}
++
++		str = bcmstrtok(&pcmd, " ", NULL);
++		if (!str || !bcm_atoipv4(str, (struct ipv4_addr *)&config_ips.ap_ip)) {
++			ANDROID_ERROR(("Invalid AP IP addr %s\n", str));
++			ret = -EINVAL;
++			goto exit;
++		}
++
++		str = bcmstrtok(&pcmd, " ", NULL);
++		if (!str || !bcm_atoipv4(str, (struct ipv4_addr *)&config_ips.ap_netmask)) {
++			ANDROID_ERROR(("Invalid AP netmask %s\n", str));
++			ret = -EINVAL;
++			goto exit;
++		}
++
++		ret = bcm_pack_xtlv_entry((uint8**)&pxtlv,
++				&buflen, WL_NATOE_XTLV_CONFIG_IPS, sizeof(config_ips),
++				&config_ips, BCM_XTLV_OPTION_ALIGN32);
++
++		if (ret != BCME_OK) {
++			ret = -EINVAL;
++			goto exit;
++		}
++
++		/* adjust iocsz to the end of last data record */
++		natoe_ioc->len = (buflen_at_start - buflen);
++		iocsz = sizeof(*natoe_ioc) + natoe_ioc->len;
++
++		ret = wldev_iovar_setbuf(dev, "natoe",
++				natoe_ioc, iocsz, ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++		if (ret != BCME_OK) {
++			ANDROID_ERROR(("Fail to set iovar %d\n", ret));
++			ret = -EINVAL;
++		}
++	}
++
++exit:
++	kfree(ioctl_buf);
++	kfree(natoe_ioc);
++
++	return ret;
++}
++
++static int
++wl_android_natoe_subcmd_config_ports(struct net_device *dev,
++		const wl_natoe_sub_cmd_t *cmd, char *command, wl_natoe_cmd_info_t *cmd_info)
++{
++	int ret = BCME_OK;
++	wl_natoe_ports_config_t ports_config;
++	wl_natoe_ioc_t *natoe_ioc;
++	char *pcmd = command;
++	char *str;
++	uint16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	uint16 iocsz = sizeof(*natoe_ioc) + WL_NATOE_IOC_BUFSZ;
++	uint16 buflen = WL_NATOE_IOC_BUFSZ;
++	bcm_xtlv_t *pxtlv = NULL;
++	char *ioctl_buf = NULL;
++
++	ioctl_buf = kzalloc(WLC_IOCTL_MEDLEN, kflags);
++	if (!ioctl_buf) {
++		ANDROID_ERROR(("ioctl memory alloc failed\n"));
++		return -ENOMEM;
++	}
++
++	/* alloc mem for ioctl headr + tlv data */
++	natoe_ioc = kzalloc(iocsz, kflags);
++	if (!natoe_ioc) {
++		ANDROID_ERROR(("ioctl header memory alloc failed\n"));
++		kfree(ioctl_buf);
++		return -ENOMEM;
++	}
++
++	/* make up natoe cmd ioctl header */
++	natoe_ioc->version = htod16(WL_NATOE_IOCTL_VERSION);
++	natoe_ioc->id = htod16(cmd->id);
++	natoe_ioc->len = htod16(WL_NATOE_IOC_BUFSZ);
++	pxtlv = (bcm_xtlv_t *)natoe_ioc->data;
++
++	if(*pcmd == WL_IOCTL_ACTION_GET) { /* get */
++		iocsz = sizeof(*natoe_ioc) + sizeof(*pxtlv);
++		ret = wl_natoe_get_ioctl(dev, natoe_ioc, iocsz, ioctl_buf,
++				WLC_IOCTL_MEDLEN, cmd_info);
++		if (ret != BCME_OK) {
++			ANDROID_ERROR(("Fail to get iovar %s\n", __FUNCTION__));
++			ret = -EINVAL;
++		}
++	} else {	/* set */
++		/* buflen is max tlv data we can write, it will be decremented as we pack */
++		/* save buflen at start */
++		uint16 buflen_at_start = buflen;
++
++		memset(&ports_config, 0, sizeof(ports_config));
++
++		str = bcmstrtok(&pcmd, " ", NULL);
++		if (!str) {
++			ANDROID_ERROR(("Invalid port string %s\n", str));
++			ret = -EINVAL;
++			goto exit;
++		}
++		ports_config.start_port_num = htod16(bcm_atoi(str));
++
++		str = bcmstrtok(&pcmd, " ", NULL);
++		if (!str) {
++			ANDROID_ERROR(("Invalid port string %s\n", str));
++			ret = -EINVAL;
++			goto exit;
++		}
++		ports_config.no_of_ports = htod16(bcm_atoi(str));
++
++		if ((uint32)(ports_config.start_port_num + ports_config.no_of_ports) >
++				NATOE_MAX_PORT_NUM) {
++			ANDROID_ERROR(("Invalid port configuration\n"));
++			ret = -EINVAL;
++			goto exit;
++		}
++		ret = bcm_pack_xtlv_entry((uint8**)&pxtlv,
++				&buflen, WL_NATOE_XTLV_CONFIG_PORTS, sizeof(ports_config),
++				&ports_config, BCM_XTLV_OPTION_ALIGN32);
++
++		if (ret != BCME_OK) {
++			ret = -EINVAL;
++			goto exit;
++		}
++
++		/* adjust iocsz to the end of last data record */
++		natoe_ioc->len = (buflen_at_start - buflen);
++		iocsz = sizeof(*natoe_ioc) + natoe_ioc->len;
++
++		ret = wldev_iovar_setbuf(dev, "natoe",
++				natoe_ioc, iocsz, ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++		if (ret != BCME_OK) {
++			ANDROID_ERROR(("Fail to set iovar %d\n", ret));
++			ret = -EINVAL;
++		}
++	}
++
++exit:
++	kfree(ioctl_buf);
++	kfree(natoe_ioc);
++
++	return ret;
++}
++
++static int
++wl_android_natoe_subcmd_dbg_stats(struct net_device *dev, const wl_natoe_sub_cmd_t *cmd,
++		char *command, wl_natoe_cmd_info_t *cmd_info)
++{
++	int ret = BCME_OK;
++	wl_natoe_ioc_t *natoe_ioc;
++	char *pcmd = command;
++	uint16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	uint16 iocsz = sizeof(*natoe_ioc) + WL_NATOE_DBG_STATS_BUFSZ;
++	uint16 buflen = WL_NATOE_DBG_STATS_BUFSZ;
++	bcm_xtlv_t *pxtlv = NULL;
++	char *ioctl_buf = NULL;
++
++	ioctl_buf = kzalloc(WLC_IOCTL_MAXLEN, kflags);
++	if (!ioctl_buf) {
++		ANDROID_ERROR(("ioctl memory alloc failed\n"));
++		return -ENOMEM;
++	}
++
++	/* alloc mem for ioctl headr + tlv data */
++	natoe_ioc = kzalloc(iocsz, kflags);
++	if (!natoe_ioc) {
++		ANDROID_ERROR(("ioctl header memory alloc failed\n"));
++		kfree(ioctl_buf);
++		return -ENOMEM;
++	}
++
++	/* make up natoe cmd ioctl header */
++	natoe_ioc->version = htod16(WL_NATOE_IOCTL_VERSION);
++	natoe_ioc->id = htod16(cmd->id);
++	natoe_ioc->len = htod16(WL_NATOE_DBG_STATS_BUFSZ);
++	pxtlv = (bcm_xtlv_t *)natoe_ioc->data;
++
++	if(*pcmd == WL_IOCTL_ACTION_GET) { /* get */
++		iocsz = sizeof(*natoe_ioc) + sizeof(*pxtlv);
++		ret = wl_natoe_get_ioctl(dev, natoe_ioc, iocsz, ioctl_buf,
++				WLC_IOCTL_MAXLEN, cmd_info);
++		if (ret != BCME_OK) {
++			ANDROID_ERROR(("Fail to get iovar %s\n", __FUNCTION__));
++			ret = -EINVAL;
++		}
++	} else {	/* set */
++		uint8 val = bcm_atoi(pcmd);
++
++		/* buflen is max tlv data we can write, it will be decremented as we pack */
++		/* save buflen at start */
++		uint16 buflen_at_start = buflen;
++
++		/* we'll adjust final ioc size at the end */
++		ret = bcm_pack_xtlv_entry((uint8**)&pxtlv, &buflen, WL_NATOE_XTLV_ENABLE,
++			sizeof(uint8), &val, BCM_XTLV_OPTION_ALIGN32);
++
++		if (ret != BCME_OK) {
++			ret = -EINVAL;
++			goto exit;
++		}
++
++		/* adjust iocsz to the end of last data record */
++		natoe_ioc->len = (buflen_at_start - buflen);
++		iocsz = sizeof(*natoe_ioc) + natoe_ioc->len;
++
++		ret = wldev_iovar_setbuf(dev, "natoe",
++				natoe_ioc, iocsz, ioctl_buf, WLC_IOCTL_MAXLEN, NULL);
++		if (ret != BCME_OK) {
++			ANDROID_ERROR(("Fail to set iovar %d\n", ret));
++			ret = -EINVAL;
++		}
++	}
++
++exit:
++	kfree(ioctl_buf);
++	kfree(natoe_ioc);
++
++	return ret;
++}
++
++static int
++wl_android_natoe_subcmd_tbl_cnt(struct net_device *dev, const wl_natoe_sub_cmd_t *cmd,
++		char *command, wl_natoe_cmd_info_t *cmd_info)
++{
++	int ret = BCME_OK;
++	wl_natoe_ioc_t *natoe_ioc;
++	char *pcmd = command;
++	uint16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	uint16 iocsz = sizeof(*natoe_ioc) + WL_NATOE_IOC_BUFSZ;
++	uint16 buflen = WL_NATOE_IOC_BUFSZ;
++	bcm_xtlv_t *pxtlv = NULL;
++	char *ioctl_buf = NULL;
++
++	ioctl_buf = kzalloc(WLC_IOCTL_MEDLEN, kflags);
++	if (!ioctl_buf) {
++		ANDROID_ERROR(("ioctl memory alloc failed\n"));
++		return -ENOMEM;
++	}
++
++	/* alloc mem for ioctl headr + tlv data */
++	natoe_ioc = kzalloc(iocsz, kflags);
++	if (!natoe_ioc) {
++		ANDROID_ERROR(("ioctl header memory alloc failed\n"));
++		kfree(ioctl_buf);
++		return -ENOMEM;
++	}
++
++	/* make up natoe cmd ioctl header */
++	natoe_ioc->version = htod16(WL_NATOE_IOCTL_VERSION);
++	natoe_ioc->id = htod16(cmd->id);
++	natoe_ioc->len = htod16(WL_NATOE_IOC_BUFSZ);
++	pxtlv = (bcm_xtlv_t *)natoe_ioc->data;
++
++	if(*pcmd == WL_IOCTL_ACTION_GET) { /* get */
++		iocsz = sizeof(*natoe_ioc) + sizeof(*pxtlv);
++		ret = wl_natoe_get_ioctl(dev, natoe_ioc, iocsz, ioctl_buf,
++				WLC_IOCTL_MEDLEN, cmd_info);
++		if (ret != BCME_OK) {
++			ANDROID_ERROR(("Fail to get iovar %s\n", __FUNCTION__));
++			ret = -EINVAL;
++		}
++	} else {	/* set */
++		uint32 val = bcm_atoi(pcmd);
++
++		/* buflen is max tlv data we can write, it will be decremented as we pack */
++		/* save buflen at start */
++		uint16 buflen_at_start = buflen;
++
++		/* we'll adjust final ioc size at the end */
++		ret = bcm_pack_xtlv_entry((uint8**)&pxtlv, &buflen, WL_NATOE_XTLV_TBL_CNT,
++			sizeof(uint32), &val, BCM_XTLV_OPTION_ALIGN32);
++
++		if (ret != BCME_OK) {
++			ret = -EINVAL;
++			goto exit;
++		}
++
++		/* adjust iocsz to the end of last data record */
++		natoe_ioc->len = (buflen_at_start - buflen);
++		iocsz = sizeof(*natoe_ioc) + natoe_ioc->len;
++
++		ret = wldev_iovar_setbuf(dev, "natoe",
++				natoe_ioc, iocsz, ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++		if (ret != BCME_OK) {
++			ANDROID_ERROR(("Fail to set iovar %d\n", ret));
++			ret = -EINVAL;
++		}
++	}
++
++exit:
++	kfree(ioctl_buf);
++	kfree(natoe_ioc);
++
++	return ret;
++}
++
++#endif /* WL_NATOE */
++
++#ifdef CUSTOMER_HW4_PRIVATE_CMD
++#endif /* CUSTOMER_HW4_PRIVATE_CMD */
++
++#if defined(WL_SUPPORT_AUTO_CHANNEL)
++/* SoftAP feature */
++#define APCS_BAND_2G_LEGACY1	20
++#define APCS_BAND_2G_LEGACY2	0
++#define APCS_BAND_AUTO		"band=auto"
++#define APCS_BAND_2G		"band=2g"
++#define APCS_BAND_5G		"band=5g"
++#define APCS_MAX_2G_CHANNELS	11
++#define APCS_MAX_RETRY		10
++#define APCS_DEFAULT_2G_CH	1
++#define APCS_DEFAULT_5G_CH	149
++
++static int
++wl_android_set_auto_channel(struct net_device *dev, const char* cmd_str,
++	char* command, int total_len)
++{
++	int channel = 0;
++	int chosen = 0;
++	int retry = 0;
++	int ret = 0;
++	int spect = 0;
++	u8 *reqbuf = NULL;
++	uint32 band = WLC_BAND_2G, sta_band = WLC_BAND_2G;
++	uint32 buf_size;
++
++	if (cmd_str) {
++		ANDROID_INFO(("Command: %s len:%d \n", cmd_str, (int)strlen(cmd_str)));
++		if (strnicmp(cmd_str, APCS_BAND_AUTO, strlen(APCS_BAND_AUTO)) == 0) {
++			band = WLC_BAND_AUTO;
++		} else if (strnicmp(cmd_str, APCS_BAND_5G, strlen(APCS_BAND_5G)) == 0) {
++			band = WLC_BAND_5G;
++		} else if (strnicmp(cmd_str, APCS_BAND_2G, strlen(APCS_BAND_2G)) == 0) {
++			band = WLC_BAND_2G;
++		} else {
++			/*
++			 * For backward compatibility: Some platforms used to issue argument 20 or 0
++			 * to enforce the 2G channel selection
++			 */
++			channel = bcm_atoi(cmd_str);
++			if ((channel == APCS_BAND_2G_LEGACY1) ||
++				(channel == APCS_BAND_2G_LEGACY2)) {
++				band = WLC_BAND_2G;
++			} else {
++				ANDROID_ERROR(("Invalid argument\n"));
++				return -EINVAL;
++			}
++		}
++	} else {
++		/* If no argument is provided, default to 2G */
++		ANDROID_ERROR(("No argument given default to 2.4G scan\n"));
++		band = WLC_BAND_2G;
++	}
++	ANDROID_INFO(("HAPD_AUTO_CHANNEL = %d, band=%d \n", channel, band));
++
++	/* If STA is connected, return is STA channel, else ACS can be issued,
++	 * set spect to 0 and proceed with ACS
++	 */
++	channel = wl_cfg80211_get_sta_channel(dev);
++	if (channel) {
++		sta_band = WL_GET_BAND(channel);
++		switch (sta_band) {
++			case (WL_CHANSPEC_BAND_5G): {
++				if (band == WLC_BAND_2G || band == WLC_BAND_AUTO) {
++					channel = APCS_DEFAULT_2G_CH;
++				}
++				break;
++			}
++			case (WL_CHANSPEC_BAND_2G): {
++				if (band == WLC_BAND_5G) {
++					channel = APCS_DEFAULT_5G_CH;
++				}
++				break;
++			}
++			default:
++				/* Intentional fall through to use same sta channel for softap */
++				break;
++		}
++		WL_MSG(dev->name, "band=%d, sta_band=%d, channel=%d\n", band, sta_band, channel);
++		goto done2;
++	}
++
++	channel = wl_ext_autochannel(dev, ACS_FW_BIT|ACS_DRV_BIT, band);
++	if (channel)
++		goto done2;
++	else
++		goto done;
++
++	if ((ret =
++	     wldev_ioctl_get(dev, WLC_GET_SPECT_MANAGMENT, &spect, sizeof(spect))) < 0) {
++		ANDROID_ERROR(("ACS: error getting the spect\n"));
++		goto done;
++	}
++
++	if (spect > 0) {
++		/* If STA is connected, return is STA channel, else ACS can be issued,
++		 * set spect to 0 and proceed with ACS
++		 */
++		channel = wl_cfg80211_get_sta_channel(dev);
++		if (channel) {
++			channel = (channel <= CH_MAX_2G_CHANNEL) ? channel : APCS_DEFAULT_2G_CH;
++			goto done2;
++		}
++
++		if ((ret = wl_cfg80211_set_spect(dev, 0) < 0)) {
++			ANDROID_ERROR(("ACS: error while setting spect\n"));
++			goto done;
++		}
++	}
++
++	reqbuf = kzalloc(CHANSPEC_BUF_SIZE, GFP_KERNEL);
++	if (reqbuf == NULL) {
++		ANDROID_ERROR(("failed to allocate chanspec buffer\n"));
++		return -ENOMEM;
++	}
++
++	if (band == WLC_BAND_AUTO) {
++		ANDROID_INFO(("ACS full channel scan \n"));
++		reqbuf[0] = htod32(0);
++	} else if (band == WLC_BAND_5G) {
++		ANDROID_INFO(("ACS 5G band scan \n"));
++		if ((ret = wl_cfg80211_get_chanspecs_5g(dev, reqbuf, CHANSPEC_BUF_SIZE)) < 0) {
++			ANDROID_ERROR(("ACS 5g chanspec retreival failed! \n"));
++			goto done;
++		}
++	} else if (band == WLC_BAND_2G) {
++		/*
++		 * If channel argument is not provided/ argument 20 is provided,
++		 * Restrict channel to 2GHz, 20MHz BW, No SB
++		 */
++		ANDROID_INFO(("ACS 2G band scan \n"));
++		if ((ret = wl_cfg80211_get_chanspecs_2g(dev, reqbuf, CHANSPEC_BUF_SIZE)) < 0) {
++			ANDROID_ERROR(("ACS 2g chanspec retreival failed! \n"));
++			goto done;
++		}
++	} else {
++		ANDROID_ERROR(("ACS: No band chosen\n"));
++		goto done2;
++	}
++
++	buf_size = (band == WLC_BAND_AUTO) ? sizeof(int) : CHANSPEC_BUF_SIZE;
++	ret = wldev_ioctl_set(dev, WLC_START_CHANNEL_SEL, (void *)reqbuf,
++		buf_size);
++	if (ret < 0) {
++		ANDROID_ERROR(("can't start auto channel scan, err = %d\n", ret));
++		channel = 0;
++		goto done;
++	}
++
++	/* Wait for auto channel selection, max 3000 ms */
++	if ((band == WLC_BAND_2G) || (band == WLC_BAND_5G)) {
++		OSL_SLEEP(500);
++	} else {
++		/*
++		 * Full channel scan at the minimum takes 1.2secs
++		 * even with parallel scan. max wait time: 3500ms
++		 */
++		OSL_SLEEP(1000);
++	}
++
++	retry = APCS_MAX_RETRY;
++	while (retry--) {
++		ret = wldev_ioctl_get(dev, WLC_GET_CHANNEL_SEL, &chosen,
++			sizeof(chosen));
++		if (ret < 0) {
++			chosen = 0;
++		} else {
++			chosen = dtoh32(chosen);
++		}
++
++		if (chosen) {
++			int chosen_band;
++			int apcs_band;
++#ifdef D11AC_IOTYPES
++			if (wl_cfg80211_get_ioctl_version() == 1) {
++				channel = LCHSPEC_CHANNEL((chanspec_t)chosen);
++			} else {
++				channel = CHSPEC_CHANNEL((chanspec_t)chosen);
++			}
++#else
++			channel = CHSPEC_CHANNEL((chanspec_t)chosen);
++#endif /* D11AC_IOTYPES */
++			apcs_band = (band == WLC_BAND_AUTO) ? WLC_BAND_2G : band;
++			chosen_band = (channel <= CH_MAX_2G_CHANNEL) ? WLC_BAND_2G : WLC_BAND_5G;
++			if (apcs_band == chosen_band) {
++				WL_MSG(dev->name, "selected channel = %d\n", channel);
++				break;
++			}
++		}
++		ANDROID_INFO(("%d tried, ret = %d, chosen = 0x%x\n",
++			(APCS_MAX_RETRY - retry), ret, chosen));
++		OSL_SLEEP(250);
++	}
++
++done:
++	if ((retry == 0) || (ret < 0)) {
++		/* On failure, fallback to a default channel */
++		if ((band == WLC_BAND_5G)) {
++			channel = APCS_DEFAULT_5G_CH;
++		} else {
++			channel = APCS_DEFAULT_2G_CH;
++		}
++		ANDROID_ERROR(("ACS failed. Fall back to default channel (%d) \n", channel));
++	}
++done2:
++	if (spect > 0) {
++		if ((ret = wl_cfg80211_set_spect(dev, spect) < 0)) {
++			ANDROID_ERROR(("ACS: error while setting spect\n"));
++		}
++	}
++
++	if (reqbuf) {
++		kfree(reqbuf);
++	}
++
++	if (channel) {
++		snprintf(command, 4, "%d", channel);
++		ANDROID_INFO(("command result is %s \n", command));
++		return strlen(command);
++	} else {
++		return ret;
++	}
++}
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++
++#ifdef CUSTOMER_HW4_PRIVATE_CMD
++
++
++#ifdef SUPPORT_SET_LPC
++static int
++wl_android_set_lpc(struct net_device *dev, const char* string_num)
++{
++	int lpc_enabled, ret;
++	s32 val = 1;
++
++	lpc_enabled = bcm_atoi(string_num);
++	ANDROID_INFO(("%s : HAPD_LPC_ENABLED = %d\n", __FUNCTION__, lpc_enabled));
++
++	ret = wldev_ioctl_set(dev, WLC_DOWN, &val, sizeof(s32));
++	if (ret < 0)
++		ANDROID_ERROR(("WLC_DOWN error %d\n", ret));
++
++	wldev_iovar_setint(dev, "lpc", lpc_enabled);
++
++	ret = wldev_ioctl_set(dev, WLC_UP, &val, sizeof(s32));
++	if (ret < 0)
++		ANDROID_ERROR(("WLC_UP error %d\n", ret));
++
++	return 1;
++}
++#endif /* SUPPORT_SET_LPC */
++
++static int
++wl_android_ch_res_rl(struct net_device *dev, bool change)
++{
++	int error = 0;
++	s32 srl = 7;
++	s32 lrl = 4;
++	printk("%s enter\n", __FUNCTION__);
++	if (change) {
++		srl = 4;
++		lrl = 2;
++	}
++	error = wldev_ioctl_set(dev, WLC_SET_SRL, &srl, sizeof(s32));
++	if (error) {
++		ANDROID_ERROR(("Failed to set SRL, error = %d\n", error));
++	}
++	error = wldev_ioctl_set(dev, WLC_SET_LRL, &lrl, sizeof(s32));
++	if (error) {
++		ANDROID_ERROR(("Failed to set LRL, error = %d\n", error));
++	}
++	return error;
++}
++
++
++#ifdef WL_RELMCAST
++static int
++wl_android_rmc_enable(struct net_device *net, int rmc_enable)
++{
++	int err;
++
++	err = wldev_iovar_setint(net, "rmc_ackreq", rmc_enable);
++	return err;
++}
++
++static int
++wl_android_rmc_set_leader(struct net_device *dev, const char* straddr)
++{
++	int error  = BCME_OK;
++	char smbuf[WLC_IOCTL_SMLEN];
++	wl_rmc_entry_t rmc_entry;
++	ANDROID_INFO(("%s: Set new RMC leader %s\n", __FUNCTION__, straddr));
++
++	memset(&rmc_entry, 0, sizeof(wl_rmc_entry_t));
++	if (!bcm_ether_atoe(straddr, &rmc_entry.addr)) {
++		if (strlen(straddr) == 1 && bcm_atoi(straddr) == 0) {
++			ANDROID_INFO(("%s: Set auto leader selection mode\n", __FUNCTION__));
++			memset(&rmc_entry, 0, sizeof(wl_rmc_entry_t));
++		} else {
++			ANDROID_ERROR(("%s: No valid mac address provided\n",
++				__FUNCTION__));
++			return BCME_ERROR;
++		}
++	}
++
++	error = wldev_iovar_setbuf(dev, "rmc_ar", &rmc_entry, sizeof(wl_rmc_entry_t),
++		smbuf, sizeof(smbuf), NULL);
++
++	if (error != BCME_OK) {
++		ANDROID_ERROR(("%s: Unable to set RMC leader, error = %d\n",
++			__FUNCTION__, error));
++	}
++
++	return error;
++}
++
++static int wl_android_set_rmc_event(struct net_device *dev, char *command, int total_len)
++{
++	int err = 0;
++	int pid = 0;
++
++	if (sscanf(command, CMD_SET_RMC_EVENT " %d", &pid) <= 0) {
++		ANDROID_ERROR(("Failed to get Parameter from : %s\n", command));
++		return -1;
++	}
++
++	/* set pid, and if the event was happened, let's send a notification through netlink */
++	wl_cfg80211_set_rmc_pid(dev, pid);
++
++	ANDROID_TRACE(("RMC pid=%d\n", pid));
++
++	return err;
++}
++#endif /* WL_RELMCAST */
++
++int wl_android_get_singlecore_scan(struct net_device *dev, char *command, int total_len)
++{
++	int error = 0;
++	int bytes_written = 0;
++	int mode = 0;
++
++	error = wldev_iovar_getint(dev, "scan_ps", &mode);
++	if (error) {
++		ANDROID_ERROR(("%s: Failed to get single core scan Mode, error = %d\n",
++			__FUNCTION__, error));
++		return -1;
++	}
++
++	bytes_written = snprintf(command, total_len, "%s %d", CMD_GET_SCSCAN, mode);
++
++	return bytes_written;
++}
++
++int wl_android_set_singlecore_scan(struct net_device *dev, char *command, int total_len)
++{
++	int error = 0;
++	int mode = 0;
++
++	if (sscanf(command, "%*s %d", &mode) != 1) {
++		ANDROID_ERROR(("%s: Failed to get Parameter\n", __FUNCTION__));
++		return -1;
++	}
++
++	error = wldev_iovar_setint(dev, "scan_ps", mode);
++	if (error) {
++		ANDROID_ERROR(("%s[1]: Failed to set Mode %d, error = %d\n",
++		__FUNCTION__, mode, error));
++		return -1;
++	}
++
++	return error;
++}
++#ifdef TEST_TX_POWER_CONTROL
++static int
++wl_android_set_tx_power(struct net_device *dev, const char* string_num)
++{
++	int err = 0;
++	s32 dbm;
++	enum nl80211_tx_power_setting type;
++
++	dbm = bcm_atoi(string_num);
++
++	if (dbm < -1) {
++		ANDROID_ERROR(("%s: dbm is negative...\n", __FUNCTION__));
++		return -EINVAL;
++	}
++
++	if (dbm == -1)
++		type = NL80211_TX_POWER_AUTOMATIC;
++	else
++		type = NL80211_TX_POWER_FIXED;
++
++	err = wl_set_tx_power(dev, type, dbm);
++	if (unlikely(err)) {
++		ANDROID_ERROR(("%s: error (%d)\n", __FUNCTION__, err));
++		return err;
++	}
++
++	return 1;
++}
++
++static int
++wl_android_get_tx_power(struct net_device *dev, char *command, int total_len)
++{
++	int err;
++	int bytes_written;
++	s32 dbm = 0;
++
++	err = wl_get_tx_power(dev, &dbm);
++	if (unlikely(err)) {
++		ANDROID_ERROR(("%s: error (%d)\n", __FUNCTION__, err));
++		return err;
++	}
++
++	bytes_written = snprintf(command, total_len, "%s %d",
++		CMD_TEST_GET_TX_POWER, dbm);
++
++	ANDROID_ERROR(("%s: GET_TX_POWER: dBm=%d\n", __FUNCTION__, dbm));
++
++	return bytes_written;
++}
++#endif /* TEST_TX_POWER_CONTROL */
++
++static int
++wl_android_set_sarlimit_txctrl(struct net_device *dev, const char* string_num)
++{
++	int err = 0;
++	int setval = 0;
++	s32 mode = bcm_atoi(string_num);
++
++	/* '0' means activate sarlimit
++	 * and '-1' means back to normal state (deactivate sarlimit)
++	 */
++	if (mode == 0) {
++		ANDROID_INFO(("%s: SAR limit control activated\n", __FUNCTION__));
++		setval = 1;
++	} else if (mode == -1) {
++		ANDROID_INFO(("%s: SAR limit control deactivated\n", __FUNCTION__));
++		setval = 0;
++	} else {
++		return -EINVAL;
++	}
++
++	err = wldev_iovar_setint(dev, "sar_enable", setval);
++	if (unlikely(err)) {
++		ANDROID_ERROR(("%s: error (%d)\n", __FUNCTION__, err));
++		return err;
++	}
++	return 1;
++}
++#endif /* CUSTOMER_HW4_PRIVATE_CMD */
++
++int wl_android_set_roam_mode(struct net_device *dev, char *command, int total_len)
++{
++	int error = 0;
++	int mode = 0;
++
++	if (sscanf(command, "%*s %d", &mode) != 1) {
++		ANDROID_ERROR(("%s: Failed to get Parameter\n", __FUNCTION__));
++		return -1;
++	}
++
++	error = wldev_iovar_setint(dev, "roam_off", mode);
++	if (error) {
++		ANDROID_ERROR(("%s: Failed to set roaming Mode %d, error = %d\n",
++		__FUNCTION__, mode, error));
++		return -1;
++	}
++	else
++		ANDROID_ERROR(("%s: succeeded to set roaming Mode %d, error = %d\n",
++		__FUNCTION__, mode, error));
++	return 0;
++}
++
++#ifdef WL_CFG80211
++int wl_android_set_ibss_beacon_ouidata(struct net_device *dev, char *command, int total_len)
++{
++	char ie_buf[VNDR_IE_MAX_LEN];
++	char *ioctl_buf = NULL;
++	char hex[] = "XX";
++	char *pcmd = NULL;
++	int ielen = 0, datalen = 0, idx = 0, tot_len = 0;
++	vndr_ie_setbuf_t *vndr_ie = NULL;
++	s32 iecount;
++	uint32 pktflag;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	s32 err = BCME_OK, bssidx;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++
++	/* Check the VSIE (Vendor Specific IE) which was added.
++	 *  If exist then send IOVAR to delete it
++	 */
++	if (wl_cfg80211_ibss_vsie_delete(dev) != BCME_OK) {
++		return -EINVAL;
++	}
++
++	if (total_len < (strlen(CMD_SETIBSSBEACONOUIDATA) + 1)) {
++		ANDROID_ERROR(("error. total_len:%d\n", total_len));
++		return -EINVAL;
++	}
++
++	pcmd = command + strlen(CMD_SETIBSSBEACONOUIDATA) + 1;
++	for (idx = 0; idx < DOT11_OUI_LEN; idx++) {
++		if (*pcmd == '\0') {
++			ANDROID_ERROR(("error while parsing OUI.\n"));
++			return -EINVAL;
++		}
++		hex[0] = *pcmd++;
++		hex[1] = *pcmd++;
++		ie_buf[idx] =  (uint8)simple_strtoul(hex, NULL, 16);
++	}
++	pcmd++;
++	while ((*pcmd != '\0') && (idx < VNDR_IE_MAX_LEN)) {
++		hex[0] = *pcmd++;
++		hex[1] = *pcmd++;
++		ie_buf[idx++] =  (uint8)simple_strtoul(hex, NULL, 16);
++		datalen++;
++	}
++
++	if (datalen <= 0) {
++		ANDROID_ERROR(("error. vndr ie len:%d\n", datalen));
++		return -EINVAL;
++	}
++
++	tot_len = (int)(sizeof(vndr_ie_setbuf_t) + (datalen - 1));
++	vndr_ie = (vndr_ie_setbuf_t *) kzalloc(tot_len, kflags);
++	if (!vndr_ie) {
++		ANDROID_ERROR(("IE memory alloc failed\n"));
++		return -ENOMEM;
++	}
++	/* Copy the vndr_ie SET command ("add"/"del") to the buffer */
++	strncpy(vndr_ie->cmd, "add", VNDR_IE_CMD_LEN - 1);
++	vndr_ie->cmd[VNDR_IE_CMD_LEN - 1] = '\0';
++
++	/* Set the IE count - the buffer contains only 1 IE */
++	iecount = htod32(1);
++	memcpy((void *)&vndr_ie->vndr_ie_buffer.iecount, &iecount, sizeof(s32));
++
++	/* Set packet flag to indicate that BEACON's will contain this IE */
++	pktflag = htod32(VNDR_IE_BEACON_FLAG | VNDR_IE_PRBRSP_FLAG);
++	memcpy((void *)&vndr_ie->vndr_ie_buffer.vndr_ie_list[0].pktflag, &pktflag,
++		sizeof(u32));
++	/* Set the IE ID */
++	vndr_ie->vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.id = (uchar) DOT11_MNG_PROPR_ID;
++
++	memcpy(&vndr_ie->vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.oui, &ie_buf,
++		DOT11_OUI_LEN);
++	memcpy(&vndr_ie->vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.data,
++		&ie_buf[DOT11_OUI_LEN], datalen);
++
++	ielen = DOT11_OUI_LEN + datalen;
++	vndr_ie->vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.len = (uchar) ielen;
++
++	ioctl_buf = kmalloc(WLC_IOCTL_MEDLEN, GFP_KERNEL);
++	if (!ioctl_buf) {
++		ANDROID_ERROR(("ioctl memory alloc failed\n"));
++		if (vndr_ie) {
++			kfree(vndr_ie);
++		}
++		return -ENOMEM;
++	}
++	memset(ioctl_buf, 0, WLC_IOCTL_MEDLEN);	/* init the buffer */
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		ANDROID_ERROR(("Find index failed\n"));
++		err = BCME_ERROR;
++		goto end;
++	}
++	err = wldev_iovar_setbuf_bsscfg(dev, "vndr_ie", vndr_ie, tot_len, ioctl_buf,
++		WLC_IOCTL_MEDLEN, bssidx, &cfg->ioctl_buf_sync);
++
++end:
++	if (err != BCME_OK) {
++		err = -EINVAL;
++		if (vndr_ie) {
++			kfree(vndr_ie);
++		}
++	}
++	else {
++		/* do NOT free 'vndr_ie' for the next process */
++		wl_cfg80211_ibss_vsie_set_buffer(dev, vndr_ie, tot_len);
++	}
++
++	if (ioctl_buf) {
++		kfree(ioctl_buf);
++	}
++
++	return err;
++}
++#endif
++
++#if defined(BCMFW_ROAM_ENABLE)
++static int
++wl_android_set_roampref(struct net_device *dev, char *command, int total_len)
++{
++	int error = 0;
++	char smbuf[WLC_IOCTL_SMLEN];
++	uint8 buf[MAX_BUF_SIZE];
++	uint8 *pref = buf;
++	char *pcmd;
++	int num_ucipher_suites = 0;
++	int num_akm_suites = 0;
++	wpa_suite_t ucipher_suites[MAX_NUM_SUITES];
++	wpa_suite_t akm_suites[MAX_NUM_SUITES];
++	int num_tuples = 0;
++	int total_bytes = 0;
++	int total_len_left;
++	int i, j;
++	char hex[] = "XX";
++
++	pcmd = command + strlen(CMD_SET_ROAMPREF) + 1;
++	total_len_left = total_len - strlen(CMD_SET_ROAMPREF) + 1;
++
++	num_akm_suites = simple_strtoul(pcmd, NULL, 16);
++	if (num_akm_suites > MAX_NUM_SUITES) {
++		ANDROID_ERROR(("too many AKM suites = %d\n", num_akm_suites));
++		return -1;
++	}
++
++	/* Increment for number of AKM suites field + space */
++	pcmd += 3;
++	total_len_left -= 3;
++
++	/* check to make sure pcmd does not overrun */
++	if (total_len_left < (num_akm_suites * WIDTH_AKM_SUITE))
++		return -1;
++
++	memset(buf, 0, sizeof(buf));
++	memset(akm_suites, 0, sizeof(akm_suites));
++	memset(ucipher_suites, 0, sizeof(ucipher_suites));
++
++	/* Save the AKM suites passed in the command */
++	for (i = 0; i < num_akm_suites; i++) {
++		/* Store the MSB first, as required by join_pref */
++		for (j = 0; j < 4; j++) {
++			hex[0] = *pcmd++;
++			hex[1] = *pcmd++;
++			buf[j] = (uint8)simple_strtoul(hex, NULL, 16);
++		}
++		memcpy((uint8 *)&akm_suites[i], buf, sizeof(uint32));
++	}
++
++	total_len_left -= (num_akm_suites * WIDTH_AKM_SUITE);
++	num_ucipher_suites = simple_strtoul(pcmd, NULL, 16);
++	/* Increment for number of cipher suites field + space */
++	pcmd += 3;
++	total_len_left -= 3;
++
++	if (total_len_left < (num_ucipher_suites * WIDTH_AKM_SUITE))
++		return -1;
++
++	/* Save the cipher suites passed in the command */
++	for (i = 0; i < num_ucipher_suites; i++) {
++		/* Store the MSB first, as required by join_pref */
++		for (j = 0; j < 4; j++) {
++			hex[0] = *pcmd++;
++			hex[1] = *pcmd++;
++			buf[j] = (uint8)simple_strtoul(hex, NULL, 16);
++		}
++		memcpy((uint8 *)&ucipher_suites[i], buf, sizeof(uint32));
++	}
++
++	/* Join preference for RSSI
++	 * Type	  : 1 byte (0x01)
++	 * Length : 1 byte (0x02)
++	 * Value  : 2 bytes	(reserved)
++	 */
++	*pref++ = WL_JOIN_PREF_RSSI;
++	*pref++ = JOIN_PREF_RSSI_LEN;
++	*pref++ = 0;
++	*pref++ = 0;
++
++	/* Join preference for WPA
++	 * Type	  : 1 byte (0x02)
++	 * Length : 1 byte (not used)
++	 * Value  : (variable length)
++	 *		reserved: 1 byte
++	 *      count	: 1 byte (no of tuples)
++	 *		Tuple1	: 12 bytes
++	 *			akm[4]
++	 *			ucipher[4]
++	 *			mcipher[4]
++	 *		Tuple2	: 12 bytes
++	 *		Tuplen	: 12 bytes
++	 */
++	num_tuples = num_akm_suites * num_ucipher_suites;
++	if (num_tuples != 0) {
++		if (num_tuples <= JOIN_PREF_MAX_WPA_TUPLES) {
++			*pref++ = WL_JOIN_PREF_WPA;
++			*pref++ = 0;
++			*pref++ = 0;
++			*pref++ = (uint8)num_tuples;
++			total_bytes = JOIN_PREF_RSSI_SIZE + JOIN_PREF_WPA_HDR_SIZE +
++				(JOIN_PREF_WPA_TUPLE_SIZE * num_tuples);
++		} else {
++			ANDROID_ERROR(("%s: Too many wpa configs for join_pref \n", __FUNCTION__));
++			return -1;
++		}
++	} else {
++		/* No WPA config, configure only RSSI preference */
++		total_bytes = JOIN_PREF_RSSI_SIZE;
++	}
++
++	/* akm-ucipher-mcipher tuples in the format required for join_pref */
++	for (i = 0; i < num_ucipher_suites; i++) {
++		for (j = 0; j < num_akm_suites; j++) {
++			memcpy(pref, (uint8 *)&akm_suites[j], WPA_SUITE_LEN);
++			pref += WPA_SUITE_LEN;
++			memcpy(pref, (uint8 *)&ucipher_suites[i], WPA_SUITE_LEN);
++			pref += WPA_SUITE_LEN;
++			/* Set to 0 to match any available multicast cipher */
++			memset(pref, 0, WPA_SUITE_LEN);
++			pref += WPA_SUITE_LEN;
++		}
++	}
++
++	prhex("join pref", (uint8 *)buf, total_bytes);
++	error = wldev_iovar_setbuf(dev, "join_pref", buf, total_bytes, smbuf, sizeof(smbuf), NULL);
++	if (error) {
++		ANDROID_ERROR(("Failed to set join_pref, error = %d\n", error));
++	}
++	return error;
++}
++#endif /* defined(BCMFW_ROAM_ENABLE */
++
++#ifdef WL_CFG80211
++static int
++wl_android_iolist_add(struct net_device *dev, struct list_head *head, struct io_cfg *config)
++{
++	struct io_cfg *resume_cfg;
++	s32 ret;
++
++	resume_cfg = kzalloc(sizeof(struct io_cfg), GFP_KERNEL);
++	if (!resume_cfg)
++		return -ENOMEM;
++
++	if (config->iovar) {
++		ret = wldev_iovar_getint(dev, config->iovar, &resume_cfg->param);
++		if (ret) {
++			ANDROID_ERROR(("%s: Failed to get current %s value\n",
++				__FUNCTION__, config->iovar));
++			goto error;
++		}
++
++		ret = wldev_iovar_setint(dev, config->iovar, config->param);
++		if (ret) {
++			ANDROID_ERROR(("%s: Failed to set %s to %d\n", __FUNCTION__,
++				config->iovar, config->param));
++			goto error;
++		}
++
++		resume_cfg->iovar = config->iovar;
++	} else {
++		resume_cfg->arg = kzalloc(config->len, GFP_KERNEL);
++		if (!resume_cfg->arg) {
++			ret = -ENOMEM;
++			goto error;
++		}
++		ret = wldev_ioctl_get(dev, config->ioctl, resume_cfg->arg, config->len);
++		if (ret) {
++			ANDROID_ERROR(("%s: Failed to get ioctl %d\n", __FUNCTION__,
++				config->ioctl));
++			goto error;
++		}
++		ret = wldev_ioctl_set(dev, config->ioctl + 1, config->arg, config->len);
++		if (ret) {
++			ANDROID_ERROR(("%s: Failed to set %s to %d\n", __FUNCTION__,
++				config->iovar, config->param));
++			goto error;
++		}
++		if (config->ioctl + 1 == WLC_SET_PM)
++			wl_cfg80211_update_power_mode(dev);
++		resume_cfg->ioctl = config->ioctl;
++		resume_cfg->len = config->len;
++	}
++
++	list_add(&resume_cfg->list, head);
++
++	return 0;
++error:
++	kfree(resume_cfg->arg);
++	kfree(resume_cfg);
++	return ret;
++}
++
++static void
++wl_android_iolist_resume(struct net_device *dev, struct list_head *head)
++{
++	struct io_cfg *config;
++	struct list_head *cur, *q;
++	s32 ret = 0;
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	list_for_each_safe(cur, q, head) {
++		config = list_entry(cur, struct io_cfg, list);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++		if (config->iovar) {
++			if (!ret)
++				ret = wldev_iovar_setint(dev, config->iovar,
++					config->param);
++		} else {
++			if (!ret)
++				ret = wldev_ioctl_set(dev, config->ioctl + 1,
++					config->arg, config->len);
++			if (config->ioctl + 1 == WLC_SET_PM)
++				wl_cfg80211_update_power_mode(dev);
++			kfree(config->arg);
++		}
++		list_del(cur);
++		kfree(config);
++	}
++}
++#ifdef WL11ULB
++static int
++wl_android_set_ulb_mode(struct net_device *dev, char *command, int total_len)
++{
++	int mode = 0;
++
++	ANDROID_INFO(("set ulb mode (%s) \n", command));
++	if (sscanf(command, "%*s %d", &mode) != 1) {
++		ANDROID_ERROR(("%s: Failed to get Parameter\n", __FUNCTION__));
++		return -1;
++	}
++	return wl_cfg80211_set_ulb_mode(dev, mode);
++}
++static int
++wl_android_set_ulb_bw(struct net_device *dev, char *command, int total_len)
++{
++	int bw = 0;
++	u8 *pos;
++	char *ifname = NULL;
++	ANDROID_INFO(("set ulb bw (%s) \n", command));
++
++	/*
++	 * For sta/ap: IFNAME=<ifname> DRIVER ULB_BW <bw> ifname
++	 * For p2p:    IFNAME=wlan0 DRIVER ULB_BW <bw> p2p-dev-wlan0
++	 */
++	if (total_len < strlen(CMD_ULB_BW) + 2)
++		return -EINVAL;
++
++	pos = command + strlen(CMD_ULB_BW) + 1;
++	bw = bcm_atoi(pos);
++
++	if ((strlen(pos) >= 5)) {
++		ifname = pos + 2;
++	}
++
++	ANDROID_INFO(("[ULB] ifname:%s ulb_bw:%d \n", ifname, bw));
++	return wl_cfg80211_set_ulb_bw(dev, bw, ifname);
++}
++#endif /* WL11ULB */
++
++static int
++wl_android_set_miracast(struct net_device *dev, char *command, int total_len)
++{
++	int mode, val;
++	int ret = 0;
++	struct io_cfg config;
++
++	if (sscanf(command, "%*s %d", &mode) != 1) {
++		ANDROID_ERROR(("%s: Failed to get Parameter\n", __FUNCTION__));
++		return -1;
++	}
++
++	ANDROID_INFO(("%s: enter miracast mode %d\n", __FUNCTION__, mode));
++
++	if (miracast_cur_mode == mode) {
++		return 0;
++	}
++
++	wl_android_iolist_resume(dev, &miracast_resume_list);
++	miracast_cur_mode = MIRACAST_MODE_OFF;
++
++	switch (mode) {
++	case MIRACAST_MODE_SOURCE:
++		/* setting mchan_algo to platform specific value */
++		config.iovar = "mchan_algo";
++
++		ret = wldev_ioctl_get(dev, WLC_GET_BCNPRD, &val, sizeof(int));
++		if (!ret && val > 100) {
++			config.param = 0;
++			ANDROID_ERROR(("%s: Connected station's beacon interval: "
++				"%d and set mchan_algo to %d \n",
++				__FUNCTION__, val, config.param));
++		} else {
++			config.param = MIRACAST_MCHAN_ALGO;
++		}
++		ret = wl_android_iolist_add(dev, &miracast_resume_list, &config);
++		if (ret) {
++			goto resume;
++		}
++
++		/* setting mchan_bw to platform specific value */
++		config.iovar = "mchan_bw";
++		config.param = MIRACAST_MCHAN_BW;
++		ret = wl_android_iolist_add(dev, &miracast_resume_list, &config);
++		if (ret) {
++			goto resume;
++		}
++
++		/* setting apmdu to platform specific value */
++		config.iovar = "ampdu_mpdu";
++		config.param = MIRACAST_AMPDU_SIZE;
++		ret = wl_android_iolist_add(dev, &miracast_resume_list, &config);
++		if (ret) {
++			goto resume;
++		}
++		/* FALLTROUGH */
++		/* Source mode shares most configurations with sink mode.
++		 * Fall through here to avoid code duplication
++		 */
++	case MIRACAST_MODE_SINK:
++		/* disable internal roaming */
++		config.iovar = "roam_off";
++		config.param = 1;
++		ret = wl_android_iolist_add(dev, &miracast_resume_list, &config);
++		if (ret) {
++			goto resume;
++		}
++
++		/* tunr off pm */
++		ret = wldev_ioctl_get(dev, WLC_GET_PM, &val, sizeof(val));
++		if (ret) {
++			goto resume;
++		}
++
++		if (val != PM_OFF) {
++			val = PM_OFF;
++			config.iovar = NULL;
++			config.ioctl = WLC_GET_PM;
++			config.arg = &val;
++			config.len = sizeof(int);
++			ret = wl_android_iolist_add(dev, &miracast_resume_list, &config);
++			if (ret) {
++				goto resume;
++			}
++		}
++		break;
++	case MIRACAST_MODE_OFF:
++	default:
++		break;
++	}
++	miracast_cur_mode = mode;
++
++	return 0;
++
++resume:
++	ANDROID_ERROR(("%s: turnoff miracast mode because of err%d\n", __FUNCTION__, ret));
++	wl_android_iolist_resume(dev, &miracast_resume_list);
++	return ret;
++}
++#endif
++
++#ifdef WL_RELMCAST
++#define NETLINK_OXYGEN     30
++#define AIBSS_BEACON_TIMEOUT	10
++
++static struct sock *nl_sk = NULL;
++
++static void wl_netlink_recv(struct sk_buff *skb)
++{
++	ANDROID_ERROR(("netlink_recv called\n"));
++}
++
++static int wl_netlink_init(void)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	struct netlink_kernel_cfg cfg = {
++		.input	= wl_netlink_recv,
++	};
++#endif
++
++	if (nl_sk != NULL) {
++		ANDROID_ERROR(("nl_sk already exist\n"));
++		return BCME_ERROR;
++	}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++	nl_sk = netlink_kernel_create(&init_net, NETLINK_OXYGEN,
++		0, wl_netlink_recv, NULL, THIS_MODULE);
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0))
++	nl_sk = netlink_kernel_create(&init_net, NETLINK_OXYGEN, THIS_MODULE, &cfg);
++#else
++	nl_sk = netlink_kernel_create(&init_net, NETLINK_OXYGEN, &cfg);
++#endif
++
++	if (nl_sk == NULL) {
++		ANDROID_ERROR(("nl_sk is not ready\n"));
++		return BCME_ERROR;
++	}
++
++	return BCME_OK;
++}
++
++static void wl_netlink_deinit(void)
++{
++	if (nl_sk) {
++		netlink_kernel_release(nl_sk);
++		nl_sk = NULL;
++	}
++}
++
++s32
++wl_netlink_send_msg(int pid, int type, int seq, const void *data, size_t size)
++{
++	struct sk_buff *skb = NULL;
++	struct nlmsghdr *nlh = NULL;
++	int ret = -1;
++
++	if (nl_sk == NULL) {
++		ANDROID_ERROR(("nl_sk was not initialized\n"));
++		goto nlmsg_failure;
++	}
++
++	skb = alloc_skb(NLMSG_SPACE(size), GFP_ATOMIC);
++	if (skb == NULL) {
++		ANDROID_ERROR(("failed to allocate memory\n"));
++		goto nlmsg_failure;
++	}
++
++	nlh = nlmsg_put(skb, 0, 0, 0, size, 0);
++	if (nlh == NULL) {
++		ANDROID_ERROR(("failed to build nlmsg, skb_tailroom:%d, nlmsg_total_size:%d\n",
++			skb_tailroom(skb), nlmsg_total_size(size)));
++		dev_kfree_skb(skb);
++		goto nlmsg_failure;
++	}
++
++	memcpy(nlmsg_data(nlh), data, size);
++	nlh->nlmsg_seq = seq;
++	nlh->nlmsg_type = type;
++
++	/* netlink_unicast() takes ownership of the skb and frees it itself. */
++	ret = netlink_unicast(nl_sk, skb, pid, 0);
++	ANDROID_TRACE(("netlink_unicast() pid=%d, ret=%d\n", pid, ret));
++
++nlmsg_failure:
++	return ret;
++}
++#endif /* WL_RELMCAST */
++
++int wl_keep_alive_set(struct net_device *dev, char* extra, int total_len)
++{
++	wl_mkeep_alive_pkt_t	mkeep_alive_pkt;
++	int ret;
++	uint period_msec = 0;
++	char *buf;
++
++	if (extra == NULL) {
++		 ANDROID_ERROR(("%s: extra is NULL\n", __FUNCTION__));
++		 return -1;
++	}
++	if (sscanf(extra, "%d", &period_msec) != 1) {
++		 ANDROID_ERROR(("%s: sscanf error. check period_msec value\n", __FUNCTION__));
++		 return -EINVAL;
++	}
++	ANDROID_ERROR(("%s: period_msec is %d\n", __FUNCTION__, period_msec));
++
++	memset(&mkeep_alive_pkt, 0, sizeof(wl_mkeep_alive_pkt_t));
++
++	mkeep_alive_pkt.period_msec = period_msec;
++	mkeep_alive_pkt.version = htod16(WL_MKEEP_ALIVE_VERSION);
++	mkeep_alive_pkt.length = htod16(WL_MKEEP_ALIVE_FIXED_LEN);
++
++	/* Setup keep alive zero for null packet generation */
++	mkeep_alive_pkt.keep_alive_id = 0;
++	mkeep_alive_pkt.len_bytes = 0;
++
++	buf = kmalloc(WLC_IOCTL_SMLEN, GFP_KERNEL);
++	if (!buf) {
++		ANDROID_ERROR(("%s: buffer alloc failed\n", __FUNCTION__));
++		return BCME_NOMEM;
++	}
++	ret = wldev_iovar_setbuf(dev, "mkeep_alive", (char *)&mkeep_alive_pkt,
++			WL_MKEEP_ALIVE_FIXED_LEN, buf, WLC_IOCTL_SMLEN, NULL);
++	if (ret < 0)
++		ANDROID_ERROR(("%s:keep_alive set failed:%d\n", __FUNCTION__, ret));
++	else
++		ANDROID_TRACE(("%s:keep_alive set ok\n", __FUNCTION__));
++	kfree(buf);
++	return ret;
++}
++
++#ifdef P2PRESP_WFDIE_SRC
++static int wl_android_get_wfdie_resp(struct net_device *dev, char *command, int total_len)
++{
++	int error = 0;
++	int bytes_written = 0;
++	int only_resp_wfdsrc = 0;
++
++	error = wldev_iovar_getint(dev, "p2p_only_resp_wfdsrc", &only_resp_wfdsrc);
++	if (error) {
++		ANDROID_ERROR(("%s: Failed to get the mode for only_resp_wfdsrc, error = %d\n",
++			__FUNCTION__, error));
++		return -1;
++	}
++
++	bytes_written = snprintf(command, total_len, "%s %d",
++		CMD_P2P_GET_WFDIE_RESP, only_resp_wfdsrc);
++
++	return bytes_written;
++}
++
++static int wl_android_set_wfdie_resp(struct net_device *dev, int only_resp_wfdsrc)
++{
++	int error = 0;
++
++	error = wldev_iovar_setint(dev, "p2p_only_resp_wfdsrc", only_resp_wfdsrc);
++	if (error) {
++		ANDROID_ERROR(("%s: Failed to set only_resp_wfdsrc %d, error = %d\n",
++			__FUNCTION__, only_resp_wfdsrc, error));
++		return -1;
++	}
++
++	return 0;
++}
++#endif /* P2PRESP_WFDIE_SRC */
++
++#ifdef BT_WIFI_HANDOVER
++static int
++wl_tbow_teardown(struct net_device *dev, char *command, int total_len)
++{
++	int err = BCME_OK;
++	char buf[WLC_IOCTL_SMLEN];
++	tbow_setup_netinfo_t netinfo;
++	memset(&netinfo, 0, sizeof(netinfo));
++	netinfo.opmode = TBOW_HO_MODE_TEARDOWN;
++
++	err = wldev_iovar_setbuf_bsscfg(dev, "tbow_doho", &netinfo,
++			sizeof(tbow_setup_netinfo_t), buf, WLC_IOCTL_SMLEN, 0, NULL);
++	if (err < 0) {
++		ANDROID_ERROR(("tbow_doho iovar error %d\n", err));
++			return err;
++	}
++	return err;
++}
++#endif /* BT_WIFI_HANOVER */
++
++#ifdef SET_RPS_CPUS
++static int
++wl_android_set_rps_cpus(struct net_device *dev, char *command, int total_len)
++{
++	int error, enable;
++
++	enable = command[strlen(CMD_RPSMODE) + 1] - '0';
++	error = dhd_rps_cpus_enable(dev, enable);
++
++#if defined(DHDTCPACK_SUPPRESS) && defined(BCMPCIE) && defined(WL_CFG80211)
++	if (!error) {
++		void *dhdp = wl_cfg80211_get_dhdp(net);
++		if (enable) {
++			ANDROID_TRACE(("%s : set ack suppress. TCPACK_SUP_HOLD.\n", __FUNCTION__));
++			dhd_tcpack_suppress_set(dhdp, TCPACK_SUP_HOLD);
++		} else {
++			ANDROID_TRACE(("%s : clear ack suppress.\n", __FUNCTION__));
++			dhd_tcpack_suppress_set(dhdp, TCPACK_SUP_OFF);
++		}
++	}
++#endif /* DHDTCPACK_SUPPRESS && BCMPCIE && WL_CFG80211 */
++
++	return error;
++}
++#endif /* SET_RPS_CPUS */
++
++static int wl_android_get_link_status(struct net_device *dev, char *command,
++	int total_len)
++{
++	int bytes_written, error, result = 0, single_stream, stf = -1, i, nss = 0, mcs_map;
++	uint32 rspec;
++	uint encode, rate, txexp;
++	struct wl_bss_info *bi;
++	int datalen = sizeof(uint32) + sizeof(wl_bss_info_t);
++	char buf[datalen];
++
++	/* get BSS information */
++	*(u32 *) buf = htod32(datalen);
++	error = wldev_ioctl_get(dev, WLC_GET_BSS_INFO, (void *)buf, datalen);
++	if (unlikely(error)) {
++		ANDROID_ERROR(("Could not get bss info %d\n", error));
++		return -1;
++	}
++
++	bi = (struct wl_bss_info *) (buf + sizeof(uint32));
++
++	for (i = 0; i < ETHER_ADDR_LEN; i++) {
++		if (bi->BSSID.octet[i] > 0) {
++			break;
++		}
++	}
++
++	if (i == ETHER_ADDR_LEN) {
++		ANDROID_TRACE(("No BSSID\n"));
++		return -1;
++	}
++
++	/* check VHT capability at beacon */
++	if (bi->vht_cap) {
++		if (CHSPEC_IS5G(bi->chanspec)) {
++			result |= WL_ANDROID_LINK_AP_VHT_SUPPORT;
++		}
++	}
++
++	/* get a rspec (radio spectrum) rate */
++	error = wldev_iovar_getint(dev, "nrate", &rspec);
++	if (unlikely(error) || rspec == 0) {
++		ANDROID_ERROR(("get link status error (%d)\n", error));
++		return -1;
++	}
++
++	encode = (rspec & WL_RSPEC_ENCODING_MASK);
++	rate = (rspec & WL_RSPEC_RATE_MASK);
++	txexp = (rspec & WL_RSPEC_TXEXP_MASK) >> WL_RSPEC_TXEXP_SHIFT;
++
++	switch (encode) {
++	case WL_RSPEC_ENCODE_HT:
++		/* check Rx MCS Map for HT */
++		for (i = 0; i < MAX_STREAMS_SUPPORTED; i++) {
++			int8 bitmap = 0xFF;
++			if (i == MAX_STREAMS_SUPPORTED-1) {
++				bitmap = 0x7F;
++			}
++			if (bi->basic_mcs[i] & bitmap) {
++				nss++;
++			}
++		}
++		break;
++	case WL_RSPEC_ENCODE_VHT:
++		/* check Rx MCS Map for VHT */
++		for (i = 1; i <= VHT_CAP_MCS_MAP_NSS_MAX; i++) {
++			mcs_map = VHT_MCS_MAP_GET_MCS_PER_SS(i, dtoh16(bi->vht_rxmcsmap));
++			if (mcs_map != VHT_CAP_MCS_MAP_NONE) {
++				nss++;
++			}
++		}
++		break;
++	}
++
++	/* check MIMO capability with nss in beacon */
++	if (nss > 1) {
++		result |= WL_ANDROID_LINK_AP_MIMO_SUPPORT;
++	}
++
++	single_stream = (encode == WL_RSPEC_ENCODE_RATE) ||
++		((encode == WL_RSPEC_ENCODE_HT) && rate < 8) ||
++		((encode == WL_RSPEC_ENCODE_VHT) &&
++		((rspec & WL_RSPEC_VHT_NSS_MASK) >> WL_RSPEC_VHT_NSS_SHIFT) == 1);
++
++	if (txexp == 0) {
++		if ((rspec & WL_RSPEC_STBC) && single_stream) {
++			stf = OLD_NRATE_STF_STBC;
++		} else {
++			stf = (single_stream) ? OLD_NRATE_STF_SISO : OLD_NRATE_STF_SDM;
++		}
++	} else if (txexp == 1 && single_stream) {
++		stf = OLD_NRATE_STF_CDD;
++	}
++
++	/* check 11ac (VHT) */
++	if (encode == WL_RSPEC_ENCODE_VHT) {
++		if (CHSPEC_IS5G(bi->chanspec)) {
++			result |= WL_ANDROID_LINK_VHT;
++		}
++	}
++
++	/* check MIMO */
++	if (result & WL_ANDROID_LINK_AP_MIMO_SUPPORT) {
++		switch (stf) {
++		case OLD_NRATE_STF_SISO:
++			break;
++		case OLD_NRATE_STF_CDD:
++		case OLD_NRATE_STF_STBC:
++			result |= WL_ANDROID_LINK_MIMO;
++			break;
++		case OLD_NRATE_STF_SDM:
++			if (!single_stream) {
++				result |= WL_ANDROID_LINK_MIMO;
++			}
++			break;
++		}
++	}
++
++	ANDROID_TRACE(("%s:result=%d, stf=%d, single_stream=%d, mcs map=%d\n",
++		__FUNCTION__, result, stf, single_stream, nss));
++
++	bytes_written = sprintf(command, "%s %d", CMD_GET_LINK_STATUS, result);
++
++	return bytes_written;
++}
++
++#ifdef P2P_LISTEN_OFFLOADING
++s32
++wl_cfg80211_p2plo_offload(struct net_device *dev, char *cmd, char* buf, int len)
++{
++	int ret = 0;
++
++	ANDROID_ERROR(("Entry cmd:%s arg_len:%d \n", cmd, len));
++
++	if (strncmp(cmd, "P2P_LO_START", strlen("P2P_LO_START")) == 0) {
++		ret = wl_cfg80211_p2plo_listen_start(dev, buf, len);
++	} else if (strncmp(cmd, "P2P_LO_STOP", strlen("P2P_LO_STOP")) == 0) {
++		ret = wl_cfg80211_p2plo_listen_stop(dev);
++	} else {
++		ANDROID_ERROR(("Request for Unsupported CMD:%s \n", buf));
++		ret = -EINVAL;
++	}
++	return ret;
++}
++#endif /* P2P_LISTEN_OFFLOADING */
++
++#if defined(BCM4359_CHIP) && defined(WL_CFG80211)
++int
++wl_android_murx_bfe_cap(struct net_device *dev, int val)
++{
++	int err = BCME_OK;
++	int iface_count = wl_cfg80211_iface_count(dev);
++	struct ether_addr bssid;
++	wl_reassoc_params_t params;
++
++	if (iface_count > 1) {
++		ANDROID_ERROR(("murx_bfe_cap change is not allowed when "
++				"there are multiple interfaces\n"));
++		return -EINVAL;
++	}
++	/* Now there is only single interface */
++	err = wldev_iovar_setint(dev, "murx_bfe_cap", val);
++	if (unlikely(err)) {
++		ANDROID_ERROR(("Failed to set murx_bfe_cap IOVAR to %d,"
++				"error %d\n", val, err));
++		return err;
++	}
++
++	/* If successful intiate a reassoc */
++	memset(&bssid, 0, ETHER_ADDR_LEN);
++	if ((err = wldev_ioctl_get(dev, WLC_GET_BSSID, &bssid, ETHER_ADDR_LEN)) < 0) {
++		ANDROID_ERROR(("Failed to get bssid, error=%d\n", err));
++		return err;
++	}
++
++	bzero(&params, sizeof(wl_reassoc_params_t));
++	memcpy(&params.bssid, &bssid, ETHER_ADDR_LEN);
++
++	if ((err = wldev_ioctl_set(dev, WLC_REASSOC, &params,
++		sizeof(wl_reassoc_params_t))) < 0) {
++		ANDROID_ERROR(("reassoc failed err:%d \n", err));
++	} else {
++		ANDROID_TRACE(("reassoc issued successfully\n"));
++	}
++
++	return err;
++}
++#endif /* BCM4359_CHIP */
++
++#ifdef SUPPORT_AP_HIGHER_BEACONRATE
++int
++wl_android_set_ap_beaconrate(struct net_device *dev, char *command)
++{
++	int rate = 0;
++	char *pos, *token;
++	char *ifname = NULL;
++	int err = BCME_OK;
++
++	/*
++	 * DRIVER SET_AP_BEACONRATE <rate> <ifname>
++	 */
++	pos = command;
++
++	/* drop command */
++	token = bcmstrtok(&pos, " ", NULL);
++
++	/* Rate */
++	token = bcmstrtok(&pos, " ", NULL);
++	if (!token)
++		return -EINVAL;
++	rate = bcm_atoi(token);
++
++	/* get the interface name */
++	token = bcmstrtok(&pos, " ", NULL);
++	if (!token)
++		return -EINVAL;
++	ifname = token;
++
++	ANDROID_TRACE(("rate %d, ifacename %s\n", rate, ifname));
++
++	err = wl_set_ap_beacon_rate(dev, rate, ifname);
++	if (unlikely(err)) {
++		ANDROID_ERROR(("Failed to set ap beacon rate to %d, error = %d\n", rate, err));
++	}
++
++	return err;
++}
++
++int wl_android_get_ap_basicrate(struct net_device *dev, char *command, int total_len)
++{
++	char *pos, *token;
++	char *ifname = NULL;
++	int bytes_written = 0;
++	/*
++	 * DRIVER GET_AP_BASICRATE <ifname>
++	 */
++	pos = command;
++
++	/* drop command */
++	token = bcmstrtok(&pos, " ", NULL);
++
++	/* get the interface name */
++	token = bcmstrtok(&pos, " ", NULL);
++	if (!token)
++		return -EINVAL;
++	ifname = token;
++
++	ANDROID_TRACE(("ifacename %s\n", ifname));
++
++	bytes_written = wl_get_ap_basic_rate(dev, command, ifname, total_len);
++	if (bytes_written < 1) {
++		ANDROID_ERROR(("Failed to get ap basic rate, error = %d\n", bytes_written));
++		return -EPROTO;
++	}
++
++	return bytes_written;
++
++}
++#endif /* SUPPORT_AP_HIGHER_BEACONRATE */
++
++#ifdef SUPPORT_AP_RADIO_PWRSAVE
++int
++wl_android_get_ap_rps(struct net_device *dev, char *command, int total_len)
++{
++	char *pos, *token;
++	char *ifname = NULL;
++	int bytes_written = 0;
++	/*
++	 * DRIVER GET_AP_RPS <ifname>
++	 */
++	pos = command;
++
++	/* drop command */
++	token = bcmstrtok(&pos, " ", NULL);
++
++	/* get the interface name */
++	token = bcmstrtok(&pos, " ", NULL);
++	if (!token)
++		return -EINVAL;
++	ifname = token;
++
++	ANDROID_TRACE(("ifacename %s\n", ifname));
++
++	bytes_written = wl_get_ap_rps(dev, command, ifname, total_len);
++	if (bytes_written < 1) {
++		ANDROID_ERROR(("Failed to get rps, error = %d\n", bytes_written));
++		return -EPROTO;
++	}
++
++	return bytes_written;
++
++}
++
++int
++wl_android_set_ap_rps(struct net_device *dev, char *command, int total_len)
++{
++	int enable = 0;
++	char *pos, *token;
++	char *ifname = NULL;
++	int err = BCME_OK;
++
++	/*
++	 * DRIVER SET_AP_RPS <0/1> <ifname>
++	 */
++	pos = command;
++
++	/* drop command */
++	token = bcmstrtok(&pos, " ", NULL);
++
++	/* Enable */
++	token = bcmstrtok(&pos, " ", NULL);
++	if (!token)
++		return -EINVAL;
++	enable = bcm_atoi(token);
++
++	/* get the interface name */
++	token = bcmstrtok(&pos, " ", NULL);
++	if (!token)
++		return -EINVAL;
++	ifname = token;
++
++	ANDROID_TRACE(("enable %d, ifacename %s\n", enable, ifname));
++
++	err = wl_set_ap_rps(dev, enable? TRUE: FALSE, ifname);
++	if (unlikely(err)) {
++		ANDROID_ERROR(("Failed to set rps, enable %d, error = %d\n", enable, err));
++	}
++
++	return err;
++}
++
++int
++wl_android_set_ap_rps_params(struct net_device *dev, char *command, int total_len)
++{
++	ap_rps_info_t rps;
++	char *pos, *token;
++	char *ifname = NULL;
++	int err = BCME_OK;
++
++	memset(&rps, 0, sizeof(rps));
++	/*
++	 * DRIVER SET_AP_RPS_PARAMS <pps> <level> <quiettime> <assoccheck> <ifname>
++	 */
++	pos = command;
++
++	/* drop command */
++	token = bcmstrtok(&pos, " ", NULL);
++
++	/* pps */
++	token = bcmstrtok(&pos, " ", NULL);
++	if (!token)
++		return -EINVAL;
++	rps.pps = bcm_atoi(token);
++
++	/* level */
++	token = bcmstrtok(&pos, " ", NULL);
++	if (!token)
++		return -EINVAL;
++	rps.level = bcm_atoi(token);
++
++	/* quiettime */
++	token = bcmstrtok(&pos, " ", NULL);
++	if (!token)
++		return -EINVAL;
++	rps.quiet_time = bcm_atoi(token);
++
++	/* sta assoc check */
++	token = bcmstrtok(&pos, " ", NULL);
++	if (!token)
++		return -EINVAL;
++	rps.sta_assoc_check = bcm_atoi(token);
++
++	/* get the interface name */
++	token = bcmstrtok(&pos, " ", NULL);
++	if (!token)
++		return -EINVAL;
++	ifname = token;
++
++	ANDROID_TRACE(("pps %d, level %d, quiettime %d, sta_assoc_check %d, "
++		"ifacename %s\n", rps.pps, rps.level, rps.quiet_time,
++		rps.sta_assoc_check, ifname));
++
++	err = wl_update_ap_rps_params(dev, &rps, ifname);
++	if (unlikely(err)) {
++		ANDROID_ERROR(("Failed to update rps, pps %d, level %d, quiettime %d, "
++			"sta_assoc_check %d, err = %d\n", rps.pps, rps.level, rps.quiet_time,
++			rps.sta_assoc_check, err));
++	}
++
++	return err;
++}
++#endif /* SUPPORT_AP_RADIO_PWRSAVE */
++
++#ifdef SUPPORT_RSSI_LOGGING
++int
++wl_android_get_rssi_per_ant(struct net_device *dev, char *command, int total_len)
++{
++	wl_rssi_ant_mimo_t rssi_ant_mimo;
++	char *ifname = NULL;
++	char *peer_mac = NULL;
++	char *mimo_cmd = "mimo";
++	char *pos, *token;
++	int err = BCME_OK;
++	int bytes_written = 0;
++	bool mimo_rssi = FALSE;
++
++	memset(&rssi_ant_mimo, 0, sizeof(wl_rssi_ant_mimo_t));
++	/*
++	 * STA I/F: DRIVER GET_RSSI_PER_ANT <ifname> <mimo>
++	 * AP/GO I/F: DRIVER GET_RSSI_PER_ANT <ifname> <Peer MAC addr> <mimo>
++	 */
++	pos = command;
++
++	/* drop command */
++	token = bcmstrtok(&pos, " ", NULL);
++
++	/* get the interface name */
++	token = bcmstrtok(&pos, " ", NULL);
++	if (!token) {
++		ANDROID_ERROR(("Invalid arguments\n"));
++		return -EINVAL;
++	}
++	ifname = token;
++
++	/* Optional: Check the MIMO RSSI mode or peer MAC address */
++	token = bcmstrtok(&pos, " ", NULL);
++	if (token) {
++		/* Check the MIMO RSSI mode */
++		if (strncmp(token, mimo_cmd, strlen(mimo_cmd)) == 0) {
++			mimo_rssi = TRUE;
++		} else {
++			peer_mac = token;
++		}
++	}
++
++	/* Optional: Check the MIMO RSSI mode - RSSI sum across antennas */
++	token = bcmstrtok(&pos, " ", NULL);
++	if (token && strncmp(token, mimo_cmd, strlen(mimo_cmd)) == 0) {
++		mimo_rssi = TRUE;
++	}
++
++	err = wl_get_rssi_per_ant(dev, ifname, peer_mac, &rssi_ant_mimo);
++	if (unlikely(err)) {
++		ANDROID_ERROR(("Failed to get RSSI info, err=%d\n", err));
++		return err;
++	}
++
++	/* Parse the results */
++	ANDROID_TRACE(("ifname %s, version %d, count %d, mimo rssi %d\n",
++		ifname, rssi_ant_mimo.version, rssi_ant_mimo.count, mimo_rssi));
++	if (mimo_rssi) {
++		ANDROID_TRACE(("MIMO RSSI: %d\n", rssi_ant_mimo.rssi_sum));
++		bytes_written = snprintf(command, total_len, "%s MIMO %d",
++			CMD_GET_RSSI_PER_ANT, rssi_ant_mimo.rssi_sum);
++	} else {
++		int cnt;
++		bytes_written = snprintf(command, total_len, "%s PER_ANT ", CMD_GET_RSSI_PER_ANT);
++		for (cnt = 0; cnt < rssi_ant_mimo.count; cnt++) {
++			ANDROID_TRACE(("RSSI[%d]: %d\n", cnt, rssi_ant_mimo.rssi_ant[cnt]));
++			bytes_written = snprintf(command, total_len, "%d ",
++				rssi_ant_mimo.rssi_ant[cnt]);
++		}
++	}
++
++	return bytes_written;
++}
++
++int
++wl_android_set_rssi_logging(struct net_device *dev, char *command, int total_len)
++{
++	rssilog_set_param_t set_param;
++	char *pos, *token;
++	int err = BCME_OK;
++
++	memset(&set_param, 0, sizeof(rssilog_set_param_t));
++	/*
++	 * DRIVER SET_RSSI_LOGGING <enable/disable> <RSSI Threshold> <Time Threshold>
++	 */
++	pos = command;
++
++	/* drop command */
++	token = bcmstrtok(&pos, " ", NULL);
++
++	/* enable/disable */
++	token = bcmstrtok(&pos, " ", NULL);
++	if (!token) {
++		ANDROID_ERROR(("Invalid arguments\n"));
++		return -EINVAL;
++	}
++	set_param.enable = bcm_atoi(token);
++
++	/* RSSI Threshold */
++	token = bcmstrtok(&pos, " ", NULL);
++	if (!token) {
++		ANDROID_ERROR(("Invalid arguments\n"));
++		return -EINVAL;
++	}
++	set_param.rssi_threshold = bcm_atoi(token);
++
++	/* Time Threshold */
++	token = bcmstrtok(&pos, " ", NULL);
++	if (!token) {
++		ANDROID_ERROR(("Invalid arguments\n"));
++		return -EINVAL;
++	}
++	set_param.time_threshold = bcm_atoi(token);
++
++	ANDROID_TRACE(("enable %d, RSSI threshold %d, Time threshold %d\n", set_param.enable,
++		set_param.rssi_threshold, set_param.time_threshold));
++
++	err = wl_set_rssi_logging(dev, (void *)&set_param);
++	if (unlikely(err)) {
++		ANDROID_ERROR(("Failed to configure RSSI logging: enable %d, RSSI Threshold %d,"
++			" Time Threshold %d\n", set_param.enable, set_param.rssi_threshold,
++			set_param.time_threshold));
++	}
++
++	return err;
++}
++
++int
++wl_android_get_rssi_logging(struct net_device *dev, char *command, int total_len)
++{
++	rssilog_get_param_t get_param;
++	int err = BCME_OK;
++	int bytes_written = 0;
++
++	err = wl_get_rssi_logging(dev, (void *)&get_param);
++	if (unlikely(err)) {
++		ANDROID_ERROR(("Failed to get RSSI logging info\n"));
++		return BCME_ERROR;
++	}
++
++	ANDROID_TRACE(("report_count %d, enable %d, rssi_threshold %d, time_threshold %d\n",
++		get_param.report_count, get_param.enable, get_param.rssi_threshold,
++		get_param.time_threshold));
++
++	/* Parse the parameter */
++	if (!get_param.enable) {
++		ANDROID_TRACE(("RSSI LOGGING: Feature is disables\n"));
++		bytes_written = snprintf(command, total_len,
++			"%s FEATURE DISABLED\n", CMD_GET_RSSI_LOGGING);
++	} else if (get_param.enable &
++		(RSSILOG_FLAG_FEATURE_SW | RSSILOG_FLAG_REPORT_READY)) {
++		if (!get_param.report_count) {
++			ANDROID_TRACE(("[PASS] RSSI difference across antennas is within"
++				" threshold limits\n"));
++			bytes_written = snprintf(command, total_len, "%s PASS\n",
++				CMD_GET_RSSI_LOGGING);
++		} else {
++			ANDROID_TRACE(("[FAIL] RSSI difference across antennas found "
++				"to be greater than %3d dB\n", get_param.rssi_threshold));
++			ANDROID_TRACE(("[FAIL] RSSI difference check have failed for "
++				"%d out of %d times\n", get_param.report_count,
++				get_param.time_threshold));
++			ANDROID_TRACE(("[FAIL] RSSI difference is being monitored once "
++				"per second, for a %d secs window\n", get_param.time_threshold));
++			bytes_written = snprintf(command, total_len, "%s FAIL - RSSI Threshold "
++				"%d dBm for %d out of %d times\n", CMD_GET_RSSI_LOGGING,
++				get_param.rssi_threshold, get_param.report_count,
++				get_param.time_threshold);
++		}
++	} else {
++		ANDROID_TRACE(("[BUSY] Reprot is not ready\n"));
++		bytes_written = snprintf(command, total_len, "%s BUSY - NOT READY\n",
++			CMD_GET_RSSI_LOGGING);
++	}
++
++	return bytes_written;
++}
++#endif /* SUPPORT_RSSI_LOGGING */
++
++#ifdef SET_PCIE_IRQ_CPU_CORE
++void
++wl_android_set_irq_cpucore(struct net_device *net, int set)
++{
++	dhd_pub_t *dhdp = wl_cfg80211_get_dhdp(net);
++	if (!dhdp) {
++		ANDROID_ERROR(("dhd is NULL\n"));
++		return;
++	}
++	dhd_set_irq_cpucore(dhdp, set);
++}
++#endif /* SET_PCIE_IRQ_CPU_CORE */
++
++#if defined(DHD_HANG_SEND_UP_TEST)
++void
++wl_android_make_hang_with_reason(struct net_device *dev, const char *string_num)
++{
++	dhd_make_hang_with_reason(dev, string_num);
++}
++#endif /* DHD_HANG_SEND_UP_TEST */
++
++#ifdef WL_CFG80211
++#ifdef WLMESH_CFG80211
++static int
++wl_android_set_rsdb_mode(struct net_device *dev, char *command, int total_len)
++{
++	int ret;
++	wl_config_t rsdb_mode_cfg = {-1, 0};
++	char smbuf[WLC_IOCTL_SMLEN];
++	s32 val = 1;
++
++	if (sscanf(command, "%*s %d", &rsdb_mode_cfg.config) != 1) {
++		DHD_ERROR(("%s: Failed to get Parameter\n", __FUNCTION__));
++		return -1;
++	}
++	DHD_INFO(("%s : RSDB_MODE = %d\n", __FUNCTION__, rsdb_mode_cfg.config));
++
++	ret = wldev_ioctl_set(dev, WLC_DOWN, &val, sizeof(s32));
++	if (ret < 0)
++		DHD_ERROR(("WLC_DOWN error %d\n", ret));
++
++	ret = wldev_iovar_setbuf(dev, "rsdb_mode", &rsdb_mode_cfg, sizeof(rsdb_mode_cfg),
++		smbuf, sizeof(smbuf), NULL);
++	if (ret < 0)
++		DHD_ERROR(("%s : set rsdb_mode error=%d\n", __FUNCTION__, ret));
++
++	ret = wldev_ioctl_set(dev, WLC_UP, &val, sizeof(s32));
++	if (ret < 0)
++		DHD_ERROR(("WLC_UP error %d\n", ret));
++
++	return ret;
++}
++#endif /* WLMESH */
++#endif /* WL_CFG80211 */
++
++#ifdef SUPPORT_LQCM
++static int
++wl_android_lqcm_enable(struct net_device *net, int lqcm_enable)
++{
++	int err = 0;
++
++	err = wldev_iovar_setint(net, "lqcm", lqcm_enable);
++	if (err != BCME_OK) {
++		ANDROID_ERROR(("failed to set lqcm enable %d, error = %d\n", lqcm_enable, err));
++		return -EIO;
++	}
++	return err;
++}
++
++static int wl_android_get_lqcm_report(
++	struct net_device *dev, char *command, int total_len)
++{
++	int bytes_written, err = 0;
++	uint32 lqcm_report = 0;
++	uint32 lqcm_enable, tx_lqcm_idx, rx_lqcm_idx;
++
++	err = wldev_iovar_getint(dev, "lqcm", &lqcm_report);
++	if (err != BCME_OK) {
++		ANDROID_ERROR(("failed to get lqcm report, error = %d\n", err));
++		return -EIO;
++	}
++	lqcm_enable = lqcm_report & LQCM_ENAB_MASK;
++	tx_lqcm_idx = (lqcm_report & LQCM_TX_INDEX_MASK) >> LQCM_TX_INDEX_SHIFT;
++	rx_lqcm_idx = (lqcm_report & LQCM_RX_INDEX_MASK) >> LQCM_RX_INDEX_SHIFT;
++
++	ANDROID_ERROR(("lqcm report EN:%d, TX:%d, RX:%d\n", lqcm_enable, tx_lqcm_idx, rx_lqcm_idx));
++
++	bytes_written = snprintf(command, total_len, "%s %d",
++		CMD_GET_LQCM_REPORT, lqcm_report);
++
++	return bytes_written;
++}
++#endif /* SUPPORT_LQCM */
++
++int
++wl_android_get_snr(struct net_device *dev, char *command, int total_len)
++{
++	int bytes_written, error = 0;
++	s32 snr = 0;
++
++	error = wldev_iovar_getint(dev, "snr", &snr);
++	if (error) {
++		ANDROID_ERROR(("%s: Failed to get SNR %d, error = %d\n",
++			__FUNCTION__, snr, error));
++		return -EIO;
++	}
++
++	bytes_written = snprintf(command, total_len, "snr %d", snr);
++	ANDROID_INFO(("%s: command result is %s\n", __FUNCTION__, command));
++	return bytes_written;
++}
++#ifdef WLADPS_PRIVATE_CMD
++static int
++wl_android_set_adps_mode(struct net_device *dev, const char* string_num)
++{
++	int err = 0, adps_mode;
++	dhd_pub_t *dhdp = wl_cfg80211_get_dhdp(dev);
++
++	adps_mode = bcm_atoi(string_num);
++
++	if ((adps_mode < 0) && (1 < adps_mode)) {
++		ANDROID_ERROR(("%s: Invalid value %d.\n", __FUNCTION__, adps_mode));
++		return -EINVAL;
++	}
++
++	err = dhd_enable_adps(dhdp, adps_mode);
++	if (err != BCME_OK) {
++		ANDROID_ERROR(("failed to set adps mode %d, error = %d\n", adps_mode, err));
++		return -EIO;
++	}
++	return err;
++}
++static int
++wl_android_get_adps_mode(
++	struct net_device *dev, char *command, int total_len)
++{
++	int bytes_written, err = 0;
++	int len;
++	char buf[WLC_IOCTL_SMLEN];
++
++	bcm_iov_buf_t iov_buf;
++	bcm_iov_buf_t *ptr = NULL;
++	wl_adps_params_v1_t *data = NULL;
++
++	uint8 *pdata = NULL;
++	uint8 band, mode = 0;
++
++	memset(&iov_buf, 0, sizeof(iov_buf));
++
++	len = OFFSETOF(bcm_iov_buf_t, data) + sizeof(*data);
++
++	iov_buf.version = WL_ADPS_IOV_VER;
++	iov_buf.len = sizeof(band);
++	iov_buf.id = WL_ADPS_IOV_MODE;
++
++	pdata = (uint8 *)&iov_buf.data;
++
++	for (band = 1; band <= MAX_BANDS; band++) {
++		pdata[0] = band;
++		err = wldev_iovar_getbuf(dev, "adps", &iov_buf, len,
++			buf, WLC_IOCTL_SMLEN, NULL);
++		if (err != BCME_OK) {
++			ANDROID_ERROR(("%s fail to get adps band %d(%d).\n",
++					__FUNCTION__, band, err));
++			return -EIO;
++		}
++		ptr = (bcm_iov_buf_t *) buf;
++		data = (wl_adps_params_v1_t *) ptr->data;
++		mode = data->mode;
++		if (mode != OFF) {
++			break;
++		}
++	}
++
++	bytes_written = snprintf(command, total_len, "%s %d",
++		CMD_GET_ADPS, mode);
++	return bytes_written;
++}
++#endif /* WLADPS_PRIVATE_CMD */
++
++#ifdef DHD_PKT_LOGGING
++static int
++wl_android_pktlog_filter_enable(struct net_device *dev, char *command, int total_len)
++{
++	int bytes_written = 0;
++	dhd_pub_t *dhdp = wl_cfg80211_get_dhdp(dev);
++	dhd_pktlog_filter_t *filter;
++	int err = BCME_OK;
++
++	if (!dhdp || !dhdp->pktlog) {
++		DHD_PKT_LOG(("%s(): dhdp=%p pktlog=%p\n",
++			__FUNCTION__, dhdp, (dhdp ? dhdp->pktlog : NULL)));
++		return -EINVAL;
++	}
++
++	filter = dhdp->pktlog->pktlog_filter;
++
++	err = dhd_pktlog_filter_enable(filter, PKTLOG_TXPKT_CASE, TRUE);
++	err = dhd_pktlog_filter_enable(filter, PKTLOG_TXSTATUS_CASE, TRUE);
++	err = dhd_pktlog_filter_enable(filter, PKTLOG_RXPKT_CASE, TRUE);
++
++	if (err == BCME_OK) {
++		bytes_written = snprintf(command, total_len, "OK");
++		ANDROID_ERROR(("%s: pktlog filter enable success\n", __FUNCTION__));
++	} else {
++		ANDROID_ERROR(("%s: pktlog filter enable fail\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	return bytes_written;
++}
++
++static int
++wl_android_pktlog_filter_disable(struct net_device *dev, char *command, int total_len)
++{
++	int bytes_written = 0;
++	dhd_pub_t *dhdp = wl_cfg80211_get_dhdp(dev);
++	dhd_pktlog_filter_t *filter;
++	int err = BCME_OK;
++
++	if (!dhdp || !dhdp->pktlog) {
++		DHD_PKT_LOG(("%s(): dhdp=%p pktlog=%p\n",
++			__FUNCTION__, dhdp, (dhdp ? dhdp->pktlog : NULL)));
++		return -EINVAL;
++	}
++
++	filter = dhdp->pktlog->pktlog_filter;
++
++	err = dhd_pktlog_filter_enable(filter, PKTLOG_TXPKT_CASE, FALSE);
++	err = dhd_pktlog_filter_enable(filter, PKTLOG_TXSTATUS_CASE, FALSE);
++	err = dhd_pktlog_filter_enable(filter, PKTLOG_RXPKT_CASE, FALSE);
++
++	if (err == BCME_OK) {
++		bytes_written = snprintf(command, total_len, "OK");
++		ANDROID_ERROR(("%s: pktlog filter disable success\n", __FUNCTION__));
++	} else {
++		ANDROID_ERROR(("%s: pktlog filter disable fail\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	return bytes_written;
++}
++
++static int
++wl_android_pktlog_filter_pattern_enable(struct net_device *dev, char *command, int total_len)
++{
++	int bytes_written = 0;
++	dhd_pub_t *dhdp = wl_cfg80211_get_dhdp(dev);
++	dhd_pktlog_filter_t *filter;
++	int err = BCME_OK;
++
++	if (!dhdp || !dhdp->pktlog) {
++		DHD_PKT_LOG(("%s(): dhdp=%p pktlog=%p\n",
++			__FUNCTION__, dhdp, (dhdp ? dhdp->pktlog : NULL)));
++		return -EINVAL;
++	}
++
++	filter = dhdp->pktlog->pktlog_filter;
++
++	if (strlen(CMD_PKTLOG_FILTER_PATTERN_ENABLE) + 1 > total_len) {
++		return BCME_ERROR;
++	}
++
++	err = dhd_pktlog_filter_pattern_enable(filter,
++			command + strlen(CMD_PKTLOG_FILTER_PATTERN_ENABLE) + 1, TRUE);
++
++	if (err == BCME_OK) {
++		bytes_written = snprintf(command, total_len, "OK");
++		ANDROID_ERROR(("%s: pktlog filter pattern enable success\n", __FUNCTION__));
++	} else {
++		ANDROID_ERROR(("%s: pktlog filter pattern enable fail\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	return bytes_written;
++}
++
++static int
++wl_android_pktlog_filter_pattern_disable(struct net_device *dev, char *command, int total_len)
++{
++	int bytes_written = 0;
++	dhd_pub_t *dhdp = wl_cfg80211_get_dhdp(dev);
++	dhd_pktlog_filter_t *filter;
++	int err = BCME_OK;
++
++	if (!dhdp || !dhdp->pktlog) {
++		DHD_PKT_LOG(("%s(): dhdp=%p pktlog=%p\n",
++			__FUNCTION__, dhdp, (dhdp ? dhdp->pktlog : NULL)));
++		return -EINVAL;
++	}
++
++	filter = dhdp->pktlog->pktlog_filter;
++
++	if (strlen(CMD_PKTLOG_FILTER_PATTERN_DISABLE) + 1 > total_len) {
++		return BCME_ERROR;
++	}
++
++	err = dhd_pktlog_filter_pattern_enable(filter,
++			command + strlen(CMD_PKTLOG_FILTER_PATTERN_DISABLE) + 1, FALSE);
++
++	if (err == BCME_OK) {
++		bytes_written = snprintf(command, total_len, "OK");
++		ANDROID_ERROR(("%s: pktlog filter pattern disable success\n", __FUNCTION__));
++	} else {
++		ANDROID_ERROR(("%s: pktlog filter pattern disable fail\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	return bytes_written;
++}
++
++static int
++wl_android_pktlog_filter_add(struct net_device *dev, char *command, int total_len)
++{
++	int bytes_written = 0;
++	dhd_pub_t *dhdp = wl_cfg80211_get_dhdp(dev);
++	dhd_pktlog_filter_t *filter;
++	int err = BCME_OK;
++
++	if (!dhdp || !dhdp->pktlog) {
++		DHD_PKT_LOG(("%s(): dhdp=%p pktlog=%p\n",
++			__FUNCTION__, dhdp, (dhdp ? dhdp->pktlog : NULL)));
++		return -EINVAL;
++	}
++
++	filter = dhdp->pktlog->pktlog_filter;
++
++	if (strlen(CMD_PKTLOG_FILTER_ADD) + 1 > total_len) {
++		return BCME_ERROR;
++	}
++
++	err = dhd_pktlog_filter_add(filter, command + strlen(CMD_PKTLOG_FILTER_ADD) + 1);
++
++	if (err == BCME_OK) {
++		bytes_written = snprintf(command, total_len, "OK");
++		ANDROID_ERROR(("%s: pktlog filter add success\n", __FUNCTION__));
++	} else {
++		ANDROID_ERROR(("%s: pktlog filter add fail\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	return bytes_written;
++}
++
++static int
++wl_android_pktlog_filter_info(struct net_device *dev, char *command, int total_len)
++{
++	int bytes_written = 0;
++	dhd_pub_t *dhdp = wl_cfg80211_get_dhdp(dev);
++	dhd_pktlog_filter_t *filter;
++	int err = BCME_OK;
++
++	if (!dhdp || !dhdp->pktlog) {
++		DHD_PKT_LOG(("%s(): dhdp=%p pktlog=%p\n",
++			__FUNCTION__, dhdp, (dhdp ? dhdp->pktlog : NULL)));
++		return -EINVAL;
++	}
++
++	filter = dhdp->pktlog->pktlog_filter;
++
++	err = dhd_pktlog_filter_info(filter);
++
++	if (err == BCME_OK) {
++		bytes_written = snprintf(command, total_len, "OK");
++		ANDROID_ERROR(("%s: pktlog filter info success\n", __FUNCTION__));
++	} else {
++		ANDROID_ERROR(("%s: pktlog filter info fail\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	return bytes_written;
++}
++
++static int
++wl_android_pktlog_start(struct net_device *dev, char *command, int total_len)
++{
++	int bytes_written = 0;
++	dhd_pub_t *dhdp = wl_cfg80211_get_dhdp(dev);
++
++	if (!dhdp || !dhdp->pktlog) {
++		DHD_PKT_LOG(("%s(): dhdp=%p pktlog=%p\n",
++			__FUNCTION__, dhdp, (dhdp ? dhdp->pktlog : NULL)));
++		return -EINVAL;
++	}
++
++	if (!dhdp->pktlog->tx_pktlog_ring || !dhdp->pktlog->rx_pktlog_ring) {
++		DHD_PKT_LOG(("%s(): tx_pktlog_ring=%p rx_pktlog_ring=%p\n",
++			__FUNCTION__, dhdp->pktlog->tx_pktlog_ring, dhdp->pktlog->rx_pktlog_ring));
++		return -EINVAL;
++	}
++
++	dhdp->pktlog->tx_pktlog_ring->start = TRUE;
++	dhdp->pktlog->rx_pktlog_ring->start = TRUE;
++
++	bytes_written = snprintf(command, total_len, "OK");
++
++	ANDROID_ERROR(("%s: pktlog start success\n", __FUNCTION__));
++
++	return bytes_written;
++}
++
++static int
++wl_android_pktlog_stop(struct net_device *dev, char *command, int total_len)
++{
++	int bytes_written = 0;
++	dhd_pub_t *dhdp = wl_cfg80211_get_dhdp(dev);
++
++	if (!dhdp || !dhdp->pktlog) {
++		DHD_PKT_LOG(("%s(): dhdp=%p pktlog=%p\n",
++			__FUNCTION__, dhdp, (dhdp ? dhdp->pktlog : NULL)));
++		return -EINVAL;
++	}
++
++	if (!dhdp->pktlog->tx_pktlog_ring || !dhdp->pktlog->rx_pktlog_ring) {
++		DHD_PKT_LOG(("%s(): tx_pktlog_ring=%p rx_pktlog_ring=%p\n",
++			__FUNCTION__, dhdp->pktlog->tx_pktlog_ring, dhdp->pktlog->rx_pktlog_ring));
++		return -EINVAL;
++	}
++
++	dhdp->pktlog->tx_pktlog_ring->start = FALSE;
++	dhdp->pktlog->rx_pktlog_ring->start = FALSE;
++
++	bytes_written = snprintf(command, total_len, "OK");
++
++	ANDROID_ERROR(("%s: pktlog stop success\n", __FUNCTION__));
++
++	return bytes_written;
++}
++
++static int
++wl_android_pktlog_filter_exist(struct net_device *dev, char *command, int total_len)
++{
++	int bytes_written = 0;
++	dhd_pub_t *dhdp = wl_cfg80211_get_dhdp(dev);
++	dhd_pktlog_filter_t *filter;
++	uint32 id;
++	bool exist = FALSE;
++
++	if (!dhdp || !dhdp->pktlog) {
++		DHD_PKT_LOG(("%s(): dhdp=%p pktlog=%p\n",
++			__FUNCTION__, dhdp, (dhdp ? dhdp->pktlog : NULL)));
++		return -EINVAL;
++	}
++
++	filter = dhdp->pktlog->pktlog_filter;
++
++	if (strlen(CMD_PKTLOG_FILTER_EXIST) + 1 > total_len) {
++		return BCME_ERROR;
++	}
++
++	exist = dhd_pktlog_filter_existed(filter, command + strlen(CMD_PKTLOG_FILTER_EXIST) + 1,
++			&id);
++
++	if (exist) {
++		bytes_written = snprintf(command, total_len, "TRUE");
++		ANDROID_ERROR(("%s: pktlog filter pattern id: %d is existed\n", __FUNCTION__, id));
++	} else {
++		bytes_written = snprintf(command, total_len, "FALSE");
++		ANDROID_ERROR(("%s: pktlog filter pattern id: %d is not existed\n", __FUNCTION__, id));
++	}
++
++	return bytes_written;
++}
++#endif /* DHD_PKT_LOGGING */
++
++int wl_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd)
++{
++#define PRIVATE_COMMAND_MAX_LEN	8192
++#define PRIVATE_COMMAND_DEF_LEN	4096
++	int ret = 0;
++	char *command = NULL;
++	int bytes_written = 0;
++	android_wifi_priv_cmd priv_cmd;
++	int buf_size = 0;
++
++	net_os_wake_lock(net);
++
++	if (!capable(CAP_NET_ADMIN)) {
++		ret = -EPERM;
++		goto exit;
++	}
++
++	if (!ifr->ifr_data) {
++		ret = -EINVAL;
++		goto exit;
++	}
++
++#ifdef CONFIG_COMPAT
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 6, 0))
++	if (in_compat_syscall())
++#else
++	if (is_compat_task())
++#endif
++	{
++		compat_android_wifi_priv_cmd compat_priv_cmd;
++		if (copy_from_user(&compat_priv_cmd, ifr->ifr_data,
++			sizeof(compat_android_wifi_priv_cmd))) {
++			ret = -EFAULT;
++			goto exit;
++
++		}
++		priv_cmd.buf = compat_ptr(compat_priv_cmd.buf);
++		priv_cmd.used_len = compat_priv_cmd.used_len;
++		priv_cmd.total_len = compat_priv_cmd.total_len;
++	} else
++#endif /* CONFIG_COMPAT */
++	{
++		if (copy_from_user(&priv_cmd, ifr->ifr_data, sizeof(android_wifi_priv_cmd))) {
++			ret = -EFAULT;
++			goto exit;
++		}
++	}
++	if ((priv_cmd.total_len > PRIVATE_COMMAND_MAX_LEN) || (priv_cmd.total_len < 0)) {
++		ANDROID_ERROR(("%s: buf length invalid:%d\n", __FUNCTION__,
++			priv_cmd.total_len));
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	buf_size = max(priv_cmd.total_len, PRIVATE_COMMAND_DEF_LEN);
++	command = kmalloc((buf_size + 1), GFP_KERNEL);
++
++	if (!command)
++	{
++		ANDROID_ERROR(("%s: failed to allocate memory\n", __FUNCTION__));
++		ret = -ENOMEM;
++		goto exit;
++	}
++	if (copy_from_user(command, priv_cmd.buf, priv_cmd.total_len)) {
++		ret = -EFAULT;
++		goto exit;
++	}
++	command[priv_cmd.total_len] = '\0';
++
++	ANDROID_INFO(("%s: Android private cmd \"%s\" on %s\n", __FUNCTION__, command, ifr->ifr_name));
++
++	bytes_written = wl_handle_private_cmd(net, command, priv_cmd.total_len);
++	if (bytes_written >= 0) {
++		if ((bytes_written == 0) && (priv_cmd.total_len > 0)) {
++			command[0] = '\0';
++		}
++		if (bytes_written >= priv_cmd.total_len) {
++			ANDROID_ERROR(("%s: err. bytes_written:%d >= total_len:%d, buf_size:%d\n",
++				__FUNCTION__, bytes_written, priv_cmd.total_len, buf_size));
++			ret = BCME_BUFTOOSHORT;
++			goto exit;
++		}
++		bytes_written++;
++		priv_cmd.used_len = bytes_written;
++		if (copy_to_user(priv_cmd.buf, command, bytes_written)) {
++			ANDROID_ERROR(("%s: failed to copy data to user buffer\n", __FUNCTION__));
++			ret = -EFAULT;
++		}
++	}
++	else {
++		/* Propagate the error */
++		ret = bytes_written;
++	}
++
++exit:
++	net_os_wake_unlock(net);
++	kfree(command);
++	return ret;
++}
++
++int
++wl_handle_private_cmd(struct net_device *net, char *command, u32 cmd_len)
++{
++	int bytes_written = 0;
++	android_wifi_priv_cmd priv_cmd;
++
++	bzero(&priv_cmd, sizeof(android_wifi_priv_cmd));
++	priv_cmd.total_len = cmd_len;
++
++	if (strnicmp(command, CMD_START, strlen(CMD_START)) == 0) {
++		ANDROID_INFO(("%s, Received regular START command\n", __FUNCTION__));
++#ifdef  BT_OVER_SDIO
++		bytes_written = dhd_net_bus_get(net);
++#else
++		bytes_written = wl_android_wifi_on(net);
++#endif /* BT_OVER_SDIO */
++	}
++	else if (strnicmp(command, CMD_SETFWPATH, strlen(CMD_SETFWPATH)) == 0) {
++		bytes_written = wl_android_set_fwpath(net, command, priv_cmd.total_len);
++	}
++
++	if (!g_wifi_on) {
++		ANDROID_ERROR(("%s: Ignore private cmd \"%s\" - iface is down\n",
++			__FUNCTION__, command));
++		return 0;
++	}
++
++	if (strnicmp(command, CMD_STOP, strlen(CMD_STOP)) == 0) {
++#ifdef  BT_OVER_SDIO
++		bytes_written = dhd_net_bus_put(net);
++#else
++		bytes_written = wl_android_wifi_off(net, FALSE);
++#endif /* BT_OVER_SDIO */
++	}
++#ifdef WL_CFG80211
++	else if (strnicmp(command, CMD_SCAN_ACTIVE, strlen(CMD_SCAN_ACTIVE)) == 0) {
++		wl_cfg80211_set_passive_scan(net, command);
++	}
++	else if (strnicmp(command, CMD_SCAN_PASSIVE, strlen(CMD_SCAN_PASSIVE)) == 0) {
++		wl_cfg80211_set_passive_scan(net, command);
++	}
++#endif
++	else if (strnicmp(command, CMD_RSSI, strlen(CMD_RSSI)) == 0) {
++		bytes_written = wl_android_get_rssi(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_LINKSPEED, strlen(CMD_LINKSPEED)) == 0) {
++		bytes_written = wl_android_get_link_speed(net, command, priv_cmd.total_len);
++	}
++#ifdef PKT_FILTER_SUPPORT
++	else if (strnicmp(command, CMD_RXFILTER_START, strlen(CMD_RXFILTER_START)) == 0) {
++		bytes_written = net_os_enable_packet_filter(net, 1);
++	}
++	else if (strnicmp(command, CMD_RXFILTER_STOP, strlen(CMD_RXFILTER_STOP)) == 0) {
++		bytes_written = net_os_enable_packet_filter(net, 0);
++	}
++	else if (strnicmp(command, CMD_RXFILTER_ADD, strlen(CMD_RXFILTER_ADD)) == 0) {
++		int filter_num = *(command + strlen(CMD_RXFILTER_ADD) + 1) - '0';
++		bytes_written = net_os_rxfilter_add_remove(net, TRUE, filter_num);
++	}
++	else if (strnicmp(command, CMD_RXFILTER_REMOVE, strlen(CMD_RXFILTER_REMOVE)) == 0) {
++		int filter_num = *(command + strlen(CMD_RXFILTER_REMOVE) + 1) - '0';
++		bytes_written = net_os_rxfilter_add_remove(net, FALSE, filter_num);
++	}
++#endif /* PKT_FILTER_SUPPORT */
++	else if (strnicmp(command, CMD_BTCOEXSCAN_START, strlen(CMD_BTCOEXSCAN_START)) == 0) {
++		/* TBD: BTCOEXSCAN-START */
++	}
++	else if (strnicmp(command, CMD_BTCOEXSCAN_STOP, strlen(CMD_BTCOEXSCAN_STOP)) == 0) {
++		/* TBD: BTCOEXSCAN-STOP */
++	}
++	else if (strnicmp(command, CMD_BTCOEXMODE, strlen(CMD_BTCOEXMODE)) == 0) {
++#ifdef WL_CFG80211
++		void *dhdp = wl_cfg80211_get_dhdp(net);
++		bytes_written = wl_cfg80211_set_btcoex_dhcp(net, dhdp, command);
++#else
++#ifdef PKT_FILTER_SUPPORT
++		uint mode = *(command + strlen(CMD_BTCOEXMODE) + 1) - '0';
++
++		if (mode == 1)
++			net_os_enable_packet_filter(net, 0); /* DHCP starts */
++		else
++			net_os_enable_packet_filter(net, 1); /* DHCP ends */
++#endif /* PKT_FILTER_SUPPORT */
++#endif /* WL_CFG80211 */
++	}
++	else if (strnicmp(command, CMD_SETSUSPENDOPT, strlen(CMD_SETSUSPENDOPT)) == 0) {
++		bytes_written = wl_android_set_suspendopt(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_SETSUSPENDMODE, strlen(CMD_SETSUSPENDMODE)) == 0) {
++		bytes_written = wl_android_set_suspendmode(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_MAXDTIM_IN_SUSPEND, strlen(CMD_MAXDTIM_IN_SUSPEND)) == 0) {
++		bytes_written = wl_android_set_max_dtim(net, command, priv_cmd.total_len);
++	}
++#ifdef WL_CFG80211
++	else if (strnicmp(command, CMD_SETBAND, strlen(CMD_SETBAND)) == 0) {
++#ifdef DISABLE_SETBAND
++		bytes_written = BCME_DISABLED;
++#else	/* DISABLE_SETBAND */
++		uint band = *(command + strlen(CMD_SETBAND) + 1) - '0';
++		if (dhd_conf_get_band(dhd_get_pub(net)) >= WLC_BAND_AUTO) {
++			printf("%s: Band is fixed in config.txt\n", __FUNCTION__);
++		} else
++			bytes_written = wl_cfg80211_set_if_band(net, band);
++#endif /* DISABLE_SETBAND */
++	}
++#endif
++	else if (strnicmp(command, CMD_GETBAND, strlen(CMD_GETBAND)) == 0) {
++		bytes_written = wl_android_get_band(net, command, priv_cmd.total_len);
++	}
++#ifdef WL_CFG80211
++	else if (strnicmp(command, CMD_SET_CSA, strlen(CMD_SET_CSA)) == 0) {
++		bytes_written = wl_android_set_csa(net, command, priv_cmd.total_len);
++	} else if (strnicmp(command, CMD_80211_MODE, strlen(CMD_80211_MODE)) == 0) {
++		bytes_written = wl_android_get_80211_mode(net, command, priv_cmd.total_len);
++	} else if (strnicmp(command, CMD_CHANSPEC, strlen(CMD_CHANSPEC)) == 0) {
++		bytes_written = wl_android_get_chanspec(net, command, priv_cmd.total_len);
++	}
++#endif /* WL_CFG80211 */
++	/* CUSTOMER_SET_COUNTRY feature is define for only GGSM model */
++	else if (strnicmp(command, CMD_COUNTRY, strlen(CMD_COUNTRY)) == 0) {
++		/*
++		 * Usage examples:
++		 * DRIVER COUNTRY US
++		 * DRIVER COUNTRY US/7
++		 */
++		char *country_code = command + strlen(CMD_COUNTRY) + 1;
++		char *rev_info_delim = country_code + 2; /* 2 bytes of country code */
++		int revinfo = -1;
++#if defined(DHD_BLOB_EXISTENCE_CHECK)
++		dhd_pub_t *dhdp = wl_cfg80211_get_dhdp(net);
++
++		if (dhdp->is_blob) {
++			revinfo = 0;
++		} else
++#endif /* DHD_BLOB_EXISTENCE_CHECK */
++		if ((rev_info_delim) &&
++			(strnicmp(rev_info_delim, CMD_COUNTRY_DELIMITER,
++			strlen(CMD_COUNTRY_DELIMITER)) == 0) &&
++			(rev_info_delim + 1)) {
++			revinfo  = bcm_atoi(rev_info_delim + 1);
++		}
++		bytes_written = wldev_set_country(net, country_code, true, true, revinfo);
++#ifdef CUSTOMER_HW4_PRIVATE_CMD
++#ifdef FCC_PWR_LIMIT_2G
++		if (wldev_iovar_setint(net, "fccpwrlimit2g", FALSE)) {
++			ANDROID_ERROR(("%s: fccpwrlimit2g deactivation is failed\n", __FUNCTION__));
++		} else {
++			ANDROID_ERROR(("%s: fccpwrlimit2g is deactivated\n", __FUNCTION__));
++		}
++#endif /* FCC_PWR_LIMIT_2G */
++#endif /* CUSTOMER_HW4_PRIVATE_CMD */
++	}
++	else if (strnicmp(command, CMD_DATARATE, strlen(CMD_DATARATE)) == 0) {
++		bytes_written = wl_android_get_datarate(net, command, priv_cmd.total_len);
++	} else if (strnicmp(command, CMD_ASSOC_CLIENTS,	strlen(CMD_ASSOC_CLIENTS)) == 0) {
++		bytes_written = wl_android_get_assoclist(net, command, priv_cmd.total_len);
++	}
++
++#ifdef CUSTOMER_HW4_PRIVATE_CMD
++#ifdef WLTDLS
++	else if (strnicmp(command, CMD_TDLS_RESET, strlen(CMD_TDLS_RESET)) == 0) {
++		bytes_written = wl_android_tdls_reset(net);
++	}
++#endif /* WLTDLS */
++#endif /* CUSTOMER_HW4_PRIVATE_CMD */
++
++#ifdef PNO_SUPPORT
++	else if (strnicmp(command, CMD_PNOSSIDCLR_SET, strlen(CMD_PNOSSIDCLR_SET)) == 0) {
++		bytes_written = dhd_dev_pno_stop_for_ssid(net);
++	}
++#ifndef WL_SCHED_SCAN
++	else if (strnicmp(command, CMD_PNOSETUP_SET, strlen(CMD_PNOSETUP_SET)) == 0) {
++		bytes_written = wl_android_set_pno_setup(net, command, priv_cmd.total_len);
++	}
++#endif /* !WL_SCHED_SCAN */
++	else if (strnicmp(command, CMD_PNOENABLE_SET, strlen(CMD_PNOENABLE_SET)) == 0) {
++		int enable = *(command + strlen(CMD_PNOENABLE_SET) + 1) - '0';
++		bytes_written = (enable)? 0 : dhd_dev_pno_stop_for_ssid(net);
++	}
++	else if (strnicmp(command, CMD_WLS_BATCHING, strlen(CMD_WLS_BATCHING)) == 0) {
++		bytes_written = wls_parse_batching_cmd(net, command, priv_cmd.total_len);
++	}
++#endif /* PNO_SUPPORT */
++	else if (strnicmp(command, CMD_P2P_DEV_ADDR, strlen(CMD_P2P_DEV_ADDR)) == 0) {
++		bytes_written = wl_android_get_p2p_dev_addr(net, command, priv_cmd.total_len);
++	}
++#ifdef WL_CFG80211
++#ifdef WLMESH_CFG80211
++	else if (strnicmp(command, CMD_SAE_SET_PASSWORD, strlen(CMD_SAE_SET_PASSWORD)) == 0) {
++		int skip = strlen(CMD_SAE_SET_PASSWORD) + 1;
++		bytes_written = wl_cfg80211_set_sae_password(net, command + skip,
++			priv_cmd.total_len - skip);
++	}
++	else if (strnicmp(command, CMD_SET_RSDB_MODE, strlen(CMD_SET_RSDB_MODE)) == 0) {
++		bytes_written = wl_android_set_rsdb_mode(net, command, priv_cmd.total_len);
++	}
++#endif
++#endif /* WL_CFG80211 */
++	else if (strnicmp(command, CMD_P2P_SET_NOA, strlen(CMD_P2P_SET_NOA)) == 0) {
++		int skip = strlen(CMD_P2P_SET_NOA) + 1;
++		bytes_written = wl_cfg80211_set_p2p_noa(net, command + skip,
++			priv_cmd.total_len - skip);
++	}
++#ifdef P2P_LISTEN_OFFLOADING
++	else if (strnicmp(command, CMD_P2P_LISTEN_OFFLOAD, strlen(CMD_P2P_LISTEN_OFFLOAD)) == 0) {
++		u8 *sub_command = strchr(command, ' ');
++		bytes_written = wl_cfg80211_p2plo_offload(net, command, sub_command,
++				sub_command ? strlen(sub_command) : 0);
++	}
++#endif /* P2P_LISTEN_OFFLOADING */
++#if !defined WL_ENABLE_P2P_IF
++	else if (strnicmp(command, CMD_P2P_GET_NOA, strlen(CMD_P2P_GET_NOA)) == 0) {
++		bytes_written = wl_cfg80211_get_p2p_noa(net, command, priv_cmd.total_len);
++	}
++#endif /* WL_ENABLE_P2P_IF */
++	else if (strnicmp(command, CMD_P2P_SET_PS, strlen(CMD_P2P_SET_PS)) == 0) {
++		int skip = strlen(CMD_P2P_SET_PS) + 1;
++		bytes_written = wl_cfg80211_set_p2p_ps(net, command + skip,
++			priv_cmd.total_len - skip);
++	}
++	else if (strnicmp(command, CMD_P2P_ECSA, strlen(CMD_P2P_ECSA)) == 0) {
++		int skip = strlen(CMD_P2P_ECSA) + 1;
++		bytes_written = wl_cfg80211_set_p2p_ecsa(net, command + skip,
++			priv_cmd.total_len - skip);
++	}
++	else if (strnicmp(command, CMD_P2P_INC_BW, strlen(CMD_P2P_INC_BW)) == 0) {
++		int skip = strlen(CMD_P2P_INC_BW) + 1;
++		bytes_written = wl_cfg80211_increase_p2p_bw(net,
++				command + skip, priv_cmd.total_len - skip);
++	}
++#ifdef WL_CFG80211
++	else if (strnicmp(command, CMD_SET_AP_WPS_P2P_IE,
++		strlen(CMD_SET_AP_WPS_P2P_IE)) == 0) {
++		int skip = strlen(CMD_SET_AP_WPS_P2P_IE) + 3;
++		bytes_written = wl_cfg80211_set_wps_p2p_ie(net, command + skip,
++			priv_cmd.total_len - skip, *(command + skip - 2) - '0');
++	}
++#ifdef WLFBT
++	else if (strnicmp(command, CMD_GET_FTKEY, strlen(CMD_GET_FTKEY)) == 0) {
++		bytes_written = wl_cfg80211_get_fbt_key(net, command, priv_cmd.total_len);
++	}
++#endif /* WLFBT */
++#endif /* WL_CFG80211 */
++#if defined(WL_SUPPORT_AUTO_CHANNEL)
++	else if (strnicmp(command, CMD_GET_BEST_CHANNELS,
++		strlen(CMD_GET_BEST_CHANNELS)) == 0) {
++		bytes_written = wl_cfg80211_get_best_channels(net, command,
++			priv_cmd.total_len);
++	}
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++#if defined(WL_SUPPORT_AUTO_CHANNEL)
++	else if (strnicmp(command, CMD_SET_HAPD_AUTO_CHANNEL,
++		strlen(CMD_SET_HAPD_AUTO_CHANNEL)) == 0) {
++		int skip = strlen(CMD_SET_HAPD_AUTO_CHANNEL) + 1;
++		bytes_written = wl_android_set_auto_channel(net, (const char*)command+skip, command,
++			priv_cmd.total_len);
++	}
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++#ifdef CUSTOMER_HW4_PRIVATE_CMD
++#ifdef SUPPORT_SET_LPC
++	else if (strnicmp(command, CMD_HAPD_LPC_ENABLED,
++		strlen(CMD_HAPD_LPC_ENABLED)) == 0) {
++		int skip = strlen(CMD_HAPD_LPC_ENABLED) + 3;
++		wl_android_set_lpc(net, (const char*)command+skip);
++	}
++#endif /* SUPPORT_SET_LPC */
++#ifdef SUPPORT_TRIGGER_HANG_EVENT
++	else if (strnicmp(command, CMD_TEST_FORCE_HANG,
++		strlen(CMD_TEST_FORCE_HANG)) == 0) {
++		int skip = strlen(CMD_TEST_FORCE_HANG) + 1;
++		net_os_send_hang_message_reason(net, (const char*)command+skip);
++	}
++#endif /* SUPPORT_TRIGGER_HANG_EVENT */
++	else if (strnicmp(command, CMD_CHANGE_RL, strlen(CMD_CHANGE_RL)) == 0)
++		bytes_written = wl_android_ch_res_rl(net, true);
++	else if (strnicmp(command, CMD_RESTORE_RL, strlen(CMD_RESTORE_RL)) == 0)
++		bytes_written = wl_android_ch_res_rl(net, false);
++#ifdef WL_RELMCAST
++	else if (strnicmp(command, CMD_SET_RMC_ENABLE, strlen(CMD_SET_RMC_ENABLE)) == 0) {
++		int rmc_enable = *(command + strlen(CMD_SET_RMC_ENABLE) + 1) - '0';
++		bytes_written = wl_android_rmc_enable(net, rmc_enable);
++	}
++	else if (strnicmp(command, CMD_SET_RMC_TXRATE, strlen(CMD_SET_RMC_TXRATE)) == 0) {
++		int rmc_txrate;
++		sscanf(command, "%*s %10d", &rmc_txrate);
++		bytes_written = wldev_iovar_setint(net, "rmc_txrate", rmc_txrate * 2);
++	}
++	else if (strnicmp(command, CMD_SET_RMC_ACTPERIOD, strlen(CMD_SET_RMC_ACTPERIOD)) == 0) {
++		int actperiod;
++		sscanf(command, "%*s %10d", &actperiod);
++		bytes_written = wldev_iovar_setint(net, "rmc_actf_time", actperiod);
++	}
++	else if (strnicmp(command, CMD_SET_RMC_IDLEPERIOD, strlen(CMD_SET_RMC_IDLEPERIOD)) == 0) {
++		int acktimeout;
++		sscanf(command, "%*s %10d", &acktimeout);
++		acktimeout *= 1000;
++		bytes_written = wldev_iovar_setint(net, "rmc_acktmo", acktimeout);
++	}
++	else if (strnicmp(command, CMD_SET_RMC_LEADER, strlen(CMD_SET_RMC_LEADER)) == 0) {
++		int skip = strlen(CMD_SET_RMC_LEADER) + 1;
++		bytes_written = wl_android_rmc_set_leader(net, (const char*)command+skip);
++	}
++	else if (strnicmp(command, CMD_SET_RMC_EVENT,
++		strlen(CMD_SET_RMC_EVENT)) == 0) {
++		bytes_written = wl_android_set_rmc_event(net, command, priv_cmd.total_len);
++	}
++#endif /* WL_RELMCAST */
++	else if (strnicmp(command, CMD_GET_SCSCAN, strlen(CMD_GET_SCSCAN)) == 0) {
++		bytes_written = wl_android_get_singlecore_scan(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_SET_SCSCAN, strlen(CMD_SET_SCSCAN)) == 0) {
++		bytes_written = wl_android_set_singlecore_scan(net, command, priv_cmd.total_len);
++	}
++#ifdef TEST_TX_POWER_CONTROL
++	else if (strnicmp(command, CMD_TEST_SET_TX_POWER,
++		strlen(CMD_TEST_SET_TX_POWER)) == 0) {
++		int skip = strlen(CMD_TEST_SET_TX_POWER) + 1;
++		wl_android_set_tx_power(net, (const char*)command+skip);
++	}
++	else if (strnicmp(command, CMD_TEST_GET_TX_POWER,
++		strlen(CMD_TEST_GET_TX_POWER)) == 0) {
++		wl_android_get_tx_power(net, command, priv_cmd.total_len);
++	}
++#endif /* TEST_TX_POWER_CONTROL */
++	else if (strnicmp(command, CMD_SARLIMIT_TX_CONTROL,
++		strlen(CMD_SARLIMIT_TX_CONTROL)) == 0) {
++		int skip = strlen(CMD_SARLIMIT_TX_CONTROL) + 1;
++		wl_android_set_sarlimit_txctrl(net, (const char*)command+skip);
++	}
++#endif /* CUSTOMER_HW4_PRIVATE_CMD */
++	else if (strnicmp(command, CMD_HAPD_MAC_FILTER, strlen(CMD_HAPD_MAC_FILTER)) == 0) {
++		int skip = strlen(CMD_HAPD_MAC_FILTER) + 1;
++		wl_android_set_mac_address_filter(net, command+skip);
++	}
++	else if (strnicmp(command, CMD_SETROAMMODE, strlen(CMD_SETROAMMODE)) == 0)
++		bytes_written = wl_android_set_roam_mode(net, command, priv_cmd.total_len);
++#if defined(BCMFW_ROAM_ENABLE)
++	else if (strnicmp(command, CMD_SET_ROAMPREF, strlen(CMD_SET_ROAMPREF)) == 0) {
++		bytes_written = wl_android_set_roampref(net, command, priv_cmd.total_len);
++	}
++#endif /* BCMFW_ROAM_ENABLE */
++#ifdef WL_CFG80211
++	else if (strnicmp(command, CMD_MIRACAST, strlen(CMD_MIRACAST)) == 0)
++		bytes_written = wl_android_set_miracast(net, command, priv_cmd.total_len);
++#ifdef WL11ULB
++	else if (strnicmp(command, CMD_ULB_MODE, strlen(CMD_ULB_MODE)) == 0)
++		bytes_written = wl_android_set_ulb_mode(net, command, priv_cmd.total_len);
++	else if (strnicmp(command, CMD_ULB_BW, strlen(CMD_ULB_BW)) == 0)
++		bytes_written = wl_android_set_ulb_bw(net, command, priv_cmd.total_len);
++#endif /* WL11ULB */
++	else if (strnicmp(command, CMD_SETIBSSBEACONOUIDATA, strlen(CMD_SETIBSSBEACONOUIDATA)) == 0)
++		bytes_written = wl_android_set_ibss_beacon_ouidata(net,
++		command, priv_cmd.total_len);
++#endif
++	else if (strnicmp(command, CMD_KEEP_ALIVE, strlen(CMD_KEEP_ALIVE)) == 0) {
++		int skip = strlen(CMD_KEEP_ALIVE) + 1;
++		bytes_written = wl_keep_alive_set(net, command + skip, priv_cmd.total_len - skip);
++	}
++#ifdef WL_CFG80211
++	else if (strnicmp(command, CMD_ROAM_OFFLOAD, strlen(CMD_ROAM_OFFLOAD)) == 0) {
++		int enable = *(command + strlen(CMD_ROAM_OFFLOAD) + 1) - '0';
++		bytes_written = wl_cfg80211_enable_roam_offload(net, enable);
++	}
++#endif
++#if defined(WL_VIRTUAL_APSTA)
++	else if (strnicmp(command, CMD_INTERFACE_CREATE, strlen(CMD_INTERFACE_CREATE)) == 0) {
++		char *name = (command + strlen(CMD_INTERFACE_CREATE) +1);
++		ANDROID_INFO(("Creating %s interface\n", name));
++		bytes_written = wl_cfg80211_interface_create(net, name);
++	}
++	else if (strnicmp(command, CMD_INTERFACE_DELETE, strlen(CMD_INTERFACE_DELETE)) == 0) {
++		char *name = (command + strlen(CMD_INTERFACE_DELETE) +1);
++		ANDROID_INFO(("Deleteing %s interface\n", name));
++		bytes_written = wl_cfg80211_interface_delete(net, name);
++	}
++#endif /* defined (WL_VIRTUAL_APSTA) */
++	else if (strnicmp(command, CMD_GET_LINK_STATUS, strlen(CMD_GET_LINK_STATUS)) == 0) {
++		bytes_written = wl_android_get_link_status(net, command, priv_cmd.total_len);
++	}
++#ifdef P2PRESP_WFDIE_SRC
++	else if (strnicmp(command, CMD_P2P_SET_WFDIE_RESP,
++		strlen(CMD_P2P_SET_WFDIE_RESP)) == 0) {
++		int mode = *(command + strlen(CMD_P2P_SET_WFDIE_RESP) + 1) - '0';
++		bytes_written = wl_android_set_wfdie_resp(net, mode);
++	} else if (strnicmp(command, CMD_P2P_GET_WFDIE_RESP,
++		strlen(CMD_P2P_GET_WFDIE_RESP)) == 0) {
++		bytes_written = wl_android_get_wfdie_resp(net, command, priv_cmd.total_len);
++	}
++#endif /* P2PRESP_WFDIE_SRC */
++#ifdef WL_CFG80211
++	else if (strnicmp(command, CMD_DFS_AP_MOVE, strlen(CMD_DFS_AP_MOVE)) == 0) {
++		char *data = (command + strlen(CMD_DFS_AP_MOVE) +1);
++		bytes_written = wl_cfg80211_dfs_ap_move(net, data, command, priv_cmd.total_len);
++	}
++#endif
++#ifdef WBTEXT
++	else if (strnicmp(command, CMD_WBTEXT_ENABLE, strlen(CMD_WBTEXT_ENABLE)) == 0) {
++		bytes_written = wl_android_wbtext(net, command, priv_cmd.total_len);
++	}
++#ifdef WL_CFG80211
++	else if (strnicmp(command, CMD_WBTEXT_PROFILE_CONFIG,
++			strlen(CMD_WBTEXT_PROFILE_CONFIG)) == 0) {
++		char *data = (command + strlen(CMD_WBTEXT_PROFILE_CONFIG) + 1);
++		bytes_written = wl_cfg80211_wbtext_config(net, data, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_WBTEXT_WEIGHT_CONFIG,
++			strlen(CMD_WBTEXT_WEIGHT_CONFIG)) == 0) {
++		char *data = (command + strlen(CMD_WBTEXT_WEIGHT_CONFIG) + 1);
++		bytes_written = wl_cfg80211_wbtext_weight_config(net, data,
++				command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_WBTEXT_TABLE_CONFIG,
++			strlen(CMD_WBTEXT_TABLE_CONFIG)) == 0) {
++		char *data = (command + strlen(CMD_WBTEXT_TABLE_CONFIG) + 1);
++		bytes_written = wl_cfg80211_wbtext_table_config(net, data,
++				command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_WBTEXT_DELTA_CONFIG,
++			strlen(CMD_WBTEXT_DELTA_CONFIG)) == 0) {
++		char *data = (command + strlen(CMD_WBTEXT_DELTA_CONFIG) + 1);
++		bytes_written = wl_cfg80211_wbtext_delta_config(net, data,
++				command, priv_cmd.total_len);
++	}
++#endif
++	else if (strnicmp(command, CMD_WBTEXT_BTM_TIMER_THRESHOLD,
++			strlen(CMD_WBTEXT_BTM_TIMER_THRESHOLD)) == 0) {
++		bytes_written = wl_cfg80211_wbtext_btm_timer_threshold(net, command,
++			priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_WBTEXT_BTM_DELTA,
++			strlen(CMD_WBTEXT_BTM_DELTA)) == 0) {
++		bytes_written = wl_cfg80211_wbtext_btm_delta(net, command,
++			priv_cmd.total_len);
++	}
++#endif /* WBTEXT */
++#ifdef SET_RPS_CPUS
++	else if (strnicmp(command, CMD_RPSMODE, strlen(CMD_RPSMODE)) == 0) {
++		bytes_written = wl_android_set_rps_cpus(net, command, priv_cmd.total_len);
++	}
++#endif /* SET_RPS_CPUS */
++#ifdef WLWFDS
++	else if (strnicmp(command, CMD_ADD_WFDS_HASH, strlen(CMD_ADD_WFDS_HASH)) == 0) {
++		bytes_written = wl_android_set_wfds_hash(net, command, priv_cmd.total_len, 1);
++	}
++	else if (strnicmp(command, CMD_DEL_WFDS_HASH, strlen(CMD_DEL_WFDS_HASH)) == 0) {
++		bytes_written = wl_android_set_wfds_hash(net, command, priv_cmd.total_len, 0);
++	}
++#endif /* WLWFDS */
++#ifdef BT_WIFI_HANDOVER
++	else if (strnicmp(command, CMD_TBOW_TEARDOWN, strlen(CMD_TBOW_TEARDOWN)) == 0) {
++	    bytes_written = wl_tbow_teardown(net, command, priv_cmd.total_len);
++	}
++#endif /* BT_WIFI_HANDOVER */
++#ifdef CUSTOMER_HW4_PRIVATE_CMD
++#ifdef FCC_PWR_LIMIT_2G
++	else if (strnicmp(command, CMD_GET_FCC_PWR_LIMIT_2G,
++		strlen(CMD_GET_FCC_PWR_LIMIT_2G)) == 0) {
++		bytes_written = wl_android_get_fcc_pwr_limit_2g(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_SET_FCC_PWR_LIMIT_2G,
++		strlen(CMD_SET_FCC_PWR_LIMIT_2G)) == 0) {
++		bytes_written = wl_android_set_fcc_pwr_limit_2g(net, command, priv_cmd.total_len);
++	}
++#endif /* FCC_PWR_LIMIT_2G */
++	else if (strnicmp(command, CMD_GET_STA_INFO, strlen(CMD_GET_STA_INFO)) == 0) {
++		bytes_written = wl_cfg80211_get_sta_info(net, command, priv_cmd.total_len);
++	}
++#endif /* CUSTOMER_HW4_PRIVATE_CMD */
++	else if (strnicmp(command, CMD_MURX_BFE_CAP,
++			strlen(CMD_MURX_BFE_CAP)) == 0) {
++#if defined(BCM4359_CHIP) && defined(WL_CFG80211)
++		uint val = *(command + strlen(CMD_MURX_BFE_CAP) + 1) - '0';
++		bytes_written = wl_android_murx_bfe_cap(net, val);
++#else
++		return BCME_UNSUPPORTED;
++#endif /* BCM4359_CHIP */
++	}
++#ifdef SUPPORT_AP_HIGHER_BEACONRATE
++	else if (strnicmp(command, CMD_GET_AP_BASICRATE, strlen(CMD_GET_AP_BASICRATE)) == 0) {
++		bytes_written = wl_android_get_ap_basicrate(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_SET_AP_BEACONRATE, strlen(CMD_SET_AP_BEACONRATE)) == 0) {
++		bytes_written = wl_android_set_ap_beaconrate(net, command);
++	}
++#endif /* SUPPORT_AP_HIGHER_BEACONRATE */
++#ifdef SUPPORT_AP_RADIO_PWRSAVE
++	else if (strnicmp(command, CMD_SET_AP_RPS_PARAMS, strlen(CMD_SET_AP_RPS_PARAMS)) == 0) {
++		bytes_written = wl_android_set_ap_rps_params(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_SET_AP_RPS, strlen(CMD_SET_AP_RPS)) == 0) {
++		bytes_written = wl_android_set_ap_rps(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_GET_AP_RPS, strlen(CMD_GET_AP_RPS)) == 0) {
++		bytes_written = wl_android_get_ap_rps(net, command, priv_cmd.total_len);
++	}
++#endif /* SUPPORT_AP_RADIO_PWRSAVE */
++#ifdef SUPPORT_RSSI_LOGGING
++	else if (strnicmp(command, CMD_SET_RSSI_LOGGING, strlen(CMD_SET_RSSI_LOGGING)) == 0) {
++		bytes_written = wl_android_set_rssi_logging(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_GET_RSSI_LOGGING, strlen(CMD_GET_RSSI_LOGGING)) == 0) {
++		bytes_written = wl_android_get_rssi_logging(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_GET_RSSI_PER_ANT, strlen(CMD_GET_RSSI_PER_ANT)) == 0) {
++		bytes_written = wl_android_get_rssi_per_ant(net, command, priv_cmd.total_len);
++	}
++#endif /* SUPPORT_RSSI_LOGGING */
++#if defined(DHD_ENABLE_BIGDATA_LOGGING)
++	else if (strnicmp(command, CMD_GET_BSS_INFO, strlen(CMD_GET_BSS_INFO)) == 0) {
++		bytes_written = wl_cfg80211_get_bss_info(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_GET_ASSOC_REJECT_INFO, strlen(CMD_GET_ASSOC_REJECT_INFO))
++			== 0) {
++		bytes_written = wl_cfg80211_get_connect_failed_status(net, command,
++				priv_cmd.total_len);
++	}
++#endif /* DHD_ENABLE_BIGDATA_LOGGING */
++#if defined(SUPPORT_RANDOM_MAC_SCAN)
++	else if (strnicmp(command, ENABLE_RANDOM_MAC, strlen(ENABLE_RANDOM_MAC)) == 0) {
++		bytes_written = wl_cfg80211_set_random_mac(net, TRUE);
++	} else if (strnicmp(command, DISABLE_RANDOM_MAC, strlen(DISABLE_RANDOM_MAC)) == 0) {
++		bytes_written = wl_cfg80211_set_random_mac(net, FALSE);
++	}
++#endif /* SUPPORT_RANDOM_MAC_SCAN */
++#ifdef WL_NATOE
++	else if (strnicmp(command, CMD_NATOE, strlen(CMD_NATOE)) == 0) {
++		bytes_written = wl_android_process_natoe_cmd(net, command,
++				priv_cmd.total_len);
++	}
++#endif /* WL_NATOE */
++#ifdef CONNECTION_STATISTICS
++	else if (strnicmp(command, CMD_GET_CONNECTION_STATS,
++		strlen(CMD_GET_CONNECTION_STATS)) == 0) {
++		bytes_written = wl_android_get_connection_stats(net, command,
++			priv_cmd.total_len);
++	}
++#endif
++#ifdef DHD_LOG_DUMP
++	else if (strnicmp(command, CMD_NEW_DEBUG_PRINT_DUMP,
++		strlen(CMD_NEW_DEBUG_PRINT_DUMP)) == 0) {
++		dhd_pub_t *dhdp = wl_cfg80211_get_dhdp(net);
++		dhd_schedule_log_dump(dhdp);
++#if defined(DHD_DEBUG) && defined(BCMPCIE) && defined(DHD_FW_COREDUMP)
++		dhdp->memdump_type = DUMP_TYPE_BY_SYSDUMP;
++		dhd_bus_mem_dump(dhdp);
++#endif /* DHD_DEBUG && BCMPCIE && DHD_FW_COREDUMP */
++#ifdef DHD_PKT_LOGGING
++		dhd_schedule_pktlog_dump(dhdp);
++#endif /* DHD_PKT_LOGGING */
++	}
++#endif /* DHD_LOG_DUMP */
++#ifdef SET_PCIE_IRQ_CPU_CORE
++	else if (strnicmp(command, CMD_PCIE_IRQ_CORE, strlen(CMD_PCIE_IRQ_CORE)) == 0) {
++		int set = *(command + strlen(CMD_PCIE_IRQ_CORE) + 1) - '0';
++		wl_android_set_irq_cpucore(net, set);
++	}
++#endif /* SET_PCIE_IRQ_CPU_CORE */
++#if defined(DHD_HANG_SEND_UP_TEST)
++	else if (strnicmp(command, CMD_MAKE_HANG, strlen(CMD_MAKE_HANG)) == 0) {
++		int skip = strlen(CMD_MAKE_HANG) + 1;
++		wl_android_make_hang_with_reason(net, (const char*)command+skip);
++	}
++#endif /* DHD_HANG_SEND_UP_TEST */
++#ifdef SUPPORT_LQCM
++	else if (strnicmp(command, CMD_SET_LQCM_ENABLE, strlen(CMD_SET_LQCM_ENABLE)) == 0) {
++		int lqcm_enable = *(command + strlen(CMD_SET_LQCM_ENABLE) + 1) - '0';
++		bytes_written = wl_android_lqcm_enable(net, lqcm_enable);
++	}
++	else if (strnicmp(command, CMD_GET_LQCM_REPORT,
++		strlen(CMD_GET_LQCM_REPORT)) == 0) {
++		bytes_written = wl_android_get_lqcm_report(net, command,
++		priv_cmd.total_len);
++	}
++#endif
++	else if (strnicmp(command, CMD_GET_SNR, strlen(CMD_GET_SNR)) == 0) {
++		bytes_written = wl_android_get_snr(net, command, priv_cmd.total_len);
++	}
++#ifdef WLADPS_PRIVATE_CMD
++	else if (strnicmp(command, CMD_SET_ADPS, strlen(CMD_SET_ADPS)) == 0) {
++		int skip = strlen(CMD_SET_ADPS) + 1;
++		bytes_written = wl_android_set_adps_mode(net, (const char*)command+skip);
++	}
++	else if (strnicmp(command, CMD_GET_ADPS, strlen(CMD_GET_ADPS)) == 0) {
++		bytes_written = wl_android_get_adps_mode(net, command, priv_cmd.total_len);
++	}
++#endif /* WLADPS_PRIVATE_CMD */
++#ifdef DHD_PKT_LOGGING
++	else if (strnicmp(command, CMD_PKTLOG_FILTER_ENABLE,
++		strlen(CMD_PKTLOG_FILTER_ENABLE)) == 0) {
++		bytes_written = wl_android_pktlog_filter_enable(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_PKTLOG_FILTER_DISABLE,
++		strlen(CMD_PKTLOG_FILTER_DISABLE)) == 0) {
++		bytes_written = wl_android_pktlog_filter_disable(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_PKTLOG_FILTER_PATTERN_ENABLE,
++		strlen(CMD_PKTLOG_FILTER_PATTERN_ENABLE)) == 0) {
++		bytes_written =
++			wl_android_pktlog_filter_pattern_enable(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_PKTLOG_FILTER_PATTERN_DISABLE,
++		strlen(CMD_PKTLOG_FILTER_PATTERN_DISABLE)) == 0) {
++		bytes_written =
++			wl_android_pktlog_filter_pattern_disable(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_PKTLOG_FILTER_ADD, strlen(CMD_PKTLOG_FILTER_ADD)) == 0) {
++		bytes_written = wl_android_pktlog_filter_add(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_PKTLOG_FILTER_INFO, strlen(CMD_PKTLOG_FILTER_INFO)) == 0) {
++		bytes_written = wl_android_pktlog_filter_info(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_PKTLOG_START, strlen(CMD_PKTLOG_START)) == 0) {
++		bytes_written = wl_android_pktlog_start(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_PKTLOG_STOP, strlen(CMD_PKTLOG_STOP)) == 0) {
++		bytes_written = wl_android_pktlog_stop(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_PKTLOG_FILTER_EXIST, strlen(CMD_PKTLOG_FILTER_EXIST)) == 0) {
++		bytes_written = wl_android_pktlog_filter_exist(net, command, priv_cmd.total_len);
++	}
++#endif /* DHD_PKT_LOGGING */
++#if defined(STAT_REPORT)
++	else if (strnicmp(command, CMD_STAT_REPORT_GET_START,
++		strlen(CMD_STAT_REPORT_GET_START)) == 0) {
++		bytes_written = wl_android_stat_report_get_start(net, command, priv_cmd.total_len);
++	} else if (strnicmp(command, CMD_STAT_REPORT_GET_NEXT,
++		strlen(CMD_STAT_REPORT_GET_NEXT)) == 0) {
++		bytes_written = wl_android_stat_report_get_next(net, command, priv_cmd.total_len);
++	}
++#endif /* STAT_REPORT */
++	else if (wl_android_ext_priv_cmd(net, command, priv_cmd.total_len, &bytes_written) == 0) {
++	}
++	else {
++		ANDROID_ERROR(("Unknown PRIVATE command %s - ignored\n", command));
++		bytes_written = scnprintf(command, sizeof("FAIL"), "FAIL");
++	}
++
++	return bytes_written;
++}
++
++int wl_android_init(void)
++{
++	int ret = 0;
++
++#if defined(ENABLE_INSMOD_NO_FW_LOAD) || defined(BUS_POWER_RESTORE)
++	dhd_download_fw_on_driverload = FALSE;
++#endif /* ENABLE_INSMOD_NO_FW_LOAD */
++	if (!iface_name[0]) {
++		memset(iface_name, 0, IFNAMSIZ);
++		bcm_strncpy_s(iface_name, IFNAMSIZ, "wlan", IFNAMSIZ);
++	}
++
++#ifdef WL_RELMCAST
++	wl_netlink_init();
++#endif /* WL_RELMCAST */
++
++	return ret;
++}
++
++int wl_android_exit(void)
++{
++	int ret = 0;
++	struct io_cfg *cur, *q;
++
++#ifdef WL_RELMCAST
++	wl_netlink_deinit();
++#endif
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	list_for_each_entry_safe(cur, q, &miracast_resume_list, list) {
++		list_del(&cur->list);
++		kfree(cur);
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++	return ret;
++}
++
++void wl_android_post_init(void)
++{
++
++#ifdef ENABLE_4335BT_WAR
++	bcm_bt_unlock(lock_cookie_wifi);
++	printk("%s: btlock released\n", __FUNCTION__);
++#endif /* ENABLE_4335BT_WAR */
++
++	if (!dhd_download_fw_on_driverload)
++		g_wifi_on = FALSE;
++}
++
++
++
++int wl_fatal_error(void * wl, int rc)
++{
++	return FALSE;
++}
++
++#if defined(BT_OVER_SDIO)
++void
++wl_android_set_wifi_on_flag(bool enable)
++{
++	g_wifi_on = enable;
++}
++#endif /* BT_OVER_SDIO */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_android.h b/module_drivers/drivers/net/wireless/bcmdhd/wl_android.h
+new file mode 100644
+index 000000000..745d006b8
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_android.h
+@@ -0,0 +1,311 @@
++/*
++ * Linux cfg80211 driver - Android related functions
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_android.h 607319 2015-12-18 14:16:55Z $
++ */
++
++#ifndef _wl_android_
++#define _wl_android_
++
++#include <linux/module.h>
++#include <linux/netdevice.h>
++#include <wldev_common.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++
++/* If any feature uses the Generic Netlink Interface, put it here to enable WL_GENL
++ * automatically
++ */
++#if defined(BT_WIFI_HANDOVER)
++#define WL_GENL
++#endif
++
++
++
++typedef struct _android_wifi_priv_cmd {
++    char *buf;
++    int used_len;
++    int total_len;
++} android_wifi_priv_cmd;
++
++#ifdef CONFIG_COMPAT
++typedef struct _compat_android_wifi_priv_cmd {
++    compat_caddr_t buf;
++    int used_len;
++    int total_len;
++} compat_android_wifi_priv_cmd;
++#endif /* CONFIG_COMPAT */
++
++/**
++ * Android platform dependent functions, feel free to add Android specific functions here
++ * (save the macros in dhd). Please do NOT declare functions that are NOT exposed to dhd
++ * or cfg, define them as static in wl_android.c
++ */
++
++/* message levels */
++#define ANDROID_ERROR_LEVEL	(1 << 0)
++#define ANDROID_TRACE_LEVEL	(1 << 1)
++#define ANDROID_INFO_LEVEL	(1 << 2)
++#define ANDROID_SCAN_LEVEL	(1 << 3)
++#define ANDROID_DBG_LEVEL	(1 << 4)
++#define ANDROID_MSG_LEVEL	(1 << 0)
++
++#define WL_MSG(name, arg1, args...) \
++	do { \
++		if (android_msg_level & ANDROID_MSG_LEVEL) { \
++			printk(KERN_ERR "[dhd-%s] %s : " arg1, name, __func__, ## args); \
++		} \
++	} while (0)
++
++#define WL_MSG_PRINT_RATE_LIMIT_PERIOD 1000000000u /* 1s in units of ns */
++#define WL_MSG_RLMT(name, cmp, size, arg1, args...) \
++do {	\
++	if (android_msg_level & ANDROID_MSG_LEVEL) {	\
++		static uint64 __err_ts = 0; \
++		static uint32 __err_cnt = 0; \
++		uint64 __cur_ts = 0; \
++		static uint8 static_tmp[size]; \
++		__cur_ts = local_clock(); \
++		if (__err_ts == 0 || (__cur_ts > __err_ts && \
++		(__cur_ts - __err_ts > WL_MSG_PRINT_RATE_LIMIT_PERIOD)) || \
++		memcmp(&static_tmp, cmp, size)) { \
++			__err_ts = __cur_ts; \
++			memcpy(static_tmp, cmp, size); \
++			printk(KERN_ERR "[dhd-%s] %s : [%u times] " arg1, \
++				name, __func__, __err_cnt, ## args); \
++			__err_cnt = 0; \
++		} else { \
++			++__err_cnt; \
++		} \
++	}	\
++} while (0)
++
++/**
++ * wl_android_init will be called from module init function (dhd_module_init now), similarly
++ * wl_android_exit will be called from module exit function (dhd_module_cleanup now)
++ */
++int wl_android_init(void);
++int wl_android_exit(void);
++void wl_android_post_init(void);
++int wl_android_wifi_on(struct net_device *dev);
++int wl_android_wifi_off(struct net_device *dev, bool on_failure);
++int wl_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd);
++int wl_handle_private_cmd(struct net_device *net, char *command, u32 cmd_len);
++
++s32 wl_netlink_send_msg(int pid, int type, int seq, const void *data, size_t size);
++#ifdef WL_EXT_IAPSTA
++int wl_ext_iapsta_attach_netdev(struct net_device *net, int ifidx, uint8 bssidx);
++int wl_ext_iapsta_attach_name(struct net_device *net, int ifidx);
++int wl_ext_iapsta_dettach_netdev(struct net_device *net, int ifidx);
++int wl_ext_iapsta_update_net_device(struct net_device *net, int ifidx);
++int wl_ext_iapsta_alive_preinit(struct net_device *dev);
++int wl_ext_iapsta_alive_postinit(struct net_device *dev);
++int wl_ext_iapsta_attach(dhd_pub_t *pub);
++void wl_ext_iapsta_dettach(dhd_pub_t *pub);
++#ifdef WL_CFG80211
++u32 wl_ext_iapsta_update_channel(dhd_pub_t *dhd, struct net_device *dev, u32 channel);
++void wl_ext_iapsta_update_iftype(struct net_device *net, int ifidx, int wl_iftype);
++void wl_ext_iapsta_ifadding(struct net_device *net, int ifidx);
++bool wl_ext_iapsta_mesh_creating(struct net_device *net);
++#endif
++extern int op_mode;
++#endif
++typedef struct bcol_gtk_para {
++	int enable;
++	int ptk_len;
++	char ptk[64];
++	char replay[8];
++} bcol_gtk_para_t;
++#define ACS_FW_BIT		(1<<0)
++#define ACS_DRV_BIT		(1<<1)
++#if defined(WL_EXT_IAPSTA) || defined(USE_IW)
++typedef enum WL_EVENT_PRIO {
++	PRIO_EVENT_IAPSTA,
++	PRIO_EVENT_ESCAN,
++	PRIO_EVENT_WEXT
++}wl_event_prio_t;
++s32 wl_ext_event_attach(struct net_device *dev, dhd_pub_t *dhdp);
++void wl_ext_event_dettach(dhd_pub_t *dhdp);
++int wl_ext_event_attach_netdev(struct net_device *net, int ifidx, uint8 bssidx);
++int wl_ext_event_dettach_netdev(struct net_device *net, int ifidx);
++int wl_ext_event_register(struct net_device *dev, dhd_pub_t *dhd,
++	uint32 event, void *cb_func, void *data, wl_event_prio_t prio);
++void wl_ext_event_deregister(struct net_device *dev, dhd_pub_t *dhd,
++	uint32 event, void *cb_func);
++void wl_ext_event_send(void *params, const wl_event_msg_t * e, void *data);
++#endif
++int wl_ext_autochannel(struct net_device *dev, uint acs, uint32 band);
++int wl_android_ext_priv_cmd(struct net_device *net, char *command, int total_len,
++	int *bytes_written);
++void wl_ext_get_sec(struct net_device *dev, int ifmode, char *sec, int total_len);
++bool wl_ext_check_scan(struct net_device *dev, dhd_pub_t *dhdp);
++#if defined(WL_CFG80211) || defined(WL_ESCAN)
++void wl_ext_user_sync(struct dhd_pub *dhd, int ifidx, bool lock);
++bool wl_ext_event_complete(struct dhd_pub *dhd, int ifidx);
++#endif
++enum wl_ext_status {
++	WL_EXT_STATUS_DISCONNECTING = 0,
++	WL_EXT_STATUS_DISCONNECTED,
++	WL_EXT_STATUS_SCAN,
++	WL_EXT_STATUS_CONNECTING,
++	WL_EXT_STATUS_CONNECTED,
++	WL_EXT_STATUS_ADD_KEY,
++	WL_EXT_STATUS_AP_ENABLED,
++	WL_EXT_STATUS_DELETE_STA,
++	WL_EXT_STATUS_STA_DISCONNECTED,
++	WL_EXT_STATUS_STA_CONNECTED,
++	WL_EXT_STATUS_AP_DISABLED
++};
++typedef struct wl_conn_info {
++	uint8 bssidx;
++	wlc_ssid_t ssid;
++	struct ether_addr bssid;
++	uint16 channel;
++} wl_conn_info_t;
++#if defined(WL_WIRELESS_EXT)
++s32 wl_ext_connect(struct net_device *dev, wl_conn_info_t *conn_info);
++#endif /* defined(WL_WIRELESS_EXT) */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
++#define strnicmp(str1, str2, len) strncasecmp((str1), (str2), (len))
++#endif
++
++/* hostap mac mode */
++#define MACLIST_MODE_DISABLED   0
++#define MACLIST_MODE_DENY       1
++#define MACLIST_MODE_ALLOW      2
++
++/* max number of assoc list */
++#define MAX_NUM_OF_ASSOCLIST    64
++
++/* Bandwidth */
++#define WL_CH_BANDWIDTH_20MHZ 20
++#define WL_CH_BANDWIDTH_40MHZ 40
++#define WL_CH_BANDWIDTH_80MHZ 80
++/* max number of mac filter list
++ * restrict max number to 10 as maximum cmd string size is 255
++ */
++#define MAX_NUM_MAC_FILT        10
++#define	WL_GET_BAND(ch)	(((uint)(ch) <= CH_MAX_2G_CHANNEL) ?	\
++	WLC_BAND_2G : WLC_BAND_5G)
++
++int wl_android_set_ap_mac_list(struct net_device *dev, int macmode, struct maclist *maclist);
++
++/* terence:
++ * BSSCACHE: Cache bss list
++ * RSSAVG: Average RSSI of BSS list
++ * RSSIOFFSET: RSSI offset
++ * SORT_BSS_BY_RSSI: Sort BSS by RSSI
++ */
++//#define BSSCACHE
++//#define RSSIAVG
++//#define RSSIOFFSET
++//#define RSSIOFFSET_NEW
++//#define SORT_BSS_BY_RSSI
++
++#define RSSI_MAXVAL -2
++#define RSSI_MINVAL -200
++
++#if defined(ESCAN_RESULT_PATCH)
++#define REPEATED_SCAN_RESULT_CNT	2
++#else
++#define REPEATED_SCAN_RESULT_CNT	1
++#endif
++
++#if defined(RSSIAVG) || defined(RSSIOFFSET)
++extern int g_wifi_on;
++#endif
++
++#if defined(RSSIAVG)
++#define RSSIAVG_LEN (4*REPEATED_SCAN_RESULT_CNT)
++#define RSSICACHE_TIMEOUT 15
++
++typedef struct wl_rssi_cache {
++	struct wl_rssi_cache *next;
++	int dirty;
++	struct osl_timespec tv;
++	struct ether_addr BSSID;
++	int16 RSSI[RSSIAVG_LEN];
++} wl_rssi_cache_t;
++
++typedef struct wl_rssi_cache_ctrl {
++	wl_rssi_cache_t *m_cache_head;
++} wl_rssi_cache_ctrl_t;
++
++void wl_free_rssi_cache(wl_rssi_cache_ctrl_t *rssi_cache_ctrl);
++void wl_delete_dirty_rssi_cache(wl_rssi_cache_ctrl_t *rssi_cache_ctrl);
++void wl_delete_disconnected_rssi_cache(wl_rssi_cache_ctrl_t *rssi_cache_ctrl, u8 *bssid);
++void wl_reset_rssi_cache(wl_rssi_cache_ctrl_t *rssi_cache_ctrl);
++void wl_update_rssi_cache(wl_rssi_cache_ctrl_t *rssi_cache_ctrl, wl_scan_results_t *ss_list);
++int wl_update_connected_rssi_cache(struct net_device *net, wl_rssi_cache_ctrl_t *rssi_cache_ctrl, int *rssi_avg);
++int16 wl_get_avg_rssi(wl_rssi_cache_ctrl_t *rssi_cache_ctrl, void *addr);
++#endif
++
++#if defined(RSSIOFFSET)
++#define RSSI_OFFSET	5
++#if defined(RSSIOFFSET_NEW)
++#define RSSI_OFFSET_MAXVAL -80
++#define RSSI_OFFSET_MINVAL -94
++#define RSSI_OFFSET_INTVAL ((RSSI_OFFSET_MAXVAL-RSSI_OFFSET_MINVAL)/RSSI_OFFSET)
++#endif
++#define BCM4330_CHIP_ID		0x4330
++#define BCM4330B2_CHIP_REV      4
++int wl_update_rssi_offset(struct net_device *net, int rssi);
++#endif
++
++#if defined(BSSCACHE)
++#define BSSCACHE_TIMEOUT	15
++
++typedef struct wl_bss_cache {
++	struct wl_bss_cache *next;
++	int dirty;
++	struct osl_timespec tv;
++	wl_scan_results_t results;
++} wl_bss_cache_t;
++
++typedef struct wl_bss_cache_ctrl {
++	wl_bss_cache_t *m_cache_head;
++} wl_bss_cache_ctrl_t;
++
++void wl_free_bss_cache(wl_bss_cache_ctrl_t *bss_cache_ctrl);
++void wl_delete_dirty_bss_cache(wl_bss_cache_ctrl_t *bss_cache_ctrl);
++void wl_delete_disconnected_bss_cache(wl_bss_cache_ctrl_t *bss_cache_ctrl, u8 *bssid);
++void wl_reset_bss_cache(wl_bss_cache_ctrl_t *bss_cache_ctrl);
++void wl_update_bss_cache(wl_bss_cache_ctrl_t *bss_cache_ctrl,
++#if defined(RSSIAVG)
++	wl_rssi_cache_ctrl_t *rssi_cache_ctrl,
++#endif
++	wl_scan_results_t *ss_list);
++void wl_release_bss_cache_ctrl(wl_bss_cache_ctrl_t *bss_cache_ctrl);
++#endif
++int wl_ext_get_best_channel(struct net_device *net,
++#if defined(BSSCACHE)
++	wl_bss_cache_ctrl_t *bss_cache_ctrl,
++#else
++	struct wl_scan_results *bss_list,
++#endif
++	int ioctl_ver, int *best_2g_ch, int *best_5g_ch
++);
++#endif /* _wl_android_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_android_ext.c b/module_drivers/drivers/net/wireless/bcmdhd/wl_android_ext.c
+new file mode 100644
+index 000000000..af8ffb2f8
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_android_ext.c
+@@ -0,0 +1,6631 @@
++
++#include <linux/module.h>
++#include <linux/netdevice.h>
++#include <net/netlink.h>
++#include <typedefs.h>
++#include <linuxver.h>
++#include <osl.h>
++
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <ethernet.h>
++
++#include <wl_android.h>
++#include <linux/if_arp.h>
++#include <asm/uaccess.h>
++#include <linux/wireless.h>
++#if defined(WL_WIRELESS_EXT)
++#include <wl_iw.h>
++#endif /* WL_WIRELESS_EXT */
++#include <wldev_common.h>
++#include <wlioctl.h>
++#include <bcmutils.h>
++#include <linux_osl.h>
++#include <dhd_dbg.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_config.h>
++#ifdef WL_CFG80211
++#include <wl_cfg80211.h>
++#endif /* WL_CFG80211 */
++#ifdef WL_ESCAN
++#include <wl_escan.h>
++#endif /* WL_ESCAN */
++
++#define AEXT_ERROR(name, arg1, args...) \
++	do { \
++		if (android_msg_level & ANDROID_ERROR_LEVEL) { \
++			printk(KERN_ERR "[dhd-%s] AEXT-ERROR) %s : " arg1, name, __func__, ## args); \
++		} \
++	} while (0)
++#define AEXT_TRACE(name, arg1, args...) \
++	do { \
++		if (android_msg_level & ANDROID_TRACE_LEVEL) { \
++			printk(KERN_INFO "[dhd-%s] AEXT-TRACE) %s : " arg1, name, __func__, ## args); \
++		} \
++	} while (0)
++#define AEXT_INFO(name, arg1, args...) \
++	do { \
++		if (android_msg_level & ANDROID_INFO_LEVEL) { \
++			printk(KERN_INFO "[dhd-%s] AEXT-INFO) %s : " arg1, name, __func__, ## args); \
++		} \
++	} while (0)
++#define AEXT_DBG(name, arg1, args...) \
++	do { \
++		if (android_msg_level & ANDROID_DBG_LEVEL) { \
++			printk(KERN_INFO "[dhd-%s] AEXT-DBG) %s : " arg1, name, __func__, ## args); \
++		} \
++	} while (0)
++
++#ifndef WL_CFG80211
++#define htod32(i) i
++#define htod16(i) i
++#define dtoh32(i) i
++#define dtoh16(i) i
++#define htodchanspec(i) i
++#define dtohchanspec(i) i
++#define IEEE80211_BAND_2GHZ 0
++#define IEEE80211_BAND_5GHZ 1
++#define WL_SCAN_JOIN_PROBE_INTERVAL_MS 		20
++#define WL_SCAN_JOIN_ACTIVE_DWELL_TIME_MS 	320
++#define WL_SCAN_JOIN_PASSIVE_DWELL_TIME_MS 	400
++#endif /* WL_CFG80211 */
++#define strtoul(nptr, endptr, base) bcm_strtoul((nptr), (endptr), (base))
++
++#ifndef IW_CUSTOM_MAX
++#define IW_CUSTOM_MAX 256 /* size of extra buffer used for translation of events */
++#endif /* IW_CUSTOM_MAX */
++
++#define CMD_CHANNEL				"CHANNEL"
++#define CMD_CHANNELS			"CHANNELS"
++#define CMD_ROAM_TRIGGER		"ROAM_TRIGGER"
++#define CMD_PM					"PM"
++#define CMD_MONITOR				"MONITOR"
++#define CMD_SET_SUSPEND_BCN_LI_DTIM		"SET_SUSPEND_BCN_LI_DTIM"
++
++#ifdef WL_EXT_IAPSTA
++#include <net/rtnetlink.h>
++#define CMD_IAPSTA_INIT			"IAPSTA_INIT"
++#define CMD_IAPSTA_CONFIG		"IAPSTA_CONFIG"
++#define CMD_IAPSTA_ENABLE		"IAPSTA_ENABLE"
++#define CMD_IAPSTA_DISABLE		"IAPSTA_DISABLE"
++#define CMD_ISAM_INIT			"ISAM_INIT"
++#define CMD_ISAM_CONFIG			"ISAM_CONFIG"
++#define CMD_ISAM_ENABLE			"ISAM_ENABLE"
++#define CMD_ISAM_DISABLE		"ISAM_DISABLE"
++#define CMD_ISAM_STATUS			"ISAM_STATUS"
++#define CMD_ISAM_PARAM			"ISAM_PARAM"
++#ifdef PROP_TXSTATUS
++#ifdef PROP_TXSTATUS_VSDB
++#include <dhd_wlfc.h>
++extern int disable_proptx;
++#endif /* PROP_TXSTATUS_VSDB */
++#endif /* PROP_TXSTATUS */
++#endif /* WL_EXT_IAPSTA */
++#define CMD_AUTOCHANNEL		"AUTOCHANNEL"
++#define CMD_WL		"WL"
++
++#ifdef WL_EXT_IAPSTA
++typedef enum APSTAMODE {
++	IUNKNOWN_MODE = 0,
++	ISTAONLY_MODE = 1,
++	IAPONLY_MODE = 2,
++	ISTAAP_MODE = 3,
++	ISTAGO_MODE = 4,
++	ISTASTA_MODE = 5,
++	IDUALAP_MODE = 6,
++	ISTAAPAP_MODE = 7,
++	IMESHONLY_MODE = 8,
++	ISTAMESH_MODE = 9,
++	IMESHAP_MODE = 10,
++	ISTAAPMESH_MODE = 11,
++	IMESHAPAP_MODE = 12
++} apstamode_t;
++
++typedef enum IFMODE {
++	ISTA_MODE = 1,
++	IAP_MODE,
++	IGO_MODE,
++	IGC_MODE,
++	IMESH_MODE
++} ifmode_t;
++
++typedef enum BGNMODE {
++	IEEE80211B = 1,
++	IEEE80211G,
++	IEEE80211BG,
++	IEEE80211BGN,
++	IEEE80211BGNAC
++} bgnmode_t;
++
++typedef enum AUTHMODE {
++	AUTH_OPEN,
++	AUTH_SHARED,
++	AUTH_WPAPSK,
++	AUTH_WPA2PSK,
++	AUTH_WPAWPA2PSK,
++	AUTH_SAE
++} authmode_t;
++
++typedef enum ENCMODE {
++	ENC_NONE,
++	ENC_WEP,
++	ENC_TKIP,
++	ENC_AES,
++	ENC_TKIPAES
++} encmode_t;
++
++enum wl_if_list {
++	IF_PIF,
++	IF_VIF,
++	IF_VIF2,
++	MAX_IF_NUM
++};
++
++typedef enum WL_PRIO {
++	PRIO_AP,
++	PRIO_MESH,
++	PRIO_STA
++} wl_prio_t;
++
++typedef struct wl_if_info {
++	struct net_device *dev;
++	ifmode_t ifmode;
++	unsigned long status;
++	char prefix;
++	wl_prio_t prio;
++	int ifidx;
++	uint8 bssidx;
++	char ifname[IFNAMSIZ+1];
++	char ssid[DOT11_MAX_SSID_LEN];
++	struct ether_addr bssid;
++	bgnmode_t bgnmode;
++	int hidden;
++	int maxassoc;
++	uint16 channel;
++	authmode_t amode;
++	encmode_t emode;
++	char key[100];
++#if defined(WLMESH) && defined(WL_ESCAN)
++	struct wl_escan_info *escan;
++	timer_list_compat_t delay_scan;
++#endif /* WLMESH && WL_ESCAN */
++} wl_if_info_t;
++
++#define CSA_FW_BIT		(1<<0)
++#define CSA_DRV_BIT		(1<<1)
++
++typedef struct wl_apsta_params {
++	struct wl_if_info if_info[MAX_IF_NUM];
++	struct dhd_pub *dhd;
++	int ioctl_ver;
++	bool init;
++	int rsdb;
++	bool vsdb;
++	uint csa;
++	uint acs;
++	bool radar;
++	apstamode_t apstamode;
++	wait_queue_head_t netif_change_event;
++	struct mutex usr_sync;
++#if defined(WLMESH) && defined(WL_ESCAN)
++	int macs;
++	struct wl_mesh_params mesh_info;
++#endif /* WLMESH && WL_ESCAN */
++} wl_apsta_params_t;
++
++#define MAX_AP_LINK_WAIT_TIME   3000
++#define MAX_STA_LINK_WAIT_TIME   15000
++enum wifi_isam_status {
++	ISAM_STATUS_IF_ADDING = 0,
++	ISAM_STATUS_IF_READY,
++	ISAM_STATUS_STA_CONNECTING,
++	ISAM_STATUS_STA_CONNECTED,
++	ISAM_STATUS_AP_CREATING,
++	ISAM_STATUS_AP_CREATED
++};
++
++#define wl_get_isam_status(cur_if, stat) \
++	(test_bit(ISAM_STATUS_ ## stat, &(cur_if)->status))
++#define wl_set_isam_status(cur_if, stat) \
++	(set_bit(ISAM_STATUS_ ## stat, &(cur_if)->status))
++#define wl_clr_isam_status(cur_if, stat) \
++	(clear_bit(ISAM_STATUS_ ## stat, &(cur_if)->status))
++#define wl_chg_isam_status(cur_if, stat) \
++	(change_bit(ISAM_STATUS_ ## stat, &(cur_if)->status))
++
++static int wl_ext_enable_iface(struct net_device *dev, char *ifname, int wait_up);
++static int wl_ext_disable_iface(struct net_device *dev, char *ifname);
++#if defined(WLMESH) && defined(WL_ESCAN)
++static int wl_mesh_escan_attach(dhd_pub_t *dhd, struct wl_if_info *cur_if);
++#endif /* WLMESH && WL_ESCAN */
++#endif /* WL_EXT_IAPSTA */
++
++#ifdef IDHCP
++typedef struct dhcpc_parameter {
++	uint32 ip_addr;
++	uint32 ip_serv;
++	uint32 lease_time;
++} dhcpc_para_t;
++#endif /* IDHCP */
++
++#ifdef WL_EXT_WOWL
++#define WL_WOWL_TCPFIN	(1 << 26)
++typedef struct wl_wowl_pattern2 {
++	char cmd[4];
++	wl_wowl_pattern_t wowl_pattern;
++} wl_wowl_pattern2_t;
++#endif /* WL_EXT_WOWL */
++
++#ifdef WL_EXT_TCPKA
++typedef struct tcpka_conn {
++	uint32 sess_id;
++	struct ether_addr dst_mac;	/* Destinition Mac */
++	struct ipv4_addr  src_ip;	/* Sorce IP */
++	struct ipv4_addr  dst_ip;	/* Destinition IP */
++	uint16 ipid;	/* Ip Identification */
++	uint16 srcport;	/* Source Port Address */
++	uint16 dstport;	/* Destination Port Address */
++	uint32 seq;		/* TCP Sequence Number */
++	uint32 ack;		/* TCP Ack Number */
++	uint16 tcpwin;	/* TCP window */
++	uint32 tsval;	/* Timestamp Value */
++	uint32 tsecr;	/* Timestamp Echo Reply */
++	uint32 len;		/* last packet payload len */
++	uint32 ka_payload_len;	/* keep alive payload length */
++	uint8  ka_payload[1];	/* keep alive payload */
++} tcpka_conn_t;
++
++typedef struct tcpka_conn_sess {
++	uint32 sess_id;	/* session id */
++	uint32 flag;	/* enable/disable flag */
++	wl_mtcpkeep_alive_timers_pkt_t  tcpka_timers;
++} tcpka_conn_sess_t;
++
++typedef struct tcpka_conn_info {
++	uint32 ipid;
++	uint32 seq;
++	uint32 ack;
++} tcpka_conn_sess_info_t;
++#endif /* WL_EXT_TCPKA */
++
++static int wl_ext_wl_iovar(struct net_device *dev, char *command, int total_len);
++
++static int
++wl_ext_ioctl(struct net_device *dev, u32 cmd, void *arg, u32 len, u32 set)
++{
++	int ret;
++
++	ret = wldev_ioctl(dev, cmd, arg, len, set);
++	if (ret)
++		AEXT_ERROR(dev->name, "cmd=%d, ret=%d\n", cmd, ret);
++	return ret;
++}
++
++static int
++wl_ext_iovar_getint(struct net_device *dev, s8 *iovar, s32 *val)
++{
++	int ret;
++
++	ret = wldev_iovar_getint(dev, iovar, val);
++	if (ret)
++		AEXT_ERROR(dev->name, "iovar=%s, ret=%d\n", iovar, ret);
++
++	return ret;
++}
++
++static int
++wl_ext_iovar_setint(struct net_device *dev, s8 *iovar, s32 val)
++{
++	int ret;
++
++	ret = wldev_iovar_setint(dev, iovar, val);
++	if (ret)
++		AEXT_ERROR(dev->name, "iovar=%s, ret=%d\n", iovar, ret);
++
++	return ret;
++}
++
++static int
++wl_ext_iovar_getbuf(struct net_device *dev, s8 *iovar_name,
++	void *param, s32 paramlen, void *buf, s32 buflen, struct mutex* buf_sync)
++{
++	int ret;
++
++	ret = wldev_iovar_getbuf(dev, iovar_name, param, paramlen, buf, buflen, buf_sync);
++	if (ret != 0)
++		AEXT_ERROR(dev->name, "iovar=%s, ret=%d\n", iovar_name, ret);
++
++	return ret;
++}
++
++static int
++wl_ext_iovar_setbuf(struct net_device *dev, s8 *iovar_name,
++	void *param, s32 paramlen, void *buf, s32 buflen, struct mutex* buf_sync)
++{
++	int ret;
++
++	ret = wldev_iovar_setbuf(dev, iovar_name, param, paramlen, buf, buflen, buf_sync);
++	if (ret != 0)
++		AEXT_ERROR(dev->name, "iovar=%s, ret=%d\n", iovar_name, ret);
++
++	return ret;
++}
++
++static int
++wl_ext_iovar_setbuf_bsscfg(struct net_device *dev, s8 *iovar_name,
++	void *param, s32 paramlen, void *buf, s32 buflen, s32 bsscfg_idx,
++	struct mutex* buf_sync)
++{
++	int ret;
++
++	ret = wldev_iovar_setbuf_bsscfg(dev, iovar_name, param, paramlen,
++		buf, buflen, bsscfg_idx, buf_sync);
++	if (ret < 0)
++		AEXT_ERROR(dev->name, "iovar=%s, ret=%d\n", iovar_name, ret);
++
++	return ret;
++}
++
++static chanspec_t
++wl_ext_chspec_to_legacy(chanspec_t chspec)
++{
++	chanspec_t lchspec;
++
++	if (wf_chspec_malformed(chspec)) {
++		AEXT_ERROR("wlan", "input chanspec (0x%04X) malformed\n", chspec);
++		return INVCHANSPEC;
++	}
++
++	/* get the channel number */
++	lchspec = CHSPEC_CHANNEL(chspec);
++
++	/* convert the band */
++	if (CHSPEC_IS2G(chspec)) {
++		lchspec |= WL_LCHANSPEC_BAND_2G;
++	} else {
++		lchspec |= WL_LCHANSPEC_BAND_5G;
++	}
++
++	/* convert the bw and sideband */
++	if (CHSPEC_IS20(chspec)) {
++		lchspec |= WL_LCHANSPEC_BW_20;
++		lchspec |= WL_LCHANSPEC_CTL_SB_NONE;
++	} else if (CHSPEC_IS40(chspec)) {
++		lchspec |= WL_LCHANSPEC_BW_40;
++		if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_L) {
++			lchspec |= WL_LCHANSPEC_CTL_SB_LOWER;
++		} else {
++			lchspec |= WL_LCHANSPEC_CTL_SB_UPPER;
++		}
++	} else {
++		/* cannot express the bandwidth */
++		char chanbuf[CHANSPEC_STR_LEN];
++		AEXT_ERROR("wlan", "unable to convert chanspec %s (0x%04X) "
++			"to pre-11ac format\n",
++			wf_chspec_ntoa(chspec, chanbuf), chspec);
++		return INVCHANSPEC;
++	}
++
++	return lchspec;
++}
++
++static chanspec_t
++wl_ext_chspec_host_to_driver(int ioctl_ver, chanspec_t chanspec)
++{
++	if (ioctl_ver == 1) {
++		chanspec = wl_ext_chspec_to_legacy(chanspec);
++		if (chanspec == INVCHANSPEC) {
++			return chanspec;
++		}
++	}
++	chanspec = htodchanspec(chanspec);
++
++	return chanspec;
++}
++
++static void
++wl_ext_ch_to_chanspec(int ioctl_ver, int ch,
++	struct wl_join_params *join_params, size_t *join_params_size)
++{
++	chanspec_t chanspec = 0;
++
++	if (ch != 0) {
++		join_params->params.chanspec_num = 1;
++		join_params->params.chanspec_list[0] = ch;
++
++		if (join_params->params.chanspec_list[0] <= CH_MAX_2G_CHANNEL)
++			chanspec |= WL_CHANSPEC_BAND_2G;
++		else
++			chanspec |= WL_CHANSPEC_BAND_5G;
++
++		chanspec |= WL_CHANSPEC_BW_20;
++		chanspec |= WL_CHANSPEC_CTL_SB_NONE;
++
++		*join_params_size += WL_ASSOC_PARAMS_FIXED_SIZE +
++			join_params->params.chanspec_num * sizeof(chanspec_t);
++
++		join_params->params.chanspec_list[0]  &= WL_CHANSPEC_CHAN_MASK;
++		join_params->params.chanspec_list[0] |= chanspec;
++		join_params->params.chanspec_list[0] =
++			wl_ext_chspec_host_to_driver(ioctl_ver,
++				join_params->params.chanspec_list[0]);
++
++		join_params->params.chanspec_num =
++			htod32(join_params->params.chanspec_num);
++	}
++}
++
++#if defined(WL_EXT_IAPSTA) || defined(WL_CFG80211) || defined(WL_ESCAN)
++static chanspec_t
++wl_ext_chspec_from_legacy(chanspec_t legacy_chspec)
++{
++	chanspec_t chspec;
++
++	/* get the channel number */
++	chspec = LCHSPEC_CHANNEL(legacy_chspec);
++
++	/* convert the band */
++	if (LCHSPEC_IS2G(legacy_chspec)) {
++		chspec |= WL_CHANSPEC_BAND_2G;
++	} else {
++		chspec |= WL_CHANSPEC_BAND_5G;
++	}
++
++	/* convert the bw and sideband */
++	if (LCHSPEC_IS20(legacy_chspec)) {
++		chspec |= WL_CHANSPEC_BW_20;
++	} else {
++		chspec |= WL_CHANSPEC_BW_40;
++		if (LCHSPEC_CTL_SB(legacy_chspec) == WL_LCHANSPEC_CTL_SB_LOWER) {
++			chspec |= WL_CHANSPEC_CTL_SB_L;
++		} else {
++			chspec |= WL_CHANSPEC_CTL_SB_U;
++		}
++	}
++
++	if (wf_chspec_malformed(chspec)) {
++		AEXT_ERROR("wlan", "output chanspec (0x%04X) malformed\n", chspec);
++		return INVCHANSPEC;
++	}
++
++	return chspec;
++}
++
++static chanspec_t
++wl_ext_chspec_driver_to_host(int ioctl_ver, chanspec_t chanspec)
++{
++	chanspec = dtohchanspec(chanspec);
++	if (ioctl_ver == 1) {
++		chanspec = wl_ext_chspec_from_legacy(chanspec);
++	}
++
++	return chanspec;
++}
++#endif /* WL_EXT_IAPSTA || WL_CFG80211 || WL_ESCAN */
++
++bool
++wl_ext_check_scan(struct net_device *dev, dhd_pub_t *dhdp)
++{
++#ifdef WL_CFG80211
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++#endif /* WL_CFG80211 */
++#ifdef WL_ESCAN
++	struct wl_escan_info *escan = dhdp->escan;
++#endif /* WL_ESCAN */
++
++#ifdef WL_CFG80211
++	if (wl_get_drv_status_all(cfg, SCANNING)) {
++		AEXT_ERROR(dev->name, "cfg80211 scanning...\n");
++		return TRUE;
++	}
++#endif /* WL_CFG80211 */
++
++#ifdef WL_ESCAN
++	if (escan->escan_state == ESCAN_STATE_SCANING) {
++		AEXT_ERROR(dev->name, "escan scanning...\n");
++		return TRUE;
++	}
++#endif /* WL_ESCAN */
++
++	return FALSE;
++}
++
++#if defined(WL_CFG80211) || defined(WL_ESCAN)
++void
++wl_ext_user_sync(struct dhd_pub *dhd, int ifidx, bool lock)
++{
++	struct net_device *dev = dhd_idx2net(dhd, ifidx);
++#ifdef WL_CFG80211
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++#endif /* WL_CFG80211 */
++#ifdef WL_ESCAN
++	struct wl_escan_info *escan = dhd->escan;
++#endif /* WL_ESCAN */
++
++	AEXT_INFO(dev->name, "lock=%d\n", lock);
++
++	if (lock) {
++#if defined(WL_CFG80211)
++		mutex_lock(&cfg->usr_sync);
++#endif
++#if defined(WL_ESCAN)
++		mutex_lock(&escan->usr_sync);
++#endif
++	} else {
++#if defined(WL_CFG80211)
++		mutex_unlock(&cfg->usr_sync);
++#endif
++#if defined(WL_ESCAN)
++		mutex_unlock(&escan->usr_sync);
++#endif
++	}
++}
++
++bool
++wl_ext_event_complete(struct dhd_pub *dhd, int ifidx)
++{
++	struct net_device *dev = dhd_idx2net(dhd, ifidx);
++#ifdef WL_CFG80211
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++#endif /* WL_CFG80211 */
++#ifdef WL_ESCAN
++	struct wl_escan_info *escan = dhd->escan;
++#endif /* WL_ESCAN */
++	bool complete = TRUE;
++
++#ifdef WL_CFG80211
++	if (wl_get_drv_status_all(cfg, SCANNING)) {
++		AEXT_INFO(dev->name, "SCANNING\n");
++		complete = FALSE;
++	}
++	if (wl_get_drv_status_all(cfg, CONNECTING)) {
++		AEXT_INFO(dev->name, "CONNECTING\n");
++		complete = FALSE;
++	}
++	if (wl_get_drv_status_all(cfg, DISCONNECTING)) {
++		AEXT_INFO(dev->name, "DISCONNECTING\n");
++		complete = FALSE;
++	}
++#endif /* WL_CFG80211 */
++#ifdef WL_ESCAN
++	if (escan->escan_state == ESCAN_STATE_SCANING) {
++		AEXT_INFO(dev->name, "ESCAN_STATE_SCANING\n");
++		complete = FALSE;
++	}
++#endif /* WL_ESCAN */
++	if (dhd->conf->eapol_status >= EAPOL_STATUS_4WAY_START &&
++			dhd->conf->eapol_status < EAPOL_STATUS_4WAY_DONE) {
++		AEXT_INFO(dev->name, "4-WAY handshaking\n");
++		complete = FALSE;
++	}
++
++	return complete;
++}
++#endif /* WL_CFG80211 && WL_ESCAN */
++
++static int
++wl_ext_get_ioctl_ver(struct net_device *dev, int *ioctl_ver)
++{
++	int ret = 0;
++	s32 val = 0;
++
++	val = 1;
++	ret = wl_ext_ioctl(dev, WLC_GET_VERSION, &val, sizeof(val), 0);
++	if (ret) {
++		return ret;
++	}
++	val = dtoh32(val);
++	if (val != WLC_IOCTL_VERSION && val != 1) {
++		AEXT_ERROR(dev->name, "Version mismatch, please upgrade. Got %d, expected %d or 1\n",
++			val, WLC_IOCTL_VERSION);
++		return BCME_VERSION;
++	}
++	*ioctl_ver = val;
++
++	return ret;
++}
++
++static int
++wl_ext_set_chanspec(struct net_device *dev, int ioctl_ver,
++	uint16 channel, chanspec_t *ret_chspec)
++{
++	s32 _chan = channel;
++	chanspec_t chspec = 0;
++	chanspec_t fw_chspec = 0;
++	u32 bw = WL_CHANSPEC_BW_20;
++	s32 err = BCME_OK;
++	s32 bw_cap = 0;
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	struct {
++		u32 band;
++		u32 bw_cap;
++	} param = {0, 0};
++	uint band;
++
++	if (_chan <= CH_MAX_2G_CHANNEL)
++		band = IEEE80211_BAND_2GHZ;
++	else
++		band = IEEE80211_BAND_5GHZ;
++
++	if (band == IEEE80211_BAND_5GHZ) {
++		param.band = WLC_BAND_5G;
++		err = wl_ext_iovar_getbuf(dev, "bw_cap", &param, sizeof(param),
++			iovar_buf, WLC_IOCTL_SMLEN, NULL);
++		if (err) {
++			if (err != BCME_UNSUPPORTED) {
++				AEXT_ERROR(dev->name, "bw_cap failed, %d\n", err);
++				return err;
++			} else {
++				err = wl_ext_iovar_getint(dev, "mimo_bw_cap", &bw_cap);
++				if (bw_cap != WLC_N_BW_20ALL)
++					bw = WL_CHANSPEC_BW_40;
++			}
++		} else {
++			if (WL_BW_CAP_80MHZ(iovar_buf[0]))
++				bw = WL_CHANSPEC_BW_80;
++			else if (WL_BW_CAP_40MHZ(iovar_buf[0]))
++				bw = WL_CHANSPEC_BW_40;
++			else
++				bw = WL_CHANSPEC_BW_20;
++
++		}
++	}
++	else if (band == IEEE80211_BAND_2GHZ)
++		bw = WL_CHANSPEC_BW_20;
++
++set_channel:
++	chspec = wf_channel2chspec(_chan, bw);
++	if (wf_chspec_valid(chspec)) {
++		fw_chspec = wl_ext_chspec_host_to_driver(ioctl_ver, chspec);
++		if (fw_chspec != INVCHANSPEC) {
++			if ((err = wl_ext_iovar_setint(dev, "chanspec", fw_chspec)) == BCME_BADCHAN) {
++				if (bw == WL_CHANSPEC_BW_80)
++					goto change_bw;
++				err = wl_ext_ioctl(dev, WLC_SET_CHANNEL, &_chan, sizeof(_chan), 1);
++				WL_MSG(dev->name, "channel %d\n", _chan);
++			} else if (err) {
++				AEXT_ERROR(dev->name, "failed to set chanspec error %d\n", err);
++			} else
++				WL_MSG(dev->name, "channel %d, 0x%x\n", channel, chspec);
++		} else {
++			AEXT_ERROR(dev->name, "failed to convert host chanspec to fw chanspec\n");
++			err = BCME_ERROR;
++		}
++	} else {
++change_bw:
++		if (bw == WL_CHANSPEC_BW_80)
++			bw = WL_CHANSPEC_BW_40;
++		else if (bw == WL_CHANSPEC_BW_40)
++			bw = WL_CHANSPEC_BW_20;
++		else
++			bw = 0;
++		if (bw)
++			goto set_channel;
++		AEXT_ERROR(dev->name, "Invalid chanspec 0x%x\n", chspec);
++		err = BCME_ERROR;
++	}
++	*ret_chspec = fw_chspec;
++
++	return err;
++}
++
++static int
++wl_ext_channel(struct net_device *dev, char* command, int total_len)
++{
++	int ret;
++	int channel=0;
++	channel_info_t ci;
++	int bytes_written = 0;
++	chanspec_t fw_chspec;
++	int ioctl_ver = 0;
++
++	AEXT_TRACE(dev->name, "cmd %s", command);
++
++	sscanf(command, "%*s %d", &channel);
++
++	if (channel > 0) {
++		wl_ext_get_ioctl_ver(dev, &ioctl_ver);
++		ret = wl_ext_set_chanspec(dev, ioctl_ver, channel, &fw_chspec);
++	} else {
++		if (!(ret = wl_ext_ioctl(dev, WLC_GET_CHANNEL, &ci,
++				sizeof(channel_info_t), FALSE))) {
++			AEXT_TRACE(dev->name, "hw_channel %d\n", ci.hw_channel);
++			AEXT_TRACE(dev->name, "target_channel %d\n", ci.target_channel);
++			AEXT_TRACE(dev->name, "scan_channel %d\n", ci.scan_channel);
++			bytes_written = snprintf(command, sizeof(channel_info_t)+2,
++				"channel %d", ci.hw_channel);
++			AEXT_TRACE(dev->name, "command result is %s\n", command);
++			ret = bytes_written;
++		}
++	}
++
++	return ret;
++}
++
++static int
++wl_ext_channels(struct net_device *dev, char* command, int total_len)
++{
++	int ret, i;
++	int bytes_written = -1;
++	u8 valid_chan_list[sizeof(u32)*(WL_NUMCHANNELS + 1)];
++	wl_uint32_list_t *list;
++
++	AEXT_TRACE(dev->name, "cmd %s", command);
++
++	memset(valid_chan_list, 0, sizeof(valid_chan_list));
++	list = (wl_uint32_list_t *)(void *) valid_chan_list;
++	list->count = htod32(WL_NUMCHANNELS);
++	ret = wl_ext_ioctl(dev, WLC_GET_VALID_CHANNELS, valid_chan_list,
++		sizeof(valid_chan_list), 0);
++	if (ret<0) {
++		AEXT_ERROR(dev->name, "get channels failed with %d\n", ret);
++	} else {
++		bytes_written = snprintf(command, total_len, "channels");
++		for (i = 0; i < dtoh32(list->count); i++) {
++			bytes_written += snprintf(command+bytes_written, total_len, " %d",
++				dtoh32(list->element[i]));
++		}
++		AEXT_TRACE(dev->name, "command result is %s\n", command);
++		ret = bytes_written;
++	}
++
++	return ret;
++}
++
++static int
++wl_ext_roam_trigger(struct net_device *dev, char* command, int total_len)
++{
++	int ret = 0;
++	int roam_trigger[2] = {0, 0};
++	int trigger[2]= {0, 0};
++	int bytes_written=-1;
++
++	sscanf(command, "%*s %10d", &roam_trigger[0]);
++
++	if (roam_trigger[0]) {
++		roam_trigger[1] = WLC_BAND_ALL;
++		ret = wl_ext_ioctl(dev, WLC_SET_ROAM_TRIGGER, roam_trigger,
++			sizeof(roam_trigger), 1);
++	} else {
++		roam_trigger[1] = WLC_BAND_2G;
++		ret = wl_ext_ioctl(dev, WLC_GET_ROAM_TRIGGER, roam_trigger,
++			sizeof(roam_trigger), 0);
++		if (!ret)
++			trigger[0] = roam_trigger[0];
++
++		roam_trigger[1] = WLC_BAND_5G;
++		ret = wl_ext_ioctl(dev, WLC_GET_ROAM_TRIGGER, &roam_trigger,
++			sizeof(roam_trigger), 0);
++		if (!ret)
++			trigger[1] = roam_trigger[0];
++
++		AEXT_TRACE(dev->name, "roam_trigger %d %d\n", trigger[0], trigger[1]);
++		bytes_written = snprintf(command, total_len, "%d %d", trigger[0], trigger[1]);
++		ret = bytes_written;
++	}
++
++	return ret;
++}
++
++static int
++wl_ext_pm(struct net_device *dev, char *command, int total_len)
++{
++	int pm=-1, ret = -1;
++	char *pm_local;
++	int bytes_written=-1;
++
++	AEXT_TRACE(dev->name, "cmd %s", command);
++
++	sscanf(command, "%*s %d", &pm);
++
++	if (pm >= 0) {
++		ret = wl_ext_ioctl(dev, WLC_SET_PM, &pm, sizeof(pm), 1);
++	} else {
++		ret = wl_ext_ioctl(dev, WLC_GET_PM, &pm, sizeof(pm), 0);
++		if (!ret) {
++			AEXT_TRACE(dev->name, "PM = %d", pm);
++			if (pm == PM_OFF)
++				pm_local = "PM_OFF";
++			else if(pm == PM_MAX)
++				pm_local = "PM_MAX";
++			else if(pm == PM_FAST)
++				pm_local = "PM_FAST";
++			else {
++				pm = 0;
++				pm_local = "Invalid";
++			}
++			bytes_written = snprintf(command, total_len, "PM %s", pm_local);
++			AEXT_TRACE(dev->name, "command result is %s\n", command);
++			ret = bytes_written;
++		}
++	}
++
++	return ret;
++}
++
++static int
++wl_ext_monitor(struct net_device *dev, char *command, int total_len)
++{
++	int val = -1, ret = -1;
++	int bytes_written=-1;
++
++	sscanf(command, "%*s %d", &val);
++
++	if (val >=0) {
++		ret = wl_ext_ioctl(dev, WLC_SET_MONITOR, &val, sizeof(val), 1);
++	} else {
++		ret = wl_ext_ioctl(dev, WLC_GET_MONITOR, &val, sizeof(val), 0);
++		if (!ret) {
++			AEXT_TRACE(dev->name, "monitor = %d\n", val);
++			bytes_written = snprintf(command, total_len, "monitor %d", val);
++			AEXT_TRACE(dev->name, "command result is %s\n", command);
++			ret = bytes_written;
++		}
++	}
++
++	return ret;
++}
++
++s32
++wl_ext_connect(struct net_device *dev, struct wl_conn_info *conn_info)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	wl_extjoin_params_t *ext_join_params = NULL;
++	struct wl_join_params join_params;
++	size_t join_params_size;
++	s32 err = 0;
++	u32 chan_cnt = 0;
++	s8 *iovar_buf = NULL;
++	int ioctl_ver = 0;
++	char sec[32];
++
++	wl_ext_get_ioctl_ver(dev, &ioctl_ver);
++
++	if (dhd->conf->chip == BCM43362_CHIP_ID)
++		goto set_ssid;
++
++	if (conn_info->channel) {
++		chan_cnt = 1;
++	}
++
++	iovar_buf = kzalloc(WLC_IOCTL_MAXLEN, GFP_KERNEL);
++	if (iovar_buf == NULL) {
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	/*
++	 *	Join with specific BSSID and cached SSID
++	 *	If SSID is zero join based on BSSID only
++	 */
++	join_params_size = WL_EXTJOIN_PARAMS_FIXED_SIZE +
++		chan_cnt * sizeof(chanspec_t);
++	ext_join_params =  (wl_extjoin_params_t*)kzalloc(join_params_size, GFP_KERNEL);
++	if (ext_join_params == NULL) {
++		err = -ENOMEM;
++		goto exit;
++	}
++	ext_join_params->ssid.SSID_len = min((uint32)sizeof(ext_join_params->ssid.SSID),
++		conn_info->ssid.SSID_len);
++	memcpy(&ext_join_params->ssid.SSID, conn_info->ssid.SSID, ext_join_params->ssid.SSID_len);
++	ext_join_params->ssid.SSID_len = htod32(ext_join_params->ssid.SSID_len);
++	/* increate dwell time to receive probe response or detect Beacon
++	* from target AP at a noisy air only during connect command
++	*/
++	ext_join_params->scan.active_time = chan_cnt ? WL_SCAN_JOIN_ACTIVE_DWELL_TIME_MS : -1;
++	ext_join_params->scan.passive_time = chan_cnt ? WL_SCAN_JOIN_PASSIVE_DWELL_TIME_MS : -1;
++	/* Set up join scan parameters */
++	ext_join_params->scan.scan_type = -1;
++	ext_join_params->scan.nprobes = chan_cnt ?
++		(ext_join_params->scan.active_time/WL_SCAN_JOIN_PROBE_INTERVAL_MS) : -1;
++	ext_join_params->scan.home_time = -1;
++
++	if (memcmp(&ether_null, &conn_info->bssid, ETHER_ADDR_LEN))
++		memcpy(&ext_join_params->assoc.bssid, &conn_info->bssid, ETH_ALEN);
++	else
++		memcpy(&ext_join_params->assoc.bssid, &ether_bcast, ETH_ALEN);
++	ext_join_params->assoc.chanspec_num = chan_cnt;
++	if (chan_cnt) {
++		u16 band, bw, ctl_sb;
++		chanspec_t chspec;
++		band = (conn_info->channel <= CH_MAX_2G_CHANNEL) ? WL_CHANSPEC_BAND_2G
++			: WL_CHANSPEC_BAND_5G;
++		bw = WL_CHANSPEC_BW_20;
++		ctl_sb = WL_CHANSPEC_CTL_SB_NONE;
++		chspec = (conn_info->channel | band | bw | ctl_sb);
++		ext_join_params->assoc.chanspec_list[0]  &= WL_CHANSPEC_CHAN_MASK;
++		ext_join_params->assoc.chanspec_list[0] |= chspec;
++		ext_join_params->assoc.chanspec_list[0] =
++			wl_ext_chspec_host_to_driver(ioctl_ver,
++				ext_join_params->assoc.chanspec_list[0]);
++	}
++	ext_join_params->assoc.chanspec_num = htod32(ext_join_params->assoc.chanspec_num);
++
++	wl_ext_get_sec(dev, 0, sec, sizeof(sec));
++	WL_MSG(dev->name,
++		"Connecting with %pM channel (%d) ssid \"%s\", len (%d), sec=%s\n\n",
++		&ext_join_params->assoc.bssid, conn_info->channel,
++		ext_join_params->ssid.SSID, ext_join_params->ssid.SSID_len, sec);
++	err = wl_ext_iovar_setbuf_bsscfg(dev, "join", ext_join_params,
++		join_params_size, iovar_buf, WLC_IOCTL_MAXLEN, conn_info->bssidx, NULL);
++
++	if (err) {
++		if (err == BCME_UNSUPPORTED) {
++			AEXT_TRACE(dev->name, "join iovar is not supported\n");
++			goto set_ssid;
++		} else {
++			AEXT_ERROR(dev->name, "error (%d)\n", err);
++			goto exit;
++		}
++	} else
++		goto exit;
++
++set_ssid:
++	memset(&join_params, 0, sizeof(join_params));
++	join_params_size = sizeof(join_params.ssid);
++
++	join_params.ssid.SSID_len = min((uint32)sizeof(join_params.ssid.SSID),
++		conn_info->ssid.SSID_len);
++	memcpy(&join_params.ssid.SSID, conn_info->ssid.SSID, join_params.ssid.SSID_len);
++	join_params.ssid.SSID_len = htod32(join_params.ssid.SSID_len);
++	if (memcmp(&ether_null, &conn_info->bssid, ETHER_ADDR_LEN))
++		memcpy(&join_params.params.bssid, &conn_info->bssid, ETH_ALEN);
++	else
++		memcpy(&join_params.params.bssid, &ether_bcast, ETH_ALEN);
++
++	wl_ext_ch_to_chanspec(ioctl_ver, conn_info->channel, &join_params, &join_params_size);
++	AEXT_TRACE(dev->name, "join_param_size %zu\n", join_params_size);
++
++	if (join_params.ssid.SSID_len < IEEE80211_MAX_SSID_LEN) {
++		AEXT_INFO(dev->name, "ssid \"%s\", len (%d)\n", join_params.ssid.SSID,
++			join_params.ssid.SSID_len);
++	}
++	wl_ext_get_sec(dev, 0, sec, sizeof(sec));
++	WL_MSG(dev->name,
++		"Connecting with %pM channel (%d) ssid \"%s\", len (%d), sec=%s\n\n",
++		&join_params.params.bssid, conn_info->channel,
++		join_params.ssid.SSID, join_params.ssid.SSID_len, sec);
++	err = wl_ext_ioctl(dev, WLC_SET_SSID, &join_params, join_params_size, 1);
++
++exit:
++	if (iovar_buf)
++		kfree(iovar_buf);
++	if (ext_join_params)
++		kfree(ext_join_params);
++	return err;
++
++}
++
++void
++wl_ext_get_sec(struct net_device *dev, int ifmode, char *sec, int total_len)
++{
++	int auth=0, wpa_auth=0, wsec=0, mfp=0;
++	int bytes_written=0;
++
++	memset(sec, 0, total_len);
++	wl_ext_iovar_getint(dev, "auth", &auth);
++	wl_ext_iovar_getint(dev, "wpa_auth", &wpa_auth);
++	wl_ext_iovar_getint(dev, "wsec", &wsec);
++	wldev_iovar_getint(dev, "mfp", &mfp);
++
++#ifdef WL_EXT_IAPSTA
++	if (ifmode == IMESH_MODE) {
++		if (auth == WL_AUTH_OPEN_SYSTEM && wpa_auth == WPA_AUTH_DISABLED) {
++			bytes_written += snprintf(sec+bytes_written, total_len, "open");
++		} else if (auth == WL_AUTH_OPEN_SYSTEM && wpa_auth == WPA2_AUTH_PSK) {
++			bytes_written += snprintf(sec+bytes_written, total_len, "sae");
++		} else {
++			bytes_written += snprintf(sec+bytes_written, total_len, "%d/0x%x",
++				auth, wpa_auth);
++		}
++	} else
++#endif /* WL_EXT_IAPSTA */
++	{
++		if (auth == WL_AUTH_OPEN_SYSTEM && wpa_auth == WPA_AUTH_DISABLED) {
++			bytes_written += snprintf(sec+bytes_written, total_len, "open");
++		} else if (auth == WL_AUTH_SHARED_KEY && wpa_auth == WPA_AUTH_DISABLED) {
++			bytes_written += snprintf(sec+bytes_written, total_len, "shared");
++		} else if (auth == WL_AUTH_OPEN_SYSTEM && wpa_auth == WPA_AUTH_PSK) {
++			bytes_written += snprintf(sec+bytes_written, total_len, "wpapsk");
++		} else if (auth == WL_AUTH_OPEN_SYSTEM && wpa_auth == WPA2_AUTH_PSK) {
++			bytes_written += snprintf(sec+bytes_written, total_len, "wpa2psk");
++		} else if (auth == WL_AUTH_OPEN_SHARED && wpa_auth == WPA3_AUTH_SAE_PSK) {
++			bytes_written += snprintf(sec+bytes_written, total_len, "wpa3");
++		} else {
++			bytes_written += snprintf(sec+bytes_written, total_len, "%d/0x%x",
++				auth, wpa_auth);
++		}
++	}
++
++	if (mfp == WL_MFP_NONE) {
++		bytes_written += snprintf(sec+bytes_written, total_len, "/mfpn");
++	} else if (mfp == WL_MFP_CAPABLE) {
++		bytes_written += snprintf(sec+bytes_written, total_len, "/mfpc");
++	} else if (mfp == WL_MFP_REQUIRED) {
++		bytes_written += snprintf(sec+bytes_written, total_len, "/mfpr");
++	} else {
++		bytes_written += snprintf(sec+bytes_written, total_len, "/%d", mfp);
++	}
++
++#ifdef WL_EXT_IAPSTA
++	if (ifmode == IMESH_MODE) {
++		if (wsec == WSEC_NONE) {
++			bytes_written += snprintf(sec+bytes_written, total_len, "/none");
++		} else {
++			bytes_written += snprintf(sec+bytes_written, total_len, "/aes");
++		}
++	} else
++#endif /* WL_EXT_IAPSTA */
++	{
++		if (wsec == WSEC_NONE) {
++			bytes_written += snprintf(sec+bytes_written, total_len, "/none");
++		} else if (wsec == WEP_ENABLED) {
++			bytes_written += snprintf(sec+bytes_written, total_len, "/wep");
++		} else if (wsec == (TKIP_ENABLED|AES_ENABLED) ||
++				wsec == (WSEC_SWFLAG|TKIP_ENABLED|AES_ENABLED)) {
++			bytes_written += snprintf(sec+bytes_written, total_len, "/tkipaes");
++		} else if (wsec == TKIP_ENABLED || wsec == (WSEC_SWFLAG|TKIP_ENABLED)) {
++			bytes_written += snprintf(sec+bytes_written, total_len, "/tkip");
++		} else if (wsec == AES_ENABLED || wsec == (WSEC_SWFLAG|AES_ENABLED)) {
++			bytes_written += snprintf(sec+bytes_written, total_len, "/aes");
++		} else {
++			bytes_written += snprintf(sec+bytes_written, total_len, "/0x%x", wsec);
++		}
++	}
++
++}
++
++static bool
++wl_ext_dfs_chan(uint16 chan)
++{
++	if (chan >= 52 && chan <= 144)
++		return TRUE;
++	return FALSE;
++}
++
++static uint16
++wl_ext_get_default_chan(struct net_device *dev,
++	uint16 *chan_2g, uint16 *chan_5g, bool nodfs)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	uint16 chan_tmp = 0, chan = 0;
++	wl_uint32_list_t *list;
++	u8 valid_chan_list[sizeof(u32)*(WL_NUMCHANNELS + 1)];
++	s32 ret = BCME_OK;
++	int i;
++
++	*chan_2g = 0;
++	*chan_5g = 0;
++	memset(valid_chan_list, 0, sizeof(valid_chan_list));
++	list = (wl_uint32_list_t *)(void *) valid_chan_list;
++	list->count = htod32(WL_NUMCHANNELS);
++	ret = wl_ext_ioctl(dev, WLC_GET_VALID_CHANNELS, valid_chan_list,
++		sizeof(valid_chan_list), 0);
++	if (ret == 0) {
++		for (i=0; i<dtoh32(list->count); i++) {
++			chan_tmp = dtoh32(list->element[i]);
++			if (!dhd_conf_match_channel(dhd, chan_tmp))
++				continue;
++			if (chan_tmp <= 13) {
++				*chan_2g = chan_tmp;
++			} else {
++				if (wl_ext_dfs_chan(chan_tmp) && nodfs)
++					continue;
++				else if (chan_tmp >= 36 && chan_tmp <= 161)
++					*chan_5g = chan_tmp;
++			}
++		}
++	}
++
++	return chan;
++}
++
++#if defined(SENDPROB) || (defined(WLMESH) && defined(WL_ESCAN))
++static int
++wl_ext_add_del_ie(struct net_device *dev, uint pktflag, char *ie_data, const char* add_del_cmd)
++{
++	vndr_ie_setbuf_t *vndr_ie = NULL;
++	char iovar_buf[WLC_IOCTL_SMLEN]="\0";
++	int ie_data_len = 0, tot_len = 0, iecount;
++	int err = -1;
++
++	if (!strlen(ie_data)) {
++		AEXT_ERROR(dev->name, "wrong ie %s\n", ie_data);
++		goto exit;
++	}
++
++	tot_len = (int)(sizeof(vndr_ie_setbuf_t) + ((strlen(ie_data)-2)/2));
++	vndr_ie = (vndr_ie_setbuf_t *) kzalloc(tot_len, GFP_KERNEL);
++	if (!vndr_ie) {
++		AEXT_ERROR(dev->name, "IE memory alloc failed\n");
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	/* Copy the vndr_ie SET command ("add"/"del") to the buffer */
++	strncpy(vndr_ie->cmd, add_del_cmd, VNDR_IE_CMD_LEN - 1);
++	vndr_ie->cmd[VNDR_IE_CMD_LEN - 1] = '\0';
++
++	/* Set the IE count - the buffer contains only 1 IE */
++	iecount = htod32(1);
++	memcpy((void *)&vndr_ie->vndr_ie_buffer.iecount, &iecount, sizeof(s32));
++
++	/* Set packet flag to indicate that BEACON's will contain this IE */
++	pktflag = htod32(pktflag);
++	memcpy((void *)&vndr_ie->vndr_ie_buffer.vndr_ie_list[0].pktflag, &pktflag,
++		sizeof(u32));
++
++	/* Set the IE ID */
++	vndr_ie->vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.id = (uchar)DOT11_MNG_VS_ID;
++
++	/* Set the IE LEN */
++	vndr_ie->vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.len = (strlen(ie_data)-2)/2;
++
++	/* Set the IE OUI and DATA */
++	ie_data_len = wl_pattern_atoh(ie_data,
++		(char *)vndr_ie->vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.oui);
++	if (ie_data_len <= 0) {
++		AEXT_ERROR(dev->name, "wrong ie_data_len %d\n", (int)strlen(ie_data)-2);
++		goto exit;
++	}
++
++	err = wl_ext_iovar_setbuf(dev, "vndr_ie", vndr_ie, tot_len, iovar_buf,
++		sizeof(iovar_buf), NULL);
++
++exit:
++	if (vndr_ie) {
++		kfree(vndr_ie);
++	}
++	return err;
++}
++#endif /* SENDPROB || (WLMESH && WL_ESCAN) */
++
++#ifdef WL_EXT_IAPSTA
++static int
++wl_ext_parse_wep(char *key, struct wl_wsec_key *wsec_key)
++{
++	char hex[] = "XX";
++	unsigned char *data = wsec_key->data;
++	char *keystr = key;
++
++	switch (strlen(keystr)) {
++	case 5:
++	case 13:
++	case 16:
++		wsec_key->len = strlen(keystr);
++		memcpy(data, keystr, wsec_key->len + 1);
++		break;
++	case 12:
++	case 28:
++	case 34:
++	case 66:
++		/* strip leading 0x */
++		if (!strnicmp(keystr, "0x", 2))
++			keystr += 2;
++		else
++			return -1;
++		/* fall through */
++	case 10:
++	case 26:
++	case 32:
++	case 64:
++		wsec_key->len = strlen(keystr) / 2;
++		while (*keystr) {
++			strncpy(hex, keystr, 2);
++			*data++ = (char) strtoul(hex, NULL, 16);
++			keystr += 2;
++		}
++		break;
++	default:
++		return -1;
++	}
++
++	switch (wsec_key->len) {
++	case 5:
++		wsec_key->algo = CRYPTO_ALGO_WEP1;
++		break;
++	case 13:
++		wsec_key->algo = CRYPTO_ALGO_WEP128;
++		break;
++	case 16:
++		/* default to AES-CCM */
++		wsec_key->algo = CRYPTO_ALGO_AES_CCM;
++		break;
++	case 32:
++		wsec_key->algo = CRYPTO_ALGO_TKIP;
++		break;
++	default:
++		return -1;
++	}
++
++	/* Set as primary wsec_key by default */
++	wsec_key->flags |= WL_PRIMARY_KEY;
++
++	return 0;
++}
++
++static int
++wl_ext_set_bgnmode(struct wl_if_info *cur_if)
++{
++	struct net_device *dev = cur_if->dev;
++	bgnmode_t bgnmode = cur_if->bgnmode;
++	int val;
++
++	if (bgnmode == 0)
++		return 0;
++
++	wl_ext_ioctl(dev, WLC_DOWN, NULL, 0, 1);
++	if (bgnmode == IEEE80211B) {
++		wl_ext_iovar_setint(dev, "nmode", 0);
++		val = 0;
++		wl_ext_ioctl(dev, WLC_SET_GMODE, &val, sizeof(val), 1);
++		AEXT_TRACE(dev->name, "Network mode: B only\n");
++	} else if (bgnmode == IEEE80211G) {
++		wl_ext_iovar_setint(dev, "nmode", 0);
++		val = 2;
++		wl_ext_ioctl(dev, WLC_SET_GMODE, &val, sizeof(val), 1);
++		AEXT_TRACE(dev->name, "Network mode: G only\n");
++	} else if (bgnmode == IEEE80211BG) {
++		wl_ext_iovar_setint(dev, "nmode", 0);
++		val = 1;
++		wl_ext_ioctl(dev, WLC_SET_GMODE, &val, sizeof(val), 1);
++		AEXT_TRACE(dev->name, "Network mode: B/G mixed\n");
++	} else if (bgnmode == IEEE80211BGN) {
++		wl_ext_iovar_setint(dev, "nmode", 0);
++		wl_ext_iovar_setint(dev, "nmode", 1);
++		wl_ext_iovar_setint(dev, "vhtmode", 0);
++		val = 1;
++		wl_ext_ioctl(dev, WLC_SET_GMODE, &val, sizeof(val), 1);
++		AEXT_TRACE(dev->name, "Network mode: B/G/N mixed\n");
++	} else if (bgnmode == IEEE80211BGNAC) {
++		wl_ext_iovar_setint(dev, "nmode", 0);
++		wl_ext_iovar_setint(dev, "nmode", 1);
++		wl_ext_iovar_setint(dev, "vhtmode", 1);
++		val = 1;
++		wl_ext_ioctl(dev, WLC_SET_GMODE, &val, sizeof(val), 1);
++		AEXT_TRACE(dev->name, "Network mode: B/G/N/AC mixed\n");
++	}
++	wl_ext_ioctl(dev, WLC_UP, NULL, 0, 1);
++
++	return 0;
++}
++
++static int
++wl_ext_set_amode(struct wl_if_info *cur_if)
++{
++	struct net_device *dev = cur_if->dev;
++	authmode_t amode = cur_if->amode;
++	int auth=0, wpa_auth=0;
++
++#ifdef WLMESH
++	if (cur_if->ifmode == IMESH_MODE) {
++		if (amode == AUTH_SAE) {
++			auth = WL_AUTH_OPEN_SYSTEM;
++			wpa_auth = WPA2_AUTH_PSK;
++			AEXT_INFO(dev->name, "SAE\n");
++		} else {
++			auth = WL_AUTH_OPEN_SYSTEM;
++			wpa_auth = WPA_AUTH_DISABLED;
++			AEXT_INFO(dev->name, "Open System\n");
++		}
++	} else
++#endif /* WLMESH */
++	if (amode == AUTH_OPEN) {
++		auth = WL_AUTH_OPEN_SYSTEM;
++		wpa_auth = WPA_AUTH_DISABLED;
++		AEXT_INFO(dev->name, "Open System\n");
++	} else if (amode == AUTH_SHARED) {
++		auth = WL_AUTH_SHARED_KEY;
++		wpa_auth = WPA_AUTH_DISABLED;
++		AEXT_INFO(dev->name, "Shared Key\n");
++	} else if (amode == AUTH_WPAPSK) {
++		auth = WL_AUTH_OPEN_SYSTEM;
++		wpa_auth = WPA_AUTH_PSK;
++		AEXT_INFO(dev->name, "WPA-PSK\n");
++	} else if (amode == AUTH_WPA2PSK) {
++		auth = WL_AUTH_OPEN_SYSTEM;
++		wpa_auth = WPA2_AUTH_PSK;
++		AEXT_INFO(dev->name, "WPA2-PSK\n");
++	} else if (amode == AUTH_WPAWPA2PSK) {
++		auth = WL_AUTH_OPEN_SYSTEM;
++		wpa_auth = WPA2_AUTH_PSK | WPA_AUTH_PSK;
++		AEXT_INFO(dev->name, "WPA/WPA2-PSK\n");
++	}
++#ifdef WLMESH
++	if (cur_if->ifmode == IMESH_MODE) {
++		s32 val = WL_BSSTYPE_MESH;
++		wl_ext_ioctl(dev, WLC_SET_INFRA, &val, sizeof(val), 1);
++	} else
++#endif /* WLMESH */
++	if (cur_if->ifmode == ISTA_MODE) {
++		s32 val = WL_BSSTYPE_INFRA;
++		wl_ext_ioctl(dev, WLC_SET_INFRA, &val, sizeof(val), 1);
++	}
++	wl_ext_iovar_setint(dev, "auth", auth);
++
++	wl_ext_iovar_setint(dev, "wpa_auth", wpa_auth);
++
++	return 0;
++}
++
++static int
++wl_ext_set_emode(struct wl_apsta_params *apsta_params,
++	struct wl_if_info *cur_if)
++{
++	struct net_device *dev = cur_if->dev;
++	int wsec=0;
++	struct wl_wsec_key wsec_key;
++	wsec_pmk_t psk;
++	authmode_t amode = cur_if->amode;
++	encmode_t emode = cur_if->emode;
++	char *key = cur_if->key;
++	struct dhd_pub *dhd = apsta_params->dhd;
++
++	memset(&wsec_key, 0, sizeof(wsec_key));
++	memset(&psk, 0, sizeof(psk));
++
++#ifdef WLMESH
++	if (cur_if->ifmode == IMESH_MODE) {
++		if (amode == AUTH_SAE) {
++			wsec = AES_ENABLED;
++		} else {
++			wsec = WSEC_NONE;
++		}
++	} else
++#endif /* WLMESH */
++	if (emode == ENC_NONE) {
++		wsec = WSEC_NONE;
++		AEXT_INFO(dev->name, "No securiy\n");
++	} else if (emode == ENC_WEP) {
++		wsec = WEP_ENABLED;
++		wl_ext_parse_wep(key, &wsec_key);
++		AEXT_INFO(dev->name, "WEP key \"%s\"\n", wsec_key.data);
++	} else if (emode == ENC_TKIP) {
++		wsec = TKIP_ENABLED;
++		psk.key_len = strlen(key);
++		psk.flags = WSEC_PASSPHRASE;
++		memcpy(psk.key, key, strlen(key));
++		AEXT_INFO(dev->name, "TKIP key \"%s\"\n", psk.key);
++	} else if (emode == ENC_AES || amode == AUTH_SAE) {
++		wsec = AES_ENABLED;
++		psk.key_len = strlen(key);
++		psk.flags = WSEC_PASSPHRASE;
++		memcpy(psk.key, key, strlen(key));
++		AEXT_INFO(dev->name, "AES key \"%s\"\n", psk.key);
++	} else if (emode == ENC_TKIPAES) {
++		wsec = TKIP_ENABLED | AES_ENABLED;
++		psk.key_len = strlen(key);
++		psk.flags = WSEC_PASSPHRASE;
++		memcpy(psk.key, key, strlen(key));
++		AEXT_INFO(dev->name, "TKIP/AES key \"%s\"\n", psk.key);
++	}
++	if (dhd->conf->chip == BCM43430_CHIP_ID && cur_if->ifidx > 0 && wsec >= 2 &&
++			apsta_params->apstamode == ISTAAP_MODE) {
++		wsec |= WSEC_SWFLAG; // terence 20180628: fix me, this is a workaround
++	}
++
++	wl_ext_iovar_setint(dev, "wsec", wsec);
++
++#ifdef WLMESH
++	if (cur_if->ifmode == IMESH_MODE) {
++		if (amode == AUTH_SAE) {
++			s8 iovar_buf[WLC_IOCTL_SMLEN];
++			AEXT_INFO(dev->name, "AES key \"%s\"\n", key);
++			wl_ext_iovar_setint(dev, "mesh_auth_proto", 1);
++			wl_ext_iovar_setint(dev, "mfp", WL_MFP_REQUIRED);
++			wl_ext_iovar_setbuf(dev, "sae_password", key, strlen(key),
++				iovar_buf, WLC_IOCTL_SMLEN, NULL);
++		} else {
++			AEXT_INFO(dev->name, "No securiy\n");
++			wl_ext_iovar_setint(dev, "mesh_auth_proto", 0);
++			wl_ext_iovar_setint(dev, "mfp", WL_MFP_NONE);
++		}
++	} else
++#endif /* WLMESH */
++	if (emode == ENC_WEP) {
++		wl_ext_ioctl(dev, WLC_SET_KEY, &wsec_key, sizeof(wsec_key), 1);
++	} else if (emode == ENC_TKIP || emode == ENC_AES || emode == ENC_TKIPAES) {
++		if (cur_if->ifmode == ISTA_MODE)
++			wl_ext_iovar_setint(dev, "sup_wpa", 1);
++		wl_ext_ioctl(dev, WLC_SET_WSEC_PMK, &psk, sizeof(psk), 1);
++	}
++
++	return 0;
++}
++
++static u32
++wl_ext_get_chanspec(struct wl_apsta_params *apsta_params,
++	struct net_device *dev)
++{
++	int ret = 0;
++	struct ether_addr bssid;
++	u32 chanspec = 0;
++
++	ret = wldev_ioctl(dev, WLC_GET_BSSID, &bssid, sizeof(bssid), 0);
++	if (ret != BCME_NOTASSOCIATED && memcmp(&ether_null, &bssid, ETHER_ADDR_LEN)) {
++		if (wl_ext_iovar_getint(dev, "chanspec", (s32 *)&chanspec) == BCME_OK) {
++			chanspec = wl_ext_chspec_driver_to_host(apsta_params->ioctl_ver, chanspec);
++			return chanspec;
++		}
++	}
++
++	return 0;
++}
++
++static uint16
++wl_ext_get_chan(struct wl_apsta_params *apsta_params, struct net_device *dev)
++{
++	int ret = 0;
++	uint16 chan = 0, ctl_chan;
++	struct ether_addr bssid;
++	u32 chanspec = 0;
++
++	ret = wldev_ioctl(dev, WLC_GET_BSSID, &bssid, sizeof(bssid), 0);
++	if (ret != BCME_NOTASSOCIATED && memcmp(&ether_null, &bssid, ETHER_ADDR_LEN)) {
++		if (wl_ext_iovar_getint(dev, "chanspec", (s32 *)&chanspec) == BCME_OK) {
++			chanspec = wl_ext_chspec_driver_to_host(apsta_params->ioctl_ver, chanspec);
++			ctl_chan = wf_chspec_ctlchan(chanspec);
++			chan = (u16)(ctl_chan & 0x00FF);
++			return chan;
++		}
++	}
++
++	return 0;
++}
++
++static chanspec_t
++wl_ext_chan_to_chanspec(struct wl_apsta_params *apsta_params,
++	struct net_device *dev, uint16 channel)
++{
++	s32 _chan = channel;
++	chanspec_t chspec = 0;
++	chanspec_t fw_chspec = 0;
++	u32 bw = WL_CHANSPEC_BW_20;
++	s32 err = BCME_OK;
++	s32 bw_cap = 0;
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	struct {
++		u32 band;
++		u32 bw_cap;
++	} param = {0, 0};
++	uint band;
++
++	if (_chan <= CH_MAX_2G_CHANNEL)
++		band = IEEE80211_BAND_2GHZ;
++	else
++		band = IEEE80211_BAND_5GHZ;
++
++	if (band == IEEE80211_BAND_5GHZ) {
++		param.band = WLC_BAND_5G;
++		err = wl_ext_iovar_getbuf(dev, "bw_cap", &param, sizeof(param),
++			iovar_buf, WLC_IOCTL_SMLEN, NULL);
++		if (err) {
++			if (err != BCME_UNSUPPORTED) {
++				AEXT_ERROR(dev->name, "bw_cap failed, %d\n", err);
++				return err;
++			} else {
++				err = wl_ext_iovar_getint(dev, "mimo_bw_cap", &bw_cap);
++				if (bw_cap != WLC_N_BW_20ALL)
++					bw = WL_CHANSPEC_BW_40;
++			}
++		} else {
++			if (WL_BW_CAP_80MHZ(iovar_buf[0]))
++				bw = WL_CHANSPEC_BW_80;
++			else if (WL_BW_CAP_40MHZ(iovar_buf[0]))
++				bw = WL_CHANSPEC_BW_40;
++			else
++				bw = WL_CHANSPEC_BW_20;
++		}
++	}
++	else if (band == IEEE80211_BAND_2GHZ)
++		bw = WL_CHANSPEC_BW_20;
++
++set_channel:
++	chspec = wf_channel2chspec(_chan, bw);
++	if (wf_chspec_valid(chspec)) {
++		fw_chspec = wl_ext_chspec_host_to_driver(apsta_params->ioctl_ver, chspec);
++		if (fw_chspec == INVCHANSPEC) {
++			AEXT_ERROR(dev->name, "failed to convert host chanspec to fw chanspec\n");
++			fw_chspec = 0;
++		}
++	} else {
++		if (bw == WL_CHANSPEC_BW_80)
++			bw = WL_CHANSPEC_BW_40;
++		else if (bw == WL_CHANSPEC_BW_40)
++			bw = WL_CHANSPEC_BW_20;
++		else
++			bw = 0;
++		if (bw)
++			goto set_channel;
++		AEXT_ERROR(dev->name, "Invalid chanspec 0x%x\n", chspec);
++		err = BCME_ERROR;
++	}
++
++	return fw_chspec;
++}
++
++static bool
++wl_ext_radar_detect(struct net_device *dev)
++{
++	int ret = BCME_OK;
++	bool radar = FALSE;
++	s32 val = 0;
++
++	if ((ret = wldev_ioctl(dev, WLC_GET_RADAR, &val, sizeof(int), false) == 0)) {
++		radar = TRUE;
++	}
++
++	return radar;
++}
++
++static void
++wl_ext_wait_netif_change(struct wl_apsta_params *apsta_params,
++	struct wl_if_info *cur_if)
++{
++	rtnl_unlock();
++	wait_event_interruptible_timeout(apsta_params->netif_change_event,
++		wl_get_isam_status(cur_if, IF_READY),
++		msecs_to_jiffies(MAX_AP_LINK_WAIT_TIME));
++	rtnl_lock();
++}
++
++static void
++wl_ext_interface_create(struct net_device *dev, struct wl_apsta_params *apsta_params,
++	struct wl_if_info *cur_if, int iftype, u8 *addr)
++{
++	wl_interface_create_t iface;
++	u8 iovar_buf[WLC_IOCTL_SMLEN];
++
++	bzero(&iface, sizeof(iface));
++	if (addr) {
++		iftype |= WL_INTERFACE_MAC_USE;
++	}
++	iface.ver = WL_INTERFACE_CREATE_VER;
++	iface.flags = iftype;
++	if (addr) {
++		memcpy(&iface.mac_addr.octet, addr, ETH_ALEN);
++	}
++	wl_set_isam_status(cur_if, IF_ADDING);
++	wl_ext_iovar_getbuf(dev, "interface_create", &iface, sizeof(iface),
++		iovar_buf, WLC_IOCTL_SMLEN, NULL);
++	wl_ext_wait_netif_change(apsta_params, cur_if);
++}
++
++static void
++wl_ext_iapsta_intf_add(struct net_device *dev, struct wl_apsta_params *apsta_params)
++{
++	struct dhd_pub *dhd;
++	apstamode_t apstamode = apsta_params->apstamode;
++	struct wl_if_info *cur_if;
++	wlc_ssid_t ssid = { 0, {0} };
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	wl_p2p_if_t ifreq;
++	struct ether_addr mac_addr;
++
++	dhd = dhd_get_pub(dev);
++	bzero(&mac_addr, sizeof(mac_addr));
++
++	if (apstamode == ISTAAP_MODE) {
++		cur_if = &apsta_params->if_info[IF_VIF];
++		if (FW_SUPPORTED(dhd, rsdb)) {
++			wl_ext_interface_create(dev, apsta_params, cur_if, WL_INTERFACE_CREATE_AP, NULL);
++		} else {
++			wl_set_isam_status(cur_if, IF_ADDING);
++			wl_ext_iovar_setbuf_bsscfg(dev, "ssid", &ssid, sizeof(ssid),
++				iovar_buf, WLC_IOCTL_SMLEN, 1, NULL);
++			wl_ext_wait_netif_change(apsta_params, cur_if);
++		}
++	}
++	else if (apstamode == ISTAGO_MODE) {
++		bzero(&ifreq, sizeof(wl_p2p_if_t));
++		ifreq.type = htod32(WL_P2P_IF_GO);
++		cur_if = &apsta_params->if_info[IF_VIF];
++		wl_set_isam_status(cur_if, IF_ADDING);
++		wl_ext_iovar_setbuf(dev, "p2p_ifadd", &ifreq, sizeof(ifreq),
++			iovar_buf, WLC_IOCTL_SMLEN, NULL);
++		wl_ext_wait_netif_change(apsta_params, cur_if);
++	}
++	else if (apstamode == ISTASTA_MODE) {
++		cur_if = &apsta_params->if_info[IF_VIF];
++		memcpy(&mac_addr, dev->dev_addr, ETHER_ADDR_LEN);
++		mac_addr.octet[0] |= 0x02;
++		wl_ext_interface_create(dev, apsta_params, cur_if, WL_INTERFACE_CREATE_STA,
++			(u8*)&mac_addr);
++	}
++	else if (apstamode == IDUALAP_MODE) {
++		cur_if = &apsta_params->if_info[IF_VIF];
++		wl_ext_interface_create(dev, apsta_params, cur_if, WL_INTERFACE_CREATE_AP, NULL);
++	}
++	else if (apstamode == ISTAAPAP_MODE) {
++		u8 rand_bytes[2] = {0, };
++		get_random_bytes(&rand_bytes, sizeof(rand_bytes));
++		cur_if = &apsta_params->if_info[IF_VIF];
++		memcpy(&mac_addr, dev->dev_addr, ETHER_ADDR_LEN);
++		mac_addr.octet[0] |= 0x02;
++		mac_addr.octet[5] += 0x01;
++		memcpy(&mac_addr.octet[3], rand_bytes, sizeof(rand_bytes));
++		wl_ext_interface_create(dev, apsta_params, cur_if, WL_INTERFACE_CREATE_AP,
++			(u8*)&mac_addr);
++		cur_if = &apsta_params->if_info[IF_VIF2];
++		memcpy(&mac_addr, dev->dev_addr, ETHER_ADDR_LEN);
++		mac_addr.octet[0] |= 0x02;
++		mac_addr.octet[5] += 0x02;
++		memcpy(&mac_addr.octet[3], rand_bytes, sizeof(rand_bytes));
++		wl_ext_interface_create(dev, apsta_params, cur_if, WL_INTERFACE_CREATE_AP,
++			(u8*)&mac_addr);
++	}
++#ifdef WLMESH
++	else if (apstamode == ISTAMESH_MODE) {
++		cur_if = &apsta_params->if_info[IF_VIF];
++		wl_ext_interface_create(dev, apsta_params, cur_if, WL_INTERFACE_CREATE_STA, NULL);
++	}
++	else if (apstamode == IMESHAP_MODE) {
++		cur_if = &apsta_params->if_info[IF_VIF];
++		wl_ext_interface_create(dev, apsta_params, cur_if, WL_INTERFACE_CREATE_AP, NULL);
++	}
++	else if (apstamode == ISTAAPMESH_MODE) {
++		cur_if = &apsta_params->if_info[IF_VIF];
++		wl_ext_interface_create(dev, apsta_params, cur_if, WL_INTERFACE_CREATE_AP, NULL);
++		cur_if = &apsta_params->if_info[IF_VIF2];
++		wl_ext_interface_create(dev, apsta_params, cur_if, WL_INTERFACE_CREATE_STA, NULL);
++	}
++	else if (apstamode == IMESHAPAP_MODE) {
++		cur_if = &apsta_params->if_info[IF_VIF];
++		wl_ext_interface_create(dev, apsta_params, cur_if, WL_INTERFACE_CREATE_AP, NULL);
++		cur_if = &apsta_params->if_info[IF_VIF2];
++		wl_ext_interface_create(dev, apsta_params, cur_if, WL_INTERFACE_CREATE_AP, NULL);
++	}
++#endif /* WLMESH */
++
++}
++
++static void
++wl_ext_iapsta_preinit(struct net_device *dev, struct wl_apsta_params *apsta_params)
++{
++	struct dhd_pub *dhd;
++	apstamode_t apstamode = apsta_params->apstamode;
++	struct wl_if_info *cur_if;
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	s32 val = 0;
++	int i;
++
++	dhd = dhd_get_pub(dev);
++
++	for (i=0; i<MAX_IF_NUM; i++) {
++		cur_if = &apsta_params->if_info[i];
++		if (i >= 1 && !strlen(cur_if->ifname))
++			snprintf(cur_if->ifname, IFNAMSIZ, "wlan%d", i);
++		if (cur_if->ifmode == ISTA_MODE) {
++			cur_if->channel = 0;
++			cur_if->maxassoc = -1;
++			cur_if->prio = PRIO_STA;
++			cur_if->prefix = 'S';
++			snprintf(cur_if->ssid, DOT11_MAX_SSID_LEN, "ttt_sta");
++		} else if (cur_if->ifmode == IAP_MODE) {
++			cur_if->channel = 1;
++			cur_if->maxassoc = -1;
++			cur_if->prio = PRIO_AP;
++			cur_if->prefix = 'A';
++			snprintf(cur_if->ssid, DOT11_MAX_SSID_LEN, "ttt_ap");
++#ifdef WLMESH
++		} else if (cur_if->ifmode == IMESH_MODE) {
++			cur_if->channel = 1;
++			cur_if->maxassoc = -1;
++			cur_if->prio = PRIO_MESH;
++			cur_if->prefix = 'M';
++			snprintf(cur_if->ssid, DOT11_MAX_SSID_LEN, "ttt_mesh");
++#ifdef WL_ESCAN
++			if (i == 0 && apsta_params->macs)
++				wl_mesh_escan_attach(dhd, cur_if);
++#endif /* WL_ESCAN */
++#endif /* WLMESH */
++		}
++	}
++
++	if (FW_SUPPORTED(dhd, rsdb)) {
++		if (apstamode == IDUALAP_MODE)
++			apsta_params->rsdb = -1;
++		else if (apstamode == ISTAAPAP_MODE)
++			apsta_params->rsdb = 0;
++		if (apstamode == ISTAAPAP_MODE || apstamode == IDUALAP_MODE ||
++				apstamode == IMESHONLY_MODE || apstamode == ISTAMESH_MODE ||
++				apstamode == IMESHAP_MODE || apstamode == ISTAAPMESH_MODE ||
++				apstamode == IMESHAPAP_MODE) {
++			wl_config_t rsdb_mode_cfg = {0, 0};
++			rsdb_mode_cfg.config = apsta_params->rsdb;
++			AEXT_INFO(dev->name, "set rsdb_mode %d\n", rsdb_mode_cfg.config);
++			wl_ext_ioctl(dev, WLC_DOWN, NULL, 0, 1);
++			wl_ext_iovar_setbuf(dev, "rsdb_mode", &rsdb_mode_cfg,
++				sizeof(rsdb_mode_cfg), iovar_buf, sizeof(iovar_buf), NULL);
++			wl_ext_ioctl(dev, WLC_UP, NULL, 0, 1);
++		}
++	} else {
++		apsta_params->rsdb = 0;
++	}
++
++	if (apstamode == ISTAONLY_MODE) {
++		wl_ext_ioctl(dev, WLC_DOWN, NULL, 0, 1);
++		wl_ext_iovar_setint(dev, "apsta", 1); // keep 1 as we set in dhd_preinit_ioctls
++		// don't set WLC_SET_AP to 0, some parameters will be reset, such as bcn_timeout and roam_off
++		wl_ext_ioctl(dev, WLC_UP, NULL, 0, 1);
++	} else if (apstamode == IAPONLY_MODE) {
++		wl_ext_ioctl(dev, WLC_DOWN, NULL, 0, 1);
++#ifdef ARP_OFFLOAD_SUPPORT
++		/* IF SoftAP is enabled, disable arpoe */
++		dhd_arp_offload_set(dhd, 0);
++		dhd_arp_offload_enable(dhd, FALSE);
++#endif /* ARP_OFFLOAD_SUPPORT */
++		wl_ext_iovar_setint(dev, "mpc", 0);
++		wl_ext_iovar_setint(dev, "apsta", 0);
++		val = 1;
++		wl_ext_ioctl(dev, WLC_SET_AP, &val, sizeof(val), 1);
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO)
++		if (!(FW_SUPPORTED(dhd, rsdb)) && !disable_proptx) {
++			bool enabled;
++			dhd_wlfc_get_enable(dhd, &enabled);
++			if (!enabled) {
++				dhd_wlfc_init(dhd);
++				wl_ext_ioctl(dev, WLC_UP, NULL, 0, 1);
++			}
++		}
++#endif /* BCMSDIO */
++#endif /* PROP_TXSTATUS_VSDB */
++	}
++	else if (apstamode == ISTAAP_MODE) {
++		wl_ext_ioctl(dev, WLC_DOWN, NULL, 0, 1);
++		wl_ext_iovar_setint(dev, "mpc", 0);
++		wl_ext_iovar_setint(dev, "apsta", 1);
++		wl_ext_ioctl(dev, WLC_UP, NULL, 0, 1);
++	}
++	else if (apstamode == ISTAGO_MODE) {
++		wl_ext_ioctl(dev, WLC_DOWN, NULL, 0, 1);
++		wl_ext_iovar_setint(dev, "apsta", 1);
++		wl_ext_ioctl(dev, WLC_UP, NULL, 0, 1);
++	}
++	else if (apstamode == ISTASTA_MODE) {
++	}
++	else if (apstamode == IDUALAP_MODE) {
++		wl_ext_ioctl(dev, WLC_DOWN, NULL, 0, 1);
++		/* IF SoftAP is enabled, disable arpoe or wlan1 will ping fail */
++#ifdef ARP_OFFLOAD_SUPPORT
++		/* IF SoftAP is enabled, disable arpoe */
++		dhd_arp_offload_set(dhd, 0);
++		dhd_arp_offload_enable(dhd, FALSE);
++#endif /* ARP_OFFLOAD_SUPPORT */
++		wl_ext_iovar_setint(dev, "mpc", 0);
++		wl_ext_iovar_setint(dev, "mbcn", 1);
++		wl_ext_iovar_setint(dev, "apsta", 0);
++		wl_ext_ioctl(dev, WLC_UP, NULL, 0, 1);
++		val = 1;
++		wl_ext_ioctl(dev, WLC_SET_AP, &val, sizeof(val), 1);
++	}
++	else if (apstamode == ISTAAPAP_MODE) {
++		wl_ext_ioctl(dev, WLC_DOWN, NULL, 0, 1);
++		wl_ext_iovar_setint(dev, "mpc", 0);
++		wl_ext_iovar_setint(dev, "mbss", 1);
++		wl_ext_iovar_setint(dev, "apsta", 1); // keep 1 as we set in dhd_preinit_ioctls
++		wl_ext_ioctl(dev, WLC_UP, NULL, 0, 1);
++		// don't set WLC_SET_AP to 0, some parameters will be reset, such as bcn_timeout and roam_off
++	}
++#ifdef WLMESH
++	else if (apstamode == IMESHONLY_MODE || apstamode == ISTAMESH_MODE ||
++			apstamode == IMESHAP_MODE || apstamode == ISTAAPMESH_MODE ||
++			apstamode == IMESHAPAP_MODE) {
++		int pm = 0;
++		wl_ext_ioctl(dev, WLC_DOWN, NULL, 0, 1);
++		wl_ext_iovar_setint(dev, "mpc", 0);
++		if (apstamode == IMESHONLY_MODE)
++			wl_ext_ioctl(dev, WLC_SET_PM, &pm, sizeof(pm), 1);
++		else
++			wl_ext_iovar_setint(dev, "mbcn", 1);
++		wl_ext_iovar_setint(dev, "apsta", 1); // keep 1 as we set in dhd_preinit_ioctls
++		wl_ext_ioctl(dev, WLC_UP, NULL, 0, 1);
++		// don't set WLC_SET_AP to 0, some parameters will be reset, such as bcn_timeout and roam_off
++	}
++#endif /* WLMESH */
++
++	wl_ext_get_ioctl_ver(dev, &apsta_params->ioctl_ver);
++	apsta_params->init = TRUE;
++
++	WL_MSG(dev->name, "apstamode=%d\n", apstamode);
++}
++
++static int
++wl_ext_isam_param(struct net_device *dev, char *command, int total_len)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++	int ret = -1;
++	char *pick_tmp, *data, *param;
++	int bytes_written=-1;
++
++	AEXT_TRACE(dev->name, "command=%s, len=%d\n", command, total_len);
++
++	pick_tmp = command;
++	param = bcmstrtok(&pick_tmp, " ", 0); // pick isam_param
++	param = bcmstrtok(&pick_tmp, " ", 0); // pick cmd
++	while (param != NULL) {
++		data = bcmstrtok(&pick_tmp, " ", 0); // pick data
++		if (!strcmp(param, "acs")) {
++			if (data) {
++				apsta_params->acs = simple_strtol(data, NULL, 0);
++				ret = 0;
++			} else {
++				bytes_written = snprintf(command, total_len, "%d", apsta_params->acs);
++				ret = bytes_written;
++				goto exit;
++			}
++		}
++		param = bcmstrtok(&pick_tmp, " ", 0); // pick cmd
++	}
++
++exit:
++	return ret;
++}
++
++static int
++wl_ext_isam_init(struct net_device *dev, char *command, int total_len)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	char *pch, *pick_tmp, *pick_tmp2, *param;
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++	int i;
++
++	if (apsta_params->init) {
++		AEXT_ERROR(dev->name, "don't init twice\n");
++		return -1;
++	}
++	AEXT_TRACE(dev->name, "command=%s, len=%d\n", command, total_len);
++
++	pick_tmp = command;
++	param = bcmstrtok(&pick_tmp, " ", 0); // skip iapsta_init
++	param = bcmstrtok(&pick_tmp, " ", 0);
++	while (param != NULL) {
++		pick_tmp2 = bcmstrtok(&pick_tmp, " ", 0);
++		if (!pick_tmp2) {
++			AEXT_ERROR(dev->name, "wrong param %s\n", param);
++			return -1;
++		}
++		if (!strcmp(param, "mode")) {
++			pch = NULL;
++			if (!strcmp(pick_tmp2, "sta")) {
++				apsta_params->apstamode = ISTAONLY_MODE;
++			} else if (!strcmp(pick_tmp2, "ap")) {
++				apsta_params->apstamode = IAPONLY_MODE;
++			} else if (!strcmp(pick_tmp2, "sta-ap")) {
++				apsta_params->apstamode = ISTAAP_MODE;
++			} else if (!strcmp(pick_tmp2, "sta-sta")) {
++				apsta_params->apstamode = ISTASTA_MODE;
++				apsta_params->vsdb = TRUE;
++			} else if (!strcmp(pick_tmp2, "ap-ap")) {
++				apsta_params->apstamode = IDUALAP_MODE;
++			} else if (!strcmp(pick_tmp2, "sta-ap-ap")) {
++				apsta_params->apstamode = ISTAAPAP_MODE;
++			} else if (!strcmp(pick_tmp2, "apsta")) {
++				apsta_params->apstamode = ISTAAP_MODE;
++				apsta_params->if_info[IF_PIF].ifmode = ISTA_MODE;
++				apsta_params->if_info[IF_VIF].ifmode = IAP_MODE;
++			} else if (!strcmp(pick_tmp2, "dualap")) {
++				apsta_params->apstamode = IDUALAP_MODE;
++				apsta_params->if_info[IF_PIF].ifmode = IAP_MODE;
++				apsta_params->if_info[IF_VIF].ifmode = IAP_MODE;
++			} else if (!strcmp(pick_tmp2, "sta-go") ||
++					!strcmp(pick_tmp2, "gosta")) {
++				if (!FW_SUPPORTED(dhd, p2p)) {
++					return -1;
++				}
++				apsta_params->apstamode = ISTAGO_MODE;
++				apsta_params->if_info[IF_PIF].ifmode = ISTA_MODE;
++				apsta_params->if_info[IF_VIF].ifmode = IAP_MODE;
++#ifdef WLMESH
++			} else if (!strcmp(pick_tmp2, "mesh")) {
++				apsta_params->apstamode = IMESHONLY_MODE;
++			} else if (!strcmp(pick_tmp2, "sta-mesh")) {
++				apsta_params->apstamode = ISTAMESH_MODE;
++			} else if (!strcmp(pick_tmp2, "sta-ap-mesh")) {
++				apsta_params->apstamode = ISTAAPMESH_MODE;
++			} else if (!strcmp(pick_tmp2, "mesh-ap")) {
++				apsta_params->apstamode = IMESHAP_MODE;
++			} else if (!strcmp(pick_tmp2, "mesh-ap-ap")) {
++				apsta_params->apstamode = IMESHAPAP_MODE;
++#endif /* WLMESH */
++			} else {
++				AEXT_ERROR(dev->name, "mode [sta|ap|sta-ap|ap-ap]\n");
++				return -1;
++			}
++			pch = bcmstrtok(&pick_tmp2, " -", 0);
++			for (i=0; i<MAX_IF_NUM && pch; i++) {
++				if (!strcmp(pch, "sta"))
++					apsta_params->if_info[i].ifmode = ISTA_MODE;
++				else if (!strcmp(pch, "ap"))
++					apsta_params->if_info[i].ifmode = IAP_MODE;
++#ifdef WLMESH
++				else if (!strcmp(pch, "mesh")) {
++					if (dhd->conf->fw_type != FW_TYPE_MESH) {
++						AEXT_ERROR(dev->name, "wrong fw type\n");
++						return -1;
++					}
++					apsta_params->if_info[i].ifmode = IMESH_MODE;
++				}
++#endif /* WLMESH */
++				pch = bcmstrtok(&pick_tmp2, " -", 0);
++			}
++		}
++		else if (!strcmp(param, "rsdb")) {
++			apsta_params->rsdb = (int)simple_strtol(pick_tmp2, NULL, 0);
++		} else if (!strcmp(param, "vsdb")) {
++			if (!strcmp(pick_tmp2, "y")) {
++				apsta_params->vsdb = TRUE;
++			} else if (!strcmp(pick_tmp2, "n")) {
++				apsta_params->vsdb = FALSE;
++			} else {
++				AEXT_ERROR(dev->name, "vsdb [y|n]\n");
++				return -1;
++			}
++		} else if (!strcmp(param, "csa")) {
++			apsta_params->csa = (int)simple_strtol(pick_tmp2, NULL, 0);
++		} else if (!strcmp(param, "acs")) {
++			apsta_params->acs = (int)simple_strtol(pick_tmp2, NULL, 0);
++#if defined(WLMESH) && defined(WL_ESCAN)
++		} else if (!strcmp(param, "macs")) {
++			apsta_params->macs = (int)simple_strtol(pick_tmp2, NULL, 0);
++#endif /* WLMESH && WL_ESCAN */
++		} else if (!strcmp(param, "ifname")) {
++			pch = NULL;
++			pch = bcmstrtok(&pick_tmp2, " -", 0);
++			for (i=0; i<MAX_IF_NUM && pch; i++) {
++				strcpy(apsta_params->if_info[i].ifname, pch);
++				pch = bcmstrtok(&pick_tmp2, " -", 0);
++			}
++		} else if (!strcmp(param, "vifname")) {
++			strcpy(apsta_params->if_info[IF_VIF].ifname, pick_tmp2);
++		}
++		param = bcmstrtok(&pick_tmp, " ", 0);
++	}
++
++	if (apsta_params->apstamode == 0) {
++		AEXT_ERROR(dev->name, "mode [sta|ap|sta-ap|ap-ap]\n");
++		return -1;
++	}
++
++	wl_ext_iapsta_preinit(dev, apsta_params);
++	wl_ext_iapsta_intf_add(dev, apsta_params);
++
++	return 0;
++}
++
++static int
++wl_ext_parse_config(struct wl_if_info *cur_if, char *command, char **pick_next)
++{
++	char *pch, *pick_tmp;
++	char name[20], data[100];
++	int i, j, len;
++	char *ifname_head = NULL;
++
++	typedef struct config_map_t {
++		char name[20];
++		char *head;
++		char *tail;
++	} config_map_t;
++
++	config_map_t config_map [] = {
++		{" ifname ",	NULL, NULL},
++		{" ssid ",		NULL, NULL},
++		{" bssid ", 	NULL, NULL},
++		{" bgnmode ",	NULL, NULL},
++		{" hidden ",	NULL, NULL},
++		{" maxassoc ",	NULL, NULL},
++		{" chan ",		NULL, NULL},
++		{" amode ", 	NULL, NULL},
++		{" emode ", 	NULL, NULL},
++		{" key ",		NULL, NULL},
++	};
++	config_map_t *row, *row_prev;
++
++	pick_tmp = command;
++
++	// reset head and tail
++	for (i = 0; i < sizeof(config_map)/sizeof(config_map[0]); i++) {
++		row = &config_map[i];
++		row->head = NULL;
++		row->tail = pick_tmp + strlen(pick_tmp);
++	}
++
++	// pick head
++	for (i = 0; i < sizeof(config_map)/sizeof(config_map[0]); i++) {
++		row = &config_map[i];
++		pch = strstr(pick_tmp, row->name);
++		if (pch) {
++			row->head = pch;
++		}
++	}
++
++	// sort by head
++	for (i = 0; i < sizeof(config_map)/sizeof(config_map[0]) - 1; i++) {
++		row_prev = &config_map[i];
++		for (j = i+1; j < sizeof(config_map)/sizeof(config_map[0]); j++) {
++			row = &config_map[j];
++			if (row->head < row_prev->head) {
++				strcpy(name, row_prev->name);
++				strcpy(row_prev->name, row->name);
++				strcpy(row->name, name);
++				pch = row_prev->head;
++				row_prev->head = row->head;
++				row->head = pch;
++			}
++		}
++	}
++
++	// pick tail
++	for (i = 0; i < sizeof(config_map)/sizeof(config_map[0]) - 1; i++) {
++		row_prev = &config_map[i];
++		row = &config_map[i+1];
++		if (row_prev->head) {
++			row_prev->tail = row->head;
++		}
++	}
++
++	// remove name from head
++	for (i = 0; i < sizeof(config_map)/sizeof(config_map[0]); i++) {
++		row = &config_map[i];
++		if (row->head) {
++			if (!strcmp(row->name, " ifname ")) {
++				ifname_head = row->head + 1;
++				break;
++			}
++			row->head += strlen(row->name);
++		}
++	}
++
++	for (i = 0; i < sizeof(config_map)/sizeof(config_map[0]); i++) {
++		row = &config_map[i];
++		if (row->head) {
++			memset(data, 0, sizeof(data));
++			if (row->tail && row->tail > row->head) {
++				strncpy(data, row->head, row->tail-row->head);
++			} else {
++				strcpy(data, row->head);
++			}
++			pick_tmp = data;
++
++			if (!strcmp(row->name, " ifname ")) {
++				break;
++			} else if (!strcmp(row->name, " ssid ")) {
++				len = strlen(pick_tmp);
++				memset(cur_if->ssid, 0, sizeof(cur_if->ssid));
++				if (pick_tmp[0] == '"' && pick_tmp[len-1] == '"')
++					strncpy(cur_if->ssid, &pick_tmp[1], len-2);
++				else
++					strcpy(cur_if->ssid, pick_tmp);
++			} else if (!strcmp(row->name, " bssid ")) {
++				pch = bcmstrtok(&pick_tmp, ": ", 0);
++				for (j=0; j<6 && pch; j++) {
++					((u8 *)&cur_if->bssid)[j] = (int)simple_strtol(pch, NULL, 16);
++					pch = bcmstrtok(&pick_tmp, ": ", 0);
++				}
++			} else if (!strcmp(row->name, " bgnmode ")) {
++				if (!strcmp(pick_tmp, "b"))
++					cur_if->bgnmode = IEEE80211B;
++				else if (!strcmp(pick_tmp, "g"))
++					cur_if->bgnmode = IEEE80211G;
++				else if (!strcmp(pick_tmp, "bg"))
++					cur_if->bgnmode = IEEE80211BG;
++				else if (!strcmp(pick_tmp, "bgn"))
++					cur_if->bgnmode = IEEE80211BGN;
++				else if (!strcmp(pick_tmp, "bgnac"))
++					cur_if->bgnmode = IEEE80211BGNAC;
++				else {
++					AEXT_ERROR(cur_if->dev->name, "bgnmode [b|g|bg|bgn|bgnac]\n");
++					return -1;
++				}
++			} else if (!strcmp(row->name, " hidden ")) {
++				if (!strcmp(pick_tmp, "n"))
++					cur_if->hidden = 0;
++				else if (!strcmp(pick_tmp, "y"))
++					cur_if->hidden = 1;
++				else {
++					AEXT_ERROR(cur_if->dev->name, "hidden [y|n]\n");
++					return -1;
++				}
++			} else if (!strcmp(row->name, " maxassoc ")) {
++				cur_if->maxassoc = (int)simple_strtol(pick_tmp, NULL, 10);
++			} else if (!strcmp(row->name, " chan ")) {
++				cur_if->channel = (int)simple_strtol(pick_tmp, NULL, 10);
++			} else if (!strcmp(row->name, " amode ")) {
++				if (!strcmp(pick_tmp, "open"))
++					cur_if->amode = AUTH_OPEN;
++				else if (!strcmp(pick_tmp, "shared"))
++					cur_if->amode = AUTH_SHARED;
++				else if (!strcmp(pick_tmp, "wpapsk"))
++					cur_if->amode = AUTH_WPAPSK;
++				else if (!strcmp(pick_tmp, "wpa2psk"))
++					cur_if->amode = AUTH_WPA2PSK;
++				else if (!strcmp(pick_tmp, "wpawpa2psk"))
++					cur_if->amode = AUTH_WPAWPA2PSK;
++				else if (!strcmp(pick_tmp, "sae"))
++					cur_if->amode = AUTH_SAE;
++				else {
++					AEXT_ERROR(cur_if->dev->name, "amode [open|shared|wpapsk|wpa2psk|wpawpa2psk]\n");
++					return -1;
++				}
++			} else if (!strcmp(row->name, " emode ")) {
++				if (!strcmp(pick_tmp, "none"))
++					cur_if->emode = ENC_NONE;
++				else if (!strcmp(pick_tmp, "wep"))
++					cur_if->emode = ENC_WEP;
++				else if (!strcmp(pick_tmp, "tkip"))
++					cur_if->emode = ENC_TKIP;
++				else if (!strcmp(pick_tmp, "aes"))
++					cur_if->emode = ENC_AES;
++				else if (!strcmp(pick_tmp, "tkipaes"))
++					cur_if->emode = ENC_TKIPAES;
++				else {
++					AEXT_ERROR(cur_if->dev->name, "emode [none|wep|tkip|aes|tkipaes]\n");
++					return -1;
++				}
++			} else if (!strcmp(row->name, " key ")) {
++				len = strlen(pick_tmp);
++				memset(cur_if->key, 0, sizeof(cur_if->key));
++				if (pick_tmp[0] == '"' && pick_tmp[len-1] == '"')
++					strncpy(cur_if->key, &pick_tmp[1], len-2);
++				else
++					strcpy(cur_if->key, pick_tmp);
++			}
++		}
++	}
++
++	*pick_next = ifname_head;
++	return 0;
++}
++
++static int
++wl_ext_iapsta_config(struct net_device *dev, char *command, int total_len)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	int ret=0, i;
++	char *pch, *pch2, *pick_tmp, *pick_next=NULL, *param;
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++	char ifname[IFNAMSIZ+1];
++	struct wl_if_info *cur_if = NULL, *tmp_if = NULL;
++
++	if (!apsta_params->init) {
++		AEXT_ERROR(dev->name, "please init first\n");
++		return -1;
++	}
++
++	AEXT_TRACE(dev->name, "command=%s, len=%d\n", command, total_len);
++
++	pick_tmp = command;
++	param = bcmstrtok(&pick_tmp, " ", 0); // skip iapsta_config
++
++	mutex_lock(&apsta_params->usr_sync);
++
++	while (pick_tmp != NULL) {
++		memset(ifname, 0, IFNAMSIZ+1);
++		if (!strncmp(pick_tmp, "ifname ", strlen("ifname "))) {
++			pch = pick_tmp + strlen("ifname ");
++			pch2 = strchr(pch, ' ');
++			if (pch && pch2) {
++				strncpy(ifname, pch, pch2-pch);
++			} else {
++				AEXT_ERROR(dev->name, "ifname [wlanX]\n");
++				ret = -1;
++				break;
++			}
++			for (i=0; i<MAX_IF_NUM; i++) {
++				tmp_if = &apsta_params->if_info[i];
++				if (tmp_if->dev && !strcmp(tmp_if->dev->name, ifname)) {
++					cur_if = tmp_if;
++					break;
++				}
++			}
++			if (!cur_if) {
++				AEXT_ERROR(dev->name, "wrong ifname=%s in apstamode=%d\n",
++					ifname, apsta_params->apstamode);
++				ret = -1;
++				break;
++			}
++			ret = wl_ext_parse_config(cur_if, pick_tmp, &pick_next);
++			if (ret)
++				break;
++			pick_tmp = pick_next;
++		} else {
++			AEXT_ERROR(dev->name, "first arg must be ifname\n");
++			ret = -1;
++			break;
++		}
++
++	}
++
++	mutex_unlock(&apsta_params->usr_sync);
++
++	return ret;
++}
++
++static int
++wl_ext_assoclist(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	int ret = 0, i, maxassoc = 0, bytes_written = 0;
++	char mac_buf[MAX_NUM_OF_ASSOCLIST *
++		sizeof(struct ether_addr) + sizeof(uint)] = {0};
++	struct maclist *assoc_maclist = (struct maclist *)mac_buf;
++
++	assoc_maclist->count = htod32(MAX_NUM_OF_ASSOCLIST);
++	ret = wl_ext_ioctl(dev, WLC_GET_ASSOCLIST, assoc_maclist, sizeof(mac_buf), 0);
++	if (ret)
++		return -1;
++	maxassoc = dtoh32(assoc_maclist->count);
++	bytes_written += snprintf(command+bytes_written, total_len,
++		"%2s: %12s",
++		"no", "------addr------");
++	for (i=0; i<maxassoc; i++) {
++		bytes_written += snprintf(command+bytes_written, total_len,
++			"\n%2d: %pM", i, &assoc_maclist->ea[i]);
++	}
++
++	return bytes_written;
++}
++
++#ifdef WLMESH
++static int
++wl_mesh_print_peer_info(mesh_peer_info_ext_t *mpi_ext,
++	uint32 peer_results_count, char *command, int total_len)
++{
++	char *peering_map[] = MESH_PEERING_STATE_STRINGS;
++	uint32 count = 0;
++	int bytes_written = 0;
++
++	bytes_written += snprintf(command+bytes_written, total_len,
++		"%2s: %12s : %6s : %-6s : %6s :"
++		" %5s : %4s : %4s : %11s : %4s",
++		"no", "------addr------ ", "l.aid", "state", "p.aid",
++		"mppid", "llid", "plid", "entry_state", "rssi");
++	for (count=0; count < peer_results_count; count++) {
++		if (mpi_ext->entry_state != MESH_SELF_PEER_ENTRY_STATE_TIMEDOUT) {
++			bytes_written += snprintf(command+bytes_written, total_len,
++				"\n%2d: %pM : 0x%4x : %6s : 0x%4x :"
++				" %5d : %4d : %4d : %11s : %4d",
++				count, &mpi_ext->ea, mpi_ext->local_aid,
++				peering_map[mpi_ext->peer_info.state],
++				mpi_ext->peer_info.peer_aid,
++				mpi_ext->peer_info.mesh_peer_prot_id,
++				mpi_ext->peer_info.local_link_id,
++				mpi_ext->peer_info.peer_link_id,
++				(mpi_ext->entry_state == MESH_SELF_PEER_ENTRY_STATE_ACTIVE) ?
++				"ACTIVE" :
++				"EXTERNAL",
++				mpi_ext->rssi);
++		} else {
++			bytes_written += snprintf(command+bytes_written, total_len,
++				"\n%2d: %pM : %6s : %5s : %6s :"
++				" %5s : %4s : %4s : %11s : %4s",
++				count, &mpi_ext->ea, "  NA  ", "  NA  ", "  NA  ",
++				"  NA ", " NA ", " NA ", "  TIMEDOUT ", " NA ");
++		}
++		mpi_ext++;
++	}
++
++	return bytes_written;
++}
++
++static int
++wl_mesh_get_peer_results(struct net_device *dev, char *buf, int len)
++{
++	int indata, inlen;
++	mesh_peer_info_dump_t *peer_results;
++	int ret;
++
++	memset(buf, 0, len);
++	peer_results = (mesh_peer_info_dump_t *)buf;
++	indata = htod32(len);
++	inlen = 4;
++	ret = wl_ext_iovar_getbuf(dev, "mesh_peer_status", &indata, inlen, buf, len, NULL);
++	if (!ret) {
++		peer_results = (mesh_peer_info_dump_t *)buf;
++		ret = peer_results->count;
++	}
++
++	return ret;
++}
++
++static int
++wl_ext_mesh_peer_status(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++	int i;
++	struct wl_if_info *cur_if;
++	mesh_peer_info_dump_t *peer_results;
++	mesh_peer_info_ext_t *mpi_ext;
++	char *peer_buf = NULL;
++	int peer_len = WLC_IOCTL_MAXLEN;
++	int dump_written = 0, ret;
++
++	if (!data) {
++		peer_buf = kmalloc(peer_len, GFP_KERNEL);
++		if (peer_buf == NULL) {
++			AEXT_ERROR(dev->name, "Failed to allocate buffer of %d bytes\n",
++				peer_len); 
++			return -1;
++		}
++		for (i=0; i<MAX_IF_NUM; i++) {
++			cur_if = &apsta_params->if_info[i];
++			if (cur_if && dev == cur_if->dev && cur_if->ifmode == IMESH_MODE) {
++				memset(peer_buf, 0, peer_len);
++				ret = wl_mesh_get_peer_results(dev, peer_buf, peer_len);
++				if (ret >= 0) {
++					peer_results = (mesh_peer_info_dump_t *)peer_buf;
++					mpi_ext = (mesh_peer_info_ext_t *)peer_results->mpi_ext;
++					dump_written += wl_mesh_print_peer_info(mpi_ext,
++						peer_results->count, command+dump_written,
++						total_len-dump_written);
++				}
++			} else if (cur_if && dev == cur_if->dev) {
++				AEXT_ERROR(dev->name, "[%s][%c] is not mesh interface\n",
++					cur_if->ifname, cur_if->prefix);
++			}
++		}
++	}
++
++	if (peer_buf)
++		kfree(peer_buf);
++	return dump_written;
++}
++
++#ifdef WL_ESCAN
++#define WL_MESH_DELAY_SCAN_MS	3000
++static void
++wl_mesh_timer(unsigned long data)
++{
++	wl_event_msg_t msg;
++	struct wl_if_info *mesh_if = (struct wl_if_info *)data;
++	struct dhd_pub *dhd;
++
++	if (!mesh_if) {
++		AEXT_ERROR("wlan", "mesh_if is not ready\n");
++		return;
++	}
++
++	if (!mesh_if->dev) {
++		AEXT_ERROR("wlan", "ifidx %d is not ready\n", mesh_if->ifidx);
++		return;
++	}
++	dhd = dhd_get_pub(mesh_if->dev);
++
++	bzero(&msg, sizeof(wl_event_msg_t));
++	AEXT_TRACE(mesh_if->dev->name, "timer expired\n");
++
++	msg.ifidx = mesh_if->ifidx;
++	msg.event_type = hton32(WLC_E_RESERVED);
++	msg.reason = 0xFFFFFFFF;
++	wl_ext_event_send(dhd->event_params, &msg, NULL);
++}
++
++static void
++wl_mesh_set_timer(struct wl_if_info *mesh_if, uint timeout)
++{
++	AEXT_TRACE(mesh_if->dev->name, "timeout=%d\n", timeout);
++
++	if (timer_pending(&mesh_if->delay_scan))
++		_del_timer_sync(&mesh_if->delay_scan);
++
++	if (timeout) {
++		if (timer_pending(&mesh_if->delay_scan))
++			_del_timer_sync(&mesh_if->delay_scan);
++		mod_timer(&mesh_if->delay_scan, jiffies + msecs_to_jiffies(timeout));
++	}
++}
++
++static struct wl_if_info *
++wl_ext_if_enabled(struct wl_apsta_params *apsta_params, ifmode_t ifmode)
++{
++	struct wl_if_info *tmp_if, *target_if = NULL;
++	int i;
++
++	for (i=0; i<MAX_IF_NUM; i++) {
++		tmp_if = &apsta_params->if_info[i];
++		if (tmp_if && tmp_if->ifmode == ifmode &&
++				wl_get_isam_status(tmp_if, IF_READY)) {
++			if (wl_ext_get_chan(apsta_params, tmp_if->dev)) {
++				target_if = tmp_if;
++				break;
++			}
++		}
++	}
++
++	return target_if;
++}
++
++static int
++wl_mesh_clear_vndr_ie(struct net_device *dev, uchar *oui)
++{
++	char *vndr_ie_buf = NULL;
++	vndr_ie_setbuf_t *vndr_ie = NULL;
++	ie_getbuf_t vndr_ie_tmp;
++	char *iovar_buf = NULL;
++	int err = -1, i;
++	vndr_ie_buf_t *vndr_ie_dump = NULL;
++	uchar *iebuf;
++	vndr_ie_info_t *ie_info;
++	vndr_ie_t *ie;
++
++	vndr_ie_buf = kzalloc(WLC_IOCTL_SMLEN, GFP_KERNEL);
++	if (!vndr_ie_buf) {
++		AEXT_ERROR(dev->name, "IE memory alloc failed\n");
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	iovar_buf = kzalloc(WLC_IOCTL_MEDLEN, GFP_KERNEL);
++	if (!iovar_buf) {
++		AEXT_ERROR(dev->name, "iovar_buf alloc failed\n");
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	memset(iovar_buf, 0, WLC_IOCTL_MEDLEN);
++	vndr_ie_tmp.pktflag = (uint32) -1;
++	vndr_ie_tmp.id = (uint8) DOT11_MNG_PROPR_ID;
++	err = wl_ext_iovar_getbuf(dev, "vndr_ie", &vndr_ie_tmp, sizeof(vndr_ie_tmp),
++		iovar_buf, WLC_IOCTL_MEDLEN, NULL);
++	if (err)
++		goto exit;
++
++	vndr_ie_dump = (vndr_ie_buf_t *)iovar_buf;
++	if (!vndr_ie_dump->iecount)
++		goto exit;
++
++	iebuf = (uchar *)&vndr_ie_dump->vndr_ie_list[0];
++	for (i=0; i<vndr_ie_dump->iecount; i++) {
++		ie_info = (vndr_ie_info_t *) iebuf;
++		ie = &ie_info->vndr_ie_data;
++		if (memcmp(ie->oui, oui, 3))
++			memset(ie->oui, 0, 3);
++		iebuf += sizeof(uint32) + ie->len + VNDR_IE_HDR_LEN;
++	}
++
++	vndr_ie = (vndr_ie_setbuf_t *) vndr_ie_buf;
++	strncpy(vndr_ie->cmd, "del", VNDR_IE_CMD_LEN - 1);
++	vndr_ie->cmd[VNDR_IE_CMD_LEN - 1] = '\0';
++	memcpy(&vndr_ie->vndr_ie_buffer, vndr_ie_dump, WLC_IOCTL_SMLEN-VNDR_IE_CMD_LEN-1);
++
++	memset(iovar_buf, 0, WLC_IOCTL_MEDLEN);
++	err = wl_ext_iovar_setbuf(dev, "vndr_ie", vndr_ie, WLC_IOCTL_SMLEN, iovar_buf,
++		WLC_IOCTL_MEDLEN, NULL);
++
++exit:
++	if (vndr_ie) {
++		kfree(vndr_ie);
++	}
++	if (iovar_buf) {
++		kfree(iovar_buf);
++	}
++	return err;
++}
++
++static int
++wl_mesh_clear_mesh_info(struct wl_apsta_params *apsta_params,
++	struct wl_if_info *mesh_if, bool scan)
++{
++	struct wl_mesh_params *mesh_info = &apsta_params->mesh_info;
++	uchar mesh_oui[]={0x00, 0x22, 0xf4};
++	int ret;
++
++	AEXT_TRACE(mesh_if->dev->name, "Enter\n");
++
++	ret = wl_mesh_clear_vndr_ie(mesh_if->dev, mesh_oui);
++	memset(mesh_info, 0, sizeof(struct wl_mesh_params));
++	if (scan) {
++		mesh_info->scan_channel = wl_ext_get_chan(apsta_params, mesh_if->dev);
++		wl_mesh_set_timer(mesh_if, 100);
++	}
++
++	return ret;
++}
++
++static int
++wl_mesh_update_vndr_ie(struct wl_apsta_params *apsta_params,
++	struct wl_if_info *mesh_if)
++{
++	struct wl_mesh_params *mesh_info = &apsta_params->mesh_info;
++	char vndr_ie[64];
++	uchar mesh_oui[]={0x00, 0x22, 0xf4};
++	int bytes_written = 0;
++	int ret;
++
++	wl_mesh_clear_vndr_ie(mesh_if->dev, mesh_oui);
++
++	bytes_written += snprintf(vndr_ie+bytes_written, sizeof(vndr_ie),
++		"0x%02x%02x%02x", mesh_oui[0], mesh_oui[1], mesh_oui[2]);
++
++	bytes_written += snprintf(vndr_ie+bytes_written, sizeof(vndr_ie),
++		"%02d%02d%02x%02x%02x%02x%02x%02x", MESH_INFO_MASTER_BSSID, ETHER_ADDR_LEN,
++		((u8 *)(&mesh_info->master_bssid))[0], ((u8 *)(&mesh_info->master_bssid))[1],
++		((u8 *)(&mesh_info->master_bssid))[2], ((u8 *)(&mesh_info->master_bssid))[3],
++		((u8 *)(&mesh_info->master_bssid))[4], ((u8 *)(&mesh_info->master_bssid))[5]);
++
++	bytes_written += snprintf(vndr_ie+bytes_written, sizeof(vndr_ie),
++		"%02x%02x%02x", MESH_INFO_MASTER_CHANNEL, 1, mesh_info->master_channel);
++
++	bytes_written += snprintf(vndr_ie+bytes_written, sizeof(vndr_ie),
++		"%02x%02x%02x", MESH_INFO_HOP_CNT, 1, mesh_info->hop_cnt);
++
++	bytes_written += snprintf(vndr_ie+bytes_written, sizeof(vndr_ie),
++		"%02d%02d%02x%02x%02x%02x%02x%02x", MESH_INFO_PEER_BSSID, ETHER_ADDR_LEN,
++		((u8 *)(&mesh_info->peer_bssid))[0], ((u8 *)(&mesh_info->peer_bssid))[1],
++		((u8 *)(&mesh_info->peer_bssid))[2], ((u8 *)(&mesh_info->peer_bssid))[3],
++		((u8 *)(&mesh_info->peer_bssid))[4], ((u8 *)(&mesh_info->peer_bssid))[5]);
++
++	ret = wl_ext_add_del_ie(mesh_if->dev, VNDR_IE_BEACON_FLAG|VNDR_IE_PRBRSP_FLAG,
++		vndr_ie, "add");
++	if (!ret) {
++		AEXT_INFO(mesh_if->dev->name, "mbssid=%pM, mchannel=%d, hop=%d, pbssid=%pM\n",
++			&mesh_info->master_bssid, mesh_info->master_channel, mesh_info->hop_cnt,
++			&mesh_info->peer_bssid); 
++	}
++
++	return ret;
++}
++
++static bool
++wl_mesh_update_master_info(struct wl_apsta_params *apsta_params,
++	struct wl_if_info *mesh_if)
++{
++	struct wl_mesh_params *mesh_info = &apsta_params->mesh_info;
++	struct wl_if_info *sta_if = NULL;
++	bool updated = FALSE;
++
++	sta_if = wl_ext_if_enabled(apsta_params, ISTA_MODE);
++	if (sta_if) {
++		wldev_ioctl(mesh_if->dev, WLC_GET_BSSID, &mesh_info->master_bssid,
++			ETHER_ADDR_LEN, 0);
++		mesh_info->master_channel = wl_ext_get_chan(apsta_params, mesh_if->dev);
++		mesh_info->hop_cnt = 1;
++		memcpy(&mesh_info->peer_bssid, &mesh_info->master_bssid, ETHER_ADDR_LEN);
++		wl_mesh_update_vndr_ie(apsta_params, mesh_if);
++		updated = TRUE;
++	}
++
++	return updated;
++}
++
++static uint
++wl_mesh_update_mesh_info(struct wl_apsta_params *apsta_params,
++	struct wl_if_info *mesh_if)
++{
++	struct wl_mesh_params *mesh_info = &apsta_params->mesh_info, peer_mesh_info;
++	uint32 count = 0;
++	char *dump_buf = NULL;
++	mesh_peer_info_dump_t *peer_results;
++	mesh_peer_info_ext_t *mpi_ext;
++	struct ether_addr bssid;
++	bool updated = FALSE;
++	uint16 cur_chan;
++
++	dump_buf = kmalloc(WLC_IOCTL_MAXLEN, GFP_KERNEL);
++	if (dump_buf == NULL) {
++		AEXT_ERROR(mesh_if->dev->name, "Failed to allocate buffer of %d bytes\n",
++			WLC_IOCTL_MAXLEN); 
++		return FALSE;
++	}
++	count = wl_mesh_get_peer_results(mesh_if->dev, dump_buf, WLC_IOCTL_MAXLEN);
++	if (count > 0) {
++		memset(&bssid, 0 , ETHER_ADDR_LEN);
++		wldev_ioctl(mesh_if->dev, WLC_GET_BSSID, &bssid, ETHER_ADDR_LEN, 0);
++		peer_results = (mesh_peer_info_dump_t *)dump_buf;
++		mpi_ext = (mesh_peer_info_ext_t *)peer_results->mpi_ext;
++		for (count = 0; count < peer_results->count; count++) {
++			if (mpi_ext->entry_state != MESH_SELF_PEER_ENTRY_STATE_TIMEDOUT &&
++					mpi_ext->peer_info.state == MESH_PEERING_ESTAB) {
++				memset(&peer_mesh_info, 0 , sizeof(struct wl_mesh_params));
++				wl_escan_mesh_info(mesh_if->dev, mesh_if->escan,
++					&mpi_ext->ea, &peer_mesh_info);
++				if ((memcmp(&peer_mesh_info.peer_bssid, &bssid, ETHER_ADDR_LEN)) &&
++						peer_mesh_info.hop_cnt && (mesh_info->hop_cnt == 0 ||
++						peer_mesh_info.hop_cnt <= mesh_info->hop_cnt)) {
++					memcpy(&mesh_info->master_bssid, &peer_mesh_info.master_bssid,
++						ETHER_ADDR_LEN);
++					mesh_info->master_channel = peer_mesh_info.master_channel;
++					mesh_info->hop_cnt = peer_mesh_info.hop_cnt+1;
++					memcpy(&mesh_info->peer_bssid, &mpi_ext->ea, ETHER_ADDR_LEN);
++					mesh_info->channel = peer_mesh_info.channel;
++					updated = TRUE;
++				}
++			}
++			mpi_ext++;
++		}
++		if (updated)
++			wl_mesh_update_vndr_ie(apsta_params, mesh_if);
++	}
++
++	if (!mesh_info->hop_cnt) {
++		wlc_ssid_t cur_ssid;
++		char sec[32];
++		bool sae = FALSE;
++		memset(&peer_mesh_info, 0, sizeof(struct wl_mesh_params));
++		wl_ext_ioctl(mesh_if->dev, WLC_GET_SSID, &cur_ssid, sizeof(cur_ssid), 0);
++		wl_ext_get_sec(mesh_if->dev, mesh_if->ifmode, sec, sizeof(sec));
++		if (strnicmp(sec, "sae/sae", strlen("sae/sae")) == 0)
++			sae = TRUE;
++		cur_chan = wl_ext_get_chan(apsta_params, mesh_if->dev);
++		wl_escan_mesh_peer(mesh_if->dev, mesh_if->escan, &cur_ssid, cur_chan,
++			sae, &peer_mesh_info);
++
++		if (peer_mesh_info.hop_cnt && peer_mesh_info.channel &&
++				(cur_chan != peer_mesh_info.channel)) {
++			WL_MSG(mesh_if->ifname, "moving channel %d -> %d\n",
++				cur_chan, peer_mesh_info.channel);
++			wl_ext_disable_iface(mesh_if->dev, mesh_if->ifname);
++			mesh_if->channel = peer_mesh_info.channel;
++			wl_ext_enable_iface(mesh_if->dev, mesh_if->ifname, 500);
++		}
++	}
++
++	if (dump_buf)
++		kfree(dump_buf);
++	return mesh_info->hop_cnt;
++}
++
++static void
++wl_mesh_event_handler(	struct wl_apsta_params *apsta_params,
++	struct wl_if_info *mesh_if, const wl_event_msg_t *e, void *data)
++{
++	struct wl_mesh_params *mesh_info = &apsta_params->mesh_info;
++	uint32 event_type = ntoh32(e->event_type);
++	uint32 status = ntoh32(e->status);
++	uint32 reason = ntoh32(e->reason);
++	wlc_ssid_t ssid;
++	int ret;
++
++	if (wl_get_isam_status(mesh_if, AP_CREATED) &&
++			((event_type == WLC_E_SET_SSID && status == WLC_E_STATUS_SUCCESS) ||
++			(event_type == WLC_E_LINK && status == WLC_E_STATUS_SUCCESS &&
++			reason == WLC_E_REASON_INITIAL_ASSOC))) {
++		if (!wl_mesh_update_master_info(apsta_params, mesh_if)) {
++			mesh_info->scan_channel = wl_ext_get_chan(apsta_params, mesh_if->dev);
++			wl_mesh_set_timer(mesh_if, WL_MESH_DELAY_SCAN_MS);
++		}
++	}
++	else if ((event_type == WLC_E_LINK && reason == WLC_E_LINK_BSSCFG_DIS) ||
++			(event_type == WLC_E_LINK && status == WLC_E_STATUS_SUCCESS &&
++			reason == WLC_E_REASON_DEAUTH)) {
++		wl_mesh_clear_mesh_info(apsta_params, mesh_if, FALSE);
++	}
++	else if (wl_get_isam_status(mesh_if, AP_CREATED) &&
++			(event_type == WLC_E_ASSOC_IND || event_type == WLC_E_REASSOC_IND) &&
++			reason == DOT11_SC_SUCCESS) {
++		mesh_info->scan_channel = wl_ext_get_chan(apsta_params, mesh_if->dev);
++		wl_mesh_set_timer(mesh_if, 100);
++	}
++	else if (event_type == WLC_E_DISASSOC_IND || event_type == WLC_E_DEAUTH_IND ||
++			(event_type == WLC_E_DEAUTH && reason != DOT11_RC_RESERVED)) {
++		if (!memcmp(&mesh_info->peer_bssid, &e->addr, ETHER_ADDR_LEN))
++			wl_mesh_clear_mesh_info(apsta_params, mesh_if, TRUE);
++	}
++	else if (wl_get_isam_status(mesh_if, AP_CREATED) &&
++			event_type == WLC_E_RESERVED && reason == 0xFFFFFFFF) {
++		if (!wl_mesh_update_master_info(apsta_params, mesh_if)) {
++			wl_ext_ioctl(mesh_if->dev, WLC_GET_SSID, &ssid, sizeof(ssid), 0);
++			ret = wl_escan_set_scan(mesh_if->dev, apsta_params->dhd, &ssid,
++				mesh_info->scan_channel, FALSE);
++			if (ret)
++				wl_mesh_set_timer(mesh_if, WL_MESH_DELAY_SCAN_MS);
++		}
++	}
++	else if (wl_get_isam_status(mesh_if, AP_CREATED) &&
++			((event_type == WLC_E_ESCAN_RESULT && status == WLC_E_STATUS_SUCCESS) ||
++			(event_type == WLC_E_ESCAN_RESULT &&
++			(status == WLC_E_STATUS_ABORT || status == WLC_E_STATUS_NEWSCAN ||
++			status == WLC_E_STATUS_11HQUIET || status == WLC_E_STATUS_CS_ABORT ||
++			status == WLC_E_STATUS_NEWASSOC || status == WLC_E_STATUS_TIMEOUT)))) {
++		if (!wl_mesh_update_master_info(apsta_params, mesh_if)) {
++			if (!wl_mesh_update_mesh_info(apsta_params, mesh_if)) {
++				mesh_info->scan_channel = 0;
++				wl_mesh_set_timer(mesh_if, WL_MESH_DELAY_SCAN_MS);
++			}
++		}
++	}
++}
++
++static void
++wl_mesh_escan_detach(dhd_pub_t *dhd, struct wl_if_info *mesh_if)
++{
++	AEXT_TRACE(mesh_if->dev->name, "Enter\n");
++
++	_del_timer_sync(&mesh_if->delay_scan);
++
++	if (mesh_if->escan) {
++		mesh_if->escan = NULL;
++	}
++}
++
++static int
++wl_mesh_escan_attach(dhd_pub_t *dhd, struct wl_if_info *mesh_if)
++{
++	AEXT_TRACE(mesh_if->dev->name, "Enter\n");
++
++	mesh_if->escan = dhd->escan;
++	init_timer_compat(&mesh_if->delay_scan, wl_mesh_timer, mesh_if);
++
++	return 0;
++}
++#endif /* WL_ESCAN */
++#endif /* WLMESH */
++
++static int
++wl_ext_isam_status(struct net_device *dev, char *command, int total_len)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++	int i;
++	struct wl_if_info *tmp_if;
++	uint16 chan = 0;
++	wlc_ssid_t ssid = { 0, {0} };
++	struct ether_addr bssid;
++	scb_val_t scb_val;
++	char sec[32];
++	u32 chanspec = 0;
++	char *dump_buf = NULL;
++	int dump_len = WLC_IOCTL_MEDLEN;
++	int dump_written = 0;
++
++	if (command || android_msg_level & ANDROID_INFO_LEVEL) {
++		if (command) {
++			dump_buf = command;
++			dump_len = total_len;
++		} else {
++			dump_buf = kmalloc(dump_len, GFP_KERNEL);
++			if (dump_buf == NULL) {
++				AEXT_ERROR(dev->name, "Failed to allocate buffer of %d bytes\n",
++					dump_len); 
++				return -1;
++			}
++		}
++		dump_written += snprintf(dump_buf+dump_written, dump_len,
++			"apstamode=%d", apsta_params->apstamode);
++		for (i=0; i<MAX_IF_NUM; i++) {
++			memset(&ssid, 0, sizeof(ssid));
++			memset(&bssid, 0, sizeof(bssid));
++			memset(&scb_val, 0, sizeof(scb_val));
++			tmp_if = &apsta_params->if_info[i];
++			if (tmp_if->dev) {
++				chan = wl_ext_get_chan(apsta_params, tmp_if->dev);
++				if (chan) {
++					wl_ext_ioctl(tmp_if->dev, WLC_GET_SSID, &ssid, sizeof(ssid), 0);
++					wldev_ioctl(tmp_if->dev, WLC_GET_BSSID, &bssid, sizeof(bssid), 0);
++					wldev_ioctl(tmp_if->dev, WLC_GET_RSSI, &scb_val,
++						sizeof(scb_val_t), 0);
++					chanspec = wl_ext_get_chanspec(apsta_params, tmp_if->dev);
++					wl_ext_get_sec(tmp_if->dev, tmp_if->ifmode, sec, sizeof(sec));
++					dump_written += snprintf(dump_buf+dump_written, dump_len,
++						"\n[dhd-%s-%c]: bssid=%pM, chan=%3d(0x%x %sMHz), "
++						"rssi=%3d, sec=%-15s, SSID=\"%s\"",
++						tmp_if->ifname, tmp_if->prefix, &bssid, chan, chanspec,
++						CHSPEC_IS20(chanspec)?"20":
++						CHSPEC_IS40(chanspec)?"40":
++						CHSPEC_IS80(chanspec)?"80":"160",
++						dtoh32(scb_val.val), sec, ssid.SSID);
++					if (tmp_if->ifmode == IAP_MODE) {
++						dump_written += snprintf(dump_buf+dump_written, dump_len, "\n");
++						dump_written += wl_ext_assoclist(tmp_if->dev, NULL,
++							dump_buf+dump_written, dump_len-dump_written);
++					}
++#ifdef WLMESH
++					else if (tmp_if->ifmode == IMESH_MODE) {
++						dump_written += snprintf(dump_buf+dump_written, dump_len, "\n");
++						dump_written += wl_ext_mesh_peer_status(tmp_if->dev, NULL,
++							dump_buf+dump_written, dump_len-dump_written);
++					}
++#endif /* WLMESH */
++				} else {
++					dump_written += snprintf(dump_buf+dump_written, dump_len,
++						"\n[dhd-%s-%c]:", tmp_if->ifname, tmp_if->prefix);
++				}
++			}
++		}
++		AEXT_INFO(dev->name, "%s\n", dump_buf);
++	}
++
++	if (!command && dump_buf)
++		kfree(dump_buf);
++	return dump_written;
++}
++
++static bool
++wl_ext_master_if(struct wl_if_info *cur_if)
++{
++	if (cur_if->ifmode == IAP_MODE || cur_if->ifmode == IMESH_MODE)
++		return TRUE;
++	else
++		return FALSE;
++}
++
++static int
++wl_ext_if_down(struct wl_apsta_params *apsta_params, struct wl_if_info *cur_if)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	scb_val_t scbval;
++	struct {
++		s32 cfg;
++		s32 val;
++	} bss_setbuf;
++	apstamode_t apstamode = apsta_params->apstamode;
++
++	WL_MSG(cur_if->ifname, "[%c] Turning off...\n", cur_if->prefix);
++
++	if (cur_if->ifmode == ISTA_MODE) {
++		wl_ext_ioctl(cur_if->dev, WLC_DISASSOC, NULL, 0, 1);
++	} else if (cur_if->ifmode == IAP_MODE || cur_if->ifmode == IMESH_MODE) {
++		// deauthenticate all STA first
++		memcpy(scbval.ea.octet, &ether_bcast, ETHER_ADDR_LEN);
++		wl_ext_ioctl(cur_if->dev, WLC_SCB_DEAUTHENTICATE, &scbval.ea, ETHER_ADDR_LEN, 1);
++	}
++
++	if (apstamode == IAPONLY_MODE || apstamode == IMESHONLY_MODE) {
++		wl_ext_ioctl(cur_if->dev, WLC_DOWN, NULL, 0, 1);
++	} else {
++		bss_setbuf.cfg = 0xffffffff;
++		bss_setbuf.val = htod32(0);
++		wl_ext_iovar_setbuf(cur_if->dev, "bss", &bss_setbuf, sizeof(bss_setbuf),
++			iovar_buf, WLC_IOCTL_SMLEN, NULL);
++	}
++	wl_clr_isam_status(cur_if, AP_CREATED);
++
++	return 0;
++}
++
++static int
++wl_ext_if_up(struct wl_apsta_params *apsta_params, struct wl_if_info *cur_if)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	struct {
++		s32 cfg;
++		s32 val;
++	} bss_setbuf;
++	apstamode_t apstamode = apsta_params->apstamode;
++	chanspec_t fw_chspec;
++	u32 timeout;
++	wlc_ssid_t ssid = { 0, {0} };
++	uint16 chan = 0;
++
++	if (cur_if->ifmode != IAP_MODE) {
++		AEXT_ERROR(cur_if->ifname, "Wrong ifmode\n");
++		return 0;
++	}
++
++	if (wl_ext_dfs_chan(cur_if->channel) && !apsta_params->radar) {
++		WL_MSG(cur_if->ifname, "[%c] skip DFS channel %d\n",
++			cur_if->prefix, cur_if->channel);
++		return 0;
++	} else if (!cur_if->channel) {
++		WL_MSG(cur_if->ifname, "[%c] no valid channel\n", cur_if->prefix);
++		return 0;
++	}
++
++	WL_MSG(cur_if->ifname, "[%c] Turning on...\n", cur_if->prefix);
++
++	wl_ext_set_chanspec(cur_if->dev, apsta_params->ioctl_ver, cur_if->channel,
++		&fw_chspec);
++
++	wl_clr_isam_status(cur_if, AP_CREATED);
++	wl_set_isam_status(cur_if, AP_CREATING);
++	if (apstamode == IAPONLY_MODE) {
++		wl_ext_ioctl(cur_if->dev, WLC_UP, NULL, 0, 1);
++	} else {
++		bss_setbuf.cfg = 0xffffffff;	
++		bss_setbuf.val = htod32(1);
++		wl_ext_iovar_setbuf(cur_if->dev, "bss", &bss_setbuf,
++			sizeof(bss_setbuf), iovar_buf, WLC_IOCTL_SMLEN, NULL);
++	}
++
++	timeout = wait_event_interruptible_timeout(apsta_params->netif_change_event,
++		wl_get_isam_status(cur_if, AP_CREATED),
++		msecs_to_jiffies(MAX_AP_LINK_WAIT_TIME));
++	if (timeout <= 0 || !wl_get_isam_status(cur_if, AP_CREATED)) {
++		wl_ext_if_down(apsta_params, cur_if);
++		WL_MSG(cur_if->ifname, "[%c] failed to up with SSID: \"%s\"\n",
++			cur_if->prefix, cur_if->ssid);
++	} else {
++		wl_ext_ioctl(cur_if->dev, WLC_GET_SSID, &ssid, sizeof(ssid), 0);
++		chan = wl_ext_get_chan(apsta_params, cur_if->dev);
++		WL_MSG(cur_if->ifname, "[%c] enabled with SSID: \"%s\" on channel %d\n",
++			cur_if->prefix, ssid.SSID, chan);
++	}
++	wl_clr_isam_status(cur_if, AP_CREATING);
++
++	wl_ext_isam_status(cur_if->dev, NULL, 0);
++
++	return 0;
++}
++
++static int
++wl_ext_disable_iface(struct net_device *dev, char *ifname)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	int i;
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	wlc_ssid_t ssid = { 0, {0} };
++	scb_val_t scbval;
++	struct {
++		s32 cfg;
++		s32 val;
++	} bss_setbuf;
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++	apstamode_t apstamode = apsta_params->apstamode;
++	struct wl_if_info *cur_if = NULL, *tmp_if = NULL;
++
++	for (i=0; i<MAX_IF_NUM; i++) {
++		tmp_if = &apsta_params->if_info[i];
++		if (tmp_if->dev && !strcmp(tmp_if->dev->name, ifname)) {
++			cur_if = tmp_if;
++			break;
++		}
++	}
++	if (!cur_if) {
++		AEXT_ERROR(dev->name, "wrong ifname=%s or dev not ready\n", ifname);
++		return -1;
++	}
++
++	mutex_lock(&apsta_params->usr_sync);
++	WL_MSG(ifname, "[%c] Disabling...\n", cur_if->prefix);
++
++	if (cur_if->ifmode == ISTA_MODE) {
++		wl_ext_ioctl(cur_if->dev, WLC_DISASSOC, NULL, 0, 1);
++	} else if (cur_if->ifmode == IAP_MODE || cur_if->ifmode == IMESH_MODE) {
++		// deauthenticate all STA first
++		memcpy(scbval.ea.octet, &ether_bcast, ETHER_ADDR_LEN);
++		wl_ext_ioctl(cur_if->dev, WLC_SCB_DEAUTHENTICATE, &scbval.ea, ETHER_ADDR_LEN, 1);
++	}
++
++	if (apstamode == IAPONLY_MODE || apstamode == IMESHONLY_MODE) {
++		wl_ext_ioctl(dev, WLC_DOWN, NULL, 0, 1);
++		wl_ext_ioctl(dev, WLC_SET_SSID, &ssid, sizeof(ssid), 1); // reset ssid
++		wl_ext_iovar_setint(dev, "mpc", 1);
++	} else if ((apstamode==ISTAAP_MODE || apstamode==ISTAGO_MODE) &&
++			cur_if->ifmode == IAP_MODE) {
++		bss_setbuf.cfg = 0xffffffff;
++		bss_setbuf.val = htod32(0);
++		wl_ext_iovar_setbuf(cur_if->dev, "bss", &bss_setbuf, sizeof(bss_setbuf),
++			iovar_buf, WLC_IOCTL_SMLEN, NULL);
++		wl_ext_iovar_setint(dev, "mpc", 1);
++#ifdef ARP_OFFLOAD_SUPPORT
++		/* IF SoftAP is disabled, enable arpoe back for STA mode. */
++		dhd_arp_offload_set(dhd, dhd_arp_mode);
++		dhd_arp_offload_enable(dhd, TRUE);
++#endif /* ARP_OFFLOAD_SUPPORT */
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO)
++		if (dhd->conf->disable_proptx!=0) {
++			bool enabled;
++			dhd_wlfc_get_enable(dhd, &enabled);
++			if (enabled) {
++				dhd_wlfc_deinit(dhd);
++			}
++		}
++#endif /* BCMSDIO */
++#endif /* PROP_TXSTATUS_VSDB */
++	}
++	else if (apstamode == IDUALAP_MODE || apstamode == ISTAAPAP_MODE) {
++		bss_setbuf.cfg = 0xffffffff;
++		bss_setbuf.val = htod32(0);
++		wl_ext_iovar_setbuf(cur_if->dev, "bss", &bss_setbuf, sizeof(bss_setbuf),
++			iovar_buf, WLC_IOCTL_SMLEN, NULL);
++#ifdef WLMESH
++	} else if (apstamode == ISTAMESH_MODE || apstamode == IMESHAP_MODE ||
++			apstamode == ISTAAPMESH_MODE || apstamode == IMESHAPAP_MODE) {
++		bss_setbuf.cfg = 0xffffffff;
++		bss_setbuf.val = htod32(0);
++		wl_ext_iovar_setbuf(cur_if->dev, "bss", &bss_setbuf, sizeof(bss_setbuf),
++			iovar_buf, WLC_IOCTL_SMLEN, NULL);
++		if (cur_if->ifmode == IMESH_MODE) {
++			int scan_assoc_time = DHD_SCAN_ASSOC_ACTIVE_TIME;
++			for (i=0; i<MAX_IF_NUM; i++) {
++				tmp_if = &apsta_params->if_info[i];
++				if (tmp_if->dev && tmp_if->ifmode == ISTA_MODE) {
++					wl_ext_ioctl(tmp_if->dev, WLC_SET_SCAN_CHANNEL_TIME,
++						&scan_assoc_time, sizeof(scan_assoc_time), 1);
++				}
++			}
++		}
++#endif /* WLMESH */
++	}
++
++	wl_clr_isam_status(cur_if, AP_CREATED);
++
++	WL_MSG(ifname, "[%c] Exit\n", cur_if->prefix);
++	mutex_unlock(&apsta_params->usr_sync);
++	return 0;
++}
++
++static int
++wl_ext_iapsta_disable(struct net_device *dev, char *command, int total_len)
++{
++	int ret = 0;
++	char *pch, *pick_tmp, *param;
++	char ifname[IFNAMSIZ+1];
++
++	AEXT_TRACE(dev->name, "command=%s, len=%d\n", command, total_len);
++
++	pick_tmp = command;
++	param = bcmstrtok(&pick_tmp, " ", 0); // skip iapsta_disable
++	param = bcmstrtok(&pick_tmp, " ", 0);
++	while (param != NULL) {
++		if (!strcmp(param, "ifname")) {
++			pch = bcmstrtok(&pick_tmp, " ", 0);
++			if (pch) {
++				strcpy(ifname, pch);
++				ret = wl_ext_disable_iface(dev, ifname);
++				if (ret)
++					return ret;
++			}
++			else {
++				AEXT_ERROR(dev->name, "ifname [wlanX]\n");
++				return -1;
++			}
++		}
++		param = bcmstrtok(&pick_tmp, " ", 0);
++	}
++
++	return ret;
++}
++
++static bool
++wl_ext_diff_band(uint16 chan1, uint16 chan2)
++{
++	if ((chan1 <= CH_MAX_2G_CHANNEL && chan2 > CH_MAX_2G_CHANNEL) ||
++		(chan1 > CH_MAX_2G_CHANNEL && chan2 <= CH_MAX_2G_CHANNEL)) {
++		return TRUE;
++	}
++	return FALSE;
++}
++
++static uint16
++wl_ext_same_band(struct wl_apsta_params *apsta_params,
++	struct wl_if_info *cur_if, bool nodfs)
++{
++	struct wl_if_info *tmp_if;
++	uint16 tmp_chan, target_chan = 0;
++	wl_prio_t max_prio;
++	int i;
++
++	// find the max prio
++	max_prio = cur_if->prio;
++	for (i=0; i<MAX_IF_NUM; i++) {
++		tmp_if = &apsta_params->if_info[i];
++		if (cur_if != tmp_if && wl_get_isam_status(tmp_if, IF_READY) &&
++				tmp_if->prio > max_prio) {
++			tmp_chan = wl_ext_get_chan(apsta_params, tmp_if->dev);
++			if (wl_ext_dfs_chan(tmp_chan) && nodfs)
++				continue;
++			if (tmp_chan && !wl_ext_diff_band(cur_if->channel, tmp_chan)) {
++				target_chan = tmp_chan;
++				max_prio = tmp_if->prio;
++			}
++		}
++	}
++
++	return target_chan;
++}
++
++static uint16
++wl_ext_get_vsdb_chan(struct wl_apsta_params *apsta_params,
++	struct wl_if_info *cur_if, struct wl_if_info *target_if)
++{
++	uint16 target_chan = 0, cur_chan = cur_if->channel;
++
++	target_chan = wl_ext_get_chan(apsta_params, target_if->dev);
++	if (target_chan) {
++		AEXT_INFO(cur_if->ifname, "cur_chan=%d, target_chan=%d\n",
++			cur_chan, target_chan);
++		if (wl_ext_diff_band(cur_chan, target_chan)) {
++			if (!apsta_params->rsdb)
++				return target_chan;
++		} else {
++			if (cur_chan != target_chan)
++				return target_chan;
++		}
++	}
++
++	return 0;
++}
++
++static int
++wl_ext_rsdb_core_conflict(struct wl_apsta_params *apsta_params,
++	struct wl_if_info *cur_if)
++{
++	struct wl_if_info *tmp_if;
++	uint16 cur_chan, tmp_chan;
++	int i;
++
++	if (apsta_params->rsdb) {
++		cur_chan = wl_ext_get_chan(apsta_params, cur_if->dev);
++		for (i=0; i<MAX_IF_NUM; i++) {
++			tmp_if = &apsta_params->if_info[i];
++			if (tmp_if != cur_if && wl_get_isam_status(tmp_if, IF_READY) &&
++					tmp_if->prio > cur_if->prio) {
++				tmp_chan = wl_ext_get_chan(apsta_params, tmp_if->dev);
++				if (!tmp_chan)
++					continue;
++				if (wl_ext_diff_band(cur_chan, tmp_chan) &&
++						wl_ext_diff_band(cur_chan, cur_if->channel))
++					return TRUE;
++				else if (!wl_ext_diff_band(cur_chan, tmp_chan) &&
++						wl_ext_diff_band(cur_chan, cur_if->channel))
++					return TRUE;
++			}
++		}
++	}
++	return FALSE;
++}
++
++static int
++wl_ext_trigger_csa(struct wl_apsta_params *apsta_params, struct wl_if_info *cur_if)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	bool core_conflict = FALSE;
++
++	if (wl_ext_master_if(cur_if) && (apsta_params->csa & CSA_DRV_BIT)) {
++		if (!cur_if->channel) {
++			WL_MSG(cur_if->ifname, "[%c] no valid channel\n", cur_if->prefix);
++		} else if (wl_ext_dfs_chan(cur_if->channel) && !apsta_params->radar) {
++			WL_MSG(cur_if->ifname, "[%c] skip DFS channel %d\n",
++				cur_if->prefix, cur_if->channel);
++			wl_ext_if_down(apsta_params, cur_if);
++		} else {
++			wl_chan_switch_t csa_arg;
++			memset(&csa_arg, 0, sizeof(csa_arg));
++			csa_arg.mode = 1;
++			csa_arg.count = 3;
++			csa_arg.chspec = wl_ext_chan_to_chanspec(apsta_params, cur_if->dev,
++				cur_if->channel);
++			core_conflict = wl_ext_rsdb_core_conflict(apsta_params, cur_if);
++			if (core_conflict) {
++				WL_MSG(cur_if->ifname, "[%c] Skip CSA due to rsdb core conflict\n",
++					cur_if->prefix);
++			} else if (csa_arg.chspec) {
++				WL_MSG(cur_if->ifname, "[%c] Trigger CSA to channel %d(0x%x)\n",
++					cur_if->prefix, cur_if->channel, csa_arg.chspec);
++				wl_set_isam_status(cur_if, AP_CREATING);
++				wl_ext_iovar_setbuf(cur_if->dev, "csa", &csa_arg, sizeof(csa_arg),
++					iovar_buf, sizeof(iovar_buf), NULL);
++				OSL_SLEEP(500);
++				wl_clr_isam_status(cur_if, AP_CREATING);
++				wl_ext_isam_status(cur_if->dev, NULL, 0);
++			} else {
++				AEXT_ERROR(cur_if->ifname, "fail to get chanspec\n");
++			}
++		}
++	}
++
++	return 0;
++}
++
++static void
++wl_ext_move_cur_dfs_channel(struct wl_apsta_params *apsta_params,
++	struct wl_if_info *cur_if)
++{
++	uint16 other_chan = 0, cur_chan = cur_if->channel;
++	uint16 chan_2g = 0, chan_5g = 0;
++	uint32 auto_band = WLC_BAND_2G;
++
++	if (wl_ext_master_if(cur_if) && wl_ext_dfs_chan(cur_if->channel) &&
++			!apsta_params->radar) {
++
++		wl_ext_get_default_chan(cur_if->dev, &chan_2g, &chan_5g, TRUE);
++		if (!chan_2g && !chan_5g) {
++			cur_if->channel = 0;
++			WL_MSG(cur_if->ifname, "[%c] no valid channel\n", cur_if->prefix);
++			return;
++		}
++
++		if (apsta_params->vsdb) {
++			if (chan_5g) {
++				cur_if->channel = chan_5g;
++				auto_band = WLC_BAND_5G;
++				other_chan = wl_ext_same_band(apsta_params, cur_if, TRUE);
++			} else {
++				cur_if->channel = chan_2g;
++				auto_band = WLC_BAND_2G;
++				other_chan = wl_ext_same_band(apsta_params, cur_if, TRUE);
++			}
++			if (!other_chan) {
++				other_chan = wl_ext_autochannel(cur_if->dev, ACS_FW_BIT|ACS_DRV_BIT,
++					auto_band);
++			}
++			if (other_chan)
++				cur_if->channel = other_chan;
++		} else if (apsta_params->rsdb) {
++			if (chan_5g) {
++				cur_if->channel = chan_5g;
++				auto_band = WLC_BAND_5G;
++				other_chan = wl_ext_same_band(apsta_params, cur_if, FALSE);
++				if (wl_ext_dfs_chan(other_chan) && chan_2g) {
++					cur_if->channel = chan_2g;
++					auto_band = WLC_BAND_2G;
++					other_chan = wl_ext_same_band(apsta_params, cur_if, TRUE);
++				}
++			} else {
++				cur_if->channel = chan_2g;
++				auto_band = WLC_BAND_2G;
++				other_chan = wl_ext_same_band(apsta_params, cur_if, TRUE);
++			}
++			if (!other_chan) {
++				other_chan = wl_ext_autochannel(cur_if->dev, ACS_FW_BIT|ACS_DRV_BIT,
++					auto_band);
++			}
++			if (other_chan)
++				cur_if->channel = other_chan;
++		} else {
++			cur_if->channel = chan_5g;
++			auto_band = WLC_BAND_5G;
++			other_chan = wl_ext_same_band(apsta_params, cur_if, FALSE);
++			if (wl_ext_dfs_chan(other_chan)) {
++				cur_if->channel = 0;
++			}
++			else if (!other_chan) {
++				other_chan = wl_ext_autochannel(cur_if->dev, ACS_FW_BIT|ACS_DRV_BIT,
++					auto_band);
++			}
++			if (other_chan)
++				cur_if->channel = other_chan;
++		}
++		WL_MSG(cur_if->ifname, "[%c] move channel %d => %d\n",
++			cur_if->prefix, cur_chan, cur_if->channel);
++	}
++}
++
++static void
++wl_ext_move_other_dfs_channel(struct wl_apsta_params *apsta_params,
++	struct wl_if_info *cur_if)
++{
++	uint16 other_chan = 0, cur_chan = cur_if->channel;
++	uint16 chan_2g = 0, chan_5g = 0;
++	uint32 auto_band = WLC_BAND_2G;
++
++	if (wl_ext_master_if(cur_if) && wl_ext_dfs_chan(cur_if->channel) &&
++			!apsta_params->radar) {
++
++		wl_ext_get_default_chan(cur_if->dev, &chan_2g, &chan_5g, TRUE);
++		if (!chan_2g && !chan_5g) {
++			cur_if->channel = 0;
++			WL_MSG(cur_if->ifname, "[%c] no valid channel\n", cur_if->prefix);
++			return;
++		}
++
++		if (apsta_params->vsdb) {
++			if (chan_5g) {
++				cur_if->channel = chan_5g;
++				auto_band = WLC_BAND_5G;
++				other_chan = wl_ext_same_band(apsta_params, cur_if, TRUE);
++			} else {
++				cur_if->channel = chan_2g;
++				auto_band = WLC_BAND_2G;
++				other_chan = wl_ext_same_band(apsta_params, cur_if, TRUE);
++			}
++			if (!other_chan) {
++				other_chan = wl_ext_autochannel(cur_if->dev, ACS_FW_BIT|ACS_DRV_BIT,
++					auto_band);
++			}
++			if (other_chan)
++				cur_if->channel = other_chan;
++		} else if (apsta_params->rsdb) {
++			if (chan_2g) {
++				cur_if->channel = chan_2g;
++				auto_band = WLC_BAND_2G;
++				other_chan = wl_ext_same_band(apsta_params, cur_if, TRUE);
++				if (!other_chan) {
++					other_chan = wl_ext_autochannel(cur_if->dev, ACS_FW_BIT|ACS_DRV_BIT,
++						auto_band);
++				}
++			} else {
++				cur_if->channel = 0;
++			}
++			if (other_chan)
++				cur_if->channel = other_chan;
++		} else {
++			cur_if->channel = 0;
++		}
++		WL_MSG(cur_if->ifname, "[%c] move channel %d => %d\n",
++			cur_if->prefix, cur_chan, cur_if->channel);
++	}
++}
++
++static uint16
++wl_ext_move_cur_channel(struct wl_apsta_params *apsta_params,
++	struct wl_if_info *cur_if)
++{
++	struct wl_if_info *tmp_if, *target_if = NULL;
++	uint16 tmp_chan, target_chan = 0;
++	wl_prio_t max_prio;
++	int i;
++
++	if (apsta_params->vsdb) {
++		target_chan = cur_if->channel;
++		goto exit;
++	}
++
++	// find the max prio
++	max_prio = cur_if->prio;
++	for (i=0; i<MAX_IF_NUM; i++) {
++		tmp_if = &apsta_params->if_info[i];
++		if (cur_if != tmp_if && wl_get_isam_status(tmp_if, IF_READY) &&
++				tmp_if->prio > max_prio) {
++			tmp_chan = wl_ext_get_vsdb_chan(apsta_params, cur_if, tmp_if);
++			if (tmp_chan) {
++				target_if = tmp_if;
++				target_chan = tmp_chan;
++				max_prio = tmp_if->prio;
++			}
++		}
++	}
++
++	if (target_chan) {
++		tmp_chan = wl_ext_get_chan(apsta_params, cur_if->dev);
++		if (apsta_params->rsdb && tmp_chan &&
++				wl_ext_diff_band(tmp_chan, target_chan)) {
++			WL_MSG(cur_if->ifname, "[%c] keep on current channel %d\n",
++				cur_if->prefix, tmp_chan);
++			cur_if->channel = 0;
++		} else {
++			WL_MSG(cur_if->ifname, "[%c] channel=%d => %s[%c] channel=%d\n",
++				cur_if->prefix, cur_if->channel,
++				target_if->ifname, target_if->prefix, target_chan);
++			cur_if->channel = target_chan;
++		}
++	}
++
++exit:
++	wl_ext_move_cur_dfs_channel(apsta_params, cur_if);
++
++	return cur_if->channel;
++}
++
++static void
++wl_ext_move_other_channel(struct wl_apsta_params *apsta_params,
++	struct wl_if_info *cur_if)
++{
++	struct wl_if_info *tmp_if, *target_if=NULL;
++	uint16 tmp_chan, target_chan = 0;
++	wl_prio_t max_prio = 0, cur_prio;
++	int i;
++
++	if (apsta_params->vsdb || !cur_if->channel) {
++		return;
++	}
++
++	// find the max prio, but lower than cur_if
++	cur_prio = cur_if->prio;
++	for (i=0; i<MAX_IF_NUM; i++) {
++		tmp_if = &apsta_params->if_info[i];
++		if (cur_if != tmp_if && wl_get_isam_status(tmp_if, IF_READY) &&
++				tmp_if->prio >= max_prio && tmp_if->prio <= cur_prio) {
++			tmp_chan = wl_ext_get_vsdb_chan(apsta_params, cur_if, tmp_if);
++			if (tmp_chan) {
++				target_if = tmp_if;
++				target_chan = tmp_chan;
++				max_prio = tmp_if->prio;
++			}
++		}
++	}
++
++	if (target_if) {
++		WL_MSG(target_if->ifname, "channel=%d => %s channel=%d\n",
++			target_chan, cur_if->ifname, cur_if->channel);
++		target_if->channel = cur_if->channel;
++		wl_ext_move_other_dfs_channel(apsta_params, target_if);
++		if (apsta_params->csa == 0) {
++			wl_ext_if_down(apsta_params, target_if);
++			wl_ext_move_other_channel(apsta_params, cur_if);
++			if (target_if->ifmode == ISTA_MODE || target_if->ifmode == IMESH_MODE) {
++				wl_ext_enable_iface(target_if->dev, target_if->ifname, 0);
++			} else if (target_if->ifmode == IAP_MODE) {
++				wl_ext_if_up(apsta_params, target_if);
++			}
++		} else {
++			wl_ext_trigger_csa(apsta_params, target_if);
++		}
++	}
++
++}
++
++static bool
++wl_ext_wait_other_enabling(struct wl_apsta_params *apsta_params,
++	struct wl_if_info *cur_if)
++{
++	struct wl_if_info *tmp_if;
++	bool enabling = FALSE;
++	u32 timeout = 1;
++	int i;
++
++	for (i=0; i<MAX_IF_NUM; i++) {
++		tmp_if = &apsta_params->if_info[i];
++		if (tmp_if->dev && tmp_if->dev != cur_if->dev) {
++			if (tmp_if->ifmode == ISTA_MODE)
++				enabling = wl_get_isam_status(tmp_if, STA_CONNECTING);
++			else if (tmp_if->ifmode == IAP_MODE || tmp_if->ifmode == IMESH_MODE)
++				enabling = wl_get_isam_status(tmp_if, AP_CREATING);
++			if (enabling)
++				WL_MSG(cur_if->ifname, "waiting for %s[%c] enabling...\n",
++					tmp_if->ifname, tmp_if->prefix);
++			if (enabling && tmp_if->ifmode == ISTA_MODE) {
++				timeout = wait_event_interruptible_timeout(
++					apsta_params->netif_change_event,
++					!wl_get_isam_status(tmp_if, STA_CONNECTING),
++					msecs_to_jiffies(MAX_STA_LINK_WAIT_TIME));
++			} else if (enabling &&
++					(tmp_if->ifmode == IAP_MODE || tmp_if->ifmode == IMESH_MODE)) {
++				timeout = wait_event_interruptible_timeout(
++					apsta_params->netif_change_event,
++					!wl_get_isam_status(tmp_if, AP_CREATING),
++					msecs_to_jiffies(MAX_STA_LINK_WAIT_TIME));
++			}
++			if (tmp_if->ifmode == ISTA_MODE)
++				enabling = wl_get_isam_status(tmp_if, STA_CONNECTING);
++			else if (tmp_if->ifmode == IAP_MODE || tmp_if->ifmode == IMESH_MODE)
++				enabling = wl_get_isam_status(tmp_if, AP_CREATING);
++			if (timeout <= 0 || enabling) {
++				WL_MSG(cur_if->ifname, "%s[%c] is still enabling...\n",
++					tmp_if->ifname, tmp_if->prefix);
++			}
++		}
++	}
++
++	return enabling;
++}
++
++static int
++wl_ext_enable_iface(struct net_device *dev, char *ifname, int wait_up)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	int i, ret = 0;
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	wlc_ssid_t ssid = { 0, {0} };
++	chanspec_t fw_chspec;
++	struct {
++		s32 cfg;
++		s32 val;
++	} bss_setbuf;
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++	apstamode_t apstamode = apsta_params->apstamode;
++	struct wl_if_info *cur_if = NULL, *tmp_if = NULL;
++	uint16 cur_chan;
++	struct wl_conn_info conn_info;
++	u32 timeout;
++
++	for (i=0; i<MAX_IF_NUM; i++) {
++		tmp_if = &apsta_params->if_info[i];
++		if (tmp_if->dev && !strcmp(tmp_if->dev->name, ifname)) {
++			cur_if = tmp_if;
++			break;
++		}
++	}
++	if (!cur_if) {
++		AEXT_ERROR(dev->name, "wrong ifname=%s or dev not ready\n", ifname);
++		return -1;
++	}
++
++	mutex_lock(&apsta_params->usr_sync);
++
++	if (cur_if->ifmode == ISTA_MODE) {
++		wl_set_isam_status(cur_if, STA_CONNECTING);
++	} else if (cur_if->ifmode == IAP_MODE || cur_if->ifmode == IMESH_MODE) {
++		wl_set_isam_status(cur_if, AP_CREATING);
++	}
++
++	wl_ext_isam_status(cur_if->dev, NULL, 0);
++	WL_MSG(ifname, "[%c] Enabling...\n", cur_if->prefix);
++
++	wl_ext_wait_other_enabling(apsta_params, cur_if);
++
++	if (wl_ext_master_if(cur_if) && apsta_params->acs) {
++		uint16 chan_2g, chan_5g;
++		uint auto_band;
++		auto_band = WL_GET_BAND(cur_if->channel);
++		wl_ext_get_default_chan(cur_if->dev, &chan_2g, &chan_5g, TRUE);
++		if ((chan_2g && auto_band == WLC_BAND_2G) ||
++				(chan_5g && auto_band == WLC_BAND_5G)) {
++			cur_if->channel = wl_ext_autochannel(cur_if->dev, apsta_params->acs,
++				auto_band);
++		} else {
++			AEXT_ERROR(ifname, "invalid channel\n");
++			ret = -1;
++			goto exit;
++		}
++	}
++
++	wl_ext_move_cur_channel(apsta_params, cur_if);
++
++	if (wl_ext_master_if(cur_if) && !cur_if->channel) {
++		AEXT_ERROR(ifname, "skip channel 0\n");
++		ret = -1;
++		goto exit;
++	}
++
++	cur_chan = wl_ext_get_chan(apsta_params, cur_if->dev);
++	if (cur_chan) {
++		AEXT_INFO(cur_if->ifname, "Associated\n");
++		if (cur_chan != cur_if->channel) {
++			wl_ext_trigger_csa(apsta_params, cur_if);
++		}
++		goto exit;
++	}
++	if (cur_if->ifmode == ISTA_MODE) {
++		wl_clr_isam_status(cur_if, STA_CONNECTED);
++	} else if (cur_if->ifmode == IAP_MODE || cur_if->ifmode == IMESH_MODE) {
++		wl_clr_isam_status(cur_if, AP_CREATED);
++	}
++
++	wl_ext_move_other_channel(apsta_params, cur_if);
++
++	if (cur_if->ifidx > 0) {
++		wl_ext_iovar_setbuf(cur_if->dev, "cur_etheraddr", (u8 *)cur_if->dev->dev_addr,
++			ETHER_ADDR_LEN, iovar_buf, WLC_IOCTL_SMLEN, NULL);
++	}
++
++	// set ssid for AP
++	ssid.SSID_len = strlen(cur_if->ssid);
++	memcpy(ssid.SSID, cur_if->ssid, ssid.SSID_len);
++	if (cur_if->ifmode == IAP_MODE || cur_if->ifmode == IMESH_MODE) {
++		wl_ext_iovar_setint(dev, "mpc", 0);
++		if (apstamode == IAPONLY_MODE || apstamode == IMESHONLY_MODE) {
++			wl_ext_ioctl(dev, WLC_UP, NULL, 0, 1);
++		} else if (apstamode==ISTAAP_MODE || apstamode==ISTAGO_MODE) {
++			wl_ext_iovar_setbuf_bsscfg(cur_if->dev, "ssid", &ssid, sizeof(ssid),
++				iovar_buf, WLC_IOCTL_SMLEN, cur_if->bssidx, NULL);
++		}
++	}
++
++	if (wl_ext_master_if(cur_if)) {
++		wl_ext_set_bgnmode(cur_if);
++		if (!cur_if->channel) {
++			cur_if->channel = 1;
++		}
++		ret = wl_ext_set_chanspec(cur_if->dev, apsta_params->ioctl_ver,
++			cur_if->channel, &fw_chspec);
++		if (ret)
++			goto exit;
++	}
++
++	wl_ext_set_amode(cur_if);
++	wl_ext_set_emode(apsta_params, cur_if);
++
++	if (cur_if->ifmode == ISTA_MODE) {
++		conn_info.bssidx = cur_if->bssidx;
++		conn_info.channel = cur_if->channel;
++		memcpy(conn_info.ssid.SSID, cur_if->ssid, strlen(cur_if->ssid));
++		conn_info.ssid.SSID_len = strlen(cur_if->ssid);
++		memcpy(&conn_info.bssid, &cur_if->bssid, ETHER_ADDR_LEN);
++	}
++	if (cur_if->ifmode == IAP_MODE) {
++		if (cur_if->maxassoc >= 0)
++			wl_ext_iovar_setint(dev, "maxassoc", cur_if->maxassoc);
++		// terence: fix me, hidden does not work in dualAP mode
++		if (cur_if->hidden > 0) {
++			wl_ext_ioctl(cur_if->dev, WLC_SET_CLOSED, &cur_if->hidden,
++				sizeof(cur_if->hidden), 1);
++			WL_MSG(ifname, "[%c] Broadcast SSID: %s\n",
++				cur_if->prefix, cur_if->hidden ? "OFF":"ON");
++		}
++	}
++
++	if (apstamode == ISTAONLY_MODE) {
++		wl_ext_connect(cur_if->dev, &conn_info);
++	} else if (apstamode == IAPONLY_MODE) {
++		wl_ext_ioctl(cur_if->dev, WLC_SET_SSID, &ssid, sizeof(ssid), 1);
++		wl_ext_ioctl(dev, WLC_UP, NULL, 0, 1);
++	} else if (apstamode == ISTAAP_MODE || apstamode == ISTAGO_MODE) {
++		if (cur_if->ifmode == ISTA_MODE) {
++			wl_ext_connect(cur_if->dev, &conn_info);
++		} else {
++			if (FW_SUPPORTED(dhd, rsdb)) {
++				wl_ext_ioctl(cur_if->dev, WLC_SET_SSID, &ssid, sizeof(ssid), 1);
++			} else {
++				bss_setbuf.cfg = htod32(cur_if->bssidx);
++				bss_setbuf.val = htod32(1);
++				wl_ext_iovar_setbuf(cur_if->dev, "bss", &bss_setbuf,
++					sizeof(bss_setbuf), iovar_buf, WLC_IOCTL_SMLEN, NULL);
++			}
++#ifdef ARP_OFFLOAD_SUPPORT
++			/* IF SoftAP is enabled, disable arpoe */
++			dhd_arp_offload_set(dhd, 0);
++			dhd_arp_offload_enable(dhd, FALSE);
++#endif /* ARP_OFFLOAD_SUPPORT */
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO)
++			if (!(FW_SUPPORTED(dhd, rsdb)) && !disable_proptx) {
++				bool enabled;
++				dhd_wlfc_get_enable(dhd, &enabled);
++				if (!enabled) {
++					dhd_wlfc_init(dhd);
++					wl_ext_ioctl(dev, WLC_UP, NULL, 0, 1);
++				}
++			}
++#endif /* BCMSDIO */
++#endif /* PROP_TXSTATUS_VSDB */
++		}
++	}
++	else if (apstamode == IDUALAP_MODE) {
++		wl_ext_ioctl(cur_if->dev, WLC_SET_SSID, &ssid, sizeof(ssid), 1);
++	} else if (apstamode == ISTAAPAP_MODE) {
++		if (cur_if->ifmode == ISTA_MODE) {
++			wl_ext_connect(cur_if->dev, &conn_info);
++		} else if (cur_if->ifmode == IAP_MODE) {
++			wl_ext_ioctl(cur_if->dev, WLC_SET_SSID, &ssid, sizeof(ssid), 1);
++		} else {
++			AEXT_ERROR(cur_if->ifname, "wrong ifmode %d\n", cur_if->ifmode);
++		}
++#ifdef WLMESH
++	} else if (apstamode == IMESHONLY_MODE ||
++			apstamode == ISTAMESH_MODE || apstamode == IMESHAP_MODE ||
++			apstamode == ISTAAPMESH_MODE || apstamode == IMESHAPAP_MODE) {
++		if (cur_if->ifmode == ISTA_MODE) {
++			wl_ext_connect(cur_if->dev, &conn_info);
++		} else if (cur_if->ifmode == IAP_MODE) {
++			wl_ext_ioctl(cur_if->dev, WLC_SET_SSID, &ssid, sizeof(ssid), 1);
++		} else if (cur_if->ifmode == IMESH_MODE) {
++			struct wl_join_params join_params;
++			// need to up before setting ssid
++			memset(&join_params, 0, sizeof(join_params));
++			join_params.ssid.SSID_len = strlen(cur_if->ssid);
++			memcpy((void *)join_params.ssid.SSID, cur_if->ssid, strlen(cur_if->ssid));
++			join_params.params.chanspec_list[0] = fw_chspec;
++			join_params.params.chanspec_num = 1;
++			wl_ext_ioctl(cur_if->dev, WLC_SET_SSID, &join_params, sizeof(join_params), 1);
++		} else {
++			AEXT_ERROR(cur_if->ifname, "wrong ifmode %d\n", cur_if->ifmode);
++		}
++#endif /* WLMESH */
++	}
++
++	if (wait_up) {
++		OSL_SLEEP(wait_up);
++	} else if (cur_if->ifmode == IAP_MODE || cur_if->ifmode == IMESH_MODE) {
++		timeout = wait_event_interruptible_timeout(apsta_params->netif_change_event,
++			wl_get_isam_status(cur_if, AP_CREATED),
++			msecs_to_jiffies(MAX_AP_LINK_WAIT_TIME));
++		if (timeout <= 0 || !wl_get_isam_status(cur_if, AP_CREATED)) {
++			mutex_unlock(&apsta_params->usr_sync);
++			wl_ext_disable_iface(dev, cur_if->ifname);
++			WL_MSG(ifname, "[%c] failed to enable with SSID: \"%s\"\n",
++				cur_if->prefix, cur_if->ssid);
++			ret = -1;
++		}
++	}
++
++	if (wl_get_isam_status(cur_if, AP_CREATED) &&
++			(cur_if->ifmode == IMESH_MODE || cur_if->ifmode == IAP_MODE) &&
++			(apstamode == ISTAAP_MODE || apstamode == ISTAAPAP_MODE ||
++			apstamode == ISTAMESH_MODE || apstamode == IMESHAP_MODE ||
++			apstamode == ISTAAPMESH_MODE || apstamode == IMESHAPAP_MODE)) {
++		int scan_assoc_time = 80;
++		for (i=0; i<MAX_IF_NUM; i++) {
++			tmp_if = &apsta_params->if_info[i];
++			if (tmp_if->dev && tmp_if->ifmode == ISTA_MODE) {
++				wl_ext_ioctl(tmp_if->dev, WLC_SET_SCAN_CHANNEL_TIME,
++					&scan_assoc_time, sizeof(scan_assoc_time), 1);
++			}
++		}
++	}
++
++	wl_ext_isam_status(cur_if->dev, NULL, 0);
++
++exit:
++	if (cur_if->ifmode == IAP_MODE || cur_if->ifmode == IMESH_MODE) {
++		wl_clr_isam_status(cur_if, AP_CREATING);
++	}
++	WL_MSG(ifname, "[%c] Exit ret=%d\n", cur_if->prefix, ret);
++	mutex_unlock(&apsta_params->usr_sync);
++	return ret;
++}
++
++static int
++wl_ext_iapsta_enable(struct net_device *dev, char *command, int total_len)
++{
++	int ret = 0;
++	char *pch, *pick_tmp, *param;
++	char ifname[IFNAMSIZ+1];
++
++	AEXT_TRACE(dev->name, "command=%s, len=%d\n", command, total_len);
++
++	pick_tmp = command;
++	param = bcmstrtok(&pick_tmp, " ", 0); // skip iapsta_enable
++	param = bcmstrtok(&pick_tmp, " ", 0);
++	while (param != NULL) {
++		if (!strcmp(param, "ifname")) {
++			pch = bcmstrtok(&pick_tmp, " ", 0);
++			if (pch) {
++				strcpy(ifname, pch);
++				ret = wl_ext_enable_iface(dev, ifname, 0);
++				if (ret)
++					return ret;
++			} else {
++				AEXT_ERROR(dev->name, "ifname [wlanX]\n");
++				return -1;
++			}
++		}
++		param = bcmstrtok(&pick_tmp, " ", 0);
++	}
++
++	return ret;
++}
++
++static int
++wl_ext_iapsta_event(struct net_device *dev,
++	struct wl_apsta_params *apsta_params, wl_event_msg_t *e, void* data)
++{
++	struct wl_if_info *cur_if = NULL, *tmp_if = NULL;
++#if defined(WLMESH) && defined(WL_ESCAN)
++	struct wl_if_info *mesh_if = NULL;
++#endif /* WLMESH && WL_ESCAN */
++	int i;
++	uint32 event_type = ntoh32(e->event_type);
++	uint32 status =  ntoh32(e->status);
++	uint32 reason =  ntoh32(e->reason);
++	uint16 flags =  ntoh16(e->flags);
++
++	for (i=0; i<MAX_IF_NUM; i++) {
++		tmp_if = &apsta_params->if_info[i];
++		if (tmp_if->dev == dev) {
++			cur_if = tmp_if;
++			break;
++		}
++	}
++#if defined(WLMESH) && defined(WL_ESCAN)
++	for (i=0; i<MAX_IF_NUM; i++) {
++		tmp_if = &apsta_params->if_info[i];
++		if (tmp_if->dev && tmp_if->ifmode == IMESH_MODE) {
++			mesh_if = tmp_if;
++			break;
++		}
++	}
++#endif /* WLMESH && WL_ESCAN */
++	if (!cur_if || !cur_if->dev) {
++		AEXT_DBG(dev->name, "ifidx %d is not ready\n", e->ifidx);
++		return -1;
++	}
++
++	if (cur_if->ifmode == ISTA_MODE) {
++		if (event_type == WLC_E_LINK) {
++			if (!(flags & WLC_EVENT_MSG_LINK)) {
++				WL_MSG(cur_if->ifname,
++					"[%c] Link down with %pM, %s(%d), reason %d\n",
++					cur_if->prefix, &e->addr, bcmevent_get_name(event_type),
++					event_type, reason);
++				wl_clr_isam_status(cur_if, STA_CONNECTED);
++#if defined(WLMESH) && defined(WL_ESCAN)
++				if (mesh_if && apsta_params->macs)
++					wl_mesh_clear_mesh_info(apsta_params, mesh_if, TRUE);
++#endif /* WLMESH && WL_ESCAN */
++			} else {
++				WL_MSG(cur_if->ifname, "[%c] Link UP with %pM\n",
++					cur_if->prefix, &e->addr);
++				wl_set_isam_status(cur_if, STA_CONNECTED);
++#if defined(WLMESH) && defined(WL_ESCAN)
++				if (mesh_if && apsta_params->macs)
++					wl_mesh_update_master_info(apsta_params, mesh_if);
++#endif /* WLMESH && WL_ESCAN */
++			}
++			wl_clr_isam_status(cur_if, STA_CONNECTING);
++			wake_up_interruptible(&apsta_params->netif_change_event);
++		}
++		else if (event_type == WLC_E_SET_SSID && status != WLC_E_STATUS_SUCCESS) {
++			WL_MSG(cur_if->ifname,
++				"connect failed event=%d, reason=%d, status=%d\n",
++				event_type, reason, status);
++			wl_clr_isam_status(cur_if, STA_CONNECTING);
++			wake_up_interruptible(&apsta_params->netif_change_event);
++#if defined(WLMESH) && defined(WL_ESCAN)
++			if (mesh_if && apsta_params->macs)
++				wl_mesh_clear_mesh_info(apsta_params, mesh_if, TRUE);
++#endif /* WLMESH && WL_ESCAN */
++		}
++		else if (event_type == WLC_E_DEAUTH || event_type == WLC_E_DEAUTH_IND ||
++				event_type == WLC_E_DISASSOC || event_type == WLC_E_DISASSOC_IND) {
++			WL_MSG(cur_if->ifname, "[%c] Link down with %pM, %s(%d), reason %d\n",
++				cur_if->prefix, &e->addr, bcmevent_get_name(event_type),
++				event_type, reason);
++#if defined(WLMESH) && defined(WL_ESCAN)
++			if (mesh_if && apsta_params->macs)
++				wl_mesh_clear_mesh_info(apsta_params, mesh_if, TRUE);
++#endif /* WLMESH && WL_ESCAN */
++		}
++	}
++	else if (cur_if->ifmode == IAP_MODE || cur_if->ifmode == IMESH_MODE) {
++		if ((event_type == WLC_E_SET_SSID && status == WLC_E_STATUS_SUCCESS) ||
++				(event_type == WLC_E_LINK && status == WLC_E_STATUS_SUCCESS &&
++				reason == WLC_E_REASON_INITIAL_ASSOC)) {
++			if (wl_get_isam_status(cur_if, AP_CREATING)) {
++				WL_MSG(cur_if->ifname, "[%c] Link up (etype=%d)\n",
++					cur_if->prefix, event_type);
++				wl_set_isam_status(cur_if, AP_CREATED);
++				wake_up_interruptible(&apsta_params->netif_change_event);
++			} else {
++				wl_set_isam_status(cur_if, AP_CREATED);
++				WL_MSG(cur_if->ifname, "[%c] Link up w/o creating? (etype=%d)\n",
++					cur_if->prefix, event_type);
++			}
++		}
++		else if ((event_type == WLC_E_LINK && reason == WLC_E_LINK_BSSCFG_DIS) ||
++				(event_type == WLC_E_LINK && status == WLC_E_STATUS_SUCCESS &&
++				reason == WLC_E_REASON_DEAUTH)) {
++			wl_clr_isam_status(cur_if, AP_CREATED);
++			WL_MSG(cur_if->ifname, "[%c] Link down, reason=%d\n",
++				cur_if->prefix, reason);
++		}
++		else if ((event_type == WLC_E_ASSOC_IND || event_type == WLC_E_REASSOC_IND) &&
++				reason == DOT11_SC_SUCCESS) {
++			WL_MSG(cur_if->ifname, "[%c] connected device %pM\n",
++				cur_if->prefix, &e->addr);
++			wl_ext_isam_status(cur_if->dev, NULL, 0);
++		}
++		else if (event_type == WLC_E_DISASSOC_IND ||
++				event_type == WLC_E_DEAUTH_IND ||
++				(event_type == WLC_E_DEAUTH && reason != DOT11_RC_RESERVED)) {
++			WL_MSG_RLMT(cur_if->ifname, &e->addr, ETHER_ADDR_LEN,
++				"[%c] disconnected device %pM, %s(%d), reason=%d\n",
++				cur_if->prefix, &e->addr, bcmevent_get_name(event_type),
++				event_type, reason);
++			wl_ext_isam_status(cur_if->dev, NULL, 0);
++		}
++#if defined(WLMESH) && defined(WL_ESCAN)
++		if (cur_if->ifmode == IMESH_MODE && apsta_params->macs)
++			wl_mesh_event_handler(apsta_params, cur_if, e, data);
++#endif /* WLMESH && WL_ESCAN */
++	}
++
++	return 0;
++}
++
++#ifdef WL_CFG80211
++u32
++wl_ext_iapsta_update_channel(dhd_pub_t *dhd, struct net_device *dev,
++	u32 channel)
++{
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++	struct wl_if_info *cur_if = NULL, *tmp_if = NULL;
++	int i;
++
++	for (i=0; i<MAX_IF_NUM; i++) {
++		tmp_if = &apsta_params->if_info[i];
++		if (tmp_if->dev && tmp_if->dev == dev) {
++			cur_if = tmp_if;
++			break;
++		}
++	}
++
++	if (cur_if) {
++		wl_ext_isam_status(cur_if->dev, NULL, 0);
++		cur_if->channel = channel;
++		if (wl_ext_master_if(cur_if) && apsta_params->acs) {
++			uint auto_band = WL_GET_BAND(channel);
++			cur_if->channel = wl_ext_autochannel(cur_if->dev, apsta_params->acs,
++				auto_band);
++		}
++		channel = wl_ext_move_cur_channel(apsta_params, cur_if);
++		if (channel)
++			wl_ext_move_other_channel(apsta_params, cur_if);
++		if (cur_if->ifmode == ISTA_MODE)
++			wl_set_isam_status(cur_if, STA_CONNECTING);
++	}
++
++	return channel;
++}
++
++void
++wl_ext_iapsta_update_iftype(struct net_device *net, int ifidx, int wl_iftype)
++{
++	struct dhd_pub *dhd = dhd_get_pub(net);
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++	struct wl_if_info *cur_if = NULL;
++
++	AEXT_TRACE(net->name, "ifidx=%d, wl_iftype=%d\n", ifidx, wl_iftype);
++
++	if (ifidx < MAX_IF_NUM) {
++		cur_if = &apsta_params->if_info[ifidx];
++	}
++
++	if (cur_if) {
++		if (wl_iftype == WLC_E_IF_ROLE_STA) {
++			cur_if->ifmode = ISTA_MODE;
++			cur_if->prio = PRIO_STA;
++			cur_if->prefix = 'S';
++		} else if (wl_iftype == WLC_E_IF_ROLE_AP && cur_if->ifmode != IMESH_MODE) {
++			cur_if->ifmode = IAP_MODE;
++			cur_if->prio = PRIO_AP;
++			cur_if->prefix = 'A';
++		} else if (wl_iftype == WLC_E_IF_ROLE_P2P_GO) {
++			cur_if->ifmode = IGO_MODE;
++			cur_if->prio = PRIO_AP;
++			cur_if->prefix = 'P';
++			apsta_params->vsdb = TRUE;
++		} else if (wl_iftype == WLC_E_IF_ROLE_P2P_CLIENT) {
++			cur_if->ifmode = IGC_MODE;
++			cur_if->prio = PRIO_STA;
++			cur_if->prefix = 'P';
++			apsta_params->vsdb = TRUE;
++			wl_ext_iovar_setint(cur_if->dev, "assoc_retry_max", 3);
++		}
++	}
++}
++
++void
++wl_ext_iapsta_ifadding(struct net_device *net, int ifidx)
++{
++	struct dhd_pub *dhd = dhd_get_pub(net);
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++	struct wl_if_info *cur_if = NULL;
++
++	AEXT_TRACE(net->name, "ifidx=%d\n", ifidx);
++	if (ifidx < MAX_IF_NUM) {
++		cur_if = &apsta_params->if_info[ifidx];
++		wl_set_isam_status(cur_if, IF_ADDING);
++	}
++}
++
++bool
++wl_ext_iapsta_mesh_creating(struct net_device *net)
++{
++	struct dhd_pub *dhd = dhd_get_pub(net);
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++	struct wl_if_info *cur_if;
++	int i;
++
++	if (apsta_params) {
++		for (i=0; i<MAX_IF_NUM; i++) {
++			cur_if = &apsta_params->if_info[i];
++			if (cur_if->ifmode==IMESH_MODE && wl_get_isam_status(cur_if, IF_ADDING))
++				return TRUE;
++		}
++	}
++	return FALSE;
++}
++#endif /* WL_CFG80211 */
++
++int
++wl_ext_iapsta_alive_preinit(struct net_device *dev)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++
++	if (apsta_params->init == TRUE) {
++		AEXT_ERROR(dev->name, "don't init twice\n");
++		return -1;
++	}
++
++	AEXT_TRACE(dev->name, "Enter\n");
++
++	apsta_params->init = TRUE;
++
++	return 0;
++}
++
++int
++wl_ext_iapsta_alive_postinit(struct net_device *dev)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++	s32 apsta = 0, ap = 0;
++	struct wl_if_info *cur_if;
++	int i;
++
++	wl_ext_iovar_getint(dev, "apsta", &apsta);
++	wl_ext_ioctl(dev, WLC_GET_AP, &ap, sizeof(ap), 0);
++	if (apsta == 1 || ap == 0) {
++		apsta_params->apstamode = ISTAONLY_MODE;
++		apsta_params->if_info[IF_PIF].ifmode = ISTA_MODE;
++		op_mode = DHD_FLAG_STA_MODE;
++	} else {
++		apsta_params->apstamode = IAPONLY_MODE;
++		apsta_params->if_info[IF_PIF].ifmode = IAP_MODE;
++		op_mode = DHD_FLAG_HOSTAP_MODE;
++	}
++	// fix me: how to check it's ISTAAP_MODE or IDUALAP_MODE?
++
++	wl_ext_get_ioctl_ver(dev, &apsta_params->ioctl_ver);
++	WL_MSG(dev->name, "apstamode=%d\n", apsta_params->apstamode);
++
++	for (i=0; i<MAX_IF_NUM; i++) {
++		cur_if = &apsta_params->if_info[i];
++		if (i == 1 && !strlen(cur_if->ifname))
++			strcpy(cur_if->ifname, "wlan1");
++		if (i == 2 && !strlen(cur_if->ifname))
++			strcpy(cur_if->ifname, "wlan2");
++		if (cur_if->ifmode == ISTA_MODE) {
++			cur_if->channel = 0;
++			cur_if->maxassoc = -1;
++			wl_set_isam_status(cur_if, IF_READY);
++			cur_if->prio = PRIO_STA;
++			cur_if->prefix = 'S';
++			snprintf(cur_if->ssid, DOT11_MAX_SSID_LEN, "ttt_sta");
++		} else if (cur_if->ifmode == IAP_MODE) {
++			cur_if->channel = 1;
++			cur_if->maxassoc = -1;
++			wl_set_isam_status(cur_if, IF_READY);
++			cur_if->prio = PRIO_AP;
++			cur_if->prefix = 'A';
++			snprintf(cur_if->ssid, DOT11_MAX_SSID_LEN, "ttt_ap");
++#ifdef WLMESH
++		} else if (cur_if->ifmode == IMESH_MODE) {
++			cur_if->channel = 1;
++			cur_if->maxassoc = -1;
++			wl_set_isam_status(cur_if, IF_READY);
++			cur_if->prio = PRIO_MESH;
++			cur_if->prefix = 'M';
++			snprintf(cur_if->ssid, DOT11_MAX_SSID_LEN, "ttt_mesh");
++#endif /* WLMESH */
++		}
++	}
++
++	return op_mode;
++}
++
++static int
++wl_ext_iapsta_get_rsdb(struct net_device *net, struct dhd_pub *dhd)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	wl_config_t *rsdb_p;
++	int ret = 0, rsdb = 0;
++
++	if (dhd->conf->chip == BCM4359_CHIP_ID) {
++		ret = wldev_iovar_getbuf(net, "rsdb_mode", NULL, 0,
++			iovar_buf, WLC_IOCTL_SMLEN, NULL);
++		if (!ret) {
++			if (dhd->conf->fw_type == FW_TYPE_MESH) {
++				rsdb = 1;
++			} else {
++				rsdb_p = (wl_config_t *) iovar_buf;
++				rsdb = rsdb_p->config;
++			}
++		}
++	}
++
++	AEXT_INFO(net->name, "rsdb_mode=%d\n", rsdb);
++
++	return rsdb;
++}
++
++static void
++wl_ext_iapsta_postinit(struct net_device *net, struct wl_if_info *cur_if)
++{
++	struct dhd_pub *dhd = dhd_get_pub(net);
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++	int pm;
++
++	AEXT_TRACE(cur_if->ifname, "ifidx=%d\n", cur_if->ifidx);
++	if (cur_if->ifidx == 0) {
++		apsta_params->rsdb = wl_ext_iapsta_get_rsdb(net, dhd);
++		apsta_params->vsdb = FALSE;
++		apsta_params->csa = 0;
++		apsta_params->acs = 0;
++		apsta_params->radar = wl_ext_radar_detect(net);
++		if (dhd->conf->fw_type == FW_TYPE_MESH) {
++			apsta_params->csa |= (CSA_FW_BIT | CSA_DRV_BIT);
++		}
++	} else {
++		if (cur_if->ifmode == ISTA_MODE) {
++			wl_ext_iovar_setint(cur_if->dev, "roam_off", dhd->conf->roam_off);
++			wl_ext_iovar_setint(cur_if->dev, "bcn_timeout", dhd->conf->bcn_timeout);
++			if (dhd->conf->pm >= 0)
++				pm = dhd->conf->pm;
++			else
++				pm = PM_FAST;
++			wl_ext_ioctl(cur_if->dev, WLC_SET_PM, &pm, sizeof(pm), 1);
++			wl_ext_iovar_setint(cur_if->dev, "assoc_retry_max", 20);
++		}
++#ifdef WLMESH
++		else if (cur_if->ifmode == IMESH_MODE) {
++			pm = 0;
++			wl_ext_ioctl(cur_if->dev, WLC_SET_PM, &pm, sizeof(pm), 1);
++		}
++#endif /* WLMESH */
++	}
++
++}
++
++int
++wl_ext_iapsta_attach_name(struct net_device *net, int ifidx)
++{
++	struct dhd_pub *dhd = dhd_get_pub(net);
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++	struct wl_if_info *cur_if = NULL;
++
++	AEXT_TRACE(net->name, "ifidx=%d\n", ifidx);
++	if (ifidx < MAX_IF_NUM) {
++		cur_if = &apsta_params->if_info[ifidx];
++	}
++	if (ifidx == 0) {
++		strcpy(cur_if->ifname, net->name);
++		wl_ext_iapsta_postinit(net, cur_if);
++		wl_set_isam_status(cur_if, IF_READY);
++	} else if (cur_if && wl_get_isam_status(cur_if, IF_ADDING)) {
++		strcpy(cur_if->ifname, net->name);
++		wl_ext_iapsta_postinit(net, cur_if);
++		wl_clr_isam_status(cur_if, IF_ADDING);
++		wl_set_isam_status(cur_if, IF_READY);
++		wake_up_interruptible(&apsta_params->netif_change_event);
++	}
++
++	return 0;
++}
++
++int
++wl_ext_iapsta_update_net_device(struct net_device *net, int ifidx)
++{
++	struct dhd_pub *dhd = dhd_get_pub(net);
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++	struct wl_if_info *cur_if = NULL, *primary_if;
++
++	AEXT_TRACE(net->name, "ifidx=%d\n", ifidx);
++	if (ifidx < MAX_IF_NUM) {
++		cur_if = &apsta_params->if_info[ifidx];
++	}
++	if (cur_if && wl_get_isam_status(cur_if, IF_ADDING)) {
++		primary_if = &apsta_params->if_info[IF_PIF];
++		if (strlen(cur_if->ifname)) {
++			memset(net->name, 0, sizeof(IFNAMSIZ));
++			strcpy(net->name, cur_if->ifname);
++			net->name[IFNAMSIZ-1] = '\0';
++		}
++		if (apsta_params->apstamode != IUNKNOWN_MODE &&
++				apsta_params->apstamode != ISTAAPAP_MODE &&
++				apsta_params->apstamode != ISTASTA_MODE) {
++			memcpy(net->dev_addr, primary_if->dev->dev_addr, ETHER_ADDR_LEN);
++			net->dev_addr[0] |= 0x02;
++			if (ifidx >= 2) {
++				net->dev_addr[4] ^= 0x80;
++				net->dev_addr[4] += ifidx;
++				net->dev_addr[5] += (ifidx-1);
++			}
++		}
++	}
++
++	return 0;
++}
++
++int
++wl_ext_iapsta_attach_netdev(struct net_device *net, int ifidx, uint8 bssidx)
++{
++	struct dhd_pub *dhd = dhd_get_pub(net);
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++	struct wl_if_info *cur_if = NULL, *primary_if;
++
++	AEXT_TRACE(net->name, "ifidx=%d, bssidx=%d\n", ifidx, bssidx);
++	if (ifidx < MAX_IF_NUM) {
++		cur_if = &apsta_params->if_info[ifidx];
++	}
++	if (ifidx == 0) {
++		memset(apsta_params, 0, sizeof(struct wl_apsta_params));
++		apsta_params->dhd = dhd;
++		cur_if->dev = net;
++		cur_if->ifidx = ifidx;
++		cur_if->bssidx = bssidx;
++		cur_if->ifmode = ISTA_MODE;
++		cur_if->prio = PRIO_STA;
++		cur_if->prefix = 'S';
++		wl_ext_event_register(net, dhd, WLC_E_LAST, wl_ext_iapsta_event,
++			apsta_params, PRIO_EVENT_IAPSTA);
++		strcpy(cur_if->ifname, net->name);
++		init_waitqueue_head(&apsta_params->netif_change_event);
++		mutex_init(&apsta_params->usr_sync);
++	} else if (cur_if && wl_get_isam_status(cur_if, IF_ADDING)) {
++		primary_if = &apsta_params->if_info[IF_PIF];
++		cur_if->dev = net;
++		cur_if->ifidx = ifidx;
++		cur_if->bssidx = bssidx;
++		wl_ext_event_register(net, dhd, WLC_E_LAST, wl_ext_iapsta_event,
++			apsta_params, PRIO_EVENT_IAPSTA);
++#if defined(WLMESH) && defined(WL_ESCAN)
++		if (cur_if->ifmode == IMESH_MODE && apsta_params->macs) {
++			wl_mesh_escan_attach(dhd, cur_if);
++		}
++#endif /* WLMESH && WL_ESCAN */
++	}
++
++	return 0;
++}
++
++int
++wl_ext_iapsta_dettach_netdev(struct net_device *net, int ifidx)
++{
++	struct dhd_pub *dhd = dhd_get_pub(net);
++	struct wl_apsta_params *apsta_params = dhd->iapsta_params;
++	struct wl_if_info *cur_if = NULL;
++
++	if (!apsta_params)
++		return 0;
++
++	AEXT_TRACE(net->name, "ifidx=%d\n", ifidx);
++	if (ifidx < MAX_IF_NUM) {
++		cur_if = &apsta_params->if_info[ifidx];
++	}
++
++	if (ifidx == 0) {
++		wl_ext_event_deregister(net, dhd, WLC_E_LAST, wl_ext_iapsta_event);
++#if defined(WLMESH) && defined(WL_ESCAN)
++		if (cur_if->ifmode == IMESH_MODE && apsta_params->macs) {
++			wl_mesh_escan_detach(dhd, cur_if);
++		}
++#endif /* WLMESH && WL_ESCAN */
++		memset(apsta_params, 0, sizeof(struct wl_apsta_params));
++	} else if (cur_if && (wl_get_isam_status(cur_if, IF_READY) ||
++			wl_get_isam_status(cur_if, IF_ADDING))) {
++		wl_ext_event_deregister(net, dhd, WLC_E_LAST, wl_ext_iapsta_event);
++#if defined(WLMESH) && defined(WL_ESCAN)
++		if (cur_if->ifmode == IMESH_MODE && apsta_params->macs) {
++			wl_mesh_escan_detach(dhd, cur_if);
++		}
++#endif /* WLMESH && WL_ESCAN */
++		memset(cur_if, 0, sizeof(struct wl_if_info));
++	}
++
++	return 0;
++}
++
++int
++wl_ext_iapsta_attach(dhd_pub_t *pub)
++{
++	struct wl_apsta_params *iapsta_params;
++
++	iapsta_params = kzalloc(sizeof(struct wl_apsta_params), GFP_KERNEL);
++	if (unlikely(!iapsta_params)) {
++		AEXT_ERROR("wlan", "Could not allocate apsta_params\n");
++		return -ENOMEM;
++	}
++	pub->iapsta_params = (void *)iapsta_params;
++
++	return 0;
++}
++
++void
++wl_ext_iapsta_dettach(dhd_pub_t *pub)
++{
++	if (pub->iapsta_params) {
++		kfree(pub->iapsta_params);
++		pub->iapsta_params = NULL;
++	}
++}
++#endif /* WL_EXT_IAPSTA */
++
++#ifdef IDHCP
++/*
++terence 20190409:
++dhd_priv wl dhcpc_dump
++dhd_priv wl dhcpc_param <client ip> <server ip> <lease time>
++*/
++static int
++wl_ext_dhcpc_dump(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	int ret = 0;
++	int bytes_written = 0;
++	uint32 ip_addr;
++	char buf[20]="";
++
++	if (!data) {
++		ret = wl_ext_iovar_getint(dev, "dhcpc_ip_addr", &ip_addr);
++		if (!ret) {
++			bcm_ip_ntoa((struct ipv4_addr *)&ip_addr, buf);
++			bytes_written += snprintf(command+bytes_written, total_len,
++				"ipaddr %s ", buf);
++		}
++
++		ret = wl_ext_iovar_getint(dev, "dhcpc_ip_mask", &ip_addr);
++		if (!ret) {
++			bcm_ip_ntoa((struct ipv4_addr *)&ip_addr, buf);
++			bytes_written += snprintf(command+bytes_written, total_len,
++				"mask %s ", buf);
++		}
++
++		ret = wl_ext_iovar_getint(dev, "dhcpc_ip_gateway", &ip_addr);
++		if (!ret) {
++			bcm_ip_ntoa((struct ipv4_addr *)&ip_addr, buf);
++			bytes_written += snprintf(command+bytes_written, total_len,
++				"gw %s ", buf);
++		}
++
++		ret = wl_ext_iovar_getint(dev, "dhcpc_ip_dnsserv", &ip_addr);
++		if (!ret) {
++			bcm_ip_ntoa((struct ipv4_addr *)&ip_addr, buf);
++			bytes_written += snprintf(command+bytes_written, total_len,
++				"dnsserv %s ", buf);
++		}
++
++		if (!bytes_written)
++			bytes_written = -1;
++
++		AEXT_TRACE(dev->name, "command result is %s\n", command);
++	}
++
++	return bytes_written;
++}
++
++int
++wl_ext_dhcpc_param(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	int ret = -1, bytes_written = 0;
++	char ip_addr_str[20]="", ip_serv_str[20]="";
++	struct dhcpc_parameter dhcpc_param;
++	uint32 ip_addr, ip_serv, lease_time;
++	char iovar_buf[WLC_IOCTL_SMLEN]="\0";
++
++	if (data) {
++		AEXT_TRACE(dev->name, "cmd %s", command);
++		sscanf(data, "%s %s %d", ip_addr_str, ip_serv_str, &lease_time);
++		AEXT_TRACE(dev->name, "ip_addr = %s, ip_serv = %s, lease_time = %d",
++			ip_addr_str, ip_serv_str, lease_time);
++
++		memset(&dhcpc_param, 0, sizeof(struct dhcpc_parameter));
++		if (!bcm_atoipv4(ip_addr_str, (struct ipv4_addr *)&ip_addr)) {
++			AEXT_ERROR(dev->name, "wrong ip_addr_str %s\n", ip_addr_str);
++			ret = -1;
++			goto exit;
++		}
++		dhcpc_param.ip_addr = ip_addr;
++
++		if (!bcm_atoipv4(ip_addr_str, (struct ipv4_addr *)&ip_serv)) {
++			AEXT_ERROR(dev->name, "wrong ip_addr_str %s\n", ip_addr_str);
++			ret = -1;
++			goto exit;
++		}
++		dhcpc_param.ip_serv = ip_serv;
++		dhcpc_param.lease_time = lease_time;
++		ret = wl_ext_iovar_setbuf(dev, "dhcpc_param", &dhcpc_param,
++			sizeof(struct dhcpc_parameter), iovar_buf, sizeof(iovar_buf), NULL);
++	} else {
++		ret = wl_ext_iovar_getbuf(dev, "dhcpc_param", &dhcpc_param,
++			sizeof(struct dhcpc_parameter), iovar_buf, WLC_IOCTL_SMLEN, NULL);
++		if (!ret) {
++			bcm_ip_ntoa((struct ipv4_addr *)&dhcpc_param.ip_addr, ip_addr_str);
++			bytes_written += snprintf(command + bytes_written, total_len,
++				"ip_addr %s\n", ip_addr_str);
++			bcm_ip_ntoa((struct ipv4_addr *)&dhcpc_param.ip_serv, ip_serv_str);
++			bytes_written += snprintf(command + bytes_written, total_len,
++				"ip_serv %s\n", ip_serv_str);
++			bytes_written += snprintf(command + bytes_written, total_len,
++				"lease_time %d\n", dhcpc_param.lease_time);
++			AEXT_TRACE(dev->name, "command result is %s\n", command);
++			ret = bytes_written;
++		}
++	}
++
++	exit:
++		return ret;
++}
++#endif /* IDHCP */
++
++int
++wl_ext_mkeep_alive(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	wl_mkeep_alive_pkt_t *mkeep_alive_pktp;
++	int ret = -1, i, ifidx, id, period=-1;
++	char *packet = NULL, *buf = NULL;
++	int bytes_written = 0;
++
++	if (data) {
++		buf = kmalloc(total_len, GFP_KERNEL);
++		if (buf == NULL) {
++			AEXT_ERROR(dev->name, "Failed to allocate buffer of %d bytes\n", WLC_IOCTL_SMLEN);
++			goto exit;
++		}
++		packet = kmalloc(WLC_IOCTL_SMLEN, GFP_KERNEL);
++		if (packet == NULL) {
++			AEXT_ERROR(dev->name, "Failed to allocate buffer of %d bytes\n", WLC_IOCTL_SMLEN);
++			goto exit;
++		}
++		AEXT_TRACE(dev->name, "cmd %s", command);
++		sscanf(data, "%d %d %s", &id, &period, packet);
++		AEXT_TRACE(dev->name, "id=%d, period=%d, packet=%s", id, period, packet);
++		if (period >= 0) {
++			ifidx = dhd_net2idx(dhd->info, dev);
++			ret = dhd_conf_mkeep_alive(dhd, ifidx, id, period, packet, FALSE);
++		} else {
++			if (id < 0)
++				id = 0;
++			ret = wl_ext_iovar_getbuf(dev, "mkeep_alive", &id, sizeof(id), buf,
++				total_len, NULL);
++			if (!ret) {
++				mkeep_alive_pktp = (wl_mkeep_alive_pkt_t *) buf;
++				bytes_written += snprintf(command+bytes_written, total_len,
++					"Id            :%d\n"
++					"Period (msec) :%d\n"
++					"Length        :%d\n"
++					"Packet        :0x",
++					mkeep_alive_pktp->keep_alive_id,
++					dtoh32(mkeep_alive_pktp->period_msec),
++					dtoh16(mkeep_alive_pktp->len_bytes));
++				for (i=0; i<mkeep_alive_pktp->len_bytes; i++) {
++					bytes_written += snprintf(command+bytes_written, total_len,
++						"%02x", mkeep_alive_pktp->data[i]);
++				}
++				AEXT_TRACE(dev->name, "command result is %s\n", command);
++				ret = bytes_written;
++			}
++		}
++	}
++
++exit:
++	if (buf)
++		kfree(buf);
++	if (packet)
++		kfree(packet);
++	return ret;
++}
++
++#ifdef WL_EXT_TCPKA
++static int
++wl_ext_tcpka_conn_add(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	int ret = 0;
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	tcpka_conn_t *tcpka = NULL;
++	uint32 sess_id = 0, ipid = 0, srcport = 0, dstport = 0, seq = 0, ack = 0,
++		tcpwin = 0, tsval = 0, tsecr = 0, len = 0, ka_payload_len = 0;
++	char dst_mac[ETHER_ADDR_STR_LEN], src_ip[IPV4_ADDR_STR_LEN],
++		dst_ip[IPV4_ADDR_STR_LEN], ka_payload[32];
++
++	if (data) {
++		memset(dst_mac, 0, sizeof(dst_mac));
++		memset(src_ip, 0, sizeof(src_ip));
++		memset(dst_ip, 0, sizeof(dst_ip));
++		memset(ka_payload, 0, sizeof(ka_payload));
++		sscanf(data, "%d %s %s %s %d %d %d %u %u %d %u %u %u %32s",
++			&sess_id, dst_mac, src_ip, dst_ip, &ipid, &srcport, &dstport, &seq,
++			&ack, &tcpwin, &tsval, &tsecr, &len, ka_payload);
++
++		ka_payload_len = strlen(ka_payload) / 2;
++		tcpka = kmalloc(sizeof(struct tcpka_conn) + ka_payload_len, GFP_KERNEL);
++		if (tcpka == NULL) {
++			AEXT_ERROR(dev->name, "Failed to allocate buffer of %d bytes\n",
++				sizeof(struct tcpka_conn) + ka_payload_len);
++			goto exit;
++		}
++		memset(tcpka, 0, sizeof(struct tcpka_conn) + ka_payload_len);
++
++		tcpka->sess_id = sess_id;
++		if (!(ret = bcm_ether_atoe(dst_mac, &tcpka->dst_mac))) {
++			AEXT_ERROR(dev->name, "mac parsing err addr=%s\n", dst_mac);
++			goto exit;
++		}
++		if (!bcm_atoipv4(src_ip, &tcpka->src_ip)) {
++			AEXT_ERROR(dev->name, "src_ip parsing err ip=%s\n", src_ip);
++			goto exit;
++		}
++		if (!bcm_atoipv4(dst_ip, &tcpka->dst_ip)) {
++			AEXT_ERROR(dev->name, "dst_ip parsing err ip=%s\n", dst_ip);
++			goto exit;
++		}
++		tcpka->ipid = ipid;
++		tcpka->srcport = srcport;
++		tcpka->dstport = dstport;
++		tcpka->seq = seq;
++		tcpka->ack = ack;
++		tcpka->tcpwin = tcpwin;
++		tcpka->tsval = tsval;
++		tcpka->tsecr = tsecr;
++		tcpka->len = len;
++		ka_payload_len = wl_pattern_atoh(ka_payload, (char *)tcpka->ka_payload);
++		if (ka_payload_len == -1) {
++			AEXT_ERROR(dev->name,"rejecting ka_payload=%s\n", ka_payload);
++			goto exit;
++		}
++		tcpka->ka_payload_len = ka_payload_len;
++
++		AEXT_INFO(dev->name,
++			"tcpka_conn_add %d %pM %pM %pM %d %d %d %u %u %d %u %u %u %u \"%s\"\n",
++			tcpka->sess_id, &tcpka->dst_mac, &tcpka->src_ip, &tcpka->dst_ip,
++			tcpka->ipid, tcpka->srcport, tcpka->dstport, tcpka->seq,
++			tcpka->ack, tcpka->tcpwin, tcpka->tsval, tcpka->tsecr,
++			tcpka->len, tcpka->ka_payload_len, tcpka->ka_payload);
++
++		ret = wl_ext_iovar_setbuf(dev, "tcpka_conn_add", (char *)tcpka,
++			(sizeof(tcpka_conn_t) + tcpka->ka_payload_len - 1),
++			iovar_buf, sizeof(iovar_buf), NULL);
++	}
++
++exit:
++	if (tcpka)
++		kfree(tcpka);
++	return ret;
++}
++
++static int
++wl_ext_tcpka_conn_enable(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	tcpka_conn_sess_t tcpka_conn;
++	int ret = 0;
++	uint32 sess_id = 0, flag, interval = 0, retry_interval = 0, retry_count = 0;
++
++	if (data) {
++		sscanf(data, "%d %d %d %d %d",
++			&sess_id, &flag, &interval, &retry_interval, &retry_count);
++		tcpka_conn.sess_id = sess_id;
++		tcpka_conn.flag = flag;
++		if (tcpka_conn.flag) {
++			tcpka_conn.tcpka_timers.interval = interval;
++			tcpka_conn.tcpka_timers.retry_interval = retry_interval;
++			tcpka_conn.tcpka_timers.retry_count = retry_count;
++		} else {
++			tcpka_conn.tcpka_timers.interval = 0;
++			tcpka_conn.tcpka_timers.retry_interval = 0;
++			tcpka_conn.tcpka_timers.retry_count = 0;
++		}
++
++		AEXT_INFO(dev->name, "tcpka_conn_enable %d %d %d %d %d\n",
++			tcpka_conn.sess_id, tcpka_conn.flag,
++			tcpka_conn.tcpka_timers.interval,
++			tcpka_conn.tcpka_timers.retry_interval,
++			tcpka_conn.tcpka_timers.retry_count);
++
++		ret = wl_ext_iovar_setbuf(dev, "tcpka_conn_enable", (char *)&tcpka_conn,
++			sizeof(tcpka_conn_sess_t), iovar_buf, sizeof(iovar_buf), NULL);
++	}
++
++	return ret;
++}
++
++static int
++wl_ext_tcpka_conn_info(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	tcpka_conn_sess_info_t *info = NULL;
++	uint32 sess_id = 0;
++	int ret = 0, bytes_written = 0;
++
++	if (data) {
++		sscanf(data, "%d", &sess_id);
++		AEXT_INFO(dev->name, "tcpka_conn_sess_info %d\n", sess_id);
++		ret = wl_ext_iovar_getbuf(dev, "tcpka_conn_sess_info", (char *)&sess_id,
++			sizeof(uint32), iovar_buf, sizeof(iovar_buf), NULL);
++		if (!ret) {
++			info = (tcpka_conn_sess_info_t *) iovar_buf;
++			bytes_written += snprintf(command+bytes_written, total_len,
++				"id   :%d\n"
++				"ipid :%d\n"
++				"seq  :%u\n"
++				"ack  :%u",
++				sess_id, info->ipid, info->seq, info->ack);
++			AEXT_INFO(dev->name, "%s\n", command);
++			ret = bytes_written;
++		}
++	}
++
++	return ret;
++}
++#endif /* WL_EXT_TCPKA */
++
++static int
++wl_ext_rsdb_mode(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	wl_config_t rsdb_mode_cfg = {1, 0}, *rsdb_p;
++	int ret = 0;
++
++	if (data) {
++		rsdb_mode_cfg.config = (int)simple_strtol(data, NULL, 0);
++		ret = wl_ext_iovar_setbuf(dev, "rsdb_mode", (char *)&rsdb_mode_cfg,
++			sizeof(rsdb_mode_cfg), iovar_buf, WLC_IOCTL_SMLEN, NULL);
++		AEXT_INFO(dev->name, "rsdb_mode %d\n", rsdb_mode_cfg.config);
++	} else {
++		ret = wl_ext_iovar_getbuf(dev, "rsdb_mode", NULL, 0,
++			iovar_buf, WLC_IOCTL_SMLEN, NULL);
++		if (!ret) {
++			rsdb_p = (wl_config_t *) iovar_buf;
++			ret = snprintf(command, total_len, "%d", rsdb_p->config);
++			AEXT_TRACE(dev->name, "command result is %s\n", command);
++		}
++	}
++
++	return ret;
++}
++
++static int
++wl_ext_recal(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	int ret = 0, i, nchan, nssid = 0;
++	int params_size = WL_SCAN_PARAMS_FIXED_SIZE + WL_NUMCHANNELS * sizeof(uint16);
++	wl_scan_params_t *params = NULL;
++	int ioctl_ver;
++	char *p;
++
++	AEXT_TRACE(dev->name, "Enter\n");
++
++	if (data) {
++		params_size += WL_SCAN_PARAMS_SSID_MAX * sizeof(wlc_ssid_t);
++		params = (wl_scan_params_t *) kzalloc(params_size, GFP_KERNEL);
++		if (params == NULL) {
++			ret = -ENOMEM;
++			goto exit;
++		}
++		memset(params, 0, params_size);
++
++		wl_ext_get_ioctl_ver(dev, &ioctl_ver);
++
++		memcpy(&params->bssid, &ether_bcast, ETHER_ADDR_LEN);
++		params->bss_type = DOT11_BSSTYPE_ANY;
++		params->scan_type = 0;
++		params->nprobes = -1;
++		params->active_time = -1;
++		params->passive_time = -1;
++		params->home_time = -1;
++		params->channel_num = 0;
++
++		params->scan_type |= WL_SCANFLAGS_PASSIVE;
++		nchan = 2;
++		params->channel_list[0] = wf_channel2chspec(1, WL_CHANSPEC_BW_20);
++		params->channel_list[1] = wf_channel2chspec(2, WL_CHANSPEC_BW_20);
++
++		params->nprobes = htod32(params->nprobes);
++		params->active_time = htod32(params->active_time);
++		params->passive_time = htod32(params->passive_time);
++		params->home_time = htod32(params->home_time);
++
++		for (i = 0; i < nchan; i++) {
++			wl_ext_chspec_host_to_driver(ioctl_ver, params->channel_list[i]);
++		}
++
++		p = (char*)params->channel_list + nchan * sizeof(uint16);
++
++		params->channel_num = htod32((nssid << WL_SCAN_PARAMS_NSSID_SHIFT) |
++		                             (nchan & WL_SCAN_PARAMS_COUNT_MASK));
++		params_size = p - (char*)params + nssid * sizeof(wlc_ssid_t);
++
++		AEXT_INFO(dev->name, "recal\n");
++		ret = wl_ext_ioctl(dev, WLC_SCAN, params, params_size, 1);
++	}
++
++exit:
++	if (params)
++		kfree(params);
++	return ret;
++}
++
++static s32
++wl_ext_add_remove_eventmsg(struct net_device *ndev, u16 event, bool add)
++{
++	s8 iovbuf[WL_EVENTING_MASK_LEN + 12];
++	s8 eventmask[WL_EVENTING_MASK_LEN];
++	s32 err = 0;
++
++	if (!ndev)
++		return -ENODEV;
++
++	/* Setup event_msgs */
++	err = wldev_iovar_getbuf(ndev, "event_msgs", NULL, 0, iovbuf, sizeof(iovbuf), NULL);
++	if (unlikely(err)) {
++		AEXT_ERROR(ndev->name, "Get event_msgs error (%d)\n", err);
++		goto eventmsg_out;
++	}
++	memcpy(eventmask, iovbuf, WL_EVENTING_MASK_LEN);
++	if (add) {
++		setbit(eventmask, event);
++	} else {
++		clrbit(eventmask, event);
++	}
++	err = wldev_iovar_setbuf(ndev, "event_msgs", eventmask, WL_EVENTING_MASK_LEN, iovbuf,
++			sizeof(iovbuf), NULL);
++	if (unlikely(err)) {
++		AEXT_ERROR(ndev->name, "Set event_msgs error (%d)\n", err);
++		goto eventmsg_out;
++	}
++
++eventmsg_out:
++	return err;
++}
++
++static int
++wl_ext_event_msg(struct net_device *dev, char *data,
++	char *command, int total_len)
++{
++	s8 iovbuf[WL_EVENTING_MASK_LEN + 12];
++	s8 eventmask[WL_EVENTING_MASK_LEN];
++	int i, bytes_written = 0, add = -1;
++	uint event;
++	char *vbuf;
++	bool skipzeros;
++
++	/* dhd_priv wl event_msg [offset] [1/0, 1 for add, 0 for remove] */
++	/* dhd_priv wl event_msg 40 1 */
++	if (data) {
++		AEXT_TRACE(dev->name, "data = %s\n", data);
++		sscanf(data, "%d %d", &event, &add);
++		/* Setup event_msgs */
++		bytes_written = wldev_iovar_getbuf(dev, "event_msgs", NULL, 0, iovbuf,
++			sizeof(iovbuf), NULL);
++		if (unlikely(bytes_written)) {
++			AEXT_ERROR(dev->name, "Get event_msgs error (%d)\n", bytes_written);
++			goto eventmsg_out;
++		}
++		memcpy(eventmask, iovbuf, WL_EVENTING_MASK_LEN);
++		if (add == -1) {
++			if (isset(eventmask, event))
++				bytes_written += snprintf(command+bytes_written, total_len, "1");
++			else
++				bytes_written += snprintf(command+bytes_written, total_len, "0");
++			AEXT_INFO(dev->name, "%s\n", command);
++			goto eventmsg_out;
++		}
++		bytes_written = wl_ext_add_remove_eventmsg(dev, event, add);
++	}
++	else {
++		/* Setup event_msgs */
++		bytes_written = wldev_iovar_getbuf(dev, "event_msgs", NULL, 0, iovbuf,
++			sizeof(iovbuf), NULL);
++		if (bytes_written) {
++			AEXT_ERROR(dev->name, "Get event_msgs error (%d)\n", bytes_written);
++			goto eventmsg_out;
++		}
++		vbuf = (char *)iovbuf;
++		bytes_written += snprintf(command+bytes_written, total_len, "0x");
++		for (i = (sizeof(eventmask) - 1); i >= 0; i--) {
++			if (vbuf[i] || (i == 0))
++				skipzeros = FALSE;
++			if (skipzeros)
++				continue;
++			bytes_written += snprintf(command+bytes_written, total_len,
++				"%02x", vbuf[i] & 0xff);
++		}
++		AEXT_INFO(dev->name, "%s\n", command);
++	}
++
++eventmsg_out:
++	return bytes_written;
++}
++
++#ifdef PKT_FILTER_SUPPORT
++extern void dhd_pktfilter_offload_set(dhd_pub_t * dhd, char *arg);
++extern void dhd_pktfilter_offload_delete(dhd_pub_t *dhd, int id);
++extern void dhd_pktfilter_offload_enable(dhd_pub_t * dhd, char *arg, int enable, int master_mode);
++static int
++wl_ext_pkt_filter_add(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	int i, filter_id, new_id = 0, cnt;
++	conf_pkt_filter_add_t *filter_add = &dhd->conf->pkt_filter_add;
++	char **pktfilter = dhd->pktfilter;
++	int err = 0;
++
++	if (data) {
++		AEXT_TRACE(dev->name, "data = %s\n", data);
++
++		new_id = simple_strtol(data, NULL, 10);
++		if (new_id <= 0) {
++			AEXT_ERROR(dev->name, "wrong id %d\n", new_id);
++			return -1;
++		}
++
++		cnt = dhd->pktfilter_count;
++		for (i=0; i<cnt; i++) {
++			if (!pktfilter[i])
++				continue;
++			filter_id = simple_strtol(pktfilter[i], NULL, 10);
++			if (new_id == filter_id) {
++				AEXT_ERROR(dev->name, "filter id %d already in list\n", filter_id);
++				return -1;
++			}
++		}
++
++		cnt = filter_add->count;
++		if (cnt >= DHD_CONF_FILTER_MAX) {
++			AEXT_ERROR(dev->name, "not enough filter\n");
++			return -1;
++		}
++		for (i=0; i<cnt; i++) {
++			filter_id = simple_strtol(filter_add->filter[i], NULL, 10);
++			if (new_id == filter_id) {
++				AEXT_ERROR(dev->name, "filter id %d already in list\n", filter_id);
++				return -1;
++			}
++		}
++
++		strcpy(&filter_add->filter[cnt][0], data);
++		dhd->pktfilter[dhd->pktfilter_count] = filter_add->filter[cnt];
++		filter_add->count++;
++		dhd->pktfilter_count++;
++
++		dhd_pktfilter_offload_set(dhd, data);
++		AEXT_INFO(dev->name, "filter id %d added\n", new_id);
++	}
++
++	return err;
++}
++
++static int
++wl_ext_pkt_filter_delete(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	int i, j, filter_id, cnt;
++	char **pktfilter = dhd->pktfilter;
++	conf_pkt_filter_add_t *filter_add = &dhd->conf->pkt_filter_add;
++	bool in_filter = FALSE;
++	int id, err = 0;
++
++	if (data) {
++		AEXT_TRACE(dev->name, "data = %s\n", data);
++		id = (int)simple_strtol(data, NULL, 0);
++
++		cnt = filter_add->count;
++		for (i=0; i<cnt; i++) {
++			filter_id = simple_strtol(filter_add->filter[i], NULL, 10);
++			if (id == filter_id) {
++				in_filter = TRUE;
++				memset(filter_add->filter[i], 0, PKT_FILTER_LEN);
++				for (j=i; j<(cnt-1); j++) {
++					strcpy(filter_add->filter[j], filter_add->filter[j+1]);
++					memset(filter_add->filter[j+1], 0, PKT_FILTER_LEN);
++				}
++				cnt--;
++				filter_add->count--;
++				dhd->pktfilter_count--;
++			}
++		}
++
++		cnt = dhd->pktfilter_count;
++		for (i=0; i<cnt; i++) {
++			if (!pktfilter[i])
++				continue;
++			filter_id = simple_strtol(pktfilter[i], NULL, 10);
++			if (id == filter_id) {
++				in_filter = TRUE;
++				memset(pktfilter[i], 0, strlen(pktfilter[i]));
++			}
++		}
++
++		if (in_filter) {
++			dhd_pktfilter_offload_delete(dhd, id);
++			AEXT_INFO(dev->name, "filter id %d deleted\n", id);
++		} else {
++			AEXT_ERROR(dev->name, "filter id %d not in list\n", id);
++			err = -1;
++		}
++	}
++
++	return err;
++}
++
++static int
++wl_ext_pkt_filter_enable(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	int err = 0, id, enable;
++	int i, filter_id, cnt;
++	char **pktfilter = dhd->pktfilter;
++	bool in_filter = FALSE;
++
++	/* dhd_priv wl pkt_filter_enable [id] [1/0] */
++	/* dhd_priv wl pkt_filter_enable 141 1 */
++	if (data) {
++		sscanf(data, "%d %d", &id, &enable);
++
++		cnt = dhd->pktfilter_count;
++		for (i=0; i<cnt; i++) {
++			if (!pktfilter[i])
++				continue;
++			filter_id = simple_strtol(pktfilter[i], NULL, 10);
++			if (id == filter_id) {
++				in_filter = TRUE;
++				break;
++			}
++		}
++
++		if (in_filter) {
++			dhd_pktfilter_offload_enable(dhd, dhd->pktfilter[i],
++				enable, dhd_master_mode);
++			AEXT_INFO(dev->name, "filter id %d %s\n", id, enable?"enabled":"disabled");
++		} else {
++			AEXT_ERROR(dev->name, "filter id %d not in list\n", id);
++			err = -1;
++		}
++	}
++
++	return err;
++}
++#endif /* PKT_FILTER_SUPPORT */
++
++#ifdef SENDPROB
++static int
++wl_ext_send_probreq(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	int err = 0;
++	char addr_str[16], addr[6];
++	char iovar_buf[WLC_IOCTL_SMLEN]="\0";
++	char ie_data[WLC_IOCTL_SMLEN] = "\0";
++	wl_probe_params_t params;
++
++	/* dhd_priv wl send_probreq [dest. addr] [OUI+VAL] */
++	/* dhd_priv wl send_probreq 0x00904c010203 0x00904c01020304050607 */
++	if (data) {
++		AEXT_TRACE(dev->name, "data = %s\n", data);
++		sscanf(data, "%s %s", addr_str, ie_data);
++		AEXT_TRACE(dev->name, "addr=%s, ie=%s\n", addr_str, ie_data);
++
++		if (strlen(addr_str) != 14) {
++			AEXT_ERROR(dev->name, "wrong addr %s\n", addr_str);
++			goto exit;
++		}
++		wl_pattern_atoh(addr_str, (char *) addr);
++		memset(&params, 0, sizeof(params));
++		memcpy(&params.bssid, addr, ETHER_ADDR_LEN);
++		memcpy(&params.mac, addr, ETHER_ADDR_LEN);
++
++		err = wl_ext_add_del_ie(dev, VNDR_IE_PRBREQ_FLAG, ie_data, "add");
++		if (err)
++			goto exit;
++		err = wl_ext_iovar_setbuf(dev, "sendprb", (char *)&params, sizeof(params),
++			iovar_buf, sizeof(iovar_buf), NULL);
++		OSL_SLEEP(100);
++		wl_ext_add_del_ie(dev, VNDR_IE_PRBREQ_FLAG, ie_data, "del");
++	}
++
++exit:
++    return err;
++}
++
++static int
++wl_ext_send_probresp(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	int err = 0;
++	char addr_str[16], addr[6];
++	char iovar_buf[WLC_IOCTL_SMLEN]="\0";
++	char ie_data[WLC_IOCTL_SMLEN] = "\0";
++
++	/* dhd_priv wl send_probresp [dest. addr] [OUI+VAL] */
++	/* dhd_priv wl send_probresp 0x00904c010203 0x00904c01020304050607 */
++	if (data) {
++		AEXT_TRACE(dev->name, "data = %s\n", data);
++		sscanf(data, "%s %s", addr_str, ie_data);
++		AEXT_TRACE(dev->name, "addr=%s, ie=%s\n", addr_str, ie_data);
++
++		if (strlen(addr_str) != 14) {
++			AEXT_ERROR(dev->name, "wrong addr %s\n", addr_str);
++			goto exit;
++		}
++		wl_pattern_atoh(addr_str, (char *) addr);
++
++		err = wl_ext_add_del_ie(dev, VNDR_IE_PRBRSP_FLAG, ie_data, "add");
++		if (err)
++			goto exit;
++		err = wl_ext_iovar_setbuf(dev, "send_probresp", addr, sizeof(addr),
++			iovar_buf, sizeof(iovar_buf), NULL);
++		OSL_SLEEP(100);
++		wl_ext_add_del_ie(dev, VNDR_IE_PRBRSP_FLAG, ie_data, "del");
++	}
++
++exit:
++    return err;
++}
++
++static int
++wl_ext_recv_probreq(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	int err = 0, enable = 0;
++	char cmd[32];
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++
++	/* enable:
++	    1. dhd_priv wl 86 0
++	    2. dhd_priv wl event_msg 44 1
++	    disable:
++	    1. dhd_priv wl 86 2;
++	    2. dhd_priv wl event_msg 44 0
++	*/
++	if (data) {
++		AEXT_TRACE(dev->name, "data = %s\n", data);
++		sscanf(data, "%d", &enable);
++		if (enable) {
++			strcpy(cmd, "wl 86 0");
++			err = wl_ext_wl_iovar(dev, cmd, total_len);
++			if (err)
++				goto exit;
++			strcpy(cmd, "wl event_msg 44 1");
++			err = wl_ext_wl_iovar(dev, cmd, total_len);
++			if (err)
++				goto exit;
++			dhd->recv_probereq = TRUE;
++		} else {
++			if (dhd->conf->pm)
++				strcpy(cmd, "wl 86 2"); {
++				wl_ext_wl_iovar(dev, cmd, total_len);
++			}
++			strcpy(cmd, "wl event_msg 44 0");
++			wl_ext_wl_iovar(dev, cmd, total_len);
++			dhd->recv_probereq = FALSE;
++		}
++	}
++
++exit:
++    return err;
++}
++
++static int
++wl_ext_recv_probresp(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	int err = 0, enable = 0;
++	char cmd[32];
++
++	/* enable:
++	    1. dhd_priv wl pkt_filter_add 150 0 0 0 0xFF 0x50
++	    2. dhd_priv wl pkt_filter_enable 150 1 
++	    3. dhd_priv wl mpc 0
++	    4. dhd_priv wl 108 1
++	    disable:
++	    1. dhd_priv wl 108 0
++	    2. dhd_priv wl mpc 1
++	    3. dhd_priv wl pkt_filter_disable 150 0
++	    4. dhd_priv pkt_filter_delete 150
++	*/
++	if (data) {
++		AEXT_TRACE(dev->name, "data = %s\n", data);
++		sscanf(data, "%d", &enable);
++		if (enable) {
++			strcpy(cmd, "wl pkt_filter_add 150 0 0 0 0xFF 0x50");
++			err = wl_ext_wl_iovar(dev, cmd, total_len);
++			if (err)
++				goto exit;
++			strcpy(cmd, "wl pkt_filter_enable 150 1");
++			err = wl_ext_wl_iovar(dev, cmd, total_len);
++			if (err)
++				goto exit;
++			strcpy(cmd, "wl mpc 0");
++			err = wl_ext_wl_iovar(dev, cmd, total_len);
++			if (err)
++				goto exit;
++			strcpy(cmd, "wl 108 1");
++			err= wl_ext_wl_iovar(dev, cmd, total_len);
++		} else {
++			strcpy(cmd, "wl 108 0");
++			wl_ext_wl_iovar(dev, cmd, total_len);
++			strcpy(cmd, "wl mpc 1");
++			wl_ext_wl_iovar(dev, cmd, total_len);
++			strcpy(cmd, "wl pkt_filter_enable 150 0");
++			wl_ext_wl_iovar(dev, cmd, total_len);
++			strcpy(cmd, "wl pkt_filter_delete 150");
++			wl_ext_wl_iovar(dev, cmd, total_len);
++		}
++	}
++
++exit:
++    return err;
++}
++#endif /* SENDPROB */
++
++static int
++wl_ext_gtk_key_info(struct net_device *dev, char *data, char *command, int total_len)
++{
++	int err = 0;
++	char iovar_buf[WLC_IOCTL_SMLEN]="\0";
++	gtk_keyinfo_t keyinfo;
++	bcol_gtk_para_t bcol_keyinfo;
++
++	/* wl gtk_key_info [kck kek replay_ctr] */
++	/* wl gtk_key_info 001122..FF001122..FF00000000000001 */
++	if (data) {
++		memset(&keyinfo, 0, sizeof(keyinfo));
++		memcpy(&keyinfo, data, RSN_KCK_LENGTH+RSN_KEK_LENGTH+RSN_REPLAY_LEN);
++		if (android_msg_level & ANDROID_INFO_LEVEL) {
++			prhex("kck", (uchar *)keyinfo.KCK, RSN_KCK_LENGTH);
++			prhex("kek", (uchar *)keyinfo.KEK, RSN_KEK_LENGTH);
++			prhex("replay_ctr", (uchar *)keyinfo.ReplayCounter, RSN_REPLAY_LEN);
++		}
++
++		memset(&bcol_keyinfo, 0, sizeof(bcol_keyinfo));
++		bcol_keyinfo.enable = 1;
++		bcol_keyinfo.ptk_len = 64;
++		memcpy(&bcol_keyinfo.ptk, data, RSN_KCK_LENGTH+RSN_KEK_LENGTH);
++		err = wl_ext_iovar_setbuf(dev, "bcol_gtk_rekey_ptk", &bcol_keyinfo,
++			sizeof(bcol_keyinfo), iovar_buf, sizeof(iovar_buf), NULL);
++		if (!err) {
++			goto exit;
++		}
++
++		err = wl_ext_iovar_setbuf(dev, "gtk_key_info", &keyinfo, sizeof(keyinfo),
++			iovar_buf, sizeof(iovar_buf), NULL);
++		if (err) {
++			AEXT_ERROR(dev->name, "failed to set gtk_key_info\n");
++			goto exit;
++		}
++	}
++
++exit:
++    return err;
++}
++
++#ifdef WL_EXT_WOWL
++static int
++wl_ext_wowl_pattern(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	uint buf_len = 0;
++	int	offset;
++	char mask[128]="\0", pattern[128]="\0", add[4]="\0",
++		mask_tmp[128], *pmask_tmp;
++	uint32 masksize, patternsize, pad_len = 0;
++	wl_wowl_pattern2_t *wowl_pattern2 = NULL;
++	wl_wowl_pattern_t *wowl_pattern = NULL;
++	char *mask_and_pattern;
++	wl_wowl_pattern_list_t *list;
++	uint8 *ptr;
++	int ret = 0, i, j, v;
++
++	if (data) {
++		sscanf(data, "%s %d %s %s", add, &offset, mask_tmp, pattern);
++		if (strcmp(add, "add") != 0 && strcmp(add, "clr") != 0) {
++			AEXT_ERROR(dev->name, "first arg should be add or clr\n");
++			goto exit;
++		}
++		if (!strcmp(add, "clr")) {
++			AEXT_INFO(dev->name, "wowl_pattern clr\n");
++			ret = wl_ext_iovar_setbuf(dev, "wowl_pattern", add,
++				sizeof(add), iovar_buf, sizeof(iovar_buf), NULL);
++			goto exit;
++		}
++		masksize = strlen(mask_tmp) -2;
++		AEXT_TRACE(dev->name, "0 mask_tmp=%s, masksize=%d\n", mask_tmp, masksize);
++
++		// add pading
++		if (masksize % 16)
++			pad_len = (16 - masksize % 16);
++		for (i=0; i<pad_len; i++)
++			strcat(mask_tmp, "0");
++		masksize += pad_len;
++		AEXT_TRACE(dev->name, "1 mask_tmp=%s, masksize=%d\n", mask_tmp, masksize);
++
++		// translate 0x00 to 0, others to 1
++		j = 0;
++		pmask_tmp = &mask_tmp[2];
++		for (i=0; i<masksize/2; i++) {
++			if(strncmp(&pmask_tmp[i*2], "00", 2))
++				pmask_tmp[j] = '1';
++			else
++				pmask_tmp[j] = '0';
++			j++;
++		}
++		pmask_tmp[j] = '\0';
++		masksize = masksize / 2;
++		AEXT_TRACE(dev->name, "2 mask_tmp=%s, masksize=%d\n", mask_tmp, masksize);
++
++		// reorder per 8bits
++		pmask_tmp = &mask_tmp[2];
++		for (i=0; i<masksize/8; i++) {
++			char c;
++			for (j=0; j<4; j++) {
++				c = pmask_tmp[i*8+j];
++				pmask_tmp[i*8+j] = pmask_tmp[(i+1)*8-j-1];
++				pmask_tmp[(i+1)*8-j-1] = c;
++			}
++		}
++		AEXT_TRACE(dev->name, "3 mask_tmp=%s, masksize=%d\n", mask_tmp, masksize);
++
++		// translate 8bits to 1byte
++		j = 0; v = 0;
++		pmask_tmp = &mask_tmp[2];
++		strcpy(mask, "0x");
++		for (i=0; i<masksize; i++) {
++			v = (v<<1) | (pmask_tmp[i]=='1');
++			if (((i+1)%4) == 0) {
++				if (v < 10)
++					mask[j+2] = v + '0';
++				else
++					mask[j+2] = (v-10) + 'a';
++				j++;
++				v = 0;
++			}
++		}
++		mask[j+2] = '\0';
++		masksize = j/2;
++		AEXT_TRACE(dev->name, "4 mask=%s, masksize=%d\n", mask, masksize);
++
++		patternsize = (strlen(pattern)-2)/2;
++		buf_len = sizeof(wl_wowl_pattern2_t) + patternsize + masksize;
++		wowl_pattern2 = kmalloc(buf_len, GFP_KERNEL);
++		if (wowl_pattern2 == NULL) {
++			AEXT_ERROR(dev->name, "Failed to allocate buffer of %d bytes\n", buf_len);
++			goto exit;
++		}
++		memset(wowl_pattern2, 0, sizeof(wl_wowl_pattern2_t));
++
++		strncpy(wowl_pattern2->cmd, add, sizeof(add));
++		wowl_pattern2->wowl_pattern.type = 0;
++		wowl_pattern2->wowl_pattern.offset = offset;
++		mask_and_pattern = (char*)wowl_pattern2 + sizeof(wl_wowl_pattern2_t);
++
++		wowl_pattern2->wowl_pattern.masksize = masksize;
++		ret = wl_pattern_atoh(mask, mask_and_pattern);
++		if (ret == -1) {
++			AEXT_ERROR(dev->name, "rejecting mask=%s\n", mask);
++			goto exit;
++		}
++
++		mask_and_pattern += wowl_pattern2->wowl_pattern.masksize;
++		wowl_pattern2->wowl_pattern.patternoffset = sizeof(wl_wowl_pattern_t) +
++			wowl_pattern2->wowl_pattern.masksize;
++
++		wowl_pattern2->wowl_pattern.patternsize = patternsize;
++		ret = wl_pattern_atoh(pattern, mask_and_pattern);
++		if (ret == -1) {
++			AEXT_ERROR(dev->name, "rejecting pattern=%s\n", pattern);
++			goto exit;
++		}
++
++		AEXT_INFO(dev->name, "%s %d %s %s\n", add, offset, mask, pattern);
++
++		ret = wl_ext_iovar_setbuf(dev, "wowl_pattern", (char *)wowl_pattern2,
++			buf_len, iovar_buf, sizeof(iovar_buf), NULL);
++	}
++	else {
++		ret = wl_ext_iovar_getbuf(dev, "wowl_pattern", NULL, 0,
++			iovar_buf, sizeof(iovar_buf), NULL);
++		if (!ret) {
++			list = (wl_wowl_pattern_list_t *)iovar_buf;
++			ret = snprintf(command, total_len, "#of patterns :%d\n", list->count);
++			ptr = (uint8 *)list->pattern;
++			for (i=0; i<list->count; i++) {
++				uint8 *pattern;
++				wowl_pattern = (wl_wowl_pattern_t *)ptr;
++				ret += snprintf(command+ret, total_len,
++					"Pattern %d:\n"
++					"ID         :0x%x\n"
++					"Offset     :%d\n"
++					"Masksize   :%d\n"
++					"Mask       :0x",
++					i+1, (uint32)wowl_pattern->id, wowl_pattern->offset,
++					wowl_pattern->masksize);
++				pattern = ((uint8 *)wowl_pattern + sizeof(wl_wowl_pattern_t));
++				for (j = 0; j < wowl_pattern->masksize; j++) {
++					ret += snprintf(command+ret, total_len, "%02x", pattern[j]);
++				}
++				ret += snprintf(command+ret, total_len, "\n");
++				ret += snprintf(command+ret, total_len,
++					"PatternSize:%d\n"
++					"Pattern    :0x",
++					wowl_pattern->patternsize);
++
++				pattern = ((uint8*)wowl_pattern + wowl_pattern->patternoffset);
++				for (j=0; j<wowl_pattern->patternsize; j++)
++					ret += snprintf(command+ret, total_len, "%02x", pattern[j]);
++				ret += snprintf(command+ret, total_len, "\n");
++				ptr += (wowl_pattern->masksize + wowl_pattern->patternsize +
++				        sizeof(wl_wowl_pattern_t));
++			}
++
++			AEXT_INFO(dev->name, "%s\n", command);
++		}
++	}
++
++exit:
++	if (wowl_pattern2)
++		kfree(wowl_pattern2);
++	return ret;
++}
++
++static int
++wl_ext_wowl_wakeind(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	wl_wowl_wakeind_t *wake = NULL;
++	int ret = -1;
++	char clr[6]="\0";
++
++	if (data) {
++		sscanf(data, "%s", clr);
++		if (!strcmp(clr, "clear")) {
++			AEXT_INFO(dev->name, "wowl_wakeind clear\n");
++			ret = wl_ext_iovar_setbuf(dev, "wowl_wakeind", clr, sizeof(clr),
++				iovar_buf, sizeof(iovar_buf), NULL);
++		} else {
++			AEXT_ERROR(dev->name, "first arg should be clear\n");
++		}
++	} else {
++		ret = wl_ext_iovar_getbuf(dev, "wowl_wakeind", NULL, 0,
++			iovar_buf, sizeof(iovar_buf), NULL);
++		if (!ret) {
++			wake = (wl_wowl_wakeind_t *) iovar_buf;
++			ret = snprintf(command, total_len, "wakeind=0x%x", wake->ucode_wakeind);
++			if (wake->ucode_wakeind & WL_WOWL_MAGIC)
++				ret += snprintf(command+ret, total_len, " (MAGIC packet)");
++			if (wake->ucode_wakeind & WL_WOWL_NET)
++				ret += snprintf(command+ret, total_len, " (Netpattern)");
++			if (wake->ucode_wakeind & WL_WOWL_DIS)
++				ret += snprintf(command+ret, total_len, " (Disassoc/Deauth)");
++			if (wake->ucode_wakeind & WL_WOWL_BCN)
++				ret += snprintf(command+ret, total_len, " (Loss of beacon)");
++			if (wake->ucode_wakeind & WL_WOWL_TCPKEEP_TIME)
++				ret += snprintf(command+ret, total_len, " (TCPKA timeout)");
++			if (wake->ucode_wakeind & WL_WOWL_TCPKEEP_DATA)
++				ret += snprintf(command+ret, total_len, " (TCPKA data)");
++			if (wake->ucode_wakeind & WL_WOWL_TCPFIN)
++				ret += snprintf(command+ret, total_len, " (TCP FIN)");
++			AEXT_INFO(dev->name, "%s\n", command);
++		}
++	}
++
++	return ret;
++}
++#endif /* WL_EXT_WOWL */
++
++#ifdef WL_GPIO_NOTIFY
++typedef struct notify_payload {
++	int index;
++	int len;
++	char payload[128];
++} notify_payload_t;
++
++static int
++wl_ext_gpio_notify(struct net_device *dev, char *data, char *command,
++	int total_len)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	notify_payload_t notify, *pnotify = NULL;
++	int i, ret = 0, bytes_written = 0;
++	char frame_str[WLC_IOCTL_SMLEN+3];
++
++	if (data) {
++		memset(&notify, 0, sizeof(notify));
++		memset(frame_str, 0, sizeof(frame_str));
++		sscanf(data, "%d %s", &notify.index, frame_str);
++
++		if (notify.index < 0)
++			notify.index = 0;
++
++		if (strlen(frame_str)) {
++			notify.len = wl_pattern_atoh(frame_str, notify.payload);
++			if (notify.len == -1) {
++				AEXT_ERROR(dev->name, "rejecting pattern=%s\n", frame_str);
++				goto exit;
++			}
++			AEXT_INFO(dev->name, "index=%d, len=%d\n", notify.index, notify.len);
++			if (android_msg_level & ANDROID_INFO_LEVEL)
++				prhex("payload", (uchar *)notify.payload, notify.len);
++			ret = wl_ext_iovar_setbuf(dev, "bcol_gpio_noti", (char *)&notify,
++				sizeof(notify), iovar_buf, WLC_IOCTL_SMLEN, NULL);
++		} else {
++			AEXT_INFO(dev->name, "index=%d\n", notify.index);
++			ret = wl_ext_iovar_getbuf(dev, "bcol_gpio_noti", &notify.index,
++				sizeof(notify.index), iovar_buf, sizeof(iovar_buf), NULL);
++			if (!ret) {
++				pnotify = (notify_payload_t *)iovar_buf;
++				bytes_written += snprintf(command+bytes_written, total_len,
++					"Id            :%d\n"
++					"Packet        :0x",
++					pnotify->index);
++				for (i=0; i<pnotify->len; i++) {
++					bytes_written += snprintf(command+bytes_written, total_len,
++						"%02x", pnotify->payload[i]);
++				}
++				AEXT_TRACE(dev->name, "command result is\n%s\n", command);
++				ret = bytes_written;
++			}
++		}
++	}
++
++exit:
++	return ret;
++}
++#endif /* WL_GPIO_NOTIFY */
++
++typedef int (wl_ext_tpl_parse_t)(struct net_device *dev, char *data, char *command,
++	int total_len);
++
++typedef struct wl_ext_iovar_tpl_t {
++	int get;
++	int set;
++	char *name;
++	wl_ext_tpl_parse_t *parse;
++} wl_ext_iovar_tpl_t;
++
++const wl_ext_iovar_tpl_t wl_ext_iovar_tpl_list[] = {
++	{WLC_GET_VAR,	WLC_SET_VAR,	"event_msg",	wl_ext_event_msg},
++	{WLC_GET_VAR,	WLC_SET_VAR,	"gtk_key_info",	wl_ext_gtk_key_info},
++	{WLC_GET_VAR,	WLC_SET_VAR,	"recal",		wl_ext_recal},
++	{WLC_GET_VAR,	WLC_SET_VAR,	"rsdb_mode",	wl_ext_rsdb_mode},
++	{WLC_GET_VAR,	WLC_SET_VAR,	"mkeep_alive",	wl_ext_mkeep_alive},
++#ifdef PKT_FILTER_SUPPORT
++	{WLC_GET_VAR,	WLC_SET_VAR,	"pkt_filter_add",		wl_ext_pkt_filter_add},
++	{WLC_GET_VAR,	WLC_SET_VAR,	"pkt_filter_delete",	wl_ext_pkt_filter_delete},
++	{WLC_GET_VAR,	WLC_SET_VAR,	"pkt_filter_enable",	wl_ext_pkt_filter_enable},
++#endif /* PKT_FILTER_SUPPORT */
++#if defined(WL_EXT_IAPSTA) && defined(WLMESH)
++	{WLC_GET_VAR,	WLC_SET_VAR,	"mesh_peer_status",	wl_ext_mesh_peer_status},
++#endif /* WL_EXT_IAPSTA && WLMESH */
++#ifdef SENDPROB
++	{WLC_GET_VAR,	WLC_SET_VAR,	"send_probreq",		wl_ext_send_probreq},
++	{WLC_GET_VAR,	WLC_SET_VAR,	"send_probresp",	wl_ext_send_probresp},
++	{WLC_GET_VAR,	WLC_SET_VAR,	"recv_probreq",		wl_ext_recv_probreq},
++	{WLC_GET_VAR,	WLC_SET_VAR,	"recv_probresp",	wl_ext_recv_probresp},
++#endif /* SENDPROB */
++#ifdef WL_EXT_TCPKA
++	{WLC_GET_VAR,	WLC_SET_VAR,	"tcpka_conn_add",		wl_ext_tcpka_conn_add},
++	{WLC_GET_VAR,	WLC_SET_VAR,	"tcpka_conn_enable",	wl_ext_tcpka_conn_enable},
++	{WLC_GET_VAR,	WLC_SET_VAR,	"tcpka_conn_sess_info",	wl_ext_tcpka_conn_info},
++#endif /* WL_EXT_TCPKA */
++#ifdef WL_EXT_WOWL
++	{WLC_GET_VAR,	WLC_SET_VAR,	"wowl_pattern",		wl_ext_wowl_pattern},
++	{WLC_GET_VAR,	WLC_SET_VAR,	"wowl_wakeind",		wl_ext_wowl_wakeind},
++#endif /* WL_EXT_WOWL */
++#ifdef IDHCP
++	{WLC_GET_VAR,	WLC_SET_VAR,	"dhcpc_dump",		wl_ext_dhcpc_dump},
++	{WLC_GET_VAR,	WLC_SET_VAR,	"dhcpc_param",		wl_ext_dhcpc_param},
++#endif /* IDHCP */
++#ifdef WL_GPIO_NOTIFY
++	{WLC_GET_VAR,	WLC_SET_VAR,	"bcol_gpio_noti",	wl_ext_gpio_notify},
++#endif /* WL_GPIO_NOTIFY */
++};
++
++/*
++Ex: dhd_priv wl [cmd] [val]
++  dhd_priv wl 85
++  dhd_priv wl 86 1
++  dhd_priv wl mpc
++  dhd_priv wl mpc 1
++*/
++static int
++wl_ext_wl_iovar(struct net_device *dev, char *command, int total_len)
++{
++	int cmd, val, ret = -1, i;
++	char name[32], *pch, *pick_tmp, *data;
++	int bytes_written=-1;
++	const wl_ext_iovar_tpl_t *tpl = wl_ext_iovar_tpl_list;
++	int tpl_count = ARRAY_SIZE(wl_ext_iovar_tpl_list);
++
++	AEXT_TRACE(dev->name, "cmd %s\n", command);
++	pick_tmp = command;
++
++	pch = bcmstrtok(&pick_tmp, " ", 0); // pick wl
++	if (!pch || strncmp(pch, "wl", 2))
++		goto exit;
++
++	pch = bcmstrtok(&pick_tmp, " ", 0); // pick cmd
++	if (!pch)
++		goto exit;
++
++	memset(name, 0 , sizeof (name));
++	cmd = (int)simple_strtol(pch, NULL, 0);
++	if (cmd == 0) {
++		strcpy(name, pch);
++	}
++	data = bcmstrtok(&pick_tmp, "", 0); // pick data
++	if (data && cmd == 0) {
++		cmd = WLC_SET_VAR;
++	} else if (cmd == 0) {
++		cmd = WLC_GET_VAR;
++	}
++
++	/* look for a matching code in the table */
++	for (i = 0; i < tpl_count; i++, tpl++) {
++		if ((tpl->get == cmd || tpl->set == cmd) && !strcmp(tpl->name, name))
++			break;
++	}
++	if (i < tpl_count && tpl->parse) {
++		ret = tpl->parse(dev, data, command, total_len);
++	} else {
++		if (cmd == WLC_SET_VAR) {
++			val = (int)simple_strtol(data, NULL, 0);
++			AEXT_INFO(dev->name, "set %s %d\n", name, val);
++			ret = wl_ext_iovar_setint(dev, name, val);
++		} else if (cmd == WLC_GET_VAR) {
++			AEXT_INFO(dev->name, "get %s\n", name);
++			ret = wl_ext_iovar_getint(dev, name, &val);
++			if (!ret) {
++				bytes_written = snprintf(command, total_len, "%d", val);
++				AEXT_INFO(dev->name, "command result is %s\n", command);
++				ret = bytes_written;
++			}
++		} else if (data) {
++			val = (int)simple_strtol(data, NULL, 0);
++			AEXT_INFO(dev->name, "set %d %d\n", cmd, val);
++			ret = wl_ext_ioctl(dev, cmd, &val, sizeof(val), TRUE);
++		} else {
++			AEXT_INFO(dev->name, "get %d\n", cmd);
++			ret = wl_ext_ioctl(dev, cmd, &val, sizeof(val), FALSE);
++			if (!ret) {
++				bytes_written = snprintf(command, total_len, "%d", val);
++				AEXT_INFO(dev->name, "command result is %s\n", command);
++				ret = bytes_written;
++			}
++		}
++	}
++
++exit:
++	return ret;
++}
++
++int
++wl_android_ext_priv_cmd(struct net_device *net, char *command,
++	int total_len, int *bytes_written)
++{
++	int ret = 0;
++
++	if (strnicmp(command, CMD_CHANNELS, strlen(CMD_CHANNELS)) == 0) {
++		*bytes_written = wl_ext_channels(net, command, total_len);
++	}
++	else if (strnicmp(command, CMD_CHANNEL, strlen(CMD_CHANNEL)) == 0) {
++		*bytes_written = wl_ext_channel(net, command, total_len);
++	}
++	else if (strnicmp(command, CMD_ROAM_TRIGGER, strlen(CMD_ROAM_TRIGGER)) == 0) {
++		*bytes_written = wl_ext_roam_trigger(net, command, total_len);
++	}
++	else if (strnicmp(command, CMD_PM, strlen(CMD_PM)) == 0) {
++		*bytes_written = wl_ext_pm(net, command, total_len);
++	}
++	else if (strnicmp(command, CMD_MONITOR, strlen(CMD_MONITOR)) == 0) {
++		*bytes_written = wl_ext_monitor(net, command, total_len);
++	}
++	else if (strnicmp(command, CMD_SET_SUSPEND_BCN_LI_DTIM, strlen(CMD_SET_SUSPEND_BCN_LI_DTIM)) == 0) {
++		int bcn_li_dtim;
++		bcn_li_dtim = (int)simple_strtol((command + strlen(CMD_SET_SUSPEND_BCN_LI_DTIM) + 1), NULL, 10);
++		*bytes_written = net_os_set_suspend_bcn_li_dtim(net, bcn_li_dtim);
++	}
++#ifdef WL_EXT_IAPSTA
++	else if (strnicmp(command, CMD_IAPSTA_INIT, strlen(CMD_IAPSTA_INIT)) == 0 ||
++			strnicmp(command, CMD_ISAM_INIT, strlen(CMD_ISAM_INIT)) == 0) {
++		*bytes_written = wl_ext_isam_init(net, command, total_len);
++	}
++	else if (strnicmp(command, CMD_IAPSTA_CONFIG, strlen(CMD_IAPSTA_CONFIG)) == 0 ||
++			strnicmp(command, CMD_ISAM_CONFIG, strlen(CMD_ISAM_CONFIG)) == 0) {
++		*bytes_written = wl_ext_iapsta_config(net, command, total_len);
++	}
++	else if (strnicmp(command, CMD_IAPSTA_ENABLE, strlen(CMD_IAPSTA_ENABLE)) == 0 ||
++			strnicmp(command, CMD_ISAM_ENABLE, strlen(CMD_ISAM_ENABLE)) == 0) {
++		*bytes_written = wl_ext_iapsta_enable(net, command, total_len);
++	}
++	else if (strnicmp(command, CMD_IAPSTA_DISABLE, strlen(CMD_IAPSTA_DISABLE)) == 0 ||
++			strnicmp(command, CMD_ISAM_DISABLE, strlen(CMD_ISAM_DISABLE)) == 0) {
++		*bytes_written = wl_ext_iapsta_disable(net, command, total_len);
++	}
++	else if (strnicmp(command, CMD_ISAM_STATUS, strlen(CMD_ISAM_STATUS)) == 0) {
++		*bytes_written = wl_ext_isam_status(net, command, total_len);
++	}
++	else if (strnicmp(command, CMD_ISAM_PARAM, strlen(CMD_ISAM_PARAM)) == 0) {
++		*bytes_written = wl_ext_isam_param(net, command, total_len);
++	}
++#endif /* WL_EXT_IAPSTA */
++#ifdef WL_CFG80211
++	else if (strnicmp(command, CMD_AUTOCHANNEL, strlen(CMD_AUTOCHANNEL)) == 0) {
++		*bytes_written = wl_cfg80211_autochannel(net, command, total_len);
++	}
++#endif /* WL_CFG80211 */
++#if defined(WL_WIRELESS_EXT) && defined(WL_ESCAN)
++	else if (strnicmp(command, CMD_AUTOCHANNEL, strlen(CMD_AUTOCHANNEL)) == 0) {
++		*bytes_written = wl_iw_autochannel(net, command, total_len);
++	}
++#endif /* WL_WIRELESS_EXT && WL_ESCAN */
++	else if (strnicmp(command, CMD_WL, strlen(CMD_WL)) == 0) {
++		*bytes_written = wl_ext_wl_iovar(net, command, total_len);
++	}
++	else
++		ret = -1;
++
++	return ret;
++}
++
++#if defined(WL_CFG80211) || defined(WL_ESCAN)
++int
++wl_ext_get_distance(struct net_device *net, u32 band)
++{
++	u32 bw = WL_CHANSPEC_BW_20;
++	s32 bw_cap = 0, distance = 0;
++	struct {
++		u32 band;
++		u32 bw_cap;
++	} param = {0, 0};
++	char buf[WLC_IOCTL_SMLEN]="\0";
++	s32 err = BCME_OK;
++
++	param.band = band;
++	err = wl_ext_iovar_getbuf(net, "bw_cap", &param, sizeof(param), buf,
++		sizeof(buf), NULL);
++	if (err) {
++		if (err != BCME_UNSUPPORTED) {
++			AEXT_ERROR(net->name, "bw_cap failed, %d\n", err);
++			return err;
++		} else {
++			err = wl_ext_iovar_getint(net, "mimo_bw_cap", &bw_cap);
++			if (bw_cap != WLC_N_BW_20ALL)
++				bw = WL_CHANSPEC_BW_40;
++		}
++	} else {
++		if (WL_BW_CAP_80MHZ(buf[0]))
++			bw = WL_CHANSPEC_BW_80;
++		else if (WL_BW_CAP_40MHZ(buf[0]))
++			bw = WL_CHANSPEC_BW_40;
++		else
++			bw = WL_CHANSPEC_BW_20;
++	}
++
++	if (bw == WL_CHANSPEC_BW_20)
++		distance = 2;
++	else if (bw == WL_CHANSPEC_BW_40)
++		distance = 4;
++	else if (bw == WL_CHANSPEC_BW_80)
++		distance = 8;
++	else
++		distance = 16;
++	AEXT_INFO(net->name, "bw=0x%x, distance=%d\n", bw, distance);
++
++	return distance;
++}
++
++int
++wl_ext_get_best_channel(struct net_device *net,
++#if defined(BSSCACHE)
++	wl_bss_cache_ctrl_t *bss_cache_ctrl,
++#else
++	struct wl_scan_results *bss_list,
++#endif /* BSSCACHE */
++	int ioctl_ver, int *best_2g_ch, int *best_5g_ch
++)
++{
++	struct wl_bss_info *bi = NULL;	/* must be initialized */
++	s32 i, j;
++#if defined(BSSCACHE)
++	wl_bss_cache_t *node;
++#endif /* BSSCACHE */
++	int b_band[CH_MAX_2G_CHANNEL]={0}, a_band1[4]={0}, a_band4[5]={0};
++	s32 cen_ch, distance, distance_2g, distance_5g, ch, min_ap=999;
++	u8 valid_chan_list[sizeof(u32)*(WL_NUMCHANNELS + 1)];
++	wl_uint32_list_t *list;
++	int ret;
++	chanspec_t chanspec;
++	struct dhd_pub *dhd = dhd_get_pub(net);
++
++	memset(b_band, -1, sizeof(b_band));
++	memset(a_band1, -1, sizeof(a_band1));
++	memset(a_band4, -1, sizeof(a_band4));
++
++	memset(valid_chan_list, 0, sizeof(valid_chan_list));
++	list = (wl_uint32_list_t *)(void *) valid_chan_list;
++	list->count = htod32(WL_NUMCHANNELS);
++	ret = wl_ext_ioctl(net, WLC_GET_VALID_CHANNELS, &valid_chan_list,
++		sizeof(valid_chan_list), 0);
++	if (ret<0) {
++		AEXT_ERROR(net->name, "get channels failed with %d\n", ret);
++		return 0;
++	} else {
++		for (i = 0; i < dtoh32(list->count); i++) {
++			ch = dtoh32(list->element[i]);
++			if (!dhd_conf_match_channel(dhd, ch))
++				continue;
++			if (ch < CH_MAX_2G_CHANNEL)
++				b_band[ch-1] = 0;
++			else if (ch <= 48)
++				a_band1[(ch-36)/4] = 0;
++			else if (ch >= 149 && ch <= 161)
++				a_band4[(ch-149)/4] = 0;
++		}
++	}
++
++	distance_2g = wl_ext_get_distance(net, WLC_BAND_2G);
++	distance_5g = wl_ext_get_distance(net, WLC_BAND_5G);
++
++#if defined(BSSCACHE)
++	node = bss_cache_ctrl->m_cache_head;
++	for (i=0; node && i<256; i++)
++#else
++	for (i=0; i < bss_list->count; i++)
++#endif /* BSSCACHE */
++	{
++#if defined(BSSCACHE)
++		bi = node->results.bss_info;
++#else
++		bi = bi ? (wl_bss_info_t *)((uintptr)bi + dtoh32(bi->length)) : bss_list->bss_info;
++#endif /* BSSCACHE */
++		chanspec = wl_ext_chspec_driver_to_host(ioctl_ver, bi->chanspec);
++		cen_ch = CHSPEC_CHANNEL(bi->chanspec);
++		distance = 0;
++		if (CHSPEC_IS20(chanspec))
++			distance += 2;
++		else if (CHSPEC_IS40(chanspec))
++			distance += 4;
++		else if (CHSPEC_IS80(chanspec))
++			distance += 8;
++		else
++			distance += 16;
++
++		if (CHSPEC_IS2G(chanspec)) {
++			distance += distance_2g;
++			for (j=0; j<ARRAYSIZE(b_band); j++) {
++				if (b_band[j] >= 0 && abs(cen_ch-(1+j)) <= distance)
++					b_band[j] += 1;
++			}
++		} else {
++			distance += distance_5g;
++			if (cen_ch <= 48) {
++				for (j=0; j<ARRAYSIZE(a_band1); j++) {
++					if (a_band1[j] >= 0 && abs(cen_ch-(36+j*4)) <= distance)
++						a_band1[j] += 1;
++				}
++			} else if (cen_ch >= 149) {
++				for (j=0; j<ARRAYSIZE(a_band4); j++) {
++					if (a_band4[j] >= 0 && abs(cen_ch-(149+j*4)) <= distance)
++						a_band4[j] += 1;
++				}
++			}
++		}
++#if defined(BSSCACHE)
++		node = node->next;
++#endif /* BSSCACHE */
++	}
++
++	*best_2g_ch = 0;
++	min_ap = 999;
++	for (i=0; i<CH_MAX_2G_CHANNEL; i++) {
++		if(b_band[i] < min_ap && b_band[i] >= 0) {
++			min_ap = b_band[i];
++			*best_2g_ch = i+1;
++		}
++	}
++	*best_5g_ch = 0;
++	min_ap = 999;
++	for (i=0; i<ARRAYSIZE(a_band1); i++) {
++		if(a_band1[i] < min_ap && a_band1[i] >= 0) {
++			min_ap = a_band1[i];
++			*best_5g_ch = i*4 + 36;
++		}
++	}
++	for (i=0; i<ARRAYSIZE(a_band4); i++) {
++		if(a_band4[i] < min_ap && a_band4[i] >= 0) {
++			min_ap = a_band4[i];
++			*best_5g_ch = i*4 + 149;
++		}
++	}
++
++	if (android_msg_level & ANDROID_INFO_LEVEL) {
++		struct bcmstrbuf strbuf;
++		char *tmp_buf = NULL;
++		tmp_buf = kmalloc(WLC_IOCTL_SMLEN, GFP_KERNEL);
++		if (tmp_buf == NULL) {
++			AEXT_ERROR(net->name, "Failed to allocate buffer of %d bytes\n", WLC_IOCTL_SMLEN);
++			goto exit;
++		}
++		bcm_binit(&strbuf, tmp_buf, WLC_IOCTL_SMLEN);
++		for (j=0; j<ARRAYSIZE(b_band); j++)
++			bcm_bprintf(&strbuf, "%d/%d, ", b_band[j], 1+j);
++		bcm_bprintf(&strbuf, "\n");
++		for (j=0; j<ARRAYSIZE(a_band1); j++)
++			bcm_bprintf(&strbuf, "%d/%d, ", a_band1[j], 36+j*4);
++		bcm_bprintf(&strbuf, "\n");
++		for (j=0; j<ARRAYSIZE(a_band4); j++)
++			bcm_bprintf(&strbuf, "%d/%d, ", a_band4[j], 149+j*4);
++		bcm_bprintf(&strbuf, "\n");
++		bcm_bprintf(&strbuf, "best_2g_ch=%d, best_5g_ch=%d\n",
++			*best_2g_ch, *best_5g_ch);
++		AEXT_INFO(net->name, "\n%s", strbuf.origbuf);
++		if (tmp_buf) {
++			kfree(tmp_buf);
++		}
++	}
++
++exit:
++	return 0;
++}
++#endif /* WL_CFG80211 || WL_ESCAN */
++
++#ifdef WL_CFG80211
++#define APCS_MAX_RETRY		10
++static int
++wl_ext_fw_apcs(struct net_device *dev, uint32 band)
++{
++	int channel = 0, chosen = 0, retry = 0, ret = 0, spect = 0;
++	u8 *reqbuf = NULL;
++	uint32 buf_size;
++
++	ret = wldev_ioctl_get(dev, WLC_GET_SPECT_MANAGMENT, &spect, sizeof(spect));
++	if (ret) {
++		AEXT_ERROR(dev->name, "ACS: error getting the spect, ret=%d\n", ret);
++		goto done;
++	}
++
++	if (spect > 0) {
++		ret = wl_cfg80211_set_spect(dev, 0);
++		if (ret < 0) {
++			AEXT_ERROR(dev->name, "ACS: error while setting spect, ret=%d\n", ret);
++			goto done;
++		}
++	}
++
++	reqbuf = kmalloc(CHANSPEC_BUF_SIZE, GFP_KERNEL);
++	if (reqbuf == NULL) {
++		AEXT_ERROR(dev->name, "failed to allocate chanspec buffer\n");
++		goto done;
++	}
++	memset(reqbuf, 0, CHANSPEC_BUF_SIZE);
++
++	if (band == WLC_BAND_AUTO) {
++		AEXT_INFO(dev->name, "ACS full channel scan \n");
++		reqbuf[0] = htod32(0);
++	} else if (band == WLC_BAND_5G) {
++		AEXT_INFO(dev->name, "ACS 5G band scan \n");
++		if ((ret = wl_cfg80211_get_chanspecs_5g(dev, reqbuf, CHANSPEC_BUF_SIZE)) < 0) {
++			AEXT_ERROR(dev->name, "ACS 5g chanspec retreival failed! \n");
++			goto done;
++		}
++	} else if (band == WLC_BAND_2G) {
++		/*
++		 * If channel argument is not provided/ argument 20 is provided,
++		 * Restrict channel to 2GHz, 20MHz BW, No SB
++		 */
++		AEXT_INFO(dev->name, "ACS 2G band scan \n");
++		if ((ret = wl_cfg80211_get_chanspecs_2g(dev, reqbuf, CHANSPEC_BUF_SIZE)) < 0) {
++			AEXT_ERROR(dev->name, "ACS 2g chanspec retreival failed! \n");
++			goto done;
++		}
++	} else {
++		AEXT_ERROR(dev->name, "ACS: No band chosen\n");
++		goto done;
++	}
++
++	buf_size = (band == WLC_BAND_AUTO) ? sizeof(int) : CHANSPEC_BUF_SIZE;
++	ret = wldev_ioctl_set(dev, WLC_START_CHANNEL_SEL, (void *)reqbuf,
++		buf_size);
++	if (ret < 0) {
++		AEXT_ERROR(dev->name, "can't start auto channel scan, err = %d\n", ret);
++		channel = 0;
++		goto done;
++	}
++
++	/* Wait for auto channel selection, max 3000 ms */
++	if ((band == WLC_BAND_2G) || (band == WLC_BAND_5G)) {
++		OSL_SLEEP(500);
++	} else {
++		/*
++		 * Full channel scan at the minimum takes 1.2secs
++		 * even with parallel scan. max wait time: 3500ms
++		 */
++		OSL_SLEEP(1000);
++	}
++
++	retry = APCS_MAX_RETRY;
++	while (retry--) {
++		ret = wldev_ioctl_get(dev, WLC_GET_CHANNEL_SEL, &chosen,
++			sizeof(chosen));
++		if (ret < 0) {
++			chosen = 0;
++		} else {
++			chosen = dtoh32(chosen);
++		}
++
++		if (chosen) {
++			int chosen_band;
++			int apcs_band;
++#ifdef D11AC_IOTYPES
++			if (wl_cfg80211_get_ioctl_version() == 1) {
++				channel = LCHSPEC_CHANNEL((chanspec_t)chosen);
++			} else {
++				channel = CHSPEC_CHANNEL((chanspec_t)chosen);
++			}
++#else
++			channel = CHSPEC_CHANNEL((chanspec_t)chosen);
++#endif /* D11AC_IOTYPES */
++			apcs_band = (band == WLC_BAND_AUTO) ? WLC_BAND_2G : band;
++			chosen_band = (channel <= CH_MAX_2G_CHANNEL) ? WLC_BAND_2G : WLC_BAND_5G;
++			if (apcs_band == chosen_band) {
++				WL_MSG(dev->name, "selected channel = %d\n", channel);
++				break;
++			}
++		}
++		AEXT_INFO(dev->name, "%d tried, ret = %d, chosen = 0x%x\n",
++			(APCS_MAX_RETRY - retry), ret, chosen);
++		OSL_SLEEP(250);
++	}
++
++done:
++	if (spect > 0) {
++		if ((ret = wl_cfg80211_set_spect(dev, spect) < 0)) {
++			AEXT_ERROR(dev->name, "ACS: error while setting spect\n");
++		}
++	}
++
++	if (reqbuf) {
++		kfree(reqbuf);
++	}
++
++	return channel;
++}
++#endif /* WL_CFG80211 */
++
++#ifdef WL_ESCAN
++int
++wl_ext_drv_apcs(struct net_device *dev, uint32 band)
++{
++	int ret = 0, channel = 0;
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	struct wl_escan_info *escan = NULL;
++	int retry = 0, retry_max, retry_interval = 250, up = 1;
++#ifdef WL_CFG80211
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++#endif /* WL_CFG80211 */
++
++	escan = dhd->escan;
++	if (dhd) {
++		retry_max = WL_ESCAN_TIMER_INTERVAL_MS/retry_interval;
++		ret = wldev_ioctl_get(dev, WLC_GET_UP, &up, sizeof(s32));
++		if (ret < 0 || up == 0) {
++			ret = wldev_ioctl_set(dev, WLC_UP, &up, sizeof(s32));
++		}
++		retry = retry_max;
++		while (retry--) {
++			if (escan->escan_state == ESCAN_STATE_SCANING
++#ifdef WL_CFG80211
++				|| wl_get_drv_status_all(cfg, SCANNING)
++#endif
++			)
++			{
++				AEXT_INFO(dev->name, "Scanning %d tried, ret = %d\n",
++					(retry_max - retry), ret);
++			} else {
++				escan->autochannel = 1;
++				ret = wl_escan_set_scan(dev, dhd, NULL, 0, TRUE);
++				if (!ret)
++					break;
++			}
++			OSL_SLEEP(retry_interval);
++		}
++		if ((retry == 0) || (ret < 0))
++			goto done;
++		retry = retry_max;
++		while (retry--) {
++			if (escan->escan_state == ESCAN_STATE_IDLE) {
++				if (band == WLC_BAND_5G)
++					channel = escan->best_5g_ch;
++				else
++					channel = escan->best_2g_ch;
++				WL_MSG(dev->name, "selected channel = %d\n", channel);
++				goto done;
++			}
++			AEXT_INFO(dev->name, "escan_state=%d, %d tried, ret = %d\n",
++				escan->escan_state, (retry_max - retry), ret);
++			OSL_SLEEP(retry_interval);
++		}
++		if ((retry == 0) || (ret < 0))
++			goto done;
++	}
++
++done:
++	if (escan)
++		escan->autochannel = 0;
++
++	return channel;
++}
++#endif /* WL_ESCAN */
++
++int
++wl_ext_autochannel(struct net_device *dev, uint acs, uint32 band)
++{
++	int channel = 0;
++	uint16 chan_2g, chan_5g;
++
++	AEXT_INFO(dev->name, "acs=0x%x, band=%d \n", acs, band);
++
++#ifdef WL_CFG80211
++	if (acs & ACS_FW_BIT) {
++		int ret = 0;
++		ret = wldev_ioctl_get(dev, WLC_GET_CHANNEL_SEL, &channel, sizeof(channel));
++		channel = 0;
++		if (ret != BCME_UNSUPPORTED)
++			channel = wl_ext_fw_apcs(dev, band);
++		if (channel)
++			return channel;
++	}
++#endif
++
++#ifdef WL_ESCAN
++	if (acs & ACS_DRV_BIT)
++		channel = wl_ext_drv_apcs(dev, band);
++#endif /* WL_ESCAN */
++
++	if (channel == 0) {
++		wl_ext_get_default_chan(dev, &chan_2g, &chan_5g, TRUE);
++		if (band == WLC_BAND_5G) {
++			channel = chan_5g;
++		} else {
++			channel = chan_2g;
++		}
++		AEXT_ERROR(dev->name, "ACS failed. Fall back to default channel (%d) \n", channel);
++	}
++
++	return channel;
++}
++
++#if defined(RSSIAVG)
++void
++wl_free_rssi_cache(wl_rssi_cache_ctrl_t *rssi_cache_ctrl)
++{
++	wl_rssi_cache_t *node, *cur, **rssi_head;
++	int i=0;
++
++	rssi_head = &rssi_cache_ctrl->m_cache_head;
++	node = *rssi_head;
++
++	for (;node;) {
++		AEXT_INFO("wlan", "Free %d with BSSID %pM\n", i, &node->BSSID);
++		cur = node;
++		node = cur->next;
++		kfree(cur);
++		i++;
++	}
++	*rssi_head = NULL;
++}
++
++void
++wl_delete_dirty_rssi_cache(wl_rssi_cache_ctrl_t *rssi_cache_ctrl)
++{
++	wl_rssi_cache_t *node, *prev, **rssi_head;
++	int i = -1, tmp = 0;
++	struct osl_timespec now;
++
++	osl_do_gettimeofday(&now);
++
++	rssi_head = &rssi_cache_ctrl->m_cache_head;
++	node = *rssi_head;
++	prev = node;
++	for (;node;) {
++		i++;
++		if (now.tv_sec > node->tv.tv_sec) {
++			if (node == *rssi_head) {
++				tmp = 1;
++				*rssi_head = node->next;
++			} else {
++				tmp = 0;
++				prev->next = node->next;
++			}
++			AEXT_INFO("wlan", "Del %d with BSSID %pM\n", i, &node->BSSID);
++			kfree(node);
++			if (tmp == 1) {
++				node = *rssi_head;
++				prev = node;
++			} else {
++				node = prev->next;
++			}
++			continue;
++		}
++		prev = node;
++		node = node->next;
++	}
++}
++
++void
++wl_delete_disconnected_rssi_cache(wl_rssi_cache_ctrl_t *rssi_cache_ctrl,
++	u8 *bssid)
++{
++	wl_rssi_cache_t *node, *prev, **rssi_head;
++	int i = -1, tmp = 0;
++
++	rssi_head = &rssi_cache_ctrl->m_cache_head;
++	node = *rssi_head;
++	prev = node;
++	for (;node;) {
++		i++;
++		if (!memcmp(&node->BSSID, bssid, ETHER_ADDR_LEN)) {
++			if (node == *rssi_head) {
++				tmp = 1;
++				*rssi_head = node->next;
++			} else {
++				tmp = 0;
++				prev->next = node->next;
++			}
++			AEXT_INFO("wlan", "Del %d with BSSID %pM\n", i, &node->BSSID);
++			kfree(node);
++			if (tmp == 1) {
++				node = *rssi_head;
++				prev = node;
++			} else {
++				node = prev->next;
++			}
++			continue;
++		}
++		prev = node;
++		node = node->next;
++	}
++}
++
++void
++wl_reset_rssi_cache(wl_rssi_cache_ctrl_t *rssi_cache_ctrl)
++{
++	wl_rssi_cache_t *node, **rssi_head;
++
++	rssi_head = &rssi_cache_ctrl->m_cache_head;
++
++	/* reset dirty */
++	node = *rssi_head;
++	for (;node;) {
++		node->dirty += 1;
++		node = node->next;
++	}
++}
++
++int
++wl_update_connected_rssi_cache(struct net_device *net,
++	wl_rssi_cache_ctrl_t *rssi_cache_ctrl, int *rssi_avg)
++{
++	wl_rssi_cache_t *node, *prev, *leaf, **rssi_head;
++	int j, k=0;
++	int rssi, error=0;
++	struct ether_addr bssid;
++	struct osl_timespec now, timeout;
++	scb_val_t scbval;
++
++	if (!g_wifi_on)
++		return 0;
++
++	error = wldev_ioctl(net, WLC_GET_BSSID, &bssid, sizeof(bssid), 0);
++	if (error == BCME_NOTASSOCIATED) {
++		AEXT_INFO("wlan", "Not Associated! res:%d\n", error);
++		return 0;
++	}
++	if (error) {
++		AEXT_ERROR(net->name, "Could not get bssid (%d)\n", error);
++	}
++	error = wldev_get_rssi(net, &scbval);
++	if (error) {
++		AEXT_ERROR(net->name, "Could not get rssi (%d)\n", error);
++		return error;
++	}
++	rssi = scbval.val;
++
++	osl_do_gettimeofday(&now);
++	timeout.tv_sec = now.tv_sec + RSSICACHE_TIMEOUT;
++	if (timeout.tv_sec < now.tv_sec) {
++		/*
++		 * Integer overflow - assume long enough timeout to be assumed
++		 * to be infinite, i.e., the timeout would never happen.
++		 */
++		AEXT_TRACE(net->name,
++			"Too long timeout (secs=%d) to ever happen - now=%lu, timeout=%lu\n",
++			RSSICACHE_TIMEOUT, now.tv_sec, timeout.tv_sec);
++	}
++
++	/* update RSSI */
++	rssi_head = &rssi_cache_ctrl->m_cache_head;
++	node = *rssi_head;
++	prev = NULL;
++	for (;node;) {
++		if (!memcmp(&node->BSSID, &bssid, ETHER_ADDR_LEN)) {
++			AEXT_INFO("wlan", "Update %d with BSSID %pM, RSSI=%d\n", k, &bssid, rssi);
++			for (j=0; j<RSSIAVG_LEN-1; j++)
++				node->RSSI[j] = node->RSSI[j+1];
++			node->RSSI[j] = rssi;
++			node->dirty = 0;
++			node->tv = timeout;
++			goto exit;
++		}
++		prev = node;
++		node = node->next;
++		k++;
++	}
++
++	leaf = kmalloc(sizeof(wl_rssi_cache_t), GFP_KERNEL);
++	if (!leaf) {
++		AEXT_ERROR(net->name, "Memory alloc failure %d\n", (int)sizeof(wl_rssi_cache_t));
++		return 0;
++	}
++	AEXT_INFO(net->name, "Add %d with cached BSSID %pM, RSSI=%3d in the leaf\n",
++		k, &bssid, rssi);
++
++	leaf->next = NULL;
++	leaf->dirty = 0;
++	leaf->tv = timeout;
++	memcpy(&leaf->BSSID, &bssid, ETHER_ADDR_LEN);
++	for (j=0; j<RSSIAVG_LEN; j++)
++		leaf->RSSI[j] = rssi;
++
++	if (!prev)
++		*rssi_head = leaf;
++	else
++		prev->next = leaf;
++
++exit:
++	*rssi_avg = (int)wl_get_avg_rssi(rssi_cache_ctrl, &bssid);
++
++	return error;
++}
++
++void
++wl_update_rssi_cache(wl_rssi_cache_ctrl_t *rssi_cache_ctrl,
++	wl_scan_results_t *ss_list)
++{
++	wl_rssi_cache_t *node, *prev, *leaf, **rssi_head;
++	wl_bss_info_t *bi = NULL;
++	int i, j, k;
++	struct osl_timespec now, timeout;
++
++	if (!ss_list->count)
++		return;
++
++	osl_do_gettimeofday(&now);
++	timeout.tv_sec = now.tv_sec + RSSICACHE_TIMEOUT;
++	if (timeout.tv_sec < now.tv_sec) {
++		/*
++		 * Integer overflow - assume long enough timeout to be assumed
++		 * to be infinite, i.e., the timeout would never happen.
++		 */
++		AEXT_TRACE("wlan",
++			"Too long timeout (secs=%d) to ever happen - now=%lu, timeout=%lu\n",
++			RSSICACHE_TIMEOUT, now.tv_sec, timeout.tv_sec);
++	}
++
++	rssi_head = &rssi_cache_ctrl->m_cache_head;
++
++	/* update RSSI */
++	for (i = 0; i < ss_list->count; i++) {
++		node = *rssi_head;
++		prev = NULL;
++		k = 0;
++		bi = bi ? (wl_bss_info_t *)((uintptr)bi + dtoh32(bi->length)) : ss_list->bss_info;
++		for (;node;) {
++			if (!memcmp(&node->BSSID, &bi->BSSID, ETHER_ADDR_LEN)) {
++				AEXT_INFO("wlan", "Update %d with BSSID %pM, RSSI=%3d, SSID \"%s\"\n",
++					k, &bi->BSSID, dtoh16(bi->RSSI), bi->SSID);
++				for (j=0; j<RSSIAVG_LEN-1; j++)
++					node->RSSI[j] = node->RSSI[j+1];
++				node->RSSI[j] = dtoh16(bi->RSSI);
++				node->dirty = 0;
++				node->tv = timeout;
++				break;
++			}
++			prev = node;
++			node = node->next;
++			k++;
++		}
++
++		if (node)
++			continue;
++
++		leaf = kmalloc(sizeof(wl_rssi_cache_t), GFP_KERNEL);
++		if (!leaf) {
++			AEXT_ERROR("wlan", "Memory alloc failure %d\n",
++				(int)sizeof(wl_rssi_cache_t));
++			return;
++		}
++		AEXT_INFO("wlan", "Add %d with cached BSSID %pM, RSSI=%3d, SSID \"%s\" in the leaf\n",
++			k, &bi->BSSID, dtoh16(bi->RSSI), bi->SSID);
++
++		leaf->next = NULL;
++		leaf->dirty = 0;
++		leaf->tv = timeout;
++		memcpy(&leaf->BSSID, &bi->BSSID, ETHER_ADDR_LEN);
++		for (j=0; j<RSSIAVG_LEN; j++)
++			leaf->RSSI[j] = dtoh16(bi->RSSI);
++
++		if (!prev)
++			*rssi_head = leaf;
++		else
++			prev->next = leaf;
++	}
++}
++
++int16
++wl_get_avg_rssi(wl_rssi_cache_ctrl_t *rssi_cache_ctrl, void *addr)
++{
++	wl_rssi_cache_t *node, **rssi_head;
++	int j, rssi_sum, rssi=RSSI_MINVAL;
++
++	rssi_head = &rssi_cache_ctrl->m_cache_head;
++
++	node = *rssi_head;
++	for (;node;) {
++		if (!memcmp(&node->BSSID, addr, ETHER_ADDR_LEN)) {
++			rssi_sum = 0;
++			rssi = 0;
++			for (j=0; j<RSSIAVG_LEN; j++)
++				rssi_sum += node->RSSI[RSSIAVG_LEN-j-1];
++			rssi = rssi_sum / j;
++			break;
++		}
++		node = node->next;
++	}
++	rssi = MIN(rssi, RSSI_MAXVAL);
++	if (rssi == RSSI_MINVAL) {
++		AEXT_ERROR("wlan", "BSSID %pM does not in RSSI cache\n", addr);
++	}
++	return (int16)rssi;
++}
++#endif /* RSSIAVG */
++
++#if defined(RSSIOFFSET)
++int
++wl_update_rssi_offset(struct net_device *net, int rssi)
++{
++#if defined(RSSIOFFSET_NEW)
++	int j;
++#endif /* RSSIOFFSET_NEW */
++
++	if (!g_wifi_on)
++		return rssi;
++
++#if defined(RSSIOFFSET_NEW)
++	for (j=0; j<RSSI_OFFSET; j++) {
++		if (rssi - (RSSI_OFFSET_MINVAL+RSSI_OFFSET_INTVAL*(j+1)) < 0)
++			break;
++	}
++	rssi += j;
++#else
++	rssi += RSSI_OFFSET;
++#endif /* RSSIOFFSET_NEW */
++	return MIN(rssi, RSSI_MAXVAL);
++}
++#endif /* RSSIOFFSET */
++
++#if defined(BSSCACHE)
++void
++wl_free_bss_cache(wl_bss_cache_ctrl_t *bss_cache_ctrl)
++{
++	wl_bss_cache_t *node, *cur, **bss_head;
++	int i=0;
++
++	AEXT_TRACE("wlan", "called\n");
++
++	bss_head = &bss_cache_ctrl->m_cache_head;
++	node = *bss_head;
++
++	for (;node;) {
++		AEXT_TRACE("wlan", "Free %d with BSSID %pM\n",
++			i, &node->results.bss_info->BSSID);
++		cur = node;
++		node = cur->next;
++		kfree(cur);
++		i++;
++	}
++	*bss_head = NULL;
++}
++
++void
++wl_delete_dirty_bss_cache(wl_bss_cache_ctrl_t *bss_cache_ctrl)
++{
++	wl_bss_cache_t *node, *prev, **bss_head;
++	int i = -1, tmp = 0;
++	struct osl_timespec now;
++
++	osl_do_gettimeofday(&now);
++
++	bss_head = &bss_cache_ctrl->m_cache_head;
++	node = *bss_head;
++	prev = node;
++	for (;node;) {
++		i++;
++		if (now.tv_sec > node->tv.tv_sec) {
++			if (node == *bss_head) {
++				tmp = 1;
++				*bss_head = node->next;
++			} else {
++				tmp = 0;
++				prev->next = node->next;
++			}
++			AEXT_TRACE("wlan", "Del %d with BSSID %pM, RSSI=%3d, SSID \"%s\"\n",
++				i, &node->results.bss_info->BSSID,
++				dtoh16(node->results.bss_info->RSSI), node->results.bss_info->SSID);
++			kfree(node);
++			if (tmp == 1) {
++				node = *bss_head;
++				prev = node;
++			} else {
++				node = prev->next;
++			}
++			continue;
++		}
++		prev = node;
++		node = node->next;
++	}
++}
++
++void
++wl_delete_disconnected_bss_cache(wl_bss_cache_ctrl_t *bss_cache_ctrl,
++	u8 *bssid)
++{
++	wl_bss_cache_t *node, *prev, **bss_head;
++	int i = -1, tmp = 0;
++
++	bss_head = &bss_cache_ctrl->m_cache_head;
++	node = *bss_head;
++	prev = node;
++	for (;node;) {
++		i++;
++		if (!memcmp(&node->results.bss_info->BSSID, bssid, ETHER_ADDR_LEN)) {
++			if (node == *bss_head) {
++				tmp = 1;
++				*bss_head = node->next;
++			} else {
++				tmp = 0;
++				prev->next = node->next;
++			}
++			AEXT_TRACE("wlan", "Del %d with BSSID %pM, RSSI=%3d, SSID \"%s\"\n",
++				i, &node->results.bss_info->BSSID,
++				dtoh16(node->results.bss_info->RSSI), node->results.bss_info->SSID);
++			kfree(node);
++			if (tmp == 1) {
++				node = *bss_head;
++				prev = node;
++			} else {
++				node = prev->next;
++			}
++			continue;
++		}
++		prev = node;
++		node = node->next;
++	}
++}
++
++void
++wl_reset_bss_cache(wl_bss_cache_ctrl_t *bss_cache_ctrl)
++{
++	wl_bss_cache_t *node, **bss_head;
++
++	bss_head = &bss_cache_ctrl->m_cache_head;
++
++	/* reset dirty */
++	node = *bss_head;
++	for (;node;) {
++		node->dirty += 1;
++		node = node->next;
++	}
++}
++
++void dump_bss_cache(
++#if defined(RSSIAVG)
++	wl_rssi_cache_ctrl_t *rssi_cache_ctrl,
++#endif /* RSSIAVG */
++	wl_bss_cache_t *node)
++{
++	int k = 0;
++	int16 rssi;
++
++	for (;node;) {
++#if defined(RSSIAVG)
++		rssi = wl_get_avg_rssi(rssi_cache_ctrl, &node->results.bss_info->BSSID);
++#else
++		rssi = dtoh16(node->results.bss_info->RSSI);
++#endif /* RSSIAVG */
++		AEXT_TRACE("wlan", "dump %d with cached BSSID %pM, RSSI=%3d, SSID \"%s\"\n",
++			k, &node->results.bss_info->BSSID, rssi, node->results.bss_info->SSID);
++		k++;
++		node = node->next;
++	}
++}
++
++void
++wl_update_bss_cache(wl_bss_cache_ctrl_t *bss_cache_ctrl,
++#if defined(RSSIAVG)
++	wl_rssi_cache_ctrl_t *rssi_cache_ctrl,
++#endif /* RSSIAVG */
++	wl_scan_results_t *ss_list)
++{
++	wl_bss_cache_t *node, *prev, *leaf, **bss_head;
++	wl_bss_info_t *bi = NULL;
++	int i, k=0;
++#if defined(SORT_BSS_BY_RSSI)
++	int16 rssi, rssi_node;
++#endif /* SORT_BSS_BY_RSSI */
++	struct osl_timespec now, timeout;
++
++	if (!ss_list->count)
++		return;
++
++	osl_do_gettimeofday(&now);
++	timeout.tv_sec = now.tv_sec + BSSCACHE_TIMEOUT;
++	if (timeout.tv_sec < now.tv_sec) {
++		/*
++		 * Integer overflow - assume long enough timeout to be assumed
++		 * to be infinite, i.e., the timeout would never happen.
++		 */
++		AEXT_TRACE("wlan",
++			"Too long timeout (secs=%d) to ever happen - now=%lu, timeout=%lu\n",
++			BSSCACHE_TIMEOUT, now.tv_sec, timeout.tv_sec);
++	}
++
++	bss_head = &bss_cache_ctrl->m_cache_head;
++
++	for (i=0; i < ss_list->count; i++) {
++		node = *bss_head;
++		prev = NULL;
++		bi = bi ? (wl_bss_info_t *)((uintptr)bi + dtoh32(bi->length)) : ss_list->bss_info;
++
++		for (;node;) {
++			if (!memcmp(&node->results.bss_info->BSSID, &bi->BSSID, ETHER_ADDR_LEN)) {
++				if (node == *bss_head)
++					*bss_head = node->next;
++				else {
++					prev->next = node->next;
++				}
++				break;
++			}
++			prev = node;
++			node = node->next;
++		}
++
++		leaf = kmalloc(dtoh32(bi->length) + sizeof(wl_bss_cache_t), GFP_KERNEL);
++		if (!leaf) {
++			AEXT_ERROR("wlan", "Memory alloc failure %d\n",
++				dtoh32(bi->length) + (int)sizeof(wl_bss_cache_t));
++			return;
++		}
++		if (node) {
++			kfree(node);
++			node = NULL;
++			AEXT_TRACE("wlan",
++				"Update %d with cached BSSID %pM, RSSI=%3d, SSID \"%s\"\n",
++				k, &bi->BSSID, dtoh16(bi->RSSI), bi->SSID);
++		} else
++			AEXT_TRACE("wlan",
++				"Add %d with cached BSSID %pM, RSSI=%3d, SSID \"%s\"\n",
++				k, &bi->BSSID, dtoh16(bi->RSSI), bi->SSID);
++
++		memcpy(leaf->results.bss_info, bi, dtoh32(bi->length));
++		leaf->next = NULL;
++		leaf->dirty = 0;
++		leaf->tv = timeout;
++		leaf->results.count = 1;
++		leaf->results.version = ss_list->version;
++		k++;
++
++		if (*bss_head == NULL)
++			*bss_head = leaf;
++		else {
++#if defined(SORT_BSS_BY_RSSI)
++			node = *bss_head;
++#if defined(RSSIAVG)
++			rssi = wl_get_avg_rssi(rssi_cache_ctrl, &leaf->results.bss_info->BSSID);
++#else
++			rssi = dtoh16(leaf->results.bss_info->RSSI);
++#endif /* RSSIAVG */
++			for (;node;) {
++#if defined(RSSIAVG)
++				rssi_node = wl_get_avg_rssi(rssi_cache_ctrl,
++					&node->results.bss_info->BSSID);
++#else
++				rssi_node = dtoh16(node->results.bss_info->RSSI);
++#endif /* RSSIAVG */
++				if (rssi > rssi_node) {
++					leaf->next = node;
++					if (node == *bss_head)
++						*bss_head = leaf;
++					else
++						prev->next = leaf;
++					break;
++				}
++				prev = node;
++				node = node->next;
++			}
++			if (node == NULL)
++				prev->next = leaf;
++#else
++			leaf->next = *bss_head;
++			*bss_head = leaf;
++#endif /* SORT_BSS_BY_RSSI */
++		}
++	}
++	dump_bss_cache(
++#if defined(RSSIAVG)
++		rssi_cache_ctrl,
++#endif /* RSSIAVG */
++		*bss_head);
++}
++
++void
++wl_release_bss_cache_ctrl(wl_bss_cache_ctrl_t *bss_cache_ctrl)
++{
++	AEXT_TRACE("wlan", "Enter\n");
++	wl_free_bss_cache(bss_cache_ctrl);
++}
++#endif /* BSSCACHE */
++
++
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_cfg80211.c b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfg80211.c
+new file mode 100644
+index 000000000..8296fd846
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfg80211.c
+@@ -0,0 +1,22544 @@
++/*
++ * Linux cfg80211 driver
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfg80211.c 711110 2017-07-17 04:38:25Z $
++ */
++/* */
++#include <typedefs.h>
++#include <linuxver.h>
++#include <osl.h>
++#include <linux/kernel.h>
++
++#include <wlc_types.h>
++#include <bcmutils.h>
++#include <bcmwifi_channels.h>
++#include <bcmendian.h>
++#include <ethernet.h>
++#include <802.11.h>
++#include <linux/if_arp.h>
++#include <asm/uaccess.h>
++
++#include <ethernet.h>
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/netdevice.h>
++#include <linux/sched.h>
++#include <linux/etherdevice.h>
++#include <linux/wireless.h>
++#include <linux/ieee80211.h>
++#include <linux/wait.h>
++#include <net/cfg80211.h>
++#include <net/rtnetlink.h>
++
++#include <wlioctl.h>
++#include <wldev_common.h>
++#include <wl_cfg80211.h>
++#include <wl_cfgp2p.h>
++#include <bcmdevs.h>
++#include <wl_android.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_linux.h>
++#include <dhd_debug.h>
++#include <dhdioctl.h>
++#include <wlioctl.h>
++#include <dhd_cfg80211.h>
++#include <dhd_bus.h>
++#ifdef PNO_SUPPORT
++#include <dhd_pno.h>
++#endif /* PNO_SUPPORT */
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) || defined(WL_VENDOR_EXT_SUPPORT)
++#include <wl_cfgvendor.h>
++#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) || defined(WL_VENDOR_EXT_SUPPORT) */
++
++#if !defined(WL_VENDOR_EXT_SUPPORT)
++#undef GSCAN_SUPPORT
++#endif
++
++#if defined(STAT_REPORT)
++#include <wl_statreport.h>
++#endif /* STAT_REPORT */
++#include <dhd_config.h>
++
++
++#ifdef PROP_TXSTATUS
++#include <dhd_wlfc.h>
++#endif
++
++#ifdef BCMPCIE
++#include <dhd_flowring.h>
++#endif
++#ifdef RTT_SUPPORT
++#include <dhd_rtt.h>
++#endif /* RTT_SUPPORT */
++
++#define BRCM_SAE_VENDOR_EVENT_BUF_LEN 500
++
++#ifdef WL11U
++#endif /* WL11U */
++
++#ifndef DHD_UNSUPPORT_IF_CNTS
++#define DHD_SUPPORT_IF_CNTS
++#endif /* !DHD_UN_SUPPORT_IF_CNTS */
++
++#ifdef BCMWAPI_WPI
++/* these items should evetually go into wireless.h of the linux system headfile dir */
++#ifndef IW_ENCODE_ALG_SM4
++#define IW_ENCODE_ALG_SM4 0x20
++#endif
++
++#ifndef IW_AUTH_WAPI_ENABLED
++#define IW_AUTH_WAPI_ENABLED 0x20
++#endif
++
++#ifndef IW_AUTH_WAPI_VERSION_1
++#define IW_AUTH_WAPI_VERSION_1  0x00000008
++#endif
++
++#ifndef IW_AUTH_CIPHER_SMS4
++#define IW_AUTH_CIPHER_SMS4     0x00000020
++#endif
++
++#ifndef IW_AUTH_KEY_MGMT_WAPI_PSK
++#define IW_AUTH_KEY_MGMT_WAPI_PSK 4
++#endif
++
++#ifndef IW_AUTH_KEY_MGMT_WAPI_CERT
++#define IW_AUTH_KEY_MGMT_WAPI_CERT 8
++#endif
++#endif /* BCMWAPI_WPI */
++
++#ifdef BCMWAPI_WPI
++#define IW_WSEC_ENABLED(wsec)   ((wsec) & (WEP_ENABLED | TKIP_ENABLED | AES_ENABLED | SMS4_ENABLED))
++#else /* BCMWAPI_WPI */
++#define IW_WSEC_ENABLED(wsec)   ((wsec) & (WEP_ENABLED | TKIP_ENABLED | AES_ENABLED))
++#endif /* BCMWAPI_WPI */
++
++static struct device *cfg80211_parent_dev = NULL;
++#ifdef CUSTOMER_HW4_DEBUG
++u32 wl_dbg_level = WL_DBG_ERR | WL_DBG_P2P_ACTION;
++#else
++u32 wl_dbg_level = WL_DBG_ERR;
++#endif /* CUSTOMER_HW4_DEBUG */
++
++#define MAX_WAIT_TIME 1500
++#ifdef WLAIBSS_MCHAN
++#define IBSS_IF_NAME "ibss%d"
++#endif /* WLAIBSS_MCHAN */
++
++#ifdef VSDB
++/* sleep time to keep STA's connecting or connection for continuous af tx or finding a peer */
++#define DEFAULT_SLEEP_TIME_VSDB		120
++#define OFF_CHAN_TIME_THRESHOLD_MS	200
++#define AF_RETRY_DELAY_TIME			40
++
++/* if sta is connected or connecting, sleep for a while before retry af tx or finding a peer */
++#define WL_AF_TX_KEEP_PRI_CONNECTION_VSDB(cfg)	\
++	do {	\
++		if (wl_get_drv_status(cfg, CONNECTED, bcmcfg_to_prmry_ndev(cfg)) ||	\
++			wl_get_drv_status(cfg, CONNECTING, bcmcfg_to_prmry_ndev(cfg))) {	\
++			OSL_SLEEP(DEFAULT_SLEEP_TIME_VSDB);			\
++		}	\
++	} while (0)
++#else /* VSDB */
++/* if not VSDB, do nothing */
++#define WL_AF_TX_KEEP_PRI_CONNECTION_VSDB(cfg)
++#endif /* VSDB */
++
++#ifdef WL_CFG80211_SYNC_GON
++#define WL_DRV_STATUS_SENDING_AF_FRM_EXT(cfg) \
++	(wl_get_drv_status_all(cfg, SENDING_ACT_FRM) || \
++		wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM_LISTEN))
++#else
++#define WL_DRV_STATUS_SENDING_AF_FRM_EXT(cfg) wl_get_drv_status_all(cfg, SENDING_ACT_FRM)
++#endif /* WL_CFG80211_SYNC_GON */
++
++#define DNGL_FUNC(func, parameters) func parameters
++#define COEX_DHCP
++
++#define WLAN_EID_SSID	0
++#define CH_MIN_5G_CHANNEL 34
++#define CH_MIN_2G_CHANNEL 1
++#define ACTIVE_SCAN 1
++#define PASSIVE_SCAN 0
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++#define BCM_SET_LIST_FIRST_ENTRY(entry, ptr, type, member) \
++_Pragma("GCC diagnostic push") \
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"") \
++(entry) = list_first_entry((ptr), type, member); \
++_Pragma("GCC diagnostic pop") \
++
++#define BCM_SET_CONTAINER_OF(entry, ptr, type, member) \
++_Pragma("GCC diagnostic push") \
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"") \
++entry = container_of((ptr), type, member); \
++_Pragma("GCC diagnostic pop") \
++
++#else
++#define BCM_SET_LIST_FIRST_ENTRY(entry, ptr, type, member) \
++(entry) = list_first_entry((ptr), type, member); \
++
++#define BCM_SET_CONTAINER_OF(entry, ptr, type, member) \
++entry = container_of((ptr), type, member); \
++
++#endif /* STRICT_GCC_WARNINGS */
++
++#ifdef WL_RELMCAST
++enum rmc_event_type {
++	RMC_EVENT_NONE,
++	RMC_EVENT_LEADER_CHECK_FAIL
++};
++#endif /* WL_RELMCAST */
++
++#ifdef WL_LASTEVT
++typedef struct wl_last_event {
++	uint32 current_time;		/* current tyime */
++	uint32 timestamp;		/* event timestamp */
++	wl_event_msg_t event;	/* Encapsulated event */
++} wl_last_event_t;
++#endif /* WL_LASTEVT */
++
++/* This is to override regulatory domains defined in cfg80211 module (reg.c)
++ * By default world regulatory domain defined in reg.c puts the flags NL80211_RRF_PASSIVE_SCAN
++ * and NL80211_RRF_NO_IBSS for 5GHz channels (for 36..48 and 149..165).
++ * With respect to these flags, wpa_supplicant doesn't start p2p operations on 5GHz channels.
++ * All the chnages in world regulatory domain are to be done here.
++ *
++ * this definition reuires disabling missing-field-initializer warning
++ * as the ieee80211_regdomain definition differs in plain linux and in Android
++ */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wmissing-field-initializers\"")
++#endif
++static const struct ieee80211_regdomain brcm_regdom = {
++	.n_reg_rules = 4,
++	.alpha2 =  "99",
++	.reg_rules = {
++		/* IEEE 802.11b/g, channels 1..11 */
++		REG_RULE(2412-10, 2472+10, 40, 6, 20, 0),
++		/* If any */
++		/* IEEE 802.11 channel 14 - Only JP enables
++		 * this and for 802.11b only
++		 */
++		REG_RULE(2484-10, 2484+10, 20, 6, 20, 0),
++		/* IEEE 802.11a, channel 36..64 */
++		REG_RULE(5150-10, 5350+10, 40, 6, 20, 0),
++		/* IEEE 802.11a, channel 100..165 */
++		REG_RULE(5470-10, 5850+10, 40, 6, 20, 0), }
++};
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) && \
++	(defined(WL_IFACE_COMB_NUM_CHANNELS) || defined(WL_CFG80211_P2P_DEV_IF))
++static const struct ieee80211_iface_limit common_if_limits[] = {
++	{
++	/*
++	 * Driver can support up to 2 AP's
++	 */
++	.max = 2,
++	.types = BIT(NL80211_IFTYPE_AP),
++	},
++	{
++	/*
++	 * During P2P-GO removal, P2P-GO is first changed to STA and later only
++	 * removed. So setting maximum possible number of STA interfaces according
++	 * to kernel version.
++	 *
++	 * less than linux-3.8 - max:3 (wlan0 + p2p0 + group removal of p2p-p2p0-x)
++	 * linux-3.8 and above - max:2 (wlan0 + group removal of p2p-wlan0-x)
++	 */
++#ifdef WL_ENABLE_P2P_IF
++	.max = 3,
++#else
++	.max = 2,
++#endif /* WL_ENABLE_P2P_IF */
++	.types = BIT(NL80211_IFTYPE_STATION),
++	},
++	{
++	.max = 2,
++	.types = BIT(NL80211_IFTYPE_P2P_GO) | BIT(NL80211_IFTYPE_P2P_CLIENT),
++	},
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	{
++	.max = 1,
++	.types = BIT(NL80211_IFTYPE_P2P_DEVICE),
++	},
++#endif /* WL_CFG80211_P2P_DEV_IF */
++	{
++	.max = 1,
++	.types = BIT(NL80211_IFTYPE_ADHOC),
++	},
++};
++#ifdef BCM4330_CHIP
++#define NUM_DIFF_CHANNELS 1
++#else
++#define NUM_DIFF_CHANNELS 2
++#endif
++static const struct ieee80211_iface_combination
++common_iface_combinations[] = {
++	{
++	.num_different_channels = NUM_DIFF_CHANNELS,
++	/*
++	 * max_interfaces = 4
++	 * The max no of interfaces will be used in dual p2p case.
++	 * {STA, P2P Device, P2P Group 1, P2P Group 2}. Though we
++	 * will not be using the STA functionality in this case, it
++	 * will remain registered as it is the primary interface.
++	 */
++	.max_interfaces = 4,
++	.limits = common_if_limits,
++	.n_limits = ARRAY_SIZE(common_if_limits),
++	},
++};
++#endif /* LINUX_VER >= 3.0 && (WL_IFACE_COMB_NUM_CHANNELS || WL_CFG80211_P2P_DEV_IF) */
++
++/* Data Element Definitions */
++#define WPS_ID_CONFIG_METHODS     0x1008
++#define WPS_ID_REQ_TYPE           0x103A
++#define WPS_ID_DEVICE_NAME        0x1011
++#define WPS_ID_VERSION            0x104A
++#define WPS_ID_DEVICE_PWD_ID      0x1012
++#define WPS_ID_REQ_DEV_TYPE       0x106A
++#define WPS_ID_SELECTED_REGISTRAR_CONFIG_METHODS 0x1053
++#define WPS_ID_PRIM_DEV_TYPE      0x1054
++
++/* Device Password ID */
++#define DEV_PW_DEFAULT 0x0000
++#define DEV_PW_USER_SPECIFIED 0x0001,
++#define DEV_PW_MACHINE_SPECIFIED 0x0002
++#define DEV_PW_REKEY 0x0003
++#define DEV_PW_PUSHBUTTON 0x0004
++#define DEV_PW_REGISTRAR_SPECIFIED 0x0005
++
++/* Config Methods */
++#define WPS_CONFIG_USBA 0x0001
++#define WPS_CONFIG_ETHERNET 0x0002
++#define WPS_CONFIG_LABEL 0x0004
++#define WPS_CONFIG_DISPLAY 0x0008
++#define WPS_CONFIG_EXT_NFC_TOKEN 0x0010
++#define WPS_CONFIG_INT_NFC_TOKEN 0x0020
++#define WPS_CONFIG_NFC_INTERFACE 0x0040
++#define WPS_CONFIG_PUSHBUTTON 0x0080
++#define WPS_CONFIG_KEYPAD 0x0100
++#define WPS_CONFIG_VIRT_PUSHBUTTON 0x0280
++#define WPS_CONFIG_PHY_PUSHBUTTON 0x0480
++#define WPS_CONFIG_VIRT_DISPLAY 0x2008
++#define WPS_CONFIG_PHY_DISPLAY 0x4008
++
++#define PM_BLOCK 1
++#define PM_ENABLE 0
++
++
++#define WL_AKM_SUITE_SHA256_1X  0x000FAC05
++#define WL_AKM_SUITE_SHA256_PSK 0x000FAC06
++
++#ifndef IBSS_COALESCE_ALLOWED
++#define IBSS_COALESCE_ALLOWED IBSS_COALESCE_DEFAULT
++#endif
++
++#ifndef IBSS_INITIAL_SCAN_ALLOWED
++#define IBSS_INITIAL_SCAN_ALLOWED IBSS_INITIAL_SCAN_ALLOWED_DEFAULT
++#endif
++
++#define CUSTOM_RETRY_MASK 0xff000000 /* Mask for retry counter of custom dwell time */
++#define LONG_LISTEN_TIME 2000
++
++#ifdef WBTEXT
++#define CMD_WBTEXT_PROFILE_CONFIG	"WBTEXT_PROFILE_CONFIG"
++#define CMD_WBTEXT_WEIGHT_CONFIG	"WBTEXT_WEIGHT_CONFIG"
++#define CMD_WBTEXT_TABLE_CONFIG		"WBTEXT_TABLE_CONFIG"
++#define CMD_WBTEXT_DELTA_CONFIG		"WBTEXT_DELTA_CONFIG"
++#define DEFAULT_WBTEXT_PROFILE_A		"a -70 -75 70 10 -75 -128 0 10"
++#define DEFAULT_WBTEXT_PROFILE_B		"b -60 -75 70 10 -75 -128 0 10"
++#define DEFAULT_WBTEXT_WEIGHT_RSSI_A	"RSSI a 65"
++#define DEFAULT_WBTEXT_WEIGHT_RSSI_B	"RSSI b 65"
++#define DEFAULT_WBTEXT_WEIGHT_CU_A	"CU a 35"
++#define DEFAULT_WBTEXT_WEIGHT_CU_B	"CU b 35"
++#define DEFAULT_WBTEXT_TABLE_RSSI_A	"RSSI a 0 55 100 55 60 90 \
++60 65 70 65 70 50 70 128 20"
++#define DEFAULT_WBTEXT_TABLE_RSSI_B	"RSSI b 0 55 100 55 60 90 \
++60 65 70 65 70 50 70 128 20"
++#define DEFAULT_WBTEXT_TABLE_CU_A	"CU a 0 30 100 30 50 90 \
++50 60 70 60 80 50 80 100 20"
++#define DEFAULT_WBTEXT_TABLE_CU_B	"CU b 0 10 100 10 25 90 \
++25 40 70 40 70 50 70 100 20"
++
++typedef struct wl_wbtext_bssid {
++	struct ether_addr ea;
++	struct list_head list;
++} wl_wbtext_bssid_t;
++
++static void wl_cfg80211_wbtext_update_rcc(struct bcm_cfg80211 *cfg, struct net_device *dev);
++static bool wl_cfg80211_wbtext_check_bssid_list(struct bcm_cfg80211 *cfg, struct ether_addr *ea);
++static bool wl_cfg80211_wbtext_add_bssid_list(struct bcm_cfg80211 *cfg, struct ether_addr *ea);
++static void wl_cfg80211_wbtext_clear_bssid_list(struct bcm_cfg80211 *cfg);
++static bool wl_cfg80211_wbtext_send_nbr_req(struct bcm_cfg80211 *cfg, struct net_device *dev,
++	struct wl_profile *profile);
++static bool wl_cfg80211_wbtext_send_btm_query(struct bcm_cfg80211 *cfg, struct net_device *dev,
++	struct wl_profile *profile);
++static void wl_cfg80211_wbtext_set_wnm_maxidle(struct bcm_cfg80211 *cfg, struct net_device *dev);
++static int wl_cfg80211_recv_nbr_resp(struct net_device *dev, uint8 *body, int body_len);
++#endif /* WBTEXT */
++
++#ifdef SUPPORT_AP_RADIO_PWRSAVE
++#define RADIO_PWRSAVE_PPS					10
++#define RADIO_PWRSAVE_QUIET_TIME			10
++#define RADIO_PWRSAVE_LEVEL				3
++#define RADIO_PWRSAVE_STAS_ASSOC_CHECK	0
++
++#define RADIO_PWRSAVE_LEVEL_MIN				1
++#define RADIO_PWRSAVE_LEVEL_MAX				5
++#define RADIO_PWRSAVE_PPS_MIN					1
++#define RADIO_PWRSAVE_QUIETTIME_MIN			1
++#define RADIO_PWRSAVE_ASSOCCHECK_MIN		0
++#define RADIO_PWRSAVE_ASSOCCHECK_MAX		1
++
++#define RADIO_PWRSAVE_MAJOR_VER 1
++#define RADIO_PWRSAVE_MINOR_VER 0
++#define RADIO_PWRSAVE_MAJOR_VER_SHIFT 8
++#define RADIO_PWRSAVE_VERSION \
++	((RADIO_PWRSAVE_MAJOR_VER << RADIO_PWRSAVE_MAJOR_VER_SHIFT)| RADIO_PWRSAVE_MINOR_VER)
++#endif /* SUPPORT_AP_RADIO_PWRSAVE */
++
++#ifdef WLADPS_SEAK_AP_WAR
++#define ATHEROS_OUI "\x00\x03\x7F"
++#define CAMEO_MAC_PREFIX "\x00\x18\xE7"
++#define MAC_PREFIX_LEN 3
++static bool
++wl_find_vndr_ies_specific_vender(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev, const u8 *vndr_oui);
++static s32 wl_set_adps_mode(struct bcm_cfg80211 *cfg, struct net_device *ndev, uint8 enable_mode);
++#endif /* WLADPS_SEAK_AP_WAR */
++
++#define MAX_VNDR_OUI_STR_LEN	256
++#define VNDR_OUI_STR_LEN	10
++static const uchar *exclude_vndr_oui_list[] = {
++	"\x00\x50\xf2",			/* Microsoft */
++	"\x00\x00\xf0",			/* Samsung Elec */
++	WFA_OUI,			/* WFA */
++	NULL
++};
++
++typedef struct wl_vndr_oui_entry {
++	uchar oui[DOT11_OUI_LEN];
++	struct list_head list;
++} wl_vndr_oui_entry_t;
++
++static int wl_vndr_ies_get_vendor_oui(struct bcm_cfg80211 *cfg,
++		struct net_device *ndev, char *vndr_oui, u32 vndr_oui_len);
++static void wl_vndr_ies_clear_vendor_oui_list(struct bcm_cfg80211 *cfg);
++
++/*
++ * cfg80211_ops api/callback list
++ */
++static s32 wl_frame_get_mgmt(u16 fc, const struct ether_addr *da,
++	const struct ether_addr *sa, const struct ether_addr *bssid,
++	u8 **pheader, u32 *body_len, u8 *pbody);
++static s32 __wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
++	struct cfg80211_scan_request *request,
++	struct cfg80211_ssid *this_ssid);
++#if defined(WL_CFG80211_P2P_DEV_IF)
++static s32
++wl_cfg80211_scan(struct wiphy *wiphy, struct cfg80211_scan_request *request);
++#else
++static s32
++wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
++	struct cfg80211_scan_request *request);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++static s32 wl_cfg80211_set_wiphy_params(struct wiphy *wiphy, u32 changed);
++#ifdef WLAIBSS_MCHAN
++static bcm_struct_cfgdev* bcm_cfg80211_add_ibss_if(struct wiphy *wiphy, char *name);
++static s32 bcm_cfg80211_del_ibss_if(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev);
++#endif /* WLAIBSS_MCHAN */
++static s32 wl_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_ibss_params *params);
++static s32 wl_cfg80211_leave_ibss(struct wiphy *wiphy,
++	struct net_device *dev);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++static s32 wl_cfg80211_get_station(struct wiphy *wiphy,
++	struct net_device *dev, const u8 *mac,
++	struct station_info *sinfo);
++#else
++static s32 wl_cfg80211_get_station(struct wiphy *wiphy,
++	struct net_device *dev, u8 *mac,
++	struct station_info *sinfo);
++#endif
++static s32 wl_cfg80211_set_power_mgmt(struct wiphy *wiphy,
++	struct net_device *dev, bool enabled,
++	s32 timeout);
++static int wl_cfg80211_connect(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_connect_params *sme);
++static s32 wl_cfg80211_disconnect(struct wiphy *wiphy, struct net_device *dev,
++	u16 reason_code);
++#if defined(WL_CFG80211_P2P_DEV_IF)
++static s32
++wl_cfg80211_set_tx_power(struct wiphy *wiphy, struct wireless_dev *wdev,
++	enum nl80211_tx_power_setting type, s32 mbm);
++#else
++static s32
++wl_cfg80211_set_tx_power(struct wiphy *wiphy,
++	enum nl80211_tx_power_setting type, s32 dbm);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++#if defined(WL_CFG80211_P2P_DEV_IF)
++static s32 wl_cfg80211_get_tx_power(struct wiphy *wiphy,
++	struct wireless_dev *wdev, s32 *dbm);
++#else
++static s32 wl_cfg80211_get_tx_power(struct wiphy *wiphy, s32 *dbm);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++static s32 wl_cfg80211_config_default_key(struct wiphy *wiphy,
++	struct net_device *dev,
++	u8 key_idx, bool unicast, bool multicast);
++static s32 wl_cfg80211_add_key(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, bool pairwise, const u8 *mac_addr,
++	struct key_params *params);
++static s32 wl_cfg80211_del_key(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, bool pairwise, const u8 *mac_addr);
++static s32 wl_cfg80211_get_key(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, bool pairwise, const u8 *mac_addr,
++	void *cookie, void (*callback) (void *cookie,
++	struct key_params *params));
++static s32 wl_cfg80211_config_default_mgmt_key(struct wiphy *wiphy,
++	struct net_device *dev,	u8 key_idx);
++static s32 wl_cfg80211_resume(struct wiphy *wiphy);
++#if defined(WL_SUPPORT_BACKPORTED_KPATCHES) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, \
++	2, 0))
++static s32 wl_cfg80211_mgmt_tx_cancel_wait(struct wiphy *wiphy,
++	bcm_struct_cfgdev *cfgdev, u64 cookie);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++static s32 wl_cfg80211_del_station(
++		struct wiphy *wiphy, struct net_device *ndev,
++		struct station_del_parameters *params);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++static s32 wl_cfg80211_del_station(struct wiphy *wiphy,
++	struct net_device *ndev, const u8* mac_addr);
++#else
++static s32 wl_cfg80211_del_station(struct wiphy *wiphy,
++	struct net_device *ndev, u8* mac_addr);
++#endif
++#ifdef WLMESH_CFG80211
++static s32 wl_cfg80211_join_mesh(
++	struct wiphy *wiphy, struct net_device *dev,
++	const struct mesh_config *conf,
++	const struct mesh_setup *setup);
++static s32 wl_cfg80211_leave_mesh(struct wiphy *wiphy,
++	struct net_device *dev);
++#endif /* WLMESH_CFG80211 */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++static s32 wl_cfg80211_change_station(struct wiphy *wiphy,
++	struct net_device *dev, const u8 *mac, struct station_parameters *params);
++#else
++static s32 wl_cfg80211_change_station(struct wiphy *wiphy,
++	struct net_device *dev, u8 *mac, struct station_parameters *params);
++#endif
++#endif /* WL_SUPPORT_BACKPORTED_KPATCHES || KERNEL_VER >= KERNEL_VERSION(3, 2, 0)) */
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39))
++static s32 wl_cfg80211_suspend(struct wiphy *wiphy, struct cfg80211_wowlan *wow);
++#else
++static s32 wl_cfg80211_suspend(struct wiphy *wiphy);
++#endif
++static s32 wl_cfg80211_set_pmksa(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_pmksa *pmksa);
++static s32 wl_cfg80211_del_pmksa(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_pmksa *pmksa);
++static s32 wl_cfg80211_flush_pmksa(struct wiphy *wiphy,
++	struct net_device *dev);
++void wl_cfg80211_scan_abort(struct bcm_cfg80211 *cfg);
++static void wl_cfg80211_cancel_scan(struct bcm_cfg80211 *cfg);
++static s32 wl_notify_escan_complete(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev, bool aborted, bool fw_abort);
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 2, 0))
++#if (defined(CONFIG_ARCH_MSM) && defined(TDLS_MGMT_VERSION2)) || (LINUX_VERSION_CODE < \
++	KERNEL_VERSION(3, 16, 0) && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))
++static s32 wl_cfg80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev,
++	u8 *peer, u8 action_code, u8 dialog_token, u16 status_code,
++	u32 peer_capability, const u8 *buf, size_t len);
++#elif ((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) && \
++		(LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0)))
++static s32 wl_cfg80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev,
++	const u8 *peer, u8 action_code, u8 dialog_token, u16 status_code,
++	u32 peer_capability, const u8 *buf, size_t len);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
++static s32 wl_cfg80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev,
++       const u8 *peer, u8 action_code, u8 dialog_token, u16 status_code,
++       u32 peer_capability, bool initiator, const u8 *buf, size_t len);
++#else /* CONFIG_ARCH_MSM && TDLS_MGMT_VERSION2 */
++static s32 wl_cfg80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev,
++	u8 *peer, u8 action_code, u8 dialog_token, u16 status_code,
++	const u8 *buf, size_t len);
++#endif /* CONFIG_ARCH_MSM && TDLS_MGMT_VERSION2 */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++static s32 wl_cfg80211_tdls_oper(struct wiphy *wiphy, struct net_device *dev,
++	const u8 *peer, enum nl80211_tdls_operation oper);
++#else
++static s32 wl_cfg80211_tdls_oper(struct wiphy *wiphy, struct net_device *dev,
++	u8 *peer, enum nl80211_tdls_operation oper);
++#endif
++#endif 
++#ifdef WL_SCHED_SCAN
++static int wl_cfg80211_sched_scan_stop(struct wiphy *wiphy, struct net_device *dev
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++	, u64 reqid
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)) */
++);
++#endif
++static s32 wl_cfg80211_set_ap_role(struct bcm_cfg80211 *cfg, struct net_device *dev);
++#if defined(WL_VIRTUAL_APSTA) || defined(DUAL_STA_STATIC_IF)
++bcm_struct_cfgdev*
++wl_cfg80211_create_iface(struct wiphy *wiphy, enum nl80211_iftype
++		 iface_type, u8 *mac_addr, const char *name);
++s32
++wl_cfg80211_del_iface(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev);
++#endif /* defined(WL_VIRTUAL_APSTA) || defined(DUAL_STA_STATIC_IF) */
++
++s32 wl_cfg80211_interface_ops(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev, s32 bsscfg_idx,
++	enum nl80211_iftype iface_type, s32 del, u8 *addr);
++s32 wl_cfg80211_add_del_bss(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev, s32 bsscfg_idx,
++	enum nl80211_iftype iface_type, s32 del, u8 *addr);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
++static s32 wl_cfg80211_stop_ap(struct wiphy *wiphy, struct net_device *dev);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0) */
++#ifdef GTK_OFFLOAD_SUPPORT
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
++static s32 wl_cfg80211_set_rekey_data(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_gtk_rekey_data *data);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0) */
++#endif /* GTK_OFFLOAD_SUPPORT */
++chanspec_t wl_chspec_driver_to_host(chanspec_t chanspec);
++chanspec_t wl_chspec_host_to_driver(chanspec_t chanspec);
++#ifdef WL11ULB
++static s32 wl_cfg80211_get_ulb_bw(struct bcm_cfg80211 *cfg, struct wireless_dev *wdev);
++static chanspec_t wl_cfg80211_ulb_get_min_bw_chspec(struct bcm_cfg80211 *cfg,
++	struct wireless_dev *wdev, s32 bssidx);
++static s32 wl_cfg80211_ulbbw_to_ulbchspec(u32 ulb_bw);
++#else
++static inline chanspec_t wl_cfg80211_ulb_get_min_bw_chspec(
++		struct bcm_cfg80211 *cfg, struct wireless_dev *wdev, s32 bssidx)
++{
++	return WL_CHANSPEC_BW_20;
++}
++#endif /* WL11ULB */
++static void wl_cfg80211_wait_for_disconnection(struct bcm_cfg80211 *cfg, struct net_device *dev);
++
++/*
++ * event & event Q handlers for cfg80211 interfaces
++ */
++static s32 wl_create_event_handler(struct bcm_cfg80211 *cfg);
++static void wl_destroy_event_handler(struct bcm_cfg80211 *cfg);
++static void wl_event_handler(struct work_struct *work_data);
++static void wl_init_eq(struct bcm_cfg80211 *cfg);
++static void wl_flush_eq(struct bcm_cfg80211 *cfg);
++static unsigned long wl_lock_eq(struct bcm_cfg80211 *cfg);
++static void wl_unlock_eq(struct bcm_cfg80211 *cfg, unsigned long flags);
++static void wl_init_eq_lock(struct bcm_cfg80211 *cfg);
++static void wl_init_event_handler(struct bcm_cfg80211 *cfg);
++static struct wl_event_q *wl_deq_event(struct bcm_cfg80211 *cfg);
++static s32 wl_enq_event(struct bcm_cfg80211 *cfg, struct net_device *ndev, u32 type,
++	const wl_event_msg_t *msg, void *data);
++static void wl_put_event(struct wl_event_q *e);
++static s32 wl_notify_connect_status_ap(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data);
++static s32 wl_notify_connect_status(struct bcm_cfg80211 *cfg,
++	bcm_struct_cfgdev *cfgdev, const wl_event_msg_t *e, void *data);
++static s32 wl_notify_roaming_status(struct bcm_cfg80211 *cfg,
++	bcm_struct_cfgdev *cfgdev, const wl_event_msg_t *e, void *data);
++static s32 wl_notify_scan_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++static s32 wl_bss_connect_done(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data, bool completed);
++static s32 wl_bss_roaming_done(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data);
++static s32 wl_notify_mic_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++#ifdef BT_WIFI_HANDOVER
++static s32 wl_notify_bt_wifi_handover_req(struct bcm_cfg80211 *cfg,
++	bcm_struct_cfgdev *cfgdev, const wl_event_msg_t *e, void *data);
++#endif /* BT_WIFI_HANDOVER */
++#ifdef WL_SCHED_SCAN
++static s32
++wl_notify_sched_scan_results(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data);
++#endif /* WL_SCHED_SCAN */
++#ifdef PNO_SUPPORT
++static s32 wl_notify_pfn_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++#endif /* PNO_SUPPORT */
++#ifdef GSCAN_SUPPORT
++static s32 wl_notify_gscan_event(struct bcm_cfg80211 *wl, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++static s32 wl_handle_roam_exp_event(struct bcm_cfg80211 *wl, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++#endif /* GSCAN_SUPPORT */
++#ifdef RSSI_MONITOR_SUPPORT
++static s32 wl_handle_rssi_monitor_event(struct bcm_cfg80211 *wl, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++#endif /* RSSI_MONITOR_SUPPORT */
++static s32 wl_notifier_change_state(struct bcm_cfg80211 *cfg, struct net_info *_net_info,
++	enum wl_status state, bool set);
++#ifdef CUSTOM_EVENT_PM_WAKE
++static s32 wl_check_pmstatus(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++#endif	/* CUSTOM_EVENT_PM_WAKE */
++#ifdef ENABLE_TEMP_THROTTLING
++static s32 wl_check_rx_throttle_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++#endif /* ENABLE_TEMP_THROTTLING */
++#if defined(DHD_LOSSLESS_ROAMING) || defined(DBG_PKT_MON)
++static s32 wl_notify_roam_prep_status(struct bcm_cfg80211 *cfg,
++	bcm_struct_cfgdev *cfgdev, const wl_event_msg_t *e, void *data);
++#endif /* DHD_LOSSLESS_ROAMING || DBG_PKT_MON */
++#ifdef DHD_LOSSLESS_ROAMING
++static void wl_del_roam_timeout(struct bcm_cfg80211 *cfg);
++#endif /* DHD_LOSSLESS_ROAMING */
++
++#ifdef WLTDLS
++static s32 wl_cfg80211_tdls_config(struct bcm_cfg80211 *cfg,
++	enum wl_tdls_config state, bool tdls_mode);
++static s32 wl_tdls_event_handler(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++#endif /* WLTDLS */
++/*
++ * register/deregister parent device
++ */
++static void wl_cfg80211_clear_parent_dev(void);
++/*
++ * ioctl utilites
++ */
++
++/*
++ * cfg80211 set_wiphy_params utilities
++ */
++static s32 wl_set_frag(struct net_device *dev, u32 frag_threshold);
++static s32 wl_set_rts(struct net_device *dev, u32 frag_threshold);
++static s32 wl_set_retry(struct net_device *dev, u32 retry, bool l);
++
++/*
++ * cfg profile utilities
++ */
++static s32 wl_update_prof(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, const void *data, s32 item);
++static void *wl_read_prof(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 item);
++static void wl_init_prof(struct bcm_cfg80211 *cfg, struct net_device *ndev);
++
++/*
++ * cfg80211 connect utilites
++ */
++static s32 wl_set_wpa_version(struct net_device *dev,
++	struct cfg80211_connect_params *sme);
++static s32 wl_set_auth_type(struct net_device *dev,
++	struct cfg80211_connect_params *sme);
++static s32 wl_set_set_cipher(struct net_device *dev,
++	struct cfg80211_connect_params *sme);
++static s32 wl_set_key_mgmt(struct net_device *dev,
++	struct cfg80211_connect_params *sme);
++#ifdef BCMWAPI_WPI
++static s32 wl_set_set_wapi_ie(struct net_device *dev,
++        struct cfg80211_connect_params *sme);
++#endif
++static s32 wl_set_set_sharedkey(struct net_device *dev,
++	struct cfg80211_connect_params *sme);
++static s32 wl_get_assoc_ies(struct bcm_cfg80211 *cfg, struct net_device *ndev);
++static s32 wl_ch_to_chanspec(struct net_device *dev, int ch,
++	struct wl_join_params *join_params, size_t *join_params_size);
++void wl_cfg80211_clear_security(struct bcm_cfg80211 *cfg);
++
++/*
++ * information element utilities
++ */
++static void wl_rst_ie(struct bcm_cfg80211 *cfg);
++static __used s32 wl_add_ie(struct bcm_cfg80211 *cfg, u8 t, u8 l, u8 *v);
++static void wl_update_hidden_ap_ie(struct wl_bss_info *bi, const u8 *ie_stream, u32 *ie_size,
++	bool roam);
++static s32 wl_mrg_ie(struct bcm_cfg80211 *cfg, u8 *ie_stream, u16 ie_size);
++static s32 wl_cp_ie(struct bcm_cfg80211 *cfg, u8 *dst, u16 dst_size);
++static u32 wl_get_ielen(struct bcm_cfg80211 *cfg);
++#ifdef MFP
++static int wl_cfg80211_get_rsn_capa(bcm_tlv_t *wpa2ie, u8** rsn_cap);
++#endif
++
++#ifdef WL11U
++static bcm_tlv_t *
++wl_cfg80211_find_interworking_ie(const u8 *parse, u32 len);
++static s32
++wl_cfg80211_clear_iw_ie(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 bssidx);
++static s32
++wl_cfg80211_add_iw_ie(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 bssidx, s32 pktflag,
++            uint8 ie_id, uint8 *data, uint8 data_len);
++#endif /* WL11U */
++
++static s32 wl_setup_wiphy(struct wireless_dev *wdev, struct device *dev, dhd_pub_t *data);
++static void wl_free_wdev(struct bcm_cfg80211 *cfg);
++#ifdef CONFIG_CFG80211_INTERNAL_REGDB
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 11))
++static int
++#else
++static void
++#endif /* kernel version < 3.10.11 */
++wl_cfg80211_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request);
++#endif /* CONFIG_CFG80211_INTERNAL_REGDB */
++
++static s32 wl_inform_bss(struct bcm_cfg80211 *cfg);
++static s32 wl_inform_single_bss(struct bcm_cfg80211 *cfg, struct wl_bss_info *bi, bool roam);
++static s32 wl_update_bss_info(struct bcm_cfg80211 *cfg, struct net_device *ndev, bool roam);
++static chanspec_t wl_cfg80211_get_shared_freq(struct wiphy *wiphy);
++s32 wl_cfg80211_channel_to_freq(u32 channel);
++
++
++static void wl_cfg80211_work_handler(struct work_struct *work);
++static s32 wl_add_keyext(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, const u8 *mac_addr,
++	struct key_params *params);
++/*
++ * key indianess swap utilities
++ */
++static void swap_key_from_BE(struct wl_wsec_key *key);
++static void swap_key_to_BE(struct wl_wsec_key *key);
++
++/*
++ * bcm_cfg80211 memory init/deinit utilities
++ */
++static s32 wl_init_priv_mem(struct bcm_cfg80211 *cfg);
++static void wl_deinit_priv_mem(struct bcm_cfg80211 *cfg);
++
++static void wl_delay(u32 ms);
++
++/*
++ * ibss mode utilities
++ */
++static bool wl_is_ibssmode(struct bcm_cfg80211 *cfg, struct net_device *ndev);
++static __used bool wl_is_ibssstarter(struct bcm_cfg80211 *cfg);
++
++/*
++ * link up/down , default configuration utilities
++ */
++static s32 __wl_cfg80211_up(struct bcm_cfg80211 *cfg);
++static s32 __wl_cfg80211_down(struct bcm_cfg80211 *cfg);
++
++#ifdef WL_LASTEVT
++static bool wl_is_linkdown(struct bcm_cfg80211 *cfg, const wl_event_msg_t *e, void *data);
++#define WL_IS_LINKDOWN(cfg, e, data) wl_is_linkdown(cfg, e, data)
++#else
++static bool wl_is_linkdown(struct bcm_cfg80211 *cfg, const wl_event_msg_t *e);
++#define WL_IS_LINKDOWN(cfg, e, data) wl_is_linkdown(cfg, e)
++#endif /* WL_LASTEVT */
++
++static bool wl_is_linkup(struct bcm_cfg80211 *cfg, const wl_event_msg_t *e,
++	struct net_device *ndev);
++static bool wl_is_nonetwork(struct bcm_cfg80211 *cfg, const wl_event_msg_t *e);
++static void wl_link_up(struct bcm_cfg80211 *cfg);
++static void wl_link_down(struct bcm_cfg80211 *cfg);
++static s32 wl_config_ifmode(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 iftype);
++static void wl_init_conf(struct wl_conf *conf);
++static s32 wl_cfg80211_handle_ifdel(struct bcm_cfg80211 *cfg, wl_if_event_info *if_event_info,
++	struct net_device* ndev);
++int wl_cfg80211_get_ioctl_version(void);
++
++/*
++ * find most significant bit set
++ */
++static __used u32 wl_find_msb(u16 bit16);
++
++/*
++ * rfkill support
++ */
++static int wl_setup_rfkill(struct bcm_cfg80211 *cfg, bool setup);
++static int wl_rfkill_set(void *data, bool blocked);
++#ifdef DEBUGFS_CFG80211
++static s32 wl_setup_debugfs(struct bcm_cfg80211 *cfg);
++static s32 wl_free_debugfs(struct bcm_cfg80211 *cfg);
++#endif
++static wl_scan_params_t *wl_cfg80211_scan_alloc_params(struct bcm_cfg80211 *cfg,
++	int channel, int nprobes, int *out_params_size);
++static bool check_dev_role_integrity(struct bcm_cfg80211 *cfg, u32 dev_role);
++
++#ifdef WL_CFG80211_ACL
++/* ACL */
++static int wl_cfg80211_set_mac_acl(struct wiphy *wiphy, struct net_device *cfgdev,
++	const struct cfg80211_acl_data *acl);
++#endif /* WL_CFG80211_ACL */
++
++/*
++ * Some external functions, TODO: move them to dhd_linux.h
++ */
++int dhd_add_monitor(const char *name, struct net_device **new_ndev);
++int dhd_del_monitor(struct net_device *ndev);
++int dhd_monitor_init(void *dhd_pub);
++int dhd_monitor_uninit(void);
++int dhd_start_xmit(struct sk_buff *skb, struct net_device *net);
++
++
++#ifdef P2P_LISTEN_OFFLOADING
++s32 wl_cfg80211_p2plo_deinit(struct bcm_cfg80211 *cfg);
++#endif /* P2P_LISTEN_OFFLOADING */
++
++#ifdef PKT_FILTER_SUPPORT
++extern uint dhd_pkt_filter_enable;
++extern uint dhd_master_mode;
++extern void dhd_pktfilter_offload_enable(dhd_pub_t * dhd, char *arg, int enable, int master_mode);
++#endif /* PKT_FILTER_SUPPORT */
++
++#ifdef SUPPORT_SET_CAC
++static void wl_cfg80211_set_cac(struct bcm_cfg80211 *cfg, int enable);
++#endif /* SUPPORT_SET_CAC */
++
++static int wl_cfg80211_delayed_roam(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const struct ether_addr *bssid);
++static s32 __wl_update_wiphybands(struct bcm_cfg80211 *cfg, bool notify);
++
++static int bw2cap[] = { 0, 0, WLC_BW_CAP_20MHZ, WLC_BW_CAP_40MHZ, WLC_BW_CAP_80MHZ,
++	WLC_BW_CAP_160MHZ, WLC_BW_CAP_160MHZ };
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0)) || (defined(CONFIG_ARCH_MSM) && \
++	defined(CFG80211_DISCONNECTED_V2))
++#define CFG80211_DISCONNECTED(dev, reason, ie, len, loc_gen, gfp) \
++	cfg80211_disconnected(dev, reason, ie, len, loc_gen, gfp);
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0))
++#define CFG80211_DISCONNECTED(dev, reason, ie, len, loc_gen, gfp) \
++	cfg80211_disconnected(dev, reason, ie, len, gfp);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0)) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) || (defined(CONFIG_ARCH_MSM) && \
++	defined(CFG80211_DISCONNECTED_V2))
++#define CFG80211_GET_BSS(wiphy, channel, bssid, ssid, ssid_len) \
++	cfg80211_get_bss(wiphy, channel, bssid, ssid, ssid_len,	\
++			IEEE80211_BSS_TYPE_ESS, IEEE80211_PRIVACY_ANY);
++#else
++#define CFG80211_GET_BSS(wiphy, channel, bssid, ssid, ssid_len) \
++	cfg80211_get_bss(wiphy, channel, bssid, ssid, ssid_len,	\
++			WLAN_CAPABILITY_ESS, WLAN_CAPABILITY_ESS);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) */
++
++#define IS_WPA_AKM(akm) ((akm) == RSN_AKM_NONE || 			\
++				 (akm) == RSN_AKM_UNSPECIFIED || 	\
++				 (akm) == RSN_AKM_PSK)
++
++
++extern int dhd_wait_pend8021x(struct net_device *dev);
++#ifdef PROP_TXSTATUS_VSDB
++extern int disable_proptx;
++#endif /* PROP_TXSTATUS_VSDB */
++static int wl_cfg80211_check_in4way(struct bcm_cfg80211 *cfg,
++	struct net_device *dev, uint action, enum wl_ext_status status, void *context);
++
++
++extern int passive_channel_skip;
++
++static s32
++wl_ap_start_ind(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++static s32
++wl_csa_complete_ind(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++#if ((LINUX_VERSION_CODE >= KERNEL_VERSION (3, 5, 0)) && (LINUX_VERSION_CODE <= (3, 7, \
++	0)))
++struct chan_info {
++	int freq;
++	int chan_type;
++};
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++#define CFG80211_PUT_BSS(wiphy, bss) cfg80211_put_bss(wiphy, bss);
++#else
++#define CFG80211_PUT_BSS(wiphy, bss) cfg80211_put_bss(bss);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) */
++
++#define CHAN2G(_channel, _freq, _flags) {			\
++	.band			= IEEE80211_BAND_2GHZ,		\
++	.center_freq		= (_freq),			\
++	.hw_value		= (_channel),			\
++	.flags			= (_flags),			\
++	.max_antenna_gain	= 0,				\
++	.max_power		= 30,				\
++}
++
++#define CHAN5G(_channel, _flags) {				\
++	.band			= IEEE80211_BAND_5GHZ,		\
++	.center_freq		= 5000 + (5 * (_channel)),	\
++	.hw_value		= (_channel),			\
++	.flags			= (_flags),			\
++	.max_antenna_gain	= 0,				\
++	.max_power		= 30,				\
++}
++
++#define RATE_TO_BASE100KBPS(rate)   (((rate) * 10) / 2)
++#define RATETAB_ENT(_rateid, _flags) \
++	{								\
++		.bitrate	= RATE_TO_BASE100KBPS(_rateid),     \
++		.hw_value	= (_rateid),			    \
++		.flags	  = (_flags),			     \
++	}
++
++static struct ieee80211_rate __wl_rates[] = {
++	RATETAB_ENT(DOT11_RATE_1M, 0),
++	RATETAB_ENT(DOT11_RATE_2M, IEEE80211_RATE_SHORT_PREAMBLE),
++	RATETAB_ENT(DOT11_RATE_5M5, IEEE80211_RATE_SHORT_PREAMBLE),
++	RATETAB_ENT(DOT11_RATE_11M, IEEE80211_RATE_SHORT_PREAMBLE),
++	RATETAB_ENT(DOT11_RATE_6M, 0),
++	RATETAB_ENT(DOT11_RATE_9M, 0),
++	RATETAB_ENT(DOT11_RATE_12M, 0),
++	RATETAB_ENT(DOT11_RATE_18M, 0),
++	RATETAB_ENT(DOT11_RATE_24M, 0),
++	RATETAB_ENT(DOT11_RATE_36M, 0),
++	RATETAB_ENT(DOT11_RATE_48M, 0),
++	RATETAB_ENT(DOT11_RATE_54M, 0)
++};
++
++#define wl_a_rates		(__wl_rates + 4)
++#define wl_a_rates_size	8
++#define wl_g_rates		(__wl_rates + 0)
++#define wl_g_rates_size	12
++
++static struct ieee80211_channel __wl_2ghz_channels[] = {
++	CHAN2G(1, 2412, 0),
++	CHAN2G(2, 2417, 0),
++	CHAN2G(3, 2422, 0),
++	CHAN2G(4, 2427, 0),
++	CHAN2G(5, 2432, 0),
++	CHAN2G(6, 2437, 0),
++	CHAN2G(7, 2442, 0),
++	CHAN2G(8, 2447, 0),
++	CHAN2G(9, 2452, 0),
++	CHAN2G(10, 2457, 0),
++	CHAN2G(11, 2462, 0),
++	CHAN2G(12, 2467, 0),
++	CHAN2G(13, 2472, 0),
++	CHAN2G(14, 2484, 0)
++};
++
++static struct ieee80211_channel __wl_5ghz_a_channels[] = {
++	CHAN5G(34, 0), CHAN5G(36, 0),
++	CHAN5G(38, 0), CHAN5G(40, 0),
++	CHAN5G(42, 0), CHAN5G(44, 0),
++	CHAN5G(46, 0), CHAN5G(48, 0),
++	CHAN5G(52, 0), CHAN5G(56, 0),
++	CHAN5G(60, 0), CHAN5G(64, 0),
++	CHAN5G(100, 0), CHAN5G(104, 0),
++	CHAN5G(108, 0), CHAN5G(112, 0),
++	CHAN5G(116, 0), CHAN5G(120, 0),
++	CHAN5G(124, 0), CHAN5G(128, 0),
++	CHAN5G(132, 0), CHAN5G(136, 0),
++	CHAN5G(140, 0), CHAN5G(144, 0),
++	CHAN5G(149, 0), CHAN5G(153, 0),
++	CHAN5G(157, 0), CHAN5G(161, 0),
++	CHAN5G(165, 0)
++};
++
++static struct ieee80211_supported_band __wl_band_2ghz = {
++	.band = IEEE80211_BAND_2GHZ,
++	.channels = __wl_2ghz_channels,
++	.n_channels = ARRAY_SIZE(__wl_2ghz_channels),
++	.bitrates = wl_g_rates,
++	.n_bitrates = wl_g_rates_size
++};
++
++static struct ieee80211_supported_band __wl_band_5ghz_a = {
++	.band = IEEE80211_BAND_5GHZ,
++	.channels = __wl_5ghz_a_channels,
++	.n_channels = ARRAY_SIZE(__wl_5ghz_a_channels),
++	.bitrates = wl_a_rates,
++	.n_bitrates = wl_a_rates_size
++};
++
++static const u32 __wl_cipher_suites[] = {
++	WLAN_CIPHER_SUITE_WEP40,
++	WLAN_CIPHER_SUITE_WEP104,
++	WLAN_CIPHER_SUITE_TKIP,
++	WLAN_CIPHER_SUITE_CCMP,
++#ifdef MFP
++	/*
++	 * Advertising AES_CMAC cipher suite to userspace would imply that we
++	 * are supporting MFP. So advertise only when MFP support is enabled.
++	 */
++	WLAN_CIPHER_SUITE_AES_CMAC,
++#endif /* MFP */
++#ifdef BCMWAPI_WPI
++	WLAN_CIPHER_SUITE_SMS4,
++#endif
++#if defined(WLAN_CIPHER_SUITE_PMK)
++	WLAN_CIPHER_SUITE_PMK,
++#endif
++};
++
++#ifdef WL_SUPPORT_ACS
++/*
++ * The firmware code required for this feature to work is currently under
++ * BCMINTERNAL flag. In future if this is to enabled we need to bring the
++ * required firmware code out of the BCMINTERNAL flag.
++ */
++struct wl_dump_survey {
++	u32 obss;
++	u32 ibss;
++	u32 no_ctg;
++	u32 no_pckt;
++	u32 tx;
++	u32 idle;
++};
++#endif /* WL_SUPPORT_ACS */
++
++
++#if defined(USE_DYNAMIC_MAXPKT_RXGLOM)
++static int maxrxpktglom = 0;
++#endif
++
++/* IOCtl version read from targeted driver */
++int ioctl_version;
++#ifdef DEBUGFS_CFG80211
++#define S_SUBLOGLEVEL 20
++static const struct {
++	u32 log_level;
++	char *sublogname;
++} sublogname_map[] = {
++	{WL_DBG_ERR, "ERR"},
++	{WL_DBG_INFO, "INFO"},
++	{WL_DBG_DBG, "DBG"},
++	{WL_DBG_SCAN, "SCAN"},
++	{WL_DBG_TRACE, "TRACE"},
++	{WL_DBG_P2P_ACTION, "P2PACTION"}
++};
++#endif
++
++#ifdef CUSTOMER_HW4_DEBUG
++uint prev_dhd_console_ms = 0;
++u32 prev_wl_dbg_level = 0;
++bool wl_scan_timeout_dbg_enabled = 0;
++static void wl_scan_timeout_dbg_set(void);
++static void wl_scan_timeout_dbg_clear(void);
++
++static void wl_scan_timeout_dbg_set(void)
++{
++	WL_ERR(("Enter \n"));
++	prev_dhd_console_ms = dhd_console_ms;
++	prev_wl_dbg_level = wl_dbg_level;
++
++	dhd_console_ms = 1;
++	wl_dbg_level |= (WL_DBG_ERR | WL_DBG_P2P_ACTION | WL_DBG_SCAN);
++
++	wl_scan_timeout_dbg_enabled = 1;
++}
++static void wl_scan_timeout_dbg_clear(void)
++{
++	WL_ERR(("Enter \n"));
++	dhd_console_ms = prev_dhd_console_ms;
++	wl_dbg_level = prev_wl_dbg_level;
++
++	wl_scan_timeout_dbg_enabled = 0;
++}
++#endif /* CUSTOMER_HW4_DEBUG */
++
++/* watchdog timer for disconnecting when fw is not associated for FW_ASSOC_WATCHDOG_TIME ms */
++uint32 fw_assoc_watchdog_ms = 0;
++bool fw_assoc_watchdog_started = 0;
++#define FW_ASSOC_WATCHDOG_TIME 10 * 1000 /* msec */
++
++static void wl_add_remove_pm_enable_work(struct bcm_cfg80211 *cfg,
++	enum wl_pm_workq_act_type type)
++{
++	u16 wq_duration = 0;
++	dhd_pub_t *dhd =  NULL;
++
++	if (cfg == NULL)
++		return;
++
++	dhd = (dhd_pub_t *)(cfg->pub);
++
++	mutex_lock(&cfg->pm_sync);
++	/*
++	 * Make cancel and schedule work part mutually exclusive
++	 * so that while cancelling, we are sure that there is no
++	 * work getting scheduled.
++	 */
++	if (delayed_work_pending(&cfg->pm_enable_work)) {
++		cancel_delayed_work_sync(&cfg->pm_enable_work);
++		DHD_PM_WAKE_UNLOCK(cfg->pub);
++	}
++
++	if (type == WL_PM_WORKQ_SHORT) {
++		wq_duration = WL_PM_ENABLE_TIMEOUT;
++	} else if (type == WL_PM_WORKQ_LONG) {
++		wq_duration = (WL_PM_ENABLE_TIMEOUT*2);
++	}
++
++	/* It should schedule work item only if driver is up */
++	if (wq_duration && dhd->up) {
++		if (schedule_delayed_work(&cfg->pm_enable_work,
++				msecs_to_jiffies((const unsigned int)wq_duration))) {
++			DHD_PM_WAKE_LOCK_TIMEOUT(cfg->pub, wq_duration);
++		} else {
++			WL_ERR(("Can't schedule pm work handler\n"));
++		}
++	}
++	mutex_unlock(&cfg->pm_sync);
++}
++
++/* Return a new chanspec given a legacy chanspec
++ * Returns INVCHANSPEC on error
++ */
++chanspec_t
++wl_chspec_from_legacy(chanspec_t legacy_chspec)
++{
++	chanspec_t chspec;
++
++	/* get the channel number */
++	chspec = LCHSPEC_CHANNEL(legacy_chspec);
++
++	/* convert the band */
++	if (LCHSPEC_IS2G(legacy_chspec)) {
++		chspec |= WL_CHANSPEC_BAND_2G;
++	} else {
++		chspec |= WL_CHANSPEC_BAND_5G;
++	}
++
++	/* convert the bw and sideband */
++	if (LCHSPEC_IS20(legacy_chspec)) {
++		chspec |= WL_CHANSPEC_BW_20;
++	} else {
++		chspec |= WL_CHANSPEC_BW_40;
++		if (LCHSPEC_CTL_SB(legacy_chspec) == WL_LCHANSPEC_CTL_SB_LOWER) {
++			chspec |= WL_CHANSPEC_CTL_SB_L;
++		} else {
++			chspec |= WL_CHANSPEC_CTL_SB_U;
++		}
++	}
++
++	if (wf_chspec_malformed(chspec)) {
++		WL_ERR(("wl_chspec_from_legacy: output chanspec (0x%04X) malformed\n",
++		        chspec));
++		return INVCHANSPEC;
++	}
++
++	return chspec;
++}
++
++/* Return a legacy chanspec given a new chanspec
++ * Returns INVCHANSPEC on error
++ */
++static chanspec_t
++wl_chspec_to_legacy(chanspec_t chspec)
++{
++	chanspec_t lchspec;
++
++	if (wf_chspec_malformed(chspec)) {
++		WL_ERR(("wl_chspec_to_legacy: input chanspec (0x%04X) malformed\n",
++		        chspec));
++		return INVCHANSPEC;
++	}
++
++	/* get the channel number */
++	lchspec = CHSPEC_CHANNEL(chspec);
++
++	/* convert the band */
++	if (CHSPEC_IS2G(chspec)) {
++		lchspec |= WL_LCHANSPEC_BAND_2G;
++	} else {
++		lchspec |= WL_LCHANSPEC_BAND_5G;
++	}
++
++	/* convert the bw and sideband */
++	if (CHSPEC_IS20(chspec)) {
++		lchspec |= WL_LCHANSPEC_BW_20;
++		lchspec |= WL_LCHANSPEC_CTL_SB_NONE;
++	} else if (CHSPEC_IS40(chspec)) {
++		lchspec |= WL_LCHANSPEC_BW_40;
++		if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_L) {
++			lchspec |= WL_LCHANSPEC_CTL_SB_LOWER;
++		} else {
++			lchspec |= WL_LCHANSPEC_CTL_SB_UPPER;
++		}
++	} else {
++		/* cannot express the bandwidth */
++		char chanbuf[CHANSPEC_STR_LEN];
++		WL_ERR((
++		        "wl_chspec_to_legacy: unable to convert chanspec %s (0x%04X) "
++		        "to pre-11ac format\n",
++		        wf_chspec_ntoa(chspec, chanbuf), chspec));
++		return INVCHANSPEC;
++	}
++
++	return lchspec;
++}
++
++/* given a chanspec value, do the endian and chanspec version conversion to
++ * a chanspec_t value
++ * Returns INVCHANSPEC on error
++ */
++chanspec_t
++wl_chspec_host_to_driver(chanspec_t chanspec)
++{
++	if (ioctl_version == 1) {
++		chanspec = wl_chspec_to_legacy(chanspec);
++		if (chanspec == INVCHANSPEC) {
++			return chanspec;
++		}
++	}
++	chanspec = htodchanspec(chanspec);
++
++	return chanspec;
++}
++
++/* given a channel value, do the endian and chanspec version conversion to
++ * a chanspec_t value
++ * Returns INVCHANSPEC on error
++ */
++chanspec_t
++wl_ch_host_to_driver(struct bcm_cfg80211 *cfg, s32 bssidx, u16 channel)
++{
++	chanspec_t chanspec;
++
++	chanspec = channel & WL_CHANSPEC_CHAN_MASK;
++
++	if (channel <= CH_MAX_2G_CHANNEL)
++		chanspec |= WL_CHANSPEC_BAND_2G;
++	else
++		chanspec |= WL_CHANSPEC_BAND_5G;
++
++	chanspec |= wl_cfg80211_ulb_get_min_bw_chspec(cfg, NULL, bssidx);
++
++	chanspec |= WL_CHANSPEC_CTL_SB_NONE;
++
++	return wl_chspec_host_to_driver(chanspec);
++}
++
++/* given a chanspec value from the driver, do the endian and chanspec version conversion to
++ * a chanspec_t value
++ * Returns INVCHANSPEC on error
++ */
++chanspec_t
++wl_chspec_driver_to_host(chanspec_t chanspec)
++{
++	chanspec = dtohchanspec(chanspec);
++	if (ioctl_version == 1) {
++		chanspec = wl_chspec_from_legacy(chanspec);
++	}
++
++	return chanspec;
++}
++
++/*
++ * convert ASCII string to MAC address (colon-delimited format)
++ * eg: 00:11:22:33:44:55
++ */
++int
++wl_cfg80211_ether_atoe(const char *a, struct ether_addr *n)
++{
++	char *c = NULL;
++	int count = 0;
++
++	memset(n, 0, ETHER_ADDR_LEN);
++	for (;;) {
++		n->octet[count++] = (uint8)simple_strtoul(a, &c, 16);
++		if (!*c++ || count == ETHER_ADDR_LEN)
++			break;
++		a = c;
++	}
++	return (count == ETHER_ADDR_LEN);
++}
++
++/* There isn't a lot of sense in it, but you can transmit anything you like */
++static const struct ieee80211_txrx_stypes
++wl_cfg80211_default_mgmt_stypes[NUM_NL80211_IFTYPES] = {
++#ifdef WLMESH_CFG80211
++	[NL80211_IFTYPE_MESH_POINT] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
++		BIT(IEEE80211_STYPE_AUTH >> 4)
++	},
++#endif /* WLMESH_CFG80211 */
++	[NL80211_IFTYPE_ADHOC] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ACTION >> 4)
++	},
++	[NL80211_IFTYPE_STATION] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
++		BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
++	},
++	[NL80211_IFTYPE_AP] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
++		BIT(IEEE80211_STYPE_DISASSOC >> 4) |
++		BIT(IEEE80211_STYPE_AUTH >> 4) |
++		BIT(IEEE80211_STYPE_DEAUTH >> 4) |
++		BIT(IEEE80211_STYPE_ACTION >> 4)
++	},
++	[NL80211_IFTYPE_AP_VLAN] = {
++		/* copy AP */
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
++		BIT(IEEE80211_STYPE_DISASSOC >> 4) |
++		BIT(IEEE80211_STYPE_AUTH >> 4) |
++		BIT(IEEE80211_STYPE_DEAUTH >> 4) |
++		BIT(IEEE80211_STYPE_ACTION >> 4)
++	},
++	[NL80211_IFTYPE_P2P_CLIENT] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
++		BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
++	},
++	[NL80211_IFTYPE_P2P_GO] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
++		BIT(IEEE80211_STYPE_DISASSOC >> 4) |
++		BIT(IEEE80211_STYPE_AUTH >> 4) |
++		BIT(IEEE80211_STYPE_DEAUTH >> 4) |
++		BIT(IEEE80211_STYPE_ACTION >> 4)
++	},
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	[NL80211_IFTYPE_P2P_DEVICE] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
++		BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
++	},
++#endif /* WL_CFG80211_P2P_DEV_IF */
++};
++
++static void swap_key_from_BE(struct wl_wsec_key *key)
++{
++	key->index = htod32(key->index);
++	key->len = htod32(key->len);
++	key->algo = htod32(key->algo);
++	key->flags = htod32(key->flags);
++	key->rxiv.hi = htod32(key->rxiv.hi);
++	key->rxiv.lo = htod16(key->rxiv.lo);
++	key->iv_initialized = htod32(key->iv_initialized);
++}
++
++static void swap_key_to_BE(struct wl_wsec_key *key)
++{
++	key->index = dtoh32(key->index);
++	key->len = dtoh32(key->len);
++	key->algo = dtoh32(key->algo);
++	key->flags = dtoh32(key->flags);
++	key->rxiv.hi = dtoh32(key->rxiv.hi);
++	key->rxiv.lo = dtoh16(key->rxiv.lo);
++	key->iv_initialized = dtoh32(key->iv_initialized);
++}
++
++/* Dump the contents of the encoded wps ie buffer and get pbc value */
++static void
++wl_validate_wps_ie(char *wps_ie, s32 wps_ie_len, bool *pbc)
++{
++	#define WPS_IE_FIXED_LEN 6
++	s16 len;
++	u8 *subel = NULL;
++	u16 subelt_id;
++	u16 subelt_len;
++	u16 val;
++	u8 *valptr = (uint8*) &val;
++	if (wps_ie == NULL || wps_ie_len < WPS_IE_FIXED_LEN) {
++		WL_ERR(("invalid argument : NULL\n"));
++		return;
++	}
++	len = (s16)wps_ie[TLV_LEN_OFF];
++
++	if (len > wps_ie_len) {
++		WL_ERR(("invalid length len %d, wps ie len %d\n", len, wps_ie_len));
++		return;
++	}
++	WL_DBG(("wps_ie len=%d\n", len));
++	len -= 4;	/* for the WPS IE's OUI, oui_type fields */
++	subel = wps_ie + WPS_IE_FIXED_LEN;
++	while (len >= 4) {		/* must have attr id, attr len fields */
++		valptr[0] = *subel++;
++		valptr[1] = *subel++;
++		subelt_id = HTON16(val);
++
++		valptr[0] = *subel++;
++		valptr[1] = *subel++;
++		subelt_len = HTON16(val);
++
++		len -= 4;			/* for the attr id, attr len fields */
++		len -= (s16)subelt_len;	/* for the remaining fields in this attribute */
++		if (len < 0) {
++			break;
++		}
++		WL_DBG((" subel=%p, subelt_id=0x%x subelt_len=%u\n",
++			subel, subelt_id, subelt_len));
++
++		if (subelt_id == WPS_ID_VERSION) {
++			WL_DBG(("  attr WPS_ID_VERSION: %u\n", *subel));
++		} else if (subelt_id == WPS_ID_REQ_TYPE) {
++			WL_DBG(("  attr WPS_ID_REQ_TYPE: %u\n", *subel));
++		} else if (subelt_id == WPS_ID_CONFIG_METHODS) {
++			valptr[0] = *subel;
++			valptr[1] = *(subel + 1);
++			WL_DBG(("  attr WPS_ID_CONFIG_METHODS: %x\n", HTON16(val)));
++		} else if (subelt_id == WPS_ID_DEVICE_NAME) {
++			char devname[100];
++			int namelen = MIN(subelt_len, (sizeof(devname) - 1));
++
++			if (namelen) {
++				memcpy(devname, subel, namelen);
++				devname[namelen] = '\0';
++				/* Printing len as rx'ed in the IE */
++				WL_DBG(("  attr WPS_ID_DEVICE_NAME: %s (len %u)\n",
++					devname, subelt_len));
++			}
++		} else if (subelt_id == WPS_ID_DEVICE_PWD_ID) {
++			valptr[0] = *subel;
++			valptr[1] = *(subel + 1);
++			WL_DBG(("  attr WPS_ID_DEVICE_PWD_ID: %u\n", HTON16(val)));
++			*pbc = (HTON16(val) == DEV_PW_PUSHBUTTON) ? true : false;
++		} else if (subelt_id == WPS_ID_PRIM_DEV_TYPE) {
++			valptr[0] = *subel;
++			valptr[1] = *(subel + 1);
++			WL_DBG(("  attr WPS_ID_PRIM_DEV_TYPE: cat=%u \n", HTON16(val)));
++			valptr[0] = *(subel + 6);
++			valptr[1] = *(subel + 7);
++			WL_DBG(("  attr WPS_ID_PRIM_DEV_TYPE: subcat=%u\n", HTON16(val)));
++		} else if (subelt_id == WPS_ID_REQ_DEV_TYPE) {
++			valptr[0] = *subel;
++			valptr[1] = *(subel + 1);
++			WL_DBG(("  attr WPS_ID_REQ_DEV_TYPE: cat=%u\n", HTON16(val)));
++			valptr[0] = *(subel + 6);
++			valptr[1] = *(subel + 7);
++			WL_DBG(("  attr WPS_ID_REQ_DEV_TYPE: subcat=%u\n", HTON16(val)));
++		} else if (subelt_id == WPS_ID_SELECTED_REGISTRAR_CONFIG_METHODS) {
++			valptr[0] = *subel;
++			valptr[1] = *(subel + 1);
++			WL_DBG(("  attr WPS_ID_SELECTED_REGISTRAR_CONFIG_METHODS"
++				": cat=%u\n", HTON16(val)));
++		} else {
++			WL_DBG(("  unknown attr 0x%x\n", subelt_id));
++		}
++
++		subel += subelt_len;
++	}
++}
++
++s32 wl_set_tx_power(struct net_device *dev,
++	enum nl80211_tx_power_setting type, s32 dbm)
++{
++	s32 err = 0;
++	s32 disable = 0;
++	s32 txpwrqdbm;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++
++	/* Make sure radio is off or on as far as software is concerned */
++	disable = WL_RADIO_SW_DISABLE << 16;
++	disable = htod32(disable);
++	err = wldev_ioctl_set(dev, WLC_SET_RADIO, &disable, sizeof(disable));
++	if (unlikely(err)) {
++		WL_ERR(("WLC_SET_RADIO error (%d)\n", err));
++		return err;
++	}
++
++	if (dbm > 0xffff)
++		dbm = 0xffff;
++	txpwrqdbm = dbm * 4;
++	err = wldev_iovar_setbuf_bsscfg(dev, "qtxpower", (void *)&txpwrqdbm,
++		sizeof(txpwrqdbm), cfg->ioctl_buf, WLC_IOCTL_SMLEN, 0,
++		&cfg->ioctl_buf_sync);
++	if (unlikely(err))
++		WL_ERR(("qtxpower error (%d)\n", err));
++	else
++		WL_ERR(("dBm=%d, txpwrqdbm=0x%x\n", dbm, txpwrqdbm));
++
++	return err;
++}
++
++s32 wl_get_tx_power(struct net_device *dev, s32 *dbm)
++{
++	s32 err = 0;
++	s32 txpwrdbm;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++
++	err = wldev_iovar_getbuf_bsscfg(dev, "qtxpower",
++		NULL, 0, cfg->ioctl_buf, WLC_IOCTL_SMLEN, 0, &cfg->ioctl_buf_sync);
++	if (unlikely(err)) {
++		WL_ERR(("error (%d)\n", err));
++		return err;
++	}
++
++	memcpy(&txpwrdbm, cfg->ioctl_buf, sizeof(txpwrdbm));
++	txpwrdbm = dtoh32(txpwrdbm);
++	*dbm = (txpwrdbm & ~WL_TXPWR_OVERRIDE) / 4;
++
++	WL_INFORM(("dBm=%d, txpwrdbm=0x%x\n", *dbm, txpwrdbm));
++
++	return err;
++}
++
++static chanspec_t wl_cfg80211_get_shared_freq(struct wiphy *wiphy)
++{
++	chanspec_t chspec;
++	int cur_band, err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *dev = bcmcfg_to_prmry_ndev(cfg);
++	struct ether_addr bssid;
++	struct wl_bss_info *bss = NULL;
++	s32 bssidx = 0; /* Explicitly set to primary bssidx */
++	char *buf;
++
++	memset(&bssid, 0, sizeof(bssid));
++	if ((err = wldev_ioctl_get(dev, WLC_GET_BSSID, &bssid, sizeof(bssid)))) {
++		/* STA interface is not associated. So start the new interface on a temp
++		 * channel . Later proper channel will be applied by the above framework
++		 * via set_channel (cfg80211 API).
++		 */
++		WL_DBG(("Not associated. Return a temp channel. \n"));
++		cur_band = 0;
++		err = wldev_ioctl_get(dev, WLC_GET_BAND, &cur_band, sizeof(int));
++		if (unlikely(err)) {
++			WL_ERR(("Get band failed\n"));
++			return wl_ch_host_to_driver(cfg, bssidx, WL_P2P_TEMP_CHAN);
++		}
++		if (cur_band == WLC_BAND_5G)
++			return wl_ch_host_to_driver(cfg, bssidx, WL_P2P_TEMP_CHAN_5G);
++		else
++			return wl_ch_host_to_driver(cfg, bssidx, WL_P2P_TEMP_CHAN);
++	}
++
++	buf = kzalloc(WL_EXTRA_BUF_MAX, GFP_KERNEL);
++	if (!buf) {
++		WL_ERR(("buf alloc failed. use temp channel\n"));
++		return wl_ch_host_to_driver(cfg, bssidx, WL_P2P_TEMP_CHAN);
++	}
++
++	*(u32 *)buf = htod32(WL_EXTRA_BUF_MAX);
++	if ((err = wldev_ioctl_get(dev, WLC_GET_BSS_INFO, buf,
++		WL_EXTRA_BUF_MAX))) {
++			WL_ERR(("Failed to get associated bss info, use temp channel \n"));
++			chspec = wl_ch_host_to_driver(cfg, bssidx, WL_P2P_TEMP_CHAN);
++	}
++	else {
++			bss = (struct wl_bss_info *) (buf + 4);
++			chspec =  bss->chanspec;
++
++			WL_DBG(("Valid BSS Found. chanspec:%d \n", chspec));
++	}
++
++	kfree(buf);
++	return chspec;
++}
++
++static bcm_struct_cfgdev *
++wl_cfg80211_add_monitor_if(const char *name)
++{
++#if defined(WL_ENABLE_P2P_IF) || defined(WL_CFG80211_P2P_DEV_IF)
++	WL_INFORM(("wl_cfg80211_add_monitor_if: No more support monitor interface\n"));
++	return ERR_PTR(-EOPNOTSUPP);
++#else
++	struct net_device* ndev = NULL;
++
++	dhd_add_monitor(name, &ndev);
++	WL_INFORM(("wl_cfg80211_add_monitor_if net device returned: 0x%p\n", ndev));
++	return ndev_to_cfgdev(ndev);
++#endif /* WL_ENABLE_P2P_IF || WL_CFG80211_P2P_DEV_IF */
++}
++
++static bcm_struct_cfgdev *
++wl_cfg80211_add_virtual_iface(struct wiphy *wiphy,
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	const char *name,
++#else
++	char *name,
++#endif /* WL_CFG80211_P2P_DEV_IF */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
++	unsigned char name_assign_type,
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) */
++	enum nl80211_iftype type,
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
++	u32 *flags,
++#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) */
++	struct vif_params *params)
++{
++	s32 err = -ENODEV;
++	s32 timeout = -1;
++	s32 wlif_type = -1;
++	s32 mode = 0;
++	s32 val = 0;
++	s32 cfg_type;
++	s32 dhd_mode = 0;
++	chanspec_t chspec;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *primary_ndev;
++	struct net_device *new_ndev;
++	struct ether_addr primary_mac;
++	bcm_struct_cfgdev *new_cfgdev;
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO) || defined(BCMDBUS)
++	s32 up = 1;
++	bool enabled;
++#endif /* BCMSDIO || BCMDBUS */
++#endif /* PROP_TXSTATUS_VSDB */
++	dhd_pub_t *dhd;
++	bool hang_required = false;
++
++	if (!cfg)
++		return ERR_PTR(-EINVAL);
++
++	dhd = (dhd_pub_t *)(cfg->pub);
++
++	/* Use primary I/F for sending cmds down to firmware */
++	primary_ndev = bcmcfg_to_prmry_ndev(cfg);
++
++	if (unlikely(!wl_get_drv_status(cfg, READY, primary_ndev))) {
++		WL_ERR(("device is not ready\n"));
++		return ERR_PTR(-ENODEV);
++	}
++
++	if (!name) {
++		WL_ERR(("Interface name not provided \n"));
++		return ERR_PTR(-EINVAL);
++	}
++
++#ifdef WLTDLS
++	/* disable TDLS if number of connected interfaces is >= 1 */
++	wl_cfg80211_tdls_config(cfg, TDLS_STATE_IF_CREATE, false);
++#endif /* WLTDLS */
++
++	mutex_lock(&cfg->if_sync);
++	WL_DBG(("if name: %s, type: %d\n", name, type));
++	switch (type) {
++	case NL80211_IFTYPE_ADHOC:
++#ifdef WLAIBSS_MCHAN
++		new_cfgdev = bcm_cfg80211_add_ibss_if(wiphy, (char *)name);
++		mutex_unlock(&cfg->if_sync);
++		return new_cfgdev;
++#endif /* WLAIBSS_MCHAN */
++	case NL80211_IFTYPE_AP_VLAN:
++	case NL80211_IFTYPE_WDS:
++	case NL80211_IFTYPE_MESH_POINT:
++		WL_ERR(("Unsupported interface type\n"));
++		mode = WL_MODE_IBSS;
++		err = -EINVAL;
++		goto fail;
++	case NL80211_IFTYPE_MONITOR:
++		new_cfgdev = wl_cfg80211_add_monitor_if(name);
++		mutex_unlock(&cfg->if_sync);
++		return new_cfgdev;
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	case NL80211_IFTYPE_P2P_DEVICE:
++		cfg->down_disc_if = FALSE;
++		new_cfgdev = wl_cfgp2p_add_p2p_disc_if(cfg);
++		mutex_unlock(&cfg->if_sync);
++		return new_cfgdev;
++#endif /* WL_CFG80211_P2P_DEV_IF */
++	case NL80211_IFTYPE_STATION:
++#ifdef WL_VIRTUAL_APSTA
++#ifdef WLAIBSS_MCHAN
++		if (cfg->ibss_cfgdev) {
++			WL_ERR(("AIBSS is already operational. "
++					" AIBSS & DUALSTA can't be used together \n"));
++			err = -ENOMEM;
++			goto fail;
++		}
++#endif /* WLAIBSS_MCHAN */
++
++		if (wl_cfgp2p_vif_created(cfg)) {
++			WL_ERR(("Could not create new iface."
++				"Already one p2p interface is running"));
++			err = -ENOMEM;
++			goto fail;
++		}
++		new_cfgdev = wl_cfg80211_create_iface(cfg->wdev->wiphy,
++			NL80211_IFTYPE_STATION, NULL, name);
++		if (!new_cfgdev) {
++			err = -ENOMEM;
++			goto fail;
++		 } else {
++			mutex_unlock(&cfg->if_sync);
++			return new_cfgdev;
++		}
++#endif /* WL_VIRTUAL_APSTA */
++	case NL80211_IFTYPE_P2P_CLIENT:
++		wlif_type = WL_P2P_IF_CLIENT;
++		mode = WL_MODE_BSS;
++		break;
++	case NL80211_IFTYPE_P2P_GO:
++		wlif_type = WL_P2P_IF_GO;
++		mode = WL_MODE_AP;
++		break;
++#ifdef WL_VIRTUAL_APSTA
++	case NL80211_IFTYPE_AP:
++		dhd->op_mode = DHD_FLAG_HOSTAP_MODE;
++		new_cfgdev = wl_cfg80211_create_iface(cfg->wdev->wiphy,
++			NL80211_IFTYPE_AP, NULL, name);
++		if (!new_cfgdev) {
++			err = -ENOMEM;
++			goto fail;
++		} else {
++			mutex_unlock(&cfg->if_sync);
++			return new_cfgdev;
++		}
++#endif /* WL_VIRTUAL_APSTA */
++	default:
++		WL_ERR(("Unsupported interface type\n"));
++		err = -EINVAL;
++		goto fail;
++	}
++
++	if (cfg->p2p_supported && (wlif_type != -1)) {
++		ASSERT(cfg->p2p); /* ensure expectation of p2p initialization */
++
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO)
++		if (!dhd) {
++			err = -EINVAL;
++			goto fail;
++		}
++#endif 
++#endif /* PROP_TXSTATUS_VSDB */
++
++		if (!cfg->p2p) {
++			WL_ERR(("Failed to start p2p"));
++			err = -ENODEV;
++			goto fail;
++		}
++
++		if (cfg->p2p && !cfg->p2p->on && strstr(name, WL_P2P_INTERFACE_PREFIX)) {
++			p2p_on(cfg) = true;
++			wl_cfgp2p_set_firm_p2p(cfg);
++			wl_cfgp2p_init_discovery(cfg);
++			get_primary_mac(cfg, &primary_mac);
++			wl_cfgp2p_generate_bss_mac(cfg, &primary_mac);
++		}
++
++		strncpy(cfg->p2p->vir_ifname, name, IFNAMSIZ - 1);
++		cfg->p2p->vir_ifname[IFNAMSIZ - 1] = '\0';
++
++		wl_cfg80211_scan_abort(cfg);
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO) || defined(BCMDBUS)
++		if (!cfg->wlfc_on && !disable_proptx) {
++			dhd_wlfc_get_enable(dhd, &enabled);
++			if (!enabled && dhd->op_mode != DHD_FLAG_HOSTAP_MODE &&
++				dhd->op_mode != DHD_FLAG_IBSS_MODE) {
++				dhd_wlfc_init(dhd);
++				err = wldev_ioctl_set(primary_ndev, WLC_UP, &up, sizeof(s32));
++				if (err < 0)
++					WL_ERR(("WLC_UP return err:%d\n", err));
++			}
++			cfg->wlfc_on = true;
++		}
++#endif /* BCMSDIO || BCMDBUS */
++#endif /* PROP_TXSTATUS_VSDB */
++
++		/* Dual p2p doesn't support multiple P2PGO interfaces,
++		 * p2p_go_count is the counter for GO creation
++		 * requests.
++		 */
++		if ((cfg->p2p->p2p_go_count > 0) && (type == NL80211_IFTYPE_P2P_GO)) {
++			WL_ERR(("Fw does not support multiple Go\n"));
++			err = -ENOTSUPP;
++			goto fail;
++		}
++		/* In concurrency case, STA may be already associated in a particular channel.
++		 * so retrieve the current channel of primary interface and then start the virtual
++		 * interface on that.
++		 */
++		 chspec = wl_cfg80211_get_shared_freq(wiphy);
++
++		/* For P2P mode, use P2P-specific driver features to create the
++		 * bss: "cfg p2p_ifadd"
++		 */
++		wl_set_p2p_status(cfg, IF_ADDING);
++		memset(&cfg->if_event_info, 0, sizeof(cfg->if_event_info));
++		cfg_type = wl_cfgp2p_get_conn_idx(cfg);
++		if (cfg_type == BCME_ERROR) {
++			wl_clr_p2p_status(cfg, IF_ADDING);
++			WL_ERR(("Failed to get connection idx for p2p interface\n"));
++			err = -ENOTSUPP;
++			goto fail;
++		}
++		err = wl_cfgp2p_ifadd(cfg, wl_to_p2p_bss_macaddr(cfg, cfg_type),
++			htod32(wlif_type), chspec);
++		if (unlikely(err)) {
++			wl_clr_p2p_status(cfg, IF_ADDING);
++			WL_ERR((" virtual iface add failed (%d) \n", err));
++			err = -ENOMEM;
++			goto fail;
++		}
++
++		timeout = wait_event_interruptible_timeout(cfg->netif_change_event,
++			((wl_get_p2p_status(cfg, IF_ADDING) == false) &&
++			(cfg->if_event_info.valid)),
++			msecs_to_jiffies(MAX_WAIT_TIME));
++
++		if (timeout > 0 && !wl_get_p2p_status(cfg, IF_ADDING) && cfg->if_event_info.valid) {
++			struct wireless_dev *vwdev;
++			int pm_mode = PM_ENABLE;
++			wl_if_event_info *event = &cfg->if_event_info;
++			/* IF_ADD event has come back, we can proceed to to register
++			 * the new interface now, use the interface name provided by caller (thus
++			 * ignore the one from wlc)
++			 */
++			new_ndev = wl_cfg80211_allocate_if(cfg, event->ifidx, cfg->p2p->vir_ifname,
++				event->mac, event->bssidx, event->name);
++			if (new_ndev == NULL) {
++				err = -ENODEV;
++				goto fail;
++			}
++
++			wl_to_p2p_bss_ndev(cfg, cfg_type) = new_ndev;
++			wl_to_p2p_bss_bssidx(cfg, cfg_type) = event->bssidx;
++			vwdev = kzalloc(sizeof(*vwdev), GFP_KERNEL);
++			if (unlikely(!vwdev)) {
++				WL_ERR(("Could not allocate wireless device\n"));
++				err = -ENOMEM;
++				goto fail;
++			}
++			vwdev->wiphy = cfg->wdev->wiphy;
++			WL_INFORM(("virtual interface(%s) is created\n", cfg->p2p->vir_ifname));
++			if (type == NL80211_IFTYPE_P2P_GO) {
++				cfg->p2p->p2p_go_count++;
++			}
++			vwdev->iftype = type;
++			vwdev->netdev = new_ndev;
++			new_ndev->ieee80211_ptr = vwdev;
++			SET_NETDEV_DEV(new_ndev, wiphy_dev(vwdev->wiphy));
++			wl_set_drv_status(cfg, READY, new_ndev);
++			if (wl_config_ifmode(cfg, new_ndev, type) < 0) {
++				WL_ERR(("conf ifmode failed\n"));
++				kfree(vwdev);
++				err = -ENOTSUPP;
++				goto fail;
++			}
++
++			if (wl_cfg80211_register_if(cfg,
++				event->ifidx, new_ndev, FALSE) != BCME_OK) {
++				wl_cfg80211_remove_if(cfg, event->ifidx, new_ndev, FALSE);
++				err = -ENODEV;
++				goto fail;
++			}
++			err = wl_alloc_netinfo(cfg, new_ndev, vwdev, mode, pm_mode, event->bssidx);
++			if (unlikely(err != 0)) {
++				wl_cfg80211_remove_if(cfg, event->ifidx, new_ndev, FALSE);
++				WL_ERR(("Allocation of netinfo failed (%d) \n", err));
++				goto fail;
++			}
++			val = 1;
++			/* Disable firmware roaming for P2P interface  */
++			wldev_iovar_setint(new_ndev, "roam_off", val);
++			wldev_iovar_setint(new_ndev, "bcn_timeout", dhd->conf->bcn_timeout);
++#ifdef WL11ULB
++			if (cfg->p2p_wdev && is_p2p_group_iface(new_ndev->ieee80211_ptr)) {
++				u32 ulb_bw = wl_cfg80211_get_ulb_bw(cfg, cfg->p2p_wdev);
++				if (ulb_bw) {
++					/* Apply ULB BW settings on the newly spawned interface */
++					WL_DBG(("[ULB] Applying ULB BW for the newly"
++						"created P2P interface \n"));
++					if (wl_cfg80211_set_ulb_bw(new_ndev,
++						ulb_bw, new_ndev->name) < 0) {
++						/*
++						 * If ulb_bw set failed, fail the iface creation.
++						 * wl_dealloc_netinfo_by_wdev will be called by the
++						 * unregister notifier.
++						 */
++						wl_cfg80211_remove_if(cfg,
++							event->ifidx, new_ndev, FALSE);
++						err = -EINVAL;
++						goto fail;
++					}
++				}
++			}
++#endif /* WL11ULB */
++
++			if (mode != WL_MODE_AP)
++				wldev_iovar_setint(new_ndev, "buf_key_b4_m4", 1);
++
++			WL_ERR((" virtual interface(%s) is "
++				"created net attach done\n", cfg->p2p->vir_ifname));
++			if (mode == WL_MODE_AP)
++				wl_set_drv_status(cfg, CONNECTED, new_ndev);
++#ifdef SUPPORT_AP_POWERSAVE
++			if (mode == WL_MODE_AP) {
++				dhd_set_ap_powersave(dhd, 0, TRUE);
++			}
++#endif /* SUPPORT_AP_POWERSAVE */
++			if (type == NL80211_IFTYPE_P2P_CLIENT)
++				dhd_mode = DHD_FLAG_P2P_GC_MODE;
++			else if (type == NL80211_IFTYPE_P2P_GO)
++				dhd_mode = DHD_FLAG_P2P_GO_MODE;
++			DNGL_FUNC(dhd_cfg80211_set_p2p_info, (cfg, dhd_mode));
++			/* reinitialize completion to clear previous count */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0))
++			INIT_COMPLETION(cfg->iface_disable);
++#else
++			init_completion(&cfg->iface_disable);
++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0) */
++#ifdef SUPPORT_SET_CAC
++			wl_cfg80211_set_cac(cfg, 0);
++#endif /* SUPPORT_SET_CAC */
++			mutex_unlock(&cfg->if_sync);
++			return ndev_to_cfgdev(new_ndev);
++		} else {
++			wl_clr_p2p_status(cfg, IF_ADDING);
++			WL_ERR((" virtual interface(%s) is not created \n", cfg->p2p->vir_ifname));
++
++			WL_ERR(("left timeout : %d\n", timeout));
++			WL_ERR(("IF_ADDING status : %d\n", wl_get_p2p_status(cfg, IF_ADDING)));
++			WL_ERR(("event valid : %d\n", cfg->if_event_info.valid));
++
++			wl_clr_p2p_status(cfg, GO_NEG_PHASE);
++			wl_set_p2p_status(cfg, IF_DELETING);
++
++			hang_required = true;
++			if ((err = wl_cfgp2p_ifdel(cfg,
++					wl_to_p2p_bss_macaddr(cfg,
++					cfg_type))) == BCME_OK) {
++				timeout = wait_event_interruptible_timeout(cfg->netif_change_event,
++					((wl_get_p2p_status(cfg, IF_DELETING) == false) &&
++					(cfg->if_event_info.valid)),
++					msecs_to_jiffies(MAX_WAIT_TIME));
++				if (timeout > 0 && !wl_get_p2p_status(cfg, IF_DELETING) &&
++					cfg->if_event_info.valid) {
++					hang_required = false;
++					WL_ERR(("IFDEL operation done\n"));
++				} else {
++					WL_ERR(("IFDEL didn't complete properly\n"));
++				}
++				err = -ENODEV;
++#ifdef SUPPORT_SET_CAC
++				wl_cfg80211_set_cac(cfg, 1);
++#endif /* SUPPORT_SET_CAC */
++			} else {
++				WL_ERR(("IFDEL operation failed, error code = %d\n", err));
++			}
++
++			memset(cfg->p2p->vir_ifname, '\0', IFNAMSIZ);
++			wl_to_p2p_bss_bssidx(cfg, cfg_type) = -1;
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO) || defined(BCMDBUS)
++			dhd_wlfc_get_enable(dhd, &enabled);
++			if (enabled && cfg->wlfc_on && dhd->op_mode != DHD_FLAG_HOSTAP_MODE &&
++				dhd->op_mode != DHD_FLAG_IBSS_MODE && dhd->conf->disable_proptx!=0) {
++				dhd_wlfc_deinit(dhd);
++				cfg->wlfc_on = false;
++			}
++#endif /* BCMSDIO || BCMDBUS */
++#endif /* PROP_TXSTATUS_VSDB */
++		}
++	}
++
++fail:
++	mutex_unlock(&cfg->if_sync);
++	if (err) {
++#ifdef WLTDLS
++		/* Enable back TDLS on failure */
++		wl_cfg80211_tdls_config(cfg, TDLS_STATE_IF_DELETE, false);
++#endif /* WLTDLS */
++		if (err != -ENOTSUPP) {
++#if defined(BCMPCIE) && defined(DHD_FW_COREDUMP)
++			if (dhd->memdump_enabled) {
++				/* Load the dongle side dump to host
++				 * memory and then BUG_ON()
++				 */
++				dhd->memdump_type = DUMP_TYPE_HANG_ON_IFACE_OP_FAIL;
++				dhd_bus_mem_dump(dhd);
++			}
++#endif /* BCMPCIE && DHD_FW_COREDUMP */
++			if (hang_required) {
++				/* Notify the user space to recover */
++				struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++				WL_ERR(("if add failed, error %d, sent HANG event to %s\n",
++					err, ndev->name));
++				dhd->hang_reason = HANG_REASON_IFACE_OP_FAILURE;
++				net_os_send_hang_message(ndev);
++			}
++		}
++	}
++	return ERR_PTR(err);
++}
++
++static s32
++wl_cfg80211_del_virtual_iface(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev)
++{
++	struct net_device *dev = NULL;
++	struct ether_addr p2p_mac;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 timeout = -1;
++	s32 ret = 0;
++	s32 index = -1;
++	s32 type = -1;
++#if defined(CUSTOM_SET_CPUCORE) || defined(DHD_HANG_SEND_UP_TEST)
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++#endif /* CUSTOM_SET_CPUCORE || DHD_HANG_SEND_UP_TEST */
++	WL_DBG(("Enter\n"));
++
++	memset(&p2p_mac, 0, sizeof(struct ether_addr));
++#ifdef CUSTOM_SET_CPUCORE
++	dhd->chan_isvht80 &= ~DHD_FLAG_P2P_MODE;
++	if (!(dhd->chan_isvht80))
++		dhd_set_cpucore(dhd, FALSE);
++#endif /* CUSTOM_SET_CPUCORE */
++	mutex_lock(&cfg->if_sync);
++#ifdef WL_CFG80211_P2P_DEV_IF
++	if (cfgdev->iftype == NL80211_IFTYPE_P2P_DEVICE) {
++		if (dhd_download_fw_on_driverload) {
++			ret = wl_cfgp2p_del_p2p_disc_if(cfgdev, cfg);
++		} else {
++			cfg->down_disc_if = TRUE;
++			ret = 0;
++		}
++		mutex_unlock(&cfg->if_sync);
++		return ret;
++	}
++#endif /* WL_CFG80211_P2P_DEV_IF */
++	dev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++#ifdef WLAIBSS_MCHAN
++	if (cfgdev == cfg->ibss_cfgdev) {
++		ret = bcm_cfg80211_del_ibss_if(wiphy, cfgdev);
++		goto done;
++	}
++#endif /* WLAIBSS_MCHAN */
++
++	if ((index = wl_get_bssidx_by_wdev(cfg, cfgdev_to_wdev(cfgdev))) < 0) {
++		WL_ERR(("Find p2p index from wdev failed\n"));
++		ret = -ENODEV;
++		goto done;
++	}
++	if ((cfg->p2p_supported) && index && (wl_cfgp2p_find_type(cfg, index, &type) == BCME_OK)) {
++		/* Handle P2P Interace del */
++		memcpy(p2p_mac.octet, wl_to_p2p_bss_macaddr(cfg, type).octet, ETHER_ADDR_LEN);
++
++		/* Clear GO_NEG_PHASE bit to take care of GO-NEG-FAIL cases
++		 */
++		WL_DBG(("P2P: GO_NEG_PHASE status cleared "));
++		wl_clr_p2p_status(cfg, GO_NEG_PHASE);
++		if (wl_cfgp2p_vif_created(cfg)) {
++			if (wl_get_drv_status(cfg, SCANNING, dev)) {
++				wl_notify_escan_complete(cfg, dev, true, true);
++			}
++			/* Delete pm_enable_work */
++			wl_add_remove_pm_enable_work(cfg, WL_PM_WORKQ_DEL);
++
++			/* for GC */
++			if (wl_get_drv_status(cfg, DISCONNECTING, dev) &&
++				(wl_get_mode_by_netdev(cfg, dev) != WL_MODE_AP)) {
++				WL_ERR(("Wait for Link Down event for GC !\n"));
++				wait_for_completion_timeout
++					(&cfg->iface_disable, msecs_to_jiffies(500));
++			}
++
++			memset(&cfg->if_event_info, 0, sizeof(cfg->if_event_info));
++			wl_set_p2p_status(cfg, IF_DELETING);
++			DNGL_FUNC(dhd_cfg80211_clean_p2p_info, (cfg));
++
++			/* for GO */
++			if (wl_get_mode_by_netdev(cfg, dev) == WL_MODE_AP) {
++				wl_add_remove_eventmsg(dev, WLC_E_PROBREQ_MSG, false);
++				cfg->p2p->p2p_go_count--;
++				/* disable interface before bsscfg free */
++				ret = wl_cfgp2p_ifdisable(cfg, &p2p_mac);
++				/* if fw doesn't support "ifdis",
++				   do not wait for link down of ap mode
++				 */
++				if (ret == 0) {
++					WL_ERR(("Wait for Link Down event for GO !!!\n"));
++					wait_for_completion_timeout(&cfg->iface_disable,
++						msecs_to_jiffies(500));
++				} else if (ret != BCME_UNSUPPORTED) {
++					msleep(300);
++				}
++			}
++			wl_cfg80211_clear_per_bss_ies(cfg, index);
++
++			if (wl_get_mode_by_netdev(cfg, dev) != WL_MODE_AP)
++				wldev_iovar_setint(dev, "buf_key_b4_m4", 0);
++			memcpy(p2p_mac.octet, wl_to_p2p_bss_macaddr(cfg, type).octet,
++			ETHER_ADDR_LEN);
++			CFGP2P_INFO(("primary idx %d : cfg p2p_ifdis "MACDBG"\n",
++			       dev->ifindex, MAC2STRDBG(p2p_mac.octet)));
++
++			/* delete interface after link down */
++			ret = wl_cfgp2p_ifdel(cfg, &p2p_mac);
++#if defined(DHD_HANG_SEND_UP_TEST)
++			if (ret != BCME_OK ||
++				dhd->req_hang_type == HANG_REASON_IFACE_OP_FAILURE)
++#else /* DHD_HANG_SEND_UP_TEST */
++			if (ret != BCME_OK)
++#endif /* DHD_HANG_SEND_UP_TEST */
++			{
++				struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++				dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++
++				WL_ERR(("p2p_ifdel failed, error %d, sent HANG event to %s\n",
++					ret, ndev->name));
++#if defined(BCMPCIE) && defined(DHD_FW_COREDUMP)
++				if (dhd->memdump_enabled) {
++					/* Load the dongle side dump to host
++					 * memory and then BUG_ON()
++					 */
++					dhd->memdump_type = DUMP_TYPE_HANG_ON_IFACE_OP_FAIL;
++					dhd_bus_mem_dump(dhd);
++				}
++#endif /* BCMPCIE && DHD_FW_COREDUMP */
++				dhd->hang_reason = HANG_REASON_IFACE_OP_FAILURE;
++				net_os_send_hang_message(ndev);
++			} else {
++				/* Wait for IF_DEL operation to be finished */
++				timeout = wait_event_interruptible_timeout(cfg->netif_change_event,
++					((wl_get_p2p_status(cfg, IF_DELETING) == false) &&
++					(cfg->if_event_info.valid)),
++					msecs_to_jiffies(MAX_WAIT_TIME));
++				if (timeout > 0 && !wl_get_p2p_status(cfg, IF_DELETING) &&
++					cfg->if_event_info.valid) {
++
++					WL_DBG(("IFDEL operation done\n"));
++					wl_cfg80211_handle_ifdel(cfg, &cfg->if_event_info, dev);
++				} else {
++					WL_ERR(("IFDEL didn't complete properly\n"));
++				}
++#ifdef SUPPORT_SET_CAC
++				wl_cfg80211_set_cac(cfg, 1);
++#endif /* SUPPORT_SET_CAC */
++			}
++
++			ret = dhd_del_monitor(dev);
++			if (wl_get_mode_by_netdev(cfg, dev) == WL_MODE_AP) {
++				DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_CANCEL((dhd_pub_t *)(cfg->pub));
++			}
++		}
++	} else if ((dev->ieee80211_ptr->iftype == NL80211_IFTYPE_AP) ||
++		(dev->ieee80211_ptr->iftype == NL80211_IFTYPE_STATION)) {
++#ifdef WL_VIRTUAL_APSTA
++		ret = wl_cfg80211_del_iface(wiphy, cfgdev);
++#else
++		WL_ERR(("Virtual APSTA not supported!\n"));
++#endif /* WL_VIRTUAL_APSTA */
++	}
++
++done:
++	mutex_unlock(&cfg->if_sync);
++#ifdef WLTDLS
++	if (ret == BCME_OK) {
++		/* If interface del is success, try enabling back TDLS */
++		wl_cfg80211_tdls_config(cfg, TDLS_STATE_IF_DELETE, false);
++	}
++#endif /* WLTDLS */
++	return ret;
++}
++
++static s32
++wl_cfg80211_change_virtual_iface(struct wiphy *wiphy, struct net_device *ndev,
++	enum nl80211_iftype type,
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
++	u32 *flags,
++#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) */
++	struct vif_params *params)
++{
++	s32 ap = 0;
++	s32 infra_ibss = 1;
++	s32 wlif_type;
++	s32 mode = 0;
++	s32 err = BCME_OK;
++	s32 index;
++	s32 conn_idx = -1;
++	chanspec_t chspec;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++
++	mutex_lock(&cfg->if_sync);
++	WL_DBG(("Enter type %d\n", type));
++	switch (type) {
++	case NL80211_IFTYPE_MONITOR:
++	case NL80211_IFTYPE_WDS:
++#ifndef WLMESH_CFG80211
++	case NL80211_IFTYPE_MESH_POINT:
++#endif /* WLMESH_CFG80211 */
++		ap = 1;
++		WL_ERR(("type (%d) : currently we do not support this type\n",
++			type));
++		break;
++#ifdef WLMESH_CFG80211
++	case NL80211_IFTYPE_MESH_POINT:
++		infra_ibss = WL_BSSTYPE_MESH;
++		break;
++#endif /* WLMESH_CFG80211 */
++	case NL80211_IFTYPE_ADHOC:
++		mode = WL_MODE_IBSS;
++		infra_ibss = 0;
++		break;
++	case NL80211_IFTYPE_STATION:
++	case NL80211_IFTYPE_P2P_CLIENT:
++		if (ndev->ieee80211_ptr->iftype == NL80211_IFTYPE_AP) {
++			s32 bssidx = wl_get_bssidx_by_wdev(cfg, ndev->ieee80211_ptr);
++			if (bssidx < 0) {
++				/* validate bssidx */
++				WL_ERR(("Wrong bssidx! \n"));
++				err = -EINVAL;
++				goto error;
++			}
++			WL_DBG(("del interface. bssidx:%d", bssidx));
++			/* Downgrade role from AP to STA */
++			if ((err = wl_cfg80211_add_del_bss(cfg, ndev,
++					bssidx, NL80211_IFTYPE_STATION, 0, NULL)) < 0) {
++				WL_ERR(("AP-STA Downgrade failed \n"));
++				err = -EINVAL;
++				goto error;
++			}
++		}
++		mode = WL_MODE_BSS;
++		break;
++	case NL80211_IFTYPE_AP:
++		dhd->op_mode |= DHD_FLAG_HOSTAP_MODE;
++		/* intentional fall through */
++	case NL80211_IFTYPE_AP_VLAN:
++	case NL80211_IFTYPE_P2P_GO:
++		mode = WL_MODE_AP;
++		ap = 1;
++		break;
++	default:
++		err = -EINVAL;
++		goto error;
++	}
++
++	if (!dhd) {
++		err = -EINVAL;
++		goto error;
++	}
++	if (ap) {
++		wl_set_mode_by_netdev(cfg, ndev, mode);
++		if (is_p2p_group_iface(ndev->ieee80211_ptr) &&
++			cfg->p2p && wl_cfgp2p_vif_created(cfg)) {
++			WL_DBG(("p2p_vif_created p2p_on (%d)\n", p2p_on(cfg)));
++			wl_notify_escan_complete(cfg, ndev, true, true);
++
++			/* Dual p2p doesn't support multiple P2PGO interfaces,
++			 * p2p_go_count is the counter for GO creation
++			 * requests.
++			 */
++			if ((cfg->p2p->p2p_go_count > 0) && (type == NL80211_IFTYPE_P2P_GO)) {
++				wl_set_mode_by_netdev(cfg, ndev, WL_MODE_BSS);
++				WL_ERR(("Fw does not support multiple GO\n"));
++				err = BCME_ERROR;
++				goto error;
++			}
++			/* In concurrency case, STA may be already associated in a particular
++			 * channel. so retrieve the current channel of primary interface and
++			 * then start the virtual interface on that.
++			 */
++			chspec = wl_cfg80211_get_shared_freq(wiphy);
++			index = wl_get_bssidx_by_wdev(cfg, ndev->ieee80211_ptr);
++			if (index < 0) {
++				WL_ERR(("Find p2p index from ndev(%p) failed\n", ndev));
++				err = BCME_ERROR;
++				goto error;
++			}
++			if (wl_cfgp2p_find_type(cfg, index, &conn_idx) != BCME_OK) {
++				err = BCME_ERROR;
++				goto error;
++			}
++
++			wlif_type = WL_P2P_IF_GO;
++			WL_MSG(ndev->name, "ap (%d), infra_ibss (%d), iftype (%d) conn_idx (%d)\n",
++				ap, infra_ibss, type, conn_idx);
++			wl_set_p2p_status(cfg, IF_CHANGING);
++			wl_clr_p2p_status(cfg, IF_CHANGED);
++			wl_cfgp2p_ifchange(cfg, wl_to_p2p_bss_macaddr(cfg, conn_idx),
++				htod32(wlif_type), chspec, conn_idx);
++			wait_event_interruptible_timeout(cfg->netif_change_event,
++				(wl_get_p2p_status(cfg, IF_CHANGED) == true),
++				msecs_to_jiffies(MAX_WAIT_TIME));
++			wl_set_mode_by_netdev(cfg, ndev, mode);
++			dhd->op_mode &= ~DHD_FLAG_P2P_GC_MODE;
++			dhd->op_mode |= DHD_FLAG_P2P_GO_MODE;
++			wl_clr_p2p_status(cfg, IF_CHANGING);
++			wl_clr_p2p_status(cfg, IF_CHANGED);
++			if (mode == WL_MODE_AP)
++				wl_set_drv_status(cfg, CONNECTED, ndev);
++#ifdef SUPPORT_AP_POWERSAVE
++			dhd_set_ap_powersave(dhd, 0, TRUE);
++#endif /* SUPPORT_AP_POWERSAVE */
++		} else if ((type == NL80211_IFTYPE_AP) &&
++			!wl_get_drv_status(cfg, AP_CREATED, ndev)) {
++#if 0
++			err = wl_cfg80211_set_ap_role(cfg, ndev);
++			if (unlikely(err)) {
++				WL_ERR(("set ap role failed!\n"));
++				goto error;
++			}
++#else
++			wl_set_drv_status(cfg, AP_CREATING, ndev);
++#endif
++		} else {
++			WL_ERR(("Cannot change the interface for GO or SOFTAP\n"));
++			err = -EINVAL;
++			goto error;
++		}
++	} else {
++		/* P2P GO interface deletion is handled on the basis of role type (AP).
++		 * So avoid changing role for p2p type.
++		 */
++		if (ndev->ieee80211_ptr->iftype != NL80211_IFTYPE_P2P_GO)
++			wl_set_mode_by_netdev(cfg, ndev, mode);
++		WL_DBG(("Change_virtual_iface for transition from GO/AP to client/STA\n"));
++#ifdef SUPPORT_AP_POWERSAVE
++		dhd_set_ap_powersave(dhd, 0, FALSE);
++#endif /* SUPPORT_AP_POWERSAVE */
++	}
++
++	if (!infra_ibss) {
++		err = wldev_ioctl_set(ndev, WLC_SET_INFRA, &infra_ibss, sizeof(s32));
++		if (err < 0) {
++			WL_ERR(("SET INFRA/IBSS  error %d\n", err));
++			err = -EINVAL;
++			goto error;
++		}
++	}
++
++	WL_DBG(("Setting iftype to %d \n", type));
++	ndev->ieee80211_ptr->iftype = type;
++error:
++	mutex_unlock(&cfg->if_sync);
++	return err;
++}
++
++s32
++wl_cfg80211_notify_ifadd(struct net_device *dev, int ifidx, char *name, uint8 *mac, uint8 bssidx)
++{
++	bool ifadd_expected = FALSE;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++
++	/* P2P may send WLC_E_IF_ADD and/or WLC_E_IF_CHANGE during IF updating ("p2p_ifupd")
++	 * redirect the IF_ADD event to ifchange as it is not a real "new" interface
++	 */
++	if (wl_get_p2p_status(cfg, IF_CHANGING))
++		return wl_cfg80211_notify_ifchange(dev, ifidx, name, mac, bssidx);
++
++	/* Okay, we are expecting IF_ADD (as IF_ADDING is true) */
++	if (wl_get_p2p_status(cfg, IF_ADDING)) {
++		ifadd_expected = TRUE;
++		wl_clr_p2p_status(cfg, IF_ADDING);
++	} else if (cfg->bss_pending_op) {
++		ifadd_expected = TRUE;
++		cfg->bss_pending_op = FALSE;
++	}
++
++	if (ifadd_expected) {
++		wl_if_event_info *if_event_info = &cfg->if_event_info;
++
++		if_event_info->valid = TRUE;
++		if_event_info->ifidx = ifidx;
++		if_event_info->bssidx = bssidx;
++		strncpy(if_event_info->name, name, IFNAMSIZ);
++		if_event_info->name[IFNAMSIZ] = '\0';
++		if (mac)
++			memcpy(if_event_info->mac, mac, ETHER_ADDR_LEN);
++		wake_up_interruptible(&cfg->netif_change_event);
++		return BCME_OK;
++	}
++
++	return BCME_ERROR;
++}
++
++s32
++wl_cfg80211_notify_ifdel(struct net_device *dev, int ifidx, char *name, uint8 *mac, uint8 bssidx)
++{
++	bool ifdel_expected = FALSE;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	wl_if_event_info *if_event_info = &cfg->if_event_info;
++
++	if (wl_get_p2p_status(cfg, IF_DELETING)) {
++		ifdel_expected = TRUE;
++		wl_clr_p2p_status(cfg, IF_DELETING);
++	} else if (cfg->bss_pending_op) {
++		ifdel_expected = TRUE;
++		cfg->bss_pending_op = FALSE;
++	}
++
++	if (ifdel_expected) {
++		if_event_info->valid = TRUE;
++		if_event_info->ifidx = ifidx;
++		if_event_info->bssidx = bssidx;
++		wake_up_interruptible(&cfg->netif_change_event);
++		return BCME_OK;
++	}
++
++	return BCME_ERROR;
++}
++
++s32
++wl_cfg80211_notify_ifchange(struct net_device * dev, int ifidx, char *name, uint8 *mac,
++	uint8 bssidx)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++
++	if (wl_get_p2p_status(cfg, IF_CHANGING)) {
++		wl_set_p2p_status(cfg, IF_CHANGED);
++		wake_up_interruptible(&cfg->netif_change_event);
++		return BCME_OK;
++	}
++
++	return BCME_ERROR;
++}
++
++static s32 wl_cfg80211_handle_ifdel(struct bcm_cfg80211 *cfg, wl_if_event_info *if_event_info,
++	struct net_device* ndev)
++{
++	s32 type = -1;
++	s32 bssidx = -1;
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO) || defined(BCMDBUS)
++	dhd_pub_t *dhd =  (dhd_pub_t *)(cfg->pub);
++	bool enabled;
++#endif /* BCMSDIO || BCMDBUS */
++#endif /* PROP_TXSTATUS_VSDB */
++
++	bssidx = if_event_info->bssidx;
++	if (bssidx != wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_CONNECTION1) &&
++		bssidx != wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_CONNECTION2)) {
++		WL_ERR(("got IF_DEL for if %d, not owned by cfg driver\n", bssidx));
++		return BCME_ERROR;
++	}
++
++	if (p2p_is_on(cfg) && wl_cfgp2p_vif_created(cfg)) {
++		if (cfg->scan_request && (cfg->escan_info.ndev == ndev)) {
++			/* Abort any pending scan requests */
++			cfg->escan_info.escan_state = WL_ESCAN_STATE_IDLE;
++			WL_DBG(("ESCAN COMPLETED\n"));
++			wl_notify_escan_complete(cfg, cfg->escan_info.ndev, true, false);
++		}
++
++		memset(cfg->p2p->vir_ifname, '\0', IFNAMSIZ);
++		if (wl_cfgp2p_find_type(cfg, bssidx, &type) == BCME_OK) {
++			/* Update P2P data */
++			wl_clr_drv_status(cfg, CONNECTED, wl_to_p2p_bss_ndev(cfg, type));
++			wl_to_p2p_bss_ndev(cfg, type) = NULL;
++			wl_to_p2p_bss_bssidx(cfg, type) = -1;
++		} else if (wl_get_bssidx_by_wdev(cfg, ndev->ieee80211_ptr) < 0) {
++			WL_ERR(("bssidx not known for the given ndev as per net_info data \n"));
++			return BCME_ERROR;
++		}
++
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO) || defined(BCMDBUS)
++		dhd_wlfc_get_enable(dhd, &enabled);
++		if (enabled && cfg->wlfc_on && dhd->op_mode != DHD_FLAG_HOSTAP_MODE &&
++			dhd->op_mode != DHD_FLAG_IBSS_MODE && dhd->conf->disable_proptx!=0) {
++			dhd_wlfc_deinit(dhd);
++			cfg->wlfc_on = false;
++		}
++#endif /* BCMSDIO || BCMDBUS */
++#endif /* PROP_TXSTATUS_VSDB */
++	}
++
++	dhd_net_if_lock(ndev);
++	wl_cfg80211_remove_if(cfg, if_event_info->ifidx, ndev, FALSE);
++	dhd_net_if_unlock(ndev);
++
++	return BCME_OK;
++}
++
++/* Find listen channel */
++static s32 wl_find_listen_channel(struct bcm_cfg80211 *cfg,
++	const u8 *ie, u32 ie_len)
++{
++	wifi_p2p_ie_t *p2p_ie;
++	u8 *end, *pos;
++	s32 listen_channel;
++
++/* unfortunately const cast required here - function is
++ * a callback so its signature must not be changed
++ * and cascade of changing wl_cfgp2p_find_p2pie
++ * causes need for const cast in other places
++ */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++	pos = (u8 *)ie;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	p2p_ie = wl_cfgp2p_find_p2pie(pos, ie_len);
++
++	if (p2p_ie == NULL)
++		return 0;
++
++	pos = p2p_ie->subelts;
++	end = p2p_ie->subelts + (p2p_ie->len - 4);
++
++	CFGP2P_DBG((" found p2p ie ! lenth %d \n",
++		p2p_ie->len));
++
++	while (pos < end) {
++		uint16 attr_len;
++		if (pos + 2 >= end) {
++			CFGP2P_DBG((" -- Invalid P2P attribute"));
++			return 0;
++		}
++		attr_len = ((uint16) (((pos + 1)[1] << 8) | (pos + 1)[0]));
++
++		if (pos + 3 + attr_len > end) {
++			CFGP2P_DBG(("P2P: Attribute underflow "
++				   "(len=%u left=%d)",
++				   attr_len, (int) (end - pos - 3)));
++			return 0;
++		}
++
++		/* if Listen Channel att id is 6 and the vailue is valid,
++		 * return the listen channel
++		 */
++		if (pos[0] == 6) {
++			/* listen channel subel length format
++			 * 1(id) + 2(len) + 3(country) + 1(op. class) + 1(chan num)
++			 */
++			listen_channel = pos[1 + 2 + 3 + 1];
++
++			if (listen_channel == SOCIAL_CHAN_1 ||
++				listen_channel == SOCIAL_CHAN_2 ||
++				listen_channel == SOCIAL_CHAN_3) {
++				CFGP2P_DBG((" Found my Listen Channel %d \n", listen_channel));
++				return listen_channel;
++			}
++		}
++		pos += 3 + attr_len;
++	}
++	return 0;
++}
++
++static void wl_scan_prep(struct bcm_cfg80211 *cfg, struct wl_scan_params *params,
++	struct cfg80211_scan_request *request)
++{
++	u32 n_ssids;
++	u32 n_channels;
++	u16 channel;
++	chanspec_t chanspec;
++	s32 i = 0, j = 0, offset;
++	char *ptr;
++	wlc_ssid_t ssid;
++	struct wireless_dev *wdev;
++
++	memcpy(&params->bssid, &ether_bcast, ETHER_ADDR_LEN);
++	params->bss_type = DOT11_BSSTYPE_ANY;
++	params->scan_type = 0;
++	params->nprobes = -1;
++	params->active_time = -1;
++	params->passive_time = -1;
++	params->home_time = -1;
++	params->channel_num = 0;
++	memset(&params->ssid, 0, sizeof(wlc_ssid_t));
++
++	WL_SCAN(("Preparing Scan request\n"));
++	WL_SCAN(("nprobes=%d\n", params->nprobes));
++	WL_SCAN(("active_time=%d\n", params->active_time));
++	WL_SCAN(("passive_time=%d\n", params->passive_time));
++	WL_SCAN(("home_time=%d\n", params->home_time));
++	WL_SCAN(("scan_type=%d\n", params->scan_type));
++
++	params->nprobes = htod32(params->nprobes);
++	params->active_time = htod32(params->active_time);
++	params->passive_time = htod32(params->passive_time);
++	params->home_time = htod32(params->home_time);
++
++	/* if request is null just exit so it will be all channel broadcast scan */
++	if (!request)
++		return;
++
++	n_ssids = request->n_ssids;
++	n_channels = request->n_channels;
++
++	/* Copy channel array if applicable */
++	WL_SCAN(("### List of channelspecs to scan ###\n"));
++	if (n_channels > 0) {
++		for (i = 0; i < n_channels; i++) {
++			channel = ieee80211_frequency_to_channel(request->channels[i]->center_freq);
++			/* SKIP DFS channels for Secondary interface */
++			if ((cfg->escan_info.ndev != bcmcfg_to_prmry_ndev(cfg)) &&
++				(request->channels[i]->flags &
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
++				(IEEE80211_CHAN_RADAR | IEEE80211_CHAN_PASSIVE_SCAN)))
++#else
++				(IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR)))
++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0) */
++				continue;
++			if (!dhd_conf_match_channel(cfg->pub, channel))
++				continue;
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++			wdev = request->wdev;
++#else
++			wdev = request->dev->ieee80211_ptr;
++#endif /* WL_CFG80211_P2P_DEV_IF */
++			chanspec = wl_cfg80211_ulb_get_min_bw_chspec(cfg, wdev, -1);
++			if (chanspec == INVCHANSPEC) {
++				WL_ERR(("Invalid chanspec! Skipping channel\n"));
++				continue;
++			}
++
++			if (request->channels[i]->band == IEEE80211_BAND_2GHZ) {
++				chanspec |= WL_CHANSPEC_BAND_2G;
++			} else {
++				chanspec |= WL_CHANSPEC_BAND_5G;
++			}
++			params->channel_list[j] = channel;
++			params->channel_list[j] &= WL_CHANSPEC_CHAN_MASK;
++			params->channel_list[j] |= chanspec;
++			WL_SCAN(("Chan : %d, Channel spec: %x \n",
++				channel, params->channel_list[j]));
++			params->channel_list[j] = wl_chspec_host_to_driver(params->channel_list[j]);
++			j++;
++		}
++	} else {
++		WL_SCAN(("Scanning all channels\n"));
++	}
++	n_channels = j;
++	/* Copy ssid array if applicable */
++	WL_SCAN(("### List of SSIDs to scan ###\n"));
++	if (n_ssids > 0) {
++		offset = offsetof(wl_scan_params_t, channel_list) + n_channels * sizeof(u16);
++		offset = roundup(offset, sizeof(u32));
++		ptr = (char*)params + offset;
++		for (i = 0; i < n_ssids; i++) {
++			memset(&ssid, 0, sizeof(wlc_ssid_t));
++			ssid.SSID_len = MIN(request->ssids[i].ssid_len, DOT11_MAX_SSID_LEN);
++			memcpy(ssid.SSID, request->ssids[i].ssid, ssid.SSID_len);
++			if (!ssid.SSID_len)
++				WL_SCAN(("%d: Broadcast scan\n", i));
++			else
++				WL_SCAN(("%d: scan  for  %s size =%d\n", i,
++				ssid.SSID, ssid.SSID_len));
++			memcpy(ptr, &ssid, sizeof(wlc_ssid_t));
++			ptr += sizeof(wlc_ssid_t);
++		}
++	} else {
++		WL_SCAN(("Broadcast scan\n"));
++	}
++	/* Adding mask to channel numbers */
++	params->channel_num =
++	        htod32((n_ssids << WL_SCAN_PARAMS_NSSID_SHIFT) |
++	               (n_channels & WL_SCAN_PARAMS_COUNT_MASK));
++
++	if (n_channels == 1) {
++		params->active_time = htod32(WL_SCAN_CONNECT_DWELL_TIME_MS);
++		params->nprobes = htod32(params->active_time / WL_SCAN_JOIN_PROBE_INTERVAL_MS);
++	}
++}
++
++static s32
++wl_get_valid_channels(struct net_device *ndev, u8 *valid_chan_list, s32 size)
++{
++	wl_uint32_list_t *list;
++	s32 err = BCME_OK;
++	if (valid_chan_list == NULL || size <= 0)
++		return -ENOMEM;
++
++	memset(valid_chan_list, 0, size);
++	list = (wl_uint32_list_t *)(void *) valid_chan_list;
++	list->count = htod32(WL_NUMCHANNELS);
++	err = wldev_ioctl_get(ndev, WLC_GET_VALID_CHANNELS, valid_chan_list, size);
++	if (err != 0) {
++		WL_ERR(("get channels failed with %d\n", err));
++	}
++
++	return err;
++}
++
++#if defined(USE_INITIAL_SHORT_DWELL_TIME)
++#define FIRST_SCAN_ACTIVE_DWELL_TIME_MS 40
++bool g_first_broadcast_scan = TRUE;
++#endif 
++
++static s32
++wl_run_escan(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	struct cfg80211_scan_request *request, uint16 action)
++{
++	s32 err = BCME_OK;
++	u32 n_channels;
++	u32 n_ssids;
++	s32 params_size = (WL_SCAN_PARAMS_FIXED_SIZE + OFFSETOF(wl_escan_params_t, params));
++	wl_escan_params_t *params = NULL;
++	u8 chan_buf[sizeof(u32)*(WL_NUMCHANNELS + 1)];
++	u32 num_chans = 0;
++	s32 channel;
++	u32 n_valid_chan;
++	s32 search_state = WL_P2P_DISC_ST_SCAN;
++	u32 i, j, n_nodfs = 0;
++	u16 *default_chan_list = NULL;
++	wl_uint32_list_t *list;
++	s32 bssidx = -1;
++	struct net_device *dev = NULL;
++#if defined(USE_INITIAL_SHORT_DWELL_TIME)
++	bool is_first_init_2g_scan = false;
++#endif 
++	p2p_scan_purpose_t	p2p_scan_purpose = P2P_SCAN_PURPOSE_MIN;
++	scb_val_t scbval;
++	static int cnt = 0;
++
++	WL_DBG(("Enter \n"));
++
++	/* scan request can come with empty request : perform all default scan */
++	if (!cfg) {
++		err = -EINVAL;
++		goto exit;
++	}
++	if (!cfg->p2p_supported || !p2p_scan(cfg)) {
++		/* LEGACY SCAN TRIGGER */
++		WL_SCAN((" LEGACY E-SCAN START\n"));
++
++#if defined(USE_INITIAL_SHORT_DWELL_TIME)
++		if (!request) {
++			err = -EINVAL;
++			goto exit;
++		}
++		if (ndev == bcmcfg_to_prmry_ndev(cfg) && g_first_broadcast_scan == true) {
++			is_first_init_2g_scan = true;
++			g_first_broadcast_scan = false;
++		}
++#endif 
++
++		/* if scan request is not empty parse scan request paramters */
++		if (request != NULL) {
++			n_channels = request->n_channels;
++			n_ssids = request->n_ssids;
++			if (n_channels % 2)
++				/* If n_channels is odd, add a padd of u16 */
++				params_size += sizeof(u16) * (n_channels + 1);
++			else
++				params_size += sizeof(u16) * n_channels;
++
++			/* Allocate space for populating ssids in wl_escan_params_t struct */
++			params_size += sizeof(struct wlc_ssid) * n_ssids;
++		}
++		params = (wl_escan_params_t *) kzalloc(params_size, GFP_KERNEL);
++		if (params == NULL) {
++			err = -ENOMEM;
++			goto exit;
++		}
++		wl_scan_prep(cfg, &params->params, request);
++
++#if defined(USE_INITIAL_SHORT_DWELL_TIME)
++		/* Override active_time to reduce scan time if it's first bradcast scan. */
++		if (is_first_init_2g_scan)
++			params->params.active_time = FIRST_SCAN_ACTIVE_DWELL_TIME_MS;
++#endif 
++
++		params->version = htod32(ESCAN_REQ_VERSION);
++		params->action =  htod16(action);
++		wl_escan_set_sync_id(params->sync_id, cfg);
++		wl_escan_set_type(cfg, WL_SCANTYPE_LEGACY);
++		if (params_size + sizeof("escan") >= WLC_IOCTL_MEDLEN) {
++			WL_ERR(("ioctl buffer length not sufficient\n"));
++			kfree(params);
++			err = -ENOMEM;
++			goto exit;
++		}
++		if (cfg->active_scan == PASSIVE_SCAN) {
++			params->params.scan_type = DOT11_SCANTYPE_PASSIVE;
++			WL_DBG(("Passive scan_type %d \n", params->params.scan_type));
++		}
++
++		bssidx = wl_get_bssidx_by_wdev(cfg, ndev->ieee80211_ptr);
++
++		WL_MSG(ndev->name, "LEGACY_SCAN sync ID: %d, bssidx: %d\n", params->sync_id, bssidx);
++		err = wldev_iovar_setbuf(ndev, "escan", params, params_size,
++			cfg->escan_ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++		if (unlikely(err)) {
++			if (err == BCME_EPERM)
++				/* Scan Not permitted at this point of time */
++				WL_DBG((" Escan not permitted at this time (%d)\n", err));
++			else
++				WL_ERR((" Escan set error (%d)\n", err));
++		} else {
++			DBG_EVENT_LOG((dhd_pub_t *)cfg->pub, WIFI_EVENT_DRIVER_SCAN_REQUESTED);
++		}
++		kfree(params);
++	}
++	else if (p2p_is_on(cfg) && p2p_scan(cfg)) {
++		/* P2P SCAN TRIGGER */
++		s32 _freq = 0;
++		n_nodfs = 0;
++		if (request && request->n_channels) {
++			num_chans = request->n_channels;
++			WL_SCAN((" chann number : %d\n", num_chans));
++			default_chan_list = kzalloc(num_chans * sizeof(*default_chan_list),
++				GFP_KERNEL);
++			if (default_chan_list == NULL) {
++				WL_ERR(("channel list allocation failed \n"));
++				err = -ENOMEM;
++				goto exit;
++			}
++			if (!wl_get_valid_channels(ndev, chan_buf, sizeof(chan_buf))) {
++#ifdef P2P_SKIP_DFS
++				int is_printed = false;
++#endif /* P2P_SKIP_DFS */
++				list = (wl_uint32_list_t *) chan_buf;
++				n_valid_chan = dtoh32(list->count);
++				if (n_valid_chan > WL_NUMCHANNELS) {
++					WL_ERR(("wrong n_valid_chan:%d\n", n_valid_chan));
++					kfree(default_chan_list);
++					err = -EINVAL;
++					goto exit;
++				}
++
++				for (i = 0; i < num_chans; i++)
++				{
++					_freq = request->channels[i]->center_freq;
++					channel = ieee80211_frequency_to_channel(_freq);
++
++					/* ignore DFS channels */
++					if (request->channels[i]->flags &
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
++						(IEEE80211_CHAN_NO_IR
++						| IEEE80211_CHAN_RADAR))
++#else
++						(IEEE80211_CHAN_RADAR
++						| IEEE80211_CHAN_PASSIVE_SCAN))
++#endif
++						continue;
++#ifdef P2P_SKIP_DFS
++					if (channel >= 52 && channel <= 144) {
++						if (is_printed == false) {
++							WL_ERR(("SKIP DFS CHANs(52~144)\n"));
++							is_printed = true;
++						}
++						continue;
++					}
++#endif /* P2P_SKIP_DFS */
++
++					for (j = 0; j < n_valid_chan; j++) {
++						/* allows only supported channel on
++						*  current reguatory
++						*/
++						if (n_nodfs >= num_chans) {
++							break;
++						}
++						if (channel == (dtoh32(list->element[j]))) {
++							default_chan_list[n_nodfs++] =
++								channel;
++						}
++					}
++
++				}
++			}
++			if (num_chans == SOCIAL_CHAN_CNT && (
++						(default_chan_list[0] == SOCIAL_CHAN_1) &&
++						(default_chan_list[1] == SOCIAL_CHAN_2) &&
++						(default_chan_list[2] == SOCIAL_CHAN_3))) {
++				/* SOCIAL CHANNELS 1, 6, 11 */
++				search_state = WL_P2P_DISC_ST_SEARCH;
++				p2p_scan_purpose = P2P_SCAN_SOCIAL_CHANNEL;
++				WL_INFORM(("P2P SEARCH PHASE START \n"));
++			} else if (((dev = wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_CONNECTION1)) &&
++				(wl_get_mode_by_netdev(cfg, dev) == WL_MODE_AP)) ||
++				((dev = wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_CONNECTION2)) &&
++				(wl_get_mode_by_netdev(cfg, dev) == WL_MODE_AP))) {
++				/* If you are already a GO, then do SEARCH only */
++				WL_INFORM(("Already a GO. Do SEARCH Only"));
++				search_state = WL_P2P_DISC_ST_SEARCH;
++				num_chans = n_nodfs;
++				p2p_scan_purpose = P2P_SCAN_NORMAL;
++
++			} else if (num_chans == 1) {
++				p2p_scan_purpose = P2P_SCAN_CONNECT_TRY;
++			} else if (num_chans == SOCIAL_CHAN_CNT + 1) {
++			/* SOCIAL_CHAN_CNT + 1 takes care of the Progressive scan supported by
++			 * the supplicant
++			 */
++				p2p_scan_purpose = P2P_SCAN_SOCIAL_CHANNEL;
++			} else {
++				WL_INFORM(("P2P SCAN STATE START \n"));
++				num_chans = n_nodfs;
++				p2p_scan_purpose = P2P_SCAN_NORMAL;
++			}
++		} else {
++			err = -EINVAL;
++			goto exit;
++		}
++		err = wl_cfgp2p_escan(cfg, ndev, ACTIVE_SCAN, num_chans, default_chan_list,
++			search_state, action,
++			wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE), NULL,
++			p2p_scan_purpose);
++
++		if (!err)
++			cfg->p2p->search_state = search_state;
++
++		kfree(default_chan_list);
++	}
++exit:
++	if (unlikely(err)) {
++		/* Don't print Error incase of Scan suppress */
++		if ((err == BCME_EPERM) && cfg->scan_suppressed)
++			WL_DBG(("Escan failed: Scan Suppressed \n"));
++		else {
++			cnt++;
++			WL_ERR(("error (%d), cnt=%d\n", err, cnt));
++			// terence 20140111: send disassoc to firmware
++			if (cnt >= 4) {
++				memset(&scbval, 0, sizeof(scb_val_t));
++				wldev_ioctl(ndev, WLC_DISASSOC, &scbval, sizeof(scb_val_t), true);
++				WL_ERR(("Send disassoc to break the busy dev=%p\n", dev));
++				cnt = 0;
++			}
++		}
++	} else {
++		cnt = 0;
++	}
++	return err;
++}
++
++
++static s32
++wl_do_escan(struct bcm_cfg80211 *cfg, struct wiphy *wiphy, struct net_device *ndev,
++	struct cfg80211_scan_request *request)
++{
++	s32 err = BCME_OK;
++	s32 passive_scan = 0;
++	s32 passive_scan_time = 0;
++	s32 passive_scan_time_org = 0;
++	wl_scan_results_t *results;
++	WL_SCAN(("Enter \n"));
++
++	results = wl_escan_get_buf(cfg, FALSE);
++	results->version = 0;
++	results->count = 0;
++	results->buflen = WL_SCAN_RESULTS_FIXED_SIZE;
++
++	cfg->escan_info.ndev = ndev;
++	cfg->escan_info.wiphy = wiphy;
++	cfg->escan_info.escan_state = WL_ESCAN_STATE_SCANING;
++	passive_scan = cfg->active_scan ? 0 : 1;
++	err = wldev_ioctl_set(ndev, WLC_SET_PASSIVE_SCAN,
++	                      &passive_scan, sizeof(passive_scan));
++	if (unlikely(err)) {
++		WL_ERR(("error (%d)\n", err));
++		goto exit;
++	}
++
++	if (passive_channel_skip) {
++
++		err = wldev_ioctl_get(ndev, WLC_GET_SCAN_PASSIVE_TIME,
++			&passive_scan_time_org, sizeof(passive_scan_time_org));
++		if (unlikely(err)) {
++			WL_ERR(("== error (%d)\n", err));
++			goto exit;
++		}
++
++		WL_SCAN(("PASSIVE SCAN time : %d \n", passive_scan_time_org));
++
++		passive_scan_time = 0;
++		err = wldev_ioctl_set(ndev, WLC_SET_SCAN_PASSIVE_TIME,
++			&passive_scan_time, sizeof(passive_scan_time));
++		if (unlikely(err)) {
++			WL_ERR(("== error (%d)\n", err));
++			goto exit;
++		}
++
++		WL_SCAN(("PASSIVE SCAN SKIPED!! (passive_channel_skip:%d) \n",
++			passive_channel_skip));
++	}
++
++	err = wl_run_escan(cfg, ndev, request, WL_SCAN_ACTION_START);
++
++	if (passive_channel_skip) {
++		err = wldev_ioctl_set(ndev, WLC_SET_SCAN_PASSIVE_TIME,
++			&passive_scan_time_org, sizeof(passive_scan_time_org));
++		if (unlikely(err)) {
++			WL_ERR(("== error (%d)\n", err));
++			goto exit;
++		}
++
++		WL_SCAN(("PASSIVE SCAN RECOVERED!! (passive_scan_time_org:%d) \n",
++			passive_scan_time_org));
++	}
++
++exit:
++	return err;
++}
++
++static s32
++__wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
++	struct cfg80211_scan_request *request,
++	struct cfg80211_ssid *this_ssid)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct cfg80211_ssid *ssids;
++	struct ether_addr primary_mac;
++	bool p2p_ssid;
++#ifdef WL11U
++	bcm_tlv_t *interworking_ie;
++#endif
++	s32 err = 0;
++	s32 bssidx = -1;
++	s32 i;
++
++	unsigned long flags;
++	static s32 busy_count = 0;
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++	struct net_device *remain_on_channel_ndev = NULL;
++#endif
++	uint scan_timer_interval_ms = WL_SCAN_TIMER_INTERVAL_MS;
++
++	/*
++	 * Hostapd triggers scan before starting automatic channel selection
++	 * to collect channel characteristics. However firmware scan engine
++	 * doesn't support any channel characteristics collection along with
++	 * scan. Hence return scan success.
++	 */
++	if (request && (scan_req_iftype(request) == NL80211_IFTYPE_AP)) {
++		WL_INFORM(("Scan Command on SoftAP Interface. Ignoring...\n"));
++// terence 20161023: let it scan in SoftAP mode
++//		return 0;
++	}
++
++	ndev = ndev_to_wlc_ndev(ndev, cfg);
++
++	if (WL_DRV_STATUS_SENDING_AF_FRM_EXT(cfg)) {
++		WL_ERR(("Sending Action Frames. Try it again.\n"));
++		return -EAGAIN;
++	}
++
++	WL_DBG(("Enter wiphy (%p)\n", wiphy));
++	if (wl_get_drv_status_all(cfg, SCANNING)) {
++		if (cfg->scan_request == NULL) {
++			wl_clr_drv_status_all(cfg, SCANNING);
++			WL_DBG(("<<<<<<<<<<<Force Clear Scanning Status>>>>>>>>>>>\n"));
++		} else {
++			WL_ERR(("Scanning already\n"));
++			return -EAGAIN;
++		}
++	}
++	if (wl_get_drv_status(cfg, SCAN_ABORTING, ndev)) {
++		WL_ERR(("Scanning being aborted\n"));
++		return -EAGAIN;
++	}
++	if (request && request->n_ssids > WL_SCAN_PARAMS_SSID_MAX) {
++		WL_ERR(("request null or n_ssids > WL_SCAN_PARAMS_SSID_MAX\n"));
++		return -EOPNOTSUPP;
++	}
++
++#ifdef P2P_LISTEN_OFFLOADING
++	if (wl_get_p2p_status(cfg, DISC_IN_PROGRESS)) {
++		WL_ERR(("P2P_FIND: Discovery offload is in progress\n"));
++		return -EAGAIN;
++	}
++#endif /* P2P_LISTEN_OFFLOADING */
++
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++	remain_on_channel_ndev = wl_cfg80211_get_remain_on_channel_ndev(cfg);
++	if (remain_on_channel_ndev) {
++		WL_DBG(("Remain_on_channel bit is set, somehow it didn't get cleared\n"));
++		wl_notify_escan_complete(cfg, remain_on_channel_ndev, true, true);
++	}
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++
++
++	/* Arm scan timeout timer */
++	mod_timer(&cfg->scan_timeout, jiffies + msecs_to_jiffies(scan_timer_interval_ms));
++	if (request) {		/* scan bss */
++		ssids = request->ssids;
++		p2p_ssid = false;
++		for (i = 0; i < request->n_ssids; i++) {
++			if (ssids[i].ssid_len &&
++				IS_P2P_SSID(ssids[i].ssid, ssids[i].ssid_len)) {
++				p2p_ssid = true;
++				break;
++			}
++		}
++		if (p2p_ssid) {
++			if (cfg->p2p_supported) {
++				/* p2p scan trigger */
++				if (p2p_on(cfg) == false) {
++					/* p2p on at the first time */
++					p2p_on(cfg) = true;
++					wl_cfgp2p_set_firm_p2p(cfg);
++					get_primary_mac(cfg, &primary_mac);
++					wl_cfgp2p_generate_bss_mac(cfg, &primary_mac);
++#if defined(P2P_IE_MISSING_FIX)
++					cfg->p2p_prb_noti = false;
++#endif
++				}
++				wl_clr_p2p_status(cfg, GO_NEG_PHASE);
++				WL_DBG(("P2P: GO_NEG_PHASE status cleared \n"));
++				p2p_scan(cfg) = true;
++			}
++		} else {
++			/* legacy scan trigger
++			 * So, we have to disable p2p discovery if p2p discovery is on
++			 */
++			if (cfg->p2p_supported) {
++				p2p_scan(cfg) = false;
++				/* If Netdevice is not equals to primary and p2p is on
++				*  , we will do p2p scan using P2PAPI_BSSCFG_DEVICE.
++				*/
++
++				if (p2p_scan(cfg) == false) {
++					if (wl_get_p2p_status(cfg, DISCOVERY_ON)) {
++						err = wl_cfgp2p_discover_enable_search(cfg,
++						false);
++						if (unlikely(err)) {
++							goto scan_out;
++						}
++
++					}
++				}
++			}
++			if (!cfg->p2p_supported || !p2p_scan(cfg)) {
++				if ((bssidx = wl_get_bssidx_by_wdev(cfg,
++					ndev->ieee80211_ptr)) < 0) {
++					WL_ERR(("Find p2p index from ndev(%p) failed\n",
++						ndev));
++					err = BCME_ERROR;
++					goto scan_out;
++				}
++#ifdef WL11U
++				if (request && (interworking_ie =
++						wl_cfg80211_find_interworking_ie(
++						request->ie, request->ie_len)) != NULL) {
++					if ((err = wl_cfg80211_add_iw_ie(cfg, ndev, bssidx,
++							VNDR_IE_CUSTOM_FLAG, interworking_ie->id,
++							interworking_ie->data,
++							interworking_ie->len)) != BCME_OK) {
++						WL_ERR(("Failed to add interworking IE"));
++					}
++				} else if (cfg->wl11u) {
++					/* we have to clear IW IE and disable gratuitous APR */
++					wl_cfg80211_clear_iw_ie(cfg, ndev, bssidx);
++					err = wldev_iovar_setint_bsscfg(ndev, "grat_arp",
++					                                0, bssidx);
++					/* we don't care about error here
++					 * because the only failure case is unsupported,
++					 * which is fine
++					 */
++					if (unlikely(err)) {
++						WL_ERR(("Set grat_arp failed:(%d) Ignore!\n", err));
++					}
++					cfg->wl11u = FALSE;
++				}
++#endif /* WL11U */
++				if (request) {
++					err = wl_cfg80211_set_mgmt_vndr_ies(cfg,
++							ndev_to_cfgdev(ndev),
++							bssidx, VNDR_IE_PRBREQ_FLAG, request->ie,
++							request->ie_len);
++				}
++
++				if (unlikely(err)) {
++// terence 20161023: let it scan in SoftAP mode
++//					goto scan_out;
++				}
++
++			}
++		}
++	} else {		/* scan in ibss */
++		ssids = this_ssid;
++	}
++
++	if (request && cfg->p2p_supported) {
++		WL_TRACE_HW4(("START SCAN\n"));
++		DHD_OS_SCAN_WAKE_LOCK_TIMEOUT((dhd_pub_t *)(cfg->pub),
++			SCAN_WAKE_LOCK_TIMEOUT);
++		DHD_DISABLE_RUNTIME_PM((dhd_pub_t *)(cfg->pub));
++	}
++
++	if (cfg->p2p_supported) {
++		if (request && p2p_on(cfg) && p2p_scan(cfg)) {
++
++			/* find my listen channel */
++			cfg->afx_hdl->my_listen_chan =
++				wl_find_listen_channel(cfg, request->ie,
++				request->ie_len);
++			err = wl_cfgp2p_enable_discovery(cfg, ndev,
++			request->ie, request->ie_len);
++
++			if (unlikely(err)) {
++				goto scan_out;
++			}
++		}
++	}
++	err = wl_do_escan(cfg, wiphy, ndev, request);
++	if (likely(!err))
++		goto scan_success;
++	else
++		goto scan_out;
++
++scan_success:
++	busy_count = 0;
++	cfg->scan_request = request;
++	wl_set_drv_status(cfg, SCANNING, ndev);
++
++	return 0;
++
++scan_out:
++	if (err == BCME_BUSY || err == BCME_NOTREADY) {
++		WL_ERR(("Scan err = (%d), busy?%d", err, -EBUSY));
++		err = -EBUSY;
++	} else if ((err == BCME_EPERM) && cfg->scan_suppressed) {
++		WL_ERR(("Scan not permitted due to scan suppress\n"));
++		err = -EPERM;
++	} else {
++		/* For all other fw errors, use a generic error code as return
++		 * value to cfg80211 stack
++		 */
++		err = -EAGAIN;
++	}
++
++#define SCAN_EBUSY_RETRY_LIMIT 20
++	if (err == -EBUSY) {
++		if (busy_count++ > SCAN_EBUSY_RETRY_LIMIT) {
++			struct ether_addr bssid;
++			s32 ret = 0;
++#if defined(DHD_DEBUG) && defined(DHD_FW_COREDUMP)
++			dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++#endif /* DHD_DEBUG && DHD_FW_COREDUMP */
++			busy_count = 0;
++			WL_ERR(("Unusual continuous EBUSY error, %d %d %d %d %d %d %d %d %d\n",
++				wl_get_drv_status(cfg, SCANNING, ndev),
++				wl_get_drv_status(cfg, SCAN_ABORTING, ndev),
++				wl_get_drv_status(cfg, CONNECTING, ndev),
++				wl_get_drv_status(cfg, CONNECTED, ndev),
++				wl_get_drv_status(cfg, DISCONNECTING, ndev),
++				wl_get_drv_status(cfg, AP_CREATING, ndev),
++				wl_get_drv_status(cfg, AP_CREATED, ndev),
++				wl_get_drv_status(cfg, SENDING_ACT_FRM, ndev),
++				wl_get_drv_status(cfg, SENDING_ACT_FRM, ndev)));
++
++#if defined(DHD_DEBUG) && defined(DHD_FW_COREDUMP)
++			if (dhdp->memdump_enabled) {
++				dhdp->memdump_type = DUMP_TYPE_SCAN_BUSY;
++				dhd_bus_mem_dump(dhdp);
++			}
++#endif /* DHD_DEBUG && DHD_FW_COREDUMP */
++
++			bzero(&bssid, sizeof(bssid));
++			if ((ret = wldev_ioctl_get(ndev, WLC_GET_BSSID,
++				&bssid, ETHER_ADDR_LEN)) == 0)
++				WL_ERR(("FW is connected with " MACDBG "/n",
++					MAC2STRDBG(bssid.octet)));
++			else
++				WL_ERR(("GET BSSID failed with %d\n", ret));
++
++			wl_cfg80211_scan_abort(cfg);
++
++		} else {
++			/* Hold the context for 400msec, so that 10 subsequent scans
++			* can give a buffer of 4sec which is enough to
++			* cover any on-going scan in the firmware
++			*/
++			WL_DBG(("Enforcing delay for EBUSY case \n"));
++			msleep(400);
++		}
++	} else {
++		busy_count = 0;
++	}
++
++	wl_clr_drv_status(cfg, SCANNING, ndev);
++	if (timer_pending(&cfg->scan_timeout))
++		_del_timer_sync(&cfg->scan_timeout);
++	DHD_OS_SCAN_WAKE_UNLOCK((dhd_pub_t *)(cfg->pub));
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++	cfg->scan_request = NULL;
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++
++	return err;
++}
++
++static s32
++#if defined(WL_CFG80211_P2P_DEV_IF)
++wl_cfg80211_scan(struct wiphy *wiphy, struct cfg80211_scan_request *request)
++#else
++wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
++	struct cfg80211_scan_request *request)
++#endif /* WL_CFG80211_P2P_DEV_IF */
++{
++	s32 err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	struct net_device *ndev = wdev_to_wlc_ndev(request->wdev, cfg);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++	WL_DBG(("Enter\n"));
++	RETURN_EIO_IF_NOT_UP(cfg);
++
++#ifdef DHD_IFDEBUG
++#ifdef WL_CFG80211_P2P_DEV_IF
++	PRINT_WDEV_INFO(request->wdev);
++#else
++	PRINT_WDEV_INFO(ndev);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++#endif /* DHD_IFDEBUG */
++
++	if (ndev == bcmcfg_to_prmry_ndev(cfg)) {
++		if (wl_cfg_multip2p_operational(cfg)) {
++			WL_ERR(("wlan0 scan failed, p2p devices are operational"));
++			 return -ENODEV;
++		}
++	}
++	err = wl_cfg80211_check_in4way(cfg, ndev_to_wlc_ndev(ndev, cfg), NO_SCAN_IN4WAY,
++		WL_EXT_STATUS_SCAN, NULL);
++	if (err)
++		return err;
++
++	mutex_lock(&cfg->usr_sync);
++	err = __wl_cfg80211_scan(wiphy, ndev, request, NULL);
++	if (unlikely(err)) {
++		WL_ERR(("scan error (%d)\n", err));
++	}
++	mutex_unlock(&cfg->usr_sync);
++#ifdef WL_DRV_AVOID_SCANCACHE
++	/* Reset roam cache after successful scan request */
++#endif /* WL_DRV_AVOID_SCANCACHE */
++	return err;
++}
++
++static s32 wl_set_rts(struct net_device *dev, u32 rts_threshold)
++{
++	s32 err = 0;
++
++	err = wldev_iovar_setint(dev, "rtsthresh", rts_threshold);
++	if (unlikely(err)) {
++		WL_ERR(("Error (%d)\n", err));
++		return err;
++	}
++	return err;
++}
++
++static s32 wl_set_frag(struct net_device *dev, u32 frag_threshold)
++{
++	s32 err = 0;
++
++	err = wldev_iovar_setint_bsscfg(dev, "fragthresh", frag_threshold, 0);
++	if (unlikely(err)) {
++		WL_ERR(("Error (%d)\n", err));
++		return err;
++	}
++	return err;
++}
++
++static s32 wl_set_retry(struct net_device *dev, u32 retry, bool l)
++{
++	s32 err = 0;
++	u32 cmd = (l ? WLC_SET_LRL : WLC_SET_SRL);
++
++	retry = htod32(retry);
++	err = wldev_ioctl_set(dev, cmd, &retry, sizeof(retry));
++	if (unlikely(err)) {
++		WL_ERR(("cmd (%d) , error (%d)\n", cmd, err));
++		return err;
++	}
++	return err;
++}
++
++static s32 wl_cfg80211_set_wiphy_params(struct wiphy *wiphy, u32 changed)
++{
++	struct bcm_cfg80211 *cfg = (struct bcm_cfg80211 *)wiphy_priv(wiphy);
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	s32 err = 0;
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	WL_DBG(("Enter\n"));
++	if (changed & WIPHY_PARAM_RTS_THRESHOLD &&
++		(cfg->conf->rts_threshold != wiphy->rts_threshold)) {
++		cfg->conf->rts_threshold = wiphy->rts_threshold;
++		err = wl_set_rts(ndev, cfg->conf->rts_threshold);
++		if (err != BCME_OK)
++			return err;
++	}
++	if (changed & WIPHY_PARAM_FRAG_THRESHOLD &&
++		(cfg->conf->frag_threshold != wiphy->frag_threshold)) {
++		cfg->conf->frag_threshold = wiphy->frag_threshold;
++		err = wl_set_frag(ndev, cfg->conf->frag_threshold);
++		if (err != BCME_OK)
++			return err;
++	}
++	if (changed & WIPHY_PARAM_RETRY_LONG &&
++		(cfg->conf->retry_long != wiphy->retry_long)) {
++		cfg->conf->retry_long = wiphy->retry_long;
++		err = wl_set_retry(ndev, cfg->conf->retry_long, true);
++		if (err != BCME_OK)
++			return err;
++	}
++	if (changed & WIPHY_PARAM_RETRY_SHORT &&
++		(cfg->conf->retry_short != wiphy->retry_short)) {
++		cfg->conf->retry_short = wiphy->retry_short;
++		err = wl_set_retry(ndev, cfg->conf->retry_short, false);
++		if (err != BCME_OK) {
++			return err;
++		}
++	}
++
++	return err;
++}
++static chanspec_t
++channel_to_chanspec(struct wiphy *wiphy, struct net_device *dev, u32 channel, u32 bw_cap)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	u8 *buf = NULL;
++	wl_uint32_list_t *list;
++	int err = BCME_OK;
++	chanspec_t c = 0, ret_c = 0;
++	int bw = 0, tmp_bw = 0;
++	int i;
++	u32 tmp_c;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++#define LOCAL_BUF_SIZE	1024
++	buf = (u8 *) kzalloc(LOCAL_BUF_SIZE, kflags);
++	if (!buf) {
++		WL_ERR(("buf memory alloc failed\n"));
++		goto exit;
++	}
++
++	err = wldev_iovar_getbuf_bsscfg(dev, "chanspecs", NULL,
++		0, buf, LOCAL_BUF_SIZE, 0, &cfg->ioctl_buf_sync);
++	if (err != BCME_OK) {
++		WL_ERR(("get chanspecs failed with %d\n", err));
++		goto exit;
++	}
++
++	list = (wl_uint32_list_t *)(void *)buf;
++	for (i = 0; i < dtoh32(list->count); i++) {
++		c = dtoh32(list->element[i]);
++		if (channel <= CH_MAX_2G_CHANNEL) {
++			if (!CHSPEC_IS20(c))
++				continue;
++			if (channel == CHSPEC_CHANNEL(c)) {
++				ret_c = c;
++				bw = 20;
++				goto exit;
++			}
++		}
++		tmp_c = wf_chspec_ctlchan(c);
++		tmp_bw = bw2cap[CHSPEC_BW(c) >> WL_CHANSPEC_BW_SHIFT];
++		if (tmp_c != channel)
++			continue;
++
++		if ((tmp_bw > bw) && (tmp_bw <= bw_cap)) {
++			bw = tmp_bw;
++			ret_c = c;
++			if (bw == bw_cap)
++				goto exit;
++		}
++	}
++exit:
++	if (buf)
++		kfree(buf);
++#undef LOCAL_BUF_SIZE
++	WL_INFORM(("return chanspec %x %d\n", ret_c, bw));
++	return ret_c;
++}
++
++void
++wl_cfg80211_ibss_vsie_set_buffer(struct net_device *dev, vndr_ie_setbuf_t *ibss_vsie,
++	int ibss_vsie_len)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++
++	if (cfg != NULL && ibss_vsie != NULL) {
++		if (cfg->ibss_vsie != NULL) {
++			kfree(cfg->ibss_vsie);
++		}
++		cfg->ibss_vsie = ibss_vsie;
++		cfg->ibss_vsie_len = ibss_vsie_len;
++	}
++}
++
++static void
++wl_cfg80211_ibss_vsie_free(struct bcm_cfg80211 *cfg)
++{
++	/* free & initiralize VSIE (Vendor Specific IE) */
++	if (cfg->ibss_vsie != NULL) {
++		kfree(cfg->ibss_vsie);
++		cfg->ibss_vsie = NULL;
++		cfg->ibss_vsie_len = 0;
++	}
++}
++
++s32
++wl_cfg80211_ibss_vsie_delete(struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	char *ioctl_buf = NULL;
++	s32 ret = BCME_OK, bssidx;
++
++	if (cfg != NULL && cfg->ibss_vsie != NULL) {
++		ioctl_buf = kmalloc(WLC_IOCTL_MEDLEN, GFP_KERNEL);
++		if (!ioctl_buf) {
++			WL_ERR(("ioctl memory alloc failed\n"));
++			return -ENOMEM;
++		}
++
++		if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++			WL_ERR(("Find index failed\n"));
++			ret = BCME_ERROR;
++			goto end;
++		}
++		/* change the command from "add" to "del" */
++		strncpy(cfg->ibss_vsie->cmd, "del", VNDR_IE_CMD_LEN - 1);
++		cfg->ibss_vsie->cmd[VNDR_IE_CMD_LEN - 1] = '\0';
++
++		ret = wldev_iovar_setbuf_bsscfg(dev, "vndr_ie",
++			cfg->ibss_vsie, cfg->ibss_vsie_len,
++			ioctl_buf, WLC_IOCTL_MEDLEN, bssidx, &cfg->ioctl_buf_sync);
++		WL_ERR(("ret=%d\n", ret));
++
++		if (ret == BCME_OK) {
++			/* free & initiralize VSIE */
++			kfree(cfg->ibss_vsie);
++			cfg->ibss_vsie = NULL;
++			cfg->ibss_vsie_len = 0;
++		}
++end:
++		if (ioctl_buf) {
++			kfree(ioctl_buf);
++		}
++	}
++
++	return ret;
++}
++
++#ifdef WLAIBSS_MCHAN
++static bcm_struct_cfgdev*
++bcm_cfg80211_add_ibss_if(struct wiphy *wiphy, char *name)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct wireless_dev* wdev = NULL;
++	struct net_device *new_ndev = NULL;
++	struct net_device *primary_ndev = NULL;
++	s32 timeout;
++	wl_aibss_if_t aibss_if;
++	wl_if_event_info *event = NULL;
++
++	if (cfg->ibss_cfgdev != NULL) {
++		WL_ERR(("IBSS interface %s already exists\n", name));
++		return NULL;
++	}
++
++	WL_ERR(("Try to create IBSS interface %s\n", name));
++	primary_ndev = bcmcfg_to_prmry_ndev(cfg);
++	/* generate a new MAC address for the IBSS interface */
++	get_primary_mac(cfg, &cfg->ibss_if_addr);
++	cfg->ibss_if_addr.octet[4] ^= 0x40;
++	memset(&aibss_if, sizeof(aibss_if), 0);
++	memcpy(&aibss_if.addr, &cfg->ibss_if_addr, sizeof(aibss_if.addr));
++	aibss_if.chspec = 0;
++	aibss_if.len = sizeof(aibss_if);
++
++	cfg->bss_pending_op = TRUE;
++	memset(&cfg->if_event_info, 0, sizeof(cfg->if_event_info));
++	err = wldev_iovar_setbuf(primary_ndev, "aibss_ifadd", &aibss_if,
++		sizeof(aibss_if), cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++	if (err) {
++		WL_ERR(("IOVAR aibss_ifadd failed with error %d\n", err));
++		goto fail;
++	}
++	timeout = wait_event_interruptible_timeout(cfg->netif_change_event,
++		!cfg->bss_pending_op, msecs_to_jiffies(MAX_WAIT_TIME));
++	if (timeout <= 0 || cfg->bss_pending_op)
++		goto fail;
++
++	event = &cfg->if_event_info;
++	/* By calling wl_cfg80211_allocate_if (dhd_allocate_if eventually) we give the control
++	 * over this net_device interface to dhd_linux, hence the interface is managed by dhd_liux
++	 * and will be freed by dhd_detach unless it gets unregistered before that. The
++	 * wireless_dev instance new_ndev->ieee80211_ptr associated with this net_device will
++	 * be freed by wl_dealloc_netinfo
++	 */
++	new_ndev = wl_cfg80211_allocate_if(cfg, event->ifidx, event->name,
++		event->mac, event->bssidx, event->name);
++	if (new_ndev == NULL)
++		goto fail;
++	wdev = kzalloc(sizeof(*wdev), GFP_KERNEL);
++	if (wdev == NULL)
++		goto fail;
++	wdev->wiphy = wiphy;
++	wdev->iftype = NL80211_IFTYPE_ADHOC;
++	wdev->netdev = new_ndev;
++	new_ndev->ieee80211_ptr = wdev;
++	SET_NETDEV_DEV(new_ndev, wiphy_dev(wdev->wiphy));
++
++	/* rtnl lock must have been acquired, if this is not the case, wl_cfg80211_register_if
++	* needs to be modified to take one parameter (bool need_rtnl_lock)
++	 */
++	ASSERT_RTNL();
++	if (wl_cfg80211_register_if(cfg, event->ifidx, new_ndev, FALSE) != BCME_OK)
++		goto fail;
++
++	wl_alloc_netinfo(cfg, new_ndev, wdev, WL_MODE_IBSS, PM_ENABLE, event->bssidx);
++	cfg->ibss_cfgdev = ndev_to_cfgdev(new_ndev);
++	WL_ERR(("IBSS interface %s created\n", new_ndev->name));
++	return cfg->ibss_cfgdev;
++
++fail:
++	WL_ERR(("failed to create IBSS interface %s \n", name));
++	cfg->bss_pending_op = FALSE;
++	if (new_ndev)
++		wl_cfg80211_remove_if(cfg, event->ifidx, new_ndev, FALSE);
++	if (wdev)
++		kfree(wdev);
++	return NULL;
++}
++
++static s32
++bcm_cfg80211_del_ibss_if(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *ndev = NULL;
++	struct net_device *primary_ndev = NULL;
++	s32 timeout;
++
++	if (!cfgdev || cfg->ibss_cfgdev != cfgdev || ETHER_ISNULLADDR(&cfg->ibss_if_addr.octet))
++		return -EINVAL;
++	ndev = (struct net_device *)cfgdev_to_ndev(cfg->ibss_cfgdev);
++	primary_ndev = bcmcfg_to_prmry_ndev(cfg);
++
++	cfg->bss_pending_op = TRUE;
++	memset(&cfg->if_event_info, 0, sizeof(cfg->if_event_info));
++	err = wldev_iovar_setbuf(primary_ndev, "aibss_ifdel", &cfg->ibss_if_addr,
++		sizeof(cfg->ibss_if_addr), cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++	if (err) {
++		WL_ERR(("IOVAR aibss_ifdel failed with error %d\n", err));
++		goto fail;
++	}
++	timeout = wait_event_interruptible_timeout(cfg->netif_change_event,
++		!cfg->bss_pending_op, msecs_to_jiffies(MAX_WAIT_TIME));
++	if (timeout <= 0 || cfg->bss_pending_op) {
++		WL_ERR(("timeout in waiting IF_DEL event\n"));
++		goto fail;
++	}
++
++	wl_cfg80211_remove_if(cfg, cfg->if_event_info.ifidx, ndev, FALSE);
++	cfg->ibss_cfgdev = NULL;
++	return 0;
++
++fail:
++	cfg->bss_pending_op = FALSE;
++	return -1;
++}
++#endif /* WLAIBSS_MCHAN */
++
++#ifdef WLMESH_CFG80211
++s32
++wl_cfg80211_interface_ops(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev, s32 bsscfg_idx,
++	enum nl80211_iftype iface_type, s32 del, u8 *addr)
++{
++	wl_interface_create_t iface;
++	s32 ret;
++	wl_interface_info_t *info;
++
++	bzero(&iface, sizeof(wl_interface_create_t));
++
++	iface.ver = WL_INTERFACE_CREATE_VER;
++
++	if (iface_type == NL80211_IFTYPE_AP)
++		iface.flags = WL_INTERFACE_CREATE_AP;
++	else
++		iface.flags = WL_INTERFACE_CREATE_STA;
++
++	if (del) {
++		ret = wldev_iovar_setbuf(ndev, "interface_remove",
++			NULL, 0, cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	} else {
++		if (addr) {
++			memcpy(&iface.mac_addr.octet, addr, ETH_ALEN);
++			iface.flags |= WL_INTERFACE_MAC_USE;
++		}
++		ret = wldev_iovar_getbuf(ndev, "interface_create",
++			&iface, sizeof(wl_interface_create_t),
++			cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++		if (ret == 0) {
++			/* success */
++			info = (wl_interface_info_t *)cfg->ioctl_buf;
++			WL_DBG(("wl interface create success!! bssidx:%d \n",
++				info->bsscfgidx));
++		}
++	}
++
++	if (ret < 0)
++		WL_ERR(("Interface %s failed!! ret %d\n",
++			del ? "remove" : "create", ret));
++
++	return ret;
++}
++#else
++s32
++wl_cfg80211_interface_ops(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev, s32 bsscfg_idx,
++	enum nl80211_iftype iface_type, s32 del, u8 *addr)
++{
++	s32 ret;
++	struct wl_interface_create_v2 iface;
++	wl_interface_create_v3_t iface_v3;
++	struct wl_interface_info_v1 *info;
++	wl_interface_info_v2_t *info_v2;
++	enum wl_interface_type iftype;
++	uint32 ifflags;
++	bool use_iface_info_v2 = false;
++	u8 ioctl_buf[WLC_IOCTL_SMLEN];
++
++	if (del) {
++		ret = wldev_iovar_setbuf(ndev, "interface_remove",
++			NULL, 0, ioctl_buf, sizeof(ioctl_buf), NULL);
++		if (unlikely(ret))
++			WL_ERR(("Interface remove failed!! ret %d\n", ret));
++		return ret;
++	}
++
++	/* Interface create */
++	bzero(&iface, sizeof(iface));
++	/*
++	 * flags field is still used along with iftype inorder to support the old version of the
++	 * FW work with the latest app changes.
++	 */
++	if (iface_type == NL80211_IFTYPE_AP) {
++		iftype = WL_INTERFACE_TYPE_AP;
++		ifflags = WL_INTERFACE_CREATE_AP;
++	} else {
++		iftype = WL_INTERFACE_TYPE_STA;
++		ifflags = WL_INTERFACE_CREATE_STA;
++	}
++	if (addr) {
++		ifflags |= WL_INTERFACE_MAC_USE;
++	}
++
++	/* Pass ver = 0 for fetching the interface_create iovar version */
++	ret = wldev_iovar_getbuf(ndev, "interface_create",
++		&iface, sizeof(struct wl_interface_create_v2),
++		ioctl_buf, sizeof(ioctl_buf), NULL);
++	if (ret == BCME_UNSUPPORTED) {
++		WL_ERR(("interface_create iovar not supported\n"));
++		return ret;
++	} else if ((ret == 0) && *((uint32 *)ioctl_buf) == WL_INTERFACE_CREATE_VER_3) {
++		WL_DBG(("interface_create version 3\n"));
++		use_iface_info_v2 = true;
++		bzero(&iface_v3, sizeof(wl_interface_create_v3_t));
++		iface_v3.ver = WL_INTERFACE_CREATE_VER_3;
++		iface_v3.iftype = iftype;
++		iface_v3.flags = ifflags;
++		if (addr) {
++			memcpy(&iface_v3.mac_addr.octet, addr, ETH_ALEN);
++		}
++		ret = wldev_iovar_getbuf(ndev, "interface_create",
++			&iface_v3, sizeof(wl_interface_create_v3_t),
++			ioctl_buf, sizeof(ioctl_buf), NULL);
++	} else {
++#if 0
++		/* On any other error, attempt with iovar version 2 */
++		WL_DBG(("interface_create version 2. get_ver:%d\n", ret));
++		iface.ver = WL_INTERFACE_CREATE_VER_2;
++		iface.iftype = iftype;
++		iface.flags = ifflags;
++		if (addr) {
++			memcpy(&iface.mac_addr.octet, addr, ETH_ALEN);
++		}
++		ret = wldev_iovar_getbuf(ndev, "interface_create",
++			&iface, sizeof(struct wl_interface_create_v2),
++			ioctl_buf, sizeof(ioctl_buf), NULL);
++#endif
++	}
++
++	if (unlikely(ret)) {
++		WL_ERR(("Interface create failed!! ret %d\n", ret));
++		return ret;
++	}
++
++	/* success case */
++	if (use_iface_info_v2 == true) {
++		info_v2 = (wl_interface_info_v2_t *)ioctl_buf;
++		ret = info_v2->bsscfgidx;
++	} else {
++		/* Use v1 struct */
++		info = (struct wl_interface_info_v1 *)ioctl_buf;
++		ret = info->bsscfgidx;
++	}
++
++	WL_DBG(("wl interface create success!! bssidx:%d \n", ret));
++	return ret;
++}
++#endif
++
++bool
++wl_customer6_legacy_chip_check(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev)
++{
++	u32 chipnum;
++	wlc_rev_info_t revinfo;
++	int ret;
++
++	/* Get the device rev info */
++	memset(&revinfo, 0, sizeof(revinfo));
++	ret = wldev_ioctl_get(ndev, WLC_GET_REVINFO, &revinfo, sizeof(revinfo));
++	if (ret < 0) {
++		WL_ERR(("%s: GET revinfo FAILED. ret:%d\n", __FUNCTION__, ret));
++		ASSERT(0);
++		return false;
++	}
++
++	WL_DBG(("%s: GET_REVINFO device 0x%x, vendor 0x%x, chipnum 0x%x\n", __FUNCTION__,
++		dtoh32(revinfo.deviceid), dtoh32(revinfo.vendorid), dtoh32(revinfo.chipnum)));
++	chipnum = revinfo.chipnum;
++	if ((chipnum == BCM4350_CHIP_ID) || (chipnum == BCM4355_CHIP_ID) ||
++		(chipnum == BCM4345_CHIP_ID) || (chipnum == BCM43430_CHIP_ID) ||
++		(chipnum == BCM43362_CHIP_ID)) {
++		/* WAR required */
++		return true;
++	}
++
++	return false;
++}
++
++void
++wl_bss_iovar_war(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev, s32 *val)
++{
++	u32 chipnum;
++	wlc_rev_info_t revinfo;
++	int ret;
++	bool need_war = false;
++
++	/* Get the device rev info */
++	memset(&revinfo, 0, sizeof(revinfo));
++	ret = wldev_ioctl_get(ndev, WLC_GET_REVINFO, &revinfo, sizeof(revinfo));
++	if (ret < 0) {
++		WL_ERR(("%s: GET revinfo FAILED. ret:%d\n", __FUNCTION__, ret));
++	} else {
++		WL_DBG(("%s: GET_REVINFO device 0x%x, vendor 0x%x, chipnum 0x%x\n", __FUNCTION__,
++			dtoh32(revinfo.deviceid), dtoh32(revinfo.vendorid), dtoh32(revinfo.chipnum)));
++		chipnum = revinfo.chipnum;
++		if ((chipnum == BCM4359_CHIP_ID) || (chipnum == BCM43596_CHIP_ID)) { 
++			/* WAR required */
++			need_war = true;
++		}
++	}
++
++	if (wl_customer6_legacy_chip_check(cfg, ndev) || need_war) {
++		/* Few firmware branches have issues in bss iovar handling and
++		 * that can't be changed since they are in production.
++		 */
++		if (*val == WLC_AP_IOV_OP_MANUAL_AP_BSSCFG_CREATE) {
++			*val = WLC_AP_IOV_OP_MANUAL_STA_BSSCFG_CREATE;
++		} else if (*val == WLC_AP_IOV_OP_MANUAL_STA_BSSCFG_CREATE) {
++			*val = WLC_AP_IOV_OP_MANUAL_AP_BSSCFG_CREATE;
++		} else {
++			/* Ignore for other bss enums */
++			return;
++		}
++		WL_ERR(("wl bss %d\n", *val));
++	}
++}
++
++s32
++wl_cfg80211_add_del_bss(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev, s32 bsscfg_idx,
++	enum nl80211_iftype iface_type, s32 del, u8 *addr)
++{
++	s32 ret = BCME_OK;
++	s32 val = 0;
++
++	struct {
++		s32 cfg;
++		s32 val;
++		struct ether_addr ea;
++	} bss_setbuf;
++
++	WL_INFORM(("iface_type:%d del:%d \n", iface_type, del));
++
++	bzero(&bss_setbuf, sizeof(bss_setbuf));
++
++	/* AP=2, STA=3, up=1, down=0, val=-1 */
++	if (del) {
++		val = WLC_AP_IOV_OP_DELETE;
++	} else if (iface_type == NL80211_IFTYPE_AP) {
++		/* Add/role change to AP Interface */
++		WL_DBG(("Adding AP Interface \n"));
++		val = WLC_AP_IOV_OP_MANUAL_AP_BSSCFG_CREATE;
++	} else if (iface_type == NL80211_IFTYPE_STATION) {
++		/* Add/role change to STA Interface */
++		WL_DBG(("Adding STA Interface \n"));
++		val = WLC_AP_IOV_OP_MANUAL_STA_BSSCFG_CREATE;
++	} else {
++		WL_ERR((" add_del_bss NOT supported for IFACE type:0x%x", iface_type));
++		return -EINVAL;
++	}
++
++	if (!del) {
++		wl_bss_iovar_war(cfg, ndev, &val);
++	}
++
++	bss_setbuf.cfg = htod32(bsscfg_idx);
++	bss_setbuf.val = htod32(val);
++
++	if (addr) {
++		memcpy(&bss_setbuf.ea.octet, addr, ETH_ALEN);
++	}
++
++	WL_DBG(("wl bss %d bssidx:%d iface:%s \n", val, bsscfg_idx, ndev->name));
++	ret = wldev_iovar_setbuf(ndev, "bss", &bss_setbuf, sizeof(bss_setbuf),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++	if (ret != 0)
++		WL_ERR(("'bss %d' failed with %d\n", val, ret));
++
++	return ret;
++}
++
++s32
++wl_cfg80211_bss_up(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 bsscfg_idx, s32 bss_up)
++{
++	s32 ret = BCME_OK;
++	s32 val = bss_up ? 1 : 0;
++
++	struct {
++		s32 cfg;
++		s32 val;
++	} bss_setbuf;
++
++	bss_setbuf.cfg = htod32(bsscfg_idx);
++	bss_setbuf.val = htod32(val);
++
++	WL_DBG(("wl bss -C %d %s\n", bsscfg_idx, bss_up ? "up" : "down"));
++	ret = wldev_iovar_setbuf(ndev, "bss", &bss_setbuf, sizeof(bss_setbuf),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++
++	if (ret != 0) {
++		WL_ERR(("'bss %d' failed with %d\n", bss_up, ret));
++	}
++
++	return ret;
++}
++
++bool
++wl_cfg80211_bss_isup(struct net_device *ndev, int bsscfg_idx)
++{
++	s32 result, val;
++	bool isup = false;
++	s8 getbuf[64];
++
++	/* Check if the BSS is up */
++	*(int*)getbuf = -1;
++	result = wldev_iovar_getbuf_bsscfg(ndev, "bss", &bsscfg_idx,
++		sizeof(bsscfg_idx), getbuf, sizeof(getbuf), 0, NULL);
++	if (result != 0) {
++		WL_ERR(("'cfg bss -C %d' failed: %d\n", bsscfg_idx, result));
++		WL_ERR(("NOTE: this ioctl error is normal "
++			"when the BSS has not been created yet.\n"));
++	} else {
++		val = *(int*)getbuf;
++		val = dtoh32(val);
++		WL_DBG(("wl bss -C %d = %d\n", bsscfg_idx, val));
++		isup = (val ? TRUE : FALSE);
++	}
++	return isup;
++}
++
++static s32
++cfg80211_to_wl_iftype(uint16 type, uint16 *role, uint16 *mode)
++{
++	switch (type) {
++		case NL80211_IFTYPE_STATION:
++			*role = WLC_E_IF_ROLE_STA;
++			*mode = WL_MODE_BSS;
++			break;
++		case NL80211_IFTYPE_AP:
++			*role = WLC_E_IF_ROLE_AP;
++			*mode = WL_MODE_AP;
++			break;
++		case NL80211_IFTYPE_P2P_GO:
++			*role = WLC_E_IF_ROLE_P2P_GO;
++			*mode = WL_MODE_AP;
++			break;
++		case NL80211_IFTYPE_P2P_CLIENT:
++			*role = WLC_E_IF_ROLE_P2P_CLIENT;
++			*mode = WL_MODE_BSS;
++			break;
++		case NL80211_IFTYPE_MONITOR:
++			WL_ERR(("Unsupported mode \n"));
++			return BCME_UNSUPPORTED;
++		case NL80211_IFTYPE_ADHOC:
++			*role = WLC_E_IF_ROLE_IBSS;
++			*mode = WL_MODE_IBSS;
++			break;
++#ifdef WLMESH_CFG80211
++		case NL80211_IFTYPE_MESH_POINT:
++			*role = WLC_E_IF_ROLE_AP;
++			*mode = WL_MODE_MESH;
++			break;
++#endif
++		default:
++			WL_ERR(("Unknown interface type:0x%x\n", type));
++			return BCME_ERROR;
++	}
++	return BCME_OK;
++}
++
++static s32
++wl_if_to_cfg80211_type(uint16 role)
++{
++	switch (role) {
++	case WLC_E_IF_ROLE_STA:
++		return NL80211_IFTYPE_STATION;
++	case WLC_E_IF_ROLE_AP:
++		return NL80211_IFTYPE_AP;
++	case WLC_E_IF_ROLE_P2P_GO:
++		return NL80211_IFTYPE_P2P_GO;
++	case WLC_E_IF_ROLE_P2P_CLIENT:
++		return NL80211_IFTYPE_P2P_CLIENT;
++	case WLC_E_IF_ROLE_IBSS:
++		return NL80211_IFTYPE_ADHOC;
++	default:
++		WL_ERR(("Unknown interface role:0x%x. Forcing type station\n", role));
++		return BCME_ERROR;
++	}
++}
++
++struct net_device *
++wl_cfg80211_post_ifcreate(struct net_device *ndev,
++	wl_if_event_info *event, u8 *addr,
++	const char *name, bool rtnl_lock_reqd)
++{
++	struct bcm_cfg80211 *cfg;
++	struct net_device *primary_ndev;
++	struct net_device *new_ndev = NULL;
++	struct wireless_dev *wdev = NULL;
++	s32 iface_type;
++	s32 ret;
++	u16 mode;
++	u16 role;
++	u8 mac_addr[ETH_ALEN];
++
++	if (!ndev || !event) {
++		WL_ERR(("Wrong arg\n"));
++		return NULL;
++	}
++
++	cfg = wl_get_cfg(ndev);
++	if (!cfg) {
++		WL_ERR(("cfg null\n"));
++		return NULL;
++	}
++
++	WL_DBG(("Enter. role:%d ifidx:%d bssidx:%d\n",
++		event->role, event->ifidx, event->bssidx));
++	if (!event->ifidx || !event->bssidx) {
++		/* Fw returned primary idx (0) for virtual interface */
++		WL_ERR(("Wrong index. ifidx:%d bssidx:%d \n",
++			event->ifidx, event->bssidx));
++		return NULL;
++	}
++
++	iface_type = wl_if_to_cfg80211_type(event->role);
++	if (iface_type < 0) {
++		/* Unknown iface type */
++		WL_ERR(("Wrong iface type \n"));
++		return NULL;
++	}
++
++#ifdef WL_EXT_IAPSTA
++	if (wl_ext_iapsta_mesh_creating(ndev)) {
++		WL_MSG(ndev->name, "change iface_type to NL80211_IFTYPE_MESH_POINT\n");
++		iface_type = NL80211_IFTYPE_MESH_POINT;
++	}
++#endif
++	if (cfg80211_to_wl_iftype(iface_type, &role, &mode) < 0) {
++		/* Unsupported operating mode */
++		WL_ERR(("Unsupported operating mode \n"));
++		return NULL;
++	}
++
++	WL_DBG(("mac_ptr:%p name:%s role:%d nl80211_iftype:%d " MACDBG "\n",
++		addr, name, event->role, iface_type, MAC2STRDBG(event->mac)));
++	if (!name) {
++		/* If iface name is not provided, use dongle ifname */
++		name = event->name;
++	}
++
++	if (!addr) {
++		/* If mac address is not set, use primary mac with locally administered
++		 * bit set.
++		 */
++		primary_ndev = bcmcfg_to_prmry_ndev(cfg);
++		memcpy(mac_addr, primary_ndev->dev_addr, ETH_ALEN);
++#ifndef CUSTOMER_HW6
++		/* For customer6 builds, use primary mac address for virtual interface */
++		mac_addr[0] |= 0x02;
++#endif /* CUSTOMER_HW6 */
++		addr = mac_addr;
++	}
++
++	new_ndev = wl_cfg80211_allocate_if(cfg, event->ifidx,
++		name, addr, event->bssidx, event->name);
++	if (!new_ndev) {
++		WL_ERR(("I/F allocation failed! \n"));
++		goto fail;
++	} else {
++		WL_DBG(("I/F allocation succeeded! ifidx:0x%x bssidx:0x%x \n",
++		 event->ifidx, event->bssidx));
++	}
++
++	wdev = kzalloc(sizeof(*wdev), GFP_KERNEL);
++	if (!wdev) {
++		WL_ERR(("wireless_dev alloc failed! \n"));
++		goto fail;
++	}
++
++	wdev->wiphy = bcmcfg_to_wiphy(cfg);
++	wdev->iftype = iface_type;
++	new_ndev->ieee80211_ptr = wdev;
++	SET_NETDEV_DEV(new_ndev, wiphy_dev(wdev->wiphy));
++
++	/* Check whether mac addr is in sync with fw. If not,
++	 * apply it using cur_etheraddr.
++	 */
++	if (memcmp(addr, event->mac, ETH_ALEN) != 0) {
++		ret = wldev_iovar_setbuf_bsscfg(new_ndev, "cur_etheraddr",
++			addr, ETH_ALEN, cfg->ioctl_buf, WLC_IOCTL_MAXLEN,
++			event->bssidx, &cfg->ioctl_buf_sync);
++		if (unlikely(ret)) {
++			WL_ERR(("set cur_etheraddr Error (%d)\n", ret));
++			goto fail;
++		}
++		memcpy(new_ndev->dev_addr, addr, ETH_ALEN);
++		WL_ERR(("Applying updated mac address to firmware\n"));
++	}
++#ifdef WL_EXT_IAPSTA
++	wl_ext_iapsta_ifadding(new_ndev, event->ifidx);
++#endif /* WL_EXT_IAPSTA */
++
++	if (wl_cfg80211_register_if(cfg, event->ifidx, new_ndev, rtnl_lock_reqd) != BCME_OK) {
++		WL_ERR(("IFACE register failed \n"));
++		goto fail;
++	}
++
++	/* Initialize with the station mode params */
++	ret = wl_alloc_netinfo(cfg, new_ndev, wdev, mode,
++		PM_ENABLE, event->bssidx);
++	if (unlikely(ret)) {
++		WL_ERR(("wl_alloc_netinfo Error (%d)\n", ret));
++		goto fail;
++	}
++
++	/* Apply the mode & infra setting based on iftype */
++	if ((ret = wl_config_ifmode(cfg, new_ndev, iface_type)) < 0) {
++		WL_ERR(("config ifmode failure (%d)\n", ret));
++		goto fail;
++	}
++
++	if (mode == WL_MODE_AP) {
++		wl_set_drv_status(cfg, AP_CREATING, new_ndev);
++	}
++#ifdef WL_EXT_IAPSTA
++	wl_ext_iapsta_update_iftype(new_ndev, event->ifidx, role);
++#endif
++
++	WL_INFORM(("Host Network Interface (%s) for Secondary I/F created."
++		" cfg_iftype:%d wl_role:%d\n", new_ndev->name, iface_type, event->role));
++
++	return new_ndev;
++
++fail:
++	if (wdev)
++		kfree(wdev);
++	if (new_ndev)
++		wl_cfg80211_remove_if(cfg, event->ifidx, new_ndev, rtnl_lock_reqd);
++
++	return NULL;
++}
++
++void
++wl_cfg80211_cleanup_virtual_ifaces(struct net_device *dev, bool rtnl_lock_reqd)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	struct net_info *iter, *next;
++	struct net_device *primary_ndev;
++
++	/* Note: This function will clean up only the network interface and host
++	 * data structures. The firmware interface clean up will happen in the
++	 * during chip reset (ifconfig wlan0 down for built-in drivers/rmmod
++	 * context for the module case).
++	 */
++	primary_ndev = bcmcfg_to_prmry_ndev(cfg);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	for_each_ndev(cfg, iter, next) {
++		if (iter->ndev && (iter->ndev != primary_ndev)) {
++			WL_DBG(("Cleaning up iface:%s \n", iter->ndev->name));
++			wl_cfg80211_post_ifdel(iter->ndev, rtnl_lock_reqd);
++		}
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++}
++
++s32
++wl_cfg80211_post_ifdel(struct net_device *ndev, bool rtnl_lock_reqd)
++{
++	int ifidx = -1;
++	struct bcm_cfg80211 *cfg;
++
++	if (!ndev || !ndev->ieee80211_ptr) {
++		/* No wireless dev done for this interface */
++		return -EINVAL;
++	}
++
++	cfg = wl_get_cfg(ndev);
++	if (!cfg) {
++		WL_ERR(("cfg null\n"));
++		return BCME_ERROR;
++	}
++	ifidx = dhd_net2idx(((struct dhd_pub *)(cfg->pub))->info, ndev);
++	BCM_REFERENCE(ifidx);
++	if (ifidx <= 0) {
++		WL_ERR(("Invalid IF idx for iface:%s\n", ndev->name));
++		ASSERT(0);
++		return BCME_ERROR;
++	}
++	WL_DBG(("cfg80211_remove for iface:%s \n", ndev->name));
++	wl_cfg80211_remove_if(cfg, ifidx, ndev, rtnl_lock_reqd);
++	cfg->bss_pending_op = FALSE;
++
++	return BCME_OK;
++}
++
++#if defined(WL_VIRTUAL_APSTA) || defined(DUAL_STA_STATIC_IF)
++/* Create a Generic Network Interface and initialize it depending up on
++ * the interface type
++ */
++bcm_struct_cfgdev*
++wl_cfg80211_create_iface(struct wiphy *wiphy,
++	enum nl80211_iftype iface_type,
++	u8 *mac_addr, const char *name)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *new_ndev = NULL;
++	struct net_device *primary_ndev = NULL;
++	s32 ret = BCME_OK;
++	s32 bsscfg_idx = 0;
++	u32 timeout;
++	wl_if_event_info *event = NULL;
++	u8 addr[ETH_ALEN];
++	struct net_info *iter, *next;
++#ifdef WLMESH_CFG80211
++	u16 role = 0, mode = 0;
++#endif
++
++	WL_DBG(("Enter\n"));
++	if (!name) {
++		WL_ERR(("Interface name not provided\n"));
++		return NULL;
++	}
++	else {
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++		for_each_ndev(cfg, iter, next) {
++			if (iter->ndev) {
++				if (strcmp(iter->ndev->name, name) == 0) {
++					WL_ERR(("Interface name, %s exists !\n", iter->ndev->name));
++					return NULL;
++				}
++			}
++		}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	}
++	primary_ndev = bcmcfg_to_prmry_ndev(cfg);
++
++	if (likely(!mac_addr)) {
++		/* Use primary MAC with the locally administered bit for the
++		 *  Secondary STA I/F
++		 */
++		memcpy(addr, primary_ndev->dev_addr, ETH_ALEN);
++		addr[0] |= 0x02;
++	} else {
++		/* Use the application provided mac address (if any) */
++		memcpy(addr, mac_addr, ETH_ALEN);
++	}
++
++	if ((iface_type != NL80211_IFTYPE_STATION) && (iface_type != NL80211_IFTYPE_AP)) {
++		WL_ERR(("IFACE type:%d not supported. STA "
++					"or AP IFACE is only supported\n", iface_type));
++		return NULL;
++	}
++
++	cfg->bss_pending_op = TRUE;
++	memset(&cfg->if_event_info, 0, sizeof(cfg->if_event_info));
++
++	/* De-initialize the p2p discovery interface, if operational */
++	if (p2p_is_on(cfg)) {
++		WL_DBG(("Disabling P2P Discovery Interface \n"));
++#ifdef WL_CFG80211_P2P_DEV_IF
++		ret = wl_cfg80211_scan_stop(cfg, bcmcfg_to_p2p_wdev(cfg));
++#else
++		ret = wl_cfg80211_scan_stop(cfg, cfg->p2p_net);
++#endif
++		if (unlikely(ret < 0)) {
++			CFGP2P_ERR(("P2P scan stop failed, ret=%d\n", ret));
++		}
++
++		wl_cfgp2p_disable_discovery(cfg);
++		wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE) = 0;
++		p2p_on(cfg) = false;
++	}
++
++	/*
++	 * Intialize the firmware I/F.
++	 */
++	if (wl_customer6_legacy_chip_check(cfg, primary_ndev)) {
++		/* Use bss iovar instead of interface_create iovar */
++		ret = BCME_UNSUPPORTED;
++	} else {
++		ret = wl_cfg80211_interface_ops(cfg, primary_ndev, bsscfg_idx,
++			iface_type, 0, addr);
++	}
++	if (ret == BCME_UNSUPPORTED) {
++		/* Use bssidx 1 by default */
++		bsscfg_idx = 1;
++		if ((ret = wl_cfg80211_add_del_bss(cfg, primary_ndev,
++			bsscfg_idx, iface_type, 0, addr)) < 0) {
++			goto exit;
++		}
++	} else if (ret < 0) {
++		WL_ERR(("Interface create failed!! ret:%d \n", ret));
++		goto exit;
++	} else {
++		/* Success */
++		bsscfg_idx = ret;
++	}
++
++	WL_DBG(("Interface created!! bssidx:%d \n", bsscfg_idx));
++
++	/*
++	 * Wait till the firmware send a confirmation event back.
++	 */
++	WL_DBG(("Wait for the FW I/F Event\n"));
++	timeout = wait_event_interruptible_timeout(cfg->netif_change_event,
++		!cfg->bss_pending_op, msecs_to_jiffies(MAX_WAIT_TIME));
++	if (timeout <= 0 || cfg->bss_pending_op) {
++		WL_ERR(("ADD_IF event, didn't come. Return \n"));
++		goto exit;
++	}
++
++	event = &cfg->if_event_info;
++#ifdef WLMESH_CFG80211
++	cfg80211_to_wl_iftype(iface_type, &role, &mode);
++	event->role = role;
++#endif
++
++	/*
++	 * Since FW operation is successful,we can go ahead with the
++	 * the host interface creation.
++	 */
++	if ((new_ndev = wl_cfg80211_post_ifcreate(primary_ndev,
++		event, mac_addr, name, false))) {
++		/* Iface post ops successful. Return ndev/wdev ptr */
++		return  ndev_to_cfgdev(new_ndev);
++	}
++
++exit:
++	cfg->bss_pending_op = FALSE;
++	return NULL;
++}
++
++s32
++wl_cfg80211_del_iface(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *ndev = NULL;
++	s32 ret = BCME_OK;
++	s32 bsscfg_idx = 1;
++	u32 timeout;
++	enum nl80211_iftype iface_type = NL80211_IFTYPE_STATION;
++
++	WL_DBG(("Enter\n"));
++
++	/* If any scan is going on, abort it */
++	if (wl_get_drv_status_all(cfg, SCANNING)) {
++		WL_DBG(("Scan in progress. Aborting the scan!\n"));
++		wl_notify_escan_complete(cfg, cfg->escan_info.ndev, true, true);
++	}
++
++	ndev = (struct net_device *)cfgdev_to_ndev(cfgdev);
++	cfg->bss_pending_op = TRUE;
++	memset(&cfg->if_event_info, 0, sizeof(cfg->if_event_info));
++
++	/* Delete the firmware interface. "interface_remove" command
++	 * should go on the interface to be deleted
++	 */
++	bsscfg_idx = wl_get_bssidx_by_wdev(cfg, ndev->ieee80211_ptr);
++	if (bsscfg_idx <= 0) {
++		/* validate bsscfgidx */
++		WL_ERR(("Wrong bssidx! \n"));
++		return -EINVAL;
++	}
++	WL_DBG(("del interface. bssidx:%d", bsscfg_idx));
++	ret = wl_cfg80211_interface_ops(cfg, ndev, bsscfg_idx,
++		NL80211_IFTYPE_STATION, 1, NULL);
++	if (ret == BCME_UNSUPPORTED) {
++		if ((ret = wl_cfg80211_add_del_bss(cfg, ndev,
++			bsscfg_idx, iface_type, true, NULL)) < 0) {
++			WL_ERR(("DEL bss failed ret:%d \n", ret));
++			goto exit;
++		}
++	} else if (ret < 0) {
++		WL_ERR(("Interface DEL failed ret:%d \n", ret));
++		goto exit;
++	}
++
++	timeout = wait_event_interruptible_timeout(cfg->netif_change_event,
++		!cfg->bss_pending_op, msecs_to_jiffies(MAX_WAIT_TIME));
++	if (timeout <= 0 || cfg->bss_pending_op) {
++		WL_ERR(("timeout in waiting IF_DEL event\n"));
++	}
++
++exit:
++	ret = wl_cfg80211_post_ifdel(ndev, false);
++	if (unlikely(ret)) {
++		WL_ERR(("post_ifdel failed\n"));
++	}
++
++	return ret;
++}
++#endif /* defined(WL_VIRTUAL_APSTA) || defined(DUAL_STA_STATIC_IF) */
++
++#ifdef WLMESH_CFG80211
++s32 wl_cfg80211_set_sae_password(struct net_device *dev, char* buf, int len)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++
++	sscanf(buf, "%s %d", cfg->sae_password, &cfg->sae_password_len);
++	return 0;
++}
++
++static s32 wl_cfg80211_join_mesh(
++	struct wiphy *wiphy, struct net_device *dev,
++	const struct mesh_config *conf,
++	const struct mesh_setup *setup)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	struct ieee80211_channel *chan = setup->chandef.chan;
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 6, 0))
++	struct ieee80211_channel *chan = setup->channel;
++#endif
++	u32 param[2] = {0, 0};
++	s32 err = 0;
++	u32 bw_cap = 0;
++	u32 beacon_interval = setup->beacon_interval;
++	u32 dtim_period = setup->dtim_period;
++	size_t join_params_size;
++	struct wl_join_params join_params;
++	chanspec_t chanspec = 0;
++
++	cfg->channel = ieee80211_frequency_to_channel(chan->center_freq);
++
++	if (wl_get_drv_status(cfg, CONNECTED, dev)) {
++		struct wlc_ssid *lssid = (struct wlc_ssid *)wl_read_prof(cfg, dev, WL_PROF_SSID);
++		u8 *bssid = (u8 *)wl_read_prof(cfg, dev, WL_PROF_BSSID);
++		u32 *channel = (u32 *)wl_read_prof(cfg, dev, WL_PROF_CHAN);
++		if ((memcmp(setup->mesh_id, lssid->SSID, lssid->SSID_len) == 0) &&
++			(*channel == cfg->channel)) {
++			WL_ERR(("MESH connection already existed to " MACDBG "\n",
++				MAC2STRDBG((u8 *)wl_read_prof(cfg, dev, WL_PROF_BSSID))));
++			return -EISCONN;
++		}
++		WL_ERR(("Previous connecton existed, please disconnect mesh %s (" MACDBG ") first\n",
++			lssid->SSID, MAC2STRDBG(bssid)));
++		return -EISCONN;
++	}
++
++	if (chan) {
++		if (chan->band == IEEE80211_BAND_5GHZ)
++			param[0] = WLC_BAND_5G;
++		else if (chan->band == IEEE80211_BAND_2GHZ)
++			param[0] = WLC_BAND_2G;
++		err = wldev_iovar_getint(dev, "bw_cap", param);
++		if (unlikely(err)) {
++			WL_ERR(("Get bw_cap Failed (%d)\n", err));
++			return err;
++		}
++		bw_cap = param[0];
++		chanspec = channel_to_chanspec(wiphy, dev, cfg->channel, bw_cap);
++	}
++
++	memset(&join_params, 0, sizeof(join_params));
++	memcpy((void *)join_params.ssid.SSID, (void *)setup->mesh_id,
++		setup->mesh_id_len);
++
++	join_params.ssid.SSID_len = htod32(setup->mesh_id_len);
++	join_params.params.chanspec_list[0] = chanspec;
++	join_params.params.chanspec_num = 1;
++	wldev_iovar_setint(dev, "chanspec", chanspec);
++	join_params_size = sizeof(join_params);
++
++	wldev_iovar_setint(dev, "wpa_auth", WPA_AUTH_DISABLED);
++	wldev_iovar_setint(dev, "wsec", 0);
++
++	if (cfg->sae_password_len > 0) {
++		wldev_iovar_setint(dev, "mesh_auth_proto", 1);
++		wldev_iovar_setint(dev, "wpa_auth", WPA2_AUTH_PSK);
++		wldev_iovar_setint(dev, "wsec", AES_ENABLED);
++		wldev_iovar_setint(dev, "mfp", WL_MFP_REQUIRED);
++		WL_MSG(dev->name, "password=%s, len=%d\n",
++			cfg->sae_password, cfg->sae_password_len);
++		wldev_iovar_setbuf(dev, "sae_password", cfg->sae_password, cfg->sae_password_len,
++			cfg->ioctl_buf, WLC_IOCTL_MAXLEN, NULL);
++	} else {
++		wldev_iovar_setint(dev, "mesh_auth_proto", 0);
++		wldev_iovar_setint(dev, "mfp", WL_MFP_NONE);
++	}
++
++	if (beacon_interval) {
++		if ((err = wldev_ioctl_set(dev, WLC_SET_BCNPRD,
++			&beacon_interval, sizeof(s32))) < 0) {
++			WL_ERR(("Beacon Interval Set Error, %d\n", err));
++			return err;
++		}
++	}
++
++	if (dtim_period) {
++		if ((err = wldev_ioctl_set(dev, WLC_SET_DTIMPRD,
++			&dtim_period, sizeof(s32))) < 0) {
++			WL_ERR(("DTIM Interval Set Error, %d\n", err));
++			return err;
++		}
++	}
++	wldev_iovar_setint(dev, "mpc", 0);
++
++	WL_ERR(("JOIN %s on channel %d with chanspec 0x%4x\n",
++				join_params.ssid.SSID, cfg->channel, chanspec));
++
++	err = wldev_ioctl_set(dev, WLC_SET_SSID, &join_params,
++		join_params_size);
++
++	if (unlikely(err)) {
++		WL_ERR(("Error (%d)\n", err));
++		return err;
++	}
++
++	wl_update_prof(cfg, dev, NULL, &join_params.ssid, WL_PROF_SSID);
++	wl_update_prof(cfg, dev, NULL, &cfg->channel, WL_PROF_CHAN);
++	return err;
++}
++
++
++static s32 wl_cfg80211_leave_mesh(
++	struct wiphy *wiphy, struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 err = 0;
++	scb_val_t scbval;
++	u8 *curbssid;
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	wl_link_down(cfg);
++
++	WL_ERR(("Leave MESH\n"));
++	curbssid = wl_read_prof(cfg, dev, WL_PROF_BSSID);
++	wl_set_drv_status(cfg, DISCONNECTING, dev);
++	scbval.val = 0;
++	memcpy(&scbval.ea, curbssid, ETHER_ADDR_LEN);
++	err = wldev_ioctl_set(dev, WLC_DISASSOC, &scbval,
++		sizeof(scb_val_t));
++	if (unlikely(err)) {
++		wl_clr_drv_status(cfg, DISCONNECTING, dev);
++		WL_ERR(("error(%d)\n", err));
++		return err;
++	}
++	memset(cfg->sae_password, 0, SAE_MAX_PASSWD_LEN);
++	cfg->sae_password_len = 0;
++
++	return err;
++}
++#endif /* WLMESH_CFG80211 */
++
++static s32
++wl_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_ibss_params *params)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct cfg80211_bss *bss;
++	struct ieee80211_channel *chan;
++	struct wl_join_params join_params;
++	int scan_suppress;
++	struct cfg80211_ssid ssid;
++	s32 scan_retry = 0;
++	s32 err = 0;
++	size_t join_params_size;
++	chanspec_t chanspec = 0;
++	u32 param[2] = {0, 0};
++	u32 bw_cap = 0;
++
++	WL_TRACE(("In\n"));
++	RETURN_EIO_IF_NOT_UP(cfg);
++	WL_INFORM(("JOIN BSSID:" MACDBG "\n", MAC2STRDBG(params->bssid)));
++	if (!params->ssid || params->ssid_len <= 0 ||
++			params->ssid_len > DOT11_MAX_SSID_LEN) {
++		WL_ERR(("Invalid parameter\n"));
++		return -EINVAL;
++	}
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	chan = params->chandef.chan;
++#else
++	chan = params->channel;
++#endif /* WL_CFG80211_P2P_DEV_IF */
++	if (chan)
++		cfg->channel = ieee80211_frequency_to_channel(chan->center_freq);
++	if (wl_get_drv_status(cfg, CONNECTED, dev)) {
++		struct wlc_ssid *lssid = (struct wlc_ssid *)wl_read_prof(cfg, dev, WL_PROF_SSID);
++		u8 *bssid = (u8 *)wl_read_prof(cfg, dev, WL_PROF_BSSID);
++		u32 *channel = (u32 *)wl_read_prof(cfg, dev, WL_PROF_CHAN);
++		if (!params->bssid || ((memcmp(params->bssid, bssid, ETHER_ADDR_LEN) == 0) &&
++			(memcmp(params->ssid, lssid->SSID, lssid->SSID_len) == 0) &&
++			(*channel == cfg->channel))) {
++			WL_ERR(("Connection already existed to " MACDBG "\n",
++				MAC2STRDBG((u8 *)wl_read_prof(cfg, dev, WL_PROF_BSSID))));
++			return -EISCONN;
++		}
++		WL_ERR(("Ignore Previous connecton to %s (" MACDBG ")\n",
++			lssid->SSID, MAC2STRDBG(bssid)));
++	}
++
++	/* remove the VSIE */
++	wl_cfg80211_ibss_vsie_delete(dev);
++
++	bss = cfg80211_get_ibss(wiphy, NULL, params->ssid, params->ssid_len);
++	if (!bss) {
++		if (IBSS_INITIAL_SCAN_ALLOWED == TRUE) {
++			memcpy(ssid.ssid, params->ssid, params->ssid_len);
++			ssid.ssid_len = params->ssid_len;
++			do {
++				if (unlikely
++					(__wl_cfg80211_scan(wiphy, dev, NULL, &ssid) ==
++					 -EBUSY)) {
++					wl_delay(150);
++				} else {
++					break;
++				}
++			} while (++scan_retry < WL_SCAN_RETRY_MAX);
++
++			/* rtnl lock code is removed here. don't see why rtnl lock
++			 * needs to be released.
++			 */
++
++			/* wait 4 secons till scan done.... */
++			schedule_timeout_interruptible(msecs_to_jiffies(4000));
++
++			bss = cfg80211_get_ibss(wiphy, NULL,
++				params->ssid, params->ssid_len);
++		}
++	}
++	if (bss && ((IBSS_COALESCE_ALLOWED == TRUE) ||
++		((IBSS_COALESCE_ALLOWED == FALSE) && params->bssid &&
++		!memcmp(bss->bssid, params->bssid, ETHER_ADDR_LEN)))) {
++		cfg->ibss_starter = false;
++		WL_DBG(("Found IBSS\n"));
++	} else {
++		cfg->ibss_starter = true;
++	}
++
++	if (bss) {
++		CFG80211_PUT_BSS(wiphy, bss);
++	}
++
++	if (chan) {
++		if (chan->band == IEEE80211_BAND_5GHZ)
++			param[0] = WLC_BAND_5G;
++		else if (chan->band == IEEE80211_BAND_2GHZ)
++			param[0] = WLC_BAND_2G;
++		err = wldev_iovar_getint(dev, "bw_cap", param);
++		if (unlikely(err)) {
++			WL_ERR(("Get bw_cap Failed (%d)\n", err));
++			return err;
++		}
++		bw_cap = param[0];
++		chanspec = channel_to_chanspec(wiphy, dev, cfg->channel, bw_cap);
++	}
++	/*
++	 * Join with specific BSSID and cached SSID
++	 * If SSID is zero join based on BSSID only
++	 */
++	memset(&join_params, 0, sizeof(join_params));
++	memcpy((void *)join_params.ssid.SSID, (void *)params->ssid,
++		params->ssid_len);
++	join_params.ssid.SSID_len = htod32(params->ssid_len);
++	if (params->bssid) {
++		memcpy(&join_params.params.bssid, params->bssid, ETHER_ADDR_LEN);
++		err = wldev_ioctl_set(dev, WLC_SET_DESIRED_BSSID, &join_params.params.bssid,
++			ETHER_ADDR_LEN);
++		if (unlikely(err)) {
++			WL_ERR(("Error (%d)\n", err));
++			return err;
++		}
++	} else
++		memset(&join_params.params.bssid, 0, ETHER_ADDR_LEN);
++
++	if (IBSS_INITIAL_SCAN_ALLOWED == FALSE) {
++		scan_suppress = TRUE;
++		/* Set the SCAN SUPPRESS Flag in the firmware to skip join scan */
++		err = wldev_ioctl_set(dev, WLC_SET_SCANSUPPRESS,
++			&scan_suppress, sizeof(int));
++		if (unlikely(err)) {
++			WL_ERR(("Scan Suppress Setting Failed (%d)\n", err));
++			return err;
++		}
++	}
++
++	join_params.params.chanspec_list[0] = chanspec;
++	join_params.params.chanspec_num = 1;
++	wldev_iovar_setint(dev, "chanspec", chanspec);
++	join_params_size = sizeof(join_params);
++
++	/* Disable Authentication, IBSS will add key if it required */
++	wldev_iovar_setint(dev, "wpa_auth", WPA_AUTH_DISABLED);
++	wldev_iovar_setint(dev, "wsec", 0);
++
++	err = wldev_ioctl_set(dev, WLC_SET_SSID, &join_params,
++		join_params_size);
++	if (unlikely(err)) {
++		WL_ERR(("Error (%d)\n", err));
++		return err;
++	}
++
++	if (IBSS_INITIAL_SCAN_ALLOWED == FALSE) {
++		scan_suppress = FALSE;
++		/* Reset the SCAN SUPPRESS Flag */
++		err = wldev_ioctl_set(dev, WLC_SET_SCANSUPPRESS,
++			&scan_suppress, sizeof(int));
++		if (unlikely(err)) {
++			WL_ERR(("Reset Scan Suppress Flag Failed (%d)\n", err));
++			return err;
++		}
++	}
++	wl_update_prof(cfg, dev, NULL, &join_params.ssid, WL_PROF_SSID);
++	wl_update_prof(cfg, dev, NULL, &cfg->channel, WL_PROF_CHAN);
++#ifdef WL_RELMCAST
++	cfg->rmc_event_seq = 0; /* initialize rmcfail sequence */
++#endif /* WL_RELMCAST */
++	return err;
++}
++
++static s32 wl_cfg80211_leave_ibss(struct wiphy *wiphy, struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 err = 0;
++	scb_val_t scbval;
++	u8 *curbssid;
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	wl_link_down(cfg);
++
++	WL_ERR(("Leave IBSS\n"));
++	curbssid = wl_read_prof(cfg, dev, WL_PROF_BSSID);
++	wl_set_drv_status(cfg, DISCONNECTING, dev);
++	scbval.val = 0;
++	memcpy(&scbval.ea, curbssid, ETHER_ADDR_LEN);
++	err = wldev_ioctl_set(dev, WLC_DISASSOC, &scbval,
++		sizeof(scb_val_t));
++	if (unlikely(err)) {
++		wl_clr_drv_status(cfg, DISCONNECTING, dev);
++		WL_ERR(("error(%d)\n", err));
++		return err;
++	}
++
++	/* remove the VSIE */
++	wl_cfg80211_ibss_vsie_delete(dev);
++
++	return err;
++}
++
++#ifdef MFP
++static int wl_cfg80211_get_rsn_capa(bcm_tlv_t *wpa2ie, u8** rsn_cap)
++{
++	u16 suite_count;
++	wpa_suite_mcast_t *mcast;
++	wpa_suite_ucast_t *ucast;
++	u16 len;
++	wpa_suite_auth_key_mgmt_t *mgmt;
++
++	if (!wpa2ie)
++		return -1;
++
++	len = wpa2ie->len;
++	mcast = (wpa_suite_mcast_t *)&wpa2ie->data[WPA2_VERSION_LEN];
++	if ((len -= WPA_SUITE_LEN) <= 0)
++		return BCME_BADLEN;
++	ucast = (wpa_suite_ucast_t *)&mcast[1];
++	suite_count = ltoh16_ua(&ucast->count);
++	if ((suite_count > NL80211_MAX_NR_CIPHER_SUITES) ||
++		(len -= (WPA_IE_SUITE_COUNT_LEN +
++		(WPA_SUITE_LEN * suite_count))) <= 0)
++		return BCME_BADLEN;
++
++	mgmt = (wpa_suite_auth_key_mgmt_t *)&ucast->list[suite_count];
++	suite_count = ltoh16_ua(&mgmt->count);
++
++	if ((suite_count > NL80211_MAX_NR_CIPHER_SUITES) ||
++		(len -= (WPA_IE_SUITE_COUNT_LEN +
++		(WPA_SUITE_LEN * suite_count))) >= RSN_CAP_LEN) {
++		rsn_cap[0] = (u8 *)&mgmt->list[suite_count];
++	} else
++		return BCME_BADLEN;
++
++	return 0;
++}
++#endif /* MFP */
++
++static s32
++wl_set_wpa_version(struct net_device *dev, struct cfg80211_connect_params *sme)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	struct wl_security *sec;
++	s32 val = 0;
++	s32 err = 0;
++	s32 bssidx;
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	if (sme->crypto.wpa_versions & NL80211_WPA_VERSION_1)
++		val = WPA_AUTH_PSK |
++			WPA_AUTH_UNSPECIFIED;
++	else if (sme->crypto.wpa_versions & NL80211_WPA_VERSION_2)
++		val = WPA2_AUTH_PSK|
++			WPA2_AUTH_UNSPECIFIED;
++	else
++		val = WPA_AUTH_DISABLED;
++
++	if (is_wps_conn(sme))
++		val = WPA_AUTH_DISABLED;
++
++#ifdef BCMWAPI_WPI
++	if (sme->crypto.wpa_versions & NL80211_WAPI_VERSION_1) {
++		WL_DBG((" * wl_set_wpa_version, set wpa_auth"
++			" to WPA_AUTH_WAPI 0x400"));
++		val = WAPI_AUTH_PSK | WAPI_AUTH_UNSPECIFIED;
++	}
++#endif
++	WL_DBG(("setting wpa_auth to 0x%0x\n", val));
++	err = wldev_iovar_setint_bsscfg(dev, "wpa_auth", val, bssidx);
++	if (unlikely(err)) {
++		WL_ERR(("set wpa_auth failed (%d)\n", err));
++		return err;
++	}
++	sec = wl_read_prof(cfg, dev, WL_PROF_SEC);
++	sec->wpa_versions = sme->crypto.wpa_versions;
++	return err;
++}
++ 
++#ifdef BCMWAPI_WPI
++static s32
++wl_set_set_wapi_ie(struct net_device *dev, struct cfg80211_connect_params *sme)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	s32 err = 0;
++	s32 bssidx;
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	WL_DBG((" %s \n", __FUNCTION__));
++
++	if (sme->crypto.wpa_versions & NL80211_WAPI_VERSION_1) {
++		err = wldev_iovar_setbuf_bsscfg(dev, "wapiie", (void *)sme->ie, sme->ie_len,
++			cfg->ioctl_buf, WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++
++		if (unlikely(err)) {
++			WL_ERR(("===> set_wapi_ie Error (%d)\n", err));
++			return err;
++		}
++	} else
++		WL_DBG((" * skip \n"));
++	return err;
++}
++#endif /* BCMWAPI_WPI */
++
++static s32
++wl_set_auth_type(struct net_device *dev, struct cfg80211_connect_params *sme)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	struct wl_security *sec;
++	s32 val = 0;
++	s32 err = 0;
++	s32 bssidx;
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	switch (sme->auth_type) {
++	case NL80211_AUTHTYPE_OPEN_SYSTEM:
++		val = WL_AUTH_OPEN_SYSTEM;
++		WL_DBG(("open system\n"));
++		break;
++	case NL80211_AUTHTYPE_SHARED_KEY:
++		val = WL_AUTH_SHARED_KEY;
++		WL_DBG(("shared key\n"));
++		break;
++	case NL80211_AUTHTYPE_AUTOMATIC:
++		val = WL_AUTH_OPEN_SHARED;
++		WL_DBG(("automatic\n"));
++		break;
++#ifdef WL_SAE
++	case NL80211_AUTHTYPE_SAE:
++		val = WL_AUTH_OPEN_SHARED;
++		WL_DBG(("sae\n"));
++		break;
++#endif /* WL_SAE */
++	default:
++		val = 2;
++		WL_ERR(("invalid auth type (%d)\n", sme->auth_type));
++		break;
++	}
++
++	err = wldev_iovar_setint_bsscfg(dev, "auth", val, bssidx);
++	if (unlikely(err)) {
++		WL_ERR(("set auth failed (%d)\n", err));
++		return err;
++	}
++	sec = wl_read_prof(cfg, dev, WL_PROF_SEC);
++	sec->auth_type = sme->auth_type;
++	return err;
++}
++
++static s32
++wl_set_set_cipher(struct net_device *dev, struct cfg80211_connect_params *sme)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	struct wl_security *sec;
++	s32 pval = 0;
++	s32 gval = 0;
++	s32 err = 0;
++	s32 wsec_val = 0;
++	s32 bssidx;
++#ifdef BCMWAPI_WPI
++	s32 val = 0;
++#endif
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	if (sme->crypto.n_ciphers_pairwise) {
++		switch (sme->crypto.ciphers_pairwise[0]) {
++		case WLAN_CIPHER_SUITE_WEP40:
++		case WLAN_CIPHER_SUITE_WEP104:
++			pval = WEP_ENABLED;
++			break;
++		case WLAN_CIPHER_SUITE_TKIP:
++			pval = TKIP_ENABLED;
++			break;
++		case WLAN_CIPHER_SUITE_CCMP:
++		case WLAN_CIPHER_SUITE_AES_CMAC:
++			pval = AES_ENABLED;
++			break;
++#ifdef BCMWAPI_WPI
++		case WLAN_CIPHER_SUITE_SMS4:
++			val = SMS4_ENABLED;
++			pval = SMS4_ENABLED;
++			break;
++#endif
++		default:
++			WL_ERR(("invalid cipher pairwise (%d)\n",
++				sme->crypto.ciphers_pairwise[0]));
++			return -EINVAL;
++		}
++	}
++	if (sme->crypto.cipher_group) {
++		switch (sme->crypto.cipher_group) {
++		case WLAN_CIPHER_SUITE_WEP40:
++		case WLAN_CIPHER_SUITE_WEP104:
++			gval = WEP_ENABLED;
++			break;
++		case WLAN_CIPHER_SUITE_TKIP:
++			gval = TKIP_ENABLED;
++			break;
++		case WLAN_CIPHER_SUITE_CCMP:
++			gval = AES_ENABLED;
++			break;
++		case WLAN_CIPHER_SUITE_AES_CMAC:
++			gval = AES_ENABLED;
++			break;
++#ifdef BCMWAPI_WPI
++		case WLAN_CIPHER_SUITE_SMS4:
++			val = SMS4_ENABLED;
++			gval = SMS4_ENABLED;
++			break;
++#endif
++		default:
++			WL_ERR(("invalid cipher group (%d)\n",
++				sme->crypto.cipher_group));
++			return -EINVAL;
++		}
++	}
++
++	WL_DBG(("pval (%d) gval (%d)\n", pval, gval));
++
++	if (is_wps_conn(sme)) {
++		if (sme->privacy)
++			err = wldev_iovar_setint_bsscfg(dev, "wsec", 4, bssidx);
++		else
++			/* WPS-2.0 allows no security */
++			err = wldev_iovar_setint_bsscfg(dev, "wsec", 0, bssidx);
++	} else {
++#ifdef BCMWAPI_WPI
++		if (sme->crypto.cipher_group == WLAN_CIPHER_SUITE_SMS4) {
++			WL_DBG((" NO, is_wps_conn, WAPI set to SMS4_ENABLED"));
++			err = wldev_iovar_setint_bsscfg(dev, "wsec", val, bssidx);
++		} else {
++#endif
++			WL_DBG((" NO, is_wps_conn, Set pval | gval to WSEC"));
++			wsec_val = pval | gval;
++
++			WL_DBG((" Set WSEC to fW 0x%x \n", wsec_val));
++			err = wldev_iovar_setint_bsscfg(dev, "wsec",
++				wsec_val, bssidx);
++#ifdef BCMWAPI_WPI
++		}
++#endif
++	}
++	if (unlikely(err)) {
++		WL_ERR(("error (%d)\n", err));
++		return err;
++	}
++
++	sec = wl_read_prof(cfg, dev, WL_PROF_SEC);
++	sec->cipher_pairwise = sme->crypto.ciphers_pairwise[0];
++	sec->cipher_group = sme->crypto.cipher_group;
++
++	return err;
++}
++
++#ifdef MFP
++static s32
++wl_cfg80211_set_mfp(struct bcm_cfg80211 *cfg,
++	struct net_device *dev,
++	struct cfg80211_connect_params *sme)
++{
++	s32 mfp = WL_MFP_NONE;
++	s32 current_mfp = WL_MFP_NONE;
++	bcm_tlv_t *wpa2_ie;
++	u8* rsn_cap = NULL;
++	bool fw_support = false;
++	int err, count = 0;
++	u8 *eptr = NULL, *ptr = NULL;
++	u8* group_mgmt_cs = NULL;
++	wpa_pmkid_list_t* pmkid = NULL;
++
++	if (!sme) {
++		/* No connection params from userspace, Do nothing. */
++		return 0;
++	}
++
++	/* Check fw support and retreive current mfp val */
++	err = wldev_iovar_getint(dev, "mfp", &current_mfp);
++	if (!err) {
++		fw_support = true;
++	}
++
++	/* Parse the wpa2ie to decode the MFP capablity */
++	if (((wpa2_ie = bcm_parse_tlvs((u8 *)sme->ie, sme->ie_len,
++			DOT11_MNG_RSN_ID)) != NULL) &&
++			(wl_cfg80211_get_rsn_capa(wpa2_ie, &rsn_cap) == 0)) {
++		/* Check for MFP cap in the RSN capability field */
++		if (rsn_cap[0] & RSN_CAP_MFPR) {
++			mfp = WL_MFP_REQUIRED;
++		} else if (rsn_cap[0] & RSN_CAP_MFPC) {
++			mfp = WL_MFP_CAPABLE;
++		}
++
++		/*
++		 * eptr --> end/last byte addr of wpa2_ie
++		 * ptr --> to keep track of current/required byte addr
++		 */
++		eptr = (u8*)wpa2_ie + (wpa2_ie->len + TLV_HDR_LEN);
++		/* pointing ptr to the next byte after rns_cap */
++		ptr = (u8*)rsn_cap + RSN_CAP_LEN;
++		if (mfp && (eptr - ptr) >= WPA2_PMKID_COUNT_LEN) {
++			/* pmkid now to point to 1st byte addr of pmkid in wpa2_ie */
++			pmkid = (wpa_pmkid_list_t*)ptr;
++			count = pmkid->count.low | (pmkid->count.high << 8);
++			/* ptr now to point to last byte addr of pmkid */
++			ptr = (u8*)pmkid + (count * WPA2_PMKID_LEN
++				+ WPA2_PMKID_COUNT_LEN);
++			if ((eptr - ptr) >= WPA_SUITE_LEN) {
++				/* group_mgmt_cs now to point to first byte addr of bip */
++				group_mgmt_cs = ptr;
++			}
++		}
++	}
++
++	WL_DBG((" mfp:%d wpa2_ie ptr:%p rsn_cap 0x%x%x fw mfp support:%d\n",
++		mfp, wpa2_ie, rsn_cap[0], rsn_cap[1], fw_support));
++
++	if (fw_support == false) {
++		if (mfp == WL_MFP_REQUIRED) {
++			/* if mfp > 0, mfp capability set in wpa ie, but
++			 * FW indicated error for mfp. Propagate the error up.
++			 */
++			WL_ERR(("mfp capability found in wpaie. But fw doesn't "
++				"seem to support MFP\n"));
++			return -EINVAL;
++		} else {
++			/* Firmware doesn't support mfp. But since connection request
++			 * is for non-mfp case, don't bother.
++			 */
++			return 0;
++		}
++	} else if (mfp != current_mfp) {
++		err = wldev_iovar_setint(dev, "mfp", mfp);
++		if (unlikely(err)) {
++			WL_ERR(("mfp (%d) set failed ret:%d \n", mfp, err));
++			return err;
++		}
++		WL_DBG(("mfp set to 0x%x \n", mfp));
++	}
++
++	if (group_mgmt_cs && bcmp((const uint8 *)WPA2_OUI,
++			group_mgmt_cs, (WPA_SUITE_LEN - 1)) == 0) {
++		WL_DBG(("BIP is found\n"));
++		err = wldev_iovar_setbuf(dev, "bip",
++				group_mgmt_cs, WPA_SUITE_LEN, cfg->ioctl_buf,
++				WLC_IOCTL_SMLEN, &cfg->ioctl_buf_sync);
++		/*
++		 * Dont return failure for unsupported cases
++		 * of bip iovar for backward compatibility
++		 */
++		if (err != BCME_UNSUPPORTED && err < 0) {
++			WL_ERR(("bip set error (%d)\n", err));
++			return err;
++		}
++	}
++
++	return 0;
++}
++#endif /* MFP */
++
++static s32
++wl_set_key_mgmt(struct net_device *dev, struct cfg80211_connect_params *sme)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	struct wl_security *sec;
++	s32 val = 0;
++	s32 err = 0;
++	s32 bssidx;
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	if (sme->crypto.n_akm_suites) {
++		err = wldev_iovar_getint(dev, "wpa_auth", &val);
++		if (unlikely(err)) {
++			WL_ERR(("could not get wpa_auth (%d)\n", err));
++			return err;
++		}
++		if (val & (WPA_AUTH_PSK |
++			WPA_AUTH_UNSPECIFIED)) {
++			switch (sme->crypto.akm_suites[0]) {
++			case WLAN_AKM_SUITE_8021X:
++				val = WPA_AUTH_UNSPECIFIED;
++				break;
++			case WLAN_AKM_SUITE_PSK:
++				val = WPA_AUTH_PSK;
++				break;
++			default:
++				WL_ERR(("invalid akm suite (0x%x)\n",
++					sme->crypto.akm_suites[0]));
++				return -EINVAL;
++			}
++		} else if (val & (WPA2_AUTH_PSK |
++			WPA2_AUTH_UNSPECIFIED)) {
++			switch (sme->crypto.akm_suites[0]) {
++			case WLAN_AKM_SUITE_8021X:
++				val = WPA2_AUTH_UNSPECIFIED;
++				break;
++#ifdef MFP
++#ifdef CUSTOMER_HW6
++			case WL_AKM_SUITE_SHA256_1X:
++				if (wl_customer6_legacy_chip_check(cfg,	dev)) {
++					val = WPA2_AUTH_UNSPECIFIED;
++				} else {
++					val = WPA2_AUTH_1X_SHA256;
++				}
++				break;
++			case WL_AKM_SUITE_SHA256_PSK:
++				if (wl_customer6_legacy_chip_check(cfg,	dev)) {
++					val = WPA2_AUTH_PSK;
++				} else {
++					val = WPA2_AUTH_PSK_SHA256;
++				}
++				break;
++#else
++			case WL_AKM_SUITE_SHA256_1X:
++				val = WPA2_AUTH_1X_SHA256;
++				break;
++			case WL_AKM_SUITE_SHA256_PSK:
++				val = WPA2_AUTH_PSK_SHA256;
++				break;
++#endif /* CUSTOMER_HW6 */
++#endif /* MFP */
++#if defined(WLFBT) && defined(WLAN_AKM_SUITE_FT_8021X)
++			case WLAN_AKM_SUITE_FT_8021X:
++				val = WPA2_AUTH_UNSPECIFIED | WPA2_AUTH_FT;
++				break;
++#endif
++#if defined(WLFBT) && defined(WLAN_AKM_SUITE_FT_PSK)
++			case WLAN_AKM_SUITE_FT_PSK:
++				val = WPA2_AUTH_PSK | WPA2_AUTH_FT;
++				break;
++#endif
++			case WLAN_AKM_SUITE_PSK:
++				val = WPA2_AUTH_PSK;
++				break;
++#ifdef WL_SAE
++			case WLAN_AKM_SUITE_SAE:
++				val = WPA3_AUTH_SAE_PSK;
++				break;
++#endif /* WL_SAE */
++			default:
++				WL_ERR(("invalid akm suite (0x%x)\n",
++					sme->crypto.akm_suites[0]));
++				return -EINVAL;
++			}
++		}
++#ifdef BCMWAPI_WPI
++		else if (val & (WAPI_AUTH_PSK | WAPI_AUTH_UNSPECIFIED)) {
++			switch (sme->crypto.akm_suites[0]) {
++			case WLAN_AKM_SUITE_WAPI_CERT:
++				val = WAPI_AUTH_UNSPECIFIED;
++				break;
++			case WLAN_AKM_SUITE_WAPI_PSK:
++				val = WAPI_AUTH_PSK;
++				break;
++			default:
++				WL_ERR(("invalid cipher group (%d)\n",
++					sme->crypto.cipher_group));
++				return -EINVAL;
++			}
++		}
++#endif
++
++#ifdef MFP
++		if ((err = wl_cfg80211_set_mfp(cfg, dev, sme)) < 0) {
++			WL_ERR(("MFP set failed err:%d\n", err));
++			return -EINVAL;
++		}
++#endif /* MFP */
++
++		WL_DBG(("setting wpa_auth to 0x%x\n", val));
++		err = wldev_iovar_setint_bsscfg(dev, "wpa_auth", val, bssidx);
++		if (unlikely(err)) {
++			WL_ERR(("could not set wpa_auth (0x%x)\n", err));
++			return err;
++		}
++	}
++	sec = wl_read_prof(cfg, dev, WL_PROF_SEC);
++	sec->wpa_auth = sme->crypto.akm_suites[0];
++
++	return err;
++}
++
++static s32
++wl_set_set_sharedkey(struct net_device *dev,
++	struct cfg80211_connect_params *sme)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	struct wl_security *sec;
++	struct wl_wsec_key key;
++	s32 val;
++	s32 err = 0;
++	s32 bssidx;
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	WL_DBG(("key len (%d)\n", sme->key_len));
++	if (sme->key_len) {
++		sec = wl_read_prof(cfg, dev, WL_PROF_SEC);
++		WL_DBG(("wpa_versions 0x%x cipher_pairwise 0x%x\n",
++			sec->wpa_versions, sec->cipher_pairwise));
++		if (!(sec->wpa_versions & (NL80211_WPA_VERSION_1 |
++#ifdef BCMWAPI_WPI
++			NL80211_WPA_VERSION_2 | NL80211_WAPI_VERSION_1)) &&
++#else
++			NL80211_WPA_VERSION_2)) &&
++#endif
++			(sec->cipher_pairwise & (WLAN_CIPHER_SUITE_WEP40 |
++#ifdef BCMWAPI_WPI
++		    WLAN_CIPHER_SUITE_WEP104 | WLAN_CIPHER_SUITE_SMS4)))
++#else
++		    WLAN_CIPHER_SUITE_WEP104)))
++#endif
++		{
++			memset(&key, 0, sizeof(key));
++			key.len = (u32) sme->key_len;
++			key.index = (u32) sme->key_idx;
++			if (unlikely(key.len > sizeof(key.data))) {
++				WL_ERR(("Too long key length (%u)\n", key.len));
++				return -EINVAL;
++			}
++			memcpy(key.data, sme->key, key.len);
++			key.flags = WL_PRIMARY_KEY;
++			switch (sec->cipher_pairwise) {
++			case WLAN_CIPHER_SUITE_WEP40:
++				key.algo = CRYPTO_ALGO_WEP1;
++				break;
++			case WLAN_CIPHER_SUITE_WEP104:
++				key.algo = CRYPTO_ALGO_WEP128;
++				break;
++#ifdef BCMWAPI_WPI
++			case WLAN_CIPHER_SUITE_SMS4:
++				key.algo = CRYPTO_ALGO_SMS4;
++				break;
++#endif
++			default:
++				WL_ERR(("Invalid algorithm (%d)\n",
++					sme->crypto.ciphers_pairwise[0]));
++				return -EINVAL;
++			}
++			/* Set the new key/index */
++			WL_DBG(("key length (%d) key index (%d) algo (%d)\n",
++				key.len, key.index, key.algo));
++			WL_DBG(("key \"%s\"\n", key.data));
++			swap_key_from_BE(&key);
++			err = wldev_iovar_setbuf_bsscfg(dev, "wsec_key", &key, sizeof(key),
++				cfg->ioctl_buf, WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++			if (unlikely(err)) {
++				WL_ERR(("WLC_SET_KEY error (%d)\n", err));
++				return err;
++			}
++			if (sec->auth_type == NL80211_AUTHTYPE_SHARED_KEY) {
++				WL_DBG(("set auth_type to shared key\n"));
++				val = WL_AUTH_SHARED_KEY;	/* shared key */
++				err = wldev_iovar_setint_bsscfg(dev, "auth", val, bssidx);
++				if (unlikely(err)) {
++					WL_ERR(("set auth failed (%d)\n", err));
++					return err;
++				}
++			}
++		}
++	}
++	return err;
++}
++
++#if defined(ESCAN_RESULT_PATCH)
++static u8 connect_req_bssid[6];
++static u8 broad_bssid[6];
++#endif /* ESCAN_RESULT_PATCH */
++
++
++
++#if defined(CUSTOM_SET_CPUCORE) || defined(CONFIG_TCPACK_FASTTX)
++static bool wl_get_chan_isvht80(struct net_device *net, dhd_pub_t *dhd)
++{
++	u32 chanspec = 0;
++	bool isvht80 = 0;
++
++	if (wldev_iovar_getint(net, "chanspec", (s32 *)&chanspec) == BCME_OK)
++		chanspec = wl_chspec_driver_to_host(chanspec);
++
++	isvht80 = chanspec & WL_CHANSPEC_BW_80;
++	WL_INFORM(("%s: chanspec(%x:%d)\n", __FUNCTION__, chanspec, isvht80));
++
++	return isvht80;
++}
++#endif /* CUSTOM_SET_CPUCORE || CONFIG_TCPACK_FASTTX */
++
++int wl_cfg80211_cleanup_mismatch_status(struct net_device *dev, struct bcm_cfg80211 *cfg,
++	bool disassociate)
++{
++	scb_val_t scbval;
++	int err = TRUE;
++	int wait_cnt;
++
++	if (disassociate) {
++		WL_ERR(("Disassociate previous connection!\n"));
++		wl_set_drv_status(cfg, DISCONNECTING, dev);
++		scbval.val = DOT11_RC_DISASSOC_LEAVING;
++		scbval.val = htod32(scbval.val);
++
++		err = wldev_ioctl_set(dev, WLC_DISASSOC, &scbval,
++				sizeof(scb_val_t));
++		if (unlikely(err)) {
++			wl_clr_drv_status(cfg, DISCONNECTING, dev);
++			WL_ERR(("error (%d)\n", err));
++			return err;
++		}
++		wait_cnt = 500/10;
++	} else {
++		wait_cnt = 200/10;
++		WL_ERR(("Waiting for previous DISCONNECTING status!\n"));
++		if (wl_get_drv_status(cfg, DISCONNECTING, dev)) {
++			wl_clr_drv_status(cfg, DISCONNECTING, dev);
++		}
++	}
++
++	while (wl_get_drv_status(cfg, DISCONNECTING, dev) && wait_cnt) {
++		WL_DBG(("Waiting for disconnection terminated, wait_cnt: %d\n",
++			wait_cnt));
++		wait_cnt--;
++		OSL_SLEEP(10);
++	}
++
++	if (wait_cnt == 0) {
++		WL_ERR(("DISCONNECING clean up failed!\n"));
++		/* Clear DISCONNECTING driver status as we have made sufficient attempts
++		* for driver clean up.
++		*/
++		wl_clr_drv_status(cfg, DISCONNECTING, dev);
++		return BCME_NOTREADY;
++	}
++	return BCME_OK;
++}
++
++#define MAX_SCAN_ABORT_WAIT_CNT 20
++#define WAIT_SCAN_ABORT_OSL_SLEEP_TIME 10
++
++static s32
++wl_cfg80211_connect(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_connect_params *sme)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct ieee80211_channel *chan = sme->channel;
++	wl_extjoin_params_t *ext_join_params;
++	struct wl_join_params join_params;
++	size_t join_params_size;
++	dhd_pub_t *dhdp =  (dhd_pub_t *)(cfg->pub);
++	s32 err = 0;
++	wpa_ie_fixed_t *wpa_ie;
++	bcm_tlv_t *wpa2_ie;
++	u8* wpaie  = 0;
++	u32 wpaie_len = 0;
++	u32 chan_cnt = 0;
++	struct ether_addr bssid;
++	s32 bssidx = -1;
++#if (defined(BCM4359_CHIP) || !defined(ESCAN_RESULT_PATCH))
++	int wait_cnt;
++#endif
++	char sec[32];
++
++	WL_DBG(("In\n"));
++	BCM_REFERENCE(dhdp);
++
++#ifdef WLMESH
++	wl_config_ifmode(cfg, dev, dev->ieee80211_ptr->iftype);
++#endif
++#if defined(SUPPORT_RANDOM_MAC_SCAN)
++	wl_cfg80211_set_random_mac(dev, FALSE);
++#endif /* SUPPORT_RANDOM_MAC_SCAN */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))
++	if (sme->channel_hint) {
++		chan = sme->channel_hint;
++		WL_DBG(("channel_hint (%d), channel_hint center_freq (%d)\n",
++			ieee80211_frequency_to_channel(sme->channel_hint->center_freq),
++			sme->channel_hint->center_freq));
++	}
++	if (sme->bssid_hint) {
++		sme->bssid = sme->bssid_hint;
++		WL_DBG(("bssid_hint "MACDBG" \n", MAC2STRDBG(sme->bssid_hint)));
++	}
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0) */
++
++	if (unlikely(!sme->ssid)) {
++		WL_ERR(("Invalid ssid\n"));
++		return -EOPNOTSUPP;
++	}
++
++	if (unlikely(sme->ssid_len > DOT11_MAX_SSID_LEN)) {
++		WL_ERR(("Invalid SSID info: SSID=%s, length=%zd\n",
++			sme->ssid, sme->ssid_len));
++		return -EINVAL;
++	}
++
++	WL_DBG(("SME IE : len=%zu\n", sme->ie_len));
++	if (sme->ie != NULL && sme->ie_len > 0 && (wl_dbg_level & WL_DBG_DBG)) {
++		prhex(NULL, (uchar *)sme->ie, sme->ie_len);
++	}
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++
++	/*
++	 * Cancel ongoing scan to sync up with sme state machine of cfg80211.
++	 */
++#if (defined(BCM4359_CHIP) || !defined(ESCAN_RESULT_PATCH))
++	if (cfg->scan_request) {
++		WL_TRACE_HW4(("Aborting the scan! \n"));
++		wl_cfg80211_scan_abort(cfg);
++		wait_cnt = MAX_SCAN_ABORT_WAIT_CNT;
++		while (wl_get_drv_status(cfg, SCANNING, dev) && wait_cnt) {
++			WL_DBG(("Waiting for SCANNING terminated, wait_cnt: %d\n", wait_cnt));
++			wait_cnt--;
++			OSL_SLEEP(WAIT_SCAN_ABORT_OSL_SLEEP_TIME);
++		}
++		if (wl_get_drv_status(cfg, SCANNING, dev)) {
++			wl_notify_escan_complete(cfg, dev, true, true);
++		}
++	}
++#endif
++#ifdef WL_SCHED_SCAN
++	/* Locks are taken in wl_cfg80211_sched_scan_stop()
++	 * A start scan occuring during connect is unlikely
++	 */
++	if (cfg->sched_scan_req) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++		wl_cfg80211_sched_scan_stop(wiphy, bcmcfg_to_prmry_ndev(cfg), 0);
++#else
++		wl_cfg80211_sched_scan_stop(wiphy, bcmcfg_to_prmry_ndev(cfg));
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)) */
++	}
++#endif
++#if defined(ESCAN_RESULT_PATCH)
++	if (sme->bssid)
++		memcpy(connect_req_bssid, sme->bssid, ETHER_ADDR_LEN);
++	else
++		bzero(connect_req_bssid, ETHER_ADDR_LEN);
++	bzero(broad_bssid, ETHER_ADDR_LEN);
++#endif
++#if defined(USE_DYNAMIC_MAXPKT_RXGLOM)
++	maxrxpktglom = 0;
++#endif
++	if (wl_get_drv_status(cfg, CONNECTING, dev) || wl_get_drv_status(cfg, CONNECTED, dev)) {
++		/* set nested connect bit to identify the context */
++		wl_set_drv_status(cfg, NESTED_CONNECT, dev);
++		/* DHD prev status is CONNECTING/CONNECTED */
++		err = wl_cfg80211_cleanup_mismatch_status(dev, cfg, TRUE);
++	} else if (wl_get_drv_status(cfg, DISCONNECTING, dev)) {
++		/* DHD prev status is DISCONNECTING */
++		err = wl_cfg80211_cleanup_mismatch_status(dev, cfg, FALSE);
++	} else if (!wl_get_drv_status(cfg, CONNECTED, dev)) {
++		/* DHD previous status is not connected and FW connected */
++		if (wldev_ioctl_get(dev, WLC_GET_BSSID, &bssid, ETHER_ADDR_LEN) == 0) {
++			/* set nested connect bit to identify the context */
++			wl_set_drv_status(cfg, NESTED_CONNECT, dev);
++			err = wl_cfg80211_cleanup_mismatch_status(dev, cfg, TRUE);
++		}
++	}
++	wl_cfg80211_check_in4way(cfg, dev, WAIT_DISCONNECTED,
++		WL_EXT_STATUS_CONNECTING, NULL);
++
++	/* 'connect' request received */
++	wl_set_drv_status(cfg, CONNECTING, dev);
++	/* clear nested connect bit on proceeding for connection */
++	wl_clr_drv_status(cfg, NESTED_CONNECT, dev);
++
++	/* Clean BSSID */
++	bzero(&bssid, sizeof(bssid));
++	if (!wl_get_drv_status(cfg, DISCONNECTING, dev))
++		wl_update_prof(cfg, dev, NULL, (void *)&bssid, WL_PROF_BSSID);
++
++	if (p2p_is_on(cfg) && (dev != bcmcfg_to_prmry_ndev(cfg))) {
++		/* we only allow to connect using virtual interface in case of P2P */
++			if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++				WL_ERR(("Find p2p index from wdev(%p) failed\n",
++					dev->ieee80211_ptr));
++				err = BCME_ERROR;
++				goto exit;
++			}
++			wl_cfg80211_set_mgmt_vndr_ies(cfg, ndev_to_cfgdev(dev), bssidx,
++				VNDR_IE_ASSOCREQ_FLAG, sme->ie, sme->ie_len);
++	} else if (dev == bcmcfg_to_prmry_ndev(cfg)) {
++		if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++			WL_ERR(("Find wlan index from wdev(%p) failed\n", dev->ieee80211_ptr));
++			err = BCME_ERROR;
++			goto exit;
++		}
++
++		/* find the RSN_IE */
++		if ((wpa2_ie = bcm_parse_tlvs((u8 *)sme->ie, sme->ie_len,
++			DOT11_MNG_RSN_ID)) != NULL) {
++			WL_DBG((" WPA2 IE is found\n"));
++		}
++		/* find the WPA_IE */
++		if ((wpa_ie = wl_cfgp2p_find_wpaie((u8 *)sme->ie,
++			sme->ie_len)) != NULL) {
++			WL_DBG((" WPA IE is found\n"));
++		}
++		if (wpa_ie != NULL || wpa2_ie != NULL) {
++			wpaie = (wpa_ie != NULL) ? (u8 *)wpa_ie : (u8 *)wpa2_ie;
++			wpaie_len = (wpa_ie != NULL) ? wpa_ie->length : wpa2_ie->len;
++			wpaie_len += WPA_RSN_IE_TAG_FIXED_LEN;
++			err = wldev_iovar_setbuf(dev, "wpaie", wpaie, wpaie_len,
++				cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++			if (unlikely(err)) {
++				WL_ERR(("wpaie set error (%d)\n", err));
++				goto exit;
++			}
++		} else {
++			err = wldev_iovar_setbuf(dev, "wpaie", NULL, 0,
++				cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++			if (unlikely(err)) {
++				WL_ERR(("wpaie set error (%d)\n", err));
++				goto exit;
++			}
++		}
++		err = wl_cfg80211_set_mgmt_vndr_ies(cfg, ndev_to_cfgdev(dev), bssidx,
++			VNDR_IE_ASSOCREQ_FLAG, (const u8 *)sme->ie, sme->ie_len);
++		if (unlikely(err)) {
++			goto exit;
++		}
++	}
++
++	if (chan) {
++		cfg->channel = ieee80211_frequency_to_channel(chan->center_freq);
++		chan_cnt = 1;
++		WL_DBG(("channel (%d), center_req (%d), %d channels\n", cfg->channel,
++			chan->center_freq, chan_cnt));
++	} else {
++		WL_DBG(("No channel info from user space\n"));
++		cfg->channel = 0;
++	}
++#ifdef BCMWAPI_WPI
++	WL_DBG(("1. enable wapi auth\n"));
++	if (sme->crypto.wpa_versions & NL80211_WAPI_VERSION_1) {
++		WL_DBG(("2. set wapi ie  \n"));
++		err = wl_set_set_wapi_ie(dev, sme);
++		if (unlikely(err))
++			goto exit;
++	} else
++		WL_DBG(("2. Not wapi ie  \n"));
++#endif
++	WL_DBG(("3. set wpa version \n"));
++
++	err = wl_set_wpa_version(dev, sme);
++	if (unlikely(err)) {
++		WL_ERR(("Invalid wpa_version\n"));
++		goto exit;
++	}
++#ifdef BCMWAPI_WPI
++	if (sme->crypto.wpa_versions & NL80211_WAPI_VERSION_1)
++		WL_DBG(("4. WAPI Dont Set wl_set_auth_type\n"));
++	else {
++		WL_DBG(("4. wl_set_auth_type\n"));
++#endif
++		err = wl_set_auth_type(dev, sme);
++		if (unlikely(err)) {
++			WL_ERR(("Invalid auth type\n"));
++			goto exit;
++		}
++#ifdef BCMWAPI_WPI
++	}
++#endif
++
++	err = wl_set_set_cipher(dev, sme);
++	if (unlikely(err)) {
++		WL_ERR(("Invalid ciper\n"));
++		goto exit;
++	}
++
++	err = wl_set_key_mgmt(dev, sme);
++	if (unlikely(err)) {
++		WL_ERR(("Invalid key mgmt\n"));
++		goto exit;
++	}
++
++	err = wl_set_set_sharedkey(dev, sme);
++	if (unlikely(err)) {
++		WL_ERR(("Invalid shared key\n"));
++		goto exit;
++	}
++
++	/*
++	 *  Join with specific BSSID and cached SSID
++	 *  If SSID is zero join based on BSSID only
++	 */
++	join_params_size = WL_EXTJOIN_PARAMS_FIXED_SIZE +
++		chan_cnt * sizeof(chanspec_t);
++	ext_join_params =  (wl_extjoin_params_t*)kzalloc(join_params_size, GFP_KERNEL);
++	if (ext_join_params == NULL) {
++		err = -ENOMEM;
++		wl_clr_drv_status(cfg, CONNECTING, dev);
++		goto exit;
++	}
++	ext_join_params->ssid.SSID_len = min(sizeof(ext_join_params->ssid.SSID), sme->ssid_len);
++	memcpy(&ext_join_params->ssid.SSID, sme->ssid, ext_join_params->ssid.SSID_len);
++	wl_update_prof(cfg, dev, NULL, &ext_join_params->ssid, WL_PROF_SSID);
++	ext_join_params->ssid.SSID_len = htod32(ext_join_params->ssid.SSID_len);
++	/* increate dwell time to receive probe response or detect Beacon
++	* from target AP at a noisy air only during connect command
++	*/
++	ext_join_params->scan.active_time = chan_cnt ? WL_SCAN_JOIN_ACTIVE_DWELL_TIME_MS : -1;
++	ext_join_params->scan.passive_time = chan_cnt ? WL_SCAN_JOIN_PASSIVE_DWELL_TIME_MS : -1;
++	/* Set up join scan parameters */
++	ext_join_params->scan.scan_type = -1;
++	ext_join_params->scan.nprobes = chan_cnt ?
++		(ext_join_params->scan.active_time/WL_SCAN_JOIN_PROBE_INTERVAL_MS) : -1;
++	ext_join_params->scan.home_time = -1;
++
++	if (sme->bssid)
++		memcpy(&ext_join_params->assoc.bssid, sme->bssid, ETH_ALEN);
++	else
++		memcpy(&ext_join_params->assoc.bssid, &ether_bcast, ETH_ALEN);
++	ext_join_params->assoc.chanspec_num = chan_cnt;
++	if (chan_cnt) {
++		if (cfg->channel) {
++			/*
++			 * Use the channel provided by userspace
++			 */
++			u16 channel, band, bw, ctl_sb;
++			chanspec_t chspec;
++			channel = cfg->channel;
++			band = (channel <= CH_MAX_2G_CHANNEL) ? WL_CHANSPEC_BAND_2G
++				: WL_CHANSPEC_BAND_5G;
++
++			/* Get min_bw set for the interface */
++			bw = wl_cfg80211_ulb_get_min_bw_chspec(cfg, dev->ieee80211_ptr, bssidx);
++			if (bw == INVCHANSPEC) {
++				WL_ERR(("Invalid chanspec \n"));
++				kfree(ext_join_params);
++				err = BCME_ERROR;
++				goto exit;
++			}
++
++			ctl_sb = WL_CHANSPEC_CTL_SB_NONE;
++			chspec = (channel | band | bw | ctl_sb);
++			ext_join_params->assoc.chanspec_list[0]  &= WL_CHANSPEC_CHAN_MASK;
++			ext_join_params->assoc.chanspec_list[0] |= chspec;
++			ext_join_params->assoc.chanspec_list[0] =
++				wl_chspec_host_to_driver(ext_join_params->assoc.chanspec_list[0]);
++		}
++	}
++	ext_join_params->assoc.chanspec_num = htod32(ext_join_params->assoc.chanspec_num);
++	if (ext_join_params->ssid.SSID_len < IEEE80211_MAX_SSID_LEN) {
++		WL_INFORM(("ssid \"%s\", len (%d)\n", ext_join_params->ssid.SSID,
++			ext_join_params->ssid.SSID_len));
++	}
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		kfree(ext_join_params);
++		err = BCME_ERROR;
++		goto exit;
++	}
++#if defined(CUSTOMER_HW2)
++	DHD_DISABLE_RUNTIME_PM((dhd_pub_t *)cfg->pub);
++#endif /* BCMDONGLEHOST && CUSTOMER_HW2 */
++#ifdef WL_EXT_IAPSTA
++	wl_ext_iapsta_update_channel(dhdp, dev, cfg->channel);
++#endif
++
++	wl_ext_get_sec(dev, 0, sec, sizeof(sec));
++	if (cfg->rcc_enabled) {
++		WL_MSG(dev->name, "Connecting with " MACDBG " ssid \"%s\", len (%d), "
++			"sec=%s, with rcc channels\n\n",
++			MAC2STRDBG((u8*)(&ext_join_params->assoc.bssid)),
++			ext_join_params->ssid.SSID, ext_join_params->ssid.SSID_len, sec);
++	} else {
++		WL_MSG(dev->name, "Connecting with " MACDBG " ssid \"%s\", len (%d), "
++			"sec=%s, channel=%d\n\n",
++			MAC2STRDBG((u8*)(&ext_join_params->assoc.bssid)),
++			ext_join_params->ssid.SSID, ext_join_params->ssid.SSID_len, sec,
++			cfg->channel);
++	}
++	err = wldev_iovar_setbuf_bsscfg(dev, "join", ext_join_params, join_params_size,
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++
++	kfree(ext_join_params);
++	if (err) {
++		wl_clr_drv_status(cfg, CONNECTING, dev);
++		if (err == BCME_UNSUPPORTED) {
++			WL_DBG(("join iovar is not supported\n"));
++			goto set_ssid;
++		} else {
++			WL_ERR(("error (%d)\n", err));
++			goto exit;
++		}
++	} else
++		goto exit;
++
++set_ssid:
++	memset(&join_params, 0, sizeof(join_params));
++	join_params_size = sizeof(join_params.ssid);
++
++	join_params.ssid.SSID_len = min(sizeof(join_params.ssid.SSID), sme->ssid_len);
++	memcpy(&join_params.ssid.SSID, sme->ssid, join_params.ssid.SSID_len);
++	join_params.ssid.SSID_len = htod32(join_params.ssid.SSID_len);
++	wl_update_prof(cfg, dev, NULL, &join_params.ssid, WL_PROF_SSID);
++	if (sme->bssid)
++		memcpy(&join_params.params.bssid, sme->bssid, ETH_ALEN);
++	else
++		memcpy(&join_params.params.bssid, &ether_bcast, ETH_ALEN);
++
++	if (wl_ch_to_chanspec(dev, cfg->channel, &join_params, &join_params_size) < 0) {
++		WL_ERR(("Invalid chanspec\n"));
++		return -EINVAL;
++	}
++
++	WL_DBG(("join_param_size %zu\n", join_params_size));
++
++	if (join_params.ssid.SSID_len < IEEE80211_MAX_SSID_LEN) {
++		WL_MSG(dev->name, "ssid \"%s\", len (%d)\n", join_params.ssid.SSID,
++			join_params.ssid.SSID_len);
++	}
++	err = wldev_ioctl_set(dev, WLC_SET_SSID, &join_params, join_params_size);
++exit:
++	if (err) {
++		WL_ERR(("error (%d)\n", err));
++		wl_clr_drv_status(cfg, CONNECTING, dev);
++	}
++	if (!err)
++		wl_cfg80211_check_in4way(cfg, dev, NO_SCAN_IN4WAY|NO_BTC_IN4WAY,
++			WL_EXT_STATUS_CONNECTING, NULL);
++
++#ifdef WLTDLS
++	/* disable TDLS if number of connected interfaces is >= 1 */
++	wl_cfg80211_tdls_config(cfg, TDLS_STATE_CONNECT, false);
++#endif /* WLTDLS */
++
++#ifdef DBG_PKT_MON
++	if ((dev == bcmcfg_to_prmry_ndev(cfg)) && !err) {
++		DHD_DBG_PKT_MON_START(dhdp);
++	}
++#endif /* DBG_PKT_MON */
++	return err;
++}
++
++#define WAIT_FOR_DISCONNECT_MAX 10
++static void wl_cfg80211_wait_for_disconnection(struct bcm_cfg80211 *cfg, struct net_device *dev)
++{
++	uint8 wait_cnt;
++
++	wait_cnt = WAIT_FOR_DISCONNECT_MAX;
++	while (wl_get_drv_status(cfg, DISCONNECTING, dev) && wait_cnt) {
++		WL_DBG(("Waiting for disconnection, wait_cnt: %d\n", wait_cnt));
++		wait_cnt--;
++		OSL_SLEEP(50);
++	}
++
++	return;
++}
++
++static s32
++wl_cfg80211_disconnect(struct wiphy *wiphy, struct net_device *dev,
++	u16 reason_code)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	scb_val_t scbval;
++	bool act = false;
++	s32 err = 0;
++	u8 *curbssid;
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++
++	WL_MSG(dev->name, "Reason %d\n", reason_code);
++	RETURN_EIO_IF_NOT_UP(cfg);
++	act = *(bool *) wl_read_prof(cfg, dev, WL_PROF_ACT);
++	curbssid = wl_read_prof(cfg, dev, WL_PROF_BSSID);
++
++	BCM_REFERENCE(dhdp);
++
++#ifdef ESCAN_RESULT_PATCH
++	if (wl_get_drv_status(cfg, CONNECTING, dev) && curbssid &&
++		(memcmp(curbssid, connect_req_bssid, ETHER_ADDR_LEN) == 0)) {
++		WL_ERR(("Disconnecting from connecting device: " MACDBG "\n",
++			MAC2STRDBG(curbssid)));
++		act = true;
++	}
++#endif /* ESCAN_RESULT_PATCH */
++
++	if (act) {
++#ifdef DBG_PKT_MON
++		if (dev == bcmcfg_to_prmry_ndev(cfg)) {
++			DHD_DBG_PKT_MON_STOP(dhdp);
++		}
++#endif /* DBG_PKT_MON */
++		/*
++		* Cancel ongoing scan to sync up with sme state machine of cfg80211.
++		*/
++#if !defined(ESCAN_RESULT_PATCH)
++		/* Let scan aborted by F/W */
++		if (cfg->scan_request) {
++			WL_TRACE_HW4(("Aborting the scan! \n"));
++			wl_notify_escan_complete(cfg, dev, true, true);
++		}
++#endif /* ESCAN_RESULT_PATCH */
++		if (wl_get_drv_status(cfg, CONNECTING, dev) ||
++			wl_get_drv_status(cfg, CONNECTED, dev)) {
++				wl_set_drv_status(cfg, DISCONNECTING, dev);
++				scbval.val = reason_code;
++				memcpy(&scbval.ea, curbssid, ETHER_ADDR_LEN);
++				scbval.val = htod32(scbval.val);
++				err = wldev_ioctl_set(dev, WLC_DISASSOC, &scbval,
++						sizeof(scb_val_t));
++				if (unlikely(err)) {
++					wl_clr_drv_status(cfg, DISCONNECTING, dev);
++					WL_ERR(("error (%d)\n", err));
++					return err;
++				}
++				wl_cfg80211_check_in4way(cfg, dev, NO_SCAN_IN4WAY|NO_BTC_IN4WAY|WAIT_DISCONNECTED,
++					WL_EXT_STATUS_DISCONNECTING, NULL);
++				wl_cfg80211_wait_for_disconnection(cfg, dev);
++		}
++	}
++#ifdef CUSTOM_SET_CPUCORE
++	/* set default cpucore */
++	if (dev == bcmcfg_to_prmry_ndev(cfg)) {
++		dhdp->chan_isvht80 &= ~DHD_FLAG_STA_MODE;
++		if (!(dhdp->chan_isvht80))
++			dhd_set_cpucore(dhdp, FALSE);
++	}
++#endif /* CUSTOM_SET_CPUCORE */
++
++	return err;
++}
++
++static s32
++#if defined(WL_CFG80211_P2P_DEV_IF)
++wl_cfg80211_set_tx_power(struct wiphy *wiphy, struct wireless_dev *wdev,
++	enum nl80211_tx_power_setting type, s32 mbm)
++#else
++wl_cfg80211_set_tx_power(struct wiphy *wiphy,
++	enum nl80211_tx_power_setting type, s32 dbm)
++#endif /* WL_CFG80211_P2P_DEV_IF */
++{
++
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	s32 err = 0;
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	s32 dbm = MBM_TO_DBM(mbm);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) || \
++	defined(WL_COMPAT_WIRELESS) || defined(WL_SUPPORT_BACKPORTED_KPATCHES)
++	dbm = MBM_TO_DBM(dbm);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	switch (type) {
++	case NL80211_TX_POWER_AUTOMATIC:
++		break;
++	case NL80211_TX_POWER_LIMITED:
++		if (dbm < 0) {
++			WL_ERR(("TX_POWER_LIMITTED - dbm is negative\n"));
++			return -EINVAL;
++		}
++		break;
++	case NL80211_TX_POWER_FIXED:
++		if (dbm < 0) {
++			WL_ERR(("TX_POWER_FIXED - dbm is negative..\n"));
++			return -EINVAL;
++		}
++		break;
++	}
++
++	err = wl_set_tx_power(ndev, type, dbm);
++	if (unlikely(err)) {
++		WL_ERR(("error (%d)\n", err));
++		return err;
++	}
++
++	cfg->conf->tx_power = dbm;
++
++	return err;
++}
++
++static s32
++#if defined(WL_CFG80211_P2P_DEV_IF)
++wl_cfg80211_get_tx_power(struct wiphy *wiphy,
++	struct wireless_dev *wdev, s32 *dbm)
++#else
++wl_cfg80211_get_tx_power(struct wiphy *wiphy, s32 *dbm)
++#endif /* WL_CFG80211_P2P_DEV_IF */
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	s32 err = 0;
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	err = wl_get_tx_power(ndev, dbm);
++	if (unlikely(err))
++		WL_ERR(("error (%d)\n", err));
++
++	return err;
++}
++
++static s32
++wl_cfg80211_config_default_key(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, bool unicast, bool multicast)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	u32 index;
++	s32 wsec;
++	s32 err = 0;
++	s32 bssidx;
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from dev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	WL_DBG(("key index (%d)\n", key_idx));
++	RETURN_EIO_IF_NOT_UP(cfg);
++	err = wldev_iovar_getint_bsscfg(dev, "wsec", &wsec, bssidx);
++	if (unlikely(err)) {
++		WL_ERR(("WLC_GET_WSEC error (%d)\n", err));
++		return err;
++	}
++	if (wsec == WEP_ENABLED) {
++		/* Just select a new current key */
++		index = (u32) key_idx;
++		index = htod32(index);
++		err = wldev_ioctl_set(dev, WLC_SET_KEY_PRIMARY, &index,
++			sizeof(index));
++		if (unlikely(err)) {
++			WL_ERR(("error (%d)\n", err));
++		}
++	}
++	return err;
++}
++
++static s32
++wl_add_keyext(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, const u8 *mac_addr, struct key_params *params)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct wl_wsec_key key;
++	s32 err = 0;
++	s32 bssidx;
++	s32 mode = wl_get_mode_by_netdev(cfg, dev);
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++	memset(&key, 0, sizeof(key));
++	key.index = (u32) key_idx;
++
++	if (!ETHER_ISMULTI(mac_addr))
++		memcpy((char *)&key.ea, (const void *)mac_addr, ETHER_ADDR_LEN);
++	key.len = (u32) params->key_len;
++
++	/* check for key index change */
++	if (key.len == 0) {
++		/* key delete */
++		swap_key_from_BE(&key);
++		err = wldev_iovar_setbuf_bsscfg(dev, "wsec_key", &key, sizeof(key),
++			cfg->ioctl_buf, WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++		if (unlikely(err)) {
++			WL_ERR(("key delete error (%d)\n", err));
++			return err;
++		}
++	} else {
++		if (key.len > sizeof(key.data)) {
++			WL_ERR(("Invalid key length (%d)\n", key.len));
++			return -EINVAL;
++		}
++		WL_DBG(("Setting the key index %d\n", key.index));
++		memcpy(key.data, params->key, key.len);
++
++		if ((mode == WL_MODE_BSS) &&
++			(params->cipher == WLAN_CIPHER_SUITE_TKIP)) {
++			u8 keybuf[8];
++			memcpy(keybuf, &key.data[24], sizeof(keybuf));
++			memcpy(&key.data[24], &key.data[16], sizeof(keybuf));
++			memcpy(&key.data[16], keybuf, sizeof(keybuf));
++		}
++
++		/* if IW_ENCODE_EXT_RX_SEQ_VALID set */
++		if (params->seq && params->seq_len == 6) {
++			/* rx iv */
++			u8 *ivptr;
++			ivptr = (u8 *) params->seq;
++			key.rxiv.hi = (ivptr[5] << 24) | (ivptr[4] << 16) |
++				(ivptr[3] << 8) | ivptr[2];
++			key.rxiv.lo = (ivptr[1] << 8) | ivptr[0];
++			key.iv_initialized = true;
++		}
++
++		switch (params->cipher) {
++		case WLAN_CIPHER_SUITE_WEP40:
++			key.algo = CRYPTO_ALGO_WEP1;
++			WL_DBG(("WLAN_CIPHER_SUITE_WEP40\n"));
++			break;
++		case WLAN_CIPHER_SUITE_WEP104:
++			key.algo = CRYPTO_ALGO_WEP128;
++			WL_DBG(("WLAN_CIPHER_SUITE_WEP104\n"));
++			break;
++		case WLAN_CIPHER_SUITE_TKIP:
++			key.algo = CRYPTO_ALGO_TKIP;
++			WL_DBG(("WLAN_CIPHER_SUITE_TKIP\n"));
++			break;
++		case WLAN_CIPHER_SUITE_AES_CMAC:
++			key.algo = CRYPTO_ALGO_AES_CCM;
++			WL_DBG(("WLAN_CIPHER_SUITE_AES_CMAC\n"));
++			break;
++		case WLAN_CIPHER_SUITE_CCMP:
++			key.algo = CRYPTO_ALGO_AES_CCM;
++			WL_DBG(("WLAN_CIPHER_SUITE_CCMP\n"));
++			break;
++#ifdef BCMWAPI_WPI
++		case WLAN_CIPHER_SUITE_SMS4:
++			key.algo = CRYPTO_ALGO_SMS4;
++			WL_DBG(("WLAN_CIPHER_SUITE_SMS4\n"));
++			break;
++#endif
++		default:
++			WL_ERR(("Invalid cipher (0x%x)\n", params->cipher));
++			return -EINVAL;
++		}
++		swap_key_from_BE(&key);
++		/* need to guarantee EAPOL 4/4 send out before set key */
++		dhd_wait_pend8021x(dev);
++		err = wldev_iovar_setbuf_bsscfg(dev, "wsec_key", &key, sizeof(key),
++			cfg->ioctl_buf, WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++		if (unlikely(err)) {
++			WL_ERR(("WLC_SET_KEY error (%d)\n", err));
++			return err;
++		}
++	}
++	return err;
++}
++
++int
++wl_cfg80211_enable_roam_offload(struct net_device *dev, int enable)
++{
++	int err;
++	wl_eventmsg_buf_t ev_buf;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++
++	if (dev != bcmcfg_to_prmry_ndev(cfg)) {
++		/* roam offload is only for the primary device */
++		return -1;
++	}
++	err = wldev_iovar_setint(dev, "roam_offload", enable);
++	if (err)
++		return err;
++
++	bzero(&ev_buf, sizeof(wl_eventmsg_buf_t));
++	wl_cfg80211_add_to_eventbuffer(&ev_buf, WLC_E_PSK_SUP, !enable);
++	wl_cfg80211_add_to_eventbuffer(&ev_buf, WLC_E_ASSOC_REQ_IE, !enable);
++	wl_cfg80211_add_to_eventbuffer(&ev_buf, WLC_E_ASSOC_RESP_IE, !enable);
++	wl_cfg80211_add_to_eventbuffer(&ev_buf, WLC_E_REASSOC, !enable);
++	wl_cfg80211_add_to_eventbuffer(&ev_buf, WLC_E_JOIN, !enable);
++	wl_cfg80211_add_to_eventbuffer(&ev_buf, WLC_E_ROAM, !enable);
++	err = wl_cfg80211_apply_eventbuffer(dev, cfg, &ev_buf);
++	if (!err) {
++		cfg->roam_offload = enable;
++	}
++	return err;
++}
++
++#if defined(WL_VIRTUAL_APSTA)
++int
++wl_cfg80211_interface_create(struct net_device *dev, char *name)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	bcm_struct_cfgdev *new_cfgdev;
++	char ifname[IFNAMSIZ];
++	char iftype[IFNAMSIZ];
++	enum nl80211_iftype iface_type = NL80211_IFTYPE_STATION;
++
++	sscanf(name, "%s %s", ifname, iftype);
++
++	if (strnicmp(iftype, "AP", strlen("AP")) == 0) {
++		iface_type = NL80211_IFTYPE_AP;
++	}
++
++	new_cfgdev = wl_cfg80211_create_iface(cfg->wdev->wiphy,
++		iface_type, NULL, ifname);
++	if (!new_cfgdev) {
++		return BCME_ERROR;
++	}
++	else {
++		WL_DBG(("Iface %s created successfuly\n", name));
++		return BCME_OK;
++	}
++}
++
++int
++wl_cfg80211_interface_delete(struct net_device *dev, char *name)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	struct net_info *iter, *next;
++	int err = BCME_ERROR;
++
++	if (name == NULL) {
++		return BCME_ERROR;
++	}
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	for_each_ndev(cfg, iter, next) {
++		if (iter->ndev) {
++			if (strcmp(iter->ndev->name, name) == 0) {
++				err =  wl_cfg80211_del_iface(cfg->wdev->wiphy,
++					ndev_to_cfgdev(iter->ndev));
++				break;
++			}
++		}
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	if (!err) {
++		WL_DBG(("Iface %s deleted successfuly", name));
++	}
++	return err;
++}
++
++#if defined(PKT_FILTER_SUPPORT) && defined(APSTA_BLOCK_ARP_DURING_DHCP)
++void
++wl_cfg80211_block_arp(struct net_device *dev, int enable)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++
++	if (!dhd_pkt_filter_enable) {
++		WL_INFORM(("Packet filter isn't enabled\n"));
++		return;
++	}
++
++	/* Block/Unblock ARP frames only if STA is connected to
++	 * the upstream AP in case of STA+SoftAP Concurrenct mode
++	 */
++	if (!wl_get_drv_status(cfg, CONNECTED, dev)) {
++		WL_INFORM(("STA doesn't connected to upstream AP\n"));
++		return;
++	}
++
++	if (enable) {
++		WL_DBG(("Enable ARP Filter\n"));
++		/* Add ARP filter */
++		dhd_packet_filter_add_remove(dhdp, TRUE, DHD_BROADCAST_ARP_FILTER_NUM);
++
++		/* Enable ARP packet filter - blacklist */
++		dhd_master_mode = FALSE;
++		dhd_pktfilter_offload_enable(dhdp, dhdp->pktfilter[DHD_BROADCAST_ARP_FILTER_NUM],
++			TRUE, dhd_master_mode);
++	} else {
++		WL_DBG(("Disable ARP Filter\n"));
++		/* Disable ARP packet filter */
++		dhd_master_mode = TRUE;
++		dhd_pktfilter_offload_enable(dhdp, dhdp->pktfilter[DHD_BROADCAST_ARP_FILTER_NUM],
++			FALSE, dhd_master_mode);
++
++		/* Delete ARP filter */
++		dhd_packet_filter_add_remove(dhdp, FALSE, DHD_BROADCAST_ARP_FILTER_NUM);
++	}
++}
++#endif /* PKT_FILTER_SUPPORT && APSTA_BLOCK_ARP_DURING_DHCP */
++#endif /* defined (WL_VIRTUAL_APSTA) */
++
++static s32
++wl_cfg80211_add_key(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, bool pairwise, const u8 *mac_addr,
++	struct key_params *params)
++{
++	struct wl_wsec_key key;
++	s32 val = 0;
++	s32 wsec = 0;
++	s32 err = 0;
++	u8 keybuf[8];
++	s32 bssidx = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 mode = wl_get_mode_by_netdev(cfg, dev);
++
++	WL_DBG(("key index (%d)\n", key_idx));
++	RETURN_EIO_IF_NOT_UP(cfg);
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from dev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	if (mac_addr &&
++		((params->cipher != WLAN_CIPHER_SUITE_WEP40) &&
++		(params->cipher != WLAN_CIPHER_SUITE_WEP104))) {
++			wl_add_keyext(wiphy, dev, key_idx, mac_addr, params);
++			goto exit;
++	}
++	memset(&key, 0, sizeof(key));
++	/* Clear any buffered wep key */
++	memset(&cfg->wep_key, 0, sizeof(struct wl_wsec_key));
++
++	key.len = (u32) params->key_len;
++	key.index = (u32) key_idx;
++
++	if (unlikely(key.len > sizeof(key.data))) {
++		WL_ERR(("Too long key length (%u)\n", key.len));
++		return -EINVAL;
++	}
++	memcpy(key.data, params->key, key.len);
++
++	key.flags = WL_PRIMARY_KEY;
++	switch (params->cipher) {
++	case WLAN_CIPHER_SUITE_WEP40:
++		key.algo = CRYPTO_ALGO_WEP1;
++		val = WEP_ENABLED;
++		WL_DBG(("WLAN_CIPHER_SUITE_WEP40\n"));
++		break;
++	case WLAN_CIPHER_SUITE_WEP104:
++		key.algo = CRYPTO_ALGO_WEP128;
++		val = WEP_ENABLED;
++		WL_DBG(("WLAN_CIPHER_SUITE_WEP104\n"));
++		break;
++	case WLAN_CIPHER_SUITE_TKIP:
++		key.algo = CRYPTO_ALGO_TKIP;
++		val = TKIP_ENABLED;
++		/* wpa_supplicant switches the third and fourth quarters of the TKIP key */
++		if (mode == WL_MODE_BSS) {
++			bcopy(&key.data[24], keybuf, sizeof(keybuf));
++			bcopy(&key.data[16], &key.data[24], sizeof(keybuf));
++			bcopy(keybuf, &key.data[16], sizeof(keybuf));
++		}
++		WL_DBG(("WLAN_CIPHER_SUITE_TKIP\n"));
++		break;
++	case WLAN_CIPHER_SUITE_AES_CMAC:
++		key.algo = CRYPTO_ALGO_AES_CCM;
++		val = AES_ENABLED;
++		WL_DBG(("WLAN_CIPHER_SUITE_AES_CMAC\n"));
++		break;
++	case WLAN_CIPHER_SUITE_CCMP:
++		key.algo = CRYPTO_ALGO_AES_CCM;
++		val = AES_ENABLED;
++		WL_DBG(("WLAN_CIPHER_SUITE_CCMP\n"));
++		break;
++#if defined(WLFBT) && defined(WLAN_CIPHER_SUITE_PMK)
++	case WLAN_CIPHER_SUITE_PMK: {
++		int j;
++		wsec_pmk_t pmk;
++		char keystring[WSEC_MAX_PSK_LEN + 1];
++		char* charptr = keystring;
++		uint len;
++		struct wl_security *sec;
++		sec = wl_read_prof(cfg, dev, WL_PROF_SEC);
++		if (sec->wpa_auth == WLAN_AKM_SUITE_8021X) {
++			err = wldev_iovar_setbuf(dev, "okc_info_pmk", (void *)params->key,
++				WSEC_MAX_PSK_LEN / 2, keystring, sizeof(keystring), NULL);
++			if (err) {
++				/* could fail in case that 'okc' is not supported */
++				WL_INFORM(("Setting 'okc_info_pmk' failed, err=%d\n", err));
++			}
++		}
++		/* copy the raw hex key to the appropriate format */
++		for (j = 0; j < (WSEC_MAX_PSK_LEN / 2); j++) {
++			charptr += snprintf(charptr, sizeof(keystring), "%02x", params->key[j]);
++		}
++		len = strlen(keystring);
++		pmk.key_len = htod16(len);
++		bcopy(keystring, pmk.key, len);
++		pmk.flags = htod16(WSEC_PASSPHRASE);
++		err = wldev_ioctl(dev, WLC_SET_WSEC_PMK, &pmk, sizeof(pmk), true);
++		if (err)
++			return err;
++	} break;
++#endif /* WLFBT && WLAN_CIPHER_SUITE_PMK */
++#ifdef BCMWAPI_WPI
++	case WLAN_CIPHER_SUITE_SMS4:
++		key.algo = CRYPTO_ALGO_SMS4;
++		WL_DBG(("WLAN_CIPHER_SUITE_SMS4\n"));
++		val = SMS4_ENABLED;
++		break;
++#endif /* BCMWAPI_WPI */
++	default:
++		WL_ERR(("Invalid cipher (0x%x)\n", params->cipher));
++		return -EINVAL;
++	}
++
++	/* Set the new key/index */
++	if ((mode == WL_MODE_IBSS) && (val & (TKIP_ENABLED | AES_ENABLED))) {
++		WL_ERR(("IBSS KEY setted\n"));
++		wldev_iovar_setint(dev, "wpa_auth", WPA_AUTH_NONE);
++	}
++	swap_key_from_BE(&key);
++	if ((params->cipher == WLAN_CIPHER_SUITE_WEP40) ||
++		(params->cipher == WLAN_CIPHER_SUITE_WEP104)) {
++		/*
++		 * For AP role, since we are doing a wl down before bringing up AP,
++		 * the plumbed keys will be lost. So for AP once we bring up AP, we
++		 * need to plumb keys again. So buffer the keys for future use. This
++		 * is more like a WAR. If firmware later has the capability to do
++		 * interface upgrade without doing a "wl down" and "wl apsta 0", then
++		 * this will not be required.
++		 */
++		WL_DBG(("Buffering WEP Keys \n"));
++		memcpy(&cfg->wep_key, &key, sizeof(struct wl_wsec_key));
++	}
++	err = wldev_iovar_setbuf_bsscfg(dev, "wsec_key", &key, sizeof(key), cfg->ioctl_buf,
++		WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++	if (unlikely(err)) {
++		WL_ERR(("WLC_SET_KEY error (%d)\n", err));
++		return err;
++	}
++
++exit:
++	err = wldev_iovar_getint_bsscfg(dev, "wsec", &wsec, bssidx);
++	if (unlikely(err)) {
++		WL_ERR(("get wsec error (%d)\n", err));
++		return err;
++	}
++
++	wsec |= val;
++	err = wldev_iovar_setint_bsscfg(dev, "wsec", wsec, bssidx);
++	if (unlikely(err)) {
++		WL_ERR(("set wsec error (%d)\n", err));
++		return err;
++	}
++	wl_cfg80211_check_in4way(cfg, dev, NO_SCAN_IN4WAY|NO_BTC_IN4WAY,
++		WL_EXT_STATUS_ADD_KEY, NULL);
++
++	return err;
++}
++
++static s32
++wl_cfg80211_del_key(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, bool pairwise, const u8 *mac_addr)
++{
++	struct wl_wsec_key key;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 err = 0;
++	s32 bssidx;
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++	WL_DBG(("Enter\n"));
++
++#ifndef MFP
++	if ((key_idx >= DOT11_MAX_DEFAULT_KEYS) && (key_idx < DOT11_MAX_DEFAULT_KEYS+2))
++		return -EINVAL;
++#endif
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	memset(&key, 0, sizeof(key));
++
++	key.flags = WL_PRIMARY_KEY;
++	key.algo = CRYPTO_ALGO_OFF;
++	key.index = (u32) key_idx;
++
++	WL_DBG(("key index (%d)\n", key_idx));
++	/* Set the new key/index */
++	swap_key_from_BE(&key);
++	err = wldev_iovar_setbuf_bsscfg(dev, "wsec_key", &key, sizeof(key), cfg->ioctl_buf,
++		WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++	if (unlikely(err)) {
++		if (err == -EINVAL) {
++			if (key.index >= DOT11_MAX_DEFAULT_KEYS) {
++				/* we ignore this key index in this case */
++				WL_DBG(("invalid key index (%d)\n", key_idx));
++			}
++		} else {
++			WL_ERR(("WLC_SET_KEY error (%d)\n", err));
++		}
++		return err;
++	}
++	return err;
++}
++
++static s32
++wl_cfg80211_get_key(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, bool pairwise, const u8 *mac_addr, void *cookie,
++	void (*callback) (void *cookie, struct key_params * params))
++{
++	struct key_params params;
++	struct wl_wsec_key key;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct wl_security *sec;
++	s32 wsec;
++	s32 err = 0;
++	s32 bssidx;
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++	WL_DBG(("key index (%d)\n", key_idx));
++	RETURN_EIO_IF_NOT_UP(cfg);
++	memset(&key, 0, sizeof(key));
++	key.index = key_idx;
++	swap_key_to_BE(&key);
++	memset(&params, 0, sizeof(params));
++	params.key_len = (u8) min_t(u8, DOT11_MAX_KEY_SIZE, key.len);
++	memcpy((void *)params.key, key.data, params.key_len);
++
++	err = wldev_iovar_getint_bsscfg(dev, "wsec", &wsec, bssidx);
++	if (unlikely(err)) {
++		WL_ERR(("WLC_GET_WSEC error (%d)\n", err));
++		return err;
++	}
++	switch (WSEC_ENABLED(wsec)) {
++		case WEP_ENABLED:
++			sec = wl_read_prof(cfg, dev, WL_PROF_SEC);
++			if (sec->cipher_pairwise & WLAN_CIPHER_SUITE_WEP40) {
++				params.cipher = WLAN_CIPHER_SUITE_WEP40;
++				WL_DBG(("WLAN_CIPHER_SUITE_WEP40\n"));
++			} else if (sec->cipher_pairwise & WLAN_CIPHER_SUITE_WEP104) {
++				params.cipher = WLAN_CIPHER_SUITE_WEP104;
++				WL_DBG(("WLAN_CIPHER_SUITE_WEP104\n"));
++			}
++			break;
++		case TKIP_ENABLED:
++			params.cipher = WLAN_CIPHER_SUITE_TKIP;
++			WL_DBG(("WLAN_CIPHER_SUITE_TKIP\n"));
++			break;
++		case AES_ENABLED:
++			params.cipher = WLAN_CIPHER_SUITE_AES_CMAC;
++			WL_DBG(("WLAN_CIPHER_SUITE_AES_CMAC\n"));
++			break;
++#if defined(SUPPORT_SOFTAP_WPAWPA2_MIXED)
++		/* to connect to mixed mode AP */
++		case (AES_ENABLED | TKIP_ENABLED): /* TKIP CCMP */
++			params.cipher = WLAN_CIPHER_SUITE_AES_CMAC;
++			WL_DBG(("WLAN_CIPHER_SUITE_TKIP\n"));
++			break;
++#endif
++#ifdef BCMWAPI_WPI
++		case SMS4_ENABLED:
++			params.cipher = WLAN_CIPHER_SUITE_SMS4;
++			WL_DBG(("WLAN_CIPHER_SUITE_SMS4\n"));
++			break;
++#endif
++		default:
++			WL_ERR(("Invalid algo (0x%x)\n", wsec));
++			return -EINVAL;
++	}
++
++	callback(cookie, &params);
++	return err;
++}
++
++static s32
++wl_cfg80211_config_default_mgmt_key(struct wiphy *wiphy,
++	struct net_device *dev, u8 key_idx)
++{
++#ifdef MFP
++	return 0;
++#else
++	WL_INFORM(("Not supported\n"));
++	return -EOPNOTSUPP;
++#endif /* MFP */
++}
++
++static s32
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++wl_cfg80211_get_station(struct wiphy *wiphy, struct net_device *dev,
++	const u8 *mac, struct station_info *sinfo)
++#else
++wl_cfg80211_get_station(struct wiphy *wiphy, struct net_device *dev,
++	u8 *mac, struct station_info *sinfo)
++#endif
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	scb_val_t scb_val;
++	s32 rssi;
++	s32 rate;
++	s32 err = 0;
++	sta_info_t *sta;
++	s8 eabuf[ETHER_ADDR_STR_LEN];
++	dhd_pub_t *dhd =  (dhd_pub_t *)(cfg->pub);
++	bool fw_assoc_state = FALSE;
++	u32 dhd_assoc_state = 0;
++	static int err_cnt = 0;
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	if (wl_get_mode_by_netdev(cfg, dev) == WL_MODE_AP) {
++		err = wldev_iovar_getbuf(dev, "sta_info", (struct ether_addr *)mac,
++			ETHER_ADDR_LEN, cfg->ioctl_buf, WLC_IOCTL_SMLEN, &cfg->ioctl_buf_sync);
++		if (err < 0) {
++			WL_ERR(("GET STA INFO failed, %d\n", err));
++			return err;
++		}
++		sinfo->filled = STA_INFO_BIT(INFO_INACTIVE_TIME);
++		sta = (sta_info_t *)cfg->ioctl_buf;
++		sta->len = dtoh16(sta->len);
++		sta->cap = dtoh16(sta->cap);
++		sta->flags = dtoh32(sta->flags);
++		sta->idle = dtoh32(sta->idle);
++		sta->in = dtoh32(sta->in);
++		sinfo->inactive_time = sta->idle * 1000;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++		if (sta->flags & WL_STA_ASSOC) {
++			sinfo->filled |= STA_INFO_BIT(INFO_CONNECTED_TIME);
++			sinfo->connected_time = sta->in;
++		}
++#endif
++		WL_INFORM(("STA %s, flags 0x%x, idle time %ds, connected time %ds\n",
++			bcm_ether_ntoa((const struct ether_addr *)mac, eabuf),
++			sta->flags, sta->idle, sta->in));
++	} else if (wl_get_mode_by_netdev(cfg, dev) == WL_MODE_BSS ||
++		wl_get_mode_by_netdev(cfg, dev) == WL_MODE_IBSS) {
++		get_pktcnt_t pktcnt;
++#ifdef DHD_SUPPORT_IF_CNTS
++		wl_if_stats_t *if_stats = NULL;
++#endif /* DHD_SUPPORT_IF_CNTS */
++		u8 *curmacp;
++
++		if (cfg->roam_offload) {
++			struct ether_addr bssid;
++			memset(&bssid, 0, sizeof(bssid));
++			err = wldev_ioctl_get(dev, WLC_GET_BSSID, &bssid, ETHER_ADDR_LEN);
++			if (err) {
++				WL_ERR(("Failed to get current BSSID\n"));
++			} else {
++				if (memcmp(mac, &bssid.octet, ETHER_ADDR_LEN) != 0) {
++					/* roaming is detected */
++					err = wl_cfg80211_delayed_roam(cfg, dev, &bssid);
++					if (err)
++						WL_ERR(("Failed to handle the delayed roam, "
++							"err=%d", err));
++					mac = (u8 *)bssid.octet;
++				}
++			}
++		}
++		dhd_assoc_state = wl_get_drv_status(cfg, CONNECTED, dev);
++		DHD_OS_WAKE_LOCK(dhd);
++		fw_assoc_state = dhd_is_associated(dhd, 0, &err);
++		DHD_OS_WAKE_UNLOCK(dhd);
++		if (!dhd_assoc_state || !fw_assoc_state) {
++			WL_ERR(("NOT assoc\n"));
++			if (err == -ENODATA)
++				return err;
++			if (!dhd_assoc_state) {
++				WL_TRACE_HW4(("drv state is not connected \n"));
++			}
++			if (!fw_assoc_state) {
++				WL_TRACE_HW4(("fw state is not associated \n"));
++			}
++			/* Disconnect due to fw is not associated for FW_ASSOC_WATCHDOG_TIME ms.
++			* 'err == 0' of dhd_is_associated() and '!fw_assoc_state'
++			* means that BSSID is null.
++			*/
++			if (dhd_assoc_state && !fw_assoc_state && !err) {
++				if (!fw_assoc_watchdog_started) {
++					fw_assoc_watchdog_ms = OSL_SYSUPTIME();
++					fw_assoc_watchdog_started = TRUE;
++					WL_TRACE_HW4(("fw_assoc_watchdog_started \n"));
++				} else {
++					if (OSL_SYSUPTIME() - fw_assoc_watchdog_ms >
++						FW_ASSOC_WATCHDOG_TIME) {
++						fw_assoc_watchdog_started = FALSE;
++						err = -ENODEV;
++						WL_TRACE_HW4(("fw is not associated for %d ms \n",
++							(OSL_SYSUPTIME() - fw_assoc_watchdog_ms)));
++						goto get_station_err;
++					}
++				}
++			}
++			err = -ENODEV;
++			return err;
++		}
++		fw_assoc_watchdog_started = FALSE;
++		curmacp = wl_read_prof(cfg, dev, WL_PROF_BSSID);
++		if (memcmp(mac, curmacp, ETHER_ADDR_LEN)) {
++			WL_ERR(("Wrong Mac address: "MACDBG" != "MACDBG"\n",
++				MAC2STRDBG(mac), MAC2STRDBG(curmacp)));
++		}
++
++		/* Report the current tx rate */
++		rate = 0;
++		err = wldev_ioctl_get(dev, WLC_GET_RATE, &rate, sizeof(rate));
++		if (err) {
++			WL_ERR(("Could not get rate (%d)\n", err));
++		} else {
++#if defined(USE_DYNAMIC_MAXPKT_RXGLOM)
++			int rxpktglom;
++#endif
++			rate = dtoh32(rate);
++			sinfo->filled |= STA_INFO_BIT(INFO_TX_BITRATE);
++			sinfo->txrate.legacy = rate * 5;
++			WL_DBG(("Rate %d Mbps\n", (rate / 2)));
++#if defined(USE_DYNAMIC_MAXPKT_RXGLOM)
++			rxpktglom = ((rate/2) > 150) ? 20 : 10;
++
++			if (maxrxpktglom != rxpktglom) {
++				maxrxpktglom = rxpktglom;
++				WL_DBG(("Rate %d Mbps, update bus:maxtxpktglom=%d\n", (rate/2),
++					maxrxpktglom));
++				err = wldev_iovar_setbuf(dev, "bus:maxtxpktglom",
++					(char*)&maxrxpktglom, 4, cfg->ioctl_buf,
++					WLC_IOCTL_MAXLEN, NULL);
++				if (err < 0) {
++					WL_ERR(("set bus:maxtxpktglom failed, %d\n", err));
++				}
++			}
++#endif
++		}
++
++		memset(&scb_val, 0, sizeof(scb_val));
++		scb_val.val = 0;
++		err = wldev_ioctl_get(dev, WLC_GET_RSSI, &scb_val,
++			sizeof(scb_val_t));
++		if (err) {
++			WL_ERR(("Could not get rssi (%d)\n", err));
++			goto get_station_err;
++		}
++		rssi = dtoh32(scb_val.val);
++#if defined(RSSIAVG)
++		err = wl_update_connected_rssi_cache(dev, &cfg->g_connected_rssi_cache_ctrl, &rssi);
++		if (err) {
++			WL_ERR(("Could not get rssi (%d)\n", err));
++			goto get_station_err;
++		}
++		wl_delete_dirty_rssi_cache(&cfg->g_connected_rssi_cache_ctrl);
++		wl_reset_rssi_cache(&cfg->g_connected_rssi_cache_ctrl);
++#endif
++#if defined(RSSIOFFSET)
++		rssi = wl_update_rssi_offset(dev, rssi);
++#endif
++#if !defined(RSSIAVG) && !defined(RSSIOFFSET)
++		// terence 20150419: limit the max. rssi to -2 or the bss will be filtered out in android OS
++		rssi = MIN(rssi, RSSI_MAXVAL);
++#endif
++		sinfo->filled |= STA_INFO_BIT(INFO_SIGNAL);
++		sinfo->signal = rssi;
++		WL_DBG(("RSSI %d dBm\n", rssi));
++
++#ifdef DHD_SUPPORT_IF_CNTS
++		if ((if_stats = kmalloc(sizeof(*if_stats), GFP_KERNEL)) == NULL) {
++			WL_ERR(("%s(%d): kmalloc failed\n", __FUNCTION__, __LINE__));
++			goto error;
++		}
++		memset(if_stats, 0, sizeof(*if_stats));
++
++		err = wldev_iovar_getbuf(dev, "if_counters", NULL, 0,
++			(char *)if_stats, sizeof(*if_stats), NULL);
++		if (!err) {
++			sinfo->rx_packets = (uint32)dtoh64(if_stats->rxframe);
++			sinfo->rx_dropped_misc = 0;
++			sinfo->tx_packets = (uint32)dtoh64(if_stats->txfrmsnt);
++			sinfo->tx_failed = (uint32)dtoh64(if_stats->txnobuf) +
++				(uint32)dtoh64(if_stats->txrunt) +
++				(uint32)dtoh64(if_stats->txfail);
++		} else {
++//			WL_ERR(("%s: if_counters not supported ret=%d\n",
++//				__FUNCTION__, err));
++#endif /* DHD_SUPPORT_IF_CNTS */
++
++			err = wldev_ioctl_get(dev, WLC_GET_PKTCNTS, &pktcnt,
++				sizeof(pktcnt));
++			if (err) {
++				WL_ERR(("Could not get WLC_GET_PKTCNTS (%d)\n", err));
++				goto get_station_err;
++			}
++			sinfo->rx_packets = pktcnt.rx_good_pkt;
++			sinfo->rx_dropped_misc = pktcnt.rx_bad_pkt;
++			sinfo->tx_packets = pktcnt.tx_good_pkt;
++			sinfo->tx_failed  = pktcnt.tx_bad_pkt;
++#ifdef DHD_SUPPORT_IF_CNTS
++		}
++#endif /* DHD_SUPPORT_IF_CNTS */
++
++		sinfo->filled |= (STA_INFO_BIT(INFO_RX_PACKETS) |
++			STA_INFO_BIT(INFO_RX_DROP_MISC) |
++			STA_INFO_BIT(INFO_TX_PACKETS) |
++			STA_INFO_BIT(INFO_TX_FAILED));
++
++get_station_err:
++		if (err)
++			err_cnt++;
++		else
++			err_cnt = 0;
++		if (err_cnt >= 3 && (err != -ENODATA)) {
++			/* Disconnect due to zero BSSID or error to get RSSI */
++			scb_val_t scbval;
++			scbval.val = htod32(DOT11_RC_DISASSOC_LEAVING);
++			err = wldev_ioctl_set(dev, WLC_DISASSOC, &scbval, sizeof(scb_val_t));
++			if (unlikely(err)) {
++				WL_ERR(("disassoc error (%d)\n", err));
++			}
++
++			WL_ERR(("force cfg80211_disconnected: %d\n", err));
++			wl_clr_drv_status(cfg, CONNECTED, dev);
++			CFG80211_DISCONNECTED(dev, 0, NULL, 0, false, GFP_KERNEL);
++			wl_link_down(cfg);
++		}
++#ifdef DHD_SUPPORT_IF_CNTS
++error:
++		if (if_stats) {
++			kfree(if_stats);
++		}
++#endif /* DHD_SUPPORT_IF_CNTS */
++	}
++	else {
++		WL_ERR(("Invalid device mode %d\n", wl_get_mode_by_netdev(cfg, dev)));
++	}
++
++	return err;
++}
++
++static s32
++wl_cfg80211_set_power_mgmt(struct wiphy *wiphy, struct net_device *dev,
++	bool enabled, s32 timeout)
++{
++	s32 pm;
++	s32 err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_info *_net_info = wl_get_netinfo_by_netdev(cfg, dev);
++#ifdef RTT_SUPPORT
++	rtt_status_info_t *rtt_status;
++#endif /* RTT_SUPPORT */
++	dhd_pub_t *dhd = cfg->pub;
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	WL_DBG(("Enter\n"));
++	if (cfg->p2p_net == dev || _net_info == NULL ||
++			!wl_get_drv_status(cfg, CONNECTED, dev) ||
++			(wl_get_mode_by_netdev(cfg, dev) != WL_MODE_BSS &&
++			wl_get_mode_by_netdev(cfg, dev) != WL_MODE_IBSS)) {
++		return err;
++	}
++
++	/* Enlarge pm_enable_work */
++	wl_add_remove_pm_enable_work(cfg, WL_PM_WORKQ_LONG);
++
++	pm = enabled ? PM_FAST : PM_OFF;
++	if (_net_info->pm_block) {
++		WL_ERR(("%s:Do not enable the power save for pm_block %d\n",
++			dev->name, _net_info->pm_block));
++		pm = PM_OFF;
++	}
++	if (enabled && dhd_conf_get_pm(dhd) >= 0)
++		pm = dhd_conf_get_pm(dhd);
++	pm = htod32(pm);
++	WL_DBG(("%s:power save %s\n", dev->name, (pm ? "enabled" : "disabled")));
++#ifdef RTT_SUPPORT
++	rtt_status = GET_RTTSTATE(dhd);
++	if (rtt_status->status != RTT_ENABLED) {
++#endif /* RTT_SUPPORT */
++		err = wldev_ioctl_set(dev, WLC_SET_PM, &pm, sizeof(pm));
++		if (unlikely(err)) {
++			if (err == -ENODEV)
++				WL_DBG(("net_device is not ready yet\n"));
++			else
++				WL_ERR(("error (%d)\n", err));
++			return err;
++		}
++#ifdef RTT_SUPPORT
++	}
++#endif /* RTT_SUPPORT */
++	wl_cfg80211_update_power_mode(dev);
++	return err;
++}
++
++void wl_cfg80211_update_power_mode(struct net_device *dev)
++{
++	int err, pm = -1;
++
++	err = wldev_ioctl_get(dev, WLC_GET_PM, &pm, sizeof(pm));
++	if (err)
++		WL_ERR(("%s:error (%d)\n", __FUNCTION__, err));
++	else if (pm != -1 && dev->ieee80211_ptr)
++		dev->ieee80211_ptr->ps = (pm == PM_OFF) ? false : true;
++}
++
++void wl_cfg80211_set_passive_scan(struct net_device *dev, char *command)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++
++	if (strcmp(command, "SCAN-ACTIVE") == 0) {
++		cfg->active_scan = 1;
++	} else if (strcmp(command, "SCAN-PASSIVE") == 0) {
++		cfg->active_scan = 0;
++	} else
++		WL_ERR(("Unknown command \n"));
++}
++
++static __used u32 wl_find_msb(u16 bit16)
++{
++	u32 ret = 0;
++
++	if (bit16 & 0xff00) {
++		ret += 8;
++		bit16 >>= 8;
++	}
++
++	if (bit16 & 0xf0) {
++		ret += 4;
++		bit16 >>= 4;
++	}
++
++	if (bit16 & 0xc) {
++		ret += 2;
++		bit16 >>= 2;
++	}
++
++	if (bit16 & 2)
++		ret += bit16 & 2;
++	else if (bit16)
++		ret += bit16;
++
++	return ret;
++}
++
++static s32 wl_cfg80211_resume(struct wiphy *wiphy)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	s32 err = BCME_OK;
++
++	if (unlikely(!wl_get_drv_status(cfg, READY, ndev))) {
++		WL_INFORM(("device is not ready\n"));
++		return err;
++	}
++
++
++	return err;
++}
++
++
++static s32
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39))
++wl_cfg80211_suspend(struct wiphy *wiphy, struct cfg80211_wowlan *wow)
++#else
++wl_cfg80211_suspend(struct wiphy *wiphy)
++#endif /* KERNEL_VERSION(2, 6, 39) || WL_COMPAT_WIRELES */
++{
++	s32 err = BCME_OK;
++#ifdef DHD_CLEAR_ON_SUSPEND
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_info *iter, *next;
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	unsigned long flags;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
++	struct cfg80211_scan_info info;
++#endif
++
++	if (unlikely(!wl_get_drv_status(cfg, READY, ndev))) {
++		WL_INFORM(("device is not ready : status (%d)\n",
++			(int)cfg->status));
++		return err;
++	}
++	for_each_ndev(cfg, iter, next) {
++		/* p2p discovery iface doesn't have a ndev associated with it (for kernel > 3.8) */
++		if (iter->ndev)
++			wl_set_drv_status(cfg, SCAN_ABORTING, iter->ndev);
++		}
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++	if (cfg->scan_request) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
++		info.aborted = true;
++		cfg80211_scan_done(cfg->scan_request, &info);
++#else
++		cfg80211_scan_done(cfg->scan_request, true);
++#endif
++		cfg->scan_request = NULL;
++	}
++	for_each_ndev(cfg, iter, next) {
++		if (iter->ndev) {
++			wl_clr_drv_status(cfg, SCANNING, iter->ndev);
++			wl_clr_drv_status(cfg, SCAN_ABORTING, iter->ndev);
++		}
++	}
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++	for_each_ndev(cfg, iter, next) {
++		if (iter->ndev) {
++			if (wl_get_drv_status(cfg, CONNECTING, iter->ndev)) {
++				wl_bss_connect_done(cfg, iter->ndev, NULL, NULL, false);
++			}
++		}
++	}
++#endif /* DHD_CLEAR_ON_SUSPEND */
++
++
++	return err;
++}
++
++static s32
++wl_update_pmklist(struct net_device *dev, struct wl_pmk_list *pmk_list,
++	s32 err)
++{
++	int i, j;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	struct net_device *primary_dev = bcmcfg_to_prmry_ndev(cfg);
++
++	if (!pmk_list) {
++		WL_MSG(dev->name, "pmk_list is NULL\n");
++		return -EINVAL;
++	}
++	/* pmk list is supported only for STA interface i.e. primary interface
++	 * Refer code wlc_bsscfg.c->wlc_bsscfg_sta_init
++	 */
++	if (primary_dev != dev) {
++		WL_INFORM(("Not supporting Flushing pmklist on virtual"
++			" interfaces than primary interface\n"));
++		return err;
++	}
++
++	WL_DBG(("No of elements %d\n", pmk_list->pmkids.npmkid));
++	for (i = 0; i < pmk_list->pmkids.npmkid; i++) {
++		WL_DBG(("PMKID[%d]: %pM =\n", i,
++			&pmk_list->pmkids.pmkid[i].BSSID));
++		for (j = 0; j < WPA2_PMKID_LEN; j++) {
++			WL_DBG(("%02x\n", pmk_list->pmkids.pmkid[i].PMKID[j]));
++		}
++	}
++	if (likely(!err)) {
++		err = wldev_iovar_setbuf(dev, "pmkid_info", (char *)pmk_list,
++			sizeof(*pmk_list), cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++	}
++
++	return err;
++}
++
++static s32
++wl_cfg80211_set_pmksa(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_pmksa *pmksa)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 err = 0;
++	int i;
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	for (i = 0; i < cfg->pmk_list->pmkids.npmkid; i++)
++		if (!memcmp(pmksa->bssid, &cfg->pmk_list->pmkids.pmkid[i].BSSID,
++			ETHER_ADDR_LEN))
++			break;
++	if (i < WL_NUM_PMKIDS_MAX) {
++		memcpy(&cfg->pmk_list->pmkids.pmkid[i].BSSID, pmksa->bssid,
++			ETHER_ADDR_LEN);
++		memcpy(&cfg->pmk_list->pmkids.pmkid[i].PMKID, pmksa->pmkid,
++			WPA2_PMKID_LEN);
++		if (i == cfg->pmk_list->pmkids.npmkid)
++			cfg->pmk_list->pmkids.npmkid++;
++	} else {
++		err = -EINVAL;
++	}
++	WL_DBG(("set_pmksa,IW_PMKSA_ADD - PMKID: %pM =\n",
++		&cfg->pmk_list->pmkids.pmkid[cfg->pmk_list->pmkids.npmkid - 1].BSSID));
++	for (i = 0; i < WPA2_PMKID_LEN; i++) {
++		WL_DBG(("%02x\n",
++			cfg->pmk_list->pmkids.pmkid[cfg->pmk_list->pmkids.npmkid - 1].
++			PMKID[i]));
++	}
++
++	err = wl_update_pmklist(dev, cfg->pmk_list, err);
++
++	return err;
++}
++
++static s32
++wl_cfg80211_del_pmksa(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_pmksa *pmksa)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	struct _pmkid_list pmkid = {.npmkid = 0};
++	s32 err = 0;
++	int i;
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	memcpy(&pmkid.pmkid[0].BSSID, pmksa->bssid, ETHER_ADDR_LEN);
++	memcpy(pmkid.pmkid[0].PMKID, pmksa->pmkid, WPA2_PMKID_LEN);
++
++	WL_DBG(("del_pmksa,IW_PMKSA_REMOVE - PMKID: %pM =\n",
++		&pmkid.pmkid[0].BSSID));
++	for (i = 0; i < WPA2_PMKID_LEN; i++) {
++		WL_DBG(("%02x\n", pmkid.pmkid[0].PMKID[i]));
++	}
++
++	for (i = 0; i < cfg->pmk_list->pmkids.npmkid; i++)
++		if (!memcmp
++		    (pmksa->bssid, &cfg->pmk_list->pmkids.pmkid[i].BSSID,
++		     ETHER_ADDR_LEN))
++			break;
++
++	if ((cfg->pmk_list->pmkids.npmkid > 0) &&
++		(i < cfg->pmk_list->pmkids.npmkid)) {
++		memset(&cfg->pmk_list->pmkids.pmkid[i], 0, sizeof(pmkid_t));
++		for (; i < (cfg->pmk_list->pmkids.npmkid - 1); i++) {
++			memcpy(&cfg->pmk_list->pmkids.pmkid[i].BSSID,
++				&cfg->pmk_list->pmkids.pmkid[i + 1].BSSID,
++				ETHER_ADDR_LEN);
++			memcpy(&cfg->pmk_list->pmkids.pmkid[i].PMKID,
++				&cfg->pmk_list->pmkids.pmkid[i + 1].PMKID,
++				WPA2_PMKID_LEN);
++		}
++		cfg->pmk_list->pmkids.npmkid--;
++	} else {
++		err = -EINVAL;
++	}
++
++	err = wl_update_pmklist(dev, cfg->pmk_list, err);
++
++	return err;
++
++}
++
++static s32
++wl_cfg80211_flush_pmksa(struct wiphy *wiphy, struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 err = 0;
++	RETURN_EIO_IF_NOT_UP(cfg);
++	memset(cfg->pmk_list, 0, sizeof(*cfg->pmk_list));
++	err = wl_update_pmklist(dev, cfg->pmk_list, err);
++	return err;
++}
++
++static wl_scan_params_t *
++wl_cfg80211_scan_alloc_params(struct bcm_cfg80211 *cfg, int channel, int nprobes,
++	int *out_params_size)
++{
++	wl_scan_params_t *params;
++	int params_size;
++	int num_chans;
++	int bssidx = 0;
++
++	*out_params_size = 0;
++
++	/* Our scan params only need space for 1 channel and 0 ssids */
++	params_size = WL_SCAN_PARAMS_FIXED_SIZE + 1 * sizeof(uint16);
++	params = (wl_scan_params_t*) kzalloc(params_size, GFP_KERNEL);
++	if (params == NULL) {
++		WL_ERR(("mem alloc failed (%d bytes)\n", params_size));
++		return params;
++	}
++	memset(params, 0, params_size);
++	params->nprobes = nprobes;
++
++	num_chans = (channel == 0) ? 0 : 1;
++
++	memcpy(&params->bssid, &ether_bcast, ETHER_ADDR_LEN);
++	params->bss_type = DOT11_BSSTYPE_ANY;
++	params->scan_type = DOT11_SCANTYPE_ACTIVE;
++	params->nprobes = htod32(1);
++	params->active_time = htod32(-1);
++	params->passive_time = htod32(-1);
++	params->home_time = htod32(10);
++	if (channel == -1)
++		params->channel_list[0] = htodchanspec(channel);
++	else
++		params->channel_list[0] = wl_ch_host_to_driver(cfg, bssidx, channel);
++
++	/* Our scan params have 1 channel and 0 ssids */
++	params->channel_num = htod32((0 << WL_SCAN_PARAMS_NSSID_SHIFT) |
++		(num_chans & WL_SCAN_PARAMS_COUNT_MASK));
++
++	*out_params_size = params_size;	/* rtn size to the caller */
++	return params;
++}
++
++static s32
++#if defined(WL_CFG80211_P2P_DEV_IF)
++wl_cfg80211_remain_on_channel(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev,
++	struct ieee80211_channel *channel, unsigned int duration, u64 *cookie)
++#else
++wl_cfg80211_remain_on_channel(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev,
++	struct ieee80211_channel * channel,
++	enum nl80211_channel_type channel_type,
++	unsigned int duration, u64 *cookie)
++#endif /* WL_CFG80211_P2P_DEV_IF */
++{
++	s32 target_channel;
++	u32 id;
++	s32 err = BCME_OK;
++	struct ether_addr primary_mac;
++	struct net_device *ndev = NULL;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++#ifdef DHD_IFDEBUG
++	PRINT_WDEV_INFO(cfgdev);
++#endif /* DHD_IFDEBUG */
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	WL_DBG(("Enter, channel: %d, duration ms (%d) SCANNING ?? %s \n",
++		ieee80211_frequency_to_channel(channel->center_freq),
++		duration, (wl_get_drv_status(cfg, SCANNING, ndev)) ? "YES":"NO"));
++
++	if (!cfg->p2p) {
++		WL_ERR(("cfg->p2p is not initialized\n"));
++		err = BCME_ERROR;
++		goto exit;
++	}
++
++#ifdef P2P_LISTEN_OFFLOADING
++	if (wl_get_p2p_status(cfg, DISC_IN_PROGRESS)) {
++		WL_ERR(("P2P_FIND: Discovery offload is in progress\n"));
++		return -EAGAIN;
++	}
++#endif /* P2P_LISTEN_OFFLOADING */
++
++#ifndef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++	if (wl_get_drv_status_all(cfg, SCANNING)) {
++		wl_notify_escan_complete(cfg, cfg->escan_info.ndev, true, true);
++	}
++#endif /* not WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++
++	target_channel = ieee80211_frequency_to_channel(channel->center_freq);
++	memcpy(&cfg->remain_on_chan, channel, sizeof(struct ieee80211_channel));
++#if defined(WL_ENABLE_P2P_IF)
++	cfg->remain_on_chan_type = channel_type;
++#endif /* WL_ENABLE_P2P_IF */
++	id = ++cfg->last_roc_id;
++	if (id == 0)
++		id = ++cfg->last_roc_id;
++	*cookie = id;
++
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++	if (wl_get_drv_status(cfg, SCANNING, ndev)) {
++		timer_list_compat_t *_timer;
++		WL_DBG(("scan is running. go to fake listen state\n"));
++
++		if (duration > LONG_LISTEN_TIME) {
++			wl_cfg80211_scan_abort(cfg);
++		} else {
++			wl_set_drv_status(cfg, FAKE_REMAINING_ON_CHANNEL, ndev);
++
++			if (timer_pending(&cfg->p2p->listen_timer)) {
++				WL_DBG(("cancel current listen timer \n"));
++				_del_timer_sync(&cfg->p2p->listen_timer);
++			}
++
++			_timer = &cfg->p2p->listen_timer;
++			wl_clr_p2p_status(cfg, LISTEN_EXPIRED);
++
++			INIT_TIMER(_timer, wl_cfgp2p_listen_expired, duration, 0);
++
++			err = BCME_OK;
++			goto exit;
++		}
++	}
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++
++#ifdef WL_CFG80211_SYNC_GON
++	if (wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM_LISTEN)) {
++		/* do not enter listen mode again if we are in listen mode already for next af.
++		 * remain on channel completion will be returned by waiting next af completion.
++		 */
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++		wl_set_drv_status(cfg, FAKE_REMAINING_ON_CHANNEL, ndev);
++#else
++		wl_set_drv_status(cfg, REMAINING_ON_CHANNEL, ndev);
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++		goto exit;
++	}
++#endif /* WL_CFG80211_SYNC_GON */
++	if (cfg->p2p && !cfg->p2p->on) {
++		/* In case of p2p_listen command, supplicant send remain_on_channel
++		 * without turning on P2P
++		 */
++		get_primary_mac(cfg, &primary_mac);
++		wl_cfgp2p_generate_bss_mac(cfg, &primary_mac);
++		p2p_on(cfg) = true;
++	}
++
++	if (p2p_is_on(cfg)) {
++		err = wl_cfgp2p_enable_discovery(cfg, ndev, NULL, 0);
++		if (unlikely(err)) {
++			goto exit;
++		}
++#ifndef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++		wl_set_drv_status(cfg, REMAINING_ON_CHANNEL, ndev);
++#endif /* not WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++		err = wl_cfgp2p_discover_listen(cfg, target_channel, duration);
++
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++		if (err == BCME_OK) {
++			wl_set_drv_status(cfg, REMAINING_ON_CHANNEL, ndev);
++		} else {
++			/* if failed, firmware may be internal scanning state.
++			 * so other scan request shall not abort it
++			 */
++			wl_set_drv_status(cfg, FAKE_REMAINING_ON_CHANNEL, ndev);
++		}
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++		/* WAR: set err = ok to prevent cookie mismatch in wpa_supplicant
++		 * and expire timer will send a completion to the upper layer
++		 */
++		err = BCME_OK;
++	}
++
++exit:
++	if (err == BCME_OK) {
++		WL_INFORM(("Success\n"));
++#if defined(WL_CFG80211_P2P_DEV_IF)
++		cfg80211_ready_on_channel(cfgdev, *cookie, channel,
++			duration, GFP_KERNEL);
++#else
++		cfg80211_ready_on_channel(cfgdev, *cookie, channel,
++			channel_type, duration, GFP_KERNEL);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++	} else {
++		WL_ERR(("Fail to Set (err=%d cookie:%llu)\n", err, *cookie));
++	}
++	return err;
++}
++
++static s32
++wl_cfg80211_cancel_remain_on_channel(struct wiphy *wiphy,
++	bcm_struct_cfgdev *cfgdev, u64 cookie)
++{
++	s32 err = 0;
++
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++#ifdef P2PLISTEN_AP_SAMECHN
++	struct net_device *dev;
++#endif /* P2PLISTEN_AP_SAMECHN */
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++
++#ifdef DHD_IFDEBUG
++	PRINT_WDEV_INFO(cfgdev);
++#endif /* DHD_IFDEBUG */
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	if (cfgdev->iftype == NL80211_IFTYPE_P2P_DEVICE) {
++		WL_DBG((" enter ) on P2P dedicated discover interface\n"));
++	}
++#else
++	WL_DBG((" enter ) netdev_ifidx: %d \n", cfgdev->ifindex));
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++#ifdef P2PLISTEN_AP_SAMECHN
++	if (cfg && cfg->p2p_resp_apchn_status) {
++		dev = bcmcfg_to_prmry_ndev(cfg);
++		wl_cfg80211_set_p2p_resp_ap_chn(dev, 0);
++		cfg->p2p_resp_apchn_status = false;
++		WL_DBG(("p2p_resp_apchn_status Turn OFF \n"));
++	}
++#endif /* P2PLISTEN_AP_SAMECHN */
++
++	if (cfg->last_roc_id == cookie) {
++		wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_SCAN, 0, 0,
++			wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE));
++	} else {
++		WL_ERR(("%s : ignore, request cookie(%llu) is not matched. (cur : %llu)\n",
++			__FUNCTION__, cookie, cfg->last_roc_id));
++	}
++
++	return err;
++}
++
++static void
++wl_cfg80211_afx_handler(struct work_struct *work)
++{
++	struct afx_hdl *afx_instance;
++	struct bcm_cfg80211 *cfg;
++	s32 ret = BCME_OK;
++
++	BCM_SET_CONTAINER_OF(afx_instance, work, struct afx_hdl, work);
++	if (!afx_instance) {
++		WL_ERR(("afx_instance is NULL\n"));
++		return;
++	}
++	cfg = wl_get_cfg(afx_instance->dev);
++	if (afx_instance) {
++		if (cfg->afx_hdl->is_active) {
++			if (cfg->afx_hdl->is_listen && cfg->afx_hdl->my_listen_chan) {
++				ret = wl_cfgp2p_discover_listen(cfg, cfg->afx_hdl->my_listen_chan,
++					(100 * (1 + (RANDOM32() % 3)))); /* 100ms ~ 300ms */
++			} else {
++				ret = wl_cfgp2p_act_frm_search(cfg, cfg->afx_hdl->dev,
++					cfg->afx_hdl->bssidx, cfg->afx_hdl->peer_listen_chan,
++					NULL);
++			}
++			if (unlikely(ret != BCME_OK)) {
++				WL_ERR(("ERROR occurred! returned value is (%d)\n", ret));
++				if (wl_get_drv_status_all(cfg, FINDING_COMMON_CHANNEL))
++					complete(&cfg->act_frm_scan);
++			}
++		}
++	}
++}
++
++static s32
++wl_cfg80211_af_searching_channel(struct bcm_cfg80211 *cfg, struct net_device *dev)
++{
++	u32 max_retry = WL_CHANNEL_SYNC_RETRY;
++	bool is_p2p_gas = false;
++
++	if (dev == NULL)
++		return -1;
++
++	WL_DBG((" enter ) \n"));
++
++	wl_set_drv_status(cfg, FINDING_COMMON_CHANNEL, dev);
++	cfg->afx_hdl->is_active = TRUE;
++
++	if (cfg->afx_hdl->pending_tx_act_frm) {
++		wl_action_frame_t *action_frame;
++		action_frame = &(cfg->afx_hdl->pending_tx_act_frm->action_frame);
++		if (wl_cfgp2p_is_p2p_gas_action(action_frame->data, action_frame->len))
++			is_p2p_gas = true;
++	}
++
++	/* Loop to wait until we find a peer's channel or the
++	 * pending action frame tx is cancelled.
++	 */
++	while ((cfg->afx_hdl->retry < max_retry) &&
++		(cfg->afx_hdl->peer_chan == WL_INVALID)) {
++		cfg->afx_hdl->is_listen = FALSE;
++		wl_set_drv_status(cfg, SCANNING, dev);
++		WL_DBG(("Scheduling the action frame for sending.. retry %d\n",
++			cfg->afx_hdl->retry));
++		/* search peer on peer's listen channel */
++		schedule_work(&cfg->afx_hdl->work);
++		wait_for_completion_timeout(&cfg->act_frm_scan,
++			msecs_to_jiffies(WL_AF_SEARCH_TIME_MAX));
++
++		if ((cfg->afx_hdl->peer_chan != WL_INVALID) ||
++			!(wl_get_drv_status(cfg, FINDING_COMMON_CHANNEL, dev)))
++			break;
++
++		if (is_p2p_gas)
++			break;
++
++		if (cfg->afx_hdl->my_listen_chan) {
++			WL_DBG(("Scheduling Listen peer in my listen channel = %d\n",
++				cfg->afx_hdl->my_listen_chan));
++			/* listen on my listen channel */
++			cfg->afx_hdl->is_listen = TRUE;
++			schedule_work(&cfg->afx_hdl->work);
++			wait_for_completion_timeout(&cfg->act_frm_scan,
++				msecs_to_jiffies(WL_AF_SEARCH_TIME_MAX));
++		}
++		if ((cfg->afx_hdl->peer_chan != WL_INVALID) ||
++			!(wl_get_drv_status(cfg, FINDING_COMMON_CHANNEL, dev)))
++			break;
++
++		cfg->afx_hdl->retry++;
++
++		WL_AF_TX_KEEP_PRI_CONNECTION_VSDB(cfg);
++	}
++
++	cfg->afx_hdl->is_active = FALSE;
++
++	wl_clr_drv_status(cfg, SCANNING, dev);
++	wl_clr_drv_status(cfg, FINDING_COMMON_CHANNEL, dev);
++
++	return (cfg->afx_hdl->peer_chan);
++}
++
++struct p2p_config_af_params {
++	s32 max_tx_retry;	/* max tx retry count if tx no ack */
++#ifdef WL_CFG80211_SYNC_GON
++	bool extra_listen;
++#endif
++	bool search_channel;	/* 1: search peer's channel to send af */
++};
++
++static s32
++wl_cfg80211_config_p2p_pub_af_tx(struct wiphy *wiphy,
++	wl_action_frame_t *action_frame, wl_af_params_t *af_params,
++	struct p2p_config_af_params *config_af_params)
++{
++	s32 err = BCME_OK;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	wifi_p2p_pub_act_frame_t *act_frm =
++		(wifi_p2p_pub_act_frame_t *) (action_frame->data);
++
++	/* initialize default value */
++#ifdef WL_CFG80211_SYNC_GON
++	config_af_params->extra_listen = true;
++#endif
++	config_af_params->search_channel = false;
++	config_af_params->max_tx_retry = WL_AF_TX_MAX_RETRY;
++	cfg->next_af_subtype = P2P_PAF_SUBTYPE_INVALID;
++
++	switch (act_frm->subtype) {
++	case P2P_PAF_GON_REQ: {
++		WL_DBG(("P2P: GO_NEG_PHASE status set \n"));
++		wl_set_p2p_status(cfg, GO_NEG_PHASE);
++
++		config_af_params->search_channel = true;
++		cfg->next_af_subtype = act_frm->subtype + 1;
++
++		/* increase dwell time to wait for RESP frame */
++		af_params->dwell_time = WL_MED_DWELL_TIME;
++
++		break;
++	}
++	case P2P_PAF_GON_RSP: {
++		cfg->next_af_subtype = act_frm->subtype + 1;
++		/* increase dwell time to wait for CONF frame */
++		af_params->dwell_time = WL_MED_DWELL_TIME + 100;
++		break;
++	}
++	case P2P_PAF_GON_CONF: {
++		/* If we reached till GO Neg confirmation reset the filter */
++		WL_DBG(("P2P: GO_NEG_PHASE status cleared \n"));
++		wl_clr_p2p_status(cfg, GO_NEG_PHASE);
++
++		/* minimize dwell time */
++		af_params->dwell_time = WL_MIN_DWELL_TIME;
++
++#ifdef WL_CFG80211_SYNC_GON
++		config_af_params->extra_listen = false;
++#endif /* WL_CFG80211_SYNC_GON */
++		break;
++	}
++	case P2P_PAF_INVITE_REQ: {
++		config_af_params->search_channel = true;
++		cfg->next_af_subtype = act_frm->subtype + 1;
++
++		/* increase dwell time */
++		af_params->dwell_time = WL_MED_DWELL_TIME;
++		break;
++	}
++	case P2P_PAF_INVITE_RSP:
++		/* minimize dwell time */
++		af_params->dwell_time = WL_MIN_DWELL_TIME;
++#ifdef WL_CFG80211_SYNC_GON
++		config_af_params->extra_listen = false;
++#endif /* WL_CFG80211_SYNC_GON */
++		break;
++	case P2P_PAF_DEVDIS_REQ: {
++		if (IS_ACTPUB_WITHOUT_GROUP_ID(&act_frm->elts[0],
++			action_frame->len)) {
++			config_af_params->search_channel = true;
++		}
++
++		cfg->next_af_subtype = act_frm->subtype + 1;
++		/* maximize dwell time to wait for RESP frame */
++		af_params->dwell_time = WL_LONG_DWELL_TIME;
++		break;
++	}
++	case P2P_PAF_DEVDIS_RSP:
++		/* minimize dwell time */
++		af_params->dwell_time = WL_MIN_DWELL_TIME;
++#ifdef WL_CFG80211_SYNC_GON
++		config_af_params->extra_listen = false;
++#endif /* WL_CFG80211_SYNC_GON */
++		break;
++	case P2P_PAF_PROVDIS_REQ: {
++		if (IS_ACTPUB_WITHOUT_GROUP_ID(&act_frm->elts[0],
++			action_frame->len)) {
++			config_af_params->search_channel = true;
++		}
++
++		cfg->next_af_subtype = act_frm->subtype + 1;
++		/* increase dwell time to wait for RESP frame */
++		af_params->dwell_time = WL_MED_DWELL_TIME;
++		break;
++	}
++	case P2P_PAF_PROVDIS_RSP: {
++		cfg->next_af_subtype = P2P_PAF_GON_REQ;
++		af_params->dwell_time = WL_MED_DWELL_TIME;
++#ifdef WL_CFG80211_SYNC_GON
++		config_af_params->extra_listen = false;
++#endif /* WL_CFG80211_SYNC_GON */
++		break;
++	}
++	default:
++		WL_DBG(("Unknown p2p pub act frame subtype: %d\n",
++			act_frm->subtype));
++		err = BCME_BADARG;
++	}
++	return err;
++}
++
++#ifdef WL11U
++static bool
++wl_cfg80211_check_DFS_channel(struct bcm_cfg80211 *cfg, wl_af_params_t *af_params,
++	void *frame, u16 frame_len)
++{
++	struct wl_scan_results *bss_list;
++	struct wl_bss_info *bi = NULL;
++	bool result = false;
++	s32 i;
++	chanspec_t chanspec;
++
++	/* If DFS channel is 52~148, check to block it or not */
++	if (af_params &&
++		(af_params->channel >= 52 && af_params->channel <= 148)) {
++		if (!wl_cfgp2p_is_p2p_action(frame, frame_len)) {
++			bss_list = cfg->bss_list;
++			bi = next_bss(bss_list, bi);
++			for_each_bss(bss_list, bi, i) {
++				chanspec = wl_chspec_driver_to_host(bi->chanspec);
++				if (CHSPEC_IS5G(chanspec) &&
++					((bi->ctl_ch ? bi->ctl_ch : CHSPEC_CHANNEL(chanspec))
++					== af_params->channel)) {
++					result = true;	/* do not block the action frame */
++					break;
++				}
++			}
++		}
++	}
++	else {
++		result = true;
++	}
++
++	WL_DBG(("result=%s", result?"true":"false"));
++	return result;
++}
++#endif /* WL11U */
++static bool
++wl_cfg80211_check_dwell_overflow(int32 requested_dwell, ulong dwell_jiffies)
++{
++	if ((requested_dwell & CUSTOM_RETRY_MASK) &&
++			(jiffies_to_msecs(jiffies - dwell_jiffies) >
++			 (requested_dwell & ~CUSTOM_RETRY_MASK))) {
++		WL_ERR(("Action frame TX retry time over dwell time!\n"));
++		return true;
++	}
++	return false;
++}
++
++static bool
++wl_cfg80211_send_action_frame(struct wiphy *wiphy, struct net_device *dev,
++	bcm_struct_cfgdev *cfgdev, wl_af_params_t *af_params,
++	wl_action_frame_t *action_frame, u16 action_frame_len, s32 bssidx)
++{
++#ifdef WL11U
++	struct net_device *ndev = NULL;
++#endif /* WL11U */
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	bool ack = false;
++	u8 category, action;
++	s32 tx_retry;
++	struct p2p_config_af_params config_af_params;
++	struct net_info *netinfo;
++#ifdef VSDB
++	ulong off_chan_started_jiffies = 0;
++#endif
++	ulong dwell_jiffies = 0;
++	bool dwell_overflow = false;
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++	bool miss_gon_cfm = false;
++
++	int32 requested_dwell = af_params->dwell_time;
++
++	/* Add the default dwell time
++	 * Dwell time to stay off-channel to wait for a response action frame
++	 * after transmitting an GO Negotiation action frame
++	 */
++	af_params->dwell_time = WL_DWELL_TIME;
++
++#ifdef WL11U
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	ndev = dev;
++#else
++	ndev = ndev_to_cfgdev(cfgdev);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++#endif /* WL11U */
++
++	category = action_frame->data[DOT11_ACTION_CAT_OFF];
++	action = action_frame->data[DOT11_ACTION_ACT_OFF];
++
++	/* initialize variables */
++	tx_retry = 0;
++	cfg->next_af_subtype = P2P_PAF_SUBTYPE_INVALID;
++	config_af_params.max_tx_retry = WL_AF_TX_MAX_RETRY;
++	config_af_params.search_channel = false;
++#ifdef WL_CFG80211_SYNC_GON
++	config_af_params.extra_listen = false;
++#endif
++
++	/* config parameters */
++	/* Public Action Frame Process - DOT11_ACTION_CAT_PUBLIC */
++	if (category == DOT11_ACTION_CAT_PUBLIC) {
++		if ((action == P2P_PUB_AF_ACTION) &&
++			(action_frame_len >= sizeof(wifi_p2p_pub_act_frame_t))) {
++			/* p2p public action frame process */
++			if (BCME_OK != wl_cfg80211_config_p2p_pub_af_tx(wiphy,
++				action_frame, af_params, &config_af_params)) {
++				WL_DBG(("Unknown subtype.\n"));
++			}
++
++		} else if (action_frame_len >= sizeof(wifi_p2psd_gas_pub_act_frame_t)) {
++			/* service discovery process */
++			if (action == P2PSD_ACTION_ID_GAS_IREQ ||
++				action == P2PSD_ACTION_ID_GAS_CREQ) {
++				/* configure service discovery query frame */
++
++				config_af_params.search_channel = true;
++
++				/* save next af suptype to cancel remained dwell time */
++				cfg->next_af_subtype = action + 1;
++
++				af_params->dwell_time = WL_MED_DWELL_TIME;
++				if (requested_dwell & CUSTOM_RETRY_MASK) {
++					config_af_params.max_tx_retry =
++						(requested_dwell & CUSTOM_RETRY_MASK) >> 24;
++					af_params->dwell_time =
++						(requested_dwell & ~CUSTOM_RETRY_MASK);
++					WL_DBG(("Custom retry(%d) and dwell time(%d) is set.\n",
++						config_af_params.max_tx_retry,
++						af_params->dwell_time));
++				}
++			} else if (action == P2PSD_ACTION_ID_GAS_IRESP ||
++				action == P2PSD_ACTION_ID_GAS_CRESP) {
++				/* configure service discovery response frame */
++				af_params->dwell_time = WL_MIN_DWELL_TIME;
++			} else {
++				WL_DBG(("Unknown action type: %d\n", action));
++			}
++		} else {
++			WL_DBG(("Unknown Frame: category 0x%x, action 0x%x, length %d\n",
++				category, action, action_frame_len));
++		}
++	} else if (category == P2P_AF_CATEGORY) {
++		/* do not configure anything. it will be sent with a default configuration */
++	} else {
++		WL_DBG(("Unknown Frame: category 0x%x, action 0x%x\n",
++			category, action));
++		if (dhd->op_mode & DHD_FLAG_HOSTAP_MODE) {
++			wl_clr_drv_status(cfg, SENDING_ACT_FRM, dev);
++			return false;
++		}
++	}
++	netinfo = wl_get_netinfo_by_bssidx(cfg, bssidx);
++	/* validate channel and p2p ies */
++	if (config_af_params.search_channel && IS_P2P_SOCIAL(af_params->channel) &&
++		netinfo && netinfo->bss.ies.probe_req_ie_len) {
++		config_af_params.search_channel = true;
++	} else {
++		config_af_params.search_channel = false;
++	}
++#ifdef WL11U
++	if (ndev == bcmcfg_to_prmry_ndev(cfg))
++		config_af_params.search_channel = false;
++#endif /* WL11U */
++
++#ifdef VSDB
++	/* if connecting on primary iface, sleep for a while before sending af tx for VSDB */
++	if (wl_get_drv_status(cfg, CONNECTING, bcmcfg_to_prmry_ndev(cfg))) {
++		OSL_SLEEP(50);
++	}
++#endif
++
++	/* if scan is ongoing, abort current scan. */
++	if (wl_get_drv_status_all(cfg, SCANNING)) {
++		wl_notify_escan_complete(cfg, cfg->escan_info.ndev, true, true);
++	}
++
++	/* Abort P2P listen */
++	if (discover_cfgdev(cfgdev, cfg)) {
++		if (cfg->p2p_supported && cfg->p2p) {
++			wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_SCAN, 0, 0,
++				wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE));
++		}
++	}
++
++#ifdef WL11U
++	/* handling DFS channel exceptions */
++	if (!wl_cfg80211_check_DFS_channel(cfg, af_params, action_frame->data, action_frame->len)) {
++		return false;	/* the action frame was blocked */
++	}
++#endif /* WL11U */
++
++	/* set status and destination address before sending af */
++	if (cfg->next_af_subtype != P2P_PAF_SUBTYPE_INVALID) {
++		/* set this status to cancel the remained dwell time in rx process */
++		wl_set_drv_status(cfg, WAITING_NEXT_ACT_FRM, dev);
++	}
++	wl_set_drv_status(cfg, SENDING_ACT_FRM, dev);
++	memcpy(cfg->afx_hdl->tx_dst_addr.octet,
++		af_params->action_frame.da.octet,
++		sizeof(cfg->afx_hdl->tx_dst_addr.octet));
++
++	/* save af_params for rx process */
++	cfg->afx_hdl->pending_tx_act_frm = af_params;
++
++	if (wl_cfgp2p_is_p2p_gas_action(action_frame->data, action_frame->len)) {
++		WL_DBG(("Set GAS action frame config.\n"));
++		config_af_params.search_channel = false;
++		config_af_params.max_tx_retry = 1;
++	}
++
++	/* search peer's channel */
++	if (config_af_params.search_channel) {
++		/* initialize afx_hdl */
++		if ((cfg->afx_hdl->bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++			WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++			goto exit;
++		}
++		cfg->afx_hdl->dev = dev;
++		cfg->afx_hdl->retry = 0;
++		cfg->afx_hdl->peer_chan = WL_INVALID;
++
++		if (wl_cfg80211_af_searching_channel(cfg, dev) == WL_INVALID) {
++			WL_ERR(("couldn't find peer's channel.\n"));
++			wl_cfgp2p_print_actframe(true, action_frame->data, action_frame->len,
++				af_params->channel);
++			/* Even if we couldn't find peer channel, try to send the frame
++			 * out. P2P cert 5.1.14 testbed device (realtek) doesn't seem to
++			 * respond to probe request (Ideally it has to be in listen and
++			 * responsd to probe request). However if we send Go neg req, the
++			 * peer is sending GO-neg resp. So instead of giving up here, just
++			 * proceed and attempt sending out the action frame.
++			 */
++		}
++
++		wl_clr_drv_status(cfg, SCANNING, cfg->afx_hdl->dev);
++		/*
++		 * Abort scan even for VSDB scenarios. Scan gets aborted in firmware
++		 * but after the check of piggyback algorithm.
++		 * To take care of current piggback algo, lets abort the scan here itself.
++		 */
++		wl_notify_escan_complete(cfg, dev, true, true);
++		/* Suspend P2P discovery's search-listen to prevent it from
++		 * starting a scan or changing the channel.
++		 */
++		if ((wl_cfgp2p_discover_enable_search(cfg, false)) < 0) {
++			WL_ERR(("Can not disable discovery mode\n"));
++			goto exit;
++		}
++
++		/* update channel */
++		if (cfg->afx_hdl->peer_chan != WL_INVALID) {
++			af_params->channel = cfg->afx_hdl->peer_chan;
++			WL_ERR(("Attempt tx on peer listen channel:%d ",
++				cfg->afx_hdl->peer_chan));
++		} else {
++			WL_ERR(("Attempt tx with the channel provided by userspace."
++			"Channel: %d\n", af_params->channel));
++		}
++	}
++
++#ifdef VSDB
++	off_chan_started_jiffies = jiffies;
++#endif /* VSDB */
++
++	wl_cfgp2p_print_actframe(true, action_frame->data, action_frame->len, af_params->channel);
++
++	wl_cfgp2p_need_wait_actfrmae(cfg, action_frame->data, action_frame->len, true);
++
++	dwell_jiffies = jiffies;
++	/* Now send a tx action frame */
++	ack = wl_cfgp2p_tx_action_frame(cfg, dev, af_params, bssidx) ? false : true;
++	dwell_overflow = wl_cfg80211_check_dwell_overflow(requested_dwell, dwell_jiffies);
++
++	if (ack && (wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM))) {
++		wifi_p2p_pub_act_frame_t *pact_frm;
++		pact_frm = (wifi_p2p_pub_act_frame_t *)(action_frame->data);
++		if (pact_frm->subtype == P2P_PAF_GON_RSP) {
++			WL_ERR(("Miss GO Nego cfm after P2P_PAF_GON_RSP\n"));
++			miss_gon_cfm = true;
++		}
++	}
++
++	/* if failed, retry it. tx_retry_max value is configure by .... */
++	while ((miss_gon_cfm || (ack == false)) && (tx_retry++ < config_af_params.max_tx_retry) &&
++			!dwell_overflow) {
++#ifdef VSDB
++		if (af_params->channel) {
++			if (jiffies_to_msecs(jiffies - off_chan_started_jiffies) >
++				OFF_CHAN_TIME_THRESHOLD_MS) {
++				WL_AF_TX_KEEP_PRI_CONNECTION_VSDB(cfg);
++				off_chan_started_jiffies = jiffies;
++			} else
++				OSL_SLEEP(AF_RETRY_DELAY_TIME);
++		}
++#endif /* VSDB */
++		ack = wl_cfgp2p_tx_action_frame(cfg, dev, af_params, bssidx) ?
++			false : true;
++		if (miss_gon_cfm && !wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM)) {
++			WL_ERR(("Received GO Nego cfm after P2P_PAF_GON_RSP\n"));
++			miss_gon_cfm = false;
++		}
++		dwell_overflow = wl_cfg80211_check_dwell_overflow(requested_dwell, dwell_jiffies);
++	}
++
++	if (ack == false) {
++		WL_ERR(("Failed to send Action Frame(retry %d)\n", tx_retry));
++	}
++	WL_DBG(("Complete to send action frame\n"));
++exit:
++	/* Clear SENDING_ACT_FRM after all sending af is done */
++	wl_clr_drv_status(cfg, SENDING_ACT_FRM, dev);
++
++#ifdef WL_CFG80211_SYNC_GON
++	/* WAR: sometimes dongle does not keep the dwell time of 'actframe'.
++	 * if we coundn't get the next action response frame and dongle does not keep
++	 * the dwell time, go to listen state again to get next action response frame.
++	 */
++	if (ack && config_af_params.extra_listen &&
++		wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM) &&
++		cfg->af_sent_channel == cfg->afx_hdl->my_listen_chan) {
++		s32 extar_listen_time;
++
++		extar_listen_time = af_params->dwell_time -
++			jiffies_to_msecs(jiffies - cfg->af_tx_sent_jiffies);
++
++		if (extar_listen_time > 50) {
++			wl_set_drv_status(cfg, WAITING_NEXT_ACT_FRM_LISTEN, dev);
++			WL_DBG(("Wait more time! actual af time:%d,"
++				"calculated extar listen:%d\n",
++				af_params->dwell_time, extar_listen_time));
++			if (wl_cfgp2p_discover_listen(cfg, cfg->af_sent_channel,
++				extar_listen_time + 100) == BCME_OK) {
++				wait_for_completion_timeout(&cfg->wait_next_af,
++					msecs_to_jiffies(extar_listen_time + 100 + 300));
++			}
++			wl_clr_drv_status(cfg, WAITING_NEXT_ACT_FRM_LISTEN, dev);
++		}
++	}
++#endif /* WL_CFG80211_SYNC_GON */
++	wl_clr_drv_status(cfg, WAITING_NEXT_ACT_FRM, dev);
++	cfg->afx_hdl->pending_tx_act_frm = NULL;
++
++	WL_INFORM(("-- sending Action Frame is %s, listen chan: %d\n",
++		(ack) ? "Succeeded!!":"Failed!!", cfg->afx_hdl->my_listen_chan));
++
++	return ack;
++}
++
++#define MAX_NUM_OF_ASSOCIATED_DEV       64
++static s32
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
++wl_cfg80211_mgmt_tx(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev,
++	struct cfg80211_mgmt_tx_params *params, u64 *cookie)
++#else
++wl_cfg80211_mgmt_tx(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev,
++	struct ieee80211_channel *channel, bool offchan,
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 7, 0))
++	enum nl80211_channel_type channel_type,
++	bool channel_type_valid,
++#endif /* LINUX_VERSION_CODE <= KERNEL_VERSION(3, 7, 0) */
++	unsigned int wait, const u8* buf, size_t len,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	bool no_cck,
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
++	bool dont_wait_for_ack,
++#endif
++	u64 *cookie)
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) */
++{
++	wl_action_frame_t *action_frame;
++	wl_af_params_t *af_params;
++	scb_val_t scb_val;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
++	struct ieee80211_channel *channel = params->chan;
++	const u8 *buf = params->buf;
++	size_t len = params->len;
++#endif
++	const struct ieee80211_mgmt *mgmt;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *dev = NULL;
++	s32 err = BCME_OK;
++	s32 bssidx = 0;
++	u32 id;
++	bool ack = false;
++	s8 eabuf[ETHER_ADDR_STR_LEN];
++
++	WL_DBG(("Enter \n"));
++
++	if (len > ACTION_FRAME_SIZE) {
++		WL_ERR(("bad length:%zu\n", len));
++		return BCME_BADLEN;
++	}
++#ifdef DHD_IFDEBUG
++	PRINT_WDEV_INFO(cfgdev);
++#endif /* DHD_IFDEBUG */
++
++	dev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	if (!dev) {
++		WL_ERR(("dev is NULL\n"));
++		return -EINVAL;
++	}
++
++	/* set bsscfg idx for iovar (wlan0: P2PAPI_BSSCFG_PRIMARY, p2p: P2PAPI_BSSCFG_DEVICE)	*/
++	if (discover_cfgdev(cfgdev, cfg)) {
++		if (!cfg->p2p_supported || !cfg->p2p) {
++			WL_ERR(("P2P doesn't setup completed yet\n"));
++			return -EINVAL;
++		}
++		bssidx = wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++	}
++	else {
++		if ((bssidx = wl_get_bssidx_by_wdev(cfg, cfgdev_to_wdev(cfgdev))) < 0) {
++			WL_ERR(("Find p2p index failed\n"));
++			return BCME_ERROR;
++		}
++	}
++
++	WL_DBG(("TX target bssidx=%d\n", bssidx));
++
++	if (p2p_is_on(cfg)) {
++		/* Suspend P2P discovery search-listen to prevent it from changing the
++		 * channel.
++		 */
++		if ((err = wl_cfgp2p_discover_enable_search(cfg, false)) < 0) {
++			WL_ERR(("Can not disable discovery mode\n"));
++			return -EFAULT;
++		}
++	}
++	*cookie = 0;
++	id = cfg->send_action_id++;
++	if (id == 0)
++		id = cfg->send_action_id++;
++	*cookie = id;
++	mgmt = (const struct ieee80211_mgmt *)buf;
++	if (ieee80211_is_mgmt(mgmt->frame_control)) {
++		if (ieee80211_is_probe_resp(mgmt->frame_control)) {
++			s32 ie_offset =  DOT11_MGMT_HDR_LEN + DOT11_BCN_PRB_FIXED_LEN;
++			s32 ie_len = len - ie_offset;
++			if ((dev == bcmcfg_to_prmry_ndev(cfg)) && cfg->p2p) {
++				bssidx = wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++			}
++			wl_cfg80211_set_mgmt_vndr_ies(cfg, ndev_to_cfgdev(dev), bssidx,
++				VNDR_IE_PRBRSP_FLAG, (const u8 *)(buf + ie_offset), ie_len);
++			cfg80211_mgmt_tx_status(cfgdev, *cookie, buf, len, true, GFP_KERNEL);
++#if defined(P2P_IE_MISSING_FIX)
++			if (!cfg->p2p_prb_noti) {
++				cfg->p2p_prb_noti = true;
++				WL_DBG(("%s: TX 802_1X Probe Response first time.\n",
++					__FUNCTION__));
++			}
++#endif
++			goto exit;
++		} else if (ieee80211_is_disassoc(mgmt->frame_control) ||
++			ieee80211_is_deauth(mgmt->frame_control)) {
++			char mac_buf[MAX_NUM_OF_ASSOCIATED_DEV *
++				sizeof(struct ether_addr) + sizeof(uint)] = {0};
++			int num_associated = 0;
++			struct maclist *assoc_maclist = (struct maclist *)mac_buf;
++			if (!bcmp((const uint8 *)BSSID_BROADCAST,
++				(const struct ether_addr *)mgmt->da, ETHER_ADDR_LEN)) {
++				assoc_maclist->count = MAX_NUM_OF_ASSOCIATED_DEV;
++				err = wldev_ioctl_get(dev, WLC_GET_ASSOCLIST,
++					assoc_maclist, sizeof(mac_buf));
++				if (err < 0)
++					WL_ERR(("WLC_GET_ASSOCLIST error %d\n", err));
++				else
++					num_associated = assoc_maclist->count;
++			}
++			memcpy(scb_val.ea.octet, mgmt->da, ETH_ALEN);
++			scb_val.val = mgmt->u.disassoc.reason_code;
++			err = wldev_ioctl_set(dev, WLC_SCB_DEAUTHENTICATE_FOR_REASON, &scb_val,
++				sizeof(scb_val_t));
++			if (err < 0)
++				WL_ERR(("WLC_SCB_DEAUTHENTICATE_FOR_REASON error %d\n", err));
++			WL_ERR(("Disconnect STA : %s scb_val.val %d\n",
++				bcm_ether_ntoa((const struct ether_addr *)mgmt->da, eabuf),
++				scb_val.val));
++
++			if (num_associated > 0 && ETHER_ISBCAST(mgmt->da))
++				wl_delay(400);
++
++			cfg80211_mgmt_tx_status(cfgdev, *cookie, buf, len, true, GFP_KERNEL);
++			goto exit;
++
++		} else if (ieee80211_is_action(mgmt->frame_control)) {
++			/* Abort the dwell time of any previous off-channel
++			* action frame that may be still in effect.  Sending
++			* off-channel action frames relies on the driver's
++			* scan engine.  If a previous off-channel action frame
++			* tx is still in progress (including the dwell time),
++			* then this new action frame will not be sent out.
++			*/
++/* Do not abort scan for VSDB. Scan will be aborted in firmware if necessary.
++ * And previous off-channel action frame must be ended before new af tx.
++ */
++#ifndef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++			wl_notify_escan_complete(cfg, dev, true, true);
++#endif /* not WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++		}
++
++	} else {
++		WL_ERR(("Driver only allows MGMT packet type\n"));
++		goto exit;
++	}
++
++	af_params = (wl_af_params_t *) kzalloc(WL_WIFI_AF_PARAMS_SIZE, GFP_KERNEL);
++
++	if (af_params == NULL)
++	{
++		WL_ERR(("unable to allocate frame\n"));
++		return -ENOMEM;
++	}
++
++	action_frame = &af_params->action_frame;
++
++	/* Add the packet Id */
++	action_frame->packetId = *cookie;
++	WL_DBG(("action frame %d\n", action_frame->packetId));
++	/* Add BSSID */
++	memcpy(&action_frame->da, &mgmt->da[0], ETHER_ADDR_LEN);
++	memcpy(&af_params->BSSID, &mgmt->bssid[0], ETHER_ADDR_LEN);
++
++	/* Add the length exepted for 802.11 header  */
++	action_frame->len = len - DOT11_MGMT_HDR_LEN;
++	WL_DBG(("action_frame->len: %d\n", action_frame->len));
++
++	/* Add the channel */
++	af_params->channel =
++		ieee80211_frequency_to_channel(channel->center_freq);
++	/* Save listen_chan for searching common channel */
++	cfg->afx_hdl->peer_listen_chan = af_params->channel;
++	WL_DBG(("channel from upper layer %d\n", cfg->afx_hdl->peer_listen_chan));
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
++	af_params->dwell_time = params->wait;
++#else
++	af_params->dwell_time = wait;
++#endif
++
++	memcpy(action_frame->data, &buf[DOT11_MGMT_HDR_LEN], action_frame->len);
++
++	ack = wl_cfg80211_send_action_frame(wiphy, dev, cfgdev, af_params,
++		action_frame, action_frame->len, bssidx);
++	cfg80211_mgmt_tx_status(cfgdev, *cookie, buf, len, ack, GFP_KERNEL);
++
++	kfree(af_params);
++exit:
++	return err;
++}
++
++static s32
++wl_cfg80211_change_bss(struct wiphy *wiphy,
++	struct net_device *dev,
++	struct bss_parameters *params)
++{
++	s32 err = 0;
++	s32 ap_isolate = 0;
++#ifdef PCIE_FULL_DONGLE
++	s32 ifidx = DHD_BAD_IF;
++#endif
++#if defined(PCIE_FULL_DONGLE)
++	dhd_pub_t *dhd;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd = (dhd_pub_t *)(cfg->pub);
++#if defined(WL_ENABLE_P2P_IF)
++	if (cfg->p2p_net == dev)
++		dev = bcmcfg_to_prmry_ndev(cfg);
++#endif
++#endif 
++
++	if (params->use_cts_prot >= 0) {
++	}
++
++	if (params->use_short_preamble >= 0) {
++	}
++
++	if (params->use_short_slot_time >= 0) {
++	}
++
++	if (params->basic_rates) {
++	}
++
++	if (params->ap_isolate >= 0) {
++		ap_isolate = params->ap_isolate;
++#ifdef PCIE_FULL_DONGLE
++		ifidx = dhd_net2idx(dhd->info, dev);
++
++		if (ifidx != DHD_BAD_IF) {
++			err = dhd_set_ap_isolate(dhd, ifidx, ap_isolate);
++		} else {
++			WL_ERR(("Failed to set ap_isolate\n"));
++		}
++#else
++		err = wldev_iovar_setint(dev, "ap_isolate", ap_isolate);
++		if (unlikely(err))
++		{
++			WL_ERR(("set ap_isolate Error (%d)\n", err));
++		}
++#endif /* PCIE_FULL_DONGLE */
++	}
++
++	if (params->ht_opmode >= 0) {
++	}
++
++
++	return err;
++}
++
++static s32
++wl_cfg80211_set_channel(struct wiphy *wiphy, struct net_device *dev,
++	struct ieee80211_channel *chan,
++	enum nl80211_channel_type channel_type)
++{
++	s32 _chan;
++	chanspec_t chspec = 0;
++	chanspec_t fw_chspec = 0;
++	u32 bw = WL_CHANSPEC_BW_20;
++#ifdef WL11ULB
++	u32 ulb_bw = wl_cfg80211_get_ulb_bw(wl_get_cfg(dev), dev->ieee80211_ptr);
++#endif /* WL11ULB */
++
++	s32 err = BCME_OK;
++	s32 bw_cap = 0;
++	struct {
++		u32 band;
++		u32 bw_cap;
++	} param = {0, 0};
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++#if defined(CUSTOM_SET_CPUCORE) || (defined(WL_VIRTUAL_APSTA) && \
++	defined(APSTA_RESTRICTED_CHANNEL)) || defined(WL_EXT_IAPSTA)
++	dhd_pub_t *dhd =  (dhd_pub_t *)(cfg->pub);
++#endif /* CUSTOM_SET_CPUCORE || (WL_VIRTUAL_APSTA && APSTA_RESTRICTED_CHANNEL) */
++
++	dev = ndev_to_wlc_ndev(dev, cfg);
++	_chan = ieee80211_frequency_to_channel(chan->center_freq);
++#ifdef WL_EXT_IAPSTA
++	if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_AP) {
++		wl_ext_iapsta_update_iftype(dev, dhd_net2idx(dhd->info, dev), WLC_E_IF_ROLE_AP);
++		_chan = wl_ext_iapsta_update_channel(dhd, dev, _chan);
++	}
++#endif
++	WL_MSG(dev->name, "netdev_ifidx(%d), chan_type(%d) target channel(%d) \n",
++		dev->ifindex, channel_type, _chan);
++
++
++#if defined(WL_VIRTUAL_APSTA) && defined(APSTA_RESTRICTED_CHANNEL)
++#define DEFAULT_2G_SOFTAP_CHANNEL	1
++#define DEFAULT_5G_SOFTAP_CHANNEL	149
++	if (wl_get_mode_by_netdev(cfg, dev) == WL_MODE_AP &&
++		(dhd->op_mode & DHD_FLAG_CONCURR_STA_HOSTAP_MODE) ==
++		DHD_FLAG_CONCURR_STA_HOSTAP_MODE &&
++		wl_get_drv_status(cfg, CONNECTED, bcmcfg_to_prmry_ndev(cfg))) {
++		u32 *sta_chan = (u32 *)wl_read_prof(cfg,
++			bcmcfg_to_prmry_ndev(cfg), WL_PROF_CHAN);
++		u32 sta_band = (*sta_chan > CH_MAX_2G_CHANNEL) ?
++			IEEE80211_BAND_5GHZ : IEEE80211_BAND_2GHZ;
++		if (chan->band == sta_band) {
++			/* Do not try SCC in 5GHz if channel is not CH149 */
++			_chan = (sta_band == IEEE80211_BAND_5GHZ &&
++				*sta_chan != DEFAULT_5G_SOFTAP_CHANNEL) ?
++				DEFAULT_2G_SOFTAP_CHANNEL : *sta_chan;
++			WL_ERR(("target channel will be changed to %d\n", _chan));
++			if (_chan <= CH_MAX_2G_CHANNEL) {
++				bw = WL_CHANSPEC_BW_20;
++				goto set_channel;
++			}
++		}
++	}
++#undef DEFAULT_2G_SOFTAP_CHANNEL
++#undef DEFAULT_5G_SOFTAP_CHANNEL
++#endif /* WL_VIRTUAL_APSTA && APSTA_RESTRICTED_CHANNEL */
++
++#ifdef WL11ULB
++	if (ulb_bw) {
++		WL_DBG(("[ULB] setting AP/GO BW to ulb_bw 0x%x \n", ulb_bw));
++		bw = wl_cfg80211_ulbbw_to_ulbchspec(ulb_bw);
++		goto set_channel;
++	}
++#endif /* WL11ULB */
++	if (chan->band == IEEE80211_BAND_5GHZ) {
++		param.band = WLC_BAND_5G;
++		err = wldev_iovar_getbuf(dev, "bw_cap", &param, sizeof(param),
++			cfg->ioctl_buf, WLC_IOCTL_SMLEN, &cfg->ioctl_buf_sync);
++		if (err) {
++			if (err != BCME_UNSUPPORTED) {
++				WL_ERR(("bw_cap failed, %d\n", err));
++				return err;
++			} else {
++				err = wldev_iovar_getint(dev, "mimo_bw_cap", &bw_cap);
++				if (err) {
++					WL_ERR(("error get mimo_bw_cap (%d)\n", err));
++				}
++				if (bw_cap != WLC_N_BW_20ALL)
++					bw = WL_CHANSPEC_BW_40;
++			}
++		} else {
++			if (WL_BW_CAP_80MHZ(cfg->ioctl_buf[0]))
++				bw = WL_CHANSPEC_BW_80;
++			else if (WL_BW_CAP_40MHZ(cfg->ioctl_buf[0]))
++				bw = WL_CHANSPEC_BW_40;
++			else
++				bw = WL_CHANSPEC_BW_20;
++
++		}
++
++	} else if (chan->band == IEEE80211_BAND_2GHZ)
++		bw = WL_CHANSPEC_BW_20;
++set_channel:
++	chspec = wf_channel2chspec(_chan, bw);
++	if (wf_chspec_valid(chspec)) {
++		fw_chspec = wl_chspec_host_to_driver(chspec);
++		if (fw_chspec != INVCHANSPEC) {
++			if ((err = wldev_iovar_setint(dev, "chanspec",
++				fw_chspec)) == BCME_BADCHAN) {
++				if (bw == WL_CHANSPEC_BW_80)
++					goto change_bw;
++				err = wldev_ioctl_set(dev, WLC_SET_CHANNEL,
++					&_chan, sizeof(_chan));
++				if (err < 0) {
++					WL_ERR(("WLC_SET_CHANNEL error %d"
++					"chip may not be supporting this channel\n", err));
++				}
++			} else if (err) {
++				WL_ERR(("failed to set chanspec error %d\n", err));
++			}
++		} else {
++			WL_ERR(("failed to convert host chanspec to fw chanspec\n"));
++			err = BCME_ERROR;
++		}
++	} else {
++change_bw:
++		if (bw == WL_CHANSPEC_BW_80)
++			bw = WL_CHANSPEC_BW_40;
++		else if (bw == WL_CHANSPEC_BW_40)
++			bw = WL_CHANSPEC_BW_20;
++		else
++			bw = 0;
++		if (bw)
++			goto set_channel;
++		WL_ERR(("Invalid chanspec 0x%x\n", chspec));
++		err = BCME_ERROR;
++	}
++#ifdef CUSTOM_SET_CPUCORE
++	if (dhd->op_mode == DHD_FLAG_HOSTAP_MODE) {
++		WL_DBG(("SoftAP mode do not need to set cpucore\n"));
++	} else if (chspec & WL_CHANSPEC_BW_80) {
++		/* SoftAp only mode do not need to set cpucore */
++		if ((dev->ieee80211_ptr->iftype == NL80211_IFTYPE_AP) &&
++			dev != bcmcfg_to_prmry_ndev(cfg)) {
++			/* Soft AP on virtual Iface (AP+STA case) */
++			dhd->chan_isvht80 |= DHD_FLAG_HOSTAP_MODE;
++			dhd_set_cpucore(dhd, TRUE);
++		} else if (is_p2p_group_iface(dev->ieee80211_ptr)) {
++			/* If P2P IF is vht80 */
++			dhd->chan_isvht80 |= DHD_FLAG_P2P_MODE;
++			dhd_set_cpucore(dhd, TRUE);
++		}
++	}
++#endif /* CUSTOM_SET_CPUCORE */
++	if (!err && (wl_get_mode_by_netdev(cfg, dev) == WL_MODE_AP)) {
++		/* Update AP/GO operating channel */
++		cfg->ap_oper_channel = ieee80211_frequency_to_channel(chan->center_freq);
++	}
++	return err;
++}
++
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++struct net_device *
++wl_cfg80211_get_remain_on_channel_ndev(struct bcm_cfg80211 *cfg)
++{
++	struct net_info *_net_info, *next;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	list_for_each_entry_safe(_net_info, next, &cfg->net_list, list) {
++		if (_net_info->ndev &&
++			test_bit(WL_STATUS_REMAINING_ON_CHANNEL, &_net_info->sme_state))
++			return _net_info->ndev;
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	return NULL;
++}
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++
++static s32
++wl_validate_opensecurity(struct net_device *dev, s32 bssidx, bool privacy)
++{
++	s32 err = BCME_OK;
++	u32 wpa_val;
++	s32 wsec = 0;
++
++	/* set auth */
++	err = wldev_iovar_setint_bsscfg(dev, "auth", 0, bssidx);
++	if (err < 0) {
++		WL_ERR(("auth error %d\n", err));
++		return BCME_ERROR;
++	}
++
++	if (privacy) {
++		/* If privacy bit is set in open mode, then WEP would be enabled */
++		wsec = WEP_ENABLED;
++		WL_DBG(("Setting wsec to %d for WEP \n", wsec));
++	}
++
++	/* set wsec */
++	err = wldev_iovar_setint_bsscfg(dev, "wsec", wsec, bssidx);
++	if (err < 0) {
++		WL_ERR(("wsec error %d\n", err));
++		return BCME_ERROR;
++	}
++
++	/* set upper-layer auth */
++	if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_ADHOC)
++		wpa_val = WPA_AUTH_NONE;
++	else
++		wpa_val = WPA_AUTH_DISABLED;
++	err = wldev_iovar_setint_bsscfg(dev, "wpa_auth", wpa_val, bssidx);
++	if (err < 0) {
++		WL_ERR(("wpa_auth error %d\n", err));
++		return BCME_ERROR;
++	}
++
++	return 0;
++}
++
++static s32
++wl_validate_wpa2ie(struct net_device *dev, bcm_tlv_t *wpa2ie, s32 bssidx)
++{
++	s32 len = 0;
++	s32 err = BCME_OK;
++	u16 auth = 0; /* d11 open authentication */
++	u32 wsec;
++	u32 pval = 0;
++	u32 gval = 0;
++	u32 wpa_auth = 0;
++	wpa_suite_mcast_t *mcast;
++	wpa_suite_ucast_t *ucast;
++	wpa_suite_auth_key_mgmt_t *mgmt;
++	wpa_pmkid_list_t *pmkid;
++	int cnt = 0;
++#ifdef MFP
++	int mfp = 0;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++#endif /* MFP */
++
++	u16 suite_count;
++	u8 rsn_cap[2];
++	u32 wme_bss_disable;
++
++	if (wpa2ie == NULL)
++		goto exit;
++
++	WL_DBG(("Enter \n"));
++	len =  wpa2ie->len - WPA2_VERSION_LEN;
++	/* check the mcast cipher */
++	mcast = (wpa_suite_mcast_t *)&wpa2ie->data[WPA2_VERSION_LEN];
++	switch (mcast->type) {
++		case WPA_CIPHER_NONE:
++			gval = 0;
++			break;
++		case WPA_CIPHER_WEP_40:
++		case WPA_CIPHER_WEP_104:
++			gval = WEP_ENABLED;
++			break;
++		case WPA_CIPHER_TKIP:
++			gval = TKIP_ENABLED;
++			break;
++		case WPA_CIPHER_AES_CCM:
++			gval = AES_ENABLED;
++			break;
++#ifdef BCMWAPI_WPI
++		case WAPI_CIPHER_SMS4:
++			gval = SMS4_ENABLED;
++			break;
++#endif
++		default:
++			WL_ERR(("No Security Info\n"));
++			break;
++	}
++	if ((len -= WPA_SUITE_LEN) <= 0)
++		return BCME_BADLEN;
++
++	/* check the unicast cipher */
++	ucast = (wpa_suite_ucast_t *)&mcast[1];
++	suite_count = ltoh16_ua(&ucast->count);
++	switch (ucast->list[0].type) {
++		case WPA_CIPHER_NONE:
++			pval = 0;
++			break;
++		case WPA_CIPHER_WEP_40:
++		case WPA_CIPHER_WEP_104:
++			pval = WEP_ENABLED;
++			break;
++		case WPA_CIPHER_TKIP:
++			pval = TKIP_ENABLED;
++			break;
++		case WPA_CIPHER_AES_CCM:
++			pval = AES_ENABLED;
++			break;
++#ifdef BCMWAPI_WPI
++		case WAPI_CIPHER_SMS4:
++			pval = SMS4_ENABLED;
++			break;
++#endif
++		default:
++			WL_ERR(("No Security Info\n"));
++	}
++	if ((len -= (WPA_IE_SUITE_COUNT_LEN + (WPA_SUITE_LEN * suite_count))) <= 0)
++		return BCME_BADLEN;
++
++	/* FOR WPS , set SEC_OW_ENABLED */
++	wsec = (pval | gval | SES_OW_ENABLED);
++	/* check the AKM */
++	mgmt = (wpa_suite_auth_key_mgmt_t *)&ucast->list[suite_count];
++	suite_count = cnt = ltoh16_ua(&mgmt->count);
++	while (cnt--) {
++		switch (mgmt->list[cnt].type) {
++		case RSN_AKM_NONE:
++			wpa_auth |= WPA_AUTH_NONE;
++			break;
++		case RSN_AKM_UNSPECIFIED:
++			wpa_auth |= WPA2_AUTH_UNSPECIFIED;
++			break;
++		case RSN_AKM_PSK:
++			wpa_auth |= WPA2_AUTH_PSK;
++			break;
++#ifdef MFP
++		case RSN_AKM_MFP_PSK:
++			wpa_auth |= WPA2_AUTH_PSK_SHA256;
++			break;
++		case RSN_AKM_MFP_1X:
++			wpa_auth |= WPA2_AUTH_1X_SHA256;
++			break;
++#endif /* MFP */
++#ifdef WL_SAE
++		case RSN_AKM_SAE_PSK:
++		case RSN_AKM_SAE_FBT:
++			wpa_auth |= WPA3_AUTH_SAE_PSK;
++			break;
++#endif /* WL_SAE */
++		default:
++			WL_ERR(("No Key Mgmt Info\n"));
++		}
++	}
++
++	if ((len -= (WPA_IE_SUITE_COUNT_LEN + (WPA_SUITE_LEN * suite_count))) >= RSN_CAP_LEN) {
++		rsn_cap[0] = *(u8 *)&mgmt->list[suite_count];
++		rsn_cap[1] = *((u8 *)&mgmt->list[suite_count] + 1);
++
++		if (rsn_cap[0] & (RSN_CAP_16_REPLAY_CNTRS << RSN_CAP_PTK_REPLAY_CNTR_SHIFT)) {
++			wme_bss_disable = 0;
++		} else {
++			wme_bss_disable = 1;
++		}
++
++#ifdef MFP
++	if (rsn_cap[0] & RSN_CAP_MFPR) {
++		WL_DBG(("MFP Required \n"));
++		mfp = WL_MFP_REQUIRED;
++		/* Our firmware has requirement that WPA2_AUTH_PSK/WPA2_AUTH_UNSPECIFIED
++		 * be set, if SHA256 OUI is to be included in the rsn ie.
++		 */
++		if (wpa_auth & WPA2_AUTH_PSK_SHA256) {
++			wpa_auth |= WPA2_AUTH_PSK;
++		} else if (wpa_auth & WPA2_AUTH_1X_SHA256) {
++			wpa_auth |= WPA2_AUTH_UNSPECIFIED;
++		}
++	} else if (rsn_cap[0] & RSN_CAP_MFPC) {
++		WL_DBG(("MFP Capable \n"));
++		mfp = WL_MFP_CAPABLE;
++	}
++#endif /* MFP */
++
++		/* set wme_bss_disable to sync RSN Capabilities */
++		err = wldev_iovar_setint_bsscfg(dev, "wme_bss_disable", wme_bss_disable, bssidx);
++		if (err < 0) {
++			WL_ERR(("wme_bss_disable error %d\n", err));
++			return BCME_ERROR;
++		}
++	} else {
++		WL_DBG(("There is no RSN Capabilities. remained len %d\n", len));
++	}
++
++	len -= RSN_CAP_LEN;
++	if (len >= WPA2_PMKID_COUNT_LEN) {
++		pmkid = (wpa_pmkid_list_t *)((u8 *)&mgmt->list[suite_count] + RSN_CAP_LEN);
++		cnt = ltoh16_ua(&pmkid->count);
++		if (cnt != 0) {
++			WL_ERR(("AP has non-zero PMKID count. Wrong!\n"));
++			return BCME_ERROR;
++		}
++		/* since PMKID cnt is known to be 0 for AP, */
++		/* so don't bother to send down this info to firmware */
++	}
++
++#ifdef MFP
++	len -= WPA2_PMKID_COUNT_LEN;
++	if (len >= WPA_SUITE_LEN) {
++		cfg->bip_pos = (u8 *)&mgmt->list[suite_count] + RSN_CAP_LEN + WPA2_PMKID_COUNT_LEN;
++	} else {
++		cfg->bip_pos = NULL;
++	}
++#endif
++
++	/* set auth */
++	err = wldev_iovar_setint_bsscfg(dev, "auth", auth, bssidx);
++	if (err < 0) {
++		WL_ERR(("auth error %d\n", err));
++		return BCME_ERROR;
++	}
++
++	/* set wsec */
++	err = wldev_iovar_setint_bsscfg(dev, "wsec", wsec, bssidx);
++	if (err < 0) {
++		WL_ERR(("wsec error %d\n", err));
++		return BCME_ERROR;
++	}
++
++#ifdef MFP
++	cfg->mfp_mode = mfp;
++#endif /* MFP */
++
++	/* set upper-layer auth */
++	err = wldev_iovar_setint_bsscfg(dev, "wpa_auth", wpa_auth, bssidx);
++	if (err < 0) {
++		WL_ERR(("wpa_auth error %d\n", err));
++		return BCME_ERROR;
++	}
++exit:
++	return 0;
++}
++
++static s32
++wl_validate_wpaie(struct net_device *dev, wpa_ie_fixed_t *wpaie, s32 bssidx)
++{
++	wpa_suite_mcast_t *mcast;
++	wpa_suite_ucast_t *ucast;
++	wpa_suite_auth_key_mgmt_t *mgmt;
++	u16 auth = 0; /* d11 open authentication */
++	u16 count;
++	s32 err = BCME_OK;
++	s32 len = 0;
++	u32 i;
++	u32 wsec;
++	u32 pval = 0;
++	u32 gval = 0;
++	u32 wpa_auth = 0;
++	u32 tmp = 0;
++
++	if (wpaie == NULL)
++		goto exit;
++	WL_DBG(("Enter \n"));
++	len = wpaie->length;    /* value length */
++	len -= WPA_IE_TAG_FIXED_LEN;
++	/* check for multicast cipher suite */
++	if (len < WPA_SUITE_LEN) {
++		WL_INFORM(("no multicast cipher suite\n"));
++		goto exit;
++	}
++
++	/* pick up multicast cipher */
++	mcast = (wpa_suite_mcast_t *)&wpaie[1];
++	len -= WPA_SUITE_LEN;
++	if (!bcmp(mcast->oui, WPA_OUI, WPA_OUI_LEN)) {
++		if (IS_WPA_CIPHER(mcast->type)) {
++			tmp = 0;
++			switch (mcast->type) {
++				case WPA_CIPHER_NONE:
++					tmp = 0;
++					break;
++				case WPA_CIPHER_WEP_40:
++				case WPA_CIPHER_WEP_104:
++					tmp = WEP_ENABLED;
++					break;
++				case WPA_CIPHER_TKIP:
++					tmp = TKIP_ENABLED;
++					break;
++				case WPA_CIPHER_AES_CCM:
++					tmp = AES_ENABLED;
++					break;
++				default:
++					WL_ERR(("No Security Info\n"));
++			}
++			gval |= tmp;
++		}
++	}
++	/* Check for unicast suite(s) */
++	if (len < WPA_IE_SUITE_COUNT_LEN) {
++		WL_INFORM(("no unicast suite\n"));
++		goto exit;
++	}
++	/* walk thru unicast cipher list and pick up what we recognize */
++	ucast = (wpa_suite_ucast_t *)&mcast[1];
++	count = ltoh16_ua(&ucast->count);
++	len -= WPA_IE_SUITE_COUNT_LEN;
++	for (i = 0; i < count && len >= WPA_SUITE_LEN;
++		i++, len -= WPA_SUITE_LEN) {
++		if (!bcmp(ucast->list[i].oui, WPA_OUI, WPA_OUI_LEN)) {
++			if (IS_WPA_CIPHER(ucast->list[i].type)) {
++				tmp = 0;
++				switch (ucast->list[i].type) {
++					case WPA_CIPHER_NONE:
++						tmp = 0;
++						break;
++					case WPA_CIPHER_WEP_40:
++					case WPA_CIPHER_WEP_104:
++						tmp = WEP_ENABLED;
++						break;
++					case WPA_CIPHER_TKIP:
++						tmp = TKIP_ENABLED;
++						break;
++					case WPA_CIPHER_AES_CCM:
++						tmp = AES_ENABLED;
++						break;
++					default:
++						WL_ERR(("No Security Info\n"));
++				}
++				pval |= tmp;
++			}
++		}
++	}
++	len -= (count - i) * WPA_SUITE_LEN;
++	/* Check for auth key management suite(s) */
++	if (len < WPA_IE_SUITE_COUNT_LEN) {
++		WL_INFORM((" no auth key mgmt suite\n"));
++		goto exit;
++	}
++	/* walk thru auth management suite list and pick up what we recognize */
++	mgmt = (wpa_suite_auth_key_mgmt_t *)&ucast->list[count];
++	count = ltoh16_ua(&mgmt->count);
++	len -= WPA_IE_SUITE_COUNT_LEN;
++	for (i = 0; i < count && len >= WPA_SUITE_LEN;
++		i++, len -= WPA_SUITE_LEN) {
++		if (!bcmp(mgmt->list[i].oui, WPA_OUI, WPA_OUI_LEN)) {
++			if (IS_WPA_AKM(mgmt->list[i].type)) {
++				tmp = 0;
++				switch (mgmt->list[i].type) {
++					case RSN_AKM_NONE:
++						tmp = WPA_AUTH_NONE;
++						break;
++					case RSN_AKM_UNSPECIFIED:
++						tmp = WPA_AUTH_UNSPECIFIED;
++						break;
++					case RSN_AKM_PSK:
++						tmp = WPA_AUTH_PSK;
++						break;
++					default:
++						WL_ERR(("No Key Mgmt Info\n"));
++				}
++				wpa_auth |= tmp;
++			}
++		}
++
++	}
++	/* FOR WPS , set SEC_OW_ENABLED */
++	wsec = (pval | gval | SES_OW_ENABLED);
++	/* set auth */
++	err = wldev_iovar_setint_bsscfg(dev, "auth", auth, bssidx);
++	if (err < 0) {
++		WL_ERR(("auth error %d\n", err));
++		return BCME_ERROR;
++	}
++	/* set wsec */
++	err = wldev_iovar_setint_bsscfg(dev, "wsec", wsec, bssidx);
++	if (err < 0) {
++		WL_ERR(("wsec error %d\n", err));
++		return BCME_ERROR;
++	}
++	/* set upper-layer auth */
++	err = wldev_iovar_setint_bsscfg(dev, "wpa_auth", wpa_auth, bssidx);
++	if (err < 0) {
++		WL_ERR(("wpa_auth error %d\n", err));
++		return BCME_ERROR;
++	}
++exit:
++	return 0;
++}
++
++#if defined(SUPPORT_SOFTAP_WPAWPA2_MIXED)
++static u32 wl_get_cipher_type(uint8 type)
++{
++	u32 ret = 0;
++	switch (type) {
++		case WPA_CIPHER_NONE:
++			ret = 0;
++			break;
++		case WPA_CIPHER_WEP_40:
++		case WPA_CIPHER_WEP_104:
++			ret = WEP_ENABLED;
++			break;
++		case WPA_CIPHER_TKIP:
++			ret = TKIP_ENABLED;
++			break;
++		case WPA_CIPHER_AES_CCM:
++			ret = AES_ENABLED;
++			break;
++#ifdef BCMWAPI_WPI
++		case WAPI_CIPHER_SMS4:
++			ret = SMS4_ENABLED;
++			break;
++#endif
++		default:
++			WL_ERR(("No Security Info\n"));
++	}
++	return ret;
++}
++
++static u32 wl_get_suite_auth_key_mgmt_type(uint8 type)
++{
++	u32 ret = 0;
++	switch (type) {
++		case RSN_AKM_NONE:
++			ret = WPA_AUTH_NONE;
++			break;
++		case RSN_AKM_UNSPECIFIED:
++			ret = WPA_AUTH_UNSPECIFIED;
++			break;
++		case RSN_AKM_PSK:
++			ret = WPA_AUTH_PSK;
++			break;
++		default:
++			WL_ERR(("No Key Mgmt Info\n"));
++	}
++	return ret;
++}
++
++static u32 wl_get_suite_auth2_key_mgmt_type(uint8 type)
++{
++	u32 ret = 0;
++	switch (type) {
++		case RSN_AKM_NONE:
++			ret = WPA_AUTH_NONE;
++			break;
++		case RSN_AKM_UNSPECIFIED:
++			ret = WPA2_AUTH_UNSPECIFIED;
++			break;
++		case RSN_AKM_PSK:
++			ret = WPA2_AUTH_PSK;
++			break;
++		default:
++			WL_ERR(("No Key Mgmt Info\n"));
++	}
++	return ret;
++}
++
++static s32
++wl_validate_wpaie_wpa2ie(struct net_device *dev, wpa_ie_fixed_t *wpaie,
++	bcm_tlv_t *wpa2ie, s32 bssidx)
++{
++	wpa_suite_mcast_t *mcast;
++	wpa_suite_ucast_t *ucast;
++	wpa_suite_auth_key_mgmt_t *mgmt;
++	u16 auth = 0; /* d11 open authentication */
++	u16 count;
++	s32 err = BCME_OK;
++	u32 wme_bss_disable;
++	u16 suite_count;
++	u8 rsn_cap[2];
++	s32 len = 0;
++	u32 i;
++	u32 wsec1, wsec2, wsec;
++	u32 pval = 0;
++	u32 gval = 0;
++	u32 wpa_auth = 0;
++	u32 wpa_auth1 = 0;
++	u32 wpa_auth2 = 0;
++	u8* ptmp;
++
++	if (wpaie == NULL || wpa2ie == NULL)
++		goto exit;
++
++	WL_DBG(("Enter \n"));
++	len = wpaie->length;    /* value length */
++	len -= WPA_IE_TAG_FIXED_LEN;
++	/* check for multicast cipher suite */
++	if (len < WPA_SUITE_LEN) {
++		WL_INFORM(("no multicast cipher suite\n"));
++		goto exit;
++	}
++
++	/* pick up multicast cipher */
++	mcast = (wpa_suite_mcast_t *)&wpaie[1];
++	len -= WPA_SUITE_LEN;
++	if (!bcmp(mcast->oui, WPA_OUI, WPA_OUI_LEN)) {
++		if (IS_WPA_CIPHER(mcast->type)) {
++			gval |= wl_get_cipher_type(mcast->type);
++		}
++	}
++	WL_ERR(("\nwpa ie validate\n"));
++	WL_ERR(("wpa ie mcast cipher = 0x%X\n", gval));
++
++	/* Check for unicast suite(s) */
++	if (len < WPA_IE_SUITE_COUNT_LEN) {
++		WL_INFORM(("no unicast suite\n"));
++		goto exit;
++	}
++
++	/* walk thru unicast cipher list and pick up what we recognize */
++	ucast = (wpa_suite_ucast_t *)&mcast[1];
++	count = ltoh16_ua(&ucast->count);
++	len -= WPA_IE_SUITE_COUNT_LEN;
++	for (i = 0; i < count && len >= WPA_SUITE_LEN;
++		i++, len -= WPA_SUITE_LEN) {
++		if (!bcmp(ucast->list[i].oui, WPA_OUI, WPA_OUI_LEN)) {
++			if (IS_WPA_CIPHER(ucast->list[i].type)) {
++				pval |= wl_get_cipher_type(ucast->list[i].type);
++			}
++		}
++	}
++	WL_ERR(("wpa ie ucast count =%d, cipher = 0x%X\n", count, pval));
++
++	/* FOR WPS , set SEC_OW_ENABLED */
++	wsec1 = (pval | gval | SES_OW_ENABLED);
++	WL_ERR(("wpa ie wsec = 0x%X\n", wsec1));
++
++	len -= (count - i) * WPA_SUITE_LEN;
++	/* Check for auth key management suite(s) */
++	if (len < WPA_IE_SUITE_COUNT_LEN) {
++		WL_INFORM((" no auth key mgmt suite\n"));
++		goto exit;
++	}
++	/* walk thru auth management suite list and pick up what we recognize */
++	mgmt = (wpa_suite_auth_key_mgmt_t *)&ucast->list[count];
++	count = ltoh16_ua(&mgmt->count);
++	len -= WPA_IE_SUITE_COUNT_LEN;
++	for (i = 0; i < count && len >= WPA_SUITE_LEN;
++		i++, len -= WPA_SUITE_LEN) {
++		if (!bcmp(mgmt->list[i].oui, WPA_OUI, WPA_OUI_LEN)) {
++			if (IS_WPA_AKM(mgmt->list[i].type)) {
++
++				wpa_auth1 |= wl_get_suite_auth_key_mgmt_type(mgmt->list[i].type);
++			}
++		}
++
++	}
++	WL_ERR(("wpa ie wpa_suite_auth_key_mgmt count=%d, key_mgmt = 0x%X\n", count, wpa_auth1));
++	WL_ERR(("\nwpa2 ie validate\n"));
++
++	pval = 0;
++	gval = 0;
++	len =  wpa2ie->len;
++	/* check the mcast cipher */
++	mcast = (wpa_suite_mcast_t *)&wpa2ie->data[WPA2_VERSION_LEN];
++	ptmp = mcast->oui;
++	gval = wl_get_cipher_type(ptmp[DOT11_OUI_LEN]);
++
++	WL_ERR(("wpa2 ie mcast cipher = 0x%X\n", gval));
++	if ((len -= WPA_SUITE_LEN) <= 0)
++	{
++		WL_ERR(("P:wpa2 ie len[%d]", len));
++		return BCME_BADLEN;
++	}
++
++	/* check the unicast cipher */
++	ucast = (wpa_suite_ucast_t *)&mcast[1];
++	suite_count = ltoh16_ua(&ucast->count);
++	WL_ERR((" WPA2 ucast cipher count=%d\n", suite_count));
++	pval |= wl_get_cipher_type(ucast->list[0].type);
++
++	if ((len -= (WPA_IE_SUITE_COUNT_LEN + (WPA_SUITE_LEN * suite_count))) <= 0)
++		return BCME_BADLEN;
++
++	WL_ERR(("wpa2 ie ucast cipher = 0x%X\n", pval));
++
++	/* FOR WPS , set SEC_OW_ENABLED */
++	wsec2 = (pval | gval | SES_OW_ENABLED);
++	WL_ERR(("wpa2 ie wsec = 0x%X\n", wsec2));
++
++	/* check the AKM */
++	mgmt = (wpa_suite_auth_key_mgmt_t *)&ucast->list[suite_count];
++	suite_count = ltoh16_ua(&mgmt->count);
++	ptmp = (u8 *)&mgmt->list[0];
++	wpa_auth2 = wl_get_suite_auth2_key_mgmt_type(ptmp[DOT11_OUI_LEN]);
++	WL_ERR(("wpa ie wpa_suite_auth_key_mgmt count=%d, key_mgmt = 0x%X\n", count, wpa_auth2));
++
++	if ((len -= (WPA_IE_SUITE_COUNT_LEN + (WPA_SUITE_LEN * suite_count))) >= RSN_CAP_LEN) {
++		rsn_cap[0] = *(u8 *)&mgmt->list[suite_count];
++		rsn_cap[1] = *((u8 *)&mgmt->list[suite_count] + 1);
++		if (rsn_cap[0] & (RSN_CAP_16_REPLAY_CNTRS << RSN_CAP_PTK_REPLAY_CNTR_SHIFT)) {
++			wme_bss_disable = 0;
++		} else {
++			wme_bss_disable = 1;
++		}
++		WL_DBG(("P:rsn_cap[0]=[0x%X]:wme_bss_disabled[%d]\n", rsn_cap[0], wme_bss_disable));
++
++		/* set wme_bss_disable to sync RSN Capabilities */
++		err = wldev_iovar_setint_bsscfg(dev, "wme_bss_disable", wme_bss_disable, bssidx);
++		if (err < 0) {
++			WL_ERR(("wme_bss_disable error %d\n", err));
++			return BCME_ERROR;
++		}
++	} else {
++		WL_DBG(("There is no RSN Capabilities. remained len %d\n", len));
++	}
++
++	wsec = (wsec1 | wsec2);
++	wpa_auth = (wpa_auth1 | wpa_auth2);
++	WL_ERR(("wpa_wpa2 wsec=0x%X wpa_auth=0x%X\n", wsec, wpa_auth));
++
++	/* set auth */
++	err = wldev_iovar_setint_bsscfg(dev, "auth", auth, bssidx);
++	if (err < 0) {
++		WL_ERR(("auth error %d\n", err));
++		return BCME_ERROR;
++	}
++	/* set wsec */
++	err = wldev_iovar_setint_bsscfg(dev, "wsec", wsec, bssidx);
++	if (err < 0) {
++		WL_ERR(("wsec error %d\n", err));
++		return BCME_ERROR;
++	}
++	/* set upper-layer auth */
++	err = wldev_iovar_setint_bsscfg(dev, "wpa_auth", wpa_auth, bssidx);
++	if (err < 0) {
++		WL_ERR(("wpa_auth error %d\n", err));
++		return BCME_ERROR;
++	}
++exit:
++	return 0;
++}
++#endif /* SUPPORT_SOFTAP_WPAWPA2_MIXED */
++
++static s32
++wl_cfg80211_bcn_validate_sec(
++	struct net_device *dev,
++	struct parsed_ies *ies,
++	u32 dev_role,
++	s32 bssidx,
++	bool privacy)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	wl_cfgbss_t *bss = wl_get_cfgbss_by_wdev(cfg, dev->ieee80211_ptr);
++
++	if (!bss) {
++		WL_ERR(("cfgbss is NULL \n"));
++		return BCME_ERROR;
++	}
++
++	if (dev_role == NL80211_IFTYPE_P2P_GO && (ies->wpa2_ie)) {
++		/* For P2P GO, the sec type is WPA2-PSK */
++		WL_DBG(("P2P GO: validating wpa2_ie"));
++		if (wl_validate_wpa2ie(dev, ies->wpa2_ie, bssidx)  < 0)
++			return BCME_ERROR;
++
++	} else if (dev_role == NL80211_IFTYPE_AP) {
++
++		WL_DBG(("SoftAP: validating security"));
++		/* If wpa2_ie or wpa_ie is present validate it */
++
++#if defined(SUPPORT_SOFTAP_WPAWPA2_MIXED)
++		if ((ies->wpa_ie != NULL && ies->wpa2_ie != NULL)) {
++			if (wl_validate_wpaie_wpa2ie(dev, ies->wpa_ie, ies->wpa2_ie, bssidx)  < 0) {
++				bss->security_mode = false;
++				return BCME_ERROR;
++			}
++		}
++		else {
++#endif /* SUPPORT_SOFTAP_WPAWPA2_MIXED */
++		if ((ies->wpa2_ie || ies->wpa_ie) &&
++			((wl_validate_wpa2ie(dev, ies->wpa2_ie, bssidx)  < 0 ||
++			wl_validate_wpaie(dev, ies->wpa_ie, bssidx) < 0))) {
++			bss->security_mode = false;
++			return BCME_ERROR;
++		}
++
++		bss->security_mode = true;
++		if (bss->rsn_ie) {
++			kfree(bss->rsn_ie);
++			bss->rsn_ie = NULL;
++		}
++		if (bss->wpa_ie) {
++			kfree(bss->wpa_ie);
++			bss->wpa_ie = NULL;
++		}
++		if (bss->wps_ie) {
++			kfree(bss->wps_ie);
++			bss->wps_ie = NULL;
++		}
++		if (ies->wpa_ie != NULL) {
++			/* WPAIE */
++			bss->rsn_ie = NULL;
++			bss->wpa_ie = kmemdup(ies->wpa_ie,
++				ies->wpa_ie->length + WPA_RSN_IE_TAG_FIXED_LEN,
++				GFP_KERNEL);
++		} else if (ies->wpa2_ie != NULL) {
++			/* RSNIE */
++			bss->wpa_ie = NULL;
++			bss->rsn_ie = kmemdup(ies->wpa2_ie,
++				ies->wpa2_ie->len + WPA_RSN_IE_TAG_FIXED_LEN,
++				GFP_KERNEL);
++		}
++#if defined(SUPPORT_SOFTAP_WPAWPA2_MIXED)
++		}
++#endif /* SUPPORT_SOFTAP_WPAWPA2_MIXED */
++		if (!ies->wpa2_ie && !ies->wpa_ie) {
++			wl_validate_opensecurity(dev, bssidx, privacy);
++			bss->security_mode = false;
++		}
++
++		if (ies->wps_ie) {
++			bss->wps_ie = kmemdup(ies->wps_ie, ies->wps_ie_len, GFP_KERNEL);
++		}
++	}
++
++	return 0;
++
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
++static s32 wl_cfg80211_bcn_set_params(
++	struct cfg80211_ap_settings *info,
++	struct net_device *dev,
++	u32 dev_role, s32 bssidx)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	s32 err = BCME_OK;
++
++	WL_DBG(("interval (%d) \ndtim_period (%d) \n",
++		info->beacon_interval, info->dtim_period));
++
++	if (info->beacon_interval) {
++		if ((err = wldev_ioctl_set(dev, WLC_SET_BCNPRD,
++			&info->beacon_interval, sizeof(s32))) < 0) {
++			WL_ERR(("Beacon Interval Set Error, %d\n", err));
++			return err;
++		}
++	}
++
++	if (info->dtim_period) {
++		if ((err = wldev_ioctl_set(dev, WLC_SET_DTIMPRD,
++			&info->dtim_period, sizeof(s32))) < 0) {
++			WL_ERR(("DTIM Interval Set Error, %d\n", err));
++			return err;
++		}
++	}
++
++	if ((info->ssid) && (info->ssid_len > 0) &&
++		(info->ssid_len <= DOT11_MAX_SSID_LEN)) {
++		WL_DBG(("SSID (%s) len:%zd \n", info->ssid, info->ssid_len));
++		if (dev_role == NL80211_IFTYPE_AP) {
++			/* Store the hostapd SSID */
++			memset(cfg->hostapd_ssid.SSID, 0x00, DOT11_MAX_SSID_LEN);
++			memcpy(cfg->hostapd_ssid.SSID, info->ssid, info->ssid_len);
++			cfg->hostapd_ssid.SSID_len = info->ssid_len;
++		} else {
++				/* P2P GO */
++			memset(cfg->p2p->ssid.SSID, 0x00, DOT11_MAX_SSID_LEN);
++			memcpy(cfg->p2p->ssid.SSID, info->ssid, info->ssid_len);
++			cfg->p2p->ssid.SSID_len = info->ssid_len;
++		}
++	}
++
++	if (info->hidden_ssid != NL80211_HIDDEN_SSID_NOT_IN_USE) {
++		if ((err = wldev_iovar_setint(dev, "closednet", 1)) < 0)
++			WL_ERR(("failed to set hidden : %d\n", err));
++		WL_DBG(("hidden_ssid_enum_val: %d \n", info->hidden_ssid));
++	}
++
++	return err;
++}
++#endif 
++
++static s32
++wl_cfg80211_parse_ies(u8 *ptr, u32 len, struct parsed_ies *ies)
++{
++	s32 err = BCME_OK;
++
++	memset(ies, 0, sizeof(struct parsed_ies));
++
++	/* find the WPSIE */
++	if ((ies->wps_ie = wl_cfgp2p_find_wpsie(ptr, len)) != NULL) {
++		WL_DBG(("WPSIE in beacon \n"));
++		ies->wps_ie_len = ies->wps_ie->length + WPA_RSN_IE_TAG_FIXED_LEN;
++	} else {
++		WL_DBG(("No WPSIE in beacon \n"));
++	}
++
++	/* find the RSN_IE */
++	if ((ies->wpa2_ie = bcm_parse_tlvs(ptr, len,
++		DOT11_MNG_RSN_ID)) != NULL) {
++		WL_DBG((" WPA2 IE found\n"));
++		ies->wpa2_ie_len = ies->wpa2_ie->len;
++	}
++
++	/* find the WPA_IE */
++	if ((ies->wpa_ie = wl_cfgp2p_find_wpaie(ptr, len)) != NULL) {
++		WL_DBG((" WPA found\n"));
++		ies->wpa_ie_len = ies->wpa_ie->length;
++	}
++
++	return err;
++
++}
++static s32
++wl_cfg80211_set_ap_role(
++	struct bcm_cfg80211 *cfg,
++	struct net_device *dev)
++{
++	s32 err = BCME_OK;
++	s32 infra = 1;
++	s32 ap = 1;
++	s32 pm;
++	s32 is_rsdb_supported = BCME_ERROR;
++	s32 bssidx;
++	s32 apsta = 0;
++
++	is_rsdb_supported = DHD_OPMODE_SUPPORTED(cfg->pub, DHD_FLAG_RSDB_MODE);
++	if (is_rsdb_supported < 0)
++		return (-ENODEV);
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return -EINVAL;
++	}
++
++	/* AP on primary Interface */
++	if (bssidx == 0) {
++		if (is_rsdb_supported) {
++			if ((err = wl_cfg80211_add_del_bss(cfg, dev, bssidx,
++				NL80211_IFTYPE_AP, 0, NULL)) < 0) {
++				WL_ERR(("wl add_del_bss returned error:%d\n", err));
++				return err;
++			}
++		} else if (is_rsdb_supported == 0) {
++			/* AP mode switch not supported. Try setting up AP explicitly */
++			err = wldev_iovar_getint(dev, "apsta", (s32 *)&apsta);
++			if (unlikely(err)) {
++				WL_ERR(("Could not get apsta %d\n", err));
++			}
++			if (1) { // terence: fix me
++				/* If apsta is not set, set it */
++				err = wldev_ioctl_set(dev, WLC_DOWN, &ap, sizeof(s32));
++				if (err < 0) {
++					WL_ERR(("WLC_DOWN error %d\n", err));
++					return err;
++				}
++				err = wldev_iovar_setint(dev, "apsta", 0);
++				if (err < 0) {
++					WL_ERR(("wl apsta 0 error %d\n", err));
++					return err;
++				}
++				if ((err = wldev_ioctl_set(dev,
++					WLC_SET_AP, &ap, sizeof(s32))) < 0) {
++					WL_ERR(("setting AP mode failed %d \n", err));
++					return err;
++				}
++			}
++		}
++
++		pm = 0;
++		if ((err = wldev_ioctl_set(dev, WLC_SET_PM, &pm, sizeof(pm))) != 0) {
++			WL_ERR(("wl PM 0 returned error:%d\n", err));
++			/* Ignore error, if any */
++			err = BCME_OK;
++		}
++		err = wldev_ioctl_set(dev, WLC_SET_INFRA, &infra, sizeof(s32));
++		if (err < 0) {
++			WL_ERR(("SET INFRA error %d\n", err));
++			return err;
++		}
++	} else {
++		WL_DBG(("Bringup SoftAP on virtual Interface bssidx:%d \n", bssidx));
++		if ((err = wl_cfg80211_add_del_bss(cfg, dev,
++			bssidx, NL80211_IFTYPE_AP, 0, NULL)) < 0) {
++			WL_ERR(("wl bss ap returned error:%d\n", err));
++			return err;
++		}
++	}
++
++	/* On success, mark AP creation in progress. */
++	wl_set_drv_status(cfg, AP_CREATING, dev);
++	return 0;
++}
++
++
++/* In RSDB downgrade cases, the link up event can get delayed upto 7-8 secs */
++#define MAX_AP_LINK_WAIT_TIME   10000
++static s32
++wl_cfg80211_bcn_bringup_ap(
++	struct net_device *dev,
++	struct parsed_ies *ies,
++	u32 dev_role, s32 bssidx)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	struct wl_join_params join_params;
++	bool is_bssup = false;
++	s32 infra = 1;
++	s32 join_params_size = 0;
++	s32 ap = 1;
++	s32 wsec;
++#ifdef WLMESH_CFG80211
++	bool retried = false;
++#endif
++#ifdef SOFTAP_UAPSD_OFF
++	uint32 wme_apsd = 0;
++#endif /* SOFTAP_UAPSD_OFF */
++	s32 err = BCME_OK;
++	s32 is_rsdb_supported = BCME_ERROR;
++	u32 timeout;
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++	char sec[32];
++
++	is_rsdb_supported = DHD_OPMODE_SUPPORTED(cfg->pub, DHD_FLAG_RSDB_MODE);
++	if (is_rsdb_supported < 0)
++		return (-ENODEV);
++
++	WL_DBG(("Enter dev_role:%d bssidx:%d ifname:%s\n", dev_role, bssidx, dev->name));
++
++	/* Common code for SoftAP and P2P GO */
++	wl_clr_drv_status(cfg, AP_CREATED, dev);
++
++	/* Make sure INFRA is set for AP/GO */
++	err = wldev_ioctl_set(dev, WLC_SET_INFRA, &infra, sizeof(s32));
++	if (err < 0) {
++		WL_ERR(("SET INFRA error %d\n", err));
++		goto exit;
++	}
++
++	/* Do abort scan before creating GO */
++	wl_cfg80211_scan_abort(cfg);
++
++	if (dev_role == NL80211_IFTYPE_P2P_GO) {
++		wl_ext_get_sec(dev, 0, sec, sizeof(sec));
++		WL_MSG(dev->name, "Creating GO with sec=%s\n", sec);
++		is_bssup = wl_cfg80211_bss_isup(dev, bssidx);
++		if (!is_bssup && (ies->wpa2_ie != NULL)) {
++
++			err = wldev_iovar_setbuf_bsscfg(dev, "ssid", &cfg->p2p->ssid,
++				sizeof(cfg->p2p->ssid), cfg->ioctl_buf, WLC_IOCTL_MAXLEN,
++				bssidx, &cfg->ioctl_buf_sync);
++			if (err < 0) {
++				WL_ERR(("GO SSID setting error %d\n", err));
++				goto exit;
++			}
++
++			if ((err = wl_cfg80211_bss_up(cfg, dev, bssidx, 1)) < 0) {
++				WL_ERR(("GO Bring up error %d\n", err));
++				goto exit;
++			}
++		} else
++			WL_DBG(("Bss is already up\n"));
++	} else if (dev_role == NL80211_IFTYPE_AP) {
++
++//		if (!wl_get_drv_status(cfg, AP_CREATING, dev)) {
++			/* Make sure fw is in proper state */
++			err = wl_cfg80211_set_ap_role(cfg, dev);
++			if (unlikely(err)) {
++				WL_ERR(("set ap role failed!\n"));
++				goto exit;
++			}
++//		}
++
++		/* Device role SoftAP */
++		WL_DBG(("Creating AP bssidx:%d dev_role:%d\n", bssidx, dev_role));
++		/* Clear the status bit after use */
++		wl_clr_drv_status(cfg, AP_CREATING, dev);
++
++
++#ifdef SOFTAP_UAPSD_OFF
++		err = wldev_iovar_setbuf_bsscfg(dev, "wme_apsd", &wme_apsd, sizeof(wme_apsd),
++			cfg->ioctl_buf, WLC_IOCTL_SMLEN, bssidx, &cfg->ioctl_buf_sync);
++		if (err < 0) {
++			WL_ERR(("failed to disable uapsd, error=%d\n", err));
++		}
++#endif /* SOFTAP_UAPSD_OFF */
++
++		err = wldev_ioctl_set(dev, WLC_UP, &ap, sizeof(s32));
++		if (unlikely(err)) {
++			WL_ERR(("WLC_UP error (%d)\n", err));
++			goto exit;
++		}
++
++#ifdef MFP
++		if (cfg->bip_pos) {
++			err = wldev_iovar_setbuf_bsscfg(dev, "bip",
++				(void *)(cfg->bip_pos), WPA_SUITE_LEN, cfg->ioctl_buf,
++				WLC_IOCTL_SMLEN, bssidx, &cfg->ioctl_buf_sync);
++			if (err < 0) {
++				WL_ERR(("bip set error %d\n", err));
++				if (wl_customer6_legacy_chip_check(cfg,
++					bcmcfg_to_prmry_ndev(cfg))) {
++					/* Ignore bip error: Some older firmwares doesn't
++					 * support bip iovar/ return BCME_NOTUP while trying
++					 * to set bip from AP bring up context. These firmares
++					 * include bip in RSNIE by default. So its okay to ignore
++					 * the error.
++					 */
++					err = BCME_OK;
++				} else {
++					goto exit;
++				}
++			}
++		}
++#endif /* MFP */
++
++		err = wldev_iovar_getint(dev, "wsec", (s32 *)&wsec);
++		if (unlikely(err)) {
++			WL_ERR(("Could not get wsec %d\n", err));
++			goto exit;
++		}
++		if (dhdp->conf->chip == BCM43430_CHIP_ID && bssidx > 0 &&
++				(wsec & (TKIP_ENABLED|AES_ENABLED))) {
++			wsec |= WSEC_SWFLAG; // terence 20180628: fix me, this is a workaround
++			err = wldev_iovar_setint_bsscfg(dev, "wsec", wsec, bssidx);
++			if (err < 0) {
++				WL_ERR(("wsec error %d\n", err));
++				goto exit;
++			}
++		}
++		if ((wsec == WEP_ENABLED) && cfg->wep_key.len) {
++			WL_DBG(("Applying buffered WEP KEY \n"));
++			err = wldev_iovar_setbuf_bsscfg(dev, "wsec_key", &cfg->wep_key,
++				sizeof(struct wl_wsec_key), cfg->ioctl_buf,
++				WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++			/* clear the key after use */
++			memset(&cfg->wep_key, 0, sizeof(struct wl_wsec_key));
++			if (unlikely(err)) {
++				WL_ERR(("WLC_SET_KEY error (%d)\n", err));
++				goto exit;
++			}
++		}
++
++#ifdef MFP
++		if (cfg->mfp_mode) {
++			/* This needs to go after wsec otherwise the wsec command will
++			 * overwrite the values set by MFP
++			 */
++			err = wldev_iovar_setint_bsscfg(dev, "mfp", cfg->mfp_mode, bssidx);
++			if (err < 0) {
++				WL_ERR(("MFP Setting failed. ret = %d \n", err));
++				/* If fw doesn't support mfp, Ignore the error */
++				if (err != BCME_UNSUPPORTED) {
++					goto exit;
++				}
++			}
++		}
++#endif /* MFP */
++
++#ifdef WLMESH_CFG80211
++ssid_retry:
++#endif
++		memset(&join_params, 0, sizeof(join_params));
++		/* join parameters starts with ssid */
++		join_params_size = sizeof(join_params.ssid);
++		join_params.ssid.SSID_len = MIN(cfg->hostapd_ssid.SSID_len,
++			(uint32)DOT11_MAX_SSID_LEN);
++		memcpy(join_params.ssid.SSID, cfg->hostapd_ssid.SSID,
++			join_params.ssid.SSID_len);
++		join_params.ssid.SSID_len = htod32(join_params.ssid.SSID_len);
++
++		wl_ext_get_sec(dev, 0, sec, sizeof(sec));
++		WL_MSG(dev->name, "Creating AP with sec=%s\n", sec);
++		/* create softap */
++		if ((err = wldev_ioctl_set(dev, WLC_SET_SSID, &join_params,
++			join_params_size)) != 0) {
++			WL_ERR(("SoftAP/GO set ssid failed! %d\n", err));
++			goto exit;
++		} else {
++			WL_DBG((" SoftAP SSID \"%s\" \n", join_params.ssid.SSID));
++		}
++
++		if (bssidx != 0) {
++			/* AP on Virtual Interface */
++			if ((err = wl_cfg80211_bss_up(cfg, dev, bssidx, 1)) < 0) {
++				WL_ERR(("AP Bring up error %d\n", err));
++				goto exit;
++			}
++		}
++
++	}
++
++	/* Wait for Linkup event to mark successful AP/GO bring up */
++	timeout = wait_event_interruptible_timeout(cfg->netif_change_event,
++		wl_get_drv_status(cfg, AP_CREATED, dev), msecs_to_jiffies(MAX_AP_LINK_WAIT_TIME));
++	if (timeout <= 0 || !wl_get_drv_status(cfg, AP_CREATED, dev)) {
++#ifdef WLMESH_CFG80211
++		if (!retried) {
++			retried = true;
++			WL_ERR(("Link up didn't come for AP interface. Try to set ssid again to recover it! \n"));
++			goto ssid_retry;
++		}
++#endif
++		WL_ERR(("Link up didn't come for AP interface. AP/GO creation failed! \n"));
++		if (timeout == -ERESTARTSYS) {
++			WL_ERR(("waitqueue was interrupted by a signal, returns -ERESTARTSYS\n"));
++			err = -ERESTARTSYS;
++			goto exit;
++		}
++#if defined(DHD_DEBUG) && defined(DHD_FW_COREDUMP)
++		if (dhdp->memdump_enabled) {
++			dhdp->memdump_type = DUMP_TYPE_AP_LINKUP_FAILURE;
++			dhd_bus_mem_dump(dhdp);
++		}
++#endif /* DHD_DEBUG && DHD_FW_COREDUMP */
++		err = -ENODEV;
++		goto exit;
++	}
++
++exit:
++	if (cfg->wep_key.len) {
++		memset(&cfg->wep_key, 0, sizeof(struct wl_wsec_key));
++	}
++
++#ifdef MFP
++	if (cfg->mfp_mode) {
++		cfg->mfp_mode = 0;
++	}
++
++	if (cfg->bip_pos) {
++		cfg->bip_pos = NULL;
++	}
++#endif /* MFP */
++
++	return err;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
++s32
++wl_cfg80211_parse_ap_ies(
++	struct net_device *dev,
++	struct cfg80211_beacon_data *info,
++	struct parsed_ies *ies)
++{
++	struct parsed_ies prb_ies;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++	const u8 *vndr = NULL;
++	u32 vndr_ie_len = 0;
++	s32 err = BCME_OK;
++
++	/* Parse Beacon IEs */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	if (wl_cfg80211_parse_ies((u8 *)info->tail,
++		info->tail_len, ies) < 0) {
++		WL_ERR(("Beacon get IEs failed \n"));
++		err = -EINVAL;
++		goto fail;
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	vndr = (const u8 *)info->proberesp_ies;
++	vndr_ie_len = info->proberesp_ies_len;
++
++	if (dhd->op_mode & DHD_FLAG_HOSTAP_MODE) {
++		/* SoftAP mode */
++		const struct ieee80211_mgmt *mgmt;
++		mgmt = (const struct ieee80211_mgmt *)info->probe_resp;
++		if (mgmt != NULL) {
++			vndr = (const u8 *)&mgmt->u.probe_resp.variable;
++			vndr_ie_len = info->probe_resp_len -
++				offsetof(const struct ieee80211_mgmt, u.probe_resp.variable);
++		}
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	/* Parse Probe Response IEs */
++	if (wl_cfg80211_parse_ies((u8 *)vndr, vndr_ie_len, &prb_ies) < 0) {
++		WL_ERR(("PROBE RESP get IEs failed \n"));
++		err = -EINVAL;
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++fail:
++
++	return err;
++}
++
++s32
++wl_cfg80211_set_ies(
++	struct net_device *dev,
++	struct cfg80211_beacon_data *info,
++	s32 bssidx)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++	const u8 *vndr = NULL;
++	u32 vndr_ie_len = 0;
++	s32 err = BCME_OK;
++
++	/* Set Beacon IEs to FW */
++	if ((err = wl_cfg80211_set_mgmt_vndr_ies(cfg, ndev_to_cfgdev(dev), bssidx,
++		VNDR_IE_BEACON_FLAG, (const u8 *)info->tail,
++		info->tail_len)) < 0) {
++		WL_ERR(("Set Beacon IE Failed \n"));
++	} else {
++		WL_DBG(("Applied Vndr IEs for Beacon \n"));
++	}
++
++	vndr = (const u8 *)info->proberesp_ies;
++	vndr_ie_len = info->proberesp_ies_len;
++
++	if (dhd->op_mode & DHD_FLAG_HOSTAP_MODE) {
++		/* SoftAP mode */
++		const struct ieee80211_mgmt *mgmt;
++		mgmt = (const struct ieee80211_mgmt *)info->probe_resp;
++		if (mgmt != NULL) {
++			vndr = (const u8 *)&mgmt->u.probe_resp.variable;
++			vndr_ie_len = info->probe_resp_len -
++				offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
++		}
++	}
++
++	/* Set Probe Response IEs to FW */
++	if ((err = wl_cfg80211_set_mgmt_vndr_ies(cfg, ndev_to_cfgdev(dev), bssidx,
++		VNDR_IE_PRBRSP_FLAG, vndr, vndr_ie_len)) < 0) {
++		WL_ERR(("Set Probe Resp IE Failed \n"));
++	} else {
++		WL_DBG(("Applied Vndr IEs for Probe Resp \n"));
++	}
++
++	return err;
++}
++#endif 
++
++static s32 wl_cfg80211_hostapd_sec(
++	struct net_device *dev,
++	struct parsed_ies *ies,
++	s32 bssidx)
++{
++	bool update_bss = 0;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	wl_cfgbss_t *bss = wl_get_cfgbss_by_wdev(cfg, dev->ieee80211_ptr);
++
++	if (!bss) {
++		WL_ERR(("cfgbss is NULL \n"));
++		return -EINVAL;
++	}
++
++	if (ies->wps_ie) {
++		if (bss->wps_ie &&
++			memcmp(bss->wps_ie, ies->wps_ie, ies->wps_ie_len)) {
++			WL_DBG((" WPS IE is changed\n"));
++			kfree(bss->wps_ie);
++			bss->wps_ie = kmemdup(ies->wps_ie, ies->wps_ie_len, GFP_KERNEL);
++		} else if (bss->wps_ie == NULL) {
++			WL_DBG((" WPS IE is added\n"));
++			bss->wps_ie = kmemdup(ies->wps_ie, ies->wps_ie_len, GFP_KERNEL);
++		}
++
++		if ((ies->wpa_ie != NULL || ies->wpa2_ie != NULL)) {
++			if (!bss->security_mode) {
++				/* change from open mode to security mode */
++				update_bss = true;
++				if (ies->wpa_ie != NULL) {
++					bss->wpa_ie = kmemdup(ies->wpa_ie,
++					ies->wpa_ie->length + WPA_RSN_IE_TAG_FIXED_LEN,
++					GFP_KERNEL);
++				} else {
++					bss->rsn_ie = kmemdup(ies->wpa2_ie,
++					ies->wpa2_ie->len + WPA_RSN_IE_TAG_FIXED_LEN,
++					GFP_KERNEL);
++				}
++			} else if (bss->wpa_ie) {
++				/* change from WPA2 mode to WPA mode */
++				if (ies->wpa_ie != NULL) {
++					update_bss = true;
++					kfree(bss->rsn_ie);
++					bss->rsn_ie = NULL;
++					bss->wpa_ie = kmemdup(ies->wpa_ie,
++					ies->wpa_ie->length + WPA_RSN_IE_TAG_FIXED_LEN,
++					GFP_KERNEL);
++				} else if (memcmp(bss->rsn_ie,
++					ies->wpa2_ie, ies->wpa2_ie->len
++					+ WPA_RSN_IE_TAG_FIXED_LEN)) {
++					update_bss = true;
++					kfree(bss->rsn_ie);
++					bss->rsn_ie = kmemdup(ies->wpa2_ie,
++					ies->wpa2_ie->len + WPA_RSN_IE_TAG_FIXED_LEN,
++					GFP_KERNEL);
++					bss->wpa_ie = NULL;
++				}
++			}
++			if (update_bss) {
++				bss->security_mode = true;
++				wl_cfg80211_bss_up(cfg, dev, bssidx, 0);
++				if (wl_validate_wpa2ie(dev, ies->wpa2_ie, bssidx)  < 0 ||
++					wl_validate_wpaie(dev, ies->wpa_ie, bssidx) < 0) {
++					return BCME_ERROR;
++				}
++				wl_cfg80211_bss_up(cfg, dev, bssidx, 1);
++			}
++		}
++	} else {
++		WL_ERR(("No WPSIE in beacon \n"));
++	}
++	return 0;
++}
++
++#if defined(WL_SUPPORT_BACKPORTED_KPATCHES) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, \
++	2, 0))
++static s32
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++wl_cfg80211_del_station(
++		struct wiphy *wiphy, struct net_device *ndev,
++		struct station_del_parameters *params)
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++wl_cfg80211_del_station(
++	struct wiphy *wiphy,
++	struct net_device *ndev,
++	const u8* mac_addr)
++#else
++wl_cfg80211_del_station(
++	struct wiphy *wiphy,
++	struct net_device *ndev,
++	u8* mac_addr)
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) */
++{
++	struct net_device *dev;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	scb_val_t scb_val;
++	s8 eabuf[ETHER_ADDR_STR_LEN];
++	int err;
++	char mac_buf[MAX_NUM_OF_ASSOCIATED_DEV *
++		sizeof(struct ether_addr) + sizeof(uint)] = {0};
++	struct maclist *assoc_maclist = (struct maclist *)mac_buf;
++	int num_associated = 0;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++	const u8 *mac_addr = params->mac;
++#ifdef CUSTOM_BLOCK_DEAUTH_AT_EAP_FAILURE
++	u16 rc = params->reason_code;
++#endif /* CUSTOM_BLOCK_DEAUTH_AT_EAP_FAILURE */
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) */
++
++	WL_DBG(("Entry\n"));
++	if (mac_addr == NULL) {
++		WL_DBG(("mac_addr is NULL ignore it\n"));
++		return 0;
++	}
++
++	dev = ndev_to_wlc_ndev(ndev, cfg);
++
++	if (p2p_is_on(cfg)) {
++		/* Suspend P2P discovery search-listen to prevent it from changing the
++		 * channel.
++		 */
++		if ((wl_cfgp2p_discover_enable_search(cfg, false)) < 0) {
++			WL_ERR(("Can not disable discovery mode\n"));
++			return -EFAULT;
++		}
++	}
++	err = wl_cfg80211_check_in4way(cfg, ndev, DONT_DELETE_GC_AFTER_WPS,
++		WL_EXT_STATUS_DELETE_STA, (void *)mac_addr);
++	if (err) {
++		return 0;
++	}
++
++	assoc_maclist->count = MAX_NUM_OF_ASSOCIATED_DEV;
++	err = wldev_ioctl_get(ndev, WLC_GET_ASSOCLIST,
++		assoc_maclist, sizeof(mac_buf));
++	if (err < 0)
++		WL_ERR(("WLC_GET_ASSOCLIST error %d\n", err));
++	else
++		num_associated = assoc_maclist->count;
++
++	memcpy(scb_val.ea.octet, mac_addr, ETHER_ADDR_LEN);
++#ifdef CUSTOM_BLOCK_DEAUTH_AT_EAP_FAILURE
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++	if (rc == DOT11_RC_8021X_AUTH_FAIL) {
++		WL_ERR(("deauth will be sent at F/W\n"));
++		scb_val.val = DOT11_RC_8021X_AUTH_FAIL;
++	} else {
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) */
++#endif /* CUSTOM_BLOCK_DEAUTH_AT_EAP_FAILURE */
++	scb_val.val = DOT11_RC_DEAUTH_LEAVING;
++	WL_MSG(dev->name, "Disconnect STA %s scb_val.val %d\n",
++		bcm_ether_ntoa((const struct ether_addr *)mac_addr, eabuf),
++		scb_val.val);
++#ifndef BCMDBUS
++	dhd_wait_pend8021x(dev);
++#endif /* !BCMDBUS */
++	err = wldev_ioctl_set(dev, WLC_SCB_DEAUTHENTICATE_FOR_REASON, &scb_val,
++		sizeof(scb_val_t));
++	if (err < 0)
++		WL_ERR(("WLC_SCB_DEAUTHENTICATE_FOR_REASON err %d\n", err));
++#ifdef CUSTOM_BLOCK_DEAUTH_AT_EAP_FAILURE
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++	}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) */
++#endif /* CUSTOM_BLOCK_DEAUTH_AT_EAP_FAILURE */
++
++	if (num_associated > 0 && ETHER_ISBCAST(mac_addr))
++		wl_delay(400);
++
++	return 0;
++}
++
++static s32
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++wl_cfg80211_change_station(
++	struct wiphy *wiphy,
++	struct net_device *dev,
++	const u8 *mac,
++	struct station_parameters *params)
++#else
++wl_cfg80211_change_station(
++	struct wiphy *wiphy,
++	struct net_device *dev,
++	u8 *mac,
++	struct station_parameters *params)
++#endif
++{
++	int err;
++#if defined(WL_ENABLE_P2P_IF)
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++#endif
++	struct net_device *ndev = ndev_to_wlc_ndev(dev, cfg);
++
++	WL_DBG(("SCB_AUTHORIZE mac_addr:"MACDBG" sta_flags_mask:0x%x "
++				"sta_flags_set:0x%x iface:%s \n", MAC2STRDBG(mac),
++				params->sta_flags_mask, params->sta_flags_set, ndev->name));
++
++	/* Processing only authorize/de-authorize flag for now */
++	if (!(params->sta_flags_mask & BIT(NL80211_STA_FLAG_AUTHORIZED))) {
++		WL_ERR(("WLC_SCB_AUTHORIZE sta_flags_mask not set \n"));
++		return -ENOTSUPP;
++	}
++
++	if (!(params->sta_flags_set & BIT(NL80211_STA_FLAG_AUTHORIZED))) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++		err = wldev_ioctl_set(ndev, WLC_SCB_DEAUTHORIZE, (u8 *)mac, ETH_ALEN);
++#else
++		err = wldev_ioctl_set(ndev, WLC_SCB_DEAUTHORIZE, mac, ETH_ALEN);
++#endif
++		if (err)
++			WL_ERR(("WLC_SCB_DEAUTHORIZE error (%d)\n", err));
++		return err;
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++	err = wldev_ioctl_set(ndev, WLC_SCB_AUTHORIZE, (u8 *)mac, ETH_ALEN);
++#else
++	err = wldev_ioctl_set(ndev, WLC_SCB_AUTHORIZE, mac, ETH_ALEN);
++#endif
++	if (err)
++		WL_ERR(("WLC_SCB_AUTHORIZE error (%d)\n", err));
++#ifdef DHD_LOSSLESS_ROAMING
++	wl_del_roam_timeout(cfg);
++#endif
++	return err;
++}
++#endif /* WL_SUPPORT_BACKPORTED_KPATCHES || KERNEL_VER >= KERNEL_VERSION(3, 2, 0)) */
++
++static s32
++wl_cfg80211_set_scb_timings(
++	struct bcm_cfg80211 *cfg,
++	struct net_device *dev)
++{
++	int err;
++	u32 ps_pretend;
++	wl_scb_probe_t scb_probe;
++
++	bzero(&scb_probe, sizeof(wl_scb_probe_t));
++	scb_probe.scb_timeout = WL_SCB_TIMEOUT;
++	scb_probe.scb_activity_time = WL_SCB_ACTIVITY_TIME;
++	scb_probe.scb_max_probe = WL_SCB_MAX_PROBE;
++	err = wldev_iovar_setbuf(dev, "scb_probe", (void *)&scb_probe,
++		sizeof(wl_scb_probe_t), cfg->ioctl_buf, WLC_IOCTL_SMLEN,
++		&cfg->ioctl_buf_sync);
++	if (unlikely(err)) {
++		WL_ERR(("set 'scb_probe' failed, error = %d\n", err));
++		return err;
++	}
++
++	ps_pretend = MAX(WL_SCB_MAX_PROBE / 2, WL_MIN_PSPRETEND_THRESHOLD);
++	err = wldev_iovar_setint(dev, "pspretend_threshold", ps_pretend);
++	if (unlikely(err)) {
++		if (err == BCME_UNSUPPORTED) {
++			/* Ignore error if fw doesn't support the iovar */
++			WL_DBG(("wl pspretend_threshold %d set error %d\n",
++				ps_pretend, err));
++		} else {
++			WL_ERR(("wl pspretend_threshold %d set error %d\n",
++				ps_pretend, err));
++			return err;
++		}
++	}
++
++	return 0;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
++static s32
++wl_cfg80211_start_ap(
++	struct wiphy *wiphy,
++	struct net_device *dev,
++	struct cfg80211_ap_settings *info)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 err = BCME_OK;
++	struct parsed_ies ies;
++	s32 bssidx = 0;
++	u32 dev_role = 0;
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++#ifdef WLMESH_CFG80211
++	struct wl_join_params join_params;
++	s32 join_params_size = 0;
++#endif
++
++	WL_DBG(("Enter \n"));
++
++#if defined(SUPPORT_RANDOM_MAC_SCAN)
++	wl_cfg80211_set_random_mac(dev, FALSE);
++#endif /* SUPPORT_RANDOM_MAC_SCAN */
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	if (p2p_is_on(cfg) && (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_P2P_GO)) {
++		dev_role = NL80211_IFTYPE_P2P_GO;
++	} else if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_AP) {
++		dev_role = NL80211_IFTYPE_AP;
++		dhd->op_mode |= DHD_FLAG_HOSTAP_MODE;
++		err = dhd_ndo_enable(dhd, FALSE);
++		WL_DBG(("%s: Disabling NDO on Hostapd mode %d\n", __FUNCTION__, err));
++		if (err) {
++			WL_ERR(("%s: Disabling NDO Failed %d\n", __FUNCTION__, err));
++		}
++#ifdef WL_EXT_IAPSTA
++		wl_ext_iapsta_update_iftype(dev, dhd_net2idx(dhd->info, dev), WLC_E_IF_ROLE_AP);
++#endif /* WL_EXT_IAPSTA */
++#ifdef PKT_FILTER_SUPPORT
++		/* Disable packet filter */
++		if (dhd->early_suspended) {
++			WL_ERR(("Disable pkt_filter\n"));
++			dhd_enable_packet_filter(0, dhd);
++		}
++#endif /* PKT_FILTER_SUPPORT */
++#ifdef ARP_OFFLOAD_SUPPORT
++		/* IF SoftAP is enabled, disable arpoe */
++		if (dhd->op_mode & DHD_FLAG_STA_MODE) {
++			dhd_arp_offload_set(dhd, 0);
++			dhd_arp_offload_enable(dhd, FALSE);
++		}
++#endif /* ARP_OFFLOAD_SUPPORT */
++#ifdef SUPPORT_SET_CAC
++		wl_cfg80211_set_cac(cfg, 0);
++#endif /* SUPPORT_SET_CAC */
++	} else {
++		/* only AP or GO role need to be handled here. */
++		err = -EINVAL;
++		goto fail;
++	}
++
++	/* disable TDLS */
++#ifdef WLTDLS
++	if (bssidx == 0) {
++		/* Disable TDLS for primary Iface. For virtual interface,
++		 * tdls disable will happen from interface create context
++		 */
++		wl_cfg80211_tdls_config(cfg, TDLS_STATE_AP_CREATE, false);
++	}
++#endif /*  WLTDLS */
++
++	if (!check_dev_role_integrity(cfg, dev_role)) {
++		err = -EINVAL;
++		goto fail;
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	if ((err = wl_cfg80211_set_channel(wiphy, dev,
++		dev->ieee80211_ptr->preset_chandef.chan,
++		NL80211_CHAN_HT20) < 0)) {
++		WL_ERR(("Set channel failed \n"));
++		goto fail;
++	}
++#endif 
++
++	if ((err = wl_cfg80211_bcn_set_params(info, dev,
++		dev_role, bssidx)) < 0) {
++		WL_ERR(("Beacon params set failed \n"));
++		goto fail;
++	}
++
++	/* Parse IEs */
++	if ((err = wl_cfg80211_parse_ap_ies(dev, &info->beacon, &ies)) < 0) {
++		WL_ERR(("Set IEs failed \n"));
++		goto fail;
++	}
++
++	if ((err = wl_cfg80211_bcn_validate_sec(dev, &ies,
++		dev_role, bssidx, info->privacy)) < 0)
++	{
++		WL_ERR(("Beacon set security failed \n"));
++		goto fail;
++	}
++
++	if ((err = wl_cfg80211_bcn_bringup_ap(dev, &ies,
++		dev_role, bssidx)) < 0) {
++		WL_ERR(("Beacon bring up AP/GO failed \n"));
++		goto fail;
++	}
++
++	/* Set GC/STA SCB expiry timings. */
++	if ((err = wl_cfg80211_set_scb_timings(cfg, dev))) {
++		WL_ERR(("scb setting failed \n"));
++//		goto fail;
++	}
++
++#ifdef WLMESH_CFG80211
++	OSL_SLEEP(1000);
++	if ((dev_role == NL80211_IFTYPE_P2P_GO) || (dev_role == NL80211_IFTYPE_AP)) {
++		memset(&join_params, 0, sizeof(join_params));
++		/* join parameters starts with ssid */
++		join_params_size = sizeof(join_params.ssid);
++		if (dev_role == NL80211_IFTYPE_P2P_GO) {
++			join_params.ssid.SSID_len = min(cfg->p2p->ssid.SSID_len,
++				(uint32)DOT11_MAX_SSID_LEN);
++			memcpy(join_params.ssid.SSID, cfg->p2p->ssid.SSID,
++				join_params.ssid.SSID_len);
++		} else if (dev_role == NL80211_IFTYPE_AP) {
++			join_params.ssid.SSID_len = min(cfg->hostapd_ssid.SSID_len,
++				(uint32)DOT11_MAX_SSID_LEN);
++			memcpy(join_params.ssid.SSID, cfg->hostapd_ssid.SSID,
++				join_params.ssid.SSID_len);
++		}
++		join_params.ssid.SSID_len = htod32(join_params.ssid.SSID_len);
++		/* create softap */
++		if ((err = wldev_ioctl_set(dev, WLC_SET_SSID, &join_params,
++			join_params_size)) != 0) {
++			WL_ERR(("SoftAP/GO set ssid failed! \n"));
++			goto fail;
++		} else {
++			WL_DBG((" SoftAP SSID \"%s\" \n", join_params.ssid.SSID));
++		}
++	}
++#endif
++
++	WL_DBG(("** AP/GO Created **\n"));
++
++#ifdef WL_CFG80211_ACL
++	/* Enfoce Admission Control. */
++	if ((err = wl_cfg80211_set_mac_acl(wiphy, dev, info->acl)) < 0) {
++		WL_ERR(("Set ACL failed\n"));
++	}
++#endif /* WL_CFG80211_ACL */
++
++	/* Set IEs to FW */
++	if ((err = wl_cfg80211_set_ies(dev, &info->beacon, bssidx)) < 0)
++		WL_ERR(("Set IEs failed \n"));
++
++	/* Enable Probe Req filter, WPS-AP certification 4.2.13 */
++	if ((dev_role == NL80211_IFTYPE_AP) && (ies.wps_ie != NULL)) {
++		bool pbc = 0;
++		wl_validate_wps_ie((char *) ies.wps_ie, ies.wps_ie_len, &pbc);
++		if (pbc) {
++			WL_DBG(("set WLC_E_PROBREQ_MSG\n"));
++			wl_add_remove_eventmsg(dev, WLC_E_PROBREQ_MSG, true);
++		}
++	}
++
++#ifdef SUPPORT_AP_RADIO_PWRSAVE
++	if ((dev_role == NL80211_IFTYPE_AP)) {
++		wl_set_ap_rps(dev, FALSE, dev->name);
++		wl_cfg80211_init_ap_rps(cfg);
++	}
++#endif /* SUPPORT_AP_RADIO_PWRSAVE */
++fail:
++	if (err) {
++		WL_ERR(("ADD/SET beacon failed\n"));
++		wl_cfg80211_stop_ap(wiphy, dev);
++		if (dev_role == NL80211_IFTYPE_AP) {
++			dhd->op_mode &= ~DHD_FLAG_HOSTAP_MODE;
++#ifdef PKT_FILTER_SUPPORT
++			/* Enable packet filter */
++			if (dhd->early_suspended) {
++				WL_ERR(("Enable pkt_filter\n"));
++				dhd_enable_packet_filter(1, dhd);
++			}
++#endif /* PKT_FILTER_SUPPORT */
++#ifdef ARP_OFFLOAD_SUPPORT
++			/* IF SoftAP is disabled, enable arpoe back for STA mode. */
++			if (dhd->op_mode & DHD_FLAG_STA_MODE) {
++				dhd_arp_offload_set(dhd, dhd_arp_mode);
++				dhd_arp_offload_enable(dhd, TRUE);
++			}
++#endif /* ARP_OFFLOAD_SUPPORT */
++		}
++#ifdef WLTDLS
++		if (bssidx == 0) {
++			/* Since AP creation failed, re-enable TDLS */
++			wl_cfg80211_tdls_config(cfg, TDLS_STATE_AP_DELETE, false);
++		}
++#endif /*  WLTDLS */
++
++	}
++
++	return err;
++}
++
++static s32
++wl_cfg80211_stop_ap(
++	struct wiphy *wiphy,
++	struct net_device *dev)
++{
++	int err = 0;
++	u32 dev_role = 0;
++	int ap = 0;
++	s32 bssidx = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 is_rsdb_supported = BCME_ERROR;
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++
++	WL_DBG(("Enter \n"));
++
++	is_rsdb_supported = DHD_OPMODE_SUPPORTED(cfg->pub, DHD_FLAG_RSDB_MODE);
++	if (is_rsdb_supported < 0)
++		return (-ENODEV);
++
++	wl_clr_drv_status(cfg, AP_CREATING, dev);
++	wl_clr_drv_status(cfg, AP_CREATED, dev);
++	cfg->ap_oper_channel = 0;
++
++	if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_AP) {
++		dev_role = NL80211_IFTYPE_AP;
++		WL_DBG(("stopping AP operation\n"));
++	} else if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_P2P_GO) {
++		dev_role = NL80211_IFTYPE_P2P_GO;
++		WL_DBG(("stopping P2P GO operation\n"));
++	} else {
++		WL_ERR(("no AP/P2P GO interface is operational.\n"));
++		return -EINVAL;
++	}
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	if (!check_dev_role_integrity(cfg, dev_role)) {
++		WL_ERR(("role integrity check failed \n"));
++		err = -EINVAL;
++		goto exit;
++	}
++
++	/* Clear AP/GO connected status */
++	wl_clr_drv_status(cfg, CONNECTED, dev);
++	if ((err = wl_cfg80211_bss_up(cfg, dev, bssidx, 0)) < 0) {
++		WL_ERR(("bss down error %d\n", err));
++	}
++
++	if (dev_role == NL80211_IFTYPE_AP) {
++#ifdef PKT_FILTER_SUPPORT
++		/* Enable packet filter */
++		if (dhd->early_suspended) {
++			WL_ERR(("Enable pkt_filter\n"));
++			dhd_enable_packet_filter(1, dhd);
++		}
++#endif /* PKT_FILTER_SUPPORT */
++#ifdef ARP_OFFLOAD_SUPPORT
++		/* IF SoftAP is disabled, enable arpoe back for STA mode. */
++		if (dhd->op_mode & DHD_FLAG_STA_MODE) {
++			dhd_arp_offload_set(dhd, dhd_arp_mode);
++			dhd_arp_offload_enable(dhd, TRUE);
++		}
++#endif /* ARP_OFFLOAD_SUPPORT */
++
++		if (is_rsdb_supported == 0) {
++			if (dhd_download_fw_on_driverload && bssidx == 0) {
++				wldev_ioctl_set(dev, WLC_DOWN, &ap, sizeof(s32));
++				wldev_iovar_setint(dev, "apsta", 1);
++			}
++			/* For non-rsdb chips, we use stand alone AP. Do wl down on stop AP */
++			err = wldev_ioctl_set(dev, WLC_UP, &ap, sizeof(s32));
++			if (unlikely(err)) {
++				WL_ERR(("WLC_UP error (%d)\n", err));
++				err = -EINVAL;
++				goto exit;
++			}
++		}
++
++		 wl_cfg80211_clear_per_bss_ies(cfg, bssidx);
++#ifdef SUPPORT_AP_RADIO_PWRSAVE
++		wl_set_ap_rps(dev, FALSE, dev->name);
++		wl_cfg80211_init_ap_rps(cfg);
++#endif /* SUPPORT_AP_RADIO_PWRSAVE */
++	} else {
++		WL_DBG(("Stopping P2P GO \n"));
++		DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_ENABLE((dhd_pub_t *)(cfg->pub),
++			DHD_EVENT_TIMEOUT_MS*3);
++		DHD_OS_WAKE_LOCK_TIMEOUT((dhd_pub_t *)(cfg->pub));
++	}
++exit:
++#ifdef WLTDLS
++	if (bssidx == 0) {
++		/* re-enable TDLS if the number of connected interfaces is less than 2 */
++		wl_cfg80211_tdls_config(cfg, TDLS_STATE_AP_DELETE, false);
++	}
++#endif /* WLTDLS */
++
++	if (dev_role == NL80211_IFTYPE_AP) {
++		/* clear the AP mode */
++		dhd->op_mode &= ~DHD_FLAG_HOSTAP_MODE;
++	}
++#ifdef SUPPORT_SET_CAC
++	wl_cfg80211_set_cac(cfg, 1);
++#endif /* SUPPORT_SET_CAC */
++	return err;
++}
++
++static s32
++wl_cfg80211_change_beacon(
++	struct wiphy *wiphy,
++	struct net_device *dev,
++	struct cfg80211_beacon_data *info)
++{
++	s32 err = BCME_OK;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct parsed_ies ies;
++	u32 dev_role = 0;
++	s32 bssidx = 0;
++	bool pbc = 0;
++
++	WL_DBG(("Enter \n"));
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_P2P_GO) {
++		dev_role = NL80211_IFTYPE_P2P_GO;
++	} else if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_AP) {
++		dev_role = NL80211_IFTYPE_AP;
++	} else {
++		err = -EINVAL;
++		goto fail;
++	}
++
++	if (!check_dev_role_integrity(cfg, dev_role)) {
++		err = -EINVAL;
++		goto fail;
++	}
++
++	if ((dev_role == NL80211_IFTYPE_P2P_GO) && (cfg->p2p_wdev == NULL)) {
++		WL_ERR(("P2P already down status!\n"));
++		err = BCME_ERROR;
++		goto fail;
++	}
++
++	/* Parse IEs */
++	if ((err = wl_cfg80211_parse_ap_ies(dev, info, &ies)) < 0) {
++		WL_ERR(("Parse IEs failed \n"));
++		goto fail;
++	}
++
++	/* Set IEs to FW */
++	if ((err = wl_cfg80211_set_ies(dev, info, bssidx)) < 0) {
++		WL_ERR(("Set IEs failed \n"));
++		goto fail;
++	}
++
++	if (dev_role == NL80211_IFTYPE_AP) {
++		if (wl_cfg80211_hostapd_sec(dev, &ies, bssidx) < 0) {
++			WL_ERR(("Hostapd update sec failed \n"));
++			err = -EINVAL;
++			goto fail;
++		}
++		/* Enable Probe Req filter, WPS-AP certification 4.2.13 */
++		if ((dev_role == NL80211_IFTYPE_AP) && (ies.wps_ie != NULL)) {
++			wl_validate_wps_ie((char *) ies.wps_ie, ies.wps_ie_len, &pbc);
++			WL_DBG((" WPS AP, wps_ie is exists pbc=%d\n", pbc));
++			if (pbc)
++				wl_add_remove_eventmsg(dev, WLC_E_PROBREQ_MSG, true);
++			else
++				wl_add_remove_eventmsg(dev, WLC_E_PROBREQ_MSG, false);
++		}
++	}
++
++fail:
++	return err;
++}
++#else
++static s32
++wl_cfg80211_add_set_beacon(struct wiphy *wiphy, struct net_device *dev,
++	struct beacon_parameters *info)
++{
++	s32 err = BCME_OK;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 ie_offset = 0;
++	s32 bssidx = 0;
++	u32 dev_role = NL80211_IFTYPE_AP;
++	struct parsed_ies ies;
++	bcm_tlv_t *ssid_ie;
++	bool pbc = 0;
++	bool privacy;
++	bool is_bss_up = 0;
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++
++	WL_DBG(("interval (%d) dtim_period (%d) head_len (%d) tail_len (%d)\n",
++		info->interval, info->dtim_period, info->head_len, info->tail_len));
++
++	if (dev == bcmcfg_to_prmry_ndev(cfg)) {
++		dev_role = NL80211_IFTYPE_AP;
++	}
++#if defined(WL_ENABLE_P2P_IF)
++	else if (dev == cfg->p2p_net) {
++		/* Group Add request on p2p0 */
++		dev = bcmcfg_to_prmry_ndev(cfg);
++		dev_role = NL80211_IFTYPE_P2P_GO;
++	}
++#endif /* WL_ENABLE_P2P_IF */
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_P2P_GO) {
++		dev_role = NL80211_IFTYPE_P2P_GO;
++	} else if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_AP) {
++		dhd->op_mode |= DHD_FLAG_HOSTAP_MODE;
++	}
++
++	if (!check_dev_role_integrity(cfg, dev_role)) {
++		err = -ENODEV;
++		goto fail;
++	}
++
++	if ((dev_role == NL80211_IFTYPE_P2P_GO) && (cfg->p2p_wdev == NULL)) {
++		WL_ERR(("P2P already down status!\n"));
++		err = BCME_ERROR;
++		goto fail;
++	}
++
++	ie_offset = DOT11_MGMT_HDR_LEN + DOT11_BCN_PRB_FIXED_LEN;
++	/* find the SSID */
++	if ((ssid_ie = bcm_parse_tlvs((u8 *)&info->head[ie_offset],
++		info->head_len - ie_offset,
++		DOT11_MNG_SSID_ID)) != NULL) {
++		if (dev_role == NL80211_IFTYPE_AP) {
++			/* Store the hostapd SSID */
++			memset(&cfg->hostapd_ssid.SSID[0], 0x00, DOT11_MAX_SSID_LEN);
++			cfg->hostapd_ssid.SSID_len = MIN(ssid_ie->len, DOT11_MAX_SSID_LEN);
++			memcpy(&cfg->hostapd_ssid.SSID[0], ssid_ie->data,
++				cfg->hostapd_ssid.SSID_len);
++		} else {
++			/* P2P GO */
++			memset(&cfg->p2p->ssid.SSID[0], 0x00, DOT11_MAX_SSID_LEN);
++			cfg->p2p->ssid.SSID_len = MIN(ssid_ie->len, DOT11_MAX_SSID_LEN);
++			memcpy(cfg->p2p->ssid.SSID, ssid_ie->data,
++				cfg->p2p->ssid.SSID_len);
++		}
++	}
++
++	if (wl_cfg80211_parse_ies((u8 *)info->tail,
++		info->tail_len, &ies) < 0) {
++		WL_ERR(("Beacon get IEs failed \n"));
++		err = -EINVAL;
++		goto fail;
++	}
++
++	if ((err = wl_cfg80211_set_mgmt_vndr_ies(cfg, ndev_to_cfgdev(dev), bssidx,
++		VNDR_IE_BEACON_FLAG, (u8 *)info->tail,
++		info->tail_len)) < 0) {
++		WL_ERR(("Beacon set IEs failed \n"));
++		goto fail;
++	} else {
++		WL_DBG(("Applied Vndr IEs for Beacon \n"));
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	if ((err = wl_cfg80211_set_mgmt_vndr_ies(cfg, ndev_to_cfgdev(dev), bssidx,
++		VNDR_IE_PRBRSP_FLAG, (u8 *)info->proberesp_ies,
++		info->proberesp_ies_len)) < 0) {
++		WL_ERR(("ProbeRsp set IEs failed \n"));
++		goto fail;
++	} else {
++		WL_DBG(("Applied Vndr IEs for ProbeRsp \n"));
++	}
++#endif
++
++	is_bss_up = wl_cfg80211_bss_isup(dev, bssidx);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	privacy = info->privacy;
++#else
++	privacy = 0;
++#endif
++	if (!is_bss_up &&
++		(wl_cfg80211_bcn_validate_sec(dev, &ies, dev_role, bssidx, privacy) < 0))
++	{
++		WL_ERR(("Beacon set security failed \n"));
++		err = -EINVAL;
++		goto fail;
++	}
++
++	/* Set BI and DTIM period */
++	if (info->interval) {
++		if ((err = wldev_ioctl_set(dev, WLC_SET_BCNPRD,
++			&info->interval, sizeof(s32))) < 0) {
++			WL_ERR(("Beacon Interval Set Error, %d\n", err));
++			return err;
++		}
++	}
++	if (info->dtim_period) {
++		if ((err = wldev_ioctl_set(dev, WLC_SET_DTIMPRD,
++			&info->dtim_period, sizeof(s32))) < 0) {
++			WL_ERR(("DTIM Interval Set Error, %d\n", err));
++			return err;
++		}
++	}
++
++	/* If bss is already up, skip bring up */
++	if (!is_bss_up &&
++		(err = wl_cfg80211_bcn_bringup_ap(dev, &ies, dev_role, bssidx)) < 0)
++	{
++		WL_ERR(("Beacon bring up AP/GO failed \n"));
++		goto fail;
++	}
++
++	/* Set GC/STA SCB expiry timings. */
++	if ((err = wl_cfg80211_set_scb_timings(cfg, dev))) {
++		WL_ERR(("scb setting failed \n"));
++		if (err == BCME_UNSUPPORTED)
++			err = 0;
++//		goto fail;
++	}
++
++	if (wl_get_drv_status(cfg, AP_CREATED, dev)) {
++		/* Soft AP already running. Update changed params */
++		if (wl_cfg80211_hostapd_sec(dev, &ies, bssidx) < 0) {
++			WL_ERR(("Hostapd update sec failed \n"));
++			err = -EINVAL;
++			goto fail;
++		}
++	}
++
++	/* Enable Probe Req filter */
++	if (((dev_role == NL80211_IFTYPE_P2P_GO) ||
++		(dev_role == NL80211_IFTYPE_AP)) && (ies.wps_ie != NULL)) {
++		wl_validate_wps_ie((char *) ies.wps_ie, ies.wps_ie_len, &pbc);
++		if (pbc)
++			wl_add_remove_eventmsg(dev, WLC_E_PROBREQ_MSG, true);
++	}
++
++	WL_DBG(("** ADD/SET beacon done **\n"));
++
++fail:
++	if (err) {
++		WL_ERR(("ADD/SET beacon failed\n"));
++		if (dev_role == NL80211_IFTYPE_AP) {
++			/* clear the AP mode */
++			dhd->op_mode &= ~DHD_FLAG_HOSTAP_MODE;
++		}
++	}
++	return err;
++
++}
++
++static s32
++wl_cfg80211_del_beacon(struct wiphy *wiphy, struct net_device *dev)
++{
++	int err = 0;
++	s32 bssidx = 0;
++	int infra = 0;
++	struct wireless_dev *wdev = dev->ieee80211_ptr;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++
++	WL_DBG(("Enter. \n"));
++
++	if (!wdev) {
++		WL_ERR(("wdev null \n"));
++		return -EINVAL;
++	}
++
++	if ((wdev->iftype != NL80211_IFTYPE_P2P_GO) && (wdev->iftype != NL80211_IFTYPE_AP)) {
++		WL_ERR(("Unspported iface type iftype:%d \n", wdev->iftype));
++	}
++
++	wl_clr_drv_status(cfg, AP_CREATING, dev);
++	wl_clr_drv_status(cfg, AP_CREATED, dev);
++
++	/* Clear AP/GO connected status */
++	wl_clr_drv_status(cfg, CONNECTED, dev);
++
++	cfg->ap_oper_channel = 0;
++
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	/* Do bss down */
++	if ((err = wl_cfg80211_bss_up(cfg, dev, bssidx, 0)) < 0) {
++		WL_ERR(("bss down error %d\n", err));
++	}
++
++	/* fall through is intentional */
++	err = wldev_ioctl_set(dev, WLC_SET_INFRA, &infra, sizeof(s32));
++	if (err < 0) {
++		WL_ERR(("SET INFRA error %d\n", err));
++	}
++	 wl_cfg80211_clear_per_bss_ies(cfg, bssidx);
++
++	if (wdev->iftype == NL80211_IFTYPE_AP) {
++		/* clear the AP mode */
++		dhd->op_mode &= ~DHD_FLAG_HOSTAP_MODE;
++	}
++
++	return 0;
++}
++#endif 
++
++#ifdef WL_SCHED_SCAN
++#define PNO_TIME		30
++#define PNO_REPEAT		4
++#define PNO_FREQ_EXPO_MAX	2
++static bool
++is_ssid_in_list(struct cfg80211_ssid *ssid, struct cfg80211_ssid *ssid_list, int count)
++{
++	int i;
++
++	if (!ssid || !ssid_list)
++		return FALSE;
++
++	for (i = 0; i < count; i++) {
++		if (ssid->ssid_len == ssid_list[i].ssid_len) {
++			if (strncmp(ssid->ssid, ssid_list[i].ssid, ssid->ssid_len) == 0)
++				return TRUE;
++		}
++	}
++	return FALSE;
++}
++
++static int
++wl_cfg80211_sched_scan_start(struct wiphy *wiphy,
++                             struct net_device *dev,
++                             struct cfg80211_sched_scan_request *request)
++{
++	ushort pno_time = PNO_TIME;
++	int pno_repeat = PNO_REPEAT;
++	int pno_freq_expo_max = PNO_FREQ_EXPO_MAX;
++	wlc_ssid_ext_t ssids_local[MAX_PFN_LIST_COUNT];
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++	struct cfg80211_ssid *ssid = NULL;
++	struct cfg80211_ssid *hidden_ssid_list = NULL;
++	log_conn_event_t *event_data = NULL;
++	tlv_log *tlv_data = NULL;
++	u32 alloc_len, tlv_len;
++	u32 payload_len;
++	int ssid_cnt = 0;
++	int i;
++	int ret = 0;
++	unsigned long flags;
++
++	if (!request) {
++		WL_ERR(("Sched scan request was NULL\n"));
++		return -EINVAL;
++	}
++
++	WL_DBG(("Enter \n"));
++	WL_PNO((">>> SCHED SCAN START\n"));
++	WL_PNO(("Enter n_match_sets:%d   n_ssids:%d \n",
++		request->n_match_sets, request->n_ssids));
++	WL_PNO(("ssids:%d pno_time:%d pno_repeat:%d pno_freq:%d \n",
++		request->n_ssids, pno_time, pno_repeat, pno_freq_expo_max));
++
++
++	if (!request->n_ssids || !request->n_match_sets) {
++		WL_ERR(("Invalid sched scan req!! n_ssids:%d \n", request->n_ssids));
++		return -EINVAL;
++	}
++
++	memset(&ssids_local, 0, sizeof(ssids_local));
++
++	if (request->n_ssids > 0) {
++		hidden_ssid_list = request->ssids;
++	}
++
++	if (DBG_RING_ACTIVE(dhdp, DHD_EVENT_RING_ID)) {
++		alloc_len = sizeof(log_conn_event_t) + DOT11_MAX_SSID_LEN;
++		event_data = MALLOC(dhdp->osh, alloc_len);
++		if (!event_data) {
++			WL_ERR(("%s: failed to allocate log_conn_event_t with "
++						"length(%d)\n", __func__, alloc_len));
++			return -ENOMEM;
++		}
++		memset(event_data, 0, alloc_len);
++		event_data->tlvs = NULL;
++		tlv_len = sizeof(tlv_log);
++		event_data->tlvs = (tlv_log *)MALLOC(dhdp->osh, tlv_len);
++		if (!event_data->tlvs) {
++			WL_ERR(("%s: failed to allocate log_tlv with "
++					"length(%d)\n", __func__, tlv_len));
++			MFREE(dhdp->osh, event_data, alloc_len);
++			return -ENOMEM;
++		}
++	}
++	for (i = 0; i < request->n_match_sets && ssid_cnt < MAX_PFN_LIST_COUNT; i++) {
++		ssid = &request->match_sets[i].ssid;
++		/* No need to include null ssid */
++		if (ssid->ssid_len) {
++			ssids_local[ssid_cnt].SSID_len = MIN(ssid->ssid_len,
++				(uint32)DOT11_MAX_SSID_LEN);
++			memcpy(ssids_local[ssid_cnt].SSID, ssid->ssid,
++				ssids_local[ssid_cnt].SSID_len);
++			if (is_ssid_in_list(ssid, hidden_ssid_list, request->n_ssids)) {
++				ssids_local[ssid_cnt].hidden = TRUE;
++				WL_PNO((">>> PNO hidden SSID (%s) \n", ssid->ssid));
++			} else {
++				ssids_local[ssid_cnt].hidden = FALSE;
++				WL_PNO((">>> PNO non-hidden SSID (%s) \n", ssid->ssid));
++			}
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 15, 0))
++			if (request->match_sets[i].rssi_thold != NL80211_SCAN_RSSI_THOLD_OFF) {
++				ssids_local[ssid_cnt].rssi_thresh =
++				      (int8)request->match_sets[i].rssi_thold;
++			}
++#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(3, 15, 0)) */
++			ssid_cnt++;
++		}
++	}
++
++	if (ssid_cnt) {
++		if ((ret = dhd_dev_pno_set_for_ssid(dev, ssids_local, ssid_cnt,
++			pno_time, pno_repeat, pno_freq_expo_max, NULL, 0)) < 0) {
++			WL_ERR(("PNO setup failed!! ret=%d \n", ret));
++			ret = -EINVAL;
++			goto exit;
++		}
++
++		if (DBG_RING_ACTIVE(dhdp, DHD_EVENT_RING_ID)) {
++			for (i = 0; i < ssid_cnt; i++) {
++				payload_len = sizeof(log_conn_event_t);
++				event_data->event = WIFI_EVENT_DRIVER_PNO_ADD;
++				tlv_data = event_data->tlvs;
++				/* ssid */
++				tlv_data->tag = WIFI_TAG_SSID;
++				tlv_data->len = ssids_local[i].SSID_len;
++				memcpy(tlv_data->value, ssids_local[i].SSID,
++					ssids_local[i].SSID_len);
++				payload_len += TLV_LOG_SIZE(tlv_data);
++
++				dhd_os_push_push_ring_data(dhdp, DHD_EVENT_RING_ID,
++					event_data, payload_len);
++			}
++		}
++
++		spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++		cfg->sched_scan_req = request;
++		spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++	} else {
++		ret = -EINVAL;
++	}
++exit:
++	if (event_data) {
++		MFREE(dhdp->osh, event_data->tlvs, tlv_len);
++		MFREE(dhdp->osh, event_data, alloc_len);
++	}
++	return ret;
++}
++
++static int
++wl_cfg80211_sched_scan_stop(struct wiphy *wiphy, struct net_device *dev
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++	, u64 reqid
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)) */
++)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++	unsigned long flags;
++
++	WL_DBG(("Enter \n"));
++	WL_PNO((">>> SCHED SCAN STOP\n"));
++
++	BCM_REFERENCE(dhdp);
++	if (dhd_dev_pno_stop_for_ssid(dev) < 0) {
++		WL_ERR(("PNO Stop for SSID failed"));
++	} else {
++		DBG_EVENT_LOG(dhdp, WIFI_EVENT_DRIVER_PNO_REMOVE);
++	}
++
++	if (cfg->scan_request && cfg->sched_scan_running) {
++		WL_PNO((">>> Sched scan running. Aborting it..\n"));
++		wl_notify_escan_complete(cfg, dev, true, true);
++	}
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++	cfg->sched_scan_req = NULL;
++	cfg->sched_scan_running = FALSE;
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++	return 0;
++}
++#endif /* WL_SCHED_SCAN */
++
++#ifdef WL_SUPPORT_ACS
++/*
++ * Currently the dump_obss IOVAR is returning string as output so we need to
++ * parse the output buffer in an unoptimized way. Going forward if we get the
++ * IOVAR output in binary format this method can be optimized
++ */
++static int wl_parse_dump_obss(char *buf, struct wl_dump_survey *survey)
++{
++	int i;
++	char *token;
++	char delim[] = " \n";
++
++	token = strsep(&buf, delim);
++	while (token != NULL) {
++		if (!strcmp(token, "OBSS")) {
++			for (i = 0; i < OBSS_TOKEN_IDX; i++)
++				token = strsep(&buf, delim);
++			survey->obss = simple_strtoul(token, NULL, 10);
++		}
++
++		if (!strcmp(token, "IBSS")) {
++			for (i = 0; i < IBSS_TOKEN_IDX; i++)
++				token = strsep(&buf, delim);
++			survey->ibss = simple_strtoul(token, NULL, 10);
++		}
++
++		if (!strcmp(token, "TXDur")) {
++			for (i = 0; i < TX_TOKEN_IDX; i++)
++				token = strsep(&buf, delim);
++			survey->tx = simple_strtoul(token, NULL, 10);
++		}
++
++		if (!strcmp(token, "Category")) {
++			for (i = 0; i < CTG_TOKEN_IDX; i++)
++				token = strsep(&buf, delim);
++			survey->no_ctg = simple_strtoul(token, NULL, 10);
++		}
++
++		if (!strcmp(token, "Packet")) {
++			for (i = 0; i < PKT_TOKEN_IDX; i++)
++				token = strsep(&buf, delim);
++			survey->no_pckt = simple_strtoul(token, NULL, 10);
++		}
++
++		if (!strcmp(token, "Opp(time):")) {
++			for (i = 0; i < IDLE_TOKEN_IDX; i++)
++				token = strsep(&buf, delim);
++			survey->idle = simple_strtoul(token, NULL, 10);
++		}
++
++		token = strsep(&buf, delim);
++	}
++
++	return 0;
++}
++
++static int wl_dump_obss(struct net_device *ndev, cca_msrmnt_query req,
++	struct wl_dump_survey *survey)
++{
++	cca_stats_n_flags *results;
++	char *buf;
++	int retry, err;
++
++	buf = kzalloc(sizeof(char) * WLC_IOCTL_MAXLEN, GFP_KERNEL);
++	if (unlikely(!buf)) {
++		WL_ERR(("%s: buf alloc failed\n", __func__));
++		return -ENOMEM;
++	}
++
++	retry = IOCTL_RETRY_COUNT;
++	while (retry--) {
++		err = wldev_iovar_getbuf(ndev, "dump_obss", &req, sizeof(req),
++			buf, WLC_IOCTL_MAXLEN, NULL);
++		if (err >=  0) {
++			break;
++		}
++		WL_DBG(("attempt = %d, err = %d, \n",
++			(IOCTL_RETRY_COUNT - retry), err));
++	}
++
++	if (retry <= 0)	{
++		WL_ERR(("failure, dump_obss IOVAR failed\n"));
++		err = -EINVAL;
++		goto exit;
++	}
++
++	results = (cca_stats_n_flags *)(buf);
++	wl_parse_dump_obss(results->buf, survey);
++	kfree(buf);
++
++	return 0;
++exit:
++	kfree(buf);
++	return err;
++}
++
++static int wl_cfg80211_dump_survey(struct wiphy *wiphy, struct net_device *ndev,
++	int idx, struct survey_info *info)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct wl_dump_survey *survey;
++	struct ieee80211_supported_band *band;
++	struct ieee80211_channel*chan;
++	cca_msrmnt_query req;
++	int val, err, noise, retry;
++
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++	if (!(dhd->op_mode & DHD_FLAG_HOSTAP_MODE)) {
++		return -ENOENT;
++	}
++	band = wiphy->bands[IEEE80211_BAND_2GHZ];
++	if (band && idx >= band->n_channels) {
++		idx -= band->n_channels;
++		band = NULL;
++	}
++
++	if (!band || idx >= band->n_channels) {
++		/* Move to 5G band */
++		band = wiphy->bands[IEEE80211_BAND_5GHZ];
++		if (idx >= band->n_channels) {
++			return -ENOENT;
++		}
++	}
++
++	chan = &band->channels[idx];
++	/* Setting current channel to the requested channel */
++	if ((err = wl_cfg80211_set_channel(wiphy, ndev, chan,
++		NL80211_CHAN_HT20) < 0)) {
++		WL_ERR(("Set channel failed \n"));
++	}
++
++	if (!idx) {
++		/* Set interface up, explicitly. */
++		val = 1;
++		err = wldev_ioctl_set(ndev, WLC_UP, (void *)&val, sizeof(val));
++		if (err < 0) {
++			WL_ERR(("set interface up failed, error = %d\n", err));
++		}
++	}
++
++	/* Get noise value */
++	retry = IOCTL_RETRY_COUNT;
++	while (retry--) {
++		noise = 0;
++		err = wldev_ioctl_get(ndev, WLC_GET_PHY_NOISE, &noise,
++			sizeof(noise));
++		if (err >=  0) {
++			break;
++		}
++		WL_DBG(("attempt = %d, err = %d, \n",
++			(IOCTL_RETRY_COUNT - retry), err));
++	}
++
++	if (retry <= 0)	{
++		WL_ERR(("Get Phy Noise failed, error = %d\n", err));
++		noise = CHAN_NOISE_DUMMY;
++	}
++
++	survey = (struct wl_dump_survey *) kzalloc(sizeof(struct wl_dump_survey),
++		GFP_KERNEL);
++	if (unlikely(!survey)) {
++		WL_ERR(("%s: alloc failed\n", __func__));
++		return -ENOMEM;
++	}
++
++	/* Start Measurement for obss stats on current channel */
++	req.msrmnt_query = 0;
++	req.time_req = ACS_MSRMNT_DELAY;
++	if ((err = wl_dump_obss(ndev, req, survey)) < 0) {
++		goto exit;
++	}
++
++	/*
++	 * Wait for the meaurement to complete, adding a buffer value of 10 to take
++	 * into consideration any delay in IOVAR completion
++	 */
++	msleep(ACS_MSRMNT_DELAY + 10);
++
++	/* Issue IOVAR to collect measurement results */
++	req.msrmnt_query = 1;
++	if ((err = wl_dump_obss(ndev, req, survey)) < 0) {
++		goto exit;
++	}
++
++	info->channel = chan;
++	info->noise = noise;
++	info->channel_time = ACS_MSRMNT_DELAY;
++	info->channel_time_busy = ACS_MSRMNT_DELAY - survey->idle;
++	info->channel_time_rx = survey->obss + survey->ibss + survey->no_ctg +
++		survey->no_pckt;
++	info->channel_time_tx = survey->tx;
++	info->filled = SURVEY_INFO_NOISE_DBM |SURVEY_INFO_CHANNEL_TIME |
++		SURVEY_INFO_CHANNEL_TIME_BUSY |	SURVEY_INFO_CHANNEL_TIME_RX |
++		SURVEY_INFO_CHANNEL_TIME_TX;
++	kfree(survey);
++
++	return 0;
++exit:
++	kfree(survey);
++	return err;
++}
++#endif /* WL_SUPPORT_ACS */
++
++static struct cfg80211_ops wl_cfg80211_ops = {
++	.add_virtual_intf = wl_cfg80211_add_virtual_iface,
++	.del_virtual_intf = wl_cfg80211_del_virtual_iface,
++	.change_virtual_intf = wl_cfg80211_change_virtual_iface,
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	.start_p2p_device = wl_cfgp2p_start_p2p_device,
++	.stop_p2p_device = wl_cfgp2p_stop_p2p_device,
++#endif /* WL_CFG80211_P2P_DEV_IF */
++	.scan = wl_cfg80211_scan,
++	.set_wiphy_params = wl_cfg80211_set_wiphy_params,
++	.join_ibss = wl_cfg80211_join_ibss,
++	.leave_ibss = wl_cfg80211_leave_ibss,
++	.get_station = wl_cfg80211_get_station,
++	.set_tx_power = wl_cfg80211_set_tx_power,
++	.get_tx_power = wl_cfg80211_get_tx_power,
++	.add_key = wl_cfg80211_add_key,
++	.del_key = wl_cfg80211_del_key,
++	.get_key = wl_cfg80211_get_key,
++	.set_default_key = wl_cfg80211_config_default_key,
++	.set_default_mgmt_key = wl_cfg80211_config_default_mgmt_key,
++	.set_power_mgmt = wl_cfg80211_set_power_mgmt,
++	.connect = wl_cfg80211_connect,
++	.disconnect = wl_cfg80211_disconnect,
++	.suspend = wl_cfg80211_suspend,
++	.resume = wl_cfg80211_resume,
++	.set_pmksa = wl_cfg80211_set_pmksa,
++	.del_pmksa = wl_cfg80211_del_pmksa,
++	.flush_pmksa = wl_cfg80211_flush_pmksa,
++	.remain_on_channel = wl_cfg80211_remain_on_channel,
++	.cancel_remain_on_channel = wl_cfg80211_cancel_remain_on_channel,
++	.mgmt_tx = wl_cfg80211_mgmt_tx,
++	.change_bss = wl_cfg80211_change_bss,
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++	.set_channel = wl_cfg80211_set_channel,
++#endif 
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0))
++	.set_beacon = wl_cfg80211_add_set_beacon,
++	.add_beacon = wl_cfg80211_add_set_beacon,
++	.del_beacon = wl_cfg80211_del_beacon,
++#else
++	.change_beacon = wl_cfg80211_change_beacon,
++	.start_ap = wl_cfg80211_start_ap,
++	.stop_ap = wl_cfg80211_stop_ap,
++#endif 
++#ifdef WL_SCHED_SCAN
++	.sched_scan_start = wl_cfg80211_sched_scan_start,
++	.sched_scan_stop = wl_cfg80211_sched_scan_stop,
++#endif /* WL_SCHED_SCAN */
++#if defined(WL_SUPPORT_BACKPORTED_KPATCHES) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, \
++	2, 0))
++	.del_station = wl_cfg80211_del_station,
++	.change_station = wl_cfg80211_change_station,
++	.mgmt_tx_cancel_wait = wl_cfg80211_mgmt_tx_cancel_wait,
++#endif /* WL_SUPPORT_BACKPORTED_KPATCHES || KERNEL_VERSION >= (3,2,0) */
++#ifdef WLMESH_CFG80211
++	.join_mesh = wl_cfg80211_join_mesh,
++	.leave_mesh = wl_cfg80211_leave_mesh,
++#endif /* WLMESH_CFG80211 */
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 2, 0))
++	.tdls_mgmt = wl_cfg80211_tdls_mgmt,
++	.tdls_oper = wl_cfg80211_tdls_oper,
++#endif 
++#ifdef WL_SUPPORT_ACS
++	.dump_survey = wl_cfg80211_dump_survey,
++#endif /* WL_SUPPORT_ACS */
++#ifdef WL_CFG80211_ACL
++	.set_mac_acl = wl_cfg80211_set_mac_acl,
++#endif /* WL_CFG80211_ACL */
++#ifdef GTK_OFFLOAD_SUPPORT
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
++	.set_rekey_data = wl_cfg80211_set_rekey_data,
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0) */
++#endif /* GTK_OFFLOAD_SUPPORT */
++};
++
++s32 wl_mode_to_nl80211_iftype(s32 mode)
++{
++	s32 err = 0;
++
++	switch (mode) {
++	case WL_MODE_BSS:
++		return NL80211_IFTYPE_STATION;
++	case WL_MODE_IBSS:
++		return NL80211_IFTYPE_ADHOC;
++	case WL_MODE_AP:
++		return NL80211_IFTYPE_AP;
++#ifdef WLMESH_CFG80211
++	case WL_MODE_MESH:
++		return NL80211_IFTYPE_MESH_POINT;
++#endif
++	default:
++		return NL80211_IFTYPE_UNSPECIFIED;
++	}
++
++	return err;
++}
++
++#ifdef CONFIG_CFG80211_INTERNAL_REGDB
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
++#define WL_CFG80211_REG_NOTIFIER() static int wl_cfg80211_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
++#else
++#define WL_CFG80211_REG_NOTIFIER() static void wl_cfg80211_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
++#endif /* kernel version < 3.9.0 */
++#endif
++
++#ifdef CONFIG_CFG80211_INTERNAL_REGDB
++WL_CFG80211_REG_NOTIFIER()
++{
++	struct bcm_cfg80211 *cfg = (struct bcm_cfg80211 *)wiphy_priv(wiphy);
++	int ret = 0;
++	int revinfo = -1;
++
++	if (!request || !cfg) {
++		WL_ERR(("Invalid arg\n"));
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 11))
++		return -EINVAL;
++#else
++		return;
++#endif /* kernel version < 3.10.11 */
++	}
++
++	WL_DBG(("ccode: %c%c Initiator: %d\n",
++		request->alpha2[0], request->alpha2[1], request->initiator));
++
++	/* We support only REGDOM_SET_BY_USER as of now */
++	if ((request->initiator != NL80211_REGDOM_SET_BY_USER) &&
++		(request->initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE)) {
++		WL_ERR(("reg_notifier for intiator:%d not supported : set default\n",
++			request->initiator));
++		/* in case of no supported country by regdb
++		     lets driver setup platform default Locale
++		*/
++	}
++
++	WL_ERR(("Set country code %c%c from %s\n",
++		request->alpha2[0], request->alpha2[1],
++		((request->initiator == NL80211_REGDOM_SET_BY_COUNTRY_IE) ? " 11d AP" : "User")));
++
++	if ((ret = wldev_set_country(bcmcfg_to_prmry_ndev(cfg), request->alpha2,
++		false, (request->initiator == NL80211_REGDOM_SET_BY_USER ? true : false),
++		revinfo)) < 0) {
++		WL_ERR(("set country Failed :%d\n", ret));
++	}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 11))
++	return ret;
++#else
++	return;
++#endif /* kernel version < 3.10.11 */
++}
++#endif /* CONFIG_CFG80211_INTERNAL_REGDB */
++
++#ifdef CONFIG_PM
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++static const struct wiphy_wowlan_support brcm_wowlan_support = {
++	.flags = WIPHY_WOWLAN_ANY,
++	.n_patterns = WL_WOWLAN_MAX_PATTERNS,
++	.pattern_min_len = WL_WOWLAN_MIN_PATTERN_LEN,
++	.pattern_max_len = WL_WOWLAN_MAX_PATTERN_LEN,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++	.max_pkt_offset = WL_WOWLAN_MAX_PATTERN_LEN,
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) */
++};
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0) */
++#endif /* CONFIG_PM */
++
++static s32 wl_setup_wiphy(struct wireless_dev *wdev, struct device *sdiofunc_dev, dhd_pub_t *context)
++{
++	s32 err = 0;
++#ifdef CONFIG_PM
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++	struct cfg80211_wowlan *brcm_wowlan_config = NULL;
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0) */
++#endif /* CONFIG_PM */
++
++//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
++	dhd_pub_t *dhd = (dhd_pub_t *)context;
++	BCM_REFERENCE(dhd);
++
++	if (!dhd) {
++		WL_ERR(("DHD is NULL!!"));
++		err = -ENODEV;
++		return err;
++	}
++//#endif 
++
++	wdev->wiphy =
++	    wiphy_new(&wl_cfg80211_ops, sizeof(struct bcm_cfg80211));
++	if (unlikely(!wdev->wiphy)) {
++		WL_ERR(("Couldn not allocate wiphy device\n"));
++		err = -ENOMEM;
++		return err;
++	}
++	set_wiphy_dev(wdev->wiphy, sdiofunc_dev);
++	wdev->wiphy->max_scan_ie_len = WL_SCAN_IE_LEN_MAX;
++	/* Report  how many SSIDs Driver can support per Scan request */
++	wdev->wiphy->max_scan_ssids = WL_SCAN_PARAMS_SSID_MAX;
++	wdev->wiphy->max_num_pmkids = WL_NUM_PMKIDS_MAX;
++#ifdef WL_SCHED_SCAN
++	wdev->wiphy->max_sched_scan_ssids = MAX_PFN_LIST_COUNT;
++	wdev->wiphy->max_match_sets = MAX_PFN_LIST_COUNT;
++	wdev->wiphy->max_sched_scan_ie_len = WL_SCAN_IE_LEN_MAX;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++	wdev->wiphy->max_sched_scan_plan_interval = PNO_SCAN_MAX_FW_SEC;
++#else
++	wdev->wiphy->flags |= WIPHY_FLAG_SUPPORTS_SCHED_SCAN;
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)) */
++#endif /* WL_SCHED_SCAN */
++#ifdef WLMESH_CFG80211
++	wdev->wiphy->flags |= WIPHY_FLAG_MESH_AUTH;
++#endif
++	wdev->wiphy->interface_modes =
++		BIT(NL80211_IFTYPE_STATION)
++		| BIT(NL80211_IFTYPE_ADHOC)
++#if !defined(WL_ENABLE_P2P_IF) && !defined(WL_CFG80211_P2P_DEV_IF)
++		| BIT(NL80211_IFTYPE_MONITOR)
++#endif /* !WL_ENABLE_P2P_IF && !WL_CFG80211_P2P_DEV_IF */
++#if defined(WL_IFACE_COMB_NUM_CHANNELS) || defined(WL_CFG80211_P2P_DEV_IF)
++		| BIT(NL80211_IFTYPE_P2P_CLIENT)
++		| BIT(NL80211_IFTYPE_P2P_GO)
++#endif /* WL_IFACE_COMB_NUM_CHANNELS || WL_CFG80211_P2P_DEV_IF */
++#if defined(WL_CFG80211_P2P_DEV_IF)
++		| BIT(NL80211_IFTYPE_P2P_DEVICE)
++#endif /* WL_CFG80211_P2P_DEV_IF */
++#ifdef WLMESH_CFG80211
++		| BIT(NL80211_IFTYPE_MESH_POINT)
++#endif /* WLMESH_CFG80211 */
++		| BIT(NL80211_IFTYPE_AP);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) && \
++	(defined(WL_IFACE_COMB_NUM_CHANNELS) || defined(WL_CFG80211_P2P_DEV_IF))
++	WL_DBG(("Setting interface combinations for common mode\n"));
++	wdev->wiphy->iface_combinations = common_iface_combinations;
++	wdev->wiphy->n_iface_combinations =
++		ARRAY_SIZE(common_iface_combinations);
++#endif /* LINUX_VER >= 3.0 && (WL_IFACE_COMB_NUM_CHANNELS || WL_CFG80211_P2P_DEV_IF) */
++
++	wdev->wiphy->bands[IEEE80211_BAND_2GHZ] = &__wl_band_2ghz;
++
++	wdev->wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
++	wdev->wiphy->cipher_suites = __wl_cipher_suites;
++	wdev->wiphy->n_cipher_suites = ARRAY_SIZE(__wl_cipher_suites);
++	wdev->wiphy->max_remain_on_channel_duration = 5000;
++	wdev->wiphy->mgmt_stypes = wl_cfg80211_default_mgmt_stypes;
++#ifndef WL_POWERSAVE_DISABLED
++	wdev->wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT;
++#else
++	wdev->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
++#endif				/* !WL_POWERSAVE_DISABLED */
++	wdev->wiphy->flags |= WIPHY_FLAG_NETNS_OK |
++		WIPHY_FLAG_4ADDR_AP |
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39))
++		WIPHY_FLAG_SUPPORTS_SEPARATE_DEFAULT_KEYS |
++#endif
++		WIPHY_FLAG_4ADDR_STATION;
++#if ((defined(ROAM_ENABLE) || defined(BCMFW_ROAM_ENABLE)) && (LINUX_VERSION_CODE >= \
++	KERNEL_VERSION(3, 2, 0)))
++	/*
++	 * If FW ROAM flag is advertised, upper layer wouldn't provide
++	 * the bssid & freq in the connect command. This will result a
++	 * delay in initial connection time due to firmware doing a full
++	 * channel scan to figure out the channel & bssid. However kernel
++	 * ver >= 3.15, provides bssid_hint & freq_hint and hence kernel
++	 * ver >= 3.15 won't have any issue. So if this flags need to be
++	 * advertised for kernel < 3.15, suggest to use RCC along with it
++	 * to avoid the initial connection delay.
++	 */
++	wdev->wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM;
++#endif 
++#ifdef UNSET_FW_ROAM_WIPHY_FLAG
++	wdev->wiphy->flags &= ~WIPHY_FLAG_SUPPORTS_FW_ROAM;
++#endif /* UNSET_FW_ROAM_WIPHY_FLAG */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
++	wdev->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL |
++		WIPHY_FLAG_OFFCHAN_TX;
++#endif
++#if defined(WL_SUPPORT_BACKPORTED_KPATCHES) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, \
++	4, 0))
++	/* From 3.4 kernel ownards AP_SME flag can be advertised
++	 * to remove the patch from supplicant
++	 */
++	wdev->wiphy->flags |= WIPHY_FLAG_HAVE_AP_SME;
++
++#ifdef WL_CFG80211_ACL
++	/* Configure ACL capabilities. */
++	wdev->wiphy->max_acl_mac_addrs = MAX_NUM_MAC_FILT;
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
++	/* Supplicant distinguish between the SoftAP mode and other
++	 * modes (e.g. P2P, WPS, HS2.0) when it builds the probe
++	 * response frame from Supplicant MR1 and Kernel 3.4.0 or
++	 * later version. To add Vendor specific IE into the
++	 * probe response frame in case of SoftAP mode,
++	 * AP_PROBE_RESP_OFFLOAD flag is set to wiphy->flags variable.
++	 */
++	if (dhd_get_fw_mode(dhd->info) == DHD_FLAG_HOSTAP_MODE) {
++		wdev->wiphy->flags |= WIPHY_FLAG_AP_PROBE_RESP_OFFLOAD;
++		wdev->wiphy->probe_resp_offload = 0;
++	}
++#endif 
++#endif /* WL_SUPPORT_BACKPORTED_KPATCHES) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) */
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 2, 0))
++	wdev->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
++#endif
++
++#if defined(CONFIG_PM) && defined(WL_CFG80211_P2P_DEV_IF)
++	/*
++	 * From linux-3.10 kernel, wowlan packet filter is mandated to avoid the
++	 * disconnection of connected network before suspend. So a dummy wowlan
++	 * filter is configured for kernels linux-3.8 and above.
++	 */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++	wdev->wiphy->wowlan = &brcm_wowlan_support;
++	/* If this is not provided cfg stack will get disconnect
++	* during suspend.
++	*/
++	brcm_wowlan_config = kmalloc(sizeof(struct cfg80211_wowlan), GFP_KERNEL);
++	if (brcm_wowlan_config) {
++		brcm_wowlan_config->disconnect = true;
++		brcm_wowlan_config->gtk_rekey_failure = true;
++		brcm_wowlan_config->eap_identity_req = true;
++		brcm_wowlan_config->four_way_handshake = true;
++		brcm_wowlan_config->patterns = NULL;
++		brcm_wowlan_config->n_patterns = 0;
++		brcm_wowlan_config->tcp = NULL;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++		brcm_wowlan_config->nd_config = NULL;
++#endif
++	} else {
++		WL_ERR(("Can not allocate memory for brcm_wowlan_config,"
++			" So wiphy->wowlan_config is set to NULL\n"));
++	}
++	wdev->wiphy->wowlan_config = brcm_wowlan_config;
++#else
++	wdev->wiphy->wowlan.flags = WIPHY_WOWLAN_ANY;
++	wdev->wiphy->wowlan.n_patterns = WL_WOWLAN_MAX_PATTERNS;
++	wdev->wiphy->wowlan.pattern_min_len = WL_WOWLAN_MIN_PATTERN_LEN;
++	wdev->wiphy->wowlan.pattern_max_len = WL_WOWLAN_MAX_PATTERN_LEN;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++	wdev->wiphy->wowlan.max_pkt_offset = WL_WOWLAN_MAX_PATTERN_LEN;
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) */
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0) */
++#endif /* CONFIG_PM && WL_CFG80211_P2P_DEV_IF */
++
++	WL_DBG(("Registering custom regulatory)\n"));
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
++	wdev->wiphy->regulatory_flags |=
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++		REGULATORY_IGNORE_STALE_KICKOFF |
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0) */
++		REGULATORY_CUSTOM_REG;
++#else
++	wdev->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY;
++#endif
++	wiphy_apply_custom_regulatory(wdev->wiphy, &brcm_regdom);
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) || defined(WL_VENDOR_EXT_SUPPORT)
++	WL_ERR(("Registering Vendor80211\n"));
++	err = wl_cfgvendor_attach(wdev->wiphy, dhd);
++	if (unlikely(err < 0)) {
++		WL_ERR(("Couldn not attach vendor commands (%d)\n", err));
++	}
++#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) || defined(WL_VENDOR_EXT_SUPPORT) */
++
++	/* Now we can register wiphy with cfg80211 module */
++	err = wiphy_register(wdev->wiphy);
++	if (unlikely(err < 0)) {
++		WL_ERR(("Couldn not register wiphy device (%d)\n", err));
++		wiphy_free(wdev->wiphy);
++	}
++
++#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) && (LINUX_VERSION_CODE <= \
++	KERNEL_VERSION(3, 3, 0))) && defined(WL_IFACE_COMB_NUM_CHANNELS)
++	wdev->wiphy->flags &= ~WIPHY_FLAG_ENFORCE_COMBINATIONS;
++#endif
++
++#ifdef WL_SAE
++	WL_ERR(("SAE support\n"));
++	wdev->wiphy->features |= NL80211_FEATURE_SAE;
++#endif /* WL_SAE */
++
++	return err;
++}
++
++static void wl_free_wdev(struct bcm_cfg80211 *cfg)
++{
++	struct wireless_dev *wdev = cfg->wdev;
++	struct wiphy *wiphy = NULL;
++	if (!wdev) {
++		WL_ERR(("wdev is invalid\n"));
++		return;
++	}
++	if (wdev->wiphy) {
++		wiphy = wdev->wiphy;
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) || defined(WL_VENDOR_EXT_SUPPORT)
++		wl_cfgvendor_detach(wdev->wiphy);
++#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) || defined(WL_VENDOR_EXT_SUPPORT) */
++#if defined(CONFIG_PM) && defined(WL_CFG80211_P2P_DEV_IF)
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++		/* Reset wowlan & wowlan_config before Unregister to avoid  Kernel Panic */
++		WL_DBG(("wl_free_wdev Clearing wowlan Config \n"));
++		wdev->wiphy->wowlan = NULL;
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0) */
++#endif /* CONFIG_PM && WL_CFG80211_P2P_DEV_IF */
++		wiphy_unregister(wdev->wiphy);
++		wdev->wiphy->dev.parent = NULL;
++		wdev->wiphy = NULL;
++	}
++
++	wl_delete_all_netinfo(cfg);
++	if (wiphy)
++		wiphy_free(wiphy);
++
++	/* PLEASE do NOT call any function after wiphy_free, the driver's private structure "cfg",
++	 * which is the private part of wiphy, has been freed in wiphy_free !!!!!!!!!!!
++	 */
++}
++
++#if defined(BSSCACHE) || defined(RSSIAVG)
++void wl_cfg80211_update_bss_cache(struct bcm_cfg80211 *cfg)
++{
++#if defined(RSSIAVG)
++	int rssi;
++#endif
++	struct wl_scan_results *bss_list = cfg->bss_list;
++
++	/* Free cache in p2p scanning*/
++	if (p2p_is_on(cfg) && p2p_scan(cfg)) {
++#if defined(RSSIAVG)
++		wl_free_rssi_cache(&cfg->g_rssi_cache_ctrl);
++#endif
++#if defined(BSSCACHE)
++		wl_free_bss_cache(&cfg->g_bss_cache_ctrl);
++#endif
++	}
++
++	/* Delete disconnected cache */
++#if defined(BSSCACHE)
++	wl_delete_disconnected_bss_cache(&cfg->g_bss_cache_ctrl,
++		(u8*)&cfg->disconnected_bssid);
++#if defined(RSSIAVG)
++	wl_delete_disconnected_rssi_cache(&cfg->g_rssi_cache_ctrl,
++		(u8*)&cfg->disconnected_bssid);
++#endif
++	if (cfg->p2p_disconnected == 0)
++		memset(&cfg->disconnected_bssid, 0, ETHER_ADDR_LEN);
++#endif
++
++	/* Update cache */
++#if defined(RSSIAVG)
++	wl_update_rssi_cache(&cfg->g_rssi_cache_ctrl, bss_list);
++	if (!in_atomic())
++		wl_update_connected_rssi_cache(ndev, &cfg->g_rssi_cache_ctrl, &rssi);
++#endif
++#if defined(BSSCACHE)
++	wl_update_bss_cache(&cfg->g_bss_cache_ctrl,
++#if defined(RSSIAVG)
++		&cfg->g_rssi_cache_ctrl,
++#endif
++		bss_list);
++#endif
++
++	/* delete dirty cache */
++#if defined(RSSIAVG)
++	wl_delete_dirty_rssi_cache(&cfg->g_rssi_cache_ctrl);
++	wl_reset_rssi_cache(&cfg->g_rssi_cache_ctrl);
++#endif
++#if defined(BSSCACHE)
++	wl_delete_dirty_bss_cache(&cfg->g_bss_cache_ctrl);
++	wl_reset_bss_cache(&cfg->g_bss_cache_ctrl);
++#endif
++
++}
++#endif
++
++#if defined(BSSCACHE)
++s32 wl_inform_bss_cache(struct bcm_cfg80211 *cfg)
++{
++	struct wl_scan_results *bss_list = cfg->bss_list;
++	wl_bss_info_t *bi = NULL;	/* must be initialized */
++	s32 err = 0;
++	s32 i;
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++#if defined(BSSCACHE)
++	wl_bss_cache_t *node;
++#endif
++
++	if (cfg->p2p_disconnected > 0) {
++		// terence 20130703: Fix for wrong group_capab (timing issue)
++		wl_delete_disconnected_bss_cache(&cfg->g_bss_cache_ctrl, (u8*)&cfg->disconnected_bssid);
++#if defined(RSSIAVG)
++		wl_delete_disconnected_rssi_cache(&cfg->g_rssi_cache_ctrl, (u8*)&cfg->disconnected_bssid);
++#endif
++	}
++	WL_SCAN(("scanned AP count (%d)\n", bss_list->count));
++	node = cfg->g_bss_cache_ctrl.m_cache_head;
++	for (i=0; node && i<WL_AP_MAX; i++) {
++		bi = node->results.bss_info;
++		err = wl_inform_single_bss(cfg, bi, false);
++		node = node->next;
++	}
++	if (cfg->autochannel)
++		wl_ext_get_best_channel(ndev, &cfg->g_bss_cache_ctrl, ioctl_version,
++			&cfg->best_2g_ch, &cfg->best_5g_ch);
++
++	return err;
++}
++#endif
++
++s32 wl_inform_bss(struct bcm_cfg80211 *cfg)
++{
++#if !defined(BSSCACHE)
++	struct wl_scan_results *bss_list;
++	struct wl_bss_info *bi = NULL;	/* must be initialized */
++	s32 i;
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++#endif
++	s32 err = 0;
++
++#if defined(BSSCACHE) || defined(RSSIAVG)
++	wl_cfg80211_update_bss_cache(cfg);
++#endif
++
++#if defined(BSSCACHE)
++	err = wl_inform_bss_cache(cfg);
++#else
++	bss_list = cfg->bss_list;
++	WL_SCAN(("scanned AP count (%d)\n", bss_list->count));
++	preempt_disable();
++	bi = next_bss(bss_list, bi);
++	for_each_bss(bss_list, bi, i) {
++		if (cfg->p2p_disconnected > 0 &&
++				!memcmp(&bi->BSSID, &cfg->disconnected_bssid, ETHER_ADDR_LEN)) {
++			WL_SCAN(("Skip %pM\n", &bi->BSSID));
++			continue;
++		}
++		err = wl_inform_single_bss(cfg, bi, false);
++	}
++	preempt_enable();
++	if (cfg->autochannel)
++		wl_ext_get_best_channel(ndev, bss_list, ioctl_version,
++			&cfg->best_2g_ch, &cfg->best_5g_ch);
++#endif
++
++	if (cfg->p2p_disconnected > 0) {
++		// terence 20130703: Fix for wrong group_capab (timing issue)
++		cfg->p2p_disconnected++;
++		if (cfg->p2p_disconnected >= 2) {
++			cfg->p2p_disconnected = 0;
++			memset(&cfg->disconnected_bssid, 0, ETHER_ADDR_LEN);
++		}
++	}
++
++	return err;
++}
++
++static s32 wl_inform_single_bss(struct bcm_cfg80211 *cfg, struct wl_bss_info *bi, bool roam)
++{
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	struct ieee80211_mgmt *mgmt;
++	struct ieee80211_channel *channel;
++	struct ieee80211_supported_band *band;
++	struct wl_cfg80211_bss_info *notif_bss_info;
++	struct wl_scan_req *sr = wl_to_sr(cfg);
++	struct beacon_proberesp *beacon_proberesp;
++	struct cfg80211_bss *cbss = NULL;
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++	log_conn_event_t *event_data = NULL;
++	tlv_log *tlv_data = NULL;
++	u32 alloc_len, tlv_len;
++	u32 payload_len;
++	s32 mgmt_type;
++	s32 signal;
++	u32 freq;
++	s32 err = 0;
++	gfp_t aflags;
++	chanspec_t chanspec;
++
++	if (unlikely(dtoh32(bi->length) > WL_BSS_INFO_MAX)) {
++		WL_DBG(("Beacon is larger than buffer. Discarding\n"));
++		return err;
++	}
++	aflags = (in_atomic()) ? GFP_ATOMIC : GFP_KERNEL;
++	notif_bss_info = kzalloc(sizeof(*notif_bss_info) + sizeof(*mgmt)
++		- sizeof(u8) + WL_BSS_INFO_MAX, aflags);
++	if (unlikely(!notif_bss_info)) {
++		WL_ERR(("notif_bss_info alloc failed\n"));
++		return -ENOMEM;
++	}
++	mgmt = (struct ieee80211_mgmt *)notif_bss_info->frame_buf;
++	chanspec = wl_chspec_driver_to_host(bi->chanspec);
++	notif_bss_info->channel = wf_chspec_ctlchan(chanspec);
++
++	if (notif_bss_info->channel <= CH_MAX_2G_CHANNEL)
++		band = wiphy->bands[IEEE80211_BAND_2GHZ];
++	else
++		band = wiphy->bands[IEEE80211_BAND_5GHZ];
++	if (!band) {
++		WL_ERR(("No valid band\n"));
++		kfree(notif_bss_info);
++		return -EINVAL;
++	}
++	notif_bss_info->rssi = dtoh16(bi->RSSI);
++#if defined(RSSIAVG)
++	notif_bss_info->rssi = wl_get_avg_rssi(&cfg->g_rssi_cache_ctrl, &bi->BSSID);
++	if (notif_bss_info->rssi == RSSI_MINVAL)
++		notif_bss_info->rssi = MIN(dtoh16(bi->RSSI), RSSI_MAXVAL);
++#endif
++#if defined(RSSIOFFSET)
++	notif_bss_info->rssi = wl_update_rssi_offset(bcmcfg_to_prmry_ndev(cfg), notif_bss_info->rssi);
++#endif
++#if !defined(RSSIAVG) && !defined(RSSIOFFSET)
++	// terence 20150419: limit the max. rssi to -2 or the bss will be filtered out in android OS
++	notif_bss_info->rssi = MIN(notif_bss_info->rssi, RSSI_MAXVAL);
++#endif
++	memcpy(mgmt->bssid, &bi->BSSID, ETHER_ADDR_LEN);
++	mgmt_type = cfg->active_scan ?
++		IEEE80211_STYPE_PROBE_RESP : IEEE80211_STYPE_BEACON;
++	if (!memcmp(bi->SSID, sr->ssid.SSID, bi->SSID_len)) {
++	    mgmt->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | mgmt_type);
++	}
++	beacon_proberesp = cfg->active_scan ?
++		(struct beacon_proberesp *)&mgmt->u.probe_resp :
++		(struct beacon_proberesp *)&mgmt->u.beacon;
++	beacon_proberesp->timestamp = 0;
++	beacon_proberesp->beacon_int = cpu_to_le16(bi->beacon_period);
++	beacon_proberesp->capab_info = cpu_to_le16(bi->capability);
++	wl_rst_ie(cfg);
++	wl_update_hidden_ap_ie(bi, ((u8 *) bi) + bi->ie_offset, &bi->ie_length, roam);
++	wl_mrg_ie(cfg, ((u8 *) bi) + bi->ie_offset, bi->ie_length);
++	wl_cp_ie(cfg, beacon_proberesp->variable, WL_BSS_INFO_MAX -
++		offsetof(struct wl_cfg80211_bss_info, frame_buf));
++	notif_bss_info->frame_len = offsetof(struct ieee80211_mgmt,
++		u.beacon.variable) + wl_get_ielen(cfg);
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39)
++	freq = ieee80211_channel_to_frequency(notif_bss_info->channel);
++	(void)band->band;
++#else
++	freq = ieee80211_channel_to_frequency(notif_bss_info->channel, band->band);
++#endif
++	if (freq == 0) {
++		WL_ERR(("Invalid channel, fail to change channel to freq\n"));
++		kfree(notif_bss_info);
++		return -EINVAL;
++	}
++	channel = ieee80211_get_channel(wiphy, freq);
++	WL_SCAN(("BSSID %pM, channel %3d(%3d %sMHz), rssi %3d, capa 0x04%x, mgmt_type %d, "
++		"frame_len %d, SSID \"%s\"\n",
++		&bi->BSSID, notif_bss_info->channel, CHSPEC_CHANNEL(chanspec),
++		CHSPEC_IS20(chanspec)?"20":
++		CHSPEC_IS40(chanspec)?"40":
++		CHSPEC_IS80(chanspec)?"80":"160",
++		notif_bss_info->rssi, mgmt->u.beacon.capab_info, mgmt_type,
++		notif_bss_info->frame_len, bi->SSID));
++	if (unlikely(!channel)) {
++		WL_ERR(("ieee80211_get_channel error, freq=%d, channel=%d\n",
++			freq, notif_bss_info->channel));
++		kfree(notif_bss_info);
++		return -EINVAL;
++	}
++
++	signal = notif_bss_info->rssi * 100;
++	if (!mgmt->u.probe_resp.timestamp) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39))
++		struct osl_timespec ts;
++		osl_get_monotonic_boottime(&ts);
++		mgmt->u.probe_resp.timestamp = ((u64)ts.tv_sec*1000000)
++				+ ts.tv_nsec / 1000;
++#else
++		struct timeval tv;
++		do_gettimeofday(&tv);
++		mgmt->u.probe_resp.timestamp = ((u64)tv.tv_sec*1000000)
++				+ tv.tv_usec;
++#endif
++	}
++
++
++	cbss = cfg80211_inform_bss_frame(wiphy, channel, mgmt,
++		le16_to_cpu(notif_bss_info->frame_len), signal, aflags);
++	if (unlikely(!cbss)) {
++		WL_ERR(("cfg80211_inform_bss_frame error\n"));
++		err = -EINVAL;
++		goto out_err;
++	}
++
++	CFG80211_PUT_BSS(wiphy, cbss);
++
++	if (DBG_RING_ACTIVE(dhdp, DHD_EVENT_RING_ID) &&
++			(cfg->sched_scan_req && !cfg->scan_request)) {
++		alloc_len = sizeof(log_conn_event_t) + IEEE80211_MAX_SSID_LEN + sizeof(uint16) +
++			sizeof(int16);
++		event_data = MALLOCZ(dhdp->osh, alloc_len);
++		if (!event_data) {
++			WL_ERR(("%s: failed to allocate the log_conn_event_t with "
++				"length(%d)\n", __func__, alloc_len));
++			goto out_err;
++		}
++		tlv_len = 3 * sizeof(tlv_log);
++		event_data->tlvs = MALLOC(dhdp->osh, tlv_len);
++		if (!event_data->tlvs) {
++			WL_ERR(("%s: failed to allocate the log_conn_event_t with "
++						"length(%d)\n", __func__, tlv_len));
++			goto out_err;
++		}
++
++		payload_len = sizeof(log_conn_event_t);
++		event_data->event = WIFI_EVENT_DRIVER_PNO_SCAN_RESULT_FOUND;
++		tlv_data = event_data->tlvs;
++
++		/* ssid */
++		tlv_data->tag = WIFI_TAG_SSID;
++		tlv_data->len = bi->SSID_len;
++		memcpy(tlv_data->value, bi->SSID, bi->SSID_len);
++		payload_len += TLV_LOG_SIZE(tlv_data);
++		tlv_data = TLV_LOG_NEXT(tlv_data);
++
++		/* channel */
++		tlv_data->tag = WIFI_TAG_CHANNEL;
++		tlv_data->len = sizeof(uint16);
++		memcpy(tlv_data->value, &notif_bss_info->channel, sizeof(uint16));
++		payload_len += TLV_LOG_SIZE(tlv_data);
++		tlv_data = TLV_LOG_NEXT(tlv_data);
++
++		/* rssi */
++		tlv_data->tag = WIFI_TAG_RSSI;
++		tlv_data->len = sizeof(int16);
++		memcpy(tlv_data->value, &notif_bss_info->rssi, sizeof(int16));
++		payload_len += TLV_LOG_SIZE(tlv_data);
++		tlv_data = TLV_LOG_NEXT(tlv_data);
++
++		dhd_os_push_push_ring_data(dhdp, DHD_EVENT_RING_ID,
++				event_data, payload_len);
++		MFREE(dhdp->osh, event_data->tlvs, tlv_len);
++		MFREE(dhdp->osh, event_data, alloc_len);
++	}
++
++out_err:
++	kfree(notif_bss_info);
++	return err;
++}
++
++static bool wl_is_linkup(struct bcm_cfg80211 *cfg, const wl_event_msg_t *e, struct net_device *ndev)
++{
++	u32 event = ntoh32(e->event_type);
++	u32 status =  ntoh32(e->status);
++	u16 flags = ntoh16(e->flags);
++#if defined(CUSTOM_SET_ANTNPM) || defined(CUSTOM_SET_OCLOFF)
++	dhd_pub_t *dhd;
++	dhd = (dhd_pub_t *)(cfg->pub);
++#endif /* CUSTOM_SET_ANTNPM */
++
++	WL_DBG(("event %d, status %d flags %x\n", event, status, flags));
++	if (event == WLC_E_SET_SSID) {
++		if (status == WLC_E_STATUS_SUCCESS) {
++#ifdef CUSTOM_SET_ANTNPM
++			if (dhd->mimo_ant_set) {
++				int err = 0;
++
++				WL_ERR(("[WIFI_SEC] mimo_ant_set = %d\n", dhd->mimo_ant_set));
++				err = wldev_iovar_setint(ndev, "txchain", dhd->mimo_ant_set);
++				if (err != 0) {
++					WL_ERR(("[WIFI_SEC] Fail set txchain\n"));
++				}
++				err = wldev_iovar_setint(ndev, "rxchain", dhd->mimo_ant_set);
++				if (err != 0) {
++					WL_ERR(("[WIFI_SEC] Fail set rxchain\n"));
++				}
++			}
++#endif /* CUSTOM_SET_ANTNPM */
++#ifdef CUSTOM_SET_OCLOFF
++			if (dhd->ocl_off) {
++				int err = 0;
++				int ocl_enable = 0;
++				err = wldev_iovar_setint(ndev, "ocl_enable", ocl_enable);
++				if (err != 0) {
++					WL_ERR(("[WIFI_SEC] %s: Set ocl_enable %d failed %d\n",
++						__FUNCTION__, ocl_enable, err));
++				} else {
++					WL_ERR(("[WIFI_SEC] %s: Set ocl_enable %d succeeded %d\n",
++						__FUNCTION__, ocl_enable, err));
++				}
++			}
++#endif /* CUSTOM_SET_OCLOFF */
++			if (!wl_is_ibssmode(cfg, ndev))
++				return true;
++		}
++	} else if (event == WLC_E_LINK) {
++		if (flags & WLC_EVENT_MSG_LINK)
++			return true;
++	}
++
++	WL_DBG(("wl_is_linkup false\n"));
++	return false;
++}
++
++#ifdef WL_LASTEVT
++static bool wl_is_linkdown(struct bcm_cfg80211 *cfg, const wl_event_msg_t *e, void *data)
++{
++	u32 event = ntoh32(e->event_type);
++	u16 flags = ntoh16(e->flags);
++	wl_last_event_t *last_event = (wl_last_event_t *)data;
++	u32 len = ntoh32(e->datalen);
++
++	if (event == WLC_E_DEAUTH_IND ||
++	event == WLC_E_DISASSOC_IND ||
++	event == WLC_E_DISASSOC ||
++	event == WLC_E_DEAUTH) {
++		WL_ERR(("Link down Reason : %s\n", bcmevent_get_name(event)));
++		return true;
++	} else if (event == WLC_E_LINK) {
++		if (!(flags & WLC_EVENT_MSG_LINK)) {
++			if (last_event && len > 0) {
++				u32 current_time = last_event->current_time;
++				u32 timestamp = last_event->timestamp;
++				u32 event_type = last_event->event.event_type;
++				u32 status = last_event->event.status;
++				u32 reason = last_event->event.reason;
++
++				WL_ERR(("Last roam event before disconnection : current_time %d,"
++					" time %d, type %d, status %d, reason %d\n",
++					current_time, timestamp, event_type, status, reason));
++			}
++			WL_ERR(("Link down Reason : %s\n", bcmevent_get_name(event)));
++			return true;
++		}
++	}
++
++	return false;
++}
++#else
++static bool wl_is_linkdown(struct bcm_cfg80211 *cfg, const wl_event_msg_t *e)
++{
++	u32 event = ntoh32(e->event_type);
++	u16 flags = ntoh16(e->flags);
++
++	if (event == WLC_E_DEAUTH_IND ||
++	event == WLC_E_DISASSOC_IND ||
++	event == WLC_E_DISASSOC ||
++	event == WLC_E_DEAUTH) {
++		WL_ERR(("Link down Reason : %s\n", bcmevent_get_name(event)));
++		return true;
++	} else if (event == WLC_E_LINK) {
++		if (!(flags & WLC_EVENT_MSG_LINK)) {
++			WL_ERR(("Link down Reason : %s\n", bcmevent_get_name(event)));
++			return true;
++		}
++	}
++
++	return false;
++}
++#endif /* WL_LASTEVT */
++
++static bool wl_is_nonetwork(struct bcm_cfg80211 *cfg, const wl_event_msg_t *e)
++{
++	u32 event = ntoh32(e->event_type);
++	u32 status = ntoh32(e->status);
++
++	if (event == WLC_E_LINK && status == WLC_E_STATUS_NO_NETWORKS)
++		return true;
++	if (event == WLC_E_SET_SSID && status != WLC_E_STATUS_SUCCESS)
++		return true;
++
++	return false;
++}
++
++#ifdef WL_SAE
++static s32
++wl_cfg80211_event_sae_key(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	wl_sae_key_info_t *sae_key)
++{
++	struct sk_buff *skb;
++	gfp_t kflags;
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	int err = BCME_OK;
++
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++#if (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || \
++	LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
++	skb = cfg80211_vendor_event_alloc(wiphy, ndev_to_wdev(ndev), BRCM_SAE_VENDOR_EVENT_BUF_LEN,
++		BRCM_VENDOR_EVENT_SAE_KEY, kflags);
++#else
++	skb = cfg80211_vendor_event_alloc(wiphy, BRCM_SAE_VENDOR_EVENT_BUF_LEN,
++		BRCM_VENDOR_EVENT_SAE_KEY, kflags);
++#endif /* (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || */
++		/* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) */
++	if (!skb) {
++		WL_ERR(("skb alloc failed"));
++		err = BCME_NOMEM;
++		goto done;
++	}
++
++	WL_INFORM(("Received Sae Key event for "MACDBG" key length %x %x",
++		MAC2STRDBG(sae_key->peer_mac), sae_key->pmk_len, sae_key->pmkid_len));
++	nla_put(skb, BRCM_SAE_KEY_ATTR_PEER_MAC, ETHER_ADDR_LEN, sae_key->peer_mac);
++	nla_put(skb, BRCM_SAE_KEY_ATTR_PMK, sae_key->pmk_len, sae_key->pmk);
++	nla_put(skb, BRCM_SAE_KEY_ATTR_PMKID, sae_key->pmkid_len, sae_key->pmkid);
++	cfg80211_vendor_event(skb, kflags);
++
++done:
++	return err;
++}
++
++static s32
++wl_bss_handle_sae_auth(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *event, void *data)
++{
++	int err = BCME_OK;
++	uint status = ntoh32(event->status);
++	wl_auth_event_t *auth_data;
++	wl_sae_key_info_t sae_key;
++	uint16 tlv_buf_len;
++
++	if (status == WLC_E_STATUS_SUCCESS) {
++		auth_data = (wl_auth_event_t *)data;
++		if (auth_data->version != WL_AUTH_EVENT_DATA_V1) {
++			WL_ERR(("unknown auth event data version %x\n",
++				auth_data->version));
++			err = BCME_VERSION;
++			goto done;
++		}
++
++		tlv_buf_len = auth_data->length - WL_AUTH_EVENT_FIXED_LEN_V1;
++
++		/* check if PMK info present */
++		sae_key.pmk = bcm_get_data_from_xtlv_buf(auth_data->xtlvs, tlv_buf_len,
++			WL_AUTH_PMK_TLV_ID, &(sae_key.pmk_len), BCM_XTLV_OPTION_ALIGN32);
++		if (!sae_key.pmk || !sae_key.pmk_len) {
++			WL_ERR(("Mandatory PMK info not present"));
++			err = BCME_NOTFOUND;
++			goto done;
++		}
++		/* check if PMKID info present */
++		sae_key.pmkid = bcm_get_data_from_xtlv_buf(auth_data->xtlvs, tlv_buf_len,
++			WL_AUTH_PMKID_TLV_ID, &(sae_key.pmkid_len), BCM_XTLV_OPTION_ALIGN32);
++		if (!sae_key.pmkid || !sae_key.pmkid_len) {
++			WL_ERR(("Mandatory PMKID info not present\n"));
++			err = BCME_NOTFOUND;
++			goto done;
++		}
++		memcpy(sae_key.peer_mac, event->addr.octet, ETHER_ADDR_LEN);
++		err = wl_cfg80211_event_sae_key(cfg, ndev, &sae_key);
++		if (err) {
++			WL_ERR(("Failed to event sae key info\n"));
++		}
++	} else {
++		WL_ERR(("sae auth status failure:%d\n", status));
++	}
++done:
++	return err;
++}
++#endif /* WL_SAE */
++
++static s32
++wl_get_auth_assoc_status(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data)
++{
++	u32 reason = ntoh32(e->reason);
++	u32 event = ntoh32(e->event_type);
++	uint auth_type = ntoh32(e->auth_type);
++	struct wl_security *sec = wl_read_prof(cfg, ndev, WL_PROF_SEC);
++
++	WL_DBG(("event type : %d, reason : %d, auth_type : %d\n", event, reason, auth_type));
++
++#if defined(DHD_ENABLE_BIGDATA_LOGGING)
++	memcpy(&cfg->event_auth_assoc, e, sizeof(wl_event_msg_t));
++	WL_ERR(("event=%d status %d reason %d \n",
++		ntoh32(cfg->event_auth_assoc.event_type),
++		ntoh32(cfg->event_auth_assoc.status),
++		ntoh32(cfg->event_auth_assoc.reason)));
++#endif /* DHD_ENABLE_BIGDATA_LOGGING */
++	if (sec) {
++		switch (event) {
++		case WLC_E_ASSOC:
++		case WLC_E_AUTH:
++			sec->auth_assoc_res_status = reason;
++#ifdef WL_SAE
++			if (event == WLC_E_AUTH && auth_type == DOT11_SAE) {
++				wl_bss_handle_sae_auth(cfg, ndev, e, data);
++			}
++#endif /* WL_SAE */
++		default:
++			break;
++		}
++	} else
++		WL_ERR(("sec is NULL\n"));
++	return 0;
++}
++
++/* The mainline kernel >= 3.2.0 has support for indicating new/del station
++ * to AP/P2P GO via events. If this change is backported to kernel for which
++ * this driver is being built, then define WL_CFG80211_STA_EVENT. You
++ * should use this new/del sta event mechanism for BRCM supplicant >= 22.
++ */
++static s32
++wl_notify_connect_status_ap(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data)
++{
++	s32 err = 0;
++	u32 event = ntoh32(e->event_type);
++	u32 reason = ntoh32(e->reason);
++	u32 len = ntoh32(e->datalen);
++	u32 status = ntoh32(e->status);
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0)) && !defined(WL_CFG80211_STA_EVENT)
++	bool isfree = false;
++	u8 *mgmt_frame;
++	u8 bsscfgidx = e->bsscfgidx;
++	s32 freq;
++	s32 channel;
++	u8 *body = NULL;
++	u16 fc = 0;
++
++	struct ieee80211_supported_band *band;
++	struct ether_addr da;
++	struct ether_addr bssid;
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	channel_info_t ci;
++#else
++	struct station_info sinfo;
++#endif 
++
++	WL_DBG(("event %d status %d reason %d\n", event, ntoh32(e->status), reason));
++#ifdef WL_SAE
++	if (event == WLC_E_AUTH_IND)
++		wl_get_auth_assoc_status(cfg, ndev, e, data);
++#endif /* WL_SAE */
++	/* if link down, bsscfg is disabled. */
++	if (event == WLC_E_LINK && reason == WLC_E_LINK_BSSCFG_DIS &&
++		wl_get_p2p_status(cfg, IF_DELETING) && (ndev != bcmcfg_to_prmry_ndev(cfg))) {
++		wl_add_remove_eventmsg(ndev, WLC_E_PROBREQ_MSG, false);
++		WL_MSG(ndev->name, "AP mode link down !! \n");
++		complete(&cfg->iface_disable);
++		return 0;
++	}
++
++	if ((event == WLC_E_LINK) && (status == WLC_E_STATUS_SUCCESS) &&
++		(reason == WLC_E_REASON_INITIAL_ASSOC) &&
++		(wl_get_mode_by_netdev(cfg, ndev) == WL_MODE_AP)) {
++		if (!wl_get_drv_status(cfg, AP_CREATED, ndev)) {
++			/* AP/GO brought up successfull in firmware */
++			WL_MSG(ndev->name, "AP/GO Link up\n");
++			wl_set_drv_status(cfg, AP_CREATED, ndev);
++			wake_up_interruptible(&cfg->netif_change_event);
++			wl_cfg80211_check_in4way(cfg, ndev, 0, WL_EXT_STATUS_AP_ENABLED, NULL);
++			return 0;
++		}
++	}
++
++	if (event == WLC_E_DISASSOC_IND || event == WLC_E_DEAUTH_IND || event == WLC_E_DEAUTH) {
++		WL_MSG_RLMT(ndev->name, &e->addr, ETHER_ADDR_LEN,
++			"event %s(%d) status %d reason %d\n",
++			bcmevent_get_name(event), event, ntoh32(e->status), reason);
++	}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0)) && !defined(WL_CFG80211_STA_EVENT)
++	WL_DBG(("Enter \n"));
++	if (!len && (event == WLC_E_DEAUTH)) {
++		len = 2; /* reason code field */
++		data = &reason;
++	}
++	if (len) {
++		body = kzalloc(len, GFP_KERNEL);
++
++		if (body == NULL) {
++			WL_ERR(("Failed to allocate body\n"));
++			return WL_INVALID;
++		}
++	}
++	memset(&bssid, 0, ETHER_ADDR_LEN);
++	WL_DBG(("Enter event %d ndev %p\n", event, ndev));
++	if (wl_get_mode_by_netdev(cfg, ndev) == WL_INVALID) {
++		kfree(body);
++		return WL_INVALID;
++	}
++	if (len)
++		memcpy(body, data, len);
++
++	wldev_iovar_getbuf_bsscfg(ndev, "cur_etheraddr",
++		NULL, 0, cfg->ioctl_buf, WLC_IOCTL_SMLEN, bsscfgidx, &cfg->ioctl_buf_sync);
++	memcpy(da.octet, cfg->ioctl_buf, ETHER_ADDR_LEN);
++	memset(&bssid, 0, sizeof(bssid));
++	err = wldev_ioctl_get(ndev, WLC_GET_BSSID, &bssid, ETHER_ADDR_LEN);
++	switch (event) {
++		case WLC_E_ASSOC_IND:
++			fc = FC_ASSOC_REQ;
++			break;
++		case WLC_E_REASSOC_IND:
++			fc = FC_REASSOC_REQ;
++			break;
++		case WLC_E_DISASSOC_IND:
++			fc = FC_DISASSOC;
++			break;
++		case WLC_E_DEAUTH_IND:
++			fc = FC_DISASSOC;
++			break;
++		case WLC_E_DEAUTH:
++			fc = FC_DISASSOC;
++			break;
++		default:
++			fc = 0;
++			goto exit;
++	}
++	memset(&ci, 0, sizeof(ci));
++	if ((err = wldev_ioctl_get(ndev, WLC_GET_CHANNEL, &ci, sizeof(ci)))) {
++		kfree(body);
++		return err;
++	}
++
++	channel = dtoh32(ci.hw_channel);
++	if (channel <= CH_MAX_2G_CHANNEL)
++		band = wiphy->bands[IEEE80211_BAND_2GHZ];
++	else
++		band = wiphy->bands[IEEE80211_BAND_5GHZ];
++	if (!band) {
++		WL_ERR(("No valid band\n"));
++		if (body)
++			kfree(body);
++		return -EINVAL;
++	}
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39)
++	freq = ieee80211_channel_to_frequency(channel);
++	(void)band->band;
++#else
++	freq = ieee80211_channel_to_frequency(channel, band->band);
++#endif
++
++	err = wl_frame_get_mgmt(fc, &da, &e->addr, &bssid,
++		&mgmt_frame, &len, body);
++	if (err < 0)
++		goto exit;
++	isfree = true;
++
++	if ((event == WLC_E_ASSOC_IND && reason == DOT11_SC_SUCCESS) ||
++			(event == WLC_E_DISASSOC_IND) ||
++			((event == WLC_E_DEAUTH_IND) || (event == WLC_E_DEAUTH))) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
++		cfg80211_rx_mgmt(ndev, freq, 0, mgmt_frame, len, 0);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 12, 0))
++		cfg80211_rx_mgmt(ndev, freq, 0, mgmt_frame, len, 0, GFP_ATOMIC);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) || \
++		defined(WL_COMPAT_WIRELESS)
++		cfg80211_rx_mgmt(ndev, freq, 0, mgmt_frame, len, GFP_ATOMIC);
++#else
++		cfg80211_rx_mgmt(ndev, freq, mgmt_frame, len, GFP_ATOMIC);
++#endif 
++	}
++
++exit:
++	if (isfree)
++		kfree(mgmt_frame);
++	if (body)
++		kfree(body);
++#else /* LINUX_VERSION < VERSION(3,2,0) && !WL_CFG80211_STA_EVENT && !WL_COMPAT_WIRELESS */
++	memset(&sinfo, 0, sizeof(struct station_info));
++	sinfo.filled = 0;
++	if (((event == WLC_E_ASSOC_IND) || (event == WLC_E_REASSOC_IND)) &&
++		reason == DOT11_SC_SUCCESS) {
++		/* Linux ver >= 4.0 assoc_req_ies_len is used instead of
++		 * STATION_INFO_ASSOC_REQ_IES flag
++		 */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))
++		sinfo.filled = STA_INFO_BIT(INFO_ASSOC_REQ_IES);
++#endif /*  (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) */
++		if (!data) {
++			WL_ERR(("No IEs present in ASSOC/REASSOC_IND"));
++			return -EINVAL;
++		}
++		sinfo.assoc_req_ies = data;
++		sinfo.assoc_req_ies_len = len;
++		WL_MSG(ndev->name, "connected device "MACDBG"\n", MAC2STRDBG(e->addr.octet));
++		wl_cfg80211_check_in4way(cfg, ndev, DONT_DELETE_GC_AFTER_WPS,
++			WL_EXT_STATUS_STA_CONNECTED, NULL);
++		cfg80211_new_sta(ndev, e->addr.octet, &sinfo, GFP_ATOMIC);
++	} else if (event == WLC_E_DISASSOC_IND) {
++		WL_MSG(ndev->name, "disassociated device "MACDBG"\n", MAC2STRDBG(e->addr.octet));
++		wl_cfg80211_check_in4way(cfg, ndev, DONT_DELETE_GC_AFTER_WPS,
++			WL_EXT_STATUS_STA_DISCONNECTED, NULL);
++		cfg80211_del_sta(ndev, e->addr.octet, GFP_ATOMIC);
++	} else if ((event == WLC_E_DEAUTH_IND) ||
++		((event == WLC_E_DEAUTH) && (reason != DOT11_RC_RESERVED))) {
++		WL_MSG_RLMT(ndev->name, &e->addr, ETHER_ADDR_LEN,
++			"deauthenticated device "MACDBG"\n", MAC2STRDBG(e->addr.octet));
++		wl_cfg80211_check_in4way(cfg, ndev, DONT_DELETE_GC_AFTER_WPS,
++			WL_EXT_STATUS_STA_DISCONNECTED, NULL);
++		cfg80211_del_sta(ndev, e->addr.octet, GFP_ATOMIC);
++	}
++#endif 
++	return err;
++}
++
++#if defined(DHD_ENABLE_BIGDATA_LOGGING)
++#define MAX_ASSOC_REJECT_ERR_STATUS 5
++int wl_get_connect_failed_status(struct bcm_cfg80211 *cfg, const wl_event_msg_t *e)
++{
++	u32 status = ntoh32(e->status);
++
++	cfg->assoc_reject_status = 0;
++
++	if (status == WLC_E_STATUS_FAIL) {
++		WL_ERR(("auth assoc status event=%d e->status %d e->reason %d \n",
++			ntoh32(cfg->event_auth_assoc.event_type),
++			(int)ntoh32(cfg->event_auth_assoc.status),
++			(int)ntoh32(cfg->event_auth_assoc.reason)));
++
++		switch ((int)ntoh32(cfg->event_auth_assoc.status)) {
++			case WLC_E_STATUS_NO_ACK:
++				cfg->assoc_reject_status = 1;
++				break;
++			case WLC_E_STATUS_FAIL:
++				cfg->assoc_reject_status = 2;
++				break;
++			case WLC_E_STATUS_UNSOLICITED:
++				cfg->assoc_reject_status = 3;
++				break;
++			case WLC_E_STATUS_TIMEOUT:
++				cfg->assoc_reject_status = 4;
++				break;
++			case WLC_E_STATUS_ABORT:
++				cfg->assoc_reject_status = 5;
++				break;
++			default:
++				break;
++		}
++		if (cfg->assoc_reject_status) {
++			if (ntoh32(cfg->event_auth_assoc.event_type) == WLC_E_ASSOC) {
++				cfg->assoc_reject_status += MAX_ASSOC_REJECT_ERR_STATUS;
++			}
++		}
++	}
++
++	WL_ERR(("assoc_reject_status %d \n", cfg->assoc_reject_status));
++
++	return 0;
++}
++
++s32 wl_cfg80211_get_connect_failed_status(struct net_device *dev, char* cmd, int total_len)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	int bytes_written = 0;
++
++	if (cfg == NULL) {
++		return -1;
++	}
++
++	memset(cmd, 0, total_len);
++	bytes_written = snprintf(cmd, 30, "assoc_reject.status %d", cfg->assoc_reject_status);
++
++	WL_ERR(("cmd: %s \n", cmd));
++
++	return bytes_written;
++}
++#endif /* DHD_ENABLE_BIGDATA_LOGGING */
++
++static s32
++wl_notify_connect_status_ibss(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data)
++{
++	s32 err = 0;
++	u32 event = ntoh32(e->event_type);
++	u16 flags = ntoh16(e->flags);
++	u32 status =  ntoh32(e->status);
++	bool active;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)
++	struct ieee80211_channel *channel = NULL;
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	u32 chanspec, chan;
++	u32 freq, band;
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0) */
++
++	if (event == WLC_E_JOIN) {
++		WL_DBG(("joined in IBSS network\n"));
++	}
++	if (event == WLC_E_START) {
++		WL_DBG(("started IBSS network\n"));
++	}
++	if (event == WLC_E_JOIN || event == WLC_E_START ||
++		(event == WLC_E_LINK && (flags == WLC_EVENT_MSG_LINK))) {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)
++		err = wldev_iovar_getint(ndev, "chanspec", (s32 *)&chanspec);
++		if (unlikely(err)) {
++			WL_ERR(("Could not get chanspec %d\n", err));
++			return err;
++		}
++		chan = wf_chspec_ctlchan(wl_chspec_driver_to_host(chanspec));
++		band = (chan <= CH_MAX_2G_CHANNEL) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
++		freq = ieee80211_channel_to_frequency(chan, band);
++		channel = ieee80211_get_channel(wiphy, freq);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0) */
++		if (wl_get_drv_status(cfg, CONNECTED, ndev)) {
++			/* ROAM or Redundant */
++			u8 *cur_bssid = wl_read_prof(cfg, ndev, WL_PROF_BSSID);
++			if (memcmp(cur_bssid, &e->addr, ETHER_ADDR_LEN) == 0) {
++				WL_DBG(("IBSS connected event from same BSSID("
++					MACDBG "), ignore it\n", MAC2STRDBG(cur_bssid)));
++				return err;
++			}
++			WL_INFORM(("IBSS BSSID is changed from " MACDBG " to " MACDBG "\n",
++				MAC2STRDBG(cur_bssid), MAC2STRDBG((const u8 *)&e->addr)));
++			wl_get_assoc_ies(cfg, ndev);
++			wl_update_prof(cfg, ndev, NULL, (const void *)&e->addr, WL_PROF_BSSID);
++			wl_update_bss_info(cfg, ndev, false);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)
++			cfg80211_ibss_joined(ndev, (const s8 *)&e->addr, channel, GFP_KERNEL);
++#else
++			cfg80211_ibss_joined(ndev, (const s8 *)&e->addr, GFP_KERNEL);
++#endif
++		}
++		else {
++			/* New connection */
++			WL_INFORM(("IBSS connected to " MACDBG "\n",
++				MAC2STRDBG((const u8 *)&e->addr)));
++			wl_link_up(cfg);
++			wl_get_assoc_ies(cfg, ndev);
++			wl_update_prof(cfg, ndev, NULL, (const void *)&e->addr, WL_PROF_BSSID);
++			wl_update_bss_info(cfg, ndev, false);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)
++			cfg80211_ibss_joined(ndev, (const s8 *)&e->addr, channel, GFP_KERNEL);
++#else
++			cfg80211_ibss_joined(ndev, (const s8 *)&e->addr, GFP_KERNEL);
++#endif
++			wl_set_drv_status(cfg, CONNECTED, ndev);
++			active = true;
++			wl_update_prof(cfg, ndev, NULL, (const void *)&active, WL_PROF_ACT);
++		}
++	} else if ((event == WLC_E_LINK && !(flags & WLC_EVENT_MSG_LINK)) ||
++		event == WLC_E_DEAUTH_IND || event == WLC_E_DISASSOC_IND) {
++		wl_clr_drv_status(cfg, CONNECTED, ndev);
++		wl_link_down(cfg);
++		wl_init_prof(cfg, ndev);
++	}
++	else if (event == WLC_E_SET_SSID && status == WLC_E_STATUS_NO_NETWORKS) {
++		WL_DBG(("no action - join fail (IBSS mode)\n"));
++	}
++	else {
++		WL_DBG(("no action (IBSS mode)\n"));
++}
++	return err;
++}
++
++#if defined(DHD_ENABLE_BIGDATA_LOGGING)
++#define WiFiALL_OUI         "\x50\x6F\x9A"  /* Wi-FiAll OUI */
++#define WiFiALL_OUI_LEN     3
++#define WiFiALL_OUI_TYPE    16
++
++int wl_get_bss_info(struct bcm_cfg80211 *cfg, struct net_device *dev, uint8 *mac)
++{
++	s32 err = 0;
++	struct wl_bss_info *bi;
++	uint8 eabuf[ETHER_ADDR_LEN];
++	u32 rate, channel, freq, supported_rate, nss = 0, mcs_map, mode_80211 = 0;
++	char rate_str[4];
++	u8 *ie = NULL;
++	u32 ie_len;
++	struct wiphy *wiphy;
++	struct cfg80211_bss *bss;
++	bcm_tlv_t *interworking_ie = NULL;
++	bcm_tlv_t *tlv_ie = NULL;
++	bcm_tlv_t *vht_ie = NULL;
++	vndr_ie_t *vndrie;
++	int16 ie_11u_rel_num = -1, ie_mu_mimo_cap = -1;
++	u32 i, remained_len, count = 0;
++	char roam_count_str[4], akm_str[4];
++	s32 val = 0;
++
++	/* get BSS information */
++
++	strncpy(cfg->bss_info, "x x x x x x x x x x x x x", GET_BSS_INFO_LEN);
++
++	memset(cfg->extra_buf, 0, WL_EXTRA_BUF_MAX);
++	*(u32 *) cfg->extra_buf = htod32(WL_EXTRA_BUF_MAX);
++
++	err = wldev_ioctl_get(dev, WLC_GET_BSS_INFO, cfg->extra_buf, WL_EXTRA_BUF_MAX);
++	if (unlikely(err)) {
++		WL_ERR(("Could not get bss info %d\n", err));
++		cfg->roam_count = 0;
++		return -1;
++	}
++
++	if (!mac) {
++		WL_ERR(("mac is null \n"));
++		cfg->roam_count = 0;
++		return -1;
++	}
++
++	memcpy(eabuf, mac, ETHER_ADDR_LEN);
++
++	bi = (struct wl_bss_info *)(cfg->extra_buf + 4);
++	channel = wf_chspec_ctlchan(bi->chanspec);
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39)
++	freq = ieee80211_channel_to_frequency(channel);
++#else
++	if (channel > 14) {
++		freq = ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ);
++	} else {
++		freq = ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ);
++	}
++#endif
++	rate = 0;
++	err = wldev_ioctl_get(dev, WLC_GET_RATE, &rate, sizeof(rate));
++	if (err) {
++		WL_ERR(("Could not get rate (%d)\n", err));
++		snprintf(rate_str, sizeof(rate_str), "x"); // Unknown
++
++	} else {
++		rate = dtoh32(rate);
++		snprintf(rate_str, sizeof(rate_str), "%d", (rate/2));
++	}
++
++	//supported maximum rate
++	supported_rate = (bi->rateset.rates[bi->rateset.count - 1] & 0x7f) / 2;
++
++	if (supported_rate < 12) {
++		mode_80211 = 0; //11b maximum rate is 11Mbps. 11b mode
++	} else {
++		//It's not HT Capable case.
++		if (channel > 14) {
++			mode_80211 = 3; // 11a mode
++		} else {
++			mode_80211 = 1; // 11g mode
++		}
++	}
++
++	if (bi->n_cap) {
++		/* check Rx MCS Map for HT */
++		nss = 0;
++		mode_80211 = 2;
++		for (i = 0; i < MAX_STREAMS_SUPPORTED; i++) {
++			int8 bitmap = 0xFF;
++			if (i == MAX_STREAMS_SUPPORTED-1) {
++				bitmap = 0x7F;
++			}
++			if (bi->basic_mcs[i] & bitmap) {
++				nss++;
++			}
++		}
++	}
++
++	if (bi->vht_cap) {
++		nss = 0;
++		mode_80211 = 4;
++		for (i = 1; i <= VHT_CAP_MCS_MAP_NSS_MAX; i++) {
++			mcs_map = VHT_MCS_MAP_GET_MCS_PER_SS(i, dtoh16(bi->vht_rxmcsmap));
++			if (mcs_map != VHT_CAP_MCS_MAP_NONE) {
++				nss++;
++			}
++		}
++	}
++
++	if (nss) {
++		nss = nss - 1;
++	}
++
++	wiphy = bcmcfg_to_wiphy(cfg);
++	bss = CFG80211_GET_BSS(wiphy, NULL, eabuf, bi->SSID, bi->SSID_len);
++	if (!bss) {
++		WL_ERR(("Could not find the AP\n"));
++	} else {
++#if defined(WL_CFG80211_P2P_DEV_IF)
++		ie = (u8 *)bss->ies->data;
++		ie_len = bss->ies->len;
++#else
++		ie = bss->information_elements;
++		ie_len = bss->len_information_elements;
++#endif /* WL_CFG80211_P2P_DEV_IF */
++	}
++
++	if (ie) {
++		ie_mu_mimo_cap = 0;
++		ie_11u_rel_num = 0;
++
++		if (bi->vht_cap) {
++			if ((vht_ie = bcm_parse_tlvs(ie, (u32)ie_len,
++					DOT11_MNG_VHT_CAP_ID)) != NULL) {
++				ie_mu_mimo_cap = (vht_ie->data[2] & 0x08) >> 3;
++			}
++		}
++
++		if ((interworking_ie = bcm_parse_tlvs(ie, (u32)ie_len,
++				DOT11_MNG_INTERWORKING_ID)) != NULL) {
++			if ((tlv_ie = bcm_parse_tlvs(ie, (u32)ie_len, DOT11_MNG_VS_ID)) != NULL) {
++				remained_len = ie_len;
++
++				while (tlv_ie) {
++					if (count > MAX_VNDR_IE_NUMBER)
++						break;
++
++					if (tlv_ie->id == DOT11_MNG_VS_ID) {
++						vndrie = (vndr_ie_t *) tlv_ie;
++
++						if (vndrie->len < (VNDR_IE_MIN_LEN + 1)) {
++							WL_ERR(("%s: invalid vndr ie."
++								"length is too small %d\n",
++								__FUNCTION__, vndrie->len));
++							break;
++						}
++
++						if (!bcmp(vndrie->oui,
++							(u8*)WiFiALL_OUI, WiFiALL_OUI_LEN) &&
++							(vndrie->data[0] == WiFiALL_OUI_TYPE))
++						{
++							WL_ERR(("Found Wi-FiAll OUI oui.\n"));
++							ie_11u_rel_num = vndrie->data[1];
++							ie_11u_rel_num = (ie_11u_rel_num & 0xf0)>>4;
++							ie_11u_rel_num += 1;
++
++							break;
++						}
++					}
++					count++;
++					tlv_ie = bcm_next_tlv(tlv_ie, &remained_len);
++				}
++			}
++		}
++	}
++
++	for (i = 0; i < bi->SSID_len; i++) {
++		if (bi->SSID[i] == ' ') {
++			bi->SSID[i] = '_';
++		}
++	}
++
++	//0 : None, 1 : OKC, 2 : FT, 3 : CCKM
++	err = wldev_iovar_getint(dev, "wpa_auth", &val);
++	if (unlikely(err)) {
++		WL_ERR(("could not get wpa_auth (%d)\n", err));
++		snprintf(akm_str, sizeof(akm_str), "x"); // Unknown
++	} else {
++		WL_ERR(("wpa_auth val %d \n", val));
++#if defined(BCMEXTCCX)
++		if (val & (WPA_AUTH_CCKM | WPA2_AUTH_CCKM)) {
++			snprintf(akm_str, sizeof(akm_str), "3");
++		} else
++#endif  
++		if (val & WPA2_AUTH_FT) {
++			snprintf(akm_str, sizeof(akm_str), "2");
++		} else if (val & (WPA_AUTH_UNSPECIFIED | WPA2_AUTH_UNSPECIFIED)) {
++			snprintf(akm_str, sizeof(akm_str), "1");
++		} else {
++			snprintf(akm_str, sizeof(akm_str), "0");
++		}
++	}
++
++	if (cfg->roam_offload) {
++		snprintf(roam_count_str, sizeof(roam_count_str), "x"); // Unknown
++	} else {
++		snprintf(roam_count_str, sizeof(roam_count_str), "%d", cfg->roam_count);
++	}
++	cfg->roam_count = 0;
++
++	WL_ERR(("BSSID:" MACDBG " SSID %s \n", MAC2STRDBG(eabuf), bi->SSID));
++	WL_ERR(("freq:%d, BW:%s, RSSI:%d dBm, Rate:%d Mbps, 11mode:%d, stream:%d,"
++				"MU-MIMO:%d, Passpoint:%d, SNR:%d, Noise:%d, \n"
++				"akm:%s roam:%s \n",
++				freq, wf_chspec_to_bw_str(bi->chanspec),
++				dtoh32(bi->RSSI), (rate / 2), mode_80211, nss,
++				ie_mu_mimo_cap, ie_11u_rel_num, bi->SNR, bi->phy_noise,
++				akm_str, roam_count_str));
++
++	if (ie) {
++		snprintf(cfg->bss_info, GET_BSS_INFO_LEN,
++				"%02x:%02x:%02x %d %s %d %s %d %d %d %d %d %d %s %s",
++				eabuf[0], eabuf[1], eabuf[2],
++				freq, wf_chspec_to_bw_str(bi->chanspec),
++				dtoh32(bi->RSSI), rate_str, mode_80211, nss,
++				ie_mu_mimo_cap, ie_11u_rel_num,
++				bi->SNR, bi->phy_noise, akm_str, roam_count_str);
++	} else {
++		//ie_mu_mimo_cap and ie_11u_rel_num is unknow.
++		snprintf(cfg->bss_info, GET_BSS_INFO_LEN,
++				"%02x:%02x:%02x %d %s %d %s %d %d x x %d %d %s %s",
++				eabuf[0], eabuf[1], eabuf[2],
++				freq, wf_chspec_to_bw_str(bi->chanspec),
++				dtoh32(bi->RSSI), rate_str, mode_80211, nss,
++				bi->SNR, bi->phy_noise, akm_str, roam_count_str);
++	}
++
++	CFG80211_PUT_BSS(wiphy, bss);
++
++	return 0;
++}
++
++s32 wl_cfg80211_get_bss_info(struct net_device *dev, char* cmd, int total_len)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++
++	if (cfg == NULL) {
++		return -1;
++	}
++
++	memset(cmd, 0, total_len);
++	memcpy(cmd, cfg->bss_info, GET_BSS_INFO_LEN);
++
++	WL_ERR(("cmd: %s \n", cmd));
++
++	return GET_BSS_INFO_LEN;
++}
++
++#endif /* DHD_ENABLE_BIGDATA_LOGGING */
++
++#ifdef WLMESH_CFG80211
++static s32
++wl_notify_connect_status_mesh(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data)
++{
++	s32 err = 0;
++	u32 event = ntoh32(e->event_type);
++	u32 reason = ntoh32(e->reason);
++	u32 len = ntoh32(e->datalen);
++	u32 status = ntoh32(e->status);
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0)) && !defined(WL_CFG80211_STA_EVENT)
++	bool isfree = false;
++	u8 *mgmt_frame;
++	u8 bsscfgidx = e->bsscfgidx;
++	s32 freq;
++	s32 channel;
++	u8 *body = NULL;
++	u16 fc = 0;
++
++	struct ieee80211_supported_band *band;
++	struct ether_addr da;
++	struct ether_addr bssid;
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	channel_info_t ci;
++#else
++	struct station_info sinfo;
++#endif 
++
++	WL_DBG(("event %d status %d reason %d\n", event, ntoh32(e->status), reason));
++	/* if link down, bsscfg is disabled. */
++	if (event == WLC_E_LINK && reason == WLC_E_LINK_BSSCFG_DIS &&
++			(ndev != bcmcfg_to_prmry_ndev(cfg))) {
++		WL_MSG(ndev->name, "Mesh mode link down !! \n");
++		return 0;
++	}
++
++	if ((event == WLC_E_LINK) && (status == WLC_E_STATUS_SUCCESS) &&
++			(reason == WLC_E_REASON_INITIAL_ASSOC)) {
++		/* AP/GO brought up successfull in firmware */
++		WL_MSG(ndev->name, "Mesh Link up\n");
++		return 0;
++	}
++
++	if (event == WLC_E_DISASSOC_IND || event == WLC_E_DEAUTH_IND || event == WLC_E_DEAUTH) {
++		WL_MSG(ndev->name, "event %s(%d) status %d reason %d\n",
++		bcmevent_get_name(event), event, ntoh32(e->status), reason);
++	}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0)) && !defined(WL_CFG80211_STA_EVENT)
++	WL_DBG(("Enter \n"));
++	if (!len && (event == WLC_E_DEAUTH)) {
++		len = 2; /* reason code field */
++		data = &reason;
++	}
++	if (len) {
++		body = kzalloc(len, GFP_KERNEL);
++
++		if (body == NULL) {
++			WL_ERR(("Failed to allocate body\n"));
++			return WL_INVALID;
++		}
++	}
++	memset(&bssid, 0, ETHER_ADDR_LEN);
++	WL_DBG(("Enter event %d ndev %p\n", event, ndev));
++	if (wl_get_mode_by_netdev(cfg, ndev) == WL_INVALID) {
++		kfree(body);
++		return WL_INVALID;
++	}
++	if (len)
++		memcpy(body, data, len);
++
++	wldev_iovar_getbuf_bsscfg(ndev, "cur_etheraddr",
++		NULL, 0, cfg->ioctl_buf, WLC_IOCTL_SMLEN, bsscfgidx, &cfg->ioctl_buf_sync);
++	memcpy(da.octet, cfg->ioctl_buf, ETHER_ADDR_LEN);
++	memset(&bssid, 0, sizeof(bssid));
++	err = wldev_ioctl_get(ndev, WLC_GET_BSSID, &bssid, ETHER_ADDR_LEN);
++	switch (event) {
++		case WLC_E_ASSOC_IND:
++			fc = FC_ASSOC_REQ;
++			break;
++		case WLC_E_REASSOC_IND:
++			fc = FC_REASSOC_REQ;
++			break;
++		case WLC_E_DISASSOC_IND:
++			fc = FC_DISASSOC;
++			break;
++		case WLC_E_DEAUTH_IND:
++			fc = FC_DISASSOC;
++			break;
++		case WLC_E_DEAUTH:
++			fc = FC_DISASSOC;
++			break;
++		default:
++			fc = 0;
++			goto exit;
++	}
++	memset(&ci, 0, sizeof(ci));
++	if ((err = wldev_ioctl_get(ndev, WLC_GET_CHANNEL, &ci, sizeof(ci)))) {
++		kfree(body);
++		return err;
++	}
++
++	channel = dtoh32(ci.hw_channel);
++	if (channel <= CH_MAX_2G_CHANNEL)
++		band = wiphy->bands[IEEE80211_BAND_2GHZ];
++	else
++		band = wiphy->bands[IEEE80211_BAND_5GHZ];
++	if (!band) {
++		WL_ERR(("No valid band\n"));
++		if (body)
++			kfree(body);
++		return -EINVAL;
++	}
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39)
++	freq = ieee80211_channel_to_frequency(channel);
++	(void)band->band;
++#else
++	freq = ieee80211_channel_to_frequency(channel, band->band);
++#endif
++
++	err = wl_frame_get_mgmt(fc, &da, &e->addr, &bssid,
++		&mgmt_frame, &len, body);
++	if (err < 0)
++		goto exit;
++	isfree = true;
++
++	if ((event == WLC_E_ASSOC_IND && reason == DOT11_SC_SUCCESS) ||
++			(event == WLC_E_DISASSOC_IND) ||
++			((event == WLC_E_DEAUTH_IND) || (event == WLC_E_DEAUTH))) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
++		cfg80211_rx_mgmt(ndev, freq, 0, mgmt_frame, len, 0);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 12, 0))
++		cfg80211_rx_mgmt(ndev, freq, 0, mgmt_frame, len, 0, GFP_ATOMIC);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) || \
++		defined(WL_COMPAT_WIRELESS)
++		cfg80211_rx_mgmt(ndev, freq, 0, mgmt_frame, len, GFP_ATOMIC);
++#else
++		cfg80211_rx_mgmt(ndev, freq, mgmt_frame, len, GFP_ATOMIC);
++#endif 
++	}
++
++exit:
++	if (isfree)
++		kfree(mgmt_frame);
++	if (body)
++		kfree(body);
++#else /* LINUX_VERSION < VERSION(3,2,0) && !WL_CFG80211_STA_EVENT && !WL_COMPAT_WIRELESS */
++	memset(&sinfo, 0, sizeof(struct station_info));
++	sinfo.filled = 0;
++	if (((event == WLC_E_ASSOC_IND) || (event == WLC_E_REASSOC_IND)) &&
++		reason == DOT11_SC_SUCCESS) {
++		/* Linux ver >= 4.0 assoc_req_ies_len is used instead of
++		 * STATION_INFO_ASSOC_REQ_IES flag
++		 */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))
++		sinfo.filled = STA_INFO_BIT(INFO_ASSOC_REQ_IES);
++#endif /*  (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) */
++		if (!data) {
++			WL_ERR(("No IEs present in ASSOC/REASSOC_IND"));
++			return -EINVAL;
++		}
++		sinfo.assoc_req_ies = data;
++		sinfo.assoc_req_ies_len = len;
++		WL_MSG(ndev->name, "connected device "MACDBG"\n", MAC2STRDBG(e->addr.octet));
++		cfg80211_new_sta(ndev, e->addr.octet, &sinfo, GFP_ATOMIC);
++	} else if (event == WLC_E_DISASSOC_IND) {
++		WL_MSG(ndev->name, "disassociated device "MACDBG"\n", MAC2STRDBG(e->addr.octet));
++		cfg80211_del_sta(ndev, e->addr.octet, GFP_ATOMIC);
++	} else if ((event == WLC_E_DEAUTH_IND) ||
++		((event == WLC_E_DEAUTH) && (reason != DOT11_RC_RESERVED))) {
++		WL_MSG(ndev->name, "deauthenticated device "MACDBG"\n", MAC2STRDBG(e->addr.octet));
++		cfg80211_del_sta(ndev, e->addr.octet, GFP_ATOMIC);
++	}
++#endif 
++	return err;
++}
++#endif
++
++static s32
++wl_notify_connect_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	bool act;
++	struct net_device *ndev = NULL;
++	s32 err = 0;
++	u32 event = ntoh32(e->event_type);
++	struct wiphy *wiphy = NULL;
++	struct cfg80211_bss *bss = NULL;
++	struct wlc_ssid *ssid = NULL;
++	u8 *bssid = 0;
++	dhd_pub_t *dhdp;
++	int vndr_oui_num = 0;
++	char vndr_oui[MAX_VNDR_OUI_STR_LEN] = {0, };
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++	dhdp = (dhd_pub_t *)(cfg->pub);
++	BCM_REFERENCE(dhdp);
++
++	if (wl_get_mode_by_netdev(cfg, ndev) == WL_MODE_AP) {
++		err = wl_notify_connect_status_ap(cfg, ndev, e, data);
++#ifdef WLMESH_CFG80211
++	} else if (wl_get_mode_by_netdev(cfg, ndev) == WL_MODE_MESH) {
++		err = wl_notify_connect_status_mesh(cfg, ndev, e, data);
++#endif
++	} else if (wl_get_mode_by_netdev(cfg, ndev) == WL_MODE_IBSS) {
++		err = wl_notify_connect_status_ibss(cfg, ndev, e, data);
++	} else if (wl_get_mode_by_netdev(cfg, ndev) == WL_MODE_BSS) {
++		WL_DBG(("event %d status : %d ndev %p\n",
++			ntoh32(e->event_type), ntoh32(e->status), ndev));
++		if (event == WLC_E_ASSOC || event == WLC_E_AUTH) {
++			wl_get_auth_assoc_status(cfg, ndev, e, data);
++			return 0;
++		}
++		DHD_DISABLE_RUNTIME_PM((dhd_pub_t *)cfg->pub);
++		if (wl_is_linkup(cfg, e, ndev)) {
++			wl_link_up(cfg);
++			act = true;
++			if (!wl_get_drv_status(cfg, DISCONNECTING, ndev)) {
++				if (event == WLC_E_LINK &&
++#ifdef DHD_LOSSLESS_ROAMING
++					!cfg->roam_offload &&
++#endif /* DHD_LOSSLESS_ROAMING */
++					wl_get_drv_status(cfg, CONNECTED, ndev)) {
++					wl_bss_roaming_done(cfg, ndev, e, data);
++				}
++
++				if (ndev == bcmcfg_to_prmry_ndev(cfg)) {
++					vndr_oui_num = wl_vndr_ies_get_vendor_oui(cfg,
++						ndev, vndr_oui, ARRAYSIZE(vndr_oui));
++#if defined(STAT_REPORT)
++					/* notify STA connection only */
++					wl_stat_report_notify_connected(cfg);
++#endif /* STAT_REPORT */
++				}
++
++				WL_MSG(ndev->name, "wl_bss_connect_done succeeded with "
++					MACDBG " %s%s\n", MAC2STRDBG((const u8*)(&e->addr)),
++					vndr_oui_num > 0 ? "vndr_oui: " : "",
++					vndr_oui_num > 0 ? vndr_oui : "");
++
++				wl_bss_connect_done(cfg, ndev, e, data, true);
++				WL_DBG(("joined in BSS network \"%s\"\n",
++					((struct wlc_ssid *)
++					 wl_read_prof(cfg, ndev, WL_PROF_SSID))->SSID));
++
++#ifdef WBTEXT
++				if (ndev->ieee80211_ptr->iftype == NL80211_IFTYPE_STATION &&
++					dhdp->wbtext_support &&
++					event == WLC_E_SET_SSID) {
++					/* set wnm_keepalives_max_idle after association */
++					wl_cfg80211_wbtext_set_wnm_maxidle(cfg, ndev);
++					/* send nbr request or BTM query to update RCC */
++					wl_cfg80211_wbtext_update_rcc(cfg, ndev);
++				}
++#endif /* WBTEXT */
++			}
++			wl_update_prof(cfg, ndev, e, &act, WL_PROF_ACT);
++			wl_update_prof(cfg, ndev, NULL, (const void *)&e->addr, WL_PROF_BSSID);
++		} else if (WL_IS_LINKDOWN(cfg, e, data) ||
++				((event == WLC_E_SET_SSID) &&
++				(ntoh32(e->status) != WLC_E_STATUS_SUCCESS) &&
++				(wl_get_drv_status(cfg, CONNECTED, ndev)))) {
++
++			WL_INFORM(("connection state bit status: [%d:%d:%d:%d]\n",
++				wl_get_drv_status(cfg, CONNECTING, ndev),
++				wl_get_drv_status(cfg, CONNECTED, ndev),
++				wl_get_drv_status(cfg, DISCONNECTING, ndev),
++				wl_get_drv_status(cfg, NESTED_CONNECT, ndev)));
++
++			if (wl_get_drv_status(cfg, DISCONNECTING, ndev) &&
++				(wl_get_drv_status(cfg, NESTED_CONNECT, ndev) ||
++				wl_get_drv_status(cfg, CONNECTING, ndev))) {
++				/* wl_cfg80211_connect was called before 'DISCONNECTING' was
++				 * cleared. Deauth/Link down event is caused by WLC_DISASSOC
++				 * command issued from the wl_cfg80211_connect context. Ignore
++				 * the event to avoid pre-empting the current connection
++				 */
++				WL_INFORM(("Nested connection case. Drop event. \n"));
++				wl_cfg80211_check_in4way(cfg, ndev, NO_SCAN_IN4WAY|NO_BTC_IN4WAY|WAIT_DISCONNECTED,
++					WL_EXT_STATUS_DISCONNECTED, NULL);
++				wl_clr_drv_status(cfg, NESTED_CONNECT, ndev);
++				wl_clr_drv_status(cfg, DISCONNECTING, ndev);
++				/* Not in 'CONNECTED' state, clear it */
++				wl_clr_drv_status(cfg, CONNECTED, ndev);
++				return 0;
++			}
++
++#ifdef DHD_LOSSLESS_ROAMING
++			wl_del_roam_timeout(cfg);
++#endif
++#ifdef P2PLISTEN_AP_SAMECHN
++			if (ndev == bcmcfg_to_prmry_ndev(cfg)) {
++				wl_cfg80211_set_p2p_resp_ap_chn(ndev, 0);
++				cfg->p2p_resp_apchn_status = false;
++				WL_DBG(("p2p_resp_apchn_status Turn OFF \n"));
++			}
++#endif /* P2PLISTEN_AP_SAMECHN */
++			wl_cfg80211_cancel_scan(cfg);
++
++#if defined(DHD_ENABLE_BIGDATA_LOGGING)
++			if (wl_get_drv_status(cfg, CONNECTED, ndev)) {
++				wl_get_bss_info(cfg, ndev, (u8*)(&e->addr));
++			}
++#endif /* DHD_ENABLE_BIGDATA_LOGGING */
++			if (wl_get_drv_status(cfg, CONNECTED, ndev)) {
++				u8 *curbssid = wl_read_prof(cfg, ndev, WL_PROF_BSSID);
++				if (memcmp(curbssid, &e->addr, ETHER_ADDR_LEN) != 0) {
++					bool fw_assoc_state = TRUE;
++					dhd_pub_t *dhd = (dhd_pub_t *)cfg->pub;
++					fw_assoc_state = dhd_is_associated(dhd, e->ifidx, &err);
++					if (!fw_assoc_state) {
++						WL_ERR(("Event sends up even different BSSID"
++							" cur: " MACDBG " event: " MACDBG"\n",
++							MAC2STRDBG(curbssid),
++							MAC2STRDBG((const u8*)(&e->addr))));
++					} else {
++						WL_ERR(("BSSID of event is not the connected BSSID"
++							"(ignore it) cur: " MACDBG
++							" event: " MACDBG"\n",
++							MAC2STRDBG(curbssid),
++							MAC2STRDBG((const u8*)(&e->addr))));
++						return 0;
++					}
++				}
++			}
++			/* Explicitly calling unlink to remove BSS in CFG */
++			wiphy = bcmcfg_to_wiphy(cfg);
++			ssid = (struct wlc_ssid *)wl_read_prof(cfg, ndev, WL_PROF_SSID);
++			bssid = (u8 *)wl_read_prof(cfg, ndev, WL_PROF_BSSID);
++			if (ssid && bssid) {
++				bss = CFG80211_GET_BSS(wiphy, NULL, bssid,
++					ssid->SSID, ssid->SSID_len);
++				if (bss) {
++					cfg80211_unlink_bss(wiphy, bss);
++					CFG80211_PUT_BSS(wiphy, bss);
++				}
++			}
++
++			if (wl_get_drv_status(cfg, CONNECTED, ndev)) {
++				scb_val_t scbval;
++				u8 *curbssid = wl_read_prof(cfg, ndev, WL_PROF_BSSID);
++				s32 reason = 0;
++				struct ether_addr bssid_dongle = {{0, 0, 0, 0, 0, 0}};
++				struct ether_addr bssid_null = {{0, 0, 0, 0, 0, 0}};
++
++				if (event == WLC_E_DEAUTH_IND || event == WLC_E_DISASSOC_IND)
++					reason = ntoh32(e->reason);
++				/* WLAN_REASON_UNSPECIFIED is used for hang up event in Android */
++				reason = (reason == WLAN_REASON_UNSPECIFIED)? 0 : reason;
++
++				WL_MSG(ndev->name, "link down if %s may call cfg80211_disconnected. "
++					"event : %d, reason=%d from " MACDBG "\n",
++					ndev->name, event, ntoh32(e->reason),
++					MAC2STRDBG((const u8*)(&e->addr)));
++
++				/* roam offload does not sync BSSID always, get it from dongle */
++				if (cfg->roam_offload) {
++					memset(&bssid_dongle, 0, sizeof(bssid_dongle));
++					if (wldev_ioctl_get(ndev, WLC_GET_BSSID, &bssid_dongle,
++							sizeof(bssid_dongle)) == BCME_OK) {
++						/* if not roam case, it would return null bssid */
++						if (memcmp(&bssid_dongle, &bssid_null,
++								ETHER_ADDR_LEN) != 0) {
++							curbssid = (u8 *)&bssid_dongle;
++						}
++					}
++				}
++				if (memcmp(curbssid, &e->addr, ETHER_ADDR_LEN) != 0) {
++					bool fw_assoc_state = TRUE;
++					dhd_pub_t *dhd = (dhd_pub_t *)cfg->pub;
++					fw_assoc_state = dhd_is_associated(dhd, e->ifidx, &err);
++					if (!fw_assoc_state) {
++						WL_ERR(("Event sends up even different BSSID"
++							" cur: " MACDBG " event: " MACDBG"\n",
++							MAC2STRDBG(curbssid),
++							MAC2STRDBG((const u8*)(&e->addr))));
++					} else {
++						WL_ERR(("BSSID of event is not the connected BSSID"
++							"(ignore it) cur: " MACDBG
++							" event: " MACDBG"\n",
++							MAC2STRDBG(curbssid),
++							MAC2STRDBG((const u8*)(&e->addr))));
++						return 0;
++					}
++				}
++
++#ifdef DBG_PKT_MON
++				if (ndev == bcmcfg_to_prmry_ndev(cfg)) {
++					DHD_DBG_PKT_MON_STOP(dhdp);
++				}
++#endif /* DBG_PKT_MON */
++
++				/* clear RSSI monitor, framework will set new cfg */
++#ifdef RSSI_MONITOR_SUPPORT
++				dhd_dev_set_rssi_monitor_cfg(bcmcfg_to_prmry_ndev(cfg),
++				    FALSE, 0, 0);
++#endif /* RSSI_MONITOR_SUPPORT */
++				if (!memcmp(ndev->name, WL_P2P_INTERFACE_PREFIX, strlen(WL_P2P_INTERFACE_PREFIX))) {
++					// terence 20130703: Fix for wrong group_capab (timing issue)
++					cfg->p2p_disconnected = 1;
++				}
++				memcpy(&cfg->disconnected_bssid, curbssid, ETHER_ADDR_LEN);
++				wl_clr_drv_status(cfg, CONNECTED, ndev);
++
++				if (!wl_get_drv_status(cfg, DISCONNECTING, ndev)) {
++					/* To make sure disconnect, explictly send dissassoc
++					*  for BSSID 00:00:00:00:00:00 issue
++					*/
++					scbval.val = WLAN_REASON_DEAUTH_LEAVING;
++
++					memcpy(&scbval.ea, curbssid, ETHER_ADDR_LEN);
++					scbval.val = htod32(scbval.val);
++					err = wldev_ioctl_set(ndev, WLC_DISASSOC, &scbval,
++						sizeof(scb_val_t));
++					if (err < 0) {
++						WL_ERR(("WLC_DISASSOC error %d\n", err));
++						err = 0;
++					}
++				}
++
++				/* Send up deauth and clear states */
++				CFG80211_DISCONNECTED(ndev, reason, NULL, 0,
++						false, GFP_KERNEL);
++				wl_link_down(cfg);
++				wl_init_prof(cfg, ndev);
++#ifdef WBTEXT
++				/* when STA was disconnected, clear join pref and set wbtext */
++				if (ndev->ieee80211_ptr->iftype == NL80211_IFTYPE_STATION) {
++					char smbuf[WLC_IOCTL_SMLEN];
++					char clear[] = { 0x01, 0x02, 0x00, 0x00, 0x03,
++						0x02, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00 };
++					if ((err = wldev_iovar_setbuf(ndev, "join_pref",
++							clear, sizeof(clear), smbuf,
++							sizeof(smbuf), NULL))
++							== BCME_OK) {
++						if ((err = wldev_iovar_setint(ndev,
++								"wnm_bsstrans_resp",
++								WL_BSSTRANS_POLICY_PRODUCT_WBTEXT))
++								== BCME_OK) {
++							wl_cfg80211_wbtext_set_default(ndev);
++						} else {
++							WL_ERR(("%s: Failed to set wbtext = %d\n",
++								__FUNCTION__, err));
++						}
++					} else {
++						WL_ERR(("%s: Failed to clear join pref = %d\n",
++							__FUNCTION__, err));
++					}
++					wl_cfg80211_wbtext_clear_bssid_list(cfg);
++				}
++#endif /* WBTEXT */
++				wl_vndr_ies_clear_vendor_oui_list(cfg);
++			}
++			else if (wl_get_drv_status(cfg, CONNECTING, ndev)) {
++				WL_MSG(ndev->name, "link down, during connecting\n");
++				/* Issue WLC_DISASSOC to prevent FW roam attempts */
++				err = wldev_ioctl_set(ndev, WLC_DISASSOC, NULL, 0);
++				if (err < 0) {
++					WL_ERR(("CONNECTING state, WLC_DISASSOC error %d\n", err));
++					err = 0;
++				}
++#ifdef ESCAN_RESULT_PATCH
++				if ((memcmp(connect_req_bssid, broad_bssid, ETHER_ADDR_LEN) == 0) ||
++					(memcmp(&e->addr, broad_bssid, ETHER_ADDR_LEN) == 0) ||
++					(memcmp(&e->addr, connect_req_bssid, ETHER_ADDR_LEN) == 0))
++					/* In case this event comes while associating another AP */
++#endif /* ESCAN_RESULT_PATCH */
++					wl_bss_connect_done(cfg, ndev, e, data, false);
++				WL_INFORM(("Clear drv CONNECTING status\n"));
++				wl_clr_drv_status(cfg, CONNECTING, ndev);
++			}
++			wl_clr_drv_status(cfg, DISCONNECTING, ndev);
++			wl_cfg80211_check_in4way(cfg, ndev, NO_SCAN_IN4WAY|NO_BTC_IN4WAY|WAIT_DISCONNECTED,
++				WL_EXT_STATUS_DISCONNECTED, NULL);
++
++			/* if link down, bsscfg is diabled */
++			if (ndev != bcmcfg_to_prmry_ndev(cfg))
++				complete(&cfg->iface_disable);
++#ifdef WLTDLS
++			/* re-enable TDLS if the number of connected interfaces
++			 * is less than 2.
++			 */
++			wl_cfg80211_tdls_config(cfg, TDLS_STATE_DISCONNECT, false);
++#endif /* WLTDLS */
++		} else if (wl_is_nonetwork(cfg, e)) {
++			WL_MSG(ndev->name, "connect failed event=%d e->status %d e->reason %d \n",
++				event, (int)ntoh32(e->status), (int)ntoh32(e->reason));
++			wl_cfg80211_check_in4way(cfg, ndev, NO_SCAN_IN4WAY|NO_BTC_IN4WAY|WAIT_DISCONNECTED,
++				WL_EXT_STATUS_DISCONNECTED, NULL);
++#if defined(DHD_ENABLE_BIGDATA_LOGGING)
++			if (event == WLC_E_SET_SSID) {
++				wl_get_connect_failed_status(cfg, e);
++			}
++#endif /* DHD_ENABLE_BIGDATA_LOGGING */
++
++			if (wl_get_drv_status(cfg, DISCONNECTING, ndev) &&
++				wl_get_drv_status(cfg, CONNECTING, ndev)) {
++				wl_clr_drv_status(cfg, DISCONNECTING, ndev);
++				wl_clr_drv_status(cfg, CONNECTING, ndev);
++				wl_cfg80211_scan_abort(cfg);
++				DHD_ENABLE_RUNTIME_PM((dhd_pub_t *)cfg->pub);
++				return err;
++			}
++			/* Clean up any pending scan request */
++			wl_cfg80211_cancel_scan(cfg);
++
++			if (wl_get_drv_status(cfg, CONNECTING, ndev))
++				wl_bss_connect_done(cfg, ndev, e, data, false);
++		} else {
++			WL_DBG(("%s nothing\n", __FUNCTION__));
++		}
++		DHD_ENABLE_RUNTIME_PM((dhd_pub_t *)cfg->pub);
++	}
++	else {
++		WL_MSG(ndev->name, "Invalid mode %d event %d status %d\n",
++			wl_get_mode_by_netdev(cfg, ndev), ntoh32(e->event_type),
++			ntoh32(e->status));
++	}
++	return err;
++}
++
++#ifdef WL_RELMCAST
++void wl_cfg80211_set_rmc_pid(struct net_device *dev, int pid)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	if (pid > 0)
++		cfg->rmc_event_pid = pid;
++	WL_DBG(("set pid for rmc event : pid=%d\n", pid));
++}
++#endif /* WL_RELMCAST */
++
++#ifdef WL_RELMCAST
++static s32
++wl_notify_rmc_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	u32 evt = ntoh32(e->event_type);
++	u32 reason = ntoh32(e->reason);
++	int ret = -1;
++
++	switch (reason) {
++		case WLC_E_REASON_RMC_AR_LOST:
++		case WLC_E_REASON_RMC_AR_NO_ACK:
++			if (cfg->rmc_event_pid != 0) {
++				ret = wl_netlink_send_msg(cfg->rmc_event_pid,
++					RMC_EVENT_LEADER_CHECK_FAIL,
++					cfg->rmc_event_seq++, NULL, 0);
++			}
++			break;
++		default:
++			break;
++	}
++	WL_DBG(("rmcevent : evt=%d, pid=%d, ret=%d\n", evt, cfg->rmc_event_pid, ret));
++	return ret;
++}
++#endif /* WL_RELMCAST */
++
++#ifdef GSCAN_SUPPORT
++static s32
++wl_handle_roam_exp_event(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	struct net_device *ndev = NULL;
++	u32 datalen = be32_to_cpu(e->datalen);
++
++	if (datalen) {
++		wl_roam_exp_event_t *evt_data = (wl_roam_exp_event_t *)data;
++		if (evt_data->version == ROAM_EXP_EVENT_VERSION) {
++			wlc_ssid_t *ssid = &evt_data->cur_ssid;
++			struct wireless_dev *wdev;
++			ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++			if (ndev) {
++				wdev = ndev->ieee80211_ptr;
++				wdev->ssid_len = min(ssid->SSID_len, (uint32)DOT11_MAX_SSID_LEN);
++				memcpy(wdev->ssid, ssid->SSID, wdev->ssid_len);
++				WL_ERR(("SSID is %s\n", ssid->SSID));
++				wl_update_prof(cfg, ndev, NULL, ssid, WL_PROF_SSID);
++			} else {
++				WL_ERR(("NULL ndev!\n"));
++			}
++		} else {
++			WL_ERR(("Version mismatch %d, expected %d", evt_data->version,
++			       ROAM_EXP_EVENT_VERSION));
++		}
++	}
++	return BCME_OK;
++}
++#endif /* GSCAN_SUPPORT */
++
++#ifdef RSSI_MONITOR_SUPPORT
++static s32 wl_handle_rssi_monitor_event(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++
++#if defined(WL_VENDOR_EXT_SUPPORT) || defined(CONFIG_BCMDHD_VENDOR_EXT)
++	u32 datalen = be32_to_cpu(e->datalen);
++	struct net_device *ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++
++	if (datalen) {
++		wl_rssi_monitor_evt_t *evt_data = (wl_rssi_monitor_evt_t *)data;
++		if (evt_data->version == RSSI_MONITOR_VERSION) {
++			dhd_rssi_monitor_evt_t monitor_data;
++			monitor_data.version = DHD_RSSI_MONITOR_EVT_VERSION;
++			monitor_data.cur_rssi = evt_data->cur_rssi;
++			memcpy(&monitor_data.BSSID, &e->addr, ETHER_ADDR_LEN);
++			wl_cfgvendor_send_async_event(wiphy, ndev,
++				GOOGLE_RSSI_MONITOR_EVENT,
++				&monitor_data, sizeof(monitor_data));
++		} else {
++			WL_ERR(("Version mismatch %d, expected %d", evt_data->version,
++			       RSSI_MONITOR_VERSION));
++		}
++	}
++#endif /* WL_VENDOR_EXT_SUPPORT || CONFIG_BCMDHD_VENDOR_EXT */
++	return BCME_OK;
++}
++#endif /* RSSI_MONITOR_SUPPORT */
++
++static s32
++wl_notify_roaming_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	bool act;
++	struct net_device *ndev = NULL;
++	s32 err = 0;
++	u32 event = be32_to_cpu(e->event_type);
++	u32 status = be32_to_cpu(e->status);
++#ifdef DHD_LOSSLESS_ROAMING
++	struct wl_security *sec;
++#endif
++	WL_DBG(("Enter \n"));
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	if ((!cfg->disable_roam_event) && (event == WLC_E_BSSID)) {
++		wl_add_remove_eventmsg(ndev, WLC_E_ROAM, false);
++		cfg->disable_roam_event = TRUE;
++	}
++
++	if ((cfg->disable_roam_event) && (event == WLC_E_ROAM))
++		return err;
++
++	if ((event == WLC_E_ROAM || event == WLC_E_BSSID) && status == WLC_E_STATUS_SUCCESS) {
++		if (wl_get_drv_status(cfg, CONNECTED, ndev)) {
++#ifdef DHD_LOSSLESS_ROAMING
++			sec = wl_read_prof(cfg, ndev, WL_PROF_SEC);
++			/* In order to reduce roaming delay, wl_bss_roaming_done is
++			 * early called with WLC_E_LINK event. It is called from
++			 * here only if WLC_E_LINK event is blocked for specific
++			 * security type.
++			 */
++			if (IS_AKM_SUITE_FT(sec)) {
++				wl_bss_roaming_done(cfg, ndev, e, data);
++			}
++			/* Roam timer is deleted mostly from wl_cfg80211_change_station
++			 * after roaming is finished successfully. We need to delete
++			 * the timer from here only for some security types that aren't
++			 * using wl_cfg80211_change_station to authorize SCB
++			 */
++			if (IS_AKM_SUITE_FT(sec) || IS_AKM_SUITE_CCKM(sec)) {
++				wl_del_roam_timeout(cfg);
++			}
++#else
++			wl_bss_roaming_done(cfg, ndev, e, data);
++#endif /* DHD_LOSSLESS_ROAMING */
++		} else {
++			wl_bss_connect_done(cfg, ndev, e, data, true);
++		}
++		act = true;
++		wl_update_prof(cfg, ndev, e, &act, WL_PROF_ACT);
++		wl_update_prof(cfg, ndev, NULL, (const void *)&e->addr, WL_PROF_BSSID);
++
++		if (ndev == bcmcfg_to_prmry_ndev(cfg)) {
++			wl_vndr_ies_get_vendor_oui(cfg, ndev, NULL, 0);
++		}
++	}
++#ifdef DHD_LOSSLESS_ROAMING
++	else if ((event == WLC_E_ROAM || event == WLC_E_BSSID) && status != WLC_E_STATUS_SUCCESS) {
++		wl_del_roam_timeout(cfg);
++	}
++#endif
++	return err;
++}
++
++#ifdef CUSTOM_EVENT_PM_WAKE
++uint32 last_dpm_upd_time = 0;	/* ms */
++#define DPM_UPD_LMT_TIME	25000	/* ms */
++#define DPM_UPD_LMT_RSSI	-85	/* dbm */
++
++static s32
++wl_check_pmstatus(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	s32 err = BCME_OK;
++	struct net_device *ndev = NULL;
++	u8 *pbuf = NULL;
++	uint32 cur_dpm_upd_time = 0;
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++	s32 rssi;
++	scb_val_t scb_val;
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	pbuf = kzalloc(WLC_IOCTL_MEDLEN, GFP_KERNEL);
++	if (pbuf == NULL) {
++		WL_ERR(("failed to allocate local pbuf\n"));
++		return -ENOMEM;
++	}
++
++	err = wldev_iovar_getbuf_bsscfg(ndev, "dump",
++		"pm", strlen("pm"), pbuf, WLC_IOCTL_MEDLEN, 0, &cfg->ioctl_buf_sync);
++
++	if (err) {
++		WL_ERR(("dump ioctl err = %d", err));
++	} else {
++		WL_ERR(("PM status : %s\n", pbuf));
++	}
++
++	if (pbuf) {
++		kfree(pbuf);
++	}
++
++	if (dhd->early_suspended) {
++		/* LCD off */
++		memset(&scb_val, 0, sizeof(scb_val_t));
++		scb_val.val = 0;
++		err = wldev_ioctl_get(ndev, WLC_GET_RSSI, &scb_val, sizeof(scb_val_t));
++		if (err) {
++			WL_ERR(("Could not get rssi (%d)\n", err));
++		}
++		rssi = wl_rssi_offset(dtoh32(scb_val.val));
++		WL_ERR(("[%s] RSSI %d dBm\n", ndev->name, rssi));
++		if (rssi > DPM_UPD_LMT_RSSI) {
++			return err;
++		}
++	} else {
++		/* LCD on */
++		return err;
++	}
++
++	if (last_dpm_upd_time == 0) {
++		last_dpm_upd_time = OSL_SYSUPTIME();
++	} else {
++		cur_dpm_upd_time = OSL_SYSUPTIME();
++		if (cur_dpm_upd_time - last_dpm_upd_time < DPM_UPD_LMT_TIME) {
++			scb_val_t scbval;
++			bzero(&scbval, sizeof(scb_val_t));
++
++			err = wldev_ioctl_set(ndev, WLC_DISASSOC, &scbval, sizeof(scb_val_t));
++			if (err < 0) {
++				WL_ERR(("%s: Disassoc error %d\n", __FUNCTION__, err));
++				return err;
++			}
++			WL_ERR(("%s: Force Disassoc due to updated DPM event.\n", __FUNCTION__));
++
++			last_dpm_upd_time = 0;
++		} else {
++			last_dpm_upd_time = cur_dpm_upd_time;
++		}
++	}
++
++	return err;
++}
++#endif	/* CUSTOM_EVENT_PM_WAKE */
++
++#ifdef QOS_MAP_SET
++/* get user priority table */
++uint8 *
++wl_get_up_table(dhd_pub_t * dhdp, int idx)
++{
++	struct net_device *ndev;
++	struct bcm_cfg80211 *cfg;
++
++	ndev = dhd_idx2net(dhdp, idx);
++	if (ndev) {
++		cfg = wl_get_cfg(ndev);
++		if (cfg)
++			return (uint8 *)(cfg->up_table);
++	}
++
++	return NULL;
++}
++#endif /* QOS_MAP_SET */
++
++#if defined(DHD_LOSSLESS_ROAMING) || defined(DBG_PKT_MON)
++static s32
++wl_notify_roam_prep_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	struct wl_security *sec;
++	struct net_device *ndev;
++#if defined(DHD_LOSSLESS_ROAMING) || defined(DBG_PKT_MON)
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++#endif /* DHD_LOSSLESS_ROAMING || DBG_PKT_MON */
++	u32 status = ntoh32(e->status);
++	u32 reason = ntoh32(e->reason);
++
++	BCM_REFERENCE(sec);
++
++	if (status == WLC_E_STATUS_SUCCESS && reason != WLC_E_REASON_INITIAL_ASSOC) {
++		WL_ERR(("Attempting roam with reason code : %d\n", reason));
++	}
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++#ifdef DBG_PKT_MON
++	if (ndev == bcmcfg_to_prmry_ndev(cfg)) {
++		DHD_DBG_PKT_MON_STOP(dhdp);
++		DHD_DBG_PKT_MON_START(dhdp);
++	}
++#endif /* DBG_PKT_MON */
++
++#ifdef DHD_LOSSLESS_ROAMING
++sec = wl_read_prof(cfg, ndev, WL_PROF_SEC);
++	/* Disable Lossless Roaming for specific AKM suite
++	 * Any other AKM suite can be added below if transition time
++	 * is delayed because of Lossless Roaming
++	 * and it causes any certication failure
++	 */
++	if (IS_AKM_SUITE_FT(sec)) {
++		return BCME_OK;
++	}
++	dhdp->dequeue_prec_map = 1 << PRIO_8021D_NC;
++	/* Restore flow control  */
++	dhd_txflowcontrol(dhdp, ALL_INTERFACES, OFF);
++
++	mod_timer(&cfg->roam_timeout, jiffies + msecs_to_jiffies(WL_ROAM_TIMEOUT_MS));
++#endif /* DHD_LOSSLESS_ROAMING */
++	return BCME_OK;
++
++}
++#endif /* DHD_LOSSLESS_ROAMING || DBG_PKT_MON */
++#ifdef ENABLE_TEMP_THROTTLING
++static s32
++wl_check_rx_throttle_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	s32 err = 0;
++	u32 status = ntoh32(e->status);
++	u32 reason = ntoh32(e->reason);
++
++	WL_ERR_EX(("RX THROTTLE : status=%d, reason=0x%x\n", status, reason));
++
++	return err;
++}
++#endif /* ENABLE_TEMP_THROTTLING */
++
++static s32 wl_get_assoc_ies(struct bcm_cfg80211 *cfg, struct net_device *ndev)
++{
++	wl_assoc_info_t assoc_info;
++	struct wl_connect_info *conn_info = wl_to_conn(cfg);
++	s32 err = 0;
++#ifdef QOS_MAP_SET
++	bcm_tlv_t * qos_map_ie = NULL;
++#endif /* QOS_MAP_SET */
++
++	WL_DBG(("Enter \n"));
++	err = wldev_iovar_getbuf(ndev, "assoc_info", NULL, 0, cfg->extra_buf,
++		WL_ASSOC_INFO_MAX, NULL);
++	if (unlikely(err)) {
++		WL_ERR(("could not get assoc info (%d)\n", err));
++		return err;
++	}
++	memcpy(&assoc_info, cfg->extra_buf, sizeof(wl_assoc_info_t));
++	assoc_info.req_len = htod32(assoc_info.req_len);
++	assoc_info.resp_len = htod32(assoc_info.resp_len);
++	assoc_info.flags = htod32(assoc_info.flags);
++	if (conn_info->req_ie_len) {
++		conn_info->req_ie_len = 0;
++		bzero(conn_info->req_ie, sizeof(conn_info->req_ie));
++	}
++	if (conn_info->resp_ie_len) {
++		conn_info->resp_ie_len = 0;
++		bzero(conn_info->resp_ie, sizeof(conn_info->resp_ie));
++	}
++	if (assoc_info.req_len) {
++		err = wldev_iovar_getbuf(ndev, "assoc_req_ies", NULL, 0, cfg->extra_buf,
++			WL_ASSOC_INFO_MAX, NULL);
++		if (unlikely(err)) {
++			WL_ERR(("could not get assoc req (%d)\n", err));
++			return err;
++		}
++		conn_info->req_ie_len = assoc_info.req_len - sizeof(struct dot11_assoc_req);
++		if (assoc_info.flags & WLC_ASSOC_REQ_IS_REASSOC) {
++			conn_info->req_ie_len -= ETHER_ADDR_LEN;
++		}
++		if (conn_info->req_ie_len <= MAX_REQ_LINE)
++			memcpy(conn_info->req_ie, cfg->extra_buf, conn_info->req_ie_len);
++		else {
++			WL_ERR(("IE size %d above max %d size \n",
++				conn_info->req_ie_len, MAX_REQ_LINE));
++			return err;
++		}
++	} else {
++		conn_info->req_ie_len = 0;
++	}
++	if (assoc_info.resp_len) {
++		err = wldev_iovar_getbuf(ndev, "assoc_resp_ies", NULL, 0, cfg->extra_buf,
++			WL_ASSOC_INFO_MAX, NULL);
++		if (unlikely(err)) {
++			WL_ERR(("could not get assoc resp (%d)\n", err));
++			return err;
++		}
++		conn_info->resp_ie_len = assoc_info.resp_len -sizeof(struct dot11_assoc_resp);
++		if (conn_info->resp_ie_len <= MAX_REQ_LINE) {
++			memcpy(conn_info->resp_ie, cfg->extra_buf, conn_info->resp_ie_len);
++		} else {
++			WL_ERR(("IE size %d above max %d size \n",
++				conn_info->resp_ie_len, MAX_REQ_LINE));
++			return err;
++		}
++
++#ifdef QOS_MAP_SET
++		/* find qos map set ie */
++		if ((qos_map_ie = bcm_parse_tlvs(conn_info->resp_ie, conn_info->resp_ie_len,
++				DOT11_MNG_QOS_MAP_ID)) != NULL) {
++			WL_DBG((" QoS map set IE found in assoc response\n"));
++			if (!cfg->up_table) {
++				cfg->up_table = kmalloc(UP_TABLE_MAX, GFP_KERNEL);
++			}
++			wl_set_up_table(cfg->up_table, qos_map_ie);
++		} else {
++			kfree(cfg->up_table);
++			cfg->up_table = NULL;
++		}
++#endif /* QOS_MAP_SET */
++	} else {
++		conn_info->resp_ie_len = 0;
++	}
++	WL_DBG(("req len (%d) resp len (%d)\n", conn_info->req_ie_len,
++		conn_info->resp_ie_len));
++
++	return err;
++}
++
++static s32 wl_ch_to_chanspec(struct net_device *dev, int ch, struct wl_join_params *join_params,
++        size_t *join_params_size)
++{
++	s32 bssidx = -1;
++	chanspec_t chanspec = 0, chspec;
++
++	if (ch != 0) {
++		struct bcm_cfg80211 *cfg =
++			(struct bcm_cfg80211 *)wiphy_priv(dev->ieee80211_ptr->wiphy);
++			join_params->params.chanspec_num = 1;
++			join_params->params.chanspec_list[0] = ch;
++
++			if (join_params->params.chanspec_list[0] <= CH_MAX_2G_CHANNEL)
++				chanspec |= WL_CHANSPEC_BAND_2G;
++			else
++				chanspec |= WL_CHANSPEC_BAND_5G;
++
++			/* Get the min_bw set for the interface */
++			chspec = wl_cfg80211_ulb_get_min_bw_chspec(cfg, dev->ieee80211_ptr, bssidx);
++			if (chspec == INVCHANSPEC) {
++				WL_ERR(("Invalid chanspec \n"));
++				return -EINVAL;
++			}
++			chanspec |= chspec;
++			chanspec |= WL_CHANSPEC_CTL_SB_NONE;
++
++			*join_params_size += WL_ASSOC_PARAMS_FIXED_SIZE +
++				join_params->params.chanspec_num * sizeof(chanspec_t);
++
++			join_params->params.chanspec_list[0]  &= WL_CHANSPEC_CHAN_MASK;
++			join_params->params.chanspec_list[0] |= chanspec;
++			join_params->params.chanspec_list[0] =
++				wl_chspec_host_to_driver(join_params->params.chanspec_list[0]);
++
++			join_params->params.chanspec_num =
++				htod32(join_params->params.chanspec_num);
++
++		WL_DBG(("join_params->params.chanspec_list[0]= %X, %d channels\n",
++			join_params->params.chanspec_list[0],
++			join_params->params.chanspec_num));
++	}
++	return 0;
++}
++
++static s32 wl_update_bss_info(struct bcm_cfg80211 *cfg, struct net_device *ndev, bool roam)
++{
++	struct cfg80211_bss *bss;
++	struct wl_bss_info *bi;
++	struct wlc_ssid *ssid;
++	struct bcm_tlv *tim;
++	s32 beacon_interval;
++	s32 dtim_period;
++	size_t ie_len;
++	u8 *ie;
++	u8 *curbssid;
++	s32 err = 0;
++	struct wiphy *wiphy;
++	u32 channel;
++	char *buf;
++	u32 freq, band;
++
++	wiphy = bcmcfg_to_wiphy(cfg);
++
++	ssid = (struct wlc_ssid *)wl_read_prof(cfg, ndev, WL_PROF_SSID);
++	curbssid = wl_read_prof(cfg, ndev, WL_PROF_BSSID);
++	bss = CFG80211_GET_BSS(wiphy, NULL, curbssid,
++		ssid->SSID, ssid->SSID_len);
++	buf = kzalloc(WL_EXTRA_BUF_MAX, GFP_ATOMIC);
++	if (!buf) {
++		WL_ERR(("buffer alloc failed.\n"));
++		return BCME_NOMEM;
++	}
++	mutex_lock(&cfg->usr_sync);
++	*(u32 *)buf = htod32(WL_EXTRA_BUF_MAX);
++	err = wldev_ioctl_get(ndev, WLC_GET_BSS_INFO, buf, WL_EXTRA_BUF_MAX);
++	if (unlikely(err)) {
++		WL_ERR(("Could not get bss info %d\n", err));
++		goto update_bss_info_out;
++	}
++	bi = (struct wl_bss_info *)(buf + 4);
++	channel = wf_chspec_ctlchan(wl_chspec_driver_to_host(bi->chanspec));
++	wl_update_prof(cfg, ndev, NULL, &channel, WL_PROF_CHAN);
++
++	if (!bss) {
++		WL_DBG(("Could not find the AP\n"));
++		if (memcmp(bi->BSSID.octet, curbssid, ETHER_ADDR_LEN)) {
++			WL_ERR(("Bssid doesn't match\n"));
++			err = -EIO;
++			goto update_bss_info_out;
++		}
++		err = wl_inform_single_bss(cfg, bi, roam);
++		if (unlikely(err))
++			goto update_bss_info_out;
++
++		ie = ((u8 *)bi) + bi->ie_offset;
++		ie_len = bi->ie_length;
++		beacon_interval = cpu_to_le16(bi->beacon_period);
++	} else {
++		WL_DBG(("Found the AP in the list - BSSID %pM\n", bss->bssid));
++#if LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 38)
++		freq = ieee80211_channel_to_frequency(channel);
++#else
++		band = (channel <= CH_MAX_2G_CHANNEL) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
++		freq = ieee80211_channel_to_frequency(channel, band);
++#endif
++		bss->channel = ieee80211_get_channel(wiphy, freq);
++#if defined(WL_CFG80211_P2P_DEV_IF)
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++		ie = (u8 *)bss->ies->data;
++		ie_len = bss->ies->len;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++#else
++		ie = bss->information_elements;
++		ie_len = bss->len_information_elements;
++#endif /* WL_CFG80211_P2P_DEV_IF */
++		beacon_interval = bss->beacon_interval;
++
++		CFG80211_PUT_BSS(wiphy, bss);
++	}
++
++	tim = bcm_parse_tlvs(ie, ie_len, WLAN_EID_TIM);
++	if (tim) {
++		dtim_period = tim->data[1];
++	} else {
++		/*
++		* active scan was done so we could not get dtim
++		* information out of probe response.
++		* so we speficially query dtim information.
++		*/
++		dtim_period = 0;
++		err = wldev_ioctl_get(ndev, WLC_GET_DTIMPRD,
++			&dtim_period, sizeof(dtim_period));
++		if (unlikely(err)) {
++			WL_ERR(("WLC_GET_DTIMPRD error (%d)\n", err));
++			goto update_bss_info_out;
++		}
++	}
++
++	wl_update_prof(cfg, ndev, NULL, &beacon_interval, WL_PROF_BEACONINT);
++	wl_update_prof(cfg, ndev, NULL, &dtim_period, WL_PROF_DTIMPERIOD);
++
++update_bss_info_out:
++	if (unlikely(err)) {
++		WL_ERR(("Failed with error %d\n", err));
++	}
++
++	kfree(buf);
++	mutex_unlock(&cfg->usr_sync);
++	return err;
++}
++
++static s32
++wl_bss_roaming_done(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data)
++{
++	struct wl_connect_info *conn_info = wl_to_conn(cfg);
++	s32 err = 0;
++	u8 *curbssid;
++	u32 *channel;
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39))
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	struct ieee80211_supported_band *band;
++	struct ieee80211_channel *notify_channel = NULL;
++	u32 freq;
++	u32 cur_channel, chanspec;
++#endif 
++#if defined(WLADPS_SEAK_AP_WAR) || defined(WBTEXT)
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++#endif /* WLADPS_SEAK_AP_WAR || WBTEXT */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++	struct cfg80211_roam_info roam_info = {};
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)) */
++#ifdef WLFBT
++	uint32 data_len = 0;
++	if (data)
++		data_len = ntoh32(e->datalen);
++#endif /* WLFBT */
++
++#ifdef WLADPS_SEAK_AP_WAR
++	BCM_REFERENCE(dhdp);
++#endif /* WLADPS_SEAK_AP_WAR */
++
++	curbssid = wl_read_prof(cfg, ndev, WL_PROF_BSSID);
++	channel = (u32 *)wl_read_prof(cfg, ndev, WL_PROF_CHAN);
++
++	/* Skip calling cfg80211_roamed If the channels are same and
++	 * the current bssid/last_roamed_bssid & the new bssid are same
++	 * Also clear timer roam_timeout.
++	 * Only used on BCM4359 devices.
++	 */
++	err = wldev_iovar_getint(ndev, "chanspec", (s32 *)&chanspec);
++	if (unlikely(err)) {
++		return  err;
++	}
++	cur_channel = wf_chspec_ctlchan(wl_chspec_driver_to_host(chanspec));
++	WL_DBG(("%d=>%d, %pM(%pM)=>%pM\n", *channel, cur_channel,
++		curbssid, (const u8*)(&cfg->last_roamed_addr), (const u8*)(&e->addr)));
++	if ((*channel == cur_channel) &&
++			((memcmp(curbssid, &e->addr, ETHER_ADDR_LEN) == 0) ||
++			(memcmp(&cfg->last_roamed_addr,	&e->addr, ETHER_ADDR_LEN) == 0))) {
++		WL_DBG(("BSS already present, Skipping roamed event to"
++		" upper layer\n"));
++#ifdef DHD_LOSSLESS_ROAMING
++		wl_del_roam_timeout(cfg);
++#endif  /* DHD_LOSSLESS_ROAMING */
++		return  err;
++	}
++
++	wl_get_assoc_ies(cfg, ndev);
++	wl_update_prof(cfg, ndev, NULL, (const void *)(e->addr.octet), WL_PROF_BSSID);
++	curbssid = wl_read_prof(cfg, ndev, WL_PROF_BSSID);
++	wl_update_bss_info(cfg, ndev, true);
++	wl_update_pmklist(ndev, cfg->pmk_list, err);
++
++	channel = (u32 *)wl_read_prof(cfg, ndev, WL_PROF_CHAN);
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39))
++	/* channel info for cfg80211_roamed introduced in 2.6.39-rc1 */
++	if (*channel <= CH_MAX_2G_CHANNEL)
++		band = wiphy->bands[IEEE80211_BAND_2GHZ];
++	else
++		band = wiphy->bands[IEEE80211_BAND_5GHZ];
++	freq = ieee80211_channel_to_frequency(*channel, band->band);
++	notify_channel = ieee80211_get_channel(wiphy, freq);
++#endif 
++#ifdef WLFBT
++	/* back up the given FBT key for the further supplicant request,
++	 * currently not checking the FBT is enabled for current BSS in DHD,
++	 * because the supplicant decides to take it or not.
++	 */
++	if (data && (data_len == FBT_KEYLEN)) {
++		memcpy(cfg->fbt_key, data, FBT_KEYLEN);
++	}
++#endif /* WLFBT */
++#ifdef WLADPS_SEAK_AP_WAR
++	if ((dhdp->op_mode & DHD_FLAG_STA_MODE) &&
++			(!dhdp->disabled_adps)) {
++		bool find = FALSE;
++		uint8 enable_mode;
++		if (!memcmp(curbssid, (u8*)CAMEO_MAC_PREFIX, MAC_PREFIX_LEN)) {
++			find = wl_find_vndr_ies_specific_vender(cfg, ndev, ATHEROS_OUI);
++		}
++		enable_mode = (find == TRUE) ? OFF : ON;
++		wl_set_adps_mode(cfg, ndev, enable_mode);
++	}
++#endif /* WLADPS_SEAK_AP_WAR */
++	WL_MSG(ndev->name, "succeeded to " MACDBG " (ch:%d)\n",
++		MAC2STRDBG((const u8*)(&e->addr)), *channel);
++	wl_cfg80211_check_in4way(cfg, ndev, 0, WL_EXT_STATUS_CONNECTED, NULL);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++	roam_info.channel = notify_channel;
++	roam_info.bssid = curbssid;
++	roam_info.req_ie = conn_info->req_ie;
++	roam_info.req_ie_len = conn_info->req_ie_len;
++	roam_info.resp_ie = conn_info->resp_ie;
++	roam_info.resp_ie_len = conn_info->resp_ie_len;
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++	cfg80211_roamed(ndev, &roam_info, GFP_KERNEL);
++#else
++	cfg80211_roamed(ndev,
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39))
++		notify_channel,
++#endif
++		curbssid,
++		conn_info->req_ie, conn_info->req_ie_len,
++		conn_info->resp_ie, conn_info->resp_ie_len, GFP_KERNEL);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)) */
++	WL_DBG(("Report roaming result\n"));
++
++	memcpy(&cfg->last_roamed_addr, &e->addr, ETHER_ADDR_LEN);
++	wl_set_drv_status(cfg, CONNECTED, ndev);
++
++#if defined(DHD_ENABLE_BIGDATA_LOGGING)
++	cfg->roam_count++;
++#endif /* DHD_ENABLE_BIGDATA_LOGGING */
++
++#ifdef WBTEXT
++	if (dhdp->wbtext_support) {
++		/* set wnm_keepalives_max_idle after association */
++		wl_cfg80211_wbtext_set_wnm_maxidle(cfg, ndev);
++		/* send nbr request or BTM query to update RCC */
++		wl_cfg80211_wbtext_update_rcc(cfg, ndev);
++	}
++#endif /* WBTEXT */
++
++	return err;
++}
++
++static bool
++wl_cfg80211_verify_bss(struct bcm_cfg80211 *cfg, struct net_device *ndev)
++{
++	struct cfg80211_bss *bss;
++	struct wiphy *wiphy;
++	struct wlc_ssid *ssid;
++	uint8 *curbssid;
++	int count = 0;
++	int ret = false;
++
++	wiphy = bcmcfg_to_wiphy(cfg);
++	ssid = (struct wlc_ssid *)wl_read_prof(cfg, ndev, WL_PROF_SSID);
++	curbssid = wl_read_prof(cfg, ndev, WL_PROF_BSSID);
++	if (!ssid) {
++		WL_ERR(("No SSID found in the saved profile \n"));
++		return false;
++	}
++
++	do {
++		bss = CFG80211_GET_BSS(wiphy, NULL, curbssid,
++			ssid->SSID, ssid->SSID_len);
++		if (bss || (count > 5)) {
++			break;
++		}
++
++		count++;
++		msleep(100);
++	} while (bss == NULL);
++
++	WL_DBG(("cfg80211 bss_ptr:%p loop_cnt:%d\n", bss, count));
++	if (bss) {
++		/* Update the reference count after use */
++		CFG80211_PUT_BSS(wiphy, bss);
++		ret = true;
++	}
++
++	return ret;
++}
++
++static s32
++wl_bss_connect_done(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data, bool completed)
++{
++	struct wl_connect_info *conn_info = wl_to_conn(cfg);
++	struct wl_security *sec = wl_read_prof(cfg, ndev, WL_PROF_SEC);
++	s32 err = 0;
++	u8 *curbssid = wl_read_prof(cfg, ndev, WL_PROF_BSSID);
++	dhd_pub_t *dhdp;
++
++	dhdp = (dhd_pub_t *)(cfg->pub);
++	BCM_REFERENCE(dhdp);
++
++	if (!sec) {
++		WL_ERR(("sec is NULL\n"));
++		return -ENODEV;
++	}
++	WL_DBG((" enter\n"));
++#ifdef ESCAN_RESULT_PATCH
++	if (wl_get_drv_status(cfg, CONNECTED, ndev)) {
++		if (memcmp(curbssid, connect_req_bssid, ETHER_ADDR_LEN) == 0) {
++			WL_DBG((" Connected event of connected device e=%d s=%d, ignore it\n",
++				ntoh32(e->event_type), ntoh32(e->status)));
++			return err;
++		}
++	}
++	if (memcmp(curbssid, broad_bssid, ETHER_ADDR_LEN) == 0 &&
++		memcmp(broad_bssid, connect_req_bssid, ETHER_ADDR_LEN) != 0) {
++		WL_DBG(("copy bssid\n"));
++		memcpy(curbssid, connect_req_bssid, ETHER_ADDR_LEN);
++	}
++
++#else
++	if (cfg->scan_request) {
++		wl_notify_escan_complete(cfg, ndev, true, true);
++	}
++#endif /* ESCAN_RESULT_PATCH */
++	if (wl_get_drv_status(cfg, CONNECTING, ndev)) {
++		wl_cfg80211_scan_abort(cfg);
++		wl_clr_drv_status(cfg, CONNECTING, ndev);
++		if (completed) {
++			wl_get_assoc_ies(cfg, ndev);
++			wl_update_prof(cfg, ndev, NULL, (const void *)(e->addr.octet),
++				WL_PROF_BSSID);
++			curbssid = wl_read_prof(cfg, ndev, WL_PROF_BSSID);
++			wl_update_bss_info(cfg, ndev, false);
++			wl_update_pmklist(ndev, cfg->pmk_list, err);
++			wl_set_drv_status(cfg, CONNECTED, ndev);
++#ifdef WLADPS_SEAK_AP_WAR
++			if ((dhdp->op_mode & DHD_FLAG_STA_MODE) &&
++					(!dhdp->disabled_adps)) {
++				bool find = FALSE;
++				uint8 enable_mode;
++				if (!memcmp(curbssid, (u8*)CAMEO_MAC_PREFIX, MAC_PREFIX_LEN)) {
++					find = wl_find_vndr_ies_specific_vender(cfg,
++						ndev, ATHEROS_OUI);
++				}
++				enable_mode = (find == TRUE) ? OFF : ON;
++				wl_set_adps_mode(cfg, ndev, enable_mode);
++			}
++#endif /* WLADPS_SEAK_AP_WAR */
++			if (ndev != bcmcfg_to_prmry_ndev(cfg)) {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)
++				init_completion(&cfg->iface_disable);
++#else
++				/* reinitialize completion to clear previous count */
++				INIT_COMPLETION(cfg->iface_disable);
++#endif
++			}
++#ifdef CUSTOM_SET_CPUCORE
++			if (wl_get_chan_isvht80(ndev, dhdp)) {
++				if (ndev == bcmcfg_to_prmry_ndev(cfg))
++					dhdp->chan_isvht80 |= DHD_FLAG_STA_MODE; /* STA mode */
++				else if (is_p2p_group_iface(ndev->ieee80211_ptr))
++					dhdp->chan_isvht80 |= DHD_FLAG_P2P_MODE; /* p2p mode */
++				dhd_set_cpucore(dhdp, TRUE);
++			}
++#endif /* CUSTOM_SET_CPUCORE */
++			memset(&cfg->last_roamed_addr, 0, ETHER_ADDR_LEN);
++		}
++
++		if (completed && (wl_cfg80211_verify_bss(cfg, ndev) != true)) {
++			/* If bss entry is not available in the cfg80211 bss cache
++			 * the wireless stack will complain and won't populate
++			 * wdev->current_bss ptr
++			 */
++			WL_ERR(("BSS entry not found. Indicate assoc event failure\n"));
++			completed = false;
++			sec->auth_assoc_res_status = WLAN_STATUS_UNSPECIFIED_FAILURE;
++		}
++		if (completed) {
++			WL_INFORM(("Report connect result - connection succeeded\n"));
++			wl_cfg80211_check_in4way(cfg, ndev, 0, WL_EXT_STATUS_CONNECTED, NULL);
++		} else {
++			WL_MSG(ndev->name, "Report connect result - connection failed\n");
++			wl_cfg80211_check_in4way(cfg, ndev, NO_SCAN_IN4WAY|NO_BTC_IN4WAY|WAIT_DISCONNECTED,
++				WL_EXT_STATUS_DISCONNECTED, NULL);
++		}
++		cfg80211_connect_result(ndev,
++			curbssid,
++			conn_info->req_ie,
++			conn_info->req_ie_len,
++			conn_info->resp_ie,
++			conn_info->resp_ie_len,
++			completed ? WLAN_STATUS_SUCCESS :
++			(sec->auth_assoc_res_status) ?
++			sec->auth_assoc_res_status :
++			WLAN_STATUS_UNSPECIFIED_FAILURE,
++			GFP_KERNEL);
++	}
++#ifdef CONFIG_TCPACK_FASTTX
++	if (wl_get_chan_isvht80(ndev, dhdp))
++		wldev_iovar_setint(ndev, "tcpack_fast_tx", 0);
++	else
++		wldev_iovar_setint(ndev, "tcpack_fast_tx", 1);
++#endif /* CONFIG_TCPACK_FASTTX */
++
++	return err;
++}
++
++static s32
++wl_notify_mic_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	struct net_device *ndev = NULL;
++	u16 flags = ntoh16(e->flags);
++	enum nl80211_key_type key_type;
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	mutex_lock(&cfg->usr_sync);
++	if (flags & WLC_EVENT_MSG_GROUP)
++		key_type = NL80211_KEYTYPE_GROUP;
++	else
++		key_type = NL80211_KEYTYPE_PAIRWISE;
++
++	cfg80211_michael_mic_failure(ndev, (const u8 *)&e->addr, key_type, -1,
++		NULL, GFP_KERNEL);
++	mutex_unlock(&cfg->usr_sync);
++
++	return 0;
++}
++
++#ifdef BT_WIFI_HANDOVER
++static s32
++wl_notify_bt_wifi_handover_req(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	struct net_device *ndev = NULL;
++	u32 event = ntoh32(e->event_type);
++	u32 datalen = ntoh32(e->datalen);
++	s32 err;
++
++	WL_ERR(("wl_notify_bt_wifi_handover_req: event_type : %d, datalen : %d\n", event, datalen));
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++	err = wl_genl_send_msg(ndev, event, data, (u16)datalen, 0, 0);
++
++	return err;
++}
++#endif /* BT_WIFI_HANDOVER */
++
++#ifdef PNO_SUPPORT
++static s32
++wl_notify_pfn_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	struct net_device *ndev = NULL;
++#ifdef GSCAN_SUPPORT
++	void *ptr;
++	int send_evt_bytes = 0;
++	u32 event = be32_to_cpu(e->event_type);
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++#endif /* GSCAN_SUPPORT */
++
++	WL_ERR((">>> PNO Event\n"));
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++#ifdef GSCAN_SUPPORT
++	ptr = dhd_dev_process_epno_result(ndev, data, event, &send_evt_bytes);
++	if (ptr) {
++		wl_cfgvendor_send_async_event(wiphy, ndev,
++			GOOGLE_SCAN_EPNO_EVENT, ptr, send_evt_bytes);
++		kfree(ptr);
++	}
++	if (!dhd_dev_is_legacy_pno_enabled(ndev))
++		return 0;
++#endif /* GSCAN_SUPPORT */
++
++
++#ifndef WL_SCHED_SCAN
++	mutex_lock(&cfg->usr_sync);
++	/* TODO: Use cfg80211_sched_scan_results(wiphy); */
++	CFG80211_DISCONNECTED(ndev, 0, NULL, 0, false, GFP_KERNEL);
++	mutex_unlock(&cfg->usr_sync);
++#else
++	/* If cfg80211 scheduled scan is supported, report the pno results via sched
++	 * scan results
++	 */
++	wl_notify_sched_scan_results(cfg, ndev, e, data);
++#endif /* WL_SCHED_SCAN */
++	return 0;
++}
++#endif /* PNO_SUPPORT */
++
++#ifdef GSCAN_SUPPORT
++static s32
++wl_notify_gscan_event(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	s32 err = 0;
++	u32 event = be32_to_cpu(e->event_type);
++	void *ptr;
++	int send_evt_bytes = 0;
++	int event_type;
++	struct net_device *ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	u32 len = ntoh32(e->datalen);
++
++	switch (event) {
++		case WLC_E_PFN_BEST_BATCHING:
++			err = dhd_dev_retrieve_batch_scan(ndev);
++			if (err < 0) {
++				WL_ERR(("Batch retrieval already in progress %d\n", err));
++			} else {
++				event_type = WIFI_SCAN_THRESHOLD_NUM_SCANS;
++				if (data && len) {
++					event_type = *((int *)data);
++				}
++				wl_cfgvendor_send_async_event(wiphy, ndev,
++				    GOOGLE_GSCAN_BATCH_SCAN_EVENT,
++				     &event_type, sizeof(int));
++			}
++			break;
++		case WLC_E_PFN_SCAN_COMPLETE:
++			event_type = WIFI_SCAN_COMPLETE;
++			wl_cfgvendor_send_async_event(wiphy, ndev,
++				GOOGLE_SCAN_COMPLETE_EVENT,
++				&event_type, sizeof(int));
++			break;
++		case WLC_E_PFN_BSSID_NET_FOUND:
++			ptr = dhd_dev_hotlist_scan_event(ndev, data, &send_evt_bytes,
++			      HOTLIST_FOUND);
++			if (ptr) {
++				wl_cfgvendor_send_hotlist_event(wiphy, ndev,
++				 ptr, send_evt_bytes, GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT);
++				dhd_dev_gscan_hotlist_cache_cleanup(ndev, HOTLIST_FOUND);
++			} else {
++				err = -ENOMEM;
++			}
++			break;
++		case WLC_E_PFN_BSSID_NET_LOST:
++			/* WLC_E_PFN_BSSID_NET_LOST is conflict shared with WLC_E_PFN_SCAN_ALLGONE
++			 * We currently do not use WLC_E_PFN_SCAN_ALLGONE, so if we get it, ignore
++			 */
++			if (len) {
++				ptr = dhd_dev_hotlist_scan_event(ndev, data, &send_evt_bytes,
++				            HOTLIST_LOST);
++				if (ptr) {
++					wl_cfgvendor_send_hotlist_event(wiphy, ndev,
++					 ptr, send_evt_bytes, GOOGLE_GSCAN_GEOFENCE_LOST_EVENT);
++					dhd_dev_gscan_hotlist_cache_cleanup(ndev, HOTLIST_LOST);
++				} else {
++					err = -ENOMEM;
++				}
++			} else {
++				err = -EINVAL;
++			}
++			break;
++		case WLC_E_PFN_GSCAN_FULL_RESULT:
++			ptr = dhd_dev_process_full_gscan_result(ndev, data, len, &send_evt_bytes);
++			if (ptr) {
++				wl_cfgvendor_send_async_event(wiphy, ndev,
++				    GOOGLE_SCAN_FULL_RESULTS_EVENT, ptr, send_evt_bytes);
++				kfree(ptr);
++			} else {
++				err = -ENOMEM;
++			}
++			break;
++		case WLC_E_PFN_SSID_EXT:
++			ptr = dhd_dev_process_epno_result(ndev, data, event, &send_evt_bytes);
++			if (ptr) {
++				wl_cfgvendor_send_async_event(wiphy, ndev,
++				    GOOGLE_SCAN_EPNO_EVENT, ptr, send_evt_bytes);
++				kfree(ptr);
++			} else {
++				err = -ENOMEM;
++			}
++			break;
++		default:
++			WL_ERR(("Unknown event %d\n", event));
++			break;
++	}
++	return err;
++}
++#endif /* GSCAN_SUPPORT */
++
++static s32
++wl_notify_scan_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	struct channel_info channel_inform;
++	struct wl_scan_results *bss_list;
++	struct net_device *ndev = NULL;
++	u32 len = WL_SCAN_BUF_MAX;
++	s32 err = 0;
++	unsigned long flags;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
++	struct cfg80211_scan_info info;
++#endif
++
++	WL_DBG(("Enter \n"));
++	if (!wl_get_drv_status(cfg, SCANNING, ndev)) {
++		WL_ERR(("scan is not ready \n"));
++		return err;
++	}
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	mutex_lock(&cfg->usr_sync);
++	wl_clr_drv_status(cfg, SCANNING, ndev);
++	memset(&channel_inform, 0, sizeof(channel_inform));
++	err = wldev_ioctl_get(ndev, WLC_GET_CHANNEL, &channel_inform,
++		sizeof(channel_inform));
++	if (unlikely(err)) {
++		WL_ERR(("scan busy (%d)\n", err));
++		goto scan_done_out;
++	}
++	channel_inform.scan_channel = dtoh32(channel_inform.scan_channel);
++	if (unlikely(channel_inform.scan_channel)) {
++
++		WL_DBG(("channel_inform.scan_channel (%d)\n",
++			channel_inform.scan_channel));
++	}
++	cfg->bss_list = cfg->scan_results;
++	bss_list = cfg->bss_list;
++	memset(bss_list, 0, len);
++	bss_list->buflen = htod32(len);
++	err = wldev_ioctl_get(ndev, WLC_SCAN_RESULTS, bss_list, len);
++	if (unlikely(err) && unlikely(!cfg->scan_suppressed)) {
++		WL_ERR(("%s Scan_results error (%d)\n", ndev->name, err));
++		err = -EINVAL;
++		goto scan_done_out;
++	}
++	bss_list->buflen = dtoh32(bss_list->buflen);
++	bss_list->version = dtoh32(bss_list->version);
++	bss_list->count = dtoh32(bss_list->count);
++
++	err = wl_inform_bss(cfg);
++
++scan_done_out:
++	_del_timer_sync(&cfg->scan_timeout);
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++	if (cfg->scan_request) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
++		info.aborted = false;
++		cfg80211_scan_done(cfg->scan_request, &info);
++#else
++		cfg80211_scan_done(cfg->scan_request, false);
++#endif
++		cfg->scan_request = NULL;
++	}
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++	WL_DBG(("cfg80211_scan_done\n"));
++	mutex_unlock(&cfg->usr_sync);
++	return err;
++}
++
++static s32
++wl_frame_get_mgmt(u16 fc, const struct ether_addr *da,
++	const struct ether_addr *sa, const struct ether_addr *bssid,
++	u8 **pheader, u32 *body_len, u8 *pbody)
++{
++	struct dot11_management_header *hdr;
++	u32 totlen = 0;
++	s32 err = 0;
++	u8 *offset;
++	u32 prebody_len = *body_len;
++	switch (fc) {
++		case FC_ASSOC_REQ:
++			/* capability , listen interval */
++			totlen = DOT11_ASSOC_REQ_FIXED_LEN;
++			*body_len += DOT11_ASSOC_REQ_FIXED_LEN;
++			break;
++
++		case FC_REASSOC_REQ:
++			/* capability, listen inteval, ap address */
++			totlen = DOT11_REASSOC_REQ_FIXED_LEN;
++			*body_len += DOT11_REASSOC_REQ_FIXED_LEN;
++			break;
++	}
++	totlen += DOT11_MGMT_HDR_LEN + prebody_len;
++	*pheader = kzalloc(totlen, GFP_KERNEL);
++	if (*pheader == NULL) {
++		WL_ERR(("memory alloc failed \n"));
++		return -ENOMEM;
++	}
++	hdr = (struct dot11_management_header *) (*pheader);
++	hdr->fc = htol16(fc);
++	hdr->durid = 0;
++	hdr->seq = 0;
++	offset = (u8*)(hdr + 1) + (totlen - DOT11_MGMT_HDR_LEN - prebody_len);
++	bcopy((const char*)da, (u8*)&hdr->da, ETHER_ADDR_LEN);
++	bcopy((const char*)sa, (u8*)&hdr->sa, ETHER_ADDR_LEN);
++	bcopy((const char*)bssid, (u8*)&hdr->bssid, ETHER_ADDR_LEN);
++	if ((pbody != NULL) && prebody_len)
++		bcopy((const char*)pbody, offset, prebody_len);
++	*body_len = totlen;
++	return err;
++}
++
++
++void
++wl_stop_wait_next_action_frame(struct bcm_cfg80211 *cfg, struct net_device *ndev, u8 bsscfgidx)
++{
++	s32 err = 0;
++
++	if (wl_get_drv_status_all(cfg, FINDING_COMMON_CHANNEL)) {
++		if (timer_pending(&cfg->p2p->listen_timer)) {
++			_del_timer_sync(&cfg->p2p->listen_timer);
++		}
++		if (cfg->afx_hdl != NULL) {
++			if (cfg->afx_hdl->dev != NULL) {
++				wl_clr_drv_status(cfg, SCANNING, cfg->afx_hdl->dev);
++				wl_clr_drv_status(cfg, FINDING_COMMON_CHANNEL, cfg->afx_hdl->dev);
++			}
++			cfg->afx_hdl->peer_chan = WL_INVALID;
++		}
++		complete(&cfg->act_frm_scan);
++		WL_DBG(("*** Wake UP ** Working afx searching is cleared\n"));
++	} else if (wl_get_drv_status_all(cfg, SENDING_ACT_FRM)) {
++		if (!(wl_get_p2p_status(cfg, ACTION_TX_COMPLETED) ||
++			wl_get_p2p_status(cfg, ACTION_TX_NOACK)))
++			wl_set_p2p_status(cfg, ACTION_TX_COMPLETED);
++
++		WL_DBG(("*** Wake UP ** abort actframe iovar on bsscfxidx %d\n", bsscfgidx));
++		/* if channel is not zero, "actfame" uses off channel scan.
++		 * So abort scan for off channel completion.
++		 */
++		if (cfg->af_sent_channel) {
++			/* Scan engine is not used for sending action frames in the latest driver
++			 * branches. So, actframe_abort is used in the latest driver branches
++			 * instead of scan abort.
++			 * New driver branches:
++			 *     Issue actframe_abort and it succeeded. So, don't execute scan abort.
++			 * Old driver branches:
++			 *     Issue actframe_abort and it fails. So, execute scan abort.
++			 */
++			err = wldev_iovar_setint_bsscfg(ndev, "actframe_abort", 1, bsscfgidx);
++			if (err < 0) {
++				wl_cfg80211_scan_abort(cfg);
++			}
++		}
++	}
++#ifdef WL_CFG80211_SYNC_GON
++	else if (wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM_LISTEN)) {
++		WL_DBG(("*** Wake UP ** abort listen for next af frame\n"));
++		/* So abort scan to cancel listen */
++		wl_cfg80211_scan_abort(cfg);
++	}
++#endif /* WL_CFG80211_SYNC_GON */
++}
++
++#if defined(WLTDLS)
++bool wl_cfg80211_is_tdls_tunneled_frame(void *frame, u32 frame_len)
++{
++	unsigned char *data;
++
++	if (frame == NULL) {
++		WL_ERR(("Invalid frame \n"));
++		return false;
++	}
++
++	if (frame_len < 5) {
++		WL_ERR(("Invalid frame length [%d] \n", frame_len));
++		return false;
++	}
++
++	data = frame;
++
++	if (!memcmp(data, TDLS_TUNNELED_PRB_REQ, 5) ||
++		!memcmp(data, TDLS_TUNNELED_PRB_RESP, 5)) {
++		WL_DBG(("TDLS Vendor Specific Received type\n"));
++		return true;
++	}
++
++	return false;
++}
++#endif /* WLTDLS */
++
++
++int wl_cfg80211_get_ioctl_version(void)
++{
++	return ioctl_version;
++}
++
++static s32
++wl_notify_rx_mgmt_frame(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	struct ieee80211_supported_band *band;
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	struct ether_addr da;
++	struct ether_addr bssid;
++	bool isfree = false;
++	s32 err = 0;
++	s32 freq;
++#if defined(TDLS_MSG_ONLY_WFD)
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++#endif /* TDLS_MSG_ONLY_WFD && BCMDONGLEHOST */
++	struct net_device *ndev = NULL;
++	wifi_p2p_pub_act_frame_t *act_frm = NULL;
++	wifi_p2p_action_frame_t *p2p_act_frm = NULL;
++	wifi_p2psd_gas_pub_act_frame_t *sd_act_frm = NULL;
++	wl_event_rx_frame_data_t *rxframe;
++	u32 event;
++	u8 *mgmt_frame;
++	u8 bsscfgidx;
++	u32 mgmt_frame_len;
++	u16 channel;
++	if (ntoh32(e->datalen) < sizeof(wl_event_rx_frame_data_t)) {
++		WL_ERR(("wrong datalen:%d\n", ntoh32(e->datalen)));
++		return -EINVAL;
++	}
++	mgmt_frame_len = ntoh32(e->datalen) - sizeof(wl_event_rx_frame_data_t);
++	event = ntoh32(e->event_type);
++	bsscfgidx = e->bsscfgidx;
++	rxframe = (wl_event_rx_frame_data_t *)data;
++	if (!rxframe) {
++		WL_ERR(("rxframe: NULL\n"));
++		return -EINVAL;
++	}
++	channel = (ntoh16(rxframe->channel) & WL_CHANSPEC_CHAN_MASK);
++	memset(&bssid, 0, ETHER_ADDR_LEN);
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++	if ((ndev->ieee80211_ptr->iftype != NL80211_IFTYPE_AP) &&
++		(event == WLC_E_PROBREQ_MSG)) {
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++		struct net_info *iter, *next;
++		for_each_ndev(cfg, iter, next) {
++			if (iter->ndev && iter->wdev &&
++					iter->wdev->iftype == NL80211_IFTYPE_AP) {
++					ndev = iter->ndev;
++					cfgdev =  ndev_to_cfgdev(ndev);
++					break;
++			}
++		}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	}
++
++	if (channel <= CH_MAX_2G_CHANNEL)
++		band = wiphy->bands[IEEE80211_BAND_2GHZ];
++	else
++		band = wiphy->bands[IEEE80211_BAND_5GHZ];
++	if (!band) {
++		WL_ERR(("No valid band\n"));
++		return -EINVAL;
++	}
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39)
++	freq = ieee80211_channel_to_frequency(channel);
++	(void)band->band;
++#else
++	freq = ieee80211_channel_to_frequency(channel, band->band);
++#endif
++	if (event == WLC_E_ACTION_FRAME_RX) {
++		if ((err = wldev_iovar_getbuf_bsscfg(ndev, "cur_etheraddr",
++			NULL, 0, cfg->ioctl_buf, WLC_IOCTL_SMLEN, bsscfgidx,
++			&cfg->ioctl_buf_sync)) != BCME_OK) {
++			WL_ERR(("WLC_GET_CUR_ETHERADDR failed, error %d\n", err));
++			goto exit;
++		}
++
++		err = wldev_ioctl_get(ndev, WLC_GET_BSSID, &bssid, ETHER_ADDR_LEN);
++		if (err < 0)
++			 WL_ERR(("WLC_GET_BSSID error %d\n", err));
++		memcpy(da.octet, cfg->ioctl_buf, ETHER_ADDR_LEN);
++		err = wl_frame_get_mgmt(FC_ACTION, &da, &e->addr, &bssid,
++			&mgmt_frame, &mgmt_frame_len,
++			(u8 *)((wl_event_rx_frame_data_t *)rxframe + 1));
++		if (err < 0) {
++			WL_ERR(("Error in receiving action frame len %d channel %d freq %d\n",
++				mgmt_frame_len, channel, freq));
++			goto exit;
++		}
++		isfree = true;
++		if (wl_cfgp2p_is_pub_action(&mgmt_frame[DOT11_MGMT_HDR_LEN],
++			mgmt_frame_len - DOT11_MGMT_HDR_LEN)) {
++			act_frm = (wifi_p2p_pub_act_frame_t *)
++					(&mgmt_frame[DOT11_MGMT_HDR_LEN]);
++		} else if (wl_cfgp2p_is_p2p_action(&mgmt_frame[DOT11_MGMT_HDR_LEN],
++			mgmt_frame_len - DOT11_MGMT_HDR_LEN)) {
++			p2p_act_frm = (wifi_p2p_action_frame_t *)
++					(&mgmt_frame[DOT11_MGMT_HDR_LEN]);
++			(void) p2p_act_frm;
++		} else if (wl_cfgp2p_is_gas_action(&mgmt_frame[DOT11_MGMT_HDR_LEN],
++			mgmt_frame_len - DOT11_MGMT_HDR_LEN)) {
++
++			sd_act_frm = (wifi_p2psd_gas_pub_act_frame_t *)
++					(&mgmt_frame[DOT11_MGMT_HDR_LEN]);
++			if (sd_act_frm && wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM)) {
++				if (cfg->next_af_subtype == sd_act_frm->action) {
++					WL_DBG(("We got a right next frame of SD!(%d)\n",
++						sd_act_frm->action));
++					wl_clr_drv_status(cfg, WAITING_NEXT_ACT_FRM, ndev);
++
++					/* Stop waiting for next AF. */
++					wl_stop_wait_next_action_frame(cfg, ndev, bsscfgidx);
++				}
++			}
++			(void) sd_act_frm;
++#ifdef WLTDLS
++		} else if ((mgmt_frame[DOT11_MGMT_HDR_LEN] == TDLS_AF_CATEGORY) ||
++				(wl_cfg80211_is_tdls_tunneled_frame(
++				    &mgmt_frame[DOT11_MGMT_HDR_LEN],
++				    mgmt_frame_len - DOT11_MGMT_HDR_LEN))) {
++			if (mgmt_frame[DOT11_MGMT_HDR_LEN] == TDLS_AF_CATEGORY) {
++				WL_ERR((" TDLS Action Frame Received type = %d \n",
++					mgmt_frame[DOT11_MGMT_HDR_LEN + 1]));
++			}
++#ifdef TDLS_MSG_ONLY_WFD
++			if (!dhdp->tdls_mode) {
++				WL_DBG((" TDLS Frame filtered \n"));
++				return 0;
++			}
++#else
++			if (mgmt_frame[DOT11_MGMT_HDR_LEN + 1] == TDLS_ACTION_SETUP_RESP) {
++				cfg->tdls_mgmt_frame = mgmt_frame;
++				cfg->tdls_mgmt_frame_len = mgmt_frame_len;
++				cfg->tdls_mgmt_freq = freq;
++				return 0;
++			}
++#endif /* TDLS_MSG_ONLY_WFD */
++#endif /* WLTDLS */
++#ifdef QOS_MAP_SET
++		} else if (mgmt_frame[DOT11_MGMT_HDR_LEN] == DOT11_ACTION_CAT_QOS) {
++			/* update QoS map set table */
++			bcm_tlv_t * qos_map_ie = NULL;
++			if ((qos_map_ie = bcm_parse_tlvs(&mgmt_frame[DOT11_MGMT_HDR_LEN],
++					mgmt_frame_len - DOT11_MGMT_HDR_LEN,
++					DOT11_MNG_QOS_MAP_ID)) != NULL) {
++				WL_DBG((" QoS map set IE found in QoS action frame\n"));
++				if (!cfg->up_table) {
++					cfg->up_table = kmalloc(UP_TABLE_MAX, GFP_KERNEL);
++				}
++				wl_set_up_table(cfg->up_table, qos_map_ie);
++			} else {
++				kfree(cfg->up_table);
++				cfg->up_table = NULL;
++			}
++#endif /* QOS_MAP_SET */
++#ifdef WBTEXT
++		} else if (mgmt_frame[DOT11_MGMT_HDR_LEN] == DOT11_ACTION_CAT_RRM) {
++			/* radio measurement category */
++			switch (mgmt_frame[DOT11_MGMT_HDR_LEN+1]) {
++				case DOT11_RM_ACTION_NR_REP:
++					if (wl_cfg80211_recv_nbr_resp(ndev,
++							&mgmt_frame[DOT11_MGMT_HDR_LEN],
++							mgmt_frame_len - DOT11_MGMT_HDR_LEN)
++							== BCME_OK) {
++						WL_DBG(("RCC updated by nbr response\n"));
++					}
++					break;
++				default:
++					break;
++			}
++#endif /* WBTEXT */
++		} else {
++			/*
++			 *  if we got normal action frame and ndev is p2p0,
++			 *  we have to change ndev from p2p0 to wlan0
++			 */
++
++
++			if (cfg->next_af_subtype != P2P_PAF_SUBTYPE_INVALID) {
++				u8 action = 0;
++				if (wl_get_public_action(&mgmt_frame[DOT11_MGMT_HDR_LEN],
++					mgmt_frame_len - DOT11_MGMT_HDR_LEN, &action) != BCME_OK) {
++					WL_DBG(("Recived action is not public action frame\n"));
++				} else if (cfg->next_af_subtype == action) {
++					WL_DBG(("Recived action is the waiting action(%d)\n",
++						action));
++					wl_clr_drv_status(cfg, WAITING_NEXT_ACT_FRM, ndev);
++
++					/* Stop waiting for next AF. */
++					wl_stop_wait_next_action_frame(cfg, ndev, bsscfgidx);
++				}
++			}
++		}
++
++		if (act_frm) {
++
++			if (wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM)) {
++				if (cfg->next_af_subtype == act_frm->subtype) {
++					WL_DBG(("We got a right next frame!(%d)\n",
++						act_frm->subtype));
++					wl_clr_drv_status(cfg, WAITING_NEXT_ACT_FRM, ndev);
++
++					if (cfg->next_af_subtype == P2P_PAF_GON_CONF) {
++						OSL_SLEEP(20);
++					}
++
++					/* Stop waiting for next AF. */
++					wl_stop_wait_next_action_frame(cfg, ndev, bsscfgidx);
++				}
++			}
++		}
++
++		wl_cfgp2p_print_actframe(false, &mgmt_frame[DOT11_MGMT_HDR_LEN],
++			mgmt_frame_len - DOT11_MGMT_HDR_LEN, channel);
++		if (act_frm && (act_frm->subtype == P2P_PAF_GON_CONF)) {
++			WL_DBG(("P2P: GO_NEG_PHASE status cleared \n"));
++			wl_clr_p2p_status(cfg, GO_NEG_PHASE);
++		}
++	} else if (event == WLC_E_PROBREQ_MSG) {
++
++		/* Handle probe reqs frame
++		 * WPS-AP certification 4.2.13
++		 */
++		struct parsed_ies prbreq_ies;
++		u32 prbreq_ie_len = 0;
++		bool pbc = 0;
++
++		WL_DBG((" Event WLC_E_PROBREQ_MSG received\n"));
++		mgmt_frame = (u8 *)(data);
++		mgmt_frame_len = ntoh32(e->datalen);
++		if (mgmt_frame_len < DOT11_MGMT_HDR_LEN) {
++			WL_ERR(("wrong datalen:%d\n", mgmt_frame_len));
++			return -EINVAL;
++		}
++		prbreq_ie_len = mgmt_frame_len - DOT11_MGMT_HDR_LEN;
++
++		/* Parse prob_req IEs */
++		if (wl_cfg80211_parse_ies(&mgmt_frame[DOT11_MGMT_HDR_LEN],
++			prbreq_ie_len, &prbreq_ies) < 0) {
++			WL_ERR(("Prob req get IEs failed\n"));
++			return 0;
++		}
++		if (prbreq_ies.wps_ie != NULL) {
++			wl_validate_wps_ie((char *)prbreq_ies.wps_ie, prbreq_ies.wps_ie_len, &pbc);
++			WL_DBG((" wps_ie exist pbc = %d\n", pbc));
++			/* if pbc method, send prob_req mgmt frame to upper layer */
++			if (!pbc)
++				return 0;
++		} else
++			return 0;
++	} else {
++		mgmt_frame = (u8 *)((wl_event_rx_frame_data_t *)rxframe + 1);
++
++		/* wpa supplicant use probe request event for restarting another GON Req.
++		 * but it makes GON Req repetition.
++		 * so if src addr of prb req is same as my target device,
++		 * do not send probe request event during sending action frame.
++		 */
++		if (event == WLC_E_P2P_PROBREQ_MSG) {
++			WL_DBG((" Event %s\n", (event == WLC_E_P2P_PROBREQ_MSG) ?
++				"WLC_E_P2P_PROBREQ_MSG":"WLC_E_PROBREQ_MSG"));
++
++
++			/* Filter any P2P probe reqs arriving during the
++			 * GO-NEG Phase
++			 */
++			if (cfg->p2p &&
++#if defined(P2P_IE_MISSING_FIX)
++				cfg->p2p_prb_noti &&
++#endif
++				wl_get_p2p_status(cfg, GO_NEG_PHASE)) {
++				WL_DBG(("Filtering P2P probe_req while "
++					"being in GO-Neg state\n"));
++				return 0;
++			}
++		}
++	}
++
++	if (discover_cfgdev(cfgdev, cfg))
++		WL_DBG(("Rx Managment frame For P2P Discovery Interface \n"));
++	else
++		WL_DBG(("Rx Managment frame For Iface (%s) \n", ndev->name));
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
++	 cfg80211_rx_mgmt(cfgdev, freq, 0,  mgmt_frame, mgmt_frame_len, 0);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 12, 0))
++	cfg80211_rx_mgmt(cfgdev, freq, 0,  mgmt_frame, mgmt_frame_len, 0, GFP_ATOMIC);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) || \
++	defined(WL_COMPAT_WIRELESS)
++	cfg80211_rx_mgmt(cfgdev, freq, 0, mgmt_frame, mgmt_frame_len, GFP_ATOMIC);
++#else
++	cfg80211_rx_mgmt(cfgdev, freq, mgmt_frame, mgmt_frame_len, GFP_ATOMIC);
++#endif /* LINUX_VERSION >= VERSION(3, 18, 0) */
++
++	WL_DBG(("mgmt_frame_len (%d) , e->datalen (%d), channel (%d), freq (%d)\n",
++		mgmt_frame_len, ntoh32(e->datalen), channel, freq));
++exit:
++	if (isfree)
++		kfree(mgmt_frame);
++	return err;
++}
++
++#ifdef WL_SCHED_SCAN
++/* If target scan is not reliable, set the below define to "1" to do a
++ * full escan
++ */
++#define FULL_ESCAN_ON_PFN_NET_FOUND		0
++static s32
++wl_notify_sched_scan_results(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data)
++{
++	wl_pfn_net_info_v2_t *netinfo, *pnetinfo;
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++	int err = 0;
++	struct cfg80211_scan_request *request = NULL;
++	struct cfg80211_ssid ssid[MAX_PFN_LIST_COUNT];
++	struct ieee80211_channel *channel = NULL;
++	int channel_req = 0;
++	int band = 0;
++	wl_pfn_scanresults_t *pfn_result = (wl_pfn_scanresults_t *)data;
++	int n_pfn_results = pfn_result->count;
++	log_conn_event_t *event_data = NULL;
++	tlv_log *tlv_data = NULL;
++	u32 alloc_len, tlv_len;
++	u32 payload_len;
++
++	WL_DBG(("Enter\n"));
++
++	if (pfn_result->version != PFN_SCANRESULT_VERSION) {
++		WL_ERR(("Incorrect version %d, expected %d\n", pfn_result->version,
++		       PFN_SCANRESULT_VERSION));
++		return BCME_VERSION;
++	}
++
++	if (e->event_type == WLC_E_PFN_NET_LOST) {
++		WL_PNO(("PFN NET LOST event. Do Nothing\n"));
++		return 0;
++	}
++
++	WL_PNO((">>> PFN NET FOUND event. count:%d \n", n_pfn_results));
++	if (n_pfn_results > 0) {
++		int i;
++
++		if (n_pfn_results > MAX_PFN_LIST_COUNT)
++			n_pfn_results = MAX_PFN_LIST_COUNT;
++		pnetinfo = (wl_pfn_net_info_v2_t *)((char *)data + sizeof(wl_pfn_scanresults_v2_t)
++				- sizeof(wl_pfn_net_info_v2_t));
++
++		memset(&ssid, 0x00, sizeof(ssid));
++
++		request = kzalloc(sizeof(*request)
++			+ sizeof(*request->channels) * n_pfn_results,
++			GFP_KERNEL);
++		channel = (struct ieee80211_channel *)kzalloc(
++			(sizeof(struct ieee80211_channel) * n_pfn_results),
++			GFP_KERNEL);
++		if (!request || !channel) {
++			WL_ERR(("No memory"));
++			err = -ENOMEM;
++			goto out_err;
++		}
++
++		request->wiphy = wiphy;
++
++		if (DBG_RING_ACTIVE(dhdp, DHD_EVENT_RING_ID)) {
++			alloc_len = sizeof(log_conn_event_t) + DOT11_MAX_SSID_LEN + sizeof(uint16) +
++				sizeof(int16);
++			event_data = MALLOC(dhdp->osh, alloc_len);
++			if (!event_data) {
++				WL_ERR(("%s: failed to allocate the log_conn_event_t with "
++					"length(%d)\n", __func__, alloc_len));
++				goto out_err;
++			}
++			tlv_len = 3 * sizeof(tlv_log);
++			event_data->tlvs = MALLOC(dhdp->osh, tlv_len);
++			if (!event_data->tlvs) {
++				WL_ERR(("%s: failed to allocate the tlv_log with "
++					"length(%d)\n", __func__, tlv_len));
++				goto out_err;
++			}
++		}
++
++		for (i = 0; i < n_pfn_results; i++) {
++			netinfo = &pnetinfo[i];
++			if (!netinfo) {
++				WL_ERR(("Invalid netinfo ptr. index:%d", i));
++				err = -EINVAL;
++				goto out_err;
++			}
++			WL_PNO((">>> SSID:%s Channel:%d \n",
++				netinfo->pfnsubnet.u.SSID, netinfo->pfnsubnet.channel));
++			/* PFN result doesn't have all the info which are required by the supplicant
++			 * (For e.g IEs) Do a target Escan so that sched scan results are reported
++			 * via wl_inform_single_bss in the required format. Escan does require the
++			 * scan request in the form of cfg80211_scan_request. For timebeing, create
++			 * cfg80211_scan_request one out of the received PNO event.
++			 */
++			ssid[i].ssid_len = MIN(DOT11_MAX_SSID_LEN, netinfo->pfnsubnet.SSID_len);
++			memcpy(ssid[i].ssid, netinfo->pfnsubnet.u.SSID,
++				ssid[i].ssid_len);
++			request->n_ssids++;
++
++			channel_req = netinfo->pfnsubnet.channel;
++			band = (channel_req <= CH_MAX_2G_CHANNEL) ? NL80211_BAND_2GHZ
++				: NL80211_BAND_5GHZ;
++			channel[i].center_freq = ieee80211_channel_to_frequency(channel_req, band);
++			channel[i].band = band;
++			channel[i].flags |= IEEE80211_CHAN_NO_HT40;
++			request->channels[i] = &channel[i];
++			request->n_channels++;
++
++			if (DBG_RING_ACTIVE(dhdp, DHD_EVENT_RING_ID)) {
++				payload_len = sizeof(log_conn_event_t);
++				event_data->event = WIFI_EVENT_DRIVER_PNO_NETWORK_FOUND;
++				tlv_data = event_data->tlvs;
++
++				/* ssid */
++				tlv_data->tag = WIFI_TAG_SSID;
++				tlv_data->len = netinfo->pfnsubnet.SSID_len;
++				memcpy(tlv_data->value, ssid[i].ssid, ssid[i].ssid_len);
++				payload_len += TLV_LOG_SIZE(tlv_data);
++				tlv_data = TLV_LOG_NEXT(tlv_data);
++
++				/* channel */
++				tlv_data->tag = WIFI_TAG_CHANNEL;
++				tlv_data->len = sizeof(uint16);
++				memcpy(tlv_data->value, &channel_req, sizeof(uint16));
++				payload_len += TLV_LOG_SIZE(tlv_data);
++				tlv_data = TLV_LOG_NEXT(tlv_data);
++
++				/* rssi */
++				tlv_data->tag = WIFI_TAG_RSSI;
++				tlv_data->len = sizeof(int16);
++				memcpy(tlv_data->value, &netinfo->RSSI, sizeof(int16));
++				payload_len += TLV_LOG_SIZE(tlv_data);
++				tlv_data = TLV_LOG_NEXT(tlv_data);
++
++				dhd_os_push_push_ring_data(dhdp, DHD_EVENT_RING_ID,
++					&event_data->event, payload_len);
++			}
++		}
++
++		/* assign parsed ssid array */
++		if (request->n_ssids)
++			request->ssids = &ssid[0];
++
++		if (wl_get_drv_status_all(cfg, SCANNING)) {
++			/* Abort any on-going scan */
++			wl_notify_escan_complete(cfg, ndev, true, true);
++		}
++
++		if (wl_get_p2p_status(cfg, DISCOVERY_ON)) {
++			WL_PNO((">>> P2P discovery was ON. Disabling it\n"));
++			err = wl_cfgp2p_discover_enable_search(cfg, false);
++			if (unlikely(err)) {
++				wl_clr_drv_status(cfg, SCANNING, ndev);
++				goto out_err;
++			}
++			p2p_scan(cfg) = false;
++		}
++
++		wl_set_drv_status(cfg, SCANNING, ndev);
++#if FULL_ESCAN_ON_PFN_NET_FOUND
++		WL_PNO((">>> Doing Full ESCAN on PNO event\n"));
++		err = wl_do_escan(cfg, wiphy, ndev, NULL);
++#else
++		WL_PNO((">>> Doing targeted ESCAN on PNO event\n"));
++		err = wl_do_escan(cfg, wiphy, ndev, request);
++#endif
++		if (err) {
++			wl_clr_drv_status(cfg, SCANNING, ndev);
++			goto out_err;
++		}
++		DBG_EVENT_LOG(dhdp, WIFI_EVENT_DRIVER_PNO_SCAN_REQUESTED);
++		cfg->sched_scan_running = TRUE;
++	}
++	else {
++		WL_ERR(("FALSE PNO Event. (pfn_count == 0) \n"));
++	}
++out_err:
++	if (request)
++		kfree(request);
++	if (channel)
++		kfree(channel);
++
++	if (event_data) {
++		MFREE(dhdp->osh, event_data->tlvs, tlv_len);
++		MFREE(dhdp->osh, event_data, alloc_len);
++	}
++	return err;
++}
++#endif /* WL_SCHED_SCAN */
++
++static void wl_init_conf(struct wl_conf *conf)
++{
++	WL_DBG(("Enter \n"));
++	conf->frag_threshold = (u32)-1;
++	conf->rts_threshold = (u32)-1;
++	conf->retry_short = (u32)-1;
++	conf->retry_long = (u32)-1;
++	conf->tx_power = -1;
++}
++
++static void wl_init_prof(struct bcm_cfg80211 *cfg, struct net_device *ndev)
++{
++	unsigned long flags;
++	struct wl_profile *profile = wl_get_profile_by_netdev(cfg, ndev);
++
++	if (profile) {
++		spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++		memset(profile, 0, sizeof(struct wl_profile));
++		spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++	} else {
++		WL_ERR(("%s: No profile\n", __FUNCTION__));
++	}
++	return;
++}
++
++static void wl_init_event_handler(struct bcm_cfg80211 *cfg)
++{
++	memset(cfg->evt_handler, 0, sizeof(cfg->evt_handler));
++
++	cfg->evt_handler[WLC_E_SCAN_COMPLETE] = wl_notify_scan_status;
++	cfg->evt_handler[WLC_E_AUTH] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_ASSOC] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_LINK] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_DEAUTH_IND] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_DEAUTH] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_DISASSOC_IND] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_ASSOC_IND] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_REASSOC_IND] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_ROAM] = wl_notify_roaming_status;
++	cfg->evt_handler[WLC_E_MIC_ERROR] = wl_notify_mic_status;
++	cfg->evt_handler[WLC_E_SET_SSID] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_ACTION_FRAME_RX] = wl_notify_rx_mgmt_frame;
++	cfg->evt_handler[WLC_E_PROBREQ_MSG] = wl_notify_rx_mgmt_frame;
++	cfg->evt_handler[WLC_E_P2P_PROBREQ_MSG] = wl_notify_rx_mgmt_frame;
++	cfg->evt_handler[WLC_E_P2P_DISC_LISTEN_COMPLETE] = wl_cfgp2p_listen_complete;
++	cfg->evt_handler[WLC_E_ACTION_FRAME_COMPLETE] = wl_cfgp2p_action_tx_complete;
++	cfg->evt_handler[WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE] = wl_cfgp2p_action_tx_complete;
++	cfg->evt_handler[WLC_E_JOIN] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_START] = wl_notify_connect_status;
++#ifdef PNO_SUPPORT
++	cfg->evt_handler[WLC_E_PFN_NET_FOUND] = wl_notify_pfn_status;
++#endif /* PNO_SUPPORT */
++#ifdef GSCAN_SUPPORT
++	cfg->evt_handler[WLC_E_PFN_BEST_BATCHING] = wl_notify_gscan_event;
++	cfg->evt_handler[WLC_E_PFN_SCAN_COMPLETE] = wl_notify_gscan_event;
++	cfg->evt_handler[WLC_E_PFN_GSCAN_FULL_RESULT] = wl_notify_gscan_event;
++	cfg->evt_handler[WLC_E_PFN_BSSID_NET_FOUND] = wl_notify_gscan_event;
++	cfg->evt_handler[WLC_E_PFN_BSSID_NET_LOST] = wl_notify_gscan_event;
++	cfg->evt_handler[WLC_E_PFN_SSID_EXT] = wl_notify_gscan_event;
++	cfg->evt_handler[WLC_E_GAS_FRAGMENT_RX] = wl_notify_gscan_event;
++	cfg->evt_handler[WLC_E_ROAM_EXP_EVENT] = wl_handle_roam_exp_event;
++#endif /* GSCAN_SUPPORT */
++#ifdef RSSI_MONITOR_SUPPORT
++	cfg->evt_handler[WLC_E_RSSI_LQM] = wl_handle_rssi_monitor_event;
++#endif /* RSSI_MONITOR_SUPPORT */
++#ifdef WLTDLS
++	cfg->evt_handler[WLC_E_TDLS_PEER_EVENT] = wl_tdls_event_handler;
++#endif /* WLTDLS */
++	cfg->evt_handler[WLC_E_BSSID] = wl_notify_roaming_status;
++#ifdef	WL_RELMCAST
++	cfg->evt_handler[WLC_E_RMC_EVENT] = wl_notify_rmc_status;
++#endif /* WL_RELMCAST */
++#ifdef BT_WIFI_HANDOVER
++	cfg->evt_handler[WLC_E_BT_WIFI_HANDOVER_REQ] = wl_notify_bt_wifi_handover_req;
++#endif
++	cfg->evt_handler[WLC_E_CSA_COMPLETE_IND] = wl_csa_complete_ind;
++	cfg->evt_handler[WLC_E_AP_STARTED] = wl_ap_start_ind;
++#ifdef CUSTOM_EVENT_PM_WAKE
++	cfg->evt_handler[WLC_E_EXCESS_PM_WAKE_EVENT] = wl_check_pmstatus;
++#endif	/* CUSTOM_EVENT_PM_WAKE */
++#if defined(DHD_LOSSLESS_ROAMING) || defined(DBG_PKT_MON)
++	cfg->evt_handler[WLC_E_ROAM_PREP] = wl_notify_roam_prep_status;
++#endif /* DHD_LOSSLESS_ROAMING || DBG_PKT_MON  */
++#ifdef ENABLE_TEMP_THROTTLING
++	cfg->evt_handler[WLC_E_TEMP_THROTTLE] = wl_check_rx_throttle_status;
++#endif /* ENABLE_TEMP_THROTTLING */
++#ifdef WL_SAE
++	cfg->evt_handler[WLC_E_AUTH_IND] = wl_notify_connect_status;
++#endif /* WL_SAE */
++}
++
++#if defined(STATIC_WL_PRIV_STRUCT)
++static int
++wl_init_escan_result_buf(struct bcm_cfg80211 *cfg)
++{
++	cfg->escan_info.escan_buf = DHD_OS_PREALLOC(cfg->pub,
++		DHD_PREALLOC_WIPHY_ESCAN0, ESCAN_BUF_SIZE);
++	if (cfg->escan_info.escan_buf == NULL) {
++		WL_ERR(("Failed to alloc ESCAN_BUF\n"));
++		return -ENOMEM;
++	}
++	bzero(cfg->escan_info.escan_buf, ESCAN_BUF_SIZE);
++
++	return 0;
++}
++
++static void
++wl_deinit_escan_result_buf(struct bcm_cfg80211 *cfg)
++{
++	if (cfg->escan_info.escan_buf != NULL) {
++		cfg->escan_info.escan_buf = NULL;
++	}
++}
++#endif /* STATIC_WL_PRIV_STRUCT */
++
++static s32 wl_init_priv_mem(struct bcm_cfg80211 *cfg)
++{
++	WL_DBG(("Enter \n"));
++
++	cfg->scan_results = (void *)kzalloc(WL_SCAN_BUF_MAX, GFP_KERNEL);
++	if (unlikely(!cfg->scan_results)) {
++		WL_ERR(("Scan results alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++	cfg->conf = (void *)kzalloc(sizeof(*cfg->conf), GFP_KERNEL);
++	if (unlikely(!cfg->conf)) {
++		WL_ERR(("wl_conf alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++	cfg->scan_req_int =
++	    (void *)kzalloc(sizeof(*cfg->scan_req_int), GFP_KERNEL);
++	if (unlikely(!cfg->scan_req_int)) {
++		WL_ERR(("Scan req alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++	cfg->ioctl_buf = (void *)kzalloc(WLC_IOCTL_MAXLEN, GFP_KERNEL);
++	if (unlikely(!cfg->ioctl_buf)) {
++		WL_ERR(("Ioctl buf alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++	cfg->escan_ioctl_buf = (void *)kzalloc(WLC_IOCTL_MAXLEN, GFP_KERNEL);
++	if (unlikely(!cfg->escan_ioctl_buf)) {
++		WL_ERR(("Ioctl buf alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++	cfg->extra_buf = (void *)kzalloc(WL_EXTRA_BUF_MAX, GFP_KERNEL);
++	if (unlikely(!cfg->extra_buf)) {
++		WL_ERR(("Extra buf alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++	cfg->pmk_list = (void *)kzalloc(sizeof(*cfg->pmk_list), GFP_KERNEL);
++	if (unlikely(!cfg->pmk_list)) {
++		WL_ERR(("pmk list alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++#if defined(STATIC_WL_PRIV_STRUCT)
++	cfg->conn_info = (void *)kzalloc(sizeof(*cfg->conn_info), GFP_KERNEL);
++	if (unlikely(!cfg->conn_info)) {
++		WL_ERR(("cfg->conn_info  alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++	cfg->ie = (void *)kzalloc(sizeof(*cfg->ie), GFP_KERNEL);
++	if (unlikely(!cfg->ie)) {
++		WL_ERR(("cfg->ie  alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++	if (unlikely(wl_init_escan_result_buf(cfg))) {
++		WL_ERR(("Failed to init escan resul buf\n"));
++		goto init_priv_mem_out;
++	}
++#endif /* STATIC_WL_PRIV_STRUCT */
++	cfg->afx_hdl = (void *)kzalloc(sizeof(*cfg->afx_hdl), GFP_KERNEL);
++	if (unlikely(!cfg->afx_hdl)) {
++		WL_ERR(("afx hdl  alloc failed\n"));
++		goto init_priv_mem_out;
++	} else {
++		init_completion(&cfg->act_frm_scan);
++		init_completion(&cfg->wait_next_af);
++
++		INIT_WORK(&cfg->afx_hdl->work, wl_cfg80211_afx_handler);
++	}
++#ifdef WLTDLS
++	if (cfg->tdls_mgmt_frame) {
++		kfree(cfg->tdls_mgmt_frame);
++		cfg->tdls_mgmt_frame = NULL;
++	}
++#endif /* WLTDLS */
++	return 0;
++
++init_priv_mem_out:
++	wl_deinit_priv_mem(cfg);
++
++	return -ENOMEM;
++}
++
++static void wl_deinit_priv_mem(struct bcm_cfg80211 *cfg)
++{
++	kfree(cfg->scan_results);
++	cfg->scan_results = NULL;
++	kfree(cfg->conf);
++	cfg->conf = NULL;
++	kfree(cfg->scan_req_int);
++	cfg->scan_req_int = NULL;
++	kfree(cfg->ioctl_buf);
++	cfg->ioctl_buf = NULL;
++	kfree(cfg->escan_ioctl_buf);
++	cfg->escan_ioctl_buf = NULL;
++	kfree(cfg->extra_buf);
++	cfg->extra_buf = NULL;
++	kfree(cfg->pmk_list);
++	cfg->pmk_list = NULL;
++#if defined(STATIC_WL_PRIV_STRUCT)
++	kfree(cfg->conn_info);
++	cfg->conn_info = NULL;
++	kfree(cfg->ie);
++	cfg->ie = NULL;
++	wl_deinit_escan_result_buf(cfg);
++#endif /* STATIC_WL_PRIV_STRUCT */
++	if (cfg->afx_hdl) {
++		cancel_work_sync(&cfg->afx_hdl->work);
++		kfree(cfg->afx_hdl);
++		cfg->afx_hdl = NULL;
++	}
++
++}
++
++static s32 wl_create_event_handler(struct bcm_cfg80211 *cfg)
++{
++	int ret = 0;
++	WL_DBG(("Enter \n"));
++
++	/* Allocate workqueue for event */
++	if (!cfg->event_workq) {
++		cfg->event_workq = alloc_workqueue("dhd_eventd", WQ_MEM_RECLAIM | WQ_HIGHPRI, 0);
++	}
++
++	if (!cfg->event_workq) {
++		WL_ERR(("event_workq alloc_workqueue failed\n"));
++		ret = -ENOMEM;
++	} else {
++		INIT_WORK(&cfg->event_work, wl_event_handler);
++	}
++	return ret;
++}
++
++static void wl_destroy_event_handler(struct bcm_cfg80211 *cfg)
++{
++	if (cfg && cfg->event_workq) {
++		cancel_work_sync(&cfg->event_work);
++		destroy_workqueue(cfg->event_workq);
++		cfg->event_workq = NULL;
++	}
++}
++
++void wl_terminate_event_handler(struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++
++	if (cfg) {
++		wl_destroy_event_handler(cfg);
++		wl_flush_eq(cfg);
++	}
++}
++
++static void wl_scan_timeout(unsigned long data)
++{
++	wl_event_msg_t msg;
++	struct bcm_cfg80211 *cfg = (struct bcm_cfg80211 *)data;
++	struct wireless_dev *wdev = NULL;
++	struct net_device *ndev = NULL;
++	struct wl_scan_results *bss_list;
++	struct wl_bss_info *bi = NULL;
++	s32 i;
++	u32 channel;
++#if 0
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++	uint32 prev_memdump_mode = dhdp->memdump_enabled;
++#endif /* DHD_DEBUG && DHD_FW_COREDUMP */
++
++	if (!(cfg->scan_request)) {
++		WL_ERR(("timer expired but no scan request\n"));
++		return;
++	}
++
++	bss_list = wl_escan_get_buf(cfg, FALSE);
++	if (!bss_list) {
++		WL_ERR(("bss_list is null. Didn't receive any partial scan results\n"));
++	} else {
++		WL_ERR(("scanned AP count (%d)\n", bss_list->count));
++
++		bi = next_bss(bss_list, bi);
++		for_each_bss(bss_list, bi, i) {
++			channel = wf_chspec_ctlchan(wl_chspec_driver_to_host(bi->chanspec));
++			WL_ERR(("SSID :%s  Channel :%d\n", bi->SSID, channel));
++		}
++	}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++	if (cfg->scan_request->dev)
++		wdev = cfg->scan_request->dev->ieee80211_ptr;
++#else
++	wdev = cfg->scan_request->wdev;
++#endif /* LINUX_VERSION < KERNEL_VERSION(3, 6, 0) */
++	if (!wdev) {
++		WL_ERR(("No wireless_dev present\n"));
++		return;
++	}
++	ndev = wdev_to_wlc_ndev(wdev, cfg);
++
++	bzero(&msg, sizeof(wl_event_msg_t));
++	WL_ERR(("timer expired\n"));
++#if 0
++	if (dhdp->memdump_enabled) {
++		dhdp->memdump_enabled = DUMP_MEMFILE;
++		dhdp->memdump_type = DUMP_TYPE_SCAN_TIMEOUT;
++		dhd_bus_mem_dump(dhdp);
++		dhdp->memdump_enabled = prev_memdump_mode;
++	}
++#endif /* DHD_DEBUG && DHD_FW_COREDUMP */
++	msg.event_type = hton32(WLC_E_ESCAN_RESULT);
++	msg.status = hton32(WLC_E_STATUS_TIMEOUT);
++	msg.reason = 0xFFFFFFFF;
++	wl_cfg80211_event(ndev, &msg, NULL);
++#ifdef CUSTOMER_HW4_DEBUG
++	if (!wl_scan_timeout_dbg_enabled)
++		wl_scan_timeout_dbg_set();
++#endif /* CUSTOMER_HW4_DEBUG */
++
++	// terence 20130729: workaround to fix out of memory in firmware
++//	if (dhd_conf_get_chip(dhd_get_pub(ndev)) == BCM43362_CHIP_ID) {
++//		WL_ERR(("Send hang event\n"));
++//		net_os_send_hang_message(ndev);
++//	}
++}
++
++#ifdef DHD_LOSSLESS_ROAMING
++static void wl_del_roam_timeout(struct bcm_cfg80211 *cfg)
++{
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++
++	/* restore prec_map to ALLPRIO */
++	dhdp->dequeue_prec_map = ALLPRIO;
++	if (timer_pending(&cfg->roam_timeout)) {
++		_del_timer_sync(&cfg->roam_timeout);
++	}
++
++}
++
++static void wl_roam_timeout(unsigned long data)
++{
++	struct bcm_cfg80211 *cfg = (struct bcm_cfg80211 *)data;
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++
++	WL_ERR(("roam timer expired\n"));
++
++	/* restore prec_map to ALLPRIO */
++	dhdp->dequeue_prec_map = ALLPRIO;
++}
++
++#endif /* DHD_LOSSLESS_ROAMING */
++
++static s32
++wl_cfg80211_netdev_notifier_call(struct notifier_block * nb,
++	unsigned long state, void *ptr)
++{
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0))
++	struct net_device *dev = ptr;
++#else
++	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
++#endif /* LINUX_VERSION < VERSION(3, 11, 0) */
++	struct wireless_dev *wdev = ndev_to_wdev(dev);
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++
++	WL_DBG(("Enter \n"));
++
++	if (!wdev || !cfg || dev == bcmcfg_to_prmry_ndev(cfg))
++		return NOTIFY_DONE;
++
++	switch (state) {
++		case NETDEV_DOWN:
++		{
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0))
++			int max_wait_timeout = 2;
++			int max_wait_count = 100;
++			int refcnt = 0;
++			unsigned long limit = jiffies + max_wait_timeout * HZ;
++			while (work_pending(&wdev->cleanup_work)) {
++				if (refcnt%5 == 0) {
++					WL_ERR(("[NETDEV_DOWN] wait for "
++						"complete of cleanup_work"
++						" (%d th)\n", refcnt));
++				}
++				if (!time_before(jiffies, limit)) {
++					WL_ERR(("[NETDEV_DOWN] cleanup_work"
++						" of CFG80211 is not"
++						" completed in %d sec\n",
++						max_wait_timeout));
++					break;
++				}
++				if (refcnt >= max_wait_count) {
++					WL_ERR(("[NETDEV_DOWN] cleanup_work"
++						" of CFG80211 is not"
++						" completed in %d loop\n",
++						max_wait_count));
++					break;
++				}
++				set_current_state(TASK_INTERRUPTIBLE);
++				(void)schedule_timeout(100);
++				set_current_state(TASK_RUNNING);
++				refcnt++;
++			}
++#endif /* LINUX_VERSION < VERSION(3, 14, 0) */
++			break;
++		}
++		case NETDEV_UNREGISTER:
++			/* after calling list_del_rcu(&wdev->list) */
++			wl_cfg80211_clear_per_bss_ies(cfg,
++				wl_get_bssidx_by_wdev(cfg, wdev));
++			wl_dealloc_netinfo_by_wdev(cfg, wdev);
++			break;
++		case NETDEV_GOING_DOWN:
++			/*
++			 * At NETDEV_DOWN state, wdev_cleanup_work work will be called.
++			 * In front of door, the function checks whether current scan
++			 * is working or not. If the scanning is still working,
++			 * wdev_cleanup_work call WARN_ON and make the scan done forcibly.
++			 */
++			if (wl_get_drv_status(cfg, SCANNING, dev))
++				wl_notify_escan_complete(cfg, dev, true, true);
++			break;
++	}
++	return NOTIFY_DONE;
++}
++
++static struct notifier_block wl_cfg80211_netdev_notifier = {
++	.notifier_call = wl_cfg80211_netdev_notifier_call,
++};
++
++/*
++ * to make sure we won't register the same notifier twice, otherwise a loop is likely to be
++ * created in kernel notifier link list (with 'next' pointing to itself)
++ */
++static bool wl_cfg80211_netdev_notifier_registered = FALSE;
++
++static void wl_cfg80211_cancel_scan(struct bcm_cfg80211 *cfg)
++{
++	struct wireless_dev *wdev = NULL;
++	struct net_device *ndev = NULL;
++
++	if (!cfg->scan_request)
++		return;
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++	if (cfg->scan_request->dev)
++		wdev = cfg->scan_request->dev->ieee80211_ptr;
++#else
++	wdev = cfg->scan_request->wdev;
++#endif /* LINUX_VERSION < KERNEL_VERSION(3, 6, 0) */
++
++	if (!wdev) {
++		WL_ERR(("No wireless_dev present\n"));
++		return;
++	}
++
++	ndev = wdev_to_wlc_ndev(wdev, cfg);
++	wl_notify_escan_complete(cfg, ndev, true, true);
++	WL_ERR(("Scan aborted! \n"));
++}
++
++void wl_cfg80211_scan_abort(struct bcm_cfg80211 *cfg)
++{
++	wl_scan_params_t *params = NULL;
++	s32 params_size = 0;
++	s32 err = BCME_OK;
++	struct net_device *dev = bcmcfg_to_prmry_ndev(cfg);
++	if (!in_atomic()) {
++		/* Our scan params only need space for 1 channel and 0 ssids */
++		params = wl_cfg80211_scan_alloc_params(cfg, -1, 0, &params_size);
++		if (params == NULL) {
++			WL_ERR(("scan params allocation failed \n"));
++			err = -ENOMEM;
++		} else {
++			/* Do a scan abort to stop the driver's scan engine */
++			err = wldev_ioctl_set(dev, WLC_SCAN, params, params_size);
++			if (err < 0) {
++				WL_ERR(("scan abort  failed \n"));
++			}
++			kfree(params);
++		}
++	}
++#ifdef WLTDLS
++	if (cfg->tdls_mgmt_frame) {
++		kfree(cfg->tdls_mgmt_frame);
++		cfg->tdls_mgmt_frame = NULL;
++	}
++#endif /* WLTDLS */
++}
++
++static s32 wl_notify_escan_complete(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev,
++	bool aborted, bool fw_abort)
++{
++	s32 err = BCME_OK;
++	unsigned long flags;
++	struct net_device *dev;
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
++	struct cfg80211_scan_info info;
++	info.aborted = aborted;
++#endif
++
++	WL_DBG(("Enter \n"));
++	BCM_REFERENCE(dhdp);
++
++	mutex_lock(&cfg->scan_complete);
++
++	if (!ndev) {
++		WL_ERR(("ndev is null\n"));
++		err = BCME_ERROR;
++		goto out;
++	}
++
++	if (cfg->escan_info.ndev != ndev) {
++		WL_ERR(("ndev is different %p %p\n", cfg->escan_info.ndev, ndev));
++		err = BCME_ERROR;
++		goto out;
++	}
++
++	if (cfg->scan_request) {
++		dev = bcmcfg_to_prmry_ndev(cfg);
++#if defined(WL_ENABLE_P2P_IF)
++		if (cfg->scan_request->dev != cfg->p2p_net)
++			dev = cfg->scan_request->dev;
++#elif defined(WL_CFG80211_P2P_DEV_IF)
++		if (cfg->scan_request->wdev->iftype != NL80211_IFTYPE_P2P_DEVICE)
++			dev = cfg->scan_request->wdev->netdev;
++#endif /* WL_ENABLE_P2P_IF */
++	}
++	else {
++		WL_DBG(("cfg->scan_request is NULL may be internal scan."
++			"doing scan_abort for ndev %p primary %p",
++				ndev, bcmcfg_to_prmry_ndev(cfg)));
++		dev = ndev;
++	}
++	if (fw_abort && !in_atomic())
++		wl_cfg80211_scan_abort(cfg);
++	if (timer_pending(&cfg->scan_timeout))
++		_del_timer_sync(&cfg->scan_timeout);
++#if defined(ESCAN_RESULT_PATCH)
++	if (likely(cfg->scan_request)) {
++		cfg->bss_list = wl_escan_get_buf(cfg, aborted);
++		wl_inform_bss(cfg);
++	}
++#endif /* ESCAN_RESULT_PATCH */
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++#ifdef WL_SCHED_SCAN
++	if (cfg->sched_scan_req && !cfg->scan_request) {
++		WL_PNO((">>> REPORTING SCHED SCAN RESULTS \n"));
++		if (!aborted) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++			cfg80211_sched_scan_results(cfg->sched_scan_req->wiphy, 0);
++#else
++			cfg80211_sched_scan_results(cfg->sched_scan_req->wiphy);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)) */
++		}
++
++		DBG_EVENT_LOG(dhdp, WIFI_EVENT_DRIVER_PNO_SCAN_COMPLETE);
++		cfg->sched_scan_running = FALSE;
++	}
++#endif /* WL_SCHED_SCAN */
++	if (likely(cfg->scan_request)) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
++		cfg80211_scan_done(cfg->scan_request, &info);
++#else
++		cfg80211_scan_done(cfg->scan_request, aborted);
++#endif
++		cfg->scan_request = NULL;
++		DHD_OS_SCAN_WAKE_UNLOCK((dhd_pub_t *)(cfg->pub));
++		DHD_ENABLE_RUNTIME_PM((dhd_pub_t *)(cfg->pub));
++	}
++	if (p2p_is_on(cfg))
++		wl_clr_p2p_status(cfg, SCANNING);
++	wl_clr_drv_status(cfg, SCANNING, dev);
++	wake_up_interruptible(&dhdp->conf->event_complete);
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++
++out:
++	mutex_unlock(&cfg->scan_complete);
++	return err;
++}
++
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++#ifndef WL_DRV_AVOID_SCANCACHE
++static void
++wl_cfg80211_find_removal_candidate(wl_bss_info_t *bss, removal_element_t *candidate)
++{
++	int idx;
++	for (idx = 0; idx < BUF_OVERFLOW_MGMT_COUNT; idx++) {
++		int len = BUF_OVERFLOW_MGMT_COUNT - idx - 1;
++		if (bss->RSSI < candidate[idx].RSSI) {
++			if (len)
++				memcpy(&candidate[idx + 1], &candidate[idx],
++					sizeof(removal_element_t) * len);
++			candidate[idx].RSSI = bss->RSSI;
++			candidate[idx].length = bss->length;
++			memcpy(&candidate[idx].BSSID, &bss->BSSID, ETHER_ADDR_LEN);
++			return;
++		}
++	}
++}
++
++static void
++wl_cfg80211_remove_lowRSSI_info(wl_scan_results_t *list, removal_element_t *candidate,
++	wl_bss_info_t *bi)
++{
++	int idx1, idx2;
++	int total_delete_len = 0;
++	for (idx1 = 0; idx1 < BUF_OVERFLOW_MGMT_COUNT; idx1++) {
++		int cur_len = WL_SCAN_RESULTS_FIXED_SIZE;
++		wl_bss_info_t *bss = NULL;
++		if (candidate[idx1].RSSI >= bi->RSSI)
++			continue;
++		for (idx2 = 0; idx2 < list->count; idx2++) {
++			bss = bss ? (wl_bss_info_t *)((uintptr)bss + dtoh32(bss->length)) :
++				list->bss_info;
++			if (!bcmp(&candidate[idx1].BSSID, &bss->BSSID, ETHER_ADDR_LEN) &&
++				candidate[idx1].RSSI == bss->RSSI &&
++				candidate[idx1].length == dtoh32(bss->length)) {
++				u32 delete_len = dtoh32(bss->length);
++				WL_DBG(("delete scan info of " MACDBG " to add new AP\n",
++					MAC2STRDBG(bss->BSSID.octet)));
++				if (idx2 < list->count -1) {
++					memmove((u8 *)bss, (u8 *)bss + delete_len,
++						list->buflen - cur_len - delete_len);
++				}
++				list->buflen -= delete_len;
++				list->count--;
++				total_delete_len += delete_len;
++				/* if delete_len is greater than or equal to result length */
++				if (total_delete_len >= bi->length) {
++					return;
++				}
++				break;
++			}
++			cur_len += dtoh32(bss->length);
++		}
++	}
++}
++#endif /* WL_DRV_AVOID_SCANCACHE */
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++
++#ifdef WL_DRV_AVOID_SCANCACHE
++static u32 wl_p2p_find_peer_channel(struct bcm_cfg80211 *cfg, s32 status, wl_bss_info_t *bi,
++		u32 bi_length)
++{
++	u32 ret;
++	u8 *p2p_dev_addr = NULL;
++
++	ret = wl_get_drv_status_all(cfg, FINDING_COMMON_CHANNEL);
++	if (!ret) {
++		return ret;
++	}
++	if (status == WLC_E_STATUS_PARTIAL) {
++		p2p_dev_addr = wl_cfgp2p_retreive_p2p_dev_addr(bi, bi_length);
++		if (p2p_dev_addr && !memcmp(p2p_dev_addr,
++			cfg->afx_hdl->tx_dst_addr.octet, ETHER_ADDR_LEN)) {
++			s32 channel = wf_chspec_ctlchan(
++				wl_chspec_driver_to_host(bi->chanspec));
++
++			if ((channel > MAXCHANNEL) || (channel <= 0))
++				channel = WL_INVALID;
++			else
++				WL_ERR(("ACTION FRAME SCAN : Peer " MACDBG " found,"
++					" channel : %d\n",
++					MAC2STRDBG(cfg->afx_hdl->tx_dst_addr.octet),
++					channel));
++
++			wl_clr_p2p_status(cfg, SCANNING);
++			cfg->afx_hdl->peer_chan = channel;
++			complete(&cfg->act_frm_scan);
++		}
++	} else {
++		WL_INFORM(("ACTION FRAME SCAN DONE\n"));
++		wl_clr_p2p_status(cfg, SCANNING);
++		wl_clr_drv_status(cfg, SCANNING, cfg->afx_hdl->dev);
++		if (cfg->afx_hdl->peer_chan == WL_INVALID)
++			complete(&cfg->act_frm_scan);
++	}
++
++	return ret;
++}
++
++static s32 wl_escan_without_scan_cache(struct bcm_cfg80211 *cfg, wl_escan_result_t *escan_result,
++	struct net_device *ndev, const wl_event_msg_t *e, s32 status)
++{
++	s32 err = BCME_OK;
++	wl_bss_info_t *bi;
++	u32 bi_length;
++	bool aborted = false;
++	bool fw_abort = false;
++	bool notify_escan_complete = false;
++
++	if (wl_escan_check_sync_id(status, escan_result->sync_id,
++		cfg->escan_info.cur_sync_id) < 0) {
++		goto exit;
++	}
++
++	wl_escan_print_sync_id(status, escan_result->sync_id,
++			cfg->escan_info.cur_sync_id);
++
++	if (!(status == WLC_E_STATUS_TIMEOUT) || !(status == WLC_E_STATUS_PARTIAL)) {
++		cfg->escan_info.escan_state = WL_ESCAN_STATE_IDLE;
++	}
++
++	if ((likely(cfg->scan_request)) || (cfg->sched_scan_running)) {
++		notify_escan_complete = true;
++	}
++
++	if (status == WLC_E_STATUS_PARTIAL) {
++		WL_INFORM(("WLC_E_STATUS_PARTIAL \n"));
++		DBG_EVENT_LOG((dhd_pub_t *)cfg->pub, WIFI_EVENT_DRIVER_SCAN_RESULT_FOUND);
++		if ((!escan_result) || (dtoh16(escan_result->bss_count) != 1)) {
++			WL_ERR(("Invalid escan result (NULL pointer) or invalid bss_count\n"));
++			goto exit;
++		}
++
++		bi = escan_result->bss_info;
++		bi_length = dtoh32(bi->length);
++		if ((!bi) ||
++		(bi_length != (dtoh32(escan_result->buflen) - WL_ESCAN_RESULTS_FIXED_SIZE))) {
++			WL_ERR(("Invalid escan bss info (NULL pointer)"
++				"or invalid bss_info length\n"));
++			goto exit;
++		}
++
++		if (!(bcmcfg_to_wiphy(cfg)->interface_modes & BIT(NL80211_IFTYPE_ADHOC))) {
++			if (dtoh16(bi->capability) & DOT11_CAP_IBSS) {
++				WL_DBG(("Ignoring IBSS result\n"));
++				goto exit;
++			}
++		}
++
++		if (wl_p2p_find_peer_channel(cfg, status, bi, bi_length)) {
++			goto exit;
++		} else {
++			if (scan_req_match(cfg)) {
++				/* p2p scan && allow only probe response */
++				if ((cfg->p2p->search_state != WL_P2P_DISC_ST_SCAN) &&
++					(bi->flags & WL_BSS_FLAGS_FROM_BEACON))
++					goto exit;
++			}
++			err = wl_inform_single_bss(cfg, bi, false);
++
++			/*
++			 * !Broadcast && number of ssid = 1 && number of channels =1
++			 * means specific scan to association
++			 */
++			if (wl_cfgp2p_is_p2p_specific_scan(cfg->scan_request)) {
++				WL_ERR(("P2P assoc scan fast aborted.\n"));
++				aborted = false;
++				fw_abort = true;
++			}
++			/* Directly exit from function here and
++			* avoid sending notify completion to cfg80211
++			*/
++			goto exit;
++		}
++	} else if (status == WLC_E_STATUS_SUCCESS) {
++		if (wl_p2p_find_peer_channel(cfg, status, NULL, 0)) {
++			goto exit;
++		}
++		WL_INFORM(("ESCAN COMPLETED\n"));
++		DBG_EVENT_LOG((dhd_pub_t *)cfg->pub, WIFI_EVENT_DRIVER_SCAN_COMPLETE);
++
++		/* Update escan complete status */
++		aborted = false;
++		fw_abort = false;
++
++#ifdef CUSTOMER_HW4_DEBUG
++		if (wl_scan_timeout_dbg_enabled)
++			wl_scan_timeout_dbg_clear();
++#endif /* CUSTOMER_HW4_DEBUG */
++	} else if ((status == WLC_E_STATUS_ABORT) || (status == WLC_E_STATUS_NEWSCAN) ||
++		(status == WLC_E_STATUS_11HQUIET) || (status == WLC_E_STATUS_CS_ABORT) ||
++		(status == WLC_E_STATUS_NEWASSOC)) {
++		/* Handle all cases of scan abort */
++
++		WL_DBG(("ESCAN ABORT reason: %d\n", status));
++		if (wl_p2p_find_peer_channel(cfg, status, NULL, 0)) {
++			goto exit;
++		}
++		WL_INFORM(("ESCAN ABORTED\n"));
++
++		/* Update escan complete status */
++		aborted = true;
++		fw_abort = false;
++
++	} else if (status == WLC_E_STATUS_TIMEOUT) {
++		WL_ERR(("WLC_E_STATUS_TIMEOUT : scan_request[%p]\n", cfg->scan_request));
++		WL_ERR(("reason[0x%x]\n", e->reason));
++		if (e->reason == 0xFFFFFFFF) {
++			/* Update escan complete status */
++			aborted = true;
++			fw_abort = true;
++		}
++	} else {
++		WL_ERR(("unexpected Escan Event %d : abort\n", status));
++
++		if (wl_p2p_find_peer_channel(cfg, status, NULL, 0)) {
++			goto exit;
++		}
++		/* Update escan complete status */
++		aborted = true;
++		fw_abort = false;
++	}
++
++	/* Notify escan complete status */
++	if (notify_escan_complete) {
++		wl_notify_escan_complete(cfg, ndev, aborted, fw_abort);
++	}
++
++exit:
++	return err;
++
++}
++#endif /* WL_DRV_AVOID_SCANCACHE */
++
++static s32 wl_escan_handler(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	s32 err = BCME_OK;
++	s32 status = ntoh32(e->status);
++	wl_escan_result_t *escan_result;
++	struct net_device *ndev = NULL;
++#ifndef WL_DRV_AVOID_SCANCACHE
++	wl_bss_info_t *bi;
++	u32 bi_length;
++	wifi_p2p_ie_t * p2p_ie;
++	u8 *p2p_dev_addr = NULL;
++	wl_scan_results_t *list;
++	wl_bss_info_t *bss = NULL;
++	u32 i;
++#endif /* WL_DRV_AVOID_SCANCACHE */
++	u16 channel;
++	struct ieee80211_supported_band *band;
++
++	WL_DBG((" enter event type : %d, status : %d \n",
++		ntoh32(e->event_type), ntoh32(e->status)));
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	mutex_lock(&cfg->usr_sync);
++	/* P2P SCAN is coming from primary interface */
++	if (wl_get_p2p_status(cfg, SCANNING)) {
++		if (wl_get_drv_status_all(cfg, SENDING_ACT_FRM))
++			ndev = cfg->afx_hdl->dev;
++		else
++			ndev = cfg->escan_info.ndev;
++
++	}
++	if (!ndev || (!wl_get_drv_status(cfg, SCANNING, ndev) && !cfg->sched_scan_running)) {
++		WL_ERR_RLMT(("escan is not ready. drv_scan_status 0x%x"
++			" e_type %d e_states %d\n",
++			wl_get_drv_status(cfg, SCANNING, ndev),
++			ntoh32(e->event_type), ntoh32(e->status)));
++		goto exit;
++	}
++	escan_result = (wl_escan_result_t *)data;
++
++#ifndef WL_DRV_AVOID_SCANCACHE
++	if (status == WLC_E_STATUS_PARTIAL) {
++		WL_INFORM(("WLC_E_STATUS_PARTIAL \n"));
++		DBG_EVENT_LOG((dhd_pub_t *)cfg->pub, WIFI_EVENT_DRIVER_SCAN_RESULT_FOUND);
++		if (!escan_result) {
++			WL_ERR(("Invalid escan result (NULL pointer)\n"));
++			goto exit;
++		}
++		if ((dtoh32(escan_result->buflen) > (int)ESCAN_BUF_SIZE) ||
++		    (dtoh32(escan_result->buflen) < sizeof(wl_escan_result_t))) {
++			WL_ERR(("Invalid escan buffer len:%d\n", dtoh32(escan_result->buflen)));
++			goto exit;
++		}
++		if (dtoh16(escan_result->bss_count) != 1) {
++			WL_ERR(("Invalid bss_count %d: ignoring\n", escan_result->bss_count));
++			goto exit;
++		}
++		bi = escan_result->bss_info;
++		if (!bi) {
++			WL_ERR(("Invalid escan bss info (NULL pointer)\n"));
++			goto exit;
++		}
++		bi_length = dtoh32(bi->length);
++		if (bi_length != (dtoh32(escan_result->buflen) - WL_ESCAN_RESULTS_FIXED_SIZE)) {
++			WL_ERR(("Invalid bss_info length %d: ignoring\n", bi_length));
++			goto exit;
++		}
++
++		/* +++++ terence 20130524: skip invalid bss */
++		channel =
++			bi->ctl_ch ? bi->ctl_ch : CHSPEC_CHANNEL(wl_chspec_driver_to_host(bi->chanspec));
++		if (channel <= CH_MAX_2G_CHANNEL)
++			band = bcmcfg_to_wiphy(cfg)->bands[IEEE80211_BAND_2GHZ];
++		else
++			band = bcmcfg_to_wiphy(cfg)->bands[IEEE80211_BAND_5GHZ];
++		if (!band) {
++			WL_ERR(("No valid band\n"));
++			goto exit;
++		}
++		if (!dhd_conf_match_channel(cfg->pub, channel))
++			goto exit;
++		/* ----- terence 20130524: skip invalid bss */
++
++		if (wl_escan_check_sync_id(status, escan_result->sync_id,
++				cfg->escan_info.cur_sync_id) < 0)
++			goto exit;
++
++		if (!(bcmcfg_to_wiphy(cfg)->interface_modes & BIT(NL80211_IFTYPE_ADHOC))) {
++			if (dtoh16(bi->capability) & DOT11_CAP_IBSS) {
++				WL_DBG(("Ignoring IBSS result\n"));
++				goto exit;
++			}
++		}
++
++		if (wl_get_drv_status_all(cfg, FINDING_COMMON_CHANNEL)) {
++			p2p_dev_addr = wl_cfgp2p_retreive_p2p_dev_addr(bi, bi_length);
++			if (p2p_dev_addr && !memcmp(p2p_dev_addr,
++				cfg->afx_hdl->tx_dst_addr.octet, ETHER_ADDR_LEN)) {
++				s32 channel = wf_chspec_ctlchan(
++					wl_chspec_driver_to_host(bi->chanspec));
++
++				if ((channel > MAXCHANNEL) || (channel <= 0))
++					channel = WL_INVALID;
++				else
++					WL_ERR(("ACTION FRAME SCAN : Peer " MACDBG " found,"
++						" channel : %d\n",
++						MAC2STRDBG(cfg->afx_hdl->tx_dst_addr.octet),
++						channel));
++
++				wl_clr_p2p_status(cfg, SCANNING);
++				cfg->afx_hdl->peer_chan = channel;
++				complete(&cfg->act_frm_scan);
++				goto exit;
++			}
++
++		} else {
++			int cur_len = WL_SCAN_RESULTS_FIXED_SIZE;
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++			removal_element_t candidate[BUF_OVERFLOW_MGMT_COUNT];
++			int remove_lower_rssi = FALSE;
++
++			bzero(candidate, sizeof(removal_element_t)*BUF_OVERFLOW_MGMT_COUNT);
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++
++			list = wl_escan_get_buf(cfg, FALSE);
++			if (scan_req_match(cfg)) {
++				/* p2p scan && allow only probe response */
++				if ((cfg->p2p->search_state != WL_P2P_DISC_ST_SCAN) &&
++					(bi->flags & WL_BSS_FLAGS_FROM_BEACON))
++					goto exit;
++				if ((p2p_ie = wl_cfgp2p_find_p2pie(((u8 *) bi) + bi->ie_offset,
++					bi->ie_length)) == NULL) {
++						WL_ERR(("Couldn't find P2PIE in probe"
++							" response/beacon\n"));
++						goto exit;
++				}
++			}
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++			if (bi_length > ESCAN_BUF_SIZE - list->buflen)
++				remove_lower_rssi = TRUE;
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++
++			WL_DBG(("%s("MACDBG") RSSI %d flags 0x%x length %d\n", bi->SSID,
++				MAC2STRDBG(bi->BSSID.octet), bi->RSSI, bi->flags, bi->length));
++			for (i = 0; i < list->count; i++) {
++				bss = bss ? (wl_bss_info_t *)((uintptr)bss + dtoh32(bss->length))
++					: list->bss_info;
++				if (!bss) {
++					WL_ERR(("bss is NULL\n"));
++					goto exit;
++				}
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++				WL_DBG(("%s("MACDBG"), i=%d bss: RSSI %d list->count %d\n",
++					bss->SSID, MAC2STRDBG(bss->BSSID.octet),
++					i, bss->RSSI, list->count));
++
++				if (remove_lower_rssi)
++					wl_cfg80211_find_removal_candidate(bss, candidate);
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++
++				if (!bcmp(&bi->BSSID, &bss->BSSID, ETHER_ADDR_LEN) &&
++					(CHSPEC_BAND(wl_chspec_driver_to_host(bi->chanspec))
++					== CHSPEC_BAND(wl_chspec_driver_to_host(bss->chanspec))) &&
++					bi->SSID_len == bss->SSID_len &&
++					!bcmp(bi->SSID, bss->SSID, bi->SSID_len)) {
++
++					/* do not allow beacon data to update
++					*the data recd from a probe response
++					*/
++					if (!(bss->flags & WL_BSS_FLAGS_FROM_BEACON) &&
++						(bi->flags & WL_BSS_FLAGS_FROM_BEACON))
++						goto exit;
++
++					WL_DBG(("%s("MACDBG"), i=%d prev: RSSI %d"
++						" flags 0x%x, new: RSSI %d flags 0x%x\n",
++						bss->SSID, MAC2STRDBG(bi->BSSID.octet), i,
++						bss->RSSI, bss->flags, bi->RSSI, bi->flags));
++
++					if ((bss->flags & WL_BSS_FLAGS_RSSI_ONCHANNEL) ==
++						(bi->flags & WL_BSS_FLAGS_RSSI_ONCHANNEL)) {
++						/* preserve max RSSI if the measurements are
++						* both on-channel or both off-channel
++						*/
++						WL_DBG(("%s("MACDBG"), same onchan"
++						", RSSI: prev %d new %d\n",
++						bss->SSID, MAC2STRDBG(bi->BSSID.octet),
++						bss->RSSI, bi->RSSI));
++						bi->RSSI = MAX(bss->RSSI, bi->RSSI);
++					} else if ((bss->flags & WL_BSS_FLAGS_RSSI_ONCHANNEL) &&
++						(bi->flags & WL_BSS_FLAGS_RSSI_ONCHANNEL) == 0) {
++						/* preserve the on-channel rssi measurement
++						* if the new measurement is off channel
++						*/
++						WL_DBG(("%s("MACDBG"), prev onchan"
++						", RSSI: prev %d new %d\n",
++						bss->SSID, MAC2STRDBG(bi->BSSID.octet),
++						bss->RSSI, bi->RSSI));
++						bi->RSSI = bss->RSSI;
++						bi->flags |= WL_BSS_FLAGS_RSSI_ONCHANNEL;
++					}
++					if (dtoh32(bss->length) != bi_length) {
++						u32 prev_len = dtoh32(bss->length);
++
++						WL_DBG(("bss info replacement"
++							" is occured(bcast:%d->probresp%d)\n",
++							bss->ie_length, bi->ie_length));
++						WL_DBG(("%s("MACDBG"), replacement!(%d -> %d)\n",
++						bss->SSID, MAC2STRDBG(bi->BSSID.octet),
++						prev_len, bi_length));
++
++						if (list->buflen - prev_len + bi_length
++							> ESCAN_BUF_SIZE) {
++							WL_ERR(("Buffer is too small: keep the"
++								" previous result of this AP\n"));
++							/* Only update RSSI */
++							bss->RSSI = bi->RSSI;
++							bss->flags |= (bi->flags
++								& WL_BSS_FLAGS_RSSI_ONCHANNEL);
++							goto exit;
++						}
++
++						if (i < list->count - 1) {
++							/* memory copy required by this case only */
++							memmove((u8 *)bss + bi_length,
++								(u8 *)bss + prev_len,
++								list->buflen - cur_len - prev_len);
++						}
++						list->buflen -= prev_len;
++						list->buflen += bi_length;
++					}
++					list->version = dtoh32(bi->version);
++					memcpy((u8 *)bss, (u8 *)bi, bi_length);
++					goto exit;
++				}
++				cur_len += dtoh32(bss->length);
++			}
++			if (bi_length > ESCAN_BUF_SIZE - list->buflen) {
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++				wl_cfg80211_remove_lowRSSI_info(list, candidate, bi);
++				if (bi_length > ESCAN_BUF_SIZE - list->buflen) {
++					WL_DBG(("RSSI(" MACDBG ") is too low(%d) to add Buffer\n",
++						MAC2STRDBG(bi->BSSID.octet), bi->RSSI));
++					goto exit;
++				}
++#else
++				WL_ERR(("Buffer is too small: ignoring\n"));
++				goto exit;
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++			}
++
++			memcpy(&(((char *)list)[list->buflen]), bi, bi_length);
++			list->version = dtoh32(bi->version);
++			list->buflen += bi_length;
++			list->count++;
++
++			/*
++			 * !Broadcast && number of ssid = 1 && number of channels =1
++			 * means specific scan to association
++			 */
++			if (wl_cfgp2p_is_p2p_specific_scan(cfg->scan_request)) {
++				WL_ERR(("P2P assoc scan fast aborted.\n"));
++				wl_notify_escan_complete(cfg, cfg->escan_info.ndev, false, true);
++				goto exit;
++			}
++		}
++	}
++	else if (status == WLC_E_STATUS_SUCCESS) {
++		cfg->escan_info.escan_state = WL_ESCAN_STATE_IDLE;
++		wl_escan_print_sync_id(status, cfg->escan_info.cur_sync_id,
++			escan_result->sync_id);
++
++		if (wl_get_drv_status_all(cfg, FINDING_COMMON_CHANNEL)) {
++			WL_INFORM(("ACTION FRAME SCAN DONE\n"));
++			wl_clr_p2p_status(cfg, SCANNING);
++			wl_clr_drv_status(cfg, SCANNING, cfg->afx_hdl->dev);
++			if (cfg->afx_hdl->peer_chan == WL_INVALID)
++				complete(&cfg->act_frm_scan);
++		} else if ((likely(cfg->scan_request)) || (cfg->sched_scan_running)) {
++			WL_INFORM(("ESCAN COMPLETED\n"));
++			DBG_EVENT_LOG((dhd_pub_t *)cfg->pub, WIFI_EVENT_DRIVER_SCAN_COMPLETE);
++			cfg->bss_list = wl_escan_get_buf(cfg, FALSE);
++			if (!scan_req_match(cfg)) {
++				WL_DBG(("SCAN COMPLETED: scanned AP count=%d\n",
++					cfg->bss_list->count));
++			}
++			wl_inform_bss(cfg);
++			wl_notify_escan_complete(cfg, ndev, false, false);
++		}
++		wl_escan_increment_sync_id(cfg, SCAN_BUF_NEXT);
++#ifdef CUSTOMER_HW4_DEBUG
++		if (wl_scan_timeout_dbg_enabled)
++			wl_scan_timeout_dbg_clear();
++#endif /* CUSTOMER_HW4_DEBUG */
++	} else if ((status == WLC_E_STATUS_ABORT) || (status == WLC_E_STATUS_NEWSCAN) ||
++		(status == WLC_E_STATUS_11HQUIET) || (status == WLC_E_STATUS_CS_ABORT) ||
++		(status == WLC_E_STATUS_NEWASSOC)) {
++		/* Handle all cases of scan abort */
++		cfg->escan_info.escan_state = WL_ESCAN_STATE_IDLE;
++		wl_escan_print_sync_id(status, escan_result->sync_id,
++			cfg->escan_info.cur_sync_id);
++		WL_DBG(("ESCAN ABORT reason: %d\n", status));
++		if (wl_get_drv_status_all(cfg, FINDING_COMMON_CHANNEL)) {
++			WL_INFORM(("ACTION FRAME SCAN DONE\n"));
++			wl_clr_drv_status(cfg, SCANNING, cfg->afx_hdl->dev);
++			wl_clr_p2p_status(cfg, SCANNING);
++			if (cfg->afx_hdl->peer_chan == WL_INVALID)
++				complete(&cfg->act_frm_scan);
++		} else if ((likely(cfg->scan_request)) || (cfg->sched_scan_running)) {
++			WL_INFORM(("ESCAN ABORTED\n"));
++			cfg->bss_list = wl_escan_get_buf(cfg, TRUE);
++			if (!scan_req_match(cfg)) {
++				WL_TRACE_HW4(("SCAN ABORTED: scanned AP count=%d\n",
++					cfg->bss_list->count));
++			}
++			wl_inform_bss(cfg);
++			wl_notify_escan_complete(cfg, ndev, true, false);
++		} else {
++			/* If there is no pending host initiated scan, do nothing */
++			WL_DBG(("ESCAN ABORT: No pending scans. Ignoring event.\n"));
++		}
++		wl_escan_increment_sync_id(cfg, SCAN_BUF_CNT);
++	} else if (status == WLC_E_STATUS_TIMEOUT) {
++		WL_ERR(("WLC_E_STATUS_TIMEOUT : scan_request[%p]\n", cfg->scan_request));
++		WL_ERR(("reason[0x%x]\n", e->reason));
++		if (e->reason == 0xFFFFFFFF) {
++			wl_notify_escan_complete(cfg, cfg->escan_info.ndev, true, true);
++		}
++	} else {
++		WL_ERR(("unexpected Escan Event %d : abort\n", status));
++		cfg->escan_info.escan_state = WL_ESCAN_STATE_IDLE;
++		wl_escan_print_sync_id(status, escan_result->sync_id,
++			cfg->escan_info.cur_sync_id);
++		if (wl_get_drv_status_all(cfg, FINDING_COMMON_CHANNEL)) {
++			WL_INFORM(("ACTION FRAME SCAN DONE\n"));
++			wl_clr_p2p_status(cfg, SCANNING);
++			wl_clr_drv_status(cfg, SCANNING, cfg->afx_hdl->dev);
++			if (cfg->afx_hdl->peer_chan == WL_INVALID)
++				complete(&cfg->act_frm_scan);
++		} else if ((likely(cfg->scan_request)) || (cfg->sched_scan_running)) {
++			cfg->bss_list = wl_escan_get_buf(cfg, TRUE);
++			if (!scan_req_match(cfg)) {
++				WL_TRACE_HW4(("SCAN ABORTED(UNEXPECTED): "
++					"scanned AP count=%d\n",
++					cfg->bss_list->count));
++			}
++			wl_inform_bss(cfg);
++			wl_notify_escan_complete(cfg, ndev, true, false);
++		}
++		wl_escan_increment_sync_id(cfg, 2);
++	}
++#else /* WL_DRV_AVOID_SCANCACHE */
++	err = wl_escan_without_scan_cache(cfg, escan_result, ndev, e, status);
++#endif /* WL_DRV_AVOID_SCANCACHE */
++exit:
++	mutex_unlock(&cfg->usr_sync);
++	return err;
++}
++
++static void wl_cfg80211_concurrent_roam(struct bcm_cfg80211 *cfg, int enable)
++{
++	u32 connected_cnt  = wl_get_drv_status_all(cfg, CONNECTED);
++	bool p2p_connected  = wl_cfgp2p_vif_created(cfg);
++	struct net_info *iter, *next;
++
++	if (!(cfg->roam_flags & WL_ROAM_OFF_ON_CONCURRENT))
++		return;
++
++	WL_DBG(("roam off:%d p2p_connected:%d connected_cnt:%d \n",
++		enable, p2p_connected, connected_cnt));
++	/* Disable FW roam when we have a concurrent P2P connection */
++	if (enable && p2p_connected && connected_cnt > 1) {
++
++		/* Mark it as to be reverted */
++		cfg->roam_flags |= WL_ROAM_REVERT_STATUS;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++		for_each_ndev(cfg, iter, next) {
++			if (iter->ndev && iter->wdev &&
++					iter->wdev->iftype == NL80211_IFTYPE_STATION) {
++				if (wldev_iovar_setint(iter->ndev, "roam_off", TRUE)
++						== BCME_OK) {
++					iter->roam_off = TRUE;
++				}
++				else {
++					WL_ERR(("error to enable roam_off\n"));
++				}
++			}
++		}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	}
++	else if (!enable && (cfg->roam_flags & WL_ROAM_REVERT_STATUS)) {
++		cfg->roam_flags &= ~WL_ROAM_REVERT_STATUS;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++		for_each_ndev(cfg, iter, next) {
++			if (iter->ndev && iter->wdev &&
++					iter->wdev->iftype == NL80211_IFTYPE_STATION) {
++				if (iter->roam_off != WL_INVALID) {
++					if (wldev_iovar_setint(iter->ndev, "roam_off", FALSE)
++							== BCME_OK) {
++						iter->roam_off = FALSE;
++					}
++					else {
++						WL_ERR(("error to disable roam_off\n"));
++					}
++				}
++			}
++		}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	}
++
++	return;
++}
++
++static void wl_cfg80211_determine_vsdb_mode(struct bcm_cfg80211 *cfg)
++{
++	struct net_info *iter, *next;
++	u32 ctl_chan = 0;
++	u32 chanspec = 0;
++	u32 pre_ctl_chan = 0;
++	u32 connected_cnt  = wl_get_drv_status_all(cfg, CONNECTED);
++	cfg->vsdb_mode = false;
++
++	if (connected_cnt <= 1)  {
++		return;
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++	for_each_ndev(cfg, iter, next) {
++		/* p2p discovery iface ndev could be null */
++		if (iter->ndev) {
++			chanspec = 0;
++			ctl_chan = 0;
++			if (wl_get_drv_status(cfg, CONNECTED, iter->ndev)) {
++				if (wldev_iovar_getint(iter->ndev, "chanspec",
++					(s32 *)&chanspec) == BCME_OK) {
++					chanspec = wl_chspec_driver_to_host(chanspec);
++					ctl_chan = wf_chspec_ctlchan(chanspec);
++					wl_update_prof(cfg, iter->ndev, NULL,
++						&ctl_chan, WL_PROF_CHAN);
++				}
++				if (!cfg->vsdb_mode) {
++					if (!pre_ctl_chan && ctl_chan)
++						pre_ctl_chan = ctl_chan;
++					else if (pre_ctl_chan && (pre_ctl_chan != ctl_chan)) {
++						cfg->vsdb_mode = true;
++					}
++				}
++			}
++		}
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	WL_MSG("wlan", "%s concurrency is enabled\n", cfg->vsdb_mode ? "Multi Channel" : "Same Channel");
++	return;
++}
++
++#if defined(DISABLE_FRAMEBURST_VSDB) && defined(USE_WFA_CERT_CONF)
++extern int g_frameburst;
++#endif /* DISABLE_FRAMEBURST_VSDB && USE_WFA_CERT_CONF */
++
++static s32 wl_notifier_change_state(struct bcm_cfg80211 *cfg, struct net_info *_net_info,
++	enum wl_status state, bool set)
++{
++	s32 pm = PM_FAST;
++	s32 err = BCME_OK;
++	u32 mode;
++	u32 chan = 0;
++	struct net_device *primary_dev = bcmcfg_to_prmry_ndev(cfg);
++	dhd_pub_t *dhd = cfg->pub;
++#ifdef RTT_SUPPORT
++	rtt_status_info_t *rtt_status;
++#endif /* RTT_SUPPORT */
++	if (dhd->busstate == DHD_BUS_DOWN) {
++		WL_ERR(("%s : busstate is DHD_BUS_DOWN!\n", __FUNCTION__));
++		return 0;
++	}
++	WL_DBG(("Enter state %d set %d _net_info->pm_restore %d iface %s\n",
++		state, set, _net_info->pm_restore, _net_info->ndev->name));
++
++	if (state != WL_STATUS_CONNECTED)
++		return 0;
++	mode = wl_get_mode_by_netdev(cfg, _net_info->ndev);
++	if (set) {
++		wl_cfg80211_concurrent_roam(cfg, 1);
++		wl_cfg80211_determine_vsdb_mode(cfg);
++		if (mode == WL_MODE_AP) {
++			if (wl_add_remove_eventmsg(primary_dev, WLC_E_P2P_PROBREQ_MSG, false))
++				WL_ERR((" failed to unset WLC_E_P2P_PROPREQ_MSG\n"));
++		}
++		pm = PM_OFF;
++		if ((err = wldev_ioctl_set(_net_info->ndev, WLC_SET_PM, &pm,
++				sizeof(pm))) != 0) {
++			if (err == -ENODEV)
++				WL_DBG(("%s:netdev not ready\n",
++					_net_info->ndev->name));
++			else
++				WL_ERR(("%s:error (%d)\n",
++					_net_info->ndev->name, err));
++
++			wl_cfg80211_update_power_mode(_net_info->ndev);
++		}
++		wl_add_remove_pm_enable_work(cfg, WL_PM_WORKQ_SHORT);
++
++	} else { /* clear */
++		chan = 0;
++		/* clear chan information when the net device is disconnected */
++		wl_update_prof(cfg, _net_info->ndev, NULL, &chan, WL_PROF_CHAN);
++		wl_cfg80211_determine_vsdb_mode(cfg);
++		if (primary_dev == _net_info->ndev) {
++			pm = PM_FAST;
++#ifdef RTT_SUPPORT
++			rtt_status = GET_RTTSTATE(dhd);
++			if (rtt_status->status != RTT_ENABLED) {
++#endif /* RTT_SUPPORT */
++				if (dhd_conf_get_pm(dhd) >= 0)
++					pm = dhd_conf_get_pm(dhd);
++				if ((err = wldev_ioctl_set(_net_info->ndev, WLC_SET_PM, &pm,
++						sizeof(pm))) != 0) {
++					if (err == -ENODEV)
++						WL_DBG(("%s:netdev not ready\n",
++							_net_info->ndev->name));
++					else
++						WL_ERR(("%s:error (%d)\n",
++							_net_info->ndev->name, err));
++
++					wl_cfg80211_update_power_mode(_net_info->ndev);
++				}
++#ifdef RTT_SUPPORT
++			}
++#endif /* RTT_SUPPORT */
++		}
++		wl_cfg80211_concurrent_roam(cfg, 0);
++
++	}
++	return err;
++}
++
++static s32 wl_init_scan(struct bcm_cfg80211 *cfg)
++{
++	int err = 0;
++
++	cfg->evt_handler[WLC_E_ESCAN_RESULT] = wl_escan_handler;
++	cfg->escan_info.escan_state = WL_ESCAN_STATE_IDLE;
++	wl_escan_init_sync_id(cfg);
++
++	/* Init scan_timeout timer */
++	init_timer_compat(&cfg->scan_timeout, wl_scan_timeout, cfg);
++
++	return err;
++}
++
++#ifdef DHD_LOSSLESS_ROAMING
++static s32 wl_init_roam_timeout(struct bcm_cfg80211 *cfg)
++{
++	int err = 0;
++
++	/* Init roam timer */
++	init_timer_compat(&cfg->roam_timeout, wl_roam_timeout, cfg);
++
++	return err;
++}
++#endif /* DHD_LOSSLESS_ROAMING */
++
++static s32 wl_init_priv(struct bcm_cfg80211 *cfg)
++{
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	s32 err = 0;
++
++	cfg->scan_request = NULL;
++	cfg->pwr_save = !!(wiphy->flags & WIPHY_FLAG_PS_ON_BY_DEFAULT);
++#ifdef DISABLE_BUILTIN_ROAM
++	cfg->roam_on = false;
++#else
++	cfg->roam_on = true;
++#endif /* DISABLE_BUILTIN_ROAM */
++	cfg->active_scan = true;
++	cfg->rf_blocked = false;
++	cfg->vsdb_mode = false;
++#if defined(BCMSDIO) || defined(BCMDBUS)
++	cfg->wlfc_on = false;
++#endif /* BCMSDIO || BCMDBUS */
++	cfg->roam_flags |= WL_ROAM_OFF_ON_CONCURRENT;
++	cfg->disable_roam_event = false;
++	/* register interested state */
++	set_bit(WL_STATUS_CONNECTED, &cfg->interrested_state);
++	spin_lock_init(&cfg->cfgdrv_lock);
++	mutex_init(&cfg->ioctl_buf_sync);
++	init_waitqueue_head(&cfg->netif_change_event);
++	init_waitqueue_head(&cfg->wps_done_event);
++	init_completion(&cfg->send_af_done);
++	init_completion(&cfg->iface_disable);
++	mutex_init(&cfg->usr_sync);
++	mutex_init(&cfg->event_sync);
++	mutex_init(&cfg->scan_complete);
++	mutex_init(&cfg->if_sync);
++	mutex_init(&cfg->pm_sync);
++	mutex_init(&cfg->in4way_sync);
++#ifdef WLTDLS
++	mutex_init(&cfg->tdls_sync);
++#endif /* WLTDLS */
++	wl_init_eq(cfg);
++	err = wl_init_priv_mem(cfg);
++	if (err)
++		return err;
++	if (wl_create_event_handler(cfg))
++		return -ENOMEM;
++	wl_init_event_handler(cfg);
++	err = wl_init_scan(cfg);
++	if (err)
++		return err;
++#ifdef DHD_LOSSLESS_ROAMING
++	err = wl_init_roam_timeout(cfg);
++	if (err) {
++		return err;
++	}
++#endif /* DHD_LOSSLESS_ROAMING */
++	wl_init_conf(cfg->conf);
++	wl_init_prof(cfg, ndev);
++	wl_link_down(cfg);
++	DNGL_FUNC(dhd_cfg80211_init, (cfg));
++#ifdef NAN_DP
++	cfg->nan_dp_state = NAN_DP_STATE_DISABLED;
++	init_waitqueue_head(&cfg->ndp_if_change_event);
++#endif /* NAN_DP */
++	return err;
++}
++
++static void wl_deinit_priv(struct bcm_cfg80211 *cfg)
++{
++	DNGL_FUNC(dhd_cfg80211_deinit, (cfg));
++	wl_destroy_event_handler(cfg);
++	wl_flush_eq(cfg);
++	wl_link_down(cfg);
++	_del_timer_sync(&cfg->scan_timeout);
++#ifdef DHD_LOSSLESS_ROAMING
++	_del_timer_sync(&cfg->roam_timeout);
++#endif
++	wl_deinit_priv_mem(cfg);
++	if (wl_cfg80211_netdev_notifier_registered) {
++		wl_cfg80211_netdev_notifier_registered = FALSE;
++		unregister_netdevice_notifier(&wl_cfg80211_netdev_notifier);
++	}
++}
++
++#if defined(WL_ENABLE_P2P_IF)
++static s32 wl_cfg80211_attach_p2p(struct bcm_cfg80211 *cfg)
++{
++	WL_TRACE(("Enter \n"));
++
++	if (wl_cfgp2p_register_ndev(cfg) < 0) {
++		WL_ERR(("P2P attach failed. \n"));
++		return -ENODEV;
++	}
++
++	return 0;
++}
++
++static s32  wl_cfg80211_detach_p2p(struct bcm_cfg80211 *cfg)
++{
++	struct wireless_dev *wdev;
++
++	WL_DBG(("Enter \n"));
++	if (!cfg) {
++		WL_ERR(("Invalid Ptr\n"));
++		return -EINVAL;
++	}
++	else {
++		wdev = cfg->p2p_wdev;
++		if (!wdev) {
++			WL_ERR(("Invalid Ptr\n"));
++			return -EINVAL;
++		}
++	}
++
++	wl_cfgp2p_unregister_ndev(cfg);
++
++	cfg->p2p_wdev = NULL;
++	cfg->p2p_net = NULL;
++	WL_DBG(("Freeing 0x%p \n", wdev));
++	kfree(wdev);
++
++	return 0;
++}
++#endif 
++
++static s32 wl_cfg80211_attach_post(struct net_device *ndev)
++{
++	struct bcm_cfg80211 * cfg;
++	s32 err = 0;
++	s32 ret = 0;
++	WL_TRACE(("In\n"));
++	if (unlikely(!ndev)) {
++		WL_ERR(("ndev is invaild\n"));
++		return -ENODEV;
++	}
++	cfg = wl_get_cfg(ndev);
++	if (unlikely(!cfg)) {
++		WL_ERR(("cfg is invaild\n"));
++		return -EINVAL;
++	}
++	if (!wl_get_drv_status(cfg, READY, ndev)) {
++		if (cfg->wdev) {
++			ret = wl_cfgp2p_supported(cfg, ndev);
++			if (ret > 0) {
++#if !defined(WL_ENABLE_P2P_IF)
++				cfg->wdev->wiphy->interface_modes |=
++					(BIT(NL80211_IFTYPE_P2P_CLIENT)|
++					BIT(NL80211_IFTYPE_P2P_GO));
++#endif /* !WL_ENABLE_P2P_IF */
++				if ((err = wl_cfgp2p_init_priv(cfg)) != 0)
++					goto fail;
++
++#if defined(WL_ENABLE_P2P_IF)
++				if (cfg->p2p_net) {
++					/* Update MAC addr for p2p0 interface here. */
++					memcpy(cfg->p2p_net->dev_addr, ndev->dev_addr, ETH_ALEN);
++					cfg->p2p_net->dev_addr[0] |= 0x02;
++					WL_MSG(cfg->p2p_net->name, "p2p_dev_addr="MACDBG "\n",
++						MAC2STRDBG(cfg->p2p_net->dev_addr));
++				} else {
++					WL_ERR(("p2p_net not yet populated."
++					" Couldn't update the MAC Address for p2p0 \n"));
++					return -ENODEV;
++				}
++#endif /* WL_ENABLE_P2P_IF */
++				cfg->p2p_supported = true;
++			} else if (ret == 0) {
++				if ((err = wl_cfgp2p_init_priv(cfg)) != 0)
++					goto fail;
++			} else {
++				/* SDIO bus timeout */
++				err = -ENODEV;
++				goto fail;
++			}
++		}
++	}
++	wl_set_drv_status(cfg, READY, ndev);
++fail:
++	return err;
++}
++
++struct bcm_cfg80211 *wl_get_cfg(struct net_device *ndev)
++{
++	struct wireless_dev *wdev = ndev->ieee80211_ptr;
++
++	if (!wdev || !wdev->wiphy)
++		return NULL;
++
++	return wiphy_priv(wdev->wiphy);
++}
++
++s32 wl_cfg80211_attach(struct net_device *ndev, void *context)
++{
++	struct wireless_dev *wdev;
++	struct bcm_cfg80211 *cfg;
++	s32 err = 0;
++	struct device *dev;
++
++	WL_TRACE(("In\n"));
++	if (!ndev) {
++		WL_ERR(("ndev is invaild\n"));
++		return -ENODEV;
++	}
++	WL_DBG(("func %p\n", wl_cfg80211_get_parent_dev()));
++	dev = wl_cfg80211_get_parent_dev();
++
++	wdev = kzalloc(sizeof(*wdev), GFP_KERNEL);
++	if (unlikely(!wdev)) {
++		WL_ERR(("Could not allocate wireless device\n"));
++		return -ENOMEM;
++	}
++	err = wl_setup_wiphy(wdev, dev, context);
++	if (unlikely(err)) {
++		kfree(wdev);
++		return -ENOMEM;
++	}
++#ifdef WLMESH_CFG80211
++	wdev->iftype = wl_mode_to_nl80211_iftype(WL_MODE_MESH);
++#else
++	wdev->iftype = wl_mode_to_nl80211_iftype(WL_MODE_BSS);
++#endif
++	cfg = wiphy_priv(wdev->wiphy);
++	cfg->wdev = wdev;
++	cfg->pub = context;
++	INIT_LIST_HEAD(&cfg->net_list);
++#ifdef WBTEXT
++	INIT_LIST_HEAD(&cfg->wbtext_bssid_list);
++#endif /* WBTEXT */
++	INIT_LIST_HEAD(&cfg->vndr_oui_list);
++	spin_lock_init(&cfg->net_list_sync);
++	ndev->ieee80211_ptr = wdev;
++	SET_NETDEV_DEV(ndev, wiphy_dev(wdev->wiphy));
++	wdev->netdev = ndev;
++	cfg->state_notifier = wl_notifier_change_state;
++	err = wl_init_priv(cfg);
++	if (err) {
++		WL_ERR(("Failed to init iwm_priv (%d)\n", err));
++		goto cfg80211_attach_out;
++	}
++	err = wl_alloc_netinfo(cfg, ndev, wdev, wdev->iftype, PM_ENABLE, 0);
++	if (err) {
++		WL_ERR(("Failed to alloc net_info (%d)\n", err));
++		goto cfg80211_attach_out;
++	}
++
++	err = wl_setup_rfkill(cfg, TRUE);
++	if (err) {
++		WL_ERR(("Failed to setup rfkill %d\n", err));
++		goto cfg80211_attach_out;
++	}
++#ifdef DEBUGFS_CFG80211
++	err = wl_setup_debugfs(cfg);
++	if (err) {
++		WL_ERR(("Failed to setup debugfs %d\n", err));
++		goto cfg80211_attach_out;
++	}
++#endif
++	if (!wl_cfg80211_netdev_notifier_registered) {
++		wl_cfg80211_netdev_notifier_registered = TRUE;
++		err = register_netdevice_notifier(&wl_cfg80211_netdev_notifier);
++		if (err) {
++			wl_cfg80211_netdev_notifier_registered = FALSE;
++			WL_ERR(("Failed to register notifierl %d\n", err));
++			goto cfg80211_attach_out;
++		}
++	}
++#if defined(COEX_DHCP)
++	cfg->btcoex_info = wl_cfg80211_btcoex_init(cfg->wdev->netdev);
++	if (!cfg->btcoex_info)
++		goto cfg80211_attach_out;
++#endif 
++#if defined(SUPPORT_RANDOM_MAC_SCAN)
++	cfg->random_mac_enabled = FALSE;
++#endif /* SUPPORT_RANDOM_MAC_SCAN */
++
++#ifdef CONFIG_CFG80211_INTERNAL_REGDB
++	wdev->wiphy->reg_notifier = wl_cfg80211_reg_notifier;
++#endif /* CONFIG_CFG80211_INTERNAL_REGDB */
++
++#if defined(WL_ENABLE_P2P_IF)
++	err = wl_cfg80211_attach_p2p(cfg);
++	if (err)
++		goto cfg80211_attach_out;
++#endif 
++
++	INIT_DELAYED_WORK(&cfg->pm_enable_work, wl_cfg80211_work_handler);
++
++#if defined(STAT_REPORT)
++	err = wl_attach_stat_report(cfg);
++	if (err) {
++		goto cfg80211_attach_out;
++	}
++#endif /* STAT_REPORT */
++	return err;
++
++cfg80211_attach_out:
++	wl_cfg80211_detach(cfg);
++	return err;
++}
++
++void wl_cfg80211_detach(struct bcm_cfg80211 *cfg)
++{
++
++	WL_TRACE(("In\n"));
++	if (!cfg)
++		return;
++
++	wl_add_remove_pm_enable_work(cfg, WL_PM_WORKQ_DEL);
++
++#if defined(COEX_DHCP)
++	wl_cfg80211_btcoex_deinit();
++	cfg->btcoex_info = NULL;
++#endif 
++
++	wl_setup_rfkill(cfg, FALSE);
++#ifdef DEBUGFS_CFG80211
++	wl_free_debugfs(cfg);
++#endif
++	if (cfg->p2p_supported) {
++		if (timer_pending(&cfg->p2p->listen_timer))
++			_del_timer_sync(&cfg->p2p->listen_timer);
++		wl_cfgp2p_deinit_priv(cfg);
++	}
++
++	if (timer_pending(&cfg->scan_timeout))
++		_del_timer_sync(&cfg->scan_timeout);
++#ifdef DHD_LOSSLESS_ROAMING
++	if (timer_pending(&cfg->roam_timeout)) {
++		_del_timer_sync(&cfg->roam_timeout);
++	}
++#endif /* DHD_LOSSLESS_ROAMING */
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	if (cfg->p2p_wdev)
++		wl_cfgp2p_del_p2p_disc_if(cfg->p2p_wdev, cfg);
++#endif /* WL_CFG80211_P2P_DEV_IF  */
++#if defined(WL_ENABLE_P2P_IF)
++	wl_cfg80211_detach_p2p(cfg);
++#endif 
++#if defined(STAT_REPORT)
++	wl_detach_stat_report(cfg);
++#endif /* STAT_REPORT */
++
++	wl_cfg80211_ibss_vsie_free(cfg);
++	wl_cfg80211_clear_mgmt_vndr_ies(cfg);
++	wl_deinit_priv(cfg);
++	wl_cfg80211_clear_parent_dev();
++#if defined(RSSIAVG)
++	wl_free_rssi_cache(&cfg->g_rssi_cache_ctrl);
++	wl_free_rssi_cache(&cfg->g_connected_rssi_cache_ctrl);
++#endif
++#if defined(BSSCACHE)
++	wl_release_bss_cache_ctrl(&cfg->g_bss_cache_ctrl);
++#endif
++	wl_free_wdev(cfg);
++	/* PLEASE do NOT call any function after wl_free_wdev, the driver's private
++	 * structure "cfg", which is the private part of wiphy, has been freed in
++	 * wl_free_wdev !!!!!!!!!!!
++	 */
++}
++
++static void wl_event_handler(struct work_struct *work_data)
++{
++	struct bcm_cfg80211 *cfg = NULL;
++	struct wl_event_q *e;
++	struct wireless_dev *wdev = NULL;
++
++	BCM_SET_CONTAINER_OF(cfg, work_data, struct bcm_cfg80211, event_work);
++	DHD_EVENT_WAKE_LOCK(cfg->pub);
++	while ((e = wl_deq_event(cfg))) {
++		WL_DBG(("event type (%d), ifidx: %d bssidx: %d \n",
++			e->etype, e->emsg.ifidx, e->emsg.bsscfgidx));
++
++		if (e->emsg.ifidx > WL_MAX_IFS) {
++			WL_ERR((" Event ifidx not in range. val:%d \n", e->emsg.ifidx));
++			goto fail;
++		}
++
++		/* Make sure iface operations, don't creat race conditions */
++		mutex_lock(&cfg->if_sync);
++		if (!(wdev = wl_get_wdev_by_bssidx(cfg, e->emsg.bsscfgidx))) {
++			/* For WLC_E_IF would be handled by wl_host_event */
++			if (e->etype != WLC_E_IF)
++				WL_ERR(("No wdev corresponding to bssidx: 0x%x found!"
++					" Ignoring event.\n", e->emsg.bsscfgidx));
++		} else if (e->etype < WLC_E_LAST && cfg->evt_handler[e->etype]) {
++			dhd_pub_t *dhd = (struct dhd_pub *)(cfg->pub);
++			if (dhd->busstate == DHD_BUS_DOWN) {
++				WL_ERR((": BUS is DOWN.\n"));
++			} else
++				cfg->evt_handler[e->etype](cfg, wdev_to_cfgdev(wdev),
++					&e->emsg, e->edata);
++		} else {
++			WL_DBG(("Unknown Event (%d): ignoring\n", e->etype));
++		}
++		mutex_unlock(&cfg->if_sync);
++fail:
++		wl_put_event(e);
++	}
++	DHD_EVENT_WAKE_UNLOCK(cfg->pub);
++}
++
++void
++wl_cfg80211_event(struct net_device *ndev, const wl_event_msg_t * e, void *data)
++{
++	u32 event_type = ntoh32(e->event_type);
++	struct bcm_cfg80211 *cfg = wl_get_cfg(ndev);
++	struct net_info *netinfo;
++
++	WL_DBG(("event_type (%d): %s\n", event_type, bcmevent_get_name(event_type)));
++
++	if ((cfg == NULL) || (cfg->p2p_supported && cfg->p2p == NULL)) {
++		WL_ERR(("Stale event ignored\n"));
++		return;
++	}
++
++	if (cfg->event_workq == NULL) {
++		WL_ERR(("Event handler is not created\n"));
++		return;
++	}
++
++	if (wl_get_p2p_status(cfg, IF_CHANGING) || wl_get_p2p_status(cfg, IF_ADDING)) {
++		WL_ERR(("during IF change, ignore event %d\n", event_type));
++		return;
++	}
++
++	netinfo = wl_get_netinfo_by_bssidx(cfg, e->bsscfgidx);
++	if (!netinfo) {
++		/* Since the netinfo entry is not there, the netdev entry is not
++		 * created via cfg80211 interface. so the event is not of interest
++		 * to the cfg80211 layer.
++		 */
++		WL_ERR(("ignore event %d, not interested\n", event_type));
++		return;
++	}
++
++	if (event_type == WLC_E_PFN_NET_FOUND) {
++		WL_DBG((" PNOEVENT: PNO_NET_FOUND\n"));
++	}
++	else if (event_type == WLC_E_PFN_NET_LOST) {
++		WL_DBG((" PNOEVENT: PNO_NET_LOST\n"));
++	}
++
++	if (likely(!wl_enq_event(cfg, ndev, event_type, e, data))) {
++		queue_work(cfg->event_workq, &cfg->event_work);
++	}
++}
++
++static void wl_init_eq(struct bcm_cfg80211 *cfg)
++{
++	wl_init_eq_lock(cfg);
++	INIT_LIST_HEAD(&cfg->eq_list);
++}
++
++static void wl_flush_eq(struct bcm_cfg80211 *cfg)
++{
++	struct wl_event_q *e;
++	unsigned long flags;
++
++	flags = wl_lock_eq(cfg);
++	while (!list_empty_careful(&cfg->eq_list)) {
++		BCM_SET_LIST_FIRST_ENTRY(e, &cfg->eq_list, struct wl_event_q, eq_list);
++		list_del(&e->eq_list);
++		kfree(e);
++	}
++	wl_unlock_eq(cfg, flags);
++}
++
++/*
++* retrieve first queued event from head
++*/
++
++static struct wl_event_q *wl_deq_event(struct bcm_cfg80211 *cfg)
++{
++	struct wl_event_q *e = NULL;
++	unsigned long flags;
++
++	flags = wl_lock_eq(cfg);
++	if (likely(!list_empty(&cfg->eq_list))) {
++		BCM_SET_LIST_FIRST_ENTRY(e, &cfg->eq_list, struct wl_event_q, eq_list);
++		list_del(&e->eq_list);
++	}
++	wl_unlock_eq(cfg, flags);
++
++	return e;
++}
++
++/*
++ * push event to tail of the queue
++ */
++
++static s32
++wl_enq_event(struct bcm_cfg80211 *cfg, struct net_device *ndev, u32 event,
++	const wl_event_msg_t *msg, void *data)
++{
++	struct wl_event_q *e;
++	s32 err = 0;
++	uint32 evtq_size;
++	uint32 data_len;
++	unsigned long flags;
++	gfp_t aflags;
++
++	data_len = 0;
++	if (data)
++		data_len = ntoh32(msg->datalen);
++	evtq_size = sizeof(struct wl_event_q) + data_len;
++	aflags = (in_atomic()) ? GFP_ATOMIC : GFP_KERNEL;
++	e = kzalloc(evtq_size, aflags);
++	if (unlikely(!e)) {
++		WL_ERR(("event alloc failed\n"));
++		return -ENOMEM;
++	}
++	e->etype = event;
++	memcpy(&e->emsg, msg, sizeof(wl_event_msg_t));
++	if (data)
++		memcpy(e->edata, data, data_len);
++	flags = wl_lock_eq(cfg);
++	list_add_tail(&e->eq_list, &cfg->eq_list);
++	wl_unlock_eq(cfg, flags);
++
++	return err;
++}
++
++static void wl_put_event(struct wl_event_q *e)
++{
++	kfree(e);
++}
++
++static s32 wl_config_ifmode(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 iftype)
++{
++	s32 infra = 0;
++	s32 err = 0;
++	s32 mode = 0;
++	switch (iftype) {
++	case NL80211_IFTYPE_MONITOR:
++	case NL80211_IFTYPE_WDS:
++		WL_ERR(("type (%d) : currently we do not support this mode\n",
++			iftype));
++		err = -EINVAL;
++		return err;
++	case NL80211_IFTYPE_ADHOC:
++		mode = WL_MODE_IBSS;
++		break;
++	case NL80211_IFTYPE_STATION:
++	case NL80211_IFTYPE_P2P_CLIENT:
++		mode = WL_MODE_BSS;
++		infra = 1;
++		break;
++#ifdef WLMESH_CFG80211
++	case NL80211_IFTYPE_MESH_POINT:
++		mode = WL_MODE_MESH;
++		infra = WL_BSSTYPE_MESH;
++		break;
++#endif /* WLMESH_CFG80211 */
++	case NL80211_IFTYPE_AP:
++	case NL80211_IFTYPE_P2P_GO:
++		mode = WL_MODE_AP;
++		infra = 1;
++		break;
++	default:
++		err = -EINVAL;
++		WL_ERR(("invalid type (%d)\n", iftype));
++		return err;
++	}
++	infra = htod32(infra);
++	err = wldev_ioctl_set(ndev, WLC_SET_INFRA, &infra, sizeof(infra));
++	if (unlikely(err)) {
++		WL_ERR(("WLC_SET_INFRA error (%d)\n", err));
++		return err;
++	}
++
++	wl_set_mode_by_netdev(cfg, ndev, mode);
++
++	return 0;
++}
++
++void wl_cfg80211_add_to_eventbuffer(struct wl_eventmsg_buf *ev, u16 event, bool set)
++{
++	if (!ev || (event > WLC_E_LAST))
++		return;
++
++	if (ev->num < MAX_EVENT_BUF_NUM) {
++		ev->event[ev->num].type = event;
++		ev->event[ev->num].set = set;
++		ev->num++;
++	} else {
++		WL_ERR(("evenbuffer doesn't support > %u events. Update"
++			" the define MAX_EVENT_BUF_NUM \n", MAX_EVENT_BUF_NUM));
++		ASSERT(0);
++	}
++}
++
++s32 wl_cfg80211_apply_eventbuffer(
++	struct net_device *ndev,
++	struct bcm_cfg80211 *cfg,
++	wl_eventmsg_buf_t *ev)
++{
++	char eventmask[WL_EVENTING_MASK_LEN];
++	int i, ret = 0;
++	s8 iovbuf[WL_EVENTING_MASK_LEN + 12];
++
++	if (!ev || (!ev->num))
++		return -EINVAL;
++
++	mutex_lock(&cfg->event_sync);
++
++	/* Read event_msgs mask */
++	ret = wldev_iovar_getbuf(ndev, "event_msgs", NULL, 0, iovbuf, sizeof(iovbuf), NULL);
++	if (unlikely(ret)) {
++		WL_ERR(("Get event_msgs error (%d)\n", ret));
++		goto exit;
++	}
++	memcpy(eventmask, iovbuf, WL_EVENTING_MASK_LEN);
++
++	/* apply the set bits */
++	for (i = 0; i < ev->num; i++) {
++		if (ev->event[i].set)
++			setbit(eventmask, ev->event[i].type);
++		else
++			clrbit(eventmask, ev->event[i].type);
++	}
++
++	/* Write updated Event mask */
++	ret = wldev_iovar_setbuf(ndev, "event_msgs", eventmask, sizeof(eventmask), iovbuf,
++			sizeof(iovbuf), NULL);
++	if (unlikely(ret)) {
++		WL_ERR(("Set event_msgs error (%d)\n", ret));
++	}
++
++exit:
++	mutex_unlock(&cfg->event_sync);
++	return ret;
++}
++
++s32 wl_add_remove_eventmsg(struct net_device *ndev, u16 event, bool add)
++{
++	s8 iovbuf[WL_EVENTING_MASK_LEN + 12];
++	s8 eventmask[WL_EVENTING_MASK_LEN];
++	s32 err = 0;
++	struct bcm_cfg80211 *cfg;
++
++	if (!ndev)
++		return -ENODEV;
++
++	cfg = wl_get_cfg(ndev);
++	if (!cfg)
++		return -ENODEV;
++
++	mutex_lock(&cfg->event_sync);
++
++	/* Setup event_msgs */
++	err = wldev_iovar_getbuf(ndev, "event_msgs", NULL, 0, iovbuf, sizeof(iovbuf), NULL);
++	if (unlikely(err)) {
++		WL_ERR(("Get event_msgs error (%d)\n", err));
++		goto eventmsg_out;
++	}
++	memcpy(eventmask, iovbuf, WL_EVENTING_MASK_LEN);
++	if (add) {
++		setbit(eventmask, event);
++	} else {
++		clrbit(eventmask, event);
++	}
++	err = wldev_iovar_setbuf(ndev, "event_msgs", eventmask, WL_EVENTING_MASK_LEN, iovbuf,
++			sizeof(iovbuf), NULL);
++	if (unlikely(err)) {
++		WL_ERR(("Set event_msgs error (%d)\n", err));
++		goto eventmsg_out;
++	}
++
++eventmsg_out:
++	mutex_unlock(&cfg->event_sync);
++	return err;
++}
++
++static int wl_construct_reginfo(struct bcm_cfg80211 *cfg, s32 bw_cap)
++{
++	struct net_device *dev = bcmcfg_to_prmry_ndev(cfg);
++	struct ieee80211_channel *band_chan_arr = NULL;
++	wl_uint32_list_t *list;
++	u32 i, j, index, n_2g, n_5g, band, channel, array_size;
++	u32 *n_cnt = NULL;
++	chanspec_t c = 0;
++	s32 err = BCME_OK;
++	bool update;
++	bool ht40_allowed;
++	u8 *pbuf = NULL;
++	bool dfs_radar_disabled = FALSE;
++
++#define LOCAL_BUF_LEN 1024
++	pbuf = kzalloc(LOCAL_BUF_LEN, GFP_KERNEL);
++
++	if (pbuf == NULL) {
++		WL_ERR(("failed to allocate local buf\n"));
++		return -ENOMEM;
++	}
++
++	err = wldev_iovar_getbuf_bsscfg(dev, "chanspecs", NULL,
++		0, pbuf, LOCAL_BUF_LEN, 0, &cfg->ioctl_buf_sync);
++	if (err != 0) {
++		WL_ERR(("get chanspecs failed with %d\n", err));
++		kfree(pbuf);
++		return err;
++	}
++#undef LOCAL_BUF_LEN
++
++	list = (wl_uint32_list_t *)(void *)pbuf;
++	band = array_size = n_2g = n_5g = 0;
++	for (i = 0; i < dtoh32(list->count); i++) {
++		index = 0;
++		update = false;
++		ht40_allowed = false;
++		c = (chanspec_t)dtoh32(list->element[i]);
++		c = wl_chspec_driver_to_host(c);
++		channel = wf_chspec_ctlchan(c);
++
++		if (!CHSPEC_IS40(c) && ! CHSPEC_IS20(c)) {
++			WL_DBG(("HT80/160/80p80 center channel : %d\n", channel));
++			continue;
++		}
++		if (CHSPEC_IS2G(c) && (channel >= CH_MIN_2G_CHANNEL) &&
++			(channel <= CH_MAX_2G_CHANNEL)) {
++			band_chan_arr = __wl_2ghz_channels;
++			array_size = ARRAYSIZE(__wl_2ghz_channels);
++			n_cnt = &n_2g;
++			band = IEEE80211_BAND_2GHZ;
++			ht40_allowed = (bw_cap  == WLC_N_BW_40ALL)? true : false;
++		} else if (CHSPEC_IS5G(c) && channel >= CH_MIN_5G_CHANNEL) {
++			band_chan_arr = __wl_5ghz_a_channels;
++			array_size = ARRAYSIZE(__wl_5ghz_a_channels);
++			n_cnt = &n_5g;
++			band = IEEE80211_BAND_5GHZ;
++			ht40_allowed = (bw_cap  == WLC_N_BW_20ALL)? false : true;
++		} else {
++			WL_ERR(("Invalid channel Sepc. 0x%x.\n", c));
++			continue;
++		}
++		if (!ht40_allowed && CHSPEC_IS40(c))
++			continue;
++		for (j = 0; (j < *n_cnt && (*n_cnt < array_size)); j++) {
++			if (band_chan_arr[j].hw_value == channel) {
++				update = true;
++				break;
++			}
++		}
++		if (update)
++			index = j;
++		else
++			index = *n_cnt;
++		if (!dhd_conf_match_channel(cfg->pub, channel))
++			continue;
++		if (index <  array_size) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39)
++			band_chan_arr[index].center_freq =
++				ieee80211_channel_to_frequency(channel);
++#else
++			band_chan_arr[index].center_freq =
++				ieee80211_channel_to_frequency(channel, band);
++#endif
++			band_chan_arr[index].hw_value = channel;
++			band_chan_arr[index].beacon_found = false;
++
++			if (CHSPEC_IS40(c) && ht40_allowed) {
++				/* assuming the order is HT20, HT40 Upper,
++				 *  HT40 lower from chanspecs
++				 */
++				u32 ht40_flag = band_chan_arr[index].flags & IEEE80211_CHAN_NO_HT40;
++				if (CHSPEC_SB_UPPER(c)) {
++					if (ht40_flag == IEEE80211_CHAN_NO_HT40)
++						band_chan_arr[index].flags &=
++							~IEEE80211_CHAN_NO_HT40;
++					band_chan_arr[index].flags |= IEEE80211_CHAN_NO_HT40PLUS;
++				} else {
++					/* It should be one of
++					 * IEEE80211_CHAN_NO_HT40 or IEEE80211_CHAN_NO_HT40PLUS
++					 */
++					band_chan_arr[index].flags &= ~IEEE80211_CHAN_NO_HT40;
++					if (ht40_flag == IEEE80211_CHAN_NO_HT40)
++						band_chan_arr[index].flags |=
++							IEEE80211_CHAN_NO_HT40MINUS;
++				}
++			} else {
++				band_chan_arr[index].flags = IEEE80211_CHAN_NO_HT40;
++				if (!dfs_radar_disabled) {
++					if (band == IEEE80211_BAND_2GHZ)
++						channel |= WL_CHANSPEC_BAND_2G;
++					else
++						channel |= WL_CHANSPEC_BAND_5G;
++					channel |= WL_CHANSPEC_BW_20;
++					channel = wl_chspec_host_to_driver(channel);
++					err = wldev_iovar_getint(dev, "per_chan_info", &channel);
++					if (!err) {
++						if (channel & WL_CHAN_RADAR) {
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
++							band_chan_arr[index].flags |=
++								(IEEE80211_CHAN_RADAR
++								| IEEE80211_CHAN_NO_IBSS);
++#else
++							band_chan_arr[index].flags |=
++								IEEE80211_CHAN_RADAR;
++#endif
++						}
++
++						if (channel & WL_CHAN_PASSIVE)
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
++							band_chan_arr[index].flags |=
++								IEEE80211_CHAN_PASSIVE_SCAN;
++#else
++							band_chan_arr[index].flags |=
++								IEEE80211_CHAN_NO_IR;
++#endif
++					} else if (err == BCME_UNSUPPORTED) {
++						dfs_radar_disabled = TRUE;
++						WL_ERR(("does not support per_chan_info\n"));
++					}
++				}
++			}
++			if (!update)
++				(*n_cnt)++;
++		}
++
++	}
++	__wl_band_2ghz.n_channels = n_2g;
++	__wl_band_5ghz_a.n_channels = n_5g;
++	kfree(pbuf);
++	return err;
++}
++
++static s32 __wl_update_wiphybands(struct bcm_cfg80211 *cfg, bool notify)
++{
++	struct wiphy *wiphy;
++	struct net_device *dev = bcmcfg_to_prmry_ndev(cfg);
++	u32 bandlist[3];
++	u32 nband = 0;
++	u32 i = 0;
++	s32 err = 0;
++	s32 index = 0;
++	s32 nmode = 0;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	u32 j = 0;
++	s32 vhtmode = 0;
++	s32 txstreams = 0;
++	s32 rxstreams = 0;
++	s32 ldpc_cap = 0;
++	s32 stbc_rx = 0;
++	s32 stbc_tx = 0;
++	s32 txbf_bfe_cap = 0;
++	s32 txbf_bfr_cap = 0;
++#endif 
++	s32 bw_cap = 0;
++	s32 cur_band = -1;
++	struct ieee80211_supported_band *bands[IEEE80211_NUM_BANDS] = {NULL, };
++
++	memset(bandlist, 0, sizeof(bandlist));
++	err = wldev_ioctl_get(dev, WLC_GET_BANDLIST, bandlist,
++		sizeof(bandlist));
++	if (unlikely(err)) {
++		WL_ERR(("error read bandlist (%d)\n", err));
++		return err;
++	}
++	err = wldev_ioctl_get(dev, WLC_GET_BAND, &cur_band,
++		sizeof(s32));
++	if (unlikely(err)) {
++		WL_ERR(("error (%d)\n", err));
++		return err;
++	}
++
++	err = wldev_iovar_getint(dev, "nmode", &nmode);
++	if (unlikely(err)) {
++		WL_ERR(("error reading nmode (%d)\n", err));
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	err = wldev_iovar_getint(dev, "vhtmode", &vhtmode);
++	if (unlikely(err)) {
++		WL_ERR(("error reading vhtmode (%d)\n", err));
++	}
++
++	if (vhtmode) {
++		err = wldev_iovar_getint(dev, "txstreams", &txstreams);
++		if (unlikely(err)) {
++			WL_ERR(("error reading txstreams (%d)\n", err));
++		}
++
++		err = wldev_iovar_getint(dev, "rxstreams", &rxstreams);
++		if (unlikely(err)) {
++			WL_ERR(("error reading rxstreams (%d)\n", err));
++		}
++
++		err = wldev_iovar_getint(dev, "ldpc_cap", &ldpc_cap);
++		if (unlikely(err)) {
++			WL_ERR(("error reading ldpc_cap (%d)\n", err));
++		}
++
++		err = wldev_iovar_getint(dev, "stbc_rx", &stbc_rx);
++		if (unlikely(err)) {
++			WL_ERR(("error reading stbc_rx (%d)\n", err));
++		}
++
++		err = wldev_iovar_getint(dev, "stbc_tx", &stbc_tx);
++		if (unlikely(err)) {
++			WL_ERR(("error reading stbc_tx (%d)\n", err));
++		}
++
++		err = wldev_iovar_getint(dev, "txbf_bfe_cap", &txbf_bfe_cap);
++		if (unlikely(err)) {
++			WL_ERR(("error reading txbf_bfe_cap (%d)\n", err));
++		}
++
++		err = wldev_iovar_getint(dev, "txbf_bfr_cap", &txbf_bfr_cap);
++		if (unlikely(err)) {
++			WL_ERR(("error reading txbf_bfr_cap (%d)\n", err));
++		}
++	}
++#endif 
++
++	/* For nmode and vhtmode   check bw cap */
++	if (nmode ||
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++		vhtmode ||
++#endif 
++		0) {
++		err = wldev_iovar_getint(dev, "mimo_bw_cap", &bw_cap);
++		if (unlikely(err)) {
++			WL_ERR(("error get mimo_bw_cap (%d)\n", err));
++		}
++	}
++
++	err = wl_construct_reginfo(cfg, bw_cap);
++	if (err) {
++		WL_ERR(("wl_construct_reginfo() fails err=%d\n", err));
++		if (err != BCME_UNSUPPORTED)
++			return err;
++	}
++
++	wiphy = bcmcfg_to_wiphy(cfg);
++	nband = bandlist[0];
++
++	for (i = 1; i <= nband && i < ARRAYSIZE(bandlist); i++) {
++		index = -1;
++		if (bandlist[i] == WLC_BAND_5G && __wl_band_5ghz_a.n_channels > 0) {
++			bands[IEEE80211_BAND_5GHZ] =
++				&__wl_band_5ghz_a;
++			index = IEEE80211_BAND_5GHZ;
++			if (nmode && (bw_cap == WLC_N_BW_40ALL || bw_cap == WLC_N_BW_20IN2G_40IN5G))
++				bands[index]->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++			/* VHT capabilities. */
++			if (vhtmode) {
++				/* Supported */
++				bands[index]->vht_cap.vht_supported = TRUE;
++
++				for (j = 1; j <= VHT_CAP_MCS_MAP_NSS_MAX; j++) {
++					/* TX stream rates. */
++					if (j <= txstreams) {
++						VHT_MCS_MAP_SET_MCS_PER_SS(j, VHT_CAP_MCS_MAP_0_9,
++							bands[index]->vht_cap.vht_mcs.tx_mcs_map);
++					} else {
++						VHT_MCS_MAP_SET_MCS_PER_SS(j, VHT_CAP_MCS_MAP_NONE,
++							bands[index]->vht_cap.vht_mcs.tx_mcs_map);
++					}
++
++					/* RX stream rates. */
++					if (j <= rxstreams) {
++						VHT_MCS_MAP_SET_MCS_PER_SS(j, VHT_CAP_MCS_MAP_0_9,
++							bands[index]->vht_cap.vht_mcs.rx_mcs_map);
++					} else {
++						VHT_MCS_MAP_SET_MCS_PER_SS(j, VHT_CAP_MCS_MAP_NONE,
++							bands[index]->vht_cap.vht_mcs.rx_mcs_map);
++					}
++				}
++
++
++				/* Capabilities */
++				/* 80 MHz is mandatory */
++				bands[index]->vht_cap.cap |=
++					IEEE80211_VHT_CAP_SHORT_GI_80;
++
++				if (WL_BW_CAP_160MHZ(bw_cap)) {
++					bands[index]->vht_cap.cap |=
++						IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ;
++					bands[index]->vht_cap.cap |=
++						IEEE80211_VHT_CAP_SHORT_GI_160;
++				}
++
++				bands[index]->vht_cap.cap |=
++					IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
++
++				if (ldpc_cap)
++					bands[index]->vht_cap.cap |=
++						IEEE80211_VHT_CAP_RXLDPC;
++
++				if (stbc_tx)
++					bands[index]->vht_cap.cap |=
++						IEEE80211_VHT_CAP_TXSTBC;
++
++				if (stbc_rx)
++					bands[index]->vht_cap.cap |=
++						(stbc_rx << VHT_CAP_INFO_RX_STBC_SHIFT);
++
++				if (txbf_bfe_cap)
++					bands[index]->vht_cap.cap |=
++						IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
++
++				if (txbf_bfr_cap) {
++					bands[index]->vht_cap.cap |=
++						IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE;
++				}
++
++				if (txbf_bfe_cap || txbf_bfr_cap) {
++					bands[index]->vht_cap.cap |=
++						(2 << VHT_CAP_INFO_NUM_BMFMR_ANT_SHIFT);
++					bands[index]->vht_cap.cap |=
++						((txstreams - 1) <<
++							VHT_CAP_INFO_NUM_SOUNDING_DIM_SHIFT);
++					bands[index]->vht_cap.cap |=
++						IEEE80211_VHT_CAP_VHT_LINK_ADAPTATION_VHT_MRQ_MFB;
++				}
++
++				/* AMPDU length limit, support max 1MB (2 ^ (13 + 7)) */
++				bands[index]->vht_cap.cap |=
++					(7 << VHT_CAP_INFO_AMPDU_MAXLEN_EXP_SHIFT);
++				WL_INFORM(("%s band[%d] vht_enab=%d vht_cap=%08x "
++					"vht_rx_mcs_map=%04x vht_tx_mcs_map=%04x\n",
++					__FUNCTION__, index,
++					bands[index]->vht_cap.vht_supported,
++					bands[index]->vht_cap.cap,
++					bands[index]->vht_cap.vht_mcs.rx_mcs_map,
++					bands[index]->vht_cap.vht_mcs.tx_mcs_map));
++			}
++#endif 
++		}
++		else if (bandlist[i] == WLC_BAND_2G && __wl_band_2ghz.n_channels > 0) {
++			bands[IEEE80211_BAND_2GHZ] =
++				&__wl_band_2ghz;
++			index = IEEE80211_BAND_2GHZ;
++			if (bw_cap == WLC_N_BW_40ALL)
++				bands[index]->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
++		}
++
++		if ((index >= 0) && nmode) {
++			bands[index]->ht_cap.cap |=
++				(IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_DSSSCCK40);
++			bands[index]->ht_cap.ht_supported = TRUE;
++			bands[index]->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
++			bands[index]->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
++			/* An HT shall support all EQM rates for one spatial stream */
++			bands[index]->ht_cap.mcs.rx_mask[0] = 0xff;
++		}
++
++	}
++
++	wiphy->bands[IEEE80211_BAND_2GHZ] = bands[IEEE80211_BAND_2GHZ];
++	wiphy->bands[IEEE80211_BAND_5GHZ] = bands[IEEE80211_BAND_5GHZ];
++
++	/* check if any bands populated otherwise makes 2Ghz as default */
++	if (wiphy->bands[IEEE80211_BAND_2GHZ] == NULL &&
++		wiphy->bands[IEEE80211_BAND_5GHZ] == NULL) {
++		/* Setup 2Ghz band as default */
++		wiphy->bands[IEEE80211_BAND_2GHZ] = &__wl_band_2ghz;
++	}
++
++	if (notify)
++		wiphy_apply_custom_regulatory(wiphy, &brcm_regdom);
++
++	return 0;
++}
++
++s32 wl_update_wiphybands(struct bcm_cfg80211 *cfg, bool notify)
++{
++	s32 err;
++
++	mutex_lock(&cfg->usr_sync);
++	err = __wl_update_wiphybands(cfg, notify);
++	mutex_unlock(&cfg->usr_sync);
++
++	return err;
++}
++
++static s32 __wl_cfg80211_up(struct bcm_cfg80211 *cfg)
++{
++	s32 err = 0;
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	struct wireless_dev *wdev = ndev->ieee80211_ptr;
++#ifdef WBTEXT
++	dhd_pub_t *dhd =  (dhd_pub_t *)(cfg->pub);
++#endif /* WBTEXT */
++#ifdef WLTDLS
++	u32 tdls;
++#endif /* WLTDLS */
++
++	WL_DBG(("In\n"));
++
++	if (!dhd_download_fw_on_driverload) {
++		err = wl_create_event_handler(cfg);
++		if (err) {
++			WL_ERR(("wl_create_event_handler failed\n"));
++			return err;
++		}
++		wl_init_event_handler(cfg);
++	}
++
++	err = dhd_config_dongle(cfg);
++	if (unlikely(err))
++		return err;
++
++	err = wl_config_ifmode(cfg, ndev, wdev->iftype);
++	if (unlikely(err && err != -EINPROGRESS)) {
++		WL_ERR(("wl_config_ifmode failed\n"));
++		if (err == -1) {
++			WL_ERR(("return error %d\n", err));
++			return err;
++		}
++	}
++
++	err = wl_init_scan(cfg);
++	if (err) {
++		WL_ERR(("wl_init_scan failed\n"));
++		return err;
++	}
++	err = __wl_update_wiphybands(cfg, true);
++	if (unlikely(err)) {
++		WL_ERR(("wl_update_wiphybands failed\n"));
++		if (err == -1) {
++			WL_ERR(("return error %d\n", err));
++			return err;
++		}
++	}
++
++#ifdef DHD_LOSSLESS_ROAMING
++	if (timer_pending(&cfg->roam_timeout)) {
++		_del_timer_sync(&cfg->roam_timeout);
++	}
++#endif /* DHD_LOSSLESS_ROAMING */
++
++	err = dhd_monitor_init(cfg->pub);
++
++#ifdef WBTEXT
++	/* when wifi up, set roam_prof to default value */
++	if (dhd->wbtext_support) {
++		if (dhd->op_mode & DHD_FLAG_STA_MODE) {
++			wl_cfg80211_wbtext_set_default(ndev);
++			wl_cfg80211_wbtext_clear_bssid_list(cfg);
++		}
++	}
++#endif /* WBTEXT */
++#ifdef WLTDLS
++	if (wldev_iovar_getint(ndev, "tdls_enable", &tdls) == 0) {
++		WL_DBG(("TDLS supported in fw\n"));
++		cfg->tdls_supported = true;
++	}
++#endif /* WLTDLS */
++	INIT_DELAYED_WORK(&cfg->pm_enable_work, wl_cfg80211_work_handler);
++	wl_set_drv_status(cfg, READY, ndev);
++	return err;
++}
++
++static s32 __wl_cfg80211_down(struct bcm_cfg80211 *cfg)
++{
++	s32 err = 0;
++	unsigned long flags;
++	struct net_info *iter, *next;
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++#if defined(WL_CFG80211) && (defined(WL_ENABLE_P2P_IF) || \
++	defined(WL_NEW_CFG_PRIVCMD_SUPPORT)) && !defined(PLATFORM_SLP)
++	struct net_device *p2p_net = cfg->p2p_net;
++#endif 
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO) || defined(BCMDBUS)
++	dhd_pub_t *dhd =  (dhd_pub_t *)(cfg->pub);
++#endif /* BCMSDIO || BCMDBUS */
++#endif /* PROP_TXSTATUS_VSDB */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
++	struct cfg80211_scan_info info;
++#endif
++
++	WL_DBG(("In\n"));
++
++	/* Check if cfg80211 interface is already down */
++	if (!wl_get_drv_status(cfg, READY, ndev)) {
++		WL_DBG(("cfg80211 interface is already down\n"));
++		return err;	/* it is even not ready */
++	}
++
++#ifdef WLTDLS
++	cfg->tdls_supported = false;
++#endif /* WLTDLS */
++
++	/* Delete pm_enable_work */
++	wl_add_remove_pm_enable_work(cfg, WL_PM_WORKQ_DEL);
++
++	/* clear all the security setting on primary Interface */
++	wl_cfg80211_clear_security(cfg);
++
++
++	if (cfg->p2p_supported) {
++		wl_clr_p2p_status(cfg, GO_NEG_PHASE);
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO) || defined(BCMDBUS)
++		if (wl_cfgp2p_vif_created(cfg)) {
++			bool enabled = false;
++			dhd_wlfc_get_enable(dhd, &enabled);
++			if (enabled && cfg->wlfc_on && dhd->op_mode != DHD_FLAG_HOSTAP_MODE &&
++				dhd->op_mode != DHD_FLAG_IBSS_MODE) {
++				dhd_wlfc_deinit(dhd);
++				cfg->wlfc_on = false;
++			}
++		}
++#endif /* BCMSDIO || BCMDBUS */
++#endif /* PROP_TXSTATUS_VSDB */
++	}
++
++
++	/* clean up any left over interfaces */
++	wl_cfg80211_cleanup_virtual_ifaces(ndev, false);
++
++	/* If primary BSS is operational (for e.g SoftAP), bring it down */
++	if (wl_cfg80211_bss_isup(ndev, 0)) {
++		if (wl_cfg80211_bss_up(cfg, ndev, 0, 0) < 0)
++			WL_ERR(("BSS down failed \n"));
++	}
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++	for_each_ndev(cfg, iter, next) {
++		if (iter->ndev) /* p2p discovery iface is null */
++			wl_set_drv_status(cfg, SCAN_ABORTING, iter->ndev);
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++
++#ifdef P2P_LISTEN_OFFLOADING
++	wl_cfg80211_p2plo_deinit(cfg);
++#endif /* P2P_LISTEN_OFFLOADING */
++
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++	if (cfg->scan_request) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
++		info.aborted = true;
++		cfg80211_scan_done(cfg->scan_request, &info);
++#else
++		cfg80211_scan_done(cfg->scan_request, true);
++#endif
++		cfg->scan_request = NULL;
++	}
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++	for_each_ndev(cfg, iter, next) {
++		/* p2p discovery iface ndev ptr could be null */
++		if (iter->ndev == NULL)
++			continue;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
++		if (wl_get_drv_status(cfg, CONNECTED, iter->ndev)) {
++			CFG80211_DISCONNECTED(iter->ndev, 0, NULL, 0, false, GFP_KERNEL);
++		}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) */
++		wl_clr_drv_status(cfg, READY, iter->ndev);
++		wl_clr_drv_status(cfg, SCANNING, iter->ndev);
++		wl_clr_drv_status(cfg, SCAN_ABORTING, iter->ndev);
++		wl_clr_drv_status(cfg, CONNECTING, iter->ndev);
++		wl_clr_drv_status(cfg, CONNECTED, iter->ndev);
++		wl_clr_drv_status(cfg, DISCONNECTING, iter->ndev);
++		wl_clr_drv_status(cfg, AP_CREATED, iter->ndev);
++		wl_clr_drv_status(cfg, AP_CREATING, iter->ndev);
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	bcmcfg_to_prmry_ndev(cfg)->ieee80211_ptr->iftype =
++		NL80211_IFTYPE_STATION;
++#if defined(WL_CFG80211) && (defined(WL_ENABLE_P2P_IF) || \
++	defined(WL_NEW_CFG_PRIVCMD_SUPPORT)) && !defined(PLATFORM_SLP)
++		if (p2p_net)
++			dev_close(p2p_net);
++#endif 
++
++	/* Avoid deadlock from wl_cfg80211_down */
++	if (!dhd_download_fw_on_driverload) {
++		mutex_unlock(&cfg->usr_sync);
++		wl_destroy_event_handler(cfg);
++		mutex_lock(&cfg->usr_sync);
++	}
++
++	wl_flush_eq(cfg);
++	wl_link_down(cfg);
++	if (cfg->p2p_supported) {
++		if (timer_pending(&cfg->p2p->listen_timer))
++			_del_timer_sync(&cfg->p2p->listen_timer);
++		wl_cfgp2p_down(cfg);
++	}
++
++	if (timer_pending(&cfg->scan_timeout)) {
++		_del_timer_sync(&cfg->scan_timeout);
++	}
++
++	DHD_OS_SCAN_WAKE_UNLOCK((dhd_pub_t *)(cfg->pub));
++
++	dhd_monitor_uninit();
++#ifdef WLAIBSS_MCHAN
++	bcm_cfg80211_del_ibss_if(cfg->wdev->wiphy, cfg->ibss_cfgdev);
++#endif /* WLAIBSS_MCHAN */
++
++
++#ifdef WL11U
++	/* Clear interworking element. */
++	if (cfg->wl11u) {
++		cfg->wl11u = FALSE;
++	}
++#endif /* WL11U */
++
++#ifdef CUSTOMER_HW4_DEBUG
++	if (wl_scan_timeout_dbg_enabled) {
++		wl_scan_timeout_dbg_clear();
++	}
++#endif /* CUSTOMER_HW4_DEBUG */
++
++	cfg->disable_roam_event = false;
++
++	DNGL_FUNC(dhd_cfg80211_down, (cfg));
++
++#ifdef DHD_IFDEBUG
++	/* Printout all netinfo entries */
++	wl_probe_wdev_all(cfg);
++#endif /* DHD_IFDEBUG */
++
++	return err;
++}
++
++s32 wl_cfg80211_up(struct net_device *net)
++{
++	struct bcm_cfg80211 *cfg;
++	s32 err = 0;
++	int val = 1;
++	dhd_pub_t *dhd;
++#ifdef DISABLE_PM_BCNRX
++	s32 interr = 0;
++	uint param = 0;
++	s8 iovbuf[WLC_IOCTL_SMLEN];
++#endif /* DISABLE_PM_BCNRX */
++
++	WL_DBG(("In\n"));
++	cfg = wl_get_cfg(net);
++
++	if ((err = wldev_ioctl_get(bcmcfg_to_prmry_ndev(cfg), WLC_GET_VERSION, &val,
++		sizeof(int)) < 0)) {
++		WL_ERR(("WLC_GET_VERSION failed, err=%d\n", err));
++		return err;
++	}
++	val = dtoh32(val);
++	if (val != WLC_IOCTL_VERSION && val != 1) {
++		WL_ERR(("Version mismatch, please upgrade. Got %d, expected %d or 1\n",
++			val, WLC_IOCTL_VERSION));
++		return BCME_VERSION;
++	}
++	ioctl_version = val;
++	WL_TRACE(("WLC_GET_VERSION=%d\n", ioctl_version));
++	wl_cfg80211_check_in4way(cfg, net, NO_SCAN_IN4WAY|NO_BTC_IN4WAY|WAIT_DISCONNECTED,
++		WL_EXT_STATUS_DISCONNECTED, NULL);
++
++	mutex_lock(&cfg->usr_sync);
++	dhd = (dhd_pub_t *)(cfg->pub);
++	if (!(dhd->op_mode & DHD_FLAG_HOSTAP_MODE)) {
++		err = wl_cfg80211_attach_post(bcmcfg_to_prmry_ndev(cfg));
++		if (unlikely(err)) {
++			mutex_unlock(&cfg->usr_sync);
++			return err;
++		}
++	}
++#ifdef WLMESH_CFG80211
++	cfg->wdev->wiphy->features |= NL80211_FEATURE_USERSPACE_MPM;
++#endif /* WLMESH_CFG80211 */
++
++	err = __wl_cfg80211_up(cfg);
++	if (unlikely(err))
++		WL_ERR(("__wl_cfg80211_up failed\n"));
++
++
++
++	/* IOVAR configurations with 'up' condition */
++#ifdef DISABLE_PM_BCNRX
++	interr = wldev_iovar_setbuf(bcmcfg_to_prmry_ndev(cfg), "pm_bcnrx", (char *)&param,
++			sizeof(param), iovbuf, sizeof(iovbuf), NULL);
++	if (unlikely(interr)) {
++		WL_ERR(("Set pm_bcnrx returned (%d)\n", interr));
++	}
++#endif /* DISABLE_PM_BCNRX */
++
++	mutex_unlock(&cfg->usr_sync);
++
++#ifdef WLAIBSS_MCHAN
++	bcm_cfg80211_add_ibss_if(cfg->wdev->wiphy, IBSS_IF_NAME);
++#endif /* WLAIBSS_MCHAN */
++
++#ifdef DUAL_STA_STATIC_IF
++#ifdef WL_VIRTUAL_APSTA
++#error "Both DUAL STA and DUAL_STA_STATIC_IF can't be enabled together"
++#endif
++	/* Static Interface support is currently supported only for STA only builds (without P2P) */
++	wl_cfg80211_create_iface(cfg->wdev->wiphy, NL80211_IFTYPE_STATION, NULL, "wlan%d");
++#endif /* DUAL_STA_STATIC_IF */
++
++	return err;
++}
++
++/* Private Event to Supplicant with indication that chip hangs */
++int wl_cfg80211_hang(struct net_device *dev, u16 reason)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	dhd_pub_t *dhd;
++#if defined(SOFTAP_SEND_HANGEVT)
++	/* specifc mac address used for hang event */
++	uint8 hang_mac[ETHER_ADDR_LEN] = {0x11, 0x11, 0x11, 0x11, 0x11, 0x11};
++#endif /* SOFTAP_SEND_HANGEVT */
++	if (!cfg) {
++		return BCME_ERROR;
++	}
++
++	dhd = (dhd_pub_t *)(cfg->pub);
++#if defined(DHD_HANG_SEND_UP_TEST)
++	if (dhd->req_hang_type) {
++		WL_ERR(("%s, Clear HANG test request 0x%x\n",
++			__FUNCTION__, dhd->req_hang_type));
++		dhd->req_hang_type = 0;
++	}
++#endif /* DHD_HANG_SEND_UP_TEST */
++	if ((dhd->hang_reason <= HANG_REASON_MASK) || (dhd->hang_reason >= HANG_REASON_MAX)) {
++		WL_ERR(("%s, Invalid hang reason 0x%x\n",
++			__FUNCTION__, dhd->hang_reason));
++		dhd->hang_reason = HANG_REASON_UNKNOWN;
++	}
++#ifdef DHD_USE_EXTENDED_HANG_REASON
++	if (dhd->hang_reason != 0) {
++		reason = dhd->hang_reason;
++	}
++#endif /* DHD_USE_EXTENDED_HANG_REASON */
++	WL_ERR(("In : chip crash eventing, reason=0x%x\n", (uint32)(dhd->hang_reason)));
++
++	wl_add_remove_pm_enable_work(cfg, WL_PM_WORKQ_DEL);
++#ifdef SOFTAP_SEND_HANGEVT
++	if (dhd->op_mode & DHD_FLAG_HOSTAP_MODE) {
++		cfg80211_del_sta(dev, hang_mac, GFP_ATOMIC);
++	} else
++#endif /* SOFTAP_SEND_HANGEVT */
++	{
++		CFG80211_DISCONNECTED(dev, reason, NULL, 0, false, GFP_KERNEL);
++	}
++#if defined(RSSIAVG)
++	wl_free_rssi_cache(&cfg->g_rssi_cache_ctrl);
++#endif
++#if defined(BSSCACHE)
++	wl_free_bss_cache(&cfg->g_bss_cache_ctrl);
++#endif
++	if (cfg != NULL) {
++		wl_link_down(cfg);
++	}
++	return 0;
++}
++
++s32 wl_cfg80211_down(struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	s32 err = 0;
++
++	WL_DBG(("In\n"));
++	if (cfg == NULL)
++		return err;
++	mutex_lock(&cfg->usr_sync);
++#if defined(RSSIAVG)
++	wl_free_rssi_cache(&cfg->g_rssi_cache_ctrl);
++#endif
++#if defined(BSSCACHE)
++	wl_free_bss_cache(&cfg->g_bss_cache_ctrl);
++#endif
++	err = __wl_cfg80211_down(cfg);
++	mutex_unlock(&cfg->usr_sync);
++
++	return err;
++}
++
++static void *wl_read_prof(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 item)
++{
++	unsigned long flags;
++	void *rptr = NULL;
++	struct wl_profile *profile = wl_get_profile_by_netdev(cfg, ndev);
++
++	if (!profile)
++		return NULL;
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++	switch (item) {
++	case WL_PROF_SEC:
++		rptr = &profile->sec;
++		break;
++	case WL_PROF_ACT:
++		rptr = &profile->active;
++		break;
++	case WL_PROF_BSSID:
++		rptr = profile->bssid;
++		break;
++	case WL_PROF_SSID:
++		rptr = &profile->ssid;
++		break;
++	case WL_PROF_CHAN:
++		rptr = &profile->channel;
++		break;
++	}
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++	if (!rptr)
++		WL_ERR(("invalid item (%d)\n", item));
++	return rptr;
++}
++
++static s32
++wl_update_prof(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, const void *data, s32 item)
++{
++	s32 err = 0;
++	const struct wlc_ssid *ssid;
++	unsigned long flags;
++	struct wl_profile *profile = wl_get_profile_by_netdev(cfg, ndev);
++
++	if (!profile)
++		return WL_INVALID;
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++	switch (item) {
++	case WL_PROF_SSID:
++		ssid = (const wlc_ssid_t *) data;
++		memset(profile->ssid.SSID, 0,
++			sizeof(profile->ssid.SSID));
++		profile->ssid.SSID_len = MIN(ssid->SSID_len, DOT11_MAX_SSID_LEN);
++		memcpy(profile->ssid.SSID, ssid->SSID, profile->ssid.SSID_len);
++		break;
++	case WL_PROF_BSSID:
++		if (data)
++			memcpy(profile->bssid, data, ETHER_ADDR_LEN);
++		else
++			memset(profile->bssid, 0, ETHER_ADDR_LEN);
++		break;
++	case WL_PROF_SEC:
++		memcpy(&profile->sec, data, sizeof(profile->sec));
++		break;
++	case WL_PROF_ACT:
++		profile->active = *(const bool *)data;
++		break;
++	case WL_PROF_BEACONINT:
++		profile->beacon_interval = *(const u16 *)data;
++		break;
++	case WL_PROF_DTIMPERIOD:
++		profile->dtim_period = *(const u8 *)data;
++		break;
++	case WL_PROF_CHAN:
++		profile->channel = *(const u32*)data;
++		break;
++	default:
++		err = -EOPNOTSUPP;
++		break;
++	}
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++
++	if (err == -EOPNOTSUPP)
++		WL_ERR(("unsupported item (%d)\n", item));
++
++	return err;
++}
++
++void wl_cfg80211_dbg_level(u32 level)
++{
++	/*
++	* prohibit to change debug level
++	* by insmod parameter.
++	* eventually debug level will be configured
++	* in compile time by using CONFIG_XXX
++	*/
++	/* wl_dbg_level = level; */
++}
++
++static bool wl_is_ibssmode(struct bcm_cfg80211 *cfg, struct net_device *ndev)
++{
++	return wl_get_mode_by_netdev(cfg, ndev) == WL_MODE_IBSS;
++}
++
++static __used bool wl_is_ibssstarter(struct bcm_cfg80211 *cfg)
++{
++	return cfg->ibss_starter;
++}
++
++static void wl_rst_ie(struct bcm_cfg80211 *cfg)
++{
++	struct wl_ie *ie = wl_to_ie(cfg);
++
++	ie->offset = 0;
++}
++
++static __used s32 wl_add_ie(struct bcm_cfg80211 *cfg, u8 t, u8 l, u8 *v)
++{
++	struct wl_ie *ie = wl_to_ie(cfg);
++	s32 err = 0;
++
++	if (unlikely(ie->offset + l + 2 > WL_TLV_INFO_MAX)) {
++		WL_ERR(("ei crosses buffer boundary\n"));
++		return -ENOSPC;
++	}
++	ie->buf[ie->offset] = t;
++	ie->buf[ie->offset + 1] = l;
++	memcpy(&ie->buf[ie->offset + 2], v, l);
++	ie->offset += l + 2;
++
++	return err;
++}
++
++static void wl_update_hidden_ap_ie(struct wl_bss_info *bi, const u8 *ie_stream, u32 *ie_size,
++	bool roam)
++{
++	u8 *ssidie;
++	int32 ssid_len = MIN(bi->SSID_len, DOT11_MAX_SSID_LEN);
++	int32 remaining_ie_buf_len, available_buffer_len;
++	/* cfg80211_find_ie defined in kernel returning const u8 */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++	ssidie = (u8 *)cfg80211_find_ie(WLAN_EID_SSID, ie_stream, *ie_size);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	/* ERROR out if
++	 * 1. No ssid IE is FOUND or
++	 * 2. New ssid length is > what was allocated for existing ssid (as
++	 * we do not want to overwrite the rest of the IEs) or
++	 * 3. If in case of erroneous buffer input where ssid length doesnt match the space
++	 * allocated to it.
++	 */
++	if (!ssidie) {
++		return;
++	}
++	available_buffer_len = ((int)(*ie_size)) - (ssidie + 2 - ie_stream);
++	remaining_ie_buf_len = available_buffer_len - (int)ssidie[1];
++	if ((ssid_len > ssidie[1]) ||
++		(ssidie[1] > available_buffer_len)) {
++		return;
++	}
++
++
++	if (ssidie[1] != ssid_len) {
++		if (ssidie[1]) {
++			WL_ERR(("%s: Wrong SSID len: %d != %d\n",
++				__FUNCTION__, ssidie[1], bi->SSID_len));
++		}
++		if (roam) {
++			WL_ERR(("Changing the SSID Info.\n"));
++			memmove(ssidie + ssid_len + 2,
++				(ssidie + 2) + ssidie[1],
++				remaining_ie_buf_len);
++			memcpy(ssidie + 2, bi->SSID, ssid_len);
++			*ie_size = *ie_size + ssid_len - ssidie[1];
++			ssidie[1] = ssid_len;
++		}
++		return;
++	}
++	if (*(ssidie + 2) == '\0')
++		 memcpy(ssidie + 2, bi->SSID, ssid_len);
++	return;
++}
++
++static s32 wl_mrg_ie(struct bcm_cfg80211 *cfg, u8 *ie_stream, u16 ie_size)
++{
++	struct wl_ie *ie = wl_to_ie(cfg);
++	s32 err = 0;
++
++	if (unlikely(ie->offset + ie_size > WL_TLV_INFO_MAX)) {
++		WL_ERR(("ei_stream crosses buffer boundary\n"));
++		return -ENOSPC;
++	}
++	memcpy(&ie->buf[ie->offset], ie_stream, ie_size);
++	ie->offset += ie_size;
++
++	return err;
++}
++
++static s32 wl_cp_ie(struct bcm_cfg80211 *cfg, u8 *dst, u16 dst_size)
++{
++	struct wl_ie *ie = wl_to_ie(cfg);
++	s32 err = 0;
++
++	if (unlikely(ie->offset > dst_size)) {
++		WL_ERR(("dst_size is not enough\n"));
++		return -ENOSPC;
++	}
++	memcpy(dst, &ie->buf[0], ie->offset);
++
++	return err;
++}
++
++static u32 wl_get_ielen(struct bcm_cfg80211 *cfg)
++{
++	struct wl_ie *ie = wl_to_ie(cfg);
++
++	return ie->offset;
++}
++
++static void wl_link_up(struct bcm_cfg80211 *cfg)
++{
++	cfg->link_up = true;
++}
++
++static void wl_link_down(struct bcm_cfg80211 *cfg)
++{
++	struct wl_connect_info *conn_info = wl_to_conn(cfg);
++
++	WL_DBG(("In\n"));
++	cfg->link_up = false;
++	if (conn_info) {
++		conn_info->req_ie_len = 0;
++		conn_info->resp_ie_len = 0;
++	}
++}
++
++static unsigned long wl_lock_eq(struct bcm_cfg80211 *cfg)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&cfg->eq_lock, flags);
++	return flags;
++}
++
++static void wl_unlock_eq(struct bcm_cfg80211 *cfg, unsigned long flags)
++{
++	spin_unlock_irqrestore(&cfg->eq_lock, flags);
++}
++
++static void wl_init_eq_lock(struct bcm_cfg80211 *cfg)
++{
++	spin_lock_init(&cfg->eq_lock);
++}
++
++static void wl_delay(u32 ms)
++{
++	if (in_atomic() || (ms < jiffies_to_msecs(1))) {
++		OSL_DELAY(ms*1000);
++	} else {
++		OSL_SLEEP(ms);
++	}
++}
++
++s32 wl_cfg80211_get_p2p_dev_addr(struct net_device *net, struct ether_addr *p2pdev_addr)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(net);
++	struct ether_addr primary_mac;
++	if (!cfg->p2p)
++		return -1;
++	if (!p2p_is_on(cfg)) {
++		get_primary_mac(cfg, &primary_mac);
++		wl_cfgp2p_generate_bss_mac(cfg, &primary_mac);
++	} else {
++		memcpy(p2pdev_addr->octet, wl_to_p2p_bss_macaddr(cfg, P2PAPI_BSSCFG_DEVICE).octet,
++			ETHER_ADDR_LEN);
++	}
++
++	return 0;
++}
++s32 wl_cfg80211_set_p2p_noa(struct net_device *net, char* buf, int len)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(net);
++
++	return wl_cfgp2p_set_p2p_noa(cfg, net, buf, len);
++}
++
++s32 wl_cfg80211_get_p2p_noa(struct net_device *net, char* buf, int len)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(net);
++
++	return wl_cfgp2p_get_p2p_noa(cfg, net, buf, len);
++}
++
++s32 wl_cfg80211_set_p2p_ps(struct net_device *net, char* buf, int len)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(net);
++
++	return wl_cfgp2p_set_p2p_ps(cfg, net, buf, len);
++}
++
++s32 wl_cfg80211_set_p2p_ecsa(struct net_device *net, char* buf, int len)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(net);
++
++	return wl_cfgp2p_set_p2p_ecsa(cfg, net, buf, len);
++}
++
++s32 wl_cfg80211_increase_p2p_bw(struct net_device *net, char* buf, int len)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(net);
++
++	return wl_cfgp2p_increase_p2p_bw(cfg, net, buf, len);
++}
++
++#ifdef P2PLISTEN_AP_SAMECHN
++s32 wl_cfg80211_set_p2p_resp_ap_chn(struct net_device *net, s32 enable)
++{
++	s32 ret = wldev_iovar_setint(net, "p2p_resp_ap_chn", enable);
++
++	if ((ret == 0) && enable) {
++		/* disable PM for p2p responding on infra AP channel */
++		s32 pm = PM_OFF;
++
++		ret = wldev_ioctl_set(net, WLC_SET_PM, &pm, sizeof(pm));
++	}
++
++	return ret;
++}
++#endif /* P2PLISTEN_AP_SAMECHN */
++
++s32 wl_cfg80211_channel_to_freq(u32 channel)
++{
++	int freq = 0;
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39)
++	freq = ieee80211_channel_to_frequency(channel);
++#else
++	{
++		u16 band = 0;
++		if (channel <= CH_MAX_2G_CHANNEL)
++			band = IEEE80211_BAND_2GHZ;
++		else
++			band = IEEE80211_BAND_5GHZ;
++		freq = ieee80211_channel_to_frequency(channel, band);
++	}
++#endif
++	return freq;
++}
++
++
++#ifdef WLTDLS
++static s32
++wl_tdls_event_handler(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data) {
++
++	struct net_device *ndev = NULL;
++	u32 reason = ntoh32(e->reason);
++	s8 *msg = NULL;
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	switch (reason) {
++	case WLC_E_TDLS_PEER_DISCOVERED :
++		msg = " TDLS PEER DISCOVERD ";
++		break;
++	case WLC_E_TDLS_PEER_CONNECTED :
++		if (cfg->tdls_mgmt_frame) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
++			cfg80211_rx_mgmt(cfgdev, cfg->tdls_mgmt_freq, 0,
++					cfg->tdls_mgmt_frame, cfg->tdls_mgmt_frame_len, 0);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 12, 0))
++			cfg80211_rx_mgmt(cfgdev, cfg->tdls_mgmt_freq, 0,
++					cfg->tdls_mgmt_frame, cfg->tdls_mgmt_frame_len,	0,
++					GFP_ATOMIC);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) || \
++			defined(WL_COMPAT_WIRELESS)
++			cfg80211_rx_mgmt(cfgdev, cfg->tdls_mgmt_freq, 0,
++					cfg->tdls_mgmt_frame, cfg->tdls_mgmt_frame_len,
++					GFP_ATOMIC);
++#else
++			cfg80211_rx_mgmt(cfgdev, cfg->tdls_mgmt_freq,
++					cfg->tdls_mgmt_frame, cfg->tdls_mgmt_frame_len, GFP_ATOMIC);
++#endif 
++		}
++		msg = " TDLS PEER CONNECTED ";
++#ifdef SUPPORT_SET_CAC
++		/* TDLS connect reset CAC */
++		wl_cfg80211_set_cac(cfg, 0);
++#endif /* SUPPORT_SET_CAC */
++		break;
++	case WLC_E_TDLS_PEER_DISCONNECTED :
++		if (cfg->tdls_mgmt_frame) {
++			kfree(cfg->tdls_mgmt_frame);
++			cfg->tdls_mgmt_frame = NULL;
++			cfg->tdls_mgmt_freq = 0;
++		}
++		msg = "TDLS PEER DISCONNECTED ";
++#ifdef SUPPORT_SET_CAC
++		/* TDLS disconnec, set CAC */
++		wl_cfg80211_set_cac(cfg, 1);
++#endif /* SUPPORT_SET_CAC */
++		break;
++	}
++	if (msg) {
++		WL_ERR(("%s: " MACDBG " on %s ndev\n", msg, MAC2STRDBG((const u8*)(&e->addr)),
++			(bcmcfg_to_prmry_ndev(cfg) == ndev) ? "primary" : "secondary"));
++	}
++	return 0;
++
++}
++#endif /* WLTDLS */
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 2, 0))
++static s32
++#if (defined(CONFIG_ARCH_MSM) && defined(TDLS_MGMT_VERSION2)) || (LINUX_VERSION_CODE < \
++	KERNEL_VERSION(3, 16, 0) && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))
++wl_cfg80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev,
++	u8 *peer, u8 action_code, u8 dialog_token, u16 status_code,
++	u32 peer_capability, const u8 *buf, size_t len)
++#elif ((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) && \
++		(LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0)))
++wl_cfg80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev,
++	const u8 *peer, u8 action_code, u8 dialog_token, u16 status_code,
++	u32 peer_capability, const u8 *buf, size_t len)
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
++wl_cfg80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev,
++       const u8 *peer, u8 action_code, u8 dialog_token, u16 status_code,
++       u32 peer_capability, bool initiator, const u8 *buf, size_t len)
++#else /* CONFIG_ARCH_MSM && TDLS_MGMT_VERSION2 */
++wl_cfg80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev,
++	u8 *peer, u8 action_code, u8 dialog_token, u16 status_code,
++	const u8 *buf, size_t len)
++#endif /* CONFIG_ARCH_MSM && TDLS_MGMT_VERSION2 */
++{
++	s32 ret = 0;
++#ifdef WLTDLS
++	struct bcm_cfg80211 *cfg;
++	tdls_wfd_ie_iovar_t info;
++	memset(&info, 0, sizeof(tdls_wfd_ie_iovar_t));
++	cfg = wl_get_cfg(dev);
++
++#if defined(CONFIG_ARCH_MSM) && defined(TDLS_MGMT_VERSION2)
++	/* Some customer platform back ported this feature from kernel 3.15 to kernel 3.10
++	 * and that cuases build error
++	 */
++	BCM_REFERENCE(peer_capability);
++#endif  /* CONFIG_ARCH_MSM && TDLS_MGMT_VERSION2 */
++
++	switch (action_code) {
++		/* We need to set TDLS Wifi Display IE to firmware
++		 * using tdls_wfd_ie iovar
++		 */
++		case WLAN_TDLS_SET_PROBE_WFD_IE:
++			WL_ERR(("%s WLAN_TDLS_SET_PROBE_WFD_IE\n", __FUNCTION__));
++			info.mode = TDLS_WFD_PROBE_IE_TX;
++			memcpy(&info.data, buf, len);
++			info.length = len;
++			break;
++		case WLAN_TDLS_SET_SETUP_WFD_IE:
++			WL_ERR(("%s WLAN_TDLS_SET_SETUP_WFD_IE\n", __FUNCTION__));
++			info.mode = TDLS_WFD_IE_TX;
++			memcpy(&info.data, buf, len);
++			info.length = len;
++			break;
++		case WLAN_TDLS_SET_WFD_ENABLED:
++			WL_ERR(("%s WLAN_TDLS_SET_MODE_WFD_ENABLED\n", __FUNCTION__));
++			dhd_tdls_set_mode((dhd_pub_t *)(cfg->pub), true);
++			goto out;
++		case WLAN_TDLS_SET_WFD_DISABLED:
++			WL_ERR(("%s WLAN_TDLS_SET_MODE_WFD_DISABLED\n", __FUNCTION__));
++			dhd_tdls_set_mode((dhd_pub_t *)(cfg->pub), false);
++			goto out;
++		default:
++			WL_ERR(("Unsupported action code : %d\n", action_code));
++			goto out;
++	}
++	ret = wldev_iovar_setbuf(dev, "tdls_wfd_ie", &info, sizeof(info),
++			cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++
++	if (ret) {
++		WL_ERR(("tdls_wfd_ie error %d\n", ret));
++	}
++
++out:
++#endif /* WLTDLS */
++	return ret;
++}
++
++static s32
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++wl_cfg80211_tdls_oper(struct wiphy *wiphy, struct net_device *dev,
++	const u8 *peer, enum nl80211_tdls_operation oper)
++#else
++wl_cfg80211_tdls_oper(struct wiphy *wiphy, struct net_device *dev,
++	u8 *peer, enum nl80211_tdls_operation oper)
++#endif
++{
++	s32 ret = 0;
++#ifdef WLTDLS
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	tdls_iovar_t info;
++	dhd_pub_t *dhdp;
++	bool tdls_auto_mode = false;
++	dhdp = (dhd_pub_t *)(cfg->pub);
++	memset(&info, 0, sizeof(tdls_iovar_t));
++	if (peer) {
++		memcpy(&info.ea, peer, ETHER_ADDR_LEN);
++	} else {
++		return -1;
++	}
++	switch (oper) {
++	case NL80211_TDLS_DISCOVERY_REQ:
++		/* If the discovery request is broadcast then we need to set
++		 * info.mode to Tunneled Probe Request
++		 */
++		if (memcmp(peer, (const uint8 *)BSSID_BROADCAST, ETHER_ADDR_LEN) == 0) {
++			info.mode = TDLS_MANUAL_EP_WFD_TPQ;
++			WL_ERR(("%s TDLS TUNNELED PRBOBE REQUEST\n", __FUNCTION__));
++		} else {
++			info.mode = TDLS_MANUAL_EP_DISCOVERY;
++		}
++		break;
++	case NL80211_TDLS_SETUP:
++		if (dhdp->tdls_mode == true) {
++			info.mode = TDLS_MANUAL_EP_CREATE;
++			tdls_auto_mode = false;
++			/* Do tear down and create a fresh one */
++			ret = wl_cfg80211_tdls_config(cfg, TDLS_STATE_TEARDOWN, tdls_auto_mode);
++			if (ret < 0) {
++				return ret;
++			}
++		} else {
++			tdls_auto_mode = true;
++		}
++		break;
++	case NL80211_TDLS_TEARDOWN:
++		info.mode = TDLS_MANUAL_EP_DELETE;
++		break;
++	default:
++		WL_ERR(("Unsupported operation : %d\n", oper));
++		goto out;
++	}
++	/* turn on TDLS */
++	wl_cfg80211_tdls_config(cfg, TDLS_STATE_SETUP, tdls_auto_mode);
++	if (ret < 0) {
++		return ret;
++	}
++	if (info.mode) {
++		ret = wldev_iovar_setbuf(dev, "tdls_endpoint", &info, sizeof(info),
++			cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++		if (ret) {
++			WL_ERR(("tdls_endpoint error %d\n", ret));
++		}
++	}
++out:
++	if (ret) {
++		return -ENOTSUPP;
++	}
++#endif /* WLTDLS */
++	return ret;
++}
++#endif 
++
++/*
++ * This function returns no of bytes written
++ * In case of failure return zero, not bcme_error
++ */
++s32 wl_cfg80211_set_wps_p2p_ie(struct net_device *ndev, char *buf, int len,
++	enum wl_management_type type)
++{
++	struct bcm_cfg80211 *cfg;
++	s32 ret = 0;
++	struct ether_addr primary_mac;
++	s32 bssidx = 0;
++	s32 pktflag = 0;
++	cfg = wl_get_cfg(ndev);
++
++	if (wl_get_drv_status(cfg, AP_CREATING, ndev)) {
++		/* Vendor IEs should be set to FW
++		 * after SoftAP interface is brought up
++		 */
++		WL_DBG(("Skipping set IE since AP is not up \n"));
++		goto exit;
++	} else  if (ndev == bcmcfg_to_prmry_ndev(cfg)) {
++		/* Either stand alone AP case or P2P discovery */
++		if (wl_get_drv_status(cfg, AP_CREATED, ndev)) {
++			/* Stand alone AP case on primary interface */
++			WL_DBG(("Apply IEs for Primary AP Interface \n"));
++			bssidx = 0;
++		} else {
++			if (!cfg->p2p) {
++				/* If p2p not initialized, return failure */
++				WL_ERR(("P2P not initialized \n"));
++				goto exit;
++			}
++			/* P2P Discovery case (p2p listen) */
++			if (!cfg->p2p->on) {
++				/* Turn on Discovery interface */
++				get_primary_mac(cfg, &primary_mac);
++				wl_cfgp2p_generate_bss_mac(cfg, &primary_mac);
++				p2p_on(cfg) = true;
++				ret = wl_cfgp2p_enable_discovery(cfg, ndev, NULL, 0);
++				if (unlikely(ret)) {
++					WL_ERR(("Enable discovery failed \n"));
++					goto exit;
++				}
++			}
++			WL_DBG(("Apply IEs for P2P Discovery Iface \n"));
++			ndev = wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_PRIMARY);
++			bssidx = wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++		}
++	} else {
++		/* Virtual AP/ P2P Group Interface */
++		WL_DBG(("Apply IEs for iface:%s\n", ndev->name));
++		bssidx = wl_get_bssidx_by_wdev(cfg, ndev->ieee80211_ptr);
++	}
++
++	if (ndev != NULL) {
++		switch (type) {
++			case WL_BEACON:
++				pktflag = VNDR_IE_BEACON_FLAG;
++				break;
++			case WL_PROBE_RESP:
++				pktflag = VNDR_IE_PRBRSP_FLAG;
++				break;
++			case WL_ASSOC_RESP:
++				pktflag = VNDR_IE_ASSOCRSP_FLAG;
++				break;
++		}
++		if (pktflag) {
++			ret = wl_cfg80211_set_mgmt_vndr_ies(cfg,
++				ndev_to_cfgdev(ndev), bssidx, pktflag, buf, len);
++		}
++	}
++exit:
++	return ret;
++}
++
++#ifdef WL_SUPPORT_AUTO_CHANNEL
++static s32
++wl_cfg80211_set_auto_channel_scan_state(struct net_device *ndev)
++{
++	u32 val = 0;
++	s32 ret = BCME_ERROR;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(ndev);
++	/* Set interface up, explicitly. */
++	val = 1;
++
++	ret = wldev_ioctl_set(ndev, WLC_UP, (void *)&val, sizeof(val));
++	if (ret < 0) {
++		WL_ERR(("set interface up failed, error = %d\n", ret));
++		goto done;
++	}
++
++	/* Stop all scan explicitly, till auto channel selection complete. */
++	wl_set_drv_status(cfg, SCANNING, ndev);
++	if (cfg->escan_info.ndev == NULL) {
++		ret = BCME_OK;
++		goto done;
++	}
++	ret = wl_notify_escan_complete(cfg, ndev, true, true);
++	if (ret < 0) {
++		WL_ERR(("set scan abort failed, error = %d\n", ret));
++		ret = BCME_OK; // terence 20140115: fix escan_complete error
++		goto done;
++	}
++
++done:
++	return ret;
++}
++
++static bool
++wl_cfg80211_valid_channel_p2p(int channel)
++{
++	bool valid = false;
++
++	/* channel 1 to 14 */
++	if ((channel >= 1) && (channel <= 14)) {
++		valid = true;
++	}
++	/* channel 36 to 48 */
++	else if ((channel >= 36) && (channel <= 48)) {
++		valid = true;
++	}
++	/* channel 149 to 161 */
++	else if ((channel >= 149) && (channel <= 161)) {
++		valid = true;
++	}
++	else {
++		valid = false;
++		WL_INFORM(("invalid P2P chanspec, channel = %d\n", channel));
++	}
++
++	return valid;
++}
++
++s32
++wl_cfg80211_get_chanspecs_2g(struct net_device *ndev, void *buf, s32 buflen)
++{
++	s32 ret = BCME_ERROR;
++	struct bcm_cfg80211 *cfg = NULL;
++	chanspec_t chanspec = 0;
++
++	cfg = wl_get_cfg(ndev);
++
++	/* Restrict channels to 2.4GHz, 20MHz BW, no SB. */
++	chanspec |= (WL_CHANSPEC_BAND_2G | WL_CHANSPEC_BW_20 |
++		WL_CHANSPEC_CTL_SB_NONE);
++	chanspec = wl_chspec_host_to_driver(chanspec);
++
++	ret = wldev_iovar_getbuf_bsscfg(ndev, "chanspecs", (void *)&chanspec,
++		sizeof(chanspec), buf, buflen, 0, &cfg->ioctl_buf_sync);
++	if (ret < 0) {
++		WL_ERR(("get 'chanspecs' failed, error = %d\n", ret));
++	}
++
++	return ret;
++}
++
++s32
++wl_cfg80211_get_chanspecs_5g(struct net_device *ndev, void *buf, s32 buflen)
++{
++	u32 channel = 0;
++	s32 ret = BCME_ERROR;
++	s32 i = 0;
++	s32 j = 0;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(ndev);
++	wl_uint32_list_t *list = NULL;
++	chanspec_t chanspec = 0;
++
++	/* Restrict channels to 5GHz, 20MHz BW, no SB. */
++	chanspec |= (WL_CHANSPEC_BAND_5G | WL_CHANSPEC_BW_20 |
++		WL_CHANSPEC_CTL_SB_NONE);
++	chanspec = wl_chspec_host_to_driver(chanspec);
++
++	ret = wldev_iovar_getbuf_bsscfg(ndev, "chanspecs", (void *)&chanspec,
++		sizeof(chanspec), buf, buflen, 0, &cfg->ioctl_buf_sync);
++	if (ret < 0) {
++		WL_ERR(("get 'chanspecs' failed, error = %d\n", ret));
++		goto done;
++	}
++
++	list = (wl_uint32_list_t *)buf;
++	/* Skip DFS and inavlid P2P channel. */
++	for (i = 0, j = 0; i < dtoh32(list->count); i++) {
++		chanspec = (chanspec_t) dtoh32(list->element[i]);
++		channel = CHSPEC_CHANNEL(chanspec);
++
++		ret = wldev_iovar_getint(ndev, "per_chan_info", &channel);
++		if (ret < 0) {
++			WL_ERR(("get 'per_chan_info' failed, error = %d\n", ret));
++			goto done;
++		}
++
++		if (CHANNEL_IS_RADAR(channel) ||
++			!(wl_cfg80211_valid_channel_p2p(CHSPEC_CHANNEL(chanspec)))) {
++			continue;
++		} else {
++			list->element[j] = list->element[i];
++		}
++
++		j++;
++	}
++
++	list->count = j;
++
++done:
++	return ret;
++}
++
++static s32
++wl_cfg80211_get_best_channel(struct net_device *ndev, void *buf, int buflen,
++	int *channel)
++{
++	s32 ret = BCME_ERROR;
++	int chosen = 0;
++	int retry = 0;
++	uint chip;
++
++	/* Start auto channel selection scan. */
++	ret = wldev_ioctl_set(ndev, WLC_START_CHANNEL_SEL, buf, buflen);
++	if (ret < 0) {
++		WL_ERR(("can't start auto channel scan, error = %d\n", ret));
++		*channel = 0;
++		goto done;
++	}
++
++	/* Wait for auto channel selection, worst case possible delay is 5250ms. */
++	retry = CHAN_SEL_RETRY_COUNT;
++
++	while (retry--) {
++		OSL_SLEEP(CHAN_SEL_IOCTL_DELAY);
++		chosen = 0;
++		ret = wldev_ioctl_get(ndev, WLC_GET_CHANNEL_SEL, &chosen, sizeof(chosen));
++		if ((ret == 0) && (dtoh32(chosen) != 0)) {
++			chip = dhd_conf_get_chip(dhd_get_pub(ndev));
++			if (chip != BCM43362_CHIP_ID &&	chip != BCM4330_CHIP_ID &&
++					chip != BCM43143_CHIP_ID) {
++				u32 chanspec = 0;
++				int ctl_chan;
++				chanspec = wl_chspec_driver_to_host(chosen);
++				WL_INFORM(("selected chanspec = 0x%x\n", chanspec));
++				ctl_chan = wf_chspec_ctlchan(chanspec);
++				WL_INFORM(("selected ctl_chan = %d\n", ctl_chan));
++				*channel = (u16)(ctl_chan & 0x00FF);
++			} else
++				*channel = (u16)(chosen & 0x00FF);
++			WL_INFORM(("selected channel = %d\n", *channel));
++			break;
++		}
++		WL_INFORM(("attempt = %d, ret = %d, chosen = %d\n",
++			(CHAN_SEL_RETRY_COUNT - retry), ret, dtoh32(chosen)));
++	}
++
++	if (retry <= 0)	{
++		WL_ERR(("failure, auto channel selection timed out\n"));
++		*channel = 0;
++		ret = BCME_ERROR;
++	}
++	WL_INFORM(("selected channel = %d\n", *channel));
++
++done:
++	return ret;
++}
++
++static s32
++wl_cfg80211_restore_auto_channel_scan_state(struct net_device *ndev)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(ndev);
++	/* Clear scan stop driver status. */
++	wl_clr_drv_status(cfg, SCANNING, ndev);
++
++	return BCME_OK;
++}
++
++s32
++wl_cfg80211_get_best_channels(struct net_device *dev, char* cmd, int total_len)
++{
++	int channel = 0, band, band_cur;
++	s32 ret = BCME_ERROR;
++	u8 *buf = NULL;
++	char *pos = cmd;
++	struct bcm_cfg80211 *cfg = NULL;
++	struct net_device *ndev = NULL;
++
++	memset(cmd, 0, total_len);
++
++	buf = kmalloc(CHANSPEC_BUF_SIZE, GFP_KERNEL);
++	if (buf == NULL) {
++		WL_ERR(("failed to allocate chanspec buffer\n"));
++		return -ENOMEM;
++	}
++
++	/*
++	 * Always use primary interface, irrespective of interface on which
++	 * command came.
++	 */
++	cfg = wl_get_cfg(dev);
++	ndev = bcmcfg_to_prmry_ndev(cfg);
++
++	/*
++	 * Make sure that FW and driver are in right state to do auto channel
++	 * selection scan.
++	 */
++	ret = wl_cfg80211_set_auto_channel_scan_state(ndev);
++	if (ret < 0) {
++		WL_ERR(("can't set auto channel scan state, error = %d\n", ret));
++		goto done;
++	}
++
++	ret = wldev_ioctl(dev, WLC_GET_BAND, &band_cur, sizeof(band_cur), false);
++	if (band_cur != WLC_BAND_5G) {
++		/* Best channel selection in 2.4GHz band. */
++		ret = wl_cfg80211_get_chanspecs_2g(ndev, (void *)buf, CHANSPEC_BUF_SIZE);
++		if (ret < 0) {
++			WL_ERR(("can't get chanspecs in 2.4GHz, error = %d\n", ret));
++			goto done;
++		}
++
++		ret = wl_cfg80211_get_best_channel(ndev, (void *)buf, CHANSPEC_BUF_SIZE,
++			&channel);
++		if (ret < 0) {
++			WL_ERR(("can't select best channel scan in 2.4GHz, error = %d\n", ret));
++			goto done;
++		}
++
++		if (CHANNEL_IS_2G(channel)) {
++#if 0
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39) && !defined(WL_COMPAT_WIRELESS)
++			channel = ieee80211_channel_to_frequency(channel);
++#else
++			channel = ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ);
++#endif
++#endif
++		} else {
++			WL_ERR(("invalid 2.4GHz channel, channel = %d\n", channel));
++			channel = 0;
++		}
++		pos += snprintf(pos, total_len, "2g=%d ", channel);
++	}
++
++	if (band_cur != WLC_BAND_2G) {
++		// terence 20140120: fix for some chipsets only return 2.4GHz channel (4330b2/43341b0/4339a0)
++		band = band_cur==WLC_BAND_2G ? band_cur : WLC_BAND_5G;
++		ret = wldev_ioctl(dev, WLC_SET_BAND, &band, sizeof(band), true);
++		if (ret < 0) {
++			WL_ERR(("WLC_SET_BAND error %d\n", ret));
++			goto done;
++		}
++
++		/* Best channel selection in 5GHz band. */
++		ret = wl_cfg80211_get_chanspecs_5g(ndev, (void *)buf, CHANSPEC_BUF_SIZE);
++		if (ret < 0) {
++			WL_ERR(("can't get chanspecs in 5GHz, error = %d\n", ret));
++			goto done;
++		}
++
++		ret = wl_cfg80211_get_best_channel(ndev, (void *)buf, CHANSPEC_BUF_SIZE,
++			&channel);
++		if (ret < 0) {
++			WL_ERR(("can't select best channel scan in 5GHz, error = %d\n", ret));
++			goto done;
++		}
++
++		if (CHANNEL_IS_5G(channel)) {
++#if 0
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39) && !defined(WL_COMPAT_WIRELESS)
++			channel = ieee80211_channel_to_frequency(channel);
++#else
++			channel = ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ);
++#endif
++#endif
++		} else {
++			WL_ERR(("invalid 5GHz channel, channel = %d\n", channel));
++			channel = 0;
++		}
++
++		ret = wldev_ioctl(dev, WLC_SET_BAND, &band_cur, sizeof(band_cur), true);
++		if (ret < 0)
++			WL_ERR(("WLC_SET_BAND error %d\n", ret));
++		pos += snprintf(pos, total_len, "5g=%d ", channel);
++	}
++
++done:
++	if (NULL != buf) {
++		kfree(buf);
++	}
++
++	/* Restore FW and driver back to normal state. */
++	ret = wl_cfg80211_restore_auto_channel_scan_state(ndev);
++	if (ret < 0) {
++		WL_ERR(("can't restore auto channel scan state, error = %d\n", ret));
++	}
++
++	WL_MSG(ndev->name, "%s\n", cmd);
++
++	return (pos - cmd);
++}
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++
++static const struct rfkill_ops wl_rfkill_ops = {
++	.set_block = wl_rfkill_set
++};
++
++static int wl_rfkill_set(void *data, bool blocked)
++{
++	struct bcm_cfg80211 *cfg = (struct bcm_cfg80211 *)data;
++
++	WL_DBG(("Enter \n"));
++	WL_DBG(("RF %s\n", blocked ? "blocked" : "unblocked"));
++
++	if (!cfg)
++		return -EINVAL;
++
++	cfg->rf_blocked = blocked;
++
++	return 0;
++}
++
++static int wl_setup_rfkill(struct bcm_cfg80211 *cfg, bool setup)
++{
++	s32 err = 0;
++
++	WL_DBG(("Enter \n"));
++	if (!cfg)
++		return -EINVAL;
++	if (setup) {
++		cfg->rfkill = rfkill_alloc("brcmfmac-wifi",
++			wl_cfg80211_get_parent_dev(),
++			RFKILL_TYPE_WLAN, &wl_rfkill_ops, (void *)cfg);
++
++		if (!cfg->rfkill) {
++			err = -ENOMEM;
++			goto err_out;
++		}
++
++		err = rfkill_register(cfg->rfkill);
++
++		if (err)
++			rfkill_destroy(cfg->rfkill);
++	} else {
++		if (!cfg->rfkill) {
++			err = -ENOMEM;
++			goto err_out;
++		}
++
++		rfkill_unregister(cfg->rfkill);
++		rfkill_destroy(cfg->rfkill);
++	}
++
++err_out:
++	return err;
++}
++
++#ifdef DEBUGFS_CFG80211
++/**
++* Format : echo "SCAN:1 DBG:1" > /sys/kernel/debug/dhd/debug_level
++* to turn on SCAN and DBG log.
++* To turn off SCAN partially, echo "SCAN:0" > /sys/kernel/debug/dhd/debug_level
++* To see current setting of debug level,
++* cat /sys/kernel/debug/dhd/debug_level
++*/
++static ssize_t
++wl_debuglevel_write(struct file *file, const char __user *userbuf,
++	size_t count, loff_t *ppos)
++{
++	char tbuf[S_SUBLOGLEVEL * ARRAYSIZE(sublogname_map)], sublog[S_SUBLOGLEVEL];
++	char *params, *token, *colon;
++	uint i, tokens, log_on = 0;
++	size_t minsize = min_t(size_t, (sizeof(tbuf) - 1), count);
++
++	memset(tbuf, 0, sizeof(tbuf));
++	memset(sublog, 0, sizeof(sublog));
++	if (copy_from_user(&tbuf, userbuf, minsize)) {
++		return -EFAULT;
++	}
++
++	tbuf[minsize + 1] = '\0';
++	params = &tbuf[0];
++	colon = strchr(params, '\n');
++	if (colon != NULL)
++		*colon = '\0';
++	while ((token = strsep(&params, " ")) != NULL) {
++		memset(sublog, 0, sizeof(sublog));
++		if (token == NULL || !*token)
++			break;
++		if (*token == '\0')
++			continue;
++		colon = strchr(token, ':');
++		if (colon != NULL) {
++			*colon = ' ';
++		}
++		tokens = sscanf(token, "%s %u", sublog, &log_on);
++		if (colon != NULL)
++			*colon = ':';
++
++		if (tokens == 2) {
++				for (i = 0; i < ARRAYSIZE(sublogname_map); i++) {
++					if (!strncmp(sublog, sublogname_map[i].sublogname,
++						strlen(sublogname_map[i].sublogname))) {
++						if (log_on)
++							wl_dbg_level |=
++							(sublogname_map[i].log_level);
++						else
++							wl_dbg_level &=
++							~(sublogname_map[i].log_level);
++					}
++				}
++		} else
++			WL_ERR(("%s: can't parse '%s' as a "
++			       "SUBMODULE:LEVEL (%d tokens)\n",
++			       tbuf, token, tokens));
++
++
++	}
++	return count;
++}
++
++static ssize_t
++wl_debuglevel_read(struct file *file, char __user *user_buf,
++	size_t count, loff_t *ppos)
++{
++	char *param;
++	char tbuf[S_SUBLOGLEVEL * ARRAYSIZE(sublogname_map)];
++	uint i;
++	memset(tbuf, 0, sizeof(tbuf));
++	param = &tbuf[0];
++	for (i = 0; i < ARRAYSIZE(sublogname_map); i++) {
++		param += snprintf(param, sizeof(tbuf) - 1, "%s:%d ",
++			sublogname_map[i].sublogname,
++			(wl_dbg_level & sublogname_map[i].log_level) ? 1 : 0);
++	}
++	*param = '\n';
++	return simple_read_from_buffer(user_buf, count, ppos, tbuf, strlen(&tbuf[0]));
++
++}
++static const struct file_operations fops_debuglevel = {
++	.open = NULL,
++	.write = wl_debuglevel_write,
++	.read = wl_debuglevel_read,
++	.owner = THIS_MODULE,
++	.llseek = NULL,
++};
++
++static s32 wl_setup_debugfs(struct bcm_cfg80211 *cfg)
++{
++	s32 err = 0;
++	struct dentry *_dentry;
++	if (!cfg)
++		return -EINVAL;
++	cfg->debugfs = debugfs_create_dir(KBUILD_MODNAME, NULL);
++	if (!cfg->debugfs || IS_ERR(cfg->debugfs)) {
++		if (cfg->debugfs == ERR_PTR(-ENODEV))
++			WL_ERR(("Debugfs is not enabled on this kernel\n"));
++		else
++			WL_ERR(("Can not create debugfs directory\n"));
++		cfg->debugfs = NULL;
++		goto exit;
++
++	}
++	_dentry = debugfs_create_file("debug_level", S_IRUSR | S_IWUSR,
++		cfg->debugfs, cfg, &fops_debuglevel);
++	if (!_dentry || IS_ERR(_dentry)) {
++		WL_ERR(("failed to create debug_level debug file\n"));
++		wl_free_debugfs(cfg);
++	}
++exit:
++	return err;
++}
++static s32 wl_free_debugfs(struct bcm_cfg80211 *cfg)
++{
++	if (!cfg)
++		return -EINVAL;
++	if (cfg->debugfs)
++		debugfs_remove_recursive(cfg->debugfs);
++	cfg->debugfs = NULL;
++	return 0;
++}
++#endif /* DEBUGFS_CFG80211 */
++
++struct device *wl_cfg80211_get_parent_dev(void)
++{
++	return cfg80211_parent_dev;
++}
++
++void wl_cfg80211_set_parent_dev(void *dev)
++{
++	cfg80211_parent_dev = dev;
++}
++
++static void wl_cfg80211_clear_parent_dev(void)
++{
++	cfg80211_parent_dev = NULL;
++}
++
++void get_primary_mac(struct bcm_cfg80211 *cfg, struct ether_addr *mac)
++{
++	if (wldev_iovar_getbuf_bsscfg(bcmcfg_to_prmry_ndev(cfg), "cur_etheraddr", NULL,
++		0, cfg->ioctl_buf, WLC_IOCTL_SMLEN, 0, &cfg->ioctl_buf_sync) == BCME_OK) {
++		memcpy(mac->octet, cfg->ioctl_buf, ETHER_ADDR_LEN);
++	} else {
++		memset(mac->octet, 0, ETHER_ADDR_LEN);
++	}
++}
++static bool check_dev_role_integrity(struct bcm_cfg80211 *cfg, u32 dev_role)
++{
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++	if (((dev_role == NL80211_IFTYPE_AP) &&
++		!(dhd->op_mode & DHD_FLAG_HOSTAP_MODE)) ||
++		((dev_role == NL80211_IFTYPE_P2P_GO) &&
++		!(dhd->op_mode & DHD_FLAG_P2P_GO_MODE)))
++	{
++		WL_ERR(("device role select failed role:%d op_mode:%d \n", dev_role, dhd->op_mode));
++		return false;
++	}
++	return true;
++}
++
++int wl_cfg80211_do_driver_init(struct net_device *net)
++{
++	struct bcm_cfg80211 *cfg = *(struct bcm_cfg80211 **)netdev_priv(net);
++
++	if (!cfg || !cfg->wdev)
++		return -EINVAL;
++
++	if (dhd_do_driver_init(cfg->wdev->netdev) < 0)
++		return -1;
++
++	return 0;
++}
++
++void wl_cfg80211_enable_trace(u32 level)
++{
++	wl_dbg_level = level;
++	WL_MSG("wlan", "wl_dbg_level = 0x%x\n", wl_dbg_level);
++}
++
++#if defined(WL_SUPPORT_BACKPORTED_KPATCHES) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, \
++	2, 0))
++static s32
++wl_cfg80211_mgmt_tx_cancel_wait(struct wiphy *wiphy,
++	bcm_struct_cfgdev *cfgdev, u64 cookie)
++{
++	/* CFG80211 checks for tx_cancel_wait callback when ATTR_DURATION
++	 * is passed with CMD_FRAME. This callback is supposed to cancel
++	 * the OFFCHANNEL Wait. Since we are already taking care of that
++	 *  with the tx_mgmt logic, do nothing here.
++	 */
++
++	return 0;
++}
++#endif /* WL_SUPPORT_BACKPORTED_PATCHES || KERNEL >= 3.2.0 */
++
++#ifdef WL11U
++static bcm_tlv_t *
++wl_cfg80211_find_interworking_ie(const u8 *parse, u32 len)
++{
++	bcm_tlv_t *ie;
++
++/* unfortunately it's too much work to dispose the const cast - bcm_parse_tlvs
++ * is used everywhere and changing its prototype to take const qualifier needs
++ * a massive change to all its callers...
++ */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++	if ((ie = bcm_parse_tlvs((void *)parse, (int)len, DOT11_MNG_INTERWORKING_ID))) {
++		return ie;
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	return NULL;
++}
++
++static s32
++wl_cfg80211_clear_iw_ie(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 bssidx)
++{
++	ie_setbuf_t ie_setbuf;
++
++	WL_DBG(("clear interworking IE\n"));
++
++	memset(&ie_setbuf, 0, sizeof(ie_setbuf_t));
++
++	ie_setbuf.ie_buffer.iecount = htod32(1);
++	ie_setbuf.ie_buffer.ie_list[0].ie_data.id = DOT11_MNG_INTERWORKING_ID;
++	ie_setbuf.ie_buffer.ie_list[0].ie_data.len = 0;
++
++	return wldev_iovar_setbuf_bsscfg(ndev, "ie", &ie_setbuf, sizeof(ie_setbuf),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++}
++
++static s32
++wl_cfg80211_add_iw_ie(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 bssidx, s32 pktflag,
++            uint8 ie_id, uint8 *data, uint8 data_len)
++{
++	s32 err = BCME_OK;
++	s32 buf_len;
++	ie_setbuf_t *ie_setbuf;
++	ie_getbuf_t ie_getbufp;
++	char getbuf[WLC_IOCTL_SMLEN];
++
++	if (ie_id != DOT11_MNG_INTERWORKING_ID) {
++		WL_ERR(("unsupported (id=%d)\n", ie_id));
++		return BCME_UNSUPPORTED;
++	}
++
++	/* access network options (1 octet)  is the mandatory field */
++	if (!data || data_len == 0 || data_len > IW_IES_MAX_BUF_LEN) {
++		WL_ERR(("wrong interworking IE (len=%d)\n", data_len));
++		return BCME_BADARG;
++	}
++
++	/* Validate the pktflag parameter */
++	if ((pktflag & ~(VNDR_IE_BEACON_FLAG | VNDR_IE_PRBRSP_FLAG |
++			VNDR_IE_ASSOCRSP_FLAG | VNDR_IE_AUTHRSP_FLAG |
++			VNDR_IE_PRBREQ_FLAG | VNDR_IE_ASSOCREQ_FLAG|
++			VNDR_IE_CUSTOM_FLAG))) {
++		WL_ERR(("invalid packet flag 0x%x\n", pktflag));
++		return BCME_BADARG;
++	}
++
++	buf_len = sizeof(ie_setbuf_t) + data_len - 1;
++
++	ie_getbufp.id = DOT11_MNG_INTERWORKING_ID;
++	if (wldev_iovar_getbuf_bsscfg(ndev, "ie", (void *)&ie_getbufp,
++			sizeof(ie_getbufp), getbuf, WLC_IOCTL_SMLEN, bssidx, &cfg->ioctl_buf_sync)
++			== BCME_OK) {
++		if (!memcmp(&getbuf[TLV_HDR_LEN], data, data_len)) {
++			WL_DBG(("skip to set interworking IE\n"));
++			return BCME_OK;
++		}
++	}
++
++	/* if already set with previous values, delete it first */
++	if (cfg->wl11u) {
++		if ((err = wl_cfg80211_clear_iw_ie(cfg, ndev, bssidx)) != BCME_OK) {
++			return err;
++		}
++	}
++
++	ie_setbuf = (ie_setbuf_t *) kzalloc(buf_len, GFP_KERNEL);
++	if (!ie_setbuf) {
++		WL_ERR(("Error allocating buffer for IE\n"));
++		return -ENOMEM;
++	}
++	strncpy(ie_setbuf->cmd, "add", sizeof(ie_setbuf->cmd));
++	ie_setbuf->cmd[sizeof(ie_setbuf->cmd) - 1] = '\0';
++
++	/* Buffer contains only 1 IE */
++	ie_setbuf->ie_buffer.iecount = htod32(1);
++	/* use VNDR_IE_CUSTOM_FLAG flags for none vendor IE . currently fixed value */
++	ie_setbuf->ie_buffer.ie_list[0].pktflag = htod32(pktflag);
++
++	/* Now, add the IE to the buffer */
++	ie_setbuf->ie_buffer.ie_list[0].ie_data.id = DOT11_MNG_INTERWORKING_ID;
++	ie_setbuf->ie_buffer.ie_list[0].ie_data.len = data_len;
++	memcpy((uchar *)&ie_setbuf->ie_buffer.ie_list[0].ie_data.data[0], data, data_len);
++
++	if ((err = wldev_iovar_setbuf_bsscfg(ndev, "ie", ie_setbuf, buf_len,
++			cfg->ioctl_buf, WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync))
++			== BCME_OK) {
++		WL_DBG(("set interworking IE\n"));
++		cfg->wl11u = TRUE;
++		err = wldev_iovar_setint_bsscfg(ndev, "grat_arp", 1, bssidx);
++	}
++
++	kfree(ie_setbuf);
++	return err;
++}
++#endif /* WL11U */
++
++
++s32
++wl_cfg80211_set_if_band(struct net_device *ndev, int band)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(ndev);
++	int ret = 0, wait_cnt;
++	char ioctl_buf[32];
++
++	if ((band < WLC_BAND_AUTO) || (band > WLC_BAND_2G)) {
++		WL_ERR(("Invalid band\n"));
++		return -EINVAL;
++	}
++	if (wl_get_drv_status(cfg, CONNECTED, ndev) ||
++			wl_get_drv_status(cfg, CONNECTING, ndev)) {
++		/* if driver is connected or connecting status, try to disconnect first.
++		* if dongle is associated, iovar 'if_band' would be rejected.
++		*/
++		wl_set_drv_status(cfg, DISCONNECTING, ndev);
++		ret = wldev_ioctl_set(ndev, WLC_DISASSOC, NULL, 0);
++		if (ret < 0) {
++			WL_ERR(("WLC_DISASSOC error %d\n", ret));
++			/* continue to set 'if_band' */
++		}
++		else {
++			/* This is to ensure that 'if_band' iovar is issued only after
++			* disconnection is completed
++			*/
++			wait_cnt = WAIT_FOR_DISCONNECT_MAX;
++			while (wl_get_drv_status(cfg, DISCONNECTING, ndev) && wait_cnt) {
++				WL_DBG(("Wait until disconnected. wait_cnt: %d\n", wait_cnt));
++				wait_cnt--;
++				OSL_SLEEP(10);
++			}
++		}
++	}
++	if ((ret = wldev_iovar_setbuf(ndev, "if_band", &band,
++			sizeof(int), ioctl_buf, sizeof(ioctl_buf), NULL)) < 0) {
++		WL_ERR(("seting if_band failed ret=%d\n", ret));
++		/* issue 'WLC_SET_BAND' if if_band is not supported */
++		if (ret == BCME_UNSUPPORTED) {
++			ret = wldev_set_band(ndev, band);
++			if (ret < 0) {
++				WL_ERR(("seting band failed ret=%d\n", ret));
++			}
++		}
++	}
++	return ret;
++}
++
++s32
++wl_cfg80211_dfs_ap_move(struct net_device *ndev, char *data, char *command, int total_len)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(ndev);
++	char ioctl_buf[50];
++	int err = 0;
++	uint32 val = 0;
++	chanspec_t chanspec = 0;
++	int abort;
++	int bytes_written = 0;
++	wl_dfs_ap_move_status_t *status;
++	char chanbuf[CHANSPEC_STR_LEN];
++	const char *dfs_state_str[DFS_SCAN_S_MAX] = {
++		"Radar Free On Channel",
++		"Radar Found On Channel",
++		"Radar Scan In Progress",
++		"Radar Scan Aborted",
++		"RSDB Mode switch in Progress For Scan"
++	};
++	if (ndev->ieee80211_ptr->iftype != NL80211_IFTYPE_AP) {
++		bytes_written = snprintf(command, total_len, "AP is not up\n");
++		return bytes_written;
++	}
++	if (!*data) {
++		if ((err = wldev_iovar_getbuf(ndev, "dfs_ap_move", NULL, 0,
++				cfg->ioctl_buf, WLC_IOCTL_MAXLEN,  &cfg->ioctl_buf_sync))) {
++			WL_ERR(("setting dfs_ap_move failed with err=%d \n", err));
++			return err;
++		}
++		status = (wl_dfs_ap_move_status_t *)cfg->ioctl_buf;
++
++		if (status->version != WL_DFS_AP_MOVE_VERSION) {
++			err = BCME_UNSUPPORTED;
++			WL_ERR(("err=%d version=%d\n", err, status->version));
++			return err;
++		}
++
++		if (status->move_status != (int8) DFS_SCAN_S_IDLE) {
++			chanspec = wl_chspec_driver_to_host(status->chanspec);
++			if (chanspec != 0 && chanspec != INVCHANSPEC) {
++				wf_chspec_ntoa(chanspec, chanbuf);
++				bytes_written = snprintf(command, total_len,
++					"AP Target Chanspec %s (0x%x)\n", chanbuf, chanspec);
++
++			}
++			bytes_written += snprintf(command + bytes_written, total_len,
++					 "%s\n", dfs_state_str[status->move_status]);
++			return bytes_written;
++		} else {
++			bytes_written = snprintf(command, total_len, "dfs AP move in IDLE state\n");
++			return bytes_written;
++		}
++
++	}
++
++	abort = bcm_atoi(data);
++	if (abort == -1) {
++		if ((err = wldev_iovar_setbuf(ndev, "dfs_ap_move", &abort,
++				sizeof(int), ioctl_buf, sizeof(ioctl_buf), NULL)) < 0) {
++			WL_ERR(("seting dfs_ap_move failed with err %d\n", err));
++			return err;
++		}
++	} else {
++		chanspec = wf_chspec_aton(data);
++		if (chanspec != 0) {
++			val = wl_chspec_host_to_driver(chanspec);
++			if (val != INVCHANSPEC) {
++				if ((err = wldev_iovar_setbuf(ndev, "dfs_ap_move", &val,
++					sizeof(int), ioctl_buf, sizeof(ioctl_buf), NULL)) < 0) {
++					WL_ERR(("seting dfs_ap_move failed with err %d\n", err));
++					return err;
++				}
++				WL_DBG((" set dfs_ap_move successfull"));
++			} else {
++				err = BCME_USAGE_ERROR;
++			}
++		}
++	}
++	return err;
++}
++
++#ifdef WBTEXT
++s32
++wl_cfg80211_wbtext_set_default(struct net_device *ndev)
++{
++	char commandp[WLC_IOCTL_SMLEN];
++	s32 ret = BCME_OK;
++	char *data;
++
++	WL_DBG(("set wbtext to default\n"));
++
++	/* set roam profile */
++	memset(commandp, 0, sizeof(commandp));
++	snprintf(commandp, WLC_IOCTL_SMLEN, "%s %s",
++		CMD_WBTEXT_PROFILE_CONFIG, DEFAULT_WBTEXT_PROFILE_A);
++	data = (commandp + strlen(CMD_WBTEXT_PROFILE_CONFIG) + 1);
++	ret = wl_cfg80211_wbtext_config(ndev, data, commandp, WLC_IOCTL_SMLEN);
++	if (ret != BCME_OK) {
++		WL_ERR(("%s: Failed to set roam_prof %s error = %d\n",
++			__FUNCTION__, data, ret));
++		return ret;
++	}
++
++	memset(commandp, 0, sizeof(commandp));
++	snprintf(commandp, WLC_IOCTL_SMLEN, "%s %s",
++		CMD_WBTEXT_PROFILE_CONFIG, DEFAULT_WBTEXT_PROFILE_B);
++	data = (commandp + strlen(CMD_WBTEXT_PROFILE_CONFIG) + 1);
++	ret = wl_cfg80211_wbtext_config(ndev, data, commandp, WLC_IOCTL_SMLEN);
++	if (ret != BCME_OK) {
++		WL_ERR(("%s: Failed to set roam_prof %s error = %d\n",
++			__FUNCTION__, data, ret));
++		return ret;
++	}
++
++	/* set RSSI weight */
++	memset(commandp, 0, sizeof(commandp));
++	snprintf(commandp, WLC_IOCTL_SMLEN, "%s %s",
++		CMD_WBTEXT_WEIGHT_CONFIG, DEFAULT_WBTEXT_WEIGHT_RSSI_A);
++	data = (commandp + strlen(CMD_WBTEXT_WEIGHT_CONFIG) + 1);
++	ret = wl_cfg80211_wbtext_weight_config(ndev, data, commandp, WLC_IOCTL_SMLEN);
++	if (ret != BCME_OK) {
++		WL_ERR(("%s: Failed to set weight config %s error = %d\n",
++			__FUNCTION__, data, ret));
++		return ret;
++	}
++
++	memset(commandp, 0, sizeof(commandp));
++	snprintf(commandp, WLC_IOCTL_SMLEN, "%s %s",
++		CMD_WBTEXT_WEIGHT_CONFIG, DEFAULT_WBTEXT_WEIGHT_RSSI_B);
++	data = (commandp + strlen(CMD_WBTEXT_WEIGHT_CONFIG) + 1);
++	ret = wl_cfg80211_wbtext_weight_config(ndev, data, commandp, WLC_IOCTL_SMLEN);
++	if (ret != BCME_OK) {
++		WL_ERR(("%s: Failed to set weight config %s error = %d\n",
++			__FUNCTION__, data, ret));
++		return ret;
++	}
++
++	/* set CU weight */
++	memset(commandp, 0, sizeof(commandp));
++	snprintf(commandp, WLC_IOCTL_SMLEN, "%s %s",
++		CMD_WBTEXT_WEIGHT_CONFIG, DEFAULT_WBTEXT_WEIGHT_CU_A);
++	data = (commandp + strlen(CMD_WBTEXT_WEIGHT_CONFIG) + 1);
++	ret = wl_cfg80211_wbtext_weight_config(ndev, data, commandp, WLC_IOCTL_SMLEN);
++	if (ret != BCME_OK) {
++		WL_ERR(("%s: Failed to set weight config %s error = %d\n",
++			__FUNCTION__, data, ret));
++		return ret;
++	}
++
++	memset(commandp, 0, sizeof(commandp));
++	snprintf(commandp, WLC_IOCTL_SMLEN, "%s %s",
++		CMD_WBTEXT_WEIGHT_CONFIG, DEFAULT_WBTEXT_WEIGHT_CU_B);
++	data = (commandp + strlen(CMD_WBTEXT_WEIGHT_CONFIG) + 1);
++	ret = wl_cfg80211_wbtext_weight_config(ndev, data, commandp, WLC_IOCTL_SMLEN);
++	if (ret != BCME_OK) {
++		WL_ERR(("%s: Failed to set weight config %s error = %d\n",
++			__FUNCTION__, data, ret));
++		return ret;
++	}
++
++	/* set RSSI table */
++	memset(commandp, 0, sizeof(commandp));
++	snprintf(commandp, WLC_IOCTL_SMLEN, "%s %s",
++		CMD_WBTEXT_TABLE_CONFIG, DEFAULT_WBTEXT_TABLE_RSSI_A);
++	data = (commandp + strlen(CMD_WBTEXT_TABLE_CONFIG) + 1);
++	ret = wl_cfg80211_wbtext_table_config(ndev, data, commandp, WLC_IOCTL_SMLEN);
++	if (ret != BCME_OK) {
++		WL_ERR(("%s: Failed to set RSSI table %s error = %d\n",
++			__FUNCTION__, data, ret));
++		return ret;
++	}
++
++	memset(commandp, 0, sizeof(commandp));
++	snprintf(commandp, WLC_IOCTL_SMLEN, "%s %s",
++		CMD_WBTEXT_TABLE_CONFIG, DEFAULT_WBTEXT_TABLE_RSSI_B);
++	data = (commandp + strlen(CMD_WBTEXT_TABLE_CONFIG) + 1);
++	ret = wl_cfg80211_wbtext_table_config(ndev, data, commandp, WLC_IOCTL_SMLEN);
++	if (ret != BCME_OK) {
++		WL_ERR(("%s: Failed to set RSSI table %s error = %d\n",
++			__FUNCTION__, data, ret));
++		return ret;
++	}
++
++	/* set CU table */
++	memset(commandp, 0, sizeof(commandp));
++	snprintf(commandp, WLC_IOCTL_SMLEN, "%s %s",
++		CMD_WBTEXT_TABLE_CONFIG, DEFAULT_WBTEXT_TABLE_CU_A);
++	data = (commandp + strlen(CMD_WBTEXT_TABLE_CONFIG) + 1);
++	ret = wl_cfg80211_wbtext_table_config(ndev, data, commandp, WLC_IOCTL_SMLEN);
++	if (ret != BCME_OK) {
++		WL_ERR(("%s: Failed to set CU table %s error = %d\n",
++			__FUNCTION__, data, ret));
++		return ret;
++	}
++
++	memset(commandp, 0, sizeof(commandp));
++	snprintf(commandp, WLC_IOCTL_SMLEN, "%s %s",
++		CMD_WBTEXT_TABLE_CONFIG, DEFAULT_WBTEXT_TABLE_CU_B);
++	data = (commandp + strlen(CMD_WBTEXT_TABLE_CONFIG) + 1);
++	ret = wl_cfg80211_wbtext_table_config(ndev, data, commandp, WLC_IOCTL_SMLEN);
++	if (ret != BCME_OK) {
++		WL_ERR(("%s: Failed to set CU table %s error = %d\n",
++			__FUNCTION__, data, ret));
++		return ret;
++	}
++
++	return ret;
++}
++
++s32
++wl_cfg80211_wbtext_config(struct net_device *ndev, char *data, char *command, int total_len)
++{
++	uint i = 0;
++	long int rssi_lower, roam_trigger;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(ndev);
++	wl_roam_prof_band_t *rp;
++	int err = -EINVAL, bytes_written = 0;
++	size_t len = strlen(data);
++	int rp_len = 0;
++	data[len] = '\0';
++	rp = (wl_roam_prof_band_t *) kzalloc(sizeof(*rp)
++			* WL_MAX_ROAM_PROF_BRACKETS, GFP_KERNEL);
++	if (unlikely(!rp)) {
++		WL_ERR(("%s: failed to allocate memory\n", __func__));
++		err =  -ENOMEM;
++		goto exit;
++	}
++	rp->ver = WL_MAX_ROAM_PROF_VER;
++	if (*data && (!strncmp(data, "b", 1))) {
++		rp->band = WLC_BAND_2G;
++	} else if (*data && (!strncmp(data, "a", 1))) {
++		rp->band = WLC_BAND_5G;
++	} else {
++		err = snprintf(command, total_len, "Missing band\n");
++		goto exit;
++	}
++	data++;
++	rp->len = 0;
++	/* Getting roam profile  from fw */
++	if ((err = wldev_iovar_getbuf(ndev, "roam_prof", rp, sizeof(*rp),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN,  &cfg->ioctl_buf_sync))) {
++		WL_ERR(("Getting roam_profile failed with err=%d \n", err));
++		goto exit;
++	}
++	memcpy(rp, cfg->ioctl_buf, sizeof(*rp) * WL_MAX_ROAM_PROF_BRACKETS);
++	/* roam_prof version get */
++	if (rp->ver != WL_MAX_ROAM_PROF_VER) {
++		WL_ERR(("bad version (=%d) in return data\n", rp->ver));
++		err = -EINVAL;
++		goto exit;
++	}
++	if ((rp->len % sizeof(wl_roam_prof_t)) != 0) {
++		WL_ERR(("bad length (=%d) in return data\n", rp->len));
++		err = -EINVAL;
++		goto exit;
++	}
++
++	if (!*data) {
++		for (i = 0; i < WL_MAX_ROAM_PROF_BRACKETS; i++) {
++			/* printing contents of roam profile data from fw and exits
++			 * if code hits any of one of the below condtion. If remaining
++			 * length of buffer is less than roam profile size or
++			 * if there is no valid entry.
++			 */
++			if (((i * sizeof(wl_roam_prof_t)) > rp->len) ||
++				(rp->roam_prof[i].fullscan_period == 0)) {
++				break;
++			}
++			bytes_written += snprintf(command+bytes_written,
++					total_len, "RSSI[%d,%d] CU(trigger:%d%%: duration:%ds)\n",
++					rp->roam_prof[i].roam_trigger, rp->roam_prof[i].rssi_lower,
++					rp->roam_prof[i].channel_usage,
++					rp->roam_prof[i].cu_avg_calc_dur);
++		}
++		err = bytes_written;
++		goto exit;
++	} else {
++		for (i = 0; i < WL_MAX_ROAM_PROF_BRACKETS; i++) {
++			/* reading contents of roam profile data from fw and exits
++			 * if code hits any of one of the below condtion, If remaining
++			 * length of buffer is less than roam profile size or if there
++			 * is no valid entry.
++			 */
++			if (((i * sizeof(wl_roam_prof_t)) > rp->len) ||
++				(rp->roam_prof[i].fullscan_period == 0)) {
++				break;
++			}
++		}
++		/* Do not set roam_prof from upper layer if fw doesn't have 2 rows */
++		if (i != 2) {
++			WL_ERR(("FW must have 2 rows to fill roam_prof\n"));
++			err = -EINVAL;
++			goto exit;
++		}
++		/* setting roam profile to fw */
++		data++;
++		for (i = 0; i < WL_MAX_ROAM_PROF_BRACKETS; i++) {
++			roam_trigger = simple_strtol(data, &data, 10);
++			if (roam_trigger >= 0) {
++				WL_ERR(("roam trigger[%d] value must be negative\n", i));
++				err = -EINVAL;
++				goto exit;
++			}
++			rp->roam_prof[i].roam_trigger = roam_trigger;
++			data++;
++			rssi_lower = simple_strtol(data, &data, 10);
++			if (rssi_lower >= 0) {
++				WL_ERR(("rssi lower[%d] value must be negative\n", i));
++				err = -EINVAL;
++				goto exit;
++			}
++			rp->roam_prof[i].rssi_lower = rssi_lower;
++			data++;
++			rp->roam_prof[i].channel_usage = simple_strtol(data, &data, 10);
++			data++;
++			rp->roam_prof[i].cu_avg_calc_dur = simple_strtol(data, &data, 10);
++
++			rp_len += sizeof(wl_roam_prof_t);
++
++			if (*data == '\0') {
++				break;
++			}
++			data++;
++		}
++		if (i != 1) {
++			WL_ERR(("Only two roam_prof rows supported.\n"));
++			err = -EINVAL;
++			goto exit;
++		}
++		rp->len = rp_len;
++		if ((err = wldev_iovar_setbuf(ndev, "roam_prof", rp,
++				sizeof(*rp), cfg->ioctl_buf, WLC_IOCTL_MEDLEN,
++				&cfg->ioctl_buf_sync)) < 0) {
++			WL_ERR(("seting roam_profile failed with err %d\n", err));
++		}
++	}
++exit:
++	if (rp) {
++		kfree(rp);
++	}
++	return err;
++}
++
++#define BUFSZ 5
++
++#define _S(x) #x
++#define S(x) _S(x)
++
++int wl_cfg80211_wbtext_weight_config(struct net_device *ndev, char *data,
++		char *command, int total_len)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(ndev);
++	int bytes_written = 0, err = -EINVAL, argc = 0;
++	char rssi[BUFSZ], band[BUFSZ], weight[BUFSZ];
++	char *endptr = NULL;
++	wnm_bss_select_weight_cfg_t *bwcfg;
++
++	bwcfg = kzalloc(sizeof(*bwcfg), GFP_KERNEL);
++	if (unlikely(!bwcfg)) {
++		WL_ERR(("%s: failed to allocate memory\n", __func__));
++		err = -ENOMEM;
++		goto exit;
++	}
++	bwcfg->version =  WNM_BSSLOAD_MONITOR_VERSION;
++	bwcfg->type = 0;
++	bwcfg->weight = 0;
++
++	argc = sscanf(data, "%"S(BUFSZ)"s %"S(BUFSZ)"s %"S(BUFSZ)"s", rssi, band, weight);
++
++	if (!strcasecmp(rssi, "rssi"))
++		bwcfg->type = WNM_BSS_SELECT_TYPE_RSSI;
++	else if (!strcasecmp(rssi, "cu"))
++		bwcfg->type = WNM_BSS_SELECT_TYPE_CU;
++	else {
++		/* Usage DRIVER WBTEXT_WEIGHT_CONFIG <rssi/cu> <band> <weight> */
++		WL_ERR(("%s: Command usage error\n", __func__));
++		goto exit;
++	}
++
++	if (!strcasecmp(band, "a"))
++		bwcfg->band = WLC_BAND_5G;
++	else if (!strcasecmp(band, "b"))
++		bwcfg->band = WLC_BAND_2G;
++	else if (!strcasecmp(band, "all"))
++		bwcfg->band = WLC_BAND_ALL;
++	else {
++		WL_ERR(("%s: Command usage error\n", __func__));
++		goto exit;
++	}
++
++	if (argc == 2) {
++		/* If there is no data after band, getting wnm_bss_select_weight from fw */
++		if (bwcfg->band == WLC_BAND_ALL) {
++			WL_ERR(("band option \"all\" is for set only, not get\n"));
++			goto exit;
++		}
++		if ((err = wldev_iovar_getbuf(ndev, "wnm_bss_select_weight", bwcfg,
++				sizeof(*bwcfg),
++				cfg->ioctl_buf, WLC_IOCTL_MAXLEN,  &cfg->ioctl_buf_sync))) {
++			WL_ERR(("Getting wnm_bss_select_weight failed with err=%d \n", err));
++			goto exit;
++		}
++		memcpy(bwcfg, cfg->ioctl_buf, sizeof(*bwcfg));
++		bytes_written = snprintf(command, total_len, "%s %s weight = %d\n",
++			(bwcfg->type == WNM_BSS_SELECT_TYPE_RSSI) ? "RSSI" : "CU",
++			(bwcfg->band == WLC_BAND_2G) ? "2G" : "5G", bwcfg->weight);
++		err = bytes_written;
++		goto exit;
++	} else {
++		/* if weight is non integer returns command usage error */
++		bwcfg->weight = simple_strtol(weight, &endptr, 0);
++		if (*endptr != '\0') {
++			WL_ERR(("%s: Command usage error", __func__));
++			goto exit;
++		}
++		/* setting weight for iovar wnm_bss_select_weight to fw */
++		if ((err = wldev_iovar_setbuf(ndev, "wnm_bss_select_weight", bwcfg,
++				sizeof(*bwcfg),
++				cfg->ioctl_buf, WLC_IOCTL_MAXLEN,  &cfg->ioctl_buf_sync))) {
++			WL_ERR(("Getting wnm_bss_select_weight failed with err=%d\n", err));
++		}
++	}
++exit:
++	if (bwcfg) {
++		kfree(bwcfg);
++	}
++	return err;
++}
++
++/* WBTEXT_TUPLE_MIN_LEN_CHECK :strlen(low)+" "+strlen(high)+" "+strlen(factor) */
++#define WBTEXT_TUPLE_MIN_LEN_CHECK 5
++
++int wl_cfg80211_wbtext_table_config(struct net_device *ndev, char *data,
++	char *command, int total_len)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(ndev);
++	int bytes_written = 0, err = -EINVAL;
++	char rssi[BUFSZ], band[BUFSZ];
++	int btcfg_len = 0, i = 0, parsed_len = 0;
++	wnm_bss_select_factor_cfg_t *btcfg;
++	size_t slen = strlen(data);
++	char *start_addr = NULL;
++	data[slen] = '\0';
++
++	btcfg = kzalloc((sizeof(*btcfg) + sizeof(*btcfg) *
++			WL_FACTOR_TABLE_MAX_LIMIT), GFP_KERNEL);
++	if (unlikely(!btcfg)) {
++		WL_ERR(("%s: failed to allocate memory\n", __func__));
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	btcfg->version = WNM_BSS_SELECT_FACTOR_VERSION;
++	btcfg->band = WLC_BAND_AUTO;
++	btcfg->type = 0;
++	btcfg->count = 0;
++
++	sscanf(data, "%"S(BUFSZ)"s %"S(BUFSZ)"s", rssi, band);
++
++	if (!strcasecmp(rssi, "rssi")) {
++		btcfg->type = WNM_BSS_SELECT_TYPE_RSSI;
++	}
++	else if (!strcasecmp(rssi, "cu")) {
++		btcfg->type = WNM_BSS_SELECT_TYPE_CU;
++	}
++	else {
++		WL_ERR(("%s: Command usage error\n", __func__));
++		goto exit;
++	}
++
++	if (!strcasecmp(band, "a")) {
++		btcfg->band = WLC_BAND_5G;
++	}
++	else if (!strcasecmp(band, "b")) {
++		btcfg->band = WLC_BAND_2G;
++	}
++	else if (!strcasecmp(band, "all")) {
++		btcfg->band = WLC_BAND_ALL;
++	}
++	else {
++		WL_ERR(("%s: Command usage, Wrong band\n", __func__));
++		goto exit;
++	}
++
++	if ((slen - 1) == (strlen(rssi) + strlen(band))) {
++		/* Getting factor table using iovar 'wnm_bss_select_table' from fw */
++		if ((err = wldev_iovar_getbuf(ndev, "wnm_bss_select_table", btcfg,
++				sizeof(*btcfg),
++				cfg->ioctl_buf, WLC_IOCTL_MAXLEN,  &cfg->ioctl_buf_sync))) {
++			WL_ERR(("Getting wnm_bss_select_table failed with err=%d \n", err));
++			goto exit;
++		}
++		memcpy(btcfg, cfg->ioctl_buf, sizeof(*btcfg));
++		memcpy(btcfg, cfg->ioctl_buf, (btcfg->count+1) * sizeof(*btcfg));
++
++		bytes_written += snprintf(command + bytes_written, total_len,
++					"No of entries in table: %d\n", btcfg->count);
++		bytes_written += snprintf(command + bytes_written, total_len, "%s factor table\n",
++				(btcfg->type == WNM_BSS_SELECT_TYPE_RSSI) ? "RSSI" : "CU");
++		bytes_written += snprintf(command + bytes_written, total_len,
++					"low\thigh\tfactor\n");
++		for (i = 0; i <= btcfg->count-1; i++) {
++			bytes_written += snprintf(command + bytes_written, total_len,
++				"%d\t%d\t%d\n", btcfg->params[i].low, btcfg->params[i].high,
++				btcfg->params[i].factor);
++		}
++		err = bytes_written;
++		goto exit;
++	} else {
++		memset(btcfg->params, 0, sizeof(wnm_bss_select_factor_params_t)
++				* WL_FACTOR_TABLE_MAX_LIMIT);
++		data += (strlen(rssi) + strlen(band) + 2);
++		start_addr = data;
++		slen = slen - (strlen(rssi) + strlen(band) + 2);
++		for (i = 0; i < WL_FACTOR_TABLE_MAX_LIMIT; i++) {
++			if (parsed_len + WBTEXT_TUPLE_MIN_LEN_CHECK <= slen) {
++				btcfg->params[i].low = simple_strtol(data, &data, 10);
++				data++;
++				btcfg->params[i].high = simple_strtol(data, &data, 10);
++				data++;
++				btcfg->params[i].factor = simple_strtol(data, &data, 10);
++				btcfg->count++;
++				if (*data == '\0') {
++					break;
++				}
++				data++;
++				parsed_len = data - start_addr;
++			} else {
++				WL_ERR(("%s:Command usage:less no of args\n", __func__));
++				goto exit;
++			}
++		}
++		btcfg_len = sizeof(*btcfg) + ((btcfg->count) * sizeof(*btcfg));
++		if ((err = wldev_iovar_setbuf(ndev, "wnm_bss_select_table", btcfg, btcfg_len,
++				cfg->ioctl_buf, WLC_IOCTL_MEDLEN, &cfg->ioctl_buf_sync)) < 0) {
++			WL_ERR(("seting wnm_bss_select_table failed with err %d\n", err));
++			goto exit;
++		}
++	}
++exit:
++	if (btcfg) {
++		kfree(btcfg);
++	}
++	return err;
++}
++
++s32
++wl_cfg80211_wbtext_delta_config(struct net_device *ndev, char *data, char *command, int total_len)
++{
++	uint i = 0;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(ndev);
++	int err = -EINVAL, bytes_written = 0, argc = 0, val, len = 0;
++	char delta[BUFSZ], band[BUFSZ], *endptr = NULL;
++	wl_roam_prof_band_t *rp;
++
++	rp = (wl_roam_prof_band_t *) kzalloc(sizeof(*rp)
++			* WL_MAX_ROAM_PROF_BRACKETS, GFP_KERNEL);
++	if (unlikely(!rp)) {
++		WL_ERR(("%s: failed to allocate memory\n", __func__));
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	argc = sscanf(data, "%"S(BUFSZ)"s %"S(BUFSZ)"s", band, delta);
++	if (!strcasecmp(band, "a"))
++		rp->band = WLC_BAND_5G;
++	else if (!strcasecmp(band, "b"))
++		rp->band = WLC_BAND_2G;
++	else {
++		WL_ERR(("%s: Missing band\n", __func__));
++		goto exit;
++	}
++	/* Getting roam profile  from fw */
++	if ((err = wldev_iovar_getbuf(ndev, "roam_prof", rp, sizeof(*rp),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN,  &cfg->ioctl_buf_sync))) {
++		WL_ERR(("Getting roam_profile failed with err=%d \n", err));
++		goto exit;
++	}
++	memcpy(rp, cfg->ioctl_buf, sizeof(wl_roam_prof_band_t));
++	if (rp->ver != WL_MAX_ROAM_PROF_VER) {
++		WL_ERR(("bad version (=%d) in return data\n", rp->ver));
++		err = -EINVAL;
++		goto exit;
++	}
++	if ((rp->len % sizeof(wl_roam_prof_t)) != 0) {
++		WL_ERR(("bad length (=%d) in return data\n", rp->len));
++		err = -EINVAL;
++		goto exit;
++	}
++
++	if (argc == 2) {
++		/* if delta is non integer returns command usage error */
++		val = simple_strtol(delta, &endptr, 0);
++		if (*endptr != '\0') {
++			WL_ERR(("%s: Command usage error", __func__));
++			goto exit;
++		}
++		for (i = 0; i < WL_MAX_ROAM_PROF_BRACKETS; i++) {
++		/*
++		 * Checking contents of roam profile data from fw and exits
++		 * if code hits below condtion. If remaining length of buffer is
++		 * less than roam profile size or if there is no valid entry.
++		 */
++			if (((i * sizeof(wl_roam_prof_t)) > rp->len) ||
++				(rp->roam_prof[i].fullscan_period == 0)) {
++				break;
++			}
++			if (rp->roam_prof[i].channel_usage != 0) {
++				rp->roam_prof[i].roam_delta = val;
++			}
++			len += sizeof(wl_roam_prof_t);
++		}
++	}
++	else {
++		if (rp->roam_prof[i].channel_usage != 0) {
++			bytes_written = snprintf(command, total_len,
++				"%s Delta %d\n", (rp->band == WLC_BAND_2G) ? "2G" : "5G",
++				rp->roam_prof[0].roam_delta);
++		}
++		err = bytes_written;
++		goto exit;
++	}
++	rp->len = len;
++	if ((err = wldev_iovar_setbuf(ndev, "roam_prof", rp,
++			sizeof(*rp), cfg->ioctl_buf, WLC_IOCTL_MEDLEN, &cfg->ioctl_buf_sync)) < 0) {
++		WL_ERR(("seting roam_profile failed with err %d\n", err));
++	}
++exit :
++	if (rp) {
++		kfree(rp);
++	}
++	return err;
++}
++#endif /* WBTEXT */
++
++
++int wl_cfg80211_scan_stop(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev)
++{
++	struct net_device *ndev = NULL;
++	unsigned long flags;
++	int clear_flag = 0;
++	int ret = 0;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
++	struct cfg80211_scan_info info;
++#endif
++
++	WL_TRACE(("Enter\n"));
++
++	if (!cfg)
++		return -EINVAL;
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++#ifdef WL_CFG80211_P2P_DEV_IF
++	if (cfg->scan_request && cfg->scan_request->wdev == cfgdev)
++#else
++	if (cfg->scan_request && cfg->scan_request->dev == cfgdev)
++#endif
++	{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
++		info.aborted = true;
++		cfg80211_scan_done(cfg->scan_request, &info);
++#else
++		cfg80211_scan_done(cfg->scan_request, true);
++#endif
++		cfg->scan_request = NULL;
++		clear_flag = 1;
++	}
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++
++	if (clear_flag)
++		wl_clr_drv_status(cfg, SCANNING, ndev);
++
++	return ret;
++}
++
++bool wl_cfg80211_is_concurrent_mode(struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	if ((cfg) && (wl_get_drv_status_all(cfg, CONNECTED) > 1)) {
++		return true;
++	} else {
++		return false;
++	}
++}
++
++void* wl_cfg80211_get_dhdp(struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++
++	return cfg->pub;
++}
++
++bool wl_cfg80211_is_p2p_active(struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	return (cfg && cfg->p2p);
++}
++
++bool wl_cfg80211_is_roam_offload(struct net_device * dev)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	return (cfg && cfg->roam_offload);
++}
++
++bool wl_cfg80211_is_event_from_connected_bssid(struct net_device * dev, const wl_event_msg_t *e,
++		int ifidx)
++{
++	u8 *curbssid = NULL;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++
++	if (!cfg) {
++		/* When interface is created using wl
++		 * ndev->ieee80211_ptr will be NULL.
++		 */
++		return NULL;
++	}
++	curbssid = wl_read_prof(cfg, dev, WL_PROF_BSSID);
++
++	if (!curbssid) {
++		return NULL;
++	}
++
++	if (memcmp(curbssid, &e->addr, ETHER_ADDR_LEN) == 0) {
++		return true;
++	}
++	return false;
++}
++
++static void wl_cfg80211_work_handler(struct work_struct * work)
++{
++	struct bcm_cfg80211 *cfg = NULL;
++	struct net_info *iter, *next;
++	s32 err = BCME_OK;
++	s32 pm = PM_FAST;
++	dhd_pub_t *dhd;
++	BCM_SET_CONTAINER_OF(cfg, work, struct bcm_cfg80211, pm_enable_work.work);
++	WL_DBG(("Enter \n"));
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++	for_each_ndev(cfg, iter, next) {
++		/* p2p discovery iface ndev could be null */
++		if (iter->ndev) {
++			if (!wl_get_drv_status(cfg, CONNECTED, iter->ndev) ||
++				(wl_get_mode_by_netdev(cfg, iter->ndev) != WL_MODE_BSS &&
++				wl_get_mode_by_netdev(cfg, iter->ndev) != WL_MODE_IBSS))
++				continue;
++			if (iter->ndev) {
++				dhd = (dhd_pub_t *)(cfg->pub);
++				if (dhd_conf_get_pm(dhd) >= 0)
++					pm = dhd_conf_get_pm(dhd);
++				if ((err = wldev_ioctl_set(iter->ndev, WLC_SET_PM,
++						&pm, sizeof(pm))) != 0) {
++					if (err == -ENODEV)
++						WL_DBG(("%s:netdev not ready\n",
++							iter->ndev->name));
++					else
++						WL_ERR(("%s:error (%d)\n",
++							iter->ndev->name, err));
++				} else
++					wl_cfg80211_update_power_mode(iter->ndev);
++			}
++		}
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	DHD_PM_WAKE_UNLOCK(cfg->pub);
++}
++
++u8
++wl_get_action_category(void *frame, u32 frame_len)
++{
++	u8 category;
++	u8 *ptr = (u8 *)frame;
++	if (frame == NULL)
++		return DOT11_ACTION_CAT_ERR_MASK;
++	if (frame_len < DOT11_ACTION_HDR_LEN)
++		return DOT11_ACTION_CAT_ERR_MASK;
++	category = ptr[DOT11_ACTION_CAT_OFF];
++	WL_INFORM(("Action Category: %d\n", category));
++	return category;
++}
++
++int
++wl_get_public_action(void *frame, u32 frame_len, u8 *ret_action)
++{
++	u8 *ptr = (u8 *)frame;
++	if (frame == NULL || ret_action == NULL)
++		return BCME_ERROR;
++	if (frame_len < DOT11_ACTION_HDR_LEN)
++		return BCME_ERROR;
++	if (DOT11_ACTION_CAT_PUBLIC != wl_get_action_category(frame, frame_len))
++		return BCME_ERROR;
++	*ret_action = ptr[DOT11_ACTION_ACT_OFF];
++	WL_INFORM(("Public Action : %d\n", *ret_action));
++	return BCME_OK;
++}
++
++#ifdef WLFBT
++int
++wl_cfg80211_get_fbt_key(struct net_device *dev, uint8 *key, int total_len)
++{
++	struct bcm_cfg80211 * cfg = wl_get_cfg(dev);
++	int bytes_written = -1;
++
++	if (total_len < FBT_KEYLEN) {
++		WL_ERR(("wl_cfg80211_get_fbt_key: Insufficient buffer \n"));
++		goto end;
++	}
++	if (cfg) {
++		memcpy(key, cfg->fbt_key, FBT_KEYLEN);
++		bytes_written = FBT_KEYLEN;
++	} else {
++		bzero(key, FBT_KEYLEN);
++		WL_ERR(("wl_cfg80211_get_fbt_key: Failed to copy KCK and KEK \n"));
++	}
++	prhex("KCK, KEK", (uchar *)key, FBT_KEYLEN);
++end:
++	return bytes_written;
++}
++#endif /* WLFBT */
++
++static int
++wl_cfg80211_delayed_roam(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const struct ether_addr *bssid)
++{
++	s32 err;
++	wl_event_msg_t e;
++
++	bzero(&e, sizeof(e));
++	e.event_type = cpu_to_be32(WLC_E_ROAM);
++	memcpy(&e.addr, bssid, ETHER_ADDR_LEN);
++	/* trigger the roam event handler */
++	err = wl_notify_roaming_status(cfg, ndev_to_cfgdev(ndev), &e, NULL);
++
++	return err;
++}
++
++static s32
++wl_cfg80211_parse_vndr_ies(u8 *parse, u32 len,
++    struct parsed_vndr_ies *vndr_ies)
++{
++	s32 err = BCME_OK;
++	vndr_ie_t *vndrie;
++	bcm_tlv_t *ie;
++	struct parsed_vndr_ie_info *parsed_info;
++	u32 count = 0;
++	s32 remained_len;
++
++	remained_len = (s32)len;
++	memset(vndr_ies, 0, sizeof(*vndr_ies));
++
++	WL_DBG(("---> len %d\n", len));
++	ie = (bcm_tlv_t *) parse;
++	if (!bcm_valid_tlv(ie, remained_len))
++		ie = NULL;
++	while (ie) {
++		if (count >= MAX_VNDR_IE_NUMBER)
++			break;
++		if (ie->id == DOT11_MNG_VS_ID) {
++			vndrie = (vndr_ie_t *) ie;
++			/* len should be bigger than OUI length + one data length at least */
++			if (vndrie->len < (VNDR_IE_MIN_LEN + 1)) {
++				WL_ERR(("%s: invalid vndr ie. length is too small %d\n",
++					__FUNCTION__, vndrie->len));
++				goto end;
++			}
++			/* if wpa or wme ie, do not add ie */
++			if (!bcmp(vndrie->oui, (u8*)WPA_OUI, WPA_OUI_LEN) &&
++				((vndrie->data[0] == WPA_OUI_TYPE) ||
++				(vndrie->data[0] == WME_OUI_TYPE))) {
++				WL_DBG(("Found WPA/WME oui. Do not add it\n"));
++				goto end;
++			}
++
++			parsed_info = &vndr_ies->ie_info[count++];
++
++			/* save vndr ie information */
++			parsed_info->ie_ptr = (char *)vndrie;
++			parsed_info->ie_len = (vndrie->len + TLV_HDR_LEN);
++			memcpy(&parsed_info->vndrie, vndrie, sizeof(vndr_ie_t));
++			vndr_ies->count = count;
++
++			WL_DBG(("\t ** OUI %02x %02x %02x, type 0x%02x len:%d\n",
++			parsed_info->vndrie.oui[0], parsed_info->vndrie.oui[1],
++			parsed_info->vndrie.oui[2], parsed_info->vndrie.data[0],
++			parsed_info->ie_len));
++		}
++end:
++		ie = bcm_next_tlv(ie, &remained_len);
++	}
++	return err;
++}
++
++#ifdef WLADPS_SEAK_AP_WAR
++static bool
++wl_find_vndr_ies_specific_vender(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev, const u8 *vndr_oui)
++{
++	struct wl_connect_info *conn_info = wl_to_conn(cfg);
++	struct parsed_vndr_ie_info *vndr_info_list;
++	struct parsed_vndr_ies vndr_ies;
++	bool ret = FALSE;
++	int i;
++
++	if (conn_info->resp_ie_len) {
++		if ((wl_cfg80211_parse_vndr_ies((u8 *)conn_info->resp_ie,
++				conn_info->resp_ie_len, &vndr_ies)) == BCME_OK) {
++			for (i = 0; i < vndr_ies.count; i++) {
++				vndr_info_list = &vndr_ies.ie_info[i];
++				if (!bcmp(vndr_info_list->vndrie.oui,
++						(u8*)vndr_oui, DOT11_OUI_LEN)) {
++					WL_ERR(("Find OUI %02x %02x %02x\n",
++						vndr_info_list->vndrie.oui[0],
++						vndr_info_list->vndrie.oui[1],
++						vndr_info_list->vndrie.oui[2]));
++					ret = TRUE;
++					break;
++				}
++			}
++		}
++	}
++	return ret;
++}
++
++static s32
++wl_set_adps_mode(struct bcm_cfg80211 *cfg, struct net_device *ndev, uint8 enable_mode)
++{
++	int i;
++	int len;
++	int ret = BCME_OK;
++
++	bcm_iov_buf_t *iov_buf = NULL;
++	wl_adps_params_v1_t *data = NULL;
++
++	len = OFFSETOF(bcm_iov_buf_t, data) + sizeof(*data);
++	iov_buf = kmalloc(len, GFP_KERNEL);
++	if (iov_buf == NULL) {
++		WL_ERR(("%s - failed to allocate %d bytes for iov_buf\n", __FUNCTION__, len));
++		ret = BCME_NOMEM;
++		goto exit;
++	}
++
++	iov_buf->version = WL_ADPS_IOV_VER;
++	iov_buf->len = sizeof(*data);
++	iov_buf->id = WL_ADPS_IOV_MODE;
++
++	data = (wl_adps_params_v1_t *)iov_buf->data;
++	data->version = ADPS_SUB_IOV_VERSION_1;
++	data->length = sizeof(*data);
++	data->mode = enable_mode;
++
++	for (i = 1; i <= MAX_BANDS; i++) {
++		data->band = i;
++		ret = wldev_iovar_setbuf(ndev, "adps", iov_buf, len,
++				cfg->ioctl_buf, WLC_IOCTL_SMLEN, NULL);
++	}
++
++exit:
++	if (iov_buf) {
++		kfree(iov_buf);
++	}
++	return ret;
++
++}
++#endif /* WLADPS_SEAK_AP_WAR */
++
++static bool
++wl_vndr_ies_exclude_vndr_oui(struct parsed_vndr_ie_info *vndr_info)
++{
++	int i = 0;
++
++	while (exclude_vndr_oui_list[i]) {
++		if (!memcmp(vndr_info->vndrie.oui,
++			exclude_vndr_oui_list[i],
++			DOT11_OUI_LEN)) {
++			return TRUE;
++		}
++		i++;
++	}
++
++	return FALSE;
++}
++
++static bool
++wl_vndr_ies_check_duplicate_vndr_oui(struct bcm_cfg80211 *cfg,
++	struct parsed_vndr_ie_info *vndr_info)
++{
++	wl_vndr_oui_entry_t *oui_entry = NULL;
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	list_for_each_entry(oui_entry, &cfg->vndr_oui_list, list) {
++		if (!memcmp(oui_entry->oui, vndr_info->vndrie.oui, DOT11_OUI_LEN)) {
++			return TRUE;
++		}
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++	return FALSE;
++}
++
++static bool
++wl_vndr_ies_add_vendor_oui_list(struct bcm_cfg80211 *cfg,
++	struct parsed_vndr_ie_info *vndr_info)
++{
++	wl_vndr_oui_entry_t *oui_entry = NULL;
++
++	oui_entry = kmalloc(sizeof(*oui_entry), GFP_KERNEL);
++	if (oui_entry == NULL) {
++		WL_ERR(("alloc failed\n"));
++		return FALSE;
++	}
++
++	memcpy(oui_entry->oui, vndr_info->vndrie.oui, DOT11_OUI_LEN);
++
++	INIT_LIST_HEAD(&oui_entry->list);
++	list_add_tail(&oui_entry->list, &cfg->vndr_oui_list);
++
++	return TRUE;
++}
++
++static void
++wl_vndr_ies_clear_vendor_oui_list(struct bcm_cfg80211 *cfg)
++{
++	wl_vndr_oui_entry_t *oui_entry = NULL;
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	while (!list_empty(&cfg->vndr_oui_list)) {
++		oui_entry = list_entry(cfg->vndr_oui_list.next, wl_vndr_oui_entry_t, list);
++		if (oui_entry) {
++			list_del(&oui_entry->list);
++			kfree(oui_entry);
++		}
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++}
++
++static int
++wl_vndr_ies_get_vendor_oui(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	char *vndr_oui, u32 vndr_oui_len)
++{
++	int i;
++	int vndr_oui_num = 0;
++
++	struct wl_connect_info *conn_info = wl_to_conn(cfg);
++	wl_vndr_oui_entry_t *oui_entry = NULL;
++	struct parsed_vndr_ie_info *vndr_info;
++	struct parsed_vndr_ies vndr_ies;
++
++	char *pos = vndr_oui;
++	u32 remained_buf_len = vndr_oui_len;
++
++	if (!conn_info->resp_ie_len) {
++		return BCME_ERROR;
++	}
++
++	wl_vndr_ies_clear_vendor_oui_list(cfg);
++
++	if ((wl_cfg80211_parse_vndr_ies((u8 *)conn_info->resp_ie,
++		conn_info->resp_ie_len, &vndr_ies)) == BCME_OK) {
++		for (i = 0; i < vndr_ies.count; i++) {
++			vndr_info = &vndr_ies.ie_info[i];
++			if (wl_vndr_ies_exclude_vndr_oui(vndr_info)) {
++				continue;
++			}
++
++			if (wl_vndr_ies_check_duplicate_vndr_oui(cfg, vndr_info)) {
++				continue;
++			}
++
++			wl_vndr_ies_add_vendor_oui_list(cfg, vndr_info);
++			vndr_oui_num++;
++		}
++	}
++
++	if (vndr_oui) {
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++		list_for_each_entry(oui_entry, &cfg->vndr_oui_list, list) {
++			if (remained_buf_len < VNDR_OUI_STR_LEN) {
++				return BCME_ERROR;
++			}
++			pos += snprintf(pos, VNDR_OUI_STR_LEN, "%02X-%02X-%02X ",
++				oui_entry->oui[0], oui_entry->oui[1], oui_entry->oui[2]);
++			remained_buf_len -= VNDR_OUI_STR_LEN;
++		}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	}
++
++	return vndr_oui_num;
++}
++
++int
++wl_cfg80211_get_vndr_ouilist(struct bcm_cfg80211 *cfg, uint8 *buf, int max_cnt)
++{
++	wl_vndr_oui_entry_t *oui_entry = NULL;
++	int cnt = 0;
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	list_for_each_entry(oui_entry, &cfg->vndr_oui_list, list) {
++		memcpy(buf, oui_entry->oui, DOT11_OUI_LEN);
++		cnt++;
++		if (cnt >= max_cnt) {
++			return cnt;
++		}
++		buf += DOT11_OUI_LEN;
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	return cnt;
++}
++
++s32
++wl_cfg80211_clear_per_bss_ies(struct bcm_cfg80211 *cfg, s32 bssidx)
++{
++	s32 index;
++	struct net_info *netinfo;
++	s32 vndrie_flag[] = {VNDR_IE_BEACON_FLAG, VNDR_IE_PRBRSP_FLAG,
++		VNDR_IE_ASSOCRSP_FLAG, VNDR_IE_PRBREQ_FLAG, VNDR_IE_ASSOCREQ_FLAG};
++
++	netinfo = wl_get_netinfo_by_bssidx(cfg, bssidx);
++	if (!netinfo || !netinfo->wdev) {
++		WL_ERR(("netinfo or netinfo->wdev is NULL\n"));
++		return -1;
++	}
++
++	WL_DBG(("clear management vendor IEs for bssidx:%d \n", bssidx));
++	/* Clear the IEs set in the firmware so that host is in sync with firmware */
++	for (index = 0; index < ARRAYSIZE(vndrie_flag); index++) {
++		if (wl_cfg80211_set_mgmt_vndr_ies(cfg, wdev_to_cfgdev(netinfo->wdev),
++			bssidx, vndrie_flag[index], NULL, 0) < 0)
++			WL_ERR(("vndr_ies clear failed. Ignoring.. \n"));
++	}
++
++	return 0;
++}
++
++s32
++wl_cfg80211_clear_mgmt_vndr_ies(struct bcm_cfg80211 *cfg)
++{
++	struct net_info *iter, *next;
++
++	WL_DBG(("clear management vendor IEs \n"));
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++	for_each_ndev(cfg, iter, next) {
++		wl_cfg80211_clear_per_bss_ies(cfg, iter->bssidx);
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	return 0;
++}
++
++#define WL_VNDR_IE_MAXLEN 2048
++static s8 g_mgmt_ie_buf[WL_VNDR_IE_MAXLEN];
++int
++wl_cfg80211_set_mgmt_vndr_ies(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	s32 bssidx, s32 pktflag, const u8 *vndr_ie, u32 vndr_ie_len)
++{
++	struct net_device *ndev = NULL;
++	s32 ret = BCME_OK;
++	u8  *curr_ie_buf = NULL;
++	u8  *mgmt_ie_buf = NULL;
++	u32 mgmt_ie_buf_len = 0;
++	u32 *mgmt_ie_len = 0;
++	u32 del_add_ie_buf_len = 0;
++	u32 total_ie_buf_len = 0;
++	u32 parsed_ie_buf_len = 0;
++	struct parsed_vndr_ies old_vndr_ies;
++	struct parsed_vndr_ies new_vndr_ies;
++	s32 i;
++	u8 *ptr;
++	s32 remained_buf_len;
++	wl_bss_vndr_ies_t *ies = NULL;
++	struct net_info *netinfo;
++
++	WL_DBG(("Enter. pktflag:0x%x bssidx:%x vnd_ie_len:%d \n",
++		pktflag, bssidx, vndr_ie_len));
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	if (bssidx > WL_MAX_IFS) {
++		WL_ERR(("bssidx > supported concurrent Ifaces \n"));
++		return -EINVAL;
++	}
++
++	netinfo = wl_get_netinfo_by_bssidx(cfg, bssidx);
++	if (!netinfo) {
++		WL_ERR(("net_info ptr is NULL \n"));
++		return -EINVAL;
++	}
++
++	/* Clear the global buffer */
++	memset(g_mgmt_ie_buf, 0, sizeof(g_mgmt_ie_buf));
++	curr_ie_buf = g_mgmt_ie_buf;
++	ies = &netinfo->bss.ies;
++
++	switch (pktflag) {
++		case VNDR_IE_PRBRSP_FLAG :
++			mgmt_ie_buf = ies->probe_res_ie;
++			mgmt_ie_len = &ies->probe_res_ie_len;
++			mgmt_ie_buf_len = sizeof(ies->probe_res_ie);
++			break;
++		case VNDR_IE_ASSOCRSP_FLAG :
++			mgmt_ie_buf = ies->assoc_res_ie;
++			mgmt_ie_len = &ies->assoc_res_ie_len;
++			mgmt_ie_buf_len = sizeof(ies->assoc_res_ie);
++			break;
++		case VNDR_IE_BEACON_FLAG :
++			mgmt_ie_buf = ies->beacon_ie;
++			mgmt_ie_len = &ies->beacon_ie_len;
++			mgmt_ie_buf_len = sizeof(ies->beacon_ie);
++			break;
++		case VNDR_IE_PRBREQ_FLAG :
++			mgmt_ie_buf = ies->probe_req_ie;
++			mgmt_ie_len = &ies->probe_req_ie_len;
++			mgmt_ie_buf_len = sizeof(ies->probe_req_ie);
++			break;
++		case VNDR_IE_ASSOCREQ_FLAG :
++			mgmt_ie_buf = ies->assoc_req_ie;
++			mgmt_ie_len = &ies->assoc_req_ie_len;
++			mgmt_ie_buf_len = sizeof(ies->assoc_req_ie);
++			break;
++		default:
++			mgmt_ie_buf = NULL;
++			mgmt_ie_len = NULL;
++			WL_ERR(("not suitable packet type (%d)\n", pktflag));
++			return BCME_ERROR;
++	}
++
++	if (vndr_ie_len > mgmt_ie_buf_len) {
++		WL_ERR(("extra IE size too big\n"));
++		ret = -ENOMEM;
++	} else {
++		/* parse and save new vndr_ie in curr_ie_buff before comparing it */
++		if (vndr_ie && vndr_ie_len && curr_ie_buf) {
++			ptr = curr_ie_buf;
++/* must discard vndr_ie constness, attempt to change vndr_ie arg to non-const
++ * causes cascade of errors in other places, fix involves const casts there
++ */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++			if ((ret = wl_cfg80211_parse_vndr_ies((u8 *)vndr_ie,
++				vndr_ie_len, &new_vndr_ies)) < 0) {
++				WL_ERR(("parse vndr ie failed \n"));
++				goto exit;
++			}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++			for (i = 0; i < new_vndr_ies.count; i++) {
++				struct parsed_vndr_ie_info *vndrie_info =
++					&new_vndr_ies.ie_info[i];
++
++				if ((parsed_ie_buf_len + vndrie_info->ie_len) > WL_VNDR_IE_MAXLEN) {
++					WL_ERR(("IE size is too big (%d > %d)\n",
++						parsed_ie_buf_len, WL_VNDR_IE_MAXLEN));
++					ret = -EINVAL;
++					goto exit;
++				}
++
++				memcpy(ptr + parsed_ie_buf_len, vndrie_info->ie_ptr,
++					vndrie_info->ie_len);
++				parsed_ie_buf_len += vndrie_info->ie_len;
++			}
++		}
++
++		if (mgmt_ie_buf != NULL) {
++			if (parsed_ie_buf_len && (parsed_ie_buf_len == *mgmt_ie_len) &&
++				(memcmp(mgmt_ie_buf, curr_ie_buf, parsed_ie_buf_len) == 0)) {
++				WL_INFORM(("Previous mgmt IE is equals to current IE"));
++				goto exit;
++			}
++
++			/* parse old vndr_ie */
++			if ((ret = wl_cfg80211_parse_vndr_ies(mgmt_ie_buf, *mgmt_ie_len,
++				&old_vndr_ies)) < 0) {
++				WL_ERR(("parse vndr ie failed \n"));
++				goto exit;
++			}
++			/* make a command to delete old ie */
++			for (i = 0; i < old_vndr_ies.count; i++) {
++				struct parsed_vndr_ie_info *vndrie_info =
++				&old_vndr_ies.ie_info[i];
++
++				WL_INFORM(("DELETED ID : %d, Len: %d , OUI:%02x:%02x:%02x\n",
++					vndrie_info->vndrie.id, vndrie_info->vndrie.len,
++					vndrie_info->vndrie.oui[0], vndrie_info->vndrie.oui[1],
++					vndrie_info->vndrie.oui[2]));
++
++				del_add_ie_buf_len = wl_cfgp2p_vndr_ie(cfg, curr_ie_buf,
++					pktflag, vndrie_info->vndrie.oui,
++					vndrie_info->vndrie.id,
++					vndrie_info->ie_ptr + VNDR_IE_FIXED_LEN,
++					vndrie_info->ie_len - VNDR_IE_FIXED_LEN,
++					"del");
++
++				curr_ie_buf += del_add_ie_buf_len;
++				total_ie_buf_len += del_add_ie_buf_len;
++			}
++		}
++
++		*mgmt_ie_len = 0;
++		/* Add if there is any extra IE */
++		if (mgmt_ie_buf && parsed_ie_buf_len) {
++			ptr = mgmt_ie_buf;
++
++			remained_buf_len = mgmt_ie_buf_len;
++
++			/* make a command to add new ie */
++			for (i = 0; i < new_vndr_ies.count; i++) {
++				struct parsed_vndr_ie_info *vndrie_info =
++					&new_vndr_ies.ie_info[i];
++
++				WL_INFORM(("ADDED ID : %d, Len: %d(%d), OUI:%02x:%02x:%02x\n",
++					vndrie_info->vndrie.id, vndrie_info->vndrie.len,
++					vndrie_info->ie_len - 2,
++					vndrie_info->vndrie.oui[0], vndrie_info->vndrie.oui[1],
++					vndrie_info->vndrie.oui[2]));
++
++				del_add_ie_buf_len = wl_cfgp2p_vndr_ie(cfg, curr_ie_buf,
++					pktflag, vndrie_info->vndrie.oui,
++					vndrie_info->vndrie.id,
++					vndrie_info->ie_ptr + VNDR_IE_FIXED_LEN,
++					vndrie_info->ie_len - VNDR_IE_FIXED_LEN,
++					"add");
++
++				/* verify remained buf size before copy data */
++				if (remained_buf_len >= vndrie_info->ie_len) {
++					remained_buf_len -= vndrie_info->ie_len;
++				} else {
++					WL_ERR(("no space in mgmt_ie_buf: pktflag = %d, "
++					"found vndr ies # = %d(cur %d), remained len %d, "
++					"cur mgmt_ie_len %d, new ie len = %d\n",
++					pktflag, new_vndr_ies.count, i, remained_buf_len,
++					*mgmt_ie_len, vndrie_info->ie_len));
++					break;
++				}
++
++				/* save the parsed IE in cfg struct */
++				memcpy(ptr + (*mgmt_ie_len), vndrie_info->ie_ptr,
++					vndrie_info->ie_len);
++				*mgmt_ie_len += vndrie_info->ie_len;
++				curr_ie_buf += del_add_ie_buf_len;
++				total_ie_buf_len += del_add_ie_buf_len;
++			}
++		}
++
++		if (total_ie_buf_len && cfg->ioctl_buf != NULL) {
++			ret  = wldev_iovar_setbuf_bsscfg(ndev, "vndr_ie", g_mgmt_ie_buf,
++				total_ie_buf_len, cfg->ioctl_buf, WLC_IOCTL_MAXLEN,
++				bssidx, &cfg->ioctl_buf_sync);
++			if (ret)
++				WL_ERR(("vndr ie set error : %d\n", ret));
++		}
++	}
++exit:
++
++return ret;
++}
++
++#ifdef WL_CFG80211_ACL
++static int
++wl_cfg80211_set_mac_acl(struct wiphy *wiphy, struct net_device *cfgdev,
++	const struct cfg80211_acl_data *acl)
++{
++	int i;
++	int ret = 0;
++	int macnum = 0;
++	int macmode = MACLIST_MODE_DISABLED;
++	struct maclist *list;
++
++	/* get the MAC filter mode */
++	if (acl && acl->acl_policy == NL80211_ACL_POLICY_DENY_UNLESS_LISTED) {
++		macmode = MACLIST_MODE_ALLOW;
++	} else if (acl && acl->acl_policy == NL80211_ACL_POLICY_ACCEPT_UNLESS_LISTED &&
++	acl->n_acl_entries) {
++		macmode = MACLIST_MODE_DENY;
++	}
++
++	/* if acl == NULL, macmode is still disabled.. */
++	if (macmode == MACLIST_MODE_DISABLED) {
++		if ((ret = wl_android_set_ap_mac_list(cfgdev, macmode, NULL)) != 0)
++			WL_ERR(("%s : Setting MAC list failed error=%d\n", __FUNCTION__, ret));
++
++		return ret;
++	}
++
++	macnum = acl->n_acl_entries;
++	if (macnum < 0 || macnum > MAX_NUM_MAC_FILT) {
++		WL_ERR(("%s : invalid number of MAC address entries %d\n",
++			__FUNCTION__, macnum));
++		return -1;
++	}
++
++	/* allocate memory for the MAC list */
++	list = (struct maclist*)kmalloc(sizeof(int) +
++		sizeof(struct ether_addr) * macnum, GFP_KERNEL);
++	if (!list) {
++		WL_ERR(("%s : failed to allocate memory\n", __FUNCTION__));
++		return -1;
++	}
++
++	/* prepare the MAC list */
++	list->count = htod32(macnum);
++	for (i = 0; i < macnum; i++) {
++		memcpy(&list->ea[i], &acl->mac_addrs[i], ETHER_ADDR_LEN);
++	}
++	/* set the list */
++	if ((ret = wl_android_set_ap_mac_list(cfgdev, macmode, list)) != 0)
++		WL_ERR(("%s : Setting MAC list failed error=%d\n", __FUNCTION__, ret));
++
++	kfree(list);
++
++	return ret;
++}
++#endif /* WL_CFG80211_ACL */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++int wl_chspec_chandef(chanspec_t chanspec,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	struct cfg80211_chan_def *chandef,
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 5, 0) && (LINUX_VERSION_CODE <= (3, 7, 0)))
++	struct chan_info *chaninfo,
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) */
++struct wiphy *wiphy)
++
++{
++	uint16 freq = 0;
++	int chan_type = 0;
++	int channel = 0;
++	struct ieee80211_channel *chan;
++
++	if (!chandef) {
++		return -1;
++	}
++	channel = CHSPEC_CHANNEL(chanspec);
++
++	switch (CHSPEC_BW(chanspec)) {
++		case WL_CHANSPEC_BW_20:
++			chan_type = NL80211_CHAN_HT20;
++			break;
++		case WL_CHANSPEC_BW_40:
++		{
++			if (CHSPEC_SB_UPPER(chanspec)) {
++				channel += CH_10MHZ_APART;
++			} else {
++				channel -= CH_10MHZ_APART;
++			}
++		}
++			chan_type = NL80211_CHAN_HT40PLUS;
++			break;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0))
++		case WL_CHANSPEC_BW_80:
++		case WL_CHANSPEC_BW_8080:
++		{
++			uint16 sb = CHSPEC_CTL_SB(chanspec);
++
++			if (sb == WL_CHANSPEC_CTL_SB_LL) {
++				channel -= (CH_10MHZ_APART + CH_20MHZ_APART);
++			} else if (sb == WL_CHANSPEC_CTL_SB_LU) {
++				channel -= CH_10MHZ_APART;
++			} else if (sb == WL_CHANSPEC_CTL_SB_UL) {
++				channel += CH_10MHZ_APART;
++			} else {
++				/* WL_CHANSPEC_CTL_SB_UU */
++				channel += (CH_10MHZ_APART + CH_20MHZ_APART);
++			}
++
++			if (sb == WL_CHANSPEC_CTL_SB_LL || sb == WL_CHANSPEC_CTL_SB_LU)
++				chan_type = NL80211_CHAN_HT40MINUS;
++			else if (sb == WL_CHANSPEC_CTL_SB_UL || sb == WL_CHANSPEC_CTL_SB_UU)
++				chan_type = NL80211_CHAN_HT40PLUS;
++		}
++			break;
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0)) */
++		default:
++			chan_type = NL80211_CHAN_HT20;
++			break;
++
++	}
++
++	if (CHSPEC_IS5G(chanspec))
++		freq = ieee80211_channel_to_frequency(channel, NL80211_BAND_5GHZ);
++	else
++		freq = ieee80211_channel_to_frequency(channel, NL80211_BAND_2GHZ);
++
++	chan = ieee80211_get_channel(wiphy, freq);
++	WL_DBG(("channel:%d freq:%d chan_type: %d chan_ptr:%p \n",
++		channel, freq, chan_type, chan));
++
++	if (unlikely(!chan)) {
++		/* fw and cfg80211 channel lists are not in sync */
++		WL_ERR(("Couldn't find matching channel in wiphy channel list \n"));
++		ASSERT(0);
++		return -EINVAL;
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0))
++	cfg80211_chandef_create(chandef, chan, chan_type);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 5, 0) && (LINUX_VERSION_CODE <= (3, 7, 0)))
++	chaninfo->freq = freq;
++	chaninfo->chan_type = chan_type;
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0)) */
++	return 0;
++}
++
++void
++wl_cfg80211_ch_switch_notify(struct net_device *dev, uint16 chanspec, struct wiphy *wiphy)
++{
++	u32 freq;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0))
++	struct cfg80211_chan_def chandef;
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 5, 0) && (LINUX_VERSION_CODE <= (3, 7, 0)))
++	struct chan_info chaninfo;
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0)) */
++
++	if (!wiphy) {
++		WL_MSG(dev->name, "wiphy is null\n");
++		return;
++	}
++#ifndef ALLOW_CHSW_EVT
++	/* Channel switch support is only for AP/GO/ADHOC/MESH */
++	if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_STATION ||
++		dev->ieee80211_ptr->iftype == NL80211_IFTYPE_P2P_CLIENT) {
++		WL_ERR(("No channel switch notify support for STA/GC\n"));
++		return;
++	}
++#endif /* !ALLOW_CHSW_EVT */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0))
++	if (wl_chspec_chandef(chanspec, &chandef, wiphy))
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 5, 0) && (LINUX_VERSION_CODE <= (3, 7, 0)))
++	if (wl_chspec_chandef(chanspec, &chaninfo, wiphy))
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0)) */
++	{
++		WL_ERR(("chspec_chandef failed\n"));
++		return;
++	}
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0))
++	freq = chandef.chan ? chandef.chan->center_freq : chandef.center_freq1;
++	cfg80211_ch_switch_notify(dev, &chandef);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 5, 0) && (LINUX_VERSION_CODE <= (3, 7, 0)))
++	freq = chan_info.freq;
++	cfg80211_ch_switch_notify(dev, freq, chan_info.chan_type);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0)) */
++
++	WL_MSG(dev->name, "Channel switch notification for freq: %d chanspec: 0x%x\n",
++		freq, chanspec);
++	return;
++}
++#endif /* LINUX_VERSION_CODE >= (3, 5, 0) */
++
++#ifdef WL11ULB
++s32
++wl_cfg80211_set_ulb_mode(struct net_device *dev, int mode)
++{
++	int ret;
++	int cur_mode;
++
++	ret = wldev_iovar_getint(dev, "ulb_mode", &cur_mode);
++	if (unlikely(ret)) {
++		WL_ERR(("[ULB] ulb_mode get failed. ret:%d \n", ret));
++		return ret;
++	}
++
++	if (cur_mode == mode) {
++		/* If request mode is same as that of the current mode, then
++		 * do nothing (Avoid unnecessary wl down and up).
++		 */
++		WL_INFORM(("[ULB] No change in ulb_mode. Do nothing.\n"));
++		return 0;
++	}
++
++	/* setting of ulb_mode requires wl to be down */
++	ret = wldev_ioctl_set(dev, WLC_DOWN, NULL, 0);
++	if (unlikely(ret)) {
++		WL_ERR(("[ULB] WLC_DOWN command failed:[%d]\n", ret));
++		return ret;
++	}
++
++	if (mode >= MAX_SUPP_ULB_MODES) {
++		WL_ERR(("[ULB] unsupported ulb_mode :[%d]\n", mode));
++		return -EINVAL;
++	}
++
++	ret = wldev_iovar_setint(dev, "ulb_mode", mode);
++	if (unlikely(ret)) {
++		WL_ERR(("[ULB] ulb_mode set failed. ret:%d \n", ret));
++		return ret;
++	}
++
++	ret = wldev_ioctl_set(dev, WLC_UP, NULL, 0);
++	if (unlikely(ret)) {
++		WL_ERR(("[ULB] WLC_DOWN command failed:[%d]\n", ret));
++		return ret;
++	}
++
++	WL_DBG(("[ULB] ulb_mode set to %d successfully \n", mode));
++
++	return ret;
++}
++
++static s32
++wl_cfg80211_ulbbw_to_ulbchspec(u32 bw)
++{
++	if (bw == ULB_BW_DISABLED) {
++		return WL_CHANSPEC_BW_20;
++	} else if (bw == ULB_BW_10MHZ) {
++		return WL_CHANSPEC_BW_10;
++	} else if (bw == ULB_BW_5MHZ) {
++		return WL_CHANSPEC_BW_5;
++	} else if (bw == ULB_BW_2P5MHZ) {
++		return WL_CHANSPEC_BW_2P5;
++	} else {
++		WL_ERR(("[ULB] unsupported value for ulb_bw \n"));
++		return -EINVAL;
++	}
++}
++
++static chanspec_t
++wl_cfg80211_ulb_get_min_bw_chspec(struct bcm_cfg80211 *cfg, struct wireless_dev *wdev, s32 bssidx)
++{
++	struct net_info *_netinfo;
++
++	/*
++	 *  Return the chspec value corresponding to the
++	 *  BW setting for a particular interface
++	 */
++	if (wdev) {
++		/* if wdev is provided, use it */
++		_netinfo = wl_get_netinfo_by_wdev(cfg, wdev);
++	} else if (bssidx >= 0) {
++		/* if wdev is not provided, use it */
++		_netinfo = wl_get_netinfo_by_bssidx(cfg, bssidx);
++	} else {
++		WL_ERR(("[ULB] wdev/bssidx not provided\n"));
++		return INVCHANSPEC;
++	}
++
++	if (unlikely(!_netinfo)) {
++		WL_ERR(("[ULB] net_info is null \n"));
++		return INVCHANSPEC;
++	}
++
++	if (_netinfo->ulb_bw) {
++		WL_DBG(("[ULB] wdev_ptr:%p ulb_bw:0x%x \n", _netinfo->wdev, _netinfo->ulb_bw));
++		return wl_cfg80211_ulbbw_to_ulbchspec(_netinfo->ulb_bw);
++	} else {
++		return WL_CHANSPEC_BW_20;
++	}
++}
++
++static s32
++wl_cfg80211_get_ulb_bw(struct bcm_cfg80211 *cfg, struct wireless_dev *wdev)
++{
++	struct net_info *_netinfo = wl_get_netinfo_by_wdev(cfg, wdev);
++
++	/*
++	 *  Return the ulb_bw setting for a
++	 *  particular interface
++	 */
++	if (unlikely(!_netinfo)) {
++		WL_ERR(("[ULB] net_info is null \n"));
++		return -1;
++	}
++
++	return _netinfo->ulb_bw;
++}
++
++s32
++wl_cfg80211_set_ulb_bw(struct net_device *dev,
++	u32 ulb_bw,  char *ifname)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	int ret;
++	int mode;
++	struct net_info *_netinfo = NULL, *iter, *next;
++	u32 bssidx;
++
++	if (!ifname)
++		return -EINVAL;
++
++	WL_DBG(("[ULB] Enter. bw_type:%d \n", ulb_bw));
++
++	ret = wldev_iovar_getint(dev, "ulb_mode", &mode);
++	if (unlikely(ret)) {
++		WL_ERR(("[ULB] ulb_mode not supported \n"));
++		return ret;
++	}
++
++	if (mode != ULB_MODE_STD_ALONE_MODE) {
++		WL_ERR(("[ULB] ulb bw modification allowed only in stand-alone mode\n"));
++		return -EINVAL;
++	}
++
++	if (ulb_bw >= MAX_SUPP_ULB_BW) {
++		WL_ERR(("[ULB] unsupported value (%d) for ulb_bw \n", ulb_bw));
++		return -EINVAL;
++	}
++
++#ifdef WL_CFG80211_P2P_DEV_IF
++	if (strcmp(ifname, "p2p-dev-wlan0") == 0) {
++		/* Use wdev corresponding to the dedicated p2p discovery interface */
++		if (likely(cfg->p2p_wdev)) {
++			_netinfo = wl_get_netinfo_by_wdev(cfg, cfg->p2p_wdev);
++		} else {
++			return -ENODEV;
++		}
++	}
++#endif /* WL_CFG80211_P2P_DEV_IF */
++	if (!_netinfo) {
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++		for_each_ndev(cfg, iter, next) {
++			if (iter->ndev) {
++				if (strncmp(iter->ndev->name, ifname, strlen(ifname)) == 0) {
++					_netinfo = wl_get_netinfo_by_netdev(cfg, iter->ndev);
++				}
++			}
++		}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	}
++
++	if (!_netinfo)
++		return -ENODEV;
++	bssidx = _netinfo->bssidx;
++	_netinfo->ulb_bw = ulb_bw;
++
++
++	WL_DBG(("[ULB] Applying ulb_bw:%d for bssidx:%d \n", ulb_bw, bssidx));
++	ret = wldev_iovar_setbuf_bsscfg(dev, "ulb_bw", (void *)&ulb_bw, 4,
++		cfg->ioctl_buf, WLC_IOCTL_SMLEN, bssidx,
++		&cfg->ioctl_buf_sync);
++	if (unlikely(ret)) {
++		WL_ERR(("[ULB] ulb_bw set failed. ret:%d \n", ret));
++		return ret;
++	}
++
++	return ret;
++}
++#endif /* WL11ULB */
++
++static void
++wl_ap_channel_ind(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev,
++	chanspec_t chanspec)
++{
++	u32 channel = LCHSPEC_CHANNEL(chanspec);
++
++	WL_DBG(("(%s) AP channel:%d chspec:0x%x \n",
++		ndev->name, channel, chanspec));
++	if (cfg->ap_oper_channel && (cfg->ap_oper_channel != channel)) {
++		/*
++		 * If cached channel is different from the channel indicated
++		 * by the event, notify user space about the channel switch.
++		 */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++		wl_cfg80211_ch_switch_notify(ndev, chanspec, bcmcfg_to_wiphy(cfg));
++#endif /* LINUX_VERSION_CODE >= (3, 5, 0) */
++		cfg->ap_oper_channel = channel;
++	}
++}
++
++static s32
++wl_ap_start_ind(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++const wl_event_msg_t *e, void *data)
++{
++	struct net_device *ndev = NULL;
++	chanspec_t chanspec;
++
++	WL_DBG(("Enter\n"));
++	if (unlikely(e->status)) {
++		WL_ERR(("status:0x%x \n", e->status));
++		return -1;
++	}
++
++	if (!data) {
++		return -EINVAL;
++	}
++
++	if (likely(cfgdev)) {
++		ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++		chanspec = *((chanspec_t *)data);
++
++		if (wl_get_mode_by_netdev(cfg, ndev) == WL_MODE_AP) {
++			/* For AP/GO role */
++			wl_ap_channel_ind(cfg, ndev, chanspec);
++		}
++	}
++
++	return 0;
++}
++
++static s32
++wl_csa_complete_ind(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++const wl_event_msg_t *e, void *data)
++{
++	int error = 0;
++	u32 chanspec = 0;
++	struct net_device *ndev = NULL;
++
++	WL_DBG(("Enter\n"));
++	if (unlikely(e->status)) {
++		WL_ERR(("status:0x%x \n", e->status));
++		return -1;
++	}
++
++	if (likely(cfgdev)) {
++		ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++		error = wldev_iovar_getint(ndev, "chanspec", &chanspec);
++		if (unlikely(error)) {
++			WL_ERR(("Get chanspec error: %d \n", error));
++			return -1;
++		}
++
++		if (wl_get_mode_by_netdev(cfg, ndev) == WL_MODE_AP) {
++			/* For AP/GO role */
++			wl_ap_channel_ind(cfg, ndev, chanspec);
++		} else {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++			wl_cfg80211_ch_switch_notify(ndev, chanspec, bcmcfg_to_wiphy(cfg));
++#endif /* LINUX_VERSION_CODE >= (3, 5, 0) */
++		}
++
++	}
++
++	return 0;
++}
++
++
++void wl_cfg80211_clear_security(struct bcm_cfg80211 *cfg)
++{
++	struct net_device *dev = bcmcfg_to_prmry_ndev(cfg);
++	int err;
++
++	/* Clear the security settings on the primary Interface */
++	err = wldev_iovar_setint(dev, "wsec", 0);
++	if (unlikely(err)) {
++		WL_ERR(("wsec clear failed \n"));
++	}
++	err = wldev_iovar_setint(dev, "auth", 0);
++	if (unlikely(err)) {
++		WL_ERR(("auth clear failed \n"));
++	}
++	err = wldev_iovar_setint(dev, "wpa_auth", WPA_AUTH_DISABLED);
++	if (unlikely(err)) {
++		WL_ERR(("wpa_auth clear failed \n"));
++	}
++}
++
++#ifdef WL_CFG80211_P2P_DEV_IF
++void wl_cfg80211_del_p2p_wdev(struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	struct wireless_dev *wdev = NULL;
++
++	WL_DBG(("Enter \n"));
++	if (!cfg) {
++		WL_ERR(("Invalid Ptr\n"));
++		return;
++	} else {
++		wdev = cfg->p2p_wdev;
++	}
++
++	if (wdev && cfg->down_disc_if) {
++		wl_cfgp2p_del_p2p_disc_if(wdev, cfg);
++		cfg->down_disc_if = FALSE;
++	}
++}
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++#ifdef GTK_OFFLOAD_SUPPORT
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
++static s32
++wl_cfg80211_set_rekey_data(struct wiphy *wiphy, struct net_device *dev,
++		struct cfg80211_gtk_rekey_data *data)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 err = 0;
++	gtk_keyinfo_t keyinfo;
++	bcol_gtk_para_t bcol_keyinfo;
++
++	WL_DBG(("Enter\n"));
++	if (data == NULL || cfg->p2p_net == dev) {
++		WL_ERR(("data is NULL or wrong net device\n"));
++		return -EINVAL;
++	}
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)
++	prhex("kck", (uchar *) (data->kck), RSN_KCK_LENGTH);
++	prhex("kek", (uchar *) (data->kek), RSN_KEK_LENGTH);
++	prhex("replay_ctr", (uchar *) (data->replay_ctr), RSN_REPLAY_LEN);
++#else
++	prhex("kck", (uchar *)data->kck, RSN_KCK_LENGTH);
++	prhex("kek", (uchar *)data->kek, RSN_KEK_LENGTH);
++	prhex("replay_ctr", (uchar *)data->replay_ctr, RSN_REPLAY_LEN);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) */
++	bcopy(data->kck, keyinfo.KCK, RSN_KCK_LENGTH);
++	bcopy(data->kek, keyinfo.KEK, RSN_KEK_LENGTH);
++	bcopy(data->replay_ctr, keyinfo.ReplayCounter, RSN_REPLAY_LEN);
++
++	memset(&bcol_keyinfo, 0, sizeof(bcol_keyinfo));
++	bcol_keyinfo.enable = 1;
++	bcol_keyinfo.ptk_len = 64;
++	memcpy(&bcol_keyinfo.ptk[0], data->kck, RSN_KCK_LENGTH);
++	memcpy(&bcol_keyinfo.ptk[RSN_KCK_LENGTH], data->kek, RSN_KEK_LENGTH);
++	err = wldev_iovar_setbuf(dev, "bcol_gtk_rekey_ptk", &bcol_keyinfo,
++		sizeof(bcol_keyinfo), cfg->ioctl_buf, WLC_IOCTL_SMLEN, &cfg->ioctl_buf_sync);
++	if (!err) {
++		return err;
++	}
++
++	if ((err = wldev_iovar_setbuf(dev, "gtk_key_info", &keyinfo, sizeof(keyinfo),
++		cfg->ioctl_buf, WLC_IOCTL_SMLEN, &cfg->ioctl_buf_sync)) < 0) {
++		WL_ERR(("seting gtk_key_info failed code=%d\n", err));
++		return err;
++	}
++
++	WL_DBG(("Exit\n"));
++	return err;
++}
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0) */
++#endif /* GTK_OFFLOAD_SUPPORT */
++
++#if defined(WL_SUPPORT_AUTO_CHANNEL)
++int
++wl_cfg80211_set_spect(struct net_device *dev, int spect)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	int wlc_down = 1;
++	int wlc_up = 1;
++	int err = BCME_OK;
++
++	if (!wl_get_drv_status_all(cfg, CONNECTED)) {
++		err = wldev_ioctl_set(dev, WLC_DOWN, &wlc_down, sizeof(wlc_down));
++		if (err) {
++			WL_ERR(("%s: WLC_DOWN failed: code: %d\n", __func__, err));
++			return err;
++		}
++
++		err = wldev_ioctl_set(dev, WLC_SET_SPECT_MANAGMENT, &spect, sizeof(spect));
++		if (err) {
++			WL_ERR(("%s: error setting spect: code: %d\n", __func__, err));
++			return err;
++		}
++
++		err = wldev_ioctl_set(dev, WLC_UP, &wlc_up, sizeof(wlc_up));
++		if (err) {
++			WL_ERR(("%s: WLC_UP failed: code: %d\n", __func__, err));
++			return err;
++		}
++	}
++	return err;
++}
++
++int
++wl_cfg80211_get_sta_channel(struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	int channel = 0;
++
++	if (wl_get_drv_status(cfg, CONNECTED, dev)) {
++		channel = cfg->channel;
++	}
++	return channel;
++}
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++#ifdef P2P_LISTEN_OFFLOADING
++s32
++wl_cfg80211_p2plo_deinit(struct bcm_cfg80211 *cfg)
++{
++	s32 bssidx;
++	int ret = 0;
++	int p2plo_pause = 0;
++	if (!cfg || !cfg->p2p) {
++		WL_ERR(("Wl %p or cfg->p2p %p is null\n",
++			cfg, cfg ? cfg->p2p : 0));
++		return 0;
++	}
++
++	bssidx = wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++	ret = wldev_iovar_setbuf_bsscfg(bcmcfg_to_prmry_ndev(cfg),
++			"p2po_stop", (void*)&p2plo_pause, sizeof(p2plo_pause),
++			cfg->ioctl_buf, WLC_IOCTL_SMLEN, bssidx, &cfg->ioctl_buf_sync);
++	if (ret < 0) {
++		WL_ERR(("p2po_stop Failed :%d\n", ret));
++	}
++
++	return  ret;
++}
++s32
++wl_cfg80211_p2plo_listen_start(struct net_device *dev, u8 *buf, int len)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	s32 bssidx = wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++	wl_p2plo_listen_t p2plo_listen;
++	int ret = -EAGAIN;
++	int channel = 0;
++	int period = 0;
++	int interval = 0;
++	int count = 0;
++	if (WL_DRV_STATUS_SENDING_AF_FRM_EXT(cfg)) {
++		WL_ERR(("Sending Action Frames. Try it again.\n"));
++		goto exit;
++	}
++
++	if (wl_get_drv_status_all(cfg, SCANNING)) {
++		WL_ERR(("Scanning already\n"));
++		goto exit;
++	}
++
++	if (wl_get_drv_status(cfg, SCAN_ABORTING, dev)) {
++		WL_ERR(("Scanning being aborted\n"));
++		goto exit;
++	}
++
++	if (wl_get_p2p_status(cfg, DISC_IN_PROGRESS)) {
++		WL_ERR(("p2p listen offloading already running\n"));
++		goto exit;
++	}
++
++	/* Just in case if it is not enabled */
++	if ((ret = wl_cfgp2p_enable_discovery(cfg, dev, NULL, 0)) < 0) {
++		WL_ERR(("cfgp2p_enable discovery failed"));
++		goto exit;
++	}
++
++	bzero(&p2plo_listen, sizeof(wl_p2plo_listen_t));
++
++	if (len) {
++		sscanf(buf, " %10d %10d %10d %10d", &channel, &period, &interval, &count);
++		if ((channel == 0) || (period == 0) ||
++				(interval == 0) || (count == 0)) {
++			WL_ERR(("Wrong argument %d/%d/%d/%d \n",
++				channel, period, interval, count));
++			ret = -EAGAIN;
++			goto exit;
++		}
++		p2plo_listen.period = period;
++		p2plo_listen.interval = interval;
++		p2plo_listen.count = count;
++
++		WL_ERR(("channel:%d period:%d, interval:%d count:%d\n",
++			channel, period, interval, count));
++	} else {
++		WL_ERR(("Argument len is wrong.\n"));
++		ret = -EAGAIN;
++		goto exit;
++	}
++
++	if ((ret = wldev_iovar_setbuf_bsscfg(dev, "p2po_listen_channel", (void*)&channel,
++			sizeof(channel), cfg->ioctl_buf, WLC_IOCTL_SMLEN,
++			bssidx, &cfg->ioctl_buf_sync)) < 0) {
++		WL_ERR(("p2po_listen_channel Failed :%d\n", ret));
++		goto exit;
++	}
++
++	if ((ret = wldev_iovar_setbuf_bsscfg(dev, "p2po_listen", (void*)&p2plo_listen,
++			sizeof(wl_p2plo_listen_t), cfg->ioctl_buf, WLC_IOCTL_SMLEN,
++			bssidx, &cfg->ioctl_buf_sync)) < 0) {
++		WL_ERR(("p2po_listen Failed :%d\n", ret));
++		goto exit;
++	}
++
++	wl_set_p2p_status(cfg, DISC_IN_PROGRESS);
++exit :
++	return ret;
++}
++s32
++wl_cfg80211_p2plo_listen_stop(struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	s32 bssidx = wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++	int ret = -EAGAIN;
++
++	if ((ret = wldev_iovar_setbuf_bsscfg(dev, "p2po_stop", NULL,
++			0, cfg->ioctl_buf, WLC_IOCTL_SMLEN,
++			bssidx, &cfg->ioctl_buf_sync)) < 0) {
++		WL_ERR(("p2po_stop Failed :%d\n", ret));
++		goto exit;
++	}
++
++exit:
++	return ret;
++}
++#endif /* P2P_LISTEN_OFFLOADING */
++
++u64
++wl_cfg80211_get_new_roc_id(struct bcm_cfg80211 *cfg)
++{
++	u64 id = 0;
++	id = ++cfg->last_roc_id;
++#ifdef  P2P_LISTEN_OFFLOADING
++	if (id == P2PO_COOKIE) {
++		id = ++cfg->last_roc_id;
++	}
++#endif /* P2P_LISTEN_OFFLOADING */
++	if (id == 0)
++		id = ++cfg->last_roc_id;
++	return id;
++}
++
++#if defined(SUPPORT_RANDOM_MAC_SCAN)
++int
++wl_cfg80211_set_random_mac(struct net_device *dev, bool enable)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	int ret;
++
++	if (cfg->random_mac_enabled == enable) {
++		WL_ERR(("Random MAC already %s\n", enable ? "Enabled" : "Disabled"));
++		return BCME_OK;
++	}
++
++	if (enable) {
++		ret = wl_cfg80211_random_mac_enable(dev);
++	} else {
++		ret = wl_cfg80211_random_mac_disable(dev);
++	}
++
++	if (!ret) {
++		cfg->random_mac_enabled = enable;
++	}
++
++	return ret;
++}
++
++int
++wl_cfg80211_random_mac_enable(struct net_device *dev)
++{
++	u8 random_mac[ETH_ALEN] = {0, };
++	u8 rand_bytes[3] = {0, };
++	s32 err = BCME_ERROR;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++
++	if (wl_get_drv_status_all(cfg, CONNECTED) || wl_get_drv_status_all(cfg, CONNECTING) ||
++	    wl_get_drv_status_all(cfg, AP_CREATED) || wl_get_drv_status_all(cfg, AP_CREATING)) {
++		WL_ERR(("fail to Set random mac, current state is wrong\n"));
++		return err;
++	}
++
++	memcpy(random_mac, bcmcfg_to_prmry_ndev(cfg)->dev_addr, ETH_ALEN);
++	get_random_bytes(&rand_bytes, sizeof(rand_bytes));
++
++	if (rand_bytes[2] == 0x0 || rand_bytes[2] == 0xff) {
++		rand_bytes[2] = 0xf0;
++	}
++
++	memcpy(&random_mac[3], rand_bytes, sizeof(rand_bytes));
++
++	err = wldev_iovar_setbuf_bsscfg(bcmcfg_to_prmry_ndev(cfg), "cur_etheraddr",
++		random_mac, ETH_ALEN, cfg->ioctl_buf, WLC_IOCTL_SMLEN, 0, &cfg->ioctl_buf_sync);
++
++	if (err != BCME_OK) {
++		WL_ERR(("failed to set random generate MAC address\n"));
++	} else {
++		WL_ERR(("set mac " MACDBG " to " MACDBG "\n",
++			MAC2STRDBG((const u8 *)bcmcfg_to_prmry_ndev(cfg)->dev_addr),
++			MAC2STRDBG((const u8 *)&random_mac)));
++		WL_ERR(("random MAC enable done"));
++	}
++
++	return err;
++}
++
++int
++wl_cfg80211_random_mac_disable(struct net_device *dev)
++{
++	s32 err = BCME_ERROR;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++
++	WL_ERR(("set original mac " MACDBG "\n",
++		MAC2STRDBG((const u8 *)bcmcfg_to_prmry_ndev(cfg)->dev_addr)));
++
++	err = wldev_iovar_setbuf_bsscfg(bcmcfg_to_prmry_ndev(cfg), "cur_etheraddr",
++		bcmcfg_to_prmry_ndev(cfg)->dev_addr, ETH_ALEN,
++		cfg->ioctl_buf, WLC_IOCTL_SMLEN, 0, &cfg->ioctl_buf_sync);
++
++	if (err != BCME_OK) {
++		WL_ERR(("failed to set original MAC address\n"));
++	} else {
++		WL_ERR(("random MAC disable done\n"));
++	}
++
++	return err;
++}
++#endif /* SUPPORT_RANDOM_MAC_SCAN */
++
++#ifdef WLTDLS
++static s32
++wl_cfg80211_tdls_config(struct bcm_cfg80211 *cfg, enum wl_tdls_config state, bool auto_mode)
++{
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	int err = 0;
++	struct net_info *iter, *next;
++	int update_reqd = 0;
++	int enable = 0;
++	dhd_pub_t *dhdp;
++	dhdp = (dhd_pub_t *)(cfg->pub);
++
++	/*
++	 * TDLS need to be enabled only if we have a single STA/GC
++	 * connection.
++	 */
++
++	WL_DBG(("Enter state:%d\n", state));
++
++	if (!cfg->tdls_supported) {
++		/* FW doesn't support tdls. Do nothing */
++		return -ENODEV;
++	}
++
++	/* Protect tdls config session */
++	mutex_lock(&cfg->tdls_sync);
++
++	if ((state == TDLS_STATE_TEARDOWN)) {
++		/* Host initiated TDLS tear down */
++		err = dhd_tdls_enable(ndev, false, auto_mode, NULL);
++		goto exit;
++	} else if (state == TDLS_STATE_AP_CREATE) {
++		/* We don't support tdls while AP/GO is operational */
++		update_reqd = true;
++		enable = false;
++	} else if ((state == TDLS_STATE_CONNECT) || (state == TDLS_STATE_IF_CREATE)) {
++		if (wl_get_drv_status_all(cfg,
++			CONNECTED) >= TDLS_MAX_IFACE_FOR_ENABLE) {
++			/* For STA/GC connect command request, disable
++			 * tdls if we have any concurrent interfaces
++			 * operational.
++			 */
++			WL_DBG(("Interface limit restriction. disable tdls.\n"));
++			update_reqd = true;
++			enable = false;
++		}
++	} else if ((state == TDLS_STATE_DISCONNECT) ||
++		(state == TDLS_STATE_AP_DELETE) ||
++		(state == TDLS_STATE_SETUP) ||
++		(state == TDLS_STATE_IF_DELETE)) {
++		/* Enable back the tdls connection only if we have less than
++		 * or equal to a single STA/GC connection.
++		 */
++		if (wl_get_drv_status_all(cfg,
++			CONNECTED) == 0) {
++			/* If there are no interfaces connected, enable tdls */
++			update_reqd = true;
++			enable = true;
++		} else if (wl_get_drv_status_all(cfg,
++			CONNECTED) == TDLS_MAX_IFACE_FOR_ENABLE) {
++			/* We have one interface in CONNECTED state.
++			 * Verify whether its a non-AP interface before
++			 * we enable back tdls.
++			 */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++			for_each_ndev(cfg, iter, next) {
++				if ((iter->ndev) && (wl_get_drv_status(cfg, CONNECTED, ndev)) &&
++					wl_get_mode_by_netdev(cfg, ndev) == WL_MODE_AP) {
++					WL_DBG(("AP/GO operational. Can't enable tdls. \n"));
++					err = -ENOTSUPP;
++					goto exit;
++				}
++			}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++			/* No AP/GO found. Enable back tdls */
++			update_reqd = true;
++			enable = true;
++		} else {
++			WL_DBG(("Concurrent connection mode. Can't enable tdls. \n"));
++			err = -ENOTSUPP;
++			goto exit;
++		}
++	} else {
++		WL_ERR(("Unknown tdls state:%d \n", state));
++		err = -EINVAL;
++		goto exit;
++	}
++
++	if (update_reqd == true) {
++		if (dhdp->tdls_enable == enable) {
++			WL_ERR(("No change in tdls state. Do nothing."
++				" tdls_enable:%d\n", enable));
++			goto exit;
++		}
++		err = wldev_iovar_setint(ndev, "tdls_enable", enable);
++		if (unlikely(err)) {
++			WL_ERR(("tdls_enable setting failed. err:%d\n", err));
++			goto exit;
++		} else {
++			WL_DBG(("set tdls_enable: %d done\n", enable));
++			/* Update the dhd state variable to be in sync */
++			dhdp->tdls_enable = enable;
++			if (state == TDLS_STATE_SETUP) {
++				/* For host initiated setup, apply TDLS params
++				 * Don't propagate errors up for param config
++				 * failures
++				 */
++				dhd_tdls_enable(ndev, true, auto_mode, NULL);
++
++			}
++		}
++	} else {
++		WL_DBG(("Skip tdls config. state:%d update_reqd:%d "
++			"current_status:%d \n",
++			state, update_reqd, dhdp->tdls_enable));
++	}
++
++exit:
++	mutex_unlock(&cfg->tdls_sync);
++
++	return err;
++}
++#endif /* WLTDLS */
++
++struct net_device* wl_get_ap_netdev(struct bcm_cfg80211 *cfg, char *ifname)
++{
++	struct net_info *iter, *next;
++	struct net_device *ndev = NULL;
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	for_each_ndev(cfg, iter, next) {
++		if (iter->ndev) {
++			if (strncmp(iter->ndev->name, ifname, strlen(iter->ndev->name)) == 0) {
++				if (iter->ndev->ieee80211_ptr->iftype == NL80211_IFTYPE_AP) {
++					ndev = iter->ndev;
++					break;
++				}
++			}
++		}
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++	return ndev;
++}
++
++struct net_device*
++wl_get_netdev_by_name(struct bcm_cfg80211 *cfg, char *ifname)
++{
++	struct net_info *iter, *next;
++	struct net_device *ndev = NULL;
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	for_each_ndev(cfg, iter, next) {
++		if (iter->ndev) {
++			if (strncmp(iter->ndev->name, ifname, IFNAMSIZ) == 0) {
++				ndev = iter->ndev;
++				break;
++			}
++		}
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++	return ndev;
++}
++
++#ifdef SUPPORT_AP_HIGHER_BEACONRATE
++#define WLC_RATE_FLAG	0x80
++#define RATE_MASK		0x7f
++
++int wl_set_ap_beacon_rate(struct net_device *dev, int val, char *ifname)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	dhd_pub_t *dhdp;
++	wl_rateset_args_t rs;
++	int error = BCME_ERROR, i;
++	struct net_device *ndev = NULL;
++
++	dhdp = (dhd_pub_t *)(cfg->pub);
++
++	if (dhdp && !(dhdp->op_mode & DHD_FLAG_HOSTAP_MODE)) {
++		WL_ERR(("Not Hostapd mode\n"));
++		return BCME_NOTAP;
++	}
++
++	ndev = wl_get_ap_netdev(cfg, ifname);
++
++	if (ndev == NULL) {
++		WL_ERR(("No softAP interface named %s\n", ifname));
++		return BCME_NOTAP;
++	}
++
++	bzero(&rs, sizeof(wl_rateset_args_t));
++	error = wldev_iovar_getbuf(ndev, "rateset", NULL, 0,
++		&rs, sizeof(wl_rateset_args_t), NULL);
++	if (error < 0) {
++		WL_ERR(("get rateset failed = %d\n", error));
++		return error;
++	}
++
++	if (rs.count < 1) {
++		WL_ERR(("Failed to get rate count\n"));
++		return BCME_ERROR;
++	}
++
++	/* Host delivers target rate in the unit of 500kbps */
++	/* To make it to 1mbps unit, atof should be implemented for 5.5mbps basic rate */
++	for (i = 0; i < rs.count && i < WL_NUMRATES; i++)
++		if (rs.rates[i] & WLC_RATE_FLAG)
++			if ((rs.rates[i] & RATE_MASK) == val)
++				break;
++
++	/* Valid rate has been delivered as an argument */
++	if (i < rs.count && i < WL_NUMRATES) {
++		error = wldev_iovar_setint(ndev, "force_bcn_rspec", val);
++		if (error < 0) {
++			WL_ERR(("set beacon rate failed = %d\n", error));
++			return BCME_ERROR;
++		}
++	} else {
++		WL_ERR(("Rate is invalid"));
++		return BCME_BADARG;
++	}
++
++	return BCME_OK;
++}
++
++int
++wl_get_ap_basic_rate(struct net_device *dev, char* command, char *ifname, int total_len)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	dhd_pub_t *dhdp;
++	wl_rateset_args_t rs;
++	int error = BCME_ERROR;
++	int i, bytes_written = 0;
++	struct net_device *ndev = NULL;
++
++	dhdp = (dhd_pub_t *)(cfg->pub);
++
++	if (!(dhdp->op_mode & DHD_FLAG_HOSTAP_MODE)) {
++		WL_ERR(("Not Hostapd mode\n"));
++		return BCME_NOTAP;
++	}
++
++	ndev = wl_get_ap_netdev(cfg, ifname);
++
++	if (ndev == NULL) {
++		WL_ERR(("No softAP interface named %s\n", ifname));
++		return BCME_NOTAP;
++	}
++
++	bzero(&rs, sizeof(wl_rateset_args_t));
++	error = wldev_iovar_getbuf(ndev, "rateset", NULL, 0,
++		&rs, sizeof(wl_rateset_args_t), NULL);
++	if (error < 0) {
++		WL_ERR(("get rateset failed = %d\n", error));
++		return error;
++	}
++
++	if (rs.count < 1) {
++		WL_ERR(("Failed to get rate count\n"));
++		return BCME_ERROR;
++	}
++
++	/* Delivers basic rate in the unit of 500kbps to host */
++	for (i = 0; i < rs.count && i < WL_NUMRATES; i++)
++		if (rs.rates[i] & WLC_RATE_FLAG)
++			bytes_written += snprintf(command + bytes_written, total_len,
++							"%d ", rs.rates[i] & RATE_MASK);
++
++	/* Remove last space in the command buffer */
++	if (bytes_written) {
++		command[bytes_written - 1] = '\0';
++		bytes_written--;
++	}
++
++	return bytes_written;
++
++}
++#endif /* SUPPORT_AP_HIGHER_BEACONRATE */
++
++#ifdef SUPPORT_AP_RADIO_PWRSAVE
++static int
++_wl_update_ap_rps_params(struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	rpsnoa_iovar_params_t iovar;
++	u8 smbuf[WLC_IOCTL_SMLEN];
++
++	if (!dev)
++		return BCME_BADARG;
++
++	memset(&iovar, 0, sizeof(iovar));
++	memset(smbuf, 0, sizeof(smbuf));
++
++	iovar.hdr.ver = RADIO_PWRSAVE_VERSION;
++	iovar.hdr.subcmd = WL_RPSNOA_CMD_PARAMS;
++	iovar.hdr.len = sizeof(iovar);
++	iovar.param->band = WLC_BAND_ALL;
++	iovar.param->level = cfg->ap_rps_info.level;
++	iovar.param->stas_assoc_check = cfg->ap_rps_info.sta_assoc_check;
++	iovar.param->pps = cfg->ap_rps_info.pps;
++	iovar.param->quiet_time = cfg->ap_rps_info.quiet_time;
++
++	if (wldev_iovar_setbuf(dev, "rpsnoa", &iovar, sizeof(iovar),
++		smbuf, sizeof(smbuf), NULL)) {
++		WL_ERR(("Failed to set rpsnoa params"));
++		return BCME_ERROR;
++	}
++
++	return BCME_OK;
++}
++
++int
++wl_get_ap_rps(struct net_device *dev, char* command, char *ifname, int total_len)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	dhd_pub_t *dhdp;
++	int error = BCME_ERROR;
++	int bytes_written = 0;
++	struct net_device *ndev = NULL;
++	rpsnoa_iovar_t iovar;
++	u8 smbuf[WLC_IOCTL_SMLEN];
++	u32 chanspec = 0;
++	u8 idx = 0;
++	u8 val;
++
++	dhdp = (dhd_pub_t *)(cfg->pub);
++
++	if (!dhdp) {
++		error = BCME_NOTUP;
++		goto fail;
++	}
++
++	if (!(dhdp->op_mode & DHD_FLAG_HOSTAP_MODE)) {
++		WL_ERR(("Not Hostapd mode\n"));
++		error = BCME_NOTAP;
++		goto fail;
++	}
++
++	ndev = wl_get_ap_netdev(cfg, ifname);
++
++	if (ndev == NULL) {
++		WL_ERR(("No softAP interface named %s\n", ifname));
++		error = BCME_NOTAP;
++		goto fail;
++	}
++
++	memset(&iovar, 0, sizeof(iovar));
++	memset(smbuf, 0, sizeof(smbuf));
++
++	iovar.hdr.ver = RADIO_PWRSAVE_VERSION;
++	iovar.hdr.subcmd = WL_RPSNOA_CMD_STATUS;
++	iovar.hdr.len = sizeof(iovar);
++	iovar.data->band = WLC_BAND_ALL;
++
++	error = wldev_iovar_getbuf(ndev, "rpsnoa", &iovar, sizeof(iovar),
++		smbuf, sizeof(smbuf), NULL);
++	if (error < 0) {
++		WL_ERR(("get ap radio pwrsave failed = %d\n", error));
++		goto fail;
++	}
++
++	/* RSDB event doesn't seem to be handled correctly.
++	 * So check chanspec of AP directly from the firmware
++	 */
++	error = wldev_iovar_getint(ndev, "chanspec", (s32 *)&chanspec);
++	if (error < 0) {
++		WL_ERR(("get chanspec from AP failed = %d\n", error));
++		goto fail;
++	}
++
++	chanspec = wl_chspec_driver_to_host(chanspec);
++	if (CHSPEC_IS2G(chanspec))
++		idx = 0;
++	else if (CHSPEC_IS5G(chanspec))
++		idx = 1;
++	else {
++		error = BCME_BADCHAN;
++		goto fail;
++	}
++
++	val = ((rpsnoa_iovar_t *)smbuf)->data[idx].value;
++	bytes_written += snprintf(command + bytes_written, total_len, "%d", val);
++	error = bytes_written;
++
++fail:
++	return error;
++}
++
++int
++wl_set_ap_rps(struct net_device *dev, bool enable, char *ifname)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	dhd_pub_t *dhdp;
++	struct net_device *ndev = NULL;
++	rpsnoa_iovar_t iovar;
++	u8 smbuf[WLC_IOCTL_SMLEN];
++	int ret = BCME_OK;
++
++	dhdp = (dhd_pub_t *)(cfg->pub);
++
++	if (!dhdp) {
++		ret = BCME_NOTUP;
++		goto exit;
++	}
++
++	if (!(dhdp->op_mode & DHD_FLAG_HOSTAP_MODE)) {
++		WL_ERR(("Not Hostapd mode\n"));
++		ret = BCME_NOTAP;
++		goto exit;
++	}
++
++	ndev = wl_get_ap_netdev(cfg, ifname);
++
++	if (ndev == NULL) {
++		WL_ERR(("No softAP interface named %s\n", ifname));
++		ret = BCME_NOTAP;
++		goto exit;
++	}
++
++	if (cfg->ap_rps_info.enable != enable) {
++		cfg->ap_rps_info.enable = enable;
++		if (enable) {
++			ret = _wl_update_ap_rps_params(ndev);
++			if (ret) {
++				WL_ERR(("Filed to update rpsnoa params\n"));
++				goto exit;
++			}
++		}
++		memset(&iovar, 0, sizeof(iovar));
++		memset(smbuf, 0, sizeof(smbuf));
++
++		iovar.hdr.ver = RADIO_PWRSAVE_VERSION;
++		iovar.hdr.subcmd = WL_RPSNOA_CMD_ENABLE;
++		iovar.hdr.len = sizeof(iovar);
++		iovar.data->band = WLC_BAND_ALL;
++		iovar.data->value = (int16)enable;
++
++		ret = wldev_iovar_setbuf(ndev, "rpsnoa", &iovar, sizeof(iovar),
++			smbuf, sizeof(smbuf), NULL);
++		if (ret) {
++			WL_ERR(("Failed to enable AP radio power save"));
++			goto exit;
++		}
++		cfg->ap_rps_info.enable = enable;
++	}
++exit:
++	return ret;
++}
++
++int
++wl_update_ap_rps_params(struct net_device *dev, ap_rps_info_t* rps, char *ifname)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	dhd_pub_t *dhdp;
++	struct net_device *ndev = NULL;
++
++	dhdp = (dhd_pub_t *)(cfg->pub);
++
++	if (!dhdp)
++		return BCME_NOTUP;
++
++	if (!(dhdp->op_mode & DHD_FLAG_HOSTAP_MODE)) {
++		WL_ERR(("Not Hostapd mode\n"));
++		return BCME_NOTAP;
++	}
++
++	ndev = wl_get_ap_netdev(cfg, ifname);
++
++	if (ndev == NULL) {
++		WL_ERR(("No softAP interface named %s\n", ifname));
++		return BCME_NOTAP;
++	}
++
++	if (!rps)
++		return BCME_BADARG;
++
++	if (rps->pps < RADIO_PWRSAVE_PPS_MIN)
++		return BCME_BADARG;
++
++	if (rps->level < RADIO_PWRSAVE_LEVEL_MIN ||
++		rps->level > RADIO_PWRSAVE_LEVEL_MAX)
++		return BCME_BADARG;
++
++	if (rps->quiet_time < RADIO_PWRSAVE_QUIETTIME_MIN)
++		return BCME_BADARG;
++
++	if (rps->sta_assoc_check > RADIO_PWRSAVE_ASSOCCHECK_MAX ||
++		rps->sta_assoc_check < RADIO_PWRSAVE_ASSOCCHECK_MIN)
++		return BCME_BADARG;
++
++	cfg->ap_rps_info.pps = rps->pps;
++	cfg->ap_rps_info.level = rps->level;
++	cfg->ap_rps_info.quiet_time = rps->quiet_time;
++	cfg->ap_rps_info.sta_assoc_check = rps->sta_assoc_check;
++
++	if (cfg->ap_rps_info.enable) {
++		if (_wl_update_ap_rps_params(ndev)) {
++			WL_ERR(("Failed to update rpsnoa params"));
++			return BCME_ERROR;
++		}
++	}
++
++	return BCME_OK;
++}
++
++void
++wl_cfg80211_init_ap_rps(struct bcm_cfg80211 *cfg)
++{
++	cfg->ap_rps_info.enable = FALSE;
++	cfg->ap_rps_info.sta_assoc_check = RADIO_PWRSAVE_STAS_ASSOC_CHECK;
++	cfg->ap_rps_info.pps = RADIO_PWRSAVE_PPS;
++	cfg->ap_rps_info.quiet_time = RADIO_PWRSAVE_QUIET_TIME;
++	cfg->ap_rps_info.level = RADIO_PWRSAVE_LEVEL;
++}
++#endif /* SUPPORT_AP_RADIO_PWRSAVE */
++
++int
++wl_cfg80211_iface_count(struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	struct net_info *iter, *next;
++	int iface_count = 0;
++
++	/* Return the count of network interfaces (skip netless p2p discovery
++	 * interface)
++	 */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	for_each_ndev(cfg, iter, next) {
++		if (iter->ndev) {
++			iface_count++;
++		}
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++	return iface_count;
++}
++
++#ifdef WBTEXT
++static bool wl_cfg80211_wbtext_check_bssid_list(struct bcm_cfg80211 *cfg, struct ether_addr *ea)
++{
++	wl_wbtext_bssid_t *bssid = NULL;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++
++	/* check duplicate */
++	list_for_each_entry(bssid, &cfg->wbtext_bssid_list, list) {
++		if (!memcmp(bssid->ea.octet, ea, ETHER_ADDR_LEN)) {
++			return FALSE;
++		}
++	}
++
++	return TRUE;
++}
++
++static bool wl_cfg80211_wbtext_add_bssid_list(struct bcm_cfg80211 *cfg, struct ether_addr *ea)
++{
++	wl_wbtext_bssid_t *bssid = NULL;
++	char eabuf[ETHER_ADDR_STR_LEN];
++
++	bssid = kmalloc(sizeof(wl_wbtext_bssid_t), GFP_KERNEL);
++	if (bssid == NULL) {
++		WL_ERR(("alloc failed\n"));
++		return FALSE;
++	}
++
++	memcpy(bssid->ea.octet, ea, ETHER_ADDR_LEN);
++
++	INIT_LIST_HEAD(&bssid->list);
++	list_add_tail(&bssid->list, &cfg->wbtext_bssid_list);
++
++	WL_DBG(("add wbtext bssid : %s\n", bcm_ether_ntoa(ea, eabuf)));
++
++	return TRUE;
++}
++
++static void wl_cfg80211_wbtext_clear_bssid_list(struct bcm_cfg80211 *cfg)
++{
++	wl_wbtext_bssid_t *bssid = NULL;
++	char eabuf[ETHER_ADDR_STR_LEN];
++
++	while (!list_empty(&cfg->wbtext_bssid_list)) {
++		bssid = list_entry(cfg->wbtext_bssid_list.next, wl_wbtext_bssid_t, list);
++		if (bssid) {
++			WL_DBG(("clear wbtext bssid : %s\n", bcm_ether_ntoa(&bssid->ea, eabuf)));
++			list_del(&bssid->list);
++			kfree(bssid);
++		}
++	}
++}
++
++static void wl_cfg80211_wbtext_update_rcc(struct bcm_cfg80211 *cfg, struct net_device *dev)
++{
++	struct wl_connect_info *conn_info = wl_to_conn(cfg);
++	bcm_tlv_t * cap_ie = NULL;
++	bool req_sent = FALSE;
++	struct wl_profile *profile;
++
++	WL_DBG(("Enter\n"));
++
++	profile = wl_get_profile_by_netdev(cfg, dev);
++	if (!profile) {
++		WL_ERR(("no profile exists\n"));
++		return;
++	}
++
++	if (wl_cfg80211_wbtext_check_bssid_list(cfg,
++			(struct ether_addr *)&profile->bssid) == FALSE) {
++		WL_DBG(("already updated\n"));
++		return;
++	}
++
++	/* first, check NBR bit in RRM IE */
++	if ((cap_ie = bcm_parse_tlvs(conn_info->resp_ie, conn_info->resp_ie_len,
++			DOT11_MNG_RRM_CAP_ID)) != NULL) {
++		if (isset(cap_ie->data, DOT11_RRM_CAP_NEIGHBOR_REPORT)) {
++			req_sent = wl_cfg80211_wbtext_send_nbr_req(cfg, dev, profile);
++		}
++	}
++
++	/* if RRM nbr was not supported, check BTM bit in extend cap. IE */
++	if (!req_sent) {
++		if ((cap_ie = bcm_parse_tlvs(conn_info->resp_ie, conn_info->resp_ie_len,
++				DOT11_MNG_EXT_CAP_ID)) != NULL) {
++			if (cap_ie->len >= DOT11_EXTCAP_LEN_BSSTRANS &&
++					isset(cap_ie->data, DOT11_EXT_CAP_BSSTRANS_MGMT)) {
++				wl_cfg80211_wbtext_send_btm_query(cfg, dev, profile);
++			}
++		}
++	}
++}
++
++static bool wl_cfg80211_wbtext_send_nbr_req(struct bcm_cfg80211 *cfg, struct net_device *dev,
++	struct wl_profile *profile)
++{
++	int error = -1;
++	char *smbuf = NULL;
++	struct wl_connect_info *conn_info = wl_to_conn(cfg);
++	bcm_tlv_t * rrm_cap_ie = NULL;
++	wlc_ssid_t *ssid = NULL;
++	bool ret = FALSE;
++
++	WL_DBG(("Enter\n"));
++
++	/* check RRM nbr bit in extend cap. IE of assoc response */
++	if ((rrm_cap_ie = bcm_parse_tlvs(conn_info->resp_ie, conn_info->resp_ie_len,
++			DOT11_MNG_RRM_CAP_ID)) != NULL) {
++		if (!isset(rrm_cap_ie->data, DOT11_RRM_CAP_NEIGHBOR_REPORT)) {
++			WL_DBG(("AP doesn't support neighbor report\n"));
++			return FALSE;
++		}
++	}
++
++	smbuf = (char *) kmalloc(WLC_IOCTL_MAXLEN, GFP_KERNEL);
++	if (smbuf == NULL) {
++		WL_ERR(("failed to allocated memory\n"));
++		goto nbr_req_out;
++	}
++
++	ssid = (wlc_ssid_t *) kzalloc(sizeof(wlc_ssid_t), GFP_KERNEL);
++	if (ssid == NULL) {
++		WL_ERR(("failed to allocated memory\n"));
++		goto nbr_req_out;
++	}
++
++	ssid->SSID_len = MIN(profile->ssid.SSID_len, DOT11_MAX_SSID_LEN);
++	memcpy(ssid->SSID, profile->ssid.SSID, ssid->SSID_len);
++
++	error = wldev_iovar_setbuf(dev, "rrm_nbr_req", ssid,
++		sizeof(wlc_ssid_t), smbuf, WLC_IOCTL_MAXLEN, NULL);
++	if (error == BCME_OK) {
++		ret = wl_cfg80211_wbtext_add_bssid_list(cfg,
++			(struct ether_addr *)&profile->bssid);
++	} else {
++		WL_ERR(("failed to send neighbor report request, error=%d\n", error));
++	}
++
++nbr_req_out:
++	if (ssid) {
++		kfree(ssid);
++	}
++
++	if (smbuf) {
++		kfree(smbuf);
++	}
++	return ret;
++}
++
++static bool wl_cfg80211_wbtext_send_btm_query(struct bcm_cfg80211 *cfg, struct net_device *dev,
++	struct wl_profile *profile)
++
++{
++	int error = -1;
++	bool ret = FALSE;
++
++	WL_DBG(("Enter\n"));
++
++	error = wldev_iovar_setbuf(dev, "wnm_bsstrans_query", NULL,
++		0, cfg->ioctl_buf, WLC_IOCTL_SMLEN, &cfg->ioctl_buf_sync);
++	if (error == BCME_OK) {
++		ret = wl_cfg80211_wbtext_add_bssid_list(cfg,
++			(struct ether_addr *)&profile->bssid);
++	} else {
++		WL_ERR(("%s: failed to set BTM query, error=%d\n", __FUNCTION__, error));
++	}
++	return ret;
++}
++
++static void wl_cfg80211_wbtext_set_wnm_maxidle(struct bcm_cfg80211 *cfg, struct net_device *dev)
++{
++	keepalives_max_idle_t keepalive = {0, 0, 0, 0};
++	s32 bssidx, error;
++	int wnm_maxidle = 0;
++	struct wl_connect_info *conn_info = wl_to_conn(cfg);
++
++	/* AP supports wnm max idle ? */
++	if (bcm_parse_tlvs(conn_info->resp_ie, conn_info->resp_ie_len,
++			DOT11_MNG_BSS_MAX_IDLE_PERIOD_ID) != NULL) {
++		error = wldev_iovar_getint(dev, "wnm_maxidle", &wnm_maxidle);
++		if (error < 0) {
++			WL_ERR(("failed to get wnm max idle period : %d\n", error));
++		}
++	}
++
++	WL_DBG(("wnm max idle period : %d\n", wnm_maxidle));
++
++	/* if wnm maxidle has valid period, set it as keep alive */
++	if (wnm_maxidle > 0) {
++		keepalive.keepalive_count = 1;
++	}
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) >= 0) {
++		error = wldev_iovar_setbuf_bsscfg(dev, "wnm_keepalives_max_idle", &keepalive,
++			sizeof(keepalives_max_idle_t), cfg->ioctl_buf, WLC_IOCTL_SMLEN,
++			bssidx, &cfg->ioctl_buf_sync);
++		if (error < 0) {
++			WL_ERR(("set wnm_keepalives_max_idle failed : %d\n", error));
++		}
++	}
++}
++
++static int
++wl_cfg80211_recv_nbr_resp(struct net_device *dev, uint8 *body, int body_len)
++{
++	dot11_rm_action_t *rm_rep;
++	bcm_tlv_t *tlvs;
++	int tlv_len, i, error;
++	dot11_neighbor_rep_ie_t *nbr_rep_ie;
++	chanspec_t ch;
++	wl_roam_channel_list_t channel_list;
++	char iobuf[WLC_IOCTL_SMLEN];
++
++	if (body_len < DOT11_RM_ACTION_LEN) {
++		WL_ERR(("Received Neighbor Report frame with incorrect length %d\n",
++			body_len));
++		return BCME_ERROR;
++	}
++
++	rm_rep = (dot11_rm_action_t *)body;
++	WL_DBG(("received neighbor report (token = %d)\n", rm_rep->token));
++
++	tlvs = (bcm_tlv_t *)&rm_rep->data[0];
++
++	tlv_len = body_len - DOT11_RM_ACTION_LEN;
++
++	while (tlvs && tlvs->id == DOT11_MNG_NEIGHBOR_REP_ID) {
++		nbr_rep_ie = (dot11_neighbor_rep_ie_t *)tlvs;
++
++		if (nbr_rep_ie->len < DOT11_NEIGHBOR_REP_IE_FIXED_LEN) {
++			WL_ERR(("malformed Neighbor Report element with length %d\n",
++				nbr_rep_ie->len));
++			tlvs = bcm_next_tlv(tlvs, &tlv_len);
++			continue;
++		}
++
++		ch = CH20MHZ_CHSPEC(nbr_rep_ie->channel);
++		WL_DBG(("ch:%d, bssid:%02x:%02x:%02x:%02x:%02x:%02x\n",
++			ch, nbr_rep_ie->bssid.octet[0], nbr_rep_ie->bssid.octet[1],
++			nbr_rep_ie->bssid.octet[2],	nbr_rep_ie->bssid.octet[3],
++			nbr_rep_ie->bssid.octet[4],	nbr_rep_ie->bssid.octet[5]));
++
++		/* get RCC list */
++		error = wldev_iovar_getbuf(dev, "roamscan_channels", 0, 0,
++			(void *)&channel_list, sizeof(channel_list), NULL);
++		if (error) {
++			WL_ERR(("Failed to get roamscan channels, error = %d\n", error));
++			return BCME_ERROR;
++		}
++
++		/* update RCC */
++		if (channel_list.n < MAX_ROAM_CHANNEL) {
++			for (i = 0; i < channel_list.n; i++) {
++				if (channel_list.channels[i] == ch) {
++					break;
++				}
++			}
++			if (i == channel_list.n) {
++				channel_list.channels[channel_list.n] = ch;
++				channel_list.n++;
++			}
++		}
++
++		/* set RCC list */
++		error = wldev_iovar_setbuf(dev, "roamscan_channels", &channel_list,
++			sizeof(channel_list), iobuf, sizeof(iobuf), NULL);
++		if (error) {
++			WL_DBG(("Failed to set roamscan channels, error = %d\n", error));
++		}
++
++		tlvs = bcm_next_tlv(tlvs, &tlv_len);
++	}
++
++	return BCME_OK;
++}
++#endif /* WBTEXT */
++
++#ifdef SUPPORT_SET_CAC
++static void
++wl_cfg80211_set_cac(struct bcm_cfg80211 *cfg, int enable)
++{
++	int ret = 0;
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++
++	WL_DBG(("cac enable %d, op_mode 0x%04x\n", enable, dhd->op_mode));
++	if (!dhd) {
++		WL_ERR(("dhd is NULL\n"));
++		return;
++	}
++	if (enable && ((dhd->op_mode & DHD_FLAG_HOSTAP_MODE) ||
++			(dhd->op_mode & DHD_FLAG_P2P_GC_MODE) ||
++			(dhd->op_mode & DHD_FLAG_P2P_GO_MODE))) {
++		WL_ERR(("op_mode 0x%04x\n", dhd->op_mode));
++		enable = 0;
++	}
++	if ((ret = dhd_wl_ioctl_set_intiovar(dhd, "cac", enable,
++			WLC_SET_VAR, TRUE, 0)) < 0) {
++		WL_ERR(("Failed set CAC, ret=%d\n", ret));
++	} else {
++		WL_DBG(("CAC set successfully\n"));
++	}
++	return;
++}
++#endif /* SUPPORT_SET_CAC */
++
++#ifdef SUPPORT_RSSI_LOGGING
++int
++wl_get_rssi_per_ant(struct net_device *dev, char *ifname, char *peer_mac, void *param)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	wl_rssi_ant_mimo_t *get_param = (wl_rssi_ant_mimo_t *)param;
++	rssi_ant_param_t *set_param = NULL;
++	struct net_device *ifdev = NULL;
++	char iobuf[WLC_IOCTL_SMLEN];
++	int err = BCME_OK;
++	int iftype = 0;
++
++	memset(iobuf, 0, WLC_IOCTL_SMLEN);
++
++	/* Check the interface type */
++	ifdev = wl_get_netdev_by_name(cfg, ifname);
++	if (ifdev == NULL) {
++		WL_ERR(("Could not find net_device for ifname:%s\n", ifname));
++		err = BCME_BADARG;
++		goto fail;
++	}
++
++	iftype = ifdev->ieee80211_ptr->iftype;
++	if (iftype == NL80211_IFTYPE_AP || iftype == NL80211_IFTYPE_P2P_GO) {
++		if (peer_mac) {
++			set_param = (rssi_ant_param_t *)kzalloc(sizeof(rssi_ant_param_t),
++				GFP_KERNEL);
++			err = wl_cfg80211_ether_atoe(peer_mac, &set_param->ea);
++			if (!err) {
++				WL_ERR(("Invalid Peer MAC format\n"));
++				err = BCME_BADARG;
++				goto fail;
++			}
++		} else {
++			WL_ERR(("Peer MAC is not provided for iftype %d\n", iftype));
++			err = BCME_BADARG;
++			goto fail;
++		}
++	}
++
++	err = wldev_iovar_getbuf(ifdev, "phy_rssi_ant", peer_mac ?
++		(void *)&(set_param->ea) : NULL, peer_mac ? ETHER_ADDR_LEN : 0,
++		(void *)iobuf, sizeof(iobuf), NULL);
++	if (unlikely(err)) {
++		WL_ERR(("Failed to get rssi info, err=%d\n", err));
++	} else {
++		memcpy(get_param, iobuf, sizeof(wl_rssi_ant_mimo_t));
++		if (get_param->count == 0) {
++			WL_ERR(("Not supported on this chip\n"));
++			err = BCME_UNSUPPORTED;
++		}
++	}
++
++fail:
++	if (set_param) {
++		kfree(set_param);
++	}
++
++	return err;
++}
++
++int
++wl_get_rssi_logging(struct net_device *dev, void *param)
++{
++	rssilog_get_param_t *get_param = (rssilog_get_param_t *)param;
++	char iobuf[WLC_IOCTL_SMLEN];
++	int err = BCME_OK;
++
++	memset(iobuf, 0, WLC_IOCTL_SMLEN);
++	memset(get_param, 0, sizeof(*get_param));
++	err = wldev_iovar_getbuf(dev, "rssilog", NULL, 0, (void *)iobuf,
++		sizeof(iobuf), NULL);
++	if (err) {
++		WL_ERR(("Failed to get rssi logging info, err=%d\n", err));
++	} else {
++		memcpy(get_param, iobuf, sizeof(*get_param));
++	}
++
++	return err;
++}
++
++int
++wl_set_rssi_logging(struct net_device *dev, void *param)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	rssilog_set_param_t *set_param = (rssilog_set_param_t *)param;
++	int err;
++
++	err = wldev_iovar_setbuf(dev, "rssilog", set_param,
++		sizeof(*set_param), cfg->ioctl_buf, WLC_IOCTL_SMLEN,
++		&cfg->ioctl_buf_sync);
++	if (err) {
++		WL_ERR(("Failed to set rssi logging param, err=%d\n", err));
++	}
++
++	return err;
++}
++#endif /* SUPPORT_RSSI_LOGGING */
++
++s32
++wl_cfg80211_autochannel(struct net_device *dev, char* command, int total_len)
++{
++	struct bcm_cfg80211 *cfg = wl_get_cfg(dev);
++	int ret = 0;
++	int bytes_written = -1;
++
++	sscanf(command, "%*s %d", &cfg->autochannel);
++
++	if (cfg->autochannel == 0) {
++		cfg->best_2g_ch = 0;
++		cfg->best_5g_ch = 0;
++	} else if (cfg->autochannel == 2) {
++		bytes_written = snprintf(command, total_len, "2g=%d 5g=%d",
++			cfg->best_2g_ch, cfg->best_5g_ch);
++		WL_TRACE(("%s: command result is %s\n", __FUNCTION__, command));
++		ret = bytes_written;
++	}
++
++	return ret;
++}
++
++static int
++wl_cfg80211_check_in4way(struct bcm_cfg80211 *cfg,
++	struct net_device *dev, uint action, enum wl_ext_status status, void *context)
++{
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++	struct wl_security *sec;
++	s32 bssidx = -1;
++	int ret = 0, cur_eapol_status, ifidx;
++	int max_wait_time, max_wait_cnt;
++	int suppressed = 0;
++
++	mutex_lock(&cfg->in4way_sync);
++	action = action & dhdp->conf->in4way;
++	WL_DBG(("status=%d, action=0x%x, in4way=0x%x\n", status, action, dhdp->conf->in4way));
++
++	cur_eapol_status = dhdp->conf->eapol_status;
++	switch (status) {
++		case WL_EXT_STATUS_SCAN:
++			wldev_ioctl(dev, WLC_GET_SCANSUPPRESS, &suppressed, sizeof(int), false);
++			if (suppressed) {
++				WL_ERR(("scan suppressed\n"));
++				ret = -EBUSY;
++				break;
++			}
++			if (action & NO_SCAN_IN4WAY) {
++				if (cfg->handshaking > 0 && cfg->handshaking <= 3) {
++					WL_ERR(("return -EBUSY cnt %d\n", cfg->handshaking));
++					cfg->handshaking++;
++					ret = -EBUSY;
++					break;
++				}
++			}
++			break;
++ 		case WL_EXT_STATUS_DISCONNECTING:
++			if (cur_eapol_status >= EAPOL_STATUS_4WAY_START &&
++					cur_eapol_status < EAPOL_STATUS_4WAY_DONE) {
++				WL_ERR(("WPA failed at %d\n", cur_eapol_status));
++				dhdp->conf->eapol_status = EAPOL_STATUS_NONE;
++			} else if (cur_eapol_status >= EAPOL_STATUS_WSC_START &&
++					cur_eapol_status < EAPOL_STATUS_WSC_DONE) {
++				WL_ERR(("WPS failed at %d\n", cur_eapol_status));
++				dhdp->conf->eapol_status = EAPOL_STATUS_NONE;
++			}
++			if (action & (NO_SCAN_IN4WAY|NO_BTC_IN4WAY)) {
++				if (cfg->handshaking) {
++					if ((action & NO_BTC_IN4WAY) && cfg->btc_mode) {
++						WL_TRACE(("status=%d, restore btc_mode %d\n",
++							status, cfg->btc_mode));
++						wldev_iovar_setint(dev, "btc_mode", cfg->btc_mode);
++					}
++					cfg->handshaking = 0;
++				}
++			}
++			if (action & WAIT_DISCONNECTED) {
++				max_wait_time = 200;
++				max_wait_cnt = 20;
++				cfg->disconnected_jiffies = jiffies;
++				while (!time_after(jiffies,
++						cfg->disconnected_jiffies + msecs_to_jiffies(max_wait_time)) &&
++						max_wait_cnt) {
++					WL_TRACE(("status=%d, max_wait_cnt=%d waiting...\n",
++						status, max_wait_cnt));
++					mutex_unlock(&cfg->in4way_sync);
++					OSL_SLEEP(50);
++					mutex_lock(&cfg->in4way_sync);
++					max_wait_cnt--;
++				}
++				wake_up_interruptible(&dhdp->conf->event_complete);
++			}
++			break;
++		case WL_EXT_STATUS_CONNECTING:
++			if (action & (NO_SCAN_IN4WAY|NO_BTC_IN4WAY)) {
++				bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr);
++				sec = wl_read_prof(cfg, dev, WL_PROF_SEC);
++				if ((sec->wpa_versions & (NL80211_WPA_VERSION_1 | NL80211_WPA_VERSION_2)) &&
++						bssidx == 0) {
++					dhdp->conf->eapol_status = EAPOL_STATUS_4WAY_START;
++					cfg->handshaking = 1;
++					if (action & NO_BTC_IN4WAY) {
++						ret = wldev_iovar_getint(dev, "btc_mode", &cfg->btc_mode);
++						if (!ret && cfg->btc_mode) {
++							WL_TRACE(("status=%d, disable current btc_mode %d\n",
++								status, cfg->btc_mode));
++							wldev_iovar_setint(dev, "btc_mode", 0);
++						}
++					}
++				}
++			}
++			if (action & WAIT_DISCONNECTED) {
++				max_wait_time = 200;
++				max_wait_cnt = 10;
++				while (!time_after(jiffies,
++						cfg->disconnected_jiffies + msecs_to_jiffies(max_wait_time)) &&
++						max_wait_cnt) {
++					WL_TRACE(("status=%d, max_wait_cnt=%d waiting...\n",
++						status, max_wait_cnt));
++					mutex_unlock(&cfg->in4way_sync);
++					OSL_SLEEP(50);
++					mutex_lock(&cfg->in4way_sync);
++					max_wait_cnt--;
++				}
++				wake_up_interruptible(&dhdp->conf->event_complete);
++			}
++			break;
++		case WL_EXT_STATUS_CONNECTED:
++			ifidx = dhd_net2idx(dhdp->info, dev);
++			if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_STATION && ifidx >= 0) {
++				dhd_conf_set_wme(cfg->pub, ifidx, 0);
++				wake_up_interruptible(&dhdp->conf->event_complete);
++			}
++			else if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_P2P_CLIENT) {
++				dhd_conf_set_mchan_bw(cfg->pub, WL_P2P_IF_CLIENT, -1);
++			}
++			break;
++		case WL_EXT_STATUS_DISCONNECTED:
++			if (cur_eapol_status >= EAPOL_STATUS_4WAY_START &&
++					cur_eapol_status < EAPOL_STATUS_4WAY_DONE) {
++				WL_ERR(("WPA failed at %d\n", cur_eapol_status));
++				dhdp->conf->eapol_status = EAPOL_STATUS_NONE;
++			} else if (cur_eapol_status >= EAPOL_STATUS_WSC_START &&
++					cur_eapol_status < EAPOL_STATUS_WSC_DONE) {
++				WL_ERR(("WPS failed at %d\n", cur_eapol_status));
++				dhdp->conf->eapol_status = EAPOL_STATUS_NONE;
++			}
++			if (action & (NO_SCAN_IN4WAY|NO_BTC_IN4WAY)) {
++				if (cfg->handshaking) {
++					if ((action & NO_BTC_IN4WAY) && cfg->btc_mode) {
++						WL_TRACE(("status=%d, restore btc_mode %d\n",
++							status, cfg->btc_mode));
++						wldev_iovar_setint(dev, "btc_mode", cfg->btc_mode);
++					}
++					cfg->handshaking = 0;
++				}
++			}
++			if (action & WAIT_DISCONNECTED) {
++				cfg->disconnected_jiffies = jiffies;
++			}
++			wake_up_interruptible(&dhdp->conf->event_complete);
++			break;
++		case WL_EXT_STATUS_ADD_KEY:
++			dhdp->conf->eapol_status = EAPOL_STATUS_4WAY_DONE;
++			if (action & (NO_SCAN_IN4WAY|NO_BTC_IN4WAY)) {
++				if (cfg->handshaking) {
++					if ((action & NO_BTC_IN4WAY) && cfg->btc_mode) {
++						WL_TRACE(("status=%d, restore btc_mode %d\n",
++							status, cfg->btc_mode));
++						wldev_iovar_setint(dev, "btc_mode", cfg->btc_mode);
++					}
++					cfg->handshaking = 0;
++				}
++			}
++			wake_up_interruptible(&dhdp->conf->event_complete);
++			break;
++		case WL_EXT_STATUS_AP_ENABLED:
++			ifidx = dhd_net2idx(dhdp->info, dev);
++			if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_AP && ifidx >= 0) {
++				dhd_conf_set_wme(cfg->pub, ifidx, 1);
++			}
++			else if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_P2P_GO) {
++				dhd_conf_set_mchan_bw(cfg->pub, WL_P2P_IF_GO, -1);
++			}
++			break;
++		case WL_EXT_STATUS_DELETE_STA:
++			if ((action & DONT_DELETE_GC_AFTER_WPS) &&
++					(dev->ieee80211_ptr->iftype == NL80211_IFTYPE_P2P_GO)) {
++				u8* mac_addr = context;
++				if (mac_addr && memcmp(&ether_bcast, mac_addr, ETHER_ADDR_LEN) &&
++						cur_eapol_status == EAPOL_STATUS_WSC_DONE) {
++					u32 timeout;
++					max_wait_time = 300;
++					WL_TRACE(("status=%d, wps_done=%d, waiting %dms ...\n",
++						status, cfg->wps_done, max_wait_time));
++					mutex_unlock(&cfg->in4way_sync);
++					timeout = wait_event_interruptible_timeout(cfg->wps_done_event,
++						cfg->wps_done, msecs_to_jiffies(max_wait_time));
++					mutex_lock(&cfg->in4way_sync);
++					WL_TRACE(("status=%d, wps_done=%d, timeout=%d\n",
++						status, cfg->wps_done, timeout));
++					if (timeout > 0) {
++						ret = -1;
++						break;
++					}
++				} else {
++					WL_TRACE(("status=%d, wps_done=%d => 0\n", status, cfg->wps_done));
++					cfg->wps_done = FALSE;
++					dhdp->conf->eapol_status = EAPOL_STATUS_NONE;
++				}
++			}
++			break;
++		case WL_EXT_STATUS_STA_DISCONNECTED:
++			if ((action & DONT_DELETE_GC_AFTER_WPS) &&
++					(dev->ieee80211_ptr->iftype == NL80211_IFTYPE_P2P_GO) &&
++					cur_eapol_status == EAPOL_STATUS_WSC_DONE) {
++				WL_TRACE(("status=%d, wps_done=%d => 0\n", status, cfg->wps_done));
++				cfg->wps_done = FALSE;
++			}
++			break;
++		case WL_EXT_STATUS_STA_CONNECTED:
++			if ((action & DONT_DELETE_GC_AFTER_WPS) &&
++					(dev->ieee80211_ptr->iftype == NL80211_IFTYPE_P2P_GO) &&
++					cur_eapol_status == EAPOL_STATUS_WSC_DONE) {
++				WL_TRACE(("status=%d, wps_done=%d => 1\n", status, cfg->wps_done));
++				cfg->wps_done = TRUE;
++				wake_up_interruptible(&cfg->wps_done_event);
++			}
++			break;
++		default:
++			WL_ERR(("Unknown action=0x%x, status=%d\n", action, status));
++	}
++
++	mutex_unlock(&cfg->in4way_sync);
++
++	return ret;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_cfg80211.h b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfg80211.h
+new file mode 100644
+index 000000000..979bf22ae
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfg80211.h
+@@ -0,0 +1,1742 @@
++/*
++ * Linux cfg80211 driver
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfg80211.h 710862 2017-07-14 07:43:59Z $
++ */
++
++/**
++ * Older Linux versions support the 'iw' interface, more recent ones the 'cfg80211' interface.
++ */
++
++#ifndef _wl_cfg80211_h_
++#define _wl_cfg80211_h_
++
++#include <linux/wireless.h>
++#include <typedefs.h>
++#include <ethernet.h>
++#include <wlioctl.h>
++#include <linux/wireless.h>
++#include <net/cfg80211.h>
++#include <linux/rfkill.h>
++
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <wl_cfgp2p.h>
++#include <wl_android.h>
++struct wl_conf;
++struct wl_iface;
++struct bcm_cfg80211;
++struct wl_security;
++struct wl_ibss;
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)
++#undef WL_SAE
++#endif // endif
++
++#define htod32(i) (i)
++#define htod16(i) (i)
++#define dtoh64(i) (i)
++#define dtoh32(i) (i)
++#define dtoh16(i) (i)
++#define htodchanspec(i) (i)
++#define dtohchanspec(i) (i)
++
++#define WL_DBG_NONE	0
++#define WL_DBG_P2P_ACTION	(1 << 5)
++#define WL_DBG_TRACE	(1 << 4)
++#define WL_DBG_SCAN	(1 << 3)
++#define WL_DBG_DBG	(1 << 2)
++#define WL_DBG_INFO	(1 << 1)
++#define WL_DBG_ERR	(1 << 0)
++
++#ifdef DHD_LOG_DUMP
++extern void dhd_log_dump_write(int type, const char *fmt, ...);
++extern char *dhd_log_dump_get_timestamp(void);
++#ifndef _DHD_LOG_DUMP_DEFINITIONS_
++#define DLD_BUF_TYPE_GENERAL    0
++#define DLD_BUF_TYPE_SPECIAL    1
++#define DHD_LOG_DUMP_WRITE(fmt, ...)	dhd_log_dump_write(DLD_BUF_TYPE_GENERAL, fmt, ##__VA_ARGS__)
++#define DHD_LOG_DUMP_WRITE_EX(fmt, ...)	dhd_log_dump_write(DLD_BUF_TYPE_SPECIAL, fmt, ##__VA_ARGS__)
++#endif /* !_DHD_LOG_DUMP_DEFINITIONS_ */
++#endif /* DHD_LOG_DUMP */
++
++/* 0 invalidates all debug messages.  default is 1 */
++#define WL_DBG_LEVEL 0xFF
++
++#ifdef CUSTOMER_HW4_DEBUG
++#define CFG80211_ERROR_TEXT		"[dhd] CFG80211-INFO2) "
++#else
++#define CFG80211_ERROR_TEXT		"[dhd] CFG80211-ERROR) "
++#endif /* CUSTOMER_HW4_DEBUG */
++
++#if defined(DHD_DEBUG)
++#ifdef DHD_LOG_DUMP
++#define	WL_ERR_MSG(x, args...)	\
++do {	\
++	if (wl_dbg_level & WL_DBG_ERR) {	\
++		printk(KERN_INFO CFG80211_ERROR_TEXT "%s : " x, __func__, ## args);	\
++		DHD_LOG_DUMP_WRITE("[%s] %s: ", dhd_log_dump_get_timestamp(), __func__);	\
++		DHD_LOG_DUMP_WRITE(x, ## args);	\
++	}	\
++} while (0)
++#define	WL_ERR_MEM(args)	\
++do {	\
++	if (wl_dbg_level & WL_DBG_ERR) {	\
++		DHD_LOG_DUMP_WRITE("[%s] %s: ", dhd_log_dump_get_timestamp(), __func__);	\
++		DHD_LOG_DUMP_WRITE(x, ## args);	\
++	}	\
++} while (0)
++#define	WL_ERR_EX_MSG(x, args...)	\
++do {	\
++	if (wl_dbg_level & WL_DBG_ERR) {	\
++		printk(KERN_INFO CFG80211_ERROR_TEXT "%s : " x, __func__, ## args);	\
++		DHD_LOG_DUMP_WRITE_EX("[%s] %s: ", dhd_log_dump_get_timestamp(), __func__); \
++		DHD_LOG_DUMP_WRITE_EX(x, ## args); \
++	}	\
++} while (0)
++#define WL_ERR(x) WL_ERR_MSG x
++#define WL_ERR_EX(args) WL_ERR_EX_MSG(args)
++#else
++#define	WL_ERR_MSG(x, args...)									\
++do {										\
++	if (wl_dbg_level & WL_DBG_ERR) {				\
++		printk(KERN_INFO CFG80211_ERROR_TEXT "%s : " x, __func__, ## args);	\
++	}								\
++} while (0)
++#define WL_ERR(x) WL_ERR_MSG x
++#define WL_ERR_MEM(args) WL_ERR(args)
++#define WL_ERR_EX(args) WL_ERR(args)
++#endif /* DHD_LOG_DUMP */
++#else /* defined(DHD_DEBUG) */
++#define	WL_ERR_MSG(x, args...)									\
++do {										\
++	if ((wl_dbg_level & WL_DBG_ERR) && net_ratelimit()) {				\
++		printk(KERN_INFO CFG80211_ERROR_TEXT "%s : " x, __func__, ## args);	\
++	}								\
++} while (0)
++#define WL_ERR(x) WL_ERR_MSG x
++#define WL_ERR_MEM(args) WL_ERR(args)
++#define WL_ERR_EX(args) WL_ERR(args)
++#endif /* defined(DHD_DEBUG) */
++
++#define WL_PRINT_RATE_LIMIT_PERIOD 4000000000u /* 4s in units of ns */
++#define WL_ERR_RLMT(args) \
++do {	\
++	if (wl_dbg_level & WL_DBG_ERR) {	\
++		static uint64 __err_ts = 0; \
++		static uint32 __err_cnt = 0; \
++		uint64 __cur_ts = 0; \
++		__cur_ts = local_clock(); \
++		if (__err_ts == 0 || (__cur_ts > __err_ts && \
++		(__cur_ts - __err_ts > WL_PRINT_RATE_LIMIT_PERIOD))) { \
++			__err_ts = __cur_ts; \
++			WL_ERR(args);	\
++			WL_ERR(("[Repeats %u times]\n", __err_cnt)); \
++			__err_cnt = 0; \
++		} else { \
++			++__err_cnt; \
++		} \
++	}	\
++} while (0)
++
++#ifdef WL_INFORM
++#undef WL_INFORM
++#endif
++
++#define	WL_INFORM_MSG(x, args...)									\
++do {										\
++	if (wl_dbg_level & WL_DBG_INFO) {				\
++		printk(KERN_INFO "[dhd] CFG80211-INFO) %s : " x, __func__, ## args);	\
++	}								\
++} while (0)
++#define WL_INFORM(x) WL_INFORM_MSG x
++
++#ifdef WL_SCAN
++#undef WL_SCAN
++#endif
++#define	WL_SCAN_MSG(x, args...)								\
++do {									\
++	if (wl_dbg_level & WL_DBG_SCAN) {			\
++		printk(KERN_INFO "[dhd] CFG80211-SCAN) %s :" x, __func__, ## args);	\
++	}									\
++} while (0)
++#define WL_SCAN(x) WL_SCAN_MSG x
++#ifdef WL_TRACE
++#undef WL_TRACE
++#endif
++#define	WL_TRACE_MSG(x, args...)								\
++do {									\
++	if (wl_dbg_level & WL_DBG_TRACE) {			\
++		printk(KERN_INFO "[dhd] CFG80211-TRACE) %s :" x, __func__, ## args);	\
++	}									\
++} while (0)
++#define WL_TRACE(x) WL_TRACE_MSG x
++#ifdef WL_TRACE_HW4
++#undef WL_TRACE_HW4
++#endif
++#ifdef CUSTOMER_HW4_DEBUG
++#define	WL_TRACE_HW4_MSG(x, args...)					\
++do {										\
++	if (wl_dbg_level & WL_DBG_ERR) {				\
++		printk(KERN_INFO "[dhd] CFG80211-TRACE) %s : " x, __func__, ## args);	\
++	} 								\
++} while (0)
++#define WL_TRACE_HW4(x) WL_TRACE_HW4_MSG x
++#else
++#define	WL_TRACE_HW4			WL_TRACE
++#endif /* CUSTOMER_HW4_DEBUG */
++#if (WL_DBG_LEVEL > 0)
++#define	WL_DBG_MSG(x, args...)								\
++do {									\
++	if (wl_dbg_level & WL_DBG_DBG) {			\
++		printk(KERN_INFO "[dhd] CFG80211-DEBUG) %s :" x, __func__, ## args);	\
++	}									\
++} while (0)
++#define WL_DBG(x) WL_DBG_MSG x
++#else				/* !(WL_DBG_LEVEL > 0) */
++#define	WL_DBG(args)
++#endif				/* (WL_DBG_LEVEL > 0) */
++#define WL_PNO(x)
++#define WL_SD(x)
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))
++#define ieee80211_band nl80211_band
++#define IEEE80211_BAND_2GHZ NL80211_BAND_2GHZ
++#define IEEE80211_BAND_5GHZ NL80211_BAND_5GHZ
++#define IEEE80211_NUM_BANDS NUM_NL80211_BANDS
++#endif
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
++#ifdef WLMESH_CFG80211
++#undef WLMESH_CFG80211
++#endif
++#endif
++
++#define WL_SCAN_RETRY_MAX	3
++#define WL_NUM_PMKIDS_MAX	MAXPMKID
++#define WL_SCAN_BUF_MAX 	(1024 * 8)
++#define WL_TLV_INFO_MAX 	1500
++#define WL_SCAN_IE_LEN_MAX      2048
++#define WL_BSS_INFO_MAX		2048
++#define WL_ASSOC_INFO_MAX	512
++#define WL_IOCTL_LEN_MAX	2048
++#define WL_EXTRA_BUF_MAX	2048
++#define WL_SCAN_ERSULTS_LAST 	(WL_SCAN_RESULTS_NO_MEM+1)
++#define WL_AP_MAX			256
++#define WL_FILE_NAME_MAX	256
++#define WL_DWELL_TIME		200
++#define WL_MED_DWELL_TIME	400
++#define WL_MIN_DWELL_TIME	100
++#define WL_LONG_DWELL_TIME	1000
++#define IFACE_MAX_CNT	4
++#define WL_SCAN_CONNECT_DWELL_TIME_MS		200
++#define WL_SCAN_JOIN_PROBE_INTERVAL_MS		20
++#define WL_SCAN_JOIN_ACTIVE_DWELL_TIME_MS	320
++#define WL_SCAN_JOIN_PASSIVE_DWELL_TIME_MS	400
++#define WL_AF_TX_MAX_RETRY	5
++
++#define WL_AF_SEARCH_TIME_MAX		450
++#define WL_AF_TX_EXTRA_TIME_MAX		200
++
++#define WL_SCAN_TIMER_INTERVAL_MS	10000 /* Scan timeout */
++#define WL_CHANNEL_SYNC_RETRY 	5
++#define WL_INVALID 		-1
++
++#ifdef DHD_LOSSLESS_ROAMING
++#define WL_ROAM_TIMEOUT_MS	1000 /* Roam timeout */
++#endif
++/* Bring down SCB Timeout to 20secs from 60secs default */
++#ifndef WL_SCB_TIMEOUT
++#define WL_SCB_TIMEOUT	20
++#endif
++
++#ifndef WL_SCB_ACTIVITY_TIME
++#define WL_SCB_ACTIVITY_TIME	5
++#endif
++
++#ifndef WL_SCB_MAX_PROBE
++#define WL_SCB_MAX_PROBE	3
++#endif
++
++#ifndef WL_MIN_PSPRETEND_THRESHOLD
++#define WL_MIN_PSPRETEND_THRESHOLD	2
++#endif
++
++/* Cipher suites */
++#define WLAN_CIPHER_SUITE_PMK		0x00904C00
++
++#ifndef WLAN_AKM_SUITE_FT_8021X
++#define WLAN_AKM_SUITE_FT_8021X		0x000FAC03
++#endif /* WLAN_AKM_SUITE_FT_8021X */
++
++#ifndef WLAN_AKM_SUITE_FT_PSK
++#define WLAN_AKM_SUITE_FT_PSK		0x000FAC04
++#endif /* WLAN_AKM_SUITE_FT_PSK */
++
++/*
++ * BRCM local.
++ * Use a high number that's unlikely to clash with linux upstream for a while until we can
++ * submit these changes to the community.
++*/
++#define NL80211_FEATURE_FW_4WAY_HANDSHAKE (1<<31)
++
++/* SCAN_SUPPRESS timer values in ms */
++#define WL_SCAN_SUPPRESS_TIMEOUT 31000 /* default Framwork DHCP timeout is 30 sec */
++#define WL_SCAN_SUPPRESS_RETRY 3000
++
++#define WL_PM_ENABLE_TIMEOUT 10000
++
++/* cfg80211 wowlan definitions */
++#define WL_WOWLAN_MAX_PATTERNS			8
++#define WL_WOWLAN_MIN_PATTERN_LEN		1
++#define WL_WOWLAN_MAX_PATTERN_LEN		255
++#define WL_WOWLAN_PKT_FILTER_ID_FIRST	201
++#define WL_WOWLAN_PKT_FILTER_ID_LAST	(WL_WOWLAN_PKT_FILTER_ID_FIRST + \
++									WL_WOWLAN_MAX_PATTERNS - 1)
++
++#ifdef WLTDLS
++#define TDLS_TUNNELED_PRB_REQ	"\x7f\x50\x6f\x9a\04"
++#define TDLS_TUNNELED_PRB_RESP	"\x7f\x50\x6f\x9a\05"
++#define TDLS_MAX_IFACE_FOR_ENABLE 1
++#endif /* WLTDLS */
++
++
++/* driver status */
++enum wl_status {
++	WL_STATUS_READY = 0,
++	WL_STATUS_SCANNING,
++	WL_STATUS_SCAN_ABORTING,
++	WL_STATUS_CONNECTING,
++	WL_STATUS_CONNECTED,
++	WL_STATUS_DISCONNECTING,
++	WL_STATUS_AP_CREATING,
++	WL_STATUS_AP_CREATED,
++	/* whole sending action frame procedure:
++	 * includes a) 'finding common channel' for public action request frame
++	 * and b) 'sending af via 'actframe' iovar'
++	 */
++	WL_STATUS_SENDING_ACT_FRM,
++	/* find a peer to go to a common channel before sending public action req frame */
++	WL_STATUS_FINDING_COMMON_CHANNEL,
++	/* waiting for next af to sync time of supplicant.
++	 * it includes SENDING_ACT_FRM and WAITING_NEXT_ACT_FRM_LISTEN
++	 */
++	WL_STATUS_WAITING_NEXT_ACT_FRM,
++#ifdef WL_CFG80211_SYNC_GON
++	/* go to listen state to wait for next af after SENDING_ACT_FRM */
++	WL_STATUS_WAITING_NEXT_ACT_FRM_LISTEN,
++#endif /* WL_CFG80211_SYNC_GON */
++	/* it will be set when upper layer requests listen and succeed in setting listen mode.
++	 * if set, other scan request can abort current listen state
++	 */
++	WL_STATUS_REMAINING_ON_CHANNEL,
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++	/* it's fake listen state to keep current scan state.
++	 * it will be set when upper layer requests listen but scan is running. then just run
++	 * a expire timer without actual listen state.
++	 * if set, other scan request does not need to abort scan.
++	 */
++	WL_STATUS_FAKE_REMAINING_ON_CHANNEL,
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++	WL_STATUS_NESTED_CONNECT
++};
++
++/* wi-fi mode */
++enum wl_mode {
++	WL_MODE_BSS,
++	WL_MODE_IBSS,
++	WL_MODE_AP,
++#ifdef WLMESH_CFG80211
++	WL_MODE_MESH
++#endif
++};
++
++/* driver profile list */
++enum wl_prof_list {
++	WL_PROF_MODE,
++	WL_PROF_SSID,
++	WL_PROF_SEC,
++	WL_PROF_IBSS,
++	WL_PROF_BAND,
++	WL_PROF_CHAN,
++	WL_PROF_BSSID,
++	WL_PROF_ACT,
++	WL_PROF_BEACONINT,
++	WL_PROF_DTIMPERIOD
++};
++
++/* donlge escan state */
++enum wl_escan_state {
++	WL_ESCAN_STATE_IDLE,
++	WL_ESCAN_STATE_SCANING
++};
++/* fw downloading status */
++enum wl_fw_status {
++	WL_FW_LOADING_DONE,
++	WL_NVRAM_LOADING_DONE
++};
++
++enum wl_management_type {
++	WL_BEACON = 0x1,
++	WL_PROBE_RESP = 0x2,
++	WL_ASSOC_RESP = 0x4
++};
++
++enum wl_pm_workq_act_type {
++	WL_PM_WORKQ_SHORT,
++	WL_PM_WORKQ_LONG,
++	WL_PM_WORKQ_DEL
++};
++
++enum wl_tdls_config {
++    TDLS_STATE_AP_CREATE,
++    TDLS_STATE_AP_DELETE,
++    TDLS_STATE_CONNECT,
++    TDLS_STATE_DISCONNECT,
++    TDLS_STATE_SETUP,
++    TDLS_STATE_TEARDOWN,
++    TDLS_STATE_IF_CREATE,
++    TDLS_STATE_IF_DELETE
++};
++
++/* beacon / probe_response */
++struct beacon_proberesp {
++	__le64 timestamp;
++	__le16 beacon_int;
++	__le16 capab_info;
++	u8 variable[0];
++} __attribute__ ((packed));
++
++/* driver configuration */
++struct wl_conf {
++	u32 frag_threshold;
++	u32 rts_threshold;
++	u32 retry_short;
++	u32 retry_long;
++	s32 tx_power;
++	struct ieee80211_channel channel;
++};
++
++typedef s32(*EVENT_HANDLER) (struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++                            const wl_event_msg_t *e, void *data);
++
++/* bss inform structure for cfg80211 interface */
++struct wl_cfg80211_bss_info {
++	u16 band;
++	u16 channel;
++	s16 rssi;
++	u16 frame_len;
++	u8 frame_buf[1];
++};
++
++/* basic structure of scan request */
++struct wl_scan_req {
++	struct wlc_ssid ssid;
++};
++
++/* basic structure of information element */
++struct wl_ie {
++	u16 offset;
++	u8 buf[WL_TLV_INFO_MAX];
++};
++
++/* event queue for cfg80211 main event */
++struct wl_event_q {
++	struct list_head eq_list;
++	u32 etype;
++	wl_event_msg_t emsg;
++	s8 edata[1];
++};
++
++/* security information with currently associated ap */
++struct wl_security {
++	u32 wpa_versions;
++	u32 auth_type;
++	u32 cipher_pairwise;
++	u32 cipher_group;
++	u32 wpa_auth;
++	u32 auth_assoc_res_status;
++};
++
++/* ibss information for currently joined ibss network */
++struct wl_ibss {
++	u8 beacon_interval;	/* in millisecond */
++	u8 atim;		/* in millisecond */
++	s8 join_only;
++	u8 band;
++	u8 channel;
++};
++
++typedef struct wl_bss_vndr_ies {
++	u8  probe_req_ie[VNDR_IES_BUF_LEN];
++	u8  probe_res_ie[VNDR_IES_MAX_BUF_LEN];
++	u8  assoc_req_ie[VNDR_IES_BUF_LEN];
++	u8  assoc_res_ie[VNDR_IES_BUF_LEN];
++	u8  beacon_ie[VNDR_IES_MAX_BUF_LEN];
++	u32 probe_req_ie_len;
++	u32 probe_res_ie_len;
++	u32 assoc_req_ie_len;
++	u32 assoc_res_ie_len;
++	u32 beacon_ie_len;
++} wl_bss_vndr_ies_t;
++
++typedef struct wl_cfgbss {
++	u8 *wpa_ie;
++	u8 *rsn_ie;
++	u8 *wps_ie;
++	bool security_mode;
++	struct wl_bss_vndr_ies ies;	/* Common for STA, P2P GC, GO, AP, P2P Disc Interface */
++} wl_cfgbss_t;
++
++/* cfg driver profile */
++struct wl_profile {
++	u32 mode;
++	s32 band;
++	u32 channel;
++	struct wlc_ssid ssid;
++	struct wl_security sec;
++	struct wl_ibss ibss;
++	u8 bssid[ETHER_ADDR_LEN];
++	u16 beacon_interval;
++	u8 dtim_period;
++	bool active;
++};
++
++struct net_info {
++	struct net_device *ndev;
++	struct wireless_dev *wdev;
++	struct wl_profile profile;
++	s32 mode;
++	s32 roam_off;
++	unsigned long sme_state;
++	bool pm_restore;
++	bool pm_block;
++	s32 pm;
++	s32 bssidx;
++	wl_cfgbss_t bss;
++	u32 ulb_bw;
++	struct list_head list; /* list of all net_info structure */
++};
++
++/* association inform */
++#define MAX_REQ_LINE 1024
++struct wl_connect_info {
++	u8 req_ie[MAX_REQ_LINE];
++	s32 req_ie_len;
++	u8 resp_ie[MAX_REQ_LINE];
++	s32 resp_ie_len;
++};
++
++/* firmware /nvram downloading controller */
++struct wl_fw_ctrl {
++	const struct firmware *fw_entry;
++	unsigned long status;
++	u32 ptr;
++	s8 fw_name[WL_FILE_NAME_MAX];
++	s8 nvram_name[WL_FILE_NAME_MAX];
++};
++
++/* assoc ie length */
++struct wl_assoc_ielen {
++	u32 req_len;
++	u32 resp_len;
++};
++
++/* wpa2 pmk list */
++struct wl_pmk_list {
++	pmkid_list_t pmkids;
++	pmkid_t foo[MAXPMKID - 1];
++};
++
++#ifdef DHD_MAX_IFS
++#define WL_MAX_IFS DHD_MAX_IFS
++#else
++#define WL_MAX_IFS 16
++#endif
++
++#define ESCAN_BUF_SIZE (64 * 1024)
++
++struct escan_info {
++	u32 escan_state;
++#ifdef STATIC_WL_PRIV_STRUCT
++#ifndef CONFIG_DHD_USE_STATIC_BUF
++#error STATIC_WL_PRIV_STRUCT should be used with CONFIG_DHD_USE_STATIC_BUF
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++	u8 *escan_buf;
++#else
++	u8 escan_buf[ESCAN_BUF_SIZE];
++#endif /* STATIC_WL_PRIV_STRUCT */
++	struct wiphy *wiphy;
++	struct net_device *ndev;
++};
++
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++#define BUF_OVERFLOW_MGMT_COUNT 3
++typedef struct {
++	int RSSI;
++	int length;
++	struct ether_addr BSSID;
++} removal_element_t;
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++
++struct afx_hdl {
++	wl_af_params_t *pending_tx_act_frm;
++	struct ether_addr	tx_dst_addr;
++	struct net_device *dev;
++	struct work_struct work;
++	s32 bssidx;
++	u32 retry;
++	s32 peer_chan;
++	s32 peer_listen_chan; /* search channel: configured by upper layer */
++	s32 my_listen_chan;	/* listen chanel: extract it from prb req or gon req */
++	bool is_listen;
++	bool ack_recv;
++	bool is_active;
++};
++
++struct parsed_ies {
++	wpa_ie_fixed_t *wps_ie;
++	u32 wps_ie_len;
++	wpa_ie_fixed_t *wpa_ie;
++	u32 wpa_ie_len;
++	bcm_tlv_t *wpa2_ie;
++	u32 wpa2_ie_len;
++};
++
++
++#ifdef P2P_LISTEN_OFFLOADING
++typedef struct {
++	uint16	period;                 /* listen offload period */
++	uint16	interval;               /* listen offload interval */
++	uint16	count;			/* listen offload count */
++	uint16	pad;                    /* pad for 32bit align */
++} wl_p2plo_listen_t;
++#endif /* P2P_LISTEN_OFFLOADING */
++
++#ifdef WL11U
++/* Max length of Interworking element */
++#define IW_IES_MAX_BUF_LEN 		9
++#endif
++#ifdef WLFBT
++#define FBT_KEYLEN		32
++#endif
++#define MAX_EVENT_BUF_NUM 16
++typedef struct wl_eventmsg_buf {
++	u16 num;
++	struct {
++		u16 type;
++		bool set;
++	} event [MAX_EVENT_BUF_NUM];
++} wl_eventmsg_buf_t;
++
++typedef struct wl_if_event_info {
++	bool valid;
++	int ifidx;
++	int bssidx;
++	uint8 mac[ETHER_ADDR_LEN];
++	char name[IFNAMSIZ+1];
++	uint8 role;
++} wl_if_event_info;
++
++
++#ifdef SUPPORT_AP_RADIO_PWRSAVE
++typedef struct ap_rps_info {
++	bool enable;
++	bool sta_assoc_check;
++	int pps;
++	int quiet_time;
++	int level;
++} ap_rps_info_t;
++#endif /* SUPPORT_AP_RADIO_PWRSAVE */
++
++#ifdef SUPPORT_RSSI_LOGGING
++#define RSSILOG_FLAG_FEATURE_SW		0x1
++#define RSSILOG_FLAG_REPORT_READY	0x2
++typedef struct rssilog_set_param {
++	uint8 enable;
++	uint8 rssi_threshold;
++	uint8 time_threshold;
++	uint8 pad;
++} rssilog_set_param_t;
++
++typedef struct rssilog_get_param {
++	uint8 report_count;
++	uint8 enable;
++	uint8 rssi_threshold;
++	uint8 time_threshold;
++} rssilog_get_param_t;
++
++typedef struct rssi_ant_param {
++	struct ether_addr ea;
++	chanspec_t chanspec;
++} rssi_ant_param_t;
++
++typedef struct wl_rssi_ant_mimo {
++	uint32 version;
++	uint32 count;
++	int8 rssi_ant[WL_RSSI_ANT_MAX];
++	int8 rssi_sum;
++	int8 PAD[3];
++} wl_rssi_ant_mimo_t;
++#endif /* SUPPORT_RSSI_LOGGING */
++
++#if defined(DHD_ENABLE_BIGDATA_LOGGING)
++#define GET_BSS_INFO_LEN 90
++#endif /* DHD_ENABLE_BIGDATA_LOGGING */
++
++
++/* private data of cfg80211 interface */
++struct bcm_cfg80211 {
++	struct wireless_dev *wdev;	/* representing cfg cfg80211 device */
++
++	struct wireless_dev *p2p_wdev;	/* representing cfg cfg80211 device for P2P */
++	struct net_device *p2p_net;    /* reference to p2p0 interface */
++
++	struct wl_conf *conf;
++	struct cfg80211_scan_request *scan_request;	/* scan request object */
++	EVENT_HANDLER evt_handler[WLC_E_LAST];
++	struct list_head eq_list;	/* used for event queue */
++	struct list_head net_list;     /* used for struct net_info */
++	spinlock_t net_list_sync;	/* to protect scan status (and others if needed) */
++	spinlock_t eq_lock;	/* for event queue synchronization */
++	spinlock_t cfgdrv_lock;	/* to protect scan status (and others if needed) */
++	struct completion act_frm_scan;
++	struct completion iface_disable;
++	struct completion wait_next_af;
++	struct mutex usr_sync;	/* maily for up/down synchronization */
++	struct mutex if_sync;	/* maily for iface op synchronization */
++	struct mutex scan_complete;	/* serialize scan_complete call */
++	struct wl_scan_results *bss_list;
++	struct wl_scan_results *scan_results;
++
++	/* scan request object for internal purpose */
++	struct wl_scan_req *scan_req_int;
++	/* information element object for internal purpose */
++#if defined(STATIC_WL_PRIV_STRUCT)
++	struct wl_ie *ie;
++#else
++	struct wl_ie ie;
++#endif
++
++	/* association information container */
++#if defined(STATIC_WL_PRIV_STRUCT)
++	struct wl_connect_info *conn_info;
++#else
++	struct wl_connect_info conn_info;
++#endif
++#ifdef DEBUGFS_CFG80211
++	struct dentry		*debugfs;
++#endif /* DEBUGFS_CFG80211 */
++	struct wl_pmk_list *pmk_list;	/* wpa2 pmk list */
++	tsk_ctl_t event_tsk;  		/* task of main event handler thread */
++	dhd_pub_t *pub;
++	u32 iface_cnt;
++	u32 channel;		/* current channel */
++	u32 af_sent_channel;	/* channel action frame is sent */
++	/* next af subtype to cancel the remained dwell time in rx process */
++	u8 next_af_subtype;
++#ifdef WL_CFG80211_SYNC_GON
++	ulong af_tx_sent_jiffies;
++#endif /* WL_CFG80211_SYNC_GON */
++	struct escan_info escan_info;   /* escan information */
++	bool active_scan;	/* current scan mode */
++	bool ibss_starter;	/* indicates this sta is ibss starter */
++	bool link_up;		/* link/connection up flag */
++
++	/* indicate whether chip to support power save mode */
++	bool pwr_save;
++	bool roam_on;		/* on/off switch for self-roaming */
++	bool scan_tried;	/* indicates if first scan attempted */
++#if defined(BCMSDIO) || defined(BCMDBUS)
++	bool wlfc_on;
++#endif 
++	bool vsdb_mode;
++#define WL_ROAM_OFF_ON_CONCURRENT 	0x0001
++#define WL_ROAM_REVERT_STATUS		0x0002
++	u32 roam_flags;
++	u8 *ioctl_buf;		/* ioctl buffer */
++	struct mutex ioctl_buf_sync;
++	u8 *escan_ioctl_buf;
++	u8 *extra_buf;	/* maily to grab assoc information */
++	struct dentry *debugfsdir;
++	struct rfkill *rfkill;
++	bool rf_blocked;
++	struct ieee80211_channel remain_on_chan;
++	enum nl80211_channel_type remain_on_chan_type;
++	u64 send_action_id;
++	u64 last_roc_id;
++	wait_queue_head_t netif_change_event;
++	wl_if_event_info if_event_info;
++	struct completion send_af_done;
++	struct afx_hdl *afx_hdl;
++	struct p2p_info *p2p;
++	bool p2p_supported;
++	void *btcoex_info;
++	timer_list_compat_t scan_timeout;   /* Timer for catch scan event timeout */
++#if defined(P2P_IE_MISSING_FIX)
++	bool p2p_prb_noti;
++#endif
++	s32(*state_notifier) (struct bcm_cfg80211 *cfg,
++		struct net_info *_net_info, enum wl_status state, bool set);
++	unsigned long interrested_state;
++	wlc_ssid_t hostapd_ssid;
++#ifdef WL11U
++	bool wl11u;
++#endif /* WL11U */
++	bool sched_scan_running;	/* scheduled scan req status */
++	struct cfg80211_sched_scan_request *sched_scan_req;	/* scheduled scan req */
++	bool scan_suppressed;
++	timer_list_compat_t scan_supp_timer;
++	struct work_struct wlan_work;
++	struct mutex event_sync;	/* maily for up/down synchronization */
++	bool disable_roam_event;
++	struct delayed_work pm_enable_work;
++	struct workqueue_struct *event_workq;   /* workqueue for event */
++	struct work_struct event_work;		/* work item for event */
++	struct mutex pm_sync;	/* mainly for pm work synchronization */
++
++	vndr_ie_setbuf_t *ibss_vsie;	/* keep the VSIE for IBSS */
++	int ibss_vsie_len;
++#ifdef WL_RELMCAST
++	u32 rmc_event_pid;
++	u32 rmc_event_seq;
++#endif /* WL_RELMCAST */
++#ifdef WLAIBSS_MCHAN
++	struct ether_addr ibss_if_addr;
++	bcm_struct_cfgdev *ibss_cfgdev; /* For AIBSS */
++#endif /* WLAIBSS_MCHAN */
++	bool bss_pending_op;		/* indicate where there is a pending IF operation */
++#ifdef WLFBT
++	uint8 fbt_key[FBT_KEYLEN];
++#endif
++	int roam_offload;
++#ifdef WL_CFG80211_P2P_DEV_IF
++	bool down_disc_if;
++#endif /* WL_CFG80211_P2P_DEV_IF */
++#ifdef P2PLISTEN_AP_SAMECHN
++	bool p2p_resp_apchn_status;
++#endif /* P2PLISTEN_AP_SAMECHN */
++	struct wl_wsec_key wep_key;
++#ifdef WLTDLS
++	u8 *tdls_mgmt_frame;
++	u32 tdls_mgmt_frame_len;
++	s32 tdls_mgmt_freq;
++#endif /* WLTDLS */
++	bool need_wait_afrx;
++#ifdef QOS_MAP_SET
++	uint8	 *up_table;	/* user priority table, size is UP_TABLE_MAX */
++#endif /* QOS_MAP_SET */
++	struct ether_addr last_roamed_addr;
++	bool rcc_enabled;	/* flag for Roam channel cache feature */
++#if defined(DHD_ENABLE_BIGDATA_LOGGING)
++	char bss_info[GET_BSS_INFO_LEN];
++	wl_event_msg_t event_auth_assoc;
++	u32 assoc_reject_status;
++	u32 roam_count;
++#endif /* DHD_ENABLE_BIGDATA_LOGGING */
++	u16 ap_oper_channel;
++#if defined(SUPPORT_RANDOM_MAC_SCAN)
++	bool random_mac_enabled;
++#endif /* SUPPORT_RANDOM_MAC_SCAN */
++#ifdef DHD_LOSSLESS_ROAMING
++	timer_list_compat_t roam_timeout;   /* Timer for catch roam timeout */
++#endif
++	uint16 escan_sync_id_cntr;
++#ifdef WLTDLS
++	uint8 tdls_supported;
++	struct mutex tdls_sync;	/* protect tdls config operations */
++#endif /* WLTDLS */
++#ifdef MFP
++	uint8 *bip_pos;
++	int mfp_mode;
++#endif /* MFP */
++#ifdef SUPPORT_AP_RADIO_PWRSAVE
++	ap_rps_info_t ap_rps_info;
++#endif /* SUPPORT_AP_RADIO_PWRSAVE */
++#ifdef WBTEXT
++	struct list_head wbtext_bssid_list;
++#endif /* WBTEXT */
++	struct list_head vndr_oui_list;
++
++#ifdef STAT_REPORT
++	void *stat_report_info;
++#endif
++#ifdef WLMESH_CFG80211
++	char sae_password[SAE_MAX_PASSWD_LEN];
++	uint sae_password_len;
++#endif /* WLMESH_CFG80211 */
++#if defined(RSSIAVG)
++	wl_rssi_cache_ctrl_t g_rssi_cache_ctrl;
++	wl_rssi_cache_ctrl_t g_connected_rssi_cache_ctrl;
++#endif
++#if defined(BSSCACHE)
++	wl_bss_cache_ctrl_t g_bss_cache_ctrl;
++#endif
++	int p2p_disconnected; // terence 20130703: Fix for wrong group_capab (timing issue)
++	struct ether_addr disconnected_bssid;
++	int autochannel;
++	int best_2g_ch;
++	int best_5g_ch;
++	uint handshaking;
++	int btc_mode;
++	bool wps_done;
++	wait_queue_head_t wps_done_event;
++	struct mutex in4way_sync;
++	ulong disconnected_jiffies;
++};
++
++#ifdef WL_SAE
++typedef struct wl_sae_key_info {
++	uint8 peer_mac[ETHER_ADDR_LEN];
++	uint16 pmk_len;
++	uint16 pmkid_len;
++	const uint8 *pmk;
++	const uint8 *pmkid;
++} wl_sae_key_info_t;
++#endif /* WL_SAE */
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++#define GCC_DIAGNOSTIC_PUSH() \
++_Pragma("GCC diagnostic push") \
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#define GCC_DIAGNOSTIC_POP() \
++_Pragma("GCC diagnostic pop")
++#else
++#define GCC_DIAGNOSTIC_PUSH()
++#define GCC_DIAGNOSTIC_POP()
++#endif /* STRICT_GCC_WARNINGS */
++
++#define BCM_LIST_FOR_EACH_ENTRY_SAFE(pos, next, head, member) \
++	list_for_each_entry_safe((pos), (next), (head), member)
++extern int ioctl_version;
++
++static inline struct wl_bss_info *next_bss(struct wl_scan_results *list, struct wl_bss_info *bss)
++{
++	return bss = bss ?
++		(struct wl_bss_info *)((uintptr) bss + dtoh32(bss->length)) : list->bss_info;
++}
++
++static inline void
++wl_probe_wdev_all(struct bcm_cfg80211 *cfg)
++{
++	struct net_info *_net_info, *next;
++	unsigned long int flags;
++	int idx = 0;
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	GCC_DIAGNOSTIC_PUSH();
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next,
++		&cfg->net_list, list) {
++		WL_ERR(("%s: net_list[%d] bssidx: %d, "
++			"ndev: %p, wdev: %p \n", __FUNCTION__,
++			idx++, _net_info->bssidx,
++			_net_info->ndev, _net_info->wdev));
++	}
++	GCC_DIAGNOSTIC_POP();
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return;
++}
++
++static inline struct net_info *
++wl_get_netinfo_by_bssidx(struct bcm_cfg80211 *cfg, s32 bssidx)
++{
++	struct net_info *_net_info, *next, *info = NULL;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	GCC_DIAGNOSTIC_PUSH();
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if ((bssidx >= 0) && (_net_info->bssidx == bssidx)) {
++			info = _net_info;
++			break;
++		}
++	}
++	GCC_DIAGNOSTIC_POP();
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return info;
++}
++
++static inline void
++wl_dealloc_netinfo_by_wdev(struct bcm_cfg80211 *cfg, struct wireless_dev *wdev)
++{
++	struct net_info *_net_info, *next;
++	unsigned long int flags;
++
++#ifdef DHD_IFDEBUG
++	WL_ERR(("dealloc_netinfo enter wdev=%p \n", wdev));
++#endif
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	GCC_DIAGNOSTIC_PUSH();
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (wdev && (_net_info->wdev == wdev)) {
++			wl_cfgbss_t *bss = &_net_info->bss;
++
++			kfree(bss->wpa_ie);
++			bss->wpa_ie = NULL;
++			kfree(bss->rsn_ie);
++			bss->rsn_ie = NULL;
++			kfree(bss->wps_ie);
++			bss->wps_ie = NULL;
++			list_del(&_net_info->list);
++			cfg->iface_cnt--;
++			kfree(_net_info);
++		}
++	}
++	GCC_DIAGNOSTIC_POP();
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++#ifdef DHD_IFDEBUG
++	WL_ERR(("dealloc_netinfo exit iface_cnt=%d \n", cfg->iface_cnt));
++#endif
++}
++
++static inline s32
++wl_alloc_netinfo(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	struct wireless_dev * wdev, s32 mode, bool pm_block, u8 bssidx)
++{
++	struct net_info *_net_info;
++	s32 err = 0;
++	unsigned long int flags;
++#ifdef DHD_IFDEBUG
++	WL_ERR(("alloc_netinfo enter bssidx=%d wdev=%p ndev=%p\n", bssidx, wdev, ndev));
++#endif
++	/* Check whether there is any duplicate entry for the
++	 *  same bssidx *
++	 */
++	if ((_net_info = wl_get_netinfo_by_bssidx(cfg, bssidx))) {
++		/* We have a duplicate entry for the same bssidx
++		 * already present which shouldn't have been the case.
++		 * Attempt recovery.
++		 */
++		WL_ERR(("Duplicate entry for bssidx=%d present\n", bssidx));
++		wl_probe_wdev_all(cfg);
++#ifdef DHD_DEBUG
++		ASSERT(0);
++#endif /* DHD_DEBUG */
++		WL_ERR(("Removing the Dup entry for bssidx=%d \n", bssidx));
++		wl_dealloc_netinfo_by_wdev(cfg, _net_info->wdev);
++	}
++	if (cfg->iface_cnt == IFACE_MAX_CNT)
++		return -ENOMEM;
++	_net_info = kzalloc(sizeof(struct net_info), GFP_KERNEL);
++	if (!_net_info)
++		err = -ENOMEM;
++	else {
++		_net_info->mode = mode;
++		_net_info->ndev = ndev;
++		_net_info->wdev = wdev;
++		_net_info->pm_restore = 0;
++		_net_info->pm = 0;
++		_net_info->pm_block = pm_block;
++		_net_info->roam_off = WL_INVALID;
++		_net_info->bssidx = bssidx;
++		spin_lock_irqsave(&cfg->net_list_sync, flags);
++		cfg->iface_cnt++;
++		list_add(&_net_info->list, &cfg->net_list);
++		spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	}
++#ifdef DHD_IFDEBUG
++	WL_ERR(("alloc_netinfo exit iface_cnt=%d \n", cfg->iface_cnt));
++#endif
++	return err;
++}
++
++static inline void
++wl_delete_all_netinfo(struct bcm_cfg80211 *cfg)
++{
++	struct net_info *_net_info, *next;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	GCC_DIAGNOSTIC_PUSH();
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		wl_cfgbss_t *bss = &_net_info->bss;
++
++		kfree(bss->wpa_ie);
++		bss->wpa_ie = NULL;
++		kfree(bss->rsn_ie);
++		bss->rsn_ie = NULL;
++		kfree(bss->wps_ie);
++		bss->wps_ie = NULL;
++		list_del(&_net_info->list);
++		if (_net_info->wdev)
++			kfree(_net_info->wdev);
++		kfree(_net_info);
++	}
++	cfg->iface_cnt = 0;
++	GCC_DIAGNOSTIC_POP();
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++}
++static inline u32
++wl_get_status_all(struct bcm_cfg80211 *cfg, s32 status)
++
++{
++	struct net_info *_net_info, *next;
++	u32 cnt = 0;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	GCC_DIAGNOSTIC_PUSH();
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (_net_info->ndev &&
++			test_bit(status, &_net_info->sme_state))
++			cnt++;
++	}
++	GCC_DIAGNOSTIC_POP();
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return cnt;
++}
++static inline void
++wl_set_status_all(struct bcm_cfg80211 *cfg, s32 status, u32 op)
++{
++	struct net_info *_net_info, *next;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	GCC_DIAGNOSTIC_PUSH();
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		switch (op) {
++			case 1:
++				break; /* set all status is not allowed */
++			case 2:
++				/*
++				 * Release the spinlock before calling notifier. Else there
++				 * will be nested calls
++				 */
++				spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++				clear_bit(status, &_net_info->sme_state);
++				if (cfg->state_notifier &&
++					test_bit(status, &(cfg->interrested_state)))
++					cfg->state_notifier(cfg, _net_info, status, false);
++				return;
++			case 4:
++				break; /* change all status is not allowed */
++			default:
++				break; /* unknown operation */
++		}
++	}
++	GCC_DIAGNOSTIC_POP();
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++}
++static inline void
++wl_set_status_by_netdev(struct bcm_cfg80211 *cfg, s32 status,
++	struct net_device *ndev, u32 op)
++{
++
++	struct net_info *_net_info, *next;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	GCC_DIAGNOSTIC_PUSH();
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (ndev && (_net_info->ndev == ndev)) {
++			switch (op) {
++				case 1:
++					/*
++					 * Release the spinlock before calling notifier. Else there
++					 * will be nested calls
++					 */
++					spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++					set_bit(status, &_net_info->sme_state);
++					if (cfg->state_notifier &&
++						test_bit(status, &(cfg->interrested_state)))
++						cfg->state_notifier(cfg, _net_info, status, true);
++					return;
++				case 2:
++					/*
++					 * Release the spinlock before calling notifier. Else there
++					 * will be nested calls
++					 */
++					spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++					clear_bit(status, &_net_info->sme_state);
++					if (cfg->state_notifier &&
++						test_bit(status, &(cfg->interrested_state)))
++						cfg->state_notifier(cfg, _net_info, status, false);
++					return;
++				case 4:
++					change_bit(status, &_net_info->sme_state);
++					break;
++			}
++		}
++
++	}
++	GCC_DIAGNOSTIC_POP();
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++
++}
++
++static inline wl_cfgbss_t *
++wl_get_cfgbss_by_wdev(struct bcm_cfg80211 *cfg,
++	struct wireless_dev *wdev)
++{
++	struct net_info *_net_info, *next;
++	wl_cfgbss_t *bss = NULL;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	GCC_DIAGNOSTIC_PUSH();
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (wdev && (_net_info->wdev == wdev)) {
++			bss = &_net_info->bss;
++			break;
++		}
++	}
++	GCC_DIAGNOSTIC_POP();
++
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return bss;
++}
++
++static inline u32
++wl_get_status_by_netdev(struct bcm_cfg80211 *cfg, s32 status,
++	struct net_device *ndev)
++{
++	struct net_info *_net_info, *next;
++	u32 stat = 0;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	GCC_DIAGNOSTIC_PUSH();
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (ndev && (_net_info->ndev == ndev)) {
++			stat = test_bit(status, &_net_info->sme_state);
++			break;
++		}
++	}
++	GCC_DIAGNOSTIC_POP();
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return stat;
++}
++
++static inline s32
++wl_get_mode_by_netdev(struct bcm_cfg80211 *cfg, struct net_device *ndev)
++{
++	struct net_info *_net_info, *next;
++	s32 mode = -1;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	GCC_DIAGNOSTIC_PUSH();
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (ndev && (_net_info->ndev == ndev)) {
++			mode = _net_info->mode;
++			break;
++		}
++	}
++	GCC_DIAGNOSTIC_POP();
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return mode;
++}
++
++static inline void
++wl_set_mode_by_netdev(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	s32 mode)
++{
++	struct net_info *_net_info, *next;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	GCC_DIAGNOSTIC_PUSH();
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (ndev && (_net_info->ndev == ndev))
++			_net_info->mode = mode;
++	}
++	GCC_DIAGNOSTIC_POP();
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++}
++
++static inline s32
++wl_get_bssidx_by_wdev(struct bcm_cfg80211 *cfg, struct wireless_dev *wdev)
++{
++	struct net_info *_net_info, *next;
++	s32 bssidx = -1;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	GCC_DIAGNOSTIC_PUSH();
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (_net_info->wdev && (_net_info->wdev == wdev)) {
++			bssidx = _net_info->bssidx;
++			break;
++		}
++	}
++	GCC_DIAGNOSTIC_POP();
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return bssidx;
++}
++
++static inline struct wireless_dev *
++wl_get_wdev_by_bssidx(struct bcm_cfg80211 *cfg, s32 bssidx)
++{
++	struct net_info *_net_info, *next;
++	struct wireless_dev *wdev = NULL;
++	unsigned long int flags;
++
++	if (bssidx < 0)
++		return NULL;
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	GCC_DIAGNOSTIC_PUSH();
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (_net_info->bssidx == bssidx) {
++			wdev = _net_info->wdev;
++			break;
++		}
++	}
++	GCC_DIAGNOSTIC_POP();
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return wdev;
++}
++
++static inline struct wl_profile *
++wl_get_profile_by_netdev(struct bcm_cfg80211 *cfg, struct net_device *ndev)
++{
++	struct net_info *_net_info, *next;
++	struct wl_profile *prof = NULL;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	GCC_DIAGNOSTIC_PUSH();
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (ndev && (_net_info->ndev == ndev)) {
++			prof = &_net_info->profile;
++			break;
++		}
++	}
++	GCC_DIAGNOSTIC_POP();
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return prof;
++}
++static inline struct net_info *
++wl_get_netinfo_by_netdev(struct bcm_cfg80211 *cfg, struct net_device *ndev)
++{
++	struct net_info *_net_info, *next, *info = NULL;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	GCC_DIAGNOSTIC_PUSH();
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (ndev && (_net_info->ndev == ndev)) {
++			info = _net_info;
++			break;
++		}
++	}
++	GCC_DIAGNOSTIC_POP();
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return info;
++}
++
++static inline struct net_info *
++wl_get_netinfo_by_wdev(struct bcm_cfg80211 *cfg, struct wireless_dev *wdev)
++{
++	struct net_info *_net_info, *next, *info = NULL;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	GCC_DIAGNOSTIC_PUSH();
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (wdev && (_net_info->wdev == wdev)) {
++			info = _net_info;
++			break;
++		}
++	}
++	GCC_DIAGNOSTIC_POP();
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return info;
++}
++
++#define is_p2p_group_iface(wdev) (((wdev->iftype == NL80211_IFTYPE_P2P_GO) || \
++		(wdev->iftype == NL80211_IFTYPE_P2P_CLIENT)) ? 1 : 0)
++#define bcmcfg_to_wiphy(cfg) (cfg->wdev->wiphy)
++#define bcmcfg_to_prmry_ndev(cfg) (cfg->wdev->netdev)
++#define bcmcfg_to_prmry_wdev(cfg) (cfg->wdev)
++#define bcmcfg_to_p2p_wdev(cfg) (cfg->p2p_wdev)
++#define ndev_to_wl(n) (wdev_to_wl(n->ieee80211_ptr))
++#define ndev_to_wdev(ndev) (ndev->ieee80211_ptr)
++#define wdev_to_ndev(wdev) (wdev->netdev)
++
++#if defined(WL_ENABLE_P2P_IF)
++#define ndev_to_wlc_ndev(ndev, cfg)	((ndev == cfg->p2p_net) ? \
++	bcmcfg_to_prmry_ndev(cfg) : ndev)
++#else
++#define ndev_to_wlc_ndev(ndev, cfg)	(ndev)
++#endif /* WL_ENABLE_P2P_IF */
++
++#define wdev_to_wlc_ndev(wdev, cfg)	\
++	(wdev_to_ndev(wdev) ? \
++	wdev_to_ndev(wdev) : bcmcfg_to_prmry_ndev(cfg))
++#if defined(WL_CFG80211_P2P_DEV_IF)
++#define cfgdev_to_wlc_ndev(cfgdev, cfg)	wdev_to_wlc_ndev(cfgdev, cfg)
++#define bcmcfg_to_prmry_cfgdev(cfgdev, cfg) bcmcfg_to_prmry_wdev(cfg)
++#elif defined(WL_ENABLE_P2P_IF)
++#define cfgdev_to_wlc_ndev(cfgdev, cfg)	ndev_to_wlc_ndev(cfgdev, cfg)
++#define bcmcfg_to_prmry_cfgdev(cfgdev, cfg) bcmcfg_to_prmry_ndev(cfg)
++#else
++#define cfgdev_to_wlc_ndev(cfgdev, cfg)	(cfgdev)
++#define bcmcfg_to_prmry_cfgdev(cfgdev, cfg) (cfgdev)
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++#define cfgdev_to_wdev(cfgdev)	(cfgdev)
++#define ndev_to_cfgdev(ndev)	ndev_to_wdev(ndev)
++#define cfgdev_to_ndev(cfgdev)	(cfgdev ? (cfgdev->netdev) : NULL)
++#define wdev_to_cfgdev(cfgdev)	(cfgdev)
++#define discover_cfgdev(cfgdev, cfg) (cfgdev->iftype == NL80211_IFTYPE_P2P_DEVICE)
++#else
++#define cfgdev_to_wdev(cfgdev)	(cfgdev->ieee80211_ptr)
++#define wdev_to_cfgdev(cfgdev)	cfgdev ? (cfgdev->netdev) : NULL
++#define ndev_to_cfgdev(ndev)	(ndev)
++#define cfgdev_to_ndev(cfgdev)	(cfgdev)
++#define discover_cfgdev(cfgdev, cfg) (cfgdev == cfg->p2p_net)
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++#define scan_req_match(cfg)	(((cfg) && (cfg->scan_request) && \
++	(cfg->scan_request->wdev == cfg->p2p_wdev)) ? true : false)
++#elif defined(WL_ENABLE_P2P_IF)
++#define scan_req_match(cfg)	(((cfg) && (cfg->scan_request) && \
++	(cfg->scan_request->dev == cfg->p2p_net)) ? true : false)
++#else
++#define scan_req_match(cfg)	(((cfg) && p2p_is_on(cfg) && p2p_scan(cfg)) ? \
++	true : false)
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++#define	PRINT_WDEV_INFO(cfgdev)	\
++	{ \
++		struct wireless_dev *wdev = cfgdev_to_wdev(cfgdev); \
++		struct net_device *netdev = wdev ? wdev->netdev : NULL; \
++		WL_DBG(("wdev_ptr:%p ndev_ptr:%p ifname:%s iftype:%d\n", wdev, netdev,	\
++			netdev ? netdev->name : "NULL (non-ndev device)",	\
++			wdev ? wdev->iftype : 0xff)); \
++	}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++#define scan_req_iftype(req) (req->dev->ieee80211_ptr->iftype)
++#else
++#define scan_req_iftype(req) (req->wdev->iftype)
++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0) */
++
++#define wl_to_sr(w) (w->scan_req_int)
++#if defined(STATIC_WL_PRIV_STRUCT)
++#define wl_to_ie(w) (w->ie)
++#define wl_to_conn(w) (w->conn_info)
++#else
++#define wl_to_ie(w) (&w->ie)
++#define wl_to_conn(w) (&w->conn_info)
++#endif
++#define wiphy_from_scan(w) (w->escan_info.wiphy)
++#define wl_get_drv_status_all(cfg, stat) \
++	(wl_get_status_all(cfg, WL_STATUS_ ## stat))
++#define wl_get_drv_status(cfg, stat, ndev)  \
++	(wl_get_status_by_netdev(cfg, WL_STATUS_ ## stat, ndev))
++#define wl_set_drv_status(cfg, stat, ndev)  \
++	(wl_set_status_by_netdev(cfg, WL_STATUS_ ## stat, ndev, 1))
++#define wl_clr_drv_status(cfg, stat, ndev)  \
++	(wl_set_status_by_netdev(cfg, WL_STATUS_ ## stat, ndev, 2))
++#define wl_clr_drv_status_all(cfg, stat)  \
++	(wl_set_status_all(cfg, WL_STATUS_ ## stat, 2))
++#define wl_chg_drv_status(cfg, stat, ndev)  \
++	(wl_set_status_by_netdev(cfg, WL_STATUS_ ## stat, ndev, 4))
++
++#define for_each_bss(list, bss, __i)	\
++	for (__i = 0; __i < list->count && __i < WL_AP_MAX; __i++, bss = next_bss(list, bss))
++
++#define for_each_ndev(cfg, iter, next) \
++	list_for_each_entry_safe(iter, next, &cfg->net_list, list)
++
++/* In case of WPS from wpa_supplicant, pairwise siute and group suite is 0.
++ * In addtion to that, wpa_version is WPA_VERSION_1
++ */
++#define is_wps_conn(_sme) \
++	((wl_cfgp2p_find_wpsie((u8 *)_sme->ie, _sme->ie_len) != NULL) && \
++	 (!_sme->crypto.n_ciphers_pairwise) && \
++	 (!_sme->crypto.cipher_group))
++
++#ifdef WLFBT
++#if defined(WLAN_AKM_SUITE_FT_8021X) && defined(WLAN_AKM_SUITE_FT_PSK)
++#define IS_AKM_SUITE_FT(sec) (sec->wpa_auth == WLAN_AKM_SUITE_FT_8021X || \
++		sec->wpa_auth == WLAN_AKM_SUITE_FT_PSK)
++#elif defined(WLAN_AKM_SUITE_FT_8021X)
++#define IS_AKM_SUITE_FT(sec) (sec->wpa_auth == WLAN_AKM_SUITE_FT_8021X)
++#elif defined(WLAN_AKM_SUITE_FT_PSK)
++#define IS_AKM_SUITE_FT(sec) (sec->wpa_auth == WLAN_AKM_SUITE_FT_PSK)
++#else
++#define IS_AKM_SUITE_FT(sec) ({BCM_REFERENCE(sec); FALSE;})
++#endif /* WLAN_AKM_SUITE_FT_8021X && WLAN_AKM_SUITE_FT_PSK */
++#else
++#define IS_AKM_SUITE_FT(sec) ({BCM_REFERENCE(sec); FALSE;})
++#endif /* WLFBT */
++
++#define IS_AKM_SUITE_CCKM(sec) ({BCM_REFERENCE(sec); FALSE;})
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
++#define STA_INFO_BIT(info) (1ul << NL80211_STA_ ## info)
++#ifdef strnicmp
++#undef strnicmp
++#endif /* strnicmp */
++#define strnicmp(str1, str2, len) strncasecmp((str1), (str2), (len))
++#else
++#define STA_INFO_BIT(info) (STATION_ ## info)
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) */
++
++extern s32 wl_cfg80211_attach(struct net_device *ndev, void *context);
++extern void wl_cfg80211_detach(struct bcm_cfg80211 *cfg);
++
++extern void wl_cfg80211_event(struct net_device *ndev, const wl_event_msg_t *e,
++            void *data);
++void wl_cfg80211_set_parent_dev(void *dev);
++struct device *wl_cfg80211_get_parent_dev(void);
++
++/* clear IEs */
++extern s32 wl_cfg80211_clear_mgmt_vndr_ies(struct bcm_cfg80211 *cfg);
++extern s32 wl_cfg80211_clear_per_bss_ies(struct bcm_cfg80211 *cfg, s32 bssidx);
++
++extern s32 wl_cfg80211_up(struct net_device *net);
++extern s32 wl_cfg80211_down(struct net_device *net);
++extern s32 wl_cfg80211_notify_ifadd(struct net_device * dev, int ifidx, char *name, uint8 *mac,
++	uint8 bssidx);
++extern s32 wl_cfg80211_notify_ifdel(struct net_device * dev, int ifidx, char *name, uint8 *mac,
++	uint8 bssidx);
++extern s32 wl_cfg80211_notify_ifchange(struct net_device * dev, int ifidx, char *name, uint8 *mac,
++	uint8 bssidx);
++extern struct net_device* wl_cfg80211_allocate_if(struct bcm_cfg80211 *cfg, int ifidx,
++	const char *name, uint8 *mac, uint8 bssidx, const char *dngl_name);
++extern int wl_cfg80211_register_if(struct bcm_cfg80211 *cfg,
++	int ifidx, struct net_device* ndev, bool rtnl_lock_reqd);
++extern int wl_cfg80211_remove_if(struct bcm_cfg80211 *cfg,
++	int ifidx, struct net_device* ndev, bool rtnl_lock_reqd);
++extern int wl_cfg80211_scan_stop(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev);
++extern void wl_cfg80211_scan_abort(struct bcm_cfg80211 *cfg);
++extern bool wl_cfg80211_is_concurrent_mode(struct net_device * dev);
++extern void* wl_cfg80211_get_dhdp(struct net_device * dev);
++extern bool wl_cfg80211_is_p2p_active(struct net_device * dev);
++extern bool wl_cfg80211_is_roam_offload(struct net_device * dev);
++extern bool wl_cfg80211_is_event_from_connected_bssid(struct net_device * dev,
++		const wl_event_msg_t *e, int ifidx);
++extern void wl_cfg80211_dbg_level(u32 level);
++extern s32 wl_cfg80211_get_p2p_dev_addr(struct net_device *net, struct ether_addr *p2pdev_addr);
++extern s32 wl_cfg80211_set_p2p_noa(struct net_device *net, char* buf, int len);
++extern s32 wl_cfg80211_get_p2p_noa(struct net_device *net, char* buf, int len);
++extern s32 wl_cfg80211_set_wps_p2p_ie(struct net_device *net, char *buf, int len,
++	enum wl_management_type type);
++extern s32 wl_cfg80211_set_p2p_ps(struct net_device *net, char* buf, int len);
++extern s32 wl_cfg80211_set_p2p_ecsa(struct net_device *net, char* buf, int len);
++extern s32 wl_cfg80211_increase_p2p_bw(struct net_device *net, char* buf, int len);
++#ifdef WLMESH_CFG80211
++extern s32 wl_cfg80211_set_sae_password(struct net_device *net, char* buf, int len);
++#endif
++#ifdef WL11ULB
++extern s32 wl_cfg80211_set_ulb_mode(struct net_device *dev, int mode);
++extern s32 wl_cfg80211_set_ulb_bw(struct net_device *dev,
++	u32 ulb_bw,  char *ifname);
++#endif /* WL11ULB */
++#ifdef P2PLISTEN_AP_SAMECHN
++extern s32 wl_cfg80211_set_p2p_resp_ap_chn(struct net_device *net, s32 enable);
++#endif /* P2PLISTEN_AP_SAMECHN */
++
++/* btcoex functions */
++void* wl_cfg80211_btcoex_init(struct net_device *ndev);
++void wl_cfg80211_btcoex_deinit(void);
++
++extern chanspec_t wl_chspec_from_legacy(chanspec_t legacy_chspec);
++extern chanspec_t wl_chspec_driver_to_host(chanspec_t chanspec);
++
++#ifdef WL_SUPPORT_AUTO_CHANNEL
++#define CHANSPEC_BUF_SIZE	1024
++#define CHAN_SEL_IOCTL_DELAY	300
++#define CHAN_SEL_RETRY_COUNT	15
++#define CHANNEL_IS_RADAR(channel)	(((channel & WL_CHAN_RADAR) || \
++	(channel & WL_CHAN_PASSIVE)) ? true : false)
++#define CHANNEL_IS_2G(channel)	(((channel >= 1) && (channel <= 14)) ? \
++	true : false)
++#define CHANNEL_IS_5G(channel)	(((channel >= 36) && (channel <= 165)) ? \
++	true : false)
++extern s32 wl_cfg80211_get_best_channels(struct net_device *dev, char* command,
++	int total_len);
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++extern int wl_cfg80211_ether_atoe(const char *a, struct ether_addr *n);
++extern int wl_cfg80211_hang(struct net_device *dev, u16 reason);
++extern s32 wl_mode_to_nl80211_iftype(s32 mode);
++int wl_cfg80211_do_driver_init(struct net_device *net);
++void wl_cfg80211_enable_trace(u32 level);
++extern s32 wl_update_wiphybands(struct bcm_cfg80211 *cfg, bool notify);
++extern s32 wl_cfg80211_if_is_group_owner(void);
++extern chanspec_t wl_chspec_host_to_driver(chanspec_t chanspec);
++extern chanspec_t wl_ch_host_to_driver(struct bcm_cfg80211 *cfg, s32 bssidx, u16 channel);
++extern s32 wl_set_tx_power(struct net_device *dev,
++	enum nl80211_tx_power_setting type, s32 dbm);
++extern s32 wl_get_tx_power(struct net_device *dev, s32 *dbm);
++extern s32 wl_add_remove_eventmsg(struct net_device *ndev, u16 event, bool add);
++extern void wl_stop_wait_next_action_frame(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	u8 bsscfgidx);
++extern void wl_cfg80211_add_to_eventbuffer(wl_eventmsg_buf_t *ev, u16 event, bool set);
++extern s32 wl_cfg80211_apply_eventbuffer(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, wl_eventmsg_buf_t *ev);
++extern void get_primary_mac(struct bcm_cfg80211 *cfg, struct ether_addr *mac);
++extern void wl_cfg80211_update_power_mode(struct net_device *dev);
++extern void wl_cfg80211_set_passive_scan(struct net_device *dev, char *command);
++extern void wl_terminate_event_handler(struct net_device *dev);
++#if defined(DHD_ENABLE_BIGDATA_LOGGING)
++extern s32 wl_cfg80211_get_bss_info(struct net_device *dev, char* cmd, int total_len);
++extern s32 wl_cfg80211_get_connect_failed_status(struct net_device *dev, char* cmd, int total_len);
++#endif /* DHD_ENABLE_BIGDATA_LOGGING */
++extern struct bcm_cfg80211 *wl_get_cfg(struct net_device *ndev);
++extern s32 wl_cfg80211_set_if_band(struct net_device *ndev, int band);
++
++#define SCAN_BUF_CNT	2
++#define SCAN_BUF_NEXT	1
++#define WL_SCANTYPE_LEGACY	0x1
++#define WL_SCANTYPE_P2P		0x2
++#define wl_escan_set_sync_id(a, b) ((a) = htod16((b)->escan_sync_id_cntr++))
++#define wl_escan_set_type(a, b)
++#define wl_escan_get_buf(a, b) ((wl_scan_results_t *) (a)->escan_info.escan_buf)
++#define wl_escan_check_sync_id(a, b, c) 0
++#define wl_escan_print_sync_id(a, b, c)
++#define wl_escan_increment_sync_id(a, b)
++#define wl_escan_init_sync_id(a)
++extern void wl_cfg80211_ibss_vsie_set_buffer(struct net_device *dev, vndr_ie_setbuf_t *ibss_vsie,
++	int ibss_vsie_len);
++extern s32 wl_cfg80211_ibss_vsie_delete(struct net_device *dev);
++#ifdef WL_RELMCAST
++extern void wl_cfg80211_set_rmc_pid(struct net_device *dev, int pid);
++#endif /* WL_RELMCAST */
++extern int wl_cfg80211_set_mgmt_vndr_ies(struct bcm_cfg80211 *cfg,
++	bcm_struct_cfgdev *cfgdev, s32 bssidx, s32 pktflag,
++	const u8 *vndr_ie, u32 vndr_ie_len);
++
++#ifdef WLFBT
++extern int wl_cfg80211_get_fbt_key(struct net_device *dev, uint8 *key, int total_len);
++#endif
++
++/* Action frame specific functions */
++extern u8 wl_get_action_category(void *frame, u32 frame_len);
++extern int wl_get_public_action(void *frame, u32 frame_len, u8 *ret_action);
++
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++struct net_device *wl_cfg80211_get_remain_on_channel_ndev(struct bcm_cfg80211 *cfg);
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++
++#ifdef WL_SUPPORT_ACS
++#define ACS_MSRMNT_DELAY 1000 /* dump_obss delay in ms */
++#define IOCTL_RETRY_COUNT 5
++#define CHAN_NOISE_DUMMY -80
++#define OBSS_TOKEN_IDX 15
++#define IBSS_TOKEN_IDX 15
++#define TX_TOKEN_IDX 14
++#define CTG_TOKEN_IDX 13
++#define PKT_TOKEN_IDX 15
++#define IDLE_TOKEN_IDX 12
++#endif /* WL_SUPPORT_ACS */
++
++
++extern int wl_cfg80211_get_ioctl_version(void);
++extern int wl_cfg80211_enable_roam_offload(struct net_device *dev, int enable);
++extern s32 wl_cfg80211_dfs_ap_move(struct net_device *ndev, char *data,
++		char *command, int total_len);
++#ifdef WBTEXT
++extern s32 wl_cfg80211_wbtext_set_default(struct net_device *ndev);
++extern s32 wl_cfg80211_wbtext_config(struct net_device *ndev, char *data,
++		char *command, int total_len);
++extern int wl_cfg80211_wbtext_weight_config(struct net_device *ndev, char *data,
++		char *command, int total_len);
++extern int wl_cfg80211_wbtext_table_config(struct net_device *ndev, char *data,
++		char *command, int total_len);
++extern s32 wl_cfg80211_wbtext_delta_config(struct net_device *ndev, char *data,
++		char *command, int total_len);
++#endif /* WBTEXT */
++extern s32 wl_cfg80211_get_chanspecs_2g(struct net_device *ndev,
++		void *buf, s32 buflen);
++extern s32 wl_cfg80211_get_chanspecs_5g(struct net_device *ndev,
++		void *buf, s32 buflen);
++
++extern s32 wl_cfg80211_bss_up(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev, s32 bsscfg_idx, s32 up);
++extern bool wl_cfg80211_bss_isup(struct net_device *ndev, int bsscfg_idx);
++
++struct net_device *wl_cfg80211_post_ifcreate(struct net_device *ndev,
++	wl_if_event_info *event, u8 *addr, const char *name, bool rtnl_lock_reqd);
++extern s32 wl_cfg80211_post_ifdel(struct net_device *ndev, bool rtnl_lock_reqd);
++#if defined(WL_VIRTUAL_APSTA)
++extern int wl_cfg80211_interface_create(struct net_device *dev, char *name);
++extern int wl_cfg80211_interface_delete(struct net_device *dev, char *name);
++#if defined(PKT_FILTER_SUPPORT) && defined(APSTA_BLOCK_ARP_DURING_DHCP)
++extern void wl_cfg80211_block_arp(struct net_device *dev, int enable);
++#endif /* PKT_FILTER_SUPPORT && APSTA_BLOCK_ARP_DURING_DHCP */
++#endif /* defined (WL_VIRTUAL_APSTA) */
++
++
++#ifdef WL_CFG80211_P2P_DEV_IF
++extern void wl_cfg80211_del_p2p_wdev(struct net_device *dev);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++#if defined(WL_SUPPORT_AUTO_CHANNEL)
++extern int wl_cfg80211_set_spect(struct net_device *dev, int spect);
++extern int wl_cfg80211_get_sta_channel(struct net_device *dev);
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++
++#ifdef P2P_LISTEN_OFFLOADING
++extern s32 wl_cfg80211_p2plo_listen_start(struct net_device *dev, u8 *buf, int len);
++extern s32 wl_cfg80211_p2plo_listen_stop(struct net_device *dev);
++#endif /* P2P_LISTEN_OFFLOADING */
++
++#define RETURN_EIO_IF_NOT_UP(wlpriv)                        \
++do {                                    \
++	struct net_device *checkSysUpNDev = bcmcfg_to_prmry_ndev(wlpriv);           \
++	if (unlikely(!wl_get_drv_status(wlpriv, READY, checkSysUpNDev))) {  \
++		WL_INFORM(("device is not ready\n"));           \
++		return -EIO;                        \
++	}                               \
++} while (0)
++
++#ifdef QOS_MAP_SET
++extern uint8 *wl_get_up_table(void);
++#endif /* QOS_MAP_SET */
++
++#define P2PO_COOKIE     65535
++u64 wl_cfg80211_get_new_roc_id(struct bcm_cfg80211 *cfg);
++
++#if defined(SUPPORT_RANDOM_MAC_SCAN)
++int wl_cfg80211_set_random_mac(struct net_device *dev, bool enable);
++int wl_cfg80211_random_mac_enable(struct net_device *dev);
++int wl_cfg80211_random_mac_disable(struct net_device *dev);
++#endif /* SUPPORT_RANDOM_MAC_SCAN */
++#ifdef SUPPORT_AP_HIGHER_BEACONRATE
++int wl_set_ap_beacon_rate(struct net_device *dev, int val, char *ifname);
++int wl_get_ap_basic_rate(struct net_device *dev, char* command, char *ifname, int total_len);
++#endif /* SUPPORT_AP_HIGHER_BEACONRATE */
++#ifdef SUPPORT_AP_RADIO_PWRSAVE
++int wl_get_ap_rps(struct net_device *dev, char* command, char *ifname, int total_len);
++int wl_set_ap_rps(struct net_device *dev, bool enable, char *ifname);
++int wl_update_ap_rps_params(struct net_device *dev, ap_rps_info_t* rps, char *ifname);
++void wl_cfg80211_init_ap_rps(struct bcm_cfg80211 *cfg);
++#endif /* SUPPORT_AP_RADIO_PWRSAVE */
++#ifdef SUPPORT_RSSI_LOGGING
++int wl_get_rssi_logging(struct net_device *dev, void *param);
++int wl_set_rssi_logging(struct net_device *dev, void *param);
++int wl_get_rssi_per_ant(struct net_device *dev, char *ifname, char *peer_mac, void *param);
++#endif /* SUPPORT_RSSI_LOGGING */
++int wl_cfg80211_iface_count(struct net_device *dev);
++struct net_device* wl_get_ap_netdev(struct bcm_cfg80211 *cfg, char *ifname);
++struct net_device* wl_get_netdev_by_name(struct bcm_cfg80211 *cfg, char *ifname);
++int wl_cfg80211_get_vndr_ouilist(struct bcm_cfg80211 *cfg, uint8 *buf, int max_cnt);
++s32 wl_cfg80211_autochannel(struct net_device *dev, char* command, int total_len);
++#endif /* _wl_cfg80211_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_cfg_btcoex.c b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfg_btcoex.c
+new file mode 100644
+index 000000000..a60f3e25a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfg_btcoex.c
+@@ -0,0 +1,570 @@
++/*
++ * Linux cfg80211 driver - Dongle Host Driver (DHD) related
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfg_btcoex.c 699163 2017-05-12 05:18:23Z $
++ */
++
++#include <net/rtnetlink.h>
++
++#include <bcmutils.h>
++#include <wldev_common.h>
++#include <wl_cfg80211.h>
++#include <dhd_cfg80211.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhdioctl.h>
++#include <wlioctl.h>
++
++#ifdef PKT_FILTER_SUPPORT
++extern uint dhd_pkt_filter_enable;
++extern uint dhd_master_mode;
++extern void dhd_pktfilter_offload_enable(dhd_pub_t * dhd, char *arg, int enable, int master_mode);
++#endif
++
++struct btcoex_info {
++	timer_list_compat_t timer;
++	u32 timer_ms;
++	u32 timer_on;
++	u32 ts_dhcp_start;	/* ms ts ecord time stats */
++	u32 ts_dhcp_ok;		/* ms ts ecord time stats */
++	bool dhcp_done;	/* flag, indicates that host done with
++					 * dhcp before t1/t2 expiration
++					 */
++	s32 bt_state;
++	struct work_struct work;
++	struct net_device *dev;
++};
++
++static struct btcoex_info *btcoex_info_loc = NULL;
++
++/* TODO: clean up the BT-Coex code, it still have some legacy ioctl/iovar functions */
++
++/* use New SCO/eSCO smart YG suppression */
++#define BT_DHCP_eSCO_FIX
++/* this flag boost wifi pkt priority to max, caution: -not fair to sco */
++#define BT_DHCP_USE_FLAGS
++/* T1 start SCO/ESCo priority suppression */
++#define BT_DHCP_OPPR_WIN_TIME	2500
++/* T2 turn off SCO/SCO supperesion is (timeout) */
++#define BT_DHCP_FLAG_FORCE_TIME 5500
++
++enum wl_cfg80211_btcoex_status {
++	BT_DHCP_IDLE,
++	BT_DHCP_START,
++	BT_DHCP_OPPR_WIN,
++	BT_DHCP_FLAG_FORCE_TIMEOUT
++};
++
++/*
++ * get named driver variable to uint register value and return error indication
++ * calling example: dev_wlc_intvar_get_reg(dev, "btc_params",66, &reg_value)
++ */
++static int
++dev_wlc_intvar_get_reg(struct net_device *dev, char *name,
++	uint reg, int *retval)
++{
++	union {
++		char buf[WLC_IOCTL_SMLEN];
++		int val;
++	} var;
++	int error;
++
++	bcm_mkiovar(name, (char *)(&reg), sizeof(reg),
++		(char *)(&var), sizeof(var.buf));
++	error = wldev_ioctl_get(dev, WLC_GET_VAR, (char *)(&var), sizeof(var.buf));
++
++	*retval = dtoh32(var.val);
++	return (error);
++}
++
++static int
++dev_wlc_bufvar_set(struct net_device *dev, char *name, char *buf, int len)
++{
++	char ioctlbuf_local[WLC_IOCTL_SMLEN];
++
++	bcm_mkiovar(name, buf, len, ioctlbuf_local, sizeof(ioctlbuf_local));
++
++	return (wldev_ioctl_set(dev, WLC_SET_VAR, ioctlbuf_local, sizeof(ioctlbuf_local)));
++}
++/*
++get named driver variable to uint register value and return error indication
++calling example: dev_wlc_intvar_set_reg(dev, "btc_params",66, value)
++*/
++static int
++dev_wlc_intvar_set_reg(struct net_device *dev, char *name, char *addr, char * val)
++{
++	char reg_addr[8];
++
++	memset(reg_addr, 0, sizeof(reg_addr));
++	memcpy((char *)&reg_addr[0], (char *)addr, 4);
++	memcpy((char *)&reg_addr[4], (char *)val, 4);
++
++	return (dev_wlc_bufvar_set(dev, name, (char *)&reg_addr[0], sizeof(reg_addr)));
++}
++
++static bool btcoex_is_sco_active(struct net_device *dev)
++{
++	int ioc_res = 0;
++	bool res = FALSE;
++	int sco_id_cnt = 0;
++	int param27;
++	int i;
++
++	for (i = 0; i < 12; i++) {
++
++		ioc_res = dev_wlc_intvar_get_reg(dev, "btc_params", 27, &param27);
++
++		WL_TRACE(("sample[%d], btc params: 27:%x\n", i, param27));
++
++		if (ioc_res < 0) {
++			WL_ERR(("ioc read btc params error\n"));
++			break;
++		}
++
++		if ((param27 & 0x6) == 2) { /* count both sco & esco  */
++			sco_id_cnt++;
++		}
++
++		if (sco_id_cnt > 2) {
++			WL_TRACE(("sco/esco detected, pkt id_cnt:%d  samples:%d\n",
++				sco_id_cnt, i));
++			res = TRUE;
++			break;
++		}
++
++		OSL_SLEEP(5);
++	}
++
++	return res;
++}
++
++#if defined(BT_DHCP_eSCO_FIX)
++/* Enhanced BT COEX settings for eSCO compatibility during DHCP window */
++static int set_btc_esco_params(struct net_device *dev, bool trump_sco)
++{
++	static bool saved_status = FALSE;
++
++	char buf_reg50va_dhcp_on[8] =
++		{ 50, 00, 00, 00, 0x22, 0x80, 0x00, 0x00 };
++	char buf_reg51va_dhcp_on[8] =
++		{ 51, 00, 00, 00, 0x00, 0x00, 0x00, 0x00 };
++	char buf_reg64va_dhcp_on[8] =
++		{ 64, 00, 00, 00, 0x00, 0x00, 0x00, 0x00 };
++	char buf_reg65va_dhcp_on[8] =
++		{ 65, 00, 00, 00, 0x00, 0x00, 0x00, 0x00 };
++	char buf_reg71va_dhcp_on[8] =
++		{ 71, 00, 00, 00, 0x00, 0x00, 0x00, 0x00 };
++	uint32 regaddr;
++	static uint32 saved_reg50;
++	static uint32 saved_reg51;
++	static uint32 saved_reg64;
++	static uint32 saved_reg65;
++	static uint32 saved_reg71;
++
++	if (trump_sco) {
++		/* this should reduce eSCO agressive retransmit
++		 * w/o breaking it
++		 */
++
++		/* 1st save current */
++		WL_TRACE(("Do new SCO/eSCO coex algo {save &"
++			  "override}\n"));
++		if ((!dev_wlc_intvar_get_reg(dev, "btc_params", 50, &saved_reg50)) &&
++			(!dev_wlc_intvar_get_reg(dev, "btc_params", 51, &saved_reg51)) &&
++			(!dev_wlc_intvar_get_reg(dev, "btc_params", 64, &saved_reg64)) &&
++			(!dev_wlc_intvar_get_reg(dev, "btc_params", 65, &saved_reg65)) &&
++			(!dev_wlc_intvar_get_reg(dev, "btc_params", 71, &saved_reg71))) {
++			saved_status = TRUE;
++			WL_TRACE(("saved bt_params[50,51,64,65,71]:"
++				  "0x%x 0x%x 0x%x 0x%x 0x%x\n",
++				  saved_reg50, saved_reg51,
++				  saved_reg64, saved_reg65, saved_reg71));
++		} else {
++			WL_ERR((":%s: save btc_params failed\n",
++				__FUNCTION__));
++			saved_status = FALSE;
++			return -1;
++		}
++
++		WL_TRACE(("override with [50,51,64,65,71]:"
++			  "0x%x 0x%x 0x%x 0x%x 0x%x\n",
++			  *(u32 *)(buf_reg50va_dhcp_on+4),
++			  *(u32 *)(buf_reg51va_dhcp_on+4),
++			  *(u32 *)(buf_reg64va_dhcp_on+4),
++			  *(u32 *)(buf_reg65va_dhcp_on+4),
++			  *(u32 *)(buf_reg71va_dhcp_on+4)));
++
++		dev_wlc_bufvar_set(dev, "btc_params",
++			(char *)&buf_reg50va_dhcp_on[0], 8);
++		dev_wlc_bufvar_set(dev, "btc_params",
++			(char *)&buf_reg51va_dhcp_on[0], 8);
++		dev_wlc_bufvar_set(dev, "btc_params",
++			(char *)&buf_reg64va_dhcp_on[0], 8);
++		dev_wlc_bufvar_set(dev, "btc_params",
++			(char *)&buf_reg65va_dhcp_on[0], 8);
++		dev_wlc_bufvar_set(dev, "btc_params",
++			(char *)&buf_reg71va_dhcp_on[0], 8);
++
++		saved_status = TRUE;
++	} else if (saved_status) {
++		/* restore previously saved bt params */
++		WL_TRACE(("Do new SCO/eSCO coex algo {save &"
++			  "override}\n"));
++
++		regaddr = 50;
++		dev_wlc_intvar_set_reg(dev, "btc_params",
++			(char *)&regaddr, (char *)&saved_reg50);
++		regaddr = 51;
++		dev_wlc_intvar_set_reg(dev, "btc_params",
++			(char *)&regaddr, (char *)&saved_reg51);
++		regaddr = 64;
++		dev_wlc_intvar_set_reg(dev, "btc_params",
++			(char *)&regaddr, (char *)&saved_reg64);
++		regaddr = 65;
++		dev_wlc_intvar_set_reg(dev, "btc_params",
++			(char *)&regaddr, (char *)&saved_reg65);
++		regaddr = 71;
++		dev_wlc_intvar_set_reg(dev, "btc_params",
++			(char *)&regaddr, (char *)&saved_reg71);
++
++		WL_TRACE(("restore bt_params[50,51,64,65,71]:"
++			"0x%x 0x%x 0x%x 0x%x 0x%x\n",
++			saved_reg50, saved_reg51, saved_reg64,
++			saved_reg65, saved_reg71));
++
++		saved_status = FALSE;
++	} else {
++		WL_ERR((":%s att to restore not saved BTCOEX params\n",
++			__FUNCTION__));
++		return -1;
++	}
++	return 0;
++}
++#endif /* BT_DHCP_eSCO_FIX */
++
++static void
++wl_cfg80211_bt_setflag(struct net_device *dev, bool set)
++{
++#if defined(BT_DHCP_USE_FLAGS)
++	char buf_flag7_dhcp_on[8] = { 7, 00, 00, 00, 0x1, 0x0, 0x00, 0x00 };
++	char buf_flag7_default[8]   = { 7, 00, 00, 00, 0x0, 0x00, 0x00, 0x00};
++#endif
++
++
++#if defined(BT_DHCP_eSCO_FIX)
++	/* set = 1, save & turn on  0 - off & restore prev settings */
++	set_btc_esco_params(dev, set);
++#endif
++
++#if defined(BT_DHCP_USE_FLAGS)
++	WL_TRACE(("WI-FI priority boost via bt flags, set:%d\n", set));
++	if (set == TRUE)
++		/* Forcing bt_flag7  */
++		dev_wlc_bufvar_set(dev, "btc_flags",
++			(char *)&buf_flag7_dhcp_on[0],
++			sizeof(buf_flag7_dhcp_on));
++	else
++		/* Restoring default bt flag7 */
++		dev_wlc_bufvar_set(dev, "btc_flags",
++			(char *)&buf_flag7_default[0],
++			sizeof(buf_flag7_default));
++#endif
++}
++
++static void wl_cfg80211_bt_timerfunc(ulong data)
++{
++	struct btcoex_info *bt_local = (struct btcoex_info *)data;
++	WL_TRACE(("Enter\n"));
++	bt_local->timer_on = 0;
++	schedule_work(&bt_local->work);
++}
++
++static void wl_cfg80211_bt_handler(struct work_struct *work)
++{
++	struct btcoex_info *btcx_inf;
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	btcx_inf = container_of(work, struct btcoex_info, work);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++	if (btcx_inf->timer_on) {
++		btcx_inf->timer_on = 0;
++		_del_timer_sync(&btcx_inf->timer);
++	}
++
++	switch (btcx_inf->bt_state) {
++		case BT_DHCP_START:
++			/* DHCP started
++			 * provide OPPORTUNITY window to get DHCP address
++			 */
++			WL_TRACE(("bt_dhcp stm: started \n"));
++
++			btcx_inf->bt_state = BT_DHCP_OPPR_WIN;
++			mod_timer(&btcx_inf->timer,
++				jiffies + msecs_to_jiffies(BT_DHCP_OPPR_WIN_TIME));
++			btcx_inf->timer_on = 1;
++			break;
++
++		case BT_DHCP_OPPR_WIN:
++			if (btcx_inf->dhcp_done) {
++				WL_TRACE(("DHCP Done before T1 expiration\n"));
++				goto btc_coex_idle;
++			}
++
++			/* DHCP is not over yet, start lowering BT priority
++			 * enforce btc_params + flags if necessary
++			 */
++			WL_TRACE(("DHCP T1:%d expired\n", BT_DHCP_OPPR_WIN_TIME));
++			if (btcx_inf->dev)
++				wl_cfg80211_bt_setflag(btcx_inf->dev, TRUE);
++			btcx_inf->bt_state = BT_DHCP_FLAG_FORCE_TIMEOUT;
++			mod_timer(&btcx_inf->timer,
++				jiffies + msecs_to_jiffies(BT_DHCP_FLAG_FORCE_TIME));
++			btcx_inf->timer_on = 1;
++			break;
++
++		case BT_DHCP_FLAG_FORCE_TIMEOUT:
++			if (btcx_inf->dhcp_done) {
++				WL_TRACE(("DHCP Done before T2 expiration\n"));
++			} else {
++				/* Noo dhcp during T1+T2, restore BT priority */
++				WL_TRACE(("DHCP wait interval T2:%d msec expired\n",
++					BT_DHCP_FLAG_FORCE_TIME));
++			}
++
++			/* Restoring default bt priority */
++			if (btcx_inf->dev)
++				wl_cfg80211_bt_setflag(btcx_inf->dev, FALSE);
++btc_coex_idle:
++			btcx_inf->bt_state = BT_DHCP_IDLE;
++			btcx_inf->timer_on = 0;
++			break;
++
++		default:
++			WL_ERR(("error g_status=%d !!!\n",	btcx_inf->bt_state));
++			if (btcx_inf->dev)
++				wl_cfg80211_bt_setflag(btcx_inf->dev, FALSE);
++			btcx_inf->bt_state = BT_DHCP_IDLE;
++			btcx_inf->timer_on = 0;
++			break;
++	}
++
++	net_os_wake_unlock(btcx_inf->dev);
++}
++
++void* wl_cfg80211_btcoex_init(struct net_device *ndev)
++{
++	struct btcoex_info *btco_inf = NULL;
++
++	btco_inf = kmalloc(sizeof(struct btcoex_info), GFP_KERNEL);
++	if (!btco_inf)
++		return NULL;
++
++	btco_inf->bt_state = BT_DHCP_IDLE;
++	btco_inf->ts_dhcp_start = 0;
++	btco_inf->ts_dhcp_ok = 0;
++	/* Set up timer for BT  */
++	btco_inf->timer_ms = 10;
++	init_timer_compat(&btco_inf->timer, wl_cfg80211_bt_timerfunc, btco_inf);
++
++	btco_inf->dev = ndev;
++
++	INIT_WORK(&btco_inf->work, wl_cfg80211_bt_handler);
++
++	btcoex_info_loc = btco_inf;
++	return btco_inf;
++}
++
++void wl_cfg80211_btcoex_deinit()
++{
++	if (!btcoex_info_loc)
++		return;
++
++	if (btcoex_info_loc->timer_on) {
++		btcoex_info_loc->timer_on = 0;
++		_del_timer_sync(&btcoex_info_loc->timer);
++	}
++
++	cancel_work_sync(&btcoex_info_loc->work);
++
++	kfree(btcoex_info_loc);
++}
++
++int wl_cfg80211_set_btcoex_dhcp(struct net_device *dev, dhd_pub_t *dhd, char *command)
++{
++
++	struct btcoex_info *btco_inf = btcoex_info_loc;
++	char powermode_val = 0;
++	char buf_reg66va_dhcp_on[8] = { 66, 00, 00, 00, 0x10, 0x27, 0x00, 0x00 };
++	char buf_reg41va_dhcp_on[8] = { 41, 00, 00, 00, 0x33, 0x00, 0x00, 0x00 };
++	char buf_reg68va_dhcp_on[8] = { 68, 00, 00, 00, 0x90, 0x01, 0x00, 0x00 };
++
++	uint32 regaddr;
++	static uint32 saved_reg66;
++	static uint32 saved_reg41;
++	static uint32 saved_reg68;
++	static bool saved_status = FALSE;
++
++	char buf_flag7_default[8] =   { 7, 00, 00, 00, 0x0, 0x00, 0x00, 0x00};
++
++	/* Figure out powermode 1 or o command */
++	strncpy((char *)&powermode_val, command + strlen("BTCOEXMODE") +1, 1);
++
++	if (strnicmp((char *)&powermode_val, "1", strlen("1")) == 0) {
++		WL_TRACE_HW4(("DHCP session starts\n"));
++
++
++#ifdef PKT_FILTER_SUPPORT
++		dhd->dhcp_in_progress = 1;
++
++#if defined(WL_VIRTUAL_APSTA) && defined(APSTA_BLOCK_ARP_DURING_DHCP)
++		if ((dhd->op_mode & DHD_FLAG_CONCURR_STA_HOSTAP_MODE) ==
++			DHD_FLAG_CONCURR_STA_HOSTAP_MODE) {
++			/* Block ARP frames while DHCP of STA interface is in
++			 * progress in case of STA/SoftAP concurrent mode
++			 */
++			wl_cfg80211_block_arp(dev, TRUE);
++		} else
++#endif /* WL_VIRTUAL_APSTA && APSTA_BLOCK_ARP_DURING_DHCP */
++		if (dhd->early_suspended) {
++			WL_TRACE_HW4(("DHCP in progressing , disable packet filter!!!\n"));
++			dhd_enable_packet_filter(0, dhd);
++		}
++#endif /* PKT_FILTER_SUPPORT */
++
++		/* Retrieve and saved orig regs value */
++		if ((saved_status == FALSE) &&
++			(!dev_wlc_intvar_get_reg(dev, "btc_params", 66,  &saved_reg66)) &&
++			(!dev_wlc_intvar_get_reg(dev, "btc_params", 41,  &saved_reg41)) &&
++			(!dev_wlc_intvar_get_reg(dev, "btc_params", 68,  &saved_reg68)))   {
++				saved_status = TRUE;
++				WL_TRACE(("Saved 0x%x 0x%x 0x%x\n",
++					saved_reg66, saved_reg41, saved_reg68));
++
++				/* Disable PM mode during dhpc session */
++
++				/* Disable PM mode during dhpc session */
++				/* Start  BT timer only for SCO connection */
++				if (btcoex_is_sco_active(dev)) {
++					/* btc_params 66 */
++					dev_wlc_bufvar_set(dev, "btc_params",
++						(char *)&buf_reg66va_dhcp_on[0],
++						sizeof(buf_reg66va_dhcp_on));
++					/* btc_params 41 0x33 */
++					dev_wlc_bufvar_set(dev, "btc_params",
++						(char *)&buf_reg41va_dhcp_on[0],
++						sizeof(buf_reg41va_dhcp_on));
++					/* btc_params 68 0x190 */
++					dev_wlc_bufvar_set(dev, "btc_params",
++						(char *)&buf_reg68va_dhcp_on[0],
++						sizeof(buf_reg68va_dhcp_on));
++					saved_status = TRUE;
++
++					btco_inf->bt_state = BT_DHCP_START;
++					btco_inf->timer_on = 1;
++					mod_timer(&btco_inf->timer,
++						timer_expires(&btco_inf->timer));
++					WL_TRACE(("enable BT DHCP Timer\n"));
++				}
++		}
++		else if (saved_status == TRUE) {
++			WL_ERR(("was called w/o DHCP OFF. Continue\n"));
++		}
++	}
++	else if (strnicmp((char *)&powermode_val, "2", strlen("2")) == 0) {
++
++
++
++#ifdef PKT_FILTER_SUPPORT
++		dhd->dhcp_in_progress = 0;
++		WL_TRACE_HW4(("DHCP is complete \n"));
++
++#if defined(WL_VIRTUAL_APSTA) && defined(APSTA_BLOCK_ARP_DURING_DHCP)
++		if ((dhd->op_mode & DHD_FLAG_CONCURR_STA_HOSTAP_MODE) ==
++			DHD_FLAG_CONCURR_STA_HOSTAP_MODE) {
++			/* Unblock ARP frames */
++			wl_cfg80211_block_arp(dev, FALSE);
++		} else
++#endif /* WL_VIRTUAL_APSTA && APSTA_BLOCK_ARP_DURING_DHCP */
++		if (dhd->early_suspended) {
++			/* Enable packet filtering */
++			WL_TRACE_HW4(("DHCP is complete , enable packet filter!!!\n"));
++			dhd_enable_packet_filter(1, dhd);
++		}
++#endif /* PKT_FILTER_SUPPORT */
++
++		/* Restoring PM mode */
++
++		/* Stop any bt timer because DHCP session is done */
++		WL_TRACE(("disable BT DHCP Timer\n"));
++		if (btco_inf->timer_on) {
++			btco_inf->timer_on = 0;
++			_del_timer_sync(&btco_inf->timer);
++
++			if (btco_inf->bt_state != BT_DHCP_IDLE) {
++			/* need to restore original btc flags & extra btc params */
++				WL_TRACE(("bt->bt_state:%d\n", btco_inf->bt_state));
++				/* wake up btcoex thread to restore btlags+params  */
++				schedule_work(&btco_inf->work);
++			}
++		}
++
++		/* Restoring btc_flag paramter anyway */
++		if (saved_status == TRUE)
++			dev_wlc_bufvar_set(dev, "btc_flags",
++				(char *)&buf_flag7_default[0], sizeof(buf_flag7_default));
++
++		/* Restore original values */
++		if (saved_status == TRUE) {
++			regaddr = 66;
++			dev_wlc_intvar_set_reg(dev, "btc_params",
++				(char *)&regaddr, (char *)&saved_reg66);
++			regaddr = 41;
++			dev_wlc_intvar_set_reg(dev, "btc_params",
++				(char *)&regaddr, (char *)&saved_reg41);
++			regaddr = 68;
++			dev_wlc_intvar_set_reg(dev, "btc_params",
++				(char *)&regaddr, (char *)&saved_reg68);
++
++			WL_TRACE(("restore regs {66,41,68} <- 0x%x 0x%x 0x%x\n",
++				saved_reg66, saved_reg41, saved_reg68));
++		}
++		saved_status = FALSE;
++
++	}
++	else {
++		WL_ERR(("Unkwown yet power setting, ignored\n"));
++	}
++
++	snprintf(command, 3, "OK");
++
++	return (strlen("OK"));
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgnan.c b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgnan.c
+new file mode 100644
+index 000000000..39682b5dc
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgnan.c
+@@ -0,0 +1,27 @@
++/*
++ * Neighbor Awareness Networking
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfgnan.c 676811 2016-12-24 20:48:46Z $
++ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgnan.h b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgnan.h
+new file mode 100644
+index 000000000..a609af3d2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgnan.h
+@@ -0,0 +1,364 @@
++/*
++ * Neighbor Awareness Networking
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfgnan.h 650782 2016-07-22 11:51:53Z $
++ */
++
++#ifndef _wl_cfgnan_h_
++#define _wl_cfgnan_h_
++
++#define NAN_IOCTL_BUF_SIZE			512
++#define NAN_EVENT_NAME_MAX_LEN		40
++#define NAN_CONFIG_ATTR_MAX_LEN		24
++#define NAN_RTT_IOVAR_BUF_SIZE		1024
++#define WL_NAN_EVENT_CLEAR_BIT		32
++#define NAN_EVENT_MASK_ALL			0x7fffffff
++
++#define NAN_MAXIMUM_ID_NUMBER 255
++#define NAN_MAXIMUM_MASTER_PREFERENCE 255
++#ifdef NAN_DP
++#define MAX_IF_ADD_WAIT_TIME	1000
++#endif /* NAN_DP */
++#define NAN_INVALID_ID(id)	(id > NAN_MAXIMUM_ID_NUMBER)
++#define NAN_INVALID_ROLE(role)	(role > WL_NAN_ROLE_ANCHOR_MASTER)
++#define NAN_INVALID_CHANSPEC(chanspec)	((chanspec == INVCHANSPEC) || \
++	(chanspec == 0))
++#define NAN_INVALID_EVENT(num)	((num < WL_NAN_EVENT_START) || \
++	(num >= WL_NAN_EVENT_INVALID))
++#define NAN_INVALID_PROXD_EVENT(num)	(num != WLC_E_PROXD_NAN_EVENT)
++#define NAN_EVENT_BIT(event) (1U << (event - WL_NAN_EVENT_START))
++#define NAME_TO_STR(name) #name
++#define NAN_ID_CTRL_SIZE ((NAN_MAXIMUM_ID_NUMBER/8) + 1)
++
++#define SUPP_EVENT_PREFIX		"CTRL-EVENT-"
++#define EVENT_RTT_STATUS_STR	"NAN-RTT-STATUS"
++
++#define TIMESTAMP_PREFIX	"TSF="			/* timestamp */
++#define AMR_PREFIX			"AMR="			/* anchor master rank */
++#define DISTANCE_PREFIX		"DIST="			/* distance */
++#define ATTR_PREFIX			"ATTR="			/* attribute */
++#define ROLE_PREFIX			"ROLE="			/* role */
++#define CHAN_PREFIX			"CHAN="			/* channel */
++#define BITMAP_PREFIX		"BMAP="			/* bitmap */
++#define DEBUG_PREFIX		"DEBUG="		/* debug enable/disable flag */
++#define DW_LEN_PREFIX		"DW_LEN="		/* discovery window length */
++#define DW_INT_PREFIX		"DW_INT="		/* discovery window interval */
++#define STATUS_PREFIX		"STATUS="		/* status */
++#define PUB_ID_PREFIX		"PUB_ID="		/* publisher id */
++#define SUB_ID_PREFIX		"SUB_ID="		/* subscriber id */
++#define INSTANCE_ID_PREFIX		"LOCAL_ID="		/* Instance id */
++#define REMOTE_INSTANCE_ID_PREFIX		"PEER_ID="		/* Peer id */
++
++#ifdef NAN_P2P_CONFIG
++#define P2P_IE_PREFIX		"P2P_IE="		/* p2p ie  id */
++#define IE_EN_PREFIX		"ENBLE_IE="		/* enable p2p ie  */
++#endif
++#define PUB_PR_PREFIX		"PUB_PR="		/* publish period */
++#define PUB_INT_PREFIX		"PUB_INT="		/* publish interval (ttl) */
++#define CLUS_ID_PREFIX		"CLUS_ID="		/* cluster id */
++#define IF_ADDR_PREFIX		"IF_ADDR="		/* IF address */
++#define MAC_ADDR_PREFIX		"MAC_ADDR="		/* mac address */
++#define SVC_HASH_PREFIX		"SVC_HASH="		/* service hash */
++#define SVC_INFO_PREFIX		"SVC_INFO="		/* service information */
++#define HOP_COUNT_PREFIX	"HOP_COUNT="	/* hop count */
++#define MASTER_PREF_PREFIX	"MASTER_PREF="	/* master preference */
++#define ACTIVE_OPTION		"ACTIVE"		/* Active Subscribe. */
++#define SOLICITED_OPTION	"SOLICITED"		/* Solicited Publish. */
++#define UNSOLICITED_OPTION	"UNSOLICITED"	/* Unsolicited Publish. */
++/* anchor master beacon transmission time */
++#define AMBTT_PREFIX		"AMBTT="
++/* passive scan period for cluster merge */
++#define SCAN_PERIOD_PREFIX	"SCAN_PERIOD="
++/* passive scan interval for cluster merge */
++#define SCAN_INTERVAL_PREFIX	"SCAN_INTERVAL="
++#define BCN_INTERVAL_PREFIX		"BCN_INTERVAL="
++
++#define NAN_EVENT_STR_STARTED               "NAN-STARTED"
++#define NAN_EVENT_STR_JOINED                "NAN-JOINED"
++#define NAN_EVENT_STR_ROLE_CHANGE           "NAN-ROLE-CHANGE"
++#define NAN_EVENT_STR_SCAN_COMPLETE         "NAN-SCAN-COMPLETE"
++#define NAN_EVENT_STR_SDF_RX                "NAN-SDF-RX"
++#define NAN_EVENT_STR_REPLIED               "NAN-REPLIED"
++#define NAN_EVENT_STR_TERMINATED            "NAN-TERMINATED"
++#define NAN_EVENT_STR_FOLLOWUP_RX           "NAN-FOLLOWUP-RX"
++#define NAN_EVENT_STR_STATUS_CHANGE         "NAN-STATUS-CHANGE"
++#define NAN_EVENT_STR_MERGED                "NAN-MERGED"
++#define NAN_EVENT_STR_STOPPED               "NAN-STOPPED"
++#define NAN_EVENT_STR_P2P_RX                "NAN-P2P-RX"
++#define NAN_EVENT_STR_WINDOW_BEGUN_P2P      "NAN-WINDOW-BEGUN-P2P"
++#define NAN_EVENT_STR_WINDOW_BEGUN_MESH     "NAN-WINDOW-BEGUN-MESH"
++#define NAN_EVENT_STR_WINDOW_BEGUN_IBSS     "NAN-WINDOW-BEGUN-IBSS"
++#define NAN_EVENT_STR_WINDOW_BEGUN_RANGING  "NAN-WINDOW-BEGUN-RANGING"
++#define NAN_EVENT_STR_INVALID               "NAN-INVALID"
++
++#ifdef NAN_DP
++enum nan_dp_states {
++	NAN_DP_STATE_DISABLED = 0,
++	NAN_DP_STATE_ENABLED = 1
++};
++#endif /* NAN_DP */
++
++enum nan_de_event_type {
++	NAN_EVENT_START = 0,
++	NAN_EVENT_JOIN = 1
++};
++
++typedef struct nan_str_data {
++	u8 *data;
++	u32 dlen;
++} nan_str_data_t;
++
++typedef struct nan_mac_list {
++	u8 *list;
++	u32 num_mac_addr;
++} nan_mac_list_t;
++
++typedef struct nan_config_attr {
++	char name[NAN_CONFIG_ATTR_MAX_LEN];	/* attribute name */
++	u16 type;							/* attribute xtlv type */
++} nan_config_attr_t;
++
++typedef struct wl_nan_sid_beacon_tune {
++	u8 sid_enable;	/* flag for sending service id in beacon */
++	u8 sid_count;	/* Limit for number of SIDs to be included in Beacons */
++} wl_nan_sid_beacon_ctrl_t;
++
++typedef struct nan_cmd_data {
++	nan_config_attr_t attr;			/* set config attributes */
++	nan_str_data_t svc_hash;		/* service hash */
++	nan_str_data_t svc_info;		/* service information */
++	nan_str_data_t p2p_info;		/* p2p information */
++	struct ether_addr mac_addr;		/* mac address */
++	struct ether_addr clus_id;		/* cluster id */
++	struct ether_addr if_addr;		/* if addr */
++	u32 beacon_int;					/* beacon interval */
++	u32 ttl;                      /* time to live */
++	u32 period;                   /* publish period */
++	u32 bmap;						/* bitmap */
++	u32 role;						/* role */
++	wl_nan_instance_id_t pub_id;	/* publisher id */
++	wl_nan_instance_id_t sub_id;	/* subscriber id */
++	wl_nan_instance_id_t local_id;	/* Local id */
++	wl_nan_instance_id_t remote_id;	/* Remote id */
++	uint32 flags;					/* Flag bits */
++	u16 dw_len;						/* discovery window length */
++	u16 master_pref;				/* master preference */
++	chanspec_t chanspec;			/* channel */
++	u8 debug_flag;					/* debug enable/disable flag */
++	u8 life_count;             /* life count of the instance */
++	u8 srf_type;               /* SRF type */
++	u8 srf_include;            /* SRF include */
++	u8 use_srf;                /* use SRF */
++	nan_str_data_t rx_match;	/* matching filter rx */
++	nan_str_data_t tx_match;	/* matching filter tx */
++	nan_mac_list_t mac_list;   /* mac list */
++	uint8 hop_count_limit;     /* hop count limit */
++	uint8 nan_band;            /* nan band <A/B/AUTO> */
++	uint8 support_5g;          /* To decide dual band support */
++	uint32 nan_oui;            /* configured nan oui */
++#ifdef NAN_DP
++	struct ether_addr data_cluster_id;		/* data cluster id */
++#endif /* NAN_DP */
++	wl_nan_sid_beacon_ctrl_t sid_beacon;          /* sending service id in beacon */
++} nan_cmd_data_t;
++
++typedef int (nan_func_t)(struct net_device *ndev, struct bcm_cfg80211 *cfg,
++	char *cmd, int size, nan_cmd_data_t *cmd_data);
++
++typedef struct nan_cmd {
++	const char *name;					/* command name */
++	nan_func_t *func;					/* command hadler */
++} nan_cmd_t;
++
++typedef struct nan_event_hdr {
++	u16 event_subtype;
++	u32 flags;							/* future use */
++} nan_event_hdr_t;
++
++typedef struct wl_nan_tlv_data {
++	wl_nan_status_t nstatus;			/* status data */
++	wl_nan_disc_params_t params;		/* discovery parameters */
++	struct ether_addr mac_addr;			/* peer mac address */
++	struct ether_addr clus_id;			/* cluster id */
++	nan_str_data_t svc_info;			/* service info */
++	nan_str_data_t vend_info;			/* vendor info */
++	/* anchor master beacon transmission time */
++	u32 ambtt;
++	u32 dev_role;						/* device role */
++	u16 inst_id;						/* instance id */
++	u16 peer_inst_id;					/* Peer instance id */
++	u16 pub_id;							/* publisher id */
++	u16 sub_id;							/* subscriber id */
++	u16 master_pref;					/* master preference */
++	chanspec_t chanspec;				/* channel */
++	u8 amr[NAN_MASTER_RANK_LEN];		/* anchor master role */
++	u8 svc_name[WL_NAN_SVC_HASH_LEN];	/* service name */
++	u8 hop_count;						/* hop count */
++	u8 enabled;							/* nan status flag */
++	nan_scan_params_t scan_params;		/* scan_param */
++	int reason_code;              /* reason code */
++} wl_nan_tlv_data_t;
++
++typedef struct _nan_de_event_data {
++	wl_nan_cfg_status_t *nstatus;
++	u8 nan_de_evt_type;
++} nan_de_event_data_t;
++
++typedef struct _nan_hal_resp {
++	unsigned short instance_id;
++	unsigned short subcmd;
++	int status;
++	int value;
++} nan_hal_resp_t;
++
++#ifdef NAN_DP
++typedef struct nan_data_path_peer {
++	struct ether_addr addr;        /* peer mac address */
++	chanspec_t chanspec;           /* Channel Specification */
++} nan_data_path_peer_t;
++#endif /* NAN_DP */
++
++extern int wl_cfgnan_set_vars_cbfn(void *ctx, uint8 *tlv_buf,
++	uint16 type, uint16 len);
++extern int wl_cfgnan_enable_events(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg);
++extern int wl_cfgnan_start_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_stop_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_support_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_status_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_pub_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_p2p_ie_add_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_p2p_ie_enable_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_p2p_ie_del_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++
++extern int wl_cfgnan_sub_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_cancel_pub_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_cancel_sub_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_transmit_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_set_config_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_rtt_config_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_rtt_find_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++#ifdef WL_NAN_DEBUG
++extern int wl_cfgnan_debug_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++#endif /* WL_NAN_DEBUG */
++extern int wl_cfgnan_cmd_handler(struct net_device *dev,
++	struct bcm_cfg80211 *cfg, char *cmd, int cmd_len);
++extern s32 wl_cfgnan_notify_nan_status(struct bcm_cfg80211 *cfg,
++	bcm_struct_cfgdev *cfgdev, const wl_event_msg_t *e, void *data);
++extern s32 wl_cfgnan_notify_proxd_status(struct bcm_cfg80211 *cfg,
++	bcm_struct_cfgdev *cfgdev, const wl_event_msg_t *e, void *data);
++extern int wl_cfgnan_generate_inst_id(struct bcm_cfg80211 *cfg,
++	uint8 inst_type, uint8 *p_inst_id);
++extern int wl_cfgnan_validate_inst_id(struct bcm_cfg80211 *cfg,
++	uint8 inst_id);
++extern int wl_cfgnan_remove_inst_id(struct bcm_cfg80211 *cfg,
++	uint8 inst_id);
++extern int wl_cfgnan_get_inst_type(struct bcm_cfg80211 *cfg,
++	uint8 inst_id, uint8 *inst_type);
++
++typedef enum {
++	NAN_ATTRIBUTE_HEADER = 100,
++	NAN_ATTRIBUTE_HANDLE,
++	NAN_ATTRIBUTE_TRANSAC_ID,
++	/* NAN Enable request attributes */
++	NAN_ATTRIBUTE_5G_SUPPORT,
++	NAN_ATTRIBUTE_CLUSTER_LOW,
++	NAN_ATTRIBUTE_CLUSTER_HIGH,
++	NAN_ATTRIBUTE_SID_BEACON,
++	NAN_ATTRIBUTE_SYNC_DISC_5G,
++	NAN_ATTRIBUTE_RSSI_CLOSE,
++	NAN_ATTRIBUTE_RSSI_MIDDLE,
++	NAN_ATTRIBUTE_RSSI_PROXIMITY,
++	NAN_ATTRIBUTE_HOP_COUNT_LIMIT,
++	NAN_ATTRIBUTE_RANDOM_TIME,
++	NAN_ATTRIBUTE_MASTER_PREF,
++	NAN_ATTRIBUTE_PERIODIC_SCAN_INTERVAL,
++	/* Nan Publish/Subscribe request Attributes */
++	NAN_ATTRIBUTE_PUBLISH_ID,
++	NAN_ATTRIBUTE_TTL,
++	NAN_ATTRIBUTE_PERIOD,
++	NAN_ATTRIBUTE_REPLIED_EVENT_FLAG,
++	NAN_ATTRIBUTE_PUBLISH_TYPE,
++	NAN_ATTRIBUTE_TX_TYPE,
++	NAN_ATTRIBUTE_PUBLISH_COUNT,
++	NAN_ATTRIBUTE_SERVICE_NAME_LEN,
++	NAN_ATTRIBUTE_SERVICE_NAME,
++	NAN_ATTRIBUTE_SERVICE_SPECIFIC_INFO_LEN,
++	NAN_ATTRIBUTE_SERVICE_SPECIFIC_INFO,
++	NAN_ATTRIBUTE_RX_MATCH_FILTER_LEN,
++	NAN_ATTRIBUTE_RX_MATCH_FILTER,
++	NAN_ATTRIBUTE_TX_MATCH_FILTER_LEN,
++	NAN_ATTRIBUTE_TX_MATCH_FILTER,
++	NAN_ATTRIBUTE_SUBSCRIBE_ID,
++	NAN_ATTRIBUTE_SUBSCRIBE_TYPE,
++	NAN_ATTRIBUTE_SERVICERESPONSEFILTER,
++	NAN_ATTRIBUTE_SERVICERESPONSEINCLUDE,
++	NAN_ATTRIBUTE_USESERVICERESPONSEFILTER,
++	NAN_ATTRIBUTE_SSIREQUIREDFORMATCHINDICATION,
++	NAN_ATTRIBUTE_SUBSCRIBE_MATCH,
++	NAN_ATTRIBUTE_SUBSCRIBE_COUNT,
++	NAN_ATTRIBUTE_MAC_ADDR,
++	NAN_ATTRIBUTE_MAC_ADDR_LIST,
++	NAN_ATTRIBUTE_MAC_ADDR_LIST_NUM_ENTRIES,
++	NAN_ATTRIBUTE_PUBLISH_MATCH,
++	/* Nan Event attributes */
++	NAN_ATTRIBUTE_ENABLE_STATUS,
++	NAN_ATTRIBUTE_JOIN_STATUS,
++	NAN_ATTRIBUTE_ROLE,
++	NAN_ATTRIBUTE_CHANNEL,	/* channel */
++	NAN_ATTRIBUTE_PEER_ID,
++	NAN_ATTRIBUTE_INST_ID,
++	NAN_ATTRIBUTE_OUI,
++	NAN_ATTRIBUTE_DATA_IF_ADD,       /* NAN DP Interface Address */
++	NAN_ATTRIBUTE_STATUS,
++	NAN_ATTRIBUTE_DE_EVENT_TYPE
++} NAN_ATTRIBUTE;
++
++#define NAN_BLOOM_LENGTH_DEFAULT        240
++#define NAN_SRF_MAX_MAC (NAN_BLOOM_LENGTH_DEFAULT / ETHER_ADDR_LEN)
++
++#ifdef NAN_DP
++int wl_cfgnan_data_path_open_handler(struct net_device *ndev,
++		struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++int wl_cfgnan_data_path_close_handler(struct net_device *ndev,
++		struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++#endif /* NAN_DP */
++#endif	/* _wl_cfgnan_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgp2p.c b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgp2p.c
+new file mode 100644
+index 000000000..19755f65a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgp2p.c
+@@ -0,0 +1,2600 @@
++/*
++ * Linux cfgp2p driver
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfgp2p.c 699163 2017-05-12 05:18:23Z $
++ *
++ */
++#include <typedefs.h>
++#include <linuxver.h>
++#include <osl.h>
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/types.h>
++#include <linux/string.h>
++#include <linux/timer.h>
++#include <linux/if_arp.h>
++#include <asm/uaccess.h>
++
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <ethernet.h>
++#include <802.11.h>
++#include <net/rtnetlink.h>
++
++#include <wl_cfg80211.h>
++#include <wl_cfgp2p.h>
++#include <wldev_common.h>
++#include <wl_android.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_linux.h>
++#include <dhdioctl.h>
++#include <wlioctl.h>
++#include <dhd_cfg80211.h>
++#include <dhd_config.h>
++
++#if defined(BCMPCIE) && defined(DHD_FW_COREDUMP)
++extern int dhd_bus_mem_dump(dhd_pub_t *dhd);
++#endif /* BCMPCIE && DHD_FW_COREDUMP */
++
++static s8 scanparambuf[WLC_IOCTL_SMLEN];
++static bool
++wl_cfgp2p_has_ie(u8 *ie, u8 **tlvs, u32 *tlvs_len, const u8 *oui, u32 oui_len, u8 type);
++
++static s32 wl_cfgp2p_cancel_listen(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	struct wireless_dev *wdev, bool notify);
++
++#if defined(WL_ENABLE_P2P_IF)
++static int wl_cfgp2p_start_xmit(struct sk_buff *skb, struct net_device *ndev);
++static int wl_cfgp2p_do_ioctl(struct net_device *net, struct ifreq *ifr, int cmd);
++static int wl_cfgp2p_if_open(struct net_device *net);
++static int wl_cfgp2p_if_stop(struct net_device *net);
++
++static const struct net_device_ops wl_cfgp2p_if_ops = {
++	.ndo_open       = wl_cfgp2p_if_open,
++	.ndo_stop       = wl_cfgp2p_if_stop,
++	.ndo_do_ioctl   = wl_cfgp2p_do_ioctl,
++	.ndo_start_xmit = wl_cfgp2p_start_xmit,
++};
++#endif /* WL_ENABLE_P2P_IF */
++
++
++bool wl_cfgp2p_is_pub_action(void *frame, u32 frame_len)
++{
++	wifi_p2p_pub_act_frame_t *pact_frm;
++
++	if (frame == NULL)
++		return false;
++	pact_frm = (wifi_p2p_pub_act_frame_t *)frame;
++	if (frame_len < sizeof(wifi_p2p_pub_act_frame_t) -1)
++		return false;
++
++	if (pact_frm->category == P2P_PUB_AF_CATEGORY &&
++		pact_frm->action == P2P_PUB_AF_ACTION &&
++		pact_frm->oui_type == P2P_VER &&
++		memcmp(pact_frm->oui, P2P_OUI, sizeof(pact_frm->oui)) == 0) {
++		return true;
++	}
++
++	return false;
++}
++
++bool wl_cfgp2p_is_p2p_action(void *frame, u32 frame_len)
++{
++	wifi_p2p_action_frame_t *act_frm;
++
++	if (frame == NULL)
++		return false;
++	act_frm = (wifi_p2p_action_frame_t *)frame;
++	if (frame_len < sizeof(wifi_p2p_action_frame_t) -1)
++		return false;
++
++	if (act_frm->category == P2P_AF_CATEGORY &&
++		act_frm->type  == P2P_VER &&
++		memcmp(act_frm->OUI, P2P_OUI, DOT11_OUI_LEN) == 0) {
++		return true;
++	}
++
++	return false;
++}
++
++#define GAS_RESP_LEN		2
++#define DOUBLE_TLV_BODY_OFF	4
++#define GAS_RESP_OFFSET		4
++#define GAS_CRESP_OFFSET	5
++
++bool wl_cfgp2p_find_gas_subtype(u8 subtype, u8* data, u32 len)
++{
++	bcm_tlv_t *ie = (bcm_tlv_t *)data;
++	u8 *frame = NULL;
++	u16 id, flen;
++
++	/* Skipped first ANQP Element, if frame has anqp elemnt */
++	ie = bcm_parse_tlvs(ie, (int)len, DOT11_MNG_ADVERTISEMENT_ID);
++
++	if (ie == NULL)
++		return false;
++
++	frame = (uint8 *)ie + ie->len + TLV_HDR_LEN + GAS_RESP_LEN;
++	id = ((u16) (((frame)[1] << 8) | (frame)[0]));
++	flen = ((u16) (((frame)[3] << 8) | (frame)[2]));
++
++	/* If the contents match the OUI and the type */
++	if (flen >= WFA_OUI_LEN + 1 &&
++		id ==  P2PSD_GAS_NQP_INFOID &&
++		!bcmp(&frame[DOUBLE_TLV_BODY_OFF], (const uint8*)WFA_OUI, WFA_OUI_LEN) &&
++		subtype == frame[DOUBLE_TLV_BODY_OFF+WFA_OUI_LEN]) {
++		return true;
++	}
++
++	return false;
++}
++
++bool wl_cfgp2p_is_gas_action(void *frame, u32 frame_len)
++{
++
++	wifi_p2psd_gas_pub_act_frame_t *sd_act_frm;
++
++	if (frame == NULL)
++		return false;
++
++	sd_act_frm = (wifi_p2psd_gas_pub_act_frame_t *)frame;
++	if (frame_len < (sizeof(wifi_p2psd_gas_pub_act_frame_t) - 1))
++		return false;
++	if (sd_act_frm->category != P2PSD_ACTION_CATEGORY)
++		return false;
++
++#ifdef WL11U
++	if (sd_act_frm->action == P2PSD_ACTION_ID_GAS_IRESP)
++		return wl_cfgp2p_find_gas_subtype(P2PSD_GAS_OUI_SUBTYPE,
++			(u8 *)sd_act_frm->query_data + GAS_RESP_OFFSET,
++			frame_len);
++
++	else if (sd_act_frm->action == P2PSD_ACTION_ID_GAS_CRESP)
++		return wl_cfgp2p_find_gas_subtype(P2PSD_GAS_OUI_SUBTYPE,
++			(u8 *)sd_act_frm->query_data + GAS_CRESP_OFFSET,
++			frame_len);
++	else if (sd_act_frm->action == P2PSD_ACTION_ID_GAS_IREQ ||
++		sd_act_frm->action == P2PSD_ACTION_ID_GAS_CREQ)
++		return true;
++	else
++		return false;
++#else
++	if (sd_act_frm->action == P2PSD_ACTION_ID_GAS_IREQ ||
++		sd_act_frm->action == P2PSD_ACTION_ID_GAS_IRESP ||
++		sd_act_frm->action == P2PSD_ACTION_ID_GAS_CREQ ||
++		sd_act_frm->action == P2PSD_ACTION_ID_GAS_CRESP)
++		return true;
++	else
++		return false;
++#endif /* WL11U */
++}
++
++bool wl_cfgp2p_is_p2p_gas_action(void *frame, u32 frame_len)
++{
++
++	wifi_p2psd_gas_pub_act_frame_t *sd_act_frm;
++
++	if (frame == NULL)
++		return false;
++
++	sd_act_frm = (wifi_p2psd_gas_pub_act_frame_t *)frame;
++	if (frame_len < (sizeof(wifi_p2psd_gas_pub_act_frame_t) - 1))
++		return false;
++	if (sd_act_frm->category != P2PSD_ACTION_CATEGORY)
++		return false;
++
++	if (sd_act_frm->action == P2PSD_ACTION_ID_GAS_IREQ)
++		return wl_cfgp2p_find_gas_subtype(P2PSD_GAS_OUI_SUBTYPE,
++			(u8 *)sd_act_frm->query_data,
++			frame_len);
++	else
++		return false;
++}
++
++void wl_cfgp2p_print_actframe(bool tx, void *frame, u32 frame_len, u32 channel)
++{
++	wifi_p2p_pub_act_frame_t *pact_frm;
++	wifi_p2p_action_frame_t *act_frm;
++	wifi_p2psd_gas_pub_act_frame_t *sd_act_frm;
++	if (!frame || frame_len <= 2)
++		return;
++
++	if (wl_cfgp2p_is_pub_action(frame, frame_len)) {
++		pact_frm = (wifi_p2p_pub_act_frame_t *)frame;
++		switch (pact_frm->subtype) {
++			case P2P_PAF_GON_REQ:
++				CFGP2P_ACTION(("%s P2P Group Owner Negotiation Req Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_PAF_GON_RSP:
++				CFGP2P_ACTION(("%s P2P Group Owner Negotiation Rsp Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_PAF_GON_CONF:
++				CFGP2P_ACTION(("%s P2P Group Owner Negotiation Confirm Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_PAF_INVITE_REQ:
++				CFGP2P_ACTION(("%s P2P Invitation Request  Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_PAF_INVITE_RSP:
++				CFGP2P_ACTION(("%s P2P Invitation Response Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_PAF_DEVDIS_REQ:
++				CFGP2P_ACTION(("%s P2P Device Discoverability Request Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_PAF_DEVDIS_RSP:
++				CFGP2P_ACTION(("%s P2P Device Discoverability Response Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_PAF_PROVDIS_REQ:
++				CFGP2P_ACTION(("%s P2P Provision Discovery Request Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_PAF_PROVDIS_RSP:
++				CFGP2P_ACTION(("%s P2P Provision Discovery Response Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			default:
++				CFGP2P_ACTION(("%s Unknown Public Action Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++
++		}
++
++	} else if (wl_cfgp2p_is_p2p_action(frame, frame_len)) {
++		act_frm = (wifi_p2p_action_frame_t *)frame;
++		switch (act_frm->subtype) {
++			case P2P_AF_NOTICE_OF_ABSENCE:
++				CFGP2P_ACTION(("%s P2P Notice of Absence Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_AF_PRESENCE_REQ:
++				CFGP2P_ACTION(("%s P2P Presence Request Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_AF_PRESENCE_RSP:
++				CFGP2P_ACTION(("%s P2P Presence Response Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_AF_GO_DISC_REQ:
++				CFGP2P_ACTION(("%s P2P Discoverability Request Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			default:
++				CFGP2P_ACTION(("%s Unknown P2P Action Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++		}
++
++	} else if (wl_cfgp2p_is_gas_action(frame, frame_len)) {
++		sd_act_frm = (wifi_p2psd_gas_pub_act_frame_t *)frame;
++		switch (sd_act_frm->action) {
++			case P2PSD_ACTION_ID_GAS_IREQ:
++				CFGP2P_ACTION(("%s GAS Initial Request,"
++					" channel=%d\n", (tx)? "TX" : "RX", channel));
++				break;
++			case P2PSD_ACTION_ID_GAS_IRESP:
++				CFGP2P_ACTION(("%s GAS Initial Response,"
++					" channel=%d\n", (tx)? "TX" : "RX", channel));
++				break;
++			case P2PSD_ACTION_ID_GAS_CREQ:
++				CFGP2P_ACTION(("%s GAS Comback Request,"
++					" channel=%d\n", (tx)? "TX" : "RX", channel));
++				break;
++			case P2PSD_ACTION_ID_GAS_CRESP:
++				CFGP2P_ACTION(("%s GAS Comback Response,"
++					" channel=%d\n", (tx)? "TX" : "RX", channel));
++				break;
++			default:
++				CFGP2P_ACTION(("%s Unknown GAS Frame,"
++					" channel=%d\n", (tx)? "TX" : "RX", channel));
++		}
++
++
++	}
++}
++
++/*
++ *  Initialize variables related to P2P
++ *
++ */
++s32
++wl_cfgp2p_init_priv(struct bcm_cfg80211 *cfg)
++{
++	if (!(cfg->p2p = kzalloc(sizeof(struct p2p_info), GFP_KERNEL))) {
++		CFGP2P_ERR(("struct p2p_info allocation failed\n"));
++		return -ENOMEM;
++	}
++
++	wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_PRIMARY) = bcmcfg_to_prmry_ndev(cfg);
++	wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_PRIMARY) = 0;
++	wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_DEVICE) = NULL;
++	wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE) = 0;
++	wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_CONNECTION1) = NULL;
++	wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_CONNECTION1) = -1;
++	wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_CONNECTION2) = NULL;
++	wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_CONNECTION2) = -1;
++	return BCME_OK;
++
++}
++/*
++ *  Deinitialize variables related to P2P
++ *
++ */
++void
++wl_cfgp2p_deinit_priv(struct bcm_cfg80211 *cfg)
++{
++	CFGP2P_ERR(("In\n"));
++	if (cfg->p2p) {
++		kfree(cfg->p2p);
++		cfg->p2p = NULL;
++	}
++	cfg->p2p_supported = 0;
++}
++/*
++ * Set P2P functions into firmware
++ */
++s32
++wl_cfgp2p_set_firm_p2p(struct bcm_cfg80211 *cfg)
++{
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	struct ether_addr null_eth_addr = { { 0, 0, 0, 0, 0, 0 } };
++	s32 ret = BCME_OK;
++	s32 val = 0;
++	/* Do we have to check whether APSTA is enabled or not ? */
++	ret = wldev_iovar_getint(ndev, "apsta", &val);
++	if (ret < 0) {
++		CFGP2P_ERR(("get apsta error %d\n", ret));
++		return ret;
++	}
++	if (val == 0) {
++		val = 1;
++		ret = wldev_ioctl_set(ndev, WLC_DOWN, &val, sizeof(s32));
++		if (ret < 0) {
++			CFGP2P_ERR(("WLC_DOWN error %d\n", ret));
++			return ret;
++		}
++
++		ret = wldev_iovar_setint(ndev, "apsta", val);
++		if (ret < 0) {
++			/* return error and fail the initialization */
++			CFGP2P_ERR(("wl apsta %d set error. ret: %d\n", val, ret));
++			return ret;
++		}
++
++		ret = wldev_ioctl_set(ndev, WLC_UP, &val, sizeof(s32));
++		if (ret < 0) {
++			CFGP2P_ERR(("WLC_UP error %d\n", ret));
++			return ret;
++		}
++	}
++
++	/* In case of COB type, firmware has default mac address
++	 * After Initializing firmware, we have to set current mac address to
++	 * firmware for P2P device address
++	 */
++	ret = wldev_iovar_setbuf_bsscfg(ndev, "p2p_da_override", &null_eth_addr,
++		sizeof(null_eth_addr), cfg->ioctl_buf, WLC_IOCTL_MAXLEN, 0, &cfg->ioctl_buf_sync);
++	if (ret && ret != BCME_UNSUPPORTED) {
++		CFGP2P_ERR(("failed to update device address ret %d\n", ret));
++	}
++	return ret;
++}
++
++int wl_cfg_multip2p_operational(struct bcm_cfg80211 *cfg)
++{
++	if (!cfg->p2p) {
++		CFGP2P_DBG(("p2p not enabled! \n"));
++		return false;
++	}
++
++	if ((wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_CONNECTION1) != -1) &&
++	    (wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_CONNECTION2) != -1))
++		return true;
++	else
++		return false;
++}
++
++/* Create a new P2P BSS.
++ * Parameters:
++ * @mac      : MAC address of the BSS to create
++ * @if_type  : interface type: WL_P2P_IF_GO or WL_P2P_IF_CLIENT
++ * @chspec   : chspec to use if creating a GO BSS.
++ * Returns 0 if success.
++ */
++s32
++wl_cfgp2p_ifadd(struct bcm_cfg80211 *cfg, struct ether_addr *mac, u8 if_type,
++            chanspec_t chspec)
++{
++	wl_p2p_if_t ifreq;
++	s32 err;
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++
++	ifreq.type = if_type;
++	ifreq.chspec = chspec;
++	memcpy(ifreq.addr.octet, mac->octet, sizeof(ifreq.addr.octet));
++
++	CFGP2P_ERR(("---cfg p2p_ifadd "MACDBG" %s %u\n",
++		MAC2STRDBG(ifreq.addr.octet),
++		(if_type == WL_P2P_IF_GO) ? "go" : "client",
++	        (chspec & WL_CHANSPEC_CHAN_MASK) >> WL_CHANSPEC_CHAN_SHIFT));
++
++	err = wldev_iovar_setbuf(ndev, "p2p_ifadd", &ifreq, sizeof(ifreq),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++	if (unlikely(err < 0)) {
++		printk("'cfg p2p_ifadd' error %d\n", err);
++		return err;
++	}
++
++	return err;
++}
++
++/* Disable a P2P BSS.
++ * Parameters:
++ * @mac      : MAC address of the BSS to disable
++ * Returns 0 if success.
++ */
++s32
++wl_cfgp2p_ifdisable(struct bcm_cfg80211 *cfg, struct ether_addr *mac)
++{
++	s32 ret;
++	struct net_device *netdev = bcmcfg_to_prmry_ndev(cfg);
++
++	CFGP2P_INFO(("------primary idx %d : cfg p2p_ifdis "MACDBG"\n",
++		netdev->ifindex, MAC2STRDBG(mac->octet)));
++	ret = wldev_iovar_setbuf(netdev, "p2p_ifdis", mac, sizeof(*mac),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++	if (unlikely(ret < 0)) {
++		printk("'cfg p2p_ifdis' error %d\n", ret);
++	}
++	return ret;
++}
++
++/* Delete a P2P BSS.
++ * Parameters:
++ * @mac      : MAC address of the BSS to delete
++ * Returns 0 if success.
++ */
++s32
++wl_cfgp2p_ifdel(struct bcm_cfg80211 *cfg, struct ether_addr *mac)
++{
++	s32 ret;
++	struct net_device *netdev = bcmcfg_to_prmry_ndev(cfg);
++
++	CFGP2P_ERR(("------primary idx %d : cfg p2p_ifdel "MACDBG"\n",
++	    netdev->ifindex, MAC2STRDBG(mac->octet)));
++	ret = wldev_iovar_setbuf(netdev, "p2p_ifdel", mac, sizeof(*mac),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++	if (unlikely(ret < 0)) {
++		printk("'cfg p2p_ifdel' error %d\n", ret);
++	}
++	return ret;
++}
++
++/* Change a P2P Role.
++ * Parameters:
++ * @mac      : MAC address of the BSS to change a role
++ * Returns 0 if success.
++ */
++s32
++wl_cfgp2p_ifchange(struct bcm_cfg80211 *cfg, struct ether_addr *mac, u8 if_type,
++            chanspec_t chspec, s32 conn_idx)
++{
++	wl_p2p_if_t ifreq;
++	s32 err;
++
++	struct net_device *netdev =  wl_to_p2p_bss_ndev(cfg, conn_idx);
++
++	ifreq.type = if_type;
++	ifreq.chspec = chspec;
++	memcpy(ifreq.addr.octet, mac->octet, sizeof(ifreq.addr.octet));
++
++	CFGP2P_INFO(("---cfg p2p_ifchange "MACDBG" %s %u"
++		" chanspec 0x%04x\n", MAC2STRDBG(ifreq.addr.octet),
++		(if_type == WL_P2P_IF_GO) ? "go" : "client",
++		(chspec & WL_CHANSPEC_CHAN_MASK) >> WL_CHANSPEC_CHAN_SHIFT,
++		ifreq.chspec));
++
++	err = wldev_iovar_setbuf(netdev, "p2p_ifupd", &ifreq, sizeof(ifreq),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++	if (unlikely(err < 0)) {
++		printk("'cfg p2p_ifupd' error %d\n", err);
++	} else if (if_type == WL_P2P_IF_GO) {
++		cfg->p2p->p2p_go_count++;
++	}
++	return err;
++}
++
++
++/* Get the index of a created P2P BSS.
++ * Parameters:
++ * @mac      : MAC address of the created BSS
++ * @index    : output: index of created BSS
++ * Returns 0 if success.
++ */
++s32
++wl_cfgp2p_ifidx(struct bcm_cfg80211 *cfg, struct ether_addr *mac, s32 *index)
++{
++	s32 ret;
++	u8 getbuf[64];
++	struct net_device *dev = bcmcfg_to_prmry_ndev(cfg);
++
++	CFGP2P_INFO(("---cfg p2p_if "MACDBG"\n", MAC2STRDBG(mac->octet)));
++
++	ret = wldev_iovar_getbuf_bsscfg(dev, "p2p_if", mac, sizeof(*mac), getbuf,
++		sizeof(getbuf), wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_PRIMARY), NULL);
++
++	if (ret == 0) {
++		memcpy(index, getbuf, sizeof(s32));
++		CFGP2P_INFO(("---cfg p2p_if   ==> %d\n", *index));
++	}
++
++	return ret;
++}
++
++static s32
++wl_cfgp2p_set_discovery(struct bcm_cfg80211 *cfg, s32 on)
++{
++	s32 ret = BCME_OK;
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	CFGP2P_DBG(("enter\n"));
++
++	ret = wldev_iovar_setint(ndev, "p2p_disc", on);
++
++	if (unlikely(ret < 0)) {
++		CFGP2P_ERR(("p2p_disc %d error %d\n", on, ret));
++	}
++
++	return ret;
++}
++
++/* Set the WL driver's P2P mode.
++ * Parameters :
++ * @mode      : is one of WL_P2P_DISC_ST_{SCAN,LISTEN,SEARCH}.
++ * @channel   : the channel to listen
++ * @listen_ms : the time (milli seconds) to wait
++ * @bssidx    : bss index for BSSCFG
++ * Returns 0 if success
++ */
++
++s32
++wl_cfgp2p_set_p2p_mode(struct bcm_cfg80211 *cfg, u8 mode, u32 channel, u16 listen_ms, int bssidx)
++{
++	wl_p2p_disc_st_t discovery_mode;
++	s32 ret;
++	struct net_device *dev;
++	CFGP2P_DBG(("enter\n"));
++
++	if (unlikely(bssidx == WL_INVALID)) {
++		CFGP2P_ERR((" %d index out of range\n", bssidx));
++		return -1;
++	}
++
++	dev = wl_cfgp2p_find_ndev(cfg, bssidx);
++	if (unlikely(dev == NULL)) {
++		CFGP2P_ERR(("bssidx %d is not assigned\n", bssidx));
++		return BCME_NOTFOUND;
++	}
++
++#ifdef P2PLISTEN_AP_SAMECHN
++	CFGP2P_DBG(("p2p0 listen channel %d  AP connection chan %d \n",
++		channel, cfg->channel));
++	if ((mode == WL_P2P_DISC_ST_LISTEN) && (cfg->channel == channel)) {
++		struct net_device *primary_ndev = bcmcfg_to_prmry_ndev(cfg);
++
++		if (cfg->p2p_resp_apchn_status) {
++			CFGP2P_DBG(("p2p_resp_apchn_status already ON \n"));
++			return BCME_OK;
++		}
++
++		if (wl_get_drv_status(cfg, CONNECTED, primary_ndev)) {
++			ret = wl_cfg80211_set_p2p_resp_ap_chn(primary_ndev, 1);
++			cfg->p2p_resp_apchn_status = true;
++			CFGP2P_DBG(("p2p_resp_apchn_status ON \n"));
++			return ret;
++		}
++	}
++#endif /* P2PLISTEN_AP_SAMECHN */
++
++	/* Put the WL driver into P2P Listen Mode to respond to P2P probe reqs */
++	discovery_mode.state = mode;
++	discovery_mode.chspec = wl_ch_host_to_driver(cfg, bssidx, channel);
++	discovery_mode.dwell = listen_ms;
++	ret = wldev_iovar_setbuf_bsscfg(dev, "p2p_state", &discovery_mode,
++		sizeof(discovery_mode), cfg->ioctl_buf, WLC_IOCTL_MAXLEN,
++		bssidx, &cfg->ioctl_buf_sync);
++
++	return ret;
++}
++
++/* Get the index of the P2P Discovery BSS */
++static s32
++wl_cfgp2p_get_disc_idx(struct bcm_cfg80211 *cfg, s32 *index)
++{
++	s32 ret;
++	struct net_device *dev = wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_PRIMARY);
++
++	ret = wldev_iovar_getint(dev, "p2p_dev", index);
++	CFGP2P_INFO(("p2p_dev bsscfg_idx=%d ret=%d\n", *index, ret));
++
++	if (unlikely(ret <  0)) {
++	    CFGP2P_ERR(("'p2p_dev' error %d\n", ret));
++		return ret;
++	}
++	return ret;
++}
++
++int wl_cfgp2p_get_conn_idx(struct bcm_cfg80211 *cfg)
++{
++	int i;
++	s32 connected_cnt;
++	dhd_pub_t *dhd =  (dhd_pub_t *)(cfg->pub);
++	if (!dhd)
++		return (-ENODEV);
++	for (i = P2PAPI_BSSCFG_CONNECTION1; i < P2PAPI_BSSCFG_MAX; i++) {
++		if (wl_to_p2p_bss_bssidx(cfg, i) == -1) {
++			if (i == P2PAPI_BSSCFG_CONNECTION2) {
++				if (!(dhd->op_mode & DHD_FLAG_MP2P_MODE)) {
++					CFGP2P_ERR(("Multi p2p not supported"));
++					return BCME_ERROR;
++				}
++				if ((connected_cnt = wl_get_drv_status_all(cfg, CONNECTED)) > 1) {
++					CFGP2P_ERR(("Failed to create second p2p interface"
++						"Already one connection exists"));
++					return BCME_ERROR;
++				}
++			}
++		return i;
++		}
++	}
++	return BCME_ERROR;
++}
++
++s32
++wl_cfgp2p_init_discovery(struct bcm_cfg80211 *cfg)
++{
++
++	s32 bssidx = 0;
++	s32 ret = BCME_OK;
++
++	CFGP2P_DBG(("enter\n"));
++
++	if (wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE) > 0) {
++		CFGP2P_ERR(("do nothing, already initialized\n"));
++		return ret;
++	}
++
++	ret = wl_cfgp2p_set_discovery(cfg, 1);
++	if (ret < 0) {
++		CFGP2P_ERR(("set discover error\n"));
++		return ret;
++	}
++	/* Enable P2P Discovery in the WL Driver */
++	ret = wl_cfgp2p_get_disc_idx(cfg, &bssidx);
++
++	if (ret < 0) {
++		return ret;
++	}
++	/* In case of CFG80211 case, check if p2p_discovery interface has allocated p2p_wdev */
++	if (!cfg->p2p_wdev) {
++		CFGP2P_ERR(("p2p_wdev is NULL.\n"));
++		return BCME_NODEVICE;
++	}
++	/* Make an entry in the netinfo */
++	ret = wl_alloc_netinfo(cfg, NULL, cfg->p2p_wdev, WL_MODE_BSS, 0, bssidx);
++	if (unlikely(ret)) {
++		return ret;
++	}
++
++	wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_DEVICE) =
++	    wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_PRIMARY);
++	wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE) = bssidx;
++
++	/* Set the initial discovery state to SCAN */
++	ret = wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_SCAN, 0, 0,
++		wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE));
++
++	if (unlikely(ret != 0)) {
++		CFGP2P_ERR(("unable to set WL_P2P_DISC_ST_SCAN\n"));
++		wl_cfgp2p_set_discovery(cfg, 0);
++		wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE) = 0;
++		wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_DEVICE) = NULL;
++		return 0;
++	}
++	return ret;
++}
++
++/* Deinitialize P2P Discovery
++ * Parameters :
++ * @cfg        : wl_private data
++ * Returns 0 if succes
++ */
++static s32
++wl_cfgp2p_deinit_discovery(struct bcm_cfg80211 *cfg)
++{
++	s32 ret = BCME_OK;
++	s32 bssidx;
++
++	CFGP2P_DBG(("enter\n"));
++	bssidx = wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++	if (bssidx <= 0) {
++		CFGP2P_ERR(("do nothing, not initialized\n"));
++		return -1;
++	}
++
++	/* Clear our saved WPS and P2P IEs for the discovery BSS */
++	wl_cfg80211_clear_per_bss_ies(cfg, bssidx);
++
++	/* Set the discovery state to SCAN */
++	wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_SCAN, 0, 0,
++	            bssidx);
++	/* Disable P2P discovery in the WL driver (deletes the discovery BSSCFG) */
++	ret = wl_cfgp2p_set_discovery(cfg, 0);
++
++	/* Remove the p2p disc entry in the netinfo */
++	wl_dealloc_netinfo_by_wdev(cfg, cfg->p2p_wdev);
++
++	wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE) = WL_INVALID;
++	wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_DEVICE) = NULL;
++
++	return ret;
++
++}
++/* Enable P2P Discovery
++ * Parameters:
++ * @cfg	: wl_private data
++ * @ie  : probe request ie (WPS IE + P2P IE)
++ * @ie_len   : probe request ie length
++ * Returns 0 if success.
++ */
++s32
++wl_cfgp2p_enable_discovery(struct bcm_cfg80211 *cfg, struct net_device *dev,
++	const u8 *ie, u32 ie_len)
++{
++	s32 ret = BCME_OK;
++	s32 bssidx;
++
++	CFGP2P_DBG(("enter\n"));
++	if (wl_get_p2p_status(cfg, DISCOVERY_ON)) {
++		CFGP2P_INFO((" DISCOVERY is already initialized, we have nothing to do\n"));
++		goto set_ie;
++	}
++
++	ret = wl_cfgp2p_init_discovery(cfg);
++	if (unlikely(ret < 0)) {
++		CFGP2P_ERR((" init discovery error %d\n", ret));
++		goto exit;
++	}
++
++	wl_set_p2p_status(cfg, DISCOVERY_ON);
++	/* Set wsec to any non-zero value in the discovery bsscfg to ensure our
++	 * P2P probe responses have the privacy bit set in the 802.11 WPA IE.
++	 * Some peer devices may not initiate WPS with us if this bit is not set.
++	 */
++	ret = wldev_iovar_setint_bsscfg(wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_DEVICE),
++			"wsec", AES_ENABLED, wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE));
++	if (unlikely(ret < 0)) {
++		CFGP2P_ERR((" wsec error %d\n", ret));
++	}
++set_ie:
++	if (ie_len) {
++
++		if (bcmcfg_to_prmry_ndev(cfg) == dev) {
++			bssidx = wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++		} else if ((bssidx = wl_get_bssidx_by_wdev(cfg, cfg->p2p_wdev)) < 0) {
++			WL_ERR(("Find p2p index from wdev(%p) failed\n", cfg->p2p_wdev));
++			return BCME_ERROR;
++		}
++
++		ret = wl_cfg80211_set_mgmt_vndr_ies(cfg, ndev_to_cfgdev(dev),
++			bssidx,
++			VNDR_IE_PRBREQ_FLAG, ie, ie_len);
++
++		if (unlikely(ret < 0)) {
++			CFGP2P_ERR(("set probreq ie occurs error %d\n", ret));
++			goto exit;
++		}
++	}
++exit:
++	return ret;
++}
++
++/* Disable P2P Discovery
++ * Parameters:
++ * @cfg       : wl_private_data
++ * Returns 0 if success.
++ */
++s32
++wl_cfgp2p_disable_discovery(struct bcm_cfg80211 *cfg)
++{
++	s32 ret = BCME_OK;
++	s32 bssidx;
++
++	CFGP2P_DBG((" enter\n"));
++	wl_clr_p2p_status(cfg, DISCOVERY_ON);
++
++	if (!cfg->p2p) { // terence 20130113: Fix for p2p NULL pointer
++		ret = BCME_ERROR;
++		CFGP2P_ERR(("wl->p2p is NULL\n"));
++		goto exit;
++	}
++
++#ifdef DHD_IFDEBUG
++	WL_ERR(("%s: (cfg)->p2p->bss[type].bssidx: %d\n",
++		__FUNCTION__, (cfg)->p2p->bss[P2PAPI_BSSCFG_DEVICE].bssidx));
++#endif
++	bssidx = wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++	if (bssidx <= 0) {
++		CFGP2P_ERR((" do nothing, not initialized\n"));
++		return 0;
++	}
++
++	ret = wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_SCAN, 0, 0, bssidx);
++	if (unlikely(ret < 0)) {
++		CFGP2P_ERR(("unable to set WL_P2P_DISC_ST_SCAN\n"));
++	}
++	/* Do a scan abort to stop the driver's scan engine in case it is still
++	 * waiting out an action frame tx dwell time.
++	 */
++	wl_clr_p2p_status(cfg, DISCOVERY_ON);
++	ret = wl_cfgp2p_deinit_discovery(cfg);
++
++exit:
++	return ret;
++}
++
++s32
++wl_cfgp2p_escan(struct bcm_cfg80211 *cfg, struct net_device *dev, u16 active,
++	u32 num_chans, u16 *channels,
++	s32 search_state, u16 action, u32 bssidx, struct ether_addr *tx_dst_addr,
++	p2p_scan_purpose_t p2p_scan_purpose)
++{
++	s32 ret = BCME_OK;
++	s32 memsize;
++	s32 eparams_size;
++	u32 i;
++	s8 *memblk;
++	wl_p2p_scan_t *p2p_params;
++	wl_escan_params_t *eparams;
++	wlc_ssid_t ssid;
++	/* Scan parameters */
++#define P2PAPI_SCAN_NPROBES 1
++#define P2PAPI_SCAN_DWELL_TIME_MS 80
++#define P2PAPI_SCAN_SOCIAL_DWELL_TIME_MS 40
++#define P2PAPI_SCAN_HOME_TIME_MS 60
++#define P2PAPI_SCAN_NPROBS_TIME_MS 30
++#define P2PAPI_SCAN_AF_SEARCH_DWELL_TIME_MS 100
++
++	struct net_device *pri_dev = wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_PRIMARY);
++	/* Allocate scan params which need space for 3 channels and 0 ssids */
++	eparams_size = (WL_SCAN_PARAMS_FIXED_SIZE +
++	    OFFSETOF(wl_escan_params_t, params)) +
++		num_chans * sizeof(eparams->params.channel_list[0]);
++
++	memsize = sizeof(wl_p2p_scan_t) + eparams_size;
++	memblk = scanparambuf;
++	if (memsize > sizeof(scanparambuf)) {
++		CFGP2P_ERR((" scanpar buf too small (%u > %zu)\n",
++		    memsize, sizeof(scanparambuf)));
++		return -1;
++	}
++	memset(memblk, 0, memsize);
++	memset(cfg->ioctl_buf, 0, WLC_IOCTL_MAXLEN);
++	if (search_state == WL_P2P_DISC_ST_SEARCH) {
++		/*
++		 * If we in SEARCH STATE, we don't need to set SSID explictly
++		 * because dongle use P2P WILDCARD internally by default
++		 */
++		wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_SEARCH, 0, 0, bssidx);
++		/* use null ssid */
++		ssid.SSID_len = 0;
++		memset(&ssid.SSID, 0, sizeof(ssid.SSID));
++	} else if (search_state == WL_P2P_DISC_ST_SCAN) {
++		/* SCAN STATE 802.11 SCAN
++		 * WFD Supplicant has p2p_find command with (type=progressive, type= full)
++		 * So if P2P_find command with type=progressive,
++		 * we have to set ssid to P2P WILDCARD because
++		 * we just do broadcast scan unless setting SSID
++		 */
++		wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_SCAN, 0, 0, bssidx);
++		/* use wild card ssid */
++		ssid.SSID_len = WL_P2P_WILDCARD_SSID_LEN;
++		memset(&ssid.SSID, 0, sizeof(ssid.SSID));
++		memcpy(&ssid.SSID, WL_P2P_WILDCARD_SSID, WL_P2P_WILDCARD_SSID_LEN);
++	} else {
++		CFGP2P_ERR((" invalid search state %d\n", search_state));
++		return -1;
++	}
++
++
++	/* Fill in the P2P scan structure at the start of the iovar param block */
++	p2p_params = (wl_p2p_scan_t*) memblk;
++	p2p_params->type = 'E';
++	/* Fill in the Scan structure that follows the P2P scan structure */
++	eparams = (wl_escan_params_t*) (p2p_params + 1);
++	eparams->params.bss_type = DOT11_BSSTYPE_ANY;
++	if (active)
++		eparams->params.scan_type = DOT11_SCANTYPE_ACTIVE;
++	else
++		eparams->params.scan_type = DOT11_SCANTYPE_PASSIVE;
++
++	if (tx_dst_addr == NULL)
++		memcpy(&eparams->params.bssid, &ether_bcast, ETHER_ADDR_LEN);
++	else
++		memcpy(&eparams->params.bssid, tx_dst_addr, ETHER_ADDR_LEN);
++
++	if (ssid.SSID_len)
++		memcpy(&eparams->params.ssid, &ssid, sizeof(wlc_ssid_t));
++
++	eparams->params.home_time = htod32(P2PAPI_SCAN_HOME_TIME_MS);
++
++	switch (p2p_scan_purpose) {
++		case P2P_SCAN_SOCIAL_CHANNEL:
++		eparams->params.active_time = htod32(P2PAPI_SCAN_SOCIAL_DWELL_TIME_MS);
++			break;
++		case P2P_SCAN_AFX_PEER_NORMAL:
++		case P2P_SCAN_AFX_PEER_REDUCED:
++		eparams->params.active_time = htod32(P2PAPI_SCAN_AF_SEARCH_DWELL_TIME_MS);
++			break;
++		case P2P_SCAN_CONNECT_TRY:
++			eparams->params.active_time = htod32(WL_SCAN_CONNECT_DWELL_TIME_MS);
++			break;
++		default :
++			if (wl_get_drv_status_all(cfg, CONNECTED))
++		eparams->params.active_time = -1;
++	else
++		eparams->params.active_time = htod32(P2PAPI_SCAN_DWELL_TIME_MS);
++			break;
++	}
++
++	if (p2p_scan_purpose == P2P_SCAN_CONNECT_TRY)
++		eparams->params.nprobes = htod32(eparams->params.active_time /
++			WL_SCAN_JOIN_PROBE_INTERVAL_MS);
++	else
++	eparams->params.nprobes = htod32((eparams->params.active_time /
++		P2PAPI_SCAN_NPROBS_TIME_MS));
++
++
++	if (eparams->params.nprobes <= 0)
++		eparams->params.nprobes = 1;
++	CFGP2P_DBG(("nprobes # %d, active_time %d\n",
++		eparams->params.nprobes, eparams->params.active_time));
++	eparams->params.passive_time = htod32(-1);
++	eparams->params.channel_num = htod32((0 << WL_SCAN_PARAMS_NSSID_SHIFT) |
++	    (num_chans & WL_SCAN_PARAMS_COUNT_MASK));
++
++	for (i = 0; i < num_chans; i++) {
++		eparams->params.channel_list[i] = wl_ch_host_to_driver(cfg, bssidx, channels[i]);
++	}
++	eparams->version = htod32(ESCAN_REQ_VERSION);
++	eparams->action =  htod16(action);
++	wl_escan_set_sync_id(eparams->sync_id, cfg);
++	wl_escan_set_type(cfg, WL_SCANTYPE_P2P);
++	CFGP2P_INFO(("SCAN CHANNELS : "));
++
++	for (i = 0; i < num_chans; i++) {
++		if (i == 0) CFGP2P_INFO(("%d", channels[i]));
++		else CFGP2P_INFO((",%d", channels[i]));
++	}
++
++	CFGP2P_INFO(("\n"));
++
++	ret = wldev_iovar_setbuf_bsscfg(pri_dev, "p2p_scan",
++		memblk, memsize, cfg->ioctl_buf, WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++	printf("%s: P2P_SEARCH sync ID: %d, bssidx: %d\n", __FUNCTION__, eparams->sync_id, bssidx);
++	if (ret == BCME_OK)
++		wl_set_p2p_status(cfg, SCANNING);
++	return ret;
++}
++
++/* search function to reach at common channel to send action frame
++ * Parameters:
++ * @cfg       : wl_private data
++ * @ndev     : net device for bssidx
++ * @bssidx   : bssidx for BSS
++ * Returns 0 if success.
++ */
++s32
++wl_cfgp2p_act_frm_search(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	s32 bssidx, s32 channel, struct ether_addr *tx_dst_addr)
++{
++	s32 ret = 0;
++	u32 chan_cnt = 0;
++	u16 *default_chan_list = NULL;
++	p2p_scan_purpose_t p2p_scan_purpose = P2P_SCAN_AFX_PEER_NORMAL;
++	if (!p2p_is_on(cfg) || ndev == NULL || bssidx == WL_INVALID)
++		return -EINVAL;
++	WL_TRACE_HW4((" Enter\n"));
++	if (bssidx == wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_PRIMARY))
++		bssidx = wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++	if (channel)
++		chan_cnt = AF_PEER_SEARCH_CNT;
++	else
++		chan_cnt = SOCIAL_CHAN_CNT;
++
++	if (cfg->afx_hdl->pending_tx_act_frm && cfg->afx_hdl->is_active) {
++		wl_action_frame_t *action_frame;
++		action_frame = &(cfg->afx_hdl->pending_tx_act_frm->action_frame);
++		if (wl_cfgp2p_is_p2p_gas_action(action_frame->data, action_frame->len))	{
++			chan_cnt = 1;
++			p2p_scan_purpose = P2P_SCAN_AFX_PEER_REDUCED;
++		}
++	}
++
++	default_chan_list = kzalloc(chan_cnt * sizeof(*default_chan_list), GFP_KERNEL);
++	if (default_chan_list == NULL) {
++		CFGP2P_ERR(("channel list allocation failed \n"));
++		ret = -ENOMEM;
++		goto exit;
++	}
++	if (channel) {
++		u32 i;
++		/* insert same channel to the chan_list */
++		for (i = 0; i < chan_cnt; i++) {
++			default_chan_list[i] = channel;
++		}
++	} else {
++		default_chan_list[0] = SOCIAL_CHAN_1;
++		default_chan_list[1] = SOCIAL_CHAN_2;
++		default_chan_list[2] = SOCIAL_CHAN_3;
++	}
++	ret = wl_cfgp2p_escan(cfg, ndev, true, chan_cnt,
++		default_chan_list, WL_P2P_DISC_ST_SEARCH,
++		WL_SCAN_ACTION_START, bssidx, NULL, p2p_scan_purpose);
++	kfree(default_chan_list);
++exit:
++	return ret;
++}
++
++/* Check whether pointed-to IE looks like WPA. */
++#define wl_cfgp2p_is_wpa_ie(ie, tlvs, len)	wl_cfgp2p_has_ie(ie, tlvs, len, \
++		(const uint8 *)WPS_OUI, WPS_OUI_LEN, WPA_OUI_TYPE)
++/* Check whether pointed-to IE looks like WPS. */
++#define wl_cfgp2p_is_wps_ie(ie, tlvs, len)	wl_cfgp2p_has_ie(ie, tlvs, len, \
++		(const uint8 *)WPS_OUI, WPS_OUI_LEN, WPS_OUI_TYPE)
++/* Check whether the given IE looks like WFA P2P IE. */
++#define wl_cfgp2p_is_p2p_ie(ie, tlvs, len)	wl_cfgp2p_has_ie(ie, tlvs, len, \
++		(const uint8 *)WFA_OUI, WFA_OUI_LEN, WFA_OUI_TYPE_P2P)
++/* Check whether the given IE looks like WFA WFDisplay IE. */
++#ifndef WFA_OUI_TYPE_WFD
++#define WFA_OUI_TYPE_WFD	0x0a			/* WiFi Display OUI TYPE */
++#endif
++#define wl_cfgp2p_is_wfd_ie(ie, tlvs, len)	wl_cfgp2p_has_ie(ie, tlvs, len, \
++		(const uint8 *)WFA_OUI, WFA_OUI_LEN, WFA_OUI_TYPE_WFD)
++
++
++/* Is any of the tlvs the expected entry? If
++ * not update the tlvs buffer pointer/length.
++ */
++static bool
++wl_cfgp2p_has_ie(u8 *ie, u8 **tlvs, u32 *tlvs_len, const u8 *oui, u32 oui_len, u8 type)
++{
++	/* If the contents match the OUI and the type */
++	if (ie[TLV_LEN_OFF] >= oui_len + 1 &&
++		!bcmp(&ie[TLV_BODY_OFF], oui, oui_len) &&
++		type == ie[TLV_BODY_OFF + oui_len]) {
++		return TRUE;
++	}
++
++	if (tlvs == NULL)
++		return FALSE;
++	/* point to the next ie */
++	ie += ie[TLV_LEN_OFF] + TLV_HDR_LEN;
++	/* calculate the length of the rest of the buffer */
++	*tlvs_len -= (int)(ie - *tlvs);
++	/* update the pointer to the start of the buffer */
++	*tlvs = ie;
++
++	return FALSE;
++}
++
++wpa_ie_fixed_t *
++wl_cfgp2p_find_wpaie(u8 *parse, u32 len)
++{
++	bcm_tlv_t *ie;
++
++	while ((ie = bcm_parse_tlvs(parse, (u32)len, DOT11_MNG_VS_ID))) {
++		if (wl_cfgp2p_is_wpa_ie((u8*)ie, &parse, &len)) {
++			return (wpa_ie_fixed_t *)ie;
++		}
++	}
++	return NULL;
++}
++
++wpa_ie_fixed_t *
++wl_cfgp2p_find_wpsie(u8 *parse, u32 len)
++{
++	bcm_tlv_t *ie;
++
++	while ((ie = bcm_parse_tlvs(parse, (u32)len, DOT11_MNG_VS_ID))) {
++		if (wl_cfgp2p_is_wps_ie((u8*)ie, &parse, &len)) {
++			return (wpa_ie_fixed_t *)ie;
++		}
++	}
++	return NULL;
++}
++
++wifi_p2p_ie_t *
++wl_cfgp2p_find_p2pie(u8 *parse, u32 len)
++{
++	bcm_tlv_t *ie;
++
++	while ((ie = bcm_parse_tlvs(parse, (int)len, DOT11_MNG_VS_ID))) {
++		if (wl_cfgp2p_is_p2p_ie((uint8*)ie, &parse, &len)) {
++			return (wifi_p2p_ie_t *)ie;
++		}
++	}
++	return NULL;
++}
++
++wifi_wfd_ie_t *
++wl_cfgp2p_find_wfdie(u8 *parse, u32 len)
++{
++	bcm_tlv_t *ie;
++
++	while ((ie = bcm_parse_tlvs(parse, (int)len, DOT11_MNG_VS_ID))) {
++		if (wl_cfgp2p_is_wfd_ie((uint8*)ie, &parse, &len)) {
++			return (wifi_wfd_ie_t *)ie;
++		}
++	}
++	return NULL;
++}
++u32
++wl_cfgp2p_vndr_ie(struct bcm_cfg80211 *cfg, u8 *iebuf, s32 pktflag,
++            s8 *oui, s32 ie_id, s8 *data, s32 datalen, const s8* add_del_cmd)
++{
++	vndr_ie_setbuf_t hdr;	/* aligned temporary vndr_ie buffer header */
++	s32 iecount;
++	u32 data_offset;
++
++	/* Validate the pktflag parameter */
++	if ((pktflag & ~(VNDR_IE_BEACON_FLAG | VNDR_IE_PRBRSP_FLAG |
++	            VNDR_IE_ASSOCRSP_FLAG | VNDR_IE_AUTHRSP_FLAG |
++	            VNDR_IE_PRBREQ_FLAG | VNDR_IE_ASSOCREQ_FLAG))) {
++		CFGP2P_ERR(("p2pwl_vndr_ie: Invalid packet flag 0x%x\n", pktflag));
++		return -1;
++	}
++
++	/* Copy the vndr_ie SET command ("add"/"del") to the buffer */
++	strncpy(hdr.cmd, add_del_cmd, VNDR_IE_CMD_LEN - 1);
++	hdr.cmd[VNDR_IE_CMD_LEN - 1] = '\0';
++
++	/* Set the IE count - the buffer contains only 1 IE */
++	iecount = htod32(1);
++	memcpy((void *)&hdr.vndr_ie_buffer.iecount, &iecount, sizeof(s32));
++
++	/* Copy packet flags that indicate which packets will contain this IE */
++	pktflag = htod32(pktflag);
++	memcpy((void *)&hdr.vndr_ie_buffer.vndr_ie_list[0].pktflag, &pktflag,
++		sizeof(u32));
++
++	/* Add the IE ID to the buffer */
++	hdr.vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.id = ie_id;
++
++	/* Add the IE length to the buffer */
++	hdr.vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.len =
++		(uint8) VNDR_IE_MIN_LEN + datalen;
++
++	/* Add the IE OUI to the buffer */
++	hdr.vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.oui[0] = oui[0];
++	hdr.vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.oui[1] = oui[1];
++	hdr.vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.oui[2] = oui[2];
++
++	/* Copy the aligned temporary vndr_ie buffer header to the IE buffer */
++	memcpy(iebuf, &hdr, sizeof(hdr) - 1);
++
++	/* Copy the IE data to the IE buffer */
++	data_offset =
++		(u8*)&hdr.vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.data[0] -
++		(u8*)&hdr;
++	memcpy(iebuf + data_offset, data, datalen);
++	return data_offset + datalen;
++
++}
++
++struct net_device *
++wl_cfgp2p_find_ndev(struct bcm_cfg80211 *cfg, s32 bssidx)
++{
++	u32 i;
++	struct net_device *ndev = NULL;
++	if (bssidx < 0) {
++		CFGP2P_ERR((" bsscfg idx is invalid\n"));
++		goto exit;
++	}
++
++	for (i = 0; i < P2PAPI_BSSCFG_MAX; i++) {
++		if (bssidx == wl_to_p2p_bss_bssidx(cfg, i)) {
++			ndev = wl_to_p2p_bss_ndev(cfg, i);
++			break;
++		}
++	}
++
++exit:
++	return ndev;
++}
++/*
++ * Search the driver array idx based on bssidx argument
++ * Parameters: Note that this idx is applicable only
++ * for primary and P2P interfaces. The virtual AP/STA is not
++ * covered here.
++ * @cfg     : wl_private data
++ * @bssidx : bssidx which indicate bsscfg->idx of firmware.
++ * @type   : output arg to store array idx of p2p->bss.
++ * Returns error
++ */
++
++s32
++wl_cfgp2p_find_type(struct bcm_cfg80211 *cfg, s32 bssidx, s32 *type)
++{
++	u32 i;
++	if (bssidx < 0 || type == NULL) {
++		CFGP2P_ERR((" argument is invalid\n"));
++		goto exit;
++	}
++
++	for (i = 0; i < P2PAPI_BSSCFG_MAX; i++) {
++		if (bssidx == wl_to_p2p_bss_bssidx(cfg, i)) {
++			*type = i;
++			return BCME_OK;
++		}
++	}
++
++exit:
++	return BCME_BADARG;
++}
++
++/*
++ * Callback function for WLC_E_P2P_DISC_LISTEN_COMPLETE
++ */
++s32
++wl_cfgp2p_listen_complete(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	s32 ret = BCME_OK;
++	struct net_device *ndev = NULL;
++
++	if (!cfg || !cfg->p2p || !cfgdev)
++		return BCME_ERROR;
++
++	CFGP2P_DBG((" Enter\n"));
++#ifdef DHD_IFDEBUG
++	PRINT_WDEV_INFO(cfgdev);
++#endif /* DHD_IFDEBUG */
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++#ifdef P2P_LISTEN_OFFLOADING
++	if (wl_get_p2p_status(cfg, DISC_IN_PROGRESS)) {
++		wl_clr_p2p_status(cfg, DISC_IN_PROGRESS);
++		CFGP2P_ERR(("DISC_IN_PROGRESS cleared\n"));
++		if (ndev && (ndev->ieee80211_ptr != NULL)) {
++#if defined(WL_CFG80211_P2P_DEV_IF)
++			if (cfgdev && ((struct wireless_dev *)cfgdev)->wiphy) {
++				cfg80211_remain_on_channel_expired(cfgdev, cfg->last_roc_id,
++						&cfg->remain_on_chan, GFP_KERNEL);
++			} else {
++				CFGP2P_ERR(("Invalid cfgdev. Dropping the"
++						"remain_on_channel_expired event.\n"));
++			}
++#else
++			cfg80211_remain_on_channel_expired(cfgdev, cfg->last_roc_id,
++					&cfg->remain_on_chan, cfg->remain_on_chan_type, GFP_KERNEL);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++		}
++	}
++#endif /* P2P_LISTEN_OFFLOADING */
++
++	if (wl_get_p2p_status(cfg, LISTEN_EXPIRED) == 0) {
++		wl_set_p2p_status(cfg, LISTEN_EXPIRED);
++		if (timer_pending(&cfg->p2p->listen_timer)) {
++			_del_timer_sync(&cfg->p2p->listen_timer);
++		}
++
++		if (cfg->afx_hdl->is_listen == TRUE &&
++			wl_get_drv_status_all(cfg, FINDING_COMMON_CHANNEL)) {
++			WL_DBG(("Listen DONE for action frame\n"));
++			complete(&cfg->act_frm_scan);
++		}
++#ifdef WL_CFG80211_SYNC_GON
++		else if (wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM_LISTEN)) {
++			wl_clr_drv_status(cfg, WAITING_NEXT_ACT_FRM_LISTEN, ndev);
++			WL_DBG(("Listen DONE and wake up wait_next_af !!(%d)\n",
++				jiffies_to_msecs(jiffies - cfg->af_tx_sent_jiffies)));
++
++			if (wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM))
++				wl_clr_drv_status(cfg, WAITING_NEXT_ACT_FRM, ndev);
++
++			complete(&cfg->wait_next_af);
++		}
++#endif /* WL_CFG80211_SYNC_GON */
++
++#ifndef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++		if (wl_get_drv_status_all(cfg, REMAINING_ON_CHANNEL))
++#else
++		if (wl_get_drv_status_all(cfg, REMAINING_ON_CHANNEL) ||
++			wl_get_drv_status_all(cfg, FAKE_REMAINING_ON_CHANNEL))
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++		{
++			WL_DBG(("Listen DONE for remain on channel expired\n"));
++			wl_clr_drv_status(cfg, REMAINING_ON_CHANNEL, ndev);
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++			wl_clr_drv_status(cfg, FAKE_REMAINING_ON_CHANNEL, ndev);
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++			if (ndev && (ndev->ieee80211_ptr != NULL)) {
++#if defined(WL_CFG80211_P2P_DEV_IF)
++				if (cfgdev && ((struct wireless_dev *)cfgdev)->wiphy &&
++				    bcmcfg_to_p2p_wdev(cfg)) {
++					/*
++					 * To prevent kernel panic,
++					 * if cfgdev->wiphy may be invalid, adding explicit check
++					 */
++					cfg80211_remain_on_channel_expired(bcmcfg_to_p2p_wdev(cfg),
++						cfg->last_roc_id, &cfg->remain_on_chan, GFP_KERNEL);
++				} else
++					CFGP2P_ERR(("Invalid cfgdev. Dropping the"
++						"remain_on_channel_expired event.\n"));
++#else
++				if (cfgdev && ((struct wireless_dev *)cfgdev)->wiphy)
++					cfg80211_remain_on_channel_expired(cfgdev,
++						cfg->last_roc_id, &cfg->remain_on_chan,
++						cfg->remain_on_chan_type, GFP_KERNEL);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++			}
++		}
++		if (wl_add_remove_eventmsg(bcmcfg_to_prmry_ndev(cfg),
++			WLC_E_P2P_PROBREQ_MSG, false) != BCME_OK) {
++			CFGP2P_ERR((" failed to unset WLC_E_P2P_PROPREQ_MSG\n"));
++		}
++	} else
++		wl_clr_p2p_status(cfg, LISTEN_EXPIRED);
++
++	return ret;
++
++}
++
++/*
++ *  Timer expire callback function for LISTEN
++ *  We can't report cfg80211_remain_on_channel_expired from Timer ISR context,
++ *  so lets do it from thread context.
++ */
++void
++wl_cfgp2p_listen_expired(unsigned long data)
++{
++	wl_event_msg_t msg;
++	struct bcm_cfg80211 *cfg = (struct bcm_cfg80211 *) data;
++	struct net_device *ndev;
++	CFGP2P_DBG((" Enter\n"));
++
++	if (!cfg) {
++		CFGP2P_ERR((" No cfg\n"));
++		return;
++	}
++	bzero(&msg, sizeof(wl_event_msg_t));
++	msg.event_type =  hton32(WLC_E_P2P_DISC_LISTEN_COMPLETE);
++	msg.bsscfgidx  =  wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++#if defined(WL_ENABLE_P2P_IF)
++	ndev = cfg->p2p_net ? cfg->p2p_net :
++		wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_DEVICE);
++#else
++	ndev = wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_DEVICE);
++#endif /* WL_ENABLE_P2P_IF */
++	if (!ndev) {
++		CFGP2P_ERR((" No ndev\n"));
++		return;
++	}
++	wl_cfg80211_event(ndev, &msg, NULL);
++}
++/*
++ *  Routine for cancelling the P2P LISTEN
++ */
++static s32
++wl_cfgp2p_cancel_listen(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++                         struct wireless_dev *wdev, bool notify)
++{
++	WL_DBG(("Enter \n"));
++	/* Irrespective of whether timer is running or not, reset
++	 * the LISTEN state.
++	 */
++	if (timer_pending(&cfg->p2p->listen_timer)) {
++		_del_timer_sync(&cfg->p2p->listen_timer);
++		if (notify) {
++#if defined(WL_CFG80211_P2P_DEV_IF)
++			if (bcmcfg_to_p2p_wdev(cfg))
++				cfg80211_remain_on_channel_expired(wdev, cfg->last_roc_id,
++					&cfg->remain_on_chan, GFP_KERNEL);
++#else
++			if (ndev && ndev->ieee80211_ptr)
++				cfg80211_remain_on_channel_expired(ndev, cfg->last_roc_id,
++					&cfg->remain_on_chan, cfg->remain_on_chan_type, GFP_KERNEL);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++		}
++	}
++	return 0;
++}
++/*
++ * Do a P2P Listen on the given channel for the given duration.
++ * A listen consists of sitting idle and responding to P2P probe requests
++ * with a P2P probe response.
++ *
++ * This fn assumes dongle p2p device discovery is already enabled.
++ * Parameters   :
++ * @cfg          : wl_private data
++ * @channel     : channel to listen
++ * @duration_ms : the time (milli seconds) to wait
++ */
++s32
++wl_cfgp2p_discover_listen(struct bcm_cfg80211 *cfg, s32 channel, u32 duration_ms)
++{
++#define EXTRA_DELAY_TIME	100
++	s32 ret = BCME_OK;
++	timer_list_compat_t *_timer;
++	s32 extra_delay;
++	struct net_device *netdev = bcmcfg_to_prmry_ndev(cfg);
++
++	CFGP2P_DBG((" Enter Listen Channel : %d, Duration : %d\n", channel, duration_ms));
++	if (unlikely(wl_get_p2p_status(cfg, DISCOVERY_ON) == 0)) {
++
++		CFGP2P_ERR((" Discovery is not set, so we have noting to do\n"));
++
++		ret = BCME_NOTREADY;
++		goto exit;
++	}
++	if (timer_pending(&cfg->p2p->listen_timer)) {
++		CFGP2P_DBG(("previous LISTEN is not completed yet\n"));
++		goto exit;
++
++	}
++#ifndef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++	else
++		wl_clr_p2p_status(cfg, LISTEN_EXPIRED);
++#endif /* not WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++	if (wl_add_remove_eventmsg(netdev, WLC_E_P2P_PROBREQ_MSG, true) != BCME_OK) {
++			CFGP2P_ERR((" failed to set WLC_E_P2P_PROPREQ_MSG\n"));
++	}
++
++	ret = wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_LISTEN, channel, (u16) duration_ms,
++	            wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE));
++	_timer = &cfg->p2p->listen_timer;
++
++	/*  We will wait to receive WLC_E_P2P_DISC_LISTEN_COMPLETE from dongle ,
++	 *  otherwise we will wait up to duration_ms + 100ms + duration / 10
++	 */
++	if (ret == BCME_OK) {
++		extra_delay = EXTRA_DELAY_TIME + (duration_ms / 10);
++	} else {
++		/* if failed to set listen, it doesn't need to wait whole duration. */
++		duration_ms = 100 + duration_ms / 20;
++		extra_delay = 0;
++	}
++
++	INIT_TIMER(_timer, wl_cfgp2p_listen_expired, duration_ms, extra_delay);
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++	wl_clr_p2p_status(cfg, LISTEN_EXPIRED);
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++
++#undef EXTRA_DELAY_TIME
++exit:
++	return ret;
++}
++
++
++s32
++wl_cfgp2p_discover_enable_search(struct bcm_cfg80211 *cfg, u8 enable)
++{
++	s32 ret = BCME_OK;
++	CFGP2P_DBG((" Enter\n"));
++	if (!wl_get_p2p_status(cfg, DISCOVERY_ON)) {
++
++		CFGP2P_DBG((" do nothing, discovery is off\n"));
++		return ret;
++	}
++	if (wl_get_p2p_status(cfg, SEARCH_ENABLED) == enable) {
++		CFGP2P_DBG(("already : %d\n", enable));
++		return ret;
++	}
++
++	wl_chg_p2p_status(cfg, SEARCH_ENABLED);
++	/* When disabling Search, reset the WL driver's p2p discovery state to
++	 * WL_P2P_DISC_ST_SCAN.
++	 */
++	if (!enable) {
++		wl_clr_p2p_status(cfg, SCANNING);
++		ret = wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_SCAN, 0, 0,
++		            wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE));
++	}
++
++	return ret;
++}
++
++/*
++ * Callback function for WLC_E_ACTION_FRAME_COMPLETE, WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE
++ */
++s32
++wl_cfgp2p_action_tx_complete(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++            const wl_event_msg_t *e, void *data)
++{
++	s32 ret = BCME_OK;
++	u32 event_type = ntoh32(e->event_type);
++	u32 status = ntoh32(e->status);
++	struct net_device *ndev = NULL;
++	u8 bsscfgidx = e->bsscfgidx;
++
++	CFGP2P_DBG((" Enter\n"));
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	if (wl_get_drv_status_all(cfg, SENDING_ACT_FRM)) {
++		if (event_type == WLC_E_ACTION_FRAME_COMPLETE) {
++
++			CFGP2P_INFO((" WLC_E_ACTION_FRAME_COMPLETE is received : %d\n", status));
++			if (status == WLC_E_STATUS_SUCCESS) {
++				wl_set_p2p_status(cfg, ACTION_TX_COMPLETED);
++				CFGP2P_DBG(("WLC_E_ACTION_FRAME_COMPLETE : ACK\n"));
++				if (!cfg->need_wait_afrx && cfg->af_sent_channel) {
++					CFGP2P_DBG(("no need to wait next AF.\n"));
++					wl_stop_wait_next_action_frame(cfg, ndev, bsscfgidx);
++				}
++			}
++			else if (!wl_get_p2p_status(cfg, ACTION_TX_COMPLETED)) {
++				wl_set_p2p_status(cfg, ACTION_TX_NOACK);
++				CFGP2P_INFO(("WLC_E_ACTION_FRAME_COMPLETE : NO ACK\n"));
++				wl_stop_wait_next_action_frame(cfg, ndev, bsscfgidx);
++			}
++		} else {
++			CFGP2P_INFO((" WLC_E_ACTION_FRAME_OFFCHAN_COMPLETE is received,"
++						"status : %d\n", status));
++
++			if (wl_get_drv_status_all(cfg, SENDING_ACT_FRM))
++				complete(&cfg->send_af_done);
++		}
++	}
++	return ret;
++}
++/* Send an action frame immediately without doing channel synchronization.
++ *
++ * This function does not wait for a completion event before returning.
++ * The WLC_E_ACTION_FRAME_COMPLETE event will be received when the action
++ * frame is transmitted.
++ * The WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE event will be received when an
++ * 802.11 ack has been received for the sent action frame.
++ */
++s32
++wl_cfgp2p_tx_action_frame(struct bcm_cfg80211 *cfg, struct net_device *dev,
++	wl_af_params_t *af_params, s32 bssidx)
++{
++	s32 ret = BCME_OK;
++	s32 evt_ret = BCME_OK;
++	s32 timeout = 0;
++	wl_eventmsg_buf_t buf;
++
++
++	CFGP2P_INFO(("\n"));
++	CFGP2P_INFO(("channel : %u , dwell time : %u\n",
++	    af_params->channel, af_params->dwell_time));
++
++	wl_clr_p2p_status(cfg, ACTION_TX_COMPLETED);
++	wl_clr_p2p_status(cfg, ACTION_TX_NOACK);
++
++	bzero(&buf, sizeof(wl_eventmsg_buf_t));
++	wl_cfg80211_add_to_eventbuffer(&buf, WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE, true);
++	wl_cfg80211_add_to_eventbuffer(&buf, WLC_E_ACTION_FRAME_COMPLETE, true);
++	if ((evt_ret = wl_cfg80211_apply_eventbuffer(bcmcfg_to_prmry_ndev(cfg), cfg, &buf)) < 0)
++		return evt_ret;
++
++	cfg->af_sent_channel  = af_params->channel;
++#ifdef WL_CFG80211_SYNC_GON
++	cfg->af_tx_sent_jiffies = jiffies;
++#endif /* WL_CFG80211_SYNC_GON */
++
++	ret = wldev_iovar_setbuf_bsscfg(dev, "actframe", af_params, sizeof(*af_params),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++
++	if (ret < 0) {
++		CFGP2P_ERR((" sending action frame is failed\n"));
++		goto exit;
++	}
++
++	timeout = wait_for_completion_timeout(&cfg->send_af_done,
++		msecs_to_jiffies(af_params->dwell_time + WL_AF_TX_EXTRA_TIME_MAX));
++
++	if (timeout >= 0 && wl_get_p2p_status(cfg, ACTION_TX_COMPLETED)) {
++		CFGP2P_INFO(("tx action frame operation is completed\n"));
++		ret = BCME_OK;
++	} else if (ETHER_ISBCAST(&cfg->afx_hdl->tx_dst_addr)) {
++		CFGP2P_INFO(("bcast tx action frame operation is completed\n"));
++		ret = BCME_OK;
++	} else {
++		ret = BCME_ERROR;
++		CFGP2P_INFO(("tx action frame operation is failed\n"));
++	}
++	/* clear status bit for action tx */
++	wl_clr_p2p_status(cfg, ACTION_TX_COMPLETED);
++	wl_clr_p2p_status(cfg, ACTION_TX_NOACK);
++
++exit:
++	CFGP2P_INFO((" via act frame iovar : status = %d\n", ret));
++
++	bzero(&buf, sizeof(wl_eventmsg_buf_t));
++	wl_cfg80211_add_to_eventbuffer(&buf, WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE, false);
++	wl_cfg80211_add_to_eventbuffer(&buf, WLC_E_ACTION_FRAME_COMPLETE, false);
++	if ((evt_ret = wl_cfg80211_apply_eventbuffer(bcmcfg_to_prmry_ndev(cfg), cfg, &buf)) < 0) {
++		WL_ERR(("TX frame events revert back failed \n"));
++		return evt_ret;
++	}
++
++	return ret;
++}
++
++/* Generate our P2P Device Address and P2P Interface Address from our primary
++ * MAC address.
++ */
++void
++wl_cfgp2p_generate_bss_mac(struct bcm_cfg80211 *cfg, struct ether_addr *primary_addr)
++{
++	struct ether_addr *mac_addr = wl_to_p2p_bss_macaddr(cfg, P2PAPI_BSSCFG_DEVICE);
++	struct ether_addr *int_addr;
++
++	memcpy(mac_addr, primary_addr, sizeof(struct ether_addr));
++	mac_addr->octet[0] |= 0x02;
++	WL_DBG(("P2P Discovery address:"MACDBG "\n", MAC2STRDBG(mac_addr->octet)));
++
++	int_addr = wl_to_p2p_bss_macaddr(cfg, P2PAPI_BSSCFG_CONNECTION1);
++	memcpy(int_addr, mac_addr, sizeof(struct ether_addr));
++	int_addr->octet[4] ^= 0x80;
++	WL_DBG(("Primary P2P Interface address:"MACDBG "\n", MAC2STRDBG(int_addr->octet)));
++
++	int_addr = wl_to_p2p_bss_macaddr(cfg, P2PAPI_BSSCFG_CONNECTION2);
++	memcpy(int_addr, mac_addr, sizeof(struct ether_addr));
++	int_addr->octet[4] ^= 0x90;
++}
++
++/* P2P IF Address change to Virtual Interface MAC Address */
++void
++wl_cfg80211_change_ifaddr(u8* buf, struct ether_addr *p2p_int_addr, u8 element_id)
++{
++	wifi_p2p_ie_t *ie = (wifi_p2p_ie_t*) buf;
++	u16 len = ie->len;
++	u8 *subel;
++	u8 subelt_id;
++	u16 subelt_len;
++	CFGP2P_DBG((" Enter\n"));
++
++	/* Point subel to the P2P IE's subelt field.
++	 * Subtract the preceding fields (id, len, OUI, oui_type) from the length.
++	 */
++	subel = ie->subelts;
++	len -= 4;	/* exclude OUI + OUI_TYPE */
++
++	while (len >= 3) {
++	/* attribute id */
++		subelt_id = *subel;
++		subel += 1;
++		len -= 1;
++
++		/* 2-byte little endian */
++		subelt_len = *subel++;
++		subelt_len |= *subel++ << 8;
++
++		len -= 2;
++		len -= subelt_len;	/* for the remaining subelt fields */
++
++		if (subelt_id == element_id) {
++			if (subelt_id == P2P_SEID_INTINTADDR) {
++				memcpy(subel, p2p_int_addr->octet, ETHER_ADDR_LEN);
++				CFGP2P_INFO(("Intended P2P Interface Address ATTR FOUND\n"));
++			} else if (subelt_id == P2P_SEID_DEV_ID) {
++				memcpy(subel, p2p_int_addr->octet, ETHER_ADDR_LEN);
++				CFGP2P_INFO(("Device ID ATTR FOUND\n"));
++			} else if (subelt_id == P2P_SEID_DEV_INFO) {
++				memcpy(subel, p2p_int_addr->octet, ETHER_ADDR_LEN);
++				CFGP2P_INFO(("Device INFO ATTR FOUND\n"));
++			} else if (subelt_id == P2P_SEID_GROUP_ID) {
++				memcpy(subel, p2p_int_addr->octet, ETHER_ADDR_LEN);
++				CFGP2P_INFO(("GROUP ID ATTR FOUND\n"));
++			}			return;
++		} else {
++			CFGP2P_DBG(("OTHER id : %d\n", subelt_id));
++		}
++		subel += subelt_len;
++	}
++}
++
++s32
++wl_cfgp2p_supported(struct bcm_cfg80211 *cfg, struct net_device *ndev)
++{
++	s32 ret = BCME_OK;
++	s32 p2p_supported = 0;
++	ret = wldev_iovar_getint(ndev, "p2p",
++	               &p2p_supported);
++	if (ret < 0) {
++		if (ret == BCME_UNSUPPORTED) {
++			CFGP2P_INFO(("p2p is unsupported\n"));
++			return 0;
++		} else {
++			CFGP2P_ERR(("cfg p2p error %d\n", ret));
++			return ret;
++		}
++	}
++	if (cfg->pub->conf->fw_type == FW_TYPE_MESH)
++		p2p_supported = 0;
++	if (p2p_supported == 1) {
++		CFGP2P_INFO(("p2p is supported\n"));
++	} else {
++		CFGP2P_INFO(("p2p is unsupported\n"));
++		p2p_supported = 0;
++	}
++	return p2p_supported;
++}
++
++/* Cleanup P2P resources */
++s32
++wl_cfgp2p_down(struct bcm_cfg80211 *cfg)
++{
++	struct net_device *ndev = NULL;
++	struct wireless_dev *wdev = NULL;
++	s32 i = 0, index = -1;
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	ndev = bcmcfg_to_prmry_ndev(cfg);
++	wdev = bcmcfg_to_p2p_wdev(cfg);
++#elif defined(WL_ENABLE_P2P_IF)
++	ndev = cfg->p2p_net ? cfg->p2p_net : bcmcfg_to_prmry_ndev(cfg);
++	wdev = ndev_to_wdev(ndev);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++	wl_cfgp2p_cancel_listen(cfg, ndev, wdev, TRUE);
++	wl_cfgp2p_disable_discovery(cfg);
++
++#if defined(WL_CFG80211_P2P_DEV_IF) && !defined(KEEP_WIFION_OPTION)
++/*
++ * In CUSTOMER_HW4 implementation "ifconfig wlan0 down" can get
++ * called during phone suspend and customer requires the p2p
++ * discovery interface to be left untouched so that the user
++ * space can resume without any problem.
++ */
++	if (cfg->p2p_wdev) {
++		/* If p2p wdev is left out, clean it up */
++		WL_ERR(("Clean up the p2p discovery IF\n"));
++		wl_cfgp2p_del_p2p_disc_if(cfg->p2p_wdev, cfg);
++	}
++#endif /* WL_CFG80211_P2P_DEV_IF !defined(KEEP_WIFION_OPTION) */
++
++	for (i = 0; i < P2PAPI_BSSCFG_MAX; i++) {
++			index = wl_to_p2p_bss_bssidx(cfg, i);
++			if (index != WL_INVALID)
++				wl_cfg80211_clear_per_bss_ies(cfg, index);
++	}
++	wl_cfgp2p_deinit_priv(cfg);
++	return 0;
++}
++
++int wl_cfgp2p_vif_created(struct bcm_cfg80211 *cfg)
++{
++	if (cfg->p2p && ((wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_CONNECTION1) != -1) ||
++		(wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_CONNECTION2) != -1)))
++		return true;
++	else
++		return false;
++
++}
++
++s32
++wl_cfgp2p_set_p2p_noa(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int len)
++{
++	s32 ret = -1;
++	int count, start, duration;
++	wl_p2p_sched_t dongle_noa;
++	s32 bssidx, type;
++	int iovar_len = sizeof(dongle_noa);
++	CFGP2P_DBG((" Enter\n"));
++
++	memset(&dongle_noa, 0, sizeof(dongle_noa));
++
++	if (wl_cfgp2p_vif_created(cfg)) {
++		cfg->p2p->noa.desc[0].start = 0;
++
++		sscanf(buf, "%10d %10d %10d", &count, &start, &duration);
++		CFGP2P_DBG(("set_p2p_noa count %d start %d duration %d\n",
++			count, start, duration));
++		if (count != -1)
++			cfg->p2p->noa.desc[0].count = count;
++
++		/* supplicant gives interval as start */
++		if (start != -1)
++			cfg->p2p->noa.desc[0].interval = start;
++
++		if (duration != -1)
++			cfg->p2p->noa.desc[0].duration = duration;
++
++		if (cfg->p2p->noa.desc[0].count != 255 && cfg->p2p->noa.desc[0].count != 0) {
++			cfg->p2p->noa.desc[0].start = 200;
++			dongle_noa.type = WL_P2P_SCHED_TYPE_REQ_ABS;
++			dongle_noa.action = WL_P2P_SCHED_ACTION_GOOFF;
++			dongle_noa.option = WL_P2P_SCHED_OPTION_TSFOFS;
++		}
++		else if (cfg->p2p->noa.desc[0].count == 0) {
++			cfg->p2p->noa.desc[0].start = 0;
++			dongle_noa.type = WL_P2P_SCHED_TYPE_ABS;
++			dongle_noa.option = WL_P2P_SCHED_OPTION_NORMAL;
++			dongle_noa.action = WL_P2P_SCHED_ACTION_RESET;
++		}
++		else {
++			/* Continuous NoA interval. */
++			dongle_noa.action = WL_P2P_SCHED_ACTION_DOZE;
++			dongle_noa.type = WL_P2P_SCHED_TYPE_ABS;
++			if ((cfg->p2p->noa.desc[0].interval == 102) ||
++				(cfg->p2p->noa.desc[0].interval == 100)) {
++				cfg->p2p->noa.desc[0].start = 100 -
++					cfg->p2p->noa.desc[0].duration;
++				dongle_noa.option = WL_P2P_SCHED_OPTION_BCNPCT;
++			}
++			else {
++				dongle_noa.option = WL_P2P_SCHED_OPTION_NORMAL;
++			}
++		}
++		/* Put the noa descriptor in dongle format for dongle */
++		dongle_noa.desc[0].count = htod32(cfg->p2p->noa.desc[0].count);
++		if (dongle_noa.option == WL_P2P_SCHED_OPTION_BCNPCT) {
++			dongle_noa.desc[0].start = htod32(cfg->p2p->noa.desc[0].start);
++			dongle_noa.desc[0].duration = htod32(cfg->p2p->noa.desc[0].duration);
++		}
++		else {
++			dongle_noa.desc[0].start = htod32(cfg->p2p->noa.desc[0].start*1000);
++			dongle_noa.desc[0].duration = htod32(cfg->p2p->noa.desc[0].duration*1000);
++		}
++		dongle_noa.desc[0].interval = htod32(cfg->p2p->noa.desc[0].interval*1000);
++		bssidx = wl_get_bssidx_by_wdev(cfg, ndev->ieee80211_ptr);
++		if (wl_cfgp2p_find_type(cfg, bssidx, &type) != BCME_OK)
++			return BCME_ERROR;
++
++		if (dongle_noa.action == WL_P2P_SCHED_ACTION_RESET) {
++			iovar_len -= sizeof(wl_p2p_sched_desc_t);
++		}
++
++		ret = wldev_iovar_setbuf(wl_to_p2p_bss_ndev(cfg, type),
++			"p2p_noa", &dongle_noa, iovar_len, cfg->ioctl_buf,
++			WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++
++		if (ret < 0) {
++			CFGP2P_ERR(("fw set p2p_noa failed %d\n", ret));
++		}
++	}
++	else {
++		CFGP2P_ERR(("ERROR: set_noa in non-p2p mode\n"));
++	}
++	return ret;
++}
++s32
++wl_cfgp2p_get_p2p_noa(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int buf_len)
++{
++
++	wifi_p2p_noa_desc_t *noa_desc;
++	int len = 0, i;
++	char _buf[200];
++
++	CFGP2P_DBG((" Enter\n"));
++	buf[0] = '\0';
++	if (wl_cfgp2p_vif_created(cfg)) {
++		if (cfg->p2p->noa.desc[0].count || cfg->p2p->ops.ops) {
++			_buf[0] = 1; /* noa index */
++			_buf[1] = (cfg->p2p->ops.ops ? 0x80: 0) |
++				(cfg->p2p->ops.ctw & 0x7f); /* ops + ctw */
++			len += 2;
++			if (cfg->p2p->noa.desc[0].count) {
++				noa_desc = (wifi_p2p_noa_desc_t*)&_buf[len];
++				noa_desc->cnt_type = cfg->p2p->noa.desc[0].count;
++				noa_desc->duration = cfg->p2p->noa.desc[0].duration;
++				noa_desc->interval = cfg->p2p->noa.desc[0].interval;
++				noa_desc->start = cfg->p2p->noa.desc[0].start;
++				len += sizeof(wifi_p2p_noa_desc_t);
++			}
++			if (buf_len <= len * 2) {
++				CFGP2P_ERR(("ERROR: buf_len %d in not enough for"
++					"returning noa in string format\n", buf_len));
++				return -1;
++			}
++			/* We have to convert the buffer data into ASCII strings */
++			for (i = 0; i < len; i++) {
++				snprintf(buf, 3, "%02x", _buf[i]);
++				buf += 2;
++			}
++			buf[i*2] = '\0';
++		}
++	}
++	else {
++		CFGP2P_ERR(("ERROR: get_noa in non-p2p mode\n"));
++		return -1;
++	}
++	return len * 2;
++}
++s32
++wl_cfgp2p_set_p2p_ps(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int len)
++{
++	int ps, ctw;
++	int ret = -1;
++	s32 legacy_ps;
++	s32 conn_idx;
++	s32 bssidx;
++	struct net_device *dev;
++
++	CFGP2P_DBG((" Enter\n"));
++	if (wl_cfgp2p_vif_created(cfg)) {
++		sscanf(buf, "%10d %10d %10d", &legacy_ps, &ps, &ctw);
++		CFGP2P_DBG((" Enter legacy_ps %d ps %d ctw %d\n", legacy_ps, ps, ctw));
++
++		bssidx = wl_get_bssidx_by_wdev(cfg, ndev->ieee80211_ptr);
++		if (wl_cfgp2p_find_type(cfg, bssidx, &conn_idx) != BCME_OK)
++			return BCME_ERROR;
++		dev = wl_to_p2p_bss_ndev(cfg, conn_idx);
++		if (ctw != -1) {
++			cfg->p2p->ops.ctw = ctw;
++			ret = 0;
++		}
++		if (ps != -1) {
++			cfg->p2p->ops.ops = ps;
++			ret = wldev_iovar_setbuf(dev,
++				"p2p_ops", &cfg->p2p->ops, sizeof(cfg->p2p->ops),
++				cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++			if (ret < 0) {
++				CFGP2P_ERR(("fw set p2p_ops failed %d\n", ret));
++			}
++		}
++
++		if ((legacy_ps != -1) && ((legacy_ps == PM_MAX) || (legacy_ps == PM_OFF))) {
++			ret = wldev_ioctl_set(dev,
++				WLC_SET_PM, &legacy_ps, sizeof(legacy_ps));
++			if (unlikely(ret))
++				CFGP2P_ERR(("error (%d)\n", ret));
++			wl_cfg80211_update_power_mode(dev);
++		}
++		else
++			CFGP2P_ERR(("ilegal setting\n"));
++	}
++	else {
++		CFGP2P_ERR(("ERROR: set_p2p_ps in non-p2p mode\n"));
++		ret = -1;
++	}
++	return ret;
++}
++
++s32
++wl_cfgp2p_set_p2p_ecsa(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int len)
++{
++	int ch, bw;
++	s32 conn_idx;
++	s32 bssidx;
++	struct net_device *dev;
++	char smbuf[WLC_IOCTL_SMLEN];
++	wl_chan_switch_t csa_arg;
++	u32 chnsp = 0;
++	int err = 0;
++
++	CFGP2P_DBG((" Enter\n"));
++	if (wl_cfgp2p_vif_created(cfg)) {
++		sscanf(buf, "%10d %10d", &ch, &bw);
++		CFGP2P_DBG(("Enter ch %d bw %d\n", ch, bw));
++
++		bssidx = wl_get_bssidx_by_wdev(cfg, ndev->ieee80211_ptr);
++		if (wl_cfgp2p_find_type(cfg, bssidx, &conn_idx) != BCME_OK) {
++			return BCME_ERROR;
++		}
++		dev = wl_to_p2p_bss_ndev(cfg, conn_idx);
++		if (ch <= 0 || bw <= 0) {
++			CFGP2P_ERR(("Negative value not permitted!\n"));
++			return BCME_ERROR;
++		}
++
++		csa_arg.mode = DOT11_CSA_MODE_ADVISORY;
++		csa_arg.count = P2P_ECSA_CNT;
++		csa_arg.reg = 0;
++
++		snprintf(buf, len, "%d/%d", ch, bw);
++		chnsp = wf_chspec_aton(buf);
++		if (chnsp == 0) {
++			CFGP2P_ERR(("%s:chsp is not correct\n", __FUNCTION__));
++			return BCME_ERROR;
++		}
++		chnsp = wl_chspec_host_to_driver(chnsp);
++		csa_arg.chspec = chnsp;
++
++		err = wldev_iovar_setbuf(dev, "csa", &csa_arg, sizeof(csa_arg),
++			smbuf, sizeof(smbuf), NULL);
++		if (err) {
++			CFGP2P_ERR(("%s:set p2p_ecsa failed:%d\n", __FUNCTION__, err));
++			return BCME_ERROR;
++		}
++	} else {
++		CFGP2P_ERR(("ERROR: set_p2p_ecsa in non-p2p mode\n"));
++		return BCME_ERROR;
++	}
++	return BCME_OK;
++}
++
++s32
++wl_cfgp2p_increase_p2p_bw(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int len)
++{
++	int algo;
++	int bw;
++	int ret = BCME_OK;
++
++
++	sscanf(buf, "%3d", &bw);
++	if (bw == 0) {
++		algo = 0;
++		ret = wldev_iovar_setbuf(ndev, "mchan_algo", &algo, sizeof(algo), cfg->ioctl_buf,
++				WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++		if (ret < 0) {
++			CFGP2P_ERR(("fw set mchan_algo failed %d\n", ret));
++			return BCME_ERROR;
++		}
++	} else {
++		algo = 1;
++		ret = wldev_iovar_setbuf(ndev, "mchan_algo", &algo, sizeof(algo), cfg->ioctl_buf,
++				WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++		if (ret < 0) {
++			CFGP2P_ERR(("fw set mchan_algo failed %d\n", ret));
++			return BCME_ERROR;
++		}
++		ret = wldev_iovar_setbuf(ndev, "mchan_bw", &bw, sizeof(algo), cfg->ioctl_buf,
++				WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++		if (ret < 0) {
++			CFGP2P_ERR(("fw set mchan_bw failed %d\n", ret));
++			return BCME_ERROR;
++		}
++	}
++	return BCME_OK;
++}
++
++u8 *
++wl_cfgp2p_retreive_p2pattrib(void *buf, u8 element_id)
++{
++	wifi_p2p_ie_t *ie = NULL;
++	u16 len = 0;
++	u8 *subel;
++	u8 subelt_id;
++	u16 subelt_len;
++
++	if (!buf) {
++		WL_ERR(("P2P IE not present"));
++		return 0;
++	}
++
++	ie = (wifi_p2p_ie_t*) buf;
++	len = ie->len;
++
++	/* Point subel to the P2P IE's subelt field.
++	 * Subtract the preceding fields (id, len, OUI, oui_type) from the length.
++	 */
++	subel = ie->subelts;
++	len -= 4;	/* exclude OUI + OUI_TYPE */
++
++	while (len >= 3) {
++		/* attribute id */
++		subelt_id = *subel;
++		subel += 1;
++		len -= 1;
++
++		/* 2-byte little endian */
++		subelt_len = *subel++;
++		subelt_len |= *subel++ << 8;
++
++		len -= 2;
++		len -= subelt_len;	/* for the remaining subelt fields */
++
++		if (subelt_id == element_id) {
++			/* This will point to start of subelement attrib after
++			 * attribute id & len
++			 */
++			return subel;
++		}
++
++		/* Go to next subelement */
++		subel += subelt_len;
++	}
++
++	/* Not Found */
++	return NULL;
++}
++
++#define P2P_GROUP_CAPAB_GO_BIT	0x01
++
++u8*
++wl_cfgp2p_find_attrib_in_all_p2p_Ies(u8 *parse, u32 len, u32 attrib)
++{
++	bcm_tlv_t *ie;
++	u8* pAttrib;
++
++	CFGP2P_INFO(("Starting parsing parse %p attrib %d remaining len %d ", parse, attrib, len));
++	while ((ie = bcm_parse_tlvs(parse, (int)len, DOT11_MNG_VS_ID))) {
++		if (wl_cfgp2p_is_p2p_ie((uint8*)ie, &parse, &len) == TRUE) {
++			/* Have the P2p ie. Now check for attribute */
++			if ((pAttrib = wl_cfgp2p_retreive_p2pattrib(parse, attrib)) != NULL) {
++				CFGP2P_INFO(("P2P attribute %d was found at parse %p",
++					attrib, parse));
++				return pAttrib;
++			}
++			else {
++				parse += (ie->len + TLV_HDR_LEN);
++				len -= (ie->len + TLV_HDR_LEN);
++				CFGP2P_INFO(("P2P Attribute %d not found Moving parse"
++					" to %p len to %d", attrib, parse, len));
++			}
++		}
++		else {
++			/* It was not p2p IE. parse will get updated automatically to next TLV */
++			CFGP2P_INFO(("IT was NOT P2P IE parse %p len %d", parse, len));
++		}
++	}
++	CFGP2P_ERR(("P2P attribute %d was NOT found", attrib));
++	return NULL;
++}
++
++u8 *
++wl_cfgp2p_retreive_p2p_dev_addr(wl_bss_info_t *bi, u32 bi_length)
++{
++	u8 *capability = NULL;
++	bool p2p_go	= 0;
++	u8 *ptr = NULL;
++
++	if ((capability = wl_cfgp2p_find_attrib_in_all_p2p_Ies(((u8 *) bi) + bi->ie_offset,
++	bi->ie_length, P2P_SEID_P2P_INFO)) == NULL) {
++		WL_ERR(("P2P Capability attribute not found"));
++		return NULL;
++	}
++
++	/* Check Group capability for Group Owner bit */
++	p2p_go = capability[1] & P2P_GROUP_CAPAB_GO_BIT;
++	if (!p2p_go) {
++		return bi->BSSID.octet;
++	}
++
++	/* In probe responses, DEVICE INFO attribute will be present */
++	if (!(ptr = wl_cfgp2p_find_attrib_in_all_p2p_Ies(((u8 *) bi) + bi->ie_offset,
++	bi->ie_length,  P2P_SEID_DEV_INFO))) {
++		/* If DEVICE_INFO is not found, this might be a beacon frame.
++		 * check for DEVICE_ID in the beacon frame.
++		 */
++		ptr = wl_cfgp2p_find_attrib_in_all_p2p_Ies(((u8 *) bi) + bi->ie_offset,
++		bi->ie_length,  P2P_SEID_DEV_ID);
++	}
++
++	if (!ptr)
++		WL_ERR((" Both DEVICE_ID & DEVICE_INFO attribute not present in P2P IE "));
++
++	return ptr;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
++static void
++wl_cfgp2p_ethtool_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *info)
++{
++	snprintf(info->driver, sizeof(info->driver), "p2p");
++	snprintf(info->version, sizeof(info->version), "%lu", (unsigned long)(0));
++}
++
++struct ethtool_ops cfgp2p_ethtool_ops = {
++	.get_drvinfo = wl_cfgp2p_ethtool_get_drvinfo
++};
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24) */
++
++#if defined(WL_ENABLE_P2P_IF)
++s32
++wl_cfgp2p_register_ndev(struct bcm_cfg80211 *cfg)
++{
++	int ret = 0;
++	struct net_device* net = NULL;
++	struct wireless_dev *wdev = NULL;
++	uint8 temp_addr[ETHER_ADDR_LEN] = { 0x00, 0x90, 0x4c, 0x33, 0x22, 0x11 };
++
++	if (cfg->p2p_net) {
++		CFGP2P_ERR(("p2p_net defined already.\n"));
++		return -EINVAL;
++	}
++
++	/* Allocate etherdev, including space for private structure */
++	if (!(net = alloc_etherdev(sizeof(struct bcm_cfg80211 *)))) {
++		CFGP2P_ERR(("%s: OOM - alloc_etherdev\n", __FUNCTION__));
++		return -ENODEV;
++	}
++
++	wdev = kzalloc(sizeof(*wdev), GFP_KERNEL);
++	if (unlikely(!wdev)) {
++		WL_ERR(("Could not allocate wireless device\n"));
++		free_netdev(net);
++		return -ENOMEM;
++	}
++
++	strncpy(net->name, "p2p%d", sizeof(net->name) - 1);
++	net->name[IFNAMSIZ - 1] = '\0';
++
++	/* Copy the reference to bcm_cfg80211 */
++	memcpy((void *)netdev_priv(net), &cfg, sizeof(struct bcm_cfg80211 *));
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31))
++	ASSERT(!net->open);
++	net->do_ioctl = wl_cfgp2p_do_ioctl;
++	net->hard_start_xmit = wl_cfgp2p_start_xmit;
++	net->open = wl_cfgp2p_if_open;
++	net->stop = wl_cfgp2p_if_stop;
++#else
++	ASSERT(!net->netdev_ops);
++	net->netdev_ops = &wl_cfgp2p_if_ops;
++#endif
++
++	/* Register with a dummy MAC addr */
++	memcpy(net->dev_addr, temp_addr, ETHER_ADDR_LEN);
++
++	wdev->wiphy = cfg->wdev->wiphy;
++
++	wdev->iftype = wl_mode_to_nl80211_iftype(WL_MODE_BSS);
++
++	net->ieee80211_ptr = wdev;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
++	net->ethtool_ops = &cfgp2p_ethtool_ops;
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24) */
++
++	SET_NETDEV_DEV(net, wiphy_dev(wdev->wiphy));
++
++	/* Associate p2p0 network interface with new wdev */
++	wdev->netdev = net;
++
++	ret = register_netdev(net);
++	if (ret) {
++		CFGP2P_ERR((" register_netdevice failed (%d)\n", ret));
++		free_netdev(net);
++		kfree(wdev);
++		return -ENODEV;
++	}
++
++	/* store p2p net ptr for further reference. Note that iflist won't have this
++	 * entry as there corresponding firmware interface is a "Hidden" interface.
++	 */
++	cfg->p2p_wdev = wdev;
++	cfg->p2p_net = net;
++
++	printk("%s: P2P Interface Registered\n", net->name);
++
++	return ret;
++}
++
++s32
++wl_cfgp2p_unregister_ndev(struct bcm_cfg80211 *cfg)
++{
++
++	if (!cfg || !cfg->p2p_net) {
++		CFGP2P_ERR(("Invalid Ptr\n"));
++		return -EINVAL;
++	}
++
++	unregister_netdev(cfg->p2p_net);
++	free_netdev(cfg->p2p_net);
++
++	return 0;
++}
++static int wl_cfgp2p_start_xmit(struct sk_buff *skb, struct net_device *ndev)
++{
++
++	if (skb)
++	{
++		CFGP2P_DBG(("(%s) is not used for data operations.Droping the packet.\n",
++			ndev->name));
++		dev_kfree_skb_any(skb);
++	}
++
++	return 0;
++}
++
++static int wl_cfgp2p_do_ioctl(struct net_device *net, struct ifreq *ifr, int cmd)
++{
++	int ret = 0;
++	struct bcm_cfg80211 *cfg = *(struct bcm_cfg80211 **)netdev_priv(net);
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++
++	/* There is no ifidx corresponding to p2p0 in our firmware. So we should
++	 * not Handle any IOCTL cmds on p2p0 other than ANDROID PRIVATE CMDs.
++	 * For Android PRIV CMD handling map it to primary I/F
++	 */
++	if (cmd == SIOCDEVPRIVATE+1) {
++		ret = wl_android_priv_cmd(ndev, ifr, cmd);
++
++	} else {
++		CFGP2P_ERR(("%s: IOCTL req 0x%x on p2p0 I/F. Ignoring. \n",
++		__FUNCTION__, cmd));
++		return -1;
++	}
++
++	return ret;
++}
++#endif 
++
++#if defined(WL_ENABLE_P2P_IF)
++static int wl_cfgp2p_if_open(struct net_device *net)
++{
++	struct wireless_dev *wdev = net->ieee80211_ptr;
++
++	if (!wdev || !wl_cfg80211_is_p2p_active(net))
++		return -EINVAL;
++	WL_TRACE(("Enter\n"));
++#if !defined(WL_IFACE_COMB_NUM_CHANNELS)
++	/* If suppose F/W download (ifconfig wlan0 up) hasn't been done by now,
++	 * do it here. This will make sure that in concurrent mode, supplicant
++	 * is not dependent on a particular order of interface initialization.
++	 * i.e you may give wpa_supp -iwlan0 -N -ip2p0 or wpa_supp -ip2p0 -N
++	 * -iwlan0.
++	 */
++	wdev->wiphy->interface_modes |= (BIT(NL80211_IFTYPE_P2P_CLIENT)
++		| BIT(NL80211_IFTYPE_P2P_GO));
++#endif /* !WL_IFACE_COMB_NUM_CHANNELS */
++	wl_cfg80211_do_driver_init(net);
++
++	return 0;
++}
++
++static int wl_cfgp2p_if_stop(struct net_device *net)
++{
++	struct wireless_dev *wdev = net->ieee80211_ptr;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(net);
++
++	if (!wdev)
++		return -EINVAL;
++
++	wl_cfg80211_scan_stop(cfg, net);
++
++#if !defined(WL_IFACE_COMB_NUM_CHANNELS)
++	wdev->wiphy->interface_modes = (wdev->wiphy->interface_modes)
++					& (~(BIT(NL80211_IFTYPE_P2P_CLIENT)|
++					BIT(NL80211_IFTYPE_P2P_GO)));
++#endif /* !WL_IFACE_COMB_NUM_CHANNELS */
++	return 0;
++}
++
++bool wl_cfgp2p_is_ifops(const struct net_device_ops *if_ops)
++{
++	return (if_ops == &wl_cfgp2p_if_ops);
++}
++#endif /* WL_ENABLE_P2P_IF */
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++struct wireless_dev *
++wl_cfgp2p_add_p2p_disc_if(struct bcm_cfg80211 *cfg)
++{
++	struct wireless_dev *wdev = NULL;
++	struct ether_addr primary_mac;
++
++	if (!cfg || !cfg->p2p_supported)
++		return ERR_PTR(-EINVAL);
++
++	WL_TRACE(("Enter\n"));
++
++	if (cfg->p2p_wdev) {
++#ifndef EXPLICIT_DISCIF_CLEANUP
++		dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++#endif /* EXPLICIT_DISCIF_CLEANUP */
++		/*
++		 * This is not expected. This can happen due to
++		 * supplicant crash/unclean de-initialization which
++		 * didn't free the p2p discovery interface. Indicate
++		 * driver hang to user space so that the framework
++		 * can rei-init the Wi-Fi.
++		 */
++		CFGP2P_ERR(("p2p_wdev defined already.\n"));
++		wl_probe_wdev_all(cfg);
++#ifdef EXPLICIT_DISCIF_CLEANUP
++		/*
++		 * CUSTOMER_HW4 design doesn't delete the p2p discovery
++		 * interface on ifconfig wlan0 down context which comes
++		 * without a preceeding NL80211_CMD_DEL_INTERFACE for p2p
++		 * discovery. But during supplicant crash the DEL_IFACE
++		 * command will not happen and will cause a left over iface
++		 * even after ifconfig wlan0 down. So delete the iface
++		 * first and then indicate the HANG event
++		 */
++		wl_cfgp2p_del_p2p_disc_if(cfg->p2p_wdev, cfg);
++#else
++		dhd->hang_reason = HANG_REASON_IFACE_OP_FAILURE;
++#if defined(BCMPCIE) && defined(DHD_FW_COREDUMP)
++		if (dhd->memdump_enabled) {
++			/* Load the dongle side dump to host
++			 * memory and then BUG_ON()
++			 */
++			dhd->memdump_type = DUMP_TYPE_HANG_ON_IFACE_OP_FAIL;
++			dhd_bus_mem_dump(dhd);
++		}
++#endif /* BCMPCIE && DHD_FW_COREDUMP */
++		net_os_send_hang_message(bcmcfg_to_prmry_ndev(cfg));
++		return ERR_PTR(-ENODEV);
++#endif /* EXPLICIT_DISCIF_CLEANUP */
++	}
++
++	wdev = kzalloc(sizeof(*wdev), GFP_KERNEL);
++	if (unlikely(!wdev)) {
++		WL_ERR(("Could not allocate wireless device\n"));
++		return ERR_PTR(-ENOMEM);
++	}
++
++	memset(&primary_mac, 0, sizeof(primary_mac));
++	get_primary_mac(cfg, &primary_mac);
++	wl_cfgp2p_generate_bss_mac(cfg, &primary_mac);
++
++	wdev->wiphy = cfg->wdev->wiphy;
++	wdev->iftype = NL80211_IFTYPE_P2P_DEVICE;
++	memcpy(wdev->address, wl_to_p2p_bss_macaddr(cfg, P2PAPI_BSSCFG_DEVICE), ETHER_ADDR_LEN);
++
++
++	/* store p2p wdev ptr for further reference. */
++	cfg->p2p_wdev = wdev;
++
++	printf("P2P interface registered\n");
++	printf("%s: wdev: %p, wdev->net: %p\n", __FUNCTION__, wdev, wdev->netdev);
++
++	return wdev;
++}
++
++int
++wl_cfgp2p_start_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev)
++{
++	int ret = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	if (!cfg)
++		return -EINVAL;
++
++	WL_TRACE(("Enter\n"));
++
++	ret = wl_cfgp2p_set_firm_p2p(cfg);
++	if (unlikely(ret < 0)) {
++		CFGP2P_ERR(("Set P2P in firmware failed, ret=%d\n", ret));
++		goto exit;
++	}
++
++	ret = wl_cfgp2p_enable_discovery(cfg, bcmcfg_to_prmry_ndev(cfg), NULL, 0);
++	if (unlikely(ret < 0)) {
++		CFGP2P_ERR(("P2P enable discovery failed, ret=%d\n", ret));
++		goto exit;
++	}
++
++	p2p_on(cfg) = true;
++#if defined(P2P_IE_MISSING_FIX)
++	cfg->p2p_prb_noti = false;
++#endif
++
++	printf("P2P interface started\n");
++
++exit:
++	return ret;
++}
++
++void
++wl_cfgp2p_stop_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev)
++{
++	int ret = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	if (!cfg)
++		return;
++
++	CFGP2P_DBG(("Enter\n"));
++
++	ret = wl_cfg80211_scan_stop(cfg, wdev);
++	if (unlikely(ret < 0)) {
++		CFGP2P_ERR(("P2P scan stop failed, ret=%d\n", ret));
++	}
++
++	if (!cfg->p2p)
++		return;
++
++	/* Cancel any on-going listen */
++	wl_cfgp2p_cancel_listen(cfg, bcmcfg_to_prmry_ndev(cfg), wdev, TRUE);
++
++	ret = wl_cfgp2p_disable_discovery(cfg);
++	if (unlikely(ret < 0)) {
++		CFGP2P_ERR(("P2P disable discovery failed, ret=%d\n", ret));
++	}
++
++	p2p_on(cfg) = false;
++
++	printf("Exit. P2P interface stopped\n");
++
++	return;
++}
++
++int
++wl_cfgp2p_del_p2p_disc_if(struct wireless_dev *wdev, struct bcm_cfg80211 *cfg)
++{
++	bool rollback_lock = false;
++
++	if (!wdev)
++		return -EINVAL;
++
++	WL_TRACE(("Enter\n"));
++	printf("%s: wdev: %p, wdev->net: %p\n", __FUNCTION__, wdev, wdev->netdev);
++
++	if (!rtnl_is_locked()) {
++		rtnl_lock();
++		rollback_lock = true;
++	}
++
++	cfg80211_unregister_wdev(wdev);
++
++	if (rollback_lock)
++		rtnl_unlock();
++
++	synchronize_rcu();
++
++	kfree(wdev);
++
++	if (cfg)
++		cfg->p2p_wdev = NULL;
++
++	printf("P2P interface unregistered\n");
++
++	return 0;
++}
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++void
++wl_cfgp2p_need_wait_actfrmae(struct bcm_cfg80211 *cfg, void *frame, u32 frame_len, bool tx)
++{
++	wifi_p2p_pub_act_frame_t *pact_frm;
++	int status = 0;
++
++	if (!frame || (frame_len < (sizeof(*pact_frm) + WL_P2P_AF_STATUS_OFFSET - 1))) {
++		return;
++	}
++
++	if (wl_cfgp2p_is_pub_action(frame, frame_len)) {
++		pact_frm = (wifi_p2p_pub_act_frame_t *)frame;
++		if (pact_frm->subtype == P2P_PAF_GON_RSP && tx) {
++			CFGP2P_ACTION(("Check TX P2P Group Owner Negotiation Rsp Frame status\n"));
++			status = pact_frm->elts[WL_P2P_AF_STATUS_OFFSET];
++			if (status) {
++				cfg->need_wait_afrx = false;
++				return;
++			}
++		}
++	}
++
++	cfg->need_wait_afrx = true;
++	return;
++}
++
++int
++wl_cfgp2p_is_p2p_specific_scan(struct cfg80211_scan_request *request)
++{
++	if (request && (request->n_ssids == 1) &&
++		(request->n_channels == 1) &&
++		IS_P2P_SSID(request->ssids[0].ssid, WL_P2P_WILDCARD_SSID_LEN) &&
++		(request->ssids[0].ssid_len > WL_P2P_WILDCARD_SSID_LEN)) {
++		return true;
++	}
++	return false;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgp2p.h b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgp2p.h
+new file mode 100644
+index 000000000..a963b9a8d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgp2p.h
+@@ -0,0 +1,451 @@
++/*
++ * Linux cfgp2p driver
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfgp2p.h 676811 2016-12-24 20:48:46Z $
++ */
++#ifndef _wl_cfgp2p_h_
++#define _wl_cfgp2p_h_
++#include <802.11.h>
++#include <p2p.h>
++
++struct bcm_cfg80211;
++extern u32 wl_dbg_level;
++
++typedef struct wifi_p2p_ie wifi_wfd_ie_t;
++/* Enumeration of the usages of the BSSCFGs used by the P2P Library.  Do not
++ * confuse this with a bsscfg index.  This value is an index into the
++ * saved_ie[] array of structures which in turn contains a bsscfg index field.
++ */
++typedef enum {
++	P2PAPI_BSSCFG_PRIMARY, /**< maps to driver's primary bsscfg */
++	P2PAPI_BSSCFG_DEVICE, /**< maps to driver's P2P device discovery bsscfg */
++	P2PAPI_BSSCFG_CONNECTION1, /**< maps to driver's P2P connection bsscfg */
++	P2PAPI_BSSCFG_CONNECTION2,
++	P2PAPI_BSSCFG_MAX
++} p2p_bsscfg_type_t;
++
++typedef enum {
++	P2P_SCAN_PURPOSE_MIN,
++	P2P_SCAN_SOCIAL_CHANNEL, /**< scan for social channel */
++	P2P_SCAN_AFX_PEER_NORMAL, /**< scan for action frame search */
++	P2P_SCAN_AFX_PEER_REDUCED, /**< scan for action frame search with short time */
++	P2P_SCAN_DURING_CONNECTED, /**< scan during connected status */
++	P2P_SCAN_CONNECT_TRY, /**< scan for connecting */
++	P2P_SCAN_NORMAL, /**< scan during not-connected status */
++	P2P_SCAN_PURPOSE_MAX
++} p2p_scan_purpose_t;
++
++/** vendor ies max buffer length for probe response or beacon */
++#define VNDR_IES_MAX_BUF_LEN	1400
++/** normal vendor ies buffer length */
++#define VNDR_IES_BUF_LEN 		512
++
++struct p2p_bss {
++	s32 bssidx;
++	struct net_device *dev;
++	void *private_data;
++	struct ether_addr mac_addr;
++};
++
++struct p2p_info {
++	bool on;    /**< p2p on/off switch */
++	bool scan;
++	int16 search_state;
++	s8 vir_ifname[IFNAMSIZ];
++	unsigned long status;
++	struct p2p_bss bss[P2PAPI_BSSCFG_MAX];
++	timer_list_compat_t listen_timer;
++	wl_p2p_sched_t noa;
++	wl_p2p_ops_t ops;
++	wlc_ssid_t ssid;
++	s8 p2p_go_count;
++};
++
++#define MAX_VNDR_IE_NUMBER	10
++
++struct parsed_vndr_ie_info {
++	char *ie_ptr;
++	u32 ie_len;	/**< total length including id & length field */
++	vndr_ie_t vndrie;
++};
++
++struct parsed_vndr_ies {
++	u32 count;
++	struct parsed_vndr_ie_info ie_info[MAX_VNDR_IE_NUMBER];
++};
++
++/* dongle status */
++enum wl_cfgp2p_status {
++	WLP2P_STATUS_DISCOVERY_ON = 0,
++	WLP2P_STATUS_SEARCH_ENABLED,
++	WLP2P_STATUS_IF_ADDING,
++	WLP2P_STATUS_IF_DELETING,
++	WLP2P_STATUS_IF_CHANGING,
++	WLP2P_STATUS_IF_CHANGED,
++	WLP2P_STATUS_LISTEN_EXPIRED,
++	WLP2P_STATUS_ACTION_TX_COMPLETED,
++	WLP2P_STATUS_ACTION_TX_NOACK,
++	WLP2P_STATUS_SCANNING,
++	WLP2P_STATUS_GO_NEG_PHASE,
++	WLP2P_STATUS_DISC_IN_PROGRESS
++};
++
++
++#define wl_to_p2p_bss_ndev(cfg, type)		((cfg)->p2p->bss[type].dev)
++#define wl_to_p2p_bss_bssidx(cfg, type)		((cfg)->p2p->bss[type].bssidx)
++#define wl_to_p2p_bss_macaddr(cfg, type)     &((cfg)->p2p->bss[type].mac_addr)
++#define wl_to_p2p_bss_saved_ie(cfg, type)	((cfg)->p2p->bss[type].saved_ie)
++#define wl_to_p2p_bss_private(cfg, type)		((cfg)->p2p->bss[type].private_data)
++#define wl_to_p2p_bss(cfg, type)			((cfg)->p2p->bss[type])
++#define wl_get_p2p_status(cfg, stat) ((!(cfg)->p2p_supported) ? 0 : \
++		test_bit(WLP2P_STATUS_ ## stat, &(cfg)->p2p->status))
++#define wl_set_p2p_status(cfg, stat) ((!(cfg)->p2p_supported) ? 0 : \
++		set_bit(WLP2P_STATUS_ ## stat, &(cfg)->p2p->status))
++#define wl_clr_p2p_status(cfg, stat) ((!(cfg)->p2p_supported) ? 0 : \
++		clear_bit(WLP2P_STATUS_ ## stat, &(cfg)->p2p->status))
++#define wl_chg_p2p_status(cfg, stat) ((!(cfg)->p2p_supported) ? 0 : \
++	change_bit(WLP2P_STATUS_ ## stat, &(cfg)->p2p->status))
++#define p2p_on(cfg) ((cfg)->p2p->on)
++#define p2p_scan(cfg) ((cfg)->p2p->scan)
++#define p2p_is_on(cfg) ((cfg)->p2p && (cfg)->p2p->on)
++
++/* dword align allocation */
++#define WLC_IOCTL_MAXLEN 8192
++
++#ifdef CUSTOMER_HW4_DEBUG
++#define CFGP2P_ERROR_TEXT		"[dhd] CFGP2P-INFO2) "
++#else
++#define CFGP2P_ERROR_TEXT		"[dhd] CFGP2P-ERROR) "
++#endif /* CUSTOMER_HW4_DEBUG */
++
++#ifdef DHD_LOG_DUMP
++#define	CFGP2P_ERR_MSG(x, args...)	\
++	do {	\
++		if (wl_dbg_level & WL_DBG_ERR) {	\
++			printk(KERN_INFO CFGP2P_ERROR_TEXT "%s : " x, __func__, ## args);	\
++			DHD_LOG_DUMP_WRITE("[%s] %s: ", dhd_log_dump_get_timestamp(), __func__);	\
++			DHD_LOG_DUMP_WRITE(x, ## args);	\
++		}	\
++	} while (0)
++#define CFGP2P_ERR(x) CFGP2P_ERR_MSG x
++#else
++#define	CFGP2P_ERR_MSG(x, args...)	\
++	do {										\
++		if (wl_dbg_level & WL_DBG_ERR) {				\
++			printk(KERN_INFO CFGP2P_ERROR_TEXT "%s : " x, __func__, ## args);	\
++		}									\
++	} while (0)
++#define CFGP2P_ERR(x) CFGP2P_ERR_MSG x
++#endif /* DHD_LOG_DUMP */
++#define	CFGP2P_INFO_MSG(x, args...)									\
++	do {										\
++		if (wl_dbg_level & WL_DBG_INFO) {				\
++			printk(KERN_INFO "[dhd] CFGP2P-INFO) %s : " x, __func__, ## args);	\
++		}									\
++	} while (0)
++#define CFGP2P_INFO(x) CFGP2P_INFO_MSG x
++#define	CFGP2P_DBG_MSG(x, args...)								\
++	do {									\
++		if (wl_dbg_level & WL_DBG_DBG) {			\
++			printk(KERN_INFO "[dhd] CFGP2P-DEBUG) %s :" x, __func__, ## args);	\
++		}									\
++	} while (0)
++#define CFGP2P_DBG(x) CFGP2P_DBG_MSG x
++
++#define	CFGP2P_ACTION_MSG(x, args...)								\
++	do {									\
++		if (wl_dbg_level & WL_DBG_P2P_ACTION) {			\
++			printk(KERN_INFO "[dhd] CFGP2P-ACTION) %s :" x, __func__, ## args);	\
++		}									\
++	} while (0)
++#define CFGP2P_ACTION(x) CFGP2P_ACTION_MSG x
++
++#define INIT_TIMER(timer, func, duration, extra_delay)	\
++	do {				   \
++		init_timer_compat(timer, func, cfg); \
++		timer_expires(timer) = jiffies + msecs_to_jiffies(duration + extra_delay); \
++		add_timer(timer); \
++	} while (0);
++
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 0, 8))
++#ifdef WL_SUPPORT_BACKPORTED_KPATCHES
++#undef WL_SUPPORT_BACKPORTED_KPATCHES
++#endif
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0))
++#ifdef WL_CFG80211_STA_EVENT
++#undef WL_CFG80211_STA_EVENT
++#endif
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) && !defined(WL_CFG80211_P2P_DEV_IF)
++#define WL_CFG80211_P2P_DEV_IF
++
++#ifdef WL_ENABLE_P2P_IF
++#undef WL_ENABLE_P2P_IF
++#endif
++
++#ifdef WL_SUPPORT_BACKPORTED_KPATCHES
++#undef WL_SUPPORT_BACKPORTED_KPATCHES
++#endif
++#else
++#ifdef WLP2P
++#ifndef WL_ENABLE_P2P_IF
++/* Enable P2P network Interface if P2P support is enabled */
++#define WL_ENABLE_P2P_IF
++#endif /* WL_ENABLE_P2P_IF */
++#endif /* WLP2P */
++#endif /* (LINUX_VERSION >= VERSION(3, 8, 0)) */
++
++#ifndef WL_CFG80211_P2P_DEV_IF
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++#if defined(WL_ENABLE_P2P_IF) && (defined(WL_CFG80211_P2P_DEV_IF) || \
++	(LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)))
++#error Disable 'WL_ENABLE_P2P_IF', if 'WL_CFG80211_P2P_DEV_IF' is enabled \
++	or kernel version is 3.8.0 or above
++#endif /* WL_ENABLE_P2P_IF && (WL_CFG80211_P2P_DEV_IF || (LINUX_VERSION >= VERSION(3, 8, 0))) */
++
++#if !defined(WLP2P) && (defined(WL_ENABLE_P2P_IF) || defined(WL_CFG80211_P2P_DEV_IF))
++#error WLP2P not defined
++#endif /* !WLP2P && (WL_ENABLE_P2P_IF || WL_CFG80211_P2P_DEV_IF) */
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++#define bcm_struct_cfgdev	struct wireless_dev
++#else
++#define bcm_struct_cfgdev	struct net_device
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++#define P2P_ECSA_CNT 50
++
++extern void
++wl_cfgp2p_listen_expired(ulong data);
++extern bool
++wl_cfgp2p_is_pub_action(void *frame, u32 frame_len);
++extern bool
++wl_cfgp2p_is_p2p_action(void *frame, u32 frame_len);
++extern bool
++wl_cfgp2p_is_gas_action(void *frame, u32 frame_len);
++extern bool
++wl_cfgp2p_find_gas_subtype(u8 subtype, u8* data, u32 len);
++extern bool
++wl_cfgp2p_is_p2p_gas_action(void *frame, u32 frame_len);
++extern void
++wl_cfgp2p_print_actframe(bool tx, void *frame, u32 frame_len, u32 channel);
++extern s32
++wl_cfgp2p_init_priv(struct bcm_cfg80211 *cfg);
++extern void
++wl_cfgp2p_deinit_priv(struct bcm_cfg80211 *cfg);
++extern s32
++wl_cfgp2p_set_firm_p2p(struct bcm_cfg80211 *cfg);
++extern s32
++wl_cfgp2p_set_p2p_mode(struct bcm_cfg80211 *cfg, u8 mode,
++            u32 channel, u16 listen_ms, int bssidx);
++extern s32
++wl_cfgp2p_ifadd(struct bcm_cfg80211 *cfg, struct ether_addr *mac, u8 if_type,
++            chanspec_t chspec);
++extern s32
++wl_cfgp2p_ifdisable(struct bcm_cfg80211 *cfg, struct ether_addr *mac);
++extern s32
++wl_cfgp2p_ifdel(struct bcm_cfg80211 *cfg, struct ether_addr *mac);
++extern s32
++wl_cfgp2p_ifchange(struct bcm_cfg80211 *cfg, struct ether_addr *mac, u8 if_type,
++	chanspec_t chspec, s32 conn_idx);
++
++extern s32
++wl_cfgp2p_ifidx(struct bcm_cfg80211 *cfg, struct ether_addr *mac, s32 *index);
++
++extern s32
++wl_cfgp2p_init_discovery(struct bcm_cfg80211 *cfg);
++extern s32
++wl_cfgp2p_enable_discovery(struct bcm_cfg80211 *cfg, struct net_device *dev, const u8 *ie,
++	u32 ie_len);
++extern s32
++wl_cfgp2p_disable_discovery(struct bcm_cfg80211 *cfg);
++extern s32
++wl_cfgp2p_escan(struct bcm_cfg80211 *cfg, struct net_device *dev, u16 active, u32 num_chans,
++	u16 *channels,
++	s32 search_state, u16 action, u32 bssidx, struct ether_addr *tx_dst_addr,
++	p2p_scan_purpose_t p2p_scan_purpose);
++
++extern s32
++wl_cfgp2p_act_frm_search(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	s32 bssidx, s32 channel, struct ether_addr *tx_dst_addr);
++
++extern wpa_ie_fixed_t *
++wl_cfgp2p_find_wpaie(u8 *parse, u32 len);
++
++extern wpa_ie_fixed_t *
++wl_cfgp2p_find_wpsie(u8 *parse, u32 len);
++
++extern wifi_p2p_ie_t *
++wl_cfgp2p_find_p2pie(u8 *parse, u32 len);
++
++extern wifi_wfd_ie_t *
++wl_cfgp2p_find_wfdie(u8 *parse, u32 len);
++extern s32
++wl_cfgp2p_set_management_ie(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 bssidx,
++            s32 pktflag, const u8 *vndr_ie, u32 vndr_ie_len);
++extern s32
++wl_cfgp2p_clear_management_ie(struct bcm_cfg80211 *cfg, s32 bssidx);
++
++extern struct net_device *
++wl_cfgp2p_find_ndev(struct bcm_cfg80211 *cfg, s32 bssidx);
++extern s32
++wl_cfgp2p_find_type(struct bcm_cfg80211 *cfg, s32 bssidx, s32 *type);
++
++
++extern s32
++wl_cfgp2p_listen_complete(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++extern s32
++wl_cfgp2p_discover_listen(struct bcm_cfg80211 *cfg, s32 channel, u32 duration_ms);
++
++extern s32
++wl_cfgp2p_discover_enable_search(struct bcm_cfg80211 *cfg, u8 enable);
++
++extern s32
++wl_cfgp2p_action_tx_complete(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++
++extern s32
++wl_cfgp2p_tx_action_frame(struct bcm_cfg80211 *cfg, struct net_device *dev,
++	wl_af_params_t *af_params, s32 bssidx);
++
++extern void
++wl_cfgp2p_generate_bss_mac(struct bcm_cfg80211 *cfg, struct ether_addr *primary_addr);
++
++extern void
++wl_cfg80211_change_ifaddr(u8* buf, struct ether_addr *p2p_int_addr, u8 element_id);
++
++extern s32
++wl_cfgp2p_supported(struct bcm_cfg80211 *cfg, struct net_device *ndev);
++
++extern s32
++wl_cfgp2p_down(struct bcm_cfg80211 *cfg);
++
++extern s32
++wl_cfgp2p_set_p2p_noa(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int len);
++
++extern s32
++wl_cfgp2p_get_p2p_noa(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int len);
++
++extern s32
++wl_cfgp2p_set_p2p_ps(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int len);
++
++extern s32
++wl_cfgp2p_set_p2p_ecsa(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int len);
++
++extern s32
++wl_cfgp2p_increase_p2p_bw(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int len);
++
++extern u8 *
++wl_cfgp2p_retreive_p2pattrib(void *buf, u8 element_id);
++
++extern u8*
++wl_cfgp2p_find_attrib_in_all_p2p_Ies(u8 *parse, u32 len, u32 attrib);
++
++extern u8 *
++wl_cfgp2p_retreive_p2p_dev_addr(wl_bss_info_t *bi, u32 bi_length);
++
++extern s32
++wl_cfgp2p_register_ndev(struct bcm_cfg80211 *cfg);
++
++extern s32
++wl_cfgp2p_unregister_ndev(struct bcm_cfg80211 *cfg);
++
++extern bool
++wl_cfgp2p_is_ifops(const struct net_device_ops *if_ops);
++
++extern u32
++wl_cfgp2p_vndr_ie(struct bcm_cfg80211 *cfg, u8 *iebuf, s32 pktflag,
++	s8 *oui, s32 ie_id, s8 *data, s32 datalen, const s8* add_del_cmd);
++
++extern int wl_cfgp2p_get_conn_idx(struct bcm_cfg80211 *cfg);
++
++extern
++int wl_cfg_multip2p_operational(struct bcm_cfg80211 *cfg);
++
++extern
++int wl_cfgp2p_vif_created(struct bcm_cfg80211 *cfg);
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++extern struct wireless_dev *
++wl_cfgp2p_add_p2p_disc_if(struct bcm_cfg80211 *cfg);
++
++extern int
++wl_cfgp2p_start_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev);
++
++extern void
++wl_cfgp2p_stop_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev);
++
++extern int
++wl_cfgp2p_del_p2p_disc_if(struct wireless_dev *wdev, struct bcm_cfg80211 *cfg);
++
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++extern void
++wl_cfgp2p_need_wait_actfrmae(struct bcm_cfg80211 *cfg, void *frame, u32 frame_len, bool tx);
++
++extern int
++wl_cfgp2p_is_p2p_specific_scan(struct cfg80211_scan_request *request);
++
++/* WiFi Direct */
++#define SOCIAL_CHAN_1 1
++#define SOCIAL_CHAN_2 6
++#define SOCIAL_CHAN_3 11
++#define IS_P2P_SOCIAL_CHANNEL(channel) ((channel == SOCIAL_CHAN_1) || \
++					(channel == SOCIAL_CHAN_2) || \
++					(channel == SOCIAL_CHAN_3))
++#define SOCIAL_CHAN_CNT 3
++#define AF_PEER_SEARCH_CNT 2
++#define WL_P2P_WILDCARD_SSID "DIRECT-"
++#define WL_P2P_WILDCARD_SSID_LEN 7
++#define WL_P2P_INTERFACE_PREFIX "p2p"
++#define WL_P2P_TEMP_CHAN 11
++#define WL_P2P_TEMP_CHAN_5G 36
++#define WL_P2P_AF_STATUS_OFFSET 9
++
++/* If the provision discovery is for JOIN operations,
++ * or the device discoverablity frame is destined to GO
++ * then we need not do an internal scan to find GO.
++ */
++#define IS_ACTPUB_WITHOUT_GROUP_ID(p2p_ie, len) \
++	(wl_cfgp2p_retreive_p2pattrib(p2p_ie, P2P_SEID_GROUP_ID) == NULL)
++
++#define IS_GAS_REQ(frame, len) (wl_cfgp2p_is_gas_action(frame, len) && \
++					((frame->action == P2PSD_ACTION_ID_GAS_IREQ) || \
++					(frame->action == P2PSD_ACTION_ID_GAS_CREQ)))
++
++#define IS_P2P_PUB_ACT_RSP_SUBTYPE(subtype) ((subtype == P2P_PAF_GON_RSP) || \
++							((subtype == P2P_PAF_GON_CONF) || \
++							(subtype == P2P_PAF_INVITE_RSP) || \
++							(subtype == P2P_PAF_PROVDIS_RSP)))
++#define IS_P2P_SOCIAL(ch) ((ch == SOCIAL_CHAN_1) || (ch == SOCIAL_CHAN_2) || (ch == SOCIAL_CHAN_3))
++#define IS_P2P_SSID(ssid, len) (!memcmp(ssid, WL_P2P_WILDCARD_SSID, WL_P2P_WILDCARD_SSID_LEN) && \
++					(len == WL_P2P_WILDCARD_SSID_LEN))
++#endif				/* _wl_cfgp2p_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgvendor.c b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgvendor.c
+new file mode 100644
+index 000000000..6a332250b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgvendor.c
+@@ -0,0 +1,3746 @@
++/*
++ * Linux cfg80211 Vendor Extension Code
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfgvendor.c 710862 2017-07-14 07:43:59Z $
++ */
++
++/*
++ * New vendor interface additon to nl80211/cfg80211 to allow vendors
++ * to implement proprietary features over the cfg80211 stack.
++*/
++
++#include <typedefs.h>
++#include <linuxver.h>
++#include <osl.h>
++#include <linux/kernel.h>
++#include <linux/vmalloc.h>
++
++#include <bcmutils.h>
++#include <bcmwifi_channels.h>
++#include <bcmendian.h>
++#include <ethernet.h>
++#include <802.11.h>
++#include <linux/if_arp.h>
++#include <asm/uaccess.h>
++
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_debug.h>
++#include <dhdioctl.h>
++#include <wlioctl.h>
++#include <wlioctl_utils.h>
++#include <dhd_cfg80211.h>
++#ifdef PNO_SUPPORT
++#include <dhd_pno.h>
++#endif /* PNO_SUPPORT */
++#ifdef RTT_SUPPORT
++#include <dhd_rtt.h>
++#endif /* RTT_SUPPORT */
++
++#include <ethernet.h>
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/netdevice.h>
++#include <linux/sched.h>
++#include <linux/etherdevice.h>
++#include <linux/wireless.h>
++#include <linux/ieee80211.h>
++#include <linux/wait.h>
++#include <net/cfg80211.h>
++#include <net/rtnetlink.h>
++
++#include <wlioctl.h>
++#include <wldev_common.h>
++#include <wl_cfg80211.h>
++#include <wl_cfgp2p.h>
++#include <wl_android.h>
++#include <wl_cfgvendor.h>
++#ifdef PROP_TXSTATUS
++#include <dhd_wlfc.h>
++#endif
++#include <brcm_nl80211.h>
++
++#ifdef STAT_REPORT
++#include <wl_statreport.h>
++#endif
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 13, 0)) || defined(WL_VENDOR_EXT_SUPPORT)
++
++/*
++ * This API is to be used for asynchronous vendor events. This
++ * shouldn't be used in response to a vendor command from its
++ * do_it handler context (instead wl_cfgvendor_send_cmd_reply should
++ * be used).
++ */
++int wl_cfgvendor_send_async_event(struct wiphy *wiphy,
++	struct net_device *dev, int event_id, const void  *data, int len)
++{
++	u16 kflags;
++	struct sk_buff *skb;
++
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++
++	/* Alloc the SKB for vendor_event */
++#if (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || \
++	LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
++	skb = cfg80211_vendor_event_alloc(wiphy, NULL, len, event_id, kflags);
++#else
++	skb = cfg80211_vendor_event_alloc(wiphy, len, event_id, kflags);
++#endif /* (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || */
++		/* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) */
++	if (!skb) {
++		WL_ERR(("skb alloc failed"));
++		return -ENOMEM;
++	}
++
++	/* Push the data to the skb */
++	nla_put_nohdr(skb, len, data);
++
++	cfg80211_vendor_event(skb, kflags);
++
++	return 0;
++}
++
++static int
++wl_cfgvendor_send_cmd_reply(struct wiphy *wiphy,
++	struct net_device *dev, const void  *data, int len)
++{
++	struct sk_buff *skb;
++
++	/* Alloc the SKB for vendor_event */
++	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len);
++	if (unlikely(!skb)) {
++		WL_ERR(("skb alloc failed"));
++		return -ENOMEM;
++	}
++
++	/* Push the data to the skb */
++	nla_put_nohdr(skb, len, data);
++
++	return cfg80211_vendor_cmd_reply(skb);
++}
++
++static int
++wl_cfgvendor_get_feature_set(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int reply;
++
++	reply = dhd_dev_get_feature_set(bcmcfg_to_prmry_ndev(cfg));
++
++	err =  wl_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++	        &reply, sizeof(int));
++	if (unlikely(err))
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++
++	return err;
++}
++
++static int
++wl_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct sk_buff *skb;
++	int reply;
++	int mem_needed, i;
++
++	mem_needed = VENDOR_REPLY_OVERHEAD +
++		(ATTRIBUTE_U32_LEN * MAX_FEATURE_SET_CONCURRRENT_GROUPS) + ATTRIBUTE_U32_LEN;
++
++	/* Alloc the SKB for vendor_event */
++	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		WL_ERR(("skb alloc failed"));
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET, MAX_FEATURE_SET_CONCURRRENT_GROUPS);
++	for (i = 0; i < MAX_FEATURE_SET_CONCURRRENT_GROUPS; i++) {
++		reply = dhd_dev_get_feature_set_matrix(bcmcfg_to_prmry_ndev(cfg), i);
++		if (reply != WIFI_FEATURE_INVALID) {
++			nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_FEATURE_SET, reply);
++		}
++	}
++
++	err =  cfg80211_vendor_cmd_reply(skb);
++
++	if (unlikely(err)) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++	}
++exit:
++	return err;
++}
++
++static int
++wl_cfgvendor_set_rand_mac_oui(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type;
++	uint8 random_mac_oui[DOT11_OUI_LEN];
++
++	type = nla_type(data);
++
++	if (type == ANDR_WIFI_ATTRIBUTE_RANDOM_MAC_OUI) {
++		memcpy(random_mac_oui, nla_data(data), DOT11_OUI_LEN);
++
++		err = dhd_dev_cfg_rand_mac_oui(bcmcfg_to_prmry_ndev(cfg), random_mac_oui);
++
++		if (unlikely(err))
++			WL_ERR(("Bad OUI, could not set:%d \n", err));
++
++	} else {
++		err = -1;
++	}
++
++	return err;
++}
++#ifdef CUSTOM_FORCE_NODFS_FLAG
++static int
++wl_cfgvendor_set_nodfs_flag(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type;
++	u32 nodfs;
++
++	type = nla_type(data);
++	if (type == ANDR_WIFI_ATTRIBUTE_NODFS_SET) {
++		nodfs = nla_get_u32(data);
++		err = dhd_dev_set_nodfs(bcmcfg_to_prmry_ndev(cfg), nodfs);
++	} else {
++		err = -1;
++	}
++	return err;
++}
++#endif /* CUSTOM_FORCE_NODFS_FLAG */
++
++static int
++wl_cfgvendor_set_country(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void *data, int len)
++{
++	int err = BCME_ERROR, rem, type;
++	char country_code[WLC_CNTRY_BUF_SZ] = {0};
++	const struct nlattr *iter;
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case ANDR_WIFI_ATTRIBUTE_COUNTRY:
++				memcpy(country_code, nla_data(iter),
++					MIN(nla_len(iter), WLC_CNTRY_BUF_SZ));
++				break;
++			default:
++				WL_ERR(("Unknown type: %d\n", type));
++				return err;
++		}
++	}
++
++	err = wldev_set_country(wdev->netdev, country_code, true, true, -1);
++	if (err < 0) {
++		WL_ERR(("Set country failed ret:%d\n", err));
++	}
++
++	return err;
++}
++
++#ifdef GSCAN_SUPPORT
++int
++wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
++	struct net_device *dev, void  *data, int len, wl_vendor_event_t event)
++{
++	u16 kflags;
++	const void *ptr;
++	struct sk_buff *skb;
++	int malloc_len, total, iter_cnt_to_send, cnt;
++	gscan_results_cache_t *cache = (gscan_results_cache_t *)data;
++
++	total = len/sizeof(wifi_gscan_result_t);
++	while (total > 0) {
++		malloc_len = (total * sizeof(wifi_gscan_result_t)) + VENDOR_DATA_OVERHEAD;
++		if (malloc_len > NLMSG_DEFAULT_SIZE) {
++			malloc_len = NLMSG_DEFAULT_SIZE;
++		}
++		iter_cnt_to_send =
++		   (malloc_len - VENDOR_DATA_OVERHEAD)/sizeof(wifi_gscan_result_t);
++		total = total - iter_cnt_to_send;
++
++		kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++
++		/* Alloc the SKB for vendor_event */
++#if (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || \
++	LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
++		skb = cfg80211_vendor_event_alloc(wiphy, NULL, malloc_len, event, kflags);
++#else
++		skb = cfg80211_vendor_event_alloc(wiphy, malloc_len, event, kflags);
++#endif /* (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || */
++		/* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) */
++		if (!skb) {
++			WL_ERR(("skb alloc failed"));
++			return -ENOMEM;
++		}
++
++		while (cache && iter_cnt_to_send) {
++			ptr = (const void *) &cache->results[cache->tot_consumed];
++
++			if (iter_cnt_to_send < (cache->tot_count - cache->tot_consumed)) {
++				cnt = iter_cnt_to_send;
++			} else {
++				cnt = (cache->tot_count - cache->tot_consumed);
++			}
++
++			iter_cnt_to_send -= cnt;
++			cache->tot_consumed += cnt;
++			/* Push the data to the skb */
++			nla_append(skb, cnt * sizeof(wifi_gscan_result_t), ptr);
++			if (cache->tot_consumed == cache->tot_count) {
++				cache = cache->next;
++			}
++
++		}
++
++		cfg80211_vendor_event(skb, kflags);
++	}
++
++	return 0;
++}
++
++
++static int
++wl_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pno_gscan_capabilities_t *reply = NULL;
++	uint32 reply_len = 0;
++
++
++	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++	   DHD_PNO_GET_CAPABILITIES, NULL, &reply_len);
++	if (!reply) {
++		WL_ERR(("Could not get capabilities\n"));
++		err = -EINVAL;
++		return err;
++	}
++
++	err =  wl_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++	        reply, reply_len);
++
++	if (unlikely(err)) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++	}
++
++	kfree(reply);
++	return err;
++}
++
++static int
++wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_results_cache_t *results, *iter;
++	uint32 reply_len, is_done = 1;
++	int32 mem_needed, num_results_iter;
++	wifi_gscan_result_t *ptr;
++	uint16 num_scan_ids, num_results;
++	struct sk_buff *skb;
++	struct nlattr *scan_hdr, *complete_flag;
++
++	err = dhd_dev_wait_batch_results_complete(bcmcfg_to_prmry_ndev(cfg));
++	if (err != BCME_OK)
++		return -EBUSY;
++
++	err = dhd_dev_pno_lock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++	if (err != BCME_OK) {
++		WL_ERR(("Can't obtain lock to access batch results %d\n", err));
++		return -EBUSY;
++	}
++	results = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++	             DHD_PNO_GET_BATCH_RESULTS, NULL, &reply_len);
++
++	if (!results) {
++		WL_ERR(("No results to send %d\n", err));
++		err =  wl_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++		        results, 0);
++
++		if (unlikely(err))
++			WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++		return err;
++	}
++	num_scan_ids = reply_len & 0xFFFF;
++	num_results = (reply_len & 0xFFFF0000) >> 16;
++	mem_needed = (num_results * sizeof(wifi_gscan_result_t)) +
++	             (num_scan_ids * GSCAN_BATCH_RESULT_HDR_LEN) +
++	             VENDOR_REPLY_OVERHEAD + SCAN_RESULTS_COMPLETE_FLAG_LEN;
++
++	if (mem_needed > (int32)NLMSG_DEFAULT_SIZE) {
++		mem_needed = (int32)NLMSG_DEFAULT_SIZE;
++	}
++
++	WL_TRACE(("is_done %d mem_needed %d max_mem %d\n", is_done, mem_needed,
++		(int)NLMSG_DEFAULT_SIZE));
++	/* Alloc the SKB for vendor_event */
++	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		WL_ERR(("skb alloc failed"));
++		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++		return -ENOMEM;
++	}
++	iter = results;
++	complete_flag = nla_reserve(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE,
++	                    sizeof(is_done));
++	mem_needed = mem_needed - (SCAN_RESULTS_COMPLETE_FLAG_LEN + VENDOR_REPLY_OVERHEAD);
++
++	while (iter) {
++		num_results_iter = (mem_needed - (int32)GSCAN_BATCH_RESULT_HDR_LEN);
++		num_results_iter /= (int32)sizeof(wifi_gscan_result_t);
++		if (num_results_iter <= 0 ||
++		    ((iter->tot_count - iter->tot_consumed) > num_results_iter)) {
++			break;
++		}
++		scan_hdr = nla_nest_start(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS);
++		/* no more room? we are done then (for now) */
++		if (scan_hdr == NULL) {
++			is_done = 0;
++			break;
++		}
++		nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_ID, iter->scan_id);
++		nla_put_u8(skb, GSCAN_ATTRIBUTE_SCAN_FLAGS, iter->flag);
++		nla_put_u32(skb, GSCAN_ATTRIBUTE_CH_BUCKET_BITMASK, iter->scan_ch_bucket);
++
++		num_results_iter = iter->tot_count - iter->tot_consumed;
++
++		nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_OF_RESULTS, num_results_iter);
++		if (num_results_iter) {
++			ptr = &iter->results[iter->tot_consumed];
++			iter->tot_consumed += num_results_iter;
++			nla_put(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS,
++			 num_results_iter * sizeof(wifi_gscan_result_t), ptr);
++		}
++		nla_nest_end(skb, scan_hdr);
++		mem_needed -= GSCAN_BATCH_RESULT_HDR_LEN +
++		    (num_results_iter * sizeof(wifi_gscan_result_t));
++		iter = iter->next;
++	}
++	/* Returns TRUE if all result consumed */
++	is_done = dhd_dev_gscan_batch_cache_cleanup(bcmcfg_to_prmry_ndev(cfg));
++	memcpy(nla_data(complete_flag), &is_done, sizeof(is_done));
++	dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++	return cfg80211_vendor_cmd_reply(skb);
++}
++
++static int
++wl_cfgvendor_initiate_gscan(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type, tmp = len;
++	int run = 0xFF;
++	int flush = 0;
++	const struct nlattr *iter;
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++		if (type == GSCAN_ATTRIBUTE_ENABLE_FEATURE)
++			run = nla_get_u32(iter);
++		else if (type == GSCAN_ATTRIBUTE_FLUSH_FEATURE)
++			flush = nla_get_u32(iter);
++	}
++
++	if (run != 0xFF) {
++		err = dhd_dev_pno_run_gscan(bcmcfg_to_prmry_ndev(cfg), run, flush);
++
++		if (unlikely(err)) {
++			WL_ERR(("Could not run gscan:%d \n", err));
++		}
++		return err;
++	} else {
++		return -EINVAL;
++	}
++
++
++}
++
++static int
++wl_cfgvendor_enable_full_scan_result(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type;
++	bool real_time = FALSE;
++
++	type = nla_type(data);
++
++	if (type == GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS) {
++		real_time = nla_get_u32(data);
++
++		err = dhd_dev_pno_enable_full_scan_result(bcmcfg_to_prmry_ndev(cfg), real_time);
++
++		if (unlikely(err)) {
++			WL_ERR(("Could not run gscan:%d \n", err));
++		}
++
++	} else {
++		err = -EINVAL;
++	}
++
++	return err;
++}
++
++static int
++wl_cfgvendor_set_scan_cfg_bucket(const struct nlattr *prev,
++	gscan_scan_params_t *scan_param, int num)
++{
++	struct dhd_pno_gscan_channel_bucket  *ch_bucket;
++	int k = 0;
++	int type, err = 0, rem;
++	const struct nlattr *cur, *next;
++
++	nla_for_each_nested(cur, prev, rem) {
++		type = nla_type(cur);
++		ch_bucket = scan_param->channel_bucket;
++		switch (type) {
++		case GSCAN_ATTRIBUTE_BUCKET_ID:
++			break;
++		case GSCAN_ATTRIBUTE_BUCKET_PERIOD:
++			if (nla_len(cur) != sizeof(uint32)) {
++				err = -EINVAL;
++				goto exit;
++			}
++
++			ch_bucket[num].bucket_freq_multiple =
++				nla_get_u32(cur) / MSEC_PER_SEC;
++			break;
++		case GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS:
++			if (nla_len(cur) != sizeof(uint32)) {
++				err = -EINVAL;
++				goto exit;
++			}
++			ch_bucket[num].num_channels = nla_get_u32(cur);
++			if (ch_bucket[num].num_channels >
++				GSCAN_MAX_CHANNELS_IN_BUCKET) {
++				WL_ERR(("channel range:%d,bucket:%d\n",
++					ch_bucket[num].num_channels,
++					num));
++				err = -EINVAL;
++				goto exit;
++			}
++			break;
++		case GSCAN_ATTRIBUTE_BUCKET_CHANNELS:
++			nla_for_each_nested(next, cur, rem) {
++				if (k >= GSCAN_MAX_CHANNELS_IN_BUCKET)
++					break;
++				if (nla_len(next) != sizeof(uint32)) {
++					err = -EINVAL;
++					goto exit;
++				}
++				ch_bucket[num].chan_list[k] = nla_get_u32(next);
++				k++;
++			}
++			break;
++		case GSCAN_ATTRIBUTE_BUCKETS_BAND:
++			if (nla_len(cur) != sizeof(uint32)) {
++				err = -EINVAL;
++				goto exit;
++			}
++			ch_bucket[num].band = (uint16)nla_get_u32(cur);
++			break;
++		case GSCAN_ATTRIBUTE_REPORT_EVENTS:
++			if (nla_len(cur) != sizeof(uint32)) {
++				err = -EINVAL;
++				goto exit;
++			}
++			ch_bucket[num].report_flag = (uint8)nla_get_u32(cur);
++			break;
++		case GSCAN_ATTRIBUTE_BUCKET_STEP_COUNT:
++			if (nla_len(cur) != sizeof(uint32)) {
++				err = -EINVAL;
++				goto exit;
++			}
++			ch_bucket[num].repeat = (uint16)nla_get_u32(cur);
++			break;
++		case GSCAN_ATTRIBUTE_BUCKET_MAX_PERIOD:
++			if (nla_len(cur) != sizeof(uint32)) {
++				err = -EINVAL;
++				goto exit;
++			}
++			ch_bucket[num].bucket_max_multiple =
++				nla_get_u32(cur) / MSEC_PER_SEC;
++			break;
++		default:
++			WL_ERR(("unknown attr type:%d\n", type));
++			err = -EINVAL;
++			goto exit;
++		}
++	}
++
++exit:
++	return err;
++}
++
++static int
++wl_cfgvendor_set_scan_cfg(struct wiphy *wiphy, struct wireless_dev *wdev,
++	const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_scan_params_t *scan_param;
++	int j = 0;
++	int type, tmp;
++	const struct nlattr *iter;
++
++	scan_param = kzalloc(sizeof(gscan_scan_params_t), GFP_KERNEL);
++	if (!scan_param) {
++		WL_ERR(("Could not set GSCAN scan cfg, mem alloc failure\n"));
++		err = -EINVAL;
++		return err;
++
++	}
++
++	scan_param->scan_fr = PNO_SCAN_MIN_FW_SEC;
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++
++		if (j >= GSCAN_MAX_CH_BUCKETS) {
++			break;
++		}
++
++		switch (type) {
++			case GSCAN_ATTRIBUTE_BASE_PERIOD:
++				if (nla_len(iter) != sizeof(uint32)) {
++					err = -EINVAL;
++					goto exit;
++				}
++				scan_param->scan_fr = nla_get_u32(iter) / MSEC_PER_SEC;
++				break;
++			case GSCAN_ATTRIBUTE_NUM_BUCKETS:
++				if (nla_len(iter) != sizeof(uint32)) {
++					err = -EINVAL;
++					goto exit;
++				}
++				scan_param->nchannel_buckets = nla_get_u32(iter);
++				if (scan_param->nchannel_buckets >=
++				    GSCAN_MAX_CH_BUCKETS) {
++					WL_ERR(("ncha_buck out of range %d\n",
++					scan_param->nchannel_buckets));
++					err = -EINVAL;
++					goto exit;
++				}
++				break;
++			case GSCAN_ATTRIBUTE_CH_BUCKET_1:
++			case GSCAN_ATTRIBUTE_CH_BUCKET_2:
++			case GSCAN_ATTRIBUTE_CH_BUCKET_3:
++			case GSCAN_ATTRIBUTE_CH_BUCKET_4:
++			case GSCAN_ATTRIBUTE_CH_BUCKET_5:
++			case GSCAN_ATTRIBUTE_CH_BUCKET_6:
++			case GSCAN_ATTRIBUTE_CH_BUCKET_7:
++				err = wl_cfgvendor_set_scan_cfg_bucket(iter, scan_param, j);
++				if (err < 0) {
++					WL_ERR(("set_scan_cfg_buck error:%d\n", err));
++					goto exit;
++				}
++				j++;
++				break;
++			default:
++				WL_ERR(("Unknown type %d\n", type));
++				err = -EINVAL;
++				goto exit;
++		}
++	}
++
++	err = dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++	     DHD_PNO_SCAN_CFG_ID, scan_param, FALSE);
++
++	if (err < 0) {
++		WL_ERR(("Could not set GSCAN scan cfg\n"));
++		err = -EINVAL;
++	}
++
++exit:
++	kfree(scan_param);
++	return err;
++
++}
++
++static int
++wl_cfgvendor_hotlist_cfg(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_hotlist_scan_params_t *hotlist_params;
++	int tmp, tmp1, tmp2, type, j = 0, dummy;
++	const struct nlattr *outer, *inner = NULL, *iter;
++	bool flush = FALSE;
++	struct bssid_t *pbssid;
++
++	BCM_REFERENCE(dummy);
++
++	if (len < sizeof(*hotlist_params) || len >= WLC_IOCTL_MAXLEN) {
++		WL_ERR(("buffer length :%d wrong - bail out.\n", len));
++		return -EINVAL;
++	}
++
++	hotlist_params = kzalloc(sizeof(*hotlist_params)
++		+ (sizeof(struct bssid_t) * (PFN_SWC_MAX_NUM_APS - 1)),
++		GFP_KERNEL);
++
++	if (!hotlist_params) {
++		WL_ERR(("Cannot Malloc memory.\n"));
++		return -ENOMEM;
++	}
++
++	hotlist_params->lost_ap_window = GSCAN_LOST_AP_WINDOW_DEFAULT;
++
++	nla_for_each_attr(iter, data, len, tmp2) {
++		type = nla_type(iter);
++		switch (type) {
++		case GSCAN_ATTRIBUTE_HOTLIST_BSSIDS:
++			pbssid = hotlist_params->bssid;
++			nla_for_each_nested(outer, iter, tmp) {
++				nla_for_each_nested(inner, outer, tmp1) {
++					type = nla_type(inner);
++
++					switch (type) {
++					case GSCAN_ATTRIBUTE_BSSID:
++						if (nla_len(inner) != sizeof(pbssid[j].macaddr)) {
++							WL_ERR(("type:%d length:%d not matching.\n",
++								type, nla_len(inner)));
++							err = -EINVAL;
++							goto exit;
++						}
++						memcpy(
++							&(pbssid[j].macaddr),
++							nla_data(inner),
++							sizeof(pbssid[j].macaddr));
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_LOW:
++						if (nla_len(inner) != sizeof(uint8)) {
++							WL_ERR(("type:%d length:%d not matching.\n",
++								type, nla_len(inner)));
++							err = -EINVAL;
++							goto exit;
++						}
++						pbssid[j].rssi_reporting_threshold =
++							(int8)nla_get_u8(inner);
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_HIGH:
++						if (nla_len(inner) != sizeof(uint8)) {
++							WL_ERR(("type:%d length:%d not matching.\n",
++								type, nla_len(inner)));
++							err = -EINVAL;
++							goto exit;
++						}
++						dummy = (int8)nla_get_u8(inner);
++						break;
++					default:
++						WL_ERR(("ATTR unknown %d\n", type));
++						err = -EINVAL;
++						goto exit;
++					}
++				}
++				if (++j >= PFN_SWC_MAX_NUM_APS) {
++					WL_ERR(("cap hotlist max:%d\n", j));
++					break;
++				}
++			}
++			hotlist_params->nbssid = j;
++			break;
++		case GSCAN_ATTRIBUTE_HOTLIST_FLUSH:
++			if (nla_len(iter) != sizeof(uint8)) {
++				WL_ERR(("type:%d length:%d not matching.\n",
++					type, nla_len(inner)));
++				err = -EINVAL;
++				goto exit;
++			}
++			flush = nla_get_u8(iter);
++			break;
++		case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
++			if (nla_len(iter) != sizeof(uint32)) {
++				WL_ERR(("type:%d length:%d not matching.\n",
++					type, nla_len(inner)));
++				err = -EINVAL;
++				goto exit;
++			}
++			hotlist_params->lost_ap_window = (uint16)nla_get_u32(iter);
++			break;
++		default:
++			WL_ERR(("Unknown type %d\n", type));
++			err = -EINVAL;
++			goto exit;
++		}
++
++	}
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++	      DHD_PNO_GEOFENCE_SCAN_CFG_ID, hotlist_params, flush) < 0) {
++		WL_ERR(("Could not set GSCAN HOTLIST cfg error: %d\n", err));
++		err = -EINVAL;
++		goto exit;
++	}
++exit:
++	kfree(hotlist_params);
++	return err;
++}
++
++static int wl_cfgvendor_epno_cfg(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pno_ssid_t *ssid_elem;
++	int tmp, tmp1, tmp2, type = 0, num = 0;
++	const struct nlattr *outer, *inner, *iter;
++	uint8 flush = FALSE, i = 0;
++	wl_pfn_ssid_params_t params;
++
++	nla_for_each_attr(iter, data, len, tmp2) {
++		type = nla_type(iter);
++		switch (type) {
++			case GSCAN_ATTRIBUTE_EPNO_SSID_LIST:
++				nla_for_each_nested(outer, iter, tmp) {
++					ssid_elem = (dhd_pno_ssid_t *)
++						dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++						DHD_PNO_GET_NEW_EPNO_SSID_ELEM,
++						NULL, &num);
++					if (!ssid_elem) {
++						WL_ERR(("Failed to get SSID LIST buffer\n"));
++						err = -ENOMEM;
++						goto exit;
++					}
++					i++;
++					nla_for_each_nested(inner, outer, tmp1) {
++						type = nla_type(inner);
++
++						switch (type) {
++							case GSCAN_ATTRIBUTE_EPNO_SSID:
++								memcpy(ssid_elem->SSID,
++								  nla_data(inner),
++								  DOT11_MAX_SSID_LEN);
++								break;
++							case GSCAN_ATTRIBUTE_EPNO_SSID_LEN:
++								ssid_elem->SSID_len =
++									nla_get_u32(inner);
++								if (ssid_elem->SSID_len >
++									DOT11_MAX_SSID_LEN) {
++									WL_ERR(("SSID too"
++									"long %d\n",
++									ssid_elem->SSID_len));
++									err = -EINVAL;
++									goto exit;
++								}
++								break;
++							case GSCAN_ATTRIBUTE_EPNO_FLAGS:
++								ssid_elem->flags =
++									nla_get_u32(inner);
++								ssid_elem->hidden =
++									((ssid_elem->flags &
++									DHD_EPNO_HIDDEN_SSID) != 0);
++								break;
++							case GSCAN_ATTRIBUTE_EPNO_AUTH:
++								ssid_elem->wpa_auth =
++								        nla_get_u32(inner);
++								break;
++						}
++					}
++					if (!ssid_elem->SSID_len) {
++						WL_ERR(("Broadcast SSID is illegal for ePNO\n"));
++						err = -EINVAL;
++						goto exit;
++					}
++					dhd_pno_translate_epno_fw_flags(&ssid_elem->flags);
++					dhd_pno_set_epno_auth_flag(&ssid_elem->wpa_auth);
++				}
++				break;
++			case GSCAN_ATTRIBUTE_EPNO_SSID_NUM:
++				num = nla_get_u8(iter);
++				break;
++			case GSCAN_ATTRIBUTE_EPNO_FLUSH:
++				flush = (bool)nla_get_u32(iter);
++				/* Flush attribute is expected before any ssid attribute */
++				if (i && flush) {
++					WL_ERR(("Bad attributes\n"));
++					err = -EINVAL;
++					goto exit;
++				}
++				/* Need to flush driver and FW cfg */
++				dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++				DHD_PNO_EPNO_CFG_ID, NULL, flush);
++				dhd_dev_flush_fw_epno(bcmcfg_to_prmry_ndev(cfg));
++				break;
++			case GSCAN_ATTRIBUTE_EPNO_5G_RSSI_THR:
++				params.min5G_rssi = nla_get_s8(iter);
++				break;
++			case GSCAN_ATTRIBUTE_EPNO_2G_RSSI_THR:
++				params.min2G_rssi = nla_get_s8(iter);
++				break;
++			case GSCAN_ATTRIBUTE_EPNO_INIT_SCORE_MAX:
++				params.init_score_max = nla_get_s16(iter);
++				break;
++			case GSCAN_ATTRIBUTE_EPNO_CUR_CONN_BONUS:
++				params.cur_bssid_bonus = nla_get_s16(iter);
++				break;
++			case GSCAN_ATTRIBUTE_EPNO_SAME_NETWORK_BONUS:
++				params.same_ssid_bonus = nla_get_s16(iter);
++				break;
++			case GSCAN_ATTRIBUTE_EPNO_SECURE_BONUS:
++				params.secure_bonus = nla_get_s16(iter);
++				break;
++			case GSCAN_ATTRIBUTE_EPNO_5G_BONUS:
++				params.band_5g_bonus = nla_get_s16(iter);
++				break;
++			default:
++				WL_ERR(("%s: No such attribute %d\n", __FUNCTION__, type));
++				err = -EINVAL;
++				goto exit;
++			}
++	}
++	if (i != num) {
++		WL_ERR(("%s: num_ssid %d does not match ssids sent %d\n", __FUNCTION__,
++		     num, i));
++		err = -EINVAL;
++	}
++exit:
++	/* Flush all configs if error condition */
++	if (err < 0) {
++		dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++		   DHD_PNO_EPNO_CFG_ID, NULL, TRUE);
++		dhd_dev_flush_fw_epno(bcmcfg_to_prmry_ndev(cfg));
++	} else if (type != GSCAN_ATTRIBUTE_EPNO_FLUSH) {
++		/* If the last attribute was FLUSH, nothing else to do */
++		dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++		DHD_PNO_EPNO_PARAMS_ID, &params, FALSE);
++		err = dhd_dev_set_epno(bcmcfg_to_prmry_ndev(cfg));
++	}
++	return err;
++}
++
++static int
++wl_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0, tmp, type;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_batch_params_t batch_param;
++	const struct nlattr *iter;
++
++	batch_param.mscan = batch_param.bestn = 0;
++	batch_param.buffer_threshold = GSCAN_BATCH_NO_THR_SET;
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++
++		switch (type) {
++			case GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN:
++				batch_param.bestn = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE:
++				batch_param.mscan = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_REPORT_THRESHOLD:
++				batch_param.buffer_threshold = nla_get_u32(iter);
++				break;
++			default:
++				WL_ERR(("Unknown type %d\n", type));
++				break;
++		}
++	}
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++	       DHD_PNO_BATCH_SCAN_CFG_ID, &batch_param, FALSE) < 0) {
++		WL_ERR(("Could not set batch cfg\n"));
++		err = -EINVAL;
++		return err;
++	}
++
++	return err;
++}
++
++#endif /* GSCAN_SUPPORT */
++#if defined(GSCAN_SUPPORT) || defined(DHD_GET_VALID_CHANNELS)
++static int
++wl_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0, type, band;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	uint16 *reply = NULL;
++	uint32 reply_len = 0, num_channels, mem_needed;
++	struct sk_buff *skb;
++
++	type = nla_type(data);
++
++	if (type == GSCAN_ATTRIBUTE_BAND) {
++		band = nla_get_u32(data);
++	} else {
++		return -EINVAL;
++	}
++
++	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++	   DHD_PNO_GET_CHANNEL_LIST, &band, &reply_len);
++
++	if (!reply) {
++		WL_ERR(("Could not get channel list\n"));
++		err = -EINVAL;
++		return err;
++	}
++	num_channels =  reply_len/ sizeof(uint32);
++	mem_needed = reply_len + VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * 2);
++
++	/* Alloc the SKB for vendor_event */
++	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		WL_ERR(("skb alloc failed"));
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_CHANNELS, num_channels);
++	nla_put(skb, GSCAN_ATTRIBUTE_CHANNEL_LIST, reply_len, reply);
++
++	err =  cfg80211_vendor_cmd_reply(skb);
++
++	if (unlikely(err)) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++	}
++exit:
++	kfree(reply);
++	return err;
++}
++#endif	/* GSCAN_SUPPORT || DHD_GET_VALID_CHANNELS */
++
++#ifdef RSSI_MONITOR_SUPPORT
++static int wl_cfgvendor_set_rssi_monitor(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0, tmp, type, start = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int8 max_rssi = 0, min_rssi = 0;
++	const struct nlattr *iter;
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++		switch (type) {
++			case RSSI_MONITOR_ATTRIBUTE_MAX_RSSI:
++				max_rssi = (int8) nla_get_u32(iter);
++				break;
++			case RSSI_MONITOR_ATTRIBUTE_MIN_RSSI:
++				min_rssi = (int8) nla_get_u32(iter);
++				break;
++			case RSSI_MONITOR_ATTRIBUTE_START:
++				start = nla_get_u32(iter);
++		}
++	}
++
++	if (dhd_dev_set_rssi_monitor_cfg(bcmcfg_to_prmry_ndev(cfg),
++	       start, max_rssi, min_rssi) < 0) {
++		WL_ERR(("Could not set rssi monitor cfg\n"));
++		err = -EINVAL;
++	}
++	return err;
++}
++#endif /* RSSI_MONITOR_SUPPORT */
++
++#ifdef DHDTCPACK_SUPPRESS
++static int wl_cfgvendor_set_tcpack_sup_mode(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0, tmp, type;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *ndev = wdev_to_wlc_ndev(wdev, cfg);
++	uint8 enable = 0;
++	const struct nlattr *iter;
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++		if (type == ANDR_WIFI_ATTRIBUTE_TCPACK_SUP_VALUE) {
++			enable = (int8)nla_get_u32(iter);
++		}
++	}
++
++	if (dhd_dev_set_tcpack_sup_mode_cfg(ndev, enable) < 0) {
++		WL_ERR(("Could not set TCP Ack Suppress mode cfg\n"));
++		err = -EINVAL;
++	}
++	return err;
++}
++#endif /* DHDTCPACK_SUPPRESS */
++
++#ifdef DHD_WAKE_STATUS
++static int
++wl_cfgvendor_get_wake_reason_stats(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void *data, int len)
++{
++	struct net_device *ndev = wdev_to_ndev(wdev);
++	wake_counts_t *pwake_count_info;
++	int ret, mem_needed;
++#if defined(DHD_WAKE_EVENT_STATUS) && defined(DHD_DEBUG)
++	int flowid;
++#endif	/* DHD_WAKE_EVENT_STATUS && DHD_DEBUG */
++	struct sk_buff *skb;
++	dhd_pub_t *dhdp = wl_cfg80211_get_dhdp(ndev);
++
++	WL_DBG(("Recv get wake status info cmd.\n"));
++
++	pwake_count_info = dhd_get_wakecount(dhdp);
++	mem_needed =  VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * 20) +
++		(WLC_E_LAST * sizeof(uint));
++
++	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		WL_ERR(("%s: can't allocate %d bytes\n", __FUNCTION__, mem_needed));
++		return -ENOMEM;
++		goto exit;
++	}
++#ifdef DHD_WAKE_EVENT_STATUS
++	WL_ERR(("pwake_count_info->rcwake %d\n", pwake_count_info->rcwake));
++	nla_put_u32(skb, WAKE_STAT_ATTRIBUTE_TOTAL_CMD_EVENT, pwake_count_info->rcwake);
++	nla_put_u32(skb, WAKE_STAT_ATTRIBUTE_CMD_EVENT_COUNT_USED, WLC_E_LAST);
++	nla_put(skb, WAKE_STAT_ATTRIBUTE_CMD_EVENT_WAKE, (WLC_E_LAST * sizeof(uint)),
++		pwake_count_info->rc_event);
++#ifdef DHD_DEBUG
++	for (flowid = 0; flowid < WLC_E_LAST; flowid++) {
++		if (pwake_count_info->rc_event[flowid] != 0) {
++			WL_ERR((" %s = %u\n", bcmevent_get_name(flowid),
++				pwake_count_info->rc_event[flowid]));
++		}
++	}
++#endif /* DHD_DEBUG */
++#endif /* DHD_WAKE_EVENT_STATUS */
++#ifdef DHD_WAKE_RX_STATUS
++	WL_ERR(("pwake_count_info->rxwake %d\n", pwake_count_info->rxwake));
++	nla_put_u32(skb, WAKE_STAT_ATTRIBUTE_TOTAL_RX_DATA_WAKE, pwake_count_info->rxwake);
++	nla_put_u32(skb, WAKE_STAT_ATTRIBUTE_RX_UNICAST_COUNT, pwake_count_info->rx_ucast);
++	nla_put_u32(skb, WAKE_STAT_ATTRIBUTE_RX_MULTICAST_COUNT, pwake_count_info->rx_mcast);
++	nla_put_u32(skb, WAKE_STAT_ATTRIBUTE_RX_BROADCAST_COUNT, pwake_count_info->rx_bcast);
++	nla_put_u32(skb, WAKE_STAT_ATTRIBUTE_RX_ICMP_PKT, pwake_count_info->rx_arp);
++	nla_put_u32(skb, WAKE_STAT_ATTRIBUTE_RX_ICMP6_PKT, pwake_count_info->rx_icmpv6);
++	nla_put_u32(skb, WAKE_STAT_ATTRIBUTE_RX_ICMP6_RA, pwake_count_info->rx_icmpv6_ra);
++	nla_put_u32(skb, WAKE_STAT_ATTRIBUTE_RX_ICMP6_NA, pwake_count_info->rx_icmpv6_na);
++	nla_put_u32(skb, WAKE_STAT_ATTRIBUTE_RX_ICMP6_NS, pwake_count_info->rx_icmpv6_ns);
++	nla_put_u32(skb, WAKE_STAT_ATTRIBUTE_IPV4_RX_MULTICAST_ADD_CNT,
++		pwake_count_info->rx_multi_ipv4);
++	nla_put_u32(skb, WAKE_STAT_ATTRIBUTE_IPV6_RX_MULTICAST_ADD_CNT,
++		pwake_count_info->rx_multi_ipv6);
++	nla_put_u32(skb, WAKE_STAT_ATTRIBUTE_OTHER_RX_MULTICAST_ADD_CNT,
++		pwake_count_info->rx_multi_other);
++#endif /* #ifdef DHD_WAKE_RX_STATUS */
++	ret = cfg80211_vendor_cmd_reply(skb);
++	if (unlikely(ret)) {
++		WL_ERR(("Vendor cmd reply for -get wake status failed:%d \n", ret));
++	}
++exit:
++	return ret;
++}
++#endif /* DHD_WAKE_STATUS */
++
++#ifdef RTT_SUPPORT
++void
++wl_cfgvendor_rtt_evt(void *ctx, void *rtt_data)
++{
++	struct wireless_dev *wdev = (struct wireless_dev *)ctx;
++	struct wiphy *wiphy;
++	struct sk_buff *skb;
++	uint32 evt_complete = 0;
++	gfp_t kflags;
++	rtt_result_t *rtt_result;
++	rtt_results_header_t *rtt_header;
++	struct list_head *rtt_cache_list;
++	struct nlattr *rtt_nl_hdr;
++	wiphy = wdev->wiphy;
++
++	WL_DBG(("In\n"));
++	/* Push the data to the skb */
++	if (!rtt_data) {
++		WL_ERR(("rtt_data is NULL\n"));
++		return;
++	}
++	rtt_cache_list = (struct list_head *)rtt_data;
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	if (list_empty(rtt_cache_list)) {
++#if (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || \
++	LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
++		skb = cfg80211_vendor_event_alloc(wiphy, NULL, 100,
++			GOOGLE_RTT_COMPLETE_EVENT, kflags);
++#else
++		skb = cfg80211_vendor_event_alloc(wiphy, 100, GOOGLE_RTT_COMPLETE_EVENT, kflags);
++#endif /* (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || */
++		/* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) */
++		if (!skb) {
++			WL_ERR(("skb alloc failed"));
++			return;
++		}
++		evt_complete = 1;
++		nla_put_u32(skb, RTT_ATTRIBUTE_RESULTS_COMPLETE, evt_complete);
++		cfg80211_vendor_event(skb, kflags);
++		return;
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	list_for_each_entry(rtt_header, rtt_cache_list, list) {
++		/* Alloc the SKB for vendor_event */
++#if (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || \
++	LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
++		skb = cfg80211_vendor_event_alloc(wiphy, NULL, rtt_header->result_tot_len + 100,
++			GOOGLE_RTT_COMPLETE_EVENT, kflags);
++#else
++		skb = cfg80211_vendor_event_alloc(wiphy, rtt_header->result_tot_len + 100,
++			GOOGLE_RTT_COMPLETE_EVENT, kflags);
++#endif /* (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || */
++		/* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) */
++		if (!skb) {
++			WL_ERR(("skb alloc failed"));
++			return;
++		}
++		if (list_is_last(&rtt_header->list, rtt_cache_list)) {
++			evt_complete = 1;
++		}
++		nla_put_u32(skb, RTT_ATTRIBUTE_RESULTS_COMPLETE, evt_complete);
++		rtt_nl_hdr = nla_nest_start(skb, RTT_ATTRIBUTE_RESULTS_PER_TARGET);
++		if (!rtt_nl_hdr) {
++			WL_ERR(("rtt_nl_hdr is NULL\n"));
++			break;
++		}
++		nla_put(skb, RTT_ATTRIBUTE_TARGET_MAC, ETHER_ADDR_LEN, &rtt_header->peer_mac);
++		nla_put_u32(skb, RTT_ATTRIBUTE_RESULT_CNT, rtt_header->result_cnt);
++		list_for_each_entry(rtt_result, &rtt_header->result_list, list) {
++			nla_put(skb, RTT_ATTRIBUTE_RESULT,
++				rtt_result->report_len, &rtt_result->report);
++		}
++		nla_nest_end(skb, rtt_nl_hdr);
++		cfg80211_vendor_event(skb, kflags);
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++}
++
++static int
++wl_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev *wdev,
++	const void *data, int len) {
++	int err = 0, rem, rem1, rem2, type;
++	int target_cnt;
++	rtt_config_params_t rtt_param;
++	rtt_target_info_t* rtt_target = NULL;
++	const struct nlattr *iter, *iter1, *iter2;
++	int8 eabuf[ETHER_ADDR_STR_LEN];
++	int8 chanbuf[CHANSPEC_STR_LEN];
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	rtt_capabilities_t capability;
++
++	memset(&rtt_param, 0, sizeof(rtt_param));
++
++	WL_DBG(("In\n"));
++	err = dhd_dev_rtt_register_noti_callback(wdev->netdev, wdev, wl_cfgvendor_rtt_evt);
++	if (err < 0) {
++		WL_ERR(("failed to register rtt_noti_callback\n"));
++		goto exit;
++	}
++	err = dhd_dev_rtt_capability(bcmcfg_to_prmry_ndev(cfg), &capability);
++	if (err < 0) {
++		WL_ERR(("failed to get the capability\n"));
++		goto exit;
++	}
++
++	if (len <= 0) {
++		WL_ERR(("Length of the nlattr is not valid len : %d\n", len));
++		err = BCME_ERROR;
++		goto exit;
++	}
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++		case RTT_ATTRIBUTE_TARGET_CNT:
++			target_cnt = nla_get_u8(iter);
++			if ((target_cnt <= 0) || (target_cnt > RTT_MAX_TARGET_CNT)) {
++				WL_ERR(("target_cnt is not valid : %d\n",
++					target_cnt));
++				err = BCME_RANGE;
++				goto exit;
++			}
++			rtt_param.rtt_target_cnt = target_cnt;
++
++			rtt_param.target_info = kzalloc(TARGET_INFO_SIZE(target_cnt), GFP_KERNEL);
++			if (rtt_param.target_info == NULL) {
++				WL_ERR(("failed to allocate target info for (%d)\n", target_cnt));
++				err = BCME_NOMEM;
++				goto exit;
++			}
++			break;
++		case RTT_ATTRIBUTE_TARGET_INFO:
++			/* Added this variable for safe check to avoid crash
++			 * incase the caller did not respect the order
++			 */
++			if (rtt_param.target_info == NULL) {
++				WL_ERR(("rtt_target_info is NULL\n"));
++				err = BCME_NOMEM;
++				goto exit;
++			}
++			rtt_target = rtt_param.target_info;
++			nla_for_each_nested(iter1, iter, rem1) {
++				nla_for_each_nested(iter2, iter1, rem2) {
++					type = nla_type(iter2);
++					switch (type) {
++					case RTT_ATTRIBUTE_TARGET_MAC:
++						memcpy(&rtt_target->addr, nla_data(iter2),
++							ETHER_ADDR_LEN);
++						break;
++					case RTT_ATTRIBUTE_TARGET_TYPE:
++						rtt_target->type = nla_get_u8(iter2);
++						if (rtt_target->type == RTT_INVALID ||
++							(rtt_target->type == RTT_ONE_WAY &&
++							!capability.rtt_one_sided_supported)) {
++							WL_ERR(("doesn't support RTT type"
++								" : %d\n",
++								rtt_target->type));
++							err = -EINVAL;
++							goto exit;
++						}
++						break;
++					case RTT_ATTRIBUTE_TARGET_PEER:
++						rtt_target->peer = nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_CHAN:
++						memcpy(&rtt_target->channel, nla_data(iter2),
++							sizeof(rtt_target->channel));
++						break;
++					case RTT_ATTRIBUTE_TARGET_PERIOD:
++						rtt_target->burst_period = nla_get_u32(iter2);
++						if (rtt_target->burst_period < 32) {
++							/* 100ms unit */
++							rtt_target->burst_period *= 100;
++						} else {
++							WL_ERR(("%d value must in (0-31)\n",
++								rtt_target->burst_period));
++							err = EINVAL;
++							goto exit;
++						}
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_BURST:
++						rtt_target->num_burst = nla_get_u32(iter2);
++						if (rtt_target->num_burst > 16) {
++							WL_ERR(("%d value must in (0-15)\n",
++								rtt_target->num_burst));
++							err = -EINVAL;
++							goto exit;
++						}
++						rtt_target->num_burst = BIT(rtt_target->num_burst);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_FTM_BURST:
++						rtt_target->num_frames_per_burst =
++						nla_get_u32(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_RETRY_FTM:
++						rtt_target->num_retries_per_ftm =
++						nla_get_u32(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_RETRY_FTMR:
++						rtt_target->num_retries_per_ftmr =
++						nla_get_u32(iter2);
++						if (rtt_target->num_retries_per_ftmr > 3) {
++							WL_ERR(("%d value must in (0-3)\n",
++								rtt_target->num_retries_per_ftmr));
++							err = -EINVAL;
++							goto exit;
++						}
++						break;
++					case RTT_ATTRIBUTE_TARGET_LCI:
++						rtt_target->LCI_request = nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_LCR:
++						rtt_target->LCI_request = nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_BURST_DURATION:
++						if ((nla_get_u32(iter2) > 1 &&
++							nla_get_u32(iter2) < 12)) {
++							rtt_target->burst_duration =
++							dhd_rtt_idx_to_burst_duration(
++								nla_get_u32(iter2));
++						} else if (nla_get_u32(iter2) == 15) {
++							/* use default value */
++							rtt_target->burst_duration = 0;
++						} else {
++							WL_ERR(("%d value must in (2-11) or 15\n",
++								nla_get_u32(iter2)));
++							err = -EINVAL;
++							goto exit;
++						}
++						break;
++					case RTT_ATTRIBUTE_TARGET_BW:
++						rtt_target->bw = nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_PREAMBLE:
++						rtt_target->preamble = nla_get_u8(iter2);
++						break;
++					}
++				}
++				/* convert to chanspec value */
++				rtt_target->chanspec =
++					dhd_rtt_convert_to_chspec(rtt_target->channel);
++				if (rtt_target->chanspec == 0) {
++					WL_ERR(("Channel is not valid \n"));
++					err = -EINVAL;
++					goto exit;
++				}
++				WL_INFORM(("Target addr %s, Channel : %s for RTT \n",
++					bcm_ether_ntoa((const struct ether_addr *)&rtt_target->addr,
++					eabuf),
++					wf_chspec_ntoa(rtt_target->chanspec, chanbuf)));
++				rtt_target++;
++			}
++			break;
++		}
++	}
++	WL_DBG(("leave :target_cnt : %d\n", rtt_param.rtt_target_cnt));
++	if (dhd_dev_rtt_set_cfg(bcmcfg_to_prmry_ndev(cfg), &rtt_param) < 0) {
++		WL_ERR(("Could not set RTT configuration\n"));
++		err = -EINVAL;
++	}
++exit:
++	/* free the target info list */
++	if (rtt_param.target_info) {
++		kfree(rtt_param.target_info);
++		rtt_param.target_info = NULL;
++	}
++	return err;
++}
++
++static int
++wl_cfgvendor_rtt_cancel_config(struct wiphy *wiphy, struct wireless_dev *wdev,
++	const void *data, int len)
++{
++	int err = 0, rem, type, target_cnt = 0;
++	int target_cnt_chk = 0;
++	const struct nlattr *iter;
++	struct ether_addr *mac_list = NULL, *mac_addr = NULL;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	if (len <= 0) {
++		WL_ERR(("Length of nlattr is not valid len : %d\n", len));
++		err = -EINVAL;
++		goto exit;
++	}
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++		case RTT_ATTRIBUTE_TARGET_CNT:
++			if (mac_list != NULL) {
++				WL_ERR(("mac_list is not NULL\n"));
++				err = -EINVAL;
++				goto exit;
++			}
++			target_cnt = nla_get_u8(iter);
++			if ((target_cnt > 0) && (target_cnt < RTT_MAX_TARGET_CNT)) {
++				mac_list = (struct ether_addr *)kzalloc(target_cnt * ETHER_ADDR_LEN,
++					GFP_KERNEL);
++				if (mac_list == NULL) {
++					WL_ERR(("failed to allocate mem for mac list\n"));
++					err = -EINVAL;
++					goto exit;
++				}
++				mac_addr = &mac_list[0];
++			} else {
++				/* cancel the current whole RTT process */
++				goto cancel;
++			}
++			break;
++		case RTT_ATTRIBUTE_TARGET_MAC:
++			if (mac_addr) {
++				memcpy(mac_addr++, nla_data(iter), ETHER_ADDR_LEN);
++				target_cnt_chk++;
++				if (target_cnt_chk > target_cnt) {
++					WL_ERR(("over target count\n"));
++					err = -EINVAL;
++					goto exit;
++				}
++				break;
++			} else {
++				WL_ERR(("mac_list is NULL\n"));
++				err = -EINVAL;
++				goto exit;
++			}
++		}
++	}
++cancel:
++	if (dhd_dev_rtt_cancel_cfg(bcmcfg_to_prmry_ndev(cfg), mac_list, target_cnt) < 0) {
++		WL_ERR(("Could not cancel RTT configuration\n"));
++		err = -EINVAL;
++	}
++
++exit:
++	if (mac_list) {
++		kfree(mac_list);
++	}
++	return err;
++}
++
++static int
++wl_cfgvendor_rtt_get_capability(struct wiphy *wiphy, struct wireless_dev *wdev,
++	const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	rtt_capabilities_t capability;
++
++	err = dhd_dev_rtt_capability(bcmcfg_to_prmry_ndev(cfg), &capability);
++	if (unlikely(err)) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++		goto exit;
++	}
++	err =  wl_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++	        &capability, sizeof(capability));
++
++	if (unlikely(err)) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++	}
++exit:
++	return err;
++}
++static int
++get_responder_info(struct bcm_cfg80211 *cfg,
++	struct wifi_rtt_responder *responder_info)
++{
++	int err = 0;
++	rtt_capabilities_t capability;
++	err = dhd_dev_rtt_capability(bcmcfg_to_prmry_ndev(cfg), &capability);
++	if (unlikely(err)) {
++		WL_ERR(("Could not get responder capability:%d \n", err));
++		return err;
++	}
++	if (capability.preamble_support & RTT_PREAMBLE_VHT) {
++		responder_info->preamble |= RTT_PREAMBLE_VHT;
++	}
++	if (capability.preamble_support & RTT_PREAMBLE_HT) {
++		responder_info->preamble |= RTT_PREAMBLE_HT;
++	}
++	err = dhd_dev_rtt_avail_channel(bcmcfg_to_prmry_ndev(cfg), &(responder_info->channel));
++	if (unlikely(err)) {
++		WL_ERR(("Could not get available channel:%d \n", err));
++		return err;
++	}
++	return err;
++}
++static int
++wl_cfgvendor_rtt_get_responder_info(struct wiphy *wiphy, struct wireless_dev *wdev,
++	const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	wifi_rtt_responder_t responder_info;
++
++	WL_DBG(("Recv -get_avail_ch command \n"));
++
++	memset(&responder_info, 0, sizeof(responder_info));
++	err = get_responder_info(cfg, &responder_info);
++	if (unlikely(err)) {
++		WL_ERR(("Failed to get responder info:%d \n", err));
++		return err;
++	}
++	err =  wl_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++	        &responder_info, sizeof(responder_info));
++
++	if (unlikely(err)) {
++		WL_ERR(("Vendor cmd reply for -get_avail_ch failed ret:%d \n", err));
++	}
++	return err;
++}
++
++static int
++wl_cfgvendor_rtt_set_responder(struct wiphy *wiphy, struct wireless_dev *wdev,
++	const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *ndev = wdev_to_wlc_ndev(wdev, cfg);
++	wifi_rtt_responder_t responder_info;
++
++	WL_DBG(("Recv rtt -enable_resp cmd.\n"));
++
++	memset(&responder_info, 0, sizeof(responder_info));
++
++	/*
++	*Passing channel as NULL until implementation
++	*to get chan info from upper layers is donex
++	*/
++	err = dhd_dev_rtt_enable_responder(ndev, NULL);
++	if (unlikely(err)) {
++		WL_ERR(("Could not enable responder ret:%d \n", err));
++		goto done;
++	}
++	err = get_responder_info(cfg, &responder_info);
++	if (unlikely(err)) {
++		WL_ERR(("Failed to get responder info:%d \n", err));
++		dhd_dev_rtt_cancel_responder(ndev);
++		goto done;
++	}
++done:
++	err =  wl_cfgvendor_send_cmd_reply(wiphy, ndev,
++			&responder_info, sizeof(responder_info));
++
++	if (unlikely(err)) {
++		WL_ERR(("Vendor cmd reply for -enable_resp failed ret:%d \n", err));
++	}
++	return err;
++}
++
++static int
++wl_cfgvendor_rtt_cancel_responder(struct wiphy *wiphy, struct wireless_dev *wdev,
++	const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	WL_DBG(("Recv rtt -cancel_resp cmd \n"));
++
++	err = dhd_dev_rtt_cancel_responder(bcmcfg_to_prmry_ndev(cfg));
++	if (unlikely(err)) {
++		WL_ERR(("Vendor cmd -cancel_resp failed ret:%d \n", err));
++	}
++	return err;
++}
++#endif /* RTT_SUPPORT */
++
++#ifdef GSCAN_SUPPORT
++static int wl_cfgvendor_enable_lazy_roam(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = -EINVAL;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type;
++	uint32 lazy_roam_enable_flag;
++
++	type = nla_type(data);
++
++	if (type == GSCAN_ATTRIBUTE_LAZY_ROAM_ENABLE) {
++		lazy_roam_enable_flag = nla_get_u32(data);
++
++		err = dhd_dev_lazy_roam_enable(bcmcfg_to_prmry_ndev(cfg),
++		           lazy_roam_enable_flag);
++
++		if (unlikely(err))
++			WL_ERR(("Could not enable lazy roam:%d \n", err));
++
++	}
++	return err;
++}
++
++static int wl_cfgvendor_set_lazy_roam_cfg(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0, tmp, type;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	wlc_roam_exp_params_t roam_param;
++	const struct nlattr *iter;
++
++	memset(&roam_param, 0, sizeof(roam_param));
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++
++		switch (type) {
++			case GSCAN_ATTRIBUTE_A_BAND_BOOST_THRESHOLD:
++				roam_param.a_band_boost_threshold = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_A_BAND_PENALTY_THRESHOLD:
++				roam_param.a_band_penalty_threshold = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_A_BAND_BOOST_FACTOR:
++				roam_param.a_band_boost_factor = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_A_BAND_PENALTY_FACTOR:
++				roam_param.a_band_penalty_factor = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_A_BAND_MAX_BOOST:
++				roam_param.a_band_max_boost = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_LAZY_ROAM_HYSTERESIS:
++				roam_param.cur_bssid_boost = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_ALERT_ROAM_RSSI_TRIGGER:
++				roam_param.alert_roam_trigger_threshold = nla_get_u32(iter);
++				break;
++		}
++	}
++
++	if (dhd_dev_set_lazy_roam_cfg(bcmcfg_to_prmry_ndev(cfg), &roam_param) < 0) {
++		WL_ERR(("Could not set batch cfg\n"));
++		err = -EINVAL;
++	}
++	return err;
++}
++
++/* small helper function */
++static wl_bssid_pref_cfg_t *
++create_bssid_pref_cfg(uint32 num)
++{
++	uint32 mem_needed;
++	wl_bssid_pref_cfg_t *bssid_pref;
++
++	mem_needed = sizeof(wl_bssid_pref_cfg_t);
++	if (num)
++		mem_needed += (num - 1) * sizeof(wl_bssid_pref_list_t);
++	bssid_pref = (wl_bssid_pref_cfg_t *) kmalloc(mem_needed, GFP_KERNEL);
++	return bssid_pref;
++}
++
++static int
++wl_cfgvendor_set_bssid_pref(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	wl_bssid_pref_cfg_t *bssid_pref = NULL;
++	wl_bssid_pref_list_t *bssids;
++	int tmp, tmp1, tmp2, type;
++	const struct nlattr *outer, *inner, *iter;
++	uint32 flush = 0, i = 0, num = 0;
++
++	/* Assumption: NUM attribute must come first */
++	nla_for_each_attr(iter, data, len, tmp2) {
++		type = nla_type(iter);
++		switch (type) {
++			case GSCAN_ATTRIBUTE_NUM_BSSID:
++				num = nla_get_u32(iter);
++				if (num > MAX_BSSID_PREF_LIST_NUM) {
++					WL_ERR(("Too many Preferred BSSIDs!\n"));
++					err = -EINVAL;
++					goto exit;
++				}
++				break;
++			case GSCAN_ATTRIBUTE_BSSID_PREF_FLUSH:
++				flush = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_BSSID_PREF_LIST:
++				if (!num)
++					return -EINVAL;
++				if ((bssid_pref = create_bssid_pref_cfg(num)) == NULL) {
++					WL_ERR(("%s: Can't malloc memory\n", __FUNCTION__));
++					err = -ENOMEM;
++					goto exit;
++				}
++				bssid_pref->count = num;
++				bssids = bssid_pref->bssids;
++				nla_for_each_nested(outer, iter, tmp) {
++					if (i >= num) {
++						WL_ERR(("CFGs don't seem right!\n"));
++						err = -EINVAL;
++						goto exit;
++					}
++					nla_for_each_nested(inner, outer, tmp1) {
++						type = nla_type(inner);
++						switch (type) {
++							case GSCAN_ATTRIBUTE_BSSID_PREF:
++								memcpy(&(bssids[i].bssid),
++								  nla_data(inner), ETHER_ADDR_LEN);
++								/* not used for now */
++								bssids[i].flags = 0;
++								break;
++							case GSCAN_ATTRIBUTE_RSSI_MODIFIER:
++								bssids[i].rssi_factor =
++								       (int8) nla_get_u32(inner);
++								break;
++						}
++					}
++					i++;
++				}
++				break;
++			default:
++				WL_ERR(("%s: No such attribute %d\n", __FUNCTION__, type));
++				break;
++			}
++	}
++
++	if (!bssid_pref) {
++		/* What if only flush is desired? */
++		if (flush) {
++			if ((bssid_pref = create_bssid_pref_cfg(0)) == NULL) {
++				WL_ERR(("%s: Can't malloc memory\n", __FUNCTION__));
++				err = -ENOMEM;
++				goto exit;
++			}
++			bssid_pref->count = 0;
++		} else {
++			err = -EINVAL;
++			goto exit;
++		}
++	}
++	err = dhd_dev_set_lazy_roam_bssid_pref(bcmcfg_to_prmry_ndev(cfg),
++	          bssid_pref, flush);
++exit:
++	kfree(bssid_pref);
++	return err;
++}
++
++static int
++wl_cfgvendor_set_bssid_blacklist(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	maclist_t *blacklist = NULL;
++	int err = 0;
++	int type, tmp;
++	const struct nlattr *iter;
++	uint32 mem_needed = 0, flush = 0, i = 0, num = 0;
++
++	/* Assumption: NUM attribute must come first */
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++		switch (type) {
++			case GSCAN_ATTRIBUTE_NUM_BSSID:
++				num = nla_get_u32(iter);
++				if (num > MAX_BSSID_BLACKLIST_NUM) {
++					WL_ERR(("Too many Blacklist BSSIDs!\n"));
++					err = -EINVAL;
++					goto exit;
++				}
++				break;
++			case GSCAN_ATTRIBUTE_BSSID_BLACKLIST_FLUSH:
++				flush = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_BLACKLIST_BSSID:
++				if (num) {
++					if (!blacklist) {
++						mem_needed = sizeof(maclist_t) +
++						     sizeof(struct ether_addr) * (num - 1);
++						blacklist = (maclist_t *)
++						      kmalloc(mem_needed, GFP_KERNEL);
++						if (!blacklist) {
++							WL_ERR(("%s: Can't malloc %d bytes\n",
++							     __FUNCTION__, mem_needed));
++							err = -ENOMEM;
++							goto exit;
++						}
++						blacklist->count = num;
++					}
++					if (i >= num) {
++						WL_ERR(("CFGs don't seem right!\n"));
++						err = -EINVAL;
++						goto exit;
++					}
++					memcpy(&(blacklist->ea[i]),
++					  nla_data(iter), ETHER_ADDR_LEN);
++					i++;
++				}
++				break;
++			default:
++				WL_ERR(("%s: No such attribute %d\n", __FUNCTION__, type));
++				break;
++			}
++	}
++	err = dhd_dev_set_blacklist_bssid(bcmcfg_to_prmry_ndev(cfg),
++	          blacklist, mem_needed, flush);
++exit:
++	kfree(blacklist);
++	return err;
++}
++
++static int
++wl_cfgvendor_set_ssid_whitelist(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	wl_ssid_whitelist_t *ssid_whitelist = NULL;
++	wlc_ssid_t *ssid_elem;
++	int tmp, tmp2, mem_needed = 0, type;
++	const struct nlattr *inner, *iter;
++	uint32 flush = 0, i = 0, num = 0;
++
++	/* Assumption: NUM attribute must come first */
++	nla_for_each_attr(iter, data, len, tmp2) {
++		type = nla_type(iter);
++		switch (type) {
++			case GSCAN_ATTRIBUTE_NUM_WL_SSID:
++				num = nla_get_u32(iter);
++				if (num > MAX_SSID_WHITELIST_NUM) {
++					WL_ERR(("Too many WL SSIDs!\n"));
++					err = -EINVAL;
++					goto exit;
++				}
++				mem_needed = sizeof(wl_ssid_whitelist_t);
++				if (num)
++					mem_needed += (num - 1) * sizeof(ssid_info_t);
++				ssid_whitelist = (wl_ssid_whitelist_t *)
++				        kzalloc(mem_needed, GFP_KERNEL);
++				if (ssid_whitelist == NULL) {
++					WL_ERR(("%s: Can't malloc %d bytes\n",
++					      __FUNCTION__, mem_needed));
++					err = -ENOMEM;
++					goto exit;
++				}
++				ssid_whitelist->ssid_count = num;
++				break;
++			case GSCAN_ATTRIBUTE_WL_SSID_FLUSH:
++				flush = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_WHITELIST_SSID_ELEM:
++				if (!num || !ssid_whitelist) {
++					WL_ERR(("num ssid is not set!\n"));
++					return -EINVAL;
++				}
++				if (i >= num) {
++					WL_ERR(("CFGs don't seem right!\n"));
++					err = -EINVAL;
++					goto exit;
++				}
++				ssid_elem = &ssid_whitelist->ssids[i];
++				nla_for_each_nested(inner, iter, tmp) {
++					type = nla_type(inner);
++					switch (type) {
++						case GSCAN_ATTRIBUTE_WHITELIST_SSID:
++							memcpy(ssid_elem->SSID,
++							  nla_data(inner),
++							  DOT11_MAX_SSID_LEN);
++							break;
++						case GSCAN_ATTRIBUTE_WL_SSID_LEN:
++							ssid_elem->SSID_len = (uint8)
++							        nla_get_u32(inner);
++							break;
++					}
++				}
++				i++;
++				break;
++			default:
++				WL_ERR(("%s: No such attribute %d\n", __FUNCTION__, type));
++				break;
++		}
++	}
++
++	err = dhd_dev_set_whitelist_ssid(bcmcfg_to_prmry_ndev(cfg),
++	          ssid_whitelist, mem_needed, flush);
++exit:
++	kfree(ssid_whitelist);
++	return err;
++}
++#endif /* GSCAN_SUPPORT */
++
++static int
++wl_cfgvendor_priv_string_handler(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int ret = 0;
++	int ret_len = 0, payload = 0, msglen;
++	const struct bcm_nlmsg_hdr *nlioc = data;
++	void *buf = NULL, *cur;
++	int maxmsglen = PAGE_SIZE - 0x100;
++	struct sk_buff *reply;
++
++	WL_ERR(("entry: cmd = %d\n", nlioc->cmd));
++
++	len -= sizeof(struct bcm_nlmsg_hdr);
++	ret_len = nlioc->len;
++	if (ret_len > 0 || len > 0) {
++		if (len > DHD_IOCTL_MAXLEN) {
++			WL_ERR(("oversize input buffer %d\n", len));
++			len = DHD_IOCTL_MAXLEN;
++		}
++		if (ret_len > DHD_IOCTL_MAXLEN) {
++			WL_ERR(("oversize return buffer %d\n", ret_len));
++			ret_len = DHD_IOCTL_MAXLEN;
++		}
++		payload = max(ret_len, len) + 1;
++		buf = vzalloc(payload);
++		if (!buf) {
++			return -ENOMEM;
++		}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++		memcpy(buf, (void *)((char *)nlioc + nlioc->offset), len);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++		*((char *)buf + len) = '\0';
++	}
++
++	ret = dhd_cfgvendor_priv_string_handler(cfg, wdev, nlioc, buf);
++	if (ret) {
++		WL_ERR(("dhd_cfgvendor returned error %d", ret));
++		vfree(buf);
++		return ret;
++	}
++	cur = buf;
++	while (ret_len > 0) {
++		msglen = nlioc->len > maxmsglen ? maxmsglen : ret_len;
++		ret_len -= msglen;
++		payload = msglen + sizeof(msglen);
++		reply = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, payload);
++		if (!reply) {
++			WL_ERR(("Failed to allocate reply msg\n"));
++			ret = -ENOMEM;
++			break;
++		}
++
++		if (nla_put(reply, BCM_NLATTR_DATA, msglen, cur) ||
++			nla_put_u16(reply, BCM_NLATTR_LEN, msglen)) {
++			kfree_skb(reply);
++			ret = -ENOBUFS;
++			break;
++		}
++
++		ret = cfg80211_vendor_cmd_reply(reply);
++		if (ret) {
++			WL_ERR(("testmode reply failed:%d\n", ret));
++			break;
++		}
++		cur = (void *)((char *)cur + msglen);
++	}
++
++	return ret;
++}
++
++struct net_device *
++wl_cfgvendor_get_ndev(struct bcm_cfg80211 *cfg, struct wireless_dev *wdev,
++	const void *data, unsigned long int *out_addr)
++{
++	char *pos, *pos1;
++	char ifname[IFNAMSIZ + 1] = {0};
++	struct net_info *iter, *next;
++	struct net_device *ndev = NULL;
++	*out_addr = (unsigned long int) data; /* point to command str by default */
++
++	/* check whether ifname=<ifname> is provided in the command */
++	pos = strstr(data, "ifname=");
++	if (pos) {
++		pos += strlen("ifname=");
++		pos1 = strstr(pos, " ");
++		if (!pos1) {
++			WL_ERR(("command format error \n"));
++			return NULL;
++		}
++		memcpy(ifname, pos, (pos1 - pos));
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++		for_each_ndev(cfg, iter, next) {
++			if (iter->ndev) {
++				if (strncmp(iter->ndev->name, ifname,
++					strlen(iter->ndev->name)) == 0) {
++					/* matching ifname found */
++					WL_DBG(("matching interface (%s) found ndev:%p \n",
++						iter->ndev->name, iter->ndev));
++					*out_addr = (unsigned long int)(pos1 + 1);
++					/* Returns the command portion after ifname=<name> */
++					return iter->ndev;
++				}
++			}
++		}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++		WL_ERR(("Couldn't find ifname:%s in the netinfo list \n",
++			ifname));
++		return NULL;
++	}
++
++	/* If ifname=<name> arg is not provided, use default ndev */
++	ndev = wdev->netdev ? wdev->netdev : bcmcfg_to_prmry_ndev(cfg);
++	WL_DBG(("Using default ndev (%s) \n", ndev->name));
++	return ndev;
++}
++
++#ifdef WL_SAE
++static int
++wl_cfgvendor_set_sae_password(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = BCME_OK;
++	struct net_device *net = wdev->netdev;
++	struct bcm_cfg80211 *cfg = wl_get_cfg(net);
++	wsec_pmk_t pmk;
++	s32 bssidx;
++
++	/* clear the content of pmk structure before usage */
++	(void)memset(&pmk, 0x0, sizeof(wsec_pmk_t));
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, net->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", net->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	if ((len < WSEC_MIN_PSK_LEN) || (len >= WSEC_MAX_PASSPHRASE_LEN)) {
++		WL_ERR(("Invalid passphrase length %d..should be >= 8 and < 256\n",
++			len));
++		err = BCME_BADLEN;
++		goto done;
++	}
++	/* Set AUTH to SAE */
++	err = wldev_iovar_setint_bsscfg(net, "wpa_auth", WPA3_AUTH_SAE_PSK, bssidx);
++	if (unlikely(err)) {
++		WL_ERR(("could not set wpa_auth (0x%x)\n", err));
++		goto done;
++	}
++	pmk.key_len = htod16(len);
++	bcopy((const u8*)data, pmk.key, len);
++	pmk.flags = htod16(WSEC_PASSPHRASE);
++
++	err = wldev_ioctl_set(net, WLC_SET_WSEC_PMK, &pmk, sizeof(pmk));
++	if (err) {
++		WL_ERR(("\n failed to set pmk %d\n", err));
++		goto done;
++	} else {
++		WL_INFORM(("sae passphrase set successfully\n"));
++	}
++done:
++	return err;
++}
++#endif /* WL_SAE */
++
++/* Max length for the reply buffer. For BRCM_ATTR_DRIVER_CMD, the reply
++ * would be a formatted string and reply buf would be the size of the
++ * string.
++ */
++#define WL_DRIVER_PRIV_CMD_LEN 512
++static int
++wl_cfgvendor_priv_bcm_handler(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	const struct nlattr *iter;
++	int err = 0;
++	int data_len = 0, cmd_len = 0, tmp = 0, type = 0;
++	struct net_device *ndev = wdev->netdev;
++	char *reply_buf = NULL;
++	char *cmd = NULL;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int bytes_written;
++	struct net_device *net = NULL;
++	unsigned long int cmd_out = 0;
++	u32 reply_len = WL_DRIVER_PRIV_CMD_LEN;
++
++
++	WL_DBG(("%s: Enter \n", __func__));
++
++	/* hold wake lock */
++	net_os_wake_lock(ndev);
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++		cmd = nla_data(iter);
++		cmd_len = nla_len(iter);
++
++		WL_DBG(("%s: type: %d cmd_len:%d cmd_ptr:%p \n", __func__, type, cmd_len, cmd));
++		if (!cmd || !cmd_len) {
++			WL_ERR(("Invalid cmd data \n"));
++			err = -EINVAL;
++			goto exit;
++		}
++
++		if (type == BRCM_ATTR_DRIVER_CMD) {
++			if (cmd_len >= WL_DRIVER_PRIV_CMD_LEN) {
++				WL_ERR(("Unexpected command length. Ignore the command\n"));
++				err = -EINVAL;
++				goto exit;
++			}
++			net = wl_cfgvendor_get_ndev(cfg, wdev, cmd, &cmd_out);
++			if (!cmd_out || !net) {
++				err = -ENODEV;
++				goto exit;
++			}
++			cmd = (char *)cmd_out;
++			reply_buf = kzalloc(reply_len, GFP_KERNEL);
++			if (!reply_buf) {
++				WL_ERR(("memory alloc failed for %u \n", cmd_len));
++				err = -ENOMEM;
++				goto exit;
++			}
++			memcpy(reply_buf, cmd, cmd_len);
++			WL_DBG(("vendor_command: %s len: %u \n", cmd, cmd_len));
++			bytes_written = wl_handle_private_cmd(net, reply_buf, reply_len);
++			WL_DBG(("bytes_written: %d \n", bytes_written));
++			if (bytes_written == 0) {
++				snprintf(reply_buf, reply_len, "%s", "OK");
++				data_len = strlen("OK");
++			} else if (bytes_written > 0) {
++				data_len = bytes_written > reply_len ?
++					reply_len : bytes_written;
++			} else {
++				/* -ve return value. Propagate the error back */
++				err = bytes_written;
++				goto exit;
++			}
++			break;
++		}
++	}
++
++	if ((data_len > 0) && reply_buf) {
++		err =  wl_cfgvendor_send_cmd_reply(wiphy, wdev->netdev,
++			reply_buf, data_len+1);
++		if (unlikely(err))
++			WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++		else
++			WL_DBG(("Vendor Command reply sent successfully!\n"));
++	} else {
++		/* No data to be sent back as reply */
++		WL_ERR(("Vendor_cmd: No reply expected. data_len:%u reply_buf %p \n",
++			data_len, reply_buf));
++	}
++
++exit:
++	if (reply_buf)
++		kfree(reply_buf);
++	net_os_wake_unlock(ndev);
++	return err;
++}
++
++
++#ifdef LINKSTAT_SUPPORT
++#define NUM_RATE 32
++#define NUM_PEER 1
++#define NUM_CHAN 11
++#define HEADER_SIZE sizeof(ver_len)
++static int wl_cfgvendor_lstats_get_info(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	static char iovar_buf[WLC_IOCTL_MAXLEN];
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int err = 0, i;
++	wifi_radio_stat *radio;
++	wifi_radio_stat_h radio_h;
++	wl_wme_cnt_t *wl_wme_cnt;
++	wl_cnt_ge40mcst_v1_t *macstat_cnt;
++	wl_cnt_wlc_t *wlc_cnt;
++	scb_val_t scbval;
++	char *output = NULL;
++	char *outdata = NULL;
++	wifi_rate_stat_v1 *p_wifi_rate_stat_v1 = NULL;
++	wifi_rate_stat *p_wifi_rate_stat = NULL;
++	uint total_len = 0;
++	wifi_iface_stat iface;
++	wlc_rev_info_t revinfo;
++#ifdef CONFIG_COMPAT
++	compat_wifi_iface_stat compat_iface;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 6, 0))
++	int compat_task_state = in_compat_syscall();
++#else
++	int compat_task_state = is_compat_task();
++#endif
++#endif /* CONFIG_COMPAT */
++
++	WL_INFORM(("%s: Enter \n", __func__));
++	RETURN_EIO_IF_NOT_UP(cfg);
++
++	/* Get the device rev info */
++	memset(&revinfo, 0, sizeof(revinfo));
++	err = wldev_ioctl_get(bcmcfg_to_prmry_ndev(cfg), WLC_GET_REVINFO, &revinfo,
++			sizeof(revinfo));
++	if (err != BCME_OK) {
++		goto exit;
++	}
++
++	outdata = (void *)kzalloc(WLC_IOCTL_MAXLEN, GFP_KERNEL);
++	if (outdata == NULL) {
++		WL_ERR(("%s: alloc failed\n", __func__));
++		return -ENOMEM;
++	}
++
++	memset(&scbval, 0, sizeof(scb_val_t));
++	memset(outdata, 0, WLC_IOCTL_MAXLEN);
++	output = outdata;
++
++	err = wldev_iovar_getbuf(bcmcfg_to_prmry_ndev(cfg), "radiostat", NULL, 0,
++		iovar_buf, WLC_IOCTL_MAXLEN, NULL);
++	if (err != BCME_OK && err != BCME_UNSUPPORTED) {
++		WL_ERR(("error (%d) - size = %zu\n", err, sizeof(wifi_radio_stat)));
++		goto exit;
++	}
++	radio = (wifi_radio_stat *)iovar_buf;
++
++	memset(&radio_h, 0, sizeof(wifi_radio_stat_h));
++	radio_h.on_time = radio->on_time;
++	radio_h.tx_time = radio->tx_time;
++	radio_h.rx_time = radio->rx_time;
++	radio_h.on_time_scan = radio->on_time_scan;
++	radio_h.on_time_nbd = radio->on_time_nbd;
++	radio_h.on_time_gscan = radio->on_time_gscan;
++	radio_h.on_time_roam_scan = radio->on_time_roam_scan;
++	radio_h.on_time_pno_scan = radio->on_time_pno_scan;
++	radio_h.on_time_hs20 = radio->on_time_hs20;
++	radio_h.num_channels = NUM_CHAN;
++
++	memcpy(output, &radio_h, sizeof(wifi_radio_stat_h));
++
++	output += sizeof(wifi_radio_stat_h);
++	output += (NUM_CHAN * sizeof(wifi_channel_stat));
++
++	err = wldev_iovar_getbuf(bcmcfg_to_prmry_ndev(cfg), "wme_counters", NULL, 0,
++		iovar_buf, WLC_IOCTL_MAXLEN, NULL);
++	if (unlikely(err)) {
++		WL_ERR(("error (%d)\n", err));
++		goto exit;
++	}
++	wl_wme_cnt = (wl_wme_cnt_t *)iovar_buf;
++
++	COMPAT_ASSIGN_VALUE(iface, ac[WIFI_AC_VO].ac, WIFI_AC_VO);
++	COMPAT_ASSIGN_VALUE(iface, ac[WIFI_AC_VO].tx_mpdu, wl_wme_cnt->tx[AC_VO].packets);
++	COMPAT_ASSIGN_VALUE(iface, ac[WIFI_AC_VO].rx_mpdu, wl_wme_cnt->rx[AC_VO].packets);
++	COMPAT_ASSIGN_VALUE(iface, ac[WIFI_AC_VO].mpdu_lost,
++		wl_wme_cnt->tx_failed[WIFI_AC_VO].packets);
++
++	COMPAT_ASSIGN_VALUE(iface, ac[WIFI_AC_VI].ac, WIFI_AC_VI);
++	COMPAT_ASSIGN_VALUE(iface, ac[WIFI_AC_VI].tx_mpdu, wl_wme_cnt->tx[AC_VI].packets);
++	COMPAT_ASSIGN_VALUE(iface, ac[WIFI_AC_VI].rx_mpdu, wl_wme_cnt->rx[AC_VI].packets);
++	COMPAT_ASSIGN_VALUE(iface, ac[WIFI_AC_VI].mpdu_lost,
++		wl_wme_cnt->tx_failed[WIFI_AC_VI].packets);
++
++	COMPAT_ASSIGN_VALUE(iface, ac[WIFI_AC_BE].ac, WIFI_AC_BE);
++	COMPAT_ASSIGN_VALUE(iface, ac[WIFI_AC_BE].tx_mpdu, wl_wme_cnt->tx[AC_BE].packets);
++	COMPAT_ASSIGN_VALUE(iface, ac[WIFI_AC_BE].rx_mpdu, wl_wme_cnt->rx[AC_BE].packets);
++	COMPAT_ASSIGN_VALUE(iface, ac[WIFI_AC_BE].mpdu_lost,
++		wl_wme_cnt->tx_failed[WIFI_AC_BE].packets);
++
++	COMPAT_ASSIGN_VALUE(iface, ac[WIFI_AC_BK].ac, WIFI_AC_BK);
++	COMPAT_ASSIGN_VALUE(iface, ac[WIFI_AC_BK].tx_mpdu, wl_wme_cnt->tx[AC_BK].packets);
++	COMPAT_ASSIGN_VALUE(iface, ac[WIFI_AC_BK].rx_mpdu, wl_wme_cnt->rx[AC_BK].packets);
++	COMPAT_ASSIGN_VALUE(iface, ac[WIFI_AC_BK].mpdu_lost,
++		wl_wme_cnt->tx_failed[WIFI_AC_BK].packets);
++
++
++	err = wldev_iovar_getbuf(bcmcfg_to_prmry_ndev(cfg), "counters", NULL, 0,
++		iovar_buf, WLC_IOCTL_MAXLEN, NULL);
++	if (unlikely(err)) {
++		WL_ERR(("error (%d) - size = %zu\n", err, sizeof(wl_cnt_wlc_t)));
++		goto exit;
++	}
++
++	CHK_CNTBUF_DATALEN(iovar_buf, WLC_IOCTL_MAXLEN);
++
++#ifdef STAT_REPORT
++	wl_stat_report_gather(cfg, iovar_buf);
++#endif
++
++	/* Translate traditional (ver <= 10) counters struct to new xtlv type struct */
++	err = wl_cntbuf_to_xtlv_format(NULL, iovar_buf, WLC_IOCTL_MAXLEN, revinfo.corerev);
++	if (err != BCME_OK) {
++		WL_ERR(("%s wl_cntbuf_to_xtlv_format ERR %d\n",
++			__FUNCTION__, err));
++		goto exit;
++	}
++
++	if (!(wlc_cnt = GET_WLCCNT_FROM_CNTBUF(iovar_buf))) {
++		WL_ERR(("%s wlc_cnt NULL!\n", __FUNCTION__));
++		err = BCME_ERROR;
++		goto exit;
++	}
++
++	COMPAT_ASSIGN_VALUE(iface, ac[WIFI_AC_BE].retries, wlc_cnt->txretry);
++
++	if ((macstat_cnt = bcm_get_data_from_xtlv_buf(((wl_cnt_info_t *)iovar_buf)->data,
++			((wl_cnt_info_t *)iovar_buf)->datalen,
++			WL_CNT_XTLV_CNTV_LE10_UCODE, NULL,
++			BCM_XTLV_OPTION_ALIGN32)) == NULL) {
++		if ((macstat_cnt = bcm_get_data_from_xtlv_buf(((wl_cnt_info_t *)iovar_buf)->data,
++				((wl_cnt_info_t *)iovar_buf)->datalen,
++				WL_CNT_XTLV_GE40_UCODE_V1, NULL,
++				BCM_XTLV_OPTION_ALIGN32)) == NULL) {
++			macstat_cnt = bcm_get_data_from_xtlv_buf(((wl_cnt_info_t *)iovar_buf)->data,
++				((wl_cnt_info_t *)iovar_buf)->datalen,
++				WL_CNT_XTLV_LT40_UCODE_V1, NULL,
++				BCM_XTLV_OPTION_ALIGN32);
++		}
++	}
++
++	if (macstat_cnt == NULL) {
++		printf("wlmTxGetAckedPackets: macstat_cnt NULL!\n");
++		err = BCME_ERROR;
++		goto exit;
++	}
++
++	err = wldev_get_rssi(bcmcfg_to_prmry_ndev(cfg), &scbval);
++	if (unlikely(err)) {
++		WL_ERR(("get_rssi error (%d)\n", err));
++		goto exit;
++	}
++
++	COMPAT_ASSIGN_VALUE(iface, beacon_rx, macstat_cnt->rxbeaconmbss);
++	COMPAT_ASSIGN_VALUE(iface, rssi_mgmt, scbval.val);
++	COMPAT_ASSIGN_VALUE(iface, num_peers, NUM_PEER);
++	COMPAT_ASSIGN_VALUE(iface, peer_info->num_rate, NUM_RATE);
++
++#ifdef CONFIG_COMPAT
++	if (compat_task_state) {
++		memcpy(output, &compat_iface, sizeof(compat_iface));
++		output += (sizeof(compat_iface) - sizeof(wifi_rate_stat));
++	} else
++#endif /* CONFIG_COMPAT */
++	{
++		memcpy(output, &iface, sizeof(iface));
++		output += (sizeof(iface) - sizeof(wifi_rate_stat));
++	}
++
++	err = wldev_iovar_getbuf(bcmcfg_to_prmry_ndev(cfg), "ratestat", NULL, 0,
++		iovar_buf, WLC_IOCTL_MAXLEN, NULL);
++	if (err != BCME_OK && err != BCME_UNSUPPORTED) {
++		WL_ERR(("error (%d) - size = %zu\n", err, NUM_RATE*sizeof(wifi_rate_stat)));
++		goto exit;
++	}
++	for (i = 0; i < NUM_RATE; i++) {
++		p_wifi_rate_stat =
++			(wifi_rate_stat *)(iovar_buf + i*sizeof(wifi_rate_stat));
++		p_wifi_rate_stat_v1 = (wifi_rate_stat_v1 *)output;
++		p_wifi_rate_stat_v1->rate.preamble = p_wifi_rate_stat->rate.preamble;
++		p_wifi_rate_stat_v1->rate.nss = p_wifi_rate_stat->rate.nss;
++		p_wifi_rate_stat_v1->rate.bw = p_wifi_rate_stat->rate.bw;
++		p_wifi_rate_stat_v1->rate.rateMcsIdx = p_wifi_rate_stat->rate.rateMcsIdx;
++		p_wifi_rate_stat_v1->rate.reserved = p_wifi_rate_stat->rate.reserved;
++		p_wifi_rate_stat_v1->rate.bitrate = p_wifi_rate_stat->rate.bitrate;
++		p_wifi_rate_stat_v1->tx_mpdu = p_wifi_rate_stat->tx_mpdu;
++		p_wifi_rate_stat_v1->rx_mpdu = p_wifi_rate_stat->rx_mpdu;
++		p_wifi_rate_stat_v1->mpdu_lost = p_wifi_rate_stat->mpdu_lost;
++		p_wifi_rate_stat_v1->retries = p_wifi_rate_stat->retries;
++		p_wifi_rate_stat_v1->retries_short = p_wifi_rate_stat->retries_short;
++		p_wifi_rate_stat_v1->retries_long = p_wifi_rate_stat->retries_long;
++		output = (char *) &(p_wifi_rate_stat_v1->retries_long);
++		output += sizeof(p_wifi_rate_stat_v1->retries_long);
++	}
++
++	total_len = sizeof(wifi_radio_stat_h) +
++		NUM_CHAN * sizeof(wifi_channel_stat);
++
++#ifdef CONFIG_COMPAT
++	if (compat_task_state) {
++		total_len += sizeof(compat_wifi_iface_stat);
++	} else
++#endif /* CONFIG_COMPAT */
++	{
++		total_len += sizeof(wifi_iface_stat);
++	}
++
++	total_len = total_len - sizeof(wifi_peer_info) +
++		NUM_PEER * (sizeof(wifi_peer_info) - sizeof(wifi_rate_stat_v1) +
++			NUM_RATE * sizeof(wifi_rate_stat_v1));
++
++	if (total_len > WLC_IOCTL_MAXLEN) {
++		WL_ERR(("Error! total_len:%d is unexpected value\n", total_len));
++		err = BCME_BADLEN;
++		goto exit;
++	}
++	err =  wl_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++		outdata,
++		total_len);
++
++	if (unlikely(err))
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++
++exit:
++	if (outdata) {
++		kfree(outdata);
++	}
++	return err;
++}
++#endif /* LINKSTAT_SUPPORT */
++
++#ifdef DEBUGABILITY
++static int wl_cfgvendor_dbg_start_logging(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = BCME_OK, rem, type;
++	char ring_name[DBGRING_NAME_MAX] = {0};
++	int log_level = 0, flags = 0, time_intval = 0, threshold = 0;
++	const struct nlattr *iter;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd_pub = cfg->pub;
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case DEBUG_ATTRIBUTE_RING_NAME:
++				strncpy(ring_name, nla_data(iter),
++					MIN(sizeof(ring_name) -1, nla_len(iter)));
++				break;
++			case DEBUG_ATTRIBUTE_LOG_LEVEL:
++				log_level = nla_get_u32(iter);
++				break;
++			case DEBUG_ATTRIBUTE_RING_FLAGS:
++				flags = nla_get_u32(iter);
++				break;
++			case DEBUG_ATTRIBUTE_LOG_TIME_INTVAL:
++				time_intval = nla_get_u32(iter);
++				break;
++			case DEBUG_ATTRIBUTE_LOG_MIN_DATA_SIZE:
++				threshold = nla_get_u32(iter);
++				break;
++			default:
++				WL_ERR(("Unknown type: %d\n", type));
++				ret = BCME_BADADDR;
++				goto exit;
++		}
++	}
++
++	ret = dhd_os_start_logging(dhd_pub, ring_name, log_level, flags, time_intval, threshold);
++	if (ret < 0) {
++		WL_ERR(("start_logging is failed ret: %d\n", ret));
++	}
++exit:
++	return ret;
++}
++
++static int wl_cfgvendor_dbg_reset_logging(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = BCME_OK;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd_pub = cfg->pub;
++
++	ret = dhd_os_reset_logging(dhd_pub);
++	if (ret < 0) {
++		WL_ERR(("reset logging is failed ret: %d\n", ret));
++	}
++
++	return ret;
++}
++
++static int
++wl_cfgvendor_dbg_trigger_mem_dump(struct wiphy *wiphy,
++		struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = BCME_OK;
++	uint32 alloc_len;
++	struct sk_buff *skb;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++
++	dhdp->memdump_type = DUMP_TYPE_CFG_VENDOR_TRIGGERED;
++
++	ret = dhd_os_socram_dump(bcmcfg_to_prmry_ndev(cfg), &alloc_len);
++	if (ret) {
++		WL_ERR(("failed to call dhd_os_socram_dump : %d\n", ret));
++		goto exit;
++	}
++	/* Alloc the SKB for vendor_event */
++	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, 100);
++	if (!skb) {
++		WL_ERR(("skb allocation is failed\n"));
++		ret = BCME_NOMEM;
++		goto exit;
++	}
++	nla_put_u32(skb, DEBUG_ATTRIBUTE_FW_DUMP_LEN, alloc_len);
++
++	ret = cfg80211_vendor_cmd_reply(skb);
++
++	if (ret) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", ret));
++	}
++
++exit:
++	return ret;
++}
++
++static int
++wl_cfgvendor_dbg_get_mem_dump(struct wiphy *wiphy,
++		struct wireless_dev *wdev, const void *data, int len)
++{
++	int ret = BCME_OK, rem, type;
++	int buf_len = 0;
++	uintptr_t user_buf = (uintptr_t)NULL;
++	const struct nlattr *iter;
++	char *mem_buf = NULL;
++	struct sk_buff *skb;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case DEBUG_ATTRIBUTE_FW_DUMP_LEN:
++				/* Check if the iter is valid and
++				 * buffer length is not already initialized.
++				 */
++				if ((nla_len(iter) == sizeof(uint32)) &&
++					!buf_len) {
++					buf_len = nla_get_u32(iter);
++				} else {
++					ret = BCME_ERROR;
++					goto exit;
++				}
++				break;
++			case DEBUG_ATTRIBUTE_FW_DUMP_DATA:
++				if (nla_len(iter) != sizeof(uint64)) {
++					WL_ERR(("Invalid len\n"));
++					ret = BCME_ERROR;
++					goto exit;
++				}
++				user_buf = (uintptr_t)nla_get_u64(iter);
++				break;
++			default:
++				WL_ERR(("Unknown type: %d\n", type));
++				ret = BCME_ERROR;
++				goto exit;
++		}
++	}
++	if (buf_len > 0 && user_buf) {
++		mem_buf = vmalloc(buf_len);
++		if (!mem_buf) {
++			WL_ERR(("failed to allocate mem_buf with size : %d\n", buf_len));
++			ret = BCME_NOMEM;
++			goto exit;
++		}
++		ret = dhd_os_get_socram_dump(bcmcfg_to_prmry_ndev(cfg), &mem_buf, &buf_len);
++		if (ret) {
++			WL_ERR(("failed to get_socram_dump : %d\n", ret));
++			goto free_mem;
++		}
++#ifdef CONFIG_COMPAT
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 6, 0))
++		if (in_compat_syscall())
++#else
++		if (is_compat_task())
++#endif
++		{
++			void * usr_ptr =  compat_ptr((uintptr_t) user_buf);
++			ret = copy_to_user(usr_ptr, mem_buf, buf_len);
++			if (ret) {
++				WL_ERR(("failed to copy memdump into user buffer : %d\n", ret));
++				goto free_mem;
++			}
++		}
++		else
++#endif /* CONFIG_COMPAT */
++		{
++			ret = copy_to_user((void*)user_buf, mem_buf, buf_len);
++			if (ret) {
++				WL_ERR(("failed to copy memdump into user buffer : %d\n", ret));
++				goto free_mem;
++			}
++		}
++		/* Alloc the SKB for vendor_event */
++		skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, 100);
++		if (!skb) {
++			WL_ERR(("skb allocation is failed\n"));
++			ret = BCME_NOMEM;
++			goto free_mem;
++		}
++		/* Indicate the memdump is succesfully copied */
++		nla_put(skb, DEBUG_ATTRIBUTE_FW_DUMP_DATA, sizeof(ret), &ret);
++
++		ret = cfg80211_vendor_cmd_reply(skb);
++
++		if (ret) {
++			WL_ERR(("Vendor Command reply failed ret:%d \n", ret));
++		}
++	}
++
++free_mem:
++	vfree(mem_buf);
++exit:
++	return ret;
++}
++
++static int wl_cfgvendor_dbg_get_version(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void *data, int len)
++{
++	int ret = BCME_OK, rem, type;
++	int buf_len = 1024;
++	bool dhd_ver = FALSE;
++	char *buf_ptr;
++	const struct nlattr *iter;
++	gfp_t kflags;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	buf_ptr = kzalloc(buf_len, kflags);
++	if (!buf_ptr) {
++		WL_ERR(("failed to allocate the buffer for version n"));
++		ret = BCME_NOMEM;
++		goto exit;
++	}
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case DEBUG_ATTRIBUTE_GET_DRIVER:
++				dhd_ver = TRUE;
++				break;
++			case DEBUG_ATTRIBUTE_GET_FW:
++				dhd_ver = FALSE;
++				break;
++			default:
++				WL_ERR(("Unknown type: %d\n", type));
++				ret = BCME_ERROR;
++				goto exit;
++		}
++	}
++	ret = dhd_os_get_version(bcmcfg_to_prmry_ndev(cfg), dhd_ver, &buf_ptr, buf_len);
++	if (ret < 0) {
++		WL_ERR(("failed to get the version %d\n", ret));
++		goto exit;
++	}
++	ret = wl_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++	        buf_ptr, strlen(buf_ptr));
++exit:
++	kfree(buf_ptr);
++	return ret;
++}
++
++static int wl_cfgvendor_dbg_get_ring_status(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = BCME_OK;
++	int ring_id, i;
++	int ring_cnt;
++	struct sk_buff *skb;
++	dhd_dbg_ring_status_t dbg_ring_status[DEBUG_RING_ID_MAX];
++	dhd_dbg_ring_status_t ring_status;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd_pub = cfg->pub;
++	memset(dbg_ring_status, 0, DBG_RING_STATUS_SIZE * DEBUG_RING_ID_MAX);
++	ring_cnt = 0;
++	for (ring_id = DEBUG_RING_ID_INVALID + 1; ring_id < DEBUG_RING_ID_MAX; ring_id++) {
++		ret = dhd_os_get_ring_status(dhd_pub, ring_id, &ring_status);
++		if (ret == BCME_NOTFOUND) {
++			WL_DBG(("The ring (%d) is not found \n", ring_id));
++		} else if (ret == BCME_OK) {
++			dbg_ring_status[ring_cnt++] = ring_status;
++		}
++	}
++	/* Alloc the SKB for vendor_event */
++	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy,
++		(DBG_RING_STATUS_SIZE * ring_cnt) + 100);
++	if (!skb) {
++		WL_ERR(("skb allocation is failed\n"));
++		ret = BCME_NOMEM;
++		goto exit;
++	}
++
++	nla_put_u32(skb, DEBUG_ATTRIBUTE_RING_NUM, ring_cnt);
++	for (i = 0; i < ring_cnt; i++) {
++		nla_put(skb, DEBUG_ATTRIBUTE_RING_STATUS, DBG_RING_STATUS_SIZE,
++				&dbg_ring_status[i]);
++	}
++	ret = cfg80211_vendor_cmd_reply(skb);
++
++	if (ret) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", ret));
++	}
++exit:
++	return ret;
++}
++
++static int wl_cfgvendor_dbg_get_ring_data(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = BCME_OK, rem, type;
++	char ring_name[DBGRING_NAME_MAX] = {0};
++	const struct nlattr *iter;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd_pub = cfg->pub;
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case DEBUG_ATTRIBUTE_RING_NAME:
++				strncpy(ring_name, nla_data(iter),
++					MIN(sizeof(ring_name) -1, nla_len(iter)));
++				break;
++			default:
++				WL_ERR(("Unknown type: %d\n", type));
++				return ret;
++		}
++	}
++
++	ret = dhd_os_trigger_get_ring_data(dhd_pub, ring_name);
++	if (ret < 0) {
++		WL_ERR(("trigger_get_data failed ret:%d\n", ret));
++	}
++
++	return ret;
++}
++
++static int wl_cfgvendor_dbg_get_feature(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = BCME_OK;
++	u32 supported_features = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd_pub = cfg->pub;
++
++	ret = dhd_os_dbg_get_feature(dhd_pub, &supported_features);
++	if (ret < 0) {
++		WL_ERR(("dbg_get_feature failed ret:%d\n", ret));
++		goto exit;
++	}
++	ret = wl_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++	        &supported_features, sizeof(supported_features));
++	if (ret < 0) {
++		WL_ERR(("wl_cfgvendor_send_cmd_reply failed ret:%d\n", ret));
++		goto exit;
++	}
++exit:
++	return ret;
++}
++
++static void wl_cfgvendor_dbg_ring_send_evt(void *ctx,
++	const int ring_id, const void *data, const uint32 len,
++	const dhd_dbg_ring_status_t ring_status)
++{
++	struct net_device *ndev = ctx;
++	struct wiphy *wiphy;
++	gfp_t kflags;
++	struct sk_buff *skb;
++	if (!ndev) {
++		WL_ERR(("ndev is NULL\n"));
++		return;
++	}
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	wiphy = ndev->ieee80211_ptr->wiphy;
++	/* Alloc the SKB for vendor_event */
++#if (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || \
++	LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
++	skb = cfg80211_vendor_event_alloc(wiphy, NULL, len + 100,
++			GOOGLE_DEBUG_RING_EVENT, kflags);
++#else
++	skb = cfg80211_vendor_event_alloc(wiphy, len + 100,
++			GOOGLE_DEBUG_RING_EVENT, kflags);
++#endif /* (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || */
++		/* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) */
++	if (!skb) {
++		WL_ERR(("skb alloc failed"));
++		return;
++	}
++	nla_put(skb, DEBUG_ATTRIBUTE_RING_STATUS, sizeof(ring_status), &ring_status);
++	nla_put(skb, DEBUG_ATTRIBUTE_RING_DATA, len, data);
++	cfg80211_vendor_event(skb, kflags);
++}
++
++static void wl_cfgvendor_dbg_send_urgent_evt(void *ctx, const void *data,
++	const uint32 len, const uint32 fw_len)
++{
++	struct net_device *ndev = ctx;
++	struct wiphy *wiphy;
++	gfp_t kflags;
++	struct sk_buff *skb;
++	if (!ndev) {
++		WL_ERR(("ndev is NULL\n"));
++		return;
++	}
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	wiphy = ndev->ieee80211_ptr->wiphy;
++	/* Alloc the SKB for vendor_event */
++#if (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || \
++	LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
++	skb = cfg80211_vendor_event_alloc(wiphy, NULL, len + 100,
++			GOOGLE_FW_DUMP_EVENT, kflags);
++#else
++	skb = cfg80211_vendor_event_alloc(wiphy, len + 100,
++			GOOGLE_FW_DUMP_EVENT, kflags);
++#endif /* (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || */
++		/* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) */
++	if (!skb) {
++		WL_ERR(("skb alloc failed"));
++		return;
++	}
++	nla_put_u32(skb, DEBUG_ATTRIBUTE_FW_DUMP_LEN, fw_len);
++	nla_put(skb, DEBUG_ATTRIBUTE_RING_DATA, len, data);
++	cfg80211_vendor_event(skb, kflags);
++}
++#endif /* DEBUGABILITY */
++
++#ifdef DBG_PKT_MON
++static int wl_cfgvendor_dbg_start_pkt_fate_monitoring(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void *data, int len)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd_pub = cfg->pub;
++	int ret;
++
++	ret = dhd_os_dbg_attach_pkt_monitor(dhd_pub);
++	if (unlikely(ret)) {
++		WL_ERR(("failed to start pkt fate monitoring, ret=%d", ret));
++	}
++
++	return ret;
++}
++
++typedef int (*dbg_mon_get_pkts_t) (dhd_pub_t *dhdp, void __user *user_buf,
++	uint16 req_count, uint16 *resp_count);
++
++static int __wl_cfgvendor_dbg_get_pkt_fates(struct wiphy *wiphy,
++	const void *data, int len, dbg_mon_get_pkts_t dbg_mon_get_pkts)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd_pub = cfg->pub;
++	struct sk_buff *skb = NULL;
++	const struct nlattr *iter;
++	void __user *user_buf = NULL;
++	uint16 req_count = 0, resp_count = 0;
++	int ret, tmp, type, mem_needed;
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++		switch (type) {
++			case DEBUG_ATTRIBUTE_PKT_FATE_NUM:
++				req_count = nla_get_u32(iter);
++				break;
++			case DEBUG_ATTRIBUTE_PKT_FATE_DATA:
++				user_buf = (void __user *)(unsigned long) nla_get_u64(iter);
++				break;
++			default:
++				WL_ERR(("%s: no such attribute %d\n", __FUNCTION__, type));
++				ret = -EINVAL;
++				goto exit;
++		}
++	}
++
++	if (!req_count || !user_buf) {
++		WL_ERR(("%s: invalid request, user_buf=%p, req_count=%u\n",
++			__FUNCTION__, user_buf, req_count));
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	ret = dbg_mon_get_pkts(dhd_pub, user_buf, req_count, &resp_count);
++	if (unlikely(ret)) {
++		WL_ERR(("failed to get packets, ret:%d \n", ret));
++		goto exit;
++	}
++
++	mem_needed = VENDOR_REPLY_OVERHEAD + ATTRIBUTE_U32_LEN;
++	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		WL_ERR(("skb alloc failed"));
++		ret = -ENOMEM;
++		goto exit;
++	}
++
++	nla_put_u32(skb, DEBUG_ATTRIBUTE_PKT_FATE_NUM, resp_count);
++
++	ret = cfg80211_vendor_cmd_reply(skb);
++	if (unlikely(ret)) {
++		WL_ERR(("vendor Command reply failed ret:%d \n", ret));
++	}
++
++exit:
++	return ret;
++}
++
++static int wl_cfgvendor_dbg_get_tx_pkt_fates(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret;
++
++	ret = __wl_cfgvendor_dbg_get_pkt_fates(wiphy, data, len,
++			dhd_os_dbg_monitor_get_tx_pkts);
++	if (unlikely(ret)) {
++		WL_ERR(("failed to get tx packets, ret:%d \n", ret));
++	}
++
++	return ret;
++}
++
++static int wl_cfgvendor_dbg_get_rx_pkt_fates(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret;
++
++	ret = __wl_cfgvendor_dbg_get_pkt_fates(wiphy, data, len,
++			dhd_os_dbg_monitor_get_rx_pkts);
++	if (unlikely(ret)) {
++		WL_ERR(("failed to get rx packets, ret:%d \n", ret));
++	}
++
++	return ret;
++}
++#endif /* DBG_PKT_MON */
++
++#ifdef KEEP_ALIVE
++static int wl_cfgvendor_start_mkeep_alive(struct wiphy *wiphy, struct wireless_dev *wdev,
++	const void *data, int len)
++{
++	/* max size of IP packet for keep alive */
++	const int MKEEP_ALIVE_IP_PKT_MAX = 256;
++
++	int ret = BCME_OK, rem, type;
++	uint8 mkeep_alive_id = 0;
++	uint8 *ip_pkt = NULL;
++	uint16 ip_pkt_len = 0;
++	uint8 src_mac[ETHER_ADDR_LEN];
++	uint8 dst_mac[ETHER_ADDR_LEN];
++	uint32 period_msec = 0;
++	const struct nlattr *iter;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd_pub = cfg->pub;
++	gfp_t kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case MKEEP_ALIVE_ATTRIBUTE_ID:
++				mkeep_alive_id = nla_get_u8(iter);
++				break;
++			case MKEEP_ALIVE_ATTRIBUTE_IP_PKT_LEN:
++				ip_pkt_len = nla_get_u16(iter);
++				if (ip_pkt_len > MKEEP_ALIVE_IP_PKT_MAX) {
++					ret = BCME_BADARG;
++					goto exit;
++				}
++				break;
++			case MKEEP_ALIVE_ATTRIBUTE_IP_PKT:
++				if (!ip_pkt_len) {
++					ret = BCME_BADARG;
++					WL_ERR(("ip packet length is 0\n"));
++					goto exit;
++				}
++				ip_pkt = (u8 *)kzalloc(ip_pkt_len, kflags);
++				if (ip_pkt == NULL) {
++					ret = BCME_NOMEM;
++					WL_ERR(("Failed to allocate mem for ip packet\n"));
++					goto exit;
++				}
++				memcpy(ip_pkt, (u8*)nla_data(iter), ip_pkt_len);
++				break;
++			case MKEEP_ALIVE_ATTRIBUTE_SRC_MAC_ADDR:
++				memcpy(src_mac, nla_data(iter), ETHER_ADDR_LEN);
++				break;
++			case MKEEP_ALIVE_ATTRIBUTE_DST_MAC_ADDR:
++				memcpy(dst_mac, nla_data(iter), ETHER_ADDR_LEN);
++				break;
++			case MKEEP_ALIVE_ATTRIBUTE_PERIOD_MSEC:
++				period_msec = nla_get_u32(iter);
++				break;
++			default:
++				WL_ERR(("Unknown type: %d\n", type));
++				ret = BCME_BADARG;
++				goto exit;
++		}
++	}
++
++	if (ip_pkt == NULL) {
++		ret = BCME_BADARG;
++		WL_ERR(("ip packet is NULL\n"));
++		goto exit;
++	}
++
++	ret = dhd_dev_start_mkeep_alive(dhd_pub, mkeep_alive_id, ip_pkt, ip_pkt_len, src_mac,
++		dst_mac, period_msec);
++	if (ret < 0) {
++		WL_ERR(("start_mkeep_alive is failed ret: %d\n", ret));
++	}
++
++exit:
++	if (ip_pkt) {
++		kfree(ip_pkt);
++	}
++
++	return ret;
++}
++
++static int wl_cfgvendor_stop_mkeep_alive(struct wiphy *wiphy, struct wireless_dev *wdev,
++	const void *data, int len)
++{
++	int ret = BCME_OK, rem, type;
++	uint8 mkeep_alive_id = 0;
++	const struct nlattr *iter;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd_pub = cfg->pub;
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case MKEEP_ALIVE_ATTRIBUTE_ID:
++				mkeep_alive_id = nla_get_u8(iter);
++				break;
++			default:
++				WL_ERR(("Unknown type: %d\n", type));
++				ret = BCME_BADARG;
++				break;
++		}
++	}
++
++	ret = dhd_dev_stop_mkeep_alive(dhd_pub, mkeep_alive_id);
++	if (ret < 0) {
++		WL_ERR(("stop_mkeep_alive is failed ret: %d\n", ret));
++	}
++
++	return ret;
++}
++#endif /* KEEP_ALIVE */
++
++#if defined(PKT_FILTER_SUPPORT) && defined(APF)
++static int
++wl_cfgvendor_apf_get_capabilities(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void *data, int len)
++{
++	struct net_device *ndev = wdev_to_ndev(wdev);
++	struct sk_buff *skb;
++	int ret, ver, max_len, mem_needed;
++
++	/* APF version */
++	ver = 0;
++	ret = dhd_dev_apf_get_version(ndev, &ver);
++	if (unlikely(ret)) {
++		WL_ERR(("APF get version failed, ret=%d\n", ret));
++		return ret;
++	}
++
++	/* APF memory size limit */
++	max_len = 0;
++	ret = dhd_dev_apf_get_max_len(ndev, &max_len);
++	if (unlikely(ret)) {
++		WL_ERR(("APF get maximum length failed, ret=%d\n", ret));
++		return ret;
++	}
++
++	mem_needed = VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * 2);
++
++	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		WL_ERR(("%s: can't allocate %d bytes\n", __FUNCTION__, mem_needed));
++		return -ENOMEM;
++	}
++
++	nla_put_u32(skb, APF_ATTRIBUTE_VERSION, ver);
++	nla_put_u32(skb, APF_ATTRIBUTE_MAX_LEN, max_len);
++
++	ret = cfg80211_vendor_cmd_reply(skb);
++	if (unlikely(ret)) {
++		WL_ERR(("vendor command reply failed, ret=%d\n", ret));
++	}
++
++	return ret;
++}
++
++static int
++wl_cfgvendor_apf_set_filter(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	struct net_device *ndev = wdev_to_ndev(wdev);
++	const struct nlattr *iter;
++	u8 *program = NULL;
++	u32 program_len = 0;
++	int ret, tmp, type;
++	gfp_t kflags;
++
++	if (len <= 0) {
++		WL_ERR(("Invalid len: %d\n", len));
++		ret = -EINVAL;
++		goto exit;
++	}
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++		switch (type) {
++			case APF_ATTRIBUTE_PROGRAM_LEN:
++				/* check if the iter value is valid and program_len
++				 * is not already initialized.
++				 */
++				if (nla_len(iter) == sizeof(uint32) && !program_len) {
++					program_len = nla_get_u32(iter);
++				} else {
++					ret = -EINVAL;
++					goto exit;
++				}
++
++				if (program_len > WL_APF_PROGRAM_MAX_SIZE) {
++					WL_ERR(("program len is more than expected len\n"));
++					ret = -EINVAL;
++					goto exit;
++				}
++
++				if (unlikely(!program_len)) {
++					WL_ERR(("zero program length\n"));
++					ret = -EINVAL;
++					goto exit;
++				}
++				break;
++			case APF_ATTRIBUTE_PROGRAM:
++				if (unlikely(!program_len)) {
++					WL_ERR(("program len is not set\n"));
++					ret = -EINVAL;
++					goto exit;
++				}
++				kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++				program = kzalloc(program_len, kflags);
++				if (unlikely(!program)) {
++					WL_ERR(("%s: can't allocate %d bytes\n",
++					      __FUNCTION__, program_len));
++					ret = -ENOMEM;
++					goto exit;
++				}
++				memcpy(program, (u8*)nla_data(iter), program_len);
++				break;
++			default:
++				WL_ERR(("%s: no such attribute %d\n", __FUNCTION__, type));
++				ret = -EINVAL;
++				goto exit;
++		}
++	}
++
++	ret = dhd_dev_apf_add_filter(ndev, program, program_len);
++
++exit:
++	if (program) {
++		kfree(program);
++	}
++	return ret;
++}
++#endif /* PKT_FILTER_SUPPORT && APF */
++
++#ifdef NDO_CONFIG_SUPPORT
++static int wl_cfgvendor_configure_nd_offload(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	const struct nlattr *iter;
++	int ret = BCME_OK, rem, type;
++	u8 enable = 0;
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case ANDR_WIFI_ATTRIBUTE_ND_OFFLOAD_VALUE:
++				enable = nla_get_u8(iter);
++				break;
++			default:
++				WL_ERR(("Unknown type: %d\n", type));
++				ret = BCME_BADARG;
++				goto exit;
++		}
++	}
++
++	ret = dhd_dev_ndo_cfg(bcmcfg_to_prmry_ndev(cfg), enable);
++	if (ret < 0) {
++		WL_ERR(("dhd_dev_ndo_cfg() failed: %d\n", ret));
++	}
++
++exit:
++	return ret;
++}
++#endif /* NDO_CONFIG_SUPPORT */
++
++static const struct wiphy_vendor_command wl_vendor_cmds [] = {
++	{
++		{
++			.vendor_id = OUI_BRCM,
++			.subcmd = BRCM_VENDOR_SCMD_PRIV_STR
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_priv_string_handler
++	},
++	{
++		{
++			.vendor_id = OUI_BRCM,
++			.subcmd = BRCM_VENDOR_SCMD_BCM_STR
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_priv_bcm_handler
++	},
++#ifdef WL_SAE
++	{
++		{
++			.vendor_id = OUI_BRCM,
++			.subcmd = BRCM_VENDOR_SCMD_BCM_PSK
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_sae_password
++	},
++#endif /* WL_SAE */
++#ifdef GSCAN_SUPPORT
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_GET_CAPABILITIES
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_gscan_get_capabilities
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_SET_CONFIG
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_scan_cfg
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_batch_scan_cfg
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_ENABLE_GSCAN
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_initiate_gscan
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_enable_full_scan_result
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_SET_HOTLIST
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_hotlist_cfg
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_gscan_get_batch_results
++	},
++#endif /* GSCAN_SUPPORT */
++#if defined(GSCAN_SUPPORT) || defined(DHD_GET_VALID_CHANNELS)
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_gscan_get_channel_list
++	},
++#endif /* GSCAN_SUPPORT || DHD_GET_VALID_CHANNELS */
++#ifdef RTT_SUPPORT
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = RTT_SUBCMD_SET_CONFIG
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_rtt_set_config
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = RTT_SUBCMD_CANCEL_CONFIG
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_rtt_cancel_config
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = RTT_SUBCMD_GETCAPABILITY
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_rtt_get_capability
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = RTT_SUBCMD_GETAVAILCHANNEL
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_rtt_get_responder_info
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = RTT_SUBCMD_SET_RESPONDER
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_rtt_set_responder
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = RTT_SUBCMD_CANCEL_RESPONDER
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_rtt_cancel_responder
++	},
++#endif /* RTT_SUPPORT */
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_get_feature_set
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_get_feature_set_matrix
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = ANDR_WIFI_RANDOM_MAC_OUI
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_rand_mac_oui
++	},
++#ifdef CUSTOM_FORCE_NODFS_FLAG
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = ANDR_WIFI_NODFS_CHANNELS
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_nodfs_flag
++	},
++#endif /* CUSTOM_FORCE_NODFS_FLAG */
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = ANDR_WIFI_SET_COUNTRY
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_country
++	},
++#ifdef LINKSTAT_SUPPORT
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = LSTATS_SUBCMD_GET_INFO
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_lstats_get_info
++	},
++#endif /* LINKSTAT_SUPPORT */
++
++#ifdef GSCAN_SUPPORT
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_SET_EPNO_SSID
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_epno_cfg
++
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_SET_SSID_WHITELIST
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_ssid_whitelist
++
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_SET_LAZY_ROAM_PARAMS
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_lazy_roam_cfg
++
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_ENABLE_LAZY_ROAM
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_enable_lazy_roam
++
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_SET_BSSID_PREF
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_bssid_pref
++
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_SET_BSSID_BLACKLIST
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_bssid_blacklist
++	},
++#endif /* GSCAN_SUPPORT */
++#ifdef DEBUGABILITY
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_START_LOGGING
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_start_logging
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_RESET_LOGGING
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_reset_logging
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_TRIGGER_MEM_DUMP
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_trigger_mem_dump
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_GET_MEM_DUMP
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_get_mem_dump
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_GET_VER
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_get_version
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_GET_RING_STATUS
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_get_ring_status
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_GET_RING_DATA
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_get_ring_data
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_GET_FEATURE
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_get_feature
++	},
++#endif /* DEBUGABILITY */
++#ifdef DBG_PKT_MON
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_START_PKT_FATE_MONITORING
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_start_pkt_fate_monitoring
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_GET_TX_PKT_FATES
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_get_tx_pkt_fates
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_GET_RX_PKT_FATES
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_get_rx_pkt_fates
++	},
++#endif /* DBG_PKT_MON */
++#ifdef KEEP_ALIVE
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_OFFLOAD_SUBCMD_START_MKEEP_ALIVE
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_start_mkeep_alive
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_OFFLOAD_SUBCMD_STOP_MKEEP_ALIVE
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_stop_mkeep_alive
++	},
++#endif /* KEEP_ALIVE */
++#if defined(PKT_FILTER_SUPPORT) && defined(APF)
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = APF_SUBCMD_GET_CAPABILITIES
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_apf_get_capabilities
++	},
++
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = APF_SUBCMD_SET_FILTER
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_apf_set_filter
++	},
++#endif /* PKT_FILTER_SUPPORT && APF */
++#ifdef NDO_CONFIG_SUPPORT
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_CONFIG_ND_OFFLOAD
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_configure_nd_offload
++	},
++#endif /* NDO_CONFIG_SUPPORT */
++#ifdef RSSI_MONITOR_SUPPORT
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_SET_RSSI_MONITOR
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_rssi_monitor
++	},
++#endif /* RSSI_MONITOR_SUPPORT */
++#ifdef DHDTCPACK_SUPPRESS
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_CONFIG_TCPACK_SUP
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_tcpack_sup_mode
++	},
++#endif /* DHDTCPACK_SUPPRESS */
++#ifdef DHD_WAKE_STATUS
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_GET_WAKE_REASON_STATS
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_get_wake_reason_stats
++	}
++#endif /* DHD_WAKE_STATUS */
++};
++
++static const struct  nl80211_vendor_cmd_info wl_vendor_events [] = {
++		{ OUI_BRCM, BRCM_VENDOR_EVENT_UNSPEC },
++		{ OUI_BRCM, BRCM_VENDOR_EVENT_PRIV_STR },
++		{ OUI_GOOGLE, GOOGLE_GSCAN_SIGNIFICANT_EVENT },
++		{ OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT },
++		{ OUI_GOOGLE, GOOGLE_GSCAN_BATCH_SCAN_EVENT },
++		{ OUI_GOOGLE, GOOGLE_SCAN_FULL_RESULTS_EVENT },
++		{ OUI_GOOGLE, GOOGLE_RTT_COMPLETE_EVENT },
++		{ OUI_GOOGLE, GOOGLE_SCAN_COMPLETE_EVENT },
++		{ OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_LOST_EVENT },
++		{ OUI_GOOGLE, GOOGLE_SCAN_EPNO_EVENT },
++		{ OUI_GOOGLE, GOOGLE_DEBUG_RING_EVENT },
++		{ OUI_GOOGLE, GOOGLE_FW_DUMP_EVENT },
++		{ OUI_GOOGLE, GOOGLE_PNO_HOTSPOT_FOUND_EVENT },
++		{ OUI_GOOGLE, GOOGLE_RSSI_MONITOR_EVENT },
++		{ OUI_GOOGLE, GOOGLE_MKEEP_ALIVE_EVENT },
++		{ OUI_GOOGLE, GOOGLE_NAN_EVENT_ENABLED},
++		{ OUI_GOOGLE, GOOGLE_NAN_EVENT_DISABLED},
++		{ OUI_GOOGLE, GOOGLE_NAN_EVENT_SUBSCRIBE_MATCH},
++		{ OUI_GOOGLE, GOOGLE_NAN_EVENT_REPLIED},
++		{ OUI_GOOGLE, GOOGLE_NAN_EVENT_PUBLISH_TERMINATED},
++		{ OUI_GOOGLE, GOOGLE_NAN_EVENT_SUBSCRIBE_TERMINATED},
++		{ OUI_GOOGLE, GOOGLE_NAN_EVENT_DE_EVENT},
++		{ OUI_GOOGLE, GOOGLE_NAN_EVENT_FOLLOWUP},
++		{ OUI_GOOGLE, GOOGLE_NAN_EVENT_TRANSMIT_FOLLOWUP_IND},
++		{ OUI_GOOGLE, GOOGLE_NAN_EVENT_DATA_REQUEST},
++		{ OUI_GOOGLE, GOOGLE_NAN_EVENT_DATA_CONFIRMATION},
++		{ OUI_GOOGLE, GOOGLE_NAN_EVENT_DATA_END},
++		{ OUI_GOOGLE, GOOGLE_NAN_EVENT_BEACON},
++		{ OUI_GOOGLE, GOOGLE_NAN_EVENT_SDF},
++		{ OUI_GOOGLE, GOOGLE_NAN_EVENT_TCA},
++		{ OUI_GOOGLE, GOOGLE_NAN_EVENT_SUBSCRIBE_UNMATCH},
++		{ OUI_GOOGLE, GOOGLE_NAN_EVENT_UNKNOWN},
++		{ OUI_GOOGLE, GOOGLE_ROAM_EVENT_START},
++		{ OUI_BRCM, BRCM_VENDOR_EVENT_HANGED},
++		{ OUI_BRCM, BRCM_VENDOR_EVENT_SAE_KEY},
++		{ OUI_BRCM, BRCM_VENDOR_EVENT_BEACON_RECV},
++		{ OUI_BRCM, BRCM_VENDOR_EVENT_PORT_AUTHORIZED},
++		{ OUI_GOOGLE, GOOGLE_FILE_DUMP_EVENT },
++		{ OUI_BRCM, BRCM_VENDOR_EVENT_CU},
++		{ OUI_BRCM, BRCM_VENDOR_EVENT_WIPS},
++		{ OUI_GOOGLE, NAN_ASYNC_RESPONSE_DISABLED}
++};
++
++int wl_cfgvendor_attach(struct wiphy *wiphy, dhd_pub_t *dhd)
++{
++
++	WL_INFORM(("Vendor: Register BRCM cfg80211 vendor cmd(0x%x) interface \n",
++		NL80211_CMD_VENDOR));
++
++	wiphy->vendor_commands	= wl_vendor_cmds;
++	wiphy->n_vendor_commands = ARRAY_SIZE(wl_vendor_cmds);
++	wiphy->vendor_events	= wl_vendor_events;
++	wiphy->n_vendor_events	= ARRAY_SIZE(wl_vendor_events);
++
++#ifdef DEBUGABILITY
++	dhd_os_dbg_register_callback(FW_VERBOSE_RING_ID, wl_cfgvendor_dbg_ring_send_evt);
++	dhd_os_dbg_register_callback(FW_EVENT_RING_ID, wl_cfgvendor_dbg_ring_send_evt);
++	dhd_os_dbg_register_callback(DHD_EVENT_RING_ID, wl_cfgvendor_dbg_ring_send_evt);
++	dhd_os_dbg_register_callback(NAN_EVENT_RING_ID, wl_cfgvendor_dbg_ring_send_evt);
++	dhd_os_dbg_register_urgent_notifier(dhd, wl_cfgvendor_dbg_send_urgent_evt);
++#endif /* DEBUGABILITY */
++
++	return 0;
++}
++
++int wl_cfgvendor_detach(struct wiphy *wiphy)
++{
++	WL_INFORM(("Vendor: Unregister BRCM cfg80211 vendor interface \n"));
++
++	wiphy->vendor_commands  = NULL;
++	wiphy->vendor_events    = NULL;
++	wiphy->n_vendor_commands = 0;
++	wiphy->n_vendor_events  = 0;
++
++	return 0;
++}
++#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(3, 13, 0)) || defined(WL_VENDOR_EXT_SUPPORT) */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgvendor.h b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgvendor.h
+new file mode 100644
+index 000000000..fa7dd523a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_cfgvendor.h
+@@ -0,0 +1,583 @@
++/*
++ * Linux cfg80211 Vendor Extension Code
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfgvendor.h 698895 2017-05-11 02:55:17Z $
++ */
++
++
++#ifndef _wl_cfgvendor_h_
++#define _wl_cfgvendor_h_
++#if ((LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) || \
++	defined(CONFIG_BCMDHD_VENDOR_EXT)) && !defined(WL_VENDOR_EXT_SUPPORT)
++/* defined CONFIG_BCMDHD_VENDOR_EXT in brix kernel to enable GSCAN testing */
++#define WL_VENDOR_EXT_SUPPORT
++#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0) && CONFIG_BCMDHD_VENDOR_EXT */
++
++#define OUI_BRCM    0x001018
++#define OUI_GOOGLE  0x001A11
++#define BRCM_VENDOR_SUBCMD_PRIV_STR	1
++#define ATTRIBUTE_U32_LEN                  (NLA_HDRLEN  + 4)
++#define VENDOR_ID_OVERHEAD                 ATTRIBUTE_U32_LEN
++#define VENDOR_SUBCMD_OVERHEAD             ATTRIBUTE_U32_LEN
++#define VENDOR_DATA_OVERHEAD               (NLA_HDRLEN)
++
++enum brcm_vendor_attr {
++	BRCM_ATTR_DRIVER_CMD,
++	BRCM_ATTR_DRIVER_MAX
++};
++
++#define SCAN_RESULTS_COMPLETE_FLAG_LEN       ATTRIBUTE_U32_LEN
++#define SCAN_INDEX_HDR_LEN                   (NLA_HDRLEN)
++#define SCAN_ID_HDR_LEN                      ATTRIBUTE_U32_LEN
++#define SCAN_FLAGS_HDR_LEN                   ATTRIBUTE_U32_LEN
++#define GSCAN_NUM_RESULTS_HDR_LEN            ATTRIBUTE_U32_LEN
++#define GSCAN_CH_BUCKET_MASK_HDR_LEN         ATTRIBUTE_U32_LEN
++#define GSCAN_RESULTS_HDR_LEN                (NLA_HDRLEN)
++#define GSCAN_BATCH_RESULT_HDR_LEN  (SCAN_INDEX_HDR_LEN + SCAN_ID_HDR_LEN + \
++									SCAN_FLAGS_HDR_LEN + \
++							        GSCAN_NUM_RESULTS_HDR_LEN + \
++								GSCAN_CH_BUCKET_MASK_HDR_LEN + \
++									GSCAN_RESULTS_HDR_LEN)
++
++#define VENDOR_REPLY_OVERHEAD       (VENDOR_ID_OVERHEAD + \
++									VENDOR_SUBCMD_OVERHEAD + \
++									VENDOR_DATA_OVERHEAD)
++
++#define GSCAN_ATTR_SET1				10
++#define GSCAN_ATTR_SET2				20
++#define GSCAN_ATTR_SET3				30
++#define GSCAN_ATTR_SET4				40
++#define GSCAN_ATTR_SET5				50
++#define GSCAN_ATTR_SET6				60
++#define GSCAN_ATTR_SET7				70
++#define GSCAN_ATTR_SET8				80
++#define GSCAN_ATTR_SET9				90
++#define GSCAN_ATTR_SET10			100
++#define GSCAN_ATTR_SET11			110
++#define GSCAN_ATTR_SET12			120
++#define GSCAN_ATTR_SET13			130
++
++
++typedef enum {
++	/* don't use 0 as a valid subcommand */
++	VENDOR_NL80211_SUBCMD_UNSPECIFIED,
++
++	/* define all vendor startup commands between 0x0 and 0x0FFF */
++	VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001,
++	VENDOR_NL80211_SUBCMD_RANGE_END   = 0x0FFF,
++
++	/* define all GScan related commands between 0x1000 and 0x10FF */
++	ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000,
++	ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END   = 0x10FF,
++
++	/* define all RTT related commands between 0x1100 and 0x11FF */
++	ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100,
++	ANDROID_NL80211_SUBCMD_RTT_RANGE_END   = 0x11FF,
++
++	ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200,
++	ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END   = 0x12FF,
++
++	ANDROID_NL80211_SUBCMD_TDLS_RANGE_START = 0x1300,
++	ANDROID_NL80211_SUBCMD_TDLS_RANGE_END	= 0x13FF,
++
++	ANDROID_NL80211_SUBCMD_DEBUG_RANGE_START = 0x1400,
++	ANDROID_NL80211_SUBCMD_DEBUG_RANGE_END	= 0x14FF,
++
++	/* define all NearbyDiscovery related commands between 0x1500 and 0x15FF */
++	ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1500,
++	ANDROID_NL80211_SUBCMD_NBD_RANGE_END   = 0x15FF,
++
++	/* define all wifi calling related commands between 0x1600 and 0x16FF */
++	ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_START = 0x1600,
++	ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_END   = 0x16FF,
++
++	/* define all NAN related commands between 0x1700 and 0x17FF */
++	ANDROID_NL80211_SUBCMD_NAN_RANGE_START = 0x1700,
++	ANDROID_NL80211_SUBCMD_NAN_RANGE_END   = 0x17FF,
++
++	/* define all packet filter related commands between 0x1800 and 0x18FF */
++	ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_START = 0x1800,
++	ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_END   = 0x18FF,
++
++	/* This is reserved for future usage */
++
++} ANDROID_VENDOR_SUB_COMMAND;
++
++enum andr_vendor_subcmd {
++	GSCAN_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START,
++	GSCAN_SUBCMD_SET_CONFIG,
++	GSCAN_SUBCMD_SET_SCAN_CONFIG,
++	GSCAN_SUBCMD_ENABLE_GSCAN,
++	GSCAN_SUBCMD_GET_SCAN_RESULTS,
++	GSCAN_SUBCMD_SCAN_RESULTS,
++	GSCAN_SUBCMD_SET_HOTLIST,
++	GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG,
++	GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS,
++	GSCAN_SUBCMD_GET_CHANNEL_LIST,
++	/* ANDR_WIFI_XXX although not related to gscan are defined here */
++	ANDR_WIFI_SUBCMD_GET_FEATURE_SET,
++	ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX,
++	ANDR_WIFI_RANDOM_MAC_OUI,
++	ANDR_WIFI_NODFS_CHANNELS,
++	ANDR_WIFI_SET_COUNTRY,
++	GSCAN_SUBCMD_SET_EPNO_SSID,
++	WIFI_SUBCMD_SET_SSID_WHITELIST,
++	WIFI_SUBCMD_SET_LAZY_ROAM_PARAMS,
++	WIFI_SUBCMD_ENABLE_LAZY_ROAM,
++	WIFI_SUBCMD_SET_BSSID_PREF,
++	WIFI_SUBCMD_SET_BSSID_BLACKLIST,
++	GSCAN_SUBCMD_ANQPO_CONFIG,
++	WIFI_SUBCMD_SET_RSSI_MONITOR,
++	WIFI_SUBCMD_CONFIG_ND_OFFLOAD,
++	WIFI_SUBCMD_CONFIG_TCPACK_SUP,
++	RTT_SUBCMD_SET_CONFIG = ANDROID_NL80211_SUBCMD_RTT_RANGE_START,
++	RTT_SUBCMD_CANCEL_CONFIG,
++	RTT_SUBCMD_GETCAPABILITY,
++	RTT_SUBCMD_GETAVAILCHANNEL,
++	RTT_SUBCMD_SET_RESPONDER,
++	RTT_SUBCMD_CANCEL_RESPONDER,
++	LSTATS_SUBCMD_GET_INFO = ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START,
++
++	DEBUG_START_LOGGING = ANDROID_NL80211_SUBCMD_DEBUG_RANGE_START,
++	DEBUG_TRIGGER_MEM_DUMP,
++	DEBUG_GET_MEM_DUMP,
++	DEBUG_GET_VER,
++	DEBUG_GET_RING_STATUS,
++	DEBUG_GET_RING_DATA,
++	DEBUG_GET_FEATURE,
++	DEBUG_RESET_LOGGING,
++
++	DEBUG_TRIGGER_DRIVER_MEM_DUMP,
++	DEBUG_GET_DRIVER_MEM_DUMP,
++	DEBUG_START_PKT_FATE_MONITORING,
++	DEBUG_GET_TX_PKT_FATES,
++	DEBUG_GET_RX_PKT_FATES,
++	DEBUG_GET_WAKE_REASON_STATS,
++
++	WIFI_OFFLOAD_SUBCMD_START_MKEEP_ALIVE = ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_START,
++	WIFI_OFFLOAD_SUBCMD_STOP_MKEEP_ALIVE,
++
++	NAN_WIFI_SUBCMD_ENABLE = ANDROID_NL80211_SUBCMD_NAN_RANGE_START,
++	NAN_WIFI_SUBCMD_DISABLE,
++	NAN_WIFI_SUBCMD_REQUEST_PUBLISH,
++	NAN_WIFI_SUBCMD_REQUEST_SUBSCRIBE,
++	NAN_WIFI_SUBCMD_CANCEL_PUBLISH,
++	NAN_WIFI_SUBCMD_CANCEL_SUBSCRIBE,
++	NAN_WIFI_SUBCMD_TRANSMIT,
++#ifdef NAN_DP
++	NAN_WIFI_SUBCMD_DATA_PATH_OPEN,
++	NAN_WIFI_SUBCMD_DATA_PATH_CLOSE,
++#endif /* NAN_DP */
++	APF_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_START,
++	APF_SUBCMD_SET_FILTER,
++	/* Add more sub commands here */
++	VENDOR_SUBCMD_MAX
++};
++
++enum gscan_attributes {
++    GSCAN_ATTRIBUTE_NUM_BUCKETS = GSCAN_ATTR_SET1,
++    GSCAN_ATTRIBUTE_BASE_PERIOD,
++    GSCAN_ATTRIBUTE_BUCKETS_BAND,
++    GSCAN_ATTRIBUTE_BUCKET_ID,
++    GSCAN_ATTRIBUTE_BUCKET_PERIOD,
++    GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS,
++    GSCAN_ATTRIBUTE_BUCKET_CHANNELS,
++    GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN,
++    GSCAN_ATTRIBUTE_REPORT_THRESHOLD,
++    GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE,
++    GSCAN_ATTRIBUTE_BAND = GSCAN_ATTRIBUTE_BUCKETS_BAND,
++
++    GSCAN_ATTRIBUTE_ENABLE_FEATURE = GSCAN_ATTR_SET2,
++    GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE,
++    GSCAN_ATTRIBUTE_FLUSH_FEATURE,
++    GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS,
++    GSCAN_ATTRIBUTE_REPORT_EVENTS,
++    /* remaining reserved for additional attributes */
++    GSCAN_ATTRIBUTE_NUM_OF_RESULTS = GSCAN_ATTR_SET3,
++    GSCAN_ATTRIBUTE_FLUSH_RESULTS,
++    GSCAN_ATTRIBUTE_SCAN_RESULTS,                       /* flat array of wifi_scan_result */
++    GSCAN_ATTRIBUTE_SCAN_ID,                            /* indicates scan number */
++    GSCAN_ATTRIBUTE_SCAN_FLAGS,                         /* indicates if scan was aborted */
++    GSCAN_ATTRIBUTE_AP_FLAGS,                           /* flags on significant change event */
++    GSCAN_ATTRIBUTE_NUM_CHANNELS,
++    GSCAN_ATTRIBUTE_CHANNEL_LIST,
++    GSCAN_ATTRIBUTE_CH_BUCKET_BITMASK,
++
++	/* remaining reserved for additional attributes */
++
++    GSCAN_ATTRIBUTE_SSID = GSCAN_ATTR_SET4,
++    GSCAN_ATTRIBUTE_BSSID,
++    GSCAN_ATTRIBUTE_CHANNEL,
++    GSCAN_ATTRIBUTE_RSSI,
++    GSCAN_ATTRIBUTE_TIMESTAMP,
++    GSCAN_ATTRIBUTE_RTT,
++    GSCAN_ATTRIBUTE_RTTSD,
++
++    /* remaining reserved for additional attributes */
++
++    GSCAN_ATTRIBUTE_HOTLIST_BSSIDS = GSCAN_ATTR_SET5,
++    GSCAN_ATTRIBUTE_RSSI_LOW,
++    GSCAN_ATTRIBUTE_RSSI_HIGH,
++    GSCAN_ATTRIBUTE_HOSTLIST_BSSID_ELEM,
++    GSCAN_ATTRIBUTE_HOTLIST_FLUSH,
++
++    /* remaining reserved for additional attributes */
++    GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE = GSCAN_ATTR_SET6,
++    GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE,
++    GSCAN_ATTRIBUTE_MIN_BREACHING,
++    GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS,
++    GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH,
++
++    /* EPNO */
++    GSCAN_ATTRIBUTE_EPNO_SSID_LIST = GSCAN_ATTR_SET7,
++    GSCAN_ATTRIBUTE_EPNO_SSID,
++    GSCAN_ATTRIBUTE_EPNO_SSID_LEN,
++    GSCAN_ATTRIBUTE_EPNO_RSSI,
++    GSCAN_ATTRIBUTE_EPNO_FLAGS,
++    GSCAN_ATTRIBUTE_EPNO_AUTH,
++    GSCAN_ATTRIBUTE_EPNO_SSID_NUM,
++    GSCAN_ATTRIBUTE_EPNO_FLUSH,
++
++    /* Roam SSID Whitelist and BSSID pref */
++    GSCAN_ATTRIBUTE_WHITELIST_SSID = GSCAN_ATTR_SET8,
++    GSCAN_ATTRIBUTE_NUM_WL_SSID,
++    GSCAN_ATTRIBUTE_WL_SSID_LEN,
++    GSCAN_ATTRIBUTE_WL_SSID_FLUSH,
++    GSCAN_ATTRIBUTE_WHITELIST_SSID_ELEM,
++    GSCAN_ATTRIBUTE_NUM_BSSID,
++    GSCAN_ATTRIBUTE_BSSID_PREF_LIST,
++    GSCAN_ATTRIBUTE_BSSID_PREF_FLUSH,
++    GSCAN_ATTRIBUTE_BSSID_PREF,
++    GSCAN_ATTRIBUTE_RSSI_MODIFIER,
++
++
++    /* Roam cfg */
++    GSCAN_ATTRIBUTE_A_BAND_BOOST_THRESHOLD = GSCAN_ATTR_SET9,
++    GSCAN_ATTRIBUTE_A_BAND_PENALTY_THRESHOLD,
++    GSCAN_ATTRIBUTE_A_BAND_BOOST_FACTOR,
++    GSCAN_ATTRIBUTE_A_BAND_PENALTY_FACTOR,
++    GSCAN_ATTRIBUTE_A_BAND_MAX_BOOST,
++    GSCAN_ATTRIBUTE_LAZY_ROAM_HYSTERESIS,
++    GSCAN_ATTRIBUTE_ALERT_ROAM_RSSI_TRIGGER,
++    GSCAN_ATTRIBUTE_LAZY_ROAM_ENABLE,
++
++    /* BSSID blacklist */
++    GSCAN_ATTRIBUTE_BSSID_BLACKLIST_FLUSH = GSCAN_ATTR_SET10,
++    GSCAN_ATTRIBUTE_BLACKLIST_BSSID,
++
++    GSCAN_ATTRIBUTE_ANQPO_HS_LIST = GSCAN_ATTR_SET11,
++    GSCAN_ATTRIBUTE_ANQPO_HS_LIST_SIZE,
++    GSCAN_ATTRIBUTE_ANQPO_HS_NETWORK_ID,
++    GSCAN_ATTRIBUTE_ANQPO_HS_NAI_REALM,
++    GSCAN_ATTRIBUTE_ANQPO_HS_ROAM_CONSORTIUM_ID,
++    GSCAN_ATTRIBUTE_ANQPO_HS_PLMN,
++
++    /* Adaptive scan attributes */
++    GSCAN_ATTRIBUTE_BUCKET_STEP_COUNT = GSCAN_ATTR_SET12,
++    GSCAN_ATTRIBUTE_BUCKET_MAX_PERIOD,
++
++    /* ePNO cfg */
++    GSCAN_ATTRIBUTE_EPNO_5G_RSSI_THR = GSCAN_ATTR_SET13,
++    GSCAN_ATTRIBUTE_EPNO_2G_RSSI_THR,
++    GSCAN_ATTRIBUTE_EPNO_INIT_SCORE_MAX,
++    GSCAN_ATTRIBUTE_EPNO_CUR_CONN_BONUS,
++    GSCAN_ATTRIBUTE_EPNO_SAME_NETWORK_BONUS,
++    GSCAN_ATTRIBUTE_EPNO_SECURE_BONUS,
++    GSCAN_ATTRIBUTE_EPNO_5G_BONUS,
++    GSCAN_ATTRIBUTE_MAX
++};
++
++enum gscan_bucket_attributes {
++	GSCAN_ATTRIBUTE_CH_BUCKET_1,
++	GSCAN_ATTRIBUTE_CH_BUCKET_2,
++	GSCAN_ATTRIBUTE_CH_BUCKET_3,
++	GSCAN_ATTRIBUTE_CH_BUCKET_4,
++	GSCAN_ATTRIBUTE_CH_BUCKET_5,
++	GSCAN_ATTRIBUTE_CH_BUCKET_6,
++	GSCAN_ATTRIBUTE_CH_BUCKET_7
++};
++
++enum gscan_ch_attributes {
++	GSCAN_ATTRIBUTE_CH_ID_1,
++	GSCAN_ATTRIBUTE_CH_ID_2,
++	GSCAN_ATTRIBUTE_CH_ID_3,
++	GSCAN_ATTRIBUTE_CH_ID_4,
++	GSCAN_ATTRIBUTE_CH_ID_5,
++	GSCAN_ATTRIBUTE_CH_ID_6,
++	GSCAN_ATTRIBUTE_CH_ID_7
++};
++
++enum rtt_attributes {
++	RTT_ATTRIBUTE_TARGET_CNT,
++	RTT_ATTRIBUTE_TARGET_INFO,
++	RTT_ATTRIBUTE_TARGET_MAC,
++	RTT_ATTRIBUTE_TARGET_TYPE,
++	RTT_ATTRIBUTE_TARGET_PEER,
++	RTT_ATTRIBUTE_TARGET_CHAN,
++	RTT_ATTRIBUTE_TARGET_PERIOD,
++	RTT_ATTRIBUTE_TARGET_NUM_BURST,
++	RTT_ATTRIBUTE_TARGET_NUM_FTM_BURST,
++	RTT_ATTRIBUTE_TARGET_NUM_RETRY_FTM,
++	RTT_ATTRIBUTE_TARGET_NUM_RETRY_FTMR,
++	RTT_ATTRIBUTE_TARGET_LCI,
++	RTT_ATTRIBUTE_TARGET_LCR,
++	RTT_ATTRIBUTE_TARGET_BURST_DURATION,
++	RTT_ATTRIBUTE_TARGET_PREAMBLE,
++	RTT_ATTRIBUTE_TARGET_BW,
++	RTT_ATTRIBUTE_RESULTS_COMPLETE = 30,
++	RTT_ATTRIBUTE_RESULTS_PER_TARGET,
++	RTT_ATTRIBUTE_RESULT_CNT,
++	RTT_ATTRIBUTE_RESULT
++};
++
++enum wifi_rssi_monitor_attr {
++	RSSI_MONITOR_ATTRIBUTE_MAX_RSSI,
++	RSSI_MONITOR_ATTRIBUTE_MIN_RSSI,
++	RSSI_MONITOR_ATTRIBUTE_START
++};
++
++enum wifi_sae_key_attr {
++	BRCM_SAE_KEY_ATTR_PEER_MAC,
++	BRCM_SAE_KEY_ATTR_PMK,
++	BRCM_SAE_KEY_ATTR_PMKID
++};
++
++enum debug_attributes {
++	DEBUG_ATTRIBUTE_GET_DRIVER,
++	DEBUG_ATTRIBUTE_GET_FW,
++	DEBUG_ATTRIBUTE_RING_ID,
++	DEBUG_ATTRIBUTE_RING_NAME,
++	DEBUG_ATTRIBUTE_RING_FLAGS,
++	DEBUG_ATTRIBUTE_LOG_LEVEL,
++	DEBUG_ATTRIBUTE_LOG_TIME_INTVAL,
++	DEBUG_ATTRIBUTE_LOG_MIN_DATA_SIZE,
++	DEBUG_ATTRIBUTE_FW_DUMP_LEN,
++	DEBUG_ATTRIBUTE_FW_DUMP_DATA,
++	DEBUG_ATTRIBUTE_RING_DATA,
++	DEBUG_ATTRIBUTE_RING_STATUS,
++	DEBUG_ATTRIBUTE_RING_NUM,
++	DEBUG_ATTRIBUTE_DRIVER_DUMP_LEN,
++	DEBUG_ATTRIBUTE_DRIVER_DUMP_DATA,
++	DEBUG_ATTRIBUTE_PKT_FATE_NUM,
++	DEBUG_ATTRIBUTE_PKT_FATE_DATA
++};
++
++enum mkeep_alive_attributes {
++	MKEEP_ALIVE_ATTRIBUTE_ID,
++	MKEEP_ALIVE_ATTRIBUTE_IP_PKT,
++	MKEEP_ALIVE_ATTRIBUTE_IP_PKT_LEN,
++	MKEEP_ALIVE_ATTRIBUTE_SRC_MAC_ADDR,
++	MKEEP_ALIVE_ATTRIBUTE_DST_MAC_ADDR,
++	MKEEP_ALIVE_ATTRIBUTE_PERIOD_MSEC
++};
++enum apf_attributes {
++	APF_ATTRIBUTE_VERSION,
++	APF_ATTRIBUTE_MAX_LEN,
++	APF_ATTRIBUTE_PROGRAM,
++	APF_ATTRIBUTE_PROGRAM_LEN
++};
++
++typedef enum wl_vendor_event {
++	BRCM_VENDOR_EVENT_UNSPEC		= 0,
++	BRCM_VENDOR_EVENT_PRIV_STR		= 1,
++	GOOGLE_GSCAN_SIGNIFICANT_EVENT		= 2,
++	GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT	= 3,
++	GOOGLE_GSCAN_BATCH_SCAN_EVENT		= 4,
++	GOOGLE_SCAN_FULL_RESULTS_EVENT		= 5,
++	GOOGLE_RTT_COMPLETE_EVENT		= 6,
++	GOOGLE_SCAN_COMPLETE_EVENT		= 7,
++	GOOGLE_GSCAN_GEOFENCE_LOST_EVENT	= 8,
++	GOOGLE_SCAN_EPNO_EVENT			= 9,
++	GOOGLE_DEBUG_RING_EVENT			= 10,
++	GOOGLE_FW_DUMP_EVENT			= 11,
++	GOOGLE_PNO_HOTSPOT_FOUND_EVENT		= 12,
++	GOOGLE_RSSI_MONITOR_EVENT		= 13,
++	GOOGLE_MKEEP_ALIVE_EVENT		= 14,
++
++	/*
++	 * BRCM specific events should be placed after
++	 * the Generic events so that enums don't mismatch
++	 * between the DHD and HAL
++	 */
++	GOOGLE_NAN_EVENT_ENABLED		= 15,
++	GOOGLE_NAN_EVENT_DISABLED		= 16,
++	GOOGLE_NAN_EVENT_SUBSCRIBE_MATCH	= 17,
++	GOOGLE_NAN_EVENT_REPLIED		= 18,
++	GOOGLE_NAN_EVENT_PUBLISH_TERMINATED	= 19,
++	GOOGLE_NAN_EVENT_SUBSCRIBE_TERMINATED	= 20,
++	GOOGLE_NAN_EVENT_DE_EVENT		= 21,
++	GOOGLE_NAN_EVENT_FOLLOWUP		= 22,
++	GOOGLE_NAN_EVENT_TRANSMIT_FOLLOWUP_IND	= 23,
++	GOOGLE_NAN_EVENT_DATA_REQUEST		= 24,
++	GOOGLE_NAN_EVENT_DATA_CONFIRMATION	= 25,
++	GOOGLE_NAN_EVENT_DATA_END		= 26,
++	GOOGLE_NAN_EVENT_BEACON			= 27,
++	GOOGLE_NAN_EVENT_SDF			= 28,
++	GOOGLE_NAN_EVENT_TCA			= 29,
++	GOOGLE_NAN_EVENT_SUBSCRIBE_UNMATCH	= 30,
++	GOOGLE_NAN_EVENT_UNKNOWN		= 31,
++	GOOGLE_ROAM_EVENT_START			= 32,
++	BRCM_VENDOR_EVENT_HANGED                = 33,
++	BRCM_VENDOR_EVENT_SAE_KEY               = 34,
++	BRCM_VENDOR_EVENT_BEACON_RECV           = 35,
++	BRCM_VENDOR_EVENT_PORT_AUTHORIZED       = 36,
++	GOOGLE_FILE_DUMP_EVENT			= 37,
++	BRCM_VENDOR_EVENT_CU			= 38,
++	BRCM_VENDOR_EVENT_WIPS			= 39,
++	NAN_ASYNC_RESPONSE_DISABLED		= 40
++} wl_vendor_event_t;
++
++enum andr_wifi_attr {
++	ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET,
++	ANDR_WIFI_ATTRIBUTE_FEATURE_SET,
++	ANDR_WIFI_ATTRIBUTE_RANDOM_MAC_OUI,
++	ANDR_WIFI_ATTRIBUTE_NODFS_SET,
++	ANDR_WIFI_ATTRIBUTE_COUNTRY,
++	ANDR_WIFI_ATTRIBUTE_ND_OFFLOAD_VALUE,
++	ANDR_WIFI_ATTRIBUTE_TCPACK_SUP_VALUE
++};
++
++typedef enum wl_vendor_gscan_attribute {
++	ATTR_START_GSCAN,
++	ATTR_STOP_GSCAN,
++	ATTR_SET_SCAN_BATCH_CFG_ID, /* set batch scan params */
++	ATTR_SET_SCAN_GEOFENCE_CFG_ID, /* set list of bssids to track */
++	ATTR_SET_SCAN_SIGNIFICANT_CFG_ID, /* set list of bssids, rssi threshold etc.. */
++	ATTR_SET_SCAN_CFG_ID, /* set common scan config params here */
++	ATTR_GET_GSCAN_CAPABILITIES_ID,
++    /* Add more sub commands here */
++	ATTR_GSCAN_MAX
++} wl_vendor_gscan_attribute_t;
++
++typedef enum gscan_batch_attribute {
++	ATTR_GSCAN_BATCH_BESTN,
++	ATTR_GSCAN_BATCH_MSCAN,
++	ATTR_GSCAN_BATCH_BUFFER_THRESHOLD
++} gscan_batch_attribute_t;
++
++typedef enum gscan_geofence_attribute {
++	ATTR_GSCAN_NUM_HOTLIST_BSSID,
++	ATTR_GSCAN_HOTLIST_BSSID
++} gscan_geofence_attribute_t;
++
++typedef enum gscan_complete_event {
++	WIFI_SCAN_COMPLETE,
++	WIFI_SCAN_THRESHOLD_NUM_SCANS,
++	WIFI_SCAN_BUFFER_THR_BREACHED
++} gscan_complete_event_t;
++
++#ifdef DHD_WAKE_STATUS
++enum wake_stat_attributes {
++	WAKE_STAT_ATTRIBUTE_TOTAL_CMD_EVENT,
++	WAKE_STAT_ATTRIBUTE_CMD_EVENT_WAKE,
++	WAKE_STAT_ATTRIBUTE_CMD_EVENT_COUNT,
++	WAKE_STAT_ATTRIBUTE_CMD_EVENT_COUNT_USED,
++	WAKE_STAT_ATTRIBUTE_TOTAL_DRIVER_FW,
++	WAKE_STAT_ATTRIBUTE_DRIVER_FW_WAKE,
++	WAKE_STAT_ATTRIBUTE_DRIVER_FW_COUNT,
++	WAKE_STAT_ATTRIBUTE_DRIVER_FW_COUNT_USED,
++	WAKE_STAT_ATTRIBUTE_TOTAL_RX_DATA_WAKE,
++	WAKE_STAT_ATTRIBUTE_RX_UNICAST_COUNT,
++	WAKE_STAT_ATTRIBUTE_RX_MULTICAST_COUNT,
++	WAKE_STAT_ATTRIBUTE_RX_BROADCAST_COUNT,
++	WAKE_STAT_ATTRIBUTE_RX_ICMP_PKT,
++	WAKE_STAT_ATTRIBUTE_RX_ICMP6_PKT,
++	WAKE_STAT_ATTRIBUTE_RX_ICMP6_RA,
++	WAKE_STAT_ATTRIBUTE_RX_ICMP6_NA,
++	WAKE_STAT_ATTRIBUTE_RX_ICMP6_NS,
++	WAKE_STAT_ATTRIBUTE_IPV4_RX_MULTICAST_ADD_CNT,
++	WAKE_STAT_ATTRIBUTE_IPV6_RX_MULTICAST_ADD_CNT,
++	WAKE_STAT_ATTRIBUTE_OTHER_RX_MULTICAST_ADD_CNT
++};
++
++typedef struct rx_data_cnt_details_t {
++	int rx_unicast_cnt;		/* Total rx unicast packet which woke up host */
++	int rx_multicast_cnt;   /* Total rx multicast packet which woke up host */
++	int rx_broadcast_cnt;   /* Total rx broadcast packet which woke up host */
++} RX_DATA_WAKE_CNT_DETAILS;
++
++typedef struct rx_wake_pkt_type_classification_t {
++	int icmp_pkt;   /* wake icmp packet count */
++	int icmp6_pkt;  /* wake icmp6 packet count */
++	int icmp6_ra;   /* wake icmp6 RA packet count */
++	int icmp6_na;   /* wake icmp6 NA packet count */
++	int icmp6_ns;   /* wake icmp6 NS packet count */
++} RX_WAKE_PKT_TYPE_CLASSFICATION;
++
++typedef struct rx_multicast_cnt_t {
++	int ipv4_rx_multicast_addr_cnt; /* Rx wake packet was ipv4 multicast */
++	int ipv6_rx_multicast_addr_cnt; /* Rx wake packet was ipv6 multicast */
++	int other_rx_multicast_addr_cnt; /* Rx wake packet was non-ipv4 and non-ipv6 */
++} RX_MULTICAST_WAKE_DATA_CNT;
++
++typedef struct wlan_driver_wake_reason_cnt_t {
++	int total_cmd_event_wake;    /* Total count of cmd event wakes */
++	int *cmd_event_wake_cnt;     /* Individual wake count array, each index a reason */
++	int cmd_event_wake_cnt_sz;   /* Max number of cmd event wake reasons */
++	int cmd_event_wake_cnt_used; /* Number of cmd event wake reasons specific to the driver */
++	int total_driver_fw_local_wake;    /* Total count of drive/fw wakes, for local reasons */
++	int *driver_fw_local_wake_cnt;     /* Individual wake count array, each index a reason */
++	int driver_fw_local_wake_cnt_sz;   /* Max number of local driver/fw wake reasons */
++	/* Number of local driver/fw wake reasons specific to the driver */
++	int driver_fw_local_wake_cnt_used;
++	int total_rx_data_wake;     /* total data rx packets, that woke up host */
++	RX_DATA_WAKE_CNT_DETAILS rx_wake_details;
++	RX_WAKE_PKT_TYPE_CLASSFICATION rx_wake_pkt_classification_info;
++	RX_MULTICAST_WAKE_DATA_CNT rx_multicast_wake_pkt_info;
++} WLAN_DRIVER_WAKE_REASON_CNT;
++#endif /* DHD_WAKE_STATUS */
++
++/* Capture the BRCM_VENDOR_SUBCMD_PRIV_STRINGS* here */
++#define BRCM_VENDOR_SCMD_CAPA	"cap"
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 13, 0)) || defined(WL_VENDOR_EXT_SUPPORT)
++extern int wl_cfgvendor_attach(struct wiphy *wiphy, dhd_pub_t *dhd);
++extern int wl_cfgvendor_detach(struct wiphy *wiphy);
++extern int wl_cfgvendor_send_async_event(struct wiphy *wiphy,
++                  struct net_device *dev, int event_id, const void  *data, int len);
++extern int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
++                struct net_device *dev, void  *data, int len, wl_vendor_event_t event);
++#else
++static INLINE int wl_cfgvendor_attach(struct wiphy *wiphy,
++		dhd_pub_t *dhd) { UNUSED_PARAMETER(wiphy); UNUSED_PARAMETER(dhd); return 0; }
++static INLINE int wl_cfgvendor_detach(struct wiphy *wiphy) { UNUSED_PARAMETER(wiphy); return 0; }
++#endif /*  (LINUX_VERSION_CODE > KERNEL_VERSION(3, 13, 0)) || defined(WL_VENDOR_EXT_SUPPORT) */
++
++#ifdef CONFIG_COMPAT
++#define COMPAT_ASSIGN_VALUE(normal_structure, member, value)	\
++	do { \
++		if (compat_task_state) {	\
++			compat_ ## normal_structure.member = value; \
++		} else { \
++			normal_structure.member = value; \
++		} \
++	} while (0)
++#else
++#define COMPAT_ASSIGN_VALUE(normal_structure, member, value) \
++	normal_structure.member = value;
++#endif /* CONFIG_COMPAT */
++
++#endif /* _wl_cfgvendor_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_dbg.h b/module_drivers/drivers/net/wireless/bcmdhd/wl_dbg.h
+new file mode 100644
+index 000000000..dc05b07b8
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_dbg.h
+@@ -0,0 +1,246 @@
++/*
++ * Minimal debug/trace/assert driver definitions for
++ * Broadcom 802.11 Networking Adapter.
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_dbg.h 664795 2016-10-13 20:13:32Z $
++ */
++
++
++#ifndef _wl_dbg_h_
++#define _wl_dbg_h_
++
++#if defined(EVENT_LOG_COMPILE)
++#include <event_log.h>
++#endif
++
++/* wl_msg_level is a bit vector with defs in wlioctl.h */
++extern uint32 wl_msg_level;
++extern uint32 wl_msg_level2;
++
++#define WL_TIMESTAMP()
++
++#ifdef ENABLE_CORECAPTURE
++#define MAX_BACKTRACE_DEPTH 32
++extern int wl_print_backtrace(const char * prefix, void * i_backtrace, int i_backtrace_depth);
++#else
++#define wl_print_backtrace(a, b, c)
++#endif /* ENABLE_CORECAPTURE */
++
++
++#define WIFICC_CAPTURE(_reason)
++#define WIFICC_LOGDEBUGIF(_flags, _args)
++#define WIFICC_LOGDEBUG(_args)
++
++#define WL_PRINT(args)		do { WL_TIMESTAMP(); printf args; } while (0)
++
++#if defined(EVENT_LOG_COMPILE) && defined(WLMSG_SRSCAN)
++#define _WL_SRSCAN(fmt, ...)	EVENT_LOG(EVENT_LOG_TAG_SRSCAN, fmt, ##__VA_ARGS__)
++#define WL_SRSCAN(args)		_WL_SRSCAN args
++#else
++#define WL_SRSCAN(args)
++#endif
++
++#if defined(BCMCONDITIONAL_LOGGING)
++
++/* Ideally this should be some include file that vendors can include to conditionalize logging */
++
++/* DBGONLY() macro to reduce ifdefs in code for statements that are only needed when
++ * BCMDBG is defined.
++ */
++#define DBGONLY(x) x
++
++/* To disable a message completely ... until you need it again */
++#define WL_NONE(args)
++#define WL_ERROR(args)		do {if (wl_msg_level & WL_ERROR_VAL) WL_PRINT(args); \
++					else WIFICC_LOGDEBUG(args); } while (0)
++#define WL_TRACE(args)
++#define WL_PRHDRS_MSG(args)
++#define WL_PRHDRS(i, p, f, t, r, l)
++#define WL_PRPKT(m, b, n)
++#define WL_INFORM(args)
++#define WL_TMP(args)
++#define WL_OID(args)
++#define WL_RATE(args)		do {if (wl_msg_level & WL_RATE_VAL) WL_PRINT(args);} while (0)
++#define WL_ASSOC(args)		do {if (wl_msg_level & WL_ASSOC_VAL) WL_PRINT(args); \
++					else WIFICC_LOGDEBUG(args);} while (0)
++#define WL_PRUSR(m, b, n)
++#define WL_PS(args)		do {if (wl_msg_level & WL_PS_VAL) WL_PRINT(args);} while (0)
++
++#define WL_PORT(args)
++#define WL_DUAL(args)
++#define WL_REGULATORY(args)	do {if (wl_msg_level & WL_REGULATORY_VAL) WL_PRINT(args); \
++					else WIFICC_LOGDEBUG(args);} while (0)
++
++#define WL_MPC(args)
++#define WL_APSTA(args)
++#define WL_APSTA_BCN(args)
++#define WL_APSTA_TX(args)
++#define WL_APSTA_TSF(args)
++#define WL_APSTA_BSSID(args)
++#define WL_BA(args)
++#define WL_MBSS(args)
++#define WL_PROTO(args)
++
++#define	WL_CAC(args)		do {if (wl_msg_level & WL_CAC_VAL) WL_PRINT(args);} while (0)
++#define WL_AMSDU(args)
++#define WL_AMPDU(args)
++#define WL_FFPLD(args)
++#define WL_MCHAN(args)
++
++#define WL_DFS(args)
++#define WL_WOWL(args)
++#define WL_DPT(args)
++#define WL_ASSOC_OR_DPT(args)
++#define WL_SCAN(args)		do {if (wl_msg_level2 & WL_SCAN_VAL) WL_PRINT(args);} while (0)
++#define WL_COEX(args)
++#define WL_RTDC(w, s, i, j)
++#define WL_RTDC2(w, s, i, j)
++#define WL_CHANINT(args)
++#define WL_P2P(args)
++#define WL_ITFR(args)
++#define WL_TDLS(args)
++#define WL_MCNX(args)
++#define WL_PROT(args)
++#define WL_PSTA(args)
++#define WL_WFDS(m, b, n)
++#define WL_TRF_MGMT(args)
++#define WL_L2FILTER(args)
++#define WL_MQ(args)
++#define WL_TXBF(args)
++#define WL_MUMIMO(args)
++#define WL_P2PO(args)
++#define WL_ROAM(args)
++#define WL_WNM(args)
++
++#ifdef WLMSG_MESH
++#define WL_MESH(args)       WL_PRINT(args)
++#define WL_MESH_AMPE(args)  WL_PRINT(args)
++#define WL_MESH_ROUTE(args) WL_PRINT(args)
++#define WL_MESH_BCN(args)
++#else
++#define WL_MESH(args)
++#define WL_MESH_AMPE(args)
++#define WL_MESH_ROUTE(args)
++#define WL_MESH_BCN(args)
++#endif
++
++
++#define WL_AMPDU_UPDN(args)
++#define WL_AMPDU_RX(args)
++#define WL_AMPDU_ERR(args)
++#define WL_AMPDU_TX(args)
++#define WL_AMPDU_CTL(args)
++#define WL_AMPDU_HW(args)
++#define WL_AMPDU_HWTXS(args)
++#define WL_AMPDU_HWDBG(args)
++#define WL_AMPDU_STAT(args)
++#define WL_AMPDU_ERR_ON()       0
++#define WL_AMPDU_HW_ON()        0
++#define WL_AMPDU_HWTXS_ON()     0
++
++#define WL_APSTA_UPDN(args)
++#define WL_APSTA_RX(args)
++#define WL_WSEC(args)
++#define WL_WSEC_DUMP(args)
++#define WL_PCIE(args)
++#define WL_TSLOG(w, s, i, j)
++#define WL_FBT(args)
++
++#define WL_ERROR_ON()		(wl_msg_level & WL_ERROR_VAL)
++#define WL_TRACE_ON()		0
++#define WL_PRHDRS_ON()		0
++#define WL_PRPKT_ON()		0
++#define WL_INFORM_ON()		0
++#define WL_TMP_ON()		0
++#define WL_OID_ON()		0
++#define WL_RATE_ON()		(wl_msg_level & WL_RATE_VAL)
++#define WL_ASSOC_ON()		(wl_msg_level & WL_ASSOC_VAL)
++#define WL_PRUSR_ON()		0
++#define WL_PS_ON()		(wl_msg_level & WL_PS_VAL)
++#define WL_PORT_ON()		0
++#define WL_WSEC_ON()		0
++#define WL_WSEC_DUMP_ON()	0
++#define WL_MPC_ON()		0
++#define WL_REGULATORY_ON()	(wl_msg_level & WL_REGULATORY_VAL)
++#define WL_APSTA_ON()		0
++#define WL_DFS_ON()		0
++#define WL_MBSS_ON()		0
++#define WL_CAC_ON()		(wl_msg_level & WL_CAC_VAL)
++#define WL_AMPDU_ON()		0
++#define WL_DPT_ON()		0
++#define WL_WOWL_ON()		0
++#define WL_SCAN_ON()		(wl_msg_level2 & WL_SCAN_VAL)
++#define WL_P2P_ON()		0
++#define WL_ITFR_ON()		0
++#define WL_MCHAN_ON()		0
++#define WL_TDLS_ON()		0
++#define WL_MCNX_ON()		0
++#define WL_PROT_ON()		0
++#define WL_PSTA_ON()		0
++#define WL_TRF_MGMT_ON()	0
++#define WL_LPC_ON()		0
++#define WL_L2FILTER_ON()	0
++#define WL_TXBF_ON()		0
++#define WL_P2PO_ON()		0
++#define WL_TSLOG_ON()		0
++#define WL_WNM_ON()		0
++#define WL_PCIE_ON()		0
++#define WL_MUMIMO_ON()		0
++#define WL_MESH_ON()		0
++
++#else /* !BCMDBG */
++
++/* DBGONLY() macro to reduce ifdefs in code for statements that are only needed when
++ * BCMDBG is defined.
++ */
++#define DBGONLY(x)
++
++/* To disable a message completely ... until you need it again */
++#define WL_NONE(args)
++
++#define	WL_ERROR(args)
++
++#define	WL_TRACE(args)
++#define WL_APSTA_UPDN(args)
++#define WL_APSTA_RX(args)
++#ifdef WLMSG_WSEC
++#define WL_WSEC(args)		WL_PRINT(args)
++#define WL_WSEC_DUMP(args)	WL_PRINT(args)
++#else
++#define WL_WSEC(args)
++#define WL_WSEC_DUMP(args)
++#endif
++#define WL_PCIE(args)		do {if (wl_msg_level2 & WL_PCIE_VAL) WL_PRINT(args);} while (0)
++#define WL_PCIE_ON()		(wl_msg_level2 & WL_PCIE_VAL)
++#define WL_PFN(args)      do {if (wl_msg_level & WL_PFN_VAL) WL_PRINT(args);} while (0)
++#define WL_PFN_ON()		(wl_msg_level & WL_PFN_VAL)
++#endif 
++
++#define DBGERRONLY(x)
++
++extern uint32 wl_msg_level;
++extern uint32 wl_msg_level2;
++#endif /* _wl_dbg_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_escan.c b/module_drivers/drivers/net/wireless/bcmdhd/wl_escan.c
+new file mode 100644
+index 000000000..80fd01113
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_escan.c
+@@ -0,0 +1,1595 @@
++
++#if defined(WL_ESCAN)
++#include <bcmendian.h>
++#include <linux/if_arp.h>
++#include <asm/uaccess.h>
++#include <wl_android.h>
++#include <wl_escan.h>
++#include <dhd_config.h>
++
++#define ESCAN_ERROR(name, arg1, args...) \
++	do { \
++		if (android_msg_level & ANDROID_ERROR_LEVEL) { \
++			printk(KERN_ERR "[dhd-%s] ESCAN-ERROR) %s : " arg1, name, __func__, ## args); \
++		} \
++	} while (0)
++#define ESCAN_TRACE(name, arg1, args...) \
++	do { \
++		if (android_msg_level & ANDROID_TRACE_LEVEL) { \
++			printk(KERN_INFO "[dhd-%s] ESCAN-TRACE) %s : " arg1, name, __func__, ## args); \
++		} \
++	} while (0)
++#define ESCAN_SCAN(name, arg1, args...) \
++	do { \
++		if (android_msg_level & ANDROID_SCAN_LEVEL) { \
++			printk(KERN_INFO "[dhd-%s] ESCAN-SCAN) %s : " arg1, name, __func__, ## args); \
++		} \
++	} while (0)
++#define ESCAN_DBG(name, arg1, args...) \
++	do { \
++		if (android_msg_level & ANDROID_DBG_LEVEL) { \
++			printk(KERN_INFO "[dhd-%s] ESCAN-DBG) %s : " arg1, name, __func__, ## args); \
++		} \
++	} while (0)
++
++/* IOCTL swapping mode for Big Endian host with Little Endian dongle.  Default to off */
++#define htod32(i) (i)
++#define htod16(i) (i)
++#define dtoh32(i) (i)
++#define dtoh16(i) (i)
++#define htodchanspec(i) (i)
++#define dtohchanspec(i) (i)
++#define WL_EXTRA_BUF_MAX 2048
++
++#define wl_escan_get_buf(a) ((wl_scan_results_t *) (a)->escan_buf)
++
++#define for_each_bss(list, bss, __i)	\
++	for (__i = 0; __i < list->count && __i < IW_MAX_AP; __i++, bss = next_bss(list, bss))
++
++#define wl_escan_set_sync_id(a) ((a) = htod16(0x1234))
++
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++#define BUF_OVERFLOW_MGMT_COUNT 3
++typedef struct {
++	int RSSI;
++	int length;
++	struct ether_addr BSSID;
++} removal_element_t;
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++
++/* Return a new chanspec given a legacy chanspec
++ * Returns INVCHANSPEC on error
++ */
++static chanspec_t
++wl_chspec_from_legacy(chanspec_t legacy_chspec)
++{
++	chanspec_t chspec;
++
++	/* get the channel number */
++	chspec = LCHSPEC_CHANNEL(legacy_chspec);
++
++	/* convert the band */
++	if (LCHSPEC_IS2G(legacy_chspec)) {
++		chspec |= WL_CHANSPEC_BAND_2G;
++	} else {
++		chspec |= WL_CHANSPEC_BAND_5G;
++	}
++
++	/* convert the bw and sideband */
++	if (LCHSPEC_IS20(legacy_chspec)) {
++		chspec |= WL_CHANSPEC_BW_20;
++	} else {
++		chspec |= WL_CHANSPEC_BW_40;
++		if (LCHSPEC_CTL_SB(legacy_chspec) == WL_LCHANSPEC_CTL_SB_LOWER) {
++			chspec |= WL_CHANSPEC_CTL_SB_L;
++		} else {
++			chspec |= WL_CHANSPEC_CTL_SB_U;
++		}
++	}
++
++	if (wf_chspec_malformed(chspec)) {
++		ESCAN_ERROR("wlan", "wl_chspec_from_legacy: output chanspec (0x%04X) malformed\n",
++			chspec);
++		return INVCHANSPEC;
++	}
++
++	return chspec;
++}
++
++/* Return a legacy chanspec given a new chanspec
++ * Returns INVCHANSPEC on error
++ */
++static chanspec_t
++wl_chspec_to_legacy(chanspec_t chspec)
++{
++	chanspec_t lchspec;
++
++	if (wf_chspec_malformed(chspec)) {
++		ESCAN_ERROR("wlan", "wl_chspec_to_legacy: input chanspec (0x%04X) malformed\n",
++			chspec);
++		return INVCHANSPEC;
++	}
++
++	/* get the channel number */
++	lchspec = CHSPEC_CHANNEL(chspec);
++
++	/* convert the band */
++	if (CHSPEC_IS2G(chspec)) {
++		lchspec |= WL_LCHANSPEC_BAND_2G;
++	} else {
++		lchspec |= WL_LCHANSPEC_BAND_5G;
++	}
++
++	/* convert the bw and sideband */
++	if (CHSPEC_IS20(chspec)) {
++		lchspec |= WL_LCHANSPEC_BW_20;
++		lchspec |= WL_LCHANSPEC_CTL_SB_NONE;
++	} else if (CHSPEC_IS40(chspec)) {
++		lchspec |= WL_LCHANSPEC_BW_40;
++		if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_L) {
++			lchspec |= WL_LCHANSPEC_CTL_SB_LOWER;
++		} else {
++			lchspec |= WL_LCHANSPEC_CTL_SB_UPPER;
++		}
++	} else {
++		/* cannot express the bandwidth */
++		char chanbuf[CHANSPEC_STR_LEN];
++		ESCAN_ERROR("wlan", "wl_chspec_to_legacy: unable to convert chanspec %s "
++			"(0x%04X) to pre-11ac format\n",
++			wf_chspec_ntoa(chspec, chanbuf), chspec);
++		return INVCHANSPEC;
++	}
++
++	return lchspec;
++}
++
++/* given a chanspec value from the driver, do the endian and chanspec version conversion to
++ * a chanspec_t value
++ * Returns INVCHANSPEC on error
++ */
++static chanspec_t
++wl_chspec_driver_to_host(int ioctl_ver, chanspec_t chanspec)
++{
++	chanspec = dtohchanspec(chanspec);
++	if (ioctl_ver == 1) {
++		chanspec = wl_chspec_from_legacy(chanspec);
++	}
++
++	return chanspec;
++}
++
++/* given a chanspec value, do the endian and chanspec version conversion to
++ * a chanspec_t value
++ * Returns INVCHANSPEC on error
++ */
++static chanspec_t
++wl_chspec_host_to_driver(int ioctl_ver, chanspec_t chanspec)
++{
++	if (ioctl_ver == 1) {
++		chanspec = wl_chspec_to_legacy(chanspec);
++		if (chanspec == INVCHANSPEC) {
++			return chanspec;
++		}
++	}
++	chanspec = htodchanspec(chanspec);
++
++	return chanspec;
++}
++
++/* given a channel value, do the endian and chanspec version conversion to
++ * a chanspec_t value
++ * Returns INVCHANSPEC on error
++ */
++static chanspec_t
++wl_ch_host_to_driver(int ioctl_ver, u16 channel)
++{
++	chanspec_t chanspec;
++
++	chanspec = channel & WL_CHANSPEC_CHAN_MASK;
++
++	if (channel <= CH_MAX_2G_CHANNEL)
++		chanspec |= WL_CHANSPEC_BAND_2G;
++	else
++		chanspec |= WL_CHANSPEC_BAND_5G;
++
++	chanspec |= WL_CHANSPEC_BW_20;
++
++	chanspec |= WL_CHANSPEC_CTL_SB_NONE;
++
++	return wl_chspec_host_to_driver(ioctl_ver, chanspec);
++}
++
++static inline struct wl_bss_info *next_bss(struct wl_scan_results *list,
++	struct wl_bss_info *bss)
++{
++	return bss = bss ?
++		(struct wl_bss_info *)((uintptr) bss + dtoh32(bss->length)) : list->bss_info;
++}
++
++#if defined(ESCAN_RESULT_PATCH)
++static s32
++wl_escan_inform_bss(struct net_device *dev, struct wl_escan_info *escan)
++{
++	struct wl_scan_results *bss_list;
++	s32 err = 0;
++#if defined(RSSIAVG)
++	int rssi;
++#endif
++
++	bss_list = escan->bss_list;
++
++	ESCAN_SCAN(dev->name, "scanned AP count (%d)\n", bss_list->count);
++
++	/* Delete disconnected cache */
++#if defined(BSSCACHE)
++	wl_delete_disconnected_bss_cache(&escan->g_bss_cache_ctrl,
++		(u8*)&escan->disconnected_bssid);
++#if defined(RSSIAVG)
++	wl_delete_disconnected_rssi_cache(&escan->g_rssi_cache_ctrl,
++		(u8*)&escan->disconnected_bssid);
++#endif
++#endif
++
++	/* Update cache */
++#if defined(RSSIAVG)
++	wl_update_rssi_cache(&escan->g_rssi_cache_ctrl, bss_list);
++	if (!in_atomic())
++		wl_update_connected_rssi_cache(dev, &escan->g_rssi_cache_ctrl, &rssi);
++#endif
++#if defined(BSSCACHE)
++	wl_update_bss_cache(&escan->g_bss_cache_ctrl,
++#if defined(RSSIAVG)
++		&escan->g_rssi_cache_ctrl,
++#endif
++		bss_list);
++#endif
++
++	/* delete dirty cache */
++#if defined(RSSIAVG)
++	wl_delete_dirty_rssi_cache(&escan->g_rssi_cache_ctrl);
++	wl_reset_rssi_cache(&escan->g_rssi_cache_ctrl);
++#endif
++#if defined(BSSCACHE)
++	wl_delete_dirty_bss_cache(&escan->g_bss_cache_ctrl);
++	wl_reset_bss_cache(&escan->g_bss_cache_ctrl);
++	if (escan->autochannel)
++		wl_ext_get_best_channel(dev, &escan->g_bss_cache_ctrl,
++			escan->ioctl_ver, &escan->best_2g_ch, &escan->best_5g_ch);
++#else
++	if (escan->autochannel)
++		wl_ext_get_best_channel(dev, bss_list, escan->ioctl_ver,
++			&escan->best_2g_ch, &escan->best_5g_ch);
++#endif
++
++	return err;
++}
++#endif /* ESCAN_RESULT_PATCH */
++
++static wl_scan_params_t *
++wl_escan_alloc_params(struct net_device *dev, struct wl_escan_info *escan,
++	int channel, int nprobes, int *out_params_size)
++{
++	wl_scan_params_t *params;
++	int params_size;
++	int num_chans;
++
++	*out_params_size = 0;
++
++	/* Our scan params only need space for 1 channel and 0 ssids */
++	params_size = WL_SCAN_PARAMS_FIXED_SIZE + 1 * sizeof(uint16);
++	params = (wl_scan_params_t*) kzalloc(params_size, GFP_KERNEL);
++	if (params == NULL) {
++		ESCAN_ERROR(dev->name, "mem alloc failed (%d bytes)\n", params_size);
++		return params;
++	}
++	memset(params, 0, params_size);
++	params->nprobes = nprobes;
++
++	num_chans = (channel == 0) ? 0 : 1;
++
++	memcpy(&params->bssid, &ether_bcast, ETHER_ADDR_LEN);
++	params->bss_type = DOT11_BSSTYPE_ANY;
++	params->scan_type = DOT11_SCANTYPE_ACTIVE;
++	params->nprobes = htod32(1);
++	params->active_time = htod32(-1);
++	params->passive_time = htod32(-1);
++	params->home_time = htod32(10);
++	if (channel == -1)
++		params->channel_list[0] = htodchanspec(channel);
++	else
++		params->channel_list[0] = wl_ch_host_to_driver(escan->ioctl_ver, channel);
++
++	/* Our scan params have 1 channel and 0 ssids */
++	params->channel_num = htod32((0 << WL_SCAN_PARAMS_NSSID_SHIFT) |
++		(num_chans & WL_SCAN_PARAMS_COUNT_MASK));
++
++	*out_params_size = params_size;	/* rtn size to the caller */
++	return params;
++}
++
++static void
++wl_escan_abort(struct net_device *dev, struct wl_escan_info *escan)
++{
++	wl_scan_params_t *params = NULL;
++	s32 params_size = 0;
++	s32 err = BCME_OK;
++	if (!in_atomic()) {
++		/* Our scan params only need space for 1 channel and 0 ssids */
++		params = wl_escan_alloc_params(dev, escan, -1, 0, &params_size);
++		if (params == NULL) {
++			ESCAN_ERROR(dev->name, "scan params allocation failed \n");
++			err = -ENOMEM;
++		} else {
++			/* Do a scan abort to stop the driver's scan engine */
++			err = wldev_ioctl(dev, WLC_SCAN, params, params_size, true);
++			if (err < 0) {
++				ESCAN_ERROR(dev->name, "scan abort  failed \n");
++			}
++			kfree(params);
++		}
++	}
++}
++
++static s32
++wl_escan_notify_complete(struct net_device *dev,
++	struct wl_escan_info *escan, bool fw_abort)
++{
++	s32 err = BCME_OK;
++#if defined(WL_WIRELESS_EXT)
++	int cmd = 0;
++#if WIRELESS_EXT > 13
++	union iwreq_data wrqu;
++	char extra[IW_CUSTOM_MAX + 1];
++#endif
++#endif
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++
++	ESCAN_TRACE(dev->name, "Enter\n");
++
++	if (fw_abort && !in_atomic())
++		wl_escan_abort(dev, escan);
++
++	if (timer_pending(&escan->scan_timeout))
++		_del_timer_sync(&escan->scan_timeout);
++
++#if defined(ESCAN_RESULT_PATCH)
++	escan->bss_list = wl_escan_get_buf(escan);
++	wl_escan_inform_bss(dev, escan);
++#endif /* ESCAN_RESULT_PATCH */
++
++	escan->escan_state = ESCAN_STATE_IDLE;
++	wake_up_interruptible(&dhd->conf->event_complete);
++
++#if defined(WL_WIRELESS_EXT)
++#if WIRELESS_EXT > 13
++#if WIRELESS_EXT > 14
++	cmd = SIOCGIWSCAN;
++#endif
++	// terence 20150224: fix "wlan0: (WE) : Wireless Event too big (65306)"
++	memset(&wrqu, 0, sizeof(wrqu));
++	memset(extra, 0, sizeof(extra));
++	if (cmd) {
++		if (cmd == SIOCGIWSCAN) {
++			wireless_send_event(dev, cmd, &wrqu, NULL);
++		} else
++			wireless_send_event(dev, cmd, &wrqu, extra);
++	}
++#endif
++#endif
++
++	return err;
++}
++
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++static void
++wl_escan_find_removal_candidate(struct wl_escan_info *escan,
++	wl_bss_info_t *bss, removal_element_t *candidate)
++{
++	int idx;
++	for (idx = 0; idx < BUF_OVERFLOW_MGMT_COUNT; idx++) {
++		int len = BUF_OVERFLOW_MGMT_COUNT - idx - 1;
++		if (bss->RSSI < candidate[idx].RSSI) {
++			if (len)
++				memcpy(&candidate[idx + 1], &candidate[idx],
++					sizeof(removal_element_t) * len);
++			candidate[idx].RSSI = bss->RSSI;
++			candidate[idx].length = bss->length;
++			memcpy(&candidate[idx].BSSID, &bss->BSSID, ETHER_ADDR_LEN);
++			return;
++		}
++	}
++}
++
++static void
++wl_escan_remove_lowRSSI_info(struct net_device *dev, struct wl_escan_info *escan,
++	wl_scan_results_t *list, removal_element_t *candidate, wl_bss_info_t *bi)
++{
++	int idx1, idx2;
++	int total_delete_len = 0;
++	for (idx1 = 0; idx1 < BUF_OVERFLOW_MGMT_COUNT; idx1++) {
++		int cur_len = WL_SCAN_RESULTS_FIXED_SIZE;
++		wl_bss_info_t *bss = NULL;
++		if (candidate[idx1].RSSI >= bi->RSSI)
++			continue;
++		for (idx2 = 0; idx2 < list->count; idx2++) {
++			bss = bss ? (wl_bss_info_t *)((uintptr)bss + dtoh32(bss->length)) :
++				list->bss_info;
++			if (!bcmp(&candidate[idx1].BSSID, &bss->BSSID, ETHER_ADDR_LEN) &&
++				candidate[idx1].RSSI == bss->RSSI &&
++				candidate[idx1].length == dtoh32(bss->length)) {
++				u32 delete_len = dtoh32(bss->length);
++				ESCAN_DBG(dev->name,
++					"delete scan info of %pM to add new AP\n", &bss->BSSID);
++				if (idx2 < list->count -1) {
++					memmove((u8 *)bss, (u8 *)bss + delete_len,
++						list->buflen - cur_len - delete_len);
++				}
++				list->buflen -= delete_len;
++				list->count--;
++				total_delete_len += delete_len;
++				/* if delete_len is greater than or equal to result length */
++				if (total_delete_len >= bi->length) {
++					return;
++				}
++				break;
++			}
++			cur_len += dtoh32(bss->length);
++		}
++	}
++}
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++
++static s32
++wl_escan_handler(struct net_device *dev, struct wl_escan_info *escan,
++	const wl_event_msg_t *e, void *data)
++{
++	s32 err = BCME_OK;
++	s32 status = ntoh32(e->status);
++	wl_bss_info_t *bi;
++	wl_escan_result_t *escan_result;
++	wl_bss_info_t *bss = NULL;
++	wl_scan_results_t *list;
++	u32 bi_length;
++	u32 i;
++	u16 channel;
++
++	mutex_lock(&escan->usr_sync);
++	escan_result = (wl_escan_result_t *)data;
++
++	if (escan->escan_state != ESCAN_STATE_SCANING) {
++		ESCAN_DBG(dev->name, "Not my scan\n");
++		goto exit;
++	}
++
++	ESCAN_DBG(dev->name, "enter event type : %d, status : %d \n",
++		ntoh32(e->event_type), ntoh32(e->status));
++
++	if (status == WLC_E_STATUS_PARTIAL) {
++		ESCAN_DBG(dev->name, "WLC_E_STATUS_PARTIAL \n");
++		if (!escan_result) {
++			ESCAN_ERROR(dev->name, "Invalid escan result (NULL pointer)\n");
++			goto exit;
++		}
++		if (dtoh16(escan_result->bss_count) != 1) {
++			ESCAN_ERROR(dev->name, "Invalid bss_count %d: ignoring\n",
++				escan_result->bss_count);
++			goto exit;
++		}
++		bi = escan_result->bss_info;
++		if (!bi) {
++			ESCAN_ERROR(dev->name, "Invalid escan bss info (NULL pointer)\n");
++			goto exit;
++		}
++		bi_length = dtoh32(bi->length);
++		if (bi_length != (dtoh32(escan_result->buflen) - WL_ESCAN_RESULTS_FIXED_SIZE)) {
++			ESCAN_ERROR(dev->name, "Invalid bss_info length %d: ignoring\n",
++				bi_length);
++			goto exit;
++		}
++
++		/* +++++ terence 20130524: skip invalid bss */
++		channel =
++			bi->ctl_ch ? bi->ctl_ch :
++			CHSPEC_CHANNEL(wl_chspec_driver_to_host(escan->ioctl_ver, bi->chanspec));
++		if (!dhd_conf_match_channel(escan->pub, channel))
++			goto exit;
++		/* ----- terence 20130524: skip invalid bss */
++
++		{
++			int cur_len = WL_SCAN_RESULTS_FIXED_SIZE;
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++			removal_element_t candidate[BUF_OVERFLOW_MGMT_COUNT];
++			int remove_lower_rssi = FALSE;
++
++			bzero(candidate, sizeof(removal_element_t)*BUF_OVERFLOW_MGMT_COUNT);
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++
++			list = wl_escan_get_buf(escan);
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++			if (bi_length > ESCAN_BUF_SIZE - list->buflen)
++				remove_lower_rssi = TRUE;
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++
++			ESCAN_DBG(dev->name, "%s(%pM) RSSI %d flags 0x%x length %d\n",
++				bi->SSID, &bi->BSSID, bi->RSSI, bi->flags, bi->length);
++			for (i = 0; i < list->count; i++) {
++				bss = bss ? (wl_bss_info_t *)((uintptr)bss + dtoh32(bss->length))
++					: list->bss_info;
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++				ESCAN_DBG(dev->name,
++					"%s(%pM), i=%d bss: RSSI %d list->count %d\n",
++					bss->SSID, &bss->BSSID, i, bss->RSSI, list->count);
++
++				if (remove_lower_rssi)
++					wl_escan_find_removal_candidate(escan, bss, candidate);
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++				if (!bcmp(&bi->BSSID, &bss->BSSID, ETHER_ADDR_LEN) &&
++						(CHSPEC_BAND(wl_chspec_driver_to_host(escan->ioctl_ver, bi->chanspec))
++						== CHSPEC_BAND(wl_chspec_driver_to_host(escan->ioctl_ver, bss->chanspec))) &&
++						bi->SSID_len == bss->SSID_len &&
++						!bcmp(bi->SSID, bss->SSID, bi->SSID_len)) {
++
++					/* do not allow beacon data to update
++					*the data recd from a probe response
++					*/
++					if (!(bss->flags & WL_BSS_FLAGS_FROM_BEACON) &&
++						(bi->flags & WL_BSS_FLAGS_FROM_BEACON))
++						goto exit;
++
++					ESCAN_DBG(dev->name,
++						"%s(%pM), i=%d prev: RSSI %d flags 0x%x, "
++						"new: RSSI %d flags 0x%x\n",
++						bss->SSID, &bi->BSSID, i, bss->RSSI, bss->flags,
++						bi->RSSI, bi->flags);
++
++					if ((bss->flags & WL_BSS_FLAGS_RSSI_ONCHANNEL) ==
++						(bi->flags & WL_BSS_FLAGS_RSSI_ONCHANNEL)) {
++						/* preserve max RSSI if the measurements are
++						* both on-channel or both off-channel
++						*/
++						ESCAN_DBG(dev->name,
++							"%s(%pM), same onchan, RSSI: prev %d new %d\n",
++							bss->SSID, &bi->BSSID, bss->RSSI, bi->RSSI);
++						bi->RSSI = MAX(bss->RSSI, bi->RSSI);
++					} else if ((bss->flags & WL_BSS_FLAGS_RSSI_ONCHANNEL) &&
++						(bi->flags & WL_BSS_FLAGS_RSSI_ONCHANNEL) == 0) {
++						/* preserve the on-channel rssi measurement
++						* if the new measurement is off channel
++						*/
++						ESCAN_DBG(dev->name,
++							"%s(%pM), prev onchan, RSSI: prev %d new %d\n",
++							bss->SSID, &bi->BSSID, bss->RSSI, bi->RSSI);
++						bi->RSSI = bss->RSSI;
++						bi->flags |= WL_BSS_FLAGS_RSSI_ONCHANNEL;
++					}
++					if (dtoh32(bss->length) != bi_length) {
++						u32 prev_len = dtoh32(bss->length);
++
++						ESCAN_DBG(dev->name,
++							"bss info replacement occured(bcast:%d->probresp%d)\n",
++							bss->ie_length, bi->ie_length);
++						ESCAN_DBG(dev->name,
++							"%s(%pM), replacement!(%d -> %d)\n",
++							bss->SSID, &bi->BSSID, prev_len, bi_length);
++
++						if (list->buflen - prev_len + bi_length	> ESCAN_BUF_SIZE) {
++							ESCAN_ERROR(dev->name,
++								"Buffer is too small: keep the previous result "
++								"of this AP\n");
++							/* Only update RSSI */
++							bss->RSSI = bi->RSSI;
++							bss->flags |= (bi->flags
++								& WL_BSS_FLAGS_RSSI_ONCHANNEL);
++							goto exit;
++						}
++
++						if (i < list->count - 1) {
++							/* memory copy required by this case only */
++							memmove((u8 *)bss + bi_length,
++								(u8 *)bss + prev_len,
++								list->buflen - cur_len - prev_len);
++						}
++						list->buflen -= prev_len;
++						list->buflen += bi_length;
++					}
++					list->version = dtoh32(bi->version);
++					memcpy((u8 *)bss, (u8 *)bi, bi_length);
++					goto exit;
++				}
++				cur_len += dtoh32(bss->length);
++			}
++			if (bi_length > ESCAN_BUF_SIZE - list->buflen) {
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++				wl_escan_remove_lowRSSI_info(dev, escan, list, candidate, bi);
++				if (bi_length > ESCAN_BUF_SIZE - list->buflen) {
++					ESCAN_DBG(dev->name,
++						"RSSI(%pM) is too low(%d) to add Buffer\n",
++						&bi->BSSID, bi->RSSI);
++					goto exit;
++				}
++#else
++				ESCAN_ERROR(dev->name, "Buffer is too small: ignoring\n");
++				goto exit;
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++			}
++
++			memcpy(&(((char *)list)[list->buflen]), bi, bi_length);
++			list->version = dtoh32(bi->version);
++			list->buflen += bi_length;
++			list->count++;
++		}
++	}
++	else if (status == WLC_E_STATUS_SUCCESS) {
++		ESCAN_DBG(dev->name, "ESCAN COMPLETED\n");
++		escan->bss_list = wl_escan_get_buf(escan);
++		ESCAN_DBG(dev->name, "SCAN COMPLETED: scanned AP count=%d\n",
++			escan->bss_list->count);
++		wl_escan_notify_complete(dev, escan, false);
++	} else if ((status == WLC_E_STATUS_ABORT) || (status == WLC_E_STATUS_NEWSCAN) ||
++		(status == WLC_E_STATUS_11HQUIET) || (status == WLC_E_STATUS_CS_ABORT) ||
++		(status == WLC_E_STATUS_NEWASSOC)) {
++		/* Handle all cases of scan abort */
++		ESCAN_DBG(dev->name, "ESCAN ABORT reason: %d\n", status);
++		escan->bss_list = wl_escan_get_buf(escan);
++		ESCAN_DBG(dev->name, "SCAN ABORT: scanned AP count=%d\n",
++			escan->bss_list->count);
++		wl_escan_notify_complete(dev, escan, false);
++	} else if (status == WLC_E_STATUS_TIMEOUT) {
++		ESCAN_ERROR(dev->name, "WLC_E_STATUS_TIMEOUT\n");
++		ESCAN_ERROR(dev->name, "reason[0x%x]\n", e->reason);
++		if (e->reason == 0xFFFFFFFF) {
++			wl_escan_notify_complete(dev, escan, true);
++		}
++	} else {
++		ESCAN_ERROR(dev->name, "unexpected Escan Event %d : abort\n", status);
++		escan->bss_list = wl_escan_get_buf(escan);
++		ESCAN_DBG(dev->name, "SCAN ABORTED(UNEXPECTED): scanned AP count=%d\n",
++			escan->bss_list->count);
++		wl_escan_notify_complete(dev, escan, false);
++	}
++exit:
++	mutex_unlock(&escan->usr_sync);
++	return err;
++}
++
++static int
++wl_escan_prep(struct net_device *dev, struct wl_escan_info *escan,
++	wl_uint32_list_t *list, wl_scan_params_t *params, wlc_ssid_t *ssid, bool bcast)
++{
++	int err = 0;
++	wl_scan_results_t *results;
++	s32 offset;
++	char *ptr;
++	int i = 0, j = 0;
++	wlc_ssid_t ssid_tmp;
++	u32 n_channels = 0;
++	uint channel;
++	chanspec_t chanspec;
++	u32 n_ssids;
++
++	results = wl_escan_get_buf(escan);
++	results->version = 0;
++	results->count = 0;
++	results->buflen = WL_SCAN_RESULTS_FIXED_SIZE;
++	escan->escan_state = ESCAN_STATE_SCANING;
++
++	/* Arm scan timeout timer */
++	mod_timer(&escan->scan_timeout, jiffies + msecs_to_jiffies(WL_ESCAN_TIMER_INTERVAL_MS));
++
++	memcpy(&params->bssid, &ether_bcast, ETHER_ADDR_LEN);
++	params->bss_type = DOT11_BSSTYPE_ANY;
++	params->scan_type = 0;
++	params->nprobes = -1;
++	params->active_time = -1;
++	params->passive_time = -1;
++	params->home_time = -1;
++	params->channel_num = 0;
++
++	params->nprobes = htod32(params->nprobes);
++	params->active_time = htod32(params->active_time);
++	params->passive_time = htod32(params->passive_time);
++	params->home_time = htod32(params->home_time);
++
++	n_channels = dtoh32(list->count);
++	/* Copy channel array if applicable */
++	ESCAN_SCAN(dev->name, "### List of channelspecs to scan ###\n");
++	if (n_channels > 0) {
++		for (i = 0; i < n_channels; i++) {
++			channel = dtoh32(list->element[i]);
++			if (!dhd_conf_match_channel(escan->pub, channel))
++				continue;
++			chanspec = WL_CHANSPEC_BW_20;
++			if (chanspec == INVCHANSPEC) {
++				ESCAN_ERROR(dev->name, "Invalid chanspec! Skipping channel\n");
++				continue;
++			}
++			if (channel <= CH_MAX_2G_CHANNEL) {
++				chanspec |= WL_CHANSPEC_BAND_2G;
++			} else {
++				chanspec |= WL_CHANSPEC_BAND_5G;
++			}
++			params->channel_list[j] = channel;
++			params->channel_list[j] &= WL_CHANSPEC_CHAN_MASK;
++			params->channel_list[j] |= chanspec;
++			ESCAN_SCAN(dev->name, "Chan : %d, Channel spec: %x\n",
++				channel, params->channel_list[j]);
++			params->channel_list[j] = wl_chspec_host_to_driver(escan->ioctl_ver,
++				params->channel_list[j]);
++			j++;
++		}
++	} else {
++		ESCAN_SCAN(dev->name, "Scanning all channels\n");
++	}
++
++	if (ssid && ssid->SSID_len) {
++		/* Copy ssid array if applicable */
++		ESCAN_SCAN(dev->name, "### List of SSIDs to scan ###\n");
++		offset = offsetof(wl_scan_params_t, channel_list) + n_channels * sizeof(u16);
++		offset = roundup(offset, sizeof(u32));
++		ptr = (char*)params + offset;
++
++		if (bcast) {
++			n_ssids = 2;
++			ESCAN_SCAN(dev->name, "0: Broadcast scan\n");
++			memset(&ssid_tmp, 0, sizeof(wlc_ssid_t));
++			ssid_tmp.SSID_len = 0;
++			memcpy(ptr, &ssid_tmp, sizeof(wlc_ssid_t));
++			ptr += sizeof(wlc_ssid_t);
++		} else {
++			n_ssids = 1;
++		}
++
++		memset(&ssid_tmp, 0, sizeof(wlc_ssid_t));
++		ssid_tmp.SSID_len = ssid->SSID_len;
++		memcpy(ssid_tmp.SSID, ssid->SSID, ssid->SSID_len);
++		memcpy(ptr, &ssid_tmp, sizeof(wlc_ssid_t));
++		ptr += sizeof(wlc_ssid_t);
++		ESCAN_SCAN(dev->name, "1: scan for %s size=%d\n",
++			ssid_tmp.SSID, ssid_tmp.SSID_len);
++		/* Adding mask to channel numbers */
++		params->channel_num =
++	        htod32((n_ssids << WL_SCAN_PARAMS_NSSID_SHIFT) |
++	               (n_channels & WL_SCAN_PARAMS_COUNT_MASK));
++	}
++	else {
++		ESCAN_SCAN(dev->name, "Broadcast scan\n");
++	}
++
++	return err;
++}
++
++static int
++wl_escan_reset(struct wl_escan_info *escan)
++{
++	if (timer_pending(&escan->scan_timeout))
++		_del_timer_sync(&escan->scan_timeout);
++	escan->escan_state = ESCAN_STATE_IDLE;
++
++	return 0;
++}
++
++static void
++wl_escan_timeout(unsigned long data)
++{
++	wl_event_msg_t msg;
++	struct wl_escan_info *escan = (struct wl_escan_info *)data;
++	struct wl_scan_results *bss_list;
++	struct wl_bss_info *bi = NULL;
++	s32 i;
++	u32 channel;
++
++	if (!escan->dev) {
++		ESCAN_ERROR("wlan", "No dev present\n");
++		return;
++	}
++
++	bss_list = wl_escan_get_buf(escan);
++	if (!bss_list) {
++		ESCAN_ERROR(escan->dev->name,
++			"bss_list is null. Didn't receive any partial scan results\n");
++	} else {
++		ESCAN_ERROR(escan->dev->name, "scanned AP count (%d)\n", bss_list->count);
++		bi = next_bss(bss_list, bi);
++		for_each_bss(bss_list, bi, i) {
++			channel = wf_chspec_ctlchan(wl_chspec_driver_to_host(escan->ioctl_ver,
++				bi->chanspec));
++			ESCAN_ERROR(escan->dev->name, "SSID :%s  Channel :%d\n", bi->SSID, channel);
++		}
++	}
++
++	bzero(&msg, sizeof(wl_event_msg_t));
++	ESCAN_ERROR(escan->dev->name, "timer expired\n");
++
++	msg.ifidx = dhd_net2idx(escan->pub->info, escan->dev);
++	msg.event_type = hton32(WLC_E_ESCAN_RESULT);
++	msg.status = hton32(WLC_E_STATUS_TIMEOUT);
++	msg.reason = 0xFFFFFFFF;
++	wl_ext_event_send(escan->pub->event_params, &msg, NULL);
++}
++
++int
++wl_escan_set_scan(struct net_device *dev, dhd_pub_t *dhdp,
++	wlc_ssid_t *ssid, uint16 channel, bool bcast)
++{
++	struct wl_escan_info *escan = dhdp->escan;
++	s32 err = BCME_OK;
++	s32 params_size = (WL_SCAN_PARAMS_FIXED_SIZE + OFFSETOF(wl_escan_params_t, params));
++	wl_escan_params_t *params = NULL;
++	scb_val_t scbval;
++	static int cnt = 0;
++	u32 n_channels = 0;
++	wl_uint32_list_t *list;
++	u8 valid_chan_list[sizeof(u32)*(WL_NUMCHANNELS + 1)];
++
++	mutex_lock(&escan->usr_sync);
++	if (escan->escan_state == ESCAN_STATE_DOWN) {
++		ESCAN_ERROR(dev->name, "STATE is down\n");
++		err = -EINVAL;
++		goto exit2;
++	}
++
++	if (wl_ext_check_scan(dev, dhdp)) {
++		err = -EBUSY;
++		goto exit;
++	}
++
++	ESCAN_TRACE(dev->name, "Enter \n");
++
++	/* if scan request is not empty parse scan request paramters */
++	memset(valid_chan_list, 0, sizeof(valid_chan_list));
++	list = (wl_uint32_list_t *)(void *) valid_chan_list;
++
++	if (channel) {
++		list->count = htod32(1);
++		list->element[0] = htod32(channel);
++	} else {
++		list->count = htod32(WL_NUMCHANNELS);
++		err = wldev_ioctl(dev, WLC_GET_VALID_CHANNELS, valid_chan_list,
++			sizeof(valid_chan_list), false);
++		if (err != 0) {
++			ESCAN_ERROR(dev->name, "get channels failed with %d\n", err);
++			goto exit;
++		}
++	}
++
++	n_channels = dtoh32(list->count);
++	/* Allocate space for populating ssids in wl_escan_params_t struct */
++	if (dtoh32(list->count) % 2)
++		/* If n_channels is odd, add a padd of u16 */
++		params_size += sizeof(u16) * (n_channels + 1);
++	else
++		params_size += sizeof(u16) * n_channels;
++	if (ssid && ssid->SSID_len) {
++		params_size += sizeof(struct wlc_ssid) * 2;
++	}
++
++	params = (wl_escan_params_t *) kzalloc(params_size, GFP_KERNEL);
++	if (params == NULL) {
++		err = -ENOMEM;
++		goto exit;
++	}
++	wl_escan_prep(dev, escan, list, &params->params, ssid, bcast);
++
++	params->version = htod32(ESCAN_REQ_VERSION);
++	params->action =  htod16(WL_SCAN_ACTION_START);
++	wl_escan_set_sync_id(params->sync_id);
++	if (params_size + sizeof("escan") >= WLC_IOCTL_MEDLEN) {
++		ESCAN_ERROR(dev->name, "ioctl buffer length not sufficient\n");
++		kfree(params);
++		err = -ENOMEM;
++		goto exit;
++	}
++	params->params.scan_type = DOT11_SCANTYPE_ACTIVE;
++	ESCAN_SCAN(dev->name, "Passive scan_type %d\n", params->params.scan_type);
++
++	WL_MSG(dev->name, "LEGACY_SCAN\n");
++	err = wldev_iovar_setbuf(dev, "escan", params, params_size,
++		escan->escan_ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	if (unlikely(err)) {
++		if (err == BCME_EPERM)
++			/* Scan Not permitted at this point of time */
++			ESCAN_TRACE(dev->name, "Escan not permitted at this time (%d)\n", err);
++		else
++			ESCAN_ERROR(dev->name, "Escan set error (%d)\n", err);
++	}
++	kfree(params);
++
++	if (unlikely(err)) {
++		/* Don't print Error incase of Scan suppress */
++		if ((err == BCME_EPERM))
++			ESCAN_TRACE(dev->name, "Escan failed: Scan Suppressed\n");
++		else {
++			cnt++;
++			ESCAN_ERROR(dev->name, "error (%d), cnt=%d\n", err, cnt);
++			// terence 20140111: send disassoc to firmware
++			if (cnt >= 4) {
++				memset(&scbval, 0, sizeof(scb_val_t));
++				wldev_ioctl(dev, WLC_DISASSOC, &scbval, sizeof(scb_val_t), true);
++				ESCAN_ERROR(dev->name, "Send disassoc to break the busy\n");
++				cnt = 0;
++			}
++		}
++	} else {
++		cnt = 0;
++		escan->dev = dev;
++	}
++exit:
++	if (unlikely(err)) {
++		wl_escan_reset(escan);
++	}
++exit2:
++	mutex_unlock(&escan->usr_sync);
++	return err;
++}
++
++#if defined(WL_WIRELESS_EXT)
++static int
++rssi_to_qual(int rssi)
++{
++	if (rssi <= WL_IW_RSSI_NO_SIGNAL)
++		return 0;
++	else if (rssi <= WL_IW_RSSI_VERY_LOW)
++		return 1;
++	else if (rssi <= WL_IW_RSSI_LOW)
++		return 2;
++	else if (rssi <= WL_IW_RSSI_GOOD)
++		return 3;
++	else if (rssi <= WL_IW_RSSI_VERY_GOOD)
++		return 4;
++	else
++		return 5;
++}
++
++static int
++wl_escan_merge_scan_results(struct net_device *dev, struct wl_escan_info *escan,
++	struct iw_request_info *info, char *extra, wl_bss_info_t *bi, int *len, int max_size)
++{
++	s32 err = BCME_OK;
++	struct iw_event	iwe;
++	int j;
++	char *event = extra, *end = extra + max_size - WE_ADD_EVENT_FIX, *value;
++	int16 rssi;
++	int channel;
++	chanspec_t chanspec;
++
++	/* overflow check cover fields before wpa IEs */
++	if (event + ETHER_ADDR_LEN + bi->SSID_len + IW_EV_UINT_LEN + IW_EV_FREQ_LEN +
++		IW_EV_QUAL_LEN >= end) {
++		err = -E2BIG;
++		goto exit;
++	}
++
++#if defined(RSSIAVG)
++	rssi = wl_get_avg_rssi(&escan->g_rssi_cache_ctrl, &bi->BSSID);
++	if (rssi == RSSI_MINVAL)
++		rssi = MIN(dtoh16(bi->RSSI), RSSI_MAXVAL);
++#else
++	// terence 20150419: limit the max. rssi to -2 or the bss will be filtered out in android OS
++	rssi = MIN(dtoh16(bi->RSSI), RSSI_MAXVAL);
++#endif
++	chanspec = wl_chspec_driver_to_host(escan->ioctl_ver, bi->chanspec);
++	channel = wf_chspec_ctlchan(chanspec);
++	ESCAN_SCAN(dev->name, "BSSID %pM, channel %3d(%3d %sMHz), rssi %3d, SSID \"%s\"\n",
++		&bi->BSSID, channel, CHSPEC_CHANNEL(chanspec),
++		CHSPEC_IS20(chanspec)?"20":
++		CHSPEC_IS40(chanspec)?"40":
++		CHSPEC_IS80(chanspec)?"80":"160",
++		rssi, bi->SSID);
++
++	/* First entry must be the BSSID */
++	iwe.cmd = SIOCGIWAP;
++	iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
++	memcpy(iwe.u.ap_addr.sa_data, &bi->BSSID, ETHER_ADDR_LEN);
++	event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_ADDR_LEN);
++
++	/* SSID */
++	iwe.u.data.length = dtoh32(bi->SSID_len);
++	iwe.cmd = SIOCGIWESSID;
++	iwe.u.data.flags = 1;
++	event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, bi->SSID);
++
++	/* Mode */
++	if (dtoh16(bi->capability) & (DOT11_CAP_ESS | DOT11_CAP_IBSS)) {
++		iwe.cmd = SIOCGIWMODE;
++		if (dtoh16(bi->capability) & DOT11_CAP_ESS)
++			iwe.u.mode = IW_MODE_INFRA;
++		else
++			iwe.u.mode = IW_MODE_ADHOC;
++		event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_UINT_LEN);
++	}
++
++	/* Channel */
++	iwe.cmd = SIOCGIWFREQ;
++#if 1
++	iwe.u.freq.m = wf_channel2mhz(channel, channel <= CH_MAX_2G_CHANNEL ?
++			WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G);
++#else
++	iwe.u.freq.m = wf_channel2mhz(bi->n_cap ?
++			bi->ctl_ch : CHSPEC_CHANNEL(bi->chanspec),
++			CHSPEC_CHANNEL(bi->chanspec) <= CH_MAX_2G_CHANNEL ?
++			WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G);
++#endif
++	iwe.u.freq.e = 6;
++	event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_FREQ_LEN);
++
++	/* Channel quality */
++	iwe.cmd = IWEVQUAL;
++	iwe.u.qual.qual = rssi_to_qual(rssi);
++	iwe.u.qual.level = 0x100 + rssi;
++	iwe.u.qual.noise = 0x100 + bi->phy_noise;
++	event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_QUAL_LEN);
++
++	wl_iw_handle_scanresults_ies(&event, end, info, bi);
++
++	/* Encryption */
++	iwe.cmd = SIOCGIWENCODE;
++	if (dtoh16(bi->capability) & DOT11_CAP_PRIVACY)
++		iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
++	else
++		iwe.u.data.flags = IW_ENCODE_DISABLED;
++	iwe.u.data.length = 0;
++	event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, (char *)event);
++
++	/* Rates */
++	if (bi->rateset.count <= sizeof(bi->rateset.rates)) {
++		if (event + IW_MAX_BITRATES*IW_EV_PARAM_LEN >= end) {
++			err = -E2BIG;
++			goto exit;
++		}
++		value = event + IW_EV_LCP_LEN;
++		iwe.cmd = SIOCGIWRATE;
++		/* Those two flags are ignored... */
++		iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0;
++		for (j = 0; j < bi->rateset.count && j < IW_MAX_BITRATES; j++) {
++			iwe.u.bitrate.value = (bi->rateset.rates[j] & 0x7f) * 500000;
++			value = IWE_STREAM_ADD_VALUE(info, event, value, end, &iwe,
++				IW_EV_PARAM_LEN);
++		}
++		event = value;
++	}
++	*len = event - extra;
++	if (*len < 0)
++		ESCAN_ERROR(dev->name, "==> Wrong size\n");
++
++exit:
++	return err;
++}
++
++int
++wl_escan_get_scan(struct net_device *dev, dhd_pub_t *dhdp,
++	struct iw_request_info *info, struct iw_point *dwrq, char *extra)
++{
++	struct wl_escan_info *escan = dhdp->escan;
++	s32 err = BCME_OK;
++	int i = 0;
++	int len_prep = 0, len_ret = 0;
++	wl_bss_info_t *bi = NULL;
++	struct wl_scan_results *bss_list;
++	__u16 buflen_from_user = dwrq->length;
++#if defined(BSSCACHE)
++	wl_bss_cache_t *node;
++#endif
++	char *buf = NULL;
++	struct ether_addr cur_bssid;
++	u8 ioctl_buf[WLC_IOCTL_SMLEN];
++
++	if (!extra) {
++		ESCAN_TRACE(dev->name, "extra is null\n");
++		return -EINVAL;
++	}
++
++	mutex_lock(&escan->usr_sync);
++
++	/* Check for scan in progress */
++	if (escan->escan_state == ESCAN_STATE_SCANING) {
++		ESCAN_DBG(dev->name, "SIOCGIWSCAN GET still scanning\n");
++		err = -EAGAIN;
++		goto exit;
++	}
++	if (!escan->bss_list) {
++		ESCAN_ERROR(dev->name, "scan not ready\n");
++		err = -EAGAIN;
++		goto exit;
++	}
++	if (dev != escan->dev) {
++		ESCAN_ERROR(dev->name, "not my scan from %s\n", escan->dev->name);
++		err = -EINVAL;
++		goto exit;
++	}
++
++	ESCAN_SCAN(dev->name, "SIOCGIWSCAN, len=%d\n", dwrq->length);
++
++	wldev_iovar_getbuf(dev, "cur_etheraddr", NULL, 0, ioctl_buf, WLC_IOCTL_SMLEN, NULL);
++	err = wldev_ioctl(dev, WLC_GET_BSSID, &cur_bssid, sizeof(cur_bssid), false);
++	if (err != BCME_NOTASSOCIATED &&
++			memcmp(&ether_null, &cur_bssid, ETHER_ADDR_LEN) &&
++			memcmp(ioctl_buf, &cur_bssid, ETHER_ADDR_LEN)) {
++		// merge current connected bss
++		buf = kzalloc(WL_EXTRA_BUF_MAX, GFP_ATOMIC);
++		if (!buf) {
++			ESCAN_ERROR(dev->name, "buffer alloc failed.\n");
++			err = BCME_NOMEM;
++			goto exit;
++		}
++		*(u32 *)buf = htod32(WL_EXTRA_BUF_MAX);
++		err = wldev_ioctl(dev, WLC_GET_BSS_INFO, buf, WL_EXTRA_BUF_MAX, false);
++		if (unlikely(err)) {
++			ESCAN_ERROR(dev->name, "Could not get bss info %d\n", err);
++			goto exit;
++		}
++		bi = (struct wl_bss_info *)(buf + 4);
++		len_prep = 0;
++		err = wl_escan_merge_scan_results(dev, escan, info, extra+len_ret, bi,
++			&len_prep, buflen_from_user-len_ret);
++		len_ret += len_prep;
++		if (err)
++			goto exit;
++		bi = NULL;
++	}
++
++#if defined(BSSCACHE)
++	bss_list = &escan->g_bss_cache_ctrl.m_cache_head->results;
++	node = escan->g_bss_cache_ctrl.m_cache_head;
++	for (i=0; node && i<IW_MAX_AP; i++)
++#else
++	bss_list = escan->bss_list;
++	bi = next_bss(bss_list, bi);
++	for_each_bss(bss_list, bi, i)
++#endif
++	{
++#if defined(BSSCACHE)
++		bi = node->results.bss_info;
++#endif
++		if (!memcmp(&bi->BSSID, &cur_bssid, ETHER_ADDR_LEN)) {
++			ESCAN_SCAN(dev->name, "skip connected AP %pM\n", &cur_bssid);
++#if defined(BSSCACHE)
++			node = node->next;
++#endif
++			continue;
++		}
++		len_prep = 0;
++		err = wl_escan_merge_scan_results(dev, escan, info, extra+len_ret, bi,
++			&len_prep, buflen_from_user-len_ret);
++		len_ret += len_prep;
++		if (err)
++			goto exit;
++#if defined(BSSCACHE)
++		node = node->next;
++#endif
++	}
++
++	if ((len_ret + WE_ADD_EVENT_FIX) < dwrq->length)
++		dwrq->length = len_ret;
++
++	dwrq->flags = 0;	/* todo */
++	ESCAN_SCAN(dev->name, "scanned AP count (%d)\n", i);
++exit:
++	kfree(buf);
++	dwrq->length = len_ret;
++	mutex_unlock(&escan->usr_sync);
++	return err;
++}
++#endif /* WL_WIRELESS_EXT */
++
++#ifdef WLMESH
++bool
++wl_escan_meshid_ie(u8 *parse, u32 len, wlc_ssid_t *mesh_id)
++{
++	bcm_tlv_t *ie;
++
++	if((ie = bcm_parse_tlvs(parse, (int)len, DOT11_MNG_MESH_ID)) != NULL) {
++		mesh_id->SSID_len = ie->len;
++		if (ie->len) {
++			strncpy(mesh_id->SSID, ie->data, ie->len);
++		}
++		return TRUE;
++	}
++	return FALSE;
++}
++
++bool
++wl_escan_rsn_ie(u8 *parse, u32 len)
++{
++	if (bcm_parse_tlvs(parse, (u32)len, DOT11_MNG_RSN_ID)) {
++		return TRUE;
++	}
++	return FALSE;
++}
++
++void
++wl_escan_mesh_info_ie(u8 *parse, u32 len, struct wl_mesh_params *mesh_info)
++{
++	bcm_tlv_t *ie;
++	uchar mesh_oui[]={0x00, 0x22, 0xf4};
++	int totl_len;
++	uint8 *pie;
++
++	if((ie = bcm_parse_tlvs(parse, (int)len, DOT11_MNG_VS_ID)) != NULL) {
++		totl_len = ie->len;
++		if (!memcmp(ie->data, &mesh_oui, sizeof(mesh_oui))) {
++			pie = ie->data + sizeof(mesh_oui);
++			ie = (bcm_tlv_t *)pie;
++			totl_len -= sizeof(mesh_oui);
++			while (totl_len > 2 && ie->len) {
++				if (ie->id == MESH_INFO_MASTER_BSSID && ie->len == ETHER_ADDR_LEN) {
++					memcpy(&mesh_info->master_bssid, ie->data, ETHER_ADDR_LEN);
++				} else if (ie->id == MESH_INFO_MASTER_CHANNEL) {
++					mesh_info->master_channel = ie->data[0];
++				} else if (ie->id == MESH_INFO_HOP_CNT) {
++					mesh_info->hop_cnt = ie->data[0];
++				} else if (ie->id == MESH_INFO_PEER_BSSID) {
++					memcpy(&mesh_info->peer_bssid, ie->data, ETHER_ADDR_LEN);
++				}
++				totl_len -= (ie->len + 2);
++				pie = ie->data + ie->len;
++				ie = (bcm_tlv_t *)pie;
++			}
++		}
++	}
++}
++
++int
++wl_escan_mesh_info(struct net_device *dev, struct wl_escan_info *escan, 
++	struct ether_addr *peer_bssid, struct wl_mesh_params *mesh_info)
++{
++	s32 err = BCME_OK;
++	int i = 0;
++	wl_bss_info_t *bi = NULL;
++	struct wl_scan_results *bss_list;
++	int16 bi_rssi, bi_chan;
++	wlc_ssid_t bi_meshid;
++	bool is_mesh_peer = FALSE;
++	struct wl_mesh_params peer_mesh_info;
++
++	mutex_lock(&escan->usr_sync);
++
++	/* Check for scan in progress */
++	if (escan->escan_state == ESCAN_STATE_SCANING) {
++		ESCAN_ERROR(dev->name, "SIOCGIWSCAN GET still scanning\n");
++		err = -EAGAIN;
++		goto exit;
++	}
++	if (!escan->bss_list) {
++		ESCAN_ERROR(dev->name, "scan not ready\n");
++		err = -EAGAIN;
++		goto exit;
++	}
++	if (dev != escan->dev) {
++		ESCAN_ERROR(dev->name, "not my scan from %s\n", escan->dev->name);
++		err = -EINVAL;
++		goto exit;
++	}
++
++	bss_list = escan->bss_list;
++	bi = next_bss(bss_list, bi);
++	ESCAN_SCAN(dev->name, "scanned AP/Mesh count (%d)\n", bss_list->count);
++	for_each_bss(bss_list, bi, i)
++	{
++		memset(&bi_meshid, 0, sizeof(bi_meshid));
++		is_mesh_peer = FALSE;
++		bi_chan = wf_chspec_ctlchan(
++			wl_chspec_driver_to_host(escan->ioctl_ver, bi->chanspec));
++		bi_rssi = MIN(dtoh16(bi->RSSI), RSSI_MAXVAL);
++		is_mesh_peer = wl_escan_meshid_ie(((u8*)bi)+bi->ie_offset,
++			bi->ie_length, &bi_meshid);
++		if (!(bi->capability & (DOT11_CAP_ESS|DOT11_CAP_IBSS)) && is_mesh_peer) {
++			bool bi_sae = FALSE, bss_found = FALSE;
++			if (!memcmp(peer_bssid, &bi->BSSID, ETHER_ADDR_LEN)) {
++				bi_sae = wl_escan_rsn_ie(((u8*)bi)+bi->ie_offset, bi->ie_length);
++				memset(&peer_mesh_info, 0, sizeof(peer_mesh_info));
++				wl_escan_mesh_info_ie(((u8*)bi)+bi->ie_offset, bi->ie_length,
++					&peer_mesh_info);
++				if (peer_mesh_info.hop_cnt) {
++					memcpy(&mesh_info->master_bssid, &peer_mesh_info.master_bssid,
++						ETHER_ADDR_LEN);
++					mesh_info->master_channel = peer_mesh_info.master_channel;
++					mesh_info->hop_cnt = peer_mesh_info.hop_cnt;
++					memcpy(&mesh_info->peer_bssid, &peer_mesh_info.peer_bssid,
++						ETHER_ADDR_LEN);
++					mesh_info->channel = bi_chan;
++					bss_found = TRUE;
++				}
++			}
++			ESCAN_SCAN(dev->name,
++				"%s[Mesh] BSSID=%pM, channel=%d, RSSI=%d, sec=%s, "
++				"mbssid=%pM, mchannel=%d, hop=%d, pbssid=%pM, MeshID=\"%s\"\n",
++				bss_found?"*":" ", &bi->BSSID, bi_chan, bi_rssi, bi_sae?"SAE":"OPEN",
++				&peer_mesh_info.master_bssid, peer_mesh_info.master_channel,
++				peer_mesh_info.hop_cnt, &peer_mesh_info.peer_bssid, bi_meshid.SSID);
++		}
++	}
++
++exit:
++	mutex_unlock(&escan->usr_sync);
++	return err;
++}
++
++int
++wl_escan_mesh_peer(struct net_device *dev, struct wl_escan_info *escan, 
++	wlc_ssid_t *cur_ssid, uint16 cur_chan, bool sae,
++	struct wl_mesh_params *mesh_info)
++{
++	s32 err = BCME_OK;
++	int i = 0;
++	wl_bss_info_t *bi = NULL;
++	struct wl_scan_results *bss_list;
++	int16 bi_rssi, bi_chan, max_rssi = -100;
++	uint min_hop_cnt = 255;
++	wlc_ssid_t bi_meshid;
++	bool is_mesh_peer = FALSE, chan_matched = FALSE;
++	struct wl_mesh_params peer_mesh_info;
++
++	mutex_lock(&escan->usr_sync);
++
++	/* Check for scan in progress */
++	if (escan->escan_state == ESCAN_STATE_SCANING) {
++		ESCAN_ERROR(dev->name, "SIOCGIWSCAN GET still scanning\n");
++		err = -EAGAIN;
++		goto exit;
++	}
++	if (!escan->bss_list) {
++		ESCAN_ERROR(dev->name, "scan not ready\n");
++		err = -EAGAIN;
++		goto exit;
++	}
++	if (dev != escan->dev) {
++		ESCAN_ERROR(dev->name, "not my scan from %s\n", escan->dev->name);
++		err = -EINVAL;
++		goto exit;
++	}
++
++	bss_list = escan->bss_list;
++	bi = next_bss(bss_list, bi);
++	ESCAN_SCAN(dev->name, "scanned AP/Mesh count (%d)\n", bss_list->count);
++	for_each_bss(bss_list, bi, i)
++	{
++		memset(&bi_meshid, 0, sizeof(bi_meshid));
++		is_mesh_peer = FALSE;
++		bi_chan = wf_chspec_ctlchan(
++			wl_chspec_driver_to_host(escan->ioctl_ver, bi->chanspec));
++		bi_rssi = MIN(dtoh16(bi->RSSI), RSSI_MAXVAL);
++		is_mesh_peer = wl_escan_meshid_ie(((u8*)bi)+bi->ie_offset,
++			bi->ie_length, &bi_meshid);
++		if (!(bi->capability & (DOT11_CAP_ESS|DOT11_CAP_IBSS)) && is_mesh_peer) {
++			bool meshid_matched = FALSE, sec_matched = FALSE, bi_sae = FALSE,
++				bss_found = FALSE;
++
++			if (cur_ssid->SSID_len && cur_ssid->SSID_len == bi_meshid.SSID_len &&
++					!memcmp(cur_ssid->SSID, bi_meshid.SSID, bi_meshid.SSID_len))
++				meshid_matched = TRUE;
++
++			bi_sae = wl_escan_rsn_ie(((u8*)bi)+bi->ie_offset, bi->ie_length);
++			if (bi_sae == sae)
++				sec_matched = TRUE;
++
++			memset(&peer_mesh_info, 0, sizeof(peer_mesh_info));
++			wl_escan_mesh_info_ie(((u8*)bi)+bi->ie_offset, bi->ie_length,
++				&peer_mesh_info);
++
++			if (meshid_matched && sec_matched && peer_mesh_info.hop_cnt &&
++					(cur_chan == bi_chan)) {
++				if (peer_mesh_info.hop_cnt < min_hop_cnt) {
++					memcpy(&mesh_info->master_bssid, &peer_mesh_info.master_bssid,
++						ETHER_ADDR_LEN);
++					mesh_info->master_channel = peer_mesh_info.master_channel;
++					mesh_info->hop_cnt = peer_mesh_info.hop_cnt;
++					memcpy(&mesh_info->peer_bssid, &peer_mesh_info.peer_bssid,
++						ETHER_ADDR_LEN);
++					mesh_info->channel = bi_chan;
++					min_hop_cnt = peer_mesh_info.hop_cnt;
++					bss_found = TRUE;
++					chan_matched = TRUE;
++				}
++			} else if (meshid_matched && sec_matched && peer_mesh_info.hop_cnt &&
++					(cur_chan != bi_chan) && !chan_matched) {
++				if (bi_rssi > max_rssi) {
++					memcpy(&mesh_info->master_bssid, &peer_mesh_info.master_bssid,
++						ETHER_ADDR_LEN);
++					mesh_info->master_channel = peer_mesh_info.master_channel;
++					mesh_info->hop_cnt = peer_mesh_info.hop_cnt;
++					memcpy(&mesh_info->peer_bssid, &peer_mesh_info.peer_bssid,
++						ETHER_ADDR_LEN);
++					mesh_info->channel = bi_chan;
++					max_rssi = bi_rssi;
++					bss_found = TRUE;
++				}
++			}
++
++			ESCAN_SCAN(dev->name,
++				"%s[Mesh] BSSID=%pM, channel=%d, RSSI=%d, sec=%s, "
++				"mbssid=%pM, mchannel=%d, hop=%d, pbssid=%pM, MeshID=\"%s\"\n",
++				bss_found?"*":" ", &bi->BSSID, bi_chan, bi_rssi, bi_sae?"SAE":"OPEN",
++				&peer_mesh_info.master_bssid, peer_mesh_info.master_channel,
++				peer_mesh_info.hop_cnt, &peer_mesh_info.peer_bssid, bi_meshid.SSID);
++		} else {
++			ESCAN_SCAN(dev->name,
++				"[AP] BSSID=%pM, channel=%d, RSSI=%d, SSID=\"%s\"\n",
++				&bi->BSSID, bi_chan, bi_rssi, bi->SSID);
++		}
++	}
++
++exit:
++	mutex_unlock(&escan->usr_sync);
++	return err;
++}
++#endif /* WLMESH */
++
++static void
++wl_escan_deinit(struct net_device *dev, struct wl_escan_info *escan)
++{
++	ESCAN_TRACE(dev->name, "Enter\n");
++
++	_del_timer_sync(&escan->scan_timeout);
++	escan->escan_state = ESCAN_STATE_DOWN;
++
++#if defined(RSSIAVG)
++	wl_free_rssi_cache(&escan->g_rssi_cache_ctrl);
++#endif
++#if defined(BSSCACHE)
++	wl_free_bss_cache(&escan->g_bss_cache_ctrl);
++#endif
++}
++
++static s32
++wl_escan_init(struct net_device *dev, struct wl_escan_info *escan)
++{
++	ESCAN_TRACE(dev->name, "Enter\n");
++
++	/* Init scan_timeout timer */
++	init_timer_compat(&escan->scan_timeout, wl_escan_timeout, escan);
++	escan->escan_state = ESCAN_STATE_IDLE;
++
++	return 0;
++}
++
++void
++wl_escan_down(struct net_device *dev, dhd_pub_t *dhdp)
++{
++	struct wl_escan_info *escan = dhdp->escan;
++
++	ESCAN_TRACE(dev->name, "Enter\n");
++	if (!escan) {
++		ESCAN_ERROR(dev->name, "escan is NULL\n");
++		return;
++	}
++
++	wl_escan_deinit(dev, escan);
++}
++
++int
++wl_escan_up(struct net_device *dev, dhd_pub_t *dhdp)
++{
++	struct wl_escan_info *escan = dhdp->escan;
++	s32 val = 0;
++	int ret = -1;
++
++	ESCAN_TRACE(dev->name, "Enter\n");
++	if (!escan) {
++		ESCAN_ERROR(dev->name, "escan is NULL\n");
++		return ret;
++	}
++
++	ret = wl_escan_init(dev, escan);
++	if (ret) {
++		ESCAN_ERROR(dev->name, "wl_escan_init ret %d\n", ret);
++		return ret;
++	}
++
++	if (!escan->ioctl_ver) {
++		val = 1;
++		if ((ret = wldev_ioctl(dev, WLC_GET_VERSION, &val, sizeof(int), false) < 0)) {
++			ESCAN_ERROR(dev->name, "WLC_GET_VERSION failed, ret=%d\n", ret);
++			return ret;
++		}
++		val = dtoh32(val);
++		if (val != WLC_IOCTL_VERSION && val != 1) {
++			ESCAN_ERROR(dev->name,
++				"Version mismatch, please upgrade. Got %d, expected %d or 1\n",
++				val, WLC_IOCTL_VERSION);
++			return ret;
++		}
++		escan->ioctl_ver = val;
++	}
++
++	return 0;
++}
++
++int
++wl_escan_event_dettach(struct net_device *dev, dhd_pub_t *dhdp)
++{
++	struct wl_escan_info *escan = dhdp->escan;
++	int ret = -1;
++
++	if (!escan) {
++		ESCAN_ERROR(dev->name, "escan is NULL\n");
++		return ret;
++	}
++
++	wl_ext_event_deregister(dev, dhdp, WLC_E_ESCAN_RESULT, wl_escan_handler);
++
++	return 0;
++}
++
++int
++wl_escan_event_attach(struct net_device *dev, dhd_pub_t *dhdp)
++{
++	struct wl_escan_info *escan = dhdp->escan;
++	int ret = -1;
++
++	if (!escan) {
++		ESCAN_ERROR(dev->name, "escan is NULL\n");
++		return ret;
++	}
++
++	ret = wl_ext_event_register(dev, dhdp, WLC_E_ESCAN_RESULT, wl_escan_handler,
++		escan, PRIO_EVENT_ESCAN);
++	if (ret) {
++		ESCAN_ERROR(dev->name, "wl_ext_event_register err %d\n", ret);
++	}
++
++	return ret;
++}
++
++void
++wl_escan_detach(struct net_device *dev, dhd_pub_t *dhdp)
++{
++	struct wl_escan_info *escan = dhdp->escan;
++
++	ESCAN_TRACE(dev->name, "Enter\n");
++
++	if (!escan)
++		return;
++
++	wl_escan_deinit(dev, escan);
++	if (escan->escan_ioctl_buf) {
++		kfree(escan->escan_ioctl_buf);
++		escan->escan_ioctl_buf = NULL;
++	}
++	wl_ext_event_deregister(dev, dhdp, WLC_E_ESCAN_RESULT, wl_escan_handler);
++
++	DHD_OS_PREFREE(dhdp, escan, sizeof(struct wl_escan_info));
++	dhdp->escan = NULL;
++}
++
++int
++wl_escan_attach(struct net_device *dev, dhd_pub_t *dhdp)
++{
++	struct wl_escan_info *escan = NULL;
++	int ret = 0;
++
++	ESCAN_TRACE(dev->name, "Enter\n");
++
++	escan = (struct wl_escan_info *)DHD_OS_PREALLOC(dhdp,
++		DHD_PREALLOC_WL_ESCAN, sizeof(struct wl_escan_info));
++	if (!escan)
++		return -ENOMEM;
++	memset(escan, 0, sizeof(struct wl_escan_info));
++
++	dhdp->escan = escan;
++
++	/* we only care about main interface so save a global here */
++	escan->pub = dhdp;
++	escan->escan_state = ESCAN_STATE_DOWN;
++
++	escan->escan_ioctl_buf = (void *)kzalloc(WLC_IOCTL_MAXLEN, GFP_KERNEL);
++	if (unlikely(!escan->escan_ioctl_buf)) {
++		ESCAN_ERROR(dev->name, "Ioctl buf alloc failed\n");
++		ret = -ENOMEM;
++		goto exit;
++	}
++	ret = wl_escan_init(dev, escan);
++	if (ret) {
++		ESCAN_ERROR(dev->name, "wl_escan_init err %d\n", ret);
++		goto exit;
++	}
++	mutex_init(&escan->usr_sync);
++
++	return 0;
++
++exit:
++	wl_escan_detach(dev, dhdp);
++	return ret;
++}
++
++#endif /* WL_ESCAN */
++
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_escan.h b/module_drivers/drivers/net/wireless/bcmdhd/wl_escan.h
+new file mode 100644
+index 000000000..9c32da58b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_escan.h
+@@ -0,0 +1,78 @@
++
++#ifndef _wl_escan_
++#define _wl_escan_
++#include <linuxver.h>
++#include <wl_iw.h>
++
++#define ESCAN_BUF_SIZE (64 * 1024)
++
++#define WL_ESCAN_TIMER_INTERVAL_MS	10000 /* Scan timeout */
++
++/* donlge escan state */
++enum escan_state {
++	ESCAN_STATE_DOWN,
++	ESCAN_STATE_IDLE,
++	ESCAN_STATE_SCANING
++};
++
++typedef struct wl_escan_info {
++	struct net_device *dev;
++	dhd_pub_t *pub;
++	timer_list_compat_t scan_timeout;   /* Timer for catch scan event timeout */
++	int escan_state;
++	int ioctl_ver;
++	u8 escan_buf[ESCAN_BUF_SIZE];
++	struct wl_scan_results *bss_list;
++	struct ether_addr disconnected_bssid;
++	u8 *escan_ioctl_buf;
++	struct mutex usr_sync;	/* maily for up/down synchronization */
++	int autochannel;
++	int best_2g_ch;
++	int best_5g_ch;
++#if defined(RSSIAVG)
++	wl_rssi_cache_ctrl_t g_rssi_cache_ctrl;
++	wl_rssi_cache_ctrl_t g_connected_rssi_cache_ctrl;
++#endif
++#if defined(BSSCACHE)
++	wl_bss_cache_ctrl_t g_bss_cache_ctrl;
++#endif
++} wl_escan_info_t;
++
++#if defined(WLMESH)
++/* donlge escan state */
++enum mesh_info_id {
++	MESH_INFO_MASTER_BSSID = 1,
++	MESH_INFO_MASTER_CHANNEL,
++	MESH_INFO_HOP_CNT,
++	MESH_INFO_PEER_BSSID
++};
++
++typedef struct wl_mesh_params {
++	struct ether_addr master_bssid;
++	uint16 master_channel;
++	uint hop_cnt;
++	struct ether_addr peer_bssid;
++	uint16 channel;
++	uint16 scan_channel;
++} wl_mesh_params_t;
++int wl_escan_mesh_info(struct net_device *dev,
++	struct wl_escan_info *escan, struct ether_addr *peer_bssid,
++	struct wl_mesh_params *mesh_info);
++int wl_escan_mesh_peer(struct net_device *dev,
++	struct wl_escan_info *escan, wlc_ssid_t *cur_ssid, uint16 cur_chan, bool sae,
++	struct wl_mesh_params *mesh_info);
++#endif /* WLMESH */
++
++int wl_escan_set_scan(struct net_device *dev, dhd_pub_t *dhdp,
++	wlc_ssid_t *ssid, uint16 channel, bool bcast);
++int wl_escan_get_scan(struct net_device *dev, dhd_pub_t *dhdp,
++	struct iw_request_info *info, struct iw_point *dwrq, char *extra);
++int wl_escan_attach(struct net_device *dev, dhd_pub_t *dhdp);
++void wl_escan_detach(struct net_device *dev, dhd_pub_t *dhdp);
++int wl_escan_event_attach(struct net_device *dev, dhd_pub_t *dhdp);
++int wl_escan_event_dettach(struct net_device *dev, dhd_pub_t *dhdp);
++int wl_escan_up(struct net_device *dev, dhd_pub_t *dhdp);
++void wl_escan_down(struct net_device *dev, dhd_pub_t *dhdp);
++
++#endif /* _wl_escan_ */
++
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_event.c b/module_drivers/drivers/net/wireless/bcmdhd/wl_event.c
+new file mode 100644
+index 000000000..8b85aa69f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_event.c
+@@ -0,0 +1,557 @@
++
++#if defined(WL_EXT_IAPSTA) || defined(USE_IW)
++#include <bcmendian.h>
++#include <wl_android.h>
++#include <dhd_config.h>
++
++#define EVENT_ERROR(name, arg1, args...) \
++	do { \
++		if (android_msg_level & ANDROID_ERROR_LEVEL) { \
++			printk(KERN_ERR "[dhd-%s] EVENT-ERROR) %s : " arg1, name, __func__, ## args); \
++		} \
++	} while (0)
++#define EVENT_TRACE(name, arg1, args...) \
++	do { \
++		if (android_msg_level & ANDROID_TRACE_LEVEL) { \
++			printk(KERN_INFO "[dhd-%s] EVENT-TRACE) %s : " arg1, name, __func__, ## args); \
++		} \
++	} while (0)
++#define EVENT_DBG(name, arg1, args...) \
++	do { \
++		if (android_msg_level & ANDROID_DBG_LEVEL) { \
++			printk(KERN_INFO "[dhd-%s] EVENT-DBG) %s : " arg1, name, __func__, ## args); \
++		} \
++	} while (0)
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++#define BCM_SET_LIST_FIRST_ENTRY(entry, ptr, type, member) \
++_Pragma("GCC diagnostic push") \
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"") \
++(entry) = list_first_entry((ptr), type, member); \
++_Pragma("GCC diagnostic pop") \
++
++#define BCM_SET_CONTAINER_OF(entry, ptr, type, member) \
++_Pragma("GCC diagnostic push") \
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"") \
++entry = container_of((ptr), type, member); \
++_Pragma("GCC diagnostic pop") \
++
++#else
++#define BCM_SET_LIST_FIRST_ENTRY(entry, ptr, type, member) \
++(entry) = list_first_entry((ptr), type, member); \
++
++#define BCM_SET_CONTAINER_OF(entry, ptr, type, member) \
++entry = container_of((ptr), type, member); \
++
++#endif /* STRICT_GCC_WARNINGS */
++
++#ifdef DHD_MAX_IFS
++#define WL_MAX_IFS DHD_MAX_IFS
++#else
++#define WL_MAX_IFS 16
++#endif
++
++/* event queue for cfg80211 main event */
++struct wl_event_q {
++	struct list_head eq_list;
++	u32 etype;
++	wl_event_msg_t emsg;
++	s8 edata[1];
++};
++
++typedef s32(*EXT_EVENT_HANDLER) (struct net_device *dev, void *cb_argu,
++	const wl_event_msg_t *e, void *data);
++
++typedef struct event_handler_list {
++	struct event_handler_list *next;
++	struct net_device *dev;
++	uint32 etype;
++	EXT_EVENT_HANDLER cb_func;
++	void *cb_argu;
++	wl_event_prio_t prio;
++} event_handler_list_t;
++
++typedef struct event_handler_head {
++	event_handler_list_t *evt_head;
++} event_handler_head_t;
++
++typedef struct wl_event_params {
++	dhd_pub_t *pub;
++	struct net_device *dev[WL_MAX_IFS];
++	struct event_handler_head evt_head;
++	struct list_head eq_list;	/* used for event queue */
++	spinlock_t eq_lock;	/* for event queue synchronization */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 0, 0))
++	tsk_ctl_t thr_event_ctl;
++#else
++	struct workqueue_struct *event_workq;   /* workqueue for event */
++	struct work_struct event_work;		/* work item for event */
++#endif
++	struct mutex event_sync;
++} wl_event_params_t;
++
++static unsigned long
++wl_ext_event_lock_eq(struct wl_event_params *event_params)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&event_params->eq_lock, flags);
++	return flags;
++}
++
++static void
++wl_ext_event_unlock_eq(struct wl_event_params *event_params, unsigned long flags)
++{
++	spin_unlock_irqrestore(&event_params->eq_lock, flags);
++}
++
++static void
++wl_ext_event_init_eq_lock(struct wl_event_params *event_params)
++{
++	spin_lock_init(&event_params->eq_lock);
++}
++
++static void
++wl_ext_event_init_eq(struct wl_event_params *event_params)
++{
++	wl_ext_event_init_eq_lock(event_params);
++	INIT_LIST_HEAD(&event_params->eq_list);
++}
++
++static void
++wl_ext_event_flush_eq(struct wl_event_params *event_params)
++{
++	struct wl_event_q *e;
++	unsigned long flags;
++
++	flags = wl_ext_event_lock_eq(event_params);
++	while (!list_empty_careful(&event_params->eq_list)) {
++		BCM_SET_LIST_FIRST_ENTRY(e, &event_params->eq_list, struct wl_event_q, eq_list);
++		list_del(&e->eq_list);
++		kfree(e);
++	}
++	wl_ext_event_unlock_eq(event_params, flags);
++}
++
++/*
++* retrieve first queued event from head
++*/
++
++static struct wl_event_q *
++wl_ext_event_deq_event(struct wl_event_params *event_params)
++{
++	struct wl_event_q *e = NULL;
++	unsigned long flags;
++
++	flags = wl_ext_event_lock_eq(event_params);
++	if (likely(!list_empty(&event_params->eq_list))) {
++		BCM_SET_LIST_FIRST_ENTRY(e, &event_params->eq_list, struct wl_event_q, eq_list);
++		list_del(&e->eq_list);
++	}
++	wl_ext_event_unlock_eq(event_params, flags);
++
++	return e;
++}
++
++/*
++ * push event to tail of the queue
++ */
++
++static s32
++wl_ext_event_enq_event(struct wl_event_params *event_params, u32 event,
++	const wl_event_msg_t *msg, void *data)
++{
++	struct wl_event_q *e;
++	s32 err = 0;
++	uint32 evtq_size;
++	uint32 data_len;
++	unsigned long flags;
++	gfp_t aflags;
++
++	data_len = 0;
++	if (data)
++		data_len = ntoh32(msg->datalen);
++	evtq_size = sizeof(struct wl_event_q) + data_len;
++	aflags = (in_atomic()) ? GFP_ATOMIC : GFP_KERNEL;
++	e = kzalloc(evtq_size, aflags);
++	if (unlikely(!e)) {
++		EVENT_ERROR("wlan", "event alloc failed\n");
++		return -ENOMEM;
++	}
++	e->etype = event;
++	memcpy(&e->emsg, msg, sizeof(wl_event_msg_t));
++	if (data)
++		memcpy(e->edata, data, data_len);
++	flags = wl_ext_event_lock_eq(event_params);
++	list_add_tail(&e->eq_list, &event_params->eq_list);
++	wl_ext_event_unlock_eq(event_params, flags);
++
++	return err;
++}
++
++static void
++wl_ext_event_put_event(struct wl_event_q *e)
++{
++	kfree(e);
++}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 0, 0))
++static int wl_ext_event_handler(void *data);
++#define WL_EXT_EVENT_HANDLER() static int wl_ext_event_handler(void *data)
++#else
++static void wl_ext_event_handler(struct work_struct *data);
++#define WL_EXT_EVENT_HANDLER() static void wl_ext_event_handler(struct work_struct *data)
++#endif
++
++WL_EXT_EVENT_HANDLER()
++{
++	struct wl_event_params *event_params = NULL;
++	struct wl_event_q *e;
++	struct net_device *dev = NULL;
++	struct event_handler_list *evt_node;
++	dhd_pub_t *dhd;
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 0, 0))
++	tsk_ctl_t *tsk = (tsk_ctl_t *)data;
++	event_params = (struct wl_event_params *)tsk->parent;
++#else
++	BCM_SET_CONTAINER_OF(event_params, data, struct wl_event_params, event_work);
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 0, 0))
++	while (1) {
++	if (down_interruptible(&tsk->sema) == 0) {
++		SMP_RD_BARRIER_DEPENDS();
++		if (tsk->terminated) {
++			break;
++		}
++#endif
++	DHD_EVENT_WAKE_LOCK(event_params->pub);
++	while ((e = wl_ext_event_deq_event(event_params))) {
++		if (e->emsg.ifidx >= DHD_MAX_IFS) {
++			EVENT_ERROR("wlan", "ifidx=%d not in range\n", e->emsg.ifidx);
++			goto fail;
++		}
++		dev = event_params->dev[e->emsg.ifidx];
++		if (!dev) {
++			EVENT_DBG("wlan", "ifidx=%d dev not ready\n", e->emsg.ifidx);
++			goto fail;
++		}
++		dhd = dhd_get_pub(dev);
++		if (e->etype > WLC_E_LAST) {
++			EVENT_TRACE(dev->name, "Unknown Event (%d): ignoring\n", e->etype);
++			goto fail;
++		}
++		if (dhd->busstate == DHD_BUS_DOWN) {
++			EVENT_ERROR(dev->name, "BUS is DOWN.\n");
++			goto fail;
++		}
++		EVENT_DBG(dev->name, "event type (%d)\n", e->etype);
++		mutex_lock(&event_params->event_sync);
++		evt_node = event_params->evt_head.evt_head;
++		for (;evt_node;) {
++			if (evt_node->dev == dev &&
++					(evt_node->etype == e->etype || evt_node->etype == WLC_E_LAST))
++				evt_node->cb_func(dev, evt_node->cb_argu, &e->emsg, e->edata);
++			evt_node = evt_node->next;
++		}
++		mutex_unlock(&event_params->event_sync);
++fail:
++		wl_ext_event_put_event(e);
++	}
++	DHD_EVENT_WAKE_UNLOCK(event_params->pub);
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 0, 0))
++	} else {
++		break;
++	}
++	}
++	complete_and_exit(&tsk->completed, 0);
++#endif
++}
++
++void
++wl_ext_event_send(void *params, const wl_event_msg_t * e, void *data)
++{
++	struct wl_event_params *event_params = params;
++	u32 event_type = ntoh32(e->event_type);
++
++	if (event_params == NULL) {
++		EVENT_ERROR("wlan", "Stale event %d(%s) ignored\n",
++			event_type, bcmevent_get_name(event_type));
++		return;
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	if (event_params->event_workq == NULL) {
++		EVENT_ERROR("wlan", "Event handler is not created %d(%s)\n",
++			event_type, bcmevent_get_name(event_type));
++		return;
++	}
++#endif
++
++	if (likely(!wl_ext_event_enq_event(event_params, event_type, e, data))) {
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 0, 0))
++		if (event_params->thr_event_ctl.thr_pid >= 0) {
++			up(&event_params->thr_event_ctl.sema);
++		}
++#else
++		queue_work(event_params->event_workq, &event_params->event_work);
++#endif
++	}
++}
++
++static s32
++wl_ext_event_create_handler(struct wl_event_params *event_params)
++{
++	int ret = 0;
++	EVENT_TRACE("wlan", "Enter\n");
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 0, 0))
++	PROC_START(wl_ext_event_handler, event_params, &event_params->thr_event_ctl, 0, "ext_eventd");
++	if (event_params->thr_event_ctl.thr_pid < 0) {
++		ret = -ENOMEM;
++	}
++#else
++	/* Allocate workqueue for event */
++	if (!event_params->event_workq) {
++		event_params->event_workq = alloc_workqueue("ext_eventd", WQ_MEM_RECLAIM | WQ_HIGHPRI, 0);
++	}
++
++	if (!event_params->event_workq) {
++		EVENT_ERROR("wlan", "event_workq alloc_workqueue failed\n");
++		ret = -ENOMEM;
++	} else {
++		INIT_WORK(&event_params->event_work, wl_ext_event_handler);
++	}
++#endif
++
++	return ret;
++}
++
++static void
++wl_ext_event_free(struct wl_event_params *event_params)
++{
++	struct event_handler_list *node, *cur, **evt_head;
++
++	evt_head = &event_params->evt_head.evt_head;
++	node = *evt_head;
++
++	for (;node;) {
++		EVENT_TRACE(node->dev->name, "Free etype=%d\n", node->etype);
++		cur = node;
++		node = cur->next;
++		kfree(cur);
++	}
++	*evt_head = NULL;
++}
++
++static void
++wl_ext_event_destroy_handler(struct wl_event_params *event_params)
++{
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 0, 0))
++	if (event_params->thr_event_ctl.thr_pid >= 0) {
++		PROC_STOP(&event_params->thr_event_ctl);
++	}
++#else
++	if (event_params && event_params->event_workq) {
++		cancel_work_sync(&event_params->event_work);
++		destroy_workqueue(event_params->event_workq);
++		event_params->event_workq = NULL;
++	}
++#endif
++}
++
++int
++wl_ext_event_register(struct net_device *dev, dhd_pub_t *dhd, uint32 event,
++	void *cb_func, void *data, wl_event_prio_t prio)
++{
++	struct wl_event_params *event_params = dhd->event_params;
++	struct event_handler_list *node, *leaf, *node_prev, **evt_head;
++	int ret = 0;
++
++	if (event_params) {
++		mutex_lock(&event_params->event_sync);
++		evt_head = &event_params->evt_head.evt_head;
++		node = *evt_head;
++		for (;node;) {
++			if (node->dev == dev && node->etype == event && node->cb_func == cb_func) {
++				EVENT_TRACE(dev->name, "skip event %d\n", event);
++				mutex_unlock(&event_params->event_sync);
++				return 0;
++			}
++			node = node->next;
++		}
++		leaf = kmalloc(sizeof(event_handler_list_t), GFP_KERNEL);
++		if (!leaf) {
++			EVENT_ERROR(dev->name, "Memory alloc failure %d for event %d\n",
++				(int)sizeof(event_handler_list_t), event);
++			mutex_unlock(&event_params->event_sync);
++			return -ENOMEM;
++		}
++		leaf->next = NULL;
++		leaf->dev = dev;
++		leaf->etype = event;
++		leaf->cb_func = cb_func;
++		leaf->cb_argu = data;
++		leaf->prio = prio;
++		if (*evt_head == NULL) {
++			*evt_head = leaf;
++		} else {
++			node = *evt_head;
++			node_prev = NULL;
++			for (;node;) {
++				if (node->prio <= prio) {
++					leaf->next = node;
++					if (node_prev)
++						node_prev->next = leaf;
++					else
++						*evt_head = leaf;
++					break;
++				} else if (node->next == NULL) {
++					node->next = leaf;
++					break;
++				}
++				node_prev = node;
++				node = node->next;
++			}
++		}
++		EVENT_TRACE(dev->name, "event %d registered\n", event);
++		mutex_unlock(&event_params->event_sync);
++	} else {
++		EVENT_ERROR(dev->name, "event_params not ready %d\n", event);
++		ret = -ENODEV;
++	}
++
++	return ret;
++}
++
++void
++wl_ext_event_deregister(struct net_device *dev, dhd_pub_t *dhd,
++	uint32 event, void *cb_func)
++{
++	struct wl_event_params *event_params = dhd->event_params;
++	struct event_handler_list *node, *prev, **evt_head;
++	int tmp = 0;
++
++	if (event_params) {
++		mutex_lock(&event_params->event_sync);
++		evt_head = &event_params->evt_head.evt_head;
++		node = *evt_head;
++		prev = node;
++		for (;node;) {
++			if (node->dev == dev && node->etype == event && node->cb_func == cb_func) {
++				if (node == *evt_head) {
++					tmp = 1;
++					*evt_head = node->next;
++				} else {
++					tmp = 0;
++					prev->next = node->next;
++				}
++				EVENT_TRACE(dev->name, "event %d deregistered\n", event);
++				kfree(node);
++				if (tmp == 1) {
++					node = *evt_head;
++					prev = node;
++				} else {
++					node = prev->next;
++				}
++				continue;
++			}
++			prev = node;
++			node = node->next;
++		}
++		mutex_unlock(&event_params->event_sync);
++	} else {
++		EVENT_ERROR(dev->name, "event_params not ready %d\n", event);
++	}
++}
++
++static s32
++wl_ext_event_init_priv(struct wl_event_params *event_params)
++{
++	s32 err = 0;
++
++	mutex_init(&event_params->event_sync);
++	wl_ext_event_init_eq(event_params);
++	if (wl_ext_event_create_handler(event_params))
++		return -ENOMEM;
++
++	return err;
++}
++
++static void
++wl_ext_event_deinit_priv(struct wl_event_params *event_params)
++{
++	wl_ext_event_destroy_handler(event_params);
++	wl_ext_event_flush_eq(event_params);
++	wl_ext_event_free(event_params);
++}
++
++int
++wl_ext_event_attach_netdev(struct net_device *net, int ifidx, uint8 bssidx)
++{
++	struct dhd_pub *dhd = dhd_get_pub(net);
++	struct wl_event_params *event_params = dhd->event_params;
++
++	EVENT_TRACE(net->name, "ifidx=%d, bssidx=%d\n", ifidx, bssidx);
++	if (event_params && ifidx < WL_MAX_IFS) {
++		event_params->dev[ifidx] = net;
++	}
++
++	return 0;
++}
++
++int
++wl_ext_event_dettach_netdev(struct net_device *net, int ifidx)
++{
++	struct dhd_pub *dhd = dhd_get_pub(net);
++	struct wl_event_params *event_params = dhd->event_params;
++
++	EVENT_TRACE(net->name, "ifidx=%d\n", ifidx);
++	if (event_params && ifidx < WL_MAX_IFS) {
++		event_params->dev[ifidx] = NULL;
++	}
++
++	return 0;
++}
++
++s32
++wl_ext_event_attach(struct net_device *dev, dhd_pub_t *dhdp)
++{
++	struct wl_event_params *event_params = NULL;
++	s32 err = 0;
++
++	event_params = kmalloc(sizeof(wl_event_params_t), GFP_KERNEL);
++	if (!event_params) {
++		EVENT_ERROR(dev->name, "Failed to allocate memory (%zu)\n",
++			sizeof(wl_event_params_t));
++		return -ENOMEM;
++	}
++	dhdp->event_params = event_params;
++	memset(event_params, 0, sizeof(wl_event_params_t));
++	event_params->pub = dhdp;
++
++	err = wl_ext_event_init_priv(event_params);
++	if (err) {
++		EVENT_ERROR(dev->name, "Failed to wl_ext_event_init_priv (%d)\n", err);
++		goto ext_attach_out;
++	}
++
++	return err;
++ext_attach_out:
++	wl_ext_event_dettach(dhdp);
++	return err;
++}
++
++void
++wl_ext_event_dettach(dhd_pub_t *dhdp)
++{
++	struct wl_event_params *event_params = dhdp->event_params;
++
++	if (event_params) {
++		wl_ext_event_deinit_priv(event_params);
++		kfree(event_params);
++		dhdp->event_params = NULL;
++	}
++}
++#endif
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_iw.c b/module_drivers/drivers/net/wireless/bcmdhd/wl_iw.c
+new file mode 100644
+index 000000000..97f358b01
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_iw.c
+@@ -0,0 +1,4450 @@
++/*
++ * Linux Wireless Extensions support
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_iw.c 616333 2016-02-01 05:30:29Z $
++ */
++
++#if defined(USE_IW)
++#define LINUX_PORT
++
++#include <typedefs.h>
++#include <linuxver.h>
++#include <osl.h>
++
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <ethernet.h>
++
++#include <linux/if_arp.h>
++#include <asm/uaccess.h>
++#include <wlioctl.h>
++#ifdef WL_NAN
++#include <wlioctl_utils.h>
++#endif
++#include <wl_iw.h>
++#include <wl_android.h>
++#ifdef WL_ESCAN
++#include <wl_escan.h>
++#endif
++#include <dhd_config.h>
++
++uint iw_msg_level = WL_ERROR_LEVEL;
++
++#define WL_ERROR_MSG(x, args...) \
++	do { \
++		if (iw_msg_level & WL_ERROR_LEVEL) { \
++			printk(KERN_ERR "[dhd] WEXT-ERROR) %s : " x, __func__, ## args); \
++		} \
++	} while (0)
++#define WL_TRACE_MSG(x, args...) \
++	do { \
++		if (iw_msg_level & WL_TRACE_LEVEL) { \
++			printk(KERN_INFO "[dhd] WEXT-TRACE) %s : " x, __func__, ## args); \
++		} \
++	} while (0)
++#define WL_SCAN_MSG(x, args...) \
++	do { \
++		if (iw_msg_level & WL_SCAN_LEVEL) { \
++			printk(KERN_INFO "[dhd] WEXT-SCAN) %s : " x, __func__, ## args); \
++		} \
++	} while (0)
++#define WL_WSEC_MSG(x, args...) \
++	do { \
++		if (iw_msg_level & WL_WSEC_LEVEL) { \
++			printk(KERN_INFO "[dhd] WEXT-WSEC) %s : " x, __func__, ## args); \
++		} \
++	} while (0)
++#define WL_ERROR(x) WL_ERROR_MSG x
++#define WL_TRACE(x) WL_TRACE_MSG x
++#define WL_SCAN(x) WL_SCAN_MSG x
++#define WL_WSEC(x) WL_WSEC_MSG x
++ 
++#ifdef BCMWAPI_WPI
++/* these items should evetually go into wireless.h of the linux system headfile dir */
++#ifndef IW_ENCODE_ALG_SM4
++#define IW_ENCODE_ALG_SM4 0x20
++#endif
++
++#ifndef IW_AUTH_WAPI_ENABLED
++#define IW_AUTH_WAPI_ENABLED 0x20
++#endif
++
++#ifndef IW_AUTH_WAPI_VERSION_1
++#define IW_AUTH_WAPI_VERSION_1	0x00000008
++#endif
++
++#ifndef IW_AUTH_CIPHER_SMS4
++#define IW_AUTH_CIPHER_SMS4	0x00000020
++#endif
++
++#ifndef IW_AUTH_KEY_MGMT_WAPI_PSK
++#define IW_AUTH_KEY_MGMT_WAPI_PSK 4
++#endif
++
++#ifndef IW_AUTH_KEY_MGMT_WAPI_CERT
++#define IW_AUTH_KEY_MGMT_WAPI_CERT 8
++#endif
++#endif /* BCMWAPI_WPI */
++
++/* Broadcom extensions to WEXT, linux upstream has obsoleted WEXT */
++#ifndef IW_AUTH_KEY_MGMT_FT_802_1X
++#define IW_AUTH_KEY_MGMT_FT_802_1X 0x04
++#endif
++
++#ifndef IW_AUTH_KEY_MGMT_FT_PSK
++#define IW_AUTH_KEY_MGMT_FT_PSK 0x08
++#endif
++
++#ifndef IW_ENC_CAPA_FW_ROAM_ENABLE
++#define IW_ENC_CAPA_FW_ROAM_ENABLE	0x00000020
++#endif
++
++
++/* FC9: wireless.h 2.6.25-14.fc9.i686 is missing these, even though WIRELESS_EXT is set to latest
++ * version 22.
++ */
++#ifndef IW_ENCODE_ALG_PMK
++#define IW_ENCODE_ALG_PMK 4
++#endif
++#ifndef IW_ENC_CAPA_4WAY_HANDSHAKE
++#define IW_ENC_CAPA_4WAY_HANDSHAKE 0x00000010
++#endif
++/* End FC9. */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++#include <linux/rtnetlink.h>
++#endif
++
++extern bool wl_iw_conn_status_str(uint32 event_type, uint32 status,
++	uint32 reason, char* stringBuf, uint buflen);
++
++uint wl_msg_level = WL_ERROR_VAL;
++
++#define MAX_WLIW_IOCTL_LEN WLC_IOCTL_MEDLEN
++
++/* IOCTL swapping mode for Big Endian host with Little Endian dongle.  Default to off */
++#define htod32(i) (i)
++#define htod16(i) (i)
++#define dtoh32(i) (i)
++#define dtoh16(i) (i)
++#define htodchanspec(i) (i)
++#define dtohchanspec(i) (i)
++
++extern struct iw_statistics *dhd_get_wireless_stats(struct net_device *dev);
++extern int dhd_wait_pend8021x(struct net_device *dev);
++
++#if WIRELESS_EXT < 19
++#define IW_IOCTL_IDX(cmd)	((cmd) - SIOCIWFIRST)
++#define IW_EVENT_IDX(cmd)	((cmd) - IWEVFIRST)
++#endif /* WIRELESS_EXT < 19 */
++
++
++#ifndef WL_ESCAN
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++#define DAEMONIZE(a)	do { \
++		allow_signal(SIGKILL);	\
++		allow_signal(SIGTERM);	\
++	} while (0)
++#elif ((LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) && \
++	(LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)))
++#define DAEMONIZE(a) daemonize(a); \
++	allow_signal(SIGKILL); \
++	allow_signal(SIGTERM);
++#else /* Linux 2.4 (w/o preemption patch) */
++#define RAISE_RX_SOFTIRQ() \
++	cpu_raise_softirq(smp_processor_id(), NET_RX_SOFTIRQ)
++#define DAEMONIZE(a) daemonize(); \
++	do { if (a) \
++		strncpy(current->comm, a, MIN(sizeof(current->comm), (strlen(a) + 1))); \
++	} while (0);
++#endif /* LINUX_VERSION_CODE  */
++
++#define ISCAN_STATE_IDLE   0
++#define ISCAN_STATE_SCANING 1
++
++/* the buf lengh can be WLC_IOCTL_MAXLEN (8K) to reduce iteration */
++#define WLC_IW_ISCAN_MAXLEN   2048
++typedef struct iscan_buf {
++	struct iscan_buf * next;
++	char   iscan_buf[WLC_IW_ISCAN_MAXLEN];
++} iscan_buf_t;
++
++typedef struct iscan_info {
++	struct net_device *dev;
++	timer_list_compat_t timer;
++	uint32 timer_ms;
++	uint32 timer_on;
++	int    iscan_state;
++	iscan_buf_t * list_hdr;
++	iscan_buf_t * list_cur;
++
++	/* Thread to work on iscan */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
++	struct task_struct *kthread;
++#endif
++	long sysioc_pid;
++	struct semaphore sysioc_sem;
++	struct completion sysioc_exited;
++	char ioctlbuf[WLC_IOCTL_SMLEN];
++} iscan_info_t;
++static void wl_iw_timerfunc(ulong data);
++static void wl_iw_set_event_mask(struct net_device *dev);
++static int wl_iw_iscan(iscan_info_t *iscan, wlc_ssid_t *ssid, uint16 action);
++#endif /* !WL_ESCAN */
++
++struct pmk_list {
++	pmkid_list_t pmkids;
++	pmkid_t foo[MAXPMKID - 1];
++};
++
++typedef struct wl_wext_info {
++	struct net_device *dev;
++	dhd_pub_t *dhd;
++	struct delayed_work pm_enable_work;
++	struct mutex pm_sync;
++	struct wl_conn_info conn_info;
++	struct pmk_list pmk_list;
++#ifndef WL_ESCAN
++	struct iscan_info iscan;
++#endif
++} wl_wext_info_t;
++
++/* priv_link becomes netdev->priv and is the link between netdev and wlif struct */
++typedef struct priv_link {
++	wl_iw_t *wliw;
++} priv_link_t;
++
++/* dev to priv_link */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
++#define WL_DEV_LINK(dev)       (priv_link_t*)(dev->priv)
++#else
++#define WL_DEV_LINK(dev)       (priv_link_t*)netdev_priv(dev)
++#endif
++
++/* dev to wl_iw_t */
++#define IW_DEV_IF(dev)          ((wl_iw_t*)(WL_DEV_LINK(dev))->wliw)
++
++static void swap_key_from_BE(
++	        wl_wsec_key_t *key
++)
++{
++	key->index = htod32(key->index);
++	key->len = htod32(key->len);
++	key->algo = htod32(key->algo);
++	key->flags = htod32(key->flags);
++	key->rxiv.hi = htod32(key->rxiv.hi);
++	key->rxiv.lo = htod16(key->rxiv.lo);
++	key->iv_initialized = htod32(key->iv_initialized);
++}
++
++static void swap_key_to_BE(
++	        wl_wsec_key_t *key
++)
++{
++	key->index = dtoh32(key->index);
++	key->len = dtoh32(key->len);
++	key->algo = dtoh32(key->algo);
++	key->flags = dtoh32(key->flags);
++	key->rxiv.hi = dtoh32(key->rxiv.hi);
++	key->rxiv.lo = dtoh16(key->rxiv.lo);
++	key->iv_initialized = dtoh32(key->iv_initialized);
++}
++
++static int
++dev_wlc_ioctl(
++	struct net_device *dev,
++	int cmd,
++	void *arg,
++	int len
++)
++{
++	struct ifreq ifr;
++	wl_ioctl_t ioc;
++	mm_segment_t fs;
++	int ret;
++
++	memset(&ioc, 0, sizeof(ioc));
++#ifdef CONFIG_COMPAT
++	ioc.cmd = cmd | WLC_SPEC_FLAG;
++#else
++	ioc.cmd = cmd;
++#endif
++	ioc.buf = arg;
++	ioc.len = len;
++
++	strncpy(ifr.ifr_name, dev->name, sizeof(ifr.ifr_name));
++	ifr.ifr_name[sizeof(ifr.ifr_name) - 1] = '\0';
++	ifr.ifr_data = (caddr_t) &ioc;
++
++	fs = get_fs();
++	set_fs(get_ds());
++#if defined(WL_USE_NETDEV_OPS)
++	ret = dev->netdev_ops->ndo_do_ioctl(dev, &ifr, SIOCDEVPRIVATE);
++#else
++	ret = dev->do_ioctl(dev, &ifr, SIOCDEVPRIVATE);
++#endif
++	set_fs(fs);
++
++	return ret;
++}
++
++/*
++set named driver variable to int value and return error indication
++calling example: dev_wlc_intvar_set(dev, "arate", rate)
++*/
++
++static int
++dev_wlc_intvar_set(
++	struct net_device *dev,
++	char *name,
++	int val)
++{
++	char buf[WLC_IOCTL_SMLEN];
++	uint len;
++
++	val = htod32(val);
++	len = bcm_mkiovar(name, (char *)(&val), sizeof(val), buf, sizeof(buf));
++	ASSERT(len);
++
++	return (dev_wlc_ioctl(dev, WLC_SET_VAR, buf, len));
++}
++
++#ifndef WL_ESCAN
++static int
++dev_iw_iovar_setbuf(
++	struct net_device *dev,
++	char *iovar,
++	void *param,
++	int paramlen,
++	void *bufptr,
++	int buflen)
++{
++	int iolen;
++
++	iolen = bcm_mkiovar(iovar, param, paramlen, bufptr, buflen);
++	ASSERT(iolen);
++	BCM_REFERENCE(iolen);
++
++	return (dev_wlc_ioctl(dev, WLC_SET_VAR, bufptr, iolen));
++}
++
++static int
++dev_iw_iovar_getbuf(
++	struct net_device *dev,
++	char *iovar,
++	void *param,
++	int paramlen,
++	void *bufptr,
++	int buflen)
++{
++	int iolen;
++
++	iolen = bcm_mkiovar(iovar, param, paramlen, bufptr, buflen);
++	ASSERT(iolen);
++	BCM_REFERENCE(iolen);
++
++	return (dev_wlc_ioctl(dev, WLC_GET_VAR, bufptr, buflen));
++}
++#endif
++
++#if WIRELESS_EXT > 17
++static int
++dev_wlc_bufvar_set(
++	struct net_device *dev,
++	char *name,
++	char *buf, int len)
++{
++	char *ioctlbuf;
++	uint buflen;
++	int error;
++
++	ioctlbuf = kmalloc(MAX_WLIW_IOCTL_LEN, GFP_KERNEL);
++	if (!ioctlbuf)
++		return -ENOMEM;
++
++	buflen = bcm_mkiovar(name, buf, len, ioctlbuf, MAX_WLIW_IOCTL_LEN);
++	ASSERT(buflen);
++	error = dev_wlc_ioctl(dev, WLC_SET_VAR, ioctlbuf, buflen);
++
++	kfree(ioctlbuf);
++	return error;
++}
++#endif /* WIRELESS_EXT > 17 */
++
++/*
++get named driver variable to int value and return error indication
++calling example: dev_wlc_bufvar_get(dev, "arate", &rate)
++*/
++
++static int
++dev_wlc_bufvar_get(
++	struct net_device *dev,
++	char *name,
++	char *buf, int buflen)
++{
++	char *ioctlbuf;
++	int error;
++
++	uint len;
++
++	ioctlbuf = kmalloc(MAX_WLIW_IOCTL_LEN, GFP_KERNEL);
++	if (!ioctlbuf)
++		return -ENOMEM;
++	len = bcm_mkiovar(name, NULL, 0, ioctlbuf, MAX_WLIW_IOCTL_LEN);
++	ASSERT(len);
++	BCM_REFERENCE(len);
++	error = dev_wlc_ioctl(dev, WLC_GET_VAR, (void *)ioctlbuf, MAX_WLIW_IOCTL_LEN);
++	if (!error)
++		bcopy(ioctlbuf, buf, buflen);
++
++	kfree(ioctlbuf);
++	return (error);
++}
++
++/*
++get named driver variable to int value and return error indication
++calling example: dev_wlc_intvar_get(dev, "arate", &rate)
++*/
++
++static int
++dev_wlc_intvar_get(
++	struct net_device *dev,
++	char *name,
++	int *retval)
++{
++	union {
++		char buf[WLC_IOCTL_SMLEN];
++		int val;
++	} var;
++	int error;
++
++	uint len;
++	uint data_null;
++
++	len = bcm_mkiovar(name, (char *)(&data_null), 0, (char *)(&var), sizeof(var.buf));
++	ASSERT(len);
++	error = dev_wlc_ioctl(dev, WLC_GET_VAR, (void *)&var, len);
++
++	*retval = dtoh32(var.val);
++
++	return (error);
++}
++
++/* Maintain backward compatibility */
++#if WIRELESS_EXT < 13
++struct iw_request_info
++{
++	__u16		cmd;		/* Wireless Extension command */
++	__u16		flags;		/* More to come ;-) */
++};
++
++typedef int (*iw_handler)(struct net_device *dev, struct iw_request_info *info,
++	void *wrqu, char *extra);
++#endif /* WIRELESS_EXT < 13 */
++
++#if WIRELESS_EXT > 12
++static int
++wl_iw_set_leddc(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	union iwreq_data *wrqu,
++	char *extra
++)
++{
++	int dc = *(int *)extra;
++	int error;
++
++	error = dev_wlc_intvar_set(dev, "leddc", dc);
++	return error;
++}
++
++static int
++wl_iw_set_vlanmode(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	union iwreq_data *wrqu,
++	char *extra
++)
++{
++	int mode = *(int *)extra;
++	int error;
++
++	mode = htod32(mode);
++	error = dev_wlc_intvar_set(dev, "vlan_mode", mode);
++	return error;
++}
++
++static int
++wl_iw_set_pm(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	union iwreq_data *wrqu,
++	char *extra
++)
++{
++	int pm = *(int *)extra;
++	int error;
++
++	pm = htod32(pm);
++	error = dev_wlc_ioctl(dev, WLC_SET_PM, &pm, sizeof(pm));
++	return error;
++}
++#endif /* WIRELESS_EXT > 12 */
++
++#define WL_PM_ENABLE_TIMEOUT 10000
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++#define BCM_SET_CONTAINER_OF(entry, ptr, type, member) \
++_Pragma("GCC diagnostic push") \
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"") \
++entry = container_of((ptr), type, member); \
++_Pragma("GCC diagnostic pop")
++#else
++#define BCM_SET_CONTAINER_OF(entry, ptr, type, member) \
++entry = container_of((ptr), type, member);
++#endif /* STRICT_GCC_WARNINGS */
++
++void wl_ext_pm_work_handler(struct work_struct *work)
++{
++	struct wl_wext_info *wext_info;
++	s32 pm = PM_FAST;
++	dhd_pub_t *dhd;
++	int ret = 0;
++
++	BCM_SET_CONTAINER_OF(wext_info, work, struct wl_wext_info, pm_enable_work.work);
++
++	WL_TRACE(("%s: Enter\n", __FUNCTION__));
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++
++	dhd = (dhd_pub_t *)(wext_info->dhd);
++	if (!dhd || !wext_info->dhd->up) {
++		WL_TRACE(("%s: dhd is null or not up\n", __FUNCTION__));
++		return;
++	}
++	if (dhd_conf_get_pm(dhd) >= 0)
++		pm = dhd_conf_get_pm(dhd);
++	ret = dev_wlc_ioctl(wext_info->dev, WLC_SET_PM, &pm, sizeof(pm));
++	if (ret)
++		WL_ERROR(("%s: WLC_SET_PM failed %d\n", __FUNCTION__, ret));
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	DHD_PM_WAKE_UNLOCK(wext_info->dhd);
++
++}
++
++void wl_ext_add_remove_pm_enable_work(struct wl_wext_info *wext_info,
++	bool add)
++{
++	u16 wq_duration = 0;
++	s32 pm = PM_OFF;
++	int ret = 0;
++
++	if (wext_info == NULL || wext_info->dhd == NULL)
++		return;
++
++	mutex_lock(&wext_info->pm_sync);
++	/*
++	 * Make cancel and schedule work part mutually exclusive
++	 * so that while cancelling, we are sure that there is no
++	 * work getting scheduled.
++	 */
++
++	if (delayed_work_pending(&wext_info->pm_enable_work)) {
++		cancel_delayed_work_sync(&wext_info->pm_enable_work);
++		DHD_PM_WAKE_UNLOCK(wext_info->dhd);
++	}
++
++	if (add) {
++		wq_duration = (WL_PM_ENABLE_TIMEOUT);
++	}
++
++	/* It should schedule work item only if driver is up */
++	if (wq_duration && wext_info->dhd->up) {
++		if (dhd_conf_get_pm(wext_info->dhd) >= 0)
++			pm = dhd_conf_get_pm(wext_info->dhd);
++		ret = dev_wlc_ioctl(wext_info->dev, WLC_SET_PM, &pm, sizeof(pm));
++		if (ret)
++			WL_ERROR(("%s: WLC_SET_PM failed %d\n", __FUNCTION__, ret));
++		if (schedule_delayed_work(&wext_info->pm_enable_work,
++				msecs_to_jiffies((const unsigned int)wq_duration))) {
++			DHD_PM_WAKE_LOCK_TIMEOUT(wext_info->dhd, wq_duration);
++		} else {
++			WL_ERROR(("%s: Can't schedule pm work handler\n", __FUNCTION__));
++		}
++	}
++	mutex_unlock(&wext_info->pm_sync);
++
++}
++
++static void
++wl_iw_update_connect_status(struct net_device *dev, enum wl_ext_status status)
++{
++#ifndef WL_CFG80211
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	int cur_eapol_status = 0;
++	int wpa_auth = 0;
++	int error = -EINVAL;
++	wl_wext_info_t *wext_info = NULL;
++
++	if (!dhd || !dhd->conf)
++		return;
++	wext_info = dhd->wext_info;
++	cur_eapol_status = dhd->conf->eapol_status;
++
++	if (status == WL_EXT_STATUS_CONNECTING) {
++		wl_ext_add_remove_pm_enable_work(wext_info, TRUE);
++		if ((error = dev_wlc_intvar_get(dev, "wpa_auth", &wpa_auth))) {
++			WL_ERROR(("wpa_auth get error %d\n", error));
++			return;
++		}
++		if (wpa_auth & (WPA_AUTH_PSK|WPA2_AUTH_PSK))
++			dhd->conf->eapol_status = EAPOL_STATUS_4WAY_START;
++		else
++			dhd->conf->eapol_status = EAPOL_STATUS_NONE;
++	} else if (status == WL_EXT_STATUS_ADD_KEY) {
++		dhd->conf->eapol_status = EAPOL_STATUS_4WAY_DONE;
++		wake_up_interruptible(&dhd->conf->event_complete);
++	} else if (status == WL_EXT_STATUS_DISCONNECTING) {
++		wl_ext_add_remove_pm_enable_work(wext_info, FALSE);
++		if (cur_eapol_status >= EAPOL_STATUS_4WAY_START &&
++				cur_eapol_status < EAPOL_STATUS_4WAY_DONE) {
++			WL_ERROR(("WPA failed at %d\n", cur_eapol_status));
++			dhd->conf->eapol_status = EAPOL_STATUS_NONE;
++		} else if (cur_eapol_status >= EAPOL_STATUS_WSC_START &&
++				cur_eapol_status < EAPOL_STATUS_WSC_DONE) {
++			WL_ERROR(("WPS failed at %d\n", cur_eapol_status));
++			dhd->conf->eapol_status = EAPOL_STATUS_NONE;
++		}
++	} else if (status == WL_EXT_STATUS_DISCONNECTED) {
++		if (cur_eapol_status >= EAPOL_STATUS_4WAY_START &&
++				cur_eapol_status < EAPOL_STATUS_4WAY_DONE) {
++			WL_ERROR(("WPA failed at %d\n", cur_eapol_status));
++			dhd->conf->eapol_status = EAPOL_STATUS_NONE;
++			wake_up_interruptible(&dhd->conf->event_complete);
++		} else if (cur_eapol_status >= EAPOL_STATUS_WSC_START &&
++				cur_eapol_status < EAPOL_STATUS_WSC_DONE) {
++			WL_ERROR(("WPS failed at %d\n", cur_eapol_status));
++			dhd->conf->eapol_status = EAPOL_STATUS_NONE;
++		}
++	}
++#endif
++	return;
++}
++
++int
++wl_iw_send_priv_event(
++	struct net_device *dev,
++	char *flag
++)
++{
++	union iwreq_data wrqu;
++	char extra[IW_CUSTOM_MAX + 1];
++	int cmd;
++
++	cmd = IWEVCUSTOM;
++	memset(&wrqu, 0, sizeof(wrqu));
++	if (strlen(flag) > sizeof(extra))
++		return -1;
++
++	strncpy(extra, flag, sizeof(extra));
++	extra[sizeof(extra) - 1] = '\0';
++	wrqu.data.length = strlen(extra);
++	wireless_send_event(dev, cmd, &wrqu, extra);
++	WL_TRACE(("Send IWEVCUSTOM Event as %s\n", extra));
++
++	return 0;
++}
++
++static int
++wl_iw_config_commit(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	void *zwrq,
++	char *extra
++)
++{
++	wlc_ssid_t ssid;
++	int error;
++	struct sockaddr bssid;
++
++	WL_TRACE(("%s: SIOCSIWCOMMIT\n", dev->name));
++
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_SSID, &ssid, sizeof(ssid))))
++		return error;
++
++	ssid.SSID_len = dtoh32(ssid.SSID_len);
++
++	if (!ssid.SSID_len)
++		return 0;
++
++	bzero(&bssid, sizeof(struct sockaddr));
++	if ((error = dev_wlc_ioctl(dev, WLC_REASSOC, &bssid, ETHER_ADDR_LEN))) {
++		WL_ERROR(("WLC_REASSOC failed (%d)\n", error));
++		return error;
++	}
++
++	return 0;
++}
++
++static int
++wl_iw_get_name(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	union iwreq_data *cwrq,
++	char *extra
++)
++{
++	int phytype, err;
++	uint band[3];
++	char cap[5];
++
++	WL_TRACE(("%s: SIOCGIWNAME\n", dev->name));
++
++	cap[0] = 0;
++	if ((err = dev_wlc_ioctl(dev, WLC_GET_PHYTYPE, &phytype, sizeof(phytype))) < 0)
++		goto done;
++	if ((err = dev_wlc_ioctl(dev, WLC_GET_BANDLIST, band, sizeof(band))) < 0)
++		goto done;
++
++	band[0] = dtoh32(band[0]);
++	switch (phytype) {
++		case WLC_PHY_TYPE_A:
++			strncpy(cap, "a", sizeof(cap));
++			break;
++		case WLC_PHY_TYPE_B:
++			strncpy(cap, "b", sizeof(cap));
++			break;
++		case WLC_PHY_TYPE_G:
++			if (band[0] >= 2)
++				strncpy(cap, "abg", sizeof(cap));
++			else
++				strncpy(cap, "bg", sizeof(cap));
++			break;
++		case WLC_PHY_TYPE_N:
++			if (band[0] >= 2)
++				strncpy(cap, "abgn", sizeof(cap));
++			else
++				strncpy(cap, "bgn", sizeof(cap));
++			break;
++	}
++done:
++	(void)snprintf(cwrq->name, IFNAMSIZ, "IEEE 802.11%s", cap);
++
++	return 0;
++}
++
++#define DHD_CHECK(dhd, dev) \
++ 	if (!dhd) { \
++		WL_ERROR (("[dhd-%s] %s: dhd is NULL\n", dev->name, __FUNCTION__)); \
++		return -ENODEV; \
++	} \
++
++static int
++wl_iw_set_freq(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_freq *fwrq,
++	char *extra
++)
++{
++	int error, chan;
++	uint sf = 0;
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	wl_wext_info_t *wext_info = NULL;
++
++	WL_TRACE(("%s: SIOCSIWFREQ\n", dev->name));
++	DHD_CHECK(dhd, dev);
++	wext_info = dhd->wext_info;
++
++	/* Setting by channel number */
++	if (fwrq->e == 0 && fwrq->m < MAXCHANNEL) {
++		chan = fwrq->m;
++	}
++
++	/* Setting by frequency */
++	else {
++		/* Convert to MHz as best we can */
++		if (fwrq->e >= 6) {
++			fwrq->e -= 6;
++			while (fwrq->e--)
++				fwrq->m *= 10;
++		} else if (fwrq->e < 6) {
++			while (fwrq->e++ < 6)
++				fwrq->m /= 10;
++		}
++	/* handle 4.9GHz frequencies as Japan 4 GHz based channelization */
++		if (fwrq->m > 4000 && fwrq->m < 5000) {
++			sf = WF_CHAN_FACTOR_4_G; /* start factor for 4 GHz */
++		}
++		chan = wf_mhz2channel(fwrq->m, sf);
++	}
++	if (wext_info)
++		wext_info->conn_info.channel = chan;
++	WL_MSG(dev->name, "chan=%d\n", chan);
++	chan = htod32(chan);
++	if ((error = dev_wlc_ioctl(dev, WLC_SET_CHANNEL, &chan, sizeof(chan)))) {
++		WL_ERROR(("WLC_SET_CHANNEL failed (%d).\n", error));
++		return error;
++	}
++
++	/* -EINPROGRESS: Call commit handler */
++	return -EINPROGRESS;
++}
++
++static int
++wl_iw_get_freq(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_freq *fwrq,
++	char *extra
++)
++{
++	int error;
++	u32 chanspec = 0;
++	int ctl_chan;
++
++	WL_TRACE(("%s: SIOCGIWFREQ\n", dev->name));
++
++	if ((error = dev_wlc_intvar_get(dev, "chanspec", &chanspec)))
++		return error;
++	ctl_chan = wf_chspec_ctlchan(chanspec);
++
++	/* Return radio channel in channel form */
++	fwrq->m = ctl_chan;
++	fwrq->e = dtoh32(0);
++	return 0;
++}
++
++static int
++wl_iw_set_mode(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	__u32 *uwrq,
++	char *extra
++)
++{
++	int infra = 0, ap = 0, error = 0;
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	wl_wext_info_t *wext_info = NULL;
++
++	WL_TRACE(("%s: SIOCSIWMODE\n", dev->name));
++	DHD_CHECK(dhd, dev);
++	wext_info = dhd->wext_info;
++	if (wext_info) {
++		memset(&wext_info->conn_info.ssid, 0, sizeof(wlc_ssid_t));
++		memset(&wext_info->conn_info.bssid, 0, sizeof(struct ether_addr));
++		wext_info->conn_info.channel = 0;
++	}
++
++	switch (*uwrq) {
++	case IW_MODE_MASTER:
++		infra = ap = 1;
++		break;
++	case IW_MODE_ADHOC:
++	case IW_MODE_AUTO:
++		break;
++	case IW_MODE_INFRA:
++		infra = 1;
++		break;
++	default:
++		return -EINVAL;
++	}
++	infra = htod32(infra);
++	ap = htod32(ap);
++
++	if ((error = dev_wlc_ioctl(dev, WLC_SET_INFRA, &infra, sizeof(infra))) ||
++	    (error = dev_wlc_ioctl(dev, WLC_SET_AP, &ap, sizeof(ap))))
++		return error;
++
++	/* -EINPROGRESS: Call commit handler */
++	return -EINPROGRESS;
++}
++
++static int
++wl_iw_get_mode(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	__u32 *uwrq,
++	char *extra
++)
++{
++	int error, infra = 0, ap = 0;
++
++	WL_TRACE(("%s: SIOCGIWMODE\n", dev->name));
++
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_INFRA, &infra, sizeof(infra))) ||
++	    (error = dev_wlc_ioctl(dev, WLC_GET_AP, &ap, sizeof(ap))))
++		return error;
++
++	infra = dtoh32(infra);
++	ap = dtoh32(ap);
++	*uwrq = infra ? ap ? IW_MODE_MASTER : IW_MODE_INFRA : IW_MODE_ADHOC;
++
++	return 0;
++}
++
++static int
++wl_iw_get_range(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	struct iw_range *range = (struct iw_range *) extra;
++	static int channels[MAXCHANNEL+1];
++	wl_uint32_list_t *list = (wl_uint32_list_t *) channels;
++	wl_rateset_t rateset;
++	int error, i, k;
++	uint sf, ch;
++
++	int phytype;
++	int bw_cap = 0, sgi_tx = 0, nmode = 0;
++	channel_info_t ci;
++	uint8 nrate_list2copy = 0;
++	uint16 nrate_list[4][8] = { {13, 26, 39, 52, 78, 104, 117, 130},
++		{14, 29, 43, 58, 87, 116, 130, 144},
++		{27, 54, 81, 108, 162, 216, 243, 270},
++		{30, 60, 90, 120, 180, 240, 270, 300}};
++	int fbt_cap = 0;
++
++	WL_TRACE(("%s: SIOCGIWRANGE\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	dwrq->length = sizeof(struct iw_range);
++	memset(range, 0, sizeof(*range));
++
++	/* We don't use nwids */
++	range->min_nwid = range->max_nwid = 0;
++
++	/* Set available channels/frequencies */
++	list->count = htod32(MAXCHANNEL);
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_VALID_CHANNELS, channels, sizeof(channels))))
++		return error;
++	for (i = 0; i < dtoh32(list->count) && i < IW_MAX_FREQUENCIES; i++) {
++		range->freq[i].i = dtoh32(list->element[i]);
++
++		ch = dtoh32(list->element[i]);
++		if (ch <= CH_MAX_2G_CHANNEL)
++			sf = WF_CHAN_FACTOR_2_4_G;
++		else
++			sf = WF_CHAN_FACTOR_5_G;
++
++		range->freq[i].m = wf_channel2mhz(ch, sf);
++		range->freq[i].e = 6;
++	}
++	range->num_frequency = range->num_channels = i;
++
++	/* Link quality (use NDIS cutoffs) */
++	range->max_qual.qual = 5;
++	/* Signal level (use RSSI) */
++	range->max_qual.level = 0x100 - 200;	/* -200 dBm */
++	/* Noise level (use noise) */
++	range->max_qual.noise = 0x100 - 200;	/* -200 dBm */
++	/* Signal level threshold range (?) */
++	range->sensitivity = 65535;
++
++#if WIRELESS_EXT > 11
++	/* Link quality (use NDIS cutoffs) */
++	range->avg_qual.qual = 3;
++	/* Signal level (use RSSI) */
++	range->avg_qual.level = 0x100 + WL_IW_RSSI_GOOD;
++	/* Noise level (use noise) */
++	range->avg_qual.noise = 0x100 - 75;	/* -75 dBm */
++#endif /* WIRELESS_EXT > 11 */
++
++	/* Set available bitrates */
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_CURR_RATESET, &rateset, sizeof(rateset))))
++		return error;
++	rateset.count = dtoh32(rateset.count);
++	range->num_bitrates = rateset.count;
++	for (i = 0; i < rateset.count && i < IW_MAX_BITRATES; i++)
++		range->bitrate[i] = (rateset.rates[i] & 0x7f) * 500000; /* convert to bps */
++	if ((error = dev_wlc_intvar_get(dev, "nmode", &nmode)))
++		return error;
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_PHYTYPE, &phytype, sizeof(phytype))))
++		return error;
++	if (nmode == 1 && (((phytype == WLC_PHY_TYPE_LCN) ||
++	                    (phytype == WLC_PHY_TYPE_LCN40)))) {
++		if ((error = dev_wlc_intvar_get(dev, "mimo_bw_cap", &bw_cap)))
++			return error;
++		if ((error = dev_wlc_intvar_get(dev, "sgi_tx", &sgi_tx)))
++			return error;
++		if ((error = dev_wlc_ioctl(dev, WLC_GET_CHANNEL, &ci, sizeof(channel_info_t))))
++			return error;
++		ci.hw_channel = dtoh32(ci.hw_channel);
++
++		if (bw_cap == 0 ||
++			(bw_cap == 2 && ci.hw_channel <= 14)) {
++			if (sgi_tx == 0)
++				nrate_list2copy = 0;
++			else
++				nrate_list2copy = 1;
++		}
++		if (bw_cap == 1 ||
++			(bw_cap == 2 && ci.hw_channel >= 36)) {
++			if (sgi_tx == 0)
++				nrate_list2copy = 2;
++			else
++				nrate_list2copy = 3;
++		}
++		range->num_bitrates += 8;
++		ASSERT(range->num_bitrates < IW_MAX_BITRATES);
++		for (k = 0; i < range->num_bitrates; k++, i++) {
++			/* convert to bps */
++			range->bitrate[i] = (nrate_list[nrate_list2copy][k]) * 500000;
++		}
++	}
++
++	/* Set an indication of the max TCP throughput
++	 * in bit/s that we can expect using this interface.
++	 * May be use for QoS stuff... Jean II
++	 */
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_PHYTYPE, &i, sizeof(i))))
++		return error;
++	i = dtoh32(i);
++	if (i == WLC_PHY_TYPE_A)
++		range->throughput = 24000000;	/* 24 Mbits/s */
++	else
++		range->throughput = 1500000;	/* 1.5 Mbits/s */
++
++	/* RTS and fragmentation thresholds */
++	range->min_rts = 0;
++	range->max_rts = 2347;
++	range->min_frag = 256;
++	range->max_frag = 2346;
++
++	range->max_encoding_tokens = DOT11_MAX_DEFAULT_KEYS;
++	range->num_encoding_sizes = 4;
++	range->encoding_size[0] = WEP1_KEY_SIZE;
++	range->encoding_size[1] = WEP128_KEY_SIZE;
++#if WIRELESS_EXT > 17
++	range->encoding_size[2] = TKIP_KEY_SIZE;
++#else
++	range->encoding_size[2] = 0;
++#endif
++	range->encoding_size[3] = AES_KEY_SIZE;
++
++	/* Do not support power micro-management */
++	range->min_pmp = 0;
++	range->max_pmp = 0;
++	range->min_pmt = 0;
++	range->max_pmt = 0;
++	range->pmp_flags = 0;
++	range->pm_capa = 0;
++
++	/* Transmit Power - values are in mW */
++	range->num_txpower = 2;
++	range->txpower[0] = 1;
++	range->txpower[1] = 255;
++	range->txpower_capa = IW_TXPOW_MWATT;
++
++#if WIRELESS_EXT > 10
++	range->we_version_compiled = WIRELESS_EXT;
++	range->we_version_source = 19;
++
++	/* Only support retry limits */
++	range->retry_capa = IW_RETRY_LIMIT;
++	range->retry_flags = IW_RETRY_LIMIT;
++	range->r_time_flags = 0;
++	/* SRL and LRL limits */
++	range->min_retry = 1;
++	range->max_retry = 255;
++	/* Retry lifetime limits unsupported */
++	range->min_r_time = 0;
++	range->max_r_time = 0;
++#endif /* WIRELESS_EXT > 10 */
++
++#if WIRELESS_EXT > 17
++	range->enc_capa = IW_ENC_CAPA_WPA;
++	range->enc_capa |= IW_ENC_CAPA_CIPHER_TKIP;
++	range->enc_capa |= IW_ENC_CAPA_CIPHER_CCMP;
++	range->enc_capa |= IW_ENC_CAPA_WPA2;
++
++	/* Determine driver FBT capability. */
++	if (dev_wlc_intvar_get(dev, "fbt_cap", &fbt_cap) == 0) {
++		if (fbt_cap == WLC_FBT_CAP_DRV_4WAY_AND_REASSOC) {
++			/* Tell the host (e.g. wpa_supplicant) to let driver do the handshake */
++			range->enc_capa |= IW_ENC_CAPA_4WAY_HANDSHAKE;
++		}
++	}
++
++#ifdef BCMFW_ROAM_ENABLE_WEXT
++	/* Advertise firmware roam capability to the external supplicant */
++	range->enc_capa |= IW_ENC_CAPA_FW_ROAM_ENABLE;
++#endif /* BCMFW_ROAM_ENABLE_WEXT */
++
++	/* Event capability (kernel) */
++	IW_EVENT_CAPA_SET_KERNEL(range->event_capa);
++	/* Event capability (driver) */
++	IW_EVENT_CAPA_SET(range->event_capa, SIOCGIWAP);
++	IW_EVENT_CAPA_SET(range->event_capa, SIOCGIWSCAN);
++	IW_EVENT_CAPA_SET(range->event_capa, IWEVTXDROP);
++	IW_EVENT_CAPA_SET(range->event_capa, IWEVMICHAELMICFAILURE);
++	IW_EVENT_CAPA_SET(range->event_capa, IWEVASSOCREQIE);
++	IW_EVENT_CAPA_SET(range->event_capa, IWEVASSOCRESPIE);
++	IW_EVENT_CAPA_SET(range->event_capa, IWEVPMKIDCAND);
++
++#if WIRELESS_EXT >= 22 && defined(IW_SCAN_CAPA_ESSID)
++	/* FC7 wireless.h defines EXT 22 but doesn't define scan_capa bits */
++	range->scan_capa = IW_SCAN_CAPA_ESSID;
++#endif
++#endif /* WIRELESS_EXT > 17 */
++
++	return 0;
++}
++
++#ifndef WL_ESCAN
++static int
++rssi_to_qual(int rssi)
++{
++	if (rssi <= WL_IW_RSSI_NO_SIGNAL)
++		return 0;
++	else if (rssi <= WL_IW_RSSI_VERY_LOW)
++		return 1;
++	else if (rssi <= WL_IW_RSSI_LOW)
++		return 2;
++	else if (rssi <= WL_IW_RSSI_GOOD)
++		return 3;
++	else if (rssi <= WL_IW_RSSI_VERY_GOOD)
++		return 4;
++	else
++		return 5;
++}
++#endif /* WL_ESCAN */
++
++static int
++wl_iw_set_spy(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_iw_t *iw = IW_DEV_IF(dev);
++	struct sockaddr *addr = (struct sockaddr *) extra;
++	int i;
++
++	WL_TRACE(("%s: SIOCSIWSPY\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	iw->spy_num = MIN(ARRAYSIZE(iw->spy_addr), dwrq->length);
++	for (i = 0; i < iw->spy_num; i++)
++		memcpy(&iw->spy_addr[i], addr[i].sa_data, ETHER_ADDR_LEN);
++	memset(iw->spy_qual, 0, sizeof(iw->spy_qual));
++
++	return 0;
++}
++
++static int
++wl_iw_get_spy(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_iw_t *iw = IW_DEV_IF(dev);
++	struct sockaddr *addr = (struct sockaddr *) extra;
++	struct iw_quality *qual = (struct iw_quality *) &addr[iw->spy_num];
++	int i;
++
++	WL_TRACE(("%s: SIOCGIWSPY\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	dwrq->length = iw->spy_num;
++	for (i = 0; i < iw->spy_num; i++) {
++		memcpy(addr[i].sa_data, &iw->spy_addr[i], ETHER_ADDR_LEN);
++		addr[i].sa_family = AF_UNIX;
++		memcpy(&qual[i], &iw->spy_qual[i], sizeof(struct iw_quality));
++		iw->spy_qual[i].updated = 0;
++	}
++
++	return 0;
++}
++
++static int
++wl_iw_set_wap(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct sockaddr *awrq,
++	char *extra
++)
++{
++	int error = -EINVAL;
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	wl_wext_info_t *wext_info = NULL;
++
++	WL_TRACE(("%s: SIOCSIWAP\n", dev->name));
++	DHD_CHECK(dhd, dev);
++ 	wext_info = dhd->wext_info;
++	if (awrq->sa_family != ARPHRD_ETHER) {
++		WL_ERROR(("Invalid Header...sa_family\n"));
++		return -EINVAL;
++	}
++
++	/* Ignore "auto" or "off" */
++	if (ETHER_ISBCAST(awrq->sa_data) || ETHER_ISNULLADDR(awrq->sa_data)) {
++		scb_val_t scbval;
++		bzero(&scbval, sizeof(scb_val_t));
++		WL_MSG(dev->name, "WLC_DISASSOC\n");
++		if ((error = dev_wlc_ioctl(dev, WLC_DISASSOC, &scbval, sizeof(scb_val_t)))) {
++			WL_ERROR(("WLC_DISASSOC failed (%d).\n", error));
++		}
++		wl_iw_update_connect_status(dev, WL_EXT_STATUS_DISCONNECTING);
++		return 0;
++	}
++	/* WL_ASSOC(("Assoc to %s\n", bcm_ether_ntoa((struct ether_addr *)&(awrq->sa_data),
++	 * eabuf)));
++	 */
++	/* Reassociate to the specified AP */
++	if (wext_info)
++		memcpy(&wext_info->conn_info.bssid, awrq->sa_data, ETHER_ADDR_LEN);
++	if (wext_info && wext_info->conn_info.ssid.SSID_len) {
++		if ((error = wl_ext_connect(dev, &wext_info->conn_info)))
++			return error;
++	} else {
++		if ((error = dev_wlc_ioctl(dev, WLC_REASSOC, awrq->sa_data, ETHER_ADDR_LEN))) {
++			WL_ERROR(("WLC_REASSOC failed (%d).\n", error));
++			return error;
++		}
++		WL_MSG(dev->name, "join BSSID="MACSTR"\n", MAC2STR((u8 *)awrq->sa_data));
++	}
++	wl_iw_update_connect_status(dev, WL_EXT_STATUS_CONNECTING);
++
++	return 0;
++}
++
++static int
++wl_iw_get_wap(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct sockaddr *awrq,
++	char *extra
++)
++{
++	WL_TRACE(("%s: SIOCGIWAP\n", dev->name));
++
++	awrq->sa_family = ARPHRD_ETHER;
++	memset(awrq->sa_data, 0, ETHER_ADDR_LEN);
++
++	/* Ignore error (may be down or disassociated) */
++	(void) dev_wlc_ioctl(dev, WLC_GET_BSSID, awrq->sa_data, ETHER_ADDR_LEN);
++
++	return 0;
++}
++
++#if WIRELESS_EXT > 17
++static int
++wl_iw_mlme(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct sockaddr *awrq,
++	char *extra
++)
++{
++	struct iw_mlme *mlme;
++	scb_val_t scbval;
++	int error  = -EINVAL;
++
++	WL_TRACE(("%s: SIOCSIWMLME\n", dev->name));
++
++	mlme = (struct iw_mlme *)extra;
++	if (mlme == NULL) {
++		WL_ERROR(("Invalid ioctl data.\n"));
++		return error;
++	}
++
++	scbval.val = mlme->reason_code;
++	bcopy(&mlme->addr.sa_data, &scbval.ea, ETHER_ADDR_LEN);
++
++	if (mlme->cmd == IW_MLME_DISASSOC) {
++		scbval.val = htod32(scbval.val);
++		WL_MSG(dev->name, "WLC_DISASSOC\n");
++		error = dev_wlc_ioctl(dev, WLC_DISASSOC, &scbval, sizeof(scb_val_t));
++	}
++	else if (mlme->cmd == IW_MLME_DEAUTH) {
++		scbval.val = htod32(scbval.val);
++		WL_MSG(dev->name, "WLC_SCB_DEAUTHENTICATE_FOR_REASON\n");
++		error = dev_wlc_ioctl(dev, WLC_SCB_DEAUTHENTICATE_FOR_REASON, &scbval,
++			sizeof(scb_val_t));
++	}
++	else {
++		WL_ERROR(("Invalid ioctl data.\n"));
++		return error;
++	}
++	wl_iw_update_connect_status(dev, WL_EXT_STATUS_DISCONNECTING);
++
++	return error;
++}
++#endif /* WIRELESS_EXT > 17 */
++
++#ifndef WL_ESCAN
++static int
++wl_iw_get_aplist(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_scan_results_t *list;
++	struct sockaddr *addr = (struct sockaddr *) extra;
++	struct iw_quality qual[IW_MAX_AP];
++	wl_bss_info_t *bi = NULL;
++	int error, i;
++	uint buflen = dwrq->length;
++	int16 rssi;
++
++	WL_TRACE(("%s: SIOCGIWAPLIST\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	/* Get scan results (too large to put on the stack) */
++	list = kmalloc(buflen, GFP_KERNEL);
++	if (!list)
++		return -ENOMEM;
++	memset(list, 0, buflen);
++	list->buflen = htod32(buflen);
++	if ((error = dev_wlc_ioctl(dev, WLC_SCAN_RESULTS, list, buflen))) {
++		WL_ERROR(("%d: Scan results error %d\n", __LINE__, error));
++		kfree(list);
++		return error;
++	}
++	list->buflen = dtoh32(list->buflen);
++	list->version = dtoh32(list->version);
++	list->count = dtoh32(list->count);
++	ASSERT(list->version == WL_BSS_INFO_VERSION);
++
++	for (i = 0, dwrq->length = 0; i < list->count && dwrq->length < IW_MAX_AP; i++) {
++		bi = bi ? (wl_bss_info_t *)((uintptr)bi + dtoh32(bi->length)) : list->bss_info;
++		ASSERT(((uintptr)bi + dtoh32(bi->length)) <= ((uintptr)list +
++			buflen));
++
++		/* Infrastructure only */
++		if (!(dtoh16(bi->capability) & DOT11_CAP_ESS))
++			continue;
++
++		/* BSSID */
++		memcpy(addr[dwrq->length].sa_data, &bi->BSSID, ETHER_ADDR_LEN);
++		addr[dwrq->length].sa_family = ARPHRD_ETHER;
++		// terence 20150419: limit the max. rssi to -2 or the bss will be filtered out in android OS
++		rssi = MIN(dtoh16(bi->RSSI), RSSI_MAXVAL);
++		qual[dwrq->length].qual = rssi_to_qual(rssi);
++		qual[dwrq->length].level = 0x100 + rssi;
++		qual[dwrq->length].noise = 0x100 + bi->phy_noise;
++
++		/* Updated qual, level, and noise */
++#if WIRELESS_EXT > 18
++		qual[dwrq->length].updated = IW_QUAL_ALL_UPDATED | IW_QUAL_DBM;
++#else
++		qual[dwrq->length].updated = 7;
++#endif /* WIRELESS_EXT > 18 */
++
++		dwrq->length++;
++	}
++
++	kfree(list);
++
++	if (dwrq->length) {
++		memcpy(&addr[dwrq->length], qual, sizeof(struct iw_quality) * dwrq->length);
++		/* Provided qual */
++		dwrq->flags = 1;
++	}
++
++	return 0;
++}
++
++static int
++wl_iw_iscan_get_aplist(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_scan_results_t *list;
++	iscan_buf_t * buf;
++	iscan_info_t *iscan;
++
++	struct sockaddr *addr = (struct sockaddr *) extra;
++	struct iw_quality qual[IW_MAX_AP];
++	wl_bss_info_t *bi = NULL;
++	int i;
++	int16 rssi;
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	wl_wext_info_t *wext_info = NULL;
++
++	WL_TRACE(("%s: SIOCGIWAPLIST\n", dev->name));
++	DHD_CHECK(dhd, dev);
++ 	wext_info = dhd->wext_info;
++	iscan = &wext_info->iscan;
++
++	if (!extra)
++		return -EINVAL;
++
++	if ((!iscan) || (iscan->sysioc_pid < 0)) {
++		return wl_iw_get_aplist(dev, info, dwrq, extra);
++	}
++
++	buf = iscan->list_hdr;
++	/* Get scan results (too large to put on the stack) */
++	while (buf) {
++	    list = &((wl_iscan_results_t*)buf->iscan_buf)->results;
++	    ASSERT(list->version == WL_BSS_INFO_VERSION);
++
++	    bi = NULL;
++	for (i = 0, dwrq->length = 0; i < list->count && dwrq->length < IW_MAX_AP; i++) {
++		bi = bi ? (wl_bss_info_t *)((uintptr)bi + dtoh32(bi->length)) : list->bss_info;
++		ASSERT(((uintptr)bi + dtoh32(bi->length)) <= ((uintptr)list +
++			WLC_IW_ISCAN_MAXLEN));
++
++		/* Infrastructure only */
++		if (!(dtoh16(bi->capability) & DOT11_CAP_ESS))
++			continue;
++
++		/* BSSID */
++		memcpy(addr[dwrq->length].sa_data, &bi->BSSID, ETHER_ADDR_LEN);
++		addr[dwrq->length].sa_family = ARPHRD_ETHER;
++		// terence 20150419: limit the max. rssi to -2 or the bss will be filtered out in android OS
++		rssi = MIN(dtoh16(bi->RSSI), RSSI_MAXVAL);
++		qual[dwrq->length].qual = rssi_to_qual(rssi);
++		qual[dwrq->length].level = 0x100 + rssi;
++		qual[dwrq->length].noise = 0x100 + bi->phy_noise;
++
++		/* Updated qual, level, and noise */
++#if WIRELESS_EXT > 18
++		qual[dwrq->length].updated = IW_QUAL_ALL_UPDATED | IW_QUAL_DBM;
++#else
++		qual[dwrq->length].updated = 7;
++#endif /* WIRELESS_EXT > 18 */
++
++		dwrq->length++;
++	    }
++	    buf = buf->next;
++	}
++	if (dwrq->length) {
++		memcpy(&addr[dwrq->length], qual, sizeof(struct iw_quality) * dwrq->length);
++		/* Provided qual */
++		dwrq->flags = 1;
++	}
++
++	return 0;
++}
++#endif
++
++#if WIRELESS_EXT > 13
++#ifndef WL_ESCAN
++static int
++wl_iw_set_scan(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	union iwreq_data *wrqu,
++	char *extra
++)
++{
++	wlc_ssid_t ssid;
++
++	WL_TRACE(("%s: SIOCSIWSCAN\n", dev->name));
++
++	/* default Broadcast scan */
++	memset(&ssid, 0, sizeof(ssid));
++
++#if WIRELESS_EXT > 17
++	/* check for given essid */
++	if (wrqu->data.length == sizeof(struct iw_scan_req)) {
++		if (wrqu->data.flags & IW_SCAN_THIS_ESSID) {
++			struct iw_scan_req *req = (struct iw_scan_req *)extra;
++			ssid.SSID_len = MIN(sizeof(ssid.SSID), req->essid_len);
++			memcpy(ssid.SSID, req->essid, ssid.SSID_len);
++			ssid.SSID_len = htod32(ssid.SSID_len);
++		}
++	}
++#endif
++	/* Ignore error (most likely scan in progress) */
++	(void) dev_wlc_ioctl(dev, WLC_SCAN, &ssid, sizeof(ssid));
++
++	return 0;
++}
++#endif
++
++static int
++wl_iw_iscan_set_scan(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	union iwreq_data *wrqu,
++	char *extra
++)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	wl_wext_info_t *wext_info = NULL;
++	wlc_ssid_t ssid;
++#ifndef WL_ESCAN
++	iscan_info_t *iscan;
++#endif
++
++	DHD_CHECK(dhd, dev);
++	wext_info = dhd->wext_info;
++#ifdef WL_ESCAN
++	/* default Broadcast scan */
++	memset(&ssid, 0, sizeof(ssid));
++#if WIRELESS_EXT > 17
++	/* check for given essid */
++	if (wrqu->data.length == sizeof(struct iw_scan_req)) {
++		if (wrqu->data.flags & IW_SCAN_THIS_ESSID) {
++			struct iw_scan_req *req = (struct iw_scan_req *)extra;
++			ssid.SSID_len = MIN(sizeof(ssid.SSID), req->essid_len);
++			memcpy(ssid.SSID, req->essid, ssid.SSID_len);
++			ssid.SSID_len = htod32(ssid.SSID_len);
++		}
++	}
++#endif
++	return wl_escan_set_scan(dev, dhd, &ssid, 0, TRUE);
++#else
++	iscan = &wext_info->iscan;
++	WL_TRACE(("%s: SIOCSIWSCAN iscan=%p\n", dev->name, iscan));
++
++	/* use backup if our thread is not successful */
++	if ((!iscan) || (iscan->sysioc_pid < 0)) {
++		return wl_iw_set_scan(dev, info, wrqu, extra);
++	}
++	if (iscan->iscan_state == ISCAN_STATE_SCANING) {
++		return 0;
++	}
++
++	/* default Broadcast scan */
++	memset(&ssid, 0, sizeof(ssid));
++
++#if WIRELESS_EXT > 17
++	/* check for given essid */
++	if (wrqu->data.length == sizeof(struct iw_scan_req)) {
++		if (wrqu->data.flags & IW_SCAN_THIS_ESSID) {
++			struct iw_scan_req *req = (struct iw_scan_req *)extra;
++			ssid.SSID_len = MIN(sizeof(ssid.SSID), req->essid_len);
++			memcpy(ssid.SSID, req->essid, ssid.SSID_len);
++			ssid.SSID_len = htod32(ssid.SSID_len);
++		}
++	}
++#endif
++
++	iscan->list_cur = iscan->list_hdr;
++	iscan->iscan_state = ISCAN_STATE_SCANING;
++
++
++	wl_iw_set_event_mask(dev);
++	wl_iw_iscan(iscan, &ssid, WL_SCAN_ACTION_START);
++
++	iscan->timer.expires = jiffies + msecs_to_jiffies(iscan->timer_ms);
++	add_timer(&iscan->timer);
++	iscan->timer_on = 1;
++
++	return 0;
++#endif
++}
++
++#if WIRELESS_EXT > 17
++static bool
++ie_is_wpa_ie(uint8 **wpaie, uint8 **tlvs, int *tlvs_len)
++{
++/* Is this body of this tlvs entry a WPA entry? If */
++/* not update the tlvs buffer pointer/length */
++	uint8 *ie = *wpaie;
++
++	/* If the contents match the WPA_OUI and type=1 */
++	if ((ie[1] >= 6) &&
++		!bcmp((const void *)&ie[2], (const void *)(WPA_OUI "\x01"), 4)) {
++		return TRUE;
++	}
++
++	/* point to the next ie */
++	ie += ie[1] + 2;
++	/* calculate the length of the rest of the buffer */
++	*tlvs_len -= (int)(ie - *tlvs);
++	/* update the pointer to the start of the buffer */
++	*tlvs = ie;
++	return FALSE;
++}
++
++static bool
++ie_is_wps_ie(uint8 **wpsie, uint8 **tlvs, int *tlvs_len)
++{
++/* Is this body of this tlvs entry a WPS entry? If */
++/* not update the tlvs buffer pointer/length */
++	uint8 *ie = *wpsie;
++
++	/* If the contents match the WPA_OUI and type=4 */
++	if ((ie[1] >= 4) &&
++		!bcmp((const void *)&ie[2], (const void *)(WPA_OUI "\x04"), 4)) {
++		return TRUE;
++	}
++
++	/* point to the next ie */
++	ie += ie[1] + 2;
++	/* calculate the length of the rest of the buffer */
++	*tlvs_len -= (int)(ie - *tlvs);
++	/* update the pointer to the start of the buffer */
++	*tlvs = ie;
++	return FALSE;
++}
++#endif /* WIRELESS_EXT > 17 */
++
++#ifdef BCMWAPI_WPI
++static inline int _wpa_snprintf_hex(char *buf, size_t buf_size, const u8 *data,
++	size_t len, int uppercase)
++{
++	size_t i;
++	char *pos = buf, *end = buf + buf_size;
++	int ret;
++	if (buf_size == 0)
++		return 0;
++	for (i = 0; i < len; i++) {
++		ret = snprintf(pos, end - pos, uppercase ? "%02X" : "%02x",
++			data[i]);
++		if (ret < 0 || ret >= end - pos) {
++			end[-1] = '\0';
++			return pos - buf;
++		}
++		pos += ret;
++	}
++	end[-1] = '\0';
++	return pos - buf;
++}
++
++/**
++ * wpa_snprintf_hex - Print data as a hex string into a buffer
++ * @buf: Memory area to use as the output buffer
++ * @buf_size: Maximum buffer size in bytes (should be at least 2 * len + 1)
++ * @data: Data to be printed
++ * @len: Length of data in bytes
++ * Returns: Number of bytes written
++ */
++static int
++wpa_snprintf_hex(char *buf, size_t buf_size, const u8 *data, size_t len)
++{
++	return _wpa_snprintf_hex(buf, buf_size, data, len, 0);
++}
++#endif /* BCMWAPI_WPI */
++
++#ifndef WL_ESCAN
++static
++#endif
++int
++wl_iw_handle_scanresults_ies(char **event_p, char *end,
++	struct iw_request_info *info, wl_bss_info_t *bi)
++{
++#if WIRELESS_EXT > 17
++	struct iw_event	iwe;
++	char *event;
++#ifdef BCMWAPI_WPI
++	char *buf;
++	int custom_event_len;
++#endif
++
++	event = *event_p;
++	if (bi->ie_length) {
++		/* look for wpa/rsn ies in the ie list... */
++		bcm_tlv_t *ie;
++		uint8 *ptr = ((uint8 *)bi) + bi->ie_offset;
++		int ptr_len = bi->ie_length;
++
++		/* OSEN IE */
++		if ((ie = bcm_parse_tlvs(ptr, ptr_len, DOT11_MNG_VS_ID)) &&
++			ie->len > WFA_OUI_LEN + 1 &&
++			!bcmp((const void *)&ie->data[0], (const void *)WFA_OUI, WFA_OUI_LEN) &&
++			ie->data[WFA_OUI_LEN] == WFA_OUI_TYPE_OSEN) {
++			iwe.cmd = IWEVGENIE;
++			iwe.u.data.length = ie->len + 2;
++			event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, (char *)ie);
++		}
++		ptr = ((uint8 *)bi) + bi->ie_offset;
++
++		if ((ie = bcm_parse_tlvs(ptr, ptr_len, DOT11_MNG_RSN_ID))) {
++			iwe.cmd = IWEVGENIE;
++			iwe.u.data.length = ie->len + 2;
++			event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, (char *)ie);
++		}
++		ptr = ((uint8 *)bi) + bi->ie_offset;
++
++		if ((ie = bcm_parse_tlvs(ptr, ptr_len, DOT11_MNG_MDIE_ID))) {
++			iwe.cmd = IWEVGENIE;
++			iwe.u.data.length = ie->len + 2;
++			event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, (char *)ie);
++		}
++		ptr = ((uint8 *)bi) + bi->ie_offset;
++
++		while ((ie = bcm_parse_tlvs(ptr, ptr_len, DOT11_MNG_WPA_ID))) {
++			/* look for WPS IE */
++			if (ie_is_wps_ie(((uint8 **)&ie), &ptr, &ptr_len)) {
++				iwe.cmd = IWEVGENIE;
++				iwe.u.data.length = ie->len + 2;
++				event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, (char *)ie);
++				break;
++			}
++		}
++
++		ptr = ((uint8 *)bi) + bi->ie_offset;
++		ptr_len = bi->ie_length;
++		while ((ie = bcm_parse_tlvs(ptr, ptr_len, DOT11_MNG_WPA_ID))) {
++			if (ie_is_wpa_ie(((uint8 **)&ie), &ptr, &ptr_len)) {
++				iwe.cmd = IWEVGENIE;
++				iwe.u.data.length = ie->len + 2;
++				event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, (char *)ie);
++				break;
++			}
++		}
++		
++#ifdef BCMWAPI_WPI
++		ptr = ((uint8 *)bi) + sizeof(wl_bss_info_t);
++		ptr_len = bi->ie_length;
++
++		while ((ie = bcm_parse_tlvs(ptr, ptr_len, DOT11_MNG_WAPI_ID))) {
++			WL_TRACE(("found a WAPI IE...\n"));
++#ifdef WAPI_IE_USE_GENIE
++			iwe.cmd = IWEVGENIE;
++			iwe.u.data.length = ie->len + 2;
++			event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, (char *)ie);
++#else /* using CUSTOM event */
++			iwe.cmd = IWEVCUSTOM;
++			custom_event_len = strlen("wapi_ie=") + 2*(ie->len + 2);
++			iwe.u.data.length = custom_event_len;
++
++			buf = kmalloc(custom_event_len+1, GFP_KERNEL);
++			if (buf == NULL)
++			{
++				WL_ERROR(("malloc(%d) returned NULL...\n", custom_event_len));
++				break;
++			}
++
++			memcpy(buf, "wapi_ie=", 8);
++			wpa_snprintf_hex(buf + 8, 2+1, &(ie->id), 1);
++			wpa_snprintf_hex(buf + 10, 2+1, &(ie->len), 1);
++			wpa_snprintf_hex(buf + 12, 2*ie->len+1, ie->data, ie->len);
++			event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, buf);
++			kfree(buf);
++#endif /* WAPI_IE_USE_GENIE */
++			break;
++		}
++#endif /* BCMWAPI_WPI */
++		*event_p = event;
++	}
++
++#endif /* WIRELESS_EXT > 17 */
++	return 0;
++}
++
++#ifndef WL_ESCAN
++static int
++wl_iw_get_scan(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	channel_info_t ci;
++	wl_scan_results_t *list;
++	struct iw_event	iwe;
++	wl_bss_info_t *bi = NULL;
++	int error, i, j;
++	char *event = extra, *end = extra + dwrq->length, *value;
++	uint buflen = dwrq->length;
++	int16 rssi;
++	int channel;
++
++	WL_TRACE(("%s SIOCGIWSCAN\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	/* Check for scan in progress */
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_CHANNEL, &ci, sizeof(ci))))
++		return error;
++	ci.scan_channel = dtoh32(ci.scan_channel);
++	if (ci.scan_channel)
++		return -EAGAIN;
++
++	/* Get scan results (too large to put on the stack) */
++	list = kmalloc(buflen, GFP_KERNEL);
++	if (!list)
++		return -ENOMEM;
++	memset(list, 0, buflen);
++	list->buflen = htod32(buflen);
++	if ((error = dev_wlc_ioctl(dev, WLC_SCAN_RESULTS, list, buflen))) {
++		kfree(list);
++		return error;
++	}
++	list->buflen = dtoh32(list->buflen);
++	list->version = dtoh32(list->version);
++	list->count = dtoh32(list->count);
++
++	ASSERT(list->version == WL_BSS_INFO_VERSION);
++
++	for (i = 0; i < list->count && i < IW_MAX_AP; i++) {
++		bi = bi ? (wl_bss_info_t *)((uintptr)bi + dtoh32(bi->length)) : list->bss_info;
++		ASSERT(((uintptr)bi + dtoh32(bi->length)) <= ((uintptr)list +
++			buflen));
++
++		// terence 20150419: limit the max. rssi to -2 or the bss will be filtered out in android OS
++		rssi = MIN(dtoh16(bi->RSSI), RSSI_MAXVAL);
++		channel = (bi->ctl_ch == 0) ? CHSPEC_CHANNEL(bi->chanspec) : bi->ctl_ch;
++		WL_SCAN(("BSSID="MACSTR", channel=%d, RSSI=%d, SSID=\"%s\"\n",
++			MAC2STR(bi->BSSID.octet), channel, rssi, bi->SSID));
++
++		/* First entry must be the BSSID */
++		iwe.cmd = SIOCGIWAP;
++		iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
++		memcpy(iwe.u.ap_addr.sa_data, &bi->BSSID, ETHER_ADDR_LEN);
++		event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_ADDR_LEN);
++
++		/* SSID */
++		iwe.u.data.length = dtoh32(bi->SSID_len);
++		iwe.cmd = SIOCGIWESSID;
++		iwe.u.data.flags = 1;
++		event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, bi->SSID);
++
++		/* Mode */
++		if (dtoh16(bi->capability) & (DOT11_CAP_ESS | DOT11_CAP_IBSS)) {
++			iwe.cmd = SIOCGIWMODE;
++			if (dtoh16(bi->capability) & DOT11_CAP_ESS)
++				iwe.u.mode = IW_MODE_INFRA;
++			else
++				iwe.u.mode = IW_MODE_ADHOC;
++			event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_UINT_LEN);
++		}
++
++		/* Channel */
++		iwe.cmd = SIOCGIWFREQ;
++
++		iwe.u.freq.m = wf_channel2mhz(CHSPEC_CHANNEL(bi->chanspec),
++			(CHSPEC_IS2G(bi->chanspec)) ?
++			WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G);
++		iwe.u.freq.e = 6;
++		event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_FREQ_LEN);
++
++		/* Channel quality */
++		iwe.cmd = IWEVQUAL;
++		iwe.u.qual.qual = rssi_to_qual(rssi);
++		iwe.u.qual.level = 0x100 + rssi;
++		iwe.u.qual.noise = 0x100 + bi->phy_noise;
++		event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_QUAL_LEN);
++
++		 wl_iw_handle_scanresults_ies(&event, end, info, bi);
++
++		/* Encryption */
++		iwe.cmd = SIOCGIWENCODE;
++		if (dtoh16(bi->capability) & DOT11_CAP_PRIVACY)
++			iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
++		else
++			iwe.u.data.flags = IW_ENCODE_DISABLED;
++		iwe.u.data.length = 0;
++		event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, (char *)event);
++
++		/* Rates */
++		if (bi->rateset.count) {
++			value = event + IW_EV_LCP_LEN;
++			iwe.cmd = SIOCGIWRATE;
++			/* Those two flags are ignored... */
++			iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0;
++			for (j = 0; j < bi->rateset.count && j < IW_MAX_BITRATES; j++) {
++				iwe.u.bitrate.value = (bi->rateset.rates[j] & 0x7f) * 500000;
++				value = IWE_STREAM_ADD_VALUE(info, event, value, end, &iwe,
++					IW_EV_PARAM_LEN);
++			}
++			event = value;
++		}
++	}
++
++	kfree(list);
++
++	dwrq->length = event - extra;
++	dwrq->flags = 0;	/* todo */
++
++	return 0;
++}
++#endif /* WL_ESCAN */
++
++static int
++wl_iw_iscan_get_scan(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	wl_wext_info_t *wext_info = NULL;
++#ifndef WL_ESCAN
++	wl_scan_results_t *list;
++	struct iw_event	iwe;
++	wl_bss_info_t *bi = NULL;
++	int ii, j;
++	int apcnt;
++	char *event = extra, *end = extra + dwrq->length, *value;
++	iscan_buf_t * p_buf;
++	int16 rssi;
++	int channel;
++	iscan_info_t *iscan;
++#endif
++
++	DHD_CHECK(dhd, dev);
++	wext_info = dhd->wext_info;
++#ifdef WL_ESCAN
++	return wl_escan_get_scan(dev, dhd, info, dwrq, extra);
++#else
++	WL_TRACE(("%s SIOCGIWSCAN\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	/* use backup if our thread is not successful */
++	iscan = &wext_info->iscan;
++	if ((!iscan) || (iscan->sysioc_pid < 0)) {
++		return wl_iw_get_scan(dev, info, dwrq, extra);
++	}
++
++	/* Check for scan in progress */
++	if (iscan->iscan_state == ISCAN_STATE_SCANING) {
++		WL_TRACE(("%s: SIOCGIWSCAN GET still scanning\n", dev->name));
++		return -EAGAIN;
++	}
++
++	apcnt = 0;
++	p_buf = iscan->list_hdr;
++	/* Get scan results */
++	while (p_buf != iscan->list_cur) {
++		list = &((wl_iscan_results_t*)p_buf->iscan_buf)->results;
++
++		if (list->version != WL_BSS_INFO_VERSION) {
++			WL_ERROR(("list->version %d != WL_BSS_INFO_VERSION\n", list->version));
++		}
++
++		bi = NULL;
++		for (ii = 0; ii < list->count && apcnt < IW_MAX_AP; apcnt++, ii++) {
++			bi = bi ? (wl_bss_info_t *)((uintptr)bi + dtoh32(bi->length)) : list->bss_info;
++			ASSERT(((uintptr)bi + dtoh32(bi->length)) <= ((uintptr)list +
++				WLC_IW_ISCAN_MAXLEN));
++
++			/* overflow check cover fields before wpa IEs */
++			if (event + ETHER_ADDR_LEN + bi->SSID_len + IW_EV_UINT_LEN + IW_EV_FREQ_LEN +
++				IW_EV_QUAL_LEN >= end)
++				return -E2BIG;
++
++			// terence 20150419: limit the max. rssi to -2 or the bss will be filtered out in android OS
++			rssi = MIN(dtoh16(bi->RSSI), RSSI_MAXVAL);
++			channel = (bi->ctl_ch == 0) ? CHSPEC_CHANNEL(bi->chanspec) : bi->ctl_ch;
++			WL_SCAN(("BSSID="MACSTR", channel=%d, RSSI=%d, SSID=\"%s\"\n",
++				MAC2STR(bi->BSSID.octet), channel, rssi, bi->SSID));
++
++			/* First entry must be the BSSID */
++			iwe.cmd = SIOCGIWAP;
++			iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
++			memcpy(iwe.u.ap_addr.sa_data, &bi->BSSID, ETHER_ADDR_LEN);
++			event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_ADDR_LEN);
++
++			/* SSID */
++			iwe.u.data.length = dtoh32(bi->SSID_len);
++			iwe.cmd = SIOCGIWESSID;
++			iwe.u.data.flags = 1;
++			event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, bi->SSID);
++
++			/* Mode */
++			if (dtoh16(bi->capability) & (DOT11_CAP_ESS | DOT11_CAP_IBSS)) {
++				iwe.cmd = SIOCGIWMODE;
++				if (dtoh16(bi->capability) & DOT11_CAP_ESS)
++					iwe.u.mode = IW_MODE_INFRA;
++				else
++					iwe.u.mode = IW_MODE_ADHOC;
++				event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_UINT_LEN);
++			}
++
++			/* Channel */
++			iwe.cmd = SIOCGIWFREQ;
++			iwe.u.freq.m = wf_channel2mhz(CHSPEC_CHANNEL(bi->chanspec),
++				(CHSPEC_IS2G(bi->chanspec)) ?
++				WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G);
++			iwe.u.freq.e = 6;
++			event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_FREQ_LEN);
++
++			/* Channel quality */
++			iwe.cmd = IWEVQUAL;
++			iwe.u.qual.qual = rssi_to_qual(rssi);
++			iwe.u.qual.level = 0x100 + rssi;
++			iwe.u.qual.noise = 0x100 + bi->phy_noise;
++			event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_QUAL_LEN);
++
++			wl_iw_handle_scanresults_ies(&event, end, info, bi);
++
++			/* Encryption */
++			iwe.cmd = SIOCGIWENCODE;
++			if (dtoh16(bi->capability) & DOT11_CAP_PRIVACY)
++				iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
++			else
++				iwe.u.data.flags = IW_ENCODE_DISABLED;
++			iwe.u.data.length = 0;
++			event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, (char *)event);
++
++			/* Rates */
++			if (bi->rateset.count <= sizeof(bi->rateset.rates)) {
++				if (event + IW_MAX_BITRATES*IW_EV_PARAM_LEN >= end)
++					return -E2BIG;
++
++				value = event + IW_EV_LCP_LEN;
++				iwe.cmd = SIOCGIWRATE;
++				/* Those two flags are ignored... */
++				iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0;
++				for (j = 0; j < bi->rateset.count && j < IW_MAX_BITRATES; j++) {
++					iwe.u.bitrate.value = (bi->rateset.rates[j] & 0x7f) * 500000;
++					value = IWE_STREAM_ADD_VALUE(info, event, value, end, &iwe,
++						IW_EV_PARAM_LEN);
++				}
++				event = value;
++			}
++		}
++		p_buf = p_buf->next;
++	} /* while (p_buf) */
++
++	dwrq->length = event - extra;
++	dwrq->flags = 0;	/* todo */
++	WL_SCAN(("apcnt=%d\n", apcnt));
++
++	return 0;
++#endif
++}
++#endif /* WIRELESS_EXT > 13 */
++
++
++static int
++wl_iw_set_essid(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wlc_ssid_t ssid;
++	int error;
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	wl_wext_info_t *wext_info = NULL;
++
++	WL_TRACE(("%s: SIOCSIWESSID\n", dev->name));
++	DHD_CHECK(dhd, dev);
++	wext_info = dhd->wext_info;
++
++	/* default Broadcast SSID */
++	memset(&ssid, 0, sizeof(ssid));
++	if (dwrq->length && extra) {
++#if WIRELESS_EXT > 20
++		ssid.SSID_len = MIN(sizeof(ssid.SSID), dwrq->length);
++#else
++		ssid.SSID_len = MIN(sizeof(ssid.SSID), dwrq->length-1);
++#endif
++		memcpy(ssid.SSID, extra, ssid.SSID_len);
++		ssid.SSID_len = htod32(ssid.SSID_len);
++
++		if (wext_info) {
++			memcpy(wext_info->conn_info.ssid.SSID, ssid.SSID, ssid.SSID_len);
++			wext_info->conn_info.ssid.SSID_len = ssid.SSID_len;
++		}
++		if (wext_info && memcmp(&ether_null, &wext_info->conn_info.bssid, ETHER_ADDR_LEN)) {
++			if ((error = wl_ext_connect(dev, &wext_info->conn_info)))
++				return error;
++		} else {
++			if ((error = dev_wlc_ioctl(dev, WLC_SET_SSID, &ssid, sizeof(ssid)))) {
++				WL_ERROR(("WLC_SET_SSID failed (%d).\n", error));
++				return error;
++			}
++			WL_MSG(dev->name, "join SSID=\"%s\"\n", ssid.SSID);
++		}
++		wl_iw_update_connect_status(dev, WL_EXT_STATUS_CONNECTING);
++	}
++	/* If essid null then it is "iwconfig <interface> essid off" command */
++	else {
++		scb_val_t scbval;
++		bzero(&scbval, sizeof(scb_val_t));
++		WL_MSG(dev->name, "WLC_DISASSOC\n");
++		if ((error = dev_wlc_ioctl(dev, WLC_DISASSOC, &scbval, sizeof(scb_val_t)))) {
++			WL_ERROR(("WLC_DISASSOC failed (%d).\n", error));
++			return error;
++		}
++		wl_iw_update_connect_status(dev, WL_EXT_STATUS_DISCONNECTING);
++	}
++	return 0;
++}
++
++static int
++wl_iw_get_essid(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wlc_ssid_t ssid;
++	int error;
++
++	WL_TRACE(("%s: SIOCGIWESSID\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_SSID, &ssid, sizeof(ssid)))) {
++		WL_ERROR(("Error getting the SSID %d\n", error));
++		return error;
++	}
++
++	ssid.SSID_len = dtoh32(ssid.SSID_len);
++
++	/* Max SSID length check */
++	if (ssid.SSID_len > IW_ESSID_MAX_SIZE) {
++		ssid.SSID_len = IW_ESSID_MAX_SIZE;
++	}
++
++	/* Get the current SSID */
++	memcpy(extra, ssid.SSID, ssid.SSID_len);
++
++	/* NULL terminating as length of extra buffer is IW_ESSID_MAX_SIZE ie 32 */
++	extra[IW_ESSID_MAX_SIZE] = '\0';
++
++	dwrq->length = ssid.SSID_len;
++
++	dwrq->flags = 1; /* active */
++
++	return 0;
++}
++
++static int
++wl_iw_set_nick(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_iw_t *iw = IW_DEV_IF(dev);
++	WL_TRACE(("%s: SIOCSIWNICKN\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	/* Check the size of the string */
++	if (dwrq->length > sizeof(iw->nickname))
++		return -E2BIG;
++
++	memcpy(iw->nickname, extra, dwrq->length);
++	iw->nickname[dwrq->length - 1] = '\0';
++
++	return 0;
++}
++
++static int
++wl_iw_get_nick(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_iw_t *iw = IW_DEV_IF(dev);
++	WL_TRACE(("%s: SIOCGIWNICKN\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	strcpy(extra, iw->nickname);
++	dwrq->length = strlen(extra) + 1;
++
++	return 0;
++}
++
++static int wl_iw_set_rate(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	wl_rateset_t rateset;
++	int error, rate, i, error_bg, error_a;
++
++	WL_TRACE(("%s: SIOCSIWRATE\n", dev->name));
++
++	/* Get current rateset */
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_CURR_RATESET, &rateset, sizeof(rateset))))
++		return error;
++
++	rateset.count = dtoh32(rateset.count);
++
++	if (vwrq->value < 0) {
++		/* Select maximum rate */
++		rate = rateset.rates[rateset.count - 1] & 0x7f;
++	} else if (vwrq->value < rateset.count) {
++		/* Select rate by rateset index */
++		rate = rateset.rates[vwrq->value] & 0x7f;
++	} else {
++		/* Specified rate in bps */
++		rate = vwrq->value / 500000;
++	}
++
++	if (vwrq->fixed) {
++		/*
++			Set rate override,
++			Since the is a/b/g-blind, both a/bg_rate are enforced.
++		*/
++		error_bg = dev_wlc_intvar_set(dev, "bg_rate", rate);
++		error_a = dev_wlc_intvar_set(dev, "a_rate", rate);
++
++		if (error_bg && error_a)
++			return (error_bg | error_a);
++	} else {
++		/*
++			clear rate override
++			Since the is a/b/g-blind, both a/bg_rate are enforced.
++		*/
++		/* 0 is for clearing rate override */
++		error_bg = dev_wlc_intvar_set(dev, "bg_rate", 0);
++		/* 0 is for clearing rate override */
++		error_a = dev_wlc_intvar_set(dev, "a_rate", 0);
++
++		if (error_bg && error_a)
++			return (error_bg | error_a);
++
++		/* Remove rates above selected rate */
++		for (i = 0; i < rateset.count; i++)
++			if ((rateset.rates[i] & 0x7f) > rate)
++				break;
++		rateset.count = htod32(i);
++
++		/* Set current rateset */
++		if ((error = dev_wlc_ioctl(dev, WLC_SET_RATESET, &rateset, sizeof(rateset))))
++			return error;
++	}
++
++	return 0;
++}
++
++static int wl_iw_get_rate(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, rate;
++
++	WL_TRACE(("%s: SIOCGIWRATE\n", dev->name));
++
++	/* Report the current tx rate */
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_RATE, &rate, sizeof(rate))))
++		return error;
++	rate = dtoh32(rate);
++	vwrq->value = rate * 500000;
++
++	return 0;
++}
++
++static int
++wl_iw_set_rts(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, rts;
++
++	WL_TRACE(("%s: SIOCSIWRTS\n", dev->name));
++
++	if (vwrq->disabled)
++		rts = DOT11_DEFAULT_RTS_LEN;
++	else if (vwrq->value < 0 || vwrq->value > DOT11_DEFAULT_RTS_LEN)
++		return -EINVAL;
++	else
++		rts = vwrq->value;
++
++	if ((error = dev_wlc_intvar_set(dev, "rtsthresh", rts)))
++		return error;
++
++	return 0;
++}
++
++static int
++wl_iw_get_rts(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, rts;
++
++	WL_TRACE(("%s: SIOCGIWRTS\n", dev->name));
++
++	if ((error = dev_wlc_intvar_get(dev, "rtsthresh", &rts)))
++		return error;
++
++	vwrq->value = rts;
++	vwrq->disabled = (rts >= DOT11_DEFAULT_RTS_LEN);
++	vwrq->fixed = 1;
++
++	return 0;
++}
++
++static int
++wl_iw_set_frag(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, frag;
++
++	WL_TRACE(("%s: SIOCSIWFRAG\n", dev->name));
++
++	if (vwrq->disabled)
++		frag = DOT11_DEFAULT_FRAG_LEN;
++	else if (vwrq->value < 0 || vwrq->value > DOT11_DEFAULT_FRAG_LEN)
++		return -EINVAL;
++	else
++		frag = vwrq->value;
++
++	if ((error = dev_wlc_intvar_set(dev, "fragthresh", frag)))
++		return error;
++
++	return 0;
++}
++
++static int
++wl_iw_get_frag(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, fragthreshold;
++
++	WL_TRACE(("%s: SIOCGIWFRAG\n", dev->name));
++
++	if ((error = dev_wlc_intvar_get(dev, "fragthresh", &fragthreshold)))
++		return error;
++
++	vwrq->value = fragthreshold;
++	vwrq->disabled = (fragthreshold >= DOT11_DEFAULT_FRAG_LEN);
++	vwrq->fixed = 1;
++
++	return 0;
++}
++
++static int
++wl_iw_set_txpow(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, disable;
++	uint16 txpwrmw;
++	WL_TRACE(("%s: SIOCSIWTXPOW\n", dev->name));
++
++	/* Make sure radio is off or on as far as software is concerned */
++	disable = vwrq->disabled ? WL_RADIO_SW_DISABLE : 0;
++	disable += WL_RADIO_SW_DISABLE << 16;
++
++	disable = htod32(disable);
++	if ((error = dev_wlc_ioctl(dev, WLC_SET_RADIO, &disable, sizeof(disable))))
++		return error;
++
++	/* If Radio is off, nothing more to do */
++	if (disable & WL_RADIO_SW_DISABLE)
++		return 0;
++
++	/* Only handle mW */
++	if (!(vwrq->flags & IW_TXPOW_MWATT))
++		return -EINVAL;
++
++	/* Value < 0 means just "on" or "off" */
++	if (vwrq->value < 0)
++		return 0;
++
++	if (vwrq->value > 0xffff) txpwrmw = 0xffff;
++	else txpwrmw = (uint16)vwrq->value;
++
++
++	error = dev_wlc_intvar_set(dev, "qtxpower", (int)(bcm_mw_to_qdbm(txpwrmw)));
++	return error;
++}
++
++static int
++wl_iw_get_txpow(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, disable, txpwrdbm;
++	uint8 result;
++
++	WL_TRACE(("%s: SIOCGIWTXPOW\n", dev->name));
++
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_RADIO, &disable, sizeof(disable))) ||
++	    (error = dev_wlc_intvar_get(dev, "qtxpower", &txpwrdbm)))
++		return error;
++
++	disable = dtoh32(disable);
++	result = (uint8)(txpwrdbm & ~WL_TXPWR_OVERRIDE);
++	vwrq->value = (int32)bcm_qdbm_to_mw(result);
++	vwrq->fixed = 0;
++	vwrq->disabled = (disable & (WL_RADIO_SW_DISABLE | WL_RADIO_HW_DISABLE)) ? 1 : 0;
++	vwrq->flags = IW_TXPOW_MWATT;
++
++	return 0;
++}
++
++#if WIRELESS_EXT > 10
++static int
++wl_iw_set_retry(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, lrl, srl;
++
++	WL_TRACE(("%s: SIOCSIWRETRY\n", dev->name));
++
++	/* Do not handle "off" or "lifetime" */
++	if (vwrq->disabled || (vwrq->flags & IW_RETRY_LIFETIME))
++		return -EINVAL;
++
++	/* Handle "[min|max] limit" */
++	if (vwrq->flags & IW_RETRY_LIMIT) {
++		/* "max limit" or just "limit" */
++#if WIRELESS_EXT > 20
++		if ((vwrq->flags & IW_RETRY_LONG) ||(vwrq->flags & IW_RETRY_MAX) ||
++			!((vwrq->flags & IW_RETRY_SHORT) || (vwrq->flags & IW_RETRY_MIN)))
++#else
++		if ((vwrq->flags & IW_RETRY_MAX) || !(vwrq->flags & IW_RETRY_MIN))
++#endif /* WIRELESS_EXT > 20 */
++		{
++			lrl = htod32(vwrq->value);
++			if ((error = dev_wlc_ioctl(dev, WLC_SET_LRL, &lrl, sizeof(lrl))))
++				return error;
++		}
++		/* "min limit" or just "limit" */
++#if WIRELESS_EXT > 20
++		if ((vwrq->flags & IW_RETRY_SHORT) ||(vwrq->flags & IW_RETRY_MIN) ||
++			!((vwrq->flags & IW_RETRY_LONG) || (vwrq->flags & IW_RETRY_MAX)))
++#else
++		if ((vwrq->flags & IW_RETRY_MIN) || !(vwrq->flags & IW_RETRY_MAX))
++#endif /* WIRELESS_EXT > 20 */
++		{
++			srl = htod32(vwrq->value);
++			if ((error = dev_wlc_ioctl(dev, WLC_SET_SRL, &srl, sizeof(srl))))
++				return error;
++		}
++	}
++
++	return 0;
++}
++
++static int
++wl_iw_get_retry(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, lrl, srl;
++
++	WL_TRACE(("%s: SIOCGIWRETRY\n", dev->name));
++
++	vwrq->disabled = 0;      /* Can't be disabled */
++
++	/* Do not handle lifetime queries */
++	if ((vwrq->flags & IW_RETRY_TYPE) == IW_RETRY_LIFETIME)
++		return -EINVAL;
++
++	/* Get retry limits */
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_LRL, &lrl, sizeof(lrl))) ||
++	    (error = dev_wlc_ioctl(dev, WLC_GET_SRL, &srl, sizeof(srl))))
++		return error;
++
++	lrl = dtoh32(lrl);
++	srl = dtoh32(srl);
++
++	/* Note : by default, display the min retry number */
++	if (vwrq->flags & IW_RETRY_MAX) {
++		vwrq->flags = IW_RETRY_LIMIT | IW_RETRY_MAX;
++		vwrq->value = lrl;
++	} else {
++		vwrq->flags = IW_RETRY_LIMIT;
++		vwrq->value = srl;
++		if (srl != lrl)
++			vwrq->flags |= IW_RETRY_MIN;
++	}
++
++	return 0;
++}
++#endif /* WIRELESS_EXT > 10 */
++
++static int
++wl_iw_set_encode(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_wsec_key_t key;
++	int error, val, wsec;
++
++	WL_TRACE(("%s: SIOCSIWENCODE\n", dev->name));
++
++	memset(&key, 0, sizeof(key));
++
++	if ((dwrq->flags & IW_ENCODE_INDEX) == 0) {
++		/* Find the current key */
++		for (key.index = 0; key.index < DOT11_MAX_DEFAULT_KEYS; key.index++) {
++			val = htod32(key.index);
++			if ((error = dev_wlc_ioctl(dev, WLC_GET_KEY_PRIMARY, &val, sizeof(val))))
++				return error;
++			val = dtoh32(val);
++			if (val)
++				break;
++		}
++		/* Default to 0 */
++		if (key.index == DOT11_MAX_DEFAULT_KEYS)
++			key.index = 0;
++	} else {
++		key.index = (dwrq->flags & IW_ENCODE_INDEX) - 1;
++		if (key.index >= DOT11_MAX_DEFAULT_KEYS)
++			return -EINVAL;
++	}
++
++	/* Interpret "off" to mean no encryption */
++	wsec = (dwrq->flags & IW_ENCODE_DISABLED) ? 0 : WEP_ENABLED;
++
++	if ((error = dev_wlc_intvar_set(dev, "wsec", wsec)))
++		return error;
++
++	/* Old API used to pass a NULL pointer instead of IW_ENCODE_NOKEY */
++	if (!extra || !dwrq->length || (dwrq->flags & IW_ENCODE_NOKEY)) {
++		/* Just select a new current key */
++		val = htod32(key.index);
++		if ((error = dev_wlc_ioctl(dev, WLC_SET_KEY_PRIMARY, &val, sizeof(val))))
++			return error;
++	} else {
++		key.len = dwrq->length;
++
++		if (dwrq->length > sizeof(key.data))
++			return -EINVAL;
++
++		memcpy(key.data, extra, dwrq->length);
++
++		key.flags = WL_PRIMARY_KEY;
++		switch (key.len) {
++		case WEP1_KEY_SIZE:
++			key.algo = CRYPTO_ALGO_WEP1;
++			break;
++		case WEP128_KEY_SIZE:
++			key.algo = CRYPTO_ALGO_WEP128;
++			break;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 14)
++		case TKIP_KEY_SIZE:
++			key.algo = CRYPTO_ALGO_TKIP;
++			break;
++#endif
++		case AES_KEY_SIZE:
++			key.algo = CRYPTO_ALGO_AES_CCM;
++			break;
++		default:
++			return -EINVAL;
++		}
++
++		/* Set the new key/index */
++		swap_key_from_BE(&key);
++		if ((error = dev_wlc_ioctl(dev, WLC_SET_KEY, &key, sizeof(key))))
++			return error;
++	}
++
++	/* Interpret "restricted" to mean shared key authentication */
++	val = (dwrq->flags & IW_ENCODE_RESTRICTED) ? 1 : 0;
++	val = htod32(val);
++	if ((error = dev_wlc_ioctl(dev, WLC_SET_AUTH, &val, sizeof(val))))
++		return error;
++
++	return 0;
++}
++
++static int
++wl_iw_get_encode(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_wsec_key_t key;
++	int error, val, wsec, auth;
++
++	WL_TRACE(("%s: SIOCGIWENCODE\n", dev->name));
++
++	/* assure default values of zero for things we don't touch */
++	bzero(&key, sizeof(wl_wsec_key_t));
++
++	if ((dwrq->flags & IW_ENCODE_INDEX) == 0) {
++		/* Find the current key */
++		for (key.index = 0; key.index < DOT11_MAX_DEFAULT_KEYS; key.index++) {
++			val = key.index;
++			if ((error = dev_wlc_ioctl(dev, WLC_GET_KEY_PRIMARY, &val, sizeof(val))))
++				return error;
++			val = dtoh32(val);
++			if (val)
++				break;
++		}
++	} else
++		key.index = (dwrq->flags & IW_ENCODE_INDEX) - 1;
++
++	if (key.index >= DOT11_MAX_DEFAULT_KEYS)
++		key.index = 0;
++
++	/* Get info */
++
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_WSEC, &wsec, sizeof(wsec))) ||
++	    (error = dev_wlc_ioctl(dev, WLC_GET_AUTH, &auth, sizeof(auth))))
++		return error;
++
++	swap_key_to_BE(&key);
++
++	wsec = dtoh32(wsec);
++	auth = dtoh32(auth);
++	/* Get key length */
++	dwrq->length = MIN(IW_ENCODING_TOKEN_MAX, key.len);
++
++	/* Get flags */
++	dwrq->flags = key.index + 1;
++	if (!(wsec & (WEP_ENABLED | TKIP_ENABLED | AES_ENABLED))) {
++		/* Interpret "off" to mean no encryption */
++		dwrq->flags |= IW_ENCODE_DISABLED;
++	}
++	if (auth) {
++		/* Interpret "restricted" to mean shared key authentication */
++		dwrq->flags |= IW_ENCODE_RESTRICTED;
++	}
++
++	/* Get key */
++	if (dwrq->length && extra)
++		memcpy(extra, key.data, dwrq->length);
++
++	return 0;
++}
++
++static int
++wl_iw_set_power(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, pm;
++
++	WL_TRACE(("%s: SIOCSIWPOWER\n", dev->name));
++
++	pm = vwrq->disabled ? PM_OFF : PM_MAX;
++
++	pm = htod32(pm);
++	if ((error = dev_wlc_ioctl(dev, WLC_SET_PM, &pm, sizeof(pm))))
++		return error;
++
++	return 0;
++}
++
++static int
++wl_iw_get_power(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, pm;
++
++	WL_TRACE(("%s: SIOCGIWPOWER\n", dev->name));
++
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_PM, &pm, sizeof(pm))))
++		return error;
++
++	pm = dtoh32(pm);
++	vwrq->disabled = pm ? 0 : 1;
++	vwrq->flags = IW_POWER_ALL_R;
++
++	return 0;
++}
++
++#if WIRELESS_EXT > 17
++static int
++wl_iw_set_wpaie(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *iwp,
++	char *extra
++)
++{
++#if defined(BCMWAPI_WPI)
++	uchar buf[WLC_IOCTL_SMLEN] = {0};
++	uchar *p = buf;
++	int wapi_ie_size;
++
++	WL_TRACE(("%s: SIOCSIWGENIE\n", dev->name));
++
++	if (extra[0] == DOT11_MNG_WAPI_ID)
++	{
++		wapi_ie_size = iwp->length;
++		memcpy(p, extra, iwp->length);
++		dev_wlc_bufvar_set(dev, "wapiie", buf, wapi_ie_size);
++	}
++	else
++#endif
++		dev_wlc_bufvar_set(dev, "wpaie", extra, iwp->length);
++
++	return 0;
++}
++
++static int
++wl_iw_get_wpaie(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *iwp,
++	char *extra
++)
++{
++	WL_TRACE(("%s: SIOCGIWGENIE\n", dev->name));
++	iwp->length = 64;
++	dev_wlc_bufvar_get(dev, "wpaie", extra, iwp->length);
++	return 0;
++}
++
++static int
++wl_iw_set_encodeext(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_wsec_key_t key;
++	int error;
++	struct iw_encode_ext *iwe;
++
++	WL_TRACE(("%s: SIOCSIWENCODEEXT\n", dev->name));
++
++	memset(&key, 0, sizeof(key));
++	iwe = (struct iw_encode_ext *)extra;
++
++	/* disable encryption completely  */
++	if (dwrq->flags & IW_ENCODE_DISABLED) {
++
++	}
++
++	/* get the key index */
++	key.index = 0;
++	if (dwrq->flags & IW_ENCODE_INDEX)
++		key.index = (dwrq->flags & IW_ENCODE_INDEX) - 1;
++
++	key.len = iwe->key_len;
++
++	/* Instead of bcast for ea address for default wep keys, driver needs it to be Null */
++	if (!ETHER_ISMULTI(iwe->addr.sa_data))
++		bcopy((void *)&iwe->addr.sa_data, (char *)&key.ea, ETHER_ADDR_LEN);
++
++	/* check for key index change */
++	if (key.len == 0) {
++		if (iwe->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) {
++			WL_WSEC(("Changing the the primary Key to %d\n", key.index));
++			/* change the key index .... */
++			key.index = htod32(key.index);
++			error = dev_wlc_ioctl(dev, WLC_SET_KEY_PRIMARY,
++				&key.index, sizeof(key.index));
++			if (error)
++				return error;
++		}
++		/* key delete */
++		else {
++			swap_key_from_BE(&key);
++			error = dev_wlc_ioctl(dev, WLC_SET_KEY, &key, sizeof(key));
++			if (error)
++				return error;
++		}
++	}
++	/* This case is used to allow an external 802.1x supplicant
++	 * to pass the PMK to the in-driver supplicant for use in
++	 * the 4-way handshake.
++	 */
++	else if (iwe->alg == IW_ENCODE_ALG_PMK) {
++		int j;
++		wsec_pmk_t pmk;
++		char keystring[WSEC_MAX_PSK_LEN + 1];
++		char* charptr = keystring;
++		uint len;
++
++		/* copy the raw hex key to the appropriate format */
++		for (j = 0; j < (WSEC_MAX_PSK_LEN / 2); j++) {
++			(void)snprintf(charptr, 3, "%02x", iwe->key[j]);
++			charptr += 2;
++		}
++		len = strlen(keystring);
++		pmk.key_len = htod16(len);
++		bcopy(keystring, pmk.key, len);
++		pmk.flags = htod16(WSEC_PASSPHRASE);
++
++		WL_WSEC(("set key %s\n", keystring));
++		error = dev_wlc_ioctl(dev, WLC_SET_WSEC_PMK, &pmk, sizeof(pmk));
++		if (error) {
++			WL_ERROR(("WLC_SET_WSEC_PMK error %d\n", error));
++			return error;
++		}
++	}
++
++	else {
++		if (iwe->key_len > sizeof(key.data))
++			return -EINVAL;
++
++		WL_WSEC(("Setting the key index %d\n", key.index));
++		if (iwe->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) {
++			WL_WSEC(("key is a Primary Key\n"));
++			key.flags = WL_PRIMARY_KEY;
++		}
++
++		bcopy((void *)iwe->key, key.data, iwe->key_len);
++
++		if (iwe->alg == IW_ENCODE_ALG_TKIP) {
++			uint8 keybuf[8];
++			bcopy(&key.data[24], keybuf, sizeof(keybuf));
++			bcopy(&key.data[16], &key.data[24], sizeof(keybuf));
++			bcopy(keybuf, &key.data[16], sizeof(keybuf));
++		}
++
++		/* rx iv */
++		if (iwe->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) {
++			uchar *ivptr;
++			ivptr = (uchar *)iwe->rx_seq;
++			key.rxiv.hi = (ivptr[5] << 24) | (ivptr[4] << 16) |
++				(ivptr[3] << 8) | ivptr[2];
++			key.rxiv.lo = (ivptr[1] << 8) | ivptr[0];
++			key.iv_initialized = TRUE;
++		}
++
++		switch (iwe->alg) {
++			case IW_ENCODE_ALG_NONE:
++				key.algo = CRYPTO_ALGO_OFF;
++				break;
++			case IW_ENCODE_ALG_WEP:
++				if (iwe->key_len == WEP1_KEY_SIZE)
++					key.algo = CRYPTO_ALGO_WEP1;
++				else
++					key.algo = CRYPTO_ALGO_WEP128;
++				break;
++			case IW_ENCODE_ALG_TKIP:
++				key.algo = CRYPTO_ALGO_TKIP;
++				break;
++			case IW_ENCODE_ALG_CCMP:
++				key.algo = CRYPTO_ALGO_AES_CCM;
++				break;
++#ifdef BCMWAPI_WPI
++			case IW_ENCODE_ALG_SM4:
++				key.algo = CRYPTO_ALGO_SMS4;
++				if (iwe->ext_flags & IW_ENCODE_EXT_GROUP_KEY) {
++					key.flags &= ~WL_PRIMARY_KEY;
++				}
++				break;
++#endif
++			default:
++				break;
++		}
++		swap_key_from_BE(&key);
++
++		dhd_wait_pend8021x(dev);
++
++		error = dev_wlc_ioctl(dev, WLC_SET_KEY, &key, sizeof(key));
++		if (error)
++			return error;
++		wl_iw_update_connect_status(dev, WL_EXT_STATUS_ADD_KEY);
++	}
++	return 0;
++}
++
++/* wpa2 pmk list */
++static int
++wl_iw_set_pmksa(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	struct pmk_list *pmk_list = NULL;
++	struct iw_pmksa *iwpmksa;
++	uint i;
++	char eabuf[ETHER_ADDR_STR_LEN];
++	pmkid_t *pmkid_array = NULL;
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	wl_wext_info_t *wext_info = NULL;
++
++	WL_TRACE(("%s: SIOCSIWPMKSA\n", dev->name));
++	DHD_CHECK(dhd, dev);
++	wext_info = dhd->wext_info;
++ 	pmk_list = &wext_info->pmk_list;
++	if (pmk_list)
++		pmkid_array = pmk_list->pmkids.pmkid;
++	iwpmksa = (struct iw_pmksa *)extra;
++	bzero((char *)eabuf, ETHER_ADDR_STR_LEN);
++	if (iwpmksa->cmd == IW_PMKSA_FLUSH) {
++		WL_TRACE(("wl_iw_set_pmksa - IW_PMKSA_FLUSH\n"));
++		bzero((char *)pmk_list, sizeof(struct pmk_list));
++	}
++	if (iwpmksa->cmd == IW_PMKSA_REMOVE) {
++		pmkid_list_t pmkid, *pmkidptr;
++		pmkidptr = &pmkid;
++		bcopy(&iwpmksa->bssid.sa_data[0], &pmkidptr->pmkid[0].BSSID, ETHER_ADDR_LEN);
++		bcopy(&iwpmksa->pmkid[0], &pmkidptr->pmkid[0].PMKID, WPA2_PMKID_LEN);
++		{
++			uint j;
++			WL_TRACE(("wl_iw_set_pmksa,IW_PMKSA_REMOVE - PMKID: %s = ",
++				bcm_ether_ntoa(&pmkidptr->pmkid[0].BSSID,
++				eabuf)));
++			for (j = 0; j < WPA2_PMKID_LEN; j++)
++				WL_TRACE(("%02x ", pmkidptr->pmkid[0].PMKID[j]));
++			WL_TRACE(("\n"));
++		}
++		for (i = 0; i < pmk_list->pmkids.npmkid; i++)
++			if (!bcmp(&iwpmksa->bssid.sa_data[0], &pmkid_array[i].BSSID,
++				ETHER_ADDR_LEN))
++				break;
++		for (; i < pmk_list->pmkids.npmkid; i++) {
++			bcopy(&pmkid_array[i+1].BSSID,
++				&pmkid_array[i].BSSID,
++				ETHER_ADDR_LEN);
++			bcopy(&pmkid_array[i+1].PMKID,
++				&pmkid_array[i].PMKID,
++				WPA2_PMKID_LEN);
++		}
++		pmk_list->pmkids.npmkid--;
++	}
++	if (iwpmksa->cmd == IW_PMKSA_ADD) {
++		bcopy(&iwpmksa->bssid.sa_data[0],
++			&pmkid_array[pmk_list->pmkids.npmkid].BSSID,
++			ETHER_ADDR_LEN);
++		bcopy(&iwpmksa->pmkid[0], &pmkid_array[pmk_list->pmkids.npmkid].PMKID,
++			WPA2_PMKID_LEN);
++		{
++			uint j;
++			uint k;
++			k = pmk_list->pmkids.npmkid;
++			BCM_REFERENCE(k);
++			WL_TRACE(("wl_iw_set_pmksa,IW_PMKSA_ADD - PMKID: %s = ",
++				bcm_ether_ntoa(&pmkid_array[k].BSSID,
++				eabuf)));
++			for (j = 0; j < WPA2_PMKID_LEN; j++)
++				WL_TRACE(("%02x ", pmkid_array[k].PMKID[j]));
++			WL_TRACE(("\n"));
++		}
++		pmk_list->pmkids.npmkid++;
++	}
++	WL_TRACE(("PRINTING pmkid LIST - No of elements %d\n", pmk_list->pmkids.npmkid));
++	for (i = 0; i < pmk_list->pmkids.npmkid; i++) {
++		uint j;
++		WL_TRACE(("PMKID[%d]: %s = ", i,
++			bcm_ether_ntoa(&pmkid_array[i].BSSID,
++			eabuf)));
++		for (j = 0; j < WPA2_PMKID_LEN; j++)
++			WL_TRACE(("%02x ", pmkid_array[i].PMKID[j]));
++		printf("\n");
++	}
++	dev_wlc_bufvar_set(dev, "pmkid_info", (char *)pmk_list, sizeof(struct pmk_list));
++	return 0;
++}
++
++static int
++wl_iw_get_encodeext(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	WL_TRACE(("%s: SIOCGIWENCODEEXT\n", dev->name));
++	return 0;
++}
++
++static int
++wl_iw_set_wpaauth(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error = 0;
++	int paramid;
++	int paramval;
++	uint32 cipher_combined;
++	int val = 0;
++	wl_iw_t *iw = IW_DEV_IF(dev);
++
++	WL_TRACE(("%s: SIOCSIWAUTH\n", dev->name));
++
++	paramid = vwrq->flags & IW_AUTH_INDEX;
++	paramval = vwrq->value;
++
++	WL_TRACE(("%s: SIOCSIWAUTH, paramid = 0x%0x, paramval = 0x%0x\n",
++		dev->name, paramid, paramval));
++
++	switch (paramid) {
++
++	case IW_AUTH_WPA_VERSION:
++		/* supported wpa version disabled or wpa or wpa2 */
++		if (paramval & IW_AUTH_WPA_VERSION_DISABLED)
++			val = WPA_AUTH_DISABLED;
++		else if (paramval & (IW_AUTH_WPA_VERSION_WPA))
++			val = WPA_AUTH_PSK | WPA_AUTH_UNSPECIFIED;
++		else if (paramval & IW_AUTH_WPA_VERSION_WPA2)
++			val = WPA2_AUTH_PSK | WPA2_AUTH_UNSPECIFIED;
++#ifdef BCMWAPI_WPI
++		else if (paramval & IW_AUTH_WAPI_VERSION_1)
++			val = WAPI_AUTH_UNSPECIFIED;
++#endif
++		WL_TRACE(("%d: setting wpa_auth to 0x%0x\n", __LINE__, val));
++		if ((error = dev_wlc_intvar_set(dev, "wpa_auth", val)))
++			return error;
++		break;
++
++	case IW_AUTH_CIPHER_PAIRWISE:
++	case IW_AUTH_CIPHER_GROUP: {
++		int fbt_cap = 0;
++
++		if (paramid == IW_AUTH_CIPHER_PAIRWISE) {
++			iw->pwsec = paramval;
++		}
++		else {
++			iw->gwsec = paramval;
++		}
++
++		if ((error = dev_wlc_intvar_get(dev, "wsec", &val))) {
++			WL_ERROR(("wsec error %d\n", error));
++			return error;
++		}
++		WL_WSEC(("get wsec=0x%x\n", val));
++
++		cipher_combined = iw->gwsec | iw->pwsec;
++		val &= ~(WEP_ENABLED | TKIP_ENABLED | AES_ENABLED);
++		if (cipher_combined & (IW_AUTH_CIPHER_WEP40 | IW_AUTH_CIPHER_WEP104))
++			val |= WEP_ENABLED;
++		if (cipher_combined & IW_AUTH_CIPHER_TKIP)
++			val |= TKIP_ENABLED;
++		if (cipher_combined & IW_AUTH_CIPHER_CCMP)
++			val |= AES_ENABLED;
++#ifdef BCMWAPI_WPI
++		val &= ~SMS4_ENABLED;
++		if (cipher_combined & IW_AUTH_CIPHER_SMS4)
++			val |= SMS4_ENABLED;
++#endif
++
++		if (iw->privacy_invoked && !val) {
++			WL_WSEC(("%s: 'Privacy invoked' TRUE but clearing wsec, assuming "
++			         "we're a WPS enrollee\n", dev->name));
++			if ((error = dev_wlc_intvar_set(dev, "is_WPS_enrollee", TRUE))) {
++				WL_WSEC(("Failed to set iovar is_WPS_enrollee\n"));
++				return error;
++			}
++		} else if (val) {
++			if ((error = dev_wlc_intvar_set(dev, "is_WPS_enrollee", FALSE))) {
++				WL_WSEC(("Failed to clear iovar is_WPS_enrollee\n"));
++				return error;
++			}
++		}
++
++		WL_WSEC(("set wsec=0x%x\n", val));
++		if ((error = dev_wlc_intvar_set(dev, "wsec", val))) {
++			WL_ERROR(("wsec error %d\n", error));
++			return error;
++		}
++
++		/* Ensure in-dongle supplicant is turned on when FBT wants to do the 4-way
++		 * handshake.
++		 */
++		if (dev_wlc_intvar_get(dev, "fbt_cap", &fbt_cap) == 0) {
++			WL_WSEC(("get fbt_cap=0x%x\n", fbt_cap));
++			if (fbt_cap == WLC_FBT_CAP_DRV_4WAY_AND_REASSOC) {
++				if ((paramid == IW_AUTH_CIPHER_PAIRWISE) && (val & AES_ENABLED)) {
++					if ((error = dev_wlc_intvar_set(dev, "sup_wpa", 1))) {
++						WL_ERROR(("sup_wpa 1 error %d\n", error));
++						return error;
++					}
++				}
++				else if (val == 0) {
++					if ((error = dev_wlc_intvar_set(dev, "sup_wpa", 0))) {
++						WL_ERROR(("sup_wpa 0 error %d\n", error));
++						return error;
++					}
++				}
++			}
++		}
++		break;
++	}
++
++	case IW_AUTH_KEY_MGMT:
++		if ((error = dev_wlc_intvar_get(dev, "wpa_auth", &val))) {
++			WL_ERROR(("wpa_auth error %d\n", error));
++			return error;
++		}
++		WL_WSEC(("get wpa_auth to %d\n", val));
++
++		if (val & (WPA_AUTH_PSK | WPA_AUTH_UNSPECIFIED)) {
++			if (paramval & (IW_AUTH_KEY_MGMT_FT_PSK | IW_AUTH_KEY_MGMT_PSK))
++				val = WPA_AUTH_PSK;
++			else
++				val = WPA_AUTH_UNSPECIFIED;
++			if (paramval & (IW_AUTH_KEY_MGMT_FT_802_1X | IW_AUTH_KEY_MGMT_FT_PSK))
++				val |= WPA2_AUTH_FT;
++		}
++		else if (val & (WPA2_AUTH_PSK | WPA2_AUTH_UNSPECIFIED)) {
++			if (paramval & (IW_AUTH_KEY_MGMT_FT_PSK | IW_AUTH_KEY_MGMT_PSK))
++				val = WPA2_AUTH_PSK;
++			else
++				val = WPA2_AUTH_UNSPECIFIED;
++			if (paramval & (IW_AUTH_KEY_MGMT_FT_802_1X | IW_AUTH_KEY_MGMT_FT_PSK))
++				val |= WPA2_AUTH_FT;
++		}
++#ifdef BCMWAPI_WPI
++		if (paramval & (IW_AUTH_KEY_MGMT_WAPI_PSK | IW_AUTH_KEY_MGMT_WAPI_CERT))
++			val = WAPI_AUTH_UNSPECIFIED;
++#endif
++		WL_TRACE(("%d: setting wpa_auth to %d\n", __LINE__, val));
++		if ((error = dev_wlc_intvar_set(dev, "wpa_auth", val)))
++			return error;
++		break;
++
++	case IW_AUTH_TKIP_COUNTERMEASURES:
++		dev_wlc_bufvar_set(dev, "tkip_countermeasures", (char *)&paramval, 1);
++		break;
++
++	case IW_AUTH_80211_AUTH_ALG:
++		/* open shared */
++		WL_MSG(dev->name, "Setting the D11auth %d\n", paramval);
++		if (paramval & IW_AUTH_ALG_OPEN_SYSTEM)
++			val = 0;
++		else if (paramval & IW_AUTH_ALG_SHARED_KEY)
++			val = 1;
++		else
++			error = 1;
++		if (!error && (error = dev_wlc_intvar_set(dev, "auth", val)))
++			return error;
++		break;
++
++	case IW_AUTH_WPA_ENABLED:
++		if (paramval == 0) {
++			val = 0;
++			WL_TRACE(("%d: setting wpa_auth to %d\n", __LINE__, val));
++			error = dev_wlc_intvar_set(dev, "wpa_auth", val);
++			return error;
++		}
++		else {
++			/* If WPA is enabled, wpa_auth is set elsewhere */
++		}
++		break;
++
++	case IW_AUTH_DROP_UNENCRYPTED:
++		dev_wlc_bufvar_set(dev, "wsec_restrict", (char *)&paramval, 1);
++		break;
++
++	case IW_AUTH_RX_UNENCRYPTED_EAPOL:
++		dev_wlc_bufvar_set(dev, "rx_unencrypted_eapol", (char *)&paramval, 1);
++		break;
++
++#if WIRELESS_EXT > 17
++
++	case IW_AUTH_ROAMING_CONTROL:
++		WL_TRACE(("IW_AUTH_ROAMING_CONTROL\n"));
++		/* driver control or user space app control */
++		break;
++
++	case IW_AUTH_PRIVACY_INVOKED: {
++		int wsec;
++
++		if (paramval == 0) {
++			iw->privacy_invoked = FALSE;
++			if ((error = dev_wlc_intvar_set(dev, "is_WPS_enrollee", FALSE))) {
++				WL_WSEC(("Failed to clear iovar is_WPS_enrollee\n"));
++				return error;
++			}
++		} else {
++			iw->privacy_invoked = TRUE;
++			if ((error = dev_wlc_intvar_get(dev, "wsec", &wsec)))
++				return error;
++
++			if (!WSEC_ENABLED(wsec)) {
++				/* if privacy is true, but wsec is false, we are a WPS enrollee */
++				if ((error = dev_wlc_intvar_set(dev, "is_WPS_enrollee", TRUE))) {
++					WL_WSEC(("Failed to set iovar is_WPS_enrollee\n"));
++					return error;
++				}
++			} else {
++				if ((error = dev_wlc_intvar_set(dev, "is_WPS_enrollee", FALSE))) {
++					WL_WSEC(("Failed to clear iovar is_WPS_enrollee\n"));
++					return error;
++				}
++			}
++		}
++		break;
++	}
++
++
++#endif /* WIRELESS_EXT > 17 */
++
++#ifdef BCMWAPI_WPI
++
++	case IW_AUTH_WAPI_ENABLED:
++		if ((error = dev_wlc_intvar_get(dev, "wsec", &val)))
++			return error;
++		if (paramval) {
++			val |= SMS4_ENABLED;
++			if ((error = dev_wlc_intvar_set(dev, "wsec", val))) {
++				WL_ERROR(("setting wsec to 0x%0x returned error %d\n",
++					val, error));
++				return error;
++			}
++			if ((error = dev_wlc_intvar_set(dev, "wpa_auth", WAPI_AUTH_UNSPECIFIED))) {
++				WL_ERROR(("setting wpa_auth(%d) returned %d\n",
++					WAPI_AUTH_UNSPECIFIED,
++					error));
++				return error;
++			}
++		}
++
++		break;
++
++#endif /* BCMWAPI_WPI */
++
++	default:
++		break;
++	}
++	return 0;
++}
++#define VAL_PSK(_val) (((_val) & WPA_AUTH_PSK) || ((_val) & WPA2_AUTH_PSK))
++
++static int
++wl_iw_get_wpaauth(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error;
++	int paramid;
++	int paramval = 0;
++	int val;
++	wl_iw_t *iw = IW_DEV_IF(dev);
++
++	WL_TRACE(("%s: SIOCGIWAUTH\n", dev->name));
++
++	paramid = vwrq->flags & IW_AUTH_INDEX;
++
++	switch (paramid) {
++	case IW_AUTH_WPA_VERSION:
++		/* supported wpa version disabled or wpa or wpa2 */
++		if ((error = dev_wlc_intvar_get(dev, "wpa_auth", &val)))
++			return error;
++		if (val & (WPA_AUTH_NONE | WPA_AUTH_DISABLED))
++			paramval = IW_AUTH_WPA_VERSION_DISABLED;
++		else if (val & (WPA_AUTH_PSK | WPA_AUTH_UNSPECIFIED))
++			paramval = IW_AUTH_WPA_VERSION_WPA;
++		else if (val & (WPA2_AUTH_PSK | WPA2_AUTH_UNSPECIFIED))
++			paramval = IW_AUTH_WPA_VERSION_WPA2;
++		break;
++
++	case IW_AUTH_CIPHER_PAIRWISE:
++		paramval = iw->pwsec;
++		break;
++
++	case IW_AUTH_CIPHER_GROUP:
++		paramval = iw->gwsec;
++		break;
++
++	case IW_AUTH_KEY_MGMT:
++		/* psk, 1x */
++		if ((error = dev_wlc_intvar_get(dev, "wpa_auth", &val)))
++			return error;
++		if (VAL_PSK(val))
++			paramval = IW_AUTH_KEY_MGMT_PSK;
++		else
++			paramval = IW_AUTH_KEY_MGMT_802_1X;
++
++		break;
++	case IW_AUTH_TKIP_COUNTERMEASURES:
++		dev_wlc_bufvar_get(dev, "tkip_countermeasures", (char *)&paramval, 1);
++		break;
++
++	case IW_AUTH_DROP_UNENCRYPTED:
++		dev_wlc_bufvar_get(dev, "wsec_restrict", (char *)&paramval, 1);
++		break;
++
++	case IW_AUTH_RX_UNENCRYPTED_EAPOL:
++		dev_wlc_bufvar_get(dev, "rx_unencrypted_eapol", (char *)&paramval, 1);
++		break;
++
++	case IW_AUTH_80211_AUTH_ALG:
++		/* open, shared, leap */
++		if ((error = dev_wlc_intvar_get(dev, "auth", &val)))
++			return error;
++		if (!val)
++			paramval = IW_AUTH_ALG_OPEN_SYSTEM;
++		else
++			paramval = IW_AUTH_ALG_SHARED_KEY;
++		break;
++	case IW_AUTH_WPA_ENABLED:
++		if ((error = dev_wlc_intvar_get(dev, "wpa_auth", &val)))
++			return error;
++		if (val)
++			paramval = TRUE;
++		else
++			paramval = FALSE;
++		break;
++
++#if WIRELESS_EXT > 17
++
++	case IW_AUTH_ROAMING_CONTROL:
++		WL_ERROR(("IW_AUTH_ROAMING_CONTROL\n"));
++		/* driver control or user space app control */
++		break;
++
++	case IW_AUTH_PRIVACY_INVOKED:
++		paramval = iw->privacy_invoked;
++		break;
++
++#endif /* WIRELESS_EXT > 17 */
++	}
++	vwrq->value = paramval;
++	return 0;
++}
++#endif /* WIRELESS_EXT > 17 */
++
++static const iw_handler wl_iw_handler[] =
++{
++	(iw_handler) wl_iw_config_commit,	/* SIOCSIWCOMMIT */
++	(iw_handler) wl_iw_get_name,		/* SIOCGIWNAME */
++	(iw_handler) NULL,			/* SIOCSIWNWID */
++	(iw_handler) NULL,			/* SIOCGIWNWID */
++	(iw_handler) wl_iw_set_freq,		/* SIOCSIWFREQ */
++	(iw_handler) wl_iw_get_freq,		/* SIOCGIWFREQ */
++	(iw_handler) wl_iw_set_mode,		/* SIOCSIWMODE */
++	(iw_handler) wl_iw_get_mode,		/* SIOCGIWMODE */
++	(iw_handler) NULL,			/* SIOCSIWSENS */
++	(iw_handler) NULL,			/* SIOCGIWSENS */
++	(iw_handler) NULL,			/* SIOCSIWRANGE */
++	(iw_handler) wl_iw_get_range,		/* SIOCGIWRANGE */
++	(iw_handler) NULL,			/* SIOCSIWPRIV */
++	(iw_handler) NULL,			/* SIOCGIWPRIV */
++	(iw_handler) NULL,			/* SIOCSIWSTATS */
++	(iw_handler) NULL,			/* SIOCGIWSTATS */
++	(iw_handler) wl_iw_set_spy,		/* SIOCSIWSPY */
++	(iw_handler) wl_iw_get_spy,		/* SIOCGIWSPY */
++	(iw_handler) NULL,			/* -- hole -- */
++	(iw_handler) NULL,			/* -- hole -- */
++	(iw_handler) wl_iw_set_wap,		/* SIOCSIWAP */
++	(iw_handler) wl_iw_get_wap,		/* SIOCGIWAP */
++#if WIRELESS_EXT > 17
++	(iw_handler) wl_iw_mlme,		/* SIOCSIWMLME */
++#else
++	(iw_handler) NULL,			/* -- hole -- */
++#endif
++#ifdef WL_ESCAN
++	(iw_handler) NULL,			/* SIOCGIWAPLIST */
++#else
++	(iw_handler) wl_iw_iscan_get_aplist,	/* SIOCGIWAPLIST */
++#endif
++#if WIRELESS_EXT > 13
++	(iw_handler) wl_iw_iscan_set_scan,	/* SIOCSIWSCAN */
++	(iw_handler) wl_iw_iscan_get_scan,	/* SIOCGIWSCAN */
++#else	/* WIRELESS_EXT > 13 */
++	(iw_handler) NULL,			/* SIOCSIWSCAN */
++	(iw_handler) NULL,			/* SIOCGIWSCAN */
++#endif	/* WIRELESS_EXT > 13 */
++	(iw_handler) wl_iw_set_essid,		/* SIOCSIWESSID */
++	(iw_handler) wl_iw_get_essid,		/* SIOCGIWESSID */
++	(iw_handler) wl_iw_set_nick,		/* SIOCSIWNICKN */
++	(iw_handler) wl_iw_get_nick,		/* SIOCGIWNICKN */
++	(iw_handler) NULL,			/* -- hole -- */
++	(iw_handler) NULL,			/* -- hole -- */
++	(iw_handler) wl_iw_set_rate,		/* SIOCSIWRATE */
++	(iw_handler) wl_iw_get_rate,		/* SIOCGIWRATE */
++	(iw_handler) wl_iw_set_rts,		/* SIOCSIWRTS */
++	(iw_handler) wl_iw_get_rts,		/* SIOCGIWRTS */
++	(iw_handler) wl_iw_set_frag,		/* SIOCSIWFRAG */
++	(iw_handler) wl_iw_get_frag,		/* SIOCGIWFRAG */
++	(iw_handler) wl_iw_set_txpow,		/* SIOCSIWTXPOW */
++	(iw_handler) wl_iw_get_txpow,		/* SIOCGIWTXPOW */
++#if WIRELESS_EXT > 10
++	(iw_handler) wl_iw_set_retry,		/* SIOCSIWRETRY */
++	(iw_handler) wl_iw_get_retry,		/* SIOCGIWRETRY */
++#endif /* WIRELESS_EXT > 10 */
++	(iw_handler) wl_iw_set_encode,		/* SIOCSIWENCODE */
++	(iw_handler) wl_iw_get_encode,		/* SIOCGIWENCODE */
++	(iw_handler) wl_iw_set_power,		/* SIOCSIWPOWER */
++	(iw_handler) wl_iw_get_power,		/* SIOCGIWPOWER */
++#if WIRELESS_EXT > 17
++	(iw_handler) NULL,			/* -- hole -- */
++	(iw_handler) NULL,			/* -- hole -- */
++	(iw_handler) wl_iw_set_wpaie,		/* SIOCSIWGENIE */
++	(iw_handler) wl_iw_get_wpaie,		/* SIOCGIWGENIE */
++	(iw_handler) wl_iw_set_wpaauth,		/* SIOCSIWAUTH */
++	(iw_handler) wl_iw_get_wpaauth,		/* SIOCGIWAUTH */
++	(iw_handler) wl_iw_set_encodeext,	/* SIOCSIWENCODEEXT */
++	(iw_handler) wl_iw_get_encodeext,	/* SIOCGIWENCODEEXT */
++	(iw_handler) wl_iw_set_pmksa,		/* SIOCSIWPMKSA */
++#endif /* WIRELESS_EXT > 17 */
++};
++
++#if WIRELESS_EXT > 12
++enum {
++	WL_IW_SET_LEDDC = SIOCIWFIRSTPRIV,
++	WL_IW_SET_VLANMODE,
++	WL_IW_SET_PM,
++	WL_IW_SET_LAST
++};
++
++static iw_handler wl_iw_priv_handler[] = {
++	wl_iw_set_leddc,
++	wl_iw_set_vlanmode,
++	wl_iw_set_pm,
++	NULL
++};
++
++static struct iw_priv_args wl_iw_priv_args[] = {
++	{
++		WL_IW_SET_LEDDC,
++		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++		0,
++		"set_leddc"
++	},
++	{
++		WL_IW_SET_VLANMODE,
++		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++		0,
++		"set_vlanmode"
++	},
++	{
++		WL_IW_SET_PM,
++		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++		0,
++		"set_pm"
++	},
++	{ 0, 0, 0, { 0 } }
++};
++
++const struct iw_handler_def wl_iw_handler_def =
++{
++	.num_standard = ARRAYSIZE(wl_iw_handler),
++	.num_private = ARRAY_SIZE(wl_iw_priv_handler),
++	.num_private_args = ARRAY_SIZE(wl_iw_priv_args),
++	.standard = (const iw_handler *) wl_iw_handler,
++	.private = wl_iw_priv_handler,
++	.private_args = wl_iw_priv_args,
++#if WIRELESS_EXT >= 19
++	get_wireless_stats: dhd_get_wireless_stats,
++#endif /* WIRELESS_EXT >= 19 */
++	};
++#endif /* WIRELESS_EXT > 12 */
++
++int
++wl_iw_ioctl(
++	struct net_device *dev,
++	struct ifreq *rq,
++	int cmd
++)
++{
++	struct iwreq *wrq = (struct iwreq *) rq;
++	struct iw_request_info info;
++	iw_handler handler;
++	char *extra = NULL;
++	size_t token_size = 1;
++	int max_tokens = 0, ret = 0;
++#ifndef WL_ESCAN
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	wl_wext_info_t *wext_info = NULL;
++	iscan_info_t *iscan;
++
++	DHD_CHECK(dhd, dev);
++	wext_info = dhd->wext_info;
++	iscan = &wext_info->iscan;
++#endif
++
++	if (cmd < SIOCIWFIRST ||
++		IW_IOCTL_IDX(cmd) >= ARRAYSIZE(wl_iw_handler) ||
++		!(handler = wl_iw_handler[IW_IOCTL_IDX(cmd)]))
++		return -EOPNOTSUPP;
++
++	switch (cmd) {
++
++	case SIOCSIWESSID:
++	case SIOCGIWESSID:
++	case SIOCSIWNICKN:
++	case SIOCGIWNICKN:
++		max_tokens = IW_ESSID_MAX_SIZE + 1;
++		break;
++
++	case SIOCSIWENCODE:
++	case SIOCGIWENCODE:
++#if WIRELESS_EXT > 17
++	case SIOCSIWENCODEEXT:
++	case SIOCGIWENCODEEXT:
++#endif
++		max_tokens = IW_ENCODING_TOKEN_MAX;
++		break;
++
++	case SIOCGIWRANGE:
++		max_tokens = sizeof(struct iw_range);
++		break;
++
++	case SIOCGIWAPLIST:
++		token_size = sizeof(struct sockaddr) + sizeof(struct iw_quality);
++		max_tokens = IW_MAX_AP;
++		break;
++
++#if WIRELESS_EXT > 13
++	case SIOCGIWSCAN:
++#ifndef WL_ESCAN
++	if (iscan)
++		max_tokens = wrq->u.data.length;
++	else
++#endif
++		max_tokens = IW_SCAN_MAX_DATA;
++		break;
++#endif /* WIRELESS_EXT > 13 */
++
++	case SIOCSIWSPY:
++		token_size = sizeof(struct sockaddr);
++		max_tokens = IW_MAX_SPY;
++		break;
++
++	case SIOCGIWSPY:
++		token_size = sizeof(struct sockaddr) + sizeof(struct iw_quality);
++		max_tokens = IW_MAX_SPY;
++		break;
++	default:
++		break;
++	}
++
++	if (max_tokens && wrq->u.data.pointer) {
++		if (wrq->u.data.length > max_tokens)
++			return -E2BIG;
++
++		if (!(extra = kmalloc(max_tokens * token_size, GFP_KERNEL)))
++			return -ENOMEM;
++
++		if (copy_from_user(extra, wrq->u.data.pointer, wrq->u.data.length * token_size)) {
++			kfree(extra);
++			return -EFAULT;
++		}
++	}
++
++	info.cmd = cmd;
++	info.flags = 0;
++
++	ret = handler(dev, &info, &wrq->u, extra);
++
++	if (extra) {
++		if (copy_to_user(wrq->u.data.pointer, extra, wrq->u.data.length * token_size)) {
++			kfree(extra);
++			return -EFAULT;
++		}
++
++		kfree(extra);
++	}
++
++	return ret;
++}
++
++/* Convert a connection status event into a connection status string.
++ * Returns TRUE if a matching connection status string was found.
++ */
++bool
++wl_iw_conn_status_str(uint32 event_type, uint32 status, uint32 reason,
++	char* stringBuf, uint buflen)
++{
++	typedef struct conn_fail_event_map_t {
++		uint32 inEvent;			/* input: event type to match */
++		uint32 inStatus;		/* input: event status code to match */
++		uint32 inReason;		/* input: event reason code to match */
++		const char* outName;	/* output: failure type */
++		const char* outCause;	/* output: failure cause */
++	} conn_fail_event_map_t;
++
++	/* Map of WLC_E events to connection failure strings */
++#	define WL_IW_DONT_CARE	9999
++	const conn_fail_event_map_t event_map [] = {
++		/* inEvent           inStatus                inReason         */
++		/* outName outCause                                           */
++		{WLC_E_SET_SSID,     WLC_E_STATUS_SUCCESS,   WL_IW_DONT_CARE,
++		"Conn", "Success"},
++		{WLC_E_SET_SSID,     WLC_E_STATUS_NO_NETWORKS, WL_IW_DONT_CARE,
++		"Conn", "NoNetworks"},
++		{WLC_E_SET_SSID,     WLC_E_STATUS_FAIL,      WL_IW_DONT_CARE,
++		"Conn", "ConfigMismatch"},
++		{WLC_E_PRUNE,        WL_IW_DONT_CARE,        WLC_E_PRUNE_ENCR_MISMATCH,
++		"Conn", "EncrypMismatch"},
++		{WLC_E_PRUNE,        WL_IW_DONT_CARE,        WLC_E_RSN_MISMATCH,
++		"Conn", "RsnMismatch"},
++		{WLC_E_AUTH,         WLC_E_STATUS_TIMEOUT,   WL_IW_DONT_CARE,
++		"Conn", "AuthTimeout"},
++		{WLC_E_AUTH,         WLC_E_STATUS_FAIL,      WL_IW_DONT_CARE,
++		"Conn", "AuthFail"},
++		{WLC_E_AUTH,         WLC_E_STATUS_NO_ACK,    WL_IW_DONT_CARE,
++		"Conn", "AuthNoAck"},
++		{WLC_E_REASSOC,      WLC_E_STATUS_FAIL,      WL_IW_DONT_CARE,
++		"Conn", "ReassocFail"},
++		{WLC_E_REASSOC,      WLC_E_STATUS_TIMEOUT,   WL_IW_DONT_CARE,
++		"Conn", "ReassocTimeout"},
++		{WLC_E_REASSOC,      WLC_E_STATUS_ABORT,     WL_IW_DONT_CARE,
++		"Conn", "ReassocAbort"},
++		{WLC_E_PSK_SUP,      WLC_SUP_KEYED,          WL_IW_DONT_CARE,
++		"Sup", "ConnSuccess"},
++		{WLC_E_PSK_SUP,      WL_IW_DONT_CARE,        WL_IW_DONT_CARE,
++		"Sup", "WpaHandshakeFail"},
++		{WLC_E_DEAUTH_IND,   WL_IW_DONT_CARE,        WL_IW_DONT_CARE,
++		"Conn", "Deauth"},
++		{WLC_E_DISASSOC_IND, WL_IW_DONT_CARE,        WL_IW_DONT_CARE,
++		"Conn", "DisassocInd"},
++		{WLC_E_DISASSOC,     WL_IW_DONT_CARE,        WL_IW_DONT_CARE,
++		"Conn", "Disassoc"}
++	};
++
++	const char* name = "";
++	const char* cause = NULL;
++	int i;
++
++	/* Search the event map table for a matching event */
++	for (i = 0;  i < sizeof(event_map)/sizeof(event_map[0]);  i++) {
++		const conn_fail_event_map_t* row = &event_map[i];
++		if (row->inEvent == event_type &&
++		    (row->inStatus == status || row->inStatus == WL_IW_DONT_CARE) &&
++		    (row->inReason == reason || row->inReason == WL_IW_DONT_CARE)) {
++			name = row->outName;
++			cause = row->outCause;
++			break;
++		}
++	}
++
++	/* If found, generate a connection failure string and return TRUE */
++	if (cause) {
++		memset(stringBuf, 0, buflen);
++		(void)snprintf(stringBuf, buflen, "%s %s %02d %02d", name, cause, status, reason);
++		WL_TRACE(("Connection status: %s\n", stringBuf));
++		return TRUE;
++	} else {
++		return FALSE;
++	}
++}
++
++#if (WIRELESS_EXT > 14)
++/* Check if we have received an event that indicates connection failure
++ * If so, generate a connection failure report string.
++ * The caller supplies a buffer to hold the generated string.
++ */
++static bool
++wl_iw_check_conn_fail(wl_event_msg_t *e, char* stringBuf, uint buflen)
++{
++	uint32 event = ntoh32(e->event_type);
++	uint32 status =  ntoh32(e->status);
++	uint32 reason =  ntoh32(e->reason);
++
++	if (wl_iw_conn_status_str(event, status, reason, stringBuf, buflen)) {
++		return TRUE;
++	} else
++	{
++		return FALSE;
++	}
++}
++#endif /* WIRELESS_EXT > 14 */
++
++#ifndef IW_CUSTOM_MAX
++#define IW_CUSTOM_MAX 256 /* size of extra buffer used for translation of events */
++#endif /* IW_CUSTOM_MAX */
++
++void
++wl_iw_event(struct net_device *dev, struct wl_wext_info *wext_info,
++	wl_event_msg_t *e, void* data)
++{
++#if WIRELESS_EXT > 13
++	union iwreq_data wrqu;
++	char extra[IW_CUSTOM_MAX + 1];
++	int cmd = 0;
++	uint32 event_type = ntoh32(e->event_type);
++	uint16 flags =  ntoh16(e->flags);
++	uint32 datalen = ntoh32(e->datalen);
++	uint32 status =  ntoh32(e->status);
++	uint32 reason =  ntoh32(e->reason);
++#ifndef WL_ESCAN
++	iscan_info_t *iscan = &wext_info->iscan;
++#endif
++
++	memset(&wrqu, 0, sizeof(wrqu));
++	memset(extra, 0, sizeof(extra));
++
++	memcpy(wrqu.addr.sa_data, &e->addr, ETHER_ADDR_LEN);
++	wrqu.addr.sa_family = ARPHRD_ETHER;
++
++	switch (event_type) {
++	case WLC_E_TXFAIL:
++		cmd = IWEVTXDROP;
++		break;
++#if WIRELESS_EXT > 14
++	case WLC_E_JOIN:
++	case WLC_E_ASSOC_IND:
++	case WLC_E_REASSOC_IND:
++		cmd = IWEVREGISTERED;
++		break;
++	case WLC_E_DEAUTH:
++	case WLC_E_DISASSOC:
++		wl_iw_update_connect_status(dev, WL_EXT_STATUS_DISCONNECTED);
++		WL_MSG_RLMT(dev->name, &e->addr, ETHER_ADDR_LEN,
++			"disconnected with "MACSTR", event %d, reason %d\n",
++			MAC2STR((u8 *)wrqu.addr.sa_data), event_type, reason);
++		break;
++	case WLC_E_DEAUTH_IND:
++	case WLC_E_DISASSOC_IND:
++		cmd = SIOCGIWAP;
++		WL_MSG(dev->name, "disconnected with "MACSTR", event %d, reason %d\n",
++			MAC2STR((u8 *)wrqu.addr.sa_data), event_type, reason);
++		bzero(wrqu.addr.sa_data, ETHER_ADDR_LEN);
++		bzero(&extra, ETHER_ADDR_LEN);
++		wl_iw_update_connect_status(dev, WL_EXT_STATUS_DISCONNECTED);
++		break;
++
++	case WLC_E_LINK:
++		cmd = SIOCGIWAP;
++		if (!(flags & WLC_EVENT_MSG_LINK)) {
++			WL_MSG(dev->name, "Link Down with "MACSTR", reason=%d\n",
++				MAC2STR((u8 *)wrqu.addr.sa_data), reason);
++			bzero(wrqu.addr.sa_data, ETHER_ADDR_LEN);
++			bzero(&extra, ETHER_ADDR_LEN);
++			wl_iw_update_connect_status(dev, WL_EXT_STATUS_DISCONNECTED);
++		} else {
++			WL_MSG(dev->name, "Link UP with "MACSTR"\n",
++				MAC2STR((u8 *)wrqu.addr.sa_data));
++		}
++		break;
++	case WLC_E_ACTION_FRAME:
++		cmd = IWEVCUSTOM;
++		if (datalen + 1 <= sizeof(extra)) {
++			wrqu.data.length = datalen + 1;
++			extra[0] = WLC_E_ACTION_FRAME;
++			memcpy(&extra[1], data, datalen);
++			WL_TRACE(("WLC_E_ACTION_FRAME len %d \n", wrqu.data.length));
++		}
++		break;
++
++	case WLC_E_ACTION_FRAME_COMPLETE:
++		cmd = IWEVCUSTOM;
++		if (sizeof(status) + 1 <= sizeof(extra)) {
++			wrqu.data.length = sizeof(status) + 1;
++			extra[0] = WLC_E_ACTION_FRAME_COMPLETE;
++			memcpy(&extra[1], &status, sizeof(status));
++			WL_TRACE(("wl_iw_event status %d  \n", status));
++		}
++		break;
++#endif /* WIRELESS_EXT > 14 */
++#if WIRELESS_EXT > 17
++	case WLC_E_MIC_ERROR: {
++		struct	iw_michaelmicfailure  *micerrevt = (struct  iw_michaelmicfailure  *)&extra;
++		cmd = IWEVMICHAELMICFAILURE;
++		wrqu.data.length = sizeof(struct iw_michaelmicfailure);
++		if (flags & WLC_EVENT_MSG_GROUP)
++			micerrevt->flags |= IW_MICFAILURE_GROUP;
++		else
++			micerrevt->flags |= IW_MICFAILURE_PAIRWISE;
++		memcpy(micerrevt->src_addr.sa_data, &e->addr, ETHER_ADDR_LEN);
++		micerrevt->src_addr.sa_family = ARPHRD_ETHER;
++
++		break;
++	}
++
++	case WLC_E_ASSOC_REQ_IE:
++		cmd = IWEVASSOCREQIE;
++		wrqu.data.length = datalen;
++		if (datalen < sizeof(extra))
++			memcpy(extra, data, datalen);
++		break;
++
++	case WLC_E_ASSOC_RESP_IE:
++		cmd = IWEVASSOCRESPIE;
++		wrqu.data.length = datalen;
++		if (datalen < sizeof(extra))
++			memcpy(extra, data, datalen);
++		break;
++
++	case WLC_E_PMKID_CACHE: {
++		struct iw_pmkid_cand *iwpmkidcand = (struct iw_pmkid_cand *)&extra;
++		pmkid_cand_list_t *pmkcandlist;
++		pmkid_cand_t	*pmkidcand;
++		int count;
++
++		if (data == NULL)
++			break;
++
++		cmd = IWEVPMKIDCAND;
++		pmkcandlist = data;
++		count = ntoh32_ua((uint8 *)&pmkcandlist->npmkid_cand);
++		wrqu.data.length = sizeof(struct iw_pmkid_cand);
++		pmkidcand = pmkcandlist->pmkid_cand;
++		while (count) {
++			bzero(iwpmkidcand, sizeof(struct iw_pmkid_cand));
++			if (pmkidcand->preauth)
++				iwpmkidcand->flags |= IW_PMKID_CAND_PREAUTH;
++			bcopy(&pmkidcand->BSSID, &iwpmkidcand->bssid.sa_data,
++			      ETHER_ADDR_LEN);
++			wireless_send_event(dev, cmd, &wrqu, extra);
++			pmkidcand++;
++			count--;
++		}
++		break;
++	}
++#endif /* WIRELESS_EXT > 17 */
++
++#ifndef WL_ESCAN
++	case WLC_E_SCAN_COMPLETE:
++#if WIRELESS_EXT > 14
++		cmd = SIOCGIWSCAN;
++#endif
++		WL_TRACE(("event WLC_E_SCAN_COMPLETE\n"));
++		// terence 20150224: fix "wlan0: (WE) : Wireless Event too big (65306)"
++		memset(&wrqu, 0, sizeof(wrqu));
++		if ((iscan) && (iscan->sysioc_pid >= 0) &&
++			(iscan->iscan_state != ISCAN_STATE_IDLE))
++			up(&iscan->sysioc_sem);
++		break;
++#endif
++
++	default:
++		/* Cannot translate event */
++		break;
++	}
++
++	if (cmd) {
++#ifndef WL_ESCAN
++		if (cmd == SIOCGIWSCAN) {
++			if ((!iscan) || (iscan->sysioc_pid < 0)) {
++				wireless_send_event(dev, cmd, &wrqu, NULL);
++			};
++		} else
++#endif
++			wireless_send_event(dev, cmd, &wrqu, extra);
++	}
++
++#if WIRELESS_EXT > 14
++	/* Look for WLC events that indicate a connection failure.
++	 * If found, generate an IWEVCUSTOM event.
++	 */
++	memset(extra, 0, sizeof(extra));
++	if (wl_iw_check_conn_fail(e, extra, sizeof(extra))) {
++		cmd = IWEVCUSTOM;
++		wrqu.data.length = strlen(extra);
++		wireless_send_event(dev, cmd, &wrqu, extra);
++	}
++#endif /* WIRELESS_EXT > 14 */
++
++#endif /* WIRELESS_EXT > 13 */
++}
++
++#ifdef WL_NAN
++static int wl_iw_get_wireless_stats_cbfn(void *ctx, uint8 *data, uint16 type, uint16 len)
++{
++	struct iw_statistics *wstats = ctx;
++	int res = BCME_OK;
++
++	switch (type) {
++		case WL_CNT_XTLV_WLC: {
++			wl_cnt_wlc_t *cnt = (wl_cnt_wlc_t *)data;
++			if (len > sizeof(wl_cnt_wlc_t)) {
++				printf("counter structure length invalid! %d > %d\n",
++					len, (int)sizeof(wl_cnt_wlc_t));
++			}
++			wstats->discard.nwid = 0;
++			wstats->discard.code = dtoh32(cnt->rxundec);
++			wstats->discard.fragment = dtoh32(cnt->rxfragerr);
++			wstats->discard.retries = dtoh32(cnt->txfail);
++			wstats->discard.misc = dtoh32(cnt->rxrunt) + dtoh32(cnt->rxgiant);
++			wstats->miss.beacon = 0;
++			WL_TRACE(("wl_iw_get_wireless_stats counters txframe=%d txbyte=%d\n",
++				dtoh32(cnt->txframe), dtoh32(cnt->txbyte)));
++			WL_TRACE(("wl_iw_get_wireless_stats counters rxundec=%d\n",
++				dtoh32(cnt->rxundec)));
++			WL_TRACE(("wl_iw_get_wireless_stats counters txfail=%d\n",
++				dtoh32(cnt->txfail)));
++			WL_TRACE(("wl_iw_get_wireless_stats counters rxfragerr=%d\n",
++				dtoh32(cnt->rxfragerr)));
++			WL_TRACE(("wl_iw_get_wireless_stats counters rxrunt=%d\n",
++				dtoh32(cnt->rxrunt)));
++			WL_TRACE(("wl_iw_get_wireless_stats counters rxgiant=%d\n",
++				dtoh32(cnt->rxgiant)));
++			break;
++		}
++		case WL_CNT_XTLV_CNTV_LE10_UCODE:
++		case WL_CNT_XTLV_LT40_UCODE_V1:
++		case WL_CNT_XTLV_GE40_UCODE_V1:
++		{
++			/* Offsets of rxfrmtoolong and rxbadplcp are the same in
++			 * wl_cnt_v_le10_mcst_t, wl_cnt_lt40mcst_v1_t, and wl_cnt_ge40mcst_v1_t.
++			 * So we can just cast to wl_cnt_v_le10_mcst_t here.
++			 */
++			wl_cnt_v_le10_mcst_t *cnt = (wl_cnt_v_le10_mcst_t *)data;
++			if (len != WL_CNT_MCST_STRUCT_SZ) {
++				printf("counter structure length mismatch! %d != %d\n",
++					len, WL_CNT_MCST_STRUCT_SZ);
++			}
++			WL_TRACE(("wl_iw_get_wireless_stats counters rxfrmtoolong=%d\n",
++				dtoh32(cnt->rxfrmtoolong)));
++			WL_TRACE(("wl_iw_get_wireless_stats counters rxbadplcp=%d\n",
++				dtoh32(cnt->rxbadplcp)));
++			BCM_REFERENCE(cnt);
++			break;
++		}
++		default:
++			WL_ERROR(("%d: Unsupported type %d\n", __LINE__, type));
++			break;
++	}
++	return res;
++}
++#endif
++
++int wl_iw_get_wireless_stats(struct net_device *dev, struct iw_statistics *wstats)
++{
++	int res = 0;
++	int phy_noise;
++	int rssi;
++	scb_val_t scb_val;
++#if WIRELESS_EXT > 11
++	char *cntbuf = NULL;
++	wl_cnt_info_t *cntinfo;
++	uint16 ver;
++	uint32 corerev = 0;
++#endif /* WIRELESS_EXT > 11 */
++
++	phy_noise = 0;
++	if ((res = dev_wlc_ioctl(dev, WLC_GET_PHY_NOISE, &phy_noise, sizeof(phy_noise)))) {
++		WL_TRACE(("WLC_GET_PHY_NOISE error=%d\n", res));
++		goto done;
++	}
++
++	phy_noise = dtoh32(phy_noise);
++	WL_TRACE(("wl_iw_get_wireless_stats phy noise=%d\n *****", phy_noise));
++
++	memset(&scb_val, 0, sizeof(scb_val));
++	if ((res = dev_wlc_ioctl(dev, WLC_GET_RSSI, &scb_val, sizeof(scb_val_t)))) {
++		WL_TRACE(("WLC_GET_RSSI error=%d\n", res));
++		goto done;
++	}
++
++	rssi = dtoh32(scb_val.val);
++	rssi = MIN(rssi, RSSI_MAXVAL);
++	WL_TRACE(("wl_iw_get_wireless_stats rssi=%d ****** \n", rssi));
++	if (rssi <= WL_IW_RSSI_NO_SIGNAL)
++		wstats->qual.qual = 0;
++	else if (rssi <= WL_IW_RSSI_VERY_LOW)
++		wstats->qual.qual = 1;
++	else if (rssi <= WL_IW_RSSI_LOW)
++		wstats->qual.qual = 2;
++	else if (rssi <= WL_IW_RSSI_GOOD)
++		wstats->qual.qual = 3;
++	else if (rssi <= WL_IW_RSSI_VERY_GOOD)
++		wstats->qual.qual = 4;
++	else
++		wstats->qual.qual = 5;
++
++	/* Wraps to 0 if RSSI is 0 */
++	wstats->qual.level = 0x100 + rssi;
++	wstats->qual.noise = 0x100 + phy_noise;
++#if WIRELESS_EXT > 18
++	wstats->qual.updated |= (IW_QUAL_ALL_UPDATED | IW_QUAL_DBM);
++#else
++	wstats->qual.updated |= 7;
++#endif /* WIRELESS_EXT > 18 */
++
++#if WIRELESS_EXT > 11
++	WL_TRACE(("wl_iw_get_wireless_stats counters\n *****"));
++
++	cntbuf = kmalloc(MAX_WLIW_IOCTL_LEN, GFP_KERNEL);
++	if (!cntbuf) {
++		res = BCME_NOMEM;
++		goto done;
++	}
++
++	memset(cntbuf, 0, MAX_WLIW_IOCTL_LEN);
++	res = dev_wlc_bufvar_get(dev, "counters", cntbuf, MAX_WLIW_IOCTL_LEN);
++	if (res)
++	{
++		WL_ERROR(("wl_iw_get_wireless_stats counters failed error=%d ****** \n", res));
++		goto done;
++	}
++
++	cntinfo = (wl_cnt_info_t *)cntbuf;
++	cntinfo->version = dtoh16(cntinfo->version);
++	cntinfo->datalen = dtoh16(cntinfo->datalen);
++	ver = cntinfo->version;
++#ifdef WL_NAN
++	CHK_CNTBUF_DATALEN(cntbuf, MAX_WLIW_IOCTL_LEN);
++#endif
++	if (ver > WL_CNT_T_VERSION) {
++		WL_TRACE(("\tIncorrect version of counters struct: expected %d; got %d\n",
++			WL_CNT_T_VERSION, ver));
++		res = BCME_VERSION;
++		goto done;
++	}
++
++	if (ver == WL_CNT_VERSION_11) {
++		wlc_rev_info_t revinfo;
++		memset(&revinfo, 0, sizeof(revinfo));
++		res = dev_wlc_ioctl(dev, WLC_GET_REVINFO, &revinfo, sizeof(revinfo));
++		if (res) {
++			WL_ERROR(("WLC_GET_REVINFO failed %d\n", res));
++			goto done;
++		}
++		corerev = dtoh32(revinfo.corerev);
++	}
++
++#ifdef WL_NAN
++	res = wl_cntbuf_to_xtlv_format(NULL, cntinfo, MAX_WLIW_IOCTL_LEN, corerev);
++	if (res) {
++		WL_ERROR(("wl_cntbuf_to_xtlv_format failed %d\n", res));
++		goto done;
++	}
++
++	if ((res = bcm_unpack_xtlv_buf(wstats, cntinfo->data, cntinfo->datalen,
++		BCM_XTLV_OPTION_ALIGN32, wl_iw_get_wireless_stats_cbfn))) {
++		goto done;
++	}
++#endif
++#endif /* WIRELESS_EXT > 11 */
++
++done:
++#if WIRELESS_EXT > 11
++	if (cntbuf) {
++		kfree(cntbuf);
++	}
++#endif /* WIRELESS_EXT > 11 */
++	return res;
++}
++
++#ifndef WL_ESCAN
++static void
++wl_iw_timerfunc(ulong data)
++{
++	iscan_info_t *iscan = (iscan_info_t *)data;
++	iscan->timer_on = 0;
++	if (iscan->iscan_state != ISCAN_STATE_IDLE) {
++		WL_TRACE(("timer trigger\n"));
++		up(&iscan->sysioc_sem);
++	}
++}
++
++static void
++wl_iw_set_event_mask(struct net_device *dev)
++{
++	char eventmask[WL_EVENTING_MASK_LEN];
++	char iovbuf[WL_EVENTING_MASK_LEN + 12];	/* Room for "event_msgs" + '\0' + bitvec */
++
++	dev_iw_iovar_getbuf(dev, "event_msgs", "", 0, iovbuf, sizeof(iovbuf));
++	bcopy(iovbuf, eventmask, WL_EVENTING_MASK_LEN);
++	setbit(eventmask, WLC_E_SCAN_COMPLETE);
++	dev_iw_iovar_setbuf(dev, "event_msgs", eventmask, WL_EVENTING_MASK_LEN,
++		iovbuf, sizeof(iovbuf));
++
++}
++
++static int
++wl_iw_iscan_prep(wl_scan_params_t *params, wlc_ssid_t *ssid)
++{
++	int err = 0;
++
++	memcpy(&params->bssid, &ether_bcast, ETHER_ADDR_LEN);
++	params->bss_type = DOT11_BSSTYPE_ANY;
++	params->scan_type = 0;
++	params->nprobes = -1;
++	params->active_time = -1;
++	params->passive_time = -1;
++	params->home_time = -1;
++	params->channel_num = 0;
++
++	params->nprobes = htod32(params->nprobes);
++	params->active_time = htod32(params->active_time);
++	params->passive_time = htod32(params->passive_time);
++	params->home_time = htod32(params->home_time);
++	if (ssid && ssid->SSID_len)
++		memcpy(&params->ssid, ssid, sizeof(wlc_ssid_t));
++
++	return err;
++}
++
++static int
++wl_iw_iscan(iscan_info_t *iscan, wlc_ssid_t *ssid, uint16 action)
++{
++	int params_size = (WL_SCAN_PARAMS_FIXED_SIZE + OFFSETOF(wl_iscan_params_t, params));
++	wl_iscan_params_t *params;
++	int err = 0;
++
++	if (ssid && ssid->SSID_len) {
++		params_size += sizeof(wlc_ssid_t);
++	}
++	params = (wl_iscan_params_t*)kmalloc(params_size, GFP_KERNEL);
++	if (params == NULL) {
++		return -ENOMEM;
++	}
++	memset(params, 0, params_size);
++	ASSERT(params_size < WLC_IOCTL_SMLEN);
++
++	err = wl_iw_iscan_prep(&params->params, ssid);
++
++	if (!err) {
++		params->version = htod32(ISCAN_REQ_VERSION);
++		params->action = htod16(action);
++		params->scan_duration = htod16(0);
++
++		/* params_size += OFFSETOF(wl_iscan_params_t, params); */
++		(void) dev_iw_iovar_setbuf(iscan->dev, "iscan", params, params_size,
++			iscan->ioctlbuf, WLC_IOCTL_SMLEN);
++	}
++
++	kfree(params);
++	return err;
++}
++
++static uint32
++wl_iw_iscan_get(iscan_info_t *iscan)
++{
++	iscan_buf_t * buf;
++	iscan_buf_t * ptr;
++	wl_iscan_results_t * list_buf;
++	wl_iscan_results_t list;
++	wl_scan_results_t *results;
++	uint32 status;
++
++	/* buffers are allocated on demand */
++	if (iscan->list_cur) {
++		buf = iscan->list_cur;
++		iscan->list_cur = buf->next;
++	}
++	else {
++		buf = kmalloc(sizeof(iscan_buf_t), GFP_KERNEL);
++		if (!buf)
++			return WL_SCAN_RESULTS_ABORTED;
++		buf->next = NULL;
++		if (!iscan->list_hdr)
++			iscan->list_hdr = buf;
++		else {
++			ptr = iscan->list_hdr;
++			while (ptr->next) {
++				ptr = ptr->next;
++			}
++			ptr->next = buf;
++		}
++	}
++	memset(buf->iscan_buf, 0, WLC_IW_ISCAN_MAXLEN);
++	list_buf = (wl_iscan_results_t*)buf->iscan_buf;
++	results = &list_buf->results;
++	results->buflen = WL_ISCAN_RESULTS_FIXED_SIZE;
++	results->version = 0;
++	results->count = 0;
++
++	memset(&list, 0, sizeof(list));
++	list.results.buflen = htod32(WLC_IW_ISCAN_MAXLEN);
++	(void) dev_iw_iovar_getbuf(
++		iscan->dev,
++		"iscanresults",
++		&list,
++		WL_ISCAN_RESULTS_FIXED_SIZE,
++		buf->iscan_buf,
++		WLC_IW_ISCAN_MAXLEN);
++	results->buflen = dtoh32(results->buflen);
++	results->version = dtoh32(results->version);
++	results->count = dtoh32(results->count);
++	WL_TRACE(("results->count = %d\n", results->count));
++
++	WL_TRACE(("results->buflen = %d\n", results->buflen));
++	status = dtoh32(list_buf->status);
++	return status;
++}
++
++static void wl_iw_send_scan_complete(iscan_info_t *iscan)
++{
++	union iwreq_data wrqu;
++
++	memset(&wrqu, 0, sizeof(wrqu));
++
++	/* wext expects to get no data for SIOCGIWSCAN Event  */
++	wireless_send_event(iscan->dev, SIOCGIWSCAN, &wrqu, NULL);
++}
++
++static int
++_iscan_sysioc_thread(void *data)
++{
++	uint32 status;
++	iscan_info_t *iscan = (iscan_info_t *)data;
++
++	WL_MSG("wlan", "thread Enter\n");
++	DAEMONIZE("iscan_sysioc");
++
++	status = WL_SCAN_RESULTS_PARTIAL;
++	while (down_interruptible(&iscan->sysioc_sem) == 0) {
++		if (iscan->timer_on) {
++			_del_timer(&iscan->timer);
++			iscan->timer_on = 0;
++		}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++		rtnl_lock();
++#endif
++		status = wl_iw_iscan_get(iscan);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++		rtnl_unlock();
++#endif
++
++		switch (status) {
++			case WL_SCAN_RESULTS_PARTIAL:
++				WL_TRACE(("iscanresults incomplete\n"));
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++				rtnl_lock();
++#endif
++				/* make sure our buffer size is enough before going next round */
++				wl_iw_iscan(iscan, NULL, WL_SCAN_ACTION_CONTINUE);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++				rtnl_unlock();
++#endif
++				/* Reschedule the timer */
++				iscan->timer.expires = jiffies + msecs_to_jiffies(iscan->timer_ms);
++				add_timer(&iscan->timer);
++				iscan->timer_on = 1;
++				break;
++			case WL_SCAN_RESULTS_SUCCESS:
++				WL_TRACE(("iscanresults complete\n"));
++				iscan->iscan_state = ISCAN_STATE_IDLE;
++				wl_iw_send_scan_complete(iscan);
++				break;
++			case WL_SCAN_RESULTS_PENDING:
++				WL_TRACE(("iscanresults pending\n"));
++				/* Reschedule the timer */
++				iscan->timer.expires = jiffies + msecs_to_jiffies(iscan->timer_ms);
++				add_timer(&iscan->timer);
++				iscan->timer_on = 1;
++				break;
++			case WL_SCAN_RESULTS_ABORTED:
++				WL_TRACE(("iscanresults aborted\n"));
++				iscan->iscan_state = ISCAN_STATE_IDLE;
++				wl_iw_send_scan_complete(iscan);
++				break;
++			default:
++				WL_TRACE(("iscanresults returned unknown status %d\n", status));
++				break;
++		 }
++	}
++	WL_MSG("wlan", "was terminated\n");
++	complete_and_exit(&iscan->sysioc_exited, 0);
++}
++#endif /* !WL_ESCAN */
++
++void
++wl_iw_detach(struct net_device *dev, dhd_pub_t *dhdp)
++{
++	wl_wext_info_t *wext_info = dhdp->wext_info;
++#ifndef WL_ESCAN
++	iscan_buf_t  *buf;
++	iscan_info_t *iscan;
++#endif
++	if (!wext_info)
++		return;
++
++#ifndef WL_ESCAN
++	iscan = &wext_info->iscan;
++	if (iscan->sysioc_pid >= 0) {
++		KILL_PROC(iscan->sysioc_pid, SIGTERM);
++		wait_for_completion(&iscan->sysioc_exited);
++	}
++
++	while (iscan->list_hdr) {
++		buf = iscan->list_hdr->next;
++		kfree(iscan->list_hdr);
++		iscan->list_hdr = buf;
++	}
++#endif
++	wl_ext_add_remove_pm_enable_work(wext_info, FALSE);
++	wl_ext_event_deregister(dev, dhdp, WLC_E_LAST, wl_iw_event);
++	if (wext_info) {
++		kfree(wext_info);
++		dhdp->wext_info = NULL;
++	}
++}
++
++int
++wl_iw_attach(struct net_device *dev, dhd_pub_t *dhdp)
++{
++	wl_wext_info_t *wext_info = NULL;
++	int ret = 0;
++#ifndef WL_ESCAN
++	iscan_info_t *iscan = NULL;
++#endif
++
++	if (!dev)
++		return 0;
++	WL_TRACE(("Enter\n"));
++
++	wext_info = (void *)kzalloc(sizeof(struct wl_wext_info), GFP_KERNEL);
++	if (!wext_info)
++		return -ENOMEM;
++	memset(wext_info, 0, sizeof(wl_wext_info_t));
++	wext_info->dev = dev;
++	wext_info->dhd = dhdp;
++	wext_info->conn_info.bssidx = 0;
++	dhdp->wext_info = (void *)wext_info;
++
++#ifndef WL_ESCAN
++	iscan = &wext_info->iscan;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
++	iscan->kthread = NULL;
++#endif
++	iscan->sysioc_pid = -1;
++	/* we only care about main interface so save a global here */
++	iscan->dev = dev;
++	iscan->iscan_state = ISCAN_STATE_IDLE;
++
++	/* Set up the timer */
++	iscan->timer_ms    = 2000;
++	init_timer_compat(&iscan->timer, wl_iw_timerfunc, iscan);
++
++	sema_init(&iscan->sysioc_sem, 0);
++	init_completion(&iscan->sysioc_exited);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
++	iscan->kthread = kthread_run(_iscan_sysioc_thread, iscan, "iscan_sysioc");
++	iscan->sysioc_pid = iscan->kthread->pid;
++#else
++	iscan->sysioc_pid = kernel_thread(_iscan_sysioc_thread, iscan, 0);
++#endif
++	if (iscan->sysioc_pid < 0) {
++		ret = -ENOMEM;
++		goto exit;
++	}
++#endif
++	mutex_init(&wext_info->pm_sync);
++	INIT_DELAYED_WORK(&wext_info->pm_enable_work, wl_ext_pm_work_handler);
++	ret = wl_ext_event_register(dev, dhdp, WLC_E_LAST, wl_iw_event, dhdp->wext_info,
++		PRIO_EVENT_WEXT);
++	if (ret) {
++		WL_ERROR(("wl_ext_event_register err %d\n", ret));
++		goto exit;
++	}
++
++	return ret;
++exit:
++	wl_iw_detach(dev, dhdp);
++	return ret;
++}
++
++void
++wl_iw_down(struct net_device *dev, dhd_pub_t *dhdp)
++{
++	wl_wext_info_t *wext_info = NULL;
++
++	if (dhdp) {
++		wext_info = dhdp->wext_info;
++ 	} else {
++		WL_ERROR (("dhd is NULL\n"));
++		return;
++	}
++	wl_ext_add_remove_pm_enable_work(wext_info, FALSE);
++}
++
++int
++wl_iw_up(struct net_device *dev, dhd_pub_t *dhdp)
++{
++	wl_wext_info_t *wext_info = NULL;
++	int ret = 0;
++
++	if (dhdp) {
++		wext_info = dhdp->wext_info;
++ 	} else {
++		WL_ERROR (("dhd is NULL\n"));
++		return -ENODEV;
++	}
++
++	return ret;
++}
++
++s32
++wl_iw_autochannel(struct net_device *dev, char* command, int total_len)
++{
++	struct dhd_pub *dhd = dhd_get_pub(dev);
++	wl_wext_info_t *wext_info = NULL;
++	int ret = 0;
++#ifdef WL_ESCAN
++	int bytes_written = -1;
++#endif
++
++	DHD_CHECK(dhd, dev);
++	wext_info = dhd->wext_info;
++#ifdef WL_ESCAN
++	sscanf(command, "%*s %d", &dhd->escan->autochannel);
++	if (dhd->escan->autochannel == 0) {
++		dhd->escan->best_2g_ch = 0;
++		dhd->escan->best_5g_ch = 0;
++	} else if (dhd->escan->autochannel == 2) {
++		bytes_written = snprintf(command, total_len, "2g=%d 5g=%d",
++			dhd->escan->best_2g_ch, dhd->escan->best_5g_ch);
++		WL_TRACE(("command result is %s\n", command));
++		ret = bytes_written;
++	}
++#endif
++
++	return ret;
++}
++
++#endif /* USE_IW */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_iw.h b/module_drivers/drivers/net/wireless/bcmdhd/wl_iw.h
+new file mode 100644
+index 000000000..0fae6a804
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_iw.h
+@@ -0,0 +1,173 @@
++/*
++ * Linux Wireless Extensions support
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_iw.h 514727 2014-11-12 03:02:48Z $
++ */
++
++#ifndef _wl_iw_h_
++#define _wl_iw_h_
++
++#include <linux/wireless.h>
++
++#include <typedefs.h>
++#include <ethernet.h>
++#include <wlioctl.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++
++#define WL_SCAN_PARAMS_SSID_MAX 	10
++#define GET_SSID			"SSID="
++#define GET_CHANNEL			"CH="
++#define GET_NPROBE 			"NPROBE="
++#define GET_ACTIVE_ASSOC_DWELL  	"ACTIVE="
++#define GET_PASSIVE_ASSOC_DWELL  	"PASSIVE="
++#define GET_HOME_DWELL  		"HOME="
++#define GET_SCAN_TYPE			"TYPE="
++
++#define BAND_GET_CMD				"GETBAND"
++#define BAND_SET_CMD				"SETBAND"
++#define DTIM_SKIP_GET_CMD			"DTIMSKIPGET"
++#define DTIM_SKIP_SET_CMD			"DTIMSKIPSET"
++#define SETSUSPEND_CMD				"SETSUSPENDOPT"
++#define PNOSSIDCLR_SET_CMD			"PNOSSIDCLR"
++/* Lin - Is the extra space needed? */
++#define PNOSETUP_SET_CMD			"PNOSETUP " /* TLV command has extra end space */
++#define PNOENABLE_SET_CMD			"PNOFORCE"
++#define PNODEBUG_SET_CMD			"PNODEBUG"
++#define TXPOWER_SET_CMD			"TXPOWER"
++
++#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
++#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
++
++/* Structure to keep global parameters */
++typedef struct wl_iw_extra_params {
++	int 	target_channel; /* target channel */
++} wl_iw_extra_params_t;
++
++/* ============================================== */
++/* Defines from wlc_pub.h */
++#define	WL_IW_RSSI_MINVAL		-200	/* Low value, e.g. for forcing roam */
++#define	WL_IW_RSSI_NO_SIGNAL	-91	/* NDIS RSSI link quality cutoffs */
++#define	WL_IW_RSSI_VERY_LOW	-80	/* Very low quality cutoffs */
++#define	WL_IW_RSSI_LOW		-70	/* Low quality cutoffs */
++#define	WL_IW_RSSI_GOOD		-68	/* Good quality cutoffs */
++#define	WL_IW_RSSI_VERY_GOOD	-58	/* Very good quality cutoffs */
++#define	WL_IW_RSSI_EXCELLENT	-57	/* Excellent quality cutoffs */
++#define	WL_IW_RSSI_INVALID	 0	/* invalid RSSI value */
++#define MAX_WX_STRING 80
++#define SSID_FMT_BUF_LEN	((4 * 32) + 1)
++#define isprint(c) bcm_isprint(c)
++#define WL_IW_SET_ACTIVE_SCAN	(SIOCIWFIRSTPRIV+1)
++#define WL_IW_GET_RSSI			(SIOCIWFIRSTPRIV+3)
++#define WL_IW_SET_PASSIVE_SCAN	(SIOCIWFIRSTPRIV+5)
++#define WL_IW_GET_LINK_SPEED	(SIOCIWFIRSTPRIV+7)
++#define WL_IW_GET_CURR_MACADDR	(SIOCIWFIRSTPRIV+9)
++#define WL_IW_SET_STOP				(SIOCIWFIRSTPRIV+11)
++#define WL_IW_SET_START			(SIOCIWFIRSTPRIV+13)
++
++#define 		G_SCAN_RESULTS 8*1024
++#define 		WE_ADD_EVENT_FIX	0x80
++#define          G_WLAN_SET_ON	0
++#define          G_WLAN_SET_OFF	1
++
++
++typedef struct wl_iw {
++	char nickname[IW_ESSID_MAX_SIZE];
++
++	struct iw_statistics wstats;
++
++	int spy_num;
++	uint32 pwsec;			/* pairwise wsec setting */
++	uint32 gwsec;			/* group wsec setting  */
++	bool privacy_invoked; 		/* IW_AUTH_PRIVACY_INVOKED setting */
++	struct ether_addr spy_addr[IW_MAX_SPY];
++	struct iw_quality spy_qual[IW_MAX_SPY];
++	void  *wlinfo;
++} wl_iw_t;
++
++struct wl_ctrl {
++	timer_list_compat_t *timer;
++	struct net_device *dev;
++	long sysioc_pid;
++	struct semaphore sysioc_sem;
++	struct completion sysioc_exited;
++};
++
++
++#if WIRELESS_EXT > 12
++#include <net/iw_handler.h>
++extern const struct iw_handler_def wl_iw_handler_def;
++#endif /* WIRELESS_EXT > 12 */
++
++extern int wl_iw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
++extern int wl_iw_get_wireless_stats(struct net_device *dev, struct iw_statistics *wstats);
++int wl_iw_send_priv_event(struct net_device *dev, char *flag);
++#ifdef WL_ESCAN
++int wl_iw_handle_scanresults_ies(char **event_p, char *end,
++	struct iw_request_info *info, wl_bss_info_t *bi);
++#endif
++int wl_iw_attach(struct net_device *dev, dhd_pub_t *dhdp);
++void wl_iw_detach(struct net_device *dev, dhd_pub_t *dhdp);
++int wl_iw_up(struct net_device *dev, dhd_pub_t *dhdp);
++void wl_iw_down(struct net_device *dev, dhd_pub_t *dhdp);
++s32 wl_iw_autochannel(struct net_device *dev, char* command, int total_len);
++
++/* message levels */
++#define WL_ERROR_LEVEL	(1 << 0)
++#define WL_TRACE_LEVEL	(1 << 1)
++#define WL_INFO_LEVEL	(1 << 2)
++#define WL_SCAN_LEVEL	(1 << 3)
++#define WL_WSEC_LEVEL	(1 << 4)
++
++#define CSCAN_COMMAND				"CSCAN "
++#define CSCAN_TLV_PREFIX 			'S'
++#define CSCAN_TLV_VERSION			1
++#define CSCAN_TLV_SUBVERSION			0
++#define CSCAN_TLV_TYPE_SSID_IE          'S'
++#define CSCAN_TLV_TYPE_CHANNEL_IE   'C'
++#define CSCAN_TLV_TYPE_NPROBE_IE     'N'
++#define CSCAN_TLV_TYPE_ACTIVE_IE      'A'
++#define CSCAN_TLV_TYPE_PASSIVE_IE    'P'
++#define CSCAN_TLV_TYPE_HOME_IE         'H'
++#define CSCAN_TLV_TYPE_STYPE_IE        'T'
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++#define IWE_STREAM_ADD_EVENT(info, stream, ends, iwe, extra) \
++	iwe_stream_add_event(info, stream, ends, iwe, extra)
++#define IWE_STREAM_ADD_VALUE(info, event, value, ends, iwe, event_len) \
++	iwe_stream_add_value(info, event, value, ends, iwe, event_len)
++#define IWE_STREAM_ADD_POINT(info, stream, ends, iwe, extra) \
++	iwe_stream_add_point(info, stream, ends, iwe, extra)
++#else
++#define IWE_STREAM_ADD_EVENT(info, stream, ends, iwe, extra) \
++	iwe_stream_add_event(stream, ends, iwe, extra)
++#define IWE_STREAM_ADD_VALUE(info, event, value, ends, iwe, event_len) \
++	iwe_stream_add_value(event, value, ends, iwe, event_len)
++#define IWE_STREAM_ADD_POINT(info, stream, ends, iwe, extra) \
++	iwe_stream_add_point(stream, ends, iwe, extra)
++#endif
++
++#endif /* _wl_iw_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_linux_mon.c b/module_drivers/drivers/net/wireless/bcmdhd/wl_linux_mon.c
+new file mode 100644
+index 000000000..75a417ba9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_linux_mon.c
+@@ -0,0 +1,406 @@
++/*
++ * Broadcom Dongle Host Driver (DHD), Linux monitor network interface
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_linux_mon.c 576195 2015-08-01 18:21:54Z $
++ */
++
++#include <osl.h>
++#include <linux/string.h>
++#include <linux/module.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/if_arp.h>
++#include <linux/ieee80211.h>
++#include <linux/rtnetlink.h>
++#include <net/ieee80211_radiotap.h>
++
++#include <wlioctl.h>
++#include <bcmutils.h>
++#include <dhd_dbg.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++
++typedef enum monitor_states
++{
++	MONITOR_STATE_DEINIT = 0x0,
++	MONITOR_STATE_INIT = 0x1,
++	MONITOR_STATE_INTERFACE_ADDED = 0x2,
++	MONITOR_STATE_INTERFACE_DELETED = 0x4
++} monitor_states_t;
++int dhd_add_monitor(const char *name, struct net_device **new_ndev);
++extern int dhd_start_xmit(struct sk_buff *skb, struct net_device *net);
++int dhd_del_monitor(struct net_device *ndev);
++int dhd_monitor_init(void *dhd_pub);
++int dhd_monitor_uninit(void);
++
++/**
++ * Local declarations and defintions (not exposed)
++ */
++#ifndef DHD_MAX_IFS
++#define DHD_MAX_IFS 16
++#endif
++#define MON_PRINT(format, ...) printk("DHD-MON: %s " format, __func__, ##__VA_ARGS__)
++#define MON_TRACE MON_PRINT
++
++typedef struct monitor_interface {
++	int radiotap_enabled;
++	struct net_device* real_ndev;	/* The real interface that the monitor is on */
++	struct net_device* mon_ndev;
++} monitor_interface;
++
++typedef struct dhd_linux_monitor {
++	void *dhd_pub;
++	monitor_states_t monitor_state;
++	monitor_interface mon_if[DHD_MAX_IFS];
++	struct mutex lock;		/* lock to protect mon_if */
++} dhd_linux_monitor_t;
++
++static dhd_linux_monitor_t g_monitor;
++
++static struct net_device* lookup_real_netdev(const char *name);
++static monitor_interface* ndev_to_monif(struct net_device *ndev);
++static int dhd_mon_if_open(struct net_device *ndev);
++static int dhd_mon_if_stop(struct net_device *ndev);
++static int dhd_mon_if_subif_start_xmit(struct sk_buff *skb, struct net_device *ndev);
++static void dhd_mon_if_set_multicast_list(struct net_device *ndev);
++static int dhd_mon_if_change_mac(struct net_device *ndev, void *addr);
++
++static const struct net_device_ops dhd_mon_if_ops = {
++	.ndo_open		= dhd_mon_if_open,
++	.ndo_stop		= dhd_mon_if_stop,
++	.ndo_start_xmit		= dhd_mon_if_subif_start_xmit,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	.ndo_set_rx_mode = dhd_mon_if_set_multicast_list,
++#else
++	.ndo_set_multicast_list = dhd_mon_if_set_multicast_list,
++#endif
++	.ndo_set_mac_address 	= dhd_mon_if_change_mac,
++};
++
++/**
++ * Local static function defintions
++ */
++
++/* Look up dhd's net device table to find a match (e.g. interface "eth0" is a match for "mon.eth0"
++ * "p2p-eth0-0" is a match for "mon.p2p-eth0-0")
++ */
++static struct net_device* lookup_real_netdev(const char *name)
++{
++	struct net_device *ndev_found = NULL;
++
++	int i;
++	int len = 0;
++	int last_name_len = 0;
++	struct net_device *ndev;
++
++	/* We need to find interface "p2p-p2p-0" corresponding to monitor interface "mon-p2p-0",
++	 * Once mon iface name reaches IFNAMSIZ, it is reset to p2p0-0 and corresponding mon
++	 * iface would be mon-p2p0-0.
++	 */
++	for (i = 0; i < DHD_MAX_IFS; i++) {
++		ndev = dhd_idx2net(g_monitor.dhd_pub, i);
++
++		/* Skip "p2p" and look for "-p2p0-x" in monitor interface name. If it
++		 * it matches, then this netdev is the corresponding real_netdev.
++		 */
++		if (ndev && strstr(ndev->name, "p2p-p2p0")) {
++			len = strlen("p2p");
++		} else {
++		/* if p2p- is not present, then the IFNAMSIZ have reached and name
++		 * would have got reset. In this casse,look for p2p0-x in mon-p2p0-x
++		 */
++			len = 0;
++		}
++		if (ndev && strstr(name, (ndev->name + len))) {
++			if (strlen(ndev->name) > last_name_len) {
++				ndev_found = ndev;
++				last_name_len = strlen(ndev->name);
++			}
++		}
++	}
++
++	return ndev_found;
++}
++
++static monitor_interface* ndev_to_monif(struct net_device *ndev)
++{
++	int i;
++
++	for (i = 0; i < DHD_MAX_IFS; i++) {
++		if (g_monitor.mon_if[i].mon_ndev == ndev)
++			return &g_monitor.mon_if[i];
++	}
++
++	return NULL;
++}
++
++static int dhd_mon_if_open(struct net_device *ndev)
++{
++	int ret = 0;
++
++	MON_PRINT("enter\n");
++	return ret;
++}
++
++static int dhd_mon_if_stop(struct net_device *ndev)
++{
++	int ret = 0;
++
++	MON_PRINT("enter\n");
++	return ret;
++}
++
++static int dhd_mon_if_subif_start_xmit(struct sk_buff *skb, struct net_device *ndev)
++{
++	int ret = 0;
++	int rtap_len;
++	int qos_len = 0;
++	int dot11_hdr_len = 24;
++	int snap_len = 6;
++	unsigned char *pdata;
++	unsigned short frame_ctl;
++	unsigned char src_mac_addr[6];
++	unsigned char dst_mac_addr[6];
++	struct ieee80211_hdr *dot11_hdr;
++	struct ieee80211_radiotap_header *rtap_hdr;
++	monitor_interface* mon_if;
++
++	MON_PRINT("enter\n");
++
++	mon_if = ndev_to_monif(ndev);
++	if (mon_if == NULL || mon_if->real_ndev == NULL) {
++		MON_PRINT(" cannot find matched net dev, skip the packet\n");
++		goto fail;
++	}
++
++	if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header)))
++		goto fail;
++
++	rtap_hdr = (struct ieee80211_radiotap_header *)skb->data;
++	if (unlikely(rtap_hdr->it_version))
++		goto fail;
++
++	rtap_len = ieee80211_get_radiotap_len(skb->data);
++	if (unlikely(skb->len < rtap_len))
++		goto fail;
++
++	MON_PRINT("radiotap len (should be 14): %d\n", rtap_len);
++
++	/* Skip the ratio tap header */
++	skb_pull(skb, rtap_len);
++
++	dot11_hdr = (struct ieee80211_hdr *)skb->data;
++	frame_ctl = le16_to_cpu(dot11_hdr->frame_control);
++	/* Check if the QoS bit is set */
++	if ((frame_ctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) {
++		/* Check if this ia a Wireless Distribution System (WDS) frame
++		 * which has 4 MAC addresses
++		 */
++		if (dot11_hdr->frame_control & 0x0080)
++			qos_len = 2;
++		if ((dot11_hdr->frame_control & 0x0300) == 0x0300)
++			dot11_hdr_len += 6;
++
++		memcpy(dst_mac_addr, dot11_hdr->addr1, sizeof(dst_mac_addr));
++		memcpy(src_mac_addr, dot11_hdr->addr2, sizeof(src_mac_addr));
++
++		/* Skip the 802.11 header, QoS (if any) and SNAP, but leave spaces for
++		 * for two MAC addresses
++		 */
++		skb_pull(skb, dot11_hdr_len + qos_len + snap_len - sizeof(src_mac_addr) * 2);
++		pdata = (unsigned char*)skb->data;
++		memcpy(pdata, dst_mac_addr, sizeof(dst_mac_addr));
++		memcpy(pdata + sizeof(dst_mac_addr), src_mac_addr, sizeof(src_mac_addr));
++		PKTSETPRIO(skb, 0);
++
++		MON_PRINT("if name: %s, matched if name %s\n", ndev->name, mon_if->real_ndev->name);
++
++		/* Use the real net device to transmit the packet */
++		ret = dhd_start_xmit(skb, mon_if->real_ndev);
++
++		return ret;
++	}
++fail:
++	dev_kfree_skb(skb);
++	return 0;
++}
++
++static void dhd_mon_if_set_multicast_list(struct net_device *ndev)
++{
++	monitor_interface* mon_if;
++
++	mon_if = ndev_to_monif(ndev);
++	if (mon_if == NULL || mon_if->real_ndev == NULL) {
++		MON_PRINT(" cannot find matched net dev, skip the packet\n");
++	} else {
++		MON_PRINT("enter, if name: %s, matched if name %s\n",
++		ndev->name, mon_if->real_ndev->name);
++	}
++}
++
++static int dhd_mon_if_change_mac(struct net_device *ndev, void *addr)
++{
++	int ret = 0;
++	monitor_interface* mon_if;
++
++	mon_if = ndev_to_monif(ndev);
++	if (mon_if == NULL || mon_if->real_ndev == NULL) {
++		MON_PRINT(" cannot find matched net dev, skip the packet\n");
++	} else {
++		MON_PRINT("enter, if name: %s, matched if name %s\n",
++		ndev->name, mon_if->real_ndev->name);
++	}
++	return ret;
++}
++
++/**
++ * Global function definitions (declared in dhd_linux_mon.h)
++ */
++
++int dhd_add_monitor(const char *name, struct net_device **new_ndev)
++{
++	int i;
++	int idx = -1;
++	int ret = 0;
++	struct net_device* ndev = NULL;
++	dhd_linux_monitor_t **dhd_mon;
++
++	mutex_lock(&g_monitor.lock);
++
++	MON_TRACE("enter, if name: %s\n", name);
++	if (!name || !new_ndev) {
++		MON_PRINT("invalid parameters\n");
++		ret = -EINVAL;
++		goto out;
++	}
++
++	/*
++	 * Find a vacancy
++	 */
++	for (i = 0; i < DHD_MAX_IFS; i++)
++		if (g_monitor.mon_if[i].mon_ndev == NULL) {
++			idx = i;
++			break;
++		}
++	if (idx == -1) {
++		MON_PRINT("exceeds maximum interfaces\n");
++		ret = -EFAULT;
++		goto out;
++	}
++
++	ndev = alloc_etherdev(sizeof(dhd_linux_monitor_t*));
++	if (!ndev) {
++		MON_PRINT("failed to allocate memory\n");
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	ndev->type = ARPHRD_IEEE80211_RADIOTAP;
++	strncpy(ndev->name, name, IFNAMSIZ);
++	ndev->name[IFNAMSIZ - 1] = 0;
++	ndev->netdev_ops = &dhd_mon_if_ops;
++
++	ret = register_netdevice(ndev);
++	if (ret) {
++		MON_PRINT(" register_netdevice failed (%d)\n", ret);
++		goto out;
++	}
++
++	*new_ndev = ndev;
++	g_monitor.mon_if[idx].radiotap_enabled = TRUE;
++	g_monitor.mon_if[idx].mon_ndev = ndev;
++	g_monitor.mon_if[idx].real_ndev = lookup_real_netdev(name);
++	dhd_mon = (dhd_linux_monitor_t **)netdev_priv(ndev);
++	*dhd_mon = &g_monitor;
++	g_monitor.monitor_state = MONITOR_STATE_INTERFACE_ADDED;
++	MON_PRINT("net device returned: 0x%p\n", ndev);
++	MON_PRINT("found a matched net device, name %s\n", g_monitor.mon_if[idx].real_ndev->name);
++
++out:
++	if (ret && ndev)
++		free_netdev(ndev);
++
++	mutex_unlock(&g_monitor.lock);
++	return ret;
++
++}
++
++int dhd_del_monitor(struct net_device *ndev)
++{
++	int i;
++	if (!ndev)
++		return -EINVAL;
++	mutex_lock(&g_monitor.lock);
++	for (i = 0; i < DHD_MAX_IFS; i++) {
++		if (g_monitor.mon_if[i].mon_ndev == ndev ||
++			g_monitor.mon_if[i].real_ndev == ndev) {
++
++			g_monitor.mon_if[i].real_ndev = NULL;
++			unregister_netdevice(g_monitor.mon_if[i].mon_ndev);
++			free_netdev(g_monitor.mon_if[i].mon_ndev);
++			g_monitor.mon_if[i].mon_ndev = NULL;
++			g_monitor.monitor_state = MONITOR_STATE_INTERFACE_DELETED;
++			break;
++		}
++	}
++
++	if (g_monitor.monitor_state != MONITOR_STATE_INTERFACE_DELETED)
++		MON_PRINT("IF not found in monitor array, is this a monitor IF? 0x%p\n", ndev);
++	mutex_unlock(&g_monitor.lock);
++
++	return 0;
++}
++
++int dhd_monitor_init(void *dhd_pub)
++{
++	if (g_monitor.monitor_state == MONITOR_STATE_DEINIT) {
++		g_monitor.dhd_pub = dhd_pub;
++		mutex_init(&g_monitor.lock);
++		g_monitor.monitor_state = MONITOR_STATE_INIT;
++	}
++	return 0;
++}
++
++int dhd_monitor_uninit(void)
++{
++	int i;
++	struct net_device *ndev;
++	if (g_monitor.monitor_state != MONITOR_STATE_DEINIT) {
++		mutex_lock(&g_monitor.lock);
++		for (i = 0; i < DHD_MAX_IFS; i++) {
++			ndev = g_monitor.mon_if[i].mon_ndev;
++			if (ndev) {
++				unregister_netdevice(ndev);
++				free_netdev(ndev);
++				g_monitor.mon_if[i].real_ndev = NULL;
++				g_monitor.mon_if[i].mon_ndev = NULL;
++			}
++		}
++		g_monitor.monitor_state = MONITOR_STATE_DEINIT;
++		mutex_unlock(&g_monitor.lock);
++	}
++	return 0;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wl_roam.c b/module_drivers/drivers/net/wireless/bcmdhd/wl_roam.c
+new file mode 100644
+index 000000000..ec68d9ad6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wl_roam.c
+@@ -0,0 +1,28 @@
++/*
++ * Linux roam cache
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_roam.c 662434 2016-09-29 12:21:46Z $
++ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wlc_types.h b/module_drivers/drivers/net/wireless/bcmdhd/wlc_types.h
+new file mode 100644
+index 000000000..7252cbd20
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wlc_types.h
+@@ -0,0 +1,337 @@
++/*
++ * Forward declarations for commonly used wl driver structs
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wlc_types.h 665242 2016-10-17 05:59:26Z $
++ */
++
++#ifndef _wlc_types_h_
++#define _wlc_types_h_
++#include <wlioctl.h>
++
++/* Version of WLC interface to be returned as a part of wl_wlc_version structure.
++ * WLC_API_VERSION_MINOR is currently not in use.
++ */
++#define WLC_API_VERSION_MAJOR      8
++#define WLC_API_VERSION_MINOR      0
++
++/* forward declarations */
++
++typedef struct wlc_info wlc_info_t;
++typedef struct wlcband wlcband_t;
++typedef struct wlc_cmn_info wlc_cmn_info_t;
++typedef struct wlc_assoc_info wlc_assoc_info_t;
++typedef struct wlc_pm_info wlc_pm_info_t;
++
++typedef struct wlc_bsscfg wlc_bsscfg_t;
++typedef struct wlc_mbss_info wlc_mbss_info_t;
++typedef struct wlc_spt wlc_spt_t;
++typedef struct scb scb_t;
++typedef struct scb_iter scb_iter_t;
++typedef struct vndr_ie_listel vndr_ie_listel_t;
++typedef struct wlc_if wlc_if_t;
++typedef struct wl_if wl_if_t;
++typedef struct led_info led_info_t;
++typedef struct bmac_led bmac_led_t;
++typedef struct bmac_led_info bmac_led_info_t;
++typedef struct seq_cmds_info wlc_seq_cmds_info_t;
++typedef struct ota_test_info ota_test_info_t;
++typedef struct wlc_ccx ccx_t;
++typedef struct wlc_ccx_rm ccx_rm_t;
++typedef struct apps_wlc_psinfo apps_wlc_psinfo_t;
++typedef struct scb_module scb_module_t;
++typedef struct ba_info ba_info_t;
++typedef struct wlc_frminfo wlc_frminfo_t;
++typedef struct amsdu_info amsdu_info_t;
++typedef struct txq_info txq_info_t;
++typedef struct txq txq_t;
++typedef struct cram_info cram_info_t;
++typedef struct wlc_extlog_info wlc_extlog_info_t;
++typedef struct wlc_txq_info wlc_txq_info_t;
++typedef struct wlc_hrt_info wlc_hrt_info_t;
++typedef struct wlc_hrt_to wlc_hrt_to_t;
++typedef struct wlc_cac wlc_cac_t;
++typedef struct ampdu_tx_info ampdu_tx_info_t;
++typedef struct ampdu_rx_info ampdu_rx_info_t;
++typedef struct wlc_ratesel_info wlc_ratesel_info_t;
++typedef struct ratesel_info ratesel_info_t;
++typedef struct wlc_ap_info wlc_ap_info_t;
++typedef struct cs_info cs_info_t;
++typedef struct wlc_scan_info wlc_scan_info_t;
++typedef struct wlc_scan_cmn_info wlc_scan_cmn_t;
++typedef struct tdls_info tdls_info_t;
++typedef struct dls_info dls_info_t;
++typedef struct l2_filter_info l2_filter_info_t;
++typedef struct wlc_auth_info wlc_auth_info_t;
++typedef struct wlc_sup_info wlc_sup_info_t;
++typedef struct wlc_fbt_info wlc_fbt_info_t;
++typedef struct wlc_assoc_mgr_info wlc_assoc_mgr_info_t;
++typedef struct wlc_ccxsup_info wlc_ccxsup_info_t;
++typedef struct wlc_psta_info wlc_psta_info_t;
++typedef struct wlc_mcnx_info wlc_mcnx_info_t;
++typedef struct wlc_p2p_info wlc_p2p_info_t;
++typedef struct wlc_cxnoa_info wlc_cxnoa_info_t;
++typedef struct mchan_info mchan_info_t;
++typedef struct wlc_mchan_context wlc_mchan_context_t;
++typedef struct bta_info bta_info_t;
++typedef struct wowl_info wowl_info_t;
++typedef struct wowlpf_info wowlpf_info_t;
++typedef struct wlc_plt_info wlc_plt_pub_t;
++typedef struct antsel_info antsel_info_t;
++typedef struct bmac_pmq bmac_pmq_t;
++typedef struct wmf_info wmf_info_t;
++typedef struct wlc_rrm_info wlc_rrm_info_t;
++typedef struct rm_info rm_info_t;
++
++struct d11init;
++
++typedef struct wlc_dpc_info wlc_dpc_info_t;
++
++typedef struct wlc_11h_info wlc_11h_info_t;
++typedef struct wlc_tpc_info wlc_tpc_info_t;
++typedef struct wlc_csa_info wlc_csa_info_t;
++typedef struct wlc_quiet_info wlc_quiet_info_t;
++typedef struct cca_info cca_info_t;
++typedef struct itfr_info itfr_info_t;
++
++typedef struct wlc_wnm_info wlc_wnm_info_t;
++typedef struct wlc_11d_info wlc_11d_info_t;
++typedef struct wlc_cntry_info wlc_cntry_info_t;
++
++typedef struct wlc_dfs_info wlc_dfs_info_t;
++
++typedef struct bsscfg_module bsscfg_module_t;
++
++typedef struct wlc_prot_info wlc_prot_info_t;
++typedef struct wlc_prot_g_info wlc_prot_g_info_t;
++typedef struct wlc_prot_n_info wlc_prot_n_info_t;
++typedef struct wlc_prot_obss_info wlc_prot_obss_info_t;
++typedef struct wlc_obss_dynbw wlc_obss_dynbw_t;
++typedef struct wlc_11u_info wlc_11u_info_t;
++typedef struct wlc_probresp_info wlc_probresp_info_t;
++typedef struct wlc_wapi_info wlc_wapi_info_t;
++
++typedef struct wlc_tbtt_info wlc_tbtt_info_t;
++typedef struct wlc_nic_info wlc_nic_info_t;
++
++typedef struct wlc_bssload_info wlc_bssload_info_t;
++
++typedef struct wlc_pcb_info wlc_pcb_info_t;
++typedef struct wlc_txc_info wlc_txc_info_t;
++
++typedef struct wlc_trf_mgmt_ctxt    wlc_trf_mgmt_ctxt_t;
++typedef struct wlc_trf_mgmt_info    wlc_trf_mgmt_info_t;
++
++typedef struct wlc_net_detect_ctxt  wlc_net_detect_ctxt_t;
++
++typedef struct wlc_powersel_info wlc_powersel_info_t;
++typedef struct powersel_info powersel_info_t;
++
++typedef struct wlc_lpc_info wlc_lpc_info_t;
++typedef struct lpc_info lpc_info_t;
++typedef struct rate_lcb_info rate_lcb_info_t;
++typedef struct wlc_txbf_info wlc_txbf_info_t;
++typedef struct wlc_murx_info wlc_murx_info_t;
++
++typedef struct wlc_olpc_eng_info_t wlc_olpc_eng_info_t;
++/* used by olpc to register for callbacks from stf */
++typedef void (*wlc_stf_txchain_evt_notify)(wlc_info_t *wlc);
++
++typedef struct wlc_rfc wlc_rfc_t;
++typedef struct wlc_pktc_info wlc_pktc_info_t;
++
++typedef struct wlc_mfp_info wlc_mfp_info_t;
++
++typedef struct wlc_mdns_info wlc_mdns_info_t;
++
++typedef struct wlc_macfltr_info wlc_macfltr_info_t;
++typedef struct wlc_bmon_info wlc_bmon_info_t;
++
++typedef struct wlc_nar_info wlc_nar_info_t;
++typedef struct wlc_bs_data_info wlc_bs_data_info_t;
++
++typedef struct wlc_keymgmt wlc_keymgmt_t;
++typedef struct wlc_key	wlc_key_t;
++typedef struct wlc_key_info wlc_key_info_t;
++
++typedef struct wlc_hw wlc_hw_t;
++typedef struct wlc_hw_info wlc_hw_info_t;
++typedef struct wlc_hwband wlc_hwband_t;
++
++typedef struct wlc_rx_stall_info wlc_rx_stall_info_t;
++
++typedef struct wlc_rmc_info wlc_rmc_info_t;
++
++typedef struct wlc_iem_info wlc_iem_info_t;
++
++typedef struct wlc_ier_info wlc_ier_info_t;
++typedef struct wlc_ier_reg wlc_ier_reg_t;
++
++typedef struct wlc_ht_info wlc_ht_info_t;
++typedef struct wlc_obss_info wlc_obss_info_t;
++typedef struct wlc_vht_info wlc_vht_info_t;
++typedef struct wlc_akm_info wlc_akm_info_t;
++typedef struct wlc_srvsdb_info wlc_srvsdb_info_t;
++
++typedef struct wlc_bss_info wlc_bss_info_t;
++
++typedef struct wlc_hs20_info wlc_hs20_info_t;
++typedef struct wlc_pmkid_info	wlc_pmkid_info_t;
++typedef struct wlc_btc_info wlc_btc_info_t;
++
++typedef struct wlc_txh_info wlc_txh_info_t;
++typedef union wlc_txd wlc_txd_t;
++
++typedef struct wlc_staprio_info wlc_staprio_info_t;
++typedef struct wlc_stamon_info wlc_stamon_info_t;
++typedef struct wlc_monitor_info wlc_monitor_info_t;
++
++typedef struct wlc_debug_crash_info wlc_debug_crash_info_t;
++
++typedef struct wlc_nan_info wlc_nan_info_t;
++typedef struct wlc_tsmap_info wlc_tsmap_info_t;
++
++typedef struct wlc_wds_info wlc_wds_info_t;
++typedef struct okc_info okc_info_t;
++typedef struct wlc_aibss_info wlc_aibss_info_t;
++typedef struct wlc_ipfo_info wlc_ipfo_info_t;
++typedef struct wlc_stats_info wlc_stats_info_t;
++
++typedef struct wlc_pps_info wlc_pps_info_t;
++
++typedef struct duration_info duration_info_t;
++
++typedef struct wlc_pdsvc_info wlc_pdsvc_info_t;
++
++/* For LTE Coex */
++typedef struct wlc_ltecx_info wlc_ltecx_info_t;
++
++typedef struct wlc_probresp_mac_filter_info wlc_probresp_mac_filter_info_t;
++
++typedef struct wlc_ltr_info wlc_ltr_info_t;
++
++typedef struct bwte_info bwte_info_t;
++
++typedef struct tbow_info tbow_info_t;
++
++typedef struct wlc_modesw_info wlc_modesw_info_t;
++
++typedef struct wlc_pm_mute_tx_info wlc_pm_mute_tx_t;
++
++typedef struct wlc_bcntrim_info wlc_bcntrim_info_t;
++
++typedef struct wlc_smfs_info wlc_smfs_info_t;
++typedef struct wlc_misc_info wlc_misc_info_t;
++typedef struct wlc_ulb_info wlc_ulb_info_t;
++
++typedef struct wlc_eventq wlc_eventq_t;
++typedef struct wlc_event wlc_event_t;
++typedef struct wlc_ulp_info wlc_ulp_info_t;
++
++typedef struct wlc_bsscfg_psq_info wlc_bsscfg_psq_info_t;
++typedef struct wlc_bsscfg_viel_info wlc_bsscfg_viel_info_t;
++
++typedef struct wlc_txmod_info wlc_txmod_info_t;
++typedef struct tx_path_node tx_path_node_t;
++
++typedef struct wlc_linkstats_info wlc_linkstats_info_t;
++typedef struct wlc_lq_info wlc_lq_info_t;
++typedef struct chanim_info chanim_info_t;
++
++typedef struct wlc_mesh_info wlc_mesh_info_t;
++typedef struct wlc_wlfc_info wlc_wlfc_info_t;
++
++typedef struct wlc_frag_info wlc_frag_info_t;
++typedef struct wlc_bss_list wlc_bss_list_t;
++
++typedef struct wlc_msch_info wlc_msch_info_t;
++typedef struct wlc_msch_req_handle wlc_msch_req_handle_t;
++
++typedef struct wlc_randmac_info wlc_randmac_info_t;
++
++typedef struct wlc_chanctxt wlc_chanctxt_t;
++typedef struct wlc_chanctxt_info wlc_chanctxt_info_t;
++typedef struct wlc_sta_info wlc_sta_info_t;
++
++typedef struct health_check_info health_check_info_t;
++typedef struct wlc_act_frame_info wlc_act_frame_info_t;
++typedef struct nan_sched_req_handle nan_sched_req_handle_t;
++
++typedef struct wlc_qos_info wlc_qos_info_t;
++
++typedef struct wlc_assoc wlc_assoc_t;
++typedef struct wlc_roam wlc_roam_t;
++typedef struct wlc_pm_st wlc_pm_st_t;
++typedef struct wlc_wme wlc_wme_t;
++
++typedef struct wlc_link_qual wlc_link_qual_t;
++
++typedef struct wlc_rsdb_info wlc_rsdb_info_t;
++
++typedef struct wlc_asdb wlc_asdb_t;
++
++typedef struct rsdb_common_info rsdb_cmn_info_t;
++
++typedef struct wlc_macdbg_info wlc_macdbg_info_t;
++typedef struct wlc_rspec_info wlc_rspec_info_t;
++typedef struct wlc_ndis_info wlc_ndis_info_t;
++
++typedef struct wlc_join_pref wlc_join_pref_t;
++
++typedef struct wlc_scan_utils wlc_scan_utils_t;
++#ifdef ACKSUPR_MAC_FILTER
++typedef struct wlc_addrmatch_info wlc_addrmatch_info_t;
++#endif /* ACKSUPR_MAC_FILTER */
++
++typedef struct cca_ucode_counts cca_ucode_counts_t;
++typedef struct cca_chan_qual cca_chan_qual_t;
++
++typedef struct wlc_perf_utils wlc_perf_utils_t;
++typedef struct wlc_test_info wlc_test_info_t;
++
++typedef struct chanswitch_times chanswitch_times_t;
++typedef struct wlc_dump_info wlc_dump_info_t;
++
++typedef struct wlc_stf wlc_stf_t;
++
++typedef sta_info_v4_t sta_info_t;
++typedef struct wl_roam_prof_band_v2 wl_roam_prof_band_t;
++typedef struct wl_roam_prof_v2 wl_roam_prof_t;
++
++/* Inteface version mapping for versioned pfn structures */
++#undef PFN_SCANRESULT_VERSION
++#define PFN_SCANRESULT_VERSION PFN_SCANRESULT_VERSION_V2
++#define PFN_SCANRESULTS_VERSION PFN_SCANRESULTS_VERSION_V2
++#define PFN_LBEST_SCAN_RESULT_VERSION PFN_LBEST_SCAN_RESULT_VERSION_V2
++typedef wl_pfn_subnet_info_v2_t wl_pfn_subnet_info_t;
++typedef wl_pfn_net_info_v2_t wl_pfn_net_info_t;
++typedef wl_pfn_lnet_info_v2_t wl_pfn_lnet_info_t;
++typedef wl_pfn_lscanresults_v2_t wl_pfn_lscanresults_t;
++typedef wl_pfn_scanresults_v2_t wl_pfn_scanresults_t;
++typedef wl_pfn_scanresult_v2_t wl_pfn_scanresult_t;
++
++typedef wl_dfs_ap_move_status_v2_t wl_dfs_ap_move_status_t;
++
++#endif	/* _wlc_types_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wldev_common.c b/module_drivers/drivers/net/wireless/bcmdhd/wldev_common.c
+new file mode 100644
+index 000000000..7bf19c398
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wldev_common.c
+@@ -0,0 +1,540 @@
++/*
++ * Common function shared by Linux WEXT, cfg80211 and p2p drivers
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wldev_common.c 699163 2017-05-12 05:18:23Z $
++ */
++
++#include <osl.h>
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/netdevice.h>
++
++#include <wldev_common.h>
++#include <bcmutils.h>
++#ifdef WL_CFG80211
++#include <wl_cfg80211.h>
++#endif
++#include <dhd_config.h>
++
++#define htod32(i) (i)
++#define htod16(i) (i)
++#define dtoh32(i) (i)
++#define dtoh16(i) (i)
++#define htodchanspec(i) (i)
++#define dtohchanspec(i) (i)
++
++#define	WLDEV_ERROR_MSG(x, args...)						\
++	do {												\
++		printk(KERN_INFO "[dhd] WLDEV-ERROR) " x, ## args);	\
++	} while (0)
++#define WLDEV_ERROR(x) WLDEV_ERROR_MSG x
++
++#define	WLDEV_INFO_MSG(x, args...)						\
++	do {												\
++		printk(KERN_INFO "[dhd] WLDEV-INFO) " x, ## args);	\
++	} while (0)
++#define WLDEV_INFO(x) WLDEV_INFO_MSG x
++
++extern int dhd_ioctl_entry_local(struct net_device *net, wl_ioctl_t *ioc, int cmd);
++
++s32 wldev_ioctl(
++	struct net_device *dev, u32 cmd, void *arg, u32 len, u32 set)
++{
++	s32 ret = 0;
++	struct wl_ioctl ioc;
++
++
++	memset(&ioc, 0, sizeof(ioc));
++	ioc.cmd = cmd;
++	ioc.buf = arg;
++	ioc.len = len;
++	ioc.set = set;
++
++	ret = dhd_ioctl_entry_local(dev, &ioc, cmd);
++
++	return ret;
++}
++
++
++/*
++SET commands :
++cast buffer to non-const  and call the GET function
++*/
++
++s32 wldev_ioctl_set(
++	struct net_device *dev, u32 cmd, const void *arg, u32 len)
++{
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	return wldev_ioctl(dev, cmd, (void *)arg, len, 1);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++}
++
++
++s32 wldev_ioctl_get(
++	struct net_device *dev, u32 cmd, void *arg, u32 len)
++{
++	return wldev_ioctl(dev, cmd, (void *)arg, len, 0);
++}
++
++/* Format a iovar buffer, not bsscfg indexed. The bsscfg index will be
++ * taken care of in dhd_ioctl_entry. Internal use only, not exposed to
++ * wl_iw, wl_cfg80211 and wl_cfgp2p
++ */
++static s32 wldev_mkiovar(
++	const s8 *iovar_name, s8 *param, s32 paramlen,
++	s8 *iovar_buf, u32 buflen)
++{
++	s32 iolen = 0;
++
++	iolen = bcm_mkiovar(iovar_name, param, paramlen, iovar_buf, buflen);
++	return iolen;
++}
++
++s32 wldev_iovar_getbuf(
++	struct net_device *dev, s8 *iovar_name,
++	void *param, s32 paramlen, void *buf, s32 buflen, struct mutex* buf_sync)
++{
++	s32 ret = 0;
++	if (buf_sync) {
++		mutex_lock(buf_sync);
++	}
++
++	if (buf && (buflen > 0)) {
++		/* initialize the response buffer */
++		memset(buf, 0, buflen);
++	} else {
++		ret = BCME_BADARG;
++		goto exit;
++	}
++
++	ret = wldev_mkiovar(iovar_name, param, paramlen, buf, buflen);
++
++	if (!ret) {
++		ret = BCME_BUFTOOSHORT;
++		goto exit;
++	}
++	ret = wldev_ioctl_get(dev, WLC_GET_VAR, buf, buflen);
++exit:
++	if (buf_sync)
++		mutex_unlock(buf_sync);
++	return ret;
++}
++
++
++s32 wldev_iovar_setbuf(
++	struct net_device *dev, s8 *iovar_name,
++	void *param, s32 paramlen, void *buf, s32 buflen, struct mutex* buf_sync)
++{
++	s32 ret = 0;
++	s32 iovar_len;
++	if (buf_sync) {
++		mutex_lock(buf_sync);
++	}
++	iovar_len = wldev_mkiovar(iovar_name, param, paramlen, buf, buflen);
++	if (iovar_len > 0)
++		ret = wldev_ioctl_set(dev, WLC_SET_VAR, buf, iovar_len);
++	else
++		ret = BCME_BUFTOOSHORT;
++
++	if (buf_sync)
++		mutex_unlock(buf_sync);
++	return ret;
++}
++
++s32 wldev_iovar_setint(
++	struct net_device *dev, s8 *iovar, s32 val)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++
++	val = htod32(val);
++	memset(iovar_buf, 0, sizeof(iovar_buf));
++	return wldev_iovar_setbuf(dev, iovar, &val, sizeof(val), iovar_buf,
++		sizeof(iovar_buf), NULL);
++}
++
++
++s32 wldev_iovar_getint(
++	struct net_device *dev, s8 *iovar, s32 *pval)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	s32 err;
++
++	memset(iovar_buf, 0, sizeof(iovar_buf));
++	err = wldev_iovar_getbuf(dev, iovar, pval, sizeof(*pval), iovar_buf,
++		sizeof(iovar_buf), NULL);
++	if (err == 0)
++	{
++		memcpy(pval, iovar_buf, sizeof(*pval));
++		*pval = dtoh32(*pval);
++	}
++	return err;
++}
++
++/** Format a bsscfg indexed iovar buffer. The bsscfg index will be
++ *  taken care of in dhd_ioctl_entry. Internal use only, not exposed to
++ *  wl_iw, wl_cfg80211 and wl_cfgp2p
++ */
++s32 wldev_mkiovar_bsscfg(
++	const s8 *iovar_name, s8 *param, s32 paramlen,
++	s8 *iovar_buf, s32 buflen, s32 bssidx)
++{
++	const s8 *prefix = "bsscfg:";
++	s8 *p;
++	u32 prefixlen;
++	u32 namelen;
++	u32 iolen;
++
++	/* initialize buffer */
++	if (!iovar_buf || buflen == 0)
++		return BCME_BADARG;
++	memset(iovar_buf, 0, buflen);
++
++	if (bssidx == 0) {
++		return wldev_mkiovar(iovar_name, param, paramlen,
++			iovar_buf, buflen);
++	}
++
++	prefixlen = (u32) strlen(prefix); /* lengh of bsscfg prefix */
++	namelen = (u32) strlen(iovar_name) + 1; /* lengh of iovar  name + null */
++	iolen = prefixlen + namelen + sizeof(u32) + paramlen;
++
++	if (buflen < 0 || iolen > (u32)buflen)
++	{
++		WLDEV_ERROR(("%s: buffer is too short\n", __FUNCTION__));
++		return BCME_BUFTOOSHORT;
++	}
++
++	p = (s8 *)iovar_buf;
++
++	/* copy prefix, no null */
++	memcpy(p, prefix, prefixlen);
++	p += prefixlen;
++
++	/* copy iovar name including null */
++	memcpy(p, iovar_name, namelen);
++	p += namelen;
++
++	/* bss config index as first param */
++	bssidx = htod32(bssidx);
++	memcpy(p, &bssidx, sizeof(u32));
++	p += sizeof(u32);
++
++	/* parameter buffer follows */
++	if (paramlen)
++		memcpy(p, param, paramlen);
++
++	return iolen;
++
++}
++
++s32 wldev_iovar_getbuf_bsscfg(
++	struct net_device *dev, s8 *iovar_name,
++	void *param, s32 paramlen, void *buf, s32 buflen, s32 bsscfg_idx, struct mutex* buf_sync)
++{
++	s32 ret = 0;
++	if (buf_sync) {
++		mutex_lock(buf_sync);
++	}
++
++	wldev_mkiovar_bsscfg(iovar_name, param, paramlen, buf, buflen, bsscfg_idx);
++	ret = wldev_ioctl_get(dev, WLC_GET_VAR, buf, buflen);
++	if (buf_sync) {
++		mutex_unlock(buf_sync);
++	}
++	return ret;
++
++}
++
++s32 wldev_iovar_setbuf_bsscfg(
++	struct net_device *dev, s8 *iovar_name,
++	void *param, s32 paramlen, void *buf, s32 buflen, s32 bsscfg_idx, struct mutex* buf_sync)
++{
++	s32 ret = 0;
++	s32 iovar_len;
++	if (buf_sync) {
++		mutex_lock(buf_sync);
++	}
++	iovar_len = wldev_mkiovar_bsscfg(iovar_name, param, paramlen, buf, buflen, bsscfg_idx);
++	if (iovar_len > 0)
++		ret = wldev_ioctl_set(dev, WLC_SET_VAR, buf, iovar_len);
++	else {
++		ret = BCME_BUFTOOSHORT;
++	}
++
++	if (buf_sync) {
++		mutex_unlock(buf_sync);
++	}
++	return ret;
++}
++
++s32 wldev_iovar_setint_bsscfg(
++	struct net_device *dev, s8 *iovar, s32 val, s32 bssidx)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++
++	val = htod32(val);
++	memset(iovar_buf, 0, sizeof(iovar_buf));
++	return wldev_iovar_setbuf_bsscfg(dev, iovar, &val, sizeof(val), iovar_buf,
++		sizeof(iovar_buf), bssidx, NULL);
++}
++
++
++s32 wldev_iovar_getint_bsscfg(
++	struct net_device *dev, s8 *iovar, s32 *pval, s32 bssidx)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	s32 err;
++
++	memset(iovar_buf, 0, sizeof(iovar_buf));
++	err = wldev_iovar_getbuf_bsscfg(dev, iovar, pval, sizeof(*pval), iovar_buf,
++		sizeof(iovar_buf), bssidx, NULL);
++	if (err == 0)
++	{
++		memcpy(pval, iovar_buf, sizeof(*pval));
++		*pval = dtoh32(*pval);
++	}
++	return err;
++}
++
++int wldev_get_link_speed(
++	struct net_device *dev, int *plink_speed)
++{
++	int error;
++
++	if (!plink_speed)
++		return -ENOMEM;
++	*plink_speed = 0;
++	error = wldev_ioctl_get(dev, WLC_GET_RATE, plink_speed, sizeof(int));
++	if (unlikely(error))
++		return error;
++
++	/* Convert internal 500Kbps to Kbps */
++	*plink_speed *= 500;
++	return error;
++}
++
++int wldev_get_rssi(
++	struct net_device *dev, scb_val_t *scb_val)
++{
++	int error;
++
++	if (!scb_val)
++		return -ENOMEM;
++	memset(scb_val, 0, sizeof(scb_val_t));
++	error = wldev_ioctl_get(dev, WLC_GET_RSSI, scb_val, sizeof(scb_val_t));
++	if (unlikely(error))
++		return error;
++
++	return error;
++}
++
++int wldev_get_ssid(
++	struct net_device *dev, wlc_ssid_t *pssid)
++{
++	int error;
++
++	if (!pssid)
++		return -ENOMEM;
++	memset(pssid, 0, sizeof(wlc_ssid_t));
++	error = wldev_ioctl_get(dev, WLC_GET_SSID, pssid, sizeof(wlc_ssid_t));
++	if (unlikely(error))
++		return error;
++	pssid->SSID_len = dtoh32(pssid->SSID_len);
++	return error;
++}
++
++int wldev_get_band(
++	struct net_device *dev, uint *pband)
++{
++	int error;
++
++	*pband = 0;
++	error = wldev_ioctl_get(dev, WLC_GET_BAND, pband, sizeof(uint));
++	return error;
++}
++
++int wldev_set_band(
++	struct net_device *dev, uint band)
++{
++	int error = -1;
++
++	if ((band == WLC_BAND_AUTO) || (band == WLC_BAND_5G) || (band == WLC_BAND_2G)) {
++		error = wldev_ioctl_set(dev, WLC_SET_BAND, &band, sizeof(band));
++		if (!error)
++			dhd_bus_band_set(dev, band);
++	}
++	return error;
++}
++int wldev_get_datarate(struct net_device *dev, int *datarate)
++{
++	int error = 0;
++
++	error = wldev_ioctl_get(dev, WLC_GET_RATE, datarate, sizeof(int));
++	if (error) {
++		return -1;
++	} else {
++		*datarate = dtoh32(*datarate);
++	}
++
++	return error;
++}
++
++#ifdef WL_CFG80211
++extern chanspec_t
++wl_chspec_driver_to_host(chanspec_t chanspec);
++#define WL_EXTRA_BUF_MAX 2048
++int wldev_get_mode(
++	struct net_device *dev, uint8 *cap, uint8 caplen)
++{
++	int error = 0;
++	int chanspec = 0;
++	uint16 band = 0;
++	uint16 bandwidth = 0;
++	wl_bss_info_t *bss = NULL;
++	char* buf = NULL;
++
++	buf = kzalloc(WL_EXTRA_BUF_MAX, GFP_KERNEL);
++	if (!buf) {
++		WLDEV_ERROR(("%s:ENOMEM\n", __FUNCTION__));
++		return -ENOMEM;
++	}
++
++	*(u32*) buf = htod32(WL_EXTRA_BUF_MAX);
++	error = wldev_ioctl_get(dev, WLC_GET_BSS_INFO, (void*)buf, WL_EXTRA_BUF_MAX);
++	if (error) {
++		WLDEV_ERROR(("%s:failed:%d\n", __FUNCTION__, error));
++		kfree(buf);
++		buf = NULL;
++		return error;
++	}
++	bss = (struct  wl_bss_info *)(buf + 4);
++	chanspec = wl_chspec_driver_to_host(bss->chanspec);
++
++	band = chanspec & WL_CHANSPEC_BAND_MASK;
++	bandwidth = chanspec & WL_CHANSPEC_BW_MASK;
++
++	if (band == WL_CHANSPEC_BAND_2G) {
++		if (bss->n_cap)
++			strncpy(cap, "n", caplen);
++		else
++			strncpy(cap, "bg", caplen);
++	} else if (band == WL_CHANSPEC_BAND_5G) {
++		if (bandwidth == WL_CHANSPEC_BW_80)
++			strncpy(cap, "ac", caplen);
++		else if ((bandwidth == WL_CHANSPEC_BW_40) || (bandwidth == WL_CHANSPEC_BW_20)) {
++			if ((bss->nbss_cap & 0xf00) && (bss->n_cap))
++				strncpy(cap, "n|ac", caplen);
++			else if (bss->n_cap)
++				strncpy(cap, "n", caplen);
++			else if (bss->vht_cap)
++				strncpy(cap, "ac", caplen);
++			else
++				strncpy(cap, "a", caplen);
++		} else {
++			WLDEV_ERROR(("%s:Mode get failed\n", __FUNCTION__));
++			error = BCME_ERROR;
++		}
++
++	}
++	kfree(buf);
++	buf = NULL;
++	return error;
++}
++#endif
++
++int wldev_set_country(
++	struct net_device *dev, char *country_code, bool notify, bool user_enforced, int revinfo)
++{
++	int error = -1;
++	wl_country_t cspec = {{0}, 0, {0}};
++	wl_country_t cur_cspec = {{0}, 0, {0}};	/* current ccode */
++	scb_val_t scbval;
++#ifdef WL_CFG80211
++	struct wireless_dev *wdev = ndev_to_wdev(dev);
++	struct wiphy *wiphy = wdev->wiphy;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++#endif
++
++	if (!country_code)
++		return error;
++
++	bzero(&scbval, sizeof(scb_val_t));
++	error = wldev_iovar_getbuf(dev, "country", NULL, 0, &cur_cspec, sizeof(wl_country_t), NULL);
++	if (error < 0) {
++		WLDEV_ERROR(("%s: get country failed = %d\n", __FUNCTION__, error));
++		return error;
++	}
++
++	cspec.rev = revinfo;
++	memcpy(cspec.country_abbrev, country_code, WLC_CNTRY_BUF_SZ);
++	memcpy(cspec.ccode, country_code, WLC_CNTRY_BUF_SZ);
++	error = dhd_conf_map_country_list(dhd_get_pub(dev), &cspec);
++	if (error)
++		dhd_get_customized_country_code(dev, (char *)&cspec.country_abbrev, &cspec);
++
++	WLDEV_INFO(("%s: Current country %s rev %d\n",
++		__FUNCTION__, cur_cspec.ccode, cur_cspec.rev));
++
++	if ((error < 0) ||
++		dhd_force_country_change(dev) ||
++	    (strncmp(cspec.ccode, cur_cspec.ccode, WLC_CNTRY_BUF_SZ) != 0)) {
++
++		if ((user_enforced)
++#ifdef WL_CFG80211
++			&& (wl_get_drv_status(cfg, CONNECTED, dev))
++#endif
++		) {
++			bzero(&scbval, sizeof(scb_val_t));
++			error = wldev_ioctl_set(dev, WLC_DISASSOC,
++			                        &scbval, sizeof(scb_val_t));
++			if (error < 0) {
++				WLDEV_ERROR(("%s: set country failed due to Disassoc error %d\n",
++					__FUNCTION__, error));
++				return error;
++			}
++		}
++
++		error = dhd_conf_set_country(dhd_get_pub(dev), &cspec);
++		if (error < 0) {
++			WLDEV_ERROR(("%s: set country for %s as %s rev %d failed\n",
++				__FUNCTION__, country_code, cspec.ccode, cspec.rev));
++			return error;
++		}
++		dhd_conf_fix_country(dhd_get_pub(dev));
++		dhd_conf_get_country(dhd_get_pub(dev), &cspec);
++		dhd_bus_country_set(dev, &cspec, notify);
++		printf("%s: set country for %s as %s rev %d\n",
++			__FUNCTION__, country_code, cspec.ccode, cspec.rev);
++	}
++	return 0;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd/wldev_common.h b/module_drivers/drivers/net/wireless/bcmdhd/wldev_common.h
+new file mode 100644
+index 000000000..4aa039e36
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd/wldev_common.h
+@@ -0,0 +1,130 @@
++/*
++ * Common function shared by Linux WEXT, cfg80211 and p2p drivers
++ *
++ * Copyright (C) 1999-2017, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wldev_common.h 699163 2017-05-12 05:18:23Z $
++ */
++#ifndef __WLDEV_COMMON_H__
++#define __WLDEV_COMMON_H__
++
++#include <wlioctl.h>
++
++/* wl_dev_ioctl - get/set IOCTLs, will call net_device's do_ioctl (or
++ *  netdev_ops->ndo_do_ioctl in new kernels)
++ *  @dev: the net_device handle
++ */
++s32 wldev_ioctl(
++	struct net_device *dev, u32 cmd, void *arg, u32 len, u32 set);
++
++s32 wldev_ioctl_get(
++	struct net_device *dev, u32 cmd, void *arg, u32 len);
++
++s32 wldev_ioctl_set(
++	struct net_device *dev, u32 cmd, const void *arg, u32 len);
++
++/** Retrieve named IOVARs, this function calls wl_dev_ioctl with
++ *  WLC_GET_VAR IOCTL code
++ */
++s32 wldev_iovar_getbuf(
++	struct net_device *dev, s8 *iovar_name,
++	void *param, s32 paramlen, void *buf, s32 buflen, struct mutex* buf_sync);
++
++/** Set named IOVARs, this function calls wl_dev_ioctl with
++ *  WLC_SET_VAR IOCTL code
++ */
++s32 wldev_iovar_setbuf(
++	struct net_device *dev, s8 *iovar_name,
++	void *param, s32 paramlen, void *buf, s32 buflen, struct mutex* buf_sync);
++
++s32 wldev_iovar_setint(
++	struct net_device *dev, s8 *iovar, s32 val);
++
++s32 wldev_iovar_getint(
++	struct net_device *dev, s8 *iovar, s32 *pval);
++
++/** The following function can be implemented if there is a need for bsscfg
++ *  indexed IOVARs
++ */
++
++s32 wldev_mkiovar_bsscfg(
++	const s8 *iovar_name, s8 *param, s32 paramlen,
++	s8 *iovar_buf, s32 buflen, s32 bssidx);
++
++/** Retrieve named and bsscfg indexed IOVARs, this function calls wl_dev_ioctl with
++ *  WLC_GET_VAR IOCTL code
++ */
++s32 wldev_iovar_getbuf_bsscfg(
++	struct net_device *dev, s8 *iovar_name, void *param, s32 paramlen,
++	void *buf, s32 buflen, s32 bsscfg_idx, struct mutex* buf_sync);
++
++/** Set named and bsscfg indexed IOVARs, this function calls wl_dev_ioctl with
++ *  WLC_SET_VAR IOCTL code
++ */
++s32 wldev_iovar_setbuf_bsscfg(
++	struct net_device *dev, s8 *iovar_name, void *param, s32 paramlen,
++	void *buf, s32 buflen, s32 bsscfg_idx, struct mutex* buf_sync);
++
++s32 wldev_iovar_getint_bsscfg(
++	struct net_device *dev, s8 *iovar, s32 *pval, s32 bssidx);
++
++s32 wldev_iovar_setint_bsscfg(
++	struct net_device *dev, s8 *iovar, s32 val, s32 bssidx);
++
++extern int dhd_net_set_fw_path(struct net_device *dev, char *fw);
++extern int dhd_net_bus_suspend(struct net_device *dev);
++extern int dhd_net_bus_resume(struct net_device *dev, uint8 stage);
++extern int dhd_net_wifi_platform_set_power(struct net_device *dev, bool on,
++	unsigned long delay_msec);
++extern void dhd_get_customized_country_code(struct net_device *dev, char *country_iso_code,
++	wl_country_t *cspec);
++extern void dhd_bus_country_set(struct net_device *dev, wl_country_t *cspec, bool notify);
++extern bool dhd_force_country_change(struct net_device *dev);
++extern void dhd_bus_band_set(struct net_device *dev, uint band);
++extern int wldev_set_country(struct net_device *dev, char *country_code, bool notify,
++	bool user_enforced, int revinfo);
++extern int net_os_wake_lock(struct net_device *dev);
++extern int net_os_wake_unlock(struct net_device *dev);
++extern int net_os_wake_lock_timeout(struct net_device *dev);
++extern int net_os_wake_lock_timeout_enable(struct net_device *dev, int val);
++extern int net_os_set_dtim_skip(struct net_device *dev, int val);
++extern int net_os_set_suspend_disable(struct net_device *dev, int val);
++extern int net_os_set_suspend(struct net_device *dev, int val, int force);
++extern int net_os_set_max_dtim_enable(struct net_device *dev, int val);
++extern int wl_parse_ssid_list_tlv(char** list_str, wlc_ssid_ext_t* ssid,
++	int max, int *bytes_left);
++
++/* Get the link speed from dongle, speed is in kpbs */
++int wldev_get_link_speed(struct net_device *dev, int *plink_speed);
++
++int wldev_get_rssi(struct net_device *dev, scb_val_t *prssi);
++
++int wldev_get_ssid(struct net_device *dev, wlc_ssid_t *pssid);
++
++int wldev_get_band(struct net_device *dev, uint *pband);
++int wldev_get_mode(struct net_device *dev, uint8 *pband, uint8 caplen);
++int wldev_get_datarate(struct net_device *dev, int *datarate);
++int wldev_set_band(struct net_device *dev, uint band);
++
++#endif /* __WLDEV_COMMON_H__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/Kconfig b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/Kconfig
+new file mode 100644
+index 000000000..5ca19c41b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/Kconfig
+@@ -0,0 +1,68 @@
++config BCMDHD_1_363_125_17
++	tristate "Broadcom FullMAC wireless cards support ver:1.363.125.17"
++	help
++	  This module adds support for wireless adapters based on
++	  Broadcom FullMAC chipset.
++
++	  If you choose to build a module, it'll be called dhd. Say M if
++	  unsure.
++
++config BCMDHD_1_363_125_17_SDIO
++	bool "SDIO bus interface support"
++	depends on BCMDHD_1_363_125_17 && MMC
++
++config BCMDHD_1_363_125_17_PCIE
++	bool "PCIe bus interface support"
++	depends on BCMDHD_1_363_125_17 && PCI && !BCMDHD_1_363_125_17_SDIO
++
++config BCM4354
++	tristate "BCM4354 support"
++	depends on BCMDHD_1_363_125_17
++
++config BCM4356
++	tristate "BCM4356 support"
++	depends on BCMDHD_1_363_125_17
++	default n
++
++config BCMDHD_1_363_125_17_FW_PATH
++	depends on BCMDHD_1_363_125_17
++	string "Firmware path"
++	default "/system/vendor/firmware/fw_bcmdhd.bin"
++	help
++	  Path to the firmware file.
++
++config BCMDHD_1_363_125_17_NVRAM_PATH
++	depends on BCMDHD_1_363_125_17
++	string "NVRAM path"
++	default "/system/etc/wifi/bcmdhd.cal"
++	help
++	  Path to the calibration file.
++
++config BCMDHD_1_363_125_17_WEXT
++	bool "Enable WEXT support"
++	depends on BCMDHD_1_363_125_17 && CFG80211 = n
++	select WIRELESS_EXT
++	select WEXT_PRIV
++	help
++	  Enables WEXT support
++
++config DHD_USE_STATIC_BUF
++	bool "Enable memory preallocation"
++	depends on BCMDHD_1_363_125_17
++	default n
++	help
++	  Use memory preallocated in platform
++
++config DHD_USE_SCHED_SCAN
++	bool "Use CFG80211 sched scan"
++	depends on BCMDHD_1_363_125_17 && CFG80211
++	default n
++	help
++	  Use CFG80211 sched scan
++
++config DHD_SET_RANDOM_MAC_VAL
++hex "Vendor OUI"
++depends on BCMDHD_1_363_125_17
++default 0x001A11
++ help
++Set vendor OUI for SoftAP
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/Makefile b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/Makefile
+new file mode 100644
+index 000000000..c5e53cd4b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/Makefile
+@@ -0,0 +1,323 @@
++# cywdhd
++#################
++# Usage and porting guide for this Makefile
++#################
++# 1 Default to the module external build, that is, no need to copy the driver into the kernel source tree
++#  Build with:
++#       make KDIR=/path/to/your/kernel
++# 2 Default to x86 build: Build the x86 driver without any modification outside of kernel
++# 3 Just change the 'DHD_PLATFORM=imx' and the IMx OOB version can work!
++# 4 Copy DHD_PLATFORM=imx as the start point and create your own name
++
++#####################
++# SDIO Basic feature
++#####################
++MODULE_NAME := bcmdhd_1_363_125_17
++DHDCFLAGS += -Wall -Wstrict-prototypes -Dlinux -DLINUX -DBCMDRIVER            \
++	-DBCMDONGLEHOST -DUNRELEASEDCHIP -DBCMDMA32 -DBCMFILEIMAGE            \
++	-DSHOW_EVENTS -DBCMDBG -DWLP2P                                        \
++	-DWIFI_ACT_FRAME -DARP_OFFLOAD_SUPPORT                                \
++	-DKEEP_ALIVE -DCSCAN -DPKT_FILTER_SUPPORT                             \
++	-DEMBEDDED_PLATFORM -DPNO_SUPPORT                                     \
++	-DDHD_DONOT_FORWARD_BCMEVENT_AS_NETWORK_PKT                           \
++	-DCUSTOMER_HW2
++#	-Idrivers/net/wireless/bcmdhd_1_363_125_17 -Idrivers/net/wireless/bcmdhd_1_363_125_17/include
++
++#################
++# Common feature
++#################
++DHDCFLAGS += -DWL_CFG80211
++# Print out kernel panic point of file and line info when assertion happened
++DHDCFLAGS += -DBCMASSERT_LOG
++
++# keepalive
++DHDCFLAGS += -DCUSTOM_KEEP_ALIVE_SETTING=28000
++
++DHDCFLAGS += -DVSDB
++
++# Fix __DATE__ & __TIME__ error on gcc version 4.9 or later
++GCCVERSION = $(shell $(CC) -dumpversion | cut -f1-2 -d.)
++ifeq ($(shell expr $(GCCVERSION) \>= 4.9),1)
++  DHDCFLAGS += -Wno-error=date-time
++endif
++
++# For p2p connection issue
++DHDCFLAGS += -DWL_SCB_TIMEOUT=10
++
++# TDLS enable
++DHDCFLAGS += -DWLTDLS
++# For TDLS tear down inactive time 40 sec
++DHDCFLAGS += -DCUSTOM_TDLS_IDLE_MODE_SETTING=40000
++# for TDLS RSSI HIGH for establishing TDLS link
++DHDCFLAGS += -DCUSTOM_TDLS_RSSI_THRESHOLD_HIGH=-60
++# for TDLS RSSI HIGH for tearing down TDLS link
++DHDCFLAGS += -DCUSTOM_TDLS_RSSI_THRESHOLD_LOW=-70
++
++# Roaming/
++DHDCFLAGS += -DROAM_AP_ENV_DETECTION
++DHDCFLAGS += -DROAM_ENABLE -DROAM_CHANNEL_CACHE -DROAM_API
++DHDCFLAGS += -DENABLE_FW_ROAM_SUSPEND
++# Roaming trigger
++DHDCFLAGS += -DCUSTOM_ROAM_TRIGGER_SETTING=-75
++DHDCFLAGS += -DCUSTOM_ROAM_DELTA_SETTING=10
++# Voice Enterprise
++DHDCFLAGS += -DWLFBT
++# Set PM 2 always regardless suspend/resume
++DHDCFLAGS += -DSUPPORT_PM2_ONLY
++
++# For special PNO Event keep wake lock for 10sec
++DHDCFLAGS += -DCUSTOM_PNO_EVENT_LOCK_xTIME=10
++DHDCFLAGS += -DMIRACAST_AMPDU_SIZE=8
++
++#Gscan
++# DHDCFLAGS += -DGSCAN_SUPPORT
++#RTT
++DHDCFLAGS += -DRTT_SUPPORT -DRTT_DEBUG
++
++
++#Link Statistics
++DHDCFLAGS += -DLINKSTAT_SUPPORT
++
++# Early suspend
++DHDCFLAGS += -DDHD_USE_EARLYSUSPEND
++
++# For Scan result patch
++DHDCFLAGS += -DESCAN_RESULT_PATCH
++
++# For Static Buffer
++ifeq ($(CONFIG_DHD_USE_STATIC_BUF),y)
++  DHDCFLAGS += -DENHANCED_STATIC_BUF
++  DHDCFLAGS += -DSTATIC_WL_PRIV_STRUCT
++endif
++ifneq ($(CONFIG_DHD_USE_SCHED_SCAN),)
++DHDCFLAGS += -DWL_SCHED_SCAN
++endif
++
++# Ioctl timeout 5000ms
++DHDCFLAGS += -DIOCTL_RESP_TIMEOUT=5000
++
++# Prevent rx thread monopolize
++DHDCFLAGS += -DWAIT_DEQUEUE
++
++# idle count
++DHDCFLAGS += -DDHD_USE_IDLECOUNT
++
++# SKB TAILPAD to avoid out of boundary memory access
++DHDCFLAGS += -DDHDENABLE_TAILPAD
++
++# Wi-Fi Direct
++DHDCFLAGS += -DWL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++DHDCFLAGS += -DWL_CFG80211_STA_EVENT
++DHDCFLAGS += -DWL_IFACE_COMB_NUM_CHANNELS
++DHDCFLAGS += -DWL_ENABLE_P2P_IF
++#SCAN time
++DHDCFLAGS += -DCUSTOM_SET_SHORT_DWELL_TIME
++DHDCFLAGS += -DCUSTOM_FORCE_NODFS_FLAG
++
++
++# SoftAP
++DHDCFLAGS += -DSET_RANDOM_MAC_SOFTAP
++DHDCFLAGS += -DWL_CFG80211_ACL
++
++##########################
++# driver type
++# m: module type driver
++# y: built-in type driver
++##########################
++DRIVER_TYPE ?= m
++
++#########################
++# Chip dependent feature
++#########################
++
++DHDCFLAGS += -DUSE_WL_TXBF
++# DHDCFLAGS += -DUSE_WL_FRAMEBURST
++DHDCFLAGS += -DCUSTOM_DPC_CPUCORE=0
++DHDCFLAGS += -DPROP_TXSTATUS_VSDB
++DHDCFLAGS += -DCUSTOM_PSPRETEND_THR=30
++# New Features
++DHDCFLAGS += -DWL11U
++DHDCFLAGS += -DMFP
++# The LPC would have the Tx 5G tput drop around 10Mbps but saving powers
++# DHDCFLAGS += -DDHD_ENABLE_LPC
++DHDCFLAGS += -DCUSTOM_COUNTRY_CODE
++
++### Platform dependent START
++#DHD_PLATFORM ?= linux
++DHD_PLATFORM ?= ingenic
++ifeq ($(DHD_PLATFORM), ingenic)
++  CONFIG_BCMDHD_1_363_125_17_SDIO = y
++  ## We only add here for the flags in our generic code
++  DHDCFLAGS += -DANDROID_SDIO_RESET
++  DHDCFLAGS += -DOOB_INTR_ONLY -DHW_OOB
++  DHDCFLAGS += -DCUSTOM_SDIO_F2_BLKSIZE=128
++  DHDCFLAGS += -DDHD_OF_SUPPORT -DCUSTOMER_OOB
++  DHDCFLAGS += -DLOAD_DHD_WITH_FW_ALIVE
++  FW_ALIVE = 1
++endif
++
++
++ifeq ($(DHD_PLATFORM), imx_android)
++  CONFIG_BCMDHD_1_363_125_17_SDIO = y
++# Config DTS support
++  DHDCFLAGS += -DCONFIG_DTS
++# for iMX platform
++  DHDCFLAGS += -DCUSTOMER_IMX
++  DHDCFLAGS += -DOOB_INTR_ONLY -DHW_OOB
++  DHDCFLAGS += -DANDROID_SDIO_RESET
++# The flags only worked for supported host
++# Remove it if you found the dhdsdio_rxglom erros
++  DHDCFLAGS += -DCUSTOM_RXCHAIN=1
++endif
++
++ifeq ($(DHD_PLATFORM), imx)
++  CONFIG_BCMDHD_1_363_125_17_SDIO = y
++# Config DTS support
++  DHDCFLAGS += -DCONFIG_DTS
++# for iMX platform
++  DHDCFLAGS += -DCUSTOMER_IMX
++  DHDCFLAGS += -DOOB_INTR_ONLY -DHW_OOB
++# The flags only worked for supported host
++# Remove it if you found the dhdsdio_rxglom erros
++  DHDCFLAGS += -DCUSTOM_RXCHAIN=1
++endif
++
++ifeq ($(CONFIG_BCMDHD_1_363_125_17_PCIE), y)
++  CONFIG_BCMDHD_1_363_125_17_PCIE = y
++else
++ifeq ($(CONFIG_BCMDHD_1_363_125_17_USB), y)
++  CONFIG_BCMDHD_1_363_125_17_USB = y
++else
++  CONFIG_BCMDHD_1_363_125_17_SDIO = y
++endif
++endif
++
++### Platform dependent END
++
++ifneq ($(CONFIG_BCMDHD_1_363_125_17_SDIO),)
++  DHDCFLAGS += -DBDC -DTOE -DDHD_BCMEVENTS -DMMC_SDIO_ABORT
++  DHDCFLAGS += -DBCMSDIO -DBCMLXSDMMC -DUSE_SDIOFIFO_IOVAR
++  DHDCFLAGS += -DPROP_TXSTATUS
++  DHDCFLAGS += -DCUSTOM_AMPDU_MPDU=16
++  DHDCFLAGS += -DCUSTOM_AMPDU_BA_WSIZE=64
++# tput enhancement
++  DHDCFLAGS += -DCUSTOM_GLOM_SETTING=8
++  DHDCFLAGS += -DBCMSDIOH_TXGLOM -DCUSTOM_TXGLOM=1
++  DHDCFLAGS += -DDHDTCPACK_SUPPRESS
++  DHDCFLAGS += -DRXFRAME_THREAD
++  DHDCFLAGS += -DCUSTOM_MAX_TXGLOM_SIZE=31
++  DHDCFLAGS += -DMAX_HDR_READ=128
++  DHDCFLAGS += -DDHD_FIRSTREAD=128
++  # bcn_timeout
++  DHDCFLAGS += -DCUSTOM_BCN_TIMEOUT=5
++ endif
++
++ifneq ($(CONFIG_BCMDHD_1_363_125_17_PCIE),)
++  DHDCFLAGS += -DPCIE_FULL_DONGLE -DBCMPCIE -DCUSTOM_DPC_PRIO_SETTING=-1
++# tput enhancement
++  DHDCFLAGS += -DCUSTOM_AMPDU_BA_WSIZE=64
++  DHDCFLAGS += -DCUSTOM_AMPDU_MPDU=32
++  DHDCFLAGS += -DCUSTOM_AMPDU_RELEASE=16
++  DHDCFLAGS += -DPROP_TXSTATUS_VSDB
++# Disable watchdog thread
++  DHDCFLAGS += -DCUSTOM_DHD_WATCHDOG_MS=0
++  DHDCFLAGS += -DMAX_CNTL_TX_TIMEOUT=1
++  DHDCFLAGS += -DSUPPORT_LINKDOWN_RECOVERY
++endif
++
++ifneq ($(CONFIG_BCMDHD_1_363_125_17_USB),)
++  DHDCFLAGS += -DBDC -DTOE
++  DHDCFLAGS += -DDHD_BCMEVENTS -DSHOW_EVENTS -DSHOW_LOGTRACE
++  DHDCFLAGS += -DBCMDHDUSB -DBCMDBUS -DBCMTRXV2 -DDBUS_USB_LOOPBACK
++  DHDCFLAGS += -DPROP_TXSTATUS
++  DHDCFLAGS += -DLIMIT_BORROW
++endif
++
++ifeq ($(CONFIG_DHD_USE_STATIC_BUF),y)
++  DHDCFLAGS += -DDHD_USE_STATIC_IOCTLBUF
++endif
++# Print 802.1X packets
++DHDCFLAGS += -DDHD_8021X_DUMP
++# Print DHCP packets
++DHDCFLAGS += -DDHD_DHCP_DUMP
++
++
++#EXTRA_LDFLAGS += --strip-debug
++
++ifeq ($(DRIVER_TYPE),y)
++  DHDCFLAGS += -DENABLE_INSMOD_NO_FW_LOAD
++  DHDCFLAGS += -DUSE_LATE_INITCALL_SYNC
++endif
++
++## Attend to fix the suspend/resume -16 error issue, refer to SWDHD-409
++DHDCFLAGS += -DSUSPEND16
++
++
++## Flags merged from Linux build
++DHDCFLAGS += -DCUSTOMER_IPCAM -DWL11ULB -DWL_NAN -DWL_SUPPORT_AUTO_CHANNEL -DWL_VIRTUAL_APSTA
++
++## Flags that may depends on Linux kernel versions
++DHDCFLAGS += -DTSQ_MULTIPLIER=10
++
++## Flags maybe useful but disable it
++
++# The WLFC AC queue credit borrow
++# DHDCFLAGS += -DLIMIT_BORROW
++
++# Advanced IBSS features
++# DHDCFLAGS += -DWLAIBSS -DWLAIBSS_PS
++
++# p2P service discovery offload
++# DHDCFLAGS += -DWL_SDO
++
++EXTRA_CFLAGS += $(DHDCFLAGS) -DDHD_DEBUG
++EXTRA_CFLAGS += -DSRCBASE=\"$(src)\"
++EXTRA_CFLAGS += -I$(srctree)/$(src)/include/ -I$(srctree)/$(src)/
++#EXTRA_CFLAGS += -I$(srctree)/$(src)/include/ -I$(srctree)/$(src)/
++#KBUILD_CFLAGS += -I$(LINUXDIR)/include -I$(shell pwd)
++
++DHDOFILES := dhd_pno.o dhd_common.o dhd_ip.o dhd_custom_gpio.o \
++	dhd_linux.o dhd_linux_sched.o dhd_cfg80211.o dhd_linux_wq.o aiutils.o bcmevent.o \
++	bcmutils.o bcmwifi_channels.o hndpmu.o linux_osl.o sbutils.o siutils.o \
++	wl_android.o wl_cfg80211.o wl_cfgp2p.o wl_cfg_btcoex.o wldev_common.o wl_linux_mon.o  \
++	dhd_linux_platdev.o dhd_pno.o dhd_rtt.o dhd_linux_wq.o wl_cfg_btcoex.o \
++        hnd_pktq.o hnd_pktpool.o wl_cfgvendor.o dhd_debug_linux.o bcmxtlv.o dhd_debug.o bcm_app_utils.o \
++	wl_cfgnan.o
++
++ifeq ($(FW_ALIVE), 1)
++  DHDCFLAGS += -DLOAD_DHD_WITH_FW_ALIVE
++  DHDOFILES += dhd_chip_info.o
++endif
++
++
++ifneq ($(CONFIG_BCMDHD_1_363_125_17_SDIO),)
++  DHDOFILES += bcmsdh.o bcmsdh_linux.o bcmsdh_sdmmc.o bcmsdh_sdmmc_linux.o
++  DHDOFILES += dhd_cdc.o dhd_wlfc.o dhd_sdio.o
++endif
++
++ifneq ($(CONFIG_BCMDHD_1_363_125_17_PCIE),)
++  DHDOFILES += dhd_pcie.o dhd_pcie_linux.o dhd_msgbuf.o dhd_flowring.o
++  DHDOFILES += pcie_core.o
++endif
++
++ifneq ($(CONFIG_BCMDHD_1_363_125_17_USB),)
++  DHDOFILES += dbus.o dbus_usb.o dbus_usb_linux.o
++  DHDOFILES += dhd_cdc.o dhd_wlfc.o
++endif
++
++#cywdhd-objs := $(DHDOFILES)
++obj-$(CONFIG_BCMDHD_1_363_125_17) += $(MODULE_NAME).o
++$(MODULE_NAME)-objs += $(DHDOFILES)
++obj-$(DRIVER_TYPE)   += $(MODULE_NAME).o
++
++all:
++	@echo "$(MAKE) --no-print-directory -C $(KDIR) SUBDIRS=$(CURDIR) modules"
++	@$(MAKE) --no-print-directory -C $(KDIR) SUBDIRS=$(CURDIR) modules
++
++clean:
++	rm -rf *.o *.ko *.mod.c *~ .*.cmd *.o.cmd .*.o.cmd \
++	Module.symvers modules.order .tmp_versions modules.builtin
++
++install:
++	@$(MAKE) --no-print-directory -C $(KDIR) \
++		SUBDIRS=$(CURDIR) modules_install
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/aiutils.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/aiutils.c
+new file mode 100644
+index 000000000..b5961a568
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/aiutils.c
+@@ -0,0 +1,1298 @@
++/*
++ * Misc utility routines for accessing chip-specific features
++ * of the SiliconBackplane-based Broadcom chips.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: aiutils.c 708487 2018-10-31 05:33:14Z $
++ */
++#include <bcm_cfg.h>
++#include <typedefs.h>
++#include <bcmdefs.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <siutils.h>
++#include <hndsoc.h>
++#include <sbchipc.h>
++#include <pcicfg.h>
++
++#include "siutils_priv.h"
++
++
++#ifdef LOAD_DHD_WITH_FW_ALIVE
++#include <bcmdevs.h>
++#include <dhd_chip_info.h>
++#endif
++
++#define BCM47162_DMP() (0)
++#define BCM5357_DMP() (0)
++#define BCM53573_DMP() (0)
++#define BCM4707_DMP() (0)
++#define PMU_DMP() (0)
++#define GCI_DMP() (0)
++#define remap_coreid(sih, coreid)	(coreid)
++#define remap_corerev(sih, corerev)	(corerev)
++
++/* EROM parsing */
++
++static uint32
++get_erom_ent(si_t *sih, uint32 **eromptr, uint32 mask, uint32 match)
++{
++	uint32 ent;
++	uint inv = 0, nom = 0;
++	uint32 size = 0;
++
++	while (TRUE) {
++		ent = R_REG(si_osh(sih), *eromptr);
++		(*eromptr)++;
++
++		if (mask == 0)
++			break;
++
++		if ((ent & ER_VALID) == 0) {
++			inv++;
++			continue;
++		}
++
++		if (ent == (ER_END | ER_VALID))
++			break;
++
++		if ((ent & mask) == match)
++			break;
++
++		/* escape condition related EROM size if it has invalid values */
++		size += sizeof(*eromptr);
++		if (size >= ER_SZ_MAX) {
++			SI_ERROR(("Failed to find end of EROM marker\n"));
++			break;
++		}
++
++		nom++;
++	}
++
++	SI_VMSG(("%s: Returning ent 0x%08x\n", __FUNCTION__, ent));
++	if (inv + nom) {
++		SI_VMSG(("  after %d invalid and %d non-matching entries\n", inv, nom));
++	}
++	return ent;
++}
++
++static uint32
++get_asd(si_t *sih, uint32 **eromptr, uint sp, uint ad, uint st, uint32 *addrl, uint32 *addrh,
++        uint32 *sizel, uint32 *sizeh)
++{
++	uint32 asd, sz, szd;
++
++	asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
++	if (((asd & ER_TAG1) != ER_ADD) ||
++	    (((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
++	    ((asd & AD_ST_MASK) != st)) {
++		/* This is not what we want, "push" it back */
++		(*eromptr)--;
++		return 0;
++	}
++	*addrl = asd & AD_ADDR_MASK;
++	if (asd & AD_AG32)
++		*addrh = get_erom_ent(sih, eromptr, 0, 0);
++	else
++		*addrh = 0;
++	*sizeh = 0;
++	sz = asd & AD_SZ_MASK;
++	if (sz == AD_SZ_SZD) {
++		szd = get_erom_ent(sih, eromptr, 0, 0);
++		*sizel = szd & SD_SZ_MASK;
++		if (szd & SD_SG32)
++			*sizeh = get_erom_ent(sih, eromptr, 0, 0);
++	} else
++		*sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
++
++	SI_VMSG(("  SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
++	        sp, ad, st, *sizeh, *sizel, *addrh, *addrl));
++
++	return asd;
++}
++
++static void
++ai_hwfixup(si_info_t *sii)
++{
++}
++
++
++/* parse the enumeration rom to identify all cores */
++void
++ai_scan(si_t *sih, void *regs, uint devid)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	chipcregs_t *cc = (chipcregs_t *)regs;
++	uint32 erombase, *eromptr, *eromlim;
++
++#ifdef LOAD_DHD_WITH_FW_ALIVE
++	if(alive == FW_ALIVE_MAGIC) {
++		switch(card_dev) {
++			case BCM43430_CHIP_ID:
++				sii->numcores = ai_core_43430;
++				sii->oob_router = oob_router_43430;
++				memcpy(&cores_info->coreid, &bcm43430_coreid, sii->numcores * 4);
++				memcpy(&cores_info->coresba, &bcm43430_coresba, sii->numcores * 4);
++				memcpy(&cores_info->coresba_size, &bcm43430_coresba_size, sii->numcores * 4);
++				memcpy(&cores_info->wrapba, &bcm43430_wrapba, sii->numcores * 4);
++				memcpy(&cores_info->cia, &bcm43430_cia, sii->numcores * 4);
++				if(card_rev == 2) {
++					memcpy(&cores_info->cib, &bcm43436_cib, sii->numcores * 4);
++				} else {
++					memcpy(&cores_info->cib, &bcm43430_cib, sii->numcores * 4);
++				}
++				break;
++
++			default:
++				break;
++
++		}
++
++		return;
++	}
++#endif
++
++	erombase = R_REG(sii->osh, &cc->eromptr);
++
++	switch (BUSTYPE(sih->bustype)) {
++	case SI_BUS:
++		eromptr = (uint32 *)REG_MAP(erombase, SI_CORE_SIZE);
++		break;
++
++	case PCI_BUS:
++		/* Set wrappers address */
++		sii->curwrap = (void *)((uintptr)regs + SI_CORE_SIZE);
++
++		/* Now point the window at the erom */
++		OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, erombase);
++		eromptr = regs;
++		break;
++
++#ifdef BCMSDIO
++	case SPI_BUS:
++	case SDIO_BUS:
++		eromptr = (uint32 *)(uintptr)erombase;
++		break;
++#endif	/* BCMSDIO */
++
++	case PCMCIA_BUS:
++	default:
++		SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n", sih->bustype));
++		ASSERT(0);
++		return;
++	}
++	eromlim = eromptr + (ER_REMAPCONTROL / sizeof(uint32));
++
++	SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n",
++	         regs, erombase, eromptr, eromlim));
++	while (eromptr < eromlim) {
++		uint32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
++		uint32 mpd, asd, addrl, addrh, sizel, sizeh;
++		uint i, j, idx;
++		bool br;
++
++		br = FALSE;
++
++		/* Grok a component */
++		cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
++		if (cia == (ER_END | ER_VALID)) {
++			SI_VMSG(("Found END of erom after %d cores\n", sii->numcores));
++			ai_hwfixup(sii);
++			return;
++		}
++
++		cib = get_erom_ent(sih, &eromptr, 0, 0);
++
++		if ((cib & ER_TAG) != ER_CI) {
++			SI_ERROR(("CIA not followed by CIB\n"));
++			goto error;
++		}
++
++		cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
++		mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
++		crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
++		nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
++		nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
++		nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
++		nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
++
++#ifdef BCMDBG_SI
++		SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, "
++		         "nsw = %d, nmp = %d & nsp = %d\n",
++		         mfg, cid, crev, eromptr - 1, nmw, nsw, nmp, nsp));
++#else
++		BCM_REFERENCE(crev);
++#endif
++
++		if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) || (nsp == 0))
++			continue;
++		if ((nmw + nsw == 0)) {
++			/* A component which is not a core */
++			if (cid == OOB_ROUTER_CORE_ID) {
++				asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
++					&addrl, &addrh, &sizel, &sizeh);
++				if (asd != 0) {
++					sii->oob_router = addrl;
++				}
++			}
++			if (cid != GMAC_COMMON_4706_CORE_ID && cid != NS_CCB_CORE_ID &&
++				cid != PMU_CORE_ID && cid != GCI_CORE_ID)
++				continue;
++		}
++
++		idx = sii->numcores;
++
++		cores_info->cia[idx] = cia;
++		cores_info->cib[idx] = cib;
++		cores_info->coreid[idx] = remap_coreid(sih, cid);
++
++		for (i = 0; i < nmp; i++) {
++			mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
++			if ((mpd & ER_TAG) != ER_MP) {
++				SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
++				goto error;
++			}
++			SI_VMSG(("  Master port %d, mp: %d id: %d\n", i,
++			         (mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
++			         (mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
++		}
++
++		/* First Slave Address Descriptor should be port 0:
++		 * the main register space for the core
++		 */
++		asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh, &sizel, &sizeh);
++		if (asd == 0) {
++			do {
++			/* Try again to see if it is a bridge */
++			asd = get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl, &addrh,
++			              &sizel, &sizeh);
++			if (asd != 0)
++				br = TRUE;
++			else {
++					if (br == TRUE) {
++						break;
++					}
++					else if ((addrh != 0) || (sizeh != 0) ||
++						(sizel != SI_CORE_SIZE)) {
++						SI_ERROR(("addrh = 0x%x\t sizeh = 0x%x\t size1 ="
++							"0x%x\n", addrh, sizeh, sizel));
++						SI_ERROR(("First Slave ASD for"
++							"core 0x%04x malformed "
++							"(0x%08x)\n", cid, asd));
++						goto error;
++					}
++				}
++			} while (1);
++		}
++		cores_info->coresba[idx] = addrl;
++		cores_info->coresba_size[idx] = sizel;
++		/* Get any more ASDs in port 0 */
++		j = 1;
++		do {
++			asd = get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl, &addrh,
++			              &sizel, &sizeh);
++			if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
++				cores_info->coresba2[idx] = addrl;
++				cores_info->coresba2_size[idx] = sizel;
++			}
++			j++;
++		} while (asd != 0);
++
++		/* Go through the ASDs for other slave ports */
++		for (i = 1; i < nsp; i++) {
++			j = 0;
++			do {
++				asd = get_asd(sih, &eromptr, i, j, AD_ST_SLAVE, &addrl, &addrh,
++				              &sizel, &sizeh);
++
++				if (asd == 0)
++					break;
++				j++;
++			} while (1);
++			if (j == 0) {
++				SI_ERROR((" SP %d has no address descriptors\n", i));
++				goto error;
++			}
++		}
++
++		/* Now get master wrappers */
++		for (i = 0; i < nmw; i++) {
++			asd = get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl, &addrh,
++			              &sizel, &sizeh);
++			if (asd == 0) {
++				SI_ERROR(("Missing descriptor for MW %d\n", i));
++				goto error;
++			}
++			if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
++				SI_ERROR(("Master wrapper %d is not 4KB\n", i));
++				goto error;
++			}
++			if (i == 0)
++				cores_info->wrapba[idx] = addrl;
++			else if (i == 1)
++				cores_info->wrapba2[idx] = addrl;
++		}
++
++		/* And finally slave wrappers */
++		for (i = 0; i < nsw; i++) {
++			uint fwp = (nsp == 1) ? 0 : 1;
++			asd = get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP, &addrl, &addrh,
++			              &sizel, &sizeh);
++
++			/* cache APB bridge wrapper address for set/clear timeout */
++			if ((mfg == MFGID_ARM) && (cid == APB_BRIDGE_ID)) {
++				ASSERT(sii->num_br < SI_MAXBR);
++				sii->br_wrapba[sii->num_br++] = addrl;
++			}
++			if (asd == 0) {
++				SI_ERROR(("Missing descriptor for SW %d\n", i));
++				goto error;
++			}
++			if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
++				SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
++				goto error;
++			}
++			if ((nmw == 0) && (i == 0))
++				cores_info->wrapba[idx] = addrl;
++			else if ((nmw == 0) && (i == 1))
++				cores_info->wrapba2[idx] = addrl;
++		}
++
++
++		/* Don't record bridges */
++		if (br)
++			continue;
++
++		/* Done with core */
++		sii->numcores++;
++	}
++
++	SI_ERROR(("Reached end of erom without finding END"));
++
++error:
++	sii->numcores = 0;
++	return;
++}
++
++#define AI_SETCOREIDX_MAPSIZE(coreid) \
++	(((coreid) == NS_CCB_CORE_ID) ? 15 * SI_CORE_SIZE : SI_CORE_SIZE)
++
++/* This function changes the logical "focus" to the indicated core.
++ * Return the current core's virtual address.
++ */
++static void *
++_ai_setcoreidx(si_t *sih, uint coreidx, uint use_wrap2)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint32 addr, wrap, wrap2;
++	void *regs;
++
++	if (coreidx >= MIN(sii->numcores, SI_MAXCORES))
++		return (NULL);
++
++	addr = cores_info->coresba[coreidx];
++	wrap = cores_info->wrapba[coreidx];
++	wrap2 = cores_info->wrapba2[coreidx];
++
++	/*
++	 * If the user has provided an interrupt mask enabled function,
++	 * then assert interrupts are disabled before switching the core.
++	 */
++	ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg));
++
++	switch (BUSTYPE(sih->bustype)) {
++	case SI_BUS:
++		/* map new one */
++		if (!cores_info->regs[coreidx]) {
++			cores_info->regs[coreidx] = REG_MAP(addr,
++				AI_SETCOREIDX_MAPSIZE(cores_info->coreid[coreidx]));
++			ASSERT(GOODREGS(cores_info->regs[coreidx]));
++		}
++		sii->curmap = regs = cores_info->regs[coreidx];
++		if (!cores_info->wrappers[coreidx] && (wrap != 0)) {
++			cores_info->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
++			ASSERT(GOODREGS(cores_info->wrappers[coreidx]));
++		}
++		if (!cores_info->wrappers2[coreidx] && (wrap2 != 0)) {
++			cores_info->wrappers2[coreidx] = REG_MAP(wrap2, SI_CORE_SIZE);
++			ASSERT(GOODREGS(cores_info->wrappers2[coreidx]));
++		}
++		if (use_wrap2)
++			sii->curwrap = cores_info->wrappers2[coreidx];
++		else
++			sii->curwrap = cores_info->wrappers[coreidx];
++		break;
++
++	case PCI_BUS:
++		/* point bar0 window */
++		OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, addr);
++		regs = sii->curmap;
++		/* point bar0 2nd 4KB window to the primary wrapper */
++		if (use_wrap2)
++			wrap = wrap2;
++		if (PCIE_GEN2(sii))
++			OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_WIN2, 4, wrap);
++		else
++			OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, wrap);
++		break;
++
++#ifdef BCMSDIO
++	case SPI_BUS:
++	case SDIO_BUS:
++		sii->curmap = regs = (void *)((uintptr)addr);
++		if (use_wrap2)
++			sii->curwrap = (void *)((uintptr)wrap2);
++		else
++			sii->curwrap = (void *)((uintptr)wrap);
++		break;
++#endif	/* BCMSDIO */
++
++	case PCMCIA_BUS:
++	default:
++		ASSERT(0);
++		regs = NULL;
++		break;
++	}
++
++	sii->curmap = regs;
++	sii->curidx = coreidx;
++
++	return regs;
++}
++
++void *
++ai_setcoreidx(si_t *sih, uint coreidx)
++{
++	return _ai_setcoreidx(sih, coreidx, 0);
++}
++
++void *
++ai_setcoreidx_2ndwrap(si_t *sih, uint coreidx)
++{
++	return _ai_setcoreidx(sih, coreidx, 1);
++}
++
++void
++ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	chipcregs_t *cc = NULL;
++	uint32 erombase, *eromptr, *eromlim;
++	uint i, j, cidx;
++	uint32 cia, cib, nmp, nsp;
++	uint32 asd, addrl, addrh, sizel, sizeh;
++
++	for (i = 0; i < sii->numcores; i++) {
++		if (cores_info->coreid[i] == CC_CORE_ID) {
++			cc = (chipcregs_t *)cores_info->regs[i];
++			break;
++		}
++	}
++	if (cc == NULL)
++		goto error;
++
++	erombase = R_REG(sii->osh, &cc->eromptr);
++	eromptr = (uint32 *)REG_MAP(erombase, SI_CORE_SIZE);
++	eromlim = eromptr + (ER_REMAPCONTROL / sizeof(uint32));
++
++	cidx = sii->curidx;
++	cia = cores_info->cia[cidx];
++	cib = cores_info->cib[cidx];
++
++	nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
++	nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
++
++	/* scan for cores */
++	while (eromptr < eromlim) {
++		if ((get_erom_ent(sih, &eromptr, ER_TAG, ER_CI) == cia) &&
++			(get_erom_ent(sih, &eromptr, 0, 0) == cib)) {
++			break;
++		}
++	}
++
++	/* skip master ports */
++	for (i = 0; i < nmp; i++)
++		get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
++
++	/* Skip ASDs in port 0 */
++	asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh, &sizel, &sizeh);
++	if (asd == 0) {
++		/* Try again to see if it is a bridge */
++		asd = get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl, &addrh,
++		              &sizel, &sizeh);
++	}
++
++	j = 1;
++	do {
++		asd = get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl, &addrh,
++		              &sizel, &sizeh);
++		j++;
++	} while (asd != 0);
++
++	/* Go through the ASDs for other slave ports */
++	for (i = 1; i < nsp; i++) {
++		j = 0;
++		do {
++			asd = get_asd(sih, &eromptr, i, j, AD_ST_SLAVE, &addrl, &addrh,
++				&sizel, &sizeh);
++			if (asd == 0)
++				break;
++
++			if (!asidx--) {
++				*addr = addrl;
++				*size = sizel;
++				return;
++			}
++			j++;
++		} while (1);
++
++		if (j == 0) {
++			SI_ERROR((" SP %d has no address descriptors\n", i));
++			break;
++		}
++	}
++
++error:
++	*size = 0;
++	return;
++}
++
++/* Return the number of address spaces in current core */
++int
++ai_numaddrspaces(si_t *sih)
++{
++	return 2;
++}
++
++/* Return the address of the nth address space in the current core */
++uint32
++ai_addrspace(si_t *sih, uint asidx)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint cidx;
++
++	cidx = sii->curidx;
++
++	if (asidx == 0)
++		return cores_info->coresba[cidx];
++	else if (asidx == 1)
++		return cores_info->coresba2[cidx];
++	else {
++		SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n",
++		          __FUNCTION__, asidx));
++		return 0;
++	}
++}
++
++/* Return the size of the nth address space in the current core */
++uint32
++ai_addrspacesize(si_t *sih, uint asidx)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint cidx;
++
++	cidx = sii->curidx;
++
++	if (asidx == 0)
++		return cores_info->coresba_size[cidx];
++	else if (asidx == 1)
++		return cores_info->coresba2_size[cidx];
++	else {
++		SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n",
++		          __FUNCTION__, asidx));
++		return 0;
++	}
++}
++
++uint
++ai_flag(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++
++	if (BCM47162_DMP()) {
++		SI_ERROR(("%s: Attempting to read MIPS DMP registers on 47162a0", __FUNCTION__));
++		return sii->curidx;
++	}
++	if (BCM5357_DMP()) {
++		SI_ERROR(("%s: Attempting to read USB20H DMP registers on 5357b0\n", __FUNCTION__));
++		return sii->curidx;
++	}
++	if (BCM4707_DMP()) {
++		SI_ERROR(("%s: Attempting to read CHIPCOMMONB DMP registers on 4707\n",
++			__FUNCTION__));
++		return sii->curidx;
++	}
++	if (BCM53573_DMP()) {
++		SI_ERROR(("%s: Attempting to read DMP registers on 53573\n", __FUNCTION__));
++		return sii->curidx;
++	}
++#ifdef REROUTE_OOBINT
++	if (PMU_DMP()) {
++		SI_ERROR(("%s: Attempting to read PMU DMP registers\n",
++			__FUNCTION__));
++		return PMU_OOB_BIT;
++	}
++#else
++	if (PMU_DMP()) {
++		uint idx, flag;
++		idx = sii->curidx;
++		ai_setcoreidx(sih, SI_CC_IDX);
++		flag = ai_flag_alt(sih);
++		ai_setcoreidx(sih, idx);
++		return flag;
++	}
++#endif /* REROUTE_OOBINT */
++
++	ai = sii->curwrap;
++	ASSERT(ai != NULL);
++
++	return (R_REG(sii->osh, &ai->oobselouta30) & 0x1f);
++}
++
++uint
++ai_flag_alt(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++
++	if (BCM47162_DMP()) {
++		SI_ERROR(("%s: Attempting to read MIPS DMP registers on 47162a0", __FUNCTION__));
++		return sii->curidx;
++	}
++	if (BCM5357_DMP()) {
++		SI_ERROR(("%s: Attempting to read USB20H DMP registers on 5357b0\n", __FUNCTION__));
++		return sii->curidx;
++	}
++	if (BCM4707_DMP()) {
++		SI_ERROR(("%s: Attempting to read CHIPCOMMONB DMP registers on 4707\n",
++			__FUNCTION__));
++		return sii->curidx;
++	}
++#ifdef REROUTE_OOBINT
++	if (PMU_DMP()) {
++		SI_ERROR(("%s: Attempting to read PMU DMP registers\n",
++			__FUNCTION__));
++		return PMU_OOB_BIT;
++	}
++#endif /* REROUTE_OOBINT */
++
++	ai = sii->curwrap;
++
++	return ((R_REG(sii->osh, &ai->oobselouta30) >> AI_OOBSEL_1_SHIFT) & AI_OOBSEL_MASK);
++}
++
++void
++ai_setint(si_t *sih, int siflag)
++{
++}
++
++uint
++ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint32 *map = (uint32 *) sii->curwrap;
++
++	if (mask || val) {
++		uint32 w = R_REG(sii->osh, map+(offset/4));
++		w &= ~mask;
++		w |= val;
++		W_REG(sii->osh, map+(offset/4), w);
++	}
++
++	return (R_REG(sii->osh, map+(offset/4)));
++}
++
++uint
++ai_corevendor(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint32 cia;
++
++	cia = cores_info->cia[sii->curidx];
++	return ((cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT);
++}
++
++uint
++ai_corerev(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint32 cib;
++
++
++	cib = cores_info->cib[sii->curidx];
++	return remap_corerev(sih, (cib & CIB_REV_MASK) >> CIB_REV_SHIFT);
++}
++
++bool
++ai_iscoreup(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++
++	ai = sii->curwrap;
++
++	return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) == SICF_CLOCK_EN) &&
++	        ((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
++}
++
++/*
++ * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
++ * switch back to the original core, and return the new value.
++ *
++ * When using the silicon backplane, no fiddling with interrupts or core switches is needed.
++ *
++ * Also, when using pci/pcie, we can optimize away the core switching for pci registers
++ * and (on newer pci cores) chipcommon registers.
++ */
++uint
++ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
++{
++	uint origidx = 0;
++	uint32 *r = NULL;
++	uint w;
++	uint intr_val = 0;
++	bool fast = FALSE;
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++
++	ASSERT(GOODIDX(coreidx));
++	ASSERT(regoff < SI_CORE_SIZE);
++	ASSERT((val & ~mask) == 0);
++
++	if (coreidx >= SI_MAXCORES)
++		return 0;
++
++	if (BUSTYPE(sih->bustype) == SI_BUS) {
++		/* If internal bus, we can always get at everything */
++		fast = TRUE;
++		/* map if does not exist */
++		if (!cores_info->regs[coreidx]) {
++			cores_info->regs[coreidx] = REG_MAP(cores_info->coresba[coreidx],
++			                            SI_CORE_SIZE);
++			ASSERT(GOODREGS(cores_info->regs[coreidx]));
++		}
++		r = (uint32 *)((uchar *)cores_info->regs[coreidx] + regoff);
++	} else if (BUSTYPE(sih->bustype) == PCI_BUS) {
++		/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
++
++		if ((cores_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
++			/* Chipc registers are mapped at 12KB */
++
++			fast = TRUE;
++			r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
++		} else if (sii->pub.buscoreidx == coreidx) {
++			/* pci registers are at either in the last 2KB of an 8KB window
++			 * or, in pcie and pci rev 13 at 8KB
++			 */
++			fast = TRUE;
++			if (SI_FAST(sii))
++				r = (uint32 *)((char *)sii->curmap +
++				               PCI_16KB0_PCIREGS_OFFSET + regoff);
++			else
++				r = (uint32 *)((char *)sii->curmap +
++				               ((regoff >= SBCONFIGOFF) ?
++				                PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
++				               regoff);
++		}
++	}
++
++	if (!fast) {
++		INTR_OFF(sii, intr_val);
++
++		/* save current core index */
++		origidx = si_coreidx(&sii->pub);
++
++		/* switch core */
++		r = (uint32*) ((uchar*) ai_setcoreidx(&sii->pub, coreidx) + regoff);
++	}
++	ASSERT(r != NULL);
++
++	/* mask and set */
++	if (mask || val) {
++		w = (R_REG(sii->osh, r) & ~mask) | val;
++		W_REG(sii->osh, r, w);
++	}
++
++	/* readback */
++	w = R_REG(sii->osh, r);
++
++	if (!fast) {
++		/* restore core index */
++		if (origidx != coreidx)
++			ai_setcoreidx(&sii->pub, origidx);
++
++		INTR_RESTORE(sii, intr_val);
++	}
++
++	return (w);
++}
++
++/*
++ * If there is no need for fiddling with interrupts or core switches (typically silicon
++ * back plane registers, pci registers and chipcommon registers), this function
++ * returns the register offset on this core to a mapped address. This address can
++ * be used for W_REG/R_REG directly.
++ *
++ * For accessing registers that would need a core switch, this function will return
++ * NULL.
++ */
++uint32 *
++ai_corereg_addr(si_t *sih, uint coreidx, uint regoff)
++{
++	uint32 *r = NULL;
++	bool fast = FALSE;
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++
++	ASSERT(GOODIDX(coreidx));
++	ASSERT(regoff < SI_CORE_SIZE);
++
++	if (coreidx >= SI_MAXCORES)
++		return 0;
++
++	if (BUSTYPE(sih->bustype) == SI_BUS) {
++		/* If internal bus, we can always get at everything */
++		fast = TRUE;
++		/* map if does not exist */
++		if (!cores_info->regs[coreidx]) {
++			cores_info->regs[coreidx] = REG_MAP(cores_info->coresba[coreidx],
++			                            SI_CORE_SIZE);
++			ASSERT(GOODREGS(cores_info->regs[coreidx]));
++		}
++		r = (uint32 *)((uchar *)cores_info->regs[coreidx] + regoff);
++	} else if (BUSTYPE(sih->bustype) == PCI_BUS) {
++		/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
++
++		if ((cores_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
++			/* Chipc registers are mapped at 12KB */
++
++			fast = TRUE;
++			r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
++		} else if (sii->pub.buscoreidx == coreidx) {
++			/* pci registers are at either in the last 2KB of an 8KB window
++			 * or, in pcie and pci rev 13 at 8KB
++			 */
++			fast = TRUE;
++			if (SI_FAST(sii))
++				r = (uint32 *)((char *)sii->curmap +
++				               PCI_16KB0_PCIREGS_OFFSET + regoff);
++			else
++				r = (uint32 *)((char *)sii->curmap +
++				               ((regoff >= SBCONFIGOFF) ?
++				                PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
++				               regoff);
++		}
++	}
++
++	if (!fast) {
++		ASSERT(sii->curidx == coreidx);
++		r = (uint32*) ((uchar*)sii->curmap + regoff);
++	}
++
++	return (r);
++}
++
++void
++ai_core_disable(si_t *sih, uint32 bits)
++{
++	si_info_t *sii = SI_INFO(sih);
++	volatile uint32 dummy;
++	uint32 status;
++	aidmp_t *ai;
++
++
++	ASSERT(GOODREGS(sii->curwrap));
++	ai = sii->curwrap;
++
++	/* if core is already in reset, just return */
++	if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET)
++		return;
++
++	/* ensure there are no pending backplane operations */
++	SPINWAIT(((status = R_REG(sii->osh, &ai->resetstatus)) != 0), 300);
++
++	/* if pending backplane ops still, try waiting longer */
++	if (status != 0) {
++		/* 300usecs was sufficient to allow backplane ops to clear for big hammer */
++		/* during driver load we may need more time */
++		SPINWAIT(((status = R_REG(sii->osh, &ai->resetstatus)) != 0), 10000);
++		/* if still pending ops, continue on and try disable anyway */
++		/* this is in big hammer path, so don't call wl_reinit in this case... */
++	}
++
++	W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
++	dummy = R_REG(sii->osh, &ai->resetctrl);
++	BCM_REFERENCE(dummy);
++	OSL_DELAY(1);
++
++	W_REG(sii->osh, &ai->ioctrl, bits);
++	dummy = R_REG(sii->osh, &ai->ioctrl);
++	BCM_REFERENCE(dummy);
++	OSL_DELAY(10);
++}
++
++/* reset and re-enable a core
++ * inputs:
++ * bits - core specific bits that are set during and after reset sequence
++ * resetbits - core specific bits that are set only during reset sequence
++ */
++static void
++_ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
++{
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++	volatile uint32 dummy;
++	uint loop_counter = 10;
++
++	ASSERT(GOODREGS(sii->curwrap));
++	ai = sii->curwrap;
++
++	/* ensure there are no pending backplane operations */
++	SPINWAIT(((dummy = R_REG(sii->osh, &ai->resetstatus)) != 0), 300);
++
++
++	/* put core into reset state */
++	W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
++	OSL_DELAY(10);
++
++	/* ensure there are no pending backplane operations */
++	SPINWAIT((R_REG(sii->osh, &ai->resetstatus) != 0), 300);
++
++	W_REG(sii->osh, &ai->ioctrl, (bits | resetbits | SICF_FGC | SICF_CLOCK_EN));
++	dummy = R_REG(sii->osh, &ai->ioctrl);
++	BCM_REFERENCE(dummy);
++
++	/* ensure there are no pending backplane operations */
++	SPINWAIT(((dummy = R_REG(sii->osh, &ai->resetstatus)) != 0), 300);
++
++
++	while (R_REG(sii->osh, &ai->resetctrl) != 0 && --loop_counter != 0) {
++		/* ensure there are no pending backplane operations */
++		SPINWAIT(((dummy = R_REG(sii->osh, &ai->resetstatus)) != 0), 300);
++
++
++		/* take core out of reset */
++		W_REG(sii->osh, &ai->resetctrl, 0);
++
++		/* ensure there are no pending backplane operations */
++		SPINWAIT((R_REG(sii->osh, &ai->resetstatus) != 0), 300);
++	}
++
++
++	W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN));
++	dummy = R_REG(sii->osh, &ai->ioctrl);
++	BCM_REFERENCE(dummy);
++	OSL_DELAY(1);
++}
++
++void
++ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint idx = sii->curidx;
++
++	if (cores_info->wrapba2[idx] != 0) {
++		ai_setcoreidx_2ndwrap(sih, idx);
++		_ai_core_reset(sih, bits, resetbits);
++		ai_setcoreidx(sih, idx);
++	}
++
++	_ai_core_reset(sih, bits, resetbits);
++}
++
++void
++ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)
++{
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++	uint32 w;
++
++
++	if (BCM47162_DMP()) {
++		SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
++		          __FUNCTION__));
++		return;
++	}
++	if (BCM5357_DMP()) {
++		SI_ERROR(("%s: Accessing USB20H DMP register (ioctrl) on 5357\n",
++		          __FUNCTION__));
++		return;
++	}
++	if (BCM4707_DMP()) {
++		SI_ERROR(("%s: Accessing CHIPCOMMONB DMP register (ioctrl) on 4707\n",
++			__FUNCTION__));
++		return;
++	}
++	if (PMU_DMP()) {
++		SI_ERROR(("%s: Accessing PMU DMP register (ioctrl)\n",
++			__FUNCTION__));
++		return;
++	}
++
++	ASSERT(GOODREGS(sii->curwrap));
++	ai = sii->curwrap;
++
++	ASSERT((val & ~mask) == 0);
++
++	if (mask || val) {
++		w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
++		W_REG(sii->osh, &ai->ioctrl, w);
++	}
++}
++
++uint32
++ai_core_cflags(si_t *sih, uint32 mask, uint32 val)
++{
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++	uint32 w;
++
++	if (BCM47162_DMP()) {
++		SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
++		          __FUNCTION__));
++		return 0;
++	}
++	if (BCM5357_DMP()) {
++		SI_ERROR(("%s: Accessing USB20H DMP register (ioctrl) on 5357\n",
++		          __FUNCTION__));
++		return 0;
++	}
++	if (BCM4707_DMP()) {
++		SI_ERROR(("%s: Accessing CHIPCOMMONB DMP register (ioctrl) on 4707\n",
++			__FUNCTION__));
++		return 0;
++	}
++
++	if (PMU_DMP()) {
++		SI_ERROR(("%s: Accessing PMU DMP register (ioctrl)\n",
++			__FUNCTION__));
++		return 0;
++	}
++	ASSERT(GOODREGS(sii->curwrap));
++	ai = sii->curwrap;
++
++	ASSERT((val & ~mask) == 0);
++
++	if (mask || val) {
++		w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
++		W_REG(sii->osh, &ai->ioctrl, w);
++	}
++
++	return R_REG(sii->osh, &ai->ioctrl);
++}
++
++uint32
++ai_core_sflags(si_t *sih, uint32 mask, uint32 val)
++{
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++	uint32 w;
++
++	if (BCM47162_DMP()) {
++		SI_ERROR(("%s: Accessing MIPS DMP register (iostatus) on 47162a0",
++		          __FUNCTION__));
++		return 0;
++	}
++	if (BCM5357_DMP()) {
++		SI_ERROR(("%s: Accessing USB20H DMP register (iostatus) on 5357\n",
++		          __FUNCTION__));
++		return 0;
++	}
++	if (BCM4707_DMP()) {
++		SI_ERROR(("%s: Accessing CHIPCOMMONB DMP register (ioctrl) on 4707\n",
++			__FUNCTION__));
++		return 0;
++	}
++	if (PMU_DMP()) {
++		SI_ERROR(("%s: Accessing PMU DMP register (ioctrl)\n",
++			__FUNCTION__));
++		return 0;
++	}
++
++	ASSERT(GOODREGS(sii->curwrap));
++	ai = sii->curwrap;
++
++	ASSERT((val & ~mask) == 0);
++	ASSERT((mask & ~SISF_CORE_BITS) == 0);
++
++	if (mask || val) {
++		w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) | val);
++		W_REG(sii->osh, &ai->iostatus, w);
++	}
++
++	return R_REG(sii->osh, &ai->iostatus);
++}
++
++#if defined(BCMDBG_PHYDUMP)
++/* print interesting aidmp registers */
++void
++ai_dumpregs(si_t *sih, struct bcmstrbuf *b)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	osl_t *osh;
++	aidmp_t *ai;
++	uint i;
++
++	osh = sii->osh;
++
++	for (i = 0; i < sii->numcores; i++) {
++		si_setcoreidx(&sii->pub, i);
++		ai = sii->curwrap;
++
++		bcm_bprintf(b, "core 0x%x: \n", cores_info->coreid[i]);
++		if (BCM47162_DMP()) {
++			bcm_bprintf(b, "Skipping mips74k in 47162a0\n");
++			continue;
++		}
++		if (BCM5357_DMP()) {
++			bcm_bprintf(b, "Skipping usb20h in 5357\n");
++			continue;
++		}
++		if (BCM4707_DMP()) {
++			bcm_bprintf(b, "Skipping chipcommonb in 4707\n");
++			continue;
++		}
++
++		if (PMU_DMP()) {
++			bcm_bprintf(b, "Skipping pmu core\n");
++			continue;
++		}
++
++		bcm_bprintf(b, "ioctrlset 0x%x ioctrlclear 0x%x ioctrl 0x%x iostatus 0x%x"
++			    "ioctrlwidth 0x%x iostatuswidth 0x%x\n"
++			    "resetctrl 0x%x resetstatus 0x%x resetreadid 0x%x resetwriteid 0x%x\n"
++			    "errlogctrl 0x%x errlogdone 0x%x errlogstatus 0x%x"
++			    "errlogaddrlo 0x%x errlogaddrhi 0x%x\n"
++			    "errlogid 0x%x errloguser 0x%x errlogflags 0x%x\n"
++			    "intstatus 0x%x config 0x%x itcr 0x%x\n",
++			    R_REG(osh, &ai->ioctrlset),
++			    R_REG(osh, &ai->ioctrlclear),
++			    R_REG(osh, &ai->ioctrl),
++			    R_REG(osh, &ai->iostatus),
++			    R_REG(osh, &ai->ioctrlwidth),
++			    R_REG(osh, &ai->iostatuswidth),
++			    R_REG(osh, &ai->resetctrl),
++			    R_REG(osh, &ai->resetstatus),
++			    R_REG(osh, &ai->resetreadid),
++			    R_REG(osh, &ai->resetwriteid),
++			    R_REG(osh, &ai->errlogctrl),
++			    R_REG(osh, &ai->errlogdone),
++			    R_REG(osh, &ai->errlogstatus),
++			    R_REG(osh, &ai->errlogaddrlo),
++			    R_REG(osh, &ai->errlogaddrhi),
++			    R_REG(osh, &ai->errlogid),
++			    R_REG(osh, &ai->errloguser),
++			    R_REG(osh, &ai->errlogflags),
++			    R_REG(osh, &ai->intstatus),
++			    R_REG(osh, &ai->config),
++			    R_REG(osh, &ai->itcr));
++	}
++}
++#endif	
++
++
++void
++ai_enable_backplane_timeouts(si_t *sih)
++{
++#ifdef AXI_TIMEOUTS
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++	int i;
++
++	for (i = 0; i < sii->num_br; ++i) {
++		ai = (aidmp_t *) sii->br_wrapba[i];
++		W_REG(sii->osh, &ai->errlogctrl, (1 << AIELC_TO_ENAB_SHIFT) |
++		      ((AXI_TO_VAL << AIELC_TO_EXP_SHIFT) & AIELC_TO_EXP_MASK));
++	}
++#endif /* AXI_TIMEOUTS */
++}
++
++void
++ai_clear_backplane_to(si_t *sih)
++{
++#ifdef AXI_TIMEOUTS
++	si_info_t *sii = SI_INFO(sih);
++	aidmp_t *ai;
++	int i;
++	uint32 errlogstatus;
++
++	for (i = 0; i < sii->num_br; ++i) {
++		ai = (aidmp_t *) sii->br_wrapba[i];
++		/* check for backplane timeout & clear backplane hang */
++		errlogstatus = R_REG(sii->osh, &ai->errlogstatus);
++
++		if ((errlogstatus & AIELS_TIMEOUT_MASK) != 0) {
++			/* set ErrDone to clear the condition */
++			W_REG(sii->osh, &ai->errlogdone, AIELD_ERRDONE_MASK);
++
++			/* SPINWAIT on errlogstatus timeout status bits */
++			while (R_REG(sii->osh, &ai->errlogstatus) & AIELS_TIMEOUT_MASK)
++				;
++
++			/* only reset APB Bridge on timeout (not slave error, or dec error) */
++			switch (errlogstatus & AIELS_TIMEOUT_MASK) {
++			case 0x1:
++				printf("AXI slave error");
++				break;
++			case 0x2:
++				/* reset APB Bridge */
++				OR_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
++				/* sync write */
++				(void)R_REG(sii->osh, &ai->resetctrl);
++				/* clear Reset bit */
++				AND_REG(sii->osh, &ai->resetctrl, ~(AIRC_RESET));
++				/* sync write */
++				(void)R_REG(sii->osh, &ai->resetctrl);
++				printf("AXI timeout");
++				break;
++			case 0x3:
++				printf("AXI decode error");
++				break;
++			default:
++				;	/* should be impossible */
++			}
++			printf("; APB Bridge %d\n", i);
++			printf("\t errlog: lo 0x%08x, hi 0x%08x, id 0x%08x, flags 0x%08x",
++				R_REG(sii->osh, &ai->errlogaddrlo),
++				R_REG(sii->osh, &ai->errlogaddrhi),
++				R_REG(sii->osh, &ai->errlogid),
++				R_REG(sii->osh, &ai->errlogflags));
++			printf(", status 0x%08x\n", errlogstatus);
++		}
++	}
++#endif /* AXI_TIMEOUTS */
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcm_app_utils.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcm_app_utils.c
+new file mode 100644
+index 000000000..df84002f0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcm_app_utils.c
+@@ -0,0 +1,1016 @@
++/*
++ * Misc utility routines used by kernel or app-level.
++ * Contents are wifi-specific, used by any kernel or app-level
++ * software that might want wifi things as it grows.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcm_app_utils.c 599883 2015-11-17 04:55:57Z $
++ */
++
++#include <typedefs.h>
++
++#ifdef BCMDRIVER
++#include <osl.h>
++#define strtoul(nptr, endptr, base) bcm_strtoul((nptr), (endptr), (base))
++#define tolower(c) (bcm_isupper((c)) ? ((c) + 'a' - 'A') : (c))
++#else /* BCMDRIVER */
++#include <stdio.h>
++#include <string.h>
++#include <stdlib.h>
++#include <ctype.h>
++#ifndef ASSERT
++#define ASSERT(exp)
++#endif
++#endif /* BCMDRIVER */
++#include <bcmwifi_channels.h>
++
++#if defined(WIN32) && (defined(BCMDLL) || defined(WLMDLL))
++#include <bcmstdlib.h>	/* For wl/exe/GNUmakefile.brcm_wlu and GNUmakefile.wlm_dll */
++#endif
++
++#include <bcmutils.h>
++#include <wlioctl.h>
++#include <wlioctl_utils.h>
++
++#ifndef BCMDRIVER
++/*	Take an array of measurments representing a single channel over time and return
++	a summary. Currently implemented as a simple average but could easily evolve
++	into more cpomplex alogrithms.
++*/
++cca_congest_channel_req_t *
++cca_per_chan_summary(cca_congest_channel_req_t *input, cca_congest_channel_req_t *avg, bool percent)
++{
++	int sec;
++	cca_congest_t totals;
++
++	totals.duration  = 0;
++	totals.congest_ibss  = 0;
++	totals.congest_obss  = 0;
++	totals.interference  = 0;
++	avg->num_secs = 0;
++
++	for (sec = 0; sec < input->num_secs; sec++) {
++		if (input->secs[sec].duration) {
++			totals.duration += input->secs[sec].duration;
++			totals.congest_ibss += input->secs[sec].congest_ibss;
++			totals.congest_obss += input->secs[sec].congest_obss;
++			totals.interference += input->secs[sec].interference;
++			avg->num_secs++;
++		}
++	}
++	avg->chanspec = input->chanspec;
++
++	if (!avg->num_secs || !totals.duration)
++		return (avg);
++
++	if (percent) {
++		avg->secs[0].duration = totals.duration / avg->num_secs;
++		avg->secs[0].congest_ibss = totals.congest_ibss * 100/totals.duration;
++		avg->secs[0].congest_obss = totals.congest_obss * 100/totals.duration;
++		avg->secs[0].interference = totals.interference * 100/totals.duration;
++	} else {
++		avg->secs[0].duration = totals.duration / avg->num_secs;
++		avg->secs[0].congest_ibss = totals.congest_ibss / avg->num_secs;
++		avg->secs[0].congest_obss = totals.congest_obss / avg->num_secs;
++		avg->secs[0].interference = totals.interference / avg->num_secs;
++	}
++
++	return (avg);
++}
++
++static void
++cca_info(uint8 *bitmap, int num_bits, int *left, int *bit_pos)
++{
++	int i;
++	for (*left = 0, i = 0; i < num_bits; i++) {
++		if (isset(bitmap, i)) {
++			(*left)++;
++			*bit_pos = i;
++		}
++	}
++}
++
++static uint8
++spec_to_chan(chanspec_t chspec)
++{
++	uint8 center_ch, edge, primary, sb;
++
++	center_ch = CHSPEC_CHANNEL(chspec);
++
++	if (CHSPEC_IS20(chspec)) {
++		return center_ch;
++	} else {
++		/* the lower edge of the wide channel is half the bw from
++		 * the center channel.
++		 */
++		if (CHSPEC_IS40(chspec)) {
++			edge = center_ch - CH_20MHZ_APART;
++		} else {
++			/* must be 80MHz (until we support more) */
++			ASSERT(CHSPEC_IS80(chspec));
++			edge = center_ch - CH_40MHZ_APART;
++		}
++
++		/* find the channel number of the lowest 20MHz primary channel */
++		primary = edge + CH_10MHZ_APART;
++
++		/* select the actual subband */
++		sb = (chspec & WL_CHANSPEC_CTL_SB_MASK) >> WL_CHANSPEC_CTL_SB_SHIFT;
++		primary = primary + sb * CH_20MHZ_APART;
++
++		return primary;
++	}
++}
++
++/*
++	Take an array of measumrements representing summaries of different channels.
++	Return a recomended channel.
++	Interference is evil, get rid of that first.
++	Then hunt for lowest Other bss traffic.
++	Don't forget that channels with low duration times may not have accurate readings.
++	For the moment, do not overwrite input array.
++*/
++int
++cca_analyze(cca_congest_channel_req_t *input[], int num_chans, uint flags, chanspec_t *answer)
++{
++	uint8 *bitmap = NULL;	/* 38 Max channels needs 5 bytes  = 40 */
++	int i, left, winner, ret_val = 0;
++	uint32 min_obss = 1 << 30;
++	uint bitmap_sz;
++
++	bitmap_sz = CEIL(num_chans, NBBY);
++	bitmap = (uint8 *)malloc(bitmap_sz);
++	if (bitmap == NULL) {
++		printf("unable to allocate memory\n");
++		return BCME_NOMEM;
++	}
++
++	memset(bitmap, 0, bitmap_sz);
++	/* Initially, all channels are up for consideration */
++	for (i = 0; i < num_chans; i++) {
++		if (input[i]->chanspec)
++			setbit(bitmap, i);
++	}
++	cca_info(bitmap, num_chans, &left, &i);
++	if (!left) {
++		ret_val = CCA_ERRNO_TOO_FEW;
++		goto f_exit;
++	}
++
++	/* Filter for 2.4 GHz Band */
++	if (flags & CCA_FLAG_2G_ONLY) {
++		for (i = 0; i < num_chans; i++) {
++			if (!CHSPEC_IS2G(input[i]->chanspec))
++				clrbit(bitmap, i);
++		}
++	}
++	cca_info(bitmap, num_chans, &left, &i);
++	if (!left) {
++		ret_val = CCA_ERRNO_BAND;
++		goto f_exit;
++	}
++
++	/* Filter for 5 GHz Band */
++	if (flags & CCA_FLAG_5G_ONLY) {
++		for (i = 0; i < num_chans; i++) {
++			if (!CHSPEC_IS5G(input[i]->chanspec))
++				clrbit(bitmap, i);
++		}
++	}
++	cca_info(bitmap, num_chans, &left, &i);
++	if (!left) {
++		ret_val = CCA_ERRNO_BAND;
++		goto f_exit;
++	}
++
++	/* Filter for Duration */
++	if (!(flags & CCA_FLAG_IGNORE_DURATION)) {
++		for (i = 0; i < num_chans; i++) {
++			if (input[i]->secs[0].duration < CCA_THRESH_MILLI)
++				clrbit(bitmap, i);
++		}
++	}
++	cca_info(bitmap, num_chans, &left, &i);
++	if (!left) {
++		ret_val = CCA_ERRNO_DURATION;
++		goto f_exit;
++	}
++
++	/* Filter for 1 6 11 on 2.4 Band */
++	if (flags &  CCA_FLAGS_PREFER_1_6_11) {
++		int tmp_channel = spec_to_chan(input[i]->chanspec);
++		int is2g = CHSPEC_IS2G(input[i]->chanspec);
++		for (i = 0; i < num_chans; i++) {
++			if (is2g && tmp_channel != 1 && tmp_channel != 6 && tmp_channel != 11)
++				clrbit(bitmap, i);
++		}
++	}
++	cca_info(bitmap, num_chans, &left, &i);
++	if (!left) {
++		ret_val = CCA_ERRNO_PREF_CHAN;
++		goto f_exit;
++	}
++
++	/* Toss high interference interference */
++	if (!(flags & CCA_FLAG_IGNORE_INTERFER)) {
++		for (i = 0; i < num_chans; i++) {
++			if (input[i]->secs[0].interference > CCA_THRESH_INTERFERE)
++				clrbit(bitmap, i);
++		}
++		cca_info(bitmap, num_chans, &left, &i);
++		if (!left) {
++			ret_val = CCA_ERRNO_INTERFER;
++			goto f_exit;
++		}
++	}
++
++	/* Now find lowest obss */
++	winner = 0;
++	for (i = 0; i < num_chans; i++) {
++		if (isset(bitmap, i) && input[i]->secs[0].congest_obss < min_obss) {
++			winner = i;
++			min_obss = input[i]->secs[0].congest_obss;
++		}
++	}
++	*answer = input[winner]->chanspec;
++	f_exit:
++	free(bitmap);	/* free the allocated memory for bitmap */
++	return ret_val;
++}
++#endif /* !BCMDRIVER */
++
++/* offset of cntmember by sizeof(uint32) from the first cnt variable, txframe. */
++#define IDX_IN_WL_CNT_VER_6_T(cntmember)		\
++	((OFFSETOF(wl_cnt_ver_6_t, cntmember) - OFFSETOF(wl_cnt_ver_6_t, txframe)) / sizeof(uint32))
++
++#define IDX_IN_WL_CNT_VER_11_T(cntmember)		\
++	((OFFSETOF(wl_cnt_ver_11_t, cntmember) - OFFSETOF(wl_cnt_ver_11_t, txframe))	\
++	/ sizeof(uint32))
++
++/* Exclude version and length fields */
++#define NUM_OF_CNT_IN_WL_CNT_VER_6_T	\
++	((sizeof(wl_cnt_ver_6_t) - 2 * sizeof(uint16)) / sizeof(uint32))
++/* Exclude macstat cnt variables. wl_cnt_ver_6_t only has 62 macstat cnt variables. */
++#define NUM_OF_WLCCNT_IN_WL_CNT_VER_6_T			\
++	(NUM_OF_CNT_IN_WL_CNT_VER_6_T - (WL_CNT_MCST_VAR_NUM - 2))
++
++/* Exclude version and length fields */
++#define NUM_OF_CNT_IN_WL_CNT_VER_11_T	\
++	((sizeof(wl_cnt_ver_11_t) - 2 * sizeof(uint16)) / sizeof(uint32))
++/* Exclude 64 macstat cnt variables. */
++#define NUM_OF_WLCCNT_IN_WL_CNT_VER_11_T		\
++	(NUM_OF_CNT_IN_WL_CNT_VER_11_T - WL_CNT_MCST_VAR_NUM)
++
++/* Index conversion table from wl_cnt_ver_6_t to wl_cnt_wlc_t */
++static const uint8 wlcntver6t_to_wlcntwlct[NUM_OF_WLCCNT_IN_WL_CNT_VER_6_T] = {
++	IDX_IN_WL_CNT_VER_6_T(txframe),
++	IDX_IN_WL_CNT_VER_6_T(txbyte),
++	IDX_IN_WL_CNT_VER_6_T(txretrans),
++	IDX_IN_WL_CNT_VER_6_T(txerror),
++	IDX_IN_WL_CNT_VER_6_T(txctl),
++	IDX_IN_WL_CNT_VER_6_T(txprshort),
++	IDX_IN_WL_CNT_VER_6_T(txserr),
++	IDX_IN_WL_CNT_VER_6_T(txnobuf),
++	IDX_IN_WL_CNT_VER_6_T(txnoassoc),
++	IDX_IN_WL_CNT_VER_6_T(txrunt),
++	IDX_IN_WL_CNT_VER_6_T(txchit),
++	IDX_IN_WL_CNT_VER_6_T(txcmiss),
++	IDX_IN_WL_CNT_VER_6_T(txuflo),
++	IDX_IN_WL_CNT_VER_6_T(txphyerr),
++	IDX_IN_WL_CNT_VER_6_T(txphycrs),
++	IDX_IN_WL_CNT_VER_6_T(rxframe),
++	IDX_IN_WL_CNT_VER_6_T(rxbyte),
++	IDX_IN_WL_CNT_VER_6_T(rxerror),
++	IDX_IN_WL_CNT_VER_6_T(rxctl),
++	IDX_IN_WL_CNT_VER_6_T(rxnobuf),
++	IDX_IN_WL_CNT_VER_6_T(rxnondata),
++	IDX_IN_WL_CNT_VER_6_T(rxbadds),
++	IDX_IN_WL_CNT_VER_6_T(rxbadcm),
++	IDX_IN_WL_CNT_VER_6_T(rxfragerr),
++	IDX_IN_WL_CNT_VER_6_T(rxrunt),
++	IDX_IN_WL_CNT_VER_6_T(rxgiant),
++	IDX_IN_WL_CNT_VER_6_T(rxnoscb),
++	IDX_IN_WL_CNT_VER_6_T(rxbadproto),
++	IDX_IN_WL_CNT_VER_6_T(rxbadsrcmac),
++	IDX_IN_WL_CNT_VER_6_T(rxbadda),
++	IDX_IN_WL_CNT_VER_6_T(rxfilter),
++	IDX_IN_WL_CNT_VER_6_T(rxoflo),
++	IDX_IN_WL_CNT_VER_6_T(rxuflo),
++	IDX_IN_WL_CNT_VER_6_T(rxuflo) + 1,
++	IDX_IN_WL_CNT_VER_6_T(rxuflo) + 2,
++	IDX_IN_WL_CNT_VER_6_T(rxuflo) + 3,
++	IDX_IN_WL_CNT_VER_6_T(rxuflo) + 4,
++	IDX_IN_WL_CNT_VER_6_T(rxuflo) + 5,
++	IDX_IN_WL_CNT_VER_6_T(d11cnt_txrts_off),
++	IDX_IN_WL_CNT_VER_6_T(d11cnt_rxcrc_off),
++	IDX_IN_WL_CNT_VER_6_T(d11cnt_txnocts_off),
++	IDX_IN_WL_CNT_VER_6_T(dmade),
++	IDX_IN_WL_CNT_VER_6_T(dmada),
++	IDX_IN_WL_CNT_VER_6_T(dmape),
++	IDX_IN_WL_CNT_VER_6_T(reset),
++	IDX_IN_WL_CNT_VER_6_T(tbtt),
++	IDX_IN_WL_CNT_VER_6_T(txdmawar),
++	IDX_IN_WL_CNT_VER_6_T(pkt_callback_reg_fail),
++	IDX_IN_WL_CNT_VER_6_T(txfrag),
++	IDX_IN_WL_CNT_VER_6_T(txmulti),
++	IDX_IN_WL_CNT_VER_6_T(txfail),
++	IDX_IN_WL_CNT_VER_6_T(txretry),
++	IDX_IN_WL_CNT_VER_6_T(txretrie),
++	IDX_IN_WL_CNT_VER_6_T(rxdup),
++	IDX_IN_WL_CNT_VER_6_T(txrts),
++	IDX_IN_WL_CNT_VER_6_T(txnocts),
++	IDX_IN_WL_CNT_VER_6_T(txnoack),
++	IDX_IN_WL_CNT_VER_6_T(rxfrag),
++	IDX_IN_WL_CNT_VER_6_T(rxmulti),
++	IDX_IN_WL_CNT_VER_6_T(rxcrc),
++	IDX_IN_WL_CNT_VER_6_T(txfrmsnt),
++	IDX_IN_WL_CNT_VER_6_T(rxundec),
++	IDX_IN_WL_CNT_VER_6_T(tkipmicfaill),
++	IDX_IN_WL_CNT_VER_6_T(tkipcntrmsr),
++	IDX_IN_WL_CNT_VER_6_T(tkipreplay),
++	IDX_IN_WL_CNT_VER_6_T(ccmpfmterr),
++	IDX_IN_WL_CNT_VER_6_T(ccmpreplay),
++	IDX_IN_WL_CNT_VER_6_T(ccmpundec),
++	IDX_IN_WL_CNT_VER_6_T(fourwayfail),
++	IDX_IN_WL_CNT_VER_6_T(wepundec),
++	IDX_IN_WL_CNT_VER_6_T(wepicverr),
++	IDX_IN_WL_CNT_VER_6_T(decsuccess),
++	IDX_IN_WL_CNT_VER_6_T(tkipicverr),
++	IDX_IN_WL_CNT_VER_6_T(wepexcluded),
++	IDX_IN_WL_CNT_VER_6_T(txchanrej),
++	IDX_IN_WL_CNT_VER_6_T(psmwds),
++	IDX_IN_WL_CNT_VER_6_T(phywatchdog),
++	IDX_IN_WL_CNT_VER_6_T(prq_entries_handled),
++	IDX_IN_WL_CNT_VER_6_T(prq_undirected_entries),
++	IDX_IN_WL_CNT_VER_6_T(prq_bad_entries),
++	IDX_IN_WL_CNT_VER_6_T(atim_suppress_count),
++	IDX_IN_WL_CNT_VER_6_T(bcn_template_not_ready),
++	IDX_IN_WL_CNT_VER_6_T(bcn_template_not_ready_done),
++	IDX_IN_WL_CNT_VER_6_T(late_tbtt_dpc),
++	IDX_IN_WL_CNT_VER_6_T(rx1mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx2mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx5mbps5),
++	IDX_IN_WL_CNT_VER_6_T(rx6mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx9mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx11mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx12mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx18mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx24mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx36mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx48mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx54mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx108mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx162mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx216mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx270mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx324mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx378mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx432mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx486mbps),
++	IDX_IN_WL_CNT_VER_6_T(rx540mbps),
++	IDX_IN_WL_CNT_VER_6_T(rfdisable),
++	IDX_IN_WL_CNT_VER_6_T(txexptime),
++	IDX_IN_WL_CNT_VER_6_T(txmpdu_sgi),
++	IDX_IN_WL_CNT_VER_6_T(rxmpdu_sgi),
++	IDX_IN_WL_CNT_VER_6_T(txmpdu_stbc),
++	IDX_IN_WL_CNT_VER_6_T(rxmpdu_stbc),
++	IDX_IN_WL_CNT_VER_6_T(rxundec_mcst),
++	IDX_IN_WL_CNT_VER_6_T(tkipmicfaill_mcst),
++	IDX_IN_WL_CNT_VER_6_T(tkipcntrmsr_mcst),
++	IDX_IN_WL_CNT_VER_6_T(tkipreplay_mcst),
++	IDX_IN_WL_CNT_VER_6_T(ccmpfmterr_mcst),
++	IDX_IN_WL_CNT_VER_6_T(ccmpreplay_mcst),
++	IDX_IN_WL_CNT_VER_6_T(ccmpundec_mcst),
++	IDX_IN_WL_CNT_VER_6_T(fourwayfail_mcst),
++	IDX_IN_WL_CNT_VER_6_T(wepundec_mcst),
++	IDX_IN_WL_CNT_VER_6_T(wepicverr_mcst),
++	IDX_IN_WL_CNT_VER_6_T(decsuccess_mcst),
++	IDX_IN_WL_CNT_VER_6_T(tkipicverr_mcst),
++	IDX_IN_WL_CNT_VER_6_T(wepexcluded_mcst)
++};
++
++/* Index conversion table from wl_cnt_ver_11_t to wl_cnt_wlc_t */
++static const uint8 wlcntver11t_to_wlcntwlct[NUM_OF_WLCCNT_IN_WL_CNT_VER_11_T] = {
++	IDX_IN_WL_CNT_VER_11_T(txframe),
++	IDX_IN_WL_CNT_VER_11_T(txbyte),
++	IDX_IN_WL_CNT_VER_11_T(txretrans),
++	IDX_IN_WL_CNT_VER_11_T(txerror),
++	IDX_IN_WL_CNT_VER_11_T(txctl),
++	IDX_IN_WL_CNT_VER_11_T(txprshort),
++	IDX_IN_WL_CNT_VER_11_T(txserr),
++	IDX_IN_WL_CNT_VER_11_T(txnobuf),
++	IDX_IN_WL_CNT_VER_11_T(txnoassoc),
++	IDX_IN_WL_CNT_VER_11_T(txrunt),
++	IDX_IN_WL_CNT_VER_11_T(txchit),
++	IDX_IN_WL_CNT_VER_11_T(txcmiss),
++	IDX_IN_WL_CNT_VER_11_T(txuflo),
++	IDX_IN_WL_CNT_VER_11_T(txphyerr),
++	IDX_IN_WL_CNT_VER_11_T(txphycrs),
++	IDX_IN_WL_CNT_VER_11_T(rxframe),
++	IDX_IN_WL_CNT_VER_11_T(rxbyte),
++	IDX_IN_WL_CNT_VER_11_T(rxerror),
++	IDX_IN_WL_CNT_VER_11_T(rxctl),
++	IDX_IN_WL_CNT_VER_11_T(rxnobuf),
++	IDX_IN_WL_CNT_VER_11_T(rxnondata),
++	IDX_IN_WL_CNT_VER_11_T(rxbadds),
++	IDX_IN_WL_CNT_VER_11_T(rxbadcm),
++	IDX_IN_WL_CNT_VER_11_T(rxfragerr),
++	IDX_IN_WL_CNT_VER_11_T(rxrunt),
++	IDX_IN_WL_CNT_VER_11_T(rxgiant),
++	IDX_IN_WL_CNT_VER_11_T(rxnoscb),
++	IDX_IN_WL_CNT_VER_11_T(rxbadproto),
++	IDX_IN_WL_CNT_VER_11_T(rxbadsrcmac),
++	IDX_IN_WL_CNT_VER_11_T(rxbadda),
++	IDX_IN_WL_CNT_VER_11_T(rxfilter),
++	IDX_IN_WL_CNT_VER_11_T(rxoflo),
++	IDX_IN_WL_CNT_VER_11_T(rxuflo),
++	IDX_IN_WL_CNT_VER_11_T(rxuflo) + 1,
++	IDX_IN_WL_CNT_VER_11_T(rxuflo) + 2,
++	IDX_IN_WL_CNT_VER_11_T(rxuflo) + 3,
++	IDX_IN_WL_CNT_VER_11_T(rxuflo) + 4,
++	IDX_IN_WL_CNT_VER_11_T(rxuflo) + 5,
++	IDX_IN_WL_CNT_VER_11_T(d11cnt_txrts_off),
++	IDX_IN_WL_CNT_VER_11_T(d11cnt_rxcrc_off),
++	IDX_IN_WL_CNT_VER_11_T(d11cnt_txnocts_off),
++	IDX_IN_WL_CNT_VER_11_T(dmade),
++	IDX_IN_WL_CNT_VER_11_T(dmada),
++	IDX_IN_WL_CNT_VER_11_T(dmape),
++	IDX_IN_WL_CNT_VER_11_T(reset),
++	IDX_IN_WL_CNT_VER_11_T(tbtt),
++	IDX_IN_WL_CNT_VER_11_T(txdmawar),
++	IDX_IN_WL_CNT_VER_11_T(pkt_callback_reg_fail),
++	IDX_IN_WL_CNT_VER_11_T(txfrag),
++	IDX_IN_WL_CNT_VER_11_T(txmulti),
++	IDX_IN_WL_CNT_VER_11_T(txfail),
++	IDX_IN_WL_CNT_VER_11_T(txretry),
++	IDX_IN_WL_CNT_VER_11_T(txretrie),
++	IDX_IN_WL_CNT_VER_11_T(rxdup),
++	IDX_IN_WL_CNT_VER_11_T(txrts),
++	IDX_IN_WL_CNT_VER_11_T(txnocts),
++	IDX_IN_WL_CNT_VER_11_T(txnoack),
++	IDX_IN_WL_CNT_VER_11_T(rxfrag),
++	IDX_IN_WL_CNT_VER_11_T(rxmulti),
++	IDX_IN_WL_CNT_VER_11_T(rxcrc),
++	IDX_IN_WL_CNT_VER_11_T(txfrmsnt),
++	IDX_IN_WL_CNT_VER_11_T(rxundec),
++	IDX_IN_WL_CNT_VER_11_T(tkipmicfaill),
++	IDX_IN_WL_CNT_VER_11_T(tkipcntrmsr),
++	IDX_IN_WL_CNT_VER_11_T(tkipreplay),
++	IDX_IN_WL_CNT_VER_11_T(ccmpfmterr),
++	IDX_IN_WL_CNT_VER_11_T(ccmpreplay),
++	IDX_IN_WL_CNT_VER_11_T(ccmpundec),
++	IDX_IN_WL_CNT_VER_11_T(fourwayfail),
++	IDX_IN_WL_CNT_VER_11_T(wepundec),
++	IDX_IN_WL_CNT_VER_11_T(wepicverr),
++	IDX_IN_WL_CNT_VER_11_T(decsuccess),
++	IDX_IN_WL_CNT_VER_11_T(tkipicverr),
++	IDX_IN_WL_CNT_VER_11_T(wepexcluded),
++	IDX_IN_WL_CNT_VER_11_T(txchanrej),
++	IDX_IN_WL_CNT_VER_11_T(psmwds),
++	IDX_IN_WL_CNT_VER_11_T(phywatchdog),
++	IDX_IN_WL_CNT_VER_11_T(prq_entries_handled),
++	IDX_IN_WL_CNT_VER_11_T(prq_undirected_entries),
++	IDX_IN_WL_CNT_VER_11_T(prq_bad_entries),
++	IDX_IN_WL_CNT_VER_11_T(atim_suppress_count),
++	IDX_IN_WL_CNT_VER_11_T(bcn_template_not_ready),
++	IDX_IN_WL_CNT_VER_11_T(bcn_template_not_ready_done),
++	IDX_IN_WL_CNT_VER_11_T(late_tbtt_dpc),
++	IDX_IN_WL_CNT_VER_11_T(rx1mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx2mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx5mbps5),
++	IDX_IN_WL_CNT_VER_11_T(rx6mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx9mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx11mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx12mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx18mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx24mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx36mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx48mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx54mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx108mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx162mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx216mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx270mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx324mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx378mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx432mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx486mbps),
++	IDX_IN_WL_CNT_VER_11_T(rx540mbps),
++	IDX_IN_WL_CNT_VER_11_T(rfdisable),
++	IDX_IN_WL_CNT_VER_11_T(txexptime),
++	IDX_IN_WL_CNT_VER_11_T(txmpdu_sgi),
++	IDX_IN_WL_CNT_VER_11_T(rxmpdu_sgi),
++	IDX_IN_WL_CNT_VER_11_T(txmpdu_stbc),
++	IDX_IN_WL_CNT_VER_11_T(rxmpdu_stbc),
++	IDX_IN_WL_CNT_VER_11_T(rxundec_mcst),
++	IDX_IN_WL_CNT_VER_11_T(tkipmicfaill_mcst),
++	IDX_IN_WL_CNT_VER_11_T(tkipcntrmsr_mcst),
++	IDX_IN_WL_CNT_VER_11_T(tkipreplay_mcst),
++	IDX_IN_WL_CNT_VER_11_T(ccmpfmterr_mcst),
++	IDX_IN_WL_CNT_VER_11_T(ccmpreplay_mcst),
++	IDX_IN_WL_CNT_VER_11_T(ccmpundec_mcst),
++	IDX_IN_WL_CNT_VER_11_T(fourwayfail_mcst),
++	IDX_IN_WL_CNT_VER_11_T(wepundec_mcst),
++	IDX_IN_WL_CNT_VER_11_T(wepicverr_mcst),
++	IDX_IN_WL_CNT_VER_11_T(decsuccess_mcst),
++	IDX_IN_WL_CNT_VER_11_T(tkipicverr_mcst),
++	IDX_IN_WL_CNT_VER_11_T(wepexcluded_mcst),
++	IDX_IN_WL_CNT_VER_11_T(dma_hang),
++	IDX_IN_WL_CNT_VER_11_T(reinit),
++	IDX_IN_WL_CNT_VER_11_T(pstatxucast),
++	IDX_IN_WL_CNT_VER_11_T(pstatxnoassoc),
++	IDX_IN_WL_CNT_VER_11_T(pstarxucast),
++	IDX_IN_WL_CNT_VER_11_T(pstarxbcmc),
++	IDX_IN_WL_CNT_VER_11_T(pstatxbcmc),
++	IDX_IN_WL_CNT_VER_11_T(cso_passthrough),
++	IDX_IN_WL_CNT_VER_11_T(cso_normal),
++	IDX_IN_WL_CNT_VER_11_T(chained),
++	IDX_IN_WL_CNT_VER_11_T(chainedsz1),
++	IDX_IN_WL_CNT_VER_11_T(unchained),
++	IDX_IN_WL_CNT_VER_11_T(maxchainsz),
++	IDX_IN_WL_CNT_VER_11_T(currchainsz),
++	IDX_IN_WL_CNT_VER_11_T(pciereset),
++	IDX_IN_WL_CNT_VER_11_T(cfgrestore),
++	IDX_IN_WL_CNT_VER_11_T(reinitreason),
++	IDX_IN_WL_CNT_VER_11_T(reinitreason) + 1,
++	IDX_IN_WL_CNT_VER_11_T(reinitreason) + 2,
++	IDX_IN_WL_CNT_VER_11_T(reinitreason) + 3,
++	IDX_IN_WL_CNT_VER_11_T(reinitreason) + 4,
++	IDX_IN_WL_CNT_VER_11_T(reinitreason) + 5,
++	IDX_IN_WL_CNT_VER_11_T(reinitreason) + 6,
++	IDX_IN_WL_CNT_VER_11_T(reinitreason) + 7,
++	IDX_IN_WL_CNT_VER_11_T(rxrtry),
++	IDX_IN_WL_CNT_VER_11_T(rxmpdu_mu),
++	IDX_IN_WL_CNT_VER_11_T(txbar),
++	IDX_IN_WL_CNT_VER_11_T(rxbar),
++	IDX_IN_WL_CNT_VER_11_T(txpspoll),
++	IDX_IN_WL_CNT_VER_11_T(rxpspoll),
++	IDX_IN_WL_CNT_VER_11_T(txnull),
++	IDX_IN_WL_CNT_VER_11_T(rxnull),
++	IDX_IN_WL_CNT_VER_11_T(txqosnull),
++	IDX_IN_WL_CNT_VER_11_T(rxqosnull),
++	IDX_IN_WL_CNT_VER_11_T(txassocreq),
++	IDX_IN_WL_CNT_VER_11_T(rxassocreq),
++	IDX_IN_WL_CNT_VER_11_T(txreassocreq),
++	IDX_IN_WL_CNT_VER_11_T(rxreassocreq),
++	IDX_IN_WL_CNT_VER_11_T(txdisassoc),
++	IDX_IN_WL_CNT_VER_11_T(rxdisassoc),
++	IDX_IN_WL_CNT_VER_11_T(txassocrsp),
++	IDX_IN_WL_CNT_VER_11_T(rxassocrsp),
++	IDX_IN_WL_CNT_VER_11_T(txreassocrsp),
++	IDX_IN_WL_CNT_VER_11_T(rxreassocrsp),
++	IDX_IN_WL_CNT_VER_11_T(txauth),
++	IDX_IN_WL_CNT_VER_11_T(rxauth),
++	IDX_IN_WL_CNT_VER_11_T(txdeauth),
++	IDX_IN_WL_CNT_VER_11_T(rxdeauth),
++	IDX_IN_WL_CNT_VER_11_T(txprobereq),
++	IDX_IN_WL_CNT_VER_11_T(rxprobereq),
++	IDX_IN_WL_CNT_VER_11_T(txprobersp),
++	IDX_IN_WL_CNT_VER_11_T(rxprobersp),
++	IDX_IN_WL_CNT_VER_11_T(txaction),
++	IDX_IN_WL_CNT_VER_11_T(rxaction),
++	IDX_IN_WL_CNT_VER_11_T(ampdu_wds),
++	IDX_IN_WL_CNT_VER_11_T(txlost),
++	IDX_IN_WL_CNT_VER_11_T(txdatamcast),
++	IDX_IN_WL_CNT_VER_11_T(txdatabcast)
++};
++
++/* Index conversion table from wl_cnt_ver_11_t to
++ * either wl_cnt_ge40mcst_v1_t or wl_cnt_lt40mcst_v1_t
++ */
++static const uint8 wlcntver11t_to_wlcntXX40mcstv1t[WL_CNT_MCST_VAR_NUM] = {
++	IDX_IN_WL_CNT_VER_11_T(txallfrm),
++	IDX_IN_WL_CNT_VER_11_T(txrtsfrm),
++	IDX_IN_WL_CNT_VER_11_T(txctsfrm),
++	IDX_IN_WL_CNT_VER_11_T(txackfrm),
++	IDX_IN_WL_CNT_VER_11_T(txdnlfrm),
++	IDX_IN_WL_CNT_VER_11_T(txbcnfrm),
++	IDX_IN_WL_CNT_VER_11_T(txfunfl),
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 1,
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 2,
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 3,
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 4,
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 5,
++	IDX_IN_WL_CNT_VER_11_T(txfbw),
++	IDX_IN_WL_CNT_VER_11_T(txmpdu),
++	IDX_IN_WL_CNT_VER_11_T(txtplunfl),
++	IDX_IN_WL_CNT_VER_11_T(txphyerror),
++	IDX_IN_WL_CNT_VER_11_T(pktengrxducast),
++	IDX_IN_WL_CNT_VER_11_T(pktengrxdmcast),
++	IDX_IN_WL_CNT_VER_11_T(rxfrmtoolong),
++	IDX_IN_WL_CNT_VER_11_T(rxfrmtooshrt),
++	IDX_IN_WL_CNT_VER_11_T(rxinvmachdr),
++	IDX_IN_WL_CNT_VER_11_T(rxbadfcs),
++	IDX_IN_WL_CNT_VER_11_T(rxbadplcp),
++	IDX_IN_WL_CNT_VER_11_T(rxcrsglitch),
++	IDX_IN_WL_CNT_VER_11_T(rxstrt),
++	IDX_IN_WL_CNT_VER_11_T(rxdfrmucastmbss),
++	IDX_IN_WL_CNT_VER_11_T(rxmfrmucastmbss),
++	IDX_IN_WL_CNT_VER_11_T(rxcfrmucast),
++	IDX_IN_WL_CNT_VER_11_T(rxrtsucast),
++	IDX_IN_WL_CNT_VER_11_T(rxctsucast),
++	IDX_IN_WL_CNT_VER_11_T(rxackucast),
++	IDX_IN_WL_CNT_VER_11_T(rxdfrmocast),
++	IDX_IN_WL_CNT_VER_11_T(rxmfrmocast),
++	IDX_IN_WL_CNT_VER_11_T(rxcfrmocast),
++	IDX_IN_WL_CNT_VER_11_T(rxrtsocast),
++	IDX_IN_WL_CNT_VER_11_T(rxctsocast),
++	IDX_IN_WL_CNT_VER_11_T(rxdfrmmcast),
++	IDX_IN_WL_CNT_VER_11_T(rxmfrmmcast),
++	IDX_IN_WL_CNT_VER_11_T(rxcfrmmcast),
++	IDX_IN_WL_CNT_VER_11_T(rxbeaconmbss),
++	IDX_IN_WL_CNT_VER_11_T(rxdfrmucastobss),
++	IDX_IN_WL_CNT_VER_11_T(rxbeaconobss),
++	IDX_IN_WL_CNT_VER_11_T(rxrsptmout),
++	IDX_IN_WL_CNT_VER_11_T(bcntxcancl),
++	IDX_IN_WL_CNT_VER_11_T(rxnodelim),
++	IDX_IN_WL_CNT_VER_11_T(rxf0ovfl),
++	IDX_IN_WL_CNT_VER_11_T(rxf1ovfl),
++	IDX_IN_WL_CNT_VER_11_T(rxf2ovfl),
++	IDX_IN_WL_CNT_VER_11_T(txsfovfl),
++	IDX_IN_WL_CNT_VER_11_T(pmqovfl),
++	IDX_IN_WL_CNT_VER_11_T(rxcgprqfrm),
++	IDX_IN_WL_CNT_VER_11_T(rxcgprsqovfl),
++	IDX_IN_WL_CNT_VER_11_T(txcgprsfail),
++	IDX_IN_WL_CNT_VER_11_T(txcgprssuc),
++	IDX_IN_WL_CNT_VER_11_T(prs_timeout),
++	IDX_IN_WL_CNT_VER_11_T(rxnack),
++	IDX_IN_WL_CNT_VER_11_T(frmscons),
++	IDX_IN_WL_CNT_VER_11_T(txnack),
++	IDX_IN_WL_CNT_VER_11_T(rxback),
++	IDX_IN_WL_CNT_VER_11_T(txback),
++	IDX_IN_WL_CNT_VER_11_T(bphy_rxcrsglitch),
++	IDX_IN_WL_CNT_VER_11_T(rxdrop20s),
++	IDX_IN_WL_CNT_VER_11_T(rxtoolate),
++	IDX_IN_WL_CNT_VER_11_T(bphy_badplcp)
++};
++
++/* For mcst offsets that were not used. (2 Pads) */
++#define INVALID_MCST_IDX ((uint8)(-1))
++/* Index conversion table from wl_cnt_ver_11_t to wl_cnt_v_le10_mcst_t */
++static const uint8 wlcntver11t_to_wlcntvle10mcstt[WL_CNT_MCST_VAR_NUM] = {
++	IDX_IN_WL_CNT_VER_11_T(txallfrm),
++	IDX_IN_WL_CNT_VER_11_T(txrtsfrm),
++	IDX_IN_WL_CNT_VER_11_T(txctsfrm),
++	IDX_IN_WL_CNT_VER_11_T(txackfrm),
++	IDX_IN_WL_CNT_VER_11_T(txdnlfrm),
++	IDX_IN_WL_CNT_VER_11_T(txbcnfrm),
++	IDX_IN_WL_CNT_VER_11_T(txfunfl),
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 1,
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 2,
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 3,
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 4,
++	IDX_IN_WL_CNT_VER_11_T(txfunfl) + 5,
++	IDX_IN_WL_CNT_VER_11_T(txfbw),
++	INVALID_MCST_IDX,
++	IDX_IN_WL_CNT_VER_11_T(txtplunfl),
++	IDX_IN_WL_CNT_VER_11_T(txphyerror),
++	IDX_IN_WL_CNT_VER_11_T(pktengrxducast),
++	IDX_IN_WL_CNT_VER_11_T(pktengrxdmcast),
++	IDX_IN_WL_CNT_VER_11_T(rxfrmtoolong),
++	IDX_IN_WL_CNT_VER_11_T(rxfrmtooshrt),
++	IDX_IN_WL_CNT_VER_11_T(rxinvmachdr),
++	IDX_IN_WL_CNT_VER_11_T(rxbadfcs),
++	IDX_IN_WL_CNT_VER_11_T(rxbadplcp),
++	IDX_IN_WL_CNT_VER_11_T(rxcrsglitch),
++	IDX_IN_WL_CNT_VER_11_T(rxstrt),
++	IDX_IN_WL_CNT_VER_11_T(rxdfrmucastmbss),
++	IDX_IN_WL_CNT_VER_11_T(rxmfrmucastmbss),
++	IDX_IN_WL_CNT_VER_11_T(rxcfrmucast),
++	IDX_IN_WL_CNT_VER_11_T(rxrtsucast),
++	IDX_IN_WL_CNT_VER_11_T(rxctsucast),
++	IDX_IN_WL_CNT_VER_11_T(rxackucast),
++	IDX_IN_WL_CNT_VER_11_T(rxdfrmocast),
++	IDX_IN_WL_CNT_VER_11_T(rxmfrmocast),
++	IDX_IN_WL_CNT_VER_11_T(rxcfrmocast),
++	IDX_IN_WL_CNT_VER_11_T(rxrtsocast),
++	IDX_IN_WL_CNT_VER_11_T(rxctsocast),
++	IDX_IN_WL_CNT_VER_11_T(rxdfrmmcast),
++	IDX_IN_WL_CNT_VER_11_T(rxmfrmmcast),
++	IDX_IN_WL_CNT_VER_11_T(rxcfrmmcast),
++	IDX_IN_WL_CNT_VER_11_T(rxbeaconmbss),
++	IDX_IN_WL_CNT_VER_11_T(rxdfrmucastobss),
++	IDX_IN_WL_CNT_VER_11_T(rxbeaconobss),
++	IDX_IN_WL_CNT_VER_11_T(rxrsptmout),
++	IDX_IN_WL_CNT_VER_11_T(bcntxcancl),
++	INVALID_MCST_IDX,
++	IDX_IN_WL_CNT_VER_11_T(rxf0ovfl),
++	IDX_IN_WL_CNT_VER_11_T(rxf1ovfl),
++	IDX_IN_WL_CNT_VER_11_T(rxf2ovfl),
++	IDX_IN_WL_CNT_VER_11_T(txsfovfl),
++	IDX_IN_WL_CNT_VER_11_T(pmqovfl),
++	IDX_IN_WL_CNT_VER_11_T(rxcgprqfrm),
++	IDX_IN_WL_CNT_VER_11_T(rxcgprsqovfl),
++	IDX_IN_WL_CNT_VER_11_T(txcgprsfail),
++	IDX_IN_WL_CNT_VER_11_T(txcgprssuc),
++	IDX_IN_WL_CNT_VER_11_T(prs_timeout),
++	IDX_IN_WL_CNT_VER_11_T(rxnack),
++	IDX_IN_WL_CNT_VER_11_T(frmscons),
++	IDX_IN_WL_CNT_VER_11_T(txnack),
++	IDX_IN_WL_CNT_VER_11_T(rxback),
++	IDX_IN_WL_CNT_VER_11_T(txback),
++	IDX_IN_WL_CNT_VER_11_T(bphy_rxcrsglitch),
++	IDX_IN_WL_CNT_VER_11_T(rxdrop20s),
++	IDX_IN_WL_CNT_VER_11_T(rxtoolate),
++	IDX_IN_WL_CNT_VER_11_T(bphy_badplcp)
++};
++
++
++/* Index conversion table from wl_cnt_ver_6_t to wl_cnt_v_le10_mcst_t */
++static const uint8 wlcntver6t_to_wlcntvle10mcstt[WL_CNT_MCST_VAR_NUM] = {
++	IDX_IN_WL_CNT_VER_6_T(txallfrm),
++	IDX_IN_WL_CNT_VER_6_T(txrtsfrm),
++	IDX_IN_WL_CNT_VER_6_T(txctsfrm),
++	IDX_IN_WL_CNT_VER_6_T(txackfrm),
++	IDX_IN_WL_CNT_VER_6_T(txdnlfrm),
++	IDX_IN_WL_CNT_VER_6_T(txbcnfrm),
++	IDX_IN_WL_CNT_VER_6_T(txfunfl),
++	IDX_IN_WL_CNT_VER_6_T(txfunfl) + 1,
++	IDX_IN_WL_CNT_VER_6_T(txfunfl) + 2,
++	IDX_IN_WL_CNT_VER_6_T(txfunfl) + 3,
++	IDX_IN_WL_CNT_VER_6_T(txfunfl) + 4,
++	IDX_IN_WL_CNT_VER_6_T(txfunfl) + 5,
++	IDX_IN_WL_CNT_VER_6_T(txfbw),
++	INVALID_MCST_IDX,
++	IDX_IN_WL_CNT_VER_6_T(txtplunfl),
++	IDX_IN_WL_CNT_VER_6_T(txphyerror),
++	IDX_IN_WL_CNT_VER_6_T(pktengrxducast),
++	IDX_IN_WL_CNT_VER_6_T(pktengrxdmcast),
++	IDX_IN_WL_CNT_VER_6_T(rxfrmtoolong),
++	IDX_IN_WL_CNT_VER_6_T(rxfrmtooshrt),
++	IDX_IN_WL_CNT_VER_6_T(rxinvmachdr),
++	IDX_IN_WL_CNT_VER_6_T(rxbadfcs),
++	IDX_IN_WL_CNT_VER_6_T(rxbadplcp),
++	IDX_IN_WL_CNT_VER_6_T(rxcrsglitch),
++	IDX_IN_WL_CNT_VER_6_T(rxstrt),
++	IDX_IN_WL_CNT_VER_6_T(rxdfrmucastmbss),
++	IDX_IN_WL_CNT_VER_6_T(rxmfrmucastmbss),
++	IDX_IN_WL_CNT_VER_6_T(rxcfrmucast),
++	IDX_IN_WL_CNT_VER_6_T(rxrtsucast),
++	IDX_IN_WL_CNT_VER_6_T(rxctsucast),
++	IDX_IN_WL_CNT_VER_6_T(rxackucast),
++	IDX_IN_WL_CNT_VER_6_T(rxdfrmocast),
++	IDX_IN_WL_CNT_VER_6_T(rxmfrmocast),
++	IDX_IN_WL_CNT_VER_6_T(rxcfrmocast),
++	IDX_IN_WL_CNT_VER_6_T(rxrtsocast),
++	IDX_IN_WL_CNT_VER_6_T(rxctsocast),
++	IDX_IN_WL_CNT_VER_6_T(rxdfrmmcast),
++	IDX_IN_WL_CNT_VER_6_T(rxmfrmmcast),
++	IDX_IN_WL_CNT_VER_6_T(rxcfrmmcast),
++	IDX_IN_WL_CNT_VER_6_T(rxbeaconmbss),
++	IDX_IN_WL_CNT_VER_6_T(rxdfrmucastobss),
++	IDX_IN_WL_CNT_VER_6_T(rxbeaconobss),
++	IDX_IN_WL_CNT_VER_6_T(rxrsptmout),
++	IDX_IN_WL_CNT_VER_6_T(bcntxcancl),
++	INVALID_MCST_IDX,
++	IDX_IN_WL_CNT_VER_6_T(rxf0ovfl),
++	IDX_IN_WL_CNT_VER_6_T(rxf1ovfl),
++	IDX_IN_WL_CNT_VER_6_T(rxf2ovfl),
++	IDX_IN_WL_CNT_VER_6_T(txsfovfl),
++	IDX_IN_WL_CNT_VER_6_T(pmqovfl),
++	IDX_IN_WL_CNT_VER_6_T(rxcgprqfrm),
++	IDX_IN_WL_CNT_VER_6_T(rxcgprsqovfl),
++	IDX_IN_WL_CNT_VER_6_T(txcgprsfail),
++	IDX_IN_WL_CNT_VER_6_T(txcgprssuc),
++	IDX_IN_WL_CNT_VER_6_T(prs_timeout),
++	IDX_IN_WL_CNT_VER_6_T(rxnack),
++	IDX_IN_WL_CNT_VER_6_T(frmscons),
++	IDX_IN_WL_CNT_VER_6_T(txnack),
++	IDX_IN_WL_CNT_VER_6_T(rxback),
++	IDX_IN_WL_CNT_VER_6_T(txback),
++	IDX_IN_WL_CNT_VER_6_T(bphy_rxcrsglitch),
++	IDX_IN_WL_CNT_VER_6_T(rxdrop20s),
++	IDX_IN_WL_CNT_VER_6_T(rxtoolate),
++	IDX_IN_WL_CNT_VER_6_T(bphy_badplcp)
++};
++
++/* copy wlc layer counters from old type cntbuf to wl_cnt_wlc_t type. */
++static int
++wl_copy_wlccnt(uint16 cntver, uint32 *dst, uint32 *src, uint8 src_max_idx)
++{
++	uint i;
++	if (dst == NULL || src == NULL) {
++		return BCME_ERROR;
++	}
++
++	/* Init wlccnt with invalid value. Unchanged value will not be printed out */
++	for (i = 0; i < (sizeof(wl_cnt_wlc_t) / sizeof(uint32)); i++) {
++		dst[i] = INVALID_CNT_VAL;
++	}
++
++	if (cntver == WL_CNT_VERSION_6) {
++		for (i = 0; i < NUM_OF_WLCCNT_IN_WL_CNT_VER_6_T; i++) {
++			if (wlcntver6t_to_wlcntwlct[i] >= src_max_idx) {
++			/* src buffer does not have counters from here */
++				break;
++			}
++			dst[i] = src[wlcntver6t_to_wlcntwlct[i]];
++		}
++	} else {
++		for (i = 0; i < NUM_OF_WLCCNT_IN_WL_CNT_VER_11_T; i++) {
++			if (wlcntver11t_to_wlcntwlct[i] >= src_max_idx) {
++			/* src buffer does not have counters from here */
++				break;
++			}
++			dst[i] = src[wlcntver11t_to_wlcntwlct[i]];
++		}
++	}
++	return BCME_OK;
++}
++
++/* copy macstat counters from old type cntbuf to wl_cnt_v_le10_mcst_t type. */
++static int
++wl_copy_macstat_upto_ver10(uint16 cntver, uint32 *dst, uint32 *src)
++{
++	uint i;
++
++	if (dst == NULL || src == NULL) {
++		return BCME_ERROR;
++	}
++
++	if (cntver == WL_CNT_VERSION_6) {
++		for (i = 0; i < WL_CNT_MCST_VAR_NUM; i++) {
++			if (wlcntver6t_to_wlcntvle10mcstt[i] == INVALID_MCST_IDX) {
++				/* This mcst counter does not exist in wl_cnt_ver_6_t */
++				dst[i] = INVALID_CNT_VAL;
++			} else {
++				dst[i] = src[wlcntver6t_to_wlcntvle10mcstt[i]];
++			}
++		}
++	} else {
++		for (i = 0; i < WL_CNT_MCST_VAR_NUM; i++) {
++			if (wlcntver11t_to_wlcntvle10mcstt[i] == INVALID_MCST_IDX) {
++				/* This mcst counter does not exist in wl_cnt_ver_11_t */
++				dst[i] = INVALID_CNT_VAL;
++			} else {
++				dst[i] = src[wlcntver11t_to_wlcntvle10mcstt[i]];
++			}
++		}
++	}
++	return BCME_OK;
++}
++
++static int
++wl_copy_macstat_ver11(uint32 *dst, uint32 *src)
++{
++	uint i;
++
++	if (dst == NULL || src == NULL) {
++		return BCME_ERROR;
++	}
++
++	for (i = 0; i < WL_CNT_MCST_VAR_NUM; i++) {
++		dst[i] = src[wlcntver11t_to_wlcntXX40mcstv1t[i]];
++	}
++	return BCME_OK;
++}
++
++/**
++ * Translate non-xtlv 'wl counters' IOVar buffer received by old driver/FW to xtlv format.
++ * Parameters:
++ *	cntbuf: pointer to non-xtlv 'wl counters' IOVar buffer received by old driver/FW.
++ *		Newly translated xtlv format is written to this pointer.
++ *	buflen: length of the "cntbuf" without any padding.
++ *	corerev: chip core revision of the driver/FW.
++ */
++int
++wl_cntbuf_to_xtlv_format(void *ctx, void *cntbuf, int buflen, uint32 corerev)
++{
++	wl_cnt_wlc_t *wlccnt = NULL;
++	uint32 *macstat = NULL;
++	xtlv_desc_t xtlv_desc[3];
++	uint16 mcst_xtlv_id;
++	int res = BCME_OK;
++	wl_cnt_info_t *cntinfo = cntbuf;
++	void *xtlvbuf_p = cntinfo->data;
++	uint16 ver = cntinfo->version;
++	uint16 xtlvbuflen = (uint16)buflen;
++	uint16 src_max_idx;
++#ifdef BCMDRIVER
++	osl_t *osh = ctx;
++#else
++	BCM_REFERENCE(ctx);
++#endif
++
++	if (ver >= WL_CNT_VERSION_XTLV) {
++		/* Already in xtlv format. */
++		goto exit;
++	}
++
++#ifdef BCMDRIVER
++	wlccnt = MALLOC(osh, sizeof(*wlccnt));
++	macstat = MALLOC(osh, WL_CNT_MCST_STRUCT_SZ);
++#else
++	wlccnt = (wl_cnt_wlc_t *)malloc(sizeof(*wlccnt));
++	macstat = (uint32 *)malloc(WL_CNT_MCST_STRUCT_SZ);
++#endif
++	if (!wlccnt || !macstat) {
++		printf("%s: malloc fail!\n", __FUNCTION__);
++		res = BCME_NOMEM;
++		goto exit;
++	}
++
++	/* Check if the max idx in the struct exceeds the boundary of uint8 */
++	if (NUM_OF_CNT_IN_WL_CNT_VER_6_T > ((uint8)(-1) + 1) ||
++		NUM_OF_CNT_IN_WL_CNT_VER_11_T > ((uint8)(-1) + 1)) {
++		printf("wlcntverXXt_to_wlcntwlct and src_max_idx need"
++			" to be of uint16 instead of uint8\n");
++		res = BCME_ERROR;
++		goto exit;
++	}
++
++	/* Exclude version and length fields in either wlc_cnt_ver_6_t or wlc_cnt_ver_11_t */
++	src_max_idx = (cntinfo->datalen - OFFSETOF(wl_cnt_info_t, data)) / sizeof(uint32);
++
++	if (src_max_idx > (uint8)(-1)) {
++		printf("wlcntverXXt_to_wlcntwlct and src_max_idx need"
++			" to be of uint16 instead of uint8\n"
++			"Try updating wl utility to the latest.\n");
++		res = BCME_ERROR;
++	}
++
++	/* Copy wlc layer counters to wl_cnt_wlc_t */
++	res = wl_copy_wlccnt(ver, (uint32 *)wlccnt, (uint32 *)cntinfo->data, (uint8)src_max_idx);
++	if (res != BCME_OK) {
++		printf("wl_copy_wlccnt fail!\n");
++		goto exit;
++	}
++
++	/* Copy macstat counters to wl_cnt_wlc_t */
++	if (ver == WL_CNT_VERSION_11) {
++		res = wl_copy_macstat_ver11(macstat, (uint32 *)cntinfo->data);
++		if (res != BCME_OK) {
++			printf("wl_copy_macstat_ver11 fail!\n");
++			goto exit;
++		}
++		if (corerev >= 40) {
++			mcst_xtlv_id = WL_CNT_XTLV_GE40_UCODE_V1;
++		} else {
++			mcst_xtlv_id = WL_CNT_XTLV_LT40_UCODE_V1;
++		}
++	} else {
++		res = wl_copy_macstat_upto_ver10(ver, macstat, (uint32 *)cntinfo->data);
++		if (res != BCME_OK) {
++			printf("wl_copy_macstat_upto_ver10 fail!\n");
++			goto exit;
++		}
++		mcst_xtlv_id = WL_CNT_XTLV_CNTV_LE10_UCODE;
++	}
++
++	xtlv_desc[0].type = WL_CNT_XTLV_WLC;
++	xtlv_desc[0].len = sizeof(*wlccnt);
++	xtlv_desc[0].ptr = wlccnt;
++
++	xtlv_desc[1].type = mcst_xtlv_id;
++	xtlv_desc[1].len = WL_CNT_MCST_STRUCT_SZ;
++	xtlv_desc[1].ptr = macstat;
++
++	xtlv_desc[2].type = 0;
++	xtlv_desc[2].len = 0;
++	xtlv_desc[2].ptr = NULL;
++
++	memset(cntbuf, 0, buflen);
++
++	res = bcm_pack_xtlv_buf_from_mem(&xtlvbuf_p, &xtlvbuflen,
++		xtlv_desc, BCM_XTLV_OPTION_ALIGN32);
++	cntinfo->datalen = (buflen - xtlvbuflen);
++exit:
++#ifdef BCMDRIVER
++	if (wlccnt) {
++		MFREE(osh, wlccnt, sizeof(*wlccnt));
++	}
++	if (macstat) {
++		MFREE(osh, macstat, WL_CNT_MCST_STRUCT_SZ);
++	}
++#else
++	if (wlccnt) {
++		free(wlccnt);
++	}
++	if (macstat) {
++		free(macstat);
++	}
++#endif
++	return res;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmevent.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmevent.c
+new file mode 100644
+index 000000000..db06cfdef
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmevent.c
+@@ -0,0 +1,234 @@
++/*
++ * bcmevent read-only data shared by kernel or app layers
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmevent.c 606400 2015-12-15 09:59:42Z $
++ */
++
++#include <typedefs.h>
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <proto/ethernet.h>
++#include <proto/bcmeth.h>
++#include <proto/bcmevent.h>
++
++
++/* Table of event name strings for UIs and debugging dumps */
++typedef struct {
++	uint event;
++	const char *name;
++} bcmevent_name_str_t;
++
++/* Use the actual name for event tracing */
++#define BCMEVENT_NAME(_event) {(_event), #_event}
++
++static const bcmevent_name_str_t bcmevent_names[] = {
++	BCMEVENT_NAME(WLC_E_SET_SSID),
++	BCMEVENT_NAME(WLC_E_JOIN),
++	BCMEVENT_NAME(WLC_E_START),
++	BCMEVENT_NAME(WLC_E_AUTH),
++	BCMEVENT_NAME(WLC_E_AUTH_IND),
++	BCMEVENT_NAME(WLC_E_DEAUTH),
++	BCMEVENT_NAME(WLC_E_DEAUTH_IND),
++	BCMEVENT_NAME(WLC_E_ASSOC),
++	BCMEVENT_NAME(WLC_E_ASSOC_IND),
++	BCMEVENT_NAME(WLC_E_REASSOC),
++	BCMEVENT_NAME(WLC_E_REASSOC_IND),
++	BCMEVENT_NAME(WLC_E_DISASSOC),
++	BCMEVENT_NAME(WLC_E_DISASSOC_IND),
++	BCMEVENT_NAME(WLC_E_QUIET_START),
++	BCMEVENT_NAME(WLC_E_QUIET_END),
++	BCMEVENT_NAME(WLC_E_BEACON_RX),
++	BCMEVENT_NAME(WLC_E_LINK),
++	BCMEVENT_NAME(WLC_E_MIC_ERROR),
++	BCMEVENT_NAME(WLC_E_NDIS_LINK),
++	BCMEVENT_NAME(WLC_E_ROAM),
++	BCMEVENT_NAME(WLC_E_TXFAIL),
++	BCMEVENT_NAME(WLC_E_PMKID_CACHE),
++	BCMEVENT_NAME(WLC_E_RETROGRADE_TSF),
++	BCMEVENT_NAME(WLC_E_PRUNE),
++	BCMEVENT_NAME(WLC_E_AUTOAUTH),
++	BCMEVENT_NAME(WLC_E_EAPOL_MSG),
++	BCMEVENT_NAME(WLC_E_SCAN_COMPLETE),
++	BCMEVENT_NAME(WLC_E_ADDTS_IND),
++	BCMEVENT_NAME(WLC_E_DELTS_IND),
++	BCMEVENT_NAME(WLC_E_BCNSENT_IND),
++	BCMEVENT_NAME(WLC_E_BCNRX_MSG),
++	BCMEVENT_NAME(WLC_E_BCNLOST_MSG),
++	BCMEVENT_NAME(WLC_E_ROAM_PREP),
++	BCMEVENT_NAME(WLC_E_PFN_NET_FOUND),
++	BCMEVENT_NAME(WLC_E_PFN_SCAN_ALLGONE),
++	BCMEVENT_NAME(WLC_E_PFN_NET_LOST),
++#if defined(IBSS_PEER_DISCOVERY_EVENT)
++	BCMEVENT_NAME(WLC_E_IBSS_ASSOC),
++#endif /* defined(IBSS_PEER_DISCOVERY_EVENT) */
++	BCMEVENT_NAME(WLC_E_RADIO),
++	BCMEVENT_NAME(WLC_E_PSM_WATCHDOG),
++	BCMEVENT_NAME(WLC_E_PROBREQ_MSG),
++	BCMEVENT_NAME(WLC_E_SCAN_CONFIRM_IND),
++	BCMEVENT_NAME(WLC_E_PSK_SUP),
++	BCMEVENT_NAME(WLC_E_COUNTRY_CODE_CHANGED),
++	BCMEVENT_NAME(WLC_E_EXCEEDED_MEDIUM_TIME),
++	BCMEVENT_NAME(WLC_E_ICV_ERROR),
++	BCMEVENT_NAME(WLC_E_UNICAST_DECODE_ERROR),
++	BCMEVENT_NAME(WLC_E_MULTICAST_DECODE_ERROR),
++	BCMEVENT_NAME(WLC_E_TRACE),
++	BCMEVENT_NAME(WLC_E_IF),
++#ifdef WLP2P
++	BCMEVENT_NAME(WLC_E_P2P_DISC_LISTEN_COMPLETE),
++#endif
++	BCMEVENT_NAME(WLC_E_RSSI),
++	BCMEVENT_NAME(WLC_E_EXTLOG_MSG),
++	BCMEVENT_NAME(WLC_E_ACTION_FRAME),
++	BCMEVENT_NAME(WLC_E_ACTION_FRAME_RX),
++	BCMEVENT_NAME(WLC_E_ACTION_FRAME_COMPLETE),
++	BCMEVENT_NAME(WLC_E_ESCAN_RESULT),
++	BCMEVENT_NAME(WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE),
++#ifdef WLP2P
++	BCMEVENT_NAME(WLC_E_PROBRESP_MSG),
++	BCMEVENT_NAME(WLC_E_P2P_PROBREQ_MSG),
++#endif
++#ifdef PROP_TXSTATUS
++	BCMEVENT_NAME(WLC_E_FIFO_CREDIT_MAP),
++#endif
++	BCMEVENT_NAME(WLC_E_WAKE_EVENT),
++	BCMEVENT_NAME(WLC_E_DCS_REQUEST),
++	BCMEVENT_NAME(WLC_E_RM_COMPLETE),
++#ifdef WLMEDIA_HTSF
++	BCMEVENT_NAME(WLC_E_HTSFSYNC),
++#endif
++	BCMEVENT_NAME(WLC_E_OVERLAY_REQ),
++	BCMEVENT_NAME(WLC_E_CSA_COMPLETE_IND),
++	BCMEVENT_NAME(WLC_E_EXCESS_PM_WAKE_EVENT),
++	BCMEVENT_NAME(WLC_E_PFN_SCAN_NONE),
++	BCMEVENT_NAME(WLC_E_PFN_SCAN_ALLGONE),
++#ifdef SOFTAP
++	BCMEVENT_NAME(WLC_E_GTK_PLUMBED),
++#endif
++	BCMEVENT_NAME(WLC_E_ASSOC_REQ_IE),
++	BCMEVENT_NAME(WLC_E_ASSOC_RESP_IE),
++	BCMEVENT_NAME(WLC_E_BEACON_FRAME_RX),
++#ifdef WLTDLS
++	BCMEVENT_NAME(WLC_E_TDLS_PEER_EVENT),
++#endif /* WLTDLS */
++	BCMEVENT_NAME(WLC_E_NATIVE),
++#ifdef WLPKTDLYSTAT
++	BCMEVENT_NAME(WLC_E_PKTDELAY_IND),
++#endif /* WLPKTDLYSTAT */
++	BCMEVENT_NAME(WLC_E_SERVICE_FOUND),
++	BCMEVENT_NAME(WLC_E_GAS_FRAGMENT_RX),
++	BCMEVENT_NAME(WLC_E_GAS_COMPLETE),
++	BCMEVENT_NAME(WLC_E_P2PO_ADD_DEVICE),
++	BCMEVENT_NAME(WLC_E_P2PO_DEL_DEVICE),
++#ifdef WLWNM
++	BCMEVENT_NAME(WLC_E_WNM_STA_SLEEP),
++#endif /* WLWNM */
++#if defined(WL_PROXDETECT)
++	BCMEVENT_NAME(WLC_E_PROXD),
++#endif
++	BCMEVENT_NAME(WLC_E_CCA_CHAN_QUAL),
++	BCMEVENT_NAME(WLC_E_BSSID),
++#ifdef PROP_TXSTATUS
++	BCMEVENT_NAME(WLC_E_BCMC_CREDIT_SUPPORT),
++#endif
++	BCMEVENT_NAME(WLC_E_PSTA_PRIMARY_INTF_IND),
++	BCMEVENT_NAME(WLC_E_TXFAIL_THRESH),
++#ifdef GSCAN_SUPPORT
++	BCMEVENT_NAME(WLC_E_PFN_GSCAN_FULL_RESULT),
++	BCMEVENT_NAME(WLC_E_PFN_SWC),
++#endif /* GSCAN_SUPPORT */
++#ifdef WLBSSLOAD_REPORT
++	BCMEVENT_NAME(WLC_E_BSS_LOAD),
++#endif
++#if defined(BT_WIFI_HANDOVER) || defined(WL_TBOW)
++	BCMEVENT_NAME(WLC_E_BT_WIFI_HANDOVER_REQ),
++#endif
++#ifdef WLFBT
++	BCMEVENT_NAME(WLC_E_FBT_AUTH_REQ_IND),
++#endif /* WLFBT */
++	BCMEVENT_NAME(WLC_E_AUTHORIZED),
++	BCMEVENT_NAME(WLC_E_PROBREQ_MSG_RX),
++	BCMEVENT_NAME(WLC_E_CSA_START_IND),
++	BCMEVENT_NAME(WLC_E_CSA_DONE_IND),
++	BCMEVENT_NAME(WLC_E_CSA_FAILURE_IND),
++	BCMEVENT_NAME(WLC_E_RMC_EVENT),
++	BCMEVENT_NAME(WLC_E_DPSTA_INTF_IND),
++	BCMEVENT_NAME(WLC_E_ALLOW_CREDIT_BORROW),
++	BCMEVENT_NAME(WLC_E_ULP),
++};
++
++const char *bcmevent_get_name(uint event_type)
++{
++	/* note:  first coded this as a static const but some
++	 * ROMs already have something called event_name so
++	 * changed it so we don't have a variable for the
++	 * 'unknown string
++	 */
++	const char *event_name = NULL;
++
++	uint idx;
++	for (idx = 0; idx < (uint)ARRAYSIZE(bcmevent_names); idx++) {
++
++		if (bcmevent_names[idx].event == event_type) {
++			event_name = bcmevent_names[idx].name;
++			break;
++		}
++	}
++
++	/* if we find an event name in the array, return it.
++	 * otherwise return unknown string.
++	 */
++	return ((event_name) ? event_name : "Unknown Event");
++}
++
++void
++wl_event_to_host_order(wl_event_msg_t * evt)
++{
++	/* Event struct members passed from dongle to host are stored in network
++	* byte order. Convert all members to host-order.
++	*/
++	evt->event_type = ntoh32(evt->event_type);
++	evt->flags = ntoh16(evt->flags);
++	evt->status = ntoh32(evt->status);
++	evt->reason = ntoh32(evt->reason);
++	evt->auth_type = ntoh32(evt->auth_type);
++	evt->datalen = ntoh32(evt->datalen);
++	evt->version = ntoh16(evt->version);
++}
++
++void
++wl_event_to_network_order(wl_event_msg_t * evt)
++{
++	/* Event struct members passed from dongle to host are stored in network
++	* byte order. Convert all members to host-order.
++	*/
++	evt->event_type = hton32(evt->event_type);
++	evt->flags = hton16(evt->flags);
++	evt->status = hton32(evt->status);
++	evt->reason = hton32(evt->reason);
++	evt->auth_type = hton32(evt->auth_type);
++	evt->datalen = hton32(evt->datalen);
++	evt->version = hton16(evt->version);
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmsdh.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmsdh.c
+new file mode 100644
+index 000000000..335d32607
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmsdh.c
+@@ -0,0 +1,723 @@
++/*
++ *  BCMSDH interface glue
++ *  implement bcmsdh API for SDIOH driver
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmsdh.c 572557 2015-07-20 07:12:29Z $
++ */
++
++/**
++ * @file bcmsdh.c
++ */
++
++/* ****************** BCMSDH Interface Functions *************************** */
++
++#include <typedefs.h>
++#include <bcmdevs.h>
++#include <bcmendian.h>
++#include <bcmutils.h>
++#include <hndsoc.h>
++#include <siutils.h>
++#include <osl.h>
++
++#include <bcmsdh.h>	/* BRCM API for SDIO clients (such as wl, dhd) */
++#include <bcmsdbus.h>	/* common SDIO/controller interface */
++#include <sbsdio.h>	/* SDIO device core hardware definitions. */
++#include <sdio.h>	/* SDIO Device and Protocol Specs */
++
++#define SDIOH_API_ACCESS_RETRY_LIMIT	2
++const uint bcmsdh_msglevel = BCMSDH_ERROR_VAL;
++
++/* local copy of bcm sd handler */
++bcmsdh_info_t * l_bcmsdh = NULL;
++
++
++#if defined(OOB_INTR_ONLY) && defined(HW_OOB)
++extern int
++sdioh_enable_hw_oob_intr(void *sdioh, bool enable);
++
++void
++bcmsdh_enable_hw_oob_intr(bcmsdh_info_t *sdh, bool enable)
++{
++	sdioh_enable_hw_oob_intr(sdh->sdioh, enable);
++}
++#endif
++
++/* Attach BCMSDH layer to SDIO Host Controller Driver
++ *
++ * @param osh OSL Handle.
++ * @param cfghdl Configuration Handle.
++ * @param regsva Virtual address of controller registers.
++ * @param irq Interrupt number of SDIO controller.
++ *
++ * @return bcmsdh_info_t Handle to BCMSDH context.
++ */
++bcmsdh_info_t *
++bcmsdh_attach(osl_t *osh, void *sdioh, ulong *regsva)
++{
++	bcmsdh_info_t *bcmsdh;
++
++	if ((bcmsdh = (bcmsdh_info_t *)MALLOC(osh, sizeof(bcmsdh_info_t))) == NULL) {
++		BCMSDH_ERROR(("bcmsdh_attach: out of memory, malloced %d bytes\n", MALLOCED(osh)));
++		return NULL;
++	}
++	bzero((char *)bcmsdh, sizeof(bcmsdh_info_t));
++	bcmsdh->sdioh = sdioh;
++	bcmsdh->osh = osh;
++	bcmsdh->init_success = TRUE;
++	*regsva = SI_ENUM_BASE;
++
++	bcmsdh_force_sbwad_calc(bcmsdh, FALSE);
++
++	/* Report the BAR, to fix if needed */
++	bcmsdh->sbwad = SI_ENUM_BASE;
++
++	/* save the handler locally */
++	l_bcmsdh = bcmsdh;
++
++	return bcmsdh;
++}
++
++int
++bcmsdh_detach(osl_t *osh, void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	if (bcmsdh != NULL) {
++		MFREE(osh, bcmsdh, sizeof(bcmsdh_info_t));
++	}
++
++	l_bcmsdh = NULL;
++
++	return 0;
++}
++
++int
++bcmsdh_iovar_op(void *sdh, const char *name,
++                void *params, int plen, void *arg, int len, bool set)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	return sdioh_iovar_op(bcmsdh->sdioh, name, params, plen, arg, len, set);
++}
++
++bool
++bcmsdh_intr_query(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	bool on;
++
++	ASSERT(bcmsdh);
++	status = sdioh_interrupt_query(bcmsdh->sdioh, &on);
++	if (SDIOH_API_SUCCESS(status))
++		return FALSE;
++	else
++		return on;
++}
++
++int
++bcmsdh_intr_enable(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	ASSERT(bcmsdh);
++
++	status = sdioh_interrupt_set(bcmsdh->sdioh, TRUE);
++	return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
++}
++
++int
++bcmsdh_intr_disable(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	ASSERT(bcmsdh);
++
++	status = sdioh_interrupt_set(bcmsdh->sdioh, FALSE);
++	return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
++}
++
++int
++bcmsdh_intr_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	ASSERT(bcmsdh);
++
++	status = sdioh_interrupt_register(bcmsdh->sdioh, fn, argh);
++	return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
++}
++
++int
++bcmsdh_intr_dereg(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	ASSERT(bcmsdh);
++
++	status = sdioh_interrupt_deregister(bcmsdh->sdioh);
++	return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
++}
++
++#if defined(DHD_DEBUG)
++bool
++bcmsdh_intr_pending(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	ASSERT(sdh);
++	return sdioh_interrupt_pending(bcmsdh->sdioh);
++}
++#endif
++
++
++int
++bcmsdh_devremove_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh)
++{
++	ASSERT(sdh);
++
++	/* don't support yet */
++	return BCME_UNSUPPORTED;
++}
++
++/**
++ * Read from SDIO Configuration Space
++ * @param sdh SDIO Host context.
++ * @param func_num Function number to read from.
++ * @param addr Address to read from.
++ * @param err Error return.
++ * @return value read from SDIO configuration space.
++ */
++uint8
++bcmsdh_cfg_read(void *sdh, uint fnc_num, uint32 addr, int *err)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
++	int32 retry = 0;
++#endif
++	uint8 data = 0;
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	ASSERT(bcmsdh->init_success);
++
++#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
++	do {
++		if (retry)	/* wait for 1 ms till bus get settled down */
++			OSL_DELAY(1000);
++#endif
++	status = sdioh_cfg_read(bcmsdh->sdioh, fnc_num, addr, (uint8 *)&data);
++#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
++	} while (!SDIOH_API_SUCCESS(status) && (retry++ < SDIOH_API_ACCESS_RETRY_LIMIT));
++#endif
++	if (err)
++		*err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
++
++	BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, uint8data = 0x%x\n", __FUNCTION__,
++	            fnc_num, addr, data));
++
++	return data;
++}
++
++void
++bcmsdh_cfg_write(void *sdh, uint fnc_num, uint32 addr, uint8 data, int *err)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
++	int32 retry = 0;
++#endif
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	ASSERT(bcmsdh->init_success);
++
++#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
++	do {
++		if (retry)	/* wait for 1 ms till bus get settled down */
++			OSL_DELAY(1000);
++#endif
++	status = sdioh_cfg_write(bcmsdh->sdioh, fnc_num, addr, (uint8 *)&data);
++#ifdef SDIOH_API_ACCESS_RETRY_LIMIT
++	} while (!SDIOH_API_SUCCESS(status) && (retry++ < SDIOH_API_ACCESS_RETRY_LIMIT));
++#endif
++	if (err)
++		*err = SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR;
++
++	BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, uint8data = 0x%x\n", __FUNCTION__,
++	            fnc_num, addr, data));
++}
++
++uint32
++bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr, int *err)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	uint32 data = 0;
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	ASSERT(bcmsdh->init_success);
++
++	status = sdioh_request_word(bcmsdh->sdioh, SDIOH_CMD_TYPE_NORMAL, SDIOH_READ, fnc_num,
++	                            addr, &data, 4);
++
++	if (err)
++		*err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
++
++	BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, uint32data = 0x%x\n", __FUNCTION__,
++	            fnc_num, addr, data));
++
++	return data;
++}
++
++void
++bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr, uint32 data, int *err)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	ASSERT(bcmsdh->init_success);
++
++	status = sdioh_request_word(bcmsdh->sdioh, SDIOH_CMD_TYPE_NORMAL, SDIOH_WRITE, fnc_num,
++	                            addr, &data, 4);
++
++	if (err)
++		*err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
++
++	BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, uint32data = 0x%x\n", __FUNCTION__, fnc_num,
++	             addr, data));
++}
++
++
++int
++bcmsdh_cis_read(void *sdh, uint func, uint8 *cis, uint length)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++
++	uint8 *tmp_buf, *tmp_ptr;
++	uint8 *ptr;
++	bool ascii = func & ~0xf;
++	func &= 0x7;
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	ASSERT(bcmsdh->init_success);
++	ASSERT(cis);
++	ASSERT(length <= SBSDIO_CIS_SIZE_LIMIT);
++
++	status = sdioh_cis_read(bcmsdh->sdioh, func, cis, length);
++
++	if (ascii) {
++		/* Move binary bits to tmp and format them into the provided buffer. */
++		if ((tmp_buf = (uint8 *)MALLOC(bcmsdh->osh, length)) == NULL) {
++			BCMSDH_ERROR(("%s: out of memory\n", __FUNCTION__));
++			return BCME_NOMEM;
++		}
++		bcopy(cis, tmp_buf, length);
++		for (tmp_ptr = tmp_buf, ptr = cis; ptr < (cis + length - 4); tmp_ptr++) {
++			ptr += snprintf((char*)ptr, (cis + length - ptr - 4),
++				"%.2x ", *tmp_ptr & 0xff);
++			if ((((tmp_ptr - tmp_buf) + 1) & 0xf) == 0)
++				ptr += snprintf((char *)ptr, (cis + length - ptr -4), "\n");
++		}
++		MFREE(bcmsdh->osh, tmp_buf, length);
++	}
++
++	return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
++}
++
++
++int
++bcmsdhsdio_set_sbaddr_window(void *sdh, uint32 address, bool force_set)
++{
++	int err = 0;
++	uint bar0 = address & ~SBSDIO_SB_OFT_ADDR_MASK;
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	if (bar0 != bcmsdh->sbwad || force_set) {
++		bcmsdh_cfg_write(bcmsdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
++			(address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
++		if (!err)
++			bcmsdh_cfg_write(bcmsdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
++				(address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
++		if (!err)
++			bcmsdh_cfg_write(bcmsdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
++				(address >> 24) & SBSDIO_SBADDRHIGH_MASK, &err);
++
++		if (!err)
++			bcmsdh->sbwad = bar0;
++		else
++			/* invalidate cached window var */
++			bcmsdh->sbwad = 0;
++
++	}
++
++	return err;
++}
++
++uint32
++bcmsdh_reg_read(void *sdh, uint32 addr, uint size)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	uint32 word = 0;
++
++	BCMSDH_INFO(("%s:fun = 1, addr = 0x%x, ", __FUNCTION__, addr));
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	ASSERT(bcmsdh->init_success);
++
++	if (bcmsdhsdio_set_sbaddr_window(bcmsdh, addr, bcmsdh->force_sbwad_calc))
++		return 0xFFFFFFFF;
++
++	addr &= SBSDIO_SB_OFT_ADDR_MASK;
++	if (size == 4)
++		addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
++
++	status = sdioh_request_word(bcmsdh->sdioh, SDIOH_CMD_TYPE_NORMAL,
++		SDIOH_READ, SDIO_FUNC_1, addr, &word, size);
++
++	bcmsdh->regfail = !(SDIOH_API_SUCCESS(status));
++
++	BCMSDH_INFO(("uint32data = 0x%x\n", word));
++
++	/* if ok, return appropriately masked word */
++	if (SDIOH_API_SUCCESS(status)) {
++		switch (size) {
++			case sizeof(uint8):
++				return (word & 0xff);
++			case sizeof(uint16):
++				return (word & 0xffff);
++			case sizeof(uint32):
++				return word;
++			default:
++				bcmsdh->regfail = TRUE;
++
++		}
++	}
++
++	/* otherwise, bad sdio access or invalid size */
++	BCMSDH_ERROR(("%s: error reading addr 0x%04x size %d\n", __FUNCTION__, addr, size));
++	return 0xFFFFFFFF;
++}
++
++uint32
++bcmsdh_reg_write(void *sdh, uint32 addr, uint size, uint32 data)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	int err = 0;
++
++	BCMSDH_INFO(("%s:fun = 1, addr = 0x%x, uint%ddata = 0x%x\n",
++	             __FUNCTION__, addr, size*8, data));
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	ASSERT(bcmsdh->init_success);
++
++	if ((err = bcmsdhsdio_set_sbaddr_window(bcmsdh, addr, bcmsdh->force_sbwad_calc)))
++		return err;
++
++	addr &= SBSDIO_SB_OFT_ADDR_MASK;
++	if (size == 4)
++		addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
++	status = sdioh_request_word(bcmsdh->sdioh, SDIOH_CMD_TYPE_NORMAL, SDIOH_WRITE, SDIO_FUNC_1,
++	                            addr, &data, size);
++	bcmsdh->regfail = !(SDIOH_API_SUCCESS(status));
++
++	if (SDIOH_API_SUCCESS(status))
++		return 0;
++
++	BCMSDH_ERROR(("%s: error writing 0x%08x to addr 0x%04x size %d\n",
++	              __FUNCTION__, data, addr, size));
++	return 0xFFFFFFFF;
++}
++
++bool
++bcmsdh_regfail(void *sdh)
++{
++	return ((bcmsdh_info_t *)sdh)->regfail;
++}
++
++int
++bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags,
++                uint8 *buf, uint nbytes, void *pkt,
++                bcmsdh_cmplt_fn_t complete_fn, void *handle)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	uint incr_fix;
++	uint width;
++	int err = 0;
++
++	ASSERT(bcmsdh);
++	ASSERT(bcmsdh->init_success);
++
++	BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, size = %d\n",
++	             __FUNCTION__, fn, addr, nbytes));
++
++	/* Async not implemented yet */
++	ASSERT(!(flags & SDIO_REQ_ASYNC));
++	if (flags & SDIO_REQ_ASYNC)
++		return BCME_UNSUPPORTED;
++
++	if ((err = bcmsdhsdio_set_sbaddr_window(bcmsdh, addr, FALSE)))
++		return err;
++
++	addr &= SBSDIO_SB_OFT_ADDR_MASK;
++
++	incr_fix = (flags & SDIO_REQ_FIXED) ? SDIOH_DATA_FIX : SDIOH_DATA_INC;
++	width = (flags & SDIO_REQ_4BYTE) ? 4 : 2;
++	if (width == 4)
++		addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
++
++	status = sdioh_request_buffer(bcmsdh->sdioh, SDIOH_DATA_PIO, incr_fix,
++	                              SDIOH_READ, fn, addr, width, nbytes, buf, pkt);
++
++	return (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
++}
++
++int
++bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags,
++                uint8 *buf, uint nbytes, void *pkt,
++                bcmsdh_cmplt_fn_t complete_fn, void *handle)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++	uint incr_fix;
++	uint width;
++	int err = 0;
++
++	ASSERT(bcmsdh);
++	ASSERT(bcmsdh->init_success);
++
++	BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, size = %d\n",
++	            __FUNCTION__, fn, addr, nbytes));
++
++	/* Async not implemented yet */
++	ASSERT(!(flags & SDIO_REQ_ASYNC));
++	if (flags & SDIO_REQ_ASYNC)
++		return BCME_UNSUPPORTED;
++
++	if ((err = bcmsdhsdio_set_sbaddr_window(bcmsdh, addr, FALSE)))
++		return err;
++
++	addr &= SBSDIO_SB_OFT_ADDR_MASK;
++
++	incr_fix = (flags & SDIO_REQ_FIXED) ? SDIOH_DATA_FIX : SDIOH_DATA_INC;
++	width = (flags & SDIO_REQ_4BYTE) ? 4 : 2;
++	if (width == 4)
++		addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
++
++	status = sdioh_request_buffer(bcmsdh->sdioh, SDIOH_DATA_PIO, incr_fix,
++	                              SDIOH_WRITE, fn, addr, width, nbytes, buf, pkt);
++
++	return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
++}
++
++int
++bcmsdh_rwdata(void *sdh, uint rw, uint32 addr, uint8 *buf, uint nbytes)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	SDIOH_API_RC status;
++
++	ASSERT(bcmsdh);
++	ASSERT(bcmsdh->init_success);
++	ASSERT((addr & SBSDIO_SBWINDOW_MASK) == 0);
++
++	addr &= SBSDIO_SB_OFT_ADDR_MASK;
++	addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
++
++	status = sdioh_request_buffer(bcmsdh->sdioh, SDIOH_DATA_PIO, SDIOH_DATA_INC,
++	                              (rw ? SDIOH_WRITE : SDIOH_READ), SDIO_FUNC_1,
++	                              addr, 4, nbytes, buf, NULL);
++
++	return (SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR);
++}
++
++int
++bcmsdh_abort(void *sdh, uint fn)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	return sdioh_abort(bcmsdh->sdioh, fn);
++}
++
++int
++bcmsdh_start(void *sdh, int stage)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	return sdioh_start(bcmsdh->sdioh, stage);
++}
++
++int
++bcmsdh_stop(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	return sdioh_stop(bcmsdh->sdioh);
++}
++
++int
++bcmsdh_waitlockfree(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	return sdioh_waitlockfree(bcmsdh->sdioh);
++}
++
++
++int
++bcmsdh_query_device(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++	bcmsdh->vendevid = (VENDOR_BROADCOM << 16) | 0;
++	return (bcmsdh->vendevid);
++}
++
++uint
++bcmsdh_query_iofnum(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	return (sdioh_query_iofnum(bcmsdh->sdioh));
++}
++
++int
++bcmsdh_reset(bcmsdh_info_t *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	return sdioh_sdio_reset(bcmsdh->sdioh);
++}
++
++void *bcmsdh_get_sdioh(bcmsdh_info_t *sdh)
++{
++	ASSERT(sdh);
++	return sdh->sdioh;
++}
++
++/* Function to pass device-status bits to DHD. */
++uint32
++bcmsdh_get_dstatus(void *sdh)
++{
++	return 0;
++}
++uint32
++bcmsdh_cur_sbwad(void *sdh)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++
++	return (bcmsdh->sbwad);
++}
++
++/* example usage: if force is TRUE, forces the bcmsdhsdio_set_sbaddr_window to
++ * calculate sbwad always instead of caching.
++ */
++void
++bcmsdh_force_sbwad_calc(void *sdh, bool force)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)sdh;
++
++	if (!bcmsdh)
++		bcmsdh = l_bcmsdh;
++	bcmsdh->force_sbwad_calc = force;
++}
++
++void
++bcmsdh_chipinfo(void *sdh, uint32 chip, uint32 chiprev)
++{
++	return;
++}
++
++
++int
++bcmsdh_sleep(void *sdh, bool enab)
++{
++#ifdef SDIOH_SLEEP_ENABLED
++	bcmsdh_info_t *p = (bcmsdh_info_t *)sdh;
++	sdioh_info_t *sd = (sdioh_info_t *)(p->sdioh);
++
++	return sdioh_sleep(sd, enab);
++#else
++	return BCME_UNSUPPORTED;
++#endif
++}
++
++int
++bcmsdh_gpio_init(void *sdh)
++{
++	bcmsdh_info_t *p = (bcmsdh_info_t *)sdh;
++	sdioh_info_t *sd = (sdioh_info_t *)(p->sdioh);
++
++	return sdioh_gpio_init(sd);
++}
++
++bool
++bcmsdh_gpioin(void *sdh, uint32 gpio)
++{
++	bcmsdh_info_t *p = (bcmsdh_info_t *)sdh;
++	sdioh_info_t *sd = (sdioh_info_t *)(p->sdioh);
++
++	return sdioh_gpioin(sd, gpio);
++}
++
++int
++bcmsdh_gpioouten(void *sdh, uint32 gpio)
++{
++	bcmsdh_info_t *p = (bcmsdh_info_t *)sdh;
++	sdioh_info_t *sd = (sdioh_info_t *)(p->sdioh);
++
++	return sdioh_gpioouten(sd, gpio);
++}
++
++int
++bcmsdh_gpioout(void *sdh, uint32 gpio, bool enab)
++{
++	bcmsdh_info_t *p = (bcmsdh_info_t *)sdh;
++	sdioh_info_t *sd = (sdioh_info_t *)(p->sdioh);
++
++	return sdioh_gpioout(sd, gpio, enab);
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmsdh_linux.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmsdh_linux.c
+new file mode 100644
+index 000000000..7e9d04994
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmsdh_linux.c
+@@ -0,0 +1,471 @@
++/*
++ * SDIO access interface for drivers - linux specific (pci only)
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmsdh_linux.c 579798 2015-08-17 07:00:05Z $
++ */
++
++/**
++ * @file bcmsdh_linux.c
++ */
++
++#define __UNDEF_NO_VERSION__
++
++#include <typedefs.h>
++#include <linuxver.h>
++#include <linux/pci.h>
++#include <linux/completion.h>
++
++#include <osl.h>
++#include <pcicfg.h>
++#include <bcmdefs.h>
++#include <bcmdevs.h>
++#include <linux/irq.h>
++extern void dhdsdio_isr(void * args);
++#include <bcmutils.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#if defined(CONFIG_ARCH_ODIN)
++#include <linux/platform_data/gpio-odin.h>
++#endif /* defined(CONFIG_ARCH_ODIN) */
++#include <dhd_linux.h>
++
++/* driver info, initialized when bcmsdh_register is called */
++static bcmsdh_driver_t drvinfo = {NULL, NULL, NULL, NULL};
++
++typedef enum {
++	DHD_INTR_INVALID = 0,
++	DHD_INTR_INBAND,
++	DHD_INTR_HWOOB,
++	DHD_INTR_SWOOB
++} DHD_HOST_INTR_TYPE;
++
++/* the BCMSDH module comprises the generic part (bcmsdh.c) and OS specific layer (e.g.
++ * bcmsdh_linux.c). Put all OS specific variables (e.g. irq number and flags) here rather
++ * than in the common structure bcmsdh_info. bcmsdh_info only keeps a handle (os_ctx) to this
++ * structure.
++ */
++typedef struct bcmsdh_os_info {
++	DHD_HOST_INTR_TYPE	intr_type;
++	int			oob_irq_num;	/* valid when hardware or software oob in use */
++	unsigned long		oob_irq_flags;	/* valid when hardware or software oob in use */
++	bool			oob_irq_registered;
++	bool			oob_irq_enabled;
++	bool			oob_irq_wake_enabled;
++	spinlock_t		oob_irq_spinlock;
++	bcmsdh_cb_fn_t		oob_irq_handler;
++	void			*oob_irq_handler_context;
++	void			*context;	/* context returned from upper layer */
++	void			*sdioh;		/* handle to lower layer (sdioh) */
++	void			*dev;		/* handle to the underlying device */
++	bool			dev_wake_enabled;
++} bcmsdh_os_info_t;
++
++/* debugging macros */
++#define SDLX_MSG(x)
++
++/**
++ * Checks to see if vendor and device IDs match a supported SDIO Host Controller.
++ */
++bool
++bcmsdh_chipmatch(uint16 vendor, uint16 device)
++{
++	/* Add other vendors and devices as required */
++
++#ifdef BCMSDIOH_STD
++	/* Check for Arasan host controller */
++	if (vendor == VENDOR_SI_IMAGE) {
++		return (TRUE);
++	}
++	/* Check for BRCM 27XX Standard host controller */
++	if (device == BCM27XX_SDIOH_ID && vendor == VENDOR_BROADCOM) {
++		return (TRUE);
++	}
++	/* Check for BRCM Standard host controller */
++	if (device == SDIOH_FPGA_ID && vendor == VENDOR_BROADCOM) {
++		return (TRUE);
++	}
++	/* Check for TI PCIxx21 Standard host controller */
++	if (device == PCIXX21_SDIOH_ID && vendor == VENDOR_TI) {
++		return (TRUE);
++	}
++	if (device == PCIXX21_SDIOH0_ID && vendor == VENDOR_TI) {
++		return (TRUE);
++	}
++	/* Ricoh R5C822 Standard SDIO Host */
++	if (device == R5C822_SDIOH_ID && vendor == VENDOR_RICOH) {
++		return (TRUE);
++	}
++	/* JMicron Standard SDIO Host */
++	if (device == JMICRON_SDIOH_ID && vendor == VENDOR_JMICRON) {
++		return (TRUE);
++	}
++
++#endif /* BCMSDIOH_STD */
++#ifdef BCMSDIOH_SPI
++	/* This is the PciSpiHost. */
++	if (device == SPIH_FPGA_ID && vendor == VENDOR_BROADCOM) {
++		printf("Found PCI SPI Host Controller\n");
++		return (TRUE);
++	}
++
++#endif /* BCMSDIOH_SPI */
++
++	return (FALSE);
++}
++
++void* bcmsdh_probe(osl_t *osh, void *dev, void *sdioh, void *adapter_info, uint bus_type,
++	uint bus_num, uint slot_num)
++{
++	ulong regs;
++	bcmsdh_info_t *bcmsdh;
++	uint32 vendevid;
++	bcmsdh_os_info_t *bcmsdh_osinfo = NULL;
++
++	bcmsdh = bcmsdh_attach(osh, sdioh, &regs);
++	if (bcmsdh == NULL) {
++		SDLX_MSG(("%s: bcmsdh_attach failed\n", __FUNCTION__));
++		goto err;
++	}
++	bcmsdh_osinfo = MALLOC(osh, sizeof(bcmsdh_os_info_t));
++	if (bcmsdh_osinfo == NULL) {
++		SDLX_MSG(("%s: failed to allocate bcmsdh_os_info_t\n", __FUNCTION__));
++		goto err;
++	}
++	bzero((char *)bcmsdh_osinfo, sizeof(bcmsdh_os_info_t));
++	bcmsdh->os_cxt = bcmsdh_osinfo;
++	bcmsdh_osinfo->sdioh = sdioh;
++	bcmsdh_osinfo->dev = dev;
++	osl_set_bus_handle(osh, bcmsdh);
++
++#if !defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++	if (dev && device_init_wakeup(dev, true) == 0)
++		bcmsdh_osinfo->dev_wake_enabled = TRUE;
++#endif /* !defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36)) */
++
++#if defined(OOB_INTR_ONLY)
++	spin_lock_init(&bcmsdh_osinfo->oob_irq_spinlock);
++	/* Get customer specific OOB IRQ parametres: IRQ number as IRQ type */
++	bcmsdh_osinfo->oob_irq_num = wifi_platform_get_irq_number(adapter_info,
++		&bcmsdh_osinfo->oob_irq_flags);
++	if  (bcmsdh_osinfo->oob_irq_num < 0) {
++		SDLX_MSG(("%s: Host OOB irq is not defined\n", __FUNCTION__));
++		goto err;
++	}
++#endif /* defined(BCMLXSDMMC) */
++
++	/* Read the vendor/device ID from the CIS */
++	vendevid = bcmsdh_query_device(bcmsdh);
++	/* try to attach to the target device */
++	bcmsdh_osinfo->context = drvinfo.probe((vendevid >> 16), (vendevid & 0xFFFF), bus_num,
++		slot_num, 0, bus_type, (void *)regs, osh, bcmsdh);
++	if (bcmsdh_osinfo->context == NULL) {
++		SDLX_MSG(("%s: device attach failed\n", __FUNCTION__));
++		goto err;
++	}
++
++	return bcmsdh;
++
++	/* error handling */
++err:
++	if (bcmsdh != NULL)
++		bcmsdh_detach(osh, bcmsdh);
++	if (bcmsdh_osinfo != NULL)
++		MFREE(osh, bcmsdh_osinfo, sizeof(bcmsdh_os_info_t));
++	return NULL;
++}
++
++int bcmsdh_remove(bcmsdh_info_t *bcmsdh)
++{
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++
++#if !defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++	if (bcmsdh_osinfo->dev)
++		device_init_wakeup(bcmsdh_osinfo->dev, false);
++	bcmsdh_osinfo->dev_wake_enabled = FALSE;
++#endif /* !defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36)) */
++
++	drvinfo.remove(bcmsdh_osinfo->context);
++	MFREE(bcmsdh->osh, bcmsdh->os_cxt, sizeof(bcmsdh_os_info_t));
++	bcmsdh_detach(bcmsdh->osh, bcmsdh);
++
++	return 0;
++}
++
++int bcmsdh_suspend(bcmsdh_info_t *bcmsdh)
++{
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++
++	if (drvinfo.suspend && drvinfo.suspend(bcmsdh_osinfo->context))
++		return -EBUSY;
++	return 0;
++}
++
++int bcmsdh_resume(bcmsdh_info_t *bcmsdh)
++{
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++
++	if (drvinfo.resume)
++		return drvinfo.resume(bcmsdh_osinfo->context);
++	return 0;
++}
++
++extern int bcmsdh_register_client_driver(void);
++extern void bcmsdh_unregister_client_driver(void);
++extern int sdio_func_reg_notify(void* semaphore);
++extern void sdio_func_unreg_notify(void);
++
++#if defined(BCMLXSDMMC)
++int bcmsdh_reg_sdio_notify(void* semaphore)
++{
++	return sdio_func_reg_notify(semaphore);
++}
++
++void bcmsdh_unreg_sdio_notify(void)
++{
++	sdio_func_unreg_notify();
++}
++#endif /* defined(BCMLXSDMMC) */
++
++int
++bcmsdh_register(bcmsdh_driver_t *driver)
++{
++	int error = 0;
++
++	drvinfo = *driver;
++	SDLX_MSG(("%s: register client driver\n", __FUNCTION__));
++	error = bcmsdh_register_client_driver();
++	if (error)
++		SDLX_MSG(("%s: failed %d\n", __FUNCTION__, error));
++
++	return error;
++}
++
++void
++bcmsdh_unregister(void)
++{
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
++		if (bcmsdh_pci_driver.node.next == NULL)
++			return;
++#endif
++
++	bcmsdh_unregister_client_driver();
++}
++
++void bcmsdh_dev_pm_stay_awake(bcmsdh_info_t *bcmsdh)
++{
++#if !defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++	pm_stay_awake(bcmsdh_osinfo->dev);
++#endif /* !defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36)) */
++}
++
++void bcmsdh_dev_relax(bcmsdh_info_t *bcmsdh)
++{
++#if !defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++	pm_relax(bcmsdh_osinfo->dev);
++#endif /* !defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36)) */
++}
++
++bool bcmsdh_dev_pm_enabled(bcmsdh_info_t *bcmsdh)
++{
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++
++	return bcmsdh_osinfo->dev_wake_enabled;
++}
++
++#if defined(OOB_INTR_ONLY)
++void bcmsdh_oob_intr_set(bcmsdh_info_t *bcmsdh, bool enable)
++{
++	unsigned long flags;
++	bcmsdh_os_info_t *bcmsdh_osinfo;
++
++	if (!bcmsdh)
++		return;
++
++	bcmsdh_osinfo = bcmsdh->os_cxt;
++	spin_lock_irqsave(&bcmsdh_osinfo->oob_irq_spinlock, flags);
++	if (bcmsdh_osinfo->oob_irq_enabled != enable) {
++		if (enable)
++			enable_irq(bcmsdh_osinfo->oob_irq_num);
++		else
++			disable_irq_nosync(bcmsdh_osinfo->oob_irq_num);
++		bcmsdh_osinfo->oob_irq_enabled = enable;
++	}
++	spin_unlock_irqrestore(&bcmsdh_osinfo->oob_irq_spinlock, flags);
++}
++
++static irqreturn_t wlan_oob_irq(int irq, void *dev_id)
++{
++	bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *)dev_id;
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++
++	bcmsdh_oob_intr_set(bcmsdh, FALSE);
++	bcmsdh_osinfo->oob_irq_handler(bcmsdh_osinfo->oob_irq_handler_context);
++
++	return IRQ_HANDLED;
++}
++
++int bcmsdh_oob_intr_register(bcmsdh_info_t *bcmsdh, bcmsdh_cb_fn_t oob_irq_handler,
++	void* oob_irq_handler_context)
++{
++	int err = 0;
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++
++	SDLX_MSG(("%s: Enter\n", __FUNCTION__));
++	if (bcmsdh_osinfo->oob_irq_registered) {
++		SDLX_MSG(("%s: irq is already registered\n", __FUNCTION__));
++		return -EBUSY;
++	}
++	SDLX_MSG(("%s OOB irq=%d flags=%X \n", __FUNCTION__,
++		(int)bcmsdh_osinfo->oob_irq_num, (int)bcmsdh_osinfo->oob_irq_flags));
++	bcmsdh_osinfo->oob_irq_handler = oob_irq_handler;
++	bcmsdh_osinfo->oob_irq_handler_context = oob_irq_handler_context;
++#if defined(CONFIG_ARCH_ODIN)
++	err = odin_gpio_sms_request_irq(bcmsdh_osinfo->oob_irq_num, wlan_oob_irq,
++		bcmsdh_osinfo->oob_irq_flags, "bcmsdh_sdmmc", bcmsdh);
++#else
++	err = request_irq(bcmsdh_osinfo->oob_irq_num, wlan_oob_irq,
++		bcmsdh_osinfo->oob_irq_flags, "bcmsdh_sdmmc", bcmsdh);
++#endif /* defined(CONFIG_ARCH_ODIN) */
++	if (err) {
++		SDLX_MSG(("%s: request_irq failed with %d\n", __FUNCTION__, err));
++		return err;
++	}
++
++		err = enable_irq_wake(bcmsdh_osinfo->oob_irq_num);
++		if (!err)
++			bcmsdh_osinfo->oob_irq_wake_enabled = TRUE;
++	bcmsdh_osinfo->oob_irq_enabled = TRUE;
++	bcmsdh_osinfo->oob_irq_registered = TRUE;
++	return err;
++}
++
++void bcmsdh_oob_intr_unregister(bcmsdh_info_t *bcmsdh)
++{
++	int err = 0;
++	bcmsdh_os_info_t *bcmsdh_osinfo = bcmsdh->os_cxt;
++
++	SDLX_MSG(("%s: Enter\n", __FUNCTION__));
++	if (!bcmsdh_osinfo->oob_irq_registered) {
++		SDLX_MSG(("%s: irq is not registered\n", __FUNCTION__));
++		return;
++	}
++	if (bcmsdh_osinfo->oob_irq_wake_enabled) {
++			err = disable_irq_wake(bcmsdh_osinfo->oob_irq_num);
++			if (!err)
++				bcmsdh_osinfo->oob_irq_wake_enabled = FALSE;
++	}
++	if (bcmsdh_osinfo->oob_irq_enabled) {
++		disable_irq(bcmsdh_osinfo->oob_irq_num);
++		bcmsdh_osinfo->oob_irq_enabled = FALSE;
++	}
++	free_irq(bcmsdh_osinfo->oob_irq_num, bcmsdh);
++	bcmsdh_osinfo->oob_irq_registered = FALSE;
++}
++#endif 
++
++/* Module parameters specific to each host-controller driver */
++
++extern uint sd_msglevel;	/* Debug message level */
++module_param(sd_msglevel, uint, 0);
++
++extern uint sd_power;	/* 0 = SD Power OFF, 1 = SD Power ON. */
++module_param(sd_power, uint, 0);
++
++extern uint sd_clock;	/* SD Clock Control, 0 = SD Clock OFF, 1 = SD Clock ON */
++module_param(sd_clock, uint, 0);
++
++extern uint sd_divisor;	/* Divisor (-1 means external clock) */
++module_param(sd_divisor, uint, 0);
++
++extern uint sd_sdmode;	/* Default is SD4, 0=SPI, 1=SD1, 2=SD4 */
++module_param(sd_sdmode, uint, 0);
++
++extern uint sd_hiok;	/* Ok to use hi-speed mode */
++module_param(sd_hiok, uint, 0);
++
++extern uint sd_f2_blocksize;
++module_param(sd_f2_blocksize, int, 0);
++
++extern uint sd_f1_blocksize;
++module_param(sd_f1_blocksize, int, 0);
++
++#ifdef BCMSDIOH_STD
++extern int sd_uhsimode;
++module_param(sd_uhsimode, int, 0);
++extern uint sd_tuning_period;
++module_param(sd_tuning_period, uint, 0);
++extern int sd_delay_value;
++module_param(sd_delay_value, uint, 0);
++
++/* SDIO Drive Strength for UHSI mode specific to SDIO3.0 */
++extern char dhd_sdiod_uhsi_ds_override[2];
++module_param_string(dhd_sdiod_uhsi_ds_override, dhd_sdiod_uhsi_ds_override, 2, 0);
++
++#endif
++
++#ifdef BCMSDH_MODULE
++EXPORT_SYMBOL(bcmsdh_attach);
++EXPORT_SYMBOL(bcmsdh_detach);
++EXPORT_SYMBOL(bcmsdh_intr_query);
++EXPORT_SYMBOL(bcmsdh_intr_enable);
++EXPORT_SYMBOL(bcmsdh_intr_disable);
++EXPORT_SYMBOL(bcmsdh_intr_reg);
++EXPORT_SYMBOL(bcmsdh_intr_dereg);
++
++#if defined(DHD_DEBUG)
++EXPORT_SYMBOL(bcmsdh_intr_pending);
++#endif
++
++EXPORT_SYMBOL(bcmsdh_devremove_reg);
++EXPORT_SYMBOL(bcmsdh_cfg_read);
++EXPORT_SYMBOL(bcmsdh_cfg_write);
++EXPORT_SYMBOL(bcmsdh_cis_read);
++EXPORT_SYMBOL(bcmsdh_reg_read);
++EXPORT_SYMBOL(bcmsdh_reg_write);
++EXPORT_SYMBOL(bcmsdh_regfail);
++EXPORT_SYMBOL(bcmsdh_send_buf);
++EXPORT_SYMBOL(bcmsdh_recv_buf);
++
++EXPORT_SYMBOL(bcmsdh_rwdata);
++EXPORT_SYMBOL(bcmsdh_abort);
++EXPORT_SYMBOL(bcmsdh_query_device);
++EXPORT_SYMBOL(bcmsdh_query_iofnum);
++EXPORT_SYMBOL(bcmsdh_iovar_op);
++EXPORT_SYMBOL(bcmsdh_register);
++EXPORT_SYMBOL(bcmsdh_unregister);
++EXPORT_SYMBOL(bcmsdh_chipmatch);
++EXPORT_SYMBOL(bcmsdh_reset);
++EXPORT_SYMBOL(bcmsdh_waitlockfree);
++
++EXPORT_SYMBOL(bcmsdh_get_dstatus);
++EXPORT_SYMBOL(bcmsdh_cfg_read_word);
++EXPORT_SYMBOL(bcmsdh_cfg_write_word);
++EXPORT_SYMBOL(bcmsdh_cur_sbwad);
++EXPORT_SYMBOL(bcmsdh_chipinfo);
++
++#endif /* BCMSDH_MODULE */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmsdh_sdmmc.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmsdh_sdmmc.c
+new file mode 100644
+index 000000000..2135db8ac
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmsdh_sdmmc.c
+@@ -0,0 +1,1536 @@
++/*
++ * BCMSDH Function Driver for the native SDIO/MMC driver in the Linux Kernel
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Proprietary,Open:>>
++ *
++ * $Id: bcmsdh_sdmmc.c 712404 2019-03-20 06:20:25Z $
++ */
++#include <typedefs.h>
++
++#include <bcmdevs.h>
++#include <bcmendian.h>
++#include <bcmutils.h>
++#include <osl.h>
++#include <sdio.h>	/* SDIO Device and Protocol Specs */
++#include <sdioh.h>	/* Standard SDIO Host Controller Specification */
++#include <bcmsdbus.h>	/* bcmsdh to/from specific controller APIs */
++#include <sdiovar.h>	/* ioctl/iovars */
++
++#include <linux/mmc/core.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/card.h>
++#include <linux/mmc/sdio_func.h>
++#include <linux/mmc/sdio_ids.h>
++
++#include <dngl_stats.h>
++#include <dhd.h>
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_PM_SLEEP)
++#include <linux/suspend.h>
++extern volatile bool dhd_mmc_suspend;
++#endif
++#include "bcmsdh_sdmmc.h"
++
++#ifndef BCMSDH_MODULE
++extern int sdio_function_init(void);
++extern void sdio_function_cleanup(void);
++#endif /* BCMSDH_MODULE */
++
++#if !defined(OOB_INTR_ONLY)
++static void IRQHandler(struct sdio_func *func);
++static void IRQHandlerF2(struct sdio_func *func);
++#endif /* !defined(OOB_INTR_ONLY) */
++static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, uint32 regaddr);
++
++#if defined(ANDROID_SDIO_RESET)
++extern int sdio_reset_comm(struct mmc_card *card);
++#else
++static int sdio_reset_comm(struct mmc_card *card)
++{
++	return 0;
++}
++#endif /* ANDROID_SDIO_RESET */
++
++#define DEFAULT_SDIO_F2_BLKSIZE		512
++#ifndef CUSTOM_SDIO_F2_BLKSIZE
++#define CUSTOM_SDIO_F2_BLKSIZE		DEFAULT_SDIO_F2_BLKSIZE
++#endif
++
++#define DEFAULT_SDIO_F1_BLKSIZE		64
++#ifndef CUSTOM_SDIO_F1_BLKSIZE
++#define CUSTOM_SDIO_F1_BLKSIZE		DEFAULT_SDIO_F1_BLKSIZE
++#endif
++
++#define MAX_IO_RW_EXTENDED_BLK		511
++
++uint sd_sdmode = SDIOH_MODE_SD4;	/* Use SD4 mode by default */
++uint sd_f2_blocksize = CUSTOM_SDIO_F2_BLKSIZE;
++uint sd_f1_blocksize = CUSTOM_SDIO_F1_BLKSIZE;
++uint sd_divisor = 2;			/* Default 48MHz/2 = 24MHz */
++
++uint sd_power = 1;		/* Default to SD Slot powered ON */
++uint sd_clock = 1;		/* Default to SD Clock turned ON */
++uint sd_hiok = FALSE;	/* Don't use hi-speed mode by default */
++uint sd_msglevel = 0x01;
++uint sd_use_dma = TRUE;
++
++#ifndef CUSTOM_RXCHAIN
++#define CUSTOM_RXCHAIN 0
++#endif
++
++/*  Enables host to dongle glomming. Also increases the
++ *  dma buffer size. This will increase the rx throughput
++ *  as there will be lesser CMD53 transactions
++ */
++#ifdef BCMSDIOH_TXGLOM
++uint sd_txglom = 1;
++module_param(sd_txglom, uint, 0664);
++#endif /* BCMSDIOH_TXGLOM */
++
++DHD_PM_RESUME_WAIT_INIT(sdioh_request_byte_wait);
++DHD_PM_RESUME_WAIT_INIT(sdioh_request_word_wait);
++DHD_PM_RESUME_WAIT_INIT(sdioh_request_packet_wait);
++DHD_PM_RESUME_WAIT_INIT(sdioh_request_buffer_wait);
++
++#define DMA_ALIGN_MASK	0x03
++#define MMC_SDIO_ABORT_RETRY_LIMIT 5
++
++int sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data);
++
++static int
++sdioh_sdmmc_card_enablefuncs(sdioh_info_t *sd)
++{
++	int err_ret;
++	uint32 fbraddr;
++	uint8 func;
++
++	sd_trace(("%s\n", __FUNCTION__));
++
++	/* Get the Card's common CIS address */
++	sd->com_cis_ptr = sdioh_sdmmc_get_cisaddr(sd, SDIOD_CCCR_CISPTR_0);
++	sd->func_cis_ptr[0] = sd->com_cis_ptr;
++	sd_info(("%s: Card's Common CIS Ptr = 0x%x\n", __FUNCTION__, sd->com_cis_ptr));
++
++	/* Get the Card's function CIS (for each function) */
++	for (fbraddr = SDIOD_FBR_STARTADDR, func = 1;
++	     func <= sd->num_funcs; func++, fbraddr += SDIOD_FBR_SIZE) {
++		sd->func_cis_ptr[func] = sdioh_sdmmc_get_cisaddr(sd, SDIOD_FBR_CISPTR_0 + fbraddr);
++		sd_info(("%s: Function %d CIS Ptr = 0x%x\n",
++		         __FUNCTION__, func, sd->func_cis_ptr[func]));
++	}
++
++	sd->func_cis_ptr[0] = sd->com_cis_ptr;
++	sd_info(("%s: Card's Common CIS Ptr = 0x%x\n", __FUNCTION__, sd->com_cis_ptr));
++
++	/* Enable Function 1 */
++	sdio_claim_host(sd->func[1]);
++	err_ret = sdio_enable_func(sd->func[1]);
++	sdio_release_host(sd->func[1]);
++	if (err_ret) {
++		sd_err(("bcmsdh_sdmmc: Failed to enable F1 Err: 0x%08x", err_ret));
++	}
++
++	return FALSE;
++}
++
++/*
++ *	Public entry points & extern's
++ */
++extern sdioh_info_t *
++sdioh_attach(osl_t *osh, struct sdio_func *func)
++{
++	sdioh_info_t *sd = NULL;
++	int err_ret;
++
++	sd_trace(("%s\n", __FUNCTION__));
++
++	if (func == NULL) {
++		sd_err(("%s: sdio function device is NULL\n", __FUNCTION__));
++		return NULL;
++	}
++
++	if ((sd = (sdioh_info_t *)MALLOC(osh, sizeof(sdioh_info_t))) == NULL) {
++		sd_err(("sdioh_attach: out of memory, malloced %d bytes\n", MALLOCED(osh)));
++		return NULL;
++	}
++	bzero((char *)sd, sizeof(sdioh_info_t));
++	sd->osh = osh;
++	sd->fake_func0.num = 0;
++	sd->fake_func0.card = func->card;
++	sd->func[0] = &sd->fake_func0;
++	sd->func[1] = func->card->sdio_func[0];
++	sd->func[2] = func->card->sdio_func[1];
++	sd->num_funcs = 2;
++	sd->sd_blockmode = TRUE;
++	sd->use_client_ints = TRUE;
++	sd->client_block_size[0] = 64;
++	sd->use_rxchain = CUSTOM_RXCHAIN;
++	if (sd->func[1] == NULL || sd->func[2] == NULL) {
++		sd_err(("%s: func 1 or 2 is null \n", __FUNCTION__));
++		goto fail;
++	}
++	sdio_set_drvdata(sd->func[1], sd);
++
++	sdio_claim_host(sd->func[1]);
++	sd->client_block_size[1] = sd_f1_blocksize;
++	err_ret = sdio_set_block_size(sd->func[1], sd_f1_blocksize);
++	sdio_release_host(sd->func[1]);
++	if (err_ret) {
++		sd_err(("bcmsdh_sdmmc: Failed to set F1 blocksize(%d)\n", err_ret));
++		goto fail;
++	}
++
++	sdio_claim_host(sd->func[2]);
++	sd->client_block_size[2] = sd_f2_blocksize;
++	err_ret = sdio_set_block_size(sd->func[2], sd_f2_blocksize);
++	sdio_release_host(sd->func[2]);
++	if (err_ret) {
++		sd_err(("bcmsdh_sdmmc: Failed to set F2 blocksize to %d(%d)\n",
++			sd_f2_blocksize, err_ret));
++		goto fail;
++	}
++
++	sdioh_sdmmc_card_enablefuncs(sd);
++
++	sd_trace(("%s: Done\n", __FUNCTION__));
++	return sd;
++
++fail:
++	MFREE(sd->osh, sd, sizeof(sdioh_info_t));
++	return NULL;
++}
++
++
++extern SDIOH_API_RC
++sdioh_detach(osl_t *osh, sdioh_info_t *sd)
++{
++	sd_trace(("%s\n", __FUNCTION__));
++
++	if (sd) {
++
++		/* Disable Function 2 */
++		if (sd->func[2]) {
++			sdio_claim_host(sd->func[2]);
++			sdio_disable_func(sd->func[2]);
++			sdio_release_host(sd->func[2]);
++		}
++
++		/* Disable Function 1 */
++		if (sd->func[1]) {
++			sdio_claim_host(sd->func[1]);
++			sdio_disable_func(sd->func[1]);
++			sdio_release_host(sd->func[1]);
++		}
++
++		sd->func[1] = NULL;
++		sd->func[2] = NULL;
++
++		MFREE(sd->osh, sd, sizeof(sdioh_info_t));
++	}
++	return SDIOH_API_RC_SUCCESS;
++}
++
++#if defined(OOB_INTR_ONLY) && defined(HW_OOB)
++
++extern SDIOH_API_RC
++sdioh_enable_func_intr(sdioh_info_t *sd)
++{
++	uint8 reg;
++	int err;
++
++	if (sd->func[0] == NULL) {
++		sd_err(("%s: function 0 pointer is NULL\n", __FUNCTION__));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	sdio_claim_host(sd->func[0]);
++	reg = sdio_readb(sd->func[0], SDIOD_CCCR_INTEN, &err);
++	if (err) {
++		sd_err(("%s: error for read SDIO_CCCR_IENx : 0x%x\n", __FUNCTION__, err));
++		sdio_release_host(sd->func[0]);
++		return SDIOH_API_RC_FAIL;
++	}
++	/* Enable F1 and F2 interrupts, clear master enable */
++	reg &= ~INTR_CTL_MASTER_EN;
++	reg |= (INTR_CTL_FUNC1_EN | INTR_CTL_FUNC2_EN);
++	sdio_writeb(sd->func[0], reg, SDIOD_CCCR_INTEN, &err);
++	sdio_release_host(sd->func[0]);
++
++	if (err) {
++		sd_err(("%s: error for write SDIO_CCCR_IENx : 0x%x\n", __FUNCTION__, err));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	return SDIOH_API_RC_SUCCESS;
++}
++
++extern SDIOH_API_RC
++sdioh_disable_func_intr(sdioh_info_t *sd)
++{
++	uint8 reg;
++	int err;
++
++	if (sd->func[0] == NULL) {
++		sd_err(("%s: function 0 pointer is NULL\n", __FUNCTION__));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	sdio_claim_host(sd->func[0]);
++	reg = sdio_readb(sd->func[0], SDIOD_CCCR_INTEN, &err);
++	if (err) {
++		sd_err(("%s: error for read SDIO_CCCR_IENx : 0x%x\n", __FUNCTION__, err));
++		sdio_release_host(sd->func[0]);
++		return SDIOH_API_RC_FAIL;
++	}
++	reg &= ~(INTR_CTL_FUNC1_EN | INTR_CTL_FUNC2_EN);
++	/* Disable master interrupt with the last function interrupt */
++	if (!(reg & 0xFE))
++		reg = 0;
++	sdio_writeb(sd->func[0], reg, SDIOD_CCCR_INTEN, &err);
++	sdio_release_host(sd->func[0]);
++
++	if (err) {
++		sd_err(("%s: error for write SDIO_CCCR_IENx : 0x%x\n", __FUNCTION__, err));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	return SDIOH_API_RC_SUCCESS;
++}
++#endif /* defined(OOB_INTR_ONLY) && defined(HW_OOB) */
++
++/* Configure callback to client when we recieve client interrupt */
++extern SDIOH_API_RC
++sdioh_interrupt_register(sdioh_info_t *sd, sdioh_cb_fn_t fn, void *argh)
++{
++	sd_trace(("%s: Entering\n", __FUNCTION__));
++	if (fn == NULL) {
++		sd_err(("%s: interrupt handler is NULL, not registering\n", __FUNCTION__));
++		return SDIOH_API_RC_FAIL;
++	}
++#if !defined(OOB_INTR_ONLY)
++	sd->intr_handler = fn;
++	sd->intr_handler_arg = argh;
++	sd->intr_handler_valid = TRUE;
++
++	/* register and unmask irq */
++	if (sd->func[2]) {
++		sdio_claim_host(sd->func[2]);
++		sdio_claim_irq(sd->func[2], IRQHandlerF2);
++		sdio_release_host(sd->func[2]);
++	}
++
++	if (sd->func[1]) {
++		sdio_claim_host(sd->func[1]);
++		sdio_claim_irq(sd->func[1], IRQHandler);
++		sdio_release_host(sd->func[1]);
++	}
++#elif defined(HW_OOB)
++	sdioh_enable_func_intr(sd);
++#endif /* !defined(OOB_INTR_ONLY) */
++
++	return SDIOH_API_RC_SUCCESS;
++}
++
++extern SDIOH_API_RC
++sdioh_interrupt_deregister(sdioh_info_t *sd)
++{
++	sd_trace(("%s: Entering\n", __FUNCTION__));
++
++#if !defined(OOB_INTR_ONLY)
++	if (sd->func[1]) {
++		/* register and unmask irq */
++		sdio_claim_host(sd->func[1]);
++		sdio_release_irq(sd->func[1]);
++		sdio_release_host(sd->func[1]);
++	}
++
++	if (sd->func[2]) {
++		/* Claim host controller F2 */
++		sdio_claim_host(sd->func[2]);
++		sdio_release_irq(sd->func[2]);
++		/* Release host controller F2 */
++		sdio_release_host(sd->func[2]);
++	}
++
++	sd->intr_handler_valid = FALSE;
++	sd->intr_handler = NULL;
++	sd->intr_handler_arg = NULL;
++#elif defined(HW_OOB)
++	sdioh_disable_func_intr(sd);
++#endif /* !defined(OOB_INTR_ONLY) */
++	return SDIOH_API_RC_SUCCESS;
++}
++
++extern SDIOH_API_RC
++sdioh_interrupt_query(sdioh_info_t *sd, bool *onoff)
++{
++	sd_trace(("%s: Entering\n", __FUNCTION__));
++	*onoff = sd->client_intr_enabled;
++	return SDIOH_API_RC_SUCCESS;
++}
++
++#if defined(DHD_DEBUG)
++extern bool
++sdioh_interrupt_pending(sdioh_info_t *sd)
++{
++	return (0);
++}
++#endif
++
++uint
++sdioh_query_iofnum(sdioh_info_t *sd)
++{
++	return sd->num_funcs;
++}
++
++/* IOVar table */
++enum {
++	IOV_MSGLEVEL = 1,
++	IOV_BLOCKMODE,
++	IOV_BLOCKSIZE,
++	IOV_DMA,
++	IOV_USEINTS,
++	IOV_NUMINTS,
++	IOV_NUMLOCALINTS,
++	IOV_HOSTREG,
++	IOV_DEVREG,
++	IOV_DIVISOR,
++	IOV_SDMODE,
++	IOV_HISPEED,
++	IOV_HCIREGS,
++	IOV_POWER,
++	IOV_CLOCK,
++	IOV_RXCHAIN
++};
++
++const bcm_iovar_t sdioh_iovars[] = {
++	{"sd_msglevel", IOV_MSGLEVEL,	0,	IOVT_UINT32,	0 },
++	{"sd_blockmode", IOV_BLOCKMODE, 0,	IOVT_BOOL,	0 },
++	{"sd_blocksize", IOV_BLOCKSIZE, 0,	IOVT_UINT32,	0 }, /* ((fn << 16) | size) */
++	{"sd_dma",	IOV_DMA,	0,	IOVT_BOOL,	0 },
++	{"sd_ints", 	IOV_USEINTS,	0,	IOVT_BOOL,	0 },
++	{"sd_numints",	IOV_NUMINTS,	0,	IOVT_UINT32,	0 },
++	{"sd_numlocalints", IOV_NUMLOCALINTS, 0, IOVT_UINT32,	0 },
++	{"sd_hostreg",	IOV_HOSTREG,	0,	IOVT_BUFFER,	sizeof(sdreg_t) },
++	{"sd_devreg",	IOV_DEVREG, 	0,	IOVT_BUFFER,	sizeof(sdreg_t) },
++	{"sd_divisor",	IOV_DIVISOR,	0,	IOVT_UINT32,	0 },
++	{"sd_power",	IOV_POWER,	0,	IOVT_UINT32,	0 },
++	{"sd_clock",	IOV_CLOCK,	0,	IOVT_UINT32,	0 },
++	{"sd_mode", 	IOV_SDMODE, 	0,	IOVT_UINT32,	100},
++	{"sd_highspeed", IOV_HISPEED,	0,	IOVT_UINT32,	0 },
++	{"sd_rxchain",  IOV_RXCHAIN,    0, 	IOVT_BOOL,	0 },
++	{NULL, 0, 0, 0, 0 }
++};
++
++int
++sdioh_iovar_op(sdioh_info_t *si, const char *name,
++                           void *params, int plen, void *arg, int len, bool set)
++{
++	const bcm_iovar_t *vi = NULL;
++	int bcmerror = 0;
++	int val_size;
++	int32 int_val = 0;
++	bool bool_val;
++	uint32 actionid;
++
++	ASSERT(name);
++	ASSERT(len >= 0);
++
++	/* Get must have return space; Set does not take qualifiers */
++	ASSERT(set || (arg && len));
++	ASSERT(!set || (!params && !plen));
++
++	sd_trace(("%s: Enter (%s %s)\n", __FUNCTION__, (set ? "set" : "get"), name));
++
++	if ((vi = bcm_iovar_lookup(sdioh_iovars, name)) == NULL) {
++		bcmerror = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++	if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, set)) != 0)
++		goto exit;
++
++	/* Set up params so get and set can share the convenience variables */
++	if (params == NULL) {
++		params = arg;
++		plen = len;
++	}
++
++	if (vi->type == IOVT_VOID)
++		val_size = 0;
++	else if (vi->type == IOVT_BUFFER)
++		val_size = len;
++	else
++		val_size = sizeof(int);
++
++	if (plen >= (int)sizeof(int_val))
++		bcopy(params, &int_val, sizeof(int_val));
++
++	bool_val = (int_val != 0) ? TRUE : FALSE;
++	BCM_REFERENCE(bool_val);
++
++	actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
++	switch (actionid) {
++	case IOV_GVAL(IOV_MSGLEVEL):
++		int_val = (int32)sd_msglevel;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_MSGLEVEL):
++		sd_msglevel = int_val;
++		break;
++
++	case IOV_GVAL(IOV_BLOCKMODE):
++		int_val = (int32)si->sd_blockmode;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_BLOCKMODE):
++		si->sd_blockmode = (bool)int_val;
++		/* Haven't figured out how to make non-block mode with DMA */
++		break;
++
++	case IOV_GVAL(IOV_BLOCKSIZE):
++		if ((uint32)int_val > si->num_funcs) {
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		int_val = (int32)si->client_block_size[int_val];
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_BLOCKSIZE):
++	{
++		uint func = ((uint32)int_val >> 16);
++		uint blksize = (uint16)int_val;
++		uint maxsize;
++
++		if (func > si->num_funcs) {
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		switch (func) {
++		case 0: maxsize = 32; break;
++		case 1: maxsize = BLOCK_SIZE_4318; break;
++		case 2: maxsize = BLOCK_SIZE_4328; break;
++		default: maxsize = 0;
++		}
++		if (blksize > maxsize) {
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		if (!blksize) {
++			blksize = maxsize;
++		}
++
++		/* Now set it */
++		si->client_block_size[func] = blksize;
++
++		break;
++	}
++
++	case IOV_GVAL(IOV_RXCHAIN):
++		int_val = (int32)si->use_rxchain;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_DMA):
++		int_val = (int32)si->sd_use_dma;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DMA):
++		si->sd_use_dma = (bool)int_val;
++		break;
++
++	case IOV_GVAL(IOV_USEINTS):
++		int_val = (int32)si->use_client_ints;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_USEINTS):
++		si->use_client_ints = (bool)int_val;
++		if (si->use_client_ints)
++			si->intmask |= CLIENT_INTR;
++		else
++			si->intmask &= ~CLIENT_INTR;
++
++		break;
++
++	case IOV_GVAL(IOV_DIVISOR):
++		int_val = (uint32)sd_divisor;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DIVISOR):
++		sd_divisor = int_val;
++		break;
++
++	case IOV_GVAL(IOV_POWER):
++		int_val = (uint32)sd_power;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_POWER):
++		sd_power = int_val;
++		break;
++
++	case IOV_GVAL(IOV_CLOCK):
++		int_val = (uint32)sd_clock;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_CLOCK):
++		sd_clock = int_val;
++		break;
++
++	case IOV_GVAL(IOV_SDMODE):
++		int_val = (uint32)sd_sdmode;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_SDMODE):
++		sd_sdmode = int_val;
++		break;
++
++	case IOV_GVAL(IOV_HISPEED):
++		int_val = (uint32)sd_hiok;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_HISPEED):
++		sd_hiok = int_val;
++		break;
++
++	case IOV_GVAL(IOV_NUMINTS):
++		int_val = (int32)si->intrcount;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_NUMLOCALINTS):
++		int_val = (int32)0;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_HOSTREG):
++	{
++		sdreg_t *sd_ptr = (sdreg_t *)params;
++
++		if (sd_ptr->offset < SD_SysAddr || sd_ptr->offset > SD_MaxCurCap) {
++			sd_err(("%s: bad offset 0x%x\n", __FUNCTION__, sd_ptr->offset));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		sd_trace(("%s: rreg%d at offset %d\n", __FUNCTION__,
++		                  (sd_ptr->offset & 1) ? 8 : ((sd_ptr->offset & 2) ? 16 : 32),
++		                  sd_ptr->offset));
++		if (sd_ptr->offset & 1)
++			int_val = 8; /* sdioh_sdmmc_rreg8(si, sd_ptr->offset); */
++		else if (sd_ptr->offset & 2)
++			int_val = 16; /* sdioh_sdmmc_rreg16(si, sd_ptr->offset); */
++		else
++			int_val = 32; /* sdioh_sdmmc_rreg(si, sd_ptr->offset); */
++
++		bcopy(&int_val, arg, sizeof(int_val));
++		break;
++	}
++
++	case IOV_SVAL(IOV_HOSTREG):
++	{
++		sdreg_t *sd_ptr = (sdreg_t *)params;
++
++		if (sd_ptr->offset < SD_SysAddr || sd_ptr->offset > SD_MaxCurCap) {
++			sd_err(("%s: bad offset 0x%x\n", __FUNCTION__, sd_ptr->offset));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		sd_trace(("%s: wreg%d value 0x%08x at offset %d\n", __FUNCTION__, sd_ptr->value,
++		                  (sd_ptr->offset & 1) ? 8 : ((sd_ptr->offset & 2) ? 16 : 32),
++		                  sd_ptr->offset));
++		break;
++	}
++
++	case IOV_GVAL(IOV_DEVREG):
++	{
++		sdreg_t *sd_ptr = (sdreg_t *)params;
++		uint8 data = 0;
++
++		if (sdioh_cfg_read(si, sd_ptr->func, sd_ptr->offset, &data)) {
++			bcmerror = BCME_SDIO_ERROR;
++			break;
++		}
++
++		int_val = (int)data;
++		bcopy(&int_val, arg, sizeof(int_val));
++		break;
++	}
++
++	case IOV_SVAL(IOV_DEVREG):
++	{
++		sdreg_t *sd_ptr = (sdreg_t *)params;
++		uint8 data = (uint8)sd_ptr->value;
++
++		if (sdioh_cfg_write(si, sd_ptr->func, sd_ptr->offset, &data)) {
++			bcmerror = BCME_SDIO_ERROR;
++			break;
++		}
++		break;
++	}
++
++	default:
++		bcmerror = BCME_UNSUPPORTED;
++		break;
++	}
++exit:
++
++	return bcmerror;
++}
++
++#if defined(OOB_INTR_ONLY) && defined(HW_OOB)
++
++SDIOH_API_RC
++sdioh_enable_hw_oob_intr(sdioh_info_t *sd, bool enable)
++{
++	SDIOH_API_RC status;
++	uint8 data;
++
++	if (enable)
++		data = SDIO_SEPINT_MASK | SDIO_SEPINT_OE | SDIO_SEPINT_ACT_HI;
++	else
++		data = SDIO_SEPINT_ACT_HI;	/* disable hw oob interrupt */
++
++	status = sdioh_request_byte(sd, SDIOH_WRITE, 0, SDIOD_CCCR_BRCM_SEPINT, &data);
++	return status;
++}
++#endif /* defined(OOB_INTR_ONLY) && defined(HW_OOB) */
++
++extern SDIOH_API_RC
++sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
++{
++	SDIOH_API_RC status;
++	/* No lock needed since sdioh_request_byte does locking */
++	status = sdioh_request_byte(sd, SDIOH_READ, fnc_num, addr, data);
++	return status;
++}
++
++extern SDIOH_API_RC
++sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
++{
++	/* No lock needed since sdioh_request_byte does locking */
++	SDIOH_API_RC status;
++	status = sdioh_request_byte(sd, SDIOH_WRITE, fnc_num, addr, data);
++	return status;
++}
++
++static int
++sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, uint32 regaddr)
++{
++	/* read 24 bits and return valid 17 bit addr */
++	int i;
++	uint32 scratch, regdata;
++	uint8 *ptr = (uint8 *)&scratch;
++	for (i = 0; i < 3; i++) {
++		if ((sdioh_sdmmc_card_regread (sd, 0, regaddr, 1, &regdata)) != SUCCESS)
++			sd_err(("%s: Can't read!\n", __FUNCTION__));
++
++		*ptr++ = (uint8) regdata;
++		regaddr++;
++	}
++
++	/* Only the lower 17-bits are valid */
++	scratch = ltoh32(scratch);
++	scratch &= 0x0001FFFF;
++	return (scratch);
++}
++
++extern SDIOH_API_RC
++sdioh_cis_read(sdioh_info_t *sd, uint func, uint8 *cisd, uint32 length)
++{
++	uint32 count;
++	int offset;
++	uint32 foo;
++	uint8 *cis = cisd;
++
++	sd_trace(("%s: Func = %d\n", __FUNCTION__, func));
++
++	if (!sd->func_cis_ptr[func]) {
++		bzero(cis, length);
++		sd_err(("%s: no func_cis_ptr[%d]\n", __FUNCTION__, func));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	sd_err(("%s: func_cis_ptr[%d]=0x%04x\n", __FUNCTION__, func, sd->func_cis_ptr[func]));
++
++	for (count = 0; count < length; count++) {
++		offset =  sd->func_cis_ptr[func] + count;
++		if (sdioh_sdmmc_card_regread (sd, 0, offset, 1, &foo) < 0) {
++			sd_err(("%s: regread failed: Can't read CIS\n", __FUNCTION__));
++			return SDIOH_API_RC_FAIL;
++		}
++
++		*cis = (uint8)(foo & 0xff);
++		cis++;
++	}
++
++	return SDIOH_API_RC_SUCCESS;
++}
++
++extern SDIOH_API_RC
++sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr, uint8 *byte)
++{
++	int err_ret = 0;
++#if defined(MMC_SDIO_ABORT)
++	int sdio_abort_retry = MMC_SDIO_ABORT_RETRY_LIMIT;
++#endif
++
++	sd_info(("%s: rw=%d, func=%d, addr=0x%05x\n", __FUNCTION__, rw, func, regaddr));
++
++	DHD_PM_RESUME_WAIT(sdioh_request_byte_wait);
++	DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
++	if(rw) { /* CMD52 Write */
++		if (func == 0) {
++			/* Can only directly write to some F0 registers.  Handle F2 enable
++			 * as a special case.
++			 */
++			if (regaddr == SDIOD_CCCR_IOEN) {
++				if (sd->func[2]) {
++					sdio_claim_host(sd->func[2]);
++					if (*byte & SDIO_FUNC_ENABLE_2) {
++						/* Enable Function 2 */
++						err_ret = sdio_enable_func(sd->func[2]);
++						if (err_ret) {
++							sd_err(("bcmsdh_sdmmc: enable F2 failed:%d",
++								err_ret));
++						}
++					} else {
++						/* Disable Function 2 */
++						err_ret = sdio_disable_func(sd->func[2]);
++						if (err_ret) {
++							sd_err(("bcmsdh_sdmmc: Disab F2 failed:%d",
++								err_ret));
++						}
++					}
++					sdio_release_host(sd->func[2]);
++				}
++			}
++#if defined(MMC_SDIO_ABORT)
++			/* to allow abort command through F1 */
++			else if (regaddr == SDIOD_CCCR_IOABORT) {
++				while (sdio_abort_retry--) {
++					if (sd->func[func]) {
++						sdio_claim_host(sd->func[func]);
++						/*
++						 * this sdio_f0_writeb() can be replaced with
++						 * another api depending upon MMC driver change.
++						 * As of this time, this is temporaray one
++						 */
++						sdio_writeb(sd->func[func],
++							*byte, regaddr, &err_ret);
++						sdio_release_host(sd->func[func]);
++					}
++					if (!err_ret)
++						break;
++				}
++			}
++#endif /* MMC_SDIO_ABORT */
++			else if (regaddr < 0xF0) {
++				sd_err(("bcmsdh_sdmmc: F0 Wr:0x%02x: write disallowed\n", regaddr));
++			} else {
++				/* Claim host controller, perform F0 write, and release */
++				if (sd->func[func]) {
++					sdio_claim_host(sd->func[func]);
++					sdio_f0_writeb(sd->func[func],
++						*byte, regaddr, &err_ret);
++					sdio_release_host(sd->func[func]);
++				}
++			}
++		} else {
++			/* Claim host controller, perform Fn write, and release */
++			if (sd->func[func]) {
++				sdio_claim_host(sd->func[func]);
++				sdio_writeb(sd->func[func], *byte, regaddr, &err_ret);
++				sdio_release_host(sd->func[func]);
++			}
++		}
++	} else { /* CMD52 Read */
++		/* Claim host controller, perform Fn read, and release */
++		if (sd->func[func]) {
++			sdio_claim_host(sd->func[func]);
++			if (func == 0) {
++				*byte = sdio_f0_readb(sd->func[func], regaddr, &err_ret);
++			} else {
++				*byte = sdio_readb(sd->func[func], regaddr, &err_ret);
++			}
++			sdio_release_host(sd->func[func]);
++		}
++	}
++
++	if (err_ret) {
++		if ((regaddr == 0x1001F) && ((err_ret == -ETIMEDOUT) || (err_ret == -EILSEQ))) {
++		} else {
++			sd_err(("bcmsdh_sdmmc: Failed to %s byte F%d:@0x%05x=%02x, Err: %d\n",
++				rw ? "Write" : "Read", func, regaddr, *byte, err_ret));
++		}
++	}
++
++	return ((err_ret == 0) ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
++}
++
++extern SDIOH_API_RC
++sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func, uint addr,
++                                   uint32 *word, uint nbytes)
++{
++	int err_ret = SDIOH_API_RC_FAIL;
++#if defined(MMC_SDIO_ABORT)
++	int sdio_abort_retry = MMC_SDIO_ABORT_RETRY_LIMIT;
++#endif
++
++	if (func == 0) {
++		sd_err(("%s: Only CMD52 allowed to F0.\n", __FUNCTION__));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	sd_info(("%s: cmd_type=%d, rw=%d, func=%d, addr=0x%05x, nbytes=%d\n",
++	         __FUNCTION__, cmd_type, rw, func, addr, nbytes));
++
++	DHD_PM_RESUME_WAIT(sdioh_request_word_wait);
++	DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
++	/* Claim host controller */
++	sdio_claim_host(sd->func[func]);
++
++	if(rw) { /* CMD52 Write */
++		if (nbytes == 4) {
++			sdio_writel(sd->func[func], *word, addr, &err_ret);
++		} else if (nbytes == 2) {
++			sdio_writew(sd->func[func], (*word & 0xFFFF), addr, &err_ret);
++		} else {
++			sd_err(("%s: Invalid nbytes: %d\n", __FUNCTION__, nbytes));
++		}
++	} else { /* CMD52 Read */
++		if (nbytes == 4) {
++			*word = sdio_readl(sd->func[func], addr, &err_ret);
++		} else if (nbytes == 2) {
++			*word = sdio_readw(sd->func[func], addr, &err_ret) & 0xFFFF;
++		} else {
++			sd_err(("%s: Invalid nbytes: %d\n", __FUNCTION__, nbytes));
++		}
++	}
++
++	/* Release host controller */
++	sdio_release_host(sd->func[func]);
++
++	if (err_ret) {
++#if defined(MMC_SDIO_ABORT)
++		/* Any error on CMD53 transaction should abort that function using function 0. */
++		while (sdio_abort_retry--) {
++			if (sd->func[0]) {
++				sdio_claim_host(sd->func[0]);
++				/*
++				 * this sdio_f0_writeb() can be replaced with another api
++				 * depending upon MMC driver change.
++				 * As of this time, this is temporaray one
++				 */
++				sdio_writeb(sd->func[0],
++					func, SDIOD_CCCR_IOABORT, &err_ret);
++				sdio_release_host(sd->func[0]);
++			}
++			if (!err_ret)
++				break;
++		}
++		if (err_ret)
++#endif /* MMC_SDIO_ABORT */
++		{
++			sd_err(("bcmsdh_sdmmc: Failed to %s word, Err: 0x%08x",
++				rw ? "Write" : "Read", err_ret));
++		}
++	}
++
++	return ((err_ret == 0) ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
++}
++
++static SDIOH_API_RC
++sdioh_request_packet_chain(sdioh_info_t *sd, uint fix_inc, uint write, uint func,
++                     uint addr, void *pkt)
++{
++	bool fifo = (fix_inc == SDIOH_DATA_FIX);
++	int err_ret = 0;
++	void *pnext;
++	uint ttl_len, pkt_offset;
++	uint blk_num;
++	uint blk_size;
++	uint max_blk_count;
++	uint max_req_size;
++	struct mmc_request mmc_req;
++	struct mmc_command mmc_cmd;
++	struct mmc_data mmc_dat;
++	uint32 sg_count;
++	struct sdio_func *sdio_func = sd->func[func];
++	struct mmc_host *host = sdio_func->card->host;
++
++	sd_trace(("%s: Enter\n", __FUNCTION__));
++	ASSERT(pkt);
++	DHD_PM_RESUME_WAIT(sdioh_request_packet_wait);
++	DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
++
++	blk_size = sd->client_block_size[func];
++	max_blk_count = min(host->max_blk_count, (uint)MAX_IO_RW_EXTENDED_BLK);
++	max_req_size = min(max_blk_count * blk_size, host->max_req_size);
++
++	pkt_offset = 0;
++	pnext = pkt;
++
++	while (pnext != NULL) {
++		ttl_len = 0;
++		sg_count = 0;
++		memset(&mmc_req, 0, sizeof(struct mmc_request));
++		memset(&mmc_cmd, 0, sizeof(struct mmc_command));
++		memset(&mmc_dat, 0, sizeof(struct mmc_data));
++		sg_init_table(sd->sg_list, ARRAYSIZE(sd->sg_list));
++
++		/* Set up scatter-gather DMA descriptors. this loop is to find out the max
++		 * data we can transfer with one command 53. blocks per command is limited by
++		 * host max_req_size and 9-bit max block number. when the total length of this
++		 * packet chain is bigger than max_req_size, use multiple SD_IO_RW_EXTENDED
++		 * commands (each transfer is still block aligned)
++		 */
++		while (pnext != NULL && ttl_len < max_req_size) {
++			int pkt_len;
++			int sg_data_size;
++			uint8 *pdata = (uint8*)PKTDATA(sd->osh, pnext);
++
++			ASSERT(pdata != NULL);
++			pkt_len = PKTLEN(sd->osh, pnext);
++			sd_trace(("%s[%d] data=%p, len=%d\n", __FUNCTION__, write, pdata, pkt_len));
++			/* sg_count is unlikely larger than the array size, and this is
++			 * NOT something we can handle here, but in case it happens, PLEASE put
++			 * a restriction on max tx/glom count (based on host->max_segs).
++			 */
++			if (sg_count >= ARRAYSIZE(sd->sg_list)) {
++				sd_err(("%s: sg list entries exceed limit\n", __FUNCTION__));
++				return (SDIOH_API_RC_FAIL);
++			}
++			pdata += pkt_offset;
++
++			sg_data_size = pkt_len - pkt_offset;
++			if (sg_data_size > max_req_size - ttl_len)
++				sg_data_size = max_req_size - ttl_len;
++			/* some platforms put a restriction on the data size of each scatter-gather
++			 * DMA descriptor, use multiple sg buffers when xfer_size is bigger than
++			 * max_seg_size
++			 */
++			if (sg_data_size > host->max_seg_size)
++				sg_data_size = host->max_seg_size;
++			sg_set_buf(&sd->sg_list[sg_count++], pdata, sg_data_size);
++
++			ttl_len += sg_data_size;
++			pkt_offset += sg_data_size;
++			if (pkt_offset == pkt_len) {
++				pnext = PKTNEXT(sd->osh, pnext);
++				pkt_offset = 0;
++			}
++		}
++
++		if (ttl_len % blk_size != 0) {
++			sd_err(("%s, data length %d not aligned to block size %d\n",
++				__FUNCTION__,  ttl_len, blk_size));
++			return SDIOH_API_RC_FAIL;
++		}
++		blk_num = ttl_len / blk_size;
++		mmc_dat.sg = sd->sg_list;
++		mmc_dat.sg_len = sg_count;
++		mmc_dat.blksz = blk_size;
++		mmc_dat.blocks = blk_num;
++		mmc_dat.flags = write ? MMC_DATA_WRITE : MMC_DATA_READ;
++		mmc_cmd.opcode = 53; /* SD_IO_RW_EXTENDED */
++		mmc_cmd.arg = write ? 1<<31 : 0;
++		mmc_cmd.arg |= (func & 0x7) << 28;
++		mmc_cmd.arg |= 1<<27;
++		mmc_cmd.arg |= fifo ? 0 : 1<<26;
++		mmc_cmd.arg |= (addr & 0x1FFFF) << 9;
++		mmc_cmd.arg |= blk_num & 0x1FF;
++		mmc_cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
++		mmc_req.cmd = &mmc_cmd;
++		mmc_req.data = &mmc_dat;
++		if (!fifo)
++			addr += ttl_len;
++
++		sdio_claim_host(sdio_func);
++		mmc_set_data_timeout(&mmc_dat, sdio_func->card);
++		mmc_wait_for_req(host, &mmc_req);
++		sdio_release_host(sdio_func);
++
++		err_ret = mmc_cmd.error? mmc_cmd.error : mmc_dat.error;
++		if (0 != err_ret) {
++			sd_err(("%s:CMD53 %s failed with code %d\n",
++				__FUNCTION__, write ? "write" : "read", err_ret));
++			return SDIOH_API_RC_FAIL;
++		}
++	}
++
++	sd_trace(("%s: Exit\n", __FUNCTION__));
++	return SDIOH_API_RC_SUCCESS;
++}
++
++static SDIOH_API_RC
++sdioh_buffer_tofrom_bus(sdioh_info_t *sd, uint fix_inc, uint write, uint func,
++                     uint addr, uint8 *buf, uint len)
++{
++	bool fifo = (fix_inc == SDIOH_DATA_FIX);
++	int err_ret = 0;
++
++	sd_trace(("%s: Enter\n", __FUNCTION__));
++	ASSERT(buf);
++
++	/* NOTE:
++	 * For all writes, each packet length is aligned to 32 (or 4)
++	 * bytes in dhdsdio_txpkt_preprocess, and for glom the last packet length
++	 * is aligned to block boundary. If you want to align each packet to
++	 * a custom size, please do it in dhdsdio_txpkt_preprocess, NOT here
++	 *
++	 * For reads, the alignment is doen in sdioh_request_buffer.
++	 *
++	 */
++	sdio_claim_host(sd->func[func]);
++
++	if ((write) && (!fifo))
++		err_ret = sdio_memcpy_toio(sd->func[func], addr, buf, len);
++	else if (write)
++		err_ret = sdio_memcpy_toio(sd->func[func], addr, buf, len);
++	else if (fifo)
++		err_ret = sdio_readsb(sd->func[func], buf, addr, len);
++	else
++		err_ret = sdio_memcpy_fromio(sd->func[func], buf, addr, len);
++
++	sdio_release_host(sd->func[func]);
++
++	if (err_ret)
++		sd_err(("%s: %s FAILED %p, addr=0x%05x, pkt_len=%d, ERR=%d\n", __FUNCTION__,
++		       (write) ? "TX" : "RX", buf, addr, len, err_ret));
++	else
++		sd_trace(("%s: %s xfr'd %p, addr=0x%05x, len=%d\n", __FUNCTION__,
++			(write) ? "TX" : "RX", buf, addr, len));
++
++	sd_trace(("%s: Exit\n", __FUNCTION__));
++	return ((err_ret == 0) ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
++}
++
++static SDIOH_API_RC
++sdioh_buffer_tofrom_bus_ext(sdioh_info_t *sd, uint fix_inc, uint write, uint func,
++                     uint addr, void *pkt)
++{
++	SDIOH_API_RC status;
++	void *pnext;
++	int blk_size;
++	uint ttl_len = 0, total_len=0;
++	uint8 *buffer = NULL;
++
++	sd_trace(("%s: Enter\n", __FUNCTION__));
++	blk_size = sd->client_block_size[func];
++
++	/* at least 4 bytes alignment of skb buff is guaranteed */
++	for (pnext = pkt; pnext; pnext = PKTNEXT(sd->osh, pnext))
++		ttl_len += PKTLEN(sd->osh, pnext);
++	/* Packet alignment */
++	if (!write || ttl_len < 32)
++		ttl_len = (ttl_len + 3) & 0xFFFFFFFC;
++	else if ((ttl_len > blk_size) && (ttl_len % blk_size))
++	{
++		if (func == SDIO_FUNC_2)
++		{
++			sd_info(("%s: [%s] dhd_sdio must align %d bytes"
++			" packet larger than a %d bytes blk size by a blk size\n",
++			__FUNCTION__, write ? "W" : "R", ttl_len, blk_size));
++		}
++		ttl_len += blk_size - (ttl_len % blk_size);
++	}
++	buffer = (uint8 *)MALLOC(sd->osh, ttl_len);
++	if(!buffer)
++		return SDIOH_API_RC_FAIL;
++
++	pnext = pkt;
++	while (pnext != NULL)
++	{
++		bcopy(PKTDATA(sd->osh, pnext), buffer + total_len, PKTLEN(sd->osh, pnext));
++		total_len += PKTLEN(sd->osh, pnext);
++		pnext = PKTNEXT(sd->osh, pnext);
++	}
++
++	status = sdioh_buffer_tofrom_bus(sd, fix_inc, write, func, addr, buffer, total_len);
++
++	if (buffer)
++		MFREE(sd->osh, buffer, ttl_len);
++
++	return status;
++}
++
++/*
++ * This function takes a buffer or packet, and fixes everything up so that in the
++ * end, a DMA-able packet is created.
++ *
++ * A buffer does not have an associated packet pointer, and may or may not be aligned.
++ * A packet may consist of a single packet, or a packet chain.  If it is a packet chain,
++ * then all the packets in the chain must be properly aligned.  If the packet data is not
++ * aligned, then there may only be one packet, and in this case, it is copied to a new
++ * aligned packet.
++ *
++ */
++extern SDIOH_API_RC
++sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint write, uint func,
++	uint addr, uint reg_width, uint buf_len, uint8 *buffer, void *pkt)
++{
++	SDIOH_API_RC status;
++	void *tmppkt;
++
++	sd_trace(("%s: Enter\n", __FUNCTION__));
++	DHD_PM_RESUME_WAIT(sdioh_request_buffer_wait);
++	DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
++
++	if (pkt) {
++		if (PKTNEXT(sd->osh, pkt))
++		{
++			/* packet chain, only used for tx/rx glom, all packets length
++			* are aligned, total length is a block multiple
++			*/
++			if (sd->func[func]->card->host->max_segs > 1 /* Multi-desc mode for scatter-gather DMA */
++				&& (!write || sd_txglom) ) /* tx will check sd_txglom */
++				return sdioh_request_packet_chain(sd, fix_inc, write, func, addr, pkt);
++			if (write && sd_txglom) /* Copy mode only in Tx */
++				return sdioh_buffer_tofrom_bus_ext(sd, fix_inc, write, func, addr, pkt);
++		}
++		/* non-glom mode, ignore the buffer parameter and use the packet pointer
++		 * (this shouldn't happen)
++		 */
++		buffer = PKTDATA(sd->osh, pkt);
++		buf_len = PKTLEN(sd->osh, pkt);
++	}
++
++	ASSERT(buffer);
++
++	/* buffer and length are aligned, use it directly so we can avoid memory copy */
++	if (((ulong)buffer & DMA_ALIGN_MASK) == 0 && (buf_len & DMA_ALIGN_MASK) == 0)
++		return sdioh_buffer_tofrom_bus(sd, fix_inc, write, func, addr, buffer, buf_len);
++
++	sd_trace(("%s: [%d] doing memory copy buf=%p, len=%d\n",
++		__FUNCTION__, write, buffer, buf_len));
++
++	/* otherwise, a memory copy is needed as the input buffer is not aligned */
++	tmppkt = PKTGET_STATIC(sd->osh, buf_len + DEFAULT_SDIO_F2_BLKSIZE, write ? TRUE : FALSE);
++	if (tmppkt == NULL) {
++		sd_err(("%s: PKTGET failed: len %d\n", __FUNCTION__, buf_len));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	if (write)
++		bcopy(buffer, PKTDATA(sd->osh, tmppkt), buf_len);
++
++	status = sdioh_buffer_tofrom_bus(sd, fix_inc, write, func, addr,
++		PKTDATA(sd->osh, tmppkt), ROUNDUP(buf_len, (DMA_ALIGN_MASK+1)));
++
++	if (!write)
++		bcopy(PKTDATA(sd->osh, tmppkt), buffer, buf_len);
++
++	PKTFREE_STATIC(sd->osh, tmppkt, write ? TRUE : FALSE);
++
++	return status;
++}
++
++/* this function performs "abort" for both of host & device */
++extern int
++sdioh_abort(sdioh_info_t *sd, uint func)
++{
++#if defined(MMC_SDIO_ABORT)
++	char t_func = (char) func;
++#endif /* defined(MMC_SDIO_ABORT) */
++	sd_trace(("%s: Enter\n", __FUNCTION__));
++
++#if defined(MMC_SDIO_ABORT)
++	/* issue abort cmd52 command through F1 */
++	sdioh_request_byte(sd, SD_IO_OP_WRITE, SDIO_FUNC_0, SDIOD_CCCR_IOABORT, &t_func);
++#endif /* defined(MMC_SDIO_ABORT) */
++
++	sd_trace(("%s: Exit\n", __FUNCTION__));
++	return SDIOH_API_RC_SUCCESS;
++}
++
++/* Reset and re-initialize the device */
++int sdioh_sdio_reset(sdioh_info_t *si)
++{
++	sd_trace(("%s: Enter\n", __FUNCTION__));
++	sd_trace(("%s: Exit\n", __FUNCTION__));
++	return SDIOH_API_RC_SUCCESS;
++}
++
++/* Disable device interrupt */
++void
++sdioh_sdmmc_devintr_off(sdioh_info_t *sd)
++{
++	sd_trace(("%s: %d\n", __FUNCTION__, sd->use_client_ints));
++	sd->intmask &= ~CLIENT_INTR;
++}
++
++/* Enable device interrupt */
++void
++sdioh_sdmmc_devintr_on(sdioh_info_t *sd)
++{
++	sd_trace(("%s: %d\n", __FUNCTION__, sd->use_client_ints));
++	sd->intmask |= CLIENT_INTR;
++}
++
++/* Read client card reg */
++int
++sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data)
++{
++
++	if ((func == 0) || (regsize == 1)) {
++		uint8 temp = 0;
++
++		sdioh_request_byte(sd, SDIOH_READ, func, regaddr, &temp);
++		*data = temp;
++		*data &= 0xff;
++		sd_data(("%s: byte read data=0x%02x\n",
++		         __FUNCTION__, *data));
++	} else {
++		sdioh_request_word(sd, 0, SDIOH_READ, func, regaddr, data, regsize);
++		if (regsize == 2)
++			*data &= 0xffff;
++
++		sd_data(("%s: word read data=0x%08x\n",
++		         __FUNCTION__, *data));
++	}
++
++	return SUCCESS;
++}
++
++#if !defined(OOB_INTR_ONLY)
++/* bcmsdh_sdmmc interrupt handler */
++static void IRQHandler(struct sdio_func *func)
++{
++	sdioh_info_t *sd;
++
++	sd = sdio_get_drvdata(func);
++
++	ASSERT(sd != NULL);
++	sdio_release_host(sd->func[0]);
++
++	if (sd->use_client_ints) {
++		sd->intrcount++;
++		ASSERT(sd->intr_handler);
++		ASSERT(sd->intr_handler_arg);
++		(sd->intr_handler)(sd->intr_handler_arg);
++	} else {
++		sd_err(("bcmsdh_sdmmc: ***IRQHandler\n"));
++
++		sd_err(("%s: Not ready for intr: enabled %d, handler %p\n",
++		        __FUNCTION__, sd->client_intr_enabled, sd->intr_handler));
++	}
++
++	sdio_claim_host(sd->func[0]);
++}
++
++/* bcmsdh_sdmmc interrupt handler for F2 (dummy handler) */
++static void IRQHandlerF2(struct sdio_func *func)
++{
++	sd_trace(("bcmsdh_sdmmc: ***IRQHandlerF2\n"));
++}
++#endif /* !defined(OOB_INTR_ONLY) */
++
++#ifdef NOTUSED
++/* Write client card reg */
++static int
++sdioh_sdmmc_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 data)
++{
++
++	if ((func == 0) || (regsize == 1)) {
++		uint8 temp;
++
++		temp = data & 0xff;
++		sdioh_request_byte(sd, SDIOH_READ, func, regaddr, &temp);
++		sd_data(("%s: byte write data=0x%02x\n",
++		         __FUNCTION__, data));
++	} else {
++		if (regsize == 2)
++			data &= 0xffff;
++
++		sdioh_request_word(sd, 0, SDIOH_READ, func, regaddr, &data, regsize);
++
++		sd_data(("%s: word write data=0x%08x\n",
++		         __FUNCTION__, data));
++	}
++
++	return SUCCESS;
++}
++#endif /* NOTUSED */
++
++int
++sdioh_start(sdioh_info_t *sd, int stage)
++{
++	int ret;
++
++	if (!sd) {
++		sd_err(("%s Failed, sd is NULL\n", __FUNCTION__));
++		return (0);
++	}
++
++	/* Need to do this stages as we can't enable the interrupt till
++		downloading of the firmware is complete, other wise polling
++		sdio access will come in way
++	*/
++	if (sd->func[0]) {
++		if (stage == 0) {
++		/* Since the power to the chip is killed, we will have
++			re enumerate the device again. Set the block size
++			and enable the fucntion 1 for in preparation for
++			downloading the code
++		*/
++		/* sdio_reset_comm() For Android kernel only
++		   has been fixed in latest kernel/msm.git for Linux
++		   2.6.27. The implementation prior to that is buggy, and needs broadcom's
++		   patch for it
++		*/
++		if ((ret = sdio_reset_comm(sd->func[0]->card))) {
++			sd_err(("%s Failed, error = %d\n", __FUNCTION__, ret));
++			return ret;
++		}
++		else {
++			sd->num_funcs = 2;
++			sd->sd_blockmode = TRUE;
++			sd->use_client_ints = TRUE;
++			sd->client_block_size[0] = 64;
++
++			if (sd->func[1]) {
++				/* Claim host controller */
++				sdio_claim_host(sd->func[1]);
++
++				sd->client_block_size[1] = 64;
++				ret = sdio_set_block_size(sd->func[1], 64);
++				if (ret) {
++					sd_err(("bcmsdh_sdmmc: Failed to set F1 "
++						"blocksize(%d)\n", ret));
++				}
++
++				/* Release host controller F1 */
++				sdio_release_host(sd->func[1]);
++			}
++
++			if (sd->func[2]) {
++				/* Claim host controller F2 */
++				sdio_claim_host(sd->func[2]);
++
++				sd->client_block_size[2] = sd_f2_blocksize;
++				ret = sdio_set_block_size(sd->func[2], sd_f2_blocksize);
++				if (ret) {
++					sd_err(("bcmsdh_sdmmc: Failed to set F2 "
++						"blocksize to %d(%d)\n", sd_f2_blocksize, ret));
++				}
++
++				/* Release host controller F2 */
++				sdio_release_host(sd->func[2]);
++			}
++
++			sdioh_sdmmc_card_enablefuncs(sd);
++			}
++		} else {
++#if !defined(OOB_INTR_ONLY)
++			sdio_claim_host(sd->func[0]);
++			if (sd->func[2])
++				sdio_claim_irq(sd->func[2], IRQHandlerF2);
++			if (sd->func[1])
++				sdio_claim_irq(sd->func[1], IRQHandler);
++			sdio_release_host(sd->func[0]);
++#else /* defined(OOB_INTR_ONLY) */
++#if defined(HW_OOB)
++			sdioh_enable_func_intr(sd);
++#endif
++			bcmsdh_oob_intr_set(sd->bcmsdh, TRUE);
++#endif /* !defined(OOB_INTR_ONLY) */
++		}
++	}
++	else
++		sd_err(("%s Failed\n", __FUNCTION__));
++
++	return (0);
++}
++
++int
++sdioh_stop(sdioh_info_t *sd)
++{
++	/* MSM7201A Android sdio stack has bug with interrupt
++		So internaly within SDIO stack they are polling
++		which cause issue when device is turned off. So
++		unregister interrupt with SDIO stack to stop the
++		polling
++	*/
++	if (sd->func[0]) {
++#if !defined(OOB_INTR_ONLY)
++		sdio_claim_host(sd->func[0]);
++		if (sd->func[1])
++			sdio_release_irq(sd->func[1]);
++		if (sd->func[2])
++			sdio_release_irq(sd->func[2]);
++		sdio_release_host(sd->func[0]);
++#else /* defined(OOB_INTR_ONLY) */
++#if defined(HW_OOB)
++		sdioh_disable_func_intr(sd);
++#endif
++		bcmsdh_oob_intr_set(sd->bcmsdh, FALSE);
++#endif /* !defined(OOB_INTR_ONLY) */
++	}
++	else
++		sd_err(("%s Failed\n", __FUNCTION__));
++	return (0);
++}
++
++int
++sdioh_waitlockfree(sdioh_info_t *sd)
++{
++	return (1);
++}
++
++
++SDIOH_API_RC
++sdioh_gpioouten(sdioh_info_t *sd, uint32 gpio)
++{
++	return SDIOH_API_RC_FAIL;
++}
++
++SDIOH_API_RC
++sdioh_gpioout(sdioh_info_t *sd, uint32 gpio, bool enab)
++{
++	return SDIOH_API_RC_FAIL;
++}
++
++bool
++sdioh_gpioin(sdioh_info_t *sd, uint32 gpio)
++{
++	return FALSE;
++}
++
++SDIOH_API_RC
++sdioh_gpio_init(sdioh_info_t *sd)
++{
++	return SDIOH_API_RC_FAIL;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmsdh_sdmmc_linux.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmsdh_sdmmc_linux.c
+new file mode 100644
+index 000000000..e008c443d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmsdh_sdmmc_linux.c
+@@ -0,0 +1,413 @@
++/*
++ * BCMSDH Function Driver for the native SDIO/MMC driver in the Linux Kernel
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Proprietary,Open:>>
++ *
++ * $Id: bcmsdh_sdmmc_linux.c 708487 2018-10-31 05:33:14Z $
++ */
++
++#include <typedefs.h>
++#include <bcmutils.h>
++#include <sdio.h>	/* SDIO Device and Protocol Specs */
++#include <bcmsdbus.h>	/* bcmsdh to/from specific controller APIs */
++#include <sdiovar.h>	/* to get msglevel bit values */
++
++#include <linux/sched.h>	/* request_irq() */
++
++#include <linux/mmc/core.h>
++#include <linux/mmc/card.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/sdio_func.h>
++#include <linux/mmc/sdio_ids.h>
++#include <dhd_linux.h>
++#include <bcmsdh_sdmmc.h>
++#include <dhd_dbg.h>
++
++#ifdef LOAD_DHD_WITH_FW_ALIVE
++#include <dhd_chip_info.h>
++#endif
++
++
++#if !defined(SDIO_VENDOR_ID_BROADCOM)
++#define SDIO_VENDOR_ID_BROADCOM		0x02d0
++#endif /* !defined(SDIO_VENDOR_ID_BROADCOM) */
++
++#define SDIO_DEVICE_ID_BROADCOM_DEFAULT	0x0000
++
++#if !defined(SDIO_DEVICE_ID_BROADCOM_4325_SDGWB)
++#define SDIO_DEVICE_ID_BROADCOM_4325_SDGWB	0x0492	/* BCM94325SDGWB */
++#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_4325_SDGWB) */
++#if !defined(SDIO_DEVICE_ID_BROADCOM_4325)
++#define SDIO_DEVICE_ID_BROADCOM_4325	0x0493
++#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_4325) */
++#if !defined(SDIO_DEVICE_ID_BROADCOM_4329)
++#define SDIO_DEVICE_ID_BROADCOM_4329	0x4329
++#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_4329) */
++#if !defined(SDIO_DEVICE_ID_BROADCOM_4319)
++#define SDIO_DEVICE_ID_BROADCOM_4319	0x4319
++#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_4319) */
++#if !defined(SDIO_DEVICE_ID_BROADCOM_4330)
++#define SDIO_DEVICE_ID_BROADCOM_4330	0x4330
++#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_4330) */
++#if !defined(SDIO_DEVICE_ID_BROADCOM_4334)
++#define SDIO_DEVICE_ID_BROADCOM_4334    0x4334
++#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_4334) */
++#if !defined(SDIO_DEVICE_ID_BROADCOM_4324)
++#define SDIO_DEVICE_ID_BROADCOM_4324    0x4324
++#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_4324) */
++#if !defined(SDIO_DEVICE_ID_BROADCOM_43239)
++#define SDIO_DEVICE_ID_BROADCOM_43239    43239
++#endif /* !defined(SDIO_DEVICE_ID_BROADCOM_43239) */
++
++extern void wl_cfg80211_set_parent_dev(void *dev);
++extern void sdioh_sdmmc_devintr_off(sdioh_info_t *sd);
++extern void sdioh_sdmmc_devintr_on(sdioh_info_t *sd);
++extern void* bcmsdh_probe(osl_t *osh, void *dev, void *sdioh, void *adapter_info, uint bus_type,
++	uint bus_num, uint slot_num);
++extern int bcmsdh_remove(bcmsdh_info_t *bcmsdh);
++
++int sdio_function_init(void);
++void sdio_function_cleanup(void);
++
++#define DESCRIPTION "bcmsdh_sdmmc Driver"
++#define AUTHOR "Broadcom Corporation"
++
++/* module param defaults */
++static int clockoverride = 0;
++
++module_param(clockoverride, int, 0644);
++MODULE_PARM_DESC(clockoverride, "SDIO card clock override");
++
++/* Maximum number of bcmsdh_sdmmc devices supported by driver */
++#define BCMSDH_SDMMC_MAX_DEVICES 1
++
++extern volatile bool dhd_mmc_suspend;
++
++static int sdioh_probe(struct sdio_func *func)
++{
++	int host_idx = func->card->host->index;
++	uint32 rca = func->card->rca;
++	wifi_adapter_info_t *adapter;
++	osl_t *osh = NULL;
++	sdioh_info_t *sdioh = NULL;
++
++#ifdef LOAD_DHD_WITH_FW_ALIVE
++	int ready = 0;
++#endif
++
++	sd_err(("bus num (host idx)=%d, slot num (rca)=%d\n", host_idx, rca));
++	adapter = dhd_wifi_platform_get_adapter(SDIO_BUS, host_idx, rca);
++	if (adapter  != NULL)
++		sd_err(("found adapter info '%s'\n", adapter->name));
++	else
++		sd_err(("can't find adapter info for this chip\n"));
++
++#ifdef WL_CFG80211
++	wl_cfg80211_set_parent_dev(&func->dev);
++#endif
++
++	 /* allocate SDIO Host Controller state info */
++	 osh = osl_attach(&func->dev, SDIO_BUS, TRUE);
++	 if (osh == NULL) {
++		 sd_err(("%s: osl_attach failed\n", __FUNCTION__));
++		 goto fail;
++	 }
++	 osl_static_mem_init(osh, adapter);
++	 sdioh = sdioh_attach(osh, func);
++	 if (sdioh == NULL) {
++		 sd_err(("%s: sdioh_attach failed\n", __FUNCTION__));
++		 goto fail;
++	 }
++#ifdef LOAD_DHD_WITH_FW_ALIVE
++	sdioh_cfg_read(sdioh, SDIO_FUNC_0, SDIOD_CCCR_IORDY, (uint8 *)&ready);
++
++	sd_info(("%s, %d, ready = %08x\n", __func__, __LINE__, ready));
++	if(ready == (SDIO_FUNC_READY_1|SDIO_FUNC_READY_2)) {
++		alive = FW_ALIVE_MAGIC;	//func->card->nr_parts;
++		card_dev = func->card->cis.device;
++	}
++
++	sd_info(("nr_parts = %08x, card_dev = %08x\n", alive, card_dev));
++#endif
++	 sdioh->bcmsdh = bcmsdh_probe(osh, &func->dev, sdioh, adapter, SDIO_BUS, host_idx, rca);
++	 if (sdioh->bcmsdh == NULL) {
++		 sd_err(("%s: bcmsdh_probe failed\n", __FUNCTION__));
++		 goto fail;
++	 }
++
++	sdio_set_drvdata(func, sdioh);
++	return 0;
++
++fail:
++	if (sdioh != NULL)
++		sdioh_detach(osh, sdioh);
++	if (osh != NULL)
++		osl_detach(osh);
++	return -ENOMEM;
++}
++
++static void sdioh_remove(struct sdio_func *func)
++{
++	sdioh_info_t *sdioh;
++	osl_t *osh;
++
++	sdioh = sdio_get_drvdata(func);
++	if (sdioh == NULL) {
++		sd_err(("%s: error, no sdioh handler found\n", __FUNCTION__));
++		return;
++	}
++
++	osh = sdioh->osh;
++	bcmsdh_remove(sdioh->bcmsdh);
++	sdioh_detach(osh, sdioh);
++	osl_detach(osh);
++}
++
++static int bcmsdh_sdmmc_probe(struct sdio_func *func,
++                              const struct sdio_device_id *id)
++{
++	int ret = 0;
++
++	if (func == NULL)
++		return -EINVAL;
++
++	sd_err(("bcmsdh_sdmmc: %s Enter\n", __FUNCTION__));
++	sd_info(("sdio_bcmsdh: func->class=%x\n", func->class));
++	sd_info(("sdio_vendor: 0x%04x\n", func->vendor));
++	sd_info(("sdio_device: 0x%04x\n", func->device));
++	sd_info(("Function#: 0x%04x\n", func->num));
++
++	/* 4318 doesn't have function 2 */
++	if ((func->num == 2) || (func->num == 1 && func->device == 0x4))
++		ret = sdioh_probe(func);
++
++	return ret;
++}
++
++static void bcmsdh_sdmmc_remove(struct sdio_func *func)
++{
++	if (func == NULL) {
++		sd_err(("%s is called with NULL SDIO function pointer\n", __FUNCTION__));
++		return;
++	}
++
++	sd_trace(("bcmsdh_sdmmc: %s Enter\n", __FUNCTION__));
++	sd_info(("sdio_bcmsdh: func->class=%x\n", func->class));
++	sd_info(("sdio_vendor: 0x%04x\n", func->vendor));
++	sd_info(("sdio_device: 0x%04x\n", func->device));
++	sd_info(("Function#: 0x%04x\n", func->num));
++
++	if ((func->num == 2) || (func->num == 1 && func->device == 0x4))
++		sdioh_remove(func);
++}
++
++/* devices we support, null terminated */
++static const struct sdio_device_id bcmsdh_sdmmc_ids[] = {
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_DEFAULT) },
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4325_SDGWB) },
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4325) },
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4329) },
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4319) },
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4330) },
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4334) },
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4324) },
++	{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_43239) },
++	{ SDIO_DEVICE_CLASS(SDIO_CLASS_NONE)		},
++	{ /* end: all zeroes */				},
++};
++
++MODULE_DEVICE_TABLE(sdio, bcmsdh_sdmmc_ids);
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39)) && defined(CONFIG_PM)
++static int bcmsdh_sdmmc_suspend(struct device *pdev)
++{
++	int err;
++	sdioh_info_t *sdioh;
++	struct sdio_func *func = dev_to_sdio_func(pdev);
++	mmc_pm_flag_t sdio_flags;
++
++	sd_err(("%s Enter\n", __FUNCTION__));
++	if (func->num != 2)
++		return 0;
++
++	dhd_mmc_suspend = TRUE;
++	sdioh = sdio_get_drvdata(func);
++	err = bcmsdh_suspend(sdioh->bcmsdh);
++	if (err) {
++		dhd_mmc_suspend = FALSE;
++		return err;
++	}
++
++	sdio_flags = sdio_get_host_pm_caps(func);
++	if (!(sdio_flags & MMC_PM_KEEP_POWER)) {
++		sd_err(("%s: can't keep power while host is suspended\n", __FUNCTION__));
++		dhd_mmc_suspend = FALSE;
++		return  -EINVAL;
++	}
++
++	/* keep power while host suspended */
++	err = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
++	if (err) {
++		sd_err(("%s: error while trying to keep power\n", __FUNCTION__));
++		dhd_mmc_suspend = FALSE;
++		return err;
++	}
++#if defined(OOB_INTR_ONLY)
++	bcmsdh_oob_intr_set(sdioh->bcmsdh, FALSE);
++#endif 
++	smp_mb();
++
++	return 0;
++}
++
++static int bcmsdh_sdmmc_resume(struct device *pdev)
++{
++	sdioh_info_t *sdioh;
++	struct sdio_func *func = dev_to_sdio_func(pdev);
++
++	sd_err(("%s Enter\n", __FUNCTION__));
++	if (func->num != 2)
++		return 0;
++
++	sdioh = sdio_get_drvdata(func);
++	dhd_mmc_suspend = FALSE;
++
++	bcmsdh_resume(sdioh->bcmsdh);
++
++	smp_mb();
++	return 0;
++}
++
++static const struct dev_pm_ops bcmsdh_sdmmc_pm_ops = {
++	.suspend	= bcmsdh_sdmmc_suspend,
++	.resume		= bcmsdh_sdmmc_resume,
++};
++#endif  /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39)) && defined(CONFIG_PM) */
++
++#if defined(BCMLXSDMMC)
++static struct semaphore *notify_semaphore = NULL;
++
++static int dummy_probe(struct sdio_func *func,
++                              const struct sdio_device_id *id)
++{
++	if (func && (func->num != 2)) {
++		return 0;
++	}
++
++	if (notify_semaphore)
++		up(notify_semaphore);
++	return 0;
++}
++
++static void dummy_remove(struct sdio_func *func)
++{
++}
++
++static struct sdio_driver dummy_sdmmc_driver = {
++	.probe		= dummy_probe,
++	.remove		= dummy_remove,
++	.name		= "dummy_sdmmc",
++	.id_table	= bcmsdh_sdmmc_ids,
++	};
++
++int sdio_func_reg_notify(void* semaphore)
++{
++	notify_semaphore = semaphore;
++	return sdio_register_driver(&dummy_sdmmc_driver);
++}
++
++void sdio_func_unreg_notify(void)
++{
++	OSL_SLEEP(15);
++	sdio_unregister_driver(&dummy_sdmmc_driver);
++}
++
++#endif /* defined(BCMLXSDMMC) */
++
++static struct sdio_driver bcmsdh_sdmmc_driver = {
++	.probe		= bcmsdh_sdmmc_probe,
++	.remove		= bcmsdh_sdmmc_remove,
++	.name		= "bcmsdh_sdmmc",
++	.id_table	= bcmsdh_sdmmc_ids,
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39)) && defined(CONFIG_PM)
++	.drv = {
++	.pm	= &bcmsdh_sdmmc_pm_ops,
++	},
++#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39)) && defined(CONFIG_PM) */
++	};
++
++struct sdos_info {
++	sdioh_info_t *sd;
++	spinlock_t lock;
++};
++
++/* Interrupt enable/disable */
++SDIOH_API_RC
++sdioh_interrupt_set(sdioh_info_t *sd, bool enable)
++{
++	if (!sd)
++		return BCME_BADARG;
++
++	sd_trace(("%s: %s\n", __FUNCTION__, enable ? "Enabling" : "Disabling"));
++	return SDIOH_API_RC_SUCCESS;
++}
++
++#ifdef BCMSDH_MODULE
++static int __init
++bcmsdh_module_init(void)
++{
++	int error = 0;
++	error = sdio_function_init();
++	return error;
++}
++
++static void __exit
++bcmsdh_module_cleanup(void)
++{
++	sdio_function_cleanup();
++}
++
++module_init(bcmsdh_module_init);
++module_exit(bcmsdh_module_cleanup);
++
++MODULE_LICENSE("GPL v2");
++MODULE_DESCRIPTION(DESCRIPTION);
++MODULE_AUTHOR(AUTHOR);
++
++#endif /* BCMSDH_MODULE */
++/*
++ * module init
++*/
++int bcmsdh_register_client_driver(void)
++{
++	return sdio_register_driver(&bcmsdh_sdmmc_driver);
++}
++
++/*
++ * module cleanup
++*/
++void bcmsdh_unregister_client_driver(void)
++{
++	sdio_unregister_driver(&bcmsdh_sdmmc_driver);
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmsdspi_linux.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmsdspi_linux.c
+new file mode 100644
+index 000000000..b168caf44
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmsdspi_linux.c
+@@ -0,0 +1,252 @@
++/*
++ * Broadcom SPI Host Controller Driver - Linux Per-port
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmsdspi_linux.c 514727 2014-11-12 03:02:48Z $
++ */
++
++#include <typedefs.h>
++#include <bcmutils.h>
++
++#include <bcmsdbus.h>		/* bcmsdh to/from specific controller APIs */
++#include <sdiovar.h>		/* to get msglevel bit values */
++
++#include <pcicfg.h>
++#include <sdio.h>		/* SDIO Device and Protocol Specs */
++#include <linux/sched.h>	/* request_irq(), free_irq() */
++#include <bcmsdspi.h>
++#include <bcmspi.h>
++
++extern uint sd_crc;
++module_param(sd_crc, uint, 0);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++#define KERNEL26
++#endif
++
++struct sdos_info {
++	sdioh_info_t *sd;
++	spinlock_t lock;
++	wait_queue_head_t intr_wait_queue;
++};
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++#define BLOCKABLE()	(!in_atomic())
++#else
++#define BLOCKABLE()	(!in_interrupt())
++#endif
++
++/* Interrupt handler */
++static irqreturn_t
++sdspi_isr(int irq, void *dev_id
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20)
++, struct pt_regs *ptregs
++#endif
++)
++{
++	sdioh_info_t *sd;
++	struct sdos_info *sdos;
++	bool ours;
++
++	sd = (sdioh_info_t *)dev_id;
++	sd->local_intrcount++;
++
++	if (!sd->card_init_done) {
++		sd_err(("%s: Hey Bogus intr...not even initted: irq %d\n", __FUNCTION__, irq));
++		return IRQ_RETVAL(FALSE);
++	} else {
++		ours = spi_check_client_intr(sd, NULL);
++
++		/* For local interrupts, wake the waiting process */
++		if (ours && sd->got_hcint) {
++			sdos = (struct sdos_info *)sd->sdos_info;
++			wake_up_interruptible(&sdos->intr_wait_queue);
++		}
++
++		return IRQ_RETVAL(ours);
++	}
++}
++
++
++/* Register with Linux for interrupts */
++int
++spi_register_irq(sdioh_info_t *sd, uint irq)
++{
++	sd_trace(("Entering %s: irq == %d\n", __FUNCTION__, irq));
++	if (request_irq(irq, sdspi_isr, IRQF_SHARED, "bcmsdspi", sd) < 0) {
++		sd_err(("%s: request_irq() failed\n", __FUNCTION__));
++		return ERROR;
++	}
++	return SUCCESS;
++}
++
++/* Free Linux irq */
++void
++spi_free_irq(uint irq, sdioh_info_t *sd)
++{
++	free_irq(irq, sd);
++}
++
++/* Map Host controller registers */
++uint32 *
++spi_reg_map(osl_t *osh, uintptr addr, int size)
++{
++	return (uint32 *)REG_MAP(addr, size);
++}
++
++void
++spi_reg_unmap(osl_t *osh, uintptr addr, int size)
++{
++	REG_UNMAP((void*)(uintptr)addr);
++}
++
++int
++spi_osinit(sdioh_info_t *sd)
++{
++	struct sdos_info *sdos;
++
++	sdos = (struct sdos_info*)MALLOC(sd->osh, sizeof(struct sdos_info));
++	sd->sdos_info = (void*)sdos;
++	if (sdos == NULL)
++		return BCME_NOMEM;
++
++	sdos->sd = sd;
++	spin_lock_init(&sdos->lock);
++	init_waitqueue_head(&sdos->intr_wait_queue);
++	return BCME_OK;
++}
++
++void
++spi_osfree(sdioh_info_t *sd)
++{
++	struct sdos_info *sdos;
++	ASSERT(sd && sd->sdos_info);
++
++	sdos = (struct sdos_info *)sd->sdos_info;
++	MFREE(sd->osh, sdos, sizeof(struct sdos_info));
++}
++
++/* Interrupt enable/disable */
++SDIOH_API_RC
++sdioh_interrupt_set(sdioh_info_t *sd, bool enable)
++{
++	ulong flags;
++	struct sdos_info *sdos;
++
++	sd_trace(("%s: %s\n", __FUNCTION__, enable ? "Enabling" : "Disabling"));
++
++	sdos = (struct sdos_info *)sd->sdos_info;
++	ASSERT(sdos);
++
++	if (!(sd->host_init_done && sd->card_init_done)) {
++		sd_err(("%s: Card & Host are not initted - bailing\n", __FUNCTION__));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	if (enable && !(sd->intr_handler && sd->intr_handler_arg)) {
++		sd_err(("%s: no handler registered, will not enable\n", __FUNCTION__));
++		return SDIOH_API_RC_FAIL;
++	}
++
++	/* Ensure atomicity for enable/disable calls */
++	spin_lock_irqsave(&sdos->lock, flags);
++
++	sd->client_intr_enabled = enable;
++	if (enable && !sd->lockcount)
++		spi_devintr_on(sd);
++	else
++		spi_devintr_off(sd);
++
++	spin_unlock_irqrestore(&sdos->lock, flags);
++
++	return SDIOH_API_RC_SUCCESS;
++}
++
++/* Protect against reentrancy (disable device interrupts while executing) */
++void
++spi_lock(sdioh_info_t *sd)
++{
++	ulong flags;
++	struct sdos_info *sdos;
++
++	sdos = (struct sdos_info *)sd->sdos_info;
++	ASSERT(sdos);
++
++	sd_trace(("%s: %d\n", __FUNCTION__, sd->lockcount));
++
++	spin_lock_irqsave(&sdos->lock, flags);
++	if (sd->lockcount) {
++		sd_err(("%s: Already locked!\n", __FUNCTION__));
++		ASSERT(sd->lockcount == 0);
++	}
++	spi_devintr_off(sd);
++	sd->lockcount++;
++	spin_unlock_irqrestore(&sdos->lock, flags);
++}
++
++/* Enable client interrupt */
++void
++spi_unlock(sdioh_info_t *sd)
++{
++	ulong flags;
++	struct sdos_info *sdos;
++
++	sd_trace(("%s: %d, %d\n", __FUNCTION__, sd->lockcount, sd->client_intr_enabled));
++	ASSERT(sd->lockcount > 0);
++
++	sdos = (struct sdos_info *)sd->sdos_info;
++	ASSERT(sdos);
++
++	spin_lock_irqsave(&sdos->lock, flags);
++	if (--sd->lockcount == 0 && sd->client_intr_enabled) {
++		spi_devintr_on(sd);
++	}
++	spin_unlock_irqrestore(&sdos->lock, flags);
++}
++
++void spi_waitbits(sdioh_info_t *sd, bool yield)
++{
++#ifndef BCMSDYIELD
++	ASSERT(!yield);
++#endif
++	sd_trace(("%s: yield %d canblock %d\n",
++	          __FUNCTION__, yield, BLOCKABLE()));
++
++	/* Clear the "interrupt happened" flag and last intrstatus */
++	sd->got_hcint = FALSE;
++
++#ifdef BCMSDYIELD
++	if (yield && BLOCKABLE()) {
++		struct sdos_info *sdos;
++		sdos = (struct sdos_info *)sd->sdos_info;
++		/* Wait for the indication, the interrupt will be masked when the ISR fires. */
++		wait_event_interruptible(sdos->intr_wait_queue, (sd->got_hcint));
++	} else
++#endif /* BCMSDYIELD */
++	{
++		spi_spinbits(sd);
++	}
++
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmspibrcm.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmspibrcm.c
+new file mode 100644
+index 000000000..da6792f06
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmspibrcm.c
+@@ -0,0 +1,1813 @@
++/*
++ * Broadcom BCMSDH to gSPI Protocol Conversion Layer
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmspibrcm.c 514727 2014-11-12 03:02:48Z $
++ */
++
++#define HSMODE
++
++#include <typedefs.h>
++
++#include <bcmdevs.h>
++#include <bcmendian.h>
++#include <bcmutils.h>
++#include <osl.h>
++#include <hndsoc.h>
++#include <siutils.h>
++#include <sbchipc.h>
++#include <sbsdio.h>	/* SDIO device core hardware definitions. */
++#include <spid.h>
++
++#include <bcmsdbus.h>	/* bcmsdh to/from specific controller APIs */
++#include <sdiovar.h>	/* ioctl/iovars */
++#include <sdio.h>	/* SDIO Device and Protocol Specs */
++
++#include <pcicfg.h>
++
++
++#include <bcmspibrcm.h>
++#include <bcmspi.h>
++
++/* these are for the older cores... for newer cores we have control for each of them */
++#define F0_RESPONSE_DELAY	16
++#define F1_RESPONSE_DELAY	16
++#define F2_RESPONSE_DELAY	F0_RESPONSE_DELAY
++
++
++#define GSPI_F0_RESP_DELAY		0
++#define GSPI_F1_RESP_DELAY		F1_RESPONSE_DELAY
++#define GSPI_F2_RESP_DELAY		0
++#define GSPI_F3_RESP_DELAY		0
++
++#define CMDLEN		4
++
++#define DWORDMODE_ON (sd->chip == BCM4329_CHIP_ID) && (sd->chiprev == 2) && (sd->dwordmode == TRUE)
++
++/* Globals */
++#if defined(DHD_DEBUG)
++uint sd_msglevel = SDH_ERROR_VAL;
++#else
++uint sd_msglevel = 0;
++#endif 
++
++uint sd_hiok = FALSE;		/* Use hi-speed mode if available? */
++uint sd_sdmode = SDIOH_MODE_SPI;		/* Use SD4 mode by default */
++uint sd_f2_blocksize = 64;		/* Default blocksize */
++
++
++uint sd_divisor = 2;
++uint sd_power = 1;		/* Default to SD Slot powered ON */
++uint sd_clock = 1;		/* Default to SD Clock turned ON */
++uint sd_crc = 0;		/* Default to SPI CRC Check turned OFF */
++uint sd_pci_slot = 0xFFFFffff; /* Used to force selection of a particular PCI slot */
++
++uint8	spi_outbuf[SPI_MAX_PKT_LEN];
++uint8	spi_inbuf[SPI_MAX_PKT_LEN];
++
++/* 128bytes buffer is enough to clear data-not-available and program response-delay F0 bits
++ * assuming we will not exceed F0 response delay > 100 bytes at 48MHz.
++ */
++#define BUF2_PKT_LEN	128
++uint8	spi_outbuf2[BUF2_PKT_LEN];
++uint8	spi_inbuf2[BUF2_PKT_LEN];
++
++#define SPISWAP_WD4(x) bcmswap32(x);
++#define SPISWAP_WD2(x) (bcmswap16(x & 0xffff)) | \
++						(bcmswap16((x & 0xffff0000) >> 16) << 16);
++
++/* Prototypes */
++static bool bcmspi_test_card(sdioh_info_t *sd);
++static bool bcmspi_host_device_init_adapt(sdioh_info_t *sd);
++static int bcmspi_set_highspeed_mode(sdioh_info_t *sd, bool hsmode);
++static int bcmspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd_arg,
++                           uint32 *data, uint32 datalen);
++static int bcmspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr,
++                              int regsize, uint32 *data);
++static int bcmspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr,
++                               int regsize, uint32 data);
++static int bcmspi_card_bytewrite(sdioh_info_t *sd, int func, uint32 regaddr,
++                               uint8 *data);
++static int bcmspi_driver_init(sdioh_info_t *sd);
++static int bcmspi_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo,
++                          uint32 addr, int nbytes, uint32 *data);
++static int bcmspi_card_regread_fixedaddr(sdioh_info_t *sd, int func, uint32 regaddr, int regsize,
++                                 uint32 *data);
++static void bcmspi_cmd_getdstatus(sdioh_info_t *sd, uint32 *dstatus_buffer);
++static int bcmspi_update_stats(sdioh_info_t *sd, uint32 cmd_arg);
++
++/*
++ *  Public entry points & extern's
++ */
++extern sdioh_info_t *
++sdioh_attach(osl_t *osh, void *bar0, uint irq)
++{
++	sdioh_info_t *sd;
++
++	sd_trace(("%s\n", __FUNCTION__));
++	if ((sd = (sdioh_info_t *)MALLOC(osh, sizeof(sdioh_info_t))) == NULL) {
++		sd_err(("%s: out of memory, malloced %d bytes\n", __FUNCTION__, MALLOCED(osh)));
++		return NULL;
++	}
++	bzero((char *)sd, sizeof(sdioh_info_t));
++	sd->osh = osh;
++	if (spi_osinit(sd) != 0) {
++		sd_err(("%s: spi_osinit() failed\n", __FUNCTION__));
++		MFREE(sd->osh, sd, sizeof(sdioh_info_t));
++		return NULL;
++	}
++
++	sd->bar0 = bar0;
++	sd->irq = irq;
++	sd->intr_handler = NULL;
++	sd->intr_handler_arg = NULL;
++	sd->intr_handler_valid = FALSE;
++
++	/* Set defaults */
++	sd->use_client_ints = TRUE;
++	sd->sd_use_dma = FALSE;	/* DMA Not supported */
++
++	/* Spi device default is 16bit mode, change to 4 when device is changed to 32bit
++	 * mode
++	 */
++	sd->wordlen = 2;
++
++
++	if (!spi_hw_attach(sd)) {
++		sd_err(("%s: spi_hw_attach() failed\n", __FUNCTION__));
++		spi_osfree(sd);
++		MFREE(sd->osh, sd, sizeof(sdioh_info_t));
++		return (NULL);
++	}
++
++	if (bcmspi_driver_init(sd) != SUCCESS) {
++		sd_err(("%s: bcmspi_driver_init() failed()\n", __FUNCTION__));
++		spi_hw_detach(sd);
++		spi_osfree(sd);
++		MFREE(sd->osh, sd, sizeof(sdioh_info_t));
++		return (NULL);
++	}
++
++	if (spi_register_irq(sd, irq) != SUCCESS) {
++		sd_err(("%s: spi_register_irq() failed for irq = %d\n", __FUNCTION__, irq));
++		spi_hw_detach(sd);
++		spi_osfree(sd);
++		MFREE(sd->osh, sd, sizeof(sdioh_info_t));
++		return (NULL);
++	}
++
++	sd_trace(("%s: Done\n", __FUNCTION__));
++
++	return sd;
++}
++
++extern SDIOH_API_RC
++sdioh_detach(osl_t *osh, sdioh_info_t *sd)
++{
++	sd_trace(("%s\n", __FUNCTION__));
++	if (sd) {
++		sd_err(("%s: detaching from hardware\n", __FUNCTION__));
++		spi_free_irq(sd->irq, sd);
++		spi_hw_detach(sd);
++		spi_osfree(sd);
++		MFREE(sd->osh, sd, sizeof(sdioh_info_t));
++	}
++	return SDIOH_API_RC_SUCCESS;
++}
++
++/* Configure callback to client when we recieve client interrupt */
++extern SDIOH_API_RC
++sdioh_interrupt_register(sdioh_info_t *sd, sdioh_cb_fn_t fn, void *argh)
++{
++	sd_trace(("%s: Entering\n", __FUNCTION__));
++#if !defined(OOB_INTR_ONLY)
++	sd->intr_handler = fn;
++	sd->intr_handler_arg = argh;
++	sd->intr_handler_valid = TRUE;
++#endif /* !defined(OOB_INTR_ONLY) */
++	return SDIOH_API_RC_SUCCESS;
++}
++
++extern SDIOH_API_RC
++sdioh_interrupt_deregister(sdioh_info_t *sd)
++{
++	sd_trace(("%s: Entering\n", __FUNCTION__));
++#if !defined(OOB_INTR_ONLY)
++	sd->intr_handler_valid = FALSE;
++	sd->intr_handler = NULL;
++	sd->intr_handler_arg = NULL;
++#endif /* !defined(OOB_INTR_ONLY) */
++	return SDIOH_API_RC_SUCCESS;
++}
++
++extern SDIOH_API_RC
++sdioh_interrupt_query(sdioh_info_t *sd, bool *onoff)
++{
++	sd_trace(("%s: Entering\n", __FUNCTION__));
++	*onoff = sd->client_intr_enabled;
++	return SDIOH_API_RC_SUCCESS;
++}
++
++#if defined(DHD_DEBUG)
++extern bool
++sdioh_interrupt_pending(sdioh_info_t *sd)
++{
++	return 0;
++}
++#endif
++
++extern SDIOH_API_RC
++sdioh_query_device(sdioh_info_t *sd)
++{
++	/* Return a BRCM ID appropriate to the dongle class */
++	return (sd->num_funcs > 1) ? BCM4329_D11N_ID : BCM4318_D11G_ID;
++}
++
++/* Provide dstatus bits of spi-transaction for dhd layers. */
++extern uint32
++sdioh_get_dstatus(sdioh_info_t *sd)
++{
++	return sd->card_dstatus;
++}
++
++extern void
++sdioh_chipinfo(sdioh_info_t *sd, uint32 chip, uint32 chiprev)
++{
++	sd->chip = chip;
++	sd->chiprev = chiprev;
++}
++
++extern void
++sdioh_dwordmode(sdioh_info_t *sd, bool set)
++{
++	uint8 reg = 0;
++	int status;
++
++	if ((status = sdioh_request_byte(sd, SDIOH_READ, SPI_FUNC_0, SPID_STATUS_ENABLE, &reg)) !=
++	     SUCCESS) {
++		sd_err(("%s: Failed to set dwordmode in gSPI\n", __FUNCTION__));
++		return;
++	}
++
++	if (set) {
++		reg |= DWORD_PKT_LEN_EN;
++		sd->dwordmode = TRUE;
++		sd->client_block_size[SPI_FUNC_2] = 4096; /* h2spi's limit is 4KB, we support 8KB */
++	} else {
++		reg &= ~DWORD_PKT_LEN_EN;
++		sd->dwordmode = FALSE;
++		sd->client_block_size[SPI_FUNC_2] = 2048;
++	}
++
++	if ((status = sdioh_request_byte(sd, SDIOH_WRITE, SPI_FUNC_0, SPID_STATUS_ENABLE, &reg)) !=
++	     SUCCESS) {
++		sd_err(("%s: Failed to set dwordmode in gSPI\n", __FUNCTION__));
++		return;
++	}
++}
++
++
++uint
++sdioh_query_iofnum(sdioh_info_t *sd)
++{
++	return sd->num_funcs;
++}
++
++/* IOVar table */
++enum {
++	IOV_MSGLEVEL = 1,
++	IOV_BLOCKMODE,
++	IOV_BLOCKSIZE,
++	IOV_DMA,
++	IOV_USEINTS,
++	IOV_NUMINTS,
++	IOV_NUMLOCALINTS,
++	IOV_HOSTREG,
++	IOV_DEVREG,
++	IOV_DIVISOR,
++	IOV_SDMODE,
++	IOV_HISPEED,
++	IOV_HCIREGS,
++	IOV_POWER,
++	IOV_CLOCK,
++	IOV_SPIERRSTATS,
++	IOV_RESP_DELAY_ALL
++};
++
++const bcm_iovar_t sdioh_iovars[] = {
++	{"sd_msglevel",	IOV_MSGLEVEL, 	0,	IOVT_UINT32,	0 },
++	{"sd_blocksize", IOV_BLOCKSIZE, 0,	IOVT_UINT32,	0 }, /* ((fn << 16) | size) */
++	{"sd_dma",	IOV_DMA,	0,	IOVT_BOOL,	0 },
++	{"sd_ints",	IOV_USEINTS,	0,	IOVT_BOOL,	0 },
++	{"sd_numints",	IOV_NUMINTS,	0,	IOVT_UINT32,	0 },
++	{"sd_numlocalints", IOV_NUMLOCALINTS, 0, IOVT_UINT32,	0 },
++	{"sd_hostreg",	IOV_HOSTREG,	0,	IOVT_BUFFER,	sizeof(sdreg_t) },
++	{"sd_devreg",	IOV_DEVREG,	0,	IOVT_BUFFER,	sizeof(sdreg_t)	},
++	{"sd_divisor",	IOV_DIVISOR,	0,	IOVT_UINT32,	0 },
++	{"sd_power",	IOV_POWER,	0,	IOVT_UINT32,	0 },
++	{"sd_clock",	IOV_CLOCK,	0,	IOVT_UINT32,	0 },
++	{"sd_mode",	IOV_SDMODE,	0,	IOVT_UINT32,	100},
++	{"sd_highspeed",	IOV_HISPEED,	0,	IOVT_UINT32,	0},
++	{"spi_errstats", IOV_SPIERRSTATS, 0, IOVT_BUFFER, sizeof(struct spierrstats_t) },
++	{"spi_respdelay",	IOV_RESP_DELAY_ALL,	0,	IOVT_BOOL,	0 },
++	{NULL, 0, 0, 0, 0 }
++};
++
++int
++sdioh_iovar_op(sdioh_info_t *si, const char *name,
++               void *params, int plen, void *arg, int len, bool set)
++{
++	const bcm_iovar_t *vi = NULL;
++	int bcmerror = 0;
++	int val_size;
++	int32 int_val = 0;
++	bool bool_val;
++	uint32 actionid;
++/*
++	sdioh_regs_t *regs;
++*/
++
++	ASSERT(name);
++	ASSERT(len >= 0);
++
++	/* Get must have return space; Set does not take qualifiers */
++	ASSERT(set || (arg && len));
++	ASSERT(!set || (!params && !plen));
++
++	sd_trace(("%s: Enter (%s %s)\n", __FUNCTION__, (set ? "set" : "get"), name));
++
++	if ((vi = bcm_iovar_lookup(sdioh_iovars, name)) == NULL) {
++		bcmerror = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++	if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, set)) != 0)
++		goto exit;
++
++	/* Set up params so get and set can share the convenience variables */
++	if (params == NULL) {
++		params = arg;
++		plen = len;
++	}
++
++	if (vi->type == IOVT_VOID)
++		val_size = 0;
++	else if (vi->type == IOVT_BUFFER)
++		val_size = len;
++	else
++		val_size = sizeof(int);
++
++	if (plen >= (int)sizeof(int_val))
++		bcopy(params, &int_val, sizeof(int_val));
++
++	bool_val = (int_val != 0) ? TRUE : FALSE;
++
++	actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
++	switch (actionid) {
++	case IOV_GVAL(IOV_MSGLEVEL):
++		int_val = (int32)sd_msglevel;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_MSGLEVEL):
++		sd_msglevel = int_val;
++		break;
++
++	case IOV_GVAL(IOV_BLOCKSIZE):
++		if ((uint32)int_val > si->num_funcs) {
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		int_val = (int32)si->client_block_size[int_val];
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_DMA):
++		int_val = (int32)si->sd_use_dma;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DMA):
++		si->sd_use_dma = (bool)int_val;
++		break;
++
++	case IOV_GVAL(IOV_USEINTS):
++		int_val = (int32)si->use_client_ints;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_USEINTS):
++		break;
++
++	case IOV_GVAL(IOV_DIVISOR):
++		int_val = (uint32)sd_divisor;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DIVISOR):
++		sd_divisor = int_val;
++		if (!spi_start_clock(si, (uint16)sd_divisor)) {
++			sd_err(("%s: set clock failed\n", __FUNCTION__));
++			bcmerror = BCME_ERROR;
++		}
++		break;
++
++	case IOV_GVAL(IOV_POWER):
++		int_val = (uint32)sd_power;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_POWER):
++		sd_power = int_val;
++		break;
++
++	case IOV_GVAL(IOV_CLOCK):
++		int_val = (uint32)sd_clock;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_CLOCK):
++		sd_clock = int_val;
++		break;
++
++	case IOV_GVAL(IOV_SDMODE):
++		int_val = (uint32)sd_sdmode;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_SDMODE):
++		sd_sdmode = int_val;
++		break;
++
++	case IOV_GVAL(IOV_HISPEED):
++		int_val = (uint32)sd_hiok;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_HISPEED):
++		sd_hiok = int_val;
++
++		if (!bcmspi_set_highspeed_mode(si, (bool)sd_hiok)) {
++			sd_err(("%s: Failed changing highspeed mode to %d.\n",
++			        __FUNCTION__, sd_hiok));
++			bcmerror = BCME_ERROR;
++			return ERROR;
++		}
++		break;
++
++	case IOV_GVAL(IOV_NUMINTS):
++		int_val = (int32)si->intrcount;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_NUMLOCALINTS):
++		int_val = (int32)si->local_intrcount;
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_GVAL(IOV_DEVREG):
++	{
++		sdreg_t *sd_ptr = (sdreg_t *)params;
++		uint8 data;
++
++		if (sdioh_cfg_read(si, sd_ptr->func, sd_ptr->offset, &data)) {
++			bcmerror = BCME_SDIO_ERROR;
++			break;
++		}
++
++		int_val = (int)data;
++		bcopy(&int_val, arg, sizeof(int_val));
++		break;
++	}
++
++	case IOV_SVAL(IOV_DEVREG):
++	{
++		sdreg_t *sd_ptr = (sdreg_t *)params;
++		uint8 data = (uint8)sd_ptr->value;
++
++		if (sdioh_cfg_write(si, sd_ptr->func, sd_ptr->offset, &data)) {
++			bcmerror = BCME_SDIO_ERROR;
++			break;
++		}
++		break;
++	}
++
++
++	case IOV_GVAL(IOV_SPIERRSTATS):
++	{
++		bcopy(&si->spierrstats, arg, sizeof(struct spierrstats_t));
++		break;
++	}
++
++	case IOV_SVAL(IOV_SPIERRSTATS):
++	{
++		bzero(&si->spierrstats, sizeof(struct spierrstats_t));
++		break;
++	}
++
++	case IOV_GVAL(IOV_RESP_DELAY_ALL):
++		int_val = (int32)si->resp_delay_all;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_RESP_DELAY_ALL):
++		si->resp_delay_all = (bool)int_val;
++		int_val = STATUS_ENABLE|INTR_WITH_STATUS;
++		if (si->resp_delay_all)
++			int_val |= RESP_DELAY_ALL;
++		else {
++			if (bcmspi_card_regwrite(si, SPI_FUNC_0, SPID_RESPONSE_DELAY, 1,
++			     F1_RESPONSE_DELAY) != SUCCESS) {
++				sd_err(("%s: Unable to set response delay.\n", __FUNCTION__));
++				bcmerror = BCME_SDIO_ERROR;
++				break;
++			}
++		}
++
++		if (bcmspi_card_regwrite(si, SPI_FUNC_0, SPID_STATUS_ENABLE, 1, int_val)
++		     != SUCCESS) {
++			sd_err(("%s: Unable to set response delay.\n", __FUNCTION__));
++			bcmerror = BCME_SDIO_ERROR;
++			break;
++		}
++		break;
++
++	default:
++		bcmerror = BCME_UNSUPPORTED;
++		break;
++	}
++exit:
++
++	return bcmerror;
++}
++
++extern SDIOH_API_RC
++sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
++{
++	SDIOH_API_RC status;
++	/* No lock needed since sdioh_request_byte does locking */
++	status = sdioh_request_byte(sd, SDIOH_READ, fnc_num, addr, data);
++	return status;
++}
++
++extern SDIOH_API_RC
++sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
++{
++	/* No lock needed since sdioh_request_byte does locking */
++	SDIOH_API_RC status;
++
++	if ((fnc_num == SPI_FUNC_1) && (addr == SBSDIO_FUNC1_FRAMECTRL)) {
++		uint8 dummy_data;
++		status = sdioh_cfg_read(sd, fnc_num, addr, &dummy_data);
++		if (status) {
++			sd_err(("sdioh_cfg_read() failed.\n"));
++			return status;
++		}
++	}
++
++	status = sdioh_request_byte(sd, SDIOH_WRITE, fnc_num, addr, data);
++	return status;
++}
++
++extern SDIOH_API_RC
++sdioh_cis_read(sdioh_info_t *sd, uint func, uint8 *cisd, uint32 length)
++{
++	uint32 count;
++	int offset;
++	uint32 cis_byte;
++	uint16 *cis = (uint16 *)cisd;
++	uint bar0 = SI_ENUM_BASE;
++	int status;
++	uint8 data;
++
++	sd_trace(("%s: Func %d\n", __FUNCTION__, func));
++
++	spi_lock(sd);
++
++	/* Set sb window address to 0x18000000 */
++	data = (bar0 >> 8) & SBSDIO_SBADDRLOW_MASK;
++	status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW, &data);
++	if (status == SUCCESS) {
++		data = (bar0 >> 16) & SBSDIO_SBADDRMID_MASK;
++		status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID, &data);
++	} else {
++		sd_err(("%s: Unable to set sb-addr-windows\n", __FUNCTION__));
++		spi_unlock(sd);
++		return (BCME_ERROR);
++	}
++	if (status == SUCCESS) {
++		data = (bar0 >> 24) & SBSDIO_SBADDRHIGH_MASK;
++		status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH, &data);
++	} else {
++		sd_err(("%s: Unable to set sb-addr-windows\n", __FUNCTION__));
++		spi_unlock(sd);
++		return (BCME_ERROR);
++	}
++
++	offset =  CC_SROM_OTP; /* OTP offset in chipcommon. */
++	for (count = 0; count < length/2; count++) {
++		if (bcmspi_card_regread (sd, SDIO_FUNC_1, offset, 2, &cis_byte) < 0) {
++			sd_err(("%s: regread failed: Can't read CIS\n", __FUNCTION__));
++			spi_unlock(sd);
++			return (BCME_ERROR);
++		}
++
++		*cis = (uint16)cis_byte;
++		cis++;
++		offset += 2;
++	}
++
++	spi_unlock(sd);
++
++	return (BCME_OK);
++}
++
++extern SDIOH_API_RC
++sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr, uint8 *byte)
++{
++	int status;
++	uint32 cmd_arg;
++	uint32 dstatus;
++	uint32 data = (uint32)(*byte);
++
++	spi_lock(sd);
++
++	cmd_arg = 0;
++	cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
++	cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1);	/* Incremental access */
++	cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
++	cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, rw == SDIOH_READ ? 0 : 1);
++	cmd_arg = SFIELD(cmd_arg, SPI_LEN, 1);
++
++	if (rw == SDIOH_READ) {
++		sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x\n",
++		          __FUNCTION__, cmd_arg, func, regaddr));
++	} else {
++		sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x data=0x%x\n",
++		          __FUNCTION__, cmd_arg, func, regaddr, data));
++	}
++
++	if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, 1)) != SUCCESS) {
++		spi_unlock(sd);
++		return status;
++	}
++
++	if (rw == SDIOH_READ) {
++		*byte = (uint8)data;
++		sd_trace(("%s: RD result=0x%x\n", __FUNCTION__, *byte));
++	}
++
++	bcmspi_cmd_getdstatus(sd, &dstatus);
++	if (dstatus)
++		sd_trace(("dstatus=0x%x\n", dstatus));
++
++	spi_unlock(sd);
++	return SDIOH_API_RC_SUCCESS;
++}
++
++extern SDIOH_API_RC
++sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func, uint addr,
++                   uint32 *word, uint nbytes)
++{
++	int status;
++
++	spi_lock(sd);
++
++	if (rw == SDIOH_READ)
++		status = bcmspi_card_regread(sd, func, addr, nbytes, word);
++	else
++		status = bcmspi_card_regwrite(sd, func, addr, nbytes, *word);
++
++	spi_unlock(sd);
++	return (status == SUCCESS ?  SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
++}
++
++extern SDIOH_API_RC
++sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint rw, uint func,
++                     uint addr, uint reg_width, uint buflen_u, uint8 *buffer, void *pkt)
++{
++	int len;
++	int buflen = (int)buflen_u;
++	bool fifo = (fix_inc == SDIOH_DATA_FIX);
++
++	spi_lock(sd);
++
++	ASSERT(reg_width == 4);
++	ASSERT(buflen_u < (1 << 30));
++	ASSERT(sd->client_block_size[func]);
++
++	sd_data(("%s: %c len %d r_cnt %d t_cnt %d, pkt @0x%p\n",
++	         __FUNCTION__, rw == SDIOH_READ ? 'R' : 'W',
++	         buflen_u, sd->r_cnt, sd->t_cnt, pkt));
++
++	/* Break buffer down into blocksize chunks. */
++	while (buflen > 0) {
++		len = MIN(sd->client_block_size[func], buflen);
++		if (bcmspi_card_buf(sd, rw, func, fifo, addr, len, (uint32 *)buffer) != SUCCESS) {
++			sd_err(("%s: bcmspi_card_buf %s failed\n",
++				__FUNCTION__, rw == SDIOH_READ ? "Read" : "Write"));
++			spi_unlock(sd);
++			return SDIOH_API_RC_FAIL;
++		}
++		buffer += len;
++		buflen -= len;
++		if (!fifo)
++			addr += len;
++	}
++	spi_unlock(sd);
++	return SDIOH_API_RC_SUCCESS;
++}
++
++/* This function allows write to gspi bus when another rd/wr function is deep down the call stack.
++ * Its main aim is to have simpler spi writes rather than recursive writes.
++ * e.g. When there is a need to program response delay on the fly after detecting the SPI-func
++ * this call will allow to program the response delay.
++ */
++static int
++bcmspi_card_byterewrite(sdioh_info_t *sd, int func, uint32 regaddr, uint8 byte)
++{
++	uint32 cmd_arg;
++	uint32 datalen = 1;
++	uint32 hostlen;
++
++	cmd_arg = 0;
++
++	cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
++	cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1);	/* Incremental access */
++	cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
++	cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
++	cmd_arg = SFIELD(cmd_arg, SPI_LEN, datalen);
++
++	sd_trace(("%s cmd_arg = 0x%x\n", __FUNCTION__, cmd_arg));
++
++
++	/* Set up and issue the SPI command.  MSByte goes out on bus first.  Increase datalen
++	 * according to the wordlen mode(16/32bit) the device is in.
++	 */
++	ASSERT(sd->wordlen == 4 || sd->wordlen == 2);
++	datalen = ROUNDUP(datalen, sd->wordlen);
++
++	/* Start by copying command in the spi-outbuffer */
++	if (sd->wordlen == 4) { /* 32bit spid */
++		*(uint32 *)spi_outbuf2 = SPISWAP_WD4(cmd_arg);
++		if (datalen & 0x3)
++			datalen += (4 - (datalen & 0x3));
++	} else if (sd->wordlen == 2) { /* 16bit spid */
++		*(uint32 *)spi_outbuf2 = SPISWAP_WD2(cmd_arg);
++		if (datalen & 0x1)
++			datalen++;
++	} else {
++		sd_err(("%s: Host is %d bit spid, could not create SPI command.\n",
++		        __FUNCTION__, 8 * sd->wordlen));
++		return ERROR;
++	}
++
++	/* for Write, put the data into the output buffer  */
++	if (datalen != 0) {
++			if (sd->wordlen == 4) { /* 32bit spid */
++				*(uint32 *)&spi_outbuf2[CMDLEN] = SPISWAP_WD4(byte);
++			} else if (sd->wordlen == 2) { /* 16bit spid */
++				*(uint32 *)&spi_outbuf2[CMDLEN] = SPISWAP_WD2(byte);
++			}
++	}
++
++	/* +4 for cmd, +4 for dstatus */
++	hostlen = datalen + 8;
++	hostlen += (4 - (hostlen & 0x3));
++	spi_sendrecv(sd, spi_outbuf2, spi_inbuf2, hostlen);
++
++	/* Last 4bytes are dstatus.  Device is configured to return status bits. */
++	if (sd->wordlen == 4) { /* 32bit spid */
++		sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
++	} else if (sd->wordlen == 2) { /* 16bit spid */
++		sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
++	} else {
++		sd_err(("%s: Host is %d bit machine, could not read SPI dstatus.\n",
++		        __FUNCTION__, 8 * sd->wordlen));
++		return ERROR;
++	}
++
++	if (sd->card_dstatus)
++		sd_trace(("dstatus after byte rewrite = 0x%x\n", sd->card_dstatus));
++
++	return (BCME_OK);
++}
++
++/* Program the response delay corresponding to the spi function */
++static int
++bcmspi_prog_resp_delay(sdioh_info_t *sd, int func, uint8 resp_delay)
++{
++	if (sd->resp_delay_all == FALSE)
++		return (BCME_OK);
++
++	if (sd->prev_fun == func)
++		return (BCME_OK);
++
++	if (F0_RESPONSE_DELAY == F1_RESPONSE_DELAY)
++		return (BCME_OK);
++
++	bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_RESPONSE_DELAY, resp_delay);
++
++	/* Remember function for which to avoid reprogramming resp-delay in next iteration */
++	sd->prev_fun = func;
++
++	return (BCME_OK);
++
++}
++
++#define GSPI_RESYNC_PATTERN	0x0
++
++/* A resync pattern is a 32bit MOSI line with all zeros. Its a special command in gSPI.
++ * It resets the spi-bkplane logic so that all F1 related ping-pong buffer logic is
++ * synchronised and all queued resuests are cancelled.
++ */
++static int
++bcmspi_resync_f1(sdioh_info_t *sd)
++{
++	uint32 cmd_arg = GSPI_RESYNC_PATTERN, data = 0, datalen = 0;
++
++
++	/* Set up and issue the SPI command.  MSByte goes out on bus first.  Increase datalen
++	 * according to the wordlen mode(16/32bit) the device is in.
++	 */
++	ASSERT(sd->wordlen == 4 || sd->wordlen == 2);
++	datalen = ROUNDUP(datalen, sd->wordlen);
++
++	/* Start by copying command in the spi-outbuffer */
++	*(uint32 *)spi_outbuf2 = cmd_arg;
++
++	/* for Write, put the data into the output buffer  */
++	*(uint32 *)&spi_outbuf2[CMDLEN] = data;
++
++	/* +4 for cmd, +4 for dstatus */
++	spi_sendrecv(sd, spi_outbuf2, spi_inbuf2, datalen + 8);
++
++	/* Last 4bytes are dstatus.  Device is configured to return status bits. */
++	if (sd->wordlen == 4) { /* 32bit spid */
++		sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
++	} else if (sd->wordlen == 2) { /* 16bit spid */
++		sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
++	} else {
++		sd_err(("%s: Host is %d bit machine, could not read SPI dstatus.\n",
++		        __FUNCTION__, 8 * sd->wordlen));
++		return ERROR;
++	}
++
++	if (sd->card_dstatus)
++		sd_trace(("dstatus after resync pattern write = 0x%x\n", sd->card_dstatus));
++
++	return (BCME_OK);
++}
++
++uint32 dstatus_count = 0;
++
++static int
++bcmspi_update_stats(sdioh_info_t *sd, uint32 cmd_arg)
++{
++	uint32 dstatus = sd->card_dstatus;
++	struct spierrstats_t *spierrstats = &sd->spierrstats;
++	int err = SUCCESS;
++
++	sd_trace(("cmd = 0x%x, dstatus = 0x%x\n", cmd_arg, dstatus));
++
++	/* Store dstatus of last few gSPI transactions */
++	spierrstats->dstatus[dstatus_count % NUM_PREV_TRANSACTIONS] = dstatus;
++	spierrstats->spicmd[dstatus_count % NUM_PREV_TRANSACTIONS] = cmd_arg;
++	dstatus_count++;
++
++	if (sd->card_init_done == FALSE)
++		return err;
++
++	if (dstatus & STATUS_DATA_NOT_AVAILABLE) {
++		spierrstats->dna++;
++		sd_trace(("Read data not available on F1 addr = 0x%x\n",
++		        GFIELD(cmd_arg, SPI_REG_ADDR)));
++		/* Clear dna bit */
++		bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_INTR_REG, DATA_UNAVAILABLE);
++	}
++
++	if (dstatus & STATUS_UNDERFLOW) {
++		spierrstats->rdunderflow++;
++		sd_err(("FIFO underflow happened due to current F2 read command.\n"));
++	}
++
++	if (dstatus & STATUS_OVERFLOW) {
++		spierrstats->wroverflow++;
++		sd_err(("FIFO overflow happened due to current (F1/F2) write command.\n"));
++		bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_INTR_REG, F1_OVERFLOW);
++		bcmspi_resync_f1(sd);
++		sd_err(("Recovering from F1 FIFO overflow.\n"));
++	}
++
++	if (dstatus & STATUS_F2_INTR) {
++		spierrstats->f2interrupt++;
++		sd_trace(("Interrupt from F2.  SW should clear corresponding IntStatus bits\n"));
++	}
++
++	if (dstatus & STATUS_F3_INTR) {
++		spierrstats->f3interrupt++;
++		sd_err(("Interrupt from F3.  SW should clear corresponding IntStatus bits\n"));
++	}
++
++	if (dstatus & STATUS_HOST_CMD_DATA_ERR) {
++		spierrstats->hostcmddataerr++;
++		sd_err(("Error in CMD or Host data, detected by CRC/Checksum (optional)\n"));
++	}
++
++	if (dstatus & STATUS_F2_PKT_AVAILABLE) {
++		spierrstats->f2pktavailable++;
++		sd_trace(("Packet is available/ready in F2 TX FIFO\n"));
++		sd_trace(("Packet length = %d\n", sd->dwordmode ?
++		         ((dstatus & STATUS_F2_PKT_LEN_MASK) >> (STATUS_F2_PKT_LEN_SHIFT - 2)) :
++		         ((dstatus & STATUS_F2_PKT_LEN_MASK) >> STATUS_F2_PKT_LEN_SHIFT)));
++	}
++
++	if (dstatus & STATUS_F3_PKT_AVAILABLE) {
++		spierrstats->f3pktavailable++;
++		sd_err(("Packet is available/ready in F3 TX FIFO\n"));
++		sd_err(("Packet length = %d\n",
++		        (dstatus & STATUS_F3_PKT_LEN_MASK) >> STATUS_F3_PKT_LEN_SHIFT));
++	}
++
++	return err;
++}
++
++extern int
++sdioh_abort(sdioh_info_t *sd, uint func)
++{
++	return 0;
++}
++
++int
++sdioh_start(sdioh_info_t *sd, int stage)
++{
++	return SUCCESS;
++}
++
++int
++sdioh_stop(sdioh_info_t *sd)
++{
++	return SUCCESS;
++}
++
++int
++sdioh_waitlockfree(sdioh_info_t *sd)
++{
++	return SUCCESS;
++}
++
++
++/*
++ * Private/Static work routines
++ */
++static int
++bcmspi_host_init(sdioh_info_t *sd)
++{
++
++	/* Default power on mode */
++	sd->sd_mode = SDIOH_MODE_SPI;
++	sd->polled_mode = TRUE;
++	sd->host_init_done = TRUE;
++	sd->card_init_done = FALSE;
++	sd->adapter_slot = 1;
++
++	return (SUCCESS);
++}
++
++static int
++get_client_blocksize(sdioh_info_t *sd)
++{
++	uint32 regdata[2];
++	int status;
++
++	/* Find F1/F2/F3 max packet size */
++	if ((status = bcmspi_card_regread(sd, 0, SPID_F1_INFO_REG,
++	                                 8, regdata)) != SUCCESS) {
++		return status;
++	}
++
++	sd_trace(("pkt_size regdata[0] = 0x%x, regdata[1] = 0x%x\n",
++	        regdata[0], regdata[1]));
++
++	sd->client_block_size[1] = (regdata[0] & F1_MAX_PKT_SIZE) >> 2;
++	sd_trace(("Func1 blocksize = %d\n", sd->client_block_size[1]));
++	ASSERT(sd->client_block_size[1] == BLOCK_SIZE_F1);
++
++	sd->client_block_size[2] = ((regdata[0] >> 16) & F2_MAX_PKT_SIZE) >> 2;
++	sd_trace(("Func2 blocksize = %d\n", sd->client_block_size[2]));
++	ASSERT(sd->client_block_size[2] == BLOCK_SIZE_F2);
++
++	sd->client_block_size[3] = (regdata[1] & F3_MAX_PKT_SIZE) >> 2;
++	sd_trace(("Func3 blocksize = %d\n", sd->client_block_size[3]));
++	ASSERT(sd->client_block_size[3] == BLOCK_SIZE_F3);
++
++	return 0;
++}
++
++static int
++bcmspi_client_init(sdioh_info_t *sd)
++{
++	uint32	status_en_reg = 0;
++	sd_trace(("%s: Powering up slot %d\n", __FUNCTION__, sd->adapter_slot));
++
++#ifdef HSMODE
++	if (!spi_start_clock(sd, (uint16)sd_divisor)) {
++		sd_err(("spi_start_clock failed\n"));
++		return ERROR;
++	}
++#else
++	/* Start at ~400KHz clock rate for initialization */
++	if (!spi_start_clock(sd, 128)) {
++		sd_err(("spi_start_clock failed\n"));
++		return ERROR;
++	}
++#endif /* HSMODE */
++
++	if (!bcmspi_host_device_init_adapt(sd)) {
++		sd_err(("bcmspi_host_device_init_adapt failed\n"));
++		return ERROR;
++	}
++
++	if (!bcmspi_test_card(sd)) {
++		sd_err(("bcmspi_test_card failed\n"));
++		return ERROR;
++	}
++
++	sd->num_funcs = SPI_MAX_IOFUNCS;
++
++	get_client_blocksize(sd);
++
++	/* Apply resync pattern cmd with all zeros to reset spi-bkplane F1 logic */
++	bcmspi_resync_f1(sd);
++
++	sd->dwordmode = FALSE;
++
++	bcmspi_card_regread(sd, 0, SPID_STATUS_ENABLE, 1, &status_en_reg);
++
++	sd_trace(("%s: Enabling interrupt with dstatus \n", __FUNCTION__));
++	status_en_reg |= INTR_WITH_STATUS;
++
++	if (bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_STATUS_ENABLE, 1,
++	    status_en_reg & 0xff) != SUCCESS) {
++		sd_err(("%s: Unable to set response delay for all fun's.\n", __FUNCTION__));
++		return ERROR;
++	}
++
++#ifndef HSMODE
++	/* After configuring for High-Speed mode, set the desired clock rate. */
++	if (!spi_start_clock(sd, 4)) {
++		sd_err(("spi_start_clock failed\n"));
++		return ERROR;
++	}
++#endif /* HSMODE */
++
++	/* check to see if the response delay needs to be programmed properly */
++	{
++		uint32 f1_respdelay = 0;
++		bcmspi_card_regread(sd, 0, SPID_RESP_DELAY_F1, 1, &f1_respdelay);
++		if ((f1_respdelay == 0) || (f1_respdelay == 0xFF)) {
++			/* older sdiodevice core and has no separte resp delay for each of */
++			sd_err(("older corerev < 4 so use the same resp delay for all funcs\n"));
++			sd->resp_delay_new = FALSE;
++		}
++		else {
++			/* older sdiodevice core and has no separte resp delay for each of */
++			int ret_val;
++			sd->resp_delay_new = TRUE;
++			sd_err(("new corerev >= 4 so set the resp delay for each of the funcs\n"));
++			sd_trace(("resp delay for funcs f0(%d), f1(%d), f2(%d), f3(%d)\n",
++				GSPI_F0_RESP_DELAY, GSPI_F1_RESP_DELAY,
++				GSPI_F2_RESP_DELAY, GSPI_F3_RESP_DELAY));
++			ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F0, 1,
++				GSPI_F0_RESP_DELAY);
++			if (ret_val != SUCCESS) {
++				sd_err(("%s: Unable to set response delay for F0\n", __FUNCTION__));
++				return ERROR;
++			}
++			ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F1, 1,
++				GSPI_F1_RESP_DELAY);
++			if (ret_val != SUCCESS) {
++				sd_err(("%s: Unable to set response delay for F1\n", __FUNCTION__));
++				return ERROR;
++			}
++			ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F2, 1,
++				GSPI_F2_RESP_DELAY);
++			if (ret_val != SUCCESS) {
++				sd_err(("%s: Unable to set response delay for F2\n", __FUNCTION__));
++				return ERROR;
++			}
++			ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F3, 1,
++				GSPI_F3_RESP_DELAY);
++			if (ret_val != SUCCESS) {
++				sd_err(("%s: Unable to set response delay for F2\n", __FUNCTION__));
++				return ERROR;
++			}
++		}
++	}
++
++
++	sd->card_init_done = TRUE;
++
++	/* get the device rev to program the prop respdelays */
++
++	return SUCCESS;
++}
++
++static int
++bcmspi_set_highspeed_mode(sdioh_info_t *sd, bool hsmode)
++{
++	uint32 regdata;
++	int status;
++
++	if ((status = bcmspi_card_regread(sd, 0, SPID_CONFIG,
++	                                 4, &regdata)) != SUCCESS)
++		return status;
++
++	sd_trace(("In %s spih-ctrl = 0x%x \n", __FUNCTION__, regdata));
++
++
++	if (hsmode == TRUE) {
++		sd_trace(("Attempting to enable High-Speed mode.\n"));
++
++		if (regdata & HIGH_SPEED_MODE) {
++			sd_trace(("Device is already in High-Speed mode.\n"));
++			return status;
++		} else {
++			regdata |= HIGH_SPEED_MODE;
++			sd_trace(("Writing %08x to device at %08x\n", regdata, SPID_CONFIG));
++			if ((status = bcmspi_card_regwrite(sd, 0, SPID_CONFIG,
++			                                  4, regdata)) != SUCCESS) {
++				return status;
++			}
++		}
++	} else {
++		sd_trace(("Attempting to disable High-Speed mode.\n"));
++
++		if (regdata & HIGH_SPEED_MODE) {
++			regdata &= ~HIGH_SPEED_MODE;
++			sd_trace(("Writing %08x to device at %08x\n", regdata, SPID_CONFIG));
++			if ((status = bcmspi_card_regwrite(sd, 0, SPID_CONFIG,
++			                                  4, regdata)) != SUCCESS)
++				return status;
++		}
++		 else {
++			sd_trace(("Device is already in Low-Speed mode.\n"));
++			return status;
++		}
++	}
++	spi_controller_highspeed_mode(sd, hsmode);
++
++	return TRUE;
++}
++
++#define bcmspi_find_curr_mode(sd) { \
++	sd->wordlen = 2; \
++	status = bcmspi_card_regread_fixedaddr(sd, 0, SPID_TEST_READ, 4, &regdata); \
++	regdata &= 0xff; \
++	if ((regdata == 0xad) || (regdata == 0x5b) || \
++	    (regdata == 0x5d) || (regdata == 0x5a)) \
++		break; \
++	sd->wordlen = 4; \
++	status = bcmspi_card_regread_fixedaddr(sd, 0, SPID_TEST_READ, 4, &regdata); \
++	regdata &= 0xff; \
++	if ((regdata == 0xad) || (regdata == 0x5b) || \
++	    (regdata == 0x5d) || (regdata == 0x5a)) \
++		break; \
++	sd_trace(("Silicon testability issue: regdata = 0x%x." \
++		" Expected 0xad, 0x5a, 0x5b or 0x5d.\n", regdata)); \
++	OSL_DELAY(100000); \
++}
++
++#define INIT_ADAPT_LOOP		100
++
++/* Adapt clock-phase-speed-bitwidth between host and device */
++static bool
++bcmspi_host_device_init_adapt(sdioh_info_t *sd)
++{
++	uint32 wrregdata, regdata = 0;
++	int status;
++	int i;
++
++	/* Due to a silicon testability issue, the first command from the Host
++	 * to the device will get corrupted (first bit will be lost). So the
++	 * Host should poll the device with a safe read request. ie: The Host
++	 * should try to read F0 addr 0x14 using the Fixed address mode
++	 * (This will prevent a unintended write command to be detected by device)
++	 */
++	for (i = 0; i < INIT_ADAPT_LOOP; i++) {
++	/* If device was not power-cycled it will stay in 32bit mode with
++	 * response-delay-all bit set.  Alternate the iteration so that
++	 * read either with or without response-delay for F0 to succeed.
++	 */
++		bcmspi_find_curr_mode(sd);
++		sd->resp_delay_all = (i & 0x1) ? TRUE : FALSE;
++
++		bcmspi_find_curr_mode(sd);
++		sd->dwordmode = TRUE;
++
++		bcmspi_find_curr_mode(sd);
++		sd->dwordmode = FALSE;
++	}
++
++	/* Bail out, device not detected */
++	if (i == INIT_ADAPT_LOOP)
++		return FALSE;
++
++	/* Softreset the spid logic */
++	if ((sd->dwordmode) || (sd->wordlen == 4)) {
++		bcmspi_card_regwrite(sd, 0, SPID_RESET_BP, 1, RESET_ON_WLAN_BP_RESET|RESET_SPI);
++		bcmspi_card_regread(sd, 0, SPID_RESET_BP, 1, &regdata);
++		sd_trace(("reset reg read = 0x%x\n", regdata));
++		sd_trace(("dwordmode = %d, wordlen = %d, resp_delay_all = %d\n", sd->dwordmode,
++		       sd->wordlen, sd->resp_delay_all));
++		/* Restore default state after softreset */
++		sd->wordlen = 2;
++		sd->dwordmode = FALSE;
++	}
++
++	if (sd->wordlen == 4) {
++		if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, &regdata)) !=
++		     SUCCESS)
++				return FALSE;
++		if (regdata == TEST_RO_DATA_32BIT_LE) {
++			sd_trace(("Spid is already in 32bit LE mode. Value read = 0x%x\n",
++			          regdata));
++			sd_trace(("Spid power was left on.\n"));
++		} else {
++			sd_err(("Spid power was left on but signature read failed."
++			        " Value read = 0x%x\n", regdata));
++			return FALSE;
++		}
++	} else {
++		sd->wordlen = 2;
++
++#define CTRL_REG_DEFAULT	0x00010430 /* according to the host m/c */
++
++		wrregdata = (CTRL_REG_DEFAULT);
++
++		if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, &regdata)) != SUCCESS)
++			return FALSE;
++		sd_trace(("(we are still in 16bit mode) 32bit READ LE regdata = 0x%x\n", regdata));
++
++#ifndef HSMODE
++		wrregdata |= (CLOCK_PHASE | CLOCK_POLARITY);
++		wrregdata &= ~HIGH_SPEED_MODE;
++		bcmspi_card_regwrite(sd, 0, SPID_CONFIG, 4, wrregdata);
++#endif /* HSMODE */
++
++		for (i = 0; i < INIT_ADAPT_LOOP; i++) {
++			if ((regdata == 0xfdda7d5b) || (regdata == 0xfdda7d5a)) {
++				sd_trace(("0xfeedbead was leftshifted by 1-bit.\n"));
++				if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4,
++				     &regdata)) != SUCCESS)
++					return FALSE;
++			}
++			OSL_DELAY(1000);
++		}
++
++		/* Change to host controller intr-polarity of active-low */
++		wrregdata &= ~INTR_POLARITY;
++		sd_trace(("(we are still in 16bit mode) 32bit Write LE reg-ctrl-data = 0x%x\n",
++		        wrregdata));
++		/* Change to 32bit mode */
++		wrregdata |= WORD_LENGTH_32;
++		bcmspi_card_regwrite(sd, 0, SPID_CONFIG, 4, wrregdata);
++
++		/* Change command/data packaging in 32bit LE mode */
++		sd->wordlen = 4;
++
++		if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, &regdata)) != SUCCESS)
++			return FALSE;
++
++		if (regdata == TEST_RO_DATA_32BIT_LE) {
++			sd_trace(("Read spid passed. Value read = 0x%x\n", regdata));
++			sd_trace(("Spid had power-on cycle OR spi was soft-resetted \n"));
++		} else {
++			sd_err(("Stale spid reg values read as it was kept powered. Value read ="
++			  "0x%x\n", regdata));
++			return FALSE;
++		}
++	}
++
++
++	return TRUE;
++}
++
++static bool
++bcmspi_test_card(sdioh_info_t *sd)
++{
++	uint32 regdata;
++	int status;
++
++	if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, &regdata)) != SUCCESS)
++		return FALSE;
++
++	if (regdata == (TEST_RO_DATA_32BIT_LE))
++		sd_trace(("32bit LE regdata = 0x%x\n", regdata));
++	else {
++		sd_trace(("Incorrect 32bit LE regdata = 0x%x\n", regdata));
++		return FALSE;
++	}
++
++
++#define RW_PATTERN1	0xA0A1A2A3
++#define RW_PATTERN2	0x4B5B6B7B
++
++	regdata = RW_PATTERN1;
++	if ((status = bcmspi_card_regwrite(sd, 0, SPID_TEST_RW, 4, regdata)) != SUCCESS)
++		return FALSE;
++	regdata = 0;
++	if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_RW, 4, &regdata)) != SUCCESS)
++		return FALSE;
++	if (regdata != RW_PATTERN1) {
++		sd_err(("Write-Read spid failed. Value wrote = 0x%x, Value read = 0x%x\n",
++			RW_PATTERN1, regdata));
++		return FALSE;
++	} else
++		sd_trace(("R/W spid passed. Value read = 0x%x\n", regdata));
++
++	regdata = RW_PATTERN2;
++	if ((status = bcmspi_card_regwrite(sd, 0, SPID_TEST_RW, 4, regdata)) != SUCCESS)
++		return FALSE;
++	regdata = 0;
++	if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_RW, 4, &regdata)) != SUCCESS)
++		return FALSE;
++	if (regdata != RW_PATTERN2) {
++		sd_err(("Write-Read spid failed. Value wrote = 0x%x, Value read = 0x%x\n",
++			RW_PATTERN2, regdata));
++		return FALSE;
++	} else
++		sd_trace(("R/W spid passed. Value read = 0x%x\n", regdata));
++
++	return TRUE;
++}
++
++static int
++bcmspi_driver_init(sdioh_info_t *sd)
++{
++	sd_trace(("%s\n", __FUNCTION__));
++	if ((bcmspi_host_init(sd)) != SUCCESS) {
++		return ERROR;
++	}
++
++	if (bcmspi_client_init(sd) != SUCCESS) {
++		return ERROR;
++	}
++
++	return SUCCESS;
++}
++
++/* Read device reg */
++static int
++bcmspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data)
++{
++	int status;
++	uint32 cmd_arg, dstatus;
++
++	ASSERT(regsize);
++
++	if (func == 2)
++		sd_trace(("Reg access on F2 will generate error indication in dstatus bits.\n"));
++
++	cmd_arg = 0;
++	cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 0);
++	cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1);	/* Incremental access */
++	cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
++	cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
++	cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize == BLOCK_SIZE_F2 ? 0 : regsize);
++
++	sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d\n",
++	          __FUNCTION__, cmd_arg, func, regaddr, regsize));
++
++	if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, regsize)) != SUCCESS)
++		return status;
++
++	bcmspi_cmd_getdstatus(sd, &dstatus);
++	if (dstatus)
++		sd_trace(("dstatus =0x%x\n", dstatus));
++
++	return SUCCESS;
++}
++
++static int
++bcmspi_card_regread_fixedaddr(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data)
++{
++
++	int status;
++	uint32 cmd_arg;
++	uint32 dstatus;
++
++	ASSERT(regsize);
++
++	if (func == 2)
++		sd_trace(("Reg access on F2 will generate error indication in dstatus bits.\n"));
++
++	cmd_arg = 0;
++	cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 0);
++	cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 0);	/* Fixed access */
++	cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
++	cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
++	cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize);
++
++	sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d\n",
++	          __FUNCTION__, cmd_arg, func, regaddr, regsize));
++
++	if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, regsize)) != SUCCESS)
++		return status;
++
++	sd_trace(("%s: RD result=0x%x\n", __FUNCTION__, *data));
++
++	bcmspi_cmd_getdstatus(sd, &dstatus);
++	sd_trace(("dstatus =0x%x\n", dstatus));
++	return SUCCESS;
++}
++
++/* write a device register */
++static int
++bcmspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 data)
++{
++	int status;
++	uint32 cmd_arg, dstatus;
++
++	ASSERT(regsize);
++
++	cmd_arg = 0;
++
++	cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
++	cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1);	/* Incremental access */
++	cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
++	cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
++	cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize == BLOCK_SIZE_F2 ? 0 : regsize);
++
++	sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d data=0x%x\n",
++	          __FUNCTION__, cmd_arg, func, regaddr, regsize, data));
++
++	if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, regsize)) != SUCCESS)
++		return status;
++
++	bcmspi_cmd_getdstatus(sd, &dstatus);
++	if (dstatus)
++		sd_trace(("dstatus=0x%x\n", dstatus));
++
++	return SUCCESS;
++}
++
++/* write a device register - 1 byte */
++static int
++bcmspi_card_bytewrite(sdioh_info_t *sd, int func, uint32 regaddr, uint8 *byte)
++{
++	int status;
++	uint32 cmd_arg;
++	uint32 dstatus;
++	uint32 data = (uint32)(*byte);
++
++	cmd_arg = 0;
++	cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
++	cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1);	/* Incremental access */
++	cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
++	cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
++	cmd_arg = SFIELD(cmd_arg, SPI_LEN, 1);
++
++	sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x data=0x%x\n",
++	          __FUNCTION__, cmd_arg, func, regaddr, data));
++
++	if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, 1)) != SUCCESS)
++		return status;
++
++	bcmspi_cmd_getdstatus(sd, &dstatus);
++	if (dstatus)
++		sd_trace(("dstatus =0x%x\n", dstatus));
++
++	return SUCCESS;
++}
++
++void
++bcmspi_cmd_getdstatus(sdioh_info_t *sd, uint32 *dstatus_buffer)
++{
++	*dstatus_buffer = sd->card_dstatus;
++}
++
++/* 'data' is of type uint32 whereas other buffers are of type uint8 */
++static int
++bcmspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd_arg,
++                uint32 *data, uint32 datalen)
++{
++	uint32	i, j;
++	uint8	resp_delay = 0;
++	int	err = SUCCESS;
++	uint32	hostlen;
++	uint32 spilen = 0;
++	uint32 dstatus_idx = 0;
++	uint16 templen, buslen, len, *ptr = NULL;
++
++	sd_trace(("spi cmd = 0x%x\n", cmd_arg));
++
++	if (DWORDMODE_ON) {
++		spilen = GFIELD(cmd_arg, SPI_LEN);
++		if ((GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_0) ||
++		    (GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_1))
++			dstatus_idx = spilen * 3;
++
++		if ((GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_2) &&
++		    (GFIELD(cmd_arg, SPI_RW_FLAG) == 1)) {
++			spilen = spilen << 2;
++			dstatus_idx = (spilen % 16) ? (16 - (spilen % 16)) : 0;
++			/* convert len to mod16 size */
++			spilen = ROUNDUP(spilen, 16);
++			cmd_arg = SFIELD(cmd_arg, SPI_LEN, (spilen >> 2));
++		}
++	}
++
++	/* Set up and issue the SPI command.  MSByte goes out on bus first.  Increase datalen
++	 * according to the wordlen mode(16/32bit) the device is in.
++	 */
++	if (sd->wordlen == 4) { /* 32bit spid */
++		*(uint32 *)spi_outbuf = SPISWAP_WD4(cmd_arg);
++		if (datalen & 0x3)
++			datalen += (4 - (datalen & 0x3));
++	} else if (sd->wordlen == 2) { /* 16bit spid */
++		*(uint32 *)spi_outbuf = SPISWAP_WD2(cmd_arg);
++		if (datalen & 0x1)
++			datalen++;
++		if (datalen < 4)
++			datalen = ROUNDUP(datalen, 4);
++	} else {
++		sd_err(("Host is %d bit spid, could not create SPI command.\n",
++			8 * sd->wordlen));
++		return ERROR;
++	}
++
++	/* for Write, put the data into the output buffer */
++	if (GFIELD(cmd_arg, SPI_RW_FLAG) == 1) {
++		/* We send len field of hw-header always a mod16 size, both from host and dongle */
++		if (DWORDMODE_ON) {
++			if (GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_2) {
++				ptr = (uint16 *)&data[0];
++				templen = *ptr;
++				/* ASSERT(*ptr == ~*(ptr + 1)); */
++				templen = ROUNDUP(templen, 16);
++				*ptr = templen;
++				sd_trace(("actual tx len = %d\n", (uint16)(~*(ptr+1))));
++			}
++		}
++
++		if (datalen != 0) {
++			for (i = 0; i < datalen/4; i++) {
++				if (sd->wordlen == 4) { /* 32bit spid */
++					*(uint32 *)&spi_outbuf[i * 4 + CMDLEN] =
++						SPISWAP_WD4(data[i]);
++				} else if (sd->wordlen == 2) { /* 16bit spid */
++					*(uint32 *)&spi_outbuf[i * 4 + CMDLEN] =
++						SPISWAP_WD2(data[i]);
++				}
++			}
++		}
++	}
++
++	/* Append resp-delay number of bytes and clock them out for F0/1/2 reads. */
++	if ((GFIELD(cmd_arg, SPI_RW_FLAG) == 0)) {
++		int func = GFIELD(cmd_arg, SPI_FUNCTION);
++		switch (func) {
++			case 0:
++				if (sd->resp_delay_new)
++					resp_delay = GSPI_F0_RESP_DELAY;
++				else
++					resp_delay = sd->resp_delay_all ? F0_RESPONSE_DELAY : 0;
++				break;
++			case 1:
++				if (sd->resp_delay_new)
++					resp_delay = GSPI_F1_RESP_DELAY;
++				else
++					resp_delay = F1_RESPONSE_DELAY;
++				break;
++			case 2:
++				if (sd->resp_delay_new)
++					resp_delay = GSPI_F2_RESP_DELAY;
++				else
++					resp_delay = sd->resp_delay_all ? F2_RESPONSE_DELAY : 0;
++				break;
++			default:
++				ASSERT(0);
++				break;
++		}
++		/* Program response delay */
++		if (sd->resp_delay_new == FALSE)
++			bcmspi_prog_resp_delay(sd, func, resp_delay);
++	}
++
++	/* +4 for cmd and +4 for dstatus */
++	hostlen = datalen + 8 + resp_delay;
++	hostlen += dstatus_idx;
++	hostlen += (4 - (hostlen & 0x3));
++	spi_sendrecv(sd, spi_outbuf, spi_inbuf, hostlen);
++
++	/* for Read, get the data into the input buffer */
++	if (datalen != 0) {
++		if (GFIELD(cmd_arg, SPI_RW_FLAG) == 0) { /* if read cmd */
++			for (j = 0; j < datalen/4; j++) {
++				if (sd->wordlen == 4) { /* 32bit spid */
++					data[j] = SPISWAP_WD4(*(uint32 *)&spi_inbuf[j * 4 +
++					            CMDLEN + resp_delay]);
++				} else if (sd->wordlen == 2) { /* 16bit spid */
++					data[j] = SPISWAP_WD2(*(uint32 *)&spi_inbuf[j * 4 +
++					            CMDLEN + resp_delay]);
++				}
++			}
++
++			if ((DWORDMODE_ON) && (GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_2)) {
++				ptr = (uint16 *)&data[0];
++				templen = *ptr;
++				buslen = len = ~(*(ptr + 1));
++				buslen = ROUNDUP(buslen, 16);
++				/* populate actual len in hw-header */
++				if (templen == buslen)
++					*ptr = len;
++			}
++		}
++	}
++
++	/* Restore back the len field of the hw header */
++	if (DWORDMODE_ON) {
++		if ((GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_2) &&
++		    (GFIELD(cmd_arg, SPI_RW_FLAG) == 1)) {
++			ptr = (uint16 *)&data[0];
++			*ptr = (uint16)(~*(ptr+1));
++		}
++	}
++
++	dstatus_idx += (datalen + CMDLEN + resp_delay);
++	/* Last 4bytes are dstatus.  Device is configured to return status bits. */
++	if (sd->wordlen == 4) { /* 32bit spid */
++		sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf[dstatus_idx]);
++	} else if (sd->wordlen == 2) { /* 16bit spid */
++		sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf[dstatus_idx]);
++	} else {
++		sd_err(("Host is %d bit machine, could not read SPI dstatus.\n",
++			8 * sd->wordlen));
++		return ERROR;
++	}
++	if (sd->card_dstatus == 0xffffffff) {
++		sd_err(("looks like not a GSPI device or device is not powered.\n"));
++	}
++
++	err = bcmspi_update_stats(sd, cmd_arg);
++
++	return err;
++
++}
++
++static int
++bcmspi_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo,
++                uint32 addr, int nbytes, uint32 *data)
++{
++	int status;
++	uint32 cmd_arg;
++	bool write = rw == SDIOH_READ ? 0 : 1;
++	uint retries = 0;
++
++	bool enable;
++	uint32	spilen;
++
++	cmd_arg = 0;
++
++	ASSERT(nbytes);
++	ASSERT(nbytes <= sd->client_block_size[func]);
++
++	if (write) sd->t_cnt++; else sd->r_cnt++;
++
++	if (func == 2) {
++		/* Frame len check limited by gSPI. */
++		if ((nbytes > 2000) && write) {
++			sd_trace((">2KB write: F2 wr of %d bytes\n", nbytes));
++		}
++		/* ASSERT(nbytes <= 2048); Fix bigger len gspi issue and uncomment. */
++		/* If F2 fifo on device is not ready to receive data, don't do F2 transfer */
++		if (write) {
++			uint32 dstatus;
++			/* check F2 ready with cached one */
++			bcmspi_cmd_getdstatus(sd, &dstatus);
++			if ((dstatus & STATUS_F2_RX_READY) == 0) {
++				retries = WAIT_F2RXFIFORDY;
++				enable = 0;
++				while (retries-- && !enable) {
++					OSL_DELAY(WAIT_F2RXFIFORDY_DELAY * 1000);
++					bcmspi_card_regread(sd, SPI_FUNC_0, SPID_STATUS_REG, 4,
++					                   &dstatus);
++					if (dstatus & STATUS_F2_RX_READY)
++						enable = TRUE;
++				}
++				if (!enable) {
++					struct spierrstats_t *spierrstats = &sd->spierrstats;
++					spierrstats->f2rxnotready++;
++					sd_err(("F2 FIFO is not ready to receive data.\n"));
++					return ERROR;
++				}
++				sd_trace(("No of retries on F2 ready %d\n",
++					(WAIT_F2RXFIFORDY - retries)));
++			}
++		}
++	}
++
++	/* F2 transfers happen on 0 addr */
++	addr = (func == 2) ? 0 : addr;
++
++	/* In pio mode buffer is read using fixed address fifo in func 1 */
++	if ((func == 1) && (fifo))
++		cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 0);
++	else
++		cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1);
++
++	cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
++	cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, addr);
++	cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, write);
++	spilen = sd->data_xfer_count = MIN(sd->client_block_size[func], nbytes);
++	if ((sd->dwordmode == TRUE) && (GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_2)) {
++		/* convert len to mod4 size */
++		spilen = spilen + ((spilen & 0x3) ? (4 - (spilen & 0x3)): 0);
++		cmd_arg = SFIELD(cmd_arg, SPI_LEN, (spilen >> 2));
++	} else
++		cmd_arg = SFIELD(cmd_arg, SPI_LEN, spilen);
++
++	if ((func == 2) && (fifo == 1)) {
++		sd_data(("%s: %s func %d, %s, addr 0x%x, len %d bytes, r_cnt %d t_cnt %d\n",
++		          __FUNCTION__, write ? "Wr" : "Rd", func, "INCR",
++		          addr, nbytes, sd->r_cnt, sd->t_cnt));
++	}
++
++	sd_trace(("%s cmd_arg = 0x%x\n", __FUNCTION__, cmd_arg));
++	sd_data(("%s: %s func %d, %s, addr 0x%x, len %d bytes, r_cnt %d t_cnt %d\n",
++	         __FUNCTION__, write ? "Wd" : "Rd", func, "INCR",
++	         addr, nbytes, sd->r_cnt, sd->t_cnt));
++
++
++	if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, nbytes)) != SUCCESS) {
++		sd_err(("%s: cmd_issue failed for %s\n", __FUNCTION__,
++			(write ? "write" : "read")));
++		return status;
++	}
++
++	/* gSPI expects that hw-header-len is equal to spi-command-len */
++	if ((func == 2) && (rw == SDIOH_WRITE) && (sd->dwordmode == FALSE)) {
++		ASSERT((uint16)sd->data_xfer_count == (uint16)(*data & 0xffff));
++		ASSERT((uint16)sd->data_xfer_count == (uint16)(~((*data & 0xffff0000) >> 16)));
++	}
++
++	if ((nbytes > 2000) && !write) {
++		sd_trace((">2KB read: F2 rd of %d bytes\n", nbytes));
++	}
++
++	return SUCCESS;
++}
++
++/* Reset and re-initialize the device */
++int
++sdioh_sdio_reset(sdioh_info_t *si)
++{
++	si->card_init_done = FALSE;
++	return bcmspi_client_init(si);
++}
++
++SDIOH_API_RC
++sdioh_gpioouten(sdioh_info_t *sd, uint32 gpio)
++{
++	return SDIOH_API_RC_FAIL;
++}
++
++SDIOH_API_RC
++sdioh_gpioout(sdioh_info_t *sd, uint32 gpio, bool enab)
++{
++	return SDIOH_API_RC_FAIL;
++}
++
++bool
++sdioh_gpioin(sdioh_info_t *sd, uint32 gpio)
++{
++	return FALSE;
++}
++
++SDIOH_API_RC
++sdioh_gpio_init(sdioh_info_t *sd)
++{
++	return SDIOH_API_RC_FAIL;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmutils.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmutils.c
+new file mode 100644
+index 000000000..24e633c89
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmutils.c
+@@ -0,0 +1,3677 @@
++/*
++ * Driver O/S-independent utility routines
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmutils.c 692666 2018-07-30 08:58:07Z $
++ */
++
++#include <bcm_cfg.h>
++#include <typedefs.h>
++#include <bcmdefs.h>
++#include <stdarg.h>
++#ifdef BCMDRIVER
++
++#include <osl.h>
++#include <bcmutils.h>
++
++#else /* !BCMDRIVER */
++
++#include <stdio.h>
++#include <string.h>
++#include <bcmutils.h>
++
++#if defined(BCMEXTSUP)
++#include <bcm_osl.h>
++#endif
++
++#ifndef ASSERT
++#define ASSERT(exp)
++#endif
++
++#endif /* !BCMDRIVER */
++
++#include <bcmendian.h>
++#include <bcmdevs.h>
++#include <proto/ethernet.h>
++#include <proto/vlan.h>
++#include <proto/bcmip.h>
++#include <proto/802.1d.h>
++#include <proto/802.11.h>
++
++
++void *_bcmutils_dummy_fn = NULL;
++
++
++
++
++#ifdef BCMDRIVER
++
++
++
++/* copy a pkt buffer chain into a buffer */
++uint
++pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf)
++{
++	uint n, ret = 0;
++
++	if (len < 0)
++		len = 4096;	/* "infinite" */
++
++	/* skip 'offset' bytes */
++	for (; p && offset; p = PKTNEXT(osh, p)) {
++		if (offset < (uint)PKTLEN(osh, p))
++			break;
++		offset -= PKTLEN(osh, p);
++	}
++
++	if (!p)
++		return 0;
++
++	/* copy the data */
++	for (; p && len; p = PKTNEXT(osh, p)) {
++		n = MIN((uint)PKTLEN(osh, p) - offset, (uint)len);
++		bcopy(PKTDATA(osh, p) + offset, buf, n);
++		buf += n;
++		len -= n;
++		ret += n;
++		offset = 0;
++	}
++
++	return ret;
++}
++
++/* copy a buffer into a pkt buffer chain */
++uint
++pktfrombuf(osl_t *osh, void *p, uint offset, int len, uchar *buf)
++{
++	uint n, ret = 0;
++
++
++	/* skip 'offset' bytes */
++	for (; p && offset; p = PKTNEXT(osh, p)) {
++		if (offset < (uint)PKTLEN(osh, p))
++			break;
++		offset -= PKTLEN(osh, p);
++	}
++
++	if (!p)
++		return 0;
++
++	/* copy the data */
++	for (; p && len; p = PKTNEXT(osh, p)) {
++		n = MIN((uint)PKTLEN(osh, p) - offset, (uint)len);
++		bcopy(buf, PKTDATA(osh, p) + offset, n);
++		buf += n;
++		len -= n;
++		ret += n;
++		offset = 0;
++	}
++
++	return ret;
++}
++
++
++
++/* return total length of buffer chain */
++uint BCMFASTPATH
++pkttotlen(osl_t *osh, void *p)
++{
++	uint total;
++	int len;
++
++	total = 0;
++	for (; p; p = PKTNEXT(osh, p)) {
++		len = PKTLEN(osh, p);
++		total += len;
++#ifdef BCMLFRAG
++		if (BCMLFRAG_ENAB()) {
++			if (PKTISFRAG(osh, p)) {
++				total += PKTFRAGTOTLEN(osh, p);
++			}
++		}
++#endif
++	}
++
++	return (total);
++}
++
++/* return the last buffer of chained pkt */
++void *
++pktlast(osl_t *osh, void *p)
++{
++	for (; PKTNEXT(osh, p); p = PKTNEXT(osh, p))
++		;
++
++	return (p);
++}
++
++/* count segments of a chained packet */
++uint BCMFASTPATH
++pktsegcnt(osl_t *osh, void *p)
++{
++	uint cnt;
++
++	for (cnt = 0; p; p = PKTNEXT(osh, p)) {
++		cnt++;
++#ifdef BCMLFRAG
++		if (BCMLFRAG_ENAB()) {
++			if (PKTISFRAG(osh, p)) {
++				cnt += PKTFRAGTOTNUM(osh, p);
++			}
++		}
++#endif
++	}
++
++	return cnt;
++}
++
++
++/* count segments of a chained packet */
++uint BCMFASTPATH
++pktsegcnt_war(osl_t *osh, void *p)
++{
++	uint cnt;
++	uint8 *pktdata;
++	uint len, remain, align64;
++
++	for (cnt = 0; p; p = PKTNEXT(osh, p)) {
++		cnt++;
++		len = PKTLEN(osh, p);
++		if (len > 128) {
++			pktdata = (uint8 *)PKTDATA(osh, p);	/* starting address of data */
++			/* Check for page boundary straddle (2048B) */
++			if (((uintptr)pktdata & ~0x7ff) != ((uintptr)(pktdata+len) & ~0x7ff))
++				cnt++;
++
++			align64 = (uint)((uintptr)pktdata & 0x3f);	/* aligned to 64B */
++			align64 = (64 - align64) & 0x3f;
++			len -= align64;		/* bytes from aligned 64B to end */
++			/* if aligned to 128B, check for MOD 128 between 1 to 4B */
++			remain = len % 128;
++			if (remain > 0 && remain <= 4)
++				cnt++;		/* add extra seg */
++		}
++	}
++
++	return cnt;
++}
++
++uint8 * BCMFASTPATH
++pktdataoffset(osl_t *osh, void *p,  uint offset)
++{
++	uint total = pkttotlen(osh, p);
++	uint pkt_off = 0, len = 0;
++	uint8 *pdata = (uint8 *) PKTDATA(osh, p);
++
++	if (offset > total)
++		return NULL;
++
++	for (; p; p = PKTNEXT(osh, p)) {
++		pdata = (uint8 *) PKTDATA(osh, p);
++		pkt_off = offset - len;
++		len += PKTLEN(osh, p);
++		if (len > offset)
++			break;
++	}
++	return (uint8*) (pdata+pkt_off);
++}
++
++
++/* given a offset in pdata, find the pkt seg hdr */
++void *
++pktoffset(osl_t *osh, void *p,  uint offset)
++{
++	uint total = pkttotlen(osh, p);
++	uint len = 0;
++
++	if (offset > total)
++		return NULL;
++
++	for (; p; p = PKTNEXT(osh, p)) {
++		len += PKTLEN(osh, p);
++		if (len > offset)
++			break;
++	}
++	return p;
++}
++
++#endif /* BCMDRIVER */
++
++#if !defined(BCMROMOFFLOAD_EXCLUDE_BCMUTILS_FUNCS)
++const unsigned char bcm_ctype[] = {
++
++	_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,			/* 0-7 */
++	_BCM_C, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C,
++	_BCM_C,	/* 8-15 */
++	_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,			/* 16-23 */
++	_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,			/* 24-31 */
++	_BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,		/* 32-39 */
++	_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,			/* 40-47 */
++	_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,			/* 48-55 */
++	_BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,			/* 56-63 */
++	_BCM_P, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X,
++	_BCM_U|_BCM_X, _BCM_U, /* 64-71 */
++	_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,			/* 72-79 */
++	_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,			/* 80-87 */
++	_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,			/* 88-95 */
++	_BCM_P, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X,
++	_BCM_L|_BCM_X, _BCM_L, /* 96-103 */
++	_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
++	_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
++	_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
++	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,		/* 128-143 */
++	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,		/* 144-159 */
++	_BCM_S|_BCM_SP, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
++	_BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,	/* 160-175 */
++	_BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
++	_BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,	/* 176-191 */
++	_BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U,
++	_BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U,	/* 192-207 */
++	_BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_P, _BCM_U, _BCM_U, _BCM_U,
++	_BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_L,	/* 208-223 */
++	_BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L,
++	_BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L,	/* 224-239 */
++	_BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_P, _BCM_L, _BCM_L, _BCM_L,
++	_BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L /* 240-255 */
++};
++
++ulong
++bcm_strtoul(const char *cp, char **endp, uint base)
++{
++	ulong result, last_result = 0, value;
++	bool minus;
++
++	minus = FALSE;
++
++	while (bcm_isspace(*cp))
++		cp++;
++
++	if (cp[0] == '+')
++		cp++;
++	else if (cp[0] == '-') {
++		minus = TRUE;
++		cp++;
++	}
++
++	if (base == 0) {
++		if (cp[0] == '0') {
++			if ((cp[1] == 'x') || (cp[1] == 'X')) {
++				base = 16;
++				cp = &cp[2];
++			} else {
++				base = 8;
++				cp = &cp[1];
++			}
++		} else
++			base = 10;
++	} else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
++		cp = &cp[2];
++	}
++
++	result = 0;
++
++	while (bcm_isxdigit(*cp) &&
++	       (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
++		result = result*base + value;
++		/* Detected overflow */
++		if (result < last_result && !minus)
++			return (ulong)-1;
++		last_result = result;
++		cp++;
++	}
++
++	if (minus)
++		result = (ulong)(-(long)result);
++
++	if (endp)
++		*endp = DISCARD_QUAL(cp, char);
++
++	return (result);
++}
++
++int
++bcm_atoi(const char *s)
++{
++	return (int)bcm_strtoul(s, NULL, 10);
++}
++
++/* return pointer to location of substring 'needle' in 'haystack' */
++char *
++bcmstrstr(const char *haystack, const char *needle)
++{
++	int len, nlen;
++	int i;
++
++	if ((haystack == NULL) || (needle == NULL))
++		return DISCARD_QUAL(haystack, char);
++
++	nlen = (int)strlen(needle);
++	len = (int)strlen(haystack) - nlen + 1;
++
++	for (i = 0; i < len; i++)
++		if (memcmp(needle, &haystack[i], nlen) == 0)
++			return DISCARD_QUAL(&haystack[i], char);
++	return (NULL);
++}
++
++char *
++bcmstrnstr(const char *s, uint s_len, const char *substr, uint substr_len)
++{
++	for (; s_len >= substr_len; s++, s_len--)
++		if (strncmp(s, substr, substr_len) == 0)
++			return DISCARD_QUAL(s, char);
++
++	return NULL;
++}
++
++char *
++bcmstrcat(char *dest, const char *src)
++{
++	char *p;
++
++	p = dest + strlen(dest);
++
++	while ((*p++ = *src++) != '\0')
++		;
++
++	return (dest);
++}
++
++char *
++bcmstrncat(char *dest, const char *src, uint size)
++{
++	char *endp;
++	char *p;
++
++	p = dest + strlen(dest);
++	endp = p + size;
++
++	while (p != endp && (*p++ = *src++) != '\0')
++		;
++
++	return (dest);
++}
++
++
++/****************************************************************************
++* Function:   bcmstrtok
++*
++* Purpose:
++*  Tokenizes a string. This function is conceptually similiar to ANSI C strtok(),
++*  but allows strToken() to be used by different strings or callers at the same
++*  time. Each call modifies '*string' by substituting a NULL character for the
++*  first delimiter that is encountered, and updates 'string' to point to the char
++*  after the delimiter. Leading delimiters are skipped.
++*
++* Parameters:
++*  string      (mod) Ptr to string ptr, updated by token.
++*  delimiters  (in)  Set of delimiter characters.
++*  tokdelim    (out) Character that delimits the returned token. (May
++*                    be set to NULL if token delimiter is not required).
++*
++* Returns:  Pointer to the next token found. NULL when no more tokens are found.
++*****************************************************************************
++*/
++char *
++bcmstrtok(char **string, const char *delimiters, char *tokdelim)
++{
++	unsigned char *str;
++	unsigned long map[8];
++	int count;
++	char *nextoken;
++
++	if (tokdelim != NULL) {
++		/* Prime the token delimiter */
++		*tokdelim = '\0';
++	}
++
++	/* Clear control map */
++	for (count = 0; count < 8; count++) {
++		map[count] = 0;
++	}
++
++	/* Set bits in delimiter table */
++	do {
++		map[*delimiters >> 5] |= (1 << (*delimiters & 31));
++	}
++	while (*delimiters++);
++
++	str = (unsigned char*)*string;
++
++	/* Find beginning of token (skip over leading delimiters). Note that
++	 * there is no token iff this loop sets str to point to the terminal
++	 * null (*str == '\0')
++	 */
++	while (((map[*str >> 5] & (1 << (*str & 31))) && *str) || (*str == ' ')) {
++		str++;
++	}
++
++	nextoken = (char*)str;
++
++	/* Find the end of the token. If it is not the end of the string,
++	 * put a null there.
++	 */
++	for (; *str; str++) {
++		if (map[*str >> 5] & (1 << (*str & 31))) {
++			if (tokdelim != NULL) {
++				*tokdelim = *str;
++			}
++
++			*str++ = '\0';
++			break;
++		}
++	}
++
++	*string = (char*)str;
++
++	/* Determine if a token has been found. */
++	if (nextoken == (char *) str) {
++		return NULL;
++	}
++	else {
++		return nextoken;
++	}
++}
++
++
++#define xToLower(C) \
++	((C >= 'A' && C <= 'Z') ? (char)((int)C - (int)'A' + (int)'a') : C)
++
++
++/****************************************************************************
++* Function:   bcmstricmp
++*
++* Purpose:    Compare to strings case insensitively.
++*
++* Parameters: s1 (in) First string to compare.
++*             s2 (in) Second string to compare.
++*
++* Returns:    Return 0 if the two strings are equal, -1 if t1 < t2 and 1 if
++*             t1 > t2, when ignoring case sensitivity.
++*****************************************************************************
++*/
++int
++bcmstricmp(const char *s1, const char *s2)
++{
++	char dc, sc;
++
++	while (*s2 && *s1) {
++		dc = xToLower(*s1);
++		sc = xToLower(*s2);
++		if (dc < sc) return -1;
++		if (dc > sc) return 1;
++		s1++;
++		s2++;
++	}
++
++	if (*s1 && !*s2) return 1;
++	if (!*s1 && *s2) return -1;
++	return 0;
++}
++
++
++/****************************************************************************
++* Function:   bcmstrnicmp
++*
++* Purpose:    Compare to strings case insensitively, upto a max of 'cnt'
++*             characters.
++*
++* Parameters: s1  (in) First string to compare.
++*             s2  (in) Second string to compare.
++*             cnt (in) Max characters to compare.
++*
++* Returns:    Return 0 if the two strings are equal, -1 if t1 < t2 and 1 if
++*             t1 > t2, when ignoring case sensitivity.
++*****************************************************************************
++*/
++int
++bcmstrnicmp(const char* s1, const char* s2, int cnt)
++{
++	char dc, sc;
++
++	while (*s2 && *s1 && cnt) {
++		dc = xToLower(*s1);
++		sc = xToLower(*s2);
++		if (dc < sc) return -1;
++		if (dc > sc) return 1;
++		s1++;
++		s2++;
++		cnt--;
++	}
++
++	if (!cnt) return 0;
++	if (*s1 && !*s2) return 1;
++	if (!*s1 && *s2) return -1;
++	return 0;
++}
++
++/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
++int
++bcm_ether_atoe(const char *p, struct ether_addr *ea)
++{
++	int i = 0;
++	char *ep;
++
++	for (;;) {
++		ea->octet[i++] = (char) bcm_strtoul(p, &ep, 16);
++		p = ep;
++		if (!*p++ || i == 6)
++			break;
++	}
++
++	return (i == 6);
++}
++
++int
++bcm_atoipv4(const char *p, struct ipv4_addr *ip)
++{
++
++	int i = 0;
++	char *c;
++	for (;;) {
++		ip->addr[i++] = (uint8)bcm_strtoul(p, &c, 0);
++		if (*c++ != '.' || i == IPV4_ADDR_LEN)
++			break;
++		p = c;
++	}
++	return (i == IPV4_ADDR_LEN);
++}
++#endif	/* !BCMROMOFFLOAD_EXCLUDE_BCMUTILS_FUNCS */
++
++
++#if defined(CONFIG_USBRNDIS_RETAIL) || defined(NDIS_MINIPORT_DRIVER)
++/* registry routine buffer preparation utility functions:
++ * parameter order is like strncpy, but returns count
++ * of bytes copied. Minimum bytes copied is null char(1)/wchar(2)
++ */
++ulong
++wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen)
++{
++	ulong copyct = 1;
++	ushort i;
++
++	if (abuflen == 0)
++		return 0;
++
++	/* wbuflen is in bytes */
++	wbuflen /= sizeof(ushort);
++
++	for (i = 0; i < wbuflen; ++i) {
++		if (--abuflen == 0)
++			break;
++		*abuf++ = (char) *wbuf++;
++		++copyct;
++	}
++	*abuf = '\0';
++
++	return copyct;
++}
++#endif /* CONFIG_USBRNDIS_RETAIL || NDIS_MINIPORT_DRIVER */
++
++char *
++bcm_ether_ntoa(const struct ether_addr *ea, char *buf)
++{
++	static const char hex[] =
++	  {
++		  '0', '1', '2', '3', '4', '5', '6', '7',
++		  '8', '9', 'a', 'b', 'c', 'd', 'e', 'f'
++	  };
++	const uint8 *octet = ea->octet;
++	char *p = buf;
++	int i;
++
++	for (i = 0; i < 6; i++, octet++) {
++		*p++ = hex[(*octet >> 4) & 0xf];
++		*p++ = hex[*octet & 0xf];
++		*p++ = ':';
++	}
++
++	*(p-1) = '\0';
++
++	return (buf);
++}
++
++char *
++bcm_ip_ntoa(struct ipv4_addr *ia, char *buf)
++{
++	snprintf(buf, 16, "%d.%d.%d.%d",
++	         ia->addr[0], ia->addr[1], ia->addr[2], ia->addr[3]);
++	return (buf);
++}
++
++char *
++bcm_ipv6_ntoa(void *ipv6, char *buf)
++{
++	/* Implementing RFC 5952 Sections 4 + 5 */
++	/* Not thoroughly tested */
++	uint16 tmp[8];
++	uint16 *a = &tmp[0];
++	char *p = buf;
++	int i, i_max = -1, cnt = 0, cnt_max = 1;
++	uint8 *a4 = NULL;
++	memcpy((uint8 *)&tmp[0], (uint8 *)ipv6, IPV6_ADDR_LEN);
++
++	for (i = 0; i < IPV6_ADDR_LEN/2; i++) {
++		if (a[i]) {
++			if (cnt > cnt_max) {
++				cnt_max = cnt;
++				i_max = i - cnt;
++			}
++			cnt = 0;
++		} else
++			cnt++;
++	}
++	if (cnt > cnt_max) {
++		cnt_max = cnt;
++		i_max = i - cnt;
++	}
++	if (i_max == 0 &&
++		/* IPv4-translated: ::ffff:0:a.b.c.d */
++		((cnt_max == 4 && a[4] == 0xffff && a[5] == 0) ||
++		/* IPv4-mapped: ::ffff:a.b.c.d */
++		(cnt_max == 5 && a[5] == 0xffff)))
++		a4 = (uint8*) (a + 6);
++
++	for (i = 0; i < IPV6_ADDR_LEN/2; i++) {
++		if ((uint8*) (a + i) == a4) {
++			snprintf(p, 16, ":%u.%u.%u.%u", a4[0], a4[1], a4[2], a4[3]);
++			break;
++		} else if (i == i_max) {
++			*p++ = ':';
++			i += cnt_max - 1;
++			p[0] = ':';
++			p[1] = '\0';
++		} else {
++			if (i)
++				*p++ = ':';
++			p += snprintf(p, 8, "%x", ntoh16(a[i]));
++		}
++	}
++
++	return buf;
++}
++#ifdef BCMDRIVER
++
++void
++bcm_mdelay(uint ms)
++{
++	uint i;
++
++	for (i = 0; i < ms; i++) {
++		OSL_DELAY(1000);
++	}
++}
++
++
++
++
++
++#if defined(DHD_DEBUG)
++/* pretty hex print a pkt buffer chain */
++void
++prpkt(const char *msg, osl_t *osh, void *p0)
++{
++	void *p;
++
++	if (msg && (msg[0] != '\0'))
++		printf("%s:\n", msg);
++
++	for (p = p0; p; p = PKTNEXT(osh, p))
++		prhex(NULL, PKTDATA(osh, p), PKTLEN(osh, p));
++}
++#endif	
++
++/* Takes an Ethernet frame and sets out-of-bound PKTPRIO.
++ * Also updates the inplace vlan tag if requested.
++ * For debugging, it returns an indication of what it did.
++ */
++uint BCMFASTPATH
++pktsetprio(void *pkt, bool update_vtag)
++{
++	struct ether_header *eh;
++	struct ethervlan_header *evh;
++	uint8 *pktdata;
++	int priority = 0;
++	int rc = 0;
++
++	pktdata = (uint8 *)PKTDATA(OSH_NULL, pkt);
++	ASSERT(ISALIGNED((uintptr)pktdata, sizeof(uint16)));
++
++	eh = (struct ether_header *) pktdata;
++
++	if (eh->ether_type == hton16(ETHER_TYPE_8021Q)) {
++		uint16 vlan_tag;
++		int vlan_prio, dscp_prio = 0;
++
++		evh = (struct ethervlan_header *)eh;
++
++		vlan_tag = ntoh16(evh->vlan_tag);
++		vlan_prio = (int) (vlan_tag >> VLAN_PRI_SHIFT) & VLAN_PRI_MASK;
++
++		if ((evh->ether_type == hton16(ETHER_TYPE_IP)) ||
++			(evh->ether_type == hton16(ETHER_TYPE_IPV6))) {
++			uint8 *ip_body = pktdata + sizeof(struct ethervlan_header);
++			uint8 tos_tc = IP_TOS46(ip_body);
++			dscp_prio = (int)(tos_tc >> IPV4_TOS_PREC_SHIFT);
++		}
++
++		/* DSCP priority gets precedence over 802.1P (vlan tag) */
++		if (dscp_prio != 0) {
++			priority = dscp_prio;
++			rc |= PKTPRIO_VDSCP;
++		} else {
++			priority = vlan_prio;
++			rc |= PKTPRIO_VLAN;
++		}
++		/*
++		 * If the DSCP priority is not the same as the VLAN priority,
++		 * then overwrite the priority field in the vlan tag, with the
++		 * DSCP priority value. This is required for Linux APs because
++		 * the VLAN driver on Linux, overwrites the skb->priority field
++		 * with the priority value in the vlan tag
++		 */
++		if (update_vtag && (priority != vlan_prio)) {
++			vlan_tag &= ~(VLAN_PRI_MASK << VLAN_PRI_SHIFT);
++			vlan_tag |= (uint16)priority << VLAN_PRI_SHIFT;
++			evh->vlan_tag = hton16(vlan_tag);
++			rc |= PKTPRIO_UPD;
++		}
++#ifdef DHD_LOSSLESS_ROAMING
++	} else if (eh->ether_type == hton16(ETHER_TYPE_802_1X)) {
++		priority = PRIO_8021D_NC;
++		rc = PKTPRIO_DSCP;
++#endif /* DHD_LOSSLESS_ROAMING */
++	} else if ((eh->ether_type == hton16(ETHER_TYPE_IP)) ||
++		(eh->ether_type == hton16(ETHER_TYPE_IPV6))) {
++		uint8 *ip_body = pktdata + sizeof(struct ether_header);
++		uint8 tos_tc = IP_TOS46(ip_body);
++		uint8 dscp = tos_tc >> IPV4_TOS_DSCP_SHIFT;
++		switch (dscp) {
++		case DSCP_EF:
++			priority = PRIO_8021D_VO;
++			break;
++		case DSCP_AF31:
++		case DSCP_AF32:
++		case DSCP_AF33:
++			priority = PRIO_8021D_CL;
++			break;
++		case DSCP_AF21:
++		case DSCP_AF22:
++		case DSCP_AF23:
++		case DSCP_AF11:
++		case DSCP_AF12:
++		case DSCP_AF13:
++			priority = PRIO_8021D_EE;
++			break;
++		default:
++			priority = (int)(tos_tc >> IPV4_TOS_PREC_SHIFT);
++			break;
++		}
++
++		rc |= PKTPRIO_DSCP;
++	}
++
++	ASSERT(priority >= 0 && priority <= MAXPRIO);
++	PKTSETPRIO(pkt, priority);
++	return (rc | priority);
++}
++
++/* lookup user priority for specified DSCP */
++static uint8
++dscp2up(uint8 *up_table, uint8 dscp)
++{
++	uint8 user_priority = 255;
++
++	/* lookup up from table if parameters valid */
++	if (up_table != NULL && dscp < UP_TABLE_MAX) {
++		user_priority = up_table[dscp];
++	}
++
++	/* 255 is unused value so return up from dscp */
++	if (user_priority == 255) {
++		user_priority = dscp >> (IPV4_TOS_PREC_SHIFT - IPV4_TOS_DSCP_SHIFT);
++	}
++
++	return user_priority;
++}
++
++/* set user priority by QoS Map Set table (UP table), table size is UP_TABLE_MAX */
++uint BCMFASTPATH
++pktsetprio_qms(void *pkt, uint8* up_table, bool update_vtag)
++{
++	if (up_table) {
++		uint8 *pktdata;
++		uint pktlen;
++		uint8 dscp;
++		uint user_priority = 0;
++		uint rc = 0;
++
++		pktdata = (uint8 *)PKTDATA(OSH_NULL, pkt);
++		pktlen = PKTLEN(OSH_NULL, pkt);
++
++		if (pktgetdscp(pktdata, pktlen, &dscp)) {
++			rc = PKTPRIO_DSCP;
++			user_priority = dscp2up(up_table, dscp);
++			PKTSETPRIO(pkt, user_priority);
++		}
++
++		return (rc | user_priority);
++	} else {
++		return pktsetprio(pkt, update_vtag);
++	}
++}
++
++/* Returns TRUE and DSCP if IP header found, FALSE otherwise.
++ */
++bool BCMFASTPATH
++pktgetdscp(uint8 *pktdata, uint pktlen, uint8 *dscp)
++{
++	struct ether_header *eh;
++	struct ethervlan_header *evh;
++	uint8 *ip_body;
++	bool rc = FALSE;
++
++	/* minimum length is ether header and IP header */
++	if (pktlen < sizeof(struct ether_header) + IPV4_MIN_HEADER_LEN)
++		return FALSE;
++
++	eh = (struct ether_header *) pktdata;
++
++	if (eh->ether_type == HTON16(ETHER_TYPE_IP)) {
++		ip_body = pktdata + sizeof(struct ether_header);
++		*dscp = IP_DSCP46(ip_body);
++		rc = TRUE;
++	}
++	else if (eh->ether_type == HTON16(ETHER_TYPE_8021Q)) {
++		evh = (struct ethervlan_header *)eh;
++
++		/* minimum length is ethervlan header and IP header */
++		if (pktlen >= sizeof(struct ethervlan_header) + IPV4_MIN_HEADER_LEN &&
++			evh->ether_type == HTON16(ETHER_TYPE_IP)) {
++			ip_body = pktdata + sizeof(struct ethervlan_header);
++			*dscp = IP_DSCP46(ip_body);
++			rc = TRUE;
++		}
++	}
++
++	return rc;
++}
++
++/* usr_prio range from low to high with usr_prio value */
++static bool
++up_table_set(uint8 *up_table, uint8 usr_prio, uint8 low, uint8 high)
++{
++	int i;
++
++	if (usr_prio > 7 || low > high || low >= UP_TABLE_MAX || high >= UP_TABLE_MAX) {
++		return FALSE;
++	}
++
++	for (i = low; i <= high; i++) {
++		up_table[i] = usr_prio;
++	}
++
++	return TRUE;
++}
++
++/* set user priority table */
++int BCMFASTPATH
++wl_set_up_table(uint8 *up_table, bcm_tlv_t *qos_map_ie)
++{
++	uint8 len;
++
++	if (up_table == NULL || qos_map_ie == NULL) {
++		return BCME_ERROR;
++	}
++
++	/* clear table to check table was set or not */
++	memset(up_table, 0xff, UP_TABLE_MAX);
++
++	/* length of QoS Map IE must be 16+n*2, n is number of exceptions */
++	if (qos_map_ie != NULL && qos_map_ie->id == DOT11_MNG_QOS_MAP_ID &&
++			(len = qos_map_ie->len) >= QOS_MAP_FIXED_LENGTH &&
++			(len % 2) == 0) {
++		uint8 *except_ptr = (uint8 *)qos_map_ie->data;
++		uint8 except_len = len - QOS_MAP_FIXED_LENGTH;
++		uint8 *range_ptr = except_ptr + except_len;
++		int i;
++
++		/* fill in ranges */
++		for (i = 0; i < QOS_MAP_FIXED_LENGTH; i += 2) {
++			uint8 low = range_ptr[i];
++			uint8 high = range_ptr[i + 1];
++			if (low == 255 && high == 255) {
++				continue;
++			}
++
++			if (!up_table_set(up_table, i / 2, low, high)) {
++				/* clear the table on failure */
++				memset(up_table, 0xff, UP_TABLE_MAX);
++				return BCME_ERROR;
++			}
++		}
++
++		/* update exceptions */
++		for (i = 0; i < except_len; i += 2) {
++			uint8 dscp = except_ptr[i];
++			uint8 usr_prio = except_ptr[i+1];
++
++			/* exceptions with invalid dscp/usr_prio are ignored */
++			up_table_set(up_table, usr_prio, dscp, dscp);
++		}
++	}
++
++	return BCME_OK;
++}
++
++/* The 0.5KB string table is not removed by compiler even though it's unused */
++
++static char bcm_undeferrstr[32];
++static const char *bcmerrorstrtable[] = BCMERRSTRINGTABLE;
++
++/* Convert the error codes into related error strings  */
++const char *
++bcmerrorstr(int bcmerror)
++{
++	/* check if someone added a bcmerror code but forgot to add errorstring */
++	ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(bcmerrorstrtable) - 1));
++
++	if (bcmerror > 0 || bcmerror < BCME_LAST) {
++		snprintf(bcm_undeferrstr, sizeof(bcm_undeferrstr), "Undefined error %d", bcmerror);
++		return bcm_undeferrstr;
++	}
++
++	ASSERT(strlen(bcmerrorstrtable[-bcmerror]) < BCME_STRLEN);
++
++	return bcmerrorstrtable[-bcmerror];
++}
++
++
++
++/* iovar table lookup */
++/* could mandate sorted tables and do a binary search */
++const bcm_iovar_t*
++bcm_iovar_lookup(const bcm_iovar_t *table, const char *name)
++{
++	const bcm_iovar_t *vi;
++	const char *lookup_name;
++
++	/* skip any ':' delimited option prefixes */
++	lookup_name = strrchr(name, ':');
++	if (lookup_name != NULL)
++		lookup_name++;
++	else
++		lookup_name = name;
++
++	ASSERT(table != NULL);
++
++	for (vi = table; vi->name; vi++) {
++		if (!strcmp(vi->name, lookup_name))
++			return vi;
++	}
++	/* ran to end of table */
++
++	return NULL; /* var name not found */
++}
++
++int
++bcm_iovar_lencheck(const bcm_iovar_t *vi, void *arg, int len, bool set)
++{
++	int bcmerror = 0;
++
++	/* length check on io buf */
++	switch (vi->type) {
++	case IOVT_BOOL:
++	case IOVT_INT8:
++	case IOVT_INT16:
++	case IOVT_INT32:
++	case IOVT_UINT8:
++	case IOVT_UINT16:
++	case IOVT_UINT32:
++		/* all integers are int32 sized args at the ioctl interface */
++		if (len < (int)sizeof(int)) {
++			bcmerror = BCME_BUFTOOSHORT;
++		}
++		break;
++
++	case IOVT_BUFFER:
++		/* buffer must meet minimum length requirement */
++		if (len < vi->minlen) {
++			bcmerror = BCME_BUFTOOSHORT;
++		}
++		break;
++
++	case IOVT_VOID:
++		if (!set) {
++			/* Cannot return nil... */
++			bcmerror = BCME_UNSUPPORTED;
++		} else if (len) {
++			/* Set is an action w/o parameters */
++			bcmerror = BCME_BUFTOOLONG;
++		}
++		break;
++
++	default:
++		/* unknown type for length check in iovar info */
++		ASSERT(0);
++		bcmerror = BCME_UNSUPPORTED;
++	}
++
++	return bcmerror;
++}
++
++#endif	/* BCMDRIVER */
++
++#ifdef BCM_OBJECT_TRACE
++
++#define BCM_OBJECT_MERGE_SAME_OBJ	0
++
++/* some place may add / remove the object to trace list for Linux: */
++/* add:    osl_alloc_skb dev_alloc_skb skb_realloc_headroom dhd_start_xmit */
++/* remove: osl_pktfree dev_kfree_skb netif_rx */
++
++#define BCM_OBJDBG_COUNT          (1024 * 100)
++static spinlock_t dbgobj_lock;
++#define	BCM_OBJDBG_LOCK_INIT()    spin_lock_init(&dbgobj_lock)
++#define	BCM_OBJDBG_LOCK_DESTROY()
++#define	BCM_OBJDBG_LOCK           spin_lock_irqsave
++#define	BCM_OBJDBG_UNLOCK         spin_unlock_irqrestore
++
++#define BCM_OBJDBG_ADDTOHEAD      0
++#define BCM_OBJDBG_ADDTOTAIL      1
++
++#define BCM_OBJDBG_CALLER_LEN     32
++struct bcm_dbgobj {
++	struct bcm_dbgobj *prior;
++	struct bcm_dbgobj *next;
++	uint32 flag;
++	void   *obj;
++	uint32 obj_sn;
++	uint32 obj_state;
++	uint32 line;
++	char   caller[BCM_OBJDBG_CALLER_LEN];
++};
++
++static struct bcm_dbgobj *dbgobj_freehead = NULL;
++static struct bcm_dbgobj *dbgobj_freetail = NULL;
++static struct bcm_dbgobj *dbgobj_objhead = NULL;
++static struct bcm_dbgobj *dbgobj_objtail = NULL;
++
++static uint32 dbgobj_sn = 0;
++static int dbgobj_count = 0;
++static struct bcm_dbgobj bcm_dbg_objs[BCM_OBJDBG_COUNT];
++
++void
++bcm_object_trace_init(void)
++{
++	int i = 0;
++	BCM_OBJDBG_LOCK_INIT();
++	memset(&bcm_dbg_objs, 0x00, sizeof(struct bcm_dbgobj) * BCM_OBJDBG_COUNT);
++	dbgobj_freehead = &bcm_dbg_objs[0];
++	dbgobj_freetail = &bcm_dbg_objs[BCM_OBJDBG_COUNT - 1];
++
++	for (i = 0; i < BCM_OBJDBG_COUNT; ++i) {
++		bcm_dbg_objs[i].next = (i == (BCM_OBJDBG_COUNT - 1)) ?
++			dbgobj_freehead : &bcm_dbg_objs[i + 1];
++		bcm_dbg_objs[i].prior = (i == 0) ?
++			dbgobj_freetail : &bcm_dbg_objs[i - 1];
++	}
++}
++
++void
++bcm_object_trace_deinit(void)
++{
++	if (dbgobj_objhead || dbgobj_objtail) {
++		printf("%s: not all objects are released\n", __FUNCTION__);
++		ASSERT(0);
++	}
++	BCM_OBJDBG_LOCK_DESTROY();
++}
++
++static void
++bcm_object_rm_list(struct bcm_dbgobj **head, struct bcm_dbgobj **tail,
++	struct bcm_dbgobj *dbgobj)
++{
++	if ((dbgobj == *head) && (dbgobj == *tail)) {
++		*head = NULL;
++		*tail = NULL;
++	} else if (dbgobj == *head) {
++		*head = (*head)->next;
++	} else if (dbgobj == *tail) {
++		*tail = (*tail)->prior;
++	}
++	dbgobj->next->prior = dbgobj->prior;
++	dbgobj->prior->next = dbgobj->next;
++}
++
++static void
++bcm_object_add_list(struct bcm_dbgobj **head, struct bcm_dbgobj **tail,
++	struct bcm_dbgobj *dbgobj, int addtotail)
++{
++	if (!(*head) && !(*tail)) {
++		*head = dbgobj;
++		*tail = dbgobj;
++		dbgobj->next = dbgobj;
++		dbgobj->prior = dbgobj;
++	} else if ((*head) && (*tail)) {
++		(*tail)->next = dbgobj;
++		(*head)->prior = dbgobj;
++		dbgobj->next = *head;
++		dbgobj->prior = *tail;
++		if (addtotail == BCM_OBJDBG_ADDTOTAIL)
++			*tail = dbgobj;
++		else
++			*head = dbgobj;
++	} else {
++		ASSERT(0); /* can't be this case */
++	}
++}
++
++static INLINE void
++bcm_object_movetoend(struct bcm_dbgobj **head, struct bcm_dbgobj **tail,
++	struct bcm_dbgobj *dbgobj, int movetotail)
++{
++	if ((*head) && (*tail)) {
++		if (movetotail == BCM_OBJDBG_ADDTOTAIL) {
++			if (dbgobj != (*tail)) {
++				bcm_object_rm_list(head, tail, dbgobj);
++				bcm_object_add_list(head, tail, dbgobj, movetotail);
++			}
++		} else {
++			if (dbgobj != (*head)) {
++				bcm_object_rm_list(head, tail, dbgobj);
++				bcm_object_add_list(head, tail, dbgobj, movetotail);
++			}
++		}
++	} else {
++		ASSERT(0); /* can't be this case */
++	}
++}
++
++void
++bcm_object_trace_opr(void *obj, uint32 opt, const char *caller, int line)
++{
++	struct bcm_dbgobj *dbgobj;
++	unsigned long flags;
++
++	BCM_REFERENCE(flags);
++	BCM_OBJDBG_LOCK(&dbgobj_lock, flags);
++
++	if (opt == BCM_OBJDBG_ADD_PKT ||
++		opt == BCM_OBJDBG_ADD) {
++		dbgobj = dbgobj_objtail;
++		while (dbgobj) {
++			if (dbgobj->obj == obj) {
++				printf("%s: obj %p allocated from %s(%d),"
++					" allocate again from %s(%d)\n",
++					__FUNCTION__, dbgobj->obj,
++					dbgobj->caller, dbgobj->line,
++					caller, line);
++				ASSERT(0);
++				goto EXIT;
++			}
++			dbgobj = dbgobj->prior;
++			if (dbgobj == dbgobj_objtail)
++				break;
++		}
++
++#if BCM_OBJECT_MERGE_SAME_OBJ
++		dbgobj = dbgobj_freetail;
++		while (dbgobj) {
++			if (dbgobj->obj == obj) {
++				goto FREED_ENTRY_FOUND;
++			}
++			dbgobj = dbgobj->prior;
++			if (dbgobj == dbgobj_freetail)
++				break;
++		}
++#endif /* BCM_OBJECT_MERGE_SAME_OBJ */
++
++		dbgobj = dbgobj_freehead;
++#if BCM_OBJECT_MERGE_SAME_OBJ
++FREED_ENTRY_FOUND:
++#endif /* BCM_OBJECT_MERGE_SAME_OBJ */
++		if (!dbgobj) {
++			printf("%s: already got %d objects ?????????????????????\n",
++				__FUNCTION__, BCM_OBJDBG_COUNT);
++			ASSERT(0);
++			goto EXIT;
++		}
++
++		bcm_object_rm_list(&dbgobj_freehead, &dbgobj_freetail, dbgobj);
++		dbgobj->obj = obj;
++		strncpy(dbgobj->caller, caller, BCM_OBJDBG_CALLER_LEN);
++		dbgobj->caller[BCM_OBJDBG_CALLER_LEN-1] = '\0';
++		dbgobj->line = line;
++		dbgobj->flag = 0;
++		if (opt == BCM_OBJDBG_ADD_PKT) {
++			dbgobj->obj_sn = dbgobj_sn++;
++			dbgobj->obj_state = 0;
++			/* first 4 bytes is pkt sn */
++			if (((unsigned long)PKTTAG(obj)) & 0x3)
++				printf("pkt tag address not aligned by 4: %p\n", PKTTAG(obj));
++			*(uint32*)PKTTAG(obj) = dbgobj->obj_sn;
++		}
++		bcm_object_add_list(&dbgobj_objhead, &dbgobj_objtail, dbgobj,
++			BCM_OBJDBG_ADDTOTAIL);
++
++		dbgobj_count++;
++
++	} else if (opt == BCM_OBJDBG_REMOVE) {
++		dbgobj = dbgobj_objtail;
++		while (dbgobj) {
++			if (dbgobj->obj == obj) {
++				if (dbgobj->flag) {
++					printf("%s: rm flagged obj %p flag 0x%08x from %s(%d)\n",
++						__FUNCTION__, obj, dbgobj->flag, caller, line);
++				}
++				bcm_object_rm_list(&dbgobj_objhead, &dbgobj_objtail, dbgobj);
++				memset(dbgobj->caller, 0x00, BCM_OBJDBG_CALLER_LEN);
++				strncpy(dbgobj->caller, caller, BCM_OBJDBG_CALLER_LEN);
++				dbgobj->caller[BCM_OBJDBG_CALLER_LEN-1] = '\0';
++				dbgobj->line = line;
++				bcm_object_add_list(&dbgobj_freehead, &dbgobj_freetail, dbgobj,
++					BCM_OBJDBG_ADDTOTAIL);
++				dbgobj_count--;
++				goto EXIT;
++			}
++			dbgobj = dbgobj->prior;
++			if (dbgobj == dbgobj_objtail)
++				break;
++		}
++
++		dbgobj = dbgobj_freetail;
++		while (dbgobj && dbgobj->obj) {
++			if (dbgobj->obj == obj) {
++				printf("%s: obj %p already freed from from %s(%d),"
++					" try free again from %s(%d)\n",
++					__FUNCTION__, obj,
++					dbgobj->caller, dbgobj->line,
++					caller, line);
++				//ASSERT(0); /* release same obj more than one time? */
++				goto EXIT;
++			}
++			dbgobj = dbgobj->prior;
++			if (dbgobj == dbgobj_freetail)
++				break;
++		}
++
++		printf("%s: ################### release none-existing obj %p from %s(%d)\n",
++			__FUNCTION__, obj, caller, line);
++		//ASSERT(0); /* release same obj more than one time? */
++
++	}
++
++EXIT:
++	BCM_OBJDBG_UNLOCK(&dbgobj_lock, flags);
++	return;
++}
++
++void
++bcm_object_trace_upd(void *obj, void *obj_new)
++{
++	struct bcm_dbgobj *dbgobj;
++	unsigned long flags;
++
++	BCM_REFERENCE(flags);
++	BCM_OBJDBG_LOCK(&dbgobj_lock, flags);
++
++	dbgobj = dbgobj_objtail;
++	while (dbgobj) {
++		if (dbgobj->obj == obj) {
++			dbgobj->obj = obj_new;
++			if (dbgobj != dbgobj_objtail) {
++				bcm_object_movetoend(&dbgobj_objhead, &dbgobj_objtail,
++					dbgobj, BCM_OBJDBG_ADDTOTAIL);
++			}
++			goto EXIT;
++		}
++		dbgobj = dbgobj->prior;
++		if (dbgobj == dbgobj_objtail)
++			break;
++	}
++
++EXIT:
++	BCM_OBJDBG_UNLOCK(&dbgobj_lock, flags);
++	return;
++}
++
++void
++bcm_object_trace_chk(void *obj, uint32 chksn, uint32 sn,
++	const char *caller, int line)
++{
++	struct bcm_dbgobj *dbgobj;
++	unsigned long flags;
++
++	BCM_REFERENCE(flags);
++	BCM_OBJDBG_LOCK(&dbgobj_lock, flags);
++
++	dbgobj = dbgobj_objtail;
++	while (dbgobj) {
++		if ((dbgobj->obj == obj) &&
++			((!chksn) || (dbgobj->obj_sn == sn))) {
++			if (dbgobj != dbgobj_objtail) {
++				bcm_object_movetoend(&dbgobj_objhead, &dbgobj_objtail,
++					dbgobj, BCM_OBJDBG_ADDTOTAIL);
++			}
++			goto EXIT;
++		}
++		dbgobj = dbgobj->prior;
++		if (dbgobj == dbgobj_objtail)
++			break;
++	}
++
++	dbgobj = dbgobj_freetail;
++	while (dbgobj) {
++		if ((dbgobj->obj == obj) &&
++			((!chksn) || (dbgobj->obj_sn == sn))) {
++			printf("%s: (%s:%d) obj %p (sn %d state %d) was freed from %s(%d)\n",
++				__FUNCTION__, caller, line,
++				dbgobj->obj, dbgobj->obj_sn, dbgobj->obj_state,
++				dbgobj->caller, dbgobj->line);
++			goto EXIT;
++		}
++		else if (dbgobj->obj == NULL) {
++			break;
++		}
++		dbgobj = dbgobj->prior;
++		if (dbgobj == dbgobj_freetail)
++			break;
++	}
++
++	printf("%s: obj %p not found, check from %s(%d), chksn %s, sn %d\n",
++		__FUNCTION__, obj, caller, line, chksn ? "yes" : "no", sn);
++	dbgobj = dbgobj_objtail;
++	while (dbgobj) {
++		printf("%s: (%s:%d) obj %p sn %d was allocated from %s(%d)\n",
++				__FUNCTION__, caller, line,
++				dbgobj->obj, dbgobj->obj_sn, dbgobj->caller, dbgobj->line);
++		dbgobj = dbgobj->prior;
++		if (dbgobj == dbgobj_objtail)
++			break;
++	}
++
++EXIT:
++	BCM_OBJDBG_UNLOCK(&dbgobj_lock, flags);
++	return;
++}
++
++void
++bcm_object_feature_set(void *obj, uint32 type, uint32 value)
++{
++	struct bcm_dbgobj *dbgobj;
++	unsigned long flags;
++
++	BCM_REFERENCE(flags);
++	BCM_OBJDBG_LOCK(&dbgobj_lock, flags);
++
++	dbgobj = dbgobj_objtail;
++	while (dbgobj) {
++		if (dbgobj->obj == obj) {
++			if (type == BCM_OBJECT_FEATURE_FLAG) {
++				if (value & BCM_OBJECT_FEATURE_CLEAR)
++					dbgobj->flag &= ~(value);
++				else
++					dbgobj->flag |= (value);
++			} else if (type == BCM_OBJECT_FEATURE_PKT_STATE) {
++				dbgobj->obj_state = value;
++			}
++			if (dbgobj != dbgobj_objtail) {
++				bcm_object_movetoend(&dbgobj_objhead, &dbgobj_objtail,
++					dbgobj, BCM_OBJDBG_ADDTOTAIL);
++			}
++			goto EXIT;
++		}
++		dbgobj = dbgobj->prior;
++		if (dbgobj == dbgobj_objtail)
++			break;
++	}
++
++	printf("%s: obj %p not found in active list\n", __FUNCTION__, obj);
++	ASSERT(0);
++
++EXIT:
++	BCM_OBJDBG_UNLOCK(&dbgobj_lock, flags);
++	return;
++}
++
++int
++bcm_object_feature_get(void *obj, uint32 type, uint32 value)
++{
++	int rtn = 0;
++	struct bcm_dbgobj *dbgobj;
++	unsigned long flags;
++
++	BCM_REFERENCE(flags);
++	BCM_OBJDBG_LOCK(&dbgobj_lock, flags);
++
++	dbgobj = dbgobj_objtail;
++	while (dbgobj) {
++		if (dbgobj->obj == obj) {
++			if (type == BCM_OBJECT_FEATURE_FLAG) {
++				rtn = (dbgobj->flag & value) & (~BCM_OBJECT_FEATURE_CLEAR);
++			}
++			if (dbgobj != dbgobj_objtail) {
++				bcm_object_movetoend(&dbgobj_objhead, &dbgobj_objtail,
++					dbgobj, BCM_OBJDBG_ADDTOTAIL);
++			}
++			goto EXIT;
++		}
++		dbgobj = dbgobj->prior;
++		if (dbgobj == dbgobj_objtail)
++			break;
++	}
++
++	printf("%s: obj %p not found in active list\n", __FUNCTION__, obj);
++	ASSERT(0);
++
++EXIT:
++	BCM_OBJDBG_UNLOCK(&dbgobj_lock, flags);
++	return rtn;
++}
++
++#endif /* BCM_OBJECT_TRACE */
++
++uint8 *
++bcm_write_tlv(int type, const void *data, int datalen, uint8 *dst)
++{
++	uint8 *new_dst = dst;
++	bcm_tlv_t *dst_tlv = (bcm_tlv_t *)dst;
++
++	/* dst buffer should always be valid */
++	ASSERT(dst);
++
++	/* data len must be within valid range */
++	ASSERT((datalen >= 0) && (datalen <= BCM_TLV_MAX_DATA_SIZE));
++
++	/* source data buffer pointer should be valid, unless datalen is 0
++	 * meaning no data with this TLV
++	 */
++	ASSERT((data != NULL) || (datalen == 0));
++
++	/* only do work if the inputs are valid
++	 * - must have a dst to write to AND
++	 * - datalen must be within range AND
++	 * - the source data pointer must be non-NULL if datalen is non-zero
++	 * (this last condition detects datalen > 0 with a NULL data pointer)
++	 */
++	if ((dst != NULL) &&
++	    ((datalen >= 0) && (datalen <= BCM_TLV_MAX_DATA_SIZE)) &&
++	    ((data != NULL) || (datalen == 0))) {
++
++	        /* write type, len fields */
++		dst_tlv->id = (uint8)type;
++	        dst_tlv->len = (uint8)datalen;
++
++		/* if data is present, copy to the output buffer and update
++		 * pointer to output buffer
++		 */
++		if (datalen > 0) {
++
++			memcpy(dst_tlv->data, data, datalen);
++		}
++
++		/* update the output destination poitner to point past
++		 * the TLV written
++		 */
++		new_dst = dst + BCM_TLV_HDR_SIZE + datalen;
++	}
++
++	return (new_dst);
++}
++
++uint8 *
++bcm_write_tlv_safe(int type, const void *data, int datalen, uint8 *dst, int dst_maxlen)
++{
++	uint8 *new_dst = dst;
++
++	if ((datalen >= 0) && (datalen <= BCM_TLV_MAX_DATA_SIZE)) {
++
++		/* if len + tlv hdr len is more than destlen, don't do anything
++		 * just return the buffer untouched
++		 */
++		if ((int)(datalen + BCM_TLV_HDR_SIZE) <= dst_maxlen) {
++
++			new_dst = bcm_write_tlv(type, data, datalen, dst);
++		}
++	}
++
++	return (new_dst);
++}
++
++uint8 *
++bcm_copy_tlv(const void *src, uint8 *dst)
++{
++	uint8 *new_dst = dst;
++	const bcm_tlv_t *src_tlv = (const bcm_tlv_t *)src;
++	uint totlen;
++
++	ASSERT(dst && src);
++	if (dst && src) {
++
++		totlen = BCM_TLV_HDR_SIZE + src_tlv->len;
++		memcpy(dst, src_tlv, totlen);
++		new_dst = dst + totlen;
++	}
++
++	return (new_dst);
++}
++
++
++uint8 *bcm_copy_tlv_safe(const void *src, uint8 *dst, int dst_maxlen)
++{
++	uint8 *new_dst = dst;
++	const bcm_tlv_t *src_tlv = (const bcm_tlv_t *)src;
++
++	ASSERT(src);
++	if (src) {
++		if (bcm_valid_tlv(src_tlv, dst_maxlen)) {
++			new_dst = bcm_copy_tlv(src, dst);
++		}
++	}
++
++	return (new_dst);
++}
++
++
++#if !defined(BCMROMOFFLOAD_EXCLUDE_BCMUTILS_FUNCS)
++/*******************************************************************************
++ * crc8
++ *
++ * Computes a crc8 over the input data using the polynomial:
++ *
++ *       x^8 + x^7 +x^6 + x^4 + x^2 + 1
++ *
++ * The caller provides the initial value (either CRC8_INIT_VALUE
++ * or the previous returned value) to allow for processing of
++ * discontiguous blocks of data.  When generating the CRC the
++ * caller is responsible for complementing the final return value
++ * and inserting it into the byte stream.  When checking, a final
++ * return value of CRC8_GOOD_VALUE indicates a valid CRC.
++ *
++ * Reference: Dallas Semiconductor Application Note 27
++ *   Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
++ *     ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
++ *     ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
++ *
++ * ****************************************************************************
++ */
++
++static const uint8 crc8_table[256] = {
++    0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
++    0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
++    0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
++    0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
++    0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
++    0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
++    0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
++    0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
++    0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
++    0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
++    0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
++    0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
++    0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
++    0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
++    0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
++    0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
++    0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
++    0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
++    0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
++    0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
++    0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
++    0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
++    0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
++    0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
++    0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
++    0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
++    0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
++    0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
++    0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
++    0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
++    0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
++    0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
++};
++
++#define CRC_INNER_LOOP(n, c, x) \
++	(c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
++
++uint8
++hndcrc8(
++	uint8 *pdata,	/* pointer to array of data to process */
++	uint  nbytes,	/* number of input data bytes to process */
++	uint8 crc	/* either CRC8_INIT_VALUE or previous return value */
++)
++{
++	/* hard code the crc loop instead of using CRC_INNER_LOOP macro
++	 * to avoid the undefined and unnecessary (uint8 >> 8) operation.
++	 */
++	while (nbytes-- > 0)
++		crc = crc8_table[(crc ^ *pdata++) & 0xff];
++
++	return crc;
++}
++
++/*******************************************************************************
++ * crc16
++ *
++ * Computes a crc16 over the input data using the polynomial:
++ *
++ *       x^16 + x^12 +x^5 + 1
++ *
++ * The caller provides the initial value (either CRC16_INIT_VALUE
++ * or the previous returned value) to allow for processing of
++ * discontiguous blocks of data.  When generating the CRC the
++ * caller is responsible for complementing the final return value
++ * and inserting it into the byte stream.  When checking, a final
++ * return value of CRC16_GOOD_VALUE indicates a valid CRC.
++ *
++ * Reference: Dallas Semiconductor Application Note 27
++ *   Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
++ *     ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
++ *     ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
++ *
++ * ****************************************************************************
++ */
++
++static const uint16 crc16_table[256] = {
++    0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF,
++    0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7,
++    0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E,
++    0x9CC9, 0x8D40, 0xBFDB, 0xAE52, 0xDAED, 0xCB64, 0xF9FF, 0xE876,
++    0x2102, 0x308B, 0x0210, 0x1399, 0x6726, 0x76AF, 0x4434, 0x55BD,
++    0xAD4A, 0xBCC3, 0x8E58, 0x9FD1, 0xEB6E, 0xFAE7, 0xC87C, 0xD9F5,
++    0x3183, 0x200A, 0x1291, 0x0318, 0x77A7, 0x662E, 0x54B5, 0x453C,
++    0xBDCB, 0xAC42, 0x9ED9, 0x8F50, 0xFBEF, 0xEA66, 0xD8FD, 0xC974,
++    0x4204, 0x538D, 0x6116, 0x709F, 0x0420, 0x15A9, 0x2732, 0x36BB,
++    0xCE4C, 0xDFC5, 0xED5E, 0xFCD7, 0x8868, 0x99E1, 0xAB7A, 0xBAF3,
++    0x5285, 0x430C, 0x7197, 0x601E, 0x14A1, 0x0528, 0x37B3, 0x263A,
++    0xDECD, 0xCF44, 0xFDDF, 0xEC56, 0x98E9, 0x8960, 0xBBFB, 0xAA72,
++    0x6306, 0x728F, 0x4014, 0x519D, 0x2522, 0x34AB, 0x0630, 0x17B9,
++    0xEF4E, 0xFEC7, 0xCC5C, 0xDDD5, 0xA96A, 0xB8E3, 0x8A78, 0x9BF1,
++    0x7387, 0x620E, 0x5095, 0x411C, 0x35A3, 0x242A, 0x16B1, 0x0738,
++    0xFFCF, 0xEE46, 0xDCDD, 0xCD54, 0xB9EB, 0xA862, 0x9AF9, 0x8B70,
++    0x8408, 0x9581, 0xA71A, 0xB693, 0xC22C, 0xD3A5, 0xE13E, 0xF0B7,
++    0x0840, 0x19C9, 0x2B52, 0x3ADB, 0x4E64, 0x5FED, 0x6D76, 0x7CFF,
++    0x9489, 0x8500, 0xB79B, 0xA612, 0xD2AD, 0xC324, 0xF1BF, 0xE036,
++    0x18C1, 0x0948, 0x3BD3, 0x2A5A, 0x5EE5, 0x4F6C, 0x7DF7, 0x6C7E,
++    0xA50A, 0xB483, 0x8618, 0x9791, 0xE32E, 0xF2A7, 0xC03C, 0xD1B5,
++    0x2942, 0x38CB, 0x0A50, 0x1BD9, 0x6F66, 0x7EEF, 0x4C74, 0x5DFD,
++    0xB58B, 0xA402, 0x9699, 0x8710, 0xF3AF, 0xE226, 0xD0BD, 0xC134,
++    0x39C3, 0x284A, 0x1AD1, 0x0B58, 0x7FE7, 0x6E6E, 0x5CF5, 0x4D7C,
++    0xC60C, 0xD785, 0xE51E, 0xF497, 0x8028, 0x91A1, 0xA33A, 0xB2B3,
++    0x4A44, 0x5BCD, 0x6956, 0x78DF, 0x0C60, 0x1DE9, 0x2F72, 0x3EFB,
++    0xD68D, 0xC704, 0xF59F, 0xE416, 0x90A9, 0x8120, 0xB3BB, 0xA232,
++    0x5AC5, 0x4B4C, 0x79D7, 0x685E, 0x1CE1, 0x0D68, 0x3FF3, 0x2E7A,
++    0xE70E, 0xF687, 0xC41C, 0xD595, 0xA12A, 0xB0A3, 0x8238, 0x93B1,
++    0x6B46, 0x7ACF, 0x4854, 0x59DD, 0x2D62, 0x3CEB, 0x0E70, 0x1FF9,
++    0xF78F, 0xE606, 0xD49D, 0xC514, 0xB1AB, 0xA022, 0x92B9, 0x8330,
++    0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78
++};
++
++uint16
++hndcrc16(
++    uint8 *pdata,  /* pointer to array of data to process */
++    uint nbytes, /* number of input data bytes to process */
++    uint16 crc     /* either CRC16_INIT_VALUE or previous return value */
++)
++{
++	while (nbytes-- > 0)
++		CRC_INNER_LOOP(16, crc, *pdata++);
++	return crc;
++}
++
++static const uint32 crc32_table[256] = {
++    0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
++    0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
++    0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
++    0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
++    0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
++    0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
++    0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
++    0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
++    0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
++    0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
++    0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
++    0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
++    0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
++    0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
++    0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
++    0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
++    0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
++    0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
++    0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
++    0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
++    0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
++    0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
++    0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
++    0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
++    0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
++    0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
++    0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
++    0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
++    0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
++    0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
++    0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
++    0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
++    0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
++    0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
++    0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
++    0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
++    0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
++    0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
++    0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
++    0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
++    0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
++    0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
++    0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
++    0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
++    0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
++    0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
++    0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
++    0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
++    0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
++    0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
++    0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
++    0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
++    0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
++    0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
++    0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
++    0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
++    0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
++    0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
++    0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
++    0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
++    0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
++    0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
++    0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
++    0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
++};
++
++/*
++ * crc input is CRC32_INIT_VALUE for a fresh start, or previous return value if
++ * accumulating over multiple pieces.
++ */
++uint32
++hndcrc32(uint8 *pdata, uint nbytes, uint32 crc)
++{
++	uint8 *pend;
++	pend = pdata + nbytes;
++	while (pdata < pend)
++		CRC_INNER_LOOP(32, crc, *pdata++);
++
++	return crc;
++}
++
++#ifdef notdef
++#define CLEN 	1499 	/*  CRC Length */
++#define CBUFSIZ 	(CLEN+4)
++#define CNBUFS		5 /* # of bufs */
++
++void
++testcrc32(void)
++{
++	uint j, k, l;
++	uint8 *buf;
++	uint len[CNBUFS];
++	uint32 crcr;
++	uint32 crc32tv[CNBUFS] =
++		{0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110};
++
++	ASSERT((buf = MALLOC(CBUFSIZ*CNBUFS)) != NULL);
++
++	/* step through all possible alignments */
++	for (l = 0; l <= 4; l++) {
++		for (j = 0; j < CNBUFS; j++) {
++			len[j] = CLEN;
++			for (k = 0; k < len[j]; k++)
++				*(buf + j*CBUFSIZ + (k+l)) = (j+k) & 0xff;
++		}
++
++		for (j = 0; j < CNBUFS; j++) {
++			crcr = crc32(buf + j*CBUFSIZ + l, len[j], CRC32_INIT_VALUE);
++			ASSERT(crcr == crc32tv[j]);
++		}
++	}
++
++	MFREE(buf, CBUFSIZ*CNBUFS);
++	return;
++}
++#endif /* notdef */
++
++/*
++ * Advance from the current 1-byte tag/1-byte length/variable-length value
++ * triple, to the next, returning a pointer to the next.
++ * If the current or next TLV is invalid (does not fit in given buffer length),
++ * NULL is returned.
++ * *buflen is not modified if the TLV elt parameter is invalid, or is decremented
++ * by the TLV parameter's length if it is valid.
++ */
++bcm_tlv_t *
++bcm_next_tlv(bcm_tlv_t *elt, int *buflen)
++{
++	int len;
++
++	/* validate current elt */
++	if (!bcm_valid_tlv(elt, *buflen)) {
++		return NULL;
++	}
++
++	/* advance to next elt */
++	len = elt->len;
++	elt = (bcm_tlv_t*)(elt->data + len);
++	*buflen -= (TLV_HDR_LEN + len);
++
++	/* validate next elt */
++	if (!bcm_valid_tlv(elt, *buflen)) {
++		return NULL;
++	}
++
++	return elt;
++}
++
++/*
++ * Traverse a string of 1-byte tag/1-byte length/variable-length value
++ * triples, returning a pointer to the substring whose first element
++ * matches tag
++ */
++bcm_tlv_t *
++bcm_parse_tlvs(void *buf, int buflen, uint key)
++{
++	bcm_tlv_t *elt;
++	int totlen;
++
++	if ((elt = (bcm_tlv_t*)buf) == NULL) {
++		return NULL;
++	}
++	totlen = buflen;
++
++	/* find tagged parameter */
++	while (totlen >= TLV_HDR_LEN) {
++		int len = elt->len;
++
++		/* validate remaining totlen */
++		if ((elt->id == key) && (totlen >= (int)(len + TLV_HDR_LEN))) {
++
++			return (elt);
++		}
++
++		elt = (bcm_tlv_t*)((uint8*)elt + (len + TLV_HDR_LEN));
++		totlen -= (len + TLV_HDR_LEN);
++	}
++
++	return NULL;
++}
++
++/*
++ * Traverse a string of 1-byte tag/1-byte length/variable-length value
++ * triples, returning a pointer to the substring whose first element
++ * matches tag
++ * return NULL if not found or length field < min_varlen
++ */
++bcm_tlv_t *
++bcm_parse_tlvs_min_bodylen(void *buf, int buflen, uint key, int min_bodylen)
++{
++	bcm_tlv_t * ret = bcm_parse_tlvs(buf, buflen, key);
++	if (ret == NULL || ret->len < min_bodylen) {
++		return NULL;
++	}
++	return ret;
++}
++
++/*
++ * Traverse a string of 1-byte tag/1-byte length/variable-length value
++ * triples, returning a pointer to the substring whose first element
++ * matches tag.  Stop parsing when we see an element whose ID is greater
++ * than the target key.
++ */
++bcm_tlv_t *
++bcm_parse_ordered_tlvs(void *buf, int buflen, uint key)
++{
++	bcm_tlv_t *elt;
++	int totlen;
++
++	elt = (bcm_tlv_t*)buf;
++	totlen = buflen;
++
++	/* find tagged parameter */
++	while (totlen >= TLV_HDR_LEN) {
++		uint id = elt->id;
++		int len = elt->len;
++
++		/* Punt if we start seeing IDs > than target key */
++		if (id > key) {
++			return (NULL);
++		}
++
++		/* validate remaining totlen */
++		if ((id == key) && (totlen >= (int)(len + TLV_HDR_LEN))) {
++			return (elt);
++		}
++
++		elt = (bcm_tlv_t*)((uint8*)elt + (len + TLV_HDR_LEN));
++		totlen -= (len + TLV_HDR_LEN);
++	}
++	return NULL;
++}
++#endif	/* !BCMROMOFFLOAD_EXCLUDE_BCMUTILS_FUNCS */
++
++#if defined(WLMSG_PRHDRS) || defined(WLMSG_PRPKT) || defined(WLMSG_ASSOC) || \
++	defined(DHD_DEBUG)
++int
++bcm_format_field(const bcm_bit_desc_ex_t *bd, uint32 flags, char* buf, int len)
++{
++	int i, slen = 0;
++	uint32 bit, mask;
++	const char *name;
++	mask = bd->mask;
++	if (len < 2 || !buf)
++		return 0;
++
++	buf[0] = '\0';
++
++	for (i = 0;  (name = bd->bitfield[i].name) != NULL; i++) {
++		bit = bd->bitfield[i].bit;
++		if ((flags & mask) == bit) {
++			if (len > (int)strlen(name)) {
++				slen = strlen(name);
++				strncpy(buf, name, slen+1);
++			}
++			break;
++		}
++	}
++	return slen;
++}
++
++int
++bcm_format_flags(const bcm_bit_desc_t *bd, uint32 flags, char* buf, int len)
++{
++	int i;
++	char* p = buf;
++	char hexstr[16];
++	int slen = 0, nlen = 0;
++	uint32 bit;
++	const char* name;
++
++	if (len < 2 || !buf)
++		return 0;
++
++	buf[0] = '\0';
++
++	for (i = 0; flags != 0; i++) {
++		bit = bd[i].bit;
++		name = bd[i].name;
++		if (bit == 0 && flags != 0) {
++			/* print any unnamed bits */
++			snprintf(hexstr, 16, "0x%X", flags);
++			name = hexstr;
++			flags = 0;	/* exit loop */
++		} else if ((flags & bit) == 0)
++			continue;
++		flags &= ~bit;
++		nlen = strlen(name);
++		slen += nlen;
++		/* count btwn flag space */
++		if (flags != 0)
++			slen += 1;
++		/* need NULL char as well */
++		if (len <= slen)
++			break;
++		/* copy NULL char but don't count it */
++		strncpy(p, name, nlen + 1);
++		p += nlen;
++		/* copy btwn flag space and NULL char */
++		if (flags != 0)
++			p += snprintf(p, 2, " ");
++	}
++
++	/* indicate the str was too short */
++	if (flags != 0) {
++		p += snprintf(p, 2, ">");
++	}
++
++	return (int)(p - buf);
++}
++#endif 
++
++/* print bytes formatted as hex to a string. return the resulting string length */
++int
++bcm_format_hex(char *str, const void *bytes, int len)
++{
++	int i;
++	char *p = str;
++	const uint8 *src = (const uint8*)bytes;
++
++	for (i = 0; i < len; i++) {
++		p += snprintf(p, 3, "%02X", *src);
++		src++;
++	}
++	return (int)(p - str);
++}
++
++/* pretty hex print a contiguous buffer */
++void
++prhex(const char *msg, uchar *buf, uint nbytes)
++{
++	char line[128], *p;
++	int len = sizeof(line);
++	int nchar;
++	uint i;
++
++	if (msg && (msg[0] != '\0'))
++		printf("%s:\n", msg);
++
++	p = line;
++	for (i = 0; i < nbytes; i++) {
++		if (i % 16 == 0) {
++			nchar = snprintf(p, len, "  %04x: ", i);	/* line prefix */
++			p += nchar;
++			len -= nchar;
++		}
++		if (len > 0) {
++			nchar = snprintf(p, len, "%02x ", buf[i]);
++			p += nchar;
++			len -= nchar;
++		}
++
++		if (i % 16 == 15) {
++			printf("%s\n", line);		/* flush line */
++			p = line;
++			len = sizeof(line);
++		}
++	}
++
++	/* flush last partial line */
++	if (p != line)
++		printf("%s\n", line);
++}
++
++static const char *crypto_algo_names[] = {
++	"NONE",
++	"WEP1",
++	"TKIP",
++	"WEP128",
++	"AES_CCM",
++	"AES_OCB_MSDU",
++	"AES_OCB_MPDU",
++	"NALG",
++	"UNDEF",
++	"UNDEF",
++	"UNDEF",
++	"WAPI",
++	"PMK",
++	"BIP",
++	"AES_GCM",
++	"AES_CCM256",
++	"AES_GCM256",
++	"BIP_CMAC256",
++	"BIP_GMAC",
++	"BIP_GMAC256",
++	"UNDEF"
++};
++
++const char *
++bcm_crypto_algo_name(uint algo)
++{
++	return (algo < ARRAYSIZE(crypto_algo_names)) ? crypto_algo_names[algo] : "ERR";
++}
++
++
++char *
++bcm_chipname(uint chipid, char *buf, uint len)
++{
++	const char *fmt;
++
++	fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
++	snprintf(buf, len, fmt, chipid);
++	return buf;
++}
++
++/* Produce a human-readable string for boardrev */
++char *
++bcm_brev_str(uint32 brev, char *buf)
++{
++	if (brev < 0x100)
++		snprintf(buf, 8, "%d.%d", (brev & 0xf0) >> 4, brev & 0xf);
++	else
++		snprintf(buf, 8, "%c%03x", ((brev & 0xf000) == 0x1000) ? 'P' : 'A', brev & 0xfff);
++
++	return (buf);
++}
++
++#define BUFSIZE_TODUMP_ATONCE 512 /* Buffer size */
++
++/* dump large strings to console */
++void
++printbig(char *buf)
++{
++	uint len, max_len;
++	char c;
++
++	len = (uint)strlen(buf);
++
++	max_len = BUFSIZE_TODUMP_ATONCE;
++
++	while (len > max_len) {
++		c = buf[max_len];
++		buf[max_len] = '\0';
++		printf("%s", buf);
++		buf[max_len] = c;
++
++		buf += max_len;
++		len -= max_len;
++	}
++	/* print the remaining string */
++	printf("%s\n", buf);
++	return;
++}
++
++/* routine to dump fields in a fileddesc structure */
++uint
++bcmdumpfields(bcmutl_rdreg_rtn read_rtn, void *arg0, uint arg1, struct fielddesc *fielddesc_array,
++	char *buf, uint32 bufsize)
++{
++	uint  filled_len;
++	int len;
++	struct fielddesc *cur_ptr;
++
++	filled_len = 0;
++	cur_ptr = fielddesc_array;
++
++	while (bufsize > 1) {
++		if (cur_ptr->nameandfmt == NULL)
++			break;
++		len = snprintf(buf, bufsize, cur_ptr->nameandfmt,
++		               read_rtn(arg0, arg1, cur_ptr->offset));
++		/* check for snprintf overflow or error */
++		if (len < 0 || (uint32)len >= bufsize)
++			len = bufsize - 1;
++		buf += len;
++		bufsize -= len;
++		filled_len += len;
++		cur_ptr++;
++	}
++	return filled_len;
++}
++
++uint
++bcm_mkiovar(const char *name, char *data, uint datalen, char *buf, uint buflen)
++{
++	uint len;
++
++	len = (uint)strlen(name) + 1;
++
++	if ((len + datalen) > buflen)
++		return 0;
++
++	strncpy(buf, name, buflen);
++
++	/* append data onto the end of the name string */
++	if (data && datalen != 0) {
++		memcpy(&buf[len], data, datalen);
++		len += datalen;
++	}
++
++	return len;
++}
++
++/* Quarter dBm units to mW
++ * Table starts at QDBM_OFFSET, so the first entry is mW for qdBm=153
++ * Table is offset so the last entry is largest mW value that fits in
++ * a uint16.
++ */
++
++#define QDBM_OFFSET 153		/* Offset for first entry */
++#define QDBM_TABLE_LEN 40	/* Table size */
++
++/* Smallest mW value that will round up to the first table entry, QDBM_OFFSET.
++ * Value is ( mW(QDBM_OFFSET - 1) + mW(QDBM_OFFSET) ) / 2
++ */
++#define QDBM_TABLE_LOW_BOUND 6493 /* Low bound */
++
++/* Largest mW value that will round down to the last table entry,
++ * QDBM_OFFSET + QDBM_TABLE_LEN-1.
++ * Value is ( mW(QDBM_OFFSET + QDBM_TABLE_LEN - 1) + mW(QDBM_OFFSET + QDBM_TABLE_LEN) ) / 2.
++ */
++#define QDBM_TABLE_HIGH_BOUND 64938 /* High bound */
++
++static const uint16 nqdBm_to_mW_map[QDBM_TABLE_LEN] = {
++/* qdBm: 	+0 	+1 	+2 	+3 	+4 	+5 	+6 	+7 */
++/* 153: */      6683,	7079,	7499,	7943,	8414,	8913,	9441,	10000,
++/* 161: */      10593,	11220,	11885,	12589,	13335,	14125,	14962,	15849,
++/* 169: */      16788,	17783,	18836,	19953,	21135,	22387,	23714,	25119,
++/* 177: */      26607,	28184,	29854,	31623,	33497,	35481,	37584,	39811,
++/* 185: */      42170,	44668,	47315,	50119,	53088,	56234,	59566,	63096
++};
++
++uint16
++bcm_qdbm_to_mw(uint8 qdbm)
++{
++	uint factor = 1;
++	int idx = qdbm - QDBM_OFFSET;
++
++	if (idx >= QDBM_TABLE_LEN) {
++		/* clamp to max uint16 mW value */
++		return 0xFFFF;
++	}
++
++	/* scale the qdBm index up to the range of the table 0-40
++	 * where an offset of 40 qdBm equals a factor of 10 mW.
++	 */
++	while (idx < 0) {
++		idx += 40;
++		factor *= 10;
++	}
++
++	/* return the mW value scaled down to the correct factor of 10,
++	 * adding in factor/2 to get proper rounding.
++	 */
++	return ((nqdBm_to_mW_map[idx] + factor/2) / factor);
++}
++
++uint8
++bcm_mw_to_qdbm(uint16 mw)
++{
++	uint8 qdbm;
++	int offset;
++	uint mw_uint = mw;
++	uint boundary;
++
++	/* handle boundary case */
++	if (mw_uint <= 1)
++		return 0;
++
++	offset = QDBM_OFFSET;
++
++	/* move mw into the range of the table */
++	while (mw_uint < QDBM_TABLE_LOW_BOUND) {
++		mw_uint *= 10;
++		offset -= 40;
++	}
++
++	for (qdbm = 0; qdbm < QDBM_TABLE_LEN-1; qdbm++) {
++		boundary = nqdBm_to_mW_map[qdbm] + (nqdBm_to_mW_map[qdbm+1] -
++		                                    nqdBm_to_mW_map[qdbm])/2;
++		if (mw_uint < boundary) break;
++	}
++
++	qdbm += (uint8)offset;
++
++	return (qdbm);
++}
++
++
++uint
++bcm_bitcount(uint8 *bitmap, uint length)
++{
++	uint bitcount = 0, i;
++	uint8 tmp;
++	for (i = 0; i < length; i++) {
++		tmp = bitmap[i];
++		while (tmp) {
++			bitcount++;
++			tmp &= (tmp - 1);
++		}
++	}
++	return bitcount;
++}
++
++#if defined(BCMDRIVER) || defined(WL_UNITTEST)
++
++/* triggers bcm_bprintf to print to kernel log */
++bool bcm_bprintf_bypass = FALSE;
++
++/* Initialization of bcmstrbuf structure */
++void
++bcm_binit(struct bcmstrbuf *b, char *buf, uint size)
++{
++	b->origsize = b->size = size;
++	b->origbuf = b->buf = buf;
++}
++
++/* Buffer sprintf wrapper to guard against buffer overflow */
++int
++bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...)
++{
++	va_list ap;
++	int r;
++
++	va_start(ap, fmt);
++
++	r = vsnprintf(b->buf, b->size, fmt, ap);
++	if (bcm_bprintf_bypass == TRUE) {
++		printf(b->buf);
++		goto exit;
++	}
++
++	/* Non Ansi C99 compliant returns -1,
++	 * Ansi compliant return r >= b->size,
++	 * bcmstdlib returns 0, handle all
++	 */
++	/* r == 0 is also the case when strlen(fmt) is zero.
++	 * typically the case when "" is passed as argument.
++	 */
++	if ((r == -1) || (r >= (int)b->size)) {
++		b->size = 0;
++	} else {
++		b->size -= r;
++		b->buf += r;
++	}
++
++exit:
++	va_end(ap);
++
++	return r;
++}
++
++void
++bcm_bprhex(struct bcmstrbuf *b, const char *msg, bool newline, const uint8 *buf, int len)
++{
++	int i;
++
++	if (msg != NULL && msg[0] != '\0')
++		bcm_bprintf(b, "%s", msg);
++	for (i = 0; i < len; i ++)
++		bcm_bprintf(b, "%02X", buf[i]);
++	if (newline)
++		bcm_bprintf(b, "\n");
++}
++
++void
++bcm_inc_bytes(uchar *num, int num_bytes, uint8 amount)
++{
++	int i;
++
++	for (i = 0; i < num_bytes; i++) {
++		num[i] += amount;
++		if (num[i] >= amount)
++			break;
++		amount = 1;
++	}
++}
++
++int
++bcm_cmp_bytes(const uchar *arg1, const uchar *arg2, uint8 nbytes)
++{
++	int i;
++
++	for (i = nbytes - 1; i >= 0; i--) {
++		if (arg1[i] != arg2[i])
++			return (arg1[i] - arg2[i]);
++	}
++	return 0;
++}
++
++void
++bcm_print_bytes(const char *name, const uchar *data, int len)
++{
++	int i;
++	int per_line = 0;
++
++	printf("%s: %d \n", name ? name : "", len);
++	for (i = 0; i < len; i++) {
++		printf("%02x ", *data++);
++		per_line++;
++		if (per_line == 16) {
++			per_line = 0;
++			printf("\n");
++		}
++	}
++	printf("\n");
++}
++
++/* Look for vendor-specific IE with specified OUI and optional type */
++bcm_tlv_t *
++bcm_find_vendor_ie(void *tlvs, int tlvs_len, const char *voui, uint8 *type, int type_len)
++{
++	bcm_tlv_t *ie;
++	uint8 ie_len;
++
++	ie = (bcm_tlv_t*)tlvs;
++
++	/* make sure we are looking at a valid IE */
++	if (ie == NULL || !bcm_valid_tlv(ie, tlvs_len)) {
++		return NULL;
++	}
++
++	/* Walk through the IEs looking for an OUI match */
++	do {
++		ie_len = ie->len;
++		if ((ie->id == DOT11_MNG_PROPR_ID) &&
++		    (ie_len >= (DOT11_OUI_LEN + type_len)) &&
++		    !bcmp(ie->data, voui, DOT11_OUI_LEN))
++		{
++			/* compare optional type */
++			if (type_len == 0 ||
++			    !bcmp(&ie->data[DOT11_OUI_LEN], type, type_len)) {
++				return (ie);		/* a match */
++			}
++		}
++	} while ((ie = bcm_next_tlv(ie, &tlvs_len)) != NULL);
++
++	return NULL;
++}
++
++#if defined(WLTINYDUMP) || defined(WLMSG_INFORM) || defined(WLMSG_ASSOC) || \
++	defined(WLMSG_PRPKT) || defined(WLMSG_WSEC)
++#define SSID_FMT_BUF_LEN	((4 * DOT11_MAX_SSID_LEN) + 1)
++
++int
++bcm_format_ssid(char* buf, const uchar ssid[], uint ssid_len)
++{
++	uint i, c;
++	char *p = buf;
++	char *endp = buf + SSID_FMT_BUF_LEN;
++
++	if (ssid_len > DOT11_MAX_SSID_LEN) ssid_len = DOT11_MAX_SSID_LEN;
++
++	for (i = 0; i < ssid_len; i++) {
++		c = (uint)ssid[i];
++		if (c == '\\') {
++			*p++ = '\\';
++			*p++ = '\\';
++		} else if (bcm_isprint((uchar)c)) {
++			*p++ = (char)c;
++		} else {
++			p += snprintf(p, (endp - p), "\\x%02X", c);
++		}
++	}
++	*p = '\0';
++	ASSERT(p < endp);
++
++	return (int)(p - buf);
++}
++#endif 
++
++#endif /* BCMDRIVER || WL_UNITTEST */
++
++/*
++ * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file and ending in a NUL.
++ * also accepts nvram files which are already in the format of <var1>=<value>\0\<var2>=<value2>\0
++ * Removes carriage returns, empty lines, comment lines, and converts newlines to NULs.
++ * Shortens buffer as needed and pads with NULs.  End of buffer is marked by two NULs.
++*/
++
++unsigned int
++process_nvram_vars(char *varbuf, unsigned int len)
++{
++	char *dp;
++	bool findNewline;
++	int column;
++	unsigned int buf_len, n;
++	unsigned int pad = 0;
++
++	dp = varbuf;
++
++	findNewline = FALSE;
++	column = 0;
++
++	for (n = 0; n < len; n++) {
++		if (varbuf[n] == '\r')
++			continue;
++		if (findNewline && varbuf[n] != '\n')
++			continue;
++		findNewline = FALSE;
++		if (varbuf[n] == '#') {
++			findNewline = TRUE;
++			continue;
++		}
++		if (varbuf[n] == '\n') {
++			if (column == 0)
++				continue;
++			*dp++ = 0;
++			column = 0;
++			continue;
++		}
++		*dp++ = varbuf[n];
++		column++;
++	}
++	buf_len = (unsigned int)(dp - varbuf);
++	if (buf_len % 4) {
++		pad = 4 - buf_len % 4;
++		if (pad && (buf_len + pad <= len)) {
++			buf_len += pad;
++		}
++	}
++
++	while (dp < varbuf + n)
++		*dp++ = 0;
++
++	return buf_len;
++}
++
++/* calculate a * b + c */
++void
++bcm_uint64_multiple_add(uint32* r_high, uint32* r_low, uint32 a, uint32 b, uint32 c)
++{
++#define FORMALIZE(var) {cc += (var & 0x80000000) ? 1 : 0; var &= 0x7fffffff;}
++	uint32 r1, r0;
++	uint32 a1, a0, b1, b0, t, cc = 0;
++
++	a1 = a >> 16;
++	a0 = a & 0xffff;
++	b1 = b >> 16;
++	b0 = b & 0xffff;
++
++	r0 = a0 * b0;
++	FORMALIZE(r0);
++
++	t = (a1 * b0) << 16;
++	FORMALIZE(t);
++
++	r0 += t;
++	FORMALIZE(r0);
++
++	t = (a0 * b1) << 16;
++	FORMALIZE(t);
++
++	r0 += t;
++	FORMALIZE(r0);
++
++	FORMALIZE(c);
++
++	r0 += c;
++	FORMALIZE(r0);
++
++	r0 |= (cc % 2) ? 0x80000000 : 0;
++	r1 = a1 * b1 + ((a1 * b0) >> 16) + ((b1 * a0) >> 16) + (cc / 2);
++
++	*r_high = r1;
++	*r_low = r0;
++}
++
++/* calculate a / b */
++void
++bcm_uint64_divide(uint32* r, uint32 a_high, uint32 a_low, uint32 b)
++{
++	uint32 a1 = a_high, a0 = a_low, r0 = 0;
++
++	if (b < 2)
++		return;
++
++	while (a1 != 0) {
++		r0 += (0xffffffff / b) * a1;
++		bcm_uint64_multiple_add(&a1, &a0, ((0xffffffff % b) + 1) % b, a1, a0);
++	}
++
++	r0 += a0 / b;
++	*r = r0;
++}
++
++#ifndef setbit /* As in the header file */
++#ifdef BCMUTILS_BIT_MACROS_USE_FUNCS
++/* Set bit in byte array. */
++void
++setbit(void *array, uint bit)
++{
++	((uint8 *)array)[bit / NBBY] |= 1 << (bit % NBBY);
++}
++
++/* Clear bit in byte array. */
++void
++clrbit(void *array, uint bit)
++{
++	((uint8 *)array)[bit / NBBY] &= ~(1 << (bit % NBBY));
++}
++
++/* Test if bit is set in byte array. */
++bool
++isset(const void *array, uint bit)
++{
++	return (((const uint8 *)array)[bit / NBBY] & (1 << (bit % NBBY)));
++}
++
++/* Test if bit is clear in byte array. */
++bool
++isclr(const void *array, uint bit)
++{
++	return ((((const uint8 *)array)[bit / NBBY] & (1 << (bit % NBBY))) == 0);
++}
++#endif /* BCMUTILS_BIT_MACROS_USE_FUNCS */
++#endif /* setbit */
++
++void
++set_bitrange(void *array, uint start, uint end, uint maxbit)
++{
++	uint startbyte = start/NBBY;
++	uint endbyte = end/NBBY;
++	uint i, startbytelastbit, endbytestartbit;
++
++	if (end >= start) {
++		if (endbyte - startbyte > 1)
++		{
++			startbytelastbit = (startbyte+1)*NBBY - 1;
++			endbytestartbit = endbyte*NBBY;
++			for (i = startbyte+1; i < endbyte; i++)
++				((uint8 *)array)[i] = 0xFF;
++			for (i = start; i <= startbytelastbit; i++)
++				setbit(array, i);
++			for (i = endbytestartbit; i <= end; i++)
++				setbit(array, i);
++		} else {
++			for (i = start; i <= end; i++)
++				setbit(array, i);
++		}
++	}
++	else {
++		set_bitrange(array, start, maxbit, maxbit);
++		set_bitrange(array, 0, end, maxbit);
++	}
++}
++
++void
++bcm_bitprint32(const uint32 u32arg)
++{
++	int i;
++	for (i = NBITS(uint32) - 1; i >= 0; i--) {
++		printf(isbitset(u32arg, i) ? "1" : "0");
++		if ((i % NBBY) == 0) printf(" ");
++	}
++	printf("\n");
++}
++
++/* calculate checksum for ip header, tcp / udp header / data */
++uint16
++bcm_ip_cksum(uint8 *buf, uint32 len, uint32 sum)
++{
++	while (len > 1) {
++		sum += (buf[0] << 8) | buf[1];
++		buf += 2;
++		len -= 2;
++	}
++
++	if (len > 0) {
++		sum += (*buf) << 8;
++	}
++
++	while (sum >> 16) {
++		sum = (sum & 0xffff) + (sum >> 16);
++	}
++
++	return ((uint16)~sum);
++}
++#if defined(BCMDRIVER) && !defined(_CFEZ_)
++/*
++ * Hierarchical Multiword bitmap based small id allocator.
++ *
++ * Multilevel hierarchy bitmap. (maximum 2 levels)
++ * First hierarchy uses a multiword bitmap to identify 32bit words in the
++ * second hierarchy that have at least a single bit set. Each bit in a word of
++ * the second hierarchy represents a unique ID that may be allocated.
++ *
++ * BCM_MWBMAP_ITEMS_MAX: Maximum number of IDs managed.
++ * BCM_MWBMAP_BITS_WORD: Number of bits in a bitmap word word
++ * BCM_MWBMAP_WORDS_MAX: Maximum number of bitmap words needed for free IDs.
++ * BCM_MWBMAP_WDMAP_MAX: Maximum number of bitmap wordss identifying first non
++ *                       non-zero bitmap word carrying at least one free ID.
++ * BCM_MWBMAP_SHIFT_OP:  Used in MOD, DIV and MUL operations.
++ * BCM_MWBMAP_INVALID_IDX: Value ~0U is treated as an invalid ID
++ *
++ * Design Notes:
++ * BCM_MWBMAP_USE_CNTSETBITS trades CPU for memory. A runtime count of how many
++ * bits are computed each time on allocation and deallocation, requiring 4
++ * array indexed access and 3 arithmetic operations. When not defined, a runtime
++ * count of set bits state is maintained. Upto 32 Bytes per 1024 IDs is needed.
++ * In a 4K max ID allocator, up to 128Bytes are hence used per instantiation.
++ * In a memory limited system e.g. dongle builds, a CPU for memory tradeoff may
++ * be used by defining BCM_MWBMAP_USE_CNTSETBITS.
++ *
++ * Note: wd_bitmap[] is statically declared and is not ROM friendly ... array
++ * size is fixed. No intention to support larger than 4K indice allocation. ID
++ * allocators for ranges smaller than 4K will have a wastage of only 12Bytes
++ * with savings in not having to use an indirect access, had it been dynamically
++ * allocated.
++ */
++#define BCM_MWBMAP_ITEMS_MAX    (64 * 1024)  /* May increase to 64K */
++
++#define BCM_MWBMAP_BITS_WORD    (NBITS(uint32))
++#define BCM_MWBMAP_WORDS_MAX    (BCM_MWBMAP_ITEMS_MAX / BCM_MWBMAP_BITS_WORD)
++#define BCM_MWBMAP_WDMAP_MAX    (BCM_MWBMAP_WORDS_MAX / BCM_MWBMAP_BITS_WORD)
++#define BCM_MWBMAP_SHIFT_OP     (5)
++#define BCM_MWBMAP_MODOP(ix)    ((ix) & (BCM_MWBMAP_BITS_WORD - 1))
++#define BCM_MWBMAP_DIVOP(ix)    ((ix) >> BCM_MWBMAP_SHIFT_OP)
++#define BCM_MWBMAP_MULOP(ix)    ((ix) << BCM_MWBMAP_SHIFT_OP)
++
++/* Redefine PTR() and/or HDL() conversion to invoke audit for debugging */
++#define BCM_MWBMAP_PTR(hdl)		((struct bcm_mwbmap *)(hdl))
++#define BCM_MWBMAP_HDL(ptr)		((void *)(ptr))
++
++#if defined(BCM_MWBMAP_DEBUG)
++#define BCM_MWBMAP_AUDIT(mwb) \
++	do { \
++		ASSERT((mwb != NULL) && \
++		       (((struct bcm_mwbmap *)(mwb))->magic == (void *)(mwb))); \
++		bcm_mwbmap_audit(mwb); \
++	} while (0)
++#define MWBMAP_ASSERT(exp)		ASSERT(exp)
++#define MWBMAP_DBG(x)           printf x
++#else   /* !BCM_MWBMAP_DEBUG */
++#define BCM_MWBMAP_AUDIT(mwb)   do {} while (0)
++#define MWBMAP_ASSERT(exp)		do {} while (0)
++#define MWBMAP_DBG(x)
++#endif  /* !BCM_MWBMAP_DEBUG */
++
++
++typedef struct bcm_mwbmap {     /* Hierarchical multiword bitmap allocator    */
++	uint16 wmaps;               /* Total number of words in free wd bitmap    */
++	uint16 imaps;               /* Total number of words in free id bitmap    */
++	int32  ifree;               /* Count of free indices. Used only in audits */
++	uint16 total;               /* Total indices managed by multiword bitmap  */
++
++	void * magic;               /* Audit handle parameter from user           */
++
++	uint32 wd_bitmap[BCM_MWBMAP_WDMAP_MAX]; /* 1st level bitmap of            */
++#if !defined(BCM_MWBMAP_USE_CNTSETBITS)
++	int8   wd_count[BCM_MWBMAP_WORDS_MAX];  /* free id running count, 1st lvl */
++#endif /*  ! BCM_MWBMAP_USE_CNTSETBITS */
++
++	uint32 id_bitmap[0];        /* Second level bitmap                        */
++} bcm_mwbmap_t;
++
++/* Incarnate a hierarchical multiword bitmap based small index allocator. */
++struct bcm_mwbmap *
++bcm_mwbmap_init(osl_t *osh, uint32 items_max)
++{
++	struct bcm_mwbmap * mwbmap_p;
++	uint32 wordix, size, words, extra;
++
++	/* Implementation Constraint: Uses 32bit word bitmap */
++	MWBMAP_ASSERT(BCM_MWBMAP_BITS_WORD == 32U);
++	MWBMAP_ASSERT(BCM_MWBMAP_SHIFT_OP == 5U);
++	MWBMAP_ASSERT(ISPOWEROF2(BCM_MWBMAP_ITEMS_MAX));
++	MWBMAP_ASSERT((BCM_MWBMAP_ITEMS_MAX % BCM_MWBMAP_BITS_WORD) == 0U);
++
++	ASSERT(items_max <= BCM_MWBMAP_ITEMS_MAX);
++
++	/* Determine the number of words needed in the multiword bitmap */
++	extra = BCM_MWBMAP_MODOP(items_max);
++	words = BCM_MWBMAP_DIVOP(items_max) + ((extra != 0U) ? 1U : 0U);
++
++	/* Allocate runtime state of multiword bitmap */
++	/* Note: wd_count[] or wd_bitmap[] are not dynamically allocated */
++	size = sizeof(bcm_mwbmap_t) + (sizeof(uint32) * words);
++	mwbmap_p = (bcm_mwbmap_t *)MALLOC(osh, size);
++	if (mwbmap_p == (bcm_mwbmap_t *)NULL) {
++		ASSERT(0);
++		goto error1;
++	}
++	memset(mwbmap_p, 0, size);
++
++	/* Initialize runtime multiword bitmap state */
++	mwbmap_p->imaps = (uint16)words;
++	mwbmap_p->ifree = (int32)items_max;
++	mwbmap_p->total = (uint16)items_max;
++
++	/* Setup magic, for use in audit of handle */
++	mwbmap_p->magic = BCM_MWBMAP_HDL(mwbmap_p);
++
++	/* Setup the second level bitmap of free indices */
++	/* Mark all indices as available */
++	for (wordix = 0U; wordix < mwbmap_p->imaps; wordix++) {
++		mwbmap_p->id_bitmap[wordix] = (uint32)(~0U);
++#if !defined(BCM_MWBMAP_USE_CNTSETBITS)
++		mwbmap_p->wd_count[wordix] = BCM_MWBMAP_BITS_WORD;
++#endif /*  ! BCM_MWBMAP_USE_CNTSETBITS */
++	}
++
++	/* Ensure that extra indices are tagged as un-available */
++	if (extra) { /* fixup the free ids in last bitmap and wd_count */
++		uint32 * bmap_p = &mwbmap_p->id_bitmap[mwbmap_p->imaps - 1];
++		*bmap_p ^= (uint32)(~0U << extra); /* fixup bitmap */
++#if !defined(BCM_MWBMAP_USE_CNTSETBITS)
++		mwbmap_p->wd_count[mwbmap_p->imaps - 1] = (int8)extra; /* fixup count */
++#endif /*  ! BCM_MWBMAP_USE_CNTSETBITS */
++	}
++
++	/* Setup the first level bitmap hierarchy */
++	extra = BCM_MWBMAP_MODOP(mwbmap_p->imaps);
++	words = BCM_MWBMAP_DIVOP(mwbmap_p->imaps) + ((extra != 0U) ? 1U : 0U);
++
++	mwbmap_p->wmaps = (uint16)words;
++
++	for (wordix = 0U; wordix < mwbmap_p->wmaps; wordix++)
++		mwbmap_p->wd_bitmap[wordix] = (uint32)(~0U);
++	if (extra) {
++		uint32 * bmap_p = &mwbmap_p->wd_bitmap[mwbmap_p->wmaps - 1];
++		*bmap_p ^= (uint32)(~0U << extra); /* fixup bitmap */
++	}
++
++	return mwbmap_p;
++
++error1:
++	return BCM_MWBMAP_INVALID_HDL;
++}
++
++/* Release resources used by multiword bitmap based small index allocator. */
++void
++bcm_mwbmap_fini(osl_t * osh, struct bcm_mwbmap * mwbmap_hdl)
++{
++	bcm_mwbmap_t * mwbmap_p;
++
++	BCM_MWBMAP_AUDIT(mwbmap_hdl);
++	mwbmap_p = BCM_MWBMAP_PTR(mwbmap_hdl);
++
++	MFREE(osh, mwbmap_p, sizeof(struct bcm_mwbmap)
++	                     + (sizeof(uint32) * mwbmap_p->imaps));
++	return;
++}
++
++/* Allocate a unique small index using a multiword bitmap index allocator.    */
++uint32 BCMFASTPATH
++bcm_mwbmap_alloc(struct bcm_mwbmap * mwbmap_hdl)
++{
++	bcm_mwbmap_t * mwbmap_p;
++	uint32 wordix, bitmap;
++
++	BCM_MWBMAP_AUDIT(mwbmap_hdl);
++	mwbmap_p = BCM_MWBMAP_PTR(mwbmap_hdl);
++
++	/* Start with the first hierarchy */
++	for (wordix = 0; wordix < mwbmap_p->wmaps; ++wordix) {
++
++		bitmap = mwbmap_p->wd_bitmap[wordix]; /* get the word bitmap */
++
++		if (bitmap != 0U) {
++
++			uint32 count, bitix, *bitmap_p;
++
++			bitmap_p = &mwbmap_p->wd_bitmap[wordix];
++
++			/* clear all except trailing 1 */
++			bitmap   = (uint32)(((int)(bitmap)) & (-((int)(bitmap))));
++			MWBMAP_ASSERT(C_bcm_count_leading_zeros(bitmap) ==
++			              bcm_count_leading_zeros(bitmap));
++			bitix    = (BCM_MWBMAP_BITS_WORD - 1)
++			         - bcm_count_leading_zeros(bitmap); /* use asm clz */
++			wordix   = BCM_MWBMAP_MULOP(wordix) + bitix;
++
++			/* Clear bit if wd count is 0, without conditional branch */
++#if defined(BCM_MWBMAP_USE_CNTSETBITS)
++			count = bcm_cntsetbits(mwbmap_p->id_bitmap[wordix]) - 1;
++#else  /* ! BCM_MWBMAP_USE_CNTSETBITS */
++			mwbmap_p->wd_count[wordix]--;
++			count = mwbmap_p->wd_count[wordix];
++			MWBMAP_ASSERT(count ==
++			              (bcm_cntsetbits(mwbmap_p->id_bitmap[wordix]) - 1));
++#endif /* ! BCM_MWBMAP_USE_CNTSETBITS */
++			MWBMAP_ASSERT(count >= 0);
++
++			/* clear wd_bitmap bit if id_map count is 0 */
++			bitmap = (count == 0) << bitix;
++
++			MWBMAP_DBG((
++			    "Lvl1: bitix<%02u> wordix<%02u>: %08x ^ %08x = %08x wfree %d",
++			    bitix, wordix, *bitmap_p, bitmap, (*bitmap_p) ^ bitmap, count));
++
++			*bitmap_p ^= bitmap;
++
++			/* Use bitix in the second hierarchy */
++			bitmap_p = &mwbmap_p->id_bitmap[wordix];
++
++			bitmap = mwbmap_p->id_bitmap[wordix]; /* get the id bitmap */
++			MWBMAP_ASSERT(bitmap != 0U);
++
++			/* clear all except trailing 1 */
++			bitmap   = (uint32)(((int)(bitmap)) & (-((int)(bitmap))));
++			MWBMAP_ASSERT(C_bcm_count_leading_zeros(bitmap) ==
++			              bcm_count_leading_zeros(bitmap));
++			bitix    = BCM_MWBMAP_MULOP(wordix)
++			         + (BCM_MWBMAP_BITS_WORD - 1)
++			         - bcm_count_leading_zeros(bitmap); /* use asm clz */
++
++			mwbmap_p->ifree--; /* decrement system wide free count */
++			MWBMAP_ASSERT(mwbmap_p->ifree >= 0);
++
++			MWBMAP_DBG((
++			    "Lvl2: bitix<%02u> wordix<%02u>: %08x ^ %08x = %08x ifree %d",
++			    bitix, wordix, *bitmap_p, bitmap, (*bitmap_p) ^ bitmap,
++			    mwbmap_p->ifree));
++
++			*bitmap_p ^= bitmap; /* mark as allocated = 1b0 */
++
++			return bitix;
++		}
++	}
++
++	ASSERT(mwbmap_p->ifree == 0);
++
++	return BCM_MWBMAP_INVALID_IDX;
++}
++
++/* Force an index at a specified position to be in use */
++void
++bcm_mwbmap_force(struct bcm_mwbmap * mwbmap_hdl, uint32 bitix)
++{
++	bcm_mwbmap_t * mwbmap_p;
++	uint32 count, wordix, bitmap, *bitmap_p;
++
++	BCM_MWBMAP_AUDIT(mwbmap_hdl);
++	mwbmap_p = BCM_MWBMAP_PTR(mwbmap_hdl);
++
++	ASSERT(bitix < mwbmap_p->total);
++
++	/* Start with second hierarchy */
++	wordix   = BCM_MWBMAP_DIVOP(bitix);
++	bitmap   = (uint32)(1U << BCM_MWBMAP_MODOP(bitix));
++	bitmap_p = &mwbmap_p->id_bitmap[wordix];
++
++	ASSERT((*bitmap_p & bitmap) == bitmap);
++
++	mwbmap_p->ifree--; /* update free count */
++	ASSERT(mwbmap_p->ifree >= 0);
++
++	MWBMAP_DBG(("Lvl2: bitix<%u> wordix<%u>: %08x ^ %08x = %08x ifree %d",
++	           bitix, wordix, *bitmap_p, bitmap, (*bitmap_p) ^ bitmap,
++	           mwbmap_p->ifree));
++
++	*bitmap_p ^= bitmap; /* mark as in use */
++
++	/* Update first hierarchy */
++	bitix    = wordix;
++
++	wordix   = BCM_MWBMAP_DIVOP(bitix);
++	bitmap_p = &mwbmap_p->wd_bitmap[wordix];
++
++#if defined(BCM_MWBMAP_USE_CNTSETBITS)
++	count = bcm_cntsetbits(mwbmap_p->id_bitmap[bitix]);
++#else  /* ! BCM_MWBMAP_USE_CNTSETBITS */
++	mwbmap_p->wd_count[bitix]--;
++	count = mwbmap_p->wd_count[bitix];
++	MWBMAP_ASSERT(count == bcm_cntsetbits(mwbmap_p->id_bitmap[bitix]));
++#endif /* ! BCM_MWBMAP_USE_CNTSETBITS */
++	MWBMAP_ASSERT(count >= 0);
++
++	bitmap   = (count == 0) << BCM_MWBMAP_MODOP(bitix);
++
++	MWBMAP_DBG(("Lvl1: bitix<%02lu> wordix<%02u>: %08x ^ %08x = %08x wfree %d",
++	           BCM_MWBMAP_MODOP(bitix), wordix, *bitmap_p, bitmap,
++	           (*bitmap_p) ^ bitmap, count));
++
++	*bitmap_p ^= bitmap; /* mark as in use */
++
++	return;
++}
++
++/* Free a previously allocated index back into the multiword bitmap allocator */
++void BCMFASTPATH
++bcm_mwbmap_free(struct bcm_mwbmap * mwbmap_hdl, uint32 bitix)
++{
++	bcm_mwbmap_t * mwbmap_p;
++	uint32 wordix, bitmap, *bitmap_p;
++
++	BCM_MWBMAP_AUDIT(mwbmap_hdl);
++	mwbmap_p = BCM_MWBMAP_PTR(mwbmap_hdl);
++
++	ASSERT(bitix < mwbmap_p->total);
++
++	/* Start with second level hierarchy */
++	wordix   = BCM_MWBMAP_DIVOP(bitix);
++	bitmap   = (1U << BCM_MWBMAP_MODOP(bitix));
++	bitmap_p = &mwbmap_p->id_bitmap[wordix];
++
++	ASSERT((*bitmap_p & bitmap) == 0U);	/* ASSERT not a double free */
++
++	mwbmap_p->ifree++; /* update free count */
++	ASSERT(mwbmap_p->ifree <= mwbmap_p->total);
++
++	MWBMAP_DBG(("Lvl2: bitix<%02u> wordix<%02u>: %08x | %08x = %08x ifree %d",
++	           bitix, wordix, *bitmap_p, bitmap, (*bitmap_p) | bitmap,
++	           mwbmap_p->ifree));
++
++	*bitmap_p |= bitmap; /* mark as available */
++
++	/* Now update first level hierarchy */
++
++	bitix    = wordix;
++
++	wordix   = BCM_MWBMAP_DIVOP(bitix); /* first level's word index */
++	bitmap   = (1U << BCM_MWBMAP_MODOP(bitix));
++	bitmap_p = &mwbmap_p->wd_bitmap[wordix];
++
++#if !defined(BCM_MWBMAP_USE_CNTSETBITS)
++	mwbmap_p->wd_count[bitix]++;
++#endif
++
++#if defined(BCM_MWBMAP_DEBUG)
++	{
++		uint32 count;
++#if defined(BCM_MWBMAP_USE_CNTSETBITS)
++		count = bcm_cntsetbits(mwbmap_p->id_bitmap[bitix]);
++#else  /*  ! BCM_MWBMAP_USE_CNTSETBITS */
++		count = mwbmap_p->wd_count[bitix];
++		MWBMAP_ASSERT(count == bcm_cntsetbits(mwbmap_p->id_bitmap[bitix]));
++#endif /*  ! BCM_MWBMAP_USE_CNTSETBITS */
++
++		MWBMAP_ASSERT(count <= BCM_MWBMAP_BITS_WORD);
++
++		MWBMAP_DBG(("Lvl1: bitix<%02u> wordix<%02u>: %08x | %08x = %08x wfree %d",
++		            bitix, wordix, *bitmap_p, bitmap, (*bitmap_p) | bitmap, count));
++	}
++#endif /* BCM_MWBMAP_DEBUG */
++
++	*bitmap_p |= bitmap;
++
++	return;
++}
++
++/* Fetch the toal number of free indices in the multiword bitmap allocator */
++uint32
++bcm_mwbmap_free_cnt(struct bcm_mwbmap * mwbmap_hdl)
++{
++	bcm_mwbmap_t * mwbmap_p;
++
++	BCM_MWBMAP_AUDIT(mwbmap_hdl);
++	mwbmap_p = BCM_MWBMAP_PTR(mwbmap_hdl);
++
++	ASSERT(mwbmap_p->ifree >= 0);
++
++	return mwbmap_p->ifree;
++}
++
++/* Determine whether an index is inuse or free */
++bool
++bcm_mwbmap_isfree(struct bcm_mwbmap * mwbmap_hdl, uint32 bitix)
++{
++	bcm_mwbmap_t * mwbmap_p;
++	uint32 wordix, bitmap;
++
++	BCM_MWBMAP_AUDIT(mwbmap_hdl);
++	mwbmap_p = BCM_MWBMAP_PTR(mwbmap_hdl);
++
++	ASSERT(bitix < mwbmap_p->total);
++
++	wordix   = BCM_MWBMAP_DIVOP(bitix);
++	bitmap   = (1U << BCM_MWBMAP_MODOP(bitix));
++
++	return ((mwbmap_p->id_bitmap[wordix] & bitmap) != 0U);
++}
++
++/* Debug dump a multiword bitmap allocator */
++void
++bcm_mwbmap_show(struct bcm_mwbmap * mwbmap_hdl)
++{
++	uint32 ix, count;
++	bcm_mwbmap_t * mwbmap_p;
++
++	BCM_MWBMAP_AUDIT(mwbmap_hdl);
++	mwbmap_p = BCM_MWBMAP_PTR(mwbmap_hdl);
++
++	printf("mwbmap_p %p wmaps %u imaps %u ifree %d total %u\n", mwbmap_p,
++	       mwbmap_p->wmaps, mwbmap_p->imaps, mwbmap_p->ifree, mwbmap_p->total);
++	for (ix = 0U; ix < mwbmap_p->wmaps; ix++) {
++		printf("\tWDMAP:%2u. 0x%08x\t", ix, mwbmap_p->wd_bitmap[ix]);
++		bcm_bitprint32(mwbmap_p->wd_bitmap[ix]);
++		printf("\n");
++	}
++	for (ix = 0U; ix < mwbmap_p->imaps; ix++) {
++#if defined(BCM_MWBMAP_USE_CNTSETBITS)
++		count = bcm_cntsetbits(mwbmap_p->id_bitmap[ix]);
++#else  /* ! BCM_MWBMAP_USE_CNTSETBITS */
++		count = mwbmap_p->wd_count[ix];
++		MWBMAP_ASSERT(count == bcm_cntsetbits(mwbmap_p->id_bitmap[ix]));
++#endif /* ! BCM_MWBMAP_USE_CNTSETBITS */
++		printf("\tIDMAP:%2u. 0x%08x %02u\t", ix, mwbmap_p->id_bitmap[ix], count);
++		bcm_bitprint32(mwbmap_p->id_bitmap[ix]);
++		printf("\n");
++	}
++
++	return;
++}
++
++/* Audit a hierarchical multiword bitmap */
++void
++bcm_mwbmap_audit(struct bcm_mwbmap * mwbmap_hdl)
++{
++	bcm_mwbmap_t * mwbmap_p;
++	uint32 count, free_cnt = 0U, wordix, idmap_ix, bitix, *bitmap_p;
++
++	mwbmap_p = BCM_MWBMAP_PTR(mwbmap_hdl);
++
++	for (wordix = 0U; wordix < mwbmap_p->wmaps; ++wordix) {
++
++		bitmap_p = &mwbmap_p->wd_bitmap[wordix];
++
++		for (bitix = 0U; bitix < BCM_MWBMAP_BITS_WORD; bitix++) {
++			if ((*bitmap_p) & (1 << bitix)) {
++				idmap_ix = BCM_MWBMAP_MULOP(wordix) + bitix;
++#if defined(BCM_MWBMAP_USE_CNTSETBITS)
++				count = bcm_cntsetbits(mwbmap_p->id_bitmap[idmap_ix]);
++#else  /* ! BCM_MWBMAP_USE_CNTSETBITS */
++				count = mwbmap_p->wd_count[idmap_ix];
++				ASSERT(count == bcm_cntsetbits(mwbmap_p->id_bitmap[idmap_ix]));
++#endif /* ! BCM_MWBMAP_USE_CNTSETBITS */
++				ASSERT(count != 0U);
++				free_cnt += count;
++			}
++		}
++	}
++
++	ASSERT((int)free_cnt == mwbmap_p->ifree);
++}
++/* END : Multiword bitmap based 64bit to Unique 32bit Id allocator. */
++
++/* Simple 16bit Id allocator using a stack implementation. */
++typedef struct id16_map {
++	uint32  failures;  /* count of failures */
++	void    *dbg;      /* debug placeholder */
++	uint16  total;     /* total number of ids managed by allocator */
++	uint16  start;     /* start value of 16bit ids to be managed */
++	int     stack_idx; /* index into stack of available ids */
++	uint16  stack[0];  /* stack of 16 bit ids */
++} id16_map_t;
++
++#define ID16_MAP_SZ(items)      (sizeof(id16_map_t) + \
++	                             (sizeof(uint16) * (items)))
++
++#if defined(BCM_DBG)
++
++/* Uncomment BCM_DBG_ID16 to debug double free */
++/* #define BCM_DBG_ID16 */
++
++typedef struct id16_map_dbg {
++	uint16  total;
++	bool    avail[0];
++} id16_map_dbg_t;
++#define ID16_MAP_DBG_SZ(items)  (sizeof(id16_map_dbg_t) + \
++	                             (sizeof(bool) * (items)))
++#define ID16_MAP_MSG(x)         print x
++#else
++#define ID16_MAP_MSG(x)
++#endif /* BCM_DBG */
++
++void * /* Construct an id16 allocator: [start_val16 .. start_val16+total_ids) */
++id16_map_init(osl_t *osh, uint16 total_ids, uint16 start_val16)
++{
++	uint16 idx, val16;
++	id16_map_t * id16_map;
++
++	ASSERT(total_ids > 0);
++
++	/* A start_val16 of ID16_UNDEFINED, allows the caller to fill the id16 map
++	 * with random values.
++	 */
++	ASSERT((start_val16 == ID16_UNDEFINED) ||
++	       (start_val16 + total_ids) < ID16_INVALID);
++
++	id16_map = (id16_map_t *) MALLOC(osh, ID16_MAP_SZ(total_ids));
++	if (id16_map == NULL) {
++		return NULL;
++	}
++
++	id16_map->total = total_ids;
++	id16_map->start = start_val16;
++	id16_map->failures = 0;
++	id16_map->dbg = NULL;
++
++	/*
++	 * Populate stack with 16bit id values, commencing with start_val16.
++	 * if start_val16 is ID16_UNDEFINED, then do not populate the id16 map.
++	 */
++	id16_map->stack_idx = -1;
++
++	if (id16_map->start != ID16_UNDEFINED) {
++		val16 = start_val16;
++
++		for (idx = 0; idx < total_ids; idx++, val16++) {
++			id16_map->stack_idx = idx;
++			id16_map->stack[id16_map->stack_idx] = val16;
++		}
++	}
++
++#if defined(BCM_DBG) && defined(BCM_DBG_ID16)
++	if (id16_map->start != ID16_UNDEFINED) {
++		id16_map->dbg = MALLOC(osh, ID16_MAP_DBG_SZ(total_ids));
++
++		if (id16_map->dbg) {
++			id16_map_dbg_t *id16_map_dbg = (id16_map_dbg_t *)id16_map->dbg;
++
++			id16_map_dbg->total = total_ids;
++			for (idx = 0; idx < total_ids; idx++) {
++				id16_map_dbg->avail[idx] = TRUE;
++			}
++		}
++	}
++#endif /* BCM_DBG && BCM_DBG_ID16 */
++
++	return (void *)id16_map;
++}
++
++void * /* Destruct an id16 allocator instance */
++id16_map_fini(osl_t *osh, void * id16_map_hndl)
++{
++	uint16 total_ids;
++	id16_map_t * id16_map;
++
++	if (id16_map_hndl == NULL)
++		return NULL;
++
++	id16_map = (id16_map_t *)id16_map_hndl;
++
++	total_ids = id16_map->total;
++	ASSERT(total_ids > 0);
++
++#if defined(BCM_DBG) && defined(BCM_DBG_ID16)
++	if (id16_map->dbg) {
++		MFREE(osh, id16_map->dbg, ID16_MAP_DBG_SZ(total_ids));
++		id16_map->dbg = NULL;
++	}
++#endif /* BCM_DBG && BCM_DBG_ID16 */
++
++	id16_map->total = 0;
++	MFREE(osh, id16_map, ID16_MAP_SZ(total_ids));
++
++	return NULL;
++}
++
++void
++id16_map_clear(void * id16_map_hndl, uint16 total_ids, uint16 start_val16)
++{
++	uint16 idx, val16;
++	id16_map_t * id16_map;
++
++	ASSERT(total_ids > 0);
++	/* A start_val16 of ID16_UNDEFINED, allows the caller to fill the id16 map
++	 * with random values.
++	 */
++	ASSERT((start_val16 == ID16_UNDEFINED) ||
++	       (start_val16 + total_ids) < ID16_INVALID);
++
++	id16_map = (id16_map_t *)id16_map_hndl;
++	if (id16_map == NULL) {
++		return;
++	}
++
++	id16_map->total = total_ids;
++	id16_map->start = start_val16;
++	id16_map->failures = 0;
++
++	/* Populate stack with 16bit id values, commencing with start_val16 */
++	id16_map->stack_idx = -1;
++
++	if (id16_map->start != ID16_UNDEFINED) {
++		val16 = start_val16;
++
++		for (idx = 0; idx < total_ids; idx++, val16++) {
++			id16_map->stack_idx = idx;
++			id16_map->stack[id16_map->stack_idx] = val16;
++		}
++	}
++
++#if defined(BCM_DBG) && defined(BCM_DBG_ID16)
++	if (id16_map->start != ID16_UNDEFINED) {
++		if (id16_map->dbg) {
++			id16_map_dbg_t *id16_map_dbg = (id16_map_dbg_t *)id16_map->dbg;
++
++			id16_map_dbg->total = total_ids;
++			for (idx = 0; idx < total_ids; idx++) {
++				id16_map_dbg->avail[idx] = TRUE;
++			}
++		}
++	}
++#endif /* BCM_DBG && BCM_DBG_ID16 */
++}
++
++uint16 BCMFASTPATH /* Allocate a unique 16bit id */
++id16_map_alloc(void * id16_map_hndl)
++{
++	uint16 val16;
++	id16_map_t * id16_map;
++
++	ASSERT(id16_map_hndl != NULL);
++
++	id16_map = (id16_map_t *)id16_map_hndl;
++
++	ASSERT(id16_map->total > 0);
++
++	if (id16_map->stack_idx < 0) {
++		id16_map->failures++;
++		return ID16_INVALID;
++	}
++
++	val16 = id16_map->stack[id16_map->stack_idx];
++	id16_map->stack_idx--;
++
++#if defined(BCM_DBG) && defined(BCM_DBG_ID16)
++	ASSERT((id16_map->start == ID16_UNDEFINED) ||
++	       (val16 < (id16_map->start + id16_map->total)));
++
++	if (id16_map->dbg) { /* Validate val16 */
++		id16_map_dbg_t *id16_map_dbg = (id16_map_dbg_t *)id16_map->dbg;
++
++		ASSERT(id16_map_dbg->avail[val16 - id16_map->start] == TRUE);
++		id16_map_dbg->avail[val16 - id16_map->start] = FALSE;
++	}
++#endif /* BCM_DBG && BCM_DBG_ID16 */
++
++	return val16;
++}
++
++
++void BCMFASTPATH /* Free a 16bit id value into the id16 allocator */
++id16_map_free(void * id16_map_hndl, uint16 val16)
++{
++	id16_map_t * id16_map;
++
++	ASSERT(id16_map_hndl != NULL);
++
++	id16_map = (id16_map_t *)id16_map_hndl;
++
++#if defined(BCM_DBG) && defined(BCM_DBG_ID16)
++	ASSERT((id16_map->start == ID16_UNDEFINED) ||
++	       (val16 < (id16_map->start + id16_map->total)));
++
++	if (id16_map->dbg) { /* Validate val16 */
++		id16_map_dbg_t *id16_map_dbg = (id16_map_dbg_t *)id16_map->dbg;
++
++		ASSERT(id16_map_dbg->avail[val16 - id16_map->start] == FALSE);
++		id16_map_dbg->avail[val16 - id16_map->start] = TRUE;
++	}
++#endif /* BCM_DBG && BCM_DBG_ID16 */
++
++	id16_map->stack_idx++;
++	id16_map->stack[id16_map->stack_idx] = val16;
++}
++
++uint32 /* Returns number of failures to allocate an unique id16 */
++id16_map_failures(void * id16_map_hndl)
++{
++	ASSERT(id16_map_hndl != NULL);
++	return ((id16_map_t *)id16_map_hndl)->failures;
++}
++
++bool
++id16_map_audit(void * id16_map_hndl)
++{
++	int idx;
++	int insane = 0;
++	id16_map_t * id16_map;
++
++	ASSERT(id16_map_hndl != NULL);
++
++	id16_map = (id16_map_t *)id16_map_hndl;
++
++	ASSERT(id16_map->stack_idx >= -1);
++	ASSERT(id16_map->stack_idx < (int)id16_map->total);
++
++	if (id16_map->start == ID16_UNDEFINED)
++		goto done;
++
++	for (idx = 0; idx <= id16_map->stack_idx; idx++) {
++		ASSERT(id16_map->stack[idx] >= id16_map->start);
++		ASSERT(id16_map->stack[idx] < (id16_map->start + id16_map->total));
++
++#if defined(BCM_DBG) && defined(BCM_DBG_ID16)
++		if (id16_map->dbg) {
++			uint16 val16 = id16_map->stack[idx];
++			if (((id16_map_dbg_t *)(id16_map->dbg))->avail[val16] != TRUE) {
++				insane |= 1;
++				ID16_MAP_MSG(("id16_map<%p>: stack_idx %u invalid val16 %u\n",
++					id16_map_hndl, idx, val16));
++			}
++		}
++#endif /* BCM_DBG && BCM_DBG_ID16 */
++	}
++
++#if defined(BCM_DBG) && defined(BCM_DBG_ID16)
++	if (id16_map->dbg) {
++		uint16 avail = 0; /* Audit available ids counts */
++		for (idx = 0; idx < id16_map_dbg->total; idx++) {
++			if (((id16_map_dbg_t *)(id16_map->dbg))->avail[idx16] == TRUE)
++				avail++;
++		}
++		if (avail && (avail != (id16_map->stack_idx + 1))) {
++			insane |= 1;
++			ID16_MAP_MSG(("id16_map<%p>: avail %u stack_idx %u\n",
++				id16_map_hndl, avail, id16_map->stack_idx));
++		}
++	}
++#endif /* BCM_DBG && BCM_DBG_ID16 */
++
++done:
++	/* invoke any other system audits */
++	return (!!insane);
++}
++/* END: Simple id16 allocator */
++
++
++#endif 
++
++/* calculate a >> b; and returns only lower 32 bits */
++void
++bcm_uint64_right_shift(uint32* r, uint32 a_high, uint32 a_low, uint32 b)
++{
++	uint32 a1 = a_high, a0 = a_low, r0 = 0;
++
++	if (b == 0) {
++		r0 = a_low;
++		*r = r0;
++		return;
++	}
++
++	if (b < 32) {
++		a0 = a0 >> b;
++		a1 = a1 & ((1 << b) - 1);
++		a1 = a1 << (32 - b);
++		r0 = a0 | a1;
++		*r = r0;
++		return;
++	} else {
++		r0 = a1 >> (b - 32);
++		*r = r0;
++		return;
++	}
++
++}
++
++/* calculate a + b where a is a 64 bit number and b is a 32 bit number */
++void
++bcm_add_64(uint32* r_hi, uint32* r_lo, uint32 offset)
++{
++	uint32 r1_lo = *r_lo;
++	(*r_lo) += offset;
++	if (*r_lo < r1_lo)
++		(*r_hi) ++;
++}
++
++/* calculate a - b where a is a 64 bit number and b is a 32 bit number */
++void
++bcm_sub_64(uint32* r_hi, uint32* r_lo, uint32 offset)
++{
++	uint32 r1_lo = *r_lo;
++	(*r_lo) -= offset;
++	if (*r_lo > r1_lo)
++		(*r_hi) --;
++}
++
++#ifdef DEBUG_COUNTER
++#if (OSL_SYSUPTIME_SUPPORT == TRUE)
++void counter_printlog(counter_tbl_t *ctr_tbl)
++{
++	uint32 now;
++
++	if (!ctr_tbl->enabled)
++		return;
++
++	now = OSL_SYSUPTIME();
++
++	if (now - ctr_tbl->prev_log_print > ctr_tbl->log_print_interval) {
++		uint8 i = 0;
++		printf("counter_print(%s %d):", ctr_tbl->name, now - ctr_tbl->prev_log_print);
++
++		for (i = 0; i < ctr_tbl->needed_cnt; i++) {
++			printf(" %u", ctr_tbl->cnt[i]);
++		}
++		printf("\n");
++
++		ctr_tbl->prev_log_print = now;
++		bzero(ctr_tbl->cnt, CNTR_TBL_MAX * sizeof(uint));
++	}
++}
++#else
++/* OSL_SYSUPTIME is not supported so no way to get time */
++#define counter_printlog(a) do {} while (0)
++#endif /* OSL_SYSUPTIME_SUPPORT == TRUE */
++#endif /* DEBUG_COUNTER */
++
++#if defined(BCMDRIVER) && !defined(_CFEZ_)
++void
++dll_pool_detach(void * osh, dll_pool_t * pool, uint16 elems_max, uint16 elem_size)
++{
++	uint32 mem_size;
++	mem_size = sizeof(dll_pool_t) + (elems_max * elem_size);
++	if (pool)
++		MFREE(osh, pool, mem_size);
++}
++dll_pool_t *
++dll_pool_init(void * osh, uint16 elems_max, uint16 elem_size)
++{
++	uint32 mem_size, i;
++	dll_pool_t * dll_pool_p;
++	dll_t * elem_p;
++
++	ASSERT(elem_size > sizeof(dll_t));
++
++	mem_size = sizeof(dll_pool_t) + (elems_max * elem_size);
++
++	if ((dll_pool_p = (dll_pool_t *)MALLOCZ(osh, mem_size)) == NULL) {
++		printf("dll_pool_init: elems_max<%u> elem_size<%u> malloc failure\n",
++			elems_max, elem_size);
++		ASSERT(0);
++		return dll_pool_p;
++	}
++
++	dll_init(&dll_pool_p->free_list);
++	dll_pool_p->elems_max = elems_max;
++	dll_pool_p->elem_size = elem_size;
++
++	elem_p = dll_pool_p->elements;
++	for (i = 0; i < elems_max; i++) {
++		dll_append(&dll_pool_p->free_list, elem_p);
++		elem_p = (dll_t *)((uintptr)elem_p + elem_size);
++	}
++
++	dll_pool_p->free_count = elems_max;
++
++	return dll_pool_p;
++}
++
++
++void *
++dll_pool_alloc(dll_pool_t * dll_pool_p)
++{
++	dll_t * elem_p;
++
++	if (dll_pool_p->free_count == 0) {
++		ASSERT(dll_empty(&dll_pool_p->free_list));
++		return NULL;
++	}
++
++	elem_p = dll_head_p(&dll_pool_p->free_list);
++	dll_delete(elem_p);
++	dll_pool_p->free_count -= 1;
++
++	return (void *)elem_p;
++}
++
++void
++dll_pool_free(dll_pool_t * dll_pool_p, void * elem_p)
++{
++	dll_t * node_p = (dll_t *)elem_p;
++	dll_prepend(&dll_pool_p->free_list, node_p);
++	dll_pool_p->free_count += 1;
++}
++
++
++void
++dll_pool_free_tail(dll_pool_t * dll_pool_p, void * elem_p)
++{
++	dll_t * node_p = (dll_t *)elem_p;
++	dll_append(&dll_pool_p->free_list, node_p);
++	dll_pool_p->free_count += 1;
++}
++
++#endif 
++
++/* calculate partial checksum */
++static uint32
++ip_cksum_partial(uint32 sum, uint8 *val8, uint32 count)
++{
++	uint32 i;
++	uint16 *val16 = (uint16 *)val8;
++
++	ASSERT(val8 != NULL);
++	/* partial chksum calculated on 16-bit values */
++	ASSERT((count % 2) == 0);
++
++	count /= 2;
++
++	for (i = 0; i < count; i++) {
++		sum += *val16++;
++	}
++	return sum;
++}
++
++/* calculate IP checksum */
++static uint16
++ip_cksum(uint32 sum, uint8 *val8, uint32 count)
++{
++	uint16 *val16 = (uint16 *)val8;
++
++	ASSERT(val8 != NULL);
++
++	while (count > 1) {
++		sum += *val16++;
++		count -= 2;
++	}
++	/*  add left-over byte, if any */
++	if (count > 0) {
++		sum += (*(uint8 *)val16);
++	}
++
++	/*  fold 32-bit sum to 16 bits */
++	sum = (sum >> 16) + (sum & 0xffff);
++	sum += (sum >> 16);
++	return ((uint16)~sum);
++}
++
++/* calculate IPv4 header checksum
++ * - input ip points to IP header in network order
++ * - output cksum is in network order
++ */
++uint16
++ipv4_hdr_cksum(uint8 *ip, int ip_len)
++{
++	uint32 sum = 0;
++	uint8 *ptr = ip;
++
++	ASSERT(ip != NULL);
++	ASSERT(ip_len >= IPV4_MIN_HEADER_LEN);
++
++	/* partial cksum skipping the hdr_chksum field */
++	sum = ip_cksum_partial(sum, ptr, OFFSETOF(struct ipv4_hdr, hdr_chksum));
++	ptr += OFFSETOF(struct ipv4_hdr, hdr_chksum) + 2;
++
++	/* return calculated chksum */
++	return ip_cksum(sum, ptr, ip_len - OFFSETOF(struct ipv4_hdr, src_ip));
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmwifi_channels.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmwifi_channels.c
+new file mode 100644
+index 000000000..7e5539d85
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmwifi_channels.c
+@@ -0,0 +1,1291 @@
++/*
++ * Misc utility routines used by kernel or app-level.
++ * Contents are wifi-specific, used by any kernel or app-level
++ * software that might want wifi things as it grows.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmwifi_channels.c 309193 2012-01-19 00:03:57Z $
++ */
++
++#include <bcm_cfg.h>
++#include <typedefs.h>
++#include <bcmutils.h>
++
++#ifdef BCMDRIVER
++#include <osl.h>
++#define strtoul(nptr, endptr, base) bcm_strtoul((nptr), (endptr), (base))
++#define tolower(c) (bcm_isupper((c)) ? ((c) + 'a' - 'A') : (c))
++#else
++#include <stdio.h>
++#include <stdlib.h>
++#include <ctype.h>
++#ifndef ASSERT
++#define ASSERT(exp)
++#endif
++#endif /* BCMDRIVER */
++
++#include <bcmwifi_channels.h>
++
++#if defined(WIN32) && (defined(BCMDLL) || defined(WLMDLL))
++#include <bcmstdlib.h> 	/* For wl/exe/GNUmakefile.brcm_wlu and GNUmakefile.wlm_dll */
++#endif
++
++/* Definitions for D11AC capable Chanspec type */
++
++/* Chanspec ASCII representation with 802.11ac capability:
++ * [<band> 'g'] <channel> ['/'<bandwidth> [<ctl-sideband>]['/'<1st80channel>'-'<2nd80channel>]]
++ *
++ * <band>:
++ *      (optional) 2, 3, 4, 5 for 2.4GHz, 3GHz, 4GHz, and 5GHz respectively.
++ *      Default value is 2g if channel <= 14, otherwise 5g.
++ * <channel>:
++ *      channel number of the 5MHz, 10MHz, 20MHz channel,
++ *      or primary channel of 40MHz, 80MHz, 160MHz, or 80+80MHz channel.
++ * <bandwidth>:
++ *      (optional) 5, 10, 20, 40, 80, 160, or 80+80. Default value is 20.
++ * <primary-sideband>:
++ *      (only for 2.4GHz band 40MHz) U for upper sideband primary, L for lower.
++ *
++ *      For 2.4GHz band 40MHz channels, the same primary channel may be the
++ *      upper sideband for one 40MHz channel, and the lower sideband for an
++ *      overlapping 40MHz channel.  The U/L disambiguates which 40MHz channel
++ *      is being specified.
++ *
++ *      For 40MHz in the 5GHz band and all channel bandwidths greater than
++ *      40MHz, the U/L specificaion is not allowed since the channels are
++ *      non-overlapping and the primary sub-band is derived from its
++ *      position in the wide bandwidth channel.
++ *
++ * <1st80Channel>:
++ * <2nd80Channel>:
++ *      Required for 80+80, otherwise not allowed.
++ *      Specifies the center channel of the first and second 80MHz band.
++ *
++ * In its simplest form, it is a 20MHz channel number, with the implied band
++ * of 2.4GHz if channel number <= 14, and 5GHz otherwise.
++ *
++ * To allow for backward compatibility with scripts, the old form for
++ * 40MHz channels is also allowed: <channel><ctl-sideband>
++ *
++ * <channel>:
++ *	primary channel of 40MHz, channel <= 14 is 2GHz, otherwise 5GHz
++ * <ctl-sideband>:
++ * 	"U" for upper, "L" for lower (or lower case "u" "l")
++ *
++ * 5 GHz Examples:
++ *      Chanspec        BW        Center Ch  Channel Range  Primary Ch
++ *      5g8             20MHz     8          -              -
++ *      52              20MHz     52         -              -
++ *      52/40           40MHz     54         52-56          52
++ *      56/40           40MHz     54         52-56          56
++ *      52/80           80MHz     58         52-64          52
++ *      56/80           80MHz     58         52-64          56
++ *      60/80           80MHz     58         52-64          60
++ *      64/80           80MHz     58         52-64          64
++ *      52/160          160MHz    50         36-64          52
++ *      36/160          160MGz    50         36-64          36
++ *      36/80+80/42-106 80+80MHz  42,106     36-48,100-112  36
++ *
++ * 2 GHz Examples:
++ *      Chanspec        BW        Center Ch  Channel Range  Primary Ch
++ *      2g8             20MHz     8          -              -
++ *      8               20MHz     8          -              -
++ *      6               20MHz     6          -              -
++ *      6/40l           40MHz     8          6-10           6
++ *      6l              40MHz     8          6-10           6
++ *      6/40u           40MHz     4          2-6            6
++ *      6u              40MHz     4          2-6            6
++ */
++
++/* bandwidth ASCII string */
++static const char *wf_chspec_bw_str[] =
++{
++	"5",
++	"10",
++	"20",
++	"40",
++	"80",
++	"160",
++	"80+80",
++#ifdef WL11ULB
++	"2.5"
++#else /* WL11ULB */
++	"na"
++#endif /* WL11ULB */
++};
++
++static const uint8 wf_chspec_bw_mhz[] =
++{5, 10, 20, 40, 80, 160, 160};
++
++#define WF_NUM_BW \
++	(sizeof(wf_chspec_bw_mhz)/sizeof(uint8))
++
++/* 40MHz channels in 5GHz band */
++static const uint8 wf_5g_40m_chans[] =
++{38, 46, 54, 62, 102, 110, 118, 126, 134, 142, 151, 159};
++#define WF_NUM_5G_40M_CHANS \
++	(sizeof(wf_5g_40m_chans)/sizeof(uint8))
++
++/* 80MHz channels in 5GHz band */
++static const uint8 wf_5g_80m_chans[] =
++{42, 58, 106, 122, 138, 155};
++#define WF_NUM_5G_80M_CHANS \
++	(sizeof(wf_5g_80m_chans)/sizeof(uint8))
++
++/* 160MHz channels in 5GHz band */
++static const uint8 wf_5g_160m_chans[] =
++{50, 114};
++#define WF_NUM_5G_160M_CHANS \
++	(sizeof(wf_5g_160m_chans)/sizeof(uint8))
++
++
++/* convert bandwidth from chanspec to MHz */
++static uint
++bw_chspec_to_mhz(chanspec_t chspec)
++{
++	uint bw;
++
++	bw = (chspec & WL_CHANSPEC_BW_MASK) >> WL_CHANSPEC_BW_SHIFT;
++	return (bw >= WF_NUM_BW ? 0 : wf_chspec_bw_mhz[bw]);
++}
++
++/* bw in MHz, return the channel count from the center channel to the
++ * the channel at the edge of the band
++ */
++static uint8
++center_chan_to_edge(uint bw)
++{
++	/* edge channels separated by BW - 10MHz on each side
++	 * delta from cf to edge is half of that,
++	 * MHz to channel num conversion is 5MHz/channel
++	 */
++	return (uint8)(((bw - 20) / 2) / 5);
++}
++
++/* return channel number of the low edge of the band
++ * given the center channel and BW
++ */
++static uint8
++channel_low_edge(uint center_ch, uint bw)
++{
++	return (uint8)(center_ch - center_chan_to_edge(bw));
++}
++
++/* return side band number given center channel and control channel
++ * return -1 on error
++ */
++static int
++channel_to_sb(uint center_ch, uint ctl_ch, uint bw)
++{
++	uint lowest = channel_low_edge(center_ch, bw);
++	uint sb;
++
++	if ((ctl_ch - lowest) % 4) {
++		/* bad ctl channel, not mult 4 */
++		return -1;
++	}
++
++	sb = ((ctl_ch - lowest) / 4);
++
++	/* sb must be a index to a 20MHz channel in range */
++	if (sb >= (bw / 20)) {
++		/* ctl_ch must have been too high for the center_ch */
++		return -1;
++	}
++
++	return sb;
++}
++
++/* return control channel given center channel and side band */
++static uint8
++channel_to_ctl_chan(uint center_ch, uint bw, uint sb)
++{
++	return (uint8)(channel_low_edge(center_ch, bw) + sb * 4);
++}
++
++/* return index of 80MHz channel from channel number
++ * return -1 on error
++ */
++static int
++channel_80mhz_to_id(uint ch)
++{
++	uint i;
++	for (i = 0; i < WF_NUM_5G_80M_CHANS; i ++) {
++		if (ch == wf_5g_80m_chans[i])
++			return i;
++	}
++
++	return -1;
++}
++
++/* wrapper function for wf_chspec_ntoa. In case of an error it puts
++ * the original chanspec in the output buffer, prepended with "invalid".
++ * Can be directly used in print routines as it takes care of null
++ */
++char *
++wf_chspec_ntoa_ex(chanspec_t chspec, char *buf)
++{
++	if (wf_chspec_ntoa(chspec, buf) == NULL)
++		snprintf(buf, CHANSPEC_STR_LEN, "invalid 0x%04x", chspec);
++	return buf;
++}
++
++/* given a chanspec and a string buffer, format the chanspec as a
++ * string, and return the original pointer a.
++ * Min buffer length must be CHANSPEC_STR_LEN.
++ * On error return NULL
++ */
++char *
++wf_chspec_ntoa(chanspec_t chspec, char *buf)
++{
++	const char *band;
++	uint ctl_chan;
++
++	if (wf_chspec_malformed(chspec))
++		return NULL;
++
++	band = "";
++
++	/* check for non-default band spec */
++	if ((CHSPEC_IS2G(chspec) && CHSPEC_CHANNEL(chspec) > CH_MAX_2G_CHANNEL) ||
++	    (CHSPEC_IS5G(chspec) && CHSPEC_CHANNEL(chspec) <= CH_MAX_2G_CHANNEL))
++		band = (CHSPEC_IS2G(chspec)) ? "2g" : "5g";
++
++	/* ctl channel */
++	ctl_chan = wf_chspec_ctlchan(chspec);
++
++	/* bandwidth and ctl sideband */
++	if (CHSPEC_IS20(chspec)) {
++		snprintf(buf, CHANSPEC_STR_LEN, "%s%d", band, ctl_chan);
++	} else if (!CHSPEC_IS8080(chspec)) {
++		const char *bw;
++		const char *sb = "";
++
++		bw = wf_chspec_bw_str[(chspec & WL_CHANSPEC_BW_MASK) >> WL_CHANSPEC_BW_SHIFT];
++
++#ifdef CHANSPEC_NEW_40MHZ_FORMAT
++		/* ctl sideband string if needed for 2g 40MHz */
++		if (CHSPEC_IS40(chspec) && CHSPEC_IS2G(chspec)) {
++			sb = CHSPEC_SB_UPPER(chspec) ? "u" : "l";
++		}
++
++		snprintf(buf, CHANSPEC_STR_LEN, "%s%d/%s%s", band, ctl_chan, bw, sb);
++#else
++		/* ctl sideband string instead of BW for 40MHz */
++		if (CHSPEC_IS40(chspec)) {
++			sb = CHSPEC_SB_UPPER(chspec) ? "u" : "l";
++			snprintf(buf, CHANSPEC_STR_LEN, "%s%d%s", band, ctl_chan, sb);
++		} else {
++			snprintf(buf, CHANSPEC_STR_LEN, "%s%d/%s", band, ctl_chan, bw);
++		}
++#endif /* CHANSPEC_NEW_40MHZ_FORMAT */
++
++	} else {
++		/* 80+80 */
++		uint chan1 = (chspec & WL_CHANSPEC_CHAN1_MASK) >> WL_CHANSPEC_CHAN1_SHIFT;
++		uint chan2 = (chspec & WL_CHANSPEC_CHAN2_MASK) >> WL_CHANSPEC_CHAN2_SHIFT;
++
++		/* convert to channel number */
++		chan1 = (chan1 < WF_NUM_5G_80M_CHANS) ? wf_5g_80m_chans[chan1] : 0;
++		chan2 = (chan2 < WF_NUM_5G_80M_CHANS) ? wf_5g_80m_chans[chan2] : 0;
++
++		/* Outputs a max of CHANSPEC_STR_LEN chars including '\0'  */
++		snprintf(buf, CHANSPEC_STR_LEN, "%d/80+80/%d-%d", ctl_chan, chan1, chan2);
++	}
++
++	return (buf);
++}
++
++static int
++read_uint(const char **p, unsigned int *num)
++{
++	unsigned long val;
++	char *endp = NULL;
++
++	val = strtoul(*p, &endp, 10);
++	/* if endp is the initial pointer value, then a number was not read */
++	if (endp == *p)
++		return 0;
++
++	/* advance the buffer pointer to the end of the integer string */
++	*p = endp;
++	/* return the parsed integer */
++	*num = (unsigned int)val;
++
++	return 1;
++}
++
++/* given a chanspec string, convert to a chanspec.
++ * On error return 0
++ */
++chanspec_t
++wf_chspec_aton(const char *a)
++{
++	chanspec_t chspec;
++	uint chspec_ch, chspec_band, bw, chspec_bw, chspec_sb;
++	uint num, ctl_ch;
++	uint ch1, ch2;
++	char c, sb_ul = '\0';
++	int i;
++
++	bw = 20;
++	chspec_sb = 0;
++	chspec_ch = ch1 = ch2 = 0;
++
++	/* parse channel num or band */
++	if (!read_uint(&a, &num))
++		return 0;
++	/* if we are looking at a 'g', then the first number was a band */
++	c = tolower((int)a[0]);
++	if (c == 'g') {
++		a++; /* consume the char */
++
++		/* band must be "2" or "5" */
++		if (num == 2)
++			chspec_band = WL_CHANSPEC_BAND_2G;
++		else if (num == 5)
++			chspec_band = WL_CHANSPEC_BAND_5G;
++		else
++			return 0;
++
++		/* read the channel number */
++		if (!read_uint(&a, &ctl_ch))
++			return 0;
++
++		c = tolower((int)a[0]);
++	}
++	else {
++		/* first number is channel, use default for band */
++		ctl_ch = num;
++		chspec_band = ((ctl_ch <= CH_MAX_2G_CHANNEL) ?
++		               WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G);
++	}
++
++	if (c == '\0') {
++		/* default BW of 20MHz */
++		chspec_bw = WL_CHANSPEC_BW_20;
++		goto done_read;
++	}
++
++	a ++; /* consume the 'u','l', or '/' */
++
++	/* check 'u'/'l' */
++	if (c == 'u' || c == 'l') {
++		sb_ul = c;
++		chspec_bw = WL_CHANSPEC_BW_40;
++		goto done_read;
++	}
++
++	/* next letter must be '/' */
++	if (c != '/')
++		return 0;
++
++	/* read bandwidth */
++	if (!read_uint(&a, &bw))
++		return 0;
++
++	/* convert to chspec value */
++	if (bw == 2) {
++		chspec_bw = WL_CHANSPEC_BW_2P5;
++	} else if (bw == 5) {
++		chspec_bw = WL_CHANSPEC_BW_5;
++	} else if (bw == 10) {
++		chspec_bw = WL_CHANSPEC_BW_10;
++	} else if (bw == 20) {
++		chspec_bw = WL_CHANSPEC_BW_20;
++	} else if (bw == 40) {
++		chspec_bw = WL_CHANSPEC_BW_40;
++	} else if (bw == 80) {
++		chspec_bw = WL_CHANSPEC_BW_80;
++	} else if (bw == 160) {
++		chspec_bw = WL_CHANSPEC_BW_160;
++	} else {
++		return 0;
++	}
++
++	/* So far we have <band>g<chan>/<bw>
++	 * Can now be followed by u/l if bw = 40,
++	 * or '+80' if bw = 80, to make '80+80' bw,
++	 * or '.5' if bw = 2.5 to make '2.5' bw .
++	 */
++
++	c = tolower((int)a[0]);
++
++	/* if we have a 2g/40 channel, we should have a l/u spec now */
++	if (chspec_band == WL_CHANSPEC_BAND_2G && bw == 40) {
++		if (c == 'u' || c == 'l') {
++			a ++; /* consume the u/l char */
++			sb_ul = c;
++			goto done_read;
++		}
++	}
++
++	/* check for 80+80 */
++	if (c == '+') {
++		/* 80+80 */
++		const char plus80[] = "80/";
++
++		/* must be looking at '+80/'
++		 * check and consume this string.
++		 */
++		chspec_bw = WL_CHANSPEC_BW_8080;
++
++		a ++; /* consume the char '+' */
++
++		/* consume the '80/' string */
++		for (i = 0; i < 3; i++) {
++			if (*a++ != plus80[i]) {
++				return 0;
++			}
++		}
++
++		/* read primary 80MHz channel */
++		if (!read_uint(&a, &ch1))
++			return 0;
++
++		/* must followed by '-' */
++		if (a[0] != '-')
++			return 0;
++		a ++; /* consume the char */
++
++		/* read secondary 80MHz channel */
++		if (!read_uint(&a, &ch2))
++			return 0;
++	} else if (c == '.') {
++		/* 2.5 */
++		/* must be looking at '.5'
++		 * check and consume this string.
++		 */
++		chspec_bw = WL_CHANSPEC_BW_2P5;
++
++		a ++; /* consume the char '.' */
++
++		/* consume the '5' string */
++		if (*a++ != '5') {
++			return 0;
++		}
++	}
++
++done_read:
++	/* skip trailing white space */
++	while (a[0] == ' ') {
++		a ++;
++	}
++
++	/* must be end of string */
++	if (a[0] != '\0')
++		return 0;
++
++	/* Now have all the chanspec string parts read;
++	 * chspec_band, ctl_ch, chspec_bw, sb_ul, ch1, ch2.
++	 * chspec_band and chspec_bw are chanspec values.
++	 * Need to convert ctl_ch, sb_ul, and ch1,ch2 into
++	 * a center channel (or two) and sideband.
++	 */
++
++	/* if a sb u/l string was given, just use that,
++	 * guaranteed to be bw = 40 by sting parse.
++	 */
++	if (sb_ul != '\0') {
++		if (sb_ul == 'l') {
++			chspec_ch = UPPER_20_SB(ctl_ch);
++			chspec_sb = WL_CHANSPEC_CTL_SB_LLL;
++		} else if (sb_ul == 'u') {
++			chspec_ch = LOWER_20_SB(ctl_ch);
++			chspec_sb = WL_CHANSPEC_CTL_SB_LLU;
++		}
++	}
++	/* if the bw is 20, center and sideband are trivial */
++	else if (BW_LE20(chspec_bw)) {
++		chspec_ch = ctl_ch;
++		chspec_sb = WL_CHANSPEC_CTL_SB_NONE;
++	}
++	/* if the bw is 40/80/160, not 80+80, a single method
++	 * can be used to to find the center and sideband
++	 */
++	else if (chspec_bw != WL_CHANSPEC_BW_8080) {
++		/* figure out ctl sideband based on ctl channel and bandwidth */
++		const uint8 *center_ch = NULL;
++		int num_ch = 0;
++		int sb = -1;
++
++		if (chspec_bw == WL_CHANSPEC_BW_40) {
++			center_ch = wf_5g_40m_chans;
++			num_ch = WF_NUM_5G_40M_CHANS;
++		} else if (chspec_bw == WL_CHANSPEC_BW_80) {
++			center_ch = wf_5g_80m_chans;
++			num_ch = WF_NUM_5G_80M_CHANS;
++		} else if (chspec_bw == WL_CHANSPEC_BW_160) {
++			center_ch = wf_5g_160m_chans;
++			num_ch = WF_NUM_5G_160M_CHANS;
++		} else {
++			return 0;
++		}
++
++		for (i = 0; i < num_ch; i ++) {
++			sb = channel_to_sb(center_ch[i], ctl_ch, bw);
++			if (sb >= 0) {
++				chspec_ch = center_ch[i];
++				chspec_sb = sb << WL_CHANSPEC_CTL_SB_SHIFT;
++				break;
++			}
++		}
++
++		/* check for no matching sb/center */
++		if (sb < 0) {
++			return 0;
++		}
++	}
++	/* Otherwise, bw is 80+80. Figure out channel pair and sb */
++	else {
++		int ch1_id = 0, ch2_id = 0;
++		int sb;
++
++		/* look up the channel ID for the specified channel numbers */
++		ch1_id = channel_80mhz_to_id(ch1);
++		ch2_id = channel_80mhz_to_id(ch2);
++
++		/* validate channels */
++		if (ch1_id < 0 || ch2_id < 0)
++			return 0;
++
++		/* combine 2 channel IDs in channel field of chspec */
++		chspec_ch = (((uint)ch1_id << WL_CHANSPEC_CHAN1_SHIFT) |
++		             ((uint)ch2_id << WL_CHANSPEC_CHAN2_SHIFT));
++
++		/* figure out primary 20 MHz sideband */
++
++		/* is the primary channel contained in the 1st 80MHz channel? */
++		sb = channel_to_sb(ch1, ctl_ch, bw);
++		if (sb < 0) {
++			/* no match for primary channel 'ctl_ch' in segment0 80MHz channel */
++			return 0;
++		}
++
++		chspec_sb = sb << WL_CHANSPEC_CTL_SB_SHIFT;
++	}
++
++	chspec = (chspec_ch | chspec_band | chspec_bw | chspec_sb);
++
++	if (wf_chspec_malformed(chspec))
++		return 0;
++
++	return chspec;
++}
++
++/*
++ * Verify the chanspec is using a legal set of parameters, i.e. that the
++ * chanspec specified a band, bw, ctl_sb and channel and that the
++ * combination could be legal given any set of circumstances.
++ * RETURNS: TRUE is the chanspec is malformed, false if it looks good.
++ */
++bool
++wf_chspec_malformed(chanspec_t chanspec)
++{
++	uint chspec_bw = CHSPEC_BW(chanspec);
++	uint chspec_ch = CHSPEC_CHANNEL(chanspec);
++
++	/* must be 2G or 5G band */
++	if (CHSPEC_IS2G(chanspec)) {
++		/* must be valid bandwidth */
++		if (!BW_LE40(chspec_bw)) {
++			return TRUE;
++		}
++	} else if (CHSPEC_IS5G(chanspec)) {
++		if (chspec_bw == WL_CHANSPEC_BW_8080) {
++			uint ch1_id, ch2_id;
++
++			/* channel IDs in 80+80 must be in range */
++			ch1_id = CHSPEC_CHAN1(chanspec);
++			ch2_id = CHSPEC_CHAN2(chanspec);
++			if (ch1_id >= WF_NUM_5G_80M_CHANS || ch2_id >= WF_NUM_5G_80M_CHANS)
++				return TRUE;
++
++		} else if (BW_LE160(chspec_bw)) {
++			if (chspec_ch > MAXCHANNEL) {
++				return TRUE;
++			}
++		} else {
++			/* invalid bandwidth */
++			return TRUE;
++		}
++	} else {
++		/* must be 2G or 5G band */
++		return TRUE;
++	}
++
++	/* side band needs to be consistent with bandwidth */
++	if (BW_LE20(chspec_bw)) {
++		if (CHSPEC_CTL_SB(chanspec) != WL_CHANSPEC_CTL_SB_LLL)
++			return TRUE;
++	} else if (chspec_bw == WL_CHANSPEC_BW_40) {
++		if (CHSPEC_CTL_SB(chanspec) > WL_CHANSPEC_CTL_SB_LLU)
++			return TRUE;
++	} else if (chspec_bw == WL_CHANSPEC_BW_80 ||
++	           chspec_bw == WL_CHANSPEC_BW_8080) {
++		if (CHSPEC_CTL_SB(chanspec) > WL_CHANSPEC_CTL_SB_LUU)
++			return TRUE;
++	}
++	else if (chspec_bw == WL_CHANSPEC_BW_160) {
++		ASSERT(CHSPEC_CTL_SB(chanspec) <= WL_CHANSPEC_CTL_SB_UUU);
++	}
++	return FALSE;
++}
++
++/*
++ * Verify the chanspec specifies a valid channel according to 802.11.
++ * RETURNS: TRUE if the chanspec is a valid 802.11 channel
++ */
++bool
++wf_chspec_valid(chanspec_t chanspec)
++{
++	uint chspec_bw = CHSPEC_BW(chanspec);
++	uint chspec_ch = CHSPEC_CHANNEL(chanspec);
++
++	if (wf_chspec_malformed(chanspec))
++		return FALSE;
++
++	if (CHSPEC_IS2G(chanspec)) {
++		/* must be valid bandwidth and channel range */
++		if (BW_LE20(chspec_bw)) {
++			if (chspec_ch >= 1 && chspec_ch <= 14)
++				return TRUE;
++		} else if (chspec_bw == WL_CHANSPEC_BW_40) {
++			if (chspec_ch >= 3 && chspec_ch <= 11)
++				return TRUE;
++		}
++	} else if (CHSPEC_IS5G(chanspec)) {
++		if (chspec_bw == WL_CHANSPEC_BW_8080) {
++			uint16 ch1, ch2;
++
++			ch1 = wf_5g_80m_chans[CHSPEC_CHAN1(chanspec)];
++			ch2 = wf_5g_80m_chans[CHSPEC_CHAN2(chanspec)];
++
++			/* the two channels must be separated by more than 80MHz by VHT req */
++			if ((ch2 > ch1 + CH_80MHZ_APART) ||
++			    (ch1 > ch2 + CH_80MHZ_APART))
++				return TRUE;
++		} else {
++			const uint8 *center_ch;
++			uint num_ch, i;
++
++			if (BW_LE40(chspec_bw)) {
++				center_ch = wf_5g_40m_chans;
++				num_ch = WF_NUM_5G_40M_CHANS;
++			} else if (chspec_bw == WL_CHANSPEC_BW_80) {
++				center_ch = wf_5g_80m_chans;
++				num_ch = WF_NUM_5G_80M_CHANS;
++			} else if (chspec_bw == WL_CHANSPEC_BW_160) {
++				center_ch = wf_5g_160m_chans;
++				num_ch = WF_NUM_5G_160M_CHANS;
++			} else {
++				/* invalid bandwidth */
++				return FALSE;
++			}
++
++			/* check for a valid center channel */
++			if (BW_LE20(chspec_bw)) {
++				/* We don't have an array of legal 20MHz 5G channels, but they are
++				 * each side of the legal 40MHz channels.  Check the chanspec
++				 * channel against either side of the 40MHz channels.
++				 */
++				for (i = 0; i < num_ch; i ++) {
++					if (chspec_ch == (uint)LOWER_20_SB(center_ch[i]) ||
++					    chspec_ch == (uint)UPPER_20_SB(center_ch[i]))
++						break; /* match found */
++				}
++
++				if (i == num_ch) {
++					/* check for channel 165 which is not the side band
++					 * of 40MHz 5G channel
++					 */
++					if (chspec_ch == 165)
++						i = 0;
++
++					/* check for legacy JP channels on failure */
++					if (chspec_ch == 34 || chspec_ch == 38 ||
++					    chspec_ch == 42 || chspec_ch == 46)
++						i = 0;
++				}
++			} else {
++				/* check the chanspec channel to each legal channel */
++				for (i = 0; i < num_ch; i ++) {
++					if (chspec_ch == center_ch[i])
++						break; /* match found */
++				}
++			}
++
++			if (i < num_ch) {
++				/* match found */
++				return TRUE;
++			}
++		}
++	}
++
++	return FALSE;
++}
++
++/*
++ * This function returns the channel number that control traffic is being sent on, for 20MHz
++ * channels this is just the channel number, for 40MHZ, 80MHz, 160MHz channels it is the 20MHZ
++ * sideband depending on the chanspec selected
++ */
++uint8
++wf_chspec_ctlchan(chanspec_t chspec)
++{
++	uint center_chan;
++	uint bw_mhz;
++	uint sb;
++
++	ASSERT(!wf_chspec_malformed(chspec));
++
++	/* Is there a sideband ? */
++	if (CHSPEC_BW_LE20(chspec)) {
++		return CHSPEC_CHANNEL(chspec);
++	} else {
++		sb = CHSPEC_CTL_SB(chspec) >> WL_CHANSPEC_CTL_SB_SHIFT;
++
++		if (CHSPEC_IS8080(chspec)) {
++			/* For an 80+80 MHz channel, the sideband 'sb' field is an 80 MHz sideband
++			 * (LL, LU, UL, LU) for the 80 MHz frequency segment 0.
++			 */
++			uint chan_id = CHSPEC_CHAN1(chspec);
++
++			bw_mhz = 80;
++
++			/* convert from channel index to channel number */
++			center_chan = wf_5g_80m_chans[chan_id];
++		}
++		else {
++			bw_mhz = bw_chspec_to_mhz(chspec);
++			center_chan = CHSPEC_CHANNEL(chspec) >> WL_CHANSPEC_CHAN_SHIFT;
++		}
++
++		return (channel_to_ctl_chan(center_chan, bw_mhz, sb));
++	}
++}
++
++/* given a chanspec, return the bandwidth string */
++char *
++wf_chspec_to_bw_str(chanspec_t chspec)
++{
++		return (char *)wf_chspec_bw_str[(CHSPEC_BW(chspec) >> WL_CHANSPEC_BW_SHIFT)];
++}
++
++/*
++ * This function returns the chanspec of the control channel of a given chanspec
++ */
++chanspec_t
++wf_chspec_ctlchspec(chanspec_t chspec)
++{
++	chanspec_t ctl_chspec = chspec;
++	uint8 ctl_chan;
++
++	ASSERT(!wf_chspec_malformed(chspec));
++
++	/* Is there a sideband ? */
++	if (!CHSPEC_BW_LE20(chspec)) {
++		ctl_chan = wf_chspec_ctlchan(chspec);
++		ctl_chspec = ctl_chan | WL_CHANSPEC_BW_20;
++		ctl_chspec |= CHSPEC_BAND(chspec);
++	}
++	return ctl_chspec;
++}
++
++/* return chanspec given control channel and bandwidth
++ * return 0 on error
++ */
++uint16
++wf_channel2chspec(uint ctl_ch, uint bw)
++{
++	uint16 chspec;
++	const uint8 *center_ch = NULL;
++	int num_ch = 0;
++	int sb = -1;
++	int i = 0;
++
++	chspec = ((ctl_ch <= CH_MAX_2G_CHANNEL) ? WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G);
++
++	chspec |= bw;
++
++	if (bw == WL_CHANSPEC_BW_40) {
++		center_ch = wf_5g_40m_chans;
++		num_ch = WF_NUM_5G_40M_CHANS;
++		bw = 40;
++	} else if (bw == WL_CHANSPEC_BW_80) {
++		center_ch = wf_5g_80m_chans;
++		num_ch = WF_NUM_5G_80M_CHANS;
++		bw = 80;
++	} else if (bw == WL_CHANSPEC_BW_160) {
++		center_ch = wf_5g_160m_chans;
++		num_ch = WF_NUM_5G_160M_CHANS;
++		bw = 160;
++	} else if (BW_LE20(bw)) {
++		chspec |= ctl_ch;
++		return chspec;
++	} else {
++		return 0;
++	}
++
++	for (i = 0; i < num_ch; i ++) {
++		sb = channel_to_sb(center_ch[i], ctl_ch, bw);
++		if (sb >= 0) {
++			chspec |= center_ch[i];
++			chspec |= (sb << WL_CHANSPEC_CTL_SB_SHIFT);
++			break;
++		}
++	}
++
++	/* check for no matching sb/center */
++	if (sb < 0) {
++		return 0;
++	}
++
++	return chspec;
++}
++
++/*
++ * This function returns the chanspec for the primary 40MHz of an 80MHz channel.
++ * The control sideband specifies the same 20MHz channel that the 80MHz channel is using
++ * as the primary 20MHz channel.
++ */
++extern chanspec_t wf_chspec_primary40_chspec(chanspec_t chspec)
++{
++	chanspec_t chspec40 = chspec;
++	uint center_chan;
++	uint sb;
++
++	ASSERT(!wf_chspec_malformed(chspec));
++
++	/* if the chanspec is > 80MHz, use the helper routine to find the primary 80 MHz channel */
++	if (CHSPEC_IS8080(chspec) || CHSPEC_IS160(chspec)) {
++		chspec = wf_chspec_primary80_chspec(chspec);
++	}
++
++	/* determine primary 40 MHz sub-channel of an 80 MHz chanspec */
++	if (CHSPEC_IS80(chspec)) {
++		center_chan = CHSPEC_CHANNEL(chspec);
++		sb = CHSPEC_CTL_SB(chspec);
++
++		if (sb < WL_CHANSPEC_CTL_SB_UL) {
++			/* Primary 40MHz is on lower side */
++			center_chan -= CH_20MHZ_APART;
++			/* sideband bits are the same for LL/LU and L/U */
++		} else {
++			/* Primary 40MHz is on upper side */
++			center_chan += CH_20MHZ_APART;
++			/* sideband bits need to be adjusted by UL offset */
++			sb -= WL_CHANSPEC_CTL_SB_UL;
++		}
++
++		/* Create primary 40MHz chanspec */
++		chspec40 = (WL_CHANSPEC_BAND_5G | WL_CHANSPEC_BW_40 |
++		            sb | center_chan);
++	}
++
++	return chspec40;
++}
++
++/*
++ * Return the channel number for a given frequency and base frequency.
++ * The returned channel number is relative to the given base frequency.
++ * If the given base frequency is zero, a base frequency of 5 GHz is assumed for
++ * frequencies from 5 - 6 GHz, and 2.407 GHz is assumed for 2.4 - 2.5 GHz.
++ *
++ * Frequency is specified in MHz.
++ * The base frequency is specified as (start_factor * 500 kHz).
++ * Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_5_G are defined for
++ * 2.4 GHz and 5 GHz bands.
++ *
++ * The returned channel will be in the range [1, 14] in the 2.4 GHz band
++ * and [0, 200] otherwise.
++ * -1 is returned if the start_factor is WF_CHAN_FACTOR_2_4_G and the
++ * frequency is not a 2.4 GHz channel, or if the frequency is not and even
++ * multiple of 5 MHz from the base frequency to the base plus 1 GHz.
++ *
++ * Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
++ */
++int
++wf_mhz2channel(uint freq, uint start_factor)
++{
++	int ch = -1;
++	uint base;
++	int offset;
++
++	/* take the default channel start frequency */
++	if (start_factor == 0) {
++		if (freq >= 2400 && freq <= 2500)
++			start_factor = WF_CHAN_FACTOR_2_4_G;
++		else if (freq >= 5000 && freq <= 6000)
++			start_factor = WF_CHAN_FACTOR_5_G;
++	}
++
++	if (freq == 2484 && start_factor == WF_CHAN_FACTOR_2_4_G)
++		return 14;
++
++	base = start_factor / 2;
++
++	/* check that the frequency is in 1GHz range of the base */
++	if ((freq < base) || (freq > base + 1000))
++		return -1;
++
++	offset = freq - base;
++	ch = offset / 5;
++
++	/* check that frequency is a 5MHz multiple from the base */
++	if (offset != (ch * 5))
++		return -1;
++
++	/* restricted channel range check for 2.4G */
++	if (start_factor == WF_CHAN_FACTOR_2_4_G && (ch < 1 || ch > 13))
++		return -1;
++
++	return ch;
++}
++
++/*
++ * Return the center frequency in MHz of the given channel and base frequency.
++ * The channel number is interpreted relative to the given base frequency.
++ *
++ * The valid channel range is [1, 14] in the 2.4 GHz band and [0, 200] otherwise.
++ * The base frequency is specified as (start_factor * 500 kHz).
++ * Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_4_G, and WF_CHAN_FACTOR_5_G
++ * are defined for 2.4 GHz, 4 GHz, and 5 GHz bands.
++ * The channel range of [1, 14] is only checked for a start_factor of
++ * WF_CHAN_FACTOR_2_4_G (4814 = 2407 * 2).
++ * Odd start_factors produce channels on .5 MHz boundaries, in which case
++ * the answer is rounded down to an integral MHz.
++ * -1 is returned for an out of range channel.
++ *
++ * Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
++ */
++int
++wf_channel2mhz(uint ch, uint start_factor)
++{
++	int freq;
++
++	if ((start_factor == WF_CHAN_FACTOR_2_4_G && (ch < 1 || ch > 14)) ||
++	    (ch > 200))
++		freq = -1;
++	else if ((start_factor == WF_CHAN_FACTOR_2_4_G) && (ch == 14))
++		freq = 2484;
++	else
++		freq = ch * 5 + start_factor / 2;
++
++	return freq;
++}
++
++static const uint16 sidebands[] = {
++	WL_CHANSPEC_CTL_SB_LLL, WL_CHANSPEC_CTL_SB_LLU,
++	WL_CHANSPEC_CTL_SB_LUL, WL_CHANSPEC_CTL_SB_LUU,
++	WL_CHANSPEC_CTL_SB_ULL, WL_CHANSPEC_CTL_SB_ULU,
++	WL_CHANSPEC_CTL_SB_UUL, WL_CHANSPEC_CTL_SB_UUU
++};
++
++/*
++ * Returns the chanspec 80Mhz channel corresponding to the following input
++ * parameters
++ *
++ *	primary_channel - primary 20Mhz channel
++ *	center_channel   - center frequecny of the 80Mhz channel
++ *
++ * The center_channel can be one of {42, 58, 106, 122, 138, 155}
++ *
++ * returns INVCHANSPEC in case of error
++ */
++chanspec_t
++wf_chspec_80(uint8 center_channel, uint8 primary_channel)
++{
++
++	chanspec_t chanspec = INVCHANSPEC;
++	chanspec_t chanspec_cur;
++	uint i;
++
++	for (i = 0; i < WF_NUM_SIDEBANDS_80MHZ; i++) {
++		chanspec_cur = CH80MHZ_CHSPEC(center_channel, sidebands[i]);
++		if (primary_channel == wf_chspec_ctlchan(chanspec_cur)) {
++			chanspec = chanspec_cur;
++			break;
++		}
++	}
++	/* If the loop ended early, we are good, otherwise we did not
++	* find a 80MHz chanspec with the given center_channel that had a primary channel
++	*matching the given primary_channel.
++	*/
++	return chanspec;
++}
++
++/*
++ * Returns the 80+80 chanspec corresponding to the following input parameters
++ *
++ *    primary_20mhz - Primary 20 MHz channel
++ *    chan0 - center channel number of one frequency segment
++ *    chan1 - center channel number of the other frequency segment
++ *
++ * Parameters chan0 and chan1 are channel numbers in {42, 58, 106, 122, 138, 155}.
++ * The primary channel must be contained in one of the 80MHz channels. This routine
++ * will determine which frequency segment is the primary 80 MHz segment.
++ *
++ * Returns INVCHANSPEC in case of error.
++ *
++ * Refer to IEEE802.11ac section 22.3.14 "Channelization".
++ */
++chanspec_t
++wf_chspec_get8080_chspec(uint8 primary_20mhz, uint8 chan0, uint8 chan1)
++{
++	int sb = 0;
++	uint16 chanspec = 0;
++	int chan0_id = 0, chan1_id = 0;
++	int seg0, seg1;
++
++	chan0_id = channel_80mhz_to_id(chan0);
++	chan1_id = channel_80mhz_to_id(chan1);
++
++	/* make sure the channel numbers were valid */
++	if (chan0_id == -1 || chan1_id == -1)
++		return INVCHANSPEC;
++
++	/* does the primary channel fit with the 1st 80MHz channel ? */
++	sb = channel_to_sb(chan0, primary_20mhz, 80);
++	if (sb >= 0) {
++		/* yes, so chan0 is frequency segment 0, and chan1 is seg 1 */
++		seg0 = chan0_id;
++		seg1 = chan1_id;
++	} else {
++		/* no, so does the primary channel fit with the 2nd 80MHz channel ? */
++		sb = channel_to_sb(chan1, primary_20mhz, 80);
++		if (sb < 0) {
++			/* no match for ctl_ch to either 80MHz center channel */
++			return INVCHANSPEC;
++		}
++		/* swapped, so chan1 is frequency segment 0, and chan0 is seg 1 */
++		seg0 = chan1_id;
++		seg1 = chan0_id;
++	}
++
++	chanspec = ((seg0 << WL_CHANSPEC_CHAN1_SHIFT) |
++	            (seg1 << WL_CHANSPEC_CHAN2_SHIFT) |
++	            (sb << WL_CHANSPEC_CTL_SB_SHIFT) |
++	            WL_CHANSPEC_BW_8080 |
++	            WL_CHANSPEC_BAND_5G);
++
++	return chanspec;
++}
++
++/*
++ * This function returns the 80Mhz channel for the given id.
++ */
++static uint8
++wf_chspec_get80Mhz_ch(uint8 chan_80Mhz_id)
++{
++	if (chan_80Mhz_id < WF_NUM_5G_80M_CHANS)
++		return wf_5g_80m_chans[chan_80Mhz_id];
++
++	return 0;
++}
++
++/*
++ * Returns the primary 80 Mhz channel for the provided chanspec
++ *
++ *    chanspec - Input chanspec for which the 80MHz primary channel has to be retrieved
++ *
++ *  returns -1 in case the provided channel is 20/40 Mhz chanspec
++ */
++
++uint8
++wf_chspec_primary80_channel(chanspec_t chanspec)
++{
++	uint8 primary80_chan;
++
++	if (CHSPEC_IS80(chanspec))	{
++		primary80_chan = CHSPEC_CHANNEL(chanspec);
++	}
++	else if (CHSPEC_IS8080(chanspec)) {
++		/* Channel ID 1 corresponds to frequency segment 0, the primary 80 MHz segment */
++		primary80_chan = wf_chspec_get80Mhz_ch(CHSPEC_CHAN1(chanspec));
++	}
++	else if (CHSPEC_IS160(chanspec)) {
++		uint8 center_chan = CHSPEC_CHANNEL(chanspec);
++		uint sb = CHSPEC_CTL_SB(chanspec) >> WL_CHANSPEC_CTL_SB_SHIFT;
++
++		/* based on the sb value primary 80 channel can be retrieved
++		 * if sb is in range 0 to 3 the lower band is the 80Mhz primary band
++		 */
++		if (sb < 4) {
++			primary80_chan = center_chan - CH_40MHZ_APART;
++		}
++		/* if sb is in range 4 to 7 the upper band is the 80Mhz primary band */
++		else
++		{
++			primary80_chan = center_chan + CH_40MHZ_APART;
++		}
++	}
++	else {
++		/* for 20 and 40 Mhz */
++		primary80_chan = -1;
++	}
++	return primary80_chan;
++}
++
++/*
++ * Returns the secondary 80 Mhz channel for the provided chanspec
++ *
++ *    chanspec - Input chanspec for which the 80MHz secondary channel has to be retrieved
++ *
++ *  returns -1 in case the provided channel is 20/40/80 Mhz chanspec
++ */
++uint8
++wf_chspec_secondary80_channel(chanspec_t chanspec)
++{
++	uint8 secondary80_chan;
++
++	if (CHSPEC_IS8080(chanspec)) {
++		secondary80_chan = wf_chspec_get80Mhz_ch(CHSPEC_CHAN2(chanspec));
++	}
++	else if (CHSPEC_IS160(chanspec)) {
++		uint8 center_chan = CHSPEC_CHANNEL(chanspec);
++		uint sb = CHSPEC_CTL_SB(chanspec) >> WL_CHANSPEC_CTL_SB_SHIFT;
++
++		/* based on the sb value  secondary 80 channel can be retrieved
++		 * if sb is in range 0 to 3 upper band is the secondary 80Mhz band
++		 */
++		if (sb < 4) {
++			secondary80_chan = center_chan + CH_40MHZ_APART;
++		}
++		/* if sb is in range 4 to 7 the lower band is the secondary 80Mhz band */
++		else
++		{
++			secondary80_chan = center_chan - CH_40MHZ_APART;
++		}
++	}
++	else {
++		/* for 20, 40, and 80 Mhz */
++		secondary80_chan = -1;
++	}
++	return secondary80_chan;
++}
++
++/*
++ * This function returns the chanspec for the primary 80MHz of an 160MHz or 80+80 channel.
++ *
++ *    chanspec - Input chanspec for which the primary 80Mhz chanspec has to be retreived
++ *
++ *  returns the input chanspec in case the provided chanspec is an 80 MHz chanspec
++ *  returns INVCHANSPEC in case the provided channel is 20/40 MHz chanspec
++ */
++chanspec_t
++wf_chspec_primary80_chspec(chanspec_t chspec)
++{
++	chanspec_t chspec80;
++	uint center_chan;
++	uint sb;
++
++	ASSERT(!wf_chspec_malformed(chspec));
++	if (CHSPEC_IS80(chspec)) {
++		chspec80 = chspec;
++	}
++	else if (CHSPEC_IS8080(chspec)) {
++
++		/* Channel ID 1 corresponds to frequency segment 0, the primary 80 MHz segment */
++		center_chan = wf_chspec_get80Mhz_ch(CHSPEC_CHAN1(chspec));
++
++		sb = CHSPEC_CTL_SB(chspec);
++
++		/* Create primary 80MHz chanspec */
++		chspec80 = (WL_CHANSPEC_BAND_5G | WL_CHANSPEC_BW_80 | sb | center_chan);
++	}
++	else if (CHSPEC_IS160(chspec)) {
++		center_chan = CHSPEC_CHANNEL(chspec);
++		sb = CHSPEC_CTL_SB(chspec);
++
++		if (sb < WL_CHANSPEC_CTL_SB_ULL) {
++			/* Primary 80MHz is on lower side */
++			center_chan -= CH_40MHZ_APART;
++		}
++		else {
++			/* Primary 80MHz is on upper side */
++			center_chan += CH_40MHZ_APART;
++			sb -= WL_CHANSPEC_CTL_SB_ULL;
++		}
++		/* Create primary 80MHz chanspec */
++		chspec80 = (WL_CHANSPEC_BAND_5G | WL_CHANSPEC_BW_80 | sb | center_chan);
++	}
++	else {
++		chspec80 = INVCHANSPEC;
++	}
++
++	return chspec80;
++}
++
++#ifdef WL11AC_80P80
++uint8
++wf_chspec_channel(chanspec_t chspec)
++{
++	if (CHSPEC_IS8080(chspec)) {
++		return wf_chspec_primary80_channel(chspec);
++	}
++	else {
++		return ((uint8)((chspec) & WL_CHANSPEC_CHAN_MASK));
++	}
++}
++#endif /* WL11AC_80P80 */
++
++#ifdef WL_OLDPPR
++/* given a chanspec and a string buffer, format the chanspec as a
++ * string, and return the original pointer a.
++ * Min buffer length must be CHANSPEC_STR_LEN.
++ * On error return NULL
++ */
++char *
++wf_chspec_ntoa_old(chanspec_t chspec, char *buf)
++{
++	const char *band, *bw, *sb;
++	uint channel;
++
++	band = "";
++	bw = "";
++	sb = "";
++	channel = CHSPEC_CHANNEL_OLD(chspec);
++	/* check for non-default band spec */
++	if ((CHSPEC_IS2G_OLD(chspec) && channel > CH_MAX_2G_CHANNEL) ||
++	    (CHSPEC_IS5G_OLD(chspec) && channel <= CH_MAX_2G_CHANNEL))
++		band = (CHSPEC_IS2G_OLD(chspec)) ? "b" : "a";
++	if (CHSPEC_IS40_OLD(chspec)) {
++		if (CHSPEC_SB_UPPER_OLD(chspec)) {
++			sb = "u";
++			channel += CH_10MHZ_APART;
++		} else {
++			sb = "l";
++			channel -= CH_10MHZ_APART;
++		}
++	} else if (CHSPEC_IS10_OLD(chspec)) {
++		bw = "n";
++	}
++
++	/* Outputs a max of 6 chars including '\0'  */
++	snprintf(buf, 6, "%d%s%s%s", channel, band, bw, sb);
++	return (buf);
++}
++#endif /* WL_OLDPPR */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmwifi_channels.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmwifi_channels.h
+new file mode 100644
+index 000000000..6c247a72c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmwifi_channels.h
+@@ -0,0 +1,663 @@
++/*
++ * Misc utility routines for WL and Apps
++ * This header file housing the define and function prototype use by
++ * both the wl driver, tools & Apps.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmwifi_channels.h 309193 2012-01-19 00:03:57Z $
++ */
++
++#ifndef	_bcmwifi_channels_h_
++#define	_bcmwifi_channels_h_
++
++
++/* A chanspec holds the channel number, band, bandwidth and control sideband */
++typedef uint16 chanspec_t;
++
++/* channel defines */
++#define CH_UPPER_SB			0x01
++#define CH_LOWER_SB			0x02
++#define CH_EWA_VALID			0x04
++#define CH_80MHZ_APART			16
++#define CH_40MHZ_APART			8
++#define CH_20MHZ_APART			4
++#define CH_10MHZ_APART			2
++#define CH_5MHZ_APART			1	/* 2G band channels are 5 Mhz apart */
++#define CH_MAX_2G_CHANNEL		14	/* Max channel in 2G band */
++
++/* maximum # channels the s/w supports */
++#define MAXCHANNEL		224	/* max # supported channels. The max channel no is above,
++					 * this is that + 1 rounded up to a multiple of NBBY (8).
++					 * DO NOT MAKE it > 255: channels are uint8's all over
++					 */
++#define MAXCHANNEL_NUM	(MAXCHANNEL - 1)	/* max channel number */
++
++/* channel bitvec */
++typedef struct {
++	uint8   vec[MAXCHANNEL/8];   /* bitvec of channels */
++} chanvec_t;
++
++/* make sure channel num is within valid range */
++#define CH_NUM_VALID_RANGE(ch_num) ((ch_num) > 0 && (ch_num) <= MAXCHANNEL_NUM)
++
++#define CHSPEC_CTLOVLP(sp1, sp2, sep)	\
++	(ABS(wf_chspec_ctlchan(sp1) - wf_chspec_ctlchan(sp2)) < (sep))
++
++/* All builds use the new 11ac ratespec/chanspec */
++#undef  D11AC_IOTYPES
++#define D11AC_IOTYPES
++
++#define WL_CHANSPEC_CHAN_MASK		0x00ff
++#define WL_CHANSPEC_CHAN_SHIFT		0
++#define WL_CHANSPEC_CHAN1_MASK		0x000f
++#define WL_CHANSPEC_CHAN1_SHIFT		0
++#define WL_CHANSPEC_CHAN2_MASK		0x00f0
++#define WL_CHANSPEC_CHAN2_SHIFT		4
++
++#define WL_CHANSPEC_CTL_SB_MASK		0x0700
++#define WL_CHANSPEC_CTL_SB_SHIFT	8
++#define WL_CHANSPEC_CTL_SB_LLL		0x0000
++#define WL_CHANSPEC_CTL_SB_LLU		0x0100
++#define WL_CHANSPEC_CTL_SB_LUL		0x0200
++#define WL_CHANSPEC_CTL_SB_LUU		0x0300
++#define WL_CHANSPEC_CTL_SB_ULL		0x0400
++#define WL_CHANSPEC_CTL_SB_ULU		0x0500
++#define WL_CHANSPEC_CTL_SB_UUL		0x0600
++#define WL_CHANSPEC_CTL_SB_UUU		0x0700
++#define WL_CHANSPEC_CTL_SB_LL		WL_CHANSPEC_CTL_SB_LLL
++#define WL_CHANSPEC_CTL_SB_LU		WL_CHANSPEC_CTL_SB_LLU
++#define WL_CHANSPEC_CTL_SB_UL		WL_CHANSPEC_CTL_SB_LUL
++#define WL_CHANSPEC_CTL_SB_UU		WL_CHANSPEC_CTL_SB_LUU
++#define WL_CHANSPEC_CTL_SB_L		WL_CHANSPEC_CTL_SB_LLL
++#define WL_CHANSPEC_CTL_SB_U		WL_CHANSPEC_CTL_SB_LLU
++#define WL_CHANSPEC_CTL_SB_LOWER	WL_CHANSPEC_CTL_SB_LLL
++#define WL_CHANSPEC_CTL_SB_UPPER	WL_CHANSPEC_CTL_SB_LLU
++#define WL_CHANSPEC_CTL_SB_NONE		WL_CHANSPEC_CTL_SB_LLL
++
++#define WL_CHANSPEC_BW_MASK		0x3800
++#define WL_CHANSPEC_BW_SHIFT		11
++#define WL_CHANSPEC_BW_5		0x0000
++#define WL_CHANSPEC_BW_10		0x0800
++#define WL_CHANSPEC_BW_20		0x1000
++#define WL_CHANSPEC_BW_40		0x1800
++#define WL_CHANSPEC_BW_80		0x2000
++#define WL_CHANSPEC_BW_160		0x2800
++#define WL_CHANSPEC_BW_8080		0x3000
++#define WL_CHANSPEC_BW_2P5		0x3800
++
++#define WL_CHANSPEC_BAND_MASK		0xc000
++#define WL_CHANSPEC_BAND_SHIFT		14
++#define WL_CHANSPEC_BAND_2G		0x0000
++#define WL_CHANSPEC_BAND_3G		0x4000
++#define WL_CHANSPEC_BAND_4G		0x8000
++#define WL_CHANSPEC_BAND_5G		0xc000
++#define INVCHANSPEC			255
++#define MAX_CHANSPEC				0xFFFF
++
++/* channel defines */
++#define LOWER_20_SB(channel)		(((channel) > CH_10MHZ_APART) ? \
++					((channel) - CH_10MHZ_APART) : 0)
++#define UPPER_20_SB(channel)		(((channel) < (MAXCHANNEL - CH_10MHZ_APART)) ? \
++					((channel) + CH_10MHZ_APART) : 0)
++
++#define LL_20_SB(channel) (((channel) > 3 * CH_10MHZ_APART) ? ((channel) - 3 * CH_10MHZ_APART) : 0)
++#define UU_20_SB(channel) 	(((channel) < (MAXCHANNEL - 3 * CH_10MHZ_APART)) ? \
++				((channel) + 3 * CH_10MHZ_APART) : 0)
++#define LU_20_SB(channel) LOWER_20_SB(channel)
++#define UL_20_SB(channel) UPPER_20_SB(channel)
++
++#define LOWER_40_SB(channel)		((channel) - CH_20MHZ_APART)
++#define UPPER_40_SB(channel)		((channel) + CH_20MHZ_APART)
++#define CHSPEC_WLCBANDUNIT(chspec)	(CHSPEC_IS5G(chspec) ? BAND_5G_INDEX : BAND_2G_INDEX)
++#define CH20MHZ_CHSPEC(channel)		(chanspec_t)((chanspec_t)(channel) | WL_CHANSPEC_BW_20 | \
++					(((channel) <= CH_MAX_2G_CHANNEL) ? \
++					WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
++#define CH2P5MHZ_CHSPEC(channel)	(chanspec_t)((chanspec_t)(channel) | WL_CHANSPEC_BW_2P5 | \
++						(((channel) <= CH_MAX_2G_CHANNEL) ? \
++						WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
++#define CH5MHZ_CHSPEC(channel)		(chanspec_t)((chanspec_t)(channel) | WL_CHANSPEC_BW_5 | \
++						(((channel) <= CH_MAX_2G_CHANNEL) ? \
++						WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
++#define CH10MHZ_CHSPEC(channel)		(chanspec_t)((chanspec_t)(channel) | WL_CHANSPEC_BW_10 | \
++						(((channel) <= CH_MAX_2G_CHANNEL) ? \
++						WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
++#define NEXT_20MHZ_CHAN(channel)	(((channel) < (MAXCHANNEL - CH_20MHZ_APART)) ? \
++					((channel) + CH_20MHZ_APART) : 0)
++#define CH40MHZ_CHSPEC(channel, ctlsb)	(chanspec_t) \
++					((channel) | (ctlsb) | WL_CHANSPEC_BW_40 | \
++					((channel) <= CH_MAX_2G_CHANNEL ? WL_CHANSPEC_BAND_2G : \
++					WL_CHANSPEC_BAND_5G))
++#define CH80MHZ_CHSPEC(channel, ctlsb)	(chanspec_t) \
++					((channel) | (ctlsb) | \
++					 WL_CHANSPEC_BW_80 | WL_CHANSPEC_BAND_5G)
++#define CH160MHZ_CHSPEC(channel, ctlsb)	(chanspec_t) \
++					((channel) | (ctlsb) | \
++					 WL_CHANSPEC_BW_160 | WL_CHANSPEC_BAND_5G)
++#define CHBW_CHSPEC(bw, channel)	(chanspec_t)((chanspec_t)(channel) | (bw) | \
++							(((channel) <= CH_MAX_2G_CHANNEL) ? \
++							WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
++
++/* simple MACROs to get different fields of chanspec */
++#ifdef WL11AC_80P80
++#define CHSPEC_CHANNEL(chspec)	wf_chspec_channel(chspec)
++#else
++#define CHSPEC_CHANNEL(chspec)	((uint8)((chspec) & WL_CHANSPEC_CHAN_MASK))
++#endif
++#define CHSPEC_CHAN1(chspec)	((chspec) & WL_CHANSPEC_CHAN1_MASK) >> WL_CHANSPEC_CHAN1_SHIFT
++#define CHSPEC_CHAN2(chspec)	((chspec) & WL_CHANSPEC_CHAN2_MASK) >> WL_CHANSPEC_CHAN2_SHIFT
++#define CHSPEC_BAND(chspec)		((chspec) & WL_CHANSPEC_BAND_MASK)
++#define CHSPEC_CTL_SB(chspec)	((chspec) & WL_CHANSPEC_CTL_SB_MASK)
++#define CHSPEC_BW(chspec)		((chspec) & WL_CHANSPEC_BW_MASK)
++
++#ifdef WL11N_20MHZONLY
++
++#define CHSPEC_IS2P5(chspec)	0
++#define CHSPEC_IS5(chspec)	0
++#define CHSPEC_IS10(chspec)	0
++#define CHSPEC_IS20(chspec)	1
++#ifndef CHSPEC_IS40
++#define CHSPEC_IS40(chspec)	0
++#endif
++#ifndef CHSPEC_IS80
++#define CHSPEC_IS80(chspec)	0
++#endif
++#ifndef CHSPEC_IS160
++#define CHSPEC_IS160(chspec)	0
++#endif
++#ifndef CHSPEC_IS8080
++#define CHSPEC_IS8080(chspec)	0
++#endif
++#define BW_LE20(bw)		TRUE
++#define CHSPEC_ISLE20(chspec)	TRUE
++#else /* !WL11N_20MHZONLY */
++
++#define CHSPEC_IS2P5(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_2P5)
++#define CHSPEC_IS5(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_5)
++#define CHSPEC_IS10(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_10)
++#define CHSPEC_IS20(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_20)
++#ifndef CHSPEC_IS40
++#define CHSPEC_IS40(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40)
++#endif
++#ifndef CHSPEC_IS80
++#define CHSPEC_IS80(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_80)
++#endif
++#ifndef CHSPEC_IS160
++#define CHSPEC_IS160(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_160)
++#endif
++#ifndef CHSPEC_IS8080
++#define CHSPEC_IS8080(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_8080)
++#endif
++
++#ifdef WL11ULB
++#define BW_LT20(bw)		(((bw) == WL_CHANSPEC_BW_2P5) || \
++				((bw) == WL_CHANSPEC_BW_5) || \
++				((bw) == WL_CHANSPEC_BW_10))
++#define CHSPEC_BW_LT20(chspec)	(BW_LT20(CHSPEC_BW(chspec)))
++/* This MACRO is strictly to avoid abandons in existing code with ULB feature and is in no way
++ * optimial to use. Should be replaced with CHSPEC_BW_LE() instead
++ */
++#define BW_LE20(bw)		(((bw) == WL_CHANSPEC_BW_2P5) || \
++				((bw) == WL_CHANSPEC_BW_5) || \
++				((bw) == WL_CHANSPEC_BW_10) || \
++				((bw) == WL_CHANSPEC_BW_20))
++#define CHSPEC_ISLE20(chspec)	(BW_LE20(CHSPEC_BW(chspec)))
++
++#else /* WL11ULB */
++#define BW_LE20(bw)		((bw) == WL_CHANSPEC_BW_20)
++#define CHSPEC_ISLE20(chspec)	(CHSPEC_IS20(chspec))
++#endif /* WL11ULB */
++#endif /* !WL11N_20MHZONLY */
++
++#define BW_LE40(bw)		(BW_LE20(bw) || ((bw) == WL_CHANSPEC_BW_40))
++#define BW_LE80(bw)		(BW_LE40(bw) || ((bw) == WL_CHANSPEC_BW_80))
++#define BW_LE160(bw)		(BW_LE80(bw) || ((bw) == WL_CHANSPEC_BW_160))
++#define CHSPEC_BW_LE20(chspec)	(BW_LE20(CHSPEC_BW(chspec)))
++#define CHSPEC_IS5G(chspec)	(((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_5G)
++#define CHSPEC_IS2G(chspec)	(((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_2G)
++#define CHSPEC_SB_UPPER(chspec)	\
++	((((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_UPPER) && \
++	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40))
++#define CHSPEC_SB_LOWER(chspec)	\
++	((((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_LOWER) && \
++	(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40))
++#define CHSPEC2WLC_BAND(chspec) (CHSPEC_IS5G(chspec) ? WLC_BAND_5G : WLC_BAND_2G)
++
++/**
++ * Number of chars needed for wf_chspec_ntoa() destination character buffer.
++ */
++#define CHANSPEC_STR_LEN    20
++
++
++#define CHSPEC_IS_BW_160_WIDE(chspec) (CHSPEC_BW(chspec) == WL_CHANSPEC_BW_160 ||\
++	CHSPEC_BW(chspec) == WL_CHANSPEC_BW_8080)
++
++/* BW inequality comparisons, LE (<=), GE (>=), LT (<), GT (>), comparisons can be made
++* as simple numeric comparisons, with the exception that 160 is the same BW as 80+80,
++* but have different numeric values; (WL_CHANSPEC_BW_160 < WL_CHANSPEC_BW_8080).
++*
++* The LT/LE/GT/GE macros check first checks whether both chspec bandwidth and bw are 160 wide.
++* If both chspec bandwidth and bw is not 160 wide, then the comparison is made.
++*/
++#ifdef WL11ULB
++#define CHSPEC_BW_GE(chspec, bw) \
++	(((CHSPEC_IS_BW_160_WIDE(chspec) &&\
++	((bw) == WL_CHANSPEC_BW_160 || (bw) == WL_CHANSPEC_BW_8080)) ||\
++	(CHSPEC_BW(chspec) >= (bw))) && \
++	(!(CHSPEC_BW(chspec) == WL_CHANSPEC_BW_2P5 && (bw) != WL_CHANSPEC_BW_2P5)))
++#else /* WL11ULB */
++#define CHSPEC_BW_GE(chspec, bw) \
++		((CHSPEC_IS_BW_160_WIDE(chspec) &&\
++		((bw) == WL_CHANSPEC_BW_160 || (bw) == WL_CHANSPEC_BW_8080)) ||\
++		(CHSPEC_BW(chspec) >= (bw)))
++#endif /* WL11ULB */
++
++#ifdef WL11ULB
++#define CHSPEC_BW_LE(chspec, bw) \
++	(((CHSPEC_IS_BW_160_WIDE(chspec) &&\
++	((bw) == WL_CHANSPEC_BW_160 || (bw) == WL_CHANSPEC_BW_8080)) ||\
++	(CHSPEC_BW(chspec) <= (bw))) || \
++	(CHSPEC_BW(chspec) == WL_CHANSPEC_BW_2P5))
++#else /* WL11ULB */
++#define CHSPEC_BW_LE(chspec, bw) \
++		((CHSPEC_IS_BW_160_WIDE(chspec) &&\
++		((bw) == WL_CHANSPEC_BW_160 || (bw) == WL_CHANSPEC_BW_8080)) ||\
++		(CHSPEC_BW(chspec) <= (bw)))
++#endif /* WL11ULB */
++
++#ifdef WL11ULB
++#define CHSPEC_BW_GT(chspec, bw) \
++	((!(CHSPEC_IS_BW_160_WIDE(chspec) &&\
++	((bw) == WL_CHANSPEC_BW_160 || (bw) == WL_CHANSPEC_BW_8080)) &&\
++	(CHSPEC_BW(chspec) > (bw))) && \
++	(CHSPEC_BW(chspec) != WL_CHANSPEC_BW_2P5))
++#else /* WL11ULB */
++#define CHSPEC_BW_GT(chspec, bw) \
++		(!(CHSPEC_IS_BW_160_WIDE(chspec) &&\
++		((bw) == WL_CHANSPEC_BW_160 || (bw) == WL_CHANSPEC_BW_8080)) &&\
++		(CHSPEC_BW(chspec) > (bw)))
++#endif /* WL11ULB */
++
++#ifdef WL11ULB
++#define CHSPEC_BW_LT(chspec, bw) \
++	((!(CHSPEC_IS_BW_160_WIDE(chspec) &&\
++	((bw) == WL_CHANSPEC_BW_160 || (bw) == WL_CHANSPEC_BW_8080)) &&\
++	(CHSPEC_BW(chspec) < (bw))) || \
++	((CHSPEC_BW(chspec) == WL_CHANSPEC_BW_2P5 && (bw) != WL_CHANSPEC_BW_2P5)))
++#else /* WL11ULB */
++#define CHSPEC_BW_LT(chspec, bw) \
++		(!(CHSPEC_IS_BW_160_WIDE(chspec) &&\
++		((bw) == WL_CHANSPEC_BW_160 || (bw) == WL_CHANSPEC_BW_8080)) &&\
++		(CHSPEC_BW(chspec) < (bw)))
++#endif /* WL11ULB */
++
++/* Legacy Chanspec defines
++ * These are the defines for the previous format of the chanspec_t
++ */
++#define WL_LCHANSPEC_CHAN_MASK		0x00ff
++#define WL_LCHANSPEC_CHAN_SHIFT		     0
++
++#define WL_LCHANSPEC_CTL_SB_MASK	0x0300
++#define WL_LCHANSPEC_CTL_SB_SHIFT	     8
++#define WL_LCHANSPEC_CTL_SB_LOWER	0x0100
++#define WL_LCHANSPEC_CTL_SB_UPPER	0x0200
++#define WL_LCHANSPEC_CTL_SB_NONE	0x0300
++
++#define WL_LCHANSPEC_BW_MASK		0x0C00
++#define WL_LCHANSPEC_BW_SHIFT		    10
++#define WL_LCHANSPEC_BW_10		0x0400
++#define WL_LCHANSPEC_BW_20		0x0800
++#define WL_LCHANSPEC_BW_40		0x0C00
++
++#define WL_LCHANSPEC_BAND_MASK		0xf000
++#define WL_LCHANSPEC_BAND_SHIFT		    12
++#define WL_LCHANSPEC_BAND_5G		0x1000
++#define WL_LCHANSPEC_BAND_2G		0x2000
++
++#define LCHSPEC_CHANNEL(chspec)	((uint8)((chspec) & WL_LCHANSPEC_CHAN_MASK))
++#define LCHSPEC_BAND(chspec)	((chspec) & WL_LCHANSPEC_BAND_MASK)
++#define LCHSPEC_CTL_SB(chspec)	((chspec) & WL_LCHANSPEC_CTL_SB_MASK)
++#define LCHSPEC_BW(chspec)	((chspec) & WL_LCHANSPEC_BW_MASK)
++#define LCHSPEC_IS10(chspec)	(((chspec) & WL_LCHANSPEC_BW_MASK) == WL_LCHANSPEC_BW_10)
++#define LCHSPEC_IS20(chspec)	(((chspec) & WL_LCHANSPEC_BW_MASK) == WL_LCHANSPEC_BW_20)
++#define LCHSPEC_IS40(chspec)	(((chspec) & WL_LCHANSPEC_BW_MASK) == WL_LCHANSPEC_BW_40)
++#define LCHSPEC_IS5G(chspec)	(((chspec) & WL_LCHANSPEC_BAND_MASK) == WL_LCHANSPEC_BAND_5G)
++#define LCHSPEC_IS2G(chspec)	(((chspec) & WL_LCHANSPEC_BAND_MASK) == WL_LCHANSPEC_BAND_2G)
++
++#define LCHSPEC_SB_UPPER(chspec)	\
++	((((chspec) & WL_LCHANSPEC_CTL_SB_MASK) == WL_LCHANSPEC_CTL_SB_UPPER) && \
++	(((chspec) & WL_LCHANSPEC_BW_MASK) == WL_LCHANSPEC_BW_40))
++#define LCHSPEC_SB_LOWER(chspec)	\
++	((((chspec) & WL_LCHANSPEC_CTL_SB_MASK) == WL_LCHANSPEC_CTL_SB_LOWER) && \
++	(((chspec) & WL_LCHANSPEC_BW_MASK) == WL_LCHANSPEC_BW_40))
++
++#define LCHSPEC_CREATE(chan, band, bw, sb)  ((uint16)((chan) | (sb) | (bw) | (band)))
++
++#define CH20MHZ_LCHSPEC(channel) \
++	(chanspec_t)((chanspec_t)(channel) | WL_LCHANSPEC_BW_20 | \
++	WL_LCHANSPEC_CTL_SB_NONE | (((channel) <= CH_MAX_2G_CHANNEL) ? \
++	WL_LCHANSPEC_BAND_2G : WL_LCHANSPEC_BAND_5G))
++
++/*
++ * WF_CHAN_FACTOR_* constants are used to calculate channel frequency
++ * given a channel number.
++ * chan_freq = chan_factor * 500Mhz + chan_number * 5
++ */
++
++/**
++ * Channel Factor for the starting frequence of 2.4 GHz channels.
++ * The value corresponds to 2407 MHz.
++ */
++#define WF_CHAN_FACTOR_2_4_G		4814	/* 2.4 GHz band, 2407 MHz */
++
++/**
++ * Channel Factor for the starting frequence of 5 GHz channels.
++ * The value corresponds to 5000 MHz.
++ */
++#define WF_CHAN_FACTOR_5_G		10000	/* 5   GHz band, 5000 MHz */
++
++/**
++ * Channel Factor for the starting frequence of 4.9 GHz channels.
++ * The value corresponds to 4000 MHz.
++ */
++#define WF_CHAN_FACTOR_4_G		8000	/* 4.9 GHz band for Japan */
++
++#define WLC_2G_25MHZ_OFFSET		5	/* 2.4GHz band channel offset */
++
++/**
++ *  No of sub-band vlaue of the specified Mhz chanspec
++ */
++#define WF_NUM_SIDEBANDS_40MHZ   2
++#define WF_NUM_SIDEBANDS_80MHZ   4
++#define WF_NUM_SIDEBANDS_8080MHZ 4
++#define WF_NUM_SIDEBANDS_160MHZ  8
++
++/**
++ * Convert chanspec to ascii string
++ *
++ * @param	chspec		chanspec format
++ * @param	buf		ascii string of chanspec
++ *
++ * @return	pointer to buf with room for at least CHANSPEC_STR_LEN bytes
++ *		Original chanspec in case of error
++ *
++ * @see		CHANSPEC_STR_LEN
++ */
++extern char * wf_chspec_ntoa_ex(chanspec_t chspec, char *buf);
++
++/**
++ * Convert chanspec to ascii string
++ *
++ * @param	chspec		chanspec format
++ * @param	buf		ascii string of chanspec
++ *
++ * @return	pointer to buf with room for at least CHANSPEC_STR_LEN bytes
++ *		NULL in case of error
++ *
++ * @see		CHANSPEC_STR_LEN
++ */
++extern char * wf_chspec_ntoa(chanspec_t chspec, char *buf);
++
++/**
++ * Convert ascii string to chanspec
++ *
++ * @param	a     pointer to input string
++ *
++ * @return	>= 0 if successful or 0 otherwise
++ */
++extern chanspec_t wf_chspec_aton(const char *a);
++
++/**
++ * Verify the chanspec fields are valid.
++ *
++ * Verify the chanspec is using a legal set field values, i.e. that the chanspec
++ * specified a band, bw, ctl_sb and channel and that the combination could be
++ * legal given some set of circumstances.
++ *
++ * @param	chanspec   input chanspec to verify
++ *
++ * @return TRUE if the chanspec is malformed, FALSE if it looks good.
++ */
++extern bool wf_chspec_malformed(chanspec_t chanspec);
++
++/**
++ * Verify the chanspec specifies a valid channel according to 802.11.
++ *
++ * @param	chanspec   input chanspec to verify
++ *
++ * @return TRUE if the chanspec is a valid 802.11 channel
++ */
++extern bool wf_chspec_valid(chanspec_t chanspec);
++
++/**
++ * Return the primary (control) channel.
++ *
++ * This function returns the channel number of the primary 20MHz channel. For
++ * 20MHz channels this is just the channel number. For 40MHz or wider channels
++ * it is the primary 20MHz channel specified by the chanspec.
++ *
++ * @param	chspec    input chanspec
++ *
++ * @return Returns the channel number of the primary 20MHz channel
++ */
++extern uint8 wf_chspec_ctlchan(chanspec_t chspec);
++
++/*
++ * Return the bandwidth string.
++ *
++ * This function returns the bandwidth string for the passed chanspec.
++ *
++ * @param	chspec    input chanspec
++ *
++ * @return Returns the bandwidth string
++ */
++extern char * wf_chspec_to_bw_str(chanspec_t chspec);
++
++/**
++ * Return the primary (control) chanspec.
++ *
++ * This function returns the chanspec of the primary 20MHz channel. For 20MHz
++ * channels this is just the chanspec. For 40MHz or wider channels it is the
++ * chanspec of the primary 20MHZ channel specified by the chanspec.
++ *
++ * @param	chspec    input chanspec
++ *
++ * @return Returns the chanspec of the primary 20MHz channel
++ */
++extern chanspec_t wf_chspec_ctlchspec(chanspec_t chspec);
++
++/**
++ * Return a channel number corresponding to a frequency.
++ *
++ * This function returns the chanspec for the primary 40MHz of an 80MHz channel.
++ * The control sideband specifies the same 20MHz channel that the 80MHz channel is using
++ * as the primary 20MHz channel.
++ */
++extern chanspec_t wf_chspec_primary40_chspec(chanspec_t chspec);
++
++/*
++ * Return the channel number for a given frequency and base frequency.
++ * The returned channel number is relative to the given base frequency.
++ * If the given base frequency is zero, a base frequency of 5 GHz is assumed for
++ * frequencies from 5 - 6 GHz, and 2.407 GHz is assumed for 2.4 - 2.5 GHz.
++ *
++ * Frequency is specified in MHz.
++ * The base frequency is specified as (start_factor * 500 kHz).
++ * Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_5_G are defined for
++ * 2.4 GHz and 5 GHz bands.
++ *
++ * The returned channel will be in the range [1, 14] in the 2.4 GHz band
++ * and [0, 200] otherwise.
++ * -1 is returned if the start_factor is WF_CHAN_FACTOR_2_4_G and the
++ * frequency is not a 2.4 GHz channel, or if the frequency is not and even
++ * multiple of 5 MHz from the base frequency to the base plus 1 GHz.
++ *
++ * Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
++ *
++ * @param	freq          frequency in MHz
++ * @param	start_factor  base frequency in 500 kHz units, e.g. 10000 for 5 GHz
++ *
++ * @return Returns a channel number
++ *
++ * @see  WF_CHAN_FACTOR_2_4_G
++ * @see  WF_CHAN_FACTOR_5_G
++ */
++extern int wf_mhz2channel(uint freq, uint start_factor);
++
++/**
++ * Return the center frequency in MHz of the given channel and base frequency.
++ *
++ * Return the center frequency in MHz of the given channel and base frequency.
++ * The channel number is interpreted relative to the given base frequency.
++ *
++ * The valid channel range is [1, 14] in the 2.4 GHz band and [0, 200] otherwise.
++ * The base frequency is specified as (start_factor * 500 kHz).
++ * Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_5_G are defined for
++ * 2.4 GHz and 5 GHz bands.
++ * The channel range of [1, 14] is only checked for a start_factor of
++ * WF_CHAN_FACTOR_2_4_G (4814).
++ * Odd start_factors produce channels on .5 MHz boundaries, in which case
++ * the answer is rounded down to an integral MHz.
++ * -1 is returned for an out of range channel.
++ *
++ * Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
++ *
++ * @param	channel       input channel number
++ * @param	start_factor  base frequency in 500 kHz units, e.g. 10000 for 5 GHz
++ *
++ * @return Returns a frequency in MHz
++ *
++ * @see  WF_CHAN_FACTOR_2_4_G
++ * @see  WF_CHAN_FACTOR_5_G
++ */
++extern int wf_channel2mhz(uint channel, uint start_factor);
++
++/**
++ * Returns the chanspec 80Mhz channel corresponding to the following input
++ * parameters
++ *
++ *	primary_channel - primary 20Mhz channel
++ *	center_channel   - center frequecny of the 80Mhz channel
++ *
++ * The center_channel can be one of {42, 58, 106, 122, 138, 155}
++ *
++ * returns INVCHANSPEC in case of error
++ */
++extern chanspec_t wf_chspec_80(uint8 center_channel, uint8 primary_channel);
++
++/**
++ * Convert ctl chan and bw to chanspec
++ *
++ * @param	ctl_ch		channel
++ * @param	bw	        bandwidth
++ *
++ * @return	> 0 if successful or 0 otherwise
++ *
++ */
++extern uint16 wf_channel2chspec(uint ctl_ch, uint bw);
++
++extern uint wf_channel2freq(uint channel);
++extern uint wf_freq2channel(uint freq);
++
++/*
++ * Returns the 80+80 MHz chanspec corresponding to the following input parameters
++ *
++ *    primary_20mhz - Primary 20 MHz channel
++ *    chan0_80MHz - center channel number of one frequency segment
++ *    chan1_80MHz - center channel number of the other frequency segment
++ *
++ * Parameters chan0_80MHz and chan1_80MHz are channel numbers in {42, 58, 106, 122, 138, 155}.
++ * The primary channel must be contained in one of the 80MHz channels. This routine
++ * will determine which frequency segment is the primary 80 MHz segment.
++ *
++ * Returns INVCHANSPEC in case of error.
++ *
++ * Refer to IEEE802.11ac section 22.3.14 "Channelization".
++ */
++extern chanspec_t wf_chspec_get8080_chspec(uint8 primary_20mhz,
++	uint8 chan0_80Mhz, uint8 chan1_80Mhz);
++
++/*
++ * Returns the primary 80 Mhz channel for the provided chanspec
++ *
++ *    chanspec - Input chanspec for which the 80MHz primary channel has to be retrieved
++ *
++ *  returns -1 in case the provided channel is 20/40 Mhz chanspec
++ */
++extern uint8 wf_chspec_primary80_channel(chanspec_t chanspec);
++
++/*
++ * Returns the secondary 80 Mhz channel for the provided chanspec
++ *
++ *    chanspec - Input chanspec for which the 80MHz secondary channel has to be retrieved
++ *
++ *  returns -1 in case the provided channel is 20/40 Mhz chanspec
++ */
++extern uint8 wf_chspec_secondary80_channel(chanspec_t chanspec);
++
++/*
++ * This function returns the chanspec for the primary 80MHz of an 160MHz or 80+80 channel.
++ */
++extern chanspec_t wf_chspec_primary80_chspec(chanspec_t chspec);
++
++#ifdef WL11AC_80P80
++/*
++ * This function returns the centre chanel for the given chanspec.
++ * In case of 80+80 chanspec it returns the primary 80 Mhz centre channel
++ */
++extern uint8 wf_chspec_channel(chanspec_t chspec);
++#endif
++
++#ifdef WL_OLDPPR
++#define WL_CHANSPEC_CTL_SB_MASK_OLD	0x0300
++#define WL_CHANSPEC_CTL_SB_SHIFT_OLD	8
++#define WL_CHANSPEC_CTL_SB_LOWER_OLD	0x0100
++#define WL_CHANSPEC_CTL_SB_UPPER_OLD	0x0200
++#define WL_CHANSPEC_CTL_SB_NONE_OLD	0x0300
++
++#define WL_CHANSPEC_BW_MASK_OLD		0x0C00
++#define WL_CHANSPEC_BW_SHIFT_OLD	10
++#define WL_CHANSPEC_BW_10_OLD		0x0400
++#define WL_CHANSPEC_BW_20_OLD		0x0800
++#define WL_CHANSPEC_BW_40_OLD		0x0C00
++
++#define WL_CHANSPEC_BAND_MASK_OLD	0xf000
++#define WL_CHANSPEC_BAND_SHIFT_OLD	12
++#define WL_CHANSPEC_BAND_5G_OLD		0x1000
++#define WL_CHANSPEC_BAND_2G_OLD		0x2000
++
++#define CHSPEC_CHANNEL_OLD(chspec)  ((uint8)((chspec) & WL_CHANSPEC_CHAN_MASK))
++#define CHSPEC_BAND_OLD(chspec)     ((chspec) & WL_CHANSPEC_BAND_MASK_OLD)
++
++#define CHSPEC_IS10_OLD(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK_OLD) == WL_CHANSPEC_BW_10_OLD)
++#define CHSPEC_IS20_OLD(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK_OLD) == WL_CHANSPEC_BW_20_OLD)
++#define CHSPEC_IS40_OLD(chspec)	(((chspec) & WL_CHANSPEC_BW_MASK_OLD) == WL_CHANSPEC_BW_40_OLD)
++#define CHSPEC_IS5G_OLD(chspec)	(((chspec) & WL_CHANSPEC_BAND_MASK_OLD) == WL_CHANSPEC_BAND_5G_OLD)
++#define CHSPEC_IS2G_OLD(chspec)	(((chspec) & WL_CHANSPEC_BAND_MASK_OLD) == WL_CHANSPEC_BAND_2G_OLD)
++#define CHSPEC_SB_NONE_OLD(chspec)	(((chspec) & WL_CHANSPEC_CTL_SB_MASK_OLD) == WL_CHANSPEC_CTL_SB_NONE_OLD)
++#define CHSPEC_SB_UPPER_OLD(chspec)	(((chspec) & WL_CHANSPEC_CTL_SB_MASK_OLD) == WL_CHANSPEC_CTL_SB_UPPER_OLD)
++#define CHSPEC_SB_LOWER_OLD(chspec)	(((chspec) & WL_CHANSPEC_CTL_SB_MASK_OLD) == WL_CHANSPEC_CTL_SB_LOWER_OLD)
++#endif /* WL_OLDPPR */
++
++#endif	/* _bcmwifi_channels_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmwifi_rates.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmwifi_rates.h
+new file mode 100644
+index 000000000..9abd7fdae
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmwifi_rates.h
+@@ -0,0 +1,930 @@
++/*
++ * Indices for 802.11 a/b/g/n/ac 1-3 chain symmetric transmit rates
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmwifi_rates.h 5187 2012-06-29 06:17:50Z $
++ */
++
++#ifndef _bcmwifi_rates_h_
++#define _bcmwifi_rates_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif /* __cplusplus */
++
++
++#define WL_RATESET_SZ_DSSS		4
++#define WL_RATESET_SZ_OFDM		8
++#define WL_RATESET_SZ_VHT_MCS	10
++#define WL_RATESET_SZ_VHT_MCS_P	12
++
++#if defined(WLPROPRIETARY_11N_RATES)
++#define WL_RATESET_SZ_HT_MCS	WL_RATESET_SZ_VHT_MCS
++#else
++#define WL_RATESET_SZ_HT_MCS	8
++#endif
++
++#define WL_RATESET_SZ_HT_IOCTL	8	/* MAC histogram, compatibility with wl utility */
++
++#define WL_TX_CHAINS_MAX		4
++
++#define WL_RATE_DISABLED		(-128) /* Power value corresponding to unsupported rate */
++
++/* Transmit channel bandwidths */
++typedef enum wl_tx_bw {
++	WL_TX_BW_20,
++	WL_TX_BW_40,
++	WL_TX_BW_80,
++	WL_TX_BW_20IN40,
++	WL_TX_BW_20IN80,
++	WL_TX_BW_40IN80,
++	WL_TX_BW_160,
++	WL_TX_BW_20IN160,
++	WL_TX_BW_40IN160,
++	WL_TX_BW_80IN160,
++	WL_TX_BW_ALL,
++	WL_TX_BW_8080,
++	WL_TX_BW_8080CHAN2,
++	WL_TX_BW_20IN8080,
++	WL_TX_BW_40IN8080,
++	WL_TX_BW_80IN8080,
++	WL_TX_BW_2P5,
++	WL_TX_BW_5,
++	WL_TX_BW_10
++} wl_tx_bw_t;
++
++
++/*
++ * Transmit modes.
++ * Not all modes are listed here, only those required for disambiguation. e.g. SPEXP is not listed
++ */
++typedef enum wl_tx_mode {
++	WL_TX_MODE_NONE,
++	WL_TX_MODE_STBC,
++	WL_TX_MODE_CDD,
++	WL_TX_MODE_TXBF,
++	WL_NUM_TX_MODES
++} wl_tx_mode_t;
++
++
++/* Number of transmit chains */
++typedef enum wl_tx_chains {
++	WL_TX_CHAINS_1 = 1,
++	WL_TX_CHAINS_2,
++	WL_TX_CHAINS_3,
++	WL_TX_CHAINS_4
++} wl_tx_chains_t;
++
++
++/* Number of transmit streams */
++typedef enum wl_tx_nss {
++	WL_TX_NSS_1 = 1,
++	WL_TX_NSS_2,
++	WL_TX_NSS_3,
++	WL_TX_NSS_4
++} wl_tx_nss_t;
++
++
++/* This enum maps each rate to a CLM index */
++
++typedef enum clm_rates {
++#ifdef WL_OLDPPR
++	/************
++	 * 1 chain  *
++	 ************
++	 */
++
++	CLM_RATE_1X1_DSSS_1			= 0,
++	CLM_RATE_1X1_DSSS_2			= 1,
++	CLM_RATE_1X1_DSSS_5_5		= 2,
++	CLM_RATE_1X1_DSSS_11		= 3,
++
++	CLM_RATE_1X1_OFDM_6			= 4,
++	CLM_RATE_1X1_OFDM_9			= 5,
++	CLM_RATE_1X1_OFDM_12		= 6,
++	CLM_RATE_1X1_OFDM_18		= 7,
++	CLM_RATE_1X1_OFDM_24		= 8,
++	CLM_RATE_1X1_OFDM_36		= 9,
++	CLM_RATE_1X1_OFDM_48		= 10,
++	CLM_RATE_1X1_OFDM_54		= 11,
++
++	CLM_RATE_1X1_MCS0			= 12,
++	CLM_RATE_1X1_MCS1			= 13,
++	CLM_RATE_1X1_MCS2			= 14,
++	CLM_RATE_1X1_MCS3			= 15,
++	CLM_RATE_1X1_MCS4			= 16,
++	CLM_RATE_1X1_MCS5			= 17,
++	CLM_RATE_1X1_MCS6			= 18,
++	CLM_RATE_1X1_MCS7			= 19,
++
++	/************
++	 * 2 chains *
++	 ************
++	 */
++
++	/* 1 Stream expanded + 1 */
++	CLM_RATE_1X2_DSSS_1			= 20,
++	CLM_RATE_1X2_DSSS_2			= 21,
++	CLM_RATE_1X2_DSSS_5_5		= 22,
++	CLM_RATE_1X2_DSSS_11		= 23,
++
++	CLM_RATE_1X2_CDD_OFDM_6		= 24,
++	CLM_RATE_1X2_CDD_OFDM_9		= 25,
++	CLM_RATE_1X2_CDD_OFDM_12	= 26,
++	CLM_RATE_1X2_CDD_OFDM_18	= 27,
++	CLM_RATE_1X2_CDD_OFDM_24	= 28,
++	CLM_RATE_1X2_CDD_OFDM_36	= 29,
++	CLM_RATE_1X2_CDD_OFDM_48	= 30,
++	CLM_RATE_1X2_CDD_OFDM_54	= 31,
++
++	CLM_RATE_1X2_CDD_MCS0		= 32,
++	CLM_RATE_1X2_CDD_MCS1		= 33,
++	CLM_RATE_1X2_CDD_MCS2		= 34,
++	CLM_RATE_1X2_CDD_MCS3		= 35,
++	CLM_RATE_1X2_CDD_MCS4		= 36,
++	CLM_RATE_1X2_CDD_MCS5		= 37,
++	CLM_RATE_1X2_CDD_MCS6		= 38,
++	CLM_RATE_1X2_CDD_MCS7		= 39,
++
++	/* 2 Streams */
++	CLM_RATE_2X2_STBC_MCS0		= 40,
++	CLM_RATE_2X2_STBC_MCS1		= 41,
++	CLM_RATE_2X2_STBC_MCS2		= 42,
++	CLM_RATE_2X2_STBC_MCS3		= 43,
++	CLM_RATE_2X2_STBC_MCS4		= 44,
++	CLM_RATE_2X2_STBC_MCS5		= 45,
++	CLM_RATE_2X2_STBC_MCS6		= 46,
++	CLM_RATE_2X2_STBC_MCS7		= 47,
++
++	CLM_RATE_2X2_SDM_MCS8		= 48,
++	CLM_RATE_2X2_SDM_MCS9		= 49,
++	CLM_RATE_2X2_SDM_MCS10		= 50,
++	CLM_RATE_2X2_SDM_MCS11		= 51,
++	CLM_RATE_2X2_SDM_MCS12		= 52,
++	CLM_RATE_2X2_SDM_MCS13		= 53,
++	CLM_RATE_2X2_SDM_MCS14		= 54,
++	CLM_RATE_2X2_SDM_MCS15		= 55,
++
++
++	/************
++	 * 3 chains *
++	 ************
++	 */
++
++	/* 1 Stream expanded + 2 */
++	CLM_RATE_1X3_DSSS_1			= 56,
++	CLM_RATE_1X3_DSSS_2			= 57,
++	CLM_RATE_1X3_DSSS_5_5		= 58,
++	CLM_RATE_1X3_DSSS_11		= 59,
++
++	CLM_RATE_1X3_CDD_OFDM_6		= 60,
++	CLM_RATE_1X3_CDD_OFDM_9		= 61,
++	CLM_RATE_1X3_CDD_OFDM_12	= 62,
++	CLM_RATE_1X3_CDD_OFDM_18	= 63,
++	CLM_RATE_1X3_CDD_OFDM_24	= 64,
++	CLM_RATE_1X3_CDD_OFDM_36	= 65,
++	CLM_RATE_1X3_CDD_OFDM_48	= 66,
++	CLM_RATE_1X3_CDD_OFDM_54	= 67,
++
++	CLM_RATE_1X3_CDD_MCS0		= 68,
++	CLM_RATE_1X3_CDD_MCS1		= 69,
++	CLM_RATE_1X3_CDD_MCS2		= 70,
++	CLM_RATE_1X3_CDD_MCS3		= 71,
++	CLM_RATE_1X3_CDD_MCS4		= 72,
++	CLM_RATE_1X3_CDD_MCS5		= 73,
++	CLM_RATE_1X3_CDD_MCS6		= 74,
++	CLM_RATE_1X3_CDD_MCS7		= 75,
++
++	/* 2 Streams expanded + 1 */
++	CLM_RATE_2X3_STBC_MCS0		= 76,
++	CLM_RATE_2X3_STBC_MCS1		= 77,
++	CLM_RATE_2X3_STBC_MCS2		= 78,
++	CLM_RATE_2X3_STBC_MCS3		= 79,
++	CLM_RATE_2X3_STBC_MCS4		= 80,
++	CLM_RATE_2X3_STBC_MCS5		= 81,
++	CLM_RATE_2X3_STBC_MCS6		= 82,
++	CLM_RATE_2X3_STBC_MCS7		= 83,
++
++	CLM_RATE_2X3_SDM_MCS8		= 84,
++	CLM_RATE_2X3_SDM_MCS9		= 85,
++	CLM_RATE_2X3_SDM_MCS10		= 86,
++	CLM_RATE_2X3_SDM_MCS11		= 87,
++	CLM_RATE_2X3_SDM_MCS12		= 88,
++	CLM_RATE_2X3_SDM_MCS13		= 89,
++	CLM_RATE_2X3_SDM_MCS14		= 90,
++	CLM_RATE_2X3_SDM_MCS15		= 91,
++
++	/* 3 Streams */
++	CLM_RATE_3X3_SDM_MCS16		= 92,
++	CLM_RATE_3X3_SDM_MCS17		= 93,
++	CLM_RATE_3X3_SDM_MCS18		= 94,
++	CLM_RATE_3X3_SDM_MCS19		= 95,
++	CLM_RATE_3X3_SDM_MCS20		= 96,
++	CLM_RATE_3X3_SDM_MCS21		= 97,
++	CLM_RATE_3X3_SDM_MCS22		= 98,
++	CLM_RATE_3X3_SDM_MCS23		= 99,
++#endif /* WL_OLDPPR */
++
++	/************
++	* 1 chain  *
++	************
++	*/
++
++	/* 1 Stream */
++	WL_RATE_1X1_DSSS_1            = 0,
++	WL_RATE_1X1_DSSS_2            = 1,
++	WL_RATE_1X1_DSSS_5_5          = 2,
++	WL_RATE_1X1_DSSS_11           = 3,
++
++	WL_RATE_1X1_OFDM_6            = 4,
++	WL_RATE_1X1_OFDM_9            = 5,
++	WL_RATE_1X1_OFDM_12           = 6,
++	WL_RATE_1X1_OFDM_18           = 7,
++	WL_RATE_1X1_OFDM_24           = 8,
++	WL_RATE_1X1_OFDM_36           = 9,
++	WL_RATE_1X1_OFDM_48           = 10,
++	WL_RATE_1X1_OFDM_54           = 11,
++
++	WL_RATE_1X1_MCS0              = 12,
++	WL_RATE_1X1_MCS1              = 13,
++	WL_RATE_1X1_MCS2              = 14,
++	WL_RATE_1X1_MCS3              = 15,
++	WL_RATE_1X1_MCS4              = 16,
++	WL_RATE_1X1_MCS5              = 17,
++	WL_RATE_1X1_MCS6              = 18,
++	WL_RATE_1X1_MCS7              = 19,
++	WL_RATE_P_1X1_MCS87           = 20,
++	WL_RATE_P_1X1_MCS88           = 21,
++
++	WL_RATE_1X1_VHT0SS1           = 12,
++	WL_RATE_1X1_VHT1SS1           = 13,
++	WL_RATE_1X1_VHT2SS1           = 14,
++	WL_RATE_1X1_VHT3SS1           = 15,
++	WL_RATE_1X1_VHT4SS1           = 16,
++	WL_RATE_1X1_VHT5SS1           = 17,
++	WL_RATE_1X1_VHT6SS1           = 18,
++	WL_RATE_1X1_VHT7SS1           = 19,
++	WL_RATE_1X1_VHT8SS1           = 20,
++	WL_RATE_1X1_VHT9SS1           = 21,
++	WL_RATE_P_1X1_VHT10SS1        = 22,
++	WL_RATE_P_1X1_VHT11SS1        = 23,
++
++
++	/************
++	* 2 chains *
++	************
++	*/
++
++	/* 1 Stream expanded + 1 */
++	WL_RATE_1X2_DSSS_1            = 24,
++	WL_RATE_1X2_DSSS_2            = 25,
++	WL_RATE_1X2_DSSS_5_5          = 26,
++	WL_RATE_1X2_DSSS_11           = 27,
++
++	WL_RATE_1X2_CDD_OFDM_6        = 28,
++	WL_RATE_1X2_CDD_OFDM_9        = 29,
++	WL_RATE_1X2_CDD_OFDM_12       = 30,
++	WL_RATE_1X2_CDD_OFDM_18       = 31,
++	WL_RATE_1X2_CDD_OFDM_24       = 32,
++	WL_RATE_1X2_CDD_OFDM_36       = 33,
++	WL_RATE_1X2_CDD_OFDM_48       = 34,
++	WL_RATE_1X2_CDD_OFDM_54       = 35,
++
++	WL_RATE_1X2_CDD_MCS0          = 36,
++	WL_RATE_1X2_CDD_MCS1          = 37,
++	WL_RATE_1X2_CDD_MCS2          = 38,
++	WL_RATE_1X2_CDD_MCS3          = 39,
++	WL_RATE_1X2_CDD_MCS4          = 40,
++	WL_RATE_1X2_CDD_MCS5          = 41,
++	WL_RATE_1X2_CDD_MCS6          = 42,
++	WL_RATE_1X2_CDD_MCS7          = 43,
++	WL_RATE_P_1X2_CDD_MCS87       = 44,
++	WL_RATE_P_1X2_CDD_MCS88       = 45,
++
++	WL_RATE_1X2_VHT0SS1           = 36,
++	WL_RATE_1X2_VHT1SS1           = 37,
++	WL_RATE_1X2_VHT2SS1           = 38,
++	WL_RATE_1X2_VHT3SS1           = 39,
++	WL_RATE_1X2_VHT4SS1           = 40,
++	WL_RATE_1X2_VHT5SS1           = 41,
++	WL_RATE_1X2_VHT6SS1           = 42,
++	WL_RATE_1X2_VHT7SS1           = 43,
++	WL_RATE_1X2_VHT8SS1           = 44,
++	WL_RATE_1X2_VHT9SS1           = 45,
++	WL_RATE_P_1X2_VHT10SS1        = 46,
++	WL_RATE_P_1X2_VHT11SS1        = 47,
++
++	/* 2 Streams */
++	WL_RATE_2X2_STBC_MCS0         = 48,
++	WL_RATE_2X2_STBC_MCS1         = 49,
++	WL_RATE_2X2_STBC_MCS2         = 50,
++	WL_RATE_2X2_STBC_MCS3         = 51,
++	WL_RATE_2X2_STBC_MCS4         = 52,
++	WL_RATE_2X2_STBC_MCS5         = 53,
++	WL_RATE_2X2_STBC_MCS6         = 54,
++	WL_RATE_2X2_STBC_MCS7         = 55,
++	WL_RATE_P_2X2_STBC_MCS87      = 56,
++	WL_RATE_P_2X2_STBC_MCS88      = 57,
++
++	WL_RATE_2X2_STBC_VHT0SS1      = 48,
++	WL_RATE_2X2_STBC_VHT1SS1      = 49,
++	WL_RATE_2X2_STBC_VHT2SS1      = 50,
++	WL_RATE_2X2_STBC_VHT3SS1      = 51,
++	WL_RATE_2X2_STBC_VHT4SS1      = 52,
++	WL_RATE_2X2_STBC_VHT5SS1      = 53,
++	WL_RATE_2X2_STBC_VHT6SS1      = 54,
++	WL_RATE_2X2_STBC_VHT7SS1      = 55,
++	WL_RATE_2X2_STBC_VHT8SS1      = 56,
++	WL_RATE_2X2_STBC_VHT9SS1      = 57,
++	WL_RATE_P_2X2_STBC_VHT10SS1   = 58,
++	WL_RATE_P_2X2_STBC_VHT11SS1   = 59,
++
++	WL_RATE_2X2_SDM_MCS8          = 60,
++	WL_RATE_2X2_SDM_MCS9          = 61,
++	WL_RATE_2X2_SDM_MCS10         = 62,
++	WL_RATE_2X2_SDM_MCS11         = 63,
++	WL_RATE_2X2_SDM_MCS12         = 64,
++	WL_RATE_2X2_SDM_MCS13         = 65,
++	WL_RATE_2X2_SDM_MCS14         = 66,
++	WL_RATE_2X2_SDM_MCS15         = 67,
++	WL_RATE_P_2X2_SDM_MCS99       = 68,
++	WL_RATE_P_2X2_SDM_MCS100      = 69,
++
++	WL_RATE_2X2_VHT0SS2           = 60,
++	WL_RATE_2X2_VHT1SS2           = 61,
++	WL_RATE_2X2_VHT2SS2           = 62,
++	WL_RATE_2X2_VHT3SS2           = 63,
++	WL_RATE_2X2_VHT4SS2           = 64,
++	WL_RATE_2X2_VHT5SS2           = 65,
++	WL_RATE_2X2_VHT6SS2           = 66,
++	WL_RATE_2X2_VHT7SS2           = 67,
++	WL_RATE_2X2_VHT8SS2           = 68,
++	WL_RATE_2X2_VHT9SS2           = 69,
++	WL_RATE_P_2X2_VHT10SS2        = 70,
++	WL_RATE_P_2X2_VHT11SS2        = 71,
++
++	/****************************
++	 * TX Beamforming, 2 chains *
++	 ****************************
++	 */
++
++	/* 1 Stream expanded + 1 */
++	WL_RATE_1X2_TXBF_OFDM_6       = 72,
++	WL_RATE_1X2_TXBF_OFDM_9       = 73,
++	WL_RATE_1X2_TXBF_OFDM_12      = 74,
++	WL_RATE_1X2_TXBF_OFDM_18      = 75,
++	WL_RATE_1X2_TXBF_OFDM_24      = 76,
++	WL_RATE_1X2_TXBF_OFDM_36      = 77,
++	WL_RATE_1X2_TXBF_OFDM_48      = 78,
++	WL_RATE_1X2_TXBF_OFDM_54      = 79,
++
++	WL_RATE_1X2_TXBF_MCS0         = 80,
++	WL_RATE_1X2_TXBF_MCS1         = 81,
++	WL_RATE_1X2_TXBF_MCS2         = 82,
++	WL_RATE_1X2_TXBF_MCS3         = 83,
++	WL_RATE_1X2_TXBF_MCS4         = 84,
++	WL_RATE_1X2_TXBF_MCS5         = 85,
++	WL_RATE_1X2_TXBF_MCS6         = 86,
++	WL_RATE_1X2_TXBF_MCS7         = 87,
++	WL_RATE_P_1X2_TXBF_MCS87      = 88,
++	WL_RATE_P_1X2_TXBF_MCS88      = 89,
++
++	WL_RATE_1X2_TXBF_VHT0SS1      = 80,
++	WL_RATE_1X2_TXBF_VHT1SS1      = 81,
++	WL_RATE_1X2_TXBF_VHT2SS1      = 82,
++	WL_RATE_1X2_TXBF_VHT3SS1      = 83,
++	WL_RATE_1X2_TXBF_VHT4SS1      = 84,
++	WL_RATE_1X2_TXBF_VHT5SS1      = 85,
++	WL_RATE_1X2_TXBF_VHT6SS1      = 86,
++	WL_RATE_1X2_TXBF_VHT7SS1      = 87,
++	WL_RATE_1X2_TXBF_VHT8SS1      = 88,
++	WL_RATE_1X2_TXBF_VHT9SS1      = 89,
++	WL_RATE_P_1X2_TXBF_VHT10SS1   = 90,
++	WL_RATE_P_1X2_TXBF_VHT11SS1   = 91,
++
++	/* 2 Streams */
++	WL_RATE_2X2_TXBF_SDM_MCS8     = 92,
++	WL_RATE_2X2_TXBF_SDM_MCS9     = 93,
++	WL_RATE_2X2_TXBF_SDM_MCS10    = 94,
++	WL_RATE_2X2_TXBF_SDM_MCS11    = 95,
++	WL_RATE_2X2_TXBF_SDM_MCS12    = 96,
++	WL_RATE_2X2_TXBF_SDM_MCS13    = 97,
++	WL_RATE_2X2_TXBF_SDM_MCS14    = 98,
++	WL_RATE_2X2_TXBF_SDM_MCS15    = 99,
++	WL_RATE_P_2X2_TXBF_SDM_MCS99  = 100,
++	WL_RATE_P_2X2_TXBF_SDM_MCS100 = 101,
++
++	WL_RATE_2X2_TXBF_VHT0SS2      = 92,
++	WL_RATE_2X2_TXBF_VHT1SS2      = 93,
++	WL_RATE_2X2_TXBF_VHT2SS2      = 94,
++	WL_RATE_2X2_TXBF_VHT3SS2      = 95,
++	WL_RATE_2X2_TXBF_VHT4SS2      = 96,
++	WL_RATE_2X2_TXBF_VHT5SS2      = 97,
++	WL_RATE_2X2_TXBF_VHT6SS2      = 98,
++	WL_RATE_2X2_TXBF_VHT7SS2      = 99,
++	WL_RATE_2X2_TXBF_VHT8SS2      = 100,
++	WL_RATE_2X2_TXBF_VHT9SS2      = 101,
++	WL_RATE_P_2X2_TXBF_VHT10SS2   = 102,
++	WL_RATE_P_2X2_TXBF_VHT11SS2   = 103,
++
++
++	/************
++	* 3 chains *
++	************
++	*/
++
++	/* 1 Stream expanded + 2 */
++	WL_RATE_1X3_DSSS_1            = 104,
++	WL_RATE_1X3_DSSS_2            = 105,
++	WL_RATE_1X3_DSSS_5_5          = 106,
++	WL_RATE_1X3_DSSS_11           = 107,
++
++	WL_RATE_1X3_CDD_OFDM_6        = 108,
++	WL_RATE_1X3_CDD_OFDM_9        = 109,
++	WL_RATE_1X3_CDD_OFDM_12       = 110,
++	WL_RATE_1X3_CDD_OFDM_18       = 111,
++	WL_RATE_1X3_CDD_OFDM_24       = 112,
++	WL_RATE_1X3_CDD_OFDM_36       = 113,
++	WL_RATE_1X3_CDD_OFDM_48       = 114,
++	WL_RATE_1X3_CDD_OFDM_54       = 115,
++
++	WL_RATE_1X3_CDD_MCS0          = 116,
++	WL_RATE_1X3_CDD_MCS1          = 117,
++	WL_RATE_1X3_CDD_MCS2          = 118,
++	WL_RATE_1X3_CDD_MCS3          = 119,
++	WL_RATE_1X3_CDD_MCS4          = 120,
++	WL_RATE_1X3_CDD_MCS5          = 121,
++	WL_RATE_1X3_CDD_MCS6          = 122,
++	WL_RATE_1X3_CDD_MCS7          = 123,
++	WL_RATE_P_1X3_CDD_MCS87       = 124,
++	WL_RATE_P_1X3_CDD_MCS88       = 125,
++
++	WL_RATE_1X3_VHT0SS1           = 116,
++	WL_RATE_1X3_VHT1SS1           = 117,
++	WL_RATE_1X3_VHT2SS1           = 118,
++	WL_RATE_1X3_VHT3SS1           = 119,
++	WL_RATE_1X3_VHT4SS1           = 120,
++	WL_RATE_1X3_VHT5SS1           = 121,
++	WL_RATE_1X3_VHT6SS1           = 122,
++	WL_RATE_1X3_VHT7SS1           = 123,
++	WL_RATE_1X3_VHT8SS1           = 124,
++	WL_RATE_1X3_VHT9SS1           = 125,
++	WL_RATE_P_1X3_VHT10SS1        = 126,
++	WL_RATE_P_1X3_VHT11SS1        = 127,
++
++	/* 2 Streams expanded + 1 */
++	WL_RATE_2X3_STBC_MCS0         = 128,
++	WL_RATE_2X3_STBC_MCS1         = 129,
++	WL_RATE_2X3_STBC_MCS2         = 130,
++	WL_RATE_2X3_STBC_MCS3         = 131,
++	WL_RATE_2X3_STBC_MCS4         = 132,
++	WL_RATE_2X3_STBC_MCS5         = 133,
++	WL_RATE_2X3_STBC_MCS6         = 134,
++	WL_RATE_2X3_STBC_MCS7         = 135,
++	WL_RATE_P_2X3_STBC_MCS87      = 136,
++	WL_RATE_P_2X3_STBC_MCS88      = 137,
++
++	WL_RATE_2X3_STBC_VHT0SS1      = 128,
++	WL_RATE_2X3_STBC_VHT1SS1      = 129,
++	WL_RATE_2X3_STBC_VHT2SS1      = 130,
++	WL_RATE_2X3_STBC_VHT3SS1      = 131,
++	WL_RATE_2X3_STBC_VHT4SS1      = 132,
++	WL_RATE_2X3_STBC_VHT5SS1      = 133,
++	WL_RATE_2X3_STBC_VHT6SS1      = 134,
++	WL_RATE_2X3_STBC_VHT7SS1      = 135,
++	WL_RATE_2X3_STBC_VHT8SS1      = 136,
++	WL_RATE_2X3_STBC_VHT9SS1      = 137,
++	WL_RATE_P_2X3_STBC_VHT10SS1   = 138,
++	WL_RATE_P_2X3_STBC_VHT11SS1   = 139,
++
++	WL_RATE_2X3_SDM_MCS8          = 140,
++	WL_RATE_2X3_SDM_MCS9          = 141,
++	WL_RATE_2X3_SDM_MCS10         = 142,
++	WL_RATE_2X3_SDM_MCS11         = 143,
++	WL_RATE_2X3_SDM_MCS12         = 144,
++	WL_RATE_2X3_SDM_MCS13         = 145,
++	WL_RATE_2X3_SDM_MCS14         = 146,
++	WL_RATE_2X3_SDM_MCS15         = 147,
++	WL_RATE_P_2X3_SDM_MCS99       = 148,
++	WL_RATE_P_2X3_SDM_MCS100      = 149,
++
++	WL_RATE_2X3_VHT0SS2           = 140,
++	WL_RATE_2X3_VHT1SS2           = 141,
++	WL_RATE_2X3_VHT2SS2           = 142,
++	WL_RATE_2X3_VHT3SS2           = 143,
++	WL_RATE_2X3_VHT4SS2           = 144,
++	WL_RATE_2X3_VHT5SS2           = 145,
++	WL_RATE_2X3_VHT6SS2           = 146,
++	WL_RATE_2X3_VHT7SS2           = 147,
++	WL_RATE_2X3_VHT8SS2           = 148,
++	WL_RATE_2X3_VHT9SS2           = 149,
++	WL_RATE_P_2X3_VHT10SS2        = 150,
++	WL_RATE_P_2X3_VHT11SS2        = 151,
++
++	/* 3 Streams */
++	WL_RATE_3X3_SDM_MCS16         = 152,
++	WL_RATE_3X3_SDM_MCS17         = 153,
++	WL_RATE_3X3_SDM_MCS18         = 154,
++	WL_RATE_3X3_SDM_MCS19         = 155,
++	WL_RATE_3X3_SDM_MCS20         = 156,
++	WL_RATE_3X3_SDM_MCS21         = 157,
++	WL_RATE_3X3_SDM_MCS22         = 158,
++	WL_RATE_3X3_SDM_MCS23         = 159,
++	WL_RATE_P_3X3_SDM_MCS101      = 160,
++	WL_RATE_P_3X3_SDM_MCS102      = 161,
++
++	WL_RATE_3X3_VHT0SS3           = 152,
++	WL_RATE_3X3_VHT1SS3           = 153,
++	WL_RATE_3X3_VHT2SS3           = 154,
++	WL_RATE_3X3_VHT3SS3           = 155,
++	WL_RATE_3X3_VHT4SS3           = 156,
++	WL_RATE_3X3_VHT5SS3           = 157,
++	WL_RATE_3X3_VHT6SS3           = 158,
++	WL_RATE_3X3_VHT7SS3           = 159,
++	WL_RATE_3X3_VHT8SS3           = 160,
++	WL_RATE_3X3_VHT9SS3           = 161,
++	WL_RATE_P_3X3_VHT10SS3        = 162,
++	WL_RATE_P_3X3_VHT11SS3        = 163,
++
++
++	/****************************
++	 * TX Beamforming, 3 chains *
++	 ****************************
++	 */
++
++	/* 1 Stream expanded + 2 */
++	WL_RATE_1X3_TXBF_OFDM_6       = 164,
++	WL_RATE_1X3_TXBF_OFDM_9       = 165,
++	WL_RATE_1X3_TXBF_OFDM_12      = 166,
++	WL_RATE_1X3_TXBF_OFDM_18      = 167,
++	WL_RATE_1X3_TXBF_OFDM_24      = 168,
++	WL_RATE_1X3_TXBF_OFDM_36      = 169,
++	WL_RATE_1X3_TXBF_OFDM_48      = 170,
++	WL_RATE_1X3_TXBF_OFDM_54      = 171,
++
++	WL_RATE_1X3_TXBF_MCS0         = 172,
++	WL_RATE_1X3_TXBF_MCS1         = 173,
++	WL_RATE_1X3_TXBF_MCS2         = 174,
++	WL_RATE_1X3_TXBF_MCS3         = 175,
++	WL_RATE_1X3_TXBF_MCS4         = 176,
++	WL_RATE_1X3_TXBF_MCS5         = 177,
++	WL_RATE_1X3_TXBF_MCS6         = 178,
++	WL_RATE_1X3_TXBF_MCS7         = 179,
++	WL_RATE_P_1X3_TXBF_MCS87      = 180,
++	WL_RATE_P_1X3_TXBF_MCS88      = 181,
++
++	WL_RATE_1X3_TXBF_VHT0SS1      = 172,
++	WL_RATE_1X3_TXBF_VHT1SS1      = 173,
++	WL_RATE_1X3_TXBF_VHT2SS1      = 174,
++	WL_RATE_1X3_TXBF_VHT3SS1      = 175,
++	WL_RATE_1X3_TXBF_VHT4SS1      = 176,
++	WL_RATE_1X3_TXBF_VHT5SS1      = 177,
++	WL_RATE_1X3_TXBF_VHT6SS1      = 178,
++	WL_RATE_1X3_TXBF_VHT7SS1      = 179,
++	WL_RATE_1X3_TXBF_VHT8SS1      = 180,
++	WL_RATE_1X3_TXBF_VHT9SS1      = 181,
++	WL_RATE_P_1X3_TXBF_VHT10SS1   = 182,
++	WL_RATE_P_1X3_TXBF_VHT11SS1   = 183,
++
++	/* 2 Streams expanded + 1 */
++	WL_RATE_2X3_TXBF_SDM_MCS8     = 184,
++	WL_RATE_2X3_TXBF_SDM_MCS9     = 185,
++	WL_RATE_2X3_TXBF_SDM_MCS10    = 186,
++	WL_RATE_2X3_TXBF_SDM_MCS11    = 187,
++	WL_RATE_2X3_TXBF_SDM_MCS12    = 188,
++	WL_RATE_2X3_TXBF_SDM_MCS13    = 189,
++	WL_RATE_2X3_TXBF_SDM_MCS14    = 190,
++	WL_RATE_2X3_TXBF_SDM_MCS15    = 191,
++	WL_RATE_P_2X3_TXBF_SDM_MCS99  = 192,
++	WL_RATE_P_2X3_TXBF_SDM_MCS100 = 193,
++
++	WL_RATE_2X3_TXBF_VHT0SS2      = 184,
++	WL_RATE_2X3_TXBF_VHT1SS2      = 185,
++	WL_RATE_2X3_TXBF_VHT2SS2      = 186,
++	WL_RATE_2X3_TXBF_VHT3SS2      = 187,
++	WL_RATE_2X3_TXBF_VHT4SS2      = 188,
++	WL_RATE_2X3_TXBF_VHT5SS2      = 189,
++	WL_RATE_2X3_TXBF_VHT6SS2      = 190,
++	WL_RATE_2X3_TXBF_VHT7SS2      = 191,
++	WL_RATE_2X3_TXBF_VHT8SS2      = 192,
++	WL_RATE_2X3_TXBF_VHT9SS2      = 193,
++	WL_RATE_P_2X3_TXBF_VHT10SS2   = 194,
++	WL_RATE_P_2X3_TXBF_VHT11SS2   = 195,
++
++	/* 3 Streams */
++	WL_RATE_3X3_TXBF_SDM_MCS16    = 196,
++	WL_RATE_3X3_TXBF_SDM_MCS17    = 197,
++	WL_RATE_3X3_TXBF_SDM_MCS18    = 198,
++	WL_RATE_3X3_TXBF_SDM_MCS19    = 199,
++	WL_RATE_3X3_TXBF_SDM_MCS20    = 200,
++	WL_RATE_3X3_TXBF_SDM_MCS21    = 201,
++	WL_RATE_3X3_TXBF_SDM_MCS22    = 202,
++	WL_RATE_3X3_TXBF_SDM_MCS23    = 203,
++	WL_RATE_P_3X3_TXBF_SDM_MCS101 = 204,
++	WL_RATE_P_3X3_TXBF_SDM_MCS102 = 205,
++
++	WL_RATE_3X3_TXBF_VHT0SS3      = 196,
++	WL_RATE_3X3_TXBF_VHT1SS3      = 197,
++	WL_RATE_3X3_TXBF_VHT2SS3      = 198,
++	WL_RATE_3X3_TXBF_VHT3SS3      = 199,
++	WL_RATE_3X3_TXBF_VHT4SS3      = 200,
++	WL_RATE_3X3_TXBF_VHT5SS3      = 201,
++	WL_RATE_3X3_TXBF_VHT6SS3      = 202,
++	WL_RATE_3X3_TXBF_VHT7SS3      = 203,
++	WL_RATE_3X3_TXBF_VHT8SS3      = 204,
++	WL_RATE_3X3_TXBF_VHT9SS3      = 205,
++	WL_RATE_P_3X3_TXBF_VHT10SS3   = 206,
++	WL_RATE_P_3X3_TXBF_VHT11SS3   = 207,
++
++
++	/************
++	* 4 chains *
++	************
++	*/
++
++	/* 1 Stream expanded + 3 */
++	WL_RATE_1X4_DSSS_1            = 208,
++	WL_RATE_1X4_DSSS_2            = 209,
++	WL_RATE_1X4_DSSS_5_5          = 210,
++	WL_RATE_1X4_DSSS_11           = 211,
++
++	WL_RATE_1X4_CDD_OFDM_6        = 212,
++	WL_RATE_1X4_CDD_OFDM_9        = 213,
++	WL_RATE_1X4_CDD_OFDM_12       = 214,
++	WL_RATE_1X4_CDD_OFDM_18       = 215,
++	WL_RATE_1X4_CDD_OFDM_24       = 216,
++	WL_RATE_1X4_CDD_OFDM_36       = 217,
++	WL_RATE_1X4_CDD_OFDM_48       = 218,
++	WL_RATE_1X4_CDD_OFDM_54       = 219,
++
++	WL_RATE_1X4_CDD_MCS0          = 220,
++	WL_RATE_1X4_CDD_MCS1          = 221,
++	WL_RATE_1X4_CDD_MCS2          = 222,
++	WL_RATE_1X4_CDD_MCS3          = 223,
++	WL_RATE_1X4_CDD_MCS4          = 224,
++	WL_RATE_1X4_CDD_MCS5          = 225,
++	WL_RATE_1X4_CDD_MCS6          = 226,
++	WL_RATE_1X4_CDD_MCS7          = 227,
++	WL_RATE_P_1X4_CDD_MCS87       = 228,
++	WL_RATE_P_1X4_CDD_MCS88       = 229,
++
++	WL_RATE_1X4_VHT0SS1           = 220,
++	WL_RATE_1X4_VHT1SS1           = 221,
++	WL_RATE_1X4_VHT2SS1           = 222,
++	WL_RATE_1X4_VHT3SS1           = 223,
++	WL_RATE_1X4_VHT4SS1           = 224,
++	WL_RATE_1X4_VHT5SS1           = 225,
++	WL_RATE_1X4_VHT6SS1           = 226,
++	WL_RATE_1X4_VHT7SS1           = 227,
++	WL_RATE_1X4_VHT8SS1           = 228,
++	WL_RATE_1X4_VHT9SS1           = 229,
++	WL_RATE_P_1X4_VHT10SS1        = 230,
++	WL_RATE_P_1X4_VHT11SS1        = 231,
++
++	/* 2 Streams expanded + 2 */
++	WL_RATE_2X4_STBC_MCS0         = 232,
++	WL_RATE_2X4_STBC_MCS1         = 233,
++	WL_RATE_2X4_STBC_MCS2         = 234,
++	WL_RATE_2X4_STBC_MCS3         = 235,
++	WL_RATE_2X4_STBC_MCS4         = 236,
++	WL_RATE_2X4_STBC_MCS5         = 237,
++	WL_RATE_2X4_STBC_MCS6         = 238,
++	WL_RATE_2X4_STBC_MCS7         = 239,
++	WL_RATE_P_2X4_STBC_MCS87      = 240,
++	WL_RATE_P_2X4_STBC_MCS88      = 241,
++
++	WL_RATE_2X4_STBC_VHT0SS1      = 232,
++	WL_RATE_2X4_STBC_VHT1SS1      = 233,
++	WL_RATE_2X4_STBC_VHT2SS1      = 234,
++	WL_RATE_2X4_STBC_VHT3SS1      = 235,
++	WL_RATE_2X4_STBC_VHT4SS1      = 236,
++	WL_RATE_2X4_STBC_VHT5SS1      = 237,
++	WL_RATE_2X4_STBC_VHT6SS1      = 238,
++	WL_RATE_2X4_STBC_VHT7SS1      = 239,
++	WL_RATE_2X4_STBC_VHT8SS1      = 240,
++	WL_RATE_2X4_STBC_VHT9SS1      = 241,
++	WL_RATE_P_2X4_STBC_VHT10SS1   = 242,
++	WL_RATE_P_2X4_STBC_VHT11SS1   = 243,
++
++	WL_RATE_2X4_SDM_MCS8          = 244,
++	WL_RATE_2X4_SDM_MCS9          = 245,
++	WL_RATE_2X4_SDM_MCS10         = 246,
++	WL_RATE_2X4_SDM_MCS11         = 247,
++	WL_RATE_2X4_SDM_MCS12         = 248,
++	WL_RATE_2X4_SDM_MCS13         = 249,
++	WL_RATE_2X4_SDM_MCS14         = 250,
++	WL_RATE_2X4_SDM_MCS15         = 251,
++	WL_RATE_P_2X4_SDM_MCS99       = 252,
++	WL_RATE_P_2X4_SDM_MCS100      = 253,
++
++	WL_RATE_2X4_VHT0SS2           = 244,
++	WL_RATE_2X4_VHT1SS2           = 245,
++	WL_RATE_2X4_VHT2SS2           = 246,
++	WL_RATE_2X4_VHT3SS2           = 247,
++	WL_RATE_2X4_VHT4SS2           = 248,
++	WL_RATE_2X4_VHT5SS2           = 249,
++	WL_RATE_2X4_VHT6SS2           = 250,
++	WL_RATE_2X4_VHT7SS2           = 251,
++	WL_RATE_2X4_VHT8SS2           = 252,
++	WL_RATE_2X4_VHT9SS2           = 253,
++	WL_RATE_P_2X4_VHT10SS2        = 254,
++	WL_RATE_P_2X4_VHT11SS2        = 255,
++
++	/* 3 Streams expanded + 1 */
++	WL_RATE_3X4_SDM_MCS16         = 256,
++	WL_RATE_3X4_SDM_MCS17         = 257,
++	WL_RATE_3X4_SDM_MCS18         = 258,
++	WL_RATE_3X4_SDM_MCS19         = 259,
++	WL_RATE_3X4_SDM_MCS20         = 260,
++	WL_RATE_3X4_SDM_MCS21         = 261,
++	WL_RATE_3X4_SDM_MCS22         = 262,
++	WL_RATE_3X4_SDM_MCS23         = 263,
++	WL_RATE_P_3X4_SDM_MCS101      = 264,
++	WL_RATE_P_3X4_SDM_MCS102      = 265,
++
++	WL_RATE_3X4_VHT0SS3           = 256,
++	WL_RATE_3X4_VHT1SS3           = 257,
++	WL_RATE_3X4_VHT2SS3           = 258,
++	WL_RATE_3X4_VHT3SS3           = 259,
++	WL_RATE_3X4_VHT4SS3           = 260,
++	WL_RATE_3X4_VHT5SS3           = 261,
++	WL_RATE_3X4_VHT6SS3           = 262,
++	WL_RATE_3X4_VHT7SS3           = 263,
++	WL_RATE_3X4_VHT8SS3           = 264,
++	WL_RATE_3X4_VHT9SS3           = 265,
++	WL_RATE_P_3X4_VHT10SS3        = 266,
++	WL_RATE_P_3X4_VHT11SS3        = 267,
++
++
++	/* 4 Streams */
++	WL_RATE_4X4_SDM_MCS24         = 268,
++	WL_RATE_4X4_SDM_MCS25         = 269,
++	WL_RATE_4X4_SDM_MCS26         = 270,
++	WL_RATE_4X4_SDM_MCS27         = 271,
++	WL_RATE_4X4_SDM_MCS28         = 272,
++	WL_RATE_4X4_SDM_MCS29         = 273,
++	WL_RATE_4X4_SDM_MCS30         = 274,
++	WL_RATE_4X4_SDM_MCS31         = 275,
++	WL_RATE_P_4X4_SDM_MCS103      = 276,
++	WL_RATE_P_4X4_SDM_MCS104      = 277,
++
++	WL_RATE_4X4_VHT0SS4           = 268,
++	WL_RATE_4X4_VHT1SS4           = 269,
++	WL_RATE_4X4_VHT2SS4           = 270,
++	WL_RATE_4X4_VHT3SS4           = 271,
++	WL_RATE_4X4_VHT4SS4           = 272,
++	WL_RATE_4X4_VHT5SS4           = 273,
++	WL_RATE_4X4_VHT6SS4           = 274,
++	WL_RATE_4X4_VHT7SS4           = 275,
++	WL_RATE_4X4_VHT8SS4           = 276,
++	WL_RATE_4X4_VHT9SS4           = 277,
++	WL_RATE_P_4X4_VHT10SS4        = 278,
++	WL_RATE_P_4X4_VHT11SS4        = 279,
++
++
++	/****************************
++	 * TX Beamforming, 4 chains *
++	 ****************************
++	 */
++
++	/* 1 Stream expanded + 3 */
++	WL_RATE_1X4_TXBF_OFDM_6       = 280,
++	WL_RATE_1X4_TXBF_OFDM_9       = 281,
++	WL_RATE_1X4_TXBF_OFDM_12      = 282,
++	WL_RATE_1X4_TXBF_OFDM_18      = 283,
++	WL_RATE_1X4_TXBF_OFDM_24      = 284,
++	WL_RATE_1X4_TXBF_OFDM_36      = 285,
++	WL_RATE_1X4_TXBF_OFDM_48      = 286,
++	WL_RATE_1X4_TXBF_OFDM_54      = 287,
++
++	WL_RATE_1X4_TXBF_MCS0         = 288,
++	WL_RATE_1X4_TXBF_MCS1         = 289,
++	WL_RATE_1X4_TXBF_MCS2         = 290,
++	WL_RATE_1X4_TXBF_MCS3         = 291,
++	WL_RATE_1X4_TXBF_MCS4         = 292,
++	WL_RATE_1X4_TXBF_MCS5         = 293,
++	WL_RATE_1X4_TXBF_MCS6         = 294,
++	WL_RATE_1X4_TXBF_MCS7         = 295,
++	WL_RATE_P_1X4_TXBF_MCS87      = 296,
++	WL_RATE_P_1X4_TXBF_MCS88      = 297,
++
++	WL_RATE_1X4_TXBF_VHT0SS1      = 288,
++	WL_RATE_1X4_TXBF_VHT1SS1      = 289,
++	WL_RATE_1X4_TXBF_VHT2SS1      = 290,
++	WL_RATE_1X4_TXBF_VHT3SS1      = 291,
++	WL_RATE_1X4_TXBF_VHT4SS1      = 292,
++	WL_RATE_1X4_TXBF_VHT5SS1      = 293,
++	WL_RATE_1X4_TXBF_VHT6SS1      = 294,
++	WL_RATE_1X4_TXBF_VHT7SS1      = 295,
++	WL_RATE_1X4_TXBF_VHT8SS1      = 296,
++	WL_RATE_1X4_TXBF_VHT9SS1      = 297,
++	WL_RATE_P_1X4_TXBF_VHT10SS1   = 298,
++	WL_RATE_P_1X4_TXBF_VHT11SS1   = 299,
++
++	/* 2 Streams expanded + 2 */
++	WL_RATE_2X4_TXBF_SDM_MCS8     = 300,
++	WL_RATE_2X4_TXBF_SDM_MCS9     = 301,
++	WL_RATE_2X4_TXBF_SDM_MCS10    = 302,
++	WL_RATE_2X4_TXBF_SDM_MCS11    = 303,
++	WL_RATE_2X4_TXBF_SDM_MCS12    = 304,
++	WL_RATE_2X4_TXBF_SDM_MCS13    = 305,
++	WL_RATE_2X4_TXBF_SDM_MCS14    = 306,
++	WL_RATE_2X4_TXBF_SDM_MCS15    = 307,
++	WL_RATE_P_2X4_TXBF_SDM_MCS99  = 308,
++	WL_RATE_P_2X4_TXBF_SDM_MCS100 = 309,
++
++	WL_RATE_2X4_TXBF_VHT0SS2      = 300,
++	WL_RATE_2X4_TXBF_VHT1SS2      = 301,
++	WL_RATE_2X4_TXBF_VHT2SS2      = 302,
++	WL_RATE_2X4_TXBF_VHT3SS2      = 303,
++	WL_RATE_2X4_TXBF_VHT4SS2      = 304,
++	WL_RATE_2X4_TXBF_VHT5SS2      = 305,
++	WL_RATE_2X4_TXBF_VHT6SS2      = 306,
++	WL_RATE_2X4_TXBF_VHT7SS2      = 307,
++	WL_RATE_2X4_TXBF_VHT8SS2      = 308,
++	WL_RATE_2X4_TXBF_VHT9SS2      = 309,
++	WL_RATE_P_2X4_TXBF_VHT10SS2   = 310,
++	WL_RATE_P_2X4_TXBF_VHT11SS2   = 311,
++
++	/* 3 Streams expanded + 1 */
++	WL_RATE_3X4_TXBF_SDM_MCS16    = 312,
++	WL_RATE_3X4_TXBF_SDM_MCS17    = 313,
++	WL_RATE_3X4_TXBF_SDM_MCS18    = 314,
++	WL_RATE_3X4_TXBF_SDM_MCS19    = 315,
++	WL_RATE_3X4_TXBF_SDM_MCS20    = 316,
++	WL_RATE_3X4_TXBF_SDM_MCS21    = 317,
++	WL_RATE_3X4_TXBF_SDM_MCS22    = 318,
++	WL_RATE_3X4_TXBF_SDM_MCS23    = 319,
++	WL_RATE_P_3X4_TXBF_SDM_MCS101 = 320,
++	WL_RATE_P_3X4_TXBF_SDM_MCS102 = 321,
++
++	WL_RATE_3X4_TXBF_VHT0SS3      = 312,
++	WL_RATE_3X4_TXBF_VHT1SS3      = 313,
++	WL_RATE_3X4_TXBF_VHT2SS3      = 314,
++	WL_RATE_3X4_TXBF_VHT3SS3      = 315,
++	WL_RATE_3X4_TXBF_VHT4SS3      = 316,
++	WL_RATE_3X4_TXBF_VHT5SS3      = 317,
++	WL_RATE_3X4_TXBF_VHT6SS3      = 318,
++	WL_RATE_3X4_TXBF_VHT7SS3      = 319,
++	WL_RATE_P_3X4_TXBF_VHT8SS3    = 320,
++	WL_RATE_P_3X4_TXBF_VHT9SS3    = 321,
++	WL_RATE_P_3X4_TXBF_VHT10SS3   = 322,
++	WL_RATE_P_3X4_TXBF_VHT11SS3   = 323,
++
++	/* 4 Streams */
++	WL_RATE_4X4_TXBF_SDM_MCS24    = 324,
++	WL_RATE_4X4_TXBF_SDM_MCS25    = 325,
++	WL_RATE_4X4_TXBF_SDM_MCS26    = 326,
++	WL_RATE_4X4_TXBF_SDM_MCS27    = 327,
++	WL_RATE_4X4_TXBF_SDM_MCS28    = 328,
++	WL_RATE_4X4_TXBF_SDM_MCS29    = 329,
++	WL_RATE_4X4_TXBF_SDM_MCS30    = 330,
++	WL_RATE_4X4_TXBF_SDM_MCS31    = 331,
++	WL_RATE_P_4X4_TXBF_SDM_MCS103 = 332,
++	WL_RATE_P_4X4_TXBF_SDM_MCS104 = 333,
++
++	WL_RATE_4X4_TXBF_VHT0SS4      = 324,
++	WL_RATE_4X4_TXBF_VHT1SS4      = 325,
++	WL_RATE_4X4_TXBF_VHT2SS4      = 326,
++	WL_RATE_4X4_TXBF_VHT3SS4      = 327,
++	WL_RATE_4X4_TXBF_VHT4SS4      = 328,
++	WL_RATE_4X4_TXBF_VHT5SS4      = 329,
++	WL_RATE_4X4_TXBF_VHT6SS4      = 330,
++	WL_RATE_4X4_TXBF_VHT7SS4      = 331,
++	WL_RATE_P_4X4_TXBF_VHT8SS4    = 332,
++	WL_RATE_P_4X4_TXBF_VHT9SS4    = 333,
++	WL_RATE_P_4X4_TXBF_VHT10SS4   = 334,
++	WL_RATE_P_4X4_TXBF_VHT11SS4   = 335
++
++} clm_rates_t;
++
++/* Number of rate codes */
++#define WL_NUMRATES 336
++
++#ifdef __cplusplus
++}
++#endif /* __cplusplus */
++
++#endif /* _bcmwifi_rates_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmxtlv.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmxtlv.c
+new file mode 100644
+index 000000000..ef858708f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/bcmxtlv.c
+@@ -0,0 +1,461 @@
++/*
++ * Driver O/S-independent utility routines
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: bcmxtlv.c 603083 2015-11-30 23:40:43Z $
++ */
++
++#include <bcm_cfg.h>
++
++#include <typedefs.h>
++#include <bcmdefs.h>
++
++#include <stdarg.h>
++
++#ifdef BCMDRIVER
++#include <osl.h>
++#else /* !BCMDRIVER */
++	#include <stdlib.h> /* AS!!! */
++#include <stdio.h>
++#include <string.h>
++#include <stdlib.h>
++#ifndef ASSERT
++#define ASSERT(exp)
++#endif
++INLINE void* MALLOCZ(void *o, size_t s) { BCM_REFERENCE(o); return calloc(1, s); }
++INLINE void MFREE(void *o, void *p, size_t s) { BCM_REFERENCE(o); BCM_REFERENCE(s); free(p); }
++#endif /* !BCMDRIVER */
++
++#include <bcmendian.h>
++#include <bcmutils.h>
++
++static INLINE int bcm_xtlv_size_for_data(int dlen, bcm_xtlv_opts_t opts)
++{
++	return ((opts & BCM_XTLV_OPTION_ALIGN32) ? ALIGN_SIZE(dlen + BCM_XTLV_HDR_SIZE, 4)
++		: (dlen + BCM_XTLV_HDR_SIZE));
++}
++
++bcm_xtlv_t *
++bcm_next_xtlv(bcm_xtlv_t *elt, int *buflen, bcm_xtlv_opts_t opts)
++{
++	int sz;
++	/* advance to next elt */
++	sz = BCM_XTLV_SIZE(elt, opts);
++	elt = (bcm_xtlv_t*)((uint8 *)elt + sz);
++	*buflen -= sz;
++
++	/* validate next elt */
++	if (!bcm_valid_xtlv(elt, *buflen, opts))
++		return NULL;
++
++	return elt;
++}
++
++int
++bcm_xtlv_buf_init(bcm_xtlvbuf_t *tlv_buf, uint8 *buf, uint16 len, bcm_xtlv_opts_t opts)
++{
++	if (!tlv_buf || !buf || !len)
++		return BCME_BADARG;
++
++	tlv_buf->opts = opts;
++	tlv_buf->size = len;
++	tlv_buf->head = buf;
++	tlv_buf->buf  = buf;
++	return BCME_OK;
++}
++
++uint16
++bcm_xtlv_buf_len(bcm_xtlvbuf_t *tbuf)
++{
++	if (tbuf == NULL) return 0;
++	return (uint16)(tbuf->buf - tbuf->head);
++}
++uint16
++bcm_xtlv_buf_rlen(bcm_xtlvbuf_t *tbuf)
++{
++	if (tbuf == NULL) return 0;
++	return tbuf->size - bcm_xtlv_buf_len(tbuf);
++}
++uint8 *
++bcm_xtlv_buf(bcm_xtlvbuf_t *tbuf)
++{
++	if (tbuf == NULL) return NULL;
++	return tbuf->buf;
++}
++uint8 *
++bcm_xtlv_head(bcm_xtlvbuf_t *tbuf)
++{
++	if (tbuf == NULL) return NULL;
++	return tbuf->head;
++}
++int
++bcm_xtlv_put_data(bcm_xtlvbuf_t *tbuf, uint16 type, const void *data, uint16 dlen)
++{
++	bcm_xtlv_t *xtlv;
++	int size;
++
++	if (tbuf == NULL)
++		return BCME_BADARG;
++	size = bcm_xtlv_size_for_data(dlen, tbuf->opts);
++	if (bcm_xtlv_buf_rlen(tbuf) < size)
++		return BCME_NOMEM;
++	xtlv = (bcm_xtlv_t *)bcm_xtlv_buf(tbuf);
++	xtlv->id = htol16(type);
++	xtlv->len = htol16(dlen);
++	memcpy(xtlv->data, data, dlen);
++	tbuf->buf += size;
++	return BCME_OK;
++}
++int
++bcm_xtlv_put_8(bcm_xtlvbuf_t *tbuf, uint16 type, const int8 data)
++{
++	bcm_xtlv_t *xtlv;
++	int size;
++
++	if (tbuf == NULL)
++		return BCME_BADARG;
++	size = bcm_xtlv_size_for_data(1, tbuf->opts);
++	if (bcm_xtlv_buf_rlen(tbuf) < size)
++		return BCME_NOMEM;
++	xtlv = (bcm_xtlv_t *)bcm_xtlv_buf(tbuf);
++	xtlv->id = htol16(type);
++	xtlv->len = htol16(sizeof(data));
++	xtlv->data[0] = data;
++	tbuf->buf += size;
++	return BCME_OK;
++}
++int
++bcm_xtlv_put_16(bcm_xtlvbuf_t *tbuf, uint16 type, const int16 data)
++{
++	bcm_xtlv_t *xtlv;
++	int size;
++
++	if (tbuf == NULL)
++		return BCME_BADARG;
++	size = bcm_xtlv_size_for_data(2, tbuf->opts);
++	if (bcm_xtlv_buf_rlen(tbuf) < size)
++		return BCME_NOMEM;
++
++	xtlv = (bcm_xtlv_t *)bcm_xtlv_buf(tbuf);
++	xtlv->id = htol16(type);
++	xtlv->len = htol16(sizeof(data));
++	htol16_ua_store(data, xtlv->data);
++	tbuf->buf += size;
++	return BCME_OK;
++}
++int
++bcm_xtlv_put_32(bcm_xtlvbuf_t *tbuf, uint16 type, const int32 data)
++{
++	bcm_xtlv_t *xtlv;
++	int size;
++
++	if (tbuf == NULL)
++		return BCME_BADARG;
++	size = bcm_xtlv_size_for_data(4, tbuf->opts);
++	if (bcm_xtlv_buf_rlen(tbuf) < size)
++		return BCME_NOMEM;
++	xtlv = (bcm_xtlv_t *)bcm_xtlv_buf(tbuf);
++	xtlv->id = htol16(type);
++	xtlv->len = htol16(sizeof(data));
++	htol32_ua_store(data, xtlv->data);
++	tbuf->buf += size;
++	return BCME_OK;
++}
++
++/*
++ *  upacks xtlv record from buf checks the type
++ *  copies data to callers buffer
++ *  advances tlv pointer to next record
++ *  caller's resposible for dst space check
++ */
++int
++bcm_unpack_xtlv_entry(uint8 **tlv_buf, uint16 xpct_type, uint16 xpct_len, void *dst,
++	bcm_xtlv_opts_t opts)
++{
++	bcm_xtlv_t *ptlv = (bcm_xtlv_t *)*tlv_buf;
++	uint16 len;
++	uint16 type;
++
++	ASSERT(ptlv);
++	/* tlv headr is always packed in LE order */
++	len = ltoh16(ptlv->len);
++	type = ltoh16(ptlv->id);
++	if	(len == 0) {
++		/* z-len tlv headers: allow, but don't process */
++		printf("z-len, skip unpack\n");
++	} else  {
++		if ((type != xpct_type) ||
++			(len > xpct_len)) {
++			printf("xtlv_unpack Error: found[type:%d,len:%d] != xpct[type:%d,len:%d]\n",
++				type, len, xpct_type, xpct_len);
++			return BCME_BADARG;
++		}
++		/* copy tlv record to caller's buffer */
++		memcpy(dst, ptlv->data, ptlv->len);
++	}
++	*tlv_buf += BCM_XTLV_SIZE(ptlv, opts);
++	return BCME_OK;
++}
++
++/*
++ *  packs user data into tlv record
++ *  advances tlv pointer to next xtlv slot
++ *  buflen is used for tlv_buf space check
++ */
++int
++bcm_pack_xtlv_entry(uint8 **tlv_buf, uint16 *buflen, uint16 type, uint16 len, void *src,
++	bcm_xtlv_opts_t opts)
++{
++	bcm_xtlv_t *ptlv = (bcm_xtlv_t *)*tlv_buf;
++	int size;
++
++	ASSERT(ptlv);
++	ASSERT(src);
++
++	size = bcm_xtlv_size_for_data(len, opts);
++
++	/* copy data from tlv buffer to dst provided by user */
++	if (size > *buflen) {
++		printf("bcm_pack_xtlv_entry: no space tlv_buf: requested:%d, available:%d\n",
++			size, *buflen);
++		return BCME_BADLEN;
++	}
++	ptlv->id = htol16(type);
++	ptlv->len = htol16(len);
++
++	/* copy callers data */
++	memcpy(ptlv->data, src, len);
++
++	/* advance callers pointer to tlv buff */
++	*tlv_buf += size;
++	/* decrement the len */
++	*buflen -= (uint16)size;
++	return BCME_OK;
++}
++
++/*
++ *  unpack all xtlv records from the issue a callback
++ *  to set function one call per found tlv record
++ */
++int
++bcm_unpack_xtlv_buf(void *ctx, uint8 *tlv_buf, uint16 buflen, bcm_xtlv_opts_t opts,
++	bcm_xtlv_unpack_cbfn_t *cbfn)
++{
++	uint16 len;
++	uint16 type;
++	int res = BCME_OK;
++	int size;
++	bcm_xtlv_t *ptlv;
++	int sbuflen = buflen;
++
++	ASSERT(!buflen || tlv_buf);
++	ASSERT(!buflen || cbfn);
++
++	while (sbuflen >= (int)BCM_XTLV_HDR_SIZE) {
++		ptlv = (bcm_xtlv_t *)tlv_buf;
++
++		/* tlv header is always packed in LE order */
++		len = ltoh16(ptlv->len);
++		type = ltoh16(ptlv->id);
++
++		size = bcm_xtlv_size_for_data(len, opts);
++
++		sbuflen -= size;
++		/* check for possible buffer overrun */
++		if (sbuflen < 0)
++			break;
++
++		if ((res = cbfn(ctx, ptlv->data, type, len)) != BCME_OK)
++			break;
++		tlv_buf += size;
++	}
++	return res;
++}
++
++int
++bcm_pack_xtlv_buf(void *ctx, void *tlv_buf, uint16 buflen, bcm_xtlv_opts_t opts,
++	bcm_pack_xtlv_next_info_cbfn_t get_next, bcm_pack_xtlv_pack_next_cbfn_t pack_next,
++	int *outlen)
++{
++	int res = BCME_OK;
++	uint16 tlv_id;
++	uint16 tlv_len;
++	uint8 *startp;
++	uint8 *endp;
++	uint8 *buf;
++	bool more;
++	int size;
++
++	ASSERT(get_next && pack_next);
++
++	buf = (uint8 *)tlv_buf;
++	startp = buf;
++	endp = (uint8 *)buf + buflen;
++	more = TRUE;
++	while (more && (buf < endp)) {
++		more = get_next(ctx, &tlv_id, &tlv_len);
++		size = bcm_xtlv_size_for_data(tlv_len, opts);
++		if ((buf + size) >= endp) {
++			res = BCME_BUFTOOSHORT;
++			goto done;
++		}
++
++		htol16_ua_store(tlv_id, buf);
++		htol16_ua_store(tlv_len, buf + sizeof(tlv_id));
++		pack_next(ctx, tlv_id, tlv_len, buf + BCM_XTLV_HDR_SIZE);
++		buf += size;
++	}
++
++	if (more)
++		res = BCME_BUFTOOSHORT;
++
++done:
++	if (outlen) {
++		*outlen = (int)(buf - startp);
++	}
++	return res;
++}
++
++/*
++ *  pack xtlv buffer from memory according to xtlv_desc_t
++ */
++int
++bcm_pack_xtlv_buf_from_mem(void **tlv_buf, uint16 *buflen, xtlv_desc_t *items,
++	bcm_xtlv_opts_t opts)
++{
++	int res = BCME_OK;
++	uint8 *ptlv = (uint8 *)*tlv_buf;
++
++	while (items->type != 0) {
++		if ((res = bcm_pack_xtlv_entry(&ptlv,
++			buflen, items->type,
++			items->len, items->ptr, opts) != BCME_OK)) {
++			break;
++		}
++		items++;
++	}
++	*tlv_buf = ptlv; /* update the external pointer */
++	return res;
++}
++
++/*
++ *  unpack xtlv buffer to memory according to xtlv_desc_t
++ *
++ */
++int
++bcm_unpack_xtlv_buf_to_mem(void *tlv_buf, int *buflen, xtlv_desc_t *items, bcm_xtlv_opts_t opts)
++{
++	int res = BCME_OK;
++	bcm_xtlv_t *elt;
++
++	elt =  bcm_valid_xtlv((bcm_xtlv_t *)tlv_buf, *buflen, opts) ? (bcm_xtlv_t *)tlv_buf : NULL;
++	if (!elt || !items) {
++		res = BCME_BADARG;
++		return res;
++	}
++
++	for (; elt != NULL && res == BCME_OK; elt = bcm_next_xtlv(elt, buflen, opts)) {
++		/*  find matches in desc_t items  */
++		xtlv_desc_t *dst_desc = items;
++		uint16 len = ltoh16(elt->len);
++
++		while (dst_desc->type != 0) {
++			if (ltoh16(elt->id) == dst_desc->type) {
++				if (len != dst_desc->len) {
++					res = BCME_BADLEN;
++				} else {
++					memcpy(dst_desc->ptr, elt->data, len);
++				}
++				break;
++			}
++			dst_desc++;
++		}
++	}
++
++	if (res == BCME_OK && *buflen != 0)
++		res =  BCME_BUFTOOSHORT;
++
++	return res;
++}
++
++/*
++ * return data pointer of a given ID from xtlv buffer.
++ * If the specified xTLV ID is found, on return *data_len_out will contain
++ * the the data length of the xTLV ID.
++ */
++void *
++bcm_get_data_from_xtlv_buf(uint8 *tlv_buf, uint16 buflen, uint16 id,
++	uint16 *datalen_out, bcm_xtlv_opts_t opts)
++{
++	void *retptr = NULL;
++	uint16 type, len;
++	int size;
++	bcm_xtlv_t *ptlv;
++	int sbuflen = buflen;
++
++	/* Init the datalength */
++	if (datalen_out) {
++		*datalen_out = 0;
++	}
++	while (sbuflen >= (int)BCM_XTLV_HDR_SIZE) {
++		ptlv = (bcm_xtlv_t *)tlv_buf;
++
++		/* tlv header is always packed in LE order */
++		type = ltoh16(ptlv->id);
++		len = ltoh16(ptlv->len);
++		size = bcm_xtlv_size_for_data(len, opts);
++
++		sbuflen -= size;
++		/* check for possible buffer overrun */
++		if (sbuflen < 0) {
++			printf("%s %d: Invalid sbuflen %d\n",
++				__FUNCTION__, __LINE__, sbuflen);
++			break;
++		}
++
++		if (id == type) {
++			retptr = ptlv->data;
++			if (datalen_out) {
++				*datalen_out = len;
++			}
++			break;
++		}
++		tlv_buf += size;
++	}
++
++	return retptr;
++}
++
++int bcm_xtlv_size(const bcm_xtlv_t *elt, bcm_xtlv_opts_t opts)
++{
++	int size; /* entire size of the XTLV including header, data, and optional padding */
++	int len; /* XTLV's value real length wthout padding */
++
++	len = BCM_XTLV_LEN(elt);
++
++	size = bcm_xtlv_size_for_data(len, opts);
++
++	return size;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dbus.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dbus.c
+new file mode 100644
+index 000000000..5e2118194
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dbus.c
+@@ -0,0 +1,2500 @@
++/** @file dbus.c
++ *
++ * Hides details of USB / SDIO / SPI interfaces and OS details. It is intended to shield details and
++ * provide the caller with one common bus interface for all dongle devices. In practice, it is only
++ * used for USB interfaces. DBUS is not a protocol, but an abstraction layer.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dbus.c 553311 2015-04-29 10:23:08Z $
++ */
++
++
++#include "osl.h"
++#include "dbus.h"
++#include <bcmutils.h>
++
++#if defined(BCM_DNGL_EMBEDIMAGE)
++#include <bcmsrom_fmt.h>
++#include <trxhdr.h>
++#include <usbrdl.h>
++#include <bcmendian.h>
++#include <zutil.h>
++#include <sbpcmcia.h>
++#include <bcmnvram.h>
++#include <bcmdevs.h>
++#elif defined(BCM_REQUEST_FW)
++#include <bcmsrom_fmt.h>
++#include <trxhdr.h>
++#include <usbrdl.h>
++#include <bcmendian.h>
++#include <sbpcmcia.h>
++#include <bcmnvram.h>
++#include <bcmdevs.h>
++#endif /* #if defined(BCM_DNGL_EMBEDIMAGE) */
++#if defined(EHCI_FASTPATH_TX) || defined(EHCI_FASTPATH_RX)
++#include <linux/usb.h>
++#endif /* EHCI_FASTPATH_TX || EHCI_FASTPATH_RX */
++
++
++#if defined(BCM_DNGL_EMBEDIMAGE)
++/* zlib file format field ids etc from gzio.c */
++#define Z_DEFLATED     8
++#define ASCII_FLAG     0x01 /* bit 0 set: file probably ascii text */
++#define HEAD_CRC       0x02 /* bit 1 set: header CRC present */
++#define EXTRA_FIELD    0x04 /* bit 2 set: extra field present */
++#define ORIG_NAME      0x08 /* bit 3 set: original file name present */
++#define COMMENT        0x10 /* bit 4 set: file comment present */
++#define RESERVED       0xE0 /* bits 5..7: reserved */
++
++#ifdef WL_FW_DECOMP
++#define UNZIP_ENAB(info)  1
++#else
++#define UNZIP_ENAB(info)  0
++
++#ifdef inflateInit2
++#undef inflateInit2
++#define inflateInit2(a, b)  Z_ERRNO
++#endif
++#define inflate(a, b)       Z_STREAM_ERROR
++#define inflateEnd(a)       do {} while (0)
++#define crc32(a, b, c)      -1
++#define free(a)             do {} while (0)
++#endif /* WL_FW_DECOMP */
++
++#elif defined(BCM_REQUEST_FW)
++#ifndef VARS_MAX
++#define VARS_MAX            8192
++#endif
++#endif /* #if defined(BCM_DNGL_EMBEDIMAGE) */
++
++#ifdef DBUS_USB_LOOPBACK
++extern bool is_loopback_pkt(void *buf);
++extern int matches_loopback_pkt(void *buf);
++#endif
++
++/** General info for all BUS types */
++typedef struct dbus_irbq {
++	dbus_irb_t *head;
++	dbus_irb_t *tail;
++	int cnt;
++} dbus_irbq_t;
++
++/**
++ * This private structure dbus_info_t is also declared in dbus_usb_linux.c.
++ * All the fields must be consistent in both declarations.
++ */
++typedef struct dbus_info {
++	dbus_pub_t   pub; /* MUST BE FIRST */
++
++	void        *cbarg;
++	dbus_callbacks_t *cbs; /* callbacks to higher level, e.g. dhd_linux.c */
++	void        *bus_info;
++	dbus_intf_t *drvintf;  /* callbacks to lower level, e.g. dbus_usb.c or dbus_usb_linux.c */
++	uint8       *fw;
++	int         fwlen;
++	uint32      errmask;
++	int         rx_low_watermark;  /* avoid rx overflow by filling rx with free IRBs */
++	int         tx_low_watermark;
++	bool        txoff;
++	bool        txoverride;   /* flow control related */
++	bool        rxoff;
++	bool        tx_timer_ticking;
++
++
++	dbus_irbq_t *rx_q;
++	dbus_irbq_t *tx_q;
++
++#ifdef EHCI_FASTPATH_RX
++	atomic_t    rx_outstanding;
++#endif
++	uint8        *nvram;
++	int          nvram_len;
++	uint8        *image;  /* buffer for combine fw and nvram */
++	int          image_len;
++	uint8        *orig_fw;
++	int          origfw_len;
++	int          decomp_memsize;
++	dbus_extdl_t extdl;
++	int          nvram_nontxt;
++#if defined(BCM_REQUEST_FW)
++	void         *firmware;
++	void         *nvfile;
++#endif
++} dbus_info_t;
++
++struct exec_parms {
++	union {
++		/* Can consolidate same params, if need be, but this shows
++		 * group of parameters per function
++		 */
++		struct {
++			dbus_irbq_t  *q;
++			dbus_irb_t   *b;
++		} qenq;
++
++		struct {
++			dbus_irbq_t  *q;
++		} qdeq;
++	};
++};
++
++#define EXEC_RXLOCK(info, fn, a) \
++	info->drvintf->exec_rxlock(dbus_info->bus_info, ((exec_cb_t)fn), ((struct exec_parms *) a))
++
++#define EXEC_TXLOCK(info, fn, a) \
++	info->drvintf->exec_txlock(dbus_info->bus_info, ((exec_cb_t)fn), ((struct exec_parms *) a))
++
++/*
++ * Callbacks common for all BUS
++ */
++static void dbus_if_send_irb_timeout(void *handle, dbus_irb_tx_t *txirb);
++static void dbus_if_send_irb_complete(void *handle, dbus_irb_tx_t *txirb, int status);
++static void dbus_if_recv_irb_complete(void *handle, dbus_irb_rx_t *rxirb, int status);
++static void dbus_if_errhandler(void *handle, int err);
++static void dbus_if_ctl_complete(void *handle, int type, int status);
++static void dbus_if_state_change(void *handle, int state);
++static void *dbus_if_pktget(void *handle, uint len, bool send);
++static void dbus_if_pktfree(void *handle, void *p, bool send);
++static struct dbus_irb *dbus_if_getirb(void *cbarg, bool send);
++static void dbus_if_rxerr_indicate(void *handle, bool on);
++
++/** functions in this file that are called by lower DBUS levels, e.g. dbus_usb.c */
++static dbus_intf_callbacks_t dbus_intf_cbs = {
++	dbus_if_send_irb_timeout,
++	dbus_if_send_irb_complete,
++	dbus_if_recv_irb_complete,
++	dbus_if_errhandler,
++	dbus_if_ctl_complete,
++	dbus_if_state_change,
++	NULL,			/* isr */
++	NULL,			/* dpc */
++	NULL,			/* watchdog */
++	dbus_if_pktget,
++	dbus_if_pktfree,
++	dbus_if_getirb,
++	dbus_if_rxerr_indicate
++};
++
++/*
++ * Need global for probe() and disconnect() since
++ * attach() is not called at probe and detach()
++ * can be called inside disconnect()
++ */
++static dbus_intf_t     *g_busintf = NULL;
++static probe_cb_t      probe_cb = NULL;
++static disconnect_cb_t disconnect_cb = NULL;
++static void            *probe_arg = NULL;
++static void            *disc_arg = NULL;
++
++#if defined(BCM_REQUEST_FW)
++int8 *nonfwnvram = NULL; /* stand-alone multi-nvram given with driver load */
++int nonfwnvramlen = 0;
++#endif /* #if defined(BCM_REQUEST_FW) */
++
++static void* q_enq(dbus_irbq_t *q, dbus_irb_t *b);
++static void* q_enq_exec(struct exec_parms *args);
++static dbus_irb_t*q_deq(dbus_irbq_t *q);
++static void* q_deq_exec(struct exec_parms *args);
++static int   dbus_tx_timer_init(dbus_info_t *dbus_info);
++static int   dbus_tx_timer_start(dbus_info_t *dbus_info, uint timeout);
++static int   dbus_tx_timer_stop(dbus_info_t *dbus_info);
++static int   dbus_irbq_init(dbus_info_t *dbus_info, dbus_irbq_t *q, int nq, int size_irb);
++static int   dbus_irbq_deinit(dbus_info_t *dbus_info, dbus_irbq_t *q, int size_irb);
++static int   dbus_rxirbs_fill(dbus_info_t *dbus_info);
++static int   dbus_send_irb(dbus_pub_t *pub, uint8 *buf, int len, void *pkt, void *info);
++static void  dbus_disconnect(void *handle);
++static void *dbus_probe(void *arg, const char *desc, uint32 bustype, uint32 hdrlen);
++
++#if (defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW))
++#if defined(BCM_REQUEST_FW)
++extern char * dngl_firmware;
++extern unsigned int dngl_fwlen;
++#endif  /* #if defined(BCM_REQUEST_FW) */
++static int dbus_get_nvram(dbus_info_t *dbus_info);
++static int dbus_jumbo_nvram(dbus_info_t *dbus_info);
++static int dbus_otp(dbus_info_t *dbus_info, uint16 *boardtype, uint16 *boardrev);
++static int dbus_select_nvram(dbus_info_t *dbus_info, int8 *jumbonvram, int jumbolen,
++uint16 boardtype, uint16 boardrev, int8 **nvram, int *nvram_len);
++#ifndef BCM_REQUEST_FW
++static int dbus_zlib_decomp(dbus_info_t *dbus_info);
++extern void *dbus_zlib_calloc(int num, int size);
++extern void dbus_zlib_free(void *ptr);
++#endif
++#endif /* defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW) */
++
++/* function */
++void
++dbus_flowctrl_tx(void *dbi, bool on)
++{
++	dbus_info_t *dbus_info = dbi;
++
++	if (dbus_info == NULL)
++		return;
++
++	DBUSTRACE(("%s on %d\n", __FUNCTION__, on));
++
++	if (dbus_info->txoff == on)
++		return;
++
++	dbus_info->txoff = on;
++
++	if (dbus_info->cbs && dbus_info->cbs->txflowcontrol)
++		dbus_info->cbs->txflowcontrol(dbus_info->cbarg, on);
++}
++
++/**
++ * if lower level DBUS signaled a rx error, more free rx IRBs should be allocated or flow control
++ * should kick in to make more free rx IRBs available.
++ */
++static void
++dbus_if_rxerr_indicate(void *handle, bool on)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) handle;
++
++	DBUSTRACE(("%s, on %d\n", __FUNCTION__, on));
++
++	if (dbus_info == NULL)
++		return;
++
++	if (dbus_info->txoverride == on)
++		return;
++
++	dbus_info->txoverride = on;	/* flow control */
++
++	if (!on)
++		dbus_rxirbs_fill(dbus_info);
++
++}
++
++/** q_enq()/q_deq() are executed with protection via exec_rxlock()/exec_txlock() */
++static void*
++q_enq(dbus_irbq_t *q, dbus_irb_t *b)
++{
++	ASSERT(q->tail != b);
++	ASSERT(b->next == NULL);
++	b->next = NULL;
++	if (q->tail) {
++		q->tail->next = b;
++		q->tail = b;
++	} else
++		q->head = q->tail = b;
++
++	q->cnt++;
++
++	return b;
++}
++
++static void*
++q_enq_exec(struct exec_parms *args)
++{
++	return q_enq(args->qenq.q, args->qenq.b);
++}
++
++static dbus_irb_t*
++q_deq(dbus_irbq_t *q)
++{
++	dbus_irb_t *b;
++
++	b = q->head;
++	if (b) {
++		q->head = q->head->next;
++		b->next = NULL;
++
++		if (q->head == NULL)
++			q->tail = q->head;
++
++		q->cnt--;
++	}
++	return b;
++}
++
++static void*
++q_deq_exec(struct exec_parms *args)
++{
++	return q_deq(args->qdeq.q);
++}
++
++/**
++ * called during attach phase. Status @ Dec 2012: this function does nothing since for all of the
++ * lower DBUS levels dbus_info->drvintf->tx_timer_init is NULL.
++ */
++static int
++dbus_tx_timer_init(dbus_info_t *dbus_info)
++{
++	if (dbus_info && dbus_info->drvintf && dbus_info->drvintf->tx_timer_init)
++		return dbus_info->drvintf->tx_timer_init(dbus_info->bus_info);
++	else
++		return DBUS_ERR;
++}
++
++static int
++dbus_tx_timer_start(dbus_info_t *dbus_info, uint timeout)
++{
++	if (dbus_info == NULL)
++		return DBUS_ERR;
++
++	if (dbus_info->tx_timer_ticking)
++		return DBUS_OK;
++
++	if (dbus_info->drvintf && dbus_info->drvintf->tx_timer_start) {
++		if (dbus_info->drvintf->tx_timer_start(dbus_info->bus_info, timeout) == DBUS_OK) {
++			dbus_info->tx_timer_ticking = TRUE;
++			return DBUS_OK;
++		}
++	}
++
++	return DBUS_ERR;
++}
++
++static int
++dbus_tx_timer_stop(dbus_info_t *dbus_info)
++{
++	if (dbus_info == NULL)
++		return DBUS_ERR;
++
++	if (!dbus_info->tx_timer_ticking)
++		return DBUS_OK;
++
++	if (dbus_info->drvintf && dbus_info->drvintf->tx_timer_stop) {
++		if (dbus_info->drvintf->tx_timer_stop(dbus_info->bus_info) == DBUS_OK) {
++			dbus_info->tx_timer_ticking = FALSE;
++			return DBUS_OK;
++		}
++	}
++
++	return DBUS_ERR;
++}
++
++/** called during attach phase. */
++static int
++dbus_irbq_init(dbus_info_t *dbus_info, dbus_irbq_t *q, int nq, int size_irb)
++{
++	int i;
++	dbus_irb_t *irb;
++
++	ASSERT(q);
++	ASSERT(dbus_info);
++
++	for (i = 0; i < nq; i++) {
++		/* MALLOC dbus_irb_tx or dbus_irb_rx, but cast to simple dbus_irb_t linkedlist */
++		irb = (dbus_irb_t *) MALLOC(dbus_info->pub.osh, size_irb);
++		if (irb == NULL) {
++			ASSERT(irb);
++			return DBUS_ERR;
++		}
++		bzero(irb, size_irb);
++
++		/* q_enq() does not need to go through EXEC_xxLOCK() during init() */
++		q_enq(q, irb);
++	}
++
++	return DBUS_OK;
++}
++
++/** called during detach phase or when attach failed */
++static int
++dbus_irbq_deinit(dbus_info_t *dbus_info, dbus_irbq_t *q, int size_irb)
++{
++	dbus_irb_t *irb;
++
++	ASSERT(q);
++	ASSERT(dbus_info);
++
++	/* q_deq() does not need to go through EXEC_xxLOCK()
++	 * during deinit(); all callbacks are stopped by this time
++	 */
++	while ((irb = q_deq(q)) != NULL) {
++		MFREE(dbus_info->pub.osh, irb, size_irb);
++	}
++
++	if (q->cnt)
++		DBUSERR(("deinit: q->cnt=%d > 0\n", q->cnt));
++	return DBUS_OK;
++}
++
++/** multiple code paths require the rx queue to be filled with more free IRBs */
++static int
++dbus_rxirbs_fill(dbus_info_t *dbus_info)
++{
++	int err = DBUS_OK;
++
++#ifdef EHCI_FASTPATH_RX
++	while (atomic_read(&dbus_info->rx_outstanding) < 100)
++	{
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++		/* NOCOPY force new packet allocation */
++		optimize_submit_rx_request(&dbus_info->pub, 1, NULL, NULL);
++#else
++		/* Copy mode - allocate own buffer to be reused */
++		void *buf = MALLOC(dbus_info->pub.osh, 4000); /* usbos_info->rxbuf_len */
++		optimize_submit_rx_request(&dbus_info->pub, 1, NULL, buf);
++#endif /* BCM_RPC_NOCOPY || BCM_RPC_RXNOCOPY */
++		atomic_inc(&dbus_info->rx_outstanding);
++	}
++#else /* EHCI_FASTPATH_RX */
++
++	dbus_irb_rx_t *rxirb;
++	struct exec_parms args;
++
++	ASSERT(dbus_info);
++	if (dbus_info->pub.busstate != DBUS_STATE_UP) {
++		DBUSERR(("dbus_rxirbs_fill: DBUS not up \n"));
++		return DBUS_ERR;
++	} else if (!dbus_info->drvintf || (dbus_info->drvintf->recv_irb == NULL)) {
++		/* Lower edge bus interface does not support recv_irb().
++		 * No need to pre-submit IRBs in this case.
++		 */
++		return DBUS_ERR;
++	}
++
++	/* The dongle recv callback is freerunning without lock. So multiple callbacks(and this
++	 *  refill) can run in parallel. While the rxoff condition is triggered outside,
++	 *  below while loop has to check and abort posting more to avoid RPC rxq overflow.
++	 */
++	args.qdeq.q = dbus_info->rx_q;
++	while ((!dbus_info->rxoff) &&
++	       (rxirb = (EXEC_RXLOCK(dbus_info, q_deq_exec, &args))) != NULL) {
++		err = dbus_info->drvintf->recv_irb(dbus_info->bus_info, rxirb);
++		if (err == DBUS_ERR_RXDROP || err == DBUS_ERR_RXFAIL) {
++			/* Add the the free rxirb back to the queue
++			 * and wait till later
++			 */
++			bzero(rxirb, sizeof(dbus_irb_rx_t));
++			args.qenq.q = dbus_info->rx_q;
++			args.qenq.b = (dbus_irb_t *) rxirb;
++			EXEC_RXLOCK(dbus_info, q_enq_exec, &args);
++			break;
++		} else if (err != DBUS_OK) {
++			int i = 0;
++			while (i++ < 100) {
++				DBUSERR(("%s :: memory leak for rxirb note?\n", __FUNCTION__));
++			}
++		}
++	}
++#endif /* EHCI_FASTPATH_RX */
++	return err;
++} /* dbus_rxirbs_fill */
++
++/** called when the DBUS interface state changed. */
++void
++dbus_flowctrl_rx(dbus_pub_t *pub, bool on)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++
++	if (dbus_info == NULL)
++		return;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dbus_info->rxoff == on)
++		return;
++
++	dbus_info->rxoff = on;
++
++	if (dbus_info->pub.busstate == DBUS_STATE_UP) {
++		if (!on) {
++			/* post more irbs, resume rx if necessary */
++			dbus_rxirbs_fill(dbus_info);
++			if (dbus_info && dbus_info->drvintf->recv_resume) {
++				dbus_info->drvintf->recv_resume(dbus_info->bus_info);
++			}
++		} else {
++			/* ??? cancell posted irbs first */
++
++			if (dbus_info && dbus_info->drvintf->recv_stop) {
++				dbus_info->drvintf->recv_stop(dbus_info->bus_info);
++			}
++		}
++	}
++}
++
++/**
++ * Several code paths in this file want to send a buffer to the dongle. This function handles both
++ * sending of a buffer or a pkt.
++ */
++static int
++dbus_send_irb(dbus_pub_t *pub, uint8 *buf, int len, void *pkt, void *info)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++	int err = DBUS_OK;
++#ifndef EHCI_FASTPATH_TX
++	dbus_irb_tx_t *txirb = NULL;
++	int txirb_pending;
++	struct exec_parms args;
++#endif /* EHCI_FASTPATH_TX */
++
++	if (dbus_info == NULL)
++		return DBUS_ERR;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dbus_info->pub.busstate == DBUS_STATE_UP ||
++		dbus_info->pub.busstate == DBUS_STATE_SLEEP) {
++#ifdef EHCI_FASTPATH_TX
++		struct ehci_qtd *qtd;
++		int token = EHCI_QTD_SET_CERR(3);
++		int len;
++
++		ASSERT(buf == NULL); /* Not handled */
++		ASSERT(pkt != NULL);
++
++		qtd = optimize_ehci_qtd_alloc(GFP_KERNEL);
++
++		if (qtd == NULL)
++			return DBUS_ERR;
++
++		len = PKTLEN(pub->osh, pkt);
++
++		len = ROUNDUP(len, sizeof(uint32));
++
++
++		optimize_qtd_fill_with_rpc(pub, 0, qtd, pkt, token, len);
++		err = optimize_submit_async(qtd, 0);
++
++		if (err) {
++			optimize_ehci_qtd_free(qtd);
++			err = DBUS_ERR_TXDROP;
++		}
++
++#else
++		args.qdeq.q = dbus_info->tx_q;
++		if (dbus_info->drvintf)
++			txirb = EXEC_TXLOCK(dbus_info, q_deq_exec, &args);
++
++		if (txirb == NULL) {
++			DBUSERR(("Out of tx dbus_bufs\n"));
++			return DBUS_ERR;
++		}
++
++		if (pkt != NULL) {
++			txirb->pkt = pkt;
++			txirb->buf = NULL;
++			txirb->len = 0;
++		} else if (buf != NULL) {
++			txirb->pkt = NULL;
++			txirb->buf = buf;
++			txirb->len = len;
++		} else {
++			ASSERT(0); /* Should not happen */
++		}
++		txirb->info = info;
++		txirb->arg = NULL;
++		txirb->retry_count = 0;
++
++		if (dbus_info->drvintf && dbus_info->drvintf->send_irb) {
++			/* call lower DBUS level send_irb function */
++			err = dbus_info->drvintf->send_irb(dbus_info->bus_info, txirb);
++			if (err == DBUS_ERR_TXDROP) {
++				/* tx fail and no completion routine to clean up, reclaim irb NOW */
++				DBUSERR(("%s: send_irb failed, status = %d\n", __FUNCTION__, err));
++				bzero(txirb, sizeof(dbus_irb_tx_t));
++				args.qenq.q = dbus_info->tx_q;
++				args.qenq.b = (dbus_irb_t *) txirb;
++				EXEC_TXLOCK(dbus_info, q_enq_exec, &args);
++			} else {
++				dbus_tx_timer_start(dbus_info, DBUS_TX_TIMEOUT_INTERVAL);
++				txirb_pending = dbus_info->pub.ntxq - dbus_info->tx_q->cnt;
++				if (txirb_pending > (dbus_info->tx_low_watermark * 3)) {
++					dbus_flowctrl_tx(dbus_info, TRUE);
++				}
++			}
++		}
++#endif /* EHCI_FASTPATH_TX */
++	} else {
++		err = DBUS_ERR_TXFAIL;
++		DBUSTRACE(("%s: bus down, send_irb failed\n", __FUNCTION__));
++	}
++
++	return err;
++} /* dbus_send_irb */
++
++#if (defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW))
++
++/**
++ * Before downloading a firmware image into the dongle, the validity of the image must be checked.
++ */
++static int
++check_file(osl_t *osh, unsigned char *headers)
++{
++	struct trx_header *trx;
++	int actual_len = -1;
++
++	/* Extract trx header */
++	trx = (struct trx_header *)headers;
++	if (ltoh32(trx->magic) != TRX_MAGIC) {
++		printf("Error: trx bad hdr %x\n", ltoh32(trx->magic));
++		return -1;
++	}
++
++	headers += SIZEOF_TRX(trx);
++
++	/* TRX V1: get firmware len */
++	/* TRX V2: get firmware len and DSG/CFG lengths */
++	if (ltoh32(trx->flag_version) & TRX_UNCOMP_IMAGE) {
++		actual_len = ltoh32(trx->offsets[TRX_OFFSETS_DLFWLEN_IDX]) +
++		                     SIZEOF_TRX(trx);
++#ifdef BCMTRXV2
++		if (ISTRX_V2(trx)) {
++			actual_len += ltoh32(trx->offsets[TRX_OFFSETS_DSG_LEN_IDX]) +
++				ltoh32(trx->offsets[TRX_OFFSETS_CFG_LEN_IDX]);
++		}
++#endif
++		return actual_len;
++	}  else {
++		printf("compressed image\n");
++	}
++
++	return -1;
++}
++
++/**
++ * It is easy for the user to pass one jumbo nvram file to the driver than a set of smaller files.
++ * The 'jumbo nvram' file format is essentially a set of nvram files. Before commencing firmware
++ * download, the dongle needs to be probed so that the correct nvram contents within the jumbo nvram
++ * file is selected.
++ */
++static int
++dbus_jumbo_nvram(dbus_info_t *dbus_info)
++{
++	int8 *nvram = NULL;
++	int nvram_len = 0;
++	int ret = DBUS_OK;
++	uint16 boardrev = 0xFFFF;
++	uint16 boardtype = 0xFFFF;
++
++	/* read the otp for boardrev & boardtype
++	* if boardtype/rev are present in otp
++	* select nvram data for that boardtype/rev
++	*/
++	dbus_otp(dbus_info, &boardtype, &boardrev);
++
++	ret = dbus_select_nvram(dbus_info, dbus_info->extdl.vars, dbus_info->extdl.varslen,
++		boardtype, boardrev, &nvram, &nvram_len);
++
++	if (ret == DBUS_JUMBO_BAD_FORMAT)
++			return DBUS_ERR_NVRAM;
++	else if (ret == DBUS_JUMBO_NOMATCH &&
++		(boardtype != 0xFFFF || boardrev  != 0xFFFF)) {
++			DBUSERR(("No matching NVRAM for boardtype 0x%02x boardrev 0x%02x\n",
++				boardtype, boardrev));
++			return DBUS_ERR_NVRAM;
++	}
++	dbus_info->nvram = nvram;
++	dbus_info->nvram_len =  nvram_len;
++
++	return DBUS_OK;
++}
++
++/** before commencing fw download, the correct NVRAM image to download has to be picked */
++static int
++dbus_get_nvram(dbus_info_t *dbus_info)
++{
++	int len, i;
++	struct trx_header *hdr;
++	int	actual_fwlen;
++	uint32 img_offset = 0;
++
++	dbus_info->nvram_len = 0;
++	if (dbus_info->extdl.varslen) {
++		if (DBUS_OK != dbus_jumbo_nvram(dbus_info))
++			return DBUS_ERR_NVRAM;
++		DBUSERR(("NVRAM %d bytes downloaded\n", dbus_info->nvram_len));
++	}
++#if defined(BCM_REQUEST_FW)
++	else if (nonfwnvram) {
++		dbus_info->nvram = nonfwnvram;
++		dbus_info->nvram_len = nonfwnvramlen;
++		DBUSERR(("NVRAM %d bytes downloaded\n", dbus_info->nvram_len));
++	}
++#endif
++	if (dbus_info->nvram) {
++		uint8 nvram_words_pad = 0;
++		/* Validate the format/length etc of the file */
++		if ((actual_fwlen = check_file(dbus_info->pub.osh, dbus_info->fw)) <= 0) {
++			DBUSERR(("%s: bad firmware format!\n", __FUNCTION__));
++			return DBUS_ERR_NVRAM;
++		}
++
++		if (!dbus_info->nvram_nontxt) {
++			/* host supplied nvram could be in .txt format
++			* with all the comments etc...
++			*/
++			dbus_info->nvram_len = process_nvram_vars(dbus_info->nvram,
++				dbus_info->nvram_len);
++		}
++		if (dbus_info->nvram_len % 4)
++			nvram_words_pad = 4 - dbus_info->nvram_len % 4;
++
++		len = actual_fwlen + dbus_info->nvram_len + nvram_words_pad;
++		dbus_info->image = MALLOC(dbus_info->pub.osh, len);
++		dbus_info->image_len = len;
++		if (dbus_info->image == NULL) {
++			DBUSERR(("%s: malloc failed!\n", __FUNCTION__));
++			return DBUS_ERR_NVRAM;
++		}
++		hdr = (struct trx_header *)dbus_info->fw;
++		/* Step1: Copy trx header + firmwre */
++		img_offset = SIZEOF_TRX(hdr) + hdr->offsets[TRX_OFFSETS_DLFWLEN_IDX];
++		bcopy(dbus_info->fw, dbus_info->image, img_offset);
++		/* Step2: Copy NVRAM + pad */
++		bcopy(dbus_info->nvram, (uint8 *)(dbus_info->image + img_offset),
++			dbus_info->nvram_len);
++		img_offset += dbus_info->nvram_len;
++		if (nvram_words_pad) {
++			bzero(&dbus_info->image[img_offset],
++				nvram_words_pad);
++			img_offset += nvram_words_pad;
++		}
++#ifdef BCMTRXV2
++		/* Step3: Copy DSG/CFG for V2 */
++		if (ISTRX_V2(hdr) &&
++			(hdr->offsets[TRX_OFFSETS_DSG_LEN_IDX] ||
++			hdr->offsets[TRX_OFFSETS_CFG_LEN_IDX])) {
++
++			bcopy(dbus_info->fw + SIZEOF_TRX(hdr) +
++				hdr->offsets[TRX_OFFSETS_DLFWLEN_IDX] +
++				hdr->offsets[TRX_OFFSETS_NVM_LEN_IDX],
++				dbus_info->image + img_offset,
++				hdr->offsets[TRX_OFFSETS_DSG_LEN_IDX] +
++				hdr->offsets[TRX_OFFSETS_CFG_LEN_IDX]);
++
++			img_offset += hdr->offsets[TRX_OFFSETS_DSG_LEN_IDX] +
++				hdr->offsets[TRX_OFFSETS_CFG_LEN_IDX];
++		}
++#endif /* BCMTRXV2 */
++		/* Step4: update TRX header for nvram size */
++		hdr = (struct trx_header *)dbus_info->image;
++		hdr->len = htol32(len);
++		/* Pass the actual fw len */
++		hdr->offsets[TRX_OFFSETS_NVM_LEN_IDX] =
++			htol32(dbus_info->nvram_len + nvram_words_pad);
++		/* Calculate CRC over header */
++		hdr->crc32 = hndcrc32((uint8 *)&hdr->flag_version,
++			SIZEOF_TRX(hdr) - OFFSETOF(struct trx_header, flag_version),
++			CRC32_INIT_VALUE);
++
++		/* Calculate CRC over data */
++		for (i = SIZEOF_TRX(hdr); i < len; ++i)
++				hdr->crc32 = hndcrc32((uint8 *)&dbus_info->image[i], 1, hdr->crc32);
++		hdr->crc32 = htol32(hdr->crc32);
++	} else {
++		dbus_info->image = dbus_info->fw;
++		dbus_info->image_len = (uint32)dbus_info->fwlen;
++	}
++
++	return DBUS_OK;
++} /* dbus_get_nvram */
++
++/**
++ * during driver initialization ('attach') or after PnP 'resume', firmware needs to be loaded into
++ * the dongle
++ */
++static int
++dbus_do_download(dbus_info_t *dbus_info)
++{
++	int err = DBUS_OK;
++#ifndef BCM_REQUEST_FW
++	int decomp_override = 0;
++#endif
++#ifdef BCM_REQUEST_FW
++	uint16 boardrev = 0xFFFF, boardtype = 0xFFFF;
++	int8 *temp_nvram;
++	int temp_len;
++#endif
++
++#if defined(BCM_DNGL_EMBEDIMAGE)
++	if (dbus_info->extdl.fw && (dbus_info->extdl.fwlen > 0)) {
++		dbus_info->fw = (uint8 *)dbus_info->extdl.fw;
++		dbus_info->fwlen = dbus_info->extdl.fwlen;
++		DBUSERR(("dbus_do_download: using override firmmware %d bytes\n",
++			dbus_info->fwlen));
++	} else
++		dbus_bus_fw_get(dbus_info->bus_info, &dbus_info->fw, &dbus_info->fwlen,
++			&decomp_override);
++
++	if (!dbus_info->fw) {
++		DBUSERR(("dbus_do_download: devid 0x%x / %d not supported\n",
++			dbus_info->pub.attrib.devid, dbus_info->pub.attrib.devid));
++		return DBUS_ERR;
++	}
++#elif defined(BCM_REQUEST_FW)
++	dbus_info->firmware = dbus_get_fw_nvfile(dbus_info->pub.attrib.devid,
++		dbus_info->pub.attrib.chiprev, &dbus_info->fw, &dbus_info->fwlen,
++		DBUS_FIRMWARE, 0, 0);
++	if (!dbus_info->firmware)
++		return DBUS_ERR;
++#endif /* defined(BCM_DNGL_EMBEDIMAGE) */
++
++	dbus_info->image = dbus_info->fw;
++	dbus_info->image_len = (uint32)dbus_info->fwlen;
++
++#ifndef BCM_REQUEST_FW
++	if (UNZIP_ENAB(dbus_info) && !decomp_override) {
++		err = dbus_zlib_decomp(dbus_info);
++		if (err) {
++			DBUSERR(("dbus_attach: fw decompress fail %d\n", err));
++			return err;
++		}
++	}
++#endif
++
++#if defined(BCM_REQUEST_FW)
++	/* check if firmware is appended with nvram file */
++	err = dbus_otp(dbus_info, &boardtype, &boardrev);
++	/* check if nvram is provided as separte file */
++	nonfwnvram = NULL;
++	nonfwnvramlen = 0;
++	dbus_info->nvfile = dbus_get_fw_nvfile(dbus_info->pub.attrib.devid,
++		dbus_info->pub.attrib.chiprev, (void *)&temp_nvram, &temp_len,
++		DBUS_NVFILE, boardtype, boardrev);
++	if (dbus_info->nvfile) {
++		int8 *tmp = MALLOC(dbus_info->pub.osh, temp_len);
++		if (tmp) {
++			bcopy(temp_nvram, tmp, temp_len);
++			nonfwnvram = tmp;
++			nonfwnvramlen = temp_len;
++		} else {
++			err = DBUS_ERR;
++			goto fail;
++		}
++	}
++#endif /* defined(BCM_REQUEST_FW) */
++
++	err = dbus_get_nvram(dbus_info);
++	if (err) {
++		DBUSERR(("dbus_do_download: fail to get nvram %d\n", err));
++		return err;
++	}
++
++
++	if (dbus_info->drvintf->dlstart && dbus_info->drvintf->dlrun) {
++		err = dbus_info->drvintf->dlstart(dbus_info->bus_info,
++			dbus_info->image, dbus_info->image_len);
++
++		if (err == DBUS_OK)
++			err = dbus_info->drvintf->dlrun(dbus_info->bus_info);
++	} else
++		err = DBUS_ERR;
++
++	if (dbus_info->nvram) {
++		MFREE(dbus_info->pub.osh, dbus_info->image, dbus_info->image_len);
++		dbus_info->image = dbus_info->fw;
++		dbus_info->image_len = (uint32)dbus_info->fwlen;
++	}
++
++#ifndef BCM_REQUEST_FW
++	if (UNZIP_ENAB(dbus_info) && (!decomp_override) && dbus_info->orig_fw) {
++		MFREE(dbus_info->pub.osh, dbus_info->fw, dbus_info->decomp_memsize);
++		dbus_info->image = dbus_info->fw = dbus_info->orig_fw;
++		dbus_info->image_len = dbus_info->fwlen = dbus_info->origfw_len;
++	}
++#endif
++
++#if defined(BCM_REQUEST_FW)
++fail:
++	if (dbus_info->firmware) {
++		dbus_release_fw_nvfile(dbus_info->firmware);
++		dbus_info->firmware = NULL;
++	}
++	if (dbus_info->nvfile) {
++		dbus_release_fw_nvfile(dbus_info->nvfile);
++		dbus_info->nvfile = NULL;
++	}
++	if (nonfwnvram) {
++		MFREE(dbus_info->pub.osh, nonfwnvram, nonfwnvramlen);
++		nonfwnvram = NULL;
++		nonfwnvramlen = 0;
++	}
++#endif
++	return err;
++} /* dbus_do_download */
++
++#endif /* defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW) */
++
++/** required for DBUS deregistration */
++static void
++dbus_disconnect(void *handle)
++{
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (disconnect_cb)
++		disconnect_cb(disc_arg);
++}
++
++/**
++ * This function is called when the sent irb times out without a tx response status.
++ * DBUS adds reliability by resending timed out IRBs DBUS_TX_RETRY_LIMIT times.
++ */
++static void
++dbus_if_send_irb_timeout(void *handle, dbus_irb_tx_t *txirb)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) handle;
++
++	if ((dbus_info == NULL) || (dbus_info->drvintf == NULL) || (txirb == NULL)) {
++		return;
++	}
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	return;
++
++} /* dbus_if_send_irb_timeout */
++
++/**
++ * When lower DBUS level signals that a send IRB completed, either successful or not, the higher
++ * level (e.g. dhd_linux.c) has to be notified, and transmit flow control has to be evaluated.
++ */
++static void BCMFASTPATH
++dbus_if_send_irb_complete(void *handle, dbus_irb_tx_t *txirb, int status)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) handle;
++	int txirb_pending;
++	struct exec_parms args;
++	void *pktinfo;
++
++	if ((dbus_info == NULL) || (txirb == NULL)) {
++		return;
++	}
++
++	DBUSTRACE(("%s: status = %d\n", __FUNCTION__, status));
++
++	dbus_tx_timer_stop(dbus_info);
++
++	/* re-queue BEFORE calling send_complete which will assume that this irb
++	   is now available.
++	 */
++	pktinfo = txirb->info;
++	bzero(txirb, sizeof(dbus_irb_tx_t));
++	args.qenq.q = dbus_info->tx_q;
++	args.qenq.b = (dbus_irb_t *) txirb;
++	EXEC_TXLOCK(dbus_info, q_enq_exec, &args);
++
++	if (dbus_info->pub.busstate != DBUS_STATE_DOWN) {
++		if ((status == DBUS_OK) || (status == DBUS_ERR_NODEVICE)) {
++			if (dbus_info->cbs && dbus_info->cbs->send_complete)
++				dbus_info->cbs->send_complete(dbus_info->cbarg, pktinfo,
++					status);
++
++			if (status == DBUS_OK) {
++				txirb_pending = dbus_info->pub.ntxq - dbus_info->tx_q->cnt;
++				if (txirb_pending)
++					dbus_tx_timer_start(dbus_info, DBUS_TX_TIMEOUT_INTERVAL);
++				if ((txirb_pending < dbus_info->tx_low_watermark) &&
++					dbus_info->txoff && !dbus_info->txoverride) {
++					dbus_flowctrl_tx(dbus_info, OFF);
++				}
++			}
++		} else {
++			DBUSERR(("%s: %d WARNING freeing orphan pkt %p\n", __FUNCTION__, __LINE__,
++				pktinfo));
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_TXNOCOPY) || defined(BCM_RPC_TOC)
++			if (pktinfo)
++				if (dbus_info->cbs && dbus_info->cbs->send_complete)
++					dbus_info->cbs->send_complete(dbus_info->cbarg, pktinfo,
++						status);
++#else
++			dbus_if_pktfree(dbus_info, (void*)pktinfo, TRUE);
++#endif /* defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_TXNOCOPY) || defined(BCM_RPC_TOC) */
++		}
++	} else {
++		DBUSERR(("%s: %d WARNING freeing orphan pkt %p\n", __FUNCTION__, __LINE__,
++			pktinfo));
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_TXNOCOPY) || defined(BCM_RPC_TOC)
++		if (pktinfo)
++			if (dbus_info->cbs && dbus_info->cbs->send_complete)
++				dbus_info->cbs->send_complete(dbus_info->cbarg, pktinfo,
++					status);
++#else
++		dbus_if_pktfree(dbus_info, (void*)pktinfo, TRUE);
++#endif /* defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_TXNOCOPY) defined(BCM_RPC_TOC) */
++	}
++} /* dbus_if_send_irb_complete */
++
++/**
++ * When lower DBUS level signals that a receive IRB completed, either successful or not, the higher
++ * level (e.g. dhd_linux.c) has to be notified, and fresh free receive IRBs may have to be given
++ * to lower levels.
++ */
++static void BCMFASTPATH
++dbus_if_recv_irb_complete(void *handle, dbus_irb_rx_t *rxirb, int status)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) handle;
++	int rxirb_pending;
++	struct exec_parms args;
++
++	if ((dbus_info == NULL) || (rxirb == NULL)) {
++		return;
++	}
++	DBUSTRACE(("%s\n", __FUNCTION__));
++	if (dbus_info->pub.busstate != DBUS_STATE_DOWN &&
++		dbus_info->pub.busstate != DBUS_STATE_SLEEP) {
++		if (status == DBUS_OK) {
++			if ((rxirb->buf != NULL) && (rxirb->actual_len > 0)) {
++#ifdef DBUS_USB_LOOPBACK
++				if (is_loopback_pkt(rxirb->buf)) {
++					matches_loopback_pkt(rxirb->buf);
++				} else
++#endif
++				if (dbus_info->cbs && dbus_info->cbs->recv_buf) {
++					dbus_info->cbs->recv_buf(dbus_info->cbarg, rxirb->buf,
++					rxirb->actual_len);
++				}
++			} else if (rxirb->pkt != NULL) {
++				if (dbus_info->cbs && dbus_info->cbs->recv_pkt)
++					dbus_info->cbs->recv_pkt(dbus_info->cbarg, rxirb->pkt);
++			} else {
++				ASSERT(0); /* Should not happen */
++			}
++
++			rxirb_pending = dbus_info->pub.nrxq - dbus_info->rx_q->cnt - 1;
++			if ((rxirb_pending <= dbus_info->rx_low_watermark) &&
++				!dbus_info->rxoff) {
++				DBUSTRACE(("Low watermark so submit more %d <= %d \n",
++					dbus_info->rx_low_watermark, rxirb_pending));
++				dbus_rxirbs_fill(dbus_info);
++			} else if (dbus_info->rxoff)
++				DBUSTRACE(("rx flow controlled. not filling more. cut_rxq=%d\n",
++					dbus_info->rx_q->cnt));
++		} else if (status == DBUS_ERR_NODEVICE) {
++			DBUSERR(("%s: %d status = %d, buf %p\n", __FUNCTION__, __LINE__, status,
++				rxirb->buf));
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++			if (rxirb->buf) {
++				PKTFRMNATIVE(dbus_info->pub.osh, rxirb->buf);
++				PKTFREE(dbus_info->pub.osh, rxirb->buf, FALSE);
++			}
++#endif /* BCM_RPC_NOCOPY || BCM_RPC_TXNOCOPY || BCM_RPC_TOC */
++		} else {
++			if (status != DBUS_ERR_RXZLP)
++				DBUSERR(("%s: %d status = %d, buf %p\n", __FUNCTION__, __LINE__,
++					status, rxirb->buf));
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++			if (rxirb->buf) {
++				PKTFRMNATIVE(dbus_info->pub.osh, rxirb->buf);
++				PKTFREE(dbus_info->pub.osh, rxirb->buf, FALSE);
++			}
++#endif /* BCM_RPC_NOCOPY || BCM_RPC_TXNOCOPY || BCM_RPC_TOC */
++		}
++	} else {
++		DBUSTRACE(("%s: DBUS down, ignoring recv callback. buf %p\n", __FUNCTION__,
++			rxirb->buf));
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++		if (rxirb->buf) {
++			PKTFRMNATIVE(dbus_info->pub.osh, rxirb->buf);
++			PKTFREE(dbus_info->pub.osh, rxirb->buf, FALSE);
++		}
++#endif /* BCM_RPC_NOCOPY || BCM_RPC_TXNOCOPY || BCM_RPC_TOC */
++	}
++	if (dbus_info->rx_q != NULL) {
++		bzero(rxirb, sizeof(dbus_irb_rx_t));
++		args.qenq.q = dbus_info->rx_q;
++		args.qenq.b = (dbus_irb_t *) rxirb;
++		EXEC_RXLOCK(dbus_info, q_enq_exec, &args);
++	} else
++		MFREE(dbus_info->pub.osh, rxirb, sizeof(dbus_irb_tx_t));
++} /* dbus_if_recv_irb_complete */
++
++/**
++ *  Accumulate errors signaled by lower DBUS levels and signal them to higher (e.g. dhd_linux.c)
++ *  level.
++ */
++static void
++dbus_if_errhandler(void *handle, int err)
++{
++	dbus_info_t *dbus_info = handle;
++	uint32 mask = 0;
++
++	if (dbus_info == NULL)
++		return;
++
++	switch (err) {
++		case DBUS_ERR_TXFAIL:
++			dbus_info->pub.stats.tx_errors++;
++			mask |= ERR_CBMASK_TXFAIL;
++			break;
++		case DBUS_ERR_TXDROP:
++			dbus_info->pub.stats.tx_dropped++;
++			mask |= ERR_CBMASK_TXFAIL;
++			break;
++		case DBUS_ERR_RXFAIL:
++			dbus_info->pub.stats.rx_errors++;
++			mask |= ERR_CBMASK_RXFAIL;
++			break;
++		case DBUS_ERR_RXDROP:
++			dbus_info->pub.stats.rx_dropped++;
++			mask |= ERR_CBMASK_RXFAIL;
++			break;
++		default:
++			break;
++	}
++
++	if (dbus_info->cbs && dbus_info->cbs->errhandler && (dbus_info->errmask & mask))
++		dbus_info->cbs->errhandler(dbus_info->cbarg, err);
++}
++
++/**
++ * When lower DBUS level signals control IRB completed, higher level (e.g. dhd_linux.c) has to be
++ * notified.
++ */
++static void
++dbus_if_ctl_complete(void *handle, int type, int status)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) handle;
++
++	if (dbus_info == NULL)
++		return;
++
++	if (dbus_info->pub.busstate != DBUS_STATE_DOWN) {
++		if (dbus_info->cbs && dbus_info->cbs->ctl_complete)
++			dbus_info->cbs->ctl_complete(dbus_info->cbarg, type, status);
++	}
++}
++
++/**
++ * Rx related functionality (flow control, posting of free IRBs to rx queue) is dependent upon the
++ * bus state. When lower DBUS level signals a change in the interface state, take appropriate action
++ * and forward the signaling to the higher (e.g. dhd_linux.c) level.
++ */
++static void
++dbus_if_state_change(void *handle, int state)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) handle;
++	int old_state;
++
++	if (dbus_info == NULL)
++		return;
++
++	if (dbus_info->pub.busstate == state)
++		return;
++	old_state = dbus_info->pub.busstate;
++	if (state == DBUS_STATE_DISCONNECT) {
++		DBUSERR(("DBUS disconnected\n"));
++	}
++
++	/* Ignore USB SUSPEND while not up yet */
++	if (state == DBUS_STATE_SLEEP && old_state != DBUS_STATE_UP)
++		return;
++
++	DBUSTRACE(("dbus state change from %d to to %d\n", old_state, state));
++
++	/* Don't update state if it's PnP firmware re-download */
++	if (state != DBUS_STATE_PNP_FWDL)
++		dbus_info->pub.busstate = state;
++	else
++		dbus_flowctrl_rx(handle, FALSE);
++	if (state == DBUS_STATE_SLEEP)
++		dbus_flowctrl_rx(handle, TRUE);
++	if (state == DBUS_STATE_UP) {
++		dbus_rxirbs_fill(dbus_info);
++		dbus_flowctrl_rx(handle, FALSE);
++	}
++
++	if (dbus_info->cbs && dbus_info->cbs->state_change)
++		dbus_info->cbs->state_change(dbus_info->cbarg, state);
++}
++
++/** Forward request for packet from lower DBUS layer to higher layer (e.g. dhd_linux.c) */
++static void *
++dbus_if_pktget(void *handle, uint len, bool send)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) handle;
++	void *p = NULL;
++
++	if (dbus_info == NULL)
++		return NULL;
++
++	if (dbus_info->cbs && dbus_info->cbs->pktget)
++		p = dbus_info->cbs->pktget(dbus_info->cbarg, len, send);
++	else
++		ASSERT(0);
++
++	return p;
++}
++
++/** Forward request to free packet from lower DBUS layer to higher layer (e.g. dhd_linux.c) */
++static void
++dbus_if_pktfree(void *handle, void *p, bool send)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) handle;
++
++	if (dbus_info == NULL)
++		return;
++
++	if (dbus_info->cbs && dbus_info->cbs->pktfree)
++		dbus_info->cbs->pktfree(dbus_info->cbarg, p, send);
++	else
++		ASSERT(0);
++}
++
++/** Lower DBUS level requests either a send or receive IRB */
++static struct dbus_irb*
++dbus_if_getirb(void *cbarg, bool send)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) cbarg;
++	struct exec_parms args;
++	struct dbus_irb *irb;
++
++	if ((dbus_info == NULL) || (dbus_info->pub.busstate != DBUS_STATE_UP))
++		return NULL;
++
++	if (send == TRUE) {
++		args.qdeq.q = dbus_info->tx_q;
++		irb = EXEC_TXLOCK(dbus_info, q_deq_exec, &args);
++	} else {
++		args.qdeq.q = dbus_info->rx_q;
++		irb = EXEC_RXLOCK(dbus_info, q_deq_exec, &args);
++	}
++
++	return irb;
++}
++
++/**
++ * Called as part of DBUS bus registration. Calls back into higher level (e.g. dhd_linux.c) probe
++ * function.
++ */
++static void *
++dbus_probe(void *arg, const char *desc, uint32 bustype, uint32 hdrlen)
++{
++	if (probe_cb) {
++		disc_arg = probe_cb(probe_arg, desc, bustype, hdrlen);
++		return disc_arg;
++	}
++
++	return (void *)DBUS_ERR;
++}
++
++/**
++ * As part of initialization, higher level (e.g. dhd_linux.c) requests DBUS to prepare for
++ * action.
++ */
++int
++dbus_register(int vid, int pid, probe_cb_t prcb,
++	disconnect_cb_t discb, void *prarg, void *param1, void *param2)
++{
++	int err;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	probe_cb = prcb;
++	disconnect_cb = discb;
++	probe_arg = prarg;
++
++	err = dbus_bus_register(vid, pid, dbus_probe, /* call lower DBUS level register function */
++		dbus_disconnect, NULL, &g_busintf, param1, param2);
++
++	return err;
++}
++
++int
++dbus_deregister()
++{
++	int ret;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	probe_cb = NULL;
++	ret = dbus_bus_deregister();
++	disconnect_cb = NULL;
++	probe_arg = NULL;
++
++	return ret;
++
++}
++
++/** As part of initialization, data structures have to be allocated and initialized */
++dbus_pub_t *
++dbus_attach(osl_t *osh, int rxsize, int nrxq, int ntxq, void *cbarg,
++	dbus_callbacks_t *cbs, dbus_extdl_t *extdl, struct shared_info *sh)
++{
++	dbus_info_t *dbus_info;
++	int err;
++
++	if ((g_busintf == NULL) || (g_busintf->attach == NULL) || (cbs == NULL))
++		return NULL;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if ((nrxq <= 0) || (ntxq <= 0))
++		return NULL;
++
++	dbus_info = MALLOC(osh, sizeof(dbus_info_t));
++	if (dbus_info == NULL)
++		return NULL;
++
++	bzero(dbus_info, sizeof(dbus_info_t));
++
++	/* BUS-specific driver interface (at a lower DBUS level) */
++	dbus_info->drvintf = g_busintf;
++	dbus_info->cbarg = cbarg;
++	dbus_info->cbs = cbs;
++
++	dbus_info->pub.sh = sh;
++	dbus_info->pub.osh = osh;
++	dbus_info->pub.rxsize = rxsize;
++
++#ifdef EHCI_FASTPATH_RX
++	atomic_set(&dbus_info->rx_outstanding, 0);
++#endif
++
++	dbus_info->pub.nrxq = nrxq;
++	dbus_info->rx_low_watermark = nrxq / 2;	/* keep enough posted rx urbs */
++	dbus_info->pub.ntxq = ntxq;
++	dbus_info->tx_low_watermark = ntxq / 4;	/* flow control when too many tx urbs posted */
++
++	dbus_info->tx_q = MALLOC(osh, sizeof(dbus_irbq_t));
++	if (dbus_info->tx_q == NULL)
++		goto error;
++	else {
++		bzero(dbus_info->tx_q, sizeof(dbus_irbq_t));
++		err = dbus_irbq_init(dbus_info, dbus_info->tx_q, ntxq, sizeof(dbus_irb_tx_t));
++		if (err != DBUS_OK)
++			goto error;
++	}
++
++	dbus_info->rx_q = MALLOC(osh, sizeof(dbus_irbq_t));
++	if (dbus_info->rx_q == NULL)
++		goto error;
++	else {
++		bzero(dbus_info->rx_q, sizeof(dbus_irbq_t));
++		err = dbus_irbq_init(dbus_info, dbus_info->rx_q, nrxq, sizeof(dbus_irb_rx_t));
++		if (err != DBUS_OK)
++			goto error;
++	}
++
++
++	dbus_info->bus_info = (void *)g_busintf->attach(&dbus_info->pub,
++		dbus_info, &dbus_intf_cbs);
++	if (dbus_info->bus_info == NULL)
++		goto error;
++
++	dbus_tx_timer_init(dbus_info);
++
++#if defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW)
++	/* Need to copy external image for re-download */
++	if (extdl && extdl->fw && (extdl->fwlen > 0)) {
++		dbus_info->extdl.fw = MALLOC(osh, extdl->fwlen);
++		if (dbus_info->extdl.fw) {
++			bcopy(extdl->fw, dbus_info->extdl.fw, extdl->fwlen);
++			dbus_info->extdl.fwlen = extdl->fwlen;
++		}
++	}
++
++	if (extdl && extdl->vars && (extdl->varslen > 0)) {
++		dbus_info->extdl.vars = MALLOC(osh, extdl->varslen);
++		if (dbus_info->extdl.vars) {
++			bcopy(extdl->vars, dbus_info->extdl.vars, extdl->varslen);
++			dbus_info->extdl.varslen = extdl->varslen;
++		}
++	}
++
++	if (dbus_download_firmware(&dbus_info->pub) != DBUS_OK)
++		goto error;
++#endif /* defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW) */
++
++	return (dbus_pub_t *)dbus_info;
++
++error:
++	dbus_detach((dbus_pub_t *)dbus_info);
++	return NULL;
++} /* dbus_attach */
++
++void
++dbus_detach(dbus_pub_t *pub)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++	osl_t *osh;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dbus_info == NULL)
++		return;
++
++	dbus_tx_timer_stop(dbus_info);
++
++	osh = pub->osh;
++
++	if (dbus_info->drvintf && dbus_info->drvintf->detach)
++		 dbus_info->drvintf->detach((dbus_pub_t *)dbus_info, dbus_info->bus_info);
++
++	if (dbus_info->tx_q) {
++		dbus_irbq_deinit(dbus_info, dbus_info->tx_q, sizeof(dbus_irb_tx_t));
++		MFREE(osh, dbus_info->tx_q, sizeof(dbus_irbq_t));
++		dbus_info->tx_q = NULL;
++	}
++
++	if (dbus_info->rx_q) {
++		dbus_irbq_deinit(dbus_info, dbus_info->rx_q, sizeof(dbus_irb_rx_t));
++		MFREE(osh, dbus_info->rx_q, sizeof(dbus_irbq_t));
++		dbus_info->rx_q = NULL;
++	}
++
++
++	if (dbus_info->extdl.fw && (dbus_info->extdl.fwlen > 0)) {
++		MFREE(osh, dbus_info->extdl.fw, dbus_info->extdl.fwlen);
++		dbus_info->extdl.fw = NULL;
++		dbus_info->extdl.fwlen = 0;
++	}
++
++	if (dbus_info->extdl.vars && (dbus_info->extdl.varslen > 0)) {
++		MFREE(osh, dbus_info->extdl.vars, dbus_info->extdl.varslen);
++		dbus_info->extdl.vars = NULL;
++		dbus_info->extdl.varslen = 0;
++	}
++
++	MFREE(osh, dbus_info, sizeof(dbus_info_t));
++} /* dbus_detach */
++
++#if (defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW))
++
++int dbus_download_firmware(dbus_pub_t *pub)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++	int err = DBUS_OK;
++
++	DBUSTRACE(("%s: state %d\n", __FUNCTION__, dbus_info->pub.busstate));
++
++	if (dbus_info->drvintf->dlneeded) {
++		if (dbus_info->drvintf->dlneeded(dbus_info->bus_info)) {
++			dbus_info->pub.busstate = DBUS_STATE_DL_PENDING;
++			err = dbus_do_download(dbus_info);
++			if (err == DBUS_OK) {
++				dbus_info->pub.busstate = DBUS_STATE_DL_DONE;
++			} else {
++				DBUSERR(("%s: download failed (%d)\n", __FUNCTION__, err));
++			}
++		}
++	}
++
++	return err;
++}
++
++#endif /* BCM_DNGL_EMBEDIMAGE || BCM_REQUEST_FW */
++
++/**
++ * higher layer requests us to 'up' the interface to the dongle. Prerequisite is that firmware (not
++ * bootloader) must be active in the dongle.
++ */
++int
++dbus_up(dbus_pub_t *pub)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++	int err = DBUS_OK;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dbus_info == NULL)
++		return DBUS_ERR;
++
++	if ((dbus_info->pub.busstate == DBUS_STATE_DL_DONE) ||
++		(dbus_info->pub.busstate == DBUS_STATE_DOWN) ||
++		(dbus_info->pub.busstate == DBUS_STATE_SLEEP)) {
++		if (dbus_info->drvintf && dbus_info->drvintf->up) {
++			err = dbus_info->drvintf->up(dbus_info->bus_info);
++
++			if (err == DBUS_OK) {
++				dbus_rxirbs_fill(dbus_info);
++			}
++		}
++	} else
++		err = DBUS_ERR;
++
++	return err;
++}
++
++/** higher layer requests us to 'down' the interface to the dongle. */
++int
++dbus_down(dbus_pub_t *pub)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dbus_info == NULL)
++		return DBUS_ERR;
++
++	dbus_tx_timer_stop(dbus_info);
++
++	if (dbus_info->pub.busstate == DBUS_STATE_UP ||
++		dbus_info->pub.busstate == DBUS_STATE_SLEEP) {
++		if (dbus_info->drvintf && dbus_info->drvintf->down)
++			return dbus_info->drvintf->down(dbus_info->bus_info);
++	}
++
++	return DBUS_ERR;
++}
++
++int
++dbus_shutdown(dbus_pub_t *pub)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dbus_info == NULL)
++		return DBUS_ERR;
++
++	if (dbus_info->drvintf && dbus_info->drvintf->shutdown)
++		return dbus_info->drvintf->shutdown(dbus_info->bus_info);
++
++	return DBUS_OK;
++}
++
++int
++dbus_stop(dbus_pub_t *pub)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dbus_info == NULL)
++		return DBUS_ERR;
++
++	if (dbus_info->pub.busstate == DBUS_STATE_UP ||
++		dbus_info->pub.busstate == DBUS_STATE_SLEEP) {
++		if (dbus_info->drvintf && dbus_info->drvintf->stop)
++			return dbus_info->drvintf->stop(dbus_info->bus_info);
++	}
++
++	return DBUS_ERR;
++}
++
++int dbus_send_txdata(dbus_pub_t *dbus, void *pktbuf)
++{
++#ifdef BCMSDIO
++	return dbus_send_pkt(dbus, pktbuf, NULL /* pktinfo */);
++#else
++	return dbus_send_pkt(dbus, pktbuf, pktbuf /* pktinfo */);
++#endif
++}
++
++int
++dbus_send_buf(dbus_pub_t *pub, uint8 *buf, int len, void *info)
++{
++	return dbus_send_irb(pub, buf, len, NULL, info);
++}
++
++int
++dbus_send_pkt(dbus_pub_t *pub, void *pkt, void *info)
++{
++	return dbus_send_irb(pub, NULL, 0, pkt, info);
++}
++
++int
++dbus_send_ctl(dbus_pub_t *pub, uint8 *buf, int len)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++
++	if (dbus_info == NULL)
++		return DBUS_ERR;
++
++	if (dbus_info->pub.busstate == DBUS_STATE_UP ||
++		dbus_info->pub.busstate == DBUS_STATE_SLEEP) {
++		if (dbus_info->drvintf && dbus_info->drvintf->send_ctl)
++			return dbus_info->drvintf->send_ctl(dbus_info->bus_info, buf, len);
++	}
++
++	return DBUS_ERR;
++}
++
++int
++dbus_recv_ctl(dbus_pub_t *pub, uint8 *buf, int len)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++
++	if ((dbus_info == NULL) || (buf == NULL))
++		return DBUS_ERR;
++
++	if (dbus_info->pub.busstate == DBUS_STATE_UP ||
++		dbus_info->pub.busstate == DBUS_STATE_SLEEP) {
++		if (dbus_info->drvintf && dbus_info->drvintf->recv_ctl)
++			return dbus_info->drvintf->recv_ctl(dbus_info->bus_info, buf, len);
++	}
++
++	return DBUS_ERR;
++}
++
++/** Only called via RPC (Dec 2012) */
++int
++dbus_recv_bulk(dbus_pub_t *pub, uint32 ep_idx)
++{
++#ifdef EHCI_FASTPATH_RX
++	/* 2nd bulk in not supported for EHCI_FASTPATH_RX */
++	ASSERT(0);
++#else
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++
++	dbus_irb_rx_t *rxirb;
++	struct exec_parms args;
++	int status;
++
++
++	if (dbus_info == NULL)
++		return DBUS_ERR;
++
++	args.qdeq.q = dbus_info->rx_q;
++	if (dbus_info->pub.busstate == DBUS_STATE_UP) {
++		if (dbus_info->drvintf && dbus_info->drvintf->recv_irb_from_ep) {
++			if ((rxirb = (EXEC_RXLOCK(dbus_info, q_deq_exec, &args))) != NULL) {
++				status = dbus_info->drvintf->recv_irb_from_ep(dbus_info->bus_info,
++					rxirb, ep_idx);
++				if (status == DBUS_ERR_RXDROP) {
++					bzero(rxirb, sizeof(dbus_irb_rx_t));
++					args.qenq.q = dbus_info->rx_q;
++					args.qenq.b = (dbus_irb_t *) rxirb;
++					EXEC_RXLOCK(dbus_info, q_enq_exec, &args);
++				}
++			}
++		}
++	}
++#endif /* EHCI_FASTPATH_RX */
++
++	return DBUS_ERR;
++}
++
++/** only called by dhd_cdc.c (Dec 2012) */
++int
++dbus_poll_intr(dbus_pub_t *pub)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++
++	int status = DBUS_ERR;
++
++	if (dbus_info == NULL)
++		return DBUS_ERR;
++
++	if (dbus_info->pub.busstate == DBUS_STATE_UP) {
++		if (dbus_info->drvintf && dbus_info->drvintf->recv_irb_from_ep) {
++			status = dbus_info->drvintf->recv_irb_from_ep(dbus_info->bus_info,
++				NULL, 0xff);
++		}
++	}
++	return status;
++}
++
++/** called by nobody (Dec 2012) */
++void *
++dbus_pktget(dbus_pub_t *pub, int len)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++
++	if ((dbus_info == NULL) || (len < 0))
++		return NULL;
++
++	return PKTGET(dbus_info->pub.osh, len, TRUE);
++}
++
++/** called by nobody (Dec 2012) */
++void
++dbus_pktfree(dbus_pub_t *pub, void* pkt)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++
++	if ((dbus_info == NULL) || (pkt == NULL))
++		return;
++
++	PKTFREE(dbus_info->pub.osh, pkt, TRUE);
++}
++
++/** called by nobody (Dec 2012) */
++int
++dbus_get_stats(dbus_pub_t *pub, dbus_stats_t *stats)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++
++	if ((dbus_info == NULL) || (stats == NULL))
++		return DBUS_ERR;
++
++	bcopy(&dbus_info->pub.stats, stats, sizeof(dbus_stats_t));
++
++	return DBUS_OK;
++}
++
++int
++dbus_get_attrib(dbus_pub_t *pub, dbus_attrib_t *attrib)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++	int err = DBUS_ERR;
++
++	if ((dbus_info == NULL) || (attrib == NULL))
++		return DBUS_ERR;
++
++	if (dbus_info->drvintf && dbus_info->drvintf->get_attrib) {
++		err = dbus_info->drvintf->get_attrib(dbus_info->bus_info,
++		&dbus_info->pub.attrib);
++	}
++
++	bcopy(&dbus_info->pub.attrib, attrib, sizeof(dbus_attrib_t));
++	return err;
++}
++
++int
++dbus_get_device_speed(dbus_pub_t *pub)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++
++	if (dbus_info == NULL)
++		return INVALID_SPEED;
++
++	return (dbus_info->pub.device_speed);
++}
++
++int
++dbus_set_config(dbus_pub_t *pub, dbus_config_t *config)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++	int err = DBUS_ERR;
++
++	if ((dbus_info == NULL) || (config == NULL))
++		return DBUS_ERR;
++
++	if (dbus_info->drvintf && dbus_info->drvintf->set_config) {
++		err = dbus_info->drvintf->set_config(dbus_info->bus_info,
++			config);
++
++		if ((config->config_id == DBUS_CONFIG_ID_AGGR_LIMIT) &&
++			(!err) &&
++			(dbus_info->pub.busstate == DBUS_STATE_UP)) {
++			dbus_rxirbs_fill(dbus_info);
++		}
++	}
++
++	return err;
++}
++
++int
++dbus_get_config(dbus_pub_t *pub, dbus_config_t *config)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++	int err = DBUS_ERR;
++
++	if ((dbus_info == NULL) || (config == NULL))
++		return DBUS_ERR;
++
++	if (dbus_info->drvintf && dbus_info->drvintf->get_config) {
++		err = dbus_info->drvintf->get_config(dbus_info->bus_info,
++		config);
++	}
++
++	return err;
++}
++
++int
++dbus_set_errmask(dbus_pub_t *pub, uint32 mask)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++	int err = DBUS_OK;
++
++	if (dbus_info == NULL)
++		return DBUS_ERR;
++
++	dbus_info->errmask = mask;
++	return err;
++}
++
++int
++dbus_pnp_resume(dbus_pub_t *pub, int *fw_reload)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++	int err = DBUS_ERR;
++	bool fwdl = FALSE;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dbus_info == NULL)
++		return DBUS_ERR;
++
++	if (dbus_info->pub.busstate == DBUS_STATE_UP) {
++		return DBUS_OK;
++	}
++
++
++#if defined(BCM_DNGL_EMBEDIMAGE)
++	if (dbus_info->drvintf->device_exists &&
++		dbus_info->drvintf->device_exists(dbus_info->bus_info)) {
++		if (dbus_info->drvintf->dlneeded) {
++			if (dbus_info->drvintf->dlneeded(dbus_info->bus_info)) {
++				err = dbus_do_download(dbus_info);
++				if (err == DBUS_OK) {
++					fwdl = TRUE;
++				}
++				if (dbus_info->pub.busstate == DBUS_STATE_DL_DONE)
++					dbus_up(&dbus_info->pub);
++			}
++		}
++	} else {
++		return DBUS_ERR;
++	}
++#endif /* BCM_DNGL_EMBEDIMAGE */
++
++	if (dbus_info->drvintf->pnp) {
++		err = dbus_info->drvintf->pnp(dbus_info->bus_info,
++			DBUS_PNP_RESUME);
++	}
++
++	if (dbus_info->drvintf->recv_needed) {
++		if (dbus_info->drvintf->recv_needed(dbus_info->bus_info)) {
++			/* Refill after sleep/hibernate */
++			dbus_rxirbs_fill(dbus_info);
++		}
++	}
++
++#if defined(BCM_DNGL_EMBEDIMAGE)
++	if (fwdl == TRUE) {
++		dbus_if_state_change(dbus_info, DBUS_STATE_PNP_FWDL);
++	}
++#endif /* BCM_DNGL_EMBEDIMAGE */
++
++	if (fw_reload)
++		*fw_reload = fwdl;
++
++	return err;
++} /* dbus_pnp_resume */
++
++int
++dbus_pnp_sleep(dbus_pub_t *pub)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++	int err = DBUS_ERR;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dbus_info == NULL)
++		return DBUS_ERR;
++
++	dbus_tx_timer_stop(dbus_info);
++
++	if (dbus_info->drvintf && dbus_info->drvintf->pnp) {
++		err = dbus_info->drvintf->pnp(dbus_info->bus_info,
++			DBUS_PNP_SLEEP);
++	}
++
++	return err;
++}
++
++int
++dbus_pnp_disconnect(dbus_pub_t *pub)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++	int err = DBUS_ERR;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dbus_info == NULL)
++		return DBUS_ERR;
++
++	dbus_tx_timer_stop(dbus_info);
++
++	if (dbus_info->drvintf && dbus_info->drvintf->pnp) {
++		err = dbus_info->drvintf->pnp(dbus_info->bus_info,
++			DBUS_PNP_DISCONNECT);
++	}
++
++	return err;
++}
++
++int
++dbus_iovar_op(dbus_pub_t *pub, const char *name,
++	void *params, int plen, void *arg, int len, bool set)
++{
++	dbus_info_t *dbus_info = (dbus_info_t *) pub;
++	int err = DBUS_ERR;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (dbus_info == NULL)
++		return DBUS_ERR;
++
++	if (dbus_info->drvintf && dbus_info->drvintf->iovar_op) {
++		err = dbus_info->drvintf->iovar_op(dbus_info->bus_info,
++			name, params, plen, arg, len, set);
++	}
++
++	return err;
++}
++
++
++void *
++dhd_dbus_txq(const dbus_pub_t *pub)
++{
++	return NULL;
++}
++
++uint
++dhd_dbus_hdrlen(const dbus_pub_t *pub)
++{
++	return 0;
++}
++
++void *
++dbus_get_devinfo(dbus_pub_t *pub)
++{
++	return pub->dev_info;
++}
++
++#if defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW)
++
++static int
++dbus_otp(dbus_info_t *dbus_info, uint16 *boardtype, uint16 *boardrev)
++{
++	uint32 value = 0;
++	uint8 *cis;
++	uint16 *otpinfo;
++	uint32 i;
++	bool standard_cis = TRUE;
++	uint8 tup, tlen;
++	bool btype_present = FALSE;
++	bool brev_present = FALSE;
++	int ret;
++	int devid;
++	uint16 btype = 0;
++	uint16 brev = 0;
++	uint32 otp_size = 0, otp_addr = 0, otp_sw_rgn = 0;
++
++	if (dbus_info == NULL || dbus_info->drvintf == NULL ||
++		dbus_info->drvintf->readreg == NULL)
++		return DBUS_ERR;
++
++	devid = dbus_info->pub.attrib.devid;
++
++	if ((devid == BCM43234_CHIP_ID) || (devid == BCM43235_CHIP_ID) ||
++		(devid == BCM43236_CHIP_ID)) {
++
++		otp_size = BCM_OTP_SIZE_43236;
++		otp_sw_rgn = BCM_OTP_SW_RGN_43236;
++		otp_addr = BCM_OTP_ADDR_43236;
++
++	} else {
++		return DBUS_ERR_NVRAM;
++	}
++
++	cis = MALLOC(dbus_info->pub.osh, otp_size * 2);
++	if (cis == NULL)
++		return DBUS_ERR;
++
++	otpinfo = (uint16 *) cis;
++
++	for (i = 0; i < otp_size; i++) {
++
++		ret = dbus_info->drvintf->readreg(dbus_info->bus_info,
++			otp_addr + ((otp_sw_rgn + i) << 1), 2, &value);
++
++		if (ret != DBUS_OK) {
++			MFREE(dbus_info->pub.osh, cis, otp_size * 2);
++			return ret;
++		}
++		otpinfo[i] = (uint16) value;
++	}
++
++	for (i = 0; i < (otp_size << 1); ) {
++
++		if (standard_cis) {
++			tup = cis[i++];
++			if (tup == CISTPL_NULL || tup == CISTPL_END)
++				tlen = 0;
++			else
++				tlen = cis[i++];
++		} else {
++			if (cis[i] == CISTPL_NULL || cis[i] == CISTPL_END) {
++				tlen = 0;
++				tup = cis[i];
++			} else {
++				tlen = cis[i];
++				tup = CISTPL_BRCM_HNBU;
++			}
++			++i;
++		}
++
++		if (tup == CISTPL_END || (i + tlen) >= (otp_size << 1)) {
++			break;
++		}
++
++		switch (tup) {
++
++		case CISTPL_BRCM_HNBU:
++
++			switch (cis[i]) {
++
++			case HNBU_BOARDTYPE:
++
++				btype = (uint16) ((cis[i + 2] << 8) + cis[i + 1]);
++				btype_present = TRUE;
++				DBUSTRACE(("%s: HNBU_BOARDTYPE = 0x%2x\n", __FUNCTION__,
++					(uint32)btype));
++				break;
++
++			case HNBU_BOARDREV:
++
++				if (tlen == 2)
++					brev = (uint16) cis[i + 1];
++				else
++					brev = (uint16) ((cis[i + 2] << 8) + cis[i + 1]);
++				brev_present = TRUE;
++				DBUSTRACE(("%s: HNBU_BOARDREV =  0x%2x\n", __FUNCTION__,
++					(uint32)*boardrev));
++				break;
++
++			case HNBU_HNBUCIS:
++				DBUSTRACE(("%s: HNBU_HNBUCIS\n", __FUNCTION__));
++				tlen++;
++				standard_cis = FALSE;
++				break;
++			}
++			break;
++		}
++
++		i += tlen;
++	}
++
++	MFREE(dbus_info->pub.osh, cis, otp_size * 2);
++
++	if (btype_present == TRUE && brev_present == TRUE) {
++		*boardtype = btype;
++		*boardrev = brev;
++		DBUSERR(("otp boardtype = 0x%2x boardrev = 0x%2x\n",
++			*boardtype, *boardrev));
++
++		return DBUS_OK;
++	}
++	else
++		return DBUS_ERR;
++} /* dbus_otp */
++
++static int
++dbus_select_nvram(dbus_info_t *dbus_info, int8 *jumbonvram, int jumbolen,
++uint16 boardtype, uint16 boardrev, int8 **nvram, int *nvram_len)
++{
++	/* Multi board nvram file format is contenation of nvram info with \r
++	*  The file format for two contatenated set is
++	*  \nBroadcom Jumbo Nvram file\nfirst_set\nsecond_set\nthird_set\n
++	*/
++	uint8 *nvram_start = NULL, *nvram_end = NULL;
++	uint8 *nvram_start_prev = NULL, *nvram_end_prev = NULL;
++	uint16 btype = 0, brev = 0;
++	int len  = 0;
++	char *field;
++
++	*nvram = NULL;
++	*nvram_len = 0;
++
++	if (strncmp(BCM_JUMBO_START, jumbonvram, strlen(BCM_JUMBO_START))) {
++		/* single nvram file in the native format */
++		DBUSTRACE(("%s: Non-Jumbo NVRAM File \n", __FUNCTION__));
++		*nvram = jumbonvram;
++		*nvram_len = jumbolen;
++		return DBUS_OK;
++	} else {
++		DBUSTRACE(("%s: Jumbo NVRAM File \n", __FUNCTION__));
++	}
++
++	/* sanity test the end of the config sets for proper ending */
++	if (jumbonvram[jumbolen - 1] != BCM_JUMBO_NVRAM_DELIMIT ||
++		jumbonvram[jumbolen - 2] != '\0') {
++		DBUSERR(("%s: Bad Jumbo NVRAM file format\n", __FUNCTION__));
++		return DBUS_JUMBO_BAD_FORMAT;
++	}
++
++	dbus_info->nvram_nontxt = DBUS_NVRAM_NONTXT;
++
++	nvram_start = jumbonvram;
++
++	while (*nvram_start != BCM_JUMBO_NVRAM_DELIMIT && len < jumbolen) {
++
++		/* consume the  first file info line
++		* \nBroadcom Jumbo Nvram file\nfile1\n ...
++		*/
++		len ++;
++		nvram_start ++;
++	}
++
++	nvram_end = nvram_start;
++
++	/* search for "boardrev=0xabcd" and "boardtype=0x1234" information in
++	* the concatenated nvram config files /sets
++	*/
++
++	while (len < jumbolen) {
++
++		if (*nvram_end == '\0') {
++			/* end of a config set is marked by multiple null characters */
++			len ++;
++			nvram_end ++;
++			DBUSTRACE(("%s: NULL chr len = %d char = 0x%x\n", __FUNCTION__,
++				len, *nvram_end));
++			continue;
++
++		} else if (*nvram_end == BCM_JUMBO_NVRAM_DELIMIT) {
++
++			/* config set delimiter is reached */
++			/* check if next config set is present or not
++			*  return  if next config is not present
++			*/
++
++			/* start search the next config set */
++			nvram_start_prev = nvram_start;
++			nvram_end_prev = nvram_end;
++
++			nvram_end ++;
++			nvram_start = nvram_end;
++			btype = brev = 0;
++			DBUSTRACE(("%s: going to next record len = %d "
++					"char = 0x%x \n", __FUNCTION__, len, *nvram_end));
++			len ++;
++			if (len >= jumbolen) {
++
++				*nvram = nvram_start_prev;
++				*nvram_len = (int)(nvram_end_prev - nvram_start_prev);
++
++				DBUSTRACE(("%s: no more len = %d nvram_end = 0x%p",
++					__FUNCTION__, len, nvram_end));
++
++				return DBUS_JUMBO_NOMATCH;
++
++			} else {
++				continue;
++			}
++
++		} else {
++
++			DBUSTRACE(("%s: config str = %s\n", __FUNCTION__, nvram_end));
++
++			if (bcmp(nvram_end, "boardtype", strlen("boardtype")) == 0) {
++
++				field = strchr(nvram_end, '=');
++				field++;
++				btype = (uint16)bcm_strtoul(field, NULL, 0);
++
++				DBUSTRACE(("%s: btype = 0x%x boardtype = 0x%x \n", __FUNCTION__,
++					btype, boardtype));
++			}
++
++			if (bcmp(nvram_end, "boardrev", strlen("boardrev")) == 0) {
++
++				field = strchr(nvram_end, '=');
++				field++;
++				brev = (uint16)bcm_strtoul(field, NULL, 0);
++
++				DBUSTRACE(("%s: brev = 0x%x boardrev = 0x%x \n", __FUNCTION__,
++					brev, boardrev));
++			}
++			if (btype == boardtype && brev == boardrev) {
++				/* locate nvram config set end - ie.find '\r' char */
++				while (*nvram_end != BCM_JUMBO_NVRAM_DELIMIT)
++					nvram_end ++;
++				*nvram = nvram_start;
++				*nvram_len = (int) (nvram_end - nvram_start);
++				DBUSTRACE(("found len = %d nvram_start = 0x%p "
++					"nvram_end = 0x%p\n", *nvram_len, nvram_start, nvram_end));
++				return DBUS_OK;
++			}
++
++			len += (strlen(nvram_end) + 1);
++			nvram_end += (strlen(nvram_end) + 1);
++		}
++	}
++	return DBUS_JUMBO_NOMATCH;
++} /* dbus_select_nvram */
++
++#if defined(BCM_DNGL_EMBEDIMAGE)
++
++/* store the global osh handle */
++static osl_t *osl_handle = NULL;
++
++/** this function is a combination of trx.c and bcmdl.c plus dbus adaptation */
++static int
++dbus_zlib_decomp(dbus_info_t *dbus_info)
++{
++
++	int method, flags, len, status;
++	unsigned int uncmp_len, uncmp_crc, dec_crc, crc_init;
++	struct trx_header *trx, *newtrx;
++	unsigned char *file = NULL;
++	unsigned char gz_magic[2] = {0x1f, 0x8b}; /* gzip magic header */
++	z_stream d_stream;
++	unsigned char unused;
++	int actual_len = -1;
++	unsigned char *headers;
++	unsigned int trxhdrsize, nvramsize, decomp_memsize, i;
++
++	(void)actual_len;
++	(void)unused;
++	(void)crc_init;
++
++	osl_handle = dbus_info->pub.osh;
++	dbus_info->orig_fw = NULL;
++
++	headers = dbus_info->fw;
++	/* Extract trx header */
++	trx = (struct trx_header *)headers;
++	trxhdrsize = sizeof(struct trx_header);
++
++	if (ltoh32(trx->magic) != TRX_MAGIC) {
++		DBUSERR(("%s: Error: trx bad hdr %x\n", __FUNCTION__,
++			ltoh32(trx->magic)));
++		return -1;
++	}
++
++	headers += sizeof(struct trx_header);
++
++	if (ltoh32(trx->flag_version) & TRX_UNCOMP_IMAGE) {
++		actual_len = ltoh32(trx->offsets[TRX_OFFSETS_DLFWLEN_IDX]) +
++		                     sizeof(struct trx_header);
++		DBUSERR(("%s: not a compressed image\n", __FUNCTION__));
++		return 0;
++	} else {
++		/* Extract the gzip header info */
++		if ((*headers++ != gz_magic[0]) || (*headers++ != gz_magic[1])) {
++			DBUSERR(("%s: Error: gzip bad hdr\n", __FUNCTION__));
++			return -1;
++		}
++
++		method = (int) *headers++;
++		flags = (int) *headers++;
++
++		if (method != Z_DEFLATED || (flags & RESERVED) != 0) {
++			DBUSERR(("%s: Error: gzip bad hdr not a Z_DEFLATED file\n", __FUNCTION__));
++			return -1;
++		}
++	}
++
++	/* Discard time, xflags and OS code: */
++	for (len = 0; len < 6; len++)
++		unused = *headers++;
++
++	if ((flags & EXTRA_FIELD) != 0) { /* skip the extra field */
++		len = (uint32) *headers++;
++		len += ((uint32)*headers++)<<8;
++		/* len is garbage if EOF but the loop below will quit anyway */
++		while (len-- != 0) unused = *headers++;
++	}
++
++	if ((flags & ORIG_NAME) != 0) { /* skip the original file name */
++		while (*headers++ && (*headers != 0));
++	}
++
++	if ((flags & COMMENT) != 0) {   /* skip the .gz file comment */
++		while (*headers++ && (*headers != 0));
++	}
++
++	if ((flags & HEAD_CRC) != 0) {  /* skip the header crc */
++		for (len = 0; len < 2; len++) unused = *headers++;
++	}
++
++	headers++;
++
++
++	/* create space for the uncompressed file */
++	/* the space is for trx header, uncompressed image  and nvram file */
++	/* with typical compression of 0.6, space double of firmware should be ok */
++
++	decomp_memsize = dbus_info->fwlen * 2;
++	dbus_info->decomp_memsize = decomp_memsize;
++	if (!(file = MALLOC(osl_handle, decomp_memsize))) {
++		DBUSERR(("%s: check_file : failed malloc\n", __FUNCTION__));
++		goto err;
++	}
++
++	bzero(file, decomp_memsize);
++
++	/* Initialise the decompression struct */
++	d_stream.next_in = NULL;
++	d_stream.avail_in = 0;
++	d_stream.next_out = NULL;
++	d_stream.avail_out = decomp_memsize - trxhdrsize;
++	d_stream.zalloc = (alloc_func)0;
++	d_stream.zfree = (free_func)0;
++	if (inflateInit2(&d_stream, -15) != Z_OK) {
++		DBUSERR(("%s: Err: inflateInit2\n", __FUNCTION__));
++		goto err;
++	}
++
++	/* Inflate the code */
++	d_stream.next_in = headers;
++	d_stream.avail_in = ltoh32(trx->len);
++	d_stream.next_out = (unsigned char*)(file + trxhdrsize);
++
++	status = inflate(&d_stream, Z_SYNC_FLUSH);
++
++	if (status != Z_STREAM_END)	{
++		DBUSERR(("%s: Error: decompression failed\n", __FUNCTION__));
++		goto err;
++	}
++
++	uncmp_crc = *d_stream.next_in++;
++	uncmp_crc |= *d_stream.next_in++<<8;
++	uncmp_crc |= *d_stream.next_in++<<16;
++	uncmp_crc |= *d_stream.next_in++<<24;
++
++	uncmp_len = *d_stream.next_in++;
++	uncmp_len |= *d_stream.next_in++<<8;
++	uncmp_len |= *d_stream.next_in++<<16;
++	uncmp_len |= *d_stream.next_in++<<24;
++
++	actual_len = (int) (d_stream.next_in - (unsigned char *)trx);
++
++	inflateEnd(&d_stream);
++
++	/* Do a CRC32 on the uncompressed data */
++	crc_init = crc32(0L, Z_NULL, 0);
++	dec_crc = crc32(crc_init, file + trxhdrsize, uncmp_len);
++
++	if (dec_crc != uncmp_crc) {
++		DBUSERR(("%s: decompression: bad crc check \n", __FUNCTION__));
++		goto err;
++	}
++	else {
++		DBUSTRACE(("%s: decompression: good crc check \n", __FUNCTION__));
++	}
++
++	/* rebuild the new trx header and calculate crc */
++	newtrx = (struct trx_header *)file;
++	newtrx->magic = trx->magic;
++	/* add the uncompressed image flag */
++	newtrx->flag_version = trx->flag_version;
++	newtrx->flag_version  |= htol32(TRX_UNCOMP_IMAGE);
++	newtrx->offsets[TRX_OFFSETS_DLFWLEN_IDX] = htol32(uncmp_len);
++	newtrx->offsets[TRX_OFFSETS_JUMPTO_IDX] = trx->offsets[TRX_OFFSETS_JUMPTO_IDX];
++	newtrx->offsets[TRX_OFFSETS_NVM_LEN_IDX] = trx->offsets[TRX_OFFSETS_NVM_LEN_IDX];
++
++	nvramsize = ltoh32(trx->offsets[TRX_OFFSETS_NVM_LEN_IDX]);
++
++	/* the original firmware has nvram file appended */
++	/* copy the nvram file to uncompressed firmware */
++
++	if (nvramsize) {
++		if (nvramsize + uncmp_len > decomp_memsize) {
++			DBUSERR(("%s: nvram cannot be accomodated\n", __FUNCTION__));
++			goto err;
++		}
++		bcopy(d_stream.next_in, &file[uncmp_len], nvramsize);
++		uncmp_len += nvramsize;
++	}
++
++	/* add trx header size to uncmp_len */
++	uncmp_len += trxhdrsize;
++	uncmp_len = ROUNDUP(uncmp_len, 4096);
++	newtrx->len	= htol32(uncmp_len);
++
++	/* Calculate CRC over header */
++	newtrx->crc32 = hndcrc32((uint8 *)&newtrx->flag_version,
++	sizeof(struct trx_header) - OFFSETOF(struct trx_header, flag_version),
++	CRC32_INIT_VALUE);
++
++	/* Calculate CRC over data */
++	for (i = trxhdrsize; i < (uncmp_len); ++i)
++				newtrx->crc32 = hndcrc32((uint8 *)&file[i], 1, newtrx->crc32);
++	newtrx->crc32 = htol32(newtrx->crc32);
++
++	dbus_info->orig_fw = dbus_info->fw;
++	dbus_info->origfw_len = dbus_info->fwlen;
++	dbus_info->image = dbus_info->fw = file;
++	dbus_info->image_len = dbus_info->fwlen = uncmp_len;
++
++	return 0;
++
++err:
++	if (file)
++		free(file);
++	return -1;
++} /* dbus_zlib_decomp */
++
++void *
++dbus_zlib_calloc(int num, int size)
++{
++	uint *ptr;
++	uint totalsize;
++
++	if (osl_handle == NULL)
++		return NULL;
++
++	totalsize = (num * (size + 1));
++
++	ptr  = MALLOC(osl_handle, totalsize);
++
++	if (ptr == NULL)
++		return NULL;
++	bzero(ptr, totalsize);
++
++	/* store the size in the first integer space */
++
++	ptr[0] = totalsize;
++
++	return ((void *) &ptr[1]);
++}
++
++void
++dbus_zlib_free(void *ptr)
++{
++	uint totalsize;
++	uchar *memptr = (uchar *)ptr;
++
++	if (ptr && osl_handle) {
++		memptr -= sizeof(uint);
++		totalsize = *(uint *) memptr;
++		MFREE(osl_handle, memptr, totalsize);
++	}
++}
++
++#endif /* #if defined(BCM_DNGL_EMBEDIMAGE) */
++#endif /* #if defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW) */
++
++
++#ifdef LINUX_EXTERNAL_MODULE_DBUS
++
++static int __init
++bcm_dbus_module_init(void)
++{
++	printf("Inserting bcm_dbus module \n");
++	return 0;
++}
++
++static void __exit
++bcm_dbus_module_exit(void)
++{
++	printf("Removing bcm_dbus module \n");
++	return;
++}
++
++EXPORT_SYMBOL(dbus_pnp_sleep);
++EXPORT_SYMBOL(dbus_register);
++EXPORT_SYMBOL(dbus_get_devinfo);
++EXPORT_SYMBOL(dbus_detach);
++EXPORT_SYMBOL(dbus_get_attrib);
++EXPORT_SYMBOL(dbus_down);
++EXPORT_SYMBOL(dbus_pnp_resume);
++EXPORT_SYMBOL(dbus_set_config);
++EXPORT_SYMBOL(dbus_flowctrl_rx);
++EXPORT_SYMBOL(dbus_up);
++EXPORT_SYMBOL(dbus_get_device_speed);
++EXPORT_SYMBOL(dbus_send_pkt);
++EXPORT_SYMBOL(dbus_recv_ctl);
++EXPORT_SYMBOL(dbus_attach);
++EXPORT_SYMBOL(dbus_deregister);
++
++MODULE_LICENSE("GPL");
++
++module_init(bcm_dbus_module_init);
++module_exit(bcm_dbus_module_exit);
++
++#endif  /* #ifdef LINUX_EXTERNAL_MODULE_DBUS */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dbus_usb.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dbus_usb.c
+new file mode 100644
+index 000000000..ea59b3e96
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dbus_usb.c
+@@ -0,0 +1,1227 @@
++/*
++ * Dongle BUS interface for USB, OS independent
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dbus_usb.c 565557 2015-06-22 19:29:44Z $
++ */
++
++/**
++ * @file @brief
++ * This file contains DBUS code that is USB, but not OS specific. DBUS is a Broadcom proprietary
++ * host specific abstraction layer.
++ */
++
++#include <osl.h>
++#include <bcmdefs.h>
++#include <bcmutils.h>
++#include <dbus.h>
++#include <usbrdl.h>
++#include <bcmdevs.h>
++#include <bcmendian.h>
++
++#if defined(BCM_DNGL_EMBEDIMAGE)
++#ifdef EMBED_IMAGE_43236b
++#include "rtecdc_43236b.h"
++#endif /* EMBED_IMAGE_43236b */
++#ifdef EMBED_IMAGE_43526a
++#include "rtecdc_43526a.h"
++#endif /* EMBED_IMAGE_43526a */
++#ifdef EMBED_IMAGE_43526b
++#include "rtecdc_43526b.h"
++#endif /* EMBED_IMAGE_43526b */
++#ifdef EMBED_IMAGE_43242a0
++#include "rtecdc_43242a0.h"
++#endif /* EMBED_IMAGE_43242a0 */
++#ifdef EMBED_IMAGE_43143a0
++#include "rtecdc_43143a0.h"
++#endif /* EMBED_IMAGE_43143a0 */
++#ifdef EMBED_IMAGE_43143b0
++#include "rtecdc_43143b0.h"
++#endif /* EMBED_IMAGE_43143b0 */
++#ifdef EMBED_IMAGE_4350a0
++#include "rtecdc_4350a0.h"
++#endif /* EMBED_IMAGE_4350a0 */
++#ifdef EMBED_IMAGE_4350b0
++#include "rtecdc_4350b0.h"
++#endif /* EMBED_IMAGE_4350b0 */
++#ifdef EMBED_IMAGE_4350b1
++#include "rtecdc_4350b1.h"
++#endif /* EMBED_IMAGE_4350b1 */
++#ifdef EMBED_IMAGE_4350c0
++#include "rtecdc_4350c0.h"
++#endif /* EMBED_IMAGE_4350c0 */
++#ifdef EMBED_IMAGE_4350c1
++#include "rtecdc_4350c1.h"
++#endif /* EMBED_IMAGE_4350c1 */
++#ifdef EMBED_IMAGE_43556b1
++#include "rtecdc_43556b1.h"
++#endif /* EMBED_IMAGE_43556b1 */
++#ifdef EMBED_IMAGE_43569a0
++#include "rtecdc_43569a0.h"
++#endif /* EMBED_IMAGE_43569a0 */
++#ifdef EMBED_IMAGE_GENERIC
++#include "rtecdc.h"
++#endif
++#endif /* BCM_DNGL_EMBEDIMAGE */
++
++
++#define USB_DLIMAGE_RETRY_TIMEOUT    3000    /* retry Timeout */
++#define USB_SFLASH_DLIMAGE_SPINWAIT  150     /* in unit of ms */
++#define USB_SFLASH_DLIMAGE_LIMIT     2000    /* spinwait limit (ms) */
++#define POSTBOOT_ID                  0xA123  /* ID to detect if dongle has boot up */
++#define USB_RESETCFG_SPINWAIT        1       /* wait after resetcfg (ms) */
++#define USB_DEV_ISBAD(u)             (u->pub->attrib.devid == 0xDEAD)
++#define USB_DLGO_SPINWAIT            100     /* wait after DL_GO (ms) */
++#define TEST_CHIP                    0x4328
++
++typedef struct {
++	dbus_pub_t  *pub;
++
++	void        *cbarg;
++	dbus_intf_callbacks_t *cbs;  /** callbacks into higher DBUS level (dbus.c) */
++	dbus_intf_t *drvintf;
++	void        *usbosl_info;
++	uint32      rdlram_base_addr;
++	uint32      rdlram_size;
++} usb_info_t;
++
++/*
++ * Callbacks common to all USB
++ */
++static void dbus_usb_disconnect(void *handle);
++static void dbus_usb_send_irb_timeout(void *handle, dbus_irb_tx_t *txirb);
++static void dbus_usb_send_irb_complete(void *handle, dbus_irb_tx_t *txirb, int status);
++static void dbus_usb_recv_irb_complete(void *handle, dbus_irb_rx_t *rxirb, int status);
++static void dbus_usb_errhandler(void *handle, int err);
++static void dbus_usb_ctl_complete(void *handle, int type, int status);
++static void dbus_usb_state_change(void *handle, int state);
++static struct dbus_irb* dbus_usb_getirb(void *handle, bool send);
++static void dbus_usb_rxerr_indicate(void *handle, bool on);
++static int dbus_usb_resetcfg(usb_info_t *usbinfo);
++static int dbus_usb_iovar_op(void *bus, const char *name,
++	void *params, int plen, void *arg, int len, bool set);
++static int dbus_iovar_process(usb_info_t* usbinfo, const char *name,
++                 void *params, int plen, void *arg, int len, bool set);
++static int dbus_usb_doiovar(usb_info_t *bus, const bcm_iovar_t *vi, uint32 actionid,
++	const char *name, void *params, int plen, void *arg, int len, int val_size);
++static int dhdusb_downloadvars(usb_info_t *bus, void *arg, int len);
++
++static int dbus_usb_dl_writeimage(usb_info_t *usbinfo, uint8 *fw, int fwlen);
++static int dbus_usb_dlstart(void *bus, uint8 *fw, int len);
++static bool dbus_usb_dlneeded(void *bus);
++static int dbus_usb_dlrun(void *bus);
++static int dbus_usb_rdl_dwnld_state(usb_info_t *usbinfo);
++
++#ifdef BCM_DNGL_EMBEDIMAGE
++static bool dbus_usb_device_exists(void *bus);
++#endif
++
++/* OS specific */
++extern bool dbus_usbos_dl_cmd(void *info, uint8 cmd, void *buffer, int buflen);
++extern int dbus_usbos_wait(void *info, uint16 ms);
++extern int dbus_write_membytes(usb_info_t *usbinfo, bool set, uint32 address,
++	uint8 *data, uint size);
++extern bool dbus_usbos_dl_send_bulk(void *info, void *buffer, int len);
++extern int dbus_usbos_loopback_tx(void *usbos_info_ptr, int cnt, int size);
++
++/**
++ * These functions are called by the lower DBUS level (dbus_usb_os.c) to notify this DBUS level
++ * (dbus_usb.c) of an event.
++ */
++static dbus_intf_callbacks_t dbus_usb_intf_cbs = {
++	dbus_usb_send_irb_timeout,
++	dbus_usb_send_irb_complete,
++	dbus_usb_recv_irb_complete,
++	dbus_usb_errhandler,
++	dbus_usb_ctl_complete,
++	dbus_usb_state_change,
++	NULL,			/* isr */
++	NULL,			/* dpc */
++	NULL,			/* watchdog */
++	NULL,			/* dbus_if_pktget */
++	NULL, 			/* dbus_if_pktfree */
++	dbus_usb_getirb,
++	dbus_usb_rxerr_indicate
++};
++
++/* IOVar table */
++enum {
++	IOV_SET_DOWNLOAD_STATE = 1,
++	IOV_MEMBYTES,
++	IOV_VARS,
++	IOV_LOOPBACK_TX
++};
++
++const bcm_iovar_t dhdusb_iovars[] = {
++	{"vars",	IOV_VARS,	0,	IOVT_BUFFER,	0 },
++	{"dwnldstate",	IOV_SET_DOWNLOAD_STATE,	0,	IOVT_BOOL,	0 },
++	{"membytes",	IOV_MEMBYTES,	0,	IOVT_BUFFER,	2 * sizeof(int) },
++	{"usb_lb_txfer", IOV_LOOPBACK_TX, 0,    IOVT_BUFFER,    2 * sizeof(int) },
++	{NULL, 0, 0, 0, 0 }
++};
++
++/*
++ * Need global for probe() and disconnect() since
++ * attach() is not called at probe and detach()
++ * can be called inside disconnect()
++ */
++static probe_cb_t	probe_cb = NULL;
++static disconnect_cb_t	disconnect_cb = NULL;
++static void		*probe_arg = NULL;
++static void		*disc_arg = NULL;
++static dbus_intf_t	*g_dbusintf = NULL;
++static dbus_intf_t	dbus_usb_intf; /** functions called by higher layer DBUS into lower layer */
++
++/*
++ * dbus_intf_t common to all USB
++ * These functions override dbus_usb_<os>.c.
++ */
++static void *dbus_usb_attach(dbus_pub_t *pub, void *cbarg, dbus_intf_callbacks_t *cbs);
++static void dbus_usb_detach(dbus_pub_t *pub, void *info);
++static void * dbus_usb_probe(void *arg, const char *desc, uint32 bustype, uint32 hdrlen);
++
++/* functions */
++
++/**
++ * As part of DBUS initialization/registration, the higher level DBUS (dbus.c) needs to know what
++ * lower level DBUS functions to call (in both dbus_usb.c and dbus_usb_os.c).
++ */
++static void *
++dbus_usb_probe(void *arg, const char *desc, uint32 bustype, uint32 hdrlen)
++{
++	DBUSTRACE(("%s(): \n", __FUNCTION__));
++	if (probe_cb) {
++
++		if (g_dbusintf != NULL) {
++			/* First, initialize all lower-level functions as default
++			 * so that dbus.c simply calls directly to dbus_usb_os.c.
++			 */
++			bcopy(g_dbusintf, &dbus_usb_intf, sizeof(dbus_intf_t));
++
++			/* Second, selectively override functions we need, if any. */
++			dbus_usb_intf.attach = dbus_usb_attach;
++			dbus_usb_intf.detach = dbus_usb_detach;
++			dbus_usb_intf.iovar_op = dbus_usb_iovar_op;
++			dbus_usb_intf.dlstart = dbus_usb_dlstart;
++			dbus_usb_intf.dlneeded = dbus_usb_dlneeded;
++			dbus_usb_intf.dlrun = dbus_usb_dlrun;
++#ifdef BCM_DNGL_EMBEDIMAGE
++			dbus_usb_intf.device_exists = dbus_usb_device_exists;
++#endif
++		}
++
++		disc_arg = probe_cb(probe_arg, "DBUS USB", USB_BUS, hdrlen);
++		return disc_arg;
++	}
++
++	return NULL;
++}
++
++/**
++ * On return, *intf contains this or lower-level DBUS functions to be called by higher
++ * level (dbus.c)
++ */
++int
++dbus_bus_register(int vid, int pid, probe_cb_t prcb,
++	disconnect_cb_t discb, void *prarg, dbus_intf_t **intf, void *param1, void *param2)
++{
++	int err;
++
++	DBUSTRACE(("%s(): \n", __FUNCTION__));
++	probe_cb = prcb;
++	disconnect_cb = discb;
++	probe_arg = prarg;
++
++	*intf = &dbus_usb_intf;
++
++	err = dbus_bus_osl_register(vid, pid, dbus_usb_probe,
++		dbus_usb_disconnect, NULL, &g_dbusintf, param1, param2);
++
++	ASSERT(g_dbusintf);
++	return err;
++}
++
++int
++dbus_bus_deregister()
++{
++	DBUSTRACE(("%s(): \n", __FUNCTION__));
++	return dbus_bus_osl_deregister();
++}
++
++/** initialization consists of registration followed by 'attach'. */
++void *
++dbus_usb_attach(dbus_pub_t *pub, void *cbarg, dbus_intf_callbacks_t *cbs)
++{
++	usb_info_t *usb_info;
++
++	DBUSTRACE(("%s(): \n", __FUNCTION__));
++
++	if ((g_dbusintf == NULL) || (g_dbusintf->attach == NULL))
++		return NULL;
++
++	/* Sanity check for BUS_INFO() */
++	ASSERT(OFFSETOF(usb_info_t, pub) == 0);
++
++	usb_info = MALLOC(pub->osh, sizeof(usb_info_t));
++	if (usb_info == NULL)
++		return NULL;
++
++	bzero(usb_info, sizeof(usb_info_t));
++
++	usb_info->pub = pub;
++	usb_info->cbarg = cbarg;
++	usb_info->cbs = cbs;
++
++	usb_info->usbosl_info = (dbus_pub_t *)g_dbusintf->attach(pub,
++		usb_info, &dbus_usb_intf_cbs);
++	if (usb_info->usbosl_info == NULL) {
++		MFREE(pub->osh, usb_info, sizeof(usb_info_t));
++		return NULL;
++	}
++
++	/* Save USB OS-specific driver entry points */
++	usb_info->drvintf = g_dbusintf;
++
++	pub->bus = usb_info;
++#if  !defined(BCM_DNGL_EMBEDIMAGE) && !defined(BCM_REQUEST_FW)
++
++	if (!dbus_usb_resetcfg(usb_info)) {
++	usb_info->pub->busstate = DBUS_STATE_DL_DONE;
++	}
++#endif
++	/* Return Lower layer info */
++	return (void *) usb_info->usbosl_info;
++}
++
++void
++dbus_usb_detach(dbus_pub_t *pub, void *info)
++{
++	usb_info_t *usb_info = (usb_info_t *) pub->bus;
++	osl_t *osh = pub->osh;
++
++	if (usb_info == NULL)
++		return;
++
++	if (usb_info->drvintf && usb_info->drvintf->detach)
++		usb_info->drvintf->detach(pub, usb_info->usbosl_info);
++
++	MFREE(osh, usb_info, sizeof(usb_info_t));
++}
++
++void
++dbus_usb_disconnect(void *handle)
++{
++	DBUSTRACE(("%s(): \n", __FUNCTION__));
++	if (disconnect_cb)
++		disconnect_cb(disc_arg);
++}
++
++/**
++ * When the lower DBUS level (dbus_usb_os.c) signals this event, the higher DBUS level has to be
++ * notified.
++ */
++static void
++dbus_usb_send_irb_timeout(void *handle, dbus_irb_tx_t *txirb)
++{
++	usb_info_t *usb_info = (usb_info_t *) handle;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (usb_info == NULL)
++		return;
++
++	if (usb_info->cbs && usb_info->cbs->send_irb_timeout)
++		usb_info->cbs->send_irb_timeout(usb_info->cbarg, txirb);
++}
++
++/**
++ * When the lower DBUS level (dbus_usb_os.c) signals this event, the higher DBUS level has to be
++ * notified.
++ */
++static void
++dbus_usb_send_irb_complete(void *handle, dbus_irb_tx_t *txirb, int status)
++{
++	usb_info_t *usb_info = (usb_info_t *) handle;
++
++	if (usb_info == NULL)
++		return;
++
++	if (usb_info->cbs && usb_info->cbs->send_irb_complete)
++		usb_info->cbs->send_irb_complete(usb_info->cbarg, txirb, status);
++}
++
++/**
++ * When the lower DBUS level (dbus_usb_os.c) signals this event, the higher DBUS level has to be
++ * notified.
++ */
++static void
++dbus_usb_recv_irb_complete(void *handle, dbus_irb_rx_t *rxirb, int status)
++{
++	usb_info_t *usb_info = (usb_info_t *) handle;
++
++	if (usb_info == NULL)
++		return;
++
++	if (usb_info->cbs && usb_info->cbs->recv_irb_complete)
++		usb_info->cbs->recv_irb_complete(usb_info->cbarg, rxirb, status);
++}
++
++/** Lower DBUS level (dbus_usb_os.c) requests a free IRB. Pass this on to the higher DBUS level. */
++static struct dbus_irb*
++dbus_usb_getirb(void *handle, bool send)
++{
++	usb_info_t *usb_info = (usb_info_t *) handle;
++
++	if (usb_info == NULL)
++		return NULL;
++
++	if (usb_info->cbs && usb_info->cbs->getirb)
++		return usb_info->cbs->getirb(usb_info->cbarg, send);
++
++	return NULL;
++}
++
++/**
++ * When the lower DBUS level (dbus_usb_os.c) signals this event, the higher DBUS level has to be
++ * notified.
++ */
++static void
++dbus_usb_rxerr_indicate(void *handle, bool on)
++{
++	usb_info_t *usb_info = (usb_info_t *) handle;
++
++	if (usb_info == NULL)
++		return;
++
++	if (usb_info->cbs && usb_info->cbs->rxerr_indicate)
++		usb_info->cbs->rxerr_indicate(usb_info->cbarg, on);
++}
++
++/**
++ * When the lower DBUS level (dbus_usb_os.c) signals this event, the higher DBUS level has to be
++ * notified.
++ */
++static void
++dbus_usb_errhandler(void *handle, int err)
++{
++	usb_info_t *usb_info = (usb_info_t *) handle;
++
++	if (usb_info == NULL)
++		return;
++
++	if (usb_info->cbs && usb_info->cbs->errhandler)
++		usb_info->cbs->errhandler(usb_info->cbarg, err);
++}
++
++/**
++ * When the lower DBUS level (dbus_usb_os.c) signals this event, the higher DBUS level has to be
++ * notified.
++ */
++static void
++dbus_usb_ctl_complete(void *handle, int type, int status)
++{
++	usb_info_t *usb_info = (usb_info_t *) handle;
++
++	if (usb_info == NULL)
++		return;
++
++	if (usb_info->cbs && usb_info->cbs->ctl_complete)
++		usb_info->cbs->ctl_complete(usb_info->cbarg, type, status);
++}
++
++/**
++ * When the lower DBUS level (dbus_usb_os.c) signals this event, the higher DBUS level has to be
++ * notified.
++ */
++static void
++dbus_usb_state_change(void *handle, int state)
++{
++	usb_info_t *usb_info = (usb_info_t *) handle;
++
++	if (usb_info == NULL)
++		return;
++
++	if (usb_info->cbs && usb_info->cbs->state_change)
++		usb_info->cbs->state_change(usb_info->cbarg, state);
++}
++
++/** called by higher DBUS level (dbus.c) */
++static int
++dbus_usb_iovar_op(void *bus, const char *name,
++	void *params, int plen, void *arg, int len, bool set)
++{
++	int err = DBUS_OK;
++
++	err = dbus_iovar_process((usb_info_t*)bus, name, params, plen, arg, len, set);
++	return err;
++}
++
++/** process iovar request from higher DBUS level */
++static int
++dbus_iovar_process(usb_info_t* usbinfo, const char *name,
++                 void *params, int plen, void *arg, int len, bool set)
++{
++	const bcm_iovar_t *vi = NULL;
++	int bcmerror = 0;
++	int val_size;
++	uint32 actionid;
++
++	DBUSTRACE(("%s: Enter\n", __FUNCTION__));
++
++	ASSERT(name);
++	ASSERT(len >= 0);
++
++	/* Get MUST have return space */
++	ASSERT(set || (arg && len));
++
++	/* Set does NOT take qualifiers */
++	ASSERT(!set || (!params && !plen));
++
++	/* Look up var locally; if not found pass to host driver */
++	if ((vi = bcm_iovar_lookup(dhdusb_iovars, name)) == NULL) {
++		/* Not Supported */
++		bcmerror = BCME_UNSUPPORTED;
++		DBUSTRACE(("%s: IOVAR %s is not supported\n", name, __FUNCTION__));
++		goto exit;
++
++	}
++
++	DBUSTRACE(("%s: %s %s, len %d plen %d\n", __FUNCTION__,
++	         name, (set ? "set" : "get"), len, plen));
++
++	/* set up 'params' pointer in case this is a set command so that
++	 * the convenience int and bool code can be common to set and get
++	 */
++	if (params == NULL) {
++		params = arg;
++		plen = len;
++	}
++
++	if (vi->type == IOVT_VOID)
++		val_size = 0;
++	else if (vi->type == IOVT_BUFFER)
++		val_size = len;
++	else
++		/* all other types are integer sized */
++		val_size = sizeof(int);
++
++	actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
++	bcmerror = dbus_usb_doiovar(usbinfo, vi, actionid,
++		name, params, plen, arg, len, val_size);
++
++exit:
++	return bcmerror;
++} /* dbus_iovar_process */
++
++static int
++dbus_usb_doiovar(usb_info_t *bus, const bcm_iovar_t *vi, uint32 actionid, const char *name,
++                void *params, int plen, void *arg, int len, int val_size)
++{
++	int bcmerror = 0;
++	int32 int_val = 0;
++	int32 int_val2 = 0;
++	bool bool_val = 0;
++
++	DBUSTRACE(("%s: Enter, action %d name %s params %p plen %d arg %p len %d val_size %d\n",
++	           __FUNCTION__, actionid, name, params, plen, arg, len, val_size));
++
++	if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid))) != 0)
++		goto exit;
++
++	if (plen >= (int)sizeof(int_val))
++		bcopy(params, &int_val, sizeof(int_val));
++
++	if (plen >= (int)sizeof(int_val) * 2)
++		bcopy((void*)((uintptr)params + sizeof(int_val)), &int_val2, sizeof(int_val2));
++
++	bool_val = (int_val != 0) ? TRUE : FALSE;
++
++	switch (actionid) {
++
++	case IOV_SVAL(IOV_MEMBYTES):
++	case IOV_GVAL(IOV_MEMBYTES):
++	{
++		uint32 address;
++		uint size, dsize;
++		uint8 *data;
++
++		bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
++
++		ASSERT(plen >= 2*sizeof(int));
++
++		address = (uint32)int_val;
++		BCM_REFERENCE(address);
++		bcopy((char *)params + sizeof(int_val), &int_val, sizeof(int_val));
++		size = (uint)int_val;
++
++		/* Do some validation */
++		dsize = set ? plen - (2 * sizeof(int)) : len;
++		if (dsize < size) {
++			DBUSTRACE(("%s: error on %s membytes, addr 0x%08x size %d dsize %d\n",
++			           __FUNCTION__, (set ? "set" : "get"), address, size, dsize));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		DBUSTRACE(("%s: Request to %s %d bytes at address 0x%08x\n", __FUNCTION__,
++		          (set ? "write" : "read"), size, address));
++
++		/* Generate the actual data pointer */
++		data = set ? (uint8*)params + 2 * sizeof(int): (uint8*)arg;
++
++		/* Call to do the transfer */
++		bcmerror = dbus_usb_dl_writeimage(BUS_INFO(bus, usb_info_t), data, size);
++	}
++		break;
++
++
++	case IOV_SVAL(IOV_SET_DOWNLOAD_STATE):
++
++		if (bool_val == TRUE) {
++			bcmerror = dbus_usb_dlneeded(bus);
++			dbus_usb_rdl_dwnld_state(BUS_INFO(bus, usb_info_t));
++		} else {
++			usb_info_t *usbinfo = BUS_INFO(bus, usb_info_t);
++			bcmerror = dbus_usb_dlrun(bus);
++			usbinfo->pub->busstate = DBUS_STATE_DL_DONE;
++		}
++		break;
++
++	case IOV_SVAL(IOV_VARS):
++		bcmerror = dhdusb_downloadvars(BUS_INFO(bus, usb_info_t), arg, len);
++		break;
++#ifdef DBUS_USB_LOOPBACK
++	case IOV_SVAL(IOV_LOOPBACK_TX):
++			bcmerror = dbus_usbos_loopback_tx(BUS_INFO(bus, usb_info_t), int_val,
++			  int_val2);
++			break;
++#endif
++	default:
++		bcmerror = BCME_UNSUPPORTED;
++		break;
++	}
++
++exit:
++	return bcmerror;
++} /* dbus_usb_doiovar */
++
++/** higher DBUS level (dbus.c) wants to set NVRAM variables in dongle */
++static int
++dhdusb_downloadvars(usb_info_t *bus, void *arg, int len)
++{
++	int bcmerror = 0;
++	uint32 varsize;
++	uint32 varaddr;
++	uint32 varsizew;
++
++	if (!len) {
++		bcmerror = BCME_BUFTOOSHORT;
++		goto err;
++	}
++
++	/* RAM size is not set. Set it at dbus_usb_dlneeded */
++	if (!bus->rdlram_size)
++		bcmerror = BCME_ERROR;
++
++	/* Even if there are no vars are to be written, we still need to set the ramsize. */
++	varsize = len ? ROUNDUP(len, 4) : 0;
++	varaddr = (bus->rdlram_size - 4) - varsize;
++
++	/* Write the vars list */
++	DBUSTRACE(("WriteVars: @%x varsize=%d\n", varaddr, varsize));
++	bcmerror = dbus_write_membytes(bus->usbosl_info, TRUE, (varaddr + bus->rdlram_base_addr),
++		arg, varsize);
++
++	/* adjust to the user specified RAM */
++	DBUSTRACE(("Usable memory size: %d\n", bus->rdlram_size));
++	DBUSTRACE(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
++
++	varsize = ((bus->rdlram_size - 4) - varaddr);
++
++	/*
++	 * Determine the length token:
++	 * Varsize, converted to words, in lower 16-bits, checksum in upper 16-bits.
++	 */
++	if (bcmerror) {
++		varsizew = 0;
++	} else {
++		varsizew = varsize / 4;
++		varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
++		varsizew = htol32(varsizew);
++	}
++
++	DBUSTRACE(("New varsize is %d, length token=0x%08x\n", varsize, varsizew));
++
++	/* Write the length token to the last word */
++	bcmerror = dbus_write_membytes(bus->usbosl_info, TRUE, ((bus->rdlram_size - 4) +
++		bus->rdlram_base_addr), (uint8*)&varsizew, 4);
++err:
++	return bcmerror;
++} /* dbus_usb_doiovar */
++
++/**
++ * After downloading firmware into dongle and starting it, we need to know if the firmware is
++ * indeed up and running.
++ */
++static int
++dbus_usb_resetcfg(usb_info_t *usbinfo)
++{
++	void *osinfo;
++	bootrom_id_t id;
++	uint16 waittime = 0;
++
++	uint32 starttime = 0;
++	uint32 endtime = 0;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (usbinfo == NULL)
++		return DBUS_ERR;
++
++	osinfo = usbinfo->usbosl_info;
++	ASSERT(osinfo);
++
++	/* Give dongle chance to boot */
++	dbus_usbos_wait(osinfo, USB_SFLASH_DLIMAGE_SPINWAIT);
++	waittime = USB_SFLASH_DLIMAGE_SPINWAIT;
++	while (waittime < USB_DLIMAGE_RETRY_TIMEOUT) {
++
++		starttime = OSL_SYSUPTIME();
++
++		id.chip = 0xDEAD;       /* Get the ID */
++		dbus_usbos_dl_cmd(osinfo, DL_GETVER, &id, sizeof(bootrom_id_t));
++		id.chip = ltoh32(id.chip);
++
++		endtime = OSL_SYSUPTIME();
++		waittime += (endtime - starttime);
++
++		if (id.chip == POSTBOOT_ID)
++			break;
++	}
++
++	if (id.chip == POSTBOOT_ID) {
++		DBUSERR(("%s: download done. Bootup time = %d ms postboot chip 0x%x/rev 0x%x\n",
++			__FUNCTION__, waittime, id.chip, id.chiprev));
++
++		dbus_usbos_dl_cmd(osinfo, DL_RESETCFG, &id, sizeof(bootrom_id_t));
++
++		dbus_usbos_wait(osinfo, USB_RESETCFG_SPINWAIT);
++		return DBUS_OK;
++	} else {
++		DBUSERR(("%s: Cannot talk to Dongle. Wait time = %d ms. Firmware is not UP \n",
++			__FUNCTION__, waittime));
++		return DBUS_ERR;
++	}
++
++	return DBUS_OK;
++}
++
++/** before firmware download, the dongle has to be prepared to receive the fw image */
++static int
++dbus_usb_rdl_dwnld_state(usb_info_t *usbinfo)
++{
++	void *osinfo = usbinfo->usbosl_info;
++	rdl_state_t state;
++	int err = DBUS_OK;
++
++	/* 1) Prepare USB boot loader for runtime image */
++	dbus_usbos_dl_cmd(osinfo, DL_START, &state, sizeof(rdl_state_t));
++
++	state.state = ltoh32(state.state);
++	state.bytes = ltoh32(state.bytes);
++
++	/* 2) Check we are in the Waiting state */
++	if (state.state != DL_WAITING) {
++		DBUSERR(("%s: Failed to DL_START\n", __FUNCTION__));
++		err = DBUS_ERR;
++		goto fail;
++	}
++
++fail:
++	return err;
++}
++
++/**
++ * Dongle contains bootcode in ROM but firmware is (partially) contained in dongle RAM. Therefore,
++ * firmware has to be downloaded into dongle RAM.
++ */
++static int
++dbus_usb_dl_writeimage(usb_info_t *usbinfo, uint8 *fw, int fwlen)
++{
++	osl_t *osh = usbinfo->pub->osh;
++	void *osinfo = usbinfo->usbosl_info;
++	unsigned int sendlen, sent, dllen;
++	char *bulkchunk = NULL, *dlpos;
++	rdl_state_t state;
++	int err = DBUS_OK;
++	bootrom_id_t id;
++	uint16 wait, wait_time;
++	uint32 dl_trunk_size = RDL_CHUNK;
++
++	if (BCM4350_CHIP(usbinfo->pub->attrib.devid))
++		dl_trunk_size = RDL_CHUNK_MAX;
++
++	while (!bulkchunk) {
++		bulkchunk = MALLOC(osh, dl_trunk_size);
++		if (dl_trunk_size == RDL_CHUNK)
++			break;
++		if (!bulkchunk) {
++			dl_trunk_size /= 2;
++			if (dl_trunk_size < RDL_CHUNK)
++				dl_trunk_size = RDL_CHUNK;
++		}
++	}
++
++	if (bulkchunk == NULL) {
++		err = DBUS_ERR;
++		goto fail;
++	}
++
++	sent = 0;
++	dlpos = fw;
++	dllen = fwlen;
++
++	/* Get chip id and rev */
++	id.chip = usbinfo->pub->attrib.devid;
++	id.chiprev = usbinfo->pub->attrib.chiprev;
++
++	DBUSTRACE(("enter %s: fwlen=%d\n", __FUNCTION__, fwlen));
++
++	dbus_usbos_dl_cmd(osinfo, DL_GETSTATE, &state, sizeof(rdl_state_t));
++
++	/* 3) Load the image */
++	while ((sent < dllen)) {
++		/* Wait until the usb device reports it received all the bytes we sent */
++
++		if (sent < dllen) {
++			if ((dllen-sent) < dl_trunk_size)
++				sendlen = dllen-sent;
++			else
++				sendlen = dl_trunk_size;
++
++			/* simply avoid having to send a ZLP by ensuring we never have an even
++			 * multiple of 64
++			 */
++			if (!(sendlen % 64))
++				sendlen -= 4;
++
++			/* send data */
++			memcpy(bulkchunk, dlpos, sendlen);
++			if (!dbus_usbos_dl_send_bulk(osinfo, bulkchunk, sendlen)) {
++				err = DBUS_ERR;
++				goto fail;
++			}
++
++			dlpos += sendlen;
++			sent += sendlen;
++			DBUSTRACE(("%s: sendlen %d\n", __FUNCTION__, sendlen));
++		}
++
++		wait = 0;
++		wait_time = USB_SFLASH_DLIMAGE_SPINWAIT;
++		while (!dbus_usbos_dl_cmd(osinfo, DL_GETSTATE, &state,
++			sizeof(rdl_state_t))) {
++			if ((id.chip == 43236) && (id.chiprev == 0)) {
++				DBUSERR(("%s: 43236a0 SFlash delay, waiting for dongle crc check "
++					 "completion!!!\n", __FUNCTION__));
++				dbus_usbos_wait(osinfo, wait_time);
++				wait += wait_time;
++				if (wait >= USB_SFLASH_DLIMAGE_LIMIT) {
++					DBUSERR(("%s: DL_GETSTATE Failed xxxx\n", __FUNCTION__));
++					err = DBUS_ERR;
++					goto fail;
++					break;
++				}
++			} else {
++				DBUSERR(("%s: DL_GETSTATE Failed xxxx\n", __FUNCTION__));
++				err = DBUS_ERR;
++				goto fail;
++			}
++		}
++
++		state.state = ltoh32(state.state);
++		state.bytes = ltoh32(state.bytes);
++
++		/* restart if an error is reported */
++		if ((state.state == DL_BAD_HDR) || (state.state == DL_BAD_CRC)) {
++			DBUSERR(("%s: Bad Hdr or Bad CRC\n", __FUNCTION__));
++			err = DBUS_ERR;
++			goto fail;
++		}
++
++	}
++fail:
++	if (bulkchunk)
++		MFREE(osh, bulkchunk, dl_trunk_size);
++
++	return err;
++} /* dbus_usb_dl_writeimage */
++
++/** Higher level DBUS layer (dbus.c) requests this layer to download image into dongle */
++static int
++dbus_usb_dlstart(void *bus, uint8 *fw, int len)
++{
++	usb_info_t *usbinfo = BUS_INFO(bus, usb_info_t);
++	int err;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (usbinfo == NULL)
++		return DBUS_ERR;
++
++	if (USB_DEV_ISBAD(usbinfo))
++		return DBUS_ERR;
++
++	err = dbus_usb_rdl_dwnld_state(usbinfo);
++
++	if (DBUS_OK == err) {
++	err = dbus_usb_dl_writeimage(usbinfo, fw, len);
++	if (err == DBUS_OK)
++		usbinfo->pub->busstate = DBUS_STATE_DL_DONE;
++	else
++		usbinfo->pub->busstate = DBUS_STATE_DL_PENDING;
++	} else
++		usbinfo->pub->busstate = DBUS_STATE_DL_PENDING;
++
++	return err;
++}
++
++static bool
++dbus_usb_update_chipinfo(usb_info_t *usbinfo, uint32 chip)
++{
++	bool retval = TRUE;
++	/* based on the CHIP Id, store the ram size which is needed for NVRAM download. */
++	switch (chip) {
++
++		case 0x4319:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_4319;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_4319;
++			break;
++
++		case 0x4329:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_4329;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_4329;
++			break;
++
++		case 43234:
++		case 43235:
++		case 43236:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_43236;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_43236;
++			break;
++
++		case 0x4328:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_4328;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_4328;
++			break;
++
++		case 0x4322:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_4322;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_4322;
++			break;
++
++		case 0x4360:
++		case 0xAA06:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_4360;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_4360;
++			break;
++
++		case 43242:
++		case 43243:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_43242;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_43242;
++			break;
++
++		case 43143:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_43143;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_43143;
++			break;
++
++		case 0x4350:
++		case 43556:
++		case 43558:
++		case 43569:
++			usbinfo->rdlram_size = RDL_RAM_SIZE_4350;
++			usbinfo->rdlram_base_addr = RDL_RAM_BASE_4350;
++			break;
++
++		case POSTBOOT_ID:
++			break;
++
++		default:
++			DBUSERR(("%s: Chip 0x%x Ram size is not known\n", __FUNCTION__, chip));
++			retval = FALSE;
++			break;
++
++	}
++
++	return retval;
++} /* dbus_usb_update_chipinfo */
++
++/** higher DBUS level (dbus.c) wants to know if firmware download is required. */
++static bool
++dbus_usb_dlneeded(void *bus)
++{
++	usb_info_t *usbinfo = BUS_INFO(bus, usb_info_t);
++	void *osinfo;
++	bootrom_id_t id;
++	bool dl_needed = TRUE;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (usbinfo == NULL)
++		return FALSE;
++
++	osinfo = usbinfo->usbosl_info;
++	ASSERT(osinfo);
++
++	/* Check if firmware downloaded already by querying runtime ID */
++	id.chip = 0xDEAD;
++	dbus_usbos_dl_cmd(osinfo, DL_GETVER, &id, sizeof(bootrom_id_t));
++
++	id.chip = ltoh32(id.chip);
++	id.chiprev = ltoh32(id.chiprev);
++
++	if (FALSE == dbus_usb_update_chipinfo(usbinfo, id.chip)) {
++		dl_needed = FALSE;
++		goto exit;
++	}
++
++	DBUSERR(("%s: chip 0x%x rev 0x%x\n", __FUNCTION__, id.chip, id.chiprev));
++	if (id.chip == POSTBOOT_ID) {
++		/* This code is  needed to support two enumerations on USB1.1 scenario */
++		DBUSERR(("%s: Firmware already downloaded\n", __FUNCTION__));
++
++		dbus_usbos_dl_cmd(osinfo, DL_RESETCFG, &id, sizeof(bootrom_id_t));
++		dl_needed = FALSE;
++		if (usbinfo->pub->busstate == DBUS_STATE_DL_PENDING)
++			usbinfo->pub->busstate = DBUS_STATE_DL_DONE;
++	} else {
++		usbinfo->pub->attrib.devid = id.chip;
++		usbinfo->pub->attrib.chiprev = id.chiprev;
++	}
++
++exit:
++	return dl_needed;
++}
++
++/** After issuing firmware download, higher DBUS level (dbus.c) wants to start the firmware. */
++static int
++dbus_usb_dlrun(void *bus)
++{
++	usb_info_t *usbinfo = BUS_INFO(bus, usb_info_t);
++	void *osinfo;
++	rdl_state_t state;
++	int err = DBUS_OK;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (usbinfo == NULL)
++		return DBUS_ERR;
++
++	if (USB_DEV_ISBAD(usbinfo))
++		return DBUS_ERR;
++
++	osinfo = usbinfo->usbosl_info;
++	ASSERT(osinfo);
++
++	/* Check we are runnable */
++	dbus_usbos_dl_cmd(osinfo, DL_GETSTATE, &state, sizeof(rdl_state_t));
++
++	state.state = ltoh32(state.state);
++	state.bytes = ltoh32(state.bytes);
++
++	/* Start the image */
++	if (state.state == DL_RUNNABLE) {
++		DBUSTRACE(("%s: Issue DL_GO\n", __FUNCTION__));
++		dbus_usbos_dl_cmd(osinfo, DL_GO, &state, sizeof(rdl_state_t));
++
++		if (usbinfo->pub->attrib.devid == TEST_CHIP)
++			dbus_usbos_wait(osinfo, USB_DLGO_SPINWAIT);
++
++		dbus_usb_resetcfg(usbinfo);
++		/* The Donlge may go for re-enumeration. */
++	} else {
++		DBUSERR(("%s: Dongle not runnable\n", __FUNCTION__));
++		err = DBUS_ERR;
++	}
++
++	return err;
++}
++
++/**
++ * As preparation for firmware download, higher DBUS level (dbus.c) requests the firmware image
++ * to be used for the type of dongle detected. Directly called by dbus.c (so not via a callback
++ * construction)
++ */
++void
++dbus_bus_fw_get(void *bus, uint8 **fw, int *fwlen, int *decomp)
++{
++	usb_info_t *usbinfo = BUS_INFO(bus, usb_info_t);
++	unsigned int devid;
++	unsigned int crev;
++
++	devid = usbinfo->pub->attrib.devid;
++	crev = usbinfo->pub->attrib.chiprev;
++
++	*fw = NULL;
++	*fwlen = 0;
++
++	switch (devid) {
++	case BCM43236_CHIP_ID:
++	case BCM43235_CHIP_ID:
++	case BCM43234_CHIP_ID:
++	case BCM43238_CHIP_ID: {
++		if (crev == 3 || crev == 2 || crev == 1) {
++#ifdef EMBED_IMAGE_43236b
++			*fw = (uint8 *)dlarray_43236b;
++			*fwlen = sizeof(dlarray_43236b);
++
++#endif
++		}
++		} break;
++	case BCM4360_CHIP_ID:
++	case BCM4352_CHIP_ID:
++	case BCM43526_CHIP_ID:
++#ifdef EMBED_IMAGE_43526a
++		if (crev <= 2) {
++			*fw = (uint8 *)dlarray_43526a;
++			*fwlen = sizeof(dlarray_43526a);
++		}
++#endif
++#ifdef EMBED_IMAGE_43526b
++		if (crev > 2) {
++			*fw = (uint8 *)dlarray_43526b;
++			*fwlen = sizeof(dlarray_43526b);
++		}
++#endif
++		break;
++
++	case BCM43242_CHIP_ID:
++#ifdef EMBED_IMAGE_43242a0
++		*fw = (uint8 *)dlarray_43242a0;
++		*fwlen = sizeof(dlarray_43242a0);
++#endif
++		break;
++
++	case BCM43143_CHIP_ID:
++#ifdef EMBED_IMAGE_43143a0
++		*fw = (uint8 *)dlarray_43143a0;
++		*fwlen = sizeof(dlarray_43143a0);
++#endif
++#ifdef EMBED_IMAGE_43143b0
++		*fw = (uint8 *)dlarray_43143b0;
++		*fwlen = sizeof(dlarray_43143b0);
++#endif
++		break;
++
++	case BCM4350_CHIP_ID:
++	case BCM4354_CHIP_ID:
++	case BCM43556_CHIP_ID:
++	case BCM43558_CHIP_ID:
++	case BCM43566_CHIP_ID:
++	case BCM43568_CHIP_ID:
++	case BCM43570_CHIP_ID:
++	case BCM4358_CHIP_ID:
++#ifdef EMBED_IMAGE_4350a0
++		if (crev == 0) {
++			*fw = (uint8 *)dlarray_4350a0;
++			*fwlen = sizeof(dlarray_4350a0);
++		}
++#endif
++#ifdef EMBED_IMAGE_4350b0
++		if (crev == 1) {
++			*fw = (uint8 *)dlarray_4350b0;
++			*fwlen = sizeof(dlarray_4350b0);
++		}
++#endif
++#ifdef EMBED_IMAGE_4350b1
++		if (crev == 2) {
++			*fw = (uint8 *)dlarray_4350b1;
++			*fwlen = sizeof(dlarray_4350b1);
++		}
++#endif
++#ifdef EMBED_IMAGE_43556b1
++		if (crev == 2) {
++			*fw = (uint8 *)dlarray_43556b1;
++			*fwlen = sizeof(dlarray_43556b1);
++		}
++#endif
++#ifdef EMBED_IMAGE_4350c0
++		if (crev == 3) {
++			*fw = (uint8 *)dlarray_4350c0;
++			*fwlen = sizeof(dlarray_4350c0);
++		}
++#endif /* EMBED_IMAGE_4350c0 */
++#ifdef EMBED_IMAGE_4350c1
++		if (crev == 4) {
++			*fw = (uint8 *)dlarray_4350c1;
++			*fwlen = sizeof(dlarray_4350c1);
++		}
++#endif /* EMBED_IMAGE_4350c1 */
++		break;
++	case BCM43569_CHIP_ID:
++#ifdef EMBED_IMAGE_43569a0
++		if (crev == 0) {
++			*fw = (uint8 *)dlarray_43569a0;
++			*fwlen = sizeof(dlarray_43569a0);
++		}
++#endif /* EMBED_IMAGE_43569a0 */
++		break;
++	default:
++#ifdef EMBED_IMAGE_GENERIC
++		*fw = (uint8 *)dlarray;
++		*fwlen = sizeof(dlarray);
++#endif
++		break;
++	}
++} /* dbus_bus_fw_get */
++
++#ifdef BCM_DNGL_EMBEDIMAGE
++static bool
++dbus_usb_device_exists(void *bus)
++{
++	usb_info_t *usbinfo = BUS_INFO(bus, usb_info_t);
++	void *osinfo;
++	bootrom_id_t id;
++
++	DBUSTRACE(("%s\n", __FUNCTION__));
++
++	if (usbinfo == NULL)
++		return FALSE;
++
++	osinfo = usbinfo->usbosl_info;
++	ASSERT(osinfo);
++
++	id.chip = 0xDEAD;
++	/* Query device to see if we get a response */
++	dbus_usbos_dl_cmd(osinfo, DL_GETVER, &id, sizeof(bootrom_id_t));
++
++	usbinfo->pub->attrib.devid = id.chip;
++	if (id.chip == 0xDEAD)
++		return FALSE;
++	else
++		return TRUE;
++}
++#endif /* BCM_DNGL_EMBEDIMAGE */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dbus_usb_linux.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dbus_usb_linux.c
+new file mode 100644
+index 000000000..469045e54
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dbus_usb_linux.c
+@@ -0,0 +1,4600 @@
++/*
++ * Dongle BUS interface
++ * USB Linux Implementation
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dbus_usb_linux.c 708808 2018-11-27 03:12:35Z $
++ */
++
++/**
++ * @file @brief
++ * This file contains DBUS code that is USB *and* OS (Linux) specific. DBUS is a Broadcom
++ * proprietary host specific abstraction layer.
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++
++/**
++ * DBUS_LINUX_RXDPC is created for router platform performance tuning. A separate thread is created
++ * to handle USB RX and avoid the call chain getting too long and enhance cache hit rate.
++ *
++ * DBUS_LINUX_RXDPC setting is in wlconfig file.
++ */
++
++/*
++ * If DBUS_LINUX_RXDPC is off, spin_lock_bh() for CTFPOOL in
++ * linux_osl.c has to be changed to spin_lock_irqsave() because
++ * PKTGET/PKTFREE are no longer in bottom half.
++ *
++ * Right now we have another queue rpcq in wl_linux.c. Maybe we
++ * can eliminate that one to reduce the overhead.
++ *
++ * Enabling 2nd EP and DBUS_LINUX_RXDPC causing traffic from
++ * both EP's to be queued in the same rx queue. If we want
++ * RXDPC to work with 2nd EP. The EP for RPC call return
++ * should bypass the dpc and go directly up.
++ */
++
++/* #define DBUS_LINUX_RXDPC */
++
++/* Dbus histogram for ntxq, nrxq, dpc parameter tuning */
++/* #define DBUS_LINUX_HIST */
++
++#include <usbrdl.h>
++#include <bcmendian.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/usb.h>
++#include <linux/skbuff.h>
++#include <linux/netdevice.h>
++#include <linux/random.h>
++#include <linux/spinlock.h>
++#include <linux/list.h>
++#include <asm/uaccess.h>
++#include <asm/unaligned.h>
++#include <dbus.h>
++#include <bcmutils.h>
++#include <bcmdevs.h>
++#include <linux/usb.h>
++#include <usbrdl.h>
++#include <linux/firmware.h>
++#ifdef DBUS_LINUX_RXDPC
++#include <linux/sched.h>
++#endif
++
++#if defined(USBOS_THREAD) || defined(USBOS_TX_THREAD)
++
++/**
++ * The usb-thread is designed to provide currency on multiprocessors and SMP linux kernels. On the
++ * dual cores platform, the WLAN driver, without threads, executed only on CPU0. The driver consumed
++ * almost of 100% on CPU0, while CPU1 remained idle. The behavior was observed on Broadcom's STB.
++ *
++ * The WLAN driver consumed most of CPU0 and not CPU1 because tasklets/queues, software irq, and
++ * hardware irq are executing from CPU0, only. CPU0 became the system's bottle-neck. TPUT is lower
++ * and system's responsiveness is slower.
++ *
++ * To improve system responsiveness and TPUT usb-thread was implemented. The system's threads could
++ * be scheduled to run on any core. One core could be processing data in the usb-layer and the other
++ * core could be processing data in the wl-layer.
++ *
++ * For further info see [WlThreadAndUsbThread] Twiki.
++ */
++
++#include <linux/kthread.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <asm/hardirq.h>
++#include <linux/list.h>
++#include <linux_osl.h>
++#endif /* USBOS_THREAD || USBOS_TX_THREAD */
++
++
++#ifdef DBUS_LINUX_RXDPC
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++#define RESCHED()   _cond_resched()
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++#define RESCHED()   cond_resched()
++#else
++#define RESCHED()   __cond_resched()
++#endif /* LINUX_VERSION_CODE  */
++#endif	/* DBUS_LINUX_RXDPC */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++#define KERNEL26
++#endif
++
++/**
++ * Starting with the 3.10 kernel release, dynamic PM support for USB is present whenever
++ * the kernel was built with CONFIG_PM_RUNTIME enabled. The CONFIG_USB_SUSPEND option has
++ * been eliminated.
++ */
++#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21)) && defined(CONFIG_USB_SUSPEND)) \
++	|| ((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) && defined(CONFIG_PM_RUNTIME))
++/* For USB power management support, see Linux kernel: Documentation/usb/power-management.txt */
++#define USB_SUSPEND_AVAILABLE
++#endif
++
++/* Define alternate fw/nvram paths used in Android */
++#define CONFIG_ANDROID_BCMDHD_1_363_125_17_FW_PATH "broadcom/dhd/firmware/fw.bin.trx"
++#define CONFIG_ANDROID_BCMDHD_1_363_125_17_NVRAM_PATH "broadcom/dhd/nvrams/nvm.txt"
++
++static inline int usb_submit_urb_linux(struct urb *urb)
++{
++
++#ifdef BCM_MAX_URB_LEN
++	if (urb && (urb->transfer_buffer_length > BCM_MAX_URB_LEN)) {
++		DBUSERR(("URB transfer length=%d exceeded %d ra=%p\n", urb->transfer_buffer_length,
++		BCM_MAX_URB_LEN, __builtin_return_address(0)));
++		return DBUS_ERR;
++	}
++#endif
++
++#ifdef KERNEL26
++	return usb_submit_urb(urb, GFP_ATOMIC);
++#else
++	return usb_submit_urb(urb);
++#endif
++
++}
++
++#define USB_SUBMIT_URB(urb) usb_submit_urb_linux(urb)
++
++#ifdef KERNEL26
++
++#define USB_ALLOC_URB()				usb_alloc_urb(0, GFP_ATOMIC)
++#define USB_UNLINK_URB(urb)			(usb_kill_urb(urb))
++#define USB_FREE_URB(urb)			(usb_free_urb(urb))
++#define USB_REGISTER()				usb_register(&dbus_usbdev)
++#define USB_DEREGISTER()			usb_deregister(&dbus_usbdev)
++
++#ifdef USB_SUSPEND_AVAILABLE
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33))
++#define USB_AUTOPM_SET_INTERFACE(intf)		usb_autopm_set_interface(intf)
++#else
++#define USB_ENABLE_AUTOSUSPEND(udev)		usb_enable_autosuspend(udev)
++#define USB_DISABLE_AUTOSUSPEND(udev)       usb_disable_autosuspend(udev)
++#endif  /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33))  */
++
++#define USB_AUTOPM_GET_INTERFACE(intf)		usb_autopm_get_interface(intf)
++#define USB_AUTOPM_PUT_INTERFACE(intf)		usb_autopm_put_interface(intf)
++#define USB_AUTOPM_GET_INTERFACE_ASYNC(intf)	usb_autopm_get_interface_async(intf)
++#define USB_AUTOPM_PUT_INTERFACE_ASYNC(intf)	usb_autopm_put_interface_async(intf)
++#define USB_MARK_LAST_BUSY(dev)			usb_mark_last_busy(dev)
++
++#else /* USB_SUSPEND_AVAILABLE */
++
++#define USB_AUTOPM_GET_INTERFACE(intf)		do {} while (0)
++#define USB_AUTOPM_PUT_INTERFACE(intf)		do {} while (0)
++#define USB_AUTOPM_GET_INTERFACE_ASYNC(intf)	do {} while (0)
++#define USB_AUTOPM_PUT_INTERFACE_ASYNC(intf)	do {} while (0)
++#define USB_MARK_LAST_BUSY(dev)			do {} while (0)
++#endif /* USB_SUSPEND_AVAILABLE */
++
++#define USB_CONTROL_MSG(dev, pipe, request, requesttype, value, index, data, size, timeout) \
++	usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), \
++	(data), (size), (timeout))
++#define USB_BULK_MSG(dev, pipe, data, len, actual_length, timeout) \
++	usb_bulk_msg((dev), (pipe), (data), (len), (actual_length), (timeout))
++#define USB_BUFFER_ALLOC(dev, size, mem, dma)	usb_buffer_alloc(dev, size, mem, dma)
++#define USB_BUFFER_FREE(dev, size, data, dma)	usb_buffer_free(dev, size, data, dma)
++
++#ifdef WL_URB_ZPKT
++#define URB_QUEUE_BULK   URB_ZERO_PACKET
++#else
++#define URB_QUEUE_BULK   0
++#endif /* WL_URB_ZPKT */
++
++#define CALLBACK_ARGS		struct urb *urb, struct pt_regs *regs
++#define CALLBACK_ARGS_DATA	urb, regs
++#define CONFIGDESC(usb)		(&((usb)->actconfig)->desc)
++#define IFPTR(usb, idx)		((usb)->actconfig->interface[idx])
++#define IFALTS(usb, idx)	(IFPTR((usb), (idx))->altsetting[0])
++#define IFDESC(usb, idx)	IFALTS((usb), (idx)).desc
++#define IFEPDESC(usb, idx, ep)	(IFALTS((usb), (idx)).endpoint[ep]).desc
++#ifdef DBUS_LINUX_RXDPC
++#define DAEMONIZE(a)		daemonize(a); allow_signal(SIGKILL); allow_signal(SIGTERM);
++#define SET_NICE(n)		set_user_nice(current, n)
++#endif
++
++#else /* KERNEL26 */
++
++#define USB_ALLOC_URB()				usb_alloc_urb(0)
++#define USB_UNLINK_URB(urb)			usb_unlink_urb(urb)
++#define USB_FREE_URB(urb)			(usb_free_urb(urb))
++#define USB_REGISTER()				usb_register(&dbus_usbdev)
++#define USB_DEREGISTER()			usb_deregister(&dbus_usbdev)
++#define USB_AUTOPM_GET_INTERFACE(intf)		do {} while (0)
++#define USB_AUTOPM_GET_INTERFACE_ASYNC(intf)	do {} while (0)
++#define USB_AUTOPM_PUT_INTERFACE_ASYNC(intf)	do {} while (0)
++#define USB_MARK_LAST_BUSY(dev)			do {} while (0)
++
++#define USB_CONTROL_MSG(dev, pipe, request, requesttype, value, index, data, size, timeout) \
++	usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), \
++	(data), (size), (timeout))
++#define USB_BUFFER_ALLOC(dev, size, mem, dma)  kmalloc(size, mem)
++#define USB_BUFFER_FREE(dev, size, data, dma)  kfree(data)
++
++#ifdef WL_URB_ZPKT
++#define URB_QUEUE_BULK   USB_QUEUE_BULK|URB_ZERO_PACKET
++#else
++#define URB_QUEUE_BULK   0
++#endif /*  WL_URB_ZPKT */
++
++#define CALLBACK_ARGS		struct urb *urb
++#define CALLBACK_ARGS_DATA	urb
++#define CONFIGDESC(usb)		((usb)->actconfig)
++#define IFPTR(usb, idx)		(&(usb)->actconfig->interface[idx])
++#define IFALTS(usb, idx)	((usb)->actconfig->interface[idx].altsetting[0])
++#define IFDESC(usb, idx)	IFALTS((usb), (idx))
++#define IFEPDESC(usb, idx, ep)	(IFALTS((usb), (idx)).endpoint[ep])
++
++#ifdef DBUS_LINUX_RXDPC
++#define DAEMONIZE(a)    daemonize();
++#define SET_NICE(n)     do {current->nice = (n);} while (0)
++#endif /* DBUS_LINUX_RXDPC */
++
++#endif /* KERNEL26 */
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31))
++#define USB_SPEED_SUPER		5
++#endif  /* #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31)) */
++
++#define CONTROL_IF   0
++#define BULK_IF      0
++
++#ifdef BCMUSBDEV_COMPOSITE
++#define USB_COMPIF_MAX       4
++
++#define USB_CLASS_WIRELESS	0xe0
++#define USB_CLASS_MISC		0xef
++#define USB_SUBCLASS_COMMON	0x02
++#define USB_PROTO_IAD		0x01
++#define USB_PROTO_VENDOR	0xff
++
++#define USB_QUIRK_NO_SET_INTF   0x04 /* device does not support set_interface */
++#endif /* BCMUSBDEV_COMPOSITE */
++
++#define USB_SYNC_WAIT_TIMEOUT  300  /* ms */
++
++/* Private data kept in skb */
++#define SKB_PRIV(skb, idx)  (&((void **)skb->cb)[idx])
++#define SKB_PRIV_URB(skb)   (*(struct urb **)SKB_PRIV(skb, 0))
++
++#ifndef DBUS_USB_RXQUEUE_BATCH_ADD
++/* items to add each time within limit */
++#define DBUS_USB_RXQUEUE_BATCH_ADD            8
++#endif
++
++#ifndef DBUS_USB_RXQUEUE_LOWER_WATERMARK
++/* add a new batch req to rx queue when waiting item count reduce to this number */
++#define DBUS_USB_RXQUEUE_LOWER_WATERMARK      4
++#endif
++
++enum usbos_suspend_state {
++	USBOS_SUSPEND_STATE_DEVICE_ACTIVE = 0, /* Device is busy, won't allow suspend */
++	USBOS_SUSPEND_STATE_SUSPEND_PENDING,   /* Device is idle, can be suspended */
++	                                       /* Wating PM to suspend */
++	USBOS_SUSPEND_STATE_SUSPENDED          /* Device suspended */
++};
++
++enum usbos_request_state {
++	USBOS_REQUEST_STATE_UNSCHEDULED = 0,	/* USB TX request not scheduled */
++	USBOS_REQUEST_STATE_SCHEDULED,		/* USB TX request given to TX thread */
++	USBOS_REQUEST_STATE_SUBMITTED		/* USB TX request submitted */
++};
++
++typedef struct {
++	uint32 notification;
++	uint32 reserved;
++} intr_t;
++
++typedef struct {
++	dbus_pub_t *pub;
++
++	void *cbarg;
++	dbus_intf_callbacks_t *cbs;
++
++	/* Imported */
++	struct usb_device *usb;	/* USB device pointer from OS */
++	struct urb *intr_urb; /* URB for interrupt endpoint */
++	struct list_head req_rxfreeq;
++	struct list_head req_txfreeq;
++	struct list_head req_rxpostedq;	/* Posted down to USB driver for RX */
++	struct list_head req_txpostedq;	/* Posted down to USB driver for TX */
++	spinlock_t rxfree_lock; /* Lock for rx free list */
++	spinlock_t txfree_lock; /* Lock for tx free list */
++	spinlock_t rxposted_lock; /* Lock for rx posted list */
++	spinlock_t txposted_lock; /* Lock for tx posted list */
++	uint rx_pipe, tx_pipe, intr_pipe, rx_pipe2; /* Pipe numbers for USB I/O */
++	uint rxbuf_len;
++
++	struct list_head req_rxpendingq; /* RXDPC: Pending for dpc to send up */
++	spinlock_t rxpending_lock;	/* RXDPC: Lock for rx pending list */
++	long dpc_pid;
++	struct semaphore dpc_sem;
++	struct completion dpc_exited;
++	int rxpending;
++#if defined(DBUS_LINUX_HIST)
++	int	dpc_cnt, dpc_pktcnt, dpc_maxpktcnt;
++#endif
++
++	struct urb               *ctl_urb;
++	int                      ctl_in_pipe, ctl_out_pipe;
++	struct usb_ctrlrequest   ctl_write;
++	struct usb_ctrlrequest   ctl_read;
++	struct semaphore         ctl_lock;     /* Lock for CTRL transfers via tx_thread */
++#ifdef USBOS_TX_THREAD
++	enum usbos_request_state ctl_state;
++#endif /* USBOS_TX_THREAD */
++
++	spinlock_t rxlock;      /* Lock for rxq management */
++	spinlock_t txlock;      /* Lock for txq management */
++
++	int intr_size;          /* Size of interrupt message */
++	int interval;           /* Interrupt polling interval */
++	intr_t intr;            /* Data buffer for interrupt endpoint */
++
++	int maxps;
++	atomic_t txposted;
++	atomic_t rxposted;
++	atomic_t txallocated;
++	atomic_t rxallocated;
++	bool rxctl_deferrespok;	/* Get a response for setup from dongle */
++
++	wait_queue_head_t wait;
++	bool waitdone;
++	int sync_urb_status;
++
++	struct urb *blk_urb; /* Used for downloading embedded image */
++
++#if defined(DBUS_LINUX_HIST)
++	int *txposted_hist;
++	int *rxposted_hist;
++#endif
++#ifdef USBOS_THREAD
++	spinlock_t              ctrl_lock;
++	spinlock_t              usbos_list_lock;
++	struct list_head        usbos_list;
++	struct list_head        usbos_free_list;
++	atomic_t                usbos_list_cnt;
++	wait_queue_head_t       usbos_queue_head;
++	struct task_struct      *usbos_kt;
++#endif /* USBOS_THREAD */
++
++#ifdef USBOS_TX_THREAD
++	spinlock_t              usbos_tx_list_lock;
++	struct list_head	usbos_tx_list;
++	wait_queue_head_t	usbos_tx_queue_head;
++	struct task_struct      *usbos_tx_kt;
++#endif /* USBOS_TX_THREAD */
++
++	struct dma_pool *qtd_pool; /* QTD pool for USB optimization only */
++	int tx_ep, rx_ep, rx2_ep;  /* EPs for USB optimization */
++	struct usb_device *usb_device; /* USB device for optimization */
++#if defined(EHCI_FASTPATH_TX) || defined(EHCI_FASTPATH_RX) /** Linux USB AP related */
++	spinlock_t fastpath_lock;
++#endif
++} usbos_info_t;
++
++typedef struct urb_req {
++	void         *pkt;
++	int          buf_len;
++	struct urb   *urb;
++	void         *arg;
++	usbos_info_t *usbinfo;
++	struct list_head urb_list;
++} urb_req_t;
++
++#ifdef USBOS_THREAD
++typedef struct usbos_list_entry {
++	struct list_head    list;   /* must be first */
++	void               *urb_context;
++	int                 urb_length;
++	int                 urb_status;
++} usbos_list_entry_t;
++
++static void* dbus_usbos_thread_init(usbos_info_t *usbos_info);
++static void  dbus_usbos_thread_deinit(usbos_info_t *usbos_info);
++static void  dbus_usbos_dispatch_schedule(CALLBACK_ARGS);
++static int   dbus_usbos_thread_func(void *data);
++#endif /* USBOS_THREAD */
++
++#ifdef USBOS_TX_THREAD
++void* dbus_usbos_tx_thread_init(usbos_info_t *usbos_info);
++void  dbus_usbos_tx_thread_deinit(usbos_info_t *usbos_info);
++int   dbus_usbos_tx_thread_func(void *data);
++#endif /* USBOS_TX_THREAD */
++
++/* Shared Function prototypes */
++bool dbus_usbos_dl_cmd(usbos_info_t *usbinfo, uint8 cmd, void *buffer, int buflen);
++int dbus_usbos_wait(usbos_info_t *usbinfo, uint16 ms);
++bool dbus_usbos_dl_send_bulk(usbos_info_t *usbinfo, void *buffer, int len);
++int dbus_write_membytes(usbos_info_t *usbinfo, bool set, uint32 address, uint8 *data, uint size);
++
++/* Local function prototypes */
++static void dbus_usbos_send_complete(CALLBACK_ARGS);
++#ifdef DBUS_LINUX_RXDPC
++static void dbus_usbos_recv_dpc(usbos_info_t *usbos_info);
++static int dbus_usbos_dpc_thread(void *data);
++#endif /* DBUS_LINUX_RXDPC */
++static void dbus_usbos_recv_complete(CALLBACK_ARGS);
++static int  dbus_usbos_errhandler(void *bus, int err);
++static int  dbus_usbos_state_change(void *bus, int state);
++static void dbusos_stop(usbos_info_t *usbos_info);
++
++#ifdef KERNEL26
++static int dbus_usbos_probe(struct usb_interface *intf, const struct usb_device_id *id);
++static void dbus_usbos_disconnect(struct usb_interface *intf);
++#if defined(USB_SUSPEND_AVAILABLE)
++static int dbus_usbos_resume(struct usb_interface *intf);
++static int dbus_usbos_suspend(struct usb_interface *intf, pm_message_t message);
++/* at the moment, used for full dongle host driver only */
++static int dbus_usbos_reset_resume(struct usb_interface *intf);
++#endif /* USB_SUSPEND_AVAILABLE */
++#else /* KERNEL26 */
++static void *dbus_usbos_probe(struct usb_device *usb, unsigned int ifnum,
++	const struct usb_device_id *id);
++static void dbus_usbos_disconnect(struct usb_device *usb, void *ptr);
++#endif /* KERNEL26 */
++
++#ifdef USB_TRIGGER_DEBUG
++static bool dbus_usbos_ctl_send_debugtrig(usbos_info_t *usbinfo);
++#endif /* USB_TRIGGER_DEBUG */
++
++#ifdef KEEPIF_ON_DEVICE_RESET
++enum usb_dev_status {
++	USB_DEVICE_INIT = 0,
++	USB_DEVICE_RESETTED = 1,
++	USB_DEVICE_DISCONNECTED = 2,
++	USB_DEVICE_PROBED
++};
++static int dbus_usbos_usbreset_func(void *data);
++#endif /* KEEPIF_ON_DEVICE_RESET */
++
++/**
++ * have to disable missing-field-initializers warning as last element {} triggers it
++ * and different versions of kernel have different number of members so it is impossible
++ * to specify the initializer. BTW issuing the warning here is bug og GCC as  universal
++ * zero {0} specified in C99 standard as correct way of initialization of struct to all zeros
++ */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
++#endif
++
++static struct usb_device_id devid_table[] = {
++	{ USB_DEVICE(BCM_DNGL_VID, 0x0000) }, /* Configurable via register() */
++#if defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW)
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_4328) },
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_4322) },
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_4319) },
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_43236) },
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_43143) },
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_43242) },
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_4360) },
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_4350) },
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BL_PID_43569) },
++#endif
++#ifdef EXTENDED_VID_PID
++	EXTENDED_VID_PID,
++#endif /* EXTENDED_VID_PID */
++	{ USB_DEVICE(BCM_DNGL_VID, BCM_DNGL_BDC_PID) }, /* Default BDC */
++	{ USB_DEVICE(CY_DNGL_VID, BCM_DNGL_BDC_PID) },  /* CY Default BDC */
++	{ }
++};
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++#pragma GCC diagnostic pop
++#endif
++
++MODULE_DEVICE_TABLE(usb, devid_table);
++
++/** functions called by the Linux kernel USB subsystem */
++static struct usb_driver dbus_usbdev = {
++	name:           "dbus_usbdev",
++	probe:          dbus_usbos_probe,
++	disconnect:     dbus_usbos_disconnect,
++	id_table:       devid_table,
++#if defined(USB_SUSPEND_AVAILABLE)
++	suspend:        dbus_usbos_suspend,
++	resume:         dbus_usbos_resume,
++	reset_resume:	dbus_usbos_reset_resume,
++	/* Linux USB core will allow autosuspend for devices bound to this driver */
++	supports_autosuspend: 1
++#endif /* USB_SUSPEND_AVAILABLE */
++};
++
++/**
++ * This stores USB info during Linux probe callback since attach() is not called yet at this point
++ */
++typedef struct {
++	void    *usbos_info;
++	struct usb_device *usb; /* USB device pointer from OS */
++	uint    rx_pipe;   /* Pipe numbers for USB I/O */
++	uint    tx_pipe;   /* Pipe numbers for USB I/O */
++	uint    intr_pipe; /* Pipe numbers for USB I/O */
++	uint    rx_pipe2;  /* Pipe numbers for USB I/O */
++	int     intr_size; /* Size of interrupt message */
++	int     interval;  /* Interrupt polling interval */
++	bool    dldone;
++	int     vid;
++	int     pid;
++	bool    dereged;
++	bool    disc_cb_done;
++	DEVICE_SPEED    device_speed;
++	enum usbos_suspend_state suspend_state;
++	struct usb_interface     *intf;
++#ifdef KEEPIF_ON_DEVICE_RESET
++	bool                  keepif_on_devreset; /* if need keep network interface on dev reset */
++	bool                  dev_resetted; /* if dev reset event occured */
++	enum dbus_state       busstate_bf_devreset; /* busstate before devreset */
++	atomic_t              usbdev_stat; /* device status: resetted? disconnected? re-probed? */
++	wait_queue_head_t     usbreset_queue_head; /* kernel thread waiting queue */
++	struct task_struct    *usbreset_kt; /* kernel thread handle dev reset/probe event */
++#endif /* KEEPIF_ON_DEVICE_RESET */
++} probe_info_t;
++
++/*
++ * USB Linux dbus_intf_t
++ */
++static void dbus_usbos_init_info(void);
++static void *dbus_usbos_intf_attach(dbus_pub_t *pub, void *cbarg, dbus_intf_callbacks_t *cbs);
++static void dbus_usbos_intf_detach(dbus_pub_t *pub, void *info);
++static int  dbus_usbos_intf_send_irb(void *bus, dbus_irb_tx_t *txirb);
++static int  dbus_usbos_intf_recv_irb(void *bus, dbus_irb_rx_t *rxirb);
++static int  dbus_usbos_intf_recv_irb_from_ep(void *bus, dbus_irb_rx_t *rxirb, uint32 ep_idx);
++static int  dbus_usbos_intf_cancel_irb(void *bus, dbus_irb_tx_t *txirb);
++static int  dbus_usbos_intf_send_ctl(void *bus, uint8 *buf, int len);
++static int  dbus_usbos_intf_recv_ctl(void *bus, uint8 *buf, int len);
++static int  dbus_usbos_intf_get_attrib(void *bus, dbus_attrib_t *attrib);
++static int  dbus_usbos_intf_up(void *bus);
++static int  dbus_usbos_intf_down(void *bus);
++static int  dbus_usbos_intf_stop(void *bus);
++static int  dbus_usbos_readreg(void *bus, uint32 regaddr, int datalen, uint32 *value);
++extern int dbus_usbos_loopback_tx(void *usbos_info_ptr, int cnt, int size);
++int dbus_usbos_writereg(void *bus, uint32 regaddr, int datalen, uint32 data);
++#if defined(DBUS_LINUX_HIST)
++static void dbus_usbos_intf_dump(void *bus, struct bcmstrbuf *b);
++#endif 
++static int  dbus_usbos_intf_set_config(void *bus, dbus_config_t *config);
++static bool dbus_usbos_intf_recv_needed(void *bus);
++static void *dbus_usbos_intf_exec_rxlock(void *bus, exec_cb_t cb, struct exec_parms *args);
++static void *dbus_usbos_intf_exec_txlock(void *bus, exec_cb_t cb, struct exec_parms *args);
++#ifdef BCMUSBDEV_COMPOSITE
++static int dbus_usbos_intf_wlan(struct usb_device *usb);
++#endif /* BCMUSBDEV_COMPOSITE */
++
++/** functions called by dbus_usb.c */
++static dbus_intf_t dbus_usbos_intf = {
++	.attach = dbus_usbos_intf_attach,
++	.detach = dbus_usbos_intf_detach,
++	.up = dbus_usbos_intf_up,
++	.down = dbus_usbos_intf_down,
++	.send_irb = dbus_usbos_intf_send_irb,
++	.recv_irb = dbus_usbos_intf_recv_irb,
++	.cancel_irb = dbus_usbos_intf_cancel_irb,
++	.send_ctl = dbus_usbos_intf_send_ctl,
++	.recv_ctl = dbus_usbos_intf_recv_ctl,
++	.get_stats = NULL,
++	.get_attrib = dbus_usbos_intf_get_attrib,
++	.remove = NULL,
++	.resume = NULL,
++	.suspend = NULL,
++	.stop = dbus_usbos_intf_stop,
++	.reset = NULL,
++	.pktget = NULL,
++	.pktfree = NULL,
++	.iovar_op = NULL,
++#if defined(DBUS_LINUX_HIST)
++	.dump = dbus_usbos_intf_dump,
++#else
++	.dump = NULL,
++#endif 
++	.set_config = dbus_usbos_intf_set_config,
++	.get_config = NULL,
++	.device_exists = NULL,
++	.dlneeded = NULL,
++	.dlstart = NULL,
++	.dlrun = NULL,
++	.recv_needed = dbus_usbos_intf_recv_needed,
++	.exec_rxlock = dbus_usbos_intf_exec_rxlock,
++	.exec_txlock = dbus_usbos_intf_exec_txlock,
++
++	.tx_timer_init = NULL,
++	.tx_timer_start = NULL,
++	.tx_timer_stop = NULL,
++
++	.sched_dpc = NULL,
++	.lock = NULL,
++	.unlock = NULL,
++	.sched_probe_cb = NULL,
++
++	.shutdown = NULL,
++
++	.recv_stop = NULL,
++	.recv_resume = NULL,
++
++	.recv_irb_from_ep = dbus_usbos_intf_recv_irb_from_ep,
++	.readreg = dbus_usbos_readreg
++};
++
++static probe_info_t    g_probe_info;
++static probe_cb_t      probe_cb = NULL;
++static disconnect_cb_t disconnect_cb = NULL;
++static void            *probe_arg = NULL;
++static void            *disc_arg = NULL;
++
++#if defined(EHCI_FASTPATH_TX) || defined(EHCI_FASTPATH_RX)
++
++#define EHCI_PAGE_SIZE    4096
++
++/* Copies of structures located elsewhere. */
++
++typedef struct {
++	dbus_pub_t *pub;
++
++	void *cbarg;
++	dbus_intf_callbacks_t *cbs;
++	dbus_intf_t *drvintf;
++	void *usbosl_info;
++} usb_info_t;
++
++/** General info for all BUS */
++typedef struct dbus_irbq {
++	dbus_irb_t *head;
++	dbus_irb_t *tail;
++	int cnt;
++} dbus_irbq_t;
++
++/**
++ * This private structure dbus_info_t is also declared in dbus.c.
++ * All the fields must be consistent in both declarations.
++ */
++typedef struct dbus_info {
++	dbus_pub_t pub; /* MUST BE FIRST */
++
++	void *cbarg;
++	dbus_callbacks_t *cbs;
++	void *bus_info;
++	dbus_intf_t *drvintf;
++	uint8 *fw;
++	int fwlen;
++	uint32 errmask;
++	int rx_low_watermark;
++	int tx_low_watermark;
++	bool txoff;
++	bool txoverride;
++	bool rxoff;
++	bool tx_timer_ticking;
++	dbus_irbq_t *rx_q;
++	dbus_irbq_t *tx_q;
++
++#ifdef EHCI_FASTPATH_RX
++	atomic_t rx_outstanding;
++#endif
++	uint8 *nvram;
++	int	nvram_len;
++	uint8 *image;	/* buffer for combine fw and nvram */
++	int image_len;
++	uint8 *orig_fw;
++	int origfw_len;
++	int decomp_memsize;
++	dbus_extdl_t extdl;
++	int nvram_nontxt;
++} dbus_info_t;
++
++static atomic_t s_tx_pending;
++
++static int optimize_init(usbos_info_t *usbos_info, struct usb_device *usb, int out,
++	int in, int in2);
++static int optimize_deinit(usbos_info_t *usbos_info, struct usb_device *usb);
++#endif  /* #if defined(EHCI_FASTPATH_TX) || defined(EHCI_FASTPATH_RX) */
++
++
++static volatile int loopback_rx_cnt, loopback_tx_cnt;
++int loopback_size;
++bool is_loopback_pkt(void *buf);
++int matches_loopback_pkt(void *buf);
++
++/**
++ * multiple code paths in this file dequeue a URB request, this function makes sure that it happens
++ * in a concurrency save manner. Don't call this from a sleepable process context.
++ */
++static urb_req_t * BCMFASTPATH
++dbus_usbos_qdeq(struct list_head *urbreq_q, spinlock_t *lock)
++{
++	unsigned long flags;
++	urb_req_t *req;
++
++	ASSERT(urbreq_q != NULL);
++
++	spin_lock_irqsave(lock, flags);
++
++	if (list_empty(urbreq_q)) {
++		req = NULL;
++	} else {
++		ASSERT(urbreq_q->next != NULL);
++		ASSERT(urbreq_q->next != urbreq_q);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++		req = list_entry(urbreq_q->next, urb_req_t, urb_list);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++		list_del_init(&req->urb_list);
++	}
++
++	spin_unlock_irqrestore(lock, flags);
++
++	return req;
++}
++
++static void BCMFASTPATH
++dbus_usbos_qenq(struct list_head *urbreq_q, urb_req_t *req, spinlock_t *lock)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(lock, flags);
++
++	list_add_tail(&req->urb_list, urbreq_q);
++
++	spin_unlock_irqrestore(lock, flags);
++}
++
++/**
++ * multiple code paths in this file remove a URB request from a list, this function makes sure that
++ * it happens in a concurrency save manner. Don't call this from a sleepable process context.
++ * Is quite similar to dbus_usbos_qdeq(), I wonder why this function is needed.
++ */
++static void
++dbus_usbos_req_del(urb_req_t *req, spinlock_t *lock)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(lock, flags);
++
++	list_del_init(&req->urb_list);
++
++	spin_unlock_irqrestore(lock, flags);
++}
++
++
++/**
++ * Driver requires a pool of URBs to operate. This function is called during
++ * initialization (attach phase), allocates a number of URBs, and puts them
++ * on the free (req_rxfreeq and req_txfreeq) queue
++ */
++static int
++dbus_usbos_urbreqs_alloc(usbos_info_t *usbos_info, uint32 count, bool is_rx)
++{
++	int i;
++	int allocated = 0;
++	int err = DBUS_OK;
++
++	for (i = 0; i < count; i++) {
++		urb_req_t *req;
++
++		req = MALLOC(usbos_info->pub->osh, sizeof(urb_req_t));
++		if (req == NULL) {
++			DBUSERR(("%s: MALLOC req failed\n", __FUNCTION__));
++			err = DBUS_ERR_NOMEM;
++			goto fail;
++		}
++		bzero(req, sizeof(urb_req_t));
++
++		req->urb = USB_ALLOC_URB();
++		if (req->urb == NULL) {
++			DBUSERR(("%s: USB_ALLOC_URB req->urb failed\n", __FUNCTION__));
++			err = DBUS_ERR_NOMEM;
++			goto fail;
++		}
++
++		INIT_LIST_HEAD(&req->urb_list);
++
++		if (is_rx) {
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++			/* don't allocate now. Do it on demand */
++			req->pkt = NULL;
++#else
++			/* pre-allocate  buffers never to be released */
++			req->pkt = MALLOC(usbos_info->pub->osh, usbos_info->rxbuf_len);
++			if (req->pkt == NULL) {
++				DBUSERR(("%s: MALLOC req->pkt failed\n", __FUNCTION__));
++				err = DBUS_ERR_NOMEM;
++				goto fail;
++			}
++#endif
++			req->buf_len = usbos_info->rxbuf_len;
++			dbus_usbos_qenq(&usbos_info->req_rxfreeq, req, &usbos_info->rxfree_lock);
++		} else {
++			req->buf_len = 0;
++			dbus_usbos_qenq(&usbos_info->req_txfreeq, req, &usbos_info->txfree_lock);
++		}
++		allocated++;
++		continue;
++
++fail:
++		if (req) {
++			if (is_rx && req->pkt) {
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++				/* req->pkt is NULL in "NOCOPY" mode */
++#else
++				MFREE(usbos_info->pub->osh, req->pkt, req->buf_len);
++#endif
++			}
++			if (req->urb) {
++				USB_FREE_URB(req->urb);
++			}
++			MFREE(usbos_info->pub->osh, req, sizeof(urb_req_t));
++		}
++		break;
++	}
++
++	atomic_add(allocated, is_rx ? &usbos_info->rxallocated : &usbos_info->txallocated);
++
++	if (is_rx) {
++		DBUSTRACE(("%s: add %d (total %d) rx buf, each has %d bytes\n", __FUNCTION__,
++			allocated, atomic_read(&usbos_info->rxallocated), usbos_info->rxbuf_len));
++	} else {
++		DBUSTRACE(("%s: add %d (total %d) tx req\n", __FUNCTION__,
++			allocated, atomic_read(&usbos_info->txallocated)));
++	}
++
++	return err;
++} /* dbus_usbos_urbreqs_alloc */
++
++/** Typically called during detach or when attach failed. Don't call until all URBs unlinked */
++static int
++dbus_usbos_urbreqs_free(usbos_info_t *usbos_info, bool is_rx)
++{
++	int rtn = 0;
++	urb_req_t *req;
++	struct list_head *req_q;
++	spinlock_t *lock;
++
++	if (is_rx) {
++		req_q = &usbos_info->req_rxfreeq;
++		lock = &usbos_info->rxfree_lock;
++	} else {
++		req_q = &usbos_info->req_txfreeq;
++		lock = &usbos_info->txfree_lock;
++	}
++	while ((req = dbus_usbos_qdeq(req_q, lock)) != NULL) {
++
++		if (is_rx) {
++			if (req->pkt) {
++				/* We do MFREE instead of PKTFREE because the pkt has been
++				 * converted to native already
++				 */
++				MFREE(usbos_info->pub->osh, req->pkt, req->buf_len);
++				req->pkt = NULL;
++				req->buf_len = 0;
++			}
++		} else {
++			/* sending req should not be assigned pkt buffer */
++			ASSERT(req->pkt == NULL);
++		}
++
++		if (req->urb) {
++			USB_FREE_URB(req->urb);
++			req->urb = NULL;
++		}
++		MFREE(usbos_info->pub->osh, req, sizeof(urb_req_t));
++
++		rtn++;
++	}
++	return rtn;
++} /* dbus_usbos_urbreqs_free */
++
++/**
++ * called by Linux kernel on URB completion. Upper DBUS layer (dbus_usb.c) has to be notified of
++ * send completion.
++ */
++void
++dbus_usbos_send_complete(CALLBACK_ARGS)
++{
++	urb_req_t *req = urb->context;
++	dbus_irb_tx_t *txirb = req->arg;
++	usbos_info_t *usbos_info = req->usbinfo;
++	unsigned long flags;
++	int status = DBUS_OK;
++	int txposted;
++
++	USB_AUTOPM_PUT_INTERFACE_ASYNC(g_probe_info.intf);
++
++	spin_lock_irqsave(&usbos_info->txlock, flags);
++
++	dbus_usbos_req_del(req, &usbos_info->txposted_lock);
++	txposted = atomic_dec_return(&usbos_info->txposted);
++#if defined(DBUS_LINUX_HIST)
++	if (usbos_info->txposted_hist) {
++		usbos_info->txposted_hist[txposted]++;
++	}
++#endif 
++	if (unlikely (txposted < 0)) {
++		DBUSERR(("%s ERROR: txposted is negative (%d)!!\n", __FUNCTION__, txposted));
++	}
++	spin_unlock_irqrestore(&usbos_info->txlock, flags);
++
++	if (unlikely (urb->status)) {
++		status = DBUS_ERR_TXFAIL;
++		DBUSTRACE(("txfail status %d\n", urb->status));
++	}
++
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++	/* sending req should not be assigned pkt buffer */
++	ASSERT(req->pkt == NULL);
++#endif
++	/*  txirb should always be set, except for ZLP. ZLP is reusing this callback function. */
++	if (txirb != NULL) {
++		if (txirb->send_buf != NULL) {
++			MFREE(usbos_info->pub->osh, txirb->send_buf, req->buf_len);
++			txirb->send_buf = NULL;
++			req->buf_len = 0;
++		}
++		if (likely (usbos_info->cbarg && usbos_info->cbs)) {
++			if (likely (usbos_info->cbs->send_irb_complete != NULL))
++			    usbos_info->cbs->send_irb_complete(usbos_info->cbarg, txirb, status);
++		}
++	}
++
++	dbus_usbos_qenq(&usbos_info->req_txfreeq, req, &usbos_info->txfree_lock);
++} /* dbus_usbos_send_complete */
++
++/**
++ * In order to receive USB traffic from the dongle, we need to supply the Linux kernel with a free
++ * URB that is going to contain received data.
++ */
++static int BCMFASTPATH
++dbus_usbos_recv_urb_submit(usbos_info_t *usbos_info, dbus_irb_rx_t *rxirb, uint32 ep_idx)
++{
++	urb_req_t *req;
++	int ret = DBUS_OK;
++	unsigned long flags;
++	void *p;
++	uint rx_pipe;
++	int rxposted;
++
++	BCM_REFERENCE(rxposted);
++
++	if (!(req = dbus_usbos_qdeq(&usbos_info->req_rxfreeq, &usbos_info->rxfree_lock))) {
++		DBUSTRACE(("%s No free URB!\n", __FUNCTION__));
++		return DBUS_ERR_RXDROP;
++	}
++
++	spin_lock_irqsave(&usbos_info->rxlock, flags);
++
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++	req->pkt = rxirb->pkt = PKTGET(usbos_info->pub->osh, req->buf_len, FALSE);
++	if (!rxirb->pkt) {
++		DBUSERR(("%s: PKTGET failed\n", __FUNCTION__));
++		dbus_usbos_qenq(&usbos_info->req_rxfreeq, req, &usbos_info->rxfree_lock);
++		ret = DBUS_ERR_RXDROP;
++		goto fail;
++	}
++	/* consider the packet "native" so we don't count it as MALLOCED in the osl */
++	PKTTONATIVE(usbos_info->pub->osh, req->pkt);
++	rxirb->buf = NULL;
++	p = PKTDATA(usbos_info->pub->osh, req->pkt);
++#else
++	if (req->buf_len != usbos_info->rxbuf_len) {
++		ASSERT(req->pkt);
++		MFREE(usbos_info->pub->osh, req->pkt, req->buf_len);
++		DBUSTRACE(("%s: replace rx buff: old len %d, new len %d\n", __FUNCTION__,
++			req->buf_len, usbos_info->rxbuf_len));
++		req->buf_len = 0;
++		req->pkt = MALLOC(usbos_info->pub->osh, usbos_info->rxbuf_len);
++		if (req->pkt == NULL) {
++			DBUSERR(("%s: MALLOC req->pkt failed\n", __FUNCTION__));
++			ret = DBUS_ERR_NOMEM;
++			goto fail;
++		}
++		req->buf_len = usbos_info->rxbuf_len;
++	}
++	rxirb->buf = req->pkt;
++	p = rxirb->buf;
++#endif /* defined(BCM_RPC_NOCOPY) */
++	rxirb->buf_len = req->buf_len;
++	req->usbinfo = usbos_info;
++	req->arg = rxirb;
++	if (ep_idx == 0) {
++		rx_pipe = usbos_info->rx_pipe;
++	} else {
++		rx_pipe = usbos_info->rx_pipe2;
++		ASSERT(usbos_info->rx_pipe2);
++	}
++	/* Prepare the URB */
++	usb_fill_bulk_urb(req->urb, usbos_info->usb, rx_pipe,
++		p,
++		rxirb->buf_len,
++		(usb_complete_t)dbus_usbos_recv_complete, req);
++		req->urb->transfer_flags |= URB_QUEUE_BULK;
++
++	if ((ret = USB_SUBMIT_URB(req->urb))) {
++		DBUSERR(("%s USB_SUBMIT_URB failed. status %d\n", __FUNCTION__, ret));
++		dbus_usbos_qenq(&usbos_info->req_rxfreeq, req, &usbos_info->rxfree_lock);
++		ret = DBUS_ERR_RXFAIL;
++		goto fail;
++	}
++	rxposted = atomic_inc_return(&usbos_info->rxposted);
++#if defined(DBUS_LINUX_HIST)
++	if (usbos_info->rxposted_hist) {
++		usbos_info->rxposted_hist[rxposted]++;
++	}
++#endif 
++
++	dbus_usbos_qenq(&usbos_info->req_rxpostedq, req, &usbos_info->rxposted_lock);
++fail:
++	spin_unlock_irqrestore(&usbos_info->rxlock, flags);
++	return ret;
++} /* dbus_usbos_recv_urb_submit */
++
++#ifdef DBUS_LINUX_RXDPC
++
++static void BCMFASTPATH
++dbus_usbos_recv_dpc(usbos_info_t *usbos_info)
++{
++	urb_req_t *req = NULL;
++	dbus_irb_rx_t *rxirb = NULL;
++	int dbus_status = DBUS_OK;
++	bool killed = (g_probe_info.suspend_state == USBOS_SUSPEND_STATE_SUSPEND_PENDING) ? 1 : 0;
++
++#if defined(DBUS_LINUX_HIST)
++	int cnt = 0;
++
++	usbos_info->dpc_cnt++;
++#endif 
++
++	while ((req = dbus_usbos_qdeq(&usbos_info->req_rxpendingq,
++		&usbos_info->rxpending_lock)) != NULL) {
++		struct urb *urb = req->urb;
++		rxirb = req->arg;
++
++		/* Handle errors */
++		if (urb->status) {
++			/*
++			 * Linux 2.4 disconnect: -ENOENT or -EILSEQ for CRC error; rmmod: -ENOENT
++			 * Linux 2.6 disconnect: -EPROTO, rmmod: -ESHUTDOWN
++			 */
++			if ((urb->status == -ENOENT && (!killed)) || urb->status == -ESHUTDOWN) {
++				/* NOTE: unlink() can not be called from URB callback().
++				 * Do not call dbusos_stop() here.
++				 */
++				dbus_usbos_state_change(usbos_info, DBUS_STATE_DOWN);
++			} else if (urb->status == -EPROTO) {
++			} else {
++				DBUSERR(("%s rx error %d\n", __FUNCTION__, urb->status));
++				dbus_usbos_errhandler(usbos_info, DBUS_ERR_RXFAIL);
++			}
++
++			/* On error, don't submit more URBs yet */
++			DBUSERR(("%s %d rx error %d\n", __FUNCTION__, __LINE__, urb->status));
++			rxirb->buf = NULL;
++			rxirb->actual_len = 0;
++			dbus_status = DBUS_ERR_RXFAIL;
++			goto fail;
++		}
++
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++		/* detach the packet from the req */
++		req->pkt = NULL;
++#endif
++		/* Make the skb represent the received urb */
++		rxirb->actual_len = urb->actual_length;
++
++fail:
++		usbos_info->rxpending--;
++#if defined(DBUS_LINUX_HIST)
++		cnt++;
++#endif 
++		if (usbos_info->cbarg && usbos_info->cbs &&
++			usbos_info->cbs->recv_irb_complete) {
++			usbos_info->cbs->recv_irb_complete(usbos_info->cbarg, rxirb, dbus_status);
++		}
++		dbus_usbos_qenq(&usbos_info->req_rxfreeq, req, &usbos_info->rxfree_lock);
++	}
++
++#if defined(DBUS_LINUX_HIST)
++	usbos_info->dpc_pktcnt += cnt;
++	usbos_info->dpc_maxpktcnt = MAX(cnt, usbos_info->dpc_maxpktcnt);
++#endif 
++#ifdef DBUS_LINUX_HIST
++	{
++		static unsigned long last_dump = 0;
++
++		/* dump every 20 sec */
++		if (jiffies > (last_dump + 20*HZ)) {
++			dbus_usbos_intf_dump(usbos_info, NULL);
++			last_dump = jiffies;
++		}
++	}
++#endif /* DBUS_LINUX_HIST */
++} /* dbus_usbos_recv_dpc */
++
++static int BCMFASTPATH
++dbus_usbos_dpc_thread(void *data)
++{
++	usbos_info_t *usbos_info = (usbos_info_t*)data;
++
++	DAEMONIZE("dbus_rx_dpc");
++	/* High priority for short response time. We will yield by ourselves. */
++	/* SET_NICE(-10); */
++
++	/* Run until signal received */
++	while (1) {
++		if (down_interruptible(&usbos_info->dpc_sem) == 0) {
++			dbus_usbos_recv_dpc(usbos_info);
++			RESCHED();
++		} else
++			break;
++	}
++
++	complete_and_exit(&usbos_info->dpc_exited, 0);
++	return 0;
++}
++
++#endif /* DBUS_LINUX_RXDPC */
++
++/**
++ * Called by worked thread when a 'receive URB' completed or Linux kernel when it returns a URB to
++ * this driver.
++ */
++static void BCMFASTPATH
++dbus_usbos_recv_complete_handle(urb_req_t *req, int len, int status)
++{
++#ifdef DBUS_LINUX_RXDPC
++	usbos_info_t *usbos_info = req->usbinfo;
++	unsigned long flags;
++	int rxallocated, rxposted;
++
++	spin_lock_irqsave(&usbos_info->rxlock, flags);
++	/* detach the packet from the queue */
++	dbus_usbos_req_del(req, &usbos_info->rxposted_lock);
++	rxposted = atomic_dec_return(&usbos_info->rxposted);
++	rxallocated = atomic_read(&usbos_info->rxallocated);
++
++	/* Enqueue to rxpending queue */
++	usbos_info->rxpending++;
++	dbus_usbos_qenq(&usbos_info->req_rxpendingq, req, &usbos_info->rxpending_lock);
++	spin_unlock_irqrestore(&usbos_info->rxlock, flags);
++
++#error "RX req/buf appending-mode not verified for DBUS_LINUX_RXDPC because it was disabled"
++	if ((rxallocated < usbos_info->pub->nrxq) && (!status) &&
++		(rxposted == DBUS_USB_RXQUEUE_LOWER_WATERMARK)) {
++			DBUSTRACE(("%s: need more rx buf: rxallocated %d rxposted %d!\n",
++				__FUNCTION__, rxallocated, rxposted));
++			dbus_usbos_urbreqs_alloc(usbos_info,
++				MIN(DBUS_USB_RXQUEUE_BATCH_ADD,
++				usbos_info->pub->nrxq - rxallocated), TRUE);
++	}
++#error "Please verify above code works if you happened to enable DBUS_LINUX_RXDPC!!"
++
++	/* Wake up dpc for further processing */
++	ASSERT(usbos_info->dpc_pid >= 0);
++	up(&usbos_info->dpc_sem);
++#else
++	dbus_irb_rx_t *rxirb = req->arg;
++	usbos_info_t *usbos_info = req->usbinfo;
++	unsigned long flags;
++	int rxallocated, rxposted;
++	int dbus_status = DBUS_OK;
++	bool killed = (g_probe_info.suspend_state == USBOS_SUSPEND_STATE_SUSPEND_PENDING) ? 1 : 0;
++
++	spin_lock_irqsave(&usbos_info->rxlock, flags);
++	dbus_usbos_req_del(req, &usbos_info->rxposted_lock);
++	rxposted = atomic_dec_return(&usbos_info->rxposted);
++	rxallocated = atomic_read(&usbos_info->rxallocated);
++	spin_unlock_irqrestore(&usbos_info->rxlock, flags);
++
++	if ((rxallocated < usbos_info->pub->nrxq) && (!status) &&
++		(rxposted == DBUS_USB_RXQUEUE_LOWER_WATERMARK)) {
++			DBUSTRACE(("%s: need more rx buf: rxallocated %d rxposted %d!\n",
++				__FUNCTION__, rxallocated, rxposted));
++			dbus_usbos_urbreqs_alloc(usbos_info,
++				MIN(DBUS_USB_RXQUEUE_BATCH_ADD,
++				usbos_info->pub->nrxq - rxallocated), TRUE);
++	}
++
++	/* Handle errors */
++	if (status) {
++		/*
++		 * Linux 2.4 disconnect: -ENOENT or -EILSEQ for CRC error; rmmod: -ENOENT
++		 * Linux 2.6 disconnect: -EPROTO, rmmod: -ESHUTDOWN
++		 */
++		if ((status == -ENOENT && (!killed))|| status == -ESHUTDOWN) {
++			/* NOTE: unlink() can not be called from URB callback().
++			 * Do not call dbusos_stop() here.
++			 */
++			DBUSTRACE(("%s rx error %d\n", __FUNCTION__, status));
++			dbus_usbos_state_change(usbos_info, DBUS_STATE_DOWN);
++		} else if (status == -EPROTO) {
++			DBUSTRACE(("%s rx error %d\n", __FUNCTION__, status));
++		} else if (killed && (status == -EHOSTUNREACH || status == -ENOENT)) {
++			/* Device is suspended */
++		} else {
++			DBUSTRACE(("%s rx error %d\n", __FUNCTION__, status));
++			dbus_usbos_errhandler(usbos_info, DBUS_ERR_RXFAIL);
++		}
++
++		/* On error, don't submit more URBs yet */
++		rxirb->buf = NULL;
++		rxirb->actual_len = 0;
++		dbus_status = DBUS_ERR_RXFAIL;
++		goto fail;
++	}
++
++	/* Make the skb represent the received urb */
++	rxirb->actual_len = len;
++
++	if (rxirb->actual_len < sizeof(uint32)) {
++		DBUSTRACE(("small pkt len %d, process as ZLP\n", rxirb->actual_len));
++		dbus_status = DBUS_ERR_RXZLP;
++	}
++
++fail:
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++	/* detach the packet from the queue */
++	req->pkt = NULL;
++#endif /* BCM_RPC_NOCOPY || BCM_RPC_RXNOCOPY */
++
++	if (usbos_info->cbarg && usbos_info->cbs) {
++		if (usbos_info->cbs->recv_irb_complete) {
++			usbos_info->cbs->recv_irb_complete(usbos_info->cbarg, rxirb, dbus_status);
++		}
++	}
++
++	dbus_usbos_qenq(&usbos_info->req_rxfreeq, req, &usbos_info->rxfree_lock);
++#endif /* DBUS_LINUX_RXDPC */
++
++	/* Mark the interface as busy to reset USB autosuspend timer */
++	USB_MARK_LAST_BUSY(usbos_info->usb);
++} /* dbus_usbos_recv_complete_handle */
++
++/** called by Linux kernel when it returns a URB to this driver */
++static void
++dbus_usbos_recv_complete(CALLBACK_ARGS)
++{
++#ifdef USBOS_THREAD
++	dbus_usbos_dispatch_schedule(CALLBACK_ARGS_DATA);
++#else /*  !USBOS_THREAD */
++	dbus_usbos_recv_complete_handle(urb->context, urb->actual_length, urb->status);
++#endif /*  USBOS_THREAD */
++}
++
++
++/**
++ * If Linux notifies our driver that a control read or write URB has completed, we should notify
++ * the DBUS layer above us (dbus_usb.c in this case).
++ */
++static void
++dbus_usbos_ctl_complete(usbos_info_t *usbos_info, int type, int urbstatus)
++{
++	int status = DBUS_ERR;
++
++	if (usbos_info == NULL)
++		return;
++
++	switch (urbstatus) {
++		case 0:
++			status = DBUS_OK;
++		break;
++		case -EINPROGRESS:
++		case -ENOENT:
++		default:
++#ifdef INTR_EP_ENABLE
++			DBUSERR(("%s:%d fail status %d bus:%d susp:%d intr:%d ctli:%d ctlo:%d\n",
++				__FUNCTION__, type, urbstatus,
++				usbos_info->pub->busstate, g_probe_info.suspend_state,
++				usbos_info->intr_urb_submitted, usbos_info->ctlin_urb_submitted,
++				usbos_info->ctlout_urb_submitted));
++#else
++			DBUSERR(("%s: failed with status %d\n", __FUNCTION__, urbstatus));
++			status = DBUS_ERR;
++		break;
++#endif /* INTR_EP_ENABLE */
++	}
++
++	if (usbos_info->cbarg && usbos_info->cbs) {
++		if (usbos_info->cbs->ctl_complete)
++			usbos_info->cbs->ctl_complete(usbos_info->cbarg, type, status);
++	}
++}
++
++/** called by Linux */
++static void
++dbus_usbos_ctlread_complete(CALLBACK_ARGS)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *)urb->context;
++
++	ASSERT(urb);
++	usbos_info = (usbos_info_t *)urb->context;
++
++	dbus_usbos_ctl_complete(usbos_info, DBUS_CBCTL_READ, urb->status);
++
++#ifdef USBOS_THREAD
++	if (usbos_info->rxctl_deferrespok) {
++		usbos_info->ctl_read.bRequestType = USB_DIR_IN | USB_TYPE_CLASS |
++		USB_RECIP_INTERFACE;
++		usbos_info->ctl_read.bRequest = 1;
++	}
++#endif
++
++	up(&usbos_info->ctl_lock);
++
++	USB_AUTOPM_PUT_INTERFACE_ASYNC(g_probe_info.intf);
++}
++
++/** called by Linux */
++static void
++dbus_usbos_ctlwrite_complete(CALLBACK_ARGS)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *)urb->context;
++
++	ASSERT(urb);
++	usbos_info = (usbos_info_t *)urb->context;
++
++	dbus_usbos_ctl_complete(usbos_info, DBUS_CBCTL_WRITE, urb->status);
++
++#ifdef USBOS_TX_THREAD
++	usbos_info->ctl_state = USBOS_REQUEST_STATE_UNSCHEDULED;
++#endif /* USBOS_TX_THREAD */
++
++	up(&usbos_info->ctl_lock);
++
++	USB_AUTOPM_PUT_INTERFACE_ASYNC(g_probe_info.intf);
++}
++
++#ifdef INTR_EP_ENABLE
++/** called by Linux */
++static void
++dbus_usbos_intr_complete(CALLBACK_ARGS)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *)urb->context;
++	bool killed = (g_probe_info.suspend_state == USBOS_SUSPEND_STATE_SUSPEND_PENDING) ? 1 : 0;
++
++	if (usbos_info == NULL || usbos_info->pub == NULL)
++		return;
++	if ((urb->status == -ENOENT && (!killed)) || urb->status == -ESHUTDOWN ||
++		urb->status == -ENODEV) {
++		dbus_usbos_state_change(usbos_info, DBUS_STATE_DOWN);
++	}
++
++	if (usbos_info->pub->busstate == DBUS_STATE_DOWN) {
++		DBUSERR(("%s: intr cb when DBUS down, ignoring\n", __FUNCTION__));
++		return;
++	}
++	dbus_usbos_ctl_complete(usbos_info, DBUS_CBINTR_POLL, urb->status);
++}
++#endif	/* INTR_EP_ENABLE */
++
++/**
++ * when the bus is going to sleep or halt, the Linux kernel requires us to take ownership of our
++ * URBs again. Multiple code paths in this file require a list of URBs to be cancelled in a
++ * concurrency save manner.
++ */
++static void
++dbus_usbos_unlink(struct list_head *urbreq_q, spinlock_t *lock)
++{
++	urb_req_t *req;
++
++	/* dbus_usbos_recv_complete() adds req back to req_freeq */
++	while ((req = dbus_usbos_qdeq(urbreq_q, lock)) != NULL) {
++		ASSERT(req->urb != NULL);
++		USB_UNLINK_URB(req->urb);
++	}
++}
++
++/** multiple code paths in this file require the bus to stop */
++static void
++dbus_usbos_cancel_all_urbs(usbos_info_t *usbos_info)
++{
++	int rxposted, txposted;
++
++	DBUSTRACE(("%s: unlink all URBs\n", __FUNCTION__));
++
++#ifdef USBOS_TX_THREAD
++	usbos_info->ctl_state = USBOS_REQUEST_STATE_UNSCHEDULED;
++
++	/* Yield the CPU to TX thread so all pending requests are submitted */
++	while (!list_empty(&usbos_info->usbos_tx_list)) {
++		wake_up_interruptible(&usbos_info->usbos_tx_queue_head);
++		OSL_SLEEP(10);
++	}
++#endif /* USBOS_TX_THREAD */
++
++	/* tell Linux kernel to cancel a single intr, ctl and blk URB */
++	if (usbos_info->intr_urb)
++		USB_UNLINK_URB(usbos_info->intr_urb);
++	if (usbos_info->ctl_urb)
++		USB_UNLINK_URB(usbos_info->ctl_urb);
++	if (usbos_info->blk_urb)
++		USB_UNLINK_URB(usbos_info->blk_urb);
++
++	dbus_usbos_unlink(&usbos_info->req_txpostedq, &usbos_info->txposted_lock);
++	dbus_usbos_unlink(&usbos_info->req_rxpostedq, &usbos_info->rxposted_lock);
++
++	/* Wait until the callbacks for all submitted URBs have been called, because the
++	 * handler needs to know is an USB suspend is in progress.
++	 */
++	SPINWAIT((atomic_read(&usbos_info->txposted) != 0 ||
++		atomic_read(&usbos_info->rxposted) != 0), 10000);
++
++	txposted = atomic_read(&usbos_info->txposted);
++	rxposted = atomic_read(&usbos_info->rxposted);
++	if (txposted != 0 || rxposted != 0) {
++		DBUSERR(("%s ERROR: REQs posted, rx=%d tx=%d!\n",
++			__FUNCTION__, rxposted, txposted));
++	}
++} /* dbus_usbos_cancel_all_urbs */
++
++/** multiple code paths require the bus to stop */
++static void
++dbusos_stop(usbos_info_t *usbos_info)
++{
++	urb_req_t *req;
++	int rxposted;
++	req = NULL;
++	BCM_REFERENCE(req);
++
++	ASSERT(usbos_info);
++
++#ifdef USB_TRIGGER_DEBUG
++	dbus_usbos_ctl_send_debugtrig(usbos_info);
++#endif /* USB_TRIGGER_DEBUG */
++	dbus_usbos_state_change(usbos_info, DBUS_STATE_DOWN);
++
++	dbus_usbos_cancel_all_urbs(usbos_info);
++
++#ifdef USBOS_THREAD
++	/* yield the CPU to rx packet thread */
++	while (1) {
++		if (atomic_read(&usbos_info->usbos_list_cnt) <= 0)	break;
++		wake_up_interruptible(&usbos_info->usbos_queue_head);
++		OSL_SLEEP(3);
++	}
++#endif /* USBOS_THREAD */
++
++	rxposted = atomic_read(&usbos_info->rxposted);
++	if (rxposted > 0) {
++		DBUSERR(("%s ERROR: rx REQs posted=%d in stop!\n", __FUNCTION__,
++			rxposted));
++	}
++
++	ASSERT(atomic_read(&usbos_info->txposted) == 0 && rxposted == 0);
++
++#ifdef DBUS_LINUX_RXDPC
++	/* Stop the dpc thread */
++	if (usbos_info->dpc_pid >= 0) {
++		KILL_PROC(usbos_info->dpc_pid, SIGTERM);
++		wait_for_completion(&usbos_info->dpc_exited);
++	}
++
++	/* Move pending reqs to free queue so they can be freed */
++	while ((req = dbus_usbos_qdeq(&usbos_info->req_rxpendingq,
++		&usbos_info->rxpending_lock)) != NULL) {
++		dbus_usbos_qenq(&usbos_info->req_rxfreeq, req,
++			&usbos_info->rxfree_lock);
++	}
++#endif /* DBUS_LINUX_RXDPC */
++} /* dbusos_stop */
++
++#if defined(USB_SUSPEND_AVAILABLE)
++
++/**
++ * Linux kernel sports a 'USB auto suspend' feature. See: http://lwn.net/Articles/373550/
++ * The suspend method is called by the Linux kernel to warn the driver that the device is going to
++ * be suspended.  If the driver returns a negative error code, the suspend will be aborted. If the
++ * driver returns 0, it must cancel all outstanding URBs (usb_kill_urb()) and not submit any more.
++ */
++static int
++dbus_usbos_suspend(struct usb_interface *intf,
++            pm_message_t message)
++{
++	DBUSERR(("%s suspend state: %d\n", __FUNCTION__, g_probe_info.suspend_state));
++	/* DHD for full dongle model */
++	g_probe_info.suspend_state = USBOS_SUSPEND_STATE_SUSPEND_PENDING;
++	dbus_usbos_state_change((usbos_info_t*)g_probe_info.usbos_info, DBUS_STATE_SLEEP);
++	dbus_usbos_cancel_all_urbs((usbos_info_t*)g_probe_info.usbos_info);
++	g_probe_info.suspend_state = USBOS_SUSPEND_STATE_SUSPENDED;
++
++	return 0;
++}
++
++/**
++ * The resume method is called to tell the driver that the device has been resumed and the driver
++ * can return to normal operation.  URBs may once more be submitted.
++ */
++static int dbus_usbos_resume(struct usb_interface *intf)
++{
++	DBUSERR(("%s Device resumed\n", __FUNCTION__));
++
++	dbus_usbos_state_change((usbos_info_t*)g_probe_info.usbos_info, DBUS_STATE_UP);
++	g_probe_info.suspend_state = USBOS_SUSPEND_STATE_DEVICE_ACTIVE;
++	return 0;
++}
++
++/**
++* This function is directly called by the Linux kernel, when the suspended device has been reset
++* instead of being resumed
++*/
++static int dbus_usbos_reset_resume(struct usb_interface *intf)
++{
++	DBUSERR(("%s Device reset resumed\n", __FUNCTION__));
++
++#ifdef KEEPIF_ON_DEVICE_RESET
++	if (g_probe_info.keepif_on_devreset) {
++		atomic_set(&g_probe_info.usbdev_stat, USB_DEVICE_RESETTED);
++		wake_up_interruptible(&g_probe_info.usbreset_queue_head);
++	} else
++#endif /* KEEPIF_ON_DEVICE_RESET */
++	{
++		/* The device may have lost power, so a firmware download may be required */
++		dbus_usbos_state_change((usbos_info_t*)g_probe_info.usbos_info,
++			DBUS_STATE_DL_NEEDED);
++		g_probe_info.suspend_state = USBOS_SUSPEND_STATE_DEVICE_ACTIVE;
++	}
++
++	return 0;
++}
++
++#endif /* USB_SUSPEND_AVAILABLE */
++
++/**
++ * Called by Linux kernel at initialization time, kernel wants to know if our driver will accept the
++ * caller supplied USB interface. Note that USB drivers are bound to interfaces, and not to USB
++ * devices.
++ */
++#ifdef KERNEL26
++static int
++dbus_usbos_probe(struct usb_interface *intf, const struct usb_device_id *id)
++#else
++static void *
++dbus_usbos_probe(struct usb_device *usb, unsigned int ifnum, const struct usb_device_id *id)
++#endif /* KERNEL26 */
++{
++	int ep;
++	struct usb_endpoint_descriptor *endpoint;
++	int ret = 0;
++#ifdef KERNEL26
++	struct usb_device *usb = interface_to_usbdev(intf);
++#else
++	int claimed = 0;
++#endif
++	int num_of_eps;
++#ifdef BCMUSBDEV_COMPOSITE
++	int wlan_if = -1;
++	bool intr_ep = FALSE;
++#endif /* BCMUSBDEV_COMPOSITE */
++
++#ifdef BCMUSBDEV_COMPOSITE
++	wlan_if = dbus_usbos_intf_wlan(usb);
++#ifdef KERNEL26
++	if ((wlan_if >= 0) && (IFPTR(usb, wlan_if) == intf)) {
++#else
++	if (wlan_if == ifnum) {
++#endif /* KERNEL26 */
++#endif /* BCMUSBDEV_COMPOSITE */
++		g_probe_info.usb = usb;
++		g_probe_info.dldone = TRUE;
++#ifdef BCMUSBDEV_COMPOSITE
++	} else {
++		DBUSTRACE(("dbus_usbos_probe: skip probe for non WLAN interface\n"));
++		ret = BCME_UNSUPPORTED;
++		goto fail;
++	}
++#endif /* BCMUSBDEV_COMPOSITE */
++
++#ifdef KERNEL26
++	g_probe_info.intf = intf;
++#endif /* KERNEL26 */
++
++#ifdef BCMUSBDEV_COMPOSITE
++	if (IFDESC(usb, wlan_if).bInterfaceNumber > USB_COMPIF_MAX) {
++#else
++	if (IFDESC(usb, CONTROL_IF).bInterfaceNumber) {
++#endif /* BCMUSBDEV_COMPOSITE */
++		ret = -1;
++		goto fail;
++	}
++	if (id != NULL) {
++		g_probe_info.vid = id->idVendor;
++		g_probe_info.pid = id->idProduct;
++	}
++
++#ifdef KERNEL26
++	usb_set_intfdata(intf, &g_probe_info);
++#endif
++
++	/* Check that the device supports only one configuration */
++	if (usb->descriptor.bNumConfigurations != 1) {
++		ret = -1;
++		goto fail;
++	}
++
++	if (usb->descriptor.bDeviceClass != USB_CLASS_VENDOR_SPEC) {
++#ifdef BCMUSBDEV_COMPOSITE
++		if ((usb->descriptor.bDeviceClass != USB_CLASS_MISC) &&
++			(usb->descriptor.bDeviceClass != USB_CLASS_WIRELESS)) {
++#endif /* BCMUSBDEV_COMPOSITE */
++			ret = -1;
++			goto fail;
++#ifdef BCMUSBDEV_COMPOSITE
++		}
++#endif /* BCMUSBDEV_COMPOSITE */
++	}
++
++	/*
++	 * Only the BDC interface configuration is supported:
++	 *	Device class: USB_CLASS_VENDOR_SPEC
++	 *	if0 class: USB_CLASS_VENDOR_SPEC
++	 *	if0/ep0: control
++	 *	if0/ep1: bulk in
++	 *	if0/ep2: bulk out (ok if swapped with bulk in)
++	 */
++	if (CONFIGDESC(usb)->bNumInterfaces != 1) {
++#ifdef BCMUSBDEV_COMPOSITE
++		if (CONFIGDESC(usb)->bNumInterfaces > USB_COMPIF_MAX) {
++#endif /* BCMUSBDEV_COMPOSITE */
++			ret = -1;
++			goto fail;
++#ifdef BCMUSBDEV_COMPOSITE
++		}
++#endif /* BCMUSBDEV_COMPOSITE */
++	}
++
++	/* Check interface */
++#ifndef KERNEL26
++#ifdef BCMUSBDEV_COMPOSITE
++	if (usb_interface_claimed(IFPTR(usb, wlan_if))) {
++#else
++	if (usb_interface_claimed(IFPTR(usb, CONTROL_IF))) {
++#endif /* BCMUSBDEV_COMPOSITE */
++		ret = -1;
++		goto fail;
++	}
++#endif /* !KERNEL26 */
++
++#ifdef BCMUSBDEV_COMPOSITE
++	if ((IFDESC(usb, wlan_if).bInterfaceClass != USB_CLASS_VENDOR_SPEC ||
++		IFDESC(usb, wlan_if).bInterfaceSubClass != 2 ||
++		IFDESC(usb, wlan_if).bInterfaceProtocol != 0xff) &&
++		(IFDESC(usb, wlan_if).bInterfaceClass != USB_CLASS_MISC ||
++		IFDESC(usb, wlan_if).bInterfaceSubClass != USB_SUBCLASS_COMMON ||
++		IFDESC(usb, wlan_if).bInterfaceProtocol != USB_PROTO_IAD)) {
++			DBUSERR(("%s: invalid control interface: class %d, subclass %d, proto %d\n",
++				__FUNCTION__,
++				IFDESC(usb, wlan_if).bInterfaceClass,
++				IFDESC(usb, wlan_if).bInterfaceSubClass,
++				IFDESC(usb, wlan_if).bInterfaceProtocol));
++#else
++	if (IFDESC(usb, CONTROL_IF).bInterfaceClass != USB_CLASS_VENDOR_SPEC ||
++		IFDESC(usb, CONTROL_IF).bInterfaceSubClass != 2 ||
++		IFDESC(usb, CONTROL_IF).bInterfaceProtocol != 0xff) {
++			DBUSERR(("%s: invalid control interface: class %d, subclass %d, proto %d\n",
++				__FUNCTION__,
++				IFDESC(usb, CONTROL_IF).bInterfaceClass,
++				IFDESC(usb, CONTROL_IF).bInterfaceSubClass,
++				IFDESC(usb, CONTROL_IF).bInterfaceProtocol));
++#endif /* BCMUSBDEV_COMPOSITE */
++			ret = -1;
++			goto fail;
++	}
++
++	/* Check control endpoint */
++#ifdef BCMUSBDEV_COMPOSITE
++	endpoint = &IFEPDESC(usb, wlan_if, 0);
++#else
++	endpoint = &IFEPDESC(usb, CONTROL_IF, 0);
++#endif /* BCMUSBDEV_COMPOSITE */
++	if ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) != USB_ENDPOINT_XFER_INT) {
++#ifdef BCMUSBDEV_COMPOSITE
++		if ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) !=
++			USB_ENDPOINT_XFER_BULK) {
++#endif /* BCMUSBDEV_COMPOSITE */
++			DBUSERR(("%s: invalid control endpoint %d\n",
++				__FUNCTION__, endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK));
++			ret = -1;
++			goto fail;
++#ifdef BCMUSBDEV_COMPOSITE
++		}
++#endif /* BCMUSBDEV_COMPOSITE */
++	}
++
++#ifdef BCMUSBDEV_COMPOSITE
++	if ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
++#endif /* BCMUSBDEV_COMPOSITE */
++		g_probe_info.intr_pipe =
++			usb_rcvintpipe(usb, endpoint->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK);
++#ifdef BCMUSBDEV_COMPOSITE
++		intr_ep = TRUE;
++	}
++#endif /* BCMUSBDEV_COMPOSITE */
++
++#ifndef KERNEL26
++	/* Claim interface */
++#ifdef BCMUSBDEV_COMPOSITE
++	usb_driver_claim_interface(&dbus_usbdev, IFPTR(usb, wlan_if), &g_probe_info);
++#else
++	usb_driver_claim_interface(&dbus_usbdev, IFPTR(usb, CONTROL_IF), &g_probe_info);
++#endif /* BCMUSBDEV_COMPOSITE */
++	claimed = 1;
++#endif /* !KERNEL26 */
++	g_probe_info.rx_pipe = 0;
++	g_probe_info.rx_pipe2 = 0;
++	g_probe_info.tx_pipe = 0;
++#ifdef BCMUSBDEV_COMPOSITE
++	if (intr_ep)
++		ep = 1;
++	else
++		ep = 0;
++	num_of_eps = IFDESC(usb, wlan_if).bNumEndpoints - 1;
++#else
++	num_of_eps = IFDESC(usb, BULK_IF).bNumEndpoints - 1;
++#endif /* BCMUSBDEV_COMPOSITE */
++
++	if ((num_of_eps != 2) && (num_of_eps != 3)) {
++#ifdef BCMUSBDEV_COMPOSITE
++		if (num_of_eps > 7)
++#endif /* BCMUSBDEV_COMPOSITE */
++			ASSERT(0);
++	}
++	/* Check data endpoints and get pipes */
++#ifdef BCMUSBDEV_COMPOSITE
++	for (; ep <= num_of_eps; ep++) {
++		endpoint = &IFEPDESC(usb, wlan_if, ep);
++#else
++	for (ep = 1; ep <= num_of_eps; ep++) {
++		endpoint = &IFEPDESC(usb, BULK_IF, ep);
++#endif /* BCMUSBDEV_COMPOSITE */
++		if ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) !=
++		    USB_ENDPOINT_XFER_BULK) {
++			DBUSERR(("%s: invalid data endpoint %d\n",
++			           __FUNCTION__, ep));
++			ret = -1;
++			goto fail;
++		}
++
++		if ((endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
++			/* direction: dongle->host */
++			if (!g_probe_info.rx_pipe) {
++				g_probe_info.rx_pipe = usb_rcvbulkpipe(usb,
++					(endpoint->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK));
++			} else {
++				g_probe_info.rx_pipe2 = usb_rcvbulkpipe(usb,
++					(endpoint->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK));
++			}
++
++		} else
++			g_probe_info.tx_pipe = usb_sndbulkpipe(usb, (endpoint->bEndpointAddress &
++			     USB_ENDPOINT_NUMBER_MASK));
++	}
++
++	/* Allocate interrupt URB and data buffer */
++	/* RNDIS says 8-byte intr, our old drivers used 4-byte */
++#ifdef BCMUSBDEV_COMPOSITE
++	g_probe_info.intr_size = (IFEPDESC(usb, wlan_if, 0).wMaxPacketSize == 16) ? 8 : 4;
++	g_probe_info.interval = IFEPDESC(usb, wlan_if, 0).bInterval;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21))
++	usb->quirks |= USB_QUIRK_NO_SET_INTF;
++#endif
++#else
++	g_probe_info.intr_size = (IFEPDESC(usb, CONTROL_IF, 0).wMaxPacketSize == 16) ? 8 : 4;
++	g_probe_info.interval = IFEPDESC(usb, CONTROL_IF, 0).bInterval;
++#endif /* BCMUSBDEV_COMPOSITE */
++
++#ifndef KERNEL26
++	/* usb_fill_int_urb does the interval decoding in 2.6 */
++	if (usb->speed == USB_SPEED_HIGH)
++		g_probe_info.interval = 1 << (g_probe_info.interval - 1);
++#endif
++	if (usb->speed == USB_SPEED_SUPER) {
++		g_probe_info.device_speed = SUPER_SPEED;
++		DBUSERR(("super speed device detected\n"));
++	} else if (usb->speed == USB_SPEED_HIGH) {
++		g_probe_info.device_speed = HIGH_SPEED;
++		DBUSERR(("high speed device detected\n"));
++	} else {
++		g_probe_info.device_speed = FULL_SPEED;
++		DBUSERR(("full speed device detected\n"));
++	}
++#ifdef KEEPIF_ON_DEVICE_RESET
++	if (g_probe_info.keepif_on_devreset && g_probe_info.dev_resetted) {
++		atomic_set(&g_probe_info.usbdev_stat, USB_DEVICE_PROBED);
++		wake_up_interruptible(&g_probe_info.usbreset_queue_head);
++	} else
++#endif /* KEEPIF_ON_DEVICE_RESET */
++	if (g_probe_info.dereged == FALSE && probe_cb) {
++		disc_arg = probe_cb(probe_arg, "", USB_BUS, 0);
++	}
++
++	g_probe_info.disc_cb_done = FALSE;
++
++#ifdef KERNEL26
++	intf->needs_remote_wakeup = 1;
++#endif /* KERNEL26 */
++
++	/* Success */
++#ifdef KERNEL26
++	return DBUS_OK;
++#else
++	usb_inc_dev_use(usb);
++	return &g_probe_info;
++#endif
++
++fail:
++#ifdef BCMUSBDEV_COMPOSITE
++	if (ret != BCME_UNSUPPORTED)
++#endif /* BCMUSBDEV_COMPOSITE */
++		DBUSERR(("%s: failed with errno %d\n", __FUNCTION__, ret));
++#ifndef KERNEL26
++	if (claimed)
++#ifdef BCMUSBDEV_COMPOSITE
++		usb_driver_release_interface(&dbus_usbdev, IFPTR(usb, wlan_if));
++#else
++		usb_driver_release_interface(&dbus_usbdev, IFPTR(usb, CONTROL_IF));
++#endif /* BCMUSBDEV_COMPOSITE */
++#endif /* !KERNEL26 */
++
++#ifdef KERNEL26
++	usb_set_intfdata(intf, NULL);
++	return ret;
++#else
++	return NULL;
++#endif
++} /* dbus_usbos_probe */
++
++/** Called by Linux kernel, is the counter part of dbus_usbos_probe() */
++#ifdef KERNEL26
++static void
++dbus_usbos_disconnect(struct usb_interface *intf)
++#else
++static void
++dbus_usbos_disconnect(struct usb_device *usb, void *ptr)
++#endif
++{
++#ifdef KERNEL26
++	struct usb_device *usb = interface_to_usbdev(intf);
++	probe_info_t *probe_usb_init_data = usb_get_intfdata(intf);
++#else
++	probe_info_t *probe_usb_init_data = (probe_info_t *) ptr;
++#endif
++	usbos_info_t *usbos_info;
++
++	if (probe_usb_init_data) {
++		usbos_info = (usbos_info_t *) probe_usb_init_data->usbos_info;
++		if (usbos_info) {
++			if ((probe_usb_init_data->dereged == FALSE) && disconnect_cb && disc_arg) {
++				bool remove_if = TRUE;
++#ifdef KEEPIF_ON_DEVICE_RESET
++				if (g_probe_info.keepif_on_devreset)
++					remove_if = FALSE;
++#endif /* KEEPIF_ON_DEVICE_RESET */
++				if (remove_if) {
++					disconnect_cb(disc_arg);
++					disc_arg = NULL;
++					probe_usb_init_data->disc_cb_done = TRUE;
++				}
++			}
++		}
++	}
++
++	if (usb) {
++#ifndef KERNEL26
++#ifdef BCMUSBDEV_COMPOSITE
++		usb_driver_release_interface(&dbus_usbdev, IFPTR(usb, wlan_if));
++#else
++		usb_driver_release_interface(&dbus_usbdev, IFPTR(usb, CONTROL_IF));
++#endif /* BCMUSBDEV_COMPOSITE */
++		usb_dec_dev_use(usb);
++#endif /* !KERNEL26 */
++	}
++
++#ifdef KEEPIF_ON_DEVICE_RESET
++	if (g_probe_info.keepif_on_devreset && (!g_probe_info.dev_resetted)) {
++		atomic_set(&g_probe_info.usbdev_stat, USB_DEVICE_DISCONNECTED);
++		wake_up_interruptible(&g_probe_info.usbreset_queue_head);
++	}
++#endif /* KEEPIF_ON_DEVICE_RESET */
++} /* dbus_usbos_disconnect */
++
++#define LOOPBACK_PKT_START 0xBABE1234
++
++bool is_loopback_pkt(void *buf)
++{
++
++	uint32 *buf_ptr = (uint32 *) buf;
++
++	if (*buf_ptr == LOOPBACK_PKT_START)
++		return TRUE;
++	return FALSE;
++
++}
++
++int matches_loopback_pkt(void *buf)
++{
++	int i, j;
++	unsigned char *cbuf = (unsigned char *) buf;
++
++	for (i = 4; i < loopback_size; i++) {
++		if (cbuf[i] != (i % 256)) {
++			printf("%s: mismatch at i=%d %d : ", __FUNCTION__, i, cbuf[i]);
++			for (j = i; ((j < i+ 16) && (j < loopback_size)); j++) {
++				printf("%d ", cbuf[j]);
++			}
++			printf("\n");
++			return 0;
++		}
++	}
++	loopback_rx_cnt++;
++	return 1;
++}
++
++int dbus_usbos_loopback_tx(void *usbos_info_ptr, int cnt, int size)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) usbos_info_ptr;
++	unsigned char *buf;
++	int j;
++	void* p = NULL;
++	int rc, last_rx_cnt;
++	int tx_failed_cnt;
++	int max_size = 1650;
++	int usb_packet_size = 512;
++	int min_packet_size = 10;
++
++	if (size % usb_packet_size == 0) {
++		size = size - 1;
++		DBUSERR(("%s: overriding size=%d \n", __FUNCTION__, size));
++	}
++
++	if (size < min_packet_size) {
++		size = min_packet_size;
++		DBUSERR(("%s: overriding size=%d\n", __FUNCTION__, min_packet_size));
++	}
++	if (size > max_size) {
++		size = max_size;
++		DBUSERR(("%s: overriding size=%d\n", __FUNCTION__, max_size));
++	}
++
++	loopback_tx_cnt = 0;
++	loopback_rx_cnt = 0;
++	tx_failed_cnt = 0;
++	loopback_size   = size;
++
++	while (loopback_tx_cnt < cnt) {
++		uint32 *x;
++		int pkt_size = loopback_size;
++
++		p = PKTGET(usbos_info->pub->osh, pkt_size, TRUE);
++		if (p == NULL) {
++			DBUSERR(("%s:%d Failed to allocate packet sz=%d\n",
++			       __FUNCTION__, __LINE__, pkt_size));
++			return BCME_ERROR;
++		}
++		x = (uint32*) PKTDATA(usbos_info->pub->osh, p);
++		*x = LOOPBACK_PKT_START;
++		buf = (unsigned char*) x;
++		for (j = 4; j < pkt_size; j++) {
++			buf[j] = j % 256;
++		}
++		rc = dbus_send_buf(usbos_info->pub, buf, pkt_size, p);
++		if (rc != BCME_OK) {
++			DBUSERR(("%s:%d Freeing packet \n", __FUNCTION__, __LINE__));
++			PKTFREE(usbos_info->pub->osh, p, TRUE);
++			dbus_usbos_wait(usbos_info, 1);
++			tx_failed_cnt++;
++		} else {
++			loopback_tx_cnt++;
++			tx_failed_cnt = 0;
++		}
++		if (tx_failed_cnt == 5) {
++			DBUSERR(("%s : Failed to send loopback packets cnt=%d loopback_tx_cnt=%d\n",
++			 __FUNCTION__, cnt, loopback_tx_cnt));
++			break;
++		}
++	}
++	printf("Transmitted %d loopback packets of size %d\n", loopback_tx_cnt, loopback_size);
++
++	last_rx_cnt = loopback_rx_cnt;
++	while (loopback_rx_cnt < loopback_tx_cnt) {
++		dbus_usbos_wait(usbos_info, 1);
++		if (loopback_rx_cnt <= last_rx_cnt) {
++			DBUSERR(("%s: Matched rx cnt stuck at %d \n", __FUNCTION__, last_rx_cnt));
++			return BCME_ERROR;
++		}
++		last_rx_cnt = loopback_rx_cnt;
++	}
++	printf("Received %d loopback packets of size %d\n", loopback_tx_cnt, loopback_size);
++
++	return BCME_OK;
++} /* dbus_usbos_loopback_tx */
++
++/**
++ * Higher layer (dbus_usb.c) wants to transmit an I/O Request Block
++ *     @param[in] txirb txirb->pkt, if non-zero, contains a single or a chain of packets
++ */
++static int
++dbus_usbos_intf_send_irb(void *bus, dbus_irb_tx_t *txirb)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++	urb_req_t *req, *req_zlp = NULL;
++	int ret = DBUS_OK;
++	unsigned long flags;
++	void *pkt;
++	uint32 buffer_length;
++	uint8 *buf;
++
++	if ((usbos_info == NULL) || !usbos_info->tx_pipe) {
++		return DBUS_ERR;
++	}
++
++	if (txirb->pkt != NULL) {
++		buffer_length = pkttotlen(usbos_info->pub->osh, txirb->pkt);
++		/* In case of multiple packets the values below may be overwritten */
++		txirb->send_buf = NULL;
++		buf = PKTDATA(usbos_info->pub->osh, txirb->pkt);
++	} else { /* txirb->buf != NULL */
++		ASSERT(txirb->buf != NULL);
++		ASSERT(txirb->send_buf == NULL);
++		buffer_length = txirb->len;
++		buf = txirb->buf;
++	}
++
++	if (!(req = dbus_usbos_qdeq(&usbos_info->req_txfreeq, &usbos_info->txfree_lock))) {
++		DBUSERR(("%s No free URB!\n", __FUNCTION__));
++		return DBUS_ERR_TXDROP;
++	}
++
++	/* If not using standard Linux kernel functionality for handling Zero Length Packet(ZLP),
++	 * the dbus needs to generate ZLP when length is multiple of MaxPacketSize.
++	 */
++#ifndef WL_URB_ZPKT
++	if (!(buffer_length % usbos_info->maxps)) {
++		if (!(req_zlp =
++			dbus_usbos_qdeq(&usbos_info->req_txfreeq, &usbos_info->txfree_lock))) {
++			DBUSERR(("%s No free URB for ZLP!\n", __FUNCTION__));
++			dbus_usbos_qenq(&usbos_info->req_txfreeq, req, &usbos_info->txfree_lock);
++			return DBUS_ERR_TXDROP;
++		}
++
++		/* No txirb, so that dbus_usbos_send_complete can differentiate between
++		 * DATA and ZLP.
++		 */
++		req_zlp->arg = NULL;
++		req_zlp->usbinfo = usbos_info;
++		req_zlp->buf_len = 0;
++
++		usb_fill_bulk_urb(req_zlp->urb, usbos_info->usb, usbos_info->tx_pipe, NULL,
++			0, (usb_complete_t)dbus_usbos_send_complete, req_zlp);
++
++		req_zlp->urb->transfer_flags |= URB_QUEUE_BULK;
++	}
++#endif /* !WL_URB_ZPKT */
++
++#ifndef USBOS_TX_THREAD
++	/* Disable USB autosuspend until this request completes, request USB resume if needed.
++	 * Because this call runs asynchronously, there is no guarantee the bus is resumed before
++	 * the URB is submitted, and the URB might be dropped. Use USBOS_TX_THREAD to avoid
++	 * this.
++	 */
++	USB_AUTOPM_GET_INTERFACE_ASYNC(g_probe_info.intf);
++#endif /* !USBOS_TX_THREAD */
++
++	spin_lock_irqsave(&usbos_info->txlock, flags);
++
++	req->arg = txirb;
++	req->usbinfo = usbos_info;
++	req->buf_len = 0;
++
++	/* Prepare the URB */
++	if (txirb->pkt != NULL) {
++		uint32 pktlen;
++		uint8 *transfer_buf;
++
++		/* For multiple packets, allocate contiguous buffer and copy packet data to it */
++		if (PKTNEXT(usbos_info->pub->osh, txirb->pkt)) {
++			transfer_buf = MALLOC(usbos_info->pub->osh, buffer_length);
++			if (!transfer_buf) {
++				ret = DBUS_ERR_TXDROP;
++				DBUSERR(("fail to alloc to usb buffer\n"));
++				goto fail;
++			}
++
++			pkt = txirb->pkt;
++			txirb->send_buf = transfer_buf;
++			req->buf_len = buffer_length;
++
++			while (pkt) {
++				pktlen = PKTLEN(usbos_info->pub->osh, pkt);
++				bcopy(PKTDATA(usbos_info->pub->osh, pkt), transfer_buf, pktlen);
++				transfer_buf += pktlen;
++				pkt = PKTNEXT(usbos_info->pub->osh, pkt);
++			}
++
++			ASSERT(((uint8 *) txirb->send_buf + buffer_length) == transfer_buf);
++
++			/* Overwrite buf pointer with pointer to allocated contiguous transfer_buf
++			 */
++			buf = txirb->send_buf;
++		}
++	}
++
++	usb_fill_bulk_urb(req->urb, usbos_info->usb, usbos_info->tx_pipe, buf,
++		buffer_length, (usb_complete_t)dbus_usbos_send_complete, req);
++
++	req->urb->transfer_flags |= URB_QUEUE_BULK;
++
++#ifdef USBOS_TX_THREAD
++	/* Enqueue TX request, the TX thread will resume the bus if needed and submit
++	 * it asynchronously
++	 */
++	dbus_usbos_qenq(&usbos_info->usbos_tx_list, req, &usbos_info->usbos_tx_list_lock);
++	if (req_zlp != NULL) {
++		dbus_usbos_qenq(&usbos_info->usbos_tx_list, req_zlp,
++			&usbos_info->usbos_tx_list_lock);
++	}
++	spin_unlock_irqrestore(&usbos_info->txlock, flags);
++
++	wake_up_interruptible(&usbos_info->usbos_tx_queue_head);
++	return DBUS_OK;
++#else
++	if ((ret = USB_SUBMIT_URB(req->urb))) {
++		ret = DBUS_ERR_TXDROP;
++		goto fail;
++	}
++
++	dbus_usbos_qenq(&usbos_info->req_txpostedq, req, &usbos_info->txposted_lock);
++	atomic_inc(&usbos_info->txposted);
++
++	if (req_zlp != NULL) {
++		if ((ret = USB_SUBMIT_URB(req_zlp->urb))) {
++			DBUSERR(("failed to submit ZLP URB!\n"));
++			ASSERT(0);
++			ret = DBUS_ERR_TXDROP;
++			goto fail2;
++		}
++
++		dbus_usbos_qenq(&usbos_info->req_txpostedq, req_zlp, &usbos_info->txposted_lock);
++		/* Also increment txposted for zlp packet, as it will be decremented in
++		 * dbus_usbos_send_complete()
++		 */
++		atomic_inc(&usbos_info->txposted);
++	}
++
++	spin_unlock_irqrestore(&usbos_info->txlock, flags);
++	return DBUS_OK;
++#endif /* USBOS_TX_THREAD */
++
++fail:
++	if (txirb->send_buf != NULL) {
++		MFREE(usbos_info->pub->osh, txirb->send_buf, req->buf_len);
++		txirb->send_buf = NULL;
++		req->buf_len = 0;
++	}
++	dbus_usbos_qenq(&usbos_info->req_txfreeq, req, &usbos_info->txfree_lock);
++#ifndef USBOS_TX_THREAD
++fail2:
++#endif
++	if (req_zlp != NULL) {
++		dbus_usbos_qenq(&usbos_info->req_txfreeq, req_zlp, &usbos_info->txfree_lock);
++	}
++
++	spin_unlock_irqrestore(&usbos_info->txlock, flags);
++
++#ifndef USBOS_TX_THREAD
++	USB_AUTOPM_PUT_INTERFACE_ASYNC(g_probe_info.intf);
++#endif /* !USBOS_TX_THREAD */
++
++	return ret;
++} /* dbus_usbos_intf_send_irb */
++
++/** Higher layer (dbus_usb.c) recycles a received (and used) packet. */
++static int
++dbus_usbos_intf_recv_irb(void *bus, dbus_irb_rx_t *rxirb)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++	int ret = DBUS_OK;
++
++	if (usbos_info == NULL)
++		return DBUS_ERR;
++
++	ret = dbus_usbos_recv_urb_submit(usbos_info, rxirb, 0);
++	return ret;
++}
++
++static int
++dbus_usbos_intf_recv_irb_from_ep(void *bus, dbus_irb_rx_t *rxirb, uint32 ep_idx)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++	int ret = DBUS_OK;
++
++	if (usbos_info == NULL)
++		return DBUS_ERR;
++
++#ifdef INTR_EP_ENABLE
++		/* By specifying the ep_idx value of 0xff, the cdc layer is asking to
++		* submit an interrupt URB
++		*/
++		if (rxirb == NULL && ep_idx == 0xff) {
++			/* submit intr URB */
++			if ((ret = USB_SUBMIT_URB(usbos_info->intr_urb)) < 0) {
++				DBUSERR(("%s intr USB_SUBMIT_URB failed, status %d\n",
++					__FUNCTION__, ret));
++			}
++			return ret;
++		}
++#else
++		if (rxirb == NULL) {
++			return DBUS_ERR;
++		}
++#endif /* INTR_EP_ENABLE */
++
++	ret = dbus_usbos_recv_urb_submit(usbos_info, rxirb, ep_idx);
++	return ret;
++}
++
++/** Higher layer (dbus_usb.c) want to cancel an IRB */
++static int
++dbus_usbos_intf_cancel_irb(void *bus, dbus_irb_tx_t *txirb)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++
++	if (usbos_info == NULL)
++		return DBUS_ERR;
++
++	return DBUS_ERR;
++}
++
++/** Only one CTL transfer can be pending at any time. This function may block. */
++static int
++dbus_usbos_intf_send_ctl(void *bus, uint8 *buf, int len)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++	uint16 size;
++#ifndef USBOS_TX_THREAD
++	int status;
++#endif /* USBOS_TX_THREAD */
++
++	if ((usbos_info == NULL) || (buf == NULL) || (len == 0))
++		return DBUS_ERR;
++
++	if (usbos_info->ctl_urb == NULL)
++		return DBUS_ERR;
++
++	/* Block until a pending CTL transfer has completed */
++	if (down_interruptible(&usbos_info->ctl_lock) != 0) {
++		return DBUS_ERR_TXCTLFAIL;
++	}
++
++#ifdef USBOS_TX_THREAD
++	ASSERT(usbos_info->ctl_state == USBOS_REQUEST_STATE_UNSCHEDULED);
++#else
++	/* Disable USB autosuspend until this request completes, request USB resume if needed.
++	 * Because this call runs asynchronously, there is no guarantee the bus is resumed before
++	 * the URB is submitted, and the URB might be dropped. Use USBOS_TX_THREAD to avoid
++	 * this.
++	 */
++	USB_AUTOPM_GET_INTERFACE_ASYNC(g_probe_info.intf);
++#endif /* USBOS_TX_THREAD */
++
++	size = len;
++	usbos_info->ctl_write.wLength = cpu_to_le16p(&size);
++	usbos_info->ctl_urb->transfer_buffer_length = size;
++
++	usb_fill_control_urb(usbos_info->ctl_urb,
++		usbos_info->usb,
++		usb_sndctrlpipe(usbos_info->usb, 0),
++		(unsigned char *) &usbos_info->ctl_write,
++		buf, size, (usb_complete_t)dbus_usbos_ctlwrite_complete, usbos_info);
++
++#ifdef USBOS_TX_THREAD
++	/* Enqueue CTRL request for transmission by the TX thread. The
++	 * USB bus will first be resumed if needed.
++	 */
++	usbos_info->ctl_state = USBOS_REQUEST_STATE_SCHEDULED;
++	wake_up_interruptible(&usbos_info->usbos_tx_queue_head);
++#else
++	status = USB_SUBMIT_URB(usbos_info->ctl_urb);
++	if (status < 0) {
++		DBUSERR(("%s: usb_submit_urb failed %d\n", __FUNCTION__, status));
++		up(&usbos_info->ctl_lock);
++
++		USB_AUTOPM_PUT_INTERFACE_ASYNC(g_probe_info.intf);
++
++		return DBUS_ERR_TXCTLFAIL;
++	}
++#endif /* USBOS_TX_THREAD */
++
++	return DBUS_OK;
++} /* dbus_usbos_intf_send_ctl */
++
++/** This function does not seem to be called by anyone, including dbus_usb.c */
++static int
++dbus_usbos_intf_recv_ctl(void *bus, uint8 *buf, int len)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++	int status;
++	uint16 size;
++
++	if ((usbos_info == NULL) || (buf == NULL) || (len == 0))
++		return DBUS_ERR;
++
++	if (usbos_info->ctl_urb == NULL)
++		return DBUS_ERR;
++
++	/* Block until a pending CTRL transfer has completed */
++	if (down_interruptible(&usbos_info->ctl_lock) != 0) {
++		return DBUS_ERR_TXCTLFAIL;
++	}
++
++	/* Disable USB autosuspend until this request completes, request USB resume if needed. */
++	USB_AUTOPM_GET_INTERFACE_ASYNC(g_probe_info.intf);
++
++	size = len;
++	usbos_info->ctl_read.wLength = cpu_to_le16p(&size);
++	usbos_info->ctl_urb->transfer_buffer_length = size;
++
++	if (usbos_info->rxctl_deferrespok) {
++		/* BMAC model */
++		usbos_info->ctl_read.bRequestType = USB_DIR_IN | USB_TYPE_VENDOR |
++			USB_RECIP_INTERFACE;
++		usbos_info->ctl_read.bRequest = DL_DEFER_RESP_OK;
++	} else {
++		/* full dongle model */
++		usbos_info->ctl_read.bRequestType = USB_DIR_IN | USB_TYPE_CLASS |
++			USB_RECIP_INTERFACE;
++		usbos_info->ctl_read.bRequest = 1;
++	}
++
++	usb_fill_control_urb(usbos_info->ctl_urb,
++		usbos_info->usb,
++		usb_rcvctrlpipe(usbos_info->usb, 0),
++		(unsigned char *) &usbos_info->ctl_read,
++		buf, size, (usb_complete_t)dbus_usbos_ctlread_complete, usbos_info);
++
++	status = USB_SUBMIT_URB(usbos_info->ctl_urb);
++	if (status < 0) {
++		DBUSERR(("%s: usb_submit_urb failed %d\n", __FUNCTION__, status));
++		up(&usbos_info->ctl_lock);
++
++		USB_AUTOPM_PUT_INTERFACE_ASYNC(g_probe_info.intf);
++
++		return DBUS_ERR_RXCTLFAIL;
++	}
++
++	return DBUS_OK;
++}
++
++static int
++dbus_usbos_intf_get_attrib(void *bus, dbus_attrib_t *attrib)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++
++	if ((usbos_info == NULL) || (attrib == NULL))
++		return DBUS_ERR;
++
++	attrib->bustype = DBUS_USB;
++	attrib->vid = g_probe_info.vid;
++	attrib->pid = g_probe_info.pid;
++
++	attrib->devid = g_probe_info.pid;
++
++	attrib->nchan = 1;
++
++	/* MaxPacketSize for USB hi-speed bulk out is 512 bytes
++	 * and 64-bytes for full-speed.
++	 * When sending pkt > MaxPacketSize, Host SW breaks it
++	 * up into multiple packets.
++	 */
++	attrib->mtu = usbos_info->maxps;
++
++	return DBUS_OK;
++}
++
++/** Called by higher layer (dbus_usb.c) when it wants to 'up' the USB interface to the dongle */
++static int
++dbus_usbos_intf_up(void *bus)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++	uint16 ifnum;
++#ifdef BCMUSBDEV_COMPOSITE
++	int wlan_if = 0;
++#endif
++	if (usbos_info == NULL)
++		return DBUS_ERR;
++
++	if (usbos_info->usb == NULL)
++		return DBUS_ERR;
++
++#if defined(INTR_EP_ENABLE)
++	/* full dongle use intr EP, bmac doesn't use it */
++	if (usbos_info->intr_urb) {
++		int ret;
++
++		usb_fill_int_urb(usbos_info->intr_urb, usbos_info->usb,
++			usbos_info->intr_pipe, &usbos_info->intr,
++			usbos_info->intr_size, (usb_complete_t)dbus_usbos_intr_complete,
++			usbos_info, usbos_info->interval);
++
++		if ((ret = USB_SUBMIT_URB(usbos_info->intr_urb))) {
++			DBUSERR(("%s USB_SUBMIT_URB failed with status %d\n", __FUNCTION__, ret));
++			return DBUS_ERR;
++		}
++	}
++#endif	
++
++	if (usbos_info->ctl_urb) {
++		usbos_info->ctl_in_pipe = usb_rcvctrlpipe(usbos_info->usb, 0);
++		usbos_info->ctl_out_pipe = usb_sndctrlpipe(usbos_info->usb, 0);
++
++#ifdef BCMUSBDEV_COMPOSITE
++		wlan_if = dbus_usbos_intf_wlan(usbos_info->usb);
++		ifnum = cpu_to_le16(IFDESC(usbos_info->usb, wlan_if).bInterfaceNumber);
++#else
++		ifnum = cpu_to_le16(IFDESC(usbos_info->usb, CONTROL_IF).bInterfaceNumber);
++#endif /* BCMUSBDEV_COMPOSITE */
++		/* CTL Write */
++		usbos_info->ctl_write.bRequestType =
++			USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE;
++		usbos_info->ctl_write.bRequest = 0;
++		usbos_info->ctl_write.wValue = cpu_to_le16(0);
++		usbos_info->ctl_write.wIndex = cpu_to_le16p(&ifnum);
++
++		/* CTL Read */
++		usbos_info->ctl_read.bRequestType =
++			USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE;
++		usbos_info->ctl_read.bRequest = 1;
++		usbos_info->ctl_read.wValue = cpu_to_le16(0);
++		usbos_info->ctl_read.wIndex = cpu_to_le16p(&ifnum);
++	}
++
++	/* Success, indicate usbos_info is fully up */
++	dbus_usbos_state_change(usbos_info, DBUS_STATE_UP);
++
++	return DBUS_OK;
++} /* dbus_usbos_intf_up */
++
++static int
++dbus_usbos_intf_down(void *bus)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++
++	if (usbos_info == NULL)
++		return DBUS_ERR;
++
++	dbusos_stop(usbos_info);
++	return DBUS_OK;
++}
++
++static int
++dbus_usbos_intf_stop(void *bus)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++
++	if (usbos_info == NULL)
++		return DBUS_ERR;
++
++	dbusos_stop(usbos_info);
++	return DBUS_OK;
++}
++
++#if defined(DBUS_LINUX_HIST)
++static void
++dbus_usbos_intf_dump(void *bus, struct bcmstrbuf *b)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++	int i = 0, j = 0, rxposted, txposted;
++
++	rxposted = atomic_read(&usbos_info->rxposted);
++	txposted = atomic_read(&usbos_info->txposted);
++	if (b) {
++		bcm_bprintf(b, "\ndbus linux dump\n");
++		bcm_bprintf(b, "txposted %d rxposted %d\n",
++			txposted, rxposted);
++
++		bcm_bprintf(b, "RXDPC: dpc_cnt %d dpc_pktcnt %d dpc_maxpktcnt %d avg_dpc_pktcnt\n",
++			usbos_info->dpc_cnt, usbos_info->dpc_pktcnt,
++			usbos_info->dpc_maxpktcnt, usbos_info->dpc_cnt ?
++			(usbos_info->dpc_pktcnt/usbos_info->dpc_cnt):1);
++
++		/* Histogram */
++		bcm_bprintf(b, "txposted\n");
++	} else {
++		printf("\ndbus linux dump\n");
++		printf("txposted %d rxposted %d\n",
++			txposted, rxposted);
++		printf("RXDPC: dpc_cnt %d dpc_pktcnt %d dpc_maxpktcnt %d avg_dpc_pktcnt %d\n",
++			usbos_info->dpc_cnt, usbos_info->dpc_pktcnt,
++			usbos_info->dpc_maxpktcnt, usbos_info->dpc_cnt ?
++			(usbos_info->dpc_pktcnt/usbos_info->dpc_cnt):1);
++
++		/* Histogram */
++		printf("txposted\n");
++	}
++
++	for (i = 0; i < usbos_info->pub->ntxq; i++) {
++		if (usbos_info->txposted_hist == NULL) {
++			break;
++		}
++		if (usbos_info->txposted_hist[i]) {
++			if (b)
++				bcm_bprintf(b, "%d: %d ", i, usbos_info->txposted_hist[i]);
++			else
++				printf("%d: %d ", i, usbos_info->txposted_hist[i]);
++			j++;
++			if (j % 10 == 0) {
++				if (b)
++					bcm_bprintf(b, "\n");
++				else
++					printf("\n");
++			}
++		}
++	}
++
++	j = 0;
++	if (b)
++		bcm_bprintf(b, "\nrxposted\n");
++	else
++		printf("\nrxposted\n");
++	for (i = 0; i < usbos_info->pub->nrxq; i++) {
++		if (usbos_info->rxposted_hist == NULL) {
++			break;
++		}
++		if (usbos_info->rxposted_hist[i]) {
++			if (b)
++				bcm_bprintf(b, "%d: %d ", i, usbos_info->rxposted_hist[i]);
++			else
++				printf("%d: %d ", i, usbos_info->rxposted_hist[i]);
++			j++;
++			if (j % 10 == 0) {
++				if (b)
++					bcm_bprintf(b, "\n");
++				else
++					printf("\n");
++			}
++		}
++	}
++	if (b)
++		bcm_bprintf(b, "\n");
++	else
++		printf("\n");
++
++	return;
++}
++#endif 
++
++/** Called by higher layer (dbus_usb.c) */
++static int
++dbus_usbos_intf_set_config(void *bus, dbus_config_t *config)
++{
++	int err = DBUS_ERR;
++	usbos_info_t* usbos_info = bus;
++
++	if (config->config_id == DBUS_CONFIG_ID_RXCTL_DEFERRES) {
++		usbos_info->rxctl_deferrespok = config->rxctl_deferrespok;
++		err = DBUS_OK;
++	}
++#ifdef KEEPIF_ON_DEVICE_RESET
++	else if (config->config_id == DBUS_CONFIG_ID_KEEPIF_ON_DEVRESET) {
++		g_probe_info.keepif_on_devreset = config->general_param ? TRUE : FALSE;
++		err = DBUS_OK;
++	}
++#endif /* KEEPIF_ON_DEVICE_RESET */
++	else if (config->config_id == DBUS_CONFIG_ID_AGGR_LIMIT) {
++#ifndef BCM_FD_AGGR
++		/* DBUS_CONFIG_ID_AGGR_LIMIT shouldn't be called after probe stage */
++		ASSERT(disc_arg == NULL);
++#endif /* BCM_FD_AGGR */
++		ASSERT(config->aggr_param.maxrxsf > 0);
++		ASSERT(config->aggr_param.maxrxsize > 0);
++		if (config->aggr_param.maxrxsize > usbos_info->rxbuf_len) {
++			int state = usbos_info->pub->busstate;
++			dbus_usbos_unlink(&usbos_info->req_rxpostedq, &usbos_info->rxposted_lock);
++			while (atomic_read(&usbos_info->rxposted)) {
++				DBUSTRACE(("%s rxposted is %d, delay 1 ms\n", __FUNCTION__,
++					atomic_read(&usbos_info->rxposted)));
++				dbus_usbos_wait(usbos_info, 1);
++			}
++			usbos_info->rxbuf_len = config->aggr_param.maxrxsize;
++			dbus_usbos_state_change(usbos_info, state);
++		}
++		err = DBUS_OK;
++	}
++
++	return err;
++}
++
++#ifdef EHCI_FASTPATH_TX
++
++/**
++ * In some cases, the code must submit an URB and wait for its completion.
++ * Related: dbus_usbos_sync_complete()
++ */
++static int
++dbus_usbos_sync_wait(usbos_info_t *usbinfo, uint16 time)
++{
++	int ret;
++	int err = DBUS_OK;
++	int ms = time;
++
++	ret = wait_event_interruptible_timeout(usbinfo->wait,
++		usbinfo->waitdone == TRUE, (ms * HZ / 1000));
++
++	if ((usbinfo->waitdone == FALSE) || (usbinfo->sync_urb_status)) {
++		DBUSERR(("%s: timeout(%d) or urb err=0x%x\n",
++			__FUNCTION__, ret, usbinfo->sync_urb_status));
++		err = DBUS_ERR;
++		BCM_REFERENCE(ret);
++	}
++	usbinfo->waitdone = FALSE;
++	return err;
++}
++
++
++#endif /* EHCI_FASTPATH_TX */
++
++/** Called by dbus_usb.c when it wants to download firmware into the dongle */
++bool
++dbus_usbos_dl_cmd(usbos_info_t *usbinfo, uint8 cmd, void *buffer, int buflen)
++{
++	int transferred;
++	int index = 0;
++	char *tmpbuf;
++
++	if ((usbinfo == NULL) || (buffer == NULL) || (buflen == 0))
++		return FALSE;
++
++	tmpbuf = (char *) MALLOC(usbinfo->pub->osh, buflen);
++	if (!tmpbuf) {
++		DBUSERR(("%s: Unable to allocate memory \n", __FUNCTION__));
++		return FALSE;
++	}
++
++#ifdef BCM_REQUEST_FW
++	if (cmd == DL_GO) {
++		index = 1;
++	}
++#endif
++
++	/* Disable USB autosuspend until this request completes, request USB resume if needed. */
++	USB_AUTOPM_GET_INTERFACE(g_probe_info.intf);
++
++	transferred = USB_CONTROL_MSG(usbinfo->usb, usb_rcvctrlpipe(usbinfo->usb, 0),
++		cmd, (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_INTERFACE),
++		0, index,
++		(void*) tmpbuf, buflen, USB_CTRL_EP_TIMEOUT);
++	if (transferred == buflen) {
++		memcpy(buffer, tmpbuf, buflen);
++	} else {
++		DBUSERR(("%s: usb_control_msg failed %d\n", __FUNCTION__, transferred));
++	}
++
++	USB_AUTOPM_PUT_INTERFACE(g_probe_info.intf);
++
++	MFREE(usbinfo->pub->osh, tmpbuf, buflen);
++	return (transferred == buflen);
++}
++
++/**
++ * Called by dbus_usb.c when it wants to download a buffer into the dongle (e.g. as part of the
++ * download process, when writing nvram variables).
++ */
++int
++dbus_write_membytes(usbos_info_t* usbinfo, bool set, uint32 address, uint8 *data, uint size)
++{
++	hwacc_t hwacc;
++	int write_bytes = 4;
++	int status;
++	int retval = 0;
++
++	DBUSTRACE(("Enter:%s\n", __FUNCTION__));
++
++	/* Read is not supported */
++	if (set == 0) {
++		DBUSERR(("Currently read is not supported!!\n"));
++		return -1;
++	}
++
++	USB_AUTOPM_GET_INTERFACE(g_probe_info.intf);
++
++	hwacc.cmd = DL_CMD_WRHW;
++	hwacc.addr = address;
++
++	DBUSTRACE(("Address:%x size:%d", hwacc.addr, size));
++	do {
++		if (size >= 4) {
++			write_bytes = 4;
++		} else if (size >= 2) {
++			write_bytes = 2;
++		} else {
++			write_bytes = 1;
++		}
++
++		hwacc.len = write_bytes;
++
++		while (size >= write_bytes) {
++			hwacc.data = *((unsigned int*)data);
++
++			status = USB_CONTROL_MSG(usbinfo->usb, usb_sndctrlpipe(usbinfo->usb, 0),
++				DL_WRHW, (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_INTERFACE),
++				1, 0, (char *)&hwacc, sizeof(hwacc_t), USB_CTRL_EP_TIMEOUT);
++
++			if (status < 0) {
++				retval = -1;
++				DBUSERR((" Ctrl write hwacc failed w/status %d @ address:%x \n",
++					status, hwacc.addr));
++				goto err;
++			}
++
++			hwacc.addr += write_bytes;
++			data += write_bytes;
++			size -= write_bytes;
++		}
++	} while (size > 0);
++
++err:
++	USB_AUTOPM_PUT_INTERFACE(g_probe_info.intf);
++
++	return retval;
++}
++
++int
++dbus_usbos_readreg(void *bus, uint32 regaddr, int datalen, uint32 *value)
++{
++	usbos_info_t *usbinfo = (usbos_info_t *) bus;
++	int ret = DBUS_OK;
++	int transferred;
++	uint32 cmd;
++	hwacc_t	hwacc;
++
++	if (usbinfo == NULL)
++		return DBUS_ERR;
++
++	if (datalen == 1)
++		cmd = DL_RDHW8;
++	else if (datalen == 2)
++		cmd = DL_RDHW16;
++	else
++		cmd = DL_RDHW32;
++
++	USB_AUTOPM_GET_INTERFACE(g_probe_info.intf);
++
++	transferred = USB_CONTROL_MSG(usbinfo->usb, usb_rcvctrlpipe(usbinfo->usb, 0),
++		cmd, (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_INTERFACE),
++		(uint16)(regaddr), (uint16)(regaddr >> 16),
++		(void *) &hwacc, sizeof(hwacc_t), USB_CTRL_EP_TIMEOUT);
++
++	if (transferred >= sizeof(hwacc_t)) {
++		*value = hwacc.data;
++	} else {
++		DBUSERR(("%s: usb_control_msg failed %d\n", __FUNCTION__, transferred));
++		ret = DBUS_ERR;
++	}
++
++	USB_AUTOPM_PUT_INTERFACE(g_probe_info.intf);
++
++	return ret;
++}
++
++int
++dbus_usbos_writereg(void *bus, uint32 regaddr, int datalen, uint32 data)
++{
++	usbos_info_t *usbinfo = (usbos_info_t *) bus;
++	int ret = DBUS_OK;
++	int transferred;
++	uint32 cmd = DL_WRHW;
++	hwacc_t	hwacc;
++
++	if (usbinfo == NULL)
++		return DBUS_ERR;
++
++	USB_AUTOPM_GET_INTERFACE(g_probe_info.intf);
++
++	hwacc.cmd = DL_WRHW;
++	hwacc.addr = regaddr;
++	hwacc.data = data;
++	hwacc.len = datalen;
++
++	transferred = USB_CONTROL_MSG(usbinfo->usb, usb_sndctrlpipe(usbinfo->usb, 0),
++		cmd, (USB_DIR_OUT| USB_TYPE_VENDOR | USB_RECIP_INTERFACE),
++		1, 0,
++		(void *) &hwacc, sizeof(hwacc_t), USB_CTRL_EP_TIMEOUT);
++
++	if (transferred != sizeof(hwacc_t)) {
++		DBUSERR(("%s: usb_control_msg failed %d\n", __FUNCTION__, transferred));
++		ret = DBUS_ERR;
++	}
++
++	USB_AUTOPM_PUT_INTERFACE(g_probe_info.intf);
++
++	return ret;
++}
++
++int
++dbus_usbos_wait(usbos_info_t *usbinfo, uint16 ms)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++	if (in_interrupt())
++		mdelay(ms);
++	else
++		msleep_interruptible(ms);
++#else
++	wait_ms(ms);
++#endif
++	return DBUS_OK;
++}
++
++/** Called by dbus_usb.c as part of the firmware download process */
++bool
++dbus_usbos_dl_send_bulk(usbos_info_t *usbinfo, void *buffer, int len)
++{
++#ifdef EHCI_FASTPATH_TX
++	int ret = DBUS_ERR;
++
++	struct ehci_qtd *qtd = optimize_ehci_qtd_alloc(GFP_KERNEL);
++	int token = EHCI_QTD_SET_CERR(3);
++
++	if (qtd == NULL)
++		goto fail;
++
++	optimize_qtd_fill_with_data(usbinfo->pub, 0, qtd, buffer, token, len);
++	optimize_submit_async(qtd, 0);
++
++	ret = dbus_usbos_sync_wait(usbinfo, USB_SYNC_WAIT_TIMEOUT);
++
++	return (ret == DBUS_OK);
++fail:
++	return FALSE;
++#else
++	bool ret = TRUE;
++	int status;
++	int transferred = 0;
++
++	if (usbinfo == NULL)
++		return DBUS_ERR;
++
++	USB_AUTOPM_GET_INTERFACE(g_probe_info.intf);
++
++	status = USB_BULK_MSG(usbinfo->usb, usbinfo->tx_pipe,
++		buffer, len,
++		&transferred, USB_BULK_EP_TIMEOUT);
++
++	if (status < 0) {
++		DBUSERR(("%s: usb_bulk_msg failed %d\n", __FUNCTION__, status));
++		ret = FALSE;
++	}
++
++	USB_AUTOPM_PUT_INTERFACE(g_probe_info.intf);
++
++	return ret;
++#endif /* EHCI_FASTPATH_TX */
++}
++
++static bool
++dbus_usbos_intf_recv_needed(void *bus)
++{
++	return FALSE;
++}
++
++/**
++ * Higher layer (dbus_usb.c) wants to execute a function on the condition that the rx spin lock has
++ * been acquired.
++ */
++static void*
++dbus_usbos_intf_exec_rxlock(void *bus, exec_cb_t cb, struct exec_parms *args)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++	void *ret;
++	unsigned long flags;
++
++	if (usbos_info == NULL)
++		return NULL;
++
++	spin_lock_irqsave(&usbos_info->rxlock, flags);
++	ret = cb(args);
++	spin_unlock_irqrestore(&usbos_info->rxlock, flags);
++
++	return ret;
++}
++
++static void*
++dbus_usbos_intf_exec_txlock(void *bus, exec_cb_t cb, struct exec_parms *args)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++	void *ret;
++	unsigned long flags;
++
++	if (usbos_info == NULL)
++		return NULL;
++
++	spin_lock_irqsave(&usbos_info->txlock, flags);
++	ret = cb(args);
++	spin_unlock_irqrestore(&usbos_info->txlock, flags);
++
++	return ret;
++}
++
++/**
++ * if an error condition was detected in this module, the higher DBUS layer (dbus_usb.c) has to
++ * be notified.
++ */
++int
++dbus_usbos_errhandler(void *bus, int err)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++
++	if (usbos_info == NULL)
++		return DBUS_ERR;
++
++	if (usbos_info->cbarg && usbos_info->cbs) {
++		if (usbos_info->cbs->errhandler)
++			usbos_info->cbs->errhandler(usbos_info->cbarg, err);
++	}
++
++	return DBUS_OK;
++}
++
++/**
++ * if a change in bus state was detected in this module, the higher DBUS layer (dbus_usb.c) has to
++ * be notified.
++ */
++int
++dbus_usbos_state_change(void *bus, int state)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) bus;
++
++	if (usbos_info == NULL)
++		return DBUS_ERR;
++
++	if (usbos_info->cbarg && usbos_info->cbs) {
++		if (usbos_info->cbs->state_change)
++			usbos_info->cbs->state_change(usbos_info->cbarg, state);
++	}
++
++	usbos_info->pub->busstate = state;
++	return DBUS_OK;
++}
++
++int
++dbus_bus_osl_register(int vid, int pid, probe_cb_t prcb,
++	disconnect_cb_t discb, void *prarg, dbus_intf_t **intf, void *param1, void *param2)
++{
++	bzero(&g_probe_info, sizeof(probe_info_t));
++
++	probe_cb = prcb;
++	disconnect_cb = discb;
++	probe_arg = prarg;
++
++	devid_table[0].idVendor = vid;
++	devid_table[0].idProduct = pid;
++
++	*intf = &dbus_usbos_intf;
++
++	USB_REGISTER();
++
++#ifdef KEEPIF_ON_DEVICE_RESET
++	init_waitqueue_head(&g_probe_info.usbreset_queue_head);
++	atomic_set(&g_probe_info.usbdev_stat, USB_DEVICE_INIT);
++	g_probe_info.usbreset_kt = kthread_create(dbus_usbos_usbreset_func,
++		&g_probe_info, "usbreset-thread");
++	ASSERT(!IS_ERR(g_probe_info.usbreset_kt));
++	wake_up_process(g_probe_info.usbreset_kt);
++#endif /* KEEPIF_ON_DEVICE_RESET */
++
++	return DBUS_ERR_NODEVICE;
++}
++
++int
++dbus_bus_osl_deregister()
++{
++	g_probe_info.dereged = TRUE;
++
++#ifdef KEEPIF_ON_DEVICE_RESET
++	wake_up_interruptible(&g_probe_info.usbreset_queue_head);
++	kthread_stop(g_probe_info.usbreset_kt);
++#endif /* KEEPIF_ON_DEVICE_RESET */
++
++	if (disconnect_cb && disc_arg && (g_probe_info.disc_cb_done == FALSE)) {
++		disconnect_cb(disc_arg);
++		disc_arg = NULL;
++	}
++
++	USB_DEREGISTER();
++
++	return DBUS_OK;
++}
++
++static void
++dbus_usbos_init_info(void)
++{
++	usbos_info_t *usbos_info = g_probe_info.usbos_info;
++
++	if (!usbos_info) {
++		return;
++	}
++
++	/* Update USB Info */
++	usbos_info->usb = g_probe_info.usb;
++	usbos_info->rx_pipe = g_probe_info.rx_pipe;
++	usbos_info->rx_pipe2 = g_probe_info.rx_pipe2;
++	usbos_info->tx_pipe = g_probe_info.tx_pipe;
++	usbos_info->intr_pipe = g_probe_info.intr_pipe;
++	usbos_info->intr_size = g_probe_info.intr_size;
++	usbos_info->interval = g_probe_info.interval;
++	usbos_info->pub->device_speed = g_probe_info.device_speed;
++	usbos_info->pub->dev_info = g_probe_info.usb;
++	if (usbos_info->rx_pipe2) {
++		usbos_info->pub->attrib.has_2nd_bulk_in_ep = 1;
++	} else {
++		usbos_info->pub->attrib.has_2nd_bulk_in_ep = 0;
++	}
++
++	if (usbos_info->tx_pipe)
++		usbos_info->maxps = usb_maxpacket(usbos_info->usb,
++			usbos_info->tx_pipe, usb_pipeout(usbos_info->tx_pipe));
++}
++
++void *
++dbus_usbos_intf_attach(dbus_pub_t *pub, void *cbarg, dbus_intf_callbacks_t *cbs)
++{
++	usbos_info_t *usbos_info;
++
++	if (g_probe_info.dldone == FALSE) {
++		DBUSERR(("%s: err device not downloaded!\n", __FUNCTION__));
++		return NULL;
++	}
++
++	/* Sanity check for BUS_INFO() */
++	ASSERT(OFFSETOF(usbos_info_t, pub) == 0);
++
++	usbos_info = MALLOC(pub->osh, sizeof(usbos_info_t));
++	if (usbos_info == NULL)
++		return NULL;
++
++	bzero(usbos_info, sizeof(usbos_info_t));
++
++	usbos_info->pub = pub;
++	usbos_info->cbarg = cbarg;
++	usbos_info->cbs = cbs;
++
++	/* Needed for disconnect() */
++	g_probe_info.usbos_info = usbos_info;
++	dbus_usbos_init_info();
++
++	INIT_LIST_HEAD(&usbos_info->req_rxfreeq);
++	INIT_LIST_HEAD(&usbos_info->req_txfreeq);
++	INIT_LIST_HEAD(&usbos_info->req_rxpostedq);
++	INIT_LIST_HEAD(&usbos_info->req_txpostedq);
++	spin_lock_init(&usbos_info->rxfree_lock);
++	spin_lock_init(&usbos_info->txfree_lock);
++	spin_lock_init(&usbos_info->rxposted_lock);
++	spin_lock_init(&usbos_info->txposted_lock);
++	spin_lock_init(&usbos_info->rxlock);
++	spin_lock_init(&usbos_info->txlock);
++
++	atomic_set(&usbos_info->rxposted, 0);
++	atomic_set(&usbos_info->txposted, 0);
++
++#ifdef DBUS_LINUX_RXDPC
++	INIT_LIST_HEAD(&usbos_info->req_rxpendingq);
++	spin_lock_init(&usbos_info->rxpending_lock);
++#endif /* DBUS_LINUX_RXDPC */
++
++#if defined(DBUS_LINUX_HIST)
++	usbos_info->txposted_hist = MALLOC(pub->osh, (usbos_info->pub->ntxq+1) * sizeof(int));
++	if (usbos_info->txposted_hist) {
++		bzero(usbos_info->txposted_hist, (usbos_info->pub->ntxq+1) * sizeof(int));
++	}
++	usbos_info->rxposted_hist = MALLOC(pub->osh, (usbos_info->pub->nrxq+1) * sizeof(int));
++	if (usbos_info->rxposted_hist) {
++		bzero(usbos_info->rxposted_hist, (usbos_info->pub->nrxq+1) * sizeof(int));
++	}
++#endif
++#ifdef USB_DISABLE_INT_EP
++	usbos_info->intr_urb = NULL;
++#else
++	if (!(usbos_info->intr_urb = USB_ALLOC_URB())) {
++		DBUSERR(("%s: usb_alloc_urb (tx) failed\n", __FUNCTION__));
++		goto fail;
++	}
++#endif
++
++	if (!(usbos_info->ctl_urb = USB_ALLOC_URB())) {
++		DBUSERR(("%s: usb_alloc_urb (tx) failed\n", __FUNCTION__));
++		goto fail;
++	}
++
++	init_waitqueue_head(&usbos_info->wait);
++
++	if (!(usbos_info->blk_urb = USB_ALLOC_URB())) {	/* for embedded image downloading */
++		DBUSERR(("%s: usb_alloc_urb (tx) failed\n", __FUNCTION__));
++		goto fail;
++	}
++
++	usbos_info->rxbuf_len = (uint)usbos_info->pub->rxsize;
++
++
++#ifdef DBUS_LINUX_RXDPC		/* Initialize DPC thread */
++	sema_init(&usbos_info->dpc_sem, 0);
++	init_completion(&usbos_info->dpc_exited);
++	usbos_info->dpc_pid = kernel_thread(dbus_usbos_dpc_thread, usbos_info, 0);
++	if (usbos_info->dpc_pid < 0) {
++		DBUSERR(("%s: failed to create dpc thread\n", __FUNCTION__));
++		goto fail;
++	}
++#endif /* DBUS_LINUX_RXDPC */
++
++	atomic_set(&usbos_info->txallocated, 0);
++	if (DBUS_OK != dbus_usbos_urbreqs_alloc(usbos_info,
++		usbos_info->pub->ntxq, FALSE)) {
++		goto fail;
++	}
++
++	atomic_set(&usbos_info->rxallocated, 0);
++	if (DBUS_OK != dbus_usbos_urbreqs_alloc(usbos_info,
++#ifdef CTFPOOL
++		usbos_info->pub->nrxq,
++#else
++		MIN(DBUS_USB_RXQUEUE_BATCH_ADD, usbos_info->pub->nrxq),
++#endif
++		TRUE)) {
++		goto fail;
++	}
++
++	sema_init(&usbos_info->ctl_lock, 1);
++
++#ifdef USBOS_THREAD
++	if (dbus_usbos_thread_init(usbos_info) == NULL)
++		goto fail;
++#endif /* USBOS_THREAD */
++
++#ifdef USBOS_TX_THREAD
++	if (dbus_usbos_tx_thread_init(usbos_info) == NULL)
++		goto fail;
++#endif /* USBOS_TX_THREAD */
++
++#if defined(EHCI_FASTPATH_TX) || defined(EHCI_FASTPATH_RX)
++	spin_lock_init(&usbos_info->fastpath_lock);
++	if (optimize_init(usbos_info, usbos_info->usb, usbos_info->tx_pipe,
++		usbos_info->rx_pipe, usbos_info->rx_pipe2) != 0) {
++		DBUSERR(("%s: optimize_init failed!\n", __FUNCTION__));
++		goto fail;
++	}
++
++#endif /* EHCI_FASTPATH_TX || EHCI_FASTPATH_RX */
++
++	return (void *) usbos_info;
++fail:
++#ifdef DBUS_LINUX_RXDPC
++	if (usbos_info->dpc_pid >= 0) {
++		KILL_PROC(usbos_info->dpc_pid, SIGTERM);
++		wait_for_completion(&usbos_info->dpc_exited);
++	}
++#endif /* DBUS_LINUX_RXDPC */
++	if (usbos_info->intr_urb) {
++		USB_FREE_URB(usbos_info->intr_urb);
++		usbos_info->intr_urb = NULL;
++	}
++
++	if (usbos_info->ctl_urb) {
++		USB_FREE_URB(usbos_info->ctl_urb);
++		usbos_info->ctl_urb = NULL;
++	}
++
++#if defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW)
++	if (usbos_info->blk_urb) {
++		USB_FREE_URB(usbos_info->blk_urb);
++		usbos_info->blk_urb = NULL;
++	}
++#endif
++
++	dbus_usbos_urbreqs_free(usbos_info, TRUE);
++	atomic_set(&usbos_info->rxallocated, 0);
++	dbus_usbos_urbreqs_free(usbos_info, FALSE);
++	atomic_set(&usbos_info->txallocated, 0);
++
++	g_probe_info.usbos_info = NULL;
++
++	MFREE(pub->osh, usbos_info, sizeof(usbos_info_t));
++	return NULL;
++} /* dbus_usbos_intf_attach */
++
++void
++dbus_usbos_intf_detach(dbus_pub_t *pub, void *info)
++{
++	usbos_info_t *usbos_info = (usbos_info_t *) info;
++	osl_t *osh = pub->osh;
++
++	if (usbos_info == NULL) {
++		return;
++	}
++
++#ifdef USBOS_TX_THREAD
++	dbus_usbos_tx_thread_deinit(usbos_info);
++#endif /* USBOS_TX_THREAD */
++
++#if defined(EHCI_FASTPATH_TX) || defined(EHCI_FASTPATH_RX)
++	optimize_deinit(usbos_info, usbos_info->usb);
++#endif
++	/* Must unlink all URBs prior to driver unload;
++	 * otherwise an URB callback can occur after driver
++	 * has been de-allocated and rmmod'd
++	 */
++	dbusos_stop(usbos_info);
++
++	if (usbos_info->intr_urb) {
++		USB_FREE_URB(usbos_info->intr_urb);
++		usbos_info->intr_urb = NULL;
++	}
++
++	if (usbos_info->ctl_urb) {
++		USB_FREE_URB(usbos_info->ctl_urb);
++		usbos_info->ctl_urb = NULL;
++	}
++
++	if (usbos_info->blk_urb) {
++		USB_FREE_URB(usbos_info->blk_urb);
++		usbos_info->blk_urb = NULL;
++	}
++
++	dbus_usbos_urbreqs_free(usbos_info, TRUE);
++	atomic_set(&usbos_info->rxallocated, 0);
++	dbus_usbos_urbreqs_free(usbos_info, FALSE);
++	atomic_set(&usbos_info->txallocated, 0);
++
++#if defined(DBUS_LINUX_HIST)
++	if (usbos_info->txposted_hist) {
++		MFREE(osh, usbos_info->txposted_hist, (usbos_info->pub->ntxq+1) * sizeof(int));
++	}
++	if (usbos_info->rxposted_hist) {
++		MFREE(osh, usbos_info->rxposted_hist, (usbos_info->pub->nrxq+1) * sizeof(int));
++	}
++#endif 
++#ifdef USBOS_THREAD
++	dbus_usbos_thread_deinit(usbos_info);
++#endif /* USBOS_THREAD */
++
++	g_probe_info.usbos_info = NULL;
++	MFREE(osh, usbos_info, sizeof(usbos_info_t));
++} /* dbus_usbos_intf_detach */
++
++
++#ifdef USBOS_TX_THREAD
++
++void*
++dbus_usbos_tx_thread_init(usbos_info_t *usbos_info)
++{
++	spin_lock_init(&usbos_info->usbos_tx_list_lock);
++	INIT_LIST_HEAD(&usbos_info->usbos_tx_list);
++	init_waitqueue_head(&usbos_info->usbos_tx_queue_head);
++
++	usbos_info->usbos_tx_kt = kthread_create(dbus_usbos_tx_thread_func,
++		usbos_info, "usb-tx-thread");
++
++	if (IS_ERR(usbos_info->usbos_tx_kt)) {
++		DBUSERR(("Thread Creation failed\n"));
++		return (NULL);
++	}
++
++	usbos_info->ctl_state = USBOS_REQUEST_STATE_UNSCHEDULED;
++	wake_up_process(usbos_info->usbos_tx_kt);
++
++	return (usbos_info->usbos_tx_kt);
++}
++
++void
++dbus_usbos_tx_thread_deinit(usbos_info_t *usbos_info)
++{
++	urb_req_t *req;
++
++	if (usbos_info->usbos_tx_kt) {
++		wake_up_interruptible(&usbos_info->usbos_tx_queue_head);
++		kthread_stop(usbos_info->usbos_tx_kt);
++	}
++
++	/* Move pending requests to free queue so they can be freed */
++	while ((req = dbus_usbos_qdeq(
++		&usbos_info->usbos_tx_list, &usbos_info->usbos_tx_list_lock)) != NULL) {
++		dbus_usbos_qenq(&usbos_info->req_txfreeq, req, &usbos_info->txfree_lock);
++	}
++}
++
++/**
++ * Allow USB in-band resume to block by submitting CTRL and DATA URBs on a separate thread.
++ */
++int
++dbus_usbos_tx_thread_func(void *data)
++{
++	usbos_info_t  *usbos_info = (usbos_info_t *)data;
++	urb_req_t     *req;
++	dbus_irb_tx_t *txirb;
++	int           ret;
++	unsigned long flags;
++
++#ifdef WL_THREADNICE
++	set_user_nice(current, WL_THREADNICE);
++#endif
++
++	while (1) {
++		/* Wait until there are URBs to submit */
++		wait_event_interruptible_timeout(
++			usbos_info->usbos_tx_queue_head,
++			!list_empty(&usbos_info->usbos_tx_list) ||
++			usbos_info->ctl_state == USBOS_REQUEST_STATE_SCHEDULED,
++			100);
++
++		if (kthread_should_stop())
++			break;
++
++		/* Submit CTRL URB if needed */
++		if (usbos_info->ctl_state == USBOS_REQUEST_STATE_SCHEDULED) {
++
++			/* Disable USB autosuspend until this request completes. If the
++			 * interface was suspended, this call blocks until it has been resumed.
++			 */
++			USB_AUTOPM_GET_INTERFACE(g_probe_info.intf);
++
++			usbos_info->ctl_state = USBOS_REQUEST_STATE_SUBMITTED;
++
++			ret = USB_SUBMIT_URB(usbos_info->ctl_urb);
++			if (ret != 0) {
++				DBUSERR(("%s CTRL USB_SUBMIT_URB failed, status %d\n",
++					__FUNCTION__, ret));
++
++				usbos_info->ctl_state = USBOS_REQUEST_STATE_UNSCHEDULED;
++				up(&usbos_info->ctl_lock);
++
++				USB_AUTOPM_PUT_INTERFACE_ASYNC(g_probe_info.intf);
++			}
++		}
++
++		/* Submit all available TX URBs */
++		while ((req = dbus_usbos_qdeq(&usbos_info->usbos_tx_list,
++			&usbos_info->usbos_tx_list_lock)) != NULL) {
++
++			/* Disable USB autosuspend until this request completes. If the
++			 * interface was suspended, this call blocks until it has been resumed.
++			 */
++			USB_AUTOPM_GET_INTERFACE(g_probe_info.intf);
++
++			spin_lock_irqsave(&usbos_info->txlock, flags);
++
++			ret = USB_SUBMIT_URB(req->urb);
++			if (ret == 0) {
++				/* URB submitted successfully */
++				dbus_usbos_qenq(&usbos_info->req_txpostedq, req,
++					&usbos_info->txposted_lock);
++				atomic_inc(&usbos_info->txposted);
++			} else {
++				/* Submitting the URB failed. */
++				DBUSERR(("%s TX USB_SUBMIT_URB failed, status %d\n",
++					__FUNCTION__, ret));
++
++				USB_AUTOPM_PUT_INTERFACE_ASYNC(g_probe_info.intf);
++			}
++
++			spin_unlock_irqrestore(&usbos_info->txlock, flags);
++
++			if (ret != 0) {
++				/* Cleanup and notify higher layers */
++				dbus_usbos_qenq(&usbos_info->req_txfreeq, req,
++					&usbos_info->txfree_lock);
++
++				txirb = req->arg;
++				if (txirb->send_buf) {
++					MFREE(usbos_info->pub->osh, txirb->send_buf, req->buf_len);
++					txirb->send_buf = NULL;
++					req->buf_len = 0;
++				}
++
++				if (likely (usbos_info->cbarg && usbos_info->cbs)) {
++					if (likely (usbos_info->cbs->send_irb_complete != NULL))
++						usbos_info->cbs->send_irb_complete(
++							usbos_info->cbarg, txirb, DBUS_ERR_TXDROP);
++				}
++			}
++		}
++	}
++
++	return 0;
++} /* dbus_usbos_tx_thread_func */
++
++#endif /* USBOS_TX_THREAD */
++
++#ifdef USBOS_THREAD
++
++/**
++ * Increase system performance by creating a USB thread that runs parallel to other system
++ * activity.
++ */
++static void*
++dbus_usbos_thread_init(usbos_info_t *usbos_info)
++{
++	usbos_list_entry_t  *entry;
++	unsigned long       flags, ii;
++
++	spin_lock_init(&usbos_info->usbos_list_lock);
++	spin_lock_init(&usbos_info->ctrl_lock);
++	INIT_LIST_HEAD(&usbos_info->usbos_list);
++	INIT_LIST_HEAD(&usbos_info->usbos_free_list);
++	init_waitqueue_head(&usbos_info->usbos_queue_head);
++	atomic_set(&usbos_info->usbos_list_cnt, 0);
++
++
++	for (ii = 0; ii < (usbos_info->pub->nrxq + usbos_info->pub->ntxq); ii++) {
++		entry = MALLOC(usbos_info->pub->osh, sizeof(usbos_list_entry_t));
++		if (entry) {
++			spin_lock_irqsave(&usbos_info->usbos_list_lock, flags);
++			list_add_tail((struct list_head*) entry, &usbos_info->usbos_free_list);
++			spin_unlock_irqrestore(&usbos_info->usbos_list_lock, flags);
++		} else {
++			DBUSERR(("Failed to create list\n"));
++		}
++	}
++
++	usbos_info->usbos_kt = kthread_create(dbus_usbos_thread_func,
++		usbos_info, "usb-thread");
++
++	if (IS_ERR(usbos_info->usbos_kt)) {
++		DBUSERR(("Thread Creation failed\n"));
++		return (NULL);
++	}
++
++	wake_up_process(usbos_info->usbos_kt);
++
++	return (usbos_info->usbos_kt);
++}
++
++static void
++dbus_usbos_thread_deinit(usbos_info_t *usbos_info)
++{
++	struct list_head    *cur, *next;
++	usbos_list_entry_t  *entry;
++	unsigned long       flags;
++
++	if (usbos_info->usbos_kt) {
++		wake_up_interruptible(&usbos_info->usbos_queue_head);
++		kthread_stop(usbos_info->usbos_kt);
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	list_for_each_safe(cur, next, &usbos_info->usbos_list)
++	{
++		entry = list_entry(cur, struct usbos_list_entry, list);
++		/* detach this entry from the list and then free the entry */
++		spin_lock_irqsave(&usbos_info->usbos_list_lock, flags);
++		list_del(cur);
++		MFREE(usbos_info->pub->osh, entry, sizeof(usbos_list_entry_t));
++		spin_unlock_irqrestore(&usbos_info->usbos_list_lock, flags);
++	}
++
++	list_for_each_safe(cur, next, &usbos_info->usbos_free_list)
++	{
++		entry = list_entry(cur, struct usbos_list_entry, list);
++		/* detach this entry from the list and then free the entry */
++		spin_lock_irqsave(&usbos_info->usbos_list_lock, flags);
++		list_del(cur);
++		MFREE(usbos_info->pub->osh, entry, sizeof(usbos_list_entry_t));
++		spin_unlock_irqrestore(&usbos_info->usbos_list_lock, flags);
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++}
++
++/** Process completed URBs in a worker thread */
++static int
++dbus_usbos_thread_func(void *data)
++{
++	usbos_info_t        *usbos_info = (usbos_info_t *)data;
++	usbos_list_entry_t  *entry;
++	struct list_head    *cur, *next;
++	unsigned long       flags;
++
++#ifdef WL_THREADNICE
++	set_user_nice(current, WL_THREADNICE);
++#endif
++
++	while (1) {
++		/* If the list is empty, then go to sleep */
++		wait_event_interruptible_timeout
++		(usbos_info->usbos_queue_head,
++			atomic_read(&usbos_info->usbos_list_cnt) > 0,
++			100);
++
++		if (kthread_should_stop())
++			break;
++
++		spin_lock_irqsave(&usbos_info->usbos_list_lock, flags);
++
++		/* For each entry on the list, process it.  Remove the entry from
++		* the list when done.
++		*/
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++		list_for_each_safe(cur, next, &usbos_info->usbos_list)
++		{
++			urb_req_t           *req;
++			int                 len;
++			int                 stat;
++			usbos_info_t        *usbos_info_local;
++
++			entry = list_entry(cur, struct usbos_list_entry, list);
++			if (entry == NULL)
++				break;
++
++			req = entry->urb_context;
++			len = entry->urb_length;
++			stat = entry->urb_status;
++			usbos_info_local = req->usbinfo;
++
++			/* detach this entry from the list and attach it to the free list */
++			list_del_init(cur);
++			spin_unlock_irqrestore(&usbos_info_local->usbos_list_lock, flags);
++
++			dbus_usbos_recv_complete_handle(req, len, stat);
++
++			spin_lock_irqsave(&usbos_info_local->usbos_list_lock, flags);
++
++			list_add_tail(cur, &usbos_info_local->usbos_free_list);
++
++			atomic_dec(&usbos_info_local->usbos_list_cnt);
++		}
++
++		spin_unlock_irqrestore(&usbos_info->usbos_list_lock, flags);
++
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++	return 0;
++} /* dbus_usbos_thread_func */
++
++/** Called on Linux calling URB callback, see dbus_usbos_recv_complete() */
++static void
++dbus_usbos_dispatch_schedule(CALLBACK_ARGS)
++{
++	urb_req_t           *req = urb->context;
++	usbos_info_t        *usbos_info = req->usbinfo;
++	usbos_list_entry_t  *entry;
++	unsigned long       flags;
++	struct list_head    *cur;
++
++	spin_lock_irqsave(&usbos_info->usbos_list_lock, flags);
++
++	cur   = usbos_info->usbos_free_list.next;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wcast-qual"
++#endif
++	entry = list_entry(cur, struct usbos_list_entry, list);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
++#pragma GCC diagnostic pop
++#endif
++
++	/* detach this entry from the free list and prepare it insert it to use list */
++	list_del_init(cur);
++
++	if (entry) {
++		entry->urb_context = urb->context;
++		entry->urb_length  = urb->actual_length;
++		entry->urb_status  = urb->status;
++
++		atomic_inc(&usbos_info->usbos_list_cnt);
++		list_add_tail(cur, &usbos_info->usbos_list);
++	} else {
++		DBUSERR(("!!!!!!OUT OF MEMORY!!!!!!!\n"));
++	}
++
++	spin_unlock_irqrestore(&usbos_info->usbos_list_lock, flags);
++
++	/* thread */
++	wake_up_interruptible(&usbos_info->usbos_queue_head);
++} /* dbus_usbos_dispatch_schedule */
++
++#endif /* USBOS_THREAD */
++
++#ifdef USB_TRIGGER_DEBUG
++static bool
++dbus_usbos_ctl_send_debugtrig(usbos_info_t* usbinfo)
++{
++	bootrom_id_t id;
++
++	if (usbinfo == NULL)
++		return FALSE;
++
++	id.chip = 0xDEAD;
++
++	dbus_usbos_dl_cmd(usbinfo, DL_DBGTRIG, &id, sizeof(bootrom_id_t));
++
++	/* ignore the result for now */
++	return TRUE;
++}
++#endif /* USB_TRIGGER_DEBUG */
++
++
++#if defined(EHCI_FASTPATH_TX) || defined(EHCI_FASTPATH_RX)
++
++/** New optimized code for USB AP. EHCI fastpath specific function. */
++void inline optimize_ehci_qtd_init(struct ehci_qtd *qtd, dma_addr_t dma)
++{
++	memset(qtd, 0, sizeof(*qtd));
++	wmb();
++	qtd->qtd_self = dma;
++	qtd->qtd_status = cpu_to_le32(EHCI_QTD_HALTED);
++	qtd->qtd_next = EHCI_NULL;
++	qtd->qtd_altnext = EHCI_NULL;
++	qtd->obj_next = NULL;
++	qtd->rpc = NULL;
++	/* qtd->buff = NULL; */
++	qtd->xacterrs = EHCI_QTD_XACTERR_MAX;
++	wmb();
++}
++
++/** EHCI fastpath specific function */
++struct ehci_qtd *optimize_ehci_qtd_alloc(gfp_t flags)
++{
++	struct ehci_qtd		*qtd;
++	dma_addr_t		dma;
++
++	usbos_info_t *usbos_info = g_probe_info.usbos_info;
++
++	struct dma_pool *pool = usbos_info->qtd_pool;
++
++	qtd = dma_pool_alloc(pool, flags, &dma);
++	if (qtd != NULL) {
++		optimize_ehci_qtd_init(qtd, dma);
++	}
++
++	return qtd;
++}
++
++/** EHCI fastpath specific function */
++void optimize_ehci_qtd_free(struct ehci_qtd *qtd)
++{
++	usbos_info_t *usbos_info = g_probe_info.usbos_info;
++	struct dma_pool *pool = usbos_info->qtd_pool;
++	dma_pool_free(pool, qtd, qtd->qtd_self);
++}
++
++/**
++ * EHCI fastpath specific function. Loosely follows qtd_copy_status
++ * Greatly simplified as there are only three options: normal, short read, and disaster
++ */
++static int BCMFASTPATH get_qtd_status(struct ehci_qtd *qtd, int token, int *actual_length)
++{
++	int	status = -EINPROGRESS;
++
++	*actual_length += qtd->length - EHCI_QTD_GET_BYTES(token);
++
++	/* Short read is not an error */
++	if (unlikely (SHORT_READ_Q (token)))
++		status = -EREMOTEIO;
++
++	/* Check for serious problems */
++	if (token & EHCI_QTD_HALTED) {
++		status = -EPROTO;
++		if (token & (EHCI_QTD_BABBLE | EHCI_QTD_MISSEDMICRO | EHCI_QTD_BUFERR |
++			EHCI_QTD_XACTERR))
++			printk("EHCI Fastpath: Serious USB issue qtd %p token %08x --> status %d\n",
++				qtd, token, status);
++	}
++
++	return status;
++}
++
++static void dump_qtd(struct ehci_qtd *qtd)
++{
++	printk("qtd_next %08x qtd_altnext %08x qtd_status %08x\n", qtd->qtd_next,
++		qtd->qtd_altnext, qtd->qtd_status);
++}
++
++static void dump_qh(struct ehci_qh *qh)
++{
++	struct ehci_qtd *qtd = (struct ehci_qtd *)(qh->qh_curqtd | 0xa0000000);
++	printk("EHCI Fastpath: QH %p Dump\n", qh);
++	printk("qtd_next %08x info1 %08x info2 %08x current %08x\n", qh->qh_link, qh->qh_endp,
++		qh->qh_endphub, qh->qh_curqtd);
++	printk("overlay\n");
++	dump_qtd((struct ehci_qtd *)&qh->ow_next);
++	while ((((int)qtd)&EHCI_NULL) == 0)
++	{
++		printk("QTD %p\n", qtd);
++		dump_qtd((struct ehci_qtd *)qtd);
++		qtd = (struct ehci_qtd *)(qtd->qtd_next | 0xa0000000);
++	}
++}
++
++
++/**
++ * EHCI fastpath specific function.
++ * This code assumes the caller holding a lock
++ * It is currently called from scan_async that should have the lock
++ * Lock shall be dropped around the actual completion, then reacquired
++ * This is a clean implementation of the qh_completions()
++ */
++static void BCMFASTPATH ehci_bypass_callback(int pipeindex, struct ehci_qh *qh, spinlock_t *lock)
++{
++							/* Loop variables */
++	struct ehci_qtd		*qtd, 			/* current QTD */
++				*end = qh->dummy, 	/* "afterend" */
++				*next;
++	int			stopped;
++
++	usbos_info_t *usbos_info = g_probe_info.usbos_info;
++
++	/* printk("EHCI Fastpath: callback pipe %d QH %p lock %p\n", pipeindex, qh, lock); */
++
++	/*
++	 * This code should not require any interlocking with QTD additions
++	 * The additions never touch QH, we should never touch 'end'
++	 * Note that QTD additions will keep 'end' in place
++	 */
++	for (qtd = qh->first_qtd; qtd != end; qtd = next)
++	{
++		u32		status;		/* Status bits from QTD */
++
++		/* Get the status bits from the QTD */
++		rmb();
++		status = hc32_to_cpu(qtd->qtd_status);
++
++		if ((status & EHCI_QTD_ACTIVE) == 0) {
++			if (unlikely((status & EHCI_QTD_HALTED) != 0)) {
++				/* Retry transaction errors until we
++				 * reach the software xacterr limit
++				 */
++				if ((status & EHCI_QTD_XACTERR) &&
++					EHCI_QTD_GET_CERR(status) == 0 &&
++					--qtd->xacterrs > 0) {
++					/* Reset the token in the qtd and the
++					 * qh overlay (which still contains
++					 * the qtd) so that we pick up from
++					 * where we left off
++					 */
++					printk("EHCI Fastpath: detected XactErr "
++						"qtd %p len %d/%d retry %d\n",
++						qtd, qtd->length - EHCI_QTD_GET_BYTES(status),
++						qtd->length,
++						EHCI_QTD_XACTERR_MAX - qtd->xacterrs);
++
++					status &= ~EHCI_QTD_HALTED;
++					status |= EHCI_QTD_ACTIVE | EHCI_QTD_SET_CERR(3);
++					qtd->qtd_status = cpu_to_le32(status);
++					wmb();
++					qh->ow_status = cpu_to_le32(status);
++
++					break;
++				}
++
++				/* QTD processing was aborted - highly unlikely (never seen, so not
++				 * tested). In very new 2.6, we can retry. In 2.4 and older 2.6,
++				 * life sucks (the USB stack does the same)
++				 */
++				printk("EHCI Fastpath: QTD halted\n");
++				dump_qh(qh);
++				stopped = 1;
++			}
++		} else {
++			/* Inactive QTD is an afterend, finished the list */
++			break;
++		}
++
++		/* Remove the QTD from software QH. This should be done before dropping the lock
++		 * in for upper layer
++		 */
++		next = qtd->obj_next;
++		qh->first_qtd = next;
++
++		/* Upper layer processing. */
++		if (EHCI_QTD_GET_PID(status) == 0)  /* OUT (host->dongle) pipe */
++		{
++			if (qtd->rpc == NULL)
++			{
++				usbos_info->waitdone = TRUE;
++				wake_up_interruptible(&usbos_info->wait);
++				usbos_info->sync_urb_status = 0;
++			} else {
++
++
++
++				/* usb_info_t *usb_info = (usb_info_t *) handle; */
++				usb_info_t *usb_info = (usb_info_t *) usbos_info->cbarg;
++				/* if(usb_info && usb_info->cbs && usb_info->cbs->send_irb_complete)
++				 * usb_info->cbs->send_irb_complete(usb_info->cbarg, txirb, status);
++				 */
++
++				dbus_info_t *dbus_info = (dbus_info_t *)usb_info->cbarg;
++
++				/* Free the coalesce buffer, if multi-buffer packet only. Do not
++				 * rely on buff, as it might not even exist
++				 */
++				if (PKTNEXT(usbos_info->pub->osh, qtd->rpc)) {
++					/* printk("k-Freeing %p\n", qtd->buff); */
++					kfree(qtd->buff);
++				}
++
++				if (dbus_info->cbs && dbus_info->cbs->send_complete)
++				{
++					atomic_dec(&s_tx_pending);
++					spin_unlock(lock);
++					/* printk("Sending to RPC qtd %p\n", qtd); */
++#if !(defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_TXNOCOPY) || defined(BCM_RPC_TOC))
++	#error Configuration not supported; read dbus_if_send_irb_complete for guidelines
++#endif
++					dbus_info->cbs->send_complete(dbus_info->cbarg, qtd->rpc,
++						0);
++					if ((atomic_read(&s_tx_pending) < 16) &&
++						dbus_info->txoff && !dbus_info->txoverride) {
++						dbus_flowctrl_tx(dbus_info, OFF);
++					}
++					spin_lock(lock);
++
++					/* Things could have happened while the lock was gone,
++					 * resync to the hardware
++					 */
++					next = qh->first_qtd;
++					end = qh->dummy;
++				}
++			}
++
++			optimize_ehci_qtd_free(qtd);
++		} else {   /* IN (dongle->host) pipe */
++			/* Simulates the upstream travel */
++			usb_info_t *usb_info = (usb_info_t *) usbos_info->cbarg;
++			dbus_info_t *dbus_info = (dbus_info_t *)usb_info->cbarg;
++			/* unsigned long       flags; */
++			int actual_length = 0;
++
++			/* All our reads must be short */
++			if (!SHORT_READ_Q (status)) ASSERT(0);
++
++			/* Done with hardware, convert status to error codes */
++			status = get_qtd_status(qtd, status, &actual_length);
++
++			switch (status) {
++			/* success */
++			case 0:
++			case -EINPROGRESS:
++			case -EREMOTEIO:
++				status = 0;
++				break;
++
++			case -ECONNRESET:		/* canceled */
++			case -ENOENT:
++			case -EPROTO:
++				DBUSERR(("%s: ehci unlink. status %x\n", __FUNCTION__, status));
++				break;
++			}
++
++			if (g_probe_info.dereged) {
++				printk("%s: DBUS deregistering, ignoring recv callback\n",
++					__FUNCTION__);
++				return;
++			}
++
++			dma_unmap_single(
++				usbos_info->usb->bus->controller,
++				(dma_addr_t)qtd->qtd_buffer_hi[0],
++				actual_length,
++				DMA_FROM_DEVICE);
++
++
++			if (dbus_info->pub.busstate != DBUS_STATE_DOWN) {
++				if (status == 0) {
++					void *buf = qtd->rpc;
++
++					ASSERT(buf != NULL);
++					spin_unlock(lock);
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++					/* Note that these ifdefs are indirectly coming from
++					 * dbus_usbos_recv_urb_submit The code itself is from
++					 * dbus_if_recv_irb_complete that makes the decision
++					 * at runtime, yet it is only pkt or buf depending on
++					 * the NOCOPY setup, never both :-)
++					 */
++					if (dbus_info->cbs && dbus_info->cbs->recv_pkt)
++						dbus_info->cbs->recv_pkt(dbus_info->cbarg, buf);
++#else
++					if (actual_length > 0) {
++						if (dbus_info->cbs && dbus_info->cbs->recv_buf)
++							dbus_info->cbs->recv_buf(dbus_info->cbarg,
++							buf, actual_length);
++					}
++#endif
++					spin_lock(lock);
++
++					/* Things could have happened while the lock was gone,
++					 * resync to the hardware
++					 */
++					next = qh->first_qtd;
++					end = qh->dummy;
++
++					/* Reinitialize this qtd since it will be reused. */
++					optimize_ehci_qtd_init(qtd, qtd->qtd_self);
++
++#if defined(BCM_RPC_NOCOPY) || defined(BCM_RPC_RXNOCOPY)
++					/* Note that these ifdefs are coming from
++					 * dbus_usbos_recv_urb_submit. In the NOCOPY configuration,
++					 * force an allocation of a new packet
++					 */
++					optimize_submit_rx_request(&dbus_info->pub, 1, qtd, NULL);
++
++#else
++					/* In the copy mode, simply reuse the buffer; upper level
++					 * had already consumed the data
++					 */
++					optimize_submit_rx_request(&dbus_info->pub, 1, qtd, buf);
++#endif
++					/* Not to free this qtd because it will be reused. */
++					continue;
++				}
++			} else {
++				printk("%s: DBUS down, ignoring recv callback\n", __FUNCTION__);
++			}
++			optimize_ehci_qtd_free(qtd);
++		}
++	}
++} /* ehci_bypass_callback */
++
++/** EHCI fastpath specific function */
++static void optimize_urb_callback(struct urb *urb)
++{
++	struct usb_ctrlrequest *req = urb->context;
++
++	kfree(req);
++	USB_FREE_URB(urb);
++}
++
++/**
++ * EHCI fastpath specific function. Shall be called under an external lock (currently RPC_TP_LOCK)
++ */
++static int optimize_submit_urb(struct usb_device *usb, void *ptr, int request)
++{
++	struct usb_ctrlrequest *req;
++	struct urb *urb;
++
++	if ((urb = USB_ALLOC_URB()) == NULL) {
++		printk("EHCI Fastpath: Error allocating URB in optimize_EP!");
++		return -ENOMEM;
++	}
++
++	if ((req = kmalloc(sizeof(struct usb_ctrlrequest), GFP_ATOMIC)) == NULL) {
++		printk("EHCI Fastpath: Failed to allocate memory for control request in"
++			" optimize_EP!");
++		USB_FREE_URB(urb);
++		return -ENOMEM;
++	}
++
++	req->bRequestType = (USB_TYPE_VENDOR | USB_RECIP_OTHER);
++	req->bRequest = request;
++
++	/* Use this instead of a buffer */
++	req->wValue = ((int)ptr & 0xffff);
++	req->wIndex = ((((int)ptr)>>16) & 0xffff);
++	req->wLength = 0;
++
++	printk("EHCI Fastpath: usb_dev %p\n", usb);
++	printk("EHCI Fastpath: bus %p\n", usb->bus);
++	printk("EHCI Fastpath: Hub %p\n", usb->bus->root_hub);
++
++	usb_fill_control_urb(
++		urb,
++		usb->bus->root_hub,
++		usb_sndctrlpipe(usb->bus->root_hub, 0),
++		(void *)req,
++		NULL,
++		0,
++		optimize_urb_callback,
++		req);
++
++	USB_SUBMIT_URB(urb);
++
++	if (urb->status != 0) {
++		printk("EHCI Fastpath: Cannot submit URB in optimize_EP: %d\n", urb->status);
++	}
++
++	return urb->status;
++} /* optimize_submit_urb */
++
++/** EHCI fastpath specific function */
++static int epnum(int pipe)
++{
++	int epn = usb_pipeendpoint(pipe);
++	if (usb_pipein (pipe))
++		epn |= 0x10;
++	return epn;
++}
++
++/** EHCI fastpath specific function */
++static int optimize_init(usbos_info_t *usbos_info, struct usb_device *usb, int out, int in, int in2)
++{
++	int retval = -EPIPE;
++
++	atomic_set(&s_tx_pending, 0);
++	/* atomic_set(&s_rx_pending, 0); */
++
++	usbos_info->tx_ep = epnum(out);
++	usbos_info->rx_ep = epnum(in);
++	usbos_info->rx2_ep = epnum(in2);
++	usbos_info->usb_device = usb;
++
++	/* printk("EHCI Fastpath: Create pool %p %p %p\n", usb, usb->bus, usb->bus->controller); */
++
++	/* QTDs for bulk transfers - separate pool */
++	usbos_info->qtd_pool = dma_pool_create("usbnet_qtd",
++		usb->bus->controller,
++		sizeof(struct ehci_qtd),
++		EHCI_QTD_ALIGN /* byte alignment (for hw parts) */,
++		4096 /* can't cross 4K */);
++	if (!usbos_info->qtd_pool) {
++		printk("EHCI Fastpath: Cannot create the QTD pool\n");
++		goto fail;
++	}
++
++	/* detaching the EP */
++	if (optimize_submit_urb(usb, usb, EHCI_SET_BYPASS_DEV) != 0)
++		goto fail;
++	optimize_submit_urb(usb, ehci_bypass_callback, EHCI_SET_BYPASS_CB);
++	optimize_submit_urb(usb, usbos_info->qtd_pool, EHCI_SET_BYPASS_POOL);
++#ifdef EHCI_FASTPATH_TX
++	optimize_submit_urb(usb, (void*)((0<<16)|usbos_info->tx_ep), EHCI_FASTPATH);
++#endif
++#ifdef EHCI_FASTPATH_RX
++	optimize_submit_urb(usb, (void*)((1<<16)|usbos_info->rx_ep),   EHCI_FASTPATH);
++#endif
++
++	/* getting the QH */
++	printk("EHCI Fastpath: EP in %d EP in2 %d EP out %d\n", usbos_info->rx_ep,
++		usbos_info->rx2_ep, usbos_info->tx_ep);
++
++	return 0;
++
++fail:
++	return retval;
++} /* optimize_submit_urb */
++
++/** EHCI fastpath specific function */
++static int optimize_deinit_qtds(struct ehci_qh *qh, int coalesce_buf)
++{
++	usbos_info_t *usbos_info = g_probe_info.usbos_info;
++	struct ehci_qtd *qtd, *end, *next;
++	unsigned long	flags;
++
++	if (qh == NULL)
++		return 0;
++
++	end = qh->dummy;
++
++	printk("%s %d. qh = %p\n", __func__, __LINE__, qh);
++
++	spin_lock_irqsave(&usbos_info->fastpath_lock, flags);
++	for (qtd = qh->first_qtd; qtd != end; qtd = next) {
++		next = qtd->obj_next;
++		qh->first_qtd = next;
++
++		/* Free the coalesce buffer, if multi-buffer packet only. Do not
++		 * rely on buff, as it might not even exist
++		 */
++		if (coalesce_buf && PKTNEXT(usbos_info->pub->osh, qtd->rpc)) {
++			printk("k-Freeing %p, ", qtd->buff);
++			kfree(qtd->buff);
++		}
++		printk("freeing qtd %p\n", qtd);
++
++		optimize_ehci_qtd_free(qtd);
++	}
++	spin_unlock_irqrestore(&usbos_info->fastpath_lock, flags);
++
++	return 0;
++}
++
++static BCMFASTPATH struct ehci_qh *get_ep(usbos_info_t *usbos_info, int ep)
++{
++#ifdef KERNEL26
++	struct usb_host_endpoint *epp = NULL;
++	switch (ep)
++	{
++	case 0: epp = usbos_info->usb_device->ep_out[usbos_info->tx_ep&0xf]; break;
++	case 1: epp = usbos_info->usb_device->ep_in[usbos_info->rx_ep&0xf]; break;
++	case 2: epp = usbos_info->usb_device->ep_in[usbos_info->rx2_ep&0xf]; break;
++	default: ASSERT(0);
++	}
++	if (epp != NULL)
++		return (struct ehci_qh *)epp->hcpriv;
++	else return NULL;
++#else
++	switch (ep)
++	{
++	case 0: return (struct ehci_qh *)(((struct hcd_dev*)(usbos_info->
++		usb_device->hcpriv))->ep[usbos_info->tx_ep]);
++	case 1: return (struct ehci_qh *)(((struct hcd_dev*)(usbos_info->
++		usb_device->hcpriv))->ep[usbos_info->rx_ep]);
++	case 2: return (struct ehci_qh *)(((struct hcd_dev*)(usbos_info->
++		usb_device->hcpriv))->ep[usbos_info->rx2_ep]);
++	default: ASSERT(0);
++	}
++	return NULL;
++#endif /* KERNEL26 */
++}
++
++/** EHCI fastpath specific function */
++int optimize_deinit(usbos_info_t *usbos_info, struct usb_device *usb)
++{
++	optimize_deinit_qtds(get_ep(usbos_info, 0), 1);
++	optimize_deinit_qtds(get_ep(usbos_info, 1), 0);
++#if defined(EHCI_FASTPATH_TX) || defined(EHCI_FASTPATH_RX)
++	optimize_submit_urb(usb, (void *)0, EHCI_CLR_EP_BYPASS);
++#endif
++	dma_pool_destroy(usbos_info->qtd_pool);
++	return 0;
++}
++
++/** EHCI fastpath specific function. Reassemble the segmented packet */
++static int BCMFASTPATH optimize_gather(const dbus_pub_t *pub, void *pkt, void **buf)
++{
++	int len = 0;
++
++	void *transfer_buf = kmalloc(pkttotlen(pub->osh, pkt),
++		GFP_ATOMIC);
++	*buf = transfer_buf;
++
++	if (!transfer_buf) {
++		printk("fail to alloc to usb buffer\n");
++		return 0;
++	}
++
++	while (pkt) {
++		int pktlen = PKTLEN(pub->osh, pkt);
++		bcopy(PKTDATA(pub->osh, pkt), transfer_buf, pktlen);
++		transfer_buf += pktlen;
++		len += pktlen;
++		pkt = PKTNEXT(pub->osh, pkt);
++	}
++
++	/* printk("Coalesced a %d-byte buffer\n", len); */
++
++	return len;
++}
++
++/** EHCI fastpath specific function */
++int BCMFASTPATH optimize_qtd_fill_with_rpc(const dbus_pub_t *pub, int epn,
++	struct ehci_qtd *qtd, void *rpc, int token, int len)
++{
++	void *data = NULL;
++
++	if (len == 0)
++		return optimize_qtd_fill_with_data(pub, epn, qtd, data, token, len);
++
++	ASSERT(rpc != NULL);
++	data = PKTDATA(pub->osh, rpc);
++	qtd->rpc = rpc;
++
++	if (PKTNEXT(pub->osh, rpc)) {
++		len = optimize_gather(pub, rpc, &data);
++		qtd->buff = data;
++	}
++
++	return optimize_qtd_fill_with_data(pub, epn, qtd, data, token, len);
++}
++
++/** EHCI fastpath specific function. Fill the QTD from the data buffer */
++int BCMFASTPATH optimize_qtd_fill_with_data(const dbus_pub_t *pub, int epn,
++	struct ehci_qtd *qtd, void *data, int token, int len)
++{
++	int		i, bytes_fit, page_offset;
++	dma_addr_t	addr = 0;
++
++	/* struct usb_host_endpoint *ep = get_ep(epn); */
++	usbos_info_t *usbos_info = g_probe_info.usbos_info;
++
++	token |= (EHCI_QTD_ACTIVE | EHCI_QTD_IOC); /* Allow execution, force interrupt */
++
++	if (len > 0) {
++		addr = dma_map_single(
++			usbos_info->usb->bus->controller,
++			data,
++			len,
++			EHCI_QTD_GET_PID(token) ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
++	}
++
++	qtd->qtd_buffer[0] = cpu_to_hc32((u32)addr);
++	/* Here qtd->qtd_buffer_hi[0] is leveraged to store addr value, which
++	 * is needed when invoking dma_unmap_single() in ehci_bypass_callback().
++	 * This is valid for EHCI 32bit only.
++	 */
++	qtd->qtd_buffer_hi[0] = cpu_to_hc32((u32)addr);
++	page_offset = (addr & (EHCI_PAGE_SIZE-1));
++	bytes_fit = EHCI_PAGE_SIZE - page_offset;
++	addr -= page_offset;
++	if (len < bytes_fit)
++		bytes_fit = len;
++	else {
++		addr +=  EHCI_PAGE_SIZE;
++
++		for (i = 1; bytes_fit < len && i < EHCI_QTD_NBUFFERS; i++) {
++			qtd->qtd_buffer[i] = cpu_to_hc32((u32)addr);
++			qtd->qtd_buffer_hi[i] = 0;
++			addr += EHCI_PAGE_SIZE;
++			if ((bytes_fit + EHCI_PAGE_SIZE) < len)
++				bytes_fit += EHCI_PAGE_SIZE;
++			else
++				bytes_fit = len;
++		}
++
++		if (bytes_fit != len)
++		{
++			ASSERT(0);
++		}
++	}
++	qtd->qtd_status = cpu_to_hc32((bytes_fit << 16) | token);
++	qtd->length = bytes_fit;
++
++	return bytes_fit;
++} /* optimize_qtd_fill_with_data */
++
++
++/**
++ * EHCI fastpath specific function. Reimplementation of qh_append_tds(). Returns nonzero if too many
++ * requests pending.
++ */
++int BCMFASTPATH optimize_submit_async(struct ehci_qtd *qtd, int epn)
++{
++	/* Clean implementation along the lines of qh_append_tds() */
++
++	struct ehci_qtd		*afterend; /* Element at the end of the QTD chain (after the
++					    * last useful one, "after-end")
++					    */
++	dma_addr_t		hw_addr;
++	__hc32			status;
++	unsigned long	flags;
++
++	usbos_info_t *usbos_info = g_probe_info.usbos_info;
++	struct ehci_qh *qh = get_ep(usbos_info, epn);
++	usb_info_t *usb_info = (usb_info_t *) usbos_info->cbarg;
++	dbus_info_t *dbus_info = (dbus_info_t *)usb_info->cbarg;
++
++	/* printk("Submit qtd %p to pipe %d (%p)\n", qtd, epn, qh); */
++	if (qh == NULL)
++	{
++		printk("EHCI Fastpath: Attempt of optimized submit to a non-optimized pipe\n");
++		return -1;
++	}
++
++	spin_lock_irqsave(&usbos_info->fastpath_lock, flags);
++
++	/* Limit outstanding - for rpc behavior only */
++	/* printk("QH qtd_status %08x\n", qh->hw->qtd_status); */
++
++	if ((qtd->qtd_status & (1<<8)) == 0)
++	{
++		atomic_inc(&s_tx_pending);
++		if (atomic_read(&s_tx_pending) > 16*2) /* (dbus_info->tx_low_watermark * 3)) */
++			dbus_flowctrl_tx(dbus_info, TRUE);
++	}
++
++	ASSERT(qh != NULL);
++
++
++	/*
++	 * Standard list processing trick:
++	 *   * old "afterend" is filled with the incoming data while still HALTed
++	 *   * new element is appended and prepared to serve as new afterend
++	 *   * now old afterend is activated
++	 * This way, HW never races the SW - no semaphores are necessary, as long as this function
++	 * is not reentered for the same QH
++	 */
++
++	/* Make new QTD to be HALTed, wait for it to actually happen */
++	status = qtd->qtd_status;
++	qtd->qtd_status = cpu_to_le32(EHCI_QTD_HALTED);
++	wmb();
++
++	/* Now copy all information from the new QTD to the old afterend,
++	 * except the own HW address
++	 */
++	afterend = qh->dummy;
++	hw_addr = afterend->qtd_self;
++	*afterend = *qtd;
++	afterend->qtd_self = hw_addr;
++
++	/* The new QTD is ready to serve as a new afterend, append it */
++	qh->dummy = qtd;
++	afterend->qtd_next = qtd->qtd_self;
++	afterend->qtd_altnext = qtd->qtd_self;  /* Always assume short read. Harmless in our case */
++	afterend->obj_next = qtd;
++
++	/* Wait for writes to happen and enable the old afterend (now containing the QTD data) */
++	wmb();
++	afterend->qtd_status = status;
++	wmb();
++
++	spin_unlock_irqrestore(&usbos_info->fastpath_lock, flags);
++
++	return 0;
++} /* optimize_submit_async */
++
++void BCMFASTPATH optimize_submit_rx_request(const dbus_pub_t *pub, int epn, struct ehci_qtd *qtd_in,
++                                            void *buf)
++{
++	usbos_info_t *usbos_info = g_probe_info.usbos_info;
++	int len = usbos_info->rxbuf_len;
++	void *pkt;
++	struct ehci_qtd *qtd;
++	int token = EHCI_QTD_SET_CERR(3) | EHCI_QTD_SET_PID(1);
++
++	if (qtd_in == NULL) {
++		qtd = optimize_ehci_qtd_alloc(GFP_KERNEL);
++		if (!qtd) {
++			printk("EHCI Fastpath: Out of QTDs\n");
++			return;
++		}
++	} else {
++		qtd = qtd_in;
++	}
++
++	if (buf == NULL)
++	{
++		/* NOCOPY, allocate own packet */
++		/* Follow dbus_usbos_recv_urb_submit */
++		pkt = PKTGET(usbos_info->pub->osh, len, FALSE);
++		if (pkt == NULL) {
++			printk("%s: PKTGET failed\n", __FUNCTION__);
++			optimize_ehci_qtd_free(qtd);
++			return;
++		}
++		/* consider the packet "native" so we don't count it as MALLOCED in the osl */
++		PKTTONATIVE(usbos_info->pub->osh, pkt);
++		qtd->rpc = pkt;
++		buf = PKTDATA(usbos_info->pub->osh, pkt);
++
++	} else {
++		qtd->rpc = buf;
++	}
++
++	optimize_qtd_fill_with_data(pub, epn, qtd, buf, token, len);
++	optimize_submit_async(qtd, epn);
++} /* optimize_submit_rx_request */
++
++#endif /* EHCI_FASTPATH_TX || EHCI_FASTPATH_RX */
++
++#ifdef BCM_REQUEST_FW
++
++struct request_fw_context {
++	const struct firmware *firmware;
++	struct semaphore lock;
++};
++
++/*
++ * Callback for dbus_request_firmware().
++ */
++static void
++dbus_request_firmware_done(const struct firmware *firmware, void *ctx)
++{
++	struct request_fw_context *context = (struct request_fw_context*)ctx;
++
++	/* Store the received firmware handle in the context and wake requester */
++	context->firmware = firmware;
++	up(&context->lock);
++}
++
++/*
++ * Send a firmware request and wait for completion.
++ *
++ * The use of the asynchronous version of request_firmware() is needed to avoid
++ * kernel oopses when we just come out of system hibernate.
++ */
++static int
++dbus_request_firmware(const char *name, const struct firmware **firmware)
++{
++	struct request_fw_context *context;
++	int ret;
++
++	context = kzalloc(sizeof(*context), GFP_KERNEL);
++	if (!context)
++		return -ENOMEM;
++
++	sema_init(&context->lock, 0);
++
++	ret = request_firmware_nowait(THIS_MODULE, true, name, &g_probe_info.usb->dev,
++	                              GFP_KERNEL, context, dbus_request_firmware_done);
++	if (ret) {
++		kfree(context);
++		return ret;
++	}
++
++	/* Wait for completion */
++	if (down_interruptible(&context->lock) != 0) {
++		kfree(context);
++		return -ERESTARTSYS;
++	}
++
++	*firmware = context->firmware;
++	kfree(context);
++
++	return *firmware != NULL ? 0 : -ENOENT;
++}
++
++static void *
++dbus_get_fwfile(int devid, int chiprev, uint8 **fw, int *fwlen, uint16 boardtype, uint16 boardrev)
++{
++	const struct firmware *firmware = NULL;
++	s8 file_name[64];
++	int ret;
++
++	snprintf(file_name, sizeof(file_name), "%s", CONFIG_ANDROID_BCMDHD_1_363_125_17_FW_PATH);
++
++	ret = dbus_request_firmware(file_name, &firmware);
++	if (ret) {
++		DBUSERR(("fail to request firmware %s\n", file_name));
++		return NULL;
++	}
++
++	*fwlen = firmware->size;
++	*fw = (uint8 *)firmware->data;
++	return (void *)firmware;
++
++}
++
++static void *
++dbus_get_nvfile(int devid, int chiprev, uint8 **fw, int *fwlen, uint16 boardtype, uint16 boardrev)
++{
++	const struct firmware *firmware = NULL;
++	s8 file_name[64];
++	int ret;
++
++	snprintf(file_name, sizeof(file_name), "%s", CONFIG_ANDROID_BCMDHD_1_363_125_17_NVRAM_PATH);
++
++	ret = dbus_request_firmware(file_name, &firmware);
++	if (ret) {
++		DBUSERR(("fail to request nvram %s\n", file_name));
++
++
++		if (ret) {
++			DBUSERR(("fail to request nvram %s\n", file_name));
++			return NULL;
++		}
++	}
++
++	*fwlen = firmware->size;
++	*fw = (uint8 *)firmware->data;
++	return (void *)firmware;
++}
++
++void *
++dbus_get_fw_nvfile(int devid, int chiprev, uint8 **fw, int *fwlen, int type, uint16 boardtype,
++	uint16 boardrev)
++{
++	switch (type) {
++		case DBUS_FIRMWARE:
++			return dbus_get_fwfile(devid, chiprev, fw, fwlen, boardtype, boardrev);
++		case DBUS_NVFILE:
++			return dbus_get_nvfile(devid, chiprev, fw, fwlen, boardtype, boardrev);
++		default:
++			return NULL;
++	}
++}
++
++void
++dbus_release_fw_nvfile(void *firmware)
++{
++	release_firmware((struct firmware *)firmware);
++}
++#endif /* BCM_REQUEST_FW */
++
++#ifdef BCMUSBDEV_COMPOSITE
++/**
++ * For a composite device the interface order is not guaranteed, scan the device struct for the WLAN
++ * interface.
++ */
++static int
++dbus_usbos_intf_wlan(struct usb_device *usb)
++{
++	int i, num_of_eps, ep, intf_wlan = -1;
++	int num_intf = CONFIGDESC(usb)->bNumInterfaces;
++	struct usb_endpoint_descriptor *endpoint;
++
++	for (i = 0; i < num_intf; i++) {
++		if (IFDESC(usb, i).bInterfaceClass != USB_CLASS_VENDOR_SPEC)
++			continue;
++		num_of_eps = IFDESC(usb, i).bNumEndpoints;
++
++		for (ep = 0; ep < num_of_eps; ep++) {
++			endpoint = &IFEPDESC(usb, i, ep);
++			if ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
++				USB_ENDPOINT_XFER_BULK) {
++				intf_wlan = i;
++				break;
++			}
++		}
++		if (ep < num_of_eps)
++			break;
++	}
++
++	return intf_wlan;
++}
++#endif /* BCMUSBDEV_COMPOSITE */
++
++#ifdef KEEPIF_ON_DEVICE_RESET
++/* if keepif_on_devreset is set, and reset_resume or disconnect got called, we need de-register or
++ * register the usb driver to OS again; but this operation can't be called inside the reset_resume
++ * or disconnect callback, so introduce a kernel thread to do these work
++ */
++static int
++dbus_usbos_usbreset_func(void *data)
++{
++	enum usb_dev_status flag = USB_DEVICE_INIT;
++	usbos_info_t *usbos_info;
++
++	while (1) {
++		wait_event_interruptible_timeout(g_probe_info.usbreset_queue_head,
++			atomic_read(&g_probe_info.usbdev_stat), 100); /* 100 ms */
++
++		if (kthread_should_stop())
++			break;
++		if (!(usbos_info = g_probe_info.usbos_info))
++			continue;
++		if (!(flag = atomic_read(&g_probe_info.usbdev_stat)))
++			continue;
++
++		usbos_info = g_probe_info.usbos_info;
++		flag = atomic_read(&g_probe_info.usbdev_stat);
++		atomic_set(&g_probe_info.usbdev_stat, USB_DEVICE_INIT);
++
++		if ((flag == USB_DEVICE_RESETTED) || (flag == USB_DEVICE_DISCONNECTED)) {
++			DBUSERR(("Device reset, re-register USB driver\n"));
++			g_probe_info.dev_resetted = TRUE;
++			g_probe_info.busstate_bf_devreset = usbos_info->pub->busstate;
++			dbus_usbos_state_change(usbos_info, DBUS_STATE_DOWN);
++
++			g_probe_info.dereged = TRUE;
++			USB_DEREGISTER();
++			USB_REGISTER();
++			g_probe_info.dereged = FALSE;
++		} else if (flag == USB_DEVICE_PROBED) {
++			DBUSERR(("Device probed, but no need to initialize higher layer\n"));
++			g_probe_info.dev_resetted = FALSE;
++			dbus_usbos_init_info();
++			/* The device may have lost power, so a firmware download may be required */
++			dbus_usbos_state_change(usbos_info,
++				DBUS_STATE_DL_NEEDED);
++			g_probe_info.suspend_state = USBOS_SUSPEND_STATE_DEVICE_ACTIVE;
++			dbus_usbos_state_change(usbos_info,
++				g_probe_info.busstate_bf_devreset);
++		}
++	}
++	return 0;
++}
++#endif /* KEEPIF_ON_DEVICE_RESET */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd.h
+new file mode 100644
+index 000000000..4f68c1a0e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd.h
+@@ -0,0 +1,1598 @@
++/*
++ * Header file describing the internal (inter-module) DHD interfaces.
++ *
++ * Provides type definitions and function prototypes used to link the
++ * DHD OS, bus, and protocol modules.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd.h 710120 2019-02-20 02:51:25Z $
++ */
++
++/****************
++ * Common types *
++ */
++
++#ifndef _dhd_h_
++#define _dhd_h_
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/skbuff.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/random.h>
++#include <linux/spinlock.h>
++#include <linux/ethtool.h>
++#include <asm/uaccess.h>
++#include <asm/unaligned.h>
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_HAS_WAKELOCK)
++#include <linux/wakelock.h>
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined (CONFIG_HAS_WAKELOCK) */
++#include <dhd_buzzz.h>
++/* The kernel threading is sdio-specific */
++struct task_struct;
++struct sched_param;
++int setScheduler(struct task_struct *p, int policy, struct sched_param *param);
++int get_scheduler_policy(struct task_struct *p);
++#define MAX_EVENT	16
++
++#define ALL_INTERFACES	0xff
++
++#include <wlioctl.h>
++#include <wlfc_proto.h>
++
++#if defined(BCMWDF)
++#include <wdf.h>
++#include <WdfMiniport.h>
++#endif /* (BCMWDF)  */
++
++#if defined(CUSTOMER_IPCAM)
++#define MAX_RESCHED_CNT 600
++#endif 
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) || \
++	defined(CONFIG_BCMDHD_VENDOR_EXT))
++#define WL_VENDOR_EXT_SUPPORT
++#endif /* 3.14.0 <= LINUX_KERNEL_VERSION || CONFIG_BCMDHD_VENDOR_EXT */
++
++#if defined(KEEP_ALIVE)
++/* Default KEEP_ALIVE Period is 55 sec to prevent AP from sending Keep Alive probe frame */
++#define KEEP_ALIVE_PERIOD 55000
++#define NULL_PKT_STR	"null_pkt"
++#endif /* KEEP_ALIVE */
++
++/* Forward decls */
++struct dhd_bus;
++struct dhd_prot;
++struct dhd_info;
++struct dhd_ioctl;
++struct dhd_dbg;
++
++/* The level of bus communication with the dongle */
++enum dhd_bus_state {
++	DHD_BUS_DOWN,		/* Not ready for frame transfers */
++	DHD_BUS_LOAD,		/* Download access only (CPU reset) */
++	DHD_BUS_DATA,		/* Ready for frame transfers */
++	DHD_BUS_SUSPEND,	/* Bus has been suspended */
++	DHD_BUS_DOWN_IN_PROGRESS,	/* Bus going Down */
++};
++
++/*
++ * Bit fields to Indicate clean up process that wait till they are finished.
++ * Future synchronizable processes can add their bit filed below and update
++ * their functionalities accordingly
++ */
++#define DHD_BUS_BUSY_IN_TX                   0x01
++#define DHD_BUS_BUSY_IN_SEND_PKT             0x02
++#define DHD_BUS_BUSY_IN_DPC                  0x04
++#define DHD_BUS_BUSY_IN_IOVAR                0x08
++#define DHD_BUS_BUSY_IN_WD                   0x10
++#define DHD_BUS_BUSY_IN_SUSPEND              0x20
++#define DHD_BUS_BUSY_IN_RESUME               0x40
++
++/* Download Types */
++typedef enum download_type {
++	FW,
++	NVRAM,
++	CLM_BLOB
++} download_type_t;
++
++
++/* For supporting multiple interfaces */
++#define DHD_MAX_IFS	16
++#define DHD_DEL_IF	-0xE
++#define DHD_BAD_IF	-0xF
++
++enum dhd_op_flags {
++/* Firmware requested operation mode */
++	DHD_FLAG_STA_MODE				= (1 << (0)), /* STA only */
++	DHD_FLAG_HOSTAP_MODE				= (1 << (1)), /* SOFTAP only */
++	DHD_FLAG_P2P_MODE				= (1 << (2)), /* P2P Only */
++	/* STA + P2P */
++	DHD_FLAG_CONCURR_SINGLE_CHAN_MODE = (DHD_FLAG_STA_MODE | DHD_FLAG_P2P_MODE),
++	DHD_FLAG_CONCURR_MULTI_CHAN_MODE		= (1 << (4)), /* STA + P2P */
++	/* Current P2P mode for P2P connection */
++	DHD_FLAG_P2P_GC_MODE				= (1 << (5)),
++	DHD_FLAG_P2P_GO_MODE				= (1 << (6)),
++	DHD_FLAG_MBSS_MODE				= (1 << (7)), /* MBSS in future */
++	DHD_FLAG_IBSS_MODE				= (1 << (8)),
++	DHD_FLAG_MFG_MODE				= (1 << (9)),
++	DHD_FLAG_RSDB_MODE				= (1 << (10)),
++	DHD_FLAG_MP2P_MODE				= (1 << (11))
++};
++
++#define DHD_OPMODE_SUPPORTED(dhd, opmode_flag) \
++	(dhd ? ((((dhd_pub_t *)dhd)->op_mode)  &  opmode_flag) : -1)
++
++/* Max sequential TX/RX Control timeouts to set HANG event */
++#ifndef MAX_CNTL_TX_TIMEOUT
++#define MAX_CNTL_TX_TIMEOUT 2
++#endif /* MAX_CNTL_TX_TIMEOUT */
++#ifndef MAX_CNTL_RX_TIMEOUT
++#define MAX_CNTL_RX_TIMEOUT 1
++#endif /* MAX_CNTL_RX_TIMEOUT */
++
++#define DHD_SCAN_ASSOC_ACTIVE_TIME	40 /* ms: Embedded default Active setting from DHD */
++#define DHD_SCAN_UNASSOC_ACTIVE_TIME 80 /* ms: Embedded def. Unassoc Active setting from DHD */
++#define DHD_SCAN_PASSIVE_TIME		130 /* ms: Embedded default Passive setting from DHD */
++
++#ifndef POWERUP_MAX_RETRY
++#define POWERUP_MAX_RETRY	3 /* how many times we retry to power up the chip */
++#endif
++#ifndef POWERUP_WAIT_MS
++#define POWERUP_WAIT_MS		2000 /* ms: time out in waiting wifi to come up */
++#endif
++#define MAX_NVRAMBUF_SIZE	(16 * 1024) /* max nvram buf size */
++#ifdef DHD_DEBUG
++#define DHD_JOIN_MAX_TIME_DEFAULT 10000 /* ms: Max time out for joining AP */
++#define DHD_SCAN_DEF_TIMEOUT 10000 /* ms: Max time out for scan in progress */
++#endif
++
++
++enum dhd_bus_wake_state {
++	WAKE_LOCK_OFF,
++	WAKE_LOCK_PRIV,
++	WAKE_LOCK_DPC,
++	WAKE_LOCK_IOCTL,
++	WAKE_LOCK_DOWNLOAD,
++	WAKE_LOCK_TMOUT,
++	WAKE_LOCK_WATCHDOG,
++	WAKE_LOCK_LINK_DOWN_TMOUT,
++	WAKE_LOCK_PNO_FIND_TMOUT,
++	WAKE_LOCK_SOFTAP_SET,
++	WAKE_LOCK_SOFTAP_STOP,
++	WAKE_LOCK_SOFTAP_START,
++	WAKE_LOCK_SOFTAP_THREAD
++};
++
++enum dhd_prealloc_index {
++	DHD_PREALLOC_PROT = 0,
++	DHD_PREALLOC_RXBUF,
++	DHD_PREALLOC_DATABUF,
++	DHD_PREALLOC_OSL_BUF,
++#if defined(STATIC_WL_PRIV_STRUCT)
++	DHD_PREALLOC_WIPHY_ESCAN0 = 5,
++#endif /* STATIC_WL_PRIV_STRUCT */
++	DHD_PREALLOC_DHD_INFO = 7,
++	DHD_PREALLOC_DHD_WLFC_INFO = 8,
++	DHD_PREALLOC_IF_FLOW_LKUP = 9,
++	/* 10 */
++	DHD_PREALLOC_MEMDUMP_RAM = 11,
++	DHD_PREALLOC_DHD_WLFC_HANGER = 12,
++	DHD_PREALLOC_PKTID_MAP = 13,
++	DHD_PREALLOC_PKTID_MAP_IOCTL = 14
++};
++
++enum dhd_dongledump_mode {
++	DUMP_DISABLED = 0,
++	DUMP_MEMONLY,
++	DUMP_MEMFILE,
++	DUMP_MEMFILE_BUGON,
++	DUMP_MEMFILE_MAX
++};
++
++enum dhd_dongledump_type {
++	DUMP_TYPE_RESUMED_ON_TIMEOUT = 1,
++	DUMP_TYPE_D3_ACK_TIMEOUT,
++	DUMP_TYPE_DONGLE_TRAP,
++	DUMP_TYPE_MEMORY_CORRUPTION,
++	DUMP_TYPE_PKTID_AUDIT_FAILURE,
++	DUMP_TYPE_SCAN_TIMEOUT
++};
++
++/* Packet alignment for most efficient SDIO (can change based on platform) */
++#ifndef DHD_SDALIGN
++#define DHD_SDALIGN	32
++#endif
++
++/*
++ * MAX_NVRAMBUF_SIZE determines the size of the Buffer in the DHD that holds
++ * the NVRAM data. That is the size of the buffer pointed by bus->vars
++ * This also needs to be increased to 16K to support NVRAM size higher than 8K
++ */
++#define MAX_NVRAMBUF_SIZE	(16 * 1024) /* max nvram buf size */
++#define MAX_CLM_BUF_SIZE	(48 * 1024) /* max clm blob size */
++
++#ifndef CONFIG_BCMDHD_CLM_PATH
++#define CONFIG_BCMDHD_CLM_PATH "/system/etc/wifi/bcmdhd_clm.blob"
++#endif /* CONFIG_BCMDHD_CLM_PATH */
++#define WL_CCODE_NULL_COUNTRY  "#n"
++
++
++/**
++ * DMA-able buffer parameters
++ * - dmaaddr_t is 32bits on a 32bit host.
++ *   dhd_dma_buf::pa may not be used as a sh_addr_t, bcm_addr64_t or uintptr
++ * - dhd_dma_buf::_alloced is ONLY for freeing a DMA-able buffer.
++ */
++typedef struct dhd_dma_buf {
++	void      *va;      /* virtual address of buffer */
++	uint32    len;      /* user requested buffer length */
++	dmaaddr_t pa;       /* physical address of buffer */
++	void      *dmah;    /* dma mapper handle */
++	void      *secdma;  /* secure dma sec_cma_info handle */
++	uint32    _alloced; /* actual size of buffer allocated with align and pad */
++} dhd_dma_buf_t;
++
++/* host reordering packts logic */
++/* followed the structure to hold the reorder buffers (void **p) */
++typedef struct reorder_info {
++	void **p;
++	uint8 flow_id;
++	uint8 cur_idx;
++	uint8 exp_idx;
++	uint8 max_idx;
++	uint8 pend_pkts;
++} reorder_info_t;
++
++#ifdef DHDTCPACK_SUPPRESS
++
++enum {
++	/* TCPACK suppress off */
++	TCPACK_SUP_OFF,
++	/* Replace TCPACK in txq when new coming one has higher ACK number. */
++	TCPACK_SUP_REPLACE,
++	/* TCPACK_SUP_REPLACE + delayed TCPACK TX unless ACK to PSH DATA.
++	 * This will give benefits to Half-Duplex bus interface(e.g. SDIO) that
++	 * 1. we are able to read TCP DATA packets first from the bus
++	 * 2. TCPACKs that don't need to hurry delivered remains longer in TXQ so can be suppressed.
++	 */
++	TCPACK_SUP_DELAYTX,
++	TCPACK_SUP_HOLD,
++	TCPACK_SUP_LAST_MODE
++};
++#endif /* DHDTCPACK_SUPPRESS */
++
++#if defined(TRAFFIC_MGMT_DWM)
++#define DHD_DWM_TBL_SIZE           57
++/* DSCP WMM AC Mapping macros and structures */
++#define DHD_TRF_MGMT_DWM_FILTER_BIT                 0x8
++#define DHD_TRF_MGMT_DWM_PRIO_BITS                  0x7
++#define DHD_TRF_MGMT_DWM_FAVORED_BIT                0x10
++#define DHD_TRF_MGMT_DWM_PRIO(dwm_tbl_entry) ((dwm_tbl_entry) & DHD_TRF_MGMT_DWM_PRIO_BITS)
++#define DHD_TRF_MGMT_DWM_IS_FAVORED_SET(dwm_tbl_entry) \
++	((dwm_tbl_entry) & DHD_TRF_MGMT_DWM_FAVORED_BIT)
++#define DHD_TRF_MGMT_DWM_SET_FAVORED(dwm_tbl_entry) \
++	((dwm_tbl_entry) |= DHD_TRF_MGMT_DWM_FAVORED_BIT)
++#define DHD_TRF_MGMT_DWM_IS_FILTER_SET(dwm_tbl_entry) \
++	((dwm_tbl_entry) & DHD_TRF_MGMT_DWM_FILTER_BIT)
++#define DHD_TRF_MGMT_DWM_SET_FILTER(dwm_tbl_entry) \
++	((dwm_tbl_entry) |= DHD_TRF_MGMT_DWM_FILTER_BIT)
++
++typedef struct {
++	uint8 dhd_dwm_enabled;
++	uint8 dhd_dwm_tbl[DHD_DWM_TBL_SIZE];
++} dhd_trf_mgmt_dwm_tbl_t;
++#endif 
++
++#define DHD_NULL_CHK_AND_RET(cond) \
++	if (!cond) { \
++		DHD_ERROR(("%s " #cond " is NULL\n", __FUNCTION__)); \
++		return; \
++	}
++
++#define DHD_NULL_CHK_AND_RET_VAL(cond, value) \
++	if (!cond) { \
++		DHD_ERROR(("%s " #cond " is NULL\n", __FUNCTION__)); \
++		return value; \
++	}
++
++#define DHD_NULL_CHK_AND_GOTO(cond, label) \
++	if (!cond) { \
++		DHD_ERROR(("%s " #cond " is NULL\n", __FUNCTION__)); \
++		goto label; \
++	}
++
++/*
++ * Accumulating the queue lengths of all flowring queues in a parent object,
++ * to assert flow control, when the cummulative queue length crosses an upper
++ * threshold defined on a parent object. Upper threshold may be maintained
++ * at a station level, at an interface level, or at a dhd instance.
++ *
++ * cumm_ctr_t abstraction:
++ * cumm_ctr_t abstraction may be enhanced to use an object with a hysterisis
++ * pause on/off threshold callback.
++ * All macros use the address of the cummulative length in the parent objects.
++ *
++ * BCM_GMAC3 builds use a single perimeter lock, as opposed to a per queue lock.
++ * Cummulative counters in parent objects may be updated without spinlocks.
++ *
++ * In non BCM_GMAC3, if a cummulative queue length is desired across all flows
++ * belonging to either of (a station, or an interface or a dhd instance), then
++ * an atomic operation is required using an atomic_t cummulative counters or
++ * using a spinlock. BCM_ROUTER_DHD uses the Linux atomic_t construct.
++ */
++
++/* Cummulative length not supported. */
++typedef uint32 cumm_ctr_t;
++#define DHD_CUMM_CTR_PTR(clen)     ((cumm_ctr_t*)(clen))
++#define DHD_CUMM_CTR(clen)         *(DHD_CUMM_CTR_PTR(clen)) /* accessor */
++#define DHD_CUMM_CTR_READ(clen)    DHD_CUMM_CTR(clen) /* read access */
++#define DHD_CUMM_CTR_INIT(clen)                                                \
++	ASSERT(DHD_CUMM_CTR_PTR(clen) != DHD_CUMM_CTR_PTR(NULL));
++#define DHD_CUMM_CTR_INCR(clen)                                                \
++	ASSERT(DHD_CUMM_CTR_PTR(clen) != DHD_CUMM_CTR_PTR(NULL));
++#define DHD_CUMM_CTR_DECR(clen)                                                \
++	ASSERT(DHD_CUMM_CTR_PTR(clen) != DHD_CUMM_CTR_PTR(NULL));
++
++/* DMA'ing r/w indices for rings supported */
++#ifdef BCM_INDX_TCM /* FW gets r/w indices in TCM */
++#define DMA_INDX_ENAB(dma_indxsup)	0
++#elif defined BCM_INDX_DMA  /* FW gets r/w indices from Host memory */
++#define DMA_INDX_ENAB(dma_indxsup)	1
++#else	/* r/w indices in TCM or host memory based on FW/Host agreement */
++#define DMA_INDX_ENAB(dma_indxsup)	dma_indxsup
++#endif	/* BCM_INDX_TCM */
++
++#if defined(WLTDLS) && defined(PCIE_FULL_DONGLE)
++struct tdls_peer_node {
++	uint8 addr[ETHER_ADDR_LEN];
++	struct tdls_peer_node *next;
++};
++typedef struct tdls_peer_node tdls_peer_node_t;
++typedef struct {
++	tdls_peer_node_t *node;
++	uint8 tdls_peer_count;
++} tdls_peer_tbl_t;
++#endif /* defined(WLTDLS) && defined(PCIE_FULL_DONGLE) */
++
++/* Common structure for module and instance linkage */
++typedef struct dhd_pub {
++	/* Linkage ponters */
++	osl_t *osh;		/* OSL handle */
++	struct dhd_bus *bus;	/* Bus module handle */
++	struct dhd_prot *prot;	/* Protocol module handle */
++	struct dhd_info  *info; /* Info module handle */
++	struct dhd_dbg *dbg;	/* Debugability module handle */
++
++	/* to NDIS developer, the structure dhd_common is redundant,
++	 * please do NOT merge it back from other branches !!!
++	 */
++
++#ifdef BCMDBUS
++	struct dbus_pub *dbus;
++#endif
++
++	/* Internal dhd items */
++	bool up;		/* Driver up/down (to OS) */
++	bool txoff;		/* Transmit flow-controlled */
++	bool dongle_reset;  /* TRUE = DEVRESET put dongle into reset */
++	enum dhd_bus_state busstate;
++	uint dhd_bus_busy_state;	/* Bus busy state */
++	uint hdrlen;		/* Total DHD header length (proto + bus) */
++	uint maxctl;		/* Max size rxctl request from proto to bus */
++	uint rxsz;		/* Rx buffer size bus module should use */
++	uint8 wme_dp;	/* wme discard priority */
++
++	/* Dongle media info */
++	bool iswl;		/* Dongle-resident driver is wl */
++	ulong drv_version;	/* Version of dongle-resident driver */
++	struct ether_addr mac;	/* MAC address obtained from dongle */
++	dngl_stats_t dstats;	/* Stats for dongle-based data */
++
++	/* Additional stats for the bus level */
++	ulong tx_packets;	/* Data packets sent to dongle */
++	ulong tx_dropped;	/* Data packets dropped in dhd */
++	ulong tx_multicast;	/* Multicast data packets sent to dongle */
++	ulong tx_errors;	/* Errors in sending data to dongle */
++	ulong tx_ctlpkts;	/* Control packets sent to dongle */
++	ulong tx_ctlerrs;	/* Errors sending control frames to dongle */
++	ulong rx_packets;	/* Packets sent up the network interface */
++	ulong rx_multicast;	/* Multicast packets sent up the network interface */
++	ulong rx_errors;	/* Errors processing rx data packets */
++	ulong rx_ctlpkts;	/* Control frames processed from dongle */
++	ulong rx_ctlerrs;	/* Errors in processing rx control frames */
++	ulong rx_dropped;	/* Packets dropped locally (no memory) */
++	ulong rx_flushed;  /* Packets flushed due to unscheduled sendup thread */
++	ulong wd_dpc_sched;   /* Number of times dhd dpc scheduled by watchdog timer */
++	ulong rx_pktgetfail; /* Number of PKTGET failures in DHD on RX */
++	ulong tx_pktgetfail; /* Number of PKTGET failures in DHD on TX */
++	ulong rx_readahead_cnt;	/* Number of packets where header read-ahead was used. */
++	ulong tx_realloc;	/* Number of tx packets we had to realloc for headroom */
++	ulong fc_packets;       /* Number of flow control pkts recvd */
++
++	/* Last error return */
++	int bcmerror;
++	uint tickcnt;
++
++	/* Last error from dongle */
++	int dongle_error;
++
++	uint8 country_code[WLC_CNTRY_BUF_SZ];
++
++	/* Suspend disable flag and "in suspend" flag */
++	int suspend_disable_flag; /* "1" to disable all extra powersaving during suspend */
++	int in_suspend;			/* flag set to 1 when early suspend called */
++#ifdef PNO_SUPPORT
++	int pno_enable;			/* pno status : "1" is pno enable */
++	int pno_suspend;		/* pno suspend status : "1" is pno suspended */
++#endif /* PNO_SUPPORT */
++	/* DTIM skip value, default 0(or 1) means wake each DTIM
++	 * 3 means skip 2 DTIMs and wake up 3rd DTIM(9th beacon when AP DTIM is 3)
++	 */
++	int suspend_bcn_li_dtim;         /* bcn_li_dtim value in suspend mode */
++#ifdef PKT_FILTER_SUPPORT
++	int early_suspended;	/* Early suspend status */
++	int dhcp_in_progress;	/* DHCP period */
++#endif
++
++	/* Pkt filter defination */
++	char * pktfilter[100];
++	int pktfilter_count;
++
++	wl_country_t dhd_cspec;		/* Current Locale info */
++#if defined(CUSTOM_COUNTRY_CODE) || defined(CUSTOM_FORCE_NODFS_FLAG)
++	u32 dhd_cflags;
++#endif /* CUSTOM_COUNTRY_CODE || CUSTOM_FORCE_NODFS_FLAG */
++	bool force_country_change;
++	char eventmask[WL_EVENTING_MASK_LEN];
++	int	op_mode;				/* STA, HostAPD, WFD, SoftAP */
++
++/* Set this to 1 to use a seperate interface (p2p0) for p2p operations.
++ *  For ICS MR1 releases it should be disable to be compatable with ICS MR1 Framework
++ *  see target dhd-cdc-sdmmc-panda-cfg80211-icsmr1-gpl-debug in Makefile
++ */
++/* #define WL_ENABLE_P2P_IF		1 */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	struct mutex 	wl_start_stop_lock; /* lock/unlock for Android start/stop */
++	struct mutex 	wl_softap_lock;		 /* lock/unlock for any SoftAP/STA settings */
++#endif 
++
++#ifdef PROP_TXSTATUS
++	bool	wlfc_enabled;
++	int	wlfc_mode;
++	void*	wlfc_state;
++	/*
++	Mode in which the dhd flow control shall operate. Must be set before
++	traffic starts to the device.
++	0 - Do not do any proptxtstatus flow control
++	1 - Use implied credit from a packet status
++	2 - Use explicit credit
++	3 - Only AMPDU hostreorder used. no wlfc.
++	*/
++	uint8	proptxstatus_mode;
++	bool	proptxstatus_txoff;
++	bool	proptxstatus_module_ignore;
++	bool	proptxstatus_credit_ignore;
++	bool	proptxstatus_txstatus_ignore;
++
++	bool	wlfc_rxpkt_chk;
++#ifdef LIMIT_BORROW
++	bool	wlfc_borrow_allowed;
++#endif /* LIMIT_BORROW */
++	/*
++	 * implement below functions in each platform if needed.
++	 */
++	/* platform specific function whether to skip flow control */
++	bool (*skip_fc)(void);
++	/* platform specific function for wlfc_enable and wlfc_deinit */
++	void (*plat_init)(void *dhd);
++	void (*plat_deinit)(void *dhd);
++#ifdef DHD_WLFC_THREAD
++	bool                wlfc_thread_go;
++	struct task_struct* wlfc_thread;
++	wait_queue_head_t   wlfc_wqhead;
++#endif /* DHD_WLFC_THREAD */
++#endif /* PROP_TXSTATUS */
++#ifdef PNO_SUPPORT
++	void *pno_state;
++#endif
++#ifdef RTT_SUPPORT
++	void *rtt_state;
++#endif
++	bool	dongle_isolation;
++	bool	dongle_trap_occured;	/* flag for sending HANG event to upper layer */
++	int   hang_was_sent;
++	int   rxcnt_timeout;		/* counter rxcnt timeout to send HANG */
++	int   txcnt_timeout;		/* counter txcnt timeout to send HANG */
++#ifdef BCMPCIE
++	int   d3ackcnt_timeout;		/* counter d3ack timeout to send HANG */
++#endif /* BCMPCIE */
++	bool hang_report;		/* enable hang report by default */
++#ifdef WLMEDIA_HTSF
++	uint8 htsfdlystat_sz; /* Size of delay stats, max 255B */
++#endif
++#ifdef WLTDLS
++	bool tdls_enable;
++#endif
++	struct reorder_info *reorder_bufs[WLHOST_REORDERDATA_MAXFLOWS];
++	#define WLC_IOCTL_MAXBUF_FWCAP	512
++	char  fw_capabilities[WLC_IOCTL_MAXBUF_FWCAP];
++	#define MAXSKBPEND 1024
++	void *skbbuf[MAXSKBPEND];
++	uint32 store_idx;
++	uint32 sent_idx;
++#ifdef DHDTCPACK_SUPPRESS
++	uint8 tcpack_sup_mode;		/* TCPACK suppress mode */
++	void *tcpack_sup_module;	/* TCPACK suppress module */
++	uint32 tcpack_sup_ratio;
++	uint32 tcpack_sup_delay;
++#endif /* DHDTCPACK_SUPPRESS */
++#if defined(ARP_OFFLOAD_SUPPORT)
++	uint32 arp_version;
++#endif
++#ifdef CUSTOM_SET_CPUCORE
++	struct task_struct * current_dpc;
++	struct task_struct * current_rxf;
++	int chan_isvht80;
++#endif /* CUSTOM_SET_CPUCORE */
++
++
++	void    *sta_pool;          /* pre-allocated pool of sta objects */
++	void    *staid_allocator;   /* allocator of sta indexes */
++#ifdef PCIE_FULL_DONGLE
++	bool	flow_rings_inited;	/* set this flag after initializing flow rings */
++#endif /* PCIE_FULL_DONGLE */
++	void    *flowid_allocator;  /* unique flowid allocator */
++	void	*flow_ring_table;   /* flow ring table, include prot and bus info */
++	void	*if_flow_lkup;      /* per interface flowid lkup hash table */
++	void    *flowid_lock;       /* per os lock for flowid info protection */
++	void    *flowring_list_lock;       /* per os lock for flowring list protection */
++	uint32  num_flow_rings;
++	cumm_ctr_t cumm_ctr;        /* cumm queue length placeholder  */
++	cumm_ctr_t l2cumm_ctr;      /* level 2 cumm queue length placeholder */
++	uint32 d2h_sync_mode;       /* D2H DMA completion sync mode */
++	uint8  flow_prio_map[NUMPRIO];
++	uint8	flow_prio_map_type;
++	char enable_log[MAX_EVENT];
++	bool dma_d2h_ring_upd_support;
++	bool dma_h2d_ring_upd_support;
++
++#ifdef DHD_WMF
++	bool wmf_ucast_igmp;
++#ifdef DHD_IGMP_UCQUERY
++	bool wmf_ucast_igmp_query;
++#endif
++#ifdef DHD_UCAST_UPNP
++	bool wmf_ucast_upnp;
++#endif
++#endif /* DHD_WMF */
++#if defined(TRAFFIC_MGMT_DWM)
++	dhd_trf_mgmt_dwm_tbl_t dhd_tm_dwm_tbl;
++#endif 
++#ifdef DHD_L2_FILTER
++	unsigned long l2_filter_cnt;	/* for L2_FILTER ARP table timeout */
++#endif /* DHD_L2_FILTER */
++	uint8 *soc_ram;
++	uint32 soc_ram_length;
++	uint32 memdump_type;
++#ifdef DHD_FW_COREDUMP
++	uint32 memdump_enabled;
++#endif /* DHD_FW_COREDUMP */
++#ifdef PCIE_FULL_DONGLE
++#ifdef WLTDLS
++	tdls_peer_tbl_t peer_tbl;
++#endif /* WLTDLS */
++	uint8 tx_in_progress;
++#endif /* PCIE_FULL_DONGLE */
++#ifdef DHD_ULP
++	void *dhd_ulp;
++#endif
++#ifdef CACHE_FW_IMAGES
++	char	*cached_fw;
++	int	cached_fw_length;
++	char	*cached_nvram;
++	int	cached_nvram_length;
++#endif
++#ifdef WLTDLS
++	uint32 tdls_mode;
++#endif
++#ifdef DHD_LOSSLESS_ROAMING
++	uint8 dequeue_prec_map;
++#endif
++#ifdef GSCAN_SUPPORT
++	bool lazy_roam_enable;
++#endif
++	uint8 rand_mac_oui[DOT11_OUI_LEN];
++	void *macdbg_info;
++#ifdef DHD_WET
++	void *wet_info;
++#endif
++} dhd_pub_t;
++
++#if defined(PCIE_FULL_DONGLE)
++
++/* Packet Tag for PCIE Full Dongle DHD */
++typedef struct dhd_pkttag_fd {
++	uint16    flowid;   /* Flowring Id */
++	uint16    dataoff;  /* start of packet */
++	uint16    dma_len;  /* pkt len for DMA_MAP/UNMAP */
++	dmaaddr_t pa;       /* physical address */
++	void      *dmah;    /* dma mapper handle */
++	void      *secdma; /* secure dma sec_cma_info handle */
++} dhd_pkttag_fd_t;
++
++/* Packet Tag for DHD PCIE Full Dongle */
++#define DHD_PKTTAG_FD(pkt)          ((dhd_pkttag_fd_t *)(PKTTAG(pkt)))
++
++#define DHD_PKT_GET_FLOWID(pkt)     ((DHD_PKTTAG_FD(pkt))->flowid)
++#define DHD_PKT_SET_FLOWID(pkt, pkt_flowid) \
++	DHD_PKTTAG_FD(pkt)->flowid = (uint16)(pkt_flowid)
++
++#define DHD_PKT_GET_DATAOFF(pkt)    ((DHD_PKTTAG_FD(pkt))->dataoff)
++#define DHD_PKT_SET_DATAOFF(pkt, pkt_dataoff) \
++	DHD_PKTTAG_FD(pkt)->dataoff = (uint16)(pkt_dataoff)
++
++#define DHD_PKT_GET_DMA_LEN(pkt)    ((DHD_PKTTAG_FD(pkt))->dma_len)
++#define DHD_PKT_SET_DMA_LEN(pkt, pkt_dma_len) \
++	DHD_PKTTAG_FD(pkt)->dma_len = (uint16)(pkt_dma_len)
++
++#define DHD_PKT_GET_PA(pkt)         ((DHD_PKTTAG_FD(pkt))->pa)
++#define DHD_PKT_SET_PA(pkt, pkt_pa) \
++	DHD_PKTTAG_FD(pkt)->pa = (dmaaddr_t)(pkt_pa)
++
++#define DHD_PKT_GET_DMAH(pkt)       ((DHD_PKTTAG_FD(pkt))->dmah)
++#define DHD_PKT_SET_DMAH(pkt, pkt_dmah) \
++	DHD_PKTTAG_FD(pkt)->dmah = (void *)(pkt_dmah)
++
++#define DHD_PKT_GET_SECDMA(pkt)    ((DHD_PKTTAG_FD(pkt))->secdma)
++#define DHD_PKT_SET_SECDMA(pkt, pkt_secdma) \
++	DHD_PKTTAG_FD(pkt)->secdma = (void *)(pkt_secdma)
++#endif /* PCIE_FULL_DONGLE */
++
++#if defined(BCMWDF)
++typedef struct {
++	dhd_pub_t *dhd_pub;
++} dhd_workitem_context_t;
++
++WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(dhd_workitem_context_t, dhd_get_dhd_workitem_context)
++#endif /* (BCMWDF)  */
++
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_PM_SLEEP)
++
++	#define DHD_PM_RESUME_WAIT_INIT(a) DECLARE_WAIT_QUEUE_HEAD(a);
++	#define _DHD_PM_RESUME_WAIT(a, b) do {\
++			int retry = 0; \
++			SMP_RD_BARRIER_DEPENDS(); \
++			while (dhd_mmc_suspend && retry++ != b) { \
++				SMP_RD_BARRIER_DEPENDS(); \
++				wait_event_interruptible_timeout(a, !dhd_mmc_suspend, 1); \
++			} \
++		} 	while (0)
++	#define DHD_PM_RESUME_WAIT(a) 		_DHD_PM_RESUME_WAIT(a, 200)
++	#define DHD_PM_RESUME_WAIT_FOREVER(a) 	_DHD_PM_RESUME_WAIT(a, ~0)
++	#ifdef CUSTOMER_HW4
++		#define DHD_PM_RESUME_RETURN_ERROR(a)   do { \
++				if (dhd_mmc_suspend) { \
++					printf("%s[%d]: mmc is still in suspend state!!!\n", \
++							__FUNCTION__, __LINE__); \
++					return a; \
++				} \
++			} while (0)
++	#else
++		#define DHD_PM_RESUME_RETURN_ERROR(a)	do { \
++			if (dhd_mmc_suspend) return a; } while (0)
++	#endif 
++	#define DHD_PM_RESUME_RETURN		do { if (dhd_mmc_suspend) return; } while (0)
++
++	#define DHD_SPINWAIT_SLEEP_INIT(a) DECLARE_WAIT_QUEUE_HEAD(a);
++	#define SPINWAIT_SLEEP(a, exp, us) do { \
++		uint countdown = (us) + 9999; \
++		while ((exp) && (countdown >= 10000)) { \
++			wait_event_interruptible_timeout(a, FALSE, 1); \
++			countdown -= 10000; \
++		} \
++	} while (0)
++
++	#else
++
++	#define DHD_PM_RESUME_WAIT_INIT(a)
++	#define DHD_PM_RESUME_WAIT(a)
++	#define DHD_PM_RESUME_WAIT_FOREVER(a)
++	#define DHD_PM_RESUME_RETURN_ERROR(a)
++	#define DHD_PM_RESUME_RETURN
++
++	#define DHD_SPINWAIT_SLEEP_INIT(a)
++	#define SPINWAIT_SLEEP(a, exp, us)  do { \
++		uint countdown = (us) + 9; \
++		while ((exp) && (countdown >= 10)) { \
++			OSL_DELAY(10);  \
++			countdown -= 10;  \
++		} \
++	} while (0)
++
++	#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_PM_SLEEP) */
++
++#ifndef OSL_SLEEP
++#define OSL_SLEEP(ms)		OSL_DELAY(ms*1000)
++#endif /* OSL_SLEEP */
++
++#define DHD_IF_VIF	0x01	/* Virtual IF (Hidden from user) */
++
++#ifdef PNO_SUPPORT
++int dhd_pno_clean(dhd_pub_t *dhd);
++#endif /* PNO_SUPPORT */
++/*
++ *  Wake locks are an Android power management concept. They are used by applications and services
++ *  to request CPU resources.
++ */
++extern int dhd_os_wake_lock(dhd_pub_t *pub);
++extern int dhd_os_wake_unlock(dhd_pub_t *pub);
++extern int dhd_os_wake_lock_timeout(dhd_pub_t *pub);
++extern int dhd_os_wake_lock_rx_timeout_enable(dhd_pub_t *pub, int val);
++extern int dhd_os_wake_lock_ctrl_timeout_enable(dhd_pub_t *pub, int val);
++extern int dhd_os_wake_lock_ctrl_timeout_cancel(dhd_pub_t *pub);
++extern int dhd_os_wd_wake_lock(dhd_pub_t *pub);
++extern int dhd_os_wd_wake_unlock(dhd_pub_t *pub);
++extern int dhd_os_wake_lock_waive(dhd_pub_t *pub);
++extern int dhd_os_wake_lock_restore(dhd_pub_t *pub);
++#ifdef BCMPCIE_OOB_HOST_WAKE
++extern void dhd_os_oob_irq_wake_lock_timeout(dhd_pub_t *pub, int val);
++extern void dhd_os_oob_irq_wake_unlock(dhd_pub_t *pub);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#ifdef DHD_USE_SCAN_WAKELOCK
++extern void dhd_os_scan_wake_lock_timeout(dhd_pub_t *pub, int val);
++extern void dhd_os_scan_wake_unlock(dhd_pub_t *pub);
++#endif /* BCMPCIE_SCAN_WAKELOCK */
++
++inline static void MUTEX_LOCK_SOFTAP_SET_INIT(dhd_pub_t * dhdp)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	mutex_init(&dhdp->wl_softap_lock);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
++}
++
++inline static void MUTEX_LOCK_SOFTAP_SET(dhd_pub_t * dhdp)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	mutex_lock(&dhdp->wl_softap_lock);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
++}
++
++inline static void MUTEX_UNLOCK_SOFTAP_SET(dhd_pub_t * dhdp)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	mutex_unlock(&dhdp->wl_softap_lock);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
++}
++
++#define DHD_OS_WAKE_LOCK(pub)			dhd_os_wake_lock(pub)
++#define DHD_OS_WAKE_UNLOCK(pub)		dhd_os_wake_unlock(pub)
++#define DHD_OS_WAKE_LOCK_TIMEOUT(pub)		dhd_os_wake_lock_timeout(pub)
++#define DHD_OS_WAKE_LOCK_RX_TIMEOUT_ENABLE(pub, val) \
++	dhd_os_wake_lock_rx_timeout_enable(pub, val)
++#define DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_ENABLE(pub, val) \
++	dhd_os_wake_lock_ctrl_timeout_enable(pub, val)
++#define DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_CANCEL(pub) \
++	dhd_os_wake_lock_ctrl_timeout_cancel(pub)
++#define DHD_OS_WAKE_LOCK_WAIVE(pub)			dhd_os_wake_lock_waive(pub)
++#define DHD_OS_WAKE_LOCK_RESTORE(pub)		dhd_os_wake_lock_restore(pub)
++
++#define DHD_OS_WD_WAKE_LOCK(pub)		dhd_os_wd_wake_lock(pub)
++#define DHD_OS_WD_WAKE_UNLOCK(pub)		dhd_os_wd_wake_unlock(pub)
++
++#ifdef BCMPCIE_OOB_HOST_WAKE
++#define OOB_WAKE_LOCK_TIMEOUT 500
++#define DHD_OS_OOB_IRQ_WAKE_LOCK_TIMEOUT(pub, val)	dhd_os_oob_irq_wake_lock_timeout(pub, val)
++#define DHD_OS_OOB_IRQ_WAKE_UNLOCK(pub)			dhd_os_oob_irq_wake_unlock(pub)
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#ifdef DHD_USE_SCAN_WAKELOCK
++#ifdef DHD_DEBUG_SCAN_WAKELOCK
++#define DHD_OS_SCAN_WAKE_LOCK_TIMEOUT(pub, val) \
++	do { \
++		printf("call wake_lock_scan: %s %d\n", \
++			__FUNCTION__, __LINE__); \
++		dhd_os_scan_wake_lock_timeout(pub, val); \
++	} while (0)
++#define DHD_OS_SCAN_WAKE_UNLOCK(pub) \
++	do { \
++		printf("call wake_unlock_scan: %s %d\n", \
++			__FUNCTION__, __LINE__); \
++		dhd_os_scan_wake_unlock(pub); \
++	} while (0)
++#else
++#define DHD_OS_SCAN_WAKE_LOCK_TIMEOUT(pub, val)		dhd_os_scan_wake_lock_timeout(pub, val)
++#define DHD_OS_SCAN_WAKE_UNLOCK(pub)			dhd_os_scan_wake_unlock(pub)
++#endif /* DHD_DEBUG_SCAN_WAKELOCK */
++#else
++#define DHD_OS_SCAN_WAKE_LOCK_TIMEOUT(pub, val)
++#define DHD_OS_SCAN_WAKE_UNLOCK(pub)
++#endif /* DHD_USE_SCAN_WAKELOCK */
++#define DHD_PACKET_TIMEOUT_MS	500
++#define DHD_EVENT_TIMEOUT_MS	1500
++#define SCAN_WAKE_LOCK_TIMEOUT	10000
++
++/* Enum for IOCTL recieved status */
++typedef enum dhd_ioctl_recieved_status
++{
++	IOCTL_WAIT = 0,
++	IOCTL_RETURN_ON_SUCCESS,
++	IOCTL_RETURN_ON_TRAP,
++	IOCTL_RETURN_ON_BUS_STOP
++} dhd_ioctl_recieved_status_t;
++
++/* interface operations (register, remove) should be atomic, use this lock to prevent race
++ * condition among wifi on/off and interface operation functions
++ */
++void dhd_net_if_lock(struct net_device *dev);
++void dhd_net_if_unlock(struct net_device *dev);
++
++
++typedef enum dhd_attach_states
++{
++	DHD_ATTACH_STATE_INIT = 0x0,
++	DHD_ATTACH_STATE_NET_ALLOC = 0x1,
++	DHD_ATTACH_STATE_DHD_ALLOC = 0x2,
++	DHD_ATTACH_STATE_ADD_IF = 0x4,
++	DHD_ATTACH_STATE_PROT_ATTACH = 0x8,
++	DHD_ATTACH_STATE_WL_ATTACH = 0x10,
++	DHD_ATTACH_STATE_THREADS_CREATED = 0x20,
++	DHD_ATTACH_STATE_WAKELOCKS_INIT = 0x40,
++	DHD_ATTACH_STATE_CFG80211 = 0x80,
++	DHD_ATTACH_STATE_EARLYSUSPEND_DONE = 0x100,
++	DHD_ATTACH_STATE_DONE = 0x200
++} dhd_attach_states_t;
++
++/* Value -1 means we are unsuccessful in creating the kthread. */
++#define DHD_PID_KT_INVALID 	-1
++/* Value -2 means we are unsuccessful in both creating the kthread and tasklet */
++#define DHD_PID_KT_TL_INVALID	-2
++
++/*
++ * Exported from dhd OS modules (dhd_linux/dhd_ndis)
++ */
++
++/* Indication from bus module regarding presence/insertion of dongle.
++ * Return dhd_pub_t pointer, used as handle to OS module in later calls.
++ * Returned structure should have bus and prot pointers filled in.
++ * bus_hdrlen specifies required headroom for bus module header.
++ */
++extern dhd_pub_t *dhd_attach(osl_t *osh, struct dhd_bus *bus, uint bus_hdrlen);
++#if defined(WLP2P) && defined(WL_CFG80211)
++/* To allow attach/detach calls corresponding to p2p0 interface  */
++extern int dhd_attach_p2p(dhd_pub_t *);
++extern int dhd_detach_p2p(dhd_pub_t *);
++#endif /* WLP2P && WL_CFG80211 */
++extern int dhd_register_if(dhd_pub_t *dhdp, int idx, bool need_rtnl_lock);
++
++/* Indication from bus module regarding removal/absence of dongle */
++extern void dhd_detach(dhd_pub_t *dhdp);
++extern void dhd_free(dhd_pub_t *dhdp);
++extern void dhd_clear(dhd_pub_t *dhdp);
++
++/* Indication from bus module to change flow-control state */
++extern void dhd_txflowcontrol(dhd_pub_t *dhdp, int ifidx, bool on);
++
++/* Store the status of a connection attempt for later retrieval by an iovar */
++extern void dhd_store_conn_status(uint32 event, uint32 status, uint32 reason);
++
++extern bool dhd_prec_enq(dhd_pub_t *dhdp, struct pktq *q, void *pkt, int prec);
++
++/* Receive frame for delivery to OS.  Callee disposes of rxp. */
++extern void dhd_rx_frame(dhd_pub_t *dhdp, int ifidx, void *rxp, int numpkt, uint8 chan);
++
++/* Return pointer to interface name */
++extern char *dhd_ifname(dhd_pub_t *dhdp, int idx);
++
++/* Request scheduling of the bus dpc */
++extern void dhd_sched_dpc(dhd_pub_t *dhdp);
++
++/* Notify tx completion */
++extern void dhd_txcomplete(dhd_pub_t *dhdp, void *txp, bool success);
++extern void dhd_dpc_enable(dhd_pub_t *dhdp);
++
++#define WIFI_FEATURE_INFRA              0x0001      /* Basic infrastructure mode        */
++#define WIFI_FEATURE_INFRA_5G           0x0002      /* Support for 5 GHz Band           */
++#define WIFI_FEATURE_HOTSPOT            0x0004      /* Support for GAS/ANQP             */
++#define WIFI_FEATURE_P2P                0x0008      /* Wifi-Direct                      */
++#define WIFI_FEATURE_SOFT_AP            0x0010      /* Soft AP                          */
++#define WIFI_FEATURE_GSCAN              0x0020      /* Google-Scan APIs                 */
++#define WIFI_FEATURE_NAN                0x0040      /* Neighbor Awareness Networking    */
++#define WIFI_FEATURE_D2D_RTT            0x0080      /* Device-to-device RTT             */
++#define WIFI_FEATURE_D2AP_RTT           0x0100      /* Device-to-AP RTT                 */
++#define WIFI_FEATURE_BATCH_SCAN         0x0200      /* Batched Scan (legacy)            */
++#define WIFI_FEATURE_PNO                0x0400      /* Preferred network offload        */
++#define WIFI_FEATURE_ADDITIONAL_STA     0x0800      /* Support for two STAs             */
++#define WIFI_FEATURE_TDLS               0x1000      /* Tunnel directed link setup       */
++#define WIFI_FEATURE_TDLS_OFFCHANNEL    0x2000      /* Support for TDLS off channel     */
++#define WIFI_FEATURE_EPR                0x4000      /* Enhanced power reporting         */
++#define WIFI_FEATURE_AP_STA             0x8000      /* Support for AP STA Concurrency   */
++#define WIFI_FEATURE_LINKSTAT           0x10000     /* Support for Linkstats            */
++#define WIFI_FEATURE_HAL_EPNO           0x40000     /* WiFi PNO enhanced                */
++#define WIFI_FEATURE_RSSI_MONITOR       0x80000     /* RSSI Monitor                     */
++
++#define MAX_FEATURE_SET_CONCURRRENT_GROUPS  3
++
++extern int dhd_dev_get_feature_set(struct net_device *dev);
++extern int *dhd_dev_get_feature_set_matrix(struct net_device *dev, int *num);
++#ifdef CUSTOM_FORCE_NODFS_FLAG
++extern int dhd_dev_set_nodfs(struct net_device *dev, uint nodfs);
++#endif /* CUSTOM_FORCE_NODFS_FLAG */
++extern int dhd_dev_cfg_rand_mac_oui(struct net_device *dev, uint8 *oui);
++extern int dhd_set_rand_mac_oui(dhd_pub_t *dhd);
++
++#ifdef GSCAN_SUPPORT
++extern int dhd_dev_set_lazy_roam_cfg(struct net_device *dev,
++             wlc_roam_exp_params_t *roam_param);
++extern int dhd_dev_lazy_roam_enable(struct net_device *dev, uint32 enable);
++extern int dhd_dev_set_lazy_roam_bssid_pref(struct net_device *dev,
++       wl_bssid_pref_cfg_t *bssid_pref, uint32 flush);
++extern int dhd_dev_set_blacklist_bssid(struct net_device *dev, maclist_t *blacklist,
++    uint32 len, uint32 flush);
++extern int dhd_dev_set_whitelist_ssid(struct net_device *dev, wl_ssid_whitelist_t *whitelist,
++    uint32 len, uint32 flush);
++#endif /* GSCAN_SUPPORT */
++
++extern int dhd_dev_set_rssi_monitor_cfg(struct net_device *dev, int start,
++             int8 max_rssi, int8 min_rssi);
++
++#define DHD_RSSI_MONITOR_EVT_VERSION   1
++typedef struct {
++	uint8 version;
++	int8 cur_rssi;
++	struct ether_addr BSSID;
++} dhd_rssi_monitor_evt_t;
++
++/* OS independent layer functions */
++extern int dhd_os_proto_block(dhd_pub_t * pub);
++extern int dhd_os_proto_unblock(dhd_pub_t * pub);
++extern int dhd_os_ioctl_resp_wait(dhd_pub_t * pub, uint * condition);
++extern int dhd_os_ioctl_resp_wake(dhd_pub_t * pub);
++extern unsigned int dhd_os_get_ioctl_resp_timeout(void);
++extern void dhd_os_set_ioctl_resp_timeout(unsigned int timeout_msec);
++extern void dhd_os_ioctl_resp_lock(dhd_pub_t * pub);
++extern void dhd_os_ioctl_resp_unlock(dhd_pub_t * pub);
++extern void dhd_wakeup_ioctl_event(dhd_pub_t *pub, dhd_ioctl_recieved_status_t reason);
++
++#define DHD_OS_IOCTL_RESP_LOCK(x)
++#define DHD_OS_IOCTL_RESP_UNLOCK(x)
++
++
++extern int dhd_os_get_image_block(char * buf, int len, void * image);
++extern void * dhd_os_open_image(char * filename);
++extern void dhd_os_close_image(void * image);
++extern void dhd_os_wd_timer(void *bus, uint wdtick);
++extern void dhd_os_sdlock(dhd_pub_t * pub);
++extern void dhd_os_sdunlock(dhd_pub_t * pub);
++extern void dhd_os_sdlock_txq(dhd_pub_t * pub);
++extern void dhd_os_sdunlock_txq(dhd_pub_t * pub);
++extern void dhd_os_sdlock_rxq(dhd_pub_t * pub);
++extern void dhd_os_sdunlock_rxq(dhd_pub_t * pub);
++extern void dhd_os_sdlock_sndup_rxq(dhd_pub_t * pub);
++#ifdef DHDTCPACK_SUPPRESS
++extern unsigned long dhd_os_tcpacklock(dhd_pub_t *pub);
++extern void dhd_os_tcpackunlock(dhd_pub_t *pub, unsigned long flags);
++#endif /* DHDTCPACK_SUPPRESS */
++
++extern int dhd_customer_oob_irq_map(void *adapter, unsigned long *irq_flags_ptr);
++extern int dhd_customer_gpio_wlan_ctrl(void *adapter, int onoff);
++extern int dhd_custom_get_mac_address(void *adapter, unsigned char *buf);
++#ifdef CUSTOM_COUNTRY_CODE
++extern void get_customized_country_code(void *adapter, char *country_iso_code,
++wl_country_t *cspec, u32 flags);
++#else
++extern void get_customized_country_code(void *adapter, char *country_iso_code, wl_country_t *cspec);
++#endif /* CUSTOM_COUNTRY_CODE */
++extern void dhd_os_sdunlock_sndup_rxq(dhd_pub_t * pub);
++extern void dhd_os_sdlock_eventq(dhd_pub_t * pub);
++extern void dhd_os_sdunlock_eventq(dhd_pub_t * pub);
++extern bool dhd_os_check_hang(dhd_pub_t *dhdp, int ifidx, int ret);
++extern int dhd_os_send_hang_message(dhd_pub_t *dhdp);
++extern void dhd_set_version_info(dhd_pub_t *pub, char *fw);
++extern bool dhd_os_check_if_up(dhd_pub_t *pub);
++extern int dhd_os_check_wakelock(dhd_pub_t *pub);
++extern int dhd_os_check_wakelock_all(dhd_pub_t *pub);
++extern int dhd_get_instance(dhd_pub_t *pub);
++#ifdef CUSTOM_SET_CPUCORE
++extern void dhd_set_cpucore(dhd_pub_t *dhd, int set);
++#endif /* CUSTOM_SET_CPUCORE */
++
++#if defined(KEEP_ALIVE)
++extern int dhd_keep_alive_onoff(dhd_pub_t *dhd);
++#endif /* KEEP_ALIVE */
++
++#ifdef SUPPORT_AP_POWERSAVE
++extern int dhd_set_ap_powersave(dhd_pub_t *dhdp, int ifidx, int enable);
++#endif
++
++#if defined(DHD_FW_COREDUMP)
++void dhd_schedule_memdump(dhd_pub_t *dhdp, uint8 *buf, uint32 size);
++#endif /* DHD_FW_COREDUMP */
++
++#ifdef SUPPORT_AP_POWERSAVE
++extern int dhd_set_ap_powersave(dhd_pub_t *dhdp, int ifidx, int enable);
++#endif /* SUPPORT_AP_POWERSAVE */
++
++
++#ifdef PKT_FILTER_SUPPORT
++#define DHD_UNICAST_FILTER_NUM		0
++#define DHD_BROADCAST_FILTER_NUM	1
++#define DHD_MULTICAST4_FILTER_NUM	2
++#define DHD_MULTICAST6_FILTER_NUM	3
++#define DHD_MDNS_FILTER_NUM		4
++#define DHD_ARP_FILTER_NUM		5
++extern int 	dhd_os_enable_packet_filter(dhd_pub_t *dhdp, int val);
++extern void dhd_enable_packet_filter(int value, dhd_pub_t *dhd);
++extern int net_os_enable_packet_filter(struct net_device *dev, int val);
++extern int net_os_rxfilter_add_remove(struct net_device *dev, int val, int num);
++#endif /* PKT_FILTER_SUPPORT */
++
++extern int dhd_get_suspend_bcn_li_dtim(dhd_pub_t *dhd);
++extern bool dhd_support_sta_mode(dhd_pub_t *dhd);
++
++extern int write_to_file(dhd_pub_t *dhd, uint8 *buf, int size);
++typedef struct {
++	uint32 limit;		/* Expiration time (usec) */
++	uint32 increment;	/* Current expiration increment (usec) */
++	uint32 elapsed;		/* Current elapsed time (usec) */
++	uint32 tick;		/* O/S tick time (usec) */
++} dhd_timeout_t;
++
++#ifdef SHOW_LOGTRACE
++typedef struct {
++	int  num_fmts;
++	char **fmts;
++	char *raw_fmts;
++	char *raw_sstr;
++	uint32 ramstart;
++	uint32 rodata_start;
++	uint32 rodata_end;
++	char *rom_raw_sstr;
++	uint32 rom_ramstart;
++	uint32 rom_rodata_start;
++	uint32 rom_rodata_end;
++} dhd_event_log_t;
++#endif /* SHOW_LOGTRACE */
++
++#if defined(KEEP_ALIVE)
++extern int dhd_dev_start_mkeep_alive(dhd_pub_t *dhd_pub, u8 mkeep_alive_id, u8 *ip_pkt,
++	u16 ip_pkt_len, u8* src_mac_addr, u8* dst_mac_addr, u32 period_msec);
++extern int dhd_dev_stop_mkeep_alive(dhd_pub_t *dhd_pub, u8 mkeep_alive_id);
++#endif /* defined(KEEP_ALIVE) */
++
++extern void dhd_timeout_start(dhd_timeout_t *tmo, uint usec);
++extern int dhd_timeout_expired(dhd_timeout_t *tmo);
++
++extern int dhd_ifname2idx(struct dhd_info *dhd, char *name);
++extern int dhd_net2idx(struct dhd_info *dhd, struct net_device *net);
++extern struct net_device * dhd_idx2net(void *pub, int ifidx);
++extern int net_os_send_hang_message(struct net_device *dev);
++extern bool dhd_wowl_cap(void *bus);
++
++extern int wl_host_event(dhd_pub_t *dhd_pub, int *idx, void *pktdata,
++                         wl_event_msg_t *, void **data_ptr,  void *);
++extern void wl_event_to_host_order(wl_event_msg_t * evt);
++extern int wl_host_event_get_data(void *pktdata, wl_event_msg_t *event, void **data_ptr);
++
++extern int dhd_wl_ioctl(dhd_pub_t *dhd_pub, int ifindex, wl_ioctl_t *ioc, void *buf, int len);
++extern int dhd_wl_ioctl_cmd(dhd_pub_t *dhd_pub, int cmd, void *arg, int len, uint8 set,
++                            int ifindex);
++extern int dhd_wl_ioctl_get_intiovar(dhd_pub_t *dhd_pub, char *name, uint *pval,
++	int cmd, uint8 set, int ifidx);
++extern int dhd_wl_ioctl_set_intiovar(dhd_pub_t *dhd_pub, char *name, uint val,
++	int cmd, uint8 set, int ifidx);
++extern void dhd_common_init(osl_t *osh);
++
++extern int dhd_do_driver_init(struct net_device *net);
++extern int dhd_event_ifadd(struct dhd_info *dhd, struct wl_event_data_if *ifevent,
++	char *name, uint8 *mac);
++extern int dhd_event_ifdel(struct dhd_info *dhd, struct wl_event_data_if *ifevent,
++	char *name, uint8 *mac);
++extern struct net_device* dhd_allocate_if(dhd_pub_t *dhdpub, int ifidx, char *name,
++	uint8 *mac, uint8 bssidx, bool need_rtnl_lock, char *dngl_name);
++extern int dhd_remove_if(dhd_pub_t *dhdpub, int ifidx, bool need_rtnl_lock);
++extern void dhd_vif_add(struct dhd_info *dhd, int ifidx, char * name);
++extern void dhd_vif_del(struct dhd_info *dhd, int ifidx);
++extern void dhd_event(struct dhd_info *dhd, char *evpkt, int evlen, int ifidx);
++extern void dhd_vif_sendup(struct dhd_info *dhd, int ifidx, uchar *cp, int len);
++
++/* Send packet to dongle via data channel */
++extern int dhd_sendpkt(dhd_pub_t *dhdp, int ifidx, void *pkt);
++
++/* send up locally generated event */
++extern void dhd_sendup_event_common(dhd_pub_t *dhdp, wl_event_msg_t *event, void *data);
++/* Send event to host */
++extern void dhd_sendup_event(dhd_pub_t *dhdp, wl_event_msg_t *event, void *data);
++#ifdef LOG_INTO_TCPDUMP
++extern void dhd_sendup_log(dhd_pub_t *dhdp, void *data, int len);
++#endif /* LOG_INTO_TCPDUMP */
++extern int dhd_bus_devreset(dhd_pub_t *dhdp, uint8 flag);
++extern uint dhd_bus_status(dhd_pub_t *dhdp);
++extern int  dhd_bus_start(dhd_pub_t *dhdp);
++extern int dhd_bus_suspend(dhd_pub_t *dhdpub);
++extern int dhd_bus_resume(dhd_pub_t *dhdpub, int stage);
++extern int dhd_bus_membytes(dhd_pub_t *dhdp, bool set, uint32 address, uint8 *data, uint size);
++extern void dhd_print_buf(void *pbuf, int len, int bytes_per_line);
++extern bool dhd_is_associated(dhd_pub_t *dhd, void *bss_buf, int *retval);
++#if defined(BCMSDIO) || defined(BCMPCIE)
++extern uint dhd_bus_chip_id(dhd_pub_t *dhdp);
++extern uint dhd_bus_chiprev_id(dhd_pub_t *dhdp);
++extern uint dhd_bus_chippkg_id(dhd_pub_t *dhdp);
++#endif /* defined(BCMSDIO) || defined(BCMPCIE) */
++
++#if defined(KEEP_ALIVE)
++extern int dhd_keep_alive_onoff(dhd_pub_t *dhd);
++#endif /* KEEP_ALIVE */
++
++/* OS spin lock API */
++extern void *dhd_os_spin_lock_init(osl_t *osh);
++extern void dhd_os_spin_lock_deinit(osl_t *osh, void *lock);
++extern unsigned long dhd_os_spin_lock(void *lock);
++void dhd_os_spin_unlock(void *lock, unsigned long flags);
++
++/*
++ * Manage sta objects in an interface. Interface is identified by an ifindex and
++ * sta(s) within an interfaces are managed using a MacAddress of the sta.
++ */
++struct dhd_sta;
++extern struct dhd_sta *dhd_find_sta(void *pub, int ifidx, void *ea);
++extern struct dhd_sta *dhd_findadd_sta(void *pub, int ifidx, void *ea);
++extern void dhd_del_sta(void *pub, int ifidx, void *ea);
++extern int dhd_get_ap_isolate(dhd_pub_t *dhdp, uint32 idx);
++extern int dhd_set_ap_isolate(dhd_pub_t *dhdp, uint32 idx, int val);
++#if defined(BCM_GMAC3)
++extern int dhd_set_dev_def(dhd_pub_t *dhdp, uint32 idx, int val);
++#endif
++extern int dhd_bssidx2idx(dhd_pub_t *dhdp, uint32 bssidx);
++extern int dhd_os_d3ack_wait(dhd_pub_t * pub, uint * condition);
++extern int dhd_os_d3ack_wake(dhd_pub_t * pub);
++extern struct net_device *dhd_linux_get_primary_netdev(dhd_pub_t *dhdp);
++extern int dhd_os_busbusy_wait_negation(dhd_pub_t * pub, uint * condition);
++extern int dhd_os_busbusy_wake(dhd_pub_t * pub);
++
++extern bool dhd_is_concurrent_mode(dhd_pub_t *dhd);
++int dhd_iovar(dhd_pub_t *pub, int ifidx, char *name, char *param_buf, uint param_len,
++		char *res_buf, uint res_len, int set);
++extern int dhd_getiovar(dhd_pub_t *pub, int ifidx, char *name, char *cmd_buf,
++		uint cmd_len, char **resptr, uint resp_len);
++
++#ifdef DHD_MCAST_REGEN
++extern int dhd_get_mcast_regen_bss_enable(dhd_pub_t *dhdp, uint32 idx);
++extern int dhd_set_mcast_regen_bss_enable(dhd_pub_t *dhdp, uint32 idx, int val);
++#endif
++typedef enum cust_gpio_modes {
++	WLAN_RESET_ON,
++	WLAN_RESET_OFF,
++	WLAN_POWER_ON,
++	WLAN_POWER_OFF
++} cust_gpio_modes_t;
++
++extern int wl_iw_iscan_set_scan_broadcast_prep(struct net_device *dev, uint flag);
++extern int wl_iw_send_priv_event(struct net_device *dev, char *flag);
++/*
++ * Insmod parameters for debug/test
++ */
++
++/* Watchdog timer interval */
++extern uint dhd_watchdog_ms;
++
++#if defined(DHD_DEBUG)
++/* Console output poll interval */
++extern uint dhd_console_ms;
++extern uint wl_msg_level;
++#endif /* defined(DHD_DEBUG) */
++
++extern uint dhd_slpauto;
++
++/* Use interrupts */
++extern uint dhd_intr;
++
++/* Use polling */
++extern uint dhd_poll;
++
++/* ARP offload agent mode */
++extern uint dhd_arp_mode;
++
++/* ARP offload enable */
++extern uint dhd_arp_enable;
++
++/* Pkt filte enable control */
++extern uint dhd_pkt_filter_enable;
++
++/*  Pkt filter init setup */
++extern uint dhd_pkt_filter_init;
++
++/* Pkt filter mode control */
++extern uint dhd_master_mode;
++
++/* Roaming mode control */
++extern uint dhd_roam_disable;
++
++/* Roaming mode control */
++extern uint dhd_radio_up;
++
++/* Initial idletime ticks (may be -1 for immediate idle, 0 for no idle) */
++extern int dhd_idletime;
++#ifdef DHD_USE_IDLECOUNT
++#define DHD_IDLETIME_TICKS 5
++#else
++#define DHD_IDLETIME_TICKS 1
++#endif /* DHD_USE_IDLECOUNT */
++
++/* SDIO Drive Strength */
++extern uint dhd_sdiod_drive_strength;
++
++/* triggers bcm_bprintf to print to kernel log */
++extern bool bcm_bprintf_bypass;
++
++/* Override to force tx queueing all the time */
++extern uint dhd_force_tx_queueing;
++/* Default KEEP_ALIVE Period is 55 sec to prevent AP from sending Keep Alive probe frame */
++#define DEFAULT_KEEP_ALIVE_VALUE 	55000 /* msec */
++#ifndef CUSTOM_KEEP_ALIVE_SETTING
++#define CUSTOM_KEEP_ALIVE_SETTING 	DEFAULT_KEEP_ALIVE_VALUE
++#endif /* DEFAULT_KEEP_ALIVE_VALUE */
++
++#define NULL_PKT_STR	"null_pkt"
++
++/* hooks for custom glom setting option via Makefile */
++#define DEFAULT_GLOM_VALUE 	-1
++#ifndef CUSTOM_GLOM_SETTING
++#define CUSTOM_GLOM_SETTING 	DEFAULT_GLOM_VALUE
++#endif
++#define WL_AUTO_ROAM_TRIGGER -75
++/* hooks for custom Roaming Trigger  setting via Makefile */
++#define DEFAULT_ROAM_TRIGGER_VALUE -75 /* dBm default roam trigger all band */
++#define DEFAULT_ROAM_TRIGGER_SETTING 	-1
++#ifndef CUSTOM_ROAM_TRIGGER_SETTING
++#define CUSTOM_ROAM_TRIGGER_SETTING 	DEFAULT_ROAM_TRIGGER_VALUE
++#endif
++
++/* hooks for custom Roaming Romaing  setting via Makefile */
++#define DEFAULT_ROAM_DELTA_VALUE  10 /* dBm default roam delta all band */
++#define DEFAULT_ROAM_DELTA_SETTING 	-1
++#ifndef CUSTOM_ROAM_DELTA_SETTING
++#define CUSTOM_ROAM_DELTA_SETTING 	DEFAULT_ROAM_DELTA_VALUE
++#endif
++
++/* hooks for custom PNO Event wake lock to guarantee enough time
++	for the Platform to detect Event before system suspended
++*/
++#define DEFAULT_PNO_EVENT_LOCK_xTIME 	2 	/* multiplay of DHD_PACKET_TIMEOUT_MS */
++#ifndef CUSTOM_PNO_EVENT_LOCK_xTIME
++#define CUSTOM_PNO_EVENT_LOCK_xTIME	 DEFAULT_PNO_EVENT_LOCK_xTIME
++#endif
++/* hooks for custom dhd_dpc_prio setting option via Makefile */
++#define DEFAULT_DHP_DPC_PRIO  1
++#ifndef CUSTOM_DPC_PRIO_SETTING
++#define CUSTOM_DPC_PRIO_SETTING 	DEFAULT_DHP_DPC_PRIO
++#endif
++
++#ifndef CUSTOM_LISTEN_INTERVAL
++#define CUSTOM_LISTEN_INTERVAL 		LISTEN_INTERVAL
++#endif /* CUSTOM_LISTEN_INTERVAL */
++
++#define DEFAULT_SUSPEND_BCN_LI_DTIM		3
++#ifndef CUSTOM_SUSPEND_BCN_LI_DTIM
++#define CUSTOM_SUSPEND_BCN_LI_DTIM		DEFAULT_SUSPEND_BCN_LI_DTIM
++#endif
++
++#ifndef CUSTOM_RXF_PRIO_SETTING
++#define CUSTOM_RXF_PRIO_SETTING		MAX((CUSTOM_DPC_PRIO_SETTING - 1), 1)
++#endif
++
++#define DEFAULT_WIFI_TURNOFF_DELAY		0
++#define WIFI_TURNOFF_DELAY		DEFAULT_WIFI_TURNOFF_DELAY
++
++#define DEFAULT_WIFI_TURNON_DELAY		200
++#ifndef WIFI_TURNON_DELAY
++#define WIFI_TURNON_DELAY		DEFAULT_WIFI_TURNON_DELAY
++#endif /* WIFI_TURNON_DELAY */
++
++#define DEFAULT_DHD_WATCHDOG_INTERVAL_MS	10 /* msec */
++#ifndef CUSTOM_DHD_WATCHDOG_MS
++#define CUSTOM_DHD_WATCHDOG_MS			DEFAULT_DHD_WATCHDOG_INTERVAL_MS
++#endif /* DEFAULT_DHD_WATCHDOG_INTERVAL_MS */
++
++#define DEFAULT_ASSOC_RETRY_MAX			3
++#ifndef CUSTOM_ASSOC_RETRY_MAX
++#define CUSTOM_ASSOC_RETRY_MAX			DEFAULT_ASSOC_RETRY_MAX
++#endif /* DEFAULT_ASSOC_RETRY_MAX */
++
++
++#ifdef WLTDLS
++#ifndef CUSTOM_TDLS_IDLE_MODE_SETTING
++#define CUSTOM_TDLS_IDLE_MODE_SETTING  60000 /* 60sec to tear down TDLS of not active */
++#endif
++#ifndef CUSTOM_TDLS_RSSI_THRESHOLD_HIGH
++#define CUSTOM_TDLS_RSSI_THRESHOLD_HIGH -70 /* rssi threshold for establishing TDLS link */
++#endif
++#ifndef CUSTOM_TDLS_RSSI_THRESHOLD_LOW
++#define CUSTOM_TDLS_RSSI_THRESHOLD_LOW -80 /* rssi threshold for tearing down TDLS link */
++#endif
++#endif /* WLTDLS */
++
++#define DEFAULT_BCN_TIMEOUT		8
++#ifndef CUSTOM_BCN_TIMEOUT
++#define CUSTOM_BCN_TIMEOUT		DEFAULT_BCN_TIMEOUT
++#endif
++
++#define MAX_DTIM_SKIP_BEACON_INTERVAL	100 /* max allowed associated AP beacon for DTIM skip */
++#ifndef MAX_DTIM_ALLOWED_INTERVAL
++#define MAX_DTIM_ALLOWED_INTERVAL 600 /* max allowed total beacon interval for DTIM skip */
++#endif
++#define NO_DTIM_SKIP 1
++#ifdef SDTEST
++/* Echo packet generator (SDIO), pkts/s */
++extern uint dhd_pktgen;
++
++/* Echo packet len (0 => sawtooth, max 1800) */
++extern uint dhd_pktgen_len;
++#define MAX_PKTGEN_LEN 1800
++#endif
++
++
++/* optionally set by a module_param_string() */
++#define MOD_PARAM_PATHLEN	2048
++#define MOD_PARAM_INFOLEN	512
++
++#ifdef SOFTAP
++extern char fw_path2[MOD_PARAM_PATHLEN];
++#endif
++
++/* Flag to indicate if we should download firmware on driver load */
++extern uint dhd_download_fw_on_driverload;
++#ifndef BCMDBUS
++extern int allow_delay_fwdl;
++#endif /* !BCMDBUS */
++
++
++extern void dhd_wait_for_event(dhd_pub_t *dhd, bool *lockvar);
++extern void dhd_wait_event_wakeup(dhd_pub_t*dhd);
++
++#define IFLOCK_INIT(lock)       *lock = 0
++#define IFLOCK(lock)    while (InterlockedCompareExchange((lock), 1, 0))	\
++	NdisStallExecution(1);
++#define IFUNLOCK(lock)  InterlockedExchange((lock), 0)
++#define IFLOCK_FREE(lock)
++#define FW_SUPPORTED(dhd, capa) ((strstr(dhd->fw_capabilities, " " #capa " ") != NULL))
++#ifdef ARP_OFFLOAD_SUPPORT
++#define MAX_IPV4_ENTRIES	8
++void dhd_arp_offload_set(dhd_pub_t * dhd, int arp_mode);
++void dhd_arp_offload_enable(dhd_pub_t * dhd, int arp_enable);
++
++/* dhd_commn arp offload wrapers */
++void dhd_aoe_hostip_clr(dhd_pub_t *dhd, int idx);
++void dhd_aoe_arp_clr(dhd_pub_t *dhd, int idx);
++int dhd_arp_get_arp_hostip_table(dhd_pub_t *dhd, void *buf, int buflen, int idx);
++void dhd_arp_offload_add_ip(dhd_pub_t *dhd, uint32 ipaddr, int idx);
++#endif /* ARP_OFFLOAD_SUPPORT */
++#ifdef WLTDLS
++int dhd_tdls_enable(struct net_device *dev, bool tdls_on, bool auto_on, struct ether_addr *mac);
++int dhd_tdls_set_mode(dhd_pub_t *dhd, bool wfd_mode);
++#ifdef PCIE_FULL_DONGLE
++void dhd_tdls_update_peer_info(struct net_device *dev, bool connect_disconnect, uint8 *addr);
++#endif /* PCIE_FULL_DONGLE */
++#endif /* WLTDLS */
++/* Neighbor Discovery Offload Support */
++int dhd_ndo_enable(dhd_pub_t * dhd, int ndo_enable);
++int dhd_ndo_add_ip(dhd_pub_t *dhd, char* ipaddr, int idx);
++int dhd_ndo_remove_ip(dhd_pub_t *dhd, int idx);
++/* ioctl processing for nl80211 */
++int dhd_ioctl_process(dhd_pub_t *pub, int ifidx, struct dhd_ioctl *ioc, void *data_buf);
++
++void dhd_bus_update_fw_nv_path(struct dhd_bus *bus, char *pfw_path, char *pnv_path);
++void dhd_set_bus_state(void *bus, uint32 state);
++
++/* Remove proper pkts(either one no-frag pkt or whole fragmented pkts) */
++typedef int (*f_droppkt_t)(dhd_pub_t *dhdp, int prec, void* p, bool bPktInQ);
++extern bool dhd_prec_drop_pkts(dhd_pub_t *dhdp, struct pktq *pq, int prec, f_droppkt_t fn);
++
++#ifdef PROP_TXSTATUS
++int dhd_os_wlfc_block(dhd_pub_t *pub);
++int dhd_os_wlfc_unblock(dhd_pub_t *pub);
++extern const uint8 prio2fifo[];
++#endif /* PROP_TXSTATUS */
++
++void dhd_save_fwdump(dhd_pub_t *dhd_pub, void * buffer, uint32 length);
++void dhd_schedule_memdump(dhd_pub_t *dhdp, uint8 *buf, uint32 size);
++int dhd_os_socram_dump(struct net_device *dev, uint32 *dump_size);
++int dhd_os_get_socram_dump(struct net_device *dev, char **buf, uint32 *size);
++int dhd_common_socram_dump(dhd_pub_t *dhdp);
++int dhd_os_get_version(struct net_device *dev, bool dhd_ver, char **buf, uint32 size);
++
++uint8* dhd_os_prealloc(dhd_pub_t *dhdpub, int section, uint size, bool kmalloc_if_fail);
++void dhd_os_prefree(dhd_pub_t *dhdpub, void *addr, uint size);
++
++int dhd_process_cid_mac(dhd_pub_t *dhdp, bool prepost);
++
++#if defined(CONFIG_DHD_USE_STATIC_BUF)
++#define DHD_OS_PREALLOC(dhdpub, section, size) dhd_os_prealloc(dhdpub, section, size, FALSE)
++#define DHD_OS_PREFREE(dhdpub, addr, size) dhd_os_prefree(dhdpub, addr, size)
++#else
++#define DHD_OS_PREALLOC(dhdpub, section, size) MALLOC(dhdpub->osh, size)
++#define DHD_OS_PREFREE(dhdpub, addr, size) MFREE(dhdpub->osh, addr, size)
++#endif /* defined(CONFIG_DHD_USE_STATIC_BUF) */
++
++
++#define dhd_add_flowid(pub, ifidx, ac_prio, ea, flowid)  do {} while (0)
++#define dhd_del_flowid(pub, ifidx, flowid)               do {} while (0)
++bool dhd_wet_chainable(dhd_pub_t *dhdp);
++
++extern unsigned long dhd_os_general_spin_lock(dhd_pub_t *pub);
++extern void dhd_os_general_spin_unlock(dhd_pub_t *pub, unsigned long flags);
++
++/** Miscellaenous DHD Spin Locks */
++
++/* Disable router 3GMAC bypass path perimeter lock */
++#define DHD_PERIM_LOCK(dhdp)              do {} while (0)
++#define DHD_PERIM_UNLOCK(dhdp)            do {} while (0)
++#define DHD_PERIM_LOCK_ALL(processor_id)    do {} while (0)
++#define DHD_PERIM_UNLOCK_ALL(processor_id)  do {} while (0)
++
++/* Enable DHD general spin lock/unlock */
++#define DHD_GENERAL_LOCK(dhdp, flags) \
++	(flags) = dhd_os_general_spin_lock(dhdp)
++#define DHD_GENERAL_UNLOCK(dhdp, flags) \
++	dhd_os_general_spin_unlock((dhdp), (flags))
++
++/* Enable DHD flowring spin lock/unlock */
++#define DHD_FLOWRING_LOCK(lock, flags)     (flags) = dhd_os_spin_lock(lock)
++#define DHD_FLOWRING_UNLOCK(lock, flags)   dhd_os_spin_unlock((lock), (flags))
++
++/* Enable DHD common flowring info spin lock/unlock */
++#define DHD_FLOWID_LOCK(lock, flags)       (flags) = dhd_os_spin_lock(lock)
++#define DHD_FLOWID_UNLOCK(lock, flags)     dhd_os_spin_unlock((lock), (flags))
++
++/* Enable DHD common flowring list spin lock/unlock */
++#define DHD_FLOWRING_LIST_LOCK(lock, flags)       (flags) = dhd_os_spin_lock(lock)
++#define DHD_FLOWRING_LIST_UNLOCK(lock, flags)     dhd_os_spin_unlock((lock), (flags))
++
++extern void dhd_dump_to_kernelog(dhd_pub_t *dhdp);
++
++#ifdef BCMDBUS
++extern void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf);
++extern void dhd_bus_clearcounts(dhd_pub_t *dhdp);
++#endif /* BCMDBUS */
++
++#ifdef DHD_L2_FILTER
++extern int dhd_get_parp_status(dhd_pub_t *dhdp, uint32 idx);
++extern int dhd_set_parp_status(dhd_pub_t *dhdp, uint32 idx, int val);
++extern int dhd_get_dhcp_unicast_status(dhd_pub_t *dhdp, uint32 idx);
++extern int dhd_set_dhcp_unicast_status(dhd_pub_t *dhdp, uint32 idx, int val);
++extern int dhd_get_block_ping_status(dhd_pub_t *dhdp, uint32 idx);
++extern int dhd_set_block_ping_status(dhd_pub_t *dhdp, uint32 idx, int val);
++extern int dhd_get_grat_arp_status(dhd_pub_t *dhdp, uint32 idx);
++extern int dhd_set_grat_arp_status(dhd_pub_t *dhdp, uint32 idx, int val);
++#endif /* DHD_L2_FILTER */
++
++
++typedef struct wl_io_pport {
++	dhd_pub_t *dhd_pub;
++	uint ifidx;
++} wl_io_pport_t;
++
++typedef struct wl_evt_pport {
++	dhd_pub_t *dhd_pub;
++	int *ifidx;
++	void *pktdata;
++	void **data_ptr;
++	void *raw_event;
++} wl_evt_pport_t;
++
++extern void *dhd_pub_shim(dhd_pub_t *dhd_pub);
++#ifdef DHD_FW_COREDUMP
++void* dhd_get_fwdump_buf(dhd_pub_t *dhd_pub, uint32 length);
++#endif /* DHD_FW_COREDUMP */
++
++#if defined(SET_RPS_CPUS)
++int dhd_rps_cpus_enable(struct net_device *net, int enable);
++int custom_rps_map_set(struct netdev_rx_queue *queue, char *buf, size_t len);
++void custom_rps_map_clear(struct netdev_rx_queue *queue);
++#define PRIMARY_INF 0
++#define VIRTUAL_INF 1
++#if defined(CONFIG_MACH_UNIVERSAL5433) || defined(CONFIG_MACH_UNIVERSAL7420) || \
++	defined(CONFIG_SOC_EXYNOS8890)
++#define RPS_CPUS_MASK "10"
++#define RPS_CPUS_MASK_P2P "10"
++#define RPS_CPUS_MASK_IBSS "10"
++#define RPS_CPUS_WLAN_CORE_ID 4
++#else
++#define RPS_CPUS_MASK "6"
++#define RPS_CPUS_MASK_P2P "6"
++#define RPS_CPUS_MASK_IBSS "6"
++#endif /* CONFIG_MACH_UNIVERSAL5433 || CONFIG_MACH_UNIVERSAL7420 || CONFIG_SOC_EXYNOS8890 */
++#endif 
++
++int dhd_get_download_buffer(dhd_pub_t	*dhd, char *file_path, download_type_t component,
++	char ** buffer, int *length);
++
++void dhd_free_download_buffer(dhd_pub_t	*dhd, void *buffer, int length);
++
++/* blob support */
++int dhd_download_clm_blob(dhd_pub_t *dhd, unsigned char *buf, uint32 len);
++
++int dhd_apply_default_clm(dhd_pub_t *dhd, char *clm_path);
++
++#define dhd_is_device_removed(x) FALSE
++#define dhd_os_ind_firmware_stall(x)
++
++#if defined(DHD_FW_COREDUMP)
++extern void dhd_get_memdump_info(dhd_pub_t *dhd);
++#endif 
++
++
++#if defined(DHD_LB_STATS)
++#include <bcmutils.h>
++extern void dhd_lb_stats_init(dhd_pub_t *dhd);
++extern void dhd_lb_stats_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf);
++extern void dhd_lb_stats_update_napi_histo(dhd_pub_t *dhdp, uint32 count);
++extern void dhd_lb_stats_update_txc_histo(dhd_pub_t *dhdp, uint32 count);
++extern void dhd_lb_stats_update_rxc_histo(dhd_pub_t *dhdp, uint32 count);
++extern void dhd_lb_stats_txc_percpu_cnt_incr(dhd_pub_t *dhdp);
++extern void dhd_lb_stats_rxc_percpu_cnt_incr(dhd_pub_t *dhdp);
++#define DHD_LB_STATS_INIT(dhdp) dhd_lb_stats_init(dhdp)
++/* Reset is called from common layer so it takes dhd_pub_t as argument */
++#define DHD_LB_STATS_RESET(dhdp) dhd_lb_stats_init(dhdp)
++#define DHD_LB_STATS_CLR(x)     (x) = 0U
++#define DHD_LB_STATS_INCR(x)    (x) = (x) + 1
++#define DHD_LB_STATS_ADD(x, c)  (x) = (x) + (c)
++#define DHD_LB_STATS_PERCPU_ARR_INCR(x) \
++	{ \
++		int cpu = get_cpu(); put_cpu(); \
++		DHD_LB_STATS_INCR(x[cpu]); \
++	}
++#define DHD_LB_STATS_UPDATE_NAPI_HISTO(dhdp, x) dhd_lb_stats_update_napi_histo(dhdp, x)
++#define DHD_LB_STATS_UPDATE_TXC_HISTO(dhdp, x)  dhd_lb_stats_update_txc_histo(dhdp, x)
++#define DHD_LB_STATS_UPDATE_RXC_HISTO(dhdp, x)  dhd_lb_stats_update_rxc_histo(dhdp, x)
++#define DHD_LB_STATS_TXC_PERCPU_CNT_INCR(dhdp)  dhd_lb_stats_txc_percpu_cnt_incr(dhdp)
++#define DHD_LB_STATS_RXC_PERCPU_CNT_INCR(dhdp)  dhd_lb_stats_rxc_percpu_cnt_incr(dhdp)
++#else /* !DHD_LB_STATS */
++#define DHD_LB_STATS_NOOP       do { /* noop */ } while (0)
++#define DHD_LB_STATS_INIT(dhdp)  DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_RESET(dhdp) DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_CLR(x)      DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_INCR(x)     DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_ADD(x, c)   DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_PERCPU_ARR_INCR(x)  DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_UPDATE_NAPI_HISTO(dhd, x) DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_UPDATE_TXC_HISTO(dhd, x) DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_UPDATE_RXC_HISTO(dhd, x) DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_TXC_PERCPU_CNT_INCR(dhdp) DHD_LB_STATS_NOOP
++#define DHD_LB_STATS_RXC_PERCPU_CNT_INCR(dhdp) DHD_LB_STATS_NOOP
++#endif /* !DHD_LB_STATS */
++
++extern int dhd_prot_debug_info_print(dhd_pub_t *dhd);
++
++#define htod32(i) (i)
++#define htod16(i) (i)
++#define dtoh32(i) (i)
++#define dtoh16(i) (i)
++#define htodchanspec(i) (i)
++#define dtohchanspec(i) (i)
++
++#endif /* _dhd_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_bta.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_bta.c
+new file mode 100644
+index 000000000..58c113c3a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_bta.c
+@@ -0,0 +1,354 @@
++/*
++ * BT-AMP support routines
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_bta.c 514727 2014-11-12 03:02:48Z $
++ */
++#error "WLBTAMP is not defined"
++
++#include <typedefs.h>
++#include <osl.h>
++#include <bcmcdc.h>
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <proto/802.11.h>
++#include <proto/802.11_bta.h>
++#include <proto/bt_amp_hci.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#ifdef BCMDBUS
++#include <dbus.h>
++#else
++#include <dhd_bus.h>
++#endif
++#include <dhd_proto.h>
++#include <dhdioctl.h>
++#include <dhd_dbg.h>
++
++#include <dhd_bta.h>
++
++
++#ifdef SEND_HCI_CMD_VIA_IOCTL
++#define BTA_HCI_CMD_MAX_LEN HCI_CMD_PREAMBLE_SIZE + HCI_CMD_DATA_SIZE
++
++/* Send HCI cmd via wl iovar HCI_cmd to the dongle. */
++int
++dhd_bta_docmd(dhd_pub_t *pub, void *cmd_buf, uint cmd_len)
++{
++	amp_hci_cmd_t *cmd = (amp_hci_cmd_t *)cmd_buf;
++	uint8 buf[BTA_HCI_CMD_MAX_LEN + 16];
++	uint len = sizeof(buf);
++	wl_ioctl_t ioc;
++
++	if (cmd_len < HCI_CMD_PREAMBLE_SIZE)
++		return BCME_BADLEN;
++
++	if ((uint)cmd->plen + HCI_CMD_PREAMBLE_SIZE > cmd_len)
++		return BCME_BADLEN;
++
++	len = bcm_mkiovar("HCI_cmd",
++		(char *)cmd, (uint)cmd->plen + HCI_CMD_PREAMBLE_SIZE, (char *)buf, len);
++
++
++	memset(&ioc, 0, sizeof(ioc));
++
++	ioc.cmd = WLC_SET_VAR;
++	ioc.buf = buf;
++	ioc.len = len;
++	ioc.set = TRUE;
++
++	return dhd_wl_ioctl(pub, &ioc, ioc.buf, ioc.len);
++}
++#else /* !SEND_HCI_CMD_VIA_IOCTL */
++
++static void
++dhd_bta_flush_hcidata(dhd_pub_t *pub, uint16 llh)
++{
++	int prec;
++	struct pktq *q;
++	uint count = 0;
++
++#ifdef BCMDBUS
++	q = dhd_dbus_txq(pub->dbus);
++#else
++	q = dhd_bus_txq(pub->bus);
++#endif /* BCMDBUS */
++	if (q == NULL)
++		return;
++
++	DHD_BTA(("dhd: flushing HCI ACL data for logical link %u...\n", llh));
++
++	dhd_os_sdlock_txq(pub);
++
++	/* Walk through the txq and toss all HCI ACL data packets */
++	PKTQ_PREC_ITER(q, prec) {
++		void *head_pkt = NULL;
++
++		while (pktq_ppeek(q, prec) != head_pkt) {
++			void *pkt = pktq_pdeq(q, prec);
++			int ifidx;
++
++#ifdef BCMDBUS
++			PKTPULL(pub->osh, pkt, dhd_dbus_hdrlen(pub->dbus));
++#endif /* BCMDBUS */
++			dhd_prot_hdrpull(pub, &ifidx, pkt, NULL, NULL);
++
++			if (PKTLEN(pub->osh, pkt) >= RFC1042_HDR_LEN) {
++				struct ether_header *eh =
++				        (struct ether_header *)PKTDATA(pub->osh, pkt);
++
++				if (ntoh16(eh->ether_type) < ETHER_TYPE_MIN) {
++					struct dot11_llc_snap_header *lsh =
++					        (struct dot11_llc_snap_header *)&eh[1];
++
++					if (bcmp(lsh, BT_SIG_SNAP_MPROT,
++					         DOT11_LLC_SNAP_HDR_LEN - 2) == 0 &&
++					    ntoh16(lsh->type) == BTA_PROT_L2CAP) {
++						amp_hci_ACL_data_t *ACL_data =
++						        (amp_hci_ACL_data_t *)&lsh[1];
++						uint16 handle = ltoh16(ACL_data->handle);
++
++						if (HCI_ACL_DATA_HANDLE(handle) == llh) {
++							PKTFREE(pub->osh, pkt, TRUE);
++							count ++;
++							continue;
++						}
++					}
++				}
++			}
++
++			dhd_prot_hdrpush(pub, ifidx, pkt);
++#ifdef BCMDBUS
++			PKTPUSH(pub->osh, pkt, dhd_dbus_hdrlen(pub->dbus));
++#endif /* BCMDBUS */
++
++			if (head_pkt == NULL)
++				head_pkt = pkt;
++			pktq_penq(q, prec, pkt);
++		}
++	}
++
++	dhd_os_sdunlock_txq(pub);
++
++	DHD_BTA(("dhd: flushed %u packet(s) for logical link %u...\n", count, llh));
++}
++
++/* Handle HCI cmd locally.
++ * Return 0: continue to send the cmd across SDIO
++ *        < 0: stop, fail
++ *        > 0: stop, succuess
++ */
++static int
++_dhd_bta_docmd(dhd_pub_t *pub, amp_hci_cmd_t *cmd)
++{
++	int status = 0;
++
++	switch (ltoh16_ua((uint8 *)&cmd->opcode)) {
++	case HCI_Enhanced_Flush: {
++		eflush_cmd_parms_t *cmdparms = (eflush_cmd_parms_t *)cmd->parms;
++		dhd_bta_flush_hcidata(pub, ltoh16_ua(cmdparms->llh));
++		break;
++	}
++	default:
++		break;
++	}
++
++	return status;
++}
++
++/* Send HCI cmd encapsulated in BT-SIG frame via data channel to the dongle. */
++int
++dhd_bta_docmd(dhd_pub_t *pub, void *cmd_buf, uint cmd_len)
++{
++	amp_hci_cmd_t *cmd = (amp_hci_cmd_t *)cmd_buf;
++	struct ether_header *eh;
++	struct dot11_llc_snap_header *lsh;
++	osl_t *osh = pub->osh;
++	uint len;
++	void *p;
++	int status;
++
++	if (cmd_len < HCI_CMD_PREAMBLE_SIZE) {
++		DHD_ERROR(("dhd_bta_docmd: short command, cmd_len %u\n", cmd_len));
++		return BCME_BADLEN;
++	}
++
++	if ((len = (uint)cmd->plen + HCI_CMD_PREAMBLE_SIZE) > cmd_len) {
++		DHD_ERROR(("dhd_bta_docmd: malformed command, len %u cmd_len %u\n",
++		           len, cmd_len));
++		/* return BCME_BADLEN; */
++	}
++
++	p = PKTGET(osh, pub->hdrlen + RFC1042_HDR_LEN + len, TRUE);
++	if (p == NULL) {
++		DHD_ERROR(("dhd_bta_docmd: out of memory\n"));
++		return BCME_NOMEM;
++	}
++
++
++	/* intercept and handle the HCI cmd locally */
++	if ((status = _dhd_bta_docmd(pub, cmd)) > 0)
++		return 0;
++	else if (status < 0)
++		return status;
++
++	/* copy in HCI cmd */
++	PKTPULL(osh, p, pub->hdrlen + RFC1042_HDR_LEN);
++	bcopy(cmd, PKTDATA(osh, p), len);
++
++	/* copy in partial Ethernet header with BT-SIG LLC/SNAP header */
++	PKTPUSH(osh, p, RFC1042_HDR_LEN);
++	eh = (struct ether_header *)PKTDATA(osh, p);
++	bzero(eh->ether_dhost, ETHER_ADDR_LEN);
++	ETHER_SET_LOCALADDR(eh->ether_dhost);
++	bcopy(&pub->mac, eh->ether_shost, ETHER_ADDR_LEN);
++	eh->ether_type = hton16(len + DOT11_LLC_SNAP_HDR_LEN);
++	lsh = (struct dot11_llc_snap_header *)&eh[1];
++	bcopy(BT_SIG_SNAP_MPROT, lsh, DOT11_LLC_SNAP_HDR_LEN - 2);
++	lsh->type = 0;
++
++	return dhd_sendpkt(pub, 0, p);
++}
++#endif /* !SEND_HCI_CMD_VIA_IOCTL */
++
++/* Send HCI ACL data to dongle via data channel */
++int
++dhd_bta_tx_hcidata(dhd_pub_t *pub, void *data_buf, uint data_len)
++{
++	amp_hci_ACL_data_t *data = (amp_hci_ACL_data_t *)data_buf;
++	struct ether_header *eh;
++	struct dot11_llc_snap_header *lsh;
++	osl_t *osh = pub->osh;
++	uint len;
++	void *p;
++
++	if (data_len < HCI_ACL_DATA_PREAMBLE_SIZE) {
++		DHD_ERROR(("dhd_bta_tx_hcidata: short data_buf, data_len %u\n", data_len));
++		return BCME_BADLEN;
++	}
++
++	if ((len = (uint)ltoh16(data->dlen) + HCI_ACL_DATA_PREAMBLE_SIZE) > data_len) {
++		DHD_ERROR(("dhd_bta_tx_hcidata: malformed hci data, len %u data_len %u\n",
++		           len, data_len));
++		/* return BCME_BADLEN; */
++	}
++
++	p = PKTGET(osh, pub->hdrlen + RFC1042_HDR_LEN + len, TRUE);
++	if (p == NULL) {
++		DHD_ERROR(("dhd_bta_tx_hcidata: out of memory\n"));
++		return BCME_NOMEM;
++	}
++
++
++	/* copy in HCI ACL data header and HCI ACL data */
++	PKTPULL(osh, p, pub->hdrlen + RFC1042_HDR_LEN);
++	bcopy(data, PKTDATA(osh, p), len);
++
++	/* copy in partial Ethernet header with BT-SIG LLC/SNAP header */
++	PKTPUSH(osh, p, RFC1042_HDR_LEN);
++	eh = (struct ether_header *)PKTDATA(osh, p);
++	bzero(eh->ether_dhost, ETHER_ADDR_LEN);
++	bcopy(&pub->mac, eh->ether_shost, ETHER_ADDR_LEN);
++	eh->ether_type = hton16(len + DOT11_LLC_SNAP_HDR_LEN);
++	lsh = (struct dot11_llc_snap_header *)&eh[1];
++	bcopy(BT_SIG_SNAP_MPROT, lsh, DOT11_LLC_SNAP_HDR_LEN - 2);
++	lsh->type = HTON16(BTA_PROT_L2CAP);
++
++	return dhd_sendpkt(pub, 0, p);
++}
++
++/* txcomplete callback */
++void
++dhd_bta_tx_hcidata_complete(dhd_pub_t *dhdp, void *txp, bool success)
++{
++	uint8 *pktdata = (uint8 *)PKTDATA(dhdp->osh, txp);
++	amp_hci_ACL_data_t *ACL_data = (amp_hci_ACL_data_t *)(pktdata + RFC1042_HDR_LEN);
++	uint16 handle = ltoh16(ACL_data->handle);
++	uint16 llh = HCI_ACL_DATA_HANDLE(handle);
++
++	wl_event_msg_t event;
++	uint8 data[HCI_EVT_PREAMBLE_SIZE + sizeof(num_completed_data_blocks_evt_parms_t)];
++	amp_hci_event_t *evt;
++	num_completed_data_blocks_evt_parms_t *parms;
++
++	uint16 len = HCI_EVT_PREAMBLE_SIZE + sizeof(num_completed_data_blocks_evt_parms_t);
++
++	/* update the event struct */
++	memset(&event, 0, sizeof(event));
++	event.version = hton16(BCM_EVENT_MSG_VERSION);
++	event.event_type = hton32(WLC_E_BTA_HCI_EVENT);
++	event.status = 0;
++	event.reason = 0;
++	event.auth_type = 0;
++	event.datalen = hton32(len);
++	event.flags = 0;
++
++	/* generate Number of Completed Blocks event */
++	evt = (amp_hci_event_t *)data;
++	evt->ecode = HCI_Number_of_Completed_Data_Blocks;
++	evt->plen = sizeof(num_completed_data_blocks_evt_parms_t);
++
++	parms = (num_completed_data_blocks_evt_parms_t *)evt->parms;
++	htol16_ua_store(dhdp->maxdatablks, (uint8 *)&parms->num_blocks);
++	parms->num_handles = 1;
++	htol16_ua_store(llh, (uint8 *)&parms->completed[0].handle);
++	parms->completed[0].pkts = 1;
++	parms->completed[0].blocks = 1;
++
++	dhd_sendup_event_common(dhdp, &event, data);
++}
++
++/* event callback */
++void
++dhd_bta_doevt(dhd_pub_t *dhdp, void *data_buf, uint data_len)
++{
++	amp_hci_event_t *evt = (amp_hci_event_t *)data_buf;
++
++	ASSERT(dhdp);
++	ASSERT(evt);
++
++	switch (evt->ecode) {
++	case HCI_Command_Complete: {
++		cmd_complete_parms_t *parms = (cmd_complete_parms_t *)evt->parms;
++		switch (ltoh16_ua((uint8 *)&parms->opcode)) {
++		case HCI_Read_Data_Block_Size: {
++			read_data_block_size_evt_parms_t *parms2 =
++			        (read_data_block_size_evt_parms_t *)parms->parms;
++			dhdp->maxdatablks = ltoh16_ua((uint8 *)&parms2->data_block_num);
++			break;
++		}
++		}
++		break;
++	}
++
++	case HCI_Flush_Occurred: {
++		flush_occurred_evt_parms_t *evt_parms = (flush_occurred_evt_parms_t *)evt->parms;
++		dhd_bta_flush_hcidata(dhdp, ltoh16_ua((uint8 *)&evt_parms->handle));
++		break;
++	}
++	default:
++		break;
++	}
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_bta.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_bta.h
+new file mode 100644
+index 000000000..f87089d07
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_bta.h
+@@ -0,0 +1,42 @@
++/*
++ * BT-AMP support routines
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_bta.h 514727 2014-11-12 03:02:48Z $
++ */
++#ifndef __dhd_bta_h__
++#define __dhd_bta_h__
++
++struct dhd_pub;
++
++extern int dhd_bta_docmd(struct dhd_pub *pub, void *cmd_buf, uint cmd_len);
++
++extern void dhd_bta_doevt(struct dhd_pub *pub, void *data_buf, uint data_len);
++
++extern int dhd_bta_tx_hcidata(struct dhd_pub *pub, void *data_buf, uint data_len);
++extern void dhd_bta_tx_hcidata_complete(struct dhd_pub *dhdp, void *txp, bool success);
++
++
++#endif /* __dhd_bta_h__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_bus.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_bus.h
+new file mode 100644
+index 000000000..68e1a4567
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_bus.h
+@@ -0,0 +1,222 @@
++/*
++ * Header file describing the internal (inter-module) DHD interfaces.
++ *
++ * Provides type definitions and function prototypes used to link the
++ * DHD OS, bus, and protocol modules.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_bus.h 603826 2015-12-03 08:57:00Z $
++ */
++
++#ifndef _dhd_bus_h_
++#define _dhd_bus_h_
++
++/*
++ * Exported from dhd bus module (dhd_usb, dhd_sdio)
++ */
++
++/* Indicate (dis)interest in finding dongles. */
++extern int dhd_bus_register(void);
++extern void dhd_bus_unregister(void);
++
++/* Download firmware image and nvram image */
++extern int dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh, char *fw_path, char *nv_path);
++
++/* Stop bus module: clear pending frames, disable data flow */
++extern void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex);
++
++/* Initialize bus module: prepare for communication w/dongle */
++extern int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex);
++
++/* Get the Bus Idle Time */
++extern void dhd_bus_getidletime(dhd_pub_t *dhdp, int *idletime);
++
++/* Set the Bus Idle Time */
++extern void dhd_bus_setidletime(dhd_pub_t *dhdp, int idle_time);
++
++/* Send a data frame to the dongle.  Callee disposes of txp. */
++#ifdef BCMPCIE
++extern int dhd_bus_txdata(struct dhd_bus *bus, void *txp, uint8 ifidx);
++#else
++extern int dhd_bus_txdata(struct dhd_bus *bus, void *txp);
++#endif
++
++
++/* Send/receive a control message to/from the dongle.
++ * Expects caller to enforce a single outstanding transaction.
++ */
++extern int dhd_bus_txctl(struct dhd_bus *bus, uchar *msg, uint msglen);
++extern int dhd_bus_rxctl(struct dhd_bus *bus, uchar *msg, uint msglen);
++
++/* Watchdog timer function */
++extern bool dhd_bus_watchdog(dhd_pub_t *dhd);
++
++extern int dhd_bus_oob_intr_register(dhd_pub_t *dhdp);
++extern void dhd_bus_oob_intr_unregister(dhd_pub_t *dhdp);
++extern void dhd_bus_oob_intr_set(dhd_pub_t *dhdp, bool enable);
++extern void dhd_bus_dev_pm_stay_awake(dhd_pub_t *dhdpub);
++extern void dhd_bus_dev_pm_relax(dhd_pub_t *dhdpub);
++extern bool dhd_bus_dev_pm_enabled(dhd_pub_t *dhdpub);
++
++#if defined(DHD_DEBUG)
++/* Device console input function */
++extern int dhd_bus_console_in(dhd_pub_t *dhd, uchar *msg, uint msglen);
++#endif /* defined(DHD_DEBUG) */
++
++/* Deferred processing for the bus, return TRUE requests reschedule */
++extern bool dhd_bus_dpc(struct dhd_bus *bus);
++extern void dhd_bus_isr(bool * InterruptRecognized, bool * QueueMiniportHandleInterrupt, void *arg);
++
++
++/* Check for and handle local prot-specific iovar commands */
++extern int dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
++                            void *params, int plen, void *arg, int len, bool set);
++
++/* Add bus dump output to a buffer */
++extern void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf);
++
++/* Clear any bus counters */
++extern void dhd_bus_clearcounts(dhd_pub_t *dhdp);
++
++/* return the dongle chipid */
++extern uint dhd_bus_chip(struct dhd_bus *bus);
++
++/* return the dongle chiprev */
++extern uint dhd_bus_chiprev(struct dhd_bus *bus);
++
++/* Set user-specified nvram parameters. */
++extern void dhd_bus_set_nvram_params(struct dhd_bus * bus, const char *nvram_params);
++
++extern void *dhd_bus_pub(struct dhd_bus *bus);
++extern void *dhd_bus_txq(struct dhd_bus *bus);
++extern void *dhd_bus_sih(struct dhd_bus *bus);
++extern uint dhd_bus_hdrlen(struct dhd_bus *bus);
++#ifdef BCMSDIO
++extern void dhd_bus_set_dotxinrx(struct dhd_bus *bus, bool val);
++/* return sdio io status */
++extern uint8 dhd_bus_is_ioready(struct dhd_bus *bus);
++#else
++#define dhd_bus_set_dotxinrx(a, b) do {} while (0)
++#endif
++
++#define DHD_SET_BUS_STATE_DOWN(_bus)  do { \
++	(_bus)->dhd->busstate = DHD_BUS_DOWN; \
++} while (0)
++
++/* Register a dummy SDIO client driver in order to be notified of new SDIO device */
++extern int dhd_bus_reg_sdio_notify(void* semaphore);
++extern void dhd_bus_unreg_sdio_notify(void);
++extern void dhd_txglom_enable(dhd_pub_t *dhdp, bool enable);
++extern int dhd_bus_get_ids(struct dhd_bus *bus, uint32 *bus_type, uint32 *bus_num,
++	uint32 *slot_num);
++
++#ifdef BCMPCIE
++enum {
++	/* Scratch buffer confiuguration update */
++	D2H_DMA_SCRATCH_BUF,
++	D2H_DMA_SCRATCH_BUF_LEN,
++
++	/* DMA Indices array buffers for: H2D WR and RD, and D2H WR and RD */
++	H2D_DMA_INDX_WR_BUF, /* update H2D WR dma indices buf base addr to dongle */
++	H2D_DMA_INDX_RD_BUF, /* update H2D RD dma indices buf base addr to dongle */
++	D2H_DMA_INDX_WR_BUF, /* update D2H WR dma indices buf base addr to dongle */
++	D2H_DMA_INDX_RD_BUF, /* update D2H RD dma indices buf base addr to dongle */
++
++	/* DHD sets/gets WR or RD index, in host's H2D and D2H DMA indices buffer */
++	H2D_DMA_INDX_WR_UPD, /* update H2D WR index in H2D WR dma indices buf */
++	H2D_DMA_INDX_RD_UPD, /* update H2D RD index in H2D RD dma indices buf */
++	D2H_DMA_INDX_WR_UPD, /* update D2H WR index in D2H WR dma indices buf */
++	D2H_DMA_INDX_RD_UPD, /* update D2H RD index in D2H RD dma indices buf */
++
++	/* H2D and D2H Mailbox data update */
++	H2D_MB_DATA,
++	D2H_MB_DATA,
++
++	/* (Common) MsgBuf Ring configuration update */
++	RING_BUF_ADDR,       /* update ring base address to dongle */
++	RING_ITEM_LEN,       /* update ring item size to dongle */
++	RING_MAX_ITEMS,      /* update ring max items to dongle */
++
++	/* Update of WR or RD index, for a MsgBuf Ring */
++	RING_RD_UPD,         /* update ring read index from/to dongle */
++	RING_WR_UPD,         /* update ring write index from/to dongle */
++
++	TOTAL_LFRAG_PACKET_CNT,
++	MAX_HOST_RXBUFS
++};
++
++typedef void (*dhd_mb_ring_t) (struct dhd_bus *, uint32);
++extern void dhd_bus_cmn_writeshared(struct dhd_bus *bus, void * data, uint32 len, uint8 type,
++	uint16 ringid);
++extern void dhd_bus_ringbell(struct dhd_bus *bus, uint32 value);
++extern void dhd_bus_cmn_readshared(struct dhd_bus *bus, void* data, uint8 type, uint16 ringid);
++extern uint32 dhd_bus_get_sharedflags(struct dhd_bus *bus);
++extern void dhd_bus_rx_frame(struct dhd_bus *bus, void* pkt, int ifidx, uint pkt_count);
++extern void dhd_bus_start_queue(struct dhd_bus *bus);
++extern void dhd_bus_stop_queue(struct dhd_bus *bus);
++
++extern dhd_mb_ring_t dhd_bus_get_mbintr_fn(struct dhd_bus *bus);
++extern void dhd_bus_write_flow_ring_states(struct dhd_bus *bus,
++	void * data, uint16 flowid);
++extern void dhd_bus_read_flow_ring_states(struct dhd_bus *bus,
++	void * data, uint8 flowid);
++extern int dhd_bus_flow_ring_create_request(struct dhd_bus *bus, void *flow_ring_node);
++extern void dhd_bus_clean_flow_ring(struct dhd_bus *bus, void *flow_ring_node);
++extern void dhd_bus_flow_ring_create_response(struct dhd_bus *bus, uint16 flow_id, int32 status);
++extern int dhd_bus_flow_ring_delete_request(struct dhd_bus *bus, void *flow_ring_node);
++extern void dhd_bus_flow_ring_delete_response(struct dhd_bus *bus, uint16 flowid, uint32 status);
++extern int dhd_bus_flow_ring_flush_request(struct dhd_bus *bus, void *flow_ring_node);
++extern void dhd_bus_flow_ring_flush_response(struct dhd_bus *bus, uint16 flowid, uint32 status);
++extern uint32 dhd_bus_max_h2d_queues(struct dhd_bus *bus);
++extern int dhd_bus_schedule_queue(struct dhd_bus *bus, uint16 flow_id, bool txs);
++
++
++extern int dhdpcie_bus_clock_start(struct dhd_bus *bus);
++extern int dhdpcie_bus_clock_stop(struct dhd_bus *bus);
++extern int dhdpcie_bus_enable_device(struct dhd_bus *bus);
++extern int dhdpcie_bus_disable_device(struct dhd_bus *bus);
++extern int dhdpcie_bus_alloc_resource(struct dhd_bus *bus);
++extern void dhdpcie_bus_free_resource(struct dhd_bus *bus);
++extern bool dhdpcie_bus_dongle_attach(struct dhd_bus *bus);
++extern int dhd_bus_release_dongle(struct dhd_bus *bus);
++extern int dhd_bus_request_irq(struct dhd_bus *bus);
++
++
++#ifdef DHD_FW_COREDUMP
++extern int dhd_bus_mem_dump(dhd_pub_t *dhd);
++#endif /* DHD_FW_COREDUMP */
++
++#endif /* BCMPCIE */
++
++#ifdef DHD_ULP
++extern int dhd_bcmsdh_send_buffer(void *bus, uint8 *frame, uint16 len);
++extern void dhd_bus_ulp_bus_wake(void *bus);
++extern void dhd_bus_ulp_disable_console(dhd_pub_t *dhdp);
++extern int dhd_bus_read_sdh_config(void *bus);
++extern void dhd_bus_schedule_dpc(void *bus);
++extern bool dhd_bus_set_default_min_res_mask(struct dhd_bus *bus);
++extern void dhd_bus_pmu_reg_reset(dhd_pub_t *dhdp);
++#endif /* DHD_ULP */
++#endif /* _dhd_bus_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_buzzz.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_buzzz.h
+new file mode 100644
+index 000000000..35d3c07a9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_buzzz.h
+@@ -0,0 +1,37 @@
++#ifndef _DHD_BUZZZ_H_INCLUDED_
++#define _DHD_BUZZZ_H_INCLUDED_
++
++/*
++ * Broadcom logging system - Empty implementaiton
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id$
++ */
++
++#define dhd_buzzz_attach()              do { /* noop */ } while (0)
++#define dhd_buzzz_detach()              do { /* noop */ } while (0)
++#define dhd_buzzz_panic(x)              do { /* noop */ } while (0)
++#define BUZZZ_LOG(ID, N, ARG...)    do { /* noop */ } while (0)
++
++#endif /* _DHD_BUZZZ_H_INCLUDED_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_cdc.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_cdc.c
+new file mode 100644
+index 000000000..28657efae
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_cdc.c
+@@ -0,0 +1,963 @@
++/*
++ * DHD Protocol Module for CDC and BDC.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_cdc.c 708487 2018-10-31 05:33:14Z $
++ *
++ * BDC is like CDC, except it includes a header for data packets to convey
++ * packet priority over the bus, and flags (e.g. to indicate checksum status
++ * for dongle offload.)
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++
++#include <bcmutils.h>
++#include <bcmcdc.h>
++#include <bcmendian.h>
++
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_proto.h>
++#ifdef BCMDBUS
++#include <dbus.h>
++#else
++#include <dhd_bus.h>
++#endif /* BCMDBUS */
++#include <dhd_dbg.h>
++
++
++#ifdef PROP_TXSTATUS
++#include <wlfc_proto.h>
++#include <dhd_wlfc.h>
++#endif
++
++#ifdef LOAD_DHD_WITH_FW_ALIVE
++#include <dhd_chip_info.h>
++#endif
++
++#ifdef DHD_ULP
++#include <dhd_ulp.h>
++#endif /* DHD_ULP */
++
++
++#define RETRIES 2		/* # of retries to retrieve matching ioctl response */
++#define BUS_HEADER_LEN	(24+DHD_SDALIGN)	/* Must be at least SDPCM_RESERVE
++				 * defined in dhd_sdio.c (amount of header tha might be added)
++				 * plus any space that might be needed for alignment padding.
++				 */
++#define ROUND_UP_MARGIN	2048	/* Biggest SDIO block size possible for
++				 * round off at the end of buffer
++				 */
++
++typedef struct dhd_prot {
++	uint16 reqid;
++	uint8 pending;
++	uint32 lastcmd;
++#ifdef BCMDBUS
++	uint ctl_completed;
++#endif
++	uint8 bus_header[BUS_HEADER_LEN];
++	cdc_ioctl_t msg;
++	unsigned char buf[WLC_IOCTL_MAXLEN + ROUND_UP_MARGIN];
++} dhd_prot_t;
++
++#if defined(BCMDBUS)
++extern int dhd_dbus_txdata(dhd_pub_t *dhdp, void *pktbuf);
++#endif
++
++static int
++dhdcdc_msg(dhd_pub_t *dhd)
++{
++#ifdef BCMDBUS
++	int timeout = 0;
++#endif /* BCMDBUS */
++	int err = 0;
++	dhd_prot_t *prot = dhd->prot;
++	int len = ltoh32(prot->msg.len) + sizeof(cdc_ioctl_t);
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	DHD_OS_WAKE_LOCK(dhd);
++
++	/* NOTE : cdc->msg.len holds the desired length of the buffer to be
++	 *        returned. Only up to CDC_MAX_MSG_SIZE of this buffer area
++	 *	  is actually sent to the dongle
++	 */
++	if (len > CDC_MAX_MSG_SIZE)
++		len = CDC_MAX_MSG_SIZE;
++
++	/* Send request */
++#ifdef BCMDBUS
++	DHD_OS_IOCTL_RESP_LOCK(dhd);
++	prot->ctl_completed = FALSE;
++	err = dbus_send_ctl(dhd->dbus, (void *)&prot->msg, len);
++	if (err) {
++		DHD_ERROR(("dbus_send_ctl error=0x%x\n", err));
++		DHD_OS_IOCTL_RESP_UNLOCK(dhd);
++		DHD_OS_WAKE_UNLOCK(dhd);
++		return err;
++	}
++#else
++	err = dhd_bus_txctl(dhd->bus, (uchar*)&prot->msg, len);
++#endif
++
++#ifdef BCMDBUS
++	timeout = dhd_os_ioctl_resp_wait(dhd, &prot->ctl_completed);
++	if ((!timeout) || (!prot->ctl_completed)) {
++		DHD_ERROR(("Txctl timeout %d ctl_completed %d\n",
++			timeout, prot->ctl_completed));
++		DHD_ERROR(("Txctl wait timed out\n"));
++		err = -1;
++	}
++	DHD_OS_IOCTL_RESP_UNLOCK(dhd);
++#endif
++#if defined(BCMDBUS) && defined(INTR_EP_ENABLE)
++	/* If the ctl write is successfully completed, wait for an acknowledgement
++	* that indicates that it is now ok to do ctl read from the dongle
++	*/
++	if (err != -1) {
++		DHD_OS_IOCTL_RESP_LOCK(dhd);
++		prot->ctl_completed = FALSE;
++		if (dbus_poll_intr(dhd->dbus)) {
++			DHD_ERROR(("dbus_poll_intr not submitted\n"));
++		} else {
++			/* interrupt polling is sucessfully submitted. Wait for dongle to send
++			* interrupt
++			*/
++			timeout = dhd_os_ioctl_resp_wait(dhd, &prot->ctl_completed);
++			if (!timeout) {
++				DHD_ERROR(("intr poll wait timed out\n"));
++			}
++		}
++		DHD_OS_IOCTL_RESP_UNLOCK(dhd);
++	}
++#endif /* defined(BCMDBUS) && defined(INTR_EP_ENABLE) */
++	DHD_OS_WAKE_UNLOCK(dhd);
++	return err;
++}
++
++static int
++dhdcdc_cmplt(dhd_pub_t *dhd, uint32 id, uint32 len)
++{
++#ifdef BCMDBUS
++	int timeout = 0;
++#endif /* BCMDBUS */
++	int ret;
++	int cdc_len = len + sizeof(cdc_ioctl_t);
++	dhd_prot_t *prot = dhd->prot;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++
++	do {
++#ifdef BCMDBUS
++		DHD_OS_IOCTL_RESP_LOCK(dhd);
++		prot->ctl_completed = FALSE;
++		ret = dbus_recv_ctl(dhd->dbus, (uchar*)&prot->msg, cdc_len);
++		if (ret) {
++			DHD_ERROR(("dbus_recv_ctl error=0x%x(%d)\n", ret, ret));
++			DHD_OS_IOCTL_RESP_UNLOCK(dhd);
++			goto done;
++		}
++		timeout = dhd_os_ioctl_resp_wait(dhd, &prot->ctl_completed);
++		if ((!timeout) || (!prot->ctl_completed)) {
++			DHD_ERROR(("Rxctl timeout %d ctl_completed %d\n",
++				timeout, prot->ctl_completed));
++			ret = -1;
++			DHD_OS_IOCTL_RESP_UNLOCK(dhd);
++
++			goto done;
++		}
++		DHD_OS_IOCTL_RESP_UNLOCK(dhd);
++
++		ret = cdc_len;
++#else
++		ret = dhd_bus_rxctl(dhd->bus, (uchar*)&prot->msg, cdc_len);
++#endif /* BCMDBUS */
++		if (ret < 0)
++			break;
++	} while (CDC_IOC_ID(ltoh32(prot->msg.flags)) != id);
++
++
++#ifdef BCMDBUS
++done:
++#endif /* BCMDBUS */
++	return ret;
++}
++
++static int
++dhdcdc_query_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len, uint8 action)
++{
++	dhd_prot_t *prot = dhd->prot;
++	cdc_ioctl_t *msg = &prot->msg;
++	int ret = 0, retries = 0;
++	uint32 id, flags = 0;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++	DHD_CTL(("%s: cmd %d len %d\n", __FUNCTION__, cmd, len));
++
++
++	/* Respond "bcmerror" and "bcmerrorstr" with local cache */
++	if (cmd == WLC_GET_VAR && buf)
++	{
++		if (!strcmp((char *)buf, "bcmerrorstr"))
++		{
++			strncpy((char *)buf, bcmerrorstr(dhd->dongle_error), BCME_STRLEN);
++			goto done;
++		}
++		else if (!strcmp((char *)buf, "bcmerror"))
++		{
++			*(int *)buf = dhd->dongle_error;
++			goto done;
++		}
++	}
++
++	memset(msg, 0, sizeof(cdc_ioctl_t));
++
++	msg->cmd = htol32(cmd);
++	msg->len = htol32(len);
++	msg->flags = (++prot->reqid << CDCF_IOC_ID_SHIFT);
++	CDC_SET_IF_IDX(msg, ifidx);
++	/* add additional action bits */
++	action &= WL_IOCTL_ACTION_MASK;
++	msg->flags |= (action << CDCF_IOC_ACTION_SHIFT);
++	msg->flags = htol32(msg->flags);
++
++	if (buf)
++		memcpy(prot->buf, buf, len);
++
++	if ((ret = dhdcdc_msg(dhd)) < 0) {
++		if (!dhd->hang_was_sent)
++		DHD_ERROR(("dhdcdc_query_ioctl: dhdcdc_msg failed w/status %d\n", ret));
++		goto done;
++	}
++
++retry:
++	/* wait for interrupt and get first fragment */
++	if ((ret = dhdcdc_cmplt(dhd, prot->reqid, len)) < 0)
++		goto done;
++
++	flags = ltoh32(msg->flags);
++	id = (flags & CDCF_IOC_ID_MASK) >> CDCF_IOC_ID_SHIFT;
++
++	if ((id < prot->reqid) && (++retries < RETRIES))
++		goto retry;
++	if (id != prot->reqid) {
++		DHD_ERROR(("%s: %s: unexpected request id %d (expected %d)\n",
++		           dhd_ifname(dhd, ifidx), __FUNCTION__, id, prot->reqid));
++		ret = -EINVAL;
++		goto done;
++	}
++
++	/* Copy info buffer */
++	if (buf)
++	{
++		if (ret < (int)len)
++			len = ret;
++		memcpy(buf, (void*) prot->buf, len);
++	}
++
++	/* Check the ERROR flag */
++	if (flags & CDCF_IOC_ERROR)
++	{
++		ret = ltoh32(msg->status);
++		/* Cache error from dongle */
++		dhd->dongle_error = ret;
++	}
++
++done:
++	return ret;
++}
++
++
++static int
++dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len, uint8 action)
++{
++	dhd_prot_t *prot = dhd->prot;
++	cdc_ioctl_t *msg = &prot->msg;
++	int ret = 0;
++	uint32 flags, id;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++	DHD_CTL(("%s: cmd %d len %d\n", __FUNCTION__, cmd, len));
++
++	if (dhd->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s : bus is down. we have nothing to do\n", __FUNCTION__));
++		return -EIO;
++	}
++
++	/* don't talk to the dongle if fw is about to be reloaded */
++	if (dhd->hang_was_sent) {
++		DHD_ERROR(("%s: HANG was sent up earlier. Not talking to the chip\n",
++			__FUNCTION__));
++		return -EIO;
++	}
++
++	memset(msg, 0, sizeof(cdc_ioctl_t));
++
++	msg->cmd = htol32(cmd);
++	msg->len = htol32(len);
++	msg->flags = (++prot->reqid << CDCF_IOC_ID_SHIFT);
++	CDC_SET_IF_IDX(msg, ifidx);
++	/* add additional action bits */
++	action &= WL_IOCTL_ACTION_MASK;
++	msg->flags |= (action << CDCF_IOC_ACTION_SHIFT) | CDCF_IOC_SET;
++	msg->flags = htol32(msg->flags);
++
++	if (buf)
++		memcpy(prot->buf, buf, len);
++
++#ifdef DHD_ULP
++	if (buf && (!strncmp(buf, "wowl_force", sizeof("wowl_force")) ||
++			!strncmp(buf, "ulp", sizeof("ulp")))) {
++		/* force all the writes after this point to NOT to use cached sbwad value */
++		dhd_ulp_disable_cached_sbwad(dhd);
++	}
++#endif /* DHD_ULP */
++
++	if ((ret = dhdcdc_msg(dhd)) < 0) {
++		DHD_ERROR(("%s: dhdcdc_msg failed w/status %d\n", __FUNCTION__, ret));
++		goto done;
++	}
++
++	if ((ret = dhdcdc_cmplt(dhd, prot->reqid, len)) < 0)
++		goto done;
++
++	flags = ltoh32(msg->flags);
++	id = (flags & CDCF_IOC_ID_MASK) >> CDCF_IOC_ID_SHIFT;
++
++	if (id != prot->reqid) {
++		DHD_ERROR(("%s: %s: unexpected request id %d (expected %d)\n",
++		           dhd_ifname(dhd, ifidx), __FUNCTION__, id, prot->reqid));
++		ret = -EINVAL;
++		goto done;
++	}
++
++#ifdef DHD_ULP
++	/* For ulp prototyping temporary */
++	if ((ret = dhd_ulp_check_ulp_request(dhd, buf)) < 0)
++		goto done;
++#endif /* DHD_ULP */
++
++	/* Check the ERROR flag */
++	if (flags & CDCF_IOC_ERROR)
++	{
++		ret = ltoh32(msg->status);
++		/* Cache error from dongle */
++		dhd->dongle_error = ret;
++	}
++
++done:
++	return ret;
++}
++
++#ifdef BCMDBUS
++int
++dhd_prot_ctl_complete(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot;
++
++	if (dhd == NULL)
++		return BCME_ERROR;
++
++	prot = dhd->prot;
++
++	ASSERT(prot);
++	DHD_OS_IOCTL_RESP_LOCK(dhd);
++	prot->ctl_completed = TRUE;
++	dhd_os_ioctl_resp_wake(dhd);
++	DHD_OS_IOCTL_RESP_UNLOCK(dhd);
++	return 0;
++}
++#endif /* BCMDBUS */
++
++int
++dhd_prot_ioctl(dhd_pub_t *dhd, int ifidx, wl_ioctl_t * ioc, void * buf, int len)
++{
++	dhd_prot_t *prot = dhd->prot;
++	int ret = -1;
++	uint8 action;
++
++	if ((dhd->busstate == DHD_BUS_DOWN) || dhd->hang_was_sent) {
++		DHD_ERROR(("%s : bus is down. we have nothing to do\n", __FUNCTION__));
++		goto done;
++	}
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	ASSERT(len <= WLC_IOCTL_MAXLEN);
++
++	if (len > WLC_IOCTL_MAXLEN)
++		goto done;
++
++	if (prot->pending == TRUE) {
++		DHD_ERROR(("CDC packet is pending!!!! cmd=0x%x (%lu) lastcmd=0x%x (%lu)\n",
++			ioc->cmd, (unsigned long)ioc->cmd, prot->lastcmd,
++			(unsigned long)prot->lastcmd));
++		if ((ioc->cmd == WLC_SET_VAR) || (ioc->cmd == WLC_GET_VAR)) {
++			DHD_TRACE(("iovar cmd=%s\n", (char*)buf));
++		}
++		goto done;
++	}
++
++	prot->pending = TRUE;
++	prot->lastcmd = ioc->cmd;
++	action = ioc->set;
++	if (action & WL_IOCTL_ACTION_SET)
++		ret = dhdcdc_set_ioctl(dhd, ifidx, ioc->cmd, buf, len, action);
++	else {
++		ret = dhdcdc_query_ioctl(dhd, ifidx, ioc->cmd, buf, len, action);
++		if (ret > 0)
++			ioc->used = ret - sizeof(cdc_ioctl_t);
++	}
++
++	/* Too many programs assume ioctl() returns 0 on success */
++	if (ret >= 0)
++		ret = 0;
++	else {
++		cdc_ioctl_t *msg = &prot->msg;
++		ioc->needed = ltoh32(msg->len); /* len == needed when set/query fails from dongle */
++	}
++
++	/* Intercept the wme_dp ioctl here */
++	if ((!ret) && (ioc->cmd == WLC_SET_VAR) && (!strcmp(buf, "wme_dp"))) {
++		int slen, val = 0;
++
++		slen = strlen("wme_dp") + 1;
++		if (len >= (int)(slen + sizeof(int)))
++			bcopy(((char *)buf + slen), &val, sizeof(int));
++		dhd->wme_dp = (uint8) ltoh32(val);
++	}
++
++	prot->pending = FALSE;
++
++done:
++
++	return ret;
++}
++
++int
++dhd_prot_iovar_op(dhd_pub_t *dhdp, const char *name,
++                  void *params, int plen, void *arg, int len, bool set)
++{
++	return BCME_UNSUPPORTED;
++}
++
++void
++dhd_prot_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
++{
++	if (!dhdp || !dhdp->prot) {
++		return;
++	}
++
++	bcm_bprintf(strbuf, "Protocol CDC: reqid %d\n", dhdp->prot->reqid);
++#ifdef PROP_TXSTATUS
++	dhd_wlfc_dump(dhdp, strbuf);
++#endif
++}
++
++/*	The FreeBSD PKTPUSH could change the packet buf pinter
++	so we need to make it changable
++*/
++#define PKTBUF pktbuf
++void
++dhd_prot_hdrpush(dhd_pub_t *dhd, int ifidx, void *PKTBUF)
++{
++#ifdef BDC
++	struct bdc_header *h;
++#endif /* BDC */
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++#ifdef BDC
++	/* Push BDC header used to convey priority for buses that don't */
++
++	PKTPUSH(dhd->osh, PKTBUF, BDC_HEADER_LEN);
++
++	h = (struct bdc_header *)PKTDATA(dhd->osh, PKTBUF);
++
++	h->flags = (BDC_PROTO_VER << BDC_FLAG_VER_SHIFT);
++	if (PKTSUMNEEDED(PKTBUF))
++		h->flags |= BDC_FLAG_SUM_NEEDED;
++
++
++	h->priority = (PKTPRIO(PKTBUF) & BDC_PRIORITY_MASK);
++	h->flags2 = 0;
++	h->dataOffset = 0;
++#endif /* BDC */
++	BDC_SET_IF_IDX(h, ifidx);
++}
++#undef PKTBUF	/* Only defined in the above routine */
++
++uint
++dhd_prot_hdrlen(dhd_pub_t *dhd, void *PKTBUF)
++{
++	uint hdrlen = 0;
++#ifdef BDC
++	/* Length of BDC(+WLFC) headers pushed */
++	hdrlen = BDC_HEADER_LEN + (((struct bdc_header *)PKTBUF)->dataOffset * 4);
++#endif
++	return hdrlen;
++}
++
++int
++dhd_prot_hdrpull(dhd_pub_t *dhd, int *ifidx, void *pktbuf, uchar *reorder_buf_info,
++	uint *reorder_info_len)
++{
++#ifdef BDC
++	struct bdc_header *h;
++#endif
++	uint8 data_offset = 0;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++#ifdef BDC
++	if (reorder_info_len)
++		*reorder_info_len = 0;
++	/* Pop BDC header used to convey priority for buses that don't */
++
++	if (PKTLEN(dhd->osh, pktbuf) < BDC_HEADER_LEN) {
++		DHD_ERROR(("%s: rx data too short (%d < %d)\n", __FUNCTION__,
++		           PKTLEN(dhd->osh, pktbuf), BDC_HEADER_LEN));
++		return BCME_ERROR;
++	}
++
++	h = (struct bdc_header *)PKTDATA(dhd->osh, pktbuf);
++
++	if (!ifidx) {
++		/* for tx packet, skip the analysis */
++		data_offset = h->dataOffset;
++		PKTPULL(dhd->osh, pktbuf, BDC_HEADER_LEN);
++		goto exit;
++	}
++
++	*ifidx = BDC_GET_IF_IDX(h);
++
++	if (((h->flags & BDC_FLAG_VER_MASK) >> BDC_FLAG_VER_SHIFT) != BDC_PROTO_VER) {
++		DHD_ERROR(("%s: non-BDC packet received, flags = 0x%x\n",
++		           dhd_ifname(dhd, *ifidx), h->flags));
++		if (((h->flags & BDC_FLAG_VER_MASK) >> BDC_FLAG_VER_SHIFT) == BDC_PROTO_VER_1)
++			h->dataOffset = 0;
++		else
++		return BCME_ERROR;
++	}
++
++	if (h->flags & BDC_FLAG_SUM_GOOD) {
++		DHD_INFO(("%s: BDC packet received with good rx-csum, flags 0x%x\n",
++		          dhd_ifname(dhd, *ifidx), h->flags));
++		PKTSETSUMGOOD(pktbuf, TRUE);
++	}
++
++	PKTSETPRIO(pktbuf, (h->priority & BDC_PRIORITY_MASK));
++	data_offset = h->dataOffset;
++	PKTPULL(dhd->osh, pktbuf, BDC_HEADER_LEN);
++#endif /* BDC */
++
++
++#ifdef PROP_TXSTATUS
++	if (!DHD_PKTTAG_PKTDIR(PKTTAG(pktbuf))) {
++		/*
++		- parse txstatus only for packets that came from the firmware
++		*/
++		dhd_wlfc_parse_header_info(dhd, pktbuf, (data_offset << 2),
++			reorder_buf_info, reorder_info_len);
++
++#ifdef BCMDBUS
++#ifndef DHD_WLFC_THREAD
++		dhd_wlfc_commit_packets(dhd,
++			(f_commitpkt_t)dhd_dbus_txdata, (void *)dhd, NULL, FALSE);
++#endif /* DHD_WLFC_THREAD */
++#endif /* BCMDBUS */
++	}
++#endif /* PROP_TXSTATUS */
++
++exit:
++	PKTPULL(dhd->osh, pktbuf, (data_offset << 2));
++	return 0;
++}
++
++
++int
++dhd_prot_attach(dhd_pub_t *dhd)
++{
++	dhd_prot_t *cdc;
++
++	if (!(cdc = (dhd_prot_t *)DHD_OS_PREALLOC(dhd, DHD_PREALLOC_PROT, sizeof(dhd_prot_t)))) {
++		DHD_ERROR(("%s: kmalloc failed\n", __FUNCTION__));
++		goto fail;
++	}
++	memset(cdc, 0, sizeof(dhd_prot_t));
++
++	/* ensure that the msg buf directly follows the cdc msg struct */
++	if ((uintptr)(&cdc->msg + 1) != (uintptr)cdc->buf) {
++		DHD_ERROR(("dhd_prot_t is not correctly defined\n"));
++		goto fail;
++	}
++
++	dhd->prot = cdc;
++#ifdef BDC
++	dhd->hdrlen += BDC_HEADER_LEN;
++#endif
++	dhd->maxctl = WLC_IOCTL_MAXLEN + sizeof(cdc_ioctl_t) + ROUND_UP_MARGIN;
++	return 0;
++
++fail:
++	if (cdc != NULL)
++		DHD_OS_PREFREE(dhd, cdc, sizeof(dhd_prot_t));
++	return BCME_NOMEM;
++}
++
++/* ~NOTE~ What if another thread is waiting on the semaphore?  Holding it? */
++void
++dhd_prot_detach(dhd_pub_t *dhd)
++{
++#ifdef PROP_TXSTATUS
++	dhd_wlfc_deinit(dhd);
++#endif
++	DHD_OS_PREFREE(dhd, dhd->prot, sizeof(dhd_prot_t));
++	dhd->prot = NULL;
++}
++
++void
++dhd_prot_dstats(dhd_pub_t *dhd)
++{
++	/*  copy bus stats */
++
++	dhd->dstats.tx_packets = dhd->tx_packets;
++	dhd->dstats.tx_errors = dhd->tx_errors;
++	dhd->dstats.rx_packets = dhd->rx_packets;
++	dhd->dstats.rx_errors = dhd->rx_errors;
++	dhd->dstats.rx_dropped = dhd->rx_dropped;
++	dhd->dstats.multicast = dhd->rx_multicast;
++	return;
++}
++
++int
++dhd_sync_with_dongle(dhd_pub_t *dhd)
++{
++	int ret = 0;
++	wlc_rev_info_t revinfo;
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++
++	/* Get the device rev info */
++	memset(&revinfo, 0, sizeof(revinfo));
++	ret = dhd_wl_ioctl_cmd(dhd, WLC_GET_REVINFO, &revinfo, sizeof(revinfo), FALSE, 0);
++	if (ret < 0)
++		goto done;
++
++#if defined(BCMDBUS) && defined(BCMDHDUSB)
++	/* dbus_set_revinfo(dhd->dbus, revinfo.chipnum, revinfo.chiprev); */
++#endif /* BCMDBUS && BCMDHDUSB */
++
++	dhd_process_cid_mac(dhd, TRUE);
++
++#ifdef LOAD_DHD_WITH_FW_ALIVE
++	if(alive == FW_ALIVE_MAGIC) {
++		char buf[WLC_IOCTL_SMLEN];
++
++		memset(buf, 0, sizeof(buf));
++		bcm_mkiovar("cur_etheraddr", 0, 0, buf, sizeof(buf));
++		if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_GET_VAR, buf, sizeof(buf), FALSE, 0)) < 0) {
++		DHD_ERROR(("%s: can't get MAC address , error=%d\n", __FUNCTION__, ret));
++		}
++	/* Update public MAC address after reading from Firmware */
++		memcpy(dhd->mac.octet, buf, ETHER_ADDR_LEN);
++
++	} else
++#endif
++		ret = dhd_preinit_ioctls(dhd);
++
++	if (!ret)
++		dhd_process_cid_mac(dhd, FALSE);
++
++	/* Always assumes wl for now */
++	dhd->iswl = TRUE;
++
++done:
++	return ret;
++}
++
++int dhd_prot_init(dhd_pub_t *dhd)
++{
++	return BCME_OK;
++}
++
++void
++dhd_prot_stop(dhd_pub_t *dhd)
++{
++/* Nothing to do for CDC */
++}
++
++
++static void
++dhd_get_hostreorder_pkts(void *osh, struct reorder_info *ptr, void **pkt,
++	uint32 *pkt_count, void **pplast, uint8 start, uint8 end)
++{
++	void *plast = NULL, *p;
++	uint32 pkt_cnt = 0;
++
++	if (ptr->pend_pkts == 0) {
++		DHD_REORDER(("%s: no packets in reorder queue \n", __FUNCTION__));
++		*pplast = NULL;
++		*pkt_count = 0;
++		*pkt = NULL;
++		return;
++	}
++	do {
++		p = (void *)(ptr->p[start]);
++		ptr->p[start] = NULL;
++
++		if (p != NULL) {
++			if (plast == NULL)
++				*pkt = p;
++			else
++				PKTSETNEXT(osh, plast, p);
++
++			plast = p;
++			pkt_cnt++;
++		}
++		start++;
++		if (start > ptr->max_idx)
++			start = 0;
++	} while (start != end);
++	*pplast = plast;
++	*pkt_count = pkt_cnt;
++	ptr->pend_pkts -= (uint8)pkt_cnt;
++}
++
++int
++dhd_process_pkt_reorder_info(dhd_pub_t *dhd, uchar *reorder_info_buf, uint reorder_info_len,
++	void **pkt, uint32 *pkt_count)
++{
++	uint8 flow_id, max_idx, cur_idx, exp_idx;
++	struct reorder_info *ptr;
++	uint8 flags;
++	void *cur_pkt, *plast = NULL;
++	uint32 cnt = 0;
++
++	if (pkt == NULL) {
++		if (pkt_count != NULL)
++			*pkt_count = 0;
++		return 0;
++	}
++
++	flow_id = reorder_info_buf[WLHOST_REORDERDATA_FLOWID_OFFSET];
++	flags = reorder_info_buf[WLHOST_REORDERDATA_FLAGS_OFFSET];
++
++	DHD_REORDER(("flow_id %d, flags 0x%02x, idx(%d, %d, %d)\n", flow_id, flags,
++		reorder_info_buf[WLHOST_REORDERDATA_CURIDX_OFFSET],
++		reorder_info_buf[WLHOST_REORDERDATA_EXPIDX_OFFSET],
++		reorder_info_buf[WLHOST_REORDERDATA_MAXIDX_OFFSET]));
++
++	/* validate flags and flow id */
++	if (flags == 0xFF) {
++		DHD_ERROR(("%s: invalid flags...so ignore this packet\n", __FUNCTION__));
++		*pkt_count = 1;
++		return 0;
++	}
++
++	cur_pkt = *pkt;
++	*pkt = NULL;
++
++	ptr = dhd->reorder_bufs[flow_id];
++	if (flags & WLHOST_REORDERDATA_DEL_FLOW) {
++		uint32 buf_size = sizeof(struct reorder_info);
++
++		DHD_REORDER(("%s: Flags indicating to delete a flow id %d\n",
++			__FUNCTION__, flow_id));
++
++		if (ptr == NULL) {
++			DHD_REORDER(("%s: received flags to cleanup, but no flow (%d) yet\n",
++				__FUNCTION__, flow_id));
++			*pkt_count = 1;
++			*pkt = cur_pkt;
++			return 0;
++		}
++
++		dhd_get_hostreorder_pkts(dhd->osh, ptr, pkt, &cnt, &plast,
++			ptr->exp_idx, ptr->exp_idx);
++		/* set it to the last packet */
++		if (plast) {
++			PKTSETNEXT(dhd->osh, plast, cur_pkt);
++			cnt++;
++		}
++		else {
++			if (cnt != 0) {
++				DHD_ERROR(("%s: del flow: something fishy, pending packets %d\n",
++					__FUNCTION__, cnt));
++			}
++			*pkt = cur_pkt;
++			cnt = 1;
++		}
++		buf_size += ((ptr->max_idx + 1) * sizeof(void *));
++		MFREE(dhd->osh, ptr, buf_size);
++		dhd->reorder_bufs[flow_id] = NULL;
++		*pkt_count = cnt;
++		return 0;
++	}
++	/* all the other cases depend on the existance of the reorder struct for that flow id */
++	if (ptr == NULL) {
++		uint32 buf_size_alloc = sizeof(reorder_info_t);
++		max_idx = reorder_info_buf[WLHOST_REORDERDATA_MAXIDX_OFFSET];
++
++		buf_size_alloc += ((max_idx + 1) * sizeof(void*));
++		/* allocate space to hold the buffers, index etc */
++
++		DHD_REORDER(("%s: alloc buffer of size %d size, reorder info id %d, maxidx %d\n",
++			__FUNCTION__, buf_size_alloc, flow_id, max_idx));
++		ptr = (struct reorder_info *)MALLOC(dhd->osh, buf_size_alloc);
++		if (ptr == NULL) {
++			DHD_ERROR(("%s: Malloc failed to alloc buffer\n", __FUNCTION__));
++			*pkt_count = 1;
++			return 0;
++		}
++		bzero(ptr, buf_size_alloc);
++		dhd->reorder_bufs[flow_id] = ptr;
++		ptr->p = (void *)(ptr+1);
++		ptr->max_idx = max_idx;
++	}
++	if (flags & WLHOST_REORDERDATA_NEW_HOLE)  {
++		DHD_REORDER(("%s: new hole, so cleanup pending buffers\n", __FUNCTION__));
++		if (ptr->pend_pkts) {
++			dhd_get_hostreorder_pkts(dhd->osh, ptr, pkt, &cnt, &plast,
++				ptr->exp_idx, ptr->exp_idx);
++			ptr->pend_pkts = 0;
++		}
++		ptr->cur_idx = reorder_info_buf[WLHOST_REORDERDATA_CURIDX_OFFSET];
++		ptr->exp_idx = reorder_info_buf[WLHOST_REORDERDATA_EXPIDX_OFFSET];
++		ptr->max_idx = reorder_info_buf[WLHOST_REORDERDATA_MAXIDX_OFFSET];
++		ptr->p[ptr->cur_idx] = cur_pkt;
++		ptr->pend_pkts++;
++		*pkt_count = cnt;
++	}
++	else if (flags & WLHOST_REORDERDATA_CURIDX_VALID) {
++		cur_idx = reorder_info_buf[WLHOST_REORDERDATA_CURIDX_OFFSET];
++		exp_idx = reorder_info_buf[WLHOST_REORDERDATA_EXPIDX_OFFSET];
++
++
++		if ((exp_idx == ptr->exp_idx) && (cur_idx != ptr->exp_idx)) {
++			/* still in the current hole */
++			/* enqueue the current on the buffer chain */
++			if (ptr->p[cur_idx] != NULL) {
++				DHD_REORDER(("%s: HOLE: ERROR buffer pending..free it\n",
++					__FUNCTION__));
++				PKTFREE(dhd->osh, ptr->p[cur_idx], TRUE);
++				ptr->p[cur_idx] = NULL;
++			}
++			ptr->p[cur_idx] = cur_pkt;
++			ptr->pend_pkts++;
++			ptr->cur_idx = cur_idx;
++			DHD_REORDER(("%s: fill up a hole..pending packets is %d\n",
++				__FUNCTION__, ptr->pend_pkts));
++			*pkt_count = 0;
++			*pkt = NULL;
++		}
++		else if (ptr->exp_idx == cur_idx) {
++			/* got the right one ..flush from cur to exp and update exp */
++			DHD_REORDER(("%s: got the right one now, cur_idx is %d\n",
++				__FUNCTION__, cur_idx));
++			if (ptr->p[cur_idx] != NULL) {
++				DHD_REORDER(("%s: Error buffer pending..free it\n",
++					__FUNCTION__));
++				PKTFREE(dhd->osh, ptr->p[cur_idx], TRUE);
++				ptr->p[cur_idx] = NULL;
++			}
++			ptr->p[cur_idx] = cur_pkt;
++			ptr->pend_pkts++;
++
++			ptr->cur_idx = cur_idx;
++			ptr->exp_idx = exp_idx;
++
++			dhd_get_hostreorder_pkts(dhd->osh, ptr, pkt, &cnt, &plast,
++				cur_idx, exp_idx);
++			*pkt_count = cnt;
++			DHD_REORDER(("%s: freeing up buffers %d, still pending %d\n",
++				__FUNCTION__, cnt, ptr->pend_pkts));
++		}
++		else {
++			uint8 end_idx;
++			bool flush_current = FALSE;
++			/* both cur and exp are moved now .. */
++			DHD_REORDER(("%s:, flow %d, both moved, cur %d(%d), exp %d(%d)\n",
++				__FUNCTION__, flow_id, ptr->cur_idx, cur_idx,
++				ptr->exp_idx, exp_idx));
++			if (flags & WLHOST_REORDERDATA_FLUSH_ALL)
++				end_idx = ptr->exp_idx;
++			else
++				end_idx = exp_idx;
++
++			/* flush pkts first */
++			dhd_get_hostreorder_pkts(dhd->osh, ptr, pkt, &cnt, &plast,
++				ptr->exp_idx, end_idx);
++
++			if (cur_idx == ptr->max_idx) {
++				if (exp_idx == 0)
++					flush_current = TRUE;
++			} else {
++				if (exp_idx == cur_idx + 1)
++					flush_current = TRUE;
++			}
++			if (flush_current) {
++				if (plast)
++					PKTSETNEXT(dhd->osh, plast, cur_pkt);
++				else
++					*pkt = cur_pkt;
++				cnt++;
++			}
++			else {
++				ptr->p[cur_idx] = cur_pkt;
++				ptr->pend_pkts++;
++			}
++			ptr->exp_idx = exp_idx;
++			ptr->cur_idx = cur_idx;
++			*pkt_count = cnt;
++		}
++	}
++	else {
++		uint8 end_idx;
++		/* no real packet but update to exp_seq...that means explicit window move */
++		exp_idx = reorder_info_buf[WLHOST_REORDERDATA_EXPIDX_OFFSET];
++
++		DHD_REORDER(("%s: move the window, cur_idx is %d, exp is %d, new exp is %d\n",
++			__FUNCTION__, ptr->cur_idx, ptr->exp_idx, exp_idx));
++		if (flags & WLHOST_REORDERDATA_FLUSH_ALL)
++			end_idx =  ptr->exp_idx;
++		else
++			end_idx =  exp_idx;
++
++		dhd_get_hostreorder_pkts(dhd->osh, ptr, pkt, &cnt, &plast, ptr->exp_idx, end_idx);
++		if (plast)
++			PKTSETNEXT(dhd->osh, plast, cur_pkt);
++		else
++			*pkt = cur_pkt;
++		cnt++;
++		*pkt_count = cnt;
++		/* set the new expected idx */
++		ptr->exp_idx = exp_idx;
++	}
++	return 0;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_cfg80211.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_cfg80211.c
+new file mode 100644
+index 000000000..dc4d4d527
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_cfg80211.c
+@@ -0,0 +1,268 @@
++/*
++ * Linux cfg80211 driver - Dongle Host Driver (DHD) related
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfg80211.c,v 1.1.4.1.2.14 2011/02/09 01:40:07 Exp $
++ */
++
++#include <linux/vmalloc.h>
++#include <net/rtnetlink.h>
++
++#include <bcmutils.h>
++#include <wldev_common.h>
++#include <wl_cfg80211.h>
++#include <dhd_cfg80211.h>
++
++#ifdef PKT_FILTER_SUPPORT
++#include <dngl_stats.h>
++#include <dhd.h>
++#endif
++
++extern struct bcm_cfg80211 *g_bcm_cfg;
++
++#ifdef PKT_FILTER_SUPPORT
++extern uint dhd_pkt_filter_enable;
++extern uint dhd_master_mode;
++extern void dhd_pktfilter_offload_enable(dhd_pub_t * dhd, char *arg, int enable, int master_mode);
++#endif
++
++static int dhd_dongle_up = FALSE;
++
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhdioctl.h>
++#include <wlioctl.h>
++#include <brcm_nl80211.h>
++#include <dhd_cfg80211.h>
++
++static s32 wl_dongle_up(struct net_device *ndev);
++static s32 wl_dongle_down(struct net_device *ndev);
++
++/**
++ * Function implementations
++ */
++
++s32 dhd_cfg80211_init(struct bcm_cfg80211 *cfg)
++{
++	dhd_dongle_up = FALSE;
++	return 0;
++}
++
++s32 dhd_cfg80211_deinit(struct bcm_cfg80211 *cfg)
++{
++	dhd_dongle_up = FALSE;
++	return 0;
++}
++
++s32 dhd_cfg80211_down(struct bcm_cfg80211 *cfg)
++{
++	struct net_device *ndev;
++	s32 err = 0;
++
++	WL_TRACE(("In\n"));
++	if (!dhd_dongle_up) {
++		WL_ERR(("Dongle is already down\n"));
++		return err;
++	}
++
++	ndev = bcmcfg_to_prmry_ndev(cfg);
++	wl_dongle_down(ndev);
++	dhd_dongle_up = FALSE;
++	return 0;
++}
++
++s32 dhd_cfg80211_set_p2p_info(struct bcm_cfg80211 *cfg, int val)
++{
++	dhd_pub_t *dhd =  (dhd_pub_t *)(cfg->pub);
++	dhd->op_mode |= val;
++	WL_ERR(("Set : op_mode=0x%04x\n", dhd->op_mode));
++#ifdef ARP_OFFLOAD_SUPPORT
++	if (dhd->arp_version == 1) {
++		/* IF P2P is enabled, disable arpoe */
++		dhd_arp_offload_set(dhd, 0);
++		dhd_arp_offload_enable(dhd, false);
++	}
++#endif /* ARP_OFFLOAD_SUPPORT */
++
++	return 0;
++}
++
++s32 dhd_cfg80211_clean_p2p_info(struct bcm_cfg80211 *cfg)
++{
++	dhd_pub_t *dhd =  (dhd_pub_t *)(cfg->pub);
++	dhd->op_mode &= ~(DHD_FLAG_P2P_GC_MODE | DHD_FLAG_P2P_GO_MODE);
++	WL_ERR(("Clean : op_mode=0x%04x\n", dhd->op_mode));
++
++#ifdef ARP_OFFLOAD_SUPPORT
++	if (dhd->arp_version == 1) {
++		/* IF P2P is disabled, enable arpoe back for STA mode. */
++		dhd_arp_offload_set(dhd, dhd_arp_mode);
++		dhd_arp_offload_enable(dhd, true);
++	}
++#endif /* ARP_OFFLOAD_SUPPORT */
++
++	return 0;
++}
++
++struct net_device* wl_cfg80211_allocate_if(struct bcm_cfg80211 *cfg, int ifidx, char *name,
++	uint8 *mac, uint8 bssidx, char *dngl_name)
++{
++	return dhd_allocate_if(cfg->pub, ifidx, name, mac, bssidx, FALSE, dngl_name);
++}
++
++int wl_cfg80211_register_if(struct bcm_cfg80211 *cfg, int ifidx, struct net_device* ndev)
++{
++	return dhd_register_if(cfg->pub, ifidx, FALSE);
++}
++
++int wl_cfg80211_remove_if(struct bcm_cfg80211 *cfg, int ifidx, struct net_device* ndev)
++{
++	return dhd_remove_if(cfg->pub, ifidx, FALSE);
++}
++
++struct net_device * dhd_cfg80211_netdev_free(struct net_device *ndev)
++{
++	if (ndev) {
++		if (ndev->ieee80211_ptr) {
++			kfree(ndev->ieee80211_ptr);
++			ndev->ieee80211_ptr = NULL;
++		}
++		free_netdev(ndev);
++		return NULL;
++	}
++
++	return ndev;
++}
++
++void dhd_netdev_free(struct net_device *ndev)
++{
++#ifdef WL_CFG80211
++	ndev = dhd_cfg80211_netdev_free(ndev);
++#endif
++	if (ndev)
++		free_netdev(ndev);
++}
++
++static s32
++wl_dongle_up(struct net_device *ndev)
++{
++	s32 err = 0;
++	u32 up = 0;
++
++	err = wldev_ioctl(ndev, WLC_UP, &up, sizeof(up), true);
++	if (unlikely(err)) {
++		WL_ERR(("WLC_UP error (%d)\n", err));
++	}
++	return err;
++}
++
++static s32
++wl_dongle_down(struct net_device *ndev)
++{
++	s32 err = 0;
++	u32 down = 0;
++
++	err = wldev_ioctl(ndev, WLC_DOWN, &down, sizeof(down), true);
++	if (unlikely(err)) {
++		WL_ERR(("WLC_DOWN error (%d)\n", err));
++	}
++	return err;
++}
++
++
++s32 dhd_config_dongle(struct bcm_cfg80211 *cfg)
++{
++#ifndef DHD_SDALIGN
++#define DHD_SDALIGN	32
++#endif
++	struct net_device *ndev;
++	s32 err = 0;
++
++	WL_TRACE(("In\n"));
++	if (dhd_dongle_up) {
++		WL_ERR(("Dongle is already up\n"));
++		return err;
++	}
++
++	ndev = bcmcfg_to_prmry_ndev(cfg);
++
++	err = wl_dongle_up(ndev);
++	if (unlikely(err)) {
++		WL_ERR(("wl_dongle_up failed\n"));
++		goto default_conf_out;
++	}
++	dhd_dongle_up = true;
++
++default_conf_out:
++
++	return err;
++
++}
++
++int dhd_cfgvendor_priv_string_handler(struct bcm_cfg80211 *cfg, struct wireless_dev *wdev,
++	const struct bcm_nlmsg_hdr *nlioc, void *buf)
++{
++	struct net_device *ndev = NULL;
++	dhd_pub_t *dhd;
++	dhd_ioctl_t ioc = { 0 };
++	int ret = 0;
++	int8 index;
++
++	WL_TRACE(("entry: cmd = %d\n", nlioc->cmd));
++
++	dhd = cfg->pub;
++	DHD_OS_WAKE_LOCK(dhd);
++
++	/* send to dongle only if we are not waiting for reload already */
++	if (dhd->hang_was_sent) {
++		WL_ERR(("HANG was sent up earlier\n"));
++		DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_ENABLE(dhd, DHD_EVENT_TIMEOUT_MS);
++		DHD_OS_WAKE_UNLOCK(dhd);
++		return OSL_ERROR(BCME_DONGLE_DOWN);
++	}
++
++	ndev = wdev_to_wlc_ndev(wdev, cfg);
++	index = dhd_net2idx(dhd->info, ndev);
++	if (index == DHD_BAD_IF) {
++		WL_ERR(("Bad ifidx from wdev:%p\n", wdev));
++		ret = BCME_ERROR;
++		goto done;
++	}
++
++	ioc.cmd = nlioc->cmd;
++	ioc.len = nlioc->len;
++	ioc.set = nlioc->set;
++	ioc.driver = nlioc->magic;
++	ret = dhd_ioctl_process(dhd, index, &ioc, buf);
++	if (ret) {
++		WL_TRACE(("dhd_ioctl_process return err %d\n", ret));
++		ret = OSL_ERROR(ret);
++		goto done;
++	}
++
++done:
++	DHD_OS_WAKE_UNLOCK(dhd);
++	return ret;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_cfg80211.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_cfg80211.h
+new file mode 100644
+index 000000000..2fff251e1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_cfg80211.h
+@@ -0,0 +1,54 @@
++/*
++ * Linux cfg80211 driver - Dongle Host Driver (DHD) related
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfg80211.c,v 1.1.4.1.2.14 2011/02/09 01:40:07 Exp $
++ */
++
++
++#ifndef __DHD_CFG80211__
++#define __DHD_CFG80211__
++
++#include <wl_cfg80211.h>
++#include <wl_cfgp2p.h>
++#include <brcm_nl80211.h>
++
++#ifndef WL_ERR
++#define WL_ERR CFG80211_ERR
++#endif
++#ifndef WL_TRACE
++#define WL_TRACE CFG80211_TRACE
++#endif
++
++s32 dhd_cfg80211_init(struct bcm_cfg80211 *cfg);
++s32 dhd_cfg80211_deinit(struct bcm_cfg80211 *cfg);
++s32 dhd_cfg80211_down(struct bcm_cfg80211 *cfg);
++s32 dhd_cfg80211_set_p2p_info(struct bcm_cfg80211 *cfg, int val);
++s32 dhd_cfg80211_clean_p2p_info(struct bcm_cfg80211 *cfg);
++s32 dhd_config_dongle(struct bcm_cfg80211 *cfg);
++int dhd_cfgvendor_priv_string_handler(struct bcm_cfg80211 *cfg,
++	struct wireless_dev *wdev, const struct bcm_nlmsg_hdr *nlioc, void  *data);
++
++#endif /* __DHD_CFG80211__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_cfg_vendor.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_cfg_vendor.c
+new file mode 100644
+index 000000000..3da36aa65
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_cfg_vendor.c
+@@ -0,0 +1,174 @@
++/*
++ * Linux cfg80211 vendor command/event handlers of DHD
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_cfg_vendor.c 525516 2015-01-09 23:12:53Z $
++ */
++
++#include <linux/vmalloc.h>
++#include <linuxver.h>
++#include <net/cfg80211.h>
++#include <net/netlink.h>
++
++#include <bcmutils.h>
++#include <wl_cfg80211.h>
++#include <wl_cfgvendor.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_dbg.h>
++#include <dhdioctl.h>
++#include <brcm_nl80211.h>
++
++#ifdef VENDOR_EXT_SUPPORT
++static int dhd_cfgvendor_priv_string_handler(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	const struct bcm_nlmsg_hdr *nlioc = data;
++	struct net_device *ndev = NULL;
++	struct bcm_cfg80211 *cfg;
++	struct sk_buff *reply;
++	void *buf = NULL, *cur;
++	dhd_pub_t *dhd;
++	dhd_ioctl_t ioc = { 0 };
++	int ret = 0, ret_len, payload, msglen;
++	int maxmsglen = PAGE_SIZE - 0x100;
++	int8 index;
++
++	WL_TRACE(("entry: cmd = %d\n", nlioc->cmd));
++	DHD_ERROR(("entry: cmd = %d\n", nlioc->cmd));
++
++	cfg = wiphy_priv(wiphy);
++	dhd = cfg->pub;
++
++	DHD_OS_WAKE_LOCK(dhd);
++
++	/* send to dongle only if we are not waiting for reload already */
++	if (dhd->hang_was_sent) {
++		WL_ERR(("HANG was sent up earlier\n"));
++		DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_ENABLE(dhd, DHD_EVENT_TIMEOUT_MS);
++		DHD_OS_WAKE_UNLOCK(dhd);
++		return OSL_ERROR(BCME_DONGLE_DOWN);
++	}
++
++	len -= sizeof(struct bcm_nlmsg_hdr);
++	ret_len = nlioc->len;
++	if (ret_len > 0 || len > 0) {
++		if (len > DHD_IOCTL_MAXLEN) {
++			WL_ERR(("oversize input buffer %d\n", len));
++			len = DHD_IOCTL_MAXLEN;
++		}
++		if (ret_len > DHD_IOCTL_MAXLEN) {
++			WL_ERR(("oversize return buffer %d\n", ret_len));
++			ret_len = DHD_IOCTL_MAXLEN;
++		}
++		payload = max(ret_len, len) + 1;
++		buf = vzalloc(payload);
++		if (!buf) {
++			DHD_OS_WAKE_UNLOCK(dhd);
++			return -ENOMEM;
++		}
++		memcpy(buf, (void *)nlioc + nlioc->offset, len);
++		*(char *)(buf + len) = '\0';
++	}
++
++	ndev = wdev_to_wlc_ndev(wdev, cfg);
++	index = dhd_net2idx(dhd->info, ndev);
++	if (index == DHD_BAD_IF) {
++		WL_ERR(("Bad ifidx from wdev:%p\n", wdev));
++		ret = BCME_ERROR;
++		goto done;
++	}
++
++	ioc.cmd = nlioc->cmd;
++	ioc.len = nlioc->len;
++	ioc.set = nlioc->set;
++	ioc.driver = nlioc->magic;
++	ret = dhd_ioctl_process(dhd, index, &ioc, buf);
++	if (ret) {
++		WL_TRACE(("dhd_ioctl_process return err %d\n", ret));
++		ret = OSL_ERROR(ret);
++		goto done;
++	}
++
++	cur = buf;
++	while (ret_len > 0) {
++		msglen = nlioc->len > maxmsglen ? maxmsglen : ret_len;
++		ret_len -= msglen;
++		payload = msglen + sizeof(msglen);
++		reply = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, payload);
++		if (!reply) {
++			WL_ERR(("Failed to allocate reply msg\n"));
++			ret = -ENOMEM;
++			break;
++		}
++
++		if (nla_put(reply, BCM_NLATTR_DATA, msglen, cur) ||
++			nla_put_u16(reply, BCM_NLATTR_LEN, msglen)) {
++			kfree_skb(reply);
++			ret = -ENOBUFS;
++			break;
++		}
++
++		ret = cfg80211_vendor_cmd_reply(reply);
++		if (ret) {
++			WL_ERR(("testmode reply failed:%d\n", ret));
++			break;
++		}
++		cur += msglen;
++	}
++
++done:
++	vfree(buf);
++	DHD_OS_WAKE_UNLOCK(dhd);
++	return ret;
++}
++
++const struct wiphy_vendor_command dhd_cfgvendor_cmds [] = {
++	{
++		{
++			.vendor_id = OUI_BRCM,
++			.subcmd = BRCM_VENDOR_SCMD_PRIV_STR
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = dhd_cfgvendor_priv_string_handler
++	},
++};
++
++int cfgvendor_attach(struct wiphy *wiphy)
++{
++	wiphy->vendor_commands	= dhd_cfgvendor_cmds;
++	wiphy->n_vendor_commands = ARRAY_SIZE(dhd_cfgvendor_cmds);
++
++	return 0;
++}
++
++int cfgvendor_detach(struct wiphy *wiphy)
++{
++	wiphy->vendor_commands  = NULL;
++	wiphy->n_vendor_commands = 0;
++
++	return 0;
++}
++#endif /* VENDOR_EXT_SUPPORT */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_chip_info.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_chip_info.c
+new file mode 100644
+index 000000000..f5eb44b12
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_chip_info.c
+@@ -0,0 +1,38 @@
++#include "dhd_chip_info.h"
++
++#ifdef LOAD_DHD_WITH_FW_ALIVE
++int alive = 0;
++int card_dev = 0;
++int card_rev = 0;
++
++
++uint32	bcm43430_coreid[] = {
++0x00000800,0x00000812,0x00000829,0x0000082a,0x0000080e,0x00000240};
++uint32  bcm43430_coresba[] = {
++0x18000000,0x18001000,0x18002000,0x18003000,0x18004000,0x19000000};
++uint32  bcm43430_coresba_size[] = {
++0x00001000,0x00001000,0x00001000,0x00001000,0x00001000,0x01000000};
++uint32  bcm43430_wrapba[] = {
++0x18100000,0x18101000,0x18102000,0x18103000,0x18104000,0x18106000};
++uint32  bcm43430_cia[] = {
++0x4bf80001,0x4bf81201,0x4bf82901,0x4bf82a01,0x4bf80e01,0x43b24001};
++uint32  bcm43430_cib[] = {
++0x31004211,0x27004211,0x15004211,0x09004211,0x16080401,0x00080201};
++
++uint32  bcm43436_cib[] = {
++0x31004211,0x27004211,0x18004211,0x0b004211,0x19080401,0x00080201};
++
++
++int sii_pub_43430[] = {
++0x00000001,0x00000003,0x00000829,0x00000015,0x00000002,0x00000031,0x10400000,0x0000001e,
++0x00000018,0x39d25f18,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0000a9a6,
++0x00000000,0x00000003,0x30c21b01,0x00000000,0x00000000,0x00000000,
++};
++
++int sii_pub_43436[] = {
++0x00000001,0x00000003,0x00000829,0x00000018,0x00000002,0x00000031,0x10400000,0x0000001e,
++0x00000018,0x39d25f18,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0000a9a6,
++0x00000002,0x00000004,0x40c01b01,0x00000000,0x00000000,0x00000000,
++};
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_chip_info.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_chip_info.h
+new file mode 100644
+index 000000000..1f9764bc7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_chip_info.h
+@@ -0,0 +1,43 @@
++#ifndef __dhd_chip_info_h__
++#define __dhd_chip_info_h__
++
++#ifdef LOAD_DHD_WITH_FW_ALIVE
++
++#include <typedefs.h>
++
++#define chip_info_dump 0
++
++#define ai_core_43341 7
++#define oob_router_43341 0x18108000
++
++#define ai_core_43430 6
++#define oob_router_43430 0x18107000
++#define FW_ALIVE_MAGIC 0x151515
++
++extern int alive;
++extern int card_dev;
++extern int card_rev;
++
++extern uint32	bcm43341_coreid[];
++extern uint32	bcm43341_coresba[];
++extern uint32	bcm43341_coresba_size[];
++extern uint32	bcm43341_coresba2_size[];
++extern uint32	bcm43341_wrapba[];
++extern uint32	bcm43341_cia[];
++extern uint32	bcm43341_cib[];
++
++extern uint32	bcm43430_coreid[];
++extern uint32	bcm43430_coresba[];
++extern uint32	bcm43430_coresba_size[];
++extern uint32	bcm43430_wrapba[];
++extern uint32	bcm43430_cia[];
++extern uint32	bcm43430_cib[];
++extern uint32	bcm43436_cib[];
++
++extern int	sii_pub_43341[];
++extern int	sii_pub_43430[];
++extern int	sii_pub_43436[];
++
++#endif	//LOAD_DHD_WITH_FW_ALIVE
++
++#endif	//__dhd_chip_info_h__
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_common.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_common.c
+new file mode 100644
+index 000000000..eadb63d6d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_common.c
+@@ -0,0 +1,3467 @@
++/*
++ * Broadcom Dongle Host Driver (DHD), common DHD core.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_common.c 692262 2018-07-04 09:30:26Z $
++ */
++#include <typedefs.h>
++#include <osl.h>
++
++#include <epivers.h>
++#include <bcmutils.h>
++
++#include <bcmendian.h>
++#include <dngl_stats.h>
++#include <wlioctl.h>
++#include <dhd.h>
++#include <dhd_ip.h>
++#include <proto/bcmevent.h>
++
++#ifdef SHOW_LOGTRACE
++#include <event_log.h>
++#endif /* SHOW_LOGTRACE */
++
++#ifdef BCMPCIE
++#include <dhd_flowring.h>
++#endif
++
++#ifdef BCMDBUS
++#include <dbus.h>
++#else
++#include <dhd_bus.h>
++#endif /* BCMDBUS */
++#include <dhd_proto.h>
++#include <dhd_dbg.h>
++#include <dhd_debug.h>
++#include <msgtrace.h>
++
++#ifdef WL_CFG80211
++#include <wl_cfg80211.h>
++#endif
++#ifdef PNO_SUPPORT
++#include <dhd_pno.h>
++#endif
++#ifdef RTT_SUPPORT
++#include <dhd_rtt.h>
++#endif
++
++#ifdef PROP_TXSTATUS
++#include <wlfc_proto.h>
++#include <dhd_wlfc.h>
++#endif
++
++#ifdef DHD_WMF
++#include <dhd_linux.h>
++#include <dhd_wmf_linux.h>
++#endif /* DHD_WMF */
++
++#ifdef DHD_L2_FILTER
++#include <dhd_l2_filter.h>
++#endif /* DHD_L2_FILTER */
++
++#ifdef DHD_PSTA
++#include <dhd_psta.h>
++#endif /* DHD_PSTA */
++
++#ifdef DHD_WET
++#include <dhd_wet.h>
++#endif /* DHD_WET */
++
++#ifdef WLMEDIA_HTSF
++extern void htsf_update(struct dhd_info *dhd, void *data);
++#endif
++
++int dhd_msg_level = DHD_ERROR_VAL | DHD_MSGTRACE_VAL | DHD_EVENT_VAL;
++
++
++#if defined(WL_WLC_SHIM)
++#include <wl_shim.h>
++#else
++#endif /* WL_WLC_SHIM */
++
++#include <wl_iw.h>
++
++#ifdef DHD_ULP
++#include <dhd_ulp.h>
++#endif /* DHD_ULP */
++
++#ifdef SOFTAP
++char fw_path2[MOD_PARAM_PATHLEN];
++extern bool softap_enabled;
++#endif
++
++#ifdef DHD_DEBUG
++#include <sdiovar.h>
++#endif /* DHD_DEBUG */
++
++/* Last connection success/failure status */
++uint32 dhd_conn_event;
++uint32 dhd_conn_status;
++uint32 dhd_conn_reason;
++
++extern int dhd_iscan_request(void * dhdp, uint16 action);
++extern void dhd_ind_scan_confirm(void *h, bool status);
++extern int dhd_iscan_in_progress(void *h);
++void dhd_iscan_lock(void);
++void dhd_iscan_unlock(void);
++extern int dhd_change_mtu(dhd_pub_t *dhd, int new_mtu, int ifidx);
++#if !defined(AP) && defined(WLP2P)
++extern int dhd_get_concurrent_capabilites(dhd_pub_t *dhd);
++#endif
++
++#ifdef BCMDHDUSB
++int dhd_socram_dump(struct dhd_bus *bus) { return -1; }
++#else
++extern int dhd_socram_dump(struct dhd_bus *bus);
++#endif /* BCMDHDUSB */
++
++#define MAX_CHUNK_LEN 1408 /* 8 * 8 * 22 */
++
++bool ap_cfg_running = FALSE;
++bool ap_fw_loaded = FALSE;
++
++/* Version string to report */
++#ifdef DHD_DEBUG
++#ifndef SRCBASE
++#define SRCBASE        "drivers/net/wireless/bcmdhd"
++#endif
++#define DHD_COMPILED "\nCompiled in " SRCBASE
++#endif /* DHD_DEBUG */
++
++#if defined(DHD_DEBUG)
++const char dhd_version[] = "Dongle Host Driver, version " EPI_VERSION_STR
++	DHD_COMPILED " on " __DATE__ " at " __TIME__;
++#else
++const char dhd_version[] = "\nDongle Host Driver, version " EPI_VERSION_STR "\nCompiled from ";
++#endif 
++
++void dhd_set_timer(void *bus, uint wdtick);
++
++#if defined(TRAFFIC_MGMT_DWM)
++static int traffic_mgmt_add_dwm_filter(dhd_pub_t *dhd,
++	trf_mgmt_filter_list_t * trf_mgmt_filter_list, int len);
++#endif
++
++#ifdef HOST_FLAG
++extern int hostsleep;
++#endif
++
++/* IOVar table */
++enum {
++	IOV_VERSION = 1,
++	IOV_MSGLEVEL,
++	IOV_BCMERRORSTR,
++	IOV_BCMERROR,
++	IOV_WDTICK,
++	IOV_DUMP,
++	IOV_CLEARCOUNTS,
++	IOV_LOGDUMP,
++	IOV_LOGCAL,
++	IOV_LOGSTAMP,
++	IOV_GPIOOB,
++	IOV_IOCTLTIMEOUT,
++#if defined(DHD_DEBUG)
++	IOV_CONS,
++	IOV_DCONSOLE_POLL,
++	IOV_DHD_JOIN_TIMEOUT_DBG,
++	IOV_SCAN_TIMEOUT,
++#endif /* defined(DHD_DEBUG) */
++#ifdef PROP_TXSTATUS
++	IOV_PROPTXSTATUS_ENABLE,
++	IOV_PROPTXSTATUS_MODE,
++	IOV_PROPTXSTATUS_OPT,
++	IOV_PROPTXSTATUS_MODULE_IGNORE,
++	IOV_PROPTXSTATUS_CREDIT_IGNORE,
++	IOV_PROPTXSTATUS_TXSTATUS_IGNORE,
++	IOV_PROPTXSTATUS_RXPKT_CHK,
++#endif /* PROP_TXSTATUS */
++	IOV_BUS_TYPE,
++#ifdef WLMEDIA_HTSF
++	IOV_WLPKTDLYSTAT_SZ,
++#endif
++	IOV_CHANGEMTU,
++	IOV_HOSTREORDER_FLOWS,
++#ifdef DHDTCPACK_SUPPRESS
++	IOV_TCPACK_SUPPRESS,
++#endif /* DHDTCPACK_SUPPRESS */
++#ifdef DHD_WMF
++	IOV_WMF_BSS_ENAB,
++	IOV_WMF_UCAST_IGMP,
++	IOV_WMF_MCAST_DATA_SENDUP,
++#ifdef WL_IGMP_UCQUERY
++	IOV_WMF_UCAST_IGMP_QUERY,
++#endif /* WL_IGMP_UCQUERY */
++#ifdef DHD_UCAST_UPNP
++	IOV_WMF_UCAST_UPNP,
++#endif /* DHD_UCAST_UPNP */
++	IOV_WMF_PSTA_DISABLE,
++#endif /* DHD_WMF */
++#if defined(TRAFFIC_MGMT_DWM)
++	IOV_TRAFFIC_MGMT_DWM,
++#endif 
++	IOV_AP_ISOLATE,
++#ifdef DHD_L2_FILTER
++	IOV_DHCP_UNICAST,
++	IOV_BLOCK_PING,
++	IOV_PROXY_ARP,
++	IOV_GRAT_ARP,
++#endif /* DHD_L2_FILTER */
++	IOV_DHD_IE,
++#ifdef DHD_PSTA
++	IOV_PSTA,
++#endif /* DHD_PSTA */
++#ifdef DHD_WET
++	IOV_WET,
++	IOV_WET_HOST_IPV4,
++	IOV_WET_HOST_MAC,
++#endif /* DHD_WET */
++	IOV_CFG80211_OPMODE,
++	IOV_ASSERT_TYPE,
++	IOV_LMTEST,
++#ifdef DHD_MCAST_REGEN
++	IOV_MCAST_REGEN_BSS_ENABLE,
++#endif
++	IOV_LAST
++};
++
++const bcm_iovar_t dhd_iovars[] = {
++	{"version",	IOV_VERSION,	0,	IOVT_BUFFER,	sizeof(dhd_version) },
++#ifdef DHD_DEBUG
++	{"msglevel",	IOV_MSGLEVEL,	0,	IOVT_UINT32,	0 },
++#endif /* DHD_DEBUG */
++	{"bcmerrorstr", IOV_BCMERRORSTR, 0, IOVT_BUFFER,	BCME_STRLEN },
++	{"bcmerror",	IOV_BCMERROR,	0,	IOVT_INT8,	0 },
++	{"wdtick",	IOV_WDTICK, 0,	IOVT_UINT32,	0 },
++	{"dump",	IOV_DUMP,	0,	IOVT_BUFFER,	DHD_IOCTL_MAXLEN },
++#ifdef DHD_DEBUG
++	{"cons",	IOV_CONS,	0,	IOVT_BUFFER,	0 },
++	{"dconpoll",	IOV_DCONSOLE_POLL, 0,	IOVT_UINT32,	0 },
++#endif
++	{"clearcounts", IOV_CLEARCOUNTS, 0, IOVT_VOID,	0 },
++	{"gpioob",	IOV_GPIOOB,	0,	IOVT_UINT32,	0 },
++	{"ioctl_timeout",	IOV_IOCTLTIMEOUT,	0,	IOVT_UINT32,	0 },
++#ifdef PROP_TXSTATUS
++	{"proptx",	IOV_PROPTXSTATUS_ENABLE,	0,	IOVT_BOOL,	0 },
++	/*
++	set the proptxtstatus operation mode:
++	0 - Do not do any proptxtstatus flow control
++	1 - Use implied credit from a packet status
++	2 - Use explicit credit
++	*/
++	{"ptxmode",	IOV_PROPTXSTATUS_MODE,	0,	IOVT_UINT32,	0 },
++	{"proptx_opt", IOV_PROPTXSTATUS_OPT,	0,	IOVT_UINT32,	0 },
++	{"pmodule_ignore", IOV_PROPTXSTATUS_MODULE_IGNORE, 0, IOVT_BOOL, 0 },
++	{"pcredit_ignore", IOV_PROPTXSTATUS_CREDIT_IGNORE, 0, IOVT_BOOL, 0 },
++	{"ptxstatus_ignore", IOV_PROPTXSTATUS_TXSTATUS_IGNORE, 0, IOVT_BOOL, 0 },
++	{"rxpkt_chk", IOV_PROPTXSTATUS_RXPKT_CHK, 0, IOVT_BOOL, 0 },
++#endif /* PROP_TXSTATUS */
++	{"bustype", IOV_BUS_TYPE, 0, IOVT_UINT32, 0},
++#ifdef WLMEDIA_HTSF
++	{"pktdlystatsz", IOV_WLPKTDLYSTAT_SZ, 0, IOVT_UINT8, 0 },
++#endif
++	{"changemtu", IOV_CHANGEMTU, 0, IOVT_UINT32, 0 },
++	{"host_reorder_flows", IOV_HOSTREORDER_FLOWS, 0, IOVT_BUFFER,
++	(WLHOST_REORDERDATA_MAXFLOWS + 1) },
++#ifdef DHDTCPACK_SUPPRESS
++	{"tcpack_suppress",	IOV_TCPACK_SUPPRESS,	0,	IOVT_UINT8,	0 },
++#endif /* DHDTCPACK_SUPPRESS */
++#ifdef DHD_WMF
++	{"wmf_bss_enable", IOV_WMF_BSS_ENAB,	0,	IOVT_BOOL,	0 },
++	{"wmf_ucast_igmp", IOV_WMF_UCAST_IGMP,	0,	IOVT_BOOL,	0 },
++	{"wmf_mcast_data_sendup", IOV_WMF_MCAST_DATA_SENDUP,	0,	IOVT_BOOL,	0 },
++#ifdef WL_IGMP_UCQUERY
++	{"wmf_ucast_igmp_query", IOV_WMF_UCAST_IGMP_QUERY, (0), IOVT_BOOL, 0 },
++#endif /* WL_IGMP_UCQUERY */
++#ifdef DHD_UCAST_UPNP
++	{"wmf_ucast_upnp", IOV_WMF_UCAST_UPNP, (0), IOVT_BOOL, 0 },
++#endif /* DHD_UCAST_UPNP */
++	{"wmf_psta_disable", IOV_WMF_PSTA_DISABLE, (0), IOVT_BOOL, 0 },
++#endif /* DHD_WMF */
++#if defined(TRAFFIC_MGMT_DWM)
++	{"trf_mgmt_filters_add", IOV_TRAFFIC_MGMT_DWM, (0), IOVT_BUFFER, 0},
++#endif 
++#ifdef DHD_L2_FILTER
++	{"dhcp_unicast", IOV_DHCP_UNICAST, (0), IOVT_BOOL, 0 },
++#endif /* DHD_L2_FILTER */
++	{"ap_isolate", IOV_AP_ISOLATE, (0), IOVT_BOOL, 0},
++#ifdef DHD_L2_FILTER
++	{"block_ping", IOV_BLOCK_PING, (0), IOVT_BOOL, 0},
++	{"proxy_arp", IOV_PROXY_ARP, (0), IOVT_BOOL, 0},
++	{"grat_arp", IOV_GRAT_ARP, (0), IOVT_BOOL, 0},
++#endif /* DHD_L2_FILTER */
++	{"dhd_ie", IOV_DHD_IE, (0), IOVT_BUFFER, 0},
++#ifdef DHD_PSTA
++	/* PSTA/PSR Mode configuration. 0: DIABLED 1: PSTA 2: PSR */
++	{"psta", IOV_PSTA, 0, IOVT_UINT32, 0},
++#endif /* DHD PSTA */
++#ifdef DHD_WET
++	/* WET Mode configuration. 0: DIABLED 1: WET */
++	{"wet", IOV_WET, 0, IOVT_UINT32, 0},
++	{"wet_host_ipv4", IOV_WET_HOST_IPV4, 0, IOVT_UINT32, 0},
++	{"wet_host_mac", IOV_WET_HOST_MAC, 0, IOVT_BUFFER, 0},
++#endif /* DHD WET */
++	{"op_mode",	IOV_CFG80211_OPMODE,	0,	IOVT_UINT32,	0 },
++	{"assert_type", IOV_ASSERT_TYPE, (0), IOVT_UINT32, 0},
++	{"lmtest", IOV_LMTEST,	0,	IOVT_UINT32,	0 },
++#ifdef DHD_MCAST_REGEN
++	{"mcast_regen_bss_enable", IOV_MCAST_REGEN_BSS_ENABLE, 0, IOVT_BOOL, 0},
++#endif
++	{NULL, 0, 0, 0, 0 }
++};
++
++#define DHD_IOVAR_BUF_SIZE	128
++
++#ifdef DHD_FW_COREDUMP
++void* dhd_get_fwdump_buf(dhd_pub_t *dhd_pub, uint32 length)
++{
++	if (!dhd_pub->soc_ram) {
++#if defined(CONFIG_DHD_USE_STATIC_BUF) && defined(DHD_USE_STATIC_MEMDUMP)
++		dhd_pub->soc_ram = (uint8*)DHD_OS_PREALLOC(dhd_pub,
++			DHD_PREALLOC_MEMDUMP_RAM, length);
++#else
++		dhd_pub->soc_ram = (uint8*) MALLOC(dhd_pub->osh, length);
++#endif /* CONFIG_DHD_USE_STATIC_BUF && DHD_USE_STATIC_MEMDUMP */
++	}
++
++	if (dhd_pub->soc_ram == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory for fw crash snap shot.\n",
++			__FUNCTION__));
++		dhd_pub->soc_ram_length = 0;
++	} else {
++		memset(dhd_pub->soc_ram, 0, length);
++		dhd_pub->soc_ram_length = length;
++	}
++
++	/* soc_ram free handled in dhd_{free,clear} */
++	return dhd_pub->soc_ram;
++}
++#endif /* DHD_FW_COREDUMP */
++
++/* to NDIS developer, the structure dhd_common is redundant,
++ * please do NOT merge it back from other branches !!!
++ */
++int dhd_common_socram_dump(dhd_pub_t *dhdp)
++{
++	return dhd_socram_dump(dhdp->bus);
++}
++
++static int
++dhd_dump(dhd_pub_t *dhdp, char *buf, int buflen)
++{
++	char eabuf[ETHER_ADDR_STR_LEN];
++
++	struct bcmstrbuf b;
++	struct bcmstrbuf *strbuf = &b;
++
++	if (!dhdp || !dhdp->prot || !buf) {
++		return BCME_ERROR;
++	}
++
++	bcm_binit(strbuf, buf, buflen);
++
++	/* Base DHD info */
++	bcm_bprintf(strbuf, "%s\n", dhd_version);
++	bcm_bprintf(strbuf, "\n");
++	bcm_bprintf(strbuf, "pub.up %d pub.txoff %d pub.busstate %d\n",
++	            dhdp->up, dhdp->txoff, dhdp->busstate);
++	bcm_bprintf(strbuf, "pub.hdrlen %u pub.maxctl %u pub.rxsz %u\n",
++	            dhdp->hdrlen, dhdp->maxctl, dhdp->rxsz);
++	bcm_bprintf(strbuf, "pub.iswl %d pub.drv_version %ld pub.mac %s\n",
++	            dhdp->iswl, dhdp->drv_version, bcm_ether_ntoa(&dhdp->mac, eabuf));
++	bcm_bprintf(strbuf, "pub.bcmerror %d tickcnt %u\n", dhdp->bcmerror, dhdp->tickcnt);
++
++	bcm_bprintf(strbuf, "dongle stats:\n");
++	bcm_bprintf(strbuf, "tx_packets %lu tx_bytes %lu tx_errors %lu tx_dropped %lu\n",
++	            dhdp->dstats.tx_packets, dhdp->dstats.tx_bytes,
++	            dhdp->dstats.tx_errors, dhdp->dstats.tx_dropped);
++	bcm_bprintf(strbuf, "rx_packets %lu rx_bytes %lu rx_errors %lu rx_dropped %lu\n",
++	            dhdp->dstats.rx_packets, dhdp->dstats.rx_bytes,
++	            dhdp->dstats.rx_errors, dhdp->dstats.rx_dropped);
++	bcm_bprintf(strbuf, "multicast %lu\n", dhdp->dstats.multicast);
++
++	bcm_bprintf(strbuf, "bus stats:\n");
++	bcm_bprintf(strbuf, "tx_packets %lu  tx_dropped %lu tx_multicast %lu tx_errors %lu\n",
++	            dhdp->tx_packets, dhdp->tx_dropped, dhdp->tx_multicast, dhdp->tx_errors);
++	bcm_bprintf(strbuf, "tx_ctlpkts %lu tx_ctlerrs %lu\n",
++	            dhdp->tx_ctlpkts, dhdp->tx_ctlerrs);
++	bcm_bprintf(strbuf, "rx_packets %lu rx_multicast %lu rx_errors %lu \n",
++	            dhdp->rx_packets, dhdp->rx_multicast, dhdp->rx_errors);
++	bcm_bprintf(strbuf, "rx_ctlpkts %lu rx_ctlerrs %lu rx_dropped %lu\n",
++	            dhdp->rx_ctlpkts, dhdp->rx_ctlerrs, dhdp->rx_dropped);
++	bcm_bprintf(strbuf, "rx_readahead_cnt %lu tx_realloc %lu\n",
++	            dhdp->rx_readahead_cnt, dhdp->tx_realloc);
++	bcm_bprintf(strbuf, "tx_pktgetfail %lu rx_pktgetfail %lu\n",
++	            dhdp->tx_pktgetfail, dhdp->rx_pktgetfail);
++	bcm_bprintf(strbuf, "\n");
++
++	/* Add any prot info */
++	dhd_prot_dump(dhdp, strbuf);
++	bcm_bprintf(strbuf, "\n");
++
++	/* Add any bus info */
++	dhd_bus_dump(dhdp, strbuf);
++
++
++#if defined(DHD_LB_STATS)
++	dhd_lb_stats_dump(dhdp, strbuf);
++#endif /* DHD_LB_STATS */
++#ifdef DHD_WET
++	dhd_wet_dump(dhdp, strbuf);
++#endif /* DHD_WET */
++	return (!strbuf->size ? BCME_BUFTOOSHORT : 0);
++}
++
++void
++dhd_dump_to_kernelog(dhd_pub_t *dhdp)
++{
++	char buf[512];
++
++	bcm_bprintf_bypass = TRUE;
++	dhd_dump(dhdp, buf, sizeof(buf));
++	bcm_bprintf_bypass = FALSE;
++}
++
++int
++dhd_wl_ioctl_cmd(dhd_pub_t *dhd_pub, int cmd, void *arg, int len, uint8 set, int ifidx)
++{
++	wl_ioctl_t ioc;
++
++	ioc.cmd = cmd;
++	ioc.buf = arg;
++	ioc.len = len;
++	ioc.set = set;
++
++	return dhd_wl_ioctl(dhd_pub, ifidx, &ioc, arg, len);
++}
++
++int
++dhd_wl_ioctl_get_intiovar(dhd_pub_t *dhd_pub, char *name, uint *pval,
++	int cmd, uint8 set, int ifidx)
++{
++	char iovbuf[WLC_IOCTL_SMLEN];
++	int ret = -1;
++
++	memset(iovbuf, 0, sizeof(iovbuf));
++	if (bcm_mkiovar(name, NULL, 0, iovbuf, sizeof(iovbuf))) {
++		ret = dhd_wl_ioctl_cmd(dhd_pub, cmd, iovbuf, sizeof(iovbuf), set, ifidx);
++		if (!ret) {
++			*pval = ltoh32(*((uint*)iovbuf));
++		} else {
++			DHD_ERROR(("%s: get int iovar %s failed, ERR %d\n",
++				__FUNCTION__, name, ret));
++		}
++	} else {
++		DHD_ERROR(("%s: mkiovar %s failed\n",
++			__FUNCTION__, name));
++	}
++
++	return ret;
++}
++
++int
++dhd_wl_ioctl_set_intiovar(dhd_pub_t *dhd_pub, char *name, uint val,
++	int cmd, uint8 set, int ifidx)
++{
++	char iovbuf[WLC_IOCTL_SMLEN];
++	int ret = -1;
++	int lval = htol32(val);
++	uint len;
++
++	len = bcm_mkiovar(name, (char*)&lval, sizeof(lval), iovbuf, sizeof(iovbuf));
++
++	if (len) {
++		ret = dhd_wl_ioctl_cmd(dhd_pub, cmd, iovbuf, len, set, ifidx);
++		if (ret) {
++			DHD_ERROR(("%s: set int iovar %s failed, ERR %d\n",
++				__FUNCTION__, name, ret));
++		}
++	} else {
++		DHD_ERROR(("%s: mkiovar %s failed\n",
++			__FUNCTION__, name));
++	}
++
++	return ret;
++}
++
++int
++dhd_wl_ioctl(dhd_pub_t *dhd_pub, int ifidx, wl_ioctl_t *ioc, void *buf, int len)
++{
++	int ret = BCME_ERROR;
++	unsigned long flags;
++
++#ifdef HOST_FLAG
++	int hostsleep_set = 0;
++	int hostsleep_val = 0;
++	char *psleep = NULL;
++#endif
++#ifdef KEEPIF_ON_DEVICE_RESET
++		if (ioc->cmd == WLC_GET_VAR) {
++			dbus_config_t config;
++			config.general_param = 0;
++			if (!strcmp(buf, "wowl_activate")) {
++				config.general_param = 2; /* 1 (TRUE) after decreased by 1 */
++			} else if (!strcmp(buf, "wowl_clear")) {
++				config.general_param = 1; /* 0 (FALSE) after decreased by 1 */
++			}
++			if (config.general_param) {
++				config.config_id = DBUS_CONFIG_ID_KEEPIF_ON_DEVRESET;
++				config.general_param -= 1; /* convert to 0 (FALSE) or 1 (TRUE) */
++				dbus_set_config(dhd_pub->dbus, &config);
++			}
++		}
++#endif /* KEEPIF_ON_DEVICE_RESET */
++
++	if (dhd_os_proto_block(dhd_pub))
++	{
++		DHD_GENERAL_LOCK(dhd_pub, flags);
++		if (dhd_pub->busstate == DHD_BUS_DOWN ||
++				dhd_pub->busstate == DHD_BUS_DOWN_IN_PROGRESS) {
++			DHD_ERROR(("%s: returning as busstate=%d\n",
++				__FUNCTION__, dhd_pub->busstate));
++			DHD_GENERAL_UNLOCK(dhd_pub, flags);
++			dhd_os_proto_unblock(dhd_pub);
++			return -ENODEV;
++		}
++		dhd_pub->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_IOVAR;
++		DHD_GENERAL_UNLOCK(dhd_pub, flags);
++
++#if defined(WL_WLC_SHIM)
++		{
++			struct wl_shim_node *shim = dhd_pub_shim(dhd_pub);
++
++			wl_io_pport_t io_pport;
++			io_pport.dhd_pub = dhd_pub;
++			io_pport.ifidx = ifidx;
++
++			ret = wl_shim_ioctl(shim, ioc, len, &io_pport);
++			if (ret != BCME_OK) {
++				DHD_TRACE(("%s: wl_shim_ioctl(%d) ERR %d\n",
++					__FUNCTION__, ioc->cmd, ret));
++			}
++		}
++#else
++#ifdef HOST_FLAG
++		/*save hostsleep val first, if ioctl success, set hostsleep to val*/
++		if (ioc->cmd == WLC_SET_VAR) {
++			psleep = strstr(ioc->buf, "hostsleep");
++			if (psleep) {
++				hostsleep_set = 1;
++				memcpy(&hostsleep_val, psleep + strlen("hostsleep") + 1, sizeof(hostsleep_val));
++				printf("###hostsleep: cmd = %d, hostsleep_val = %d, buf = %s\n",
++					ioc->cmd, hostsleep_val, (char *)ioc->buf);
++			}
++		}
++		/* block all cmd, expect hostsleep remove */
++		if (hostsleep && (!hostsleep_set || hostsleep_val)) {
++			printf("%s: block all none hostsleep clr cmd\n", __FUNCTION__);
++			dhd_os_proto_unblock(dhd_pub);
++			return BCME_EPERM;
++		} else if (hostsleep_set && hostsleep_val) {
++			printf("%s: set dhd hostsleep 1\n", __FUNCTION__);
++			hostsleep = 1;
++		}
++#endif
++		ret = dhd_prot_ioctl(dhd_pub, ifidx, ioc, buf, len);
++#endif /* defined(WL_WLC_SHIM) */
++
++#ifdef HOST_FLAG
++		if (hostsleep_set) {
++			if (hostsleep_val && ret) { // reset hostsleep if host_sleep 1 set failed
++				printf("%s: reset hostsleep\n", __FUNCTION__);
++				hostsleep = 0;
++			} else if (!hostsleep_val && !ret) { // clear hostsleep if host_sleep 0 set successfully
++				printf("%s: clear hostsleep\n", __FUNCTION__);
++				hostsleep = 0;
++			}
++		}
++#endif
++
++		if (ret && dhd_pub->up) {
++			/* Send hang event only if dhd_open() was success */
++			dhd_os_check_hang(dhd_pub, ifidx, ret);
++		}
++
++		if (ret == -ETIMEDOUT && !dhd_pub->up) {
++			DHD_ERROR(("%s: 'resumed on timeout' error is "
++				"occurred before the interface does not"
++				" bring up\n", __FUNCTION__));
++			dhd_pub->busstate = DHD_BUS_DOWN;
++		}
++
++		DHD_GENERAL_LOCK(dhd_pub, flags);
++		dhd_pub->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_IOVAR;
++		dhd_os_busbusy_wake(dhd_pub);
++		DHD_GENERAL_UNLOCK(dhd_pub, flags);
++
++		dhd_os_proto_unblock(dhd_pub);
++
++	}
++
++	return ret;
++}
++
++uint wl_get_port_num(wl_io_pport_t *io_pport)
++{
++	return 0;
++}
++
++/* Get bssidx from iovar params
++ * Input:   dhd_pub - pointer to dhd_pub_t
++ *	    params  - IOVAR params
++ * Output:  idx	    - BSS index
++ *	    val	    - ponter to the IOVAR arguments
++ */
++static int
++dhd_iovar_parse_bssidx(dhd_pub_t *dhd_pub, char *params, int *idx, char **val)
++{
++	char *prefix = "bsscfg:";
++	uint32	bssidx;
++
++	if (!(strncmp(params, prefix, strlen(prefix)))) {
++		/* per bss setting should be prefixed with 'bsscfg:' */
++		char *p = (char *)params + strlen(prefix);
++
++		/* Skip Name */
++		while (*p != '\0')
++			p++;
++		/* consider null */
++		p = p + 1;
++		bcopy(p, &bssidx, sizeof(uint32));
++		/* Get corresponding dhd index */
++		bssidx = dhd_bssidx2idx(dhd_pub, htod32(bssidx));
++
++		if (bssidx >= DHD_MAX_IFS) {
++			DHD_ERROR(("%s Wrong bssidx provided\n", __FUNCTION__));
++			return BCME_ERROR;
++		}
++
++		/* skip bss idx */
++		p += sizeof(uint32);
++		*val = p;
++		*idx = bssidx;
++	} else {
++		DHD_ERROR(("%s: bad parameter for per bss iovar\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	return BCME_OK;
++}
++
++#if defined(DHD_DEBUG) && defined(BCMDHDUSB)
++/* USB Device console input function */
++int dhd_bus_console_in(dhd_pub_t *dhd, uchar *msg, uint msglen)
++{
++	DHD_TRACE(("%s \n", __FUNCTION__));
++
++	return dhd_iovar(dhd, 0, "cons", msg, msglen, NULL, 0, TRUE);
++
++}
++#endif /* DHD_DEBUG && BCMDHDUSB  */
++
++static int
++dhd_doiovar(dhd_pub_t *dhd_pub, const bcm_iovar_t *vi, uint32 actionid, const char *name,
++            void *params, int plen, void *arg, int len, int val_size)
++{
++	int bcmerror = 0;
++	int32 int_val = 0;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++	DHD_TRACE(("%s: actionid = %d; name %s\n", __FUNCTION__, actionid, name));
++
++	if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid))) != 0)
++		goto exit;
++
++	if (plen >= (int)sizeof(int_val))
++		bcopy(params, &int_val, sizeof(int_val));
++
++	switch (actionid) {
++	case IOV_GVAL(IOV_VERSION):
++		/* Need to have checked buffer length */
++		bcm_strncpy_s((char*)arg, len, dhd_version, len);
++		break;
++
++	case IOV_GVAL(IOV_MSGLEVEL):
++		int_val = (int32)dhd_msg_level;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_MSGLEVEL):
++#ifdef WL_CFG80211
++		/* Enable DHD and WL logs in oneshot */
++		if (int_val & DHD_WL_VAL2)
++			wl_cfg80211_enable_trace(TRUE, int_val & (~DHD_WL_VAL2));
++		else if (int_val & DHD_WL_VAL)
++			wl_cfg80211_enable_trace(FALSE, WL_DBG_DBG);
++		if (!(int_val & DHD_WL_VAL2))
++#endif /* WL_CFG80211 */
++		dhd_msg_level = int_val;
++		break;
++	case IOV_GVAL(IOV_BCMERRORSTR):
++		bcm_strncpy_s((char *)arg, len, bcmerrorstr(dhd_pub->bcmerror), BCME_STRLEN);
++		((char *)arg)[BCME_STRLEN - 1] = 0x00;
++		break;
++
++	case IOV_GVAL(IOV_BCMERROR):
++		int_val = (int32)dhd_pub->bcmerror;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++#ifndef BCMDBUS
++	case IOV_GVAL(IOV_WDTICK):
++		int_val = (int32)dhd_watchdog_ms;
++		bcopy(&int_val, arg, val_size);
++		break;
++#endif
++
++	case IOV_SVAL(IOV_WDTICK):
++		if (!dhd_pub->up) {
++			bcmerror = BCME_NOTUP;
++			break;
++		}
++
++		if (CUSTOM_DHD_WATCHDOG_MS == 0 && int_val == 0) {
++			dhd_watchdog_ms = (uint)int_val;
++		}
++
++		dhd_os_wd_timer(dhd_pub, (uint)int_val);
++		break;
++
++	case IOV_GVAL(IOV_DUMP):
++		bcmerror = dhd_dump(dhd_pub, arg, len);
++		break;
++
++#ifndef BCMDBUS
++#ifdef DHD_DEBUG
++	case IOV_GVAL(IOV_DCONSOLE_POLL):
++		int_val = (int32)dhd_console_ms;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DCONSOLE_POLL):
++		dhd_console_ms = (uint)int_val;
++		break;
++
++	case IOV_SVAL(IOV_CONS):
++		if (len > 0)
++			bcmerror = dhd_bus_console_in(dhd_pub, arg, len - 1);
++		break;
++#endif /* DHD_DEBUG */
++#endif /* BCMDBUS */
++
++	case IOV_SVAL(IOV_CLEARCOUNTS):
++		dhd_pub->tx_packets = dhd_pub->rx_packets = 0;
++		dhd_pub->tx_errors = dhd_pub->rx_errors = 0;
++		dhd_pub->tx_ctlpkts = dhd_pub->rx_ctlpkts = 0;
++		dhd_pub->tx_ctlerrs = dhd_pub->rx_ctlerrs = 0;
++		dhd_pub->tx_dropped = 0;
++		dhd_pub->rx_dropped = 0;
++		dhd_pub->tx_pktgetfail = 0;
++		dhd_pub->rx_pktgetfail = 0;
++		dhd_pub->rx_readahead_cnt = 0;
++		dhd_pub->tx_realloc = 0;
++		dhd_pub->wd_dpc_sched = 0;
++		memset(&dhd_pub->dstats, 0, sizeof(dhd_pub->dstats));
++		dhd_bus_clearcounts(dhd_pub);
++#ifdef PROP_TXSTATUS
++		/* clear proptxstatus related counters */
++		dhd_wlfc_clear_counts(dhd_pub);
++#endif /* PROP_TXSTATUS */
++		DHD_LB_STATS_RESET(dhd_pub);
++		break;
++
++
++	case IOV_GVAL(IOV_IOCTLTIMEOUT): {
++		int_val = (int32)dhd_os_get_ioctl_resp_timeout();
++		bcopy(&int_val, arg, sizeof(int_val));
++		break;
++	}
++
++	case IOV_SVAL(IOV_IOCTLTIMEOUT): {
++		if (int_val <= 0)
++			bcmerror = BCME_BADARG;
++		else
++			dhd_os_set_ioctl_resp_timeout((unsigned int)int_val);
++		break;
++	}
++
++
++#ifdef PROP_TXSTATUS
++	case IOV_GVAL(IOV_PROPTXSTATUS_ENABLE): {
++		bool wlfc_enab = FALSE;
++		bcmerror = dhd_wlfc_get_enable(dhd_pub, &wlfc_enab);
++		if (bcmerror != BCME_OK)
++			goto exit;
++		int_val = wlfc_enab ? 1 : 0;
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_PROPTXSTATUS_ENABLE): {
++		bool wlfc_enab = FALSE;
++		bcmerror = dhd_wlfc_get_enable(dhd_pub, &wlfc_enab);
++		if (bcmerror != BCME_OK)
++			goto exit;
++
++		/* wlfc is already set as desired */
++		if (wlfc_enab == (int_val == 0 ? FALSE : TRUE))
++			goto exit;
++
++		if (int_val == TRUE)
++			bcmerror = dhd_wlfc_init(dhd_pub);
++		else
++			bcmerror = dhd_wlfc_deinit(dhd_pub);
++
++		break;
++	}
++	case IOV_GVAL(IOV_PROPTXSTATUS_MODE):
++		bcmerror = dhd_wlfc_get_mode(dhd_pub, &int_val);
++		if (bcmerror != BCME_OK)
++			goto exit;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_PROPTXSTATUS_MODE):
++		dhd_wlfc_set_mode(dhd_pub, int_val);
++		break;
++
++	case IOV_GVAL(IOV_PROPTXSTATUS_MODULE_IGNORE):
++		bcmerror = dhd_wlfc_get_module_ignore(dhd_pub, &int_val);
++		if (bcmerror != BCME_OK)
++			goto exit;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_PROPTXSTATUS_MODULE_IGNORE):
++		dhd_wlfc_set_module_ignore(dhd_pub, int_val);
++		break;
++
++	case IOV_GVAL(IOV_PROPTXSTATUS_CREDIT_IGNORE):
++		bcmerror = dhd_wlfc_get_credit_ignore(dhd_pub, &int_val);
++		if (bcmerror != BCME_OK)
++			goto exit;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_PROPTXSTATUS_CREDIT_IGNORE):
++		dhd_wlfc_set_credit_ignore(dhd_pub, int_val);
++		break;
++
++	case IOV_GVAL(IOV_PROPTXSTATUS_TXSTATUS_IGNORE):
++		bcmerror = dhd_wlfc_get_txstatus_ignore(dhd_pub, &int_val);
++		if (bcmerror != BCME_OK)
++			goto exit;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_PROPTXSTATUS_TXSTATUS_IGNORE):
++		dhd_wlfc_set_txstatus_ignore(dhd_pub, int_val);
++		break;
++
++	case IOV_GVAL(IOV_PROPTXSTATUS_RXPKT_CHK):
++		bcmerror = dhd_wlfc_get_rxpkt_chk(dhd_pub, &int_val);
++		if (bcmerror != BCME_OK)
++			goto exit;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_PROPTXSTATUS_RXPKT_CHK):
++		dhd_wlfc_set_rxpkt_chk(dhd_pub, int_val);
++		break;
++
++#endif /* PROP_TXSTATUS */
++
++	case IOV_GVAL(IOV_BUS_TYPE):
++		/* The dhd application queries the driver to check if its usb or sdio.  */
++#ifdef BCMDHDUSB
++		int_val = BUS_TYPE_USB;
++#endif
++#ifdef BCMSDIO
++		int_val = BUS_TYPE_SDIO;
++#endif
++#ifdef PCIE_FULL_DONGLE
++		int_val = BUS_TYPE_PCIE;
++#endif
++		bcopy(&int_val, arg, val_size);
++		break;
++
++
++#ifdef WLMEDIA_HTSF
++	case IOV_GVAL(IOV_WLPKTDLYSTAT_SZ):
++		int_val = dhd_pub->htsfdlystat_sz;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_WLPKTDLYSTAT_SZ):
++		dhd_pub->htsfdlystat_sz = int_val & 0xff;
++		printf("Setting tsfdlystat_sz:%d\n", dhd_pub->htsfdlystat_sz);
++		break;
++#endif
++	case IOV_SVAL(IOV_CHANGEMTU):
++		int_val &= 0xffff;
++		bcmerror = dhd_change_mtu(dhd_pub, int_val, 0);
++		break;
++
++	case IOV_GVAL(IOV_HOSTREORDER_FLOWS):
++	{
++		uint i = 0;
++		uint8 *ptr = (uint8 *)arg;
++		uint8 count = 0;
++
++		ptr++;
++		for (i = 0; i < WLHOST_REORDERDATA_MAXFLOWS; i++) {
++			if (dhd_pub->reorder_bufs[i] != NULL) {
++				*ptr = dhd_pub->reorder_bufs[i]->flow_id;
++				ptr++;
++				count++;
++			}
++		}
++		ptr = (uint8 *)arg;
++		*ptr = count;
++		break;
++	}
++#ifdef DHDTCPACK_SUPPRESS
++	case IOV_GVAL(IOV_TCPACK_SUPPRESS): {
++		int_val = (uint32)dhd_pub->tcpack_sup_mode;
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_TCPACK_SUPPRESS): {
++		bcmerror = dhd_tcpack_suppress_set(dhd_pub, (uint8)int_val);
++		break;
++	}
++#endif /* DHDTCPACK_SUPPRESS */
++#ifdef DHD_WMF
++	case IOV_GVAL(IOV_WMF_BSS_ENAB): {
++		uint32	bssidx;
++		dhd_wmf_t *wmf;
++		char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: wmf_bss_enable: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		wmf = dhd_wmf_conf(dhd_pub, bssidx);
++		int_val = wmf->wmf_enable ? 1 :0;
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_WMF_BSS_ENAB): {
++		/* Enable/Disable WMF */
++		uint32	bssidx;
++		dhd_wmf_t *wmf;
++		char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: wmf_bss_enable: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		ASSERT(val);
++		bcopy(val, &int_val, sizeof(uint32));
++		wmf = dhd_wmf_conf(dhd_pub, bssidx);
++		if (wmf->wmf_enable == int_val)
++			break;
++		if (int_val) {
++			/* Enable WMF */
++			if (dhd_wmf_instance_add(dhd_pub, bssidx) != BCME_OK) {
++				DHD_ERROR(("%s: Error in creating WMF instance\n",
++				__FUNCTION__));
++				break;
++			}
++			if (dhd_wmf_start(dhd_pub, bssidx) != BCME_OK) {
++				DHD_ERROR(("%s: Failed to start WMF\n", __FUNCTION__));
++				break;
++			}
++			wmf->wmf_enable = TRUE;
++		} else {
++			/* Disable WMF */
++			wmf->wmf_enable = FALSE;
++			dhd_wmf_stop(dhd_pub, bssidx);
++			dhd_wmf_instance_del(dhd_pub, bssidx);
++		}
++		break;
++	}
++	case IOV_GVAL(IOV_WMF_UCAST_IGMP):
++		int_val = dhd_pub->wmf_ucast_igmp ? 1 : 0;
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_SVAL(IOV_WMF_UCAST_IGMP):
++		if (dhd_pub->wmf_ucast_igmp == int_val)
++			break;
++
++		if (int_val >= OFF && int_val <= ON)
++			dhd_pub->wmf_ucast_igmp = int_val;
++		else
++			bcmerror = BCME_RANGE;
++		break;
++	case IOV_GVAL(IOV_WMF_MCAST_DATA_SENDUP):
++		int_val = dhd_wmf_mcast_data_sendup(dhd_pub, 0, FALSE, FALSE);
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_SVAL(IOV_WMF_MCAST_DATA_SENDUP):
++		dhd_wmf_mcast_data_sendup(dhd_pub, 0, TRUE, int_val);
++		break;
++
++#ifdef WL_IGMP_UCQUERY
++	case IOV_GVAL(IOV_WMF_UCAST_IGMP_QUERY):
++		int_val = dhd_pub->wmf_ucast_igmp_query ? 1 : 0;
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_SVAL(IOV_WMF_UCAST_IGMP_QUERY):
++		if (dhd_pub->wmf_ucast_igmp_query == int_val)
++			break;
++
++		if (int_val >= OFF && int_val <= ON)
++			dhd_pub->wmf_ucast_igmp_query = int_val;
++		else
++			bcmerror = BCME_RANGE;
++		break;
++#endif /* WL_IGMP_UCQUERY */
++#ifdef DHD_UCAST_UPNP
++	case IOV_GVAL(IOV_WMF_UCAST_UPNP):
++		int_val = dhd_pub->wmf_ucast_upnp ? 1 : 0;
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_SVAL(IOV_WMF_UCAST_UPNP):
++		if (dhd_pub->wmf_ucast_upnp == int_val)
++			break;
++
++		if (int_val >= OFF && int_val <= ON)
++			dhd_pub->wmf_ucast_upnp = int_val;
++		else
++			bcmerror = BCME_RANGE;
++		break;
++#endif /* DHD_UCAST_UPNP */
++
++	case IOV_GVAL(IOV_WMF_PSTA_DISABLE): {
++		uint32	bssidx;
++		char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: ap isoalate: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		int_val = dhd_get_wmf_psta_disable(dhd_pub, bssidx);
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++
++	case IOV_SVAL(IOV_WMF_PSTA_DISABLE): {
++		uint32	bssidx;
++		char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: ap isolate: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		ASSERT(val);
++		bcopy(val, &int_val, sizeof(uint32));
++		dhd_set_wmf_psta_disable(dhd_pub, bssidx, int_val);
++		break;
++	}
++#endif /* DHD_WMF */
++
++#if defined(TRAFFIC_MGMT_DWM)
++	case IOV_SVAL(IOV_TRAFFIC_MGMT_DWM): {
++			trf_mgmt_filter_list_t   *trf_mgmt_filter_list =
++				(trf_mgmt_filter_list_t *)(arg);
++			bcmerror = traffic_mgmt_add_dwm_filter(dhd_pub, trf_mgmt_filter_list, len);
++		}
++		break;
++#endif 
++
++#ifdef DHD_L2_FILTER
++	case IOV_GVAL(IOV_DHCP_UNICAST): {
++		uint32 bssidx;
++		char *val;
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: IOV_DHCP_UNICAST: bad parameterand name = %s\n",
++				__FUNCTION__, name));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		int_val = dhd_get_dhcp_unicast_status(dhd_pub, bssidx);
++		memcpy(arg, &int_val, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_DHCP_UNICAST): {
++		uint32	bssidx;
++		char *val;
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: IOV_DHCP_UNICAST: bad parameterand name = %s\n",
++				__FUNCTION__, name));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		memcpy(&int_val, val, sizeof(int_val));
++		bcmerror = dhd_set_dhcp_unicast_status(dhd_pub, bssidx, int_val ? 1 : 0);
++		break;
++	}
++	case IOV_GVAL(IOV_BLOCK_PING): {
++		uint32 bssidx;
++		char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: IOV_BLOCK_PING: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		int_val = dhd_get_block_ping_status(dhd_pub, bssidx);
++		memcpy(arg, &int_val, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_BLOCK_PING): {
++		uint32	bssidx;
++		char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: IOV_BLOCK_PING: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		memcpy(&int_val, val, sizeof(int_val));
++		bcmerror = dhd_set_block_ping_status(dhd_pub, bssidx, int_val ? 1 : 0);
++		break;
++	}
++	case IOV_GVAL(IOV_PROXY_ARP): {
++		uint32	bssidx;
++		char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: IOV_PROXY_ARP: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		int_val = dhd_get_parp_status(dhd_pub, bssidx);
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_PROXY_ARP): {
++		uint32	bssidx;
++		char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: IOV_PROXY_ARP: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		bcopy(val, &int_val, sizeof(int_val));
++
++		/* Issue a iovar request to WL to update the proxy arp capability bit
++		 * in the Extended Capability IE of beacons/probe responses.
++		 */
++		bcmerror = dhd_iovar(dhd_pub, bssidx, "proxy_arp_advertise", val, sizeof(int_val),
++				NULL, 0, TRUE);
++		if (bcmerror == BCME_OK) {
++			dhd_set_parp_status(dhd_pub, bssidx, int_val ? 1 : 0);
++		}
++		break;
++	}
++	case IOV_GVAL(IOV_GRAT_ARP): {
++		uint32 bssidx;
++		char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: IOV_GRAT_ARP: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		int_val = dhd_get_grat_arp_status(dhd_pub, bssidx);
++		memcpy(arg, &int_val, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_GRAT_ARP): {
++		uint32	bssidx;
++		char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: IOV_GRAT_ARP: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++		memcpy(&int_val, val, sizeof(int_val));
++		bcmerror = dhd_set_grat_arp_status(dhd_pub, bssidx, int_val ? 1 : 0);
++		break;
++	}
++#endif /* DHD_L2_FILTER */
++	case IOV_SVAL(IOV_DHD_IE): {
++		uint32	bssidx;
++		char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: dhd ie: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		break;
++	}
++	case IOV_GVAL(IOV_AP_ISOLATE): {
++		uint32	bssidx;
++		char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: ap isoalate: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		int_val = dhd_get_ap_isolate(dhd_pub, bssidx);
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++	case IOV_SVAL(IOV_AP_ISOLATE): {
++		uint32	bssidx;
++		char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: ap isolate: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		ASSERT(val);
++		bcopy(val, &int_val, sizeof(uint32));
++		dhd_set_ap_isolate(dhd_pub, bssidx, int_val);
++		break;
++	}
++#ifdef DHD_PSTA
++	case IOV_GVAL(IOV_PSTA): {
++		int_val = dhd_get_psta_mode(dhd_pub);
++		bcopy(&int_val, arg, val_size);
++		break;
++		}
++	case IOV_SVAL(IOV_PSTA): {
++		if (int_val >= DHD_MODE_PSTA_DISABLED && int_val <= DHD_MODE_PSR) {
++			dhd_set_psta_mode(dhd_pub, int_val);
++		} else {
++			bcmerror = BCME_RANGE;
++		}
++		break;
++		}
++#endif /* DHD_PSTA */
++
++#ifdef DHD_MCAST_REGEN
++	case IOV_GVAL(IOV_MCAST_REGEN_BSS_ENABLE): {
++		uint32	bssidx;
++		char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: mcast_regen_bss_enable: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		int_val = dhd_get_mcast_regen_bss_enable(dhd_pub, bssidx);
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++
++	case IOV_SVAL(IOV_MCAST_REGEN_BSS_ENABLE): {
++		uint32	bssidx;
++		char *val;
++
++		if (dhd_iovar_parse_bssidx(dhd_pub, (char *)name, &bssidx, &val) != BCME_OK) {
++			DHD_ERROR(("%s: mcast_regen_bss_enable: bad parameter\n", __FUNCTION__));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		ASSERT(val);
++		bcopy(val, &int_val, sizeof(uint32));
++		dhd_set_mcast_regen_bss_enable(dhd_pub, bssidx, int_val);
++		break;
++	}
++#endif /* DHD_MCAST_REGEN */
++
++#ifdef DHD_WET
++	case IOV_GVAL(IOV_WET):
++		int_val = dhd_get_wet_mode(dhd_pub);
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_WET):
++		if (int_val == 0 || int_val == 1) {
++			dhd_set_wet_mode(dhd_pub, int_val);
++			/* Delete the WET DB when disabled */
++			if (!int_val) {
++			    dhd_wet_sta_delete_list(dhd_pub);
++			}
++		} else {
++			bcmerror = BCME_RANGE;
++		}
++		break;
++	case IOV_SVAL(IOV_WET_HOST_IPV4):
++		dhd_set_wet_host_ipv4(dhd_pub, params, plen);
++		break;
++	case IOV_SVAL(IOV_WET_HOST_MAC):
++		dhd_set_wet_host_mac(dhd_pub, params, plen);
++		break;
++#endif /* DHD_WET */
++
++	case IOV_GVAL(IOV_CFG80211_OPMODE): {
++		int_val = (int32)dhd_pub->op_mode;
++		bcopy(&int_val, arg, sizeof(int_val));
++		break;
++		}
++	case IOV_SVAL(IOV_CFG80211_OPMODE): {
++		if (int_val <= 0)
++			bcmerror = BCME_BADARG;
++		else
++			dhd_pub->op_mode = int_val;
++		break;
++	}
++
++	case IOV_GVAL(IOV_ASSERT_TYPE):
++		int_val = g_assert_type;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_ASSERT_TYPE):
++		g_assert_type = (uint32)int_val;
++		break;
++
++
++	case IOV_GVAL(IOV_LMTEST): {
++		*(uint32 *)arg = (uint32)lmtest;
++		break;
++	}
++
++	case IOV_SVAL(IOV_LMTEST): {
++		uint32 val = *(uint32 *)arg;
++		if (val > 50)
++			bcmerror = BCME_BADARG;
++		else {
++			lmtest = (uint)val;
++			DHD_ERROR(("%s: lmtest %s\n",
++				__FUNCTION__, (lmtest == FALSE)? "OFF" : "ON"));
++		}
++		break;
++	}
++	default:
++		bcmerror = BCME_UNSUPPORTED;
++		break;
++	}
++
++exit:
++	DHD_TRACE(("%s: actionid %d, bcmerror %d\n", __FUNCTION__, actionid, bcmerror));
++	return bcmerror;
++}
++
++/* Store the status of a connection attempt for later retrieval by an iovar */
++void
++dhd_store_conn_status(uint32 event, uint32 status, uint32 reason)
++{
++	/* Do not overwrite a WLC_E_PRUNE with a WLC_E_SET_SSID
++	 * because an encryption/rsn mismatch results in both events, and
++	 * the important information is in the WLC_E_PRUNE.
++	 */
++	if (!(event == WLC_E_SET_SSID && status == WLC_E_STATUS_FAIL &&
++	      dhd_conn_event == WLC_E_PRUNE)) {
++		dhd_conn_event = event;
++		dhd_conn_status = status;
++		dhd_conn_reason = reason;
++	}
++}
++
++bool
++dhd_prec_enq(dhd_pub_t *dhdp, struct pktq *q, void *pkt, int prec)
++{
++	void *p;
++	int eprec = -1;		/* precedence to evict from */
++	bool discard_oldest;
++
++	/* Fast case, precedence queue is not full and we are also not
++	 * exceeding total queue length
++	 */
++	if (!pktq_pfull(q, prec) && !pktq_full(q)) {
++		pktq_penq(q, prec, pkt);
++		return TRUE;
++	}
++
++	/* Determine precedence from which to evict packet, if any */
++	if (pktq_pfull(q, prec))
++		eprec = prec;
++	else if (pktq_full(q)) {
++		p = pktq_peek_tail(q, &eprec);
++		ASSERT(p);
++		if (eprec > prec || eprec < 0)
++			return FALSE;
++	}
++
++	/* Evict if needed */
++	if (eprec >= 0) {
++		/* Detect queueing to unconfigured precedence */
++		ASSERT(!pktq_pempty(q, eprec));
++		discard_oldest = AC_BITMAP_TST(dhdp->wme_dp, eprec);
++		if (eprec == prec && !discard_oldest)
++			return FALSE;		/* refuse newer (incoming) packet */
++		/* Evict packet according to discard policy */
++		p = discard_oldest ? pktq_pdeq(q, eprec) : pktq_pdeq_tail(q, eprec);
++		ASSERT(p);
++#ifdef DHDTCPACK_SUPPRESS
++		if (dhd_tcpack_check_xmit(dhdp, p) == BCME_ERROR) {
++			DHD_ERROR(("%s %d: tcpack_suppress ERROR!!! Stop using it\n",
++				__FUNCTION__, __LINE__));
++			dhd_tcpack_suppress_set(dhdp, TCPACK_SUP_OFF);
++		}
++#endif /* DHDTCPACK_SUPPRESS */
++		PKTFREE(dhdp->osh, p, TRUE);
++	}
++
++	/* Enqueue */
++	p = pktq_penq(q, prec, pkt);
++	ASSERT(p);
++
++	return TRUE;
++}
++
++/*
++ * Functions to drop proper pkts from queue:
++ *	If one pkt in queue is non-fragmented, drop first non-fragmented pkt only
++ *	If all pkts in queue are all fragmented, find and drop one whole set fragmented pkts
++ *	If can't find pkts matching upper 2 cases, drop first pkt anyway
++ */
++bool
++dhd_prec_drop_pkts(dhd_pub_t *dhdp, struct pktq *pq, int prec, f_droppkt_t fn)
++{
++	struct pktq_prec *q = NULL;
++	void *p, *prev = NULL, *next = NULL, *first = NULL, *last = NULL, *prev_first = NULL;
++	pkt_frag_t frag_info;
++
++	ASSERT(dhdp && pq);
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	q = &pq->q[prec];
++	p = q->head;
++
++	if (p == NULL)
++		return FALSE;
++
++	while (p) {
++		frag_info = pkt_frag_info(dhdp->osh, p);
++		if (frag_info == DHD_PKT_FRAG_NONE) {
++			break;
++		} else if (frag_info == DHD_PKT_FRAG_FIRST) {
++			if (first) {
++				/* No last frag pkt, use prev as last */
++				last = prev;
++				break;
++			} else {
++				first = p;
++				prev_first = prev;
++			}
++		} else if (frag_info == DHD_PKT_FRAG_LAST) {
++			if (first) {
++				last = p;
++				break;
++			}
++		}
++
++		prev = p;
++		p = PKTLINK(p);
++	}
++
++	if ((p == NULL) || ((frag_info != DHD_PKT_FRAG_NONE) && !(first && last))) {
++		/* Not found matching pkts, use oldest */
++		prev = NULL;
++		p = q->head;
++		frag_info = 0;
++	}
++
++	if (frag_info == DHD_PKT_FRAG_NONE) {
++		first = last = p;
++		prev_first = prev;
++	}
++
++	p = first;
++	while (p) {
++		next = PKTLINK(p);
++		q->len--;
++		pq->len--;
++
++		PKTSETLINK(p, NULL);
++
++		if (fn)
++			fn(dhdp, prec, p, TRUE);
++
++		if (p == last)
++			break;
++
++		p = next;
++	}
++
++	if (prev_first == NULL) {
++		if ((q->head = next) == NULL)
++			q->tail = NULL;
++	} else {
++		PKTSETLINK(prev_first, next);
++		if (!next)
++			q->tail = prev_first;
++	}
++
++	return TRUE;
++}
++
++static int
++dhd_iovar_op(dhd_pub_t *dhd_pub, const char *name,
++	void *params, int plen, void *arg, int len, bool set)
++{
++	int bcmerror = 0;
++	int val_size;
++	const bcm_iovar_t *vi = NULL;
++	uint32 actionid;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	ASSERT(name);
++	ASSERT(len >= 0);
++
++	/* Get MUST have return space */
++	ASSERT(set || (arg && len));
++
++	/* Set does NOT take qualifiers */
++	ASSERT(!set || (!params && !plen));
++
++	if ((vi = bcm_iovar_lookup(dhd_iovars, name)) == NULL) {
++		bcmerror = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++	DHD_CTL(("%s: %s %s, len %d plen %d\n", __FUNCTION__,
++		name, (set ? "set" : "get"), len, plen));
++
++	/* set up 'params' pointer in case this is a set command so that
++	 * the convenience int and bool code can be common to set and get
++	 */
++	if (params == NULL) {
++		params = arg;
++		plen = len;
++	}
++
++	if (vi->type == IOVT_VOID)
++		val_size = 0;
++	else if (vi->type == IOVT_BUFFER)
++		val_size = len;
++	else
++		/* all other types are integer sized */
++		val_size = sizeof(int);
++
++	actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
++
++	bcmerror = dhd_doiovar(dhd_pub, vi, actionid, name, params, plen, arg, len, val_size);
++
++exit:
++	return bcmerror;
++}
++
++int
++dhd_ioctl(dhd_pub_t * dhd_pub, dhd_ioctl_t *ioc, void * buf, uint buflen)
++{
++	int bcmerror = 0;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (!buf) {
++		return BCME_BADARG;
++	}
++
++	switch (ioc->cmd) {
++	case DHD_GET_MAGIC:
++		if (buflen < sizeof(int))
++			bcmerror = BCME_BUFTOOSHORT;
++		else
++			*(int*)buf = DHD_IOCTL_MAGIC;
++		break;
++
++	case DHD_GET_VERSION:
++		if (buflen < sizeof(int))
++			bcmerror = BCME_BUFTOOSHORT;
++		else
++			*(int*)buf = DHD_IOCTL_VERSION;
++		break;
++
++	case DHD_GET_VAR:
++	case DHD_SET_VAR: {
++		char *arg;
++		uint arglen;
++
++		/* scan past the name to any arguments */
++		for (arg = buf, arglen = buflen; *arg && arglen; arg++, arglen--)
++			;
++
++		if (*arg) {
++			bcmerror = BCME_BUFTOOSHORT;
++			break;
++		}
++
++		/* account for the NUL terminator */
++		arg++, arglen--;
++
++		/* call with the appropriate arguments */
++		if (ioc->cmd == DHD_GET_VAR)
++			bcmerror = dhd_iovar_op(dhd_pub, buf, arg, arglen,
++			buf, buflen, IOV_GET);
++		else
++			bcmerror = dhd_iovar_op(dhd_pub, buf, NULL, 0, arg, arglen, IOV_SET);
++		if (bcmerror != BCME_UNSUPPORTED)
++			break;
++
++		/* not in generic table, try protocol module */
++		if (ioc->cmd == DHD_GET_VAR)
++			bcmerror = dhd_prot_iovar_op(dhd_pub, buf, arg,
++				arglen, buf, buflen, IOV_GET);
++		else
++			bcmerror = dhd_prot_iovar_op(dhd_pub, buf,
++				NULL, 0, arg, arglen, IOV_SET);
++		if (bcmerror != BCME_UNSUPPORTED)
++			break;
++
++		/* if still not found, try bus module */
++		if (ioc->cmd == DHD_GET_VAR) {
++#ifdef BCMDBUS
++			bcmerror = dbus_iovar_op(dhd_pub->dbus, buf,
++				arg, arglen, buf, buflen, IOV_GET);
++#else
++			bcmerror = dhd_bus_iovar_op(dhd_pub, buf,
++				arg, arglen, buf, buflen, IOV_GET);
++#endif
++		} else {
++#ifdef BCMDBUS
++			bcmerror = dbus_iovar_op(dhd_pub->dbus, buf,
++				NULL, 0, arg, arglen, IOV_SET);
++#else
++			bcmerror = dhd_bus_iovar_op(dhd_pub, buf,
++				NULL, 0, arg, arglen, IOV_SET);
++#endif
++		}
++
++		break;
++	}
++
++	default:
++		bcmerror = BCME_UNSUPPORTED;
++	}
++
++	return bcmerror;
++}
++
++#ifdef SHOW_EVENTS
++#ifdef SHOW_LOGTRACE
++
++#define MAX_NO_OF_ARG	16
++
++#define FMTSTR_SIZE	132
++#define SIZE_LOC_STR	50
++#define MIN_DLEN	4
++#define TAG_BYTES	12
++#define TAG_WORDS	3
++#define ROMSTR_SIZE	200
++
++
++
++#endif /* SHOW_LOGTRACE */
++
++static void
++wl_show_host_event(dhd_pub_t *dhd_pub, wl_event_msg_t *event, void *event_data,
++	void *raw_event_ptr, char *eventmask)
++{
++	uint i, status, reason;
++	bool group = FALSE, flush_txq = FALSE, link = FALSE;
++	bool host_data = FALSE; /* prints  event data after the case  when set */
++	const char *auth_str;
++	const char *event_name;
++	uchar *buf;
++	char err_msg[256], eabuf[ETHER_ADDR_STR_LEN];
++	uint event_type, flags, auth_type, datalen;
++
++	event_type = ntoh32(event->event_type);
++	flags = ntoh16(event->flags);
++	status = ntoh32(event->status);
++	reason = ntoh32(event->reason);
++	BCM_REFERENCE(reason);
++	auth_type = ntoh32(event->auth_type);
++	datalen = ntoh32(event->datalen);
++
++	/* debug dump of event messages */
++	snprintf(eabuf, sizeof(eabuf), "%02x:%02x:%02x:%02x:%02x:%02x",
++	        (uchar)event->addr.octet[0]&0xff,
++	        (uchar)event->addr.octet[1]&0xff,
++	        (uchar)event->addr.octet[2]&0xff,
++	        (uchar)event->addr.octet[3]&0xff,
++	        (uchar)event->addr.octet[4]&0xff,
++	        (uchar)event->addr.octet[5]&0xff);
++
++	event_name = bcmevent_get_name(event_type);
++	BCM_REFERENCE(event_name);
++
++	if (flags & WLC_EVENT_MSG_LINK)
++		link = TRUE;
++	if (flags & WLC_EVENT_MSG_GROUP)
++		group = TRUE;
++	if (flags & WLC_EVENT_MSG_FLUSHTXQ)
++		flush_txq = TRUE;
++
++	switch (event_type) {
++	case WLC_E_START:
++	case WLC_E_DEAUTH:
++	case WLC_E_DISASSOC:
++		DHD_EVENT(("MACEVENT: %s, MAC %s\n", event_name, eabuf));
++		break;
++
++	case WLC_E_ASSOC_IND:
++	case WLC_E_REASSOC_IND:
++
++		DHD_EVENT(("MACEVENT: %s, MAC %s\n", event_name, eabuf));
++		break;
++
++	case WLC_E_ASSOC:
++	case WLC_E_REASSOC:
++		if (status == WLC_E_STATUS_SUCCESS) {
++			DHD_EVENT(("MACEVENT: %s, MAC %s, SUCCESS\n", event_name, eabuf));
++		} else if (status == WLC_E_STATUS_TIMEOUT) {
++			DHD_EVENT(("MACEVENT: %s, MAC %s, TIMEOUT\n", event_name, eabuf));
++		} else if (status == WLC_E_STATUS_FAIL) {
++			DHD_EVENT(("MACEVENT: %s, MAC %s, FAILURE, reason %d\n",
++			       event_name, eabuf, (int)reason));
++		} else {
++			DHD_EVENT(("MACEVENT: %s, MAC %s, unexpected status %d\n",
++			       event_name, eabuf, (int)status));
++		}
++		break;
++
++	case WLC_E_DEAUTH_IND:
++	case WLC_E_DISASSOC_IND:
++		DHD_EVENT(("MACEVENT: %s, MAC %s, reason %d\n", event_name, eabuf, (int)reason));
++		break;
++
++	case WLC_E_AUTH:
++	case WLC_E_AUTH_IND:
++		if (auth_type == DOT11_OPEN_SYSTEM)
++			auth_str = "Open System";
++		else if (auth_type == DOT11_SHARED_KEY)
++			auth_str = "Shared Key";
++		else {
++			snprintf(err_msg, sizeof(err_msg), "AUTH unknown: %d", (int)auth_type);
++			auth_str = err_msg;
++		}
++		if (event_type == WLC_E_AUTH_IND) {
++			DHD_EVENT(("MACEVENT: %s, MAC %s, %s\n", event_name, eabuf, auth_str));
++		} else if (status == WLC_E_STATUS_SUCCESS) {
++			DHD_EVENT(("MACEVENT: %s, MAC %s, %s, SUCCESS\n",
++				event_name, eabuf, auth_str));
++		} else if (status == WLC_E_STATUS_TIMEOUT) {
++			DHD_EVENT(("MACEVENT: %s, MAC %s, %s, TIMEOUT\n",
++				event_name, eabuf, auth_str));
++		} else if (status == WLC_E_STATUS_FAIL) {
++			DHD_EVENT(("MACEVENT: %s, MAC %s, %s, FAILURE, reason %d\n",
++			       event_name, eabuf, auth_str, (int)reason));
++		}
++		BCM_REFERENCE(auth_str);
++
++		break;
++
++	case WLC_E_JOIN:
++	case WLC_E_ROAM:
++	case WLC_E_SET_SSID:
++		if (status == WLC_E_STATUS_SUCCESS) {
++			DHD_EVENT(("MACEVENT: %s, MAC %s\n", event_name, eabuf));
++		} else if (status == WLC_E_STATUS_FAIL) {
++			DHD_EVENT(("MACEVENT: %s, failed\n", event_name));
++		} else if (status == WLC_E_STATUS_NO_NETWORKS) {
++			DHD_EVENT(("MACEVENT: %s, no networks found\n", event_name));
++		} else {
++			DHD_EVENT(("MACEVENT: %s, unexpected status %d\n",
++				event_name, (int)status));
++		}
++		break;
++
++	case WLC_E_BEACON_RX:
++		if (status == WLC_E_STATUS_SUCCESS) {
++			DHD_EVENT(("MACEVENT: %s, SUCCESS\n", event_name));
++		} else if (status == WLC_E_STATUS_FAIL) {
++			DHD_EVENT(("MACEVENT: %s, FAIL\n", event_name));
++		} else {
++			DHD_EVENT(("MACEVENT: %s, status %d\n", event_name, status));
++		}
++		break;
++
++	case WLC_E_LINK:
++		DHD_EVENT(("MACEVENT: %s %s\n", event_name, link?"UP":"DOWN"));
++		BCM_REFERENCE(link);
++		break;
++
++	case WLC_E_MIC_ERROR:
++		DHD_EVENT(("MACEVENT: %s, MAC %s, Group %d, Flush %d\n",
++		       event_name, eabuf, group, flush_txq));
++		BCM_REFERENCE(group);
++		BCM_REFERENCE(flush_txq);
++		break;
++
++	case WLC_E_ICV_ERROR:
++	case WLC_E_UNICAST_DECODE_ERROR:
++	case WLC_E_MULTICAST_DECODE_ERROR:
++		DHD_EVENT(("MACEVENT: %s, MAC %s\n",
++		       event_name, eabuf));
++		break;
++
++	case WLC_E_TXFAIL:
++		DHD_EVENT(("MACEVENT: %s, RA %s status %d\n", event_name, eabuf, status));
++		break;
++
++	case WLC_E_ASSOC_REQ_IE:
++	case WLC_E_ASSOC_RESP_IE:
++	case WLC_E_PMKID_CACHE:
++	case WLC_E_SCAN_COMPLETE:
++		DHD_EVENT(("MACEVENT: %s\n", event_name));
++		break;
++	case WLC_E_RSSI_LQM:
++	case WLC_E_PFN_NET_FOUND:
++	case WLC_E_PFN_NET_LOST:
++	case WLC_E_PFN_SCAN_NONE:
++	case WLC_E_PFN_SCAN_ALLGONE:
++	case WLC_E_PFN_GSCAN_FULL_RESULT:
++	case WLC_E_PFN_SWC:
++		DHD_EVENT(("PNOEVENT: %s\n", event_name));
++		break;
++
++	case WLC_E_PSK_SUP:
++	case WLC_E_PRUNE:
++		DHD_EVENT(("MACEVENT: %s, status %d, reason %d\n",
++		           event_name, (int)status, (int)reason));
++		break;
++
++#ifdef WIFI_ACT_FRAME
++	case WLC_E_ACTION_FRAME:
++		DHD_TRACE(("MACEVENT: %s Bssid %s\n", event_name, eabuf));
++		break;
++#endif /* WIFI_ACT_FRAME */
++
++#ifdef SHOW_LOGTRACE
++	case WLC_E_TRACE:
++	{
++		dhd_dbg_trace_evnt_handler(dhd_pub, event_data, raw_event_ptr, datalen);
++		break;
++	}
++#endif /* SHOW_LOGTRACE */
++
++	case WLC_E_RSSI:
++		DHD_EVENT(("MACEVENT: %s %d\n", event_name, ntoh32(*((int *)event_data))));
++		break;
++
++	case WLC_E_SERVICE_FOUND:
++	case WLC_E_P2PO_ADD_DEVICE:
++	case WLC_E_P2PO_DEL_DEVICE:
++		DHD_EVENT(("MACEVENT: %s, MAC %s\n", event_name, eabuf));
++		break;
++
++#ifdef BT_WIFI_HANDOBER
++	case WLC_E_BT_WIFI_HANDOVER_REQ:
++		DHD_EVENT(("MACEVENT: %s, MAC %s\n", event_name, eabuf));
++		break;
++#endif
++
++	case WLC_E_CCA_CHAN_QUAL:
++		if (datalen) {
++			buf = (uchar *) event_data;
++			DHD_EVENT(("MACEVENT: %s %d, MAC %s, status %d, reason %d, auth %d, "
++				"channel 0x%02x \n", event_name, event_type, eabuf, (int)status,
++				(int)reason, (int)auth_type, *(buf + 4)));
++		}
++		break;
++	case WLC_E_ESCAN_RESULT:
++	{
++		DHD_EVENT(("MACEVENT: %s %d, MAC %s, status %d \n",
++		       event_name, event_type, eabuf, (int)status));
++	}
++		break;
++	default:
++		DHD_EVENT(("MACEVENT: %s %d, MAC %s, status %d, reason %d, auth %d\n",
++		       event_name, event_type, eabuf, (int)status, (int)reason,
++		       (int)auth_type));
++		break;
++	}
++
++	/* show any appended data if message level is set to bytes or host_data is set */
++	if ((DHD_BYTES_ON() || (host_data == TRUE)) && DHD_EVENT_ON() && datalen) {
++		buf = (uchar *) event_data;
++		BCM_REFERENCE(buf);
++		DHD_EVENT((" data (%d) : ", datalen));
++		for (i = 0; i < datalen; i++)
++			DHD_EVENT((" 0x%02x ", *buf++));
++		DHD_EVENT(("\n"));
++	}
++}
++#endif /* SHOW_EVENTS */
++
++
++/* Stub for now. Will become real function as soon as shim
++ * is being integrated to Android, Linux etc.
++ */
++int
++wl_event_process_default(wl_event_msg_t *event, struct wl_evt_pport *evt_pport)
++{
++	return BCME_OK;
++}
++
++int
++wl_event_process(dhd_pub_t *dhd_pub, int *ifidx, void *pktdata, void **data_ptr, void *raw_event)
++{
++	wl_evt_pport_t evt_pport;
++	wl_event_msg_t event;
++
++	/* make sure it is a BRCM event pkt and record event data */
++	int ret = wl_host_event_get_data(pktdata, &event, data_ptr);
++	if (ret != BCME_OK) {
++		return ret;
++	}
++
++	/* convert event from network order to host order */
++	wl_event_to_host_order(&event);
++
++	/* record event params to evt_pport */
++	evt_pport.dhd_pub = dhd_pub;
++	evt_pport.ifidx = ifidx;
++	evt_pport.pktdata = pktdata;
++	evt_pport.data_ptr = data_ptr;
++	evt_pport.raw_event = raw_event;
++
++#if defined(WL_WLC_SHIM) && defined(WL_WLC_SHIM_EVENTS)
++	{
++		struct wl_shim_node *shim = dhd_pub_shim(dhd_pub);
++		ASSERT(shim);
++		ret = wl_shim_event_process(shim, &event, &evt_pport);
++	}
++#else
++	ret = wl_event_process_default(&event, &evt_pport);
++#endif
++
++	return ret;
++}
++
++/* Check whether packet is a BRCM event pkt. If it is, record event data. */
++int
++wl_host_event_get_data(void *pktdata, wl_event_msg_t *event, void **data_ptr)
++{
++	bcm_event_t *pvt_data = (bcm_event_t *)pktdata;
++
++	if (bcmp(BRCM_OUI, &pvt_data->bcm_hdr.oui[0], DOT11_OUI_LEN)) {
++		DHD_ERROR(("%s: mismatched OUI, bailing\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	/* BRCM event pkt may be unaligned - use xxx_ua to load user_subtype. */
++	if (ntoh16_ua((void *)&pvt_data->bcm_hdr.usr_subtype) != BCMILCP_BCM_SUBTYPE_EVENT) {
++		DHD_ERROR(("%s: mismatched subtype, bailing\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	*data_ptr = &pvt_data[1];
++
++	/* memcpy since BRCM event pkt may be unaligned. */
++	memcpy(event, &pvt_data->event, sizeof(wl_event_msg_t));
++
++	return BCME_OK;
++}
++
++int
++wl_host_event(dhd_pub_t *dhd_pub, int *ifidx, void *pktdata,
++	wl_event_msg_t *event, void **data_ptr, void *raw_event)
++{
++	bcm_event_t *pvt_data;
++	uint8 *event_data;
++	uint32 type, status, datalen, reason;
++	uint16 flags;
++	int evlen;
++
++	/* make sure it is a BRCM event pkt and record event data */
++	int ret = wl_host_event_get_data(pktdata, event, data_ptr);
++	if (ret != BCME_OK) {
++		return ret;
++	}
++
++	pvt_data = (bcm_event_t *)pktdata;
++	event_data = *data_ptr;
++
++	type = ntoh32_ua((void *)&event->event_type);
++	flags = ntoh16_ua((void *)&event->flags);
++	status = ntoh32_ua((void *)&event->status);
++	reason = ntoh32_ua((void *)&event->reason);
++	datalen = ntoh32_ua((void *)&event->datalen);
++	evlen = datalen + sizeof(bcm_event_t);
++
++	switch (type) {
++#ifdef PROP_TXSTATUS
++	case WLC_E_FIFO_CREDIT_MAP:
++		dhd_wlfc_enable(dhd_pub);
++		dhd_wlfc_FIFOcreditmap_event(dhd_pub, event_data);
++		WLFC_DBGMESG(("WLC_E_FIFO_CREDIT_MAP:(AC0,AC1,AC2,AC3),(BC_MC),(OTHER): "
++			"(%d,%d,%d,%d),(%d),(%d)\n", event_data[0], event_data[1],
++			event_data[2],
++			event_data[3], event_data[4], event_data[5]));
++		break;
++
++	case WLC_E_BCMC_CREDIT_SUPPORT:
++		dhd_wlfc_BCMCCredit_support_event(dhd_pub);
++		break;
++#ifdef LIMIT_BORROW
++	case WLC_E_ALLOW_CREDIT_BORROW:
++		dhd_wlfc_disable_credit_borrow_event(dhd_pub, event_data);
++		break;
++#endif /* LIMIT_BORROW */
++#endif /* PROP_TXSTATUS */
++
++	case WLC_E_ULP:
++#ifdef DHD_ULP
++	{
++		wl_ulp_event_t *ulp_evt = (wl_ulp_event_t *)event_data;
++
++		/* Flush and disable console messages */
++		if (ulp_evt->ulp_dongle_action == WL_ULP_DISABLE_CONSOLE) {
++#ifdef DHD_ULP_NOT_USED
++			dhd_bus_ulp_disable_console(dhd_pub);
++#endif /* DHD_ULP_NOT_USED */
++		}
++	}
++#endif /* DHD_ULP */
++		break;
++
++	case WLC_E_IF:
++		{
++		struct wl_event_data_if *ifevent = (struct wl_event_data_if *)event_data;
++
++		/* Ignore the event if NOIF is set */
++		if (ifevent->reserved & WLC_E_IF_FLAGS_BSSCFG_NOIF) {
++			DHD_ERROR(("WLC_E_IF: NO_IF set, event Ignored\r\n"));
++			return (BCME_UNSUPPORTED);
++		}
++#ifdef PCIE_FULL_DONGLE
++		dhd_update_interface_flow_info(dhd_pub, ifevent->ifidx,
++			ifevent->opcode, ifevent->role);
++#endif
++#ifdef PROP_TXSTATUS
++		{
++			uint8* ea = pvt_data->eth.ether_dhost;
++			WLFC_DBGMESG(("WLC_E_IF: idx:%d, action:%s, iftype:%s, "
++			              "[%02x:%02x:%02x:%02x:%02x:%02x]\n",
++			              ifevent->ifidx,
++			              ((ifevent->opcode == WLC_E_IF_ADD) ? "ADD":"DEL"),
++			              ((ifevent->role == 0) ? "STA":"AP "),
++			              ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]));
++			(void)ea;
++
++			if (ifevent->opcode == WLC_E_IF_CHANGE)
++				dhd_wlfc_interface_event(dhd_pub,
++					eWLFC_MAC_ENTRY_ACTION_UPDATE,
++					ifevent->ifidx, ifevent->role, ea);
++			else
++				dhd_wlfc_interface_event(dhd_pub,
++					((ifevent->opcode == WLC_E_IF_ADD) ?
++					eWLFC_MAC_ENTRY_ACTION_ADD : eWLFC_MAC_ENTRY_ACTION_DEL),
++					ifevent->ifidx, ifevent->role, ea);
++
++			/* dhd already has created an interface by default, for 0 */
++			if (ifevent->ifidx == 0)
++				break;
++		}
++#endif /* PROP_TXSTATUS */
++
++		if (ifevent->ifidx > 0 && ifevent->ifidx < DHD_MAX_IFS) {
++			if (ifevent->opcode == WLC_E_IF_ADD) {
++				if (dhd_event_ifadd(dhd_pub->info, ifevent, event->ifname,
++					event->addr.octet)) {
++
++					DHD_ERROR(("%s: dhd_event_ifadd failed ifidx: %d  %s\n",
++						__FUNCTION__, ifevent->ifidx, event->ifname));
++					return (BCME_ERROR);
++				}
++			} else if (ifevent->opcode == WLC_E_IF_DEL) {
++				dhd_event_ifdel(dhd_pub->info, ifevent, event->ifname,
++					event->addr.octet);
++			} else if (ifevent->opcode == WLC_E_IF_CHANGE) {
++#ifdef WL_CFG80211
++				wl_cfg80211_notify_ifchange(ifevent->ifidx,
++					event->ifname, event->addr.octet, ifevent->bssidx);
++#endif /* WL_CFG80211 */
++			}
++		} else {
++#if !defined(PROP_TXSTATUS) && !defined(PCIE_FULL_DONGLE) && defined(WL_CFG80211)
++			DHD_ERROR(("%s: Invalid ifidx %d for %s\n",
++			           __FUNCTION__, ifevent->ifidx, event->ifname));
++#endif /* !PROP_TXSTATUS && !PCIE_FULL_DONGLE && WL_CFG80211 */
++		}
++			/* send up the if event: btamp user needs it */
++			*ifidx = dhd_ifname2idx(dhd_pub->info, event->ifname);
++			/* push up to external supp/auth */
++			dhd_event(dhd_pub->info, (char *)pvt_data, evlen, *ifidx);
++		break;
++	}
++
++#ifdef WLMEDIA_HTSF
++	case WLC_E_HTSFSYNC:
++		htsf_update(dhd_pub->info, event_data);
++		break;
++#endif /* WLMEDIA_HTSF */
++	case WLC_E_NDIS_LINK:
++		break;
++	case WLC_E_PFN_NET_FOUND:
++	case WLC_E_PFN_SCAN_ALLGONE: /* share with WLC_E_PFN_BSSID_NET_LOST */
++	case WLC_E_PFN_NET_LOST:
++		break;
++#if defined(PNO_SUPPORT)
++	case WLC_E_PFN_BSSID_NET_FOUND:
++	case WLC_E_PFN_BEST_BATCHING:
++		dhd_pno_event_handler(dhd_pub, event, (void *)event_data);
++		break;
++#endif 
++#if defined(RTT_SUPPORT)
++	case WLC_E_PROXD:
++		dhd_rtt_event_handler(dhd_pub, event, (void *)event_data);
++		break;
++#endif /* RTT_SUPPORT */
++		/* These are what external supplicant/authenticator wants */
++	case WLC_E_ASSOC_IND:
++	case WLC_E_AUTH_IND:
++	case WLC_E_REASSOC_IND:
++		dhd_findadd_sta(dhd_pub,
++			dhd_ifname2idx(dhd_pub->info, event->ifname),
++			&event->addr.octet);
++		break;
++#if !defined(BCMDBUS) && defined(DHD_FW_COREDUMP)
++	case WLC_E_PSM_WATCHDOG:
++		DHD_ERROR(("%s: WLC_E_PSM_WATCHDOG event received : \n", __FUNCTION__));
++		if (dhd_socram_dump(dhd_pub->bus) != BCME_OK) {
++			DHD_ERROR(("%s: socram dump ERROR : \n", __FUNCTION__));
++		}
++	break;
++#endif
++#ifdef DHD_WMF
++	case WLC_E_PSTA_PRIMARY_INTF_IND:
++		dhd_update_psta_interface_for_sta(dhd_pub, event->ifname,
++			(void *)(event->addr.octet), (void*) event_data);
++		break;
++#endif
++	case WLC_E_LINK:
++#ifdef PCIE_FULL_DONGLE
++		if (dhd_update_interface_link_status(dhd_pub, (uint8)dhd_ifname2idx(dhd_pub->info,
++			event->ifname), (uint8)flags) != BCME_OK)
++			break;
++		if (!flags) {
++			dhd_flow_rings_delete(dhd_pub, (uint8)dhd_ifname2idx(dhd_pub->info,
++				event->ifname));
++		}
++		/* fall through */
++#endif
++	case WLC_E_DEAUTH:
++	case WLC_E_DEAUTH_IND:
++	case WLC_E_DISASSOC:
++	case WLC_E_DISASSOC_IND:
++		DHD_EVENT(("%s: Link event %d, flags %x, status %x\n",
++		           __FUNCTION__, type, flags, status));
++#ifdef PCIE_FULL_DONGLE
++		if (type != WLC_E_LINK) {
++			uint8 ifindex = (uint8)dhd_ifname2idx(dhd_pub->info, event->ifname);
++			uint8 role = dhd_flow_rings_ifindex2role(dhd_pub, ifindex);
++			uint8 del_sta = TRUE;
++#ifdef WL_CFG80211
++			if (role == WLC_E_IF_ROLE_STA && !wl_cfg80211_is_roam_offload() &&
++				!wl_cfg80211_is_event_from_connected_bssid(event, *ifidx)) {
++				del_sta = FALSE;
++			}
++#endif /* WL_CFG80211 */
++
++			if (del_sta) {
++				dhd_del_sta(dhd_pub, dhd_ifname2idx(dhd_pub->info,
++					event->ifname), &event->addr.octet);
++				if (role == WLC_E_IF_ROLE_STA) {
++					dhd_flow_rings_delete(dhd_pub, ifindex);
++				} else {
++					dhd_flow_rings_delete_for_peer(dhd_pub, ifindex,
++						&event->addr.octet[0]);
++				}
++			}
++		}
++#endif /* PCIE_FULL_DONGLE */
++		/* fall through */
++
++	default:
++		*ifidx = dhd_ifname2idx(dhd_pub->info, event->ifname);
++		/* push up to external supp/auth */
++		dhd_event(dhd_pub->info, (char *)pvt_data, evlen, *ifidx);
++		DHD_TRACE(("%s: MAC event %d, flags %x, status %x\n",
++		           __FUNCTION__, type, flags, status));
++		BCM_REFERENCE(flags);
++		BCM_REFERENCE(status);
++		BCM_REFERENCE(reason);
++
++		break;
++	}
++#if defined(STBAP)
++	/* For routers, EAPD will be working on these events.
++	 * Overwrite interface name to that event is pushed
++	 * to host with its registered interface name
++	 */
++	memcpy(pvt_data->event.ifname, dhd_ifname(dhd_pub, *ifidx), IFNAMSIZ);
++#endif
++
++#ifdef SHOW_EVENTS
++	if (DHD_FWLOG_ON() || DHD_EVENT_ON()) {
++		wl_show_host_event(dhd_pub, event,
++			(void *)event_data, raw_event, dhd_pub->enable_log);
++	}
++#endif /* SHOW_EVENTS */
++
++	return (BCME_OK);
++}
++
++void
++dhd_print_buf(void *pbuf, int len, int bytes_per_line)
++{
++#ifdef DHD_DEBUG
++	int i, j = 0;
++	unsigned char *buf = pbuf;
++
++	if (bytes_per_line == 0) {
++		bytes_per_line = len;
++	}
++
++	for (i = 0; i < len; i++) {
++		printf("%2.2x", *buf++);
++		j++;
++		if (j == bytes_per_line) {
++			printf("\n");
++			j = 0;
++		} else {
++			printf(":");
++		}
++	}
++	printf("\n");
++#endif /* DHD_DEBUG */
++}
++#ifndef strtoul
++#define strtoul(nptr, endptr, base) bcm_strtoul((nptr), (endptr), (base))
++#endif
++
++#ifdef PKT_FILTER_SUPPORT
++/* Convert user's input in hex pattern to byte-size mask */
++static int
++wl_pattern_atoh(char *src, char *dst)
++{
++	int i;
++	if (strncmp(src, "0x", 2) != 0 &&
++	    strncmp(src, "0X", 2) != 0) {
++		DHD_ERROR(("Mask invalid format. Needs to start with 0x\n"));
++		return -1;
++	}
++	src = src + 2; /* Skip past 0x */
++	if (strlen(src) % 2 != 0) {
++		DHD_ERROR(("Mask invalid format. Needs to be of even length\n"));
++		return -1;
++	}
++	for (i = 0; *src != '\0'; i++) {
++		char num[3];
++		bcm_strncpy_s(num, sizeof(num), src, 2);
++		num[2] = '\0';
++		dst[i] = (uint8)strtoul(num, NULL, 16);
++		src += 2;
++	}
++	return i;
++}
++
++void
++dhd_pktfilter_offload_enable(dhd_pub_t * dhd, char *arg, int enable, int master_mode)
++{
++	char				*argv[8];
++	int					i = 0;
++	const char			*str;
++	int					buf_len;
++	int					str_len;
++	char				*arg_save = 0, *arg_org = 0;
++	int					rc;
++	char				buf[32] = {0};
++	wl_pkt_filter_enable_t	enable_parm;
++	wl_pkt_filter_enable_t	* pkt_filterp;
++
++	if (!arg)
++		return;
++
++	if (!(arg_save = MALLOC(dhd->osh, strlen(arg) + 1))) {
++		DHD_ERROR(("%s: malloc failed\n", __FUNCTION__));
++		goto fail;
++	}
++	arg_org = arg_save;
++	memcpy(arg_save, arg, strlen(arg) + 1);
++
++	argv[i] = bcmstrtok(&arg_save, " ", 0);
++
++	i = 0;
++	if (argv[i] == NULL) {
++		DHD_ERROR(("No args provided\n"));
++		goto fail;
++	}
++
++	str = "pkt_filter_enable";
++	str_len = strlen(str);
++	bcm_strncpy_s(buf, sizeof(buf) - 1, str, sizeof(buf) - 1);
++	buf[ sizeof(buf) - 1 ] = '\0';
++	buf_len = str_len + 1;
++
++	pkt_filterp = (wl_pkt_filter_enable_t *)(buf + str_len + 1);
++
++	/* Parse packet filter id. */
++	enable_parm.id = htod32(strtoul(argv[i], NULL, 0));
++
++	/* Parse enable/disable value. */
++	enable_parm.enable = htod32(enable);
++
++	buf_len += sizeof(enable_parm);
++	memcpy((char *)pkt_filterp,
++	       &enable_parm,
++	       sizeof(enable_parm));
++
++	/* Enable/disable the specified filter. */
++	rc = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, buf, buf_len, TRUE, 0);
++	rc = rc >= 0 ? 0 : rc;
++	if (rc)
++		DHD_TRACE(("%s: failed to add pktfilter %s, retcode = %d\n",
++		__FUNCTION__, arg, rc));
++	else
++		DHD_TRACE(("%s: successfully added pktfilter %s\n",
++		__FUNCTION__, arg));
++
++	/* Contorl the master mode */
++	rc = dhd_wl_ioctl_set_intiovar(dhd, "pkt_filter_mode",
++		master_mode, WLC_SET_VAR, TRUE, 0);
++	rc = rc >= 0 ? 0 : rc;
++	if (rc)
++		DHD_TRACE(("%s: failed to add pktfilter %s, retcode = %d\n",
++		__FUNCTION__, arg, rc));
++
++fail:
++	if (arg_org)
++		MFREE(dhd->osh, arg_org, strlen(arg) + 1);
++}
++
++void
++dhd_pktfilter_offload_set(dhd_pub_t * dhd, char *arg)
++{
++	const char 			*str;
++	wl_pkt_filter_t		pkt_filter;
++	wl_pkt_filter_t		*pkt_filterp;
++	int					buf_len;
++	int					str_len;
++	int 				rc;
++	uint32				mask_size;
++	uint32				pattern_size;
++	char				*argv[8], * buf = 0;
++	int					i = 0;
++	char				*arg_save = 0, *arg_org = 0;
++#define BUF_SIZE		2048
++
++	if (!arg)
++		return;
++
++	if (!(arg_save = MALLOC(dhd->osh, strlen(arg) + 1))) {
++		DHD_ERROR(("%s: malloc failed\n", __FUNCTION__));
++		goto fail;
++	}
++
++	arg_org = arg_save;
++
++	if (!(buf = MALLOC(dhd->osh, BUF_SIZE))) {
++		DHD_ERROR(("%s: malloc failed\n", __FUNCTION__));
++		goto fail;
++	}
++
++	memcpy(arg_save, arg, strlen(arg) + 1);
++
++	if (strlen(arg) > BUF_SIZE) {
++		DHD_ERROR(("Not enough buffer %d < %d\n", (int)strlen(arg), (int)sizeof(buf)));
++		goto fail;
++	}
++
++	argv[i] = bcmstrtok(&arg_save, " ", 0);
++	while (argv[i++])
++		argv[i] = bcmstrtok(&arg_save, " ", 0);
++
++	i = 0;
++	if (argv[i] == NULL) {
++		DHD_ERROR(("No args provided\n"));
++		goto fail;
++	}
++
++	str = "pkt_filter_add";
++	str_len = strlen(str);
++	bcm_strncpy_s(buf, BUF_SIZE, str, str_len);
++	buf[ str_len ] = '\0';
++	buf_len = str_len + 1;
++
++	pkt_filterp = (wl_pkt_filter_t *) (buf + str_len + 1);
++
++	/* Parse packet filter id. */
++	pkt_filter.id = htod32(strtoul(argv[i], NULL, 0));
++
++	if (argv[++i] == NULL) {
++		DHD_ERROR(("Polarity not provided\n"));
++		goto fail;
++	}
++
++	/* Parse filter polarity. */
++	pkt_filter.negate_match = htod32(strtoul(argv[i], NULL, 0));
++
++	if (argv[++i] == NULL) {
++		DHD_ERROR(("Filter type not provided\n"));
++		goto fail;
++	}
++
++	/* Parse filter type. */
++	pkt_filter.type = htod32(strtoul(argv[i], NULL, 0));
++
++	if (argv[++i] == NULL) {
++		DHD_ERROR(("Offset not provided\n"));
++		goto fail;
++	}
++
++	/* Parse pattern filter offset. */
++	pkt_filter.u.pattern.offset = htod32(strtoul(argv[i], NULL, 0));
++
++	if (argv[++i] == NULL) {
++		DHD_ERROR(("Bitmask not provided\n"));
++		goto fail;
++	}
++
++	/* Parse pattern filter mask. */
++	mask_size =
++		htod32(wl_pattern_atoh(argv[i], (char *) pkt_filterp->u.pattern.mask_and_pattern));
++
++	if (argv[++i] == NULL) {
++		DHD_ERROR(("Pattern not provided\n"));
++		goto fail;
++	}
++
++	/* Parse pattern filter pattern. */
++	pattern_size =
++		htod32(wl_pattern_atoh(argv[i],
++	         (char *) &pkt_filterp->u.pattern.mask_and_pattern[mask_size]));
++
++	if (mask_size != pattern_size) {
++		DHD_ERROR(("Mask and pattern not the same size\n"));
++		goto fail;
++	}
++
++	pkt_filter.u.pattern.size_bytes = mask_size;
++	buf_len += WL_PKT_FILTER_FIXED_LEN;
++	buf_len += (WL_PKT_FILTER_PATTERN_FIXED_LEN + 2 * mask_size);
++
++	/* Keep-alive attributes are set in local	variable (keep_alive_pkt), and
++	** then memcpy'ed into buffer (keep_alive_pktp) since there is no
++	** guarantee that the buffer is properly aligned.
++	*/
++	memcpy((char *)pkt_filterp,
++	       &pkt_filter,
++	       WL_PKT_FILTER_FIXED_LEN + WL_PKT_FILTER_PATTERN_FIXED_LEN);
++
++	rc = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, buf, buf_len, TRUE, 0);
++	rc = rc >= 0 ? 0 : rc;
++
++	if (rc)
++		DHD_TRACE(("%s: failed to add pktfilter %s, retcode = %d\n",
++		__FUNCTION__, arg, rc));
++	else
++		DHD_TRACE(("%s: successfully added pktfilter %s\n",
++		__FUNCTION__, arg));
++
++fail:
++	if (arg_org)
++		MFREE(dhd->osh, arg_org, strlen(arg) + 1);
++
++	if (buf)
++		MFREE(dhd->osh, buf, BUF_SIZE);
++}
++
++void dhd_pktfilter_offload_delete(dhd_pub_t *dhd, int id)
++{
++	int ret;
++
++	ret = dhd_wl_ioctl_set_intiovar(dhd, "pkt_filter_delete",
++		id, WLC_SET_VAR, TRUE, 0);
++	if (ret < 0) {
++		DHD_ERROR(("%s: Failed to delete filter ID:%d, ret=%d\n",
++			__FUNCTION__, id, ret));
++	}
++}
++#endif /* PKT_FILTER_SUPPORT */
++
++/* ========================== */
++/* ==== ARP OFFLOAD SUPPORT = */
++/* ========================== */
++#ifdef ARP_OFFLOAD_SUPPORT
++void
++dhd_arp_offload_set(dhd_pub_t * dhd, int arp_mode)
++{
++	int retcode;
++
++	retcode = dhd_wl_ioctl_set_intiovar(dhd, "arp_ol",
++		arp_mode, WLC_SET_VAR, TRUE, 0);
++
++	retcode = retcode >= 0 ? 0 : retcode;
++	if (retcode)
++		DHD_TRACE(("%s: failed to set ARP offload mode to 0x%x, retcode = %d\n",
++			__FUNCTION__, arp_mode, retcode));
++	else
++		DHD_TRACE(("%s: successfully set ARP offload mode to 0x%x\n",
++			__FUNCTION__, arp_mode));
++}
++
++void
++dhd_arp_offload_enable(dhd_pub_t * dhd, int arp_enable)
++{
++	int retcode;
++
++	retcode = dhd_wl_ioctl_set_intiovar(dhd, "arpoe",
++		arp_enable, WLC_SET_VAR, TRUE, 0);
++
++	retcode = retcode >= 0 ? 0 : retcode;
++	if (retcode)
++		DHD_TRACE(("%s: failed to enabe ARP offload to %d, retcode = %d\n",
++			__FUNCTION__, arp_enable, retcode));
++	else
++		DHD_TRACE(("%s: successfully enabed ARP offload to %d\n",
++			__FUNCTION__, arp_enable));
++	if (arp_enable) {
++		uint32 version;
++		retcode = dhd_wl_ioctl_get_intiovar(dhd, "arp_version",
++			&version, WLC_GET_VAR, FALSE, 0);
++		if (retcode) {
++			DHD_INFO(("%s: fail to get version (maybe version 1:retcode = %d\n",
++				__FUNCTION__, retcode));
++			dhd->arp_version = 1;
++		}
++		else {
++			DHD_INFO(("%s: ARP Version= %x\n", __FUNCTION__, version));
++			dhd->arp_version = version;
++		}
++	}
++}
++
++void
++dhd_aoe_arp_clr(dhd_pub_t *dhd, int idx)
++{
++	int ret = 0;
++
++	if (dhd == NULL) return;
++	if (dhd->arp_version == 1)
++		idx = 0;
++
++	ret = dhd_iovar(dhd, idx, "arp_table_clear", NULL, 0, NULL, 0, TRUE);
++	if (ret < 0)
++		DHD_ERROR(("%s failed code %d\n", __FUNCTION__, ret));
++}
++
++void
++dhd_aoe_hostip_clr(dhd_pub_t *dhd, int idx)
++{
++	int ret = 0;
++
++	if (dhd == NULL) return;
++	if (dhd->arp_version == 1)
++		idx = 0;
++
++	ret = dhd_iovar(dhd, idx, "arp_hostip_clear", NULL, 0, NULL, 0, TRUE);
++	if (ret < 0)
++		DHD_ERROR(("%s failed code %d\n", __FUNCTION__, ret));
++}
++
++void
++dhd_arp_offload_add_ip(dhd_pub_t *dhd, uint32 ipaddr, int idx)
++{
++	int ret;
++
++	if (dhd == NULL) return;
++	if (dhd->arp_version == 1)
++		idx = 0;
++
++	ret = dhd_iovar(dhd, idx, "arp_hostip", (char *)&ipaddr, sizeof(ipaddr),
++			NULL, 0, TRUE);
++	if (ret)
++		DHD_TRACE(("%s: ARP ip addr add failed, ret = %d\n", __FUNCTION__, ret));
++	else
++		DHD_TRACE(("%s: sARP H ipaddr entry added \n",
++		__FUNCTION__));
++}
++
++int
++dhd_arp_get_arp_hostip_table(dhd_pub_t *dhd, void *buf, int buflen, int idx)
++{
++	int ret, i;
++	uint32 *ptr32 = buf;
++	bool clr_bottom = FALSE;
++
++	if (!buf)
++		return -1;
++	if (dhd == NULL) return -1;
++	if (dhd->arp_version == 1)
++		idx = 0;
++
++	ret = dhd_iovar(dhd, idx, "arp_hostip", NULL, 0, (char *)buf, buflen,
++			FALSE);
++	if (ret) {
++		DHD_TRACE(("%s: ioctl WLC_GET_VAR error %d\n",
++		__FUNCTION__, ret));
++
++		return -1;
++	}
++
++	/* clean up the buf, ascii reminder */
++	for (i = 0; i < MAX_IPV4_ENTRIES; i++) {
++		if (!clr_bottom) {
++			if (*ptr32 == 0)
++				clr_bottom = TRUE;
++		} else {
++			*ptr32 = 0;
++		}
++		ptr32++;
++	}
++
++	return 0;
++}
++#endif /* ARP_OFFLOAD_SUPPORT  */
++
++/*
++ * Neighbor Discovery Offload: enable NDO feature
++ * Called  by ipv6 event handler when interface comes up/goes down
++ */
++int
++dhd_ndo_enable(dhd_pub_t * dhd, int ndo_enable)
++{
++	int retcode;
++
++	if (dhd == NULL)
++		return -1;
++
++	retcode = dhd_wl_ioctl_set_intiovar(dhd, "ndoe",
++		ndo_enable, WLC_SET_VAR, TRUE, 0);
++	if (retcode)
++		DHD_ERROR(("%s: failed to enabe ndo to %d, retcode = %d\n",
++			__FUNCTION__, ndo_enable, retcode));
++	else
++		DHD_TRACE(("%s: successfully enabed ndo offload to %d\n",
++			__FUNCTION__, ndo_enable));
++
++	return retcode;
++}
++
++/*
++ * Neighbor Discover Offload: enable NDO feature
++ * Called  by ipv6 event handler when interface comes up
++ */
++int
++dhd_ndo_add_ip(dhd_pub_t *dhd, char* ipv6addr, int idx)
++{
++	int iov_len = 0;
++	char iovbuf[DHD_IOVAR_BUF_SIZE];
++	int retcode;
++
++	if (dhd == NULL)
++		return -1;
++
++	iov_len = bcm_mkiovar("nd_hostip", (char *)ipv6addr,
++		IPV6_ADDR_LEN, iovbuf, sizeof(iovbuf));
++	if (!iov_len) {
++		DHD_ERROR(("%s: Insufficient iovar buffer size %zu \n",
++			__FUNCTION__, sizeof(iovbuf)));
++		return -1;
++	}
++	retcode = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, iovbuf, iov_len, TRUE, idx);
++
++	if (retcode)
++		DHD_ERROR(("%s: ndo ip addr add failed, retcode = %d\n",
++		__FUNCTION__, retcode));
++	else
++		DHD_TRACE(("%s: ndo ipaddr entry added \n",
++		__FUNCTION__));
++
++	return retcode;
++}
++/*
++ * Neighbor Discover Offload: enable NDO feature
++ * Called  by ipv6 event handler when interface goes down
++ */
++int
++dhd_ndo_remove_ip(dhd_pub_t *dhd, int idx)
++{
++	int iov_len = 0;
++	char iovbuf[DHD_IOVAR_BUF_SIZE];
++	int retcode;
++
++	if (dhd == NULL)
++		return -1;
++
++	iov_len = bcm_mkiovar("nd_hostip_clear", NULL,
++		0, iovbuf, sizeof(iovbuf));
++	if (!iov_len) {
++		DHD_ERROR(("%s: Insufficient iovar buffer size %zu \n",
++			__FUNCTION__, sizeof(iovbuf)));
++		return -1;
++	}
++	retcode = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, iovbuf, iov_len, TRUE, idx);
++
++	if (retcode)
++		DHD_ERROR(("%s: ndo ip addr remove failed, retcode = %d\n",
++		__FUNCTION__, retcode));
++	else
++		DHD_TRACE(("%s: ndo ipaddr entry removed \n",
++		__FUNCTION__));
++
++	return retcode;
++}
++
++
++
++/*
++ * returns = TRUE if associated, FALSE if not associated
++ */
++bool dhd_is_associated(dhd_pub_t *dhd, void *bss_buf, int *retval)
++{
++	char bssid[6], zbuf[6];
++	int ret = -1;
++
++	bzero(bssid, 6);
++	bzero(zbuf, 6);
++
++	ret  = dhd_wl_ioctl_cmd(dhd, WLC_GET_BSSID, (char *)&bssid, ETHER_ADDR_LEN, FALSE, 0);
++	DHD_TRACE((" %s WLC_GET_BSSID ioctl res = %d\n", __FUNCTION__, ret));
++
++	if (ret == BCME_NOTASSOCIATED) {
++		DHD_TRACE(("%s: not associated! res:%d\n", __FUNCTION__, ret));
++	}
++
++	if (retval)
++		*retval = ret;
++
++	if (ret < 0)
++		return FALSE;
++
++	if ((memcmp(bssid, zbuf, ETHER_ADDR_LEN) != 0)) {
++		/*  STA is assocoated BSSID is non zero */
++
++		if (bss_buf) {
++			/* return bss if caller provided buf */
++			memcpy(bss_buf, bssid, ETHER_ADDR_LEN);
++		}
++		return TRUE;
++	} else {
++		DHD_TRACE(("%s: WLC_GET_BSSID ioctl returned zero bssid\n", __FUNCTION__));
++		return FALSE;
++	}
++}
++
++/* Function to estimate possible DTIM_SKIP value */
++int
++dhd_get_suspend_bcn_li_dtim(dhd_pub_t *dhd)
++{
++	int bcn_li_dtim = 1; /* deafult no dtim skip setting */
++	int ret = -1;
++	int dtim_period = 0;
++	int ap_beacon = 0;
++#ifndef ENABLE_MAX_DTIM_IN_SUSPEND
++	int allowed_skip_dtim_cnt = 0;
++#endif /* !ENABLE_MAX_DTIM_IN_SUSPEND */
++	/* Check if associated */
++	if (dhd_is_associated(dhd, NULL, NULL) == FALSE) {
++		DHD_TRACE(("%s NOT assoc ret %d\n", __FUNCTION__, ret));
++		goto exit;
++	}
++
++	/* read associated AP beacon interval */
++	if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_GET_BCNPRD,
++		&ap_beacon, sizeof(ap_beacon), FALSE, 0)) < 0) {
++		DHD_ERROR(("%s get beacon failed code %d\n", __FUNCTION__, ret));
++		goto exit;
++	}
++
++	/* read associated ap's dtim setup */
++	if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_GET_DTIMPRD,
++		&dtim_period, sizeof(dtim_period), FALSE, 0)) < 0) {
++		DHD_ERROR(("%s failed code %d\n", __FUNCTION__, ret));
++		goto exit;
++	}
++
++	/* if not assocated just eixt */
++	if (dtim_period == 0) {
++		goto exit;
++	}
++
++#ifdef ENABLE_MAX_DTIM_IN_SUSPEND
++	bcn_li_dtim = (int) (MAX_DTIM_ALLOWED_INTERVAL / (ap_beacon * dtim_period));
++	if (bcn_li_dtim == 0) {
++		bcn_li_dtim = 1;
++	}
++#else /* ENABLE_MAX_DTIM_IN_SUSPEND */
++	/* attemp to use platform defined dtim skip interval */
++	bcn_li_dtim = dhd->suspend_bcn_li_dtim;
++
++	/* check if sta listen interval fits into AP dtim */
++	if (dtim_period > CUSTOM_LISTEN_INTERVAL) {
++		/* AP DTIM to big for our Listen Interval : no dtim skiping */
++		bcn_li_dtim = NO_DTIM_SKIP;
++		DHD_ERROR(("%s DTIM=%d > Listen=%d : too big ...\n",
++			__FUNCTION__, dtim_period, CUSTOM_LISTEN_INTERVAL));
++		goto exit;
++	}
++
++	if ((dtim_period * ap_beacon * bcn_li_dtim) > MAX_DTIM_ALLOWED_INTERVAL) {
++		 allowed_skip_dtim_cnt = MAX_DTIM_ALLOWED_INTERVAL / (dtim_period * ap_beacon);
++		 bcn_li_dtim = (allowed_skip_dtim_cnt != 0) ? allowed_skip_dtim_cnt : NO_DTIM_SKIP;
++	}
++
++	if ((bcn_li_dtim * dtim_period) > CUSTOM_LISTEN_INTERVAL) {
++		/* Round up dtim_skip to fit into STAs Listen Interval */
++		bcn_li_dtim = (int)(CUSTOM_LISTEN_INTERVAL / dtim_period);
++		DHD_TRACE(("%s agjust dtim_skip as %d\n", __FUNCTION__, bcn_li_dtim));
++	}
++#endif /* ENABLE_MAX_DTIM_IN_SUSPEND */
++
++	DHD_ERROR(("%s beacon=%d bcn_li_dtim=%d DTIM=%d Listen=%d\n",
++		__FUNCTION__, ap_beacon, bcn_li_dtim, dtim_period, CUSTOM_LISTEN_INTERVAL));
++
++exit:
++	return bcn_li_dtim;
++}
++
++/* Check if the mode supports STA MODE */
++bool dhd_support_sta_mode(dhd_pub_t *dhd)
++{
++
++#ifdef  WL_CFG80211
++	if (!(dhd->op_mode & DHD_FLAG_STA_MODE))
++		return FALSE;
++	else
++#endif /* WL_CFG80211 */
++		return TRUE;
++}
++
++#if defined(KEEP_ALIVE)
++int dhd_keep_alive_onoff(dhd_pub_t *dhd)
++{
++	char				buf[32] = {0};
++	const char			*str;
++	wl_mkeep_alive_pkt_t	mkeep_alive_pkt = {0};
++	wl_mkeep_alive_pkt_t	*mkeep_alive_pktp;
++	int					buf_len;
++	int					str_len;
++	int res					= -1;
++
++	if (!dhd_support_sta_mode(dhd))
++		return res;
++
++	DHD_TRACE(("%s execution\n", __FUNCTION__));
++
++	str = "mkeep_alive";
++	str_len = strlen(str);
++	strncpy(buf, str, sizeof(buf) - 1);
++	buf[ sizeof(buf) - 1 ] = '\0';
++	mkeep_alive_pktp = (wl_mkeep_alive_pkt_t *) (buf + str_len + 1);
++	mkeep_alive_pkt.period_msec = CUSTOM_KEEP_ALIVE_SETTING;
++	buf_len = str_len + 1;
++	mkeep_alive_pkt.version = htod16(WL_MKEEP_ALIVE_VERSION);
++	mkeep_alive_pkt.length = htod16(WL_MKEEP_ALIVE_FIXED_LEN);
++	/* Setup keep alive zero for null packet generation */
++	mkeep_alive_pkt.keep_alive_id = 0;
++	mkeep_alive_pkt.len_bytes = 0;
++	buf_len += WL_MKEEP_ALIVE_FIXED_LEN;
++	bzero(mkeep_alive_pkt.data, sizeof(mkeep_alive_pkt.data));
++	/* Keep-alive attributes are set in local	variable (mkeep_alive_pkt), and
++	 * then memcpy'ed into buffer (mkeep_alive_pktp) since there is no
++	 * guarantee that the buffer is properly aligned.
++	 */
++	memcpy((char *)mkeep_alive_pktp, &mkeep_alive_pkt, WL_MKEEP_ALIVE_FIXED_LEN);
++
++	res = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, buf, buf_len, TRUE, 0);
++
++	return res;
++}
++#endif /* defined(KEEP_ALIVE) */
++/* Android ComboSCAN support */
++
++/*
++ *  data parsing from ComboScan tlv list
++*/
++int
++wl_iw_parse_data_tlv(char** list_str, void *dst, int dst_size, const char token,
++                     int input_size, int *bytes_left)
++{
++	char* str;
++	uint16 short_temp;
++	uint32 int_temp;
++
++	if ((list_str == NULL) || (*list_str == NULL) ||(bytes_left == NULL) || (*bytes_left < 0)) {
++		DHD_ERROR(("%s error paramters\n", __FUNCTION__));
++		return -1;
++	}
++	str = *list_str;
++
++	/* Clean all dest bytes */
++	memset(dst, 0, dst_size);
++	while (*bytes_left > 0) {
++
++		if (str[0] != token) {
++			DHD_TRACE(("%s NOT Type=%d get=%d left_parse=%d \n",
++				__FUNCTION__, token, str[0], *bytes_left));
++			return -1;
++		}
++
++		*bytes_left -= 1;
++		str += 1;
++
++		if (input_size == 1) {
++			memcpy(dst, str, input_size);
++		}
++		else if (input_size == 2) {
++			memcpy(dst, (char *)htod16(memcpy(&short_temp, str, input_size)),
++				input_size);
++		}
++		else if (input_size == 4) {
++			memcpy(dst, (char *)htod32(memcpy(&int_temp, str, input_size)),
++				input_size);
++		}
++
++		*bytes_left -= input_size;
++		str += input_size;
++		*list_str = str;
++		return 1;
++	}
++	return 1;
++}
++
++/*
++ *  channel list parsing from cscan tlv list
++*/
++int
++wl_iw_parse_channel_list_tlv(char** list_str, uint16* channel_list,
++                             int channel_num, int *bytes_left)
++{
++	char* str;
++	int idx = 0;
++
++	if ((list_str == NULL) || (*list_str == NULL) ||(bytes_left == NULL) || (*bytes_left < 0)) {
++		DHD_ERROR(("%s error paramters\n", __FUNCTION__));
++		return -1;
++	}
++	str = *list_str;
++
++	while (*bytes_left > 0) {
++
++		if (str[0] != CSCAN_TLV_TYPE_CHANNEL_IE) {
++			*list_str = str;
++			DHD_TRACE(("End channel=%d left_parse=%d %d\n", idx, *bytes_left, str[0]));
++			return idx;
++		}
++		/* Get proper CSCAN_TLV_TYPE_CHANNEL_IE */
++		*bytes_left -= 1;
++		str += 1;
++
++		if (str[0] == 0) {
++			/* All channels */
++			channel_list[idx] = 0x0;
++		}
++		else {
++			channel_list[idx] = (uint16)str[0];
++			DHD_TRACE(("%s channel=%d \n", __FUNCTION__,  channel_list[idx]));
++		}
++		*bytes_left -= 1;
++		str += 1;
++
++		if (idx++ > 255) {
++			DHD_ERROR(("%s Too many channels \n", __FUNCTION__));
++			return -1;
++		}
++	}
++
++	*list_str = str;
++	return idx;
++}
++
++/*
++ *  SSIDs list parsing from cscan tlv list
++ */
++int
++wl_iw_parse_ssid_list_tlv(char** list_str, wlc_ssid_ext_t* ssid, int max, int *bytes_left)
++{
++	char* str;
++	int idx = 0;
++
++	if ((list_str == NULL) || (*list_str == NULL) || (*bytes_left < 0)) {
++		DHD_ERROR(("%s error paramters\n", __FUNCTION__));
++		return -1;
++	}
++	str = *list_str;
++	while (*bytes_left > 0) {
++
++		if (str[0] != CSCAN_TLV_TYPE_SSID_IE) {
++			*list_str = str;
++			DHD_TRACE(("nssid=%d left_parse=%d %d\n", idx, *bytes_left, str[0]));
++			return idx;
++		}
++
++		/* Get proper CSCAN_TLV_TYPE_SSID_IE */
++		*bytes_left -= 1;
++		str += 1;
++		ssid[idx].rssi_thresh = 0;
++		if (str[0] == 0) {
++			/* Broadcast SSID */
++			ssid[idx].SSID_len = 0;
++			memset((char*)ssid[idx].SSID, 0x0, DOT11_MAX_SSID_LEN);
++			*bytes_left -= 1;
++			str += 1;
++
++			DHD_TRACE(("BROADCAST SCAN  left=%d\n", *bytes_left));
++		}
++		else if (str[0] <= DOT11_MAX_SSID_LEN) {
++			/* Get proper SSID size */
++			ssid[idx].SSID_len = str[0];
++			*bytes_left -= 1;
++			str += 1;
++
++			/* Get SSID */
++			if (ssid[idx].SSID_len > *bytes_left) {
++				DHD_ERROR(("%s out of memory range len=%d but left=%d\n",
++				__FUNCTION__, ssid[idx].SSID_len, *bytes_left));
++				return -1;
++			}
++
++			memcpy((char*)ssid[idx].SSID, str, ssid[idx].SSID_len);
++
++			*bytes_left -= ssid[idx].SSID_len;
++			str += ssid[idx].SSID_len;
++			ssid[idx].hidden = TRUE;
++
++			DHD_TRACE(("%s :size=%d left=%d\n",
++				(char*)ssid[idx].SSID, ssid[idx].SSID_len, *bytes_left));
++		}
++		else {
++			DHD_ERROR(("### SSID size more that %d\n", str[0]));
++			return -1;
++		}
++
++		if (idx++ >  max) {
++			DHD_ERROR(("%s number of SSIDs more that %d\n", __FUNCTION__, idx));
++			return -1;
++		}
++	}
++
++	*list_str = str;
++	return idx;
++}
++
++/* Parse a comma-separated list from list_str into ssid array, starting
++ * at index idx.  Max specifies size of the ssid array.  Parses ssids
++ * and returns updated idx; if idx >= max not all fit, the excess have
++ * not been copied.  Returns -1 on empty string, or on ssid too long.
++ */
++int
++wl_iw_parse_ssid_list(char** list_str, wlc_ssid_t* ssid, int idx, int max)
++{
++	char* str, *ptr;
++
++	if ((list_str == NULL) || (*list_str == NULL))
++		return -1;
++
++	for (str = *list_str; str != NULL; str = ptr) {
++
++		/* check for next TAG */
++		if (!strncmp(str, GET_CHANNEL, strlen(GET_CHANNEL))) {
++			*list_str	 = str + strlen(GET_CHANNEL);
++			return idx;
++		}
++
++		if ((ptr = strchr(str, ',')) != NULL) {
++			*ptr++ = '\0';
++		}
++
++		if (strlen(str) > DOT11_MAX_SSID_LEN) {
++			DHD_ERROR(("ssid <%s> exceeds %d\n", str, DOT11_MAX_SSID_LEN));
++			return -1;
++		}
++
++		if (strlen(str) == 0)
++			ssid[idx].SSID_len = 0;
++
++		if (idx < max) {
++			bzero(ssid[idx].SSID, sizeof(ssid[idx].SSID));
++			strncpy((char*)ssid[idx].SSID, str, sizeof(ssid[idx].SSID) - 1);
++			ssid[idx].SSID_len = strlen(str);
++		}
++		idx++;
++	}
++	return idx;
++}
++
++/*
++ * Parse channel list from iwpriv CSCAN
++ */
++int
++wl_iw_parse_channel_list(char** list_str, uint16* channel_list, int channel_num)
++{
++	int num;
++	int val;
++	char* str;
++	char* endptr = NULL;
++
++	if ((list_str == NULL)||(*list_str == NULL))
++		return -1;
++
++	str = *list_str;
++	num = 0;
++	while (strncmp(str, GET_NPROBE, strlen(GET_NPROBE))) {
++		val = (int)strtoul(str, &endptr, 0);
++		if (endptr == str) {
++			printf("could not parse channel number starting at"
++				" substring \"%s\" in list:\n%s\n",
++				str, *list_str);
++			return -1;
++		}
++		str = endptr + strspn(endptr, " ,");
++
++		if (num == channel_num) {
++			DHD_ERROR(("too many channels (more than %d) in channel list:\n%s\n",
++				channel_num, *list_str));
++			return -1;
++		}
++
++		channel_list[num++] = (uint16)val;
++	}
++	*list_str = str;
++	return num;
++}
++
++#if defined(TRAFFIC_MGMT_DWM)
++static int traffic_mgmt_add_dwm_filter(dhd_pub_t *dhd,
++	trf_mgmt_filter_list_t * trf_mgmt_filter_list, int len)
++{
++	int ret = 0;
++	uint32              i;
++	trf_mgmt_filter_t   *trf_mgmt_filter;
++	uint8               dwm_tbl_entry;
++	uint32              dscp = 0;
++	uint16              dwm_filter_enabled = 0;
++
++
++	/* Check parameter length is adequate */
++	if (len < (OFFSETOF(trf_mgmt_filter_list_t, filter) +
++		trf_mgmt_filter_list->num_filters * sizeof(trf_mgmt_filter_t))) {
++		ret = BCME_BUFTOOSHORT;
++		return ret;
++	}
++
++	bzero(&dhd->dhd_tm_dwm_tbl, sizeof(dhd_trf_mgmt_dwm_tbl_t));
++
++	for (i = 0; i < trf_mgmt_filter_list->num_filters; i++) {
++		trf_mgmt_filter = &trf_mgmt_filter_list->filter[i];
++
++		dwm_filter_enabled = (trf_mgmt_filter->flags & TRF_FILTER_DWM);
++
++		if (dwm_filter_enabled) {
++			dscp = trf_mgmt_filter->dscp;
++			if (dscp >= DHD_DWM_TBL_SIZE) {
++				ret = BCME_BADARG;
++			return ret;
++			}
++		}
++
++		dhd->dhd_tm_dwm_tbl.dhd_dwm_enabled = 1;
++		/* set WMM AC bits */
++		dwm_tbl_entry = (uint8) trf_mgmt_filter->priority;
++		DHD_TRF_MGMT_DWM_SET_FILTER(dwm_tbl_entry);
++
++		/* set favored bits */
++		if (trf_mgmt_filter->flags & TRF_FILTER_FAVORED)
++			DHD_TRF_MGMT_DWM_SET_FAVORED(dwm_tbl_entry);
++
++		dhd->dhd_tm_dwm_tbl.dhd_dwm_tbl[dscp] =  dwm_tbl_entry;
++	}
++	return ret;
++}
++#endif 
++
++/* Given filename and download type,  returns a buffer pointer and length
++ * for download to f/w. Type can be FW or NVRAM.
++ *
++ */
++int dhd_get_download_buffer(dhd_pub_t	*dhd, char *file_path, download_type_t component,
++	char ** buffer, int *length)
++
++{
++	int ret = BCME_ERROR;
++	int len = 0;
++	int file_len;
++	void *image = NULL;
++	uint8 *buf = NULL;
++
++	/* Point to cache if available. */
++#ifdef CACHE_FW_IMAGES
++	if (component == FW) {
++		if (dhd->cached_fw_length) {
++			len = dhd->cached_fw_length;
++			buf = dhd->cached_fw;
++		}
++	} else if (component == NVRAM) {
++		if (dhd->cached_nvram_length) {
++			len = dhd->cached_nvram_length;
++			buf = dhd->cached_nvram;
++		}
++	}
++	else if (component == CLM_BLOB) {
++		if (dhd->cached_clm_length) {
++			len = dhd->cached_clm_length;
++			buf = dhd->cached_clm;
++		}
++	} else {
++		return ret;
++	}
++#endif
++	/* No Valid cache found on this call */
++	if (!len) {
++		file_len = *length;
++		*length = 0;
++
++		if (file_path) {
++			image = dhd_os_open_image(file_path);
++			if (image == NULL) {
++				goto err;
++			}
++		}
++
++		buf = MALLOCZ(dhd->osh, file_len);
++		if (buf == NULL) {
++			DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
++				__FUNCTION__, file_len));
++			goto err;
++		}
++
++		/* Download image */
++		len = dhd_os_get_image_block(buf, file_len, image);
++		if ((len <= 0 || len > file_len)) {
++			MFREE(dhd->osh, buf, file_len);
++			goto err;
++		}
++	}
++
++	ret = BCME_OK;
++	*length = len;
++	*buffer = buf;
++
++	/* Cache if first call. */
++#ifdef CACHE_FW_IMAGES
++	if (component == FW) {
++		if (!dhd->cached_fw_length) {
++			dhd->cached_fw = buf;
++			dhd->cached_fw_length = len;
++		}
++	} else if (component == NVRAM) {
++		if (!dhd->cached_nvram_length) {
++			dhd->cached_nvram = buf;
++			dhd->cached_nvram_length = len;
++		}
++	}
++	else if (component == CLM_BLOB) {
++		if (!dhd->cached_clm_length) {
++			 dhd->cached_clm = buf;
++			 dhd->cached_clm_length = len;
++		}
++	}
++#endif
++
++err:
++	if (image)
++		dhd_os_close_image(image);
++
++	return ret;
++}
++
++int
++dhd_download_2_dongle(dhd_pub_t	*dhd, char *iovar, uint16 flag, uint16 dload_type,
++	unsigned char *dload_buf, int len)
++{
++	struct wl_dload_data *dload_ptr = (struct wl_dload_data *)dload_buf;
++	int err = 0;
++	int dload_data_offset;
++	static char iovar_buf[WLC_IOCTL_MEDLEN];
++	int iovar_len;
++
++	memset(iovar_buf, 0, sizeof(iovar_buf));
++
++	dload_data_offset = OFFSETOF(wl_dload_data_t, data);
++	dload_ptr->flag = (DLOAD_HANDLER_VER << DLOAD_FLAG_VER_SHIFT) | flag;
++	dload_ptr->dload_type = dload_type;
++	dload_ptr->len = htod32(len - dload_data_offset);
++	dload_ptr->crc = 0;
++	len = len + 8 - (len%8);
++
++	iovar_len = bcm_mkiovar(iovar, dload_buf,
++		(uint)len, iovar_buf, sizeof(iovar_buf));
++	if (iovar_len == 0) {
++		DHD_ERROR(("%s: insufficient buffer space passed to bcm_mkiovar for '%s' \n",
++		           __FUNCTION__, iovar));
++		return BCME_BUFTOOSHORT;
++	}
++
++	err = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, iovar_buf,
++			iovar_len, IOV_SET, 0);
++
++	return err;
++}
++
++int
++dhd_download_clm_blob(dhd_pub_t	*dhd, unsigned char *buf, uint32 len)
++{
++	int chunk_len, cumulative_len = 0;
++	int size2alloc;
++	unsigned char *new_buf;
++	int err = 0, data_offset;
++	uint16 dl_flag = DL_BEGIN;
++
++	data_offset = OFFSETOF(wl_dload_data_t, data);
++	size2alloc = data_offset + MAX_CHUNK_LEN;
++
++	if ((new_buf = (unsigned char *)MALLOCZ(dhd->osh, size2alloc)) != NULL) {
++		do {
++			if (len >= MAX_CHUNK_LEN)
++				chunk_len = MAX_CHUNK_LEN;
++			else
++				chunk_len = len;
++
++			memcpy(new_buf + data_offset, buf + cumulative_len, chunk_len);
++			cumulative_len += chunk_len;
++
++			if (len - chunk_len == 0)
++				dl_flag |= DL_END;
++
++			err = dhd_download_2_dongle(dhd, "clmload", dl_flag, DL_TYPE_CLM,
++				new_buf, data_offset + chunk_len);
++
++			dl_flag &= ~DL_BEGIN;
++
++			len = len - chunk_len;
++		} while ((len > 0) && (err == 0));
++
++		MFREE(dhd->osh, new_buf, size2alloc);
++	} else {
++		err = BCME_NOMEM;
++	}
++
++	return err;
++}
++
++int
++dhd_apply_default_clm(dhd_pub_t *dhd, char *clm_path)
++{
++	char *clm_blob_path;
++	int len;
++	char *memblock = NULL;
++	int err = BCME_OK;
++	char iovbuf[WLC_IOCTL_SMLEN];
++	wl_country_t *cspec;
++
++	if (clm_path[0] != '\0') {
++		if (strlen(clm_path) > MOD_PARAM_PATHLEN) {
++			DHD_ERROR(("clm path exceeds max len\n"));
++			return BCME_ERROR;
++		}
++		clm_blob_path = clm_path;
++		DHD_ERROR(("clm path from module param:%s\n", clm_path));
++	} else {
++		clm_blob_path = CONFIG_BCMDHD_CLM_PATH;
++	}
++
++
++	/* If CLM blob file is found on the filesystem, download the file.
++	 * After CLM file download or If the blob file is not present,
++	 * validate the country code before proceeding with the initialization.
++	 * If country code is not valid, fail the initialization.
++	 */
++	len = MAX_CLM_BUF_SIZE;
++	dhd_get_download_buffer(dhd, clm_blob_path, CLM_BLOB, &memblock, &len);
++	if ((len > 0) && (len < MAX_CLM_BUF_SIZE) && memblock) {
++		/* Found blob file. Download the file */
++		DHD_ERROR(("clm file download from %s \n", clm_blob_path));
++		err = dhd_download_clm_blob(dhd, memblock, len);
++		if (err) {
++			DHD_ERROR(("%s: CLM download failed err=%d\n", __FUNCTION__, err));
++			/* Retrieve clmload_status and print */
++			bcm_mkiovar("clmload_status", NULL, 0, iovbuf, sizeof(iovbuf));
++			err = dhd_wl_ioctl_cmd(dhd, WLC_GET_VAR, iovbuf, sizeof(iovbuf), FALSE, 0);
++			if (err) {
++				DHD_ERROR(("%s: clmload_status get failed err=%d \n",
++					__FUNCTION__, err));
++			} else {
++				DHD_ERROR(("%s: clmload_status: %d \n",
++					__FUNCTION__, *((int *)iovbuf)));
++			}
++			err = BCME_ERROR;
++			goto exit;
++		} else {
++			DHD_INFO(("%s: CLM download succeeded \n", __FUNCTION__));
++		}
++	} else {
++		DHD_INFO(("Skipping the clm download. len:%d memblk:%p \n", len, memblock));
++	}
++
++	/* Verify country code */
++	bcm_mkiovar("country", NULL, 0, iovbuf, sizeof(iovbuf));
++	err = dhd_wl_ioctl_cmd(dhd, WLC_GET_VAR, iovbuf, sizeof(iovbuf), FALSE, 0);
++	if (err) {
++		DHD_ERROR(("%s: country code get failed\n", __FUNCTION__));
++		goto exit;
++	}
++
++	cspec = (wl_country_t *)iovbuf;
++	if ((strncmp(cspec->ccode, WL_CCODE_NULL_COUNTRY, WLC_CNTRY_BUF_SZ)) == 0) {
++		/* Country code not initialized or CLM download not proper */
++		DHD_ERROR(("country code not initialized\n"));
++		err = BCME_ERROR;
++	}
++exit:
++
++	if (memblock) {
++		dhd_free_download_buffer(dhd, memblock, MAX_CLM_BUF_SIZE);
++	}
++
++	return err;
++}
++
++void dhd_free_download_buffer(dhd_pub_t	*dhd, void *buffer, int length)
++{
++#ifdef CACHE_FW_IMAGES
++	return;
++#endif
++	MFREE(dhd->osh, buffer, length);
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_custom_gpio.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_custom_gpio.c
+new file mode 100644
+index 000000000..6f99bd505
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_custom_gpio.c
+@@ -0,0 +1,436 @@
++/*
++ * Customer code to add GPIO control during WLAN start/stop
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_custom_gpio.c 586390 2015-09-15 10:34:19Z $
++ */
++
++#include <typedefs.h>
++#include <linuxver.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_linux.h>
++#include <linux/gpio.h>
++
++#include <wlioctl.h>
++#if defined(WL_WIRELESS_EXT)
++#include <wl_iw.h>
++#endif
++
++#define WL_ERROR(x) printf x
++#define WL_TRACE(x)
++
++#if defined(CUSTOMER_HW2)
++
++
++#endif 
++
++#if defined(OOB_INTR_ONLY)
++
++#if defined(BCMLXSDMMC)
++extern int sdioh_mmc_irq(int irq);
++#endif /* (BCMLXSDMMC)  */
++
++#if defined(CUSTOMER_HW3)
++#include <mach/gpio.h>
++#endif
++
++/* Customer specific Host GPIO defintion  */
++static int dhd_oob_gpio_num = -1;
++
++module_param(dhd_oob_gpio_num, int, 0644);
++MODULE_PARM_DESC(dhd_oob_gpio_num, "DHD oob gpio number");
++
++/* This function will return:
++ *  1) return :  Host gpio interrupt number per customer platform
++ *  2) irq_flags_ptr : Type of Host interrupt as Level or Edge
++ *
++ *  NOTE :
++ *  Customer should check his platform definitions
++ *  and his Host Interrupt spec
++ *  to figure out the proper setting for his platform.
++ *  Broadcom provides just reference settings as example.
++ *
++ */
++int dhd_customer_oob_irq_map(void *adapter, unsigned long *irq_flags_ptr)
++{
++	int  host_oob_irq = 0;
++
++#if defined(CUSTOMER_HW2)
++	host_oob_irq = wifi_platform_get_irq_number(adapter, irq_flags_ptr);
++
++#else
++#if defined(CUSTOM_OOB_GPIO_NUM)
++	if (dhd_oob_gpio_num < 0) {
++		dhd_oob_gpio_num = CUSTOM_OOB_GPIO_NUM;
++	}
++#endif /* CUSTOMER_OOB_GPIO_NUM */
++
++	if (dhd_oob_gpio_num < 0) {
++		WL_ERROR(("%s: ERROR customer specific Host GPIO is NOT defined \n",
++		__FUNCTION__));
++		return (dhd_oob_gpio_num);
++	}
++
++	WL_ERROR(("%s: customer specific Host GPIO number is (%d)\n",
++	         __FUNCTION__, dhd_oob_gpio_num));
++
++#if defined CUSTOMER_HW3
++	gpio_request(dhd_oob_gpio_num, "oob irq");
++	host_oob_irq = gpio_to_irq(dhd_oob_gpio_num);
++	gpio_direction_input(dhd_oob_gpio_num);
++#endif 
++#endif 
++
++	return (host_oob_irq);
++}
++#endif 
++
++/* Customer function to control hw specific wlan gpios */
++//int
++//dhd_customer_gpio_wlan_ctrl(void *adapter, int onoff)
++//{
++//	int err = 0;
++//
++//	return err;
++//}
++
++extern int ingenic_sdio_wlan_power_onoff(int onoff, int flag);
++#define RESET  0
++#define NORMAL 1
++
++static int poweroff_num = 0;
++static int poweron_num = 0;
++
++int dhd_customer_gpio_wlan_ctrl(void *adapter, int onoff)
++{
++	switch (onoff) {
++	case 0:
++		if(poweroff_num){
++			WL_ERROR(("=========== WLAN placed in RESET OFF========\n"));
++			ingenic_sdio_wlan_power_onoff(onoff, RESET);
++		}else{
++			WL_ERROR(("=========== WLAN placed in NOMAL OFF ========\n"));
++			poweroff_num = 1;
++			ingenic_sdio_wlan_power_onoff(onoff, NORMAL);
++		}
++		mdelay(100);
++		break;
++	case 1:
++		if(poweron_num){
++			WL_ERROR(("=========== WLAN placed in RESET ON  ========\n"));
++			ingenic_sdio_wlan_power_onoff(onoff, RESET);
++		}else{
++			WL_ERROR(("=========== WLAN placed in NOMAL ON========\n"));
++			poweron_num = 1;
++			ingenic_sdio_wlan_power_onoff(onoff, NORMAL);
++		}
++		break;
++	}
++	return 0;
++}
++//=========================== add for OOB ===========================//
++
++struct resource dhd_wlan_resources[] = {
++	[0] = {
++		.name	= "bcmdhd_wlan_irq",
++		.start	= 0, /* Dummy */
++		.end	= 0, /* Dummy */
++		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE
++			| IORESOURCE_IRQ_HIGHLEVEL, /* Dummy */
++	},
++};
++
++#ifdef CUSTOMER_OOB
++extern int ingenic_sdio_wlan_get_irq(unsigned long *flag);
++static int gpio_wl_host_wake = -1; // WL_HOST_WAKE is output pin of WLAN module
++
++int dhd_init_gpio_wlan_hostwake(void)
++{
++	int err = 0;
++	int host_oob_irq = -1;
++	uint host_oob_irq_flags = 0;
++
++	gpio_wl_host_wake = -1;
++	gpio_wl_host_wake = ingenic_sdio_wlan_get_irq((unsigned long *)&host_oob_irq_flags);
++
++	if (gpio_wl_host_wake >= 0) {
++		err = gpio_request(gpio_wl_host_wake, "bcmdhd");
++		if (err < 0) {
++			printf("%s: gpio_request(%d) for WL_HOST_WAKE failed\n",
++				__FUNCTION__, gpio_wl_host_wake);
++			return -1;
++		}
++		err = gpio_direction_input(gpio_wl_host_wake);
++		if (err < 0) {
++			printf("%s: gpio_direction_input(%d) for WL_HOST_WAKE failed\n",
++				__FUNCTION__, gpio_wl_host_wake);
++			gpio_free(gpio_wl_host_wake);
++			return -1;
++		}
++		host_oob_irq = gpio_to_irq(gpio_wl_host_wake);
++		if (host_oob_irq < 0) {
++			printf("%s: gpio_to_irq(%d) for WL_HOST_WAKE failed\n",
++				__FUNCTION__, gpio_wl_host_wake);
++			gpio_free(gpio_wl_host_wake);
++			return -1;
++		}
++	}
++
++#ifdef HW_OOB
++#ifdef HW_OOB_LOW_LEVEL
++	host_oob_irq_flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL | IORESOURCE_IRQ_SHAREABLE;
++#else
++	host_oob_irq_flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL | IORESOURCE_IRQ_SHAREABLE;
++#endif
++#else
++	host_oob_irq_flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_SHAREABLE;
++#endif
++
++	dhd_wlan_resources[0].start = dhd_wlan_resources[0].end = host_oob_irq;
++	dhd_wlan_resources[0].flags = host_oob_irq_flags;
++	printf("%s: WL_HOST_WAKE=%d, oob_irq=%d, oob_irq_flags=0x%x\n", __FUNCTION__,
++		gpio_wl_host_wake, host_oob_irq, host_oob_irq_flags);
++
++	return 0;
++}
++
++//static void dhd_deinit_gpio_wlan_hostwake(void)
++void dhd_deinit_gpio_wlan_hostwake(void)
++{
++	if (gpio_wl_host_wake >= 0) {
++		printf("%s: gpio_free(WL_HOST_WAKE %d)\n", __FUNCTION__, gpio_wl_host_wake);
++		gpio_free(gpio_wl_host_wake);
++		gpio_wl_host_wake = -1;
++	}
++}
++#endif
++//=========================== add for OOB ===========================//
++
++#ifdef GET_CUSTOM_MAC_ENABLE
++/* Function to get custom MAC address */
++int
++dhd_custom_get_mac_address(void *adapter, unsigned char *buf)
++{
++	int ret = 0;
++
++	WL_TRACE(("%s Enter\n", __FUNCTION__));
++	if (!buf)
++		return -EINVAL;
++
++	/* Customer access to MAC address stored outside of DHD driver */
++#if defined(CUSTOMER_HW2) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	ret = wifi_platform_get_mac_addr(adapter, buf);
++#endif
++
++#ifdef EXAMPLE_GET_MAC
++	/* EXAMPLE code */
++	{
++		struct ether_addr ea_example = {{0x00, 0x11, 0x22, 0x33, 0x44, 0xFF}};
++		bcopy((char *)&ea_example, buf, sizeof(struct ether_addr));
++	}
++#endif /* EXAMPLE_GET_MAC */
++
++	return ret;
++}
++#endif /* GET_CUSTOM_MAC_ENABLE */
++
++#if !defined(WL_WIRELESS_EXT)
++struct cntry_locales_custom {
++	char iso_abbrev[WLC_CNTRY_BUF_SZ];	/* ISO 3166-1 country abbreviation */
++	char custom_locale[WLC_CNTRY_BUF_SZ];	/* Custom firmware locale */
++	int32 custom_locale_rev;		/* Custom local revisin default -1 */
++};
++#endif /* WL_WIRELESS_EXT */
++
++/* Customized Locale table : OPTIONAL feature */
++const struct cntry_locales_custom translate_custom_table[] = {
++/* Table should be filled out based on custom platform regulatory requirement */
++#ifdef EXAMPLE_TABLE
++	{"",   "XY", 4},  /* Universal if Country code is unknown or empty */
++	{"US", "US", 69}, /* input ISO "US" to : US regrev 69 */
++	{"CA", "US", 69}, /* input ISO "CA" to : US regrev 69 */
++	{"EU", "EU", 5},  /* European union countries to : EU regrev 05 */
++	{"AT", "EU", 5},
++	{"BE", "EU", 5},
++	{"BG", "EU", 5},
++	{"CY", "EU", 5},
++	{"CZ", "EU", 5},
++	{"DK", "EU", 5},
++	{"EE", "EU", 5},
++	{"FI", "EU", 5},
++	{"FR", "EU", 5},
++	{"DE", "EU", 5},
++	{"GR", "EU", 5},
++	{"HU", "EU", 5},
++	{"IE", "EU", 5},
++	{"IT", "EU", 5},
++	{"LV", "EU", 5},
++	{"LI", "EU", 5},
++	{"LT", "EU", 5},
++	{"LU", "EU", 5},
++	{"MT", "EU", 5},
++	{"NL", "EU", 5},
++	{"PL", "EU", 5},
++	{"PT", "EU", 5},
++	{"RO", "EU", 5},
++	{"SK", "EU", 5},
++	{"SI", "EU", 5},
++	{"ES", "EU", 5},
++	{"SE", "EU", 5},
++	{"GB", "EU", 5},
++	{"KR", "XY", 3},
++	{"AU", "XY", 3},
++	{"CN", "XY", 3}, /* input ISO "CN" to : XY regrev 03 */
++	{"TW", "XY", 3},
++	{"AR", "XY", 3},
++	{"MX", "XY", 3},
++	{"IL", "IL", 0},
++	{"CH", "CH", 0},
++	{"TR", "TR", 0},
++	{"NO", "NO", 0},
++#endif /* EXMAPLE_TABLE */
++#if defined(CUSTOMER_HW2)
++#if defined(BCM4335_CHIP)
++	{"",   "XZ", 11},  /* Universal if Country code is unknown or empty */
++#endif
++	{"AE", "AE", 1},
++	{"AR", "AR", 1},
++	{"AT", "AT", 1},
++	{"AU", "AU", 2},
++	{"BE", "BE", 1},
++	{"BG", "BG", 1},
++	{"BN", "BN", 1},
++	{"CA", "CA", 2},
++	{"CH", "CH", 1},
++	{"CY", "CY", 1},
++	{"CZ", "CZ", 1},
++	{"DE", "DE", 3},
++	{"DK", "DK", 1},
++	{"EE", "EE", 1},
++	{"ES", "ES", 1},
++	{"FI", "FI", 1},
++	{"FR", "FR", 1},
++	{"GB", "GB", 1},
++	{"GR", "GR", 1},
++	{"HR", "HR", 1},
++	{"HU", "HU", 1},
++	{"IE", "IE", 1},
++	{"IS", "IS", 1},
++	{"IT", "IT", 1},
++	{"ID", "ID", 1},
++	{"JP", "JP", 8},
++	{"KR", "KR", 24},
++	{"KW", "KW", 1},
++	{"LI", "LI", 1},
++	{"LT", "LT", 1},
++	{"LU", "LU", 1},
++	{"LV", "LV", 1},
++	{"MA", "MA", 1},
++	{"MT", "MT", 1},
++	{"MX", "MX", 1},
++	{"NL", "NL", 1},
++	{"NO", "NO", 1},
++	{"PL", "PL", 1},
++	{"PT", "PT", 1},
++	{"PY", "PY", 1},
++	{"RO", "RO", 1},
++	{"SE", "SE", 1},
++	{"SI", "SI", 1},
++	{"SK", "SK", 1},
++	{"TR", "TR", 7},
++	{"TW", "TW", 1},
++	{"IR", "XZ", 11},	/* Universal if Country code is IRAN, (ISLAMIC REPUBLIC OF) */
++	{"SD", "XZ", 11},	/* Universal if Country code is SUDAN */
++	{"SY", "XZ", 11},	/* Universal if Country code is SYRIAN ARAB REPUBLIC */
++	{"GL", "XZ", 11},	/* Universal if Country code is GREENLAND */
++	{"PS", "XZ", 11},	/* Universal if Country code is PALESTINIAN TERRITORY, OCCUPIED */
++	{"TL", "XZ", 11},	/* Universal if Country code is TIMOR-LESTE (EAST TIMOR) */
++	{"MH", "XZ", 11},	/* Universal if Country code is MARSHALL ISLANDS */
++#ifdef BCM4330_CHIP
++	{"RU", "RU", 1},
++	{"US", "US", 5}
++#endif
++#endif 
++};
++
++
++/* Customized Locale convertor
++*  input : ISO 3166-1 country abbreviation
++*  output: customized cspec
++*/
++#ifdef CUSTOM_COUNTRY_CODE
++void get_customized_country_code(void *adapter, char *country_iso_code,
++  wl_country_t *cspec, u32 flags)
++#else
++void get_customized_country_code(void *adapter, char *country_iso_code, wl_country_t *cspec)
++#endif /* CUSTOM_COUNTRY_CODE */
++{
++#if defined(CUSTOMER_HW2) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39))
++
++	struct cntry_locales_custom *cloc_ptr;
++
++	if (!cspec)
++		return;
++#ifdef CUSTOM_COUNTRY_CODE
++	cloc_ptr = wifi_platform_get_country_code(adapter, country_iso_code,
++	           flags);
++#else
++	cloc_ptr = wifi_platform_get_country_code(adapter, country_iso_code);
++#endif /* CUSTOM_COUNTRY_CODE */
++	if (cloc_ptr) {
++		strlcpy(cspec->ccode, cloc_ptr->custom_locale, WLC_CNTRY_BUF_SZ);
++		cspec->rev = cloc_ptr->custom_locale_rev;
++	}
++	return;
++#else
++	int size, i;
++
++	size = ARRAYSIZE(translate_custom_table);
++
++	if (cspec == 0)
++		 return;
++
++	if (size == 0)
++		 return;
++
++	for (i = 0; i < size; i++) {
++		if (strcmp(country_iso_code, translate_custom_table[i].iso_abbrev) == 0) {
++			memcpy(cspec->ccode,
++				translate_custom_table[i].custom_locale, WLC_CNTRY_BUF_SZ);
++			cspec->rev = translate_custom_table[i].custom_locale_rev;
++			return;
++		}
++	}
++#ifdef EXAMPLE_TABLE
++	/* if no country code matched return first universal code from translate_custom_table */
++	memcpy(cspec->ccode, translate_custom_table[0].custom_locale, WLC_CNTRY_BUF_SZ);
++	cspec->rev = translate_custom_table[0].custom_locale_rev;
++#endif /* EXMAPLE_TABLE */
++	return;
++#endif /* defined(CUSTOMER_HW2) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) */
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_dbg.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_dbg.h
+new file mode 100644
+index 000000000..7673a5a30
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_dbg.h
+@@ -0,0 +1,146 @@
++/*
++ * Debug/trace/assert driver definitions for Dongle Host Driver.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_dbg.h 586164 2015-09-14 18:09:12Z $
++ */
++
++#ifndef _dhd_dbg_
++#define _dhd_dbg_
++
++#define USE_NET_RATELIMIT		1
++
++#if defined(DHD_DEBUG)
++
++#define DHD_ERROR(args)		do {if ((dhd_msg_level & DHD_ERROR_VAL) && USE_NET_RATELIMIT) \
++								printf args;} while (0)
++#define DHD_TRACE(args)		do {if (dhd_msg_level & DHD_TRACE_VAL) printf args;} while (0)
++#define DHD_INFO(args)		do {if (dhd_msg_level & DHD_INFO_VAL) printf args;} while (0)
++#define DHD_DATA(args)		do {if (dhd_msg_level & DHD_DATA_VAL) printf args;} while (0)
++#define DHD_CTL(args)		do {if (dhd_msg_level & DHD_CTL_VAL) printf args;} while (0)
++#define DHD_TIMER(args)		do {if (dhd_msg_level & DHD_TIMER_VAL) printf args;} while (0)
++#define DHD_HDRS(args)		do {if (dhd_msg_level & DHD_HDRS_VAL) printf args;} while (0)
++#define DHD_BYTES(args)		do {if (dhd_msg_level & DHD_BYTES_VAL) printf args;} while (0)
++#define DHD_INTR(args)		do {if (dhd_msg_level & DHD_INTR_VAL) printf args;} while (0)
++#define DHD_GLOM(args)		do {if (dhd_msg_level & DHD_GLOM_VAL) printf args;} while (0)
++#define DHD_EVENT(args)		do {if (dhd_msg_level & DHD_EVENT_VAL) printf args;} while (0)
++#define DHD_BTA(args)		do {if (dhd_msg_level & DHD_BTA_VAL) printf args;} while (0)
++#define DHD_ISCAN(args)		do {if (dhd_msg_level & DHD_ISCAN_VAL) printf args;} while (0)
++#define DHD_ARPOE(args)		do {if (dhd_msg_level & DHD_ARPOE_VAL) printf args;} while (0)
++#define DHD_REORDER(args)	do {if (dhd_msg_level & DHD_REORDER_VAL) printf args;} while (0)
++#define DHD_PNO(args)		do {if (dhd_msg_level & DHD_PNO_VAL) printf args;} while (0)
++#define DHD_MSGTRACE_LOG(args)  do {if (dhd_msg_level & DHD_MSGTRACE_VAL) printf args;} while (0)
++#define DHD_FWLOG(args)		do {if (dhd_msg_level & DHD_FWLOG_VAL) printf args;} while (0)
++#define DHD_RTT(args)		do {if (dhd_msg_level & DHD_RTT_VAL) printf args;} while (0)
++#define DHD_DBGIF(args)		do {if (dhd_msg_level & DHD_DBGIF_VAL) printf args;} while (0)
++
++/* To dump MAC registers in case of fatal errors */
++#define DHD_DUMP	DHD_ERROR
++
++#define DHD_TRACE_HW4	DHD_TRACE
++#define DHD_INFO_HW4	DHD_INFO
++
++#define DHD_ERROR_ON()		(dhd_msg_level & DHD_ERROR_VAL)
++#define DHD_TRACE_ON()		(dhd_msg_level & DHD_TRACE_VAL)
++#define DHD_INFO_ON()		(dhd_msg_level & DHD_INFO_VAL)
++#define DHD_DATA_ON()		(dhd_msg_level & DHD_DATA_VAL)
++#define DHD_CTL_ON()		(dhd_msg_level & DHD_CTL_VAL)
++#define DHD_TIMER_ON()		(dhd_msg_level & DHD_TIMER_VAL)
++#define DHD_HDRS_ON()		(dhd_msg_level & DHD_HDRS_VAL)
++#define DHD_BYTES_ON()		(dhd_msg_level & DHD_BYTES_VAL)
++#define DHD_INTR_ON()		(dhd_msg_level & DHD_INTR_VAL)
++#define DHD_GLOM_ON()		(dhd_msg_level & DHD_GLOM_VAL)
++#define DHD_EVENT_ON()		(dhd_msg_level & DHD_EVENT_VAL)
++#define DHD_BTA_ON()		(dhd_msg_level & DHD_BTA_VAL)
++#define DHD_ISCAN_ON()		(dhd_msg_level & DHD_ISCAN_VAL)
++#define DHD_ARPOE_ON()		(dhd_msg_level & DHD_ARPOE_VAL)
++#define DHD_REORDER_ON()	(dhd_msg_level & DHD_REORDER_VAL)
++#define DHD_NOCHECKDIED_ON()	(dhd_msg_level & DHD_NOCHECKDIED_VAL)
++#define DHD_PNO_ON()		(dhd_msg_level & DHD_PNO_VAL)
++#define DHD_FWLOG_ON()		(dhd_msg_level & DHD_FWLOG_VAL)
++#define DHD_DBGIF_ON()		(dhd_msg_level & DHD_DBGIF_VAL)
++#define DHD_RTT_ON()		(dhd_msg_level & DHD_RTT_VAL)
++#define DHD_DBG_BCNRX_ON()	(dhd_msg_level & DHD_DBG_BCNRX_VAL)
++
++#else /* defined(BCMDBG) || defined(DHD_DEBUG) */
++
++#define DHD_ERROR(args)		do {if (USE_NET_RATELIMIT) printf args;} while (0)
++#define DHD_TRACE(args)
++#define DHD_INFO(args)
++#define DHD_DATA(args)
++#define DHD_CTL(args)
++#define DHD_TIMER(args)
++#define DHD_HDRS(args)
++#define DHD_BYTES(args)
++#define DHD_INTR(args)
++#define DHD_GLOM(args)
++#define DHD_EVENT(args)
++#define DHD_BTA(args)
++#define DHD_ISCAN(args)
++#define DHD_ARPOE(args)
++#define DHD_REORDER(args)
++#define DHD_PNO(args)
++#define DHD_MSGTRACE_LOG(args)
++#define DHD_FWLOG(args)
++#define DHD_RTT(args)
++#define DHD_DBGIF(args)
++
++#define DHD_TRACE_HW4	DHD_TRACE
++#define DHD_INFO_HW4	DHD_INFO
++
++#define DHD_ERROR_ON()		0
++#define DHD_TRACE_ON()		0
++#define DHD_INFO_ON()		0
++#define DHD_DATA_ON()		0
++#define DHD_CTL_ON()		0
++#define DHD_TIMER_ON()		0
++#define DHD_HDRS_ON()		0
++#define DHD_BYTES_ON()		0
++#define DHD_INTR_ON()		0
++#define DHD_GLOM_ON()		0
++#define DHD_EVENT_ON()		0
++#define DHD_BTA_ON()		0
++#define DHD_ISCAN_ON()		0
++#define DHD_ARPOE_ON()		0
++#define DHD_REORDER_ON()	0
++#define DHD_NOCHECKDIED_ON()	0
++#define DHD_PNO_ON()		0
++#define DHD_FWLOG_ON()		0
++#define DHD_DBGIF_ON()		0
++#define DHD_RTT_ON()		0
++#define DHD_DBG_BCNRX_ON()	0
++#endif 
++
++#define DHD_LOG(args)
++
++#define DHD_BLOG(cp, size)
++
++#define DHD_NONE(args)
++extern int dhd_msg_level;
++
++/* Defines msg bits */
++#include <dhdioctl.h>
++
++#endif /* _dhd_dbg_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_debug.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_debug.c
+new file mode 100644
+index 000000000..8117cd48c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_debug.c
+@@ -0,0 +1,1297 @@
++/*
++ * DHD debugability support
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * $Id: dhd_debug.c 560028 2015-05-29 10:50:33Z $
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_dbg.h>
++#include <dhd_debug.h>
++
++#include <event_log.h>
++#include <event_trace.h>
++#include <msgtrace.h>
++
++#define DBGRING_FLUSH_THRESHOLD(ring)		(ring->ring_size / 3)
++#define RING_STAT_TO_STATUS(ring, status) \
++	do {               \
++		strncpy(status.name, ring->name, \
++			sizeof(status.name) - 1);  \
++		status.ring_id = ring->id;     \
++		status.ring_buffer_byte_size = ring->ring_size;  \
++		status.written_bytes = ring->stat.written_bytes; \
++		status.written_records = ring->stat.written_records; \
++		status.read_bytes = ring->stat.read_bytes; \
++		status.verbose_level = ring->log_level; \
++	} while (0)
++
++#define READ_AVAIL_SPACE(w, r, d)	((w >= r) ? (w - r) : (d - r))
++
++struct map_table {
++	uint16 fw_id;
++	uint16 host_id;
++	char *desc;
++};
++
++struct map_table event_map[] = {
++	{WLC_E_AUTH, WIFI_EVENT_AUTH_COMPLETE, "AUTH_COMPLETE"},
++	{WLC_E_ASSOC, WIFI_EVENT_ASSOC_COMPLETE, "ASSOC_COMPLETE"},
++	{TRACE_FW_AUTH_STARTED, WIFI_EVENT_FW_AUTH_STARTED, "AUTH STARTED"},
++	{TRACE_FW_ASSOC_STARTED, WIFI_EVENT_FW_ASSOC_STARTED, "ASSOC STARTED"},
++	{TRACE_FW_RE_ASSOC_STARTED, WIFI_EVENT_FW_RE_ASSOC_STARTED, "REASSOC STARTED"},
++	{TRACE_G_SCAN_STARTED, WIFI_EVENT_G_SCAN_STARTED, "GSCAN STARTED"},
++	{WLC_E_PFN_SCAN_COMPLETE, WIFI_EVENT_G_SCAN_COMPLETE, "GSCAN COMPLETE"},
++	{WLC_E_DISASSOC, WIFI_EVENT_DISASSOCIATION_REQUESTED, "DIASSOC REQUESTED"},
++	{WLC_E_REASSOC, WIFI_EVENT_RE_ASSOCIATION_REQUESTED, "REASSOC REQUESTED"},
++	{TRACE_ROAM_SCAN_STARTED, WIFI_EVENT_ROAM_REQUESTED, "ROAM REQUESTED"},
++	{WLC_E_BEACON_FRAME_RX, WIFI_EVENT_BEACON_RECEIVED, "BEACON Received"},
++	{TRACE_ROAM_SCAN_STARTED, WIFI_EVENT_ROAM_SCAN_STARTED, "ROAM SCAN STARTED"},
++	{TRACE_ROAM_SCAN_COMPLETE, WIFI_EVENT_ROAM_SCAN_COMPLETE, "ROAM SCAN COMPLETED"},
++	{TRACE_ROAM_AUTH_STARTED, WIFI_EVENT_ROAM_AUTH_STARTED, "ROAM AUTH STARTED"},
++	{WLC_E_AUTH, WIFI_EVENT_ROAM_AUTH_COMPLETE, "ROAM AUTH COMPLETED"},
++	{TRACE_FW_RE_ASSOC_STARTED, WIFI_EVENT_ROAM_ASSOC_STARTED, "ROAM ASSOC STARTED"},
++	{WLC_E_ASSOC, WIFI_EVENT_ROAM_ASSOC_COMPLETE, "ROAM ASSOC COMPLETED"},
++	{TRACE_ROAM_SCAN_COMPLETE, WIFI_EVENT_ROAM_SCAN_COMPLETE, "ROAM SCAN COMPLETED"},
++	{TRACE_BT_COEX_BT_SCO_START, WIFI_EVENT_BT_COEX_BT_SCO_START, "BT SCO START"},
++	{TRACE_BT_COEX_BT_SCO_STOP, WIFI_EVENT_BT_COEX_BT_SCO_STOP, "BT SCO STOP"},
++	{TRACE_BT_COEX_BT_SCAN_START, WIFI_EVENT_BT_COEX_BT_SCAN_START, "BT COEX SCAN START"},
++	{TRACE_BT_COEX_BT_SCAN_STOP, WIFI_EVENT_BT_COEX_BT_SCAN_STOP, "BT COEX SCAN STOP"},
++	{TRACE_BT_COEX_BT_HID_START, WIFI_EVENT_BT_COEX_BT_HID_START, "BT HID START"},
++	{TRACE_BT_COEX_BT_HID_STOP, WIFI_EVENT_BT_COEX_BT_HID_STOP, "BT HID STOP"},
++	{WLC_E_EAPOL_MSG, WIFI_EVENT_FW_EAPOL_FRAME_RECEIVED, "FW EAPOL PKT RECEIVED"},
++	{TRACE_FW_EAPOL_FRAME_TRANSMIT_START, WIFI_EVENT_FW_EAPOL_FRAME_TRANSMIT_START,
++	"FW EAPOL PKT TRANSMITED"},
++	{TRACE_FW_EAPOL_FRAME_TRANSMIT_STOP, WIFI_EVENT_FW_EAPOL_FRAME_TRANSMIT_STOP,
++	"FW EAPOL PKT TX STOPPED"},
++	{TRACE_BLOCK_ACK_NEGOTIATION_COMPLETE, WIFI_EVENT_BLOCK_ACK_NEGOTIATION_COMPLETE,
++	"BLOCK ACK NEGO COMPLETED"},
++};
++
++struct map_table event_tag_map[] = {
++	{TRACE_TAG_VENDOR_SPECIFIC, WIFI_TAG_VENDOR_SPECIFIC, "VENDOR SPECIFIC DATA"},
++	{TRACE_TAG_BSSID, WIFI_TAG_BSSID, "BSSID"},
++	{TRACE_TAG_ADDR, WIFI_TAG_ADDR, "ADDR_0"},
++	{TRACE_TAG_SSID, WIFI_TAG_SSID, "SSID"},
++	{TRACE_TAG_STATUS, WIFI_TAG_STATUS, "STATUS"},
++	{TRACE_TAG_CHANNEL_SPEC, WIFI_TAG_CHANNEL_SPEC, "CHANSPEC"},
++	{TRACE_TAG_WAKE_LOCK_EVENT, WIFI_TAG_WAKE_LOCK_EVENT, "WAKELOCK EVENT"},
++	{TRACE_TAG_ADDR1, WIFI_TAG_ADDR1, "ADDR_1"},
++	{TRACE_TAG_ADDR2, WIFI_TAG_ADDR2, "ADDR_2"},
++	{TRACE_TAG_ADDR3, WIFI_TAG_ADDR3, "ADDR_3"},
++	{TRACE_TAG_ADDR4, WIFI_TAG_ADDR4, "ADDR_4"},
++	{TRACE_TAG_TSF, WIFI_TAG_TSF, "TSF"},
++	{TRACE_TAG_IE, WIFI_TAG_IE, "802.11 IE"},
++	{TRACE_TAG_INTERFACE, WIFI_TAG_INTERFACE, "INTERFACE"},
++	{TRACE_TAG_REASON_CODE, WIFI_TAG_REASON_CODE, "REASON CODE"},
++	{TRACE_TAG_RATE_MBPS, WIFI_TAG_RATE_MBPS, "RATE"},
++};
++
++/* define log level per ring type */
++struct log_level_table fw_verbose_level_map[] = {
++	{1, EVENT_LOG_TAG_PCI_ERROR, "PCI_ERROR"},
++	{1, EVENT_LOG_TAG_PCI_WARN, "PCI_WARN"},
++	{2, EVENT_LOG_TAG_PCI_INFO, "PCI_INFO"},
++	{3, EVENT_LOG_TAG_PCI_DBG, "PCI_DEBUG"},
++	{3, EVENT_LOG_TAG_BEACON_LOG, "BEACON_LOG"},
++	{2, EVENT_LOG_TAG_WL_ASSOC_LOG, "ASSOC_LOG"},
++	{2, EVENT_LOG_TAG_WL_ROAM_LOG, "ROAM_LOG"},
++	{1, EVENT_LOG_TAG_TRACE_WL_INFO, "WL INFO"},
++	{1, EVENT_LOG_TAG_TRACE_BTCOEX_INFO, "BTCOEX INFO"},
++	{1, EVENT_LOG_TAG_SCAN_WARN, "SCAN_WARN"},
++	{1, EVENT_LOG_TAG_SCAN_ERROR, "SCAN_ERROR"},
++	{2, EVENT_LOG_TAG_SCAN_TRACE_LOW, "SCAN_TRACE_LOW"},
++	{2, EVENT_LOG_TAG_SCAN_TRACE_HIGH, "SCAN_TRACE_HIGH"}
++};
++
++struct log_level_table fw_event_level_map[] = {
++	{1, EVENT_LOG_TAG_TRACE_WL_INFO, "WL_INFO"},
++	{1, EVENT_LOG_TAG_TRACE_BTCOEX_INFO, "BTCOEX_INFO"},
++	{2, EVENT_LOG_TAG_BEACON_LOG, "BEACON LOG"},
++};
++
++struct map_table nan_event_map[] = {
++	{TRACE_NAN_CLUSTER_STARTED, NAN_EVENT_CLUSTER_STARTED, "NAN_CLUSTER_STARTED"},
++	{TRACE_NAN_CLUSTER_JOINED, NAN_EVENT_CLUSTER_JOINED, "NAN_CLUSTER_JOINED"},
++	{TRACE_NAN_CLUSTER_MERGED, NAN_EVENT_CLUSTER_MERGED, "NAN_CLUSTER_MERGED"},
++	{TRACE_NAN_ROLE_CHANGED, NAN_EVENT_ROLE_CHANGED, "NAN_ROLE_CHANGED"},
++	{TRACE_NAN_SCAN_COMPLETE, NAN_EVENT_SCAN_COMPLETE, "NAN_SCAN_COMPLETE"},
++	{TRACE_NAN_STATUS_CHNG, NAN_EVENT_STATUS_CHNG, "NAN_STATUS_CHNG"},
++};
++
++struct log_level_table nan_event_level_map[] = {
++	{1, EVENT_LOG_TAG_NAN_ERROR, "NAN_ERROR"},
++	{2, EVENT_LOG_TAG_NAN_INFO, "NAN_INFO"},
++	{3, EVENT_LOG_TAG_NAN_DBG, "NAN_DEBUG"},
++};
++
++struct map_table nan_evt_tag_map[] = {
++	{TRACE_TAG_BSSID, WIFI_TAG_BSSID, "BSSID"},
++	{TRACE_TAG_ADDR, WIFI_TAG_ADDR, "ADDR_0"},
++};
++
++/* reference tab table */
++uint ref_tag_tbl[EVENT_LOG_TAG_MAX + 1] = {0};
++
++enum dbg_ring_state {
++	RING_STOP	= 0,	/* ring is not initialized */
++	RING_ACTIVE,	/* ring is live and logging */
++	RING_SUSPEND	/* ring is initialized but not logging */
++};
++
++struct ring_statistics {
++	/* number of bytes that was written to the buffer by driver */
++	uint32 written_bytes;
++	/* number of bytes that was read from the buffer by user land */
++	uint32 read_bytes;
++	/* number of records that was written to the buffer by driver */
++	uint32 written_records;
++};
++
++typedef struct dhd_dbg_ring {
++	int	id;		/* ring id */
++	uint8	name[DBGRING_NAME_MAX];	/* name string */
++	uint32	ring_size;	/* numbers of item in ring */
++	uint32	wp;		/* write pointer */
++	uint32	rp;		/* read pointer */
++	uint32  log_level; /* log_level */
++	uint32	threshold; /* threshold bytes */
++	void *	ring_buf;	/* pointer of actually ring buffer */
++	void *	lock;		/* spin lock for ring access */
++	struct ring_statistics stat; /* statistics */
++	enum dbg_ring_state state;	/* ring state enum */
++} dhd_dbg_ring_t;
++
++typedef struct dhd_dbg {
++	dhd_dbg_ring_t dbg_rings[DEBUG_RING_ID_MAX];
++	void *private;		/* os private_data */
++	dbg_pullreq_t pullreq;
++	dbg_urgent_noti_t urgent_notifier;
++} dhd_dbg_t;
++
++typedef struct dhddbg_loglist_item {
++	dll_t list;
++	event_log_hdr_t *hdr;
++} loglist_item_t;
++
++typedef struct dhbdbg_pending_item {
++	dll_t list;
++	dhd_dbg_ring_status_t ring_status;
++	dhd_dbg_ring_entry_t *ring_entry;
++} pending_item_t;
++
++/* get next entry; offset must point to valid entry */
++static uint32
++next_entry(dhd_dbg_ring_t *ring, int32 offset)
++{
++	dhd_dbg_ring_entry_t *entry =
++		(dhd_dbg_ring_entry_t *)((uint8 *)ring->ring_buf + offset);
++
++	/*
++	 * A length == 0 record is the end of buffer marker. Wrap around and
++	 * read the message at the start of the buffer as *this* one, and
++	 * return the one after that.
++	 */
++	if (!entry->len) {
++		entry = (dhd_dbg_ring_entry_t *)ring->ring_buf;
++		return ENTRY_LENGTH(entry);
++	}
++	return offset + ENTRY_LENGTH(entry);
++}
++
++/* get record by offset; idx must point to valid entry */
++static dhd_dbg_ring_entry_t *
++get_entry(dhd_dbg_ring_t *ring, int32 offset)
++{
++	dhd_dbg_ring_entry_t *entry =
++		(dhd_dbg_ring_entry_t *)((uint8 *)ring->ring_buf + offset);
++
++	/*
++	 * A length == 0 record is the end of buffer marker. Wrap around and
++	 * read the message at the start of the buffer.
++	 */
++	if (!entry->len)
++		return (dhd_dbg_ring_entry_t *)ring->ring_buf;
++	return entry;
++}
++
++int
++dhd_dbg_ring_pull(dhd_pub_t *dhdp, int ring_id, void *data, uint32 buf_len)
++{
++	uint32 avail_len, r_len = 0;
++	unsigned long flags;
++	dhd_dbg_ring_t *ring;
++	dhd_dbg_ring_entry_t *hdr;
++
++	if (!dhdp || !dhdp->dbg)
++		return r_len;
++	ring = &dhdp->dbg->dbg_rings[ring_id];
++	if (ring->state != RING_ACTIVE)
++		return r_len;
++
++	flags = dhd_os_spin_lock(ring->lock);
++
++	/* get a fresh pending length */
++	avail_len = READ_AVAIL_SPACE(ring->wp, ring->rp, ring->ring_size);
++	while (avail_len > 0 && buf_len > 0) {
++		hdr = get_entry(ring, ring->rp);
++		memcpy(data, hdr, ENTRY_LENGTH(hdr));
++		r_len += ENTRY_LENGTH(hdr);
++		/* update read pointer */
++		ring->rp = next_entry(ring, ring->rp);
++		data = (uint8 *)data + ENTRY_LENGTH(hdr);
++		avail_len -= ENTRY_LENGTH(hdr);
++		buf_len -= ENTRY_LENGTH(hdr);
++		ring->stat.read_bytes += ENTRY_LENGTH(hdr);
++		DHD_DBGIF(("%s read_bytes  %d\n", __FUNCTION__,
++			ring->stat.read_bytes));
++	}
++	dhd_os_spin_unlock(ring->lock, flags);
++
++	return r_len;
++}
++
++int
++dhd_dbg_ring_push(dhd_pub_t *dhdp, int ring_id, dhd_dbg_ring_entry_t *hdr, void *data)
++{
++	unsigned long flags;
++	uint32 w_len;
++	dhd_dbg_ring_t *ring;
++	dhd_dbg_ring_entry_t *w_entry;
++	if (!dhdp || !dhdp->dbg)
++		return BCME_BADADDR;
++
++	ring = &dhdp->dbg->dbg_rings[ring_id];
++
++	if (ring->state != RING_ACTIVE)
++		return BCME_OK;
++
++	flags = dhd_os_spin_lock(ring->lock);
++
++	w_len = ENTRY_LENGTH(hdr);
++	/* prep the space */
++	do {
++		if (ring->rp == ring->wp)
++			break;
++		if (ring->rp < ring->wp) {
++			if (ring->ring_size - ring->wp == w_len) {
++				if (ring->rp == 0)
++					ring->rp = next_entry(ring, ring->rp);
++				break;
++			} else if (ring->ring_size - ring->wp < w_len) {
++				if (ring->rp == 0)
++					ring->rp = next_entry(ring, ring->rp);
++				/* 0 pad insufficient tail space */
++				memset((uint8 *)ring->ring_buf + ring->wp, 0,
++				       DBG_RING_ENTRY_SIZE);
++				ring->wp = 0;
++				continue;
++			} else {
++				break;
++			}
++		}
++		if (ring->rp > ring->wp) {
++			if (ring->rp - ring->wp <= w_len) {
++				ring->rp = next_entry(ring, ring->rp);
++				continue;
++			} else {
++				break;
++			}
++		}
++	} while (1);
++
++	w_entry = (dhd_dbg_ring_entry_t *)((uint8 *)ring->ring_buf + ring->wp);
++	/* header */
++	memcpy(w_entry, hdr, DBG_RING_ENTRY_SIZE);
++	w_entry->len = hdr->len;
++	/* payload */
++	memcpy((char *)w_entry + DBG_RING_ENTRY_SIZE, data, w_entry->len);
++	/* update write pointer */
++	ring->wp += w_len;
++	/* update statistics */
++	ring->stat.written_records++;
++	ring->stat.written_bytes += w_len;
++	dhd_os_spin_unlock(ring->lock, flags);
++	DHD_DBGIF(("%s : written_records %d, written_bytes %d\n", __FUNCTION__,
++		ring->stat.written_records, ring->stat.written_bytes));
++
++	/* if the current pending size is bigger than threshold */
++	if (ring->threshold > 0 &&
++		(READ_AVAIL_SPACE(ring->wp, ring->rp, ring->ring_size) >=
++	    ring->threshold))
++		dhdp->dbg->pullreq(dhdp->dbg->private, ring->id);
++	return  BCME_OK;
++}
++
++static int
++dhd_dbg_msgtrace_seqchk(uint32 *prev, uint32 cur)
++{
++	/* normal case including wrap around */
++	if ((cur == 0 && *prev == 0xFFFFFFFF) || ((cur - *prev) == 1)) {
++		goto done;
++	} else if (cur == *prev) {
++		DHD_EVENT(("%s duplicate trace\n", __FUNCTION__));
++		return -1;
++	} else if (cur > *prev) {
++		DHD_EVENT(("%s lost %d packets\n", __FUNCTION__, cur - *prev));
++	} else {
++		DHD_EVENT(("%s seq out of order, dhd %d, dongle %d\n",
++			__FUNCTION__, *prev, cur));
++	}
++done:
++	*prev = cur;
++	return 0;
++}
++
++static void
++dhd_dbg_msgtrace_msg_parser(void *event_data)
++{
++	msgtrace_hdr_t *hdr;
++	char *data, *s;
++	static uint32 seqnum_prev = 0;
++
++	hdr = (msgtrace_hdr_t *)event_data;
++	data = (char *)event_data + MSGTRACE_HDRLEN;
++
++	/* There are 2 bytes available at the end of data */
++	data[ntoh16(hdr->len)] = '\0';
++
++	if (ntoh32(hdr->discarded_bytes) || ntoh32(hdr->discarded_printf)) {
++		DHD_DBGIF(("WLC_E_TRACE: [Discarded traces in dongle -->"
++			"discarded_bytes %d discarded_printf %d]\n",
++			ntoh32(hdr->discarded_bytes),
++			ntoh32(hdr->discarded_printf)));
++	}
++
++	if (dhd_dbg_msgtrace_seqchk(&seqnum_prev, ntoh32(hdr->seqnum)))
++		return;
++
++	/* Display the trace buffer. Advance from
++	 * \n to \n to avoid display big
++	 * printf (issue with Linux printk )
++	 */
++	while (*data != '\0' && (s = strstr(data, "\n")) != NULL) {
++		*s = '\0';
++		DHD_FWLOG(("[FWLOG] %s\n", data));
++		data = s+1;
++	}
++	if (*data)
++		DHD_FWLOG(("[FWLOG] %s", data));
++}
++
++#ifdef SHOW_LOGTRACE
++static const uint8 *
++event_get_tlv(uint16 id, const char* tlvs, uint tlvs_len)
++{
++	const uint8 *pos = tlvs;
++	const uint8 *end = pos + tlvs_len;
++	tlv_log *tlv;
++	int rest;
++
++	while (pos + 1 < end) {
++		if (pos + 4 + pos[1] > end)
++			break;
++		tlv = (tlv_log *) pos;
++		if (tlv->tag == id)
++			return pos;
++		rest = tlv->len % 4; /* padding values */
++		pos += 4 + tlv->len + rest;
++	}
++	return NULL;
++}
++
++#define DATA_UNIT_FOR_LOG_CNT 4
++static int
++dhd_dbg_nan_event_handler(dhd_pub_t *dhdp, event_log_hdr_t *hdr, uint32 *data)
++{
++	int ret = BCME_OK;
++	wl_event_log_id_t nan_hdr;
++	log_nan_event_t *evt_payload;
++	uint16 evt_payload_len = 0, tot_payload_len = 0;
++	dhd_dbg_ring_entry_t msg_hdr;
++	bool evt_match = FALSE;
++	event_log_hdr_t *ts_hdr;
++	uint32 *ts_data;
++	char *tlvs, *dest_tlvs;
++	tlv_log *tlv_data;
++	int tlv_len = 0;
++	int i = 0, evt_idx = 0;
++	char eaddr_buf[ETHER_ADDR_STR_LEN];
++
++	BCM_REFERENCE(eaddr_buf);
++
++	nan_hdr.t = *data;
++	DHD_DBGIF(("%s: version %u event %x\n", __FUNCTION__, nan_hdr.version,
++		nan_hdr.event));
++
++	if (nan_hdr.version != DIAG_VERSION) {
++		DHD_ERROR(("Event payload version %u mismatch with current version %u\n",
++			nan_hdr.version, DIAG_VERSION));
++		return BCME_VERSION;
++	}
++	memset(&msg_hdr, 0, sizeof(dhd_dbg_ring_entry_t));
++	ts_hdr = (event_log_hdr_t *)((uint8 *)data - sizeof(event_log_hdr_t));
++	if (ts_hdr->tag == EVENT_LOG_TAG_TS) {
++		ts_data = (uint32 *)ts_hdr - ts_hdr->count;
++		msg_hdr.timestamp = (uint64)ts_data[0];
++		msg_hdr.flags |= DBG_RING_ENTRY_FLAGS_HAS_TIMESTAMP;
++	}
++	msg_hdr.type = DBG_RING_ENTRY_NAN_EVENT_TYPE;
++	for (i = 0; i < ARRAYSIZE(nan_event_map); i++) {
++		if (nan_event_map[i].fw_id == nan_hdr.event) {
++			evt_match = TRUE;
++			evt_idx = i;
++			break;
++		}
++	}
++	if (evt_match) {
++		DHD_DBGIF(("%s : event (%s)\n", __FUNCTION__, nan_event_map[evt_idx].desc));
++		/* payload length for nan event data */
++		evt_payload_len = sizeof(log_nan_event_t) +
++			(hdr->count - 2) * DATA_UNIT_FOR_LOG_CNT;
++		if ((evt_payload = MALLOC(dhdp->osh, evt_payload_len)) == NULL) {
++			DHD_ERROR(("Memory allocation failed for nan evt log (%u)\n",
++				evt_payload_len));
++			return BCME_NOMEM;
++		}
++		evt_payload->version = NAN_EVENT_VERSION;
++		evt_payload->event = nan_event_map[evt_idx].host_id;
++		dest_tlvs = (char *)evt_payload->tlvs;
++		tot_payload_len = sizeof(log_nan_event_t);
++		tlvs = (char *)(&data[1]);
++		tlv_len = (hdr->count - 2) * DATA_UNIT_FOR_LOG_CNT;
++		for (i = 0; i < ARRAYSIZE(nan_evt_tag_map); i++) {
++			tlv_data = (tlv_log *)event_get_tlv(nan_evt_tag_map[i].fw_id,
++				tlvs, tlv_len);
++			if (tlv_data) {
++				DHD_DBGIF(("NAN evt tlv.tag(%s), tlv.len : %d, tlv.data :  ",
++					nan_evt_tag_map[i].desc, tlv_data->len));
++				memcpy(dest_tlvs, tlv_data, sizeof(tlv_log) + tlv_data->len);
++				tot_payload_len += tlv_data->len + sizeof(tlv_log);
++				switch (tlv_data->tag) {
++					case TRACE_TAG_BSSID:
++					case TRACE_TAG_ADDR:
++						DHD_DBGIF(("%s\n",
++						bcm_ether_ntoa(
++							(const struct ether_addr *)tlv_data->value,
++							eaddr_buf)));
++					break;
++					default:
++						if (DHD_DBGIF_ON()) {
++							prhex(NULL, &tlv_data->value[0],
++								tlv_data->len);
++						}
++					break;
++				}
++				dest_tlvs += tlv_data->len + sizeof(tlv_log);
++			}
++		}
++		msg_hdr.flags |= DBG_RING_ENTRY_FLAGS_HAS_BINARY;
++		msg_hdr.len = tot_payload_len;
++		dhd_dbg_ring_push(dhdp, NAN_EVENT_RING_ID, &msg_hdr, evt_payload);
++		MFREE(dhdp->osh, evt_payload, evt_payload_len);
++	}
++	return ret;
++}
++
++static int
++dhd_dbg_custom_evnt_handler(dhd_pub_t *dhdp, event_log_hdr_t *hdr, uint32 *data)
++{
++	int i = 0, match_idx = 0;
++	int payload_len, tlv_len;
++	uint16 tot_payload_len = 0;
++	int ret = BCME_OK;
++	int log_level;
++	wl_event_log_id_t wl_log_id;
++	dhd_dbg_ring_entry_t msg_hdr;
++	log_conn_event_t *event_data;
++	bool evt_match = FALSE;
++	event_log_hdr_t *ts_hdr;
++	uint32 *ts_data;
++	char *tlvs, *dest_tlvs;
++	tlv_log *tlv_data;
++	static uint64 ts_saved = 0;
++	char eabuf[ETHER_ADDR_STR_LEN];
++	char chanbuf[CHANSPEC_STR_LEN];
++
++	BCM_REFERENCE(eabuf);
++	BCM_REFERENCE(chanbuf);
++	/* get a event type and version */
++	wl_log_id.t = *data;
++	if (wl_log_id.version != DIAG_VERSION)
++		return BCME_VERSION;
++
++	ts_hdr = (event_log_hdr_t *)((uint8 *)data - sizeof(event_log_hdr_t));
++	if (ts_hdr->tag == EVENT_LOG_TAG_TS) {
++		ts_data = (uint32 *)ts_hdr - ts_hdr->count;
++		ts_saved = (uint64)ts_data[0];
++	}
++	memset(&msg_hdr, 0, sizeof(dhd_dbg_ring_entry_t));
++	msg_hdr.timestamp = ts_saved;
++
++	DHD_DBGIF(("Android Event ver %d, payload %d words, ts %llu\n",
++		(*data >> 16), hdr->count - 1, ts_saved));
++
++	/* Perform endian convertion */
++	for (i = 0; i < hdr->count; i++) {
++		/* *(data + i) = ntoh32(*(data + i)); */
++		DHD_DATA(("%08x ", *(data + i)));
++	}
++	DHD_DATA(("\n"));
++	msg_hdr.flags |= DBG_RING_ENTRY_FLAGS_HAS_TIMESTAMP;
++	msg_hdr.flags |= DBG_RING_ENTRY_FLAGS_HAS_BINARY;
++	msg_hdr.type = DBG_RING_ENTRY_EVENT_TYPE;
++
++	/* convert the data to log_conn_event_t format */
++	for (i = 0; i < ARRAYSIZE(event_map); i++) {
++		if (event_map[i].fw_id == wl_log_id.event) {
++			evt_match = TRUE;
++			match_idx = i;
++			break;
++		}
++	}
++	if (evt_match) {
++		log_level = dhdp->dbg->dbg_rings[FW_EVENT_RING_ID].log_level;
++		/* filter the data based on log_level */
++		for (i = 0; i < ARRAYSIZE(fw_event_level_map); i++) {
++			if ((fw_event_level_map[i].tag == hdr->tag) &&
++				(fw_event_level_map[i].log_level > log_level)) {
++				return BCME_OK;
++			}
++		}
++		DHD_DBGIF(("%s : event (%s)\n", __FUNCTION__, event_map[match_idx].desc));
++		/* get the payload length for event data (skip : log header + timestamp) */
++		payload_len = sizeof(log_conn_event_t) + DATA_UNIT_FOR_LOG_CNT * (hdr->count - 2);
++		event_data = MALLOC(dhdp->osh, payload_len);
++		if (!event_data) {
++			DHD_ERROR(("failed to allocate the log_conn_event_t with length(%d)\n",
++				payload_len));
++			return BCME_NOMEM;
++		}
++		event_data->event = event_map[match_idx].host_id;
++		dest_tlvs = (char *)event_data->tlvs;
++		tot_payload_len = sizeof(log_conn_event_t);
++		tlvs = (char *)(&data[1]);
++		tlv_len = (hdr->count - 2) * DATA_UNIT_FOR_LOG_CNT;
++		for (i = 0; i < ARRAYSIZE(event_tag_map); i++) {
++			tlv_data = (tlv_log *)event_get_tlv(event_tag_map[i].fw_id, tlvs, tlv_len);
++			if (tlv_data) {
++				DHD_DBGIF(("tlv.tag(%s), tlv.len : %d, tlv.data :  ",
++					event_tag_map[i].desc, tlv_data->len));
++				memcpy(dest_tlvs, tlv_data, sizeof(tlv_log) + tlv_data->len);
++				tot_payload_len += tlv_data->len + sizeof(tlv_log);
++				switch (tlv_data->tag) {
++				case TRACE_TAG_BSSID:
++				case TRACE_TAG_ADDR:
++				case TRACE_TAG_ADDR1:
++				case TRACE_TAG_ADDR2:
++				case TRACE_TAG_ADDR3:
++				case TRACE_TAG_ADDR4:
++					DHD_DBGIF(("%s\n",
++					bcm_ether_ntoa((const struct ether_addr *)tlv_data->value,
++							eabuf)));
++					break;
++				case TRACE_TAG_SSID:
++					DHD_DBGIF(("%s\n", tlv_data->value));
++					break;
++				case TRACE_TAG_STATUS:
++					DHD_DBGIF(("%d\n", ltoh32_ua(&tlv_data->value[0])));
++					break;
++				case TRACE_TAG_REASON_CODE:
++					DHD_DBGIF(("%d\n", ltoh16_ua(&tlv_data->value[0])));
++					break;
++				case TRACE_TAG_RATE_MBPS:
++					DHD_DBGIF(("%d Kbps\n",
++						ltoh16_ua(&tlv_data->value[0]) * 500));
++					break;
++				case TRACE_TAG_CHANNEL_SPEC:
++					DHD_DBGIF(("%s\n",
++						wf_chspec_ntoa(
++							ltoh16_ua(&tlv_data->value[0]), chanbuf)));
++					break;
++				default:
++					if (DHD_DBGIF_ON()) {
++						prhex(NULL, &tlv_data->value[0], tlv_data->len);
++					}
++				}
++				dest_tlvs += tlv_data->len + sizeof(tlv_log);
++			}
++		}
++		msg_hdr.len = tot_payload_len;
++		dhd_dbg_ring_push(dhdp, FW_EVENT_RING_ID, &msg_hdr, event_data);
++		MFREE(dhdp->osh, event_data, payload_len);
++	}
++	return ret;
++}
++
++#define MAX_NO_OF_ARG	16
++#define FMTSTR_SIZE	132
++#define ROMSTR_SIZE	200
++#define SIZE_LOC_STR	50
++static void
++dhd_dbg_verboselog_handler(dhd_pub_t *dhdp, event_log_hdr_t *hdr,
++		void *raw_event_ptr)
++{
++	dhd_event_log_t *raw_event = (dhd_event_log_t *)raw_event_ptr;
++	event_log_hdr_t *ts_hdr;
++	uint32 *log_ptr = (uint32 *)hdr - hdr->count;
++	uint16 count;
++	int log_level, id;
++	char fmtstr_loc_buf[ROMSTR_SIZE] = { 0 };
++	uint32 rom_str_len = 0;
++	char (*str_buf)[SIZE_LOC_STR] = NULL;
++	char *str_tmpptr = NULL;
++	uint32 addr = 0;
++	typedef union {
++		uint32 val;
++		char * addr;
++	} u_arg;
++	u_arg arg[MAX_NO_OF_ARG] = {{0}};
++	char *c_ptr = NULL;
++	uint32 *ts_data;
++	static uint64 ts_saved = 0;
++	dhd_dbg_ring_entry_t msg_hdr;
++	struct bcmstrbuf b;
++	UNUSED_PARAMETER(arg);
++
++	/* Get time stamp if it's updated */
++	ts_hdr = (void *)log_ptr - sizeof(event_log_hdr_t);
++	if (ts_hdr->tag == EVENT_LOG_TAG_TS) {
++		ts_data = (uint32 *)ts_hdr - ts_hdr->count;
++		ts_saved = (uint64)ts_data[0];
++		DHD_MSGTRACE_LOG(("EVENT_LOG_TS[0x%08x]: SYS:%08x CPU:%08x\n",
++			ts_data[ts_hdr->count - 1], ts_data[0], ts_data[1]));
++	}
++
++	if (hdr->tag == EVENT_LOG_TAG_ROM_PRINTF) {
++		rom_str_len = (hdr->count - 1) * sizeof(uint32);
++		if (rom_str_len >= (ROMSTR_SIZE -1))
++			rom_str_len = ROMSTR_SIZE - 1;
++
++		/* copy all ascii data for ROM printf to local string */
++		memcpy(fmtstr_loc_buf, log_ptr, rom_str_len);
++		/* add end of line at last */
++		fmtstr_loc_buf[rom_str_len] = '\0';
++
++		DHD_MSGTRACE_LOG(("EVENT_LOG_ROM[0x%08x]: %s",
++				log_ptr[hdr->count - 1], fmtstr_loc_buf));
++
++		/* Add newline if missing */
++		if (fmtstr_loc_buf[strlen(fmtstr_loc_buf) - 1] != '\n')
++			DHD_MSGTRACE_LOG(("\n"));
++
++		return;
++	}
++
++	/* print the message out in a logprint  */
++	if (!(((raw_event->raw_sstr) || (raw_event->rom_raw_sstr)) &&
++		raw_event->fmts) || hdr->fmt_num == 0xffff) {
++		if (dhdp->dbg) {
++			log_level = dhdp->dbg->dbg_rings[FW_VERBOSE_RING_ID].log_level;
++			for (id = 0; id < ARRAYSIZE(fw_verbose_level_map); id++) {
++				if ((fw_verbose_level_map[id].tag == hdr->tag) &&
++					(fw_verbose_level_map[id].log_level > log_level))
++					return;
++			}
++		}
++
++		bcm_binit(&b, fmtstr_loc_buf, FMTSTR_SIZE);
++		bcm_bprintf(&b, "%d.%d EL: %x %x", (uint32)ts_saved / 1000,
++			(uint32)ts_saved % 1000,
++			hdr->tag & EVENT_LOG_TAG_FLAG_SET_MASK,
++			hdr->fmt_num);
++		for (count = 0; count < (hdr->count - 1); count++)
++			bcm_bprintf(&b, " %x", log_ptr[count]);
++		bcm_bprintf(&b, "\n");
++		DHD_MSGTRACE_LOG(("%s\n", b.origbuf));
++		if (!dhdp->dbg)
++			return;
++		memset(&msg_hdr, 0, sizeof(dhd_dbg_ring_entry_t));
++		msg_hdr.timestamp = ts_saved;
++		msg_hdr.flags |= DBG_RING_ENTRY_FLAGS_HAS_TIMESTAMP;
++		msg_hdr.type = DBG_RING_ENTRY_DATA_TYPE;
++		msg_hdr.len = b.origsize - b.size;
++		dhd_dbg_ring_push(dhdp, FW_VERBOSE_RING_ID, &msg_hdr,
++				b.origbuf);
++		return;
++	}
++
++	str_buf = MALLOCZ(dhdp->osh, (MAX_NO_OF_ARG * SIZE_LOC_STR));
++	if (!str_buf) {
++		DHD_ERROR(("%s: malloc failed str_buf\n", __FUNCTION__));
++		return;
++	}
++
++	if ((hdr->fmt_num >> 2) < raw_event->num_fmts) {
++		snprintf(fmtstr_loc_buf, FMTSTR_SIZE, "CONSOLE_E: [0x%x] %s",
++			log_ptr[hdr->count-1],
++			raw_event->fmts[hdr->fmt_num >> 2]);
++		c_ptr = fmtstr_loc_buf;
++	} else {
++		DHD_ERROR(("%s: fmt number out of range \n", __FUNCTION__));
++		goto exit;
++	}
++
++	for (count = 0; count < (hdr->count - 1); count++) {
++		if (c_ptr != NULL)
++			if ((c_ptr = strstr(c_ptr, "%")) != NULL)
++				c_ptr++;
++
++		if ((c_ptr != NULL) && (*c_ptr == 's')) {
++			if ((raw_event->raw_sstr) &&
++				((log_ptr[count] > raw_event->rodata_start) &&
++				(log_ptr[count] < raw_event->rodata_end))) {
++				/* ram static string */
++				addr = log_ptr[count] - raw_event->rodata_start;
++				str_tmpptr = raw_event->raw_sstr + addr;
++				memcpy(str_buf[count], str_tmpptr,
++					SIZE_LOC_STR);
++				str_buf[count][SIZE_LOC_STR-1] = '\0';
++				arg[count].addr = str_buf[count];
++			} else if ((raw_event->rom_raw_sstr) &&
++					((log_ptr[count] >
++					raw_event->rom_rodata_start) &&
++					(log_ptr[count] <
++					raw_event->rom_rodata_end))) {
++				/* rom static string */
++				addr = log_ptr[count] - raw_event->rom_rodata_start;
++				str_tmpptr = raw_event->rom_raw_sstr + addr;
++				memcpy(str_buf[count], str_tmpptr,
++					SIZE_LOC_STR);
++				str_buf[count][SIZE_LOC_STR-1] = '\0';
++				arg[count].addr = str_buf[count];
++			} else {
++				/*
++				*  Dynamic string OR
++				* No data for static string.
++				* So store all string's address as string.
++				*/
++				snprintf(str_buf[count], SIZE_LOC_STR,
++					"(s)0x%x", log_ptr[count]);
++				arg[count].addr = str_buf[count];
++			}
++		} else {
++			/* Other than string */
++			arg[count].val = log_ptr[count];
++		}
++		DHD_DBGIF(("Arg val = %d and address = %p\n", arg[count].val, arg[count].addr));
++	}
++	DHD_EVENT((fmtstr_loc_buf, arg[0], arg[1], arg[2], arg[3],
++		arg[4], arg[5], arg[6], arg[7], arg[8], arg[9], arg[10],
++		arg[11], arg[12], arg[13], arg[14], arg[15]));
++
++exit:
++	MFREE(dhdp->osh, str_buf, (MAX_NO_OF_ARG * SIZE_LOC_STR));
++}
++
++static void
++dhd_dbg_msgtrace_log_parser(dhd_pub_t *dhdp, void *event_data,
++	void *raw_event_ptr, uint datalen)
++{
++	msgtrace_hdr_t *hdr;
++	char *data;
++	int id;
++	uint32 hdrlen = sizeof(event_log_hdr_t);
++	static uint32 seqnum_prev = 0;
++	event_log_hdr_t *log_hdr;
++	bool msg_processed = FALSE;
++	uint32 *log_ptr =  NULL;
++	dll_t list_head, *cur;
++	loglist_item_t *log_item;
++	uint32 nan_evt_ring_log_level = 0;
++
++	hdr = (msgtrace_hdr_t *)event_data;
++	data = (char *)event_data + MSGTRACE_HDRLEN;
++	datalen -= MSGTRACE_HDRLEN;
++
++	if (dhd_dbg_msgtrace_seqchk(&seqnum_prev, ntoh32(hdr->seqnum)))
++		return;
++
++	DHD_MSGTRACE_LOG(("EVENT_LOG_HDR[No.%d]: timestamp 0x%08x length = %d\n",
++		ltoh16(*((uint16 *)data)), ltoh16(*((uint16 *)(data + 2))),
++		ltoh32(*((uint32 *)(data+4)))));
++	data += 8;
++	datalen -= 8;
++
++	/* start parsing from the tail of packet
++	 * Sameple format of a meessage
++	 * 001d3c54 00000064 00000064 001d3c54 001dba08 035d6ce1 0c540639
++	 * 001d3c54 00000064 00000064 035d6d89 0c580439
++	 * 0x0c580439 -- 39 is tag, 04 is count, 580c is format number
++	 * all these uint32 values comes in reverse order as group as EL data
++	 * while decoding we can only parse from last to first
++	 */
++	dll_init(&list_head);
++	while (datalen > 0) {
++		log_hdr = (event_log_hdr_t *)(data + datalen - hdrlen);
++		/* pratially overwritten entries */
++		if ((uint32 *)log_hdr - (uint32 *)data < log_hdr->count)
++			break;
++		/* Check argument count (only when format is valid) */
++		if ((log_hdr->count > MAX_NO_OF_ARG) &&
++		    (log_hdr->fmt_num != 0xffff))
++			break;
++		/* end of frame? */
++		if (log_hdr->tag == EVENT_LOG_TAG_NULL) {
++			log_hdr--;
++			datalen -= hdrlen;
++			continue;
++		}
++		/* skip 4 bytes time stamp packet */
++		if (log_hdr->tag == EVENT_LOG_TAG_TS) {
++			datalen -= log_hdr->count * 4 + hdrlen;
++			log_hdr -= log_hdr->count + hdrlen / 4;
++			continue;
++		}
++		if (!(log_item = MALLOC(dhdp->osh, sizeof(*log_item)))) {
++			DHD_ERROR(("%s allocating log list item failed\n",
++				__FUNCTION__));
++			break;
++		}
++		log_item->hdr = log_hdr;
++		dll_insert(&log_item->list, &list_head);
++		datalen -= (log_hdr->count * 4 + hdrlen);
++	}
++
++	while (!dll_empty(&list_head)) {
++		msg_processed = FALSE;
++		cur = dll_head_p(&list_head);
++		log_item = (loglist_item_t *)container_of(cur, loglist_item_t, list);
++		log_hdr = log_item->hdr;
++		log_ptr = (uint32 *)log_hdr - log_hdr->count;
++		dll_delete(cur);
++		MFREE(dhdp->osh, log_item, sizeof(*log_item));
++
++		/* Before DHD debugability is implemented WLC_E_TRACE had been
++		 * used to carry verbose logging from firmware. We need to
++		 * be able to handle those messages even without a initialized
++		 * debug layer.
++		 */
++		if (dhdp->dbg) {
++			/* check the data for NAN event ring; keeping first as small table */
++			/* process only user configured to log */
++			nan_evt_ring_log_level = dhdp->dbg->dbg_rings[NAN_EVENT_RING_ID].log_level;
++			if (dhdp->dbg->dbg_rings[NAN_EVENT_RING_ID].log_level) {
++				for (id = 0; id < ARRAYSIZE(nan_event_level_map); id++) {
++					if (nan_event_level_map[id].tag == log_hdr->tag) {
++						/* dont process if tag log level is greater
++						 * than ring log level
++						 */
++						if (nan_event_level_map[id].log_level >
++							nan_evt_ring_log_level) {
++							msg_processed = TRUE;
++							break;
++						}
++						/* In case of BCME_VERSION error,
++						 * this is not NAN event type data
++						 */
++						if (dhd_dbg_nan_event_handler(dhdp,
++							log_hdr, log_ptr) != BCME_VERSION) {
++							msg_processed = TRUE;
++						}
++						break;
++					}
++				}
++			}
++			if (!msg_processed) {
++				/* check the data for event ring */
++				for (id = 0; id < ARRAYSIZE(fw_event_level_map); id++) {
++					if (fw_event_level_map[id].tag == log_hdr->tag) {
++						/* In case of BCME_VERSION error,
++						 * this is not event type data
++						 */
++						if (dhd_dbg_custom_evnt_handler(dhdp,
++							log_hdr, log_ptr) != BCME_VERSION) {
++							msg_processed = TRUE;
++						}
++						break;
++					}
++				}
++			}
++		}
++		if (!msg_processed)
++			dhd_dbg_verboselog_handler(dhdp, log_hdr, raw_event_ptr);
++
++	}
++}
++#else /* !SHOW_LOGTRACE */
++static INLINE void dhd_dbg_verboselog_handler(dhd_pub_t *dhdp,
++	event_log_hdr_t *hdr, void *raw_event_ptr) {};
++static INLINE void dhd_dbg_msgtrace_log_parser(dhd_pub_t *dhdp,
++	void *event_data, void *raw_event_ptr, uint datalen) {};
++#endif /* SHOW_LOGTRACE */
++
++void
++dhd_dbg_trace_evnt_handler(dhd_pub_t *dhdp, void *event_data,
++		void *raw_event_ptr, uint datalen)
++{
++	msgtrace_hdr_t *hdr;
++
++	hdr = (msgtrace_hdr_t *)event_data;
++
++	if (hdr->version != MSGTRACE_VERSION) {
++		DHD_DBGIF(("%s unsupported MSGTRACE version, dhd %d, dongle %d\n",
++			__FUNCTION__, MSGTRACE_VERSION, hdr->version));
++		return;
++	}
++
++	if (hdr->trace_type == MSGTRACE_HDR_TYPE_MSG)
++		dhd_dbg_msgtrace_msg_parser(event_data);
++	else if (hdr->trace_type == MSGTRACE_HDR_TYPE_LOG)
++		dhd_dbg_msgtrace_log_parser(dhdp, event_data, raw_event_ptr, datalen);
++}
++
++static int
++dhd_dbg_ring_init(dhd_pub_t *dhdp, dhd_dbg_ring_t *ring, uint16 id, uint8 *name,
++		uint32 ring_sz)
++{
++	void *buf;
++	unsigned long flags;
++
++	buf = MALLOCZ(dhdp->osh, ring_sz);
++	if (!buf)
++		return BCME_NOMEM;
++
++	ring->lock = dhd_os_spin_lock_init(dhdp->osh);
++
++	flags = dhd_os_spin_lock(ring->lock);
++	ring->id = id;
++	strncpy(ring->name, name, DBGRING_NAME_MAX);
++	ring->name[DBGRING_NAME_MAX - 1] = 0;
++	ring->ring_size = ring_sz;
++	ring->wp = ring->rp = 0;
++	ring->ring_buf = buf;
++	ring->threshold = DBGRING_FLUSH_THRESHOLD(ring);
++	ring->state = RING_SUSPEND;
++	dhd_os_spin_unlock(ring->lock, flags);
++
++	return BCME_OK;
++}
++
++static void
++dhd_dbg_ring_deinit(dhd_pub_t *dhdp, dhd_dbg_ring_t *ring)
++{
++	void *buf;
++	uint32 ring_sz;
++	unsigned long flags;
++
++	if (!ring->ring_buf)
++		return;
++
++	flags = dhd_os_spin_lock(ring->lock);
++	ring->id = 0;
++	ring->name[0] = 0;
++	ring_sz = ring->ring_size;
++	ring->ring_size = 0;
++	ring->wp = ring->rp = 0;
++	buf = ring->ring_buf;
++	ring->ring_buf = NULL;
++	memset(&ring->stat, 0, sizeof(ring->stat));
++	ring->threshold = 0;
++	ring->state = RING_STOP;
++	dhd_os_spin_unlock(ring->lock, flags);
++
++	dhd_os_spin_lock_deinit(dhdp->osh, ring->lock);
++
++	MFREE(dhdp->osh, buf, ring_sz);
++}
++
++/*
++ * dhd_dbg_set_event_log_tag : modify the state of an event log tag
++ */
++void
++dhd_dbg_set_event_log_tag(dhd_pub_t *dhdp, uint16 tag, uint8 set)
++{
++	wl_el_tag_params_t pars;
++	char *cmd = "event_log_tag_control";
++	char iovbuf[WLC_IOCTL_SMLEN] = { 0 };
++	int ret;
++
++	memset(&pars, 0, sizeof(pars));
++	pars.tag = tag;
++	pars.set = set;
++	pars.flags = EVENT_LOG_TAG_FLAG_LOG;
++
++	if (!bcm_mkiovar(cmd, (char *)&pars, sizeof(pars), iovbuf, sizeof(iovbuf))) {
++		DHD_ERROR(("%s mkiovar failed\n", __FUNCTION__));
++		return;
++	}
++
++	ret = dhd_wl_ioctl_cmd(dhdp, WLC_SET_VAR, iovbuf, sizeof(iovbuf), TRUE, 0);
++	if (ret) {
++		DHD_ERROR(("%s set log tag iovar failed %d\n", __FUNCTION__, ret));
++	}
++}
++
++int
++dhd_dbg_set_configuration(dhd_pub_t *dhdp, int ring_id, int log_level, int flags, uint32 threshold)
++{
++	dhd_dbg_ring_t *ring;
++	uint8 set = 1;
++	unsigned long lock_flags;
++	int i, array_len = 0;
++	struct log_level_table *log_level_tbl = NULL;
++	if (!dhdp || !dhdp->dbg)
++		return BCME_BADADDR;
++
++	ring = &dhdp->dbg->dbg_rings[ring_id];
++
++	if (ring->state == RING_STOP)
++		return BCME_UNSUPPORTED;
++
++	lock_flags = dhd_os_spin_lock(ring->lock);
++	if (log_level == 0)
++		ring->state = RING_SUSPEND;
++	else
++		ring->state = RING_ACTIVE;
++	ring->log_level = log_level;
++
++	ring->threshold = (threshold > ring->threshold) ? ring->ring_size : threshold;
++	dhd_os_spin_unlock(ring->lock, lock_flags);
++	if (log_level > 0)
++		set = TRUE;
++
++	if (ring->id == FW_EVENT_RING_ID) {
++		log_level_tbl = fw_event_level_map;
++		array_len = ARRAYSIZE(fw_event_level_map);
++	} else if (ring->id == FW_VERBOSE_RING_ID) {
++		log_level_tbl = fw_verbose_level_map;
++		array_len = ARRAYSIZE(fw_verbose_level_map);
++	} else if (ring->id == NAN_EVENT_RING_ID) {
++		log_level_tbl = nan_event_level_map;
++		array_len = ARRAYSIZE(nan_event_level_map);
++	}
++
++	for (i = 0; i < array_len; i++) {
++		if (log_level == 0 || (log_level_tbl[i].log_level > log_level)) {
++			/* clear the reference per ring */
++			ref_tag_tbl[log_level_tbl[i].tag] &= ~(1 << ring_id);
++		} else {
++			/* set the reference per ring */
++			ref_tag_tbl[log_level_tbl[i].tag] |= (1 << ring_id);
++		}
++		set = (ref_tag_tbl[log_level_tbl[i].tag])? 1 : 0;
++		DHD_DBGIF(("%s TAG(%s) is %s for the ring(%s)\n", __FUNCTION__,
++			log_level_tbl[i].desc, (set)? "SET" : "CLEAR", ring->name));
++		dhd_dbg_set_event_log_tag(dhdp, log_level_tbl[i].tag, set);
++	}
++	return BCME_OK;
++}
++
++/*
++* dhd_dbg_get_ring_status : get the ring status from the coresponding ring buffer
++* Return: An error code or 0 on success.
++*/
++
++int
++dhd_dbg_get_ring_status(dhd_pub_t *dhdp, int ring_id, dhd_dbg_ring_status_t *dbg_ring_status)
++{
++	int ret = BCME_OK;
++	int id = 0;
++	dhd_dbg_t *dbg;
++	dhd_dbg_ring_t *dbg_ring;
++	dhd_dbg_ring_status_t ring_status;
++	if (!dhdp || !dhdp->dbg)
++		return BCME_BADADDR;
++	dbg = dhdp->dbg;
++
++	memset(&ring_status, 0, sizeof(dhd_dbg_ring_status_t));
++	for (id = DEBUG_RING_ID_INVALID + 1; id < DEBUG_RING_ID_MAX; id++) {
++		dbg_ring = &dbg->dbg_rings[id];
++		if (VALID_RING(dbg_ring->id) && (dbg_ring->id == ring_id)) {
++			RING_STAT_TO_STATUS(dbg_ring, ring_status);
++			*dbg_ring_status = ring_status;
++			break;
++		}
++	}
++	if (!VALID_RING(id)) {
++		DHD_ERROR(("%s : cannot find the ring_id : %d\n", __FUNCTION__, ring_id));
++		ret = BCME_NOTFOUND;
++	}
++	return ret;
++}
++
++/*
++* dhd_dbg_find_ring_id : return ring_id based on ring_name
++* Return: An invalid ring id for failure or valid ring id on success.
++*/
++
++int
++dhd_dbg_find_ring_id(dhd_pub_t *dhdp, char *ring_name)
++{
++	int id;
++	dhd_dbg_t *dbg;
++	dhd_dbg_ring_t *ring;
++
++	if (!dhdp || !dhdp->dbg)
++		return BCME_BADADDR;
++
++	dbg = dhdp->dbg;
++	for (id = DEBUG_RING_ID_INVALID + 1; id < DEBUG_RING_ID_MAX; id++) {
++		ring = &dbg->dbg_rings[id];
++		if (!strncmp(ring->name, ring_name, sizeof(ring->name) - 1))
++			break;
++	}
++	return id;
++}
++
++/*
++* dhd_dbg_get_priv : get the private data of dhd dbugability module
++* Return : An NULL on failure or valid data address
++*/
++void *
++dhd_dbg_get_priv(dhd_pub_t *dhdp)
++{
++	if (!dhdp || !dhdp->dbg)
++		return NULL;
++	return dhdp->dbg->private;
++}
++
++/*
++* dhd_dbg_start : start and stop All of Ring buffers
++* Return: An error code or 0 on success.
++*/
++int
++dhd_dbg_start(dhd_pub_t *dhdp, bool start)
++{
++	int ret = BCME_OK;
++	int ring_id;
++	dhd_dbg_t *dbg;
++	dhd_dbg_ring_t *dbg_ring;
++	if (!dhdp || !dhdp->dbg)
++		return BCME_BADARG;
++	dbg = dhdp->dbg;
++
++	for (ring_id = DEBUG_RING_ID_INVALID + 1; ring_id < DEBUG_RING_ID_MAX; ring_id++) {
++		dbg_ring = &dbg->dbg_rings[ring_id];
++		if (!start) {
++			if (VALID_RING(dbg_ring->id)) {
++				/* Initialize the information for the ring */
++				dbg_ring->state = RING_SUSPEND;
++				dbg_ring->log_level = 0;
++				dbg_ring->rp = dbg_ring->wp = 0;
++				dbg_ring->threshold = 0;
++				memset(&dbg_ring->stat, 0, sizeof(struct ring_statistics));
++				memset(dbg_ring->ring_buf, 0, dbg_ring->ring_size);
++			}
++		}
++	}
++	return ret;
++}
++
++/*
++ * dhd_dbg_send_urgent_evt: send the health check evt to Upper layer
++ *
++ * Return: An error code or 0 on success.
++ */
++
++int
++dhd_dbg_send_urgent_evt(dhd_pub_t *dhdp, const void *data, const uint32 len)
++{
++	dhd_dbg_t *dbg;
++	int ret = BCME_OK;
++	if (!dhdp || !dhdp->dbg)
++		return BCME_BADADDR;
++
++	dbg = dhdp->dbg;
++	if (dbg->urgent_notifier) {
++		dbg->urgent_notifier(dhdp, data, len);
++	}
++	return ret;
++}
++/*
++ * dhd_dbg_attach: initialziation of dhd dbugability module
++ *
++ * Return: An error code or 0 on success.
++ */
++int
++dhd_dbg_attach(dhd_pub_t *dhdp, dbg_pullreq_t os_pullreq,
++	dbg_urgent_noti_t os_urgent_notifier, void *os_priv)
++{
++	dhd_dbg_t *dbg;
++	int ret, ring_id;
++
++	dbg = MALLOCZ(dhdp->osh, sizeof(dhd_dbg_t));
++	if (!dbg)
++		return BCME_NOMEM;
++
++	ret = dhd_dbg_ring_init(dhdp, &dbg->dbg_rings[FW_VERBOSE_RING_ID], FW_VERBOSE_RING_ID,
++			FW_VERBOSE_RING_NAME, FW_VERBOSE_RING_SIZE);
++	if (ret)
++		goto error;
++
++	ret = dhd_dbg_ring_init(dhdp, &dbg->dbg_rings[FW_EVENT_RING_ID], FW_EVENT_RING_ID,
++			FW_EVENT_RING_NAME, FW_EVENT_RING_SIZE);
++	if (ret)
++		goto error;
++
++	ret = dhd_dbg_ring_init(dhdp, &dbg->dbg_rings[DHD_EVENT_RING_ID], DHD_EVENT_RING_ID,
++			DHD_EVENT_RING_NAME, DHD_EVENT_RING_SIZE);
++	if (ret)
++		goto error;
++
++	ret = dhd_dbg_ring_init(dhdp, &dbg->dbg_rings[NAN_EVENT_RING_ID], NAN_EVENT_RING_ID,
++			NAN_EVENT_RING_NAME, NAN_EVENT_RING_SIZE);
++	if (ret)
++		goto error;
++
++	dbg->private = os_priv;
++	dbg->pullreq = os_pullreq;
++	dbg->urgent_notifier = os_urgent_notifier;
++	dhdp->dbg = dbg;
++
++	return BCME_OK;
++
++error:
++	for (ring_id = DEBUG_RING_ID_INVALID + 1; ring_id < DEBUG_RING_ID_MAX; ring_id++) {
++		if (VALID_RING(dbg->dbg_rings[ring_id].id)) {
++			dhd_dbg_ring_deinit(dhdp, &dbg->dbg_rings[ring_id]);
++		}
++	}
++	MFREE(dhdp->osh, dhdp->dbg, sizeof(dhd_dbg_t));
++
++	return ret;
++}
++
++/*
++ * dhd_dbg_detach: clean up dhd dbugability module
++ */
++void
++dhd_dbg_detach(dhd_pub_t *dhdp)
++{
++	int ring_id;
++	dhd_dbg_t *dbg;
++	if (!dhdp->dbg)
++		return;
++	dbg = dhdp->dbg;
++	for (ring_id = DEBUG_RING_ID_INVALID + 1; ring_id < DEBUG_RING_ID_MAX; ring_id++) {
++		if (VALID_RING(dbg->dbg_rings[ring_id].id)) {
++			dhd_dbg_ring_deinit(dhdp, &dbg->dbg_rings[ring_id]);
++		}
++	}
++	MFREE(dhdp->osh, dhdp->dbg, sizeof(dhd_dbg_t));
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_debug.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_debug.h
+new file mode 100644
+index 000000000..637d7246d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_debug.h
+@@ -0,0 +1,348 @@
++/*
++ * DHD debugability header file
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * $Id: dhd_debug.h 560028 2015-05-29 10:50:33Z $
++ */
++
++#ifndef _dhd_debug_h_
++#define _dhd_debug_h_
++enum {
++	DEBUG_RING_ID_INVALID	= 0,
++	FW_VERBOSE_RING_ID,
++	FW_EVENT_RING_ID,
++	DHD_EVENT_RING_ID,
++	NAN_EVENT_RING_ID,
++	/* add new id here */
++	DEBUG_RING_ID_MAX
++};
++
++enum {
++	/* Feature set */
++	DBG_MEMORY_DUMP_SUPPORTED = (1 << (0)), /* Memory dump of FW */
++	DBG_PER_PACKET_TX_RX_STATUS_SUPPORTED = (1 << (1)), /* PKT Status */
++	DBG_CONNECT_EVENT_SUPPORTED = (1 << (2)), /* Connectivity Event */
++	DBG_POWER_EVENT_SUPOORTED = (1 << (3)), /* POWER of Driver */
++	DBG_WAKE_LOCK_SUPPORTED = (1 << (4)), /* WAKE LOCK of Driver */
++	DBG_VERBOSE_LOG_SUPPORTED = (1 << (5)), /* verbose log of FW */
++	DBG_HEALTH_CHECK_SUPPORTED = (1 << (6)), /* monitor the health of FW */
++	DBG_NAN_EVENT_SUPPORTED = (1 << (7)), /* NAN Events */
++};
++
++enum {
++	/* set for binary entries */
++	DBG_RING_ENTRY_FLAGS_HAS_BINARY = (1 << (0)),
++	/* set if 64 bits timestamp is present */
++	DBG_RING_ENTRY_FLAGS_HAS_TIMESTAMP = (1 << (1))
++};
++
++#define DBGRING_NAME_MAX		32
++/* firmware verbose ring, ring id 1 */
++#define FW_VERBOSE_RING_NAME		"fw_verbose"
++#define FW_VERBOSE_RING_SIZE		(64 * 1024)
++/* firmware event ring, ring id 2 */
++#define FW_EVENT_RING_NAME		"fw_event"
++#define FW_EVENT_RING_SIZE		(64 * 1024)
++/* DHD connection event ring, ring id 3 */
++#define DHD_EVENT_RING_NAME		"dhd_event"
++#define DHD_EVENT_RING_SIZE		(64 * 1024)
++/* NAN event ring, ring id 4 */
++#define NAN_EVENT_RING_NAME		"nan_event"
++#define NAN_EVENT_RING_SIZE		(64 * 1024)
++
++#define DBG_RING_STATUS_SIZE (sizeof(dhd_dbg_ring_status_t))
++
++#define VALID_RING(id)	\
++	(id > DEBUG_RING_ID_INVALID && id < DEBUG_RING_ID_MAX)
++
++enum {
++	/* driver receive association command from kernel */
++	WIFI_EVENT_ASSOCIATION_REQUESTED	= 0,
++	WIFI_EVENT_AUTH_COMPLETE,
++	WIFI_EVENT_ASSOC_COMPLETE,
++	/* received firmware event indicating auth frames are sent */
++	WIFI_EVENT_FW_AUTH_STARTED,
++	/* received firmware event indicating assoc frames are sent */
++	WIFI_EVENT_FW_ASSOC_STARTED,
++	/* received firmware event indicating reassoc frames are sent */
++	WIFI_EVENT_FW_RE_ASSOC_STARTED,
++	WIFI_EVENT_DRIVER_SCAN_REQUESTED,
++	WIFI_EVENT_DRIVER_SCAN_RESULT_FOUND,
++	WIFI_EVENT_DRIVER_SCAN_COMPLETE,
++	WIFI_EVENT_G_SCAN_STARTED,
++	WIFI_EVENT_G_SCAN_COMPLETE,
++	WIFI_EVENT_DISASSOCIATION_REQUESTED,
++	WIFI_EVENT_RE_ASSOCIATION_REQUESTED,
++	WIFI_EVENT_ROAM_REQUESTED,
++	/* received beacon from AP (event enabled only in verbose mode) */
++	WIFI_EVENT_BEACON_RECEIVED,
++	/* firmware has triggered a roam scan (not g-scan) */
++	WIFI_EVENT_ROAM_SCAN_STARTED,
++	/* firmware has completed a roam scan (not g-scan) */
++	WIFI_EVENT_ROAM_SCAN_COMPLETE,
++	/* firmware has started searching for roam candidates (with reason =xx) */
++	WIFI_EVENT_ROAM_SEARCH_STARTED,
++	/* firmware has stopped searching for roam candidates (with reason =xx) */
++	WIFI_EVENT_ROAM_SEARCH_STOPPED,
++	WIFI_EVENT_UNUSED_0,
++	/* received channel switch anouncement from AP */
++	WIFI_EVENT_CHANNEL_SWITCH_ANOUNCEMENT,
++	/* fw start transmit eapol frame, with EAPOL index 1-4 */
++	WIFI_EVENT_FW_EAPOL_FRAME_TRANSMIT_START,
++	/* fw gives up eapol frame, with rate, success/failure and number retries */
++	WIFI_EVENT_FW_EAPOL_FRAME_TRANSMIT_STOP,
++	/* kernel queue EAPOL for transmission in driver with EAPOL index 1-4 */
++	WIFI_EVENT_DRIVER_EAPOL_FRAME_TRANSMIT_REQUESTED,
++	/*
++	 * with rate, regardless of the fact that EAPOL frame is accepted or
++	 * rejected by firmware
++	 */
++	WIFI_EVENT_FW_EAPOL_FRAME_RECEIVED,
++	WIFI_EVENT_UNUSED_1,
++	/* with rate, and eapol index, driver has received */
++	/* EAPOL frame and will queue it up to wpa_supplicant */
++	WIFI_EVENT_DRIVER_EAPOL_FRAME_RECEIVED,
++	/* with success/failure, parameters */
++	WIFI_EVENT_BLOCK_ACK_NEGOTIATION_COMPLETE,
++	WIFI_EVENT_BT_COEX_BT_SCO_START,
++	WIFI_EVENT_BT_COEX_BT_SCO_STOP,
++	/* for paging/scan etc..., when BT starts transmiting twice per BT slot */
++	WIFI_EVENT_BT_COEX_BT_SCAN_START,
++	WIFI_EVENT_BT_COEX_BT_SCAN_STOP,
++	WIFI_EVENT_BT_COEX_BT_HID_START,
++	WIFI_EVENT_BT_COEX_BT_HID_STOP,
++	/* firmware sends auth frame in roaming to next candidate */
++	WIFI_EVENT_ROAM_AUTH_STARTED,
++	/* firmware receive auth confirm from ap */
++	WIFI_EVENT_ROAM_AUTH_COMPLETE,
++	/* firmware sends assoc/reassoc frame in */
++	WIFI_EVENT_ROAM_ASSOC_STARTED,
++	/* firmware receive assoc/reassoc confirm from ap */
++	WIFI_EVENT_ROAM_ASSOC_COMPLETE
++};
++
++enum {
++	WIFI_TAG_VENDOR_SPECIFIC = 0, /* take a byte stream as parameter */
++	WIFI_TAG_BSSID, /* takes a 6 bytes MAC address as parameter */
++	WIFI_TAG_ADDR, /* takes a 6 bytes MAC address as parameter */
++	WIFI_TAG_SSID, /* takes a 32 bytes SSID address as parameter */
++	WIFI_TAG_STATUS, /* takes an integer as parameter */
++	WIFI_TAG_CHANNEL_SPEC, /* takes one or more wifi_channel_spec as parameter */
++	WIFI_TAG_WAKE_LOCK_EVENT, /* takes a wake_lock_event struct as parameter */
++	WIFI_TAG_ADDR1, /* takes a 6 bytes MAC address as parameter */
++	WIFI_TAG_ADDR2, /* takes a 6 bytes MAC address as parameter */
++	WIFI_TAG_ADDR3, /* takes a 6 bytes MAC address as parameter */
++	WIFI_TAG_ADDR4, /* takes a 6 bytes MAC address as parameter */
++	WIFI_TAG_TSF, /* take a 64 bits TSF value as parameter */
++	WIFI_TAG_IE,
++	/* take one or more specific 802.11 IEs parameter, IEs are in turn
++	 * indicated in TLV format as per 802.11 spec
++	 */
++	WIFI_TAG_INTERFACE, /* take interface name as parameter */
++	WIFI_TAG_REASON_CODE, /* take a reason code as per 802.11 as parameter */
++	WIFI_TAG_RATE_MBPS, /* take a wifi rate in 0.5 mbps */
++};
++
++/* NAN  events */
++typedef enum {
++	NAN_EVENT_INVALID = 0,
++	NAN_EVENT_CLUSTER_STARTED = 1,
++	NAN_EVENT_CLUSTER_JOINED = 2,
++	NAN_EVENT_CLUSTER_MERGED = 3,
++	NAN_EVENT_ROLE_CHANGED = 4,
++	NAN_EVENT_SCAN_COMPLETE = 5,
++	NAN_EVENT_STATUS_CHNG  = 6,
++	/* ADD new events before this line */
++	NAN_EVENT_MAX
++} nan_event_id_t;
++
++typedef struct {
++    uint16 tag;
++    uint16 len; /* length of value */
++    uint8 *value;
++} tlv_log;
++
++typedef struct per_packet_status_entry {
++    uint8 flags;
++    uint8 tid; /* transmit or received tid */
++    uint16 MCS; /* modulation and bandwidth */
++	/*
++	* TX: RSSI of ACK for that packet
++	* RX: RSSI of packet
++	*/
++    uint8 rssi;
++    uint8 num_retries; /* number of attempted retries */
++    uint16 last_transmit_rate; /* last transmit rate in .5 mbps */
++	 /* transmit/reeive sequence for that MPDU packet */
++    uint16 link_layer_transmit_sequence;
++	/*
++	* TX: firmware timestamp (us) when packet is queued within firmware buffer
++	* for SDIO/HSIC or into PCIe buffer
++	* RX : firmware receive timestamp
++	*/
++    uint64 firmware_entry_timestamp;
++	/*
++	* firmware timestamp (us) when packet start contending for the
++	* medium for the first time, at head of its AC queue,
++	* or as part of an MPDU or A-MPDU. This timestamp is not updated
++	* for each retry, only the first transmit attempt.
++	*/
++    uint64 start_contention_timestamp;
++	/*
++	* fimrware timestamp (us) when packet is successfully transmitted
++	* or aborted because it has exhausted its maximum number of retries
++	*/
++	uint64 transmit_success_timestamp;
++	/*
++	* packet data. The length of packet data is determined by the entry_size field of
++	* the wifi_ring_buffer_entry structure. It is expected that first bytes of the
++	* packet, or packet headers only (up to TCP or RTP/UDP headers) will be copied into the ring
++	*/
++    uint8 *data;
++} per_packet_status_entry_t;
++
++typedef struct log_conn_event {
++    uint16 event;
++    tlv_log *tlvs;
++	/*
++	* separate parameter structure per event to be provided and optional data
++	* the event_data is expected to include an official android part, with some
++	* parameter as transmit rate, num retries, num scan result found etc...
++	* as well, event_data can include a vendor proprietary part which is
++	* understood by the developer only.
++	*/
++} log_conn_event_t;
++
++/*
++ * Ring buffer name for power events ring. note that power event are extremely frequents
++ * and thus should be stored in their own ring/file so as not to clobber connectivity events
++ */
++
++typedef struct wake_lock_event {
++    uint32 status; /* 0 taken, 1 released */
++    uint32 reason; /* reason why this wake lock is taken */
++    char *name; /* null terminated */
++} wake_lock_event_t;
++
++typedef struct wifi_power_event {
++    uint16 event;
++    tlv_log *tlvs;
++} wifi_power_event_t;
++
++#define NAN_EVENT_VERSION 1
++typedef struct log_nan_event {
++    uint8 version;
++    uint8 pad;
++    uint16 event;
++    tlv_log *tlvs;
++} log_nan_event_t;
++
++/* entry type */
++enum {
++	DBG_RING_ENTRY_EVENT_TYPE = 1,
++	DBG_RING_ENTRY_PKT_TYPE,
++	DBG_RING_ENTRY_WAKE_LOCK_EVENT_TYPE,
++	DBG_RING_ENTRY_POWER_EVENT_TYPE,
++	DBG_RING_ENTRY_DATA_TYPE,
++	DBG_RING_ENTRY_NAN_EVENT_TYPE
++};
++
++typedef struct dhd_dbg_ring_entry {
++	uint16 len; /* payload length excluding the header */
++	uint8 flags;
++	uint8 type; /* Per ring specific */
++	uint64 timestamp; /* present if has_timestamp bit is set. */
++} dhd_dbg_ring_entry_t;
++
++#define DBG_RING_ENTRY_SIZE (sizeof(dhd_dbg_ring_entry_t))
++#define ENTRY_LENGTH(hdr) (hdr->len + DBG_RING_ENTRY_SIZE)
++typedef struct dhd_dbg_ring_status {
++	uint8 name[DBGRING_NAME_MAX];
++	uint32 flags;
++	int ring_id; /* unique integer representing the ring */
++	/* total memory size allocated for the buffer */
++	uint32 ring_buffer_byte_size;
++	uint32 verbose_level;
++	/* number of bytes that was written to the buffer by driver */
++	uint32 written_bytes;
++	/* number of bytes that was read from the buffer by user land */
++	uint32 read_bytes;
++	/* number of records that was read from the buffer by user land */
++	uint32 written_records;
++} dhd_dbg_ring_status_t;
++
++struct log_level_table {
++	int log_level;
++	uint16 tag;
++	char *desc;
++};
++
++typedef void (*dbg_pullreq_t)(void *os_priv, const int ring_id);
++
++typedef void (*dbg_urgent_noti_t) (dhd_pub_t *dhdp, const void *data, const uint32 len);
++
++#define DBG_EVENT_LOG(dhd, connect_state) \
++{											\
++	do {									\
++		uint16 state = connect_state;			\
++		dhd_os_push_push_ring_data(dhd, DHD_EVENT_RING_ID, &state, sizeof(state)); \
++	} while (0);						\
++}
++
++/* dhd_dbg functions */
++extern void dhd_dbg_trace_evnt_handler(dhd_pub_t *dhdp, void *event_data,
++		void *raw_event_ptr, uint datalen);
++extern int dhd_dbg_attach(dhd_pub_t *dhdp, dbg_pullreq_t os_pullreq,
++	dbg_urgent_noti_t os_urgent_notifier, void *os_priv);
++extern void dhd_dbg_detach(dhd_pub_t *dhdp);
++extern int dhd_dbg_start(dhd_pub_t *dhdp, bool start);
++extern int dhd_dbg_set_configuration(dhd_pub_t *dhdp, int ring_id,
++		int log_level, int flags, uint32 threshold);
++extern int dhd_dbg_get_ring_status(dhd_pub_t *dhdp, int ring_id,
++		dhd_dbg_ring_status_t *dbg_ring_status);
++extern int dhd_dbg_ring_push(dhd_pub_t *dhdp, int ring_id, dhd_dbg_ring_entry_t *hdr, void *data);
++extern int dhd_dbg_ring_pull(dhd_pub_t *dhdp, int ring_id, void *data, uint32 buf_len);
++extern int dhd_dbg_find_ring_id(dhd_pub_t *dhdp, char *ring_name);
++extern void *dhd_dbg_get_priv(dhd_pub_t *dhdp);
++extern int dhd_dbg_send_urgent_evt(dhd_pub_t *dhdp, const void *data, const uint32 len);
++
++/* os wrapper function */
++extern int dhd_os_dbg_attach(dhd_pub_t *dhdp);
++extern void dhd_os_dbg_detach(dhd_pub_t *dhdp);
++extern int dhd_os_dbg_register_callback(int ring_id,
++	void (*dbg_ring_sub_cb)(void *ctx, const int ring_id, const void *data,
++		const uint32 len, const dhd_dbg_ring_status_t dbg_ring_status));
++extern int dhd_os_dbg_register_urgent_notifier(dhd_pub_t *dhdp,
++	void (*urgent_noti)(void *ctx, const void *data, const uint32 len, const uint32 fw_len));
++
++extern int dhd_os_start_logging(dhd_pub_t *dhdp, char *ring_name, int log_level,
++		int flags, int time_intval, int threshold);
++extern int dhd_os_reset_logging(dhd_pub_t *dhdp);
++extern int dhd_os_suppress_logging(dhd_pub_t *dhdp, bool suppress);
++
++extern int dhd_os_get_ring_status(dhd_pub_t *dhdp, int ring_id,
++		dhd_dbg_ring_status_t *dbg_ring_status);
++extern int dhd_os_trigger_get_ring_data(dhd_pub_t *dhdp, char *ring_name);
++extern int dhd_os_push_push_ring_data(dhd_pub_t *dhdp, int ring_id, void *data, int32 data_len);
++extern int dhd_os_dbg_get_feature(dhd_pub_t *dhdp, int32 *features);
++
++#endif /* _dhd_debug_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_debug_linux.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_debug_linux.c
+new file mode 100644
+index 000000000..376aac018
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_debug_linux.c
+@@ -0,0 +1,418 @@
++/*
++ * DHD debugability Linux os layer
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * $Id: dhd_debug_linux.c 554441 2015-05-05 18:45:58Z $
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <bcmendian.h>
++#ifndef CUSTOMER_IPCAM
++#include <bcmpcie.h>
++#endif
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_dbg.h>
++#include <dhd_debug.h>
++
++#include <net/cfg80211.h>
++#include <wl_cfgvendor.h>
++
++typedef void (*dbg_ring_send_sub_t)(void *ctx, const int ring_id, const void *data,
++	const uint32 len, const dhd_dbg_ring_status_t ring_status);
++typedef void (*dbg_urgent_noti_sub_t)(void *ctx, const void *data,
++	const uint32 len, const uint32 fw_len);
++
++static dbg_ring_send_sub_t ring_send_sub_cb[DEBUG_RING_ID_MAX];
++static dbg_urgent_noti_sub_t urgent_noti_sub_cb;
++typedef struct dhd_dbg_os_ring_info {
++	dhd_pub_t *dhdp;
++	int ring_id;
++	int log_level;
++	unsigned long interval;
++	struct delayed_work work;
++	uint64 tsoffset;
++} linux_dbgring_info_t;
++
++struct log_level_table dhd_event_map[] = {
++	{1, WIFI_EVENT_DRIVER_EAPOL_FRAME_TRANSMIT_REQUESTED, "DRIVER EAPOL TX REQ"},
++	{1, WIFI_EVENT_DRIVER_EAPOL_FRAME_RECEIVED, "DRIVER EAPOL RX"},
++	{2, WIFI_EVENT_DRIVER_SCAN_REQUESTED, "SCAN_REQUESTED"},
++	{2, WIFI_EVENT_DRIVER_SCAN_COMPLETE, "SCAN COMPELETE"},
++	{3, WIFI_EVENT_DRIVER_SCAN_RESULT_FOUND, "SCAN RESULT FOUND"}
++};
++
++static void
++debug_data_send(dhd_pub_t *dhdp, int ring_id, const void *data, const uint32 len,
++	const dhd_dbg_ring_status_t ring_status)
++{
++	struct net_device *ndev;
++	dbg_ring_send_sub_t ring_sub_send;
++	ndev = dhd_linux_get_primary_netdev(dhdp);
++	if (!ndev)
++		return;
++	if (ring_send_sub_cb[ring_id]) {
++		ring_sub_send = ring_send_sub_cb[ring_id];
++		ring_sub_send(ndev, ring_id, data, len, ring_status);
++	}
++}
++
++static void
++dhd_os_dbg_urgent_notifier(dhd_pub_t *dhdp, const void *data, const uint32 len)
++{
++	struct net_device *ndev;
++	ndev = dhd_linux_get_primary_netdev(dhdp);
++	if (!ndev)
++		return;
++	if (urgent_noti_sub_cb) {
++		urgent_noti_sub_cb(ndev, data, len, dhdp->soc_ram_length);
++	}
++}
++
++static void
++dbg_ring_poll_worker(struct work_struct *work)
++{
++	struct delayed_work *d_work = to_delayed_work(work);
++	linux_dbgring_info_t *ring_info =
++		container_of(d_work, linux_dbgring_info_t, work);
++	dhd_pub_t *dhdp = ring_info->dhdp;
++	int ringid = ring_info->ring_id;
++	dhd_dbg_ring_status_t ring_status;
++	void *buf;
++	dhd_dbg_ring_entry_t *hdr;
++	uint32 buflen, rlen;
++
++	dhd_dbg_get_ring_status(dhdp, ringid, &ring_status);
++	if (ring_status.written_bytes > ring_status.read_bytes)
++		buflen = ring_status.written_bytes - ring_status.read_bytes;
++	else if (ring_status.written_bytes < ring_status.read_bytes)
++		buflen = 0xFFFFFFFF + ring_status.written_bytes -
++			ring_status.read_bytes;
++	else
++		goto exit;
++	buf = MALLOC(dhdp->osh, buflen);
++	if (!buf) {
++		DHD_ERROR(("%s failed to allocate read buf\n", __FUNCTION__));
++		return;
++	}
++	rlen = dhd_dbg_ring_pull(dhdp, ringid, buf, buflen);
++	hdr = (dhd_dbg_ring_entry_t *)buf;
++	while (rlen > 0) {
++		ring_status.read_bytes += ENTRY_LENGTH(hdr);
++		/* offset fw ts to host ts */
++		hdr->timestamp += ring_info->tsoffset;
++		debug_data_send(dhdp, ringid, hdr, ENTRY_LENGTH(hdr),
++				ring_status);
++		rlen -= ENTRY_LENGTH(hdr);
++		hdr = (dhd_dbg_ring_entry_t *)((void *)hdr + ENTRY_LENGTH(hdr));
++	}
++	MFREE(dhdp->osh, buf, buflen);
++
++	if (!ring_info->interval)
++		return;
++	dhd_dbg_get_ring_status(dhdp, ring_info->ring_id, &ring_status);
++
++exit:
++	if (ring_info->interval) {
++		/* retrigger the work at same interval */
++		if (ring_status.written_bytes == ring_status.read_bytes)
++			schedule_delayed_work(d_work, ring_info->interval);
++		else
++			schedule_delayed_work(d_work, 0);
++	}
++
++	return;
++}
++
++int
++dhd_os_dbg_register_callback(int ring_id, dbg_ring_send_sub_t callback)
++{
++	if (!VALID_RING(ring_id))
++		return BCME_RANGE;
++
++	ring_send_sub_cb[ring_id] = callback;
++	return BCME_OK;
++}
++
++int
++dhd_os_dbg_register_urgent_notifier(dhd_pub_t *dhdp, dbg_urgent_noti_sub_t urgent_noti_sub)
++{
++	if (!dhdp || !urgent_noti_sub)
++		return BCME_BADARG;
++	urgent_noti_sub_cb = urgent_noti_sub;
++
++	return BCME_OK;
++}
++
++int
++dhd_os_start_logging(dhd_pub_t *dhdp, char *ring_name, int log_level,
++	int flags, int time_intval, int threshold)
++{
++	int ret = BCME_OK;
++	int ring_id;
++	linux_dbgring_info_t *os_priv, *ring_info;
++	uint32 ms;
++
++	ring_id = dhd_dbg_find_ring_id(dhdp, ring_name);
++	if (!VALID_RING(ring_id))
++		return BCME_UNSUPPORTED;
++
++	DHD_DBGIF(("%s , log_level : %d, time_intval : %d, threshod %d Bytes\n",
++		__FUNCTION__, log_level, time_intval, threshold));
++
++	/* change the configuration */
++	ret = dhd_dbg_set_configuration(dhdp, ring_id, log_level, flags, threshold);
++	if (ret) {
++		DHD_ERROR(("dhd_set_configuration is failed : %d\n", ret));
++		return ret;
++	}
++
++	os_priv = dhd_dbg_get_priv(dhdp);
++	if (!os_priv)
++		return BCME_ERROR;
++	ring_info = &os_priv[ring_id];
++	ring_info->log_level = log_level;
++	if (ring_id == FW_VERBOSE_RING_ID || ring_id == FW_EVENT_RING_ID) {
++		ring_info->tsoffset = local_clock();
++		if (dhd_wl_ioctl_get_intiovar(dhdp, "rte_timesync", &ms, WLC_GET_VAR,
++				FALSE, 0))
++			DHD_ERROR(("%s rte_timesync failed\n", __FUNCTION__));
++		do_div(ring_info->tsoffset, 1000000);
++		ring_info->tsoffset -= ms;
++	}
++	if (time_intval == 0 || log_level == 0) {
++		ring_info->interval = 0;
++		cancel_delayed_work_sync(&ring_info->work);
++	} else {
++		ring_info->interval = msecs_to_jiffies(time_intval * MSEC_PER_SEC);
++		schedule_delayed_work(&ring_info->work, ring_info->interval);
++	}
++
++	return ret;
++}
++
++int
++dhd_os_reset_logging(dhd_pub_t *dhdp)
++{
++	int ret = BCME_OK;
++	int ring_id;
++	linux_dbgring_info_t *os_priv, *ring_info;
++
++	os_priv = dhd_dbg_get_priv(dhdp);
++	if (!os_priv)
++		return BCME_ERROR;
++
++	/* Stop all rings */
++	for (ring_id = DEBUG_RING_ID_INVALID + 1; ring_id < DEBUG_RING_ID_MAX; ring_id++) {
++		DHD_DBGIF(("%s: Stop ring buffer %d\n", __FUNCTION__, ring_id));
++
++		ring_info = &os_priv[ring_id];
++		/* cancel any pending work */
++		cancel_delayed_work_sync(&ring_info->work);
++		/* log level zero makes stop logging on that ring */
++		ring_info->log_level = 0;
++		ring_info->interval = 0;
++		/* change the configuration */
++		ret = dhd_dbg_set_configuration(dhdp, ring_id, 0, 0, 0);
++		if (ret) {
++			DHD_ERROR(("dhd_set_configuration is failed : %d\n", ret));
++			return ret;
++		}
++	}
++	return ret;
++}
++
++#define SUPPRESS_LOG_LEVEL 1
++int
++dhd_os_suppress_logging(dhd_pub_t *dhdp, bool suppress)
++{
++	int ret = BCME_OK;
++	int max_log_level;
++	int enable = (suppress) ? 0 : 1;
++	linux_dbgring_info_t *os_priv;
++
++	os_priv = dhd_dbg_get_priv(dhdp);
++	if (!os_priv)
++		return BCME_ERROR;
++
++	max_log_level = MAX(os_priv[FW_VERBOSE_RING_ID].log_level,
++		os_priv[FW_EVENT_RING_ID].log_level);
++	if (max_log_level == SUPPRESS_LOG_LEVEL) {
++		/* suppress the logging in FW not to wake up host while device in suspend mode */
++		ret = dhd_iovar(dhdp, 0, "logtrace", (char *)&enable, sizeof(enable), NULL, 0,
++			TRUE);
++		if (ret < 0 && (ret != BCME_UNSUPPORTED)) {
++			DHD_ERROR(("logtrace is failed : %d\n", ret));
++		}
++	}
++
++	return ret;
++}
++
++int
++dhd_os_get_ring_status(dhd_pub_t *dhdp, int ring_id, dhd_dbg_ring_status_t *dbg_ring_status)
++{
++	return dhd_dbg_get_ring_status(dhdp, ring_id, dbg_ring_status);
++}
++
++int
++dhd_os_trigger_get_ring_data(dhd_pub_t *dhdp, char *ring_name)
++{
++	int ret = BCME_OK;
++	int ring_id;
++	linux_dbgring_info_t *os_priv, *ring_info;
++	ring_id = dhd_dbg_find_ring_id(dhdp, ring_name);
++	if (!VALID_RING(ring_id))
++		return BCME_UNSUPPORTED;
++	os_priv = dhd_dbg_get_priv(dhdp);
++	if (os_priv) {
++		ring_info = &os_priv[ring_id];
++		if (ring_info->interval) {
++			cancel_delayed_work_sync(&ring_info->work);
++		}
++		schedule_delayed_work(&ring_info->work, 0);
++	} else {
++		DHD_ERROR(("%s : os_priv is NULL\n", __FUNCTION__));
++		ret = BCME_ERROR;
++	}
++	return ret;
++}
++
++int
++dhd_os_push_push_ring_data(dhd_pub_t *dhdp, int ring_id, void *data, int32 data_len)
++{
++	int ret = BCME_OK, i;
++	dhd_dbg_ring_entry_t msg_hdr;
++	log_conn_event_t event_data;
++	linux_dbgring_info_t *os_priv, *ring_info = NULL;
++
++	if (!VALID_RING(ring_id))
++		return BCME_UNSUPPORTED;
++
++	os_priv = dhd_dbg_get_priv(dhdp);
++	if (!os_priv)
++		return BCME_UNSUPPORTED;
++
++	ring_info = &os_priv[ring_id];
++
++	memset(&msg_hdr, 0, sizeof(dhd_dbg_ring_entry_t));
++
++	if (ring_id == DHD_EVENT_RING_ID) {
++		msg_hdr.type = DBG_RING_ENTRY_EVENT_TYPE;
++		msg_hdr.flags |= DBG_RING_ENTRY_FLAGS_HAS_TIMESTAMP;
++		msg_hdr.flags |= DBG_RING_ENTRY_FLAGS_HAS_BINARY;
++		msg_hdr.timestamp = local_clock();
++		/* convert to ms */
++		do_div(msg_hdr.timestamp, 1000000);
++		msg_hdr.len = sizeof(event_data);
++		event_data.event = *((uint16 *)(data));
++		/* filter the event for higher log level with current log level */
++		for (i = 0; i < ARRAYSIZE(dhd_event_map); i++) {
++			if ((dhd_event_map[i].tag == event_data.event) &&
++				dhd_event_map[i].log_level > ring_info->log_level) {
++				return ret;
++			}
++		}
++	}
++	ret = dhd_dbg_ring_push(dhdp, ring_id, &msg_hdr, &event_data);
++	if (ret) {
++		DHD_ERROR(("%s : failed to push data into the ring (%d) with ret(%d)\n",
++			__FUNCTION__, ring_id, ret));
++	}
++
++	return ret;
++}
++
++int
++dhd_os_dbg_get_feature(dhd_pub_t *dhdp, int32 *features)
++{
++	int ret = BCME_OK;
++	*features = 0;
++	*features |= DBG_MEMORY_DUMP_SUPPORTED;
++	if (FW_SUPPORTED(dhdp, logtrace)) {
++		*features |= DBG_CONNECT_EVENT_SUPPORTED;
++		*features |= DBG_VERBOSE_LOG_SUPPORTED;
++	}
++	if (FW_SUPPORTED(dhdp, hchk)) {
++		*features |= DBG_HEALTH_CHECK_SUPPORTED;
++	}
++	return ret;
++}
++
++static void
++dhd_os_dbg_pullreq(void *os_priv, int ring_id)
++{
++	linux_dbgring_info_t *ring_info;
++
++	ring_info = &((linux_dbgring_info_t *)os_priv)[ring_id];
++	if (ring_info->interval != 0)
++		schedule_delayed_work(&ring_info->work, 0);
++}
++
++int
++dhd_os_dbg_attach(dhd_pub_t *dhdp)
++{
++	int ret = BCME_OK;
++	linux_dbgring_info_t *os_priv, *ring_info;
++	int ring_id;
++
++	/* os_dbg data */
++	os_priv = MALLOCZ(dhdp->osh, sizeof(*os_priv) * DEBUG_RING_ID_MAX);
++	if (!os_priv)
++		return BCME_NOMEM;
++
++	for (ring_id = DEBUG_RING_ID_INVALID + 1; ring_id < DEBUG_RING_ID_MAX;
++	     ring_id++) {
++		ring_info = &os_priv[ring_id];
++		INIT_DELAYED_WORK(&ring_info->work, dbg_ring_poll_worker);
++		ring_info->dhdp = dhdp;
++		ring_info->ring_id = ring_id;
++	}
++
++	ret = dhd_dbg_attach(dhdp, dhd_os_dbg_pullreq, dhd_os_dbg_urgent_notifier, os_priv);
++	if (ret)
++		MFREE(dhdp->osh, os_priv, sizeof(*os_priv) * DEBUG_RING_ID_MAX);
++
++	return ret;
++}
++
++void
++dhd_os_dbg_detach(dhd_pub_t *dhdp)
++{
++	linux_dbgring_info_t *os_priv, *ring_info;
++	int ring_id;
++	/* free os_dbg data */
++	os_priv = dhd_dbg_get_priv(dhdp);
++	/* abort pending any job */
++	for (ring_id = DEBUG_RING_ID_INVALID + 1; ring_id < DEBUG_RING_ID_MAX; ring_id++) {
++		ring_info = &os_priv[ring_id];
++		if (ring_info->interval) {
++			ring_info->interval = 0;
++			cancel_delayed_work_sync(&ring_info->work);
++		}
++	}
++	MFREE(dhdp->osh, os_priv, sizeof(*os_priv) * DEBUG_RING_ID_MAX);
++
++	return dhd_dbg_detach(dhdp);
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_flowring.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_flowring.c
+new file mode 100644
+index 000000000..dff315aba
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_flowring.c
+@@ -0,0 +1,996 @@
++/**
++ * @file Broadcom Dongle Host Driver (DHD), Flow ring specific code at top level
++ *
++ * Flow rings are transmit traffic (=propagating towards antenna) related entities
++ *
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_flowrings.c jaganlv $
++ */
++
++
++#include <typedefs.h>
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <bcmdevs.h>
++
++#include <proto/ethernet.h>
++#include <proto/bcmevent.h>
++#include <dngl_stats.h>
++
++#include <dhd.h>
++
++#include <dhd_flowring.h>
++#include <dhd_bus.h>
++#include <dhd_proto.h>
++#include <dhd_dbg.h>
++#include <proto/802.1d.h>
++#include <pcie_core.h>
++#include <bcmmsgbuf.h>
++#include <dhd_pcie.h>
++
++
++static INLINE int dhd_flow_queue_throttle(flow_queue_t *queue);
++
++static INLINE uint16 dhd_flowid_find(dhd_pub_t *dhdp, uint8 ifindex,
++                                     uint8 prio, char *sa, char *da);
++
++static INLINE uint16 dhd_flowid_alloc(dhd_pub_t *dhdp, uint8 ifindex,
++                                      uint8 prio, char *sa, char *da);
++
++static INLINE int dhd_flowid_lookup(dhd_pub_t *dhdp, uint8 ifindex,
++                                uint8 prio, char *sa, char *da, uint16 *flowid);
++int BCMFASTPATH dhd_flow_queue_overflow(flow_queue_t *queue, void *pkt);
++
++#define FLOW_QUEUE_PKT_NEXT(p)          PKTLINK(p)
++#define FLOW_QUEUE_PKT_SETNEXT(p, x)    PKTSETLINK((p), (x))
++
++#ifdef DHD_LOSSLESS_ROAMING
++const uint8 prio2ac[8] = { 0, 1, 1, 0, 2, 2, 3, 7 };
++#else
++const uint8 prio2ac[8] = { 0, 1, 1, 0, 2, 2, 3, 3 };
++#endif
++const uint8 prio2tid[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
++
++/** Queue overflow throttle. Return value: TRUE if throttle needs to be applied */
++static INLINE int
++dhd_flow_queue_throttle(flow_queue_t *queue)
++{
++	return DHD_FLOW_QUEUE_FULL(queue);
++}
++
++int BCMFASTPATH
++dhd_flow_queue_overflow(flow_queue_t *queue, void *pkt)
++{
++	return BCME_NORESOURCE;
++}
++
++/** Returns flow ring given a flowid */
++flow_ring_node_t *
++dhd_flow_ring_node(dhd_pub_t *dhdp, uint16 flowid)
++{
++	flow_ring_node_t * flow_ring_node;
++
++	ASSERT(dhdp != (dhd_pub_t*)NULL);
++	ASSERT(flowid < dhdp->num_flow_rings);
++
++	flow_ring_node = &(((flow_ring_node_t*)(dhdp->flow_ring_table))[flowid]);
++
++	ASSERT(flow_ring_node->flowid == flowid);
++	return flow_ring_node;
++}
++
++/** Returns 'backup' queue given a flowid */
++flow_queue_t *
++dhd_flow_queue(dhd_pub_t *dhdp, uint16 flowid)
++{
++	flow_ring_node_t * flow_ring_node;
++
++	flow_ring_node = dhd_flow_ring_node(dhdp, flowid);
++	return &flow_ring_node->queue;
++}
++
++/* Flow ring's queue management functions */
++
++/** Reinitialize a flow ring's queue. */
++void
++dhd_flow_queue_reinit(dhd_pub_t *dhdp, flow_queue_t *queue, int max)
++{
++	ASSERT((queue != NULL) && (max > 0));
++
++	queue->head = queue->tail = NULL;
++	queue->len = 0;
++
++	/* Set queue's threshold and queue's parent cummulative length counter */
++	ASSERT(max > 1);
++	DHD_FLOW_QUEUE_SET_MAX(queue, max);
++	DHD_FLOW_QUEUE_SET_THRESHOLD(queue, max);
++	DHD_FLOW_QUEUE_SET_CLEN(queue, &dhdp->cumm_ctr);
++	DHD_FLOW_QUEUE_SET_L2CLEN(queue, &dhdp->l2cumm_ctr);
++
++	queue->failures = 0U;
++	queue->cb = &dhd_flow_queue_overflow;
++}
++
++/** Initialize a flow ring's queue, called on driver initialization. */
++void
++dhd_flow_queue_init(dhd_pub_t *dhdp, flow_queue_t *queue, int max)
++{
++	ASSERT((queue != NULL) && (max > 0));
++
++	dll_init(&queue->list);
++	dhd_flow_queue_reinit(dhdp, queue, max);
++}
++
++/** Register an enqueue overflow callback handler */
++void
++dhd_flow_queue_register(flow_queue_t *queue, flow_queue_cb_t cb)
++{
++	ASSERT(queue != NULL);
++	queue->cb = cb;
++}
++
++/**
++ * Enqueue an 802.3 packet at the back of a flow ring's queue. From there, it will travel later on
++ * to the flow ring itself.
++ */
++int BCMFASTPATH
++dhd_flow_queue_enqueue(dhd_pub_t *dhdp, flow_queue_t *queue, void *pkt)
++{
++	int ret = BCME_OK;
++
++	ASSERT(queue != NULL);
++
++	if (dhd_flow_queue_throttle(queue)) {
++		queue->failures++;
++		ret = (*queue->cb)(queue, pkt);
++		goto done;
++	}
++
++	if (queue->head) {
++		FLOW_QUEUE_PKT_SETNEXT(queue->tail, pkt);
++	} else {
++		queue->head = pkt;
++	}
++
++	FLOW_QUEUE_PKT_SETNEXT(pkt, NULL);
++
++	queue->tail = pkt; /* at tail */
++
++	queue->len++;
++	/* increment parent's cummulative length */
++	DHD_CUMM_CTR_INCR(DHD_FLOW_QUEUE_CLEN_PTR(queue));
++	/* increment grandparent's cummulative length */
++	DHD_CUMM_CTR_INCR(DHD_FLOW_QUEUE_L2CLEN_PTR(queue));
++
++done:
++	return ret;
++}
++
++/** Dequeue an 802.3 packet from a flow ring's queue, from head (FIFO) */
++void * BCMFASTPATH
++dhd_flow_queue_dequeue(dhd_pub_t *dhdp, flow_queue_t *queue)
++{
++	void * pkt;
++
++	ASSERT(queue != NULL);
++
++	pkt = queue->head; /* from head */
++
++	if (pkt == NULL) {
++		ASSERT((queue->len == 0) && (queue->tail == NULL));
++		goto done;
++	}
++
++	queue->head = FLOW_QUEUE_PKT_NEXT(pkt);
++	if (queue->head == NULL)
++		queue->tail = NULL;
++
++	queue->len--;
++	/* decrement parent's cummulative length */
++	DHD_CUMM_CTR_DECR(DHD_FLOW_QUEUE_CLEN_PTR(queue));
++	/* decrement grandparent's cummulative length */
++	DHD_CUMM_CTR_DECR(DHD_FLOW_QUEUE_L2CLEN_PTR(queue));
++
++	FLOW_QUEUE_PKT_SETNEXT(pkt, NULL); /* dettach packet from queue */
++
++done:
++	return pkt;
++}
++
++/** Reinsert a dequeued 802.3 packet back at the head */
++void BCMFASTPATH
++dhd_flow_queue_reinsert(dhd_pub_t *dhdp, flow_queue_t *queue, void *pkt)
++{
++	if (queue->head == NULL) {
++		queue->tail = pkt;
++	}
++
++	FLOW_QUEUE_PKT_SETNEXT(pkt, queue->head);
++	queue->head = pkt;
++	queue->len++;
++	/* increment parent's cummulative length */
++	DHD_CUMM_CTR_INCR(DHD_FLOW_QUEUE_CLEN_PTR(queue));
++	/* increment grandparent's cummulative length */
++	DHD_CUMM_CTR_INCR(DHD_FLOW_QUEUE_L2CLEN_PTR(queue));
++}
++
++/** Fetch the backup queue for a flowring, and assign flow control thresholds */
++void
++dhd_flow_ring_config_thresholds(dhd_pub_t *dhdp, uint16 flowid,
++                     int queue_budget, int cumm_threshold, void *cumm_ctr,
++                     int l2cumm_threshold, void *l2cumm_ctr)
++{
++	flow_queue_t * queue;
++
++	ASSERT(dhdp != (dhd_pub_t*)NULL);
++	ASSERT(queue_budget > 1);
++	ASSERT(cumm_threshold > 1);
++	ASSERT(cumm_ctr != (void*)NULL);
++	ASSERT(l2cumm_threshold > 1);
++	ASSERT(l2cumm_ctr != (void*)NULL);
++
++	queue = dhd_flow_queue(dhdp, flowid);
++
++	DHD_FLOW_QUEUE_SET_MAX(queue, queue_budget); /* Max queue length */
++
++	/* Set the queue's parent threshold and cummulative counter */
++	DHD_FLOW_QUEUE_SET_THRESHOLD(queue, cumm_threshold);
++	DHD_FLOW_QUEUE_SET_CLEN(queue, cumm_ctr);
++
++	/* Set the queue's grandparent threshold and cummulative counter */
++	DHD_FLOW_QUEUE_SET_L2THRESHOLD(queue, l2cumm_threshold);
++	DHD_FLOW_QUEUE_SET_L2CLEN(queue, l2cumm_ctr);
++}
++
++/** Initializes data structures of multiple flow rings */
++int
++dhd_flow_rings_init(dhd_pub_t *dhdp, uint32 num_flow_rings)
++{
++	uint32 idx;
++	uint32 flow_ring_table_sz;
++	uint32 if_flow_lkup_sz = 0;
++	void * flowid_allocator;
++	flow_ring_table_t *flow_ring_table = NULL;
++	if_flow_lkup_t *if_flow_lkup = NULL;
++	void *lock = NULL;
++	void *list_lock = NULL;
++	unsigned long flags;
++
++	DHD_INFO(("%s\n", __FUNCTION__));
++
++	/* Construct a 16bit flowid allocator */
++	flowid_allocator = id16_map_init(dhdp->osh,
++	                       num_flow_rings - FLOW_RING_COMMON, FLOWID_RESERVED);
++	if (flowid_allocator == NULL) {
++		DHD_ERROR(("%s: flowid allocator init failure\n", __FUNCTION__));
++		return BCME_NOMEM;
++	}
++
++	/* Allocate a flow ring table, comprising of requested number of rings */
++	flow_ring_table_sz = (num_flow_rings * sizeof(flow_ring_node_t));
++	flow_ring_table = (flow_ring_table_t *)MALLOCZ(dhdp->osh, flow_ring_table_sz);
++	if (flow_ring_table == NULL) {
++		DHD_ERROR(("%s: flow ring table alloc failure\n", __FUNCTION__));
++		goto fail;
++	}
++
++	/* Initialize flow ring table state */
++	DHD_CUMM_CTR_INIT(&dhdp->cumm_ctr);
++	DHD_CUMM_CTR_INIT(&dhdp->l2cumm_ctr);
++	bzero((uchar *)flow_ring_table, flow_ring_table_sz);
++	for (idx = 0; idx < num_flow_rings; idx++) {
++		flow_ring_table[idx].status = FLOW_RING_STATUS_CLOSED;
++		flow_ring_table[idx].flowid = (uint16)idx;
++		flow_ring_table[idx].lock = dhd_os_spin_lock_init(dhdp->osh);
++		if (flow_ring_table[idx].lock == NULL) {
++			DHD_ERROR(("%s: Failed to init spinlock for queue!\n", __FUNCTION__));
++			goto fail;
++		}
++
++		dll_init(&flow_ring_table[idx].list);
++
++		/* Initialize the per flow ring backup queue */
++		dhd_flow_queue_init(dhdp, &flow_ring_table[idx].queue,
++		                    FLOW_RING_QUEUE_THRESHOLD);
++	}
++
++	/* Allocate per interface hash table (for fast lookup from interface to flow ring) */
++	if_flow_lkup_sz = sizeof(if_flow_lkup_t) * DHD_MAX_IFS;
++	if_flow_lkup = (if_flow_lkup_t *)DHD_OS_PREALLOC(dhdp,
++		DHD_PREALLOC_IF_FLOW_LKUP, if_flow_lkup_sz);
++	if (if_flow_lkup == NULL) {
++		DHD_ERROR(("%s: if flow lkup alloc failure\n", __FUNCTION__));
++		goto fail;
++	}
++
++	/* Initialize per interface hash table */
++	for (idx = 0; idx < DHD_MAX_IFS; idx++) {
++		int hash_ix;
++		if_flow_lkup[idx].status = 0;
++		if_flow_lkup[idx].role = 0;
++		for (hash_ix = 0; hash_ix < DHD_FLOWRING_HASH_SIZE; hash_ix++)
++			if_flow_lkup[idx].fl_hash[hash_ix] = NULL;
++	}
++
++	lock = dhd_os_spin_lock_init(dhdp->osh);
++	if (lock == NULL)
++		goto fail;
++
++	list_lock = dhd_os_spin_lock_init(dhdp->osh);
++	if (list_lock == NULL)
++		goto lock_fail;
++
++	dhdp->flow_prio_map_type = DHD_FLOW_PRIO_AC_MAP;
++	bcopy(prio2ac, dhdp->flow_prio_map, sizeof(uint8) * NUMPRIO);
++#ifdef DHD_LOSSLESS_ROAMING
++	dhdp->dequeue_prec_map = ALLPRIO;
++#endif
++	/* Now populate into dhd pub */
++	DHD_FLOWID_LOCK(lock, flags);
++	dhdp->num_flow_rings = num_flow_rings;
++	dhdp->flowid_allocator = (void *)flowid_allocator;
++	dhdp->flow_ring_table = (void *)flow_ring_table;
++	dhdp->if_flow_lkup = (void *)if_flow_lkup;
++	dhdp->flowid_lock = lock;
++	dhdp->flow_rings_inited = TRUE;
++	dhdp->flowring_list_lock = list_lock;
++	DHD_FLOWID_UNLOCK(lock, flags);
++
++	DHD_INFO(("%s done\n", __FUNCTION__));
++	return BCME_OK;
++
++lock_fail:
++	/* deinit the spinlock */
++	dhd_os_spin_lock_deinit(dhdp->osh, lock);
++
++fail:
++	/* Destruct the per interface flow lkup table */
++	if (if_flow_lkup != NULL) {
++		DHD_OS_PREFREE(dhdp, if_flow_lkup, if_flow_lkup_sz);
++	}
++	if (flow_ring_table != NULL) {
++		for (idx = 0; idx < num_flow_rings; idx++) {
++			if (flow_ring_table[idx].lock != NULL)
++				dhd_os_spin_lock_deinit(dhdp->osh, flow_ring_table[idx].lock);
++		}
++		MFREE(dhdp->osh, flow_ring_table, flow_ring_table_sz);
++	}
++	id16_map_fini(dhdp->osh, flowid_allocator);
++
++	return BCME_NOMEM;
++}
++
++/** Deinit Flow Ring specific data structures */
++void dhd_flow_rings_deinit(dhd_pub_t *dhdp)
++{
++	uint16 idx;
++	uint32 flow_ring_table_sz;
++	uint32 if_flow_lkup_sz;
++	flow_ring_table_t *flow_ring_table;
++	unsigned long flags;
++	void *lock;
++
++	DHD_INFO(("dhd_flow_rings_deinit\n"));
++
++	if (!(dhdp->flow_rings_inited)) {
++		DHD_ERROR(("dhd_flow_rings not initialized!\n"));
++		return;
++	}
++
++	if (dhdp->flow_ring_table != NULL) {
++
++		ASSERT(dhdp->num_flow_rings > 0);
++
++		DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++		flow_ring_table = (flow_ring_table_t *)dhdp->flow_ring_table;
++		dhdp->flow_ring_table = NULL;
++		DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++		for (idx = 0; idx < dhdp->num_flow_rings; idx++) {
++			if (flow_ring_table[idx].active) {
++				dhd_bus_clean_flow_ring(dhdp->bus, &flow_ring_table[idx]);
++			}
++			ASSERT(DHD_FLOW_QUEUE_EMPTY(&flow_ring_table[idx].queue));
++
++			/* Deinit flow ring queue locks before destroying flow ring table */
++			if (flow_ring_table[idx].lock != NULL) {
++				dhd_os_spin_lock_deinit(dhdp->osh, flow_ring_table[idx].lock);
++			}
++			flow_ring_table[idx].lock = NULL;
++
++		}
++
++		/* Destruct the flow ring table */
++		flow_ring_table_sz = dhdp->num_flow_rings * sizeof(flow_ring_table_t);
++		MFREE(dhdp->osh, flow_ring_table, flow_ring_table_sz);
++	}
++
++	DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++
++	/* Destruct the per interface flow lkup table */
++	if (dhdp->if_flow_lkup != NULL) {
++		if_flow_lkup_sz = sizeof(if_flow_lkup_t) * DHD_MAX_IFS;
++		bzero((uchar *)dhdp->if_flow_lkup, if_flow_lkup_sz);
++		DHD_OS_PREFREE(dhdp, dhdp->if_flow_lkup, if_flow_lkup_sz);
++		dhdp->if_flow_lkup = NULL;
++	}
++
++	/* Destruct the flowid allocator */
++	if (dhdp->flowid_allocator != NULL)
++		dhdp->flowid_allocator = id16_map_fini(dhdp->osh, dhdp->flowid_allocator);
++
++	dhdp->num_flow_rings = 0U;
++	bzero(dhdp->flow_prio_map, sizeof(uint8) * NUMPRIO);
++
++	lock = dhdp->flowid_lock;
++	dhdp->flowid_lock = NULL;
++
++	if (lock) {
++		DHD_FLOWID_UNLOCK(lock, flags);
++		dhd_os_spin_lock_deinit(dhdp->osh, lock);
++	}
++
++	dhd_os_spin_lock_deinit(dhdp->osh, dhdp->flowring_list_lock);
++	dhdp->flowring_list_lock = NULL;
++
++	ASSERT(dhdp->if_flow_lkup == NULL);
++	ASSERT(dhdp->flowid_allocator == NULL);
++	ASSERT(dhdp->flow_ring_table == NULL);
++	dhdp->flow_rings_inited = FALSE;
++}
++
++/** Uses hash table to quickly map from ifindex to a flow ring 'role' (STA/AP) */
++uint8
++dhd_flow_rings_ifindex2role(dhd_pub_t *dhdp, uint8 ifindex)
++{
++	if_flow_lkup_t *if_flow_lkup = (if_flow_lkup_t *)dhdp->if_flow_lkup;
++	ASSERT(if_flow_lkup);
++	return if_flow_lkup[ifindex].role;
++}
++
++#ifdef WLTDLS
++bool is_tdls_destination(dhd_pub_t *dhdp, uint8 *da)
++{
++	tdls_peer_node_t *cur = dhdp->peer_tbl.node;
++	while (cur != NULL) {
++		if (!memcmp(da, cur->addr, ETHER_ADDR_LEN)) {
++			return TRUE;
++		}
++		cur = cur->next;
++	}
++	return FALSE;
++}
++#endif /* WLTDLS */
++
++/** Uses hash table to quickly map from ifindex+prio+da to a flow ring id */
++static INLINE uint16
++dhd_flowid_find(dhd_pub_t *dhdp, uint8 ifindex, uint8 prio, char *sa, char *da)
++{
++	int hash;
++	bool ismcast = FALSE;
++	flow_hash_info_t *cur;
++	if_flow_lkup_t *if_flow_lkup;
++	unsigned long flags;
++
++	DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++	if_flow_lkup = (if_flow_lkup_t *)dhdp->if_flow_lkup;
++
++	ASSERT(if_flow_lkup);
++
++	if ((if_flow_lkup[ifindex].role == WLC_E_IF_ROLE_STA) ||
++			(if_flow_lkup[ifindex].role == WLC_E_IF_ROLE_WDS)) {
++#ifdef WLTDLS
++		if (dhdp->peer_tbl.tdls_peer_count && !(ETHER_ISMULTI(da)) &&
++			is_tdls_destination(dhdp, da)) {
++			hash = DHD_FLOWRING_HASHINDEX(da, prio);
++			cur = if_flow_lkup[ifindex].fl_hash[hash];
++			while (cur != NULL) {
++				if (!memcmp(cur->flow_info.da, da, ETHER_ADDR_LEN)) {
++					DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++					return cur->flowid;
++				}
++				cur = cur->next;
++			}
++			DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++			return FLOWID_INVALID;
++		}
++#endif /* WLTDLS */
++		/* For STA non TDLS dest and WDS dest flow ring id is mapped based on prio only */
++		cur = if_flow_lkup[ifindex].fl_hash[prio];
++		if (cur) {
++			DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++			return cur->flowid;
++		}
++	} else {
++
++		if (ETHER_ISMULTI(da)) {
++			ismcast = TRUE;
++			hash = 0;
++		} else {
++			hash = DHD_FLOWRING_HASHINDEX(da, prio);
++		}
++
++		cur = if_flow_lkup[ifindex].fl_hash[hash];
++
++		while (cur) {
++			if ((ismcast && ETHER_ISMULTI(cur->flow_info.da)) ||
++				(!memcmp(cur->flow_info.da, da, ETHER_ADDR_LEN) &&
++				(cur->flow_info.tid == prio))) {
++				DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++				return cur->flowid;
++			}
++			cur = cur->next;
++		}
++	}
++	DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++
++	DHD_INFO(("%s: cannot find flowid\n", __FUNCTION__));
++	return FLOWID_INVALID;
++} /* dhd_flowid_find */
++
++/** Create unique Flow ID, called when a flow ring is created. */
++static INLINE uint16
++dhd_flowid_alloc(dhd_pub_t *dhdp, uint8 ifindex, uint8 prio, char *sa, char *da)
++{
++	flow_hash_info_t *fl_hash_node, *cur;
++	if_flow_lkup_t *if_flow_lkup;
++	int hash;
++	uint16 flowid;
++	unsigned long flags;
++
++	fl_hash_node = (flow_hash_info_t *) MALLOC(dhdp->osh, sizeof(flow_hash_info_t));
++	memcpy(fl_hash_node->flow_info.da, da, sizeof(fl_hash_node->flow_info.da));
++
++	DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++	ASSERT(dhdp->flowid_allocator != NULL);
++	flowid = id16_map_alloc(dhdp->flowid_allocator);
++	DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++
++	if (flowid == FLOWID_INVALID) {
++		MFREE(dhdp->osh, fl_hash_node,  sizeof(flow_hash_info_t));
++		DHD_ERROR(("%s: cannot get free flowid \n", __FUNCTION__));
++		return FLOWID_INVALID;
++	}
++
++	fl_hash_node->flowid = flowid;
++	fl_hash_node->flow_info.tid = prio;
++	fl_hash_node->flow_info.ifindex = ifindex;
++	fl_hash_node->next = NULL;
++
++	DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++	if_flow_lkup = (if_flow_lkup_t *)dhdp->if_flow_lkup;
++
++	if ((if_flow_lkup[ifindex].role == WLC_E_IF_ROLE_STA) ||
++			(if_flow_lkup[ifindex].role == WLC_E_IF_ROLE_WDS)) {
++		/* For STA non TDLS dest and WDS dest we allocate entry based on prio only */
++#ifdef WLTDLS
++		if (dhdp->peer_tbl.tdls_peer_count &&
++			(is_tdls_destination(dhdp, da))) {
++			hash = DHD_FLOWRING_HASHINDEX(da, prio);
++			cur = if_flow_lkup[ifindex].fl_hash[hash];
++			if (cur) {
++				while (cur->next) {
++					cur = cur->next;
++				}
++				cur->next = fl_hash_node;
++			} else {
++				if_flow_lkup[ifindex].fl_hash[hash] = fl_hash_node;
++			}
++		} else
++#endif /* WLTDLS */
++			if_flow_lkup[ifindex].fl_hash[prio] = fl_hash_node;
++	} else {
++
++		/* For bcast/mcast assign first slot in in interface */
++		hash = ETHER_ISMULTI(da) ? 0 : DHD_FLOWRING_HASHINDEX(da, prio);
++		cur = if_flow_lkup[ifindex].fl_hash[hash];
++		if (cur) {
++			while (cur->next) {
++				cur = cur->next;
++			}
++			cur->next = fl_hash_node;
++		} else
++			if_flow_lkup[ifindex].fl_hash[hash] = fl_hash_node;
++	}
++	DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++
++	DHD_INFO(("%s: allocated flowid %d\n", __FUNCTION__, fl_hash_node->flowid));
++
++	return fl_hash_node->flowid;
++} /* dhd_flowid_alloc */
++
++/** Get flow ring ID, if not present try to create one */
++static INLINE int
++dhd_flowid_lookup(dhd_pub_t *dhdp, uint8 ifindex,
++                  uint8 prio, char *sa, char *da, uint16 *flowid)
++{
++	uint16 id;
++	flow_ring_node_t *flow_ring_node;
++	flow_ring_table_t *flow_ring_table;
++	unsigned long flags;
++	int ret;
++
++	DHD_INFO(("%s\n", __FUNCTION__));
++
++	if (!dhdp->flow_ring_table) {
++		return BCME_ERROR;
++	}
++
++	flow_ring_table = (flow_ring_table_t *)dhdp->flow_ring_table;
++
++	id = dhd_flowid_find(dhdp, ifindex, prio, sa, da);
++
++	if (id == FLOWID_INVALID) {
++
++		if_flow_lkup_t *if_flow_lkup;
++		if_flow_lkup = (if_flow_lkup_t *)dhdp->if_flow_lkup;
++
++		if (!if_flow_lkup[ifindex].status)
++			return BCME_ERROR;
++
++
++		id = dhd_flowid_alloc(dhdp, ifindex, prio, sa, da);
++		if (id == FLOWID_INVALID) {
++			DHD_ERROR(("%s: alloc flowid ifindex %u status %u\n",
++			           __FUNCTION__, ifindex, if_flow_lkup[ifindex].status));
++			return BCME_ERROR;
++		}
++
++		/* register this flowid in dhd_pub */
++		dhd_add_flowid(dhdp, ifindex, prio, da, id);
++
++		ASSERT(id < dhdp->num_flow_rings);
++
++		flow_ring_node = (flow_ring_node_t *) &flow_ring_table[id];
++
++		DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++
++		/* Init Flow info */
++		memcpy(flow_ring_node->flow_info.sa, sa, sizeof(flow_ring_node->flow_info.sa));
++		memcpy(flow_ring_node->flow_info.da, da, sizeof(flow_ring_node->flow_info.da));
++		flow_ring_node->flow_info.tid = prio;
++		flow_ring_node->flow_info.ifindex = ifindex;
++		flow_ring_node->active = TRUE;
++		flow_ring_node->status = FLOW_RING_STATUS_PENDING;
++		DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++
++		/* Create and inform device about the new flow */
++		if (dhd_bus_flow_ring_create_request(dhdp->bus, (void *)flow_ring_node)
++				!= BCME_OK) {
++			DHD_ERROR(("%s: create error %d\n", __FUNCTION__, id));
++			return BCME_ERROR;
++		}
++
++		*flowid = id;
++		return BCME_OK;
++	} else {
++		/* if the Flow id was found in the hash */
++		ASSERT(id < dhdp->num_flow_rings);
++
++		flow_ring_node = (flow_ring_node_t *) &flow_ring_table[id];
++		DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++
++		/*
++		 * If the flow_ring_node is in Open State or Status pending state then
++		 * we can return the Flow id to the caller.If the flow_ring_node is in
++		 * FLOW_RING_STATUS_PENDING this means the creation is in progress and
++		 * hence the packets should be queued.
++		 *
++		 * If the flow_ring_node is in FLOW_RING_STATUS_DELETE_PENDING Or
++		 * FLOW_RING_STATUS_CLOSED, then we should return Error.
++		 * Note that if the flowing is being deleted we would mark it as
++		 * FLOW_RING_STATUS_DELETE_PENDING.  Now before Dongle could respond and
++		 * before we mark it as FLOW_RING_STATUS_CLOSED we could get tx packets.
++		 * We should drop the packets in that case.
++		 * The decission to return OK should NOT be based on 'active' variable, beause
++		 * active is made TRUE when a flow_ring_node gets allocated and is made
++		 * FALSE when the flow ring gets removed and does not reflect the True state
++		 * of the Flow ring.
++		 */
++		if (flow_ring_node->status == FLOW_RING_STATUS_OPEN ||
++			flow_ring_node->status == FLOW_RING_STATUS_PENDING) {
++			*flowid = id;
++			ret = BCME_OK;
++		} else {
++			*flowid = FLOWID_INVALID;
++			ret = BCME_ERROR;
++		}
++
++		DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++		return ret;
++
++	} /* Flow Id found in the hash */
++} /* dhd_flowid_lookup */
++
++/**
++ * Assign existing or newly created flowid to an 802.3 packet. This flowid is later on used to
++ * select the flowring to send the packet to the dongle.
++ */
++int BCMFASTPATH
++dhd_flowid_update(dhd_pub_t *dhdp, uint8 ifindex, uint8 prio, void *pktbuf)
++{
++	uint8 *pktdata = (uint8 *)PKTDATA(dhdp->osh, pktbuf);
++	struct ether_header *eh = (struct ether_header *)pktdata;
++	uint16 flowid;
++
++	ASSERT(ifindex < DHD_MAX_IFS);
++
++	if (ifindex >= DHD_MAX_IFS) {
++		return BCME_BADARG;
++	}
++
++	if (!dhdp->flowid_allocator) {
++		DHD_ERROR(("%s: Flow ring not intited yet  \n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	if (dhd_flowid_lookup(dhdp, ifindex, prio, eh->ether_shost, eh->ether_dhost,
++		&flowid) != BCME_OK) {
++		return BCME_ERROR;
++	}
++
++	DHD_INFO(("%s: prio %d flowid %d\n", __FUNCTION__, prio, flowid));
++
++	/* Tag the packet with flowid */
++	DHD_PKT_SET_FLOWID(pktbuf, flowid);
++	return BCME_OK;
++}
++
++void
++dhd_flowid_free(dhd_pub_t *dhdp, uint8 ifindex, uint16 flowid)
++{
++	int hashix;
++	bool found = FALSE;
++	flow_hash_info_t *cur, *prev;
++	if_flow_lkup_t *if_flow_lkup;
++	unsigned long flags;
++
++	DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++	if_flow_lkup = (if_flow_lkup_t *)dhdp->if_flow_lkup;
++
++	for (hashix = 0; hashix < DHD_FLOWRING_HASH_SIZE; hashix++) {
++
++		cur = if_flow_lkup[ifindex].fl_hash[hashix];
++
++		if (cur) {
++			if (cur->flowid == flowid) {
++				found = TRUE;
++			}
++
++			prev = NULL;
++			while (!found && cur) {
++				if (cur->flowid == flowid) {
++					found = TRUE;
++					break;
++				}
++				prev = cur;
++				cur = cur->next;
++			}
++			if (found) {
++				if (!prev) {
++					if_flow_lkup[ifindex].fl_hash[hashix] = cur->next;
++				} else {
++					prev->next = cur->next;
++				}
++
++				/* deregister flowid from dhd_pub. */
++				dhd_del_flowid(dhdp, ifindex, flowid);
++
++				id16_map_free(dhdp->flowid_allocator, flowid);
++				DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++				MFREE(dhdp->osh, cur, sizeof(flow_hash_info_t));
++
++				return;
++			}
++		}
++	}
++
++	DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++	DHD_ERROR(("%s: could not free flow ring hash entry flowid %d\n",
++	           __FUNCTION__, flowid));
++} /* dhd_flowid_free */
++
++/**
++ * Delete all Flow rings associated with the given interface. Is called when e.g. the dongle
++ * indicates that a wireless link has gone down.
++ */
++void
++dhd_flow_rings_delete(dhd_pub_t *dhdp, uint8 ifindex)
++{
++	uint32 id;
++	flow_ring_table_t *flow_ring_table;
++
++	DHD_INFO(("%s: ifindex %u\n", __FUNCTION__, ifindex));
++
++	ASSERT(ifindex < DHD_MAX_IFS);
++	if (ifindex >= DHD_MAX_IFS)
++		return;
++
++	if (!dhdp->flow_ring_table)
++		return;
++
++	flow_ring_table = (flow_ring_table_t *)dhdp->flow_ring_table;
++	for (id = 0; id < dhdp->num_flow_rings; id++) {
++		if (flow_ring_table[id].active &&
++		    (flow_ring_table[id].flow_info.ifindex == ifindex)) {
++			dhd_bus_flow_ring_delete_request(dhdp->bus,
++			                                 (void *) &flow_ring_table[id]);
++		}
++	}
++}
++
++/** Delete flow ring(s) for given peer address. Related to AP/AWDL/TDLS functionality. */
++void
++dhd_flow_rings_delete_for_peer(dhd_pub_t *dhdp, uint8 ifindex, char *addr)
++{
++	uint32 id;
++	flow_ring_table_t *flow_ring_table;
++
++	DHD_ERROR(("%s: ifindex %u\n", __FUNCTION__, ifindex));
++
++	ASSERT(ifindex < DHD_MAX_IFS);
++	if (ifindex >= DHD_MAX_IFS)
++		return;
++
++	if (!dhdp->flow_ring_table)
++		return;
++
++	flow_ring_table = (flow_ring_table_t *)dhdp->flow_ring_table;
++	for (id = 0; id < dhdp->num_flow_rings; id++) {
++		if (flow_ring_table[id].active &&
++			(flow_ring_table[id].flow_info.ifindex == ifindex) &&
++			(!memcmp(flow_ring_table[id].flow_info.da, addr, ETHER_ADDR_LEN)) &&
++			(flow_ring_table[id].status != FLOW_RING_STATUS_DELETE_PENDING)) {
++			DHD_INFO(("%s: deleting flowid %d\n",
++				__FUNCTION__, flow_ring_table[id].flowid));
++			dhd_bus_flow_ring_delete_request(dhdp->bus,
++				(void *) &flow_ring_table[id]);
++		}
++	}
++}
++
++/** Handles interface ADD, CHANGE, DEL indications from the dongle */
++void
++dhd_update_interface_flow_info(dhd_pub_t *dhdp, uint8 ifindex,
++                               uint8 op, uint8 role)
++{
++	if_flow_lkup_t *if_flow_lkup;
++	unsigned long flags;
++
++	ASSERT(ifindex < DHD_MAX_IFS);
++	if (ifindex >= DHD_MAX_IFS)
++		return;
++
++	DHD_INFO(("%s: ifindex %u op %u role is %u \n",
++	          __FUNCTION__, ifindex, op, role));
++	if (!dhdp->flowid_allocator) {
++		DHD_ERROR(("%s: Flow ring not intited yet  \n", __FUNCTION__));
++		return;
++	}
++
++	DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++	if_flow_lkup = (if_flow_lkup_t *)dhdp->if_flow_lkup;
++
++	if (op == WLC_E_IF_ADD || op == WLC_E_IF_CHANGE) {
++
++		if_flow_lkup[ifindex].role = role;
++
++		if (role != WLC_E_IF_ROLE_STA) {
++			/* Flowrings has to be created for WDS and DWDS when interface is created */
++			if_flow_lkup[ifindex].status = TRUE;
++			DHD_INFO(("%s: Mcast Flow ring for ifindex %d role is %d \n",
++			          __FUNCTION__, ifindex, role));
++			/* Create Mcast Flow */
++		}
++	} else	if (op == WLC_E_IF_DEL) {
++		if_flow_lkup[ifindex].status = FALSE;
++		DHD_INFO(("%s: cleanup all Flow rings for ifindex %d role is %d \n",
++		          __FUNCTION__, ifindex, role));
++	}
++	DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++}
++
++/** Handles a STA 'link' indication from the dongle */
++int
++dhd_update_interface_link_status(dhd_pub_t *dhdp, uint8 ifindex, uint8 status)
++{
++	if_flow_lkup_t *if_flow_lkup;
++	unsigned long flags;
++
++	ASSERT(ifindex < DHD_MAX_IFS);
++	if (ifindex >= DHD_MAX_IFS)
++		return BCME_BADARG;
++
++	DHD_INFO(("%s: ifindex %d status %d\n", __FUNCTION__, ifindex, status));
++
++	DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++	if_flow_lkup = (if_flow_lkup_t *)dhdp->if_flow_lkup;
++
++	if (if_flow_lkup[ifindex].role == WLC_E_IF_ROLE_STA) {
++		if (status)
++			if_flow_lkup[ifindex].status = TRUE;
++		else
++			if_flow_lkup[ifindex].status = FALSE;
++	}
++	DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++
++	return BCME_OK;
++}
++
++/** Update flow priority mapping, called on IOVAR */
++int dhd_update_flow_prio_map(dhd_pub_t *dhdp, uint8 map)
++{
++	uint16 flowid;
++	flow_ring_node_t *flow_ring_node;
++
++	if (map > DHD_FLOW_PRIO_LLR_MAP)
++		return BCME_BADOPTION;
++
++	/* Check if we need to change prio map */
++	if (map == dhdp->flow_prio_map_type)
++		return BCME_OK;
++
++	/* If any ring is active we cannot change priority mapping for flow rings */
++	for (flowid = 0; flowid < dhdp->num_flow_rings; flowid++) {
++		flow_ring_node = DHD_FLOW_RING(dhdp, flowid);
++		if (flow_ring_node->active)
++			return BCME_EPERM;
++	}
++
++	/* Inform firmware about new mapping type */
++	if (BCME_OK != dhd_flow_prio_map(dhdp, &map, TRUE))
++		return BCME_ERROR;
++
++	/* update internal structures */
++	dhdp->flow_prio_map_type = map;
++	if (dhdp->flow_prio_map_type == DHD_FLOW_PRIO_TID_MAP)
++		bcopy(prio2tid, dhdp->flow_prio_map, sizeof(uint8) * NUMPRIO);
++	else
++		bcopy(prio2ac, dhdp->flow_prio_map, sizeof(uint8) * NUMPRIO);
++
++	return BCME_OK;
++}
++
++/** Inform firmware on updated flow priority mapping, called on IOVAR */
++int dhd_flow_prio_map(dhd_pub_t *dhd, uint8 *map, bool set)
++{
++	uint8 iovbuf[24];
++	if (!set) {
++		bcm_mkiovar("bus:fl_prio_map", NULL, 0, (char*)iovbuf, sizeof(iovbuf));
++		if (dhd_wl_ioctl_cmd(dhd, WLC_GET_VAR, iovbuf, sizeof(iovbuf), FALSE, 0) < 0) {
++			DHD_ERROR(("%s: failed to get fl_prio_map\n", __FUNCTION__));
++			return BCME_ERROR;
++		}
++		*map = iovbuf[0];
++		return BCME_OK;
++	}
++	bcm_mkiovar("bus:fl_prio_map", (char *)map, 4, (char*)iovbuf, sizeof(iovbuf));
++	if (dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, iovbuf, sizeof(iovbuf), TRUE, 0) < 0) {
++		DHD_ERROR(("%s: failed to set fl_prio_map \n",
++			__FUNCTION__));
++		return BCME_ERROR;
++	}
++	return BCME_OK;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_flowring.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_flowring.h
+new file mode 100644
+index 000000000..8b79028bd
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_flowring.h
+@@ -0,0 +1,252 @@
++/**
++ * @file Header file describing the flow rings DHD interfaces.
++ *
++ * Flow rings are transmit traffic (=propagating towards antenna) related entities.
++ *
++ * Provides type definitions and function prototypes used to create, delete and manage flow rings at
++ * high level.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_flowrings.h  jaganlv $
++ */
++
++
++/****************
++ * Common types *
++ */
++
++#ifndef _dhd_flowrings_h_
++#define _dhd_flowrings_h_
++
++/* Max pkts held in a flow ring's backup queue */
++#define FLOW_RING_QUEUE_THRESHOLD       (2048)
++
++/* Number of H2D common rings */
++#define FLOW_RING_COMMON                BCMPCIE_H2D_COMMON_MSGRINGS
++
++#define FLOWID_INVALID                  (ID16_INVALID)
++#define FLOWID_RESERVED                 (FLOW_RING_COMMON)
++
++#define FLOW_RING_STATUS_OPEN           0
++#define FLOW_RING_STATUS_PENDING        1
++#define FLOW_RING_STATUS_CLOSED         2
++#define FLOW_RING_STATUS_DELETE_PENDING 3
++#define FLOW_RING_STATUS_FLUSH_PENDING  4
++#define FLOW_RING_STATUS_STA_FREEING    5
++
++#define DHD_FLOWRING_RX_BUFPOST_PKTSZ	2048
++
++#define DHD_FLOW_PRIO_AC_MAP		0
++#define DHD_FLOW_PRIO_TID_MAP		1
++#define DHD_FLOW_PRIO_LLR_MAP		2
++
++/* Pkttag not compatible with PROP_TXSTATUS or WLFC */
++typedef struct dhd_pkttag_fr {
++	uint16  flowid;
++	uint16  ifid;
++	int     dataoff;
++	dmaaddr_t physaddr;
++	uint32 pa_len;
++
++} dhd_pkttag_fr_t;
++
++#define DHD_PKTTAG_SET_FLOWID(tag, flow)    ((tag)->flowid = (uint16)(flow))
++#define DHD_PKTTAG_SET_IFID(tag, idx)       ((tag)->ifid = (uint16)(idx))
++#define DHD_PKTTAG_SET_DATAOFF(tag, offset) ((tag)->dataoff = (int)(offset))
++#define DHD_PKTTAG_SET_PA(tag, pa)          ((tag)->physaddr = (pa))
++#define DHD_PKTTAG_SET_PA_LEN(tag, palen)   ((tag)->pa_len = (palen))
++
++#define DHD_PKTTAG_FLOWID(tag)              ((tag)->flowid)
++#define DHD_PKTTAG_IFID(tag)                ((tag)->ifid)
++#define DHD_PKTTAG_DATAOFF(tag)             ((tag)->dataoff)
++#define DHD_PKTTAG_PA(tag)                  ((tag)->physaddr)
++#define DHD_PKTTAG_PA_LEN(tag)              ((tag)->pa_len)
++
++/* Hashing a MacAddress for lkup into a per interface flow hash table */
++#define DHD_FLOWRING_HASH_SIZE    256
++#define	DHD_FLOWRING_HASHINDEX(ea, prio) \
++	       ((((uint8 *)(ea))[3] ^ ((uint8 *)(ea))[4] ^ ((uint8 *)(ea))[5] ^ ((uint8)(prio))) \
++		% DHD_FLOWRING_HASH_SIZE)
++
++#define DHD_IF_ROLE(pub, idx)		(((if_flow_lkup_t *)(pub)->if_flow_lkup)[idx].role)
++#define DHD_IF_ROLE_AP(pub, idx)	(DHD_IF_ROLE(pub, idx) == WLC_E_IF_ROLE_AP)
++#define DHD_IF_ROLE_STA(pub, idx)	(DHD_IF_ROLE(pub, idx) == WLC_E_IF_ROLE_STA)
++#define DHD_IF_ROLE_P2PGO(pub, idx)	(DHD_IF_ROLE(pub, idx) == WLC_E_IF_ROLE_P2P_GO)
++#define DHD_IF_ROLE_WDS(pub, idx)	(DHD_IF_ROLE(pub, idx) == WLC_E_IF_ROLE_WDS)
++#define DHD_FLOW_RING(dhdp, flowid) \
++	(flow_ring_node_t *)&(((flow_ring_node_t *)((dhdp)->flow_ring_table))[flowid])
++
++struct flow_queue;
++
++/* Flow Ring Queue Enqueue overflow callback */
++typedef int (*flow_queue_cb_t)(struct flow_queue * queue, void * pkt);
++
++/**
++ * Each flow ring has an associated (tx flow controlled) queue. 802.3 packets are transferred
++ * between queue and ring. A packet from the host stack is first added to the queue, and in a later
++ * stage transferred to the flow ring. Packets in the queue are dhd owned, whereas packets in the
++ * flow ring are device owned.
++ */
++typedef struct flow_queue {
++	dll_t  list;                /* manage a flowring queue in a double linked list */
++	void * head;                /* first packet in the queue */
++	void * tail;                /* last packet in the queue */
++	uint16 len;                 /* number of packets in the queue */
++	uint16 max;                 /* maximum or min budget (used in cumm) */
++	uint32 threshold;           /* parent's cummulative length threshold */
++	void * clen_ptr;            /* parent's cummulative length counter */
++	uint32 failures;            /* enqueue failures due to queue overflow */
++	flow_queue_cb_t cb;         /* callback invoked on threshold crossing */
++	uint32 l2threshold;         /* grandparent's (level 2) cummulative length threshold */
++	void * l2clen_ptr;          /* grandparent's (level 2) cummulative length counter */
++} flow_queue_t;
++
++#define DHD_FLOW_QUEUE_LEN(queue)       ((int)(queue)->len)
++#define DHD_FLOW_QUEUE_MAX(queue)       ((int)(queue)->max)
++#define DHD_FLOW_QUEUE_THRESHOLD(queue) ((int)(queue)->threshold)
++#define DHD_FLOW_QUEUE_L2THRESHOLD(queue) ((int)(queue)->l2threshold)
++#define DHD_FLOW_QUEUE_EMPTY(queue)     ((queue)->len == 0)
++#define DHD_FLOW_QUEUE_FAILURES(queue)  ((queue)->failures)
++
++#define DHD_FLOW_QUEUE_AVAIL(queue)     ((int)((queue)->max - (queue)->len))
++#define DHD_FLOW_QUEUE_FULL(queue)      ((queue)->len >= (queue)->max)
++
++#define DHD_FLOW_QUEUE_OVFL(queue, budget)  \
++	(((queue)->len) > budget)
++
++#define DHD_FLOW_QUEUE_SET_MAX(queue, budget) \
++	((queue)->max) = ((budget) - 1)
++
++/* Queue's cummulative threshold. */
++#define DHD_FLOW_QUEUE_SET_THRESHOLD(queue, cumm_threshold) \
++	((queue)->threshold) = ((cumm_threshold) - 1)
++
++/* Queue's cummulative length object accessor. */
++#define DHD_FLOW_QUEUE_CLEN_PTR(queue)  ((queue)->clen_ptr)
++
++/* Set a queue's cumm_len point to a parent's cumm_ctr_t cummulative length */
++#define DHD_FLOW_QUEUE_SET_CLEN(queue, parent_clen_ptr)  \
++	((queue)->clen_ptr) = (void *)(parent_clen_ptr)
++
++/* Queue's level 2 cummulative threshold. */
++#define DHD_FLOW_QUEUE_SET_L2THRESHOLD(queue, l2cumm_threshold) \
++	((queue)->l2threshold) = ((l2cumm_threshold) - 1)
++
++/* Queue's level 2 cummulative length object accessor. */
++#define DHD_FLOW_QUEUE_L2CLEN_PTR(queue)  ((queue)->l2clen_ptr)
++
++/* Set a queue's level 2 cumm_len point to a grandparent's cumm_ctr_t cummulative length */
++#define DHD_FLOW_QUEUE_SET_L2CLEN(queue, grandparent_clen_ptr)  \
++	((queue)->l2clen_ptr) = (void *)(grandparent_clen_ptr)
++
++/*  see wlfc_proto.h for tx status details */
++#define DHD_FLOWRING_MAXSTATUS_MSGS	5
++#define DHD_FLOWRING_TXSTATUS_CNT_UPDATE(bus, flowid, txstatus)
++/** each flow ring is dedicated to a tid/sa/da combination */
++typedef struct flow_info {
++	uint8		tid;
++	uint8		ifindex;
++	char		sa[ETHER_ADDR_LEN];
++	char		da[ETHER_ADDR_LEN];
++} flow_info_t;
++
++/** a flow ring is used for outbound (towards antenna) 802.3 packets */
++typedef struct flow_ring_node {
++	dll_t		list;  /* manage a constructed flowring in a dll, must be at first place */
++	flow_queue_t	queue; /* queues packets before they enter the flow ring, flow control */
++	bool		active;
++	uint8		status;
++	/*
++	 * flowid: unique ID of a flow ring, which can either be unicast or broadcast/multicast. For
++	 * unicast flow rings, the flow id accelerates ARM 802.3->802.11 header translation.
++	 */
++	uint16		flowid;
++	flow_info_t	flow_info;
++	void		*prot_info;
++	void		*lock; /* lock for flowring access protection */
++} flow_ring_node_t;
++
++typedef flow_ring_node_t flow_ring_table_t;
++
++typedef struct flow_hash_info {
++	uint16			flowid;
++	flow_info_t		flow_info;
++	struct flow_hash_info	*next;
++} flow_hash_info_t;
++
++typedef struct if_flow_lkup {
++	bool		status;
++	uint8		role; /* Interface role: STA/AP */
++	flow_hash_info_t *fl_hash[DHD_FLOWRING_HASH_SIZE]; /* Lkup Hash table */
++} if_flow_lkup_t;
++
++static INLINE flow_ring_node_t *
++dhd_constlist_to_flowring(dll_t *item)
++{
++	return ((flow_ring_node_t *)item);
++}
++
++/* Exported API */
++
++/* Flow ring's queue management functions */
++extern flow_ring_node_t * dhd_flow_ring_node(dhd_pub_t *dhdp, uint16 flowid);
++extern flow_queue_t * dhd_flow_queue(dhd_pub_t *dhdp, uint16 flowid);
++
++extern void dhd_flow_queue_init(dhd_pub_t *dhdp, flow_queue_t *queue, int max);
++extern void dhd_flow_queue_reinit(dhd_pub_t *dhdp, flow_queue_t *queue, int max);
++extern void dhd_flow_queue_register(flow_queue_t *queue, flow_queue_cb_t cb);
++extern int  dhd_flow_queue_enqueue(dhd_pub_t *dhdp, flow_queue_t *queue, void *pkt);
++extern void * dhd_flow_queue_dequeue(dhd_pub_t *dhdp, flow_queue_t *queue);
++extern void dhd_flow_queue_reinsert(dhd_pub_t *dhdp, flow_queue_t *queue, void *pkt);
++
++extern void dhd_flow_ring_config_thresholds(dhd_pub_t *dhdp, uint16 flowid,
++                          int queue_budget, int cumm_threshold, void *cumm_ctr,
++                          int l2cumm_threshold, void *l2cumm_ctr);
++extern int  dhd_flow_rings_init(dhd_pub_t *dhdp, uint32 num_flow_rings);
++
++extern void dhd_flow_rings_deinit(dhd_pub_t *dhdp);
++
++extern int dhd_flowid_update(dhd_pub_t *dhdp, uint8 ifindex, uint8 prio,
++                void *pktbuf);
++
++extern void dhd_flowid_free(dhd_pub_t *dhdp, uint8 ifindex, uint16 flowid);
++
++extern void dhd_flow_rings_delete(dhd_pub_t *dhdp, uint8 ifindex);
++
++extern void dhd_flow_rings_delete_for_peer(dhd_pub_t *dhdp, uint8 ifindex,
++                char *addr);
++
++/* Handle Interface ADD, DEL operations */
++extern void dhd_update_interface_flow_info(dhd_pub_t *dhdp, uint8 ifindex,
++                uint8 op, uint8 role);
++
++/* Handle a STA interface link status update */
++extern int dhd_update_interface_link_status(dhd_pub_t *dhdp, uint8 ifindex,
++                uint8 status);
++extern int dhd_flow_prio_map(dhd_pub_t *dhd, uint8 *map, bool set);
++extern int dhd_update_flow_prio_map(dhd_pub_t *dhdp, uint8 map);
++
++extern uint8 dhd_flow_rings_ifindex2role(dhd_pub_t *dhdp, uint8 ifindex);
++#endif /* _dhd_flowrings_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_ip.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_ip.c
+new file mode 100644
+index 000000000..17302a9b2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_ip.c
+@@ -0,0 +1,1285 @@
++/*
++ * IP Packet Parser Module.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_ip.c 709309 2019-01-17 09:04:00Z $
++ */
++#include <typedefs.h>
++#include <osl.h>
++
++#include <proto/ethernet.h>
++#include <proto/vlan.h>
++#include <proto/802.3.h>
++#include <proto/bcmip.h>
++#include <bcmendian.h>
++
++#include <dhd_dbg.h>
++
++#include <dhd_ip.h>
++
++#ifdef DHDTCPACK_SUPPRESS
++#include <dhd_bus.h>
++#include <dhd_proto.h>
++#include <proto/bcmtcp.h>
++#endif /* DHDTCPACK_SUPPRESS */
++
++/* special values */
++/* 802.3 llc/snap header */
++static const uint8 llc_snap_hdr[SNAP_HDR_LEN] = {0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00};
++
++pkt_frag_t pkt_frag_info(osl_t *osh, void *p)
++{
++	uint8 *frame;
++	int length;
++	uint8 *pt;			/* Pointer to type field */
++	uint16 ethertype;
++	struct ipv4_hdr *iph;		/* IP frame pointer */
++	int ipl;			/* IP frame length */
++	uint16 iph_frag;
++
++	ASSERT(osh && p);
++
++	frame = PKTDATA(osh, p);
++	length = PKTLEN(osh, p);
++
++	/* Process Ethernet II or SNAP-encapsulated 802.3 frames */
++	if (length < ETHER_HDR_LEN) {
++		DHD_INFO(("%s: short eth frame (%d)\n", __FUNCTION__, length));
++		return DHD_PKT_FRAG_NONE;
++	} else if (ntoh16(*(uint16 *)(frame + ETHER_TYPE_OFFSET)) >= ETHER_TYPE_MIN) {
++		/* Frame is Ethernet II */
++		pt = frame + ETHER_TYPE_OFFSET;
++	} else if (length >= ETHER_HDR_LEN + SNAP_HDR_LEN + ETHER_TYPE_LEN &&
++	           !bcmp(llc_snap_hdr, frame + ETHER_HDR_LEN, SNAP_HDR_LEN)) {
++		pt = frame + ETHER_HDR_LEN + SNAP_HDR_LEN;
++	} else {
++		DHD_INFO(("%s: non-SNAP 802.3 frame\n", __FUNCTION__));
++		return DHD_PKT_FRAG_NONE;
++	}
++
++	ethertype = ntoh16(*(uint16 *)pt);
++
++	/* Skip VLAN tag, if any */
++	if (ethertype == ETHER_TYPE_8021Q) {
++		pt += VLAN_TAG_LEN;
++
++		if (pt + ETHER_TYPE_LEN > frame + length) {
++			DHD_INFO(("%s: short VLAN frame (%d)\n", __FUNCTION__, length));
++			return DHD_PKT_FRAG_NONE;
++		}
++
++		ethertype = ntoh16(*(uint16 *)pt);
++	}
++
++	if (ethertype != ETHER_TYPE_IP) {
++		DHD_INFO(("%s: non-IP frame (ethertype 0x%x, length %d)\n",
++			__FUNCTION__, ethertype, length));
++		return DHD_PKT_FRAG_NONE;
++	}
++
++	iph = (struct ipv4_hdr *)(pt + ETHER_TYPE_LEN);
++	ipl = (uint)(length - (pt + ETHER_TYPE_LEN - frame));
++
++	/* We support IPv4 only */
++	if ((ipl < IPV4_OPTIONS_OFFSET) || (IP_VER(iph) != IP_VER_4)) {
++		DHD_INFO(("%s: short frame (%d) or non-IPv4\n", __FUNCTION__, ipl));
++		return DHD_PKT_FRAG_NONE;
++	}
++
++	iph_frag = ntoh16(iph->frag);
++
++	if (iph_frag & IPV4_FRAG_DONT) {
++		return DHD_PKT_FRAG_NONE;
++	} else if ((iph_frag & IPV4_FRAG_MORE) == 0) {
++		return DHD_PKT_FRAG_LAST;
++	} else {
++		return (iph_frag & IPV4_FRAG_OFFSET_MASK)? DHD_PKT_FRAG_CONT : DHD_PKT_FRAG_FIRST;
++	}
++}
++
++#ifdef DHDTCPACK_SUPPRESS
++
++typedef struct {
++	void *pkt_in_q;		/* TCP ACK packet that is already in txq or DelayQ */
++	void *pkt_ether_hdr;	/* Ethernet header pointer of pkt_in_q */
++	int ifidx;
++	uint8 supp_cnt;
++	dhd_pub_t *dhdp;
++	struct timer_list timer;
++} tcpack_info_t;
++
++typedef struct _tdata_psh_info_t {
++	uint32 end_seq;			/* end seq# of a received TCP PSH DATA pkt */
++	struct _tdata_psh_info_t *next;	/* next pointer of the link chain */
++} tdata_psh_info_t;
++
++typedef struct {
++	struct {
++		uint8 src[IPV4_ADDR_LEN];	/* SRC ip addrs of this TCP stream */
++		uint8 dst[IPV4_ADDR_LEN];	/* DST ip addrs of this TCP stream */
++	} ip_addr;
++	struct {
++		uint8 src[TCP_PORT_LEN];	/* SRC tcp ports of this TCP stream */
++		uint8 dst[TCP_PORT_LEN];	/* DST tcp ports of this TCP stream */
++	} tcp_port;
++	tdata_psh_info_t *tdata_psh_info_head;	/* Head of received TCP PSH DATA chain */
++	tdata_psh_info_t *tdata_psh_info_tail;	/* Tail of received TCP PSH DATA chain */
++	uint32 last_used_time;	/* The last time this tcpdata_info was used(in ms) */
++} tcpdata_info_t;
++
++/* TCPACK SUPPRESS module */
++typedef struct {
++	int tcpack_info_cnt;
++	tcpack_info_t tcpack_info_tbl[TCPACK_INFO_MAXNUM];	/* Info of TCP ACK to send */
++	int tcpdata_info_cnt;
++	tcpdata_info_t tcpdata_info_tbl[TCPDATA_INFO_MAXNUM];	/* Info of received TCP DATA */
++	tdata_psh_info_t *tdata_psh_info_pool;	/* Pointer to tdata_psh_info elements pool */
++	tdata_psh_info_t *tdata_psh_info_free;	/* free tdata_psh_info elements chain in pool */
++#ifdef DHDTCPACK_SUP_DBG
++	int psh_info_enq_num;	/* Number of free TCP PSH DATA info elements in pool */
++#endif /* DHDTCPACK_SUP_DBG */
++} tcpack_sup_module_t;
++
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++counter_tbl_t tack_tbl = {"tcpACK", 0, 1000, 10, {0, }, 1};
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++
++static void
++_tdata_psh_info_pool_enq(tcpack_sup_module_t *tcpack_sup_mod,
++	tdata_psh_info_t *tdata_psh_info)
++{
++	if ((tcpack_sup_mod == NULL) || (tdata_psh_info == NULL)) {
++		DHD_ERROR(("%s %d: ERROR %p %p\n", __FUNCTION__, __LINE__,
++			tcpack_sup_mod, tdata_psh_info));
++		return;
++	}
++
++	ASSERT(tdata_psh_info->next == NULL);
++	tdata_psh_info->next = tcpack_sup_mod->tdata_psh_info_free;
++	tcpack_sup_mod->tdata_psh_info_free = tdata_psh_info;
++#ifdef DHDTCPACK_SUP_DBG
++	tcpack_sup_mod->psh_info_enq_num++;
++#endif
++}
++
++static tdata_psh_info_t*
++_tdata_psh_info_pool_deq(tcpack_sup_module_t *tcpack_sup_mod)
++{
++	tdata_psh_info_t *tdata_psh_info = NULL;
++
++	if (tcpack_sup_mod == NULL) {
++		DHD_ERROR(("%s %d: ERROR %p\n", __FUNCTION__, __LINE__,
++			tcpack_sup_mod));
++		return NULL;
++	}
++
++	tdata_psh_info = tcpack_sup_mod->tdata_psh_info_free;
++	if (tdata_psh_info == NULL)
++		DHD_ERROR(("%s %d: Out of tdata_disc_grp\n", __FUNCTION__, __LINE__));
++	else {
++		tcpack_sup_mod->tdata_psh_info_free = tdata_psh_info->next;
++		tdata_psh_info->next = NULL;
++#ifdef DHDTCPACK_SUP_DBG
++		tcpack_sup_mod->psh_info_enq_num--;
++#endif /* DHDTCPACK_SUP_DBG */
++	}
++
++	return tdata_psh_info;
++}
++
++#ifdef BCMSDIO
++static int _tdata_psh_info_pool_init(dhd_pub_t *dhdp,
++	tcpack_sup_module_t *tcpack_sup_mod)
++{
++	tdata_psh_info_t *tdata_psh_info_pool = NULL;
++	uint i;
++
++	DHD_TRACE(("%s %d: Enter\n", __FUNCTION__, __LINE__));
++
++	if (tcpack_sup_mod == NULL)
++		return BCME_ERROR;
++
++	ASSERT(tcpack_sup_mod->tdata_psh_info_pool == NULL);
++	ASSERT(tcpack_sup_mod->tdata_psh_info_free == NULL);
++
++	tdata_psh_info_pool =
++		MALLOC(dhdp->osh, sizeof(tdata_psh_info_t) * TCPDATA_PSH_INFO_MAXNUM);
++
++	if (tdata_psh_info_pool == NULL)
++		return BCME_NOMEM;
++	bzero(tdata_psh_info_pool, sizeof(tdata_psh_info_t) * TCPDATA_PSH_INFO_MAXNUM);
++#ifdef DHDTCPACK_SUP_DBG
++	tcpack_sup_mod->psh_info_enq_num = 0;
++#endif /* DHDTCPACK_SUP_DBG */
++
++	/* Enqueue newly allocated tcpdata psh info elements to the pool */
++	for (i = 0; i < TCPDATA_PSH_INFO_MAXNUM; i++)
++		_tdata_psh_info_pool_enq(tcpack_sup_mod, &tdata_psh_info_pool[i]);
++
++	ASSERT(tcpack_sup_mod->tdata_psh_info_free != NULL);
++	tcpack_sup_mod->tdata_psh_info_pool = tdata_psh_info_pool;
++
++	return BCME_OK;
++}
++
++static void _tdata_psh_info_pool_deinit(dhd_pub_t *dhdp,
++	tcpack_sup_module_t *tcpack_sup_mod)
++{
++	uint i;
++	tdata_psh_info_t *tdata_psh_info;
++
++	DHD_TRACE(("%s %d: Enter\n", __FUNCTION__, __LINE__));
++
++	if (tcpack_sup_mod == NULL) {
++		DHD_ERROR(("%s %d: ERROR tcpack_sup_mod NULL!\n",
++			__FUNCTION__, __LINE__));
++		return;
++	}
++
++	for (i = 0; i < tcpack_sup_mod->tcpdata_info_cnt; i++) {
++		tcpdata_info_t *tcpdata_info = &tcpack_sup_mod->tcpdata_info_tbl[i];
++		/* Return tdata_psh_info elements allocated to each tcpdata_info to the pool */
++		while ((tdata_psh_info = tcpdata_info->tdata_psh_info_head)) {
++			tcpdata_info->tdata_psh_info_head = tdata_psh_info->next;
++			tdata_psh_info->next = NULL;
++			_tdata_psh_info_pool_enq(tcpack_sup_mod, tdata_psh_info);
++		}
++		tcpdata_info->tdata_psh_info_tail = NULL;
++	}
++#ifdef DHDTCPACK_SUP_DBG
++	DHD_ERROR(("%s %d: PSH INFO ENQ %d\n",
++		__FUNCTION__, __LINE__, tcpack_sup_mod->psh_info_enq_num));
++#endif /* DHDTCPACK_SUP_DBG */
++
++	i = 0;
++	/* Be sure we recollected all tdata_psh_info elements */
++	while ((tdata_psh_info = tcpack_sup_mod->tdata_psh_info_free)) {
++		tcpack_sup_mod->tdata_psh_info_free = tdata_psh_info->next;
++		tdata_psh_info->next = NULL;
++		i++;
++	}
++	ASSERT(i == TCPDATA_PSH_INFO_MAXNUM);
++	MFREE(dhdp->osh, tcpack_sup_mod->tdata_psh_info_pool,
++		sizeof(tdata_psh_info_t) * TCPDATA_PSH_INFO_MAXNUM);
++	tcpack_sup_mod->tdata_psh_info_pool = NULL;
++
++	return;
++}
++#endif /* BCMSDIO */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++static void dhd_tcpack_send(struct timer_list *t)
++{
++	tcpack_info_t *cur_tbl = from_timer(cur_tbl, t, timer);
++#else
++static void dhd_tcpack_send(ulong data)
++{
++	tcpack_info_t *cur_tbl = (tcpack_info_t *)data;
++#endif
++	tcpack_sup_module_t *tcpack_sup_mod;
++	dhd_pub_t *dhdp;
++	int ifidx;
++	void* pkt;
++	unsigned long flags;
++
++	if (!cur_tbl) {
++		return;
++	}
++
++	dhdp = cur_tbl->dhdp;
++	if (!dhdp) {
++		return;
++	}
++
++	flags = dhd_os_tcpacklock(dhdp);
++
++	tcpack_sup_mod = dhdp->tcpack_sup_module;
++	if (!tcpack_sup_mod) {
++		DHD_ERROR(("%s %d: tcpack suppress module NULL!!\n",
++			__FUNCTION__, __LINE__));
++		dhd_os_tcpackunlock(dhdp, flags);
++		return;
++	}
++	pkt = cur_tbl->pkt_in_q;
++	ifidx = cur_tbl->ifidx;
++	if (!pkt) {
++		dhd_os_tcpackunlock(dhdp, flags);
++		return;
++	}
++	cur_tbl->pkt_in_q = NULL;
++	cur_tbl->pkt_ether_hdr = NULL;
++	cur_tbl->ifidx = 0;
++	cur_tbl->supp_cnt = 0;
++	if (--tcpack_sup_mod->tcpack_info_cnt < 0) {
++		DHD_ERROR(("%s %d: ERROR!!! tcp_ack_info_cnt %d\n",
++			__FUNCTION__, __LINE__, tcpack_sup_mod->tcpack_info_cnt));
++	}
++
++	dhd_os_tcpackunlock(dhdp, flags);
++
++	dhd_sendpkt(dhdp, ifidx, pkt);
++}
++
++int dhd_tcpack_suppress_set(dhd_pub_t *dhdp, uint8 mode)
++{
++	int ret = BCME_OK;
++	unsigned long flags;
++
++	flags = dhd_os_tcpacklock(dhdp);
++
++	if (dhdp->tcpack_sup_mode == mode) {
++		DHD_ERROR(("%s %d: already set to %d\n", __FUNCTION__, __LINE__, mode));
++		goto exit;
++	}
++
++	if (mode >= TCPACK_SUP_LAST_MODE ||
++#ifndef BCMSDIO
++		mode == TCPACK_SUP_DELAYTX ||
++#endif /* !BCMSDIO */
++		FALSE) {
++		DHD_ERROR(("%s %d: Invalid mode %d\n", __FUNCTION__, __LINE__, mode));
++		ret = BCME_BADARG;
++		goto exit;
++	}
++
++	DHD_TRACE(("%s: %d -> %d\n",
++		__FUNCTION__, dhdp->tcpack_sup_mode, mode));
++
++#ifdef BCMSDIO
++	/* Old tcpack_sup_mode is TCPACK_SUP_DELAYTX */
++	if (dhdp->tcpack_sup_mode == TCPACK_SUP_DELAYTX) {
++		tcpack_sup_module_t *tcpack_sup_mod = dhdp->tcpack_sup_module;
++		/* We won't need tdata_psh_info pool and tcpddata_info_tbl anymore */
++		_tdata_psh_info_pool_deinit(dhdp, tcpack_sup_mod);
++		tcpack_sup_mod->tcpdata_info_cnt = 0;
++		bzero(tcpack_sup_mod->tcpdata_info_tbl,
++			sizeof(tcpdata_info_t) * TCPDATA_INFO_MAXNUM);
++		/* For half duplex bus interface, tx precedes rx by default */
++		if (dhdp->bus)
++			dhd_bus_set_dotxinrx(dhdp->bus, TRUE);
++	}
++#endif /* BCMSDIO */
++	dhdp->tcpack_sup_mode = mode;
++
++	if (mode == TCPACK_SUP_OFF) {
++		ASSERT(dhdp->tcpack_sup_module != NULL);
++		/* Clean up timer/data structure for any remaining/pending packet or timer. */
++		dhd_tcpack_info_tbl_clean(dhdp);
++		MFREE(dhdp->osh, dhdp->tcpack_sup_module, sizeof(tcpack_sup_module_t));
++		dhdp->tcpack_sup_module = NULL;
++		goto exit;
++	}
++
++	if (dhdp->tcpack_sup_module == NULL) {
++		tcpack_sup_module_t *tcpack_sup_mod =
++			MALLOC(dhdp->osh, sizeof(tcpack_sup_module_t));
++		if (tcpack_sup_mod == NULL) {
++			DHD_ERROR(("%s %d: No MEM\n", __FUNCTION__, __LINE__));
++			dhdp->tcpack_sup_mode = TCPACK_SUP_OFF;
++			ret = BCME_NOMEM;
++			goto exit;
++		}
++		bzero(tcpack_sup_mod, sizeof(tcpack_sup_module_t));
++		dhdp->tcpack_sup_module = tcpack_sup_mod;
++	}
++
++#ifdef BCMSDIO
++	if (mode == TCPACK_SUP_DELAYTX) {
++		ret = _tdata_psh_info_pool_init(dhdp, dhdp->tcpack_sup_module);
++		if (ret != BCME_OK)
++			DHD_ERROR(("%s %d: pool init fail with %d\n", __FUNCTION__, __LINE__, ret));
++		else if (dhdp->bus)
++			dhd_bus_set_dotxinrx(dhdp->bus, FALSE);
++	}
++#endif /* BCMSDIO */
++
++	if (mode == TCPACK_SUP_HOLD) {
++		int i;
++		tcpack_sup_module_t *tcpack_sup_mod =
++			(tcpack_sup_module_t *)dhdp->tcpack_sup_module;
++		dhdp->tcpack_sup_ratio = CUSTOM_TCPACK_SUPP_RATIO;
++		dhdp->tcpack_sup_delay = CUSTOM_TCPACK_DELAY_TIME;
++		for (i = 0; i < TCPACK_INFO_MAXNUM; i++)
++		{
++			tcpack_sup_mod->tcpack_info_tbl[i].dhdp = dhdp;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++			timer_setup((struct timer_list *)&tcpack_sup_mod->tcpack_info_tbl[i].timer, dhd_tcpack_send, 0);
++#else
++			init_timer(&tcpack_sup_mod->tcpack_info_tbl[i].timer);
++			tcpack_sup_mod->tcpack_info_tbl[i].timer.data =
++				(ulong)&tcpack_sup_mod->tcpack_info_tbl[i];
++			tcpack_sup_mod->tcpack_info_tbl[i].timer.function = dhd_tcpack_send;
++#endif
++		}
++	}
++
++exit:
++	dhd_os_tcpackunlock(dhdp, flags);
++	return ret;
++}
++
++void
++dhd_tcpack_info_tbl_clean(dhd_pub_t *dhdp)
++{
++	tcpack_sup_module_t *tcpack_sup_mod = dhdp->tcpack_sup_module;
++	int i;
++	unsigned long flags;
++
++	if (dhdp->tcpack_sup_mode == TCPACK_SUP_OFF)
++		goto exit;
++
++	flags = dhd_os_tcpacklock(dhdp);
++
++	if (!tcpack_sup_mod) {
++		DHD_ERROR(("%s %d: tcpack suppress module NULL!!\n",
++			__FUNCTION__, __LINE__));
++		dhd_os_tcpackunlock(dhdp, flags);
++		goto exit;
++	}
++
++	if (dhdp->tcpack_sup_mode == TCPACK_SUP_HOLD) {
++		for (i = 0; i < TCPACK_INFO_MAXNUM; i++) {
++			if (tcpack_sup_mod->tcpack_info_tbl[i].pkt_in_q) {
++				PKTFREE(dhdp->osh, tcpack_sup_mod->tcpack_info_tbl[i].pkt_in_q,
++					TRUE);
++				tcpack_sup_mod->tcpack_info_tbl[i].pkt_in_q = NULL;
++				tcpack_sup_mod->tcpack_info_tbl[i].pkt_ether_hdr = NULL;
++				tcpack_sup_mod->tcpack_info_tbl[i].ifidx = 0;
++				tcpack_sup_mod->tcpack_info_tbl[i].supp_cnt = 0;
++			}
++		}
++	} else {
++		tcpack_sup_mod->tcpack_info_cnt = 0;
++		bzero(tcpack_sup_mod->tcpack_info_tbl, sizeof(tcpack_info_t) * TCPACK_INFO_MAXNUM);
++	}
++
++	dhd_os_tcpackunlock(dhdp, flags);
++
++	if (dhdp->tcpack_sup_mode == TCPACK_SUP_HOLD) {
++		for (i = 0; i < TCPACK_INFO_MAXNUM; i++) {
++			del_timer_sync(&tcpack_sup_mod->tcpack_info_tbl[i].timer);
++		}
++	}
++
++exit:
++	return;
++}
++
++inline int dhd_tcpack_check_xmit(dhd_pub_t *dhdp, void *pkt)
++{
++	uint8 i;
++	tcpack_sup_module_t *tcpack_sup_mod;
++	tcpack_info_t *tcpack_info_tbl;
++	int tbl_cnt;
++	int ret = BCME_OK;
++	void *pdata;
++	uint32 pktlen;
++	unsigned long flags;
++
++	if (dhdp->tcpack_sup_mode == TCPACK_SUP_OFF)
++		goto exit;
++
++	pdata = PKTDATA(dhdp->osh, pkt);
++	pktlen = PKTLEN(dhdp->osh, pkt) - dhd_prot_hdrlen(dhdp, pdata);
++
++	if (pktlen < TCPACKSZMIN || pktlen > TCPACKSZMAX) {
++		DHD_TRACE(("%s %d: Too short or long length %d to be TCP ACK\n",
++			__FUNCTION__, __LINE__, pktlen));
++		goto exit;
++	}
++
++	flags = dhd_os_tcpacklock(dhdp);
++	tcpack_sup_mod = dhdp->tcpack_sup_module;
++
++	if (!tcpack_sup_mod) {
++		DHD_ERROR(("%s %d: tcpack suppress module NULL!!\n", __FUNCTION__, __LINE__));
++		ret = BCME_ERROR;
++		dhd_os_tcpackunlock(dhdp, flags);
++		goto exit;
++	}
++	tbl_cnt = tcpack_sup_mod->tcpack_info_cnt;
++	tcpack_info_tbl = tcpack_sup_mod->tcpack_info_tbl;
++
++	ASSERT(tbl_cnt <= TCPACK_INFO_MAXNUM);
++
++	for (i = 0; i < tbl_cnt; i++) {
++		if (tcpack_info_tbl[i].pkt_in_q == pkt) {
++			DHD_TRACE(("%s %d: pkt %p sent out. idx %d, tbl_cnt %d\n",
++				__FUNCTION__, __LINE__, pkt, i, tbl_cnt));
++			/* This pkt is being transmitted so remove the tcp_ack_info of it. */
++			if (i < tbl_cnt - 1) {
++				bcopy(&tcpack_info_tbl[tbl_cnt - 1],
++					&tcpack_info_tbl[i], sizeof(tcpack_info_t));
++			}
++			bzero(&tcpack_info_tbl[tbl_cnt - 1], sizeof(tcpack_info_t));
++			if (--tcpack_sup_mod->tcpack_info_cnt < 0) {
++				DHD_ERROR(("%s %d: ERROR!!! tcp_ack_info_cnt %d\n",
++					__FUNCTION__, __LINE__, tcpack_sup_mod->tcpack_info_cnt));
++				ret = BCME_ERROR;
++			}
++			break;
++		}
++	}
++	dhd_os_tcpackunlock(dhdp, flags);
++
++exit:
++	return ret;
++}
++
++static INLINE bool dhd_tcpdata_psh_acked(dhd_pub_t *dhdp, uint8 *ip_hdr,
++	uint8 *tcp_hdr, uint32 tcp_ack_num)
++{
++	tcpack_sup_module_t *tcpack_sup_mod;
++	int i;
++	tcpdata_info_t *tcpdata_info = NULL;
++	tdata_psh_info_t *tdata_psh_info = NULL;
++	bool ret = FALSE;
++
++	if (dhdp->tcpack_sup_mode != TCPACK_SUP_DELAYTX)
++		goto exit;
++
++	tcpack_sup_mod = dhdp->tcpack_sup_module;
++
++	if (!tcpack_sup_mod) {
++		DHD_ERROR(("%s %d: tcpack suppress module NULL!!\n", __FUNCTION__, __LINE__));
++		goto exit;
++	}
++
++	DHD_TRACE(("%s %d: IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR
++		" TCP port %d %d, ack %u\n", __FUNCTION__, __LINE__,
++		IPV4_ADDR_TO_STR(ntoh32_ua(&ip_hdr[IPV4_SRC_IP_OFFSET])),
++		IPV4_ADDR_TO_STR(ntoh32_ua(&ip_hdr[IPV4_DEST_IP_OFFSET])),
++		ntoh16_ua(&tcp_hdr[TCP_SRC_PORT_OFFSET]),
++		ntoh16_ua(&tcp_hdr[TCP_DEST_PORT_OFFSET]),
++		tcp_ack_num));
++
++	for (i = 0; i < tcpack_sup_mod->tcpdata_info_cnt; i++) {
++		tcpdata_info_t *tcpdata_info_tmp = &tcpack_sup_mod->tcpdata_info_tbl[i];
++		DHD_TRACE(("%s %d: data info[%d], IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR
++			" TCP port %d %d\n", __FUNCTION__, __LINE__, i,
++			IPV4_ADDR_TO_STR(ntoh32_ua(tcpdata_info_tmp->ip_addr.src)),
++			IPV4_ADDR_TO_STR(ntoh32_ua(tcpdata_info_tmp->ip_addr.dst)),
++			ntoh16_ua(tcpdata_info_tmp->tcp_port.src),
++			ntoh16_ua(tcpdata_info_tmp->tcp_port.dst)));
++
++		/* If either IP address or TCP port number does not match, skip. */
++		if (memcmp(&ip_hdr[IPV4_SRC_IP_OFFSET],
++			tcpdata_info_tmp->ip_addr.dst, IPV4_ADDR_LEN) == 0 &&
++			memcmp(&ip_hdr[IPV4_DEST_IP_OFFSET],
++			tcpdata_info_tmp->ip_addr.src, IPV4_ADDR_LEN) == 0 &&
++			memcmp(&tcp_hdr[TCP_SRC_PORT_OFFSET],
++			tcpdata_info_tmp->tcp_port.dst, TCP_PORT_LEN) == 0 &&
++			memcmp(&tcp_hdr[TCP_DEST_PORT_OFFSET],
++			tcpdata_info_tmp->tcp_port.src, TCP_PORT_LEN) == 0) {
++			tcpdata_info = tcpdata_info_tmp;
++			break;
++		}
++	}
++
++	if (tcpdata_info == NULL) {
++		DHD_TRACE(("%s %d: no tcpdata_info!\n", __FUNCTION__, __LINE__));
++		goto exit;
++	}
++
++	if (tcpdata_info->tdata_psh_info_head == NULL) {
++		DHD_TRACE(("%s %d: No PSH DATA to be acked!\n", __FUNCTION__, __LINE__));
++	}
++
++	while ((tdata_psh_info = tcpdata_info->tdata_psh_info_head)) {
++		if (IS_TCPSEQ_GE(tcp_ack_num, tdata_psh_info->end_seq)) {
++			DHD_TRACE(("%s %d: PSH ACKED! %u >= %u\n",
++				__FUNCTION__, __LINE__, tcp_ack_num, tdata_psh_info->end_seq));
++			tcpdata_info->tdata_psh_info_head = tdata_psh_info->next;
++			tdata_psh_info->next = NULL;
++			_tdata_psh_info_pool_enq(tcpack_sup_mod, tdata_psh_info);
++			ret = TRUE;
++		} else
++			break;
++	}
++	if (tdata_psh_info == NULL)
++		tcpdata_info->tdata_psh_info_tail = NULL;
++
++#ifdef DHDTCPACK_SUP_DBG
++	DHD_TRACE(("%s %d: PSH INFO ENQ %d\n",
++		__FUNCTION__, __LINE__, tcpack_sup_mod->psh_info_enq_num));
++#endif /* DHDTCPACK_SUP_DBG */
++
++exit:
++	return ret;
++}
++
++bool
++dhd_tcpack_suppress(dhd_pub_t *dhdp, void *pkt)
++{
++	uint8 *new_ether_hdr;	/* Ethernet header of the new packet */
++	uint16 new_ether_type;	/* Ethernet type of the new packet */
++	uint8 *new_ip_hdr;		/* IP header of the new packet */
++	uint8 *new_tcp_hdr;		/* TCP header of the new packet */
++	uint32 new_ip_hdr_len;	/* IP header length of the new packet */
++	uint32 cur_framelen;
++	uint32 new_tcp_ack_num;		/* TCP acknowledge number of the new packet */
++	uint16 new_ip_total_len;	/* Total length of IP packet for the new packet */
++	uint32 new_tcp_hdr_len;		/* TCP header length of the new packet */
++	tcpack_sup_module_t *tcpack_sup_mod;
++	tcpack_info_t *tcpack_info_tbl;
++	int i;
++	bool ret = FALSE;
++	bool set_dotxinrx = TRUE;
++	unsigned long flags;
++
++
++	if (dhdp->tcpack_sup_mode == TCPACK_SUP_OFF)
++		goto exit;
++
++	new_ether_hdr = PKTDATA(dhdp->osh, pkt);
++	cur_framelen = PKTLEN(dhdp->osh, pkt);
++
++	if (cur_framelen < TCPACKSZMIN || cur_framelen > TCPACKSZMAX) {
++		DHD_TRACE(("%s %d: Too short or long length %d to be TCP ACK\n",
++			__FUNCTION__, __LINE__, cur_framelen));
++		goto exit;
++	}
++
++	new_ether_type = new_ether_hdr[12] << 8 | new_ether_hdr[13];
++
++	if (new_ether_type != ETHER_TYPE_IP) {
++		DHD_TRACE(("%s %d: Not a IP packet 0x%x\n",
++			__FUNCTION__, __LINE__, new_ether_type));
++		goto exit;
++	}
++
++	DHD_TRACE(("%s %d: IP pkt! 0x%x\n", __FUNCTION__, __LINE__, new_ether_type));
++
++	new_ip_hdr = new_ether_hdr + ETHER_HDR_LEN;
++	cur_framelen -= ETHER_HDR_LEN;
++
++	ASSERT(cur_framelen >= IPV4_MIN_HEADER_LEN);
++
++	new_ip_hdr_len = IPV4_HLEN(new_ip_hdr);
++	if (IP_VER(new_ip_hdr) != IP_VER_4 || IPV4_PROT(new_ip_hdr) != IP_PROT_TCP) {
++		DHD_TRACE(("%s %d: Not IPv4 nor TCP! ip ver %d, prot %d\n",
++			__FUNCTION__, __LINE__, IP_VER(new_ip_hdr), IPV4_PROT(new_ip_hdr)));
++		goto exit;
++	}
++
++	new_tcp_hdr = new_ip_hdr + new_ip_hdr_len;
++	cur_framelen -= new_ip_hdr_len;
++
++	ASSERT(cur_framelen >= TCP_MIN_HEADER_LEN);
++
++	DHD_TRACE(("%s %d: TCP pkt!\n", __FUNCTION__, __LINE__));
++
++	/* is it an ack ? Allow only ACK flag, not to suppress others. */
++	if (new_tcp_hdr[TCP_FLAGS_OFFSET] != TCP_FLAG_ACK) {
++		DHD_TRACE(("%s %d: Do not touch TCP flag 0x%x\n",
++			__FUNCTION__, __LINE__, new_tcp_hdr[TCP_FLAGS_OFFSET]));
++		goto exit;
++	}
++
++	new_ip_total_len = ntoh16_ua(&new_ip_hdr[IPV4_PKTLEN_OFFSET]);
++	new_tcp_hdr_len = 4 * TCP_HDRLEN(new_tcp_hdr[TCP_HLEN_OFFSET]);
++
++	/* This packet has TCP data, so just send */
++	if (new_ip_total_len > new_ip_hdr_len + new_tcp_hdr_len) {
++		DHD_TRACE(("%s %d: Do nothing for TCP DATA\n", __FUNCTION__, __LINE__));
++		goto exit;
++	}
++
++	ASSERT(new_ip_total_len == new_ip_hdr_len + new_tcp_hdr_len);
++
++	new_tcp_ack_num = ntoh32_ua(&new_tcp_hdr[TCP_ACK_NUM_OFFSET]);
++
++	DHD_TRACE(("%s %d: TCP ACK with zero DATA length"
++		" IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR" TCP port %d %d\n",
++		__FUNCTION__, __LINE__,
++		IPV4_ADDR_TO_STR(ntoh32_ua(&new_ip_hdr[IPV4_SRC_IP_OFFSET])),
++		IPV4_ADDR_TO_STR(ntoh32_ua(&new_ip_hdr[IPV4_DEST_IP_OFFSET])),
++		ntoh16_ua(&new_tcp_hdr[TCP_SRC_PORT_OFFSET]),
++		ntoh16_ua(&new_tcp_hdr[TCP_DEST_PORT_OFFSET])));
++
++	/* Look for tcp_ack_info that has the same ip src/dst addrs and tcp src/dst ports */
++	flags = dhd_os_tcpacklock(dhdp);
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++	counter_printlog(&tack_tbl);
++	tack_tbl.cnt[0]++;
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++
++	tcpack_sup_mod = dhdp->tcpack_sup_module;
++	tcpack_info_tbl = tcpack_sup_mod->tcpack_info_tbl;
++
++	if (!tcpack_sup_mod) {
++		DHD_ERROR(("%s %d: tcpack suppress module NULL!!\n", __FUNCTION__, __LINE__));
++		ret = BCME_ERROR;
++		dhd_os_tcpackunlock(dhdp, flags);
++		goto exit;
++	}
++
++	if (dhd_tcpdata_psh_acked(dhdp, new_ip_hdr, new_tcp_hdr, new_tcp_ack_num)) {
++		/* This TCPACK is ACK to TCPDATA PSH pkt, so keep set_dotxinrx TRUE */
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++		tack_tbl.cnt[5]++;
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++	} else
++		set_dotxinrx = FALSE;
++
++	for (i = 0; i < tcpack_sup_mod->tcpack_info_cnt; i++) {
++		void *oldpkt;	/* TCPACK packet that is already in txq or DelayQ */
++		uint8 *old_ether_hdr, *old_ip_hdr, *old_tcp_hdr;
++		uint32 old_ip_hdr_len, old_tcp_hdr_len;
++		uint32 old_tcpack_num;	/* TCP ACK number of old TCPACK packet in Q */
++
++		if ((oldpkt = tcpack_info_tbl[i].pkt_in_q) == NULL) {
++			DHD_ERROR(("%s %d: Unexpected error!! cur idx %d, ttl cnt %d\n",
++				__FUNCTION__, __LINE__, i, tcpack_sup_mod->tcpack_info_cnt));
++			break;
++		}
++
++		if (PKTDATA(dhdp->osh, oldpkt) == NULL) {
++			DHD_ERROR(("%s %d: oldpkt data NULL!! cur idx %d, ttl cnt %d\n",
++				__FUNCTION__, __LINE__, i, tcpack_sup_mod->tcpack_info_cnt));
++			break;
++		}
++
++		old_ether_hdr = tcpack_info_tbl[i].pkt_ether_hdr;
++		old_ip_hdr = old_ether_hdr + ETHER_HDR_LEN;
++		old_ip_hdr_len = IPV4_HLEN(old_ip_hdr);
++		old_tcp_hdr = old_ip_hdr + old_ip_hdr_len;
++		old_tcp_hdr_len = 4 * TCP_HDRLEN(old_tcp_hdr[TCP_HLEN_OFFSET]);
++
++		DHD_TRACE(("%s %d: oldpkt %p[%d], IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR
++			" TCP port %d %d\n", __FUNCTION__, __LINE__, oldpkt, i,
++			IPV4_ADDR_TO_STR(ntoh32_ua(&old_ip_hdr[IPV4_SRC_IP_OFFSET])),
++			IPV4_ADDR_TO_STR(ntoh32_ua(&old_ip_hdr[IPV4_DEST_IP_OFFSET])),
++			ntoh16_ua(&old_tcp_hdr[TCP_SRC_PORT_OFFSET]),
++			ntoh16_ua(&old_tcp_hdr[TCP_DEST_PORT_OFFSET])));
++
++		/* If either of IP address or TCP port number does not match, skip.
++		 * Note that src/dst addr fields in ip header are contiguous being 8 bytes in total.
++		 * Also, src/dst port fields in TCP header are contiguous being 4 bytes in total.
++		 */
++		if (memcmp(&new_ip_hdr[IPV4_SRC_IP_OFFSET],
++			&old_ip_hdr[IPV4_SRC_IP_OFFSET], IPV4_ADDR_LEN * 2) ||
++			memcmp(&new_tcp_hdr[TCP_SRC_PORT_OFFSET],
++			&old_tcp_hdr[TCP_SRC_PORT_OFFSET], TCP_PORT_LEN * 2))
++			continue;
++
++		old_tcpack_num = ntoh32_ua(&old_tcp_hdr[TCP_ACK_NUM_OFFSET]);
++
++		if (IS_TCPSEQ_GT(new_tcp_ack_num, old_tcpack_num)) {
++			/* New packet has higher TCP ACK number, so it replaces the old packet */
++			if (new_ip_hdr_len == old_ip_hdr_len &&
++				new_tcp_hdr_len == old_tcp_hdr_len) {
++				ASSERT(memcmp(new_ether_hdr, old_ether_hdr, ETHER_HDR_LEN) == 0);
++				bcopy(new_ip_hdr, old_ip_hdr, new_ip_total_len);
++				PKTFREE(dhdp->osh, pkt, FALSE);
++				DHD_TRACE(("%s %d: TCP ACK replace %u -> %u\n",
++					__FUNCTION__, __LINE__, old_tcpack_num, new_tcp_ack_num));
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++				tack_tbl.cnt[2]++;
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++				ret = TRUE;
++			} else {
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++				tack_tbl.cnt[6]++;
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++				DHD_TRACE(("%s %d: lenth mismatch %d != %d || %d != %d"
++					" ACK %u -> %u\n", __FUNCTION__, __LINE__,
++					new_ip_hdr_len, old_ip_hdr_len,
++					new_tcp_hdr_len, old_tcp_hdr_len,
++					old_tcpack_num, new_tcp_ack_num));
++			}
++		} else if (new_tcp_ack_num == old_tcpack_num) {
++			set_dotxinrx = TRUE;
++			/* TCPACK retransmission */
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++			tack_tbl.cnt[3]++;
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++		} else {
++			DHD_TRACE(("%s %d: ACK number reverse old %u(0x%p) new %u(0x%p)\n",
++				__FUNCTION__, __LINE__, old_tcpack_num, oldpkt,
++				new_tcp_ack_num, pkt));
++		}
++		dhd_os_tcpackunlock(dhdp, flags);
++		goto exit;
++	}
++
++	if (i == tcpack_sup_mod->tcpack_info_cnt && i < TCPACK_INFO_MAXNUM) {
++		/* No TCPACK packet with the same IP addr and TCP port is found
++		 * in tcp_ack_info_tbl. So add this packet to the table.
++		 */
++		DHD_TRACE(("%s %d: Add pkt 0x%p(ether_hdr 0x%p) to tbl[%d]\n",
++			__FUNCTION__, __LINE__, pkt, new_ether_hdr,
++			tcpack_sup_mod->tcpack_info_cnt));
++
++		tcpack_info_tbl[tcpack_sup_mod->tcpack_info_cnt].pkt_in_q = pkt;
++		tcpack_info_tbl[tcpack_sup_mod->tcpack_info_cnt].pkt_ether_hdr = new_ether_hdr;
++		tcpack_sup_mod->tcpack_info_cnt++;
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++		tack_tbl.cnt[1]++;
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++	} else {
++		ASSERT(i == tcpack_sup_mod->tcpack_info_cnt);
++		DHD_TRACE(("%s %d: No empty tcp ack info tbl\n",
++			__FUNCTION__, __LINE__));
++	}
++	dhd_os_tcpackunlock(dhdp, flags);
++
++exit:
++	/* Unless TCPACK_SUP_DELAYTX, dotxinrx is alwasy TRUE, so no need to set here */
++	if (dhdp->tcpack_sup_mode == TCPACK_SUP_DELAYTX && set_dotxinrx)
++		dhd_bus_set_dotxinrx(dhdp->bus, TRUE);
++
++	return ret;
++}
++
++bool
++dhd_tcpdata_info_get(dhd_pub_t *dhdp, void *pkt)
++{
++	uint8 *ether_hdr;	/* Ethernet header of the new packet */
++	uint16 ether_type;	/* Ethernet type of the new packet */
++	uint8 *ip_hdr;		/* IP header of the new packet */
++	uint8 *tcp_hdr;		/* TCP header of the new packet */
++	uint32 ip_hdr_len;	/* IP header length of the new packet */
++	uint32 cur_framelen;
++	uint16 ip_total_len;	/* Total length of IP packet for the new packet */
++	uint32 tcp_hdr_len;		/* TCP header length of the new packet */
++	uint32 tcp_seq_num;		/* TCP sequence number of the new packet */
++	uint16 tcp_data_len;	/* TCP DATA length that excludes IP and TCP headers */
++	uint32 end_tcp_seq_num;	/* TCP seq number of the last byte in the new packet */
++	tcpack_sup_module_t *tcpack_sup_mod;
++	tcpdata_info_t *tcpdata_info = NULL;
++	tdata_psh_info_t *tdata_psh_info;
++
++	int i;
++	bool ret = FALSE;
++	unsigned long flags;
++
++	if (dhdp->tcpack_sup_mode != TCPACK_SUP_DELAYTX)
++		goto exit;
++
++	ether_hdr = PKTDATA(dhdp->osh, pkt);
++	cur_framelen = PKTLEN(dhdp->osh, pkt);
++
++	ether_type = ether_hdr[12] << 8 | ether_hdr[13];
++
++	if (ether_type != ETHER_TYPE_IP) {
++		DHD_TRACE(("%s %d: Not a IP packet 0x%x\n",
++			__FUNCTION__, __LINE__, ether_type));
++		goto exit;
++	}
++
++	DHD_TRACE(("%s %d: IP pkt! 0x%x\n", __FUNCTION__, __LINE__, ether_type));
++
++	ip_hdr = ether_hdr + ETHER_HDR_LEN;
++	cur_framelen -= ETHER_HDR_LEN;
++
++	ASSERT(cur_framelen >= IPV4_MIN_HEADER_LEN);
++
++	ip_hdr_len = IPV4_HLEN(ip_hdr);
++	if (IP_VER(ip_hdr) != IP_VER_4 || IPV4_PROT(ip_hdr) != IP_PROT_TCP) {
++		DHD_TRACE(("%s %d: Not IPv4 nor TCP! ip ver %d, prot %d\n",
++			__FUNCTION__, __LINE__, IP_VER(ip_hdr), IPV4_PROT(ip_hdr)));
++		goto exit;
++	}
++
++	tcp_hdr = ip_hdr + ip_hdr_len;
++	cur_framelen -= ip_hdr_len;
++
++	ASSERT(cur_framelen >= TCP_MIN_HEADER_LEN);
++
++	DHD_TRACE(("%s %d: TCP pkt!\n", __FUNCTION__, __LINE__));
++
++	ip_total_len = ntoh16_ua(&ip_hdr[IPV4_PKTLEN_OFFSET]);
++	tcp_hdr_len = 4 * TCP_HDRLEN(tcp_hdr[TCP_HLEN_OFFSET]);
++
++	/* This packet is mere TCP ACK, so do nothing */
++	if (ip_total_len == ip_hdr_len + tcp_hdr_len) {
++		DHD_TRACE(("%s %d: Do nothing for no data TCP ACK\n", __FUNCTION__, __LINE__));
++		goto exit;
++	}
++
++	ASSERT(ip_total_len > ip_hdr_len + tcp_hdr_len);
++
++	if ((tcp_hdr[TCP_FLAGS_OFFSET] & TCP_FLAG_PSH) == 0) {
++		DHD_TRACE(("%s %d: Not interested TCP DATA packet\n", __FUNCTION__, __LINE__));
++		goto exit;
++	}
++
++	DHD_TRACE(("%s %d: TCP DATA with nonzero DATA length"
++		" IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR" TCP port %d %d, flag 0x%x\n",
++		__FUNCTION__, __LINE__,
++		IPV4_ADDR_TO_STR(ntoh32_ua(&ip_hdr[IPV4_SRC_IP_OFFSET])),
++		IPV4_ADDR_TO_STR(ntoh32_ua(&ip_hdr[IPV4_DEST_IP_OFFSET])),
++		ntoh16_ua(&tcp_hdr[TCP_SRC_PORT_OFFSET]),
++		ntoh16_ua(&tcp_hdr[TCP_DEST_PORT_OFFSET]),
++		tcp_hdr[TCP_FLAGS_OFFSET]));
++
++	flags = dhd_os_tcpacklock(dhdp);
++	tcpack_sup_mod = dhdp->tcpack_sup_module;
++
++	if (!tcpack_sup_mod) {
++		DHD_ERROR(("%s %d: tcpack suppress module NULL!!\n", __FUNCTION__, __LINE__));
++		ret = BCME_ERROR;
++		dhd_os_tcpackunlock(dhdp, flags);
++		goto exit;
++	}
++
++	/* Look for tcpdata_info that has the same ip src/dst addrs and tcp src/dst ports */
++	i = 0;
++	while (i < tcpack_sup_mod->tcpdata_info_cnt) {
++		tcpdata_info_t *tdata_info_tmp = &tcpack_sup_mod->tcpdata_info_tbl[i];
++		uint32 now_in_ms = OSL_SYSUPTIME();
++		DHD_TRACE(("%s %d: data info[%d], IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR
++			" TCP port %d %d\n", __FUNCTION__, __LINE__, i,
++			IPV4_ADDR_TO_STR(ntoh32_ua(tdata_info_tmp->ip_addr.src)),
++			IPV4_ADDR_TO_STR(ntoh32_ua(tdata_info_tmp->ip_addr.dst)),
++			ntoh16_ua(tdata_info_tmp->tcp_port.src),
++			ntoh16_ua(tdata_info_tmp->tcp_port.dst)));
++
++		/* If both IP address and TCP port number match, we found it so break.
++		 * Note that src/dst addr fields in ip header are contiguous being 8 bytes in total.
++		 * Also, src/dst port fields in TCP header are contiguous being 4 bytes in total.
++		 */
++		if (memcmp(&ip_hdr[IPV4_SRC_IP_OFFSET],
++			(void *)&tdata_info_tmp->ip_addr, IPV4_ADDR_LEN * 2) == 0 &&
++			memcmp(&tcp_hdr[TCP_SRC_PORT_OFFSET],
++			(void *)&tdata_info_tmp->tcp_port, TCP_PORT_LEN * 2) == 0) {
++			tcpdata_info = tdata_info_tmp;
++			tcpdata_info->last_used_time = now_in_ms;
++			break;
++		}
++
++		if (now_in_ms - tdata_info_tmp->last_used_time > TCPDATA_INFO_TIMEOUT) {
++			tdata_psh_info_t *tdata_psh_info_tmp;
++			tcpdata_info_t *last_tdata_info;
++
++			while ((tdata_psh_info_tmp = tdata_info_tmp->tdata_psh_info_head)) {
++				tdata_info_tmp->tdata_psh_info_head = tdata_psh_info_tmp->next;
++				tdata_psh_info_tmp->next = NULL;
++				DHD_TRACE(("%s %d: Clean tdata_psh_info(end_seq %u)!\n",
++					__FUNCTION__, __LINE__, tdata_psh_info_tmp->end_seq));
++				_tdata_psh_info_pool_enq(tcpack_sup_mod, tdata_psh_info_tmp);
++			}
++#ifdef DHDTCPACK_SUP_DBG
++			DHD_ERROR(("%s %d: PSH INFO ENQ %d\n",
++				__FUNCTION__, __LINE__, tcpack_sup_mod->psh_info_enq_num));
++#endif /* DHDTCPACK_SUP_DBG */
++			tcpack_sup_mod->tcpdata_info_cnt--;
++			ASSERT(tcpack_sup_mod->tcpdata_info_cnt >= 0);
++
++			last_tdata_info =
++				&tcpack_sup_mod->tcpdata_info_tbl[tcpack_sup_mod->tcpdata_info_cnt];
++			if (i < tcpack_sup_mod->tcpdata_info_cnt) {
++				ASSERT(last_tdata_info != tdata_info_tmp);
++				bcopy(last_tdata_info, tdata_info_tmp, sizeof(tcpdata_info_t));
++			}
++			bzero(last_tdata_info, sizeof(tcpdata_info_t));
++			DHD_INFO(("%s %d: tcpdata_info(idx %d) is aged out. ttl cnt is now %d\n",
++				__FUNCTION__, __LINE__, i, tcpack_sup_mod->tcpdata_info_cnt));
++			/* Don't increase "i" here, so that the prev last tcpdata_info is checked */
++		} else
++			 i++;
++	}
++
++	tcp_seq_num = ntoh32_ua(&tcp_hdr[TCP_SEQ_NUM_OFFSET]);
++	tcp_data_len = ip_total_len - ip_hdr_len - tcp_hdr_len;
++	end_tcp_seq_num = tcp_seq_num + tcp_data_len;
++
++	if (tcpdata_info == NULL) {
++		ASSERT(i == tcpack_sup_mod->tcpdata_info_cnt);
++		if (i >= TCPDATA_INFO_MAXNUM) {
++			DHD_TRACE(("%s %d: tcp_data_info_tbl FULL! %d %d"
++				" IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR" TCP port %d %d\n",
++				__FUNCTION__, __LINE__, i, tcpack_sup_mod->tcpdata_info_cnt,
++				IPV4_ADDR_TO_STR(ntoh32_ua(&ip_hdr[IPV4_SRC_IP_OFFSET])),
++				IPV4_ADDR_TO_STR(ntoh32_ua(&ip_hdr[IPV4_DEST_IP_OFFSET])),
++				ntoh16_ua(&tcp_hdr[TCP_SRC_PORT_OFFSET]),
++				ntoh16_ua(&tcp_hdr[TCP_DEST_PORT_OFFSET])));
++			dhd_os_tcpackunlock(dhdp, flags);
++			goto exit;
++		}
++		tcpdata_info = &tcpack_sup_mod->tcpdata_info_tbl[i];
++
++		/* No TCP flow with the same IP addr and TCP port is found
++		 * in tcp_data_info_tbl. So add this flow to the table.
++		 */
++		DHD_INFO(("%s %d: Add data info to tbl[%d]: IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR
++			" TCP port %d %d\n",
++			__FUNCTION__, __LINE__, tcpack_sup_mod->tcpdata_info_cnt,
++			IPV4_ADDR_TO_STR(ntoh32_ua(&ip_hdr[IPV4_SRC_IP_OFFSET])),
++			IPV4_ADDR_TO_STR(ntoh32_ua(&ip_hdr[IPV4_DEST_IP_OFFSET])),
++			ntoh16_ua(&tcp_hdr[TCP_SRC_PORT_OFFSET]),
++			ntoh16_ua(&tcp_hdr[TCP_DEST_PORT_OFFSET])));
++		/* Note that src/dst addr fields in ip header are contiguous being 8 bytes in total.
++		 * Also, src/dst port fields in TCP header are contiguous being 4 bytes in total.
++		 */
++		bcopy(&ip_hdr[IPV4_SRC_IP_OFFSET], (void *)&tcpdata_info->ip_addr,
++			IPV4_ADDR_LEN * 2);
++		bcopy(&tcp_hdr[TCP_SRC_PORT_OFFSET], (void *)&tcpdata_info->tcp_port,
++			TCP_PORT_LEN * 2);
++
++		tcpdata_info->last_used_time = OSL_SYSUPTIME();
++		tcpack_sup_mod->tcpdata_info_cnt++;
++	}
++
++	ASSERT(tcpdata_info != NULL);
++
++	tdata_psh_info = _tdata_psh_info_pool_deq(tcpack_sup_mod);
++#ifdef DHDTCPACK_SUP_DBG
++	DHD_TRACE(("%s %d: PSH INFO ENQ %d\n",
++		__FUNCTION__, __LINE__, tcpack_sup_mod->psh_info_enq_num));
++#endif /* DHDTCPACK_SUP_DBG */
++
++	if (tdata_psh_info == NULL) {
++		DHD_ERROR(("%s %d: No more free tdata_psh_info!!\n", __FUNCTION__, __LINE__));
++		ret = BCME_ERROR;
++		dhd_os_tcpackunlock(dhdp, flags);
++		goto exit;
++	}
++	tdata_psh_info->end_seq = end_tcp_seq_num;
++
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++	tack_tbl.cnt[4]++;
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++
++	DHD_TRACE(("%s %d: TCP PSH DATA recvd! end seq %u\n",
++		__FUNCTION__, __LINE__, tdata_psh_info->end_seq));
++
++	ASSERT(tdata_psh_info->next == NULL);
++
++	if (tcpdata_info->tdata_psh_info_head == NULL)
++		tcpdata_info->tdata_psh_info_head = tdata_psh_info;
++	else {
++		ASSERT(tcpdata_info->tdata_psh_info_tail);
++		tcpdata_info->tdata_psh_info_tail->next = tdata_psh_info;
++	}
++	tcpdata_info->tdata_psh_info_tail = tdata_psh_info;
++
++	dhd_os_tcpackunlock(dhdp, flags);
++
++exit:
++	return ret;
++}
++
++bool
++dhd_tcpack_hold(dhd_pub_t *dhdp, void *pkt, int ifidx)
++{
++	uint8 *new_ether_hdr;	/* Ethernet header of the new packet */
++	uint16 new_ether_type;	/* Ethernet type of the new packet */
++	uint8 *new_ip_hdr;		/* IP header of the new packet */
++	uint8 *new_tcp_hdr;		/* TCP header of the new packet */
++	uint32 new_ip_hdr_len;	/* IP header length of the new packet */
++	uint32 cur_framelen;
++	uint32 new_tcp_ack_num;		/* TCP acknowledge number of the new packet */
++	uint16 new_ip_total_len;	/* Total length of IP packet for the new packet */
++	uint32 new_tcp_hdr_len;		/* TCP header length of the new packet */
++	tcpack_sup_module_t *tcpack_sup_mod;
++	tcpack_info_t *tcpack_info_tbl;
++	int i, free_slot = TCPACK_INFO_MAXNUM;
++	bool hold = FALSE;
++	unsigned long flags;
++
++	if (dhdp->tcpack_sup_mode != TCPACK_SUP_HOLD) {
++		goto exit;
++	}
++
++	if (dhdp->tcpack_sup_ratio == 1) {
++		goto exit;
++	}
++
++	new_ether_hdr = PKTDATA(dhdp->osh, pkt);
++	cur_framelen = PKTLEN(dhdp->osh, pkt);
++
++	if (cur_framelen < TCPACKSZMIN || cur_framelen > TCPACKSZMAX) {
++		DHD_TRACE(("%s %d: Too short or long length %d to be TCP ACK\n",
++			__FUNCTION__, __LINE__, cur_framelen));
++		goto exit;
++	}
++
++	new_ether_type = new_ether_hdr[12] << 8 | new_ether_hdr[13];
++
++	if (new_ether_type != ETHER_TYPE_IP) {
++		DHD_TRACE(("%s %d: Not a IP packet 0x%x\n",
++			__FUNCTION__, __LINE__, new_ether_type));
++		goto exit;
++	}
++
++	DHD_TRACE(("%s %d: IP pkt! 0x%x\n", __FUNCTION__, __LINE__, new_ether_type));
++
++	new_ip_hdr = new_ether_hdr + ETHER_HDR_LEN;
++	cur_framelen -= ETHER_HDR_LEN;
++
++	ASSERT(cur_framelen >= IPV4_MIN_HEADER_LEN);
++
++	new_ip_hdr_len = IPV4_HLEN(new_ip_hdr);
++	if (IP_VER(new_ip_hdr) != IP_VER_4 || IPV4_PROT(new_ip_hdr) != IP_PROT_TCP) {
++		DHD_TRACE(("%s %d: Not IPv4 nor TCP! ip ver %d, prot %d\n",
++			__FUNCTION__, __LINE__, IP_VER(new_ip_hdr), IPV4_PROT(new_ip_hdr)));
++		goto exit;
++	}
++
++	new_tcp_hdr = new_ip_hdr + new_ip_hdr_len;
++	cur_framelen -= new_ip_hdr_len;
++
++	ASSERT(cur_framelen >= TCP_MIN_HEADER_LEN);
++
++	DHD_TRACE(("%s %d: TCP pkt!\n", __FUNCTION__, __LINE__));
++
++	/* is it an ack ? Allow only ACK flag, not to suppress others. */
++	if (new_tcp_hdr[TCP_FLAGS_OFFSET] != TCP_FLAG_ACK) {
++		DHD_TRACE(("%s %d: Do not touch TCP flag 0x%x\n",
++			__FUNCTION__, __LINE__, new_tcp_hdr[TCP_FLAGS_OFFSET]));
++		goto exit;
++	}
++
++	new_ip_total_len = ntoh16_ua(&new_ip_hdr[IPV4_PKTLEN_OFFSET]);
++	new_tcp_hdr_len = 4 * TCP_HDRLEN(new_tcp_hdr[TCP_HLEN_OFFSET]);
++
++	/* This packet has TCP data, so just send */
++	if (new_ip_total_len > new_ip_hdr_len + new_tcp_hdr_len) {
++		DHD_TRACE(("%s %d: Do nothing for TCP DATA\n", __FUNCTION__, __LINE__));
++		goto exit;
++	}
++
++	ASSERT(new_ip_total_len == new_ip_hdr_len + new_tcp_hdr_len);
++
++	new_tcp_ack_num = ntoh32_ua(&new_tcp_hdr[TCP_ACK_NUM_OFFSET]);
++
++	DHD_TRACE(("%s %d: TCP ACK with zero DATA length"
++		" IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR" TCP port %d %d\n",
++		__FUNCTION__, __LINE__,
++		IPV4_ADDR_TO_STR(ntoh32_ua(&new_ip_hdr[IPV4_SRC_IP_OFFSET])),
++		IPV4_ADDR_TO_STR(ntoh32_ua(&new_ip_hdr[IPV4_DEST_IP_OFFSET])),
++		ntoh16_ua(&new_tcp_hdr[TCP_SRC_PORT_OFFSET]),
++		ntoh16_ua(&new_tcp_hdr[TCP_DEST_PORT_OFFSET])));
++
++	/* Look for tcp_ack_info that has the same ip src/dst addrs and tcp src/dst ports */
++	flags = dhd_os_tcpacklock(dhdp);
++
++	tcpack_sup_mod = dhdp->tcpack_sup_module;
++	tcpack_info_tbl = tcpack_sup_mod->tcpack_info_tbl;
++
++	if (!tcpack_sup_mod) {
++		DHD_ERROR(("%s %d: tcpack suppress module NULL!!\n", __FUNCTION__, __LINE__));
++		dhd_os_tcpackunlock(dhdp, flags);
++		goto exit;
++	}
++
++	hold = TRUE;
++
++	for (i = 0; i < TCPACK_INFO_MAXNUM; i++) {
++		void *oldpkt;	/* TCPACK packet that is already in txq or DelayQ */
++		uint8 *old_ether_hdr, *old_ip_hdr, *old_tcp_hdr;
++		uint32 old_ip_hdr_len, old_tcp_hdr_len;
++		uint32 old_tcpack_num;	/* TCP ACK number of old TCPACK packet in Q */
++
++		if ((oldpkt = tcpack_info_tbl[i].pkt_in_q) == NULL) {
++			if (free_slot == TCPACK_INFO_MAXNUM) {
++				free_slot = i;
++			}
++			continue;
++		}
++
++		if (PKTDATA(dhdp->osh, oldpkt) == NULL) {
++			DHD_ERROR(("%s %d: oldpkt data NULL!! cur idx %d\n",
++				__FUNCTION__, __LINE__, i));
++			hold = FALSE;
++			dhd_os_tcpackunlock(dhdp, flags);
++			goto exit;
++		}
++
++		old_ether_hdr = tcpack_info_tbl[i].pkt_ether_hdr;
++		old_ip_hdr = old_ether_hdr + ETHER_HDR_LEN;
++		old_ip_hdr_len = IPV4_HLEN(old_ip_hdr);
++		old_tcp_hdr = old_ip_hdr + old_ip_hdr_len;
++		old_tcp_hdr_len = 4 * TCP_HDRLEN(old_tcp_hdr[TCP_HLEN_OFFSET]);
++
++		DHD_TRACE(("%s %d: oldpkt %p[%d], IP addr "IPV4_ADDR_STR" "IPV4_ADDR_STR
++			" TCP port %d %d\n", __FUNCTION__, __LINE__, oldpkt, i,
++			IPV4_ADDR_TO_STR(ntoh32_ua(&old_ip_hdr[IPV4_SRC_IP_OFFSET])),
++			IPV4_ADDR_TO_STR(ntoh32_ua(&old_ip_hdr[IPV4_DEST_IP_OFFSET])),
++			ntoh16_ua(&old_tcp_hdr[TCP_SRC_PORT_OFFSET]),
++			ntoh16_ua(&old_tcp_hdr[TCP_DEST_PORT_OFFSET])));
++
++		/* If either of IP address or TCP port number does not match, skip. */
++		if (memcmp(&new_ip_hdr[IPV4_SRC_IP_OFFSET],
++			&old_ip_hdr[IPV4_SRC_IP_OFFSET], IPV4_ADDR_LEN * 2) ||
++			memcmp(&new_tcp_hdr[TCP_SRC_PORT_OFFSET],
++			&old_tcp_hdr[TCP_SRC_PORT_OFFSET], TCP_PORT_LEN * 2)) {
++			continue;
++		}
++
++		old_tcpack_num = ntoh32_ua(&old_tcp_hdr[TCP_ACK_NUM_OFFSET]);
++
++		if (IS_TCPSEQ_GE(new_tcp_ack_num, old_tcpack_num)) {
++			tcpack_info_tbl[i].supp_cnt++;
++			if (tcpack_info_tbl[i].supp_cnt >= dhdp->tcpack_sup_ratio) {
++				tcpack_info_tbl[i].pkt_in_q = NULL;
++				tcpack_info_tbl[i].pkt_ether_hdr = NULL;
++				tcpack_info_tbl[i].ifidx = 0;
++				tcpack_info_tbl[i].supp_cnt = 0;
++				hold = FALSE;
++			} else {
++				tcpack_info_tbl[i].pkt_in_q = pkt;
++				tcpack_info_tbl[i].pkt_ether_hdr = new_ether_hdr;
++				tcpack_info_tbl[i].ifidx = ifidx;
++			}
++			PKTFREE(dhdp->osh, oldpkt, TRUE);
++		} else {
++			PKTFREE(dhdp->osh, pkt, TRUE);
++		}
++		dhd_os_tcpackunlock(dhdp, flags);
++
++		if (!hold) {
++			del_timer_sync(&tcpack_info_tbl[i].timer);
++		}
++		goto exit;
++	}
++
++	if (free_slot < TCPACK_INFO_MAXNUM) {
++		/* No TCPACK packet with the same IP addr and TCP port is found
++		 * in tcp_ack_info_tbl. So add this packet to the table.
++		 */
++		DHD_TRACE(("%s %d: Add pkt 0x%p(ether_hdr 0x%p) to tbl[%d]\n",
++			__FUNCTION__, __LINE__, pkt, new_ether_hdr,
++			free_slot));
++
++		tcpack_info_tbl[free_slot].pkt_in_q = pkt;
++		tcpack_info_tbl[free_slot].pkt_ether_hdr = new_ether_hdr;
++		tcpack_info_tbl[free_slot].ifidx = ifidx;
++		tcpack_info_tbl[free_slot].supp_cnt = 1;
++		mod_timer(&tcpack_sup_mod->tcpack_info_tbl[free_slot].timer,
++			jiffies + msecs_to_jiffies(dhdp->tcpack_sup_delay));
++		tcpack_sup_mod->tcpack_info_cnt++;
++	} else {
++		DHD_TRACE(("%s %d: No empty tcp ack info tbl\n",
++			__FUNCTION__, __LINE__));
++	}
++	dhd_os_tcpackunlock(dhdp, flags);
++
++exit:
++	return hold;
++}
++#endif /* DHDTCPACK_SUPPRESS */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_ip.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_ip.h
+new file mode 100644
+index 000000000..453c9a30b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_ip.h
+@@ -0,0 +1,85 @@
++/*
++ * Header file describing the common ip parser function.
++ *
++ * Provides type definitions and function prototypes used to parse ip packet.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_ip.h 537119 2015-02-25 04:24:14Z $
++ */
++
++#ifndef _dhd_ip_h_
++#define _dhd_ip_h_
++
++#ifdef DHDTCPACK_SUPPRESS
++#include <dngl_stats.h>
++#include <bcmutils.h>
++#include <dhd.h>
++#endif /* DHDTCPACK_SUPPRESS */
++
++typedef enum pkt_frag
++{
++	DHD_PKT_FRAG_NONE = 0,
++	DHD_PKT_FRAG_FIRST,
++	DHD_PKT_FRAG_CONT,
++	DHD_PKT_FRAG_LAST
++} pkt_frag_t;
++
++extern pkt_frag_t pkt_frag_info(osl_t *osh, void *p);
++
++#ifdef DHDTCPACK_SUPPRESS
++#define	TCPACKSZMIN	(ETHER_HDR_LEN + IPV4_MIN_HEADER_LEN + TCP_MIN_HEADER_LEN)
++/* Size of MAX possible TCP ACK packet. Extra bytes for IP/TCP option fields */
++#define	TCPACKSZMAX	(TCPACKSZMIN + 100)
++
++/* Max number of TCP streams that have own src/dst IP addrs and TCP ports */
++#define TCPACK_INFO_MAXNUM 4
++#define TCPDATA_INFO_MAXNUM 4
++#define TCPDATA_PSH_INFO_MAXNUM (8 * TCPDATA_INFO_MAXNUM)
++
++#define TCPDATA_INFO_TIMEOUT 5000	/* Remove tcpdata_info if inactive for this time (in ms) */
++
++#define DEFAULT_TCPACK_SUPP_RATIO 3
++#ifndef CUSTOM_TCPACK_SUPP_RATIO
++#define CUSTOM_TCPACK_SUPP_RATIO DEFAULT_TCPACK_SUPP_RATIO
++#endif /* CUSTOM_TCPACK_SUPP_RATIO */
++
++#define DEFAULT_TCPACK_DELAY_TIME 10 /* ms */
++#ifndef CUSTOM_TCPACK_DELAY_TIME
++#define CUSTOM_TCPACK_DELAY_TIME DEFAULT_TCPACK_DELAY_TIME
++#endif /* CUSTOM_TCPACK_DELAY_TIME */
++
++extern int dhd_tcpack_suppress_set(dhd_pub_t *dhdp, uint8 on);
++extern void dhd_tcpack_info_tbl_clean(dhd_pub_t *dhdp);
++extern int dhd_tcpack_check_xmit(dhd_pub_t *dhdp, void *pkt);
++extern bool dhd_tcpack_suppress(dhd_pub_t *dhdp, void *pkt);
++extern bool dhd_tcpdata_info_get(dhd_pub_t *dhdp, void *pkt);
++extern bool dhd_tcpack_hold(dhd_pub_t *dhdp, void *pkt, int ifidx);
++/* #define DHDTCPACK_SUP_DBG */
++#if defined(DEBUG_COUNTER) && defined(DHDTCPACK_SUP_DBG)
++extern counter_tbl_t tack_tbl;
++#endif /* DEBUG_COUNTER && DHDTCPACK_SUP_DBG */
++#endif /* DHDTCPACK_SUPPRESS */
++
++#endif /* _dhd_ip_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux.c
+new file mode 100644
+index 000000000..3474416fc
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux.c
+@@ -0,0 +1,14067 @@
++/*
++ * Broadcom Dongle Host Driver (DHD), Linux-specific network interface
++ * Basically selected code segments from usb-cdc.c and usb-rndis.c
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_linux.c 709615 2019-02-15 07:37:37Z $
++ */
++
++#include <typedefs.h>
++#include <linuxver.h>
++#include <osl.h>
++#ifdef SHOW_LOGTRACE
++#include <linux/syscalls.h>
++#include <event_log.h>
++#endif /* SHOW_LOGTRACE */
++
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/skbuff.h>
++#include <linux/netdevice.h>
++#include <linux/inetdevice.h>
++#include <linux/rtnetlink.h>
++#include <linux/etherdevice.h>
++#include <linux/random.h>
++#include <linux/spinlock.h>
++#include <linux/ethtool.h>
++#include <linux/fcntl.h>
++#include <linux/fs.h>
++#include <linux/ip.h>
++#include <linux/reboot.h>
++#include <linux/notifier.h>
++#include <net/addrconf.h>
++#ifdef ENABLE_ADAPTIVE_SCHED
++#include <linux/cpufreq.h>
++#endif /* ENABLE_ADAPTIVE_SCHED */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0))
++#include <uapi/linux/sched/types.h>
++#include <linux/sched/signal.h>
++#endif
++#include <asm/uaccess.h>
++#include <asm/unaligned.h>
++
++#include <epivers.h>
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <bcmdevs.h>
++
++#include <proto/ethernet.h>
++#include <proto/bcmevent.h>
++#include <proto/vlan.h>
++#include <proto/802.3.h>
++
++#include <dngl_stats.h>
++#include <dhd_linux_wq.h>
++#include <dhd.h>
++#include <dhd_debug.h>
++#include <dhd_linux.h>
++#ifdef DHD_WET
++#include <dhd_wet.h>
++#endif /* DHD_WET */
++#ifdef PCIE_FULL_DONGLE
++#include <dhd_flowring.h>
++#endif
++#include <dhd_bus.h>
++#include <dhd_proto.h>
++#include <dhd_dbg.h>
++#ifdef CONFIG_HAS_WAKELOCK
++#include <linux/wakelock.h>
++#endif
++#ifdef WL_CFG80211
++#include <wl_cfg80211.h>
++#endif
++#ifdef PNO_SUPPORT
++#include <dhd_pno.h>
++#endif
++#ifdef RTT_SUPPORT
++#include <dhd_rtt.h>
++#endif
++
++#ifdef CONFIG_COMPAT
++#include <linux/compat.h>
++#endif
++
++#ifdef DHD_WMF
++#include <dhd_wmf_linux.h>
++#endif /* DHD_WMF */
++
++#ifdef DHD_L2_FILTER
++#include <proto/bcmicmp.h>
++#include <bcm_l2_filter.h>
++#include <dhd_l2_filter.h>
++#endif /* DHD_L2_FILTER */
++
++#ifdef DHD_PSTA
++#include <dhd_psta.h>
++#endif /* DHD_PSTA */
++
++
++#ifdef DHDTCPACK_SUPPRESS
++#include <dhd_ip.h>
++#endif /* DHDTCPACK_SUPPRESS */
++
++#ifdef DHD_DEBUG_PAGEALLOC
++typedef void (*page_corrupt_cb_t)(void *handle, void *addr_corrupt, size_t len);
++void dhd_page_corrupt_cb(void *handle, void *addr_corrupt, size_t len);
++extern void register_page_corrupt_cb(page_corrupt_cb_t cb, void* handle);
++#endif /* DHD_DEBUG_PAGEALLOC */
++
++
++#if defined(DHD_LB)
++/* Dynamic CPU selection for load balancing */
++#include <linux/cpu.h>
++#include <linux/cpumask.h>
++#include <linux/notifier.h>
++#include <linux/workqueue.h>
++#include <asm/atomic.h>
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0))
++#include <linux/cpuhotplug.h>
++#endif
++
++#if !defined(DHD_LB_PRIMARY_CPUS)
++#define DHD_LB_PRIMARY_CPUS     0x0 /* Big CPU coreids mask */
++#endif
++
++#if !defined(DHD_LB_SECONDARY_CPUS)
++#define DHD_LB_SECONDARY_CPUS   0xFE /* Little CPU coreids mask */
++#endif
++
++#if (NR_CPUS > 8)
++#undef NR_CPUS
++#define NR_CPUS 8
++#endif
++#define HIST_BIN_SIZE	8
++
++#if defined(DHD_LB_RXP)
++static void dhd_rx_napi_dispatcher_fn(struct work_struct * work);
++#endif /* DHD_LB_RXP */
++
++#endif /* DHD_LB */
++
++#ifdef WLMEDIA_HTSF
++#include <linux/time.h>
++#include <htsf.h>
++
++#define HTSF_MINLEN 200    /* min. packet length to timestamp */
++#define HTSF_BUS_DELAY 150 /* assume a fix propagation in us  */
++#define TSMAX  1000        /* max no. of timing record kept   */
++#define NUMBIN 34
++
++static uint32 tsidx = 0;
++static uint32 htsf_seqnum = 0;
++uint32 tsfsync;
++struct timeval tsync;
++static uint32 tsport = 5010;
++
++typedef struct histo_ {
++	uint32 bin[NUMBIN];
++} histo_t;
++
++#if !ISPOWEROF2(DHD_SDALIGN)
++#error DHD_SDALIGN is not a power of 2!
++#endif
++
++static histo_t vi_d1, vi_d2, vi_d3, vi_d4;
++#endif /* WLMEDIA_HTSF */
++
++#ifdef STBLINUX
++#ifdef quote_str
++#undef quote_str
++#endif /* quote_str */
++#ifdef to_str
++#undef to_str
++#endif /* quote_str */
++#define to_str(s) #s
++#define quote_str(s) to_str(s)
++
++static char *driver_target = "driver_target: "quote_str(BRCM_DRIVER_TARGET);
++#endif /* STBLINUX */
++
++
++
++#if defined(SOFTAP)
++extern bool ap_cfg_running;
++extern bool ap_fw_loaded;
++#endif
++
++#ifdef SET_RANDOM_MAC_SOFTAP
++#ifndef CONFIG_DHD_SET_RANDOM_MAC_VAL
++#define CONFIG_DHD_SET_RANDOM_MAC_VAL	0x001A11
++#endif
++static u32 vendor_oui = CONFIG_DHD_SET_RANDOM_MAC_VAL;
++#endif /* SET_RANDOM_MAC_SOFTAP */
++#ifdef ENABLE_ADAPTIVE_SCHED
++#define DEFAULT_CPUFREQ_THRESH		1000000	/* threshold frequency : 1000000 = 1GHz */
++#ifndef CUSTOM_CPUFREQ_THRESH
++#define CUSTOM_CPUFREQ_THRESH	DEFAULT_CPUFREQ_THRESH
++#endif /* CUSTOM_CPUFREQ_THRESH */
++#endif /* ENABLE_ADAPTIVE_SCHED */
++
++/* enable HOSTIP cache update from the host side when an eth0:N is up */
++#define AOE_IP_ALIAS_SUPPORT 1
++
++#ifdef BCM_FD_AGGR
++#include <bcm_rpc.h>
++#include <bcm_rpc_tp.h>
++#endif
++#ifdef PROP_TXSTATUS
++#include <wlfc_proto.h>
++#include <dhd_wlfc.h>
++#endif
++
++#include <wl_android.h>
++
++/* Maximum STA per radio */
++#define DHD_MAX_STA     32
++
++
++
++
++#ifdef HOST_FLAG
++int hostsleep = 0;
++#endif
++
++const uint8 wme_fifo2ac[] = { 0, 1, 2, 3, 1, 1 };
++const uint8 prio2fifo[8] = { 1, 0, 0, 1, 2, 2, 3, 3 };
++#define WME_PRIO2AC(prio)  wme_fifo2ac[prio2fifo[(prio)]]
++
++#ifdef ARP_OFFLOAD_SUPPORT
++void aoe_update_host_ipv4_table(dhd_pub_t *dhd_pub, u32 ipa, bool add, int idx);
++static int dhd_inetaddr_notifier_call(struct notifier_block *this,
++	unsigned long event, void *ptr);
++static struct notifier_block dhd_inetaddr_notifier = {
++	.notifier_call = dhd_inetaddr_notifier_call
++};
++/* to make sure we won't register the same notifier twice, otherwise a loop is likely to be
++ * created in kernel notifier link list (with 'next' pointing to itself)
++ */
++static bool dhd_inetaddr_notifier_registered = FALSE;
++#endif /* ARP_OFFLOAD_SUPPORT */
++
++#if defined(CONFIG_IPV6)
++static int dhd_inet6addr_notifier_call(struct notifier_block *this,
++	unsigned long event, void *ptr);
++static struct notifier_block dhd_inet6addr_notifier = {
++	.notifier_call = dhd_inet6addr_notifier_call
++};
++/* to make sure we won't register the same notifier twice, otherwise a loop is likely to be
++ * created in kernel notifier link list (with 'next' pointing to itself)
++ */
++static bool dhd_inet6addr_notifier_registered = FALSE;
++#endif /* OEM_ANDROID && CONFIG_IPV6 */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_PM_SLEEP)
++#include <linux/suspend.h>
++volatile bool dhd_mmc_suspend = FALSE;
++DECLARE_WAIT_QUEUE_HEAD(dhd_dpc_wait);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_PM_SLEEP) */
++
++#if defined(OOB_INTR_ONLY)
++extern void dhd_enable_oob_intr(struct dhd_bus *bus, bool enable);
++#endif 
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++static void dhd_hang_process(void *dhd_info, void *event_data, u8 event);
++#endif 
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++MODULE_LICENSE("GPL and additional rights");
++#endif /* LinuxVer */
++
++#ifdef BCMDBUS
++#include <dbus.h>
++extern int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex);
++extern void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex);
++extern void dhd_bus_unregister(void);
++
++#ifdef BCMSDIO
++extern bool dhd_bus_dpc(struct dhd_bus *bus);
++#endif /* BCMSDIO */
++#else
++#include <dhd_bus.h>
++#endif /* BCMDBUS */
++
++#ifdef DHD_ULP
++#include <dhd_ulp.h>
++#endif /* DHD_ULP */
++
++#ifdef BCM_FD_AGGR
++#define DBUS_RX_BUFFER_SIZE_DHD(net)	(BCM_RPC_TP_DNGL_AGG_MAX_BYTE)
++#else
++#ifndef PROP_TXSTATUS
++#define DBUS_RX_BUFFER_SIZE_DHD(net)	(net->mtu + net->hard_header_len + dhd->pub.hdrlen)
++#else
++#define DBUS_RX_BUFFER_SIZE_DHD(net)	(net->mtu + net->hard_header_len + dhd->pub.hdrlen + 128)
++#endif
++#endif /* BCM_FD_AGGR */
++
++#ifdef PROP_TXSTATUS
++extern bool dhd_wlfc_skip_fc(void);
++extern void dhd_wlfc_plat_init(void *dhd);
++extern void dhd_wlfc_plat_deinit(void *dhd);
++#endif /* PROP_TXSTATUS */
++
++#if LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 15)
++const char *
++print_tainted()
++{
++	return "";
++}
++#endif	/* LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 15) */
++
++/* Linux wireless extension support */
++#if defined(WL_WIRELESS_EXT)
++#include <wl_iw.h>
++extern wl_iw_extra_params_t  g_wl_iw_params;
++#endif /* defined(WL_WIRELESS_EXT) */
++
++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND)
++#include <linux/earlysuspend.h>
++#endif /* defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++#include <linux/nl80211.h>
++#endif /* OEM_ANDROID && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) */
++
++extern int dhd_get_suspend_bcn_li_dtim(dhd_pub_t *dhd);
++
++#ifdef PKT_FILTER_SUPPORT
++extern void dhd_pktfilter_offload_set(dhd_pub_t * dhd, char *arg);
++extern void dhd_pktfilter_offload_enable(dhd_pub_t * dhd, char *arg, int enable, int master_mode);
++extern void dhd_pktfilter_offload_delete(dhd_pub_t *dhd, int id);
++#endif
++
++
++#ifdef READ_MACADDR
++extern int dhd_read_macaddr(struct dhd_info *dhd);
++#else
++static inline int dhd_read_macaddr(struct dhd_info *dhd) { return 0; }
++#endif
++#ifdef WRITE_MACADDR
++extern int dhd_write_macaddr(struct ether_addr *mac);
++#else
++static inline int dhd_write_macaddr(struct ether_addr *mac) { return 0; }
++#endif
++
++
++
++
++#if defined(TRAFFIC_MGMT_DWM)
++void traffic_mgmt_pkt_set_prio(dhd_pub_t *dhdp, void * pktbuf);
++#endif 
++
++#ifdef DHD_FW_COREDUMP
++static void dhd_mem_dump(void *dhd_info, void *event_info, u8 event);
++int dhd_os_socram_dump(struct net_device *dev, uint32 *dump_size);
++#endif /* DHD_FW_COREDUMP */
++
++static int dhd_reboot_callback(struct notifier_block *this, unsigned long code, void *unused);
++static struct notifier_block dhd_reboot_notifier = {
++	.notifier_call = dhd_reboot_callback,
++	.priority = 1,
++};
++
++#ifdef BCMPCIE
++static int is_reboot = 0;
++#endif /* BCMPCIE */
++
++typedef struct dhd_if_event {
++	struct list_head	list;
++	wl_event_data_if_t	event;
++	char			name[IFNAMSIZ+1];
++	uint8			mac[ETHER_ADDR_LEN];
++} dhd_if_event_t;
++
++/* Interface control information */
++typedef struct dhd_if {
++	struct dhd_info *info;			/* back pointer to dhd_info */
++	/* OS/stack specifics */
++	struct net_device *net;
++	int				idx;			/* iface idx in dongle */
++	uint			subunit;		/* subunit */
++	uint8			mac_addr[ETHER_ADDR_LEN];	/* assigned MAC address */
++	bool			set_macaddress;
++	bool			set_multicast;
++	uint8			bssidx;			/* bsscfg index for the interface */
++	bool			attached;		/* Delayed attachment when unset */
++	bool			txflowcontrol;	/* Per interface flow control indicator */
++	char			name[IFNAMSIZ+1]; /* linux interface name */
++	char			dngl_name[IFNAMSIZ+1]; /* corresponding dongle interface name */
++	struct net_device_stats stats;
++#ifdef DHD_WMF
++	dhd_wmf_t		wmf;		/* per bsscfg wmf setting */
++	bool	wmf_psta_disable;		/* enable/disable MC pkt to each mac
++						 * of MC group behind PSTA
++						 */
++#endif /* DHD_WMF */
++#ifdef PCIE_FULL_DONGLE
++	struct list_head sta_list;		/* sll of associated stations */
++#if !defined(BCM_GMAC3)
++	spinlock_t	sta_list_lock;		/* lock for manipulating sll */
++#endif /* ! BCM_GMAC3 */
++#endif /* PCIE_FULL_DONGLE */
++	uint32  ap_isolate;			/* ap-isolation settings */
++#ifdef DHD_L2_FILTER
++	bool parp_enable;
++	bool parp_discard;
++	bool parp_allnode;
++	arp_table_t *phnd_arp_table;
++/* for Per BSS modification */
++	bool dhcp_unicast;
++	bool block_ping;
++	bool grat_arp;
++#endif /* DHD_L2_FILTER */
++#ifdef DHD_MCAST_REGEN
++	bool mcast_regen_bss_enable;
++#endif
++	bool rx_pkt_chainable;		/* set all rx packet to chainable config by default */
++	cumm_ctr_t cumm_ctr;			/* cummulative queue length of child flowrings */
++} dhd_if_t;
++
++#ifdef WLMEDIA_HTSF
++typedef struct {
++	uint32 low;
++	uint32 high;
++} tsf_t;
++
++typedef struct {
++	uint32 last_cycle;
++	uint32 last_sec;
++	uint32 last_tsf;
++	uint32 coef;     /* scaling factor */
++	uint32 coefdec1; /* first decimal  */
++	uint32 coefdec2; /* second decimal */
++} htsf_t;
++
++typedef struct {
++	uint32 t1;
++	uint32 t2;
++	uint32 t3;
++	uint32 t4;
++} tstamp_t;
++
++static tstamp_t ts[TSMAX];
++static tstamp_t maxdelayts;
++static uint32 maxdelay = 0, tspktcnt = 0, maxdelaypktno = 0;
++
++#endif  /* WLMEDIA_HTSF */
++
++struct ipv6_work_info_t {
++	uint8			if_idx;
++	char			ipv6_addr[16];
++	unsigned long		event;
++};
++
++#ifdef DHD_DEBUG
++typedef struct dhd_dump {
++	uint8 *buf;
++	int bufsize;
++} dhd_dump_t;
++#endif /* DHD_DEBUG */
++
++
++/* When Perimeter locks are deployed, any blocking calls must be preceeded
++ * with a PERIM UNLOCK and followed by a PERIM LOCK.
++ * Examples of blocking calls are: schedule_timeout(), down_interruptible(),
++ * wait_event_timeout().
++ */
++
++/* Local private structure (extension of pub) */
++typedef struct dhd_info {
++#if defined(WL_WIRELESS_EXT)
++	wl_iw_t		iw;		/* wireless extensions state (must be first) */
++#endif /* defined(WL_WIRELESS_EXT) */
++	dhd_pub_t pub;
++	dhd_if_t *iflist[DHD_MAX_IFS]; /* for supporting multiple interfaces */
++
++	void *adapter;			/* adapter information, interrupt, fw path etc. */
++	char fw_path[PATH_MAX];		/* path to firmware image */
++	char nv_path[PATH_MAX];		/* path to nvram vars file */
++
++	struct semaphore proto_sem;
++#ifdef PROP_TXSTATUS
++	spinlock_t	wlfc_spinlock;
++
++#ifdef BCMDBUS
++	ulong		wlfc_lock_flags;
++	ulong		wlfc_pub_lock_flags;
++#endif
++#endif /* PROP_TXSTATUS */
++#ifdef WLMEDIA_HTSF
++	htsf_t  htsf;
++#endif
++	wait_queue_head_t ioctl_resp_wait;
++	wait_queue_head_t d3ack_wait;
++	wait_queue_head_t dhd_bus_busy_state_wait;
++	uint32	default_wd_interval;
++
++	struct timer_list timer;
++	bool wd_timer_valid;
++	struct tasklet_struct tasklet;
++	spinlock_t	sdlock;
++	spinlock_t	txqlock;
++	spinlock_t	dhd_lock;
++#ifdef BCMDBUS
++	ulong		txqlock_flags;
++#else
++
++	struct semaphore sdsem;
++	tsk_ctl_t	thr_dpc_ctl;
++	tsk_ctl_t	thr_wdt_ctl;
++#endif /* BCMDBUS */
++
++	tsk_ctl_t	thr_rxf_ctl;
++	spinlock_t	rxf_lock;
++	bool		rxthread_enabled;
++
++	/* Wakelocks */
++#if defined(CONFIG_HAS_WAKELOCK) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++	struct wake_lock wl_wifi;   /* Wifi wakelock */
++	struct wake_lock wl_rxwake; /* Wifi rx wakelock */
++	struct wake_lock wl_ctrlwake; /* Wifi ctrl wakelock */
++	struct wake_lock wl_wdwake; /* Wifi wd wakelock */
++#ifdef BCMPCIE_OOB_HOST_WAKE
++	struct wake_lock wl_intrwake; /* Host wakeup wakelock */
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#ifdef DHD_USE_SCAN_WAKELOCK
++	struct wake_lock wl_scanwake;  /* Wifi scan wakelock */
++#endif /* DHD_USE_SCAN_WAKELOCK */
++#endif /* CONFIG_HAS_WAKELOCK && LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	/* net_device interface lock, prevent race conditions among net_dev interface
++	 * calls and wifi_on or wifi_off
++	 */
++	struct mutex dhd_net_if_mutex;
++	struct mutex dhd_suspend_mutex;
++#endif
++	spinlock_t wakelock_spinlock;
++	uint32 wakelock_counter;
++	int wakelock_wd_counter;
++	int wakelock_rx_timeout_enable;
++	int wakelock_ctrl_timeout_enable;
++	bool waive_wakelock;
++	uint32 wakelock_before_waive;
++
++	/* Thread to issue ioctl for multicast */
++	wait_queue_head_t ctrl_wait;
++	atomic_t pend_8021x_cnt;
++	dhd_attach_states_t dhd_state;
++#ifdef SHOW_LOGTRACE
++	dhd_event_log_t event_data;
++#endif /* SHOW_LOGTRACE */
++
++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND)
++	struct early_suspend early_suspend;
++#endif /* CONFIG_HAS_EARLYSUSPEND && DHD_USE_EARLYSUSPEND */
++
++#ifdef ARP_OFFLOAD_SUPPORT
++	u32 pend_ipaddr;
++#endif /* ARP_OFFLOAD_SUPPORT */
++#ifdef BCM_FD_AGGR
++	void *rpc_th;
++	void *rpc_osh;
++	struct timer_list rpcth_timer;
++	bool rpcth_timer_active;
++	uint8 fdaggr;
++#endif
++#ifdef DHDTCPACK_SUPPRESS
++	spinlock_t	tcpack_lock;
++#endif /* DHDTCPACK_SUPPRESS */
++	void			*dhd_deferred_wq;
++#ifdef DEBUG_CPU_FREQ
++	struct notifier_block freq_trans;
++	int __percpu *new_freq;
++#endif
++	unsigned int unit;
++	struct notifier_block pm_notifier;
++#ifdef DHD_PSTA
++	uint32	psta_mode;	/* PSTA or PSR */
++#endif /* DHD_PSTA */
++#ifdef DHD_WET
++	uint32	wet_mode;
++#endif /* DHD_PSTA */
++#ifdef DHD_DEBUG
++	dhd_dump_t *dump;
++	struct timer_list join_timer;
++	u32 join_timeout_val;
++	bool join_timer_active;
++	uint scan_time_count;
++	struct timer_list scan_timer;
++	bool scan_timer_active;
++#endif
++
++#if defined(DHD_LB)
++	/* CPU Load Balance dynamic CPU selection */
++
++	/* Variable that tracks the currect CPUs available for candidacy */
++	cpumask_var_t cpumask_curr_avail;
++
++	/* Primary and secondary CPU mask */
++	cpumask_var_t cpumask_primary, cpumask_secondary; /* configuration */
++	cpumask_var_t cpumask_primary_new, cpumask_secondary_new; /* temp */
++
++#if (LINUX_VERSION_CODE  >= KERNEL_VERSION(4, 10, 0))
++	struct hlist_node node_online;
++#else
++	struct notifier_block cpu_notifier;
++#endif
++
++	/* Tasklet to handle Tx Completion packet freeing */
++	struct tasklet_struct tx_compl_tasklet;
++	atomic_t	tx_compl_cpu;
++
++
++	/* Tasklet to handle RxBuf Post during Rx completion */
++	struct tasklet_struct rx_compl_tasklet;
++	atomic_t	rx_compl_cpu;
++
++	/* Napi struct for handling rx packet sendup. Packets are removed from
++	 * H2D RxCompl ring and placed into rx_pend_queue. rx_pend_queue is then
++	 * appended to rx_napi_queue (w/ lock) and the rx_napi_struct is scheduled
++	 * to run to rx_napi_cpu.
++	 */
++	struct sk_buff_head   rx_pend_queue  ____cacheline_aligned;
++	struct sk_buff_head   rx_napi_queue  ____cacheline_aligned;
++	struct napi_struct    rx_napi_struct ____cacheline_aligned;
++	atomic_t	rx_napi_cpu; /* cpu on which the napi is dispatched */
++	struct net_device    *rx_napi_netdev; /* netdev of primary interface */
++
++	struct work_struct    rx_napi_dispatcher_work;
++	struct work_struct    tx_compl_dispatcher_work;
++	struct work_struct    rx_compl_dispatcher_work;
++	/* Number of times DPC Tasklet ran */
++	uint32	dhd_dpc_cnt;
++
++	/* Number of times NAPI processing got scheduled */
++	uint32	napi_sched_cnt;
++
++	/* Number of times NAPI processing ran on each available core */
++	uint32	napi_percpu_run_cnt[NR_CPUS];
++
++	/* Number of times RX Completions got scheduled */
++	uint32	rxc_sched_cnt;
++	/* Number of times RX Completion ran on each available core */
++	uint32	rxc_percpu_run_cnt[NR_CPUS];
++
++	/* Number of times TX Completions got scheduled */
++	uint32	txc_sched_cnt;
++	/* Number of times TX Completions ran on each available core */
++	uint32	txc_percpu_run_cnt[NR_CPUS];
++
++	/* CPU status */
++	/* Number of times each CPU came online */
++	uint32	cpu_online_cnt[NR_CPUS];
++
++	/* Number of times each CPU went offline */
++	uint32	cpu_offline_cnt[NR_CPUS];
++
++	/*
++	 * Consumer Histogram - NAPI RX Packet processing
++	 * -----------------------------------------------
++	 * On Each CPU, when the NAPI RX Packet processing call back was invoked
++	 * how many packets were processed is captured in this data structure.
++	 * Now its difficult to capture the "exact" number of packets processed.
++	 * So considering the packet counter to be a 32 bit one, we have a
++	 * bucket with 8 bins (2^1, 2^2 ... 2^8). The "number" of packets
++	 * processed is rounded off to the next power of 2 and put in the
++	 * approriate "bin" the value in the bin gets incremented.
++	 * For example, assume that in CPU 1 if NAPI Rx runs 3 times
++	 * and the packet count processed is as follows (assume the bin counters are 0)
++	 * iteration 1 - 10 (the bin counter 2^4 increments to 1)
++	 * iteration 2 - 30 (the bin counter 2^5 increments to 1)
++	 * iteration 3 - 15 (the bin counter 2^4 increments by 1 to become 2)
++	 */
++	uint32 napi_rx_hist[NR_CPUS][HIST_BIN_SIZE];
++	uint32 txc_hist[NR_CPUS][HIST_BIN_SIZE];
++	uint32 rxc_hist[NR_CPUS][HIST_BIN_SIZE];
++#endif /* DHD_LB */
++
++#if defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW)
++#if defined(BCMDBUS)
++	struct task_struct *fw_download_task;
++	struct semaphore fw_download_lock;
++#endif /* BCMDBUS */
++#endif /* defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW) */
++	struct net_device *monitor_dev; /* monitor pseudo device */
++	uint monitor_type;   /* monitor pseudo device */
++} dhd_info_t;
++
++#define DHDIF_FWDER(dhdif)      FALSE
++
++/* Flag to indicate if we should download firmware on driver load */
++//uint dhd_download_fw_on_driverload = TRUE;
++uint dhd_download_fw_on_driverload = FALSE;
++
++/* Flag to indicate if driver is initialized */
++uint dhd_driver_init_done = FALSE;
++
++/* Definitions to provide path to the firmware and nvram
++ * example nvram_path[MOD_PARAM_PATHLEN]="/projects/wlan/nvram.txt"
++ */
++char firmware_path[MOD_PARAM_PATHLEN];
++char nvram_path[MOD_PARAM_PATHLEN];
++
++/* backup buffer for firmware and nvram path */
++char fw_bak_path[MOD_PARAM_PATHLEN];
++char nv_bak_path[MOD_PARAM_PATHLEN];
++
++char clm_path[MOD_PARAM_PATHLEN];
++
++module_param_string(clm_path, clm_path, MOD_PARAM_PATHLEN, 0660);
++
++/* information string to keep firmware, chio, cheip version info visiable from log */
++char info_string[MOD_PARAM_INFOLEN];
++module_param_string(info_string, info_string, MOD_PARAM_INFOLEN, 0444);
++int op_mode = 0;
++int disable_proptx = 0;
++module_param(op_mode, int, 0644);
++
++#if defined(DHD_LB_RXP)
++static int dhd_napi_weight = 32;
++module_param(dhd_napi_weight, int, 0644);
++#endif /* DHD_LB_RXP */
++
++extern int wl_control_wl_start(struct net_device *dev);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(BCMLXSDMMC)
++struct semaphore dhd_registration_sem;
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
++
++/* deferred handlers */
++static void dhd_ifadd_event_handler(void *handle, void *event_info, u8 event);
++static void dhd_ifdel_event_handler(void *handle, void *event_info, u8 event);
++static void dhd_set_mac_addr_handler(void *handle, void *event_info, u8 event);
++static void dhd_set_mcast_list_handler(void *handle, void *event_info, u8 event);
++#if defined(CONFIG_IPV6)
++static void dhd_inet6_work_handler(void *dhd_info, void *event_data, u8 event);
++#endif /* OEM_ANDROID && CONFIG_IPV6 */
++#ifdef WL_CFG80211
++extern void dhd_netdev_free(struct net_device *ndev);
++#endif /* WL_CFG80211 */
++
++#if (defined(DHD_WET) || defined(DHD_MCAST_REGEN) || defined(DHD_L2_FILTER))
++/* update rx_pkt_chainable state of dhd interface */
++static void dhd_update_rx_pkt_chainable_state(dhd_pub_t* dhdp, uint32 idx);
++#endif /* DHD_WET || DHD_MCAST_REGEN || DHD_L2_FILTER */
++
++/* Error bits */
++module_param(dhd_msg_level, int, 0);
++
++#ifdef ARP_OFFLOAD_SUPPORT
++/* ARP offload enable */
++uint dhd_arp_enable = TRUE;
++module_param(dhd_arp_enable, uint, 0);
++
++/* ARP offload agent mode : Enable ARP Host Auto-Reply and ARP Peer Auto-Reply */
++
++uint dhd_arp_mode = ARP_OL_AGENT | ARP_OL_PEER_AUTO_REPLY;
++
++module_param(dhd_arp_mode, uint, 0);
++#endif /* ARP_OFFLOAD_SUPPORT */
++
++/* Disable Prop tx */
++module_param(disable_proptx, int, 0644);
++/* load firmware and/or nvram values from the filesystem */
++module_param_string(firmware_path, firmware_path, MOD_PARAM_PATHLEN, 0660);
++module_param_string(nvram_path, nvram_path, MOD_PARAM_PATHLEN, 0660);
++
++/* Watchdog interval */
++
++/* extend watchdog expiration to 2 seconds when DPC is running */
++#define WATCHDOG_EXTEND_INTERVAL (2000)
++
++uint dhd_watchdog_ms = CUSTOM_DHD_WATCHDOG_MS;
++module_param(dhd_watchdog_ms, uint, 0);
++
++#if defined(DHD_DEBUG)
++/* Console poll interval */
++uint dhd_console_ms = 0;
++module_param(dhd_console_ms, uint, 0644);
++#endif /* defined(DHD_DEBUG) */
++
++uint dhd_slpauto = TRUE;
++module_param(dhd_slpauto, uint, 0);
++
++#ifdef PKT_FILTER_SUPPORT
++/* Global Pkt filter enable control */
++uint dhd_pkt_filter_enable = TRUE;
++module_param(dhd_pkt_filter_enable, uint, 0);
++#endif
++
++/* Pkt filter init setup */
++uint dhd_pkt_filter_init = 0;
++module_param(dhd_pkt_filter_init, uint, 0);
++
++/* Pkt filter mode control */
++uint dhd_master_mode = TRUE;
++module_param(dhd_master_mode, uint, 0);
++
++int dhd_watchdog_prio = 0;
++module_param(dhd_watchdog_prio, int, 0);
++
++/* DPC thread priority */
++int dhd_dpc_prio = CUSTOM_DPC_PRIO_SETTING;
++module_param(dhd_dpc_prio, int, 0);
++
++/* RX frame thread priority */
++int dhd_rxf_prio = CUSTOM_RXF_PRIO_SETTING;
++module_param(dhd_rxf_prio, int, 0);
++
++#if !defined(BCMDHDUSB)
++extern int dhd_dongle_ramsize;
++module_param(dhd_dongle_ramsize, int, 0);
++#endif /* BCMDHDUSB */
++
++#ifdef WL_CFG80211
++int passive_channel_skip = 0;
++module_param(passive_channel_skip, int, (S_IRUSR|S_IWUSR));
++#endif /* WL_CFG80211 */
++
++/* Keep track of number of instances */
++static int dhd_found = 0;
++static int instance_base = 0; /* Starting instance number */
++module_param(instance_base, int, 0644);
++
++#ifdef DHD_DHCP_DUMP
++struct bootp_fmt {
++	struct iphdr ip_header;
++	struct udphdr udp_header;
++	uint8 op;
++	uint8 htype;
++	uint8 hlen;
++	uint8 hops;
++	uint32 transaction_id;
++	uint16 secs;
++	uint16 flags;
++	uint32 client_ip;
++	uint32 assigned_ip;
++	uint32 server_ip;
++	uint32 relay_ip;
++	uint8 hw_address[16];
++	uint8 server_name[64];
++	uint8 file_name[128];
++	uint8 options[312];
++};
++
++static const uint8 bootp_magic_cookie[4] = { 99, 130, 83, 99 };
++static const char dhcp_ops[][10] = {
++	"NA", "REQUEST", "REPLY"
++};
++static const char dhcp_types[][10] = {
++	"NA", "DISCOVER", "OFFER", "REQUEST", "DECLINE", "ACK", "NAK", "RELEASE", "INFORM"
++};
++static void dhd_dhcp_dump(uint8 *pktdata, bool tx);
++#endif /* DHD_DHCP_DUMP */
++
++#if defined(DHD_LB)
++
++static void
++dhd_lb_set_default_cpus(dhd_info_t *dhd)
++{
++	/* Default CPU allocation for the jobs */
++	atomic_set(&dhd->rx_napi_cpu, 1);
++	atomic_set(&dhd->rx_compl_cpu, 2);
++	atomic_set(&dhd->tx_compl_cpu, 2);
++}
++
++static void
++dhd_cpumasks_deinit(dhd_info_t *dhd)
++{
++	free_cpumask_var(dhd->cpumask_curr_avail);
++	free_cpumask_var(dhd->cpumask_primary);
++	free_cpumask_var(dhd->cpumask_primary_new);
++	free_cpumask_var(dhd->cpumask_secondary);
++	free_cpumask_var(dhd->cpumask_secondary_new);
++}
++
++static int
++dhd_cpumasks_init(dhd_info_t *dhd)
++{
++	int id;
++	uint32 cpus;
++	int ret = 0;
++
++	if (!alloc_cpumask_var(&dhd->cpumask_curr_avail, GFP_KERNEL) ||
++		!alloc_cpumask_var(&dhd->cpumask_primary, GFP_KERNEL) ||
++		!alloc_cpumask_var(&dhd->cpumask_primary_new, GFP_KERNEL) ||
++		!alloc_cpumask_var(&dhd->cpumask_secondary, GFP_KERNEL) ||
++		!alloc_cpumask_var(&dhd->cpumask_secondary_new, GFP_KERNEL)) {
++		DHD_ERROR(("%s Failed to init cpumasks\n", __FUNCTION__));
++		ret = -ENOMEM;
++		goto fail;
++	}
++
++	cpumask_copy(dhd->cpumask_curr_avail, cpu_online_mask);
++	cpumask_clear(dhd->cpumask_primary);
++	cpumask_clear(dhd->cpumask_secondary);
++
++	cpus = DHD_LB_PRIMARY_CPUS;
++	for (id = 0; id < NR_CPUS; id++) {
++		if (isset(&cpus, id))
++			cpumask_set_cpu(id, dhd->cpumask_primary);
++	}
++
++	cpus = DHD_LB_SECONDARY_CPUS;
++	for (id = 0; id < NR_CPUS; id++) {
++		if (isset(&cpus, id))
++			cpumask_set_cpu(id, dhd->cpumask_secondary);
++	}
++
++	return ret;
++fail:
++	dhd_cpumasks_deinit(dhd);
++	return ret;
++}
++
++/*
++ * The CPU Candidacy Algorithm
++ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~
++ * The available CPUs for selection are divided into two groups
++ *  Primary Set - A CPU mask that carries the First Choice CPUs
++ *  Secondary Set - A CPU mask that carries the Second Choice CPUs.
++ *
++ * There are two types of Job, that needs to be assigned to
++ * the CPUs, from one of the above mentioned CPU group. The Jobs are
++ * 1) Rx Packet Processing - napi_cpu
++ * 2) Completion Processiong (Tx, RX) - compl_cpu
++ *
++ * To begin with both napi_cpu and compl_cpu are on CPU0. Whenever a CPU goes
++ * on-line/off-line the CPU candidacy algorithm is triggerd. The candidacy
++ * algo tries to pickup the first available non boot CPU (CPU0) for napi_cpu.
++ * If there are more processors free, it assigns one to compl_cpu.
++ * It also tries to ensure that both napi_cpu and compl_cpu are not on the same
++ * CPU, as much as possible.
++ *
++ * By design, both Tx and Rx completion jobs are run on the same CPU core, as it
++ * would allow Tx completion skb's to be released into a local free pool from
++ * which the rx buffer posts could have been serviced. it is important to note
++ * that a Tx packet may not have a large enough buffer for rx posting.
++ */
++void dhd_select_cpu_candidacy(dhd_info_t *dhd)
++{
++	uint32 primary_available_cpus; /* count of primary available cpus */
++	uint32 secondary_available_cpus; /* count of secondary available cpus */
++	uint32 napi_cpu = 0; /* cpu selected for napi rx processing */
++	uint32 compl_cpu = 0; /* cpu selected for completion jobs */
++
++	cpumask_clear(dhd->cpumask_primary_new);
++	cpumask_clear(dhd->cpumask_secondary_new);
++
++	/*
++	 * Now select from the primary mask. Even if a Job is
++	 * already running on a CPU in secondary group, we still move
++	 * to primary CPU. So no conditional checks.
++	 */
++	cpumask_and(dhd->cpumask_primary_new, dhd->cpumask_primary,
++		dhd->cpumask_curr_avail);
++
++	cpumask_and(dhd->cpumask_secondary_new, dhd->cpumask_secondary,
++		dhd->cpumask_curr_avail);
++
++	primary_available_cpus = cpumask_weight(dhd->cpumask_primary_new);
++
++	if (primary_available_cpus > 0) {
++		napi_cpu = cpumask_first(dhd->cpumask_primary_new);
++
++		/* If no further CPU is available,
++		 * cpumask_next returns >= nr_cpu_ids
++		 */
++		compl_cpu = cpumask_next(napi_cpu, dhd->cpumask_primary_new);
++		if (compl_cpu >= nr_cpu_ids)
++			compl_cpu = 0;
++	}
++
++	DHD_INFO(("%s After primary CPU check napi_cpu %d compl_cpu %d\n",
++		__FUNCTION__, napi_cpu, compl_cpu));
++
++	/* -- Now check for the CPUs from the secondary mask -- */
++	secondary_available_cpus = cpumask_weight(dhd->cpumask_secondary_new);
++
++	DHD_INFO(("%s Available secondary cpus %d nr_cpu_ids %d\n",
++		__FUNCTION__, secondary_available_cpus, nr_cpu_ids));
++
++	if (secondary_available_cpus > 0) {
++		/* At this point if napi_cpu is unassigned it means no CPU
++		 * is online from Primary Group
++		 */
++		if (napi_cpu == 0) {
++			napi_cpu = cpumask_first(dhd->cpumask_secondary_new);
++			compl_cpu = cpumask_next(napi_cpu, dhd->cpumask_secondary_new);
++		} else if (compl_cpu == 0) {
++			compl_cpu = cpumask_first(dhd->cpumask_secondary_new);
++		}
++
++		/* If no CPU was available for completion, choose CPU 0 */
++		if (compl_cpu >= nr_cpu_ids)
++			compl_cpu = 0;
++	}
++	if ((primary_available_cpus == 0) &&
++		(secondary_available_cpus == 0)) {
++		/* No CPUs available from primary or secondary mask */
++		napi_cpu = 0;
++		compl_cpu = 0;
++	}
++
++	DHD_INFO(("%s After secondary CPU check napi_cpu %d compl_cpu %d\n",
++		__FUNCTION__, napi_cpu, compl_cpu));
++	ASSERT(napi_cpu < nr_cpu_ids);
++	ASSERT(compl_cpu < nr_cpu_ids);
++
++	atomic_set(&dhd->rx_napi_cpu, napi_cpu);
++	atomic_set(&dhd->tx_compl_cpu, compl_cpu);
++	atomic_set(&dhd->rx_compl_cpu, compl_cpu);
++	return;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0))
++int dhd_cpuhp_online(unsigned int cpu, struct hlist_node *node)
++{
++	dhd_info_t *dhd = hlist_entry_safe(node, dhd_info_t,
++				node_online);
++
++	DHD_INFO(("%s: cpu=%d\n", __func__, cpu));
++	DHD_LB_STATS_INCR(dhd->cpu_online_cnt[cpu]);
++	cpumask_set_cpu(cpu, dhd->cpumask_curr_avail);
++	dhd_select_cpu_candidacy(dhd);
++	return 0;
++}
++
++int dhd_cpuhp_dead(unsigned int cpu, struct hlist_node *node)
++{
++	dhd_info_t *dhd = hlist_entry_safe(node, dhd_info_t,
++				node_online);
++
++	DHD_INFO(("%s: cpu=%d\n", __func__, cpu));
++	DHD_LB_STATS_INCR(dhd->cpu_offline_cnt[cpu]);
++	cpumask_clear_cpu(cpu, dhd->cpumask_curr_avail);
++	dhd_select_cpu_candidacy(dhd);
++	return 0;
++}
++#else
++/*
++ * Function to handle CPU Hotplug notifications.
++ * One of the task it does is to trigger the CPU Candidacy algorithm
++ * for load balancing.
++ */
++int
++dhd_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
++{
++	unsigned int cpu = (unsigned int)(long)hcpu;
++
++	dhd_info_t *dhd = container_of(nfb, dhd_info_t, cpu_notifier);
++
++	switch (action)
++	{
++		case CPU_ONLINE:
++			DHD_LB_STATS_INCR(dhd->cpu_online_cnt[cpu]);
++			cpumask_set_cpu(cpu, dhd->cpumask_curr_avail);
++			dhd_select_cpu_candidacy(dhd);
++			break;
++
++		case CPU_DOWN_PREPARE:
++		case CPU_DOWN_PREPARE_FROZEN:
++			DHD_LB_STATS_INCR(dhd->cpu_offline_cnt[cpu]);
++			cpumask_clear_cpu(cpu, dhd->cpumask_curr_avail);
++			dhd_select_cpu_candidacy(dhd);
++			break;
++		default:
++			break;
++	}
++
++	return NOTIFY_OK;
++}
++#endif
++
++#if defined(DHD_LB_STATS)
++void dhd_lb_stats_init(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd;
++	int i, j;
++
++	if (dhdp == NULL) {
++		DHD_ERROR(("%s(): Invalid argument dhdp is NULL \n",
++			__FUNCTION__));
++		return;
++	}
++
++	dhd = dhdp->info;
++	if (dhd == NULL) {
++		DHD_ERROR(("%s(): DHD pointer is NULL \n", __FUNCTION__));
++		return;
++	}
++
++	DHD_LB_STATS_CLR(dhd->dhd_dpc_cnt);
++	DHD_LB_STATS_CLR(dhd->napi_sched_cnt);
++	DHD_LB_STATS_CLR(dhd->rxc_sched_cnt);
++	DHD_LB_STATS_CLR(dhd->txc_sched_cnt);
++
++	for (i = 0; i < NR_CPUS; i++) {
++		DHD_LB_STATS_CLR(dhd->napi_percpu_run_cnt[i]);
++		DHD_LB_STATS_CLR(dhd->rxc_percpu_run_cnt[i]);
++		DHD_LB_STATS_CLR(dhd->txc_percpu_run_cnt[i]);
++
++		DHD_LB_STATS_CLR(dhd->cpu_online_cnt[i]);
++		DHD_LB_STATS_CLR(dhd->cpu_offline_cnt[i]);
++	}
++
++	for (i = 0; i < NR_CPUS; i++) {
++		for (j = 0; j < HIST_BIN_SIZE; j++) {
++			DHD_LB_STATS_CLR(dhd->napi_rx_hist[i][j]);
++			DHD_LB_STATS_CLR(dhd->txc_hist[i][j]);
++			DHD_LB_STATS_CLR(dhd->rxc_hist[i][j]);
++		}
++	}
++
++	return;
++}
++
++static void dhd_lb_stats_dump_histo(
++	struct bcmstrbuf *strbuf, uint32 (*hist)[HIST_BIN_SIZE])
++{
++	int i, j;
++	uint32 per_cpu_total[NR_CPUS] = {0};
++	uint32 total = 0;
++
++	bcm_bprintf(strbuf, "CPU: \t\t");
++	for (i = 0; i < num_possible_cpus(); i++)
++		bcm_bprintf(strbuf, "%d\t", i);
++	bcm_bprintf(strbuf, "\nBin\n");
++
++	for (i = 0; i < HIST_BIN_SIZE; i++) {
++		bcm_bprintf(strbuf, "%d:\t\t", 1<<(i+1));
++		for (j = 0; j < num_possible_cpus(); j++) {
++			bcm_bprintf(strbuf, "%d\t", hist[j][i]);
++		}
++		bcm_bprintf(strbuf, "\n");
++	}
++	bcm_bprintf(strbuf, "Per CPU Total \t");
++	total = 0;
++	for (i = 0; i < num_possible_cpus(); i++) {
++		for (j = 0; j < HIST_BIN_SIZE; j++) {
++			per_cpu_total[i] += (hist[i][j] * (1<<(j+1)));
++		}
++		bcm_bprintf(strbuf, "%d\t", per_cpu_total[i]);
++		total += per_cpu_total[i];
++	}
++	bcm_bprintf(strbuf, "\nTotal\t\t%d \n", total);
++
++	return;
++}
++
++static inline void dhd_lb_stats_dump_cpu_array(struct bcmstrbuf *strbuf, uint32 *p)
++{
++	int i;
++
++	bcm_bprintf(strbuf, "CPU: \t");
++	for (i = 0; i < num_possible_cpus(); i++)
++		bcm_bprintf(strbuf, "%d\t", i);
++	bcm_bprintf(strbuf, "\n");
++
++	bcm_bprintf(strbuf, "Val: \t");
++	for (i = 0; i < num_possible_cpus(); i++)
++		bcm_bprintf(strbuf, "%u\t", *(p+i));
++	bcm_bprintf(strbuf, "\n");
++	return;
++}
++
++void dhd_lb_stats_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
++{
++	dhd_info_t *dhd;
++
++	if (dhdp == NULL || strbuf == NULL) {
++		DHD_ERROR(("%s(): Invalid argument dhdp %p strbuf %p \n",
++			__FUNCTION__, dhdp, strbuf));
++		return;
++	}
++
++	dhd = dhdp->info;
++	if (dhd == NULL) {
++		DHD_ERROR(("%s(): DHD pointer is NULL \n", __FUNCTION__));
++		return;
++	}
++
++	bcm_bprintf(strbuf, "\ncpu_online_cnt:\n");
++	dhd_lb_stats_dump_cpu_array(strbuf, dhd->cpu_online_cnt);
++
++	bcm_bprintf(strbuf, "cpu_offline_cnt:\n");
++	dhd_lb_stats_dump_cpu_array(strbuf, dhd->cpu_offline_cnt);
++
++	bcm_bprintf(strbuf, "\nsched_cnt: dhd_dpc %u napi %u rxc %u txc %u\n",
++		dhd->dhd_dpc_cnt, dhd->napi_sched_cnt, dhd->rxc_sched_cnt,
++		dhd->txc_sched_cnt);
++#ifdef DHD_LB_RXP
++	bcm_bprintf(strbuf, "napi_percpu_run_cnt:\n");
++	dhd_lb_stats_dump_cpu_array(strbuf, dhd->napi_percpu_run_cnt);
++	bcm_bprintf(strbuf, "\nNAPI Packets Received Histogram:\n");
++	dhd_lb_stats_dump_histo(strbuf, dhd->napi_rx_hist);
++#endif /* DHD_LB_RXP */
++
++#ifdef DHD_LB_RXC
++	bcm_bprintf(strbuf, "rxc_percpu_run_cnt:\n");
++	dhd_lb_stats_dump_cpu_array(strbuf, dhd->rxc_percpu_run_cnt);
++	bcm_bprintf(strbuf, "\nRX Completions (Buffer Post) Histogram:\n");
++	dhd_lb_stats_dump_histo(strbuf, dhd->rxc_hist);
++#endif /* DHD_LB_RXC */
++
++
++#ifdef DHD_LB_TXC
++	bcm_bprintf(strbuf, "txc_percpu_run_cnt:\n");
++	dhd_lb_stats_dump_cpu_array(strbuf, dhd->txc_percpu_run_cnt);
++	bcm_bprintf(strbuf, "\nTX Completions (Buffer Free) Histogram:\n");
++	dhd_lb_stats_dump_histo(strbuf, dhd->txc_hist);
++#endif /* DHD_LB_TXC */
++}
++
++static void dhd_lb_stats_update_histo(uint32 *bin, uint32 count)
++{
++	uint32 bin_power;
++	uint32 *p = NULL;
++
++	bin_power = next_larger_power2(count);
++
++	switch (bin_power) {
++		case   0: break;
++		case   1: /* Fall through intentionally */
++		case   2: p = bin + 0; break;
++		case   4: p = bin + 1; break;
++		case   8: p = bin + 2; break;
++		case  16: p = bin + 3; break;
++		case  32: p = bin + 4; break;
++		case  64: p = bin + 5; break;
++		case 128: p = bin + 6; break;
++		default : p = bin + 7; break;
++	}
++	if (p)
++		*p = *p + 1;
++	return;
++}
++
++extern void dhd_lb_stats_update_napi_histo(dhd_pub_t *dhdp, uint32 count)
++{
++	int cpu;
++	dhd_info_t *dhd = dhdp->info;
++
++	cpu = get_cpu();
++	put_cpu();
++	dhd_lb_stats_update_histo(&dhd->napi_rx_hist[cpu][0], count);
++
++	return;
++}
++
++extern void dhd_lb_stats_update_txc_histo(dhd_pub_t *dhdp, uint32 count)
++{
++	int cpu;
++	dhd_info_t *dhd = dhdp->info;
++
++	cpu = get_cpu();
++	put_cpu();
++	dhd_lb_stats_update_histo(&dhd->txc_hist[cpu][0], count);
++
++	return;
++}
++
++extern void dhd_lb_stats_update_rxc_histo(dhd_pub_t *dhdp, uint32 count)
++{
++	int cpu;
++	dhd_info_t *dhd = dhdp->info;
++
++	cpu = get_cpu();
++	put_cpu();
++	dhd_lb_stats_update_histo(&dhd->rxc_hist[cpu][0], count);
++
++	return;
++}
++
++extern void dhd_lb_stats_txc_percpu_cnt_incr(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++	DHD_LB_STATS_PERCPU_ARR_INCR(dhd->txc_percpu_run_cnt);
++}
++
++extern void dhd_lb_stats_rxc_percpu_cnt_incr(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++	DHD_LB_STATS_PERCPU_ARR_INCR(dhd->rxc_percpu_run_cnt);
++}
++
++#endif /* DHD_LB_STATS */
++#endif /* DHD_LB */
++
++
++
++static int dhd_get_pend_8021x_cnt(dhd_info_t *dhd);
++
++/* DHD Perimiter lock only used in router with bypass forwarding. */
++#define DHD_PERIM_RADIO_INIT()              do { /* noop */ } while (0)
++#define DHD_PERIM_LOCK_TRY(unit, flag)      do { /* noop */ } while (0)
++#define DHD_PERIM_UNLOCK_TRY(unit, flag)    do { /* noop */ } while (0)
++
++#ifdef PCIE_FULL_DONGLE
++#if defined(BCM_GMAC3)
++#define DHD_IF_STA_LIST_LOCK_INIT(ifp)      do { /* noop */ } while (0)
++#define DHD_IF_STA_LIST_LOCK(ifp, flags)    ({ BCM_REFERENCE(flags); })
++#define DHD_IF_STA_LIST_UNLOCK(ifp, flags)  ({ BCM_REFERENCE(flags); })
++
++#if defined(DHD_IGMP_UCQUERY) || defined(DHD_UCAST_UPNP)
++#define DHD_IF_WMF_UCFORWARD_LOCK(dhd, ifp, slist) ({ BCM_REFERENCE(slist); &(ifp)->sta_list; })
++#define DHD_IF_WMF_UCFORWARD_UNLOCK(dhd, slist) ({ BCM_REFERENCE(slist); })
++#endif /* DHD_IGMP_UCQUERY || DHD_UCAST_UPNP */
++
++#else /* ! BCM_GMAC3 */
++#define DHD_IF_STA_LIST_LOCK_INIT(ifp) spin_lock_init(&(ifp)->sta_list_lock)
++#define DHD_IF_STA_LIST_LOCK(ifp, flags) \
++	spin_lock_irqsave(&(ifp)->sta_list_lock, (flags))
++#define DHD_IF_STA_LIST_UNLOCK(ifp, flags) \
++	spin_unlock_irqrestore(&(ifp)->sta_list_lock, (flags))
++
++#if defined(DHD_IGMP_UCQUERY) || defined(DHD_UCAST_UPNP)
++static struct list_head * dhd_sta_list_snapshot(dhd_info_t *dhd, dhd_if_t *ifp,
++	struct list_head *snapshot_list);
++static void dhd_sta_list_snapshot_free(dhd_info_t *dhd, struct list_head *snapshot_list);
++#define DHD_IF_WMF_UCFORWARD_LOCK(dhd, ifp, slist) ({ dhd_sta_list_snapshot(dhd, ifp, slist); })
++#define DHD_IF_WMF_UCFORWARD_UNLOCK(dhd, slist) ({ dhd_sta_list_snapshot_free(dhd, slist); })
++#endif /* DHD_IGMP_UCQUERY || DHD_UCAST_UPNP */
++
++#endif /* ! BCM_GMAC3 */
++#endif /* PCIE_FULL_DONGLE */
++
++/* Control fw roaming */
++uint dhd_roam_disable = 0;
++
++#ifdef BCMDBGFS
++extern int dhd_dbg_init(dhd_pub_t *dhdp);
++extern void dhd_dbg_remove(void);
++#endif
++
++/* Control radio state */
++uint dhd_radio_up = 1;
++
++/* Network inteface name */
++char iface_name[IFNAMSIZ] = {'\0'};
++module_param_string(iface_name, iface_name, IFNAMSIZ, 0);
++
++/* The following are specific to the SDIO dongle */
++
++/* IOCTL response timeout */
++int dhd_ioctl_timeout_msec = IOCTL_RESP_TIMEOUT;
++
++/* Idle timeout for backplane clock */
++int dhd_idletime = DHD_IDLETIME_TICKS;
++module_param(dhd_idletime, int, 0);
++
++/* Use polling */
++uint dhd_poll = FALSE;
++module_param(dhd_poll, uint, 0);
++
++/* Use interrupts */
++uint dhd_intr = TRUE;
++module_param(dhd_intr, uint, 0);
++
++/* SDIO Drive Strength (in milliamps) */
++uint dhd_sdiod_drive_strength = 6;
++module_param(dhd_sdiod_drive_strength, uint, 0);
++
++#ifdef BCMSDIO
++/* Tx/Rx bounds */
++extern uint dhd_txbound;
++extern uint dhd_rxbound;
++module_param(dhd_txbound, uint, 0);
++module_param(dhd_rxbound, uint, 0);
++
++/* Deferred transmits */
++extern uint dhd_deferred_tx;
++module_param(dhd_deferred_tx, uint, 0);
++
++#endif /* BCMSDIO */
++
++
++#ifdef SDTEST
++/* Echo packet generator (pkts/s) */
++uint dhd_pktgen = 0;
++module_param(dhd_pktgen, uint, 0);
++
++/* Echo packet len (0 => sawtooth, max 2040) */
++uint dhd_pktgen_len = 0;
++module_param(dhd_pktgen_len, uint, 0);
++#endif /* SDTEST */
++
++
++
++#ifndef BCMDBUS
++/* Allow delayed firmware download for debug purpose */
++int allow_delay_fwdl = FALSE;
++module_param(allow_delay_fwdl, int, 0);
++#endif /* !BCMDBUS */
++
++/* Flag to indicate whether FW download has succeeded */
++bool dhd_fw_downloaded = FALSE;
++
++extern char dhd_version[];
++
++int dhd_net_bus_devreset(struct net_device *dev, uint8 flag);
++static void dhd_net_if_lock_local(dhd_info_t *dhd);
++static void dhd_net_if_unlock_local(dhd_info_t *dhd);
++static void dhd_suspend_lock(dhd_pub_t *dhdp);
++static void dhd_suspend_unlock(dhd_pub_t *dhdp);
++
++#ifdef WLMEDIA_HTSF
++void htsf_update(dhd_info_t *dhd, void *data);
++tsf_t prev_tsf, cur_tsf;
++
++uint32 dhd_get_htsf(dhd_info_t *dhd, int ifidx);
++static int dhd_ioctl_htsf_get(dhd_info_t *dhd, int ifidx);
++static void dhd_dump_latency(void);
++static void dhd_htsf_addtxts(dhd_pub_t *dhdp, void *pktbuf);
++static void dhd_htsf_addrxts(dhd_pub_t *dhdp, void *pktbuf);
++static void dhd_dump_htsfhisto(histo_t *his, char *s);
++#endif /* WLMEDIA_HTSF */
++
++/* Monitor interface */
++int dhd_monitor_init(void *dhd_pub);
++int dhd_monitor_uninit(void);
++
++
++#if defined(WL_WIRELESS_EXT)
++struct iw_statistics *dhd_get_wireless_stats(struct net_device *dev);
++#endif /* defined(WL_WIRELESS_EXT) */
++
++#ifndef BCMDBUS
++static void dhd_dpc(ulong data);
++#endif
++/* forward decl */
++extern int dhd_wait_pend8021x(struct net_device *dev);
++void dhd_os_wd_timer_extend(void *bus, bool extend);
++
++#ifdef TOE
++#ifndef BDC
++#error TOE requires BDC
++#endif /* !BDC */
++static int dhd_toe_get(dhd_info_t *dhd, int idx, uint32 *toe_ol);
++static int dhd_toe_set(dhd_info_t *dhd, int idx, uint32 toe_ol);
++#endif /* TOE */
++#ifdef BCMDBUS
++int dhd_dbus_txdata(dhd_pub_t *dhdp, void *pktbuf);
++#endif
++
++static int dhd_wl_host_event(dhd_info_t *dhd, int *ifidx, void *pktdata,
++                             wl_event_msg_t *event_ptr, void **data_ptr);
++
++#if defined(CONFIG_PM_SLEEP)
++static int dhd_pm_callback(struct notifier_block *nfb, unsigned long action, void *ignored)
++{
++	int ret = NOTIFY_DONE;
++	bool suspend = FALSE;
++	dhd_info_t *dhdinfo = (dhd_info_t*)container_of(nfb, struct dhd_info, pm_notifier);
++
++	BCM_REFERENCE(dhdinfo);
++
++	switch (action) {
++	case PM_HIBERNATION_PREPARE:
++	case PM_SUSPEND_PREPARE:
++		suspend = TRUE;
++		break;
++
++	case PM_POST_HIBERNATION:
++	case PM_POST_SUSPEND:
++		suspend = FALSE;
++		break;
++	}
++
++#if defined(SUPPORT_P2P_GO_PS)
++#ifdef PROP_TXSTATUS
++	if (suspend) {
++		DHD_OS_WAKE_LOCK_WAIVE(&dhdinfo->pub);
++		dhd_wlfc_suspend(&dhdinfo->pub);
++		DHD_OS_WAKE_LOCK_RESTORE(&dhdinfo->pub);
++	} else
++		dhd_wlfc_resume(&dhdinfo->pub);
++#endif
++#endif /* defined(SUPPORT_P2P_GO_PS) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && (LINUX_VERSION_CODE <= \
++	KERNEL_VERSION(2, 6, 39))
++	dhd_mmc_suspend = suspend;
++	smp_mb();
++#endif
++
++	return ret;
++}
++
++/* to make sure we won't register the same notifier twice, otherwise a loop is likely to be
++ * created in kernel notifier link list (with 'next' pointing to itself)
++ */
++static bool dhd_pm_notifier_registered = FALSE;
++
++extern int register_pm_notifier(struct notifier_block *nb);
++extern int unregister_pm_notifier(struct notifier_block *nb);
++#endif /* CONFIG_PM_SLEEP */
++
++/* Request scheduling of the bus rx frame */
++static void dhd_sched_rxf(dhd_pub_t *dhdp, void *skb);
++static void dhd_os_rxflock(dhd_pub_t *pub);
++static void dhd_os_rxfunlock(dhd_pub_t *pub);
++
++/** priv_link is the link between netdev and the dhdif and dhd_info structs. */
++typedef struct dhd_dev_priv {
++	dhd_info_t * dhd; /* cached pointer to dhd_info in netdevice priv */
++	dhd_if_t   * ifp; /* cached pointer to dhd_if in netdevice priv */
++	int          ifidx; /* interface index */
++	void       * lkup;
++} dhd_dev_priv_t;
++
++#define DHD_DEV_PRIV_SIZE       (sizeof(dhd_dev_priv_t))
++#define DHD_DEV_PRIV(dev)       ((dhd_dev_priv_t *)DEV_PRIV(dev))
++#define DHD_DEV_INFO(dev)       (((dhd_dev_priv_t *)DEV_PRIV(dev))->dhd)
++#define DHD_DEV_IFP(dev)        (((dhd_dev_priv_t *)DEV_PRIV(dev))->ifp)
++#define DHD_DEV_IFIDX(dev)      (((dhd_dev_priv_t *)DEV_PRIV(dev))->ifidx)
++#define DHD_DEV_LKUP(dev)		(((dhd_dev_priv_t *)DEV_PRIV(dev))->lkup)
++
++/** Clear the dhd net_device's private structure. */
++static inline void
++dhd_dev_priv_clear(struct net_device * dev)
++{
++	dhd_dev_priv_t * dev_priv;
++	ASSERT(dev != (struct net_device *)NULL);
++	dev_priv = DHD_DEV_PRIV(dev);
++	dev_priv->dhd = (dhd_info_t *)NULL;
++	dev_priv->ifp = (dhd_if_t *)NULL;
++	dev_priv->ifidx = DHD_BAD_IF;
++	dev_priv->lkup = (void *)NULL;
++}
++
++/** Setup the dhd net_device's private structure. */
++static inline void
++dhd_dev_priv_save(struct net_device * dev, dhd_info_t * dhd, dhd_if_t * ifp,
++                  int ifidx)
++{
++	dhd_dev_priv_t * dev_priv;
++	ASSERT(dev != (struct net_device *)NULL);
++	dev_priv = DHD_DEV_PRIV(dev);
++	dev_priv->dhd = dhd;
++	dev_priv->ifp = ifp;
++	dev_priv->ifidx = ifidx;
++}
++
++#ifdef PCIE_FULL_DONGLE
++
++/** Dummy objects are defined with state representing bad|down.
++ * Performance gains from reducing branch conditionals, instruction parallelism,
++ * dual issue, reducing load shadows, avail of larger pipelines.
++ * Use DHD_XXX_NULL instead of (dhd_xxx_t *)NULL, whenever an object pointer
++ * is accessed via the dhd_sta_t.
++ */
++
++/* Dummy dhd_info object */
++dhd_info_t dhd_info_null = {
++#if defined(BCM_GMAC3)
++	.fwdh = FWDER_NULL,
++#endif
++	.pub = {
++	         .info = &dhd_info_null,
++#ifdef DHDTCPACK_SUPPRESS
++	         .tcpack_sup_mode = TCPACK_SUP_REPLACE,
++#endif /* DHDTCPACK_SUPPRESS */
++#if defined(TRAFFIC_MGMT_DWM)
++	         .dhd_tm_dwm_tbl = { .dhd_dwm_enabled = TRUE },
++#endif
++	         .up = FALSE,
++	         .busstate = DHD_BUS_DOWN
++	}
++};
++#define DHD_INFO_NULL (&dhd_info_null)
++#define DHD_PUB_NULL  (&dhd_info_null.pub)
++
++/* Dummy netdevice object */
++struct net_device dhd_net_dev_null = {
++	.reg_state = NETREG_UNREGISTERED
++};
++#define DHD_NET_DEV_NULL (&dhd_net_dev_null)
++
++/* Dummy dhd_if object */
++dhd_if_t dhd_if_null = {
++#if defined(BCM_GMAC3)
++	.fwdh = FWDER_NULL,
++#endif
++#ifdef WMF
++	.wmf = { .wmf_enable = TRUE },
++#endif
++	.info = DHD_INFO_NULL,
++	.net = DHD_NET_DEV_NULL,
++	.idx = DHD_BAD_IF
++};
++#define DHD_IF_NULL  (&dhd_if_null)
++
++#define DHD_STA_NULL ((dhd_sta_t *)NULL)
++
++/** Interface STA list management. */
++
++/** Fetch the dhd_if object, given the interface index in the dhd. */
++static inline dhd_if_t *dhd_get_ifp(dhd_pub_t *dhdp, uint32 ifidx);
++
++/** Alloc/Free a dhd_sta object from the dhd instances' sta_pool. */
++static void dhd_sta_free(dhd_pub_t *pub, dhd_sta_t *sta);
++static dhd_sta_t * dhd_sta_alloc(dhd_pub_t * dhdp);
++
++/* Delete a dhd_sta or flush all dhd_sta in an interface's sta_list. */
++static void dhd_if_del_sta_list(dhd_if_t * ifp);
++static void	dhd_if_flush_sta(dhd_if_t * ifp);
++
++/* Construct/Destruct a sta pool. */
++static int dhd_sta_pool_init(dhd_pub_t *dhdp, int max_sta);
++static void dhd_sta_pool_fini(dhd_pub_t *dhdp, int max_sta);
++/* Clear the pool of dhd_sta_t objects for built-in type driver */
++static void dhd_sta_pool_clear(dhd_pub_t *dhdp, int max_sta);
++
++
++/* Return interface pointer */
++static inline dhd_if_t *dhd_get_ifp(dhd_pub_t *dhdp, uint32 ifidx)
++{
++	ASSERT(ifidx < DHD_MAX_IFS);
++
++	if (ifidx >= DHD_MAX_IFS)
++		return NULL;
++
++	return dhdp->info->iflist[ifidx];
++}
++
++/** Reset a dhd_sta object and free into the dhd pool. */
++static void
++dhd_sta_free(dhd_pub_t * dhdp, dhd_sta_t * sta)
++{
++	int prio;
++
++	ASSERT((sta != DHD_STA_NULL) && (sta->idx != ID16_INVALID));
++
++	ASSERT((dhdp->staid_allocator != NULL) && (dhdp->sta_pool != NULL));
++
++	/*
++	 * Flush and free all packets in all flowring's queues belonging to sta.
++	 * Packets in flow ring will be flushed later.
++	 */
++	for (prio = 0; prio < (int)NUMPRIO; prio++) {
++		uint16 flowid = sta->flowid[prio];
++
++		if (flowid != FLOWID_INVALID) {
++			unsigned long flags;
++			flow_queue_t * queue = dhd_flow_queue(dhdp, flowid);
++			flow_ring_node_t * flow_ring_node;
++
++#ifdef DHDTCPACK_SUPPRESS
++			/* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt,
++			 * when there is a newly coming packet from network stack.
++			 */
++			dhd_tcpack_info_tbl_clean(dhdp);
++#endif /* DHDTCPACK_SUPPRESS */
++
++			flow_ring_node = dhd_flow_ring_node(dhdp, flowid);
++			DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++			flow_ring_node->status = FLOW_RING_STATUS_STA_FREEING;
++
++			if (!DHD_FLOW_QUEUE_EMPTY(queue)) {
++				void * pkt;
++				while ((pkt = dhd_flow_queue_dequeue(dhdp, queue)) != NULL) {
++					PKTFREE(dhdp->osh, pkt, TRUE);
++				}
++			}
++
++			DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++			ASSERT(DHD_FLOW_QUEUE_EMPTY(queue));
++		}
++
++		sta->flowid[prio] = FLOWID_INVALID;
++	}
++
++	id16_map_free(dhdp->staid_allocator, sta->idx);
++	DHD_CUMM_CTR_INIT(&sta->cumm_ctr);
++	sta->ifp = DHD_IF_NULL; /* dummy dhd_if object */
++	sta->ifidx = DHD_BAD_IF;
++	bzero(sta->ea.octet, ETHER_ADDR_LEN);
++	INIT_LIST_HEAD(&sta->list);
++	sta->idx = ID16_INVALID; /* implying free */
++}
++
++/** Allocate a dhd_sta object from the dhd pool. */
++static dhd_sta_t *
++dhd_sta_alloc(dhd_pub_t * dhdp)
++{
++	uint16 idx;
++	dhd_sta_t * sta;
++	dhd_sta_pool_t * sta_pool;
++
++	ASSERT((dhdp->staid_allocator != NULL) && (dhdp->sta_pool != NULL));
++
++	idx = id16_map_alloc(dhdp->staid_allocator);
++	if (idx == ID16_INVALID) {
++		DHD_ERROR(("%s: cannot get free staid\n", __FUNCTION__));
++		return DHD_STA_NULL;
++	}
++
++	sta_pool = (dhd_sta_pool_t *)(dhdp->sta_pool);
++	sta = &sta_pool[idx];
++
++	ASSERT((sta->idx == ID16_INVALID) &&
++	       (sta->ifp == DHD_IF_NULL) && (sta->ifidx == DHD_BAD_IF));
++
++	DHD_CUMM_CTR_INIT(&sta->cumm_ctr);
++
++	sta->idx = idx; /* implying allocated */
++
++	return sta;
++}
++
++/** Delete all STAs in an interface's STA list. */
++static void
++dhd_if_del_sta_list(dhd_if_t *ifp)
++{
++	dhd_sta_t *sta, *next;
++	unsigned long flags;
++
++	DHD_IF_STA_LIST_LOCK(ifp, flags);
++
++	list_for_each_entry_safe(sta, next, &ifp->sta_list, list) {
++#if defined(BCM_GMAC3)
++		if (ifp->fwdh) {
++			/* Remove sta from WOFA forwarder. */
++			fwder_deassoc(ifp->fwdh, (uint16 *)(sta->ea.octet), (uintptr_t)sta);
++		}
++#endif /* BCM_GMAC3 */
++		list_del(&sta->list);
++		dhd_sta_free(&ifp->info->pub, sta);
++	}
++
++	DHD_IF_STA_LIST_UNLOCK(ifp, flags);
++
++	return;
++}
++
++/** Router/GMAC3: Flush all station entries in the forwarder's WOFA database. */
++static void
++dhd_if_flush_sta(dhd_if_t * ifp)
++{
++#if defined(BCM_GMAC3)
++
++	if (ifp && (ifp->fwdh != FWDER_NULL)) {
++		dhd_sta_t *sta, *next;
++		unsigned long flags;
++
++		DHD_IF_STA_LIST_LOCK(ifp, flags);
++
++		list_for_each_entry_safe(sta, next, &ifp->sta_list, list) {
++			/* Remove any sta entry from WOFA forwarder. */
++			fwder_flush(ifp->fwdh, (uintptr_t)sta);
++		}
++
++		DHD_IF_STA_LIST_UNLOCK(ifp, flags);
++	}
++#endif /* BCM_GMAC3 */
++}
++
++/** Construct a pool of dhd_sta_t objects to be used by interfaces. */
++static int
++dhd_sta_pool_init(dhd_pub_t *dhdp, int max_sta)
++{
++	int idx, prio, sta_pool_memsz;
++	dhd_sta_t * sta;
++	dhd_sta_pool_t * sta_pool;
++	void * staid_allocator;
++
++	ASSERT(dhdp != (dhd_pub_t *)NULL);
++	ASSERT((dhdp->staid_allocator == NULL) && (dhdp->sta_pool == NULL));
++
++	/* dhd_sta objects per radio are managed in a table. id#0 reserved. */
++	staid_allocator = id16_map_init(dhdp->osh, max_sta, 1);
++	if (staid_allocator == NULL) {
++		DHD_ERROR(("%s: sta id allocator init failure\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	/* Pre allocate a pool of dhd_sta objects (one extra). */
++	sta_pool_memsz = ((max_sta + 1) * sizeof(dhd_sta_t)); /* skip idx 0 */
++	sta_pool = (dhd_sta_pool_t *)MALLOC(dhdp->osh, sta_pool_memsz);
++	if (sta_pool == NULL) {
++		DHD_ERROR(("%s: sta table alloc failure\n", __FUNCTION__));
++		id16_map_fini(dhdp->osh, staid_allocator);
++		return BCME_ERROR;
++	}
++
++	dhdp->sta_pool = sta_pool;
++	dhdp->staid_allocator = staid_allocator;
++
++	/* Initialize all sta(s) for the pre-allocated free pool. */
++	bzero((uchar *)sta_pool, sta_pool_memsz);
++	for (idx = max_sta; idx >= 1; idx--) { /* skip sta_pool[0] */
++		sta = &sta_pool[idx];
++		sta->idx = id16_map_alloc(staid_allocator);
++		ASSERT(sta->idx <= max_sta);
++	}
++	/* Now place them into the pre-allocated free pool. */
++	for (idx = 1; idx <= max_sta; idx++) {
++		sta = &sta_pool[idx];
++		for (prio = 0; prio < (int)NUMPRIO; prio++) {
++			sta->flowid[prio] = FLOWID_INVALID; /* Flow rings do not exist */
++		}
++		dhd_sta_free(dhdp, sta);
++	}
++
++	return BCME_OK;
++}
++
++/** Destruct the pool of dhd_sta_t objects.
++ * Caller must ensure that no STA objects are currently associated with an if.
++ */
++static void
++dhd_sta_pool_fini(dhd_pub_t *dhdp, int max_sta)
++{
++	dhd_sta_pool_t * sta_pool = (dhd_sta_pool_t *)dhdp->sta_pool;
++
++	if (sta_pool) {
++		int idx;
++		int sta_pool_memsz = ((max_sta + 1) * sizeof(dhd_sta_t));
++		for (idx = 1; idx <= max_sta; idx++) {
++			ASSERT(sta_pool[idx].ifp == DHD_IF_NULL);
++			ASSERT(sta_pool[idx].idx == ID16_INVALID);
++		}
++		MFREE(dhdp->osh, dhdp->sta_pool, sta_pool_memsz);
++		dhdp->sta_pool = NULL;
++	}
++
++	id16_map_fini(dhdp->osh, dhdp->staid_allocator);
++	dhdp->staid_allocator = NULL;
++}
++
++/* Clear the pool of dhd_sta_t objects for built-in type driver */
++static void
++dhd_sta_pool_clear(dhd_pub_t *dhdp, int max_sta)
++{
++	int idx, prio, sta_pool_memsz;
++	dhd_sta_t * sta;
++	dhd_sta_pool_t * sta_pool;
++	void *staid_allocator;
++
++	if (!dhdp) {
++		DHD_ERROR(("%s: dhdp is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	sta_pool = (dhd_sta_pool_t *)dhdp->sta_pool;
++	staid_allocator = dhdp->staid_allocator;
++
++	if (!sta_pool) {
++		DHD_ERROR(("%s: sta_pool is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (!staid_allocator) {
++		DHD_ERROR(("%s: staid_allocator is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	/* clear free pool */
++	sta_pool_memsz = ((max_sta + 1) * sizeof(dhd_sta_t));
++	bzero((uchar *)sta_pool, sta_pool_memsz);
++
++	/* dhd_sta objects per radio are managed in a table. id#0 reserved. */
++	id16_map_clear(staid_allocator, max_sta, 1);
++
++	/* Initialize all sta(s) for the pre-allocated free pool. */
++	for (idx = max_sta; idx >= 1; idx--) { /* skip sta_pool[0] */
++		sta = &sta_pool[idx];
++		sta->idx = id16_map_alloc(staid_allocator);
++		ASSERT(sta->idx <= max_sta);
++	}
++	/* Now place them into the pre-allocated free pool. */
++	for (idx = 1; idx <= max_sta; idx++) {
++		sta = &sta_pool[idx];
++		for (prio = 0; prio < (int)NUMPRIO; prio++) {
++			sta->flowid[prio] = FLOWID_INVALID; /* Flow rings do not exist */
++		}
++		dhd_sta_free(dhdp, sta);
++	}
++}
++
++/** Find STA with MAC address ea in an interface's STA list. */
++dhd_sta_t *
++dhd_find_sta(void *pub, int ifidx, void *ea)
++{
++	dhd_sta_t *sta;
++	dhd_if_t *ifp;
++	unsigned long flags;
++
++	ASSERT(ea != NULL);
++	ifp = dhd_get_ifp((dhd_pub_t *)pub, ifidx);
++	if (ifp == NULL)
++		return DHD_STA_NULL;
++
++	DHD_IF_STA_LIST_LOCK(ifp, flags);
++
++	list_for_each_entry(sta, &ifp->sta_list, list) {
++		if (!memcmp(sta->ea.octet, ea, ETHER_ADDR_LEN)) {
++			DHD_IF_STA_LIST_UNLOCK(ifp, flags);
++			return sta;
++		}
++	}
++
++	DHD_IF_STA_LIST_UNLOCK(ifp, flags);
++
++	return DHD_STA_NULL;
++}
++
++/** Add STA into the interface's STA list. */
++dhd_sta_t *
++dhd_add_sta(void *pub, int ifidx, void *ea)
++{
++	dhd_sta_t *sta;
++	dhd_if_t *ifp;
++	unsigned long flags;
++
++	ASSERT(ea != NULL);
++	ifp = dhd_get_ifp((dhd_pub_t *)pub, ifidx);
++	if (ifp == NULL)
++		return DHD_STA_NULL;
++
++	sta = dhd_sta_alloc((dhd_pub_t *)pub);
++	if (sta == DHD_STA_NULL) {
++		DHD_ERROR(("%s: Alloc failed\n", __FUNCTION__));
++		return DHD_STA_NULL;
++	}
++
++	memcpy(sta->ea.octet, ea, ETHER_ADDR_LEN);
++
++	/* link the sta and the dhd interface */
++	sta->ifp = ifp;
++	sta->ifidx = ifidx;
++#ifdef DHD_WMF
++	sta->psta_prim = NULL;
++#endif
++	INIT_LIST_HEAD(&sta->list);
++
++	DHD_IF_STA_LIST_LOCK(ifp, flags);
++
++	list_add_tail(&sta->list, &ifp->sta_list);
++
++#if defined(BCM_GMAC3)
++	if (ifp->fwdh) {
++		ASSERT(ISALIGNED(ea, 2));
++		/* Add sta to WOFA forwarder. */
++		fwder_reassoc(ifp->fwdh, (uint16 *)ea, (uintptr_t)sta);
++	}
++#endif /* BCM_GMAC3 */
++
++	DHD_IF_STA_LIST_UNLOCK(ifp, flags);
++
++	return sta;
++}
++
++/** Delete STA from the interface's STA list. */
++void
++dhd_del_sta(void *pub, int ifidx, void *ea)
++{
++	dhd_sta_t *sta, *next;
++	dhd_if_t *ifp;
++	unsigned long flags;
++
++	ASSERT(ea != NULL);
++	ifp = dhd_get_ifp((dhd_pub_t *)pub, ifidx);
++	if (ifp == NULL)
++		return;
++
++	DHD_IF_STA_LIST_LOCK(ifp, flags);
++
++	list_for_each_entry_safe(sta, next, &ifp->sta_list, list) {
++		if (!memcmp(sta->ea.octet, ea, ETHER_ADDR_LEN)) {
++#if defined(BCM_GMAC3)
++			if (ifp->fwdh) { /* Found a sta, remove from WOFA forwarder. */
++				ASSERT(ISALIGNED(ea, 2));
++				fwder_deassoc(ifp->fwdh, (uint16 *)ea, (uintptr_t)sta);
++			}
++#endif /* BCM_GMAC3 */
++			list_del(&sta->list);
++			dhd_sta_free(&ifp->info->pub, sta);
++		}
++	}
++
++	DHD_IF_STA_LIST_UNLOCK(ifp, flags);
++#ifdef DHD_L2_FILTER
++	if (ifp->parp_enable) {
++		/* clear Proxy ARP cache of specific Ethernet Address */
++		bcm_l2_filter_arp_table_update(((dhd_pub_t*)pub)->osh, ifp->phnd_arp_table, FALSE,
++			ea, FALSE, ((dhd_pub_t*)pub)->tickcnt);
++	}
++#endif /* DHD_L2_FILTER */
++	return;
++}
++
++/** Add STA if it doesn't exist. Not reentrant. */
++dhd_sta_t*
++dhd_findadd_sta(void *pub, int ifidx, void *ea)
++{
++	dhd_sta_t *sta;
++
++	sta = dhd_find_sta(pub, ifidx, ea);
++
++	if (!sta) {
++		/* Add entry */
++		sta = dhd_add_sta(pub, ifidx, ea);
++	}
++
++	return sta;
++}
++
++#if defined(DHD_IGMP_UCQUERY) || defined(DHD_UCAST_UPNP)
++#if !defined(BCM_GMAC3)
++static struct list_head *
++dhd_sta_list_snapshot(dhd_info_t *dhd, dhd_if_t *ifp, struct list_head *snapshot_list)
++{
++	unsigned long flags;
++	dhd_sta_t *sta, *snapshot;
++
++	INIT_LIST_HEAD(snapshot_list);
++
++	DHD_IF_STA_LIST_LOCK(ifp, flags);
++
++	list_for_each_entry(sta, &ifp->sta_list, list) {
++		/* allocate one and add to snapshot */
++		snapshot = (dhd_sta_t *)MALLOC(dhd->pub.osh, sizeof(dhd_sta_t));
++		if (snapshot == NULL) {
++			DHD_ERROR(("%s: Cannot allocate memory\n", __FUNCTION__));
++			continue;
++		}
++
++		memcpy(snapshot->ea.octet, sta->ea.octet, ETHER_ADDR_LEN);
++
++		INIT_LIST_HEAD(&snapshot->list);
++		list_add_tail(&snapshot->list, snapshot_list);
++	}
++
++	DHD_IF_STA_LIST_UNLOCK(ifp, flags);
++
++	return snapshot_list;
++}
++
++static void
++dhd_sta_list_snapshot_free(dhd_info_t *dhd, struct list_head *snapshot_list)
++{
++	dhd_sta_t *sta, *next;
++
++	list_for_each_entry_safe(sta, next, snapshot_list, list) {
++		list_del(&sta->list);
++		MFREE(dhd->pub.osh, sta, sizeof(dhd_sta_t));
++	}
++}
++#endif /* !BCM_GMAC3 */
++#endif /* DHD_IGMP_UCQUERY || DHD_UCAST_UPNP */
++
++#else
++static inline void dhd_if_flush_sta(dhd_if_t * ifp) { }
++static inline void dhd_if_del_sta_list(dhd_if_t *ifp) {}
++static inline int dhd_sta_pool_init(dhd_pub_t *dhdp, int max_sta) { return BCME_OK; }
++static inline void dhd_sta_pool_fini(dhd_pub_t *dhdp, int max_sta) {}
++static inline void dhd_sta_pool_clear(dhd_pub_t *dhdp, int max_sta) {}
++dhd_sta_t *dhd_findadd_sta(void *pub, int ifidx, void *ea) { return NULL; }
++void dhd_del_sta(void *pub, int ifidx, void *ea) {}
++#endif /* PCIE_FULL_DONGLE */
++
++
++#if defined(DHD_LB)
++
++#if defined(DHD_LB_TXC) || defined(DHD_LB_RXC)
++/**
++ * dhd_tasklet_schedule - Function that runs in IPI context of the destination
++ * CPU and schedules a tasklet.
++ * @tasklet: opaque pointer to the tasklet
++ */
++static INLINE void
++dhd_tasklet_schedule(void *tasklet)
++{
++	tasklet_schedule((struct tasklet_struct *)tasklet);
++}
++
++/**
++ * dhd_tasklet_schedule_on - Executes the passed takslet in a given CPU
++ * @tasklet: tasklet to be scheduled
++ * @on_cpu: cpu core id
++ *
++ * If the requested cpu is online, then an IPI is sent to this cpu via the
++ * smp_call_function_single with no wait and the tasklet_schedule function
++ * will be invoked to schedule the specified tasklet on the requested CPU.
++ */
++static void
++dhd_tasklet_schedule_on(struct tasklet_struct *tasklet, int on_cpu)
++{
++	const int wait = 0;
++	smp_call_function_single(on_cpu,
++		dhd_tasklet_schedule, (void *)tasklet, wait);
++}
++#endif /* DHD_LB_TXC || DHD_LB_RXC */
++
++
++#if defined(DHD_LB_TXC)
++/**
++ * dhd_lb_tx_compl_dispatch - load balance by dispatching the tx_compl_tasklet
++ * on another cpu. The tx_compl_tasklet will take care of DMA unmapping and
++ * freeing the packets placed in the tx_compl workq
++ */
++void
++dhd_lb_tx_compl_dispatch(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++	int curr_cpu, on_cpu;
++
++	if (dhd->rx_napi_netdev == NULL) {
++		DHD_ERROR(("%s: dhd->rx_napi_netdev is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	DHD_LB_STATS_INCR(dhd->txc_sched_cnt);
++	/*
++	 * If the destination CPU is NOT online or is same as current CPU
++	 * no need to schedule the work
++	 */
++	curr_cpu = get_cpu();
++	put_cpu();
++
++	on_cpu = atomic_read(&dhd->tx_compl_cpu);
++
++	if ((on_cpu == curr_cpu) || (!cpu_online(on_cpu))) {
++		dhd_tasklet_schedule(&dhd->tx_compl_tasklet);
++	} else {
++		schedule_work(&dhd->tx_compl_dispatcher_work);
++	}
++}
++
++static void dhd_tx_compl_dispatcher_fn(struct work_struct * work)
++{
++	struct dhd_info *dhd =
++		container_of(work, struct dhd_info, tx_compl_dispatcher_work);
++	int cpu;
++
++	get_online_cpus();
++	cpu = atomic_read(&dhd->tx_compl_cpu);
++	if (!cpu_online(cpu))
++		dhd_tasklet_schedule(&dhd->tx_compl_tasklet);
++	else
++		dhd_tasklet_schedule_on(&dhd->tx_compl_tasklet, cpu);
++	put_online_cpus();
++}
++
++#endif /* DHD_LB_TXC */
++
++
++#if defined(DHD_LB_RXC)
++/**
++ * dhd_lb_rx_compl_dispatch - load balance by dispatching the rx_compl_tasklet
++ * on another cpu. The rx_compl_tasklet will take care of reposting rx buffers
++ * in the H2D RxBuffer Post common ring, by using the recycled pktids that were
++ * placed in the rx_compl workq.
++ *
++ * @dhdp: pointer to dhd_pub object
++ */
++void
++dhd_lb_rx_compl_dispatch(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++	int curr_cpu, on_cpu;
++
++	if (dhd->rx_napi_netdev == NULL) {
++		DHD_ERROR(("%s: dhd->rx_napi_netdev is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	DHD_LB_STATS_INCR(dhd->rxc_sched_cnt);
++	/*
++	 * If the destination CPU is NOT online or is same as current CPU
++	 * no need to schedule the work
++	 */
++	curr_cpu = get_cpu();
++	put_cpu();
++
++	on_cpu = atomic_read(&dhd->rx_compl_cpu);
++
++	if ((on_cpu == curr_cpu) || (!cpu_online(on_cpu))) {
++		dhd_tasklet_schedule(&dhd->rx_compl_tasklet);
++	} else {
++		schedule_work(&dhd->rx_compl_dispatcher_work);
++	}
++}
++
++static void dhd_rx_compl_dispatcher_fn(struct work_struct * work)
++{
++	struct dhd_info *dhd =
++		container_of(work, struct dhd_info, rx_compl_dispatcher_work);
++	int cpu;
++
++	get_online_cpus();
++	cpu = atomic_read(&dhd->tx_compl_cpu);
++	if (!cpu_online(cpu))
++		dhd_tasklet_schedule(&dhd->rx_compl_tasklet);
++	else
++		dhd_tasklet_schedule_on(&dhd->rx_compl_tasklet, cpu);
++	put_online_cpus();
++}
++
++#endif /* DHD_LB_RXC */
++
++
++#if defined(DHD_LB_RXP)
++/**
++ * dhd_napi_poll - Load balance napi poll function to process received
++ * packets and send up the network stack using netif_receive_skb()
++ *
++ * @napi: napi object in which context this poll function is invoked
++ * @budget: number of packets to be processed.
++ *
++ * Fetch the dhd_info given the rx_napi_struct. Move all packets from the
++ * rx_napi_queue into a local rx_process_queue (lock and queue move and unlock).
++ * Dequeue each packet from head of rx_process_queue, fetch the ifid from the
++ * packet tag and sendup.
++ */
++static int
++dhd_napi_poll(struct napi_struct *napi, int budget)
++{
++	int ifid;
++	const int pkt_count = 1;
++	const int chan = 0;
++	struct sk_buff * skb;
++	unsigned long flags;
++	struct dhd_info *dhd;
++	int processed = 0;
++	struct sk_buff_head rx_process_queue;
++
++	dhd = container_of(napi, struct dhd_info, rx_napi_struct);
++	DHD_INFO(("%s napi_queue<%d> budget<%d>\n",
++		__FUNCTION__, skb_queue_len(&dhd->rx_napi_queue), budget));
++
++	__skb_queue_head_init(&rx_process_queue);
++
++	/* extract the entire rx_napi_queue into local rx_process_queue */
++	spin_lock_irqsave(&dhd->rx_napi_queue.lock, flags);
++	skb_queue_splice_tail_init(&dhd->rx_napi_queue, &rx_process_queue);
++	spin_unlock_irqrestore(&dhd->rx_napi_queue.lock, flags);
++
++	while ((skb = __skb_dequeue(&rx_process_queue)) != NULL) {
++		OSL_PREFETCH(skb->data);
++
++		ifid = DHD_PKTTAG_IFID((dhd_pkttag_fr_t *)PKTTAG(skb));
++
++		DHD_INFO(("%s dhd_rx_frame pkt<%p> ifid<%d>\n",
++			__FUNCTION__, skb, ifid));
++
++		dhd_rx_frame(&dhd->pub, ifid, skb, pkt_count, chan);
++		processed++;
++	}
++
++	DHD_LB_STATS_UPDATE_NAPI_HISTO(&dhd->pub, processed);
++
++	DHD_INFO(("%s processed %d\n", __FUNCTION__, processed));
++	napi_complete(napi);
++
++	return budget - 1;
++}
++
++/**
++ * dhd_napi_schedule - Place the napi struct into the current cpus softnet napi
++ * poll list. This function may be invoked via the smp_call_function_single
++ * from a remote CPU.
++ *
++ * This function will essentially invoke __raise_softirq_irqoff(NET_RX_SOFTIRQ)
++ * after the napi_struct is added to the softnet data's poll_list
++ *
++ * @info: pointer to a dhd_info struct
++ */
++static void
++dhd_napi_schedule(void *info)
++{
++	dhd_info_t *dhd = (dhd_info_t *)info;
++
++	DHD_INFO(("%s rx_napi_struct<%p> on cpu<%d>\n",
++		__FUNCTION__, &dhd->rx_napi_struct, atomic_read(&dhd->rx_napi_cpu)));
++
++	/* add napi_struct to softnet data poll list and raise NET_RX_SOFTIRQ */
++	if (napi_schedule_prep(&dhd->rx_napi_struct)) {
++		__napi_schedule(&dhd->rx_napi_struct);
++		DHD_LB_STATS_PERCPU_ARR_INCR(dhd->napi_percpu_run_cnt);
++	}
++
++	/*
++	 * If the rx_napi_struct was already running, then we let it complete
++	 * processing all its packets. The rx_napi_struct may only run on one
++	 * core at a time, to avoid out-of-order handling.
++	 */
++}
++
++/**
++ * dhd_napi_schedule_on - API to schedule on a desired CPU core a NET_RX_SOFTIRQ
++ * action after placing the dhd's rx_process napi object in the the remote CPU's
++ * softnet data's poll_list.
++ *
++ * @dhd: dhd_info which has the rx_process napi object
++ * @on_cpu: desired remote CPU id
++ */
++static INLINE int
++dhd_napi_schedule_on(dhd_info_t *dhd, int on_cpu)
++{
++	int wait = 0; /* asynchronous IPI */
++
++	DHD_INFO(("%s dhd<%p> napi<%p> on_cpu<%d>\n",
++		__FUNCTION__, dhd, &dhd->rx_napi_struct, on_cpu));
++
++	if (smp_call_function_single(on_cpu, dhd_napi_schedule, dhd, wait)) {
++		DHD_ERROR(("%s smp_call_function_single on_cpu<%d> failed\n",
++			__FUNCTION__, on_cpu));
++	}
++
++	DHD_LB_STATS_INCR(dhd->napi_sched_cnt);
++
++	return 0;
++}
++
++/*
++ * Call get_online_cpus/put_online_cpus around dhd_napi_schedule_on
++ * Why should we do this?
++ * The candidacy algorithm is run from the call back function
++ * registered to CPU hotplug notifier. This call back happens from Worker
++ * context. The dhd_napi_schedule_on is also from worker context.
++ * Note that both of this can run on two different CPUs at the same time.
++ * So we can possibly have a window where a given CPUn is being brought
++ * down from CPUm while we try to run a function on CPUn.
++ * To prevent this its better have the whole code to execute an SMP
++ * function under get_online_cpus.
++ * This function call ensures that hotplug mechanism does not kick-in
++ * until we are done dealing with online CPUs
++ * If the hotplug worker is already running, no worries because the
++ * candidacy algo would then reflect the same in dhd->rx_napi_cpu.
++ *
++ * The below mentioned code structure is proposed in
++ * https://www.kernel.org/doc/Documentation/cpu-hotplug.txt
++ * for the question
++ * Q: I need to ensure that a particular cpu is not removed when there is some
++ *    work specific to this cpu is in progress
++ *
++ * According to the documentation calling get_online_cpus is NOT required, if
++ * we are running from tasklet context. Since dhd_rx_napi_dispatcher_fn can
++ * run from Work Queue context we have to call these functions
++ */
++static void dhd_rx_napi_dispatcher_fn(struct work_struct * work)
++{
++	struct dhd_info *dhd =
++		container_of(work, struct dhd_info, rx_napi_dispatcher_work);
++	int cpu;
++
++	get_online_cpus();
++	cpu = atomic_read(&dhd->rx_napi_cpu);
++	if (!cpu_online(cpu))
++		dhd_napi_schedule(dhd);
++	else
++		dhd_napi_schedule_on(dhd, cpu);
++	put_online_cpus();
++}
++
++/**
++ * dhd_lb_rx_napi_dispatch - load balance by dispatching the rx_napi_struct
++ * to run on another CPU. The rx_napi_struct's poll function will retrieve all
++ * the packets enqueued into the rx_napi_queue and sendup.
++ * The producer's rx packet queue is appended to the rx_napi_queue before
++ * dispatching the rx_napi_struct.
++ */
++void
++dhd_lb_rx_napi_dispatch(dhd_pub_t *dhdp)
++{
++	unsigned long flags;
++	dhd_info_t *dhd = dhdp->info;
++	int curr_cpu;
++	int on_cpu;
++
++	if (dhd->rx_napi_netdev == NULL) {
++		DHD_ERROR(("%s: dhd->rx_napi_netdev is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	DHD_INFO(("%s append napi_queue<%d> pend_queue<%d>\n", __FUNCTION__,
++		skb_queue_len(&dhd->rx_napi_queue), skb_queue_len(&dhd->rx_pend_queue)));
++
++	/* append the producer's queue of packets to the napi's rx process queue */
++	spin_lock_irqsave(&dhd->rx_napi_queue.lock, flags);
++	skb_queue_splice_tail_init(&dhd->rx_pend_queue, &dhd->rx_napi_queue);
++	spin_unlock_irqrestore(&dhd->rx_napi_queue.lock, flags);
++
++	/*
++	 * If the destination CPU is NOT online or is same as current CPU
++	 * no need to schedule the work
++	 */
++	curr_cpu = get_cpu();
++	put_cpu();
++
++	on_cpu = atomic_read(&dhd->rx_napi_cpu);
++
++	if ((on_cpu == curr_cpu) || (!cpu_online(on_cpu))) {
++		dhd_napi_schedule(dhd);
++	} else {
++		schedule_work(&dhd->rx_napi_dispatcher_work);
++	}
++}
++
++/**
++ * dhd_lb_rx_pkt_enqueue - Enqueue the packet into the producer's queue
++ */
++void
++dhd_lb_rx_pkt_enqueue(dhd_pub_t *dhdp, void *pkt, int ifidx)
++{
++	dhd_info_t *dhd = dhdp->info;
++
++	DHD_INFO(("%s enqueue pkt<%p> ifidx<%d> pend_queue<%d>\n", __FUNCTION__,
++		pkt, ifidx, skb_queue_len(&dhd->rx_pend_queue)));
++	DHD_PKTTAG_SET_IFID((dhd_pkttag_fr_t *)PKTTAG(pkt), ifidx);
++	__skb_queue_tail(&dhd->rx_pend_queue, pkt);
++}
++#endif /* DHD_LB_RXP */
++
++#endif /* DHD_LB */
++
++
++/** Returns dhd iflist index corresponding the the bssidx provided by apps */
++int dhd_bssidx2idx(dhd_pub_t *dhdp, uint32 bssidx)
++{
++	dhd_if_t *ifp;
++	dhd_info_t *dhd = dhdp->info;
++	int i;
++
++	ASSERT(bssidx < DHD_MAX_IFS);
++	ASSERT(dhdp);
++
++	for (i = 0; i < DHD_MAX_IFS; i++) {
++		ifp = dhd->iflist[i];
++		if (ifp && (ifp->bssidx == bssidx)) {
++			DHD_TRACE(("Index manipulated for %s from %d to %d\n",
++				ifp->name, bssidx, i));
++			break;
++		}
++	}
++	return i;
++}
++
++static inline int dhd_rxf_enqueue(dhd_pub_t *dhdp, void* skb)
++{
++	uint32 store_idx;
++	uint32 sent_idx;
++
++	if (!skb) {
++		DHD_ERROR(("dhd_rxf_enqueue: NULL skb!!!\n"));
++		return BCME_ERROR;
++	}
++
++	dhd_os_rxflock(dhdp);
++	store_idx = dhdp->store_idx;
++	sent_idx = dhdp->sent_idx;
++	if (dhdp->skbbuf[store_idx] != NULL) {
++		/* Make sure the previous packets are processed */
++		dhd_os_rxfunlock(dhdp);
++#ifdef RXF_DEQUEUE_ON_BUSY
++		DHD_TRACE(("dhd_rxf_enqueue: pktbuf not consumed %p, store idx %d sent idx %d\n",
++			skb, store_idx, sent_idx));
++		return BCME_BUSY;
++#else /* RXF_DEQUEUE_ON_BUSY */
++		DHD_ERROR(("dhd_rxf_enqueue: pktbuf not consumed %p, store idx %d sent idx %d\n",
++			skb, store_idx, sent_idx));
++		/* removed msleep here, should use wait_event_timeout if we
++		 * want to give rx frame thread a chance to run
++		 */
++#if defined(WAIT_DEQUEUE)
++		OSL_SLEEP(1);
++#endif
++		return BCME_ERROR;
++#endif /* RXF_DEQUEUE_ON_BUSY */
++	}
++	DHD_TRACE(("dhd_rxf_enqueue: Store SKB %p. idx %d -> %d\n",
++		skb, store_idx, (store_idx + 1) & (MAXSKBPEND - 1)));
++	dhdp->skbbuf[store_idx] = skb;
++	dhdp->store_idx = (store_idx + 1) & (MAXSKBPEND - 1);
++	dhd_os_rxfunlock(dhdp);
++
++	return BCME_OK;
++}
++
++static inline void* dhd_rxf_dequeue(dhd_pub_t *dhdp)
++{
++	uint32 store_idx;
++	uint32 sent_idx;
++	void *skb;
++
++	dhd_os_rxflock(dhdp);
++
++	store_idx = dhdp->store_idx;
++	sent_idx = dhdp->sent_idx;
++	skb = dhdp->skbbuf[sent_idx];
++
++	if (skb == NULL) {
++		dhd_os_rxfunlock(dhdp);
++		DHD_ERROR(("dhd_rxf_dequeue: Dequeued packet is NULL, store idx %d sent idx %d\n",
++			store_idx, sent_idx));
++		return NULL;
++	}
++
++	dhdp->skbbuf[sent_idx] = NULL;
++	dhdp->sent_idx = (sent_idx + 1) & (MAXSKBPEND - 1);
++
++	DHD_TRACE(("dhd_rxf_dequeue: netif_rx_ni(%p), sent idx %d\n",
++		skb, sent_idx));
++
++	dhd_os_rxfunlock(dhdp);
++
++	return skb;
++}
++
++int dhd_process_cid_mac(dhd_pub_t *dhdp, bool prepost)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++
++	if (prepost) { /* pre process */
++		dhd_read_macaddr(dhd);
++	} else { /* post process */
++		dhd_write_macaddr(&dhd->pub.mac);
++	}
++
++	return 0;
++}
++
++#if defined(PKT_FILTER_SUPPORT) && !defined(GAN_LITE_NAT_KEEPALIVE_FILTER)
++static bool
++_turn_on_arp_filter(dhd_pub_t *dhd, int op_mode)
++{
++	bool _apply = FALSE;
++	/* In case of IBSS mode, apply arp pkt filter */
++	if (op_mode & DHD_FLAG_IBSS_MODE) {
++		_apply = TRUE;
++		goto exit;
++	}
++#ifndef STBLINUX
++	/* In case of P2P GO or GC, apply pkt filter to pass arp pkt to host */
++	if ((dhd->arp_version == 1) &&
++		(op_mode & (DHD_FLAG_P2P_GC_MODE | DHD_FLAG_P2P_GO_MODE))) {
++		_apply = TRUE;
++		goto exit;
++	}
++#endif /* STBLINUX */
++exit:
++	return _apply;
++}
++#endif /* PKT_FILTER_SUPPORT && !GAN_LITE_NAT_KEEPALIVE_FILTER */
++
++void dhd_set_packet_filter(dhd_pub_t *dhd)
++{
++#ifdef PKT_FILTER_SUPPORT
++	int i;
++
++	DHD_TRACE(("%s: enter\n", __FUNCTION__));
++	if (dhd_pkt_filter_enable) {
++		for (i = 0; i < dhd->pktfilter_count; i++) {
++			dhd_pktfilter_offload_set(dhd, dhd->pktfilter[i]);
++		}
++	}
++#endif /* PKT_FILTER_SUPPORT */
++}
++
++void dhd_enable_packet_filter(int value, dhd_pub_t *dhd)
++{
++#ifdef PKT_FILTER_SUPPORT
++	int i;
++
++	DHD_TRACE(("%s: enter, value = %d\n", __FUNCTION__, value));
++	/* 1 - Enable packet filter, only allow unicast packet to send up */
++	/* 0 - Disable packet filter */
++	if (dhd_pkt_filter_enable && (!value ||
++	    (dhd_support_sta_mode(dhd) && !dhd->dhcp_in_progress)))
++	    {
++		for (i = 0; i < dhd->pktfilter_count; i++) {
++#ifndef GAN_LITE_NAT_KEEPALIVE_FILTER
++			if (value && (i == DHD_ARP_FILTER_NUM) &&
++				!_turn_on_arp_filter(dhd, dhd->op_mode)) {
++				DHD_TRACE(("Do not turn on ARP white list pkt filter:"
++					"val %d, cnt %d, op_mode 0x%x\n",
++					value, i, dhd->op_mode));
++				continue;
++			}
++#endif /* !GAN_LITE_NAT_KEEPALIVE_FILTER */
++			dhd_pktfilter_offload_enable(dhd, dhd->pktfilter[i],
++				value, dhd_master_mode);
++		}
++	}
++#endif /* PKT_FILTER_SUPPORT */
++}
++
++static int dhd_set_suspend(int value, dhd_pub_t *dhd)
++{
++#ifndef SUPPORT_PM2_ONLY
++	int power_mode = PM_MAX;
++#endif /* SUPPORT_PM2_ONLY */
++	/* wl_pkt_filter_enable_t	enable_parm; */
++	int bcn_li_dtim = 0; /* Default bcn_li_dtim in resume mode is 0 */
++#ifdef CUSTOM_BCN_TIMEOUT_IN_SUSPEND
++	int bcn_timeout = 0;
++#endif /* CUSTOM_BCN_TIMEOUT_IN_SUSPEND */
++#ifdef CUSTOM_ROAM_TIME_THRESH_IN_SUSPEND
++	int roam_time_thresh = 0;	/* (ms) */
++#endif /* CUSTOM_ROAM_TIME_THRESH_IN_SUSPEND */
++#ifndef ENABLE_FW_ROAM_SUSPEND
++	uint roamvar = 1;
++#endif /* ENABLE_FW_ROAM_SUSPEND */
++	uint nd_ra_filter = 0;
++	int ret = 0;
++
++#ifdef DYNAMIC_SWOOB_DURATION
++#ifndef CUSTOM_INTR_WIDTH
++#define CUSTOM_INTR_WIDTH 100
++	int intr_width = 0;
++#endif /* CUSTOM_INTR_WIDTH */
++#endif /* DYNAMIC_SWOOB_DURATION */
++	if (!dhd)
++		return -ENODEV;
++
++
++	DHD_TRACE(("%s: enter, value = %d in_suspend=%d\n",
++		__FUNCTION__, value, dhd->in_suspend));
++
++	dhd_suspend_lock(dhd);
++
++#ifdef CUSTOM_SET_CPUCORE
++	DHD_TRACE(("%s set cpucore(suspend%d)\n", __FUNCTION__, value));
++	/* set specific cpucore */
++	dhd_set_cpucore(dhd, TRUE);
++#endif /* CUSTOM_SET_CPUCORE */
++	if (dhd->up) {
++		if (value && dhd->in_suspend) {
++#ifdef PKT_FILTER_SUPPORT
++				dhd->early_suspended = 1;
++#endif
++				/* Kernel suspended */
++				DHD_ERROR(("%s: force extra Suspend setting \n", __FUNCTION__));
++
++#ifndef SUPPORT_PM2_ONLY
++				dhd_wl_ioctl_cmd(dhd, WLC_SET_PM, (char *)&power_mode,
++				                 sizeof(power_mode), TRUE, 0);
++#endif /* SUPPORT_PM2_ONLY */
++
++#ifdef WL_VIRTUAL_APSTA
++				/* Softap shouldn't enable packet filter in STA+SoftAP mode */
++				if (!(dhd->op_mode & DHD_FLAG_HOSTAP_MODE))
++#endif /* WL_VIRTUAL_APSTA */
++				{
++					/* Enable packet filter,
++					 * only allow unicast packet to send up
++					 */
++					dhd_enable_packet_filter(1, dhd);
++				}
++
++				/* If DTIM skip is set up as default, force it to wake
++				 * each third DTIM for better power savings.  Note that
++				 * one side effect is a chance to miss BC/MC packet.
++				 */
++#ifdef WLTDLS
++				/* Do not set bcn_li_ditm on WFD mode */
++				if (dhd->tdls_mode) {
++					bcn_li_dtim = 0;
++				} else
++#endif /* WLTDLS */
++				bcn_li_dtim = dhd_get_suspend_bcn_li_dtim(dhd);
++				if (dhd_iovar(dhd, 0, "bcn_li_dtim", (char *)&bcn_li_dtim,
++						sizeof(bcn_li_dtim), NULL, 0, TRUE) < 0)
++				DHD_ERROR(("%s: set dtim failed\n", __FUNCTION__));
++#ifdef CUSTOM_BCN_TIMEOUT_IN_SUSPEND
++				bcn_timeout = CUSTOM_BCN_TIMEOUT_IN_SUSPEND;
++				dhd_iovar(dhd, 0, "bcn_timeout", (char *)&bcn_timeout,
++						sizeof(bcn_timeout), NULL, 0, TRUE);
++#endif /* CUSTOM_BCN_TIMEOUT_IN_SUSPEND */
++#ifdef CUSTOM_ROAM_TIME_THRESH_IN_SUSPEND
++				roam_time_thresh = CUSTOM_ROAM_TIME_THRESH_IN_SUSPEND;
++				dhd_iovar(dhd, 0, "roam_time_thresh", (char *)&roam_time_thresh,
++						sizeof(roam_time_thresh), NULL, 0, TRUE);
++#endif /* CUSTOM_ROAM_TIME_THRESH_IN_SUSPEND */
++#ifndef ENABLE_FW_ROAM_SUSPEND
++				/* Disable firmware roaming during suspend */
++				dhd_iovar(dhd, 0, "roam_off", (char *)&roamvar, sizeof(roamvar),
++						NULL, 0, TRUE);
++#endif /* ENABLE_FW_ROAM_SUSPEND */
++				if (FW_SUPPORTED(dhd, ndoe)) {
++					/* enable IPv6 RA filter in  firmware during suspend */
++					nd_ra_filter = 1;
++					ret = dhd_iovar(dhd, 0, "nd_ra_filter_enable",
++							(char *)&nd_ra_filter, sizeof(nd_ra_filter),
++							NULL, 0, TRUE);
++					if (ret < 0)
++						DHD_ERROR(("failed to set nd_ra_filter (%d)\n",
++							ret));
++				}
++				dhd_os_suppress_logging(dhd, TRUE);
++#ifdef DYNAMIC_SWOOB_DURATION
++				intr_width = CUSTOM_INTR_WIDTH;
++				ret = dhd_iovar(dhd, 0, "bus:intr_width", (char *)&intr_width,
++						sizeof(intr_width), NULL, 0, TRUE);
++				if (ret < 0) {
++					DHD_ERROR(("failed to set intr_width (%d)\n", ret));
++				}
++#endif /* DYNAMIC_SWOOB_DURATION */
++			} else {
++#ifdef PKT_FILTER_SUPPORT
++				dhd->early_suspended = 0;
++#endif
++				/* Kernel resumed  */
++				DHD_ERROR(("%s: Remove extra suspend setting \n", __FUNCTION__));
++#ifdef DYNAMIC_SWOOB_DURATION
++				intr_width = 0;
++				ret = dhd_iovar(dhd, 0, "bus:intr_width", (char *)&intr_width,
++						sizeof(intr_width), NULL, 0, TRUE);
++				if (ret < 0) {
++					DHD_ERROR(("failed to set intr_width (%d)\n", ret));
++				}
++#endif /* DYNAMIC_SWOOB_DURATION */
++#ifndef SUPPORT_PM2_ONLY
++				power_mode = PM_FAST;
++				dhd_wl_ioctl_cmd(dhd, WLC_SET_PM, (char *)&power_mode,
++				                 sizeof(power_mode), TRUE, 0);
++#endif /* SUPPORT_PM2_ONLY */
++#ifdef PKT_FILTER_SUPPORT
++				/* disable pkt filter */
++				dhd_enable_packet_filter(0, dhd);
++#endif /* PKT_FILTER_SUPPORT */
++
++				/* restore pre-suspend setting for dtim_skip */
++				dhd_iovar(dhd, 0, "bcn_li_dtim", (char *)&bcn_li_dtim,
++						sizeof(bcn_li_dtim), NULL, 0, TRUE);
++#ifdef CUSTOM_BCN_TIMEOUT_IN_SUSPEND
++				bcn_timeout = CUSTOM_BCN_TIMEOUT;
++				dhd_iovar(dhd, 0, "bcn_timeout", (char *)&bcn_timeout,
++						sizeof(bcn_timeout), NULL, 0, TRUE);
++#endif /* CUSTOM_BCN_TIMEOUT_IN_SUSPEND */
++#ifdef CUSTOM_ROAM_TIME_THRESH_IN_SUSPEND
++				roam_time_thresh = 2000;
++				dhd_iovar(dhd, 0, "roam_time_thresh", (char *)&roam_time_thresh,
++						sizeof(roam_time_thresh), NULL, 0, TRUE);
++#endif /* CUSTOM_ROAM_TIME_THRESH_IN_SUSPEND */
++#ifndef ENABLE_FW_ROAM_SUSPEND
++				roamvar = dhd_roam_disable;
++				dhd_iovar(dhd, 0, "roam_off", (char *)&roamvar, sizeof(roamvar),
++						NULL, 0, TRUE);
++#endif /* ENABLE_FW_ROAM_SUSPEND */
++				if (FW_SUPPORTED(dhd, ndoe)) {
++					/* disable IPv6 RA filter in  firmware during suspend */
++					nd_ra_filter = 0;
++					ret = dhd_iovar(dhd, 0, "nd_ra_filter_enable",
++							(char *)&nd_ra_filter, sizeof(nd_ra_filter),
++							NULL, 0, TRUE);
++					if (ret < 0)
++						DHD_ERROR(("nd_ra_filter: %d\n", ret));
++				}
++				dhd_os_suppress_logging(dhd, FALSE);
++			}
++	}
++	dhd_suspend_unlock(dhd);
++
++	return 0;
++}
++
++static int dhd_suspend_resume_helper(struct dhd_info *dhd, int val, int force)
++{
++	dhd_pub_t *dhdp = &dhd->pub;
++	int ret = 0;
++
++	DHD_OS_WAKE_LOCK(dhdp);
++	DHD_PERIM_LOCK(dhdp);
++
++	/* Set flag when early suspend was called */
++	dhdp->in_suspend = val;
++	if ((force || !dhdp->suspend_disable_flag) &&
++		dhd_support_sta_mode(dhdp))
++	{
++		ret = dhd_set_suspend(val, dhdp);
++	}
++
++	DHD_PERIM_UNLOCK(dhdp);
++	DHD_OS_WAKE_UNLOCK(dhdp);
++	return ret;
++}
++
++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND)
++static void dhd_early_suspend(struct early_suspend *h)
++{
++	struct dhd_info *dhd = container_of(h, struct dhd_info, early_suspend);
++	DHD_TRACE_HW4(("%s: enter\n", __FUNCTION__));
++
++	if (dhd)
++		dhd_suspend_resume_helper(dhd, 1, 0);
++}
++
++static void dhd_late_resume(struct early_suspend *h)
++{
++	struct dhd_info *dhd = container_of(h, struct dhd_info, early_suspend);
++	DHD_TRACE_HW4(("%s: enter\n", __FUNCTION__));
++
++	if (dhd)
++		dhd_suspend_resume_helper(dhd, 0, 0);
++}
++#endif /* CONFIG_HAS_EARLYSUSPEND && DHD_USE_EARLYSUSPEND */
++
++/*
++ * Generalized timeout mechanism.  Uses spin sleep with exponential back-off until
++ * the sleep time reaches one jiffy, then switches over to task delay.  Usage:
++ *
++ *      dhd_timeout_start(&tmo, usec);
++ *      while (!dhd_timeout_expired(&tmo))
++ *              if (poll_something())
++ *                      break;
++ *      if (dhd_timeout_expired(&tmo))
++ *              fatal();
++ */
++
++void
++dhd_timeout_start(dhd_timeout_t *tmo, uint usec)
++{
++	tmo->limit = usec;
++	tmo->increment = 0;
++	tmo->elapsed = 0;
++	tmo->tick = jiffies_to_usecs(1);
++}
++
++int
++dhd_timeout_expired(dhd_timeout_t *tmo)
++{
++	/* Does nothing the first call */
++	if (tmo->increment == 0) {
++		tmo->increment = 1;
++		return 0;
++	}
++
++	if (tmo->elapsed >= tmo->limit)
++		return 1;
++
++	/* Add the delay that's about to take place */
++	tmo->elapsed += tmo->increment;
++
++	if ((!CAN_SLEEP()) || tmo->increment < tmo->tick) {
++		OSL_DELAY(tmo->increment);
++		tmo->increment *= 2;
++		if (tmo->increment > tmo->tick)
++			tmo->increment = tmo->tick;
++	} else {
++		wait_queue_head_t delay_wait;
++		DECLARE_WAITQUEUE(wait, current);
++		init_waitqueue_head(&delay_wait);
++		add_wait_queue(&delay_wait, &wait);
++		set_current_state(TASK_INTERRUPTIBLE);
++		(void)schedule_timeout(1);
++		remove_wait_queue(&delay_wait, &wait);
++		set_current_state(TASK_RUNNING);
++	}
++
++	return 0;
++}
++
++int
++dhd_net2idx(dhd_info_t *dhd, struct net_device *net)
++{
++	int i = 0;
++
++	if (!dhd) {
++		DHD_ERROR(("%s : DHD_BAD_IF return\n", __FUNCTION__));
++		return DHD_BAD_IF;
++	}
++
++	while (i < DHD_MAX_IFS) {
++		if (dhd->iflist[i] && dhd->iflist[i]->net && (dhd->iflist[i]->net == net))
++			return i;
++		i++;
++	}
++
++	return DHD_BAD_IF;
++}
++
++struct net_device * dhd_idx2net(void *pub, int ifidx)
++{
++	struct dhd_pub *dhd_pub = (struct dhd_pub *)pub;
++	struct dhd_info *dhd_info;
++
++	if (!dhd_pub || ifidx < 0 || ifidx >= DHD_MAX_IFS)
++		return NULL;
++	dhd_info = dhd_pub->info;
++	if (dhd_info && dhd_info->iflist[ifidx])
++		return dhd_info->iflist[ifidx]->net;
++	return NULL;
++}
++
++int
++dhd_ifname2idx(dhd_info_t *dhd, char *name)
++{
++	int i = DHD_MAX_IFS;
++
++	ASSERT(dhd);
++
++	if (name == NULL || *name == '\0')
++		return 0;
++
++	while (--i > 0)
++		if (dhd->iflist[i] && !strncmp(dhd->iflist[i]->dngl_name, name, IFNAMSIZ))
++				break;
++
++	DHD_TRACE(("%s: return idx %d for \"%s\"\n", __FUNCTION__, i, name));
++
++	return i;	/* default - the primary interface */
++}
++
++char *
++dhd_ifname(dhd_pub_t *dhdp, int ifidx)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++
++	ASSERT(dhd);
++
++	if (ifidx < 0 || ifidx >= DHD_MAX_IFS) {
++		DHD_ERROR(("%s: ifidx %d out of range\n", __FUNCTION__, ifidx));
++		return "<if_bad>";
++	}
++
++	if (dhd->iflist[ifidx] == NULL) {
++		DHD_ERROR(("%s: null i/f %d\n", __FUNCTION__, ifidx));
++		return "<if_null>";
++	}
++
++	if (dhd->iflist[ifidx]->net)
++		return dhd->iflist[ifidx]->net->name;
++
++	return "<if_none>";
++}
++
++uint8 *
++dhd_bssidx2bssid(dhd_pub_t *dhdp, int idx)
++{
++	int i;
++	dhd_info_t *dhd = (dhd_info_t *)dhdp;
++
++	ASSERT(dhd);
++	for (i = 0; i < DHD_MAX_IFS; i++)
++	if (dhd->iflist[i] && dhd->iflist[i]->bssidx == idx)
++		return dhd->iflist[i]->mac_addr;
++
++	return NULL;
++}
++
++#ifdef BCMDBUS
++#define DBUS_NRXQ	50
++#define DBUS_NTXQ	100
++
++static void
++dhd_dbus_send_complete(void *handle, void *info, int status)
++{
++	dhd_info_t *dhd = (dhd_info_t *)handle;
++	void *pkt = info;
++
++	if ((dhd == NULL) || (pkt == NULL))
++		return;
++
++	if (status == DBUS_OK) {
++		dhd->pub.dstats.tx_packets++;
++	} else {
++		DHD_ERROR(("TX error=%d\n", status));
++		dhd->pub.dstats.tx_errors++;
++	}
++#ifdef PROP_TXSTATUS
++	if (DHD_PKTTAG_WLFCPKT(PKTTAG(pkt)) &&
++		(dhd_wlfc_txcomplete(&dhd->pub, pkt, status == 0) != WLFC_UNSUPPORTED)) {
++		return;
++	}
++#endif /* PROP_TXSTATUS */
++	PKTFREE(dhd->pub.osh, pkt, TRUE);
++}
++
++static void
++dhd_dbus_recv_pkt(void *handle, void *pkt)
++{
++	uchar reorder_info_buf[WLHOST_REORDERDATA_TOTLEN];
++	uint reorder_info_len;
++	uint pkt_count;
++	dhd_info_t *dhd = (dhd_info_t *)handle;
++	int ifidx = 0;
++
++	if (dhd == NULL)
++		return;
++
++	/* If the protocol uses a data header, check and remove it */
++	if (dhd_prot_hdrpull(&dhd->pub, &ifidx, pkt, reorder_info_buf,
++		&reorder_info_len) != 0) {
++		DHD_ERROR(("rx protocol error\n"));
++		PKTFREE(dhd->pub.osh, pkt, FALSE);
++		dhd->pub.rx_errors++;
++		return;
++	}
++
++	if (reorder_info_len) {
++		/* Reordering info from the firmware */
++		dhd_process_pkt_reorder_info(&dhd->pub, reorder_info_buf, reorder_info_len,
++			&pkt, &pkt_count);
++		if (pkt_count == 0)
++			return;
++	}
++	else {
++		pkt_count = 1;
++	}
++	dhd_rx_frame(&dhd->pub, ifidx, pkt, pkt_count, 0);
++}
++
++static void
++dhd_dbus_recv_buf(void *handle, uint8 *buf, int len)
++{
++	dhd_info_t *dhd = (dhd_info_t *)handle;
++	void *pkt;
++
++	if (dhd == NULL)
++		return;
++
++	if ((pkt = PKTGET(dhd->pub.osh, len, FALSE)) == NULL) {
++		DHD_ERROR(("PKTGET (rx) failed=%d\n", len));
++		return;
++	}
++
++	bcopy(buf, PKTDATA(dhd->pub.osh, pkt), len);
++	dhd_dbus_recv_pkt(dhd, pkt);
++}
++
++static void
++dhd_dbus_txflowcontrol(void *handle, bool onoff)
++{
++	dhd_info_t *dhd = (dhd_info_t *)handle;
++	bool wlfc_enabled = FALSE;
++
++	if (dhd == NULL)
++		return;
++
++#ifdef PROP_TXSTATUS
++	wlfc_enabled = (dhd_wlfc_flowcontrol(&dhd->pub, onoff, !onoff) != WLFC_UNSUPPORTED);
++#endif
++
++	if (!wlfc_enabled) {
++		dhd_txflowcontrol(&dhd->pub, ALL_INTERFACES, onoff);
++	}
++}
++
++static void
++dhd_dbus_errhandler(void *handle, int err)
++{
++}
++
++static void
++dhd_dbus_ctl_complete(void *handle, int type, int status)
++{
++	dhd_info_t *dhd = (dhd_info_t *)handle;
++
++	if (dhd == NULL)
++		return;
++
++	if (type == DBUS_CBCTL_READ) {
++		if (status == DBUS_OK)
++			dhd->pub.rx_ctlpkts++;
++		else
++			dhd->pub.rx_ctlerrs++;
++	} else if (type == DBUS_CBCTL_WRITE) {
++		if (status == DBUS_OK)
++			dhd->pub.tx_ctlpkts++;
++		else
++			dhd->pub.tx_ctlerrs++;
++	}
++
++	dhd_prot_ctl_complete(&dhd->pub);
++}
++
++static void
++dhd_dbus_state_change(void *handle, int state)
++{
++	dhd_info_t *dhd = (dhd_info_t *)handle;
++
++	if (dhd == NULL)
++		return;
++
++	switch (state) {
++
++		case DBUS_STATE_DL_NEEDED:
++#if defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW)
++#if defined(BCMDBUS)
++			DHD_TRACE(("%s: firmware request\n", __FUNCTION__));
++			up(&dhd->fw_download_lock);
++#endif /* BCMDBUS */
++#else
++			DHD_ERROR(("%s: firmware request cannot be handled\n", __FUNCTION__));
++#endif /* defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW) */
++			break;
++		case DBUS_STATE_DOWN:
++			DHD_TRACE(("%s: DBUS is down\n", __FUNCTION__));
++			dhd->pub.busstate = DHD_BUS_DOWN;
++			break;
++		case DBUS_STATE_UP:
++			DHD_TRACE(("%s: DBUS is up\n", __FUNCTION__));
++			dhd->pub.busstate = DHD_BUS_DATA;
++			break;
++		default:
++			break;
++	}
++
++	DHD_TRACE(("%s: DBUS current state=%d\n", __FUNCTION__, state));
++}
++
++static void *
++dhd_dbus_pktget(void *handle, uint len, bool send)
++{
++	dhd_info_t *dhd = (dhd_info_t *)handle;
++	void *p = NULL;
++
++	if (dhd == NULL)
++		return NULL;
++
++	if (send == TRUE) {
++		dhd_os_sdlock_txq(&dhd->pub);
++		p = PKTGET(dhd->pub.osh, len, TRUE);
++		dhd_os_sdunlock_txq(&dhd->pub);
++	} else {
++		dhd_os_sdlock_rxq(&dhd->pub);
++		p = PKTGET(dhd->pub.osh, len, FALSE);
++		dhd_os_sdunlock_rxq(&dhd->pub);
++	}
++
++	return p;
++}
++
++static void
++dhd_dbus_pktfree(void *handle, void *p, bool send)
++{
++	dhd_info_t *dhd = (dhd_info_t *)handle;
++
++	if (dhd == NULL)
++		return;
++
++	if (send == TRUE) {
++#ifdef PROP_TXSTATUS
++		if (DHD_PKTTAG_WLFCPKT(PKTTAG(p)) &&
++			(dhd_wlfc_txcomplete(&dhd->pub, p, FALSE) != WLFC_UNSUPPORTED)) {
++			return;
++		}
++#endif /* PROP_TXSTATUS */
++
++		dhd_os_sdlock_txq(&dhd->pub);
++		PKTFREE(dhd->pub.osh, p, TRUE);
++		dhd_os_sdunlock_txq(&dhd->pub);
++	} else {
++		dhd_os_sdlock_rxq(&dhd->pub);
++		PKTFREE(dhd->pub.osh, p, FALSE);
++		dhd_os_sdunlock_rxq(&dhd->pub);
++	}
++}
++
++#ifdef BCM_FD_AGGR
++
++static void
++dbus_rpcth_tx_complete(void *ctx, void *pktbuf, int status)
++{
++	dhd_info_t *dhd = (dhd_info_t *)ctx;
++	void *tmp;
++
++	while (pktbuf && dhd) {
++		tmp = PKTNEXT(dhd->pub.osh, pktbuf);
++		PKTSETNEXT(dhd->pub.osh, pktbuf, NULL);
++		dhd_dbus_send_complete(ctx, pktbuf, status);
++		pktbuf = tmp;
++	}
++}
++static void
++dbus_rpcth_rx_pkt(void *context, rpc_buf_t *rpc_buf)
++{
++	dhd_dbus_recv_pkt(context, rpc_buf);
++}
++
++static void
++dbus_rpcth_rx_aggrpkt(void *context, void *rpc_buf)
++{
++	dhd_info_t *dhd = (dhd_info_t *)context;
++
++	if (dhd == NULL)
++		return;
++
++	/* all the de-aggregated packets are delivered back to function dbus_rpcth_rx_pkt()
++	* as cloned packets
++	*/
++	bcm_rpc_dbus_recv_aggrpkt(dhd->rpc_th, rpc_buf,
++		bcm_rpc_buf_len_get(dhd->rpc_th, rpc_buf));
++
++	/* free the original packet */
++	dhd_dbus_pktfree(context, rpc_buf, FALSE);
++}
++
++static void
++dbus_rpcth_rx_aggrbuf(void *context, uint8 *buf, int len)
++{
++	dhd_info_t *dhd = (dhd_info_t *)context;
++
++	if (dhd == NULL)
++		return;
++
++	if (dhd->fdaggr & BCM_FDAGGR_D2H_ENABLED) {
++		bcm_rpc_dbus_recv_aggrbuf(dhd->rpc_th, buf, len);
++	}
++	else {
++		dhd_dbus_recv_buf(context, buf, len);
++	}
++
++}
++
++static void
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++dhd_rpcth_watchdog(struct timer_list *t)
++{
++	dhd_info_t *dhd = from_timer(dhd, t, rpcth_timer);
++#else
++dhd_rpcth_watchdog(ulong data)
++{
++	dhd_info_t *dhd = (dhd_info_t *)data;
++#endif
++
++	if (dhd->pub.dongle_reset) {
++		return;
++	}
++
++	dhd->rpcth_timer_active = FALSE;
++	/* release packets in the aggregation queue */
++	bcm_rpc_tp_watchdog(dhd->rpc_th);
++}
++
++static int
++dhd_fdaggr_ioctl(dhd_pub_t *dhd_pub, int ifindex, wl_ioctl_t *ioc, void *buf, int len)
++{
++	int bcmerror = 0;
++	void *rpc_th;
++
++	rpc_th = dhd_pub->info->rpc_th;
++
++	if (!strcmp("rpc_agg", ioc->buf)) {
++		uint32 rpc_agg;
++		uint32 rpc_agg_host;
++		uint32 rpc_agg_dngl;
++
++		if (ioc->set) {
++			memcpy(&rpc_agg, ioc->buf + strlen("rpc_agg") + 1, sizeof(uint32));
++			rpc_agg_host = rpc_agg & BCM_RPC_TP_HOST_AGG_MASK;
++			if (rpc_agg_host)
++				bcm_rpc_tp_agg_set(rpc_th, rpc_agg_host, TRUE);
++			else
++				bcm_rpc_tp_agg_set(rpc_th, BCM_RPC_TP_HOST_AGG_MASK, FALSE);
++			bcmerror = dhd_wl_ioctl(dhd_pub, ifindex, ioc, buf, len);
++			if (bcmerror < 0) {
++				DHD_ERROR(("usb aggregation not supported\n"));
++			} else {
++				dhd_pub->info->fdaggr = 0;
++				if (rpc_agg & BCM_RPC_TP_HOST_AGG_MASK)
++					dhd_pub->info->fdaggr |= BCM_FDAGGR_H2D_ENABLED;
++				if (rpc_agg & BCM_RPC_TP_DNGL_AGG_MASK)
++					dhd_pub->info->fdaggr |= BCM_FDAGGR_D2H_ENABLED;
++			}
++		} else {
++			rpc_agg_host = bcm_rpc_tp_agg_get(rpc_th);
++			bcmerror = dhd_wl_ioctl(dhd_pub, ifindex, ioc, buf, len);
++			if (!bcmerror) {
++				memcpy(&rpc_agg_dngl, buf, sizeof(uint32));
++				rpc_agg = (rpc_agg_host & BCM_RPC_TP_HOST_AGG_MASK) |
++					(rpc_agg_dngl & BCM_RPC_TP_DNGL_AGG_MASK);
++				memcpy(buf, &rpc_agg, sizeof(uint32));
++			}
++		}
++	} else if (!strcmp("rpc_host_agglimit", ioc->buf)) {
++		uint8 sf;
++		uint16 bytes;
++		uint32 agglimit;
++
++		if (ioc->set) {
++			memcpy(&agglimit, ioc->buf + strlen("rpc_host_agglimit") + 1,
++				sizeof(uint32));
++			sf = agglimit >> 16;
++			bytes = agglimit & 0xFFFF;
++			bcm_rpc_tp_agg_limit_set(rpc_th, sf, bytes);
++		} else {
++			bcm_rpc_tp_agg_limit_get(rpc_th, &sf, &bytes);
++			agglimit = (uint32)((sf << 16) + bytes);
++			memcpy(buf, &agglimit, sizeof(uint32));
++		}
++
++	} else {
++		bcmerror = dhd_wl_ioctl(dhd_pub, ifindex, ioc, buf, len);
++	}
++	return bcmerror;
++}
++#endif /* BCM_FD_AGGR */
++
++static dbus_callbacks_t dhd_dbus_cbs = {
++#ifdef BCM_FD_AGGR
++	dbus_rpcth_tx_complete,
++	dbus_rpcth_rx_aggrbuf,
++	dbus_rpcth_rx_aggrpkt,
++#else
++	dhd_dbus_send_complete,
++	dhd_dbus_recv_buf,
++	dhd_dbus_recv_pkt,
++#endif
++	dhd_dbus_txflowcontrol,
++	dhd_dbus_errhandler,
++	dhd_dbus_ctl_complete,
++	dhd_dbus_state_change,
++	dhd_dbus_pktget,
++	dhd_dbus_pktfree
++};
++
++void
++dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
++{
++	bcm_bprintf(strbuf, "Bus USB\n");
++}
++
++void
++dhd_bus_clearcounts(dhd_pub_t *dhdp)
++{
++}
++
++bool
++dhd_bus_dpc(struct dhd_bus *bus)
++{
++	return FALSE;
++}
++
++int
++dhd_dbus_txdata(dhd_pub_t *dhdp, void *pktbuf)
++{
++
++	if (dhdp->txoff)
++		return BCME_EPERM;
++#ifdef BCM_FD_AGGR
++	if (((dhd_info_t *)(dhdp->info))->fdaggr & BCM_FDAGGR_H2D_ENABLED)
++
++	{
++		dhd_info_t *dhd;
++		int ret;
++		dhd = (dhd_info_t *)(dhdp->info);
++		ret = bcm_rpc_tp_buf_send(dhd->rpc_th, pktbuf);
++		if (dhd->rpcth_timer_active == FALSE) {
++			dhd->rpcth_timer_active = TRUE;
++			mod_timer(&dhd->rpcth_timer, jiffies + BCM_RPC_TP_HOST_TMOUT * HZ / 1000);
++		}
++		return ret;
++	} else
++#endif /* BCM_FD_AGGR */
++	return dbus_send_txdata(dhdp->dbus, pktbuf);
++}
++
++#endif /* BCMDBUS */
++
++static void
++_dhd_set_multicast_list(dhd_info_t *dhd, int ifidx)
++{
++	struct net_device *dev;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)
++	struct netdev_hw_addr *ha;
++#else
++	struct dev_mc_list *mclist;
++#endif
++	uint32 allmulti, cnt;
++
++	wl_ioctl_t ioc;
++	char *buf, *bufp;
++	uint buflen;
++	int ret;
++
++	if (!dhd->iflist[ifidx]) {
++		DHD_ERROR(("%s : dhd->iflist[%d] was NULL\n", __FUNCTION__, ifidx));
++		return;
++	}
++	dev = dhd->iflist[ifidx]->net;
++	if (!dev)
++		return;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++	netif_addr_lock_bh(dev);
++#endif /* LINUX >= 2.6.27 */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)
++	cnt = netdev_mc_count(dev);
++#else
++	cnt = dev->mc_count;
++#endif /* LINUX >= 2.6.35 */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++	netif_addr_unlock_bh(dev);
++#endif /* LINUX >= 2.6.27 */
++
++	/* Determine initial value of allmulti flag */
++	allmulti = (dev->flags & IFF_ALLMULTI) ? TRUE : FALSE;
++
++
++	/* Send down the multicast list first. */
++
++
++	buflen = sizeof("mcast_list") + sizeof(cnt) + (cnt * ETHER_ADDR_LEN);
++	if (!(bufp = buf = MALLOC(dhd->pub.osh, buflen))) {
++		DHD_ERROR(("%s: out of memory for mcast_list, cnt %d\n",
++		           dhd_ifname(&dhd->pub, ifidx), cnt));
++		return;
++	}
++
++	strncpy(bufp, "mcast_list", buflen - 1);
++	bufp[buflen - 1] = '\0';
++	bufp += strlen("mcast_list") + 1;
++
++	cnt = htol32(cnt);
++	memcpy(bufp, &cnt, sizeof(cnt));
++	bufp += sizeof(cnt);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++	netif_addr_lock_bh(dev);
++#endif /* LINUX >= 2.6.27 */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)
++	netdev_for_each_mc_addr(ha, dev) {
++		if (!cnt)
++			break;
++		memcpy(bufp, ha->addr, ETHER_ADDR_LEN);
++		bufp += ETHER_ADDR_LEN;
++		cnt--;
++	}
++#else /* LINUX < 2.6.35 */
++	for (mclist = dev->mc_list; (mclist && (cnt > 0));
++		cnt--, mclist = mclist->next) {
++		memcpy(bufp, (void *)mclist->dmi_addr, ETHER_ADDR_LEN);
++		bufp += ETHER_ADDR_LEN;
++	}
++#endif /* LINUX >= 2.6.35 */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++	netif_addr_unlock_bh(dev);
++#endif /* LINUX >= 2.6.27 */
++
++	memset(&ioc, 0, sizeof(ioc));
++	ioc.cmd = WLC_SET_VAR;
++	ioc.buf = buf;
++	ioc.len = buflen;
++	ioc.set = TRUE;
++
++	ret = dhd_wl_ioctl(&dhd->pub, ifidx, &ioc, ioc.buf, ioc.len);
++	if (ret < 0) {
++		DHD_ERROR(("%s: set mcast_list failed, cnt %d\n",
++			dhd_ifname(&dhd->pub, ifidx), cnt));
++		allmulti = cnt ? TRUE : allmulti;
++	}
++
++	MFREE(dhd->pub.osh, buf, buflen);
++
++	/* Now send the allmulti setting.  This is based on the setting in the
++	 * net_device flags, but might be modified above to be turned on if we
++	 * were trying to set some addresses and dongle rejected it...
++	 */
++
++	allmulti = htol32(allmulti);
++	ret = dhd_iovar(&dhd->pub, ifidx, "allmulti", (char *)&allmulti,
++			sizeof(allmulti), NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: set allmulti %d failed\n",
++		           dhd_ifname(&dhd->pub, ifidx), ltoh32(allmulti)));
++	}
++
++	/* Finally, pick up the PROMISC flag as well, like the NIC driver does */
++
++	allmulti = (dev->flags & IFF_PROMISC) ? TRUE : FALSE;
++
++	allmulti = htol32(allmulti);
++
++	memset(&ioc, 0, sizeof(ioc));
++	ioc.cmd = WLC_SET_PROMISC;
++	ioc.buf = &allmulti;
++	ioc.len = sizeof(allmulti);
++	ioc.set = TRUE;
++
++	ret = dhd_wl_ioctl(&dhd->pub, ifidx, &ioc, ioc.buf, ioc.len);
++	if (ret < 0) {
++		DHD_ERROR(("%s: set promisc %d failed\n",
++		           dhd_ifname(&dhd->pub, ifidx), ltoh32(allmulti)));
++	}
++}
++
++int
++_dhd_set_mac_address(dhd_info_t *dhd, int ifidx, uint8 *addr)
++{
++	int ret;
++
++	ret = dhd_iovar(&dhd->pub, ifidx, "cur_etheraddr", (char *)addr,
++			ETHER_ADDR_LEN, NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: set cur_etheraddr failed\n", dhd_ifname(&dhd->pub, ifidx)));
++	} else {
++		memcpy(dhd->iflist[ifidx]->net->dev_addr, addr, ETHER_ADDR_LEN);
++		if (ifidx == 0)
++			memcpy(dhd->pub.mac.octet, addr, ETHER_ADDR_LEN);
++	}
++
++	return ret;
++}
++
++#ifdef SOFTAP
++extern struct net_device *ap_net_dev;
++extern tsk_ctl_t ap_eth_ctl; /* ap netdev heper thread ctl */
++#endif
++
++#ifdef DHD_WMF
++void dhd_update_psta_interface_for_sta(dhd_pub_t* dhdp, char* ifname, void* ea,
++		void* event_data)
++{
++	struct wl_psta_primary_intf_event *psta_prim_event =
++			(struct wl_psta_primary_intf_event*)event_data;
++	dhd_sta_t *psta_interface =  NULL;
++	dhd_sta_t *sta = NULL;
++	uint8 ifindex;
++	ASSERT(ifname);
++	ASSERT(psta_prim_event);
++	ASSERT(ea);
++
++	ifindex = (uint8)dhd_ifname2idx(dhdp->info, ifname);
++	sta = dhd_find_sta(dhdp, ifindex, ea);
++	if (sta != NULL) {
++		psta_interface = dhd_find_sta(dhdp, ifindex,
++				(void *)(psta_prim_event->prim_ea.octet));
++		if (psta_interface != NULL) {
++			sta->psta_prim = psta_interface;
++		}
++	}
++}
++
++/* Get wmf_psta_disable configuration configuration */
++int dhd_get_wmf_psta_disable(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++	ASSERT(idx < DHD_MAX_IFS);
++	ifp = dhd->iflist[idx];
++	return ifp->wmf_psta_disable;
++}
++
++/* Set wmf_psta_disable configuration configuration */
++int dhd_set_wmf_psta_disable(dhd_pub_t *dhdp, uint32 idx, int val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++	ASSERT(idx < DHD_MAX_IFS);
++	ifp = dhd->iflist[idx];
++	ifp->wmf_psta_disable = val;
++	return 0;
++}
++#endif /* DHD_WMF */
++
++#ifdef DHD_PSTA
++/* Get psta/psr configuration configuration */
++int dhd_get_psta_mode(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++	return (int)dhd->psta_mode;
++}
++/* Set psta/psr configuration configuration */
++int dhd_set_psta_mode(dhd_pub_t *dhdp, uint32 val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd->psta_mode = val;
++	return 0;
++}
++#endif /* DHD_PSTA */
++
++#if (defined(DHD_WET) || defined(DHD_MCAST_REGEN) || defined(DHD_L2_FILTER))
++static void
++dhd_update_rx_pkt_chainable_state(dhd_pub_t* dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	if (
++#ifdef DHD_L2_FILTER
++		(ifp->block_ping) ||
++#endif
++#ifdef DHD_WET
++		(dhd->wet_mode) ||
++#endif
++#ifdef DHD_MCAST_REGEN
++		(ifp->mcast_regen_bss_enable) ||
++#endif
++		FALSE) {
++		ifp->rx_pkt_chainable = FALSE;
++	}
++}
++#endif /* DHD_WET || DHD_MCAST_REGEN || DHD_L2_FILTER */
++
++#ifdef DHD_WET
++/* Get wet configuration configuration */
++int dhd_get_wet_mode(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++	return (int)dhd->wet_mode;
++}
++
++/* Set wet configuration configuration */
++int dhd_set_wet_mode(dhd_pub_t *dhdp, uint32 val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd->wet_mode = val;
++
++	/* disable rx_pkt_chainable stae for dhd interface, if WET is enabled */
++	dhd_update_rx_pkt_chainable_state(dhdp, 0);
++	return 0;
++}
++#endif /* DHD_WET */
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 11, 0))
++int32 dhd_role_to_nl80211_iftype(int32 role)
++{
++	switch (role) {
++	case WLC_E_IF_ROLE_STA:
++		return NL80211_IFTYPE_STATION;
++	case WLC_E_IF_ROLE_AP:
++		return NL80211_IFTYPE_AP;
++	case WLC_E_IF_ROLE_WDS:
++		return NL80211_IFTYPE_WDS;
++	case WLC_E_IF_ROLE_P2P_GO:
++		return NL80211_IFTYPE_P2P_GO;
++	case WLC_E_IF_ROLE_P2P_CLIENT:
++		return NL80211_IFTYPE_P2P_CLIENT;
++	case WLC_E_IF_ROLE_IBSS:
++		return NL80211_IFTYPE_ADHOC;
++	default:
++		return NL80211_IFTYPE_UNSPECIFIED;
++	}
++}
++#endif /* OEM_ANDROID && (LINUX_VERSION_CODE > KERNEL_VERSION(3, 11, 0)) */
++
++static void
++dhd_ifadd_event_handler(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++	dhd_if_event_t *if_event = event_info;
++	struct net_device *ndev;
++	int ifidx, bssidx;
++	int ret;
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 11, 0))
++	struct wireless_dev *vwdev, *primary_wdev;
++	struct net_device *primary_ndev;
++#endif /* OEM_ANDROID && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) */
++
++	if (event != DHD_WQ_WORK_IF_ADD) {
++		DHD_ERROR(("%s: unexpected event \n", __FUNCTION__));
++		return;
++	}
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd info not available \n", __FUNCTION__));
++		return;
++	}
++
++	if (!if_event) {
++		DHD_ERROR(("%s: event data is null \n", __FUNCTION__));
++		return;
++	}
++
++	dhd_net_if_lock_local(dhd);
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK(&dhd->pub);
++
++	ifidx = if_event->event.ifidx;
++	bssidx = if_event->event.bssidx;
++	DHD_TRACE(("%s: registering if with ifidx %d\n", __FUNCTION__, ifidx));
++
++	/* This path is for non-android case */
++	/* The interface name in host and in event msg are same */
++	/* if name in event msg is used to create dongle if list on host */
++	ndev = dhd_allocate_if(&dhd->pub, ifidx, if_event->name,
++		if_event->mac, bssidx, TRUE, if_event->name);
++	if (!ndev) {
++		DHD_ERROR(("%s: net device alloc failed  \n", __FUNCTION__));
++		goto done;
++	}
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 11, 0))
++	vwdev = kzalloc(sizeof(*vwdev), GFP_KERNEL);
++	if (unlikely(!vwdev)) {
++		DHD_ERROR(("Could not allocate wireless device\n"));
++		goto done;
++	}
++	primary_ndev = dhd->pub.info->iflist[0]->net;
++	primary_wdev = ndev_to_wdev(primary_ndev);
++	vwdev->wiphy = primary_wdev->wiphy;
++	vwdev->iftype = dhd_role_to_nl80211_iftype(if_event->event.role);
++	vwdev->netdev = ndev;
++	ndev->ieee80211_ptr = vwdev;
++	SET_NETDEV_DEV(ndev, wiphy_dev(vwdev->wiphy));
++	DHD_ERROR(("virtual interface(%s) is created\n", if_event->name));
++#endif /* OEM_ANDROID && (LINUX_VERSION_CODE > KERNEL_VERSION(3, 11, 0)) */
++
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	ret = dhd_register_if(&dhd->pub, ifidx, TRUE);
++	DHD_PERIM_LOCK(&dhd->pub);
++	if (ret != BCME_OK) {
++		DHD_ERROR(("%s: dhd_register_if failed\n", __FUNCTION__));
++		dhd_remove_if(&dhd->pub, ifidx, TRUE);
++		goto done;
++	}
++#ifndef PCIE_FULL_DONGLE
++	/* Turn on AP isolation in the firmware for interfaces operating in AP mode */
++	if (FW_SUPPORTED((&dhd->pub), ap) && (if_event->event.role != WLC_E_IF_ROLE_STA)) {
++		uint32 var_int =  1;
++		ret = dhd_iovar(&dhd->pub, ifidx, "ap_isolate", (char *)&var_int, sizeof(var_int),
++				NULL, 0, TRUE);
++		if (ret != BCME_OK) {
++			DHD_ERROR(("%s: Failed to set ap_isolate to dongle\n", __FUNCTION__));
++			dhd_remove_if(&dhd->pub, ifidx, TRUE);
++		}
++	}
++#endif /* PCIE_FULL_DONGLE */
++
++done:
++	MFREE(dhd->pub.osh, if_event, sizeof(dhd_if_event_t));
++
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++	dhd_net_if_unlock_local(dhd);
++}
++
++static void
++dhd_ifdel_event_handler(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++	int ifidx;
++	dhd_if_event_t *if_event = event_info;
++
++
++	if (event != DHD_WQ_WORK_IF_DEL) {
++		DHD_ERROR(("%s: unexpected event \n", __FUNCTION__));
++		return;
++	}
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd info not available \n", __FUNCTION__));
++		return;
++	}
++
++	if (!if_event) {
++		DHD_ERROR(("%s: event data is null \n", __FUNCTION__));
++		return;
++	}
++
++	dhd_net_if_lock_local(dhd);
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK(&dhd->pub);
++
++	ifidx = if_event->event.ifidx;
++	DHD_TRACE(("Removing interface with idx %d\n", ifidx));
++
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	dhd_remove_if(&dhd->pub, ifidx, TRUE);
++	DHD_PERIM_LOCK(&dhd->pub);
++
++	MFREE(dhd->pub.osh, if_event, sizeof(dhd_if_event_t));
++
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++	dhd_net_if_unlock_local(dhd);
++}
++
++static void
++dhd_set_mac_addr_handler(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++	dhd_if_t *ifp = event_info;
++
++	if (event != DHD_WQ_WORK_SET_MAC) {
++		DHD_ERROR(("%s: unexpected event \n", __FUNCTION__));
++	}
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd info not available \n", __FUNCTION__));
++		return;
++	}
++
++	dhd_net_if_lock_local(dhd);
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK(&dhd->pub);
++
++#ifdef SOFTAP
++	{
++		unsigned long flags;
++		bool in_ap = FALSE;
++		DHD_GENERAL_LOCK(&dhd->pub, flags);
++		in_ap = (ap_net_dev != NULL);
++		DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++
++		if (in_ap)  {
++			DHD_ERROR(("attempt to set MAC for %s in AP Mode, blocked. \n",
++			           ifp->net->name));
++			goto done;
++		}
++	}
++#endif /* SOFTAP */
++
++	if (ifp == NULL || !dhd->pub.up) {
++		DHD_ERROR(("%s: interface info not available/down \n", __FUNCTION__));
++		goto done;
++	}
++
++	DHD_ERROR(("%s: MACID is overwritten\n", __FUNCTION__));
++	ifp->set_macaddress = FALSE;
++	if (_dhd_set_mac_address(dhd, ifp->idx, ifp->mac_addr) == 0)
++		DHD_INFO(("%s: MACID is overwritten\n",	__FUNCTION__));
++	else
++		DHD_ERROR(("%s: _dhd_set_mac_address() failed\n", __FUNCTION__));
++
++done:
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++	dhd_net_if_unlock_local(dhd);
++}
++
++static void
++dhd_set_mcast_list_handler(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++	dhd_if_t *ifp = event_info;
++	int ifidx;
++
++	if (event != DHD_WQ_WORK_SET_MCAST_LIST) {
++		DHD_ERROR(("%s: unexpected event \n", __FUNCTION__));
++		return;
++	}
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd info not available \n", __FUNCTION__));
++		return;
++	}
++
++	dhd_net_if_lock_local(dhd);
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK(&dhd->pub);
++
++#ifdef SOFTAP
++	{
++		bool in_ap = FALSE;
++		unsigned long flags;
++		DHD_GENERAL_LOCK(&dhd->pub, flags);
++		in_ap = (ap_net_dev != NULL);
++		DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++
++		if (in_ap)  {
++			DHD_ERROR(("set MULTICAST list for %s in AP Mode, blocked. \n",
++			           ifp->net->name));
++			ifp->set_multicast = FALSE;
++			goto done;
++		}
++	}
++#endif /* SOFTAP */
++
++	if (ifp == NULL || !dhd->pub.up) {
++		DHD_ERROR(("%s: interface info not available/down \n", __FUNCTION__));
++		goto done;
++	}
++
++	ifidx = ifp->idx;
++
++
++	_dhd_set_multicast_list(dhd, ifidx);
++	DHD_INFO(("%s: set multicast list for if %d\n", __FUNCTION__, ifidx));
++
++done:
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++	dhd_net_if_unlock_local(dhd);
++}
++
++static int
++dhd_set_mac_address(struct net_device *dev, void *addr)
++{
++	int ret = 0;
++
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	struct sockaddr *sa = (struct sockaddr *)addr;
++	int ifidx;
++	dhd_if_t *dhdif;
++
++	ifidx = dhd_net2idx(dhd, dev);
++	if (ifidx == DHD_BAD_IF)
++		return -1;
++
++	dhdif = dhd->iflist[ifidx];
++
++	dhd_net_if_lock_local(dhd);
++	memcpy(dhdif->mac_addr, sa->sa_data, ETHER_ADDR_LEN);
++	dhdif->set_macaddress = TRUE;
++	dhd_net_if_unlock_local(dhd);
++	dhd_deferred_schedule_work(dhd->dhd_deferred_wq, (void *)dhdif, DHD_WQ_WORK_SET_MAC,
++		dhd_set_mac_addr_handler, DHD_WORK_PRIORITY_LOW);
++	return ret;
++}
++
++static void
++dhd_set_multicast_list(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ifidx;
++
++	ifidx = dhd_net2idx(dhd, dev);
++	if (ifidx == DHD_BAD_IF)
++		return;
++
++	dhd->iflist[ifidx]->set_multicast = TRUE;
++	dhd_deferred_schedule_work(dhd->dhd_deferred_wq, (void *)dhd->iflist[ifidx],
++		DHD_WQ_WORK_SET_MCAST_LIST, dhd_set_mcast_list_handler, DHD_WORK_PRIORITY_LOW);
++}
++
++#ifdef PROP_TXSTATUS
++int
++dhd_os_wlfc_block(dhd_pub_t *pub)
++{
++	dhd_info_t *di = (dhd_info_t *)(pub->info);
++	ASSERT(di != NULL);
++#ifdef BCMDBUS
++	spin_lock_irqsave(&di->wlfc_spinlock, di->wlfc_lock_flags);
++#else
++	spin_lock_bh(&di->wlfc_spinlock);
++#endif
++	return 1;
++}
++
++int
++dhd_os_wlfc_unblock(dhd_pub_t *pub)
++{
++	dhd_info_t *di = (dhd_info_t *)(pub->info);
++
++	ASSERT(di != NULL);
++#ifdef BCMDBUS
++	spin_unlock_irqrestore(&di->wlfc_spinlock, di->wlfc_lock_flags);
++#else
++	spin_unlock_bh(&di->wlfc_spinlock);
++#endif
++	return 1;
++}
++
++#endif /* PROP_TXSTATUS */
++
++#if defined(DHD_8021X_DUMP)
++void
++dhd_tx_dump(osl_t *osh, void *pkt)
++{
++	uint8 *dump_data;
++	uint16 protocol;
++
++	dump_data = PKTDATA(osh, pkt);
++	protocol = (dump_data[12] << 8) | dump_data[13];
++
++	if (protocol == ETHER_TYPE_802_1X) {
++		DHD_ERROR(("ETHER_TYPE_802_1X [TX]: ver %d, type %d, replay %d\n",
++			dump_data[14], dump_data[15], dump_data[30]));
++	}
++}
++#endif /* DHD_8021X_DUMP */
++
++/*  This routine do not support Packet chain feature, Currently tested for
++ *  proxy arp feature
++ */
++int dhd_sendup(dhd_pub_t *dhdp, int ifidx, void *p)
++{
++	struct sk_buff *skb;
++	void *skbhead = NULL;
++	void *skbprev = NULL;
++	dhd_if_t *ifp;
++	ASSERT(!PKTISCHAINED(p));
++	skb = PKTTONATIVE(dhdp->osh, p);
++
++	ifp = dhdp->info->iflist[ifidx];
++	skb->dev = ifp->net;
++#if defined(BCM_GMAC3)
++	/* Forwarder capable interfaces use WOFA based forwarding */
++	if (ifp->fwdh) {
++		struct ether_header *eh = (struct ether_header *)PKTDATA(dhdp->osh, p);
++		uint16 * da = (uint16 *)(eh->ether_dhost);
++		uintptr_t wofa_data;
++		ASSERT(ISALIGNED(da, 2));
++
++		wofa_data = fwder_lookup(ifp->fwdh->mate, da, ifp->idx);
++		if (wofa_data == WOFA_DATA_INVALID) { /* Unknown MAC address */
++			if (fwder_transmit(ifp->fwdh, skb, 1, skb->dev) == FWDER_SUCCESS) {
++				return BCME_OK;
++			}
++		}
++		PKTFRMNATIVE(dhdp->osh, p);
++		PKTFREE(dhdp->osh, p, FALSE);
++		return BCME_OK;
++	}
++#endif /* BCM_GMAC3 */
++
++	skb->protocol = eth_type_trans(skb, skb->dev);
++
++	if (in_interrupt()) {
++		bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE,
++			__FUNCTION__, __LINE__);
++		netif_rx(skb);
++	} else {
++		if (dhdp->info->rxthread_enabled) {
++			if (!skbhead) {
++				skbhead = skb;
++			} else {
++				PKTSETNEXT(dhdp->osh, skbprev, skb);
++			}
++			skbprev = skb;
++		} else {
++			/* If the receive is not processed inside an ISR,
++			 * the softirqd must be woken explicitly to service
++			 * the NET_RX_SOFTIRQ.	In 2.6 kernels, this is handled
++			 * by netif_rx_ni(), but in earlier kernels, we need
++			 * to do it manually.
++			 */
++			bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE,
++				__FUNCTION__, __LINE__);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
++			netif_rx_ni(skb);
++#else
++			ulong flags;
++			netif_rx(skb);
++			local_irq_save(flags);
++			RAISE_RX_SOFTIRQ();
++			local_irq_restore(flags);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0) */
++		}
++	}
++
++	if (dhdp->info->rxthread_enabled && skbhead)
++		dhd_sched_rxf(dhdp, skbhead);
++
++	return BCME_OK;
++}
++
++int BCMFASTPATH
++__dhd_sendpkt(dhd_pub_t *dhdp, int ifidx, void *pktbuf)
++{
++	int ret = BCME_OK;
++	dhd_info_t *dhd = (dhd_info_t *)(dhdp->info);
++	struct ether_header *eh = NULL;
++#if defined(DHD_L2_FILTER)
++	dhd_if_t *ifp = dhd_get_ifp(dhdp, ifidx);
++#endif 
++
++	/* Reject if down */
++	if (!dhdp->up || (dhdp->busstate == DHD_BUS_DOWN)) {
++		/* free the packet here since the caller won't */
++		PKTCFREE(dhdp->osh, pktbuf, TRUE);
++		return -ENODEV;
++	}
++
++#ifdef PCIE_FULL_DONGLE
++	if (dhdp->busstate == DHD_BUS_SUSPEND) {
++		DHD_ERROR(("%s : pcie is still in suspend state!!\n", __FUNCTION__));
++		PKTFREE(dhdp->osh, pktbuf, TRUE);
++		return -EBUSY;
++	}
++#endif /* PCIE_FULL_DONGLE */
++
++#ifdef DHD_L2_FILTER
++	/* if dhcp_unicast is enabled, we need to convert the */
++	/* broadcast DHCP ACK/REPLY packets to Unicast. */
++	if (ifp->dhcp_unicast) {
++	    uint8* mac_addr;
++	    uint8* ehptr = NULL;
++	    int ret;
++	    ret = bcm_l2_filter_get_mac_addr_dhcp_pkt(dhdp->osh, pktbuf, ifidx, &mac_addr);
++	    if (ret == BCME_OK) {
++		/*  if given mac address having valid entry in sta list
++		 *  copy the given mac address, and return with BCME_OK
++		*/
++		if (dhd_find_sta(dhdp, ifidx, mac_addr)) {
++		    ehptr = PKTDATA(dhdp->osh, pktbuf);
++		    bcopy(mac_addr, ehptr + ETHER_DEST_OFFSET, ETHER_ADDR_LEN);
++		}
++	    }
++	}
++
++	if (ifp->grat_arp && DHD_IF_ROLE_AP(dhdp, ifidx)) {
++	    if (bcm_l2_filter_gratuitous_arp(dhdp->osh, pktbuf) == BCME_OK) {
++			PKTCFREE(dhdp->osh, pktbuf, TRUE);
++			return BCME_ERROR;
++	    }
++	}
++
++	if (ifp->parp_enable && DHD_IF_ROLE_AP(dhdp, ifidx)) {
++		ret = dhd_l2_filter_pkt_handle(dhdp, ifidx, pktbuf, TRUE);
++
++		/* Drop the packets if l2 filter has processed it already
++		 * otherwise continue with the normal path
++		 */
++		if (ret == BCME_OK) {
++			PKTCFREE(dhdp->osh, pktbuf, TRUE);
++			return BCME_ERROR;
++		}
++	}
++#endif /* DHD_L2_FILTER */
++	/* Update multicast statistic */
++	if (PKTLEN(dhdp->osh, pktbuf) >= ETHER_HDR_LEN) {
++		uint8 *pktdata = (uint8 *)PKTDATA(dhdp->osh, pktbuf);
++		eh = (struct ether_header *)pktdata;
++
++		if (ETHER_ISMULTI(eh->ether_dhost))
++			dhdp->tx_multicast++;
++		if (ntoh16(eh->ether_type) == ETHER_TYPE_802_1X) {
++			DBG_EVENT_LOG(dhdp, WIFI_EVENT_DRIVER_EAPOL_FRAME_TRANSMIT_REQUESTED);
++			atomic_inc(&dhd->pend_8021x_cnt);
++		}
++#ifdef DHD_DHCP_DUMP
++		if (ntoh16(eh->ether_type) == ETHER_TYPE_IP) {
++			dhd_dhcp_dump(pktdata, TRUE);
++		}
++#endif /* DHD_DHCP_DUMP */
++	} else {
++			PKTCFREE(dhdp->osh, pktbuf, TRUE);
++			return BCME_ERROR;
++	}
++
++	{
++		/* Look into the packet and update the packet priority */
++#ifndef PKTPRIO_OVERRIDE
++		if (PKTPRIO(pktbuf) == 0)
++#endif 
++		{
++#if defined(QOS_MAP_SET)
++			pktsetprio_qms(pktbuf, wl_get_up_table(), FALSE);
++#else
++			pktsetprio(pktbuf, FALSE);
++#endif /* QOS_MAP_SET */
++		}
++	}
++
++
++#if defined(TRAFFIC_MGMT_DWM)
++	traffic_mgmt_pkt_set_prio(dhdp, pktbuf);
++
++#ifdef BCM_GMAC3
++	DHD_PKT_SET_DATAOFF(pktbuf, 0);
++#endif /* BCM_GMAC3 */
++#endif 
++
++#ifdef PCIE_FULL_DONGLE
++	/*
++	 * Lkup the per interface hash table, for a matching flowring. If one is not
++	 * available, allocate a unique flowid and add a flowring entry.
++	 * The found or newly created flowid is placed into the pktbuf's tag.
++	 */
++	ret = dhd_flowid_update(dhdp, ifidx, dhdp->flow_prio_map[(PKTPRIO(pktbuf))], pktbuf);
++	if (ret != BCME_OK) {
++		PKTCFREE(dhd->pub.osh, pktbuf, TRUE);
++		return ret;
++	}
++#endif
++
++#ifdef PROP_TXSTATUS
++	if (dhd_wlfc_is_supported(dhdp)) {
++		/* store the interface ID */
++		DHD_PKTTAG_SETIF(PKTTAG(pktbuf), ifidx);
++
++		/* store destination MAC in the tag as well */
++		DHD_PKTTAG_SETDSTN(PKTTAG(pktbuf), eh->ether_dhost);
++
++		/* decide which FIFO this packet belongs to */
++		if (ETHER_ISMULTI(eh->ether_dhost))
++			/* one additional queue index (highest AC + 1) is used for bc/mc queue */
++			DHD_PKTTAG_SETFIFO(PKTTAG(pktbuf), AC_COUNT);
++		else
++			DHD_PKTTAG_SETFIFO(PKTTAG(pktbuf), WME_PRIO2AC(PKTPRIO(pktbuf)));
++	} else
++#endif /* PROP_TXSTATUS */
++	{
++		/* If the protocol uses a data header, apply it */
++		dhd_prot_hdrpush(dhdp, ifidx, pktbuf);
++	}
++
++	/* Use bus module to send data frame */
++#ifdef WLMEDIA_HTSF
++	dhd_htsf_addtxts(dhdp, pktbuf);
++#endif
++#if defined(DHD_8021X_DUMP)
++	dhd_tx_dump(dhdp->osh, pktbuf);
++#endif
++#ifdef BCMDBUS
++#ifdef PROP_TXSTATUS
++	if (dhd_wlfc_commit_packets(dhdp, (f_commitpkt_t)dhd_dbus_txdata,
++		dhdp, pktbuf, TRUE) == WLFC_UNSUPPORTED) {
++		/* non-proptxstatus way */
++		ret = dhd_dbus_txdata(dhdp, pktbuf);
++	}
++#else
++	ret = dhd_dbus_txdata(dhdp, pktbuf);
++#endif /* PROP_TXSTATUS */
++	if (ret)
++		PKTCFREE(dhdp->osh, pktbuf, TRUE);
++#else
++#ifdef PROP_TXSTATUS
++	{
++		if (dhd_wlfc_commit_packets(dhdp, (f_commitpkt_t)dhd_bus_txdata,
++			dhdp->bus, pktbuf, TRUE) == WLFC_UNSUPPORTED) {
++			/* non-proptxstatus way */
++#ifdef BCMPCIE
++			ret = dhd_bus_txdata(dhdp->bus, pktbuf, (uint8)ifidx);
++#else
++			ret = dhd_bus_txdata(dhdp->bus, pktbuf);
++#endif /* BCMPCIE */
++		}
++	}
++#else
++#ifdef BCMPCIE
++	ret = dhd_bus_txdata(dhdp->bus, pktbuf, (uint8)ifidx);
++#else
++	ret = dhd_bus_txdata(dhdp->bus, pktbuf);
++#endif /* BCMPCIE */
++#endif /* PROP_TXSTATUS */
++
++#endif /* BCMDBUS */
++
++	return ret;
++}
++
++int BCMFASTPATH
++dhd_sendpkt(dhd_pub_t *dhdp, int ifidx, void *pktbuf)
++{
++	int ret = 0;
++	unsigned long flags;
++
++	DHD_GENERAL_LOCK(dhdp, flags);
++	if (dhdp->busstate == DHD_BUS_DOWN ||
++			dhdp->busstate == DHD_BUS_DOWN_IN_PROGRESS) {
++		DHD_ERROR(("%s: returning as busstate=%d\n",
++			__FUNCTION__, dhdp->busstate));
++		DHD_GENERAL_UNLOCK(dhdp, flags);
++		PKTCFREE(dhdp->osh, pktbuf, TRUE);
++		return -ENODEV;
++	}
++	dhdp->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_SEND_PKT;
++	DHD_GENERAL_UNLOCK(dhdp, flags);
++
++	ret = __dhd_sendpkt(dhdp, ifidx, pktbuf);
++
++	DHD_GENERAL_LOCK(dhdp, flags);
++	dhdp->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_SEND_PKT;
++	DHD_GENERAL_UNLOCK(dhdp, flags);
++	return ret;
++}
++
++int BCMFASTPATH
++dhd_start_xmit(struct sk_buff *skb, struct net_device *net)
++{
++	int ret;
++	uint datalen;
++	void *pktbuf;
++	dhd_info_t *dhd = DHD_DEV_INFO(net);
++	dhd_if_t *ifp = NULL;
++	int ifidx;
++	unsigned long flags;
++#ifdef WLMEDIA_HTSF
++	uint8 htsfdlystat_sz = dhd->pub.htsfdlystat_sz;
++#else
++	uint8 htsfdlystat_sz = 0;
++#endif 
++#ifdef DHD_WMF
++	struct ether_header *eh;
++	uint8 *iph;
++#endif /* DHD_WMF */
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	DHD_GENERAL_LOCK(&dhd->pub, flags);
++
++	if (dhd->pub.busstate == DHD_BUS_SUSPEND) {
++		DHD_ERROR(("%s : pcie is still in suspend state!!\n", __FUNCTION__));
++		dev_kfree_skb(skb);
++		ifp = DHD_DEV_IFP(net);
++		ifp->stats.tx_dropped++;
++		dhd->pub.tx_dropped++;
++		DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++		return -EBUSY;
++	}
++
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK_TRY(DHD_FWDER_UNIT(dhd), lock_taken);
++
++	/* Reject if down */
++	if (dhd->pub.hang_was_sent || dhd->pub.busstate == DHD_BUS_DOWN ||
++			dhd->pub.busstate == DHD_BUS_DOWN_IN_PROGRESS) {
++		DHD_ERROR(("%s: xmit rejected pub.up=%d busstate=%d \n",
++			__FUNCTION__, dhd->pub.up, dhd->pub.busstate));
++		netif_stop_queue(net);
++		/* Send Event when bus down detected during data session */
++		if (dhd->pub.up) {
++			DHD_ERROR(("%s: Event HANG sent up\n", __FUNCTION__));
++			net_os_send_hang_message(net);
++		}
++		DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++		DHD_PERIM_UNLOCK_TRY(DHD_FWDER_UNIT(dhd), lock_taken);
++		DHD_OS_WAKE_UNLOCK(&dhd->pub);
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20))
++		return -ENODEV;
++#else
++		return NETDEV_TX_BUSY;
++#endif
++	}
++
++	ifp = DHD_DEV_IFP(net);
++	ifidx = DHD_DEV_IFIDX(net);
++	BUZZZ_LOG(START_XMIT_BGN, 2, (uint32)ifidx, (uintptr)skb);
++
++	if (ifidx == DHD_BAD_IF) {
++		DHD_ERROR(("%s: bad ifidx %d\n", __FUNCTION__, ifidx));
++		netif_stop_queue(net);
++		DHD_PERIM_UNLOCK_TRY(DHD_FWDER_UNIT(dhd), lock_taken);
++		DHD_OS_WAKE_UNLOCK(&dhd->pub);
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20))
++		return -ENODEV;
++#else
++		return NETDEV_TX_BUSY;
++#endif
++	}
++
++	dhd->pub.dhd_bus_busy_state |= DHD_BUS_BUSY_IN_TX;
++	DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++
++	ASSERT(ifidx == dhd_net2idx(dhd, net));
++	ASSERT((ifp != NULL) && ((ifidx < DHD_MAX_IFS) && (ifp == dhd->iflist[ifidx])));
++
++	bcm_object_trace_opr(skb, BCM_OBJDBG_ADD_PKT, __FUNCTION__, __LINE__);
++
++	/* re-align socket buffer if "skb->data" is odd address */
++	if (((unsigned long)(skb->data)) & 0x1) {
++		unsigned char *data = skb->data;
++		uint32 length = skb->len;
++		PKTPUSH(dhd->pub.osh, skb, 1);
++		memmove(skb->data, data, length);
++		PKTSETLEN(dhd->pub.osh, skb, length);
++	}
++
++	datalen  = PKTLEN(dhd->pub.osh, skb);
++
++	/* Make sure there's enough room for any header */
++	if (skb_headroom(skb) < dhd->pub.hdrlen + htsfdlystat_sz) {
++		struct sk_buff *skb2;
++
++		DHD_INFO(("%s: insufficient headroom\n",
++		          dhd_ifname(&dhd->pub, ifidx)));
++		dhd->pub.tx_realloc++;
++
++		bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE, __FUNCTION__, __LINE__);
++		skb2 = skb_realloc_headroom(skb, dhd->pub.hdrlen + htsfdlystat_sz);
++
++		dev_kfree_skb(skb);
++		if ((skb = skb2) == NULL) {
++			DHD_ERROR(("%s: skb_realloc_headroom failed\n",
++			           dhd_ifname(&dhd->pub, ifidx)));
++			ret = -ENOMEM;
++			goto done;
++		}
++		bcm_object_trace_opr(skb, BCM_OBJDBG_ADD_PKT, __FUNCTION__, __LINE__);
++	}
++
++	/* Convert to packet */
++	if (!(pktbuf = PKTFRMNATIVE(dhd->pub.osh, skb))) {
++		DHD_ERROR(("%s: PKTFRMNATIVE failed\n",
++		           dhd_ifname(&dhd->pub, ifidx)));
++		bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE, __FUNCTION__, __LINE__);
++		dev_kfree_skb_any(skb);
++		ret = -ENOMEM;
++		goto done;
++	}
++
++#if defined(WLMEDIA_HTSF)
++	if (htsfdlystat_sz && PKTLEN(dhd->pub.osh, pktbuf) >= ETHER_ADDR_LEN) {
++		uint8 *pktdata = (uint8 *)PKTDATA(dhd->pub.osh, pktbuf);
++		struct ether_header *eh = (struct ether_header *)pktdata;
++
++		if (!ETHER_ISMULTI(eh->ether_dhost) &&
++			(ntoh16(eh->ether_type) == ETHER_TYPE_IP)) {
++			eh->ether_type = hton16(ETHER_TYPE_BRCM_PKTDLYSTATS);
++		}
++	}
++#endif 
++#ifdef DHD_WET
++	/* wet related packet proto manipulation should be done in DHD
++	 * since dongle doesn't have complete payload
++	 */
++	if (WET_ENABLED(&dhd->pub) &&
++			(dhd_wet_send_proc(dhd->pub.wet_info, pktbuf, &pktbuf) < 0)) {
++		DHD_INFO(("%s:%s: wet send proc failed\n",
++				__FUNCTION__, dhd_ifname(&dhd->pub, ifidx)));
++		PKTFREE(dhd->pub.osh, pktbuf, FALSE);
++		ret =  -EFAULT;
++		goto done;
++	}
++#endif /* DHD_WET */
++
++#ifdef DHD_WMF
++	eh = (struct ether_header *)PKTDATA(dhd->pub.osh, pktbuf);
++	iph = (uint8 *)eh + ETHER_HDR_LEN;
++
++	/* WMF processing for multicast packets
++	 * Only IPv4 packets are handled
++	 */
++	if (ifp->wmf.wmf_enable && (ntoh16(eh->ether_type) == ETHER_TYPE_IP) &&
++		(IP_VER(iph) == IP_VER_4) && (ETHER_ISMULTI(eh->ether_dhost) ||
++		((IPV4_PROT(iph) == IP_PROT_IGMP) && dhd->pub.wmf_ucast_igmp))) {
++#if defined(DHD_IGMP_UCQUERY) || defined(DHD_UCAST_UPNP)
++		void *sdu_clone;
++		bool ucast_convert = FALSE;
++#ifdef DHD_UCAST_UPNP
++		uint32 dest_ip;
++
++		dest_ip = ntoh32(*((uint32 *)(iph + IPV4_DEST_IP_OFFSET)));
++		ucast_convert = dhd->pub.wmf_ucast_upnp && MCAST_ADDR_UPNP_SSDP(dest_ip);
++#endif /* DHD_UCAST_UPNP */
++#ifdef DHD_IGMP_UCQUERY
++		ucast_convert |= dhd->pub.wmf_ucast_igmp_query &&
++			(IPV4_PROT(iph) == IP_PROT_IGMP) &&
++			(*(iph + IPV4_HLEN(iph)) == IGMPV2_HOST_MEMBERSHIP_QUERY);
++#endif /* DHD_IGMP_UCQUERY */
++		if (ucast_convert) {
++			dhd_sta_t *sta;
++			unsigned long flags;
++			struct list_head snapshot_list;
++			struct list_head *wmf_ucforward_list;
++
++			ret = NETDEV_TX_OK;
++
++			/* For non BCM_GMAC3 platform we need a snapshot sta_list to
++			 * resolve double DHD_IF_STA_LIST_LOCK call deadlock issue.
++			 */
++			wmf_ucforward_list = DHD_IF_WMF_UCFORWARD_LOCK(dhd, ifp, &snapshot_list);
++
++			/* Convert upnp/igmp query to unicast for each assoc STA */
++			list_for_each_entry(sta, wmf_ucforward_list, list) {
++				/* Skip sending to proxy interfaces of proxySTA */
++				if (sta->psta_prim != NULL && !ifp->wmf_psta_disable) {
++					continue;
++				}
++				if ((sdu_clone = PKTDUP(dhd->pub.osh, pktbuf)) == NULL) {
++					ret = WMF_NOP;
++					break;
++				}
++				dhd_wmf_forward(ifp->wmf.wmfh, sdu_clone, 0, sta, 1);
++			}
++			DHD_IF_WMF_UCFORWARD_UNLOCK(dhd, wmf_ucforward_list);
++
++			DHD_GENERAL_LOCK(&dhd->pub, flags);
++			dhd->pub.dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_TX;
++			dhd_os_busbusy_wake(&dhd->pub);
++			DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++			DHD_PERIM_UNLOCK_TRY(DHD_FWDER_UNIT(dhd), lock_taken);
++			DHD_OS_WAKE_UNLOCK(&dhd->pub);
++
++			if (ret == NETDEV_TX_OK)
++				PKTFREE(dhd->pub.osh, pktbuf, TRUE);
++
++			return ret;
++		} else
++#endif /* defined(DHD_IGMP_UCQUERY) || defined(DHD_UCAST_UPNP) */
++		{
++			/* There will be no STA info if the packet is coming from LAN host
++			 * Pass as NULL
++			 */
++			ret = dhd_wmf_packets_handle(&dhd->pub, pktbuf, NULL, ifidx, 0);
++			switch (ret) {
++			case WMF_TAKEN:
++			case WMF_DROP:
++				/* Either taken by WMF or we should drop it.
++				 * Exiting send path
++				 */
++
++				DHD_GENERAL_LOCK(&dhd->pub, flags);
++				dhd->pub.dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_TX;
++				dhd_os_busbusy_wake(&dhd->pub);
++				DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++				DHD_PERIM_UNLOCK_TRY(DHD_FWDER_UNIT(dhd), lock_taken);
++				DHD_OS_WAKE_UNLOCK(&dhd->pub);
++				return NETDEV_TX_OK;
++			default:
++				/* Continue the transmit path */
++				break;
++			}
++		}
++	}
++#endif /* DHD_WMF */
++#ifdef DHD_PSTA
++	/* PSR related packet proto manipulation should be done in DHD
++	 * since dongle doesn't have complete payload
++	 */
++	if (PSR_ENABLED(&dhd->pub) && (dhd_psta_proc(&dhd->pub,
++		ifidx, &pktbuf, TRUE) < 0)) {
++			DHD_ERROR(("%s:%s: psta send proc failed\n", __FUNCTION__,
++				dhd_ifname(&dhd->pub, ifidx)));
++	}
++#endif /* DHD_PSTA */
++
++#ifdef DHDTCPACK_SUPPRESS
++	if (dhd->pub.tcpack_sup_mode == TCPACK_SUP_HOLD) {
++		/* If this packet has been hold or got freed, just return */
++		if (dhd_tcpack_hold(&dhd->pub, pktbuf, ifidx)) {
++			ret = 0;
++			goto done;
++		}
++	} else {
++		/* If this packet has replaced another packet and got freed, just return */
++		if (dhd_tcpack_suppress(&dhd->pub, pktbuf)) {
++			ret = 0;
++			goto done;
++		}
++	}
++#endif /* DHDTCPACK_SUPPRESS */
++#ifdef HOST_FLAG
++	if (hostsleep) {
++		printf("%s (%d): hostsleep = %d, tx_dropped = %lu\n",__FUNCTION__, __LINE__,
++			hostsleep, ifp->stats.tx_dropped);
++		PKTFREE(dhd->pub.osh, pktbuf, TRUE);
++		ret = BCME_TXFAIL;
++		goto done;
++	}
++#endif
++
++	ret = __dhd_sendpkt(&dhd->pub, ifidx, pktbuf);
++
++done:
++	if (ret) {
++		ifp->stats.tx_dropped++;
++		dhd->pub.tx_dropped++;
++	} else {
++
++#ifdef PROP_TXSTATUS
++		/* tx_packets counter can counted only when wlfc is disabled */
++		if (!dhd_wlfc_is_supported(&dhd->pub))
++#endif
++		{
++			dhd->pub.tx_packets++;
++			ifp->stats.tx_packets++;
++			ifp->stats.tx_bytes += datalen;
++		}
++	}
++
++
++	DHD_GENERAL_LOCK(&dhd->pub, flags);
++	dhd->pub.dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_TX;
++	dhd_os_busbusy_wake(&dhd->pub);
++	DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++	DHD_PERIM_UNLOCK_TRY(DHD_FWDER_UNIT(dhd), lock_taken);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++
++	BUZZZ_LOG(START_XMIT_END, 0);
++
++	/* Return ok: we always eat the packet */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20))
++	return 0;
++#else
++	return NETDEV_TX_OK;
++#endif
++}
++
++
++void
++dhd_txflowcontrol(dhd_pub_t *dhdp, int ifidx, bool state)
++{
++	struct net_device *net;
++	dhd_info_t *dhd = dhdp->info;
++	int i;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	ASSERT(dhd);
++
++#ifdef DHD_LOSSLESS_ROAMING
++	/* block flowcontrol during roaming */
++	if ((dhdp->dequeue_prec_map == 1 << PRIO_8021D_NC) && state == ON) {
++		return;
++	}
++#endif
++
++	if (ifidx == ALL_INTERFACES) {
++		/* Flow control on all active interfaces */
++		dhdp->txoff = state;
++		for (i = 0; i < DHD_MAX_IFS; i++) {
++			if (dhd->iflist[i]) {
++				net = dhd->iflist[i]->net;
++				if (state == ON)
++					netif_stop_queue(net);
++				else
++					netif_wake_queue(net);
++			}
++		}
++	} else {
++		if (dhd->iflist[ifidx]) {
++			net = dhd->iflist[ifidx]->net;
++			if (state == ON)
++				netif_stop_queue(net);
++			else
++				netif_wake_queue(net);
++		}
++	}
++}
++
++#ifdef DHD_RX_DUMP
++typedef struct {
++	uint16 type;
++	const char *str;
++} PKTTYPE_INFO;
++
++static const PKTTYPE_INFO packet_type_info[] =
++{
++	{ ETHER_TYPE_IP, "IP" },
++	{ ETHER_TYPE_ARP, "ARP" },
++	{ ETHER_TYPE_BRCM, "BRCM" },
++	{ ETHER_TYPE_802_1X, "802.1X" },
++	{ ETHER_TYPE_WAI, "WAPI" },
++	{ 0, ""}
++};
++
++static const char *_get_packet_type_str(uint16 type)
++{
++	int i;
++	int n = sizeof(packet_type_info)/sizeof(packet_type_info[1]) - 1;
++
++	for (i = 0; i < n; i++) {
++		if (packet_type_info[i].type == type)
++			return packet_type_info[i].str;
++	}
++
++	return packet_type_info[n].str;
++}
++#endif /* DHD_RX_DUMP */
++
++
++#ifdef DHD_WMF
++bool
++dhd_is_rxthread_enabled(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++
++	return dhd->rxthread_enabled;
++}
++#endif /* DHD_WMF */
++
++void
++dhd_rx_mon_pkt(dhd_pub_t *dhdp, void *pkt, int ifidx)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++	struct sk_buff *skb;
++
++	skb = PKTTONATIVE(dhdp->osh, pkt);
++
++	if (dhd->monitor_type && dhd->monitor_dev)
++		skb->dev = dhd->monitor_dev;
++	else {
++		PKTFREE(dhdp->osh, pkt, FALSE);
++		return;
++	}
++
++	skb->protocol = eth_type_trans(skb, skb->dev);
++
++	if (in_interrupt()) {
++		bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE,
++			__FUNCTION__, __LINE__);
++		DHD_PERIM_UNLOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++		netif_rx(skb);
++		DHD_PERIM_LOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++	} else {
++		/* If the receive is not processed inside an ISR,
++		 * the softirqd must be woken explicitly to service
++		 * the NET_RX_SOFTIRQ.	In 2.6 kernels, this is handled
++		 * by netif_rx_ni(), but in earlier kernels, we need
++		 * to do it manually.
++		 */
++		bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE,
++			__FUNCTION__, __LINE__);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
++		DHD_PERIM_UNLOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++		netif_rx_ni(skb);
++		DHD_PERIM_LOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++#else
++		ulong flags;
++		DHD_PERIM_UNLOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++		netif_rx(skb);
++		DHD_PERIM_LOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++		local_irq_save(flags);
++		RAISE_RX_SOFTIRQ();
++		local_irq_restore(flags);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0) */
++	}
++}
++
++#ifdef DHD_MCAST_REGEN
++/*
++ * Description: This function is called to do the reverse translation
++ *
++ * Input    eh - pointer to the ethernet header
++ */
++int32
++dhd_mcast_reverse_translation(struct ether_header *eh)
++{
++	uint8 *iph;
++	uint32 dest_ip;
++
++	iph = (uint8 *)eh + ETHER_HDR_LEN;
++	dest_ip = ntoh32(*((uint32 *)(iph + IPV4_DEST_IP_OFFSET)));
++
++	/* Only IP packets are handled */
++	if (eh->ether_type != hton16(ETHER_TYPE_IP))
++		return BCME_ERROR;
++
++	/* Non-IPv4 multicast packets are not handled */
++	if (IP_VER(iph) != IP_VER_4)
++		return BCME_ERROR;
++
++	/*
++	 * The packet has a multicast IP and unicast MAC. That means
++	 * we have to do the reverse translation
++	 */
++	if (IPV4_ISMULTI(dest_ip) && !ETHER_ISMULTI(&eh->ether_dhost)) {
++		ETHER_FILL_MCAST_ADDR_FROM_IP(eh->ether_dhost, dest_ip);
++		return BCME_OK;
++	}
++
++	return BCME_ERROR;
++}
++#endif /* MCAST_REGEN */
++
++/** Called when a frame is received by the dongle on interface 'ifidx' */
++void
++dhd_rx_frame(dhd_pub_t *dhdp, int ifidx, void *pktbuf, int numpkt, uint8 chan)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++	struct sk_buff *skb;
++	uchar *eth;
++	uint len;
++	void *data, *pnext = NULL;
++	int i;
++	dhd_if_t *ifp;
++	wl_event_msg_t event;
++	int tout_rx = 0;
++	int tout_ctrl = 0;
++	void *skbhead = NULL;
++	void *skbprev = NULL;
++	uint16 protocol;
++#if defined(DHD_RX_DUMP) || defined(DHD_8021X_DUMP)
++	char *dump_data;
++#endif /* DHD_RX_DUMP || DHD_8021X_DUMP */
++#ifdef DHD_MCAST_REGEN
++	uint8 interface_role;
++	if_flow_lkup_t *if_flow_lkup;
++	unsigned long flags;
++#endif
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	for (i = 0; pktbuf && i < numpkt; i++, pktbuf = pnext) {
++		struct ether_header *eh;
++
++		pnext = PKTNEXT(dhdp->osh, pktbuf);
++		PKTSETNEXT(dhdp->osh, pktbuf, NULL);
++
++		ifp = dhd->iflist[ifidx];
++		if (ifp == NULL) {
++			DHD_ERROR(("%s: ifp is NULL. drop packet\n",
++				__FUNCTION__));
++			PKTCFREE(dhdp->osh, pktbuf, FALSE);
++			continue;
++		}
++
++		eh = (struct ether_header *)PKTDATA(dhdp->osh, pktbuf);
++
++		/* Dropping only data packets before registering net device to avoid kernel panic */
++#ifndef PROP_TXSTATUS_VSDB
++		if ((!ifp->net || ifp->net->reg_state != NETREG_REGISTERED) &&
++			(ntoh16(eh->ether_type) != ETHER_TYPE_BRCM)) {
++#else
++		if ((!ifp->net || ifp->net->reg_state != NETREG_REGISTERED || !dhd->pub.up) &&
++			(ntoh16(eh->ether_type) != ETHER_TYPE_BRCM)) {
++#endif /* PROP_TXSTATUS_VSDB */
++			DHD_ERROR(("%s: net device is NOT registered yet. drop packet\n",
++			__FUNCTION__));
++			PKTCFREE(dhdp->osh, pktbuf, FALSE);
++			continue;
++		}
++
++
++#ifdef PROP_TXSTATUS
++		if (dhd_wlfc_is_header_only_pkt(dhdp, pktbuf)) {
++			/* WLFC may send header only packet when
++			there is an urgent message but no packet to
++			piggy-back on
++			*/
++			PKTCFREE(dhdp->osh, pktbuf, FALSE);
++			continue;
++		}
++#endif
++#ifdef DHD_L2_FILTER
++		/* If block_ping is enabled drop the ping packet */
++		if (ifp->block_ping) {
++			if (bcm_l2_filter_block_ping(dhdp->osh, pktbuf) == BCME_OK) {
++				PKTCFREE(dhdp->osh, pktbuf, FALSE);
++				continue;
++			}
++		}
++		if (ifp->grat_arp && DHD_IF_ROLE_STA(dhdp, ifidx)) {
++		    if (bcm_l2_filter_gratuitous_arp(dhdp->osh, pktbuf) == BCME_OK) {
++				PKTCFREE(dhdp->osh, pktbuf, FALSE);
++				continue;
++		    }
++		}
++		if (ifp->parp_enable && DHD_IF_ROLE_AP(dhdp, ifidx)) {
++			int ret = dhd_l2_filter_pkt_handle(dhdp, ifidx, pktbuf, FALSE);
++
++			/* Drop the packets if l2 filter has processed it already
++			 * otherwise continue with the normal path
++			 */
++			if (ret == BCME_OK) {
++				PKTCFREE(dhdp->osh, pktbuf, TRUE);
++				continue;
++			}
++		}
++#endif /* DHD_L2_FILTER */
++
++#ifdef DHD_MCAST_REGEN
++		DHD_FLOWID_LOCK(dhdp->flowid_lock, flags);
++		if_flow_lkup = (if_flow_lkup_t *)dhdp->if_flow_lkup;
++		ASSERT(if_flow_lkup);
++
++		interface_role = if_flow_lkup[ifidx].role;
++		DHD_FLOWID_UNLOCK(dhdp->flowid_lock, flags);
++
++		if (ifp->mcast_regen_bss_enable && (interface_role != WLC_E_IF_ROLE_WDS) &&
++				!DHD_IF_ROLE_AP(dhdp, ifidx) &&
++				ETHER_ISUCAST(eh->ether_dhost)) {
++			if (dhd_mcast_reverse_translation(eh) ==  BCME_OK) {
++#ifdef DHD_PSTA
++				/* Change bsscfg to primary bsscfg for unicast-multicast packets */
++				if ((dhd_get_psta_mode(dhdp) == DHD_MODE_PSTA) ||
++						(dhd_get_psta_mode(dhdp) == DHD_MODE_PSR)) {
++					if (ifidx != 0) {
++						/* Let the primary in PSTA interface handle this
++						 * frame after unicast to Multicast conversion
++						 */
++						ifp = dhd_get_ifp(dhdp, 0);
++						ASSERT(ifp);
++					}
++				}
++			}
++#endif /* PSTA */
++		}
++#endif /* MCAST_REGEN */
++
++#ifdef DHD_WMF
++		/* WMF processing for multicast packets */
++		if (ifp->wmf.wmf_enable && (ETHER_ISMULTI(eh->ether_dhost))) {
++			dhd_sta_t *sta;
++			int ret;
++
++			sta = dhd_find_sta(dhdp, ifidx, (void *)eh->ether_shost);
++			ret = dhd_wmf_packets_handle(dhdp, pktbuf, sta, ifidx, 1);
++			switch (ret) {
++				case WMF_TAKEN:
++					/* The packet is taken by WMF. Continue to next iteration */
++					continue;
++				case WMF_DROP:
++					/* Packet DROP decision by WMF. Toss it */
++					DHD_ERROR(("%s: WMF decides to drop packet\n",
++						__FUNCTION__));
++					PKTCFREE(dhdp->osh, pktbuf, FALSE);
++					continue;
++				default:
++					/* Continue the transmit path */
++					break;
++			}
++		}
++#endif /* DHD_WMF */
++
++#ifdef DHDTCPACK_SUPPRESS
++		dhd_tcpdata_info_get(dhdp, pktbuf);
++#endif
++		skb = PKTTONATIVE(dhdp->osh, pktbuf);
++
++		ASSERT(ifp);
++		skb->dev = ifp->net;
++
++#ifdef DHD_WET
++		/* wet related packet proto manipulation should be done in DHD
++		 * since dongle doesn't have complete payload
++		 */
++		if (WET_ENABLED(&dhd->pub) && (dhd_wet_recv_proc(dhd->pub.wet_info,
++				pktbuf) < 0)) {
++			DHD_INFO(("%s:%s: wet recv proc failed\n",
++				__FUNCTION__, dhd_ifname(dhdp, ifidx)));
++		}
++#endif /* DHD_WET */
++
++#ifdef DHD_PSTA
++		if (PSR_ENABLED(dhdp) && (dhd_psta_proc(dhdp, ifidx, &pktbuf, FALSE) < 0)) {
++				DHD_ERROR(("%s:%s: psta recv proc failed\n", __FUNCTION__,
++					dhd_ifname(dhdp, ifidx)));
++		}
++#endif /* DHD_PSTA */
++
++#ifdef PCIE_FULL_DONGLE
++		if ((DHD_IF_ROLE_AP(dhdp, ifidx) || DHD_IF_ROLE_P2PGO(dhdp, ifidx)) &&
++			(!ifp->ap_isolate)) {
++			eh = (struct ether_header *)PKTDATA(dhdp->osh, pktbuf);
++			if (ETHER_ISUCAST(eh->ether_dhost)) {
++				if (dhd_find_sta(dhdp, ifidx, (void *)eh->ether_dhost)) {
++					dhd_sendpkt(dhdp, ifidx, pktbuf);
++					continue;
++				}
++			} else {
++				void *npktbuf = PKTDUP(dhdp->osh, pktbuf);
++				if (npktbuf)
++					dhd_sendpkt(dhdp, ifidx, npktbuf);
++			}
++		}
++#endif /* PCIE_FULL_DONGLE */
++
++		/* Get the protocol, maintain skb around eth_type_trans()
++		 * The main reason for this hack is for the limitation of
++		 * Linux 2.4 where 'eth_type_trans' uses the 'net->hard_header_len'
++		 * to perform skb_pull inside vs ETH_HLEN. Since to avoid
++		 * coping of the packet coming from the network stack to add
++		 * BDC, Hardware header etc, during network interface registration
++		 * we set the 'net->hard_header_len' to ETH_HLEN + extra space required
++		 * for BDC, Hardware header etc. and not just the ETH_HLEN
++		 */
++		eth = skb->data;
++		len = skb->len;
++
++#if defined(DHD_RX_DUMP) || defined(DHD_8021X_DUMP) || defined(DHD_DHCP_DUMP)
++		dump_data = skb->data;
++#endif /* DHD_RX_DUMP || DHD_8021X_DUMP || DHD_DHCP_DUMP */
++
++		protocol = (skb->data[12] << 8) | skb->data[13];
++		if (protocol == ETHER_TYPE_802_1X) {
++			DBG_EVENT_LOG(dhdp, WIFI_EVENT_DRIVER_EAPOL_FRAME_RECEIVED);
++#ifdef DHD_8021X_DUMP
++			DHD_ERROR(("ETHER_TYPE_802_1X [RX]: "
++				"ver %d, type %d, replay %d\n",
++				dump_data[14], dump_data[15],
++				dump_data[30]));
++#endif /* DHD_8021X_DUMP */
++		}
++
++#ifdef DHD_DHCP_DUMP
++		if (protocol != ETHER_TYPE_BRCM && protocol == ETHER_TYPE_IP) {
++			dhd_dhcp_dump(dump_data, FALSE);
++		}
++#endif /* DHD_DHCP_DUMP */
++#if defined(DHD_RX_DUMP)
++		DHD_ERROR(("RX DUMP - %s\n", _get_packet_type_str(protocol)));
++		if (protocol != ETHER_TYPE_BRCM) {
++			if (dump_data[0] == 0xFF) {
++				DHD_ERROR(("%s: BROADCAST\n", __FUNCTION__));
++
++				if ((dump_data[12] == 8) &&
++					(dump_data[13] == 6)) {
++					DHD_ERROR(("%s: ARP %d\n",
++						__FUNCTION__, dump_data[0x15]));
++				}
++			} else if (dump_data[0] & 1) {
++				DHD_ERROR(("%s: MULTICAST: " MACDBG "\n",
++					__FUNCTION__, MAC2STRDBG(dump_data)));
++			}
++#ifdef DHD_RX_FULL_DUMP
++			{
++				int k;
++				for (k = 0; k < skb->len; k++) {
++					DHD_ERROR(("%02X ", dump_data[k]));
++					if ((k & 15) == 15)
++						DHD_ERROR(("\n"));
++				}
++				DHD_ERROR(("\n"));
++			}
++#endif /* DHD_RX_FULL_DUMP */
++		}
++#endif /* DHD_RX_DUMP */
++
++		skb->protocol = eth_type_trans(skb, skb->dev);
++
++		if (skb->pkt_type == PACKET_MULTICAST) {
++			dhd->pub.rx_multicast++;
++			ifp->stats.multicast++;
++		}
++
++		skb->data = eth;
++		skb->len = len;
++
++#ifdef WLMEDIA_HTSF
++		dhd_htsf_addrxts(dhdp, pktbuf);
++#endif
++		/* Strip header, count, deliver upward */
++		skb_pull(skb, ETH_HLEN);
++
++		/* Process special event packets and then discard them */
++		memset(&event, 0, sizeof(event));
++		if (ntoh16(skb->protocol) == ETHER_TYPE_BRCM) {
++			dhd_wl_host_event(dhd, &ifidx,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
++			skb_mac_header(skb),
++#else
++			skb->mac.raw,
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22) */
++			&event,
++			&data);
++
++			wl_event_to_host_order(&event);
++			if (!tout_ctrl)
++				tout_ctrl = DHD_PACKET_TIMEOUT_MS;
++
++#if defined(PNO_SUPPORT)
++			if (event.event_type == WLC_E_PFN_NET_FOUND) {
++				/* enforce custom wake lock to garantee that Kernel not suspended */
++				tout_ctrl = CUSTOM_PNO_EVENT_LOCK_xTIME * DHD_PACKET_TIMEOUT_MS;
++			}
++#endif /* PNO_SUPPORT */
++			if (DHD_DBG_BCNRX_ON()) {
++				if (event.event_type == WLC_E_BCNRX_MSG) {
++					prhex("Received beacon packet:", data, event.datalen);
++				}
++			}
++
++			if (numpkt != 1) {
++				DHD_ERROR(("%s: Got BRCM event packet in a chained packet.\n",
++				__FUNCTION__));
++			}
++#ifdef DHD_DONOT_FORWARD_BCMEVENT_AS_NETWORK_PKT
++#ifdef DHD_USE_STATIC_CTRLBUF
++			PKTFREE_STATIC(dhdp->osh, pktbuf, FALSE);
++#else
++			PKTFREE(dhdp->osh, pktbuf, FALSE);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++			continue;
++#else
++			/*
++			 * For the event packets, there is a possibility
++			 * of ifidx getting modifed.Thus update the ifp
++			 * once again.
++			 */
++			ASSERT(ifidx < DHD_MAX_IFS && dhd->iflist[ifidx]);
++			ifp = dhd->iflist[ifidx];
++#ifndef PROP_TXSTATUS_VSDB
++			if (!(ifp && ifp->net && (ifp->net->reg_state == NETREG_REGISTERED))) {
++#else
++			if (!(ifp && ifp->net && (ifp->net->reg_state == NETREG_REGISTERED) &&
++				dhd->pub.up)) {
++#endif /* PROP_TXSTATUS_VSDB */
++				DHD_ERROR(("%s: net device is NOT registered. drop event packet\n",
++				__FUNCTION__));
++				PKTFREE(dhdp->osh, pktbuf, FALSE);
++				continue;
++			}
++#endif /* DHD_DONOT_FORWARD_BCMEVENT_AS_NETWORK_PKT */
++		} else {
++			tout_rx = DHD_PACKET_TIMEOUT_MS;
++
++#ifdef PROP_TXSTATUS
++			dhd_wlfc_save_rxpath_ac_time(dhdp, (uint8)PKTPRIO(skb));
++#endif /* PROP_TXSTATUS */
++		}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0))
++		/* It is useless for network stack any more, and we do not use it */
++		if (ifp->net)
++			ifp->net->last_rx = jiffies;
++#endif
++
++		if (ntoh16(skb->protocol) != ETHER_TYPE_BRCM) {
++			dhdp->dstats.rx_bytes += skb->len;
++			dhdp->rx_packets++; /* Local count */
++			ifp->stats.rx_bytes += skb->len;
++			ifp->stats.rx_packets++;
++		}
++
++		if (in_interrupt()) {
++			bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE,
++				__FUNCTION__, __LINE__);
++			DHD_PERIM_UNLOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++#if defined(DHD_LB) && defined(DHD_LB_RXP)
++			netif_receive_skb(skb);
++#else
++			netif_rx(skb);
++#endif /* !defined(DHD_LB) && !defined(DHD_LB_RXP) */
++			DHD_PERIM_LOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++		} else {
++			if (dhd->rxthread_enabled) {
++				if (!skbhead)
++					skbhead = skb;
++				else
++					PKTSETNEXT(dhdp->osh, skbprev, skb);
++				skbprev = skb;
++			} else {
++
++				/* If the receive is not processed inside an ISR,
++				 * the softirqd must be woken explicitly to service
++				 * the NET_RX_SOFTIRQ.	In 2.6 kernels, this is handled
++				 * by netif_rx_ni(), but in earlier kernels, we need
++				 * to do it manually.
++				 */
++				bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE,
++					__FUNCTION__, __LINE__);
++
++#if defined(DHD_LB) && defined(DHD_LB_RXP)
++				DHD_PERIM_UNLOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++				netif_receive_skb(skb);
++				DHD_PERIM_LOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++#else
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
++				DHD_PERIM_UNLOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++				netif_rx_ni(skb);
++				DHD_PERIM_LOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++#else
++				ulong flags;
++				DHD_PERIM_UNLOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++				netif_rx(skb);
++				DHD_PERIM_LOCK_ALL((dhd->fwder_unit % FWDER_MAX_UNIT));
++				local_irq_save(flags);
++				RAISE_RX_SOFTIRQ();
++				local_irq_restore(flags);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0) */
++#endif /* !defined(DHD_LB) && !defined(DHD_LB_RXP) */
++			}
++		}
++	}
++
++	if (dhd->rxthread_enabled && skbhead)
++		dhd_sched_rxf(dhdp, skbhead);
++
++	DHD_OS_WAKE_LOCK_RX_TIMEOUT_ENABLE(dhdp, tout_rx);
++	DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_ENABLE(dhdp, tout_ctrl);
++}
++
++void
++dhd_event(struct dhd_info *dhd, char *evpkt, int evlen, int ifidx)
++{
++	/* Linux version has nothing to do */
++	return;
++}
++
++void
++dhd_txcomplete(dhd_pub_t *dhdp, void *txp, bool success)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(dhdp->info);
++	struct ether_header *eh;
++	uint16 type;
++
++	dhd_prot_hdrpull(dhdp, NULL, txp, NULL, NULL);
++
++	eh = (struct ether_header *)PKTDATA(dhdp->osh, txp);
++	type  = ntoh16(eh->ether_type);
++
++	if ((type == ETHER_TYPE_802_1X) && (dhd_get_pend_8021x_cnt(dhd) > 0))
++		atomic_dec(&dhd->pend_8021x_cnt);
++
++#ifdef PROP_TXSTATUS
++	if (dhdp->wlfc_state && (dhdp->proptxstatus_mode != WLFC_FCMODE_NONE)) {
++		dhd_if_t *ifp = dhd->iflist[DHD_PKTTAG_IF(PKTTAG(txp))];
++		uint datalen  = PKTLEN(dhd->pub.osh, txp);
++		if (ifp != NULL) {
++			if (success) {
++				dhd->pub.tx_packets++;
++				ifp->stats.tx_packets++;
++				ifp->stats.tx_bytes += datalen;
++			} else {
++				ifp->stats.tx_dropped++;
++			}
++		}
++	}
++#endif
++}
++
++static struct net_device_stats *
++dhd_get_stats(struct net_device *net)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(net);
++	dhd_if_t *ifp;
++	int ifidx;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	ifidx = dhd_net2idx(dhd, net);
++	if (ifidx == DHD_BAD_IF) {
++		DHD_ERROR(("%s: BAD_IF\n", __FUNCTION__));
++
++		memset(&net->stats, 0, sizeof(net->stats));
++		return &net->stats;
++	}
++
++	ifp = dhd->iflist[ifidx];
++	ASSERT(dhd && ifp);
++
++	if (dhd->pub.up) {
++		/* Use the protocol to get dongle stats */
++		dhd_prot_dstats(&dhd->pub);
++	}
++	return &ifp->stats;
++}
++
++#ifndef BCMDBUS
++static int
++dhd_watchdog_thread(void *data)
++{
++	tsk_ctl_t *tsk = (tsk_ctl_t *)data;
++	dhd_info_t *dhd = (dhd_info_t *)tsk->parent;
++	/* This thread doesn't need any user-level access,
++	 * so get rid of all our resources
++	 */
++	if (dhd_watchdog_prio > 0) {
++		struct sched_param param;
++		param.sched_priority = (dhd_watchdog_prio < MAX_RT_PRIO)?
++			dhd_watchdog_prio:(MAX_RT_PRIO-1);
++		setScheduler(current, SCHED_FIFO, &param);
++	}
++
++	while (1) {
++		if (down_interruptible (&tsk->sema) == 0) {
++			unsigned long flags;
++			unsigned long jiffies_at_start = jiffies;
++			unsigned long time_lapse;
++
++			DHD_OS_WD_WAKE_LOCK(&dhd->pub);
++			SMP_RD_BARRIER_DEPENDS();
++			if (tsk->terminated) {
++				break;
++			}
++
++			if (dhd->pub.dongle_reset == FALSE) {
++				DHD_TIMER(("%s:\n", __FUNCTION__));
++				dhd_bus_watchdog(&dhd->pub);
++
++				DHD_GENERAL_LOCK(&dhd->pub, flags);
++				/* Count the tick for reference */
++				dhd->pub.tickcnt++;
++#ifdef DHD_L2_FILTER
++				dhd_l2_filter_watchdog(&dhd->pub);
++#endif /* DHD_L2_FILTER */
++				time_lapse = jiffies - jiffies_at_start;
++
++				/* Reschedule the watchdog */
++				if (dhd->wd_timer_valid) {
++					mod_timer(&dhd->timer,
++					    jiffies +
++					    msecs_to_jiffies(dhd_watchdog_ms) -
++					    min(msecs_to_jiffies(dhd_watchdog_ms), time_lapse));
++				}
++				DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++			}
++			DHD_OS_WD_WAKE_UNLOCK(&dhd->pub);
++		} else {
++			break;
++		}
++	}
++
++	complete_and_exit(&tsk->completed, 0);
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++static void dhd_watchdog(struct timer_list *t)
++{
++	dhd_info_t *dhd = from_timer(dhd, t, timer);
++#else
++static void dhd_watchdog(ulong data)
++{
++	dhd_info_t *dhd = (dhd_info_t *)data;
++#endif
++	unsigned long flags;
++
++	if (dhd->pub.dongle_reset) {
++		return;
++	}
++
++	if (dhd->pub.busstate == DHD_BUS_SUSPEND) {
++		DHD_ERROR(("%s wd while suspend in progress \n", __FUNCTION__));
++		return;
++	}
++
++	if (dhd->thr_wdt_ctl.thr_pid >= 0) {
++		up(&dhd->thr_wdt_ctl.sema);
++		return;
++	}
++
++	DHD_OS_WD_WAKE_LOCK(&dhd->pub);
++	/* Call the bus module watchdog */
++	dhd_bus_watchdog(&dhd->pub);
++
++	DHD_GENERAL_LOCK(&dhd->pub, flags);
++	/* Count the tick for reference */
++	dhd->pub.tickcnt++;
++
++#ifdef DHD_L2_FILTER
++	dhd_l2_filter_watchdog(&dhd->pub);
++#endif /* DHD_L2_FILTER */
++	/* Reschedule the watchdog */
++	if (dhd->wd_timer_valid)
++		mod_timer(&dhd->timer, jiffies + msecs_to_jiffies(dhd_watchdog_ms));
++	DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++	DHD_OS_WD_WAKE_UNLOCK(&dhd->pub);
++}
++
++#ifdef ENABLE_ADAPTIVE_SCHED
++static void
++dhd_sched_policy(int prio)
++{
++	struct sched_param param;
++	if (cpufreq_quick_get(0) <= CUSTOM_CPUFREQ_THRESH) {
++		param.sched_priority = 0;
++		setScheduler(current, SCHED_NORMAL, &param);
++	} else {
++		if (get_scheduler_policy(current) != SCHED_FIFO) {
++			param.sched_priority = (prio < MAX_RT_PRIO)? prio : (MAX_RT_PRIO-1);
++			setScheduler(current, SCHED_FIFO, &param);
++		}
++	}
++}
++#endif /* ENABLE_ADAPTIVE_SCHED */
++#ifdef DEBUG_CPU_FREQ
++static int dhd_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data)
++{
++	dhd_info_t *dhd = container_of(nb, struct dhd_info, freq_trans);
++	struct cpufreq_freqs *freq = data;
++	if (dhd) {
++		if (!dhd->new_freq)
++			goto exit;
++		if (val == CPUFREQ_POSTCHANGE) {
++			DHD_ERROR(("cpu freq is changed to %u kHZ on CPU %d\n",
++				freq->new, freq->cpu));
++			*per_cpu_ptr(dhd->new_freq, freq->cpu) = freq->new;
++		}
++	}
++exit:
++	return 0;
++}
++#endif /* DEBUG_CPU_FREQ */
++static int
++dhd_dpc_thread(void *data)
++{
++	tsk_ctl_t *tsk = (tsk_ctl_t *)data;
++	dhd_info_t *dhd = (dhd_info_t *)tsk->parent;
++
++	/* This thread doesn't need any user-level access,
++	 * so get rid of all our resources
++	 */
++	if (dhd_dpc_prio > 0)
++	{
++		struct sched_param param;
++		param.sched_priority = (dhd_dpc_prio < MAX_RT_PRIO)?dhd_dpc_prio:(MAX_RT_PRIO-1);
++		setScheduler(current, SCHED_FIFO, &param);
++	}
++
++#ifdef CUSTOM_DPC_CPUCORE
++	set_cpus_allowed_ptr(current, cpumask_of(CUSTOM_DPC_CPUCORE));
++#endif
++#ifdef CUSTOM_SET_CPUCORE
++	dhd->pub.current_dpc = current;
++#endif /* CUSTOM_SET_CPUCORE */
++	/* Run until signal received */
++	while (1) {
++		if (!binary_sema_down(tsk)) {
++#ifdef ENABLE_ADAPTIVE_SCHED
++			dhd_sched_policy(dhd_dpc_prio);
++#endif /* ENABLE_ADAPTIVE_SCHED */
++			SMP_RD_BARRIER_DEPENDS();
++			if (tsk->terminated) {
++				break;
++			}
++
++			/* Call bus dpc unless it indicated down (then clean stop) */
++			if (dhd->pub.busstate != DHD_BUS_DOWN) {
++/*
++ * Enable this to prevent CPU loading too high on some platforms
++ */
++#if defined(CUSTOMER_IPCAM)
++				int resched_cnt = 0;
++#endif 
++				dhd_os_wd_timer_extend(&dhd->pub, TRUE);
++				while (dhd_bus_dpc(dhd->pub.bus)) {
++					/* process all data */
++#if defined(CUSTOMER_IPCAM)
++					resched_cnt++;
++					if (resched_cnt > MAX_RESCHED_CNT) {
++						DHD_INFO(("%s Calling msleep to"
++							"let other processes run. \n",
++							__FUNCTION__));
++#ifndef CUSTOMER_IPCAM
++						dhd->pub.dhd_bug_on = true;
++#endif
++						resched_cnt = 0;
++						OSL_SLEEP(1);
++					}
++#endif 
++				}
++				dhd_os_wd_timer_extend(&dhd->pub, FALSE);
++				DHD_OS_WAKE_UNLOCK(&dhd->pub);
++
++			} else {
++				if (dhd->pub.up)
++					dhd_bus_stop(dhd->pub.bus, TRUE);
++				DHD_OS_WAKE_UNLOCK(&dhd->pub);
++			}
++		} else {
++			break;
++		}
++	}
++	complete_and_exit(&tsk->completed, 0);
++}
++
++static int
++dhd_rxf_thread(void *data)
++{
++	tsk_ctl_t *tsk = (tsk_ctl_t *)data;
++	dhd_info_t *dhd = (dhd_info_t *)tsk->parent;
++#if defined(WAIT_DEQUEUE)
++#define RXF_WATCHDOG_TIME 250 /* BARK_TIME(1000) /  */
++	ulong watchdogTime = OSL_SYSUPTIME(); /* msec */
++#endif
++	dhd_pub_t *pub = &dhd->pub;
++
++	/* This thread doesn't need any user-level access,
++	 * so get rid of all our resources
++	 */
++	if (dhd_rxf_prio > 0)
++	{
++		struct sched_param param;
++		param.sched_priority = (dhd_rxf_prio < MAX_RT_PRIO)?dhd_rxf_prio:(MAX_RT_PRIO-1);
++		setScheduler(current, SCHED_FIFO, &param);
++	}
++
++	DAEMONIZE("dhd_rxf");
++	/* DHD_OS_WAKE_LOCK is called in dhd_sched_dpc[dhd_linux.c] down below  */
++
++	/*  signal: thread has started */
++	complete(&tsk->completed);
++#ifdef CUSTOM_SET_CPUCORE
++	dhd->pub.current_rxf = current;
++#endif /* CUSTOM_SET_CPUCORE */
++	/* Run until signal received */
++	while (1) {
++		if (down_interruptible(&tsk->sema) == 0) {
++			void *skb;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)
++			ulong flags;
++#endif
++#ifdef ENABLE_ADAPTIVE_SCHED
++			dhd_sched_policy(dhd_rxf_prio);
++#endif /* ENABLE_ADAPTIVE_SCHED */
++
++			SMP_RD_BARRIER_DEPENDS();
++
++			if (tsk->terminated) {
++				break;
++			}
++			skb = dhd_rxf_dequeue(pub);
++
++			if (skb == NULL) {
++				continue;
++			}
++			while (skb) {
++				void *skbnext = PKTNEXT(pub->osh, skb);
++				PKTSETNEXT(pub->osh, skb, NULL);
++				bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE,
++					__FUNCTION__, __LINE__);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
++				netif_rx_ni(skb);
++#else
++				netif_rx(skb);
++				local_irq_save(flags);
++				RAISE_RX_SOFTIRQ();
++				local_irq_restore(flags);
++
++#endif
++				skb = skbnext;
++			}
++#if defined(WAIT_DEQUEUE)
++			if (OSL_SYSUPTIME() - watchdogTime > RXF_WATCHDOG_TIME) {
++				OSL_SLEEP(1);
++				watchdogTime = OSL_SYSUPTIME();
++			}
++#endif
++
++			DHD_OS_WAKE_UNLOCK(pub);
++		} else {
++			break;
++		}
++	}
++	complete_and_exit(&tsk->completed, 0);
++}
++
++#ifdef BCMPCIE
++void dhd_dpc_enable(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd;
++
++	if (!dhdp || !dhdp->info)
++		return;
++	dhd = dhdp->info;
++
++#ifdef DHD_LB
++#ifdef DHD_LB_RXP
++	__skb_queue_head_init(&dhd->rx_pend_queue);
++#endif /* DHD_LB_RXP */
++#ifdef DHD_LB_TXC
++	if (atomic_read(&dhd->tx_compl_tasklet.count) == 1)
++		tasklet_enable(&dhd->tx_compl_tasklet);
++#endif /* DHD_LB_TXC */
++#ifdef DHD_LB_RXC
++	if (atomic_read(&dhd->rx_compl_tasklet.count) == 1)
++		tasklet_enable(&dhd->rx_compl_tasklet);
++#endif /* DHD_LB_RXC */
++#endif /* DHD_LB */
++	if (atomic_read(&dhd->tasklet.count) ==  1)
++		tasklet_enable(&dhd->tasklet);
++}
++#endif /* BCMPCIE */
++
++
++#ifdef BCMPCIE
++void
++dhd_dpc_kill(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd;
++
++	if (!dhdp) {
++		return;
++	}
++
++	dhd = dhdp->info;
++
++	if (!dhd) {
++		return;
++	}
++
++	if (dhd->thr_dpc_ctl.thr_pid < 0) {
++		tasklet_disable(&dhd->tasklet);
++		tasklet_kill(&dhd->tasklet);
++		DHD_ERROR(("%s: tasklet disabled\n", __FUNCTION__));
++	}
++#if defined(DHD_LB)
++#ifdef DHD_LB_RXP
++	__skb_queue_purge(&dhd->rx_pend_queue);
++#endif /* DHD_LB_RXP */
++	/* Kill the Load Balancing Tasklets */
++#if defined(DHD_LB_TXC)
++	tasklet_disable(&dhd->tx_compl_tasklet);
++	tasklet_kill(&dhd->tx_compl_tasklet);
++#endif /* DHD_LB_TXC */
++#if defined(DHD_LB_RXC)
++	tasklet_disable(&dhd->rx_compl_tasklet);
++	tasklet_kill(&dhd->rx_compl_tasklet);
++#endif /* DHD_LB_RXC */
++#endif /* DHD_LB */
++}
++#endif /* BCMPCIE */
++
++static void
++dhd_dpc(ulong data)
++{
++	dhd_info_t *dhd;
++
++	dhd = (dhd_info_t *)data;
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++
++	/* this (tasklet) can be scheduled in dhd_sched_dpc[dhd_linux.c]
++	 * down below , wake lock is set,
++	 * the tasklet is initialized in dhd_attach()
++	 */
++	/* Call bus dpc unless it indicated down (then clean stop) */
++	if (dhd->pub.busstate != DHD_BUS_DOWN) {
++		if (dhd_bus_dpc(dhd->pub.bus)) {
++			DHD_LB_STATS_INCR(dhd->dhd_dpc_cnt);
++			tasklet_schedule(&dhd->tasklet);
++		}
++	} else {
++		dhd_bus_stop(dhd->pub.bus, TRUE);
++	}
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++}
++
++void
++dhd_sched_dpc(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++
++	if (dhd->thr_dpc_ctl.thr_pid >= 0) {
++		DHD_OS_WAKE_LOCK(dhdp);
++		/* If the semaphore does not get up,
++		* wake unlock should be done here
++		*/
++		if (!binary_sema_up(&dhd->thr_dpc_ctl)) {
++			DHD_OS_WAKE_UNLOCK(dhdp);
++		}
++		return;
++	} else {
++		if (!test_bit(TASKLET_STATE_SCHED, &dhd->tasklet.state)) {
++			DHD_OS_WAKE_LOCK(dhdp);
++		}
++		tasklet_schedule(&dhd->tasklet);
++		DHD_OS_WAKE_UNLOCK(dhdp);
++	}
++}
++#endif /* BCMDBUS */
++
++static void
++dhd_sched_rxf(dhd_pub_t *dhdp, void *skb)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++#ifdef RXF_DEQUEUE_ON_BUSY
++	int ret = BCME_OK;
++	int retry = 2;
++#endif /* RXF_DEQUEUE_ON_BUSY */
++
++	DHD_OS_WAKE_LOCK(dhdp);
++
++	DHD_TRACE(("dhd_sched_rxf: Enter\n"));
++#ifdef RXF_DEQUEUE_ON_BUSY
++	do {
++		ret = dhd_rxf_enqueue(dhdp, skb);
++		if (ret == BCME_OK || ret == BCME_ERROR)
++			break;
++		else
++			OSL_SLEEP(50); /* waiting for dequeueing */
++	} while (retry-- > 0);
++
++	if (retry <= 0 && ret == BCME_BUSY) {
++		void *skbp = skb;
++
++		while (skbp) {
++			void *skbnext = PKTNEXT(dhdp->osh, skbp);
++			PKTSETNEXT(dhdp->osh, skbp, NULL);
++			bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE,
++				__FUNCTION__, __LINE__);
++			netif_rx_ni(skbp);
++			skbp = skbnext;
++		}
++		DHD_ERROR(("send skb to kernel backlog without rxf_thread\n"));
++	} else {
++		if (dhd->thr_rxf_ctl.thr_pid >= 0) {
++			up(&dhd->thr_rxf_ctl.sema);
++		}
++	}
++#else /* RXF_DEQUEUE_ON_BUSY */
++	do {
++		if (dhd_rxf_enqueue(dhdp, skb) == BCME_OK)
++			break;
++	} while (1);
++	if (dhd->thr_rxf_ctl.thr_pid >= 0) {
++		up(&dhd->thr_rxf_ctl.sema);
++	}
++	return;
++#endif /* RXF_DEQUEUE_ON_BUSY */
++}
++
++#if defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW)
++#if defined(BCMDBUS)
++static int
++fw_download_thread_func(void *data)
++{
++	dhd_info_t *dhd = (dhd_info_t *)data;
++	int ret;
++
++	while (1) {
++		/* Wait for start trigger */
++		if (down_interruptible(&dhd->fw_download_lock) != 0)
++			return -ERESTARTSYS;
++
++		if (kthread_should_stop())
++			break;
++
++		DHD_TRACE(("%s: initiating firmware check and download\n", __FUNCTION__));
++		if (dbus_download_firmware(dhd->pub.dbus) == DBUS_OK) {
++			if ((ret = dbus_up(dhd->pub.dbus)) == 0) {
++#ifdef PROP_TXSTATUS
++				/* Need to deinitialise WLFC to allow re-initialisation later. */
++				dhd_wlfc_deinit(&dhd->pub);
++#endif /* PROP_TXSTATUS */
++				/* Resynchronise with the dongle. This also re-initialises WLFC. */
++				if ((ret = dhd_sync_with_dongle(&dhd->pub)) < 0) {
++					DHD_ERROR(("%s: failed with code %d\n", __FUNCTION__, ret));
++				}
++			}
++		}
++	}
++
++	return 0;
++}
++#endif /* BCMDBUS */
++#endif /* defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW) */
++
++#ifdef TOE
++/* Retrieve current toe component enables, which are kept as a bitmap in toe_ol iovar */
++static int
++dhd_toe_get(dhd_info_t *dhd, int ifidx, uint32 *toe_ol)
++{
++	char buf[32];
++	int ret;
++
++	ret = dhd_iovar(&dhd->pub, ifidx, "toe_ol", NULL, 0, (char *)&buf, sizeof(buf), FALSE);
++
++	if (ret < 0) {
++		if (ret == -EIO) {
++			DHD_ERROR(("%s: toe not supported by device\n", dhd_ifname(&dhd->pub,
++				ifidx)));
++			return -EOPNOTSUPP;
++		}
++
++		DHD_INFO(("%s: could not get toe_ol: ret=%d\n", dhd_ifname(&dhd->pub, ifidx), ret));
++		return ret;
++	}
++
++	memcpy(toe_ol, buf, sizeof(uint32));
++	return 0;
++}
++
++/* Set current toe component enables in toe_ol iovar, and set toe global enable iovar */
++static int
++dhd_toe_set(dhd_info_t *dhd, int ifidx, uint32 toe_ol)
++{
++	int toe, ret;
++
++	/* Set toe_ol as requested */
++	ret = dhd_iovar(&dhd->pub, ifidx, "toe_ol", (char *)&toe_ol, sizeof(toe_ol), NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: could not set toe_ol: ret=%d\n",
++			dhd_ifname(&dhd->pub, ifidx), ret));
++		return ret;
++	}
++
++	/* Enable toe globally only if any components are enabled. */
++	toe = (toe_ol != 0);
++	ret = dhd_iovar(&dhd->pub, ifidx, "toe", (char *)&toe, sizeof(toe), NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: could not set toe: ret=%d\n", dhd_ifname(&dhd->pub, ifidx), ret));
++		return ret;
++	}
++
++	return 0;
++}
++#endif /* TOE */
++
++#if defined(WL_CFG80211) && defined(NUM_SCB_MAX_PROBE)
++void dhd_set_scb_probe(dhd_pub_t *dhd)
++{
++	wl_scb_probe_t scb_probe;
++	char iovbuf[WL_EVENTING_MASK_LEN + sizeof(wl_scb_probe_t)];
++	int ret;
++
++	if (dhd->op_mode & DHD_FLAG_HOSTAP_MODE) {
++		return;
++	}
++
++	ret = dhd_iovar(dhd, 0, "scb_probe", NULL, 0, iovbuf, sizeof(iovbuf), FALSE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: GET max_scb_probe failed\n", __FUNCTION__));
++	}
++
++	memcpy(&scb_probe, iovbuf, sizeof(wl_scb_probe_t));
++
++	scb_probe.scb_max_probe = NUM_SCB_MAX_PROBE;
++
++	ret = dhd_iovar(dhd, 0, "scb_probe", (char *)&scb_probe, sizeof(wl_scb_probe_t), NULL, 0,
++			TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: max_scb_probe setting failed\n", __FUNCTION__));
++		return;
++	}
++}
++#endif /* WL_CFG80211 && NUM_SCB_MAX_PROBE */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
++static void
++dhd_ethtool_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *info)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(net);
++
++	snprintf(info->driver, sizeof(info->driver), "wl");
++	snprintf(info->version, sizeof(info->version), "%lu", dhd->pub.drv_version);
++}
++
++struct ethtool_ops dhd_ethtool_ops = {
++	.get_drvinfo = dhd_ethtool_get_drvinfo
++};
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24) */
++
++
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 4, 2)
++static int
++dhd_ethtool(dhd_info_t *dhd, void *uaddr)
++{
++	struct ethtool_drvinfo info;
++	char drvname[sizeof(info.driver)];
++	uint32 cmd;
++#ifdef TOE
++	struct ethtool_value edata;
++	uint32 toe_cmpnt, csum_dir;
++	int ret;
++#endif
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	/* all ethtool calls start with a cmd word */
++	if (copy_from_user(&cmd, uaddr, sizeof (uint32)))
++		return -EFAULT;
++
++	switch (cmd) {
++	case ETHTOOL_GDRVINFO:
++		/* Copy out any request driver name */
++		if (copy_from_user(&info, uaddr, sizeof(info)))
++			return -EFAULT;
++		strncpy(drvname, info.driver, sizeof(info.driver));
++		drvname[sizeof(info.driver)-1] = '\0';
++
++		/* clear struct for return */
++		memset(&info, 0, sizeof(info));
++		info.cmd = cmd;
++
++		/* if dhd requested, identify ourselves */
++		if (strcmp(drvname, "?dhd") == 0) {
++			snprintf(info.driver, sizeof(info.driver), "dhd");
++			strncpy(info.version, EPI_VERSION_STR, sizeof(info.version) - 1);
++			info.version[sizeof(info.version) - 1] = '\0';
++		}
++
++		/* otherwise, require dongle to be up */
++		else if (!dhd->pub.up) {
++			DHD_ERROR(("%s: dongle is not up\n", __FUNCTION__));
++			return -ENODEV;
++		}
++
++		/* finally, report dongle driver type */
++		else if (dhd->pub.iswl)
++			snprintf(info.driver, sizeof(info.driver), "wl");
++		else
++			snprintf(info.driver, sizeof(info.driver), "xx");
++
++		snprintf(info.version, sizeof(info.version), "%lu", dhd->pub.drv_version);
++		if (copy_to_user(uaddr, &info, sizeof(info)))
++			return -EFAULT;
++		DHD_CTL(("%s: given %*s, returning %s\n", __FUNCTION__,
++		         (int)sizeof(drvname), drvname, info.driver));
++		break;
++
++#ifdef TOE
++	/* Get toe offload components from dongle */
++	case ETHTOOL_GRXCSUM:
++	case ETHTOOL_GTXCSUM:
++		if ((ret = dhd_toe_get(dhd, 0, &toe_cmpnt)) < 0)
++			return ret;
++
++		csum_dir = (cmd == ETHTOOL_GTXCSUM) ? TOE_TX_CSUM_OL : TOE_RX_CSUM_OL;
++
++		edata.cmd = cmd;
++		edata.data = (toe_cmpnt & csum_dir) ? 1 : 0;
++
++		if (copy_to_user(uaddr, &edata, sizeof(edata)))
++			return -EFAULT;
++		break;
++
++	/* Set toe offload components in dongle */
++	case ETHTOOL_SRXCSUM:
++	case ETHTOOL_STXCSUM:
++		if (copy_from_user(&edata, uaddr, sizeof(edata)))
++			return -EFAULT;
++
++		/* Read the current settings, update and write back */
++		if ((ret = dhd_toe_get(dhd, 0, &toe_cmpnt)) < 0)
++			return ret;
++
++		csum_dir = (cmd == ETHTOOL_STXCSUM) ? TOE_TX_CSUM_OL : TOE_RX_CSUM_OL;
++
++		if (edata.data != 0)
++			toe_cmpnt |= csum_dir;
++		else
++			toe_cmpnt &= ~csum_dir;
++
++		if ((ret = dhd_toe_set(dhd, 0, toe_cmpnt)) < 0)
++			return ret;
++
++		/* If setting TX checksum mode, tell Linux the new mode */
++		if (cmd == ETHTOOL_STXCSUM) {
++			if (edata.data)
++				dhd->iflist[0]->net->features |= NETIF_F_IP_CSUM;
++			else
++				dhd->iflist[0]->net->features &= ~NETIF_F_IP_CSUM;
++		}
++
++		break;
++#endif /* TOE */
++
++	default:
++		return -EOPNOTSUPP;
++	}
++
++	return 0;
++}
++#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 4, 2) */
++
++static bool dhd_check_hang(struct net_device *net, dhd_pub_t *dhdp, int error)
++{
++	dhd_info_t *dhd;
++#ifdef DHD_FW_COREDUMP
++	int dump_len = 0;
++#endif /* DHD_FW_COREDUMP */
++
++	if (!dhdp) {
++		DHD_ERROR(("%s: dhdp is NULL\n", __FUNCTION__));
++		return FALSE;
++	}
++
++	if (!dhdp->up)
++		return FALSE;
++
++	dhd = (dhd_info_t *)dhdp->info;
++#if (!defined(BCMDBUS) && !defined(BCMPCIE))
++	if (dhd->thr_dpc_ctl.thr_pid < 0) {
++		DHD_ERROR(("%s : skipped due to negative pid - unloading?\n", __FUNCTION__));
++		return FALSE;
++	}
++#endif /* BCMDBUS */
++#ifdef DHD_FW_COREDUMP
++	if (error == -ETIMEDOUT && dhdp->busstate != DHD_BUS_DOWN) {
++		if (dhd_os_socram_dump(net, &dump_len) == BCME_OK) {
++			dhd_dbg_send_urgent_evt(dhdp, NULL, 0);
++		}
++	}
++#endif /* DHD_FW_COREDUMP */
++	if ((error == -ETIMEDOUT) || (error == -EREMOTEIO) ||
++		((dhdp->busstate == DHD_BUS_DOWN) && (!dhdp->dongle_reset))) {
++#ifdef BCMPCIE
++		DHD_ERROR(("%s: Event HANG send up due to  re=%d te=%d d3acke=%d e=%d s=%d\n",
++			__FUNCTION__, dhdp->rxcnt_timeout, dhdp->txcnt_timeout,
++			dhdp->d3ackcnt_timeout, error, dhdp->busstate));
++#else
++		DHD_ERROR(("%s: Event HANG send up due to  re=%d te=%d e=%d s=%d\n", __FUNCTION__,
++			dhdp->rxcnt_timeout, dhdp->txcnt_timeout, error, dhdp->busstate));
++#endif /* BCMPCIE */
++		net_os_send_hang_message(net);
++		return TRUE;
++	}
++	return FALSE;
++}
++
++int dhd_ioctl_process(dhd_pub_t *pub, int ifidx, dhd_ioctl_t *ioc, void *data_buf)
++{
++	int bcmerror = BCME_OK;
++	int buflen = 0;
++	struct net_device *net;
++
++	net = dhd_idx2net(pub, ifidx);
++	if (!net) {
++		bcmerror = BCME_BADARG;
++		goto done;
++	}
++
++	if (data_buf)
++		buflen = MIN(ioc->len, DHD_IOCTL_MAXLEN);
++
++	/* check for local dhd ioctl and handle it */
++	if (ioc->driver == DHD_IOCTL_MAGIC) {
++		bcmerror = dhd_ioctl((void *)pub, ioc, data_buf, buflen);
++		if (bcmerror)
++			pub->bcmerror = bcmerror;
++		goto done;
++	}
++
++#ifndef BCMDBUS
++	/* send to dongle (must be up, and wl). */
++	if (pub->busstate == DHD_BUS_DOWN || pub->busstate == DHD_BUS_LOAD) {
++		if (allow_delay_fwdl) {
++			int ret = dhd_bus_start(pub);
++			if (ret != 0) {
++				DHD_ERROR(("%s: failed with code %d\n", __FUNCTION__, ret));
++				bcmerror = BCME_DONGLE_DOWN;
++				goto done;
++			}
++		} else {
++			bcmerror = BCME_DONGLE_DOWN;
++			goto done;
++		}
++	}
++
++	if (!pub->iswl) {
++		bcmerror = BCME_DONGLE_DOWN;
++		goto done;
++	}
++#endif /* BCMDBUS */
++
++	/*
++	 * Flush the TX queue if required for proper message serialization:
++	 * Intercept WLC_SET_KEY IOCTL - serialize M4 send and set key IOCTL to
++	 * prevent M4 encryption and
++	 * intercept WLC_DISASSOC IOCTL - serialize WPS-DONE and WLC_DISASSOC IOCTL to
++	 * prevent disassoc frame being sent before WPS-DONE frame.
++	 */
++	if (ioc->cmd == WLC_SET_KEY ||
++	    (ioc->cmd == WLC_SET_VAR && data_buf != NULL &&
++	     strncmp("wsec_key", data_buf, 9) == 0) ||
++	    (ioc->cmd == WLC_SET_VAR && data_buf != NULL &&
++	     strncmp("bsscfg:wsec_key", data_buf, 15) == 0) ||
++	    ioc->cmd == WLC_DISASSOC)
++		dhd_wait_pend8021x(net);
++
++#ifdef WLMEDIA_HTSF
++	if (data_buf) {
++		/*  short cut wl ioctl calls here  */
++		if (strcmp("htsf", data_buf) == 0) {
++			dhd_ioctl_htsf_get(dhd, 0);
++			return BCME_OK;
++		}
++
++		if (strcmp("htsflate", data_buf) == 0) {
++			if (ioc->set) {
++				memset(ts, 0, sizeof(tstamp_t)*TSMAX);
++				memset(&maxdelayts, 0, sizeof(tstamp_t));
++				maxdelay = 0;
++				tspktcnt = 0;
++				maxdelaypktno = 0;
++				memset(&vi_d1.bin, 0, sizeof(uint32)*NUMBIN);
++				memset(&vi_d2.bin, 0, sizeof(uint32)*NUMBIN);
++				memset(&vi_d3.bin, 0, sizeof(uint32)*NUMBIN);
++				memset(&vi_d4.bin, 0, sizeof(uint32)*NUMBIN);
++			} else {
++				dhd_dump_latency();
++			}
++			return BCME_OK;
++		}
++		if (strcmp("htsfclear", data_buf) == 0) {
++			memset(&vi_d1.bin, 0, sizeof(uint32)*NUMBIN);
++			memset(&vi_d2.bin, 0, sizeof(uint32)*NUMBIN);
++			memset(&vi_d3.bin, 0, sizeof(uint32)*NUMBIN);
++			memset(&vi_d4.bin, 0, sizeof(uint32)*NUMBIN);
++			htsf_seqnum = 0;
++			return BCME_OK;
++		}
++		if (strcmp("htsfhis", data_buf) == 0) {
++			dhd_dump_htsfhisto(&vi_d1, "H to D");
++			dhd_dump_htsfhisto(&vi_d2, "D to D");
++			dhd_dump_htsfhisto(&vi_d3, "D to H");
++			dhd_dump_htsfhisto(&vi_d4, "H to H");
++			return BCME_OK;
++		}
++		if (strcmp("tsport", data_buf) == 0) {
++			if (ioc->set) {
++				memcpy(&tsport, data_buf + 7, 4);
++			} else {
++				DHD_ERROR(("current timestamp port: %d \n", tsport));
++			}
++			return BCME_OK;
++		}
++	}
++#endif /* WLMEDIA_HTSF */
++
++	if ((ioc->cmd == WLC_SET_VAR || ioc->cmd == WLC_GET_VAR) &&
++		data_buf != NULL && strncmp("rpc_", data_buf, 4) == 0) {
++#ifdef BCM_FD_AGGR
++		bcmerror = dhd_fdaggr_ioctl(pub, ifidx, (wl_ioctl_t *)ioc, data_buf, buflen);
++#else
++		bcmerror = BCME_UNSUPPORTED;
++#endif
++		goto done;
++	}
++	bcmerror = dhd_wl_ioctl(pub, ifidx, (wl_ioctl_t *)ioc, data_buf, buflen);
++
++	/* Intercept monitor ioctl here, add/del monitor if */
++	if (bcmerror == BCME_OK && ioc->cmd == WLC_SET_MONITOR) {
++		dhd_set_monitor(pub, ifidx, *(int32*)data_buf);
++	}
++
++done:
++	dhd_check_hang(net, pub, bcmerror);
++
++	return bcmerror;
++}
++
++static int
++dhd_ioctl_entry(struct net_device *net, struct ifreq *ifr, int cmd)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(net);
++	dhd_ioctl_t ioc;
++	int ifidx;
++	int ret;
++	void *local_buf = NULL;
++	u16 buflen = 0;
++
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK(&dhd->pub);
++
++	/* Interface up check for built-in type */
++	if (!dhd_download_fw_on_driverload && dhd->pub.up == FALSE) {
++		DHD_TRACE(("%s: Interface is down \n", __FUNCTION__));
++		ret = BCME_NOTUP;
++		goto exit;
++	}
++
++	/* send to dongle only if we are not waiting for reload already */
++	if (dhd->pub.hang_was_sent) {
++		DHD_TRACE(("%s: HANG was sent up earlier\n", __FUNCTION__));
++		DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_ENABLE(&dhd->pub, DHD_EVENT_TIMEOUT_MS);
++		ret = BCME_DONGLE_DOWN;
++		goto exit;
++	}
++
++	ifidx = dhd_net2idx(dhd, net);
++	DHD_TRACE(("%s: ifidx %d, cmd 0x%04x\n", __FUNCTION__, ifidx, cmd));
++
++	if (ifidx == DHD_BAD_IF) {
++		DHD_ERROR(("%s: BAD IF\n", __FUNCTION__));
++		ret = -1;
++		goto exit;
++	}
++
++#if defined(WL_WIRELESS_EXT)
++	/* linux wireless extensions */
++	if ((cmd >= SIOCIWFIRST) && (cmd <= SIOCIWLAST)) {
++		/* may recurse, do NOT lock */
++		ret = wl_iw_ioctl(net, ifr, cmd);
++		goto exit;
++	}
++#endif /* defined(WL_WIRELESS_EXT) */
++
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 4, 2)
++	if (cmd == SIOCETHTOOL) {
++		ret = dhd_ethtool(dhd, (void*)ifr->ifr_data);
++		goto exit;
++	}
++#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 4, 2) */
++
++	if (cmd == SIOCDEVPRIVATE+1) {
++		ret = wl_android_priv_cmd(net, ifr, cmd);
++		dhd_check_hang(net, &dhd->pub, ret);
++		goto exit;
++	}
++
++	if (cmd != SIOCDEVPRIVATE) {
++		ret = -EOPNOTSUPP;
++		goto exit;
++	}
++
++	memset(&ioc, 0, sizeof(ioc));
++
++#ifdef CONFIG_COMPAT
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
++	if (in_compat_syscall()) {
++#else
++	if (is_compat_task()) {
++#endif
++		compat_wl_ioctl_t compat_ioc;
++		if (copy_from_user(&compat_ioc, ifr->ifr_data, sizeof(compat_wl_ioctl_t))) {
++			ret = BCME_BADADDR;
++			goto done;
++		}
++		ioc.cmd = compat_ioc.cmd;
++		ioc.buf = compat_ptr(compat_ioc.buf);
++		ioc.len = compat_ioc.len;
++		ioc.set = compat_ioc.set;
++		ioc.used = compat_ioc.used;
++		ioc.needed = compat_ioc.needed;
++		/* To differentiate between wl and dhd read 4 more byes */
++		if ((copy_from_user(&ioc.driver, (char *)ifr->ifr_data + sizeof(compat_wl_ioctl_t),
++			sizeof(uint)) != 0)) {
++			ret = BCME_BADADDR;
++			goto done;
++		}
++	} else
++#endif /* CONFIG_COMPAT */
++	{
++		/* Copy the ioc control structure part of ioctl request */
++		if (copy_from_user(&ioc, ifr->ifr_data, sizeof(wl_ioctl_t))) {
++			ret = BCME_BADADDR;
++			goto done;
++		}
++
++		/* To differentiate between wl and dhd read 4 more byes */
++		if ((copy_from_user(&ioc.driver, (char *)ifr->ifr_data + sizeof(wl_ioctl_t),
++			sizeof(uint)) != 0)) {
++			ret = BCME_BADADDR;
++			goto done;
++		}
++	}
++
++	if (!capable(CAP_NET_ADMIN)) {
++		ret = BCME_EPERM;
++		goto done;
++	}
++
++	if (ioc.len > 0) {
++		buflen = MIN(ioc.len, DHD_IOCTL_MAXLEN);
++		if (!(local_buf = MALLOC(dhd->pub.osh, buflen+1))) {
++			ret = BCME_NOMEM;
++			goto done;
++		}
++
++		DHD_PERIM_UNLOCK(&dhd->pub);
++		if (copy_from_user(local_buf, ioc.buf, buflen)) {
++			DHD_PERIM_LOCK(&dhd->pub);
++			ret = BCME_BADADDR;
++			goto done;
++		}
++		DHD_PERIM_LOCK(&dhd->pub);
++
++		*(char *)(local_buf + buflen) = '\0';
++	}
++
++	ret = dhd_ioctl_process(&dhd->pub, ifidx, &ioc, local_buf);
++
++	if (!ret && buflen && local_buf && ioc.buf) {
++		DHD_PERIM_UNLOCK(&dhd->pub);
++		if (copy_to_user(ioc.buf, local_buf, buflen))
++			ret = -EFAULT;
++		DHD_PERIM_LOCK(&dhd->pub);
++	}
++
++done:
++	if (local_buf)
++		MFREE(dhd->pub.osh, local_buf, buflen+1);
++
++exit:
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++
++	return OSL_ERROR(ret);
++}
++
++
++
++static int
++dhd_stop(struct net_device *net)
++{
++	int ifidx = 0;
++	dhd_info_t *dhd = DHD_DEV_INFO(net);
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK(&dhd->pub);
++	DHD_TRACE(("%s: Enter %p\n", __FUNCTION__, net));
++	dhd->pub.rxcnt_timeout = 0;
++	dhd->pub.txcnt_timeout = 0;
++
++#ifdef BCMPCIE
++	dhd->pub.d3ackcnt_timeout = 0;
++#endif /* BCMPCIE */
++
++	if (dhd->pub.up == 0) {
++		goto exit;
++	}
++
++	dhd_if_flush_sta(DHD_DEV_IFP(net));
++
++
++	ifidx = dhd_net2idx(dhd, net);
++	BCM_REFERENCE(ifidx);
++
++	/* Set state and stop OS transmissions */
++	netif_stop_queue(net);
++	dhd->pub.up = 0;
++
++#ifdef WL_CFG80211
++	if (ifidx == 0) {
++		dhd_if_t *ifp;
++		wl_cfg80211_down(NULL);
++
++		ifp = dhd->iflist[0];
++		ASSERT(ifp && ifp->net);
++		/*
++		 * For CFG80211: Clean up all the left over virtual interfaces
++		 * when the primary Interface is brought down. [ifconfig wlan0 down]
++		 */
++		if (!dhd_download_fw_on_driverload) {
++			if ((dhd->dhd_state & DHD_ATTACH_STATE_ADD_IF) &&
++				(dhd->dhd_state & DHD_ATTACH_STATE_CFG80211)) {
++				int i;
++
++#ifdef WL_CFG80211_P2P_DEV_IF
++				wl_cfg80211_del_p2p_wdev();
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++				dhd_net_if_lock_local(dhd);
++				for (i = 1; i < DHD_MAX_IFS; i++)
++					dhd_remove_if(&dhd->pub, i, FALSE);
++
++				if (ifp && ifp->net) {
++					dhd_if_del_sta_list(ifp);
++				}
++
++#ifdef ARP_OFFLOAD_SUPPORT
++				if (dhd_inetaddr_notifier_registered) {
++					dhd_inetaddr_notifier_registered = FALSE;
++					unregister_inetaddr_notifier(&dhd_inetaddr_notifier);
++				}
++#endif /* ARP_OFFLOAD_SUPPORT */
++#if defined(CONFIG_IPV6)
++				if (dhd_inet6addr_notifier_registered) {
++					dhd_inet6addr_notifier_registered = FALSE;
++					unregister_inet6addr_notifier(&dhd_inet6addr_notifier);
++				}
++#endif /* OEM_ANDROID && CONFIG_IPV6 */
++				dhd_net_if_unlock_local(dhd);
++			}
++			cancel_work_sync(dhd->dhd_deferred_wq);
++#if defined(DHD_LB) && defined(DHD_LB_RXP)
++			__skb_queue_purge(&dhd->rx_pend_queue);
++#endif /* DHD_LB && DHD_LB_RXP */
++		}
++
++#if defined(BCMPCIE) && defined(DHDTCPACK_SUPPRESS)
++		dhd_tcpack_suppress_set(&dhd->pub, TCPACK_SUP_OFF);
++#endif /* BCMPCIE && DHDTCPACK_SUPPRESS */
++#if defined(DHD_LB) && defined(DHD_LB_RXP)
++		if (ifp->net == dhd->rx_napi_netdev) {
++			DHD_INFO(("%s napi<%p> disabled ifp->net<%p,%s>\n",
++				__FUNCTION__, &dhd->rx_napi_struct, net, net->name));
++			skb_queue_purge(&dhd->rx_napi_queue);
++			napi_disable(&dhd->rx_napi_struct);
++			netif_napi_del(&dhd->rx_napi_struct);
++			dhd->rx_napi_netdev = NULL;
++		}
++#endif /* DHD_LB && DHD_LB_RXP */
++
++	}
++#endif /* WL_CFG80211 */
++
++#ifdef PROP_TXSTATUS
++	dhd_wlfc_cleanup(&dhd->pub, NULL, 0);
++#endif
++	/* Stop the protocol module */
++	dhd_prot_stop(&dhd->pub);
++
++	OLD_MOD_DEC_USE_COUNT;
++exit:
++#if defined(WL_CFG80211)
++	if (ifidx == 0 && !dhd_download_fw_on_driverload)
++			wl_android_wifi_off(net, TRUE);
++#endif 
++	dhd->pub.hang_was_sent = 0;
++
++	/* Clear country spec for for built-in type driver */
++	if (!dhd_download_fw_on_driverload) {
++		dhd->pub.dhd_cspec.country_abbrev[0] = 0x00;
++		dhd->pub.dhd_cspec.rev = 0;
++		dhd->pub.dhd_cspec.ccode[0] = 0x00;
++	}
++
++#ifdef BCMDBGFS
++	dhd_dbg_remove();
++#endif
++
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++	return 0;
++}
++
++#if defined(WL_CFG80211) && defined(USE_INITIAL_SHORT_DWELL_TIME)
++extern bool g_first_broadcast_scan;
++#endif 
++
++#ifdef WL11U
++static int dhd_interworking_enable(dhd_pub_t *dhd)
++{
++	uint32 enable = true;
++	int ret = BCME_OK;
++
++	ret = dhd_iovar(dhd, 0, "interworking", (char *)&enable, sizeof(enable), NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: enableing interworking failed, ret=%d\n", __FUNCTION__, ret));
++	}
++
++	if (ret == BCME_OK) {
++		/* basic capabilities for HS20 REL2 */
++		uint32 cap = WL_WNM_BSSTRANS | WL_WNM_NOTIF;
++		ret = dhd_iovar(dhd, 0, "wnm", (char *)&cap, sizeof(cap), NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s: failed to set WNM info, ret=%d\n", __FUNCTION__, ret));
++		}
++	}
++
++	return ret;
++}
++#endif /* WL11u */
++
++static int
++dhd_open(struct net_device *net)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(net);
++#ifdef TOE
++	uint32 toe_ol;
++#endif
++#ifdef BCM_FD_AGGR
++	char iovbuf[WLC_IOCTL_SMLEN];
++	dbus_config_t config;
++	uint32 agglimit = 0;
++	uint32 rpc_agg = BCM_RPC_TP_DNGL_AGG_DPC; /* host aggr not enabled yet */
++#endif /* BCM_FD_AGGR */
++	int ifidx;
++	int32 ret = 0;
++
++	if (!dhd_download_fw_on_driverload && !dhd_driver_init_done) {
++		DHD_ERROR(("%s: WLAN driver is not initialized\n", __FUNCTION__));
++		return -1;
++	}
++
++
++
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK(&dhd->pub);
++	dhd->pub.dongle_trap_occured = 0;
++	dhd->pub.hang_was_sent = 0;
++#ifdef DHD_LOSSLESS_ROAMING
++	dhd->pub.dequeue_prec_map = ALLPRIO;
++#endif
++#if !defined(WL_CFG80211)
++	/*
++	 * Force start if ifconfig_up gets called before START command
++	 *  We keep WEXT's wl_control_wl_start to provide backward compatibility
++	 *  This should be removed in the future
++	 */
++	ret = wl_control_wl_start(net);
++	if (ret != 0) {
++		DHD_ERROR(("%s: failed with code %d\n", __FUNCTION__, ret));
++		ret = -1;
++		goto exit;
++	}
++
++#endif 
++
++	ifidx = dhd_net2idx(dhd, net);
++	DHD_TRACE(("%s: ifidx %d\n", __FUNCTION__, ifidx));
++
++	if (ifidx < 0) {
++		DHD_ERROR(("%s: Error: called with invalid IF\n", __FUNCTION__));
++		ret = -1;
++		goto exit;
++	}
++
++	if (!dhd->iflist[ifidx]) {
++		DHD_ERROR(("%s: Error: called when IF already deleted\n", __FUNCTION__));
++		ret = -1;
++		goto exit;
++	}
++
++	if (ifidx == 0) {
++		atomic_set(&dhd->pend_8021x_cnt, 0);
++#if defined(WL_CFG80211)
++		if (!dhd_download_fw_on_driverload) {
++			DHD_ERROR(("\n%s\n", dhd_version));
++#if defined(USE_INITIAL_SHORT_DWELL_TIME)
++			g_first_broadcast_scan = TRUE;
++#endif 
++			ret = wl_android_wifi_on(net);
++			if (ret != 0) {
++				DHD_ERROR(("%s : wl_android_wifi_on failed (%d)\n",
++					__FUNCTION__, ret));
++				ret = -1;
++				goto exit;
++			}
++		}
++#endif 
++
++		if (dhd->pub.busstate != DHD_BUS_DATA) {
++
++#ifndef BCMDBUS
++			/* try to bring up bus */
++			DHD_PERIM_UNLOCK(&dhd->pub);
++			ret = dhd_bus_start(&dhd->pub);
++			DHD_PERIM_LOCK(&dhd->pub);
++			if (ret) {
++				DHD_ERROR(("%s: failed with code %d\n", __FUNCTION__, ret));
++				ret = -1;
++				goto exit;
++			}
++#else /* BCMDBUS */
++			if ((ret = dbus_up(dhd->pub.dbus)) != 0) {
++				goto exit;
++			} else {
++				dhd->pub.busstate = DHD_BUS_DATA;
++			}
++
++			if ((ret = dhd_sync_with_dongle(&dhd->pub)) < 0) {
++				DHD_ERROR(("%s: failed with code %d\n", __FUNCTION__, ret));
++				goto exit;
++			}
++#endif /* BCMDBUS */
++
++		}
++
++#ifdef BCM_FD_AGGR
++		config.config_id = DBUS_CONFIG_ID_AGGR_LIMIT;
++
++
++		memset(iovbuf, 0, sizeof(iovbuf));
++		if (!dhd_iovar(&dhd->pub, ifidx, "rpc_dngl_agglimit", NULL, 0,
++				(char *)iovbuf, sizeof(iovbuf), FALSE)) {
++			agglimit = *(uint32 *)iovbuf;
++			config.aggr_param.maxrxsf = agglimit >> BCM_RPC_TP_AGG_SF_SHIFT;
++			config.aggr_param.maxrxsize = agglimit & BCM_RPC_TP_AGG_BYTES_MASK;
++			DHD_ERROR(("rpc_dngl_agglimit %x : sf_limit %d bytes_limit %d\n",
++				agglimit, config.aggr_param.maxrxsf, config.aggr_param.maxrxsize));
++			if (bcm_rpc_tp_set_config(dhd->pub.info->rpc_th, &config)) {
++				DHD_ERROR(("set tx/rx queue size and buffersize failed\n"));
++			}
++		} else {
++			DHD_ERROR(("get rpc_dngl_agglimit failed\n"));
++			rpc_agg &= ~BCM_RPC_TP_DNGL_AGG_DPC;
++		}
++
++		/* Set aggregation for TX */
++		bcm_rpc_tp_agg_set(dhd->pub.info->rpc_th, BCM_RPC_TP_HOST_AGG_MASK,
++			rpc_agg & BCM_RPC_TP_HOST_AGG_MASK);
++
++		/* Set aggregation for RX */
++		if (!dhd_iovar(&dhd->pub, ifidx, "rpc_agg", (char *)&rpc_agg, sizeof(rpc_agg),
++				NULL, 0, TRUE)) {
++			dhd->pub.info->fdaggr = 0;
++			if (rpc_agg & BCM_RPC_TP_HOST_AGG_MASK)
++				dhd->pub.info->fdaggr |= BCM_FDAGGR_H2D_ENABLED;
++			if (rpc_agg & BCM_RPC_TP_DNGL_AGG_MASK)
++				dhd->pub.info->fdaggr |= BCM_FDAGGR_D2H_ENABLED;
++		} else {
++			DHD_ERROR(("%s(): Setting RX aggregation failed %d\n", __FUNCTION__, ret));
++		}
++#endif /* BCM_FD_AGGR */
++
++		/* dhd_sync_with_dongle has been called in dhd_bus_start or wl_android_wifi_on */
++		memcpy(net->dev_addr, dhd->pub.mac.octet, ETHER_ADDR_LEN);
++
++#ifdef TOE
++		/* Get current TOE mode from dongle */
++		if (dhd_toe_get(dhd, ifidx, &toe_ol) >= 0 && (toe_ol & TOE_TX_CSUM_OL) != 0) {
++			dhd->iflist[ifidx]->net->features |= NETIF_F_IP_CSUM;
++		} else {
++			dhd->iflist[ifidx]->net->features &= ~NETIF_F_IP_CSUM;
++		}
++#endif /* TOE */
++
++#if defined(WL_CFG80211)
++		if (unlikely(wl_cfg80211_up(NULL))) {
++			DHD_ERROR(("%s: failed to bring up cfg80211\n", __FUNCTION__));
++			ret = -1;
++			goto exit;
++		}
++		if (!dhd_download_fw_on_driverload) {
++#ifdef ARP_OFFLOAD_SUPPORT
++			dhd->pend_ipaddr = 0;
++			if (!dhd_inetaddr_notifier_registered) {
++				dhd_inetaddr_notifier_registered = TRUE;
++				register_inetaddr_notifier(&dhd_inetaddr_notifier);
++			}
++#endif /* ARP_OFFLOAD_SUPPORT */
++#if defined(CONFIG_IPV6)
++			if (!dhd_inet6addr_notifier_registered) {
++				dhd_inet6addr_notifier_registered = TRUE;
++				register_inet6addr_notifier(&dhd_inet6addr_notifier);
++			}
++#endif /* OEM_ANDROID && CONFIG_IPV6 */
++#ifdef DHD_LB
++			DHD_LB_STATS_INIT(&dhd->pub);
++#ifdef DHD_LB_RXP
++			__skb_queue_head_init(&dhd->rx_pend_queue);
++#endif /* DHD_LB_RXP */
++#endif /* DHD_LB */
++		}
++
++#if defined(BCMPCIE) && defined(DHDTCPACK_SUPPRESS)
++#if defined(SET_RPS_CPUS)
++		dhd_tcpack_suppress_set(&dhd->pub, TCPACK_SUP_OFF);
++#else
++		dhd_tcpack_suppress_set(&dhd->pub, TCPACK_SUP_HOLD);
++#endif 
++#endif /* BCMPCIE && DHDTCPACK_SUPPRESS */
++#if defined(DHD_LB) && defined(DHD_LB_RXP)
++		if (dhd->rx_napi_netdev == NULL) {
++			dhd->rx_napi_netdev = dhd->iflist[ifidx]->net;
++			memset(&dhd->rx_napi_struct, 0, sizeof(struct napi_struct));
++			netif_napi_add(dhd->rx_napi_netdev, &dhd->rx_napi_struct,
++					dhd_napi_poll, dhd_napi_weight);
++			DHD_INFO(("%s napi<%p> enabled ifp->net<%p,%s>\n",
++					__FUNCTION__, &dhd->rx_napi_struct, net, net->name));
++			napi_enable(&dhd->rx_napi_struct);
++			DHD_INFO(("%s load balance init rx_napi_struct\n", __FUNCTION__));
++			skb_queue_head_init(&dhd->rx_napi_queue);
++		}
++#endif /* DHD_LB && DHD_LB_RXP */
++#if defined(NUM_SCB_MAX_PROBE)
++		dhd_set_scb_probe(&dhd->pub);
++#endif /* NUM_SCB_MAX_PROBE */
++#endif /* WL_CFG80211 */
++	}
++
++	/* Allow transmit calls */
++	netif_start_queue(net);
++	dhd->pub.up = 1;
++
++	OLD_MOD_INC_USE_COUNT;
++
++#ifdef BCMDBGFS
++	dhd_dbg_init(&dhd->pub);
++#endif
++
++exit:
++	if (ret) {
++		dhd_stop(net);
++	}
++
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++
++
++	return ret;
++}
++
++int dhd_do_driver_init(struct net_device *net)
++{
++	dhd_info_t *dhd = NULL;
++
++	if (!net) {
++		DHD_ERROR(("Primary Interface not initialized \n"));
++		return -EINVAL;
++	}
++
++
++	/*  && defined(OEM_ANDROID) && defined(BCMSDIO) */
++	dhd = DHD_DEV_INFO(net);
++
++	/* If driver is already initialized, do nothing
++	 */
++	if (dhd->pub.busstate == DHD_BUS_DATA) {
++		DHD_TRACE(("Driver already Inititalized. Nothing to do"));
++		return 0;
++	}
++
++	if (dhd_open(net) < 0) {
++		DHD_ERROR(("Driver Init Failed \n"));
++		return -1;
++	}
++
++	return 0;
++}
++
++int
++dhd_event_ifadd(dhd_info_t *dhdinfo, wl_event_data_if_t *ifevent, char *name, uint8 *mac)
++{
++
++#ifdef WL_CFG80211
++	if (wl_cfg80211_notify_ifadd(ifevent->ifidx, name, mac, ifevent->bssidx) == BCME_OK)
++		return BCME_OK;
++#endif
++
++	/* handle IF event caused by wl commands, SoftAP, WEXT and
++	 * anything else. This has to be done asynchronously otherwise
++	 * DPC will be blocked (and iovars will timeout as DPC has no chance
++	 * to read the response back)
++	 */
++	if (ifevent->ifidx > 0) {
++		dhd_if_event_t *if_event = MALLOC(dhdinfo->pub.osh, sizeof(dhd_if_event_t));
++		if (if_event == NULL) {
++			DHD_ERROR(("dhd_event_ifadd: Failed MALLOC, malloced %d bytes",
++				MALLOCED(dhdinfo->pub.osh)));
++			return BCME_NOMEM;
++		}
++
++		memcpy(&if_event->event, ifevent, sizeof(if_event->event));
++		memcpy(if_event->mac, mac, ETHER_ADDR_LEN);
++		strncpy(if_event->name, name, IFNAMSIZ);
++		if_event->name[IFNAMSIZ - 1] = '\0';
++		dhd_deferred_schedule_work(dhdinfo->dhd_deferred_wq, (void *)if_event,
++			DHD_WQ_WORK_IF_ADD, dhd_ifadd_event_handler, DHD_WORK_PRIORITY_LOW);
++	}
++
++	return BCME_OK;
++}
++
++int
++dhd_event_ifdel(dhd_info_t *dhdinfo, wl_event_data_if_t *ifevent, char *name, uint8 *mac)
++{
++	dhd_if_event_t *if_event;
++
++#ifdef WL_CFG80211
++	if (wl_cfg80211_notify_ifdel(ifevent->ifidx, name, mac, ifevent->bssidx) == BCME_OK)
++		return BCME_OK;
++#endif /* WL_CFG80211 */
++
++	/* handle IF event caused by wl commands, SoftAP, WEXT and
++	 * anything else
++	 */
++	if_event = MALLOC(dhdinfo->pub.osh, sizeof(dhd_if_event_t));
++	if (if_event == NULL) {
++		DHD_ERROR(("dhd_event_ifdel: malloc failed for if_event, malloced %d bytes",
++			MALLOCED(dhdinfo->pub.osh)));
++		return BCME_NOMEM;
++	}
++	memcpy(&if_event->event, ifevent, sizeof(if_event->event));
++	memcpy(if_event->mac, mac, ETHER_ADDR_LEN);
++	strncpy(if_event->name, name, IFNAMSIZ);
++	if_event->name[IFNAMSIZ - 1] = '\0';
++	dhd_deferred_schedule_work(dhdinfo->dhd_deferred_wq, (void *)if_event, DHD_WQ_WORK_IF_DEL,
++		dhd_ifdel_event_handler, DHD_WORK_PRIORITY_LOW);
++
++	return BCME_OK;
++}
++
++/* unregister and free the existing net_device interface (if any) in iflist and
++ * allocate a new one. the slot is reused. this function does NOT register the
++ * new interface to linux kernel. dhd_register_if does the job
++ */
++struct net_device*
++dhd_allocate_if(dhd_pub_t *dhdpub, int ifidx, char *name,
++	uint8 *mac, uint8 bssidx, bool need_rtnl_lock, char *dngl_name)
++{
++	dhd_info_t *dhdinfo = (dhd_info_t *)dhdpub->info;
++	dhd_if_t *ifp;
++
++	ASSERT(dhdinfo && (ifidx < DHD_MAX_IFS));
++	ifp = dhdinfo->iflist[ifidx];
++
++	if (ifp != NULL) {
++		if (ifp->net != NULL) {
++			DHD_ERROR(("%s: free existing IF %s\n", __FUNCTION__, ifp->net->name));
++
++			dhd_dev_priv_clear(ifp->net); /* clear net_device private */
++
++			/* in unregister_netdev case, the interface gets freed by net->destructor
++			 * (which is set to free_netdev)
++			 */
++			if (ifp->net->reg_state == NETREG_UNINITIALIZED) {
++				free_netdev(ifp->net);
++			} else {
++				netif_stop_queue(ifp->net);
++				if (need_rtnl_lock)
++					unregister_netdev(ifp->net);
++				else
++					unregister_netdevice(ifp->net);
++			}
++			ifp->net = NULL;
++		}
++	} else {
++		ifp = MALLOC(dhdinfo->pub.osh, sizeof(dhd_if_t));
++		if (ifp == NULL) {
++			DHD_ERROR(("%s: OOM - dhd_if_t(%zu)\n", __FUNCTION__, sizeof(dhd_if_t)));
++			return NULL;
++		}
++	}
++
++	memset(ifp, 0, sizeof(dhd_if_t));
++	ifp->info = dhdinfo;
++	ifp->idx = ifidx;
++	ifp->bssidx = bssidx;
++#ifdef DHD_MCAST_REGEN
++	ifp->mcast_regen_bss_enable = FALSE;
++#endif
++	/* set to TRUE rx_pkt_chainable at alloc time */
++	ifp->rx_pkt_chainable = TRUE;
++
++	if (mac != NULL)
++		memcpy(&ifp->mac_addr, mac, ETHER_ADDR_LEN);
++
++	/* Allocate etherdev, including space for private structure */
++	ifp->net = alloc_etherdev(DHD_DEV_PRIV_SIZE);
++	if (ifp->net == NULL) {
++		DHD_ERROR(("%s: OOM - alloc_etherdev(%zu)\n", __FUNCTION__, sizeof(dhdinfo)));
++		goto fail;
++	}
++
++	/* Setup the dhd interface's netdevice private structure. */
++	dhd_dev_priv_save(ifp->net, dhdinfo, ifp, ifidx);
++
++	if (name && name[0]) {
++		strncpy(ifp->net->name, name, IFNAMSIZ);
++		ifp->net->name[IFNAMSIZ - 1] = '\0';
++	}
++
++#ifdef WL_CFG80211
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++	if (ifidx == 0) {
++		ifp->net->priv_destructor = free_netdev;
++	} else {
++		ifp->net->priv_destructor = dhd_netdev_free;
++	}
++#else
++	if (ifidx == 0)
++		ifp->net->destructor = free_netdev;
++	else
++		ifp->net->destructor = dhd_netdev_free;
++#endif
++#else
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++	ifp->net->priv_destructor = free_netdev;
++#else
++	ifp->net->destructor = free_netdev;
++#endif
++#endif /* WL_CFG80211 */
++	strncpy(ifp->name, ifp->net->name, IFNAMSIZ);
++	ifp->name[IFNAMSIZ - 1] = '\0';
++	dhdinfo->iflist[ifidx] = ifp;
++
++/* initialize the dongle provided if name */
++	if (dngl_name)
++		strncpy(ifp->dngl_name, dngl_name, IFNAMSIZ);
++	else
++		strncpy(ifp->dngl_name, name, IFNAMSIZ);
++
++#ifdef PCIE_FULL_DONGLE
++	/* Initialize STA info list */
++	INIT_LIST_HEAD(&ifp->sta_list);
++	DHD_IF_STA_LIST_LOCK_INIT(ifp);
++#endif /* PCIE_FULL_DONGLE */
++
++#ifdef DHD_L2_FILTER
++	ifp->phnd_arp_table = init_l2_filter_arp_table(dhdpub->osh);
++	ifp->parp_allnode = TRUE;
++#endif /* DHD_L2_FILTER */
++
++
++	DHD_CUMM_CTR_INIT(&ifp->cumm_ctr);
++
++	return ifp->net;
++
++fail:
++
++	if (ifp != NULL) {
++		if (ifp->net != NULL) {
++			dhd_dev_priv_clear(ifp->net);
++			free_netdev(ifp->net);
++			ifp->net = NULL;
++		}
++		MFREE(dhdinfo->pub.osh, ifp, sizeof(*ifp));
++		ifp = NULL;
++	}
++
++	dhdinfo->iflist[ifidx] = NULL;
++	return NULL;
++}
++
++/* unregister and free the the net_device interface associated with the indexed
++ * slot, also free the slot memory and set the slot pointer to NULL
++ */
++int
++dhd_remove_if(dhd_pub_t *dhdpub, int ifidx, bool need_rtnl_lock)
++{
++	dhd_info_t *dhdinfo = (dhd_info_t *)dhdpub->info;
++	dhd_if_t *ifp;
++#ifdef PCIE_FULL_DONGLE
++	if_flow_lkup_t *if_flow_lkup = (if_flow_lkup_t *)dhdpub->if_flow_lkup;
++#endif /* PCIE_FULL_DONGLE */
++
++	ifp = dhdinfo->iflist[ifidx];
++
++	if (ifp != NULL) {
++		if (ifp->net != NULL) {
++			DHD_ERROR(("deleting interface '%s' idx %d\n", ifp->net->name, ifp->idx));
++
++			/* in unregister_netdev case, the interface gets freed by net->destructor
++			 * (which is set to free_netdev)
++			 */
++			if (ifp->net->reg_state == NETREG_UNINITIALIZED) {
++				free_netdev(ifp->net);
++			} else {
++				netif_tx_disable(ifp->net);
++
++
++
++#if defined(SET_RPS_CPUS)
++				custom_rps_map_clear(ifp->net->_rx);
++#endif /* SET_RPS_CPUS */
++#if defined(SET_RPS_CPUS)
++#if (defined(DHDTCPACK_SUPPRESS) && defined(BCMPCIE))
++				dhd_tcpack_suppress_set(dhdpub, TCPACK_SUP_OFF);
++#endif /* DHDTCPACK_SUPPRESS && BCMPCIE */
++#endif 
++				if (need_rtnl_lock)
++					unregister_netdev(ifp->net);
++				else
++					unregister_netdevice(ifp->net);
++			}
++			ifp->net = NULL;
++		}
++#ifdef DHD_WMF
++		dhd_wmf_cleanup(dhdpub, ifidx);
++#endif /* DHD_WMF */
++#ifdef DHD_L2_FILTER
++		bcm_l2_filter_arp_table_update(dhdpub->osh, ifp->phnd_arp_table, TRUE,
++			NULL, FALSE, dhdpub->tickcnt);
++		deinit_l2_filter_arp_table(dhdpub->osh, ifp->phnd_arp_table);
++		ifp->phnd_arp_table = NULL;
++#endif /* DHD_L2_FILTER */
++
++
++		dhd_if_del_sta_list(ifp);
++#ifdef PCIE_FULL_DONGLE
++		/* Delete flowrings of WDS interface */
++		if (if_flow_lkup[ifidx].role == WLC_E_IF_ROLE_WDS) {
++			dhd_flow_rings_delete(dhdpub, ifidx);
++		}
++#endif /* PCIE_FULL_DONGLE */
++		DHD_CUMM_CTR_INIT(&ifp->cumm_ctr);
++
++		dhdinfo->iflist[ifidx] = NULL;
++		MFREE(dhdinfo->pub.osh, ifp, sizeof(*ifp));
++
++	}
++
++	return BCME_OK;
++}
++
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
++static struct net_device_ops dhd_ops_pri = {
++	.ndo_open = dhd_open,
++	.ndo_stop = dhd_stop,
++	.ndo_get_stats = dhd_get_stats,
++	.ndo_do_ioctl = dhd_ioctl_entry,
++	.ndo_start_xmit = dhd_start_xmit,
++	.ndo_set_mac_address = dhd_set_mac_address,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	.ndo_set_rx_mode = dhd_set_multicast_list,
++#else
++	.ndo_set_multicast_list = dhd_set_multicast_list,
++#endif
++};
++
++static struct net_device_ops dhd_ops_virt = {
++	.ndo_get_stats = dhd_get_stats,
++	.ndo_do_ioctl = dhd_ioctl_entry,
++	.ndo_start_xmit = dhd_start_xmit,
++	.ndo_set_mac_address = dhd_set_mac_address,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	.ndo_set_rx_mode = dhd_set_multicast_list,
++#else
++	.ndo_set_multicast_list = dhd_set_multicast_list,
++#endif
++};
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31)) */
++
++#ifdef DEBUGGER
++extern void debugger_init(void *bus_handle);
++#endif
++
++
++#ifdef SHOW_LOGTRACE
++static char *logstrs_path = "/root/logstrs.bin";
++static char *st_str_file_path = "/root/rtecdc.bin";
++static char *map_file_path = "/root/rtecdc.map";
++static char *rom_st_str_file_path = "/root/roml.bin";
++static char *rom_map_file_path = "/root/roml.map";
++
++#define BYTES_AHEAD_NUM		11	/* address in map file is before these many bytes */
++#define READ_NUM_BYTES		1000 /* read map file each time this No. of bytes */
++#define GO_BACK_FILE_POS_NUM_BYTES	100 /* set file pos back to cur pos */
++static char *ramstart_str = "text_start"; /* string in mapfile has addr ramstart */
++static char *rodata_start_str = "rodata_start"; /* string in mapfile has addr rodata start */
++static char *rodata_end_str = "rodata_end"; /* string in mapfile has addr rodata end */
++static char *ram_file_str = "rtecdc";
++static char *rom_file_str = "roml";
++#define RAMSTART_BIT	0x01
++#define RDSTART_BIT		0x02
++#define RDEND_BIT		0x04
++#define ALL_MAP_VAL		(RAMSTART_BIT | RDSTART_BIT | RDEND_BIT)
++
++module_param(logstrs_path, charp, S_IRUGO);
++module_param(st_str_file_path, charp, S_IRUGO);
++module_param(map_file_path, charp, S_IRUGO);
++module_param(rom_st_str_file_path, charp, S_IRUGO);
++module_param(rom_map_file_path, charp, S_IRUGO);
++
++static void
++dhd_init_logstrs_array(dhd_event_log_t *temp)
++{
++	struct file *filep = NULL;
++	struct kstat stat;
++	mm_segment_t fs;
++	char *raw_fmts =  NULL;
++	int logstrs_size = 0;
++
++	logstr_header_t *hdr = NULL;
++	uint32 *lognums = NULL;
++	char *logstrs = NULL;
++	int ram_index = 0;
++	char **fmts;
++	int num_fmts = 0;
++	uint32 i = 0;
++	int error = 0;
++
++	fs = get_fs();
++	set_fs(KERNEL_DS);
++
++	filep = filp_open(logstrs_path, O_RDONLY, 0);
++
++	if (IS_ERR(filep)) {
++		DHD_ERROR(("%s: Failed to open the file %s \n", __FUNCTION__, logstrs_path));
++		goto fail;
++	}
++	error = vfs_stat(logstrs_path, &stat);
++	if (error) {
++		DHD_ERROR(("%s: Failed to stat file %s \n", __FUNCTION__, logstrs_path));
++		goto fail;
++	}
++	logstrs_size = (int) stat.size;
++
++	raw_fmts = kmalloc(logstrs_size, GFP_KERNEL);
++	if (raw_fmts == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory \n", __FUNCTION__));
++		goto fail;
++	}
++	if (vfs_read(filep, raw_fmts, logstrs_size, &filep->f_pos) !=	logstrs_size) {
++		DHD_ERROR(("%s: Failed to read file %s", __FUNCTION__, logstrs_path));
++		goto fail;
++	}
++
++	/* Remember header from the logstrs.bin file */
++	hdr = (logstr_header_t *) (raw_fmts + logstrs_size -
++		sizeof(logstr_header_t));
++
++	if (hdr->log_magic == LOGSTRS_MAGIC) {
++		/*
++		* logstrs.bin start with header.
++		*/
++		num_fmts =	hdr->rom_logstrs_offset / sizeof(uint32);
++		ram_index = (hdr->ram_lognums_offset -
++			hdr->rom_lognums_offset) / sizeof(uint32);
++		lognums = (uint32 *) &raw_fmts[hdr->rom_lognums_offset];
++		logstrs = (char *)	 &raw_fmts[hdr->rom_logstrs_offset];
++	} else {
++		/*
++		 * Legacy logstrs.bin format without header.
++		 */
++		num_fmts = *((uint32 *) (raw_fmts)) / sizeof(uint32);
++		if (num_fmts == 0) {
++			/* Legacy ROM/RAM logstrs.bin format:
++			  *  - ROM 'lognums' section
++			  *   - RAM 'lognums' section
++			  *   - ROM 'logstrs' section.
++			  *   - RAM 'logstrs' section.
++			  *
++			  * 'lognums' is an array of indexes for the strings in the
++			  * 'logstrs' section. The first uint32 is 0 (index of first
++			  * string in ROM 'logstrs' section).
++			  *
++			  * The 4324b5 is the only ROM that uses this legacy format. Use the
++			  * fixed number of ROM fmtnums to find the start of the RAM
++			  * 'lognums' section. Use the fixed first ROM string ("Con\n") to
++			  * find the ROM 'logstrs' section.
++			  */
++			#define NUM_4324B5_ROM_FMTS	186
++			#define FIRST_4324B5_ROM_LOGSTR "Con\n"
++			ram_index = NUM_4324B5_ROM_FMTS;
++			lognums = (uint32 *) raw_fmts;
++			num_fmts =	ram_index;
++			logstrs = (char *) &raw_fmts[num_fmts << 2];
++			while (strncmp(FIRST_4324B5_ROM_LOGSTR, logstrs, 4)) {
++				num_fmts++;
++				logstrs = (char *) &raw_fmts[num_fmts << 2];
++			}
++		} else {
++				/* Legacy RAM-only logstrs.bin format:
++				 *	  - RAM 'lognums' section
++				 *	  - RAM 'logstrs' section.
++				 *
++				 * 'lognums' is an array of indexes for the strings in the
++				 * 'logstrs' section. The first uint32 is an index to the
++				 * start of 'logstrs'. Therefore, if this index is divided
++				 * by 'sizeof(uint32)' it provides the number of logstr
++				 *	entries.
++				 */
++				ram_index = 0;
++				lognums = (uint32 *) raw_fmts;
++				logstrs = (char *)	&raw_fmts[num_fmts << 2];
++			}
++	}
++	fmts = kmalloc(num_fmts  * sizeof(char *), GFP_KERNEL);
++	if (fmts == NULL) {
++		DHD_ERROR(("Failed to allocate fmts memory"));
++		goto fail;
++	}
++
++	for (i = 0; i < num_fmts; i++) {
++		/* ROM lognums index into logstrs using 'rom_logstrs_offset' as a base
++		* (they are 0-indexed relative to 'rom_logstrs_offset').
++		*
++		* RAM lognums are already indexed to point to the correct RAM logstrs (they
++		* are 0-indexed relative to the start of the logstrs.bin file).
++		*/
++		if (i == ram_index) {
++			logstrs = raw_fmts;
++		}
++		fmts[i] = &logstrs[lognums[i]];
++	}
++	temp->fmts = fmts;
++	temp->raw_fmts = raw_fmts;
++	temp->num_fmts = num_fmts;
++	filp_close(filep, NULL);
++	set_fs(fs);
++	return;
++fail:
++	if (raw_fmts) {
++		kfree(raw_fmts);
++		raw_fmts = NULL;
++	}
++	if (!IS_ERR(filep))
++		filp_close(filep, NULL);
++	set_fs(fs);
++	temp->fmts = NULL;
++	return;
++}
++
++static int
++dhd_read_map(char *fname, uint32 *ramstart, uint32 *rodata_start,
++	uint32 *rodata_end)
++{
++	struct file *filep = NULL;
++	mm_segment_t fs;
++	char *raw_fmts =  NULL;
++	uint32 read_size = READ_NUM_BYTES;
++	int error = 0;
++	char * cptr = NULL;
++	char c;
++	uint8 count = 0;
++
++	*ramstart = 0;
++	*rodata_start = 0;
++	*rodata_end = 0;
++
++	if (fname == NULL) {
++		DHD_ERROR(("%s: ERROR fname is NULL \n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	fs = get_fs();
++	set_fs(KERNEL_DS);
++
++	filep = filp_open(fname, O_RDONLY, 0);
++	if (IS_ERR(filep)) {
++		DHD_ERROR(("%s: Failed to open %s \n",  __FUNCTION__, fname));
++		goto fail;
++	}
++
++	/* Allocate 1 byte more than read_size to terminate it with NULL */
++	raw_fmts = kmalloc(read_size + 1, GFP_KERNEL);
++	if (raw_fmts == NULL) {
++		DHD_ERROR(("%s: Failed to allocate raw_fmts memory \n", __FUNCTION__));
++		goto fail;
++	}
++
++	/* read ram start, rodata_start and rodata_end values from map  file */
++
++	while (count != ALL_MAP_VAL)
++	{
++		error = vfs_read(filep, raw_fmts, read_size, (&filep->f_pos));
++		if (error < 0) {
++			DHD_ERROR(("%s: read failed %s err:%d \n", __FUNCTION__,
++				map_file_path, error));
++			goto fail;
++		}
++
++		if (error < read_size) {
++			/*
++			* since we reset file pos back to earlier pos by
++			* GO_BACK_FILE_POS_NUM_BYTES bytes we won't reach EOF.
++			* So if ret value is less than read_size, reached EOF don't read further
++			*/
++			break;
++		}
++		/* End raw_fmts with NULL as strstr expects NULL terminated strings */
++		raw_fmts[read_size] = '\0';
++
++		/* Get ramstart address */
++		if ((cptr = strstr(raw_fmts, ramstart_str))) {
++			cptr = cptr - BYTES_AHEAD_NUM;
++			sscanf(cptr, "%x %c text_start", ramstart, &c);
++			count |= RAMSTART_BIT;
++		}
++
++		/* Get ram rodata start address */
++		if ((cptr = strstr(raw_fmts, rodata_start_str))) {
++			cptr = cptr - BYTES_AHEAD_NUM;
++			sscanf(cptr, "%x %c rodata_start", rodata_start, &c);
++			count |= RDSTART_BIT;
++		}
++
++		/* Get ram rodata end address */
++		if ((cptr = strstr(raw_fmts, rodata_end_str))) {
++			cptr = cptr - BYTES_AHEAD_NUM;
++			sscanf(cptr, "%x %c rodata_end", rodata_end, &c);
++			count |= RDEND_BIT;
++		}
++		memset(raw_fmts, 0, read_size);
++		/*
++		* go back to predefined NUM of bytes so that we won't miss
++		* the string and  addr even if it comes as splited in next read.
++		*/
++		filep->f_pos = filep->f_pos - GO_BACK_FILE_POS_NUM_BYTES;
++	}
++
++	DHD_ERROR(("---ramstart: 0x%x, rodata_start: 0x%x, rodata_end:0x%x\n",
++		*ramstart, *rodata_start, *rodata_end));
++
++	DHD_ERROR(("readmap over \n"));
++
++fail:
++	if (raw_fmts) {
++		kfree(raw_fmts);
++		raw_fmts = NULL;
++	}
++	if (!IS_ERR(filep))
++		filp_close(filep, NULL);
++
++	set_fs(fs);
++	if (count == ALL_MAP_VAL) {
++		return BCME_OK;
++	}
++	DHD_ERROR(("readmap error 0X%x \n", count));
++	return BCME_ERROR;
++}
++
++static void
++dhd_init_static_strs_array(dhd_event_log_t *temp, char *str_file, char *map_file)
++{
++	struct file *filep = NULL;
++	mm_segment_t fs;
++	char *raw_fmts =  NULL;
++	uint32 logstrs_size = 0;
++
++	int error = 0;
++	uint32 ramstart = 0;
++	uint32 rodata_start = 0;
++	uint32 rodata_end = 0;
++	uint32 logfilebase = 0;
++
++	error = dhd_read_map(map_file, &ramstart, &rodata_start, &rodata_end);
++	if (error == BCME_ERROR) {
++		DHD_ERROR(("readmap Error!! \n"));
++		/* don't do event log parsing in actual case */
++		temp->raw_sstr = NULL;
++		return;
++	}
++	DHD_ERROR(("ramstart: 0x%x, rodata_start: 0x%x, rodata_end:0x%x\n",
++		ramstart, rodata_start, rodata_end));
++
++	fs = get_fs();
++	set_fs(KERNEL_DS);
++
++	filep = filp_open(str_file, O_RDONLY, 0);
++	if (IS_ERR(filep)) {
++		DHD_ERROR(("%s: Failed to open the file %s \n",  __FUNCTION__, str_file));
++		goto fail;
++	}
++
++	/* Full file size is huge. Just read required part */
++	logstrs_size = rodata_end - rodata_start;
++
++	raw_fmts = kmalloc(logstrs_size, GFP_KERNEL);
++	if (raw_fmts == NULL) {
++		DHD_ERROR(("%s: Failed to allocate raw_fmts memory \n", __FUNCTION__));
++		goto fail;
++	}
++
++	logfilebase = rodata_start - ramstart;
++
++	error = generic_file_llseek(filep, logfilebase, SEEK_SET);
++	if (error < 0) {
++		DHD_ERROR(("%s: %s llseek failed %d \n", __FUNCTION__, str_file, error));
++		goto fail;
++	}
++
++	error = vfs_read(filep, raw_fmts, logstrs_size, (&filep->f_pos));
++	if (error != logstrs_size) {
++		DHD_ERROR(("%s: %s read failed %d \n", __FUNCTION__, str_file, error));
++		goto fail;
++	}
++
++	if (strstr(str_file, ram_file_str) != NULL) {
++		temp->raw_sstr = raw_fmts;
++		temp->ramstart = ramstart;
++		temp->rodata_start = rodata_start;
++		temp->rodata_end = rodata_end;
++	} else if (strstr(str_file, rom_file_str) != NULL) {
++		temp->rom_raw_sstr = raw_fmts;
++		temp->rom_ramstart = ramstart;
++		temp->rom_rodata_start = rodata_start;
++		temp->rom_rodata_end = rodata_end;
++	}
++
++	filp_close(filep, NULL);
++	set_fs(fs);
++
++	return;
++fail:
++	if (raw_fmts) {
++		kfree(raw_fmts);
++		raw_fmts = NULL;
++	}
++	if (!IS_ERR(filep))
++		filp_close(filep, NULL);
++	set_fs(fs);
++	if (strstr(str_file, ram_file_str) != NULL) {
++		temp->raw_sstr = NULL;
++	} else if (strstr(str_file, rom_file_str) != NULL) {
++		temp->rom_raw_sstr = NULL;
++	}
++	return;
++}
++
++#endif /* SHOW_LOGTRACE */
++#ifdef DHD_LB
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0))
++
++static enum cpuhp_state dhd_cpuhp_online_state;
++
++static int
++dhd_cpuhp_init(osl_t *osh, dhd_info_t *dhd)
++{
++	int ret = 0;
++
++	ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/wireless/dhd:online",
++			dhd_cpuhp_online, dhd_cpuhp_dead);
++	if (ret < 0) {
++		DHD_ERROR(("%s(): cpuhp_setup_state_multi() online failed, ret=%d\n",
++			__FUNCTION__, ret));
++		return ret;
++	}
++	dhd_cpuhp_online_state = ret;
++	cpuhp_state_add_instance_nocalls(dhd_cpuhp_online_state,
++		&dhd->node_online);
++	return ret;
++}
++#endif
++#endif
++
++
++dhd_pub_t *
++dhd_attach(osl_t *osh, struct dhd_bus *bus, uint bus_hdrlen)
++{
++	dhd_info_t *dhd = NULL;
++	struct net_device *net = NULL;
++	char if_name[IFNAMSIZ] = {'\0'};
++	uint32 bus_type = -1;
++	uint32 bus_num = -1;
++	uint32 slot_num = -1;
++	wifi_adapter_info_t *adapter = NULL;
++
++	dhd_attach_states_t dhd_state = DHD_ATTACH_STATE_INIT;
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++#ifdef STBLINUX
++	DHD_ERROR(("%s\n", driver_target));
++#endif /* STBLINUX */
++	/* will implement get_ids for DBUS later */
++#if !defined(BCMDBUS) && defined(BCMSDIO)
++	dhd_bus_get_ids(bus, &bus_type, &bus_num, &slot_num);
++#endif /* !defined(BCMDBUS) && defined(BCMSDIO) */
++	adapter = dhd_wifi_platform_get_adapter(bus_type, bus_num, slot_num);
++
++	/* Allocate primary dhd_info */
++	dhd = wifi_platform_prealloc(adapter, DHD_PREALLOC_DHD_INFO, sizeof(dhd_info_t));
++	if (dhd == NULL) {
++		dhd = MALLOC(osh, sizeof(dhd_info_t));
++		if (dhd == NULL) {
++			DHD_ERROR(("%s: OOM - alloc dhd_info\n", __FUNCTION__));
++			goto fail;
++		}
++	}
++	memset(dhd, 0, sizeof(dhd_info_t));
++	dhd_state |= DHD_ATTACH_STATE_DHD_ALLOC;
++
++	dhd->unit = dhd_found + instance_base; /* do not increment dhd_found, yet */
++
++	dhd->pub.osh = osh;
++	dhd->adapter = adapter;
++
++#ifdef GET_CUSTOM_MAC_ENABLE
++	wifi_platform_get_mac_addr(dhd->adapter, dhd->pub.mac.octet);
++#endif /* GET_CUSTOM_MAC_ENABLE */
++#ifdef CUSTOM_FORCE_NODFS_FLAG
++	dhd->pub.dhd_cflags |= WLAN_PLAT_NODFS_FLAG;
++	dhd->pub.force_country_change = TRUE;
++#endif /* CUSTOM_FORCE_NODFS_FLAG */
++#ifdef CUSTOM_COUNTRY_CODE
++	get_customized_country_code(dhd->adapter,
++		dhd->pub.dhd_cspec.country_abbrev, &dhd->pub.dhd_cspec,
++		dhd->pub.dhd_cflags);
++#endif /* CUSTOM_COUNTRY_CODE */
++#ifndef BCMDBUS
++	dhd->thr_dpc_ctl.thr_pid = DHD_PID_KT_TL_INVALID;
++	dhd->thr_wdt_ctl.thr_pid = DHD_PID_KT_INVALID;
++
++#ifdef DHD_WET
++	dhd->pub.wet_info = dhd_get_wet_info(&dhd->pub);
++#endif
++
++	/* Initialize thread based operation and lock */
++	sema_init(&dhd->sdsem, 1);
++
++	/* Some DHD modules (e.g. cfg80211) configures operation mode based on firmware name.
++	 * This is indeed a hack but we have to make it work properly before we have a better
++	 * solution
++	 */
++	dhd_update_fw_nv_path(dhd);
++#endif /* BCMDBUS */
++
++	/* Link to info module */
++	dhd->pub.info = dhd;
++
++
++	/* Link to bus module */
++	dhd->pub.bus = bus;
++	dhd->pub.hdrlen = bus_hdrlen;
++
++	/* Set network interface name if it was provided as module parameter */
++	if (iface_name[0]) {
++		int len;
++		char ch;
++		strncpy(if_name, iface_name, IFNAMSIZ);
++		if_name[IFNAMSIZ - 1] = 0;
++		len = strlen(if_name);
++		ch = if_name[len - 1];
++		if ((ch > '9' || ch < '0') && (len < IFNAMSIZ - 2))
++			strcat(if_name, "%d");
++	}
++
++	/* Passing NULL to dngl_name to ensure host gets if_name in dngl_name member */
++	net = dhd_allocate_if(&dhd->pub, 0, if_name, NULL, 0, TRUE, NULL);
++	if (net == NULL) {
++		goto fail;
++	}
++
++
++	dhd_state |= DHD_ATTACH_STATE_ADD_IF;
++#ifdef DHD_L2_FILTER
++	/* initialize the l2_filter_cnt */
++	dhd->pub.l2_filter_cnt = 0;
++#endif
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31))
++	net->open = NULL;
++#else
++	net->netdev_ops = NULL;
++#endif
++
++	sema_init(&dhd->proto_sem, 1);
++#ifdef DHD_ULP
++	if (!(dhd_ulp_init(osh, &dhd->pub)))
++		goto fail;
++#endif /* DHD_ULP */
++
++#ifdef PROP_TXSTATUS
++	spin_lock_init(&dhd->wlfc_spinlock);
++
++	dhd->pub.skip_fc = dhd_wlfc_skip_fc;
++	dhd->pub.plat_init = dhd_wlfc_plat_init;
++	dhd->pub.plat_deinit = dhd_wlfc_plat_deinit;
++
++#ifdef DHD_WLFC_THREAD
++	init_waitqueue_head(&dhd->pub.wlfc_wqhead);
++	dhd->pub.wlfc_thread = kthread_create(dhd_wlfc_transfer_packets, &dhd->pub, "wlfc-thread");
++	if (IS_ERR(dhd->pub.wlfc_thread)) {
++		DHD_ERROR(("create wlfc thread failed\n"));
++		goto fail;
++	} else {
++		wake_up_process(dhd->pub.wlfc_thread);
++	}
++#endif /* DHD_WLFC_THREAD */
++#endif /* PROP_TXSTATUS */
++
++	/* Initialize other structure content */
++	init_waitqueue_head(&dhd->ioctl_resp_wait);
++	init_waitqueue_head(&dhd->d3ack_wait);
++	init_waitqueue_head(&dhd->ctrl_wait);
++	init_waitqueue_head(&dhd->dhd_bus_busy_state_wait);
++	dhd->pub.dhd_bus_busy_state = 0;
++
++	/* Initialize the spinlocks */
++	spin_lock_init(&dhd->sdlock);
++	spin_lock_init(&dhd->txqlock);
++	spin_lock_init(&dhd->dhd_lock);
++	spin_lock_init(&dhd->rxf_lock);
++#if defined(RXFRAME_THREAD)
++	dhd->rxthread_enabled = TRUE;
++#endif /* defined(RXFRAME_THREAD) */
++
++#ifdef DHDTCPACK_SUPPRESS
++	spin_lock_init(&dhd->tcpack_lock);
++#endif /* DHDTCPACK_SUPPRESS */
++
++	/* Initialize Wakelock stuff */
++	spin_lock_init(&dhd->wakelock_spinlock);
++	dhd->wakelock_counter = 0;
++	dhd->wakelock_wd_counter = 0;
++	dhd->wakelock_rx_timeout_enable = 0;
++	dhd->wakelock_ctrl_timeout_enable = 0;
++#ifdef CONFIG_HAS_WAKELOCK
++	wake_lock_init(&dhd->wl_wifi, WAKE_LOCK_SUSPEND, "wlan_wake");
++	wake_lock_init(&dhd->wl_rxwake, WAKE_LOCK_SUSPEND, "wlan_rx_wake");
++	wake_lock_init(&dhd->wl_ctrlwake, WAKE_LOCK_SUSPEND, "wlan_ctrl_wake");
++	wake_lock_init(&dhd->wl_wdwake, WAKE_LOCK_SUSPEND, "wlan_wd_wake");
++#ifdef BCMPCIE_OOB_HOST_WAKE
++	wake_lock_init(&dhd->wl_intrwake, WAKE_LOCK_SUSPEND, "wlan_oob_irq_wake");
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#ifdef DHD_USE_SCAN_WAKELOCK
++	wake_lock_init(&dhd->wl_scanwake, WAKE_LOCK_SUSPEND, "wlan_scan_wake");
++#endif /* DHD_USE_SCAN_WAKELOCK */
++#endif /* CONFIG_HAS_WAKELOCK */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	mutex_init(&dhd->dhd_net_if_mutex);
++	mutex_init(&dhd->dhd_suspend_mutex);
++#endif
++	dhd_state |= DHD_ATTACH_STATE_WAKELOCKS_INIT;
++
++	/* Attach and link in the protocol */
++	if (dhd_prot_attach(&dhd->pub) != 0) {
++		DHD_ERROR(("dhd_prot_attach failed\n"));
++		goto fail;
++	}
++	dhd_state |= DHD_ATTACH_STATE_PROT_ATTACH;
++
++#ifdef WL_CFG80211
++	/* Attach and link in the cfg80211 */
++	if (unlikely(wl_cfg80211_attach(net, &dhd->pub))) {
++		DHD_ERROR(("wl_cfg80211_attach failed\n"));
++		goto fail;
++	}
++
++	dhd_monitor_init(&dhd->pub);
++	dhd_state |= DHD_ATTACH_STATE_CFG80211;
++#endif
++#if defined(WL_WIRELESS_EXT)
++	/* Attach and link in the iw */
++	if (!(dhd_state &  DHD_ATTACH_STATE_CFG80211)) {
++		if (wl_iw_attach(net, (void *)&dhd->pub) != 0) {
++		DHD_ERROR(("wl_iw_attach failed\n"));
++		goto fail;
++	}
++	dhd_state |= DHD_ATTACH_STATE_WL_ATTACH;
++	}
++#endif /* defined(WL_WIRELESS_EXT) */
++
++#ifdef SHOW_LOGTRACE
++	dhd_init_logstrs_array(&dhd->event_data);
++	dhd_init_static_strs_array(&dhd->event_data, st_str_file_path, map_file_path);
++	dhd_init_static_strs_array(&dhd->event_data, rom_st_str_file_path, rom_map_file_path);
++
++	/* attach debug if support */
++	if (dhd_os_dbg_attach(&dhd->pub)) {
++		DHD_ERROR(("%s debug module attach failed\n", __FUNCTION__));
++		goto fail;
++	}
++#endif /* SHOW_LOGTRACE */
++
++	if (dhd_sta_pool_init(&dhd->pub, DHD_MAX_STA) != BCME_OK) {
++		DHD_ERROR(("%s: Initializing %u sta\n", __FUNCTION__, DHD_MAX_STA));
++		goto fail;
++	}
++
++
++#ifndef BCMDBUS
++
++	/* Set up the watchdog timer */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++	timer_setup(&dhd->timer, dhd_watchdog, 0);
++#else
++	init_timer(&dhd->timer);
++	dhd->timer.data = (ulong)dhd;
++	dhd->timer.function = dhd_watchdog;
++#endif
++	dhd->default_wd_interval = dhd_watchdog_ms;
++
++	if (dhd_watchdog_prio >= 0) {
++		/* Initialize watchdog thread */
++		PROC_START(dhd_watchdog_thread, dhd, &dhd->thr_wdt_ctl, 0, "dhd_watchdog_thread");
++
++	} else {
++		dhd->thr_wdt_ctl.thr_pid = -1;
++	}
++
++#ifdef DEBUGGER
++	debugger_init((void *) bus);
++#endif
++
++	/* Set up the bottom half handler */
++	if (dhd_dpc_prio >= 0) {
++		/* Initialize DPC thread */
++		PROC_START(dhd_dpc_thread, dhd, &dhd->thr_dpc_ctl, 0, "dhd_dpc");
++	} else {
++		/*  use tasklet for dpc */
++		tasklet_init(&dhd->tasklet, dhd_dpc, (ulong)dhd);
++		dhd->thr_dpc_ctl.thr_pid = -1;
++	}
++
++	if (dhd->rxthread_enabled) {
++		bzero(&dhd->pub.skbbuf[0], sizeof(void *) * MAXSKBPEND);
++		/* Initialize RXF thread */
++		PROC_START(dhd_rxf_thread, dhd, &dhd->thr_rxf_ctl, 0, "dhd_rxf");
++	}
++#endif /* BCMDBUS */
++
++	dhd_state |= DHD_ATTACH_STATE_THREADS_CREATED;
++
++#if defined(CONFIG_PM_SLEEP)
++	if (!dhd_pm_notifier_registered) {
++		dhd_pm_notifier_registered = TRUE;
++		dhd->pm_notifier.notifier_call = dhd_pm_callback;
++		dhd->pm_notifier.priority = 10;
++		register_pm_notifier(&dhd->pm_notifier);
++	}
++
++#endif /* CONFIG_PM_SLEEP */
++
++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND)
++	dhd->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 20;
++	dhd->early_suspend.suspend = dhd_early_suspend;
++	dhd->early_suspend.resume = dhd_late_resume;
++	register_early_suspend(&dhd->early_suspend);
++	dhd_state |= DHD_ATTACH_STATE_EARLYSUSPEND_DONE;
++#endif /* CONFIG_HAS_EARLYSUSPEND && DHD_USE_EARLYSUSPEND */
++
++#ifdef ARP_OFFLOAD_SUPPORT
++	dhd->pend_ipaddr = 0;
++	if (!dhd_inetaddr_notifier_registered) {
++		dhd_inetaddr_notifier_registered = TRUE;
++		register_inetaddr_notifier(&dhd_inetaddr_notifier);
++	}
++#endif /* ARP_OFFLOAD_SUPPORT */
++
++#if defined(CONFIG_IPV6)
++	if (!dhd_inet6addr_notifier_registered) {
++		dhd_inet6addr_notifier_registered = TRUE;
++		register_inet6addr_notifier(&dhd_inet6addr_notifier);
++	}
++#endif /* OEM_ANDROID && CONFIG_IPV6 */
++	dhd->dhd_deferred_wq = dhd_deferred_work_init((void *)dhd);
++#ifdef DEBUG_CPU_FREQ
++	dhd->new_freq = alloc_percpu(int);
++	dhd->freq_trans.notifier_call = dhd_cpufreq_notifier;
++	cpufreq_register_notifier(&dhd->freq_trans, CPUFREQ_TRANSITION_NOTIFIER);
++#endif
++#ifdef DHDTCPACK_SUPPRESS
++#ifdef BCMSDIO
++	dhd_tcpack_suppress_set(&dhd->pub, TCPACK_SUP_DELAYTX);
++#elif defined(BCMPCIE)
++	dhd_tcpack_suppress_set(&dhd->pub, TCPACK_SUP_HOLD);
++#else
++	dhd_tcpack_suppress_set(&dhd->pub, TCPACK_SUP_OFF);
++#endif /* BCMSDIO */
++#endif /* DHDTCPACK_SUPPRESS */
++
++#if defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW)
++#if defined(BCMDBUS)
++	sema_init(&dhd->fw_download_lock, 0);
++	dhd->fw_download_task = kthread_run(fw_download_thread_func, dhd, "fwdl-thread");
++#endif /* BCMDBUS */
++#endif /* defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW) */
++
++	dhd_state |= DHD_ATTACH_STATE_DONE;
++	dhd->dhd_state = dhd_state;
++
++	dhd_found++;
++
++#ifdef DHD_DEBUG_PAGEALLOC
++	register_page_corrupt_cb(dhd_page_corrupt_cb, &dhd->pub);
++#endif /* DHD_DEBUG_PAGEALLOC */
++
++#if defined(DHD_LB)
++	DHD_ERROR(("DHD LOAD BALANCING Enabled\n"));
++
++	dhd_lb_set_default_cpus(dhd);
++
++	/* Initialize the CPU Masks */
++	if (dhd_cpumasks_init(dhd) ==  0) {
++
++		/* Now we have the current CPU maps, run through candidacy */
++		dhd_select_cpu_candidacy(dhd);
++
++		/*
++		 * If we are able to initialize CPU masks, lets register to the
++		 * CPU Hotplug framework to change the CPU for each job dynamically
++		 * using candidacy algorithm.
++		 */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0))
++		dhd_cpuhp_init(osh, dhd);
++#else
++		dhd->cpu_notifier.notifier_call = dhd_cpu_callback;
++		register_cpu_notifier(&dhd->cpu_notifier); /* Register a callback */
++#endif
++	} else {
++		/*
++		 * We are unable to initialize CPU masks, so candidacy algorithm
++		 * won't run, but still Load Balancing will be honoured based
++		 * on the CPUs allocated for a given job statically during init
++		 */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0))
++#else
++		dhd->cpu_notifier.notifier_call = NULL;
++		DHD_ERROR(("%s(): dhd_cpumasks_init failed CPUs for JOB would be static\n",
++			__FUNCTION__));
++#endif
++	}
++
++
++	DHD_LB_STATS_INIT(&dhd->pub);
++
++	/* Initialize the Load Balancing Tasklets and Napi object */
++#if defined(DHD_LB_TXC)
++	tasklet_init(&dhd->tx_compl_tasklet,
++		dhd_lb_tx_compl_handler, (ulong)(&dhd->pub));
++	INIT_WORK(&dhd->tx_compl_dispatcher_work, dhd_tx_compl_dispatcher_fn);
++	DHD_INFO(("%s load balance init tx_compl_tasklet\n", __FUNCTION__));
++#endif /* DHD_LB_TXC */
++
++#if defined(DHD_LB_RXC)
++	tasklet_init(&dhd->rx_compl_tasklet,
++		dhd_lb_rx_compl_handler, (ulong)(&dhd->pub));
++	INIT_WORK(&dhd->rx_compl_dispatcher_work, dhd_rx_compl_dispatcher_fn);
++	DHD_INFO(("%s load balance init rx_compl_tasklet\n", __FUNCTION__));
++#endif /* DHD_LB_RXC */
++
++#if defined(DHD_LB_RXP)
++	 __skb_queue_head_init(&dhd->rx_pend_queue);
++	skb_queue_head_init(&dhd->rx_napi_queue);
++
++	/* Initialize the work that dispatches NAPI job to a given core */
++	INIT_WORK(&dhd->rx_napi_dispatcher_work, dhd_rx_napi_dispatcher_fn);
++	DHD_INFO(("%s load balance init rx_napi_queue\n", __FUNCTION__));
++#endif /* DHD_LB_RXP */
++
++#endif /* DHD_LB */
++	return &dhd->pub;
++
++fail:
++	if (dhd_state >= DHD_ATTACH_STATE_DHD_ALLOC) {
++		DHD_TRACE(("%s: Calling dhd_detach dhd_state 0x%x &dhd->pub %p\n",
++			__FUNCTION__, dhd_state, &dhd->pub));
++		dhd->dhd_state = dhd_state;
++		dhd_detach(&dhd->pub);
++		dhd_free(&dhd->pub);
++	}
++
++	return NULL;
++}
++
++int dhd_get_fw_mode(dhd_info_t *dhdinfo)
++{
++	if (strstr(dhdinfo->fw_path, "_apsta") != NULL)
++		return DHD_FLAG_HOSTAP_MODE;
++	if (strstr(dhdinfo->fw_path, "_p2p") != NULL)
++		return DHD_FLAG_P2P_MODE;
++	if (strstr(dhdinfo->fw_path, "_ibss") != NULL)
++		return DHD_FLAG_IBSS_MODE;
++	if (strstr(dhdinfo->fw_path, "_mfg") != NULL)
++		return DHD_FLAG_MFG_MODE;
++
++	return DHD_FLAG_STA_MODE;
++}
++
++#ifndef BCMDBUS
++bool dhd_update_fw_nv_path(dhd_info_t *dhdinfo)
++{
++	int fw_len;
++	int nv_len;
++	const char *fw = NULL;
++	const char *nv = NULL;
++	wifi_adapter_info_t *adapter = dhdinfo->adapter;
++
++
++	/* Update firmware and nvram path. The path may be from adapter info or module parameter
++	 * The path from adapter info is used for initialization only (as it won't change).
++	 *
++	 * The firmware_path/nvram_path module parameter may be changed by the system at run
++	 * time. When it changes we need to copy it to dhdinfo->fw_path. Also Android private
++	 * command may change dhdinfo->fw_path. As such we need to clear the path info in
++	 * module parameter after it is copied. We won't update the path until the module parameter
++	 * is changed again (first character is not '\0')
++	 */
++
++	/* set default firmware and nvram path for built-in type driver */
++	if (!dhd_download_fw_on_driverload) {
++#ifdef CONFIG_BCMDHD_1_363_125_17_FW_PATH
++		fw = CONFIG_BCMDHD_1_363_125_17_FW_PATH;
++#endif /* CONFIG_BCMDHD_1_363_125_17_FW_PATH */
++#ifdef CONFIG_BCMDHD_1_363_125_17_NVRAM_PATH
++		nv = CONFIG_BCMDHD_1_363_125_17_NVRAM_PATH;
++#endif /* CONFIG_BCMDHD_1_363_125_17_NVRAM_PATH */
++	}
++
++	/* check if we need to initialize the path */
++	if (dhdinfo->fw_path[0] == '\0') {
++		if (adapter && adapter->fw_path && adapter->fw_path[0] != '\0')
++			fw = adapter->fw_path;
++
++	}
++	if (dhdinfo->nv_path[0] == '\0') {
++		if (adapter && adapter->nv_path && adapter->nv_path[0] != '\0')
++			nv = adapter->nv_path;
++	}
++
++	/* Use module parameter if it is valid, EVEN IF the path has not been initialized
++	 *
++	 * TODO: need a solution for multi-chip, can't use the same firmware for all chips
++	 */
++	if (firmware_path[0] != '\0')
++		fw = firmware_path;
++	if (nvram_path[0] != '\0')
++		nv = nvram_path;
++
++	if (fw && fw[0] != '\0') {
++		fw_len = strlen(fw);
++		if (fw_len >= sizeof(dhdinfo->fw_path)) {
++			DHD_ERROR(("fw path len exceeds max len of dhdinfo->fw_path\n"));
++			return FALSE;
++		}
++		strncpy(dhdinfo->fw_path, fw, sizeof(dhdinfo->fw_path));
++		if (dhdinfo->fw_path[fw_len-1] == '\n')
++		       dhdinfo->fw_path[fw_len-1] = '\0';
++	}
++	if (nv && nv[0] != '\0') {
++		nv_len = strlen(nv);
++		if (nv_len >= sizeof(dhdinfo->nv_path)) {
++			DHD_ERROR(("nvram path len exceeds max len of dhdinfo->nv_path\n"));
++			return FALSE;
++		}
++		strncpy(dhdinfo->nv_path, nv, sizeof(dhdinfo->nv_path));
++		if (dhdinfo->nv_path[nv_len-1] == '\n')
++		       dhdinfo->nv_path[nv_len-1] = '\0';
++	}
++
++	/* clear the path in module parameter */
++	firmware_path[0] = '\0';
++	nvram_path[0] = '\0';
++
++#ifndef BCMEMBEDIMAGE
++	/* fw_path and nv_path are not mandatory for BCMEMBEDIMAGE */
++	if (dhdinfo->fw_path[0] == '\0') {
++		DHD_ERROR(("firmware path not found\n"));
++		return FALSE;
++	}
++	if (dhdinfo->nv_path[0] == '\0') {
++		DHD_ERROR(("nvram path not found\n"));
++		return FALSE;
++	}
++#endif /* BCMEMBEDIMAGE */
++
++	return TRUE;
++}
++
++
++int
++dhd_bus_start(dhd_pub_t *dhdp)
++{
++	int ret = -1;
++	dhd_info_t *dhd = (dhd_info_t*)dhdp->info;
++	unsigned long flags;
++
++	ASSERT(dhd);
++
++	DHD_TRACE(("Enter %s:\n", __FUNCTION__));
++
++	DHD_PERIM_LOCK(dhdp);
++
++	/* try to download image and nvram to the dongle */
++	if  (dhd->pub.busstate == DHD_BUS_DOWN && dhd_update_fw_nv_path(dhd)) {
++		DHD_INFO(("%s download fw %s, nv %s\n", __FUNCTION__, dhd->fw_path, dhd->nv_path));
++		ret = dhd_bus_download_firmware(dhd->pub.bus, dhd->pub.osh,
++		                                dhd->fw_path, dhd->nv_path);
++		if (ret < 0) {
++			DHD_ERROR(("%s: failed to download firmware %s\n",
++			          __FUNCTION__, dhd->fw_path));
++			DHD_PERIM_UNLOCK(dhdp);
++			return ret;
++		}
++		/* Indicate FW Download has succeeded */
++		dhd_fw_downloaded = TRUE;
++	}
++	if (dhd->pub.busstate != DHD_BUS_LOAD) {
++		DHD_PERIM_UNLOCK(dhdp);
++		return -ENETDOWN;
++	}
++
++	dhd_os_sdlock(dhdp);
++
++	/* Start the watchdog timer */
++	dhd->pub.tickcnt = 0;
++	dhd_os_wd_timer(&dhd->pub, dhd_watchdog_ms);
++
++	/* Bring up the bus */
++	if ((ret = dhd_bus_init(&dhd->pub, FALSE)) != 0) {
++
++		DHD_ERROR(("%s, dhd_bus_init failed %d\n", __FUNCTION__, ret));
++		dhd_os_sdunlock(dhdp);
++		DHD_PERIM_UNLOCK(dhdp);
++		return ret;
++	}
++
++#ifdef DHD_ULP
++	dhd_ulp_set_ulp_state(dhdp, DHD_ULP_DISABLED);
++#endif /* DHD_ULP */
++#if defined(OOB_INTR_ONLY) || defined(BCMPCIE_OOB_HOST_WAKE)
++#if defined(BCMPCIE_OOB_HOST_WAKE)
++	dhd_os_sdunlock(dhdp);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++	/* Host registration for OOB interrupt */
++	if (dhd_bus_oob_intr_register(dhdp)) {
++		/* deactivate timer and wait for the handler to finish */
++#if !defined(BCMPCIE_OOB_HOST_WAKE)
++		DHD_GENERAL_LOCK(&dhd->pub, flags);
++		dhd->wd_timer_valid = FALSE;
++		DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++		del_timer_sync(&dhd->timer);
++
++		dhd_os_sdunlock(dhdp);
++#endif /* !BCMPCIE_OOB_HOST_WAKE */
++		DHD_PERIM_UNLOCK(dhdp);
++		DHD_ERROR(("%s Host failed to register for OOB\n", __FUNCTION__));
++		return -ENODEV;
++	}
++
++#if defined(BCMPCIE_OOB_HOST_WAKE)
++	dhd_os_sdlock(dhdp);
++	dhd_bus_oob_intr_set(dhdp, TRUE);
++#else
++	/* Enable oob at firmware */
++	dhd_enable_oob_intr(dhd->pub.bus, TRUE);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#endif 
++#ifdef PCIE_FULL_DONGLE
++	{
++		/* max_h2d_rings includes H2D common rings */
++		uint32 max_h2d_rings = dhd_bus_max_h2d_queues(dhd->pub.bus);
++
++		DHD_ERROR(("%s: Initializing %u h2drings\n", __FUNCTION__,
++			max_h2d_rings));
++		if ((ret = dhd_flow_rings_init(&dhd->pub, max_h2d_rings)) != BCME_OK) {
++			dhd_os_sdunlock(dhdp);
++			DHD_PERIM_UNLOCK(dhdp);
++			return ret;
++		}
++	}
++#endif /* PCIE_FULL_DONGLE */
++
++	/* Do protocol initialization necessary for IOCTL/IOVAR */
++#ifdef PCIE_FULL_DONGLE
++	dhd_os_sdunlock(dhdp);
++#endif /* PCIE_FULL_DONGLE */
++	ret = dhd_prot_init(&dhd->pub);
++	if (unlikely(ret) != BCME_OK) {
++		DHD_PERIM_UNLOCK(dhdp);
++		return ret;
++	}
++#ifdef PCIE_FULL_DONGLE
++	dhd_os_sdlock(dhdp);
++#endif /* PCIE_FULL_DONGLE */
++
++	/* If bus is not ready, can't come up */
++	if (dhd->pub.busstate != DHD_BUS_DATA) {
++		DHD_GENERAL_LOCK(&dhd->pub, flags);
++		dhd->wd_timer_valid = FALSE;
++		DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++		del_timer_sync(&dhd->timer);
++		DHD_ERROR(("%s failed bus is not ready\n", __FUNCTION__));
++		dhd_os_sdunlock(dhdp);
++		DHD_PERIM_UNLOCK(dhdp);
++		return -ENODEV;
++	}
++
++	dhd_os_sdunlock(dhdp);
++
++	/* Bus is ready, query any dongle information */
++	if ((ret = dhd_sync_with_dongle(&dhd->pub)) < 0) {
++		DHD_GENERAL_LOCK(&dhd->pub, flags);
++		dhd->wd_timer_valid = FALSE;
++		DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++		del_timer_sync(&dhd->timer);
++		DHD_ERROR(("%s failed to sync with dongle\n", __FUNCTION__));
++		DHD_PERIM_UNLOCK(dhdp);
++		return ret;
++	}
++
++#ifdef ARP_OFFLOAD_SUPPORT
++	if (dhd->pend_ipaddr) {
++#ifdef AOE_IP_ALIAS_SUPPORT
++		aoe_update_host_ipv4_table(&dhd->pub, dhd->pend_ipaddr, TRUE, 0);
++#endif /* AOE_IP_ALIAS_SUPPORT */
++		dhd->pend_ipaddr = 0;
++	}
++#endif /* ARP_OFFLOAD_SUPPORT */
++
++#if defined(TRAFFIC_MGMT_DWM)
++	bzero(&dhd->pub.dhd_tm_dwm_tbl, sizeof(dhd_trf_mgmt_dwm_tbl_t));
++#endif 
++	DHD_PERIM_UNLOCK(dhdp);
++	return 0;
++}
++#endif /* BCMDBUS */
++#ifdef WLTDLS
++int _dhd_tdls_enable(dhd_pub_t *dhd, bool tdls_on, bool auto_on, struct ether_addr *mac)
++{
++	uint32 tdls = tdls_on;
++	int ret = 0;
++	uint32 tdls_auto_op = 0;
++	uint32 tdls_idle_time = CUSTOM_TDLS_IDLE_MODE_SETTING;
++	int32 tdls_rssi_high = CUSTOM_TDLS_RSSI_THRESHOLD_HIGH;
++	int32 tdls_rssi_low = CUSTOM_TDLS_RSSI_THRESHOLD_LOW;
++	BCM_REFERENCE(mac);
++	if (!FW_SUPPORTED(dhd, tdls))
++		return BCME_ERROR;
++
++	if (dhd->tdls_enable == tdls_on)
++		goto auto_mode;
++	ret = dhd_iovar(dhd, 0, "tdls_enable", (char *)&tdls, sizeof(tdls), NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: tdls %d failed %d\n", __FUNCTION__, tdls, ret));
++		goto exit;
++	}
++	dhd->tdls_enable = tdls_on;
++auto_mode:
++
++	tdls_auto_op = auto_on;
++	ret = dhd_iovar(dhd, 0, "tdls_auto_op", (char *)&tdls_auto_op, sizeof(tdls_auto_op), NULL,
++			0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s: tdls_auto_op failed %d\n", __FUNCTION__, ret));
++		goto exit;
++	}
++
++	if (tdls_auto_op) {
++		ret = dhd_iovar(dhd, 0, "tdls_idle_time", (char *)&tdls_idle_time,
++				sizeof(tdls_idle_time), NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s: tdls_idle_time failed %d\n", __FUNCTION__, ret));
++			goto exit;
++		}
++		ret = dhd_iovar(dhd, 0, "tdls_rssi_high", (char *)&tdls_rssi_high,
++				sizeof(tdls_rssi_high), NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s: tdls_rssi_high failed %d\n", __FUNCTION__, ret));
++			goto exit;
++		}
++		ret = dhd_iovar(dhd, 0, "tdls_rssi_low", (char *)&tdls_rssi_low,
++				sizeof(tdls_rssi_low), NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s: tdls_rssi_low failed %d\n", __FUNCTION__, ret));
++			goto exit;
++		}
++	}
++
++exit:
++	return ret;
++}
++int dhd_tdls_enable(struct net_device *dev, bool tdls_on, bool auto_on, struct ether_addr *mac)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret = 0;
++	if (dhd)
++		ret = _dhd_tdls_enable(&dhd->pub, tdls_on, auto_on, mac);
++	else
++		ret = BCME_ERROR;
++	return ret;
++}
++int
++dhd_tdls_set_mode(dhd_pub_t *dhd, bool wfd_mode)
++{
++	int ret = 0;
++	bool auto_on = false;
++	uint32 mode =  wfd_mode;
++
++	auto_on = false;
++	ret = _dhd_tdls_enable(dhd, false, auto_on, NULL);
++	if (ret < 0) {
++		DHD_ERROR(("Disable tdls_auto_op failed. %d\n", ret));
++		return ret;
++	}
++
++	ret = dhd_iovar(dhd, 0, "tdls_wfd_mode", (char *)&mode, sizeof(mode), NULL, 0, TRUE);
++	if ((ret < 0) && (ret != BCME_UNSUPPORTED)) {
++		DHD_ERROR(("%s: tdls_wfd_mode faile_wfd_mode %d\n", __FUNCTION__, ret));
++		return ret;
++	}
++
++	ret = _dhd_tdls_enable(dhd, true, auto_on, NULL);
++	if (ret < 0) {
++		DHD_ERROR(("enable tdls_auto_op failed. %d\n", ret));
++		return ret;
++	}
++
++	dhd->tdls_mode = mode;
++	return ret;
++}
++#ifdef PCIE_FULL_DONGLE
++void dhd_tdls_update_peer_info(struct net_device *dev, bool connect, uint8 *da)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	dhd_pub_t *dhdp =  (dhd_pub_t *)&dhd->pub;
++	tdls_peer_node_t *cur = dhdp->peer_tbl.node;
++	tdls_peer_node_t *new = NULL, *prev = NULL;
++	dhd_if_t *dhdif;
++	uint8 sa[ETHER_ADDR_LEN];
++	int ifidx = dhd_net2idx(dhd, dev);
++
++	if (ifidx == DHD_BAD_IF)
++		return;
++
++	dhdif = dhd->iflist[ifidx];
++	memcpy(sa, dhdif->mac_addr, ETHER_ADDR_LEN);
++
++	if (connect) {
++		while (cur != NULL) {
++			if (!memcmp(da, cur->addr, ETHER_ADDR_LEN)) {
++				DHD_ERROR(("%s: TDLS Peer exist already %d\n",
++					__FUNCTION__, __LINE__));
++				return;
++			}
++			cur = cur->next;
++		}
++
++		new = MALLOC(dhdp->osh, sizeof(tdls_peer_node_t));
++		if (new == NULL) {
++			DHD_ERROR(("%s: Failed to allocate memory\n", __FUNCTION__));
++			return;
++		}
++		memcpy(new->addr, da, ETHER_ADDR_LEN);
++		new->next = dhdp->peer_tbl.node;
++		dhdp->peer_tbl.node = new;
++		dhdp->peer_tbl.tdls_peer_count++;
++
++	} else {
++		while (cur != NULL) {
++			if (!memcmp(da, cur->addr, ETHER_ADDR_LEN)) {
++				dhd_flow_rings_delete_for_peer(dhdp, ifidx, da);
++				if (prev)
++					prev->next = cur->next;
++				else
++					dhdp->peer_tbl.node = cur->next;
++				MFREE(dhdp->osh, cur, sizeof(tdls_peer_node_t));
++				dhdp->peer_tbl.tdls_peer_count--;
++				return;
++			}
++			prev = cur;
++			cur = cur->next;
++		}
++		DHD_ERROR(("%s: TDLS Peer Entry Not found\n", __FUNCTION__));
++	}
++}
++#endif /* PCIE_FULL_DONGLE */
++#endif /* BCMDBUS */
++
++bool dhd_is_concurrent_mode(dhd_pub_t *dhd)
++{
++	if (!dhd)
++		return FALSE;
++
++	if (dhd->op_mode & DHD_FLAG_CONCURR_MULTI_CHAN_MODE)
++		return TRUE;
++	else if ((dhd->op_mode & DHD_FLAG_CONCURR_SINGLE_CHAN_MODE) ==
++		DHD_FLAG_CONCURR_SINGLE_CHAN_MODE)
++		return TRUE;
++	else
++		return FALSE;
++}
++#if !defined(AP) && defined(WLP2P)
++/* From Android JerryBean release, the concurrent mode is enabled by default and the firmware
++ * name would be fw_bcmdhd.bin. So we need to determine whether P2P is enabled in the STA
++ * firmware and accordingly enable concurrent mode (Apply P2P settings). SoftAP firmware
++ * would still be named as fw_bcmdhd_apsta.
++ */
++uint32
++dhd_get_concurrent_capabilites(dhd_pub_t *dhd)
++{
++	int32 ret = 0;
++	char buf[WLC_IOCTL_SMLEN];
++	bool mchan_supported = FALSE;
++	/* if dhd->op_mode is already set for HOSTAP and Manufacturing
++	 * test mode, that means we only will use the mode as it is
++	 */
++	if (dhd->op_mode & (DHD_FLAG_HOSTAP_MODE | DHD_FLAG_MFG_MODE))
++		return 0;
++	if (FW_SUPPORTED(dhd, vsdb)) {
++		mchan_supported = TRUE;
++	}
++	if (!FW_SUPPORTED(dhd, p2p)) {
++		DHD_TRACE(("Chip does not support p2p\n"));
++		return 0;
++	} else {
++		/* Chip supports p2p but ensure that p2p is really implemented in firmware or not */
++		memset(buf, 0, sizeof(buf));
++		ret = dhd_iovar(dhd, 0, "p2p", NULL, 0, (char *)&buf,
++				sizeof(buf), FALSE);
++		if (ret < 0) {
++			DHD_ERROR(("%s: Get P2P failed (error=%d)\n", __FUNCTION__, ret));
++			return 0;
++		} else {
++			if (buf[0] == 1) {
++				/* By default, chip supports single chan concurrency,
++				* now lets check for mchan
++				*/
++				ret = DHD_FLAG_CONCURR_SINGLE_CHAN_MODE;
++				if (mchan_supported)
++					ret |= DHD_FLAG_CONCURR_MULTI_CHAN_MODE;
++				if (FW_SUPPORTED(dhd, rsdb)) {
++					ret |= DHD_FLAG_RSDB_MODE;
++				}
++				if (FW_SUPPORTED(dhd, mp2p)) {
++					ret |= DHD_FLAG_MP2P_MODE;
++				}
++#if defined(WL_ENABLE_P2P_IF) || defined(WL_CFG80211_P2P_DEV_IF)
++				/* For customer_hw4, although ICS,
++				* we still support concurrent mode
++				*/
++				return ret;
++#else
++				return 0;
++#endif 
++			}
++		}
++	}
++	return 0;
++}
++#endif 
++
++#ifdef SUPPORT_AP_POWERSAVE
++#define RXCHAIN_PWRSAVE_PPS			10
++#define RXCHAIN_PWRSAVE_QUIET_TIME		10
++#define RXCHAIN_PWRSAVE_STAS_ASSOC_CHECK	0
++int dhd_set_ap_powersave(dhd_pub_t *dhdp, int ifidx, int enable)
++{
++	char iovbuf[128];
++	int32 pps = RXCHAIN_PWRSAVE_PPS;
++	int32 quiet_time = RXCHAIN_PWRSAVE_QUIET_TIME;
++	int32 stas_assoc_check = RXCHAIN_PWRSAVE_STAS_ASSOC_CHECK;
++	int ret;
++
++	if (enable) {
++		ret = dhd_iovar(dhdp, 0, "rxchain_pwrsave_enable", (char *)&enable, sizeof(enable),
++				NULL, 0, TRUE);
++		if (ret != BCME_OK) {
++			DHD_ERROR(("Failed to enable AP power save"));
++		}
++		ret = dhd_iovar(dhdp, 0, "rxchain_pwrsave_pps", (char *)&pps, sizeof(pps), NULL, 0,
++				TRUE);
++		if (ret != BCME_OK) {
++			DHD_ERROR(("Failed to set pps"));
++		}
++		ret = dhd_iovar(dhdp, 0, "rxchain_pwrsave_quiet_time", (char *)&quiet_time,
++				sizeof(quiet_time), NULL, 0, TRUE);
++		if (ret != BCME_OK) {
++			DHD_ERROR(("Failed to set quiet time"));
++		}
++		ret = dhd_iovar(dhdp., 0, "rxchain_pwrsave_stas_assoc_check",
++				(char *)&stas_assoc_check, sizeof(stas_assoc_check), NULL, 0, TRUE);
++		if (ret != BCME_OK) {
++			DHD_ERROR(("Failed to set stas assoc check"));
++		}
++	} else {
++		ret = dhd_iovar(dhdp, 0, "rxchain_pwrsave_enable", (char *)&enable, sizeof(enable),
++				NULL, 0, TRUE);
++		if (ret != BCME_OK) {
++			DHD_ERROR(("Failed to disable AP power save"));
++		}
++	}
++
++	return 0;
++}
++#endif /* SUPPORT_AP_POWERSAVE */
++
++
++int
++dhd_preinit_ioctls(dhd_pub_t *dhd)
++{
++	int ret = 0;
++	char eventmask[WL_EVENTING_MASK_LEN];
++	char iovbuf[WL_EVENTING_MASK_LEN + 12]; /*  Room for "event_msgs" + '\0' + bitvec  */
++	uint32 buf_key_b4_m4 = 1;
++	uint8 msglen;
++	eventmsgs_ext_t *eventmask_msg = NULL;
++	char* iov_buf = NULL;
++	int ret2 = 0;
++#if defined(CUSTOM_AMPDU_BA_WSIZE)
++	uint32 ampdu_ba_wsize = 0;
++#endif 
++#if defined(CUSTOM_AMPDU_MPDU)
++	int32 ampdu_mpdu = 0;
++#endif
++#if defined(CUSTOM_AMPDU_RELEASE)
++	int32 ampdu_release = 0;
++#endif
++#if defined(CUSTOM_AMSDU_AGGSF)
++	int32 amsdu_aggsf = 0;
++#endif
++
++#if defined(BCMSDIO) || defined(BCMDBUS)
++#ifdef PROP_TXSTATUS
++	int wlfc_enable = TRUE;
++#ifndef DISABLE_11N
++	uint32 hostreorder = 1;
++#endif /* DISABLE_11N */
++#endif /* PROP_TXSTATUS */
++#endif /* defined(BCMSDIO) || defined(BCMDBUS) */
++#ifndef PCIE_FULL_DONGLE
++	uint32 wl_ap_isolate;
++#endif /* PCIE_FULL_DONGLE */
++
++#if defined(BCMSDIO) || defined(DISABLE_FRAMEBURST)
++	/* default frame burst enabled for PCIe, disabled for SDIO dongles and media targets */
++	uint32 frameburst = 0;
++#else
++	uint32 frameburst = 1;
++#endif /* BCMSDIO */
++
++#ifdef DHD_ENABLE_LPC
++	uint32 lpc = 1;
++#endif /* DHD_ENABLE_LPC */
++	uint power_mode = PM_FAST;
++#if defined(BCMSDIO)
++	uint32 dongle_align = DHD_SDALIGN;
++	uint32 glom = CUSTOM_GLOM_SETTING;
++#endif /* defined(BCMSDIO) */
++#if defined(CUSTOMER_HW2) && defined(USE_WL_CREDALL)
++	uint32 credall = 1;
++#endif
++#if defined(VSDB) || defined(ROAM_ENABLE)
++	uint bcn_timeout = CUSTOM_BCN_TIMEOUT;
++#else
++	uint bcn_timeout = 4;
++#endif 
++	uint retry_max = CUSTOM_ASSOC_RETRY_MAX;
++#if defined(ARP_OFFLOAD_SUPPORT)
++	int arpoe = 1;
++#endif
++	int scan_assoc_time = DHD_SCAN_ASSOC_ACTIVE_TIME;
++	int scan_unassoc_time = DHD_SCAN_UNASSOC_ACTIVE_TIME;
++	int scan_passive_time = DHD_SCAN_PASSIVE_TIME;
++	char buf[WLC_IOCTL_SMLEN];
++	char *ptr;
++	uint32 listen_interval = CUSTOM_LISTEN_INTERVAL; /* Default Listen Interval in Beacons */
++#ifdef ROAM_ENABLE
++	uint roamvar = 0;
++	int roam_trigger[2] = {CUSTOM_ROAM_TRIGGER_SETTING, WLC_BAND_ALL};
++	int roam_scan_period[2] = {10, WLC_BAND_ALL};
++	int roam_delta[2] = {CUSTOM_ROAM_DELTA_SETTING, WLC_BAND_ALL};
++#ifdef FULL_ROAMING_SCAN_PERIOD_60_SEC
++	int roam_fullscan_period = 60;
++#else /* FULL_ROAMING_SCAN_PERIOD_60_SEC */
++	int roam_fullscan_period = 120;
++#endif /* FULL_ROAMING_SCAN_PERIOD_60_SEC */
++#else
++#ifdef DISABLE_BUILTIN_ROAM
++	uint roamvar = 1;
++#endif /* DISABLE_BUILTIN_ROAM */
++#endif /* ROAM_ENABLE */
++
++#if defined(SOFTAP)
++	uint dtim = 1;
++#endif
++#if (defined(AP) && !defined(WLP2P)) || (!defined(AP) && defined(WL_CFG80211))
++	uint32 mpc = 0; /* Turn MPC off for AP/APSTA mode */
++	struct ether_addr p2p_ea;
++#endif
++#ifdef SOFTAP_UAPSD_OFF
++	uint32 wme_apsd = 0;
++#endif /* SOFTAP_UAPSD_OFF */
++#if (defined(AP) || defined(WLP2P)) && !defined(SOFTAP_AND_GC)
++	uint32 apsta = 1; /* Enable APSTA mode */
++#elif defined(SOFTAP_AND_GC)
++	uint32 apsta = 0;
++	int ap_mode = 1;
++#endif /* (defined(AP) || defined(WLP2P)) && !defined(SOFTAP_AND_GC) */
++#ifdef GET_CUSTOM_MAC_ENABLE
++	struct ether_addr ea_addr;
++#endif /* GET_CUSTOM_MAC_ENABLE */
++
++#ifdef DISABLE_11N
++	uint32 nmode = 0;
++#endif /* DISABLE_11N */
++
++#ifdef USE_WL_TXBF
++	uint32 txbf = 1;
++#endif /* USE_WL_TXBF */
++#ifdef DISABLE_TXBFR
++	uint32 txbf_bfr_cap = 0;
++#endif /* DISABLE_TXBFR */
++#if defined(PROP_TXSTATUS)
++#endif /* PROP_TXSTATUS */
++#ifdef CUSTOM_PSPRETEND_THR
++	uint32 pspretend_thr = CUSTOM_PSPRETEND_THR;
++#endif
++	uint32 rsdb_mode = 0;
++#ifdef PKT_FILTER_SUPPORT
++	dhd_pkt_filter_enable = TRUE;
++#endif /* PKT_FILTER_SUPPORT */
++#ifdef WLTDLS
++	dhd->tdls_enable = FALSE;
++	dhd_tdls_set_mode(dhd, false);
++#endif /* WLTDLS */
++	dhd->suspend_bcn_li_dtim = CUSTOM_SUSPEND_BCN_LI_DTIM;
++	DHD_TRACE(("Enter %s\n", __FUNCTION__));
++	dhd->op_mode = 0;
++	if ((!op_mode && dhd_get_fw_mode(dhd->info) == DHD_FLAG_MFG_MODE) ||
++		(op_mode == DHD_FLAG_MFG_MODE)) {
++		/* Check and adjust IOCTL response timeout for Manufactring firmware */
++		dhd_os_set_ioctl_resp_timeout(MFG_IOCTL_RESP_TIMEOUT);
++		DHD_ERROR(("%s : Set IOCTL response time for Manufactring Firmware\n",
++			__FUNCTION__));
++	} else {
++		dhd_os_set_ioctl_resp_timeout(IOCTL_RESP_TIMEOUT);
++		DHD_INFO(("%s : Set IOCTL response time.\n", __FUNCTION__));
++	}
++#ifdef GET_CUSTOM_MAC_ENABLE
++	ret = wifi_platform_get_mac_addr(dhd->info->adapter, ea_addr.octet);
++	if (!ret) {
++		ret = dhd_iovar(dhd, 0, "cur_etheraddr", (char *)&ea_addr, ETHER_ADDR_LEN, NULL, 0,
++				TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s: can't set MAC address , error=%d\n", __FUNCTION__, ret));
++			ret = BCME_NOTUP;
++			goto done;
++		}
++		memcpy(dhd->mac.octet, ea_addr.octet, ETHER_ADDR_LEN);
++	} else {
++#endif /* GET_CUSTOM_MAC_ENABLE */
++		/* Get the default device MAC address directly from firmware */
++		ret = dhd_iovar(dhd, 0, "cur_etheraddr", NULL, 0, (char *)&buf, sizeof(buf), FALSE);
++		if (ret < 0) {
++			DHD_ERROR(("%s: can't get MAC address , error=%d\n", __FUNCTION__, ret));
++			ret = BCME_NOTUP;
++			goto done;
++		}
++		/* Update public MAC address after reading from Firmware */
++		memcpy(dhd->mac.octet, buf, ETHER_ADDR_LEN);
++
++#ifdef GET_CUSTOM_MAC_ENABLE
++	}
++#endif /* GET_CUSTOM_MAC_ENABLE */
++
++	/* get a capabilities from firmware */
++	{
++		uint32 cap_buf_size = sizeof(dhd->fw_capabilities);
++		memset(dhd->fw_capabilities, 0, cap_buf_size);
++		ret = dhd_iovar(dhd, 0, "cap", NULL, 0, dhd->fw_capabilities, (cap_buf_size - 1),
++				FALSE);
++		if (ret < 0) {
++			DHD_ERROR(("%s: Get Capability failed (error=%d)\n",
++				__FUNCTION__, ret));
++			return 0;
++		}
++
++		memmove(&dhd->fw_capabilities[1], dhd->fw_capabilities, (cap_buf_size - 1));
++		dhd->fw_capabilities[0] = ' ';
++		dhd->fw_capabilities[cap_buf_size - 2] = ' ';
++		dhd->fw_capabilities[cap_buf_size - 1] = '\0';
++	}
++
++	if ((!op_mode && dhd_get_fw_mode(dhd->info) == DHD_FLAG_HOSTAP_MODE) ||
++		(op_mode == DHD_FLAG_HOSTAP_MODE)) {
++#ifdef SET_RANDOM_MAC_SOFTAP
++		uint rand_mac;
++#endif /* SET_RANDOM_MAC_SOFTAP */
++		dhd->op_mode = DHD_FLAG_HOSTAP_MODE;
++#if defined(ARP_OFFLOAD_SUPPORT)
++			arpoe = 0;
++#endif
++#ifdef PKT_FILTER_SUPPORT
++			dhd_pkt_filter_enable = FALSE;
++#endif
++#ifdef SET_RANDOM_MAC_SOFTAP
++		SRANDOM32((uint)jiffies);
++		rand_mac = RANDOM32();
++		iovbuf[0] = (unsigned char)(vendor_oui >> 16) | 0x02;	/* local admin bit */
++		iovbuf[1] = (unsigned char)(vendor_oui >> 8);
++		iovbuf[2] = (unsigned char)vendor_oui;
++		iovbuf[3] = (unsigned char)(rand_mac & 0x0F) | 0xF0;
++		iovbuf[4] = (unsigned char)(rand_mac >> 8);
++		iovbuf[5] = (unsigned char)(rand_mac >> 16);
++
++		ret = dhd_iovar(dhd, 0, "cur_etheraddr", (char *)&iovbuf, ETHER_ADDR_LEN, NULL, 0,
++				TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s: can't set MAC address , error=%d\n", __FUNCTION__, ret));
++		} else
++			memcpy(dhd->mac.octet, iovbuf, ETHER_ADDR_LEN);
++#endif /* SET_RANDOM_MAC_SOFTAP */
++#if !defined(AP) && defined(WL_CFG80211)
++		/* Turn off MPC in AP mode */
++		ret = dhd_iovar(dhd, 0, "mpc", (char *)&mpc, sizeof(mpc), NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s mpc for HostAPD failed  %d\n", __FUNCTION__, ret));
++		}
++#endif
++#ifdef SUPPORT_AP_POWERSAVE
++		dhd_set_ap_powersave(dhd, 0, TRUE);
++#endif /* SUPPORT_AP_POWERSAVE */
++#ifdef SOFTAP_UAPSD_OFF
++		ret = dhd_iovar(dhd, 0, "wme_apsd", (char *)&wme_apsd, sizeof(wme_apsd), NULL, 0,
++				TRUE);
++		if (ret < 0) {
++				DHD_ERROR(("%s: set wme_apsd 0 fail (error=%d)\n",
++				__FUNCTION__, ret));
++		}
++#endif /* SOFTAP_UAPSD_OFF */
++	} else if ((!op_mode && dhd_get_fw_mode(dhd->info) == DHD_FLAG_MFG_MODE) ||
++		(op_mode == DHD_FLAG_MFG_MODE)) {
++#if defined(ARP_OFFLOAD_SUPPORT)
++		arpoe = 0;
++#endif /* ARP_OFFLOAD_SUPPORT */
++#ifdef PKT_FILTER_SUPPORT
++		dhd_pkt_filter_enable = FALSE;
++#endif /* PKT_FILTER_SUPPORT */
++		dhd->op_mode = DHD_FLAG_MFG_MODE;
++		if (FW_SUPPORTED(dhd, rsdb)) {
++			rsdb_mode = 0;
++			ret = dhd_iovar(dhd, 0, "rsdb_mode", (char *)&rsdb_mode, sizeof(rsdb_mode),
++					NULL, 0, TRUE);
++			if (ret < 0) {
++				DHD_ERROR(("%s Disable rsdb_mode is failed ret= %d\n",
++					__FUNCTION__, ret));
++			}
++		}
++	} else {
++		uint32 concurrent_mode = 0;
++		if ((!op_mode && dhd_get_fw_mode(dhd->info) == DHD_FLAG_P2P_MODE) ||
++			(op_mode == DHD_FLAG_P2P_MODE)) {
++#if defined(ARP_OFFLOAD_SUPPORT)
++			arpoe = 0;
++#endif
++#ifdef PKT_FILTER_SUPPORT
++			dhd_pkt_filter_enable = FALSE;
++#endif
++			dhd->op_mode = DHD_FLAG_P2P_MODE;
++		} else if ((!op_mode && dhd_get_fw_mode(dhd->info) == DHD_FLAG_IBSS_MODE) ||
++			(op_mode == DHD_FLAG_IBSS_MODE)) {
++			dhd->op_mode = DHD_FLAG_IBSS_MODE;
++		} else
++			dhd->op_mode = DHD_FLAG_STA_MODE;
++#if !defined(AP) && defined(WLP2P)
++		if (dhd->op_mode != DHD_FLAG_IBSS_MODE &&
++			(concurrent_mode = dhd_get_concurrent_capabilites(dhd))) {
++#if defined(ARP_OFFLOAD_SUPPORT)
++			arpoe = 1;
++#endif
++			dhd->op_mode |= concurrent_mode;
++		}
++
++		/* Check if we are enabling p2p */
++		if (dhd->op_mode & DHD_FLAG_P2P_MODE) {
++			ret = dhd_iovar(dhd, 0, "apsta", (char *)&apsta, sizeof(apsta), NULL, 0,
++					TRUE);
++			if (ret < 0)
++				DHD_ERROR(("%s APSTA for P2P failed ret= %d\n", __FUNCTION__, ret));
++
++#if defined(SOFTAP_AND_GC)
++		if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_SET_AP,
++			(char *)&ap_mode, sizeof(ap_mode), TRUE, 0)) < 0) {
++				DHD_ERROR(("%s WLC_SET_AP failed %d\n", __FUNCTION__, ret));
++		}
++#endif
++			memcpy(&p2p_ea, &dhd->mac, ETHER_ADDR_LEN);
++			ETHER_SET_LOCALADDR(&p2p_ea);
++			ret = dhd_iovar(dhd, 0, "p2p_da_override", (char *)&p2p_ea, sizeof(p2p_ea),
++					NULL, 0, TRUE);
++			if (ret < 0)
++				DHD_ERROR(("%s p2p_da_override ret= %d\n", __FUNCTION__, ret));
++			else
++				DHD_INFO(("dhd_preinit_ioctls: p2p_da_override succeeded\n"));
++		}
++#else
++	(void)concurrent_mode;
++#endif 
++	}
++
++	DHD_ERROR(("Firmware up: op_mode=0x%04x, MAC="MACDBG"\n",
++		dhd->op_mode, MAC2STRDBG(dhd->mac.octet)));
++	#if defined(RXFRAME_THREAD) && defined(RXTHREAD_ONLYSTA)
++	if (dhd->op_mode == DHD_FLAG_HOSTAP_MODE)
++		dhd->info->rxthread_enabled = FALSE;
++	else
++		dhd->info->rxthread_enabled = TRUE;
++	#endif
++	/* Set Country code  */
++	if (dhd->dhd_cspec.ccode[0] != 0) {
++		ret = dhd_iovar(dhd, 0, "country", (char *)&dhd->dhd_cspec, sizeof(wl_country_t),
++				NULL, 0, TRUE);
++		if (ret < 0)
++			DHD_ERROR(("%s: country code setting failed\n", __FUNCTION__));
++	}
++
++
++	/* Set Listen Interval */
++	ret = dhd_iovar(dhd, 0, "assoc_listen", (char *)&listen_interval, sizeof(listen_interval),
++			NULL, 0, TRUE);
++	if (ret < 0)
++		DHD_ERROR(("%s assoc_listen failed %d\n", __FUNCTION__, ret));
++
++#if defined(ROAM_ENABLE) || defined(DISABLE_BUILTIN_ROAM)
++	/* Disable built-in roaming to allowed ext supplicant to take care of roaming */
++	dhd_iovar(dhd, 0, "roam_off", (char *)&roamvar, sizeof(roamvar), NULL, 0, TRUE);
++#endif /* ROAM_ENABLE || DISABLE_BUILTIN_ROAM */
++#if defined(ROAM_ENABLE)
++	if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_SET_ROAM_TRIGGER, roam_trigger,
++		sizeof(roam_trigger), TRUE, 0)) < 0)
++		DHD_ERROR(("%s: roam trigger set failed %d\n", __FUNCTION__, ret));
++	if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_SET_ROAM_SCAN_PERIOD, roam_scan_period,
++		sizeof(roam_scan_period), TRUE, 0)) < 0)
++		DHD_ERROR(("%s: roam scan period set failed %d\n", __FUNCTION__, ret));
++	if ((dhd_wl_ioctl_cmd(dhd, WLC_SET_ROAM_DELTA, roam_delta,
++		sizeof(roam_delta), TRUE, 0)) < 0)
++		DHD_ERROR(("%s: roam delta set failed %d\n", __FUNCTION__, ret));
++	if ((ret = dhd_iovar(dhd, 0, "fullroamperiod", (char *)&roam_fullscan_period,
++		sizeof(roam_fullscan_period), NULL, 0, TRUE)) < 0)
++		DHD_ERROR(("%s: roam fullscan period set failed %d\n", __FUNCTION__, ret));
++#endif /* ROAM_ENABLE */
++
++#ifdef WLTDLS
++	/* by default TDLS on and auto mode off */
++	_dhd_tdls_enable(dhd, true, false, NULL);
++#endif /* WLTDLS */
++
++#ifdef DHD_ENABLE_LPC
++	/* Set lpc 1 */
++	ret = dhd_iovar(dhd, 0, "lpc", (char *)&lpc, sizeof(lpc), NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s Set lpc failed  %d\n", __FUNCTION__, ret));
++	}
++#endif /* DHD_ENABLE_LPC */
++
++	/* Set PowerSave mode */
++	dhd_wl_ioctl_cmd(dhd, WLC_SET_PM, (char *)&power_mode, sizeof(power_mode), TRUE, 0);
++
++#if defined(BCMSDIO)
++	/* Match Host and Dongle rx alignment */
++	dhd_iovar(dhd, 0, "bus:txglomalign", (char *)&dongle_align, sizeof(dongle_align),
++			NULL, 0, TRUE);
++
++#if defined(CUSTOMER_HW2) && defined(USE_WL_CREDALL)
++	/* enable credall to reduce the chance of no bus credit happened. */
++	dhd_iovar(dhd, 0, "bus:credall", (char *)&credall, sizeof(credall), NULL, 0, TRUE);
++#endif
++
++	if (glom != DEFAULT_GLOM_VALUE) {
++		DHD_INFO(("%s set glom=0x%X\n", __FUNCTION__, glom));
++		dhd_iovar(dhd, 0, "bus:txglom", (char *)&glom, sizeof(glom), NULL, 0, TRUE);
++	}
++#endif /* defined(BCMSDIO) */
++
++	/* Setup timeout if Beacons are lost and roam is off to report link down */
++	dhd_iovar(dhd, 0, "bcn_timeout", (char *)&bcn_timeout, sizeof(bcn_timeout), NULL, 0, TRUE);
++	/* Setup assoc_retry_max count to reconnect target AP in dongle */
++	dhd_iovar(dhd, 0, "assoc_retry_max", (char *)&retry_max, sizeof(retry_max), NULL, 0, TRUE);
++#if defined(AP) && !defined(WLP2P)
++	/* Turn off MPC in AP mode */
++	dhd_iovar(dhd, 0, "mpc", (char *)&mpc, sizeof(mpc), NULL, 0, TRUE);
++	dhd_iovar(dhd, 0, "apsta", (char *)&apsta, sizeof(apsta), NULL, 0, TRUE);
++#endif /* defined(AP) && !defined(WLP2P) */
++
++
++#if defined(SOFTAP)
++	if (ap_fw_loaded == TRUE) {
++		dhd_wl_ioctl_cmd(dhd, WLC_SET_DTIMPRD, (char *)&dtim, sizeof(dtim), TRUE, 0);
++	}
++#endif 
++
++#if defined(KEEP_ALIVE)
++	{
++	/* Set Keep Alive : be sure to use FW with -keepalive */
++	int res;
++
++#if defined(SOFTAP)
++	if (ap_fw_loaded == FALSE)
++#endif 
++		if (!(dhd->op_mode &
++			(DHD_FLAG_HOSTAP_MODE | DHD_FLAG_MFG_MODE))) {
++			if ((res = dhd_keep_alive_onoff(dhd)) < 0)
++				DHD_ERROR(("%s set keeplive failed %d\n",
++				__FUNCTION__, res));
++		}
++	}
++#endif /* defined(KEEP_ALIVE) */
++
++	if ((ret = dhd_apply_default_clm(dhd, clm_path)) < 0) {
++		DHD_ERROR(("%s: CLM set failed. Abort initialization.\n", __FUNCTION__));
++		goto done;
++	}
++
++#ifdef USE_WL_TXBF
++	if ((ret = dhd_iovar(dhd, 0, "txbf", (char *)&txbf, sizeof(txbf), NULL, 0, TRUE)) < 0) {
++		DHD_ERROR(("%s Set txbf failed  %d\n", __FUNCTION__, ret));
++	}
++#endif /* USE_WL_TXBF */
++#ifdef DISABLE_TXBFR
++	bcm_mkiovar("txbf_bfr_cap", (char *)&txbf_bfr_cap, 4, iovbuf, sizeof(iovbuf));
++	if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_SET_VAR, iovbuf,
++		sizeof(iovbuf), TRUE, 0)) < 0) {
++		DHD_ERROR(("%s Clear txbf_bfr_cap failed  %d\n", __FUNCTION__, ret));
++	}
++#endif /* DISABLE_TXBFR */
++#ifdef DISABLE_WL_FRAMEBURST_SOFTAP
++	/* Disable Framebursting for SofAP */
++	if (dhd->op_mode & DHD_FLAG_HOSTAP_MODE) {
++		frameburst = 0;
++	}
++#endif /* DISABLE_WL_FRAMEBURST_SOFTAP */
++/* Set frameburst to value */
++	if ((ret = dhd_wl_ioctl_cmd(dhd, WLC_SET_FAKEFRAG, (char *)&frameburst,
++		sizeof(frameburst), TRUE, 0)) < 0) {
++		DHD_INFO(("%s frameburst not supported  %d\n", __FUNCTION__, ret));
++	}
++#if defined(CUSTOM_AMPDU_BA_WSIZE)
++	/* Set ampdu ba wsize to 64 or 16 */
++#ifdef CUSTOM_AMPDU_BA_WSIZE
++	ampdu_ba_wsize = CUSTOM_AMPDU_BA_WSIZE;
++#endif
++	if (ampdu_ba_wsize != 0) {
++		ret = dhd_iovar(dhd, 0, "ampdu_ba_wsize", (char *)&ampdu_ba_wsize,
++				sizeof(ampdu_ba_wsize), NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s Set ampdu_ba_wsize to %d failed  %d\n",
++				__FUNCTION__, ampdu_ba_wsize, ret));
++		}
++	}
++#endif 
++
++	iov_buf = (char*)kmalloc(WLC_IOCTL_SMLEN, GFP_KERNEL);
++	if (iov_buf == NULL) {
++		DHD_ERROR(("failed to allocate %d bytes for iov_buf\n", WLC_IOCTL_SMLEN));
++		ret = BCME_NOMEM;
++		goto done;
++	}
++
++#if defined(CUSTOM_AMPDU_MPDU)
++	ampdu_mpdu = CUSTOM_AMPDU_MPDU;
++	if (ampdu_mpdu != 0 && (ampdu_mpdu <= ampdu_ba_wsize)) {
++		ret = dhd_iovar(dhd, 0, "ampdu_mpdu", (char *)&ampdu_mpdu, sizeof(ampdu_mpdu),
++				NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s Set ampdu_mpdu to %d failed  %d\n",
++				__FUNCTION__, CUSTOM_AMPDU_MPDU, ret));
++		}
++	}
++#endif /* CUSTOM_AMPDU_MPDU */
++
++#if defined(CUSTOM_AMPDU_RELEASE)
++	ampdu_release = CUSTOM_AMPDU_RELEASE;
++	if (ampdu_release != 0 && (ampdu_release <= ampdu_ba_wsize)) {
++		ret = dhd_iovar(dhd, 0, "ampdu_release", (char *)&ampdu_release,
++				sizeof(ampdu_release), NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s Set ampdu_release to %d failed  %d\n",
++				__FUNCTION__, CUSTOM_AMPDU_RELEASE, ret));
++		}
++	}
++#endif /* CUSTOM_AMPDU_RELEASE */
++
++#if defined(CUSTOM_AMSDU_AGGSF)
++	amsdu_aggsf = CUSTOM_AMSDU_AGGSF;
++	if (amsdu_aggsf != 0) {
++		ret = dhd_iovar(dhd, 0, "amsdu_aggsf", (char *)&amsdu_aggsf, sizeof(amsdu_aggsf),
++				NULL, 0, TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s Set amsdu_aggsf to %d failed %d\n",
++				__FUNCTION__, CUSTOM_AMSDU_AGGSF, ret));
++		}
++	}
++#endif /* CUSTOM_AMSDU_AGGSF */
++
++#ifdef CUSTOM_PSPRETEND_THR
++	/* Turn off MPC in AP mode */
++	if ((ret = dhd_iovar(dhd, 0, "pspretend_threshold", (char *)&pspretend_thr,
++		sizeof(pspretend_thr), NULL, 0, TRUE)) < 0) {
++		DHD_ERROR(("%s pspretend_threshold for HostAPD failed  %d\n",
++			__FUNCTION__, ret));
++	}
++#endif
++
++	if ((ret = dhd_iovar(dhd, 0, "buf_key_b4_m4", (char *)&buf_key_b4_m4,
++		sizeof(buf_key_b4_m4), NULL, 0, TRUE)) < 0) {
++		DHD_ERROR(("%s buf_key_b4_m4 set failed %d\n", __FUNCTION__, ret));
++	}
++
++	/* Read event_msgs mask */
++	ret = dhd_iovar(dhd, 0, "event_msgs", eventmask, WL_EVENTING_MASK_LEN, iovbuf,
++			sizeof(iovbuf), FALSE);
++	if (ret < 0) {
++		DHD_ERROR(("%s read Event mask failed %d\n", __FUNCTION__, ret));
++		goto done;
++	}
++	memcpy(eventmask, iovbuf, WL_EVENTING_MASK_LEN);
++
++	/* Setup event_msgs */
++	setbit(eventmask, WLC_E_SET_SSID);
++	setbit(eventmask, WLC_E_PRUNE);
++	setbit(eventmask, WLC_E_AUTH);
++	setbit(eventmask, WLC_E_AUTH_IND);
++	setbit(eventmask, WLC_E_ASSOC);
++	setbit(eventmask, WLC_E_REASSOC);
++	setbit(eventmask, WLC_E_REASSOC_IND);
++	if (!(dhd->op_mode & DHD_FLAG_IBSS_MODE))
++		setbit(eventmask, WLC_E_DEAUTH);
++	setbit(eventmask, WLC_E_DEAUTH_IND);
++	setbit(eventmask, WLC_E_DISASSOC_IND);
++	setbit(eventmask, WLC_E_DISASSOC);
++	setbit(eventmask, WLC_E_JOIN);
++	setbit(eventmask, WLC_E_START);
++	setbit(eventmask, WLC_E_ASSOC_IND);
++	setbit(eventmask, WLC_E_PSK_SUP);
++	setbit(eventmask, WLC_E_LINK);
++	setbit(eventmask, WLC_E_MIC_ERROR);
++	setbit(eventmask, WLC_E_ASSOC_REQ_IE);
++	setbit(eventmask, WLC_E_ASSOC_RESP_IE);
++#ifdef LIMIT_BORROW
++	setbit(eventmask, WLC_E_ALLOW_CREDIT_BORROW);
++#endif
++#ifndef WL_CFG80211
++	setbit(eventmask, WLC_E_PMKID_CACHE);
++	setbit(eventmask, WLC_E_TXFAIL);
++#endif
++	setbit(eventmask, WLC_E_JOIN_START);
++	setbit(eventmask, WLC_E_SCAN_COMPLETE);
++#ifdef DHD_DEBUG
++	setbit(eventmask, WLC_E_SCAN_CONFIRM_IND);
++#endif
++#ifdef WLMEDIA_HTSF
++	setbit(eventmask, WLC_E_HTSFSYNC);
++#endif /* WLMEDIA_HTSF */
++#ifdef PNO_SUPPORT
++	setbit(eventmask, WLC_E_PFN_NET_FOUND);
++	setbit(eventmask, WLC_E_PFN_BEST_BATCHING);
++	setbit(eventmask, WLC_E_PFN_BSSID_NET_FOUND);
++	setbit(eventmask, WLC_E_PFN_BSSID_NET_LOST);
++#endif /* PNO_SUPPORT */
++	/* enable dongle roaming event */
++	setbit(eventmask, WLC_E_ROAM);
++	setbit(eventmask, WLC_E_BSSID);
++#ifdef WLTDLS
++	setbit(eventmask, WLC_E_TDLS_PEER_EVENT);
++#endif /* WLTDLS */
++#ifdef RTT_SUPPORT
++	setbit(eventmask, WLC_E_PROXD);
++#endif /* RTT_SUPPORT */
++#ifdef WL_CFG80211
++	setbit(eventmask, WLC_E_ESCAN_RESULT);
++	if (dhd->op_mode & DHD_FLAG_P2P_MODE) {
++		setbit(eventmask, WLC_E_ACTION_FRAME_RX);
++		setbit(eventmask, WLC_E_P2P_DISC_LISTEN_COMPLETE);
++	}
++#endif /* WL_CFG80211 */
++	setbit(eventmask, WLC_E_TRACE);
++	setbit(eventmask, WLC_E_CSA_COMPLETE_IND);
++#ifdef DHD_LOSSLESS_ROAMING
++	setbit(eventmask, WLC_E_ROAM_PREP);
++#endif
++#ifdef DHD_WMF
++	setbit(eventmask, WLC_E_PSTA_PRIMARY_INTF_IND);
++#endif
++#if defined(PCIE_FULL_DONGLE) && defined(DHD_LOSSLESS_ROAMING)
++	dhd_update_flow_prio_map(dhd, DHD_FLOW_PRIO_LLR_MAP);
++#endif /* defined(PCIE_FULL_DONGLE) && defined(DHD_LOSSLESS_ROAMING) */
++
++	/* Write updated Event mask */
++	ret = dhd_iovar(dhd, 0, "event_msgs", eventmask, WL_EVENTING_MASK_LEN, NULL, 0, TRUE);
++	if (ret < 0) {
++		DHD_ERROR(("%s Set Event mask failed %d\n", __FUNCTION__, ret));
++		goto done;
++	}
++
++	/* make up event mask ext message iovar for event larger than 128 */
++	msglen = ROUNDUP(WLC_E_LAST, NBBY)/NBBY + EVENTMSGS_EXT_STRUCT_SIZE;
++	eventmask_msg = (eventmsgs_ext_t*)kmalloc(msglen, GFP_KERNEL);
++	if (eventmask_msg == NULL) {
++		DHD_ERROR(("failed to allocate %d bytes for event_msg_ext\n", msglen));
++		ret = BCME_NOMEM;
++		goto done;
++	}
++	bzero(eventmask_msg, msglen);
++	eventmask_msg->ver = EVENTMSGS_VER;
++	eventmask_msg->len = ROUNDUP(WLC_E_LAST, NBBY)/NBBY;
++
++	/* Read event_msgs_ext mask */
++	ret2 = dhd_iovar(dhd, 0, "event_msgs_ext", (char *)eventmask_msg, msglen, iov_buf,
++			WLC_IOCTL_SMLEN, FALSE);
++
++	if (ret2 != BCME_UNSUPPORTED)
++		ret = ret2;
++	if (ret2 == 0) { /* event_msgs_ext must be supported */
++		memcpy(eventmask_msg, iov_buf, msglen);
++#ifdef GSCAN_SUPPORT
++		setbit(eventmask_msg->mask, WLC_E_PFN_GSCAN_FULL_RESULT);
++		setbit(eventmask_msg->mask, WLC_E_PFN_SCAN_COMPLETE);
++		setbit(eventmask_msg->mask, WLC_E_PFN_SWC);
++		setbit(eventmask_msg->mask, WLC_E_PFN_SSID_EXT);
++		setbit(eventmask_msg->mask, WLC_E_ROAM_EXP_EVENT);
++#endif /* GSCAN_SUPPORT */
++		setbit(eventmask_msg->mask, WLC_E_RSSI_LQM);
++#ifdef BT_WIFI_HANDOVER
++		setbit(eventmask_msg->mask, WLC_E_BT_WIFI_HANDOVER_REQ);
++#endif /* BT_WIFI_HANDOVER */
++#ifdef DHD_ULP
++		setbit(eventmask_msg->mask, WLC_E_ULP);
++#endif
++
++		/* Write updated Event mask */
++		eventmask_msg->ver = EVENTMSGS_VER;
++		eventmask_msg->command = EVENTMSGS_SET_MASK;
++		eventmask_msg->len = ROUNDUP(WLC_E_LAST, NBBY)/NBBY;
++		ret = dhd_iovar(dhd, 0, "event_msgs_ext", (char *)eventmask_msg, msglen, NULL, 0,
++				TRUE);
++		if (ret < 0) {
++			DHD_ERROR(("%s write event mask ext failed %d\n", __FUNCTION__, ret));
++			goto done;
++		}
++	} else if (ret2 < 0 && ret2 == BCME_VERSION) {
++		DHD_ERROR(("%s Different Event version\n", __FUNCTION__));
++	} else if (ret2 < 0 && ret2 != BCME_UNSUPPORTED) {
++		DHD_ERROR(("%s read event mask ext failed %d\n", __FUNCTION__, ret2));
++		goto done;
++	} /* unsupported is ok */
++
++	dhd_wl_ioctl_cmd(dhd, WLC_SET_SCAN_CHANNEL_TIME, (char *)&scan_assoc_time,
++		sizeof(scan_assoc_time), TRUE, 0);
++	dhd_wl_ioctl_cmd(dhd, WLC_SET_SCAN_UNASSOC_TIME, (char *)&scan_unassoc_time,
++		sizeof(scan_unassoc_time), TRUE, 0);
++	dhd_wl_ioctl_cmd(dhd, WLC_SET_SCAN_PASSIVE_TIME, (char *)&scan_passive_time,
++		sizeof(scan_passive_time), TRUE, 0);
++
++#ifdef ARP_OFFLOAD_SUPPORT
++	/* Set and enable ARP offload feature for STA only  */
++#if defined(SOFTAP)
++	if (arpoe && !ap_fw_loaded) {
++#else
++	if (arpoe) {
++#endif 
++		dhd_arp_offload_enable(dhd, TRUE);
++		dhd_arp_offload_set(dhd, dhd_arp_mode);
++	} else {
++		dhd_arp_offload_enable(dhd, FALSE);
++		dhd_arp_offload_set(dhd, 0);
++	}
++	dhd_arp_enable = arpoe;
++#endif /* ARP_OFFLOAD_SUPPORT */
++
++#ifdef PKT_FILTER_SUPPORT
++	/* Setup default defintions for pktfilter , enable in suspend */
++	dhd->pktfilter_count = 6;
++	/* Setup filter to allow only unicast */
++	dhd->pktfilter[DHD_UNICAST_FILTER_NUM] = "100 0 0 0 0x01 0x00";
++	dhd->pktfilter[DHD_BROADCAST_FILTER_NUM] = NULL;
++	dhd->pktfilter[DHD_MULTICAST4_FILTER_NUM] = NULL;
++	dhd->pktfilter[DHD_MULTICAST6_FILTER_NUM] = NULL;
++	/* Add filter to pass multicastDNS packet and NOT filter out as Broadcast */
++	dhd->pktfilter[DHD_MDNS_FILTER_NUM] = "104 0 0 0 0xFFFFFFFFFFFF 0x01005E0000FB";
++	/* apply APP pktfilter */
++	dhd->pktfilter[DHD_ARP_FILTER_NUM] = "105 0 0 12 0xFFFF 0x0806";
++
++
++#if defined(SOFTAP)
++	if (ap_fw_loaded) {
++		dhd_enable_packet_filter(0, dhd);
++	}
++#endif /* defined(SOFTAP) */
++	dhd_set_packet_filter(dhd);
++#endif /* PKT_FILTER_SUPPORT */
++#ifdef DISABLE_11N
++	ret = dhd_iovar(dhd, 0, "nmode", (char *)&nmode, sizeof(nmode),
++			NULL, 0, TRUE);
++	if (ret < 0)
++		DHD_ERROR(("%s wl nmode 0 failed %d\n", __FUNCTION__, ret));
++#endif /* DISABLE_11N */
++
++	/* query for 'ver' to get version info from firmware */
++	memset(buf, 0, sizeof(buf));
++	ptr = buf;
++	ret = dhd_iovar(dhd, 0, "ver", NULL, 0, (char *)&buf, sizeof(buf), FALSE);
++	if (ret < 0)
++		DHD_ERROR(("%s failed %d\n", __FUNCTION__, ret));
++	else {
++		bcmstrtok(&ptr, "\n", 0);
++		/* Print fw version info */
++		DHD_ERROR(("Firmware version = %s\n", buf));
++#if defined(BCMSDIO) || defined(BCMPCIE)
++		dhd_set_version_info(dhd, buf);
++#endif /* BCMSDIO || BCMPCIE */
++	}
++
++#if defined(BCMSDIO)
++	dhd_txglom_enable(dhd, TRUE);
++#endif /* defined(BCMSDIO) */
++
++#if defined(BCMSDIO) || defined(BCMDBUS)
++#ifdef PROP_TXSTATUS
++	if (disable_proptx ||
++#ifdef PROP_TXSTATUS_VSDB
++		/* enable WLFC only if the firmware is VSDB when it is in STA mode */
++		(dhd->op_mode != DHD_FLAG_HOSTAP_MODE &&
++		 dhd->op_mode != DHD_FLAG_IBSS_MODE) ||
++#endif /* PROP_TXSTATUS_VSDB */
++		FALSE) {
++		wlfc_enable = FALSE;
++	}
++
++#if defined(PROP_TXSTATUS)
++#endif /* PROP_TXSTATUS */
++
++#ifndef DISABLE_11N
++	ret2 = dhd_iovar(dhd, 0, "ampdu_hostreorder", (char *)&hostreorder, sizeof(hostreorder),
++			NULL, 0, TRUE);
++	if (ret2 < 0) {
++		DHD_ERROR(("%s wl ampdu_hostreorder failed %d\n", __FUNCTION__, ret2));
++		if (ret2 != BCME_UNSUPPORTED)
++			ret = ret2;
++		if (ret2 != BCME_OK)
++			hostreorder = 0;
++	}
++#endif /* DISABLE_11N */
++
++
++	if (wlfc_enable)
++		dhd_wlfc_init(dhd);
++#ifndef DISABLE_11N
++	else if (hostreorder)
++		dhd_wlfc_hostreorder_init(dhd);
++#endif /* DISABLE_11N */
++
++#endif /* PROP_TXSTATUS */
++#endif /* BCMSDIO || BCMBUS */
++#ifndef PCIE_FULL_DONGLE
++	/* For FD we need all the packets at DHD to handle intra-BSS forwarding */
++	if (FW_SUPPORTED(dhd, ap)) {
++		wl_ap_isolate = AP_ISOLATE_SENDUP_ALL;
++		ret = dhd_iovar(dhd, 0, "ap_isolate", (char *)&wl_ap_isolate, sizeof(wl_ap_isolate),
++				NULL, 0, TRUE);
++		if (ret < 0)
++			DHD_ERROR(("%s failed %d\n", __FUNCTION__, ret));
++	}
++#endif /* PCIE_FULL_DONGLE */
++#ifdef PNO_SUPPORT
++	if (!dhd->pno_state) {
++		dhd_pno_init(dhd);
++	}
++#endif
++#ifdef RTT_SUPPORT
++	if (!dhd->rtt_state) {
++		ret = dhd_rtt_init(dhd);
++		if (ret < 0) {
++			DHD_ERROR(("%s failed to initialize RTT\n", __FUNCTION__));
++		}
++	}
++#endif
++#ifdef WL11U
++	dhd_interworking_enable(dhd);
++#endif /* WL11U */
++
++done:
++
++	if (eventmask_msg)
++		kfree(eventmask_msg);
++	if (iov_buf)
++		kfree(iov_buf);
++
++	return ret;
++}
++
++int
++dhd_iovar(dhd_pub_t *pub, int ifidx, char *name, char *param_buf, uint param_len, char *res_buf,
++		uint res_len, int set)
++{
++	char *buf = NULL;
++	int input_len;
++	wl_ioctl_t ioc;
++	int ret;
++
++	if (res_len > WLC_IOCTL_MAXLEN || param_len > WLC_IOCTL_MAXLEN)
++		return BCME_BADARG;
++
++	input_len = strlen(name) + 1 + param_len;
++	if (input_len > WLC_IOCTL_MAXLEN)
++		return BCME_BADARG;
++
++	buf = NULL;
++	if (set) {
++		if (res_buf || res_len != 0) {
++			DHD_ERROR(("%s: SET wrong arguemnet\n", __FUNCTION__));
++			ret = BCME_BADARG;
++			goto exit;
++		}
++		buf = kzalloc(input_len, GFP_KERNEL);
++		if (!buf) {
++			DHD_ERROR(("%s: mem alloc failed\n", __FUNCTION__));
++			ret = BCME_NOMEM;
++			goto exit;
++		}
++		ret = bcm_mkiovar(name, param_buf, param_len, buf, input_len);
++		if (!ret) {
++			ret = BCME_NOMEM;
++			goto exit;
++		}
++
++		ioc.cmd = WLC_SET_VAR;
++		ioc.buf = buf;
++		ioc.len = input_len;
++		ioc.set = set;
++
++		ret = dhd_wl_ioctl(pub, ifidx, &ioc, ioc.buf, ioc.len);
++	} else {
++		if (!res_buf || !res_len) {
++			DHD_ERROR(("%s: GET failed. resp_buf NULL or length 0.\n", __FUNCTION__));
++			ret = BCME_BADARG;
++			goto exit;
++		}
++
++		if (res_len < input_len) {
++			DHD_INFO(("%s: res_len(%d) < input_len(%d)\n", __FUNCTION__,
++					res_len, input_len));
++			buf = kzalloc(input_len, GFP_KERNEL);
++			if (!buf) {
++				DHD_ERROR(("%s: mem alloc failed\n", __FUNCTION__));
++				ret = BCME_NOMEM;
++				goto exit;
++			}
++			ret = bcm_mkiovar(name, param_buf, param_len, buf, input_len);
++			if (!ret) {
++				ret = BCME_NOMEM;
++				goto exit;
++			}
++
++			ioc.cmd = WLC_GET_VAR;
++			ioc.buf = buf;
++			ioc.len = input_len;
++			ioc.set = set;
++
++			ret = dhd_wl_ioctl(pub, ifidx, &ioc, ioc.buf, ioc.len);
++
++			if (ret == BCME_OK) {
++				memcpy(res_buf, buf, res_len);
++			}
++		} else {
++			memset(res_buf, 0, res_len);
++			ret = bcm_mkiovar(name, param_buf, param_len, res_buf, res_len);
++			if (!ret) {
++				ret = BCME_NOMEM;
++				goto exit;
++			}
++
++			ioc.cmd = WLC_GET_VAR;
++			ioc.buf = res_buf;
++			ioc.len = res_len;
++			ioc.set = set;
++
++			ret = dhd_wl_ioctl(pub, ifidx, &ioc, ioc.buf, ioc.len);
++		}
++	}
++exit:
++	kfree(buf);
++	return ret;
++}
++
++int
++dhd_getiovar(dhd_pub_t *pub, int ifidx, char *name, char *cmd_buf,
++	uint cmd_len, char **resptr, uint resp_len)
++{
++	int len = resp_len;
++	int ret;
++	char *buf = *resptr;
++	wl_ioctl_t ioc;
++	if (resp_len > WLC_IOCTL_MAXLEN)
++		return BCME_BADARG;
++
++	memset(buf, 0, resp_len);
++
++	bcm_mkiovar(name, cmd_buf, cmd_len, buf, len);
++
++	memset(&ioc, 0, sizeof(ioc));
++
++	ioc.cmd = WLC_GET_VAR;
++	ioc.buf = buf;
++	ioc.len = len;
++	ioc.set = 0;
++
++	ret = dhd_wl_ioctl(pub, ifidx, &ioc, ioc.buf, ioc.len);
++
++	return ret;
++}
++
++
++int dhd_change_mtu(dhd_pub_t *dhdp, int new_mtu, int ifidx)
++{
++	struct dhd_info *dhd = dhdp->info;
++	struct net_device *dev = NULL;
++
++	ASSERT(dhd && dhd->iflist[ifidx]);
++	dev = dhd->iflist[ifidx]->net;
++	ASSERT(dev);
++
++	if (netif_running(dev)) {
++		DHD_ERROR(("%s: Must be down to change its MTU", dev->name));
++		return BCME_NOTDOWN;
++	}
++
++#define DHD_MIN_MTU 1500
++#define DHD_MAX_MTU 1752
++
++	if ((new_mtu < DHD_MIN_MTU) || (new_mtu > DHD_MAX_MTU)) {
++		DHD_ERROR(("%s: MTU size %d is invalid.\n", __FUNCTION__, new_mtu));
++		return BCME_BADARG;
++	}
++
++	dev->mtu = new_mtu;
++	return 0;
++}
++
++#ifdef ARP_OFFLOAD_SUPPORT
++/* add or remove AOE host ip(s) (up to 8 IPs on the interface)  */
++void
++aoe_update_host_ipv4_table(dhd_pub_t *dhd_pub, u32 ipa, bool add, int idx)
++{
++	u32 ipv4_buf[MAX_IPV4_ENTRIES]; /* temp save for AOE host_ip table */
++	int i;
++	int ret;
++
++	bzero(ipv4_buf, sizeof(ipv4_buf));
++
++	/* display what we've got */
++	ret = dhd_arp_get_arp_hostip_table(dhd_pub, ipv4_buf, sizeof(ipv4_buf), idx);
++	DHD_ARPOE(("%s: hostip table read from Dongle:\n", __FUNCTION__));
++	if (ret) {
++		DHD_ERROR(("%s failed\n", __FUNCTION__));
++		return;
++	}
++#ifdef AOE_DBG
++	dhd_print_buf(ipv4_buf, 32, 4); /* max 8 IPs 4b each */
++#endif
++	/* now we saved hoste_ip table, clr it in the dongle AOE */
++	dhd_aoe_hostip_clr(dhd_pub, idx);
++
++	for (i = 0; i < MAX_IPV4_ENTRIES; i++) {
++		if (add && (ipv4_buf[i] == 0)) {
++				ipv4_buf[i] = ipa;
++				add = FALSE; /* added ipa to local table  */
++				DHD_ARPOE(("%s: Saved new IP in temp arp_hostip[%d]\n",
++				__FUNCTION__, i));
++		} else if (ipv4_buf[i] == ipa) {
++			ipv4_buf[i]	= 0;
++			DHD_ARPOE(("%s: removed IP:%x from temp table %d\n",
++				__FUNCTION__, ipa, i));
++		}
++
++		if (ipv4_buf[i] != 0) {
++			/* add back host_ip entries from our local cache */
++			dhd_arp_offload_add_ip(dhd_pub, ipv4_buf[i], idx);
++			DHD_ARPOE(("%s: added IP:%x to dongle arp_hostip[%d]\n\n",
++				__FUNCTION__, ipv4_buf[i], i));
++		}
++	}
++#ifdef AOE_DBG
++	/* see the resulting hostip table */
++	dhd_arp_get_arp_hostip_table(dhd_pub, ipv4_buf, sizeof(ipv4_buf), idx);
++	DHD_ARPOE(("%s: read back arp_hostip table:\n", __FUNCTION__));
++	dhd_print_buf(ipv4_buf, 32, 4); /* max 8 IPs 4b each */
++#endif
++}
++
++/*
++ * Notification mechanism from kernel to our driver. This function is called by the Linux kernel
++ * whenever there is an event related to an IP address.
++ * ptr : kernel provided pointer to IP address that has changed
++ */
++static int dhd_inetaddr_notifier_call(struct notifier_block *this,
++	unsigned long event,
++	void *ptr)
++{
++	struct in_ifaddr *ifa = (struct in_ifaddr *)ptr;
++
++	dhd_info_t *dhd;
++	dhd_pub_t *dhd_pub;
++	int idx;
++
++	if (!dhd_arp_enable)
++		return NOTIFY_DONE;
++	if (!ifa || !(ifa->ifa_dev->dev))
++		return NOTIFY_DONE;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
++	/* Filter notifications meant for non Broadcom devices */
++	if ((ifa->ifa_dev->dev->netdev_ops != &dhd_ops_pri) &&
++	    (ifa->ifa_dev->dev->netdev_ops != &dhd_ops_virt)) {
++#if defined(WL_ENABLE_P2P_IF)
++		if (!wl_cfgp2p_is_ifops(ifa->ifa_dev->dev->netdev_ops))
++#endif /* WL_ENABLE_P2P_IF */
++			return NOTIFY_DONE;
++	}
++#endif /* LINUX_VERSION_CODE */
++
++	dhd = DHD_DEV_INFO(ifa->ifa_dev->dev);
++	if (!dhd)
++		return NOTIFY_DONE;
++
++	dhd_pub = &dhd->pub;
++
++#ifndef STBLINUX
++	if (dhd_pub->arp_version == 1) {
++		idx = 0;
++	} else
++#endif /* STBLINUX */
++	{	for (idx = 0; idx < DHD_MAX_IFS; idx++) {
++			if (dhd->iflist[idx] && dhd->iflist[idx]->net == ifa->ifa_dev->dev)
++			break;
++		}
++		if (idx < DHD_MAX_IFS) {
++			DHD_TRACE(("ifidx : %p %s %d\n", dhd->iflist[idx]->net,
++				dhd->iflist[idx]->name, dhd->iflist[idx]->idx));
++		} else {
++			DHD_ERROR(("Cannot find ifidx for(%s) set to 0\n", ifa->ifa_label));
++			idx = 0;
++		}
++	}
++
++	switch (event) {
++		case NETDEV_UP:
++			DHD_ARPOE(("%s: [%s] Up IP: 0x%x\n",
++				__FUNCTION__, ifa->ifa_label, ifa->ifa_address));
++
++			if (dhd->pub.busstate != DHD_BUS_DATA) {
++				DHD_ERROR(("%s: bus not ready, exit\n", __FUNCTION__));
++				if (dhd->pend_ipaddr) {
++					DHD_ERROR(("%s: overwrite pending ipaddr: 0x%x\n",
++						__FUNCTION__, dhd->pend_ipaddr));
++				}
++				dhd->pend_ipaddr = ifa->ifa_address;
++				break;
++			}
++
++#ifdef AOE_IP_ALIAS_SUPPORT
++			DHD_ARPOE(("%s:add aliased IP to AOE hostip cache\n",
++				__FUNCTION__));
++			aoe_update_host_ipv4_table(dhd_pub, ifa->ifa_address, TRUE, idx);
++#endif /* AOE_IP_ALIAS_SUPPORT */
++			break;
++
++		case NETDEV_DOWN:
++			DHD_ARPOE(("%s: [%s] Down IP: 0x%x\n",
++				__FUNCTION__, ifa->ifa_label, ifa->ifa_address));
++			dhd->pend_ipaddr = 0;
++#ifdef AOE_IP_ALIAS_SUPPORT
++			DHD_ARPOE(("%s:interface is down, AOE clr all for this if\n",
++				__FUNCTION__));
++			aoe_update_host_ipv4_table(dhd_pub, ifa->ifa_address, FALSE, idx);
++#else
++			dhd_aoe_hostip_clr(&dhd->pub, idx);
++			dhd_aoe_arp_clr(&dhd->pub, idx);
++#endif /* AOE_IP_ALIAS_SUPPORT */
++			break;
++
++		default:
++			DHD_ARPOE(("%s: do noting for [%s] Event: %lu\n",
++				__func__, ifa->ifa_label, event));
++			break;
++	}
++	return NOTIFY_DONE;
++}
++#endif /* ARP_OFFLOAD_SUPPORT */
++
++#if defined(CONFIG_IPV6)
++/* Neighbor Discovery Offload: defered handler */
++static void
++dhd_inet6_work_handler(void *dhd_info, void *event_data, u8 event)
++{
++	struct ipv6_work_info_t *ndo_work = (struct ipv6_work_info_t *)event_data;
++	dhd_pub_t	*pub = &((dhd_info_t *)dhd_info)->pub;
++	int		ret;
++
++	if (event != DHD_WQ_WORK_IPV6_NDO) {
++		DHD_ERROR(("%s: unexpected event \n", __FUNCTION__));
++		return;
++	}
++
++	if (!ndo_work) {
++		DHD_ERROR(("%s: ipv6 work info is not initialized \n", __FUNCTION__));
++		return;
++	}
++
++	if (!pub) {
++		DHD_ERROR(("%s: dhd pub is not initialized \n", __FUNCTION__));
++		return;
++	}
++
++	if (ndo_work->if_idx) {
++		DHD_ERROR(("%s: idx %d \n", __FUNCTION__, ndo_work->if_idx));
++		return;
++	}
++
++	switch (ndo_work->event) {
++		case NETDEV_UP:
++			DHD_TRACE(("%s: Enable NDO and add ipv6 into table \n ", __FUNCTION__));
++			ret = dhd_ndo_enable(pub, TRUE);
++			if (ret < 0) {
++				DHD_ERROR(("%s: Enabling NDO Failed %d\n", __FUNCTION__, ret));
++			}
++
++			ret = dhd_ndo_add_ip(pub, &ndo_work->ipv6_addr[0], ndo_work->if_idx);
++			if (ret < 0) {
++				DHD_ERROR(("%s: Adding host ip for NDO failed %d\n",
++					__FUNCTION__, ret));
++			}
++			break;
++		case NETDEV_DOWN:
++			DHD_TRACE(("%s: clear ipv6 table \n", __FUNCTION__));
++			ret = dhd_ndo_remove_ip(pub, ndo_work->if_idx);
++			if (ret < 0) {
++				DHD_ERROR(("%s: Removing host ip for NDO failed %d\n",
++					__FUNCTION__, ret));
++				goto done;
++			}
++
++			ret = dhd_ndo_enable(pub, FALSE);
++			if (ret < 0) {
++				DHD_ERROR(("%s: disabling NDO Failed %d\n", __FUNCTION__, ret));
++				goto done;
++			}
++			break;
++		default:
++			DHD_ERROR(("%s: unknown notifier event \n", __FUNCTION__));
++			break;
++	}
++done:
++	/* free ndo_work. alloced while scheduling the work */
++	kfree(ndo_work);
++
++	return;
++}
++
++/*
++ * Neighbor Discovery Offload: Called when an interface
++ * is assigned with ipv6 address.
++ * Handles only primary interface
++ */
++static int dhd_inet6addr_notifier_call(struct notifier_block *this,
++	unsigned long event,
++	void *ptr)
++{
++	dhd_info_t *dhd;
++	dhd_pub_t *dhd_pub;
++	struct inet6_ifaddr *inet6_ifa = ptr;
++	struct in6_addr *ipv6_addr = &inet6_ifa->addr;
++	struct ipv6_work_info_t *ndo_info;
++	int idx = 0; /* REVISIT */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
++	/* Filter notifications meant for non Broadcom devices */
++	if (inet6_ifa->idev->dev->netdev_ops != &dhd_ops_pri) {
++			return NOTIFY_DONE;
++	}
++#endif /* LINUX_VERSION_CODE */
++
++	dhd = DHD_DEV_INFO(inet6_ifa->idev->dev);
++	if (!dhd)
++		return NOTIFY_DONE;
++
++	if (dhd->iflist[idx] && dhd->iflist[idx]->net != inet6_ifa->idev->dev)
++		return NOTIFY_DONE;
++	dhd_pub = &dhd->pub;
++
++	if (!FW_SUPPORTED(dhd_pub, ndoe))
++		return NOTIFY_DONE;
++
++	ndo_info = (struct ipv6_work_info_t *)kzalloc(sizeof(struct ipv6_work_info_t), GFP_ATOMIC);
++	if (!ndo_info) {
++		DHD_ERROR(("%s: ipv6 work alloc failed\n", __FUNCTION__));
++		return NOTIFY_DONE;
++	}
++
++	ndo_info->event = event;
++	ndo_info->if_idx = idx;
++	memcpy(&ndo_info->ipv6_addr[0], ipv6_addr, IPV6_ADDR_LEN);
++
++	/* defer the work to thread as it may block kernel */
++	dhd_deferred_schedule_work(dhd->dhd_deferred_wq, (void *)ndo_info, DHD_WQ_WORK_IPV6_NDO,
++		dhd_inet6_work_handler, DHD_WORK_PRIORITY_LOW);
++	return NOTIFY_DONE;
++}
++#endif /* OEM_ANDROID && CONFIG_IPV6 */
++
++int
++dhd_register_if(dhd_pub_t *dhdp, int ifidx, bool need_rtnl_lock)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++	dhd_if_t *ifp;
++	struct net_device *net = NULL;
++	int err = 0;
++	uint8 temp_addr[ETHER_ADDR_LEN] = { 0x00, 0x90, 0x4c, 0x11, 0x22, 0x33 };
++
++	DHD_TRACE(("%s: ifidx %d\n", __FUNCTION__, ifidx));
++
++	ASSERT(dhd && dhd->iflist[ifidx]);
++	ifp = dhd->iflist[ifidx];
++	net = ifp->net;
++	ASSERT(net && (ifp->idx == ifidx));
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31))
++	ASSERT(!net->open);
++	net->get_stats = dhd_get_stats;
++	net->do_ioctl = dhd_ioctl_entry;
++	net->hard_start_xmit = dhd_start_xmit;
++	net->set_mac_address = dhd_set_mac_address;
++	net->set_multicast_list = dhd_set_multicast_list;
++	net->open = net->stop = NULL;
++#else
++	ASSERT(!net->netdev_ops);
++	net->netdev_ops = &dhd_ops_virt;
++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31) */
++
++	/* Ok, link into the network layer... */
++	if (ifidx == 0) {
++		/*
++		 * device functions for the primary interface only
++		 */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31))
++		net->open = dhd_open;
++		net->stop = dhd_stop;
++#else
++		net->netdev_ops = &dhd_ops_pri;
++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31) */
++		if (!ETHER_ISNULLADDR(dhd->pub.mac.octet))
++			memcpy(temp_addr, dhd->pub.mac.octet, ETHER_ADDR_LEN);
++	} else {
++		/*
++		 * We have to use the primary MAC for virtual interfaces
++		 */
++		memcpy(temp_addr, ifp->mac_addr, ETHER_ADDR_LEN);
++		/*
++		 * Android sets the locally administered bit to indicate that this is a
++		 * portable hotspot.  This will not work in simultaneous AP/STA mode,
++		 * nor with P2P.  Need to set the Donlge's MAC address, and then use that.
++		 */
++		if (!memcmp(temp_addr, dhd->iflist[0]->mac_addr,
++			ETHER_ADDR_LEN)) {
++			DHD_ERROR(("%s interface [%s]: set locally administered bit in MAC\n",
++			__func__, net->name));
++			temp_addr[0] |= 0x02;
++		}
++	}
++
++	net->hard_header_len = ETH_HLEN + dhd->pub.hdrlen;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
++	net->ethtool_ops = &dhd_ethtool_ops;
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24) */
++
++#if defined(WL_WIRELESS_EXT)
++#if WIRELESS_EXT < 19
++	net->get_wireless_stats = dhd_get_wireless_stats;
++#endif /* WIRELESS_EXT < 19 */
++#if WIRELESS_EXT > 12
++	net->wireless_handlers = (struct iw_handler_def *)&wl_iw_handler_def;
++#endif /* WIRELESS_EXT > 12 */
++#endif /* defined(WL_WIRELESS_EXT) */
++
++	dhd->pub.rxsz = DBUS_RX_BUFFER_SIZE_DHD(net);
++
++	memcpy(net->dev_addr, temp_addr, ETHER_ADDR_LEN);
++
++	if (ifidx == 0)
++		printf("%s\n", dhd_version);
++
++	if (need_rtnl_lock)
++		err = register_netdev(net);
++	else
++		err = register_netdevice(net);
++
++	if (err != 0) {
++		DHD_ERROR(("couldn't register the net device [%s], err %d\n", net->name, err));
++		goto fail;
++	}
++
++
++
++	printf("Register interface [%s]  MAC: "MACDBG"\n\n", net->name,
++		MAC2STRDBG(net->dev_addr));
++
++#if defined(SOFTAP) && defined(WL_WIRELESS_EXT) && !defined(WL_CFG80211)
++		wl_iw_iscan_set_scan_broadcast_prep(net, 1);
++#endif
++
++#if (defined(BCMPCIE) || (defined(BCMLXSDMMC) && (LINUX_VERSION_CODE >= \
++	KERNEL_VERSION(2, 6, 27))))
++	if (ifidx == 0) {
++#ifdef BCMLXSDMMC
++		up(&dhd_registration_sem);
++#endif /* BCMLXSDMMC */
++		if (!dhd_download_fw_on_driverload) {
++#ifdef WL_CFG80211
++			wl_terminate_event_handler();
++#endif /* WL_CFG80211 */
++#if defined(DHD_LB) && defined(DHD_LB_RXP)
++			__skb_queue_purge(&dhd->rx_pend_queue);
++#endif /* DHD_LB && DHD_LB_RXP */
++#if defined(BCMPCIE) && defined(DHDTCPACK_SUPPRESS)
++			dhd_tcpack_suppress_set(dhdp, TCPACK_SUP_OFF);
++#endif /* BCMPCIE && DHDTCPACK_SUPPRESS */
++			dhd_net_bus_devreset(net, TRUE);
++#ifdef BCMLXSDMMC
++			dhd_net_bus_suspend(net);
++#endif /* BCMLXSDMMC */
++			wifi_platform_set_power(dhdp->info->adapter, FALSE, WIFI_TURNOFF_DELAY);
++		}
++	}
++#endif /* OEM_ANDROID && (BCMPCIE || (BCMLXSDMMC && KERNEL_VERSION >= 2.6.27)) */
++	return 0;
++
++fail:
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31)
++	net->open = NULL;
++#else
++	net->netdev_ops = NULL;
++#endif
++	return err;
++}
++
++void
++dhd_bus_detach(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (dhdp) {
++		dhd = (dhd_info_t *)dhdp->info;
++		if (dhd) {
++
++			/*
++			 * In case of Android cfg80211 driver, the bus is down in dhd_stop,
++			 *  calling stop again will cuase SD read/write errors.
++			 */
++			if (dhd->pub.busstate != DHD_BUS_DOWN) {
++				/* Stop the protocol module */
++				dhd_prot_stop(&dhd->pub);
++
++				/* Stop the bus module */
++#ifdef BCMDBUS
++				/* Force Dongle terminated */
++				if (dhd_wl_ioctl_cmd(dhdp, WLC_TERMINATED, NULL, 0, TRUE, 0) < 0)
++					DHD_ERROR(("%s Setting WLC_TERMINATED failed\n",
++						__FUNCTION__));
++				dbus_stop(dhd->pub.dbus);
++				dhd->pub.busstate = DHD_BUS_DOWN;
++#else
++				dhd_bus_stop(dhd->pub.bus, TRUE);
++#endif /* BCMDBUS */
++			}
++
++#if defined(OOB_INTR_ONLY) || defined(BCMPCIE_OOB_HOST_WAKE)
++			dhd_bus_oob_intr_unregister(dhdp);
++#endif 
++		}
++	}
++}
++
++
++void dhd_detach(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd;
++	unsigned long flags;
++	int timer_valid = FALSE;
++	struct net_device *dev;
++
++	if (!dhdp)
++		return;
++
++	dhd = (dhd_info_t *)dhdp->info;
++	if (!dhd)
++		return;
++
++	dev = dhd->iflist[0]->net;
++
++	if (dev) {
++		rtnl_lock();
++		if (dev->flags & IFF_UP) {
++			/* If IFF_UP is still up, it indicates that
++			 * "ifconfig wlan0 down" hasn't been called.
++			 * So invoke dev_close explicitly here to
++			 * bring down the interface.
++			 */
++			DHD_TRACE(("IFF_UP flag is up. Enforcing dev_close from detach \n"));
++			dev_close(dev);
++		}
++		rtnl_unlock();
++	}
++
++	DHD_TRACE(("%s: Enter state 0x%x\n", __FUNCTION__, dhd->dhd_state));
++
++	dhd->pub.up = 0;
++	if (dhd->dhd_state & DHD_ATTACH_STATE_DONE) {
++		if (dhd_found > 0)
++			dhd_found--;
++	}
++	else {
++		/* Give sufficient time for threads to start running in case
++		 * dhd_attach() has failed
++		 */
++		OSL_SLEEP(100);
++	}
++#ifdef DHD_WET
++	dhd_free_wet_info(&dhd->pub, dhd->pub.wet_info);
++#endif
++
++#if defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW)
++#if defined(BCMDBUS)
++	if (dhd->fw_download_task) {
++		up(&dhd->fw_download_lock);
++		kthread_stop(dhd->fw_download_task);
++		dhd->fw_download_task = NULL;
++	}
++#endif /* BCMDBUS */
++#endif /* defined(BCM_DNGL_EMBEDIMAGE) || defined(BCM_REQUEST_FW) */
++
++#ifdef PROP_TXSTATUS
++#ifdef DHD_WLFC_THREAD
++	if (dhd->pub.wlfc_thread) {
++		kthread_stop(dhd->pub.wlfc_thread);
++		dhdp->wlfc_thread_go = TRUE;
++		wake_up_interruptible(&dhdp->wlfc_wqhead);
++	}
++	dhd->pub.wlfc_thread = NULL;
++#endif /* DHD_WLFC_THREAD */
++#endif /* PROP_TXSTATUS */
++
++#ifdef WL_CFG80211
++	wl_cfg80211_down(NULL);
++#endif /* WL_CFG80211 */
++
++	if (dhd->dhd_state & DHD_ATTACH_STATE_PROT_ATTACH) {
++
++#ifndef	BCMSDIO
++		dhd_bus_detach(dhdp);
++#endif
++#ifdef BCMPCIE
++		if (is_reboot == SYS_RESTART) {
++			extern bcmdhd_wifi_platdata_t *dhd_wifi_platdata;
++			if (dhd_wifi_platdata && !dhdp->dongle_reset) {
++				dhdpcie_bus_clock_stop(dhdp->bus);
++				wifi_platform_set_power(dhd_wifi_platdata->adapters,
++					FALSE, WIFI_TURNOFF_DELAY);
++			}
++		}
++#endif /* BCMPCIE */
++#if !defined(PCIE_FULL_DONGLE) && !defined(BCMSDIO)
++		if (dhdp->prot)
++			dhd_prot_detach(dhdp);
++#endif
++	}
++
++#ifdef ARP_OFFLOAD_SUPPORT
++	if (dhd_inetaddr_notifier_registered) {
++		dhd_inetaddr_notifier_registered = FALSE;
++		unregister_inetaddr_notifier(&dhd_inetaddr_notifier);
++	}
++#endif /* ARP_OFFLOAD_SUPPORT */
++#if defined(CONFIG_IPV6)
++	if (dhd_inet6addr_notifier_registered) {
++		dhd_inet6addr_notifier_registered = FALSE;
++		unregister_inet6addr_notifier(&dhd_inet6addr_notifier);
++	}
++#endif /* OEM_ANDROID && CONFIG_IPV6 */
++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND)
++	if (dhd->dhd_state & DHD_ATTACH_STATE_EARLYSUSPEND_DONE) {
++		if (dhd->early_suspend.suspend)
++			unregister_early_suspend(&dhd->early_suspend);
++	}
++#endif /* CONFIG_HAS_EARLYSUSPEND && DHD_USE_EARLYSUSPEND */
++
++#if defined(WL_WIRELESS_EXT)
++	if (dhd->dhd_state & DHD_ATTACH_STATE_WL_ATTACH) {
++		/* Detatch and unlink in the iw */
++		wl_iw_detach();
++	}
++#endif /* defined(WL_WIRELESS_EXT) */
++
++#ifdef DHD_ULP
++	dhd_ulp_deinit(dhd->pub.osh, dhdp);
++#endif /* DHD_ULP */
++
++	/* delete all interfaces, start with virtual  */
++	if (dhd->dhd_state & DHD_ATTACH_STATE_ADD_IF) {
++		int i = 1;
++		dhd_if_t *ifp;
++
++		/* Cleanup virtual interfaces */
++		dhd_net_if_lock_local(dhd);
++		for (i = 1; i < DHD_MAX_IFS; i++) {
++			if (dhd->iflist[i]) {
++				dhd_remove_if(&dhd->pub, i, TRUE);
++			}
++		}
++		dhd_net_if_unlock_local(dhd);
++
++		/*  delete primary interface 0 */
++		ifp = dhd->iflist[0];
++		ASSERT(ifp);
++		ASSERT(ifp->net);
++		if (ifp && ifp->net) {
++#if (defined(STBLINUX) && defined(WL_CFG80211))
++
++			/* keep wirless framework happy */
++			wl_cfg80211_cleanup();
++#endif /* STBLINUX && WL_CFG80211 */
++
++
++
++
++			/* in unregister_netdev case, the interface gets freed by net->destructor
++			 * (which is set to free_netdev)
++			 */
++			if (ifp->net->reg_state == NETREG_UNINITIALIZED) {
++				free_netdev(ifp->net);
++			} else {
++#ifdef SET_RPS_CPUS
++				custom_rps_map_clear(ifp->net->_rx);
++#endif /* SET_RPS_CPUS */
++				netif_tx_disable(ifp->net);
++				unregister_netdev(ifp->net);
++			}
++			ifp->net = NULL;
++#ifdef BCMSDIO
++		dhd_bus_detach(dhdp);
++
++		if (dhdp->prot)
++			dhd_prot_detach(dhdp);
++#endif
++#ifdef DHD_WMF
++			dhd_wmf_cleanup(dhdp, 0);
++#endif /* DHD_WMF */
++#ifdef DHD_L2_FILTER
++			bcm_l2_filter_arp_table_update(dhdp->osh, ifp->phnd_arp_table, TRUE,
++				NULL, FALSE, dhdp->tickcnt);
++			deinit_l2_filter_arp_table(dhdp->osh, ifp->phnd_arp_table);
++			ifp->phnd_arp_table = NULL;
++#endif /* DHD_L2_FILTER */
++
++
++			dhd_if_del_sta_list(ifp);
++
++			MFREE(dhd->pub.osh, ifp, sizeof(*ifp));
++			dhd->iflist[0] = NULL;
++		}
++	}
++
++	/* Clear the watchdog timer */
++	DHD_GENERAL_LOCK(&dhd->pub, flags);
++	timer_valid = dhd->wd_timer_valid;
++	dhd->wd_timer_valid = FALSE;
++	DHD_GENERAL_UNLOCK(&dhd->pub, flags);
++	if (timer_valid)
++		del_timer_sync(&dhd->timer);
++
++#ifdef BCMDBUS
++	tasklet_kill(&dhd->tasklet);
++#else
++	if (dhd->dhd_state & DHD_ATTACH_STATE_THREADS_CREATED) {
++		if (dhd->thr_wdt_ctl.thr_pid >= 0) {
++			PROC_STOP(&dhd->thr_wdt_ctl);
++		}
++
++		if (dhd->rxthread_enabled && dhd->thr_rxf_ctl.thr_pid >= 0) {
++			PROC_STOP(&dhd->thr_rxf_ctl);
++		}
++
++		if (dhd->thr_dpc_ctl.thr_pid >= 0) {
++			PROC_STOP(&dhd->thr_dpc_ctl);
++		} else {
++			tasklet_kill(&dhd->tasklet);
++#ifdef DHD_LB_RXP
++			__skb_queue_purge(&dhd->rx_pend_queue);
++#endif /* DHD_LB_RXP */
++		}
++	}
++#endif /* BCMDBUS */
++
++#if defined(DHD_LB)
++	/* Kill the Load Balancing Tasklets */
++#if defined(DHD_LB_TXC)
++	tasklet_disable(&dhd->tx_compl_tasklet);
++	tasklet_kill(&dhd->tx_compl_tasklet);
++#endif /* DHD_LB_TXC */
++#if defined(DHD_LB_RXC)
++	tasklet_disable(&dhd->rx_compl_tasklet);
++	tasklet_kill(&dhd->rx_compl_tasklet);
++#endif /* DHD_LB_RXC */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0))
++	cpuhp_state_remove_instance(dhd_cpuhp_online_state, &dhd->node_online);
++	cpuhp_remove_multi_state(dhd_cpuhp_online_state);
++#else
++	if (dhd->cpu_notifier.notifier_call != NULL)
++		unregister_cpu_notifier(&dhd->cpu_notifier);
++#endif
++	dhd_cpumasks_deinit(dhd);
++
++#endif /* DHD_LB */
++
++#ifdef WL_CFG80211
++	if (dhd->dhd_state & DHD_ATTACH_STATE_CFG80211) {
++		wl_cfg80211_detach(NULL);
++		dhd_monitor_uninit();
++	}
++#endif
++	/* free deferred work queue */
++	dhd_deferred_work_deinit(dhd->dhd_deferred_wq);
++	dhd->dhd_deferred_wq = NULL;
++
++#ifdef BCMDBUS
++	if (dhdp->dbus) {
++		dbus_detach(dhdp->dbus);
++		dhdp->dbus = NULL;
++	}
++#endif /* BCMDBUS */
++#ifdef SHOW_LOGTRACE
++	if (dhdp->dbg)
++		dhd_os_dbg_detach(dhdp);
++	if (dhd->event_data.fmts)
++		kfree(dhd->event_data.fmts);
++	if (dhd->event_data.raw_fmts)
++		kfree(dhd->event_data.raw_fmts);
++	if (dhd->event_data.raw_sstr)
++		kfree(dhd->event_data.raw_sstr);
++#endif /* SHOW_LOGTRACE */
++
++#ifdef PNO_SUPPORT
++	if (dhdp->pno_state)
++		dhd_pno_deinit(dhdp);
++#endif
++#ifdef RTT_SUPPORT
++	if (dhdp->rtt_state) {
++	dhd_rtt_deinit(dhdp);
++	}
++#endif
++#if defined(CONFIG_PM_SLEEP)
++	if (dhd_pm_notifier_registered) {
++		unregister_pm_notifier(&dhd->pm_notifier);
++		dhd_pm_notifier_registered = FALSE;
++	}
++#endif /* CONFIG_PM_SLEEP */
++
++#ifdef DEBUG_CPU_FREQ
++		if (dhd->new_freq)
++			free_percpu(dhd->new_freq);
++		dhd->new_freq = NULL;
++		cpufreq_unregister_notifier(&dhd->freq_trans, CPUFREQ_TRANSITION_NOTIFIER);
++#endif
++	if (dhd->dhd_state & DHD_ATTACH_STATE_WAKELOCKS_INIT) {
++		DHD_TRACE(("wd wakelock count:%d\n", dhd->wakelock_wd_counter));
++#ifdef CONFIG_HAS_WAKELOCK
++		dhd->wakelock_counter = 0;
++		dhd->wakelock_wd_counter = 0;
++		dhd->wakelock_rx_timeout_enable = 0;
++		dhd->wakelock_ctrl_timeout_enable = 0;
++		wake_lock_destroy(&dhd->wl_wifi);
++		wake_lock_destroy(&dhd->wl_rxwake);
++		wake_lock_destroy(&dhd->wl_ctrlwake);
++		wake_lock_destroy(&dhd->wl_wdwake);
++#ifdef BCMPCIE_OOB_HOST_WAKE
++		wake_lock_destroy(&dhd->wl_intrwake);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#ifdef DHD_USE_SCAN_WAKELOCK
++		wake_lock_destroy(&dhd->wl_scanwake);
++#endif /* DHD_USE_SCAN_WAKELOCK */
++#endif /* CONFIG_HAS_WAKELOCK */
++	}
++
++
++
++#ifdef DHDTCPACK_SUPPRESS
++	/* This will free all MEM allocated for TCPACK SUPPRESS */
++	dhd_tcpack_suppress_set(&dhd->pub, TCPACK_SUP_OFF);
++#endif /* DHDTCPACK_SUPPRESS */
++
++#ifdef PCIE_FULL_DONGLE
++		dhd_flow_rings_deinit(dhdp);
++		if (dhdp->prot)
++			dhd_prot_detach(dhdp);
++#endif
++
++	dhd_fw_downloaded = FALSE;
++}
++
++
++void
++dhd_free(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd;
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (dhdp) {
++		int i;
++		for (i = 0; i < ARRAYSIZE(dhdp->reorder_bufs); i++) {
++			if (dhdp->reorder_bufs[i]) {
++				reorder_info_t *ptr;
++				uint32 buf_size = sizeof(struct reorder_info);
++
++				ptr = dhdp->reorder_bufs[i];
++
++				buf_size += ((ptr->max_idx + 1) * sizeof(void*));
++				DHD_REORDER(("free flow id buf %d, maxidx is %d, buf_size %d\n",
++					i, ptr->max_idx, buf_size));
++
++				MFREE(dhdp->osh, dhdp->reorder_bufs[i], buf_size);
++				dhdp->reorder_bufs[i] = NULL;
++			}
++		}
++
++		dhd_sta_pool_fini(dhdp, DHD_MAX_STA);
++
++		dhd = (dhd_info_t *)dhdp->info;
++		if (dhdp->soc_ram) {
++#if defined(CONFIG_DHD_USE_STATIC_BUF) && defined(DHD_USE_STATIC_MEMDUMP)
++			DHD_OS_PREFREE(dhdp, dhdp->soc_ram, dhdp->soc_ram_length);
++#else
++			MFREE(dhdp->osh, dhdp->soc_ram, dhdp->soc_ram_length);
++#endif /* CONFIG_DHD_USE_STATIC_BUF && DHD_USE_STATIC_MEMDUMP */
++			dhdp->soc_ram = NULL;
++		}
++#ifdef CACHE_FW_IMAGES
++		if (dhdp->cached_fw) {
++			MFREE(dhdp->osh, dhdp->cached_fw, dhdp->bus->ramsize);
++			dhdp->cached_fw = NULL;
++		}
++
++		if (dhdp->cached_nvram) {
++			MFREE(dhdp->osh, dhdp->cached_nvram, MAX_NVRAMBUF_SIZE);
++			dhdp->cached_nvram = NULL;
++		}
++#endif
++		/* If pointer is allocated by dhd_os_prealloc then avoid MFREE */
++		if (dhd &&
++			dhd != (dhd_info_t *)dhd_os_prealloc(dhdp, DHD_PREALLOC_DHD_INFO, 0, FALSE))
++			MFREE(dhd->pub.osh, dhd, sizeof(*dhd));
++		dhd = NULL;
++	}
++}
++
++void
++dhd_clear(dhd_pub_t *dhdp)
++{
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (dhdp) {
++		int i;
++#ifdef DHDTCPACK_SUPPRESS
++		/* Clean up timer/data structure for any remaining/pending packet or timer. */
++		dhd_tcpack_info_tbl_clean(dhdp);
++#endif /* DHDTCPACK_SUPPRESS */
++		for (i = 0; i < ARRAYSIZE(dhdp->reorder_bufs); i++) {
++			if (dhdp->reorder_bufs[i]) {
++				reorder_info_t *ptr;
++				uint32 buf_size = sizeof(struct reorder_info);
++
++				ptr = dhdp->reorder_bufs[i];
++
++				buf_size += ((ptr->max_idx + 1) * sizeof(void*));
++				DHD_REORDER(("free flow id buf %d, maxidx is %d, buf_size %d\n",
++					i, ptr->max_idx, buf_size));
++
++				MFREE(dhdp->osh, dhdp->reorder_bufs[i], buf_size);
++				dhdp->reorder_bufs[i] = NULL;
++			}
++		}
++
++		dhd_sta_pool_clear(dhdp, DHD_MAX_STA);
++
++		if (dhdp->soc_ram) {
++#if defined(CONFIG_DHD_USE_STATIC_BUF) && defined(DHD_USE_STATIC_MEMDUMP)
++			DHD_OS_PREFREE(dhdp, dhdp->soc_ram, dhdp->soc_ram_length);
++#else
++			MFREE(dhdp->osh, dhdp->soc_ram, dhdp->soc_ram_length);
++#endif /* CONFIG_DHD_USE_STATIC_BUF && DHD_USE_STATIC_MEMDUMP */
++			dhdp->soc_ram = NULL;
++		}
++	}
++}
++
++static void
++dhd_module_cleanup(void)
++{
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++#ifdef BCMDBUS
++	dbus_deregister();
++#else
++	dhd_bus_unregister();
++#endif /* BCMDBUS */
++
++	wl_android_exit();
++
++	dhd_wifi_platform_unregister_drv();
++}
++
++static void __exit
++dhd_module_exit(void)
++{
++	dhd_buzzz_detach();
++	dhd_module_cleanup();
++	unregister_reboot_notifier(&dhd_reboot_notifier);
++}
++
++static int __init
++dhd_module_init(void)
++{
++	int err;
++	int retry = POWERUP_MAX_RETRY;
++
++	DHD_ERROR(("%s in\n", __FUNCTION__));
++
++	dhd_buzzz_attach();
++
++	DHD_PERIM_RADIO_INIT();
++
++
++	if (firmware_path[0] != '\0') {
++		strncpy(fw_bak_path, firmware_path, MOD_PARAM_PATHLEN);
++		fw_bak_path[MOD_PARAM_PATHLEN-1] = '\0';
++	}
++
++	if (nvram_path[0] != '\0') {
++		strncpy(nv_bak_path, nvram_path, MOD_PARAM_PATHLEN);
++		nv_bak_path[MOD_PARAM_PATHLEN-1] = '\0';
++	}
++
++	do {
++		err = dhd_wifi_platform_register_drv();
++		if (!err) {
++			register_reboot_notifier(&dhd_reboot_notifier);
++			break;
++		}
++		else {
++			DHD_ERROR(("%s: Failed to load the driver, try cnt %d\n",
++				__FUNCTION__, retry));
++			strncpy(firmware_path, fw_bak_path, MOD_PARAM_PATHLEN);
++			firmware_path[MOD_PARAM_PATHLEN-1] = '\0';
++			strncpy(nvram_path, nv_bak_path, MOD_PARAM_PATHLEN);
++			nvram_path[MOD_PARAM_PATHLEN-1] = '\0';
++		}
++	} while (retry--);
++
++	if (err) {
++		DHD_ERROR(("%s: Failed to load driver max retry reached**\n", __FUNCTION__));
++	} else {
++		if (!dhd_download_fw_on_driverload) {
++			dhd_driver_init_done = TRUE;
++		}
++	}
++
++	DHD_ERROR(("%s out\n", __FUNCTION__));
++
++	return err;
++}
++
++static int
++dhd_reboot_callback(struct notifier_block *this, unsigned long code, void *unused)
++{
++	DHD_TRACE(("%s: code = %ld\n", __FUNCTION__, code));
++#ifdef STBLINUX
++	dhd_module_cleanup();
++#else
++	if (code == SYS_RESTART) {
++#ifdef BCMPCIE
++		is_reboot = code;
++#endif /* BCMPCIE */
++	}
++#endif /* STBLINUX */
++	return NOTIFY_DONE;
++}
++
++#ifdef BCMDBUS
++
++/*
++ * hdrlen is space to reserve in pkt headroom for DBUS
++ */
++void *
++dhd_dbus_probe_cb(void *arg, const char *desc, uint32 bustype, uint32 hdrlen)
++{
++	osl_t *osh;
++	int ret = 0;
++	dbus_attrib_t attrib;
++	dhd_pub_t *pub = NULL;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	/* Ask the OS interface part for an OSL handle */
++	if (!(osh = osl_attach(NULL, bustype, TRUE))) {
++		DHD_ERROR(("%s: OSL attach failed\n", __FUNCTION__));
++		ret = -ENOMEM;
++		goto fail;
++	}
++
++	/* Attach to the dhd/OS interface */
++	if (!(pub = dhd_attach(osh, NULL /* bus */, hdrlen))) {
++		DHD_ERROR(("%s: dhd_attach failed\n", __FUNCTION__));
++		ret = -ENXIO;
++		goto fail;
++	}
++
++	/* Ok, finish the attach to the OS network interface */
++	if (dhd_register_if(pub, 0, TRUE) != 0) {
++		DHD_ERROR(("%s: dhd_register_if failed\n", __FUNCTION__));
++		ret = -ENXIO;
++		goto fail;
++	}
++
++	pub->dbus = dbus_attach(osh, pub->rxsz, DBUS_NRXQ, DBUS_NTXQ,
++		pub->info, &dhd_dbus_cbs, NULL, NULL);
++	if (pub->dbus) {
++		dbus_get_attrib(pub->dbus, &attrib);
++		DHD_ERROR(("DBUS: vid=0x%x pid=0x%x devid=0x%x bustype=0x%x mtu=%d\n",
++			attrib.vid, attrib.pid, attrib.devid, attrib.bustype, attrib.mtu));
++	} else {
++		ret = -ENXIO;
++		goto fail;
++	}
++#ifdef BCM_FD_AGGR
++	pub->info->rpc_th = bcm_rpc_tp_attach(osh, (void *)pub->dbus);
++	if (!pub->info->rpc_th) {
++		DHD_ERROR(("%s: bcm_rpc_tp_attach failed\n", __FUNCTION__));
++		ret = -ENXIO;
++		goto fail;
++	}
++
++	pub->info->rpc_osh = rpc_osl_attach(osh);
++	if (!pub->info->rpc_osh) {
++		DHD_ERROR(("%s: rpc_osl_attach failed\n", __FUNCTION__));
++		bcm_rpc_tp_detach(pub->info->rpc_th);
++		pub->info->rpc_th = NULL;
++		ret = -ENXIO;
++		goto fail;
++	}
++	/* Set up the aggregation release timer */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++	timer_setup(&pub->info->rpcth_timer, dhd_rpcth_watchdog, 0)
++#else
++	init_timer(&pub->info->rpcth_timer);
++	pub->info->rpcth_timer.data = (ulong)pub->info;
++	pub->info->rpcth_timer.function = dhd_rpcth_watchdog;
++#endif
++	pub->info->rpcth_timer_active = FALSE;
++
++	bcm_rpc_tp_register_cb(pub->info->rpc_th, NULL, pub->info,
++		dbus_rpcth_rx_pkt, pub->info, pub->info->rpc_osh);
++#endif /* BCM_FD_AGGR */
++
++	/* This is passed to dhd_dbus_disconnect_cb */
++	return pub->info;
++fail:
++	/* Release resources in reverse order */
++	if (osh) {
++		if (pub) {
++			dhd_detach(pub);
++			dhd_free(pub);
++		}
++		osl_detach(osh);
++	}
++
++	BCM_REFERENCE(ret);
++	return NULL;
++}
++
++void
++dhd_dbus_disconnect_cb(void *arg)
++{
++	dhd_info_t *dhd = (dhd_info_t *)arg;
++	dhd_pub_t *pub;
++	osl_t *osh;
++
++	if (dhd == NULL)
++		return;
++
++	pub = &dhd->pub;
++	osh = pub->osh;
++#ifdef BCM_FD_AGGR
++	del_timer_sync(&dhd->rpcth_timer);
++	bcm_rpc_tp_deregister_cb(dhd->rpc_th);
++	rpc_osl_detach(dhd->rpc_osh);
++	bcm_rpc_tp_detach(dhd->rpc_th);
++#endif
++	dhd_detach(pub);
++	dhd_free(pub);
++
++	if (MALLOCED(osh)) {
++		DHD_ERROR(("%s: MEMORY LEAK %d bytes\n", __FUNCTION__, MALLOCED(osh)));
++	}
++	osl_detach(osh);
++}
++#endif /* BCMDBUS */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)
++#if defined(CONFIG_DEFERRED_INITCALLS)
++#if defined(CONFIG_MACH_UNIVERSAL7420)
++deferred_module_init_sync(dhd_module_init);
++#else
++deferred_module_init(dhd_module_init);
++#endif /* CONFIG_MACH_UNIVERSAL7420 */
++#elif defined(USE_LATE_INITCALL_SYNC)
++late_initcall_sync(dhd_module_init);
++#else
++late_initcall(dhd_module_init);
++#endif /* USE_LATE_INITCALL_SYNC */
++#else
++module_init(dhd_module_init);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0) */
++
++module_exit(dhd_module_exit);
++
++/*
++ * OS specific functions required to implement DHD driver in OS independent way
++ */
++int
++dhd_os_proto_block(dhd_pub_t *pub)
++{
++	dhd_info_t * dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		DHD_PERIM_UNLOCK(pub);
++
++		down(&dhd->proto_sem);
++
++		DHD_PERIM_LOCK(pub);
++		return 1;
++	}
++
++	return 0;
++}
++
++int
++dhd_os_proto_unblock(dhd_pub_t *pub)
++{
++	dhd_info_t * dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		up(&dhd->proto_sem);
++		return 1;
++	}
++
++	return 0;
++}
++
++unsigned int
++dhd_os_get_ioctl_resp_timeout(void)
++{
++	return ((unsigned int)dhd_ioctl_timeout_msec);
++}
++
++void
++dhd_os_set_ioctl_resp_timeout(unsigned int timeout_msec)
++{
++	dhd_ioctl_timeout_msec = (int)timeout_msec;
++}
++
++int
++dhd_os_ioctl_resp_wait(dhd_pub_t *pub, uint *condition)
++{
++	dhd_info_t * dhd = (dhd_info_t *)(pub->info);
++	int timeout;
++
++	/* Convert timeout in millsecond to jiffies */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++	timeout = msecs_to_jiffies(dhd_ioctl_timeout_msec);
++#else
++	timeout = dhd_ioctl_timeout_msec * HZ / 1000;
++#endif
++
++	DHD_PERIM_UNLOCK(pub);
++
++	timeout = wait_event_timeout(dhd->ioctl_resp_wait, (*condition), timeout);
++
++	DHD_PERIM_LOCK(pub);
++
++	return timeout;
++}
++
++int
++dhd_os_ioctl_resp_wake(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	wake_up(&dhd->ioctl_resp_wait);
++	return 0;
++}
++
++int
++dhd_os_d3ack_wait(dhd_pub_t *pub, uint *condition)
++{
++	dhd_info_t * dhd = (dhd_info_t *)(pub->info);
++	int timeout;
++
++	/* Convert timeout in millsecond to jiffies */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++	timeout = msecs_to_jiffies(dhd_ioctl_timeout_msec);
++#else
++	timeout = dhd_ioctl_timeout_msec * HZ / 1000;
++#endif
++
++	DHD_PERIM_UNLOCK(pub);
++
++	timeout = wait_event_timeout(dhd->d3ack_wait, (*condition), timeout);
++
++	DHD_PERIM_LOCK(pub);
++
++	return timeout;
++}
++
++int
++dhd_os_d3ack_wake(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	wake_up(&dhd->d3ack_wait);
++	return 0;
++}
++
++int
++dhd_os_busbusy_wait_negation(dhd_pub_t *pub, uint *condition)
++{
++	dhd_info_t * dhd = (dhd_info_t *)(pub->info);
++	int timeout;
++
++	/* Wait for bus usage contexts to gracefully exit within some timeout value
++	 * Set time out to little higher than dhd_ioctl_timeout_msec,
++	 * so that IOCTL timeout should not get affected.
++	 */
++	/* Convert timeout in millsecond to jiffies */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++	timeout = msecs_to_jiffies(DHD_BUS_BUSY_TIMEOUT);
++#else
++	timeout = DHD_BUS_BUSY_TIMEOUT * HZ / 1000;
++#endif
++
++	timeout = wait_event_timeout(dhd->dhd_bus_busy_state_wait, !(*condition), timeout);
++
++	return timeout;
++}
++
++INLINE int
++dhd_os_busbusy_wake(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	/* Call wmb() to make sure before waking up the other event value gets updated */
++	OSL_SMP_WMB();
++	wake_up(&dhd->dhd_bus_busy_state_wait);
++	return 0;
++}
++
++void
++dhd_os_wd_timer_extend(void *bus, bool extend)
++{
++#ifndef BCMDBUS
++	dhd_pub_t *pub = bus;
++	dhd_info_t *dhd = (dhd_info_t *)pub->info;
++
++	if (extend)
++		dhd_os_wd_timer(bus, WATCHDOG_EXTEND_INTERVAL);
++	else
++		dhd_os_wd_timer(bus, dhd->default_wd_interval);
++#endif /* !BCMDBUS */
++}
++
++
++void
++dhd_os_wd_timer(void *bus, uint wdtick)
++{
++#ifndef BCMDBUS
++	dhd_pub_t *pub = bus;
++	dhd_info_t *dhd = (dhd_info_t *)pub->info;
++	unsigned long flags;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd NULL\n", __FUNCTION__));
++		return;
++	}
++
++	DHD_GENERAL_LOCK(pub, flags);
++
++	/* don't start the wd until fw is loaded */
++	if (pub->busstate == DHD_BUS_DOWN) {
++		DHD_GENERAL_UNLOCK(pub, flags);
++		return;
++	}
++
++	/* Totally stop the timer */
++	if (!wdtick && dhd->wd_timer_valid == TRUE) {
++		dhd->wd_timer_valid = FALSE;
++		DHD_GENERAL_UNLOCK(pub, flags);
++		del_timer_sync(&dhd->timer);
++		return;
++	}
++
++	if (wdtick) {
++		dhd_watchdog_ms = (uint)wdtick;
++		/* Re arm the timer, at last watchdog period */
++		mod_timer(&dhd->timer, jiffies + msecs_to_jiffies(dhd_watchdog_ms));
++		dhd->wd_timer_valid = TRUE;
++	}
++	DHD_GENERAL_UNLOCK(pub, flags);
++#endif /* BCMDBUS */
++}
++
++void *
++dhd_os_open_image(char *filename)
++{
++	struct file *fp;
++
++	fp = filp_open(filename, O_RDONLY, 0);
++	/*
++	 * 2.6.11 (FC4) supports filp_open() but later revs don't?
++	 * Alternative:
++	 * fp = open_namei(AT_FDCWD, filename, O_RD, 0);
++	 * ???
++	 */
++	 if (IS_ERR(fp))
++		 fp = NULL;
++
++	 return fp;
++}
++
++int
++dhd_os_get_image_block(char *buf, int len, void *image)
++{
++	struct file *fp = (struct file *)image;
++	int rdlen;
++	loff_t pos;
++
++	if (!image)
++		return 0;
++
++	pos = fp->f_pos;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
++	rdlen = kernel_read(fp, (void *) buf, (size_t) len, (loff_t *) &pos);
++#else
++	rdlen = kernel_read(fp, pos, buf, len);
++#endif
++	if (rdlen > 0)
++		fp->f_pos += rdlen;
++
++	return rdlen;
++}
++
++void
++dhd_os_close_image(void *image)
++{
++	if (image)
++		filp_close((struct file *)image, NULL);
++}
++
++void
++dhd_os_sdlock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd;
++
++	dhd = (dhd_info_t *)(pub->info);
++
++#ifndef BCMDBUS
++	if (dhd_dpc_prio >= 0)
++		down(&dhd->sdsem);
++	else
++		spin_lock_bh(&dhd->sdlock);
++#else
++	spin_lock_bh(&dhd->sdlock);
++#endif /* BCMDBUS */
++}
++
++void
++dhd_os_sdunlock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd;
++
++	dhd = (dhd_info_t *)(pub->info);
++
++#ifndef BCMDBUS
++	if (dhd_dpc_prio >= 0)
++		up(&dhd->sdsem);
++	else
++		spin_unlock_bh(&dhd->sdlock);
++#else
++	spin_unlock_bh(&dhd->sdlock);
++#endif /* BCMDBUS */
++}
++
++void
++dhd_os_sdlock_txq(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd;
++
++	dhd = (dhd_info_t *)(pub->info);
++#ifdef BCMDBUS
++	spin_lock_irqsave(&dhd->txqlock, dhd->txqlock_flags);
++#else
++	spin_lock_bh(&dhd->txqlock);
++#endif
++}
++
++void
++dhd_os_sdunlock_txq(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd;
++
++	dhd = (dhd_info_t *)(pub->info);
++#ifdef BCMDBUS
++	spin_unlock_irqrestore(&dhd->txqlock, dhd->txqlock_flags);
++#else
++	spin_unlock_bh(&dhd->txqlock);
++#endif
++}
++
++void
++dhd_os_sdlock_rxq(dhd_pub_t *pub)
++{
++}
++
++void
++dhd_os_sdunlock_rxq(dhd_pub_t *pub)
++{
++}
++
++static void
++dhd_os_rxflock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd;
++
++	dhd = (dhd_info_t *)(pub->info);
++	spin_lock_bh(&dhd->rxf_lock);
++
++}
++
++static void
++dhd_os_rxfunlock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd;
++
++	dhd = (dhd_info_t *)(pub->info);
++	spin_unlock_bh(&dhd->rxf_lock);
++}
++
++#ifdef DHDTCPACK_SUPPRESS
++unsigned long
++dhd_os_tcpacklock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd;
++	unsigned long flags = 0;
++
++	dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++#ifdef BCMSDIO
++		spin_lock_bh(&dhd->tcpack_lock);
++#else
++		spin_lock_irqsave(&dhd->tcpack_lock, flags);
++#endif /* BCMSDIO */
++	}
++
++	return flags;
++}
++
++void
++dhd_os_tcpackunlock(dhd_pub_t *pub, unsigned long flags)
++{
++	dhd_info_t *dhd;
++
++#ifdef BCMSDIO
++	BCM_REFERENCE(flags);
++#endif /* BCMSDIO */
++
++	dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++#ifdef BCMSDIO
++		spin_unlock_bh(&dhd->tcpack_lock);
++#else
++		spin_unlock_irqrestore(&dhd->tcpack_lock, flags);
++#endif /* BCMSDIO */
++	}
++}
++#endif /* DHDTCPACK_SUPPRESS */
++
++uint8* dhd_os_prealloc(dhd_pub_t *dhdpub, int section, uint size, bool kmalloc_if_fail)
++{
++	uint8* buf;
++	gfp_t flags = CAN_SLEEP() ? GFP_KERNEL: GFP_ATOMIC;
++
++	buf = (uint8*)wifi_platform_prealloc(dhdpub->info->adapter, section, size);
++	if (buf == NULL && kmalloc_if_fail)
++		buf = kmalloc(size, flags);
++
++	return buf;
++}
++
++void dhd_os_prefree(dhd_pub_t *dhdpub, void *addr, uint size)
++{
++}
++
++#if defined(WL_WIRELESS_EXT)
++struct iw_statistics *
++dhd_get_wireless_stats(struct net_device *dev)
++{
++	int res = 0;
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	if (!dhd->pub.up) {
++		return NULL;
++	}
++
++	res = wl_iw_get_wireless_stats(dev, &dhd->iw.wstats);
++
++	if (res == 0)
++		return &dhd->iw.wstats;
++	else
++		return NULL;
++}
++#endif /* defined(WL_WIRELESS_EXT) */
++
++static int
++dhd_wl_host_event(dhd_info_t *dhd, int *ifidx, void *pktdata,
++	wl_event_msg_t *event, void **data)
++{
++	int bcmerror = 0;
++	ASSERT(dhd != NULL);
++
++#ifdef SHOW_LOGTRACE
++		bcmerror = wl_host_event(&dhd->pub, ifidx, pktdata, event, data, &dhd->event_data);
++#else
++		bcmerror = wl_host_event(&dhd->pub, ifidx, pktdata, event, data, NULL);
++#endif /* SHOW_LOGTRACE */
++
++	if (bcmerror != BCME_OK)
++		return (bcmerror);
++
++#if defined(WL_WIRELESS_EXT)
++	if (event->bsscfgidx == 0) {
++		/*
++		 * Wireless ext is on primary interface only
++		 */
++
++	ASSERT(dhd->iflist[*ifidx] != NULL);
++	ASSERT(dhd->iflist[*ifidx]->net != NULL);
++
++		if (dhd->iflist[*ifidx]->net) {
++		wl_iw_event(dhd->iflist[*ifidx]->net, event, *data);
++		}
++	}
++#endif /* defined(WL_WIRELESS_EXT)  */
++
++#ifdef WL_CFG80211
++	ASSERT(dhd->iflist[*ifidx] != NULL);
++	ASSERT(dhd->iflist[*ifidx]->net != NULL);
++	if (dhd->iflist[*ifidx]->net)
++		wl_cfg80211_event(dhd->iflist[*ifidx]->net, event, *data);
++#endif /* defined(WL_CFG80211) */
++
++	return (bcmerror);
++}
++
++/* send up locally generated event */
++void
++dhd_sendup_event(dhd_pub_t *dhdp, wl_event_msg_t *event, void *data)
++{
++	switch (ntoh32(event->event_type)) {
++
++	default:
++		break;
++	}
++}
++
++#ifdef LOG_INTO_TCPDUMP
++void
++dhd_sendup_log(dhd_pub_t *dhdp, void *data, int data_len)
++{
++	struct sk_buff *p, *skb;
++	uint32 pktlen;
++	int len;
++	dhd_if_t *ifp;
++	dhd_info_t *dhd;
++	uchar *skb_data;
++	int ifidx = 0;
++	struct ether_header eth;
++
++	pktlen = sizeof(eth) + data_len;
++	dhd = dhdp->info;
++
++	if ((p = PKTGET(dhdp->osh, pktlen, FALSE))) {
++		ASSERT(ISALIGNED((uintptr)PKTDATA(dhdp->osh, p), sizeof(uint32)));
++
++		bcopy(&dhdp->mac, &eth.ether_dhost, ETHER_ADDR_LEN);
++		bcopy(&dhdp->mac, &eth.ether_shost, ETHER_ADDR_LEN);
++		ETHER_TOGGLE_LOCALADDR(&eth.ether_shost);
++		eth.ether_type = hton16(ETHER_TYPE_BRCM);
++
++		bcopy((void *)&eth, PKTDATA(dhdp->osh, p), sizeof(eth));
++		bcopy(data, PKTDATA(dhdp->osh, p) + sizeof(eth), data_len);
++		skb = PKTTONATIVE(dhdp->osh, p);
++		skb_data = skb->data;
++		len = skb->len;
++
++		ifidx = dhd_ifname2idx(dhd, "wlan0");
++		ifp = dhd->iflist[ifidx];
++		if (ifp == NULL)
++			 ifp = dhd->iflist[0];
++
++		ASSERT(ifp);
++		skb->dev = ifp->net;
++		skb->protocol = eth_type_trans(skb, skb->dev);
++		skb->data = skb_data;
++		skb->len = len;
++
++		/* Strip header, count, deliver upward */
++		skb_pull(skb, ETH_HLEN);
++
++		bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE,
++			__FUNCTION__, __LINE__);
++		/* Send the packet */
++		if (in_interrupt()) {
++			netif_rx(skb);
++		} else {
++			netif_rx_ni(skb);
++		}
++	}
++	else {
++		/* Could not allocate a sk_buf */
++		DHD_ERROR(("%s: unable to alloc sk_buf", __FUNCTION__));
++	}
++}
++#endif /* LOG_INTO_TCPDUMP */
++
++void dhd_wait_for_event(dhd_pub_t *dhd, bool *lockvar)
++{
++#if defined(BCMSDIO) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++	struct dhd_info *dhdinfo =  dhd->info;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++	int timeout = msecs_to_jiffies(IOCTL_RESP_TIMEOUT);
++#else
++	int timeout = (IOCTL_RESP_TIMEOUT / 1000) * HZ;
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
++
++	dhd_os_sdunlock(dhd);
++	wait_event_timeout(dhdinfo->ctrl_wait, (*lockvar == FALSE), timeout);
++	dhd_os_sdlock(dhd);
++#endif /* defined(BCMSDIO) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)) */
++	return;
++}
++
++void dhd_wait_event_wakeup(dhd_pub_t *dhd)
++{
++#if defined(BCMSDIO) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++	struct dhd_info *dhdinfo =  dhd->info;
++	if (waitqueue_active(&dhdinfo->ctrl_wait))
++		wake_up(&dhdinfo->ctrl_wait);
++#endif
++	return;
++}
++
++#if defined(BCMSDIO) || defined(BCMPCIE)
++int
++dhd_net_bus_devreset(struct net_device *dev, uint8 flag)
++{
++	int ret;
++
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	if (flag == TRUE) {
++		/* Issue wl down command before resetting the chip */
++		if (dhd_wl_ioctl_cmd(&dhd->pub, WLC_DOWN, NULL, 0, TRUE, 0) < 0) {
++			DHD_TRACE(("%s: wl down failed\n", __FUNCTION__));
++		}
++#ifdef PROP_TXSTATUS
++		if (dhd->pub.wlfc_enabled) {
++			dhd_wlfc_deinit(&dhd->pub);
++		}
++#endif /* PROP_TXSTATUS */
++#ifdef PNO_SUPPORT
++		if (dhd->pub.pno_state) {
++			dhd_pno_deinit(&dhd->pub);
++		}
++#endif
++#ifdef RTT_SUPPORT
++		if (dhd->pub.rtt_state) {
++			dhd_rtt_deinit(&dhd->pub);
++		}
++#endif /* RTT_SUPPORT */
++	}
++
++#ifdef BCMSDIO
++	if (!flag) {
++		dhd_update_fw_nv_path(dhd);
++		/* update firmware and nvram path to sdio bus */
++		dhd_bus_update_fw_nv_path(dhd->pub.bus,
++			dhd->fw_path, dhd->nv_path);
++	}
++#endif /* BCMSDIO */
++
++	ret = dhd_bus_devreset(&dhd->pub, flag);
++	if (ret) {
++		DHD_ERROR(("%s: dhd_bus_devreset: %d\n", __FUNCTION__, ret));
++		return ret;
++	}
++
++	return ret;
++}
++
++#ifdef BCMSDIO
++int
++dhd_net_bus_suspend(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	return dhd_bus_suspend(&dhd->pub);
++}
++
++int
++dhd_net_bus_resume(struct net_device *dev, uint8 stage)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	return dhd_bus_resume(&dhd->pub, stage);
++}
++
++#endif /* BCMSDIO */
++#endif /* BCMSDIO || BCMPCIE */
++
++int net_os_set_suspend_disable(struct net_device *dev, int val)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret = 0;
++
++	if (dhd) {
++		ret = dhd->pub.suspend_disable_flag;
++		dhd->pub.suspend_disable_flag = val;
++	}
++	return ret;
++}
++
++int net_os_set_suspend(struct net_device *dev, int val, int force)
++{
++	int ret = 0;
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	if (dhd) {
++#ifdef CONFIG_MACH_UNIVERSAL7420
++#endif /* CONFIG_MACH_UNIVERSAL7420 */
++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND)
++		ret = dhd_set_suspend(val, &dhd->pub);
++#else
++		ret = dhd_suspend_resume_helper(dhd, val, force);
++#endif
++#ifdef WL_CFG80211
++		wl_cfg80211_update_power_mode(dev);
++#endif
++	}
++	return ret;
++}
++
++int net_os_set_suspend_bcn_li_dtim(struct net_device *dev, int val)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	if (dhd)
++		dhd->pub.suspend_bcn_li_dtim = val;
++
++	return 0;
++}
++
++#ifdef PKT_FILTER_SUPPORT
++int net_os_rxfilter_add_remove(struct net_device *dev, int add_remove, int num)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	char *filterp = NULL;
++	int filter_id = 0;
++	int ret = 0;
++
++	if (!dhd || (num == DHD_UNICAST_FILTER_NUM) ||
++		(num == DHD_MDNS_FILTER_NUM))
++		return ret;
++	if (num >= dhd->pub.pktfilter_count)
++		return -EINVAL;
++	switch (num) {
++		case DHD_BROADCAST_FILTER_NUM:
++			filterp = "101 0 0 0 0xFFFFFFFFFFFF 0xFFFFFFFFFFFF";
++			filter_id = 101;
++			break;
++		case DHD_MULTICAST4_FILTER_NUM:
++			filterp = "102 0 0 0 0xFFFFFF 0x01005E";
++			filter_id = 102;
++			break;
++		case DHD_MULTICAST6_FILTER_NUM:
++			filterp = "103 0 0 0 0xFFFF 0x3333";
++			filter_id = 103;
++			break;
++		default:
++			return -EINVAL;
++	}
++
++	/* Add filter */
++	if (add_remove) {
++		dhd->pub.pktfilter[num] = filterp;
++		dhd_pktfilter_offload_set(&dhd->pub, dhd->pub.pktfilter[num]);
++	} else { /* Delete filter */
++		if (dhd->pub.pktfilter[num] != NULL) {
++			dhd_pktfilter_offload_delete(&dhd->pub, filter_id);
++			dhd->pub.pktfilter[num] = NULL;
++		}
++	}
++	return ret;
++}
++
++int dhd_os_enable_packet_filter(dhd_pub_t *dhdp, int val)
++
++{
++	int ret = 0;
++
++	/* Packet filtering is set only if we still in early-suspend and
++	 * we need either to turn it ON or turn it OFF
++	 * We can always turn it OFF in case of early-suspend, but we turn it
++	 * back ON only if suspend_disable_flag was not set
++	*/
++	if (dhdp && dhdp->up) {
++		if (dhdp->in_suspend) {
++			if (!val || (val && !dhdp->suspend_disable_flag))
++				dhd_enable_packet_filter(val, dhdp);
++		}
++	}
++	return ret;
++}
++
++/* function to enable/disable packet for Network device */
++int net_os_enable_packet_filter(struct net_device *dev, int val)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	return dhd_os_enable_packet_filter(&dhd->pub, val);
++}
++#endif /* PKT_FILTER_SUPPORT */
++
++int
++dhd_dev_init_ioctl(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret;
++
++	if ((ret = dhd_sync_with_dongle(&dhd->pub)) < 0)
++		goto done;
++
++done:
++	return ret;
++}
++
++int
++dhd_dev_get_feature_set(struct net_device *dev)
++{
++	dhd_info_t *ptr = *(dhd_info_t **)netdev_priv(dev);
++	dhd_pub_t *dhd = (&ptr->pub);
++	int feature_set = 0;
++
++#ifdef DYNAMIC_SWOOB_DURATION
++#ifndef CUSTOM_INTR_WIDTH
++#define CUSTOM_INTR_WIDTH 100
++	int intr_width = 0;
++#endif /* CUSTOM_INTR_WIDTH */
++#endif /* DYNAMIC_SWOOB_DURATION */
++	if (!dhd)
++		return feature_set;
++
++	if (FW_SUPPORTED(dhd, sta))
++		feature_set |= WIFI_FEATURE_INFRA;
++	if (FW_SUPPORTED(dhd, dualband))
++		feature_set |= WIFI_FEATURE_INFRA_5G;
++	if (FW_SUPPORTED(dhd, p2p))
++		feature_set |= WIFI_FEATURE_P2P;
++	if (dhd->op_mode & DHD_FLAG_HOSTAP_MODE)
++		feature_set |= WIFI_FEATURE_SOFT_AP;
++	if (FW_SUPPORTED(dhd, tdls))
++		feature_set |= WIFI_FEATURE_TDLS;
++	if (FW_SUPPORTED(dhd, vsdb))
++		feature_set |= WIFI_FEATURE_TDLS_OFFCHANNEL;
++	if (FW_SUPPORTED(dhd, nan)) {
++		feature_set |= WIFI_FEATURE_NAN;
++		/* NAN is essentail for d2d rtt */
++		if (FW_SUPPORTED(dhd, rttd2d))
++			feature_set |= WIFI_FEATURE_D2D_RTT;
++	}
++#ifdef RTT_SUPPORT
++	feature_set |= WIFI_FEATURE_D2AP_RTT;
++#endif /* RTT_SUPPORT */
++#ifdef LINKSTAT_SUPPORT
++	feature_set |= WIFI_FEATURE_LINKSTAT;
++#endif /* LINKSTAT_SUPPORT */
++	/* Supports STA + STA always */
++	feature_set |= WIFI_FEATURE_ADDITIONAL_STA;
++#ifdef PNO_SUPPORT
++	if (dhd_is_pno_supported(dhd)) {
++		feature_set |= WIFI_FEATURE_PNO;
++		feature_set |= WIFI_FEATURE_BATCH_SCAN;
++#ifdef GSCAN_SUPPORT
++		feature_set |= WIFI_FEATURE_GSCAN;
++#endif /* GSCAN_SUPPORT */
++	}
++	if (FW_SUPPORTED(dhd, rssi_mon)) {
++		feature_set |= WIFI_FEATURE_RSSI_MONITOR;
++	}
++#endif /* PNO_SUPPORT */
++#ifdef WL11U
++	feature_set |= WIFI_FEATURE_HOTSPOT;
++#endif /* WL11U */
++	return feature_set;
++}
++
++int *dhd_dev_get_feature_set_matrix(struct net_device *dev, int *num)
++{
++	int feature_set_full, mem_needed;
++	int *ret;
++
++	*num = 0;
++	mem_needed = sizeof(int) * MAX_FEATURE_SET_CONCURRRENT_GROUPS;
++	ret = (int *) kmalloc(mem_needed, GFP_KERNEL);
++	if (!ret) {
++		DHD_ERROR(("%s: failed to allocate %d bytes\n", __FUNCTION__,
++			mem_needed));
++		return ret;
++	}
++
++	feature_set_full = dhd_dev_get_feature_set(dev);
++
++	ret[0] = (feature_set_full & WIFI_FEATURE_INFRA) |
++	         (feature_set_full & WIFI_FEATURE_INFRA_5G) |
++	         (feature_set_full & WIFI_FEATURE_NAN) |
++	         (feature_set_full & WIFI_FEATURE_D2D_RTT) |
++	         (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
++	         (feature_set_full & WIFI_FEATURE_PNO) |
++	         (feature_set_full & WIFI_FEATURE_HAL_EPNO) |
++	         (feature_set_full & WIFI_FEATURE_RSSI_MONITOR) |
++	         (feature_set_full & WIFI_FEATURE_BATCH_SCAN) |
++	         (feature_set_full & WIFI_FEATURE_GSCAN) |
++	         (feature_set_full & WIFI_FEATURE_HOTSPOT) |
++	         (feature_set_full & WIFI_FEATURE_ADDITIONAL_STA) |
++	         (feature_set_full & WIFI_FEATURE_EPR);
++
++	ret[1] = (feature_set_full & WIFI_FEATURE_INFRA) |
++	         (feature_set_full & WIFI_FEATURE_INFRA_5G) |
++	         (feature_set_full & WIFI_FEATURE_RSSI_MONITOR) |
++	         /* Not yet verified NAN with P2P */
++	         /* (feature_set_full & WIFI_FEATURE_NAN) | */
++	         (feature_set_full & WIFI_FEATURE_P2P) |
++	         (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
++	         (feature_set_full & WIFI_FEATURE_D2D_RTT) |
++	         (feature_set_full & WIFI_FEATURE_EPR);
++
++	ret[2] = (feature_set_full & WIFI_FEATURE_INFRA) |
++	         (feature_set_full & WIFI_FEATURE_INFRA_5G) |
++	         (feature_set_full & WIFI_FEATURE_RSSI_MONITOR) |
++	         (feature_set_full & WIFI_FEATURE_NAN) |
++	         (feature_set_full & WIFI_FEATURE_D2D_RTT) |
++	         (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
++	         (feature_set_full & WIFI_FEATURE_TDLS) |
++	         (feature_set_full & WIFI_FEATURE_TDLS_OFFCHANNEL) |
++	         (feature_set_full & WIFI_FEATURE_EPR);
++	*num = MAX_FEATURE_SET_CONCURRRENT_GROUPS;
++
++	return ret;
++}
++#ifdef CUSTOM_FORCE_NODFS_FLAG
++int
++dhd_dev_set_nodfs(struct net_device *dev, u32 nodfs)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	if (nodfs)
++		dhd->pub.dhd_cflags |= WLAN_PLAT_NODFS_FLAG;
++	else
++		dhd->pub.dhd_cflags &= ~WLAN_PLAT_NODFS_FLAG;
++	dhd->pub.force_country_change = TRUE;
++	return 0;
++}
++#endif /* CUSTOM_FORCE_NODFS_FLAG */
++#ifdef PNO_SUPPORT
++/* Linux wrapper to call common dhd_pno_stop_for_ssid */
++int
++dhd_dev_pno_stop_for_ssid(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	return (dhd_pno_stop_for_ssid(&dhd->pub));
++}
++/* Linux wrapper to call common dhd_pno_set_for_ssid */
++int
++dhd_dev_pno_set_for_ssid(struct net_device *dev, wlc_ssid_ext_t* ssids_local, int nssid,
++	uint16  scan_fr, int pno_repeat, int pno_freq_expo_max, uint16 *channel_list, int nchan)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	return (dhd_pno_set_for_ssid(&dhd->pub, ssids_local, nssid, scan_fr,
++		pno_repeat, pno_freq_expo_max, channel_list, nchan));
++}
++
++/* Linux wrapper to call common dhd_pno_enable */
++int
++dhd_dev_pno_enable(struct net_device *dev, int enable)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	return (dhd_pno_enable(&dhd->pub, enable));
++}
++
++/* Linux wrapper to call common dhd_pno_set_for_hotlist */
++int
++dhd_dev_pno_set_for_hotlist(struct net_device *dev, wl_pfn_bssid_t *p_pfn_bssid,
++	struct dhd_pno_hotlist_params *hotlist_params)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	return (dhd_pno_set_for_hotlist(&dhd->pub, p_pfn_bssid, hotlist_params));
++}
++/* Linux wrapper to call common dhd_dev_pno_stop_for_batch */
++int
++dhd_dev_pno_stop_for_batch(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	return (dhd_pno_stop_for_batch(&dhd->pub));
++}
++/* Linux wrapper to call common dhd_dev_pno_set_for_batch */
++int
++dhd_dev_pno_set_for_batch(struct net_device *dev, struct dhd_pno_batch_params *batch_params)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	return (dhd_pno_set_for_batch(&dhd->pub, batch_params));
++}
++/* Linux wrapper to call common dhd_dev_pno_get_for_batch */
++int
++dhd_dev_pno_get_for_batch(struct net_device *dev, char *buf, int bufsize)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	return (dhd_pno_get_for_batch(&dhd->pub, buf, bufsize, PNO_STATUS_NORMAL));
++}
++
++bool
++dhd_dev_is_legacy_pno_enabled(struct net_device *dev)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_is_legacy_pno_enabled(&dhd->pub));
++}
++#endif /* PNO_SUPPORT */
++
++#if defined(PNO_SUPPORT)
++#ifdef GSCAN_SUPPORT
++/* Linux wrapper to call common dhd_pno_set_cfg_gscan */
++int
++dhd_dev_pno_set_cfg_gscan(struct net_device *dev, dhd_pno_gscan_cmd_cfg_t type,
++ void *buf, uint8 flush)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_pno_set_cfg_gscan(&dhd->pub, type, buf, flush));
++}
++
++/* Linux wrapper to call common dhd_pno_get_gscan */
++void *
++dhd_dev_pno_get_gscan(struct net_device *dev, dhd_pno_gscan_cmd_cfg_t type,
++                      void *info, uint32 *len)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_pno_get_gscan(&dhd->pub, type, info, len));
++}
++
++/* Linux wrapper to call common dhd_wait_batch_results_complete */
++int
++dhd_dev_wait_batch_results_complete(struct net_device *dev)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_wait_batch_results_complete(&dhd->pub));
++}
++
++/* Linux wrapper to call common dhd_pno_lock_batch_results */
++int
++dhd_dev_pno_lock_access_batch_results(struct net_device *dev)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_pno_lock_batch_results(&dhd->pub));
++}
++/* Linux wrapper to call common dhd_pno_unlock_batch_results */
++void
++dhd_dev_pno_unlock_access_batch_results(struct net_device *dev)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_pno_unlock_batch_results(&dhd->pub));
++}
++
++/* Linux wrapper to call common dhd_pno_initiate_gscan_request */
++int
++dhd_dev_pno_run_gscan(struct net_device *dev, bool run, bool flush)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_pno_initiate_gscan_request(&dhd->pub, run, flush));
++}
++
++/* Linux wrapper to call common dhd_pno_enable_full_scan_result */
++int
++dhd_dev_pno_enable_full_scan_result(struct net_device *dev, bool real_time_flag)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_pno_enable_full_scan_result(&dhd->pub, real_time_flag));
++}
++
++/* Linux wrapper to call common dhd_handle_swc_evt */
++void *
++dhd_dev_swc_scan_event(struct net_device *dev, const void  *data, int *send_evt_bytes)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_handle_swc_evt(&dhd->pub, data, send_evt_bytes));
++}
++
++/* Linux wrapper to call common dhd_handle_hotlist_scan_evt */
++void *
++dhd_dev_hotlist_scan_event(struct net_device *dev,
++      const void  *data, int *send_evt_bytes, hotlist_type_t type)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_handle_hotlist_scan_evt(&dhd->pub, data, send_evt_bytes, type));
++}
++
++/* Linux wrapper to call common dhd_process_full_gscan_result */
++void *
++dhd_dev_process_full_gscan_result(struct net_device *dev,
++const void  *data, uint32 len, int *send_evt_bytes)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_process_full_gscan_result(&dhd->pub, data, len, send_evt_bytes));
++}
++
++void
++dhd_dev_gscan_hotlist_cache_cleanup(struct net_device *dev, hotlist_type_t type)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	dhd_gscan_hotlist_cache_cleanup(&dhd->pub, type);
++
++	return;
++}
++
++int
++dhd_dev_gscan_batch_cache_cleanup(struct net_device *dev)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_gscan_batch_cache_cleanup(&dhd->pub));
++}
++
++/* Linux wrapper to call common dhd_retreive_batch_scan_results */
++int
++dhd_dev_retrieve_batch_scan(struct net_device *dev)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_retreive_batch_scan_results(&dhd->pub));
++}
++/* Linux wrapper to call common dhd_pno_process_epno_result */
++void *
++dhd_dev_process_epno_result(struct net_device *dev,
++		const void  *data, uint32 event, int *send_evt_bytes)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_pno_process_epno_result(&dhd->pub, data, event, send_evt_bytes));
++}
++
++int
++dhd_dev_set_lazy_roam_cfg(struct net_device *dev,
++             wlc_roam_exp_params_t *roam_param)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	wl_roam_exp_cfg_t roam_exp_cfg;
++	int err;
++
++	if (!roam_param) {
++		return BCME_BADARG;
++	}
++
++	DHD_ERROR(("a_band_boost_thr %d a_band_penalty_thr %d\n",
++	      roam_param->a_band_boost_threshold, roam_param->a_band_penalty_threshold));
++	DHD_ERROR(("a_band_boost_factor %d a_band_penalty_factor %d cur_bssid_boost %d\n",
++	      roam_param->a_band_boost_factor, roam_param->a_band_penalty_factor,
++	      roam_param->cur_bssid_boost));
++	DHD_ERROR(("alert_roam_trigger_thr %d a_band_max_boost %d\n",
++	      roam_param->alert_roam_trigger_threshold, roam_param->a_band_max_boost));
++
++	memcpy(&roam_exp_cfg.params, roam_param, sizeof(*roam_param));
++	roam_exp_cfg.version = ROAM_EXP_CFG_VERSION;
++	roam_exp_cfg.flags = ROAM_EXP_CFG_PRESENT;
++	if (dhd->pub.lazy_roam_enable) {
++		roam_exp_cfg.flags |= ROAM_EXP_ENABLE_FLAG;
++	}
++	err = dhd_iovar(&dhd->pub, 0, "roam_exp_params",
++			(char *)&roam_exp_cfg, sizeof(roam_exp_cfg), NULL, 0,
++			TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : Failed to execute roam_exp_params %d\n", __FUNCTION__, err));
++	}
++	return err;
++}
++
++int
++dhd_dev_lazy_roam_enable(struct net_device *dev, uint32 enable)
++{
++	int err;
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	wl_roam_exp_cfg_t roam_exp_cfg;
++
++	memset(&roam_exp_cfg, 0, sizeof(roam_exp_cfg));
++	roam_exp_cfg.version = ROAM_EXP_CFG_VERSION;
++	if (enable) {
++		roam_exp_cfg.flags = ROAM_EXP_ENABLE_FLAG;
++	}
++
++	err = dhd_iovar(&dhd->pub, 0, "roam_exp_params",
++			(char *)&roam_exp_cfg, sizeof(roam_exp_cfg), NULL, 0,
++			TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : Failed to execute roam_exp_params %d\n", __FUNCTION__, err));
++	} else {
++		dhd->pub.lazy_roam_enable = (enable != 0);
++	}
++	return err;
++}
++int
++dhd_dev_set_lazy_roam_bssid_pref(struct net_device *dev,
++       wl_bssid_pref_cfg_t *bssid_pref, uint32 flush)
++{
++	int err;
++	int len;
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	bssid_pref->version = BSSID_PREF_LIST_VERSION;
++	/* By default programming bssid pref flushes out old values */
++	bssid_pref->flags = (flush && !bssid_pref->count) ? ROAM_EXP_CLEAR_BSSID_PREF: 0;
++	len = sizeof(wl_bssid_pref_cfg_t);
++	len += (bssid_pref->count - 1) * sizeof(wl_bssid_pref_list_t);
++	err = dhd_iovar(&dhd->pub, 0, "roam_exp_bssid_pref",
++			(char *)bssid_pref, len, NULL, 0, TRUE);
++	if (err != BCME_OK) {
++		DHD_ERROR(("%s : Failed to execute roam_exp_bssid_pref %d\n", __FUNCTION__, err));
++	}
++	return err;
++}
++int
++dhd_dev_set_blacklist_bssid(struct net_device *dev, maclist_t *blacklist,
++    uint32 len, uint32 flush)
++{
++	int err;
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	int macmode;
++
++	if (blacklist) {
++		err = dhd_wl_ioctl_cmd(&(dhd->pub), WLC_SET_MACLIST, (char *)blacklist,
++				len, TRUE, 0);
++		if (err != BCME_OK) {
++			DHD_ERROR(("%s : WLC_SET_MACLIST failed %d\n", __FUNCTION__, err));
++			return err;
++		}
++	}
++	/* By default programming blacklist flushes out old values */
++	macmode = (flush && !blacklist) ? WLC_MACMODE_DISABLED : WLC_MACMODE_DENY;
++	err = dhd_wl_ioctl_cmd(&(dhd->pub), WLC_SET_MACMODE, (char *)&macmode,
++	              sizeof(macmode), TRUE, 0);
++	if (err != BCME_OK) {
++		DHD_ERROR(("%s : WLC_SET_MACMODE failed %d\n", __FUNCTION__, err));
++	}
++	return err;
++}
++int
++dhd_dev_set_whitelist_ssid(struct net_device *dev, wl_ssid_whitelist_t *ssid_whitelist,
++    uint32 len, uint32 flush)
++{
++	int err;
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	wl_ssid_whitelist_t whitelist_ssid_flush;
++
++	if (!ssid_whitelist) {
++		if (flush) {
++			ssid_whitelist = &whitelist_ssid_flush;
++			ssid_whitelist->ssid_count = 0;
++		} else {
++			DHD_ERROR(("%s : Nothing to do here\n", __FUNCTION__));
++			return BCME_BADARG;
++		}
++	}
++	ssid_whitelist->version = SSID_WHITELIST_VERSION;
++	ssid_whitelist->flags = flush ? ROAM_EXP_CLEAR_SSID_WHITELIST : 0;
++	err = dhd_iovar(&dhd->pub, 0, "roam_exp_ssid_whitelist", (char *)ssid_whitelist, len, NULL,
++			0, TRUE);
++	if (err != BCME_OK) {
++		DHD_ERROR(("%s : Failed to execute roam_exp_bssid_pref %d\n", __FUNCTION__, err));
++	}
++	return err;
++}
++
++#endif /* GSCAN_SUPPORT */
++#endif 
++int
++dhd_dev_set_rssi_monitor_cfg(struct net_device *dev, int start,
++             int8 max_rssi, int8 min_rssi)
++{
++	int err;
++	wl_rssi_monitor_cfg_t rssi_monitor;
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	rssi_monitor.version = RSSI_MONITOR_VERSION;
++	rssi_monitor.max_rssi = max_rssi;
++	rssi_monitor.min_rssi = min_rssi;
++	rssi_monitor.flags = start ? 0: RSSI_MONITOR_STOP;
++	err = dhd_iovar(&dhd->pub, 0, "rssi_monitor", (char *)&rssi_monitor, sizeof(rssi_monitor),
++			NULL, 0, TRUE);
++	if (err < 0 && err != BCME_UNSUPPORTED) {
++		DHD_ERROR(("%s : Failed to execute rssi_monitor %d\n", __FUNCTION__, err));
++	}
++	return err;
++}
++
++int
++dhd_dev_cfg_rand_mac_oui(struct net_device *dev, uint8 *oui)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	dhd_pub_t *dhdp = &dhd->pub;
++
++	if (!dhdp || !oui) {
++		DHD_ERROR(("NULL POINTER : %s\n",
++			__FUNCTION__));
++		return BCME_ERROR;
++	}
++	if (ETHER_ISMULTI(oui)) {
++		DHD_ERROR(("Expected unicast OUI\n"));
++		return BCME_ERROR;
++	} else {
++		uint8 *rand_mac_oui = dhdp->rand_mac_oui;
++		memcpy(rand_mac_oui, oui, DOT11_OUI_LEN);
++		DHD_ERROR(("Random MAC OUI to be used - %02x:%02x:%02x\n", rand_mac_oui[0],
++		    rand_mac_oui[1], rand_mac_oui[2]));
++	}
++	return BCME_OK;
++}
++
++int
++dhd_set_rand_mac_oui(dhd_pub_t *dhd)
++{
++	int err;
++	wl_pfn_macaddr_cfg_t cfg;
++	uint8 *rand_mac_oui = dhd->rand_mac_oui;
++
++	memset(&cfg.macaddr, 0, ETHER_ADDR_LEN);
++	memcpy(&cfg.macaddr, rand_mac_oui, DOT11_OUI_LEN);
++	cfg.version = WL_PFN_MACADDR_CFG_VER;
++	if (ETHER_ISNULLADDR(&cfg.macaddr))
++		cfg.flags = 0;
++	else
++		cfg.flags = (WL_PFN_MAC_OUI_ONLY_MASK | WL_PFN_SET_MAC_UNASSOC_MASK);
++
++	DHD_ERROR(("Setting rand mac oui to FW - %02x:%02x:%02x\n", rand_mac_oui[0],
++	    rand_mac_oui[1], rand_mac_oui[2]));
++
++	err = dhd_iovar(dhd, 0, "pfn_macaddr", (char *)&cfg, sizeof(cfg), NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfn_macaddr %d\n", __FUNCTION__, err));
++	}
++	return err;
++}
++#ifdef RTT_SUPPORT
++/* Linux wrapper to call common dhd_pno_set_cfg_gscan */
++int
++dhd_dev_rtt_set_cfg(struct net_device *dev, void *buf)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_rtt_set_cfg(&dhd->pub, buf));
++}
++int
++dhd_dev_rtt_cancel_cfg(struct net_device *dev, struct ether_addr *mac_list, int mac_cnt)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_rtt_stop(&dhd->pub, mac_list, mac_cnt));
++}
++int
++dhd_dev_rtt_register_noti_callback(struct net_device *dev, void *ctx, dhd_rtt_compl_noti_fn noti_fn)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_rtt_register_noti_callback(&dhd->pub, ctx, noti_fn));
++}
++int
++dhd_dev_rtt_unregister_noti_callback(struct net_device *dev, dhd_rtt_compl_noti_fn noti_fn)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_rtt_unregister_noti_callback(&dhd->pub, noti_fn));
++}
++
++int
++dhd_dev_rtt_capability(struct net_device *dev, rtt_capabilities_t *capa)
++{
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++
++	return (dhd_rtt_capability(&dhd->pub, capa));
++}
++
++#endif /* RTT_SUPPORT */
++
++#if defined(KEEP_ALIVE)
++#define TEMP_BUF_SIZE 512
++#define TEMP_FRAME_SIZE 300
++int
++dhd_dev_start_mkeep_alive(dhd_pub_t *dhd_pub, u8 mkeep_alive_id, u8 *ip_pkt, u16 ip_pkt_len,
++	u8* src_mac, u8* dst_mac, u32 period_msec)
++{
++	char			*pbuf;
++	const char		*str;
++	wl_mkeep_alive_pkt_t mkeep_alive_pkt = {0};
++	wl_mkeep_alive_pkt_t *mkeep_alive_pktp;
++	int				buf_len;
++	int				str_len;
++	int			res = BCME_ERROR;
++	int			len_bytes = 0;
++	int			i;
++
++	/* ether frame to have both max IP pkt (256 bytes) and ether header */
++	char			*pmac_frame;
++
++	/*
++	 * The mkeep_alive packet is for STA interface only; if the bss is configured as AP,
++	 * dongle shall reject a mkeep_alive request.
++	 */
++	if (!dhd_support_sta_mode(dhd_pub))
++		return res;
++
++	DHD_TRACE(("%s execution\n", __FUNCTION__));
++
++	if ((pbuf = kzalloc(TEMP_BUF_SIZE, GFP_KERNEL)) == NULL) {
++		DHD_ERROR(("failed to allocate buf with size %d\n", TEMP_BUF_SIZE));
++		res = BCME_NOMEM;
++		return res;
++	}
++
++	if ((pmac_frame = kzalloc(TEMP_FRAME_SIZE, GFP_KERNEL)) == NULL) {
++		DHD_ERROR(("failed to allocate mac_frame with size %d\n", TEMP_FRAME_SIZE));
++		res = BCME_NOMEM;
++		goto exit;
++	}
++
++	/*
++	 * Get current mkeep-alive status.
++	 */
++	bcm_mkiovar("mkeep_alive", &mkeep_alive_id, sizeof(mkeep_alive_id),
++		pbuf, TEMP_BUF_SIZE);
++
++	if ((res = dhd_wl_ioctl_cmd(dhd_pub, WLC_GET_VAR, pbuf, TEMP_BUF_SIZE,
++		FALSE, 0)) < 0) {
++		DHD_ERROR(("%s: Get mkeep_alive failed (error=%d)\n", __FUNCTION__, res));
++		goto exit;
++	} else {
++		/* Check available ID whether it is occupied */
++		mkeep_alive_pktp = (wl_mkeep_alive_pkt_t *) pbuf;
++		if (dtoh32(mkeep_alive_pktp->period_msec != 0)) {
++			DHD_ERROR(("%s: Get mkeep_alive failed, ID %u is in use.\n",
++				__FUNCTION__, mkeep_alive_id));
++
++			/* Current occupied ID info */
++			DHD_ERROR(("%s: mkeep_alive\n", __FUNCTION__));
++			DHD_ERROR(("   Id    : %d\n"
++				"   Period: %d msec\n"
++				"   Length: %d\n"
++				"   Packet: 0x",
++				mkeep_alive_pktp->keep_alive_id,
++				dtoh32(mkeep_alive_pktp->period_msec),
++				dtoh16(mkeep_alive_pktp->len_bytes)));
++
++			for (i = 0; i < mkeep_alive_pktp->len_bytes; i++) {
++				DHD_ERROR(("%02x", mkeep_alive_pktp->data[i]));
++			}
++			DHD_ERROR(("\n"));
++
++			res = BCME_NOTFOUND;
++			goto exit;
++		}
++	}
++
++	/* Request the specified ID */
++	memset(&mkeep_alive_pkt, 0, sizeof(wl_mkeep_alive_pkt_t));
++	memset(pbuf, 0, TEMP_BUF_SIZE);
++	str = "mkeep_alive";
++	str_len = strlen(str);
++	strncpy(pbuf, str, str_len);
++	pbuf[str_len] = '\0';
++
++	mkeep_alive_pktp = (wl_mkeep_alive_pkt_t *) (pbuf + str_len + 1);
++	mkeep_alive_pkt.period_msec = htod32(period_msec);
++	buf_len = str_len + 1;
++	mkeep_alive_pkt.version = htod16(WL_MKEEP_ALIVE_VERSION);
++	mkeep_alive_pkt.length = htod16(WL_MKEEP_ALIVE_FIXED_LEN);
++
++	/* ID assigned */
++	mkeep_alive_pkt.keep_alive_id = mkeep_alive_id;
++
++	buf_len += WL_MKEEP_ALIVE_FIXED_LEN;
++
++	/*
++	 * Build up Ethernet Frame
++	 */
++
++	/* Mapping dest mac addr */
++	memcpy(pmac_frame, dst_mac, ETHER_ADDR_LEN);
++	pmac_frame += ETHER_ADDR_LEN;
++
++	/* Mapping src mac addr */
++	memcpy(pmac_frame, src_mac, ETHER_ADDR_LEN);
++	pmac_frame += ETHER_ADDR_LEN;
++
++	/* Mapping Ethernet type (ETHERTYPE_IP: 0x0800) */
++	*(pmac_frame++) = 0x08;
++	*(pmac_frame++) = 0x00;
++
++	/* Mapping IP pkt */
++	memcpy(pmac_frame, ip_pkt, ip_pkt_len);
++	pmac_frame += ip_pkt_len;
++
++	/*
++	 * Length of ether frame (assume to be all hexa bytes)
++	 *     = src mac + dst mac + ether type + ip pkt len
++	 */
++	len_bytes = ETHER_ADDR_LEN*2 + ETHER_TYPE_LEN + ip_pkt_len;
++	/* Get back to the beginning. */
++	pmac_frame -= len_bytes;
++	memcpy(mkeep_alive_pktp->data, pmac_frame, len_bytes);
++	buf_len += len_bytes;
++	mkeep_alive_pkt.len_bytes = htod16(len_bytes);
++
++	/*
++	 * Keep-alive attributes are set in local variable (mkeep_alive_pkt), and
++	 * then memcpy'ed into buffer (mkeep_alive_pktp) since there is no
++	 * guarantee that the buffer is properly aligned.
++	 */
++	memcpy((char *)mkeep_alive_pktp, &mkeep_alive_pkt, WL_MKEEP_ALIVE_FIXED_LEN);
++
++	res = dhd_wl_ioctl_cmd(dhd_pub, WLC_SET_VAR, pbuf, buf_len, TRUE, 0);
++exit:
++	kfree(pmac_frame);
++	kfree(pbuf);
++	return res;
++}
++
++int
++dhd_dev_stop_mkeep_alive(dhd_pub_t *dhd_pub, u8 mkeep_alive_id)
++{
++	char			*pbuf;
++	const char		*str;
++	wl_mkeep_alive_pkt_t	mkeep_alive_pkt;
++	wl_mkeep_alive_pkt_t	*mkeep_alive_pktp;
++	int			buf_len;
++	int			str_len;
++	int			res = BCME_ERROR;
++	int			i;
++
++	/*
++	 * The mkeep_alive packet is for STA interface only; if the bss is configured as AP,
++	 * dongle shall reject a mkeep_alive request.
++	 */
++	if (!dhd_support_sta_mode(dhd_pub))
++		return res;
++
++	DHD_TRACE(("%s execution\n", __FUNCTION__));
++
++	/*
++	 * Get current mkeep-alive status. Skip ID 0 which is being used for NULL pkt.
++	 */
++	if ((pbuf = kzalloc(TEMP_BUF_SIZE, GFP_KERNEL)) == NULL) {
++		DHD_ERROR(("failed to allocate buf with size %d\n", TEMP_BUF_SIZE));
++		return res;
++	}
++
++	bcm_mkiovar("mkeep_alive", &mkeep_alive_id, sizeof(mkeep_alive_id), pbuf, TEMP_BUF_SIZE);
++
++	if ((res = dhd_wl_ioctl_cmd(dhd_pub, WLC_GET_VAR, pbuf, TEMP_BUF_SIZE, FALSE, 0)) < 0) {
++		DHD_ERROR(("%s: Get mkeep_alive failed (error=%d)\n", __FUNCTION__, res));
++		goto exit;
++	} else {
++		/* Check occupied ID */
++		mkeep_alive_pktp = (wl_mkeep_alive_pkt_t *) pbuf;
++		DHD_INFO(("%s: mkeep_alive\n", __FUNCTION__));
++		DHD_INFO(("   Id    : %d\n"
++			"   Period: %d msec\n"
++			"   Length: %d\n"
++			"   Packet: 0x",
++			mkeep_alive_pktp->keep_alive_id,
++			dtoh32(mkeep_alive_pktp->period_msec),
++			dtoh16(mkeep_alive_pktp->len_bytes)));
++
++		for (i = 0; i < mkeep_alive_pktp->len_bytes; i++) {
++			DHD_INFO(("%02x", mkeep_alive_pktp->data[i]));
++		}
++		DHD_INFO(("\n"));
++	}
++
++	/* Make it stop if available */
++	if (dtoh32(mkeep_alive_pktp->period_msec != 0)) {
++		DHD_INFO(("stop mkeep_alive on ID %d\n", mkeep_alive_id));
++		memset(&mkeep_alive_pkt, 0, sizeof(wl_mkeep_alive_pkt_t));
++		memset(pbuf, 0, TEMP_BUF_SIZE);
++		str = "mkeep_alive";
++		str_len = strlen(str);
++		strncpy(pbuf, str, str_len);
++		pbuf[str_len] = '\0';
++
++		mkeep_alive_pktp = (wl_mkeep_alive_pkt_t *) (pbuf + str_len + 1);
++
++		mkeep_alive_pkt.period_msec = 0;
++		buf_len = str_len + 1;
++		mkeep_alive_pkt.version = htod16(WL_MKEEP_ALIVE_VERSION);
++		mkeep_alive_pkt.length = htod16(WL_MKEEP_ALIVE_FIXED_LEN);
++		mkeep_alive_pkt.keep_alive_id = mkeep_alive_id;
++		buf_len += WL_MKEEP_ALIVE_FIXED_LEN;
++
++		/*
++		 * Keep-alive attributes are set in local variable (mkeep_alive_pkt), and
++		 * then memcpy'ed into buffer (mkeep_alive_pktp) since there is no
++		 * guarantee that the buffer is properly aligned.
++		 */
++		memcpy((char *)mkeep_alive_pktp, &mkeep_alive_pkt, WL_MKEEP_ALIVE_FIXED_LEN);
++
++		res = dhd_wl_ioctl_cmd(dhd_pub, WLC_SET_VAR, pbuf, buf_len, TRUE, 0);
++	} else {
++		DHD_ERROR(("%s: ID %u does not exist.\n", __FUNCTION__, mkeep_alive_id));
++		res = BCME_NOTFOUND;
++	}
++exit:
++	kfree(pbuf);
++	return res;
++}
++#endif /* defined(KEEP_ALIVE) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++static void dhd_hang_process(void *dhd_info, void *event_info, u8 event)
++{
++	dhd_info_t *dhd;
++	struct net_device *dev;
++
++	dhd = (dhd_info_t *)dhd_info;
++	dev = dhd->iflist[0]->net;
++
++	if (dev) {
++		rtnl_lock();
++		dev_close(dev);
++		rtnl_unlock();
++#if defined(WL_WIRELESS_EXT)
++		wl_iw_send_priv_event(dev, "HANG");
++#endif
++#if defined(WL_CFG80211)
++		wl_cfg80211_hang(dev, WLAN_REASON_UNSPECIFIED);
++#endif
++	}
++}
++
++
++int dhd_os_send_hang_message(dhd_pub_t *dhdp)
++{
++	int ret = 0;
++	if (dhdp) {
++		if (!dhdp->hang_was_sent) {
++			dhdp->hang_was_sent = 1;
++			dhd_deferred_schedule_work(dhdp->info->dhd_deferred_wq, (void *)dhdp,
++				DHD_WQ_WORK_HANG_MSG, dhd_hang_process, DHD_WORK_PRIORITY_HIGH);
++		}
++	}
++	return ret;
++}
++
++int net_os_send_hang_message(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret = 0;
++
++	if (dhd) {
++		/* Report FW problem when enabled */
++		if (dhd->pub.hang_report) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++			ret = dhd_os_send_hang_message(&dhd->pub);
++#else
++			ret = wl_cfg80211_hang(dev, WLAN_REASON_UNSPECIFIED);
++#endif
++		} else {
++			DHD_ERROR(("%s: FW HANG ignored (for testing purpose) and not sent up\n",
++				__FUNCTION__));
++			/* Enforce bus down to stop any future traffic */
++			dhd->pub.busstate = DHD_BUS_DOWN;
++		}
++	}
++	return ret;
++}
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27) && OEM_ANDROID */
++
++
++int dhd_net_wifi_platform_set_power(struct net_device *dev, bool on, unsigned long delay_msec)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	return wifi_platform_set_power(dhd->adapter, on, delay_msec);
++}
++
++bool dhd_force_country_change(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	if (dhd && dhd->pub.up)
++		return dhd->pub.force_country_change;
++	return FALSE;
++}
++void dhd_get_customized_country_code(struct net_device *dev, char *country_iso_code,
++	wl_country_t *cspec)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++#ifdef CUSTOM_COUNTRY_CODE
++	get_customized_country_code(dhd->adapter, country_iso_code, cspec,
++			dhd->pub.dhd_cflags);
++#else
++	get_customized_country_code(dhd->adapter, country_iso_code, cspec);
++#endif /* CUSTOM_COUNTRY_CODE */
++}
++void dhd_bus_country_set(struct net_device *dev, wl_country_t *cspec, bool notify)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	if (dhd && dhd->pub.up) {
++		memcpy(&dhd->pub.dhd_cspec, cspec, sizeof(wl_country_t));
++#ifdef WL_CFG80211
++		wl_update_wiphybands(NULL, notify);
++#endif
++	}
++}
++
++void dhd_bus_band_set(struct net_device *dev, uint band)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	if (dhd && dhd->pub.up) {
++#ifdef WL_CFG80211
++		wl_update_wiphybands(NULL, true);
++#endif
++	}
++}
++
++int dhd_net_set_fw_path(struct net_device *dev, char *fw)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++
++	if (!fw || fw[0] == '\0')
++		return -EINVAL;
++
++	strncpy(dhd->fw_path, fw, sizeof(dhd->fw_path) - 1);
++	dhd->fw_path[sizeof(dhd->fw_path)-1] = '\0';
++
++#if defined(SOFTAP)
++	if (strstr(fw, "apsta") != NULL) {
++		DHD_INFO(("GOT APSTA FIRMWARE\n"));
++		ap_fw_loaded = TRUE;
++	} else {
++		DHD_INFO(("GOT STA FIRMWARE\n"));
++		ap_fw_loaded = FALSE;
++	}
++#endif 
++	return 0;
++}
++
++void dhd_net_if_lock(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	dhd_net_if_lock_local(dhd);
++}
++
++void dhd_net_if_unlock(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	dhd_net_if_unlock_local(dhd);
++}
++
++static void dhd_net_if_lock_local(dhd_info_t *dhd)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	if (dhd)
++		mutex_lock(&dhd->dhd_net_if_mutex);
++#endif
++}
++
++static void dhd_net_if_unlock_local(dhd_info_t *dhd)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	if (dhd)
++		mutex_unlock(&dhd->dhd_net_if_mutex);
++#endif
++}
++
++static void dhd_suspend_lock(dhd_pub_t *pub)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	if (dhd)
++		mutex_lock(&dhd->dhd_suspend_mutex);
++#endif
++}
++
++static void dhd_suspend_unlock(dhd_pub_t *pub)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	if (dhd)
++		mutex_unlock(&dhd->dhd_suspend_mutex);
++#endif
++}
++
++unsigned long dhd_os_general_spin_lock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags = 0;
++
++	if (dhd)
++		spin_lock_irqsave(&dhd->dhd_lock, flags);
++
++	return flags;
++}
++
++void dhd_os_general_spin_unlock(dhd_pub_t *pub, unsigned long flags)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd)
++		spin_unlock_irqrestore(&dhd->dhd_lock, flags);
++}
++
++/* Linux specific multipurpose spinlock API */
++void *
++dhd_os_spin_lock_init(osl_t *osh)
++{
++	/* Adding 4 bytes since the sizeof(spinlock_t) could be 0 */
++	/* if CONFIG_SMP and CONFIG_DEBUG_SPINLOCK are not defined */
++	/* and this results in kernel asserts in internal builds */
++	spinlock_t * lock = MALLOC(osh, sizeof(spinlock_t) + 4);
++	if (lock)
++		spin_lock_init(lock);
++	return ((void *)lock);
++}
++void
++dhd_os_spin_lock_deinit(osl_t *osh, void *lock)
++{
++	if (lock)
++		MFREE(osh, lock, sizeof(spinlock_t) + 4);
++}
++unsigned long
++dhd_os_spin_lock(void *lock)
++{
++	unsigned long flags = 0;
++
++	if (lock)
++		spin_lock_irqsave((spinlock_t *)lock, flags);
++
++	return flags;
++}
++void
++dhd_os_spin_unlock(void *lock, unsigned long flags)
++{
++	if (lock)
++		spin_unlock_irqrestore((spinlock_t *)lock, flags);
++}
++
++static int
++dhd_get_pend_8021x_cnt(dhd_info_t *dhd)
++{
++	return (atomic_read(&dhd->pend_8021x_cnt));
++}
++
++#define MAX_WAIT_FOR_8021X_TX	100
++
++int
++dhd_wait_pend8021x(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int timeout = msecs_to_jiffies(10);
++	int ntimes = MAX_WAIT_FOR_8021X_TX;
++	int pend = dhd_get_pend_8021x_cnt(dhd);
++
++	while (ntimes && pend) {
++		if (pend) {
++			set_current_state(TASK_INTERRUPTIBLE);
++			DHD_PERIM_UNLOCK(&dhd->pub);
++			schedule_timeout(timeout);
++			DHD_PERIM_LOCK(&dhd->pub);
++			set_current_state(TASK_RUNNING);
++			ntimes--;
++		}
++		pend = dhd_get_pend_8021x_cnt(dhd);
++	}
++	if (ntimes == 0)
++	{
++		atomic_set(&dhd->pend_8021x_cnt, 0);
++		DHD_ERROR(("%s: TIMEOUT\n", __FUNCTION__));
++	}
++	return pend;
++}
++
++#if defined(DHD_DEBUG)
++int
++write_file(char * file_name, uint32 flags, uint8 *buf, int size)
++{
++	int ret = 0;
++	struct file *fp = NULL;
++	mm_segment_t old_fs;
++	loff_t pos = 0;
++	/* change to KERNEL_DS address limit */
++	old_fs = get_fs();
++	set_fs(KERNEL_DS);
++
++	/* open file to write */
++	fp = filp_open(file_name, flags, 0644);
++	if (IS_ERR(fp)) {
++		printf("%s: open file error, err = %ld\n", __FUNCTION__, PTR_ERR(fp));
++		ret = -1;
++		goto exit;
++	}
++
++	/* Write buf to file */
++	fp->f_op->write(fp, buf, size, &pos);
++
++exit:
++	/* close file before return */
++	if (!IS_ERR(fp))
++		filp_close(fp, current->files);
++
++	/* restore previous address limit */
++	set_fs(old_fs);
++
++	/* buf is actually dhd_pub->soc_ram and freed in in dhd_{free,clear} */
++
++	return ret;
++}
++#endif 
++
++#ifdef DHD_DEBUG
++static void
++dhd_convert_memdump_type_to_str(uint32 type, char *buf)
++{
++	char *type_str = NULL;
++
++	switch (type) {
++		case DUMP_TYPE_RESUMED_ON_TIMEOUT:
++			type_str = "resumed_on_timeout";
++			break;
++		case DUMP_TYPE_D3_ACK_TIMEOUT:
++			type_str = "D3_ACK_timeout";
++			break;
++		case DUMP_TYPE_DONGLE_TRAP:
++			type_str = "Dongle_Trap";
++			break;
++		case DUMP_TYPE_MEMORY_CORRUPTION:
++			type_str = "Memory_Corruption";
++			break;
++		case DUMP_TYPE_PKTID_AUDIT_FAILURE:
++			type_str = "PKTID_AUDIT_Fail";
++			break;
++		case DUMP_TYPE_SCAN_TIMEOUT:
++			type_str = "SCAN_timeout";
++			break;
++		default:
++			type_str = "Unknown_type";
++			break;
++	}
++
++	strncpy(buf, type_str, strlen(type_str));
++	buf[strlen(type_str)] = 0;
++}
++
++int
++write_to_file(dhd_pub_t *dhd, uint8 *buf, int size)
++{
++	int ret = 0;
++	char memdump_path[64];
++	char memdump_type[32];
++	struct __kernel_timex curtime;
++	uint32 file_mode;
++
++
++	/* Init file name */
++	memset(memdump_path, 0, sizeof(memdump_path));
++	memset(memdump_type, 0, sizeof(memdump_type));
++        do_adjtimex(&curtime);
++	dhd_convert_memdump_type_to_str(dhd->memdump_type, memdump_type);
++	sprintf(memdump_path, "%s_%s_%ld.%ld", "/installmedia/mem_dump",
++		memdump_type, (unsigned long)curtime.time.tv_sec,
++		(unsigned long)curtime.time.tv_usec);
++	/* Extra flags O_DIRECT and O_SYNC are required for Brix Android, as we are
++	 * calling BUG_ON immediately after collecting the socram dump.
++	 * So the file write operation should directly write the contents into the
++	 * file instead of caching it. O_TRUNC flag ensures that file will be re-written
++	 * instead of appending.
++	 */
++	file_mode = O_CREAT | O_WRONLY | O_DIRECT | O_SYNC | O_TRUNC;
++
++	/* print SOCRAM dump file path */
++	DHD_ERROR(("%s: memdump_path = %s\n", __FUNCTION__, memdump_path));
++
++	/* Write file */
++	ret = write_file(memdump_path, file_mode, buf, size);
++
++	return ret;
++}
++#endif /* DHD_DEBUG */
++
++int dhd_os_wake_lock_timeout(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++	int ret = 0;
++
++	if (dhd) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++		ret = dhd->wakelock_rx_timeout_enable > dhd->wakelock_ctrl_timeout_enable ?
++			dhd->wakelock_rx_timeout_enable : dhd->wakelock_ctrl_timeout_enable;
++#ifdef CONFIG_HAS_WAKELOCK
++		if (dhd->wakelock_rx_timeout_enable)
++			wake_lock_timeout(&dhd->wl_rxwake,
++				msecs_to_jiffies(dhd->wakelock_rx_timeout_enable));
++		if (dhd->wakelock_ctrl_timeout_enable)
++			wake_lock_timeout(&dhd->wl_ctrlwake,
++				msecs_to_jiffies(dhd->wakelock_ctrl_timeout_enable));
++#endif
++		dhd->wakelock_rx_timeout_enable = 0;
++		dhd->wakelock_ctrl_timeout_enable = 0;
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++	return ret;
++}
++
++int net_os_wake_lock_timeout(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret = 0;
++
++	if (dhd)
++		ret = dhd_os_wake_lock_timeout(&dhd->pub);
++	return ret;
++}
++
++int dhd_os_wake_lock_rx_timeout_enable(dhd_pub_t *pub, int val)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++
++	if (dhd) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++		if (val > dhd->wakelock_rx_timeout_enable)
++			dhd->wakelock_rx_timeout_enable = val;
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++	return 0;
++}
++
++int dhd_os_wake_lock_ctrl_timeout_enable(dhd_pub_t *pub, int val)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++
++	if (dhd) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++		if (val > dhd->wakelock_ctrl_timeout_enable)
++			dhd->wakelock_ctrl_timeout_enable = val;
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++	return 0;
++}
++
++int dhd_os_wake_lock_ctrl_timeout_cancel(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++
++	if (dhd) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++		dhd->wakelock_ctrl_timeout_enable = 0;
++#ifdef CONFIG_HAS_WAKELOCK
++		if (wake_lock_active(&dhd->wl_ctrlwake))
++			wake_unlock(&dhd->wl_ctrlwake);
++#endif
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++	return 0;
++}
++
++int net_os_wake_lock_rx_timeout_enable(struct net_device *dev, int val)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret = 0;
++
++	if (dhd)
++		ret = dhd_os_wake_lock_rx_timeout_enable(&dhd->pub, val);
++	return ret;
++}
++
++int net_os_wake_lock_ctrl_timeout_enable(struct net_device *dev, int val)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret = 0;
++
++	if (dhd)
++		ret = dhd_os_wake_lock_ctrl_timeout_enable(&dhd->pub, val);
++	return ret;
++}
++
++int dhd_os_wake_lock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++	int ret = 0;
++
++	if (dhd) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++
++		if (dhd->wakelock_counter == 0 && !dhd->waive_wakelock) {
++#ifdef CONFIG_HAS_WAKELOCK
++			wake_lock(&dhd->wl_wifi);
++#elif defined(BCMSDIO) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++			dhd_bus_dev_pm_stay_awake(pub);
++#endif
++		}
++		dhd->wakelock_counter++;
++		ret = dhd->wakelock_counter;
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++	return ret;
++}
++
++int net_os_wake_lock(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret = 0;
++
++	if (dhd)
++		ret = dhd_os_wake_lock(&dhd->pub);
++	return ret;
++}
++
++int dhd_os_wake_unlock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++	int ret = 0;
++
++	dhd_os_wake_lock_timeout(pub);
++	if (dhd) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++		if (dhd->wakelock_counter > 0) {
++			dhd->wakelock_counter--;
++			if (dhd->wakelock_counter == 0 && !dhd->waive_wakelock) {
++#ifdef CONFIG_HAS_WAKELOCK
++				wake_unlock(&dhd->wl_wifi);
++#elif defined(BCMSDIO) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++				dhd_bus_dev_pm_relax(pub);
++#endif
++			}
++			ret = dhd->wakelock_counter;
++		}
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++	return ret;
++}
++
++int dhd_os_check_wakelock(dhd_pub_t *pub)
++{
++#if defined(CONFIG_HAS_WAKELOCK) || (defined(BCMSDIO) && (LINUX_VERSION_CODE > \
++	KERNEL_VERSION(2, 6, 36)))
++	dhd_info_t *dhd;
++
++	if (!pub)
++		return 0;
++	dhd = (dhd_info_t *)(pub->info);
++#endif /* CONFIG_HAS_WAKELOCK || BCMSDIO */
++
++#ifdef CONFIG_HAS_WAKELOCK
++	/* Indicate to the SD Host to avoid going to suspend if internal locks are up */
++	if (dhd && (wake_lock_active(&dhd->wl_wifi) ||
++		(wake_lock_active(&dhd->wl_wdwake))))
++		return 1;
++#elif defined(BCMSDIO) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++	if (dhd && (dhd->wakelock_counter > 0) && dhd_bus_dev_pm_enabled(pub))
++		return 1;
++#endif
++	return 0;
++}
++
++int
++dhd_os_check_wakelock_all(dhd_pub_t *pub)
++{
++#ifdef CONFIG_HAS_WAKELOCK
++	int l1, l2, l3, l4;
++	int l5 = 0, l6 = 0;
++	int c, lock_active;
++#endif /* CONFIG_HAS_WAKELOCK */
++#if defined(CONFIG_HAS_WAKELOCK) || (defined(BCMSDIO) && (LINUX_VERSION_CODE > \
++	KERNEL_VERSION(2, 6, 36)))
++	dhd_info_t *dhd;
++
++	if (!pub) {
++		return 0;
++	}
++	dhd = (dhd_info_t *)(pub->info);
++	if (!dhd) {
++		return 0;
++	}
++#endif /* CONFIG_HAS_WAKELOCK || BCMSDIO */
++
++#ifdef CONFIG_HAS_WAKELOCK
++	c = dhd->wakelock_counter;
++	l1 = wake_lock_active(&dhd->wl_wifi);
++	l2 = wake_lock_active(&dhd->wl_wdwake);
++	l3 = wake_lock_active(&dhd->wl_rxwake);
++	l4 = wake_lock_active(&dhd->wl_ctrlwake);
++#ifdef BCMPCIE_OOB_HOST_WAKE
++	l5 = wake_lock_active(&dhd->wl_intrwake);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#ifdef DHD_USE_SCAN_WAKELOCK
++	l6 = wake_lock_active(&dhd->wl_scanwake);
++#endif /* DHD_USE_SCAN_WAKELOCK */
++	lock_active = (l1 || l2 || l3 || l4 || l5 || l6);
++
++	/* Indicate to the Host to avoid going to suspend if internal locks are up */
++	if (dhd && lock_active) {
++		DHD_ERROR(("%s wakelock c-%d wl-%d wd-%d rx-%d "
++			"ctl-%d intr-%d scan-%d\n",
++			__FUNCTION__, c, l1, l2, l3, l4, l5, l6));
++		return 1;
++	}
++#elif defined(BCMSDIO) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++	if (dhd && (dhd->wakelock_counter > 0) && dhd_bus_dev_pm_enabled(pub)) {
++		return 1;
++	}
++#endif /* CONFIG_HAS_WAKELOCK */
++	return 0;
++}
++
++int net_os_wake_unlock(struct net_device *dev)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(dev);
++	int ret = 0;
++
++	if (dhd)
++		ret = dhd_os_wake_unlock(&dhd->pub);
++	return ret;
++}
++
++int dhd_os_wd_wake_lock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++	int ret = 0;
++
++	if (dhd) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++#ifdef CONFIG_HAS_WAKELOCK
++		/* if wakelock_wd_counter was never used : lock it at once */
++		if (!dhd->wakelock_wd_counter)
++			wake_lock(&dhd->wl_wdwake);
++#endif
++		dhd->wakelock_wd_counter++;
++		ret = dhd->wakelock_wd_counter;
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++	return ret;
++}
++
++int dhd_os_wd_wake_unlock(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++	int ret = 0;
++
++	if (dhd) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++		if (dhd->wakelock_wd_counter) {
++			dhd->wakelock_wd_counter = 0;
++#ifdef CONFIG_HAS_WAKELOCK
++			wake_unlock(&dhd->wl_wdwake);
++#endif
++		}
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++	return ret;
++}
++
++#ifdef BCMPCIE_OOB_HOST_WAKE
++void
++dhd_os_oob_irq_wake_lock_timeout(dhd_pub_t *pub, int val)
++{
++#ifdef CONFIG_HAS_WAKELOCK
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		wake_lock_timeout(&dhd->wl_intrwake, msecs_to_jiffies(val));
++	}
++#endif /* CONFIG_HAS_WAKELOCK */
++}
++
++void
++dhd_os_oob_irq_wake_unlock(dhd_pub_t *pub)
++{
++#ifdef CONFIG_HAS_WAKELOCK
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		/* if wl_intrwake is active, unlock it */
++		if (wake_lock_active(&dhd->wl_intrwake)) {
++			wake_unlock(&dhd->wl_intrwake);
++		}
++	}
++#endif /* CONFIG_HAS_WAKELOCK */
++}
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++
++#ifdef DHD_USE_SCAN_WAKELOCK
++void
++dhd_os_scan_wake_lock_timeout(dhd_pub_t *pub, int val)
++{
++#ifdef CONFIG_HAS_WAKELOCK
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		wake_lock_timeout(&dhd->wl_scanwake, msecs_to_jiffies(val));
++	}
++#endif /* CONFIG_HAS_WAKELOCK */
++}
++
++void
++dhd_os_scan_wake_unlock(dhd_pub_t *pub)
++{
++#ifdef CONFIG_HAS_WAKELOCK
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++
++	if (dhd) {
++		/* if wl_scanwake is active, unlock it */
++		if (wake_lock_active(&dhd->wl_scanwake)) {
++			wake_unlock(&dhd->wl_scanwake);
++		}
++	}
++#endif /* CONFIG_HAS_WAKELOCK */
++}
++#endif /* DHD_USE_SCAN_WAKELOCK */
++
++/* waive wakelocks for operations such as IOVARs in suspend function, must be closed
++ * by a paired function call to dhd_wakelock_restore. returns current wakelock counter
++ */
++int dhd_os_wake_lock_waive(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++	int ret = 0;
++
++	if (dhd) {
++		spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++		/* dhd_wakelock_waive/dhd_wakelock_restore must be paired */
++		if (dhd->waive_wakelock == FALSE) {
++			/* record current lock status */
++			dhd->wakelock_before_waive = dhd->wakelock_counter;
++			dhd->waive_wakelock = TRUE;
++		}
++		ret = dhd->wakelock_wd_counter;
++		spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	}
++	return ret;
++}
++
++int dhd_os_wake_lock_restore(dhd_pub_t *pub)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(pub->info);
++	unsigned long flags;
++	int ret = 0;
++
++	if (!dhd)
++		return 0;
++
++	spin_lock_irqsave(&dhd->wakelock_spinlock, flags);
++	/* dhd_wakelock_waive/dhd_wakelock_restore must be paired */
++	if (!dhd->waive_wakelock)
++		goto exit;
++
++	dhd->waive_wakelock = FALSE;
++	/* if somebody else acquires wakelock between dhd_wakelock_waive/dhd_wakelock_restore,
++	 * we need to make it up by calling wake_lock or pm_stay_awake. or if somebody releases
++	 * the lock in between, do the same by calling wake_unlock or pm_relax
++	 */
++	if (dhd->wakelock_before_waive == 0 && dhd->wakelock_counter > 0) {
++#ifdef CONFIG_HAS_WAKELOCK
++		wake_lock(&dhd->wl_wifi);
++#elif defined(BCMSDIO) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++		dhd_bus_dev_pm_stay_awake(&dhd->pub);
++#endif
++	} else if (dhd->wakelock_before_waive > 0 && dhd->wakelock_counter == 0) {
++#ifdef CONFIG_HAS_WAKELOCK
++		wake_unlock(&dhd->wl_wifi);
++#elif defined(BCMSDIO) && (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 36))
++		dhd_bus_dev_pm_relax(&dhd->pub);
++#endif
++	}
++	dhd->wakelock_before_waive = 0;
++exit:
++	ret = dhd->wakelock_wd_counter;
++	spin_unlock_irqrestore(&dhd->wakelock_spinlock, flags);
++	return ret;
++}
++
++bool dhd_os_check_if_up(dhd_pub_t *pub)
++{
++	if (!pub)
++		return FALSE;
++	return pub->up;
++}
++
++#if defined(BCMSDIO) || defined(BCMPCIE)
++/* function to collect firmware, chip id and chip version info */
++void dhd_set_version_info(dhd_pub_t *dhdp, char *fw)
++{
++	int i;
++
++	i = snprintf(info_string, sizeof(info_string),
++		"  Driver: %s\n  Firmware: %s ", EPI_VERSION_STR, fw);
++
++	if (!dhdp)
++		return;
++
++	i = snprintf(&info_string[i], sizeof(info_string) - i,
++		"\n  Chip: %x Rev %x Pkg %x", dhd_bus_chip_id(dhdp),
++		dhd_bus_chiprev_id(dhdp), dhd_bus_chippkg_id(dhdp));
++}
++#endif /* BCMSDIO || BCMPCIE */
++
++int dhd_ioctl_entry_local(struct net_device *net, wl_ioctl_t *ioc, int cmd)
++{
++	int ifidx;
++	int ret = 0;
++	dhd_info_t *dhd = NULL;
++
++	if (!net || !DEV_PRIV(net)) {
++		DHD_ERROR(("%s invalid parameter\n", __FUNCTION__));
++		return -EINVAL;
++	}
++
++	dhd = DHD_DEV_INFO(net);
++	if (!dhd)
++		return -EINVAL;
++
++	ifidx = dhd_net2idx(dhd, net);
++	if (ifidx == DHD_BAD_IF) {
++		DHD_ERROR(("%s bad ifidx\n", __FUNCTION__));
++		return -ENODEV;
++	}
++
++	DHD_OS_WAKE_LOCK(&dhd->pub);
++	DHD_PERIM_LOCK(&dhd->pub);
++
++	ret = dhd_wl_ioctl(&dhd->pub, ifidx, ioc, ioc->buf, ioc->len);
++	dhd_check_hang(net, &dhd->pub, ret);
++
++	DHD_PERIM_UNLOCK(&dhd->pub);
++	DHD_OS_WAKE_UNLOCK(&dhd->pub);
++
++	return ret;
++}
++
++bool dhd_os_check_hang(dhd_pub_t *dhdp, int ifidx, int ret)
++{
++	struct net_device *net;
++
++	net = dhd_idx2net(dhdp, ifidx);
++	if (!net) {
++		DHD_ERROR(("%s : Invalid index : %d\n", __FUNCTION__, ifidx));
++		return -EINVAL;
++	}
++
++	return dhd_check_hang(net, dhdp, ret);
++}
++
++/* Return instance */
++int dhd_get_instance(dhd_pub_t *dhdp)
++{
++	return dhdp->info->unit;
++}
++
++
++#ifdef PROP_TXSTATUS
++
++void dhd_wlfc_plat_init(void *dhd)
++{
++	return;
++}
++
++void dhd_wlfc_plat_deinit(void *dhd)
++{
++	return;
++}
++
++bool dhd_wlfc_skip_fc(void)
++{
++	return FALSE;
++}
++#endif /* PROP_TXSTATUS */
++
++#ifdef BCMDBGFS
++#include <linux/debugfs.h>
++
++typedef struct dhd_dbgfs {
++	struct dentry	*debugfs_dir;
++	struct dentry	*debugfs_mem;
++	dhd_pub_t	*dhdp;
++	uint32		size;
++} dhd_dbgfs_t;
++
++dhd_dbgfs_t g_dbgfs;
++
++extern uint32 dhd_readregl(void *bp, uint32 addr);
++extern uint32 dhd_writeregl(void *bp, uint32 addr, uint32 data);
++
++static int
++dhd_dbg_state_open(struct inode *inode, struct file *file)
++{
++	file->private_data = inode->i_private;
++	return 0;
++}
++
++static ssize_t
++dhd_dbg_state_read(struct file *file, char __user *ubuf,
++                       size_t count, loff_t *ppos)
++{
++	ssize_t rval;
++	uint32 tmp;
++	loff_t pos = *ppos;
++	size_t ret;
++
++	if (pos < 0)
++		return -EINVAL;
++	if (pos >= g_dbgfs.size || !count)
++		return 0;
++	if (count > g_dbgfs.size - pos)
++		count = g_dbgfs.size - pos;
++
++	/* Basically enforce aligned 4 byte reads. It's up to the user to work out the details */
++	tmp = dhd_readregl(g_dbgfs.dhdp->bus, file->f_pos & (~3));
++
++	ret = copy_to_user(ubuf, &tmp, 4);
++	if (ret == count)
++		return -EFAULT;
++
++	count -= ret;
++	*ppos = pos + count;
++	rval = count;
++
++	return rval;
++}
++
++
++static ssize_t
++dhd_debugfs_write(struct file *file, const char __user *ubuf, size_t count, loff_t *ppos)
++{
++	loff_t pos = *ppos;
++	size_t ret;
++	uint32 buf;
++
++	if (pos < 0)
++		return -EINVAL;
++	if (pos >= g_dbgfs.size || !count)
++		return 0;
++	if (count > g_dbgfs.size - pos)
++		count = g_dbgfs.size - pos;
++
++	ret = copy_from_user(&buf, ubuf, sizeof(uint32));
++	if (ret == count)
++		return -EFAULT;
++
++	/* Basically enforce aligned 4 byte writes. It's up to the user to work out the details */
++	dhd_writeregl(g_dbgfs.dhdp->bus, file->f_pos & (~3), buf);
++
++	return count;
++}
++
++
++loff_t
++dhd_debugfs_lseek(struct file *file, loff_t off, int whence)
++{
++	loff_t pos = -1;
++
++	switch (whence) {
++		case 0:
++			pos = off;
++			break;
++		case 1:
++			pos = file->f_pos + off;
++			break;
++		case 2:
++			pos = g_dbgfs.size - off;
++	}
++	return (pos < 0 || pos > g_dbgfs.size) ? -EINVAL : (file->f_pos = pos);
++}
++
++static const struct file_operations dhd_dbg_state_ops = {
++	.read   = dhd_dbg_state_read,
++	.write	= dhd_debugfs_write,
++	.open   = dhd_dbg_state_open,
++	.llseek	= dhd_debugfs_lseek
++};
++
++static void dhd_dbg_create(void)
++{
++	if (g_dbgfs.debugfs_dir) {
++		g_dbgfs.debugfs_mem = debugfs_create_file("mem", 0644, g_dbgfs.debugfs_dir,
++			NULL, &dhd_dbg_state_ops);
++	}
++}
++
++void dhd_dbg_init(dhd_pub_t *dhdp)
++{
++	g_dbgfs.dhdp = dhdp;
++	g_dbgfs.size = 0x20000000; /* Allow access to various cores regs */
++
++	g_dbgfs.debugfs_dir = debugfs_create_dir("dhd", 0);
++	if (IS_ERR(g_dbgfs.debugfs_dir)) {
++		g_dbgfs.debugfs_dir = NULL;
++		return;
++	}
++
++	dhd_dbg_create();
++
++	return;
++}
++
++void dhd_dbg_remove(void)
++{
++	debugfs_remove(g_dbgfs.debugfs_mem);
++	debugfs_remove(g_dbgfs.debugfs_dir);
++
++	bzero((unsigned char *) &g_dbgfs, sizeof(g_dbgfs));
++}
++#endif /* BCMDBGFS */
++
++#ifdef WLMEDIA_HTSF
++
++static
++void dhd_htsf_addtxts(dhd_pub_t *dhdp, void *pktbuf)
++{
++	dhd_info_t *dhd = (dhd_info_t *)(dhdp->info);
++	struct sk_buff *skb;
++	uint32 htsf = 0;
++	uint16 dport = 0, oldmagic = 0xACAC;
++	char *p1;
++	htsfts_t ts;
++
++	/*  timestamp packet  */
++
++	p1 = (char*) PKTDATA(dhdp->osh, pktbuf);
++
++	if (PKTLEN(dhdp->osh, pktbuf) > HTSF_MINLEN) {
++/*		memcpy(&proto, p1+26, 4);  	*/
++		memcpy(&dport, p1+40, 2);
++/* 	proto = ((ntoh32(proto))>> 16) & 0xFF;  */
++		dport = ntoh16(dport);
++	}
++
++	/* timestamp only if  icmp or udb iperf with port 5555 */
++/*	if (proto == 17 && dport == tsport) { */
++	if (dport >= tsport && dport <= tsport + 20) {
++
++		skb = (struct sk_buff *) pktbuf;
++
++		htsf = dhd_get_htsf(dhd, 0);
++		memset(skb->data + 44, 0, 2); /* clear checksum */
++		memcpy(skb->data+82, &oldmagic, 2);
++		memcpy(skb->data+84, &htsf, 4);
++
++		memset(&ts, 0, sizeof(htsfts_t));
++		ts.magic  = HTSFMAGIC;
++		ts.prio   = PKTPRIO(pktbuf);
++		ts.seqnum = htsf_seqnum++;
++		ts.c10    = get_cycles();
++		ts.t10    = htsf;
++		ts.endmagic = HTSFENDMAGIC;
++
++		memcpy(skb->data + HTSF_HOSTOFFSET, &ts, sizeof(ts));
++	}
++}
++
++static void dhd_dump_htsfhisto(histo_t *his, char *s)
++{
++	int pktcnt = 0, curval = 0, i;
++	for (i = 0; i < (NUMBIN-2); i++) {
++		curval += 500;
++		printf("%d ",  his->bin[i]);
++		pktcnt += his->bin[i];
++	}
++	printf(" max: %d TotPkt: %d neg: %d [%s]\n", his->bin[NUMBIN-2], pktcnt,
++		his->bin[NUMBIN-1], s);
++}
++
++static
++void sorttobin(int value, histo_t *histo)
++{
++	int i, binval = 0;
++
++	if (value < 0) {
++		histo->bin[NUMBIN-1]++;
++		return;
++	}
++	if (value > histo->bin[NUMBIN-2])  /* store the max value  */
++		histo->bin[NUMBIN-2] = value;
++
++	for (i = 0; i < (NUMBIN-2); i++) {
++		binval += 500; /* 500m s bins */
++		if (value <= binval) {
++			histo->bin[i]++;
++			return;
++		}
++	}
++	histo->bin[NUMBIN-3]++;
++}
++
++static
++void dhd_htsf_addrxts(dhd_pub_t *dhdp, void *pktbuf)
++{
++	dhd_info_t *dhd = (dhd_info_t *)dhdp->info;
++	struct sk_buff *skb;
++	char *p1;
++	uint16 old_magic;
++	int d1, d2, d3, end2end;
++	htsfts_t *htsf_ts;
++	uint32 htsf;
++
++	skb = PKTTONATIVE(dhdp->osh, pktbuf);
++	p1 = (char*)PKTDATA(dhdp->osh, pktbuf);
++
++	if (PKTLEN(osh, pktbuf) > HTSF_MINLEN) {
++		memcpy(&old_magic, p1+78, 2);
++		htsf_ts = (htsfts_t*) (p1 + HTSF_HOSTOFFSET - 4);
++	} else {
++		return;
++	}
++	if (htsf_ts->magic == HTSFMAGIC) {
++		htsf_ts->tE0 = dhd_get_htsf(dhd, 0);
++		htsf_ts->cE0 = get_cycles();
++	}
++
++	if (old_magic == 0xACAC) {
++
++		tspktcnt++;
++		htsf = dhd_get_htsf(dhd, 0);
++		memcpy(skb->data+92, &htsf, sizeof(uint32));
++
++		memcpy(&ts[tsidx].t1, skb->data+80, 16);
++
++		d1 = ts[tsidx].t2 - ts[tsidx].t1;
++		d2 = ts[tsidx].t3 - ts[tsidx].t2;
++		d3 = ts[tsidx].t4 - ts[tsidx].t3;
++		end2end = ts[tsidx].t4 - ts[tsidx].t1;
++
++		sorttobin(d1, &vi_d1);
++		sorttobin(d2, &vi_d2);
++		sorttobin(d3, &vi_d3);
++		sorttobin(end2end, &vi_d4);
++
++		if (end2end > 0 && end2end >  maxdelay) {
++			maxdelay = end2end;
++			maxdelaypktno = tspktcnt;
++			memcpy(&maxdelayts, &ts[tsidx], 16);
++		}
++		if (++tsidx >= TSMAX)
++			tsidx = 0;
++	}
++}
++
++uint32 dhd_get_htsf(dhd_info_t *dhd, int ifidx)
++{
++	uint32 htsf = 0, cur_cycle, delta, delta_us;
++	uint32    factor, baseval, baseval2;
++	cycles_t t;
++
++	t = get_cycles();
++	cur_cycle = t;
++
++	if (cur_cycle >  dhd->htsf.last_cycle) {
++		delta = cur_cycle -  dhd->htsf.last_cycle;
++	} else {
++		delta = cur_cycle + (0xFFFFFFFF -  dhd->htsf.last_cycle);
++	}
++
++	delta = delta >> 4;
++
++	if (dhd->htsf.coef) {
++		/* times ten to get the first digit */
++	        factor = (dhd->htsf.coef*10 + dhd->htsf.coefdec1);
++		baseval  = (delta*10)/factor;
++		baseval2 = (delta*10)/(factor+1);
++		delta_us  = (baseval -  (((baseval - baseval2) * dhd->htsf.coefdec2)) / 10);
++		htsf = (delta_us << 4) +  dhd->htsf.last_tsf + HTSF_BUS_DELAY;
++	} else {
++		DHD_ERROR(("-------dhd->htsf.coef = 0 -------\n"));
++	}
++
++	return htsf;
++}
++
++static void dhd_dump_latency(void)
++{
++	int i, max = 0;
++	int d1, d2, d3, d4, d5;
++
++	printf("T1       T2       T3       T4           d1  d2   t4-t1     i    \n");
++	for (i = 0; i < TSMAX; i++) {
++		d1 = ts[i].t2 - ts[i].t1;
++		d2 = ts[i].t3 - ts[i].t2;
++		d3 = ts[i].t4 - ts[i].t3;
++		d4 = ts[i].t4 - ts[i].t1;
++		d5 = ts[max].t4-ts[max].t1;
++		if (d4 > d5 && d4 > 0)  {
++			max = i;
++		}
++		printf("%08X %08X %08X %08X \t%d %d %d   %d i=%d\n",
++			ts[i].t1, ts[i].t2, ts[i].t3, ts[i].t4,
++			d1, d2, d3, d4, i);
++	}
++
++	printf("current idx = %d \n", tsidx);
++
++	printf("Highest latency %d pkt no.%d total=%d\n", maxdelay, maxdelaypktno, tspktcnt);
++	printf("%08X %08X %08X %08X \t%d %d %d   %d\n",
++	maxdelayts.t1, maxdelayts.t2, maxdelayts.t3, maxdelayts.t4,
++	maxdelayts.t2 - maxdelayts.t1,
++	maxdelayts.t3 - maxdelayts.t2,
++	maxdelayts.t4 - maxdelayts.t3,
++	maxdelayts.t4 - maxdelayts.t1);
++}
++
++
++static int
++dhd_ioctl_htsf_get(dhd_info_t *dhd, int ifidx)
++{
++	char buf[32];
++	int ret;
++	uint32 s1, s2;
++
++	struct tsf {
++		uint32 low;
++		uint32 high;
++	} tsf_buf;
++
++	memset(&tsf_buf, 0, sizeof(tsf_buf));
++
++	s1 = dhd_get_htsf(dhd, 0);
++	ret = dhd_iovar(&dhd->pub, ifidx, "tsf", NULL, 0, buf, sizeof(buf), FALSE);
++	if (ret < 0) {
++		if (ret == -EIO) {
++			DHD_ERROR(("%s: tsf is not supported by device\n",
++				dhd_ifname(&dhd->pub, ifidx)));
++			return -EOPNOTSUPP;
++		}
++		return ret;
++	}
++	s2 = dhd_get_htsf(dhd, 0);
++
++	memcpy(&tsf_buf, buf, sizeof(tsf_buf));
++	printf(" TSF_h=%04X lo=%08X Calc:htsf=%08X, coef=%d.%d%d delta=%d ",
++		tsf_buf.high, tsf_buf.low, s2, dhd->htsf.coef, dhd->htsf.coefdec1,
++		dhd->htsf.coefdec2, s2-tsf_buf.low);
++	printf("lasttsf=%08X lastcycle=%08X\n", dhd->htsf.last_tsf, dhd->htsf.last_cycle);
++	return 0;
++}
++
++void htsf_update(dhd_info_t *dhd, void *data)
++{
++	static ulong  cur_cycle = 0, prev_cycle = 0;
++	uint32 htsf, tsf_delta = 0;
++	uint32 hfactor = 0, cyc_delta, dec1 = 0, dec2, dec3, tmp;
++	ulong b, a;
++	cycles_t t;
++
++	/* cycles_t in inlcude/mips/timex.h */
++
++	t = get_cycles();
++
++	prev_cycle = cur_cycle;
++	cur_cycle = t;
++
++	if (cur_cycle > prev_cycle)
++		cyc_delta = cur_cycle - prev_cycle;
++	else {
++		b = cur_cycle;
++		a = prev_cycle;
++		cyc_delta = cur_cycle + (0xFFFFFFFF - prev_cycle);
++	}
++
++	if (data == NULL)
++		printf(" tsf update ata point er is null \n");
++
++	memcpy(&prev_tsf, &cur_tsf, sizeof(tsf_t));
++	memcpy(&cur_tsf, data, sizeof(tsf_t));
++
++	if (cur_tsf.low == 0) {
++		DHD_INFO((" ---- 0 TSF, do not update, return\n"));
++		return;
++	}
++
++	if (cur_tsf.low > prev_tsf.low)
++		tsf_delta = (cur_tsf.low - prev_tsf.low);
++	else {
++		DHD_INFO((" ---- tsf low is smaller cur_tsf= %08X, prev_tsf=%08X, \n",
++		 cur_tsf.low, prev_tsf.low));
++		if (cur_tsf.high > prev_tsf.high) {
++			tsf_delta = cur_tsf.low + (0xFFFFFFFF - prev_tsf.low);
++			DHD_INFO((" ---- Wrap around tsf coutner  adjusted TSF=%08X\n", tsf_delta));
++		} else {
++			return; /* do not update */
++		}
++	}
++
++	if (tsf_delta)  {
++		hfactor = cyc_delta / tsf_delta;
++		tmp  = 	(cyc_delta - (hfactor * tsf_delta))*10;
++		dec1 =  tmp/tsf_delta;
++		dec2 =  ((tmp - dec1*tsf_delta)*10) / tsf_delta;
++		tmp  = 	(tmp   - (dec1*tsf_delta))*10;
++		dec3 =  ((tmp - dec2*tsf_delta)*10) / tsf_delta;
++
++		if (dec3 > 4) {
++			if (dec2 == 9) {
++				dec2 = 0;
++				if (dec1 == 9) {
++					dec1 = 0;
++					hfactor++;
++				} else {
++					dec1++;
++				}
++			} else {
++				dec2++;
++			}
++		}
++	}
++
++	if (hfactor) {
++		htsf = ((cyc_delta * 10)  / (hfactor*10+dec1)) + prev_tsf.low;
++		dhd->htsf.coef = hfactor;
++		dhd->htsf.last_cycle = cur_cycle;
++		dhd->htsf.last_tsf = cur_tsf.low;
++		dhd->htsf.coefdec1 = dec1;
++		dhd->htsf.coefdec2 = dec2;
++	} else {
++		htsf = prev_tsf.low;
++	}
++}
++
++#endif /* WLMEDIA_HTSF */
++
++#ifdef CUSTOM_SET_CPUCORE
++void dhd_set_cpucore(dhd_pub_t *dhd, int set)
++{
++	int e_dpc = 0, e_rxf = 0, retry_set = 0;
++
++	if (!(dhd->chan_isvht80)) {
++		DHD_ERROR(("%s: chan_status(%d) cpucore!!!\n", __FUNCTION__, dhd->chan_isvht80));
++		return;
++	}
++
++	if (DPC_CPUCORE) {
++		do {
++			if (set == TRUE) {
++				e_dpc = set_cpus_allowed_ptr(dhd->current_dpc,
++					cpumask_of(DPC_CPUCORE));
++			} else {
++				e_dpc = set_cpus_allowed_ptr(dhd->current_dpc,
++					cpumask_of(PRIMARY_CPUCORE));
++			}
++			if (retry_set++ > MAX_RETRY_SET_CPUCORE) {
++				DHD_ERROR(("%s: dpc(%d) invalid cpu!\n", __FUNCTION__, e_dpc));
++				return;
++			}
++			if (e_dpc < 0)
++				OSL_SLEEP(1);
++		} while (e_dpc < 0);
++	}
++	if (RXF_CPUCORE) {
++		do {
++			if (set == TRUE) {
++				e_rxf = set_cpus_allowed_ptr(dhd->current_rxf,
++					cpumask_of(RXF_CPUCORE));
++			} else {
++				e_rxf = set_cpus_allowed_ptr(dhd->current_rxf,
++					cpumask_of(PRIMARY_CPUCORE));
++			}
++			if (retry_set++ > MAX_RETRY_SET_CPUCORE) {
++				DHD_ERROR(("%s: rxf(%d) invalid cpu!\n", __FUNCTION__, e_rxf));
++				return;
++			}
++			if (e_rxf < 0)
++				OSL_SLEEP(1);
++		} while (e_rxf < 0);
++	}
++#ifdef DHD_OF_SUPPORT
++	interrupt_set_cpucore(set);
++#endif /* DHD_OF_SUPPORT */
++	DHD_TRACE(("%s: set(%d) cpucore success!\n", __FUNCTION__, set));
++
++	return;
++}
++#endif /* CUSTOM_SET_CPUCORE */
++
++#ifdef DHD_MCAST_REGEN
++/* Get interface specific ap_isolate configuration */
++int dhd_get_mcast_regen_bss_enable(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	return ifp->mcast_regen_bss_enable;
++}
++
++/* Set interface specific mcast_regen configuration */
++int dhd_set_mcast_regen_bss_enable(dhd_pub_t *dhdp, uint32 idx, int val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	ifp->mcast_regen_bss_enable = val;
++
++	/* Disable rx_pkt_chain feature for interface, if mcast_regen feature
++	 * is enabled
++	 */
++	dhd_update_rx_pkt_chainable_state(dhdp, idx);
++	return BCME_OK;
++}
++#endif	/* DHD_MCAST_REGEN */
++
++/* Get interface specific ap_isolate configuration */
++int dhd_get_ap_isolate(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	return ifp->ap_isolate;
++}
++
++/* Set interface specific ap_isolate configuration */
++int dhd_set_ap_isolate(dhd_pub_t *dhdp, uint32 idx, int val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	if (ifp)
++		ifp->ap_isolate = val;
++
++	return 0;
++}
++
++#ifdef DHD_FW_COREDUMP
++
++
++/*
++ * dhd_get_memdump_info is defined only for Android builds.
++ * The filename to store memdump is defined for CUSTOMER_HW4,
++ * for other platforms it will take default path "/installmedia/.memdump.info"
++ * New platforms can add their ifdefs accordingly below.
++ */
++#define MEMDUMPINFO "/installmedia/.memdump.info"
++
++void dhd_get_memdump_info(dhd_pub_t *dhd)
++{
++	struct file *fp = NULL;
++	uint32 mem_val = DUMP_MEMFILE_MAX;
++	int ret = 0;
++	char *filepath = MEMDUMPINFO;
++
++	/* Read memdump info from the file */
++	fp = filp_open(filepath, O_RDONLY, 0);
++	if (IS_ERR(fp)) {
++		DHD_ERROR(("[WIFI_SEC] %s: File [%s] doesn't exist\n", __FUNCTION__, filepath));
++		goto done;
++	} else {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
++		loff_t zero = 0;
++		ret = kernel_read(fp, (void *) &mem_val, (size_t) 4, (loff_t *) &zero);
++#else
++		ret = kernel_read(fp, 0, (char *)&mem_val, 4);
++#endif
++		if (ret < 0) {
++			DHD_ERROR(("[WIFI_SEC] %s: File read error, ret=%d\n", __FUNCTION__, ret));
++			filp_close(fp, NULL);
++			goto done;
++		}
++
++		mem_val = bcm_atoi((char *)&mem_val);
++
++		DHD_ERROR(("[WIFI_SEC]%s: MEMDUMP ENABLED = %d\n", __FUNCTION__, mem_val));
++		filp_close(fp, NULL);
++	}
++
++done:
++	/*
++	 * The default behavior for Customer_hw4 is to disable the memdump
++	 * But for Brix Android, default behavior is to collect memdump and crash the host.
++	 * Other platforms can change the behavior accordingly by adding appropriate ifdefs
++	 */
++	dhd->memdump_enabled = (mem_val < DUMP_MEMFILE_MAX) ? mem_val : DUMP_MEMFILE_BUGON;
++}
++
++void dhd_schedule_memdump(dhd_pub_t *dhdp, uint8 *buf, uint32 size)
++{
++	dhd_dump_t *dump = NULL;
++	dump = (dhd_dump_t *)MALLOC(dhdp->osh, sizeof(dhd_dump_t));
++	if (dump == NULL) {
++		DHD_ERROR(("%s: dhd dump memory allocation failed\n", __FUNCTION__));
++		return;
++	}
++	dump->buf = buf;
++	dump->bufsize = size;
++
++#if defined(CONFIG_ARM64)
++	DHD_ERROR(("%s: buf(va)=%llx, buf(pa)=%llx, bufsize=%d\n", __FUNCTION__,
++		(uint64)buf, (uint64)__virt_to_phys((ulong)buf), size));
++#elif defined(__ARM_ARCH_7A__)
++	DHD_ERROR(("%s: buf(va)=%x, buf(pa)=%x, bufsize=%d\n", __FUNCTION__,
++		(uint32)buf, (uint32)__virt_to_phys((ulong)buf), size));
++#endif /* __ARM_ARCH_7A__ */
++	if (dhdp->memdump_enabled == DUMP_MEMONLY) {
++		BUG_ON(1);
++	}
++
++	dhd_deferred_schedule_work(dhdp->info->dhd_deferred_wq, (void *)dump,
++		DHD_WQ_WORK_SOC_RAM_DUMP, dhd_mem_dump, DHD_WORK_PRIORITY_HIGH);
++}
++
++int dhd_os_socram_dump(struct net_device *dev, uint32 *dump_size)
++{
++	int ret = BCME_OK;
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	dhd_pub_t *dhdp = &dhd->pub;
++	ret = dhd_common_socram_dump(dhdp);
++	if (ret == BCME_OK) {
++		*dump_size = dhdp->soc_ram_length;
++	}
++	return ret;
++}
++
++int dhd_os_get_socram_dump(struct net_device *dev, char **buf, uint32 *size)
++{
++	int ret = BCME_OK;
++	int orig_len = 0;
++	dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(dev);
++	dhd_pub_t *dhdp = &dhd->pub;
++	if (buf == NULL)
++		return BCME_ERROR;
++	orig_len = *size;
++	if (dhdp->soc_ram) {
++		if (orig_len >= dhdp->soc_ram_length) {
++			memcpy(*buf, dhdp->soc_ram, dhdp->soc_ram_length);
++			/* reset the storage of dump */
++			memset(dhdp->soc_ram, 0, dhdp->soc_ram_length);
++			*size = dhdp->soc_ram_length;
++			dhdp->soc_ram_length = 0;
++		} else {
++			ret = BCME_BUFTOOSHORT;
++			DHD_ERROR(("The length of the buffer is too short"
++				" to save the memory dump with %d\n", dhdp->soc_ram_length));
++		}
++	} else {
++		DHD_ERROR(("socram_dump is not ready to get\n"));
++		ret = BCME_NOTREADY;
++	}
++	return ret;
++}
++
++int dhd_os_get_version(struct net_device *dev, bool dhd_ver, char **buf, uint32 size)
++{
++	int ret = BCME_OK;
++	memset(*buf, 0, size);
++	if (dhd_ver) {
++		strncpy(*buf, dhd_version, size - 1);
++	} else {
++		strncpy(*buf, strstr(info_string, "Firmware: "), size - 1);
++	}
++	return ret;
++}
++
++static void
++dhd_mem_dump(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++	dhd_dump_t *dump = event_info;
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (!dump) {
++		DHD_ERROR(("%s: dump is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (write_to_file(&dhd->pub, dump->buf, dump->bufsize)) {
++		DHD_ERROR(("%s: writing SoC_RAM dump to the file failed\n", __FUNCTION__));
++	}
++
++	if (dhd->pub.memdump_enabled == DUMP_MEMFILE_BUGON) {
++		BUG_ON(1);
++	}
++	MFREE(dhd->pub.osh, dump, sizeof(dhd_dump_t));
++}
++#endif /* DHD_FW_COREDUMP */
++
++
++#ifdef DHD_WMF
++/* Returns interface specific WMF configuration */
++dhd_wmf_t* dhd_wmf_conf(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++	return &ifp->wmf;
++}
++#endif /* DHD_WMF */
++
++#if defined(TRAFFIC_MGMT_DWM)
++void traffic_mgmt_pkt_set_prio(dhd_pub_t *dhdp, void * pktbuf)
++{
++	struct ether_header *eh;
++	struct ethervlan_header *evh;
++	uint8 *pktdata, *ip_body;
++	uint8  dwm_filter;
++	uint8 tos_tc = 0;
++	uint8 dscp   = 0;
++	pktdata = (uint8 *)PKTDATA(dhdp->osh, pktbuf);
++	eh = (struct ether_header *) pktdata;
++	ip_body = NULL;
++
++	if (dhdp->dhd_tm_dwm_tbl.dhd_dwm_enabled) {
++		if (eh->ether_type == hton16(ETHER_TYPE_8021Q)) {
++			evh = (struct ethervlan_header *)eh;
++			if ((evh->ether_type == hton16(ETHER_TYPE_IP)) ||
++				(evh->ether_type == hton16(ETHER_TYPE_IPV6))) {
++				ip_body = pktdata + sizeof(struct ethervlan_header);
++			}
++		} else if ((eh->ether_type == hton16(ETHER_TYPE_IP)) ||
++			(eh->ether_type == hton16(ETHER_TYPE_IPV6))) {
++			ip_body = pktdata + sizeof(struct ether_header);
++		}
++		if (ip_body) {
++			tos_tc = IP_TOS46(ip_body);
++			dscp = tos_tc >> IPV4_TOS_DSCP_SHIFT;
++		}
++
++		if (dscp < DHD_DWM_TBL_SIZE) {
++			dwm_filter = dhdp->dhd_tm_dwm_tbl.dhd_dwm_tbl[dscp];
++			if (DHD_TRF_MGMT_DWM_IS_FILTER_SET(dwm_filter)) {
++				PKTSETPRIO(pktbuf, DHD_TRF_MGMT_DWM_PRIO(dwm_filter));
++			}
++		}
++	}
++}
++#endif 
++
++#if defined(DHD_L2_FILTER)
++bool dhd_sta_associated(dhd_pub_t *dhdp, uint32 bssidx, uint8 *mac)
++{
++	return dhd_find_sta(dhdp, bssidx, mac) ? TRUE : FALSE;
++}
++#endif 
++
++#ifdef DHD_L2_FILTER
++arp_table_t*
++dhd_get_ifp_arp_table_handle(dhd_pub_t *dhdp, uint32 bssidx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(bssidx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[bssidx];
++	return ifp->phnd_arp_table;
++}
++
++int dhd_get_parp_status(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	if (ifp)
++		return ifp->parp_enable;
++	else
++		return FALSE;
++}
++
++/* Set interface specific proxy arp configuration */
++int dhd_set_parp_status(dhd_pub_t *dhdp, uint32 idx, int val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++	ASSERT(idx < DHD_MAX_IFS);
++	ifp = dhd->iflist[idx];
++
++	if (!ifp)
++	    return BCME_ERROR;
++
++	/* At present all 3 variables are being
++	 * handled at once
++	 */
++	ifp->parp_enable = val;
++	ifp->parp_discard = val;
++	ifp->parp_allnode = val;
++
++	/* Flush ARP entries when disabled */
++	if (val == FALSE) {
++		bcm_l2_filter_arp_table_update(dhdp->osh, ifp->phnd_arp_table, TRUE, NULL,
++			FALSE, dhdp->tickcnt);
++	}
++	return BCME_OK;
++}
++
++bool dhd_parp_discard_is_enabled(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	ASSERT(ifp);
++	return ifp->parp_discard;
++}
++
++bool
++dhd_parp_allnode_is_enabled(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	ASSERT(ifp);
++
++	return ifp->parp_allnode;
++}
++
++int dhd_get_dhcp_unicast_status(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	ASSERT(ifp);
++
++	return ifp->dhcp_unicast;
++}
++
++int dhd_set_dhcp_unicast_status(dhd_pub_t *dhdp, uint32 idx, int val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++	ASSERT(idx < DHD_MAX_IFS);
++	ifp = dhd->iflist[idx];
++
++	ASSERT(ifp);
++
++	ifp->dhcp_unicast = val;
++	return BCME_OK;
++}
++
++int dhd_get_block_ping_status(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	ASSERT(ifp);
++
++	return ifp->block_ping;
++}
++
++int dhd_set_block_ping_status(dhd_pub_t *dhdp, uint32 idx, int val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++	ASSERT(idx < DHD_MAX_IFS);
++	ifp = dhd->iflist[idx];
++
++	ASSERT(ifp);
++
++	ifp->block_ping = val;
++	/* Disable rx_pkt_chain feature for interface if block_ping option is
++	 * enabled
++	 */
++	dhd_update_rx_pkt_chainable_state(dhdp, idx);
++	return BCME_OK;
++}
++
++int dhd_get_grat_arp_status(dhd_pub_t *dhdp, uint32 idx)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++
++	ASSERT(idx < DHD_MAX_IFS);
++
++	ifp = dhd->iflist[idx];
++
++	ASSERT(ifp);
++
++	return ifp->grat_arp;
++}
++
++int dhd_set_grat_arp_status(dhd_pub_t *dhdp, uint32 idx, int val)
++{
++	dhd_info_t *dhd = dhdp->info;
++	dhd_if_t *ifp;
++	ASSERT(idx < DHD_MAX_IFS);
++	ifp = dhd->iflist[idx];
++
++	ASSERT(ifp);
++
++	ifp->grat_arp = val;
++
++	return BCME_OK;
++}
++#endif /* DHD_L2_FILTER */
++
++
++#if defined(SET_RPS_CPUS)
++int dhd_rps_cpus_enable(struct net_device *net, int enable)
++{
++	dhd_info_t *dhd = DHD_DEV_INFO(net);
++	dhd_if_t *ifp;
++	int ifidx;
++	char * RPS_CPU_SETBUF;
++
++	ifidx = dhd_net2idx(dhd, net);
++	if (ifidx == DHD_BAD_IF) {
++		DHD_ERROR(("%s bad ifidx\n", __FUNCTION__));
++		return -ENODEV;
++	}
++
++	if (ifidx == PRIMARY_INF) {
++		if (dhd->pub.op_mode == DHD_FLAG_IBSS_MODE) {
++			DHD_INFO(("%s : set for IBSS.\n", __FUNCTION__));
++			RPS_CPU_SETBUF = RPS_CPUS_MASK_IBSS;
++		} else {
++			DHD_INFO(("%s : set for BSS.\n", __FUNCTION__));
++			RPS_CPU_SETBUF = RPS_CPUS_MASK;
++		}
++	} else if (ifidx == VIRTUAL_INF) {
++		DHD_INFO(("%s : set for P2P.\n", __FUNCTION__));
++		RPS_CPU_SETBUF = RPS_CPUS_MASK_P2P;
++	} else {
++		DHD_ERROR(("%s : Invalid index : %d.\n", __FUNCTION__, ifidx));
++		return -EINVAL;
++	}
++
++	ifp = dhd->iflist[ifidx];
++	if (ifp) {
++		if (enable) {
++			DHD_INFO(("%s : set rps_cpus as [%s]\n", __FUNCTION__, RPS_CPU_SETBUF));
++			custom_rps_map_set(ifp->net->_rx, RPS_CPU_SETBUF, strlen(RPS_CPU_SETBUF));
++		} else {
++			custom_rps_map_clear(ifp->net->_rx);
++		}
++	} else {
++		DHD_ERROR(("%s : ifp is NULL!!\n", __FUNCTION__));
++		return -ENODEV;
++	}
++	return BCME_OK;
++}
++
++int custom_rps_map_set(struct netdev_rx_queue *queue, char *buf, size_t len)
++{
++	struct rps_map *old_map, *map;
++	cpumask_var_t mask;
++	int err, cpu, i;
++	static DEFINE_SPINLOCK(rps_map_lock);
++
++	DHD_INFO(("%s : Entered.\n", __FUNCTION__));
++
++	if (!alloc_cpumask_var(&mask, GFP_KERNEL)) {
++		DHD_ERROR(("%s : alloc_cpumask_var fail.\n", __FUNCTION__));
++		return -ENOMEM;
++	}
++
++	err = bitmap_parse(buf, len, cpumask_bits(mask), nr_cpumask_bits);
++	if (err) {
++		free_cpumask_var(mask);
++		DHD_ERROR(("%s : bitmap_parse fail.\n", __FUNCTION__));
++		return err;
++	}
++
++	map = kzalloc(max_t(unsigned int,
++		RPS_MAP_SIZE(cpumask_weight(mask)), L1_CACHE_BYTES),
++		GFP_KERNEL);
++	if (!map) {
++		free_cpumask_var(mask);
++		DHD_ERROR(("%s : map malloc fail.\n", __FUNCTION__));
++		return -ENOMEM;
++	}
++
++	i = 0;
++	for_each_cpu(cpu, mask) {
++		map->cpus[i++] = cpu;
++	}
++
++	if (i) {
++		map->len = i;
++	} else {
++		kfree(map);
++		map = NULL;
++		free_cpumask_var(mask);
++		DHD_ERROR(("%s : mapping cpu fail.\n", __FUNCTION__));
++		return -1;
++	}
++
++	spin_lock(&rps_map_lock);
++	old_map = rcu_dereference_protected(queue->rps_map,
++		lockdep_is_held(&rps_map_lock));
++	rcu_assign_pointer(queue->rps_map, map);
++	spin_unlock(&rps_map_lock);
++
++	if (map) {
++		static_key_slow_inc(&rps_needed);
++	}
++	if (old_map) {
++		kfree_rcu(old_map, rcu);
++		static_key_slow_dec(&rps_needed);
++	}
++	free_cpumask_var(mask);
++
++	DHD_INFO(("%s : Done. mapping cpu nummber : %d\n", __FUNCTION__, map->len));
++	return map->len;
++}
++
++void custom_rps_map_clear(struct netdev_rx_queue *queue)
++{
++	struct rps_map *map;
++
++	DHD_INFO(("%s : Entered.\n", __FUNCTION__));
++
++	map = rcu_dereference_protected(queue->rps_map, 1);
++	if (map) {
++		RCU_INIT_POINTER(queue->rps_map, NULL);
++		kfree_rcu(map, rcu);
++		DHD_INFO(("%s : rps_cpus map clear.\n", __FUNCTION__));
++	}
++}
++#endif 
++
++
++
++#ifdef DHD_DEBUG_PAGEALLOC
++
++void
++dhd_page_corrupt_cb(void *handle, void *addr_corrupt, size_t len)
++{
++	dhd_pub_t *dhdp = (dhd_pub_t *)handle;
++
++	DHD_ERROR(("%s: Got dhd_page_corrupt_cb 0x%p %d\n",
++		__FUNCTION__, addr_corrupt, (uint32)len));
++
++	DHD_OS_WAKE_LOCK(dhdp);
++	prhex("Page Corruption:", addr_corrupt, len);
++	dhd_dump_to_kernelog(dhdp);
++#if defined(BCMPCIE) && defined(DHD_FW_COREDUMP)
++	/* Load the dongle side dump to host memory and then BUG_ON() */
++	dhdp->memdump_enabled = DUMP_MEMONLY;
++	dhdp->memdump_type = DUMP_TYPE_MEMORY_CORRUPTION;
++	dhd_bus_mem_dump(dhdp);
++#endif /* BCMPCIE && DHD_FW_COREDUMP */
++	DHD_OS_WAKE_UNLOCK(dhdp);
++}
++EXPORT_SYMBOL(dhd_page_corrupt_cb);
++
++#ifdef DHD_PKTID_AUDIT_ENABLED
++void
++dhd_pktid_audit_fail_cb(dhd_pub_t *dhdp)
++{
++	DHD_ERROR(("%s: Got Pkt Id Audit failure \n", __FUNCTION__));
++	DHD_OS_WAKE_LOCK(dhdp);
++#if defined(BCMPCIE) && defined(DHD_FW_COREDUMP)
++	/* Load the dongle side dump to host memory and then BUG_ON() */
++	dhdp->memdump_enabled = DUMP_MEMONLY;
++	dhdp->memdump_type = DUMP_TYPE_PKTID_AUDIT_FAILURE;
++	dhd_bus_mem_dump(dhdp);
++#endif /* BCMPCIE && DHD_FW_COREDUMP */
++	DHD_OS_WAKE_UNLOCK(dhdp);
++}
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++#endif /* DHD_DEBUG_PAGEALLOC */
++
++
++#ifdef DHD_DHCP_DUMP
++static void
++dhd_dhcp_dump(uint8 *pktdata, bool tx)
++{
++	struct bootp_fmt *b = (struct bootp_fmt *) &pktdata[ETHER_HDR_LEN];
++	struct iphdr *h = &b->ip_header;
++	uint8 *ptr, *opt, *end = (uint8 *) b + ntohs(b->ip_header.tot_len);
++	int dhcp_type = 0, len, opt_len;
++
++	/* check IP header */
++	if (h->ihl != 5 || h->version != 4 || h->protocol != IPPROTO_UDP) {
++		return;
++	}
++
++	/* check UDP port for bootp (67, 68) */
++	if (b->udp_header.source != htons(67) && b->udp_header.source != htons(68) &&
++			b->udp_header.dest != htons(67) && b->udp_header.dest != htons(68)) {
++		return;
++	}
++
++	/* check header length */
++	if (ntohs(h->tot_len) < ntohs(b->udp_header.len) + sizeof(struct iphdr)) {
++		return;
++	}
++
++	len = ntohs(b->udp_header.len) - sizeof(struct udphdr);
++	opt_len = len
++		- (sizeof(*b) - sizeof(struct iphdr) - sizeof(struct udphdr) - sizeof(b->options));
++
++	/* parse bootp options */
++	if (opt_len >= 4 && !memcmp(b->options, bootp_magic_cookie, 4)) {
++		ptr = &b->options[4];
++		while (ptr < end && *ptr != 0xff) {
++			opt = ptr++;
++			if (*opt == 0) {
++				continue;
++			}
++			ptr += *ptr + 1;
++			if (ptr >= end) {
++				break;
++			}
++			/* 53 is dhcp type */
++			if (*opt == 53) {
++				if (opt[1]) {
++					dhcp_type = opt[2];
++					DHD_ERROR(("DHCP - %s [%s] [%s]\n",
++						dhcp_types[dhcp_type], tx?"TX":"RX",
++						dhcp_ops[b->op]));
++					break;
++				}
++			}
++		}
++	}
++}
++#endif /* DHD_DHCP_DUMP */
++
++
++typedef struct dhd_mon_dev_priv {
++	struct net_device_stats stats;
++} dhd_mon_dev_priv_t;
++
++#define DHD_MON_DEV_PRIV_SIZE		(sizeof(dhd_mon_dev_priv_t))
++#define DHD_MON_DEV_PRIV(dev)		((dhd_mon_dev_priv_t *)DEV_PRIV(dev))
++#define DHD_MON_DEV_STATS(dev)		(((dhd_mon_dev_priv_t *)DEV_PRIV(dev))->stats)
++
++static int
++dhd_monitor_start(struct sk_buff *skb, struct net_device *dev)
++{
++	PKTFREE(NULL, skb, FALSE);
++	return 0;
++}
++
++static int
++dhd_monitor_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
++{
++	return 0;
++}
++
++static struct net_device_stats*
++dhd_monitor_get_stats(struct net_device *dev)
++{
++	return &DHD_MON_DEV_STATS(dev);
++}
++
++static const struct net_device_ops netdev_monitor_ops =
++{
++	.ndo_start_xmit = dhd_monitor_start,
++	.ndo_get_stats = dhd_monitor_get_stats,
++	.ndo_do_ioctl = dhd_monitor_ioctl
++};
++
++static void
++dhd_add_monitor_if(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++	struct net_device *dev;
++	char *devname;
++
++	if (event != DHD_WQ_WORK_IF_ADD) {
++		DHD_ERROR(("%s: unexpected event \n", __FUNCTION__));
++		return;
++	}
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd info not available \n", __FUNCTION__));
++		return;
++	}
++
++	dev = alloc_etherdev(DHD_MON_DEV_PRIV_SIZE);
++	if (!dev) {
++		DHD_ERROR(("%s: alloc wlif failed\n", __FUNCTION__));
++		return;
++	}
++
++	if (dhd->monitor_type == 1)
++		devname = "prism";
++	else
++		devname = "radiotap";
++
++	snprintf(dev->name, sizeof(dev->name), "%s%u", devname, dhd->unit);
++
++#ifndef ARPHRD_IEEE80211_PRISM  /* From Linux 2.4.18 */
++#define ARPHRD_IEEE80211_PRISM 802
++#endif
++
++#ifndef ARPHRD_IEEE80211_RADIOTAP
++#define ARPHRD_IEEE80211_RADIOTAP	803 /* IEEE 802.11 + radiotap header */
++#endif /* ARPHRD_IEEE80211_RADIOTAP */
++
++	if (dhd->monitor_type == 1)
++		dev->type = ARPHRD_IEEE80211_PRISM;
++	else
++		dev->type = ARPHRD_IEEE80211_RADIOTAP;
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31))
++	dev->hard_start_xmit = dhd_monitor_start;
++	dev->do_ioctl = dhd_monitor_ioctl;
++	dev->get_stats = dhd_monitor_get_stats;
++#else
++	dev->netdev_ops = &netdev_monitor_ops;
++#endif
++
++	if (register_netdev(dev)) {
++		DHD_ERROR(("%s, register_netdev failed for %s\n",
++			__FUNCTION__, dev->name));
++		free_netdev(dev);
++	}
++
++	dhd->monitor_dev = dev;
++}
++
++static void
++dhd_del_monitor_if(void *handle, void *event_info, u8 event)
++{
++	dhd_info_t *dhd = handle;
++
++	if (event != DHD_WQ_WORK_IF_DEL) {
++		DHD_ERROR(("%s: unexpected event \n", __FUNCTION__));
++		return;
++	}
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd info not available \n", __FUNCTION__));
++		return;
++	}
++
++	if (dhd->monitor_dev) {
++		unregister_netdev(dhd->monitor_dev);
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
++		MFREE(dhd->osh, dhd->monitor_dev->priv, DHD_MON_DEV_PRIV_SIZE);
++		MFREE(dhd->osh, dhd->monitor_dev, sizeof(struct net_device));
++#else
++		free_netdev(dhd->monitor_dev);
++#endif /* 2.6.24 */
++
++		dhd->monitor_dev = NULL;
++	}
++}
++
++void
++dhd_set_monitor(dhd_pub_t *dhd, int ifidx, int val)
++{
++	dhd_info_t *info = dhd->info;
++
++	DHD_TRACE(("%s: val %d\n", __FUNCTION__, val));
++	if ((val && info->monitor_dev) || (!val && !info->monitor_dev)) {
++		DHD_ERROR(("%s: Mismatched params, return\n", __FUNCTION__));
++		return;
++	}
++
++	/* Delete monitor */
++	if (!val) {
++		info->monitor_type = val;
++		dhd_deferred_schedule_work(info->dhd_deferred_wq, NULL, DHD_WQ_WORK_IF_DEL,
++			dhd_del_monitor_if, DHD_WORK_PRIORITY_LOW);
++		return;
++	}
++
++	/* Add monitor */
++	if (val >= 1 && val <= 3) {
++		info->monitor_type = val;
++		dhd_deferred_schedule_work(info->dhd_deferred_wq, NULL, DHD_WQ_WORK_IF_ADD,
++			dhd_add_monitor_if, DHD_WORK_PRIORITY_LOW);
++	} else {
++		DHD_ERROR(("monitor type %d not supported\n", val));
++		ASSERT(0);
++	}
++}
++
++bool
++dhd_monitor_enabled(dhd_pub_t *dhd, int ifidx)
++{
++	return (dhd->info->monitor_type != 0);
++}
++
++struct net_device *
++dhd_linux_get_primary_netdev(dhd_pub_t *dhdp)
++{
++	dhd_info_t *dhd = dhdp->info;
++
++	if (dhd->iflist[0] && dhd->iflist[0]->net)
++		return dhd->iflist[0]->net;
++	else
++		return NULL;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux.h
+new file mode 100644
+index 000000000..d42c565d9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux.h
+@@ -0,0 +1,136 @@
++/*
++ * DHD Linux header file (dhd_linux exports for cfg80211 and other components)
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_linux.h 399301 2013-04-29 21:41:52Z $
++ */
++
++/* wifi platform functions for power, interrupt and pre-alloc, either
++ * from Android-like platform device data, or Broadcom wifi platform
++ * device data.
++ *
++ */
++#ifndef __DHD_LINUX_H__
++#define __DHD_LINUX_H__
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/fs.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#ifdef DHD_WMF
++#include <dhd_wmf_linux.h>
++#endif
++/* Linux wireless extension support */
++#if defined(WL_WIRELESS_EXT)
++#include <wl_iw.h>
++#endif /* defined(WL_WIRELESS_EXT) */
++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND)
++#include <linux/earlysuspend.h>
++#endif /* defined(CONFIG_HAS_EARLYSUSPEND) && defined(DHD_USE_EARLYSUSPEND) */
++
++#if defined(CONFIG_WIFI_CONTROL_FUNC)
++#include <linux/wlan_plat.h>
++#endif
++
++#if !defined(CONFIG_WIFI_CONTROL_FUNC)
++#define WLAN_PLAT_NODFS_FLAG    0x01
++struct wifi_platform_data {
++	int (*set_power)(int val);
++	int (*set_reset)(int val);
++	int (*set_carddetect)(int val);
++	void *(*mem_prealloc)(int section, unsigned long size);
++	int (*get_mac_addr)(unsigned char *buf);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 58)) || defined(CUSTOM_COUNTRY_CODE)
++	void *(*get_country_code)(char *ccode, u32 flags);
++#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 58)) || defined (CUSTOM_COUNTRY_CODE) */
++	void *(*get_country_code)(char *ccode);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 58)) */
++ };
++#endif /* CONFIG_WIFI_CONTROL_FUNC */
++#define DHD_REGISTRATION_TIMEOUT  12000  /* msec : allowed time to finished dhd registration */
++
++typedef struct wifi_adapter_info {
++	const char	*name;
++	uint		irq_num;
++	uint		intr_flags;
++	const char	*fw_path;
++	const char	*nv_path;
++	void		*wifi_plat_data;	/* wifi ctrl func, for backward compatibility */
++	uint		bus_type;
++	uint		bus_num;
++	uint		slot_num;
++} wifi_adapter_info_t;
++
++typedef struct bcmdhd_wifi_platdata {
++	uint				num_adapters;
++	wifi_adapter_info_t	*adapters;
++} bcmdhd_wifi_platdata_t;
++
++/** Per STA params. A list of dhd_sta objects are managed in dhd_if */
++typedef struct dhd_sta {
++	cumm_ctr_t cumm_ctr;    /* cummulative queue length of child flowrings */
++	uint16 flowid[NUMPRIO]; /* allocated flow ring ids (by priority) */
++	void * ifp;             /* associated dhd_if */
++	struct ether_addr ea;   /* stations ethernet mac address */
++	struct list_head list;  /* link into dhd_if::sta_list */
++	int idx;                /* index of self in dhd_pub::sta_pool[] */
++	int ifidx;              /* index of interface in dhd */
++#ifdef DHD_WMF
++	struct dhd_sta *psta_prim; /* primary index of psta interface */
++#endif /* DHD_WMF */
++} dhd_sta_t;
++typedef dhd_sta_t dhd_sta_pool_t;
++
++int dhd_wifi_platform_register_drv(void);
++void dhd_wifi_platform_unregister_drv(void);
++wifi_adapter_info_t* dhd_wifi_platform_get_adapter(uint32 bus_type, uint32 bus_num,
++	uint32 slot_num);
++int wifi_platform_set_power(wifi_adapter_info_t *adapter, bool on, unsigned long msec);
++int wifi_platform_bus_enumerate(wifi_adapter_info_t *adapter, bool device_present);
++int wifi_platform_get_irq_number(wifi_adapter_info_t *adapter, unsigned long *irq_flags_ptr);
++int wifi_platform_get_mac_addr(wifi_adapter_info_t *adapter, unsigned char *buf);
++#ifdef CUSTOM_COUNTRY_CODE
++void *wifi_platform_get_country_code(wifi_adapter_info_t *adapter, char *ccode,
++   u32 flags);
++#else
++void *wifi_platform_get_country_code(wifi_adapter_info_t *adapter, char *ccode);
++#endif /* CUSTOM_COUNTRY_CODE */
++void* wifi_platform_prealloc(wifi_adapter_info_t *adapter, int section, unsigned long size);
++void* wifi_platform_get_prealloc_func_ptr(wifi_adapter_info_t *adapter);
++
++int dhd_get_fw_mode(struct dhd_info *dhdinfo);
++bool dhd_update_fw_nv_path(struct dhd_info *dhdinfo);
++
++#ifdef DHD_WMF
++dhd_wmf_t* dhd_wmf_conf(dhd_pub_t *dhdp, uint32 idx);
++int dhd_get_wmf_psta_disable(dhd_pub_t *dhdp, uint32 idx);
++int dhd_set_wmf_psta_disable(dhd_pub_t *dhdp, uint32 idx, int val);
++void dhd_update_psta_interface_for_sta(dhd_pub_t *dhdp, char* ifname,
++		void* mac_addr, void* event_data);
++#endif /* DHD_WMF */
++
++void dhd_set_monitor(dhd_pub_t *dhd, int ifidx, int val);
++#endif /* __DHD_LINUX_H__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux_platdev.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux_platdev.c
+new file mode 100644
+index 000000000..2465d8dae
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux_platdev.c
+@@ -0,0 +1,913 @@
++/*
++ * Linux platform device for DHD WLAN adapter
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_linux_platdev.c 401742 2013-05-13 15:03:21Z $
++ */
++#include <typedefs.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <bcmutils.h>
++#include <linux_osl.h>
++#include <dhd_dbg.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_bus.h>
++#include <dhd_linux.h>
++#include <wl_android.h>
++#if defined(CONFIG_WIFI_CONTROL_FUNC)
++#include <linux/wlan_plat.h>
++#endif
++#ifdef BCMDBUS
++#include <dbus.h>
++#endif
++#ifdef CONFIG_DTS
++#include<linux/regulator/consumer.h>
++#include<linux/of_gpio.h>
++#endif /* CONFIG_DTS */
++
++
++#define WIFI_PLAT_NAME		"bcmdhd_wlan"
++#define WIFI_PLAT_NAME2		"bcm4329_wlan"
++#define WIFI_PLAT_EXT		"bcmdhd_wifi_platform"
++
++#ifdef CONFIG_DTS
++struct regulator *wifi_regulator = NULL;
++#endif /* CONFIG_DTS */
++
++bool cfg_multichip = FALSE;
++bcmdhd_wifi_platdata_t *dhd_wifi_platdata = NULL;
++static int wifi_plat_dev_probe_ret = 0;
++static bool is_power_on = FALSE;
++#if !defined(CONFIG_DTS)
++#if defined(DHD_OF_SUPPORT)
++static bool dts_enabled = TRUE;
++extern struct resource dhd_wlan_resources;
++//extern struct wifi_platform_data dhd_wlan_control;
++struct wifi_platform_data dhd_wlan_control;
++#else
++static bool dts_enabled = FALSE;
++struct resource dhd_wlan_resources = {0};
++struct wifi_platform_data dhd_wlan_control = {0};
++#endif /* CONFIG_OF && !defined(CONFIG_ARCH_MSM) */
++#endif /* !defind(CONFIG_DTS) */
++
++static int dhd_wifi_platform_load(void);
++
++extern void* wl_cfg80211_get_dhdp(void);
++
++#ifdef CUSTOMER_OOB
++extern int dhd_init_gpio_wlan_hostwake(void);
++extern void dhd_deinit_gpio_wlan_hostwake(void);
++#endif
++
++#ifdef ENABLE_4335BT_WAR
++extern int bcm_bt_lock(int cookie);
++extern void bcm_bt_unlock(int cookie);
++static int lock_cookie_wifi = 'W' | 'i'<<8 | 'F'<<16 | 'i'<<24;	/* cookie is "WiFi" */
++#endif /* ENABLE_4335BT_WAR */
++
++wifi_adapter_info_t* dhd_wifi_platform_get_adapter(uint32 bus_type, uint32 bus_num, uint32 slot_num)
++{
++	int i;
++
++	if (dhd_wifi_platdata == NULL)
++		return NULL;
++
++	for (i = 0; i < dhd_wifi_platdata->num_adapters; i++) {
++		wifi_adapter_info_t *adapter = &dhd_wifi_platdata->adapters[i];
++		if ((adapter->bus_type == -1 || adapter->bus_type == bus_type) &&
++			(adapter->bus_num == -1 || adapter->bus_num == bus_num) &&
++			(adapter->slot_num == -1 || adapter->slot_num == slot_num)) {
++			DHD_TRACE(("found adapter info '%s'\n", adapter->name));
++			return adapter;
++		}
++	}
++	return NULL;
++}
++
++void* wifi_platform_prealloc(wifi_adapter_info_t *adapter, int section, unsigned long size)
++{
++	void *alloc_ptr = NULL;
++	struct wifi_platform_data *plat_data;
++
++	if (!adapter || !adapter->wifi_plat_data)
++		return NULL;
++	plat_data = adapter->wifi_plat_data;
++	if (plat_data->mem_prealloc) {
++		alloc_ptr = plat_data->mem_prealloc(section, size);
++		if (alloc_ptr) {
++			DHD_INFO(("success alloc section %d\n", section));
++			if (size != 0L)
++				bzero(alloc_ptr, size);
++			return alloc_ptr;
++		}
++	}
++
++	DHD_ERROR(("%s: failed to alloc static mem section %d\n", __FUNCTION__, section));
++	return NULL;
++}
++
++void* wifi_platform_get_prealloc_func_ptr(wifi_adapter_info_t *adapter)
++{
++	struct wifi_platform_data *plat_data;
++
++	if (!adapter || !adapter->wifi_plat_data)
++		return NULL;
++	plat_data = adapter->wifi_plat_data;
++	return plat_data->mem_prealloc;
++}
++
++int wifi_platform_get_irq_number(wifi_adapter_info_t *adapter, unsigned long *irq_flags_ptr)
++{
++	if (adapter == NULL)
++		return -1;
++	if (irq_flags_ptr)
++		*irq_flags_ptr = adapter->intr_flags;
++	return adapter->irq_num;
++}
++
++int wifi_platform_set_power(wifi_adapter_info_t *adapter, bool on, unsigned long msec)
++{
++	int err = 0;
++#ifdef CONFIG_DTS
++	if (on) {
++		err = regulator_enable(wifi_regulator);
++		is_power_on = TRUE;
++	}
++	else {
++		err = regulator_disable(wifi_regulator);
++		is_power_on = FALSE;
++	}
++	if (err < 0)
++		DHD_ERROR(("%s: regulator enable/disable failed", __FUNCTION__));
++#else
++	struct wifi_platform_data *plat_data;
++
++	if (!adapter || !adapter->wifi_plat_data)
++		return -EINVAL;
++	plat_data = adapter->wifi_plat_data;
++
++	DHD_ERROR(("%s = %d\n", __FUNCTION__, on));
++	if (plat_data->set_power) {
++#ifdef ENABLE_4335BT_WAR
++		if (on) {
++			printk("WiFi: trying to acquire BT lock\n");
++			if (bcm_bt_lock(lock_cookie_wifi) != 0)
++				printk("** WiFi: timeout in acquiring bt lock**\n");
++			printk("%s: btlock acquired\n", __FUNCTION__);
++		}
++		else {
++			/* For a exceptional case, release btlock */
++			bcm_bt_unlock(lock_cookie_wifi);
++		}
++#endif /* ENABLE_4335BT_WAR */
++
++		err = plat_data->set_power(on);
++	}
++
++	if (msec && !err)
++		OSL_SLEEP(msec);
++
++	if (on && !err)
++		is_power_on = TRUE;
++	else
++		is_power_on = FALSE;
++
++#endif /* CONFIG_DTS */
++/*power on bcm43455---->*/
++	err = dhd_customer_gpio_wlan_ctrl(adapter, on);
++	if (msec && !err)
++		OSL_SLEEP(msec);
++
++	return err;
++}
++
++#if defined(CUSTOMER_IMX)
++extern void wifi_card_detect(bool);
++int wifi_platform_bus_enumerate(wifi_adapter_info_t *adapter, bool device_present)
++{
++	int err = 0;
++	struct wifi_platform_data *plat_data;
++
++	if (!adapter) {
++		pr_err("!!!! %s: failed!  adapter variable is NULL!!!!!\n", __FUNCTION__);
++		return -EINVAL;
++	}
++
++	DHD_ERROR(("%s device present %d\n", __FUNCTION__, device_present));
++
++	if (!adapter->wifi_plat_data) {
++		wifi_card_detect(device_present); /* hook for card_detect */
++	} else {
++		plat_data = adapter->wifi_plat_data;
++		if (plat_data->set_carddetect)
++			err = plat_data->set_carddetect(device_present);
++	}
++
++	return 0; /* force success status returned */
++}
++#else
++int wifi_platform_bus_enumerate(wifi_adapter_info_t *adapter, bool device_present)
++{
++	int err = 0;
++	struct wifi_platform_data *plat_data;
++
++	if (!adapter || !adapter->wifi_plat_data)
++		return -EINVAL;
++	plat_data = adapter->wifi_plat_data;
++
++	DHD_ERROR(("%s device present %d\n", __FUNCTION__, device_present));
++	if (plat_data->set_carddetect) {
++		err = plat_data->set_carddetect(device_present);
++	}
++	return err;
++
++}
++#endif /* CUSTOMER_IMX */
++
++int wifi_platform_get_mac_addr(wifi_adapter_info_t *adapter, unsigned char *buf)
++{
++	struct wifi_platform_data *plat_data;
++
++	DHD_ERROR(("%s\n", __FUNCTION__));
++	if (!buf || !adapter || !adapter->wifi_plat_data)
++		return -EINVAL;
++	plat_data = adapter->wifi_plat_data;
++	if (plat_data->get_mac_addr) {
++		return plat_data->get_mac_addr(buf);
++	}
++	return -EOPNOTSUPP;
++}
++#ifdef CUSTOM_COUNTRY_CODE
++void *wifi_platform_get_country_code(wifi_adapter_info_t *adapter, char *ccode, u32 flags)
++#else
++void *wifi_platform_get_country_code(wifi_adapter_info_t *adapter, char *ccode)
++#endif /* CUSTOM_COUNTRY_CODE */
++{
++	/* get_country_code was added after 2.6.39 */
++#if	(LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39))
++	struct wifi_platform_data *plat_data;
++
++	if (!ccode || !adapter || !adapter->wifi_plat_data)
++		return NULL;
++	plat_data = adapter->wifi_plat_data;
++
++	DHD_TRACE(("%s\n", __FUNCTION__));
++	if (plat_data->get_country_code) {
++#if     (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 58))
++		return plat_data->get_country_code(ccode, WLAN_PLAT_NODFS_FLAG);
++#else
++#ifdef CUSTOM_COUNTRY_CODE
++		return plat_data->get_country_code(ccode, flags);
++#else
++		return plat_data->get_country_code(ccode);
++#endif /* CUSTOM_COUNTRY_CODE */
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 58)) */
++	}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) */
++
++	return NULL;
++}
++
++static int wifi_plat_dev_drv_probe(struct platform_device *pdev)
++{
++	struct resource *resource;
++	wifi_adapter_info_t *adapter;
++#ifdef CONFIG_DTS
++	int irq, gpio;
++#endif /* CONFIG_DTS */
++
++	/* Android style wifi platform data device ("bcmdhd_wlan" or "bcm4329_wlan")
++	 * is kept for backward compatibility and supports only 1 adapter
++	 */
++	ASSERT(dhd_wifi_platdata != NULL);
++	ASSERT(dhd_wifi_platdata->num_adapters == 1);
++	adapter = &dhd_wifi_platdata->adapters[0];
++	adapter->wifi_plat_data = (struct wifi_platform_data *)(pdev->dev.platform_data);
++
++	resource = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "bcmdhd_wlan_irq");
++	if (resource == NULL)
++		resource = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "bcm4329_wlan_irq");
++	if (resource) {
++		adapter->irq_num = resource->start;
++		adapter->intr_flags = resource->flags & IRQF_TRIGGER_MASK;
++	}
++
++#ifdef CONFIG_DTS
++	wifi_regulator = regulator_get(&pdev->dev, "wlreg_on");
++	if (wifi_regulator == NULL) {
++		DHD_ERROR(("%s regulator is null\n", __FUNCTION__));
++		return -1;
++	}
++
++	/* This is to get the irq for the OOB */
++	gpio = of_get_gpio(pdev->dev.of_node, 0);
++
++	if (gpio < 0) {
++		DHD_ERROR(("%s gpio information is incorrect\n", __FUNCTION__));
++		return -1;
++	}
++	irq = gpio_to_irq(gpio);
++	if (irq < 0) {
++		DHD_ERROR(("%s irq information is incorrect\n", __FUNCTION__));
++		return -1;
++	}
++	adapter->irq_num = irq;
++
++	/* need to change the flags according to our requirement */
++	adapter->intr_flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL |
++		IORESOURCE_IRQ_SHAREABLE;
++#endif /* CONFIG_DTS */
++
++	wifi_plat_dev_probe_ret = dhd_wifi_platform_load();
++	return wifi_plat_dev_probe_ret;
++}
++
++static int wifi_plat_dev_drv_remove(struct platform_device *pdev)
++{
++	wifi_adapter_info_t *adapter;
++
++	/* Android style wifi platform data device ("bcmdhd_wlan" or "bcm4329_wlan")
++	 * is kept for backward compatibility and supports only 1 adapter
++	 */
++	ASSERT(dhd_wifi_platdata != NULL);
++	ASSERT(dhd_wifi_platdata->num_adapters == 1);
++	adapter = &dhd_wifi_platdata->adapters[0];
++	if (is_power_on) {
++#ifdef BCMPCIE
++		wifi_platform_bus_enumerate(adapter, FALSE);
++		wifi_platform_set_power(adapter, FALSE, WIFI_TURNOFF_DELAY);
++#else
++		wifi_platform_set_power(adapter, FALSE, WIFI_TURNOFF_DELAY);
++		wifi_platform_bus_enumerate(adapter, FALSE);
++#endif /* BCMPCIE */
++	}
++
++#ifdef CONFIG_DTS
++	regulator_put(wifi_regulator);
++#endif /* CONFIG_DTS */
++	return 0;
++}
++
++static int wifi_plat_dev_drv_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	DHD_TRACE(("##> %s\n", __FUNCTION__));
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY) && \
++	defined(BCMSDIO)
++	bcmsdh_oob_intr_set(0);
++#endif /* (OOB_INTR_ONLY) */
++	return 0;
++}
++
++static int wifi_plat_dev_drv_resume(struct platform_device *pdev)
++{
++	DHD_TRACE(("##> %s\n", __FUNCTION__));
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY) && \
++	defined(BCMSDIO)
++	if (dhd_os_check_if_up(wl_cfg80211_get_dhdp()))
++		bcmsdh_oob_intr_set(1);
++#endif /* (OOB_INTR_ONLY) */
++	return 0;
++}
++
++#ifdef CONFIG_DTS
++static const struct of_device_id wifi_device_dt_match[] = {
++	{ .compatible = "android,bcmdhd_wlan", },
++	{},
++};
++#endif /* CONFIG_DTS */
++static struct platform_driver wifi_platform_dev_driver = {
++	.probe          = wifi_plat_dev_drv_probe,
++	.remove         = wifi_plat_dev_drv_remove,
++	.suspend        = wifi_plat_dev_drv_suspend,
++	.resume         = wifi_plat_dev_drv_resume,
++	.driver         = {
++	.name   = WIFI_PLAT_NAME,
++#ifdef CONFIG_DTS
++	.of_match_table = wifi_device_dt_match,
++#endif /* CONFIG_DTS */
++	}
++};
++
++static struct platform_driver wifi_platform_dev_driver_legacy = {
++	.probe          = wifi_plat_dev_drv_probe,
++	.remove         = wifi_plat_dev_drv_remove,
++	.suspend        = wifi_plat_dev_drv_suspend,
++	.resume         = wifi_plat_dev_drv_resume,
++	.driver         = {
++	.name	= WIFI_PLAT_NAME2,
++	}
++};
++
++static int wifi_platdev_match(struct device *dev, const void *data)
++{
++	char *name = (char*)data;
++	struct platform_device *pdev = to_platform_device(dev);
++
++	if (strcmp(pdev->name, name) == 0) {
++		DHD_ERROR(("found wifi platform device %s\n", name));
++		return TRUE;
++	}
++
++	return FALSE;
++}
++
++static int wifi_ctrlfunc_register_drv(void)
++{
++	int err = 0;
++	struct device *dev1, *dev2;
++	wifi_adapter_info_t *adapter;
++
++	dev1 = bus_find_device(&platform_bus_type, NULL, WIFI_PLAT_NAME, wifi_platdev_match);
++	dev2 = bus_find_device(&platform_bus_type, NULL, WIFI_PLAT_NAME2, wifi_platdev_match);
++
++#if !defined(CONFIG_DTS)
++	if (!dts_enabled) {
++		if (dev1 == NULL && dev2 == NULL) {
++			DHD_ERROR(("no wifi platform data, skip\n"));
++			return -ENXIO;
++		}
++	}
++#endif /* !defined(CONFIG_DTS) */
++
++	/* multi-chip support not enabled, build one adapter information for
++	 * DHD (either SDIO, USB or PCIe)
++	 */
++	adapter = kzalloc(sizeof(wifi_adapter_info_t), GFP_KERNEL);
++	if (adapter == NULL) {
++		DHD_ERROR(("%s:adapter alloc failed", __FUNCTION__));
++		return ENOMEM;
++	}
++	adapter->name = "DHD generic adapter";
++	adapter->bus_type = -1;
++	adapter->bus_num = -1;
++	adapter->slot_num = -1;
++	adapter->irq_num = -1;
++	is_power_on = FALSE;
++	wifi_plat_dev_probe_ret = 0;
++	dhd_wifi_platdata = kzalloc(sizeof(bcmdhd_wifi_platdata_t), GFP_KERNEL);
++	dhd_wifi_platdata->num_adapters = 1;
++	dhd_wifi_platdata->adapters = adapter;
++
++	if (dev1) {
++		err = platform_driver_register(&wifi_platform_dev_driver);
++		if (err) {
++			DHD_ERROR(("%s: failed to register wifi ctrl func driver\n",
++				__FUNCTION__));
++			return err;
++		}
++	}
++	if (dev2) {
++		err = platform_driver_register(&wifi_platform_dev_driver_legacy);
++		if (err) {
++			DHD_ERROR(("%s: failed to register wifi ctrl func legacy driver\n",
++				__FUNCTION__));
++			return err;
++		}
++	}
++
++#if !defined(CONFIG_DTS)
++	if (dts_enabled) {
++		struct resource *resource;
++
++#if defined(CUSTOMER_OOB)
++		wifi_plat_dev_probe_ret = dhd_init_gpio_wlan_hostwake();
++		if (wifi_plat_dev_probe_ret)
++			return wifi_plat_dev_probe_ret;
++#endif
++		adapter->wifi_plat_data = (void *)&dhd_wlan_control;
++		resource = &dhd_wlan_resources;
++		adapter->irq_num = resource->start;
++		adapter->intr_flags = resource->flags & IRQF_TRIGGER_MASK;
++		wifi_plat_dev_probe_ret = dhd_wifi_platform_load();
++	}
++#endif /* !defined(CONFIG_DTS) */
++
++
++#ifdef CONFIG_DTS
++	wifi_plat_dev_probe_ret = platform_driver_register(&wifi_platform_dev_driver);
++#endif /* CONFIG_DTS */
++
++	/* return probe function's return value if registeration succeeded */
++	return wifi_plat_dev_probe_ret;
++}
++
++void wifi_ctrlfunc_unregister_drv(void)
++{
++
++#ifdef CONFIG_DTS
++	DHD_ERROR(("unregister wifi platform drivers\n"));
++	platform_driver_unregister(&wifi_platform_dev_driver);
++#else
++	struct device *dev1, *dev2;
++	dev1 = bus_find_device(&platform_bus_type, NULL, WIFI_PLAT_NAME, wifi_platdev_match);
++	dev2 = bus_find_device(&platform_bus_type, NULL, WIFI_PLAT_NAME2, wifi_platdev_match);
++	if (!dts_enabled)
++		if (dev1 == NULL && dev2 == NULL)
++			return;
++
++	DHD_ERROR(("unregister wifi platform drivers\n"));
++	if (dev1)
++		platform_driver_unregister(&wifi_platform_dev_driver);
++	if (dev2)
++		platform_driver_unregister(&wifi_platform_dev_driver_legacy);
++	if (dts_enabled) {
++		wifi_adapter_info_t *adapter;
++		adapter = &dhd_wifi_platdata->adapters[0];
++		if (is_power_on) {
++			wifi_platform_set_power(adapter, FALSE, WIFI_TURNOFF_DELAY);
++			wifi_platform_bus_enumerate(adapter, FALSE);
++		}
++	}
++#endif /* !defined(CONFIG_DTS) */
++
++#if defined(CUSTOMER_OOB)
++	dhd_deinit_gpio_wlan_hostwake();
++#endif
++
++	kfree(dhd_wifi_platdata->adapters);
++	dhd_wifi_platdata->adapters = NULL;
++	dhd_wifi_platdata->num_adapters = 0;
++	kfree(dhd_wifi_platdata);
++	dhd_wifi_platdata = NULL;
++}
++
++static int bcmdhd_wifi_plat_dev_drv_probe(struct platform_device *pdev)
++{
++	dhd_wifi_platdata = (bcmdhd_wifi_platdata_t *)(pdev->dev.platform_data);
++
++	return dhd_wifi_platform_load();
++}
++
++static int bcmdhd_wifi_plat_dev_drv_remove(struct platform_device *pdev)
++{
++	int i;
++	wifi_adapter_info_t *adapter;
++	ASSERT(dhd_wifi_platdata != NULL);
++
++	/* power down all adapters */
++	for (i = 0; i < dhd_wifi_platdata->num_adapters; i++) {
++		adapter = &dhd_wifi_platdata->adapters[i];
++		wifi_platform_set_power(adapter, FALSE, WIFI_TURNOFF_DELAY);
++		wifi_platform_bus_enumerate(adapter, FALSE);
++	}
++	return 0;
++}
++
++static struct platform_driver dhd_wifi_platform_dev_driver = {
++	.probe          = bcmdhd_wifi_plat_dev_drv_probe,
++	.remove         = bcmdhd_wifi_plat_dev_drv_remove,
++	.driver         = {
++	.name   = WIFI_PLAT_EXT,
++	}
++};
++
++int dhd_wifi_platform_register_drv(void)
++{
++	int err = 0;
++	struct device *dev;
++
++	/* register Broadcom wifi platform data driver if multi-chip is enabled,
++	 * otherwise use Android style wifi platform data (aka wifi control function)
++	 * if it exists
++	 *
++	 * to support multi-chip DHD, Broadcom wifi platform data device must
++	 * be added in kernel early boot (e.g. board config file).
++	 */
++	if (cfg_multichip) {
++		dev = bus_find_device(&platform_bus_type, NULL, WIFI_PLAT_EXT, wifi_platdev_match);
++		if (dev == NULL) {
++			DHD_ERROR(("bcmdhd wifi platform data device not found!!\n"));
++			return -ENXIO;
++		}
++		err = platform_driver_register(&dhd_wifi_platform_dev_driver);
++	} else {
++		err = wifi_ctrlfunc_register_drv();
++
++		/* no wifi ctrl func either, load bus directly and ignore this error */
++		if (err) {
++			if (err == -ENXIO) {
++				/* wifi ctrl function does not exist */
++				err = dhd_wifi_platform_load();
++			} else {
++				/* unregister driver due to initialization failure */
++				wifi_ctrlfunc_unregister_drv();
++			}
++		}
++	}
++
++	return err;
++}
++
++#ifdef BCMPCIE
++static int dhd_wifi_platform_load_pcie(void)
++{
++	int err = 0;
++	int i;
++	wifi_adapter_info_t *adapter;
++
++	BCM_REFERENCE(i);
++	BCM_REFERENCE(adapter);
++
++	if (dhd_wifi_platdata == NULL) {
++		err = dhd_bus_register();
++	} else {
++		if (dhd_download_fw_on_driverload) {
++			/* power up all adapters */
++			for (i = 0; i < dhd_wifi_platdata->num_adapters; i++) {
++				int retry = POWERUP_MAX_RETRY;
++				adapter = &dhd_wifi_platdata->adapters[i];
++
++				DHD_ERROR(("Power-up adapter '%s'\n", adapter->name));
++				DHD_INFO((" - irq %d [flags %d], firmware: %s, nvram: %s\n",
++					adapter->irq_num, adapter->intr_flags, adapter->fw_path,
++					adapter->nv_path));
++				DHD_INFO((" - bus type %d, bus num %d, slot num %d\n\n",
++					adapter->bus_type, adapter->bus_num, adapter->slot_num));
++
++				do {
++					err = wifi_platform_set_power(adapter,
++						TRUE, WIFI_TURNON_DELAY);
++					if (err) {
++						DHD_ERROR(("failed to power up %s,"
++							" %d retry left\n",
++							adapter->name, retry));
++						/* WL_REG_ON state unknown, Power off forcely */
++						wifi_platform_set_power(adapter,
++							FALSE, WIFI_TURNOFF_DELAY);
++						continue;
++					} else {
++						err = wifi_platform_bus_enumerate(adapter, TRUE);
++						if (err) {
++							DHD_ERROR(("failed to enumerate bus %s, "
++								"%d retry left\n",
++								adapter->name, retry));
++							wifi_platform_set_power(adapter, FALSE,
++								WIFI_TURNOFF_DELAY);
++						} else {
++							break;
++						}
++					}
++				} while (retry--);
++
++				if (retry < 0) {
++					DHD_ERROR(("failed to power up %s, max retry reached**\n",
++						adapter->name));
++					return -ENODEV;
++				}
++			}
++		}
++
++		err = dhd_bus_register();
++
++		if (err) {
++			DHD_ERROR(("%s: pcie_register_driver failed\n", __FUNCTION__));
++			if (dhd_download_fw_on_driverload) {
++				/* power down all adapters */
++				for (i = 0; i < dhd_wifi_platdata->num_adapters; i++) {
++					adapter = &dhd_wifi_platdata->adapters[i];
++					wifi_platform_bus_enumerate(adapter, FALSE);
++					wifi_platform_set_power(adapter,
++						FALSE, WIFI_TURNOFF_DELAY);
++				}
++			}
++		}
++	}
++
++	return err;
++}
++#else
++static int dhd_wifi_platform_load_pcie(void)
++{
++	return 0;
++}
++#endif /* BCMPCIE  */
++
++
++void dhd_wifi_platform_unregister_drv(void)
++{
++	if (cfg_multichip)
++		platform_driver_unregister(&dhd_wifi_platform_dev_driver);
++	else
++		wifi_ctrlfunc_unregister_drv();
++}
++
++extern int dhd_watchdog_prio;
++extern int dhd_dpc_prio;
++extern uint dhd_deferred_tx;
++#if defined(BCMLXSDMMC)
++extern struct semaphore dhd_registration_sem;
++#endif 
++
++#ifdef BCMSDIO
++static int dhd_wifi_platform_load_sdio(void)
++{
++	int i;
++	int err = 0;
++	wifi_adapter_info_t *adapter;
++
++	BCM_REFERENCE(i);
++	BCM_REFERENCE(adapter);
++	/* Sanity check on the module parameters
++	 * - Both watchdog and DPC as tasklets are ok
++	 * - If both watchdog and DPC are threads, TX must be deferred
++	 */
++	if (!(dhd_watchdog_prio < 0 && dhd_dpc_prio < 0) &&
++		!(dhd_watchdog_prio >= 0 && dhd_dpc_prio >= 0 && dhd_deferred_tx))
++		return -EINVAL;
++
++#if defined(BCMLXSDMMC)
++	sema_init(&dhd_registration_sem, 0);
++#endif
++
++	if (dhd_wifi_platdata == NULL) {
++		DHD_ERROR(("DHD wifi platform data is required for Android build\n"));
++		DHD_ERROR(("DHD registeing bus directly\n"));
++		/* x86 bring-up PC needs no power-up operations */
++		err = dhd_bus_register();
++		return err;
++	}
++
++#if defined(BCMLXSDMMC)
++	/* power up all adapters */
++	for (i = 0; i < dhd_wifi_platdata->num_adapters; i++) {
++		bool chip_up = FALSE;
++		int retry = POWERUP_MAX_RETRY;
++		struct semaphore dhd_chipup_sem;
++
++		adapter = &dhd_wifi_platdata->adapters[i];
++
++		DHD_ERROR(("Power-up adapter '%s'\n", adapter->name));
++		DHD_INFO((" - irq %d [flags %d], firmware: %s, nvram: %s\n",
++			adapter->irq_num, adapter->intr_flags, adapter->fw_path, adapter->nv_path));
++		DHD_INFO((" - bus type %d, bus num %d, slot num %d\n\n",
++			adapter->bus_type, adapter->bus_num, adapter->slot_num));
++
++		do {
++			sema_init(&dhd_chipup_sem, 0);
++			err = dhd_bus_reg_sdio_notify(&dhd_chipup_sem);
++			if (err) {
++				DHD_ERROR(("%s dhd_bus_reg_sdio_notify fail(%d)\n\n",
++					__FUNCTION__, err));
++				return err;
++			}
++
++			/*case: sdio device probed earlier than wifi driver.*/
++			if(down_trylock(&dhd_chipup_sem) == 0) {
++				dhd_bus_unreg_sdio_notify();
++				chip_up = TRUE;
++				break;
++			}
++
++			err = wifi_platform_set_power(adapter, TRUE, WIFI_TURNON_DELAY);
++			if (err) {
++				/* WL_REG_ON state unknown, Power off forcely */
++				wifi_platform_set_power(adapter, FALSE, WIFI_TURNOFF_DELAY);
++				continue;
++			} else {
++				wifi_platform_bus_enumerate(adapter, TRUE);
++				err = 0;
++			}
++
++			if (down_timeout(&dhd_chipup_sem, msecs_to_jiffies(POWERUP_WAIT_MS)) == 0) {
++				dhd_bus_unreg_sdio_notify();
++				chip_up = TRUE;
++				break;
++			}
++
++			DHD_ERROR(("failed to power up %s, %d retry left\n", adapter->name, retry));
++			dhd_bus_unreg_sdio_notify();
++			wifi_platform_set_power(adapter, FALSE, WIFI_TURNOFF_DELAY);
++			wifi_platform_bus_enumerate(adapter, FALSE);
++		} while (retry--);
++
++		if (!chip_up) {
++			DHD_ERROR(("failed to power up %s, max retry reached**\n", adapter->name));
++			return -ENODEV;
++		}
++
++	}
++
++	err = dhd_bus_register();
++
++	if (err) {
++		DHD_ERROR(("%s: sdio_register_driver failed\n", __FUNCTION__));
++		goto fail;
++	}
++
++	/*
++	 * Wait till MMC sdio_register_driver callback called and made driver attach.
++	 * It's needed to make sync up exit from dhd insmod  and
++	 * Kernel MMC sdio device callback registration
++	 */
++	err = down_timeout(&dhd_registration_sem, msecs_to_jiffies(DHD_REGISTRATION_TIMEOUT));
++	if (err) {
++		DHD_ERROR(("%s: sdio_register_driver timeout or error \n", __FUNCTION__));
++		dhd_bus_unregister();
++		goto fail;
++	}
++
++	return err;
++
++fail:
++	/* power down all adapters */
++	for (i = 0; i < dhd_wifi_platdata->num_adapters; i++) {
++		adapter = &dhd_wifi_platdata->adapters[i];
++		wifi_platform_set_power(adapter, FALSE, WIFI_TURNOFF_DELAY);
++		wifi_platform_bus_enumerate(adapter, FALSE);
++	}
++#endif 
++
++	return err;
++}
++#else /* BCMSDIO */
++static int dhd_wifi_platform_load_sdio(void)
++{
++	return 0;
++}
++#endif /* BCMSDIO */
++
++#ifdef BCMDBUS
++/* User-specified vid/pid */
++int dhd_vid = 0xa5c;
++int dhd_pid = 0x48f;
++module_param(dhd_vid, int, 0);
++module_param(dhd_pid, int, 0);
++void *dhd_dbus_probe_cb(void *arg, const char *desc, uint32 bustype, uint32 hdrlen);
++void dhd_dbus_disconnect_cb(void *arg);
++
++static int dhd_wifi_platform_load_usb(void)
++{
++	int err = 0;
++
++	if (dhd_vid < 0 || dhd_vid > 0xffff) {
++		DHD_ERROR(("%s: invalid dhd_vid 0x%x\n", __FUNCTION__, dhd_vid));
++		return -EINVAL;
++	}
++	if (dhd_pid < 0 || dhd_pid > 0xffff) {
++		DHD_ERROR(("%s: invalid dhd_pid 0x%x\n", __FUNCTION__, dhd_pid));
++		return -EINVAL;
++	}
++
++	err = dbus_register(dhd_vid, dhd_pid, dhd_dbus_probe_cb, dhd_dbus_disconnect_cb,
++		NULL, NULL, NULL);
++
++	/* Device not detected */
++	if (err == DBUS_ERR_NODEVICE)
++		err = DBUS_OK;
++
++	return err;
++}
++#else /* BCMDBUS */
++static int dhd_wifi_platform_load_usb(void)
++{
++	return 0;
++}
++#endif /* BCMDBUS */
++
++static int dhd_wifi_platform_load()
++{
++	int err = 0;
++
++		wl_android_init();
++
++	if ((err = dhd_wifi_platform_load_usb()))
++		goto end;
++	else if ((err = dhd_wifi_platform_load_sdio()))
++		goto end;
++	else
++		err = dhd_wifi_platform_load_pcie();
++
++end:
++	if (err)
++		wl_android_exit();
++	else
++		wl_android_post_init();
++
++	return err;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux_sched.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux_sched.c
+new file mode 100644
+index 000000000..a5bf43a5c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux_sched.c
+@@ -0,0 +1,51 @@
++/*
++ * Expose some of the kernel scheduler routines
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_linux_sched.c 514727 2014-11-12 03:02:48Z $
++ */
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/sched.h>
++#include <typedefs.h>
++#include <linuxver.h>
++
++int setScheduler(struct task_struct *p, int policy, struct sched_param *param)
++{
++	int rc = 0;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++	rc = sched_setscheduler(p, policy, param);
++#endif /* LinuxVer */
++	return rc;
++}
++
++int get_scheduler_policy(struct task_struct *p)
++{
++	int rc = SCHED_NORMAL;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++	rc = p->policy;
++#endif /* LinuxVer */
++	return rc;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux_wq.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux_wq.c
+new file mode 100644
+index 000000000..282264134
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux_wq.c
+@@ -0,0 +1,320 @@
++/*
++ * Broadcom Dongle Host Driver (DHD), Generic work queue framework
++ * Generic interface to handle dhd deferred work events
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_linux_wq.c 514727 2014-11-12 03:02:48Z $
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/spinlock.h>
++#include <linux/fcntl.h>
++#include <linux/fs.h>
++#include <linux/ip.h>
++#include <linux/kfifo.h>
++
++#include <linuxver.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <bcmdevs.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_dbg.h>
++#include <dhd_linux_wq.h>
++
++struct dhd_deferred_event_t {
++	u8	event; /* holds the event */
++	void	*event_data; /* Holds event specific data */
++	event_handler_t event_handler;
++};
++#define DEFRD_EVT_SIZE	sizeof(struct dhd_deferred_event_t)
++
++struct dhd_deferred_wq {
++	struct work_struct	deferred_work; /* should be the first member */
++
++	/*
++	 * work events may occur simultaneously.
++	 * Can hold upto 64 low priority events and 4 high priority events
++	 */
++#define DHD_PRIO_WORK_FIFO_SIZE	(4 * sizeof(struct dhd_deferred_event_t))
++#define DHD_WORK_FIFO_SIZE	(64 * sizeof(struct dhd_deferred_event_t))
++	struct kfifo			*prio_fifo;
++	struct kfifo			*work_fifo;
++	u8				*prio_fifo_buf;
++	u8				*work_fifo_buf;
++	spinlock_t			work_lock;
++	void				*dhd_info; /* review: does it require */
++};
++
++static inline struct kfifo*
++dhd_kfifo_init(u8 *buf, int size, spinlock_t *lock)
++{
++	struct kfifo *fifo;
++	gfp_t flags = CAN_SLEEP()? GFP_KERNEL : GFP_ATOMIC;
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33))
++	fifo = kfifo_init(buf, size, flags, lock);
++#else
++	fifo = (struct kfifo *)kzalloc(sizeof(struct kfifo), flags);
++	if (!fifo) {
++		return NULL;
++	}
++	kfifo_init(fifo, buf, size);
++#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33)) */
++	return fifo;
++}
++
++static inline void
++dhd_kfifo_free(struct kfifo *fifo)
++{
++	kfifo_free(fifo);
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 31))
++	/* FC11 releases the fifo memory */
++	kfree(fifo);
++#endif
++}
++
++/* deferred work functions */
++static void dhd_deferred_work_handler(struct work_struct *data);
++
++void*
++dhd_deferred_work_init(void *dhd_info)
++{
++	struct dhd_deferred_wq	*work = NULL;
++	u8*	buf;
++	unsigned long	fifo_size = 0;
++	gfp_t	flags = CAN_SLEEP()? GFP_KERNEL : GFP_ATOMIC;
++
++	if (!dhd_info) {
++		DHD_ERROR(("%s: dhd info not initialized\n", __FUNCTION__));
++		goto return_null;
++	}
++
++	work = (struct dhd_deferred_wq *)kzalloc(sizeof(struct dhd_deferred_wq),
++		flags);
++
++	if (!work) {
++		DHD_ERROR(("%s: work queue creation failed \n", __FUNCTION__));
++		goto return_null;
++	}
++
++	INIT_WORK((struct work_struct *)work, dhd_deferred_work_handler);
++
++	/* initialize event fifo */
++	spin_lock_init(&work->work_lock);
++
++	/* allocate buffer to hold prio events */
++	fifo_size = DHD_PRIO_WORK_FIFO_SIZE;
++	fifo_size = is_power_of_2(fifo_size)? fifo_size : roundup_pow_of_two(fifo_size);
++	buf = (u8*)kzalloc(fifo_size, flags);
++	if (!buf) {
++		DHD_ERROR(("%s: prio work fifo allocation failed \n", __FUNCTION__));
++		goto return_null;
++	}
++
++	/* Initialize prio event fifo */
++	work->prio_fifo = dhd_kfifo_init(buf, fifo_size, &work->work_lock);
++	if (!work->prio_fifo) {
++		kfree(buf);
++		goto return_null;
++	}
++
++	/* allocate buffer to hold work events */
++	fifo_size = DHD_WORK_FIFO_SIZE;
++	fifo_size = is_power_of_2(fifo_size)? fifo_size : roundup_pow_of_two(fifo_size);
++	buf = (u8*)kzalloc(fifo_size, flags);
++	if (!buf) {
++		DHD_ERROR(("%s: work fifo allocation failed \n", __FUNCTION__));
++		goto return_null;
++	}
++
++	/* Initialize event fifo */
++	work->work_fifo = dhd_kfifo_init(buf, fifo_size, &work->work_lock);
++	if (!work->work_fifo) {
++		kfree(buf);
++		goto return_null;
++	}
++
++	work->dhd_info = dhd_info;
++	DHD_ERROR(("%s: work queue initialized \n", __FUNCTION__));
++	return work;
++
++return_null:
++
++	if (work)
++		dhd_deferred_work_deinit(work);
++
++	return NULL;
++}
++
++void
++dhd_deferred_work_deinit(void *work)
++{
++	struct dhd_deferred_wq *deferred_work = work;
++
++
++	if (!deferred_work) {
++		DHD_ERROR(("%s: deferred work has been freed alread \n", __FUNCTION__));
++		return;
++	}
++
++	/* cancel the deferred work handling */
++	cancel_work_sync((struct work_struct *)deferred_work);
++
++	/*
++	 * free work event fifo.
++	 * kfifo_free frees locally allocated fifo buffer
++	 */
++	if (deferred_work->prio_fifo)
++		dhd_kfifo_free(deferred_work->prio_fifo);
++
++	if (deferred_work->work_fifo)
++		dhd_kfifo_free(deferred_work->work_fifo);
++
++	kfree(deferred_work);
++}
++
++/*
++ *	Prepares event to be queued
++ *	Schedules the event
++ */
++int
++dhd_deferred_schedule_work(void *workq, void *event_data, u8 event,
++	event_handler_t event_handler, u8 priority)
++{
++	struct dhd_deferred_wq *deferred_wq = (struct dhd_deferred_wq *) workq;
++	struct	dhd_deferred_event_t	deferred_event;
++	int	status;
++
++	if (!deferred_wq) {
++		DHD_ERROR(("%s: work queue not initialized \n", __FUNCTION__));
++		ASSERT(0);
++		return DHD_WQ_STS_UNINITIALIZED;
++	}
++
++	if (!event || (event >= DHD_MAX_WQ_EVENTS)) {
++		DHD_ERROR(("%s: Unknown event \n", __FUNCTION__));
++		return DHD_WQ_STS_UNKNOWN_EVENT;
++	}
++
++	/*
++	 * default element size is 1, which can be changed
++	 * using kfifo_esize(). Older kernel(FC11) doesn't support
++	 * changing element size. For compatibility changing
++	 * element size is not prefered
++	 */
++	ASSERT(kfifo_esize(deferred_wq->prio_fifo) == 1);
++	ASSERT(kfifo_esize(deferred_wq->work_fifo) == 1);
++
++	deferred_event.event = event;
++	deferred_event.event_data = event_data;
++	deferred_event.event_handler = event_handler;
++
++	if (priority == DHD_WORK_PRIORITY_HIGH) {
++		status = kfifo_in_spinlocked(deferred_wq->prio_fifo, &deferred_event,
++			DEFRD_EVT_SIZE, &deferred_wq->work_lock);
++	} else {
++		status = kfifo_in_spinlocked(deferred_wq->work_fifo, &deferred_event,
++			DEFRD_EVT_SIZE, &deferred_wq->work_lock);
++	}
++
++	if (!status) {
++		return DHD_WQ_STS_SCHED_FAILED;
++	}
++	schedule_work((struct work_struct *)deferred_wq);
++	return DHD_WQ_STS_OK;
++}
++
++static int
++dhd_get_scheduled_work(struct dhd_deferred_wq *deferred_wq, struct dhd_deferred_event_t *event)
++{
++	int	status = 0;
++
++	if (!deferred_wq) {
++		DHD_ERROR(("%s: work queue not initialized \n", __FUNCTION__));
++		return DHD_WQ_STS_UNINITIALIZED;
++	}
++
++	/*
++	 * default element size is 1 byte, which can be changed
++	 * using kfifo_esize(). Older kernel(FC11) doesn't support
++	 * changing element size. For compatibility changing
++	 * element size is not prefered
++	 */
++	ASSERT(kfifo_esize(deferred_wq->prio_fifo) == 1);
++	ASSERT(kfifo_esize(deferred_wq->work_fifo) == 1);
++
++	/* first read  priorit event fifo */
++	status = kfifo_out_spinlocked(deferred_wq->prio_fifo, event,
++		DEFRD_EVT_SIZE, &deferred_wq->work_lock);
++
++	if (!status) {
++		/* priority fifo is empty. Now read low prio work fifo */
++		status = kfifo_out_spinlocked(deferred_wq->work_fifo, event,
++			DEFRD_EVT_SIZE, &deferred_wq->work_lock);
++	}
++
++	return status;
++}
++
++/*
++ *	Called when work is scheduled
++ */
++static void
++dhd_deferred_work_handler(struct work_struct *work)
++{
++	struct dhd_deferred_wq		*deferred_work = (struct dhd_deferred_wq *)work;
++	struct dhd_deferred_event_t	work_event;
++	int				status;
++
++	if (!deferred_work) {
++		DHD_ERROR(("%s: work queue not initialized\n", __FUNCTION__));
++		return;
++	}
++
++	do {
++		status = dhd_get_scheduled_work(deferred_work, &work_event);
++		DHD_TRACE(("%s: event to handle %d \n", __FUNCTION__, status));
++		if (!status) {
++			DHD_TRACE(("%s: No event to handle %d \n", __FUNCTION__, status));
++			break;
++		}
++
++		if (work_event.event > DHD_MAX_WQ_EVENTS) {
++			DHD_TRACE(("%s: Unknown event %d \n", __FUNCTION__, work_event.event));
++			break;
++		}
++
++		if (work_event.event_handler) {
++			work_event.event_handler(deferred_work->dhd_info,
++				work_event.event_data, work_event.event);
++		} else {
++			DHD_ERROR(("%s: event not defined %d\n", __FUNCTION__, work_event.event));
++		}
++	} while (1);
++	return;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux_wq.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux_wq.h
+new file mode 100644
+index 000000000..ab8f0e24d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_linux_wq.h
+@@ -0,0 +1,69 @@
++/*
++ * Broadcom Dongle Host Driver (DHD), Generic work queue framework
++ * Generic interface to handle dhd deferred work events
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_linux_wq.h 606703 2015-12-16 12:22:50Z $
++ */
++#ifndef _dhd_linux_wq_h_
++#define _dhd_linux_wq_h_
++/*
++ *	Work event definitions
++ */
++enum _wq_event {
++	DHD_WQ_WORK_IF_ADD = 1,
++	DHD_WQ_WORK_IF_DEL,
++	DHD_WQ_WORK_SET_MAC,
++	DHD_WQ_WORK_SET_MCAST_LIST,
++	DHD_WQ_WORK_IPV6_NDO,
++	DHD_WQ_WORK_HANG_MSG,
++	DHD_WQ_WORK_SOC_RAM_DUMP,
++	DHD_WQ_WORK_INFORM_DHD_MON,
++
++	DHD_MAX_WQ_EVENTS
++};
++
++/*
++ *	Work event priority
++ */
++#define DHD_WORK_PRIORITY_LOW	0
++#define DHD_WORK_PRIORITY_HIGH	1
++
++/*
++ *	Error definitions
++ */
++#define DHD_WQ_STS_OK			 0
++#define DHD_WQ_STS_FAILED		-1	/* General failure */
++#define DHD_WQ_STS_UNINITIALIZED	-2
++#define DHD_WQ_STS_SCHED_FAILED		-3
++#define DHD_WQ_STS_UNKNOWN_EVENT	-4
++
++typedef void (*event_handler_t)(void *handle, void *event_data, u8 event);
++
++void *dhd_deferred_work_init(void *dhd);
++void dhd_deferred_work_deinit(void *workq);
++int dhd_deferred_schedule_work(void *workq, void *event_data, u8 event,
++	event_handler_t evt_handler, u8 priority);
++#endif /* _dhd_linux_wq_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_msgbuf.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_msgbuf.c
+new file mode 100644
+index 000000000..cc983ed5e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_msgbuf.c
+@@ -0,0 +1,6332 @@
++/**
++ * @file definition of host message ring functionality
++ * Provides type definitions and function prototypes used to link the
++ * DHD OS, bus, and protocol modules.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_msgbuf.c 608659 2015-12-29 01:18:33Z $
++ */
++
++
++#include <typedefs.h>
++#include <osl.h>
++
++#include <bcmutils.h>
++#include <bcmmsgbuf.h>
++#include <bcmendian.h>
++
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_proto.h>
++
++#ifdef BCMDBUS
++#include <dbus.h>
++#else
++#include <dhd_bus.h>
++#endif /* BCMDBUS */
++
++#include <dhd_dbg.h>
++#include <siutils.h>
++
++
++#include <dhd_flowring.h>
++
++#include <pcie_core.h>
++#include <bcmpcie.h>
++#include <dhd_pcie.h>
++
++#if defined(DHD_LB)
++#include <linux/cpu.h>
++#include <bcm_ring.h>
++#define DHD_LB_WORKQ_SZ                            (8192)
++#define DHD_LB_WORKQ_SYNC           (16)
++#define DHD_LB_WORK_SCHED           (DHD_LB_WORKQ_SYNC * 2)
++#endif /* DHD_LB */
++
++
++/**
++ * Host configures a soft doorbell for d2h rings, by specifying a 32bit host
++ * address where a value must be written. Host may also interrupt coalescing
++ * on this soft doorbell.
++ * Use Case: Hosts with network processors, may register with the dongle the
++ * network processor's thread wakeup register and a value corresponding to the
++ * core/thread context. Dongle will issue a write transaction <address,value>
++ * to the PCIE RC which will need to be routed to the mapped register space, by
++ * the host.
++ */
++/* #define DHD_D2H_SOFT_DOORBELL_SUPPORT */
++
++/* Dependency Check */
++#if defined(IOCTLRESP_USE_CONSTMEM) && defined(DHD_USE_STATIC_CTRLBUF)
++#error "DHD_USE_STATIC_CTRLBUF is NOT working with DHD_USE_OSLPKT_FOR_RESPBUF"
++#endif /* IOCTLRESP_USE_CONSTMEM && DHD_USE_STATIC_CTRLBUF */
++
++#define RETRIES 2		/* # of retries to retrieve matching ioctl response */
++
++#define DEFAULT_RX_BUFFERS_TO_POST	256
++#define RXBUFPOST_THRESHOLD			32
++#define RX_BUF_BURST				32 /* Rx buffers for MSDU Data */
++
++#define DHD_STOP_QUEUE_THRESHOLD	200
++#define DHD_START_QUEUE_THRESHOLD	100
++
++#define RX_DMA_OFFSET		8 /* Mem2mem DMA inserts an extra 8 */
++#define IOCT_RETBUF_SIZE	(RX_DMA_OFFSET + WLC_IOCTL_MAXLEN)
++#define FLOWRING_SIZE		(H2DRING_TXPOST_MAX_ITEM * H2DRING_TXPOST_ITEMSIZE)
++
++/* flags for ioctl pending status */
++#define MSGBUF_IOCTL_ACK_PENDING	(1<<0)
++#define MSGBUF_IOCTL_RESP_PENDING	(1<<1)
++
++#define DMA_ALIGN_LEN		4
++
++#define DMA_D2H_SCRATCH_BUF_LEN	8
++#define DMA_XFER_LEN_LIMIT	0x400000
++
++#ifdef BCM_HOST_BUF
++#ifndef DMA_HOST_BUFFER_LEN
++#define DMA_HOST_BUFFER_LEN	0x80000
++#endif
++#endif /* BCM_HOST_BUF */
++
++#define DHD_FLOWRING_IOCTL_BUFPOST_PKTSZ		8192
++
++#define DHD_FLOWRING_MAX_EVENTBUF_POST			8
++#define DHD_FLOWRING_MAX_IOCTLRESPBUF_POST		8
++
++#define DHD_PROT_FUNCS	37
++
++/* Length of buffer in host for bus throughput measurement */
++#define DHD_BUS_TPUT_BUF_LEN 2048
++
++#define TXP_FLUSH_NITEMS
++
++/* optimization to write "n" tx items at a time to ring */
++#define TXP_FLUSH_MAX_ITEMS_FLUSH_CNT	48
++
++#define RING_NAME_MAX_LENGTH		24
++
++
++struct msgbuf_ring; /* ring context for common and flow rings */
++
++/**
++ * PCIE D2H DMA Complete Sync Modes
++ *
++ * Firmware may interrupt the host, prior to the D2H Mem2Mem DMA completes into
++ * Host system memory. A WAR using one of 3 approaches is needed:
++ * 1. Dongle places a modulo-253 seqnum in last word of each D2H message
++ * 2. XOR Checksum, with epoch# in each work item. Dongle builds an XOR checksum
++ *    writes in the last word of each work item. Each work item has a seqnum
++ *    number = sequence num % 253.
++ *
++ * 3. Read Barrier: Dongle does a host memory read access prior to posting an
++ *    interrupt, ensuring that D2H data transfer indeed completed.
++ * 4. Dongle DMA's all indices after producing items in the D2H ring, flushing
++ *    ring contents before the indices.
++ *
++ * Host does not sync for DMA to complete with option #3 or #4, and a noop sync
++ * callback (see dhd_prot_d2h_sync_none) may be bound.
++ *
++ * Dongle advertizes host side sync mechanism requirements.
++ */
++#define PCIE_D2H_SYNC
++
++#if defined(PCIE_D2H_SYNC)
++#define PCIE_D2H_SYNC_WAIT_TRIES    512
++
++/**
++ * Custom callback attached based upon D2H DMA Sync mode advertized by dongle.
++ *
++ * On success: return cmn_msg_hdr_t::msg_type
++ * On failure: return 0 (invalid msg_type)
++ */
++typedef uint8 (* d2h_sync_cb_t)(dhd_pub_t *dhd, struct msgbuf_ring *ring,
++                                volatile cmn_msg_hdr_t *msg, int msglen);
++#endif /* PCIE_D2H_SYNC */
++
++
++/*
++ * +----------------------------------------------------------------------------
++ *
++ * RingIds and FlowId are not equivalent as ringids include D2H rings whereas
++ * flowids do not.
++ *
++ * Dongle advertizes the max H2D rings, as max_sub_queues = 'N' which includes
++ * the H2D common rings as well as the (N-BCMPCIE_H2D_COMMON_MSGRINGS) flowrings
++ *
++ * Here is a sample mapping for (based on PCIE Full Dongle Rev5) where,
++ *  BCMPCIE_H2D_COMMON_MSGRINGS = 2, i.e. 2 H2D common rings,
++ *  BCMPCIE_COMMON_MSGRINGS     = 5, i.e. include 3 D2H common rings.
++ *
++ *  H2D Control  Submit   RingId = 0        FlowId = 0 reserved never allocated
++ *  H2D RxPost   Submit   RingId = 1        FlowId = 1 reserved never allocated
++ *
++ *  D2H Control  Complete RingId = 2
++ *  D2H Transmit Complete RingId = 3
++ *  D2H Receive  Complete RingId = 4
++ *
++ *  H2D TxPost   FLOWRING RingId = 5         FlowId = 2     (1st flowring)
++ *  H2D TxPost   FLOWRING RingId = 6         FlowId = 3     (2nd flowring)
++ *  H2D TxPost   FLOWRING RingId = 5 + (N-1) FlowId = (N-1) (Nth flowring)
++ *
++ * When TxPost FlowId(s) are allocated, the FlowIds [0..FLOWID_RESERVED) are
++ * unused, where FLOWID_RESERVED is BCMPCIE_H2D_COMMON_MSGRINGS.
++ *
++ * Example: when a system supports 4 bc/mc and 128 uc flowrings, with
++ * BCMPCIE_H2D_COMMON_MSGRINGS = 2, and BCMPCIE_H2D_COMMON_MSGRINGS = 5, and the
++ * FlowId values would be in the range [2..133] and the corresponding
++ * RingId values would be in the range [5..136].
++ *
++ * The flowId allocator, may chose to, allocate Flowids:
++ *   bc/mc (per virtual interface) in one consecutive range [2..(2+VIFS))
++ *   X# of uc flowids in consecutive ranges (per station Id), where X is the
++ *   packet's access category (e.g. 4 uc flowids per station).
++ *
++ * CAUTION:
++ * When DMA indices array feature is used, RingId=5, corresponding to the 0th
++ * FLOWRING, will actually use the FlowId as index into the H2D DMA index,
++ * since the FlowId truly represents the index in the H2D DMA indices array.
++ *
++ * Likewise, in the D2H direction, the RingId - BCMPCIE_H2D_COMMON_MSGRINGS,
++ * will represent the index in the D2H DMA indices array.
++ *
++ * +----------------------------------------------------------------------------
++ */
++
++/* First TxPost Flowring Id */
++#define DHD_FLOWRING_START_FLOWID   BCMPCIE_H2D_COMMON_MSGRINGS
++
++/* Determine whether a ringid belongs to a TxPost flowring */
++#define DHD_IS_FLOWRING(ringid) \
++	((ringid) >= BCMPCIE_COMMON_MSGRINGS)
++
++/* Convert a H2D TxPost FlowId to a MsgBuf RingId */
++#define DHD_FLOWID_TO_RINGID(flowid) \
++	(BCMPCIE_COMMON_MSGRINGS + ((flowid) - BCMPCIE_H2D_COMMON_MSGRINGS))
++
++/* Convert a MsgBuf RingId to a H2D TxPost FlowId */
++#define DHD_RINGID_TO_FLOWID(ringid) \
++	(BCMPCIE_H2D_COMMON_MSGRINGS + ((ringid) - BCMPCIE_COMMON_MSGRINGS))
++
++/* Convert a H2D MsgBuf RingId to an offset index into the H2D DMA indices array
++ * This may be used for the H2D DMA WR index array or H2D DMA RD index array or
++ * any array of H2D rings.
++ */
++#define DHD_H2D_RING_OFFSET(ringid) \
++	((DHD_IS_FLOWRING(ringid)) ? DHD_RINGID_TO_FLOWID(ringid) : (ringid))
++
++/* Convert a D2H MsgBuf RingId to an offset index into the D2H DMA indices array
++ * This may be used for the D2H DMA WR index array or D2H DMA RD index array or
++ * any array of D2H rings.
++ */
++#define DHD_D2H_RING_OFFSET(ringid) \
++	((ringid) - BCMPCIE_H2D_COMMON_MSGRINGS)
++
++/* Convert a D2H DMA Indices Offset to a RingId */
++#define DHD_D2H_RINGID(offset) \
++	((offset) + BCMPCIE_H2D_COMMON_MSGRINGS)
++
++
++#define DHD_DMAH_NULL      ((void*)NULL)
++
++/*
++ * Pad a DMA-able buffer by an additional cachline. If the end of the DMA-able
++ * buffer does not occupy the entire cacheline, and another object is placed
++ * following the DMA-able buffer, data corruption may occur if the DMA-able
++ * buffer is used to DMAing into (e.g. D2H direction), when HW cache coherency
++ * is not available.
++ */
++#if defined(L1_CACHE_BYTES)
++#define DHD_DMA_PAD        (L1_CACHE_BYTES)
++#else
++#define DHD_DMA_PAD        (128)
++#endif
++
++/* Used in loopback tests */
++typedef struct dhd_dmaxfer {
++	dhd_dma_buf_t srcmem;
++	dhd_dma_buf_t dstmem;
++	uint32        srcdelay;
++	uint32        destdelay;
++	uint32        len;
++	bool          in_progress;
++} dhd_dmaxfer_t;
++
++/**
++ * msgbuf_ring : This object manages the host side ring that includes a DMA-able
++ * buffer, the WR and RD indices, ring parameters such as max number of items
++ * an length of each items, and other miscellaneous runtime state.
++ * A msgbuf_ring may be used to represent a H2D or D2H common ring or a
++ * H2D TxPost ring as specified in the PCIE FullDongle Spec.
++ * Ring parameters are conveyed to the dongle, which maintains its own peer end
++ * ring state. Depending on whether the DMA Indices feature is supported, the
++ * host will update the WR/RD index in the DMA indices array in host memory or
++ * directly in dongle memory.
++ */
++typedef struct msgbuf_ring {
++	bool           inited;
++	uint16         idx;       /* ring id */
++	uint16         rd;        /* read index */
++	uint16         wr;        /* write index */
++	uint16         max_items; /* maximum number of items in ring */
++	uint16         item_len;  /* length of each item in the ring */
++	sh_addr_t      base_addr; /* LITTLE ENDIAN formatted: base address */
++	dhd_dma_buf_t  dma_buf;   /* DMA-able buffer: pa, va, len, dmah, secdma */
++	uint32         seqnum;    /* next expected item's sequence number */
++#ifdef TXP_FLUSH_NITEMS
++	void           *start_addr;
++	/* # of messages on ring not yet announced to dongle */
++	uint16         pend_items_count;
++#endif /* TXP_FLUSH_NITEMS */
++	uchar		name[RING_NAME_MAX_LENGTH];
++} msgbuf_ring_t;
++
++#define DHD_RING_BGN_VA(ring)           ((ring)->dma_buf.va)
++#define DHD_RING_END_VA(ring) \
++	((uint8 *)(DHD_RING_BGN_VA((ring))) + \
++	 (((ring)->max_items - 1) * (ring)->item_len))
++
++
++
++/** DHD protocol handle. Is an opaque type to other DHD software layers. */
++typedef struct dhd_prot {
++	osl_t *osh;		/* OSL handle */
++	uint16 rxbufpost;
++	uint16 max_rxbufpost;
++	uint16 max_eventbufpost;
++	uint16 max_ioctlrespbufpost;
++	uint16 cur_event_bufs_posted;
++	uint16 cur_ioctlresp_bufs_posted;
++
++	/* Flow control mechanism based on active transmits pending */
++	uint16 active_tx_count; /* increments on every packet tx, and decrements on tx_status */
++	uint16 max_tx_count;
++	uint16 txp_threshold;  /* optimization to write "n" tx items at a time to ring */
++
++	/* MsgBuf Ring info: has a dhd_dma_buf that is dynamically allocated */
++	msgbuf_ring_t h2dring_ctrl_subn; /* H2D ctrl message submission ring */
++	msgbuf_ring_t h2dring_rxp_subn; /* H2D RxBuf post ring */
++	msgbuf_ring_t d2hring_ctrl_cpln; /* D2H ctrl completion ring */
++	msgbuf_ring_t d2hring_tx_cpln; /* D2H Tx complete message ring */
++	msgbuf_ring_t d2hring_rx_cpln; /* D2H Rx complete message ring */
++
++	msgbuf_ring_t *h2d_flowrings_pool; /* Pool of preallocated flowings */
++	dhd_dma_buf_t flowrings_dma_buf; /* Contiguous DMA buffer for flowrings */
++	uint16        h2d_rings_total; /* total H2D (common rings + flowrings) */
++
++	uint32		rx_dataoffset;
++
++	dhd_mb_ring_t	mb_ring_fn;	/* called when dongle needs to be notified of new msg */
++
++	/* ioctl related resources */
++	uint8 ioctl_state;
++	int16 ioctl_status;		/* status returned from dongle */
++	uint16 ioctl_resplen;
++	dhd_ioctl_recieved_status_t ioctl_received;
++	uint curr_ioctl_cmd;
++	dhd_dma_buf_t	retbuf;		/* For holding ioctl response */
++	dhd_dma_buf_t	ioctbuf;	/* For holding ioctl request */
++
++	dhd_dma_buf_t	d2h_dma_scratch_buf;	/* For holding d2h scratch */
++
++	/* DMA-able arrays for holding WR and RD indices */
++	uint32          rw_index_sz; /* Size of a RD or WR index in dongle */
++	dhd_dma_buf_t   h2d_dma_indx_wr_buf;	/* Array of H2D WR indices */
++	dhd_dma_buf_t	h2d_dma_indx_rd_buf;	/* Array of H2D RD indices */
++	dhd_dma_buf_t	d2h_dma_indx_wr_buf;	/* Array of D2H WR indices */
++	dhd_dma_buf_t	d2h_dma_indx_rd_buf;	/* Array of D2H RD indices */
++
++	dhd_dma_buf_t	host_bus_throughput_buf; /* bus throughput measure buffer */
++
++	dhd_dma_buf_t   *flowring_buf;    /* pool of flow ring buf */
++	uint32			flowring_num;
++
++#if defined(PCIE_D2H_SYNC)
++	d2h_sync_cb_t d2h_sync_cb; /* Sync on D2H DMA done: SEQNUM or XORCSUM */
++	ulong d2h_sync_wait_max; /* max number of wait loops to receive one msg */
++	ulong d2h_sync_wait_tot; /* total wait loops */
++#endif  /* PCIE_D2H_SYNC */
++
++	dhd_dmaxfer_t	dmaxfer; /* for test/DMA loopback */
++
++	uint16		ioctl_seq_no;
++	uint16		data_seq_no;
++	uint16		ioctl_trans_id;
++	void		*pktid_map_handle; /* a pktid maps to a packet and its metadata */
++	bool		metadata_dbg;
++	void		*pktid_map_handle_ioctl;
++
++	/* Applications/utilities can read tx and rx metadata using IOVARs */
++	uint16		rx_metadata_offset;
++	uint16		tx_metadata_offset;
++
++
++#if defined(DHD_D2H_SOFT_DOORBELL_SUPPORT)
++	/* Host's soft doorbell configuration */
++	bcmpcie_soft_doorbell_t soft_doorbell[BCMPCIE_D2H_COMMON_MSGRINGS];
++#endif /* DHD_D2H_SOFT_DOORBELL_SUPPORT */
++#if defined(DHD_LB)
++	/* Work Queues to be used by the producer and the consumer, and threshold
++	 * when the WRITE index must be synced to consumer's workq
++	 */
++#if defined(DHD_LB_TXC)
++	uint32 tx_compl_prod_sync ____cacheline_aligned;
++	bcm_workq_t tx_compl_prod, tx_compl_cons;
++#endif /* DHD_LB_TXC */
++#if defined(DHD_LB_RXC)
++	uint32 rx_compl_prod_sync ____cacheline_aligned;
++	bcm_workq_t rx_compl_prod, rx_compl_cons;
++#endif /* DHD_LB_RXC */
++#endif /* DHD_LB */
++} dhd_prot_t;
++
++/* Convert a dmaaddr_t to a base_addr with htol operations */
++static INLINE void dhd_base_addr_htolpa(sh_addr_t *base_addr, dmaaddr_t pa);
++
++/* APIs for managing a DMA-able buffer */
++static int  dhd_dma_buf_audit(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf);
++static int  dhd_dma_buf_alloc(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf, uint32 buf_len);
++static void dhd_dma_buf_reset(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf);
++static void dhd_dma_buf_free(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf);
++
++/* msgbuf ring management */
++static int dhd_prot_ring_attach(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++	const char *name, uint16 max_items, uint16 len_item, uint16 ringid);
++static void dhd_prot_ring_init(dhd_pub_t *dhd, msgbuf_ring_t *ring);
++static void dhd_prot_ring_reset(dhd_pub_t *dhd, msgbuf_ring_t *ring);
++static void dhd_prot_ring_detach(dhd_pub_t *dhd, msgbuf_ring_t *ring);
++
++/* Pool of pre-allocated msgbuf_ring_t with DMA-able buffers for Flowrings */
++static int  dhd_prot_flowrings_pool_attach(dhd_pub_t *dhd);
++static void dhd_prot_flowrings_pool_reset(dhd_pub_t *dhd);
++static void dhd_prot_flowrings_pool_detach(dhd_pub_t *dhd);
++
++/* Fetch and Release a flowring msgbuf_ring from flowring  pool */
++static msgbuf_ring_t *dhd_prot_flowrings_pool_fetch(dhd_pub_t *dhd,
++	uint16 flowid);
++/* see also dhd_prot_flowrings_pool_release() in dhd_prot.h */
++
++/* Producer: Allocate space in a msgbuf ring */
++static void* dhd_prot_alloc_ring_space(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++	uint16 nitems, uint16 *alloced, bool exactly_nitems);
++static void* dhd_prot_get_ring_space(msgbuf_ring_t *ring, uint16 nitems,
++	uint16 *alloced, bool exactly_nitems);
++
++/* Consumer: Determine the location where the next message may be consumed */
++static uint8* dhd_prot_get_read_addr(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++	uint32 *available_len);
++
++/* Producer (WR index update) or Consumer (RD index update) indication */
++static void dhd_prot_ring_write_complete(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++	void *p, uint16 len);
++static void dhd_prot_upd_read_idx(dhd_pub_t *dhd, msgbuf_ring_t *ring);
++
++/* Allocate DMA-able memory for saving H2D/D2H WR/RD indices */
++static INLINE int dhd_prot_dma_indx_alloc(dhd_pub_t *dhd, uint8 type,
++	dhd_dma_buf_t *dma_buf, uint32 bufsz);
++
++/* Set/Get a RD or WR index in the array of indices */
++/* See also: dhd_prot_dma_indx_init() */
++static void dhd_prot_dma_indx_set(dhd_pub_t *dhd, uint16 new_index, uint8 type,
++	uint16 ringid);
++static uint16 dhd_prot_dma_indx_get(dhd_pub_t *dhd, uint8 type, uint16 ringid);
++
++/* Locate a packet given a pktid */
++static INLINE void *dhd_prot_packet_get(dhd_pub_t *dhd, uint32 pktid, uint8 pkttype,
++	bool free_pktid);
++/* Locate a packet given a PktId and free it. */
++static INLINE void dhd_prot_packet_free(dhd_pub_t *dhd, void *pkt, uint8 pkttype, bool send);
++
++static int dhd_msgbuf_query_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd,
++	void *buf, uint len, uint8 action);
++static int dhd_msgbuf_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd,
++	void *buf, uint len, uint8 action);
++static int dhd_msgbuf_wait_ioctl_cmplt(dhd_pub_t *dhd, uint32 len, void *buf);
++static int dhd_fillup_ioct_reqst(dhd_pub_t *dhd, uint16 len, uint cmd,
++	void *buf, int ifidx);
++
++/* Post buffers for Rx, control ioctl response and events */
++static uint16 dhd_msgbuf_rxbuf_post_ctrlpath(dhd_pub_t *dhd, bool event_buf, uint32 max_to_post);
++static void dhd_msgbuf_rxbuf_post_ioctlresp_bufs(dhd_pub_t *pub);
++static void dhd_msgbuf_rxbuf_post_event_bufs(dhd_pub_t *pub);
++static void dhd_msgbuf_rxbuf_post(dhd_pub_t *dhd, bool use_rsv_pktid);
++static int dhd_prot_rxbuf_post(dhd_pub_t *dhd, uint16 count, bool use_rsv_pktid);
++
++static void dhd_prot_return_rxbuf(dhd_pub_t *dhd, uint32 pktid, uint32 rxcnt);
++
++/* D2H Message handling */
++static int dhd_prot_process_msgtype(dhd_pub_t *dhd, msgbuf_ring_t *ring, uint8 *buf, uint32 len);
++
++/* D2H Message handlers */
++static void dhd_prot_noop(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_txstatus_process(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_ioctcmplt_process(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_ioctack_process(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_ringstatus_process(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_genstatus_process(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_rxcmplt_process(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_event_process(dhd_pub_t *dhd, void *msg);
++
++/* Loopback test with dongle */
++static void dmaxfer_free_dmaaddr(dhd_pub_t *dhd, dhd_dmaxfer_t *dma);
++static int dmaxfer_prepare_dmaaddr(dhd_pub_t *dhd, uint len, uint srcdelay,
++	uint destdelay, dhd_dmaxfer_t *dma);
++static void dhd_msgbuf_dmaxfer_process(dhd_pub_t *dhd, void *msg);
++
++/* Flowring management communication with dongle */
++static void dhd_prot_flow_ring_create_response_process(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_flow_ring_delete_response_process(dhd_pub_t *dhd, void *msg);
++static void dhd_prot_flow_ring_flush_response_process(dhd_pub_t *dhd, void *msg);
++
++/* Configure a soft doorbell per D2H ring */
++static void dhd_msgbuf_ring_config_d2h_soft_doorbell(dhd_pub_t *dhd);
++static void dhd_prot_d2h_ring_config_cmplt_process(dhd_pub_t *dhd, void *msg);
++
++typedef void (*dhd_msgbuf_func_t)(dhd_pub_t *dhd, void *msg);
++
++/** callback functions for messages generated by the dongle */
++#define MSG_TYPE_INVALID 0
++
++static dhd_msgbuf_func_t table_lookup[DHD_PROT_FUNCS] = {
++	dhd_prot_noop, /* 0 is MSG_TYPE_INVALID */
++	dhd_prot_genstatus_process, /* MSG_TYPE_GEN_STATUS */
++	dhd_prot_ringstatus_process, /* MSG_TYPE_RING_STATUS */
++	NULL,
++	dhd_prot_flow_ring_create_response_process, /* MSG_TYPE_FLOW_RING_CREATE_CMPLT */
++	NULL,
++	dhd_prot_flow_ring_delete_response_process, /* MSG_TYPE_FLOW_RING_DELETE_CMPLT */
++	NULL,
++	dhd_prot_flow_ring_flush_response_process, /* MSG_TYPE_FLOW_RING_FLUSH_CMPLT */
++	NULL,
++	dhd_prot_ioctack_process, /* MSG_TYPE_IOCTLPTR_REQ_ACK */
++	NULL,
++	dhd_prot_ioctcmplt_process, /* MSG_TYPE_IOCTL_CMPLT */
++	NULL,
++	dhd_prot_event_process, /* MSG_TYPE_WL_EVENT */
++	NULL,
++	dhd_prot_txstatus_process, /* MSG_TYPE_TX_STATUS */
++	NULL,
++	dhd_prot_rxcmplt_process, /* MSG_TYPE_RX_CMPLT */
++	NULL,
++	dhd_msgbuf_dmaxfer_process, /* MSG_TYPE_LPBK_DMAXFER_CMPLT */
++	NULL, /* MSG_TYPE_FLOW_RING_RESUME */
++	NULL, /* MSG_TYPE_FLOW_RING_RESUME_CMPLT */
++	NULL, /* MSG_TYPE_FLOW_RING_SUSPEND */
++	NULL, /* MSG_TYPE_FLOW_RING_SUSPEND_CMPLT */
++	NULL, /* MSG_TYPE_INFO_BUF_POST */
++	NULL, /* MSG_TYPE_INFO_BUF_CMPLT */
++	NULL, /* MSG_TYPE_H2D_RING_CREATE */
++	NULL, /* MSG_TYPE_D2H_RING_CREATE */
++	NULL, /* MSG_TYPE_H2D_RING_CREATE_CMPLT */
++	NULL, /* MSG_TYPE_D2H_RING_CREATE_CMPLT */
++	NULL, /* MSG_TYPE_H2D_RING_CONFIG */
++	NULL, /* MSG_TYPE_D2H_RING_CONFIG */
++	NULL, /* MSG_TYPE_H2D_RING_CONFIG_CMPLT */
++	dhd_prot_d2h_ring_config_cmplt_process, /* MSG_TYPE_D2H_RING_CONFIG_CMPLT */
++	NULL, /* MSG_TYPE_H2D_MAILBOX_DATA */
++	NULL, /* MSG_TYPE_D2H_MAILBOX_DATA */
++};
++
++
++#ifdef DHD_RX_CHAINING
++
++#define PKT_CTF_CHAINABLE(dhd, ifidx, evh, prio, h_sa, h_da, h_prio) \
++	(dhd_rx_pkt_chainable((dhd), (ifidx)) && \
++	!ETHER_ISNULLDEST(((struct ether_header *)(evh))->ether_dhost) && \
++	!ETHER_ISMULTI(((struct ether_header *)(evh))->ether_dhost) && \
++	!eacmp((h_da), ((struct ether_header *)(evh))->ether_dhost) && \
++	!eacmp((h_sa), ((struct ether_header *)(evh))->ether_shost) && \
++	((h_prio) == (prio)) && (dhd_ctf_hotbrc_check((dhd), (evh), (ifidx))) && \
++	((((struct ether_header *)(evh))->ether_type == HTON16(ETHER_TYPE_IP)) || \
++	(((struct ether_header *)(evh))->ether_type == HTON16(ETHER_TYPE_IPV6))))
++
++static INLINE void BCMFASTPATH dhd_rxchain_reset(rxchain_info_t *rxchain);
++static void BCMFASTPATH dhd_rxchain_frame(dhd_pub_t *dhd, void *pkt, uint ifidx);
++static void BCMFASTPATH dhd_rxchain_commit(dhd_pub_t *dhd);
++
++#define DHD_PKT_CTF_MAX_CHAIN_LEN	64
++
++#endif /* DHD_RX_CHAINING */
++
++static void dhd_prot_h2d_sync_init(dhd_pub_t *dhd);
++
++#if defined(PCIE_D2H_SYNC) /* avoids problems related to host CPU cache */
++
++/**
++ * D2H DMA to completion callback handlers. Based on the mode advertised by the
++ * dongle through the PCIE shared region, the appropriate callback will be
++ * registered in the proto layer to be invoked prior to precessing any message
++ * from a D2H DMA ring. If the dongle uses a read barrier or another mode that
++ * does not require host participation, then a noop callback handler will be
++ * bound that simply returns the msg_type.
++ */
++static void dhd_prot_d2h_sync_livelock(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++                                       uint32 tries, uchar *msg, int msglen);
++static uint8 dhd_prot_d2h_sync_seqnum(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++                                      volatile cmn_msg_hdr_t *msg, int msglen);
++static uint8 dhd_prot_d2h_sync_xorcsum(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++                                       volatile cmn_msg_hdr_t *msg, int msglen);
++static uint8 dhd_prot_d2h_sync_none(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++                                    volatile cmn_msg_hdr_t *msg, int msglen);
++static void dhd_prot_d2h_sync_init(dhd_pub_t *dhd);
++
++/**
++ * dhd_prot_d2h_sync_livelock - when the host determines that a DMA transfer has
++ * not completed, a livelock condition occurs. Host will avert this livelock by
++ * dropping this message and moving to the next. This dropped message can lead
++ * to a packet leak, or even something disastrous in the case the dropped
++ * message happens to be a control response.
++ * Here we will log this condition. One may choose to reboot the dongle.
++ *
++ */
++static void
++dhd_prot_d2h_sync_livelock(dhd_pub_t *dhd, msgbuf_ring_t *ring, uint32 tries,
++                           uchar *msg, int msglen)
++{
++	uint32 seqnum = ring->seqnum;
++
++	DHD_ERROR(("LIVELOCK DHD<%p> seqnum<%u:%u> tries<%u> max<%lu> tot<%lu>"
++		"dma_buf va<%p> msg<%p>\n",
++		dhd, seqnum, seqnum% D2H_EPOCH_MODULO, tries,
++		dhd->prot->d2h_sync_wait_max, dhd->prot->d2h_sync_wait_tot,
++		ring->dma_buf.va, msg));
++	prhex("D2H MsgBuf Failure", (uchar *)msg, msglen);
++
++#if defined(SUPPORT_LINKDOWN_RECOVERY) && defined(CONFIG_ARCH_MSM)
++	dhd->bus->islinkdown = 1;
++	dhd_os_check_hang(dhd, 0, -ETIMEDOUT);
++#endif /* SUPPORT_LINKDOWN_RECOVERY && CONFIG_ARCH_MSM */
++}
++
++/**
++ * dhd_prot_d2h_sync_seqnum - Sync on a D2H DMA completion using the SEQNUM
++ * mode. Sequence number is always in the last word of a message.
++ */
++static uint8 BCMFASTPATH
++dhd_prot_d2h_sync_seqnum(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++                         volatile cmn_msg_hdr_t *msg, int msglen)
++{
++	uint32 tries;
++	uint32 ring_seqnum = ring->seqnum % D2H_EPOCH_MODULO;
++	int num_words = msglen / sizeof(uint32); /* num of 32bit words */
++	volatile uint32 *marker = (uint32 *)msg + (num_words - 1); /* last word */
++	dhd_prot_t *prot = dhd->prot;
++
++	ASSERT(msglen == ring->item_len);
++
++	for (tries = 0; tries < PCIE_D2H_SYNC_WAIT_TRIES; tries++) {
++		uint32 msg_seqnum = *marker;
++		if (ltoh32(msg_seqnum) == ring_seqnum) { /* dma upto last word done */
++			ring->seqnum++; /* next expected sequence number */
++			goto dma_completed;
++		}
++
++		if (tries > prot->d2h_sync_wait_max)
++			prot->d2h_sync_wait_max = tries;
++
++		OSL_CACHE_INV(msg, msglen); /* invalidate and try again */
++		OSL_CPU_RELAX(); /* CPU relax for msg_seqnum  value to update */
++
++	} /* for PCIE_D2H_SYNC_WAIT_TRIES */
++
++	dhd_prot_d2h_sync_livelock(dhd, ring, tries, (uchar *)msg, msglen);
++
++	ring->seqnum++; /* skip this message ... leak of a pktid */
++	return MSG_TYPE_INVALID; /* invalid msg_type 0 -> noop callback */
++
++dma_completed:
++
++	prot->d2h_sync_wait_tot += tries;
++	return msg->msg_type;
++}
++
++/**
++ * dhd_prot_d2h_sync_xorcsum - Sync on a D2H DMA completion using the XORCSUM
++ * mode. The xorcsum is placed in the last word of a message. Dongle will also
++ * place a seqnum in the epoch field of the cmn_msg_hdr.
++ */
++static uint8 BCMFASTPATH
++dhd_prot_d2h_sync_xorcsum(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++                          volatile cmn_msg_hdr_t *msg, int msglen)
++{
++	uint32 tries;
++	uint32 prot_checksum = 0; /* computed checksum */
++	int num_words = msglen / sizeof(uint32); /* num of 32bit words */
++	uint8 ring_seqnum = ring->seqnum % D2H_EPOCH_MODULO;
++	dhd_prot_t *prot = dhd->prot;
++
++	ASSERT(msglen == ring->item_len);
++
++	for (tries = 0; tries < PCIE_D2H_SYNC_WAIT_TRIES; tries++) {
++		prot_checksum = bcm_compute_xor32((volatile uint32 *)msg, num_words);
++		if (prot_checksum == 0U) { /* checksum is OK */
++			if (msg->epoch == ring_seqnum) {
++				ring->seqnum++; /* next expected sequence number */
++				goto dma_completed;
++			}
++		}
++
++		if (tries > prot->d2h_sync_wait_max)
++			prot->d2h_sync_wait_max = tries;
++
++		OSL_CACHE_INV(msg, msglen); /* invalidate and try again */
++		OSL_CPU_RELAX(); /* CPU relax for msg_seqnum  value to update */
++
++	} /* for PCIE_D2H_SYNC_WAIT_TRIES */
++
++	dhd_prot_d2h_sync_livelock(dhd, ring, tries, (uchar *)msg, msglen);
++
++	ring->seqnum++; /* skip this message ... leak of a pktid */
++	return MSG_TYPE_INVALID; /* invalid msg_type 0 -> noop callback */
++
++dma_completed:
++
++	prot->d2h_sync_wait_tot += tries;
++	return msg->msg_type;
++}
++
++/**
++ * dhd_prot_d2h_sync_none - Dongle ensure that the DMA will complete and host
++ * need to try to sync. This noop sync handler will be bound when the dongle
++ * advertises that neither the SEQNUM nor XORCSUM mode of DMA sync is required.
++ */
++static uint8 BCMFASTPATH
++dhd_prot_d2h_sync_none(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++                       volatile cmn_msg_hdr_t *msg, int msglen)
++{
++	return msg->msg_type;
++}
++
++/**
++ * dhd_prot_d2h_sync_init - Setup the host side DMA sync mode based on what
++ * dongle advertizes.
++ */
++static void
++dhd_prot_d2h_sync_init(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	prot->d2h_sync_wait_max = 0UL;
++	prot->d2h_sync_wait_tot = 0UL;
++
++	prot->d2hring_ctrl_cpln.seqnum = D2H_EPOCH_INIT_VAL;
++	prot->d2hring_tx_cpln.seqnum = D2H_EPOCH_INIT_VAL;
++	prot->d2hring_rx_cpln.seqnum = D2H_EPOCH_INIT_VAL;
++
++	if (dhd->d2h_sync_mode & PCIE_SHARED_D2H_SYNC_SEQNUM) {
++		prot->d2h_sync_cb = dhd_prot_d2h_sync_seqnum;
++	} else if (dhd->d2h_sync_mode & PCIE_SHARED_D2H_SYNC_XORCSUM) {
++		prot->d2h_sync_cb = dhd_prot_d2h_sync_xorcsum;
++	} else {
++		prot->d2h_sync_cb = dhd_prot_d2h_sync_none;
++	}
++}
++
++#endif /* PCIE_D2H_SYNC */
++
++INLINE void
++dhd_wakeup_ioctl_event(dhd_pub_t *dhd, dhd_ioctl_recieved_status_t reason)
++{
++	/* To synchronize with the previous memory operations call wmb() */
++	OSL_SMP_WMB();
++	dhd->prot->ioctl_received = reason;
++	/* Call another wmb() to make sure before waking up the other event value gets updated */
++	OSL_SMP_WMB();
++	dhd_os_ioctl_resp_wake(dhd);
++}
++
++/**
++ * dhd_prot_h2d_sync_init - Per H2D common ring, setup the msgbuf ring seqnum
++ */
++static void
++dhd_prot_h2d_sync_init(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	prot->h2dring_rxp_subn.seqnum = H2D_EPOCH_INIT_VAL;
++	prot->h2dring_ctrl_subn.seqnum = H2D_EPOCH_INIT_VAL;
++}
++
++/* +-----------------  End of PCIE DHD H2D DMA SYNC ------------------------+ */
++
++
++/*
++ * +---------------------------------------------------------------------------+
++ * PCIE DMA-able buffer. Sets up a dhd_dma_buf_t object, which includes the
++ * virtual and physical address, the buffer lenght and the DMA handler.
++ * A secdma handler is also included in the dhd_dma_buf object.
++ * +---------------------------------------------------------------------------+
++ */
++
++static INLINE void
++dhd_base_addr_htolpa(sh_addr_t *base_addr, dmaaddr_t pa)
++{
++	base_addr->low_addr = htol32(PHYSADDRLO(pa));
++	base_addr->high_addr = htol32(PHYSADDRHI(pa));
++}
++
++
++/**
++ * dhd_dma_buf_audit - Any audits on a DHD DMA Buffer.
++ */
++static int
++dhd_dma_buf_audit(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf)
++{
++	uint32 base, end; /* dongle uses 32bit ptr arithmetic */
++
++	ASSERT(dma_buf);
++	base = PHYSADDRLO(dma_buf->pa);
++	ASSERT(base);
++	ASSERT(ISALIGNED(base, DMA_ALIGN_LEN));
++	ASSERT(dma_buf->len != 0);
++
++	/* test 32bit offset arithmetic over dma buffer for loss of carry-over */
++	end = (base + dma_buf->len); /* end address */
++
++	if ((end & 0xFFFFFFFF) < (base & 0xFFFFFFFF)) { /* exclude carryover */
++		DHD_ERROR(("%s: dma_buf %x len %d spans dongle 32bit ptr arithmetic\n",
++			__FUNCTION__, base, dma_buf->len));
++		return BCME_ERROR;
++	}
++
++	return BCME_OK;
++}
++
++/**
++ * dhd_dma_buf_alloc - Allocate a cache coherent DMA-able buffer.
++ * returns BCME_OK=0 on success
++ * returns non-zero negative error value on failure.
++ */
++static int
++dhd_dma_buf_alloc(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf, uint32 buf_len)
++{
++	uint32 dma_pad = 0;
++	osl_t *osh = dhd->osh;
++	int dma_align = DMA_ALIGN_LEN;
++
++
++	ASSERT(dma_buf != NULL);
++	ASSERT(dma_buf->va == NULL);
++	ASSERT(dma_buf->len == 0);
++
++	/* Pad the buffer length by one extra cacheline size.
++	 * Required for D2H direction.
++	 */
++	dma_pad = (buf_len % DHD_DMA_PAD) ? DHD_DMA_PAD : 0;
++	dma_buf->va = DMA_ALLOC_CONSISTENT(osh, buf_len + dma_pad,
++		dma_align, &dma_buf->_alloced, &dma_buf->pa, &dma_buf->dmah);
++
++	if (dma_buf->va == NULL) {
++		DHD_ERROR(("%s: buf_len %d, no memory available\n",
++			__FUNCTION__, buf_len));
++		return BCME_NOMEM;
++	}
++
++	dma_buf->len = buf_len; /* not including padded len */
++
++	if (dhd_dma_buf_audit(dhd, dma_buf) != BCME_OK) { /* audit dma buf */
++		dhd_dma_buf_free(dhd, dma_buf);
++		return BCME_ERROR;
++	}
++
++	dhd_dma_buf_reset(dhd, dma_buf); /* zero out and cache flush */
++
++	return BCME_OK;
++}
++
++/**
++ * dhd_dma_buf_reset - Reset a cache coherent DMA-able buffer.
++ */
++static void
++dhd_dma_buf_reset(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf)
++{
++	if ((dma_buf == NULL) || (dma_buf->va == NULL)) {
++		return;
++	}
++
++	(void)dhd_dma_buf_audit(dhd, dma_buf);
++
++	/* Zero out the entire buffer and cache flush */
++	memset((void*)dma_buf->va, 0, dma_buf->len);
++	OSL_CACHE_FLUSH((void *)dma_buf->va, dma_buf->len);
++}
++
++/**
++ * dhd_dma_buf_free - Free a DMA-able buffer that was previously allocated using
++ * dhd_dma_buf_alloc().
++ */
++static void
++dhd_dma_buf_free(dhd_pub_t *dhd, dhd_dma_buf_t *dma_buf)
++{
++	osl_t *osh = dhd->osh;
++
++	ASSERT(dma_buf);
++
++	if (dma_buf->va == NULL) {
++		return; /* Allow for free invocation, when alloc failed */
++	}
++
++	/* DEBUG: dhd_dma_buf_reset(dhd, dma_buf) */
++	(void)dhd_dma_buf_audit(dhd, dma_buf);
++
++	/* dma buffer may have been padded at allocation */
++	DMA_FREE_CONSISTENT(osh, dma_buf->va, dma_buf->_alloced,
++		dma_buf->pa, dma_buf->dmah);
++
++	memset(dma_buf, 0, sizeof(dhd_dma_buf_t));
++}
++
++/**
++ * dhd_dma_buf_init - Initialize a dhd_dma_buf with speicifed values.
++ * Do not use dhd_dma_buf_init to zero out a dhd_dma_buf_t object. Use memset 0.
++ */
++void
++dhd_dma_buf_init(dhd_pub_t *dhd, void *dhd_dma_buf,
++	void *va, uint32 len, dmaaddr_t pa, void *dmah, void *secdma)
++{
++	dhd_dma_buf_t *dma_buf;
++	ASSERT(dhd_dma_buf);
++	dma_buf = (dhd_dma_buf_t *)dhd_dma_buf;
++	dma_buf->va = va;
++	dma_buf->len = len;
++	dma_buf->pa = pa;
++	dma_buf->dmah = dmah;
++	dma_buf->secdma = secdma;
++
++	/* Audit user defined configuration */
++	(void)dhd_dma_buf_audit(dhd, dma_buf);
++}
++
++/* +------------------  End of PCIE DHD DMA BUF ADT ------------------------+ */
++
++/*
++ * +---------------------------------------------------------------------------+
++ * PktId Map: Provides a native packet pointer to unique 32bit PktId mapping.
++ * Main purpose is to save memory on the dongle, has other purposes as well.
++ * The packet id map, also includes storage for some packet parameters that
++ * may be saved. A native packet pointer along with the parameters may be saved
++ * and a unique 32bit pkt id will be returned. Later, the saved packet pointer
++ * and the metadata may be retrieved using the previously allocated packet id.
++ * +---------------------------------------------------------------------------+
++ */
++#define DHD_PCIE_PKTID
++#define MAX_PKTID_ITEMS     (3072 * 2) /* Maximum number of pktids supported */
++
++/* On Router, the pktptr serves as a pktid. */
++
++
++#if defined(PROP_TXSTATUS) && !defined(DHD_PCIE_PKTID)
++#error "PKTIDMAP must be supported with PROP_TXSTATUS/WLFC"
++#endif
++
++/* Enum for marking the buffer color based on usage */
++typedef enum dhd_pkttype {
++	PKTTYPE_DATA_TX = 0,
++	PKTTYPE_DATA_RX,
++	PKTTYPE_IOCTL_RX,
++	PKTTYPE_EVENT_RX,
++	/* dhd_prot_pkt_free no check, if pktid reserved and no space avail case */
++	PKTTYPE_NO_CHECK
++} dhd_pkttype_t;
++
++#define DHD_PKTID_INVALID               (0U)
++#define DHD_IOCTL_REQ_PKTID             (0xFFFE)
++#define DHD_FAKE_PKTID                  (0xFACE)
++
++#define DHD_PKTID_FREE_LOCKER           (FALSE)
++#define DHD_PKTID_RSV_LOCKER            (TRUE)
++
++typedef void * dhd_pktid_map_handle_t; /* opaque handle to a pktid map */
++
++/* Construct a packet id mapping table, returning an opaque map handle */
++static dhd_pktid_map_handle_t *dhd_pktid_map_init(dhd_pub_t *dhd, uint32 num_items, uint32 index);
++
++/* Destroy a packet id mapping table, freeing all packets active in the table */
++static void dhd_pktid_map_fini(dhd_pub_t *dhd, dhd_pktid_map_handle_t *map);
++
++#define PKTID_MAP_HANDLE	(0)
++#define PKTID_MAP_HANDLE_IOCTL	(1)
++
++#define DHD_NATIVE_TO_PKTID_INIT(dhd, items, index) dhd_pktid_map_init((dhd), (items), (index))
++#define DHD_NATIVE_TO_PKTID_FINI(dhd, map)   dhd_pktid_map_fini((dhd), (map))
++
++#if defined(DHD_PCIE_PKTID)
++
++
++/* Determine number of pktids that are available */
++static INLINE uint32 dhd_pktid_map_avail_cnt(dhd_pktid_map_handle_t *handle);
++
++/* Allocate a unique pktid against which a pkt and some metadata is saved */
++static INLINE uint32 dhd_pktid_map_reserve(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle,
++	void *pkt);
++static INLINE void dhd_pktid_map_save(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle,
++	void *pkt, uint32 nkey, dmaaddr_t pa, uint32 len, uint8 dma,
++	void *dmah, void *secdma, dhd_pkttype_t pkttype);
++static uint32 dhd_pktid_map_alloc(dhd_pub_t *dhd, dhd_pktid_map_handle_t *map,
++	void *pkt, dmaaddr_t pa, uint32 len, uint8 dma,
++	void *dmah, void *secdma, dhd_pkttype_t pkttype);
++
++/* Return an allocated pktid, retrieving previously saved pkt and metadata */
++static void *dhd_pktid_map_free(dhd_pub_t *dhd, dhd_pktid_map_handle_t *map,
++	uint32 id, dmaaddr_t *pa, uint32 *len, void **dmah,
++	void **secdma, dhd_pkttype_t pkttype, bool rsv_locker);
++
++/*
++ * DHD_PKTID_AUDIT_ENABLED: Audit of PktIds in DHD for duplicate alloc and frees
++ *
++ * DHD_PKTID_AUDIT_MAP: Audit the LIFO or FIFO PktIdMap allocator
++ * DHD_PKTID_AUDIT_RING: Audit the pktid during producer/consumer ring operation
++ *
++ * CAUTION: When DHD_PKTID_AUDIT_ENABLED is defined,
++ *    either DHD_PKTID_AUDIT_MAP or DHD_PKTID_AUDIT_RING may be selected.
++ */
++#ifndef DHD_PKTID_AUDIT_ENABLED
++#define DHD_PKTID_AUDIT_ENABLED 1
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++#define USE_DHD_PKTID_AUDIT_LOCK 1
++/* Audit the pktidmap allocator */
++/* #define DHD_PKTID_AUDIT_MAP */
++
++/* Audit the pktid during production/consumption of workitems */
++#define DHD_PKTID_AUDIT_RING
++
++#if defined(DHD_PKTID_AUDIT_MAP) && defined(DHD_PKTID_AUDIT_RING)
++#error "May only enabled audit of MAP or RING, at a time."
++#endif /* DHD_PKTID_AUDIT_MAP && DHD_PKTID_AUDIT_RING */
++
++#define DHD_DUPLICATE_ALLOC     1
++#define DHD_DUPLICATE_FREE      2
++#define DHD_TEST_IS_ALLOC       3
++#define DHD_TEST_IS_FREE        4
++
++#ifdef USE_DHD_PKTID_AUDIT_LOCK
++#define DHD_PKTID_AUDIT_LOCK_INIT(osh)          dhd_os_spin_lock_init(osh)
++#define DHD_PKTID_AUDIT_LOCK_DEINIT(osh, lock)  dhd_os_spin_lock_deinit(osh, lock)
++#define DHD_PKTID_AUDIT_LOCK(lock)              dhd_os_spin_lock(lock)
++#define DHD_PKTID_AUDIT_UNLOCK(lock, flags)     dhd_os_spin_unlock(lock, flags)
++#else
++#define DHD_PKTID_AUDIT_LOCK_INIT(osh)          (void *)(1)
++#define DHD_PKTID_AUDIT_LOCK_DEINIT(osh, lock)  do { /* noop */ } while (0)
++#define DHD_PKTID_AUDIT_LOCK(lock)              0
++#define DHD_PKTID_AUDIT_UNLOCK(lock, flags)     do { /* noop */ } while (0)
++#endif /* !USE_DHD_PKTID_AUDIT_LOCK */
++
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++/* #define USE_DHD_PKTID_LOCK   1 */
++
++#ifdef USE_DHD_PKTID_LOCK
++#define DHD_PKTID_LOCK_INIT(osh)                dhd_os_spin_lock_init(osh)
++#define DHD_PKTID_LOCK_DEINIT(osh, lock)        dhd_os_spin_lock_deinit(osh, lock)
++#define DHD_PKTID_LOCK(lock)                    dhd_os_spin_lock(lock)
++#define DHD_PKTID_UNLOCK(lock, flags)           dhd_os_spin_unlock(lock, flags)
++#else
++#define DHD_PKTID_LOCK_INIT(osh)                (void *)(1)
++#define DHD_PKTID_LOCK_DEINIT(osh, lock)	\
++	do { \
++		BCM_REFERENCE(osh); \
++		BCM_REFERENCE(lock); \
++	} while (0)
++#define DHD_PKTID_LOCK(lock)                    0
++#define DHD_PKTID_UNLOCK(lock, flags)           \
++	do { \
++		BCM_REFERENCE(lock); \
++		BCM_REFERENCE(flags); \
++	} while (0)
++#endif /* !USE_DHD_PKTID_LOCK */
++
++/* Packet metadata saved in packet id mapper */
++
++/* The Locker can be 3 states
++ * LOCKER_IS_FREE - Locker is free and can be allocated
++ * LOCKER_IS_BUSY - Locker is assigned and is being used, values in the
++ *                  locker (buffer address, len, phy addr etc) are populated
++ *		    with valid values
++ * LOCKER_IS_RSVD - The locker is reserved for future use, but the values
++ *                  in the locker are not valid. Especially pkt should be
++ *                  NULL in this state. When the user wants to re-use the
++ *                  locker dhd_pktid_map_free can be called with a flag
++ *                  to reserve the pktid for future use, which will clear
++ *                  the contents of the locker. When the user calls
++ *                  dhd_pktid_map_save the locker would move to LOCKER_IS_BUSY
++ */
++typedef enum dhd_locker_state {
++	LOCKER_IS_FREE,
++	LOCKER_IS_BUSY,
++	LOCKER_IS_RSVD
++} dhd_locker_state_t;
++
++typedef struct dhd_pktid_item {
++	dhd_locker_state_t state;  /* tag a locker to be free, busy or reserved */
++	uint8         dir;      /* dma map direction (Tx=flush or Rx=invalidate) */
++	dhd_pkttype_t pkttype;  /* pktlists are maintained based on pkttype */
++	uint16        len;      /* length of mapped packet's buffer */
++	void          *pkt;     /* opaque native pointer to a packet */
++	dmaaddr_t     pa;       /* physical address of mapped packet's buffer */
++	void          *dmah;    /* handle to OS specific DMA map */
++	void          *secdma;
++} dhd_pktid_item_t;
++
++typedef struct dhd_pktid_map {
++	uint32      items;    /* total items in map */
++	uint32      avail;    /* total available items */
++	int         failures; /* lockers unavailable count */
++	/* Spinlock to protect dhd_pktid_map in process/tasklet context */
++	void        *pktid_lock; /* Used when USE_DHD_PKTID_LOCK is defined */
++
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++	void	    *pktid_audit_lock;
++	struct bcm_mwbmap *pktid_audit; /* multi word bitmap based audit */
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++	uint32      keys[MAX_PKTID_ITEMS + 1]; /* stack of unique pkt ids */
++	dhd_pktid_item_t lockers[0];           /* metadata storage */
++} dhd_pktid_map_t;
++
++/*
++ * PktId (Locker) #0 is never allocated and is considered invalid.
++ *
++ * On request for a pktid, a value DHD_PKTID_INVALID must be treated as a
++ * depleted pktid pool and must not be used by the caller.
++ *
++ * Likewise, a caller must never free a pktid of value DHD_PKTID_INVALID.
++ */
++
++#define DHD_PKTID_ITEM_SZ               (sizeof(dhd_pktid_item_t))
++#define DHD_PKIDMAP_ITEMS(items)        (items)
++#define DHD_PKTID_MAP_SZ(items)         (sizeof(dhd_pktid_map_t) + \
++					(DHD_PKTID_ITEM_SZ * ((items) + 1)))
++
++#define DHD_NATIVE_TO_PKTID_FINI_IOCTL(dhd, map)  dhd_pktid_map_fini_ioctl((dhd), (map))
++
++/* Convert a packet to a pktid, and save pkt pointer in busy locker */
++#define DHD_NATIVE_TO_PKTID_RSV(dhd, map, pkt)    dhd_pktid_map_reserve((dhd), (map), (pkt))
++
++/* Reuse a previously reserved locker to save packet params */
++#define DHD_NATIVE_TO_PKTID_SAVE(dhd, map, pkt, nkey, pa, len, dir, dmah, secdma, pkttype) \
++	dhd_pktid_map_save((dhd), (map), (void *)(pkt), (nkey), (pa), (uint32)(len), \
++	                   (uint8)(dir), (void *)(dmah), (void *)(secdma), \
++			   (dhd_pkttype_t)(pkttype))
++
++/* Convert a packet to a pktid, and save packet params in locker */
++#define DHD_NATIVE_TO_PKTID(dhd, map, pkt, pa, len, dir, dmah, secdma, pkttype) \
++	dhd_pktid_map_alloc((dhd), (map), (void *)(pkt), (pa), (uint32)(len), \
++	                    (uint8)(dir), (void *)(dmah), (void *)(secdma), \
++			    (dhd_pkttype_t)(pkttype))
++
++/* Convert pktid to a packet, and free the locker */
++#define DHD_PKTID_TO_NATIVE(dhd, map, pktid, pa, len, dmah, secdma, pkttype) \
++	dhd_pktid_map_free((dhd), (map), (uint32)(pktid), \
++	(dmaaddr_t *)&(pa), (uint32 *)&(len), (void **)&(dmah), \
++	(void **) &secdma, (dhd_pkttype_t)(pkttype), DHD_PKTID_FREE_LOCKER)
++
++/* Convert the pktid to a packet, empty locker, but keep it reserved */
++#define DHD_PKTID_TO_NATIVE_RSV(dhd, map, pktid, pa, len, dmah, secdma, pkttype) \
++	dhd_pktid_map_free((dhd), (map), (uint32)(pktid), \
++	(dmaaddr_t *)&(pa), (uint32 *)&(len), (void **)&(dmah), \
++	(void **) &secdma, (dhd_pkttype_t)(pkttype), DHD_PKTID_RSV_LOCKER)
++
++#define DHD_PKTID_AVAIL(map)                 dhd_pktid_map_avail_cnt(map)
++
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++
++static int dhd_pktid_audit(dhd_pub_t *dhd, dhd_pktid_map_t *pktid_map, uint32 pktid,
++	const int test_for, const char *errmsg);
++
++/* Call back into OS layer to take the dongle dump and panic */
++#ifdef DHD_DEBUG_PAGEALLOC
++extern void dhd_pktid_audit_fail_cb(dhd_pub_t *dhdp);
++#endif /* DHD_DEBUG_PAGEALLOC */
++
++/**
++* dhd_pktid_audit - Use the mwbmap to audit validity of a pktid.
++*/
++static int
++dhd_pktid_audit(dhd_pub_t *dhd, dhd_pktid_map_t *pktid_map, uint32 pktid,
++	const int test_for, const char *errmsg)
++{
++#define DHD_PKT_AUDIT_STR "ERROR: %16s Host PktId Audit: "
++
++	const uint32 max_pktid_items = (MAX_PKTID_ITEMS);
++	struct bcm_mwbmap *handle;
++	uint32	flags;
++	bool ignore_audit;
++
++	if (pktid_map == (dhd_pktid_map_t *)NULL) {
++		DHD_ERROR((DHD_PKT_AUDIT_STR "Pkt id map NULL\n", errmsg));
++		return BCME_OK;
++	}
++
++	flags = DHD_PKTID_AUDIT_LOCK(pktid_map->pktid_audit_lock);
++
++	handle = pktid_map->pktid_audit;
++	if (handle == (struct bcm_mwbmap *)NULL) {
++		DHD_ERROR((DHD_PKT_AUDIT_STR "Handle NULL\n", errmsg));
++		DHD_PKTID_AUDIT_UNLOCK(pktid_map->pktid_audit_lock, flags);
++		return BCME_OK;
++	}
++
++	/* Exclude special pktids from audit */
++	ignore_audit = (pktid == DHD_IOCTL_REQ_PKTID) | (pktid == DHD_FAKE_PKTID);
++	if (ignore_audit) {
++		DHD_PKTID_AUDIT_UNLOCK(pktid_map->pktid_audit_lock, flags);
++		return BCME_OK;
++	}
++
++	if ((pktid == DHD_PKTID_INVALID) || (pktid > max_pktid_items)) {
++		DHD_ERROR((DHD_PKT_AUDIT_STR "PktId<%d> invalid\n", errmsg, pktid));
++		/* lock is released in "error" */
++		goto error;
++	}
++
++	/* Perform audit */
++	switch (test_for) {
++		case DHD_DUPLICATE_ALLOC:
++			if (!bcm_mwbmap_isfree(handle, pktid)) {
++				DHD_ERROR((DHD_PKT_AUDIT_STR "PktId<%d> alloc duplicate\n",
++				           errmsg, pktid));
++				goto error;
++			}
++			bcm_mwbmap_force(handle, pktid);
++			break;
++
++		case DHD_DUPLICATE_FREE:
++			if (bcm_mwbmap_isfree(handle, pktid)) {
++				DHD_ERROR((DHD_PKT_AUDIT_STR "PktId<%d> free duplicate\n",
++				           errmsg, pktid));
++				goto error;
++			}
++			bcm_mwbmap_free(handle, pktid);
++			break;
++
++		case DHD_TEST_IS_ALLOC:
++			if (bcm_mwbmap_isfree(handle, pktid)) {
++				DHD_ERROR((DHD_PKT_AUDIT_STR "PktId<%d> is not allocated\n",
++				           errmsg, pktid));
++				goto error;
++			}
++			break;
++
++		case DHD_TEST_IS_FREE:
++			if (!bcm_mwbmap_isfree(handle, pktid)) {
++				DHD_ERROR((DHD_PKT_AUDIT_STR "PktId<%d> is not free",
++				           errmsg, pktid));
++				goto error;
++			}
++			break;
++
++		default:
++			goto error;
++	}
++
++	DHD_PKTID_AUDIT_UNLOCK(pktid_map->pktid_audit_lock, flags);
++	return BCME_OK;
++
++error:
++
++	DHD_PKTID_AUDIT_UNLOCK(pktid_map->pktid_audit_lock, flags);
++	/* May insert any trap mechanism here ! */
++#ifdef DHD_DEBUG_PAGEALLOC
++	dhd_pktid_audit_fail_cb(dhd);
++#else
++	ASSERT(0);
++#endif /* DHD_DEBUG_PAGEALLOC */
++	return BCME_ERROR;
++}
++
++#define DHD_PKTID_AUDIT(dhdp, map, pktid, test_for) \
++	dhd_pktid_audit((dhdp), (dhd_pktid_map_t *)(map), (pktid), (test_for), __FUNCTION__)
++
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++/* +------------------  End of PCIE DHD PKTID AUDIT ------------------------+ */
++
++
++/**
++ * +---------------------------------------------------------------------------+
++ * Packet to Packet Id mapper using a <numbered_key, locker> paradigm.
++ *
++ * dhd_pktid_map manages a set of unique Packet Ids range[1..MAX_PKTID_ITEMS].
++ *
++ * dhd_pktid_map_alloc() may be used to save some packet metadata, and a unique
++ * packet id is returned. This unique packet id may be used to retrieve the
++ * previously saved packet metadata, using dhd_pktid_map_free(). On invocation
++ * of dhd_pktid_map_free(), the unique packet id is essentially freed. A
++ * subsequent call to dhd_pktid_map_alloc() may reuse this packet id.
++ *
++ * Implementation Note:
++ * Convert this into a <key,locker> abstraction and place into bcmutils !
++ * Locker abstraction should treat contents as opaque storage, and a
++ * callback should be registered to handle busy lockers on destructor.
++ *
++ * +---------------------------------------------------------------------------+
++ */
++
++/** Allocate and initialize a mapper of num_items <numbered_key, locker> */
++
++static dhd_pktid_map_handle_t *
++dhd_pktid_map_init(dhd_pub_t *dhd, uint32 num_items, uint32 index)
++{
++	void *osh;
++	uint32 nkey;
++	dhd_pktid_map_t *map;
++	uint32 dhd_pktid_map_sz;
++	uint32 map_items;
++#ifdef DHD_USE_STATIC_PKTIDMAP
++	uint32 section;
++#endif /* DHD_USE_STATIC_PKTIDMAP */
++	osh = dhd->osh;
++
++	ASSERT((num_items >= 1) && (num_items <= MAX_PKTID_ITEMS));
++	dhd_pktid_map_sz = DHD_PKTID_MAP_SZ(num_items);
++
++#ifdef DHD_USE_STATIC_PKTIDMAP
++	if (index == PKTID_MAP_HANDLE) {
++		section = DHD_PREALLOC_PKTID_MAP;
++	} else {
++		section = DHD_PREALLOC_PKTID_MAP_IOCTL;
++	}
++
++	map = (dhd_pktid_map_t *)DHD_OS_PREALLOC(dhd, section, dhd_pktid_map_sz);
++#else
++	map = (dhd_pktid_map_t *)MALLOC(osh, dhd_pktid_map_sz);
++#endif /* DHD_USE_STATIC_PKTIDMAP */
++
++	if (map == NULL) {
++		DHD_ERROR(("%s:%d: MALLOC failed for size %d\n",
++			__FUNCTION__, __LINE__, dhd_pktid_map_sz));
++		goto error;
++	}
++
++	bzero(map, dhd_pktid_map_sz);
++
++	/* Initialize the lock that protects this structure */
++	map->pktid_lock = DHD_PKTID_LOCK_INIT(osh);
++	if (map->pktid_lock == NULL) {
++		DHD_ERROR(("%s:%d: Lock init failed \r\n", __FUNCTION__, __LINE__));
++		goto error;
++	}
++
++	map->items = num_items;
++	map->avail = num_items;
++
++	map_items = DHD_PKIDMAP_ITEMS(map->items);
++
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++	/* Incarnate a hierarchical multiword bitmap for auditing pktid allocator */
++	map->pktid_audit = bcm_mwbmap_init(osh, map_items + 1);
++	if (map->pktid_audit == (struct bcm_mwbmap *)NULL) {
++		DHD_ERROR(("%s:%d: pktid_audit init failed\r\n", __FUNCTION__, __LINE__));
++		goto error;
++	} else {
++		DHD_ERROR(("%s:%d: pktid_audit init succeeded %d\n",
++			__FUNCTION__, __LINE__, map_items + 1));
++	}
++
++	map->pktid_audit_lock = DHD_PKTID_AUDIT_LOCK_INIT(osh);
++
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++	for (nkey = 1; nkey <= map_items; nkey++) { /* locker #0 is reserved */
++		map->keys[nkey] = nkey; /* populate with unique keys */
++		map->lockers[nkey].state = LOCKER_IS_FREE;
++		map->lockers[nkey].pkt   = NULL; /* bzero: redundant */
++		map->lockers[nkey].len   = 0;
++	}
++
++	/* Reserve pktid #0, i.e. DHD_PKTID_INVALID to be busy */
++	map->lockers[DHD_PKTID_INVALID].state = LOCKER_IS_BUSY;
++	map->lockers[DHD_PKTID_INVALID].pkt   = NULL; /* bzero: redundant */
++	map->lockers[DHD_PKTID_INVALID].len   = 0;
++
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++	/* do not use dhd_pktid_audit() here, use bcm_mwbmap_force directly */
++	bcm_mwbmap_force(map->pktid_audit, DHD_PKTID_INVALID);
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++	return (dhd_pktid_map_handle_t *)map; /* opaque handle */
++
++error:
++
++	if (map) {
++
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++		if (map->pktid_audit != (struct bcm_mwbmap *)NULL) {
++			bcm_mwbmap_fini(osh, map->pktid_audit); /* Destruct pktid_audit */
++			map->pktid_audit = (struct bcm_mwbmap *)NULL;
++			if (map->pktid_audit_lock)
++				DHD_PKTID_AUDIT_LOCK_DEINIT(osh, map->pktid_audit_lock);
++		}
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++		if (map->pktid_lock)
++			DHD_PKTID_LOCK_DEINIT(osh, map->pktid_lock);
++
++		MFREE(osh, map, dhd_pktid_map_sz);
++	}
++
++	return (dhd_pktid_map_handle_t *)NULL;
++}
++
++/**
++ * Retrieve all allocated keys and free all <numbered_key, locker>.
++ * Freeing implies: unmapping the buffers and freeing the native packet
++ * This could have been a callback registered with the pktid mapper.
++ */
++
++static void
++dhd_pktid_map_fini(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle)
++{
++	void *osh;
++	uint32 nkey;
++	dhd_pktid_map_t *map;
++	uint32 dhd_pktid_map_sz;
++	dhd_pktid_item_t *locker;
++	uint32 map_items;
++	uint32 flags;
++
++	if (handle == NULL) {
++		return;
++	}
++
++	map = (dhd_pktid_map_t *)handle;
++	flags =  DHD_PKTID_LOCK(map->pktid_lock);
++	osh = dhd->osh;
++
++	dhd_pktid_map_sz = DHD_PKTID_MAP_SZ(map->items);
++
++	nkey = 1; /* skip reserved KEY #0, and start from 1 */
++	locker = &map->lockers[nkey];
++
++	map_items = DHD_PKIDMAP_ITEMS(map->items);
++
++	for (; nkey <= map_items; nkey++, locker++) {
++
++		if (locker->state == LOCKER_IS_BUSY) { /* numbered key still in use */
++
++			locker->state = LOCKER_IS_FREE; /* force open the locker */
++
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++			DHD_PKTID_AUDIT(dhd, map, nkey, DHD_DUPLICATE_FREE); /* duplicate frees */
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++			{   /* This could be a callback registered with dhd_pktid_map */
++				DMA_UNMAP(osh, locker->pa, locker->len,
++					locker->dir, 0, DHD_DMAH_NULL);
++				dhd_prot_packet_free(dhd, (ulong*)locker->pkt,
++					locker->pkttype, TRUE);
++			}
++		}
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++		else {
++			DHD_PKTID_AUDIT(dhd, map, nkey, DHD_TEST_IS_FREE);
++		}
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++		locker->pkt = NULL; /* clear saved pkt */
++		locker->len = 0;
++	}
++
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++	if (map->pktid_audit != (struct bcm_mwbmap *)NULL) {
++		bcm_mwbmap_fini(osh, map->pktid_audit); /* Destruct pktid_audit */
++		map->pktid_audit = (struct bcm_mwbmap *)NULL;
++		if (map->pktid_audit_lock) {
++			DHD_PKTID_AUDIT_LOCK_DEINIT(osh, map->pktid_audit_lock);
++		}
++	}
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++	DHD_PKTID_UNLOCK(map->pktid_lock, flags);
++	DHD_PKTID_LOCK_DEINIT(osh, map->pktid_lock);
++
++#ifdef DHD_USE_STATIC_PKTIDMAP
++	DHD_OS_PREFREE(dhd, handle, dhd_pktid_map_sz);
++#else
++	MFREE(osh, handle, dhd_pktid_map_sz);
++#endif /* DHD_USE_STATIC_PKTIDMAP */
++}
++
++#ifdef IOCTLRESP_USE_CONSTMEM
++/** Called in detach scenario. Releasing IOCTL buffers. */
++static void
++dhd_pktid_map_fini_ioctl(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle)
++{
++	uint32 nkey;
++	dhd_pktid_map_t *map;
++	uint32 dhd_pktid_map_sz;
++	dhd_pktid_item_t *locker;
++	uint32 map_items;
++	uint32 flags;
++	osl_t *osh = dhd->osh;
++
++	if (handle == NULL) {
++		return;
++	}
++
++	map = (dhd_pktid_map_t *)handle;
++	flags = DHD_PKTID_LOCK(map->pktid_lock);
++
++	dhd_pktid_map_sz = DHD_PKTID_MAP_SZ(map->items);
++
++	nkey = 1; /* skip reserved KEY #0, and start from 1 */
++	locker = &map->lockers[nkey];
++
++	map_items = DHD_PKIDMAP_ITEMS(map->items);
++
++	for (; nkey <= map_items; nkey++, locker++) {
++
++		if (locker->state == LOCKER_IS_BUSY) { /* numbered key still in use */
++
++			locker->state = LOCKER_IS_FREE; /* force open the locker */
++
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++			DHD_PKTID_AUDIT(dhd, map, nkey, DHD_DUPLICATE_FREE); /* duplicate frees */
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++			{
++				dhd_dma_buf_t retbuf;
++				retbuf.va = locker->pkt;
++				retbuf.len = locker->len;
++				retbuf.pa = locker->pa;
++				retbuf.dmah = locker->dmah;
++				retbuf.secdma = locker->secdma;
++
++				/* This could be a callback registered with dhd_pktid_map */
++				DHD_PKTID_UNLOCK(map->pktid_lock, flags);
++				free_ioctl_return_buffer(dhd, &retbuf);
++				flags = DHD_PKTID_LOCK(map->pktid_lock);
++			}
++		}
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++		else {
++			DHD_PKTID_AUDIT(dhd, map, nkey, DHD_TEST_IS_FREE);
++		}
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++		locker->pkt = NULL; /* clear saved pkt */
++		locker->len = 0;
++	}
++
++#if defined(DHD_PKTID_AUDIT_ENABLED)
++	if (map->pktid_audit != (struct bcm_mwbmap *)NULL) {
++		bcm_mwbmap_fini(osh, map->pktid_audit); /* Destruct pktid_audit */
++		map->pktid_audit = (struct bcm_mwbmap *)NULL;
++		if (map->pktid_audit_lock) {
++			DHD_PKTID_AUDIT_LOCK_DEINIT(osh, map->pktid_audit_lock);
++		}
++	}
++#endif /* DHD_PKTID_AUDIT_ENABLED */
++
++	DHD_PKTID_UNLOCK(map->pktid_lock, flags);
++	DHD_PKTID_LOCK_DEINIT(osh, map->pktid_lock);
++
++#ifdef DHD_USE_STATIC_PKTIDMAP
++	DHD_OS_PREFREE(dhd, handle, dhd_pktid_map_sz);
++#else
++	MFREE(osh, handle, dhd_pktid_map_sz);
++#endif /* DHD_USE_STATIC_PKTIDMAP */
++}
++#endif /* IOCTLRESP_USE_CONSTMEM */
++
++/** Get the pktid free count */
++static INLINE uint32 BCMFASTPATH
++dhd_pktid_map_avail_cnt(dhd_pktid_map_handle_t *handle)
++{
++	dhd_pktid_map_t *map;
++	uint32	flags;
++	uint32	avail;
++
++	ASSERT(handle != NULL);
++	map = (dhd_pktid_map_t *)handle;
++
++	flags = DHD_PKTID_LOCK(map->pktid_lock);
++	avail = map->avail;
++	DHD_PKTID_UNLOCK(map->pktid_lock, flags);
++
++	return avail;
++}
++
++/**
++ * Allocate locker, save pkt contents, and return the locker's numbered key.
++ * dhd_pktid_map_alloc() is not reentrant, and is the caller's responsibility.
++ * Caller must treat a returned value DHD_PKTID_INVALID as a failure case,
++ * implying a depleted pool of pktids.
++ */
++
++static INLINE uint32
++__dhd_pktid_map_reserve(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle, void *pkt)
++{
++	uint32 nkey;
++	dhd_pktid_map_t *map;
++	dhd_pktid_item_t *locker;
++
++	ASSERT(handle != NULL);
++	map = (dhd_pktid_map_t *)handle;
++
++	if (map->avail <= 0) { /* no more pktids to allocate */
++		map->failures++;
++		DHD_INFO(("%s:%d: failed, no free keys\n", __FUNCTION__, __LINE__));
++		return DHD_PKTID_INVALID; /* failed alloc request */
++	}
++
++	ASSERT(map->avail <= map->items);
++	nkey = map->keys[map->avail]; /* fetch a free locker, pop stack */
++	locker = &map->lockers[nkey]; /* save packet metadata in locker */
++	map->avail--;
++	locker->pkt = pkt; /* pkt is saved, other params not yet saved. */
++	locker->len = 0;
++	locker->state = LOCKER_IS_BUSY; /* reserve this locker */
++
++#if defined(DHD_PKTID_AUDIT_MAP)
++	DHD_PKTID_AUDIT(dhd, map, nkey, DHD_DUPLICATE_ALLOC); /* Audit duplicate alloc */
++#endif /* DHD_PKTID_AUDIT_MAP */
++
++	ASSERT(nkey != DHD_PKTID_INVALID);
++	return nkey; /* return locker's numbered key */
++}
++
++
++/**
++ * dhd_pktid_map_reserve - reserve a unique numbered key. Reserved locker is not
++ * yet populated. Invoke the pktid save api to populate the packet parameters
++ * into the locker.
++ * Wrapper that takes the required lock when called directly.
++ */
++static INLINE uint32
++dhd_pktid_map_reserve(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle, void *pkt)
++{
++	dhd_pktid_map_t *map;
++	uint32 flags;
++	uint32 ret;
++
++	ASSERT(handle != NULL);
++	map = (dhd_pktid_map_t *)handle;
++	flags = DHD_PKTID_LOCK(map->pktid_lock);
++	ret = __dhd_pktid_map_reserve(dhd, handle, pkt);
++	DHD_PKTID_UNLOCK(map->pktid_lock, flags);
++
++	return ret;
++}
++
++static INLINE void
++__dhd_pktid_map_save(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle, void *pkt,
++	uint32 nkey, dmaaddr_t pa, uint32 len, uint8 dir, void *dmah, void *secdma,
++	dhd_pkttype_t pkttype)
++{
++	dhd_pktid_map_t *map;
++	dhd_pktid_item_t *locker;
++
++	ASSERT(handle != NULL);
++	map = (dhd_pktid_map_t *)handle;
++
++	ASSERT((nkey != DHD_PKTID_INVALID) && (nkey <= DHD_PKIDMAP_ITEMS(map->items)));
++
++	locker = &map->lockers[nkey];
++
++	ASSERT(((locker->state == LOCKER_IS_BUSY) && (locker->pkt == pkt)) ||
++		((locker->state == LOCKER_IS_RSVD) && (locker->pkt == NULL)));
++
++#if defined(DHD_PKTID_AUDIT_MAP)
++	DHD_PKTID_AUDIT(dhd, map, nkey, DHD_TEST_IS_ALLOC); /* apriori, reservation */
++#endif /* DHD_PKTID_AUDIT_MAP */
++
++	/* store contents in locker */
++	locker->dir = dir;
++	locker->pa = pa;
++	locker->len = (uint16)len; /* 16bit len */
++	locker->dmah = dmah; /* 16bit len */
++	locker->secdma = secdma;
++	locker->pkttype = pkttype;
++	locker->pkt = pkt;
++	locker->state = LOCKER_IS_BUSY; /* make this locker busy */
++}
++
++/**
++ * dhd_pktid_map_save - Save a packet's parameters into a locker corresponding
++ * to a previously reserved unique numbered key.
++ * Wrapper that takes the required lock when called directly.
++ */
++static INLINE void
++dhd_pktid_map_save(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle, void *pkt,
++	uint32 nkey, dmaaddr_t pa, uint32 len, uint8 dir, void *dmah, void *secdma,
++	dhd_pkttype_t pkttype)
++{
++	dhd_pktid_map_t *map;
++	uint32 flags;
++
++	ASSERT(handle != NULL);
++	map = (dhd_pktid_map_t *)handle;
++	flags = DHD_PKTID_LOCK(map->pktid_lock);
++	__dhd_pktid_map_save(dhd, handle, pkt, nkey, pa, len,
++		dir, dmah, secdma, pkttype);
++	DHD_PKTID_UNLOCK(map->pktid_lock, flags);
++}
++
++/**
++ * dhd_pktid_map_alloc - Allocate a unique numbered key and save the packet
++ * contents into the corresponding locker. Return the numbered key.
++ */
++static uint32 BCMFASTPATH
++dhd_pktid_map_alloc(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle, void *pkt,
++	dmaaddr_t pa, uint32 len, uint8 dir, void *dmah, void *secdma,
++	dhd_pkttype_t pkttype)
++{
++	uint32 nkey;
++	uint32 flags;
++	dhd_pktid_map_t *map;
++
++	ASSERT(handle != NULL);
++	map = (dhd_pktid_map_t *)handle;
++
++	flags = DHD_PKTID_LOCK(map->pktid_lock);
++
++	nkey = __dhd_pktid_map_reserve(dhd, handle, pkt);
++	if (nkey != DHD_PKTID_INVALID) {
++		__dhd_pktid_map_save(dhd, handle, pkt, nkey, pa,
++			len, dir, dmah, secdma, pkttype);
++#if defined(DHD_PKTID_AUDIT_MAP)
++		DHD_PKTID_AUDIT(dhd, map, nkey, DHD_TEST_IS_ALLOC); /* apriori, reservation */
++#endif /* DHD_PKTID_AUDIT_MAP */
++	}
++
++#ifdef CUSTOMER_HW_31_2
++	/* Need to do the flush at buffer allocation time */
++	DHD_TRACE(("%s: flush buffer 0x%x len %d\n", __FUNCTION__,
++		PKTDATA(dhd->osh, pkt), PKTLEN(dhd->osh, pkt)));
++	OSL_CACHE_FLUSH(PKTDATA(dhd->osh, pkt), PKTLEN(dhd->osh, pkt));
++#endif
++	DHD_PKTID_UNLOCK(map->pktid_lock, flags);
++
++	return nkey;
++}
++
++/**
++ * dhd_pktid_map_free - Given a numbered key, return the locker contents.
++ * dhd_pktid_map_free() is not reentrant, and is the caller's responsibility.
++ * Caller may not free a pktid value DHD_PKTID_INVALID or an arbitrary pktid
++ * value. Only a previously allocated pktid may be freed.
++ */
++static void * BCMFASTPATH
++dhd_pktid_map_free(dhd_pub_t *dhd, dhd_pktid_map_handle_t *handle, uint32 nkey,
++	dmaaddr_t *pa, uint32 *len, void **dmah, void **secdma,
++	dhd_pkttype_t pkttype, bool rsv_locker)
++{
++	dhd_pktid_map_t *map;
++	dhd_pktid_item_t *locker;
++	void * pkt;
++	uint32 flags;
++
++	ASSERT(handle != NULL);
++
++	map = (dhd_pktid_map_t *)handle;
++
++	flags = DHD_PKTID_LOCK(map->pktid_lock);
++
++	ASSERT((nkey != DHD_PKTID_INVALID) && (nkey <= DHD_PKIDMAP_ITEMS(map->items)));
++
++	locker = &map->lockers[nkey];
++
++#if defined(DHD_PKTID_AUDIT_MAP)
++	DHD_PKTID_AUDIT(dhd, map, nkey, DHD_DUPLICATE_FREE); /* Audit duplicate FREE */
++#endif /* DHD_PKTID_AUDIT_MAP */
++
++	if (locker->state == LOCKER_IS_FREE) { /* Debug check for cloned numbered key */
++		DHD_ERROR(("%s:%d: Error! freeing invalid pktid<%u>\n",
++			__FUNCTION__, __LINE__, nkey));
++		ASSERT(locker->state != LOCKER_IS_FREE);
++
++		DHD_PKTID_UNLOCK(map->pktid_lock, flags);
++		return NULL;
++	}
++
++	/* Check for the colour of the buffer i.e The buffer posted for TX,
++	 * should be freed for TX completion. Similarly the buffer posted for
++	 * IOCTL should be freed for IOCT completion etc.
++	 */
++	if ((pkttype != PKTTYPE_NO_CHECK) && (locker->pkttype != pkttype)) {
++
++		DHD_PKTID_UNLOCK(map->pktid_lock, flags);
++
++		DHD_ERROR(("%s:%d: Error! Invalid Buffer Free for pktid<%u> \n",
++			__FUNCTION__, __LINE__, nkey));
++		ASSERT(locker->pkttype == pkttype);
++
++		return NULL;
++	}
++
++	if (rsv_locker == DHD_PKTID_FREE_LOCKER) {
++		map->avail++;
++		map->keys[map->avail] = nkey; /* make this numbered key available */
++		locker->state = LOCKER_IS_FREE; /* open and free Locker */
++	} else {
++		/* pktid will be reused, but the locker does not have a valid pkt */
++		locker->state = LOCKER_IS_RSVD;
++	}
++
++#if defined(DHD_PKTID_AUDIT_MAP)
++	DHD_PKTID_AUDIT(dhd, map, nkey, DHD_TEST_IS_FREE);
++#endif /* DHD_PKTID_AUDIT_MAP */
++
++	*pa = locker->pa; /* return contents of locker */
++	*len = (uint32)locker->len;
++	*dmah = locker->dmah;
++	*secdma = locker->secdma;
++
++	pkt = locker->pkt;
++	locker->pkt = NULL; /* Clear pkt */
++	locker->len = 0;
++
++#ifdef CUSTOMER_HW_31_2
++	/* need to do to ensure all packet are flushed */
++	OSL_CACHE_INV(PKTDATA(dhd->osh, pkt), PKTLEN(dhd->osh, pkt));
++#endif
++
++	DHD_PKTID_UNLOCK(map->pktid_lock, flags);
++	return pkt;
++}
++
++#else /* ! DHD_PCIE_PKTID */
++
++
++typedef struct pktlist {
++	PKT_LIST *tx_pkt_list;		/* list for tx packets */
++	PKT_LIST *rx_pkt_list;		/* list for rx packets */
++	PKT_LIST *ctrl_pkt_list;	/* list for ioctl/event buf post */
++} pktlists_t;
++
++/*
++ * Given that each workitem only uses a 32bit pktid, only 32bit hosts may avail
++ * of a one to one mapping 32bit pktptr and a 32bit pktid.
++ *
++ * - When PKTIDMAP is not used, DHD_NATIVE_TO_PKTID variants will never fail.
++ * - Neither DHD_NATIVE_TO_PKTID nor DHD_PKTID_TO_NATIVE need to be protected by
++ *   a lock.
++ * - Hence DHD_PKTID_INVALID is not defined when DHD_PCIE_PKTID is undefined.
++ */
++#define DHD_PKTID32(pktptr32)	((uint32)(pktptr32))
++#define DHD_PKTPTR32(pktid32)	((void *)(pktid32))
++
++
++static INLINE uint32 dhd_native_to_pktid(dhd_pktid_map_handle_t *map, void *pktptr32,
++	dmaaddr_t pa, uint32 dma_len, void *dmah, void *secdma,
++	dhd_pkttype_t pkttype);
++static INLINE void * dhd_pktid_to_native(dhd_pktid_map_handle_t *map, uint32 pktid32,
++	dmaaddr_t *pa, uint32 *dma_len, void **dmah, void **secdma,
++	dhd_pkttype_t pkttype);
++
++static dhd_pktid_map_handle_t *
++dhd_pktid_map_init(dhd_pub_t *dhd, uint32 num_items, uint32 index)
++{
++	osl_t *osh = dhd->osh;
++	pktlists_t *handle = NULL;
++
++	if ((handle = (pktlists_t *) MALLOCZ(osh, sizeof(pktlists_t))) == NULL) {
++		DHD_ERROR(("%s:%d: MALLOC failed for lists allocation, size=%d\n",
++		           __FUNCTION__, __LINE__, sizeof(pktlists_t)));
++		goto error_done;
++	}
++
++	if ((handle->tx_pkt_list = (PKT_LIST *) MALLOC(osh, sizeof(PKT_LIST))) == NULL) {
++		DHD_ERROR(("%s:%d: MALLOC failed for list allocation, size=%d\n",
++		           __FUNCTION__, __LINE__, sizeof(PKT_LIST)));
++		goto error;
++	}
++
++	if ((handle->rx_pkt_list = (PKT_LIST *) MALLOC(osh, sizeof(PKT_LIST))) == NULL) {
++		DHD_ERROR(("%s:%d: MALLOC failed for list allocation, size=%d\n",
++		           __FUNCTION__, __LINE__, sizeof(PKT_LIST)));
++		goto error;
++	}
++
++	if ((handle->ctrl_pkt_list = (PKT_LIST *) MALLOC(osh, sizeof(PKT_LIST))) == NULL) {
++		DHD_ERROR(("%s:%d: MALLOC failed for list allocation, size=%d\n",
++		           __FUNCTION__, __LINE__, sizeof(PKT_LIST)));
++		goto error;
++	}
++
++	PKTLIST_INIT(handle->tx_pkt_list);
++	PKTLIST_INIT(handle->rx_pkt_list);
++	PKTLIST_INIT(handle->ctrl_pkt_list);
++
++	return (dhd_pktid_map_handle_t *) handle;
++
++error:
++	if (handle->ctrl_pkt_list) {
++		MFREE(osh, handle->ctrl_pkt_list, sizeof(PKT_LIST));
++	}
++
++	if (handle->rx_pkt_list) {
++		MFREE(osh, handle->rx_pkt_list, sizeof(PKT_LIST));
++	}
++
++	if (handle->tx_pkt_list) {
++		MFREE(osh, handle->tx_pkt_list, sizeof(PKT_LIST));
++	}
++
++	if (handle) {
++		MFREE(osh, handle, sizeof(pktlists_t));
++	}
++
++error_done:
++	return (dhd_pktid_map_handle_t *)NULL;
++}
++
++static void
++dhd_pktid_map_fini(dhd_pub_t *dhd, dhd_pktid_map_handle_t *map)
++{
++	osl_t *osh = dhd->osh;
++	pktlists_t *handle = (pktlists_t *) map;
++
++	ASSERT(handle != NULL);
++	if (handle == (pktlists_t *)NULL) {
++		return;
++	}
++
++	if (handle->ctrl_pkt_list) {
++		PKTLIST_FINI(handle->ctrl_pkt_list);
++		MFREE(osh, handle->ctrl_pkt_list, sizeof(PKT_LIST));
++	}
++
++	if (handle->rx_pkt_list) {
++		PKTLIST_FINI(handle->rx_pkt_list);
++		MFREE(osh, handle->rx_pkt_list, sizeof(PKT_LIST));
++	}
++
++	if (handle->tx_pkt_list) {
++		PKTLIST_FINI(handle->tx_pkt_list);
++		MFREE(osh, handle->tx_pkt_list, sizeof(PKT_LIST));
++	}
++
++	if (handle) {
++		MFREE(osh, handle, sizeof(pktlists_t));
++	}
++}
++
++/** Save dma parameters into the packet's pkttag and convert a pktptr to pktid */
++static INLINE uint32
++dhd_native_to_pktid(dhd_pktid_map_handle_t *map, void *pktptr32,
++	dmaaddr_t pa, uint32 dma_len, void *dmah, void *secdma,
++	dhd_pkttype_t pkttype)
++{
++	pktlists_t *handle = (pktlists_t *) map;
++	ASSERT(pktptr32 != NULL);
++	DHD_PKT_SET_DMA_LEN(pktptr32, dma_len);
++	DHD_PKT_SET_DMAH(pktptr32, dmah);
++	DHD_PKT_SET_PA(pktptr32, pa);
++	DHD_PKT_SET_SECDMA(pktptr32, secdma);
++
++	if (pkttype == PKTTYPE_DATA_TX) {
++		PKTLIST_ENQ(handle->tx_pkt_list,  pktptr32);
++	} else if (pkttype == PKTTYPE_DATA_RX) {
++		PKTLIST_ENQ(handle->rx_pkt_list,  pktptr32);
++	} else {
++		PKTLIST_ENQ(handle->ctrl_pkt_list,  pktptr32);
++	}
++
++	return DHD_PKTID32(pktptr32);
++}
++
++/** Convert a pktid to pktptr and retrieve saved dma parameters from packet */
++static INLINE void *
++dhd_pktid_to_native(dhd_pktid_map_handle_t *map, uint32 pktid32,
++	dmaaddr_t *pa, uint32 *dma_len, void **dmah, void **secdma,
++	dhd_pkttype_t pkttype)
++{
++	pktlists_t *handle = (pktlists_t *) map;
++	void *pktptr32;
++
++	ASSERT(pktid32 != 0U);
++	pktptr32 = DHD_PKTPTR32(pktid32);
++	*dma_len = DHD_PKT_GET_DMA_LEN(pktptr32);
++	*dmah = DHD_PKT_GET_DMAH(pktptr32);
++	*pa = DHD_PKT_GET_PA(pktptr32);
++	*secdma = DHD_PKT_GET_SECDMA(pktptr32);
++
++	if (pkttype == PKTTYPE_DATA_TX) {
++		PKTLIST_UNLINK(handle->tx_pkt_list,  pktptr32);
++	} else if (pkttype == PKTTYPE_DATA_RX) {
++		PKTLIST_UNLINK(handle->rx_pkt_list,  pktptr32);
++	} else {
++		PKTLIST_UNLINK(handle->ctrl_pkt_list,  pktptr32);
++	}
++
++	return pktptr32;
++}
++
++#define DHD_NATIVE_TO_PKTID_RSV(dhd, map, pkt)  DHD_PKTID32(pkt)
++
++#define DHD_NATIVE_TO_PKTID_SAVE(dhd, map, pkt, nkey, pa, len, dma_dir, dmah, secdma, pkttype) \
++	({ BCM_REFERENCE(dhd); BCM_REFERENCE(nkey); BCM_REFERENCE(dma_dir); \
++	   dhd_native_to_pktid((dhd_pktid_map_handle_t *) map, (pkt), (pa), (len), \
++			   (dmah), (secdma), (dhd_pkttype_t)(pkttype)); \
++	})
++
++#define DHD_NATIVE_TO_PKTID(dhd, map, pkt, pa, len, dma_dir, dmah, secdma, pkttype) \
++	({ BCM_REFERENCE(dhd); BCM_REFERENCE(dma_dir); \
++	   dhd_native_to_pktid((dhd_pktid_map_handle_t *) map, (pkt), (pa), (len), \
++			   (dmah), (secdma), (dhd_pkttype_t)(pkttype)); \
++	})
++
++#define DHD_PKTID_TO_NATIVE(dhd, map, pktid, pa, len, dmah, secdma, pkttype) \
++	({ BCM_REFERENCE(dhd); BCM_REFERENCE(pkttype);	\
++		dhd_pktid_to_native((dhd_pktid_map_handle_t *) map, (uint32)(pktid), \
++				(dmaaddr_t *)&(pa), (uint32 *)&(len), (void **)&(dmah), \
++				(void **)&secdma, (dhd_pkttype_t)(pkttype)); \
++	})
++
++#define DHD_PKTID_AVAIL(map)  (~0)
++
++#endif /* ! DHD_PCIE_PKTID */
++
++/* +------------------ End of PCIE DHD PKTID MAPPER  -----------------------+ */
++
++
++/**
++ * The PCIE FD protocol layer is constructed in two phases:
++ *    Phase 1. dhd_prot_attach()
++ *    Phase 2. dhd_prot_init()
++ *
++ * dhd_prot_attach() - Allocates a dhd_prot_t object and resets all its fields.
++ * All Common rings are allose attached (msgbuf_ring_t objects are allocated
++ * with DMA-able buffers).
++ * All dhd_dma_buf_t objects are also allocated here.
++ *
++ * As dhd_prot_attach is invoked prior to the pcie_shared object is read, any
++ * initialization of objects that requires information advertized by the dongle
++ * may not be performed here.
++ * E.g. the number of TxPost flowrings is not know at this point, neither do
++ * we know shich form of D2H DMA sync mechanism is advertized by the dongle, or
++ * whether the dongle supports DMA-ing of WR/RD indices for the H2D and/or D2H
++ * rings (common + flow).
++ *
++ * dhd_prot_init() is invoked after the bus layer has fetched the information
++ * advertized by the dongle in the pcie_shared_t.
++ */
++int
++dhd_prot_attach(dhd_pub_t *dhd)
++{
++	osl_t *osh = dhd->osh;
++	dhd_prot_t *prot;
++
++	/* Allocate prot structure */
++	if (!(prot = (dhd_prot_t *)DHD_OS_PREALLOC(dhd, DHD_PREALLOC_PROT,
++		sizeof(dhd_prot_t)))) {
++		DHD_ERROR(("%s: kmalloc failed\n", __FUNCTION__));
++		goto fail;
++	}
++	memset(prot, 0, sizeof(*prot));
++
++	prot->osh = osh;
++	dhd->prot = prot;
++
++	/* DMAing ring completes supported? FALSE by default  */
++	dhd->dma_d2h_ring_upd_support = FALSE;
++	dhd->dma_h2d_ring_upd_support = FALSE;
++
++	/* Common Ring Allocations */
++
++	/* Ring  0: H2D Control Submission */
++	if (dhd_prot_ring_attach(dhd, &prot->h2dring_ctrl_subn, "h2dctrl",
++	        H2DRING_CTRL_SUB_MAX_ITEM, H2DRING_CTRL_SUB_ITEMSIZE,
++	        BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT) != BCME_OK) {
++		DHD_ERROR(("%s: dhd_prot_ring_attach H2D Ctrl Submission failed\n",
++			__FUNCTION__));
++		goto fail;
++	}
++
++	/* Ring  1: H2D Receive Buffer Post */
++	if (dhd_prot_ring_attach(dhd, &prot->h2dring_rxp_subn, "h2drxp",
++	        H2DRING_RXPOST_MAX_ITEM, H2DRING_RXPOST_ITEMSIZE,
++	        BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT) != BCME_OK) {
++		DHD_ERROR(("%s: dhd_prot_ring_attach H2D RxPost failed\n",
++			__FUNCTION__));
++		goto fail;
++	}
++
++	/* Ring  2: D2H Control Completion */
++	if (dhd_prot_ring_attach(dhd, &prot->d2hring_ctrl_cpln, "d2hctrl",
++	        D2HRING_CTRL_CMPLT_MAX_ITEM, D2HRING_CTRL_CMPLT_ITEMSIZE,
++	        BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE) != BCME_OK) {
++		DHD_ERROR(("%s: dhd_prot_ring_attach D2H Ctrl Completion failed\n",
++			__FUNCTION__));
++		goto fail;
++	}
++
++	/* Ring  3: D2H Transmit Complete */
++	if (dhd_prot_ring_attach(dhd, &prot->d2hring_tx_cpln, "d2htxcpl",
++	        D2HRING_TXCMPLT_MAX_ITEM, D2HRING_TXCMPLT_ITEMSIZE,
++	        BCMPCIE_D2H_MSGRING_TX_COMPLETE) != BCME_OK) {
++		DHD_ERROR(("%s: dhd_prot_ring_attach D2H Tx Completion failed\n",
++			__FUNCTION__));
++		goto fail;
++
++	}
++
++	/* Ring  4: D2H Receive Complete */
++	if (dhd_prot_ring_attach(dhd, &prot->d2hring_rx_cpln, "d2hrxcpl",
++	        D2HRING_RXCMPLT_MAX_ITEM, D2HRING_RXCMPLT_ITEMSIZE,
++	        BCMPCIE_D2H_MSGRING_RX_COMPLETE) != BCME_OK) {
++		DHD_ERROR(("%s: dhd_prot_ring_attach D2H Rx Completion failed\n",
++			__FUNCTION__));
++		goto fail;
++
++	}
++
++	/*
++	 * Max number of flowrings is not yet known. msgbuf_ring_t with DMA-able
++	 * buffers for flowrings will be instantiated, in dhd_prot_init() .
++	 * See dhd_prot_flowrings_pool_attach()
++	 */
++	/* ioctl response buffer */
++	if (dhd_dma_buf_alloc(dhd, &prot->retbuf, IOCT_RETBUF_SIZE)) {
++		goto fail;
++	}
++
++	/* IOCTL request buffer */
++	if (dhd_dma_buf_alloc(dhd, &prot->ioctbuf, IOCT_RETBUF_SIZE)) {
++		goto fail;
++	}
++
++	/* Scratch buffer for dma rx offset */
++#ifdef BCM_HOST_BUF
++	if (dhd_dma_buf_alloc(dhd, &prot->d2h_dma_scratch_buf,
++		ROUNDUP(DMA_D2H_SCRATCH_BUF_LEN, 16) + DMA_HOST_BUFFER_LEN)) {
++#else
++	if (dhd_dma_buf_alloc(dhd, &prot->d2h_dma_scratch_buf, DMA_D2H_SCRATCH_BUF_LEN)) {
++
++#endif /* BCM_HOST_BUF */
++		goto fail;
++	}
++
++	/* scratch buffer bus throughput measurement */
++	if (dhd_dma_buf_alloc(dhd, &prot->host_bus_throughput_buf, DHD_BUS_TPUT_BUF_LEN)) {
++		goto fail;
++	}
++
++#ifdef DHD_RX_CHAINING
++	dhd_rxchain_reset(&prot->rxchain);
++#endif
++
++#if defined(DHD_LB)
++
++	   /* Initialize the work queues to be used by the Load Balancing logic */
++#if defined(DHD_LB_TXC)
++	{
++		void *buffer;
++		buffer = MALLOC(dhd->osh, sizeof(void*) * DHD_LB_WORKQ_SZ);
++		bcm_workq_init(&prot->tx_compl_prod, &prot->tx_compl_cons,
++			buffer, DHD_LB_WORKQ_SZ);
++		prot->tx_compl_prod_sync = 0;
++		DHD_INFO(("%s: created tx_compl_workq <%p,%d>\n",
++			__FUNCTION__, buffer, DHD_LB_WORKQ_SZ));
++	}
++#endif /* DHD_LB_TXC */
++
++#if defined(DHD_LB_RXC)
++	{
++		void *buffer;
++		buffer = MALLOC(dhd->osh, sizeof(uint32) * DHD_LB_WORKQ_SZ);
++		bcm_workq_init(&prot->rx_compl_prod, &prot->rx_compl_cons,
++			buffer, DHD_LB_WORKQ_SZ);
++		prot->rx_compl_prod_sync = 0;
++		DHD_INFO(("%s: created rx_compl_workq <%p,%d>\n",
++			__FUNCTION__, buffer, DHD_LB_WORKQ_SZ));
++	}
++#endif /* DHD_LB_RXC */
++
++#endif /* DHD_LB */
++
++	return BCME_OK;
++
++fail:
++
++#ifndef CONFIG_DHD_USE_STATIC_BUF
++	if (prot != NULL) {
++		dhd_prot_detach(dhd);
++	}
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++
++	return BCME_NOMEM;
++} /* dhd_prot_attach */
++
++
++/**
++ * dhd_prot_init - second stage of dhd_prot_attach. Now that the dongle has
++ * completed it's initialization of the pcie_shared structure, we may now fetch
++ * the dongle advertized features and adjust the protocol layer accordingly.
++ *
++ * dhd_prot_init() may be invoked again after a dhd_prot_reset().
++ */
++int
++dhd_prot_init(dhd_pub_t *dhd)
++{
++	sh_addr_t base_addr;
++	dhd_prot_t *prot = dhd->prot;
++
++	/* PKTID handle INIT */
++	if (prot->pktid_map_handle != NULL) {
++		DHD_ERROR(("%s: pktid_map_handle already set!\n", __FUNCTION__));
++		ASSERT(0);
++		return BCME_ERROR;
++	}
++
++#ifdef IOCTLRESP_USE_CONSTMEM
++	if (prot->pktid_map_handle_ioctl != NULL) {
++		DHD_ERROR(("%s: pktid_map_handle_ioctl already set!\n", __FUNCTION__));
++		ASSERT(0);
++		return BCME_ERROR;
++	}
++#endif /* IOCTLRESP_USE_CONSTMEM */
++
++	prot->pktid_map_handle = DHD_NATIVE_TO_PKTID_INIT(dhd, MAX_PKTID_ITEMS, PKTID_MAP_HANDLE);
++	if (prot->pktid_map_handle == NULL) {
++		DHD_ERROR(("%s: Unable to map packet id's\n", __FUNCTION__));
++		ASSERT(0);
++		return BCME_NOMEM;
++	}
++
++#ifdef IOCTLRESP_USE_CONSTMEM
++	prot->pktid_map_handle_ioctl = DHD_NATIVE_TO_PKTID_INIT(dhd,
++		DHD_FLOWRING_MAX_IOCTLRESPBUF_POST, PKTID_MAP_HANDLE_IOCTL);
++	if (prot->pktid_map_handle_ioctl == NULL) {
++		DHD_ERROR(("%s: Unable to map ioctl response buffers\n", __FUNCTION__));
++		ASSERT(0);
++		return BCME_NOMEM;
++	}
++#endif /* IOCTLRESP_USE_CONSTMEM */
++
++	/* Max pkts in ring */
++	prot->max_tx_count = H2DRING_TXPOST_MAX_ITEM;
++
++	DHD_INFO(("%s:%d: MAX_TX_COUNT = %d\n", __FUNCTION__, __LINE__, prot->max_tx_count));
++
++	/* Read max rx packets supported by dongle */
++	dhd_bus_cmn_readshared(dhd->bus, &prot->max_rxbufpost, MAX_HOST_RXBUFS, 0);
++	if (prot->max_rxbufpost == 0) {
++		/* This would happen if the dongle firmware is not */
++		/* using the latest shared structure template */
++		prot->max_rxbufpost = DEFAULT_RX_BUFFERS_TO_POST;
++	}
++	DHD_INFO(("%s:%d: MAX_RXBUFPOST = %d\n", __FUNCTION__, __LINE__, prot->max_rxbufpost));
++
++	/* Initialize.  bzero() would blow away the dma pointers. */
++	prot->max_eventbufpost = DHD_FLOWRING_MAX_EVENTBUF_POST;
++	prot->max_ioctlrespbufpost = DHD_FLOWRING_MAX_IOCTLRESPBUF_POST;
++
++	prot->cur_ioctlresp_bufs_posted = 0;
++	prot->active_tx_count = 0;
++	prot->data_seq_no = 0;
++	prot->ioctl_seq_no = 0;
++	prot->rxbufpost = 0;
++	prot->cur_event_bufs_posted = 0;
++	prot->ioctl_state = 0;
++	prot->curr_ioctl_cmd = 0;
++	prot->ioctl_received = IOCTL_WAIT;
++
++	prot->dmaxfer.srcmem.va = NULL;
++	prot->dmaxfer.dstmem.va = NULL;
++	prot->dmaxfer.in_progress = FALSE;
++
++	prot->metadata_dbg = FALSE;
++	prot->rx_metadata_offset = 0;
++	prot->tx_metadata_offset = 0;
++	prot->txp_threshold = TXP_FLUSH_MAX_ITEMS_FLUSH_CNT;
++
++	prot->ioctl_trans_id = 0;
++
++	/* Register the interrupt function upfront */
++	/* remove corerev checks in data path */
++	prot->mb_ring_fn = dhd_bus_get_mbintr_fn(dhd->bus);
++
++	/* Initialize Common MsgBuf Rings */
++
++	dhd_prot_ring_init(dhd, &prot->h2dring_ctrl_subn);
++	dhd_prot_ring_init(dhd, &prot->h2dring_rxp_subn);
++	dhd_prot_ring_init(dhd, &prot->d2hring_ctrl_cpln);
++	dhd_prot_ring_init(dhd, &prot->d2hring_tx_cpln);
++	dhd_prot_ring_init(dhd, &prot->d2hring_rx_cpln);
++
++#if defined(PCIE_D2H_SYNC)
++	dhd_prot_d2h_sync_init(dhd);
++#endif /* PCIE_D2H_SYNC */
++
++	dhd_prot_h2d_sync_init(dhd);
++
++	/* init the scratch buffer */
++	dhd_base_addr_htolpa(&base_addr, prot->d2h_dma_scratch_buf.pa);
++	dhd_bus_cmn_writeshared(dhd->bus, &base_addr, sizeof(base_addr),
++		D2H_DMA_SCRATCH_BUF, 0);
++	dhd_bus_cmn_writeshared(dhd->bus, &prot->d2h_dma_scratch_buf.len,
++		sizeof(prot->d2h_dma_scratch_buf.len), D2H_DMA_SCRATCH_BUF_LEN, 0);
++
++	/* If supported by the host, indicate the memory block
++	 * for completion writes / submission reads to shared space
++	 */
++	if (DMA_INDX_ENAB(dhd->dma_d2h_ring_upd_support)) {
++		dhd_base_addr_htolpa(&base_addr, prot->d2h_dma_indx_wr_buf.pa);
++		dhd_bus_cmn_writeshared(dhd->bus, &base_addr, sizeof(base_addr),
++			D2H_DMA_INDX_WR_BUF, 0);
++		dhd_base_addr_htolpa(&base_addr, prot->h2d_dma_indx_rd_buf.pa);
++		dhd_bus_cmn_writeshared(dhd->bus, &base_addr, sizeof(base_addr),
++			H2D_DMA_INDX_RD_BUF, 0);
++	}
++
++	if (DMA_INDX_ENAB(dhd->dma_h2d_ring_upd_support)) {
++		dhd_base_addr_htolpa(&base_addr, prot->h2d_dma_indx_wr_buf.pa);
++		dhd_bus_cmn_writeshared(dhd->bus, &base_addr, sizeof(base_addr),
++			H2D_DMA_INDX_WR_BUF, 0);
++		dhd_base_addr_htolpa(&base_addr, prot->d2h_dma_indx_rd_buf.pa);
++		dhd_bus_cmn_writeshared(dhd->bus, &base_addr, sizeof(base_addr),
++			D2H_DMA_INDX_RD_BUF, 0);
++	}
++
++	/*
++	 * If the DMA-able buffers for flowring needs to come from a specific
++	 * contiguous memory region, then setup prot->flowrings_dma_buf here.
++	 * dhd_prot_flowrings_pool_attach() will carve out DMA-able buffers from
++	 * this contiguous memory region, for each of the flowrings.
++	 */
++
++	/* Pre-allocate pool of msgbuf_ring for flowrings */
++	if (dhd_prot_flowrings_pool_attach(dhd) != BCME_OK) {
++		return BCME_ERROR;
++	}
++
++	/* Host should configure soft doorbells if needed ... here */
++
++	/* Post to dongle host configured soft doorbells */
++	dhd_msgbuf_ring_config_d2h_soft_doorbell(dhd);
++
++	/* Post buffers for packet reception and ioctl/event responses */
++	dhd_msgbuf_rxbuf_post(dhd, FALSE); /* alloc pkt ids */
++	dhd_msgbuf_rxbuf_post_ioctlresp_bufs(dhd);
++	dhd_msgbuf_rxbuf_post_event_bufs(dhd);
++
++	return BCME_OK;
++} /* dhd_prot_init */
++
++
++/**
++ * dhd_prot_detach - PCIE FD protocol layer destructor.
++ * Unlink, frees allocated protocol memory (including dhd_prot)
++ */
++void
++dhd_prot_detach(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++
++	/* Stop the protocol module */
++	if (prot) {
++
++		/* free up all DMA-able buffers allocated during prot attach/init */
++
++		dhd_dma_buf_free(dhd, &prot->d2h_dma_scratch_buf);
++		dhd_dma_buf_free(dhd, &prot->retbuf); /* ioctl return buffer */
++		dhd_dma_buf_free(dhd, &prot->ioctbuf);
++		dhd_dma_buf_free(dhd, &prot->host_bus_throughput_buf);
++
++		/* DMA-able buffers for DMAing H2D/D2H WR/RD indices */
++		dhd_dma_buf_free(dhd, &prot->h2d_dma_indx_wr_buf);
++		dhd_dma_buf_free(dhd, &prot->h2d_dma_indx_rd_buf);
++		dhd_dma_buf_free(dhd, &prot->d2h_dma_indx_wr_buf);
++		dhd_dma_buf_free(dhd, &prot->d2h_dma_indx_rd_buf);
++
++		/* Common MsgBuf Rings */
++		dhd_prot_ring_detach(dhd, &prot->h2dring_ctrl_subn);
++		dhd_prot_ring_detach(dhd, &prot->h2dring_rxp_subn);
++		dhd_prot_ring_detach(dhd, &prot->d2hring_ctrl_cpln);
++		dhd_prot_ring_detach(dhd, &prot->d2hring_tx_cpln);
++		dhd_prot_ring_detach(dhd, &prot->d2hring_rx_cpln);
++
++		/* Detach each DMA-able buffer and free the pool of msgbuf_ring_t */
++		dhd_prot_flowrings_pool_detach(dhd);
++
++		if (dhd->prot->pktid_map_handle) {
++			DHD_NATIVE_TO_PKTID_FINI(dhd, dhd->prot->pktid_map_handle);
++		}
++
++#ifndef CONFIG_DHD_USE_STATIC_BUF
++		MFREE(dhd->osh, dhd->prot, sizeof(dhd_prot_t));
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++
++#if defined(DHD_LB)
++#if defined(DHD_LB_TXC)
++		if (prot->tx_compl_prod.buffer) {
++			MFREE(dhd->osh, prot->tx_compl_prod.buffer,
++				sizeof(void*) * DHD_LB_WORKQ_SZ);
++		}
++#endif /* DHD_LB_TXC */
++#if defined(DHD_LB_RXC)
++		if (prot->rx_compl_prod.buffer) {
++			MFREE(dhd->osh, prot->rx_compl_prod.buffer,
++				sizeof(void*) * DHD_LB_WORKQ_SZ);
++		}
++#endif /* DHD_LB_RXC */
++#endif /* DHD_LB */
++
++		dhd->prot = NULL;
++	}
++} /* dhd_prot_detach */
++
++
++/**
++ * dhd_prot_reset - Reset the protocol layer without freeing any objects. This
++ * may be invoked to soft reboot the dongle, without having to detach and attach
++ * the entire protocol layer.
++ *
++ * After dhd_prot_reset(), dhd_prot_init() may be invoked without going through
++ * a dhd_prot_attach() phase.
++ */
++void
++dhd_prot_reset(dhd_pub_t *dhd)
++{
++	struct dhd_prot *prot = dhd->prot;
++
++	DHD_TRACE(("%s\n", __FUNCTION__));
++
++	if (prot == NULL) {
++		return;
++	}
++
++	dhd_prot_flowrings_pool_reset(dhd);
++
++	dhd_prot_ring_reset(dhd, &prot->h2dring_ctrl_subn);
++	dhd_prot_ring_reset(dhd, &prot->h2dring_rxp_subn);
++	dhd_prot_ring_reset(dhd, &prot->d2hring_ctrl_cpln);
++	dhd_prot_ring_reset(dhd, &prot->d2hring_tx_cpln);
++	dhd_prot_ring_reset(dhd, &prot->d2hring_rx_cpln);
++
++	dhd_dma_buf_reset(dhd, &prot->retbuf);
++	dhd_dma_buf_reset(dhd, &prot->ioctbuf);
++	dhd_dma_buf_reset(dhd, &prot->d2h_dma_scratch_buf);
++	dhd_dma_buf_reset(dhd, &prot->h2d_dma_indx_rd_buf);
++	dhd_dma_buf_reset(dhd, &prot->h2d_dma_indx_wr_buf);
++	dhd_dma_buf_reset(dhd, &prot->d2h_dma_indx_rd_buf);
++	dhd_dma_buf_reset(dhd, &prot->d2h_dma_indx_wr_buf);
++
++
++	prot->rx_metadata_offset = 0;
++	prot->tx_metadata_offset = 0;
++
++	prot->rxbufpost = 0;
++	prot->cur_event_bufs_posted = 0;
++	prot->cur_ioctlresp_bufs_posted = 0;
++
++	prot->active_tx_count = 0;
++	prot->data_seq_no = 0;
++	prot->ioctl_seq_no = 0;
++	prot->ioctl_state = 0;
++	prot->curr_ioctl_cmd = 0;
++	prot->ioctl_received = IOCTL_WAIT;
++	prot->ioctl_trans_id = 0;
++
++	/* dhd_flow_rings_init is located at dhd_bus_start,
++	 * so when stopping bus, flowrings shall be deleted
++	 */
++	if (dhd->flow_rings_inited) {
++		dhd_flow_rings_deinit(dhd);
++	}
++
++	if (prot->pktid_map_handle) {
++		DHD_NATIVE_TO_PKTID_FINI(dhd, prot->pktid_map_handle);
++		prot->pktid_map_handle = NULL;
++	}
++
++#ifdef IOCTLRESP_USE_CONSTMEM
++	if (prot->pktid_map_handle_ioctl) {
++		DHD_NATIVE_TO_PKTID_FINI_IOCTL(dhd, prot->pktid_map_handle_ioctl);
++		prot->pktid_map_handle_ioctl = NULL;
++	}
++#endif /* IOCTLRESP_USE_CONSTMEM */
++} /* dhd_prot_reset */
++
++
++void
++dhd_prot_rx_dataoffset(dhd_pub_t *dhd, uint32 rx_offset)
++{
++	dhd_prot_t *prot = dhd->prot;
++	prot->rx_dataoffset = rx_offset;
++}
++
++/**
++ * Initialize protocol: sync w/dongle state.
++ * Sets dongle media info (iswl, drv_version, mac address).
++ */
++int
++dhd_sync_with_dongle(dhd_pub_t *dhd)
++{
++	int ret = 0;
++	wlc_rev_info_t revinfo;
++
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	dhd_os_set_ioctl_resp_timeout(IOCTL_RESP_TIMEOUT);
++
++
++
++#ifdef DHD_FW_COREDUMP
++	/* For Android Builds check memdump capability */
++	/* Check the memdump capability */
++	dhd_get_memdump_info(dhd);
++#endif /* DHD_FW_COREDUMP */
++
++	/* Get the device rev info */
++	memset(&revinfo, 0, sizeof(revinfo));
++	ret = dhd_wl_ioctl_cmd(dhd, WLC_GET_REVINFO, &revinfo, sizeof(revinfo), FALSE, 0);
++	if (ret < 0) {
++		DHD_ERROR(("%s: GET revinfo FAILED\n", __FUNCTION__));
++		goto done;
++	}
++	DHD_ERROR(("%s: GET_REVINFO device 0x%x, vendor 0x%x, chipnum 0x%x\n", __FUNCTION__,
++		revinfo.deviceid, revinfo.vendorid, revinfo.chipnum));
++
++	dhd_process_cid_mac(dhd, TRUE);
++
++	ret = dhd_preinit_ioctls(dhd);
++	if (!ret) {
++		dhd_process_cid_mac(dhd, FALSE);
++	}
++
++	/* Always assumes wl for now */
++	dhd->iswl = TRUE;
++done:
++	return ret;
++} /* dhd_sync_with_dongle */
++
++#if defined(DHD_LB)
++
++/* DHD load balancing: deferral of work to another online CPU */
++
++/* DHD_LB_TXC DHD_LB_RXC DHD_LB_RXP dispatchers, in dhd_linux.c */
++extern void dhd_lb_tx_compl_dispatch(dhd_pub_t *dhdp);
++extern void dhd_lb_rx_compl_dispatch(dhd_pub_t *dhdp);
++extern void dhd_lb_rx_napi_dispatch(dhd_pub_t *dhdp);
++
++extern void dhd_lb_rx_pkt_enqueue(dhd_pub_t *dhdp, void *pkt, int ifidx);
++
++/**
++ * dhd_lb_dispatch - load balance by dispatch work to other CPU cores
++ * Note: rx_compl_tasklet is dispatched explicitly.
++ */
++static INLINE void
++dhd_lb_dispatch(dhd_pub_t *dhdp, uint16 ring_idx)
++{
++	switch (ring_idx) {
++
++#if defined(DHD_LB_TXC)
++		case BCMPCIE_D2H_MSGRING_TX_COMPLETE:
++			bcm_workq_prod_sync(&dhdp->prot->tx_compl_prod); /* flush WR index */
++			dhd_lb_tx_compl_dispatch(dhdp); /* dispatch tx_compl_tasklet */
++			break;
++#endif /* DHD_LB_TXC */
++
++		case BCMPCIE_D2H_MSGRING_RX_COMPLETE:
++		{
++#if defined(DHD_LB_RXC)
++			dhd_prot_t *prot = dhdp->prot;
++			/* Schedule the takslet only if we have to */
++			if (prot->rxbufpost <= (prot->max_rxbufpost - RXBUFPOST_THRESHOLD)) {
++				/* flush WR index */
++				bcm_workq_prod_sync(&dhdp->prot->rx_compl_prod);
++				dhd_lb_rx_compl_dispatch(dhdp); /* dispatch rx_compl_tasklet */
++			}
++#endif /* DHD_LB_RXC */
++#if defined(DHD_LB_RXP)
++			dhd_lb_rx_napi_dispatch(dhdp); /* dispatch rx_process_napi */
++#endif /* DHD_LB_RXP */
++			break;
++		}
++		default:
++			break;
++	}
++}
++
++
++#if defined(DHD_LB_TXC)
++/**
++ * DHD load balanced tx completion tasklet handler, that will perform the
++ * freeing of packets on the selected CPU. Packet pointers are delivered to
++ * this tasklet via the tx complete workq.
++ */
++void
++dhd_lb_tx_compl_handler(unsigned long data)
++{
++	int elem_ix;
++	void *pkt, **elem;
++	dmaaddr_t pa;
++	uint32 pa_len;
++	dhd_pub_t *dhd = (dhd_pub_t *)data;
++	dhd_prot_t *prot = dhd->prot;
++	bcm_workq_t *workq = &prot->tx_compl_cons;
++	uint32 count = 0;
++
++	DHD_LB_STATS_TXC_PERCPU_CNT_INCR(dhd);
++
++	while (1) {
++		elem_ix = bcm_ring_cons(WORKQ_RING(workq), DHD_LB_WORKQ_SZ);
++
++		if (elem_ix == BCM_RING_EMPTY) {
++			break;
++		}
++
++		elem = WORKQ_ELEMENT(void *, workq, elem_ix);
++		pkt = *elem;
++
++		DHD_INFO(("%s: tx_compl_cons pkt<%p>\n", __FUNCTION__, pkt));
++
++		OSL_PREFETCH(PKTTAG(pkt));
++		OSL_PREFETCH(pkt);
++
++		pa = DHD_PKTTAG_PA((dhd_pkttag_fr_t *)PKTTAG(pkt));
++		pa_len = DHD_PKTTAG_PA_LEN((dhd_pkttag_fr_t *)PKTTAG(pkt));
++
++		DMA_UNMAP(dhd->osh, pa, pa_len, DMA_RX, pkt, 0);
++
++#if defined(BCMPCIE)
++		dhd_txcomplete(dhd, pkt, true);
++#endif 
++
++		PKTFREE(dhd->osh, pkt, TRUE);
++		count++;
++	}
++
++	/* smp_wmb(); */
++	bcm_workq_cons_sync(workq);
++	DHD_LB_STATS_UPDATE_TXC_HISTO(dhd, count);
++}
++#endif /* DHD_LB_TXC */
++
++#if defined(DHD_LB_RXC)
++void
++dhd_lb_rx_compl_handler(unsigned long data)
++{
++	dhd_pub_t *dhd = (dhd_pub_t *)data;
++	bcm_workq_t *workq = &dhd->prot->rx_compl_cons;
++
++	DHD_LB_STATS_RXC_PERCPU_CNT_INCR(dhd);
++
++	dhd_msgbuf_rxbuf_post(dhd, TRUE); /* re-use pktids */
++	bcm_workq_cons_sync(workq);
++}
++#endif /* DHD_LB_RXC */
++
++#endif /* DHD_LB */
++
++#define DHD_DBG_SHOW_METADATA	0
++
++#if DHD_DBG_SHOW_METADATA
++static void BCMFASTPATH
++dhd_prot_print_metadata(dhd_pub_t *dhd, void *ptr, int len)
++{
++	uint8 tlv_t;
++	uint8 tlv_l;
++	uint8 *tlv_v = (uint8 *)ptr;
++
++	if (len <= BCMPCIE_D2H_METADATA_HDRLEN)
++		return;
++
++	len -= BCMPCIE_D2H_METADATA_HDRLEN;
++	tlv_v += BCMPCIE_D2H_METADATA_HDRLEN;
++
++	while (len > TLV_HDR_LEN) {
++		tlv_t = tlv_v[TLV_TAG_OFF];
++		tlv_l = tlv_v[TLV_LEN_OFF];
++
++		len -= TLV_HDR_LEN;
++		tlv_v += TLV_HDR_LEN;
++		if (len < tlv_l)
++			break;
++		if ((tlv_t == 0) || (tlv_t == WLFC_CTL_TYPE_FILLER))
++			break;
++
++		switch (tlv_t) {
++		case WLFC_CTL_TYPE_TXSTATUS: {
++			uint32 txs;
++			memcpy(&txs, tlv_v, sizeof(uint32));
++			if (tlv_l < (sizeof(wl_txstatus_additional_info_t) + sizeof(uint32))) {
++				printf("METADATA TX_STATUS: %08x\n", txs);
++			} else {
++				wl_txstatus_additional_info_t tx_add_info;
++				memcpy(&tx_add_info, tlv_v + sizeof(uint32),
++					sizeof(wl_txstatus_additional_info_t));
++				printf("METADATA TX_STATUS: %08x WLFCTS[%04x | %08x - %08x - %08x]"
++					" rate = %08x tries = %d - %d\n", txs,
++					tx_add_info.seq, tx_add_info.entry_ts,
++					tx_add_info.enq_ts, tx_add_info.last_ts,
++					tx_add_info.rspec, tx_add_info.rts_cnt,
++					tx_add_info.tx_cnt);
++			}
++			} break;
++
++		case WLFC_CTL_TYPE_RSSI: {
++			if (tlv_l == 1)
++				printf("METADATA RX_RSSI: rssi = %d\n", *tlv_v);
++			else
++				printf("METADATA RX_RSSI[%04x]: rssi = %d snr = %d\n",
++					(*(tlv_v + 3) << 8) | *(tlv_v + 2),
++					(int8)(*tlv_v), *(tlv_v + 1));
++			} break;
++
++		case WLFC_CTL_TYPE_FIFO_CREDITBACK:
++			bcm_print_bytes("METADATA FIFO_CREDITBACK", tlv_v, tlv_l);
++			break;
++
++		case WLFC_CTL_TYPE_TX_ENTRY_STAMP:
++			bcm_print_bytes("METADATA TX_ENTRY", tlv_v, tlv_l);
++			break;
++
++		case WLFC_CTL_TYPE_RX_STAMP: {
++			struct {
++				uint32 rspec;
++				uint32 bus_time;
++				uint32 wlan_time;
++			} rx_tmstamp;
++			memcpy(&rx_tmstamp, tlv_v, sizeof(rx_tmstamp));
++			printf("METADATA RX TIMESTMAP: WLFCTS[%08x - %08x] rate = %08x\n",
++				rx_tmstamp.wlan_time, rx_tmstamp.bus_time, rx_tmstamp.rspec);
++			} break;
++
++		case WLFC_CTL_TYPE_TRANS_ID:
++			bcm_print_bytes("METADATA TRANS_ID", tlv_v, tlv_l);
++			break;
++
++		case WLFC_CTL_TYPE_COMP_TXSTATUS:
++			bcm_print_bytes("METADATA COMP_TXSTATUS", tlv_v, tlv_l);
++			break;
++
++		default:
++			bcm_print_bytes("METADATA UNKNOWN", tlv_v, tlv_l);
++			break;
++		}
++
++		len -= tlv_l;
++		tlv_v += tlv_l;
++	}
++}
++#endif /* DHD_DBG_SHOW_METADATA */
++
++static INLINE void BCMFASTPATH
++dhd_prot_packet_free(dhd_pub_t *dhd, void *pkt, uint8 pkttype, bool send)
++{
++	if (pkt) {
++		if (pkttype == PKTTYPE_IOCTL_RX ||
++			pkttype == PKTTYPE_EVENT_RX) {
++#ifdef DHD_USE_STATIC_CTRLBUF
++			PKTFREE_STATIC(dhd->osh, pkt, send);
++#else
++			PKTFREE(dhd->osh, pkt, send);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++		} else {
++			PKTFREE(dhd->osh, pkt, send);
++		}
++	}
++}
++
++static INLINE void * BCMFASTPATH
++dhd_prot_packet_get(dhd_pub_t *dhd, uint32 pktid, uint8 pkttype, bool free_pktid)
++{
++	void *PKTBUF;
++	dmaaddr_t pa;
++	uint32 len;
++	void *dmah;
++	void *secdma;
++
++#ifdef DHD_PCIE_PKTID
++	if (free_pktid) {
++		PKTBUF = DHD_PKTID_TO_NATIVE(dhd, dhd->prot->pktid_map_handle,
++			pktid, pa, len, dmah, secdma, pkttype);
++	} else {
++		PKTBUF = DHD_PKTID_TO_NATIVE_RSV(dhd, dhd->prot->pktid_map_handle,
++			pktid, pa, len, dmah, secdma, pkttype);
++	}
++#else
++	PKTBUF = DHD_PKTID_TO_NATIVE(dhd, dhd->prot->pktid_map_handle, pktid, pa,
++		len, dmah, secdma, pkttype);
++#endif /* DHD_PCIE_PKTID */
++
++	if (PKTBUF) {
++		{
++			if (SECURE_DMA_ENAB(dhd->osh)) {
++				SECURE_DMA_UNMAP(dhd->osh, pa, (uint) len, DMA_RX, 0, dmah,
++					secdma, 0);
++			} else {
++				DMA_UNMAP(dhd->osh, pa, (uint) len, DMA_RX, PKTBUF, dmah);
++			}
++		}
++	}
++
++	return PKTBUF;
++}
++
++#ifdef IOCTLRESP_USE_CONSTMEM
++static INLINE void BCMFASTPATH
++dhd_prot_ioctl_ret_buffer_get(dhd_pub_t *dhd, uint32 pktid, dhd_dma_buf_t *retbuf)
++{
++	memset(retbuf, 0, sizeof(dhd_dma_buf_t));
++	retbuf->va = DHD_PKTID_TO_NATIVE(dhd, dhd->prot->pktid_map_handle_ioctl, pktid,
++		retbuf->pa, retbuf->len, retbuf->dmah, retbuf->secdma, PKTTYPE_IOCTL_RX);
++
++	return;
++}
++#endif /* IOCTLRESP_USE_CONSTMEM */
++
++static void BCMFASTPATH
++dhd_msgbuf_rxbuf_post(dhd_pub_t *dhd, bool use_rsv_pktid)
++{
++	dhd_prot_t *prot = dhd->prot;
++	int16 fillbufs;
++	uint16 cnt = 256;
++	int retcount = 0;
++
++	fillbufs = prot->max_rxbufpost - prot->rxbufpost;
++	while (fillbufs >= RX_BUF_BURST) {
++		cnt--;
++		if (cnt == 0) {
++			/* find a better way to reschedule rx buf post if space not available */
++			DHD_ERROR(("h2d rx post ring not available to post host buffers \n"));
++			DHD_ERROR(("Current posted host buf count %d \n", prot->rxbufpost));
++			break;
++		}
++
++		/* Post in a burst of 32 buffers at a time */
++		fillbufs = MIN(fillbufs, RX_BUF_BURST);
++
++		/* Post buffers */
++		retcount = dhd_prot_rxbuf_post(dhd, fillbufs, use_rsv_pktid);
++
++		if (retcount >= 0) {
++			prot->rxbufpost += (uint16)retcount;
++#ifdef DHD_LB_RXC
++			/* dhd_prot_rxbuf_post returns the number of buffers posted */
++			DHD_LB_STATS_UPDATE_RXC_HISTO(dhd, retcount);
++#endif /* DHD_LB_RXC */
++			/* how many more to post */
++			fillbufs = prot->max_rxbufpost - prot->rxbufpost;
++		} else {
++			/* Make sure we don't run loop any further */
++			fillbufs = 0;
++		}
++	}
++}
++
++/** Post 'count' no of rx buffers to dongle */
++static int BCMFASTPATH
++dhd_prot_rxbuf_post(dhd_pub_t *dhd, uint16 count, bool use_rsv_pktid)
++{
++	void *p;
++	uint16 pktsz = DHD_FLOWRING_RX_BUFPOST_PKTSZ;
++	uint8 *rxbuf_post_tmp;
++	host_rxbuf_post_t *rxbuf_post;
++	void *msg_start;
++	dmaaddr_t pa;
++	uint32 pktlen;
++	uint8 i = 0;
++	uint16 alloced = 0;
++	unsigned long flags;
++	uint32 pktid;
++	dhd_prot_t *prot = dhd->prot;
++	msgbuf_ring_t *ring = &prot->h2dring_rxp_subn;
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	/* Claim space for exactly 'count' no of messages, for mitigation purpose */
++	msg_start = (void *)
++		dhd_prot_alloc_ring_space(dhd, ring, count, &alloced, TRUE);
++
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	if (msg_start == NULL) {
++		DHD_INFO(("%s:%d: Rxbufpost Msgbuf Not available\n", __FUNCTION__, __LINE__));
++		return -1;
++	}
++	/* if msg_start !=  NULL, we should have alloced space for atleast 1 item */
++	ASSERT(alloced > 0);
++
++	rxbuf_post_tmp = (uint8*)msg_start;
++
++	/* loop through each allocated message in the rxbuf post msgbuf_ring */
++	for (i = 0; i < alloced; i++) {
++		rxbuf_post = (host_rxbuf_post_t *)rxbuf_post_tmp;
++		/* Create a rx buffer */
++		if ((p = PKTGET(dhd->osh, pktsz, FALSE)) == NULL) {
++			DHD_ERROR(("%s:%d: PKTGET for rxbuf failed\n", __FUNCTION__, __LINE__));
++			dhd->rx_pktgetfail++;
++			break;
++		}
++
++		pktlen = PKTLEN(dhd->osh, p);
++		if (SECURE_DMA_ENAB(dhd->osh)) {
++			DHD_GENERAL_LOCK(dhd, flags);
++			pa = SECURE_DMA_MAP(dhd->osh, PKTDATA(dhd->osh, p), pktlen,
++				DMA_RX, p, 0, ring->dma_buf.secdma, 0);
++			DHD_GENERAL_UNLOCK(dhd, flags);
++		}
++#ifndef BCM_SECURE_DMA
++		else {
++			pa = DMA_MAP(dhd->osh, PKTDATA(dhd->osh, p), pktlen, DMA_RX, p, 0);
++		}
++#endif /* BCM_SECURE_DMA */
++
++		if (PHYSADDRISZERO(pa)) {
++			if (SECURE_DMA_ENAB(dhd->osh)) {
++				DHD_GENERAL_LOCK(dhd, flags);
++				SECURE_DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, 0, DHD_DMAH_NULL,
++				    ring->dma_buf.secdma, 0);
++				DHD_GENERAL_UNLOCK(dhd, flags);
++			} else {
++				DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, p, DHD_DMAH_NULL);
++			}
++
++			PKTFREE(dhd->osh, p, FALSE);
++			DHD_ERROR(("Invalid phyaddr 0\n"));
++			ASSERT(0);
++			break;
++		}
++
++		PKTPULL(dhd->osh, p, prot->rx_metadata_offset);
++		pktlen = PKTLEN(dhd->osh, p);
++
++		/* Common msg header */
++		rxbuf_post->cmn_hdr.msg_type = MSG_TYPE_RXBUF_POST;
++		rxbuf_post->cmn_hdr.if_id = 0;
++		rxbuf_post->cmn_hdr.epoch = ring->seqnum % H2D_EPOCH_MODULO;
++		ring->seqnum++;
++
++#if defined(DHD_LB_RXC)
++		if (use_rsv_pktid == TRUE) {
++			bcm_workq_t *workq = &prot->rx_compl_cons;
++			int elem_ix = bcm_ring_cons(WORKQ_RING(workq), DHD_LB_WORKQ_SZ);
++			if (elem_ix == BCM_RING_EMPTY) {
++				DHD_ERROR(("%s rx_compl_cons ring is empty\n", __FUNCTION__));
++				pktid = DHD_PKTID_INVALID;
++				goto alloc_pkt_id;
++			} else {
++				uint32 *elem = WORKQ_ELEMENT(uint32, workq, elem_ix);
++				pktid = *elem;
++			}
++
++			/* Now populate the previous locker with valid information */
++			if (pktid != DHD_PKTID_INVALID) {
++				rxbuf_post->cmn_hdr.request_id = htol32(pktid);
++				DHD_NATIVE_TO_PKTID_SAVE(dhd, dhd->prot->pktid_map_handle, p, pktid,
++					pa, pktlen, DMA_RX, NULL, ring->dma_buf.secdma,
++					PKTTYPE_DATA_RX);
++			}
++		} else
++#endif /* DHD_LB_RXC */
++		{
++#if defined(DHD_LB_RXC)
++alloc_pkt_id:
++#endif
++#if defined(DHD_PCIE_PKTID)
++		/* get the lock before calling DHD_NATIVE_TO_PKTID */
++		DHD_GENERAL_LOCK(dhd, flags);
++#endif
++		pktid = DHD_NATIVE_TO_PKTID(dhd, dhd->prot->pktid_map_handle, p, pa,
++			pktlen, DMA_RX, NULL, ring->dma_buf.secdma, PKTTYPE_DATA_RX);
++
++#if defined(DHD_PCIE_PKTID)
++		/* free lock */
++		DHD_GENERAL_UNLOCK(dhd, flags);
++
++		if (pktid == DHD_PKTID_INVALID) {
++
++			if (SECURE_DMA_ENAB(dhd->osh)) {
++				DHD_GENERAL_LOCK(dhd, flags);
++				SECURE_DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, 0, DHD_DMAH_NULL,
++				    ring->dma_buf.secdma, 0);
++				DHD_GENERAL_UNLOCK(dhd, flags);
++			} else {
++				DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, p, DHD_DMAH_NULL);
++			}
++
++			PKTFREE(dhd->osh, p, FALSE);
++			DHD_ERROR(("Pktid pool depleted.\n"));
++			break;
++		}
++#endif /* DHD_PCIE_PKTID */
++		}
++
++		rxbuf_post->data_buf_len = htol16((uint16)pktlen);
++		rxbuf_post->data_buf_addr.high_addr = htol32(PHYSADDRHI(pa));
++		rxbuf_post->data_buf_addr.low_addr =
++			htol32(PHYSADDRLO(pa) + prot->rx_metadata_offset);
++
++		if (prot->rx_metadata_offset) {
++			rxbuf_post->metadata_buf_len = prot->rx_metadata_offset;
++			rxbuf_post->metadata_buf_addr.high_addr = htol32(PHYSADDRHI(pa));
++			rxbuf_post->metadata_buf_addr.low_addr  = htol32(PHYSADDRLO(pa));
++		} else {
++			rxbuf_post->metadata_buf_len = 0;
++			rxbuf_post->metadata_buf_addr.high_addr = 0;
++			rxbuf_post->metadata_buf_addr.low_addr  = 0;
++		}
++
++#if defined(DHD_PKTID_AUDIT_RING)
++		DHD_PKTID_AUDIT(dhd, prot->pktid_map_handle, pktid, DHD_DUPLICATE_ALLOC);
++#endif /* DHD_PKTID_AUDIT_RING */
++
++		rxbuf_post->cmn_hdr.request_id = htol32(pktid);
++
++		/* Move rxbuf_post_tmp to next item */
++		rxbuf_post_tmp = rxbuf_post_tmp + ring->item_len;
++	}
++
++	if (i < alloced) {
++		if (ring->wr < (alloced - i)) {
++			ring->wr = ring->max_items - (alloced - i);
++		} else {
++			ring->wr -= (alloced - i);
++		}
++
++		alloced = i;
++	}
++
++	/* Update ring's WR index and ring doorbell to dongle */
++	if (alloced > 0) {
++		dhd_prot_ring_write_complete(dhd, ring, msg_start, alloced);
++	}
++
++	return alloced;
++} /* dhd_prot_rxbuf_post */
++
++#ifdef IOCTLRESP_USE_CONSTMEM
++static int
++alloc_ioctl_return_buffer(dhd_pub_t *dhd, dhd_dma_buf_t *retbuf)
++{
++	int err;
++	memset(retbuf, 0, sizeof(dhd_dma_buf_t));
++
++	if ((err = dhd_dma_buf_alloc(dhd, retbuf, IOCT_RETBUF_SIZE)) != BCME_OK) {
++		DHD_ERROR(("%s: dhd_dma_buf_alloc err %d\n", __FUNCTION__, err));
++		ASSERT(0);
++		return BCME_NOMEM;
++	}
++
++	return BCME_OK;
++}
++
++static void
++free_ioctl_return_buffer(dhd_pub_t *dhd, dhd_dma_buf_t *retbuf)
++{
++	/* retbuf (declared on stack) not fully populated ...  */
++	if (retbuf->va) {
++		uint32 dma_pad;
++		dma_pad = (IOCT_RETBUF_SIZE % DHD_DMA_PAD) ? DHD_DMA_PAD : 0;
++		retbuf->len = IOCT_RETBUF_SIZE;
++		retbuf->_alloced = retbuf->len + dma_pad;
++		/* JIRA:SWWLAN-70021 The pa value would be overwritten by the dongle.
++		 * Need to reassign before free to pass the check in dhd_dma_buf_audit().
++		 */
++		retbuf->pa = DMA_MAP(dhd->osh, retbuf->va, retbuf->len, DMA_RX, NULL, NULL);
++	}
++
++	dhd_dma_buf_free(dhd, retbuf);
++	return;
++}
++#endif /* IOCTLRESP_USE_CONSTMEM */
++
++static int
++dhd_prot_rxbufpost_ctrl(dhd_pub_t *dhd, bool event_buf)
++{
++	void *p;
++	uint16 pktsz;
++	ioctl_resp_evt_buf_post_msg_t *rxbuf_post;
++	dmaaddr_t pa;
++	uint32 pktlen;
++	dhd_prot_t *prot = dhd->prot;
++	uint16 alloced = 0;
++	unsigned long flags;
++	dhd_dma_buf_t retbuf;
++	void *dmah = NULL;
++	uint32 pktid;
++	void *map_handle;
++	msgbuf_ring_t *ring = &prot->h2dring_ctrl_subn;
++
++	if (dhd->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s: bus is already down.\n", __FUNCTION__));
++		return -1;
++	}
++
++	memset(&retbuf, 0, sizeof(dhd_dma_buf_t));
++
++	if (event_buf) {
++		/* Allocate packet for event buffer post */
++		pktsz = DHD_FLOWRING_RX_BUFPOST_PKTSZ;
++	} else {
++		/* Allocate packet for ctrl/ioctl buffer post */
++		pktsz = DHD_FLOWRING_IOCTL_BUFPOST_PKTSZ;
++	}
++
++#ifdef IOCTLRESP_USE_CONSTMEM
++	if (!event_buf) {
++		if (alloc_ioctl_return_buffer(dhd, &retbuf) != BCME_OK) {
++			DHD_ERROR(("Could not allocate IOCTL response buffer\n"));
++			return -1;
++		}
++		ASSERT(retbuf.len == IOCT_RETBUF_SIZE);
++		p = retbuf.va;
++		pktlen = retbuf.len;
++		pa = retbuf.pa;
++		dmah = retbuf.dmah;
++	} else
++#endif /* IOCTLRESP_USE_CONSTMEM */
++	{
++#ifdef DHD_USE_STATIC_CTRLBUF
++		p = PKTGET_STATIC(dhd->osh, pktsz, FALSE);
++#else
++		p = PKTGET(dhd->osh, pktsz, FALSE);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++		if (p == NULL) {
++			DHD_ERROR(("%s:%d: PKTGET for %s buf failed\n",
++				__FUNCTION__, __LINE__, event_buf ?
++				"EVENT" : "IOCTL RESP"));
++			dhd->rx_pktgetfail++;
++			return -1;
++		}
++
++		pktlen = PKTLEN(dhd->osh, p);
++
++		if (SECURE_DMA_ENAB(dhd->osh)) {
++			DHD_GENERAL_LOCK(dhd, flags);
++			pa = SECURE_DMA_MAP(dhd->osh, PKTDATA(dhd->osh, p), pktlen,
++				DMA_RX, p, 0, ring->dma_buf.secdma, 0);
++			DHD_GENERAL_UNLOCK(dhd, flags);
++		}
++#ifndef BCM_SECURE_DMA
++		else
++			pa = DMA_MAP(dhd->osh, PKTDATA(dhd->osh, p), pktlen, DMA_RX, p, 0);
++#endif /* #ifndef BCM_SECURE_DMA */
++
++		if (PHYSADDRISZERO(pa)) {
++			DHD_ERROR(("Invalid physaddr 0\n"));
++			ASSERT(0);
++			goto free_pkt_return;
++		}
++	}
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	rxbuf_post = (ioctl_resp_evt_buf_post_msg_t *)
++		dhd_prot_alloc_ring_space(dhd, ring, 1, &alloced, FALSE);
++
++	if (rxbuf_post == NULL) {
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		DHD_ERROR(("%s:%d: Ctrl submit Msgbuf Not available to post buffer \n",
++			__FUNCTION__, __LINE__));
++
++#ifdef IOCTLRESP_USE_CONSTMEM
++		if (event_buf)
++#endif /* IOCTLRESP_USE_CONSTMEM */
++		{
++			if (SECURE_DMA_ENAB(dhd->osh)) {
++				DHD_GENERAL_LOCK(dhd, flags);
++				SECURE_DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, 0, DHD_DMAH_NULL,
++					ring->dma_buf.secdma, 0);
++				DHD_GENERAL_UNLOCK(dhd, flags);
++			} else {
++				DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, p, DHD_DMAH_NULL);
++			}
++		}
++		goto free_pkt_return;
++	}
++
++	/* CMN msg header */
++	if (event_buf) {
++		rxbuf_post->cmn_hdr.msg_type = MSG_TYPE_EVENT_BUF_POST;
++	} else {
++		rxbuf_post->cmn_hdr.msg_type = MSG_TYPE_IOCTLRESP_BUF_POST;
++	}
++
++#ifdef IOCTLRESP_USE_CONSTMEM
++	if (!event_buf) {
++		map_handle = dhd->prot->pktid_map_handle_ioctl;
++		pktid =	DHD_NATIVE_TO_PKTID(dhd, map_handle, p, pa, pktlen,
++			DMA_RX, dmah, ring->dma_buf.secdma, PKTTYPE_IOCTL_RX);
++	} else
++#endif /* IOCTLRESP_USE_CONSTMEM */
++	{
++		map_handle = dhd->prot->pktid_map_handle;
++		pktid =	DHD_NATIVE_TO_PKTID(dhd, map_handle,
++			p, pa, pktlen, DMA_RX, dmah, ring->dma_buf.secdma,
++			event_buf ? PKTTYPE_EVENT_RX : PKTTYPE_IOCTL_RX);
++	}
++
++	if (pktid == DHD_PKTID_INVALID) {
++		if (ring->wr == 0) {
++			ring->wr = ring->max_items - 1;
++		} else {
++			ring->wr--;
++		}
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, p, DHD_DMAH_NULL);
++		goto free_pkt_return;
++	}
++
++#if defined(DHD_PKTID_AUDIT_RING)
++	DHD_PKTID_AUDIT(dhd, map_handle, pktid, DHD_DUPLICATE_ALLOC);
++#endif /* DHD_PKTID_AUDIT_RING */
++
++	rxbuf_post->cmn_hdr.request_id = htol32(pktid);
++	rxbuf_post->cmn_hdr.if_id = 0;
++	rxbuf_post->cmn_hdr.epoch = ring->seqnum % H2D_EPOCH_MODULO;
++	ring->seqnum++;
++
++#if defined(DHD_PCIE_PKTID)
++	if (rxbuf_post->cmn_hdr.request_id == DHD_PKTID_INVALID) {
++		if (ring->wr == 0) {
++			ring->wr = ring->max_items - 1;
++		} else {
++			ring->wr--;
++		}
++		DHD_GENERAL_UNLOCK(dhd, flags);
++#ifdef IOCTLRESP_USE_CONSTMEM
++		if (event_buf)
++#endif /* IOCTLRESP_USE_CONSTMEM */
++		{
++			if (SECURE_DMA_ENAB(dhd->osh)) {
++				DHD_GENERAL_LOCK(dhd, flags);
++				SECURE_DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, 0, DHD_DMAH_NULL,
++					ring->dma_buf.secdma, 0);
++				DHD_GENERAL_UNLOCK(dhd, flags);
++			} else {
++				DMA_UNMAP(dhd->osh, pa, pktlen, DMA_RX, p, DHD_DMAH_NULL);
++			}
++		}
++		goto free_pkt_return;
++	}
++#endif /* DHD_PCIE_PKTID */
++
++	rxbuf_post->cmn_hdr.flags = 0;
++#ifndef IOCTLRESP_USE_CONSTMEM
++	rxbuf_post->host_buf_len = htol16((uint16)PKTLEN(dhd->osh, p));
++#else
++	rxbuf_post->host_buf_len = htol16((uint16)pktlen);
++#endif /* IOCTLRESP_USE_CONSTMEM */
++	rxbuf_post->host_buf_addr.high_addr = htol32(PHYSADDRHI(pa));
++	rxbuf_post->host_buf_addr.low_addr  = htol32(PHYSADDRLO(pa));
++
++	/* update ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ring, rxbuf_post, 1);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	return 1;
++
++free_pkt_return:
++#ifdef IOCTLRESP_USE_CONSTMEM
++	if (!event_buf) {
++		free_ioctl_return_buffer(dhd, &retbuf);
++	} else
++#endif /* IOCTLRESP_USE_CONSTMEM */
++	{
++		dhd_prot_packet_free(dhd, p,
++			event_buf ? PKTTYPE_EVENT_RX : PKTTYPE_IOCTL_RX,
++			FALSE);
++	}
++
++	return -1;
++} /* dhd_prot_rxbufpost_ctrl */
++
++static uint16
++dhd_msgbuf_rxbuf_post_ctrlpath(dhd_pub_t *dhd, bool event_buf, uint32 max_to_post)
++{
++	uint32 i = 0;
++	int32 ret_val;
++
++	DHD_INFO(("max to post %d, event %d \n", max_to_post, event_buf));
++
++	if (dhd->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s: bus is already down.\n", __FUNCTION__));
++		return 0;
++	}
++
++	while (i < max_to_post) {
++		ret_val  = dhd_prot_rxbufpost_ctrl(dhd, event_buf);
++		if (ret_val < 0) {
++			break;
++		}
++		i++;
++	}
++	DHD_INFO(("posted %d buffers to event_pool/ioctl_resp_pool %d\n", i, event_buf));
++	return (uint16)i;
++}
++
++static void
++dhd_msgbuf_rxbuf_post_ioctlresp_bufs(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	int max_to_post;
++
++	DHD_INFO(("ioctl resp buf post\n"));
++	max_to_post = prot->max_ioctlrespbufpost - prot->cur_ioctlresp_bufs_posted;
++	if (max_to_post <= 0) {
++		DHD_INFO(("%s: Cannot post more than max IOCTL resp buffers\n",
++			__FUNCTION__));
++		return;
++	}
++	prot->cur_ioctlresp_bufs_posted += dhd_msgbuf_rxbuf_post_ctrlpath(dhd,
++		FALSE, max_to_post);
++}
++
++static void
++dhd_msgbuf_rxbuf_post_event_bufs(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	int max_to_post;
++
++	max_to_post = prot->max_eventbufpost - prot->cur_event_bufs_posted;
++	if (max_to_post <= 0) {
++		DHD_INFO(("%s: Cannot post more than max event buffers\n",
++			__FUNCTION__));
++		return;
++	}
++	prot->cur_event_bufs_posted += dhd_msgbuf_rxbuf_post_ctrlpath(dhd,
++		TRUE, max_to_post);
++}
++
++/** called when DHD needs to check for 'receive complete' messages from the dongle */
++bool BCMFASTPATH
++dhd_prot_process_msgbuf_rxcpl(dhd_pub_t *dhd, uint bound)
++{
++	bool more = TRUE;
++	uint n = 0;
++	msgbuf_ring_t *ring = &dhd->prot->d2hring_rx_cpln;
++
++	/* Process all the messages - DTOH direction */
++	while (!dhd_is_device_removed(dhd)) {
++		uint8 *msg_addr;
++		uint32 msg_len;
++
++		if (dhd->hang_was_sent) {
++			more = FALSE;
++			break;
++		}
++
++		/* Get the address of the next message to be read from ring */
++		msg_addr = dhd_prot_get_read_addr(dhd, ring, &msg_len);
++		if (msg_addr == NULL) {
++			more = FALSE;
++			break;
++		}
++
++		/* Prefetch data to populate the cache */
++		OSL_PREFETCH(msg_addr);
++
++		if (dhd_prot_process_msgtype(dhd, ring, msg_addr, msg_len) != BCME_OK) {
++			DHD_ERROR(("%s: process %s msg addr %p len %d\n",
++				__FUNCTION__, ring->name, msg_addr, msg_len));
++		}
++
++		/* Update read pointer */
++		dhd_prot_upd_read_idx(dhd, ring);
++
++		/* After batch processing, check RX bound */
++		n += msg_len / ring->item_len;
++		if (n >= bound) {
++			break;
++		}
++	}
++
++	return more;
++}
++
++/**
++ * Hands transmit packets (with a caller provided flow_id) over to dongle territory (the flow ring)
++ */
++void
++dhd_prot_update_txflowring(dhd_pub_t *dhd, uint16 flowid, void *msgring)
++{
++	msgbuf_ring_t *ring = (msgbuf_ring_t *)msgring;
++
++	/* Update read pointer */
++	if (DMA_INDX_ENAB(dhd->dma_d2h_ring_upd_support)) {
++		ring->rd = dhd_prot_dma_indx_get(dhd, H2D_DMA_INDX_RD_UPD, ring->idx);
++	}
++
++	DHD_TRACE(("ringid %d flowid %d write %d read %d \n\n",
++		ring->idx, flowid, ring->wr, ring->rd));
++
++	/* Need more logic here, but for now use it directly */
++	dhd_bus_schedule_queue(dhd->bus, flowid, TRUE); /* from queue to flowring */
++}
++
++/** called when DHD needs to check for 'transmit complete' messages from the dongle */
++bool BCMFASTPATH
++dhd_prot_process_msgbuf_txcpl(dhd_pub_t *dhd, uint bound)
++{
++	bool more = TRUE;
++	uint n = 0;
++	msgbuf_ring_t *ring = &dhd->prot->d2hring_tx_cpln;
++
++	/* Process all the messages - DTOH direction */
++	while (!dhd_is_device_removed(dhd)) {
++		uint8 *msg_addr;
++		uint32 msg_len;
++
++		if (dhd->hang_was_sent) {
++			more = FALSE;
++			break;
++		}
++
++		/* Get the address of the next message to be read from ring */
++		msg_addr = dhd_prot_get_read_addr(dhd, ring, &msg_len);
++		if (msg_addr == NULL) {
++			more = FALSE;
++			break;
++		}
++
++		/* Prefetch data to populate the cache */
++		OSL_PREFETCH(msg_addr);
++
++		if (dhd_prot_process_msgtype(dhd, ring, msg_addr, msg_len) != BCME_OK) {
++			DHD_ERROR(("%s: process %s msg addr %p len %d\n",
++				__FUNCTION__, ring->name, msg_addr, msg_len));
++		}
++
++		/* Write to dngl rd ptr */
++		dhd_prot_upd_read_idx(dhd, ring);
++
++		/* After batch processing, check bound */
++		n += msg_len / ring->item_len;
++		if (n >= bound) {
++			break;
++		}
++	}
++
++	return more;
++}
++
++/** called when DHD needs to check for 'ioctl complete' messages from the dongle */
++int BCMFASTPATH
++dhd_prot_process_ctrlbuf(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	msgbuf_ring_t *ring = &prot->d2hring_ctrl_cpln;
++
++	/* Process all the messages - DTOH direction */
++	while (!dhd_is_device_removed(dhd)) {
++		uint8 *msg_addr;
++		uint32 msg_len;
++
++		if (dhd->hang_was_sent) {
++			break;
++		}
++
++		/* Get the address of the next message to be read from ring */
++		msg_addr = dhd_prot_get_read_addr(dhd, ring, &msg_len);
++		if (msg_addr == NULL) {
++			break;
++		}
++
++		/* Prefetch data to populate the cache */
++		OSL_PREFETCH(msg_addr);
++		if (dhd_prot_process_msgtype(dhd, ring, msg_addr, msg_len) != BCME_OK) {
++			DHD_ERROR(("%s: process %s msg addr %p len %d\n",
++				__FUNCTION__, ring->name, msg_addr, msg_len));
++		}
++
++		/* Write to dngl rd ptr */
++		dhd_prot_upd_read_idx(dhd, ring);
++	}
++
++	return 0;
++}
++
++/**
++ * Consume messages out of the D2H ring. Ensure that the message's DMA to host
++ * memory has completed, before invoking the message handler via a table lookup
++ * of the cmn_msg_hdr::msg_type.
++ */
++static int BCMFASTPATH
++dhd_prot_process_msgtype(dhd_pub_t *dhd, msgbuf_ring_t *ring, uint8 *buf, uint32 len)
++{
++	int buf_len = len;
++	uint16 item_len;
++	uint8 msg_type;
++	cmn_msg_hdr_t *msg = NULL;
++	int ret = BCME_OK;
++
++	ASSERT(ring);
++	item_len = ring->item_len;
++	if (item_len == 0) {
++		DHD_ERROR(("%s: ringidx %d item_len %d buf_len %d\n",
++			__FUNCTION__, ring->idx, item_len, buf_len));
++		return BCME_ERROR;
++	}
++
++	while (buf_len > 0) {
++		if (dhd->hang_was_sent) {
++			ret = BCME_ERROR;
++			goto done;
++		}
++
++		msg = (cmn_msg_hdr_t *)buf;
++
++#if defined(PCIE_D2H_SYNC)
++		/* Wait until DMA completes, then fetch msg_type */
++		msg_type = dhd->prot->d2h_sync_cb(dhd, ring, msg, item_len);
++#else
++		msg_type = msg->msg_type;
++#endif /* !PCIE_D2H_SYNC */
++
++		/* Prefetch data to populate the cache */
++		OSL_PREFETCH(buf + item_len);
++
++		DHD_INFO(("msg_type %d item_len %d buf_len %d\n",
++			msg_type, item_len, buf_len));
++
++		if (msg_type == MSG_TYPE_LOOPBACK) {
++			bcm_print_bytes("LPBK RESP: ", (uint8 *)msg, item_len);
++			DHD_ERROR((" MSG_TYPE_LOOPBACK, len %d\n", item_len));
++		}
++
++		ASSERT(msg_type < DHD_PROT_FUNCS);
++		if (msg_type >= DHD_PROT_FUNCS) {
++			DHD_ERROR(("%s: msg_type %d item_len %d buf_len %d\n",
++				__FUNCTION__, msg_type, item_len, buf_len));
++			ret = BCME_ERROR;
++			goto done;
++		}
++
++		if (table_lookup[msg_type]) {
++			table_lookup[msg_type](dhd, buf);
++		}
++
++		if (buf_len < item_len) {
++			ret = BCME_ERROR;
++			goto done;
++		}
++		buf_len = buf_len - item_len;
++		buf = buf + item_len;
++	}
++
++done:
++
++#ifdef DHD_RX_CHAINING
++	dhd_rxchain_commit(dhd);
++#endif
++#if defined(DHD_LB)
++	dhd_lb_dispatch(dhd, ring->idx);
++#endif
++	return ret;
++} /* dhd_prot_process_msgtype */
++
++static void
++dhd_prot_noop(dhd_pub_t *dhd, void *msg)
++{
++	return;
++}
++
++/** called on MSG_TYPE_RING_STATUS message received from dongle */
++static void
++dhd_prot_ringstatus_process(dhd_pub_t *dhd, void *msg)
++{
++	pcie_ring_status_t *ring_status = (pcie_ring_status_t *)msg;
++	DHD_ERROR(("ring status: request_id %d, status 0x%04x, flow ring %d, write_idx %d \n",
++		ring_status->cmn_hdr.request_id, ring_status->compl_hdr.status,
++		ring_status->compl_hdr.flow_ring_id, ring_status->write_idx));
++	/* How do we track this to pair it with ??? */
++	return;
++}
++
++/** called on MSG_TYPE_GEN_STATUS ('general status') message received from dongle */
++static void
++dhd_prot_genstatus_process(dhd_pub_t *dhd, void *msg)
++{
++	pcie_gen_status_t *gen_status = (pcie_gen_status_t *)msg;
++	DHD_ERROR(("ERROR: gen status: request_id %d, STATUS 0x%04x, flow ring %d \n",
++		gen_status->cmn_hdr.request_id, gen_status->compl_hdr.status,
++		gen_status->compl_hdr.flow_ring_id));
++
++	/* How do we track this to pair it with ??? */
++	return;
++}
++
++/**
++ * Called on MSG_TYPE_IOCTLPTR_REQ_ACK ('ioctl ack') message received from dongle, meaning that the
++ * dongle received the ioctl message in dongle memory.
++ */
++static void
++dhd_prot_ioctack_process(dhd_pub_t *dhd, void *msg)
++{
++	uint32 pktid;
++	ioctl_req_ack_msg_t *ioct_ack = (ioctl_req_ack_msg_t *)msg;
++	unsigned long flags;
++
++	pktid = ltoh32(ioct_ack->cmn_hdr.request_id);
++
++#if defined(DHD_PKTID_AUDIT_RING)
++	/* Skip DHD_IOCTL_REQ_PKTID = 0xFFFE */
++	if (pktid != DHD_IOCTL_REQ_PKTID) {
++		DHD_PKTID_AUDIT(dhd, dhd->prot->pktid_map_handle, pktid,
++			DHD_TEST_IS_ALLOC);
++	}
++#endif /* DHD_PKTID_AUDIT_RING */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++	if ((dhd->prot->ioctl_state & MSGBUF_IOCTL_ACK_PENDING) &&
++		(dhd->prot->ioctl_state & MSGBUF_IOCTL_RESP_PENDING)) {
++		dhd->prot->ioctl_state &= ~MSGBUF_IOCTL_ACK_PENDING;
++	} else {
++		DHD_ERROR(("%s: received ioctl ACK with state %02x trans_id = %d\n",
++			__FUNCTION__, dhd->prot->ioctl_state, dhd->prot->ioctl_trans_id));
++	}
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	DHD_CTL(("ioctl req ack: request_id %d, status 0x%04x, flow ring %d \n",
++		ioct_ack->cmn_hdr.request_id, ioct_ack->compl_hdr.status,
++		ioct_ack->compl_hdr.flow_ring_id));
++	if (ioct_ack->compl_hdr.status != 0)  {
++		DHD_ERROR(("got an error status for the ioctl request...need to handle that\n"));
++	}
++}
++
++/** called on MSG_TYPE_IOCTL_CMPLT message received from dongle */
++static void
++dhd_prot_ioctcmplt_process(dhd_pub_t *dhd, void *msg)
++{
++	dhd_prot_t *prot = dhd->prot;
++	uint32 pkt_id, xt_id;
++	ioctl_comp_resp_msg_t *ioct_resp = (ioctl_comp_resp_msg_t *)msg;
++	void *pkt;
++	unsigned long flags;
++	dhd_dma_buf_t retbuf;
++
++	memset(&retbuf, 0, sizeof(dhd_dma_buf_t));
++
++	pkt_id = ltoh32(ioct_resp->cmn_hdr.request_id);
++
++#if defined(DHD_PKTID_AUDIT_RING)
++#ifndef IOCTLRESP_USE_CONSTMEM
++	DHD_PKTID_AUDIT(dhd, prot->pktid_map_handle, pkt_id, DHD_DUPLICATE_FREE);
++#else
++	DHD_PKTID_AUDIT(dhd, prot->pktid_map_handle_ioctl, pkt_id, DHD_DUPLICATE_FREE);
++#endif /* !IOCTLRESP_USE_CONSTMEM */
++#endif /* DHD_PKTID_AUDIT_RING */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++	if ((prot->ioctl_state & MSGBUF_IOCTL_ACK_PENDING) ||
++		!(prot->ioctl_state & MSGBUF_IOCTL_RESP_PENDING)) {
++		DHD_ERROR(("%s: received ioctl response with state %02x trans_id = %d\n",
++			__FUNCTION__, dhd->prot->ioctl_state, dhd->prot->ioctl_trans_id));
++		/* reset ioctl state */
++		prot->ioctl_state = 0;
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		return;
++	}
++#ifndef IOCTLRESP_USE_CONSTMEM
++	pkt = dhd_prot_packet_get(dhd, pkt_id, PKTTYPE_IOCTL_RX, TRUE);
++#else
++	dhd_prot_ioctl_ret_buffer_get(dhd, pkt_id, &retbuf);
++	pkt = retbuf.va;
++#endif /* !IOCTLRESP_USE_CONSTMEM */
++	if (!pkt) {
++		prot->ioctl_state = 0;
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		DHD_ERROR(("%s: received ioctl response with NULL pkt\n", __FUNCTION__));
++		return;
++	}
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	prot->ioctl_resplen = ltoh16(ioct_resp->resp_len);
++	prot->ioctl_status = ltoh16(ioct_resp->compl_hdr.status);
++	xt_id = ltoh16(ioct_resp->trans_id);
++	if (xt_id != prot->ioctl_trans_id) {
++		ASSERT(0);
++		goto exit;
++	}
++
++	DHD_CTL(("IOCTL_COMPLETE: req_id %x transid %d status %x resplen %d\n",
++		pkt_id, xt_id, prot->ioctl_status, prot->ioctl_resplen));
++
++	if (prot->ioctl_resplen > 0) {
++#ifndef IOCTLRESP_USE_CONSTMEM
++		bcopy(PKTDATA(dhd->osh, pkt), prot->retbuf.va, prot->ioctl_resplen);
++#else
++		bcopy(pkt, prot->retbuf.va, prot->ioctl_resplen);
++#endif /* !IOCTLRESP_USE_CONSTMEM */
++	}
++
++	/* wake up any dhd_os_ioctl_resp_wait() */
++	dhd_wakeup_ioctl_event(dhd, IOCTL_RETURN_ON_SUCCESS);
++
++exit:
++#ifndef IOCTLRESP_USE_CONSTMEM
++	dhd_prot_packet_free(dhd, pkt,
++		PKTTYPE_IOCTL_RX, FALSE);
++#else
++	free_ioctl_return_buffer(dhd, &retbuf);
++#endif /* !IOCTLRESP_USE_CONSTMEM */
++}
++
++/** called on MSG_TYPE_TX_STATUS message received from dongle */
++static void BCMFASTPATH
++dhd_prot_txstatus_process(dhd_pub_t *dhd, void *msg)
++{
++	dhd_prot_t *prot = dhd->prot;
++	host_txbuf_cmpl_t * txstatus;
++	unsigned long flags;
++	uint32 pktid;
++	void *pkt = NULL;
++	ulong pa;
++	uint32 len;
++	void *dmah;
++	void *secdma;
++
++	/* locks required to protect circular buffer accesses */
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	txstatus = (host_txbuf_cmpl_t *)msg;
++	pktid = ltoh32(txstatus->cmn_hdr.request_id);
++
++#if defined(DHD_PKTID_AUDIT_RING)
++	DHD_PKTID_AUDIT(dhd, dhd->prot->pktid_map_handle, pktid,
++		DHD_DUPLICATE_FREE);
++#endif /* DHD_PKTID_AUDIT_RING */
++
++	DHD_INFO(("txstatus for pktid 0x%04x\n", pktid));
++	if (prot->active_tx_count) {
++		prot->active_tx_count--;
++
++		/* Release the Lock when no more tx packets are pending */
++		if (prot->active_tx_count == 0)
++			 DHD_OS_WAKE_UNLOCK(dhd);
++
++	} else {
++		DHD_ERROR(("Extra packets are freed\n"));
++	}
++
++	ASSERT(pktid != 0);
++
++#if defined(DHD_LB_TXC) && !defined(BCM_SECURE_DMA)
++	{
++		int elem_ix;
++		void **elem;
++		bcm_workq_t *workq;
++
++		pkt = DHD_PKTID_TO_NATIVE(dhd, dhd->prot->pktid_map_handle,
++			pktid, pa, len, dmah, secdma, PKTTYPE_DATA_TX);
++
++		workq = &prot->tx_compl_prod;
++		/*
++		 * Produce the packet into the tx_compl workq for the tx compl tasklet
++		 * to consume.
++		 */
++		OSL_PREFETCH(PKTTAG(pkt));
++
++		/* fetch next available slot in workq */
++		elem_ix = bcm_ring_prod(WORKQ_RING(workq), DHD_LB_WORKQ_SZ);
++
++		DHD_PKTTAG_SET_PA((dhd_pkttag_fr_t *)PKTTAG(pkt), pa);
++		DHD_PKTTAG_SET_PA_LEN((dhd_pkttag_fr_t *)PKTTAG(pkt), len);
++
++		if (elem_ix == BCM_RING_FULL) {
++			DHD_ERROR(("tx_compl_prod BCM_RING_FULL\n"));
++			goto workq_ring_full;
++		}
++
++		elem = WORKQ_ELEMENT(void *, &prot->tx_compl_prod, elem_ix);
++		*elem = pkt;
++
++		smp_wmb();
++
++		/* Sync WR index to consumer if the SYNC threshold has been reached */
++		if (++prot->tx_compl_prod_sync >= DHD_LB_WORKQ_SYNC) {
++			bcm_workq_prod_sync(workq);
++			prot->tx_compl_prod_sync = 0;
++		}
++
++		DHD_INFO(("%s: tx_compl_prod pkt<%p> sync<%d>\n",
++		__FUNCTION__, pkt, prot->tx_compl_prod_sync));
++
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		return;
++	   }
++
++workq_ring_full:
++
++#endif /* !DHD_LB_TXC */
++
++	/*
++	 * We can come here if no DHD_LB_TXC is enabled and in case where DHD_LB_TXC is
++	 * defined but the tx_compl queue is full.
++	 */
++	if (pkt == NULL) {
++		pkt = DHD_PKTID_TO_NATIVE(dhd, dhd->prot->pktid_map_handle,
++			pktid, pa, len, dmah, secdma, PKTTYPE_DATA_TX);
++	}
++
++	if (pkt) {
++		if (SECURE_DMA_ENAB(dhd->osh)) {
++			int offset = 0;
++			BCM_REFERENCE(offset);
++
++			if (dhd->prot->tx_metadata_offset)
++				offset = dhd->prot->tx_metadata_offset + ETHER_HDR_LEN;
++			SECURE_DMA_UNMAP(dhd->osh, (uint) pa,
++				(uint) dhd->prot->tx_metadata_offset, DMA_RX, 0, dmah,
++				secdma, offset);
++		} else {
++			DMA_UNMAP(dhd->osh, pa, (uint) len, DMA_RX, pkt, dmah);
++		}
++#if defined(BCMPCIE)
++		dhd_txcomplete(dhd, pkt, true);
++#endif 
++
++#if DHD_DBG_SHOW_METADATA
++		if (dhd->prot->metadata_dbg &&
++		    dhd->prot->tx_metadata_offset && txstatus->metadata_len) {
++			uchar *ptr;
++			/* The Ethernet header of TX frame was copied and removed.
++			 * Here, move the data pointer forward by Ethernet header size.
++			 */
++			PKTPULL(dhd->osh, pkt, ETHER_HDR_LEN);
++			ptr = PKTDATA(dhd->osh, pkt)  - (dhd->prot->tx_metadata_offset);
++			bcm_print_bytes("txmetadata", ptr, txstatus->metadata_len);
++			dhd_prot_print_metadata(dhd, ptr, txstatus->metadata_len);
++		}
++#endif /* DHD_DBG_SHOW_METADATA */
++#ifndef CUSTOMER_HW_31_2
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		PKTFREE(dhd->osh, pkt, TRUE);
++		DHD_GENERAL_LOCK(dhd, flags);
++#endif /* CUSTOMER_HW_31_2 */
++		DHD_FLOWRING_TXSTATUS_CNT_UPDATE(dhd->bus, txstatus->compl_hdr.flow_ring_id,
++		txstatus->tx_status);
++	}
++
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	return;
++} /* dhd_prot_txstatus_process */
++
++/** called on MSG_TYPE_WL_EVENT message received from dongle */
++static void
++dhd_prot_event_process(dhd_pub_t *dhd, void *msg)
++{
++	wlevent_req_msg_t *evnt;
++	uint32 bufid;
++	uint16 buflen;
++	int ifidx = 0;
++	void* pkt;
++	unsigned long flags;
++	dhd_prot_t *prot = dhd->prot;
++
++	/* Event complete header */
++	evnt = (wlevent_req_msg_t *)msg;
++	bufid = ltoh32(evnt->cmn_hdr.request_id);
++
++#if defined(DHD_PKTID_AUDIT_RING)
++	DHD_PKTID_AUDIT(dhd, dhd->prot->pktid_map_handle, bufid,
++		DHD_DUPLICATE_FREE);
++#endif /* DHD_PKTID_AUDIT_RING */
++
++	buflen = ltoh16(evnt->event_data_len);
++
++	ifidx = BCMMSGBUF_API_IFIDX(&evnt->cmn_hdr);
++
++	/* Post another rxbuf to the device */
++	if (prot->cur_event_bufs_posted) {
++		prot->cur_event_bufs_posted--;
++	}
++	dhd_msgbuf_rxbuf_post_event_bufs(dhd);
++
++	/* locks required to protect pktid_map */
++	DHD_GENERAL_LOCK(dhd, flags);
++	pkt = dhd_prot_packet_get(dhd, bufid, PKTTYPE_EVENT_RX, TRUE);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	if (!pkt) {
++		return;
++	}
++
++	/* DMA RX offset updated through shared area */
++	if (dhd->prot->rx_dataoffset) {
++		PKTPULL(dhd->osh, pkt, dhd->prot->rx_dataoffset);
++	}
++
++	PKTSETLEN(dhd->osh, pkt, buflen);
++
++	dhd_bus_rx_frame(dhd->bus, pkt, ifidx, 1);
++}
++
++extern bool dhd_monitor_enabled(dhd_pub_t *dhd, int ifidx);
++extern void dhd_rx_mon_pkt(dhd_pub_t *dhdp, void *pkt, int ifidx);
++
++/** called on MSG_TYPE_RX_CMPLT message received from dongle */
++static void BCMFASTPATH
++dhd_prot_rxcmplt_process(dhd_pub_t *dhd, void *msg)
++{
++	host_rxbuf_cmpl_t *rxcmplt_h;
++	uint16 data_offset;             /* offset at which data starts */
++	void *pkt;
++	unsigned long flags;
++	uint ifidx;
++	uint32 pktid;
++#if defined(DHD_LB_RXC)
++	const bool free_pktid = FALSE;
++#else
++	const bool free_pktid = TRUE;
++#endif /* DHD_LB_RXC */
++
++	/* RXCMPLT HDR */
++	rxcmplt_h = (host_rxbuf_cmpl_t *)msg;
++
++	/* offset from which data starts is populated in rxstatus0 */
++	data_offset = ltoh16(rxcmplt_h->data_offset);
++
++	pktid = ltoh32(rxcmplt_h->cmn_hdr.request_id);
++
++#if defined(DHD_PKTID_AUDIT_RING)
++	DHD_PKTID_AUDIT(dhd, dhd->prot->pktid_map_handle, pktid,
++		DHD_DUPLICATE_FREE);
++#endif /* DHD_PKTID_AUDIT_RING */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++	pkt = dhd_prot_packet_get(dhd, pktid, PKTTYPE_DATA_RX, free_pktid);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	if (!pkt) {
++		return;
++	}
++
++	/* Post another set of rxbufs to the device */
++	dhd_prot_return_rxbuf(dhd, pktid, 1);
++
++	DHD_INFO(("id 0x%04x, offset %d, len %d, idx %d, phase 0x%02x, pktdata %p, metalen %d\n",
++		ltoh32(rxcmplt_h->cmn_hdr.request_id), data_offset, ltoh16(rxcmplt_h->data_len),
++		rxcmplt_h->cmn_hdr.if_id, rxcmplt_h->cmn_hdr.flags, PKTDATA(dhd->osh, pkt),
++		ltoh16(rxcmplt_h->metadata_len)));
++#if DHD_DBG_SHOW_METADATA
++	if (dhd->prot->metadata_dbg &&
++	    dhd->prot->rx_metadata_offset && rxcmplt_h->metadata_len) {
++		uchar *ptr;
++		ptr = PKTDATA(dhd->osh, pkt) - (dhd->prot->rx_metadata_offset);
++		/* header followed by data */
++		bcm_print_bytes("rxmetadata", ptr, rxcmplt_h->metadata_len);
++		dhd_prot_print_metadata(dhd, ptr, rxcmplt_h->metadata_len);
++	}
++#endif /* DHD_DBG_SHOW_METADATA */
++
++	if (rxcmplt_h->flags & BCMPCIE_PKT_FLAGS_FRAME_802_11) {
++		DHD_INFO(("D11 frame rxed \n"));
++	}
++
++	/* data_offset from buf start */
++	if (data_offset) {
++		/* data offset given from dongle after split rx */
++		PKTPULL(dhd->osh, pkt, data_offset); /* data offset */
++	} else {
++		/* DMA RX offset updated through shared area */
++		if (dhd->prot->rx_dataoffset) {
++			PKTPULL(dhd->osh, pkt, dhd->prot->rx_dataoffset);
++		}
++	}
++	/* Actual length of the packet */
++	PKTSETLEN(dhd->osh, pkt, ltoh16(rxcmplt_h->data_len));
++
++	ifidx = rxcmplt_h->cmn_hdr.if_id;
++
++	if (dhd_monitor_enabled(dhd, ifidx) &&
++		(rxcmplt_h->flags & BCMPCIE_PKT_FLAGS_FRAME_802_11)) {
++		dhd_rx_mon_pkt(dhd, pkt, ifidx);
++		return;
++	}
++
++#if defined(DHD_LB_RXP)
++	dhd_lb_rx_pkt_enqueue(dhd, pkt, ifidx);
++#else  /* ! DHD_LB_RXP */
++#ifdef DHD_RX_CHAINING
++	/* Chain the packets */
++	dhd_rxchain_frame(dhd, pkt, ifidx);
++#else /* ! DHD_RX_CHAINING */
++	/* offset from which data starts is populated in rxstatus0 */
++	dhd_bus_rx_frame(dhd->bus, pkt, ifidx, 1);
++#endif /* ! DHD_RX_CHAINING */
++#endif /* ! DHD_LB_RXP */
++} /* dhd_prot_rxcmplt_process */
++
++/** Stop protocol: sync w/dongle state. */
++void dhd_prot_stop(dhd_pub_t *dhd)
++{
++	ASSERT(dhd);
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++}
++
++/* Add any protocol-specific data header.
++ * Caller must reserve prot_hdrlen prepend space.
++ */
++void BCMFASTPATH
++dhd_prot_hdrpush(dhd_pub_t *dhd, int ifidx, void *PKTBUF)
++{
++	return;
++}
++
++uint
++dhd_prot_hdrlen(dhd_pub_t *dhd, void *PKTBUF)
++{
++	return 0;
++}
++
++
++#define PKTBUF pktbuf
++
++/**
++ * Called when a tx ethernet packet has been dequeued from a flow queue, and has to be inserted in
++ * the corresponding flow ring.
++ */
++int BCMFASTPATH
++dhd_prot_txdata(dhd_pub_t *dhd, void *PKTBUF, uint8 ifidx)
++{
++	unsigned long flags;
++	dhd_prot_t *prot = dhd->prot;
++	host_txbuf_post_t *txdesc = NULL;
++	dmaaddr_t pa, meta_pa;
++	uint8 *pktdata;
++	uint32 pktlen;
++	uint32 pktid;
++	uint8	prio;
++	uint16 flowid = 0;
++	uint16 alloced = 0;
++	uint16	headroom;
++	msgbuf_ring_t *ring;
++	flow_ring_table_t *flow_ring_table;
++	flow_ring_node_t *flow_ring_node;
++
++	if (dhd->flow_ring_table == NULL) {
++		return BCME_NORESOURCE;
++	}
++
++	flowid = DHD_PKT_GET_FLOWID(PKTBUF);
++
++	flow_ring_table = (flow_ring_table_t *)dhd->flow_ring_table;
++	flow_ring_node = (flow_ring_node_t *)&flow_ring_table[flowid];
++
++	ring = (msgbuf_ring_t *)flow_ring_node->prot_info;
++
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	/* Create a unique 32-bit packet id */
++	pktid = DHD_NATIVE_TO_PKTID_RSV(dhd, dhd->prot->pktid_map_handle, PKTBUF);
++#if defined(DHD_PCIE_PKTID)
++	if (pktid == DHD_PKTID_INVALID) {
++		DHD_ERROR(("Pktid pool depleted.\n"));
++		/*
++		 * If we return error here, the caller would queue the packet
++		 * again. So we'll just free the skb allocated in DMA Zone.
++		 * Since we have not freed the original SKB yet the caller would
++		 * requeue the same.
++		 */
++		goto err_no_res_pktfree;
++	}
++#endif /* DHD_PCIE_PKTID */
++
++	/* Reserve space in the circular buffer */
++	txdesc = (host_txbuf_post_t *)
++		dhd_prot_alloc_ring_space(dhd, ring, 1, &alloced, FALSE);
++	if (txdesc == NULL) {
++#if defined(DHD_PCIE_PKTID)
++		void *dmah;
++		void *secdma;
++		/* Free up the PKTID. physaddr and pktlen will be garbage. */
++		DHD_PKTID_TO_NATIVE(dhd, dhd->prot->pktid_map_handle, pktid,
++			pa, pktlen, dmah, secdma, PKTTYPE_NO_CHECK);
++#endif /* DHD_PCIE_PKTID */
++		DHD_INFO(("%s:%d: HTOD Msgbuf Not available TxCount = %d\n",
++			__FUNCTION__, __LINE__, prot->active_tx_count));
++		goto err_no_res_pktfree;
++	}
++
++	/* Extract the data pointer and length information */
++	pktdata = PKTDATA(dhd->osh, PKTBUF);
++	pktlen  = PKTLEN(dhd->osh, PKTBUF);
++
++	/* Ethernet header: Copy before we cache flush packet using DMA_MAP */
++	bcopy(pktdata, txdesc->txhdr, ETHER_HDR_LEN);
++
++	/* Extract the ethernet header and adjust the data pointer and length */
++	pktdata = PKTPULL(dhd->osh, PKTBUF, ETHER_HDR_LEN);
++	pktlen -= ETHER_HDR_LEN;
++
++	/* Map the data pointer to a DMA-able address */
++	if (SECURE_DMA_ENAB(dhd->osh)) {
++		int offset = 0;
++		BCM_REFERENCE(offset);
++
++		if (prot->tx_metadata_offset) {
++			offset = prot->tx_metadata_offset + ETHER_HDR_LEN;
++		}
++
++		pa = SECURE_DMA_MAP(dhd->osh, PKTDATA(dhd->osh, PKTBUF), pktlen,
++			DMA_TX, PKTBUF, 0, ring->dma_buf.secdma, offset);
++	}
++#ifndef BCM_SECURE_DMA
++	else
++		pa = DMA_MAP(dhd->osh, PKTDATA(dhd->osh, PKTBUF), pktlen, DMA_TX, PKTBUF, 0);
++#endif /* #ifndef BCM_SECURE_DMA */
++
++	if ((PHYSADDRHI(pa) == 0) && (PHYSADDRLO(pa) == 0)) {
++		DHD_ERROR(("Something really bad, unless 0 is a valid phyaddr\n"));
++		ASSERT(0);
++	}
++
++	/* No need to lock. Save the rest of the packet's metadata */
++	DHD_NATIVE_TO_PKTID_SAVE(dhd, dhd->prot->pktid_map_handle, PKTBUF, pktid,
++	    pa, pktlen, DMA_TX, NULL, ring->dma_buf.secdma, PKTTYPE_DATA_TX);
++
++#ifdef TXP_FLUSH_NITEMS
++	if (ring->pend_items_count == 0) {
++		ring->start_addr = (void *)txdesc;
++	}
++	ring->pend_items_count++;
++#endif
++
++	/* Form the Tx descriptor message buffer */
++
++	/* Common message hdr */
++	txdesc->cmn_hdr.msg_type = MSG_TYPE_TX_POST;
++	txdesc->cmn_hdr.if_id = ifidx;
++
++	txdesc->flags = BCMPCIE_PKT_FLAGS_FRAME_802_3;
++	prio = (uint8)PKTPRIO(PKTBUF);
++
++
++	txdesc->flags |= (prio & 0x7) << BCMPCIE_PKT_FLAGS_PRIO_SHIFT;
++	txdesc->seg_cnt = 1;
++
++	txdesc->data_len = htol16((uint16) pktlen);
++	txdesc->data_buf_addr.high_addr = htol32(PHYSADDRHI(pa));
++	txdesc->data_buf_addr.low_addr  = htol32(PHYSADDRLO(pa));
++
++	/* Move data pointer to keep ether header in local PKTBUF for later reference */
++	PKTPUSH(dhd->osh, PKTBUF, ETHER_HDR_LEN);
++
++	/* Handle Tx metadata */
++	headroom = (uint16)PKTHEADROOM(dhd->osh, PKTBUF);
++	if (prot->tx_metadata_offset && (headroom < prot->tx_metadata_offset)) {
++		DHD_ERROR(("No headroom for Metadata tx %d %d\n",
++		prot->tx_metadata_offset, headroom));
++	}
++
++	if (prot->tx_metadata_offset && (headroom >= prot->tx_metadata_offset)) {
++		DHD_TRACE(("Metadata in tx %d\n", prot->tx_metadata_offset));
++
++		/* Adjust the data pointer to account for meta data in DMA_MAP */
++		PKTPUSH(dhd->osh, PKTBUF, prot->tx_metadata_offset);
++
++		if (SECURE_DMA_ENAB(dhd->osh)) {
++			meta_pa = SECURE_DMA_MAP_TXMETA(dhd->osh, PKTDATA(dhd->osh, PKTBUF),
++				prot->tx_metadata_offset + ETHER_HDR_LEN, DMA_RX, PKTBUF,
++				0, ring->dma_buf.secdma);
++		}
++#ifndef BCM_SECURE_DMA
++		else
++			meta_pa = DMA_MAP(dhd->osh, PKTDATA(dhd->osh, PKTBUF),
++				prot->tx_metadata_offset, DMA_RX, PKTBUF, 0);
++#endif /* #ifndef BCM_SECURE_DMA */
++
++		if (PHYSADDRISZERO(meta_pa)) {
++			DHD_ERROR(("Something really bad, unless 0 is a valid phyaddr\n"));
++			ASSERT(0);
++		}
++
++		/* Adjust the data pointer back to original value */
++		PKTPULL(dhd->osh, PKTBUF, prot->tx_metadata_offset);
++
++		txdesc->metadata_buf_len = prot->tx_metadata_offset;
++		txdesc->metadata_buf_addr.high_addr = htol32(PHYSADDRHI(meta_pa));
++		txdesc->metadata_buf_addr.low_addr = htol32(PHYSADDRLO(meta_pa));
++	} else {
++		txdesc->metadata_buf_len = htol16(0);
++		txdesc->metadata_buf_addr.high_addr = 0;
++		txdesc->metadata_buf_addr.low_addr = 0;
++	}
++
++#if defined(DHD_PKTID_AUDIT_RING)
++	DHD_PKTID_AUDIT(dhd, prot->pktid_map_handle, pktid,
++		DHD_DUPLICATE_ALLOC);
++#endif /* DHD_PKTID_AUDIT_RING */
++
++	txdesc->cmn_hdr.request_id = htol32(pktid);
++
++	DHD_TRACE(("txpost: data_len %d, pktid 0x%04x\n", txdesc->data_len,
++		txdesc->cmn_hdr.request_id));
++
++	/* Update the write pointer in TCM & ring bell */
++#ifdef TXP_FLUSH_NITEMS
++	/* Flush if we have either hit the txp_threshold or if this msg is */
++	/* occupying the last slot in the flow_ring - before wrap around.  */
++	if ((ring->pend_items_count == prot->txp_threshold) ||
++		((uint8 *) txdesc == (uint8 *) DHD_RING_END_VA(ring))) {
++		dhd_prot_txdata_write_flush(dhd, flowid, TRUE);
++	}
++#else
++	/* update ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ring, txdesc, 1);
++#endif
++
++	prot->active_tx_count++;
++
++	/*
++	 * Take a wake lock, do not sleep if we have atleast one packet
++	 * to finish.
++	 */
++	if (prot->active_tx_count == 1)
++		DHD_OS_WAKE_LOCK(dhd);
++
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	return BCME_OK;
++
++err_no_res_pktfree:
++
++
++
++	DHD_GENERAL_UNLOCK(dhd, flags);
++	return BCME_NORESOURCE;
++} /* dhd_prot_txdata */
++
++/* called with a lock */
++/** optimization to write "n" tx items at a time to ring */
++void BCMFASTPATH
++dhd_prot_txdata_write_flush(dhd_pub_t *dhd, uint16 flowid, bool in_lock)
++{
++#ifdef TXP_FLUSH_NITEMS
++	unsigned long flags = 0;
++	flow_ring_table_t *flow_ring_table;
++	flow_ring_node_t *flow_ring_node;
++	msgbuf_ring_t *ring;
++
++	if (dhd->flow_ring_table == NULL) {
++		return;
++	}
++
++	if (!in_lock) {
++		DHD_GENERAL_LOCK(dhd, flags);
++	}
++
++	flow_ring_table = (flow_ring_table_t *)dhd->flow_ring_table;
++	flow_ring_node = (flow_ring_node_t *)&flow_ring_table[flowid];
++	ring = (msgbuf_ring_t *)flow_ring_node->prot_info;
++
++	if (ring->pend_items_count) {
++		/* update ring's WR index and ring doorbell to dongle */
++		dhd_prot_ring_write_complete(dhd, ring, ring->start_addr,
++			ring->pend_items_count);
++		ring->pend_items_count = 0;
++		ring->start_addr = NULL;
++	}
++
++	if (!in_lock) {
++		DHD_GENERAL_UNLOCK(dhd, flags);
++	}
++#endif /* TXP_FLUSH_NITEMS */
++}
++
++#undef PKTBUF	/* Only defined in the above routine */
++
++int BCMFASTPATH
++dhd_prot_hdrpull(dhd_pub_t *dhd, int *ifidx, void *pkt, uchar *buf, uint *len)
++{
++	return 0;
++}
++
++/** post a set of receive buffers to the dongle */
++static void BCMFASTPATH
++dhd_prot_return_rxbuf(dhd_pub_t *dhd, uint32 pktid, uint32 rxcnt)
++{
++	dhd_prot_t *prot = dhd->prot;
++#if defined(DHD_LB_RXC)
++	int elem_ix;
++	uint32 *elem;
++	bcm_workq_t *workq;
++
++	workq = &prot->rx_compl_prod;
++
++	/* Produce the work item */
++	elem_ix = bcm_ring_prod(WORKQ_RING(workq), DHD_LB_WORKQ_SZ);
++	if (elem_ix == BCM_RING_FULL) {
++		DHD_ERROR(("%s LB RxCompl workQ is full\n", __FUNCTION__));
++		ASSERT(0);
++		return;
++	}
++
++	elem = WORKQ_ELEMENT(uint32, workq, elem_ix);
++	*elem = pktid;
++
++	smp_wmb();
++
++	/* Sync WR index to consumer if the SYNC threshold has been reached */
++	if (++prot->rx_compl_prod_sync >= DHD_LB_WORKQ_SYNC) {
++		bcm_workq_prod_sync(workq);
++		prot->rx_compl_prod_sync = 0;
++	}
++
++	DHD_INFO(("%s: rx_compl_prod pktid<%u> sync<%d>\n",
++		__FUNCTION__, pktid, prot->rx_compl_prod_sync));
++
++#endif /* DHD_LB_RXC */
++
++
++	if (prot->rxbufpost >= rxcnt) {
++		prot->rxbufpost -= rxcnt;
++	} else {
++		/* ASSERT(0); */
++		prot->rxbufpost = 0;
++	}
++
++#if !defined(DHD_LB_RXC)
++	if (prot->rxbufpost <= (prot->max_rxbufpost - RXBUFPOST_THRESHOLD)) {
++		dhd_msgbuf_rxbuf_post(dhd, FALSE); /* alloc pkt ids */
++	}
++#endif /* !DHD_LB_RXC */
++}
++
++/* called before an ioctl is sent to the dongle */
++static void
++dhd_prot_wlioctl_intercept(dhd_pub_t *dhd, wl_ioctl_t * ioc, void * buf)
++{
++	dhd_prot_t *prot = dhd->prot;
++
++	if (ioc->cmd == WLC_SET_VAR && buf != NULL && !strcmp(buf, "pcie_bus_tput")) {
++		int slen = 0;
++		pcie_bus_tput_params_t *tput_params;
++
++		slen = strlen("pcie_bus_tput") + 1;
++		tput_params = (pcie_bus_tput_params_t*)((char *)buf + slen);
++		bcopy(&prot->host_bus_throughput_buf.pa, &tput_params->host_buf_addr,
++			sizeof(tput_params->host_buf_addr));
++		tput_params->host_buf_len = DHD_BUS_TPUT_BUF_LEN;
++	}
++}
++
++
++/** Use protocol to issue ioctl to dongle. Only one ioctl may be in transit. */
++int dhd_prot_ioctl(dhd_pub_t *dhd, int ifidx, wl_ioctl_t * ioc, void * buf, int len)
++{
++	int ret = -1;
++	uint8 action;
++
++	if ((dhd->busstate == DHD_BUS_DOWN) || dhd->hang_was_sent) {
++		DHD_ERROR(("%s : bus is down. we have nothing to do\n", __FUNCTION__));
++		goto done;
++	}
++
++	if (dhd->busstate == DHD_BUS_SUSPEND) {
++		DHD_ERROR(("%s : bus is suspended\n", __FUNCTION__));
++		goto done;
++	}
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++
++	ASSERT(len <= WLC_IOCTL_MAXLEN);
++
++	if (len > WLC_IOCTL_MAXLEN) {
++		goto done;
++	}
++
++	action = ioc->set;
++
++	dhd_prot_wlioctl_intercept(dhd, ioc, buf);
++
++	if (action & WL_IOCTL_ACTION_SET) {
++		ret = dhd_msgbuf_set_ioctl(dhd, ifidx, ioc->cmd, buf, len, action);
++	} else {
++		ret = dhd_msgbuf_query_ioctl(dhd, ifidx, ioc->cmd, buf, len, action);
++		if (ret > 0) {
++			ioc->used = ret;
++		}
++	}
++
++	/* Too many programs assume ioctl() returns 0 on success */
++	if (ret >= 0) {
++		ret = 0;
++	} else {
++		DHD_ERROR(("%s: status ret value is %d \n", __FUNCTION__, ret));
++		dhd->dongle_error = ret;
++	}
++
++	if (!ret && ioc->cmd == WLC_SET_VAR && buf != NULL) {
++		/* Intercept the wme_dp ioctl here */
++		if (!strcmp(buf, "wme_dp")) {
++			int slen, val = 0;
++
++			slen = strlen("wme_dp") + 1;
++			if (len >= (int)(slen + sizeof(int))) {
++				bcopy(((char *)buf + slen), &val, sizeof(int));
++			}
++			dhd->wme_dp = (uint8) ltoh32(val);
++		}
++
++	}
++
++done:
++	return ret;
++
++} /* dhd_prot_ioctl */
++
++/** test / loopback */
++
++int
++dhdmsgbuf_lpbk_req(dhd_pub_t *dhd, uint len)
++{
++	unsigned long flags;
++	dhd_prot_t *prot = dhd->prot;
++	uint16 alloced = 0;
++
++	ioct_reqst_hdr_t *ioct_rqst;
++
++	uint16 hdrlen = sizeof(ioct_reqst_hdr_t);
++	uint16 msglen = len + hdrlen;
++	msgbuf_ring_t *ring = &prot->h2dring_ctrl_subn;
++
++	msglen = ALIGN_SIZE(msglen, DMA_ALIGN_LEN);
++	msglen = LIMIT_TO_MAX(msglen, MSGBUF_MAX_MSG_SIZE);
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	ioct_rqst = (ioct_reqst_hdr_t *)
++		dhd_prot_alloc_ring_space(dhd, ring, 1, &alloced, FALSE);
++
++	if (ioct_rqst == NULL) {
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		return 0;
++	}
++
++	{
++		uint8 *ptr;
++		uint16 i;
++
++		ptr = (uint8 *)ioct_rqst;
++		for (i = 0; i < msglen; i++) {
++			ptr[i] = i % 256;
++		}
++	}
++
++	/* Common msg buf hdr */
++	ioct_rqst->msg.epoch = ring->seqnum % H2D_EPOCH_MODULO;
++	ring->seqnum++;
++
++	ioct_rqst->msg.msg_type = MSG_TYPE_LOOPBACK;
++	ioct_rqst->msg.if_id = 0;
++
++	bcm_print_bytes("LPBK REQ: ", (uint8 *)ioct_rqst, msglen);
++
++	/* update ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ring, ioct_rqst, 1);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	return 0;
++}
++
++/** test / loopback */
++void dmaxfer_free_dmaaddr(dhd_pub_t *dhd, dhd_dmaxfer_t *dmaxfer)
++{
++	if (dmaxfer == NULL) {
++		return;
++	}
++
++	dhd_dma_buf_free(dhd, &dmaxfer->srcmem);
++	dhd_dma_buf_free(dhd, &dmaxfer->dstmem);
++}
++
++/** test / loopback */
++int dmaxfer_prepare_dmaaddr(dhd_pub_t *dhd, uint len,
++	uint srcdelay, uint destdelay, dhd_dmaxfer_t *dmaxfer)
++{
++	uint i;
++	if (!dmaxfer) {
++		return BCME_ERROR;
++	}
++
++	/* First free up existing buffers */
++	dmaxfer_free_dmaaddr(dhd, dmaxfer);
++
++	if (dhd_dma_buf_alloc(dhd, &dmaxfer->srcmem, len)) {
++		return BCME_NOMEM;
++	}
++
++	if (dhd_dma_buf_alloc(dhd, &dmaxfer->dstmem, len + 8)) {
++		dhd_dma_buf_free(dhd, &dmaxfer->srcmem);
++		return BCME_NOMEM;
++	}
++
++	dmaxfer->len = len;
++
++	/* Populate source with a pattern */
++	for (i = 0; i < dmaxfer->len; i++) {
++		((uint8*)dmaxfer->srcmem.va)[i] = i % 256;
++	}
++	OSL_CACHE_FLUSH(dmaxfer->srcmem.va, dmaxfer->len);
++
++	dmaxfer->srcdelay = srcdelay;
++	dmaxfer->destdelay = destdelay;
++
++	return BCME_OK;
++} /* dmaxfer_prepare_dmaaddr */
++
++static void
++dhd_msgbuf_dmaxfer_process(dhd_pub_t *dhd, void *msg)
++{
++	dhd_prot_t *prot = dhd->prot;
++
++	OSL_CACHE_INV(prot->dmaxfer.dstmem.va, prot->dmaxfer.len);
++	if (prot->dmaxfer.srcmem.va && prot->dmaxfer.dstmem.va) {
++		if (memcmp(prot->dmaxfer.srcmem.va,
++		        prot->dmaxfer.dstmem.va, prot->dmaxfer.len)) {
++			bcm_print_bytes("XFER SRC: ",
++			    prot->dmaxfer.srcmem.va, prot->dmaxfer.len);
++			bcm_print_bytes("XFER DST: ",
++			    prot->dmaxfer.dstmem.va, prot->dmaxfer.len);
++		} else {
++			DHD_INFO(("DMA successful\n"));
++		}
++	}
++	dmaxfer_free_dmaaddr(dhd, &prot->dmaxfer);
++	dhd->prot->dmaxfer.in_progress = FALSE;
++}
++
++/** Test functionality.
++ * Transfers bytes from host to dongle and to host again using DMA
++ * This function is not reentrant, as prot->dmaxfer.in_progress is not protected
++ * by a spinlock.
++ */
++int
++dhdmsgbuf_dmaxfer_req(dhd_pub_t *dhd, uint len, uint srcdelay, uint destdelay)
++{
++	unsigned long flags;
++	int ret = BCME_OK;
++	dhd_prot_t *prot = dhd->prot;
++	pcie_dma_xfer_params_t *dmap;
++	uint32 xferlen = LIMIT_TO_MAX(len, DMA_XFER_LEN_LIMIT);
++	uint16 alloced = 0;
++	msgbuf_ring_t *ring = &prot->h2dring_ctrl_subn;
++
++	if (prot->dmaxfer.in_progress) {
++		DHD_ERROR(("DMA is in progress...\n"));
++		return ret;
++	}
++
++	prot->dmaxfer.in_progress = TRUE;
++	if ((ret = dmaxfer_prepare_dmaaddr(dhd, xferlen, srcdelay, destdelay,
++	        &prot->dmaxfer)) != BCME_OK) {
++		prot->dmaxfer.in_progress = FALSE;
++		return ret;
++	}
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	dmap = (pcie_dma_xfer_params_t *)
++		dhd_prot_alloc_ring_space(dhd, ring, 1, &alloced, FALSE);
++
++	if (dmap == NULL) {
++		dmaxfer_free_dmaaddr(dhd, &prot->dmaxfer);
++		prot->dmaxfer.in_progress = FALSE;
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		return BCME_NOMEM;
++	}
++
++	/* Common msg buf hdr */
++	dmap->cmn_hdr.msg_type = MSG_TYPE_LPBK_DMAXFER;
++	dmap->cmn_hdr.request_id = htol32(DHD_FAKE_PKTID);
++	dmap->cmn_hdr.epoch = ring->seqnum % H2D_EPOCH_MODULO;
++	ring->seqnum++;
++
++	dmap->host_input_buf_addr.high = htol32(PHYSADDRHI(prot->dmaxfer.srcmem.pa));
++	dmap->host_input_buf_addr.low = htol32(PHYSADDRLO(prot->dmaxfer.srcmem.pa));
++	dmap->host_ouput_buf_addr.high = htol32(PHYSADDRHI(prot->dmaxfer.dstmem.pa));
++	dmap->host_ouput_buf_addr.low = htol32(PHYSADDRLO(prot->dmaxfer.dstmem.pa));
++	dmap->xfer_len = htol32(prot->dmaxfer.len);
++	dmap->srcdelay = htol32(prot->dmaxfer.srcdelay);
++	dmap->destdelay = htol32(prot->dmaxfer.destdelay);
++
++	/* update ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ring, dmap, 1);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	DHD_ERROR(("DMA Started...\n"));
++
++	return BCME_OK;
++} /* dhdmsgbuf_dmaxfer_req */
++
++/** Called in the process of submitting an ioctl to the dongle */
++static int
++dhd_msgbuf_query_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len, uint8 action)
++{
++	int ret = 0;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	/* Respond "bcmerror" and "bcmerrorstr" with local cache */
++	if (cmd == WLC_GET_VAR && buf)
++	{
++		if (!strcmp((char *)buf, "bcmerrorstr"))
++		{
++			strncpy((char *)buf, bcmerrorstr(dhd->dongle_error), BCME_STRLEN);
++			goto done;
++		}
++		else if (!strcmp((char *)buf, "bcmerror"))
++		{
++			*(int *)buf = dhd->dongle_error;
++			goto done;
++		}
++	}
++
++	ret = dhd_fillup_ioct_reqst(dhd, (uint16)len, cmd, buf, ifidx);
++
++	DHD_CTL(("query_ioctl: ACTION %d ifdix %d cmd %d len %d \n",
++		action, ifidx, cmd, len));
++
++	/* wait for IOCTL completion message from dongle and get first fragment */
++	ret = dhd_msgbuf_wait_ioctl_cmplt(dhd, len, buf);
++
++done:
++	return ret;
++}
++
++/**
++ * Waits for IOCTL completion message from the dongle, copies this into caller
++ * provided parameter 'buf'.
++ */
++static int
++dhd_msgbuf_wait_ioctl_cmplt(dhd_pub_t *dhd, uint32 len, void *buf)
++{
++	dhd_prot_t *prot = dhd->prot;
++	int timeleft;
++	unsigned long flags;
++	int ret = 0;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (dhd->dongle_reset) {
++		ret = -EIO;
++		goto out;
++	}
++
++	if (prot->cur_ioctlresp_bufs_posted) {
++		prot->cur_ioctlresp_bufs_posted--;
++	}
++
++	dhd_msgbuf_rxbuf_post_ioctlresp_bufs(dhd);
++
++	timeleft = dhd_os_ioctl_resp_wait(dhd, &prot->ioctl_received);
++	if (timeleft == 0) {
++		dhd->rxcnt_timeout++;
++		dhd->rx_ctlerrs++;
++		DHD_ERROR(("%s: resumed on timeout rxcnt_timeout %d ioctl_cmd %d "
++			"trans_id %d state %d busstate=%d ioctl_received=%d\n",
++			__FUNCTION__, dhd->rxcnt_timeout, prot->curr_ioctl_cmd,
++			prot->ioctl_trans_id, prot->ioctl_state & ~MSGBUF_IOCTL_RESP_PENDING,
++			dhd->busstate, prot->ioctl_received));
++
++		dhd_prot_debug_info_print(dhd);
++
++#if defined(DHD_FW_COREDUMP)
++		/* Collect socram dump for CUSTOMER_HW4 OR Brix Android */
++		/* As soon as FW TRAP occurs, FW dump will be collected from dhdpcie_checkdied */
++		if (dhd->memdump_enabled && !dhd->dongle_trap_occured) {
++			/* collect core dump */
++			dhd->memdump_type = DUMP_TYPE_RESUMED_ON_TIMEOUT;
++			dhd_bus_mem_dump(dhd);
++		}
++#endif /* DHD_FW_COREDUMP && OEM_ANDROID */
++		if (dhd->rxcnt_timeout >= MAX_CNTL_RX_TIMEOUT) {
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#ifdef CONFIG_ARCH_MSM
++			dhd->bus->islinkdown = 1;
++#endif /* CONFIG_ARCH_MSM */
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++			DHD_ERROR(("%s: timeout > MAX_CNTL_TX_TIMEOUT\n", __FUNCTION__));
++		}
++		ret = -ETIMEDOUT;
++		goto out;
++	} else {
++		if (prot->ioctl_received != IOCTL_RETURN_ON_SUCCESS) {
++			DHD_ERROR(("%s: IOCTL failure due to ioctl_received = %d\n",
++				__FUNCTION__, prot->ioctl_received));
++			ret = -ECONNABORTED;
++			goto out;
++		}
++		dhd->rxcnt_timeout = 0;
++		dhd->rx_ctlpkts++;
++		DHD_CTL(("%s: ioctl resp resumed, got %d\n",
++			__FUNCTION__, prot->ioctl_resplen));
++	}
++
++	if (dhd->dongle_trap_occured) {
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#ifdef CONFIG_ARCH_MSM
++		dhd->bus->islinkdown = 1;
++#endif /* CONFIG_ARCH_MSM */
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++		DHD_ERROR(("%s: TRAP occurred!!\n", __FUNCTION__));
++		ret = -EREMOTEIO;
++		goto out;
++	}
++
++	if (dhd->prot->ioctl_resplen > len) {
++		dhd->prot->ioctl_resplen = (uint16)len;
++	}
++	if (buf) {
++		bcopy(dhd->prot->retbuf.va, buf, dhd->prot->ioctl_resplen);
++	}
++
++	ret = (int)(dhd->prot->ioctl_status);
++out:
++	DHD_GENERAL_LOCK(dhd, flags);
++	dhd->prot->ioctl_state &= ~MSGBUF_IOCTL_RESP_PENDING;
++	dhd->prot->ioctl_resplen = 0;
++	dhd->prot->ioctl_received = IOCTL_WAIT;
++	dhd->prot->curr_ioctl_cmd = 0;
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	return ret;
++} /* dhd_msgbuf_wait_ioctl_cmplt */
++
++static int
++dhd_msgbuf_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len, uint8 action)
++{
++	int ret = 0;
++
++	DHD_TRACE(("%s: Enter \n", __FUNCTION__));
++
++	if (dhd->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s : bus is down. we have nothing to do\n", __FUNCTION__));
++		return -EIO;
++	}
++
++	/* don't talk to the dongle if fw is about to be reloaded */
++	if (dhd->hang_was_sent) {
++		DHD_ERROR(("%s: HANG was sent up earlier. Not talking to the chip\n",
++			__FUNCTION__));
++		return -EIO;
++	}
++
++	/* Fill up msgbuf for ioctl req */
++	ret = dhd_fillup_ioct_reqst(dhd, (uint16)len, cmd, buf, ifidx);
++
++	DHD_CTL(("ACTION %d ifdix %d cmd %d len %d \n",
++		action, ifidx, cmd, len));
++
++	ret = dhd_msgbuf_wait_ioctl_cmplt(dhd, len, buf);
++
++	return ret;
++}
++
++/** Called by upper DHD layer. Handles a protocol control response asynchronously. */
++int dhd_prot_ctl_complete(dhd_pub_t *dhd)
++{
++	return 0;
++}
++
++/** Called by upper DHD layer. Check for and handle local prot-specific iovar commands */
++int dhd_prot_iovar_op(dhd_pub_t *dhd, const char *name,
++	void *params, int plen, void *arg, int len, bool set)
++{
++	return BCME_UNSUPPORTED;
++}
++
++/** Add prot dump output to a buffer */
++void dhd_prot_dump(dhd_pub_t *dhd, struct bcmstrbuf *b)
++{
++
++#if defined(PCIE_D2H_SYNC)
++	if (dhd->d2h_sync_mode & PCIE_SHARED_D2H_SYNC_SEQNUM)
++		bcm_bprintf(b, "\nd2h_sync: SEQNUM:");
++	else if (dhd->d2h_sync_mode & PCIE_SHARED_D2H_SYNC_XORCSUM)
++		bcm_bprintf(b, "\nd2h_sync: XORCSUM:");
++	else
++		bcm_bprintf(b, "\nd2h_sync: NONE:");
++	bcm_bprintf(b, " d2h_sync_wait max<%lu> tot<%lu>\n",
++		dhd->prot->d2h_sync_wait_max, dhd->prot->d2h_sync_wait_tot);
++#endif  /* PCIE_D2H_SYNC */
++
++	bcm_bprintf(b, "\nDongle DMA Indices: h2d %d  d2h %d index size %d bytes\n",
++		DMA_INDX_ENAB(dhd->dma_h2d_ring_upd_support),
++		DMA_INDX_ENAB(dhd->dma_d2h_ring_upd_support),
++		dhd->prot->rw_index_sz);
++}
++
++/* Update local copy of dongle statistics */
++void dhd_prot_dstats(dhd_pub_t *dhd)
++{
++	return;
++}
++
++/** Called by upper DHD layer */
++int dhd_process_pkt_reorder_info(dhd_pub_t *dhd, uchar *reorder_info_buf,
++	uint reorder_info_len, void **pkt, uint32 *free_buf_count)
++{
++	return 0;
++}
++
++/** Debug related, post a dummy message to interrupt dongle. Used to process cons commands. */
++int
++dhd_post_dummy_msg(dhd_pub_t *dhd)
++{
++	unsigned long flags;
++	hostevent_hdr_t *hevent = NULL;
++	uint16 alloced = 0;
++
++	dhd_prot_t *prot = dhd->prot;
++	msgbuf_ring_t *ring = &prot->h2dring_ctrl_subn;
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	hevent = (hostevent_hdr_t *)
++		dhd_prot_alloc_ring_space(dhd, ring, 1, &alloced, FALSE);
++
++	if (hevent == NULL) {
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		return -1;
++	}
++
++	/* CMN msg header */
++	hevent->msg.epoch = ring->seqnum % H2D_EPOCH_MODULO;
++	ring->seqnum++;
++	hevent->msg.msg_type = MSG_TYPE_HOST_EVNT;
++	hevent->msg.if_id = 0;
++
++	/* Event payload */
++	hevent->evnt_pyld = htol32(HOST_EVENT_CONS_CMD);
++
++	/* Since, we are filling the data directly into the bufptr obtained
++	 * from the msgbuf, we can directly call the write_complete
++	 */
++	dhd_prot_ring_write_complete(dhd, ring, hevent, 1);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	return 0;
++}
++
++/**
++ * If exactly_nitems is true, this function will allocate space for nitems or fail
++ * If exactly_nitems is false, this function will allocate space for nitems or less
++ */
++static void * BCMFASTPATH
++dhd_prot_alloc_ring_space(dhd_pub_t *dhd, msgbuf_ring_t *ring,
++	uint16 nitems, uint16 * alloced, bool exactly_nitems)
++{
++	void * ret_buf;
++
++	/* Alloc space for nitems in the ring */
++	ret_buf = dhd_prot_get_ring_space(ring, nitems, alloced, exactly_nitems);
++
++	if (ret_buf == NULL) {
++		/* if alloc failed , invalidate cached read ptr */
++		if (DMA_INDX_ENAB(dhd->dma_d2h_ring_upd_support)) {
++			ring->rd = dhd_prot_dma_indx_get(dhd, H2D_DMA_INDX_RD_UPD, ring->idx);
++		} else {
++			dhd_bus_cmn_readshared(dhd->bus, &(ring->rd), RING_RD_UPD, ring->idx);
++		}
++
++		/* Try allocating once more */
++		ret_buf = dhd_prot_get_ring_space(ring, nitems, alloced, exactly_nitems);
++
++		if (ret_buf == NULL) {
++			DHD_INFO(("%s: Ring space not available  \n", ring->name));
++			return NULL;
++		}
++	}
++
++	/* Return alloced space */
++	return ret_buf;
++}
++
++/**
++ * Non inline ioct request.
++ * Form a ioctl request first as per ioctptr_reqst_hdr_t header in the circular buffer
++ * Form a separate request buffer where a 4 byte cmn header is added in the front
++ * buf contents from parent function is copied to remaining section of this buffer
++ */
++static int
++dhd_fillup_ioct_reqst(dhd_pub_t *dhd, uint16 len, uint cmd, void* buf, int ifidx)
++{
++	dhd_prot_t *prot = dhd->prot;
++	ioctl_req_msg_t *ioct_rqst;
++	void * ioct_buf;	/* For ioctl payload */
++	uint16  rqstlen, resplen;
++	unsigned long flags;
++	uint16 alloced = 0;
++	msgbuf_ring_t *ring = &prot->h2dring_ctrl_subn;
++
++	rqstlen = len;
++	resplen = len;
++
++	/* Limit ioct request to MSGBUF_MAX_MSG_SIZE bytes including hdrs */
++	/* 8K allocation of dongle buffer fails */
++	/* dhd doesnt give separate input & output buf lens */
++	/* so making the assumption that input length can never be more than 1.5k */
++	rqstlen = MIN(rqstlen, MSGBUF_MAX_MSG_SIZE);
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	if (prot->ioctl_state) {
++		DHD_ERROR(("%s: pending ioctl %02x\n", __FUNCTION__, prot->ioctl_state));
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		return BCME_BUSY;
++	} else {
++		prot->ioctl_state = MSGBUF_IOCTL_ACK_PENDING | MSGBUF_IOCTL_RESP_PENDING;
++	}
++
++	/* Request for cbuf space */
++	ioct_rqst = (ioctl_req_msg_t*)
++		dhd_prot_alloc_ring_space(dhd, ring, 1, &alloced, FALSE);
++	if (ioct_rqst == NULL) {
++		DHD_ERROR(("couldn't allocate space on msgring to send ioctl request\n"));
++		prot->ioctl_state = 0;
++		prot->curr_ioctl_cmd = 0;
++		prot->ioctl_received = IOCTL_WAIT;
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		return -1;
++	}
++
++	/* Common msg buf hdr */
++	ioct_rqst->cmn_hdr.msg_type = MSG_TYPE_IOCTLPTR_REQ;
++	ioct_rqst->cmn_hdr.if_id = (uint8)ifidx;
++	ioct_rqst->cmn_hdr.flags = 0;
++	ioct_rqst->cmn_hdr.request_id = htol32(DHD_IOCTL_REQ_PKTID);
++	ioct_rqst->cmn_hdr.epoch = ring->seqnum % H2D_EPOCH_MODULO;
++	ring->seqnum++;
++
++	ioct_rqst->cmd = htol32(cmd);
++	prot->curr_ioctl_cmd = cmd;
++	ioct_rqst->output_buf_len = htol16(resplen);
++	prot->ioctl_trans_id++;
++	ioct_rqst->trans_id = prot->ioctl_trans_id;
++
++	/* populate ioctl buffer info */
++	ioct_rqst->input_buf_len = htol16(rqstlen);
++	ioct_rqst->host_input_buf_addr.high = htol32(PHYSADDRHI(prot->ioctbuf.pa));
++	ioct_rqst->host_input_buf_addr.low = htol32(PHYSADDRLO(prot->ioctbuf.pa));
++	/* copy ioct payload */
++	ioct_buf = (void *) prot->ioctbuf.va;
++
++	if (buf) {
++		memcpy(ioct_buf, buf, len);
++	}
++
++	OSL_CACHE_FLUSH((void *) prot->ioctbuf.va, len);
++
++	if (!ISALIGNED(ioct_buf, DMA_ALIGN_LEN)) {
++		DHD_ERROR(("host ioct address unaligned !!!!! \n"));
++	}
++
++	DHD_CTL(("submitted IOCTL request request_id %d, cmd %d, output_buf_len %d, tx_id %d\n",
++		ioct_rqst->cmn_hdr.request_id, cmd, ioct_rqst->output_buf_len,
++		ioct_rqst->trans_id));
++
++	/* update ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ring, ioct_rqst, 1);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	return 0;
++} /* dhd_fillup_ioct_reqst */
++
++
++/**
++ * dhd_prot_ring_attach - Initialize the msgbuf_ring object and attach a
++ * DMA-able buffer to it. The ring is NOT tagged as inited until all the ring
++ * information is posted to the dongle.
++ *
++ * Invoked in dhd_prot_attach for the common rings, and in dhd_prot_init for
++ * each flowring in pool of flowrings.
++ *
++ * returns BCME_OK=0 on success
++ * returns non-zero negative error value on failure.
++ */
++static int
++dhd_prot_ring_attach(dhd_pub_t *dhd, msgbuf_ring_t *ring, const char *name,
++	uint16 max_items, uint16 item_len, uint16 ringid)
++{
++	int dma_buf_alloced = BCME_NOMEM;
++	uint32 dma_buf_len = max_items * item_len;
++	dhd_prot_t *prot = dhd->prot;
++
++	ASSERT(ring);
++	ASSERT(name);
++	ASSERT((max_items < 0xFFFF) && (item_len < 0xFFFF) && (ringid < 0xFFFF));
++
++	/* Init name */
++	strncpy(ring->name, name, RING_NAME_MAX_LENGTH);
++	ring->name[RING_NAME_MAX_LENGTH - 1] = '\0';
++
++	ring->idx = ringid;
++
++	ring->max_items = max_items;
++	ring->item_len = item_len;
++
++	/* A contiguous space may be reserved for all flowrings */
++	if (DHD_IS_FLOWRING(ringid) && (prot->flowrings_dma_buf.va)) {
++		/* Carve out from the contiguous DMA-able flowring buffer */
++		uint16 flowid;
++		uint32 base_offset;
++
++		dhd_dma_buf_t *dma_buf = &ring->dma_buf;
++		dhd_dma_buf_t *rsv_buf = &prot->flowrings_dma_buf;
++
++		flowid = DHD_RINGID_TO_FLOWID(ringid);
++		base_offset = (flowid - BCMPCIE_H2D_COMMON_MSGRINGS) * dma_buf_len;
++
++		ASSERT(base_offset + dma_buf_len <= rsv_buf->len);
++
++		dma_buf->len = dma_buf_len;
++		dma_buf->va = (void *)((uintptr)rsv_buf->va + base_offset);
++		PHYSADDRHISET(dma_buf->pa, PHYSADDRHI(rsv_buf->pa));
++		PHYSADDRLOSET(dma_buf->pa, PHYSADDRLO(rsv_buf->pa) + base_offset);
++
++		/* On 64bit, contiguous space may not span across 0x00000000FFFFFFFF */
++		ASSERT(PHYSADDRLO(dma_buf->pa) >= PHYSADDRLO(rsv_buf->pa));
++
++		dma_buf->dmah   = rsv_buf->dmah;
++		dma_buf->secdma = rsv_buf->secdma;
++
++		(void)dhd_dma_buf_audit(dhd, &ring->dma_buf);
++	} else {
++		/* Allocate a dhd_dma_buf */
++		dma_buf_alloced = dhd_dma_buf_alloc(dhd, &ring->dma_buf, dma_buf_len);
++		if (dma_buf_alloced != BCME_OK) {
++			return BCME_NOMEM;
++		}
++	}
++
++	/* CAUTION: Save ring::base_addr in little endian format! */
++	dhd_base_addr_htolpa(&ring->base_addr, ring->dma_buf.pa);
++
++#ifdef BCM_SECURE_DMA
++	if (SECURE_DMA_ENAB(prot->osh)) {
++		ring->dma_buf.secdma = MALLOCZ(prot->osh, sizeof(sec_cma_info_t));
++		if (ring->dma_buf.secdma == NULL) {
++			goto free_dma_buf;
++		}
++	}
++#endif /* BCM_SECURE_DMA */
++
++	DHD_INFO(("RING_ATTACH : %s Max item %d len item %d total size %d "
++		"ring start %p buf phys addr  %x:%x \n",
++		ring->name, ring->max_items, ring->item_len,
++		dma_buf_len, ring->dma_buf.va, ltoh32(ring->base_addr.high_addr),
++		ltoh32(ring->base_addr.low_addr)));
++
++	return BCME_OK;
++
++#ifdef BCM_SECURE_DMA
++free_dma_buf:
++	if (dma_buf_alloced == BCME_OK) {
++		dhd_dma_buf_free(dhd, &ring->dma_buf);
++	}
++#endif /* BCM_SECURE_DMA */
++
++	return BCME_NOMEM;
++
++} /* dhd_prot_ring_attach */
++
++
++/**
++ * dhd_prot_ring_init - Post the common ring information to dongle.
++ *
++ * Used only for common rings.
++ *
++ * The flowrings information is passed via the create flowring control message
++ * (tx_flowring_create_request_t) sent over the H2D control submission common
++ * ring.
++ */
++static void
++dhd_prot_ring_init(dhd_pub_t *dhd, msgbuf_ring_t *ring)
++{
++	ring->wr = 0;
++	ring->rd = 0;
++
++	/* CAUTION: ring::base_addr already in Little Endian */
++	dhd_bus_cmn_writeshared(dhd->bus, &ring->base_addr,
++		sizeof(sh_addr_t), RING_BUF_ADDR, ring->idx);
++	dhd_bus_cmn_writeshared(dhd->bus, &ring->max_items,
++		sizeof(uint16), RING_MAX_ITEMS, ring->idx);
++	dhd_bus_cmn_writeshared(dhd->bus, &ring->item_len,
++		sizeof(uint16), RING_ITEM_LEN, ring->idx);
++
++	dhd_bus_cmn_writeshared(dhd->bus, &(ring->wr),
++		sizeof(uint16), RING_WR_UPD, ring->idx);
++	dhd_bus_cmn_writeshared(dhd->bus, &(ring->rd),
++		sizeof(uint16), RING_RD_UPD, ring->idx);
++
++	/* ring inited */
++	ring->inited = TRUE;
++
++} /* dhd_prot_ring_init */
++
++
++/**
++ * dhd_prot_ring_reset - bzero a ring's DMA-ble buffer and cache flush
++ * Reset WR and RD indices to 0.
++ */
++static void
++dhd_prot_ring_reset(dhd_pub_t *dhd, msgbuf_ring_t *ring)
++{
++	DHD_TRACE(("%s\n", __FUNCTION__));
++
++	dhd_dma_buf_reset(dhd, &ring->dma_buf);
++
++	ring->rd = ring->wr = 0;
++}
++
++
++/**
++ * dhd_prot_ring_detach - Detach the DMA-able buffer and any other objects
++ * hanging off the msgbuf_ring.
++ */
++static void
++dhd_prot_ring_detach(dhd_pub_t *dhd, msgbuf_ring_t *ring)
++{
++	dhd_prot_t *prot = dhd->prot;
++	ASSERT(ring);
++
++	ring->inited = FALSE;
++	/* rd = ~0, wr = ring->rd - 1, max_items = 0, len_item = ~0 */
++
++#ifdef BCM_SECURE_DMA
++	if (SECURE_DMA_ENAB(prot->osh)) {
++		if (ring->dma_buf.secdma) {
++			SECURE_DMA_UNMAP_ALL(prot->osh, ring->dma_buf.secdma);
++			MFREE(prot->osh, ring->dma_buf.secdma, sizeof(sec_cma_info_t));
++			ring->dma_buf.secdma = NULL;
++		}
++	}
++#endif /* BCM_SECURE_DMA */
++
++	/* If the DMA-able buffer was carved out of a pre-reserved contiguous
++	 * memory, then simply stop using it.
++	 */
++	if (DHD_IS_FLOWRING(ring->idx) && (prot->flowrings_dma_buf.va)) {
++		(void)dhd_dma_buf_audit(dhd, &ring->dma_buf);
++		memset(&ring->dma_buf, 0, sizeof(dhd_dma_buf_t));
++	} else {
++		dhd_dma_buf_free(dhd, &ring->dma_buf);
++	}
++
++} /* dhd_prot_ring_detach */
++
++
++/*
++ * +----------------------------------------------------------------------------
++ * Flowring Pool
++ *
++ * Unlike common rings, which are attached very early on (dhd_prot_attach),
++ * flowrings are dynamically instantiated. Moreover, flowrings may require a
++ * larger DMA-able buffer. To avoid issues with fragmented cache coherent
++ * DMA-able memory, a pre-allocated pool of msgbuf_ring_t is allocated once.
++ * The DMA-able buffers are attached to these pre-allocated msgbuf_ring.
++ *
++ * Each DMA-able buffer may be allocated independently, or may be carved out
++ * of a single large contiguous region that is registered with the protocol
++ * layer into flowrings_dma_buf. On a 64bit platform, this contiguous region
++ * may not span 0x00000000FFFFFFFF (avoid dongle side 64bit ptr arithmetic).
++ *
++ * No flowring pool action is performed in dhd_prot_attach(), as the number
++ * of h2d rings is not yet known.
++ *
++ * In dhd_prot_init(), the dongle advertized number of h2d rings is used to
++ * determine the number of flowrings required, and a pool of msgbuf_rings are
++ * allocated and a DMA-able buffer (carved or allocated) is attached.
++ * See: dhd_prot_flowrings_pool_attach()
++ *
++ * A flowring msgbuf_ring object may be fetched from this pool during flowring
++ * creation, using the flowid. Likewise, flowrings may be freed back into the
++ * pool on flowring deletion.
++ * See: dhd_prot_flowrings_pool_fetch(), dhd_prot_flowrings_pool_release()
++ *
++ * In dhd_prot_detach(), the flowring pool is detached. The DMA-able buffers
++ * are detached (returned back to the carved region or freed), and the pool of
++ * msgbuf_ring and any objects allocated against it are freed.
++ * See: dhd_prot_flowrings_pool_detach()
++ *
++ * In dhd_prot_reset(), the flowring pool is simply reset by returning it to a
++ * state as-if upon an attach. All DMA-able buffers are retained.
++ * Following a dhd_prot_reset(), in a subsequent dhd_prot_init(), the flowring
++ * pool attach will notice that the pool persists and continue to use it. This
++ * will avoid the case of a fragmented DMA-able region.
++ *
++ * +----------------------------------------------------------------------------
++ */
++
++/* Fetch number of H2D flowrings given the total number of h2d rings */
++#define DHD_FLOWRINGS_POOL_TOTAL(h2d_rings_total) \
++	((h2d_rings_total) - BCMPCIE_H2D_COMMON_MSGRINGS)
++
++/* Conversion of a flowid to a flowring pool index */
++#define DHD_FLOWRINGS_POOL_OFFSET(flowid) \
++	((flowid) - BCMPCIE_H2D_COMMON_MSGRINGS)
++
++/* Fetch the msgbuf_ring_t from the flowring pool given a flowid */
++#define DHD_RING_IN_FLOWRINGS_POOL(prot, flowid) \
++	(msgbuf_ring_t*)((prot)->h2d_flowrings_pool) + DHD_FLOWRINGS_POOL_OFFSET(flowid)
++
++/* Traverse each flowring in the flowring pool, assigning ring and flowid */
++#define FOREACH_RING_IN_FLOWRINGS_POOL(prot, ring, flowid) \
++	for ((flowid) = DHD_FLOWRING_START_FLOWID, \
++		 (ring) = DHD_RING_IN_FLOWRINGS_POOL(prot, flowid); \
++		 (flowid) < (prot)->h2d_rings_total; \
++		 (flowid)++, (ring)++)
++
++/**
++ * dhd_prot_flowrings_pool_attach - Initialize a pool of flowring msgbuf_ring_t.
++ *
++ * Allocate a pool of msgbuf_ring along with DMA-able buffers for flowrings.
++ * Dongle includes common rings when it advertizes the number of H2D rings.
++ * Allocates a pool of msgbuf_ring_t and invokes dhd_prot_ring_attach to
++ * allocate the DMA-able buffer and initialize each msgbuf_ring_t object.
++ *
++ * dhd_prot_ring_attach is invoked to perform the actual initialization and
++ * attaching the DMA-able buffer.
++ *
++ * Later dhd_prot_flowrings_pool_fetch() may be used to fetch a preallocated and
++ * initialized msgbuf_ring_t object.
++ *
++ * returns BCME_OK=0 on success
++ * returns non-zero negative error value on failure.
++ */
++static int
++dhd_prot_flowrings_pool_attach(dhd_pub_t *dhd)
++{
++	uint16 flowid;
++	msgbuf_ring_t *ring;
++	uint16 h2d_flowrings_total; /* exclude H2D common rings */
++	dhd_prot_t *prot = dhd->prot;
++	char ring_name[RING_NAME_MAX_LENGTH];
++
++	if (prot->h2d_flowrings_pool != NULL) {
++		return BCME_OK; /* dhd_prot_init rentry after a dhd_prot_reset */
++	}
++
++	ASSERT(prot->h2d_rings_total == 0);
++
++	/* h2d_rings_total includes H2D common rings: ctrl and rxbuf subn */
++	prot->h2d_rings_total = (uint16)dhd_bus_max_h2d_queues(dhd->bus);
++
++	if (prot->h2d_rings_total < BCMPCIE_H2D_COMMON_MSGRINGS) {
++		DHD_ERROR(("%s: h2d_rings_total advertized as %u\n",
++			__FUNCTION__, prot->h2d_rings_total));
++		return BCME_ERROR;
++	}
++
++	/* Subtract number of H2D common rings, to determine number of flowrings */
++	h2d_flowrings_total = DHD_FLOWRINGS_POOL_TOTAL(prot->h2d_rings_total);
++
++	DHD_ERROR(("Attach flowrings pool for %d rings\n", h2d_flowrings_total));
++
++	/* Allocate pool of msgbuf_ring_t objects for all flowrings */
++	prot->h2d_flowrings_pool = (msgbuf_ring_t *)MALLOCZ(prot->osh,
++		(h2d_flowrings_total * sizeof(msgbuf_ring_t)));
++
++	if (prot->h2d_flowrings_pool == NULL) {
++		DHD_ERROR(("%s: flowrings pool for %d flowrings, alloc failure\n",
++			__FUNCTION__, h2d_flowrings_total));
++		goto fail;
++	}
++
++	/* Setup & Attach a DMA-able buffer to each flowring in the flowring pool */
++	FOREACH_RING_IN_FLOWRINGS_POOL(prot, ring, flowid) {
++		snprintf(ring_name, sizeof(ring_name), "h2dflr_%03u", flowid);
++		ring_name[RING_NAME_MAX_LENGTH - 1] = '\0';
++		if (dhd_prot_ring_attach(dhd, ring, ring_name,
++		        H2DRING_TXPOST_MAX_ITEM, H2DRING_TXPOST_ITEMSIZE,
++		        DHD_FLOWID_TO_RINGID(flowid)) != BCME_OK) {
++			goto attach_fail;
++		}
++	}
++
++	return BCME_OK;
++
++attach_fail:
++	dhd_prot_flowrings_pool_detach(dhd); /* Free entire pool of flowrings */
++
++fail:
++	prot->h2d_rings_total = 0;
++	return BCME_NOMEM;
++
++} /* dhd_prot_flowrings_pool_attach */
++
++
++/**
++ * dhd_prot_flowrings_pool_reset - Reset all msgbuf_ring_t objects in the pool.
++ * Invokes dhd_prot_ring_reset to perform the actual reset.
++ *
++ * The DMA-able buffer is not freed during reset and neither is the flowring
++ * pool freed.
++ *
++ * dhd_prot_flowrings_pool_reset will be invoked in dhd_prot_reset. Following
++ * the dhd_prot_reset, dhd_prot_init will be re-invoked, and the flowring pool
++ * from a previous flowring pool instantiation will be reused.
++ *
++ * This will avoid a fragmented DMA-able memory condition, if multiple
++ * dhd_prot_reset were invoked to reboot the dongle without a full detach/attach
++ * cycle.
++ */
++static void
++dhd_prot_flowrings_pool_reset(dhd_pub_t *dhd)
++{
++	uint16 flowid;
++	msgbuf_ring_t *ring;
++	dhd_prot_t *prot = dhd->prot;
++
++	if (prot->h2d_flowrings_pool == NULL) {
++		ASSERT(prot->h2d_rings_total == 0);
++		return;
++	}
++
++	/* Reset each flowring in the flowring pool */
++	FOREACH_RING_IN_FLOWRINGS_POOL(prot, ring, flowid) {
++		dhd_prot_ring_reset(dhd, ring);
++		ring->inited = FALSE;
++	}
++
++	/* Flowring pool state must be as-if dhd_prot_flowrings_pool_attach */
++}
++
++
++/**
++ * dhd_prot_flowrings_pool_detach - Free pool of msgbuf_ring along with
++ * DMA-able buffers for flowrings.
++ * dhd_prot_ring_detach is invoked to free the DMA-able buffer and perform any
++ * de-initialization of each msgbuf_ring_t.
++ */
++static void
++dhd_prot_flowrings_pool_detach(dhd_pub_t *dhd)
++{
++	int flowid;
++	msgbuf_ring_t *ring;
++	int h2d_flowrings_total; /* exclude H2D common rings */
++	dhd_prot_t *prot = dhd->prot;
++
++	if (prot->h2d_flowrings_pool == NULL) {
++		ASSERT(prot->h2d_rings_total == 0);
++		return;
++	}
++
++	/* Detach the DMA-able buffer for each flowring in the flowring pool */
++	FOREACH_RING_IN_FLOWRINGS_POOL(prot, ring, flowid) {
++		dhd_prot_ring_detach(dhd, ring);
++	}
++
++	h2d_flowrings_total = DHD_FLOWRINGS_POOL_TOTAL(prot->h2d_rings_total);
++
++	MFREE(prot->osh, prot->h2d_flowrings_pool,
++		(h2d_flowrings_total * sizeof(msgbuf_ring_t)));
++
++	prot->h2d_flowrings_pool = (msgbuf_ring_t*)NULL;
++	prot->h2d_rings_total = 0;
++
++} /* dhd_prot_flowrings_pool_detach */
++
++
++/**
++ * dhd_prot_flowrings_pool_fetch - Fetch a preallocated and initialized
++ * msgbuf_ring from the flowring pool, and assign it.
++ *
++ * Unlike common rings, which uses a dhd_prot_ring_init() to pass the common
++ * ring information to the dongle, a flowring's information is passed via a
++ * flowring create control message.
++ *
++ * Only the ring state (WR, RD) index are initialized.
++ */
++static msgbuf_ring_t *
++dhd_prot_flowrings_pool_fetch(dhd_pub_t *dhd, uint16 flowid)
++{
++	msgbuf_ring_t *ring;
++	dhd_prot_t *prot = dhd->prot;
++
++	ASSERT(flowid >= DHD_FLOWRING_START_FLOWID);
++	ASSERT(flowid < prot->h2d_rings_total);
++	ASSERT(prot->h2d_flowrings_pool != NULL);
++
++	ring = DHD_RING_IN_FLOWRINGS_POOL(prot, flowid);
++
++	/* ASSERT flow_ring->inited == FALSE */
++
++	ring->wr = 0;
++	ring->rd = 0;
++	ring->inited = TRUE;
++
++	return ring;
++}
++
++
++/**
++ * dhd_prot_flowrings_pool_release - release a previously fetched flowring's
++ * msgbuf_ring back to the flow_ring pool.
++ */
++void
++dhd_prot_flowrings_pool_release(dhd_pub_t *dhd, uint16 flowid, void *flow_ring)
++{
++	msgbuf_ring_t *ring;
++	dhd_prot_t *prot = dhd->prot;
++
++	ASSERT(flowid >= DHD_FLOWRING_START_FLOWID);
++	ASSERT(flowid < prot->h2d_rings_total);
++	ASSERT(prot->h2d_flowrings_pool != NULL);
++
++	ring = DHD_RING_IN_FLOWRINGS_POOL(prot, flowid);
++
++	ASSERT(ring == (msgbuf_ring_t*)flow_ring);
++	/* ASSERT flow_ring->inited == TRUE */
++
++	(void)dhd_dma_buf_audit(dhd, &ring->dma_buf);
++
++	ring->wr = 0;
++	ring->rd = 0;
++	ring->inited = FALSE;
++}
++
++
++/* Assumes only one index is updated at a time */
++/* If exactly_nitems is true, this function will allocate space for nitems or fail */
++/*    Exception: when wrap around is encountered, to prevent hangup (last nitems of ring buffer) */
++/* If exactly_nitems is false, this function will allocate space for nitems or less */
++static void *BCMFASTPATH
++dhd_prot_get_ring_space(msgbuf_ring_t *ring, uint16 nitems, uint16 * alloced,
++	bool exactly_nitems)
++{
++	void *ret_ptr = NULL;
++	uint16 ring_avail_cnt;
++
++	ASSERT(nitems <= ring->max_items);
++
++	ring_avail_cnt = CHECK_WRITE_SPACE(ring->rd, ring->wr, ring->max_items);
++
++	if ((ring_avail_cnt == 0) ||
++	       (exactly_nitems && (ring_avail_cnt < nitems) &&
++	       ((ring->max_items - ring->wr) >= nitems))) {
++		DHD_INFO(("Space not available: ring %s items %d write %d read %d\n",
++			ring->name, nitems, ring->wr, ring->rd));
++		return NULL;
++	}
++	*alloced = MIN(nitems, ring_avail_cnt);
++
++	/* Return next available space */
++	ret_ptr = (char *)DHD_RING_BGN_VA(ring) + (ring->wr * ring->item_len);
++
++	/* Update write index */
++	if ((ring->wr + *alloced) == ring->max_items) {
++		ring->wr = 0;
++	} else if ((ring->wr + *alloced) < ring->max_items) {
++		ring->wr += *alloced;
++	} else {
++		/* Should never hit this */
++		ASSERT(0);
++		return NULL;
++	}
++
++	return ret_ptr;
++} /* dhd_prot_get_ring_space */
++
++
++/**
++ * dhd_prot_ring_write_complete - Host updates the new WR index on producing
++ * new messages in a H2D ring. The messages are flushed from cache prior to
++ * posting the new WR index. The new WR index will be updated in the DMA index
++ * array or directly in the dongle's ring state memory.
++ * A PCIE doorbell will be generated to wake up the dongle.
++ */
++static void BCMFASTPATH
++dhd_prot_ring_write_complete(dhd_pub_t *dhd, msgbuf_ring_t * ring, void* p,
++	uint16 nitems)
++{
++	dhd_prot_t *prot = dhd->prot;
++
++	/* cache flush */
++	OSL_CACHE_FLUSH(p, ring->item_len * nitems);
++
++	if (DMA_INDX_ENAB(dhd->dma_h2d_ring_upd_support)) {
++		dhd_prot_dma_indx_set(dhd, ring->wr,
++			H2D_DMA_INDX_WR_UPD, ring->idx);
++	} else {
++		dhd_bus_cmn_writeshared(dhd->bus, &(ring->wr),
++			sizeof(uint16), RING_WR_UPD, ring->idx);
++	}
++
++	/* raise h2d interrupt */
++	prot->mb_ring_fn(dhd->bus, ring->wr);
++}
++
++
++/**
++ * dhd_prot_upd_read_idx - Host updates the new RD index on consuming messages
++ * from a D2H ring. The new RD index will be updated in the DMA Index array or
++ * directly in dongle's ring state memory.
++ */
++static void
++dhd_prot_upd_read_idx(dhd_pub_t *dhd, msgbuf_ring_t * ring)
++{
++	/* update read index */
++	/* If dma'ing h2d indices supported
++	 * update the r -indices in the
++	 * host memory o/w in TCM
++	 */
++	if (DMA_INDX_ENAB(dhd->dma_h2d_ring_upd_support)) {
++		dhd_prot_dma_indx_set(dhd, ring->rd,
++			D2H_DMA_INDX_RD_UPD, ring->idx);
++	} else {
++		dhd_bus_cmn_writeshared(dhd->bus, &(ring->rd),
++			sizeof(uint16), RING_RD_UPD, ring->idx);
++	}
++}
++
++
++/**
++ * dhd_prot_dma_indx_set - set a new WR or RD index in the DMA index array.
++ * Dongle will DMA the entire array (if DMA_INDX feature is enabled).
++ * See dhd_prot_dma_indx_init()
++ */
++static void
++dhd_prot_dma_indx_set(dhd_pub_t *dhd, uint16 new_index, uint8 type, uint16 ringid)
++{
++	uint8 *ptr;
++	uint16 offset;
++	dhd_prot_t *prot = dhd->prot;
++
++	switch (type) {
++		case H2D_DMA_INDX_WR_UPD:
++			ptr = (uint8 *)(prot->h2d_dma_indx_wr_buf.va);
++			offset = DHD_H2D_RING_OFFSET(ringid);
++			break;
++
++		case D2H_DMA_INDX_RD_UPD:
++			ptr = (uint8 *)(prot->d2h_dma_indx_rd_buf.va);
++			offset = DHD_D2H_RING_OFFSET(ringid);
++			break;
++
++		default:
++			DHD_ERROR(("%s: Invalid option for DMAing read/write index\n",
++				__FUNCTION__));
++			return;
++	}
++
++	ASSERT(prot->rw_index_sz != 0);
++	ptr += offset * prot->rw_index_sz;
++
++	*(uint16*)ptr = htol16(new_index);
++
++	OSL_CACHE_FLUSH((void *)ptr, prot->rw_index_sz);
++
++	DHD_TRACE(("%s: data %d type %d ringid %d ptr 0x%p offset %d\n",
++		__FUNCTION__, new_index, type, ringid, ptr, offset));
++
++} /* dhd_prot_dma_indx_set */
++
++
++/**
++ * dhd_prot_dma_indx_get - Fetch a WR or RD index from the dongle DMA-ed index
++ * array.
++ * Dongle DMAes an entire array to host memory (if the feature is enabled).
++ * See dhd_prot_dma_indx_init()
++ */
++static uint16
++dhd_prot_dma_indx_get(dhd_pub_t *dhd, uint8 type, uint16 ringid)
++{
++	uint8 *ptr;
++	uint16 data;
++	uint16 offset;
++	dhd_prot_t *prot = dhd->prot;
++
++	switch (type) {
++		case H2D_DMA_INDX_WR_UPD:
++			ptr = (uint8 *)(prot->h2d_dma_indx_wr_buf.va);
++			offset = DHD_H2D_RING_OFFSET(ringid);
++			break;
++
++		case H2D_DMA_INDX_RD_UPD:
++			ptr = (uint8 *)(prot->h2d_dma_indx_rd_buf.va);
++			offset = DHD_H2D_RING_OFFSET(ringid);
++			break;
++
++		case D2H_DMA_INDX_WR_UPD:
++			ptr = (uint8 *)(prot->d2h_dma_indx_wr_buf.va);
++			offset = DHD_D2H_RING_OFFSET(ringid);
++			break;
++
++		case D2H_DMA_INDX_RD_UPD:
++			ptr = (uint8 *)(prot->d2h_dma_indx_rd_buf.va);
++			offset = DHD_D2H_RING_OFFSET(ringid);
++			break;
++
++		default:
++			DHD_ERROR(("%s: Invalid option for DMAing read/write index\n",
++				__FUNCTION__));
++			return 0;
++	}
++
++	ASSERT(prot->rw_index_sz != 0);
++	ptr += offset * prot->rw_index_sz;
++
++	OSL_CACHE_INV((void *)ptr, prot->rw_index_sz);
++
++	data = LTOH16(*((uint16*)ptr));
++
++	DHD_TRACE(("%s: data %d type %d ringid %d ptr 0x%p offset %d\n",
++		__FUNCTION__, data, type, ringid, ptr, offset));
++
++	return (data);
++
++} /* dhd_prot_dma_indx_get */
++
++/**
++ * An array of DMA read/write indices, containing information about host rings, can be maintained
++ * either in host memory or in device memory, dependent on preprocessor options. This function is,
++ * dependent on these options, called during driver initialization. It reserves and initializes
++ * blocks of DMA'able host memory containing an array of DMA read or DMA write indices. The physical
++ * address of these host memory blocks are communicated to the dongle later on. By reading this host
++ * memory, the dongle learns about the state of the host rings.
++ */
++
++static INLINE int
++dhd_prot_dma_indx_alloc(dhd_pub_t *dhd, uint8 type,
++	dhd_dma_buf_t *dma_buf, uint32 bufsz)
++{
++	int rc;
++
++	if ((dma_buf->len == bufsz) || (dma_buf->va != NULL))
++		return BCME_OK;
++
++	rc = dhd_dma_buf_alloc(dhd, dma_buf, bufsz);
++
++	return rc;
++}
++
++int
++dhd_prot_dma_indx_init(dhd_pub_t *dhd, uint32 rw_index_sz, uint8 type, uint32 length)
++{
++	uint32 bufsz;
++	dhd_prot_t *prot = dhd->prot;
++	dhd_dma_buf_t *dma_buf;
++
++	if (prot == NULL) {
++		DHD_ERROR(("prot is not inited\n"));
++		return BCME_ERROR;
++	}
++
++	/* Dongle advertizes 2B or 4B RW index size */
++	ASSERT(rw_index_sz != 0);
++	prot->rw_index_sz = rw_index_sz;
++
++	bufsz = rw_index_sz * length;
++
++	switch (type) {
++		case H2D_DMA_INDX_WR_BUF:
++			dma_buf = &prot->h2d_dma_indx_wr_buf;
++			if (dhd_prot_dma_indx_alloc(dhd, type, dma_buf, bufsz)) {
++				goto ret_no_mem;
++			}
++			DHD_ERROR(("H2D DMA WR INDX : array size %d = %d * %d\n",
++				dma_buf->len, rw_index_sz, length));
++			break;
++
++		case H2D_DMA_INDX_RD_BUF:
++			dma_buf = &prot->h2d_dma_indx_rd_buf;
++			if (dhd_prot_dma_indx_alloc(dhd, type, dma_buf, bufsz)) {
++				goto ret_no_mem;
++			}
++			DHD_ERROR(("H2D DMA RD INDX : array size %d = %d * %d\n",
++				dma_buf->len, rw_index_sz, length));
++			break;
++
++		case D2H_DMA_INDX_WR_BUF:
++			dma_buf = &prot->d2h_dma_indx_wr_buf;
++			if (dhd_prot_dma_indx_alloc(dhd, type, dma_buf, bufsz)) {
++				goto ret_no_mem;
++			}
++			DHD_ERROR(("D2H DMA WR INDX : array size %d = %d * %d\n",
++				dma_buf->len, rw_index_sz, length));
++			break;
++
++		case D2H_DMA_INDX_RD_BUF:
++			dma_buf = &prot->d2h_dma_indx_rd_buf;
++			if (dhd_prot_dma_indx_alloc(dhd, type, dma_buf, bufsz)) {
++				goto ret_no_mem;
++			}
++			DHD_ERROR(("D2H DMA RD INDX : array size %d = %d * %d\n",
++				dma_buf->len, rw_index_sz, length));
++			break;
++
++		default:
++			DHD_ERROR(("%s: Unexpected option\n", __FUNCTION__));
++			return BCME_BADOPTION;
++	}
++
++	return BCME_OK;
++
++ret_no_mem:
++	DHD_ERROR(("%s: dhd_prot_dma_indx_alloc type %d buf_sz %d failure\n",
++		__FUNCTION__, type, bufsz));
++	return BCME_NOMEM;
++
++} /* dhd_prot_dma_indx_init */
++
++
++/**
++ * Called on checking for 'completion' messages from the dongle. Returns next host buffer to read
++ * from, or NULL if there are no more messages to read.
++ */
++static uint8*
++dhd_prot_get_read_addr(dhd_pub_t *dhd, msgbuf_ring_t *ring, uint32 *available_len)
++{
++	uint16 wr;
++	uint16 rd;
++	uint16 depth;
++	uint16 items;
++	void  *read_addr = NULL; /* address of next msg to be read in ring */
++	uint16 d2h_wr = 0;
++
++	DHD_TRACE(("%s: d2h_dma_indx_rd_buf %p, d2h_dma_indx_wr_buf %p\n",
++		__FUNCTION__, (uint32 *)(dhd->prot->d2h_dma_indx_rd_buf.va),
++		(uint32 *)(dhd->prot->d2h_dma_indx_wr_buf.va)));
++
++	/* update write pointer */
++	if (DMA_INDX_ENAB(dhd->dma_d2h_ring_upd_support)) {
++		/* DMAing write/read indices supported */
++		d2h_wr = dhd_prot_dma_indx_get(dhd, D2H_DMA_INDX_WR_UPD, ring->idx);
++		ring->wr = d2h_wr;
++	} else {
++		dhd_bus_cmn_readshared(dhd->bus, &(ring->wr), RING_WR_UPD, ring->idx);
++	}
++
++	wr = ring->wr;
++	rd = ring->rd;
++	depth = ring->max_items;
++
++	/* check for avail space, in number of ring items */
++	items = READ_AVAIL_SPACE(wr, rd, depth);
++	if (items == 0) {
++		return NULL;
++	}
++
++	ASSERT(items < ring->max_items);
++
++	/*
++	 * Note that there are builds where Assert translates to just printk
++	 * so, even if we had hit this condition we would never halt. Now
++	 * dhd_prot_process_msgtype can get into an big loop if this
++	 * happens.
++	 */
++	if (items >= ring->max_items) {
++		DHD_ERROR(("\r\n======================= \r\n"));
++		DHD_ERROR(("%s(): ring %p, ring->name %s, ring->max_items %d, items %d \r\n",
++			__FUNCTION__, ring, ring->name, ring->max_items, items));
++		DHD_ERROR(("wr: %d,  rd: %d,  depth: %d  \r\n", wr, rd, depth));
++		DHD_ERROR(("dhd->busstate %d bus->suspended %d bus->wait_for_d3_ack %d \r\n",
++			dhd->busstate, dhd->bus->suspended, dhd->bus->wait_for_d3_ack));
++		DHD_ERROR(("\r\n======================= \r\n"));
++
++		*available_len = 0;
++		return NULL;
++	}
++
++	/* if space is available, calculate address to be read */
++	read_addr = (char*)ring->dma_buf.va + (rd * ring->item_len);
++
++	/* update read pointer */
++	if ((ring->rd + items) >= ring->max_items) {
++		ring->rd = 0;
++	} else {
++		ring->rd += items;
++	}
++
++	ASSERT(ring->rd < ring->max_items);
++
++	/* convert items to bytes : available_len must be 32bits */
++	*available_len = (uint32)(items * ring->item_len);
++
++#ifndef CUSTOMER_HW_31_2
++	/* cannot use this since the dma ring is allocated as uncached,
++	 * this will cause an assertation
++	 */
++	OSL_CACHE_INV(read_addr, *available_len);
++#endif
++	/* return read address */
++	return read_addr;
++
++} /* dhd_prot_get_read_addr */
++
++/** Creates a flow ring and informs dongle of this event */
++int
++dhd_prot_flow_ring_create(dhd_pub_t *dhd, flow_ring_node_t *flow_ring_node)
++{
++	tx_flowring_create_request_t *flow_create_rqst;
++	msgbuf_ring_t *flow_ring;
++	dhd_prot_t *prot = dhd->prot;
++	unsigned long flags;
++	uint16 alloced = 0;
++	msgbuf_ring_t *ctrl_ring = &prot->h2dring_ctrl_subn;
++
++	/* Fetch a pre-initialized msgbuf_ring from the flowring pool */
++	flow_ring = dhd_prot_flowrings_pool_fetch(dhd, flow_ring_node->flowid);
++	if (flow_ring == NULL) {
++		DHD_ERROR(("%s: dhd_prot_flowrings_pool_fetch TX Flowid %d failed\n",
++			__FUNCTION__, flow_ring_node->flowid));
++		return BCME_NOMEM;
++	}
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	/* Request for ctrl_ring buffer space */
++	flow_create_rqst = (tx_flowring_create_request_t *)
++		dhd_prot_alloc_ring_space(dhd, ctrl_ring, 1, &alloced, FALSE);
++
++	if (flow_create_rqst == NULL) {
++		dhd_prot_flowrings_pool_release(dhd, flow_ring_node->flowid, flow_ring);
++		DHD_ERROR(("%s: Flow Create Req flowid %d - failure ring space\n",
++			__FUNCTION__, flow_ring_node->flowid));
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		return BCME_NOMEM;
++	}
++
++	flow_ring_node->prot_info = (void *)flow_ring;
++
++	/* Common msg buf hdr */
++	flow_create_rqst->msg.msg_type = MSG_TYPE_FLOW_RING_CREATE;
++	flow_create_rqst->msg.if_id = (uint8)flow_ring_node->flow_info.ifindex;
++	flow_create_rqst->msg.request_id = htol32(0); /* TBD */
++
++	flow_create_rqst->msg.epoch = ctrl_ring->seqnum % H2D_EPOCH_MODULO;
++	ctrl_ring->seqnum++;
++
++	/* Update flow create message */
++	flow_create_rqst->tid = flow_ring_node->flow_info.tid;
++	flow_create_rqst->flow_ring_id = htol16((uint16)flow_ring_node->flowid);
++	memcpy(flow_create_rqst->sa, flow_ring_node->flow_info.sa, sizeof(flow_create_rqst->sa));
++	memcpy(flow_create_rqst->da, flow_ring_node->flow_info.da, sizeof(flow_create_rqst->da));
++	/* CAUTION: ring::base_addr already in Little Endian */
++	flow_create_rqst->flow_ring_ptr.low_addr = flow_ring->base_addr.low_addr;
++	flow_create_rqst->flow_ring_ptr.high_addr = flow_ring->base_addr.high_addr;
++	flow_create_rqst->max_items = htol16(H2DRING_TXPOST_MAX_ITEM);
++	flow_create_rqst->len_item = htol16(H2DRING_TXPOST_ITEMSIZE);
++	DHD_ERROR(("%s: Send Flow Create Req flow ID %d for peer " MACDBG
++		" prio %d ifindex %d\n", __FUNCTION__, flow_ring_node->flowid,
++		MAC2STRDBG(flow_ring_node->flow_info.da), flow_ring_node->flow_info.tid,
++		flow_ring_node->flow_info.ifindex));
++
++	/* Update the flow_ring's WRITE index */
++	if (DMA_INDX_ENAB(dhd->dma_h2d_ring_upd_support)) {
++		dhd_prot_dma_indx_set(dhd, flow_ring->wr,
++			H2D_DMA_INDX_WR_UPD, flow_ring->idx);
++	} else {
++		dhd_bus_cmn_writeshared(dhd->bus, &(flow_ring->wr),
++			sizeof(uint16), RING_WR_UPD, flow_ring->idx);
++	}
++
++	/* update control subn ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ctrl_ring, flow_create_rqst, 1);
++
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	return BCME_OK;
++} /* dhd_prot_flow_ring_create */
++
++/** called on receiving MSG_TYPE_FLOW_RING_CREATE_CMPLT message from dongle */
++static void
++dhd_prot_flow_ring_create_response_process(dhd_pub_t *dhd, void *msg)
++{
++	tx_flowring_create_response_t *flow_create_resp = (tx_flowring_create_response_t *)msg;
++
++	DHD_ERROR(("%s: Flow Create Response status = %d Flow %d\n", __FUNCTION__,
++		ltoh16(flow_create_resp->cmplt.status),
++		ltoh16(flow_create_resp->cmplt.flow_ring_id)));
++
++	dhd_bus_flow_ring_create_response(dhd->bus,
++		ltoh16(flow_create_resp->cmplt.flow_ring_id),
++		ltoh16(flow_create_resp->cmplt.status));
++}
++
++/** called on e.g. flow ring delete */
++void dhd_prot_clean_flow_ring(dhd_pub_t *dhd, void *msgbuf_flow_info)
++{
++	msgbuf_ring_t *flow_ring = (msgbuf_ring_t *)msgbuf_flow_info;
++	dhd_prot_ring_detach(dhd, flow_ring);
++	DHD_INFO(("%s Cleaning up Flow \n", __FUNCTION__));
++}
++
++void dhd_prot_print_flow_ring(dhd_pub_t *dhd, void *msgbuf_flow_info,
++	struct bcmstrbuf *strbuf, const char * fmt)
++{
++	const char *default_fmt = "RD %d WR %d\n";
++	msgbuf_ring_t *flow_ring = (msgbuf_ring_t *)msgbuf_flow_info;
++	uint16 rd, wr;
++
++	if (fmt == NULL) {
++		fmt = default_fmt;
++	}
++	dhd_bus_cmn_readshared(dhd->bus, &rd, RING_RD_UPD, flow_ring->idx);
++	dhd_bus_cmn_readshared(dhd->bus, &wr, RING_WR_UPD, flow_ring->idx);
++	bcm_bprintf(strbuf, fmt, rd, wr);
++}
++
++void dhd_prot_print_info(dhd_pub_t *dhd, struct bcmstrbuf *strbuf)
++{
++	dhd_prot_t *prot = dhd->prot;
++	bcm_bprintf(strbuf, "CtrlPost: ");
++	dhd_prot_print_flow_ring(dhd, &prot->h2dring_ctrl_subn, strbuf, NULL);
++	bcm_bprintf(strbuf, "CtrlCpl: ");
++	dhd_prot_print_flow_ring(dhd, &prot->d2hring_ctrl_cpln, strbuf, NULL);
++
++	bcm_bprintf(strbuf, "RxPost: ");
++	bcm_bprintf(strbuf, "RBP %d ", prot->rxbufpost);
++	dhd_prot_print_flow_ring(dhd, &prot->h2dring_rxp_subn, strbuf, NULL);
++	bcm_bprintf(strbuf, "RxCpl: ");
++	dhd_prot_print_flow_ring(dhd, &prot->d2hring_rx_cpln, strbuf, NULL);
++
++	bcm_bprintf(strbuf, "TxCpl: ");
++	dhd_prot_print_flow_ring(dhd, &prot->d2hring_tx_cpln, strbuf, NULL);
++	bcm_bprintf(strbuf, "active_tx_count %d	 pktidmap_avail %d\n",
++		dhd->prot->active_tx_count,
++		DHD_PKTID_AVAIL(dhd->prot->pktid_map_handle));
++}
++
++int
++dhd_prot_flow_ring_delete(dhd_pub_t *dhd, flow_ring_node_t *flow_ring_node)
++{
++	tx_flowring_delete_request_t *flow_delete_rqst;
++	dhd_prot_t *prot = dhd->prot;
++	unsigned long flags;
++	uint16 alloced = 0;
++	msgbuf_ring_t *ring = &prot->h2dring_ctrl_subn;
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	/* Request for ring buffer space */
++	flow_delete_rqst = (tx_flowring_delete_request_t *)
++		dhd_prot_alloc_ring_space(dhd, ring, 1, &alloced, FALSE);
++
++	if (flow_delete_rqst == NULL) {
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		DHD_ERROR(("%s: Flow Delete Req - failure ring space\n", __FUNCTION__));
++		return BCME_NOMEM;
++	}
++
++	/* Common msg buf hdr */
++	flow_delete_rqst->msg.msg_type = MSG_TYPE_FLOW_RING_DELETE;
++	flow_delete_rqst->msg.if_id = (uint8)flow_ring_node->flow_info.ifindex;
++	flow_delete_rqst->msg.request_id = htol32(0); /* TBD */
++
++	flow_delete_rqst->msg.epoch = ring->seqnum % H2D_EPOCH_MODULO;
++	ring->seqnum++;
++
++	/* Update Delete info */
++	flow_delete_rqst->flow_ring_id = htol16((uint16)flow_ring_node->flowid);
++	flow_delete_rqst->reason = htol16(BCME_OK);
++
++	DHD_ERROR(("%s: Send Flow Delete Req RING ID %d for peer " MACDBG
++		" prio %d ifindex %d\n", __FUNCTION__, flow_ring_node->flowid,
++		MAC2STRDBG(flow_ring_node->flow_info.da), flow_ring_node->flow_info.tid,
++		flow_ring_node->flow_info.ifindex));
++
++	/* update ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ring, flow_delete_rqst, 1);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	return BCME_OK;
++}
++
++static void
++dhd_prot_flow_ring_delete_response_process(dhd_pub_t *dhd, void *msg)
++{
++	tx_flowring_delete_response_t *flow_delete_resp = (tx_flowring_delete_response_t *)msg;
++
++	DHD_ERROR(("%s: Flow Delete Response status = %d Flow %d\n", __FUNCTION__,
++		flow_delete_resp->cmplt.status, flow_delete_resp->cmplt.flow_ring_id));
++
++	dhd_bus_flow_ring_delete_response(dhd->bus, flow_delete_resp->cmplt.flow_ring_id,
++		flow_delete_resp->cmplt.status);
++}
++
++int
++dhd_prot_flow_ring_flush(dhd_pub_t *dhd, flow_ring_node_t *flow_ring_node)
++{
++	tx_flowring_flush_request_t *flow_flush_rqst;
++	dhd_prot_t *prot = dhd->prot;
++	unsigned long flags;
++	uint16 alloced = 0;
++	msgbuf_ring_t *ring = &prot->h2dring_ctrl_subn;
++
++	DHD_GENERAL_LOCK(dhd, flags);
++
++	/* Request for ring buffer space */
++	flow_flush_rqst = (tx_flowring_flush_request_t *)
++		dhd_prot_alloc_ring_space(dhd, ring, 1, &alloced, FALSE);
++	if (flow_flush_rqst == NULL) {
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		DHD_ERROR(("%s: Flow Flush Req - failure ring space\n", __FUNCTION__));
++		return BCME_NOMEM;
++	}
++
++	/* Common msg buf hdr */
++	flow_flush_rqst->msg.msg_type = MSG_TYPE_FLOW_RING_FLUSH;
++	flow_flush_rqst->msg.if_id = (uint8)flow_ring_node->flow_info.ifindex;
++	flow_flush_rqst->msg.request_id = htol32(0); /* TBD */
++
++	flow_flush_rqst->msg.epoch = ring->seqnum % H2D_EPOCH_MODULO;
++	ring->seqnum++;
++
++	flow_flush_rqst->flow_ring_id = htol16((uint16)flow_ring_node->flowid);
++	flow_flush_rqst->reason = htol16(BCME_OK);
++
++	DHD_INFO(("%s: Send Flow Flush Req\n", __FUNCTION__));
++
++	/* update ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ring, flow_flush_rqst, 1);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++	return BCME_OK;
++} /* dhd_prot_flow_ring_flush */
++
++static void
++dhd_prot_flow_ring_flush_response_process(dhd_pub_t *dhd, void *msg)
++{
++	tx_flowring_flush_response_t *flow_flush_resp = (tx_flowring_flush_response_t *)msg;
++
++	DHD_INFO(("%s: Flow Flush Response status = %d\n", __FUNCTION__,
++		flow_flush_resp->cmplt.status));
++
++	dhd_bus_flow_ring_flush_response(dhd->bus, flow_flush_resp->cmplt.flow_ring_id,
++		flow_flush_resp->cmplt.status);
++}
++
++/**
++ * Request dongle to configure soft doorbells for D2H rings. Host populated soft
++ * doorbell information is transferred to dongle via the d2h ring config control
++ * message.
++ */
++void
++dhd_msgbuf_ring_config_d2h_soft_doorbell(dhd_pub_t *dhd)
++{
++#if defined(DHD_D2H_SOFT_DOORBELL_SUPPORT)
++	uint16 ring_idx;
++	uint8 *msg_next;
++	void *msg_start;
++	uint16 alloced = 0;
++	unsigned long flags;
++	dhd_prot_t *prot = dhd->prot;
++	ring_config_req_t *ring_config_req;
++	bcmpcie_soft_doorbell_t *soft_doorbell;
++	msgbuf_ring_t *ctrl_ring = &prot->h2dring_ctrl_subn;
++	const uint16 d2h_rings = BCMPCIE_D2H_COMMON_MSGRINGS;
++
++	/* Claim space for d2h_ring number of d2h_ring_config_req_t messages */
++	DHD_GENERAL_LOCK(dhd, flags);
++	msg_start = dhd_prot_alloc_ring_space(dhd, ctrl_ring, d2h_rings, &alloced, TRUE);
++
++	if (msg_start == NULL) {
++		DHD_ERROR(("%s Msgbuf no space for %d D2H ring config soft doorbells\n",
++			__FUNCTION__, d2h_rings));
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		return;
++	}
++
++	msg_next = (uint8*)msg_start;
++
++	for (ring_idx = 0; ring_idx < d2h_rings; ring_idx++) {
++
++		/* position the ring_config_req into the ctrl subm ring */
++		ring_config_req = (ring_config_req_t *)msg_next;
++
++		/* Common msg header */
++		ring_config_req->msg.msg_type = MSG_TYPE_D2H_RING_CONFIG;
++		ring_config_req->msg.if_id = 0;
++		ring_config_req->msg.flags = 0;
++
++		ring_config_req->msg.epoch = ctrl_ring->seqnum % H2D_EPOCH_MODULO;
++		ctrl_ring->seqnum++;
++
++		ring_config_req->msg.request_id = htol32(DHD_FAKE_PKTID); /* unused */
++
++		/* Ring Config subtype and d2h ring_id */
++		ring_config_req->subtype = htol16(D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL);
++		ring_config_req->ring_id = htol16(DHD_D2H_RINGID(ring_idx));
++
++		/* Host soft doorbell configuration */
++		soft_doorbell = &prot->soft_doorbell[ring_idx];
++
++		ring_config_req->soft_doorbell.value = htol32(soft_doorbell->value);
++		ring_config_req->soft_doorbell.haddr.high =
++			htol32(soft_doorbell->haddr.high);
++		ring_config_req->soft_doorbell.haddr.low =
++			htol32(soft_doorbell->haddr.low);
++		ring_config_req->soft_doorbell.items = htol16(soft_doorbell->items);
++		ring_config_req->soft_doorbell.msecs = htol16(soft_doorbell->msecs);
++
++		DHD_INFO(("%s: Soft doorbell haddr 0x%08x 0x%08x value 0x%08x\n",
++			__FUNCTION__, ring_config_req->soft_doorbell.haddr.high,
++			ring_config_req->soft_doorbell.haddr.low,
++			ring_config_req->soft_doorbell.value));
++
++		msg_next = msg_next + ctrl_ring->item_len;
++	}
++
++	/* update control subn ring's WR index and ring doorbell to dongle */
++	dhd_prot_ring_write_complete(dhd, ctrl_ring, msg_start, d2h_rings);
++	DHD_GENERAL_UNLOCK(dhd, flags);
++#endif /* DHD_D2H_SOFT_DOORBELL_SUPPORT */
++}
++
++static void
++dhd_prot_d2h_ring_config_cmplt_process(dhd_pub_t *dhd, void *msg)
++{
++	DHD_INFO(("%s: Ring Config Response - status %d ringid %d\n",
++		__FUNCTION__, ltoh16(((ring_config_resp_t *)msg)->compl_hdr.status),
++		ltoh16(((ring_config_resp_t *)msg)->compl_hdr.flow_ring_id)));
++}
++
++int
++dhd_prot_debug_info_print(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	msgbuf_ring_t *ring;
++	uint16 rd, wr;
++	uint32 intstatus = 0;
++	uint32 intmask = 0;
++	uint32 mbintstatus = 0;
++	uint32 d2h_mb_data = 0;
++	uint32 dma_buf_len;
++
++	DHD_ERROR(("\n ------- DUMPING IOCTL RING RD WR Pointers ------- \r\n"));
++
++	ring = &prot->h2dring_ctrl_subn;
++	dma_buf_len = ring->max_items * ring->item_len;
++	DHD_ERROR(("CtrlPost: Mem Info: BASE(VA) %p BASE(PA) %x:%x SIZE %d \r\n",
++		ring->dma_buf.va, ltoh32(ring->base_addr.high_addr),
++		ltoh32(ring->base_addr.low_addr), dma_buf_len));
++	DHD_ERROR(("CtrlPost: From Host mem: RD: %d WR %d \r\n", ring->rd, ring->wr));
++	dhd_bus_cmn_readshared(dhd->bus, &rd, RING_RD_UPD, ring->idx);
++	dhd_bus_cmn_readshared(dhd->bus, &wr, RING_WR_UPD, ring->idx);
++	DHD_ERROR(("CtrlPost: From Shared Mem: RD: %d WR %d \r\n", rd, wr));
++
++	ring = &prot->d2hring_ctrl_cpln;
++	dma_buf_len = ring->max_items * ring->item_len;
++	DHD_ERROR(("CtrlCpl: Mem Info: BASE(VA) %p BASE(PA) %x:%x SIZE %d \r\n",
++		ring->dma_buf.va, ltoh32(ring->base_addr.high_addr),
++		ltoh32(ring->base_addr.low_addr), dma_buf_len));
++	DHD_ERROR(("CtrlCpl: From Host mem: RD: %d WR %d \r\n", ring->rd, ring->wr));
++	dhd_bus_cmn_readshared(dhd->bus, &rd, RING_RD_UPD, ring->idx);
++	dhd_bus_cmn_readshared(dhd->bus, &wr, RING_WR_UPD, ring->idx);
++	DHD_ERROR(("CtrlCpl: From Shared Mem: RD: %d WR %d \r\n", rd, wr));
++	DHD_ERROR(("CtrlCpl: Expected seq num: %d \r\n", ring->seqnum));
++
++	intstatus = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, PCIMailBoxInt, 0, 0);
++	intmask = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, PCIMailBoxMask, 0, 0);
++	mbintstatus = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, PCID2H_MailBox, 0, 0);
++	dhd_bus_cmn_readshared(dhd->bus, &d2h_mb_data, D2H_MB_DATA, 0);
++
++	DHD_ERROR(("\n ------- DUMPING INTR Status and Masks ------- \r\n"));
++	DHD_ERROR(("intstatus=0x%x intmask=0x%x mbintstatus=0x%x\n,",
++		intstatus, intmask, mbintstatus));
++	DHD_ERROR(("d2h_mb_data=0x%x def_intmask=0x%x \r\n", d2h_mb_data, dhd->bus->def_intmask));
++
++	return 0;
++}
++
++
++int
++dhd_prot_ringupd_dump(dhd_pub_t *dhd, struct bcmstrbuf *b)
++{
++	uint32 *ptr;
++	uint32 value;
++	uint32 i;
++	uint32 max_h2d_queues = dhd_bus_max_h2d_queues(dhd->bus);
++
++	OSL_CACHE_INV((void *)dhd->prot->d2h_dma_indx_wr_buf.va,
++		dhd->prot->d2h_dma_indx_wr_buf.len);
++
++	ptr = (uint32 *)(dhd->prot->d2h_dma_indx_wr_buf.va);
++
++	bcm_bprintf(b, "\n max_tx_queues %d\n", max_h2d_queues);
++
++	bcm_bprintf(b, "\nRPTR block H2D common rings, 0x%04x\n", ptr);
++	value = ltoh32(*ptr);
++	bcm_bprintf(b, "\tH2D CTRL: value 0x%04x\n", value);
++	ptr++;
++	value = ltoh32(*ptr);
++	bcm_bprintf(b, "\tH2D RXPOST: value 0x%04x\n", value);
++
++	ptr++;
++	bcm_bprintf(b, "RPTR block Flow rings , 0x%04x\n", ptr);
++	for (i = BCMPCIE_H2D_COMMON_MSGRINGS; i < max_h2d_queues; i++) {
++		value = ltoh32(*ptr);
++		bcm_bprintf(b, "\tflowring ID %d: value 0x%04x\n", i, value);
++		ptr++;
++	}
++
++	OSL_CACHE_INV((void *)dhd->prot->h2d_dma_indx_rd_buf.va,
++		dhd->prot->h2d_dma_indx_rd_buf.len);
++
++	ptr = (uint32 *)(dhd->prot->h2d_dma_indx_rd_buf.va);
++
++	bcm_bprintf(b, "\nWPTR block D2H common rings, 0x%04x\n", ptr);
++	value = ltoh32(*ptr);
++	bcm_bprintf(b, "\tD2H CTRLCPLT: value 0x%04x\n", value);
++	ptr++;
++	value = ltoh32(*ptr);
++	bcm_bprintf(b, "\tD2H TXCPLT: value 0x%04x\n", value);
++	ptr++;
++	value = ltoh32(*ptr);
++	bcm_bprintf(b, "\tD2H RXCPLT: value 0x%04x\n", value);
++
++	return 0;
++}
++
++uint32
++dhd_prot_metadata_dbg_set(dhd_pub_t *dhd, bool val)
++{
++	dhd_prot_t *prot = dhd->prot;
++#if DHD_DBG_SHOW_METADATA
++	prot->metadata_dbg = val;
++#endif
++	return (uint32)prot->metadata_dbg;
++}
++
++uint32
++dhd_prot_metadata_dbg_get(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	return (uint32)prot->metadata_dbg;
++}
++
++uint32
++dhd_prot_metadatalen_set(dhd_pub_t *dhd, uint32 val, bool rx)
++{
++	dhd_prot_t *prot = dhd->prot;
++	if (rx)
++		prot->rx_metadata_offset = (uint16)val;
++	else
++		prot->tx_metadata_offset = (uint16)val;
++	return dhd_prot_metadatalen_get(dhd, rx);
++}
++
++uint32
++dhd_prot_metadatalen_get(dhd_pub_t *dhd, bool rx)
++{
++	dhd_prot_t *prot = dhd->prot;
++	if (rx)
++		return prot->rx_metadata_offset;
++	else
++		return prot->tx_metadata_offset;
++}
++
++/** optimization to write "n" tx items at a time to ring */
++uint32
++dhd_prot_txp_threshold(dhd_pub_t *dhd, bool set, uint32 val)
++{
++	dhd_prot_t *prot = dhd->prot;
++	if (set)
++		prot->txp_threshold = (uint16)val;
++	val = prot->txp_threshold;
++	return val;
++}
++
++#ifdef DHD_RX_CHAINING
++
++static INLINE void BCMFASTPATH
++dhd_rxchain_reset(rxchain_info_t *rxchain)
++{
++	rxchain->pkt_count = 0;
++}
++
++static void BCMFASTPATH
++dhd_rxchain_frame(dhd_pub_t *dhd, void *pkt, uint ifidx)
++{
++	uint8 *eh;
++	uint8 prio;
++	dhd_prot_t *prot = dhd->prot;
++	rxchain_info_t *rxchain = &prot->rxchain;
++
++	ASSERT(!PKTISCHAINED(pkt));
++	ASSERT(PKTCLINK(pkt) == NULL);
++	ASSERT(PKTCGETATTR(pkt) == 0);
++
++	eh = PKTDATA(dhd->osh, pkt);
++	prio = IP_TOS46(eh + ETHER_HDR_LEN) >> IPV4_TOS_PREC_SHIFT;
++
++	if (rxchain->pkt_count && !(PKT_CTF_CHAINABLE(dhd, ifidx, eh, prio, rxchain->h_sa,
++		rxchain->h_da, rxchain->h_prio))) {
++		/* Different flow - First release the existing chain */
++		dhd_rxchain_commit(dhd);
++	}
++
++	/* For routers, with HNDCTF, link the packets using PKTSETCLINK, */
++	/* so that the chain can be handed off to CTF bridge as is. */
++	if (rxchain->pkt_count == 0) {
++		/* First packet in chain */
++		rxchain->pkthead = rxchain->pkttail = pkt;
++
++		/* Keep a copy of ptr to ether_da, ether_sa and prio */
++		rxchain->h_da = ((struct ether_header *)eh)->ether_dhost;
++		rxchain->h_sa = ((struct ether_header *)eh)->ether_shost;
++		rxchain->h_prio = prio;
++		rxchain->ifidx = ifidx;
++		rxchain->pkt_count++;
++	} else {
++		/* Same flow - keep chaining */
++		PKTSETCLINK(rxchain->pkttail, pkt);
++		rxchain->pkttail = pkt;
++		rxchain->pkt_count++;
++	}
++
++	if ((dhd_rx_pkt_chainable(dhd, ifidx)) && (!ETHER_ISMULTI(rxchain->h_da)) &&
++		((((struct ether_header *)eh)->ether_type == HTON16(ETHER_TYPE_IP)) ||
++		(((struct ether_header *)eh)->ether_type == HTON16(ETHER_TYPE_IPV6)))) {
++		PKTSETCHAINED(dhd->osh, pkt);
++		PKTCINCRCNT(rxchain->pkthead);
++		PKTCADDLEN(rxchain->pkthead, PKTLEN(dhd->osh, pkt));
++	} else {
++		dhd_rxchain_commit(dhd);
++		return;
++	}
++
++	/* If we have hit the max chain length, dispatch the chain and reset */
++	if (rxchain->pkt_count >= DHD_PKT_CTF_MAX_CHAIN_LEN) {
++		dhd_rxchain_commit(dhd);
++	}
++}
++
++static void BCMFASTPATH
++dhd_rxchain_commit(dhd_pub_t *dhd)
++{
++	dhd_prot_t *prot = dhd->prot;
++	rxchain_info_t *rxchain = &prot->rxchain;
++
++	if (rxchain->pkt_count == 0)
++		return;
++
++	/* Release the packets to dhd_linux */
++	dhd_bus_rx_frame(dhd->bus, rxchain->pkthead, rxchain->ifidx, rxchain->pkt_count);
++
++	/* Reset the chain */
++	dhd_rxchain_reset(rxchain);
++}
++
++#endif /* DHD_RX_CHAINING */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_pcie.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_pcie.c
+new file mode 100644
+index 000000000..7da0afe9c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_pcie.c
+@@ -0,0 +1,5662 @@
++/*
++ * DHD Bus Module for PCIE
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_pcie.c 608315 2015-12-24 11:35:38Z $
++ */
++
++
++/* include files */
++#include <typedefs.h>
++#include <bcmutils.h>
++#include <bcmdevs.h>
++#include <siutils.h>
++#include <hndsoc.h>
++#include <hndpmu.h>
++#include <hnd_debug.h>
++#include <sbchipc.h>
++#include <hnd_armtrap.h>
++#if defined(DHD_DEBUG)
++#include <hnd_cons.h>
++#endif /* defined(DHD_DEBUG) */
++#include <dngl_stats.h>
++#include <pcie_core.h>
++#include <dhd.h>
++#include <dhd_bus.h>
++#include <dhd_flowring.h>
++#include <dhd_proto.h>
++#include <dhd_dbg.h>
++#include <dhdioctl.h>
++#include <sdiovar.h>
++#include <bcmmsgbuf.h>
++#include <pcicfg.h>
++#include <dhd_pcie.h>
++#include <bcmpcie.h>
++#include <bcmendian.h>
++#ifdef DHDTCPACK_SUPPRESS
++#include <dhd_ip.h>
++#endif /* DHDTCPACK_SUPPRESS */
++
++#ifdef BCMEMBEDIMAGE
++#include BCMEMBEDIMAGE
++#endif /* BCMEMBEDIMAGE */
++
++#ifdef PCIE_OOB
++#include "ftdi_sio_external.h"
++#endif /* PCIE_OOB */
++
++#define MEMBLOCK	2048		/* Block size used for downloading of dongle image */
++#define MAX_WKLK_IDLE_CHECK	3	/* times wake_lock checked before deciding not to suspend */
++
++#define ARMCR4REG_BANKIDX	(0x40/sizeof(uint32))
++#define ARMCR4REG_BANKPDA	(0x4C/sizeof(uint32))
++/* Temporary war to fix precommit till sync issue between trunk & precommit branch is resolved */
++
++#if defined(SUPPORT_MULTIPLE_BOARD_REV)
++	extern unsigned int system_rev;
++#endif /* SUPPORT_MULTIPLE_BOARD_REV */
++
++int dhd_dongle_memsize;
++int dhd_dongle_ramsize;
++static int dhdpcie_checkdied(dhd_bus_t *bus, char *data, uint size);
++#ifdef DHD_DEBUG
++static int dhdpcie_bus_readconsole(dhd_bus_t *bus);
++#endif /* DHD_DEBUG */
++#if defined(DHD_FW_COREDUMP)
++static int dhdpcie_mem_dump(dhd_bus_t *bus);
++#endif /* DHD_FW_COREDUMP */
++
++static int dhdpcie_bus_membytes(dhd_bus_t *bus, bool write, ulong address, uint8 *data, uint size);
++static int dhdpcie_bus_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
++	const char *name, void *params,
++	int plen, void *arg, int len, int val_size);
++static int dhdpcie_bus_lpback_req(struct  dhd_bus *bus, uint32 intval);
++static int dhdpcie_bus_dmaxfer_req(struct  dhd_bus *bus,
++	uint32 len, uint32 srcdelay, uint32 destdelay);
++static int dhdpcie_bus_download_state(dhd_bus_t *bus, bool enter);
++static int _dhdpcie_download_firmware(struct dhd_bus *bus);
++static int dhdpcie_download_firmware(dhd_bus_t *bus, osl_t *osh);
++static int dhdpcie_bus_write_vars(dhd_bus_t *bus);
++static bool dhdpcie_bus_process_mailbox_intr(dhd_bus_t *bus, uint32 intstatus);
++static bool dhdpci_bus_read_frames(dhd_bus_t *bus);
++static int dhdpcie_readshared(dhd_bus_t *bus);
++static void dhdpcie_init_shared_addr(dhd_bus_t *bus);
++static bool dhdpcie_dongle_attach(dhd_bus_t *bus);
++static void dhdpcie_bus_dongle_setmemsize(dhd_bus_t *bus, int mem_size);
++static void dhdpcie_bus_release_dongle(dhd_bus_t *bus, osl_t *osh,
++	bool dongle_isolation, bool reset_flag);
++static void dhdpcie_bus_release_malloc(dhd_bus_t *bus, osl_t *osh);
++static int dhdpcie_downloadvars(dhd_bus_t *bus, void *arg, int len);
++static uint8 dhdpcie_bus_rtcm8(dhd_bus_t *bus, ulong offset);
++static void dhdpcie_bus_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data);
++static void dhdpcie_bus_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data);
++static uint16 dhdpcie_bus_rtcm16(dhd_bus_t *bus, ulong offset);
++static void dhdpcie_bus_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data);
++static uint32 dhdpcie_bus_rtcm32(dhd_bus_t *bus, ulong offset);
++static void dhdpcie_bus_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data);
++static uint64 dhdpcie_bus_rtcm64(dhd_bus_t *bus, ulong offset);
++static void dhdpcie_bus_cfg_set_bar0_win(dhd_bus_t *bus, uint32 data);
++static void dhdpcie_bus_reg_unmap(osl_t *osh, ulong addr, int size);
++static int dhdpcie_cc_nvmshadow(dhd_bus_t *bus, struct bcmstrbuf *b);
++static void dhdpcie_fw_trap(dhd_bus_t *bus);
++static void dhdpcie_send_mb_data(dhd_bus_t *bus, uint32 h2d_mb_data);
++static void dhd_fillup_ring_sharedptr_info(dhd_bus_t *bus, ring_info_t *ring_info);
++extern void dhd_dpc_kill(dhd_pub_t *dhdp);
++#ifdef CUSTOMER_HW_31_2
++#include <nvram_zae.h>
++#endif /* CUSTOMER_HW_31_2 */
++
++#ifdef BCMEMBEDIMAGE
++static int dhdpcie_download_code_array(dhd_bus_t *bus);
++#endif /* BCMEMBEDIMAGE */
++
++
++#define     PCI_VENDOR_ID_BROADCOM          0x14e4
++
++static void dhd_bus_set_device_wake(struct dhd_bus *bus, bool val);
++extern void wl_nddbg_wpp_log(const char *format, ...);
++#ifdef PCIE_OOB
++static void dhd_bus_doorbell_timeout_reset(struct dhd_bus *bus);
++
++#define DHD_DEFAULT_DOORBELL_TIMEOUT 200	/* ms */
++static uint dhd_doorbell_timeout = DHD_DEFAULT_DOORBELL_TIMEOUT;
++
++#define HOST_WAKE 4   /* GPIO_0 (HOST_WAKE) - Output from WLAN */
++#define DEVICE_WAKE 5  /* GPIO_1 (DEVICE_WAKE) - Input to WLAN */
++#define BIT_WL_REG_ON 6
++#define BIT_BT_REG_ON 7
++
++int gpio_handle_val = 0;
++unsigned char gpio_port = 0;
++unsigned char gpio_direction = 0;
++#define OOB_PORT "ttyUSB0"
++#endif /* PCIE_OOB */
++static bool dhdpcie_check_firmware_compatible(uint32 f_api_version, uint32 h_api_version);
++
++/* IOVar table */
++enum {
++	IOV_INTR = 1,
++	IOV_MEMBYTES,
++	IOV_MEMSIZE,
++	IOV_SET_DOWNLOAD_STATE,
++	IOV_DEVRESET,
++	IOV_VARS,
++	IOV_MSI_SIM,
++	IOV_PCIE_LPBK,
++	IOV_CC_NVMSHADOW,
++	IOV_RAMSIZE,
++	IOV_RAMSTART,
++	IOV_SLEEP_ALLOWED,
++	IOV_PCIE_DMAXFER,
++	IOV_PCIE_SUSPEND,
++	IOV_PCIEREG,
++	IOV_PCIECFGREG,
++	IOV_PCIECOREREG,
++	IOV_PCIESERDESREG,
++	IOV_PCIEASPM,
++	IOV_BAR0_SECWIN_REG,
++	IOV_SBREG,
++	IOV_DONGLEISOLATION,
++	IOV_LTRSLEEPON_UNLOOAD,
++	IOV_METADATA_DBG,
++	IOV_RX_METADATALEN,
++	IOV_TX_METADATALEN,
++	IOV_TXP_THRESHOLD,
++	IOV_BUZZZ_DUMP,
++	IOV_DUMP_RINGUPD_BLOCK,
++	IOV_DMA_RINGINDICES,
++	IOV_FORCE_FW_TRAP,
++	IOV_DB1_FOR_MB,
++	IOV_FLOW_PRIO_MAP,
++	IOV_RXBOUND,
++	IOV_TXBOUND,
++	IOV_HANGREPORT,
++#ifdef PCIE_OOB
++	IOV_OOB_BT_REG_ON,
++	IOV_OOB_ENABLE
++#endif /* PCIE_OOB */
++};
++
++
++const bcm_iovar_t dhdpcie_iovars[] = {
++	{"intr",	IOV_INTR,	0,	IOVT_BOOL,	0 },
++	{"membytes",	IOV_MEMBYTES,	0,	IOVT_BUFFER,	2 * sizeof(int) },
++	{"memsize",	IOV_MEMSIZE,	0,	IOVT_UINT32,	0 },
++	{"dwnldstate",	IOV_SET_DOWNLOAD_STATE,	0,	IOVT_BOOL,	0 },
++	{"vars",	IOV_VARS,	0,	IOVT_BUFFER,	0 },
++	{"devreset",	IOV_DEVRESET,	0,	IOVT_BOOL,	0 },
++	{"pcie_device_trap", IOV_FORCE_FW_TRAP, 0,	0,	0 },
++	{"pcie_lpbk",	IOV_PCIE_LPBK,	0,	IOVT_UINT32,	0 },
++	{"cc_nvmshadow", IOV_CC_NVMSHADOW, 0, IOVT_BUFFER, 0 },
++	{"ramsize",	IOV_RAMSIZE,	0,	IOVT_UINT32,	0 },
++	{"ramstart",	IOV_RAMSTART,	0,	IOVT_UINT32,	0 },
++	{"pciereg",	IOV_PCIEREG,	0,	IOVT_BUFFER,	2 * sizeof(int32) },
++	{"pciecfgreg",	IOV_PCIECFGREG,	0,	IOVT_BUFFER,	2 * sizeof(int32) },
++	{"pciecorereg",	IOV_PCIECOREREG,	0,	IOVT_BUFFER,	2 * sizeof(int32) },
++	{"pcieserdesreg",	IOV_PCIESERDESREG,	0,	IOVT_BUFFER,	3 * sizeof(int32) },
++	{"bar0secwinreg",	IOV_BAR0_SECWIN_REG,	0,	IOVT_BUFFER,	sizeof(sdreg_t) },
++	{"sbreg",	IOV_SBREG,	0,	IOVT_BUFFER,	sizeof(uint8) },
++	{"pcie_dmaxfer",	IOV_PCIE_DMAXFER,	0,	IOVT_BUFFER,	3 * sizeof(int32) },
++	{"pcie_suspend", IOV_PCIE_SUSPEND,	0,	IOVT_UINT32,	0 },
++#ifdef PCIE_OOB
++	{"oob_bt_reg_on", IOV_OOB_BT_REG_ON,    0,  IOVT_UINT32,    0 },
++	{"oob_enable",   IOV_OOB_ENABLE,    0,  IOVT_UINT32,    0 },
++#endif /* PCIE_OOB */
++	{"sleep_allowed",	IOV_SLEEP_ALLOWED,	0,	IOVT_BOOL,	0 },
++	{"dngl_isolation", IOV_DONGLEISOLATION,	0,	IOVT_UINT32,	0 },
++	{"ltrsleep_on_unload", IOV_LTRSLEEPON_UNLOOAD,	0,	IOVT_UINT32,	0 },
++	{"dump_ringupdblk", IOV_DUMP_RINGUPD_BLOCK,	0,	IOVT_BUFFER,	0 },
++	{"dma_ring_indices", IOV_DMA_RINGINDICES,	0,	IOVT_UINT32,	0},
++	{"metadata_dbg", IOV_METADATA_DBG,	0,	IOVT_BOOL,	0 },
++	{"rx_metadata_len", IOV_RX_METADATALEN,	0,	IOVT_UINT32,	0 },
++	{"tx_metadata_len", IOV_TX_METADATALEN,	0,	IOVT_UINT32,	0 },
++	{"db1_for_mb", IOV_DB1_FOR_MB,	0,	IOVT_UINT32,	0 },
++	{"txp_thresh", IOV_TXP_THRESHOLD,	0,	IOVT_UINT32,	0 },
++	{"buzzz_dump", IOV_BUZZZ_DUMP,		0,	IOVT_UINT32,	0 },
++	{"flow_prio_map", IOV_FLOW_PRIO_MAP,	0,	IOVT_UINT32,	0 },
++	{"rxbound",     IOV_RXBOUND,    0,      IOVT_UINT32,    0 },
++	{"txbound",     IOV_TXBOUND,    0,      IOVT_UINT32,    0 },
++	{"aspm", IOV_PCIEASPM, 0, IOVT_INT32, 0 },
++	{"fw_hang_report", IOV_HANGREPORT,	0,	IOVT_BOOL,	0 },
++	{NULL, 0, 0, 0, 0 }
++};
++
++
++#define MAX_READ_TIMEOUT	5 * 1000 * 1000
++
++#ifndef DHD_RXBOUND
++#define DHD_RXBOUND		64
++#endif
++#ifndef DHD_TXBOUND
++#define DHD_TXBOUND		64
++#endif
++uint dhd_rxbound = DHD_RXBOUND;
++uint dhd_txbound = DHD_TXBOUND;
++
++/* Register/Unregister functions are called by the main DHD entry
++ * point (e.g. module insertion) to link with the bus driver, in
++ * order to look for or await the device.
++ */
++
++int
++dhd_bus_register(void)
++{
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	return dhdpcie_bus_register();
++}
++
++void
++dhd_bus_unregister(void)
++{
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	dhdpcie_bus_unregister();
++	return;
++}
++
++
++/** returns a host virtual address */
++uint32 *
++dhdpcie_bus_reg_map(osl_t *osh, ulong addr, int size)
++{
++	return (uint32 *)REG_MAP(addr, size);
++}
++
++void
++dhdpcie_bus_reg_unmap(osl_t *osh, ulong addr, int size)
++{
++	REG_UNMAP((void*)(uintptr)addr);
++	return;
++}
++
++/**
++ * 'regs' is the host virtual address that maps to the start of the PCIe BAR0 window. The first 4096
++ * bytes in this window are mapped to the backplane address in the PCIEBAR0Window register. The
++ * precondition is that the PCIEBAR0Window register 'points' at the PCIe core.
++ *
++ * 'tcm' is the *host* virtual address at which tcm is mapped.
++ */
++dhd_bus_t* dhdpcie_bus_attach(osl_t *osh,
++	volatile char *regs, volatile char *tcm, void *pci_dev)
++{
++	dhd_bus_t *bus;
++
++	DHD_TRACE(("%s: ENTER\n", __FUNCTION__));
++
++	do {
++		if (!(bus = MALLOCZ(osh, sizeof(dhd_bus_t)))) {
++			DHD_ERROR(("%s: MALLOC of dhd_bus_t failed\n", __FUNCTION__));
++			break;
++		}
++
++		bus->regs = regs;
++		bus->tcm = tcm;
++		bus->osh = osh;
++		/* Save pci_dev into dhd_bus, as it may be needed in dhd_attach */
++		bus->dev = (struct pci_dev *)pci_dev;
++
++		dll_init(&bus->const_flowring);
++
++		/* Attach pcie shared structure */
++		if (!(bus->pcie_sh = MALLOCZ(osh, sizeof(pciedev_shared_t)))) {
++			DHD_ERROR(("%s: MALLOC of bus->pcie_sh failed\n", __FUNCTION__));
++			break;
++		}
++
++		/* dhd_common_init(osh); */
++
++		if (dhdpcie_dongle_attach(bus)) {
++			DHD_ERROR(("%s: dhdpcie_probe_attach failed\n", __FUNCTION__));
++			break;
++		}
++
++		/* software resources */
++		if (!(bus->dhd = dhd_attach(osh, bus, PCMSGBUF_HDRLEN))) {
++			DHD_ERROR(("%s: dhd_attach failed\n", __FUNCTION__));
++
++			break;
++		}
++		bus->dhd->busstate = DHD_BUS_DOWN;
++		bus->db1_for_mb = TRUE;
++		bus->dhd->hang_report = TRUE;
++
++		DHD_TRACE(("%s: EXIT SUCCESS\n",
++			__FUNCTION__));
++
++		return bus;
++	} while (0);
++
++	DHD_TRACE(("%s: EXIT FAILURE\n", __FUNCTION__));
++
++	if (bus && bus->pcie_sh) {
++		MFREE(osh, bus->pcie_sh, sizeof(pciedev_shared_t));
++	}
++
++	if (bus) {
++		MFREE(osh, bus, sizeof(dhd_bus_t));
++	}
++	return NULL;
++}
++
++uint
++dhd_bus_chip(struct dhd_bus *bus)
++{
++	ASSERT(bus->sih != NULL);
++	return bus->sih->chip;
++}
++
++uint
++dhd_bus_chiprev(struct dhd_bus *bus)
++{
++	ASSERT(bus);
++	ASSERT(bus->sih != NULL);
++	return bus->sih->chiprev;
++}
++
++void *
++dhd_bus_pub(struct dhd_bus *bus)
++{
++	return bus->dhd;
++}
++
++void *
++dhd_bus_sih(struct dhd_bus *bus)
++{
++	return (void *)bus->sih;
++}
++
++void *
++dhd_bus_txq(struct dhd_bus *bus)
++{
++	return &bus->txq;
++}
++
++/** Get Chip ID version */
++uint dhd_bus_chip_id(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	return  bus->sih->chip;
++}
++
++/** Get Chip Rev ID version */
++uint dhd_bus_chiprev_id(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	return bus->sih->chiprev;
++}
++
++/** Get Chip Pkg ID version */
++uint dhd_bus_chippkg_id(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	return bus->sih->chippkg;
++}
++
++/** Read and clear intstatus. This should be called with interupts disabled or inside isr */
++uint32
++dhdpcie_bus_intstatus(dhd_bus_t *bus)
++{
++	uint32 intstatus = 0;
++	uint32 intmask = 0;
++
++	if ((bus->sih->buscorerev == 6) || (bus->sih->buscorerev == 4) ||
++		(bus->sih->buscorerev == 2)) {
++		intstatus = dhdpcie_bus_cfg_read_dword(bus, PCIIntstatus, 4);
++		dhdpcie_bus_cfg_write_dword(bus, PCIIntstatus, 4, intstatus);
++		intstatus &= I_MB;
++	} else {
++		/* this is a PCIE core register..not a config register... */
++		intstatus = si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxInt, 0, 0);
++
++		/* this is a PCIE core register..not a config register... */
++		intmask = si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxMask, 0, 0);
++
++		/*
++		 * The fourth argument to si_corereg is the "mask" fields of the register to update
++		 * and the fifth field is the "value" to update. Now if we are interested in only
++		 * few fields of the "mask" bit map, we should not be writing back what we read
++		 * By doing so, we might clear/ack interrupts that are not handled yet.
++		 */
++		si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxInt, bus->def_intmask,
++			intstatus);
++
++		intstatus &= intmask;
++
++		/* Is device removed. intstatus & intmask read 0xffffffff */
++		if (intstatus == (uint32)-1) {
++			DHD_ERROR(("%s: !!!!!!Device Removed or dead chip.\n", __FUNCTION__));
++			intstatus = 0;
++		}
++
++		intstatus &= bus->def_intmask;
++	}
++
++	return intstatus;
++}
++
++/**
++ * Name:  dhdpcie_bus_isr
++ * Parameters:
++ * 1: IN int irq   -- interrupt vector
++ * 2: IN void *arg      -- handle to private data structure
++ * Return value:
++ * Status (TRUE or FALSE)
++ *
++ * Description:
++ * Interrupt Service routine checks for the status register,
++ * disable interrupt and queue DPC if mail box interrupts are raised.
++ */
++int32
++dhdpcie_bus_isr(dhd_bus_t *bus)
++{
++	uint32 intstatus = 0;
++
++	do {
++		DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++		/* verify argument */
++		if (!bus) {
++			DHD_ERROR(("%s : bus is null pointer, exit \n", __FUNCTION__));
++			break;
++		}
++
++		if (bus->dhd->dongle_reset) {
++			break;
++		}
++
++		if (bus->dhd->busstate == DHD_BUS_DOWN) {
++			DHD_ERROR(("%s: BUS is down, not processing the interrupt \r\n",
++				__FUNCTION__));
++			break;
++		}
++
++		intstatus = dhdpcie_bus_intstatus(bus);
++
++		/* Check if the interrupt is ours or not */
++		if (intstatus == 0) {
++			break;
++		}
++
++		/* save the intstatus */
++		bus->intstatus = intstatus;
++
++		/*  Overall operation:
++		 *    - Mask further interrupts
++		 *    - Read/ack intstatus
++		 *    - Take action based on bits and state
++		 *    - Reenable interrupts (as per state)
++		 */
++
++		/* Count the interrupt call */
++		bus->intrcount++;
++
++		/* read interrupt status register!! Status bits will be cleared in DPC !! */
++		bus->ipend = TRUE;
++		dhdpcie_bus_intr_disable(bus); /* Disable interrupt!! */
++		bus->intdis = TRUE;
++
++#if defined(PCIE_ISR_THREAD)
++
++		DHD_TRACE(("Calling dhd_bus_dpc() from %s\n", __FUNCTION__));
++		DHD_OS_WAKE_LOCK(bus->dhd);
++		while (dhd_bus_dpc(bus));
++		DHD_OS_WAKE_UNLOCK(bus->dhd);
++#else
++		bus->dpc_sched = TRUE;
++		dhd_sched_dpc(bus->dhd);     /* queue DPC now!! */
++#endif /* defined(SDIO_ISR_THREAD) */
++
++		DHD_TRACE(("%s: Exit Success DPC Queued\n", __FUNCTION__));
++		return TRUE;
++
++	} while (0);
++
++	DHD_TRACE(("%s: Exit Failure\n", __FUNCTION__));
++	return FALSE;
++}
++
++static bool
++dhdpcie_dongle_attach(dhd_bus_t *bus)
++{
++
++	osl_t *osh = bus->osh;
++	void *regsva = (void*)bus->regs;
++	uint16 devid = bus->cl_devid;
++	uint32 val;
++	sbpcieregs_t *sbpcieregs;
++
++	DHD_TRACE(("%s: ENTER\n", __FUNCTION__));
++
++
++	bus->alp_only = TRUE;
++	bus->sih = NULL;
++
++	/* Set bar0 window to si_enum_base */
++	dhdpcie_bus_cfg_set_bar0_win(bus, SI_ENUM_BASE);
++
++	/* Checking PCIe bus status with reading configuration space */
++	val = OSL_PCI_READ_CONFIG(osh, PCI_CFG_VID, sizeof(uint32));
++	if ((val & 0xFFFF) != VENDOR_BROADCOM) {
++		DHD_ERROR(("%s : failed to read PCI configuration space!\n", __FUNCTION__));
++		goto fail;
++	}
++
++	/* si_attach() will provide an SI handle and scan the backplane */
++	if (!(bus->sih = si_attach((uint)devid, osh, regsva, PCI_BUS, bus,
++	                           &bus->vars, &bus->varsz))) {
++		DHD_ERROR(("%s: si_attach failed!\n", __FUNCTION__));
++		goto fail;
++	}
++
++
++	si_setcore(bus->sih, PCIE2_CORE_ID, 0);
++	sbpcieregs = (sbpcieregs_t*)(bus->regs);
++
++	/* WAR where the BAR1 window may not be sized properly */
++	W_REG(osh, &sbpcieregs->configaddr, 0x4e0);
++	val = R_REG(osh, &sbpcieregs->configdata);
++	W_REG(osh, &sbpcieregs->configdata, val);
++
++	/* Get info on the ARM and SOCRAM cores... */
++	/* Should really be qualified by device id */
++	if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
++	    (si_setcore(bus->sih, ARMCM3_CORE_ID, 0)) ||
++	    (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) ||
++	    (si_setcore(bus->sih, ARMCA7_CORE_ID, 0))) {
++		bus->armrev = si_corerev(bus->sih);
++	} else {
++		DHD_ERROR(("%s: failed to find ARM core!\n", __FUNCTION__));
++		goto fail;
++	}
++
++	if (si_setcore(bus->sih, SYSMEM_CORE_ID, 0)) {
++		if (!(bus->orig_ramsize = si_sysmem_size(bus->sih))) {
++			DHD_ERROR(("%s: failed to find SYSMEM memory!\n", __FUNCTION__));
++			goto fail;
++		}
++		/* also populate base address */
++		bus->dongle_ram_base = CA7_4365_RAM_BASE;
++		/* Default reserve 1.75MB for CA7 */
++		bus->orig_ramsize = 0x1c0000;
++	} else if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
++		if (!(bus->orig_ramsize = si_socram_size(bus->sih))) {
++			DHD_ERROR(("%s: failed to find SOCRAM memory!\n", __FUNCTION__));
++			goto fail;
++		}
++	} else {
++		/* cr4 has a different way to find the RAM size from TCM's */
++		if (!(bus->orig_ramsize = si_tcm_size(bus->sih))) {
++			DHD_ERROR(("%s: failed to find CR4-TCM memory!\n", __FUNCTION__));
++			goto fail;
++		}
++		/* also populate base address */
++		switch ((uint16)bus->sih->chip) {
++		case BCM4339_CHIP_ID:
++		case BCM4335_CHIP_ID:
++			bus->dongle_ram_base = CR4_4335_RAM_BASE;
++			break;
++		case BCM4358_CHIP_ID:
++		case BCM4356_CHIP_ID:
++		case BCM4354_CHIP_ID:
++		case BCM43567_CHIP_ID:
++		case BCM43569_CHIP_ID:
++		case BCM4350_CHIP_ID:
++		case BCM43570_CHIP_ID:
++			bus->dongle_ram_base = CR4_4350_RAM_BASE;
++			break;
++		case BCM4360_CHIP_ID:
++			bus->dongle_ram_base = CR4_4360_RAM_BASE;
++			break;
++		CASE_BCM4345_CHIP:
++			bus->dongle_ram_base = (bus->sih->chiprev < 6)  /* changed at 4345C0 */
++				? CR4_4345_LT_C0_RAM_BASE : CR4_4345_GE_C0_RAM_BASE;
++			break;
++		CASE_BCM43602_CHIP:
++			bus->dongle_ram_base = CR4_43602_RAM_BASE;
++			break;
++		case BCM4349_CHIP_GRPID:
++			/* RAM base changed from 4349c0(revid=9) onwards */
++			bus->dongle_ram_base = ((bus->sih->chiprev < 9) ?
++			CR4_4349_RAM_BASE : CR4_4349_RAM_BASE_FROM_REV_9);
++			break;
++		default:
++			bus->dongle_ram_base = 0;
++			DHD_ERROR(("%s: WARNING: Using default ram base at 0x%x\n",
++			           __FUNCTION__, bus->dongle_ram_base));
++		}
++	}
++	bus->ramsize = bus->orig_ramsize;
++	if (dhd_dongle_memsize)
++		dhdpcie_bus_dongle_setmemsize(bus, dhd_dongle_memsize);
++
++	DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d) at 0x%x\n",
++	           bus->ramsize, bus->orig_ramsize, bus->dongle_ram_base));
++
++	bus->srmemsize = si_socram_srmem_size(bus->sih);
++
++
++	bus->def_intmask = PCIE_MB_D2H_MB_MASK | PCIE_MB_TOPCIE_FN0_0 | PCIE_MB_TOPCIE_FN0_1;
++
++	/* Set the poll and/or interrupt flags */
++	bus->intr = (bool)dhd_intr;
++
++	bus->wait_for_d3_ack = 1;
++	bus->suspended = FALSE;
++
++#ifdef PCIE_OOB
++	gpio_handle_val = get_handle(OOB_PORT);
++	if (gpio_handle_val < 0)
++	{
++		DHD_ERROR(("%s: Could not get GPIO handle.\n", __FUNCTION__));
++		ASSERT(FALSE);
++	}
++
++	gpio_direction = 0;
++	ftdi_set_bitmode(gpio_handle_val, 0, BITMODE_BITBANG);
++
++	/* Note BT core is also enabled here */
++	gpio_port = 1 << BIT_WL_REG_ON | 1 << BIT_BT_REG_ON | 1 << DEVICE_WAKE;
++	gpio_write_port(gpio_handle_val, gpio_port);
++
++	gpio_direction = 1 << BIT_WL_REG_ON | 1 << BIT_BT_REG_ON | 1 << DEVICE_WAKE;
++	ftdi_set_bitmode(gpio_handle_val, gpio_direction, BITMODE_BITBANG);
++
++	bus->oob_enabled = TRUE;
++
++	/* drive the Device_Wake GPIO low on startup */
++	bus->device_wake_state = TRUE;
++	dhd_bus_set_device_wake(bus, FALSE);
++	dhd_bus_doorbell_timeout_reset(bus);
++#endif /* PCIE_OOB */
++
++	DHD_TRACE(("%s: EXIT: SUCCESS\n", __FUNCTION__));
++	return 0;
++
++fail:
++	if (bus->sih != NULL) {
++		si_detach(bus->sih);
++		bus->sih = NULL;
++	}
++	DHD_TRACE(("%s: EXIT: FAILURE\n", __FUNCTION__));
++	return -1;
++}
++
++int
++dhpcie_bus_unmask_interrupt(dhd_bus_t *bus)
++{
++	dhdpcie_bus_cfg_write_dword(bus, PCIIntmask, 4, I_MB);
++	return 0;
++}
++int
++dhpcie_bus_mask_interrupt(dhd_bus_t *bus)
++{
++	dhdpcie_bus_cfg_write_dword(bus, PCIIntmask, 4, 0x0);
++	return 0;
++}
++
++void
++dhdpcie_bus_intr_enable(dhd_bus_t *bus)
++{
++	DHD_TRACE(("enable interrupts\n"));
++	if (bus && bus->sih) {
++		if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) ||
++			(bus->sih->buscorerev == 4)) {
++			dhpcie_bus_unmask_interrupt(bus);
++		} else {
++		si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxMask,
++			bus->def_intmask, bus->def_intmask);
++		}
++	}
++}
++
++void
++dhdpcie_bus_intr_disable(dhd_bus_t *bus)
++{
++
++	DHD_TRACE(("%s Enter\n", __FUNCTION__));
++
++	if (bus && bus->sih) {
++		if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) ||
++			(bus->sih->buscorerev == 4)) {
++			dhpcie_bus_mask_interrupt(bus);
++		} else {
++			si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxMask,
++				bus->def_intmask, 0);
++		}
++	}
++	DHD_TRACE(("%s Exit\n", __FUNCTION__));
++}
++
++/*
++ *  dhdpcie_advertise_bus_cleanup advertises that clean up is under progress
++ * to other bus user contexts like Tx, Rx, IOVAR, WD etc and it waits for other contexts
++ * to gracefully exit. All the bus usage contexts before marking busstate as busy, will check for
++ * whether the busstate is DHD_BUS_DOWN or DHD_BUS_DOWN_IN_PROGRESS, if so
++ * they will exit from there itself without marking dhd_bus_busy_state as BUSY.
++ */
++static void
++dhdpcie_advertise_bus_cleanup(dhd_pub_t	 *dhdp)
++{
++	unsigned long flags;
++	int timeleft;
++
++	DHD_GENERAL_LOCK(dhdp, flags);
++	dhdp->busstate = DHD_BUS_DOWN_IN_PROGRESS;
++	DHD_GENERAL_UNLOCK(dhdp, flags);
++
++	timeleft = dhd_os_busbusy_wait_negation(dhdp, &dhdp->dhd_bus_busy_state);
++	if (timeleft == 0) {
++		DHD_ERROR(("%s : Timeout due to dhd_bus_busy_state=0x%x\n",
++				__FUNCTION__, dhdp->dhd_bus_busy_state));
++		BUG_ON(1);
++	}
++
++	return;
++}
++
++static void
++dhdpcie_bus_remove_prep(dhd_bus_t *bus)
++{
++	unsigned long flags;
++	DHD_TRACE(("%s Enter\n", __FUNCTION__));
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	bus->dhd->busstate = DHD_BUS_DOWN;
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	dhd_os_sdlock(bus->dhd);
++
++	dhdpcie_bus_intr_disable(bus);
++
++	if (bus->sih)
++		pcie_watchdog_reset(bus->osh, bus->sih, (sbpcieregs_t *)(bus->regs));
++
++	dhd_os_sdunlock(bus->dhd);
++
++	DHD_TRACE(("%s Exit\n", __FUNCTION__));
++}
++
++/** Detach and free everything */
++void
++dhdpcie_bus_release(dhd_bus_t *bus)
++{
++	bool dongle_isolation = FALSE;
++	osl_t *osh = NULL;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus) {
++
++		osh = bus->osh;
++		ASSERT(osh);
++
++		if (bus->dhd) {
++			dhdpcie_advertise_bus_cleanup(bus->dhd);
++			dongle_isolation = bus->dhd->dongle_isolation;
++			dhdpcie_bus_remove_prep(bus);
++
++			if (bus->intr) {
++				dhdpcie_bus_intr_disable(bus);
++				dhdpcie_free_irq(bus);
++			}
++			dhdpcie_bus_release_dongle(bus, osh, dongle_isolation, TRUE);
++			dhd_detach(bus->dhd);
++			dhd_free(bus->dhd);
++			bus->dhd = NULL;
++		}
++
++		/* unmap the regs and tcm here!! */
++		if (bus->regs) {
++			dhdpcie_bus_reg_unmap(osh, (ulong)bus->regs, DONGLE_REG_MAP_SIZE);
++			bus->regs = NULL;
++		}
++		if (bus->tcm) {
++			dhdpcie_bus_reg_unmap(osh, (ulong)bus->tcm, DONGLE_TCM_MAP_SIZE);
++			bus->tcm = NULL;
++		}
++
++		dhdpcie_bus_release_malloc(bus, osh);
++		/* Detach pcie shared structure */
++		if (bus->pcie_sh) {
++			MFREE(osh, bus->pcie_sh, sizeof(pciedev_shared_t));
++			bus->pcie_sh = NULL;
++		}
++
++#ifdef DHD_DEBUG
++
++		if (bus->console.buf != NULL)
++			MFREE(osh, bus->console.buf, bus->console.bufsize);
++#endif
++
++
++		/* Finally free bus info */
++		MFREE(osh, bus, sizeof(dhd_bus_t));
++
++	}
++
++	DHD_TRACE(("%s: Exit\n", __FUNCTION__));
++} /* dhdpcie_bus_release */
++
++
++void
++dhdpcie_bus_release_dongle(dhd_bus_t *bus, osl_t *osh, bool dongle_isolation, bool reset_flag)
++{
++	DHD_TRACE(("%s: Enter bus->dhd %p bus->dhd->dongle_reset %d \n", __FUNCTION__,
++		bus->dhd, bus->dhd->dongle_reset));
++
++	if ((bus->dhd && bus->dhd->dongle_reset) && reset_flag) {
++		DHD_TRACE(("%s Exit\n", __FUNCTION__));
++		return;
++	}
++
++	if (bus->sih) {
++
++		if (!dongle_isolation)
++			pcie_watchdog_reset(bus->osh, bus->sih, (sbpcieregs_t *)(bus->regs));
++
++		if (bus->ltrsleep_on_unload) {
++			si_corereg(bus->sih, bus->sih->buscoreidx,
++				OFFSETOF(sbpcieregs_t, u.pcie2.ltr_state), ~0, 0);
++		}
++
++		if (bus->sih->buscorerev == 13)
++			 pcie_serdes_iddqdisable(bus->osh, bus->sih, (sbpcieregs_t *)(bus->regs));
++
++		if (bus->sih != NULL) {
++			si_detach(bus->sih);
++			bus->sih = NULL;
++		}
++		if (bus->vars && bus->varsz)
++			MFREE(osh, bus->vars, bus->varsz);
++		bus->vars = NULL;
++	}
++
++	DHD_TRACE(("%s Exit\n", __FUNCTION__));
++}
++
++uint32
++dhdpcie_bus_cfg_read_dword(dhd_bus_t *bus, uint32 addr, uint32 size)
++{
++	uint32 data = OSL_PCI_READ_CONFIG(bus->osh, addr, size);
++	return data;
++}
++
++/** 32 bit config write */
++void
++dhdpcie_bus_cfg_write_dword(dhd_bus_t *bus, uint32 addr, uint32 size, uint32 data)
++{
++	OSL_PCI_WRITE_CONFIG(bus->osh, addr, size, data);
++}
++
++void
++dhdpcie_bus_cfg_set_bar0_win(dhd_bus_t *bus, uint32 data)
++{
++	OSL_PCI_WRITE_CONFIG(bus->osh, PCI_BAR0_WIN, 4, data);
++}
++
++void
++dhdpcie_bus_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
++{
++	int32 min_size =  DONGLE_MIN_MEMSIZE;
++	/* Restrict the memsize to user specified limit */
++	DHD_ERROR(("user: Restrict the dongle ram size to %d, min accepted %d\n",
++		dhd_dongle_memsize, min_size));
++	if ((dhd_dongle_memsize > min_size) &&
++		(dhd_dongle_memsize < (int32)bus->orig_ramsize))
++		bus->ramsize = dhd_dongle_memsize;
++}
++
++void
++dhdpcie_bus_release_malloc(dhd_bus_t *bus, osl_t *osh)
++{
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus->dhd && bus->dhd->dongle_reset)
++		return;
++
++	if (bus->vars && bus->varsz) {
++		MFREE(osh, bus->vars, bus->varsz);
++		bus->vars = NULL;
++	}
++
++	DHD_TRACE(("%s: Exit\n", __FUNCTION__));
++	return;
++
++}
++
++/** Stop bus module: clear pending frames, disable data flow */
++void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
++{
++	uint32 status;
++	unsigned long flags;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (!bus->dhd)
++		return;
++
++	if (bus->dhd->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s: already down by net_dev_reset\n", __FUNCTION__));
++		goto done;
++	}
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	bus->dhd->busstate = DHD_BUS_DOWN;
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	dhdpcie_bus_intr_disable(bus);
++	status =  dhdpcie_bus_cfg_read_dword(bus, PCIIntstatus, 4);
++	dhdpcie_bus_cfg_write_dword(bus, PCIIntstatus, 4, status);
++
++	if (!dhd_download_fw_on_driverload) {
++		dhd_dpc_kill(bus->dhd);
++	}
++
++	/* Clear rx control and wake any waiters */
++	dhd_os_set_ioctl_resp_timeout(IOCTL_DISABLE_TIMEOUT);
++	dhd_wakeup_ioctl_event(bus->dhd, IOCTL_RETURN_ON_BUS_STOP);
++
++done:
++	return;
++}
++
++/** Watchdog timer function */
++bool dhd_bus_watchdog(dhd_pub_t *dhd)
++{
++	unsigned long flags;
++#ifdef DHD_DEBUG
++	dhd_bus_t *bus;
++	bus = dhd->bus;
++
++	DHD_GENERAL_LOCK(dhd, flags);
++	if (dhd->busstate == DHD_BUS_DOWN ||
++			dhd->busstate == DHD_BUS_DOWN_IN_PROGRESS) {
++		DHD_GENERAL_UNLOCK(dhd, flags);
++		return FALSE;
++	}
++	dhd->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_WD;
++	DHD_GENERAL_UNLOCK(dhd, flags);
++
++
++
++	/* Poll for console output periodically */
++	if (dhd->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
++		bus->console.count += dhd_watchdog_ms;
++		if (bus->console.count >= dhd_console_ms) {
++			bus->console.count -= dhd_console_ms;
++			/* Make sure backplane clock is on */
++			if (dhdpcie_bus_readconsole(bus) < 0)
++				dhd_console_ms = 0;	/* On error, stop trying */
++		}
++	}
++#endif /* DHD_DEBUG */
++
++#ifdef PCIE_OOB
++	/* If haven't communicated with device for a while, deassert the Device_Wake GPIO */
++	if (dhd_doorbell_timeout != 0 && !(bus->dhd->busstate == DHD_BUS_SUSPEND) &&
++		dhd_timeout_expired(&bus->doorbell_timer)) {
++		dhd_bus_set_device_wake(bus, FALSE);
++	}
++#endif /* PCIE_OOB */
++
++	DHD_GENERAL_LOCK(dhd, flags);
++	dhd->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_WD;
++	DHD_GENERAL_UNLOCK(dhd, flags);
++	return TRUE;
++} /* dhd_bus_watchdog */
++
++/* Download firmware image and nvram image */
++int
++dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh,
++                          char *pfw_path, char *pnv_path)
++{
++	int ret;
++
++	bus->fw_path = pfw_path;
++	bus->nv_path = pnv_path;
++
++#ifndef CUSTOMER_HW_31_2
++	DHD_ERROR(("%s: firmware path=%s, nvram path=%s\n",
++		__FUNCTION__, bus->fw_path, bus->nv_path));
++#endif
++
++	ret = dhdpcie_download_firmware(bus, osh);
++
++	return ret;
++}
++
++/* Define alternate fw/nvram paths used in Android */
++#define CONFIG_ANDROID_BCMDHD_1_363_125_17_FW_PATH "/vendor/firmware/broadcom/dhd/firmware/fw.bin.trx"
++#define CONFIG_ANDROID_BCMDHD_1_363_125_17_NVRAM_PATH "/vendor/firmware/broadcom/dhd/nvrams/nvm.txt"
++
++static int
++dhdpcie_download_firmware(struct dhd_bus *bus, osl_t *osh)
++{
++	int ret = 0;
++#if defined(BCM_REQUEST_FW)
++	char fw_path[64] = "/lib/firmware/brcm/bcm";	/* path to firmware image */
++	char nv_path[64];		/* path to nvram vars file */
++	bus->fw_path = fw_path;
++	bus->nv_path = nv_path;
++	/* load board specific nvram file */
++	snprintf(bus->nv_path, sizeof(nv_path), "%s", CONFIG_ANDROID_BCMDHD_1_363_125_17_NVRAM_PATH);
++	/* load firmware */
++	snprintf(bus->fw_path, sizeof(fw_path), "%s", CONFIG_ANDROID_BCMDHD_1_363_125_17_FW_PATH);
++#endif /* BCM_REQUEST_FW */
++
++	DHD_OS_WAKE_LOCK(bus->dhd);
++
++	ret = _dhdpcie_download_firmware(bus);
++
++	DHD_OS_WAKE_UNLOCK(bus->dhd);
++	return ret;
++}
++
++static int
++dhdpcie_download_code_file(struct dhd_bus *bus, char *pfw_path)
++{
++	int bcmerror = BCME_ERROR;
++	int offset = 0;
++	int len = 0;
++	bool store_reset;
++	char *imgbuf = NULL;
++	uint8 *memblock = NULL, *memptr;
++
++	DHD_ERROR(("%s: download firmware %s\n", __FUNCTION__, pfw_path));
++
++	/* Should succeed in opening image if it is actually given through registry
++	 * entry or in module param.
++	 */
++	imgbuf = dhd_os_open_image(pfw_path);
++	if (imgbuf == NULL)
++		goto err;
++
++	memptr = memblock = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN);
++	if (memblock == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK));
++		goto err;
++	}
++	if ((uint32)(uintptr)memblock % DHD_SDALIGN)
++		memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN));
++
++	/* check if CR4/CA7 */
++	store_reset = (si_setcore(bus->sih, ARMCR4_CORE_ID, 0) ||
++			si_setcore(bus->sih, ARMCA7_CORE_ID, 0));
++
++	/* Download image with MEMBLOCK size */
++	while ((len = dhd_os_get_image_block((char*)memptr, MEMBLOCK, imgbuf))) {
++		if (len < 0) {
++			DHD_ERROR(("%s: dhd_os_get_image_block failed (%d)\n", __FUNCTION__, len));
++			bcmerror = BCME_ERROR;
++			goto err;
++		}
++		/* if address is 0, store the reset instruction to be written in 0 */
++		if (store_reset) {
++			ASSERT(offset == 0);
++			bus->resetinstr = *(((uint32*)memptr));
++			/* Add start of RAM address to the address given by user */
++			offset += bus->dongle_ram_base;
++			store_reset = FALSE;
++		}
++
++		bcmerror = dhdpcie_bus_membytes(bus, TRUE, offset, (uint8 *)memptr, len);
++		if (bcmerror) {
++			DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
++				__FUNCTION__, bcmerror, MEMBLOCK, offset));
++			goto err;
++		}
++		offset += MEMBLOCK;
++	}
++
++err:
++	if (memblock)
++		MFREE(bus->dhd->osh, memblock, MEMBLOCK + DHD_SDALIGN);
++
++	if (imgbuf)
++		dhd_os_close_image(imgbuf);
++
++	return bcmerror;
++} /* dhdpcie_download_code_file */
++
++static int
++dhdpcie_download_nvram(struct dhd_bus *bus)
++{
++	int bcmerror = BCME_ERROR;
++	uint len;
++	char * memblock = NULL;
++	char *bufp;
++	char *pnv_path;
++	bool nvram_file_exists;
++	bool nvram_uefi_exists = FALSE;
++	bool local_alloc = FALSE;
++	pnv_path = bus->nv_path;
++
++
++#ifdef CUSTOMER_HW_31_2
++	bus->nvram_params = NVRAMARRAY;
++	bus->nvram_params_len = strlen(bus->nvram_params);
++	DHD_TRACE(("%s:--> nvram len %d\n", __FUNCTION__, bus->nvram_params_len));
++#endif
++#ifndef CUSTOMER_HW_31_2
++	nvram_file_exists = ((pnv_path != NULL) && (pnv_path[0] != '\0'));
++
++	/* First try UEFI */
++	len = MAX_NVRAMBUF_SIZE;
++	dhd_get_download_buffer(bus->dhd, NULL, NVRAM, &memblock, &len);
++
++	/* If UEFI empty, then read from file system */
++	if ((len == 0) || (memblock[0] == '\0')) {
++
++		if (nvram_file_exists) {
++			len = MAX_NVRAMBUF_SIZE;
++			dhd_get_download_buffer(bus->dhd, pnv_path, NVRAM, &memblock, &len);
++			if ((len <= 0 || len > MAX_NVRAMBUF_SIZE)) {
++				goto err;
++			}
++		}
++		else {
++			/* For SROM OTP no external file or UEFI required */
++			bcmerror = BCME_OK;
++		}
++	} else {
++		nvram_uefi_exists = TRUE;
++	}
++
++#else
++	if (bus->nvram_params_len) {
++			memblock = MALLOCZ(bus->dhd->osh, MAX_NVRAMBUF_SIZE);
++			if (memblock == NULL) {
++				DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
++						__FUNCTION__, MAX_NVRAMBUF_SIZE));
++				goto err;
++			}
++
++			local_alloc = TRUE;
++			/* nvram is string with null terminated. cannot use strlen */
++			len = bus->nvram_params_len;
++			ASSERT(len <= MAX_NVRAMBUF_SIZE);
++			memcpy(memblock, bus->nvram_params, len);
++			nvram_file_exists = TRUE;
++		}
++#endif /* !CUSTOMER_HW_31_2 */
++
++	if (len > 0 && len <= MAX_NVRAMBUF_SIZE) {
++		bufp = (char *) memblock;
++
++#ifdef CACHE_FW_IMAGES
++		if (bus->processed_nvram_params_len) {
++			len = bus->processed_nvram_params_len;
++		}
++
++		if (!bus->processed_nvram_params_len) {
++			bufp[len] = 0;
++			if (nvram_uefi_exists || nvram_file_exists) {
++				len = process_nvram_vars(bufp, len);
++				bus->processed_nvram_params_len = len;
++			}
++		} else
++#else
++		{
++			bufp[len] = 0;
++			if (nvram_uefi_exists || nvram_file_exists) {
++				len = process_nvram_vars(bufp, len);
++			}
++		}
++#endif /* CACHE_FW_IMAGES */
++
++
++		if (len % 4) {
++			len += 4 - (len % 4);
++		}
++		bufp += len;
++		*bufp++ = 0;
++		if (len)
++			bcmerror = dhdpcie_downloadvars(bus, memblock, len + 1);
++		if (bcmerror) {
++			DHD_ERROR(("%s: error downloading vars: %d\n",
++				__FUNCTION__, bcmerror));
++		}
++	}
++
++
++err:
++	if (memblock) {
++		if (local_alloc) {
++			MFREE(bus->dhd->osh, memblock, MAX_NVRAMBUF_SIZE);
++		} else {
++			dhd_free_download_buffer(bus->dhd, memblock, MAX_NVRAMBUF_SIZE);
++		}
++	}
++
++	return bcmerror;
++}
++
++
++#ifdef BCMEMBEDIMAGE
++int
++dhdpcie_download_code_array(struct dhd_bus *bus)
++{
++	int bcmerror = -1;
++	int offset = 0;
++	unsigned char *p_dlarray  = NULL;
++	unsigned int dlarray_size = 0;
++	unsigned int downloded_len, remaining_len, len;
++	char *p_dlimagename, *p_dlimagever, *p_dlimagedate;
++	uint8 *memblock = NULL, *memptr;
++
++	downloded_len = 0;
++	remaining_len = 0;
++	len = 0;
++
++	p_dlarray = dlarray;
++	dlarray_size = sizeof(dlarray);
++	p_dlimagename = dlimagename;
++	p_dlimagever  = dlimagever;
++	p_dlimagedate = dlimagedate;
++
++	if ((p_dlarray == 0) ||	(dlarray_size == 0) ||(dlarray_size > bus->ramsize) ||
++		(p_dlimagename == 0) ||	(p_dlimagever  == 0) ||	(p_dlimagedate == 0))
++		goto err;
++
++	memptr = memblock = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN);
++	if (memblock == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK));
++		goto err;
++	}
++	if ((uint32)(uintptr)memblock % DHD_SDALIGN)
++		memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN));
++
++	while (downloded_len  < dlarray_size) {
++		remaining_len = dlarray_size - downloded_len;
++		if (remaining_len >= MEMBLOCK)
++			len = MEMBLOCK;
++		else
++			len = remaining_len;
++
++		memcpy(memptr, (p_dlarray + downloded_len), len);
++		/* check if CR4/CA7 */
++		if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0) ||
++			si_setcore(bus->sih, SYSMEM_CORE_ID, 0)) {
++			/* if address is 0, store the reset instruction to be written in 0 */
++			if (offset == 0) {
++				bus->resetinstr = *(((uint32*)memptr));
++				/* Add start of RAM address to the address given by user */
++				offset += bus->dongle_ram_base;
++			}
++		}
++		bcmerror = dhdpcie_bus_membytes(bus, TRUE, offset, (uint8 *)memptr, len);
++		downloded_len += len;
++		if (bcmerror) {
++			DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
++				__FUNCTION__, bcmerror, MEMBLOCK, offset));
++			goto err;
++		}
++		offset += MEMBLOCK;
++	}
++
++#ifdef DHD_DEBUG
++	/* Upload and compare the downloaded code */
++	{
++		unsigned char *ularray = NULL;
++		unsigned int uploded_len;
++		uploded_len = 0;
++		bcmerror = -1;
++		ularray = MALLOC(bus->dhd->osh, dlarray_size);
++		if (ularray == NULL)
++			goto upload_err;
++		/* Upload image to verify downloaded contents. */
++		offset = bus->dongle_ram_base;
++		memset(ularray, 0xaa, dlarray_size);
++		while (uploded_len  < dlarray_size) {
++			remaining_len = dlarray_size - uploded_len;
++			if (remaining_len >= MEMBLOCK)
++				len = MEMBLOCK;
++			else
++				len = remaining_len;
++			bcmerror = dhdpcie_bus_membytes(bus, FALSE, offset,
++				(uint8 *)(ularray + uploded_len), len);
++			if (bcmerror) {
++				DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
++					__FUNCTION__, bcmerror, MEMBLOCK, offset));
++				goto upload_err;
++			}
++
++			uploded_len += len;
++			offset += MEMBLOCK;
++		}
++
++		if (memcmp(p_dlarray, ularray, dlarray_size)) {
++			DHD_ERROR(("%s: Downloaded image is corrupted (%s, %s, %s).\n",
++				__FUNCTION__, p_dlimagename, p_dlimagever, p_dlimagedate));
++			goto upload_err;
++
++		} else
++			DHD_ERROR(("%s: Download, Upload and compare succeeded (%s, %s, %s).\n",
++				__FUNCTION__, p_dlimagename, p_dlimagever, p_dlimagedate));
++upload_err:
++		if (ularray)
++			MFREE(bus->dhd->osh, ularray, dlarray_size);
++	}
++#endif /* DHD_DEBUG */
++err:
++
++	if (memblock)
++		MFREE(bus->dhd->osh, memblock, MEMBLOCK + DHD_SDALIGN);
++
++	return bcmerror;
++} /* dhdpcie_download_code_array */
++#endif /* BCMEMBEDIMAGE */
++
++
++static int
++dhdpcie_ramsize_read_image(struct dhd_bus *bus, char *buf, int len)
++{
++	int bcmerror = BCME_ERROR;
++	char *imgbuf = NULL;
++
++	if (buf == NULL || len == 0)
++		goto err;
++
++	/* External image takes precedence if specified */
++	if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
++		imgbuf = dhd_os_open_image(bus->fw_path);
++		if (imgbuf == NULL) {
++			DHD_ERROR(("%s: Failed to open firmware file\n", __FUNCTION__));
++			goto err;
++		}
++
++		/* Read it */
++		if (len != dhd_os_get_image_block(buf, len, imgbuf)) {
++			DHD_ERROR(("%s: Failed to read %d bytes data\n", __FUNCTION__, len));
++			goto err;
++		}
++
++		bcmerror = BCME_OK;
++	}
++
++err:
++	if (imgbuf)
++		dhd_os_close_image(imgbuf);
++
++	return bcmerror;
++}
++
++/* The ramsize can be changed in the dongle image, for example 4365 chip share the sysmem
++ * with BMC and we can adjust how many sysmem belong to CA7 during dongle compilation.
++ * So in DHD we need to detect this case and update the correct dongle RAMSIZE as well.
++ */
++static void
++dhdpcie_ramsize_adj(struct dhd_bus *bus)
++{
++	int i, search_len = 0;
++	uint8 *memptr = NULL;
++	uint8 *ramsizeptr = NULL;
++	uint ramsizelen;
++	uint32 ramsize_ptr_ptr[] = {RAMSIZE_PTR_PTR_LIST};
++	hnd_ramsize_ptr_t ramsize_info;
++
++	DHD_ERROR(("%s: Enter\n", __FUNCTION__));
++
++	/* Not handle if user restrict dongle ram size enabled */
++	if (dhd_dongle_memsize) {
++		DHD_ERROR(("%s: user restrict dongle ram size to %d.\n", __FUNCTION__,
++			dhd_dongle_memsize));
++		return;
++	}
++
++#ifndef BCMEMBEDIMAGE
++	/* Out immediately if no image to download */
++	if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
++		DHD_ERROR(("%s: no fimrware file\n", __FUNCTION__));
++		return;
++	}
++#endif /* !BCMEMBEDIMAGE */
++
++	/* Get maximum RAMSIZE info search length */
++	for (i = 0; ; i++) {
++		if (ramsize_ptr_ptr[i] == RAMSIZE_PTR_PTR_END)
++			break;
++
++		if (search_len < ramsize_ptr_ptr[i])
++			search_len = ramsize_ptr_ptr[i];
++	}
++
++	if (!search_len)
++		return;
++
++	search_len += sizeof(hnd_ramsize_ptr_t);
++
++	memptr = MALLOC(bus->dhd->osh, search_len);
++	if (memptr == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, search_len));
++		return;
++	}
++
++	/* External image takes precedence if specified */
++	if (dhdpcie_ramsize_read_image(bus, memptr, search_len) != BCME_OK) {
++#ifdef BCMEMBEDIMAGE
++		unsigned char *p_dlarray  = NULL;
++		unsigned int dlarray_size = 0;
++		char *p_dlimagename, *p_dlimagever, *p_dlimagedate;
++
++		p_dlarray = dlarray;
++		dlarray_size = sizeof(dlarray);
++		p_dlimagename = dlimagename;
++		p_dlimagever  = dlimagever;
++		p_dlimagedate = dlimagedate;
++
++		if ((p_dlarray == 0) ||	(dlarray_size == 0) || (p_dlimagename == 0) ||
++			(p_dlimagever  == 0) ||	(p_dlimagedate == 0))
++			goto err;
++
++		ramsizeptr = p_dlarray;
++		ramsizelen = dlarray_size;
++#else
++		goto err;
++#endif /* BCMEMBEDIMAGE */
++	}
++	else {
++		ramsizeptr = memptr;
++		ramsizelen = search_len;
++	}
++
++	if (ramsizeptr) {
++		/* Check Magic */
++		for (i = 0; ; i++) {
++			if (ramsize_ptr_ptr[i] == RAMSIZE_PTR_PTR_END)
++				break;
++
++			if (ramsize_ptr_ptr[i] + sizeof(hnd_ramsize_ptr_t) > ramsizelen)
++				continue;
++
++			memcpy((char *)&ramsize_info, ramsizeptr + ramsize_ptr_ptr[i],
++				sizeof(hnd_ramsize_ptr_t));
++
++			if (ramsize_info.magic == HTOL32(HND_RAMSIZE_PTR_MAGIC)) {
++				bus->orig_ramsize = LTOH32(ramsize_info.ram_size);
++				bus->ramsize = LTOH32(ramsize_info.ram_size);
++				DHD_ERROR(("%s: Adjust dongle RAMSIZE to 0x%x\n", __FUNCTION__,
++					bus->ramsize));
++				break;
++			}
++		}
++	}
++
++err:
++	if (memptr)
++		MFREE(bus->dhd->osh, memptr, search_len);
++
++	return;
++} /* _dhdpcie_download_firmware */
++
++static int
++_dhdpcie_download_firmware(struct dhd_bus *bus)
++{
++	int bcmerror = -1;
++
++	bool embed = FALSE;	/* download embedded firmware */
++	bool dlok = FALSE;	/* download firmware succeeded */
++
++	/* Out immediately if no image to download */
++	if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
++#ifdef BCMEMBEDIMAGE
++		embed = TRUE;
++#else
++		DHD_ERROR(("%s: no fimrware file\n", __FUNCTION__));
++		return 0;
++#endif
++	}
++	/* Adjust ram size */
++	dhdpcie_ramsize_adj(bus);
++
++	/* Keep arm in reset */
++	if (dhdpcie_bus_download_state(bus, TRUE)) {
++		DHD_ERROR(("%s: error placing ARM core in reset\n", __FUNCTION__));
++		goto err;
++	}
++
++	/* External image takes precedence if specified */
++	if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
++		if (dhdpcie_download_code_file(bus, bus->fw_path)) {
++			DHD_ERROR(("%s: dongle image file download failed\n", __FUNCTION__));
++#ifdef BCMEMBEDIMAGE
++			embed = TRUE;
++#else
++			goto err;
++#endif
++		} else {
++			embed = FALSE;
++			dlok = TRUE;
++		}
++	}
++
++#ifdef BCMEMBEDIMAGE
++	if (embed) {
++		if (dhdpcie_download_code_array(bus)) {
++			DHD_ERROR(("%s: dongle image array download failed\n", __FUNCTION__));
++			goto err;
++		} else {
++			dlok = TRUE;
++		}
++	}
++#else
++	BCM_REFERENCE(embed);
++#endif
++	if (!dlok) {
++		DHD_ERROR(("%s: dongle image download failed\n", __FUNCTION__));
++		goto err;
++	}
++
++	/* EXAMPLE: nvram_array */
++	/* If a valid nvram_arry is specified as above, it can be passed down to dongle */
++	/* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
++
++
++	/* External nvram takes precedence if specified */
++	if (dhdpcie_download_nvram(bus)) {
++		DHD_ERROR(("%s: dongle nvram file download failed\n", __FUNCTION__));
++		goto err;
++	}
++
++	/* Take arm out of reset */
++	if (dhdpcie_bus_download_state(bus, FALSE)) {
++		DHD_ERROR(("%s: error getting out of ARM core reset\n", __FUNCTION__));
++		goto err;
++	}
++
++	bcmerror = 0;
++
++err:
++	return bcmerror;
++} /* _dhdpcie_download_firmware */
++
++#define CONSOLE_LINE_MAX	192
++
++#if (defined(DHD_DEBUG) && !defined(CUSTOMER_HW_31_2))
++static int
++dhdpcie_bus_readconsole(dhd_bus_t *bus)
++{
++	dhd_console_t *c = &bus->console;
++	uint8 line[CONSOLE_LINE_MAX], ch;
++	uint32 n, idx, addr;
++	int rv;
++
++	/* Don't do anything until FWREADY updates console address */
++	if (bus->console_addr == 0)
++		return -1;
++
++	/* Read console log struct */
++	addr = bus->console_addr + OFFSETOF(hnd_cons_t, log);
++
++	if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)&c->log, sizeof(c->log))) < 0)
++		return rv;
++
++	/* Allocate console buffer (one time only) */
++	if (c->buf == NULL) {
++		c->bufsize = ltoh32(c->log.buf_size);
++		if ((c->buf = MALLOC(bus->dhd->osh, c->bufsize)) == NULL)
++			return BCME_NOMEM;
++	}
++	idx = ltoh32(c->log.idx);
++
++	/* Protect against corrupt value */
++	if (idx > c->bufsize)
++		return BCME_ERROR;
++
++	/* Skip reading the console buffer if the index pointer has not moved */
++	if (idx == c->last)
++		return BCME_OK;
++
++	/* Read the console buffer */
++	addr = ltoh32(c->log.buf);
++	if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, c->buf, c->bufsize)) < 0)
++		return rv;
++
++	while (c->last != idx) {
++		for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
++			if (c->last == idx) {
++				/* This would output a partial line.  Instead, back up
++				 * the buffer pointer and output this line next time around.
++				 */
++				if (c->last >= n)
++					c->last -= n;
++				else
++					c->last = c->bufsize - n;
++				goto break2;
++			}
++			ch = c->buf[c->last];
++			c->last = (c->last + 1) % c->bufsize;
++			if (ch == '\n')
++				break;
++			line[n] = ch;
++		}
++
++		if (n > 0) {
++			if (line[n - 1] == '\r')
++				n--;
++			line[n] = 0;
++			printf("CONSOLE: %s\n", line);
++
++		}
++	}
++break2:
++
++	return BCME_OK;
++} /* dhdpcie_bus_readconsole */
++#endif /* DHD_DEBUG */
++
++static int
++dhdpcie_checkdied(dhd_bus_t *bus, char *data, uint size)
++{
++	int bcmerror = 0;
++	uint msize = 512;
++	char *mbuffer = NULL;
++	char *console_buffer = NULL;
++	uint maxstrlen = 256;
++	char *str = NULL;
++	trap_t tr;
++	pciedev_shared_t *pciedev_shared = bus->pcie_sh;
++	struct bcmstrbuf strbuf;
++	uint32 console_ptr, console_size, console_index;
++	uint8 line[CONSOLE_LINE_MAX], ch;
++	uint32 n, i, addr;
++	int rv;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (DHD_NOCHECKDIED_ON()) {
++		return 0;
++	}
++
++	if (data == NULL) {
++		/*
++		 * Called after a rx ctrl timeout. "data" is NULL.
++		 * allocate memory to trace the trap or assert.
++		 */
++		size = msize;
++		mbuffer = data = MALLOC(bus->dhd->osh, msize);
++
++		if (mbuffer == NULL) {
++			DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, msize));
++			bcmerror = BCME_NOMEM;
++			goto done;
++		}
++	}
++
++	if ((str = MALLOC(bus->dhd->osh, maxstrlen)) == NULL) {
++		DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, maxstrlen));
++		bcmerror = BCME_NOMEM;
++		goto done;
++	}
++
++	if ((bcmerror = dhdpcie_readshared(bus)) < 0) {
++		goto done;
++	}
++
++	bcm_binit(&strbuf, data, size);
++
++	bcm_bprintf(&strbuf, "msgtrace address : 0x%08X\nconsole address  : 0x%08X\n",
++	            pciedev_shared->msgtrace_addr, pciedev_shared->console_addr);
++
++	if ((pciedev_shared->flags & PCIE_SHARED_ASSERT_BUILT) == 0) {
++		/* NOTE: Misspelled assert is intentional - DO NOT FIX.
++		 * (Avoids conflict with real asserts for programmatic parsing of output.)
++		 */
++		bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
++	}
++
++	if ((bus->pcie_sh->flags & (PCIE_SHARED_ASSERT|PCIE_SHARED_TRAP)) == 0) {
++		/* NOTE: Misspelled assert is intentional - DO NOT FIX.
++		 * (Avoids conflict with real asserts for programmatic parsing of output.)
++		 */
++		bcm_bprintf(&strbuf, "No trap%s in dongle",
++		          (bus->pcie_sh->flags & PCIE_SHARED_ASSERT_BUILT)
++		          ?"/assrt" :"");
++	} else {
++		if (bus->pcie_sh->flags & PCIE_SHARED_ASSERT) {
++			/* Download assert */
++			bcm_bprintf(&strbuf, "Dongle assert");
++			if (bus->pcie_sh->assert_exp_addr != 0) {
++				str[0] = '\0';
++				if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE,
++					bus->pcie_sh->assert_exp_addr,
++					(uint8 *)str, maxstrlen)) < 0) {
++					goto done;
++				}
++
++				str[maxstrlen - 1] = '\0';
++				bcm_bprintf(&strbuf, " expr \"%s\"", str);
++			}
++
++			if (bus->pcie_sh->assert_file_addr != 0) {
++				str[0] = '\0';
++				if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE,
++					bus->pcie_sh->assert_file_addr,
++					(uint8 *)str, maxstrlen)) < 0) {
++					goto done;
++				}
++
++				str[maxstrlen - 1] = '\0';
++				bcm_bprintf(&strbuf, " file \"%s\"", str);
++			}
++
++			bcm_bprintf(&strbuf, " line %d ",  bus->pcie_sh->assert_line);
++		}
++
++		if (bus->pcie_sh->flags & PCIE_SHARED_TRAP) {
++			bus->dhd->dongle_trap_occured = TRUE;
++			if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE,
++				bus->pcie_sh->trap_addr, (uint8*)&tr, sizeof(trap_t))) < 0) {
++				goto done;
++			}
++
++			bcm_bprintf(&strbuf,
++			"\nTRAP type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
++			" lp 0x%x, rpc 0x%x"
++			"\nTrap offset 0x%x, r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, "
++			"r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n\n",
++			ltoh32(tr.type), ltoh32(tr.epc), ltoh32(tr.cpsr), ltoh32(tr.spsr),
++			ltoh32(tr.r13), ltoh32(tr.r14), ltoh32(tr.pc),
++			ltoh32(bus->pcie_sh->trap_addr),
++			ltoh32(tr.r0), ltoh32(tr.r1), ltoh32(tr.r2), ltoh32(tr.r3),
++			ltoh32(tr.r4), ltoh32(tr.r5), ltoh32(tr.r6), ltoh32(tr.r7));
++
++			addr =  bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log);
++			if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr,
++				(uint8 *)&console_ptr, sizeof(console_ptr))) < 0) {
++				goto printbuf;
++			}
++
++			addr =  bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log.buf_size);
++			if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr,
++				(uint8 *)&console_size, sizeof(console_size))) < 0) {
++				goto printbuf;
++			}
++
++			addr =  bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log.idx);
++			if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr,
++				(uint8 *)&console_index, sizeof(console_index))) < 0) {
++				goto printbuf;
++			}
++
++			console_ptr = ltoh32(console_ptr);
++			console_size = ltoh32(console_size);
++			console_index = ltoh32(console_index);
++
++			if (console_size > CONSOLE_BUFFER_MAX ||
++				!(console_buffer = MALLOC(bus->dhd->osh, console_size))) {
++				goto printbuf;
++			}
++
++			if ((rv = dhdpcie_bus_membytes(bus, FALSE, console_ptr,
++				(uint8 *)console_buffer, console_size)) < 0) {
++				goto printbuf;
++			}
++
++			for (i = 0, n = 0; i < console_size; i += n + 1) {
++				for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
++					ch = console_buffer[(console_index + i + n) % console_size];
++					if (ch == '\n')
++						break;
++					line[n] = ch;
++				}
++
++
++				if (n > 0) {
++					if (line[n - 1] == '\r')
++						n--;
++					line[n] = 0;
++					/* Don't use DHD_ERROR macro since we print
++					 * a lot of information quickly. The macro
++					 * will truncate a lot of the printfs
++					 */
++
++					printf("CONSOLE: %s\n", line);
++				}
++			}
++		}
++	}
++
++printbuf:
++	if (bus->pcie_sh->flags & (PCIE_SHARED_ASSERT | PCIE_SHARED_TRAP)) {
++		printf("%s: %s\n", __FUNCTION__, strbuf.origbuf);
++
++		/* wake up IOCTL wait event */
++		dhd_wakeup_ioctl_event(bus->dhd, IOCTL_RETURN_ON_TRAP);
++
++#if defined(DHD_FW_COREDUMP)
++		/* save core dump or write to a file */
++		if (bus->dhd->memdump_enabled) {
++			bus->dhd->memdump_type = DUMP_TYPE_DONGLE_TRAP;
++			dhdpcie_mem_dump(bus);
++		}
++#endif /* DHD_FW_COREDUMP */
++
++
++	}
++
++done:
++	if (mbuffer)
++		MFREE(bus->dhd->osh, mbuffer, msize);
++	if (str)
++		MFREE(bus->dhd->osh, str, maxstrlen);
++
++	if (console_buffer)
++		MFREE(bus->dhd->osh, console_buffer, console_size);
++
++	return bcmerror;
++} /* dhdpcie_checkdied */
++
++
++/* Custom copy of dhdpcie_mem_dump() that can be called at interrupt level */
++void dhdpcie_mem_dump_bugcheck(dhd_bus_t *bus, uint8 *buf)
++{
++	int ret = 0;
++	int size; /* Full mem size */
++	int start; /* Start address */
++	int read_size = 0; /* Read size of each iteration */
++	uint8 *databuf = buf;
++
++	if (bus == NULL) {
++		return;
++	}
++
++	start = bus->dongle_ram_base;
++	/* Get full mem size */
++	size = bus->ramsize;
++	/* Read mem content */
++	while (size)
++	{
++		read_size = MIN(MEMBLOCK, size);
++		if ((ret = dhdpcie_bus_membytes(bus, FALSE, start, databuf, read_size))) {
++			return;
++		}
++
++		/* Decrement size and increment start address */
++		size -= read_size;
++		start += read_size;
++		databuf += read_size;
++	}
++	bus->dhd->soc_ram = buf;
++	bus->dhd->soc_ram_length = bus->ramsize;
++	return;
++}
++
++
++#if defined(DHD_FW_COREDUMP)
++static int
++dhdpcie_mem_dump(dhd_bus_t *bus)
++{
++	int ret = 0;
++	int size; /* Full mem size */
++	int start = bus->dongle_ram_base; /* Start address */
++	int read_size = 0; /* Read size of each iteration */
++	uint8 *buf = NULL, *databuf = NULL;
++
++	/* Get full mem size */
++	size = bus->ramsize;
++	buf = dhd_get_fwdump_buf(bus->dhd, size);
++	if (!buf) {
++		DHD_ERROR(("%s: Out of memory (%d bytes)\n", __FUNCTION__, size));
++		return BCME_ERROR;
++	}
++
++	/* Read mem content */
++	DHD_TRACE_HW4(("Dump dongle memory"));
++	databuf = buf;
++	while (size)
++	{
++		read_size = MIN(MEMBLOCK, size);
++		if ((ret = dhdpcie_bus_membytes(bus, FALSE, start, databuf, read_size)))
++		{
++			DHD_ERROR(("%s: Error membytes %d\n", __FUNCTION__, ret));
++			return BCME_ERROR;
++		}
++		DHD_TRACE(("."));
++
++		/* Decrement size and increment start address */
++		size -= read_size;
++		start += read_size;
++		databuf += read_size;
++	}
++
++	dhd_schedule_memdump(bus->dhd, buf, bus->ramsize);
++
++	/* buf, actually soc_ram free handled in dhd_{free,clear} */
++
++	return ret;
++}
++
++int
++dhd_bus_mem_dump(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++
++	if (bus->suspended) {
++		DHD_ERROR(("%s: Bus is suspend so skip\n", __FUNCTION__));
++		return 0;
++	}
++
++	return dhdpcie_mem_dump(bus);
++}
++#endif /* DHD_FW_COREDUMP */
++
++int
++dhd_socram_dump(dhd_bus_t *bus)
++{
++#if defined(DHD_FW_COREDUMP)
++	return (dhdpcie_mem_dump(bus));
++#else
++	return -1;
++#endif
++}
++
++/**
++ * Transfers bytes from host to dongle using pio mode.
++ * Parameter 'address' is a backplane address.
++ */
++static int
++dhdpcie_bus_membytes(dhd_bus_t *bus, bool write, ulong address, uint8 *data, uint size)
++{
++	uint dsize;
++	int detect_endian_flag = 0x01;
++	bool little_endian;
++
++	/* Detect endianness. */
++	little_endian = *(char *)&detect_endian_flag;
++
++	/* In remap mode, adjust address beyond socram and redirect
++	 * to devram at SOCDEVRAM_BP_ADDR since remap address > orig_ramsize
++	 * is not backplane accessible
++	 */
++
++	/* Determine initial transfer parameters */
++	dsize = sizeof(uint64);
++
++	/* Do the transfer(s) */
++	if (write) {
++		while (size) {
++			if (size >= sizeof(uint64) && little_endian &&
++#ifdef CONFIG_64BIT
++				!(address % 8) &&
++#endif /* CONFIG_64BIT */
++				1) {
++				dhdpcie_bus_wtcm64(bus, address, *((uint64 *)data));
++			} else {
++				dsize = sizeof(uint8);
++				dhdpcie_bus_wtcm8(bus, address, *data);
++			}
++
++			/* Adjust for next transfer (if any) */
++			if ((size -= dsize)) {
++				data += dsize;
++				address += dsize;
++			}
++		}
++	} else {
++		while (size) {
++			if (size >= sizeof(uint64) && little_endian &&
++#ifdef CONFIG_64BIT
++				!(address % 8) &&
++#endif /* CONFIG_64BIT */
++				1) {
++				*(uint64 *)data = dhdpcie_bus_rtcm64(bus, address);
++			} else {
++				dsize = sizeof(uint8);
++				*data = dhdpcie_bus_rtcm8(bus, address);
++			}
++
++			/* Adjust for next transfer (if any) */
++			if ((size -= dsize) > 0) {
++				data += dsize;
++				address += dsize;
++			}
++		}
++	}
++	return BCME_OK;
++} /* dhdpcie_bus_membytes */
++
++/**
++ * Transfers one transmit (ethernet) packet that was queued in the (flow controlled) flow ring queue
++ * to the (non flow controlled) flow ring.
++ */
++int BCMFASTPATH
++dhd_bus_schedule_queue(struct dhd_bus  *bus, uint16 flow_id, bool txs)
++{
++	flow_ring_node_t *flow_ring_node;
++	int ret = BCME_OK;
++#ifdef DHD_LOSSLESS_ROAMING
++	dhd_pub_t *dhdp = bus->dhd;
++#endif
++	DHD_INFO(("%s: flow_id is %d\n", __FUNCTION__, flow_id));
++
++	/* ASSERT on flow_id */
++	if (flow_id >= bus->max_sub_queues) {
++		DHD_ERROR(("%s: flow_id is invalid %d, max %d\n", __FUNCTION__,
++			flow_id, bus->max_sub_queues));
++		return 0;
++	}
++
++	flow_ring_node = DHD_FLOW_RING(bus->dhd, flow_id);
++
++#ifdef DHD_LOSSLESS_ROAMING
++	if ((dhdp->dequeue_prec_map & (1 << flow_ring_node->flow_info.tid)) == 0) {
++		DHD_INFO(("%s: tid %d is not in precedence map. block scheduling\n",
++			__FUNCTION__, flow_ring_node->flow_info.tid));
++		return BCME_OK;
++	}
++#endif /* DHD_LOSSLESS_ROAMING */
++
++	{
++		unsigned long flags;
++		void *txp = NULL;
++		flow_queue_t *queue;
++#ifdef DHD_LOSSLESS_ROAMING
++		struct ether_header *eh;
++		uint8 *pktdata;
++#endif /* DHD_LOSSLESS_ROAMING */
++
++		queue = &flow_ring_node->queue; /* queue associated with flow ring */
++
++		DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++
++		if (flow_ring_node->status != FLOW_RING_STATUS_OPEN) {
++			DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++			return BCME_NOTREADY;
++		}
++
++		while ((txp = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) {
++			PKTORPHAN(txp);
++
++			/*
++			 * Modifying the packet length caused P2P cert failures.
++			 * Specifically on test cases where a packet of size 52 bytes
++			 * was injected, the sniffer capture showed 62 bytes because of
++			 * which the cert tests failed. So making the below change
++			 * only Router specific.
++			 */
++
++#ifdef DHDTCPACK_SUPPRESS
++			if (bus->dhd->tcpack_sup_mode != TCPACK_SUP_HOLD) {
++				ret = dhd_tcpack_check_xmit(bus->dhd, txp);
++				if (ret != BCME_OK) {
++					DHD_ERROR(("%s: dhd_tcpack_check_xmit() error.\n",
++						__FUNCTION__));
++				}
++			}
++#endif /* DHDTCPACK_SUPPRESS */
++#ifdef DHD_LOSSLESS_ROAMING
++			pktdata = (uint8 *)PKTDATA(OSH_NULL, txp);
++			eh = (struct ether_header *) pktdata;
++			if (eh->ether_type == hton16(ETHER_TYPE_802_1X)) {
++				uint8 prio = (uint8)PKTPRIO(txp);
++
++				/* Restore to original priority for 802.1X packet */
++				if (prio == PRIO_8021D_NC) {
++					PKTSETPRIO(txp, PRIO_8021D_BE);
++				}
++			}
++#endif /* DHD_LOSSLESS_ROAMING */
++
++			/* Attempt to transfer packet over flow ring */
++			ret = dhd_prot_txdata(bus->dhd, txp, flow_ring_node->flow_info.ifindex);
++			if (ret != BCME_OK) { /* may not have resources in flow ring */
++				DHD_INFO(("%s: Reinserrt %d\n", __FUNCTION__, ret));
++				dhd_prot_txdata_write_flush(bus->dhd, flow_id, FALSE);
++				/* reinsert at head */
++				dhd_flow_queue_reinsert(bus->dhd, queue, txp);
++				DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++
++				/* If we are able to requeue back, return success */
++				return BCME_OK;
++			}
++		}
++
++		dhd_prot_txdata_write_flush(bus->dhd, flow_id, FALSE);
++
++		DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++	}
++
++	return ret;
++} /* dhd_bus_schedule_queue */
++
++/** Sends an (ethernet) data frame (in 'txp') to the dongle. Callee disposes of txp. */
++int BCMFASTPATH
++dhd_bus_txdata(struct dhd_bus *bus, void *txp, uint8 ifidx)
++{
++	uint16 flowid;
++	flow_queue_t *queue;
++	flow_ring_node_t *flow_ring_node;
++	unsigned long flags;
++	int ret = BCME_OK;
++	void *txp_pend = NULL;
++
++	if (!bus->dhd->flowid_allocator) {
++		DHD_ERROR(("%s: Flow ring not intited yet  \n", __FUNCTION__));
++		goto toss;
++	}
++
++	flowid = DHD_PKT_GET_FLOWID(txp);
++
++	flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid);
++
++	DHD_TRACE(("%s: pkt flowid %d, status %d active %d\n",
++		__FUNCTION__, flowid, flow_ring_node->status,
++		flow_ring_node->active));
++
++	DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++	if ((flowid >= bus->dhd->num_flow_rings) ||
++		(!flow_ring_node->active) ||
++		(flow_ring_node->status == FLOW_RING_STATUS_DELETE_PENDING) ||
++		(flow_ring_node->status == FLOW_RING_STATUS_STA_FREEING)) {
++		DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++		DHD_INFO(("%s: Dropping pkt flowid %d, status %d active %d\n",
++			__FUNCTION__, flowid, flow_ring_node->status,
++			flow_ring_node->active));
++		ret = BCME_ERROR;
++		goto toss;
++	}
++
++	queue = &flow_ring_node->queue; /* queue associated with flow ring */
++
++	if ((ret = dhd_flow_queue_enqueue(bus->dhd, queue, txp)) != BCME_OK) {
++		txp_pend = txp;
++	}
++
++	DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++
++	if (flow_ring_node->status) {
++		DHD_INFO(("%s: Enq pkt flowid %d, status %d active %d\n",
++			__FUNCTION__, flowid, flow_ring_node->status,
++			flow_ring_node->active));
++		if (txp_pend) {
++			txp = txp_pend;
++			goto toss;
++		}
++		return BCME_OK;
++	}
++	ret = dhd_bus_schedule_queue(bus, flowid, FALSE); /* from queue to flowring */
++
++	/* If we have anything pending, try to push into q */
++	if (txp_pend) {
++		DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++
++		if ((ret = dhd_flow_queue_enqueue(bus->dhd, queue, txp_pend)) != BCME_OK) {
++			DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++			txp = txp_pend;
++			goto toss;
++		}
++
++		DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++	}
++
++	return ret;
++
++toss:
++	DHD_INFO(("%s: Toss %d\n", __FUNCTION__, ret));
++#ifdef CUSTOMER_HW_31_2
++	dhd_txcomplete(bus->dhd->osh, txp, TRUE);
++#else
++	PKTCFREE(bus->dhd->osh, txp, TRUE);
++#endif
++	return ret;
++} /* dhd_bus_txdata */
++
++
++void
++dhd_bus_stop_queue(struct dhd_bus *bus)
++{
++	dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, ON);
++	bus->bus_flowctrl = TRUE;
++}
++
++void
++dhd_bus_start_queue(struct dhd_bus *bus)
++{
++	dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, OFF);
++	bus->bus_flowctrl = TRUE;
++}
++
++#if defined(DHD_DEBUG)
++/* Device console input function */
++int dhd_bus_console_in(dhd_pub_t *dhd, uchar *msg, uint msglen)
++{
++	dhd_bus_t *bus = dhd->bus;
++	uint32 addr, val;
++	int rv;
++	/* Address could be zero if CONSOLE := 0 in dongle Makefile */
++	if (bus->console_addr == 0)
++		return BCME_UNSUPPORTED;
++
++	/* Don't allow input if dongle is in reset */
++	if (bus->dhd->dongle_reset) {
++		dhd_os_sdunlock(bus->dhd);
++		return BCME_NOTREADY;
++	}
++
++	/* Zero cbuf_index */
++	addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf_idx);
++	val = htol32(0);
++	if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0)
++		goto done;
++
++	/* Write message into cbuf */
++	addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf);
++	if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)msg, msglen)) < 0)
++		goto done;
++
++	/* Write length into vcons_in */
++	addr = bus->console_addr + OFFSETOF(hnd_cons_t, vcons_in);
++	val = htol32(msglen);
++	if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0)
++		goto done;
++
++	/* generate an interrupt to dongle to indicate that it needs to process cons command */
++	dhdpcie_send_mb_data(bus, H2D_HOST_CONS_INT);
++done:
++	return rv;
++} /* dhd_bus_console_in */
++#endif /* defined(DHD_DEBUG) */
++
++/**
++ * Called on frame reception, the frame was received from the dongle on interface 'ifidx' and is
++ * contained in 'pkt'. Processes rx frame, forwards up the layer to netif.
++ */
++void BCMFASTPATH
++dhd_bus_rx_frame(struct dhd_bus *bus, void* pkt, int ifidx, uint pkt_count)
++{
++	dhd_rx_frame(bus->dhd, ifidx, pkt, pkt_count, 0);
++}
++
++/** 'offset' is a backplane address */
++void
++dhdpcie_bus_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data)
++{
++	*(volatile uint8 *)(bus->tcm + offset) = (uint8)data;
++}
++
++uint8
++dhdpcie_bus_rtcm8(dhd_bus_t *bus, ulong offset)
++{
++	volatile uint8 data;
++
++		data = *(volatile uint8 *)(bus->tcm + offset);
++
++	return data;
++}
++
++void
++dhdpcie_bus_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data)
++{
++	*(volatile uint32 *)(bus->tcm + offset) = (uint32)data;
++}
++void
++dhdpcie_bus_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data)
++{
++	*(volatile uint16 *)(bus->tcm + offset) = (uint16)data;
++}
++void
++dhdpcie_bus_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data)
++{
++	*(volatile uint64 *)(bus->tcm + offset) = (uint64)data;
++}
++
++uint16
++dhdpcie_bus_rtcm16(dhd_bus_t *bus, ulong offset)
++{
++	volatile uint16 data;
++
++		data = *(volatile uint16 *)(bus->tcm + offset);
++
++	return data;
++}
++
++uint32
++dhdpcie_bus_rtcm32(dhd_bus_t *bus, ulong offset)
++{
++	volatile uint32 data;
++
++		data = *(volatile uint32 *)(bus->tcm + offset);
++
++	return data;
++}
++
++uint64
++dhdpcie_bus_rtcm64(dhd_bus_t *bus, ulong offset)
++{
++	volatile uint64 data;
++
++		data = *(volatile uint64 *)(bus->tcm + offset);
++
++	return data;
++}
++
++/** A snippet of dongle memory is shared between host and dongle */
++void
++dhd_bus_cmn_writeshared(dhd_bus_t *bus, void *data, uint32 len, uint8 type, uint16 ringid)
++{
++	uint64 long_data;
++	ulong tcm_offset;
++
++	DHD_INFO(("%s: writing to dongle type %d len %d\n", __FUNCTION__, type, len));
++
++	switch (type) {
++		case D2H_DMA_SCRATCH_BUF:
++		{
++			pciedev_shared_t *sh = (pciedev_shared_t*)bus->shared_addr;
++			long_data = HTOL64(*(uint64 *)data);
++			tcm_offset = (ulong)&(sh->host_dma_scratch_buffer);
++			dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len);
++			prhex(__FUNCTION__, data, len);
++			break;
++		}
++
++		case D2H_DMA_SCRATCH_BUF_LEN:
++		{
++			pciedev_shared_t *sh = (pciedev_shared_t*)bus->shared_addr;
++			tcm_offset = (ulong)&(sh->host_dma_scratch_buffer_len);
++			dhdpcie_bus_wtcm32(bus, tcm_offset, (uint32) HTOL32(*(uint32 *)data));
++			prhex(__FUNCTION__, data, len);
++			break;
++		}
++
++		case H2D_DMA_INDX_WR_BUF:
++		{
++			pciedev_shared_t *shmem = (pciedev_shared_t *)bus->pcie_sh;
++
++			long_data = HTOL64(*(uint64 *)data);
++			tcm_offset = (ulong)shmem->rings_info_ptr;
++			tcm_offset += OFFSETOF(ring_info_t, h2d_w_idx_hostaddr);
++			dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len);
++			prhex(__FUNCTION__, data, len);
++			break;
++		}
++
++		case H2D_DMA_INDX_RD_BUF:
++		{
++			pciedev_shared_t *shmem = (pciedev_shared_t *)bus->pcie_sh;
++			long_data = HTOL64(*(uint64 *)data);
++			tcm_offset = (ulong)shmem->rings_info_ptr;
++			tcm_offset += OFFSETOF(ring_info_t, h2d_r_idx_hostaddr);
++			dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len);
++			prhex(__FUNCTION__, data, len);
++			break;
++		}
++
++		case D2H_DMA_INDX_WR_BUF:
++		{
++			pciedev_shared_t *shmem = (pciedev_shared_t *)bus->pcie_sh;
++			long_data = HTOL64(*(uint64 *)data);
++			tcm_offset = (ulong)shmem->rings_info_ptr;
++			tcm_offset += OFFSETOF(ring_info_t, d2h_w_idx_hostaddr);
++			dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len);
++			prhex(__FUNCTION__, data, len);
++			break;
++		}
++
++		case D2H_DMA_INDX_RD_BUF:
++		{
++			pciedev_shared_t *shmem = (pciedev_shared_t *)bus->pcie_sh;
++			long_data = HTOL64(*(uint64 *)data);
++			tcm_offset = (ulong)shmem->rings_info_ptr;
++			tcm_offset += OFFSETOF(ring_info_t, d2h_r_idx_hostaddr);
++			dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len);
++			prhex(__FUNCTION__, data, len);
++			break;
++		}
++
++		case RING_ITEM_LEN:
++			tcm_offset = bus->ring_sh[ringid].ring_mem_addr;
++			tcm_offset += OFFSETOF(ring_mem_t, len_items);
++			dhdpcie_bus_wtcm16(bus, tcm_offset, (uint16) HTOL16(*(uint16 *)data));
++			break;
++
++		case RING_MAX_ITEMS:
++			tcm_offset = bus->ring_sh[ringid].ring_mem_addr;
++			tcm_offset += OFFSETOF(ring_mem_t, max_item);
++			dhdpcie_bus_wtcm16(bus, tcm_offset, (uint16) HTOL16(*(uint16 *)data));
++			break;
++
++		case RING_BUF_ADDR:
++			long_data = HTOL64(*(uint64 *)data);
++			tcm_offset = bus->ring_sh[ringid].ring_mem_addr;
++			tcm_offset += OFFSETOF(ring_mem_t, base_addr);
++			dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8 *) &long_data, len);
++			prhex(__FUNCTION__, data, len);
++			break;
++
++		case RING_WR_UPD:
++			tcm_offset = bus->ring_sh[ringid].ring_state_w;
++			dhdpcie_bus_wtcm16(bus, tcm_offset, (uint16) HTOL16(*(uint16 *)data));
++			break;
++
++		case RING_RD_UPD:
++			tcm_offset = bus->ring_sh[ringid].ring_state_r;
++			dhdpcie_bus_wtcm16(bus, tcm_offset, (uint16) HTOL16(*(uint16 *)data));
++			break;
++
++		case D2H_MB_DATA:
++			dhdpcie_bus_wtcm32(bus, bus->d2h_mb_data_ptr_addr,
++				(uint32) HTOL32(*(uint32 *)data));
++			break;
++
++		case H2D_MB_DATA:
++			dhdpcie_bus_wtcm32(bus, bus->h2d_mb_data_ptr_addr,
++				(uint32) HTOL32(*(uint32 *)data));
++			break;
++
++		default:
++			break;
++	}
++} /* dhd_bus_cmn_writeshared */
++
++/** A snippet of dongle memory is shared between host and dongle */
++void
++dhd_bus_cmn_readshared(dhd_bus_t *bus, void* data, uint8 type, uint16 ringid)
++{
++	ulong tcm_offset;
++
++	switch (type) {
++		case RING_WR_UPD:
++			tcm_offset = bus->ring_sh[ringid].ring_state_w;
++			*(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, tcm_offset));
++			break;
++		case RING_RD_UPD:
++			tcm_offset = bus->ring_sh[ringid].ring_state_r;
++			*(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, tcm_offset));
++			break;
++		case TOTAL_LFRAG_PACKET_CNT:
++		{
++			pciedev_shared_t *sh = (pciedev_shared_t*)bus->shared_addr;
++			*(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus,
++				(ulong) &sh->total_lfrag_pkt_cnt));
++			break;
++		}
++		case H2D_MB_DATA:
++			*(uint32*)data = LTOH32(dhdpcie_bus_rtcm32(bus, bus->h2d_mb_data_ptr_addr));
++			break;
++		case D2H_MB_DATA:
++			*(uint32*)data = LTOH32(dhdpcie_bus_rtcm32(bus, bus->d2h_mb_data_ptr_addr));
++			break;
++		case MAX_HOST_RXBUFS:
++		{
++			pciedev_shared_t *sh = (pciedev_shared_t*)bus->shared_addr;
++			*(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus,
++				(ulong) &sh->max_host_rxbufs));
++			break;
++		}
++		default :
++			break;
++	}
++}
++
++uint32 dhd_bus_get_sharedflags(dhd_bus_t *bus)
++{
++	return ((pciedev_shared_t*)bus->pcie_sh)->flags;
++}
++
++void
++dhd_bus_clearcounts(dhd_pub_t *dhdp)
++{
++}
++
++int
++dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
++                 void *params, int plen, void *arg, int len, bool set)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	const bcm_iovar_t *vi = NULL;
++	int bcmerror = 0;
++	int val_size;
++	uint32 actionid;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	ASSERT(name);
++	ASSERT(len >= 0);
++
++	/* Get MUST have return space */
++	ASSERT(set || (arg && len));
++
++	/* Set does NOT take qualifiers */
++	ASSERT(!set || (!params && !plen));
++
++	DHD_INFO(("%s: %s %s, len %d plen %d\n", __FUNCTION__,
++	         name, (set ? "set" : "get"), len, plen));
++
++	/* Look up var locally; if not found pass to host driver */
++	if ((vi = bcm_iovar_lookup(dhdpcie_iovars, name)) == NULL) {
++		goto exit;
++	}
++
++
++	/* set up 'params' pointer in case this is a set command so that
++	 * the convenience int and bool code can be common to set and get
++	 */
++	if (params == NULL) {
++		params = arg;
++		plen = len;
++	}
++
++	if (vi->type == IOVT_VOID)
++		val_size = 0;
++	else if (vi->type == IOVT_BUFFER)
++		val_size = len;
++	else
++		/* all other types are integer sized */
++		val_size = sizeof(int);
++
++	actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
++	bcmerror = dhdpcie_bus_doiovar(bus, vi, actionid, name, params, plen, arg, len, val_size);
++
++exit:
++	return bcmerror;
++} /* dhd_bus_iovar_op */
++
++#ifdef BCM_BUZZZ
++#include <bcm_buzzz.h>
++
++int
++dhd_buzzz_dump_cntrs(char *p, uint32 *core, uint32 *log,
++	const int num_counters)
++{
++	int bytes = 0;
++	uint32 ctr;
++	uint32 curr[BCM_BUZZZ_COUNTERS_MAX], prev[BCM_BUZZZ_COUNTERS_MAX];
++	uint32 delta[BCM_BUZZZ_COUNTERS_MAX];
++
++	/* Compute elapsed counter values per counter event type */
++	for (ctr = 0U; ctr < num_counters; ctr++) {
++		prev[ctr] = core[ctr];
++		curr[ctr] = *log++;
++		core[ctr] = curr[ctr];  /* saved for next log */
++
++		if (curr[ctr] < prev[ctr])
++			delta[ctr] = curr[ctr] + (~0U - prev[ctr]);
++		else
++			delta[ctr] = (curr[ctr] - prev[ctr]);
++
++		bytes += sprintf(p + bytes, "%12u ", delta[ctr]);
++	}
++
++	return bytes;
++}
++
++typedef union cm3_cnts { /* export this in bcm_buzzz.h */
++	uint32 u32;
++	uint8  u8[4];
++	struct {
++		uint8 cpicnt;
++		uint8 exccnt;
++		uint8 sleepcnt;
++		uint8 lsucnt;
++	};
++} cm3_cnts_t;
++
++int
++dhd_bcm_buzzz_dump_cntrs6(char *p, uint32 *core, uint32 *log)
++{
++	int bytes = 0;
++
++	uint32 cyccnt, instrcnt;
++	cm3_cnts_t cm3_cnts;
++	uint8 foldcnt;
++
++	{   /* 32bit cyccnt */
++		uint32 curr, prev, delta;
++		prev = core[0]; curr = *log++; core[0] = curr;
++		if (curr < prev)
++			delta = curr + (~0U - prev);
++		else
++			delta = (curr - prev);
++
++		bytes += sprintf(p + bytes, "%12u ", delta);
++		cyccnt = delta;
++	}
++
++	{	/* Extract the 4 cnts: cpi, exc, sleep and lsu */
++		int i;
++		uint8 max8 = ~0;
++		cm3_cnts_t curr, prev, delta;
++		prev.u32 = core[1]; curr.u32 = * log++; core[1] = curr.u32;
++		for (i = 0; i < 4; i++) {
++			if (curr.u8[i] < prev.u8[i])
++				delta.u8[i] = curr.u8[i] + (max8 - prev.u8[i]);
++			else
++				delta.u8[i] = (curr.u8[i] - prev.u8[i]);
++			bytes += sprintf(p + bytes, "%4u ", delta.u8[i]);
++		}
++		cm3_cnts.u32 = delta.u32;
++	}
++
++	{   /* Extract the foldcnt from arg0 */
++		uint8 curr, prev, delta, max8 = ~0;
++		bcm_buzzz_arg0_t arg0; arg0.u32 = *log;
++		prev = core[2]; curr = arg0.klog.cnt; core[2] = curr;
++		if (curr < prev)
++			delta = curr + (max8 - prev);
++		else
++			delta = (curr - prev);
++		bytes += sprintf(p + bytes, "%4u ", delta);
++		foldcnt = delta;
++	}
++
++	instrcnt = cyccnt - (cm3_cnts.u8[0] + cm3_cnts.u8[1] + cm3_cnts.u8[2]
++		                 + cm3_cnts.u8[3]) + foldcnt;
++	if (instrcnt > 0xFFFFFF00)
++		bytes += sprintf(p + bytes, "[%10s] ", "~");
++	else
++		bytes += sprintf(p + bytes, "[%10u] ", instrcnt);
++	return bytes;
++}
++
++int
++dhd_buzzz_dump_log(char *p, uint32 *core, uint32 *log, bcm_buzzz_t *buzzz)
++{
++	int bytes = 0;
++	bcm_buzzz_arg0_t arg0;
++	static uint8 * fmt[] = BCM_BUZZZ_FMT_STRINGS;
++
++	if (buzzz->counters == 6) {
++		bytes += dhd_bcm_buzzz_dump_cntrs6(p, core, log);
++		log += 2; /* 32bit cyccnt + (4 x 8bit) CM3 */
++	} else {
++		bytes += dhd_buzzz_dump_cntrs(p, core, log, buzzz->counters);
++		log += buzzz->counters; /* (N x 32bit) CR4=3, CA7=4 */
++	}
++
++	/* Dump the logged arguments using the registered formats */
++	arg0.u32 = *log++;
++
++	switch (arg0.klog.args) {
++		case 0:
++			bytes += sprintf(p + bytes, fmt[arg0.klog.id]);
++			break;
++		case 1:
++		{
++			uint32 arg1 = *log++;
++			bytes += sprintf(p + bytes, fmt[arg0.klog.id], arg1);
++			break;
++		}
++		case 2:
++		{
++			uint32 arg1, arg2;
++			arg1 = *log++; arg2 = *log++;
++			bytes += sprintf(p + bytes, fmt[arg0.klog.id], arg1, arg2);
++			break;
++		}
++		case 3:
++		{
++			uint32 arg1, arg2, arg3;
++			arg1 = *log++; arg2 = *log++; arg3 = *log++;
++			bytes += sprintf(p + bytes, fmt[arg0.klog.id], arg1, arg2, arg3);
++			break;
++		}
++		case 4:
++		{
++			uint32 arg1, arg2, arg3, arg4;
++			arg1 = *log++; arg2 = *log++;
++			arg3 = *log++; arg4 = *log++;
++			bytes += sprintf(p + bytes, fmt[arg0.klog.id], arg1, arg2, arg3, arg4);
++			break;
++		}
++		default:
++			printf("Maximum one argument supported\n");
++			break;
++	}
++
++	bytes += sprintf(p + bytes, "\n");
++
++	return bytes;
++}
++
++void dhd_buzzz_dump(bcm_buzzz_t *buzzz_p, void *buffer_p, char *p)
++{
++	int i;
++	uint32 total, part1, part2, log_sz, core[BCM_BUZZZ_COUNTERS_MAX];
++	void * log;
++
++	for (i = 0; i < BCM_BUZZZ_COUNTERS_MAX; i++) {
++		core[i] = 0;
++	}
++
++	log_sz = buzzz_p->log_sz;
++
++	part1 = ((uint32)buzzz_p->cur - (uint32)buzzz_p->log) / log_sz;
++
++	if (buzzz_p->wrap == TRUE) {
++		part2 = ((uint32)buzzz_p->end - (uint32)buzzz_p->cur) / log_sz;
++		total = (buzzz_p->buffer_sz - BCM_BUZZZ_LOGENTRY_MAXSZ) / log_sz;
++	} else {
++		part2 = 0U;
++		total = buzzz_p->count;
++	}
++
++	if (total == 0U) {
++		printf("bcm_buzzz_dump total<%u> done\n", total);
++		return;
++	} else {
++		printf("bcm_buzzz_dump total<%u> : part2<%u> + part1<%u>\n",
++		       total, part2, part1);
++	}
++
++	if (part2) {   /* with wrap */
++		log = (void*)((size_t)buffer_p + (buzzz_p->cur - buzzz_p->log));
++		while (part2--) {   /* from cur to end : part2 */
++			p[0] = '\0';
++			dhd_buzzz_dump_log(p, core, (uint32 *)log, buzzz_p);
++			printf("%s", p);
++			log = (void*)((size_t)log + buzzz_p->log_sz);
++		}
++	}
++
++	log = (void*)buffer_p;
++	while (part1--) {
++		p[0] = '\0';
++		dhd_buzzz_dump_log(p, core, (uint32 *)log, buzzz_p);
++		printf("%s", p);
++		log = (void*)((size_t)log + buzzz_p->log_sz);
++	}
++
++	printf("bcm_buzzz_dump done.\n");
++}
++
++int dhd_buzzz_dump_dngl(dhd_bus_t *bus)
++{
++	bcm_buzzz_t * buzzz_p = NULL;
++	void * buffer_p = NULL;
++	char * page_p = NULL;
++	pciedev_shared_t *sh;
++	int ret = 0;
++
++	if (bus->dhd->busstate != DHD_BUS_DATA) {
++		return BCME_UNSUPPORTED;
++	}
++	if ((page_p = (char *)MALLOC(bus->dhd->osh, 4096)) == NULL) {
++		printf("Page memory allocation failure\n");
++		goto done;
++	}
++	if ((buzzz_p = MALLOC(bus->dhd->osh, sizeof(bcm_buzzz_t))) == NULL) {
++		printf("BCM BUZZZ memory allocation failure\n");
++		goto done;
++	}
++
++	ret = dhdpcie_readshared(bus);
++	if (ret < 0) {
++		DHD_ERROR(("%s :Shared area read failed \n", __FUNCTION__));
++		goto done;
++	}
++
++	sh = bus->pcie_sh;
++
++	DHD_INFO(("%s buzzz:%08x\n", __FUNCTION__, sh->buzzz));
++
++	if (sh->buzzz != 0U) {	/* Fetch and display dongle BUZZZ Trace */
++
++		dhdpcie_bus_membytes(bus, FALSE, (ulong)sh->buzzz,
++		                     (uint8 *)buzzz_p, sizeof(bcm_buzzz_t));
++
++		printf("BUZZZ[0x%08x]: log<0x%08x> cur<0x%08x> end<0x%08x> "
++			"count<%u> status<%u> wrap<%u>\n"
++			"cpu<0x%02X> counters<%u> group<%u> buffer_sz<%u> log_sz<%u>\n",
++			(int)sh->buzzz,
++			(int)buzzz_p->log, (int)buzzz_p->cur, (int)buzzz_p->end,
++			buzzz_p->count, buzzz_p->status, buzzz_p->wrap,
++			buzzz_p->cpu_idcode, buzzz_p->counters, buzzz_p->group,
++			buzzz_p->buffer_sz, buzzz_p->log_sz);
++
++		if (buzzz_p->count == 0) {
++			printf("Empty dongle BUZZZ trace\n\n");
++			goto done;
++		}
++
++		/* Allocate memory for trace buffer and format strings */
++		buffer_p = MALLOC(bus->dhd->osh, buzzz_p->buffer_sz);
++		if (buffer_p == NULL) {
++			printf("Buffer memory allocation failure\n");
++			goto done;
++		}
++
++		/* Fetch the trace. format strings are exported via bcm_buzzz.h */
++		dhdpcie_bus_membytes(bus, FALSE, (uint32)buzzz_p->log,   /* Trace */
++		                     (uint8 *)buffer_p, buzzz_p->buffer_sz);
++
++		/* Process and display the trace using formatted output */
++
++		{
++			int ctr;
++			for (ctr = 0; ctr < buzzz_p->counters; ctr++) {
++				printf("<Evt[%02X]> ", buzzz_p->eventid[ctr]);
++			}
++			printf("<code execution point>\n");
++		}
++
++		dhd_buzzz_dump(buzzz_p, buffer_p, page_p);
++
++		printf("----- End of dongle BCM BUZZZ Trace -----\n\n");
++
++		MFREE(bus->dhd->osh, buffer_p, buzzz_p->buffer_sz); buffer_p = NULL;
++	}
++
++done:
++
++	if (page_p)   MFREE(bus->dhd->osh, page_p, 4096);
++	if (buzzz_p)  MFREE(bus->dhd->osh, buzzz_p, sizeof(bcm_buzzz_t));
++	if (buffer_p) MFREE(bus->dhd->osh, buffer_p, buzzz_p->buffer_sz);
++
++	return BCME_OK;
++}
++#endif /* BCM_BUZZZ */
++
++#define PCIE_GEN2(sih) ((BUSTYPE((sih)->bustype) == PCI_BUS) &&	\
++	((sih)->buscoretype == PCIE2_CORE_ID))
++
++static bool
++pcie2_mdiosetblock(dhd_bus_t *bus, uint blk)
++{
++	uint mdiodata, mdioctrl, i = 0;
++	uint pcie_serdes_spinwait = 200;
++
++	mdioctrl = MDIOCTL2_DIVISOR_VAL | (0x1F << MDIOCTL2_REGADDR_SHF);
++	mdiodata = (blk << MDIODATA2_DEVADDR_SHF) | MDIODATA2_DONE;
++
++	si_corereg(bus->sih, bus->sih->buscoreidx, PCIE2_MDIO_CONTROL, ~0, mdioctrl);
++	si_corereg(bus->sih, bus->sih->buscoreidx, PCIE2_MDIO_WR_DATA, ~0, mdiodata);
++
++	OSL_DELAY(10);
++	/* retry till the transaction is complete */
++	while (i < pcie_serdes_spinwait) {
++		uint mdioctrl_read = si_corereg(bus->sih, bus->sih->buscoreidx, PCIE2_MDIO_WR_DATA,
++			0, 0);
++		if (!(mdioctrl_read & MDIODATA2_DONE)) {
++			break;
++		}
++		OSL_DELAY(1000);
++		i++;
++	}
++
++	if (i >= pcie_serdes_spinwait) {
++		DHD_ERROR(("pcie_mdiosetblock: timed out\n"));
++		return FALSE;
++	}
++
++	return TRUE;
++}
++
++
++int
++dhd_bus_devreset(dhd_pub_t *dhdp, uint8 flag)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	int bcmerror = 0;
++	unsigned long flags;
++#ifdef CONFIG_ARCH_MSM
++	int retry = POWERUP_MAX_RETRY;
++#endif /* CONFIG_ARCH_MSM */
++
++	if (dhd_download_fw_on_driverload) {
++		bcmerror = dhd_bus_start(dhdp);
++	} else {
++		if (flag == TRUE) { /* Turn off WLAN */
++			/* Removing Power */
++			DHD_ERROR(("%s: == Power OFF ==\n", __FUNCTION__));
++
++			bus->dhd->up = FALSE;
++
++			if (bus->dhd->busstate != DHD_BUS_DOWN) {
++				dhdpcie_advertise_bus_cleanup(bus->dhd);
++				if (bus->intr) {
++					dhdpcie_bus_intr_disable(bus);
++					dhdpcie_free_irq(bus);
++				}
++#ifdef BCMPCIE_OOB_HOST_WAKE
++				/* Clean up any pending host wake IRQ */
++				dhd_bus_oob_intr_set(bus->dhd, FALSE);
++				dhd_bus_oob_intr_unregister(bus->dhd);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++				dhd_os_wd_timer(dhdp, 0);
++				dhd_bus_stop(bus, TRUE);
++				dhd_prot_reset(dhdp);
++				dhd_clear(dhdp);
++				dhd_bus_release_dongle(bus);
++				dhdpcie_bus_free_resource(bus);
++				bcmerror = dhdpcie_bus_disable_device(bus);
++				if (bcmerror) {
++					DHD_ERROR(("%s: dhdpcie_bus_disable_device: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++#ifdef CONFIG_ARCH_MSM
++				bcmerror = dhdpcie_bus_clock_stop(bus);
++				if (bcmerror) {
++					DHD_ERROR(("%s: host clock stop failed: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++#endif /* CONFIG_ARCH_MSM */
++				DHD_GENERAL_LOCK(bus->dhd, flags);
++				bus->dhd->busstate = DHD_BUS_DOWN;
++				DHD_GENERAL_UNLOCK(bus->dhd, flags);
++			} else {
++				if (bus->intr) {
++					dhdpcie_bus_intr_disable(bus);
++					dhdpcie_free_irq(bus);
++				}
++#ifdef BCMPCIE_OOB_HOST_WAKE
++				/* Clean up any pending host wake IRQ */
++				dhd_bus_oob_intr_set(bus->dhd, FALSE);
++				dhd_bus_oob_intr_unregister(bus->dhd);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++				dhd_prot_reset(dhdp);
++				dhd_clear(dhdp);
++				dhd_bus_release_dongle(bus);
++				dhdpcie_bus_free_resource(bus);
++				bcmerror = dhdpcie_bus_disable_device(bus);
++				if (bcmerror) {
++					DHD_ERROR(("%s: dhdpcie_bus_disable_device: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++
++#ifdef CONFIG_ARCH_MSM
++				bcmerror = dhdpcie_bus_clock_stop(bus);
++				if (bcmerror) {
++					DHD_ERROR(("%s: host clock stop failed: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++#endif  /* CONFIG_ARCH_MSM */
++			}
++
++			bus->dhd->dongle_reset = TRUE;
++			DHD_ERROR(("%s:  WLAN OFF Done\n", __FUNCTION__));
++
++		} else { /* Turn on WLAN */
++			if (bus->dhd->busstate == DHD_BUS_DOWN) {
++				/* Powering On */
++				DHD_ERROR(("%s: == Power ON ==\n", __FUNCTION__));
++#ifdef CONFIG_ARCH_MSM
++				while (--retry) {
++					bcmerror = dhdpcie_bus_clock_start(bus);
++					if (!bcmerror) {
++						DHD_ERROR(("%s: dhdpcie_bus_clock_start OK\n",
++							__FUNCTION__));
++						break;
++					} else {
++						OSL_SLEEP(10);
++					}
++				}
++
++				if (bcmerror && !retry) {
++					DHD_ERROR(("%s: host pcie clock enable failed: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++#endif /* CONFIG_ARCH_MSM */
++				bcmerror = dhdpcie_bus_enable_device(bus);
++				if (bcmerror) {
++					DHD_ERROR(("%s: host configuration restore failed: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++
++				bcmerror = dhdpcie_bus_alloc_resource(bus);
++				if (bcmerror) {
++					DHD_ERROR(("%s: dhdpcie_bus_resource_alloc failed: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++
++				bcmerror = dhdpcie_bus_dongle_attach(bus);
++				if (bcmerror) {
++					DHD_ERROR(("%s: dhdpcie_bus_dongle_attach failed: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++
++				bcmerror = dhd_bus_request_irq(bus);
++				if (bcmerror) {
++					DHD_ERROR(("%s: dhd_bus_request_irq failed: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++
++				bus->dhd->dongle_reset = FALSE;
++
++				bcmerror = dhd_bus_start(dhdp);
++				if (bcmerror) {
++					DHD_ERROR(("%s: dhd_bus_start: %d\n",
++						__FUNCTION__, bcmerror));
++					goto done;
++				}
++
++				bus->dhd->up = TRUE;
++				DHD_ERROR(("%s: WLAN Power On Done\n", __FUNCTION__));
++			} else {
++				DHD_ERROR(("%s: what should we do here\n", __FUNCTION__));
++				goto done;
++			}
++		}
++	}
++
++done:
++	if (bcmerror) {
++		DHD_GENERAL_LOCK(bus->dhd, flags);
++		bus->dhd->busstate = DHD_BUS_DOWN;
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++	}
++
++	return bcmerror;
++}
++
++static int
++pcie2_mdioop(dhd_bus_t *bus, uint physmedia, uint regaddr, bool write, uint *val,
++	bool slave_bypass)
++{
++	uint pcie_serdes_spinwait = 200, i = 0, mdio_ctrl;
++	uint32 reg32;
++
++	pcie2_mdiosetblock(bus, physmedia);
++
++	/* enable mdio access to SERDES */
++	mdio_ctrl = MDIOCTL2_DIVISOR_VAL;
++	mdio_ctrl |= (regaddr << MDIOCTL2_REGADDR_SHF);
++
++	if (slave_bypass)
++		mdio_ctrl |= MDIOCTL2_SLAVE_BYPASS;
++
++	if (!write)
++		mdio_ctrl |= MDIOCTL2_READ;
++
++	si_corereg(bus->sih, bus->sih->buscoreidx, PCIE2_MDIO_CONTROL, ~0, mdio_ctrl);
++
++	if (write) {
++		reg32 =  PCIE2_MDIO_WR_DATA;
++		si_corereg(bus->sih, bus->sih->buscoreidx, PCIE2_MDIO_WR_DATA, ~0,
++			*val | MDIODATA2_DONE);
++	} else
++		reg32 =  PCIE2_MDIO_RD_DATA;
++
++	/* retry till the transaction is complete */
++	while (i < pcie_serdes_spinwait) {
++		uint done_val =  si_corereg(bus->sih, bus->sih->buscoreidx, reg32, 0, 0);
++		if (!(done_val & MDIODATA2_DONE)) {
++			if (!write) {
++				*val = si_corereg(bus->sih, bus->sih->buscoreidx,
++					PCIE2_MDIO_RD_DATA, 0, 0);
++				*val = *val & MDIODATA2_MASK;
++			}
++			return 0;
++		}
++		OSL_DELAY(1000);
++		i++;
++	}
++	return -1;
++}
++
++static int
++dhdpcie_bus_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, const char *name,
++                void *params, int plen, void *arg, int len, int val_size)
++{
++	int bcmerror = 0;
++	int32 int_val = 0;
++	int32 int_val2 = 0;
++	int32 int_val3 = 0;
++	bool bool_val = 0;
++
++	DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p len %d val_size %d\n",
++	           __FUNCTION__, actionid, name, params, plen, arg, len, val_size));
++
++	if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid))) != 0)
++		goto exit;
++
++	if (plen >= (int)sizeof(int_val))
++		bcopy(params, &int_val, sizeof(int_val));
++
++	if (plen >= (int)sizeof(int_val) * 2)
++		bcopy((void*)((uintptr)params + sizeof(int_val)), &int_val2, sizeof(int_val2));
++
++	if (plen >= (int)sizeof(int_val) * 3)
++		bcopy((void*)((uintptr)params + 2 * sizeof(int_val)), &int_val3, sizeof(int_val3));
++
++	bool_val = (int_val != 0) ? TRUE : FALSE;
++
++	/* Check if dongle is in reset. If so, only allow DEVRESET iovars */
++	if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
++	                                actionid == IOV_GVAL(IOV_DEVRESET))) {
++		bcmerror = BCME_NOTREADY;
++		goto exit;
++	}
++
++	switch (actionid) {
++
++
++	case IOV_SVAL(IOV_VARS):
++		bcmerror = dhdpcie_downloadvars(bus, arg, len);
++		break;
++
++	case IOV_SVAL(IOV_PCIEREG):
++		si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0,
++			int_val);
++		si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata), ~0,
++			int_val2);
++		break;
++
++	case IOV_GVAL(IOV_PCIEREG):
++		si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0,
++			int_val);
++		int_val = si_corereg(bus->sih, bus->sih->buscoreidx,
++			OFFSETOF(sbpcieregs_t, configdata), 0, 0);
++		bcopy(&int_val, arg, sizeof(int_val));
++		break;
++
++	case IOV_SVAL(IOV_PCIECOREREG):
++		si_corereg(bus->sih, bus->sih->buscoreidx, int_val, ~0, int_val2);
++		break;
++	case IOV_GVAL(IOV_BAR0_SECWIN_REG):
++	{
++		sdreg_t sdreg;
++		uint32 addr, size;
++
++		bcopy(params, &sdreg, sizeof(sdreg));
++
++		addr = sdreg.offset;
++		size = sdreg.func;
++
++		if (si_backplane_access(bus->sih, addr, size, &int_val, TRUE) != BCME_OK) {
++			DHD_ERROR(("Invalid size/addr combination \n"));
++			bcmerror = BCME_ERROR;
++			break;
++		}
++		bcopy(&int_val, arg, sizeof(int32));
++		break;
++	}
++
++	case IOV_SVAL(IOV_BAR0_SECWIN_REG):
++	{
++		sdreg_t sdreg;
++		uint32 addr, size;
++
++		bcopy(params, &sdreg, sizeof(sdreg));
++
++		addr = sdreg.offset;
++		size = sdreg.func;
++		if (si_backplane_access(bus->sih, addr, size, &sdreg.value, FALSE) != BCME_OK) {
++			DHD_ERROR(("Invalid size/addr combination \n"));
++			bcmerror = BCME_ERROR;
++		}
++		break;
++	}
++
++	case IOV_GVAL(IOV_SBREG):
++	{
++		sdreg_t sdreg;
++		uint32 addr, size;
++
++		bcopy(params, &sdreg, sizeof(sdreg));
++
++		addr = sdreg.offset | SI_ENUM_BASE;
++		size = sdreg.func;
++
++		if (si_backplane_access(bus->sih, addr, size, &int_val, TRUE) != BCME_OK) {
++			DHD_ERROR(("Invalid size/addr combination \n"));
++			bcmerror = BCME_ERROR;
++			break;
++		}
++		bcopy(&int_val, arg, size);
++		break;
++	}
++
++	case IOV_SVAL(IOV_SBREG):
++	{
++		sdreg_t sdreg;
++		uint32 addr, size;
++
++		bcopy(params, &sdreg, sizeof(sdreg));
++
++		addr = sdreg.offset | SI_ENUM_BASE;
++		size = sdreg.func;
++		if (si_backplane_access(bus->sih, addr, size, &sdreg.value, FALSE) != BCME_OK) {
++			DHD_ERROR(("Invalid size/addr combination \n"));
++			bcmerror = BCME_ERROR;
++		}
++		break;
++	}
++
++	case IOV_GVAL(IOV_PCIESERDESREG):
++	{
++		uint val;
++		if (!PCIE_GEN2(bus->sih)) {
++			DHD_ERROR(("supported only in pcie gen2\n"));
++			bcmerror = BCME_ERROR;
++			break;
++		}
++
++		if (!pcie2_mdioop(bus, int_val, int_val2, FALSE, &val, FALSE)) {
++			bcopy(&val, arg, sizeof(int32));
++		} else {
++			DHD_ERROR(("pcie2_mdioop failed.\n"));
++			bcmerror = BCME_ERROR;
++		}
++		break;
++	}
++
++	case IOV_SVAL(IOV_PCIESERDESREG):
++		if (!PCIE_GEN2(bus->sih)) {
++			DHD_ERROR(("supported only in pcie gen2\n"));
++			bcmerror = BCME_ERROR;
++			break;
++		}
++		if (pcie2_mdioop(bus, int_val, int_val2, TRUE, &int_val3, FALSE)) {
++			DHD_ERROR(("pcie2_mdioop failed.\n"));
++			bcmerror = BCME_ERROR;
++		}
++		break;
++	case IOV_GVAL(IOV_PCIECOREREG):
++		int_val = si_corereg(bus->sih, bus->sih->buscoreidx, int_val, 0, 0);
++		bcopy(&int_val, arg, sizeof(int_val));
++		break;
++
++	case IOV_SVAL(IOV_PCIECFGREG):
++		OSL_PCI_WRITE_CONFIG(bus->osh, int_val, 4, int_val2);
++		break;
++
++	case IOV_GVAL(IOV_PCIECFGREG):
++		int_val = OSL_PCI_READ_CONFIG(bus->osh, int_val, 4);
++		bcopy(&int_val, arg, sizeof(int_val));
++		break;
++
++	case IOV_SVAL(IOV_PCIE_LPBK):
++		bcmerror = dhdpcie_bus_lpback_req(bus, int_val);
++		break;
++
++	case IOV_SVAL(IOV_PCIE_DMAXFER):
++		bcmerror = dhdpcie_bus_dmaxfer_req(bus, int_val, int_val2, int_val3);
++		break;
++
++	case IOV_GVAL(IOV_PCIE_SUSPEND):
++		int_val = (bus->dhd->busstate == DHD_BUS_SUSPEND) ? 1 : 0;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_PCIE_SUSPEND):
++		dhdpcie_bus_suspend(bus, bool_val);
++		break;
++
++	case IOV_GVAL(IOV_MEMSIZE):
++		int_val = (int32)bus->ramsize;
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_SVAL(IOV_MEMBYTES):
++	case IOV_GVAL(IOV_MEMBYTES):
++	{
++		uint32 address;		/* absolute backplane address */
++		uint size, dsize;
++		uint8 *data;
++
++		bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
++
++		ASSERT(plen >= 2*sizeof(int));
++
++		address = (uint32)int_val;
++		bcopy((char *)params + sizeof(int_val), &int_val, sizeof(int_val));
++		size = (uint)int_val;
++
++		/* Do some validation */
++		dsize = set ? plen - (2 * sizeof(int)) : len;
++		if (dsize < size) {
++			DHD_ERROR(("%s: error on %s membytes, addr 0x%08x size %d dsize %d\n",
++			           __FUNCTION__, (set ? "set" : "get"), address, size, dsize));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		DHD_INFO(("%s: Request to %s %d bytes at address 0x%08x\n dsize %d ", __FUNCTION__,
++		          (set ? "write" : "read"), size, address, dsize));
++
++		/* check if CR4 */
++		if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0) ||
++		    si_setcore(bus->sih, SYSMEM_CORE_ID, 0)) {
++			/* if address is 0, store the reset instruction to be written in 0 */
++			if (set && address == bus->dongle_ram_base) {
++				bus->resetinstr = *(((uint32*)params) + 2);
++			}
++		} else {
++		/* If we know about SOCRAM, check for a fit */
++		if ((bus->orig_ramsize) &&
++		    ((address > bus->orig_ramsize) || (address + size > bus->orig_ramsize)))
++		{
++			uint8 enable, protect, remap;
++			si_socdevram(bus->sih, FALSE, &enable, &protect, &remap);
++			if (!enable || protect) {
++				DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d bytes at 0x%08x\n",
++					__FUNCTION__, bus->orig_ramsize, size, address));
++				DHD_ERROR(("%s: socram enable %d, protect %d\n",
++					__FUNCTION__, enable, protect));
++				bcmerror = BCME_BADARG;
++				break;
++			}
++
++			if (!REMAP_ENAB(bus) && (address >= SOCDEVRAM_ARM_ADDR)) {
++				uint32 devramsize = si_socdevram_size(bus->sih);
++				if ((address < SOCDEVRAM_ARM_ADDR) ||
++					(address + size > (SOCDEVRAM_ARM_ADDR + devramsize))) {
++					DHD_ERROR(("%s: bad address 0x%08x, size 0x%08x\n",
++						__FUNCTION__, address, size));
++					DHD_ERROR(("%s: socram range 0x%08x,size 0x%08x\n",
++						__FUNCTION__, SOCDEVRAM_ARM_ADDR, devramsize));
++					bcmerror = BCME_BADARG;
++					break;
++				}
++				/* move it such that address is real now */
++				address -= SOCDEVRAM_ARM_ADDR;
++				address += SOCDEVRAM_BP_ADDR;
++				DHD_INFO(("%s: Request to %s %d bytes @ Mapped address 0x%08x\n",
++					__FUNCTION__, (set ? "write" : "read"), size, address));
++			} else if (REMAP_ENAB(bus) && REMAP_ISADDR(bus, address) && remap) {
++				/* Can not access remap region while devram remap bit is set
++				 * ROM content would be returned in this case
++				 */
++				DHD_ERROR(("%s: Need to disable remap for address 0x%08x\n",
++					__FUNCTION__, address));
++				bcmerror = BCME_ERROR;
++				break;
++			}
++		}
++		}
++
++		/* Generate the actual data pointer */
++		data = set ? (uint8*)params + 2 * sizeof(int): (uint8*)arg;
++
++		/* Call to do the transfer */
++		bcmerror = dhdpcie_bus_membytes(bus, set, address, data, size);
++
++		break;
++	}
++
++#ifdef BCM_BUZZZ
++	/* Dump dongle side buzzz trace to console */
++	case IOV_GVAL(IOV_BUZZZ_DUMP):
++		bcmerror = dhd_buzzz_dump_dngl(bus);
++		break;
++#endif /* BCM_BUZZZ */
++
++	case IOV_SVAL(IOV_SET_DOWNLOAD_STATE):
++		bcmerror = dhdpcie_bus_download_state(bus, bool_val);
++		break;
++
++	case IOV_GVAL(IOV_RAMSIZE):
++		int_val = (int32)bus->ramsize;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_RAMSIZE):
++		bus->ramsize = int_val;
++		bus->orig_ramsize = int_val;
++		break;
++
++	case IOV_GVAL(IOV_RAMSTART):
++		int_val = (int32)bus->dongle_ram_base;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_CC_NVMSHADOW):
++	{
++		struct bcmstrbuf dump_b;
++
++		bcm_binit(&dump_b, arg, len);
++		bcmerror = dhdpcie_cc_nvmshadow(bus, &dump_b);
++		break;
++	}
++
++	case IOV_GVAL(IOV_SLEEP_ALLOWED):
++		bool_val = bus->sleep_allowed;
++		bcopy(&bool_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_SLEEP_ALLOWED):
++		bus->sleep_allowed = bool_val;
++		break;
++
++	case IOV_GVAL(IOV_DONGLEISOLATION):
++		int_val = bus->dhd->dongle_isolation;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DONGLEISOLATION):
++		bus->dhd->dongle_isolation = bool_val;
++		break;
++
++	case IOV_GVAL(IOV_LTRSLEEPON_UNLOOAD):
++		int_val = bus->ltrsleep_on_unload;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_LTRSLEEPON_UNLOOAD):
++		bus->ltrsleep_on_unload = bool_val;
++		break;
++
++	case IOV_GVAL(IOV_DUMP_RINGUPD_BLOCK):
++	{
++		struct bcmstrbuf dump_b;
++		bcm_binit(&dump_b, arg, len);
++		bcmerror = dhd_prot_ringupd_dump(bus->dhd, &dump_b);
++		break;
++	}
++	case IOV_GVAL(IOV_DMA_RINGINDICES):
++	{	int h2d_support, d2h_support;
++
++		d2h_support = DMA_INDX_ENAB(bus->dhd->dma_d2h_ring_upd_support) ? 1 : 0;
++		h2d_support = DMA_INDX_ENAB(bus->dhd->dma_h2d_ring_upd_support) ? 1 : 0;
++		int_val = d2h_support | (h2d_support << 1);
++		bcopy(&int_val, arg, sizeof(int_val));
++		break;
++	}
++	case IOV_SVAL(IOV_DMA_RINGINDICES):
++		/* Can change it only during initialization/FW download */
++		if (bus->dhd->busstate == DHD_BUS_DOWN) {
++			if ((int_val > 3) || (int_val < 0)) {
++				DHD_ERROR(("Bad argument. Possible values: 0, 1, 2 & 3\n"));
++				bcmerror = BCME_BADARG;
++			} else {
++				bus->dhd->dma_d2h_ring_upd_support = (int_val & 1) ? TRUE : FALSE;
++				bus->dhd->dma_h2d_ring_upd_support = (int_val & 2) ? TRUE : FALSE;
++			}
++		} else {
++			DHD_ERROR(("%s: Can change only when bus down (before FW download)\n",
++				__FUNCTION__));
++			bcmerror = BCME_NOTDOWN;
++		}
++		break;
++
++	case IOV_GVAL(IOV_METADATA_DBG):
++		int_val = dhd_prot_metadata_dbg_get(bus->dhd);
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_SVAL(IOV_METADATA_DBG):
++		dhd_prot_metadata_dbg_set(bus->dhd, (int_val != 0));
++		break;
++
++	case IOV_GVAL(IOV_RX_METADATALEN):
++		int_val = dhd_prot_metadatalen_get(bus->dhd, TRUE);
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_RX_METADATALEN):
++		if (int_val > 64) {
++			bcmerror = BCME_BUFTOOLONG;
++			break;
++		}
++		dhd_prot_metadatalen_set(bus->dhd, int_val, TRUE);
++		break;
++
++	case IOV_SVAL(IOV_TXP_THRESHOLD):
++		dhd_prot_txp_threshold(bus->dhd, TRUE, int_val);
++		break;
++
++	case IOV_GVAL(IOV_TXP_THRESHOLD):
++		int_val = dhd_prot_txp_threshold(bus->dhd, FALSE, int_val);
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DB1_FOR_MB):
++		if (int_val)
++			bus->db1_for_mb = TRUE;
++		else
++			bus->db1_for_mb = FALSE;
++		break;
++
++	case IOV_GVAL(IOV_DB1_FOR_MB):
++		if (bus->db1_for_mb)
++			int_val = 1;
++		else
++			int_val = 0;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_TX_METADATALEN):
++		int_val = dhd_prot_metadatalen_get(bus->dhd, FALSE);
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_TX_METADATALEN):
++		if (int_val > 64) {
++			bcmerror = BCME_BUFTOOLONG;
++			break;
++		}
++		dhd_prot_metadatalen_set(bus->dhd, int_val, FALSE);
++		break;
++
++	case IOV_SVAL(IOV_DEVRESET):
++		dhd_bus_devreset(bus->dhd, (uint8)bool_val);
++		break;
++	case IOV_SVAL(IOV_FORCE_FW_TRAP):
++		if (bus->dhd->busstate == DHD_BUS_DATA)
++			dhdpcie_fw_trap(bus);
++		else {
++			DHD_ERROR(("%s: Bus is NOT up\n", __FUNCTION__));
++			bcmerror = BCME_NOTUP;
++		}
++		break;
++	case IOV_GVAL(IOV_FLOW_PRIO_MAP):
++		int_val = bus->dhd->flow_prio_map_type;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_FLOW_PRIO_MAP):
++		int_val = (int32)dhd_update_flow_prio_map(bus->dhd, (uint8)int_val);
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_TXBOUND):
++		int_val = (int32)dhd_txbound;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_TXBOUND):
++		dhd_txbound = (uint)int_val;
++		break;
++
++	case IOV_GVAL(IOV_RXBOUND):
++		int_val = (int32)dhd_rxbound;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_RXBOUND):
++		dhd_rxbound = (uint)int_val;
++		break;
++
++	case IOV_GVAL(IOV_PCIEASPM): {
++		uint8 clkreq = 0;
++		uint32 aspm = 0;
++
++		/* this command is to hide the details, but match the lcreg
++		#define PCIE_CLKREQ_ENAB		0x100
++		#define PCIE_ASPM_L1_ENAB		2
++		#define PCIE_ASPM_L0s_ENAB		1
++		*/
++
++		clkreq = dhdpcie_clkreq(bus->dhd->osh, 0, 0);
++		aspm = dhdpcie_lcreg(bus->dhd->osh, 0, 0);
++
++		int_val = ((clkreq & 0x1) << 8) | (aspm & PCIE_ASPM_ENAB);
++		bcopy(&int_val, arg, val_size);
++		break;
++	}
++
++	case IOV_SVAL(IOV_PCIEASPM): {
++		uint32 tmp;
++
++		tmp = dhdpcie_lcreg(bus->dhd->osh, 0, 0);
++		dhdpcie_lcreg(bus->dhd->osh, PCIE_ASPM_ENAB,
++			(tmp & ~PCIE_ASPM_ENAB) | (int_val & PCIE_ASPM_ENAB));
++
++		dhdpcie_clkreq(bus->dhd->osh, 1, ((int_val & 0x100) >> 8));
++		break;
++	}
++
++	case IOV_SVAL(IOV_HANGREPORT):
++		bus->dhd->hang_report = bool_val;
++		DHD_ERROR(("%s: Set hang_report as %d\n",
++			__FUNCTION__, bus->dhd->hang_report));
++		break;
++
++	case IOV_GVAL(IOV_HANGREPORT):
++		int_val = (int32)bus->dhd->hang_report;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	default:
++		bcmerror = BCME_UNSUPPORTED;
++		break;
++	}
++
++exit:
++	return bcmerror;
++} /* dhdpcie_bus_doiovar */
++
++/** Transfers bytes from host to dongle using pio mode */
++static int
++dhdpcie_bus_lpback_req(struct  dhd_bus *bus, uint32 len)
++{
++	if (bus->dhd == NULL) {
++		DHD_ERROR(("bus not inited\n"));
++		return 0;
++	}
++	if (bus->dhd->prot == NULL) {
++		DHD_ERROR(("prot is not inited\n"));
++		return 0;
++	}
++	if (bus->dhd->busstate != DHD_BUS_DATA) {
++		DHD_ERROR(("not in a readystate to LPBK  is not inited\n"));
++		return 0;
++	}
++	dhdmsgbuf_lpbk_req(bus->dhd, len);
++	return 0;
++}
++
++int
++dhdpcie_bus_suspend(struct dhd_bus *bus, bool state)
++{
++	int timeleft;
++	unsigned long flags;
++	int rc = 0;
++
++	if (bus->dhd == NULL) {
++		DHD_ERROR(("bus not inited\n"));
++		return BCME_ERROR;
++	}
++	if (bus->dhd->prot == NULL) {
++		DHD_ERROR(("prot is not inited\n"));
++		return BCME_ERROR;
++	}
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	if (bus->dhd->busstate != DHD_BUS_DATA && bus->dhd->busstate != DHD_BUS_SUSPEND) {
++		DHD_ERROR(("not in a readystate to LPBK  is not inited\n"));
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++		return BCME_ERROR;
++	}
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++	if (bus->dhd->dongle_reset) {
++		DHD_ERROR(("Dongle is in reset state.\n"));
++		return -EIO;
++	}
++
++	if (bus->suspended == state) { /* Set to same state */
++		DHD_ERROR(("Bus is already in SUSPEND state.\n"));
++		return BCME_OK;
++	}
++
++	if (state) {
++		int idle_retry = 0;
++		int active;
++
++		/* Suspend */
++		DHD_ERROR(("%s: Entering suspend state\n", __FUNCTION__));
++		bus->wait_for_d3_ack = 0;
++		bus->suspended = TRUE;
++		DHD_GENERAL_LOCK(bus->dhd, flags);
++		bus->dhd->busstate = DHD_BUS_SUSPEND;
++		if (bus->dhd->dhd_bus_busy_state & DHD_BUS_BUSY_IN_TX) {
++			DHD_ERROR(("Tx Request is not ended\n"));
++			bus->dhd->busstate = DHD_BUS_DATA;
++			DHD_GENERAL_UNLOCK(bus->dhd, flags);
++			bus->suspended = FALSE;
++			return -EBUSY;
++		}
++		bus->dhd->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_SUSPEND;
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++		DHD_OS_WAKE_LOCK_WAIVE(bus->dhd);
++		dhd_os_set_ioctl_resp_timeout(D3_ACK_RESP_TIMEOUT);
++		dhdpcie_send_mb_data(bus, H2D_HOST_D3_INFORM);
++		timeleft = dhd_os_d3ack_wait(bus->dhd, &bus->wait_for_d3_ack);
++		dhd_os_set_ioctl_resp_timeout(IOCTL_RESP_TIMEOUT);
++		DHD_OS_WAKE_LOCK_RESTORE(bus->dhd);
++
++		/* To allow threads that got pre-empted to complete.
++		 */
++		while ((active = dhd_os_check_wakelock_all(bus->dhd)) &&
++			(idle_retry < MAX_WKLK_IDLE_CHECK)) {
++			msleep(1);
++			idle_retry++;
++		}
++
++		if (bus->wait_for_d3_ack) {
++			DHD_ERROR(("%s: Got D3 Ack \n", __FUNCTION__));
++#if defined(BCMPCIE_OOB_HOST_WAKE)
++			dhdpcie_oob_intr_set(bus, TRUE);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++
++			/* Got D3 Ack. Suspend the bus */
++			if (active) {
++				DHD_ERROR(("%s():Suspend failed because of wakelock"
++					"restoring Dongle to D0\n", __FUNCTION__));
++
++				/*
++				 * Dongle still thinks that it has to be in D3 state until
++				 * it gets a D0 Inform, but we are backing off from suspend.
++				 * Ensure that Dongle is brought back to D0.
++				 *
++				 * Bringing back Dongle from D3 Ack state to D0 state is a
++				 * 2 step process. Dongle would want to know that D0 Inform
++				 * would be sent as a MB interrupt to bring it out of D3 Ack
++				 * state to D0 state. So we have to send both this message.
++				 */
++				DHD_OS_WAKE_LOCK_WAIVE(bus->dhd);
++				dhdpcie_send_mb_data(bus,
++					(H2D_HOST_D0_INFORM_IN_USE|H2D_HOST_D0_INFORM));
++				DHD_OS_WAKE_LOCK_RESTORE(bus->dhd);
++
++				bus->suspended = FALSE;
++				DHD_GENERAL_LOCK(bus->dhd, flags);
++				bus->dhd->busstate = DHD_BUS_DATA;
++				DHD_GENERAL_UNLOCK(bus->dhd, flags);
++				rc = BCME_ERROR;
++			} else {
++				DHD_OS_WAKE_LOCK_WAIVE(bus->dhd);
++				dhdpcie_send_mb_data(bus, (H2D_HOST_D0_INFORM_IN_USE));
++				DHD_OS_WAKE_LOCK_RESTORE(bus->dhd);
++				dhdpcie_bus_intr_disable(bus);
++				rc = dhdpcie_pci_suspend_resume(bus, state);
++				dhd_bus_set_device_wake(bus, FALSE);
++			}
++			bus->dhd->d3ackcnt_timeout = 0;
++		} else if (timeleft == 0) {
++			bus->dhd->d3ackcnt_timeout++;
++			DHD_ERROR(("%s: resumed on timeout for D3 ACK d3_inform_cnt %d \n",
++				__FUNCTION__, bus->dhd->d3ackcnt_timeout));
++			bus->suspended = FALSE;
++			DHD_GENERAL_LOCK(bus->dhd, flags);
++			bus->dhd->busstate = DHD_BUS_DATA;
++			DHD_GENERAL_UNLOCK(bus->dhd, flags);
++			if (bus->dhd->d3ackcnt_timeout >= MAX_CNTL_D3ACK_TIMEOUT) {
++				DHD_ERROR(("%s: Event HANG send up "
++					"due to PCIe linkdown\n", __FUNCTION__));
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#ifdef CONFIG_ARCH_MSM
++				bus->islinkdown = 1;
++#endif /* CONFIG_ARCH_MSM */
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++				dhd_os_check_hang(bus->dhd, 0, -ETIMEDOUT);
++			}
++			rc = -ETIMEDOUT;
++
++		}
++		bus->wait_for_d3_ack = 1;
++		DHD_GENERAL_LOCK(bus->dhd, flags);
++		bus->dhd->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_SUSPEND;
++		dhd_os_busbusy_wake(bus->dhd);
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++	} else {
++		/* Resume */
++#if defined(BCMPCIE_OOB_HOST_WAKE)
++		DHD_OS_OOB_IRQ_WAKE_UNLOCK(bus->dhd);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++		DHD_GENERAL_LOCK(bus->dhd, flags);
++		bus->dhd->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_RESUME;
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++		rc = dhdpcie_pci_suspend_resume(bus, state);
++		if (bus->dhd->busstate == DHD_BUS_SUSPEND) {
++			DHD_OS_WAKE_LOCK_WAIVE(bus->dhd);
++			dhdpcie_send_mb_data(bus, (H2D_HOST_D0_INFORM));
++			DHD_OS_WAKE_LOCK_RESTORE(bus->dhd);
++			dhd_bus_set_device_wake(bus, TRUE);
++		}
++		bus->suspended = FALSE;
++		DHD_GENERAL_LOCK(bus->dhd, flags);
++		bus->dhd->busstate = DHD_BUS_DATA;
++		bus->dhd->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_RESUME;
++		dhd_os_busbusy_wake(bus->dhd);
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++		dhdpcie_bus_intr_enable(bus);
++	}
++	return rc;
++}
++
++/** Transfers bytes from host to dongle and to host again using DMA */
++static int
++dhdpcie_bus_dmaxfer_req(struct  dhd_bus *bus, uint32 len, uint32 srcdelay, uint32 destdelay)
++{
++	if (bus->dhd == NULL) {
++		DHD_ERROR(("bus not inited\n"));
++		return BCME_ERROR;
++	}
++	if (bus->dhd->prot == NULL) {
++		DHD_ERROR(("prot is not inited\n"));
++		return BCME_ERROR;
++	}
++	if (bus->dhd->busstate != DHD_BUS_DATA) {
++		DHD_ERROR(("not in a readystate to LPBK  is not inited\n"));
++		return BCME_ERROR;
++	}
++
++	if (len < 5 || len > 4194296) {
++		DHD_ERROR(("len is too small or too large\n"));
++		return BCME_ERROR;
++	}
++	return dhdmsgbuf_dmaxfer_req(bus->dhd, len, srcdelay, destdelay);
++}
++
++
++
++static int
++dhdpcie_bus_download_state(dhd_bus_t *bus, bool enter)
++{
++	int bcmerror = 0;
++	uint32 *cr4_regs;
++
++	if (!bus->sih) {
++		DHD_ERROR(("%s: NULL sih!!\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++	/* To enter download state, disable ARM and reset SOCRAM.
++	 * To exit download state, simply reset ARM (default is RAM boot).
++	 */
++	if (enter) {
++		/* To handle failures due to unmanaged perst scenarios,
++		 * introducing back plane reset before FW download.
++		 */
++		pcie_watchdog_reset(bus->osh, bus->sih, (sbpcieregs_t *)(bus->regs));
++		/* Make sure BAR1 maps to backplane address 0 */
++		dhdpcie_bus_cfg_write_dword(bus, PCI_BAR1_WIN, 4, 0x00000000);
++		bus->alp_only = TRUE;
++
++		/* some chips (e.g. 43602) have two ARM cores, the CR4 is receives the firmware. */
++		cr4_regs = si_setcore(bus->sih, ARMCR4_CORE_ID, 0);
++
++		if (cr4_regs == NULL && !(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
++		    !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0)) &&
++		    !(si_setcore(bus->sih, ARMCA7_CORE_ID, 0))) {
++			DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__));
++			bcmerror = BCME_ERROR;
++			goto fail;
++		}
++
++		if (si_setcore(bus->sih, ARMCA7_CORE_ID, 0)) {
++			/* Halt ARM & remove reset */
++			si_core_reset(bus->sih, SICF_CPUHALT, SICF_CPUHALT);
++			if (!(si_setcore(bus->sih, SYSMEM_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find SYSMEM core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++			si_core_reset(bus->sih, 0, 0);
++			/* reset last 4 bytes of RAM address. to be used for shared area */
++			dhdpcie_init_shared_addr(bus);
++		} else if (cr4_regs == NULL) { /* no CR4 present on chip */
++			si_core_disable(bus->sih, 0);
++
++			if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++
++			si_core_reset(bus->sih, 0, 0);
++
++			/* Clear the top bit of memory */
++			if (bus->ramsize) {
++				uint32 zeros = 0;
++				if (dhdpcie_bus_membytes(bus, TRUE, bus->ramsize - 4,
++				                     (uint8*)&zeros, 4) < 0) {
++					bcmerror = BCME_ERROR;
++					goto fail;
++				}
++			}
++		} else {
++			/* For CR4,
++			 * Halt ARM
++			 * Remove ARM reset
++			 * Read RAM base address [0x18_0000]
++			 * [next] Download firmware
++			 * [done at else] Populate the reset vector
++			 * [done at else] Remove ARM halt
++			*/
++			/* Halt ARM & remove reset */
++			si_core_reset(bus->sih, SICF_CPUHALT, SICF_CPUHALT);
++			if (BCM43602_CHIP(bus->sih->chip)) {
++				W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKIDX, 5);
++				W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKPDA, 0);
++				W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKIDX, 7);
++				W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKPDA, 0);
++			}
++			/* reset last 4 bytes of RAM address. to be used for shared area */
++			dhdpcie_init_shared_addr(bus);
++		}
++	} else {
++		if (si_setcore(bus->sih, ARMCA7_CORE_ID, 0)) {
++			/* write vars */
++			if ((bcmerror = dhdpcie_bus_write_vars(bus))) {
++				DHD_ERROR(("%s: could not write vars to RAM\n", __FUNCTION__));
++				goto fail;
++			}
++			/* switch back to arm core again */
++			if (!(si_setcore(bus->sih, ARMCA7_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find ARM CA7 core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++			/* write address 0 with reset instruction */
++			bcmerror = dhdpcie_bus_membytes(bus, TRUE, 0,
++				(uint8 *)&bus->resetinstr, sizeof(bus->resetinstr));
++			/* now remove reset and halt and continue to run CA7 */
++		} else if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
++			if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++
++			if (!si_iscoreup(bus->sih)) {
++				DHD_ERROR(("%s: SOCRAM core is down after reset?\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++
++			/* Enable remap before ARM reset but after vars.
++			 * No backplane access in remap mode
++			 */
++			if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
++			    !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
++				DHD_ERROR(("%s: Can't change back to SDIO core?\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++
++
++			if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
++			    !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++		} else {
++			if (BCM43602_CHIP(bus->sih->chip)) {
++				/* Firmware crashes on SOCSRAM access when core is in reset */
++				if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
++					DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
++						__FUNCTION__));
++					bcmerror = BCME_ERROR;
++					goto fail;
++				}
++				si_core_reset(bus->sih, 0, 0);
++				si_setcore(bus->sih, ARMCR4_CORE_ID, 0);
++			}
++
++			/* write vars */
++			if ((bcmerror = dhdpcie_bus_write_vars(bus))) {
++				DHD_ERROR(("%s: could not write vars to RAM\n", __FUNCTION__));
++				goto fail;
++			}
++
++			/* switch back to arm core again */
++			if (!(si_setcore(bus->sih, ARMCR4_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find ARM CR4 core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++
++			/* write address 0 with reset instruction */
++			bcmerror = dhdpcie_bus_membytes(bus, TRUE, 0,
++				(uint8 *)&bus->resetinstr, sizeof(bus->resetinstr));
++
++			if (bcmerror == BCME_OK) {
++				uint32 tmp;
++
++				bcmerror = dhdpcie_bus_membytes(bus, FALSE, 0,
++				                                (uint8 *)&tmp, sizeof(tmp));
++
++				if (bcmerror == BCME_OK && tmp != bus->resetinstr) {
++					DHD_ERROR(("%s: Failed to write 0x%08x to addr 0\n",
++					          __FUNCTION__, bus->resetinstr));
++					DHD_ERROR(("%s: contents of addr 0 is 0x%08x\n",
++					          __FUNCTION__, tmp));
++					bcmerror = BCME_ERROR;
++					goto fail;
++				}
++			}
++
++			/* now remove reset and halt and continue to run CR4 */
++		}
++
++		si_core_reset(bus->sih, 0, 0);
++
++		/* Allow HT Clock now that the ARM is running. */
++		bus->alp_only = FALSE;
++
++		bus->dhd->busstate = DHD_BUS_LOAD;
++	}
++
++fail:
++	/* Always return to PCIE core */
++	si_setcore(bus->sih, PCIE2_CORE_ID, 0);
++
++	return bcmerror;
++} /* dhdpcie_bus_download_state */
++
++static int
++dhdpcie_bus_write_vars(dhd_bus_t *bus)
++{
++	int bcmerror = 0;
++	uint32 varsize, phys_size;
++	uint32 varaddr;
++	uint8 *vbuffer;
++	uint32 varsizew;
++#if (defined DHD_DEBUG && !defined(CUSTOMER_HW_31_2))
++	uint8 *nvram_ularray;
++#endif /* DHD_DEBUG */
++
++	/* Even if there are no vars are to be written, we still need to set the ramsize. */
++	varsize = bus->varsz ? ROUNDUP(bus->varsz, 4) : 0;
++	varaddr = (bus->ramsize - 4) - varsize;
++
++	varaddr += bus->dongle_ram_base;
++
++	if (bus->vars) {
++
++		vbuffer = (uint8 *)MALLOC(bus->dhd->osh, varsize);
++		if (!vbuffer)
++			return BCME_NOMEM;
++
++		bzero(vbuffer, varsize);
++		bcopy(bus->vars, vbuffer, bus->varsz);
++		/* Write the vars list */
++		bcmerror = dhdpcie_bus_membytes(bus, TRUE, varaddr, vbuffer, varsize);
++
++		/* Implement read back and verify later */
++#if (defined DHD_DEBUG && !defined(CUSTOMER_HW_31_2))
++		/* Verify NVRAM bytes */
++		DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
++		nvram_ularray = (uint8*)MALLOC(bus->dhd->osh, varsize);
++		if (!nvram_ularray)
++			return BCME_NOMEM;
++
++		/* Upload image to verify downloaded contents. */
++		memset(nvram_ularray, 0xaa, varsize);
++
++		/* Read the vars list to temp buffer for comparison */
++		bcmerror = dhdpcie_bus_membytes(bus, FALSE, varaddr, nvram_ularray, varsize);
++		if (bcmerror) {
++				DHD_ERROR(("%s: error %d on reading %d nvram bytes at 0x%08x\n",
++					__FUNCTION__, bcmerror, varsize, varaddr));
++		}
++
++		/* Compare the org NVRAM with the one read from RAM */
++		if (memcmp(vbuffer, nvram_ularray, varsize)) {
++			DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n", __FUNCTION__));
++		} else
++			DHD_ERROR(("%s: Download, Upload and compare of NVRAM succeeded.\n",
++			__FUNCTION__));
++
++		MFREE(bus->dhd->osh, nvram_ularray, varsize);
++#endif /* DHD_DEBUG */
++
++		MFREE(bus->dhd->osh, vbuffer, varsize);
++	}
++
++	phys_size = REMAP_ENAB(bus) ? bus->ramsize : bus->orig_ramsize;
++
++	phys_size += bus->dongle_ram_base;
++
++	/* adjust to the user specified RAM */
++	DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
++		phys_size, bus->ramsize));
++	DHD_INFO(("Vars are at %d, orig varsize is %d\n",
++		varaddr, varsize));
++	varsize = ((phys_size - 4) - varaddr);
++
++	/*
++	 * Determine the length token:
++	 * Varsize, converted to words, in lower 16-bits, checksum in upper 16-bits.
++	 */
++	if (bcmerror) {
++		varsizew = 0;
++		bus->nvram_csm = varsizew;
++	} else {
++		varsizew = varsize / 4;
++		varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
++		bus->nvram_csm = varsizew;
++		varsizew = htol32(varsizew);
++	}
++
++	DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize, varsizew));
++
++	/* Write the length token to the last word */
++	bcmerror = dhdpcie_bus_membytes(bus, TRUE, (phys_size - 4),
++		(uint8*)&varsizew, 4);
++
++	return bcmerror;
++} /* dhdpcie_bus_write_vars */
++
++int
++dhdpcie_downloadvars(dhd_bus_t *bus, void *arg, int len)
++{
++	int bcmerror = BCME_OK;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	/* Basic sanity checks */
++	if (bus->dhd->up) {
++		bcmerror = BCME_NOTDOWN;
++		goto err;
++	}
++	if (!len) {
++		bcmerror = BCME_BUFTOOSHORT;
++		goto err;
++	}
++
++	/* Free the old ones and replace with passed variables */
++	if (bus->vars)
++		MFREE(bus->dhd->osh, bus->vars, bus->varsz);
++
++	bus->vars = MALLOC(bus->dhd->osh, len);
++	bus->varsz = bus->vars ? len : 0;
++	if (bus->vars == NULL) {
++		bcmerror = BCME_NOMEM;
++		goto err;
++	}
++
++	/* Copy the passed variables, which should include the terminating double-null */
++	bcopy(arg, bus->vars, bus->varsz);
++
++
++err:
++	return bcmerror;
++}
++
++/* loop through the capability list and see if the pcie capabilty exists */
++uint8
++dhdpcie_find_pci_capability(osl_t *osh, uint8 req_cap_id)
++{
++	uint8 cap_id;
++	uint8 cap_ptr = 0;
++	uint8 byte_val;
++
++	/* check for Header type 0 */
++	byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
++	if ((byte_val & 0x7f) != PCI_HEADER_NORMAL) {
++		DHD_ERROR(("%s : PCI config header not normal.\n", __FUNCTION__));
++		goto end;
++	}
++
++	/* check if the capability pointer field exists */
++	byte_val = read_pci_cfg_byte(PCI_CFG_STAT);
++	if (!(byte_val & PCI_CAPPTR_PRESENT)) {
++		DHD_ERROR(("%s : PCI CAP pointer not present.\n", __FUNCTION__));
++		goto end;
++	}
++
++	cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR);
++	/* check if the capability pointer is 0x00 */
++	if (cap_ptr == 0x00) {
++		DHD_ERROR(("%s : PCI CAP pointer is 0x00.\n", __FUNCTION__));
++		goto end;
++	}
++
++	/* loop thr'u the capability list and see if the pcie capabilty exists */
++
++	cap_id = read_pci_cfg_byte(cap_ptr);
++
++	while (cap_id != req_cap_id) {
++		cap_ptr = read_pci_cfg_byte((cap_ptr + 1));
++		if (cap_ptr == 0x00) break;
++		cap_id = read_pci_cfg_byte(cap_ptr);
++	}
++
++end:
++	return cap_ptr;
++}
++
++void
++dhdpcie_pme_active(osl_t *osh, bool enable)
++{
++	uint8 cap_ptr;
++	uint32 pme_csr;
++
++	cap_ptr = dhdpcie_find_pci_capability(osh, PCI_CAP_POWERMGMTCAP_ID);
++
++	if (!cap_ptr) {
++		DHD_ERROR(("%s : Power Management Capability not present\n", __FUNCTION__));
++		return;
++	}
++
++	pme_csr = OSL_PCI_READ_CONFIG(osh, cap_ptr + PME_CSR_OFFSET, sizeof(uint32));
++	DHD_ERROR(("%s : pme_sts_ctrl 0x%x\n", __FUNCTION__, pme_csr));
++
++	pme_csr |= PME_CSR_PME_STAT;
++	if (enable) {
++		pme_csr |= PME_CSR_PME_EN;
++	} else {
++		pme_csr &= ~PME_CSR_PME_EN;
++	}
++
++	OSL_PCI_WRITE_CONFIG(osh, cap_ptr + PME_CSR_OFFSET, sizeof(uint32), pme_csr);
++}
++
++bool
++dhdpcie_pme_cap(osl_t *osh)
++{
++	uint8 cap_ptr;
++	uint32 pme_cap;
++
++	cap_ptr = dhdpcie_find_pci_capability(osh, PCI_CAP_POWERMGMTCAP_ID);
++
++	if (!cap_ptr) {
++		DHD_ERROR(("%s : Power Management Capability not present\n", __FUNCTION__));
++		return FALSE;
++	}
++
++	pme_cap = OSL_PCI_READ_CONFIG(osh, cap_ptr, sizeof(uint32));
++
++	DHD_ERROR(("%s : pme_cap 0x%x\n", __FUNCTION__, pme_cap));
++
++	return ((pme_cap & PME_CAP_PM_STATES) != 0);
++}
++
++uint32
++dhdpcie_lcreg(osl_t *osh, uint32 mask, uint32 val)
++{
++	uint8	pcie_cap;
++	uint8	lcreg_offset;	/* PCIE capability LCreg offset in the config space */
++	uint32	reg_val;
++
++	pcie_cap = dhdpcie_find_pci_capability(osh, PCI_CAP_PCIECAP_ID);
++
++	if (!pcie_cap) {
++		DHD_ERROR(("%s : PCIe Capability not present\n", __FUNCTION__));
++		return 0;
++	}
++
++	lcreg_offset = pcie_cap + PCIE_CAP_LINKCTRL_OFFSET;
++
++	/* set operation */
++	if (mask) {
++		/* read */
++		reg_val = OSL_PCI_READ_CONFIG(osh, lcreg_offset, sizeof(uint32));
++
++		/* modify */
++		reg_val &= ~mask;
++		reg_val |= (mask & val);
++
++		/* write */
++		OSL_PCI_WRITE_CONFIG(osh, lcreg_offset, sizeof(uint32), reg_val);
++	}
++	return OSL_PCI_READ_CONFIG(osh, lcreg_offset, sizeof(uint32));
++}
++
++uint8
++dhdpcie_clkreq(osl_t *osh, uint32 mask, uint32 val)
++{
++	uint8	pcie_cap;
++	uint32	reg_val;
++	uint8	lcreg_offset;	/* PCIE capability LCreg offset in the config space */
++
++	pcie_cap = dhdpcie_find_pci_capability(osh, PCI_CAP_PCIECAP_ID);
++
++	if (!pcie_cap) {
++		DHD_ERROR(("%s : PCIe Capability not present\n", __FUNCTION__));
++		return 0;
++	}
++
++	lcreg_offset = pcie_cap + PCIE_CAP_LINKCTRL_OFFSET;
++
++	reg_val = OSL_PCI_READ_CONFIG(osh, lcreg_offset, sizeof(uint32));
++	/* set operation */
++	if (mask) {
++		if (val)
++			reg_val |= PCIE_CLKREQ_ENAB;
++		else
++			reg_val &= ~PCIE_CLKREQ_ENAB;
++		OSL_PCI_WRITE_CONFIG(osh, lcreg_offset, sizeof(uint32), reg_val);
++		reg_val = OSL_PCI_READ_CONFIG(osh, lcreg_offset, sizeof(uint32));
++	}
++	if (reg_val & PCIE_CLKREQ_ENAB)
++		return 1;
++	else
++		return 0;
++}
++
++void dhd_dump_intr_registers(dhd_pub_t *dhd, struct bcmstrbuf *strbuf)
++{
++	uint32 intstatus = 0;
++	uint32 intmask = 0;
++	uint32 mbintstatus = 0;
++	uint32 d2h_mb_data = 0;
++
++	intstatus = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, PCIMailBoxInt, 0, 0);
++	intmask = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, PCIMailBoxMask, 0, 0);
++	mbintstatus = si_corereg(dhd->bus->sih, dhd->bus->sih->buscoreidx, PCID2H_MailBox, 0, 0);
++	dhd_bus_cmn_readshared(dhd->bus, &d2h_mb_data, D2H_MB_DATA, 0);
++
++	bcm_bprintf(strbuf, "intstatus=0x%x intmask=0x%x mbintstatus=0x%x\n",
++		intstatus, intmask, mbintstatus);
++	bcm_bprintf(strbuf, "d2h_mb_data=0x%x def_intmask=0x%x\n",
++		d2h_mb_data, dhd->bus->def_intmask);
++}
++
++/** Add bus dump output to a buffer */
++void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
++{
++	uint16 flowid;
++	int ix = 0;
++	flow_ring_node_t *flow_ring_node;
++	flow_info_t *flow_info;
++	char eabuf[ETHER_ADDR_STR_LEN];
++
++	if (dhdp->busstate != DHD_BUS_DATA)
++		return;
++
++	dhd_prot_print_info(dhdp, strbuf);
++	dhd_dump_intr_registers(dhdp, strbuf);
++	bcm_bprintf(strbuf, "dhd cumm_ctr %d\n", DHD_CUMM_CTR_READ(&dhdp->cumm_ctr));
++	bcm_bprintf(strbuf,
++		"%s %4s %2s %4s %17s %4s %4s %6s %10s %4s %4s ",
++		"Num:", "Flow", "If", "Prio", ":Dest_MacAddress:", "Qlen", "CLen", "L2CLen",
++		"Overflows", "RD", "WR");
++	bcm_bprintf(strbuf, "%5s %6s %5s \n", "Acked", "tossed", "noack");
++
++	for (flowid = 0; flowid < dhdp->num_flow_rings; flowid++) {
++		flow_ring_node = DHD_FLOW_RING(dhdp, flowid);
++		if (!flow_ring_node->active)
++			continue;
++
++		flow_info = &flow_ring_node->flow_info;
++		bcm_bprintf(strbuf,
++			"%3d. %4d %2d %4d %17s %4d %4d %6d %10u ", ix++,
++			flow_ring_node->flowid, flow_info->ifindex, flow_info->tid,
++			bcm_ether_ntoa((struct ether_addr *)&flow_info->da, eabuf),
++			DHD_FLOW_QUEUE_LEN(&flow_ring_node->queue),
++			DHD_CUMM_CTR_READ(DHD_FLOW_QUEUE_CLEN_PTR(&flow_ring_node->queue)),
++			DHD_CUMM_CTR_READ(DHD_FLOW_QUEUE_L2CLEN_PTR(&flow_ring_node->queue)),
++			DHD_FLOW_QUEUE_FAILURES(&flow_ring_node->queue));
++		dhd_prot_print_flow_ring(dhdp, flow_ring_node->prot_info, strbuf,
++			"%4d %4d ");
++		bcm_bprintf(strbuf,
++			"%5s %6s %5s\n", "NA", "NA", "NA");
++	}
++	bcm_bprintf(strbuf, "D3 inform cnt %d\n", dhdp->bus->d3_inform_cnt);
++	bcm_bprintf(strbuf, "D0 inform cnt %d\n", dhdp->bus->d0_inform_cnt);
++	bcm_bprintf(strbuf, "D0 inform in use cnt %d\n", dhdp->bus->d0_inform_in_use_cnt);
++}
++
++/**
++ * Brings transmit packets on all flow rings closer to the dongle, by moving (a subset) from their
++ * flow queue to their flow ring.
++ */
++static void
++dhd_update_txflowrings(dhd_pub_t *dhd)
++{
++	unsigned long flags;
++	dll_t *item, *next;
++	flow_ring_node_t *flow_ring_node;
++	struct dhd_bus *bus = dhd->bus;
++
++	DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags);
++	for (item = dll_head_p(&bus->const_flowring);
++		(!dhd_is_device_removed(dhd) && !dll_end(&bus->const_flowring, item));
++		item = next) {
++		if (dhd->hang_was_sent) {
++			break;
++		}
++
++		next = dll_next_p(item);
++		flow_ring_node = dhd_constlist_to_flowring(item);
++
++		/* Ensure that flow_ring_node in the list is Not Null */
++		ASSERT(flow_ring_node != NULL);
++
++		/* Ensure that the flowring node has valid contents */
++		ASSERT(flow_ring_node->prot_info != NULL);
++
++		dhd_prot_update_txflowring(dhd, flow_ring_node->flowid, flow_ring_node->prot_info);
++	}
++	DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags);
++}
++
++/** Mailbox ringbell Function */
++static void
++dhd_bus_gen_devmb_intr(struct dhd_bus *bus)
++{
++	if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) ||
++		(bus->sih->buscorerev == 4)) {
++		DHD_ERROR(("mailbox communication not supported\n"));
++		return;
++	}
++	if (bus->db1_for_mb)  {
++		/* this is a pcie core register, not the config register */
++		DHD_INFO(("writing a mail box interrupt to the device, through doorbell 1\n"));
++		si_corereg(bus->sih, bus->sih->buscoreidx, PCIH2D_DB1, ~0, 0x12345678);
++	} else {
++		DHD_INFO(("writing a mail box interrupt to the device, through config space\n"));
++		dhdpcie_bus_cfg_write_dword(bus, PCISBMbx, 4, (1 << 0));
++		dhdpcie_bus_cfg_write_dword(bus, PCISBMbx, 4, (1 << 0));
++	}
++}
++
++static void
++dhd_bus_set_device_wake(struct dhd_bus *bus, bool val)
++{
++	if (bus->device_wake_state != val)
++	{
++		DHD_INFO(("Set Device_Wake to %d\n", val));
++#ifdef PCIE_OOB
++		if (bus->oob_enabled)
++		{
++			if (val)
++			{
++				gpio_port = gpio_port | (1 << DEVICE_WAKE);
++				gpio_write_port_non_block(gpio_handle_val, gpio_port);
++			} else {
++				gpio_port = gpio_port & (0xff ^ (1 << DEVICE_WAKE));
++				gpio_write_port_non_block(gpio_handle_val, gpio_port);
++			}
++		}
++#endif /* PCIE_OOB */
++		bus->device_wake_state = val;
++	}
++}
++
++#ifdef PCIE_OOB
++void
++dhd_oob_set_bt_reg_on(struct dhd_bus *bus, bool val)
++{
++	DHD_INFO(("Set Device_Wake to %d\n", val));
++	if (val)
++	{
++		gpio_port = gpio_port | (1 << BIT_BT_REG_ON);
++		gpio_write_port(gpio_handle_val, gpio_port);
++	} else {
++		gpio_port = gpio_port & (0xff ^ (1 << BIT_BT_REG_ON));
++		gpio_write_port(gpio_handle_val, gpio_port);
++	}
++}
++
++int
++dhd_oob_get_bt_reg_on(struct dhd_bus *bus)
++{
++	int ret;
++	uint8 val;
++	ret = gpio_read_port(gpio_handle_val, &val);
++
++	if (ret < 0) {
++		DHD_ERROR(("gpio_read_port returns %d\n", ret));
++		return ret;
++	}
++
++	if (val & (1 << BIT_BT_REG_ON))
++	{
++		ret = 1;
++	} else {
++		ret = 0;
++	}
++
++	return ret;
++}
++
++static void
++dhd_bus_doorbell_timeout_reset(struct dhd_bus *bus)
++{
++	if (dhd_doorbell_timeout)
++		dhd_timeout_start(&bus->doorbell_timer,
++			(dhd_doorbell_timeout * 1000) / dhd_watchdog_ms);
++	else if (!(bus->dhd->busstate == DHD_BUS_SUSPEND))
++		dhd_bus_set_device_wake(bus, FALSE);
++}
++#endif /* PCIE_OOB */
++
++/** mailbox doorbell ring function */
++void
++dhd_bus_ringbell(struct dhd_bus *bus, uint32 value)
++{
++	if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) ||
++		(bus->sih->buscorerev == 4)) {
++		si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxInt, PCIE_INTB, PCIE_INTB);
++	} else {
++		/* this is a pcie core register, not the config regsiter */
++		DHD_INFO(("writing a door bell to the device\n"));
++		si_corereg(bus->sih, bus->sih->buscoreidx, PCIH2D_MailBox, ~0, 0x12345678);
++	}
++}
++
++void
++dhdpcie_bus_ringbell_fast(struct dhd_bus *bus, uint32 value)
++{
++#ifdef PCIE_OOB
++	dhd_bus_set_device_wake(bus, TRUE);
++	dhd_bus_doorbell_timeout_reset(bus);
++#endif
++	W_REG(bus->pcie_mb_intr_osh, bus->pcie_mb_intr_addr, value);
++}
++
++static void
++dhd_bus_ringbell_oldpcie(struct dhd_bus *bus, uint32 value)
++{
++	uint32 w;
++	w = (R_REG(bus->pcie_mb_intr_osh, bus->pcie_mb_intr_addr) & ~PCIE_INTB) | PCIE_INTB;
++	W_REG(bus->pcie_mb_intr_osh, bus->pcie_mb_intr_addr, w);
++}
++
++dhd_mb_ring_t
++dhd_bus_get_mbintr_fn(struct dhd_bus *bus)
++{
++	if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) ||
++		(bus->sih->buscorerev == 4)) {
++		bus->pcie_mb_intr_addr = si_corereg_addr(bus->sih, bus->sih->buscoreidx,
++			PCIMailBoxInt);
++		if (bus->pcie_mb_intr_addr) {
++			bus->pcie_mb_intr_osh = si_osh(bus->sih);
++			return dhd_bus_ringbell_oldpcie;
++		}
++	} else {
++		bus->pcie_mb_intr_addr = si_corereg_addr(bus->sih, bus->sih->buscoreidx,
++			PCIH2D_MailBox);
++		if (bus->pcie_mb_intr_addr) {
++			bus->pcie_mb_intr_osh = si_osh(bus->sih);
++			return dhdpcie_bus_ringbell_fast;
++		}
++	}
++	return dhd_bus_ringbell;
++}
++
++bool BCMFASTPATH
++dhd_bus_dpc(struct dhd_bus *bus)
++{
++	bool resched = FALSE;	  /* Flag indicating resched wanted */
++	unsigned long flags;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	/* Check for only DHD_BUS_DOWN and not for DHD_BUS_DOWN_IN_PROGRESS
++	 * to avoid IOCTL Resumed On timeout when ioctl is waiting for response
++	 * and rmmod is fired in parallel, which will make DHD_BUS_DOWN_IN_PROGRESS
++	 * and if we return from here, then IOCTL response will never be handled
++	 */
++	if (bus->dhd->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s: Bus down, ret\n", __FUNCTION__));
++		bus->intstatus = 0;
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++		return 0;
++	}
++	bus->dhd->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_DPC;
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	resched = dhdpcie_bus_process_mailbox_intr(bus, bus->intstatus);
++	if (!resched) {
++		bus->intstatus = 0;
++		dhdpcie_bus_intr_enable(bus);
++	}
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	bus->dhd->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_DPC;
++	dhd_os_busbusy_wake(bus->dhd);
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	return resched;
++
++}
++
++
++/* Upon receiving a mailbox interrupt,
++ * if H2D_FW_TRAP bit is set in mailbox location
++ * device traps
++ */
++static void
++dhdpcie_fw_trap(dhd_bus_t *bus)
++{
++	/* Send the mailbox data and generate mailbox intr. */
++	dhdpcie_send_mb_data(bus, H2D_FW_TRAP);
++	/* For FWs that cannot interprete H2D_FW_TRAP */
++	(void)dhd_wl_ioctl_set_intiovar(bus->dhd, "bus:disconnect", 99, WLC_SET_VAR, TRUE, 0);
++}
++
++
++static void
++dhdpcie_send_mb_data(dhd_bus_t *bus, uint32 h2d_mb_data)
++{
++	uint32 cur_h2d_mb_data = 0;
++
++	DHD_INFO_HW4(("%s: H2D_MB_DATA: 0x%08X\n", __FUNCTION__, h2d_mb_data));
++	dhd_bus_cmn_readshared(bus, &cur_h2d_mb_data, H2D_MB_DATA, 0);
++
++	if (cur_h2d_mb_data != 0) {
++		uint32 i = 0;
++		DHD_INFO(("GRRRRRRR: MB transaction is already pending 0x%04x\n", cur_h2d_mb_data));
++		while ((i++ < 100) && cur_h2d_mb_data) {
++			OSL_DELAY(10);
++			dhd_bus_cmn_readshared(bus, &cur_h2d_mb_data, H2D_MB_DATA, 0);
++		}
++		if (i >= 100) {
++			DHD_ERROR(("%s : waited 1ms for the dngl "
++				"to ack the previous mb transaction\n", __FUNCTION__));
++			DHD_ERROR(("%s : MB transaction is still pending 0x%04x\n",
++				__FUNCTION__, cur_h2d_mb_data));
++		}
++	}
++
++	dhd_bus_cmn_writeshared(bus, &h2d_mb_data, sizeof(uint32), H2D_MB_DATA, 0);
++	dhd_bus_gen_devmb_intr(bus);
++
++	if (h2d_mb_data == H2D_HOST_D3_INFORM) {
++		DHD_INFO_HW4(("%s: send H2D_HOST_D3_INFORM to dongle\n", __FUNCTION__));
++		bus->d3_inform_cnt++;
++	}
++	if (h2d_mb_data == H2D_HOST_D0_INFORM_IN_USE) {
++		DHD_INFO_HW4(("%s: send H2D_HOST_D0_INFORM_IN_USE to dongle\n", __FUNCTION__));
++		bus->d0_inform_in_use_cnt++;
++	}
++	if (h2d_mb_data == H2D_HOST_D0_INFORM) {
++		DHD_INFO_HW4(("%s: send H2D_HOST_D0_INFORM to dongle\n", __FUNCTION__));
++		bus->d0_inform_cnt++;
++	}
++}
++
++static void
++dhdpcie_handle_mb_data(dhd_bus_t *bus)
++{
++	uint32 d2h_mb_data = 0;
++	uint32 zero = 0;
++	dhd_bus_cmn_readshared(bus, &d2h_mb_data, D2H_MB_DATA, 0);
++	if (!d2h_mb_data) {
++		DHD_INFO_HW4(("%s: Invalid D2H_MB_DATA: 0x%08x\n",
++			__FUNCTION__, d2h_mb_data));
++		return;
++	}
++
++	dhd_bus_cmn_writeshared(bus, &zero, sizeof(uint32), D2H_MB_DATA, 0);
++
++	DHD_INFO_HW4(("D2H_MB_DATA: 0x%08x\n", d2h_mb_data));
++	if (d2h_mb_data & D2H_DEV_DS_ENTER_REQ)  {
++		/* what should we do */
++		DHD_INFO(("D2H_MB_DATA: DEEP SLEEP REQ\n"));
++		dhdpcie_send_mb_data(bus, H2D_HOST_DS_ACK);
++		DHD_INFO(("D2H_MB_DATA: sent DEEP SLEEP ACK\n"));
++	}
++	if (d2h_mb_data & D2H_DEV_DS_EXIT_NOTE)  {
++		/* what should we do */
++		DHD_INFO(("D2H_MB_DATA: DEEP SLEEP EXIT\n"));
++	}
++	if (d2h_mb_data & D2H_DEV_D3_ACK)  {
++		/* what should we do */
++		DHD_INFO_HW4(("D2H_MB_DATA: D3 ACK\n"));
++		if (!bus->wait_for_d3_ack) {
++			bus->wait_for_d3_ack = 1;
++			dhd_os_d3ack_wake(bus->dhd);
++		}
++	}
++	if (d2h_mb_data & D2H_DEV_FWHALT)  {
++		DHD_ERROR(("FW trap has happened\n"));
++		dhdpcie_checkdied(bus, NULL, 0);
++		/* not ready yet dhd_os_ind_firmware_stall(bus->dhd); */
++		bus->dhd->busstate = DHD_BUS_DOWN;
++	}
++}
++
++static bool
++dhdpcie_bus_process_mailbox_intr(dhd_bus_t *bus, uint32 intstatus)
++{
++	bool resched = FALSE;
++
++	if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) ||
++		(bus->sih->buscorerev == 4)) {
++		/* Msg stream interrupt */
++		if (intstatus & I_BIT1) {
++			resched = dhdpci_bus_read_frames(bus);
++		} else if (intstatus & I_BIT0) {
++			/* do nothing for Now */
++		}
++	} else {
++		if (intstatus & (PCIE_MB_TOPCIE_FN0_0 | PCIE_MB_TOPCIE_FN0_1))
++			dhdpcie_handle_mb_data(bus);
++
++		if (bus->dhd->busstate == DHD_BUS_SUSPEND) {
++			goto exit;
++		}
++
++		if (intstatus & PCIE_MB_D2H_MB_MASK) {
++			resched = dhdpci_bus_read_frames(bus);
++		}
++	}
++
++exit:
++	return resched;
++}
++
++static bool
++dhdpci_bus_read_frames(dhd_bus_t *bus)
++{
++	bool more = FALSE;
++
++	/* There may be frames in both ctrl buf and data buf; check ctrl buf first */
++	DHD_PERIM_LOCK_ALL((bus->dhd->fwder_unit % FWDER_MAX_UNIT));
++	dhd_prot_process_ctrlbuf(bus->dhd);
++	/* Unlock to give chance for resp to be handled */
++	DHD_PERIM_UNLOCK_ALL((bus->dhd->fwder_unit % FWDER_MAX_UNIT));
++
++	DHD_PERIM_LOCK_ALL((bus->dhd->fwder_unit % FWDER_MAX_UNIT));
++	/* update the flow ring cpls */
++	dhd_update_txflowrings(bus->dhd);
++
++	/* With heavy TX traffic, we could get a lot of TxStatus
++	 * so add bound
++	 */
++	more |= dhd_prot_process_msgbuf_txcpl(bus->dhd, dhd_txbound);
++
++	/* With heavy RX traffic, this routine potentially could spend some time
++	 * processing RX frames without RX bound
++	 */
++	more |= dhd_prot_process_msgbuf_rxcpl(bus->dhd, dhd_rxbound);
++
++	/* don't talk to the dongle if fw is about to be reloaded */
++	if (bus->dhd->hang_was_sent) {
++		more = FALSE;
++	}
++	DHD_PERIM_UNLOCK_ALL((bus->dhd->fwder_unit % FWDER_MAX_UNIT));
++
++	return more;
++}
++
++bool
++dhdpcie_tcm_valid(dhd_bus_t *bus)
++{
++	uint32 addr = 0;
++	int rv;
++	uint32 shaddr = 0;
++	pciedev_shared_t sh;
++
++	shaddr = bus->dongle_ram_base + bus->ramsize - 4;
++
++	/* Read last word in memory to determine address of pciedev_shared structure */
++	addr = LTOH32(dhdpcie_bus_rtcm32(bus, shaddr));
++
++	if ((addr == 0) || (addr == bus->nvram_csm) || (addr < bus->dongle_ram_base) ||
++		(addr > shaddr)) {
++		DHD_ERROR(("%s: address (0x%08x) of pciedev_shared invalid addr\n",
++			__FUNCTION__, addr));
++		return FALSE;
++	}
++
++	/* Read hndrte_shared structure */
++	if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)&sh,
++		sizeof(pciedev_shared_t))) < 0) {
++		DHD_ERROR(("Failed to read PCIe shared struct with %d\n", rv));
++		return FALSE;
++	}
++
++	/* Compare any field in pciedev_shared_t */
++	if (sh.console_addr != bus->pcie_sh->console_addr) {
++		DHD_ERROR(("Contents of pciedev_shared_t structure are not matching.\n"));
++		return FALSE;
++	}
++
++	return TRUE;
++}
++
++static bool
++dhdpcie_check_firmware_compatible(uint32 firmware_api_version, uint32 host_api_version)
++{
++	DHD_INFO(("firmware api revision %d, host api revision %d\n",
++		firmware_api_version, host_api_version));
++	if (firmware_api_version <= host_api_version)
++		return TRUE;
++	if ((firmware_api_version == 6) && (host_api_version == 5))
++		return TRUE;
++	if ((firmware_api_version == 5) && (host_api_version == 6))
++		return TRUE;
++	return FALSE;
++}
++
++static int
++dhdpcie_readshared(dhd_bus_t *bus)
++{
++	uint32 addr = 0;
++	int rv, dma_indx_wr_buf, dma_indx_rd_buf;
++	uint32 shaddr = 0;
++	pciedev_shared_t *sh = bus->pcie_sh;
++	dhd_timeout_t tmo;
++#ifdef CUSTOMER_HW_31_2
++	int count = 0;
++#endif
++
++	shaddr = bus->dongle_ram_base + bus->ramsize - 4;
++	/* start a timer for 5 seconds */
++#ifdef CUSTOMER_HW_31_2
++	while (((addr == 0) || (addr == bus->nvram_csm)) && (count++ < 500)) {
++#else
++	dhd_timeout_start(&tmo, MAX_READ_TIMEOUT);
++
++	while (((addr == 0) || (addr == bus->nvram_csm)) && !dhd_timeout_expired(&tmo)) {
++#endif
++		/* Read last word in memory to determine address of pciedev_shared structure */
++		addr = LTOH32(dhdpcie_bus_rtcm32(bus, shaddr));
++#ifdef CUSTOMER_HW_31_2
++		OSL_DELAY(10000);
++#endif
++	}
++
++	if ((addr == 0) || (addr == bus->nvram_csm) || (addr < bus->dongle_ram_base) ||
++		(addr > shaddr)) {
++		DHD_ERROR(("%s: address (0x%08x) of pciedev_shared invalid\n",
++			__FUNCTION__, addr));
++		DHD_ERROR(("Waited %u usec, dongle is not ready\n", tmo.elapsed));
++		return BCME_ERROR;
++	} else {
++		bus->shared_addr = (ulong)addr;
++		DHD_ERROR(("PCIe shared addr (0x%08x) read took %u usec "
++			"before dongle is ready\n", addr, tmo.elapsed));
++	}
++
++	/* Read hndrte_shared structure */
++	if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)sh,
++		sizeof(pciedev_shared_t))) < 0) {
++		DHD_ERROR(("Failed to read PCIe shared struct with %d\n", rv));
++		return rv;
++	}
++
++	/* Endianness */
++	sh->flags = ltoh32(sh->flags);
++	sh->trap_addr = ltoh32(sh->trap_addr);
++	sh->assert_exp_addr = ltoh32(sh->assert_exp_addr);
++	sh->assert_file_addr = ltoh32(sh->assert_file_addr);
++	sh->assert_line = ltoh32(sh->assert_line);
++	sh->console_addr = ltoh32(sh->console_addr);
++	sh->msgtrace_addr = ltoh32(sh->msgtrace_addr);
++	sh->dma_rxoffset = ltoh32(sh->dma_rxoffset);
++	sh->rings_info_ptr = ltoh32(sh->rings_info_ptr);
++
++#ifdef DHD_DEBUG
++	/* load bus console address */
++	bus->console_addr = sh->console_addr;
++#endif
++
++	/* Read the dma rx offset */
++	bus->dma_rxoffset = bus->pcie_sh->dma_rxoffset;
++	dhd_prot_rx_dataoffset(bus->dhd, bus->dma_rxoffset);
++
++	DHD_ERROR(("DMA RX offset from shared Area %d\n", bus->dma_rxoffset));
++
++	if (!(dhdpcie_check_firmware_compatible(sh->flags & PCIE_SHARED_VERSION_MASK,
++		PCIE_SHARED_VERSION)))
++	{
++		DHD_ERROR(("%s: pcie_shared version %d in dhd "
++		           "is older than pciedev_shared version %d in dongle\n",
++		           __FUNCTION__, PCIE_SHARED_VERSION,
++		           sh->flags & PCIE_SHARED_VERSION_MASK));
++		return BCME_ERROR;
++	}
++
++	bus->rw_index_sz = (sh->flags & PCIE_SHARED_2BYTE_INDICES) ?
++		sizeof(uint16) : sizeof(uint32);
++	DHD_ERROR(("%s: Dongle advertizes %d size indices\n",
++		__FUNCTION__, bus->rw_index_sz));
++
++	/* Does the FW support DMA'ing r/w indices */
++	if (sh->flags & PCIE_SHARED_DMA_INDEX) {
++
++
++		DHD_ERROR(("%s: Host support DMAing indices: H2D:%d - D2H:%d. FW supports it\n",
++			__FUNCTION__,
++			(DMA_INDX_ENAB(bus->dhd->dma_h2d_ring_upd_support) ? 1 : 0),
++			(DMA_INDX_ENAB(bus->dhd->dma_d2h_ring_upd_support) ? 1 : 0)));
++
++	} else if (DMA_INDX_ENAB(bus->dhd->dma_d2h_ring_upd_support) ||
++	           DMA_INDX_ENAB(bus->dhd->dma_h2d_ring_upd_support)) {
++
++#ifdef BCM_INDX_DMA
++		DHD_ERROR(("%s: Incompatible FW. FW does not support DMAing indices\n",
++			__FUNCTION__));
++		return BCME_ERROR;
++#endif
++		DHD_ERROR(("%s: Host supports DMAing indices but FW does not\n",
++			__FUNCTION__));
++		bus->dhd->dma_d2h_ring_upd_support = FALSE;
++		bus->dhd->dma_h2d_ring_upd_support = FALSE;
++	}
++
++
++	/* get ring_info, ring_state and mb data ptrs and store the addresses in bus structure */
++	{
++		ring_info_t  ring_info;
++
++		if ((rv = dhdpcie_bus_membytes(bus, FALSE, sh->rings_info_ptr,
++			(uint8 *)&ring_info, sizeof(ring_info_t))) < 0)
++			return rv;
++
++		bus->h2d_mb_data_ptr_addr = ltoh32(sh->h2d_mb_data_ptr);
++		bus->d2h_mb_data_ptr_addr = ltoh32(sh->d2h_mb_data_ptr);
++
++
++		bus->max_sub_queues = ltoh16(ring_info.max_sub_queues);
++
++		/* If both FW and Host support DMA'ing indices, allocate memory and notify FW
++		 * The max_sub_queues is read from FW initialized ring_info
++		 */
++		if (DMA_INDX_ENAB(bus->dhd->dma_h2d_ring_upd_support)) {
++			dma_indx_wr_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz,
++				H2D_DMA_INDX_WR_BUF, bus->max_sub_queues);
++			dma_indx_rd_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz,
++				D2H_DMA_INDX_RD_BUF, BCMPCIE_D2H_COMMON_MSGRINGS);
++
++			if ((dma_indx_wr_buf != BCME_OK) || (dma_indx_rd_buf != BCME_OK)) {
++				DHD_ERROR(("%s: Failed to allocate memory for dma'ing h2d indices"
++					"Host will use w/r indices in TCM\n",
++					__FUNCTION__));
++				bus->dhd->dma_h2d_ring_upd_support = FALSE;
++			}
++		}
++
++		if (DMA_INDX_ENAB(bus->dhd->dma_d2h_ring_upd_support)) {
++			dma_indx_wr_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz,
++				D2H_DMA_INDX_WR_BUF, BCMPCIE_D2H_COMMON_MSGRINGS);
++			dma_indx_rd_buf = dhd_prot_dma_indx_init(bus->dhd, bus->rw_index_sz,
++				H2D_DMA_INDX_RD_BUF, bus->max_sub_queues);
++
++			if ((dma_indx_wr_buf != BCME_OK) || (dma_indx_rd_buf != BCME_OK)) {
++				DHD_ERROR(("%s: Failed to allocate memory for dma'ing d2h indices"
++					"Host will use w/r indices in TCM\n",
++					__FUNCTION__));
++				bus->dhd->dma_d2h_ring_upd_support = FALSE;
++			}
++		}
++
++		/* read ringmem and ringstate ptrs from shared area and store in host variables */
++		dhd_fillup_ring_sharedptr_info(bus, &ring_info);
++
++		bcm_print_bytes("ring_info_raw", (uchar *)&ring_info, sizeof(ring_info_t));
++		DHD_INFO(("ring_info\n"));
++
++		DHD_ERROR(("%s: max H2D queues %d\n",
++			__FUNCTION__, ltoh16(ring_info.max_sub_queues)));
++
++		DHD_INFO(("mail box address\n"));
++		DHD_INFO(("%s: h2d_mb_data_ptr_addr 0x%04x\n",
++			__FUNCTION__, bus->h2d_mb_data_ptr_addr));
++		DHD_INFO(("%s: d2h_mb_data_ptr_addr 0x%04x\n",
++			__FUNCTION__, bus->d2h_mb_data_ptr_addr));
++	}
++
++	bus->dhd->d2h_sync_mode = sh->flags & PCIE_SHARED_D2H_SYNC_MODE_MASK;
++	DHD_INFO(("%s: d2h_sync_mode 0x%08x\n",
++		__FUNCTION__, bus->dhd->d2h_sync_mode));
++
++	return BCME_OK;
++} /* dhdpcie_readshared */
++
++/** Read ring mem and ring state ptr info from shared memory area in device memory */
++static void
++dhd_fillup_ring_sharedptr_info(dhd_bus_t *bus, ring_info_t *ring_info)
++{
++	uint16 i = 0;
++	uint16 j = 0;
++	uint32 tcm_memloc;
++	uint32	d2h_w_idx_ptr, d2h_r_idx_ptr, h2d_w_idx_ptr, h2d_r_idx_ptr;
++
++	/* Ring mem ptr info */
++	/* Alloated in the order
++		H2D_MSGRING_CONTROL_SUBMIT              0
++		H2D_MSGRING_RXPOST_SUBMIT               1
++		D2H_MSGRING_CONTROL_COMPLETE            2
++		D2H_MSGRING_TX_COMPLETE                 3
++		D2H_MSGRING_RX_COMPLETE                 4
++	*/
++
++	{
++		/* ringmemptr holds start of the mem block address space */
++		tcm_memloc = ltoh32(ring_info->ringmem_ptr);
++
++		/* Find out ringmem ptr for each ring common  ring */
++		for (i = 0; i <= BCMPCIE_COMMON_MSGRING_MAX_ID; i++) {
++			bus->ring_sh[i].ring_mem_addr = tcm_memloc;
++			/* Update mem block */
++			tcm_memloc = tcm_memloc + sizeof(ring_mem_t);
++			DHD_INFO(("ring id %d ring mem addr 0x%04x \n",
++				i, bus->ring_sh[i].ring_mem_addr));
++		}
++	}
++
++	/* Ring state mem ptr info */
++	{
++		d2h_w_idx_ptr = ltoh32(ring_info->d2h_w_idx_ptr);
++		d2h_r_idx_ptr = ltoh32(ring_info->d2h_r_idx_ptr);
++		h2d_w_idx_ptr = ltoh32(ring_info->h2d_w_idx_ptr);
++		h2d_r_idx_ptr = ltoh32(ring_info->h2d_r_idx_ptr);
++
++		/* Store h2d common ring write/read pointers */
++		for (i = 0; i < BCMPCIE_H2D_COMMON_MSGRINGS; i++) {
++			bus->ring_sh[i].ring_state_w = h2d_w_idx_ptr;
++			bus->ring_sh[i].ring_state_r = h2d_r_idx_ptr;
++
++			/* update mem block */
++			h2d_w_idx_ptr = h2d_w_idx_ptr + bus->rw_index_sz;
++			h2d_r_idx_ptr = h2d_r_idx_ptr + bus->rw_index_sz;
++
++			DHD_INFO(("h2d w/r : idx %d write %x read %x \n", i,
++				bus->ring_sh[i].ring_state_w, bus->ring_sh[i].ring_state_r));
++		}
++
++		/* Store d2h common ring write/read pointers */
++		for (j = 0; j < BCMPCIE_D2H_COMMON_MSGRINGS; j++, i++) {
++			bus->ring_sh[i].ring_state_w = d2h_w_idx_ptr;
++			bus->ring_sh[i].ring_state_r = d2h_r_idx_ptr;
++
++			/* update mem block */
++			d2h_w_idx_ptr = d2h_w_idx_ptr + bus->rw_index_sz;
++			d2h_r_idx_ptr = d2h_r_idx_ptr + bus->rw_index_sz;
++
++			DHD_INFO(("d2h w/r : idx %d write %x read %x \n", i,
++				bus->ring_sh[i].ring_state_w, bus->ring_sh[i].ring_state_r));
++		}
++
++		/* Store txflow ring write/read pointers */
++		for (j = 0; j < (bus->max_sub_queues - BCMPCIE_H2D_COMMON_MSGRINGS);
++			i++, j++)
++		{
++			bus->ring_sh[i].ring_state_w = h2d_w_idx_ptr;
++			bus->ring_sh[i].ring_state_r = h2d_r_idx_ptr;
++
++			/* update mem block */
++			h2d_w_idx_ptr = h2d_w_idx_ptr + bus->rw_index_sz;
++			h2d_r_idx_ptr = h2d_r_idx_ptr + bus->rw_index_sz;
++
++			DHD_INFO(("FLOW Rings h2d w/r : idx %d write %x read %x \n", i,
++				bus->ring_sh[i].ring_state_w,
++				bus->ring_sh[i].ring_state_r));
++		}
++	}
++} /* dhd_fillup_ring_sharedptr_info */
++
++/**
++ * Initialize bus module: prepare for communication with the dongle. Called after downloading
++ * firmware into the dongle.
++ */
++int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	int  ret = 0;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	ASSERT(bus->dhd);
++	if (!bus->dhd)
++		return 0;
++
++	/* Make sure we're talking to the core. */
++	bus->reg = si_setcore(bus->sih, PCIE2_CORE_ID, 0);
++	ASSERT(bus->reg != NULL);
++
++	/* before opening up bus for data transfer, check if shared are is intact */
++	ret = dhdpcie_readshared(bus);
++	if (ret < 0) {
++		DHD_ERROR(("%s :Shared area read failed \n", __FUNCTION__));
++		return ret;
++	}
++
++	/* Make sure we're talking to the core. */
++	bus->reg = si_setcore(bus->sih, PCIE2_CORE_ID, 0);
++	ASSERT(bus->reg != NULL);
++
++	/* Set bus state according to enable result */
++	dhdp->busstate = DHD_BUS_DATA;
++
++	if (!dhd_download_fw_on_driverload)
++		dhd_dpc_enable(bus->dhd);
++
++	/* Enable the interrupt after device is up */
++	dhdpcie_bus_intr_enable(bus);
++
++	/* bcmsdh_intr_unmask(bus->sdh); */
++
++	return ret;
++}
++
++static void
++dhdpcie_init_shared_addr(dhd_bus_t *bus)
++{
++	uint32 addr = 0;
++	uint32 val = 0;
++	addr = bus->dongle_ram_base + bus->ramsize - 4;
++	dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val));
++}
++
++
++bool
++dhdpcie_chipmatch(uint16 vendor, uint16 device)
++{
++	if (vendor != PCI_VENDOR_ID_BROADCOM) {
++		DHD_ERROR(("%s: Unsupported vendor %x device %x\n", __FUNCTION__,
++			vendor, device));
++		return (-ENODEV);
++	}
++
++	if ((device == BCM4350_D11AC_ID) || (device == BCM4350_D11AC2G_ID) ||
++		(device == BCM4350_D11AC5G_ID) || (device == BCM4350_CHIP_ID) ||
++		(device == BCM43569_CHIP_ID))
++		return 0;
++
++	if ((device == BCM4354_D11AC_ID) || (device == BCM4354_D11AC2G_ID) ||
++		(device == BCM4354_D11AC5G_ID) || (device == BCM4354_CHIP_ID))
++		return 0;
++
++	if ((device == BCM4356_D11AC_ID) || (device == BCM4356_D11AC2G_ID) ||
++		(device == BCM4356_D11AC5G_ID) || (device == BCM4356_CHIP_ID))
++		return 0;
++
++	if ((device == BCM4345_D11AC_ID) || (device == BCM4345_D11AC2G_ID) ||
++		(device == BCM4345_D11AC5G_ID) || BCM4345_CHIP(device))
++		return 0;
++
++	if ((device == BCM4335_D11AC_ID) || (device == BCM4335_D11AC2G_ID) ||
++		(device == BCM4335_D11AC5G_ID) || (device == BCM4335_CHIP_ID))
++		return 0;
++
++	if ((device == BCM43602_D11AC_ID) || (device == BCM43602_D11AC2G_ID) ||
++		(device == BCM43602_D11AC5G_ID) || (device == BCM43602_CHIP_ID))
++		return 0;
++
++	if ((device == BCM43569_D11AC_ID) || (device == BCM43569_D11AC2G_ID) ||
++		(device == BCM43569_D11AC5G_ID) || (device == BCM43569_CHIP_ID))
++		return 0;
++
++	if ((device == BCM4358_D11AC_ID) || (device == BCM4358_D11AC2G_ID) ||
++		(device == BCM4358_D11AC5G_ID))
++		return 0;
++
++	if ((device == BCM4349_D11AC_ID) || (device == BCM4349_D11AC2G_ID) ||
++		(device == BCM4349_D11AC5G_ID) || (device == BCM4349_CHIP_ID))
++		return 0;
++
++	if ((device == BCM4355_D11AC_ID) || (device == BCM4355_D11AC2G_ID) ||
++		(device == BCM4355_D11AC5G_ID) || (device == BCM4355_CHIP_ID))
++		return 0;
++
++	if ((device == BCM4359_D11AC_ID) || (device == BCM4359_D11AC2G_ID) ||
++		(device == BCM4359_D11AC5G_ID))
++		return 0;
++
++	if ((device == BCM43596_D11AC_ID) || (device == BCM43596_D11AC2G_ID) ||
++		(device == BCM43596_D11AC5G_ID))
++		return 0;
++
++
++	if ((device == BCM4365_D11AC_ID) || (device == BCM4365_D11AC2G_ID) ||
++		(device == BCM4365_D11AC5G_ID) || (device == BCM4365_CHIP_ID))
++		return 0;
++
++	if ((device == BCM4366_D11AC_ID) || (device == BCM4366_D11AC2G_ID) ||
++		(device == BCM4366_D11AC5G_ID) || (device == BCM4366_CHIP_ID))
++		return 0;
++
++	DHD_ERROR(("%s: Unsupported vendor %x device %x\n", __FUNCTION__, vendor, device));
++	return (-ENODEV);
++} /* dhdpcie_chipmatch */
++
++/**
++ * Name:  dhdpcie_cc_nvmshadow
++ *
++ * Description:
++ * A shadow of OTP/SPROM exists in ChipCommon Region
++ * betw. 0x800 and 0xBFF (Backplane Addr. 0x1800_0800 and 0x1800_0BFF).
++ * Strapping option (SPROM vs. OTP), presence of OTP/SPROM and its size
++ * can also be read from ChipCommon Registers.
++ */
++static int
++dhdpcie_cc_nvmshadow(dhd_bus_t *bus, struct bcmstrbuf *b)
++{
++	uint16 dump_offset = 0;
++	uint32 dump_size = 0, otp_size = 0, sprom_size = 0;
++
++	/* Table for 65nm OTP Size (in bits) */
++	int  otp_size_65nm[8] = {0, 2048, 4096, 8192, 4096, 6144, 512, 1024};
++
++	volatile uint16 *nvm_shadow;
++
++	uint cur_coreid;
++	uint chipc_corerev;
++	chipcregs_t *chipcregs;
++
++	/* Save the current core */
++	cur_coreid = si_coreid(bus->sih);
++	/* Switch to ChipC */
++	chipcregs = (chipcregs_t *)si_setcore(bus->sih, CC_CORE_ID, 0);
++	ASSERT(chipcregs != NULL);
++
++	chipc_corerev = si_corerev(bus->sih);
++
++	/* Check ChipcommonCore Rev */
++	if (chipc_corerev < 44) {
++		DHD_ERROR(("%s: ChipcommonCore Rev %d < 44\n", __FUNCTION__, chipc_corerev));
++		return BCME_UNSUPPORTED;
++	}
++
++	/* Check ChipID */
++	if (((uint16)bus->sih->chip != BCM4350_CHIP_ID) && !BCM4345_CHIP((uint16)bus->sih->chip)) {
++		DHD_ERROR(("%s: cc_nvmdump cmd. supported for 4350/4345 only\n",
++			__FUNCTION__));
++		return BCME_UNSUPPORTED;
++	}
++
++	/* Check if SRC_PRESENT in SpromCtrl(0x190 in ChipCommon Regs) is set */
++	if (chipcregs->sromcontrol & SRC_PRESENT) {
++		/* SPROM Size: 1Kbits (0x0), 4Kbits (0x1), 16Kbits(0x2) */
++		sprom_size = (1 << (2 * ((chipcregs->sromcontrol & SRC_SIZE_MASK)
++					>> SRC_SIZE_SHIFT))) * 1024;
++		bcm_bprintf(b, "\nSPROM Present (Size %d bits)\n", sprom_size);
++	}
++
++	if (chipcregs->sromcontrol & SRC_OTPPRESENT) {
++		bcm_bprintf(b, "\nOTP Present");
++
++		if (((chipcregs->otplayout & OTPL_WRAP_TYPE_MASK) >> OTPL_WRAP_TYPE_SHIFT)
++			== OTPL_WRAP_TYPE_40NM) {
++			/* 40nm OTP: Size = (OtpSize + 1) * 1024 bits */
++			otp_size =  (((chipcregs->capabilities & CC_CAP_OTPSIZE)
++				        >> CC_CAP_OTPSIZE_SHIFT) + 1) * 1024;
++			bcm_bprintf(b, "(Size %d bits)\n", otp_size);
++		} else {
++			/* This part is untested since newer chips have 40nm OTP */
++			otp_size = otp_size_65nm[(chipcregs->capabilities & CC_CAP_OTPSIZE)
++				        >> CC_CAP_OTPSIZE_SHIFT];
++			bcm_bprintf(b, "(Size %d bits)\n", otp_size);
++			DHD_INFO(("%s: 65nm/130nm OTP Size not tested. \n",
++				__FUNCTION__));
++		}
++	}
++
++	if (((chipcregs->sromcontrol & SRC_PRESENT) == 0) &&
++		((chipcregs->capabilities & CC_CAP_OTPSIZE) == 0)) {
++		DHD_ERROR(("%s: SPROM and OTP could not be found \n",
++			__FUNCTION__));
++		return BCME_NOTFOUND;
++	}
++
++	/* Check the strapping option in SpromCtrl: Set = OTP otherwise SPROM */
++	if ((chipcregs->sromcontrol & SRC_OTPSEL) &&
++		(chipcregs->sromcontrol & SRC_OTPPRESENT)) {
++
++		bcm_bprintf(b, "OTP Strap selected.\n"
++		               "\nOTP Shadow in ChipCommon:\n");
++
++		dump_size = otp_size / 16 ; /* 16bit words */
++
++	} else if (((chipcregs->sromcontrol & SRC_OTPSEL) == 0) &&
++		(chipcregs->sromcontrol & SRC_PRESENT)) {
++
++		bcm_bprintf(b, "SPROM Strap selected\n"
++				"\nSPROM Shadow in ChipCommon:\n");
++
++		/* If SPROM > 8K only 8Kbits is mapped to ChipCommon (0x800 - 0xBFF) */
++		/* dump_size in 16bit words */
++		dump_size = sprom_size > 8 ? (8 * 1024) / 16 : sprom_size / 16;
++	} else {
++		DHD_ERROR(("%s: NVM Shadow does not exist in ChipCommon\n",
++			__FUNCTION__));
++		return BCME_NOTFOUND;
++	}
++
++	if (bus->regs == NULL) {
++		DHD_ERROR(("ChipCommon Regs. not initialized\n"));
++		return BCME_NOTREADY;
++	} else {
++	    bcm_bprintf(b, "\n OffSet:");
++
++	    /* Point to the SPROM/OTP shadow in ChipCommon */
++	    nvm_shadow = chipcregs->sromotp;
++
++	   /*
++	    * Read 16 bits / iteration.
++	    * dump_size & dump_offset in 16-bit words
++	    */
++	    while (dump_offset < dump_size) {
++		if (dump_offset % 2 == 0)
++			/* Print the offset in the shadow space in Bytes */
++			bcm_bprintf(b, "\n 0x%04x", dump_offset * 2);
++
++		bcm_bprintf(b, "\t0x%04x", *(nvm_shadow + dump_offset));
++		dump_offset += 0x1;
++	    }
++	}
++
++	/* Switch back to the original core */
++	si_setcore(bus->sih, cur_coreid, 0);
++
++	return BCME_OK;
++} /* dhdpcie_cc_nvmshadow */
++
++/** Flow rings are dynamically created and destroyed */
++void dhd_bus_clean_flow_ring(dhd_bus_t *bus, void *node)
++{
++	void *pkt;
++	flow_queue_t *queue;
++	flow_ring_node_t *flow_ring_node = (flow_ring_node_t *)node;
++	unsigned long flags;
++
++	queue = &flow_ring_node->queue;
++
++#ifdef DHDTCPACK_SUPPRESS
++	/* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt,
++	 * when there is a newly coming packet from network stack.
++	 */
++	dhd_tcpack_info_tbl_clean(bus->dhd);
++#endif /* DHDTCPACK_SUPPRESS */
++
++	/* clean up BUS level info */
++	DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++
++	/* Flush all pending packets in the queue, if any */
++	while ((pkt = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) {
++		PKTFREE(bus->dhd->osh, pkt, TRUE);
++	}
++	ASSERT(DHD_FLOW_QUEUE_EMPTY(queue));
++
++	/* Reinitialise flowring's queue */
++	dhd_flow_queue_reinit(bus->dhd, queue, FLOW_RING_QUEUE_THRESHOLD);
++
++	flow_ring_node->status = FLOW_RING_STATUS_CLOSED;
++	flow_ring_node->active = FALSE;
++
++	DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++
++	DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags);
++	dll_delete(&flow_ring_node->list);
++	DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags);
++
++	/* Release the flowring object back into the pool */
++	dhd_prot_flowrings_pool_release(bus->dhd,
++		flow_ring_node->flowid, flow_ring_node->prot_info);
++
++	/* Free the flowid back to the flowid allocator */
++	dhd_flowid_free(bus->dhd, flow_ring_node->flow_info.ifindex,
++		flow_ring_node->flowid);
++}
++
++/**
++ * Allocate a Flow ring buffer,
++ * Init Ring buffer, send Msg to device about flow ring creation
++*/
++int
++dhd_bus_flow_ring_create_request(dhd_bus_t *bus, void *arg)
++{
++	flow_ring_node_t *flow_ring_node = (flow_ring_node_t *)arg;
++
++	DHD_INFO(("%s :Flow create\n", __FUNCTION__));
++
++	/* Send Msg to device about flow ring creation */
++	if (dhd_prot_flow_ring_create(bus->dhd, flow_ring_node) != BCME_OK)
++		return BCME_NOMEM;
++
++	return BCME_OK;
++}
++
++/** Handle response from dongle on a 'flow ring create' request */
++void
++dhd_bus_flow_ring_create_response(dhd_bus_t *bus, uint16 flowid, int32 status)
++{
++	flow_ring_node_t *flow_ring_node;
++	unsigned long flags;
++
++	DHD_INFO(("%s :Flow Response %d \n", __FUNCTION__, flowid));
++
++	flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid);
++	ASSERT(flow_ring_node->flowid == flowid);
++
++	if (status != BCME_OK) {
++		DHD_ERROR(("%s Flow create Response failure error status = %d \n",
++		     __FUNCTION__, status));
++		/* Call Flow clean up */
++		dhd_bus_clean_flow_ring(bus, flow_ring_node);
++		return;
++	}
++
++	DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++	flow_ring_node->status = FLOW_RING_STATUS_OPEN;
++	DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++
++	/* Now add the Flow ring node into the active list
++	 * Note that this code to add the newly created node to the active
++	 * list was living in dhd_flowid_lookup. But note that after
++	 * adding the node to the active list the contents of node is being
++	 * filled in dhd_prot_flow_ring_create.
++	 * If there is a D2H interrupt after the node gets added to the
++	 * active list and before the node gets populated with values
++	 * from the Bottom half dhd_update_txflowrings would be called.
++	 * which will then try to walk through the active flow ring list,
++	 * pickup the nodes and operate on them. Now note that since
++	 * the function dhd_prot_flow_ring_create is not finished yet
++	 * the contents of flow_ring_node can still be NULL leading to
++	 * crashes. Hence the flow_ring_node should be added to the
++	 * active list only after its truely created, which is after
++	 * receiving the create response message from the Host.
++	 */
++
++	DHD_FLOWRING_LIST_LOCK(bus->dhd->flowring_list_lock, flags);
++	dll_prepend(&bus->const_flowring, &flow_ring_node->list);
++	DHD_FLOWRING_LIST_UNLOCK(bus->dhd->flowring_list_lock, flags);
++
++	dhd_bus_schedule_queue(bus, flowid, FALSE); /* from queue to flowring */
++
++	return;
++}
++
++int
++dhd_bus_flow_ring_delete_request(dhd_bus_t *bus, void *arg)
++{
++	void * pkt;
++	flow_queue_t *queue;
++	flow_ring_node_t *flow_ring_node;
++	unsigned long flags;
++
++	DHD_INFO(("%s :Flow Delete\n", __FUNCTION__));
++
++	flow_ring_node = (flow_ring_node_t *)arg;
++
++	DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++	if (flow_ring_node->status == FLOW_RING_STATUS_DELETE_PENDING) {
++		DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++		DHD_ERROR(("%s :Delete Pending Flow %d\n",
++			__FUNCTION__, flow_ring_node->flowid));
++		return BCME_ERROR;
++	}
++	flow_ring_node->status = FLOW_RING_STATUS_DELETE_PENDING;
++
++	queue = &flow_ring_node->queue; /* queue associated with flow ring */
++
++#ifdef DHDTCPACK_SUPPRESS
++	/* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt,
++	 * when there is a newly coming packet from network stack.
++	 */
++	dhd_tcpack_info_tbl_clean(bus->dhd);
++#endif /* DHDTCPACK_SUPPRESS */
++	/* Flush all pending packets in the queue, if any */
++	while ((pkt = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) {
++		PKTFREE(bus->dhd->osh, pkt, TRUE);
++	}
++	ASSERT(DHD_FLOW_QUEUE_EMPTY(queue));
++
++	DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++
++	/* Send Msg to device about flow ring deletion */
++	dhd_prot_flow_ring_delete(bus->dhd, flow_ring_node);
++
++	return BCME_OK;
++}
++
++void
++dhd_bus_flow_ring_delete_response(dhd_bus_t *bus, uint16 flowid, uint32 status)
++{
++	flow_ring_node_t *flow_ring_node;
++
++	DHD_INFO(("%s :Flow Delete Response %d \n", __FUNCTION__, flowid));
++
++	flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid);
++	ASSERT(flow_ring_node->flowid == flowid);
++
++	if (status != BCME_OK) {
++		DHD_ERROR(("%s Flow Delete Response failure error status = %d \n",
++		    __FUNCTION__, status));
++		return;
++	}
++	/* Call Flow clean up */
++	dhd_bus_clean_flow_ring(bus, flow_ring_node);
++
++	return;
++
++}
++
++/** This function is not called. Obsolete ? */
++int dhd_bus_flow_ring_flush_request(dhd_bus_t *bus, void *arg)
++{
++	void *pkt;
++	flow_queue_t *queue;
++	flow_ring_node_t *flow_ring_node;
++	unsigned long flags;
++
++	DHD_INFO(("%s :Flow Delete\n", __FUNCTION__));
++
++	flow_ring_node = (flow_ring_node_t *)arg;
++	queue = &flow_ring_node->queue; /* queue associated with flow ring */
++
++	DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
++
++#ifdef DHDTCPACK_SUPPRESS
++	/* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt,
++	 * when there is a newly coming packet from network stack.
++	 */
++	dhd_tcpack_info_tbl_clean(bus->dhd);
++#endif /* DHDTCPACK_SUPPRESS */
++
++	/* Flush all pending packets in the queue, if any */
++	while ((pkt = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) {
++		PKTFREE(bus->dhd->osh, pkt, TRUE);
++	}
++	ASSERT(DHD_FLOW_QUEUE_EMPTY(queue));
++
++	DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
++
++	/* Send Msg to device about flow ring flush */
++	dhd_prot_flow_ring_flush(bus->dhd, flow_ring_node);
++
++	flow_ring_node->status = FLOW_RING_STATUS_FLUSH_PENDING;
++	return BCME_OK;
++}
++
++void
++dhd_bus_flow_ring_flush_response(dhd_bus_t *bus, uint16 flowid, uint32 status)
++{
++	flow_ring_node_t *flow_ring_node;
++
++	if (status != BCME_OK) {
++		DHD_ERROR(("%s Flow flush Response failure error status = %d \n",
++		    __FUNCTION__, status));
++		return;
++	}
++
++	flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid);
++	ASSERT(flow_ring_node->flowid == flowid);
++
++	flow_ring_node->status = FLOW_RING_STATUS_OPEN;
++	return;
++}
++
++uint32
++dhd_bus_max_h2d_queues(struct dhd_bus *bus)
++{
++	return bus->max_sub_queues;
++}
++
++/* To be symmetric with SDIO */
++void
++dhd_bus_pktq_flush(dhd_pub_t *dhdp)
++{
++	return;
++}
++
++int
++dhdpcie_bus_clock_start(struct dhd_bus *bus)
++{
++	return dhdpcie_start_host_pcieclock(bus);
++}
++
++int
++dhdpcie_bus_clock_stop(struct dhd_bus *bus)
++{
++	return dhdpcie_stop_host_pcieclock(bus);
++}
++
++int
++dhdpcie_bus_disable_device(struct dhd_bus *bus)
++{
++	return dhdpcie_disable_device(bus);
++}
++
++int
++dhdpcie_bus_enable_device(struct dhd_bus *bus)
++{
++	return dhdpcie_enable_device(bus);
++}
++
++int
++dhdpcie_bus_alloc_resource(struct dhd_bus *bus)
++{
++	return dhdpcie_alloc_resource(bus);
++}
++
++void
++dhdpcie_bus_free_resource(struct dhd_bus *bus)
++{
++	dhdpcie_free_resource(bus);
++}
++
++int
++dhd_bus_request_irq(struct dhd_bus *bus)
++{
++	return dhdpcie_bus_request_irq(bus);
++}
++
++bool
++dhdpcie_bus_dongle_attach(struct dhd_bus *bus)
++{
++	return dhdpcie_dongle_attach(bus);
++}
++
++int
++dhd_bus_release_dongle(struct dhd_bus *bus)
++{
++	bool dongle_isolation;
++	osl_t *osh;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus) {
++		osh = bus->osh;
++		ASSERT(osh);
++
++		if (bus->dhd) {
++			dongle_isolation = bus->dhd->dongle_isolation;
++			dhdpcie_bus_release_dongle(bus, osh, dongle_isolation, TRUE);
++		}
++	}
++
++	return 0;
++}
++
++#ifdef BCMPCIE_OOB_HOST_WAKE
++int
++dhd_bus_oob_intr_register(dhd_pub_t *dhdp)
++{
++	return dhdpcie_oob_intr_register(dhdp->bus);
++}
++
++void
++dhd_bus_oob_intr_unregister(dhd_pub_t *dhdp)
++{
++	dhdpcie_oob_intr_unregister(dhdp->bus);
++}
++
++void
++dhd_bus_oob_intr_set(dhd_pub_t *dhdp, bool enable)
++{
++	dhdpcie_oob_intr_set(dhdp->bus, enable);
++}
++#endif /* BCMPCIE_OOB_HOST_WAKE */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_pcie.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_pcie.h
+new file mode 100644
+index 000000000..33703c695
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_pcie.h
+@@ -0,0 +1,266 @@
++/*
++ * Linux DHD Bus Module for PCIE
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_pcie.h 606080 2015-12-14 09:31:57Z $
++ */
++
++
++#ifndef dhd_pcie_h
++#define dhd_pcie_h
++
++#include <bcmpcie.h>
++#include <hnd_cons.h>
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#ifdef CONFIG_ARCH_MSM
++#if defined(CONFIG_ARCH_MSM8994) || defined(CONFIG_ARCH_MSM8996)
++#include <linux/msm_pcie.h>
++#else
++#include <mach/msm_pcie.h>
++#endif /* CONFIG_ARCH_MSM8994 */
++#endif /* CONFIG_ARCH_MSM */
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++
++/* defines */
++
++#define PCMSGBUF_HDRLEN 0
++#define DONGLE_REG_MAP_SIZE (32 * 1024)
++#define DONGLE_TCM_MAP_SIZE (4096 * 1024)
++#define DONGLE_MIN_MEMSIZE (128 *1024)
++#ifdef DHD_DEBUG
++#define DHD_PCIE_SUCCESS 0
++#define DHD_PCIE_FAILURE 1
++#endif /* DHD_DEBUG */
++#define	REMAP_ENAB(bus)			((bus)->remap)
++#define	REMAP_ISADDR(bus, a)		(((a) >= ((bus)->orig_ramsize)) && ((a) < ((bus)->ramsize)))
++
++/*
++ * Router with 4366 can have 128 stations and 16 BSS,
++ * hence (128 stations x 4 access categories for ucast) + 16 bc/mc flowrings
++ */
++#define MAX_DHD_TX_FLOWS	320
++
++/* user defined data structures */
++/* Device console log buffer state */
++#define CONSOLE_LINE_MAX	192
++#define CONSOLE_BUFFER_MAX	(8 * 1024)
++
++#ifndef MAX_CNTL_D3ACK_TIMEOUT
++#define MAX_CNTL_D3ACK_TIMEOUT 2
++#endif /* MAX_CNTL_D3ACK_TIMEOUT */
++
++#ifdef DHD_DEBUG
++
++typedef struct dhd_console {
++	 uint		count;	/* Poll interval msec counter */
++	 uint		log_addr;		 /* Log struct address (fixed) */
++	 hnd_log_t	 log;			 /* Log struct (host copy) */
++	 uint		 bufsize;		 /* Size of log buffer */
++	 uint8		 *buf;			 /* Log buffer (host copy) */
++	 uint		 last;			 /* Last buffer read index */
++} dhd_console_t;
++#endif /* DHD_DEBUG */
++typedef struct ring_sh_info {
++	uint32 ring_mem_addr;
++	uint32 ring_state_w;
++	uint32 ring_state_r;
++} ring_sh_info_t;
++
++typedef struct dhd_bus {
++	dhd_pub_t	*dhd;
++	struct pci_dev  *dev;		/* pci device handle */
++	dll_t       const_flowring; /* constructed list of tx flowring queues */
++
++	si_t		*sih;			/* Handle for SI calls */
++	char		*vars;			/* Variables (from CIS and/or other) */
++	uint		varsz;			/* Size of variables buffer */
++	uint32		sbaddr;			/* Current SB window pointer (-1, invalid) */
++	sbpcieregs_t	*reg;			/* Registers for PCIE core */
++
++	uint		armrev;			/* CPU core revision */
++	uint		ramrev;			/* SOCRAM core revision */
++	uint32		ramsize;		/* Size of RAM in SOCRAM (bytes) */
++	uint32		orig_ramsize;		/* Size of RAM in SOCRAM (bytes) */
++	uint32		srmemsize;		/* Size of SRMEM */
++
++	uint32		bus;			/* gSPI or SDIO bus */
++	uint32		intstatus;		/* Intstatus bits (events) pending */
++	bool		dpc_sched;		/* Indicates DPC schedule (intrpt rcvd) */
++	bool		fcstate;		/* State of dongle flow-control */
++
++	uint16		cl_devid;		/* cached devid for dhdsdio_probe_attach() */
++	char		*fw_path;		/* module_param: path to firmware image */
++	char		*nv_path;		/* module_param: path to nvram vars file */
++#ifdef CACHE_FW_IMAGES
++	int			processed_nvram_params_len;	/* Modified len of NVRAM info */
++#endif
++
++#if defined(CUSTOMER_HW_31_2)
++	char		*nvram_params;		/* user specified nvram params. */
++	int			nvram_params_len;
++#endif 
++
++	struct pktq	txq;			/* Queue length used for flow-control */
++
++	bool		intr;			/* Use interrupts */
++	bool		ipend;			/* Device interrupt is pending */
++	bool		intdis;			/* Interrupts disabled by isr */
++	uint		intrcount;		/* Count of device interrupt callbacks */
++	uint		lastintrs;		/* Count as of last watchdog timer */
++
++#ifdef DHD_DEBUG
++	dhd_console_t	console;		/* Console output polling support */
++	uint		console_addr;		/* Console address from shared struct */
++#endif /* DHD_DEBUG */
++
++	bool		alp_only;		/* Don't use HT clock (ALP only) */
++
++	bool		remap;		/* Contiguous 1MB RAM: 512K socram + 512K devram
++					 * Available with socram rev 16
++					 * Remap region not DMA-able
++					 */
++	uint32		resetinstr;
++	uint32		dongle_ram_base;
++
++	ulong		shared_addr;
++	pciedev_shared_t	*pcie_sh;
++	bool bus_flowctrl;
++	uint32		dma_rxoffset;
++	volatile char	*regs;		/* pci device memory va */
++	volatile char	*tcm;		/* pci device memory va */
++	osl_t		*osh;
++	uint32		nvram_csm;	/* Nvram checksum */
++	uint16		pollrate;
++	uint16  polltick;
++
++	uint32  *pcie_mb_intr_addr;
++	void    *pcie_mb_intr_osh;
++	bool	sleep_allowed;
++
++	/* version 3 shared struct related info start */
++	ring_sh_info_t	ring_sh[BCMPCIE_COMMON_MSGRINGS + MAX_DHD_TX_FLOWS];
++	uint8	h2d_ring_count;
++	uint8	d2h_ring_count;
++	uint32  ringmem_ptr;
++	uint32  ring_state_ptr;
++
++	uint32 d2h_dma_scratch_buffer_mem_addr;
++
++	uint32 h2d_mb_data_ptr_addr;
++	uint32 d2h_mb_data_ptr_addr;
++	/* version 3 shared struct related info end */
++
++	uint32 def_intmask;
++	bool	ltrsleep_on_unload;
++	uint	wait_for_d3_ack;
++	uint32 max_sub_queues;
++	uint32	rw_index_sz;
++	bool	db1_for_mb;
++	bool	suspended;
++
++	dhd_timeout_t doorbell_timer;
++	bool	device_wake_state;
++#ifdef PCIE_OOB
++	bool	oob_enabled;
++#endif /* PCIE_OOB */
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#ifdef CONFIG_ARCH_MSM
++	struct msm_pcie_register_event pcie_event;
++	uint8 islinkdown;
++#endif /* CONFIG_ARCH_MSM */
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++	uint32 d3_inform_cnt;
++	uint32 d0_inform_cnt;
++	uint32 d0_inform_in_use_cnt;
++	uint8 force_suspend;
++} dhd_bus_t;
++
++/* function declarations */
++
++extern uint32* dhdpcie_bus_reg_map(osl_t *osh, ulong addr, int size);
++extern int dhdpcie_bus_register(void);
++extern void dhdpcie_bus_unregister(void);
++extern bool dhdpcie_chipmatch(uint16 vendor, uint16 device);
++
++extern struct dhd_bus* dhdpcie_bus_attach(osl_t *osh,
++	volatile char *regs, volatile char *tcm, void *pci_dev);
++extern uint32 dhdpcie_bus_cfg_read_dword(struct dhd_bus *bus, uint32 addr, uint32 size);
++extern void dhdpcie_bus_cfg_write_dword(struct dhd_bus *bus, uint32 addr, uint32 size, uint32 data);
++extern void dhdpcie_bus_intr_enable(struct dhd_bus *bus);
++extern void dhdpcie_bus_intr_disable(struct dhd_bus *bus);
++extern void dhdpcie_bus_release(struct dhd_bus *bus);
++extern int32 dhdpcie_bus_isr(struct dhd_bus *bus);
++extern void dhdpcie_free_irq(dhd_bus_t *bus);
++extern void dhdpcie_bus_ringbell_fast(struct dhd_bus *bus, uint32 value);
++extern int dhdpcie_bus_suspend(struct  dhd_bus *bus, bool state);
++extern int dhdpcie_pci_suspend_resume(struct  dhd_bus *bus, bool state);
++extern bool dhdpcie_tcm_valid(dhd_bus_t *bus);
++#ifndef BCMPCIE_OOB_HOST_WAKE
++extern void dhdpcie_pme_active(osl_t *osh, bool enable);
++#endif /* !BCMPCIE_OOB_HOST_WAKE */
++extern bool dhdpcie_pme_cap(osl_t *osh);
++extern uint32 dhdpcie_lcreg(osl_t *osh, uint32 mask, uint32 val);
++extern uint8 dhdpcie_clkreq(osl_t *osh, uint32 mask, uint32 val);
++extern int dhdpcie_start_host_pcieclock(dhd_bus_t *bus);
++extern int dhdpcie_stop_host_pcieclock(dhd_bus_t *bus);
++extern int dhdpcie_disable_device(dhd_bus_t *bus);
++extern int dhdpcie_enable_device(dhd_bus_t *bus);
++extern int dhdpcie_alloc_resource(dhd_bus_t *bus);
++extern void dhdpcie_free_resource(dhd_bus_t *bus);
++extern int dhdpcie_bus_request_irq(struct dhd_bus *bus);
++#ifdef BCMPCIE_OOB_HOST_WAKE
++extern int dhdpcie_oob_intr_register(dhd_bus_t *bus);
++extern void dhdpcie_oob_intr_unregister(dhd_bus_t *bus);
++extern void dhdpcie_oob_intr_set(dhd_bus_t *bus, bool enable);
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++#ifdef PCIE_OOB
++extern void dhd_oob_set_bt_reg_on(struct dhd_bus *bus, bool val);
++extern int dhd_oob_get_bt_reg_on(struct dhd_bus *bus);
++#endif /* PCIE_OOB */
++
++#ifdef USE_EXYNOS_PCIE_RC_PMPATCH
++#if defined(CONFIG_MACH_UNIVERSAL5433)
++#define SAMSUNG_PCIE_DEVICE_ID 0xa5e3
++#define SAMSUNG_PCIE_CH_NUM
++#elif defined(CONFIG_MACH_UNIVERSAL7420)
++#define SAMSUNG_PCIE_DEVICE_ID 0xa575
++#define SAMSUNG_PCIE_CH_NUM 1
++#elif defined(CONFIG_SOC_EXYNOS8890)
++#define SAMSUNG_PCIE_DEVICE_ID 0xa544
++#define SAMSUNG_PCIE_CH_NUM 0
++#else
++#error "Not supported platform"
++#endif
++#ifdef CONFIG_MACH_UNIVERSAL5433
++extern int exynos_pcie_pm_suspend(void);
++extern int exynos_pcie_pm_resume(void);
++#else
++extern int exynos_pcie_pm_suspend(int ch_num);
++extern int exynos_pcie_pm_resume(int ch_num);
++#endif /* CONFIG_MACH_UNIVERSAL5433 */
++#endif /* USE_EXYNOS_PCIE_RC_PMPATCH */
++
++extern int dhd_buzzz_dump_dngl(dhd_bus_t *bus);
++#endif /* dhd_pcie_h */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_pcie_linux.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_pcie_linux.c
+new file mode 100644
+index 000000000..7c8ef19a6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_pcie_linux.c
+@@ -0,0 +1,1287 @@
++/*
++ * Linux DHD Bus Module for PCIE
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_pcie_linux.c 608659 2015-12-29 01:18:33Z $
++ */
++
++
++/* include files */
++#include <typedefs.h>
++#include <bcmutils.h>
++#include <bcmdevs.h>
++#include <siutils.h>
++#include <hndsoc.h>
++#include <hndpmu.h>
++#include <sbchipc.h>
++#if defined(DHD_DEBUG)
++#include <hnd_armtrap.h>
++#include <hnd_cons.h>
++#endif /* defined(DHD_DEBUG) */
++#include <dngl_stats.h>
++#include <pcie_core.h>
++#include <dhd.h>
++#include <dhd_bus.h>
++#include <dhd_proto.h>
++#include <dhd_dbg.h>
++#include <dhdioctl.h>
++#include <bcmmsgbuf.h>
++#include <pcicfg.h>
++#include <dhd_pcie.h>
++#include <dhd_linux.h>
++#ifdef CONFIG_ARCH_MSM
++#if defined(CONFIG_ARCH_MSM8994) || defined(CONFIG_ARCH_MSM8996)
++#include <linux/msm_pcie.h>
++#else
++#include <mach/msm_pcie.h>
++#endif /* CONFIG_ARCH_MSM8994 */
++#endif /* CONFIG_ARCH_MSM */
++
++#define PCI_CFG_RETRY 		10
++#define OS_HANDLE_MAGIC		0x1234abcd	/* Magic # to recognize osh */
++#define BCM_MEM_FILENAME_LEN 	24		/* Mem. filename length */
++
++#define OSL_PKTTAG_CLEAR(p) \
++do { \
++	struct sk_buff *s = (struct sk_buff *)(p); \
++	ASSERT(OSL_PKTTAG_SZ == 32); \
++	*(uint32 *)(&s->cb[0]) = 0; *(uint32 *)(&s->cb[4]) = 0; \
++	*(uint32 *)(&s->cb[8]) = 0; *(uint32 *)(&s->cb[12]) = 0; \
++	*(uint32 *)(&s->cb[16]) = 0; *(uint32 *)(&s->cb[20]) = 0; \
++	*(uint32 *)(&s->cb[24]) = 0; *(uint32 *)(&s->cb[28]) = 0; \
++} while (0)
++
++
++/* user defined data structures  */
++
++typedef struct dhd_pc_res {
++	uint32 bar0_size;
++	void* bar0_addr;
++	uint32 bar1_size;
++	void* bar1_addr;
++} pci_config_res, *pPci_config_res;
++
++typedef bool (*dhdpcie_cb_fn_t)(void *);
++
++typedef struct dhdpcie_info
++{
++	dhd_bus_t	*bus;
++	osl_t 			*osh;
++	struct pci_dev  *dev;		/* pci device handle */
++	volatile char 	*regs;		/* pci device memory va */
++	volatile char 	*tcm;		/* pci device memory va */
++	uint32			tcm_size;	/* pci device memory size */
++	struct pcos_info *pcos_info;
++	uint16		last_intrstatus;	/* to cache intrstatus */
++	int	irq;
++	char pciname[32];
++	struct pci_saved_state* default_state;
++	struct pci_saved_state* state;
++#ifdef BCMPCIE_OOB_HOST_WAKE
++	void *os_cxt;			/* Pointer to per-OS private data */
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++} dhdpcie_info_t;
++
++
++struct pcos_info {
++	dhdpcie_info_t *pc;
++	spinlock_t lock;
++	wait_queue_head_t intr_wait_queue;
++	struct timer_list tuning_timer;
++	int tuning_timer_exp;
++	atomic_t timer_enab;
++	struct tasklet_struct tuning_tasklet;
++};
++
++#ifdef BCMPCIE_OOB_HOST_WAKE
++typedef struct dhdpcie_os_info {
++	int			oob_irq_num;	/* valid when hardware or software oob in use */
++	unsigned long		oob_irq_flags;	/* valid when hardware or software oob in use */
++	bool			oob_irq_registered;
++	bool			oob_irq_enabled;
++	bool			oob_irq_wake_enabled;
++	spinlock_t		oob_irq_spinlock;
++	void			*dev;		/* handle to the underlying device */
++} dhdpcie_os_info_t;
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++
++/* function declarations */
++static int __devinit
++dhdpcie_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
++static void __devexit
++dhdpcie_pci_remove(struct pci_dev *pdev);
++static int dhdpcie_init(struct pci_dev *pdev);
++static irqreturn_t dhdpcie_isr(int irq, void *arg);
++/* OS Routine functions for PCI suspend/resume */
++
++static int dhdpcie_pci_suspend(struct pci_dev *dev, pm_message_t state);
++static int dhdpcie_set_suspend_resume(struct pci_dev *dev, bool state);
++static int dhdpcie_pci_resume(struct pci_dev *dev);
++static int dhdpcie_resume_dev(struct pci_dev *dev);
++static int dhdpcie_suspend_dev(struct pci_dev *dev);
++static struct pci_device_id dhdpcie_pci_devid[] __devinitdata = {
++	{ vendor: 0x14e4,
++	device: PCI_ANY_ID,
++	subvendor: PCI_ANY_ID,
++	subdevice: PCI_ANY_ID,
++	class: PCI_CLASS_NETWORK_OTHER << 8,
++	class_mask: 0xffff00,
++	driver_data: 0,
++	},
++	{ 0, }
++};
++MODULE_DEVICE_TABLE(pci, dhdpcie_pci_devid);
++
++static struct pci_driver dhdpcie_driver = {
++	node:		{},
++	name:		"pcieh",
++	id_table:	dhdpcie_pci_devid,
++	probe:		dhdpcie_pci_probe,
++	remove:		dhdpcie_pci_remove,
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
++	save_state:	NULL,
++#endif
++	suspend:	dhdpcie_pci_suspend,
++	resume:		dhdpcie_pci_resume,
++};
++
++int dhdpcie_init_succeeded = FALSE;
++
++static int dhdpcie_set_suspend_resume(struct pci_dev *pdev, bool state)
++{
++	int ret = 0;
++	dhdpcie_info_t *pch = pci_get_drvdata(pdev);
++	dhd_bus_t *bus = NULL;
++
++	if (pch) {
++		bus = pch->bus;
++	}
++
++	/* When firmware is not loaded do the PCI bus */
++	/* suspend/resume only */
++	if (bus && (bus->dhd->busstate == DHD_BUS_DOWN) &&
++		!bus->dhd->dongle_reset) {
++		ret = dhdpcie_pci_suspend_resume(bus, state);
++		return ret;
++	}
++
++	if (bus && ((bus->dhd->busstate == DHD_BUS_SUSPEND)||
++		(bus->dhd->busstate == DHD_BUS_DATA)) &&
++		(bus->suspended != state)) {
++		ret = dhdpcie_bus_suspend(bus, state);
++	}
++	return ret;
++}
++
++static int dhdpcie_pci_suspend(struct pci_dev * pdev, pm_message_t state)
++{
++	BCM_REFERENCE(state);
++	return dhdpcie_set_suspend_resume(pdev, TRUE);
++}
++
++static int dhdpcie_pci_resume(struct pci_dev *pdev)
++{
++	return dhdpcie_set_suspend_resume(pdev, FALSE);
++}
++
++static int dhdpcie_suspend_dev(struct pci_dev *dev)
++{
++	int ret;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	dhdpcie_info_t *pch = pci_get_drvdata(dev);
++#endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++	DHD_TRACE_HW4(("%s: Enter\n", __FUNCTION__));
++	pci_save_state(dev);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	pch->state = pci_store_saved_state(dev);
++#endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++	pci_enable_wake(dev, PCI_D0, TRUE);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
++	if (pci_is_enabled(dev))
++#endif
++		pci_disable_device(dev);
++
++	ret = pci_set_power_state(dev, PCI_D3hot);
++	if (ret) {
++		DHD_ERROR(("%s: pci_set_power_state error %d\n",
++			__FUNCTION__, ret));
++	}
++	disable_irq(dev->irq);
++	return ret;
++}
++
++static int dhdpcie_resume_dev(struct pci_dev *dev)
++{
++	int err = 0;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	dhdpcie_info_t *pch = pci_get_drvdata(dev);
++	pci_load_and_free_saved_state(dev, &pch->state);
++#endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++	DHD_TRACE_HW4(("%s: Enter\n", __FUNCTION__));
++	pci_restore_state(dev);
++	err = pci_enable_device(dev);
++	if (err) {
++		printf("%s:pci_enable_device error %d \n", __FUNCTION__, err);
++		goto out;
++	}
++	pci_set_master(dev);
++	err = pci_set_power_state(dev, PCI_D0);
++	if (err) {
++		printf("%s:pci_set_power_state error %d \n", __FUNCTION__, err);
++		goto out;
++	}
++
++out:
++	enable_irq(dev->irq);
++	return err;
++}
++
++
++int dhdpcie_pci_suspend_resume(dhd_bus_t *bus, bool state)
++{
++	int rc;
++
++	struct pci_dev *dev = bus->dev;
++#ifdef USE_EXYNOS_PCIE_RC_PMPATCH
++	struct pci_dev *rc_pci_dev;
++#endif /* USE_EXYNOS_PCIE_RC_PMPATCH */
++
++	if (state) {
++#ifndef BCMPCIE_OOB_HOST_WAKE
++		dhdpcie_pme_active(bus->osh, state);
++#endif /* !BCMPCIE_OOB_HOST_WAKE */
++		rc = dhdpcie_suspend_dev(dev);
++#ifdef USE_EXYNOS_PCIE_RC_PMPATCH
++		if (!rc) {
++			rc_pci_dev = pci_get_device(0x144d, SAMSUNG_PCIE_DEVICE_ID, NULL);
++			if (rc_pci_dev) {
++				pci_save_state(rc_pci_dev);
++			}
++			exynos_pcie_pm_suspend(SAMSUNG_PCIE_CH_NUM);
++		}
++#endif /* USE_EXYNOS_PCIE_RC_PMPATCH */
++	} else {
++#ifdef USE_EXYNOS_PCIE_RC_PMPATCH
++		exynos_pcie_pm_resume(SAMSUNG_PCIE_CH_NUM);
++#endif /* USE_EXYNOS_PCIE_RC_PMPATCH */
++
++		rc = dhdpcie_resume_dev(dev);
++#ifndef BCMPCIE_OOB_HOST_WAKE
++		dhdpcie_pme_active(bus->osh, state);
++#endif /* !BCMPCIE_OOB_HOST_WAKE */
++	}
++	return rc;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
++static int dhdpcie_device_scan(struct device *dev, void *data)
++{
++	struct pci_dev *pcidev;
++	int *cnt = data;
++
++	pcidev = container_of(dev, struct pci_dev, dev);
++	if (pcidev->vendor != 0x14e4)
++		return 0;
++
++	DHD_INFO(("Found Broadcom PCI device 0x%04x\n", pcidev->device));
++	*cnt += 1;
++	if (pcidev->driver && strcmp(pcidev->driver->name, dhdpcie_driver.name))
++		DHD_ERROR(("Broadcom PCI Device 0x%04x has allocated with driver %s\n",
++			pcidev->device, pcidev->driver->name));
++
++	return 0;
++}
++#endif /* LINUX_VERSION >= 2.6.0 */
++
++int
++dhdpcie_bus_register(void)
++{
++	int error = 0;
++
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
++	if (!(error = pci_module_init(&dhdpcie_driver)))
++		return 0;
++
++	DHD_ERROR(("%s: pci_module_init failed 0x%x\n", __FUNCTION__, error));
++#else
++	if (!(error = pci_register_driver(&dhdpcie_driver))) {
++		bus_for_each_dev(dhdpcie_driver.driver.bus, NULL, &error, dhdpcie_device_scan);
++		if (!error) {
++			DHD_ERROR(("No Broadcom PCI device enumerated!\n"));
++		} else if (!dhdpcie_init_succeeded) {
++			DHD_ERROR(("%s: dhdpcie initialize failed.\n", __FUNCTION__));
++		} else {
++			return 0;
++		}
++
++		pci_unregister_driver(&dhdpcie_driver);
++		error = BCME_ERROR;
++	}
++#endif /* LINUX_VERSION < 2.6.0 */
++
++	return error;
++}
++
++
++void
++dhdpcie_bus_unregister(void)
++{
++	pci_unregister_driver(&dhdpcie_driver);
++}
++
++int __devinit
++dhdpcie_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
++{
++	int retry = 0;
++
++
++	if (dhdpcie_chipmatch (pdev->vendor, pdev->device)) {
++		DHD_ERROR(("%s: chipmatch failed!!\n", __FUNCTION__));
++			return -ENODEV;
++	}
++	printf("PCI_PROBE:  bus %X, slot %X,vendor %X, device %X"
++		"(good PCI location)\n", pdev->bus->number,
++		PCI_SLOT(pdev->devfn), pdev->vendor, pdev->device);
++
++
++	do {
++		if (dhdpcie_init(pdev) == 0)
++			break;
++		DHD_ERROR(("%s: PCIe Enumeration failed\n", __FUNCTION__));
++	} while (retry-- >= 0);
++
++	if (retry < 0)
++		return -ENODEV;
++
++#ifdef BCMPCIE_DISABLE_ASYNC_SUSPEND
++	/* disable async suspend */
++	device_disable_async_suspend(&pdev->dev);
++#endif /* BCMPCIE_DISABLE_ASYNC_SUSPEND */
++
++	DHD_TRACE(("%s: PCIe Enumeration done!!\n", __FUNCTION__));
++	return 0;
++}
++
++int
++dhdpcie_detach(dhdpcie_info_t *pch)
++{
++	if (pch) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++		if (!dhd_download_fw_on_driverload) {
++			pci_load_and_free_saved_state(pch->dev, &pch->default_state);
++		}
++#endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++		MFREE(pch->osh, pch, sizeof(dhdpcie_info_t));
++	}
++	return 0;
++}
++
++
++void __devexit
++dhdpcie_pci_remove(struct pci_dev *pdev)
++{
++	osl_t *osh = NULL;
++	dhdpcie_info_t *pch = NULL;
++	dhd_bus_t *bus = NULL;
++
++	DHD_TRACE(("%s Enter\n", __FUNCTION__));
++	pch = pci_get_drvdata(pdev);
++	bus = pch->bus;
++	osh = pch->osh;
++
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#ifdef CONFIG_ARCH_MSM
++	if (bus) {
++		msm_pcie_deregister_event(&bus->pcie_event);
++	}
++#endif /* CONFIG_ARCH_MSM */
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++	dhdpcie_bus_release(bus);
++	if (pci_is_enabled(pdev))
++		pci_disable_device(pdev);
++#ifdef BCMPCIE_OOB_HOST_WAKE
++	/* pcie os info detach */
++	MFREE(osh, pch->os_cxt, sizeof(dhdpcie_os_info_t));
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++	/* pcie info detach */
++	dhdpcie_detach(pch);
++	/* osl detach */
++	osl_detach(osh);
++
++	dhdpcie_init_succeeded = FALSE;
++
++	DHD_TRACE(("%s Exit\n", __FUNCTION__));
++
++	return;
++}
++
++/* Free Linux irq */
++int
++dhdpcie_request_irq(dhdpcie_info_t *dhdpcie_info)
++{
++	dhd_bus_t *bus = dhdpcie_info->bus;
++	struct pci_dev *pdev = dhdpcie_info->bus->dev;
++
++	snprintf(dhdpcie_info->pciname, sizeof(dhdpcie_info->pciname),
++	    "dhdpcie:%s", pci_name(pdev));
++	if (request_irq(pdev->irq, dhdpcie_isr, IRQF_SHARED,
++	                dhdpcie_info->pciname, bus) < 0) {
++			DHD_ERROR(("%s: request_irq() failed\n", __FUNCTION__));
++			return -1;
++	}
++
++	DHD_TRACE(("%s %s\n", __FUNCTION__, dhdpcie_info->pciname));
++
++
++	return 0; /* SUCCESS */
++}
++
++#ifdef CONFIG_PHYS_ADDR_T_64BIT
++#define PRINTF_RESOURCE	"0x%016llx"
++#else
++#define PRINTF_RESOURCE	"0x%08x"
++#endif
++
++/*
++
++Name:  osl_pci_get_resource
++
++Parametrs:
++
++1: struct pci_dev *pdev   -- pci device structure
++2: pci_res                       -- structure containing pci configuration space values
++
++
++Return value:
++
++int   - Status (TRUE or FALSE)
++
++Description:
++Access PCI configuration space, retrieve  PCI allocated resources , updates in resource structure.
++
++ */
++int dhdpcie_get_resource(dhdpcie_info_t *dhdpcie_info)
++{
++	phys_addr_t  bar0_addr, bar1_addr;
++	ulong bar1_size;
++	struct pci_dev *pdev = NULL;
++	pdev = dhdpcie_info->dev;
++	do {
++		if (pci_enable_device(pdev)) {
++			printf("%s: Cannot enable PCI device\n", __FUNCTION__);
++			break;
++		}
++		pci_set_master(pdev);
++		bar0_addr = pci_resource_start(pdev, 0);	/* Bar-0 mapped address */
++		bar1_addr = pci_resource_start(pdev, 2);	/* Bar-1 mapped address */
++
++		/* read Bar-1 mapped memory range */
++		bar1_size = pci_resource_len(pdev, 2);
++
++		if ((bar1_size == 0) || (bar1_addr == 0)) {
++			printf("%s: BAR1 Not enabled for this device  size(%ld),"
++				" addr(0x"PRINTF_RESOURCE")\n",
++				__FUNCTION__, bar1_size, bar1_addr);
++			goto err;
++		}
++
++		dhdpcie_info->regs = (volatile char *) REG_MAP(bar0_addr, DONGLE_REG_MAP_SIZE);
++		dhdpcie_info->tcm_size =
++			(bar1_size > DONGLE_TCM_MAP_SIZE) ? bar1_size : DONGLE_TCM_MAP_SIZE;
++		dhdpcie_info->tcm = (volatile char *) REG_MAP(bar1_addr, dhdpcie_info->tcm_size);
++
++		if (!dhdpcie_info->regs || !dhdpcie_info->tcm) {
++			DHD_ERROR(("%s:ioremap() failed\n", __FUNCTION__));
++			break;
++		}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++		if (!dhd_download_fw_on_driverload) {
++			/* Backup PCIe configuration so as to use Wi-Fi on/off process
++			 * in case of built in driver
++			 */
++			pci_save_state(pdev);
++			dhdpcie_info->default_state = pci_store_saved_state(pdev);
++
++			if (dhdpcie_info->default_state == NULL) {
++				DHD_ERROR(("%s pci_store_saved_state returns NULL\n",
++					__FUNCTION__));
++				REG_UNMAP(dhdpcie_info->regs);
++				REG_UNMAP(dhdpcie_info->tcm);
++				pci_disable_device(pdev);
++				break;
++			}
++		}
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++
++		DHD_TRACE(("%s:Phys addr : reg space = %p base addr 0x"PRINTF_RESOURCE" \n",
++			__FUNCTION__, dhdpcie_info->regs, bar0_addr));
++		DHD_TRACE(("%s:Phys addr : tcm_space = %p base addr 0x"PRINTF_RESOURCE" \n",
++			__FUNCTION__, dhdpcie_info->tcm, bar1_addr));
++
++		return 0; /* SUCCESS  */
++	} while (0);
++err:
++	return -1;  /* FAILURE */
++}
++
++int dhdpcie_scan_resource(dhdpcie_info_t *dhdpcie_info)
++{
++
++	DHD_TRACE(("%s: ENTER\n", __FUNCTION__));
++
++	do {
++		/* define it here only!! */
++		if (dhdpcie_get_resource (dhdpcie_info)) {
++			DHD_ERROR(("%s: Failed to get PCI resources\n", __FUNCTION__));
++			break;
++		}
++		DHD_TRACE(("%s:Exit - SUCCESS \n",
++			__FUNCTION__));
++
++		return 0; /* SUCCESS */
++
++	} while (0);
++
++	DHD_TRACE(("%s:Exit - FAILURE \n", __FUNCTION__));
++
++	return -1; /* FAILURE */
++
++}
++
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#ifdef CONFIG_ARCH_MSM
++void dhdpcie_linkdown_cb(struct msm_pcie_notify *noti)
++{
++	struct pci_dev *pdev = (struct pci_dev *)noti->user;
++	dhdpcie_info_t *pch = NULL;
++
++	if (pdev) {
++		pch = pci_get_drvdata(pdev);
++		if (pch) {
++			dhd_bus_t *bus = pch->bus;
++			if (bus) {
++				dhd_pub_t *dhd = bus->dhd;
++				if (dhd) {
++					DHD_ERROR(("%s: Event HANG send up "
++						"due to PCIe linkdown\n",
++						__FUNCTION__));
++					bus->islinkdown = 1;
++					DHD_OS_WAKE_LOCK(dhd);
++					dhd_os_check_hang(dhd, 0, -ETIMEDOUT);
++				}
++			}
++		}
++	}
++
++}
++#endif /* CONFIG_ARCH_MSM */
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++
++int dhdpcie_init(struct pci_dev *pdev)
++{
++
++	osl_t 				*osh = NULL;
++	dhd_bus_t 			*bus = NULL;
++	dhdpcie_info_t		*dhdpcie_info =  NULL;
++	wifi_adapter_info_t	*adapter = NULL;
++#ifdef BCMPCIE_OOB_HOST_WAKE
++	dhdpcie_os_info_t	*dhdpcie_osinfo = NULL;
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++
++	do {
++		/* osl attach */
++		if (!(osh = osl_attach(pdev, PCI_BUS, FALSE))) {
++			DHD_ERROR(("%s: osl_attach failed\n", __FUNCTION__));
++			break;
++		}
++
++		/* initialize static buffer */
++		adapter = dhd_wifi_platform_get_adapter(PCI_BUS, pdev->bus->number,
++			PCI_SLOT(pdev->devfn));
++		if (adapter != NULL)
++			DHD_ERROR(("%s: found adapter info '%s'\n", __FUNCTION__, adapter->name));
++		else
++			DHD_ERROR(("%s: can't find adapter info for this chip\n", __FUNCTION__));
++		osl_static_mem_init(osh, adapter);
++
++		/* Set ACP coherence flag */
++		if (OSL_ACP_WAR_ENAB() || OSL_ARCH_IS_COHERENT())
++			osl_flag_set(osh, OSL_ACP_COHERENCE);
++
++		/*  allocate linux spcific pcie structure here */
++		if (!(dhdpcie_info = MALLOC(osh, sizeof(dhdpcie_info_t)))) {
++			DHD_ERROR(("%s: MALLOC of dhd_bus_t failed\n", __FUNCTION__));
++			break;
++		}
++		bzero(dhdpcie_info, sizeof(dhdpcie_info_t));
++		dhdpcie_info->osh = osh;
++		dhdpcie_info->dev = pdev;
++
++#ifdef BCMPCIE_OOB_HOST_WAKE
++		/* allocate OS speicific structure */
++		dhdpcie_osinfo = MALLOC(osh, sizeof(dhdpcie_os_info_t));
++		if (dhdpcie_osinfo == NULL) {
++			DHD_ERROR(("%s: MALLOC of dhdpcie_os_info_t failed\n",
++				__FUNCTION__));
++			break;
++		}
++		bzero(dhdpcie_osinfo, sizeof(dhdpcie_os_info_t));
++		dhdpcie_info->os_cxt = (void *)dhdpcie_osinfo;
++
++		/* Initialize host wake IRQ */
++		spin_lock_init(&dhdpcie_osinfo->oob_irq_spinlock);
++		/* Get customer specific host wake IRQ parametres: IRQ number as IRQ type */
++		dhdpcie_osinfo->oob_irq_num = wifi_platform_get_irq_number(adapter,
++			&dhdpcie_osinfo->oob_irq_flags);
++		if (dhdpcie_osinfo->oob_irq_num < 0) {
++			DHD_ERROR(("%s: Host OOB irq is not defined\n", __FUNCTION__));
++		}
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++
++		/* Find the PCI resources, verify the  */
++		/* vendor and device ID, map BAR regions and irq,  update in structures */
++		if (dhdpcie_scan_resource(dhdpcie_info)) {
++			DHD_ERROR(("%s: dhd_Scan_PCI_Res failed\n", __FUNCTION__));
++
++			break;
++		}
++
++		/* Bus initialization */
++		bus = dhdpcie_bus_attach(osh, dhdpcie_info->regs, dhdpcie_info->tcm, pdev);
++		if (!bus) {
++			DHD_ERROR(("%s:dhdpcie_bus_attach() failed\n", __FUNCTION__));
++			break;
++		}
++
++		dhdpcie_info->bus = bus;
++
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++#ifdef CONFIG_ARCH_MSM
++		bus->pcie_event.events = MSM_PCIE_EVENT_LINKDOWN;
++		bus->pcie_event.user = pdev;
++		bus->pcie_event.mode = MSM_PCIE_TRIGGER_CALLBACK;
++		bus->pcie_event.callback = dhdpcie_linkdown_cb;
++		bus->pcie_event.options = MSM_PCIE_CONFIG_NO_RECOVERY;
++		msm_pcie_register_event(&bus->pcie_event);
++		bus->islinkdown = 0;
++#endif /* CONFIG_ARCH_MSM */
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++
++		if (bus->intr) {
++			/* Register interrupt callback, but mask it (not operational yet). */
++			DHD_INTR(("%s: Registering and masking interrupts\n", __FUNCTION__));
++			dhdpcie_bus_intr_disable(bus);
++
++			if (dhdpcie_request_irq(dhdpcie_info)) {
++				DHD_ERROR(("%s: request_irq() failed\n", __FUNCTION__));
++				break;
++			}
++		} else {
++			bus->pollrate = 1;
++			DHD_INFO(("%s: PCIe interrupt function is NOT registered "
++				"due to polling mode\n", __FUNCTION__));
++		}
++
++#if defined(BCM_REQUEST_FW)
++		if (dhd_bus_download_firmware(bus, osh, NULL, NULL) < 0) {
++		DHD_ERROR(("%s: failed to download firmware\n", __FUNCTION__));
++		}
++		bus->nv_path = NULL;
++		bus->fw_path = NULL;
++#endif /* BCM_REQUEST_FW */
++
++		/* set private data for pci_dev */
++		pci_set_drvdata(pdev, dhdpcie_info);
++
++		if (dhd_download_fw_on_driverload) {
++			if (dhd_bus_start(bus->dhd)) {
++				DHD_ERROR(("%s: dhd_bud_start() failed\n", __FUNCTION__));
++				if (!allow_delay_fwdl)
++					break;
++			}
++		} else {
++			/* Set ramdom MAC address during boot time */
++			get_random_bytes(&bus->dhd->mac.octet[3], 3);
++			/* Adding BRCM OUI */
++			bus->dhd->mac.octet[0] = 0;
++			bus->dhd->mac.octet[1] = 0x90;
++			bus->dhd->mac.octet[2] = 0x4C;
++		}
++
++		/* Attach to the OS network interface */
++		DHD_TRACE(("%s(): Calling dhd_register_if() \n", __FUNCTION__));
++		if (dhd_register_if(bus->dhd, 0, TRUE)) {
++			DHD_ERROR(("%s(): ERROR.. dhd_register_if() failed\n", __FUNCTION__));
++			break;
++		}
++
++		dhdpcie_init_succeeded = TRUE;
++
++		DHD_TRACE(("%s:Exit - SUCCESS \n", __FUNCTION__));
++		return 0;  /* return  SUCCESS  */
++
++	} while (0);
++	/* reverse the initialization in order in case of error */
++
++	if (bus)
++		dhdpcie_bus_release(bus);
++
++#ifdef BCMPCIE_OOB_HOST_WAKE
++	if (dhdpcie_osinfo) {
++		MFREE(osh, dhdpcie_osinfo, sizeof(dhdpcie_os_info_t));
++	}
++#endif /* BCMPCIE_OOB_HOST_WAKE */
++
++	if (dhdpcie_info)
++		dhdpcie_detach(dhdpcie_info);
++	pci_disable_device(pdev);
++	if (osh)
++		osl_detach(osh);
++
++	dhdpcie_init_succeeded = FALSE;
++
++	DHD_TRACE(("%s:Exit - FAILURE \n", __FUNCTION__));
++
++	return -1; /* return FAILURE  */
++}
++
++/* Free Linux irq */
++void
++dhdpcie_free_irq(dhd_bus_t *bus)
++{
++	struct pci_dev *pdev = NULL;
++
++	DHD_TRACE(("%s: freeing up the IRQ\n", __FUNCTION__));
++	if (bus) {
++		pdev = bus->dev;
++		free_irq(pdev->irq, bus);
++	}
++	DHD_TRACE(("%s: Exit\n", __FUNCTION__));
++	return;
++}
++
++/*
++
++Name:  dhdpcie_isr
++
++Parametrs:
++
++1: IN int irq   -- interrupt vector
++2: IN void *arg      -- handle to private data structure
++
++Return value:
++
++Status (TRUE or FALSE)
++
++Description:
++Interrupt Service routine checks for the status register,
++disable interrupt and queue DPC if mail box interrupts are raised.
++*/
++
++
++irqreturn_t
++dhdpcie_isr(int irq, void *arg)
++{
++	dhd_bus_t *bus = (dhd_bus_t*)arg;
++	if (dhdpcie_bus_isr(bus))
++		return TRUE;
++	else
++		return FALSE;
++}
++
++int
++dhdpcie_start_host_pcieclock(dhd_bus_t *bus)
++{
++	int ret = 0;
++#ifdef CONFIG_ARCH_MSM
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++	int options = 0;
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++#endif /* CONFIG_ARCH_MSM */
++	DHD_TRACE(("%s Enter:\n", __FUNCTION__));
++
++	if (bus == NULL) {
++		return BCME_ERROR;
++	}
++
++	if (bus->dev == NULL) {
++		return BCME_ERROR;
++	}
++
++#ifdef CONFIG_ARCH_MSM
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++	if (bus->islinkdown) {
++		options = MSM_PCIE_CONFIG_NO_CFG_RESTORE;
++	}
++	ret = msm_pcie_pm_control(MSM_PCIE_RESUME, bus->dev->bus->number,
++		bus->dev, NULL, options);
++	if (bus->islinkdown && !ret) {
++		msm_pcie_recover_config(bus->dev);
++		if (bus->dhd) {
++			DHD_OS_WAKE_UNLOCK(bus->dhd);
++		}
++	}
++#else
++	ret = msm_pcie_pm_control(MSM_PCIE_RESUME, bus->dev->bus->number,
++		bus->dev, NULL, 0);
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++	if (ret) {
++		DHD_ERROR(("%s Failed to bring up PCIe link\n", __FUNCTION__));
++		goto done;
++	}
++
++done:
++#endif /* CONFIG_ARCH_MSM */
++	DHD_TRACE(("%s Exit:\n", __FUNCTION__));
++	return ret;
++}
++
++int
++dhdpcie_stop_host_pcieclock(dhd_bus_t *bus)
++{
++	int ret = 0;
++#ifdef CONFIG_ARCH_MSM
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++	int options = 0;
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++#endif /* CONFIG_ARCH_MSM */
++
++	DHD_TRACE(("%s Enter:\n", __FUNCTION__));
++
++	if (bus == NULL) {
++		return BCME_ERROR;
++	}
++
++	if (bus->dev == NULL) {
++		return BCME_ERROR;
++	}
++
++#ifdef CONFIG_ARCH_MSM
++#ifdef SUPPORT_LINKDOWN_RECOVERY
++	if (bus->islinkdown) {
++		options = MSM_PCIE_CONFIG_NO_CFG_RESTORE | MSM_PCIE_CONFIG_LINKDOWN;
++	}
++
++	ret = msm_pcie_pm_control(MSM_PCIE_SUSPEND, bus->dev->bus->number,
++		bus->dev, NULL, options);
++#else
++	ret = msm_pcie_pm_control(MSM_PCIE_SUSPEND, bus->dev->bus->number,
++		bus->dev, NULL, 0);
++#endif /* SUPPORT_LINKDOWN_RECOVERY */
++	if (ret) {
++		DHD_ERROR(("Failed to stop PCIe link\n"));
++		goto done;
++	}
++done:
++#endif /* CONFIG_ARCH_MSM */
++	DHD_TRACE(("%s Exit:\n", __FUNCTION__));
++	return ret;
++}
++
++int
++dhdpcie_disable_device(dhd_bus_t *bus)
++{
++	int islinkdown;
++	dhdpcie_info_t *pch;
++
++	DHD_TRACE(("%s Enter:\n", __FUNCTION__));
++
++	if (bus == NULL) {
++		return BCME_ERROR;
++	}
++
++	if (bus->dev == NULL) {
++		return BCME_ERROR;
++	}
++
++	pch = pci_get_drvdata(bus->dev);
++	if (pch == NULL) {
++		return BCME_ERROR;
++	}
++#if defined(SUPPORT_LINKDOWN_RECOVERY) && defined(CONFIG_ARCH_MSM)
++	islinkdown = bus->islinkdown;
++#else
++	islinkdown = 0;
++#endif /* SUPPORT_LINKDOWN_RECOVERY && CONFIG_ARCH_MSM */
++
++	/* Backup PCIe configuration so as to use Wi-Fi on/off process
++	 * in case of built in driver
++	 */
++	if (!islinkdown) {
++		pci_save_state(bus->dev);
++		pch->default_state = pci_store_saved_state(bus->dev);
++
++		if (pch->default_state == NULL) {
++			DHD_ERROR(("%s pci_store_saved_state returns NULL\n", __FUNCTION__));
++		}
++	}
++
++	pci_disable_device(bus->dev);
++
++	return 0;
++}
++
++int
++dhdpcie_enable_device(dhd_bus_t *bus)
++{
++	int ret = BCME_ERROR;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	dhdpcie_info_t *pch;
++	int islinkdown;
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++
++	DHD_TRACE(("%s Enter:\n", __FUNCTION__));
++
++	if (bus == NULL) {
++		return BCME_ERROR;
++	}
++
++	if (bus->dev == NULL) {
++		return BCME_ERROR;
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	pch = pci_get_drvdata(bus->dev);
++	if (pch == NULL) {
++		return BCME_ERROR;
++	}
++
++#if defined(CONFIG_ARCH_MSM) && defined(SUPPORT_LINKDOWN_RECOVERY)
++	islinkdown = bus->islinkdown;
++#else
++	islinkdown = 0;
++#endif /* CONFIG_ARCH_MSM && SUPPORT_LINKDOWN_RECOVERY */
++
++	if (!islinkdown) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
++		/* Updated with pci_load_and_free_saved_state to compatible
++		 * with kernel 3.14 or higher
++		 */
++		pci_load_and_free_saved_state(bus->dev, &pch->default_state);
++#else
++		pci_load_saved_state(bus->dev, pch->default_state);
++#endif /* CONFIG_ARCH_MSM */
++
++		pci_restore_state(bus->dev);
++	}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) */
++
++	ret = pci_enable_device(bus->dev);
++	if (ret) {
++		pci_disable_device(bus->dev);
++	} else {
++		pci_set_master(bus->dev);
++#if defined(CONFIG_ARCH_MSM) && defined(SUPPORT_LINKDOWN_RECOVERY)
++		bus->islinkdown = 0;
++#endif /* CONFIG_ARCH_MSM && SUPPORT_LINKDOWN_RECOVERY */
++	}
++
++	return ret;
++}
++
++int
++dhdpcie_alloc_resource(dhd_bus_t *bus)
++{
++	dhdpcie_info_t *dhdpcie_info;
++	phys_addr_t bar0_addr, bar1_addr;
++	ulong bar1_size;
++
++	do {
++		if (bus == NULL) {
++			DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
++			break;
++		}
++
++		if (bus->dev == NULL) {
++			DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
++			break;
++		}
++
++		dhdpcie_info = pci_get_drvdata(bus->dev);
++		if (dhdpcie_info == NULL) {
++			DHD_ERROR(("%s: dhdpcie_info is NULL\n", __FUNCTION__));
++			break;
++		}
++
++		bar0_addr = pci_resource_start(bus->dev, 0);	/* Bar-0 mapped address */
++		bar1_addr = pci_resource_start(bus->dev, 2);	/* Bar-1 mapped address */
++
++		/* read Bar-1 mapped memory range */
++		bar1_size = pci_resource_len(bus->dev, 2);
++
++		if ((bar1_size == 0) || (bar1_addr == 0)) {
++			printf("%s: BAR1 Not enabled for this device size(%ld),"
++				" addr(0x"PRINTF_RESOURCE")\n",
++				__FUNCTION__, bar1_size, bar1_addr);
++			break;
++		}
++
++		dhdpcie_info->regs = (volatile char *) REG_MAP(bar0_addr, DONGLE_REG_MAP_SIZE);
++		if (!dhdpcie_info->regs) {
++			DHD_ERROR(("%s: ioremap() for regs is failed\n", __FUNCTION__));
++			break;
++		}
++
++		bus->regs = dhdpcie_info->regs;
++		dhdpcie_info->tcm_size =
++			(bar1_size > DONGLE_TCM_MAP_SIZE) ? bar1_size : DONGLE_TCM_MAP_SIZE;
++		dhdpcie_info->tcm = (volatile char *) REG_MAP(bar1_addr, dhdpcie_info->tcm_size);
++		if (!dhdpcie_info->tcm) {
++			DHD_ERROR(("%s: ioremap() for regs is failed\n", __FUNCTION__));
++			REG_UNMAP(dhdpcie_info->regs);
++			bus->regs = NULL;
++			break;
++		}
++
++		bus->tcm = dhdpcie_info->tcm;
++
++		DHD_TRACE(("%s:Phys addr : reg space = %p base addr 0x"PRINTF_RESOURCE" \n",
++			__FUNCTION__, dhdpcie_info->regs, bar0_addr));
++		DHD_TRACE(("%s:Phys addr : tcm_space = %p base addr 0x"PRINTF_RESOURCE" \n",
++			__FUNCTION__, dhdpcie_info->tcm, bar1_addr));
++
++		return 0;
++	} while (0);
++
++	return BCME_ERROR;
++}
++
++void
++dhdpcie_free_resource(dhd_bus_t *bus)
++{
++	dhdpcie_info_t *dhdpcie_info;
++
++	if (bus == NULL) {
++		DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (bus->dev == NULL) {
++		DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	dhdpcie_info = pci_get_drvdata(bus->dev);
++	if (dhdpcie_info == NULL) {
++		DHD_ERROR(("%s: dhdpcie_info is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (bus->regs) {
++		REG_UNMAP(dhdpcie_info->regs);
++		bus->regs = NULL;
++	}
++
++	if (bus->tcm) {
++		REG_UNMAP(dhdpcie_info->tcm);
++		bus->tcm = NULL;
++	}
++}
++
++int
++dhdpcie_bus_request_irq(struct dhd_bus *bus)
++{
++	dhdpcie_info_t *dhdpcie_info;
++	int ret = 0;
++
++	if (bus == NULL) {
++		DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	if (bus->dev == NULL) {
++		DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	dhdpcie_info = pci_get_drvdata(bus->dev);
++	if (dhdpcie_info == NULL) {
++		DHD_ERROR(("%s: dhdpcie_info is NULL\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	if (bus->intr) {
++		/* Register interrupt callback, but mask it (not operational yet). */
++		DHD_INTR(("%s: Registering and masking interrupts\n", __FUNCTION__));
++		dhdpcie_bus_intr_disable(bus);
++		ret = dhdpcie_request_irq(dhdpcie_info);
++		if (ret) {
++			DHD_ERROR(("%s: request_irq() failed, ret=%d\n",
++				__FUNCTION__, ret));
++			return ret;
++		}
++	}
++
++	return ret;
++}
++
++#ifdef BCMPCIE_OOB_HOST_WAKE
++void dhdpcie_oob_intr_set(dhd_bus_t *bus, bool enable)
++{
++	unsigned long flags;
++	dhdpcie_info_t *pch;
++	dhdpcie_os_info_t *dhdpcie_osinfo;
++
++	if (bus == NULL) {
++		DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (bus->dev == NULL) {
++		DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	pch = pci_get_drvdata(bus->dev);
++	if (pch == NULL) {
++		DHD_ERROR(("%s: pch is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	dhdpcie_osinfo = (dhdpcie_os_info_t *)pch->os_cxt;
++	spin_lock_irqsave(&dhdpcie_osinfo->oob_irq_spinlock, flags);
++	if ((dhdpcie_osinfo->oob_irq_enabled != enable) &&
++		(dhdpcie_osinfo->oob_irq_num > 0)) {
++		if (enable) {
++			enable_irq(dhdpcie_osinfo->oob_irq_num);
++		} else {
++			disable_irq_nosync(dhdpcie_osinfo->oob_irq_num);
++		}
++		dhdpcie_osinfo->oob_irq_enabled = enable;
++	}
++	spin_unlock_irqrestore(&dhdpcie_osinfo->oob_irq_spinlock, flags);
++}
++
++static irqreturn_t wlan_oob_irq(int irq, void *data)
++{
++	dhd_bus_t *bus;
++	DHD_TRACE(("%s: IRQ Triggered\n", __FUNCTION__));
++	bus = (dhd_bus_t *)data;
++	dhdpcie_oob_intr_set(bus, FALSE);
++	if (bus->dhd->up && bus->suspended) {
++		DHD_OS_OOB_IRQ_WAKE_LOCK_TIMEOUT(bus->dhd, OOB_WAKE_LOCK_TIMEOUT);
++	}
++	return IRQ_HANDLED;
++}
++
++int dhdpcie_oob_intr_register(dhd_bus_t *bus)
++{
++	int err = 0;
++	dhdpcie_info_t *pch;
++	dhdpcie_os_info_t *dhdpcie_osinfo;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++	if (bus == NULL) {
++		DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
++		return -EINVAL;
++	}
++
++	if (bus->dev == NULL) {
++		DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
++		return -EINVAL;
++	}
++
++	pch = pci_get_drvdata(bus->dev);
++	if (pch == NULL) {
++		DHD_ERROR(("%s: pch is NULL\n", __FUNCTION__));
++		return -EINVAL;
++	}
++
++	dhdpcie_osinfo = (dhdpcie_os_info_t *)pch->os_cxt;
++	if (dhdpcie_osinfo->oob_irq_registered) {
++		DHD_ERROR(("%s: irq is already registered\n", __FUNCTION__));
++		return -EBUSY;
++	}
++
++	if (dhdpcie_osinfo->oob_irq_num > 0) {
++		DHD_INFO_HW4(("%s OOB irq=%d flags=%X \n", __FUNCTION__,
++			(int)dhdpcie_osinfo->oob_irq_num,
++			(int)dhdpcie_osinfo->oob_irq_flags));
++		err = request_irq(dhdpcie_osinfo->oob_irq_num, wlan_oob_irq,
++			dhdpcie_osinfo->oob_irq_flags, "dhdpcie_host_wake",
++			bus);
++		if (err) {
++			DHD_ERROR(("%s: request_irq failed with %d\n",
++				__FUNCTION__, err));
++			return err;
++		}
++		err = enable_irq_wake(dhdpcie_osinfo->oob_irq_num);
++		if (!err) {
++			dhdpcie_osinfo->oob_irq_wake_enabled = TRUE;
++		}
++		dhdpcie_osinfo->oob_irq_enabled = TRUE;
++	}
++
++	dhdpcie_osinfo->oob_irq_registered = TRUE;
++
++	return err;
++}
++
++void dhdpcie_oob_intr_unregister(dhd_bus_t *bus)
++{
++	int err = 0;
++	dhdpcie_info_t *pch;
++	dhdpcie_os_info_t *dhdpcie_osinfo;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++	if (bus == NULL) {
++		DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	if (bus->dev == NULL) {
++		DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	pch = pci_get_drvdata(bus->dev);
++	if (pch == NULL) {
++		DHD_ERROR(("%s: pch is NULL\n", __FUNCTION__));
++		return;
++	}
++
++	dhdpcie_osinfo = (dhdpcie_os_info_t *)pch->os_cxt;
++	if (!dhdpcie_osinfo->oob_irq_registered) {
++		DHD_ERROR(("%s: irq is not registered\n", __FUNCTION__));
++		return;
++	}
++	if (dhdpcie_osinfo->oob_irq_num > 0) {
++		if (dhdpcie_osinfo->oob_irq_wake_enabled) {
++			err = disable_irq_wake(dhdpcie_osinfo->oob_irq_num);
++			if (!err) {
++				dhdpcie_osinfo->oob_irq_wake_enabled = FALSE;
++			}
++		}
++		if (dhdpcie_osinfo->oob_irq_enabled) {
++			disable_irq(dhdpcie_osinfo->oob_irq_num);
++			dhdpcie_osinfo->oob_irq_enabled = FALSE;
++		}
++		free_irq(dhdpcie_osinfo->oob_irq_num, bus);
++	}
++	dhdpcie_osinfo->oob_irq_registered = FALSE;
++}
++#endif /* BCMPCIE_OOB_HOST_WAKE */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_pno.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_pno.c
+new file mode 100644
+index 000000000..28a5ca0a6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_pno.c
+@@ -0,0 +1,4111 @@
++/*
++ * Broadcom Dongle Host Driver (DHD)
++ * Prefered Network Offload and Wi-Fi Location Service(WLS) code.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_pno.c 423669 2013-09-18 13:01:55Z yangj$
++ */
++
++#if defined(GSCAN_SUPPORT) && !defined(PNO_SUPPORT)
++#error "GSCAN needs PNO to be enabled!"
++#endif
++
++#ifdef PNO_SUPPORT
++#include <typedefs.h>
++#include <osl.h>
++
++#include <epivers.h>
++#include <bcmutils.h>
++
++#include <bcmendian.h>
++#include <linuxver.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/sort.h>
++#include <dngl_stats.h>
++#include <wlioctl.h>
++
++#include <proto/bcmevent.h>
++#include <dhd.h>
++#include <dhd_pno.h>
++#include <dhd_dbg.h>
++#ifdef GSCAN_SUPPORT
++#include <linux/gcd.h>
++#endif /* GSCAN_SUPPORT */
++
++#ifdef __BIG_ENDIAN
++#include <bcmendian.h>
++#define htod32(i) (bcmswap32(i))
++#define htod16(i) (bcmswap16(i))
++#define dtoh32(i) (bcmswap32(i))
++#define dtoh16(i) (bcmswap16(i))
++#define htodchanspec(i) htod16(i)
++#define dtohchanspec(i) dtoh16(i)
++#else
++#define htod32(i) (i)
++#define htod16(i) (i)
++#define dtoh32(i) (i)
++#define dtoh16(i) (i)
++#define htodchanspec(i) (i)
++#define dtohchanspec(i) (i)
++#endif /* IL_BIGENDINA */
++
++#define NULL_CHECK(p, s, err)  \
++			do { \
++				if (!(p)) { \
++					printf("NULL POINTER (%s) : %s\n", __FUNCTION__, (s)); \
++					err = BCME_ERROR; \
++					return err; \
++				} \
++			} while (0)
++#define PNO_GET_PNOSTATE(dhd) ((dhd_pno_status_info_t *)dhd->pno_state)
++#define PNO_BESTNET_LEN 2048
++#define PNO_ON 1
++#define PNO_OFF 0
++#define CHANNEL_2G_MAX 14
++#define CHANNEL_5G_MAX 165
++#define MAX_NODE_CNT 5
++#define WLS_SUPPORTED(pno_state) (pno_state->wls_supported == TRUE)
++#define TIME_DIFF(timestamp1, timestamp2) (abs((uint32)(timestamp1/1000)  \
++						- (uint32)(timestamp2/1000)))
++#define TIME_DIFF_MS(timestamp1, timestamp2) (abs((uint32)(timestamp1)  \
++						- (uint32)(timestamp2)))
++#define TIMESPEC_TO_US(ts)  (((uint64)(ts).tv_sec * USEC_PER_SEC) + \
++							(ts).tv_nsec / NSEC_PER_USEC)
++
++#define ENTRY_OVERHEAD strlen("bssid=\nssid=\nfreq=\nlevel=\nage=\ndist=\ndistSd=\n====")
++#define TIME_MIN_DIFF 5
++#define EVENT_DATABUF_MAXLEN   (512 - sizeof(bcm_event_t))
++#define EVENT_MAX_NETCNT \
++   ((EVENT_DATABUF_MAXLEN - sizeof(wl_pfn_scanresults_t)) \
++   / sizeof(wl_pfn_net_info_t) + 1)
++#define WL_SCAN_IE_LEN_MAX      2048
++
++static wlc_ssid_ext_t * dhd_pno_get_legacy_pno_ssid(dhd_pub_t *dhd,
++        dhd_pno_status_info_t *pno_state);
++#ifdef GSCAN_SUPPORT
++static wl_pfn_gscan_ch_bucket_cfg_t *
++dhd_pno_gscan_create_channel_list(dhd_pub_t *dhd, dhd_pno_status_info_t *pno_state,
++      uint16 *chan_list, uint32 *num_buckets, uint32 *num_buckets_to_fw);
++#endif /* GSCAN_SUPPORT */
++
++static inline bool
++is_dfs(uint16 channel)
++{
++	if (channel >= 52 && channel <= 64)			/* class 2 */
++		return TRUE;
++	else if (channel >= 100 && channel <= 140)	/* class 4 */
++		return TRUE;
++	else
++		return FALSE;
++}
++int
++dhd_pno_clean(dhd_pub_t *dhd)
++{
++	int pfn = 0;
++	int err;
++	dhd_pno_status_info_t *_pno_state;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	/* Disable PNO */
++	err = dhd_iovar(dhd, 0, "pfn", (char *)&pfn, sizeof(pfn), NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfn(error : %d)\n",
++			__FUNCTION__, err));
++		goto exit;
++	}
++	_pno_state->pno_status = DHD_PNO_DISABLED;
++	err = dhd_iovar(dhd, 0, "pfnclear", NULL, 0, NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfnclear(error : %d)\n",
++			__FUNCTION__, err));
++	}
++exit:
++	return err;
++}
++
++bool
++dhd_is_pno_supported(dhd_pub_t *dhd)
++{
++	dhd_pno_status_info_t *_pno_state;
++
++	if (!dhd || !dhd->pno_state) {
++		DHD_ERROR(("NULL POINTER : %s\n",
++			__FUNCTION__));
++		return FALSE;
++	}
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	return WLS_SUPPORTED(_pno_state);
++}
++
++bool
++dhd_is_legacy_pno_enabled(dhd_pub_t *dhd)
++{
++	dhd_pno_status_info_t *_pno_state;
++
++	if (!dhd || !dhd->pno_state) {
++		DHD_ERROR(("NULL POINTER : %s\n",
++			__FUNCTION__));
++		return FALSE;
++	}
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	return ((_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) != 0);
++}
++
++#ifdef GSCAN_SUPPORT
++static uint64
++convert_fw_rel_time_to_systime(uint32 fw_ts_ms)
++{
++	struct timespec ts;
++
++	get_monotonic_boottime(&ts);
++	return ((uint64)(TIMESPEC_TO_US(ts)) - (uint64)(fw_ts_ms * 1000));
++}
++
++static void
++dhd_pno_idx_to_ssid(struct dhd_pno_gscan_params *gscan_params,
++            dhd_epno_results_t *res, uint32 idx)
++{
++	dhd_epno_params_t *iter, *next;
++
++	if (gscan_params->num_epno_ssid > 0) {
++		list_for_each_entry_safe(iter, next,
++			&gscan_params->epno_ssid_list, list) {
++			if (iter->index == idx) {
++				memcpy(res->ssid, iter->ssid, iter->ssid_len);
++				res->ssid_len = iter->ssid_len;
++				return;
++			}
++		}
++	}
++	/* If we are here then there was no match */
++	res->ssid[0] = '\0';
++	res->ssid_len = 0;
++	return;
++}
++
++/* Cleanup all results */
++static void
++dhd_gscan_clear_all_batch_results(dhd_pub_t *dhd)
++{
++	struct dhd_pno_gscan_params *gscan_params;
++	dhd_pno_status_info_t *_pno_state;
++	gscan_results_cache_t *iter;
++
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	gscan_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS].params_gscan;
++	iter = gscan_params->gscan_batch_cache;
++	/* Mark everything as consumed */
++	while (iter) {
++		iter->tot_consumed = iter->tot_count;
++		iter = iter->next;
++	}
++	dhd_gscan_batch_cache_cleanup(dhd);
++	return;
++}
++
++static int
++_dhd_pno_gscan_cfg(dhd_pub_t *dhd, wl_pfn_gscan_cfg_t *pfncfg_gscan_param, int size)
++{
++	int err = BCME_OK;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	err = dhd_iovar(dhd, 0, "pfn_gscan_cfg", (char *)pfncfg_gscan_param, size, NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfncfg_gscan_param\n", __FUNCTION__));
++		goto exit;
++	}
++exit:
++	return err;
++}
++
++static bool
++is_batch_retrieval_complete(struct dhd_pno_gscan_params *gscan_params)
++{
++	smp_rmb();
++	return (gscan_params->get_batch_flag == GSCAN_BATCH_RETRIEVAL_COMPLETE);
++}
++#endif /* GSCAN_SUPPORT */
++
++static int
++_dhd_pno_suspend(dhd_pub_t *dhd)
++{
++	int err;
++	int suspend = 1;
++	dhd_pno_status_info_t *_pno_state;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	err = dhd_iovar(dhd, 0, "pfn_suspend", (char *)&suspend, sizeof(suspend), NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to suspend pfn(error :%d)\n", __FUNCTION__, err));
++		goto exit;
++
++	}
++	_pno_state->pno_status = DHD_PNO_SUSPEND;
++exit:
++	return err;
++}
++static int
++_dhd_pno_enable(dhd_pub_t *dhd, int enable)
++{
++	int err = BCME_OK;
++	dhd_pno_status_info_t *_pno_state;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	if (enable & 0xfffe) {
++		DHD_ERROR(("%s invalid value\n", __FUNCTION__));
++		err = BCME_BADARG;
++		goto exit;
++	}
++	if (!dhd_support_sta_mode(dhd)) {
++		DHD_ERROR(("PNO is not allowed for non-STA mode"));
++		err = BCME_BADOPTION;
++		goto exit;
++	}
++	if (enable) {
++		if ((_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) &&
++			dhd_is_associated(dhd, NULL, NULL)) {
++			DHD_ERROR(("%s Legacy PNO mode cannot be enabled "
++				"in assoc mode , ignore it\n", __FUNCTION__));
++			err = BCME_BADOPTION;
++			goto exit;
++		}
++	}
++	/* Enable/Disable PNO */
++	err = dhd_iovar(dhd, 0, "pfn", (char *)&enable, sizeof(enable), NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfn_set - %d\n", __FUNCTION__, err));
++		goto exit;
++	}
++	_pno_state->pno_status = (enable)?
++		DHD_PNO_ENABLED : DHD_PNO_DISABLED;
++	if (!enable)
++		_pno_state->pno_mode = DHD_PNO_NONE_MODE;
++
++	DHD_PNO(("%s set pno as %s\n",
++		__FUNCTION__, enable ? "Enable" : "Disable"));
++exit:
++	return err;
++}
++
++static int
++_dhd_pno_set(dhd_pub_t *dhd, const dhd_pno_params_t *pno_params, dhd_pno_mode_t mode)
++{
++	int err = BCME_OK;
++	wl_pfn_param_t pfn_param;
++	dhd_pno_params_t *_params;
++	dhd_pno_status_info_t *_pno_state;
++	bool combined_scan = FALSE;
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++
++	memset(&pfn_param, 0, sizeof(pfn_param));
++
++	/* set pfn parameters */
++	pfn_param.version = htod32(PFN_VERSION);
++	pfn_param.flags = ((PFN_LIST_ORDER << SORT_CRITERIA_BIT) |
++		(ENABLE << IMMEDIATE_SCAN_BIT) | (ENABLE << REPORT_SEPERATELY_BIT));
++	if (mode == DHD_PNO_LEGACY_MODE) {
++		/* check and set extra pno params */
++		if ((pno_params->params_legacy.pno_repeat != 0) ||
++			(pno_params->params_legacy.pno_freq_expo_max != 0)) {
++			pfn_param.flags |= htod16(ENABLE << ENABLE_ADAPTSCAN_BIT);
++			pfn_param.repeat = (uchar) (pno_params->params_legacy.pno_repeat);
++			pfn_param.exp = (uchar) (pno_params->params_legacy.pno_freq_expo_max);
++		}
++		/* set up pno scan fr */
++		if (pno_params->params_legacy.scan_fr != 0)
++			pfn_param.scan_freq = htod32(pno_params->params_legacy.scan_fr);
++		if (_pno_state->pno_mode & DHD_PNO_BATCH_MODE) {
++			DHD_PNO(("will enable combined scan with BATCHIG SCAN MODE\n"));
++			mode |= DHD_PNO_BATCH_MODE;
++			combined_scan = TRUE;
++		} else if (_pno_state->pno_mode & DHD_PNO_HOTLIST_MODE) {
++			DHD_PNO(("will enable combined scan with HOTLIST SCAN MODE\n"));
++			mode |= DHD_PNO_HOTLIST_MODE;
++			combined_scan = TRUE;
++		}
++#ifdef GSCAN_SUPPORT
++		else if (_pno_state->pno_mode & DHD_PNO_GSCAN_MODE) {
++			DHD_PNO(("will enable combined scan with GSCAN SCAN MODE\n"));
++			mode |= DHD_PNO_GSCAN_MODE;
++		}
++#endif /* GSCAN_SUPPORT */
++	}
++	if (mode & (DHD_PNO_BATCH_MODE | DHD_PNO_HOTLIST_MODE)) {
++		/* Scan frequency of 30 sec */
++		pfn_param.scan_freq = htod32(30);
++		/* slow adapt scan is off by default */
++		pfn_param.slow_freq = htod32(0);
++		/* RSSI margin of 30 dBm */
++		pfn_param.rssi_margin = htod16(PNO_RSSI_MARGIN_DBM);
++		/* Network timeout 60 sec */
++		pfn_param.lost_network_timeout = htod32(60);
++		/* best n = 2 by default */
++		pfn_param.bestn = DEFAULT_BESTN;
++		/* mscan m=0 by default, so not record best networks by default */
++		pfn_param.mscan = DEFAULT_MSCAN;
++		/*  default repeat = 10 */
++		pfn_param.repeat = DEFAULT_REPEAT;
++		/* by default, maximum scan interval = 2^2
++		 * scan_freq when adaptive scan is turned on
++		 */
++		pfn_param.exp = DEFAULT_EXP;
++		if (mode == DHD_PNO_BATCH_MODE) {
++			/* In case of BATCH SCAN */
++			if (pno_params->params_batch.bestn)
++				pfn_param.bestn = pno_params->params_batch.bestn;
++			if (pno_params->params_batch.scan_fr)
++				pfn_param.scan_freq = htod32(pno_params->params_batch.scan_fr);
++			if (pno_params->params_batch.mscan)
++				pfn_param.mscan = pno_params->params_batch.mscan;
++			/* enable broadcast scan */
++			pfn_param.flags |= (ENABLE << ENABLE_BD_SCAN_BIT);
++		} else if (mode == DHD_PNO_HOTLIST_MODE) {
++			/* In case of HOTLIST SCAN */
++			if (pno_params->params_hotlist.scan_fr)
++				pfn_param.scan_freq = htod32(pno_params->params_hotlist.scan_fr);
++			pfn_param.bestn = 0;
++			pfn_param.repeat = 0;
++			/* enable broadcast scan */
++			pfn_param.flags |= (ENABLE << ENABLE_BD_SCAN_BIT);
++		}
++		if (combined_scan) {
++			/* Disable Adaptive Scan */
++			pfn_param.flags &= ~(htod16(ENABLE << ENABLE_ADAPTSCAN_BIT));
++			pfn_param.flags |= (ENABLE << ENABLE_BD_SCAN_BIT);
++			pfn_param.repeat = 0;
++			pfn_param.exp = 0;
++			if (_pno_state->pno_mode & DHD_PNO_BATCH_MODE) {
++				/* In case of Legacy PNO + BATCH SCAN */
++				_params = &(_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS]);
++				if (_params->params_batch.bestn)
++					pfn_param.bestn = _params->params_batch.bestn;
++				if (_params->params_batch.scan_fr)
++					pfn_param.scan_freq = htod32(_params->params_batch.scan_fr);
++				if (_params->params_batch.mscan)
++					pfn_param.mscan = _params->params_batch.mscan;
++			} else if (_pno_state->pno_mode & DHD_PNO_HOTLIST_MODE) {
++				/* In case of Legacy PNO + HOTLIST SCAN */
++				_params = &(_pno_state->pno_params_arr[INDEX_OF_HOTLIST_PARAMS]);
++				if (_params->params_hotlist.scan_fr)
++				pfn_param.scan_freq = htod32(_params->params_hotlist.scan_fr);
++				pfn_param.bestn = 0;
++				pfn_param.repeat = 0;
++			}
++		}
++	}
++#ifdef GSCAN_SUPPORT
++	if (mode & DHD_PNO_GSCAN_MODE) {
++		uint32 lost_network_timeout;
++
++		pfn_param.scan_freq = htod32(pno_params->params_gscan.scan_fr);
++		if (pno_params->params_gscan.mscan) {
++			pfn_param.bestn = pno_params->params_gscan.bestn;
++			pfn_param.mscan =  pno_params->params_gscan.mscan;
++			pfn_param.flags |= (ENABLE << ENABLE_BD_SCAN_BIT);
++		}
++		/* RSSI margin of 30 dBm */
++		pfn_param.rssi_margin = htod16(PNO_RSSI_MARGIN_DBM);
++		pfn_param.repeat = 0;
++		pfn_param.exp = 0;
++		pfn_param.slow_freq = 0;
++		pfn_param.flags |= htod16(ENABLE << ENABLE_ADAPTSCAN_BIT);
++
++		if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) {
++			dhd_pno_status_info_t *_pno_state = PNO_GET_PNOSTATE(dhd);
++			dhd_pno_params_t *_params;
++
++			_params = &(_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS]);
++
++			pfn_param.scan_freq = htod32(gcd(pno_params->params_gscan.scan_fr,
++			                 _params->params_legacy.scan_fr));
++
++			if ((_params->params_legacy.pno_repeat != 0) ||
++				(_params->params_legacy.pno_freq_expo_max != 0)) {
++				pfn_param.repeat = (uchar) (_params->params_legacy.pno_repeat);
++				pfn_param.exp = (uchar) (_params->params_legacy.pno_freq_expo_max);
++			}
++		}
++
++		lost_network_timeout = (pno_params->params_gscan.max_ch_bucket_freq *
++		                        pfn_param.scan_freq *
++		                        pno_params->params_gscan.lost_ap_window);
++		if (lost_network_timeout) {
++			pfn_param.lost_network_timeout = htod32(MIN(lost_network_timeout,
++			                                 GSCAN_MIN_BSSID_TIMEOUT));
++		} else {
++			pfn_param.lost_network_timeout = htod32(GSCAN_MIN_BSSID_TIMEOUT);
++		}
++	} else
++#endif /* GSCAN_SUPPORT */
++	{
++		if (pfn_param.scan_freq < htod32(PNO_SCAN_MIN_FW_SEC) ||
++			pfn_param.scan_freq > htod32(PNO_SCAN_MAX_FW_SEC)) {
++			DHD_ERROR(("%s pno freq(%d sec) is not valid \n",
++				__FUNCTION__, PNO_SCAN_MIN_FW_SEC));
++			err = BCME_BADARG;
++			goto exit;
++		}
++	}
++
++	err = dhd_set_rand_mac_oui(dhd);
++	/* Ignore if chip doesnt support the feature */
++	if (err < 0 && err != BCME_UNSUPPORTED) {
++		DHD_ERROR(("%s : failed to set random mac for PNO scan, %d\n", __FUNCTION__, err));
++		goto exit;
++	}
++
++#ifdef GSCAN_SUPPORT
++			if (mode == DHD_PNO_BATCH_MODE ||
++				((mode & DHD_PNO_GSCAN_MODE) && pno_params->params_gscan.mscan)) {
++#else
++			if (mode == DHD_PNO_BATCH_MODE) {
++#endif /* GSCAN_SUPPORT */
++
++		int _tmp = pfn_param.bestn;
++		/* set bestn to calculate the max mscan which firmware supports */
++		err = dhd_iovar(dhd, 0, "pfnmem", (char *)&_tmp, sizeof(_tmp), NULL, 0, TRUE);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to set pfnmem\n", __FUNCTION__));
++			goto exit;
++		}
++		/* get max mscan which the firmware supports */
++		err = dhd_iovar(dhd, 0, "pfnmem", NULL, 0, (char *)&_tmp, sizeof(_tmp), FALSE);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to get pfnmem\n", __FUNCTION__));
++			goto exit;
++		}
++		pfn_param.mscan = MIN(pfn_param.mscan, _tmp);
++		DHD_PNO((" returned mscan : %d, set bestn : %d mscan %d\n", _tmp, pfn_param.bestn,
++		        pfn_param.mscan));
++	}
++	err = dhd_iovar(dhd, 0, "pfn_set", (char *)&pfn_param, sizeof(pfn_param), NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfn_set %d\n", __FUNCTION__, err));
++		goto exit;
++	}
++	/* need to return mscan if this is for batch scan instead of err */
++	err = (mode == DHD_PNO_BATCH_MODE)? pfn_param.mscan : err;
++exit:
++	return err;
++}
++static int
++_dhd_pno_add_ssid(dhd_pub_t *dhd, wlc_ssid_ext_t* ssids_list, int nssid)
++{
++	int err = BCME_OK;
++	int i = 0;
++	wl_pfn_t pfn_element;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	if (nssid) {
++		NULL_CHECK(ssids_list, "ssid list is NULL", err);
++	}
++	memset(&pfn_element, 0, sizeof(pfn_element));
++	{
++		int j;
++		for (j = 0; j < nssid; j++) {
++			DHD_PNO(("%s size = %d hidden = %d flags = %x rssi_thresh %d\n",
++				ssids_list[j].SSID, ssids_list[j].SSID_len, ssids_list[j].hidden,
++				ssids_list[j].flags, ssids_list[i].rssi_thresh));
++		}
++	}
++	/* Check for broadcast ssid */
++	for (i = 0; i < nssid; i++) {
++		if (!ssids_list[i].SSID_len) {
++			DHD_ERROR(("%d: Broadcast SSID is ilegal for PNO setting\n", i));
++			err = BCME_ERROR;
++			goto exit;
++		}
++	}
++	/* set all pfn ssid */
++	for (i = 0; i < nssid; i++) {
++		pfn_element.infra = htod32(DOT11_BSSTYPE_INFRASTRUCTURE);
++		pfn_element.auth = (DOT11_OPEN_SYSTEM);
++		pfn_element.wpa_auth = htod32(WPA_AUTH_PFN_ANY);
++		pfn_element.wsec = htod32(0);
++		pfn_element.infra = htod32(1);
++		if (ssids_list[i].hidden) {
++			pfn_element.flags = htod32(ENABLE << WL_PFN_HIDDEN_BIT);
++		} else {
++			pfn_element.flags = 0;
++		}
++		pfn_element.flags |= htod32(ssids_list[i].flags);
++		/* If a single RSSI threshold is defined, use that */
++#ifdef PNO_MIN_RSSI_TRIGGER
++		pfn_element.flags |= ((PNO_MIN_RSSI_TRIGGER & 0xFF) << WL_PFN_RSSI_SHIFT);
++#else
++		pfn_element.flags |= ((ssids_list[i].rssi_thresh & 0xFF) << WL_PFN_RSSI_SHIFT);
++#endif /* PNO_MIN_RSSI_TRIGGER */
++		memcpy((char *)pfn_element.ssid.SSID, ssids_list[i].SSID,
++			ssids_list[i].SSID_len);
++		pfn_element.ssid.SSID_len = ssids_list[i].SSID_len;
++		err = dhd_iovar(dhd, 0, "pfn_add", (char *)&pfn_element, sizeof(pfn_element),
++				NULL, 0, TRUE);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to execute pfn_add\n", __FUNCTION__));
++			goto exit;
++		}
++	}
++exit:
++	return err;
++}
++/* qsort compare function */
++static int
++_dhd_pno_cmpfunc(const void *a, const void *b)
++{
++	return (*(uint16*)a - *(uint16*)b);
++}
++static int
++_dhd_pno_chan_merge(uint16 *d_chan_list, int *nchan,
++	uint16 *chan_list1, int nchan1, uint16 *chan_list2, int nchan2)
++{
++	int err = BCME_OK;
++	int i = 0, j = 0, k = 0;
++	uint16 tmp;
++	NULL_CHECK(d_chan_list, "d_chan_list is NULL", err);
++	NULL_CHECK(nchan, "nchan is NULL", err);
++	NULL_CHECK(chan_list1, "chan_list1 is NULL", err);
++	NULL_CHECK(chan_list2, "chan_list2 is NULL", err);
++	/* chan_list1 and chan_list2 should be sorted at first */
++	while (i < nchan1 && j < nchan2) {
++		tmp = chan_list1[i] < chan_list2[j]?
++			chan_list1[i++] : chan_list2[j++];
++		for (; i < nchan1 && chan_list1[i] == tmp; i++);
++		for (; j < nchan2 && chan_list2[j] == tmp; j++);
++		d_chan_list[k++] = tmp;
++	}
++
++	while (i < nchan1) {
++		tmp = chan_list1[i++];
++		for (; i < nchan1 && chan_list1[i] == tmp; i++);
++		d_chan_list[k++] = tmp;
++	}
++
++	while (j < nchan2) {
++		tmp = chan_list2[j++];
++		for (; j < nchan2 && chan_list2[j] == tmp; j++);
++		d_chan_list[k++] = tmp;
++
++	}
++	*nchan = k;
++	return err;
++}
++static int
++_dhd_pno_get_channels(dhd_pub_t *dhd, uint16 *d_chan_list,
++	int *nchan, uint8 band, bool skip_dfs)
++{
++	int err = BCME_OK;
++	int i, j;
++	uint32 chan_buf[WL_NUMCHANNELS + 1];
++	wl_uint32_list_t *list;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	if (*nchan) {
++		NULL_CHECK(d_chan_list, "d_chan_list is NULL", err);
++	}
++	list = (wl_uint32_list_t *) (void *)chan_buf;
++	list->count = htod32(WL_NUMCHANNELS);
++	err = dhd_wl_ioctl_cmd(dhd, WLC_GET_VALID_CHANNELS, chan_buf, sizeof(chan_buf), FALSE, 0);
++	if (err < 0) {
++		DHD_ERROR(("failed to get channel list (err: %d)\n", err));
++		goto exit;
++	}
++	for (i = 0, j = 0; i < dtoh32(list->count) && i < *nchan; i++) {
++		if (band == WLC_BAND_2G) {
++			if (dtoh32(list->element[i]) > CHANNEL_2G_MAX)
++				continue;
++		} else if (band == WLC_BAND_5G) {
++			if (dtoh32(list->element[i]) <= CHANNEL_2G_MAX)
++				continue;
++			if (skip_dfs && is_dfs(dtoh32(list->element[i])))
++				continue;
++
++		} else if (band == WLC_BAND_AUTO) {
++			if (skip_dfs || !is_dfs(dtoh32(list->element[i])))
++				continue;
++
++		} else { /* All channels */
++			if (skip_dfs && is_dfs(dtoh32(list->element[i])))
++				continue;
++		}
++		if (dtoh32(list->element[i]) <= CHANNEL_5G_MAX) {
++			d_chan_list[j++] = (uint16) dtoh32(list->element[i]);
++		} else {
++			err = BCME_BADCHAN;
++			goto exit;
++		}
++	}
++	*nchan = j;
++exit:
++	return err;
++}
++static int
++_dhd_pno_convert_format(dhd_pub_t *dhd, struct dhd_pno_batch_params *params_batch,
++	char *buf, int nbufsize)
++{
++	int err = BCME_OK;
++	int bytes_written = 0, nreadsize = 0;
++	int t_delta = 0;
++	int nleftsize = nbufsize;
++	uint8 cnt = 0;
++	char *bp = buf;
++	char eabuf[ETHER_ADDR_STR_LEN];
++#ifdef PNO_DEBUG
++	char *_base_bp;
++	char msg[150];
++#endif
++	dhd_pno_bestnet_entry_t *iter, *next;
++	dhd_pno_scan_results_t *siter, *snext;
++	dhd_pno_best_header_t *phead, *pprev;
++	NULL_CHECK(params_batch, "params_batch is NULL", err);
++	if (nbufsize > 0)
++		NULL_CHECK(buf, "buf is NULL", err);
++	/* initialize the buffer */
++	memset(buf, 0, nbufsize);
++	DHD_PNO(("%s enter \n", __FUNCTION__));
++	/* # of scans */
++	if (!params_batch->get_batch.batch_started) {
++		bp += nreadsize = sprintf(bp, "scancount=%d\n",
++			params_batch->get_batch.expired_tot_scan_cnt);
++		nleftsize -= nreadsize;
++		params_batch->get_batch.batch_started = TRUE;
++	}
++	DHD_PNO(("%s scancount %d\n", __FUNCTION__, params_batch->get_batch.expired_tot_scan_cnt));
++	/* preestimate scan count until which scan result this report is going to end */
++	list_for_each_entry_safe(siter, snext,
++		&params_batch->get_batch.expired_scan_results_list, list) {
++		phead = siter->bestnetheader;
++		while (phead != NULL) {
++			/* if left_size is less than bestheader total size , stop this */
++			if (nleftsize <=
++				(phead->tot_size + phead->tot_cnt * ENTRY_OVERHEAD))
++				goto exit;
++			/* increase scan count */
++			cnt++;
++			/* # best of each scan */
++			DHD_PNO(("\n<loop : %d, apcount %d>\n", cnt - 1, phead->tot_cnt));
++			/* attribute of the scan */
++			if (phead->reason & PNO_STATUS_ABORT_MASK) {
++				bp += nreadsize = sprintf(bp, "trunc\n");
++				nleftsize -= nreadsize;
++			}
++			list_for_each_entry_safe(iter, next,
++				&phead->entry_list, list) {
++				t_delta = jiffies_to_msecs(jiffies - iter->recorded_time);
++#ifdef PNO_DEBUG
++				_base_bp = bp;
++				memset(msg, 0, sizeof(msg));
++#endif
++				/* BSSID info */
++				bp += nreadsize = sprintf(bp, "bssid=%s\n",
++				bcm_ether_ntoa((const struct ether_addr *)&iter->BSSID, eabuf));
++				nleftsize -= nreadsize;
++				/* SSID */
++				bp += nreadsize = sprintf(bp, "ssid=%s\n", iter->SSID);
++				nleftsize -= nreadsize;
++				/* channel */
++				bp += nreadsize = sprintf(bp, "freq=%d\n",
++				wf_channel2mhz(iter->channel,
++				iter->channel <= CH_MAX_2G_CHANNEL?
++				WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G));
++				nleftsize -= nreadsize;
++				/* RSSI */
++				bp += nreadsize = sprintf(bp, "level=%d\n", iter->RSSI);
++				nleftsize -= nreadsize;
++				/* add the time consumed in Driver to the timestamp of firmware */
++				iter->timestamp += t_delta;
++				bp += nreadsize = sprintf(bp, "age=%d\n", iter->timestamp);
++				nleftsize -= nreadsize;
++				/* RTT0 */
++				bp += nreadsize = sprintf(bp, "dist=%d\n",
++				(iter->rtt0 == 0)? -1 : iter->rtt0);
++				nleftsize -= nreadsize;
++				/* RTT1 */
++				bp += nreadsize = sprintf(bp, "distSd=%d\n",
++				(iter->rtt0 == 0)? -1 : iter->rtt1);
++				nleftsize -= nreadsize;
++				bp += nreadsize = sprintf(bp, "%s", AP_END_MARKER);
++				nleftsize -= nreadsize;
++				list_del(&iter->list);
++				MFREE(dhd->osh, iter, BESTNET_ENTRY_SIZE);
++#ifdef PNO_DEBUG
++				memcpy(msg, _base_bp, bp - _base_bp);
++				DHD_PNO(("Entry : \n%s", msg));
++#endif
++			}
++			bp += nreadsize = sprintf(bp, "%s", SCAN_END_MARKER);
++			DHD_PNO(("%s", SCAN_END_MARKER));
++			nleftsize -= nreadsize;
++			pprev = phead;
++			/* reset the header */
++			siter->bestnetheader = phead = phead->next;
++			MFREE(dhd->osh, pprev, BEST_HEADER_SIZE);
++
++			siter->cnt_header--;
++		}
++		if (phead == NULL) {
++			/* we store all entry in this scan , so it is ok to delete */
++			list_del(&siter->list);
++			MFREE(dhd->osh, siter, SCAN_RESULTS_SIZE);
++		}
++	}
++exit:
++	if (cnt < params_batch->get_batch.expired_tot_scan_cnt) {
++		DHD_ERROR(("Buffer size is small to save all batch entry,"
++			" cnt : %d (remained_scan_cnt): %d\n",
++			cnt, params_batch->get_batch.expired_tot_scan_cnt - cnt));
++	}
++	params_batch->get_batch.expired_tot_scan_cnt -= cnt;
++	/* set FALSE only if the link list  is empty after returning the data */
++	if (list_empty(&params_batch->get_batch.expired_scan_results_list)) {
++		params_batch->get_batch.batch_started = FALSE;
++		bp += sprintf(bp, "%s", RESULTS_END_MARKER);
++		DHD_PNO(("%s", RESULTS_END_MARKER));
++		DHD_PNO(("%s : Getting the batching data is complete\n", __FUNCTION__));
++	}
++	/* return used memory in buffer */
++	bytes_written = (int32)(bp - buf);
++	return bytes_written;
++}
++static int
++_dhd_pno_clear_all_batch_results(dhd_pub_t *dhd, struct list_head *head, bool only_last)
++{
++	int err = BCME_OK;
++	int removed_scan_cnt = 0;
++	dhd_pno_scan_results_t *siter, *snext;
++	dhd_pno_best_header_t *phead, *pprev;
++	dhd_pno_bestnet_entry_t *iter, *next;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(head, "head is NULL", err);
++	NULL_CHECK(head->next, "head->next is NULL", err);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	list_for_each_entry_safe(siter, snext,
++		head, list) {
++		if (only_last) {
++			/* in case that we need to delete only last one */
++			if (!list_is_last(&siter->list, head)) {
++				/* skip if the one is not last */
++				continue;
++			}
++		}
++		/* delete all data belong if the one is last */
++		phead = siter->bestnetheader;
++		while (phead != NULL) {
++			removed_scan_cnt++;
++			list_for_each_entry_safe(iter, next,
++			&phead->entry_list, list) {
++				list_del(&iter->list);
++				MFREE(dhd->osh, iter, BESTNET_ENTRY_SIZE);
++			}
++			pprev = phead;
++			phead = phead->next;
++			MFREE(dhd->osh, pprev, BEST_HEADER_SIZE);
++		}
++		if (phead == NULL) {
++			/* it is ok to delete top node */
++			list_del(&siter->list);
++			MFREE(dhd->osh, siter, SCAN_RESULTS_SIZE);
++		}
++	}
++	return removed_scan_cnt;
++}
++
++static int
++_dhd_pno_cfg(dhd_pub_t *dhd, uint16 *channel_list, int nchan)
++{
++	int err = BCME_OK;
++	int i = 0;
++	wl_pfn_cfg_t pfncfg_param;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	if (nchan) {
++		NULL_CHECK(channel_list, "nchan is NULL", err);
++	}
++	if (nchan > WL_NUMCHANNELS) {
++		return BCME_RANGE;
++	}
++	DHD_PNO(("%s enter :  nchan : %d\n", __FUNCTION__, nchan));
++	memset(&pfncfg_param, 0, sizeof(wl_pfn_cfg_t));
++	/* Setup default values */
++	pfncfg_param.reporttype = htod32(WL_PFN_REPORT_ALLNET);
++	pfncfg_param.channel_num = htod32(0);
++
++	for (i = 0; i < nchan; i++)
++		pfncfg_param.channel_list[i] = channel_list[i];
++
++	pfncfg_param.channel_num = htod32(nchan);
++	err = dhd_iovar(dhd, 0, "pfn_cfg", (char *)&pfncfg_param, sizeof(pfncfg_param), NULL, 0,
++			TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfn_cfg\n", __FUNCTION__));
++		goto exit;
++	}
++exit:
++	return err;
++}
++static int
++_dhd_pno_reinitialize_prof(dhd_pub_t *dhd, dhd_pno_params_t *params, dhd_pno_mode_t mode)
++{
++	int err = BCME_OK;
++	dhd_pno_status_info_t *_pno_state;
++	NULL_CHECK(dhd, "dhd is NULL\n", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL\n", err);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	mutex_lock(&_pno_state->pno_mutex);
++	switch (mode) {
++	case DHD_PNO_LEGACY_MODE: {
++		struct dhd_pno_ssid *iter, *next;
++		if (params->params_legacy.nssid > 0) {
++			list_for_each_entry_safe(iter, next,
++				&params->params_legacy.ssid_list, list) {
++				list_del(&iter->list);
++				kfree(iter);
++			}
++		}
++		params->params_legacy.nssid = 0;
++		params->params_legacy.scan_fr = 0;
++		params->params_legacy.pno_freq_expo_max = 0;
++		params->params_legacy.pno_repeat = 0;
++		params->params_legacy.nchan = 0;
++		memset(params->params_legacy.chan_list, 0,
++			sizeof(params->params_legacy.chan_list));
++		break;
++	}
++	case DHD_PNO_BATCH_MODE: {
++		params->params_batch.scan_fr = 0;
++		params->params_batch.mscan = 0;
++		params->params_batch.nchan = 0;
++		params->params_batch.rtt = 0;
++		params->params_batch.bestn = 0;
++		params->params_batch.nchan = 0;
++		params->params_batch.band = WLC_BAND_AUTO;
++		memset(params->params_batch.chan_list, 0,
++			sizeof(params->params_batch.chan_list));
++		params->params_batch.get_batch.batch_started = FALSE;
++		params->params_batch.get_batch.buf = NULL;
++		params->params_batch.get_batch.bufsize = 0;
++		params->params_batch.get_batch.reason = 0;
++		_dhd_pno_clear_all_batch_results(dhd,
++			&params->params_batch.get_batch.scan_results_list, FALSE);
++		_dhd_pno_clear_all_batch_results(dhd,
++			&params->params_batch.get_batch.expired_scan_results_list, FALSE);
++		params->params_batch.get_batch.tot_scan_cnt = 0;
++		params->params_batch.get_batch.expired_tot_scan_cnt = 0;
++		params->params_batch.get_batch.top_node_cnt = 0;
++		INIT_LIST_HEAD(&params->params_batch.get_batch.scan_results_list);
++		INIT_LIST_HEAD(&params->params_batch.get_batch.expired_scan_results_list);
++		break;
++	}
++	case DHD_PNO_HOTLIST_MODE: {
++		struct dhd_pno_bssid *iter, *next;
++		if (params->params_hotlist.nbssid > 0) {
++			list_for_each_entry_safe(iter, next,
++				&params->params_hotlist.bssid_list, list) {
++				list_del(&iter->list);
++				kfree(iter);
++			}
++		}
++		params->params_hotlist.scan_fr = 0;
++		params->params_hotlist.nbssid = 0;
++		params->params_hotlist.nchan = 0;
++		params->params_batch.band = WLC_BAND_AUTO;
++		memset(params->params_hotlist.chan_list, 0,
++			sizeof(params->params_hotlist.chan_list));
++		break;
++	}
++	default:
++		DHD_ERROR(("%s : unknown mode : %d\n", __FUNCTION__, mode));
++		break;
++	}
++	mutex_unlock(&_pno_state->pno_mutex);
++	return err;
++}
++static int
++_dhd_pno_add_bssid(dhd_pub_t *dhd, wl_pfn_bssid_t *p_pfn_bssid, int nbssid)
++{
++	int err = BCME_OK;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	if (nbssid) {
++		NULL_CHECK(p_pfn_bssid, "bssid list is NULL", err);
++	}
++	err = dhd_iovar(dhd, 0, "pfn_add_bssid", (char *)p_pfn_bssid,
++			sizeof(wl_pfn_bssid_t) * nbssid, NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfn_cfg\n", __FUNCTION__));
++		goto exit;
++	}
++exit:
++	return err;
++}
++
++#ifdef GSCAN_SUPPORT
++static int
++_dhd_pno_add_significant_bssid(dhd_pub_t *dhd,
++   wl_pfn_significant_bssid_t *p_pfn_significant_bssid, int nbssid)
++{
++	int err = BCME_OK;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++
++	if (!nbssid) {
++		err = BCME_ERROR;
++		goto exit;
++	}
++
++	NULL_CHECK(p_pfn_significant_bssid, "bssid list is NULL", err);
++
++	err = dhd_iovar(dhd, 0, "pfn_add_swc_bssid", (char *)p_pfn_significant_bssid,
++			sizeof(wl_pfn_significant_bssid_t) * nbssid, NULL, 0, TRUE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to execute pfn_significant_bssid %d\n", __FUNCTION__, err));
++		goto exit;
++	}
++exit:
++	return err;
++}
++#endif /* GSCAN_SUPPORT */
++
++int
++dhd_pno_stop_for_ssid(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	uint32 mode = 0;
++	dhd_pno_status_info_t *_pno_state;
++	dhd_pno_params_t *_params;
++	wl_pfn_bssid_t *p_pfn_bssid = NULL;
++	NULL_CHECK(dhd, "dev is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	if (!(_pno_state->pno_mode & DHD_PNO_LEGACY_MODE)) {
++		DHD_ERROR(("%s : LEGACY PNO MODE is not enabled\n", __FUNCTION__));
++		goto exit;
++	}
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	_pno_state->pno_mode &= ~DHD_PNO_LEGACY_MODE;
++#ifdef GSCAN_SUPPORT
++	if (_pno_state->pno_mode & DHD_PNO_GSCAN_MODE) {
++		struct dhd_pno_gscan_params *gscan_params;
++
++		_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++		gscan_params = &_params->params_gscan;
++		if (gscan_params->mscan) {
++			/* retrieve the batching data from firmware into host */
++			err = dhd_wait_batch_results_complete(dhd);
++			if (err != BCME_OK)
++				goto exit;
++		}
++		/* save current pno_mode before calling dhd_pno_clean */
++		mutex_lock(&_pno_state->pno_mutex);
++		mode = _pno_state->pno_mode;
++		err = dhd_pno_clean(dhd);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++				__FUNCTION__, err));
++			mutex_unlock(&_pno_state->pno_mutex);
++			goto exit;
++		}
++		/* restore previous pno_mode */
++		_pno_state->pno_mode = mode;
++		mutex_unlock(&_pno_state->pno_mutex);
++		/* Restart gscan */
++		err = dhd_pno_initiate_gscan_request(dhd, 1, 0);
++		goto exit;
++	}
++#endif /* GSCAN_SUPPORT */
++	/* restart Batch mode  if the batch mode is on */
++	if (_pno_state->pno_mode & (DHD_PNO_BATCH_MODE | DHD_PNO_HOTLIST_MODE)) {
++		/* retrieve the batching data from firmware into host */
++		dhd_pno_get_for_batch(dhd, NULL, 0, PNO_STATUS_DISABLE);
++		/* save current pno_mode before calling dhd_pno_clean */
++		mode = _pno_state->pno_mode;
++		dhd_pno_clean(dhd);
++		/* restore previous pno_mode */
++		_pno_state->pno_mode = mode;
++		if (_pno_state->pno_mode & DHD_PNO_BATCH_MODE) {
++			_params = &(_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS]);
++			/* restart BATCH SCAN */
++			err = dhd_pno_set_for_batch(dhd, &_params->params_batch);
++			if (err < 0) {
++				_pno_state->pno_mode &= ~DHD_PNO_BATCH_MODE;
++				DHD_ERROR(("%s : failed to restart batch scan(err: %d)\n",
++					__FUNCTION__, err));
++				goto exit;
++			}
++		} else if (_pno_state->pno_mode & DHD_PNO_HOTLIST_MODE) {
++			/* restart HOTLIST SCAN */
++			struct dhd_pno_bssid *iter, *next;
++			_params = &(_pno_state->pno_params_arr[INDEX_OF_HOTLIST_PARAMS]);
++			p_pfn_bssid = kzalloc(sizeof(wl_pfn_bssid_t) *
++			_params->params_hotlist.nbssid, GFP_KERNEL);
++			if (p_pfn_bssid == NULL) {
++				DHD_ERROR(("%s : failed to allocate wl_pfn_bssid_t array"
++				" (count: %d)",
++					__FUNCTION__, _params->params_hotlist.nbssid));
++				err = BCME_ERROR;
++				_pno_state->pno_mode &= ~DHD_PNO_HOTLIST_MODE;
++				goto exit;
++			}
++			/* convert dhd_pno_bssid to wl_pfn_bssid */
++			list_for_each_entry_safe(iter, next,
++			&_params->params_hotlist.bssid_list, list) {
++				memcpy(&p_pfn_bssid->macaddr,
++				&iter->macaddr, ETHER_ADDR_LEN);
++				p_pfn_bssid->flags = iter->flags;
++				p_pfn_bssid++;
++			}
++			err = dhd_pno_set_for_hotlist(dhd, p_pfn_bssid, &_params->params_hotlist);
++			if (err < 0) {
++				_pno_state->pno_mode &= ~DHD_PNO_HOTLIST_MODE;
++				DHD_ERROR(("%s : failed to restart hotlist scan(err: %d)\n",
++					__FUNCTION__, err));
++				goto exit;
++			}
++		}
++	} else {
++		err = dhd_pno_clean(dhd);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++	}
++exit:
++	kfree(p_pfn_bssid);
++	return err;
++}
++
++int
++dhd_pno_enable(dhd_pub_t *dhd, int enable)
++{
++	int err = BCME_OK;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	return (_dhd_pno_enable(dhd, enable));
++}
++
++static wlc_ssid_ext_t *
++dhd_pno_get_legacy_pno_ssid(dhd_pub_t *dhd, dhd_pno_status_info_t *pno_state)
++{
++	int err = BCME_OK;
++	int i;
++	struct dhd_pno_ssid *iter, *next;
++	dhd_pno_params_t	*_params1 = &pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS];
++	wlc_ssid_ext_t *p_ssid_list;
++
++	p_ssid_list = kzalloc(sizeof(wlc_ssid_ext_t) *
++	                   _params1->params_legacy.nssid, GFP_KERNEL);
++	if (p_ssid_list == NULL) {
++		DHD_ERROR(("%s : failed to allocate wlc_ssid_ext_t array (count: %d)",
++			__FUNCTION__, _params1->params_legacy.nssid));
++		err = BCME_ERROR;
++		pno_state->pno_mode &= ~DHD_PNO_LEGACY_MODE;
++		goto exit;
++	}
++	i = 0;
++	/* convert dhd_pno_ssid to wlc_ssid_ext_t */
++	list_for_each_entry_safe(iter, next, &_params1->params_legacy.ssid_list, list) {
++		p_ssid_list[i].SSID_len = iter->SSID_len;
++		p_ssid_list[i].hidden = iter->hidden;
++		p_ssid_list[i].rssi_thresh = iter->rssi_thresh;
++		memcpy(p_ssid_list[i].SSID, iter->SSID, p_ssid_list[i].SSID_len);
++		i++;
++	}
++exit:
++	return p_ssid_list;
++}
++
++#ifdef GSCAN_SUPPORT
++static int dhd_epno_set_ssid(dhd_pub_t *dhd,
++            dhd_pno_status_info_t *pno_state)
++{
++	int err = BCME_OK;
++	dhd_epno_params_t *iter, *next;
++	dhd_pno_params_t *_params1 = &pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++	struct dhd_pno_gscan_params *gscan_params;
++	wlc_ssid_ext_t ssid_elem;
++	wl_pfn_ext_list_t *p_ssid_ext_elem = NULL;
++	uint32 mem_needed = 0, i = 0;
++	uint16 num_visible_epno_ssid;
++	uint8 flags;
++
++	gscan_params = &_params1->params_gscan;
++	num_visible_epno_ssid = gscan_params->num_visible_epno_ssid;
++
++	if (num_visible_epno_ssid) {
++		mem_needed =  sizeof(wl_pfn_ext_list_t) + (sizeof(wl_pfn_ext_t) *
++		                        (num_visible_epno_ssid - 1));
++		p_ssid_ext_elem = kzalloc(mem_needed, GFP_KERNEL);
++		if (p_ssid_ext_elem == NULL) {
++			DHD_ERROR(("%s : failed to allocate memory %u\n",
++				__FUNCTION__, mem_needed));
++			err = BCME_NOMEM;
++			goto exit;
++		}
++		p_ssid_ext_elem->version = PFN_SSID_EXT_VERSION;
++		p_ssid_ext_elem->count = num_visible_epno_ssid;
++	}
++
++	DHD_ERROR(("Total ssids %d, visible SSIDs %d\n", gscan_params->num_epno_ssid,
++	     num_visible_epno_ssid));
++
++	/* convert dhd_pno_ssid to wlc_ssid_ext_t */
++	list_for_each_entry_safe(iter, next, &gscan_params->epno_ssid_list, list) {
++		if (iter->flags & DHD_PNO_USE_SSID) {
++			memset(&ssid_elem, 0, sizeof(ssid_elem));
++			ssid_elem.SSID_len = iter->ssid_len;
++			ssid_elem.hidden = TRUE;
++			flags = (iter->flags & DHD_EPNO_A_BAND_TRIG) ?
++			       WL_PFN_SSID_A_BAND_TRIG: 0;
++			flags |= (iter->flags & DHD_EPNO_BG_BAND_TRIG) ?
++			       WL_PFN_SSID_BG_BAND_TRIG: 0;
++			ssid_elem.flags = flags;
++			ssid_elem.rssi_thresh = iter->rssi_thresh;
++			memcpy(ssid_elem.SSID, iter->ssid, iter->ssid_len);
++			if ((err = _dhd_pno_add_ssid(dhd, &ssid_elem, 1)) < 0) {
++				DHD_ERROR(("failed to add ssid list (err %d) in firmware\n", err));
++				goto exit;
++			}
++		} else if (i < num_visible_epno_ssid) {
++			p_ssid_ext_elem->pfn_ext[i].rssi_thresh = iter->rssi_thresh;
++			switch (iter->auth) {
++				case DHD_PNO_AUTH_CODE_OPEN:
++					p_ssid_ext_elem->pfn_ext[i].wpa_auth = WPA_AUTH_DISABLED;
++					break;
++				case DHD_PNO_AUTH_CODE_PSK:
++					p_ssid_ext_elem->pfn_ext[i].wpa_auth =
++					          (WPA2_AUTH_PSK | WPA_AUTH_PSK);
++					break;
++				case DHD_PNO_AUTH_CODE_EAPOL:
++					p_ssid_ext_elem->pfn_ext[i].wpa_auth =
++					           (uint16)WPA_AUTH_PFN_ANY;
++					break;
++				default:
++					p_ssid_ext_elem->pfn_ext[i].wpa_auth =
++					           (uint16)WPA_AUTH_PFN_ANY;
++					break;
++			}
++			memcpy(p_ssid_ext_elem->pfn_ext[i].ssid, iter->ssid, iter->ssid_len);
++			p_ssid_ext_elem->pfn_ext[i].ssid_len = iter->ssid_len;
++			iter->index = gscan_params->ssid_ext_last_used_index++;
++			flags = (iter->flags & DHD_EPNO_A_BAND_TRIG) ?
++			       WL_PFN_SSID_A_BAND_TRIG: 0;
++			flags |= (iter->flags & DHD_EPNO_BG_BAND_TRIG) ?
++			       WL_PFN_SSID_BG_BAND_TRIG: 0;
++			p_ssid_ext_elem->pfn_ext[i].flags = flags;
++			DHD_ERROR(("SSID %s idx %d rssi thresh %d flags %x\n", iter->ssid,
++			        iter->index, iter->rssi_thresh, flags));
++			i++;
++		}
++	}
++	if (num_visible_epno_ssid) {
++		err = dhd_iovar(dhd, 0, "pfn_add_ssid_ext", (char *)p_ssid_ext_elem,
++			mem_needed, NULL, 0, TRUE);
++
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to execute pfn_add_pno_ext_ssid %d\n", __FUNCTION__,
++			     err));
++		}
++	}
++exit:
++	kfree(p_ssid_ext_elem);
++	return err;
++}
++#endif /* GSCAN_SUPPORT */
++
++static int
++dhd_pno_add_to_ssid_list(dhd_pno_params_t *params, wlc_ssid_ext_t *ssid_list,
++    int nssid)
++{
++	int ret = 0;
++	int i;
++	struct dhd_pno_ssid *_pno_ssid;
++
++	for (i = 0; i < nssid; i++) {
++		if (ssid_list[i].SSID_len > DOT11_MAX_SSID_LEN) {
++			DHD_ERROR(("%s : Invalid SSID length %d\n",
++				__FUNCTION__, ssid_list[i].SSID_len));
++			ret = BCME_ERROR;
++			goto exit;
++		}
++		_pno_ssid = kzalloc(sizeof(struct dhd_pno_ssid), GFP_KERNEL);
++		if (_pno_ssid == NULL) {
++			DHD_ERROR(("%s : failed to allocate struct dhd_pno_ssid\n",
++				__FUNCTION__));
++			ret = BCME_ERROR;
++			goto exit;
++		}
++		_pno_ssid->SSID_len = ssid_list[i].SSID_len;
++		_pno_ssid->hidden = ssid_list[i].hidden;
++		_pno_ssid->rssi_thresh = ssid_list[i].rssi_thresh;
++		memcpy(_pno_ssid->SSID, ssid_list[i].SSID, _pno_ssid->SSID_len);
++		list_add_tail(&_pno_ssid->list, &params->params_legacy.ssid_list);
++		params->params_legacy.nssid++;
++	}
++
++exit:
++	return ret;
++}
++
++int
++dhd_pno_set_for_ssid(dhd_pub_t *dhd, wlc_ssid_ext_t* ssid_list, int nssid,
++	uint16  scan_fr, int pno_repeat, int pno_freq_expo_max, uint16 *channel_list, int nchan)
++{
++	dhd_pno_params_t *_params;
++	dhd_pno_params_t *_params2;
++	dhd_pno_status_info_t *_pno_state;
++	uint16 _chan_list[WL_NUMCHANNELS];
++	int32 tot_nchan = 0;
++	int err = BCME_OK;
++	int i;
++	int mode = 0;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++
++	if (!dhd_support_sta_mode(dhd)) {
++		err = BCME_BADOPTION;
++		goto exit_no_clear;
++	}
++	DHD_PNO(("%s enter : scan_fr :%d, pno_repeat :%d,"
++			"pno_freq_expo_max: %d, nchan :%d\n", __FUNCTION__,
++			scan_fr, pno_repeat, pno_freq_expo_max, nchan));
++
++	_params = &(_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS]);
++	/* If GSCAN is also ON will handle this down below */
++#ifdef GSCAN_SUPPORT
++	if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE &&
++		!(_pno_state->pno_mode & DHD_PNO_GSCAN_MODE)) {
++#else
++		if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) {
++#endif /* GSCAN_SUPPORT */
++		DHD_ERROR(("%s : Legacy PNO mode was already started, "
++			"will disable previous one to start new one\n", __FUNCTION__));
++		err = dhd_pno_stop_for_ssid(dhd);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to stop legacy PNO (err %d)\n",
++				__FUNCTION__, err));
++			goto exit_no_clear;
++		}
++	}
++	_pno_state->pno_mode |= DHD_PNO_LEGACY_MODE;
++	err = _dhd_pno_reinitialize_prof(dhd, _params, DHD_PNO_LEGACY_MODE);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to reinitialize profile (err %d)\n",
++			__FUNCTION__, err));
++		goto exit_no_clear;
++	}
++	memset(_chan_list, 0, sizeof(_chan_list));
++	tot_nchan = MIN(nchan, WL_NUMCHANNELS);
++	if (tot_nchan > 0 && channel_list) {
++		for (i = 0; i < tot_nchan; i++)
++		_params->params_legacy.chan_list[i] = _chan_list[i] = channel_list[i];
++	}
++#ifdef GSCAN_SUPPORT
++	else {
++		tot_nchan = WL_NUMCHANNELS;
++		err = _dhd_pno_get_channels(dhd, _chan_list, &tot_nchan,
++				(WLC_BAND_2G | WLC_BAND_5G), FALSE);
++		if (err < 0) {
++			tot_nchan = 0;
++			DHD_PNO(("Could not get channel list for PNO SSID\n"));
++		} else {
++			for (i = 0; i < tot_nchan; i++)
++			_params->params_legacy.chan_list[i] = _chan_list[i];
++		}
++	}
++#endif /* GSCAN_SUPPORT */
++
++	if (_pno_state->pno_mode & (DHD_PNO_BATCH_MODE | DHD_PNO_HOTLIST_MODE)) {
++		DHD_PNO(("BATCH SCAN is on progress in firmware\n"));
++		/* retrieve the batching data from firmware into host */
++		dhd_pno_get_for_batch(dhd, NULL, 0, PNO_STATUS_DISABLE);
++		/* store current pno_mode before disabling pno */
++		mode = _pno_state->pno_mode;
++		err = _dhd_pno_enable(dhd, PNO_OFF);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to disable PNO\n", __FUNCTION__));
++			goto exit_no_clear;
++		}
++		/* restore the previous mode */
++		_pno_state->pno_mode = mode;
++		/* use superset of channel list between two mode */
++		if (_pno_state->pno_mode & DHD_PNO_BATCH_MODE) {
++			_params2 = &(_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS]);
++			if (_params2->params_batch.nchan > 0 && tot_nchan > 0) {
++				err = _dhd_pno_chan_merge(_chan_list, &tot_nchan,
++					&_params2->params_batch.chan_list[0],
++					_params2->params_batch.nchan,
++					&channel_list[0], tot_nchan);
++				if (err < 0) {
++					DHD_ERROR(("%s : failed to merge channel list"
++					" between legacy and batch\n",
++						__FUNCTION__));
++					goto exit_no_clear;
++				}
++			}  else {
++				DHD_PNO(("superset channel will use"
++				" all channels in firmware\n"));
++			}
++		} else if (_pno_state->pno_mode & DHD_PNO_HOTLIST_MODE) {
++			_params2 = &(_pno_state->pno_params_arr[INDEX_OF_HOTLIST_PARAMS]);
++			if (_params2->params_hotlist.nchan > 0 && tot_nchan > 0) {
++				err = _dhd_pno_chan_merge(_chan_list, &tot_nchan,
++					&_params2->params_hotlist.chan_list[0],
++					_params2->params_hotlist.nchan,
++					&channel_list[0], tot_nchan);
++				if (err < 0) {
++					DHD_ERROR(("%s : failed to merge channel list"
++					" between legacy and hotlist\n",
++						__FUNCTION__));
++					goto exit_no_clear;
++				}
++			}
++		}
++	}
++	_params->params_legacy.scan_fr = scan_fr;
++	_params->params_legacy.pno_repeat = pno_repeat;
++	_params->params_legacy.pno_freq_expo_max = pno_freq_expo_max;
++	_params->params_legacy.nchan = tot_nchan;
++	_params->params_legacy.nssid = 0;
++	INIT_LIST_HEAD(&_params->params_legacy.ssid_list);
++#ifdef GSCAN_SUPPORT
++	/* dhd_pno_initiate_gscan_request will handle simultaneous Legacy PNO and GSCAN */
++	if (_pno_state->pno_mode & DHD_PNO_GSCAN_MODE) {
++		if (dhd_pno_add_to_ssid_list(_params, ssid_list, nssid) < 0) {
++			err = BCME_ERROR;
++			goto exit;
++		}
++		DHD_PNO(("GSCAN mode is ON! Will restart GSCAN+Legacy PNO\n"));
++		err = dhd_pno_initiate_gscan_request(dhd, 1, 0);
++		goto exit;
++	}
++#endif /* GSCAN_SUPPORT */
++	if ((err = _dhd_pno_set(dhd, _params, DHD_PNO_LEGACY_MODE)) < 0) {
++		DHD_ERROR(("failed to set call pno_set (err %d) in firmware\n", err));
++		goto exit;
++	}
++	if ((err = _dhd_pno_add_ssid(dhd, ssid_list, nssid)) < 0) {
++		DHD_ERROR(("failed to add ssid list(err %d), %d in firmware\n", err, nssid));
++		goto exit;
++	}
++	if (dhd_pno_add_to_ssid_list(_params, ssid_list, nssid) < 0) {
++		err = BCME_ERROR;
++		goto exit;
++	}
++	if (tot_nchan > 0) {
++		if ((err = _dhd_pno_cfg(dhd, _chan_list, tot_nchan)) < 0) {
++			DHD_ERROR(("%s : failed to set call pno_cfg (err %d) in firmware\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++	}
++	if (_pno_state->pno_status == DHD_PNO_DISABLED) {
++		if ((err = _dhd_pno_enable(dhd, PNO_ON)) < 0)
++			DHD_ERROR(("%s : failed to enable PNO\n", __FUNCTION__));
++	}
++exit:
++	if (err < 0) {
++		_dhd_pno_reinitialize_prof(dhd, _params, DHD_PNO_LEGACY_MODE);
++	}
++exit_no_clear:
++	/* clear mode in case of error */
++	if (err < 0) {
++		int ret = dhd_pno_clean(dhd);
++
++		if (ret < 0) {
++			DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++				__FUNCTION__, ret));
++		} else {
++			_pno_state->pno_mode &= ~DHD_PNO_LEGACY_MODE;
++		}
++	}
++	return err;
++}
++int
++dhd_pno_set_for_batch(dhd_pub_t *dhd, struct dhd_pno_batch_params *batch_params)
++{
++	int err = BCME_OK;
++	uint16 _chan_list[WL_NUMCHANNELS];
++	int rem_nchan = 0, tot_nchan = 0;
++	int mode = 0, mscan = 0;
++	dhd_pno_params_t *_params;
++	dhd_pno_params_t *_params2;
++	dhd_pno_status_info_t *_pno_state;
++	wlc_ssid_ext_t *p_ssid_list = NULL;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	NULL_CHECK(batch_params, "batch_params is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	if (!dhd_support_sta_mode(dhd)) {
++		err = BCME_BADOPTION;
++		goto exit;
++	}
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n", __FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++	_params = &_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS];
++	if (!(_pno_state->pno_mode & DHD_PNO_BATCH_MODE)) {
++		_pno_state->pno_mode |= DHD_PNO_BATCH_MODE;
++		err = _dhd_pno_reinitialize_prof(dhd, _params, DHD_PNO_BATCH_MODE);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call _dhd_pno_reinitialize_prof\n",
++				__FUNCTION__));
++			goto exit;
++		}
++	} else {
++		/* batch mode is already started */
++		return -EBUSY;
++	}
++	_params->params_batch.scan_fr = batch_params->scan_fr;
++	_params->params_batch.bestn = batch_params->bestn;
++	_params->params_batch.mscan = (batch_params->mscan)?
++		batch_params->mscan : DEFAULT_BATCH_MSCAN;
++	_params->params_batch.nchan = batch_params->nchan;
++	memcpy(_params->params_batch.chan_list, batch_params->chan_list,
++		sizeof(_params->params_batch.chan_list));
++
++	memset(_chan_list, 0, sizeof(_chan_list));
++
++	rem_nchan = ARRAYSIZE(batch_params->chan_list) - batch_params->nchan;
++	if (batch_params->band == WLC_BAND_2G || batch_params->band == WLC_BAND_5G) {
++		/* get a valid channel list based on band B or A */
++		err = _dhd_pno_get_channels(dhd,
++		&_params->params_batch.chan_list[batch_params->nchan],
++		&rem_nchan, batch_params->band, FALSE);
++		if (err < 0) {
++			DHD_ERROR(("%s: failed to get valid channel list(band : %d)\n",
++				__FUNCTION__, batch_params->band));
++			goto exit;
++		}
++		/* now we need to update nchan because rem_chan has valid channel count */
++		_params->params_batch.nchan += rem_nchan;
++		/* need to sort channel list */
++		sort(_params->params_batch.chan_list, _params->params_batch.nchan,
++			sizeof(_params->params_batch.chan_list[0]), _dhd_pno_cmpfunc, NULL);
++	}
++#ifdef PNO_DEBUG
++{
++		DHD_PNO(("Channel list : "));
++		for (i = 0; i < _params->params_batch.nchan; i++) {
++			DHD_PNO(("%d ", _params->params_batch.chan_list[i]));
++		}
++		DHD_PNO(("\n"));
++}
++#endif
++	if (_params->params_batch.nchan) {
++		/* copy the channel list into local array */
++		memcpy(_chan_list, _params->params_batch.chan_list, sizeof(_chan_list));
++		tot_nchan = _params->params_batch.nchan;
++	}
++	if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) {
++		DHD_PNO(("PNO SSID is on progress in firmware\n"));
++		/* store current pno_mode before disabling pno */
++		mode = _pno_state->pno_mode;
++		err = _dhd_pno_enable(dhd, PNO_OFF);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to disable PNO\n", __FUNCTION__));
++			goto exit;
++		}
++		/* restore the previous mode */
++		_pno_state->pno_mode = mode;
++		/* Use the superset for channelist between two mode */
++		_params2 = &(_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS]);
++		if (_params2->params_legacy.nchan > 0 && _params->params_batch.nchan > 0) {
++			err = _dhd_pno_chan_merge(_chan_list, &tot_nchan,
++				&_params2->params_legacy.chan_list[0],
++				_params2->params_legacy.nchan,
++				&_params->params_batch.chan_list[0], _params->params_batch.nchan);
++			if (err < 0) {
++				DHD_ERROR(("%s : failed to merge channel list"
++				" between legacy and batch\n",
++					__FUNCTION__));
++				goto exit;
++			}
++		} else {
++			DHD_PNO(("superset channel will use all channels in firmware\n"));
++		}
++		p_ssid_list = dhd_pno_get_legacy_pno_ssid(dhd, _pno_state);
++		if (!p_ssid_list) {
++			err = BCME_NOMEM;
++			DHD_ERROR(("failed to get Legacy PNO SSID list\n"));
++			goto exit;
++		}
++		if ((err = _dhd_pno_add_ssid(dhd, p_ssid_list,
++			_params2->params_legacy.nssid)) < 0) {
++			DHD_ERROR(("failed to add ssid list (err %d) in firmware\n", err));
++			goto exit;
++		}
++	}
++	if ((err = _dhd_pno_set(dhd, _params, DHD_PNO_BATCH_MODE)) < 0) {
++		DHD_ERROR(("%s : failed to set call pno_set (err %d) in firmware\n",
++			__FUNCTION__, err));
++		goto exit;
++	} else {
++		/* we need to return mscan */
++		mscan = err;
++	}
++	if (tot_nchan > 0) {
++		if ((err = _dhd_pno_cfg(dhd, _chan_list, tot_nchan)) < 0) {
++			DHD_ERROR(("%s : failed to set call pno_cfg (err %d) in firmware\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++	}
++	if (_pno_state->pno_status == DHD_PNO_DISABLED) {
++		if ((err = _dhd_pno_enable(dhd, PNO_ON)) < 0)
++			DHD_ERROR(("%s : failed to enable PNO\n", __FUNCTION__));
++	}
++exit:
++	/* clear mode in case of error */
++	if (err < 0)
++		_pno_state->pno_mode &= ~DHD_PNO_BATCH_MODE;
++	else {
++		/* return #max scan firmware can do */
++		err = mscan;
++	}
++	if (p_ssid_list)
++		kfree(p_ssid_list);
++	return err;
++}
++
++
++#ifdef GSCAN_SUPPORT
++static void
++dhd_pno_reset_cfg_gscan(dhd_pno_params_t *_params,
++            dhd_pno_status_info_t *_pno_state, uint8 flags)
++{
++	DHD_ERROR(("%s enter\n", __FUNCTION__));
++
++	if (flags & GSCAN_FLUSH_SCAN_CFG) {
++		_params->params_gscan.bestn = 0;
++		_params->params_gscan.mscan = 0;
++		_params->params_gscan.buffer_threshold = GSCAN_BATCH_NO_THR_SET;
++		_params->params_gscan.scan_fr = 0;
++		_params->params_gscan.send_all_results_flag = 0;
++		memset(_params->params_gscan.channel_bucket, 0,
++		_params->params_gscan.nchannel_buckets *
++		 sizeof(struct dhd_pno_gscan_channel_bucket));
++		_params->params_gscan.nchannel_buckets = 0;
++		DHD_PNO(("Flush Scan config\n"));
++	}
++	if (flags & GSCAN_FLUSH_HOTLIST_CFG) {
++		struct dhd_pno_bssid *iter, *next;
++		if (_params->params_gscan.nbssid_hotlist > 0) {
++			list_for_each_entry_safe(iter, next,
++				&_params->params_gscan.hotlist_bssid_list, list) {
++				list_del(&iter->list);
++				kfree(iter);
++			}
++		}
++		_params->params_gscan.nbssid_hotlist = 0;
++		DHD_PNO(("Flush Hotlist Config\n"));
++	}
++	if (flags & GSCAN_FLUSH_SIGNIFICANT_CFG) {
++		dhd_pno_significant_bssid_t *iter, *next;
++
++		if (_params->params_gscan.nbssid_significant_change > 0) {
++			list_for_each_entry_safe(iter, next,
++				&_params->params_gscan.significant_bssid_list, list) {
++				list_del(&iter->list);
++				kfree(iter);
++			}
++		}
++		_params->params_gscan.nbssid_significant_change = 0;
++		DHD_PNO(("Flush Significant Change Config\n"));
++	}
++	if (flags & GSCAN_FLUSH_EPNO_CFG) {
++		dhd_epno_params_t *iter, *next;
++
++		if (_params->params_gscan.num_epno_ssid > 0) {
++			list_for_each_entry_safe(iter, next,
++				&_params->params_gscan.epno_ssid_list, list) {
++				list_del(&iter->list);
++				kfree(iter);
++			}
++		}
++		_params->params_gscan.num_epno_ssid = 0;
++		_params->params_gscan.num_visible_epno_ssid = 0;
++		_params->params_gscan.ssid_ext_last_used_index = 0;
++		DHD_PNO(("Flushed ePNO Config\n"));
++	}
++
++	return;
++}
++
++int
++dhd_pno_lock_batch_results(dhd_pub_t *dhd)
++{
++	dhd_pno_status_info_t *_pno_state;
++	int err = BCME_OK;
++
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	mutex_lock(&_pno_state->pno_mutex);
++	return err;
++}
++
++void
++dhd_pno_unlock_batch_results(dhd_pub_t *dhd)
++{
++	dhd_pno_status_info_t *_pno_state;
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	mutex_unlock(&_pno_state->pno_mutex);
++	return;
++}
++
++int
++dhd_wait_batch_results_complete(dhd_pub_t *dhd)
++{
++	dhd_pno_status_info_t *_pno_state;
++	dhd_pno_params_t *_params;
++	int err = BCME_OK;
++
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++
++	/* Has the workqueue finished its job already?? */
++	if (_params->params_gscan.get_batch_flag == GSCAN_BATCH_RETRIEVAL_IN_PROGRESS) {
++		DHD_PNO(("%s: Waiting to complete retrieval..\n", __FUNCTION__));
++		wait_event_interruptible_timeout(_pno_state->batch_get_wait,
++		     is_batch_retrieval_complete(&_params->params_gscan),
++		     msecs_to_jiffies(GSCAN_BATCH_GET_MAX_WAIT));
++	} else { /* GSCAN_BATCH_RETRIEVAL_COMPLETE */
++		gscan_results_cache_t *iter;
++		uint16 num_results = 0;
++
++		mutex_lock(&_pno_state->pno_mutex);
++		iter = _params->params_gscan.gscan_batch_cache;
++		while (iter) {
++			num_results += iter->tot_count - iter->tot_consumed;
++			iter = iter->next;
++		}
++		mutex_unlock(&_pno_state->pno_mutex);
++
++		/* All results consumed/No results cached??
++		 * Get fresh results from FW
++		 */
++		if ((_pno_state->pno_mode & DHD_PNO_GSCAN_MODE) && !num_results) {
++			DHD_PNO(("%s: No results cached, getting from FW..\n", __FUNCTION__));
++			err = dhd_retreive_batch_scan_results(dhd);
++			if (err == BCME_OK) {
++				wait_event_interruptible_timeout(_pno_state->batch_get_wait,
++				  is_batch_retrieval_complete(&_params->params_gscan),
++				  msecs_to_jiffies(GSCAN_BATCH_GET_MAX_WAIT));
++			}
++		}
++	}
++	DHD_PNO(("%s: Wait complete\n", __FUNCTION__));
++	return err;
++}
++
++static void *
++dhd_get_gscan_batch_results(dhd_pub_t *dhd, uint32 *len)
++{
++	gscan_results_cache_t *iter, *results;
++	dhd_pno_status_info_t *_pno_state;
++	dhd_pno_params_t *_params;
++	uint16 num_scan_ids = 0, num_results = 0;
++
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++
++	iter = results = _params->params_gscan.gscan_batch_cache;
++	while (iter) {
++		num_results += iter->tot_count - iter->tot_consumed;
++		num_scan_ids++;
++		iter = iter->next;
++	}
++
++	*len = ((num_results << 16) | (num_scan_ids));
++	return results;
++}
++
++void *
++dhd_pno_get_gscan(dhd_pub_t *dhd, dhd_pno_gscan_cmd_cfg_t type,
++         void *info, uint32 *len)
++{
++	void *ret = NULL;
++	dhd_pno_gscan_capabilities_t *ptr;
++	dhd_epno_params_t *epno_params;
++	dhd_pno_params_t *_params;
++	dhd_pno_status_info_t *_pno_state;
++
++	if (!dhd || !dhd->pno_state) {
++		DHD_ERROR(("NULL POINTER : %s\n", __FUNCTION__));
++		return NULL;
++	}
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++	if (!len) {
++		DHD_ERROR(("%s: len is NULL\n", __FUNCTION__));
++		return NULL;
++	}
++	switch (type) {
++		case DHD_PNO_GET_CAPABILITIES:
++			ptr = (dhd_pno_gscan_capabilities_t *)
++			kmalloc(sizeof(dhd_pno_gscan_capabilities_t), GFP_KERNEL);
++			if (!ptr)
++				break;
++			/* Hardcoding these values for now, need to get
++			 * these values from FW, will change in a later check-in
++			 */
++			ptr->max_scan_cache_size = GSCAN_MAX_AP_CACHE;
++			ptr->max_scan_buckets = GSCAN_MAX_CH_BUCKETS;
++			ptr->max_ap_cache_per_scan = GSCAN_MAX_AP_CACHE_PER_SCAN;
++			ptr->max_rssi_sample_size = PFN_SWC_RSSI_WINDOW_MAX;
++			ptr->max_scan_reporting_threshold = 100;
++			ptr->max_hotlist_aps = PFN_HOTLIST_MAX_NUM_APS;
++			ptr->max_significant_wifi_change_aps = PFN_SWC_MAX_NUM_APS;
++			ptr->max_epno_ssid_crc32 = MAX_EPNO_SSID_NUM;
++			ptr->max_epno_hidden_ssid = MAX_EPNO_HIDDEN_SSID;
++			ptr->max_white_list_ssid = MAX_WHITELIST_SSID;
++			ret = (void *)ptr;
++			*len = sizeof(dhd_pno_gscan_capabilities_t);
++			break;
++
++		case DHD_PNO_GET_BATCH_RESULTS:
++			ret = dhd_get_gscan_batch_results(dhd, len);
++			break;
++		case DHD_PNO_GET_CHANNEL_LIST:
++			if (info) {
++				uint16 ch_list[WL_NUMCHANNELS];
++				uint32 *ptr, mem_needed, i;
++				int32 err, nchan = WL_NUMCHANNELS;
++				uint32 *gscan_band = (uint32 *) info;
++				uint8 band = 0;
++
++				/* No band specified?, nothing to do */
++				if ((*gscan_band & GSCAN_BAND_MASK) == 0) {
++					DHD_PNO(("No band specified\n"));
++					*len = 0;
++					break;
++				}
++
++				/* HAL and DHD use different bits for 2.4G and
++				 * 5G in bitmap. Hence translating it here...
++				 */
++				if (*gscan_band & GSCAN_BG_BAND_MASK) {
++					band |= WLC_BAND_2G;
++				}
++				if (*gscan_band & GSCAN_A_BAND_MASK) {
++					band |= WLC_BAND_5G;
++				}
++
++				err = _dhd_pno_get_channels(dhd, ch_list, &nchan,
++				                          (band & GSCAN_ABG_BAND_MASK),
++				                          !(*gscan_band & GSCAN_DFS_MASK));
++
++				if (err < 0) {
++					DHD_ERROR(("%s: failed to get valid channel list\n",
++						__FUNCTION__));
++					*len = 0;
++				} else {
++					mem_needed = sizeof(uint32) * nchan;
++					ptr = (uint32 *) kmalloc(mem_needed, GFP_KERNEL);
++					if (!ptr) {
++						DHD_ERROR(("%s: Unable to malloc %d bytes\n",
++							__FUNCTION__, mem_needed));
++						break;
++					}
++					for (i = 0; i < nchan; i++) {
++						ptr[i] = wf_channel2mhz(ch_list[i],
++							(ch_list[i] <= CH_MAX_2G_CHANNEL?
++							WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G));
++					}
++					ret = ptr;
++					*len = mem_needed;
++				}
++			} else {
++				*len = 0;
++				DHD_ERROR(("%s: info buffer is NULL\n", __FUNCTION__));
++			}
++			break;
++		case DHD_PNO_GET_EPNO_SSID_ELEM:
++			if (_params->params_gscan.num_epno_ssid >=
++			   (MAX_EPNO_SSID_NUM + MAX_EPNO_HIDDEN_SSID)) {
++				DHD_ERROR(("Excessive number of ePNO SSIDs programmed %d\n",
++				     _params->params_gscan.num_epno_ssid));
++				return NULL;
++			}
++
++			if (!_params->params_gscan.num_epno_ssid)
++				INIT_LIST_HEAD(&_params->params_gscan.epno_ssid_list);
++
++			epno_params = kzalloc(sizeof(dhd_epno_params_t), GFP_KERNEL);
++			if (!epno_params) {
++				DHD_ERROR(("EPNO ssid: cannot alloc %zd bytes",
++				sizeof(dhd_epno_params_t)));
++				return NULL;
++			}
++			_params->params_gscan.num_epno_ssid++;
++			epno_params->index = DHD_EPNO_DEFAULT_INDEX;
++			list_add_tail(&epno_params->list, &_params->params_gscan.epno_ssid_list);
++			ret = epno_params;
++			break;
++		default:
++			DHD_ERROR(("%s: Unrecognized cmd type - %d\n", __FUNCTION__, type));
++			break;
++	}
++
++	return ret;
++
++}
++
++int
++dhd_pno_set_cfg_gscan(dhd_pub_t *dhd, dhd_pno_gscan_cmd_cfg_t type,
++    void *buf, uint8 flush)
++{
++	int err = BCME_OK;
++	dhd_pno_params_t *_params;
++	int i;
++	dhd_pno_status_info_t *_pno_state;
++
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++	mutex_lock(&_pno_state->pno_mutex);
++
++	switch (type) {
++		case DHD_PNO_BATCH_SCAN_CFG_ID:
++		{
++			gscan_batch_params_t *ptr = (gscan_batch_params_t *)buf;
++			_params->params_gscan.bestn = ptr->bestn;
++			_params->params_gscan.mscan = ptr->mscan;
++			_params->params_gscan.buffer_threshold = ptr->buffer_threshold;
++			break;
++		}
++		case DHD_PNO_GEOFENCE_SCAN_CFG_ID:
++		{
++			gscan_hotlist_scan_params_t *ptr = (gscan_hotlist_scan_params_t *)buf;
++			struct dhd_pno_bssid *_pno_bssid;
++			struct bssid_t *bssid_ptr;
++			int8 flags;
++			if (flush) {
++				dhd_pno_reset_cfg_gscan(_params, _pno_state,
++				    GSCAN_FLUSH_HOTLIST_CFG);
++			}
++
++			if (!ptr->nbssid) {
++				break;
++			}
++			if (!_params->params_gscan.nbssid_hotlist) {
++				INIT_LIST_HEAD(&_params->params_gscan.hotlist_bssid_list);
++			}
++			if ((_params->params_gscan.nbssid_hotlist +
++			          ptr->nbssid) > PFN_SWC_MAX_NUM_APS) {
++				DHD_ERROR(("Excessive number of hotlist APs programmed %d\n",
++				     (_params->params_gscan.nbssid_hotlist +
++				      ptr->nbssid)));
++				err = BCME_RANGE;
++				goto exit;
++			}
++
++			for (i = 0, bssid_ptr = ptr->bssid; i < ptr->nbssid; i++, bssid_ptr++) {
++				_pno_bssid = kzalloc(sizeof(struct dhd_pno_bssid), GFP_KERNEL);
++
++				if (!_pno_bssid) {
++					DHD_ERROR(("_pno_bssid is NULL, cannot kalloc %zd bytes",
++					       sizeof(struct dhd_pno_bssid)));
++					err = BCME_NOMEM;
++					goto exit;
++				}
++				memcpy(&_pno_bssid->macaddr, &bssid_ptr->macaddr, ETHER_ADDR_LEN);
++
++				flags = (int8) bssid_ptr->rssi_reporting_threshold;
++				_pno_bssid->flags = flags  << WL_PFN_RSSI_SHIFT;
++				list_add_tail(&_pno_bssid->list,
++				   &_params->params_gscan.hotlist_bssid_list);
++			}
++
++			_params->params_gscan.nbssid_hotlist += ptr->nbssid;
++			_params->params_gscan.lost_ap_window = ptr->lost_ap_window;
++			break;
++		}
++		case DHD_PNO_SIGNIFICANT_SCAN_CFG_ID:
++		{
++			gscan_swc_params_t *ptr = (gscan_swc_params_t *)buf;
++			dhd_pno_significant_bssid_t *_pno_significant_change_bssid;
++			wl_pfn_significant_bssid_t *significant_bssid_ptr;
++
++			if (flush) {
++				dhd_pno_reset_cfg_gscan(_params, _pno_state,
++				   GSCAN_FLUSH_SIGNIFICANT_CFG);
++			}
++
++			if (!ptr->nbssid) {
++				break;
++			}
++			if (!_params->params_gscan.nbssid_significant_change) {
++				INIT_LIST_HEAD(&_params->params_gscan.significant_bssid_list);
++			}
++			if ((_params->params_gscan.nbssid_significant_change +
++			          ptr->nbssid) > PFN_SWC_MAX_NUM_APS) {
++				DHD_ERROR(("Excessive number of SWC APs programmed %d\n",
++				     (_params->params_gscan.nbssid_significant_change +
++				      ptr->nbssid)));
++				err = BCME_RANGE;
++				goto exit;
++			}
++
++			for (i = 0, significant_bssid_ptr = ptr->bssid_elem_list;
++			     i < ptr->nbssid; i++, significant_bssid_ptr++) {
++				_pno_significant_change_bssid =
++				      kzalloc(sizeof(dhd_pno_significant_bssid_t),
++				      GFP_KERNEL);
++
++				if (!_pno_significant_change_bssid) {
++					DHD_ERROR(("SWC bssidptr is NULL, cannot kalloc %zd bytes",
++					sizeof(dhd_pno_significant_bssid_t)));
++					err = BCME_NOMEM;
++					goto exit;
++				}
++				memcpy(&_pno_significant_change_bssid->BSSID,
++				    &significant_bssid_ptr->macaddr, ETHER_ADDR_LEN);
++				_pno_significant_change_bssid->rssi_low_threshold =
++				    significant_bssid_ptr->rssi_low_threshold;
++				_pno_significant_change_bssid->rssi_high_threshold =
++				    significant_bssid_ptr->rssi_high_threshold;
++				list_add_tail(&_pno_significant_change_bssid->list,
++				    &_params->params_gscan.significant_bssid_list);
++			}
++
++			_params->params_gscan.swc_nbssid_threshold = ptr->swc_threshold;
++			_params->params_gscan.swc_rssi_window_size = ptr->rssi_window;
++			_params->params_gscan.lost_ap_window = ptr->lost_ap_window;
++			_params->params_gscan.nbssid_significant_change += ptr->nbssid;
++			break;
++		}
++		case DHD_PNO_SCAN_CFG_ID:
++		{
++			int i, k;
++			uint16 band;
++			gscan_scan_params_t *ptr = (gscan_scan_params_t *)buf;
++			struct dhd_pno_gscan_channel_bucket *ch_bucket;
++
++			if (ptr->nchannel_buckets <= GSCAN_MAX_CH_BUCKETS) {
++				_params->params_gscan.nchannel_buckets = ptr->nchannel_buckets;
++
++				memcpy(_params->params_gscan.channel_bucket, ptr->channel_bucket,
++				    _params->params_gscan.nchannel_buckets *
++				    sizeof(struct dhd_pno_gscan_channel_bucket));
++				ch_bucket = _params->params_gscan.channel_bucket;
++
++				for (i = 0; i < ptr->nchannel_buckets; i++) {
++					band = ch_bucket[i].band;
++					for (k = 0; k < ptr->channel_bucket[i].num_channels; k++)  {
++						ch_bucket[i].chan_list[k] =
++						wf_mhz2channel(ptr->channel_bucket[i].chan_list[k],
++							0);
++					}
++					ch_bucket[i].band = 0;
++					/* HAL and DHD use different bits for 2.4G and
++					 * 5G in bitmap. Hence translating it here...
++					 */
++					if (band & GSCAN_BG_BAND_MASK)
++						ch_bucket[i].band |= WLC_BAND_2G;
++					if (band & GSCAN_A_BAND_MASK)
++						ch_bucket[i].band |= WLC_BAND_5G;
++					if (band & GSCAN_DFS_MASK)
++						ch_bucket[i].band |= GSCAN_DFS_MASK;
++
++					DHD_PNO(("band %d report_flag %d\n", ch_bucket[i].band,
++					          ch_bucket[i].report_flag));
++				}
++
++				for (i = 0; i < ptr->nchannel_buckets; i++) {
++					ch_bucket[i].bucket_freq_multiple =
++					ch_bucket[i].bucket_freq_multiple/ptr->scan_fr;
++					ch_bucket[i].bucket_max_multiple =
++					ch_bucket[i].bucket_max_multiple/ptr->scan_fr;
++					DHD_PNO(("mult %d max_mult %d\n",
++						ch_bucket[i].bucket_freq_multiple,
++						ch_bucket[i].bucket_max_multiple));
++				}
++				_params->params_gscan.scan_fr = ptr->scan_fr;
++
++				DHD_PNO(("num_buckets %d scan_fr %d\n", ptr->nchannel_buckets,
++				        _params->params_gscan.scan_fr));
++			} else {
++				err = BCME_BADARG;
++			}
++			break;
++		}
++	case DHD_PNO_EPNO_CFG_ID:
++		if (flush) {
++			dhd_pno_reset_cfg_gscan(_params, _pno_state,
++			   GSCAN_FLUSH_EPNO_CFG);
++		} else {
++			_params->params_gscan.num_visible_epno_ssid += *((uint16 *)buf);
++		}
++		break;
++		default:
++			err = BCME_BADARG;
++			DHD_ERROR(("%s: Unrecognized cmd type - %d\n", __FUNCTION__, type));
++			break;
++	}
++exit:
++	mutex_unlock(&_pno_state->pno_mutex);
++	return err;
++
++}
++
++
++static bool
++validate_gscan_params(struct dhd_pno_gscan_params *gscan_params)
++{
++	unsigned int i, k;
++
++	if (!gscan_params->scan_fr || !gscan_params->nchannel_buckets) {
++		DHD_ERROR(("%s : Scan freq - %d or number of channel buckets - %d is empty\n",
++		 __FUNCTION__, gscan_params->scan_fr, gscan_params->nchannel_buckets));
++		return false;
++	}
++
++	for (i = 0; i < gscan_params->nchannel_buckets; i++) {
++		if (!gscan_params->channel_bucket[i].band) {
++			for (k = 0; k < gscan_params->channel_bucket[i].num_channels; k++) {
++				if (gscan_params->channel_bucket[i].chan_list[k] > CHANNEL_5G_MAX) {
++					DHD_ERROR(("%s : Unknown channel %d\n", __FUNCTION__,
++					 gscan_params->channel_bucket[i].chan_list[k]));
++					return false;
++				}
++			}
++		}
++	}
++
++	return true;
++}
++
++static int
++dhd_pno_set_for_gscan(dhd_pub_t *dhd, struct dhd_pno_gscan_params *gscan_params)
++{
++	int err = BCME_OK;
++	int mode, i = 0, k;
++	uint16 _chan_list[WL_NUMCHANNELS];
++	int tot_nchan = 0;
++	int num_buckets_to_fw, tot_num_buckets, gscan_param_size = 0;
++	dhd_pno_status_info_t *_pno_state = PNO_GET_PNOSTATE(dhd);
++	wl_pfn_gscan_ch_bucket_cfg_t *ch_bucket = NULL;
++	wl_pfn_gscan_cfg_t *pfn_gscan_cfg_t = NULL;
++	wl_pfn_significant_bssid_t *p_pfn_significant_bssid = NULL;
++	wl_pfn_bssid_t *p_pfn_bssid = NULL;
++	wlc_ssid_ext_t *pssid_list = NULL;
++	dhd_pno_params_t	*params_legacy;
++	dhd_pno_params_t	*_params;
++
++	params_legacy = &_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS];
++	_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	NULL_CHECK(gscan_params, "gscan_params is NULL", err);
++
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	if (!dhd_support_sta_mode(dhd)) {
++		err = BCME_BADOPTION;
++		goto exit;
++	}
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n", __FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++	if (!validate_gscan_params(gscan_params)) {
++		DHD_ERROR(("%s : Cannot start gscan - bad params\n", __FUNCTION__));
++		err = BCME_BADARG;
++		goto exit;
++	}
++	/* Create channel list based on channel buckets */
++	if (!(ch_bucket = dhd_pno_gscan_create_channel_list(dhd, _pno_state,
++	    _chan_list, &tot_num_buckets, &num_buckets_to_fw))) {
++		goto exit;
++	}
++
++	mutex_lock(&_pno_state->pno_mutex);
++	/* Clear any pre-existing results in our cache
++	 * not consumed by framework
++	 */
++	dhd_gscan_clear_all_batch_results(dhd);
++	if (_pno_state->pno_mode & (DHD_PNO_GSCAN_MODE | DHD_PNO_LEGACY_MODE)) {
++		/* store current pno_mode before disabling pno */
++		mode = _pno_state->pno_mode;
++		err = dhd_pno_clean(dhd);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to disable PNO\n", __FUNCTION__));
++			mutex_unlock(&_pno_state->pno_mutex);
++			goto exit;
++		}
++		/* restore the previous mode */
++		_pno_state->pno_mode = mode;
++	}
++	_pno_state->pno_mode |= DHD_PNO_GSCAN_MODE;
++	mutex_unlock(&_pno_state->pno_mutex);
++
++	if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) {
++		pssid_list = dhd_pno_get_legacy_pno_ssid(dhd, _pno_state);
++
++		if (!pssid_list) {
++			err = BCME_NOMEM;
++			DHD_ERROR(("failed to get Legacy PNO SSID list\n"));
++			goto exit;
++		}
++
++		if ((err = _dhd_pno_add_ssid(dhd, pssid_list,
++			params_legacy->params_legacy.nssid)) < 0) {
++			DHD_ERROR(("failed to add ssid list (err %d) in firmware\n", err));
++			goto exit;
++		}
++	}
++
++	if ((err = _dhd_pno_set(dhd, _params, DHD_PNO_GSCAN_MODE)) < 0) {
++		DHD_ERROR(("failed to set call pno_set (err %d) in firmware\n", err));
++		goto exit;
++	}
++
++	gscan_param_size = sizeof(wl_pfn_gscan_cfg_t) +
++	          (num_buckets_to_fw - 1) * sizeof(wl_pfn_gscan_ch_bucket_cfg_t);
++	pfn_gscan_cfg_t = (wl_pfn_gscan_cfg_t *) MALLOC(dhd->osh, gscan_param_size);
++
++	if (!pfn_gscan_cfg_t) {
++		DHD_ERROR(("%s: failed to malloc memory of size %d\n",
++		   __FUNCTION__, gscan_param_size));
++		err = BCME_NOMEM;
++		goto exit;
++	}
++
++	pfn_gscan_cfg_t->version = WL_GSCAN_CFG_VERSION;
++	if (gscan_params->mscan) {
++		pfn_gscan_cfg_t->buffer_threshold = gscan_params->buffer_threshold;
++	} else {
++		pfn_gscan_cfg_t->buffer_threshold = GSCAN_BATCH_NO_THR_SET;
++	}
++	if (gscan_params->nbssid_significant_change) {
++		pfn_gscan_cfg_t->swc_nbssid_threshold = gscan_params->swc_nbssid_threshold;
++		pfn_gscan_cfg_t->swc_rssi_window_size = gscan_params->swc_rssi_window_size;
++		pfn_gscan_cfg_t->lost_ap_window	= gscan_params->lost_ap_window;
++	} else {
++		pfn_gscan_cfg_t->swc_nbssid_threshold = 0;
++		pfn_gscan_cfg_t->swc_rssi_window_size = 0;
++		pfn_gscan_cfg_t->lost_ap_window	= 0;
++	}
++
++	pfn_gscan_cfg_t->flags =
++	         (gscan_params->send_all_results_flag & GSCAN_SEND_ALL_RESULTS_MASK);
++	pfn_gscan_cfg_t->count_of_channel_buckets = num_buckets_to_fw;
++	pfn_gscan_cfg_t->retry_threshold = GSCAN_RETRY_THRESHOLD;
++
++	for (i = 0, k = 0; i < tot_num_buckets; i++) {
++		if (ch_bucket[i].bucket_end_index  != CHANNEL_BUCKET_EMPTY_INDEX) {
++			pfn_gscan_cfg_t->channel_bucket[k].bucket_end_index =
++			           ch_bucket[i].bucket_end_index;
++			pfn_gscan_cfg_t->channel_bucket[k].bucket_freq_multiple =
++			           ch_bucket[i].bucket_freq_multiple;
++			pfn_gscan_cfg_t->channel_bucket[k].max_freq_multiple =
++			           ch_bucket[i].max_freq_multiple;
++			pfn_gscan_cfg_t->channel_bucket[k].repeat =
++			           ch_bucket[i].repeat;
++			pfn_gscan_cfg_t->channel_bucket[k].flag =
++			           ch_bucket[i].flag;
++			k++;
++		}
++	}
++
++	tot_nchan = pfn_gscan_cfg_t->channel_bucket[num_buckets_to_fw - 1].bucket_end_index + 1;
++	DHD_PNO(("Total channel num %d total ch_buckets  %d ch_buckets_to_fw %d \n", tot_nchan,
++	      tot_num_buckets, num_buckets_to_fw));
++
++	if ((err = _dhd_pno_cfg(dhd, _chan_list, tot_nchan)) < 0) {
++		DHD_ERROR(("%s : failed to set call pno_cfg (err %d) in firmware\n",
++			__FUNCTION__, err));
++		goto exit;
++	}
++
++	if ((err = _dhd_pno_gscan_cfg(dhd, pfn_gscan_cfg_t, gscan_param_size)) < 0) {
++		DHD_ERROR(("%s : failed to set call pno_gscan_cfg (err %d) in firmware\n",
++			__FUNCTION__, err));
++		goto exit;
++	}
++	if (gscan_params->nbssid_significant_change) {
++		dhd_pno_significant_bssid_t *iter, *next;
++
++		p_pfn_significant_bssid = kzalloc(sizeof(wl_pfn_significant_bssid_t) *
++		                   gscan_params->nbssid_significant_change, GFP_KERNEL);
++		if (p_pfn_significant_bssid == NULL) {
++			DHD_ERROR(("%s : failed to allocate memory %zd\n",
++				__FUNCTION__,
++				sizeof(wl_pfn_significant_bssid_t) *
++				gscan_params->nbssid_significant_change));
++			err = BCME_NOMEM;
++			goto exit;
++		}
++		i = 0;
++		/* convert dhd_pno_significant_bssid_t to wl_pfn_significant_bssid_t */
++		list_for_each_entry_safe(iter, next, &gscan_params->significant_bssid_list, list) {
++			p_pfn_significant_bssid[i].rssi_low_threshold = iter->rssi_low_threshold;
++			p_pfn_significant_bssid[i].rssi_high_threshold = iter->rssi_high_threshold;
++			memcpy(&p_pfn_significant_bssid[i].macaddr, &iter->BSSID, ETHER_ADDR_LEN);
++			i++;
++		}
++		DHD_PNO(("nbssid_significant_change %d \n",
++				gscan_params->nbssid_significant_change));
++		err = _dhd_pno_add_significant_bssid(dhd, p_pfn_significant_bssid,
++		                     gscan_params->nbssid_significant_change);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call _dhd_pno_add_significant_bssid(err :%d)\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++	}
++
++	if (gscan_params->nbssid_hotlist) {
++		struct dhd_pno_bssid *iter, *next;
++		wl_pfn_bssid_t *ptr;
++		p_pfn_bssid = (wl_pfn_bssid_t *)kzalloc(sizeof(wl_pfn_bssid_t) *
++		       gscan_params->nbssid_hotlist, GFP_KERNEL);
++		if (p_pfn_bssid == NULL) {
++			DHD_ERROR(("%s : failed to allocate wl_pfn_bssid_t array"
++			" (count: %d)",
++				__FUNCTION__, _params->params_hotlist.nbssid));
++			err = BCME_NOMEM;
++			_pno_state->pno_mode &= ~DHD_PNO_HOTLIST_MODE;
++			goto exit;
++		}
++		ptr = p_pfn_bssid;
++		/* convert dhd_pno_bssid to wl_pfn_bssid */
++		DHD_PNO(("nhotlist %d\n", gscan_params->nbssid_hotlist));
++		list_for_each_entry_safe(iter, next,
++		          &gscan_params->hotlist_bssid_list, list) {
++			memcpy(&ptr->macaddr,
++			&iter->macaddr, ETHER_ADDR_LEN);
++			ptr->flags = iter->flags;
++			ptr++;
++		}
++
++		err = _dhd_pno_add_bssid(dhd, p_pfn_bssid, gscan_params->nbssid_hotlist);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call _dhd_pno_add_bssid(err :%d)\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++	}
++
++	if (gscan_params->num_epno_ssid > 0) {
++		DHD_ERROR(("num_epno_ssid %d\n", gscan_params->num_epno_ssid));
++		err = dhd_epno_set_ssid(dhd, _pno_state);
++		if (err  < 0) {
++			DHD_ERROR(("failed to add ssid list (err %d) in firmware\n", err));
++			goto exit;
++		}
++	}
++
++	if ((err = _dhd_pno_enable(dhd, PNO_ON)) < 0) {
++		DHD_ERROR(("%s : failed to enable PNO err %d\n", __FUNCTION__, err));
++	}
++
++exit:
++	/* clear mode in case of error */
++	if (err < 0) {
++		int ret = dhd_pno_clean(dhd);
++
++		if (ret < 0) {
++			DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++				__FUNCTION__, ret));
++		} else {
++			_pno_state->pno_mode &= ~DHD_PNO_GSCAN_MODE;
++		}
++	}
++	kfree(pssid_list);
++	kfree(p_pfn_significant_bssid);
++	kfree(p_pfn_bssid);
++	if (pfn_gscan_cfg_t) {
++		MFREE(dhd->osh, pfn_gscan_cfg_t, gscan_param_size);
++	}
++	if (ch_bucket) {
++		MFREE(dhd->osh, ch_bucket,
++		(tot_num_buckets * sizeof(wl_pfn_gscan_ch_bucket_cfg_t)));
++	}
++	return err;
++
++}
++
++static wl_pfn_gscan_ch_bucket_cfg_t *
++dhd_pno_gscan_create_channel_list(dhd_pub_t *dhd,
++                                  dhd_pno_status_info_t *_pno_state,
++                                  uint16 *chan_list,
++                                  uint32 *num_buckets,
++                                  uint32 *num_buckets_to_fw)
++{
++	int i, num_channels, err, nchan = WL_NUMCHANNELS, ch_cnt;
++	uint16 *ptr = chan_list, max;
++	wl_pfn_gscan_ch_bucket_cfg_t *ch_bucket;
++	dhd_pno_params_t *_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++	bool is_pno_legacy_running = _pno_state->pno_mode & DHD_PNO_LEGACY_MODE;
++	dhd_pno_gscan_channel_bucket_t *gscan_buckets = _params->params_gscan.channel_bucket;
++
++	if (is_pno_legacy_running)
++		*num_buckets = _params->params_gscan.nchannel_buckets + 1;
++	 else
++		*num_buckets = _params->params_gscan.nchannel_buckets;
++
++	*num_buckets_to_fw = 0;
++
++	ch_bucket = (wl_pfn_gscan_ch_bucket_cfg_t *) MALLOC(dhd->osh,
++	   ((*num_buckets) * sizeof(wl_pfn_gscan_ch_bucket_cfg_t)));
++
++	if (!ch_bucket) {
++		DHD_ERROR(("%s: failed to malloc memory of size %zd\n",
++			__FUNCTION__, (*num_buckets) * sizeof(wl_pfn_gscan_ch_bucket_cfg_t)));
++		*num_buckets_to_fw = *num_buckets = 0;
++		return NULL;
++	}
++
++	max = gscan_buckets[0].bucket_freq_multiple;
++	num_channels = 0;
++	/* nchan is the remaining space left in chan_list buffer
++	 * So any overflow list of channels is ignored
++	 */
++	for (i = 0; i < _params->params_gscan.nchannel_buckets && nchan; i++) {
++		if (!gscan_buckets[i].band) {
++			ch_cnt = MIN(gscan_buckets[i].num_channels, (uint8)nchan);
++			num_channels += ch_cnt;
++			memcpy(ptr, gscan_buckets[i].chan_list,
++			    ch_cnt * sizeof(uint16));
++			ptr = ptr + ch_cnt;
++		} else {
++			/* get a valid channel list based on band B or A */
++			err = _dhd_pno_get_channels(dhd, ptr,
++			        &nchan, (gscan_buckets[i].band & GSCAN_ABG_BAND_MASK),
++			        !(gscan_buckets[i].band & GSCAN_DFS_MASK));
++
++			if (err < 0) {
++				DHD_ERROR(("%s: failed to get valid channel list(band : %d)\n",
++					__FUNCTION__, gscan_buckets[i].band));
++				MFREE(dhd->osh, ch_bucket,
++				      ((*num_buckets) * sizeof(wl_pfn_gscan_ch_bucket_cfg_t)));
++				*num_buckets_to_fw = *num_buckets = 0;
++				return NULL;
++			}
++
++			num_channels += nchan;
++			ptr = ptr + nchan;
++		}
++
++		ch_bucket[i].bucket_end_index = num_channels - 1;
++		ch_bucket[i].bucket_freq_multiple = gscan_buckets[i].bucket_freq_multiple;
++		ch_bucket[i].repeat = gscan_buckets[i].repeat;
++		ch_bucket[i].max_freq_multiple = gscan_buckets[i].bucket_max_multiple;
++		ch_bucket[i].flag = gscan_buckets[i].report_flag;
++		/* HAL and FW interpretations are opposite for this bit */
++		ch_bucket[i].flag ^= DHD_PNO_REPORT_NO_BATCH;
++		if (max < gscan_buckets[i].bucket_freq_multiple)
++			max = gscan_buckets[i].bucket_freq_multiple;
++		nchan = WL_NUMCHANNELS - num_channels;
++		*num_buckets_to_fw = *num_buckets_to_fw + 1;
++		DHD_PNO(("end_idx  %d freq_mult - %d\n",
++		ch_bucket[i].bucket_end_index, ch_bucket[i].bucket_freq_multiple));
++	}
++
++	_params->params_gscan.max_ch_bucket_freq = max;
++	/* Legacy PNO maybe running, which means we need to create a legacy PNO bucket
++	 * Get GCF of Legacy PNO and Gscan scanfreq
++	 */
++	if (is_pno_legacy_running) {
++		dhd_pno_params_t *_params1 = &_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS];
++		uint16 *legacy_chan_list = _params1->params_legacy.chan_list;
++		uint16 common_freq;
++		uint32 legacy_bucket_idx = _params->params_gscan.nchannel_buckets;
++		/* If no space is left then only gscan buckets will be sent to FW */
++		if (nchan) {
++			common_freq = gcd(_params->params_gscan.scan_fr,
++					_params1->params_legacy.scan_fr);
++			max = gscan_buckets[0].bucket_freq_multiple;
++			/* GSCAN buckets */
++			for (i = 0; i < _params->params_gscan.nchannel_buckets; i++) {
++				ch_bucket[i].bucket_freq_multiple *= _params->params_gscan.scan_fr;
++				ch_bucket[i].bucket_freq_multiple /= common_freq;
++				if (max < gscan_buckets[i].bucket_freq_multiple)
++					max = gscan_buckets[i].bucket_freq_multiple;
++			}
++			/* Legacy PNO bucket */
++			ch_bucket[legacy_bucket_idx].bucket_freq_multiple =
++					_params1->params_legacy.scan_fr;
++			ch_bucket[legacy_bucket_idx].bucket_freq_multiple /=
++					common_freq;
++			_params->params_gscan.max_ch_bucket_freq = MAX(max,
++				ch_bucket[legacy_bucket_idx].bucket_freq_multiple);
++			ch_bucket[legacy_bucket_idx].flag = CH_BUCKET_REPORT_REGULAR;
++			/* Now add channels to the legacy scan bucket */
++			for (i = 0; i < _params1->params_legacy.nchan && nchan; i++, nchan--) {
++				ptr[i] = legacy_chan_list[i];
++				num_channels++;
++			}
++			ch_bucket[legacy_bucket_idx].bucket_end_index = num_channels - 1;
++			*num_buckets_to_fw = *num_buckets_to_fw + 1;
++			DHD_PNO(("end_idx  %d freq_mult - %d\n",
++					ch_bucket[legacy_bucket_idx].bucket_end_index,
++					ch_bucket[legacy_bucket_idx].bucket_freq_multiple));
++		}
++	}
++	return ch_bucket;
++}
++
++static int
++dhd_pno_stop_for_gscan(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	int mode;
++	dhd_pno_status_info_t *_pno_state;
++	wlc_ssid_ext_t *pssid_list = NULL;
++
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	if (!dhd_support_sta_mode(dhd)) {
++		err = BCME_BADOPTION;
++		goto exit;
++	}
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n",
++			__FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++	if (!(_pno_state->pno_mode & DHD_PNO_GSCAN_MODE)) {
++		DHD_ERROR(("%s : GSCAN is not enabled\n", __FUNCTION__));
++		goto exit;
++	}
++	if (_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS].params_gscan.mscan) {
++		/* retrieve the batching data from firmware into host */
++		err = dhd_wait_batch_results_complete(dhd);
++		if (err != BCME_OK)
++			goto exit;
++	}
++	mutex_lock(&_pno_state->pno_mutex);
++	mode = _pno_state->pno_mode & ~DHD_PNO_GSCAN_MODE;
++	err = dhd_pno_clean(dhd);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++			__FUNCTION__, err));
++		mutex_unlock(&_pno_state->pno_mutex);
++		return err;
++	}
++	_pno_state->pno_mode = mode;
++	mutex_unlock(&_pno_state->pno_mutex);
++	_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS].params_gscan.ssid_ext_last_used_index = 0;
++
++	/* Reprogram Legacy PNO if it was running */
++	if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) {
++		struct dhd_pno_legacy_params *params_legacy;
++		uint16 chan_list[WL_NUMCHANNELS];
++
++		params_legacy = &(_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS].params_legacy);
++		_pno_state->pno_mode &= ~DHD_PNO_LEGACY_MODE;
++		pssid_list = dhd_pno_get_legacy_pno_ssid(dhd, _pno_state);
++		if (!pssid_list) {
++			err = BCME_NOMEM;
++			DHD_ERROR(("failed to get Legacy PNO SSID list\n"));
++			goto exit;
++		}
++
++		DHD_PNO(("Restarting Legacy PNO SSID scan...\n"));
++		memcpy(chan_list, params_legacy->chan_list,
++		    (params_legacy->nchan * sizeof(uint16)));
++		err = dhd_pno_set_for_ssid(dhd, pssid_list, params_legacy->nssid,
++			params_legacy->scan_fr, params_legacy->pno_repeat,
++			params_legacy->pno_freq_expo_max, chan_list,
++			params_legacy->nchan);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to restart legacy PNO scan(err: %d)\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++
++	}
++
++exit:
++	kfree(pssid_list);
++	return err;
++}
++
++int
++dhd_pno_initiate_gscan_request(dhd_pub_t *dhd, bool run, bool flush)
++{
++	int err = BCME_OK;
++	dhd_pno_params_t *params;
++	dhd_pno_status_info_t *_pno_state;
++	struct dhd_pno_gscan_params *gscan_params;
++
++	NULL_CHECK(dhd, "dhd is NULL\n", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++
++	DHD_PNO(("%s enter - run %d flush %d\n", __FUNCTION__, run, flush));
++
++	params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++	gscan_params = &params->params_gscan;
++
++	if (run) {
++		err = dhd_pno_set_for_gscan(dhd, gscan_params);
++	} else {
++		if (flush) {
++			mutex_lock(&_pno_state->pno_mutex);
++			dhd_pno_reset_cfg_gscan(params, _pno_state, GSCAN_FLUSH_ALL_CFG);
++			mutex_unlock(&_pno_state->pno_mutex);
++		}
++		/* Need to stop all gscan */
++		err = dhd_pno_stop_for_gscan(dhd);
++	}
++
++	return err;
++}
++
++int
++dhd_pno_enable_full_scan_result(dhd_pub_t *dhd, bool real_time_flag)
++{
++	int err = BCME_OK;
++	dhd_pno_params_t *params;
++	dhd_pno_status_info_t *_pno_state;
++	struct dhd_pno_gscan_params *gscan_params;
++	uint8 old_flag;
++
++	NULL_CHECK(dhd, "dhd is NULL\n", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n", __FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++	params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++	gscan_params = &params->params_gscan;
++
++	mutex_lock(&_pno_state->pno_mutex);
++
++	old_flag = gscan_params->send_all_results_flag;
++	gscan_params->send_all_results_flag = (uint8) real_time_flag;
++	if (_pno_state->pno_mode & DHD_PNO_GSCAN_MODE) {
++	    if (old_flag != gscan_params->send_all_results_flag) {
++			wl_pfn_gscan_cfg_t gscan_cfg;
++			gscan_cfg.version = WL_GSCAN_CFG_VERSION;
++			gscan_cfg.flags = (gscan_params->send_all_results_flag &
++				GSCAN_SEND_ALL_RESULTS_MASK);
++			gscan_cfg.flags |= GSCAN_CFG_FLAGS_ONLY_MASK;
++
++			if ((err = _dhd_pno_gscan_cfg(dhd, &gscan_cfg,
++				sizeof(wl_pfn_gscan_cfg_t))) < 0) {
++				DHD_ERROR(("%s : pno_gscan_cfg failed (err %d) in firmware\n",
++					__FUNCTION__, err));
++				goto exit_mutex_unlock;
++			}
++		} else {
++			DHD_PNO(("No change in flag - %d\n", old_flag));
++		}
++	} else {
++		DHD_PNO(("Gscan not started\n"));
++	}
++exit_mutex_unlock:
++	mutex_unlock(&_pno_state->pno_mutex);
++exit:
++	return err;
++}
++
++/* Cleanup any consumed results
++ * Return TRUE if all results consumed, else FALSE
++ */
++int dhd_gscan_batch_cache_cleanup(dhd_pub_t *dhd)
++{
++	int ret = 0;
++	dhd_pno_params_t *params;
++	struct dhd_pno_gscan_params *gscan_params;
++	dhd_pno_status_info_t *_pno_state;
++	gscan_results_cache_t *iter, *tmp;
++
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++	gscan_params = &params->params_gscan;
++	iter = gscan_params->gscan_batch_cache;
++
++	while (iter) {
++		if (iter->tot_consumed == iter->tot_count) {
++			tmp = iter->next;
++			kfree(iter);
++			iter = tmp;
++		} else
++			break;
++	}
++	gscan_params->gscan_batch_cache = iter;
++	ret = (iter == NULL);
++	return ret;
++}
++
++static int
++_dhd_pno_get_gscan_batch_from_fw(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	uint32 timestamp = 0, ts = 0, i, j, timediff;
++	dhd_pno_params_t *params;
++	dhd_pno_status_info_t *_pno_state;
++	wl_pfn_lnet_info_t *plnetinfo;
++	struct dhd_pno_gscan_params *gscan_params;
++	wl_pfn_lscanresults_t *plbestnet = NULL;
++	gscan_results_cache_t *iter, *tail;
++	wifi_gscan_result_t *result;
++	uint8 *nAPs_per_scan = NULL;
++	uint8 num_scans_in_cur_iter;
++	uint16 count;
++
++	NULL_CHECK(dhd, "dhd is NULL\n", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n", __FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++	if (!(_pno_state->pno_mode & DHD_PNO_GSCAN_MODE)) {
++		DHD_ERROR(("%s: GSCAN is not enabled\n", __FUNCTION__));
++		goto exit;
++	}
++	gscan_params = &params->params_gscan;
++	nAPs_per_scan = (uint8 *) MALLOC(dhd->osh, gscan_params->mscan);
++
++	if (!nAPs_per_scan) {
++		DHD_ERROR(("%s :Out of memory!! Cant malloc %d bytes\n", __FUNCTION__,
++		gscan_params->mscan));
++		err = BCME_NOMEM;
++		goto exit;
++	}
++
++	plbestnet = (wl_pfn_lscanresults_t *)MALLOC(dhd->osh, PNO_BESTNET_LEN);
++
++	mutex_lock(&_pno_state->pno_mutex);
++
++	dhd_gscan_clear_all_batch_results(dhd);
++
++	if (!(_pno_state->pno_mode & DHD_PNO_GSCAN_MODE)) {
++		DHD_ERROR(("%s : GSCAN is not enabled\n", __FUNCTION__));
++		goto exit_mutex_unlock;
++	}
++
++	timediff = gscan_params->scan_fr * 1000;
++	timediff = timediff >> 1;
++
++	/* Ok, now lets start getting results from the FW */
++	plbestnet->status = PFN_INCOMPLETE;
++	tail = gscan_params->gscan_batch_cache;
++	while (plbestnet->status != PFN_COMPLETE) {
++		memset(plbestnet, 0, PNO_BESTNET_LEN);
++		err = dhd_iovar(dhd, 0, "pfnlbest", NULL, 0, (char *)plbestnet, PNO_BESTNET_LEN,
++			FALSE);
++		if (err < 0) {
++			DHD_ERROR(("%s : Cannot get all the batch results, err :%d\n",
++				__FUNCTION__, err));
++			goto exit_mutex_unlock;
++		}
++		DHD_PNO(("ver %d, status : %d, count %d\n", plbestnet->version,
++			plbestnet->status, plbestnet->count));
++		if (plbestnet->version != PFN_SCANRESULT_VERSION) {
++			err = BCME_VERSION;
++			DHD_ERROR(("bestnet version(%d) is mismatch with Driver version(%d)\n",
++				plbestnet->version, PFN_SCANRESULT_VERSION));
++			goto exit_mutex_unlock;
++		}
++		if (plbestnet->count == 0) {
++			DHD_PNO(("No more batch results\n"));
++			goto exit_mutex_unlock;
++		}
++		num_scans_in_cur_iter = 0;
++		timestamp = plbestnet->netinfo[0].timestamp;
++		/* find out how many scans' results did we get in this batch of FW results */
++		for (i = 0, count = 0; i < plbestnet->count; i++, count++) {
++			plnetinfo = &plbestnet->netinfo[i];
++			/* Unlikely to happen, but just in case the results from
++			 * FW doesnt make sense..... Assume its part of one single scan
++			 */
++			if (num_scans_in_cur_iter > gscan_params->mscan) {
++				num_scans_in_cur_iter = 0;
++				count = plbestnet->count;
++				break;
++			}
++			if (TIME_DIFF_MS(timestamp, plnetinfo->timestamp) > timediff) {
++				nAPs_per_scan[num_scans_in_cur_iter] = count;
++				count = 0;
++				num_scans_in_cur_iter++;
++			}
++			timestamp = plnetinfo->timestamp;
++		}
++		nAPs_per_scan[num_scans_in_cur_iter] = count;
++		num_scans_in_cur_iter++;
++
++		DHD_PNO(("num_scans_in_cur_iter %d\n", num_scans_in_cur_iter));
++		plnetinfo = &plbestnet->netinfo[0];
++
++		for (i = 0; i < num_scans_in_cur_iter; i++) {
++			iter = (gscan_results_cache_t *)
++			kmalloc(((nAPs_per_scan[i] - 1) * sizeof(wifi_gscan_result_t)) +
++			              sizeof(gscan_results_cache_t), GFP_KERNEL);
++			if (!iter) {
++				DHD_ERROR(("%s :Out of memory!! Cant malloc %d bytes\n",
++				 __FUNCTION__, gscan_params->mscan));
++				err = BCME_NOMEM;
++				goto exit_mutex_unlock;
++			}
++			/* Need this check because the new set of results from FW
++			 * maybe a continuation of previous sets' scan results
++			 */
++			if (TIME_DIFF_MS(ts, plnetinfo->timestamp) > timediff) {
++				iter->scan_id = ++gscan_params->scan_id;
++			} else {
++				iter->scan_id = gscan_params->scan_id;
++			}
++			DHD_PNO(("scan_id %d tot_count %d\n", gscan_params->scan_id,
++			      nAPs_per_scan[i]));
++			iter->tot_count = nAPs_per_scan[i];
++			iter->tot_consumed = 0;
++			iter->flag = 0;
++			if (plnetinfo->flags & PFN_PARTIAL_SCAN_MASK) {
++				DHD_PNO(("This scan is aborted\n"));
++				iter->flag = (ENABLE << PNO_STATUS_ABORT);
++			} else if (gscan_params->reason) {
++				iter->flag = (ENABLE << gscan_params->reason);
++			}
++
++			if (!tail) {
++				gscan_params->gscan_batch_cache = iter;
++			} else {
++				tail->next = iter;
++			}
++			tail = iter;
++			iter->next = NULL;
++			for (j = 0; j < nAPs_per_scan[i]; j++, plnetinfo++) {
++				result = &iter->results[j];
++
++				result->channel = wf_channel2mhz(plnetinfo->pfnsubnet.channel,
++					(plnetinfo->pfnsubnet.channel <= CH_MAX_2G_CHANNEL?
++					WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G));
++				result->rssi = (int32) plnetinfo->RSSI;
++				/* Info not available & not expected */
++				result->beacon_period = 0;
++				result->capability = 0;
++				result->ie_length = 0;
++				result->rtt = (uint64) plnetinfo->rtt0;
++				result->rtt_sd = (uint64) plnetinfo->rtt1;
++				result->ts = convert_fw_rel_time_to_systime(plnetinfo->timestamp);
++				ts = plnetinfo->timestamp;
++				if (plnetinfo->pfnsubnet.SSID_len > DOT11_MAX_SSID_LEN) {
++					DHD_ERROR(("%s: Invalid SSID length %d\n",
++					      __FUNCTION__, plnetinfo->pfnsubnet.SSID_len));
++					plnetinfo->pfnsubnet.SSID_len = DOT11_MAX_SSID_LEN;
++				}
++				memcpy(result->ssid, plnetinfo->pfnsubnet.SSID,
++					plnetinfo->pfnsubnet.SSID_len);
++				result->ssid[plnetinfo->pfnsubnet.SSID_len] = '\0';
++				memcpy(&result->macaddr, &plnetinfo->pfnsubnet.BSSID,
++				    ETHER_ADDR_LEN);
++
++				DHD_PNO(("\tSSID : "));
++				DHD_PNO(("\n"));
++					DHD_PNO(("\tBSSID: %02x:%02x:%02x:%02x:%02x:%02x\n",
++					result->macaddr.octet[0],
++					result->macaddr.octet[1],
++					result->macaddr.octet[2],
++					result->macaddr.octet[3],
++					result->macaddr.octet[4],
++					result->macaddr.octet[5]));
++				DHD_PNO(("\tchannel: %d, RSSI: %d, timestamp: %d ms\n",
++					plnetinfo->pfnsubnet.channel,
++					plnetinfo->RSSI, plnetinfo->timestamp));
++				DHD_PNO(("\tRTT0 : %d, RTT1: %d\n",
++				    plnetinfo->rtt0, plnetinfo->rtt1));
++
++			}
++		}
++	}
++exit_mutex_unlock:
++	mutex_unlock(&_pno_state->pno_mutex);
++exit:
++	params->params_gscan.get_batch_flag = GSCAN_BATCH_RETRIEVAL_COMPLETE;
++	smp_wmb();
++	wake_up_interruptible(&_pno_state->batch_get_wait);
++	if (nAPs_per_scan) {
++		MFREE(dhd->osh, nAPs_per_scan, gscan_params->mscan);
++	}
++	if (plbestnet) {
++		MFREE(dhd->osh, plbestnet, PNO_BESTNET_LEN);
++	}
++	DHD_PNO(("Batch retrieval done!\n"));
++	return err;
++}
++#endif /* GSCAN_SUPPORT */
++
++static int
++_dhd_pno_get_for_batch(dhd_pub_t *dhd, char *buf, int bufsize, int reason)
++{
++	int err = BCME_OK;
++	int i, j;
++	uint32 timestamp = 0;
++	dhd_pno_params_t *_params = NULL;
++	dhd_pno_status_info_t *_pno_state = NULL;
++	wl_pfn_lscanresults_t *plbestnet = NULL;
++	wl_pfn_lnet_info_t *plnetinfo;
++	dhd_pno_bestnet_entry_t *pbestnet_entry;
++	dhd_pno_best_header_t *pbestnetheader = NULL;
++	dhd_pno_scan_results_t *pscan_results = NULL, *siter, *snext;
++	bool allocate_header = FALSE;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	if (!dhd_support_sta_mode(dhd)) {
++		err = BCME_BADOPTION;
++		goto exit_no_unlock;
++	}
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n", __FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit_no_unlock;
++	}
++
++	if (!(_pno_state->pno_mode & DHD_PNO_BATCH_MODE)) {
++		DHD_ERROR(("%s: Batching SCAN mode is not enabled\n", __FUNCTION__));
++		goto exit_no_unlock;
++	}
++	mutex_lock(&_pno_state->pno_mutex);
++	_params = &_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS];
++	if (buf && bufsize) {
++		if (!list_empty(&_params->params_batch.get_batch.expired_scan_results_list)) {
++			/* need to check whether we have cashed data or not */
++			DHD_PNO(("%s: have cashed batching data in Driver\n",
++				__FUNCTION__));
++			/* convert to results format */
++			goto convert_format;
++		} else {
++			/* this is a first try to get batching results */
++			if (!list_empty(&_params->params_batch.get_batch.scan_results_list)) {
++				/* move the scan_results_list to expired_scan_results_lists */
++				list_for_each_entry_safe(siter, snext,
++					&_params->params_batch.get_batch.scan_results_list, list) {
++					list_move_tail(&siter->list,
++					&_params->params_batch.get_batch.expired_scan_results_list);
++				}
++				_params->params_batch.get_batch.top_node_cnt = 0;
++				_params->params_batch.get_batch.expired_tot_scan_cnt =
++					_params->params_batch.get_batch.tot_scan_cnt;
++				_params->params_batch.get_batch.tot_scan_cnt = 0;
++				goto convert_format;
++			}
++		}
++	}
++	/* create dhd_pno_scan_results_t whenever we got event WLC_E_PFN_BEST_BATCHING */
++	pscan_results = (dhd_pno_scan_results_t *)MALLOC(dhd->osh, SCAN_RESULTS_SIZE);
++	if (pscan_results == NULL) {
++		err = BCME_NOMEM;
++		DHD_ERROR(("failed to allocate dhd_pno_scan_results_t\n"));
++		goto exit;
++	}
++	pscan_results->bestnetheader = NULL;
++	pscan_results->cnt_header = 0;
++	/* add the element into list unless total node cnt is less than MAX_NODE_ CNT */
++	if (_params->params_batch.get_batch.top_node_cnt < MAX_NODE_CNT) {
++		list_add(&pscan_results->list, &_params->params_batch.get_batch.scan_results_list);
++		_params->params_batch.get_batch.top_node_cnt++;
++	} else {
++		int _removed_scan_cnt;
++		/* remove oldest one and add new one */
++		DHD_PNO(("%s : Remove oldest node and add new one\n", __FUNCTION__));
++		_removed_scan_cnt = _dhd_pno_clear_all_batch_results(dhd,
++			&_params->params_batch.get_batch.scan_results_list, TRUE);
++		_params->params_batch.get_batch.tot_scan_cnt -= _removed_scan_cnt;
++		list_add(&pscan_results->list, &_params->params_batch.get_batch.scan_results_list);
++
++	}
++	plbestnet = (wl_pfn_lscanresults_t *)MALLOC(dhd->osh, PNO_BESTNET_LEN);
++	NULL_CHECK(plbestnet, "failed to allocate buffer for bestnet", err);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	memset(plbestnet, 0, PNO_BESTNET_LEN);
++	while (plbestnet->status != PFN_COMPLETE) {
++		memset(plbestnet, 0, PNO_BESTNET_LEN);
++		err = dhd_iovar(dhd, 0, "pfnlbest", NULL, 0, (char *)plbestnet, PNO_BESTNET_LEN,
++			FALSE);
++		if (err < 0) {
++			if (err == BCME_EPERM) {
++				DHD_ERROR(("we cannot get the batching data "
++					"during scanning in firmware, try again\n,"));
++				msleep(500);
++				continue;
++			} else {
++				DHD_ERROR(("%s : failed to execute pfnlbest (err :%d)\n",
++					__FUNCTION__, err));
++				goto exit;
++			}
++		}
++		DHD_PNO(("ver %d, status : %d, count %d\n", plbestnet->version,
++			plbestnet->status, plbestnet->count));
++		if (plbestnet->version != PFN_SCANRESULT_VERSION) {
++			err = BCME_VERSION;
++			DHD_ERROR(("bestnet version(%d) is mismatch with Driver version(%d)\n",
++				plbestnet->version, PFN_SCANRESULT_VERSION));
++			goto exit;
++		}
++		plnetinfo = plbestnet->netinfo;
++		for (i = 0; i < plbestnet->count; i++) {
++			pbestnet_entry = (dhd_pno_bestnet_entry_t *)
++			MALLOC(dhd->osh, BESTNET_ENTRY_SIZE);
++			if (pbestnet_entry == NULL) {
++				err = BCME_NOMEM;
++				DHD_ERROR(("failed to allocate dhd_pno_bestnet_entry\n"));
++				goto exit;
++			}
++			memset(pbestnet_entry, 0, BESTNET_ENTRY_SIZE);
++			pbestnet_entry->recorded_time = jiffies; /* record the current time */
++			/* create header for the first entry */
++			allocate_header = (i == 0)? TRUE : FALSE;
++			/* check whether the new generation is started or not */
++			if (timestamp && (TIME_DIFF(timestamp, plnetinfo->timestamp)
++				> TIME_MIN_DIFF))
++				allocate_header = TRUE;
++			timestamp = plnetinfo->timestamp;
++			if (allocate_header) {
++				pbestnetheader = (dhd_pno_best_header_t *)
++				MALLOC(dhd->osh, BEST_HEADER_SIZE);
++				if (pbestnetheader == NULL) {
++					err = BCME_NOMEM;
++					if (pbestnet_entry)
++						MFREE(dhd->osh, pbestnet_entry,
++						BESTNET_ENTRY_SIZE);
++					DHD_ERROR(("failed to allocate dhd_pno_bestnet_entry\n"));
++					goto exit;
++				}
++				/* increase total cnt of bestnet header */
++				pscan_results->cnt_header++;
++				/* need to record the reason to call dhd_pno_get_for_bach */
++				if (reason)
++					pbestnetheader->reason = (ENABLE << reason);
++				memset(pbestnetheader, 0, BEST_HEADER_SIZE);
++				/* initialize the head of linked list */
++				INIT_LIST_HEAD(&(pbestnetheader->entry_list));
++				/* link the pbestnet heaer into existed list */
++				if (pscan_results->bestnetheader == NULL)
++					/* In case of header */
++					pscan_results->bestnetheader = pbestnetheader;
++				else {
++					dhd_pno_best_header_t *head = pscan_results->bestnetheader;
++					pscan_results->bestnetheader = pbestnetheader;
++					pbestnetheader->next = head;
++				}
++			}
++			/* fills the best network info */
++			pbestnet_entry->channel = plnetinfo->pfnsubnet.channel;
++			pbestnet_entry->RSSI = plnetinfo->RSSI;
++			if (plnetinfo->flags & PFN_PARTIAL_SCAN_MASK) {
++				/* if RSSI is positive value, we assume that
++				 * this scan is aborted by other scan
++				 */
++				DHD_PNO(("This scan is aborted\n"));
++				pbestnetheader->reason = (ENABLE << PNO_STATUS_ABORT);
++			}
++			pbestnet_entry->rtt0 = plnetinfo->rtt0;
++			pbestnet_entry->rtt1 = plnetinfo->rtt1;
++			pbestnet_entry->timestamp = plnetinfo->timestamp;
++			if (plnetinfo->pfnsubnet.SSID_len > DOT11_MAX_SSID_LEN) {
++				DHD_ERROR(("%s: Invalid SSID length %d: trimming it to max\n",
++				      __FUNCTION__, plnetinfo->pfnsubnet.SSID_len));
++				plnetinfo->pfnsubnet.SSID_len = DOT11_MAX_SSID_LEN;
++			}
++			pbestnet_entry->SSID_len = plnetinfo->pfnsubnet.SSID_len;
++			memcpy(pbestnet_entry->SSID, plnetinfo->pfnsubnet.SSID,
++				pbestnet_entry->SSID_len);
++			memcpy(&pbestnet_entry->BSSID, &plnetinfo->pfnsubnet.BSSID, ETHER_ADDR_LEN);
++			/* add the element into list */
++			list_add_tail(&pbestnet_entry->list, &pbestnetheader->entry_list);
++			/* increase best entry count */
++			pbestnetheader->tot_cnt++;
++			pbestnetheader->tot_size += BESTNET_ENTRY_SIZE;
++			DHD_PNO(("Header %d\n", pscan_results->cnt_header - 1));
++			DHD_PNO(("\tSSID : "));
++			for (j = 0; j < plnetinfo->pfnsubnet.SSID_len; j++)
++				DHD_PNO(("%c", plnetinfo->pfnsubnet.SSID[j]));
++			DHD_PNO(("\n"));
++			DHD_PNO(("\tBSSID: %02x:%02x:%02x:%02x:%02x:%02x\n",
++				plnetinfo->pfnsubnet.BSSID.octet[0],
++				plnetinfo->pfnsubnet.BSSID.octet[1],
++				plnetinfo->pfnsubnet.BSSID.octet[2],
++				plnetinfo->pfnsubnet.BSSID.octet[3],
++				plnetinfo->pfnsubnet.BSSID.octet[4],
++				plnetinfo->pfnsubnet.BSSID.octet[5]));
++			DHD_PNO(("\tchannel: %d, RSSI: %d, timestamp: %d ms\n",
++				plnetinfo->pfnsubnet.channel,
++				plnetinfo->RSSI, plnetinfo->timestamp));
++			DHD_PNO(("\tRTT0 : %d, RTT1: %d\n", plnetinfo->rtt0, plnetinfo->rtt1));
++			plnetinfo++;
++		}
++	}
++	if (pscan_results->cnt_header == 0) {
++		/* In case that we didn't get any data from the firmware
++		 * Remove the current scan_result list from get_bach.scan_results_list.
++		 */
++		DHD_PNO(("NO BATCH DATA from Firmware, Delete current SCAN RESULT LIST\n"));
++		list_del(&pscan_results->list);
++		MFREE(dhd->osh, pscan_results, SCAN_RESULTS_SIZE);
++		_params->params_batch.get_batch.top_node_cnt--;
++	}
++	/* increase total scan count using current scan count */
++	_params->params_batch.get_batch.tot_scan_cnt += pscan_results->cnt_header;
++
++	if (buf && bufsize) {
++		/* This is a first try to get batching results */
++		if (!list_empty(&_params->params_batch.get_batch.scan_results_list)) {
++			/* move the scan_results_list to expired_scan_results_lists */
++			list_for_each_entry_safe(siter, snext,
++				&_params->params_batch.get_batch.scan_results_list, list) {
++				list_move_tail(&siter->list,
++					&_params->params_batch.get_batch.expired_scan_results_list);
++			}
++			/* reset gloval values after  moving to expired list */
++			_params->params_batch.get_batch.top_node_cnt = 0;
++			_params->params_batch.get_batch.expired_tot_scan_cnt =
++				_params->params_batch.get_batch.tot_scan_cnt;
++			_params->params_batch.get_batch.tot_scan_cnt = 0;
++		}
++convert_format:
++		err = _dhd_pno_convert_format(dhd, &_params->params_batch, buf, bufsize);
++		if (err < 0) {
++			DHD_ERROR(("failed to convert the data into upper layer format\n"));
++			goto exit;
++		}
++	}
++exit:
++	if (plbestnet)
++		MFREE(dhd->osh, plbestnet, PNO_BESTNET_LEN);
++	if (_params) {
++		_params->params_batch.get_batch.buf = NULL;
++		_params->params_batch.get_batch.bufsize = 0;
++		_params->params_batch.get_batch.bytes_written = err;
++	}
++	mutex_unlock(&_pno_state->pno_mutex);
++exit_no_unlock:
++	if (swait_active(&_pno_state->get_batch_done.wait))
++		complete(&_pno_state->get_batch_done);
++	return err;
++}
++static void
++_dhd_pno_get_batch_handler(struct work_struct *work)
++{
++	dhd_pno_status_info_t *_pno_state;
++	dhd_pub_t *dhd;
++	struct dhd_pno_batch_params *params_batch;
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	_pno_state = container_of(work, struct dhd_pno_status_info, work);
++	dhd = _pno_state->dhd;
++	if (dhd == NULL) {
++		DHD_ERROR(("%s : dhd is NULL\n", __FUNCTION__));
++		return;
++	}
++#ifdef GSCAN_SUPPORT
++	_dhd_pno_get_gscan_batch_from_fw(dhd);
++#endif /* GSCAN_SUPPORT */
++	if (_pno_state->pno_mode & DHD_PNO_BATCH_MODE) {
++		params_batch = &_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS].params_batch;
++
++		_dhd_pno_get_for_batch(dhd, params_batch->get_batch.buf,
++			params_batch->get_batch.bufsize, params_batch->get_batch.reason);
++	}
++}
++
++int
++dhd_pno_get_for_batch(dhd_pub_t *dhd, char *buf, int bufsize, int reason)
++{
++	int err = BCME_OK;
++	char *pbuf = buf;
++	dhd_pno_status_info_t *_pno_state;
++	struct dhd_pno_batch_params *params_batch;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	if (!dhd_support_sta_mode(dhd)) {
++		err = BCME_BADOPTION;
++		goto exit;
++	}
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n", __FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++	params_batch = &_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS].params_batch;
++#ifdef GSCAN_SUPPORT
++	if (_pno_state->pno_mode & DHD_PNO_GSCAN_MODE) {
++		struct dhd_pno_gscan_params *gscan_params;
++		gscan_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS].params_gscan;
++		gscan_params->reason = reason;
++		err = dhd_retreive_batch_scan_results(dhd);
++		if (err == BCME_OK) {
++			wait_event_interruptible_timeout(_pno_state->batch_get_wait,
++			     is_batch_retrieval_complete(gscan_params),
++			     msecs_to_jiffies(GSCAN_BATCH_GET_MAX_WAIT));
++		}
++	} else
++#endif
++	{
++		if (!(_pno_state->pno_mode & DHD_PNO_BATCH_MODE)) {
++			DHD_ERROR(("%s: Batching SCAN mode is not enabled\n", __FUNCTION__));
++			memset(pbuf, 0, bufsize);
++			pbuf += sprintf(pbuf, "scancount=%d\n", 0);
++			sprintf(pbuf, "%s", RESULTS_END_MARKER);
++			err = strlen(buf);
++			goto exit;
++		}
++		params_batch->get_batch.buf = buf;
++		params_batch->get_batch.bufsize = bufsize;
++		params_batch->get_batch.reason = reason;
++		params_batch->get_batch.bytes_written = 0;
++		schedule_work(&_pno_state->work);
++		wait_for_completion(&_pno_state->get_batch_done);
++	}
++
++#ifdef GSCAN_SUPPORT
++	if (!(_pno_state->pno_mode & DHD_PNO_GSCAN_MODE))
++#endif
++	err = params_batch->get_batch.bytes_written;
++exit:
++	return err;
++}
++
++int
++dhd_pno_stop_for_batch(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	int mode = 0;
++	int i = 0;
++	dhd_pno_status_info_t *_pno_state;
++	dhd_pno_params_t *_params;
++	wl_pfn_bssid_t *p_pfn_bssid = NULL;
++	wlc_ssid_ext_t *p_ssid_list = NULL;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	if (!dhd_support_sta_mode(dhd)) {
++		err = BCME_BADOPTION;
++		goto exit;
++	}
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n",
++			__FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++#ifdef GSCAN_SUPPORT
++	if (_pno_state->pno_mode & DHD_PNO_GSCAN_MODE) {
++		DHD_PNO(("Gscan is ongoing, nothing to stop here\n"));
++		return err;
++	}
++#endif
++
++	if (!(_pno_state->pno_mode & DHD_PNO_BATCH_MODE)) {
++		DHD_ERROR(("%s : PNO BATCH MODE is not enabled\n", __FUNCTION__));
++		goto exit;
++	}
++	_pno_state->pno_mode &= ~DHD_PNO_BATCH_MODE;
++	if (_pno_state->pno_mode & (DHD_PNO_LEGACY_MODE | DHD_PNO_HOTLIST_MODE)) {
++		mode = _pno_state->pno_mode;
++		dhd_pno_clean(dhd);
++		_pno_state->pno_mode = mode;
++		/* restart Legacy PNO if the Legacy PNO is on */
++		if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) {
++			struct dhd_pno_legacy_params *_params_legacy;
++			_params_legacy =
++				&(_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS].params_legacy);
++			p_ssid_list = dhd_pno_get_legacy_pno_ssid(dhd, _pno_state);
++			if (!p_ssid_list) {
++				err = BCME_NOMEM;
++				DHD_ERROR(("failed to get Legacy PNO SSID list\n"));
++				goto exit;
++			}
++			err = dhd_pno_set_for_ssid(dhd, p_ssid_list, _params_legacy->nssid,
++				_params_legacy->scan_fr, _params_legacy->pno_repeat,
++				_params_legacy->pno_freq_expo_max, _params_legacy->chan_list,
++				_params_legacy->nchan);
++			if (err < 0) {
++				DHD_ERROR(("%s : failed to restart legacy PNO scan(err: %d)\n",
++					__FUNCTION__, err));
++				goto exit;
++			}
++		} else if (_pno_state->pno_mode & DHD_PNO_HOTLIST_MODE) {
++			struct dhd_pno_bssid *iter, *next;
++			_params = &(_pno_state->pno_params_arr[INDEX_OF_HOTLIST_PARAMS]);
++			p_pfn_bssid = kzalloc(sizeof(wl_pfn_bssid_t) *
++				_params->params_hotlist.nbssid, GFP_KERNEL);
++			if (p_pfn_bssid == NULL) {
++				DHD_ERROR(("%s : failed to allocate wl_pfn_bssid_t array"
++					" (count: %d)",
++					__FUNCTION__, _params->params_hotlist.nbssid));
++				err = BCME_ERROR;
++				_pno_state->pno_mode &= ~DHD_PNO_HOTLIST_MODE;
++				goto exit;
++			}
++			i = 0;
++			/* convert dhd_pno_bssid to wl_pfn_bssid */
++			list_for_each_entry_safe(iter, next,
++				&_params->params_hotlist.bssid_list, list) {
++				memcpy(&p_pfn_bssid[i].macaddr, &iter->macaddr, ETHER_ADDR_LEN);
++				p_pfn_bssid[i].flags = iter->flags;
++				i++;
++			}
++			err = dhd_pno_set_for_hotlist(dhd, p_pfn_bssid, &_params->params_hotlist);
++			if (err < 0) {
++				_pno_state->pno_mode &= ~DHD_PNO_HOTLIST_MODE;
++				DHD_ERROR(("%s : failed to restart hotlist scan(err: %d)\n",
++					__FUNCTION__, err));
++				goto exit;
++			}
++		}
++	} else {
++		err = dhd_pno_clean(dhd);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++	}
++exit:
++	_params = &_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS];
++	_dhd_pno_reinitialize_prof(dhd, _params, DHD_PNO_BATCH_MODE);
++	kfree(p_ssid_list);
++	kfree(p_pfn_bssid);
++	return err;
++}
++
++int
++dhd_pno_set_for_hotlist(dhd_pub_t *dhd, wl_pfn_bssid_t *p_pfn_bssid,
++	struct dhd_pno_hotlist_params *hotlist_params)
++{
++	int err = BCME_OK;
++	int i;
++	uint16 _chan_list[WL_NUMCHANNELS];
++	int rem_nchan = 0;
++	int tot_nchan = 0;
++	int mode = 0;
++	dhd_pno_params_t *_params;
++	dhd_pno_params_t *_params2;
++	struct dhd_pno_bssid *_pno_bssid;
++	dhd_pno_status_info_t *_pno_state;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	NULL_CHECK(hotlist_params, "hotlist_params is NULL", err);
++	NULL_CHECK(p_pfn_bssid, "p_pfn_bssid is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++
++	if (!dhd_support_sta_mode(dhd)) {
++		err = BCME_BADOPTION;
++		goto exit;
++	}
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n", __FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++	_params = &_pno_state->pno_params_arr[INDEX_OF_HOTLIST_PARAMS];
++	if (!(_pno_state->pno_mode & DHD_PNO_HOTLIST_MODE)) {
++		_pno_state->pno_mode |= DHD_PNO_HOTLIST_MODE;
++		err = _dhd_pno_reinitialize_prof(dhd, _params, DHD_PNO_HOTLIST_MODE);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call _dhd_pno_reinitialize_prof\n",
++				__FUNCTION__));
++			goto exit;
++		}
++	}
++	_params->params_batch.nchan = hotlist_params->nchan;
++	_params->params_batch.scan_fr = hotlist_params->scan_fr;
++	if (hotlist_params->nchan)
++		memcpy(_params->params_hotlist.chan_list, hotlist_params->chan_list,
++			sizeof(_params->params_hotlist.chan_list));
++	memset(_chan_list, 0, sizeof(_chan_list));
++
++	rem_nchan = ARRAYSIZE(hotlist_params->chan_list) - hotlist_params->nchan;
++	if (hotlist_params->band == WLC_BAND_2G || hotlist_params->band == WLC_BAND_5G) {
++		/* get a valid channel list based on band B or A */
++		err = _dhd_pno_get_channels(dhd,
++		&_params->params_hotlist.chan_list[hotlist_params->nchan],
++		&rem_nchan, hotlist_params->band, FALSE);
++		if (err < 0) {
++			DHD_ERROR(("%s: failed to get valid channel list(band : %d)\n",
++				__FUNCTION__, hotlist_params->band));
++			goto exit;
++		}
++		/* now we need to update nchan because rem_chan has valid channel count */
++		_params->params_hotlist.nchan += rem_nchan;
++		/* need to sort channel list */
++		sort(_params->params_hotlist.chan_list, _params->params_hotlist.nchan,
++			sizeof(_params->params_hotlist.chan_list[0]), _dhd_pno_cmpfunc, NULL);
++	}
++#ifdef PNO_DEBUG
++{
++		int i;
++		DHD_PNO(("Channel list : "));
++		for (i = 0; i < _params->params_batch.nchan; i++) {
++			DHD_PNO(("%d ", _params->params_batch.chan_list[i]));
++		}
++		DHD_PNO(("\n"));
++}
++#endif
++	if (_params->params_hotlist.nchan) {
++		/* copy the channel list into local array */
++		memcpy(_chan_list, _params->params_hotlist.chan_list,
++			sizeof(_chan_list));
++		tot_nchan = _params->params_hotlist.nchan;
++	}
++	if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) {
++			DHD_PNO(("PNO SSID is on progress in firmware\n"));
++			/* store current pno_mode before disabling pno */
++			mode = _pno_state->pno_mode;
++			err = _dhd_pno_enable(dhd, PNO_OFF);
++			if (err < 0) {
++				DHD_ERROR(("%s : failed to disable PNO\n", __FUNCTION__));
++				goto exit;
++			}
++			/* restore the previous mode */
++			_pno_state->pno_mode = mode;
++			/* Use the superset for channelist between two mode */
++			_params2 = &(_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS]);
++			if (_params2->params_legacy.nchan > 0 &&
++				_params->params_hotlist.nchan > 0) {
++				err = _dhd_pno_chan_merge(_chan_list, &tot_nchan,
++					&_params2->params_legacy.chan_list[0],
++					_params2->params_legacy.nchan,
++					&_params->params_hotlist.chan_list[0],
++					_params->params_hotlist.nchan);
++				if (err < 0) {
++					DHD_ERROR(("%s : failed to merge channel list"
++						"between legacy and hotlist\n",
++						__FUNCTION__));
++					goto exit;
++				}
++			}
++
++	}
++
++	INIT_LIST_HEAD(&(_params->params_hotlist.bssid_list));
++
++	err = _dhd_pno_add_bssid(dhd, p_pfn_bssid, hotlist_params->nbssid);
++	if (err < 0) {
++		DHD_ERROR(("%s : failed to call _dhd_pno_add_bssid(err :%d)\n",
++			__FUNCTION__, err));
++		goto exit;
++	}
++	if ((err = _dhd_pno_set(dhd, _params, DHD_PNO_HOTLIST_MODE)) < 0) {
++		DHD_ERROR(("%s : failed to set call pno_set (err %d) in firmware\n",
++			__FUNCTION__, err));
++		goto exit;
++	}
++	if (tot_nchan > 0) {
++		if ((err = _dhd_pno_cfg(dhd, _chan_list, tot_nchan)) < 0) {
++			DHD_ERROR(("%s : failed to set call pno_cfg (err %d) in firmware\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++	}
++	for (i = 0; i < hotlist_params->nbssid; i++) {
++		_pno_bssid = kzalloc(sizeof(struct dhd_pno_bssid), GFP_KERNEL);
++		NULL_CHECK(_pno_bssid, "_pfn_bssid is NULL", err);
++		memcpy(&_pno_bssid->macaddr, &p_pfn_bssid[i].macaddr, ETHER_ADDR_LEN);
++		_pno_bssid->flags = p_pfn_bssid[i].flags;
++		list_add_tail(&_pno_bssid->list, &_params->params_hotlist.bssid_list);
++	}
++	_params->params_hotlist.nbssid = hotlist_params->nbssid;
++	if (_pno_state->pno_status == DHD_PNO_DISABLED) {
++		if ((err = _dhd_pno_enable(dhd, PNO_ON)) < 0)
++			DHD_ERROR(("%s : failed to enable PNO\n", __FUNCTION__));
++	}
++exit:
++	/* clear mode in case of error */
++	if (err < 0)
++		_pno_state->pno_mode &= ~DHD_PNO_HOTLIST_MODE;
++	return err;
++}
++
++int
++dhd_pno_stop_for_hotlist(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	uint32 mode = 0;
++	dhd_pno_status_info_t *_pno_state;
++	dhd_pno_params_t *_params;
++	wlc_ssid_ext_t *p_ssid_list = NULL;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n",
++			__FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++
++	if (!(_pno_state->pno_mode & DHD_PNO_HOTLIST_MODE)) {
++		DHD_ERROR(("%s : Hotlist MODE is not enabled\n",
++			__FUNCTION__));
++		goto exit;
++	}
++	_pno_state->pno_mode &= ~DHD_PNO_BATCH_MODE;
++
++	if (_pno_state->pno_mode & (DHD_PNO_LEGACY_MODE | DHD_PNO_BATCH_MODE)) {
++		/* retrieve the batching data from firmware into host */
++		dhd_pno_get_for_batch(dhd, NULL, 0, PNO_STATUS_DISABLE);
++		/* save current pno_mode before calling dhd_pno_clean */
++		mode = _pno_state->pno_mode;
++		err = dhd_pno_clean(dhd);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++		/* restore previos pno mode */
++		_pno_state->pno_mode = mode;
++		if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) {
++			/* restart Legacy PNO Scan */
++			struct dhd_pno_legacy_params *_params_legacy;
++			_params_legacy =
++			&(_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS].params_legacy);
++			p_ssid_list = dhd_pno_get_legacy_pno_ssid(dhd, _pno_state);
++			if (!p_ssid_list) {
++				err = BCME_NOMEM;
++				DHD_ERROR(("failed to get Legacy PNO SSID list\n"));
++				goto exit;
++			}
++			err = dhd_pno_set_for_ssid(dhd, p_ssid_list, _params_legacy->nssid,
++				_params_legacy->scan_fr, _params_legacy->pno_repeat,
++				_params_legacy->pno_freq_expo_max, _params_legacy->chan_list,
++				_params_legacy->nchan);
++			if (err < 0) {
++				DHD_ERROR(("%s : failed to restart legacy PNO scan(err: %d)\n",
++					__FUNCTION__, err));
++				goto exit;
++			}
++		} else if (_pno_state->pno_mode & DHD_PNO_BATCH_MODE) {
++			/* restart Batching Scan */
++			_params = &(_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS]);
++			/* restart BATCH SCAN */
++			err = dhd_pno_set_for_batch(dhd, &_params->params_batch);
++			if (err < 0) {
++				_pno_state->pno_mode &= ~DHD_PNO_BATCH_MODE;
++				DHD_ERROR(("%s : failed to restart batch scan(err: %d)\n",
++					__FUNCTION__,  err));
++				goto exit;
++			}
++		}
++	} else {
++		err = dhd_pno_clean(dhd);
++		if (err < 0) {
++			DHD_ERROR(("%s : failed to call dhd_pno_clean (err: %d)\n",
++				__FUNCTION__, err));
++			goto exit;
++		}
++	}
++exit:
++	kfree(p_ssid_list);
++	return err;
++}
++
++#ifdef GSCAN_SUPPORT
++int
++dhd_retreive_batch_scan_results(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	dhd_pno_status_info_t *_pno_state;
++	dhd_pno_params_t *_params;
++	struct dhd_pno_batch_params *params_batch;
++
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++
++	params_batch = &_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS].params_batch;
++	if (_params->params_gscan.get_batch_flag == GSCAN_BATCH_RETRIEVAL_COMPLETE) {
++		DHD_PNO(("Retreive batch results\n"));
++		params_batch->get_batch.buf = NULL;
++		params_batch->get_batch.bufsize = 0;
++		params_batch->get_batch.reason = PNO_STATUS_EVENT;
++		_params->params_gscan.get_batch_flag = GSCAN_BATCH_RETRIEVAL_IN_PROGRESS;
++		smp_wmb();
++		schedule_work(&_pno_state->work);
++	} else {
++		DHD_PNO(("%s : WLC_E_PFN_BEST_BATCHING retrieval"
++			"already in progress, will skip\n", __FUNCTION__));
++		err = BCME_ERROR;
++	}
++
++	return err;
++}
++
++/* Handle Significant WiFi Change (SWC) event from FW
++ * Send event to HAL when all results arrive from FW
++ */
++void *
++dhd_handle_swc_evt(dhd_pub_t *dhd, const void *event_data, int *send_evt_bytes)
++{
++	void *ptr = NULL;
++	dhd_pno_status_info_t *_pno_state = PNO_GET_PNOSTATE(dhd);
++	struct dhd_pno_gscan_params *gscan_params;
++	struct dhd_pno_swc_evt_param *params;
++	wl_pfn_swc_results_t *results = (wl_pfn_swc_results_t *)event_data;
++	wl_pfn_significant_net_t *change_array;
++	int i;
++
++	gscan_params = &(_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS].params_gscan);
++	params = &(gscan_params->param_significant);
++
++	if (!results->total_count) {
++		*send_evt_bytes = 0;
++		return ptr;
++	}
++
++	if (!params->results_rxed_so_far) {
++		if (!params->change_array) {
++			params->change_array = (wl_pfn_significant_net_t *)
++			kmalloc(sizeof(wl_pfn_significant_net_t) * results->total_count,
++			GFP_KERNEL);
++
++			if (!params->change_array) {
++				DHD_ERROR(("%s Cannot Malloc %zd bytes!!\n", __FUNCTION__,
++				sizeof(wl_pfn_significant_net_t) * results->total_count));
++				*send_evt_bytes = 0;
++				return ptr;
++			}
++		} else {
++			DHD_ERROR(("RX'ed WLC_E_PFN_SWC evt from FW, previous evt not complete!!"));
++			*send_evt_bytes = 0;
++			return ptr;
++		}
++
++	}
++
++	DHD_PNO(("%s: pkt_count %d total_count %d\n", __FUNCTION__,
++	results->pkt_count, results->total_count));
++
++	for (i = 0; i < results->pkt_count; i++) {
++		DHD_PNO(("\t %02x:%02x:%02x:%02x:%02x:%02x\n",
++		results->list[i].BSSID.octet[0],
++		results->list[i].BSSID.octet[1],
++		results->list[i].BSSID.octet[2],
++		results->list[i].BSSID.octet[3],
++		results->list[i].BSSID.octet[4],
++		results->list[i].BSSID.octet[5]));
++	}
++
++	change_array = &params->change_array[params->results_rxed_so_far];
++	memcpy(change_array, results->list, sizeof(wl_pfn_significant_net_t) * results->pkt_count);
++	params->results_rxed_so_far += results->pkt_count;
++
++	if (params->results_rxed_so_far == results->total_count) {
++		params->results_rxed_so_far = 0;
++		*send_evt_bytes = sizeof(wl_pfn_significant_net_t) * results->total_count;
++		/* Pack up change buffer to send up and reset
++		 * results_rxed_so_far, after its done.
++		 */
++		ptr = (void *) params->change_array;
++		/* expecting the callee to free this mem chunk */
++		params->change_array = NULL;
++	}
++	 else {
++		*send_evt_bytes = 0;
++	}
++
++	return ptr;
++}
++
++void
++dhd_gscan_hotlist_cache_cleanup(dhd_pub_t *dhd, hotlist_type_t type)
++{
++	dhd_pno_status_info_t *_pno_state = PNO_GET_PNOSTATE(dhd);
++	struct dhd_pno_gscan_params *gscan_params;
++	gscan_results_cache_t *iter, *tmp;
++
++	if (!_pno_state) {
++		return;
++	}
++	gscan_params = &(_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS].params_gscan);
++
++	if (type == HOTLIST_FOUND) {
++		iter = gscan_params->gscan_hotlist_found;
++		gscan_params->gscan_hotlist_found = NULL;
++	} else {
++		iter = gscan_params->gscan_hotlist_lost;
++		gscan_params->gscan_hotlist_lost = NULL;
++	}
++
++	while (iter) {
++		tmp = iter->next;
++		kfree(iter);
++		iter = tmp;
++	}
++
++	return;
++}
++
++void *
++dhd_process_full_gscan_result(dhd_pub_t *dhd, const void *data, uint32 len, int *size)
++{
++	wl_bss_info_t *bi = NULL;
++	wl_gscan_result_t *gscan_result;
++	wifi_gscan_result_t *result = NULL;
++	u32 bi_length = 0;
++	uint8 channel;
++	uint32 mem_needed;
++	struct timespec ts;
++	u32 bi_ie_length = 0;
++	u32 bi_ie_offset = 0;
++
++	*size = 0;
++
++	gscan_result = (wl_gscan_result_t *)data;
++
++	if (!gscan_result) {
++		DHD_ERROR(("Invalid gscan result (NULL pointer)\n"));
++		goto exit;
++	}
++	if (!gscan_result->bss_info) {
++		DHD_ERROR(("Invalid gscan bss info (NULL pointer)\n"));
++		goto exit;
++	}
++
++	if ((len < sizeof(*gscan_result)) ||
++		(len < dtoh32(gscan_result->buflen)) ||
++		(dtoh32(gscan_result->buflen) >
++		 (sizeof(*gscan_result) + WL_SCAN_IE_LEN_MAX))) {
++		DHD_ERROR(("%s: invalid gscan buflen:%u\n", __FUNCTION__,
++					dtoh32(gscan_result->buflen)));
++		goto exit;
++	}
++
++	bi = &gscan_result->bss_info[0].info;
++	bi_length = dtoh32(bi->length);
++	if (bi_length != (dtoh32(gscan_result->buflen) -
++		WL_GSCAN_RESULTS_FIXED_SIZE - WL_GSCAN_INFO_FIXED_FIELD_SIZE)) {
++		DHD_ERROR(("Invalid bss_info length %d: ignoring\n", bi_length));
++		goto exit;
++	}
++	bi_ie_offset = dtoh32(bi->ie_offset);
++	bi_ie_length = dtoh32(bi->ie_length);
++	if ((bi_ie_offset + bi_ie_length) > bi_length) {
++		DHD_ERROR(("%s: Invalid ie_length:%u or ie_offset:%u\n",
++			__FUNCTION__, bi_ie_length, bi_ie_offset));
++		goto exit;
++	}
++	if (bi->SSID_len > DOT11_MAX_SSID_LEN) {
++		DHD_ERROR(("%s: Invalid SSID length:%u\n", __FUNCTION__, bi->SSID_len));
++		goto exit;
++	}
++
++	mem_needed = OFFSETOF(wifi_gscan_result_t, ie_data) + bi_ie_length;
++	result = kmalloc(mem_needed, GFP_KERNEL);
++
++	if (!result) {
++		DHD_ERROR(("%s Cannot malloc scan result buffer %d bytes\n",
++		 __FUNCTION__, mem_needed));
++		goto exit;
++	}
++
++	memcpy(result->ssid, bi->SSID, bi->SSID_len);
++	result->ssid[bi->SSID_len] = '\0';
++	channel = wf_chspec_ctlchan(bi->chanspec);
++	result->channel = wf_channel2mhz(channel,
++		(channel <= CH_MAX_2G_CHANNEL?
++		WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G));
++	result->rssi = (int32) bi->RSSI;
++	result->rtt = 0;
++	result->rtt_sd = 0;
++	get_monotonic_boottime(&ts);
++	result->ts = (uint64) TIMESPEC_TO_US(ts);
++	result->beacon_period = dtoh16(bi->beacon_period);
++	result->capability = dtoh16(bi->capability);
++	result->ie_length = bi_ie_length;
++	memcpy(&result->macaddr, &bi->BSSID, ETHER_ADDR_LEN);
++	memcpy(result->ie_data, ((uint8 *)bi + bi_ie_offset), bi->ie_length);
++	*size = mem_needed;
++exit:
++	return result;
++}
++
++void *
++dhd_pno_process_epno_result(dhd_pub_t *dhd, const void *data, uint32 event, int *size)
++{
++	dhd_epno_results_t *results = NULL;
++	dhd_pno_status_info_t *_pno_state = PNO_GET_PNOSTATE(dhd);
++	struct dhd_pno_gscan_params *gscan_params;
++	uint32 count, mem_needed = 0, i;
++	uint8 ssid[DOT11_MAX_SSID_LEN + 1];
++	struct ether_addr *bssid;
++
++	*size = 0;
++	if (!_pno_state)
++		return NULL;
++	gscan_params = &(_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS].params_gscan);
++
++	if (event == WLC_E_PFN_SSID_EXT) {
++		wl_pfn_ssid_ext_result_t *evt_data;
++		evt_data = (wl_pfn_ssid_ext_result_t *) data;
++
++		if (evt_data->version != PFN_SSID_EXT_VERSION) {
++			DHD_PNO(("ePNO event: Incorrect version %d %d\n", evt_data->version,
++			     PFN_SSID_EXT_VERSION));
++			return NULL;
++		}
++		count = evt_data->count;
++		mem_needed = sizeof(dhd_epno_results_t) * count;
++		results = (dhd_epno_results_t *) kmalloc(mem_needed, GFP_KERNEL);
++		if (!results) {
++			DHD_ERROR(("%s: Can't malloc %d bytes for results\n", __FUNCTION__,
++			        mem_needed));
++			return NULL;
++		}
++		DHD_ERROR(("Rx'ed WLC_E_PFN_SSID_EXT event: %d results\n", count));
++		for (i = 0; i < count; i++) {
++			results[i].rssi = evt_data->net[i].rssi;
++			results[i].channel = wf_channel2mhz(evt_data->net[i].channel,
++			                (evt_data->net[i].channel <= CH_MAX_2G_CHANNEL ?
++			                WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G));
++			results[i].flags = evt_data->net[i].flags;
++			dhd_pno_idx_to_ssid(gscan_params, &results[i],
++			           evt_data->net[i].index);
++			memcpy(ssid, results[i].ssid, results[i].ssid_len);
++			bssid = &results[i].bssid;
++			memcpy(bssid, &evt_data->net[i].bssid, ETHER_ADDR_LEN);
++			ssid[results[i].ssid_len] = '\0';
++			DHD_PNO(("ssid - %s bssid %02x:%02x:%02x:%02x:%02x:%02x "
++			        "idx %d ch %d rssi %d flags %d\n", ssid,
++			        bssid->octet[0], bssid->octet[1],
++			        bssid->octet[2], bssid->octet[3],
++			        bssid->octet[4], bssid->octet[5],
++			        evt_data->net[i].index, results[i].channel,
++			        results[i].rssi, results[i].flags));
++		}
++	} else if (event == WLC_E_PFN_NET_FOUND || event == WLC_E_PFN_NET_LOST) {
++		wl_pfn_scanresults_t *pfn_result = (wl_pfn_scanresults_t *)data;
++		wl_pfn_net_info_t *net;
++
++		if (pfn_result->version != PFN_SCANRESULT_VERSION) {
++			DHD_ERROR(("%s event %d: Incorrect version %d %d\n", __FUNCTION__, event,
++			          pfn_result->version, PFN_SCANRESULT_VERSION));
++			return NULL;
++		}
++		if ((pfn_result->count == 0) || (pfn_result->count > EVENT_MAX_NETCNT)) {
++			DHD_ERROR(("%s event %d: wrong pfn results count %d\n",
++				__FUNCTION__, event, pfn_result->count));
++			return NULL;
++		}
++		count = pfn_result->count;
++		mem_needed = sizeof(dhd_epno_results_t) * count;
++		results = (dhd_epno_results_t *) kmalloc(mem_needed, GFP_KERNEL);
++		if (!results) {
++			DHD_ERROR(("%s: Can't malloc %d bytes for results\n", __FUNCTION__,
++			        mem_needed));
++			return NULL;
++		}
++		for (i = 0; i < count; i++) {
++			net = &pfn_result->netinfo[i];
++			results[i].rssi = net->RSSI;
++			results[i].channel =  wf_channel2mhz(net->pfnsubnet.channel,
++			                  (net->pfnsubnet.channel <= CH_MAX_2G_CHANNEL ?
++			                  WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G));
++			results[i].flags = (event == WLC_E_PFN_NET_FOUND) ?
++			               WL_PFN_SSID_EXT_FOUND: WL_PFN_SSID_EXT_LOST;
++			results[i].ssid_len = min(net->pfnsubnet.SSID_len,
++			               (uint8)DOT11_MAX_SSID_LEN);
++			bssid = &results[i].bssid;
++			memcpy(bssid, &net->pfnsubnet.BSSID, ETHER_ADDR_LEN);
++			memcpy(results[i].ssid, net->pfnsubnet.SSID, results[i].ssid_len);
++			memcpy(ssid, results[i].ssid, results[i].ssid_len);
++			ssid[results[i].ssid_len] = '\0';
++			DHD_PNO(("ssid - %s bssid %02x:%02x:%02x:%02x:%02x:%02x "
++			        "ch %d rssi %d flags %d\n", ssid,
++			        bssid->octet[0], bssid->octet[1],
++			        bssid->octet[2], bssid->octet[3],
++			        bssid->octet[4], bssid->octet[5],
++			        results[i].channel, results[i].rssi, results[i].flags));
++		}
++	}
++	*size = mem_needed;
++	return results;
++}
++
++void *
++dhd_handle_hotlist_scan_evt(dhd_pub_t *dhd, const void *event_data,
++        int *send_evt_bytes, hotlist_type_t type)
++{
++	void *ptr = NULL;
++	dhd_pno_status_info_t *_pno_state = PNO_GET_PNOSTATE(dhd);
++	struct dhd_pno_gscan_params *gscan_params;
++	wl_pfn_scanresults_t *results = (wl_pfn_scanresults_t *)event_data;
++	wifi_gscan_result_t *hotlist_found_array;
++	wl_pfn_net_info_t *plnetinfo;
++	gscan_results_cache_t *gscan_hotlist_cache;
++	int malloc_size = 0, i, total = 0;
++
++	gscan_params = &(_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS].params_gscan);
++
++	if ((results->count == 0) || (results->count > EVENT_MAX_NETCNT)) {
++		DHD_ERROR(("%s: wrong result count:%d\n", __FUNCTION__, results->count));
++		*send_evt_bytes = 0;
++		return ptr;
++	}
++
++	malloc_size = sizeof(gscan_results_cache_t) +
++	((results->count - 1) * sizeof(wifi_gscan_result_t));
++	gscan_hotlist_cache = (gscan_results_cache_t *) kmalloc(malloc_size, GFP_KERNEL);
++
++	if (!gscan_hotlist_cache) {
++		DHD_ERROR(("%s Cannot Malloc %d bytes!!\n", __FUNCTION__, malloc_size));
++		*send_evt_bytes = 0;
++		return ptr;
++	}
++
++	if (type == HOTLIST_FOUND) {
++		gscan_hotlist_cache->next = gscan_params->gscan_hotlist_found;
++		gscan_params->gscan_hotlist_found = gscan_hotlist_cache;
++		DHD_PNO(("%s enter, FOUND results count %d\n", __FUNCTION__, results->count));
++	} else {
++		gscan_hotlist_cache->next = gscan_params->gscan_hotlist_lost;
++		gscan_params->gscan_hotlist_lost = gscan_hotlist_cache;
++		DHD_PNO(("%s enter, LOST results count %d\n", __FUNCTION__, results->count));
++	}
++
++	gscan_hotlist_cache->tot_count = results->count;
++	gscan_hotlist_cache->tot_consumed = 0;
++	plnetinfo = results->netinfo;
++
++	for (i = 0; i < results->count; i++, plnetinfo++) {
++		hotlist_found_array = &gscan_hotlist_cache->results[i];
++		hotlist_found_array->channel = wf_channel2mhz(plnetinfo->pfnsubnet.channel,
++			(plnetinfo->pfnsubnet.channel <= CH_MAX_2G_CHANNEL?
++			WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G));
++		hotlist_found_array->rssi = (int32) plnetinfo->RSSI;
++		/* Info not available & not expected */
++		hotlist_found_array->beacon_period = 0;
++		hotlist_found_array->capability = 0;
++		hotlist_found_array->ie_length = 0;
++
++		hotlist_found_array->ts = convert_fw_rel_time_to_systime(plnetinfo->timestamp);
++		if (plnetinfo->pfnsubnet.SSID_len > DOT11_MAX_SSID_LEN) {
++			DHD_ERROR(("Invalid SSID length %d: trimming it to max\n",
++			          plnetinfo->pfnsubnet.SSID_len));
++			plnetinfo->pfnsubnet.SSID_len = DOT11_MAX_SSID_LEN;
++		}
++		memcpy(hotlist_found_array->ssid, plnetinfo->pfnsubnet.SSID,
++			plnetinfo->pfnsubnet.SSID_len);
++		hotlist_found_array->ssid[plnetinfo->pfnsubnet.SSID_len] = '\0';
++
++		memcpy(&hotlist_found_array->macaddr, &plnetinfo->pfnsubnet.BSSID, ETHER_ADDR_LEN);
++	DHD_PNO(("\t%s %02x:%02x:%02x:%02x:%02x:%02x rssi %d\n", hotlist_found_array->ssid,
++		hotlist_found_array->macaddr.octet[0],
++		hotlist_found_array->macaddr.octet[1],
++		hotlist_found_array->macaddr.octet[2],
++		hotlist_found_array->macaddr.octet[3],
++		hotlist_found_array->macaddr.octet[4],
++		hotlist_found_array->macaddr.octet[5],
++		hotlist_found_array->rssi));
++	}
++
++
++	if (results->status == PFN_COMPLETE) {
++		ptr = (void *) gscan_hotlist_cache;
++		while (gscan_hotlist_cache) {
++			total += gscan_hotlist_cache->tot_count;
++			gscan_hotlist_cache = gscan_hotlist_cache->next;
++		}
++		*send_evt_bytes =  total * sizeof(wifi_gscan_result_t);
++	}
++
++	return ptr;
++}
++#endif /* GSCAN_SUPPORT */
++int
++dhd_pno_event_handler(dhd_pub_t *dhd, wl_event_msg_t *event, void *event_data)
++{
++	int err = BCME_OK;
++	uint status, event_type, flags, datalen;
++	dhd_pno_status_info_t *_pno_state;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(dhd->pno_state, "pno_state is NULL", err);
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	if (!WLS_SUPPORTED(_pno_state)) {
++		DHD_ERROR(("%s : wifi location service is not supported\n", __FUNCTION__));
++		err = BCME_UNSUPPORTED;
++		goto exit;
++	}
++	event_type = ntoh32(event->event_type);
++	flags = ntoh16(event->flags);
++	status = ntoh32(event->status);
++	datalen = ntoh32(event->datalen);
++	DHD_PNO(("%s enter : event_type :%d\n", __FUNCTION__, event_type));
++	switch (event_type) {
++	case WLC_E_PFN_BSSID_NET_FOUND:
++	case WLC_E_PFN_BSSID_NET_LOST:
++		/* TODO : need to implement event logic using generic netlink */
++		break;
++	case WLC_E_PFN_BEST_BATCHING:
++#ifndef GSCAN_SUPPORT
++	{
++		struct dhd_pno_batch_params *params_batch;
++		params_batch = &_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS].params_batch;
++//		if (!waitqueue_active(&_pno_state->get_batch_done.wait)) {
++		if (!swait_active(&_pno_state->get_batch_done.wait)) {
++			DHD_PNO(("%s : WLC_E_PFN_BEST_BATCHING\n", __FUNCTION__));
++			params_batch->get_batch.buf = NULL;
++			params_batch->get_batch.bufsize = 0;
++			params_batch->get_batch.reason = PNO_STATUS_EVENT;
++			schedule_work(&_pno_state->work);
++		} else
++			DHD_PNO(("%s : WLC_E_PFN_BEST_BATCHING"
++				"will skip this event\n", __FUNCTION__));
++		break;
++	}
++#else
++		break;
++#endif /* !GSCAN_SUPPORT */
++	default:
++		DHD_ERROR(("unknown event : %d\n", event_type));
++	}
++exit:
++	return err;
++}
++
++int dhd_pno_init(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	dhd_pno_status_info_t *_pno_state;
++	char *buf = NULL;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	UNUSED_PARAMETER(_dhd_pno_suspend);
++	if (dhd->pno_state)
++		goto exit;
++	dhd->pno_state = MALLOC(dhd->osh, sizeof(dhd_pno_status_info_t));
++	NULL_CHECK(dhd->pno_state, "failed to create dhd_pno_state", err);
++	memset(dhd->pno_state, 0, sizeof(dhd_pno_status_info_t));
++	/* need to check whether current firmware support batching and hotlist scan */
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	_pno_state->wls_supported = TRUE;
++	_pno_state->dhd = dhd;
++	mutex_init(&_pno_state->pno_mutex);
++	INIT_WORK(&_pno_state->work, _dhd_pno_get_batch_handler);
++	init_completion(&_pno_state->get_batch_done);
++#ifdef GSCAN_SUPPORT
++	init_waitqueue_head(&_pno_state->batch_get_wait);
++#endif /* GSCAN_SUPPORT */
++	buf = kmalloc(WLC_IOCTL_SMLEN, GFP_KERNEL);
++	if (!buf) {
++		DHD_ERROR((":%s buf alloc err.\n", __FUNCTION__));
++		return BCME_NOMEM;
++	}
++	err = dhd_iovar(dhd, 0, "pfnlbest", NULL, 0, buf, WLC_IOCTL_SMLEN,
++		FALSE);
++	if (err == BCME_UNSUPPORTED) {
++		_pno_state->wls_supported = FALSE;
++		DHD_INFO(("Current firmware doesn't support"
++			" Android Location Service\n"));
++	} else {
++		DHD_ERROR(("%s: Support Android Location Service\n",
++			__FUNCTION__));
++	}
++exit:
++	kfree(buf);
++	return err;
++}
++
++int dhd_pno_deinit(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	dhd_pno_status_info_t *_pno_state;
++	dhd_pno_params_t *_params;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++
++	DHD_PNO(("%s enter\n", __FUNCTION__));
++	_pno_state = PNO_GET_PNOSTATE(dhd);
++	NULL_CHECK(_pno_state, "pno_state is NULL", err);
++	/* may need to free legacy ssid_list */
++	if (_pno_state->pno_mode & DHD_PNO_LEGACY_MODE) {
++		_params = &_pno_state->pno_params_arr[INDEX_OF_LEGACY_PARAMS];
++		_dhd_pno_reinitialize_prof(dhd, _params, DHD_PNO_LEGACY_MODE);
++	}
++
++#ifdef GSCAN_SUPPORT
++	if (_pno_state->pno_mode & DHD_PNO_GSCAN_MODE) {
++		_params = &_pno_state->pno_params_arr[INDEX_OF_GSCAN_PARAMS];
++		mutex_lock(&_pno_state->pno_mutex);
++		dhd_pno_reset_cfg_gscan(_params, _pno_state, GSCAN_FLUSH_ALL_CFG);
++		mutex_unlock(&_pno_state->pno_mutex);
++	}
++#endif /* GSCAN_SUPPORT */
++
++	if (_pno_state->pno_mode & DHD_PNO_BATCH_MODE) {
++		_params = &_pno_state->pno_params_arr[INDEX_OF_BATCH_PARAMS];
++		/* clear resource if the BATCH MODE is on */
++		_dhd_pno_reinitialize_prof(dhd, _params, DHD_PNO_BATCH_MODE);
++	}
++	cancel_work_sync(&_pno_state->work);
++	MFREE(dhd->osh, _pno_state, sizeof(dhd_pno_status_info_t));
++	dhd->pno_state = NULL;
++	return err;
++}
++#endif /* PNO_SUPPORT */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_pno.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_pno.h
+new file mode 100644
+index 000000000..94f0efc08
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_pno.h
+@@ -0,0 +1,562 @@
++/*
++ * Header file of Broadcom Dongle Host Driver (DHD)
++ * Prefered Network Offload code and Wi-Fi Location Service(WLS) code.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_pno.h 423669 2013-09-18 13:01:55Z $
++ */
++
++#ifndef __DHD_PNO_H__
++#define __DHD_PNO_H__
++
++#if defined(PNO_SUPPORT)
++#define PNO_TLV_PREFIX			'S'
++#define PNO_TLV_VERSION			'1'
++#define PNO_TLV_SUBTYPE_LEGACY_PNO '2'
++#define PNO_TLV_RESERVED		'0'
++#define PNO_BATCHING_SET "SET"
++#define PNO_BATCHING_GET "GET"
++#define PNO_BATCHING_STOP "STOP"
++#define PNO_PARAMS_DELIMETER " "
++#define PNO_PARAM_CHANNEL_DELIMETER ","
++#define PNO_PARAM_VALUE_DELLIMETER '='
++#define PNO_PARAM_SCANFREQ "SCANFREQ"
++#define PNO_PARAM_BESTN	"BESTN"
++#define PNO_PARAM_MSCAN "MSCAN"
++#define PNO_PARAM_CHANNEL "CHANNEL"
++#define PNO_PARAM_RTT "RTT"
++
++#define PNO_TLV_TYPE_SSID_IE		'S'
++#define PNO_TLV_TYPE_TIME		'T'
++#define PNO_TLV_FREQ_REPEAT		'R'
++#define PNO_TLV_FREQ_EXPO_MAX		'M'
++
++#define MAXNUM_SSID_PER_ADD	16
++#define MAXNUM_PNO_PARAMS 2
++#define PNO_TLV_COMMON_LENGTH	1
++#define DEFAULT_BATCH_MSCAN 16
++
++#define RESULTS_END_MARKER "----\n"
++#define SCAN_END_MARKER "####\n"
++#define AP_END_MARKER "====\n"
++#define PNO_RSSI_MARGIN_DBM          30
++
++#ifdef GSCAN_SUPPORT
++
++#define GSCAN_MAX_CH_BUCKETS             8
++#define GSCAN_MAX_CHANNELS_IN_BUCKET     32
++#define GSCAN_MAX_AP_CACHE_PER_SCAN      32
++#define GSCAN_MAX_AP_CACHE               320
++#define GSCAN_BG_BAND_MASK             (1 << 0)
++#define GSCAN_A_BAND_MASK              (1 << 1)
++#define GSCAN_DFS_MASK                 (1 << 2)
++#define GSCAN_ABG_BAND_MASK            (GSCAN_A_BAND_MASK | GSCAN_BG_BAND_MASK)
++#define GSCAN_BAND_MASK                (GSCAN_ABG_BAND_MASK | GSCAN_DFS_MASK)
++
++#define GSCAN_FLUSH_HOTLIST_CFG      (1 << 0)
++#define GSCAN_FLUSH_SIGNIFICANT_CFG  (1 << 1)
++#define GSCAN_FLUSH_SCAN_CFG         (1 << 2)
++#define GSCAN_FLUSH_EPNO_CFG         (1 << 3)
++#define GSCAN_FLUSH_ALL_CFG     (GSCAN_FLUSH_SCAN_CFG | \
++								GSCAN_FLUSH_SIGNIFICANT_CFG | \
++								GSCAN_FLUSH_HOTLIST_CFG  | \
++								GSCAN_FLUSH_EPNO_CFG)
++#define DHD_EPNO_HIDDEN_SSID          (1 << 0)
++#define DHD_EPNO_A_BAND_TRIG          (1 << 1)
++#define DHD_EPNO_BG_BAND_TRIG         (1 << 2)
++#define DHD_EPNO_STRICT_MATCH         (1 << 3)
++#define DHD_PNO_USE_SSID              (DHD_EPNO_HIDDEN_SSID | DHD_EPNO_STRICT_MATCH)
++
++/* Do not change GSCAN_BATCH_RETRIEVAL_COMPLETE */
++#define GSCAN_BATCH_RETRIEVAL_COMPLETE      0
++#define GSCAN_BATCH_RETRIEVAL_IN_PROGRESS   1
++#define GSCAN_BATCH_NO_THR_SET              101
++#define GSCAN_LOST_AP_WINDOW_DEFAULT        4
++#define GSCAN_MIN_BSSID_TIMEOUT             90
++#define GSCAN_BATCH_GET_MAX_WAIT            500
++#define CHANNEL_BUCKET_EMPTY_INDEX                      0xFF
++#define GSCAN_RETRY_THRESHOLD              3
++#define MAX_EPNO_SSID_NUM                   32
++#endif /* GSCAN_SUPPORT */
++
++enum scan_status {
++	/* SCAN ABORT by other scan */
++	PNO_STATUS_ABORT,
++	/* RTT is presence or not */
++	PNO_STATUS_RTT_PRESENCE,
++	/* Disable PNO by Driver */
++	PNO_STATUS_DISABLE,
++	/* NORMAL BATCHING GET */
++	PNO_STATUS_NORMAL,
++	/* WLC_E_PFN_BEST_BATCHING */
++	PNO_STATUS_EVENT,
++	PNO_STATUS_MAX
++};
++#define PNO_STATUS_ABORT_MASK 0x0001
++#define PNO_STATUS_RTT_MASK 0x0002
++#define PNO_STATUS_DISABLE_MASK 0x0004
++#define PNO_STATUS_OOM_MASK 0x0010
++
++enum index_mode {
++	INDEX_OF_LEGACY_PARAMS,
++	INDEX_OF_BATCH_PARAMS,
++	INDEX_OF_HOTLIST_PARAMS,
++	/* GSCAN includes hotlist scan and they do not run
++	 * independent of each other
++	 */
++#ifdef GSCAN_SUPPORT
++	INDEX_OF_GSCAN_PARAMS = INDEX_OF_HOTLIST_PARAMS,
++#endif /* GSCAN_SUPPORT */
++	INDEX_MODE_MAX
++};
++enum dhd_pno_status {
++	DHD_PNO_DISABLED,
++	DHD_PNO_ENABLED,
++	DHD_PNO_SUSPEND
++};
++typedef struct cmd_tlv {
++	char prefix;
++	char version;
++	char subtype;
++	char reserved;
++} cmd_tlv_t;
++#ifdef GSCAN_SUPPORT
++typedef enum {
++    WIFI_BAND_UNSPECIFIED,
++    WIFI_BAND_BG = 1,                       /* 2.4 GHz                   */
++    WIFI_BAND_A = 2,                        /* 5 GHz without DFS         */
++    WIFI_BAND_A_DFS = 4,                    /* 5 GHz DFS only            */
++    WIFI_BAND_A_WITH_DFS = 6,               /* 5 GHz with DFS            */
++    WIFI_BAND_ABG = 3,                      /* 2.4 GHz + 5 GHz; no DFS   */
++    WIFI_BAND_ABG_WITH_DFS = 7,             /* 2.4 GHz + 5 GHz with DFS  */
++} gscan_wifi_band_t;
++
++typedef enum {
++	HOTLIST_LOST,
++	HOTLIST_FOUND
++} hotlist_type_t;
++
++typedef enum dhd_pno_gscan_cmd_cfg {
++	DHD_PNO_BATCH_SCAN_CFG_ID = 0,
++	DHD_PNO_GEOFENCE_SCAN_CFG_ID,
++	DHD_PNO_SIGNIFICANT_SCAN_CFG_ID,
++	DHD_PNO_SCAN_CFG_ID,
++	DHD_PNO_GET_CAPABILITIES,
++	DHD_PNO_GET_BATCH_RESULTS,
++	DHD_PNO_GET_CHANNEL_LIST,
++	DHD_PNO_GET_EPNO_SSID_ELEM,
++	DHD_PNO_EPNO_CFG_ID,
++	DHD_PNO_GET_AUTOJOIN_CAPABILITIES
++} dhd_pno_gscan_cmd_cfg_t;
++
++typedef enum dhd_pno_mode {
++	/* Wi-Fi Legacy PNO Mode */
++	DHD_PNO_NONE_MODE   = 0,
++	DHD_PNO_LEGACY_MODE = (1 << (0)),
++	/* Wi-Fi Android BATCH SCAN Mode */
++	DHD_PNO_BATCH_MODE = (1 << (1)),
++	/* Wi-Fi Android Hotlist SCAN Mode */
++	DHD_PNO_HOTLIST_MODE = (1 << (2)),
++	/* Wi-Fi Google Android SCAN Mode */
++	DHD_PNO_GSCAN_MODE = (1 << (3))
++} dhd_pno_mode_t;
++#else
++typedef enum dhd_pno_mode {
++	/* Wi-Fi Legacy PNO Mode */
++	DHD_PNO_NONE_MODE   = 0,
++	DHD_PNO_LEGACY_MODE = (1 << (0)),
++	/* Wi-Fi Android BATCH SCAN Mode */
++	DHD_PNO_BATCH_MODE = (1 << (1)),
++	/* Wi-Fi Android Hotlist SCAN Mode */
++	DHD_PNO_HOTLIST_MODE = (1 << (2))
++} dhd_pno_mode_t;
++#endif /* GSCAN_SUPPORT */
++struct dhd_pno_ssid {
++	bool		hidden;
++	int8		rssi_thresh;
++	uint8		dummy;
++	uint16		SSID_len;
++	uchar		SSID[DOT11_MAX_SSID_LEN];
++	struct list_head list;
++};
++struct dhd_pno_bssid {
++	struct ether_addr	macaddr;
++	/* Bit4: suppress_lost, Bit3: suppress_found */
++	uint16			flags;
++	struct list_head list;
++};
++typedef struct dhd_pno_bestnet_entry {
++	struct ether_addr BSSID;
++	uint8	SSID_len;
++	uint8	SSID[DOT11_MAX_SSID_LEN];
++	int8	RSSI;
++	uint8	channel;
++	uint32	timestamp;
++	uint16	rtt0; /* distance_cm based on RTT */
++	uint16	rtt1; /* distance_cm based on sample standard deviation */
++	unsigned long recorded_time;
++	struct list_head list;
++} dhd_pno_bestnet_entry_t;
++#define BESTNET_ENTRY_SIZE (sizeof(dhd_pno_bestnet_entry_t))
++
++typedef struct dhd_pno_bestnet_header {
++	struct dhd_pno_bestnet_header *next;
++	uint8 reason;
++	uint32 tot_cnt;
++	uint32 tot_size;
++	struct list_head entry_list;
++} dhd_pno_best_header_t;
++#define BEST_HEADER_SIZE (sizeof(dhd_pno_best_header_t))
++
++typedef struct dhd_pno_scan_results {
++	dhd_pno_best_header_t *bestnetheader;
++	uint8 cnt_header;
++	struct list_head list;
++} dhd_pno_scan_results_t;
++#define SCAN_RESULTS_SIZE (sizeof(dhd_pno_scan_results_t))
++
++struct dhd_pno_get_batch_info {
++	/* info related to get batch */
++	char *buf;
++	bool batch_started;
++	uint32 tot_scan_cnt;
++	uint32 expired_tot_scan_cnt;
++	uint32 top_node_cnt;
++	uint32 bufsize;
++	uint32 bytes_written;
++	int reason;
++	struct list_head scan_results_list;
++	struct list_head expired_scan_results_list;
++};
++struct dhd_pno_legacy_params {
++	uint16 scan_fr;
++	uint16 chan_list[WL_NUMCHANNELS];
++	uint16 nchan;
++	int pno_repeat;
++	int pno_freq_expo_max;
++	int nssid;
++	struct list_head ssid_list;
++};
++struct dhd_pno_batch_params {
++	int32 scan_fr;
++	uint8 bestn;
++	uint8 mscan;
++	uint8 band;
++	uint16 chan_list[WL_NUMCHANNELS];
++	uint16 nchan;
++	uint16 rtt;
++	struct dhd_pno_get_batch_info get_batch;
++};
++struct dhd_pno_hotlist_params {
++	uint8 band;
++	int32 scan_fr;
++	uint16 chan_list[WL_NUMCHANNELS];
++	uint16 nchan;
++	uint16 nbssid;
++	struct list_head bssid_list;
++};
++#ifdef GSCAN_SUPPORT
++#define DHD_PNO_REPORT_NO_BATCH      (1 << 2)
++
++typedef struct dhd_pno_gscan_channel_bucket {
++	uint16 bucket_freq_multiple;
++	/* band = 1 All bg band channels,
++	 * band = 2 All a band channels,
++	 * band = 0 chan_list channels
++	 */
++	uint16 band;
++	uint8 report_flag;
++	uint8 num_channels;
++	uint16 repeat;
++	uint16 bucket_max_multiple;
++	uint16 chan_list[GSCAN_MAX_CHANNELS_IN_BUCKET];
++} dhd_pno_gscan_channel_bucket_t;
++
++
++#define DHD_PNO_AUTH_CODE_OPEN  1 /*  Open   */
++#define DHD_PNO_AUTH_CODE_PSK   2 /* WPA_PSK or WPA2PSK */
++#define DHD_PNO_AUTH_CODE_EAPOL 4 /* any EAPOL    */
++
++#define DHD_EPNO_DEFAULT_INDEX     0xFFFFFFFF
++
++typedef struct dhd_epno_params {
++	uint8 ssid[DOT11_MAX_SSID_LEN];
++	uint8 ssid_len;
++	int8 rssi_thresh;
++	uint8 flags;
++	uint8 auth;
++	/* index required only for visble ssid */
++	uint32 index;
++	struct list_head list;
++} dhd_epno_params_t;
++
++typedef struct dhd_epno_results {
++	uint8 ssid[DOT11_MAX_SSID_LEN];
++	uint8 ssid_len;
++	int8 rssi;
++	uint16 channel;
++	uint16 flags;
++	struct ether_addr bssid;
++} dhd_epno_results_t;
++
++typedef struct dhd_pno_swc_evt_param {
++	uint16 results_rxed_so_far;
++	wl_pfn_significant_net_t *change_array;
++} dhd_pno_swc_evt_param_t;
++
++typedef struct wifi_gscan_result {
++	uint64 ts;                           /* Time of discovery           */
++	char ssid[DOT11_MAX_SSID_LEN+1];     /* null terminated             */
++	struct ether_addr	macaddr;         /* BSSID                      */
++	uint32 channel;                      /* channel frequency in MHz    */
++	int32 rssi;                          /* in db                       */
++	uint64 rtt;                          /* in nanoseconds              */
++	uint64 rtt_sd;                       /* standard deviation in rtt   */
++	uint16 beacon_period;                /* units are Kusec             */
++	uint16 capability;                   /* Capability information       */
++	uint32 ie_length;                    /* byte length of Information Elements */
++	char  ie_data[1];                    /* IE data to follow       */
++} wifi_gscan_result_t;
++
++typedef struct gscan_results_cache {
++	struct gscan_results_cache *next;
++	uint8  scan_id;
++	uint8  flag;
++	uint8  tot_count;
++	uint8  tot_consumed;
++	wifi_gscan_result_t results[1];
++} gscan_results_cache_t;
++
++typedef struct dhd_pno_gscan_capabilities {
++	int max_scan_cache_size;
++	int max_scan_buckets;
++	int max_ap_cache_per_scan;
++	int max_rssi_sample_size;
++	int max_scan_reporting_threshold;
++	int max_hotlist_aps;
++	int max_significant_wifi_change_aps;
++	int max_epno_ssid_crc32;
++	int max_epno_hidden_ssid;
++	int max_white_list_ssid;
++} dhd_pno_gscan_capabilities_t;
++
++struct dhd_pno_gscan_params {
++	int32 scan_fr;
++	uint8 bestn;
++	uint8 mscan;
++	uint8 buffer_threshold;
++	uint8 swc_nbssid_threshold;
++	uint8 swc_rssi_window_size;
++	uint8 lost_ap_window;
++	uint8 nchannel_buckets;
++	uint8 reason;
++	uint8 get_batch_flag;
++	uint8 send_all_results_flag;
++	uint16 max_ch_bucket_freq;
++	gscan_results_cache_t *gscan_batch_cache;
++	gscan_results_cache_t *gscan_hotlist_found;
++	gscan_results_cache_t *gscan_hotlist_lost;
++	uint16 nbssid_significant_change;
++	uint16 nbssid_hotlist;
++	uint16 num_epno_ssid;
++	uint8 num_visible_epno_ssid;
++	/* To keep track of visble ssid index
++	 * across multiple FW configs i.e. config
++	 * w/o clear in between
++	 */
++	uint8 ssid_ext_last_used_index;
++	struct dhd_pno_swc_evt_param param_significant;
++	struct dhd_pno_gscan_channel_bucket channel_bucket[GSCAN_MAX_CH_BUCKETS];
++	struct list_head hotlist_bssid_list;
++	struct list_head significant_bssid_list;
++	struct list_head epno_ssid_list;
++	uint32 scan_id;
++};
++
++typedef struct gscan_scan_params {
++	int32 scan_fr;
++	uint16 nchannel_buckets;
++	struct dhd_pno_gscan_channel_bucket channel_bucket[GSCAN_MAX_CH_BUCKETS];
++} gscan_scan_params_t;
++
++typedef struct gscan_batch_params {
++	uint8 bestn;
++	uint8 mscan;
++	uint8 buffer_threshold;
++} gscan_batch_params_t;
++
++struct bssid_t {
++	struct ether_addr	macaddr;
++	int16 rssi_reporting_threshold;  /* 0 -> no reporting threshold */
++};
++
++typedef struct gscan_hotlist_scan_params {
++	uint16 lost_ap_window; /* number of scans to declare LOST */
++	uint16 nbssid;   /* number of bssids  */
++	struct bssid_t bssid[1];  /* n bssids to follow */
++} gscan_hotlist_scan_params_t;
++
++/* SWC (Significant WiFi Change) params */
++typedef struct gscan_swc_params {
++	/* Rssi averaging window size */
++	uint8 rssi_window;
++	/* Number of scans that the AP has to be absent before
++	 * being declared LOST
++	 */
++	uint8 lost_ap_window;
++	/* if x  Aps have a significant change generate an event. */
++	uint8 swc_threshold;
++	uint8 nbssid;
++	wl_pfn_significant_bssid_t bssid_elem_list[1];
++} gscan_swc_params_t;
++
++typedef struct dhd_pno_significant_bssid {
++	struct ether_addr BSSID;
++	int8 rssi_low_threshold;
++	int8 rssi_high_threshold;
++	struct list_head list;
++} dhd_pno_significant_bssid_t;
++#endif /* GSCAN_SUPPORT */
++typedef union dhd_pno_params {
++	struct dhd_pno_legacy_params params_legacy;
++	struct dhd_pno_batch_params params_batch;
++	struct dhd_pno_hotlist_params params_hotlist;
++#ifdef GSCAN_SUPPORT
++	struct dhd_pno_gscan_params params_gscan;
++#endif /* GSCAN_SUPPORT */
++} dhd_pno_params_t;
++typedef struct dhd_pno_status_info {
++	dhd_pub_t *dhd;
++	struct work_struct work;
++	struct mutex pno_mutex;
++#ifdef GSCAN_SUPPORT
++	wait_queue_head_t batch_get_wait;
++#endif /* GSCAN_SUPPORT */
++	struct completion get_batch_done;
++	bool wls_supported; /* wifi location service supported or not */
++	enum dhd_pno_status pno_status;
++	enum dhd_pno_mode pno_mode;
++	dhd_pno_params_t pno_params_arr[INDEX_MODE_MAX];
++	struct list_head head_list;
++} dhd_pno_status_info_t;
++
++/* wrapper functions */
++extern int
++dhd_dev_pno_enable(struct net_device *dev, int enable);
++
++extern int
++dhd_dev_pno_stop_for_ssid(struct net_device *dev);
++
++extern int
++dhd_dev_pno_set_for_ssid(struct net_device *dev, wlc_ssid_ext_t* ssids_local, int nssid,
++	uint16 scan_fr, int pno_repeat, int pno_freq_expo_max, uint16 *channel_list, int nchan);
++
++extern int
++dhd_dev_pno_set_for_batch(struct net_device *dev,
++	struct dhd_pno_batch_params *batch_params);
++
++extern int
++dhd_dev_pno_get_for_batch(struct net_device *dev, char *buf, int bufsize);
++
++extern int
++dhd_dev_pno_stop_for_batch(struct net_device *dev);
++
++extern int
++dhd_dev_pno_set_for_hotlist(struct net_device *dev, wl_pfn_bssid_t *p_pfn_bssid,
++	struct dhd_pno_hotlist_params *hotlist_params);
++extern bool dhd_dev_is_legacy_pno_enabled(struct net_device *dev);
++#ifdef GSCAN_SUPPORT
++extern int
++dhd_dev_pno_set_cfg_gscan(struct net_device *dev, dhd_pno_gscan_cmd_cfg_t type,
++              void *buf, uint8 flush);
++extern void *
++dhd_dev_pno_get_gscan(struct net_device *dev, dhd_pno_gscan_cmd_cfg_t type, void *info,
++        uint32 *len);
++int dhd_dev_pno_lock_access_batch_results(struct net_device *dev);
++void dhd_dev_pno_unlock_access_batch_results(struct net_device *dev);
++extern int dhd_dev_pno_run_gscan(struct net_device *dev, bool run, bool flush);
++extern int dhd_dev_pno_enable_full_scan_result(struct net_device *dev, bool real_time);
++extern void * dhd_dev_swc_scan_event(struct net_device *dev, const void  *data,
++              int *send_evt_bytes);
++int dhd_retreive_batch_scan_results(dhd_pub_t *dhd);
++extern void * dhd_dev_hotlist_scan_event(struct net_device *dev,
++            const void  *data, int *send_evt_bytes, hotlist_type_t type);
++void * dhd_dev_process_full_gscan_result(struct net_device *dev,
++            const void  *data, uint32 len, int *send_evt_bytes);
++extern int dhd_dev_gscan_batch_cache_cleanup(struct net_device *dev);
++extern void dhd_dev_gscan_hotlist_cache_cleanup(struct net_device *dev, hotlist_type_t type);
++extern int dhd_dev_wait_batch_results_complete(struct net_device *dev);
++extern void * dhd_dev_process_epno_result(struct net_device *dev,
++                        const void  *data, uint32 event, int *send_evt_bytes);
++#endif /* GSCAN_SUPPORT */
++/* dhd pno fuctions */
++extern int dhd_pno_stop_for_ssid(dhd_pub_t *dhd);
++extern int dhd_pno_enable(dhd_pub_t *dhd, int enable);
++extern int dhd_pno_set_for_ssid(dhd_pub_t *dhd, wlc_ssid_ext_t* ssid_list, int nssid,
++	uint16  scan_fr, int pno_repeat, int pno_freq_expo_max, uint16 *channel_list, int nchan);
++
++extern int dhd_pno_set_for_batch(dhd_pub_t *dhd, struct dhd_pno_batch_params *batch_params);
++
++extern int dhd_pno_get_for_batch(dhd_pub_t *dhd, char *buf, int bufsize, int reason);
++
++
++extern int dhd_pno_stop_for_batch(dhd_pub_t *dhd);
++
++extern int dhd_pno_set_for_hotlist(dhd_pub_t *dhd, wl_pfn_bssid_t *p_pfn_bssid,
++	struct dhd_pno_hotlist_params *hotlist_params);
++
++extern int dhd_pno_stop_for_hotlist(dhd_pub_t *dhd);
++
++extern int dhd_pno_event_handler(dhd_pub_t *dhd, wl_event_msg_t *event, void *event_data);
++extern int dhd_pno_init(dhd_pub_t *dhd);
++extern int dhd_pno_deinit(dhd_pub_t *dhd);
++extern bool dhd_is_pno_supported(dhd_pub_t *dhd);
++extern int dhd_pno_set_mac_oui(dhd_pub_t *dhd, uint8 *oui);
++extern bool dhd_is_legacy_pno_enabled(dhd_pub_t *dhd);
++#ifdef GSCAN_SUPPORT
++extern int dhd_pno_set_cfg_gscan(dhd_pub_t *dhd, dhd_pno_gscan_cmd_cfg_t type,
++                       void *buf, uint8 flush);
++extern void * dhd_pno_get_gscan(dhd_pub_t *dhd, dhd_pno_gscan_cmd_cfg_t type, void *info,
++                       uint32 *len);
++extern int dhd_pno_lock_batch_results(dhd_pub_t *dhd);
++extern void dhd_pno_unlock_batch_results(dhd_pub_t *dhd);
++extern int dhd_pno_initiate_gscan_request(dhd_pub_t *dhd, bool run, bool flush);
++extern int dhd_pno_enable_full_scan_result(dhd_pub_t *dhd, bool real_time_flag);
++extern int dhd_pno_cfg_gscan(dhd_pub_t *dhd, dhd_pno_gscan_cmd_cfg_t type, void *buf);
++extern int dhd_dev_retrieve_batch_scan(struct net_device *dev);
++extern void *dhd_handle_swc_evt(dhd_pub_t *dhd, const void *event_data, int *send_evt_bytes);
++extern void *dhd_handle_hotlist_scan_evt(dhd_pub_t *dhd, const void *event_data,
++                       int *send_evt_bytes, hotlist_type_t type);
++extern void *dhd_process_full_gscan_result(dhd_pub_t *dhd, const void *event_data,
++                       uint32 len, int *send_evt_bytes);
++extern int dhd_gscan_batch_cache_cleanup(dhd_pub_t *dhd);
++extern void dhd_gscan_hotlist_cache_cleanup(dhd_pub_t *dhd, hotlist_type_t type);
++extern int dhd_wait_batch_results_complete(dhd_pub_t *dhd);
++extern void * dhd_pno_process_epno_result(dhd_pub_t *dhd, const void *data,
++         uint32 event, int *size);
++#endif /* GSCAN_SUPPORT */
++#endif 
++
++#endif /* __DHD_PNO_H__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_proto.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_proto.h
+new file mode 100644
+index 000000000..65dde60bd
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_proto.h
+@@ -0,0 +1,168 @@
++/*
++ * Header file describing the internal (inter-module) DHD interfaces.
++ *
++ * Provides type definitions and function prototypes used to link the
++ * DHD OS, bus, and protocol modules.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_proto.h 593174 2015-10-15 13:05:37Z $
++ */
++
++#ifndef _dhd_proto_h_
++#define _dhd_proto_h_
++
++#include <dhdioctl.h>
++#include <wlioctl.h>
++#ifdef BCMPCIE
++#include <dhd_flowring.h>
++#endif
++
++#define DEFAULT_IOCTL_RESP_TIMEOUT	2000
++#ifndef IOCTL_RESP_TIMEOUT
++/* In milli second default value for Production FW */
++#define IOCTL_RESP_TIMEOUT  DEFAULT_IOCTL_RESP_TIMEOUT
++#endif /* IOCTL_RESP_TIMEOUT */
++
++#ifndef MFG_IOCTL_RESP_TIMEOUT
++#define MFG_IOCTL_RESP_TIMEOUT  20000  /* In milli second default value for MFG FW */
++#endif /* MFG_IOCTL_RESP_TIMEOUT */
++
++#define DEFAULT_D3_ACK_RESP_TIMEOUT	4000
++#ifndef D3_ACK_RESP_TIMEOUT
++#define D3_ACK_RESP_TIMEOUT		DEFAULT_D3_ACK_RESP_TIMEOUT
++#endif /* D3_ACK_RESP_TIMEOUT */
++
++#define DEFAULT_DHD_BUS_BUSY_TIMEOUT	(IOCTL_RESP_TIMEOUT + 1000)
++#ifndef DHD_BUS_BUSY_TIMEOUT
++#define DHD_BUS_BUSY_TIMEOUT	DEFAULT_DHD_BUS_BUSY_TIMEOUT
++#endif /* DEFAULT_DHD_BUS_BUSY_TIMEOUT */
++
++#define IOCTL_DISABLE_TIMEOUT 0
++/*
++ * Exported from the dhd protocol module (dhd_cdc, dhd_rndis)
++ */
++
++/* Linkage, sets prot link and updates hdrlen in pub */
++extern int dhd_prot_attach(dhd_pub_t *dhdp);
++
++/* Initilizes the index block for dma'ing indices */
++extern int dhd_prot_dma_indx_init(dhd_pub_t *dhdp, uint32 rw_index_sz,
++	uint8 type, uint32 length);
++
++/* Unlink, frees allocated protocol memory (including dhd_prot) */
++extern void dhd_prot_detach(dhd_pub_t *dhdp);
++
++/* Initialize protocol: sync w/dongle state.
++ * Sets dongle media info (iswl, drv_version, mac address).
++ */
++extern int dhd_sync_with_dongle(dhd_pub_t *dhdp);
++
++/* Protocol initialization needed for IOCTL/IOVAR path */
++extern int dhd_prot_init(dhd_pub_t *dhd);
++
++/* Stop protocol: sync w/dongle state. */
++extern void dhd_prot_stop(dhd_pub_t *dhdp);
++
++/* Add any protocol-specific data header.
++ * Caller must reserve prot_hdrlen prepend space.
++ */
++extern void dhd_prot_hdrpush(dhd_pub_t *, int ifidx, void *txp);
++extern uint dhd_prot_hdrlen(dhd_pub_t *, void *txp);
++
++/* Remove any protocol-specific data header. */
++extern int dhd_prot_hdrpull(dhd_pub_t *, int *ifidx, void *rxp, uchar *buf, uint *len);
++
++/* Use protocol to issue ioctl to dongle */
++extern int dhd_prot_ioctl(dhd_pub_t *dhd, int ifidx, wl_ioctl_t * ioc, void * buf, int len);
++
++/* Handles a protocol control response asynchronously */
++extern int dhd_prot_ctl_complete(dhd_pub_t *dhd);
++
++/* Check for and handle local prot-specific iovar commands */
++extern int dhd_prot_iovar_op(dhd_pub_t *dhdp, const char *name,
++                             void *params, int plen, void *arg, int len, bool set);
++
++/* Add prot dump output to a buffer */
++extern void dhd_prot_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf);
++
++/* Update local copy of dongle statistics */
++extern void dhd_prot_dstats(dhd_pub_t *dhdp);
++
++extern int dhd_ioctl(dhd_pub_t * dhd_pub, dhd_ioctl_t *ioc, void * buf, uint buflen);
++
++extern int dhd_preinit_ioctls(dhd_pub_t *dhd);
++
++extern int dhd_process_pkt_reorder_info(dhd_pub_t *dhd, uchar *reorder_info_buf,
++	uint reorder_info_len, void **pkt, uint32 *free_buf_count);
++
++#ifdef BCMPCIE
++extern bool dhd_prot_process_msgbuf_txcpl(dhd_pub_t *dhd, uint bound);
++extern bool dhd_prot_process_msgbuf_rxcpl(dhd_pub_t *dhd, uint bound);
++extern int dhd_prot_process_ctrlbuf(dhd_pub_t * dhd);
++extern bool dhd_prot_dtohsplit(dhd_pub_t * dhd);
++extern int dhd_post_dummy_msg(dhd_pub_t *dhd);
++extern int dhdmsgbuf_lpbk_req(dhd_pub_t *dhd, uint len);
++extern void dhd_prot_rx_dataoffset(dhd_pub_t *dhd, uint32 offset);
++extern int dhd_prot_txdata(dhd_pub_t *dhd, void *p, uint8 ifidx);
++extern int dhdmsgbuf_dmaxfer_req(dhd_pub_t *dhd, uint len, uint srcdelay, uint destdelay);
++
++extern void dhd_dma_buf_init(dhd_pub_t *dhd, void *dma_buf,
++	void *va, uint32 len, dmaaddr_t pa, void *dmah, void *secdma);
++extern void dhd_prot_flowrings_pool_release(dhd_pub_t *dhd,
++	uint16 flowid, void *msgbuf_ring);
++extern int dhd_prot_flow_ring_create(dhd_pub_t *dhd, flow_ring_node_t *flow_ring_node);
++extern int dhd_post_tx_ring_item(dhd_pub_t *dhd, void *PKTBUF, uint8 ifindex);
++extern int dhd_prot_flow_ring_delete(dhd_pub_t *dhd, flow_ring_node_t *flow_ring_node);
++extern int dhd_prot_flow_ring_flush(dhd_pub_t *dhd, flow_ring_node_t *flow_ring_node);
++extern int dhd_prot_ringupd_dump(dhd_pub_t *dhd, struct bcmstrbuf *b);
++extern uint32 dhd_prot_metadata_dbg_set(dhd_pub_t *dhd, bool val);
++extern uint32 dhd_prot_metadata_dbg_get(dhd_pub_t *dhd);
++extern uint32 dhd_prot_metadatalen_set(dhd_pub_t *dhd, uint32 val, bool rx);
++extern uint32 dhd_prot_metadatalen_get(dhd_pub_t *dhd, bool rx);
++extern void dhd_prot_print_flow_ring(dhd_pub_t *dhd, void *msgbuf_flow_info,
++	struct bcmstrbuf *strbuf, const char * fmt);
++extern void dhd_prot_print_info(dhd_pub_t *dhd, struct bcmstrbuf *strbuf);
++extern void dhd_prot_update_txflowring(dhd_pub_t *dhdp, uint16 flow_id, void *msgring_info);
++extern void dhd_prot_txdata_write_flush(dhd_pub_t *dhd, uint16 flow_id, bool in_lock);
++extern uint32 dhd_prot_txp_threshold(dhd_pub_t *dhd, bool set, uint32 val);
++extern void dhd_prot_reset(dhd_pub_t *dhd);
++#ifdef DHD_LB
++extern void dhd_lb_tx_compl_handler(unsigned long data);
++extern void dhd_lb_rx_compl_handler(unsigned long data);
++extern void dhd_lb_rx_process_handler(unsigned long data);
++#endif /* DHD_LB */
++#endif /* BCMPCIE */
++/********************************
++ * For version-string expansion *
++ */
++#if defined(BDC)
++#define DHD_PROTOCOL "bdc"
++#elif defined(CDC)
++#define DHD_PROTOCOL "cdc"
++#else
++#define DHD_PROTOCOL "unknown"
++#endif /* proto */
++
++#endif /* _dhd_proto_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_rtt.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_rtt.c
+new file mode 100644
+index 000000000..3406a30ea
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_rtt.c
+@@ -0,0 +1,2063 @@
++/*
++ * Broadcom Dongle Host Driver (DHD), RTT
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * $Id: dhd_rtt.c 674349 2017-10-19 07:59:24Z $
++ */
++#include <typedefs.h>
++#include <osl.h>
++
++#include <epivers.h>
++#include <bcmutils.h>
++
++#include <bcmendian.h>
++#include <linuxver.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/sort.h>
++#include <dngl_stats.h>
++#include <wlioctl.h>
++
++#include <proto/bcmevent.h>
++#include <dhd.h>
++#include <dhd_rtt.h>
++#include <dhd_dbg.h>
++#define GET_RTTSTATE(dhd) ((rtt_status_info_t *)dhd->rtt_state)
++static DEFINE_SPINLOCK(noti_list_lock);
++#define NULL_CHECK(p, s, err)  \
++			do { \
++				if (!(p)) { \
++					printf("NULL POINTER (%s) : %s\n", __FUNCTION__, (s)); \
++					err = BCME_ERROR; \
++					return err; \
++				} \
++			} while (0)
++
++#define RTT_IS_ENABLED(rtt_status) (rtt_status->status == RTT_ENABLED)
++#define RTT_IS_STOPPED(rtt_status) (rtt_status->status == RTT_STOPPED)
++#define TIMESPEC_TO_US(ts)  (((uint64)(ts).tv_sec * USEC_PER_SEC) + \
++							(ts).tv_nsec / NSEC_PER_USEC)
++
++#define FTM_IOC_BUFSZ  2048	/* ioc buffsize for our module (> BCM_XTLV_HDR_SIZE) */
++#define FTM_AVAIL_MAX_SLOTS		32
++#define FTM_MAX_CONFIGS 10
++#define FTM_MAX_PARAMS 10
++#define FTM_DEFAULT_SESSION 1
++#define FTM_BURST_TIMEOUT_UNIT 250 /* 250 ns */
++#define FTM_INVALID -1
++#define	FTM_DEFAULT_CNT_20M		12
++#define FTM_DEFAULT_CNT_40M		10
++#define FTM_DEFAULT_CNT_80M		5
++
++/* convenience macros */
++#define FTM_TU2MICRO(_tu) ((uint64)(_tu) << 10)
++#define FTM_MICRO2TU(_tu) ((uint64)(_tu) >> 10)
++#define FTM_TU2MILLI(_tu) ((uint32)FTM_TU2MICRO(_tu) / 1000)
++#define FTM_MICRO2MILLI(_x) ((uint32)(_x) / 1000)
++#define FTM_MICRO2SEC(_x) ((uint32)(_x) / 1000000)
++#define FTM_INTVL2NSEC(_intvl) ((uint32)ftm_intvl2nsec(_intvl))
++#define FTM_INTVL2USEC(_intvl) ((uint32)ftm_intvl2usec(_intvl))
++#define FTM_INTVL2MSEC(_intvl) (FTM_INTVL2USEC(_intvl) / 1000)
++#define FTM_INTVL2SEC(_intvl) (FTM_INTVL2USEC(_intvl) / 1000000)
++#define FTM_USECIN100MILLI(_usec) ((_usec) / 100000)
++
++/* broadcom specific set to have more accurate data */
++#define ENABLE_VHT_ACK
++
++struct rtt_noti_callback {
++	struct list_head list;
++	void *ctx;
++	dhd_rtt_compl_noti_fn noti_fn;
++};
++
++typedef struct rtt_status_info {
++	dhd_pub_t *dhd;
++	int8 status;   /* current status for the current entry */
++	int8 txchain; /* current device tx chain */
++	int8 mpc; /* indicate we change mpc mode */
++	int8 cur_idx; /* current entry to do RTT */
++	bool all_cancel; /* cancel all request once we got the cancel requet */
++	struct capability {
++		int32 proto	:8;
++		int32 feature	:8;
++		int32 preamble	:8;
++		int32 bw	:8;
++	} rtt_capa; /* rtt capability */
++	struct mutex rtt_mutex;
++	rtt_config_params_t rtt_config;
++	struct work_struct work;
++	struct list_head noti_fn_list;
++	struct list_head rtt_results_cache; /* store results for RTT */
++} rtt_status_info_t;
++
++/* bitmask indicating which command groups; */
++typedef enum {
++	FTM_SUBCMD_FLAG_METHOD	= 0x01,	/* FTM method command */
++	FTM_SUBCMD_FLAG_SESSION	= 0x02,	/* FTM session command */
++	FTM_SUBCMD_FLAG_ALL = FTM_SUBCMD_FLAG_METHOD | FTM_SUBCMD_FLAG_SESSION
++} ftm_subcmd_flag_t;
++
++/* proxd ftm config-category definition */
++typedef enum {
++	FTM_CONFIG_CAT_GENERAL = 1,	/* generial configuration */
++	FTM_CONFIG_CAT_OPTIONS = 2,	/* 'config options' */
++	FTM_CONFIG_CAT_AVAIL = 3,	/* 'config avail' */
++} ftm_config_category_t;
++
++
++typedef struct ftm_subcmd_info {
++	int16				version;    /* FTM version (optional) */
++	char				*name;		/* cmd-name string as cmdline input */
++	wl_proxd_cmd_t		cmdid;		/* cmd-id */
++	bcm_xtlv_unpack_cbfn_t *handler;  /* cmd response handler (optional) */
++	ftm_subcmd_flag_t	cmdflag; /* CMD flag (optional)  */
++} ftm_subcmd_info_t;
++
++
++typedef struct ftm_config_options_info {
++	uint32 flags;		/* wl_proxd_flags_t/wl_proxd_session_flags_t */
++	bool enable;
++} ftm_config_options_info_t;
++
++typedef struct ftm_config_param_info {
++	uint16		tlvid;	/* mapping TLV id for the item */
++	union {
++		uint32  chanspec;
++		struct ether_addr mac_addr;
++		wl_proxd_intvl_t data_intvl;
++		uint32 data32;
++		uint16 data16;
++		uint8 data8;
++	};
++} ftm_config_param_info_t;
++
++/*
++* definition for id-string mapping.
++* This is used to map an id (can be cmd-id, tlv-id, ....) to a text-string
++* for debug-display or cmd-log-display
++*/
++typedef struct ftm_strmap_entry {
++	int32		id;
++	char		*text;
++} ftm_strmap_entry_t;
++
++
++typedef struct ftm_status_map_host_entry {
++	wl_proxd_status_t proxd_status;
++	rtt_reason_t rtt_reason;
++} ftm_status_map_host_entry_t;
++
++static int
++dhd_rtt_convert_results_to_host(rtt_report_t *rtt_report, uint8 *p_data, uint16 tlvid, uint16 len);
++
++static wifi_rate_t
++dhd_rtt_convert_rate_to_host(uint32 ratespec);
++
++static int
++dhd_rtt_start(dhd_pub_t *dhd);
++static const int burst_duration_idx[]  = {0, 0, 1, 2, 4, 8, 16, 32, 64, 128, 0, 0};
++
++/* ftm status mapping to host status */
++static const ftm_status_map_host_entry_t ftm_status_map_info[] = {
++	{WL_PROXD_E_INCOMPLETE, RTT_REASON_FAILURE},
++	{WL_PROXD_E_OVERRIDDEN, RTT_REASON_FAILURE},
++	{WL_PROXD_E_ASAP_FAILED, RTT_REASON_FAILURE},
++	{WL_PROXD_E_NOTSTARTED, RTT_REASON_FAIL_NOT_SCHEDULED_YET},
++	{WL_PROXD_E_INVALIDAVB, RTT_REASON_FAIL_INVALID_TS},
++	{WL_PROXD_E_INCAPABLE, RTT_REASON_FAIL_NO_CAPABILITY},
++	{WL_PROXD_E_MISMATCH, RTT_REASON_FAILURE},
++	{WL_PROXD_E_DUP_SESSION, RTT_REASON_FAILURE},
++	{WL_PROXD_E_REMOTE_FAIL, RTT_REASON_FAILURE},
++	{WL_PROXD_E_REMOTE_INCAPABLE, RTT_REASON_FAILURE},
++	{WL_PROXD_E_SCHED_FAIL, RTT_REASON_FAIL_SCHEDULE},
++	{WL_PROXD_E_PROTO, RTT_REASON_FAIL_PROTOCOL},
++	{WL_PROXD_E_EXPIRED, RTT_REASON_FAILURE},
++	{WL_PROXD_E_TIMEOUT, RTT_REASON_FAIL_TM_TIMEOUT},
++	{WL_PROXD_E_NOACK, RTT_REASON_FAIL_NO_RSP},
++	{WL_PROXD_E_DEFERRED, RTT_REASON_FAILURE},
++	{WL_PROXD_E_INVALID_SID, RTT_REASON_FAILURE},
++	{WL_PROXD_E_REMOTE_CANCEL, RTT_REASON_FAILURE},
++	{WL_PROXD_E_CANCELED, RTT_REASON_ABORTED},
++	{WL_PROXD_E_INVALID_SESSION, RTT_REASON_FAILURE},
++	{WL_PROXD_E_BAD_STATE, RTT_REASON_FAILURE},
++	{WL_PROXD_E_ERROR, RTT_REASON_FAILURE},
++	{WL_PROXD_E_OK, RTT_REASON_SUCCESS}
++};
++
++/* ftm tlv-id mapping */
++static const ftm_strmap_entry_t ftm_tlvid_loginfo[] = {
++	/* { WL_PROXD_TLV_ID_xxx,				"text for WL_PROXD_TLV_ID_xxx" }, */
++	{ WL_PROXD_TLV_ID_NONE,					"none" },
++	{ WL_PROXD_TLV_ID_METHOD,				"method" },
++	{ WL_PROXD_TLV_ID_FLAGS,				"flags" },
++	{ WL_PROXD_TLV_ID_CHANSPEC,				"chanspec" },
++	{ WL_PROXD_TLV_ID_TX_POWER,				"tx power" },
++	{ WL_PROXD_TLV_ID_RATESPEC,				"ratespec" },
++	{ WL_PROXD_TLV_ID_BURST_DURATION,		"burst duration" },
++	{ WL_PROXD_TLV_ID_BURST_PERIOD,			"burst period" },
++	{ WL_PROXD_TLV_ID_BURST_FTM_SEP,		"burst ftm sep" },
++	{ WL_PROXD_TLV_ID_BURST_NUM_FTM,		"burst num ftm" },
++	{ WL_PROXD_TLV_ID_NUM_BURST,			"num burst" },
++	{ WL_PROXD_TLV_ID_FTM_RETRIES,			"ftm retries" },
++	{ WL_PROXD_TLV_ID_BSS_INDEX,			"BSS index" },
++	{ WL_PROXD_TLV_ID_BSSID,				"bssid" },
++	{ WL_PROXD_TLV_ID_INIT_DELAY,			"burst init delay" },
++	{ WL_PROXD_TLV_ID_BURST_TIMEOUT,		"burst timeout" },
++	{ WL_PROXD_TLV_ID_EVENT_MASK,			"event mask" },
++	{ WL_PROXD_TLV_ID_FLAGS_MASK,			"flags mask" },
++	{ WL_PROXD_TLV_ID_PEER_MAC,				"peer addr" },
++	{ WL_PROXD_TLV_ID_FTM_REQ,				"ftm req" },
++	{ WL_PROXD_TLV_ID_LCI_REQ,				"lci req" },
++	{ WL_PROXD_TLV_ID_LCI,					"lci" },
++	{ WL_PROXD_TLV_ID_CIVIC_REQ,			"civic req" },
++	{ WL_PROXD_TLV_ID_CIVIC,				"civic" },
++	{ WL_PROXD_TLV_ID_AVAIL,				"availability" },
++	{ WL_PROXD_TLV_ID_SESSION_FLAGS,		"session flags" },
++	{ WL_PROXD_TLV_ID_SESSION_FLAGS_MASK,	"session flags mask" },
++	{ WL_PROXD_TLV_ID_RX_MAX_BURST,			"rx max bursts" },
++	{ WL_PROXD_TLV_ID_RANGING_INFO,			"ranging info" },
++	{ WL_PROXD_TLV_ID_RANGING_FLAGS,		"ranging flags" },
++	{ WL_PROXD_TLV_ID_RANGING_FLAGS_MASK,	"ranging flags mask" },
++	/* output - 512 + x */
++	{ WL_PROXD_TLV_ID_STATUS,				"status" },
++	{ WL_PROXD_TLV_ID_COUNTERS,				"counters" },
++	{ WL_PROXD_TLV_ID_INFO,					"info" },
++	{ WL_PROXD_TLV_ID_RTT_RESULT,			"rtt result" },
++	{ WL_PROXD_TLV_ID_AOA_RESULT,			"aoa result" },
++	{ WL_PROXD_TLV_ID_SESSION_INFO,			"session info" },
++	{ WL_PROXD_TLV_ID_SESSION_STATUS,		"session status" },
++	{ WL_PROXD_TLV_ID_SESSION_ID_LIST,		"session ids" },
++	/* debug tlvs can be added starting 1024 */
++	{ WL_PROXD_TLV_ID_DEBUG_MASK,			"debug mask" },
++	{ WL_PROXD_TLV_ID_COLLECT,				"collect" },
++	{ WL_PROXD_TLV_ID_STRBUF,				"result" }
++};
++
++static const ftm_strmap_entry_t ftm_event_type_loginfo[] = {
++	/* wl_proxd_event_type_t,			text-string */
++	{ WL_PROXD_EVENT_NONE,				"none" },
++	{ WL_PROXD_EVENT_SESSION_CREATE,	"session create" },
++	{ WL_PROXD_EVENT_SESSION_START,		"session start" },
++	{ WL_PROXD_EVENT_FTM_REQ,			"FTM req" },
++	{ WL_PROXD_EVENT_BURST_START,		"burst start" },
++	{ WL_PROXD_EVENT_BURST_END,			"burst end" },
++	{ WL_PROXD_EVENT_SESSION_END,		"session end" },
++	{ WL_PROXD_EVENT_SESSION_RESTART,	"session restart" },
++	{ WL_PROXD_EVENT_BURST_RESCHED,		"burst rescheduled" },
++	{ WL_PROXD_EVENT_SESSION_DESTROY,	"session destroy" },
++	{ WL_PROXD_EVENT_RANGE_REQ,			"range request" },
++	{ WL_PROXD_EVENT_FTM_FRAME,			"FTM frame" },
++	{ WL_PROXD_EVENT_DELAY,				"delay" },
++	{ WL_PROXD_EVENT_VS_INITIATOR_RPT,	"initiator-report " }, /* rx initiator-rpt */
++	{ WL_PROXD_EVENT_RANGING,			"ranging " },
++};
++
++/*
++* session-state --> text string mapping
++*/
++static const ftm_strmap_entry_t ftm_session_state_value_loginfo[] = {
++	/* wl_proxd_session_state_t,			text string */
++	{ WL_PROXD_SESSION_STATE_CREATED,		"created" },
++	{ WL_PROXD_SESSION_STATE_CONFIGURED,	"configured" },
++	{ WL_PROXD_SESSION_STATE_STARTED,		"started" },
++	{ WL_PROXD_SESSION_STATE_DELAY,			"delay" },
++	{ WL_PROXD_SESSION_STATE_USER_WAIT,		"user-wait" },
++	{ WL_PROXD_SESSION_STATE_SCHED_WAIT,	"sched-wait" },
++	{ WL_PROXD_SESSION_STATE_BURST,			"burst" },
++	{ WL_PROXD_SESSION_STATE_STOPPING,		"stopping" },
++	{ WL_PROXD_SESSION_STATE_ENDED,			"ended" },
++	{ WL_PROXD_SESSION_STATE_DESTROYING,	"destroying" },
++	{ WL_PROXD_SESSION_STATE_NONE,			"none" }
++};
++
++/*
++* ranging-state --> text string mapping
++*/
++static const ftm_strmap_entry_t ftm_ranging_state_value_loginfo [] = {
++	/* wl_proxd_ranging_state_t,			text string */
++		{ WL_PROXD_RANGING_STATE_NONE, "none" },
++		{ WL_PROXD_RANGING_STATE_NOTSTARTED, "nonstarted" },
++		{ WL_PROXD_RANGING_STATE_INPROGRESS, "inprogress" },
++		{ WL_PROXD_RANGING_STATE_DONE, "done" },
++};
++
++/*
++* status --> text string mapping
++*/
++static const ftm_strmap_entry_t ftm_status_value_loginfo[] = {
++	/* wl_proxd_status_t,			text-string */
++	{ WL_PROXD_E_OVERRIDDEN,		"overridden" },
++	{ WL_PROXD_E_ASAP_FAILED,		"ASAP failed" },
++	{ WL_PROXD_E_NOTSTARTED,		"not started" },
++	{ WL_PROXD_E_INVALIDAVB,		"invalid AVB" },
++	{ WL_PROXD_E_INCAPABLE,		"incapable" },
++	{ WL_PROXD_E_MISMATCH,		"mismatch"},
++	{ WL_PROXD_E_DUP_SESSION,		"dup session" },
++	{ WL_PROXD_E_REMOTE_FAIL,		"remote fail" },
++	{ WL_PROXD_E_REMOTE_INCAPABLE,	"remote incapable" },
++	{ WL_PROXD_E_SCHED_FAIL,		"sched failure" },
++	{ WL_PROXD_E_PROTO,			"protocol error" },
++	{ WL_PROXD_E_EXPIRED,			"expired" },
++	{ WL_PROXD_E_TIMEOUT,			"timeout" },
++	{ WL_PROXD_E_NOACK,			"no ack" },
++	{ WL_PROXD_E_DEFERRED,		"deferred" },
++	{ WL_PROXD_E_INVALID_SID,		"invalid session id" },
++	{ WL_PROXD_E_REMOTE_CANCEL,		"remote cancel" },
++	{ WL_PROXD_E_CANCELED,		"canceled" },
++	{ WL_PROXD_E_INVALID_SESSION,	"invalid session" },
++	{ WL_PROXD_E_BAD_STATE,		"bad state" },
++	{ WL_PROXD_E_ERROR,			"error" },
++	{ WL_PROXD_E_OK,				"OK" }
++};
++
++/*
++* time interval unit --> text string mapping
++*/
++static const ftm_strmap_entry_t ftm_tmu_value_loginfo[] = {
++	/* wl_proxd_tmu_t,			text-string */
++	{ WL_PROXD_TMU_TU,			"TU" },
++	{ WL_PROXD_TMU_SEC,			"sec" },
++	{ WL_PROXD_TMU_MILLI_SEC,	"ms" },
++	{ WL_PROXD_TMU_MICRO_SEC,	"us" },
++	{ WL_PROXD_TMU_NANO_SEC,	"ns" },
++	{ WL_PROXD_TMU_PICO_SEC,	"ps" }
++};
++
++#define RSPEC_BW(rspec)         ((rspec) & WL_RSPEC_BW_MASK)
++#define RSPEC_IS20MHZ(rspec)	(RSPEC_BW(rspec) == WL_RSPEC_BW_20MHZ)
++#define RSPEC_IS40MHZ(rspec)	(RSPEC_BW(rspec) == WL_RSPEC_BW_40MHZ)
++#define RSPEC_IS80MHZ(rspec)    (RSPEC_BW(rspec) == WL_RSPEC_BW_80MHZ)
++#define RSPEC_IS160MHZ(rspec)   (RSPEC_BW(rspec) == WL_RSPEC_BW_160MHZ)
++
++#define IS_MCS(rspec)     	(((rspec) & WL_RSPEC_ENCODING_MASK) != WL_RSPEC_ENCODE_RATE)
++#define IS_STBC(rspec)     	(((((rspec) & WL_RSPEC_ENCODING_MASK) == WL_RSPEC_ENCODE_HT) ||	\
++	(((rspec) & WL_RSPEC_ENCODING_MASK) == WL_RSPEC_ENCODE_VHT)) &&	\
++	(((rspec) & WL_RSPEC_STBC) == WL_RSPEC_STBC))
++#define RSPEC_ISSGI(rspec)      (((rspec) & WL_RSPEC_SGI) != 0)
++#define RSPEC_ISLDPC(rspec)     (((rspec) & WL_RSPEC_LDPC) != 0)
++#define RSPEC_ISSTBC(rspec)     (((rspec) & WL_RSPEC_STBC) != 0)
++#define RSPEC_ISTXBF(rspec)     (((rspec) & WL_RSPEC_TXBF) != 0)
++#define RSPEC_ISVHT(rspec)    	(((rspec) & WL_RSPEC_ENCODING_MASK) == WL_RSPEC_ENCODE_VHT)
++#define RSPEC_ISHT(rspec)	(((rspec) & WL_RSPEC_ENCODING_MASK) == WL_RSPEC_ENCODE_HT)
++#define RSPEC_ISLEGACY(rspec)   (((rspec) & WL_RSPEC_ENCODING_MASK) == WL_RSPEC_ENCODE_RATE)
++#define RSPEC2RATE(rspec)	(RSPEC_ISLEGACY(rspec) ? \
++				 ((rspec) & RSPEC_RATE_MASK) : rate_rspec2rate(rspec))
++/* return rate in unit of 500Kbps -- for internal use in wlc_rate_sel.c */
++#define RSPEC2KBPS(rspec)	rate_rspec2rate(rspec)
++
++struct ieee_80211_mcs_rate_info {
++	uint8 constellation_bits;
++	uint8 coding_q;
++	uint8 coding_d;
++};
++
++static const struct ieee_80211_mcs_rate_info wl_mcs_info[] = {
++	{ 1, 1, 2 }, /* MCS  0: MOD: BPSK,   CR 1/2 */
++	{ 2, 1, 2 }, /* MCS  1: MOD: QPSK,   CR 1/2 */
++	{ 2, 3, 4 }, /* MCS  2: MOD: QPSK,   CR 3/4 */
++	{ 4, 1, 2 }, /* MCS  3: MOD: 16QAM,  CR 1/2 */
++	{ 4, 3, 4 }, /* MCS  4: MOD: 16QAM,  CR 3/4 */
++	{ 6, 2, 3 }, /* MCS  5: MOD: 64QAM,  CR 2/3 */
++	{ 6, 3, 4 }, /* MCS  6: MOD: 64QAM,  CR 3/4 */
++	{ 6, 5, 6 }, /* MCS  7: MOD: 64QAM,  CR 5/6 */
++	{ 8, 3, 4 }, /* MCS  8: MOD: 256QAM, CR 3/4 */
++	{ 8, 5, 6 }  /* MCS  9: MOD: 256QAM, CR 5/6 */
++};
++
++/**
++ * Returns the rate in [Kbps] units for a caller supplied MCS/bandwidth/Nss/Sgi combination.
++ *     'mcs' : a *single* spatial stream MCS (11n or 11ac)
++ */
++uint
++rate_mcs2rate(uint mcs, uint nss, uint bw, int sgi)
++{
++	const int ksps = 250; /* kilo symbols per sec, 4 us sym */
++	const int Nsd_20MHz = 52;
++	const int Nsd_40MHz = 108;
++	const int Nsd_80MHz = 234;
++	const int Nsd_160MHz = 468;
++	uint rate;
++
++	if (mcs == 32) {
++		/* just return fixed values for mcs32 instead of trying to parametrize */
++		rate = (sgi == 0) ? 6000 : 6778;
++	} else if (mcs <= 9) {
++		/* This calculation works for 11n HT and 11ac VHT if the HT mcs values
++		 * are decomposed into a base MCS = MCS % 8, and Nss = 1 + MCS / 8.
++		 * That is, HT MCS 23 is a base MCS = 7, Nss = 3
++		 */
++
++		/* find the number of complex numbers per symbol */
++		if (RSPEC_IS20MHZ(bw)) {
++			rate = Nsd_20MHz;
++		} else if (RSPEC_IS40MHZ(bw)) {
++			rate = Nsd_40MHz;
++		} else if (bw == WL_RSPEC_BW_80MHZ) {
++			rate = Nsd_80MHz;
++		} else if (bw == WL_RSPEC_BW_160MHZ) {
++			rate = Nsd_160MHz;
++		} else {
++			rate = 0;
++		}
++
++		/* multiply by bits per number from the constellation in use */
++		rate = rate * wl_mcs_info[mcs].constellation_bits;
++
++		/* adjust for the number of spatial streams */
++		rate = rate * nss;
++
++		/* adjust for the coding rate given as a quotient and divisor */
++		rate = (rate * wl_mcs_info[mcs].coding_q) / wl_mcs_info[mcs].coding_d;
++
++		/* multiply by Kilo symbols per sec to get Kbps */
++		rate = rate * ksps;
++
++		/* adjust the symbols per sec for SGI
++		 * symbol duration is 4 us without SGI, and 3.6 us with SGI,
++		 * so ratio is 10 / 9
++		 */
++		if (sgi) {
++			/* add 4 for rounding of division by 9 */
++			rate = ((rate * 10) + 4) / 9;
++		}
++	} else {
++		rate = 0;
++	}
++
++	return rate;
++} /* wlc_rate_mcs2rate */
++
++/** take a well formed ratespec_t arg and return phy rate in [Kbps] units */
++int
++rate_rspec2rate(uint32 rspec)
++{
++	int rate = -1;
++
++	if (RSPEC_ISLEGACY(rspec)) {
++		rate = 500 * (rspec & WL_RSPEC_RATE_MASK);
++	} else if (RSPEC_ISHT(rspec)) {
++		uint mcs = (rspec & WL_RSPEC_RATE_MASK);
++
++		if (mcs == 32) {
++			rate = rate_mcs2rate(mcs, 1, WL_RSPEC_BW_40MHZ, RSPEC_ISSGI(rspec));
++		} else {
++			uint nss = 1 + (mcs / 8);
++			mcs = mcs % 8;
++			rate = rate_mcs2rate(mcs, nss, RSPEC_BW(rspec), RSPEC_ISSGI(rspec));
++		}
++	} else if (RSPEC_ISVHT(rspec)) {
++		uint mcs = (rspec & WL_RSPEC_VHT_MCS_MASK);
++		uint nss = (rspec & WL_RSPEC_VHT_NSS_MASK) >> WL_RSPEC_VHT_NSS_SHIFT;
++
++		ASSERT(mcs <= 9);
++		ASSERT(nss <= 8);
++
++		rate = rate_mcs2rate(mcs, nss, RSPEC_BW(rspec), RSPEC_ISSGI(rspec));
++	} else {
++		ASSERT(0);
++	}
++
++	return (rate == 0) ? -1 : rate;
++}
++
++char resp_buf[WLC_IOCTL_SMLEN];
++
++static uint64
++ftm_intvl2nsec(const wl_proxd_intvl_t *intvl)
++{
++	uint64 ret;
++	ret = intvl->intvl;
++	switch (intvl->tmu) {
++	case WL_PROXD_TMU_TU:			ret = FTM_TU2MICRO(ret) * 1000; break;
++	case WL_PROXD_TMU_SEC:			ret *= 1000000000; break;
++	case WL_PROXD_TMU_MILLI_SEC:	ret *= 1000000; break;
++	case WL_PROXD_TMU_MICRO_SEC:	ret *= 1000; break;
++	case WL_PROXD_TMU_PICO_SEC:		ret = intvl->intvl / 1000; break;
++	case WL_PROXD_TMU_NANO_SEC:		/* fall through */
++	default:						break;
++	}
++	return ret;
++}
++uint64
++ftm_intvl2usec(const wl_proxd_intvl_t *intvl)
++{
++	uint64 ret;
++	ret = intvl->intvl;
++	switch (intvl->tmu) {
++	case WL_PROXD_TMU_TU:			ret = FTM_TU2MICRO(ret); break;
++	case WL_PROXD_TMU_SEC:			ret *= 1000000; break;
++	case WL_PROXD_TMU_NANO_SEC:		ret = intvl->intvl / 1000; break;
++	case WL_PROXD_TMU_PICO_SEC:		ret = intvl->intvl / 1000000; break;
++	case WL_PROXD_TMU_MILLI_SEC:	ret *= 1000; break;
++	case WL_PROXD_TMU_MICRO_SEC:	/* fall through */
++	default:						break;
++	}
++	return ret;
++}
++
++/*
++* lookup 'id' (as a key) from a fw status to host map table
++* if found, return the corresponding reason code
++*/
++
++static rtt_reason_t
++ftm_get_statusmap_info(wl_proxd_status_t id, const ftm_status_map_host_entry_t *p_table,
++	uint32 num_entries)
++{
++	int i;
++	const ftm_status_map_host_entry_t *p_entry;
++	/* scan thru the table till end */
++	p_entry = p_table;
++	for (i = 0; i < (int) num_entries; i++)
++	{
++		if (p_entry->proxd_status == id) {
++			return p_entry->rtt_reason;
++		}
++		p_entry++;		/* next entry */
++	}
++	return RTT_REASON_FAILURE; /* not found */
++}
++/*
++* lookup 'id' (as a key) from a table
++* if found, return the entry pointer, otherwise return NULL
++*/
++static const ftm_strmap_entry_t*
++ftm_get_strmap_info(int32 id, const ftm_strmap_entry_t *p_table, uint32 num_entries)
++{
++	int i;
++	const ftm_strmap_entry_t *p_entry;
++
++	/* scan thru the table till end */
++	p_entry = p_table;
++	for (i = 0; i < (int) num_entries; i++)
++	{
++		if (p_entry->id == id)
++			return p_entry;
++		p_entry++;		/* next entry */
++	}
++	return NULL;			/* not found */
++}
++
++/*
++* map enum to a text-string for display, this function is called by the following:
++* For debug/trace:
++*     ftm_[cmdid|tlvid]_to_str()
++* For TLV-output log for 'get' commands
++*     ftm_[method|tmu|caps|status|state]_value_to_logstr()
++* Input:
++*     pTable -- point to a 'enum to string' table.
++*/
++static const char *
++ftm_map_id_to_str(int32 id, const ftm_strmap_entry_t *p_table, uint32 num_entries)
++{
++	const ftm_strmap_entry_t*p_entry = ftm_get_strmap_info(id, p_table, num_entries);
++	if (p_entry)
++		return (p_entry->text);
++
++	return "invalid";
++}
++
++
++#ifdef RTT_DEBUG
++
++/* define entry, e.g. { WL_PROXD_CMD_xxx, "WL_PROXD_CMD_xxx" } */
++#define DEF_STRMAP_ENTRY(id) { (id), #id }
++
++/* ftm cmd-id mapping */
++static const ftm_strmap_entry_t ftm_cmdid_map[] = {
++	/* {wl_proxd_cmd_t(WL_PROXD_CMD_xxx), "WL_PROXD_CMD_xxx" }, */
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_NONE),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_GET_VERSION),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_ENABLE),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_DISABLE),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_CONFIG),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_START_SESSION),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_BURST_REQUEST),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_STOP_SESSION),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_DELETE_SESSION),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_GET_RESULT),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_GET_INFO),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_GET_STATUS),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_GET_SESSIONS),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_GET_COUNTERS),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_CLEAR_COUNTERS),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_COLLECT),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_TUNE),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_DUMP),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_START_RANGING),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_STOP_RANGING),
++	DEF_STRMAP_ENTRY(WL_PROXD_CMD_GET_RANGING_INFO),
++};
++
++/*
++* map a ftm cmd-id to a text-string for display
++*/
++static const char *
++ftm_cmdid_to_str(uint16 cmdid)
++{
++	return ftm_map_id_to_str((int32) cmdid, &ftm_cmdid_map[0], ARRAYSIZE(ftm_cmdid_map));
++}
++#endif /* RTT_DEBUG */
++
++
++/*
++* convert BCME_xxx error codes into related error strings
++* note, bcmerrorstr() defined in bcmutils is for BCMDRIVER only,
++*       this duplicate copy is for WL access and may need to clean up later
++*/
++static const char *ftm_bcmerrorstrtable[] = BCMERRSTRINGTABLE;
++static const char *
++ftm_status_value_to_logstr(wl_proxd_status_t status)
++{
++	static char ftm_msgbuf_status_undef[32];
++	const ftm_strmap_entry_t *p_loginfo;
++	int bcmerror;
++
++	/* check if within BCME_xxx error range */
++	bcmerror = (int) status;
++	if (VALID_BCMERROR(bcmerror))
++		return ftm_bcmerrorstrtable[-bcmerror];
++
++	/* otherwise, look for 'proxd ftm status' range */
++	p_loginfo = ftm_get_strmap_info((int32) status,
++		&ftm_status_value_loginfo[0], ARRAYSIZE(ftm_status_value_loginfo));
++	if (p_loginfo)
++		return p_loginfo->text;
++
++	/* report for 'out of range' FTM-status error code */
++	memset(ftm_msgbuf_status_undef, 0, sizeof(ftm_msgbuf_status_undef));
++	snprintf(ftm_msgbuf_status_undef, sizeof(ftm_msgbuf_status_undef),
++		"Undefined status %d", status);
++	return &ftm_msgbuf_status_undef[0];
++}
++
++static const char *
++ftm_tmu_value_to_logstr(wl_proxd_tmu_t tmu)
++{
++	return ftm_map_id_to_str((int32)tmu,
++		&ftm_tmu_value_loginfo[0], ARRAYSIZE(ftm_tmu_value_loginfo));
++}
++
++static const ftm_strmap_entry_t*
++ftm_get_event_type_loginfo(wl_proxd_event_type_t	event_type)
++{
++	/* look up 'event-type' from a predefined table  */
++	return ftm_get_strmap_info((int32) event_type,
++		ftm_event_type_loginfo, ARRAYSIZE(ftm_event_type_loginfo));
++}
++
++static const char *
++ftm_session_state_value_to_logstr(wl_proxd_session_state_t state)
++{
++	return ftm_map_id_to_str((int32)state, &ftm_session_state_value_loginfo[0],
++		ARRAYSIZE(ftm_session_state_value_loginfo));
++}
++
++
++/*
++* send 'proxd' iovar for all ftm get-related commands
++*/
++static int
++rtt_do_get_ioctl(dhd_pub_t *dhd, wl_proxd_iov_t *p_proxd_iov, uint16 proxd_iovsize,
++		ftm_subcmd_info_t *p_subcmd_info)
++{
++
++	wl_proxd_iov_t *p_iovresp = (wl_proxd_iov_t *)resp_buf;
++	int status;
++	int tlvs_len;
++	/*  send getbuf proxd iovar */
++	status = dhd_getiovar(dhd, 0, "proxd", (char *)p_proxd_iov,
++			proxd_iovsize, (char **)&p_iovresp, WLC_IOCTL_SMLEN);
++	if (status != BCME_OK) {
++		DHD_ERROR(("%s: failed to send getbuf proxd iovar (CMD ID : %d), status=%d\n",
++			__FUNCTION__, p_subcmd_info->cmdid, status));
++		return status;
++	}
++	if (p_subcmd_info->cmdid == WL_PROXD_CMD_GET_VERSION) {
++		p_subcmd_info->version = ltoh16(p_iovresp->version);
++		DHD_RTT(("ftm version: 0x%x\n", ltoh16(p_iovresp->version)));
++		goto exit;
++	}
++
++	tlvs_len = ltoh16(p_iovresp->len) - WL_PROXD_IOV_HDR_SIZE;
++	if (tlvs_len < 0) {
++		DHD_ERROR(("%s: alert, p_iovresp->len(%d) should not be smaller than %d\n",
++			__FUNCTION__, ltoh16(p_iovresp->len), (int) WL_PROXD_IOV_HDR_SIZE));
++		tlvs_len = 0;
++	}
++
++	if (tlvs_len > 0 && p_subcmd_info->handler) {
++		/* unpack TLVs and invokes the cbfn for processing */
++		status = bcm_unpack_xtlv_buf(p_proxd_iov, (uint8 *)p_iovresp->tlvs,
++				tlvs_len, BCM_XTLV_OPTION_ALIGN32, p_subcmd_info->handler);
++	}
++exit:
++	return status;
++}
++
++
++static wl_proxd_iov_t *
++rtt_alloc_getset_buf(wl_proxd_method_t method, wl_proxd_session_id_t session_id,
++	wl_proxd_cmd_t cmdid, uint16 tlvs_bufsize, uint16 *p_out_bufsize)
++{
++	uint16 proxd_iovsize;
++	uint16 kflags;
++	wl_proxd_tlv_t *p_tlv;
++	wl_proxd_iov_t *p_proxd_iov = (wl_proxd_iov_t *) NULL;
++
++	*p_out_bufsize = 0;	/* init */
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	/* calculate the whole buffer size, including one reserve-tlv entry in the header */
++	proxd_iovsize = sizeof(wl_proxd_iov_t) + tlvs_bufsize;
++
++	p_proxd_iov = kzalloc(proxd_iovsize, kflags);
++	if (p_proxd_iov == NULL) {
++		DHD_ERROR(("error: failed to allocate %d bytes of memory\n", proxd_iovsize));
++		return NULL;
++	}
++
++	/* setup proxd-FTM-method iovar header */
++	p_proxd_iov->version = htol16(WL_PROXD_API_VERSION);
++	p_proxd_iov->len = htol16(proxd_iovsize); /* caller may adjust it based on #of TLVs */
++	p_proxd_iov->cmd = htol16(cmdid);
++	p_proxd_iov->method = htol16(method);
++	p_proxd_iov->sid = htol16(session_id);
++
++	/* initialize the reserved/dummy-TLV in iovar header */
++	p_tlv = p_proxd_iov->tlvs;
++	p_tlv->id = htol16(WL_PROXD_TLV_ID_NONE);
++	p_tlv->len = htol16(0);
++
++	*p_out_bufsize = proxd_iovsize;	/* for caller's reference */
++
++	return p_proxd_iov;
++}
++
++
++static int
++dhd_rtt_common_get_handler(dhd_pub_t *dhd, ftm_subcmd_info_t *p_subcmd_info,
++		wl_proxd_method_t method,
++		wl_proxd_session_id_t session_id)
++{
++	int status = BCME_OK;
++	uint16 proxd_iovsize = 0;
++	wl_proxd_iov_t *p_proxd_iov;
++#ifdef RTT_DEBUG
++	DHD_RTT(("enter %s: method=%d, session_id=%d, cmdid=%d(%s)\n",
++		__FUNCTION__, method, session_id, p_subcmd_info->cmdid,
++		ftm_cmdid_to_str(p_subcmd_info->cmdid)));
++#endif
++	/* alloc mem for ioctl headr + reserved 0 bufsize for tlvs (initialize to zero) */
++	p_proxd_iov = rtt_alloc_getset_buf(method, session_id, p_subcmd_info->cmdid,
++		0, &proxd_iovsize);
++
++	if (p_proxd_iov == NULL)
++		return BCME_NOMEM;
++
++	status = rtt_do_get_ioctl(dhd, p_proxd_iov, proxd_iovsize, p_subcmd_info);
++
++	if (status != BCME_OK) {
++		DHD_RTT(("%s failed: status=%d\n", __FUNCTION__, status));
++	}
++	kfree(p_proxd_iov);
++	return status;
++}
++
++/*
++* common handler for set-related proxd method commands which require no TLV as input
++*   wl proxd ftm [session-id] <set-subcmd>
++* e.g.
++*   wl proxd ftm enable -- to enable ftm
++*   wl proxd ftm disable -- to disable ftm
++*   wl proxd ftm <session-id> start -- to start a specified session
++*   wl proxd ftm <session-id> stop  -- to cancel a specified session;
++*                                    state is maintained till session is delete.
++*   wl proxd ftm <session-id> delete -- to delete a specified session
++*   wl proxd ftm [<session-id>] clear-counters -- to clear counters
++*   wl proxd ftm <session-id> burst-request -- on initiator: to send burst request;
++*                                              on target: send FTM frame
++*   wl proxd ftm <session-id> collect
++*   wl proxd ftm tune     (TBD)
++*/
++static int
++dhd_rtt_common_set_handler(dhd_pub_t *dhd, const ftm_subcmd_info_t *p_subcmd_info,
++	wl_proxd_method_t method, wl_proxd_session_id_t session_id)
++{
++	uint16 proxd_iovsize;
++	wl_proxd_iov_t *p_proxd_iov;
++	int ret;
++
++#ifdef RTT_DEBUG
++	DHD_ERROR(("enter %s: method=%d, session_id=%d, cmdid=%d(%s)\n",
++		__FUNCTION__, method, session_id, p_subcmd_info->cmdid,
++		ftm_cmdid_to_str(p_subcmd_info->cmdid)));
++#endif
++	/* allocate and initialize a temp buffer for 'set proxd' iovar */
++	proxd_iovsize = 0;
++	p_proxd_iov = rtt_alloc_getset_buf(method, session_id, p_subcmd_info->cmdid,
++							0, &proxd_iovsize);		/* no TLV */
++	if (p_proxd_iov == NULL)
++		return BCME_NOMEM;
++
++	/* no TLV to pack, simply issue a set-proxd iovar */
++	ret = dhd_iovar(dhd, 0, "proxd", (char *)p_proxd_iov, proxd_iovsize, NULL, 0, TRUE);
++#ifdef RTT_DEBUG
++	if (ret != BCME_OK) {
++		DHD_ERROR(("error: Proxd IOVAR failed, status=%d\n", ret));
++	}
++#endif
++	/* clean up */
++	kfree(p_proxd_iov);
++	return ret;
++}
++
++static int
++rtt_unpack_xtlv_cbfn(void *ctx, uint8 *p_data, uint16 tlvid, uint16 len)
++{
++	int ret = BCME_OK;
++	wl_proxd_ftm_session_status_t *p_data_info;
++	switch (tlvid) {
++	case WL_PROXD_TLV_ID_RTT_RESULT:
++		ret = dhd_rtt_convert_results_to_host((rtt_report_t *)ctx,
++				p_data, tlvid, len);
++		break;
++	case WL_PROXD_TLV_ID_SESSION_STATUS:
++		memcpy(ctx, p_data, sizeof(wl_proxd_ftm_session_status_t));
++		p_data_info = (wl_proxd_ftm_session_status_t *)ctx;
++		p_data_info->state = ltoh16_ua(&p_data_info->state);
++		p_data_info->status = ltoh32_ua(&p_data_info->status);
++		break;
++	default:
++		DHD_ERROR(("> Unsupported TLV ID %d\n", tlvid));
++		ret = BCME_ERROR;
++		break;
++	}
++
++	return ret;
++}
++static int
++rtt_handle_config_options(wl_proxd_session_id_t session_id, wl_proxd_tlv_t **p_tlv,
++	uint16 *p_buf_space_left, ftm_config_options_info_t *ftm_configs, int ftm_cfg_cnt)
++{
++	int ret = BCME_OK;
++	int cfg_idx = 0;
++	uint32 flags = WL_PROXD_FLAG_NONE;
++	uint32 flags_mask = WL_PROXD_FLAG_NONE;
++	uint32 new_mask;		/* cmdline input */
++	ftm_config_options_info_t *p_option_info;
++	uint16 type = (session_id == WL_PROXD_SESSION_ID_GLOBAL) ?
++			WL_PROXD_TLV_ID_FLAGS_MASK : WL_PROXD_TLV_ID_SESSION_FLAGS_MASK;
++	for (cfg_idx = 0; cfg_idx < ftm_cfg_cnt; cfg_idx++) {
++		p_option_info = (ftm_configs + cfg_idx);
++		if (p_option_info != NULL) {
++			new_mask = p_option_info->flags;
++			/* update flags mask */
++			flags_mask |= new_mask;
++			if (p_option_info->enable) {
++				flags |= new_mask;	/* set the bit on */
++			} else {
++				flags &= ~new_mask;	/* set the bit off */
++			}
++		}
++	}
++	flags = htol32(flags);
++	flags_mask = htol32(flags_mask);
++	/* setup flags_mask TLV */
++	ret = bcm_pack_xtlv_entry((uint8 **)p_tlv, p_buf_space_left,
++		type, sizeof(uint32), &flags_mask, BCM_XTLV_OPTION_ALIGN32);
++	if (ret != BCME_OK) {
++		DHD_ERROR(("%s : bcm_pack_xltv_entry() for mask flags failed, status=%d\n",
++			__FUNCTION__, ret));
++		goto exit;
++	}
++
++	type = (session_id == WL_PROXD_SESSION_ID_GLOBAL)?
++		WL_PROXD_TLV_ID_FLAGS : WL_PROXD_TLV_ID_SESSION_FLAGS;
++	/* setup flags TLV */
++	ret = bcm_pack_xtlv_entry((uint8 **)p_tlv, p_buf_space_left,
++			type, sizeof(uint32), &flags, BCM_XTLV_OPTION_ALIGN32);
++		if (ret != BCME_OK) {
++//#ifdef RTT_DEBUG
++			DHD_RTT(("%s: bcm_pack_xltv_entry() for flags failed, status=%d\n",
++				__FUNCTION__, ret));
++//#endif
++		}
++exit:
++	return ret;
++}
++
++static int
++rtt_handle_config_general(wl_proxd_session_id_t session_id, wl_proxd_tlv_t **p_tlv,
++	uint16 *p_buf_space_left, ftm_config_param_info_t *ftm_configs, int ftm_cfg_cnt)
++{
++	int ret = BCME_OK;
++	int cfg_idx = 0;
++	uint32 chanspec;
++	ftm_config_param_info_t *p_config_param_info;
++	void		*p_src_data;
++	uint16	src_data_size;	/* size of data pointed by p_src_data as 'source' */
++	for (cfg_idx = 0; cfg_idx < ftm_cfg_cnt; cfg_idx++) {
++		p_config_param_info = (ftm_configs + cfg_idx);
++		if (p_config_param_info != NULL) {
++			switch (p_config_param_info->tlvid)	{
++			case WL_PROXD_TLV_ID_BSS_INDEX:
++			case WL_PROXD_TLV_ID_FTM_RETRIES:
++			case WL_PROXD_TLV_ID_FTM_REQ_RETRIES:
++				p_src_data = &p_config_param_info->data8;
++				src_data_size = sizeof(uint8);
++				break;
++			case WL_PROXD_TLV_ID_BURST_NUM_FTM: /* uint16 */
++			case WL_PROXD_TLV_ID_NUM_BURST:
++			case WL_PROXD_TLV_ID_RX_MAX_BURST:
++				p_src_data = &p_config_param_info->data16;
++				src_data_size = sizeof(uint16);
++				break;
++			case WL_PROXD_TLV_ID_TX_POWER:		/* uint32 */
++			case WL_PROXD_TLV_ID_RATESPEC:
++			case WL_PROXD_TLV_ID_EVENT_MASK: /* wl_proxd_event_mask_t/uint32 */
++			case WL_PROXD_TLV_ID_DEBUG_MASK:
++				p_src_data = &p_config_param_info->data32;
++				src_data_size = sizeof(uint32);
++				break;
++			case WL_PROXD_TLV_ID_CHANSPEC:		/* chanspec_t --> 32bit */
++				chanspec = p_config_param_info->chanspec;
++				p_src_data = (void *) &chanspec;
++				src_data_size = sizeof(uint32);
++				break;
++			case WL_PROXD_TLV_ID_BSSID: /* mac address */
++			case WL_PROXD_TLV_ID_PEER_MAC:
++				p_src_data = &p_config_param_info->mac_addr;
++				src_data_size = sizeof(struct ether_addr);
++				break;
++			case WL_PROXD_TLV_ID_BURST_DURATION:	/* wl_proxd_intvl_t */
++			case WL_PROXD_TLV_ID_BURST_PERIOD:
++			case WL_PROXD_TLV_ID_BURST_FTM_SEP:
++			case WL_PROXD_TLV_ID_BURST_TIMEOUT:
++			case WL_PROXD_TLV_ID_INIT_DELAY:
++				p_src_data = &p_config_param_info->data_intvl;
++				src_data_size = sizeof(wl_proxd_intvl_t);
++				break;
++			default:
++				ret = BCME_BADARG;
++				break;
++			}
++			if (ret != BCME_OK) {
++				DHD_ERROR(("%s bad TLV ID : %d\n",
++					__FUNCTION__, p_config_param_info->tlvid));
++				break;
++			}
++
++			ret = bcm_pack_xtlv_entry((uint8 **) p_tlv, p_buf_space_left,
++				p_config_param_info->tlvid, src_data_size, p_src_data,
++				BCM_XTLV_OPTION_ALIGN32);
++			if (ret != BCME_OK) {
++				DHD_ERROR(("%s: bcm_pack_xltv_entry() failed,"
++					" status=%d\n", __FUNCTION__, ret));
++				break;
++			}
++
++		}
++	}
++	return ret;
++}
++
++static int
++dhd_rtt_get_version(dhd_pub_t *dhd, int *out_version)
++{
++	int ret;
++	ftm_subcmd_info_t subcmd_info;
++	subcmd_info.name = "ver";
++	subcmd_info.cmdid = WL_PROXD_CMD_GET_VERSION;
++	subcmd_info.handler = NULL;
++	ret = dhd_rtt_common_get_handler(dhd, &subcmd_info,
++			WL_PROXD_METHOD_FTM, WL_PROXD_SESSION_ID_GLOBAL);
++	*out_version = (ret == BCME_OK) ? subcmd_info.version : 0;
++	return ret;
++}
++
++static int
++dhd_rtt_ftm_enable(dhd_pub_t *dhd, bool enable)
++{
++	ftm_subcmd_info_t subcmd_info;
++	subcmd_info.name = (enable)? "enable" : "disable";
++	subcmd_info.cmdid = (enable)? WL_PROXD_CMD_ENABLE: WL_PROXD_CMD_DISABLE;
++	subcmd_info.handler = NULL;
++	return dhd_rtt_common_set_handler(dhd, &subcmd_info,
++			WL_PROXD_METHOD_FTM, WL_PROXD_SESSION_ID_GLOBAL);
++}
++
++static int
++dhd_rtt_start_session(dhd_pub_t *dhd, wl_proxd_session_id_t session_id, bool start)
++{
++	ftm_subcmd_info_t subcmd_info;
++	subcmd_info.name = (start)? "start session" : "stop session";
++	subcmd_info.cmdid = (start)? WL_PROXD_CMD_START_SESSION: WL_PROXD_CMD_STOP_SESSION;
++	subcmd_info.handler = NULL;
++	return dhd_rtt_common_set_handler(dhd, &subcmd_info,
++			WL_PROXD_METHOD_FTM, session_id);
++}
++
++static int
++dhd_rtt_delete_session(dhd_pub_t *dhd, wl_proxd_session_id_t session_id)
++{
++	ftm_subcmd_info_t subcmd_info;
++	subcmd_info.name = "delete session";
++	subcmd_info.cmdid = WL_PROXD_CMD_DELETE_SESSION;
++	subcmd_info.handler = NULL;
++	return dhd_rtt_common_set_handler(dhd, &subcmd_info,
++			WL_PROXD_METHOD_FTM, session_id);
++}
++
++static int
++dhd_rtt_ftm_config(dhd_pub_t *dhd, wl_proxd_session_id_t session_id,
++	ftm_config_category_t catagory, void *ftm_configs, int ftm_cfg_cnt)
++{
++	ftm_subcmd_info_t subcmd_info;
++	wl_proxd_tlv_t *p_tlv;
++	/* alloc mem for ioctl headr + reserved 0 bufsize for tlvs (initialize to zero) */
++	wl_proxd_iov_t *p_proxd_iov;
++	uint16 proxd_iovsize = 0;
++	uint16 bufsize;
++	uint16 buf_space_left;
++	uint16 all_tlvsize;
++	int ret = BCME_OK;
++	subcmd_info.name = "config";
++	subcmd_info.cmdid = WL_PROXD_CMD_CONFIG;
++
++	p_proxd_iov = rtt_alloc_getset_buf(WL_PROXD_METHOD_FTM, session_id, subcmd_info.cmdid,
++		FTM_IOC_BUFSZ, &proxd_iovsize);
++
++	if (p_proxd_iov == NULL) {
++		DHD_ERROR(("%s : failed to allocate the iovar (size :%d)\n",
++			__FUNCTION__, FTM_IOC_BUFSZ));
++		return BCME_NOMEM;
++	}
++	/* setup TLVs */
++	bufsize = proxd_iovsize - WL_PROXD_IOV_HDR_SIZE; /* adjust available size for TLVs */
++	p_tlv = &p_proxd_iov->tlvs[0];
++	/* TLV buffer starts with a full size, will decrement for each packed TLV */
++	buf_space_left = bufsize;
++	if (catagory == FTM_CONFIG_CAT_OPTIONS) {
++		ret = rtt_handle_config_options(session_id, &p_tlv, &buf_space_left,
++				(ftm_config_options_info_t *)ftm_configs, ftm_cfg_cnt);
++	} else if (catagory == FTM_CONFIG_CAT_GENERAL) {
++		ret = rtt_handle_config_general(session_id, &p_tlv, &buf_space_left,
++				(ftm_config_param_info_t *)ftm_configs, ftm_cfg_cnt);
++	}
++	if (ret == BCME_OK) {
++		/* update the iov header, set len to include all TLVs + header */
++		all_tlvsize = (bufsize - buf_space_left);
++		p_proxd_iov->len = htol16(all_tlvsize + WL_PROXD_IOV_HDR_SIZE);
++		ret = dhd_iovar(dhd, 0, "proxd", (char *)p_proxd_iov,
++				all_tlvsize + WL_PROXD_IOV_HDR_SIZE, NULL, 0, TRUE);
++		if (ret != BCME_OK) {
++			DHD_ERROR(("%s : failed to set config \n", __FUNCTION__));
++		}
++	}
++	/* clean up */
++	kfree(p_proxd_iov);
++	return ret;
++}
++chanspec_t
++dhd_rtt_convert_to_chspec(wifi_channel_info_t channel)
++{
++	int bw;
++	chanspec_t chanspec = 0;
++	uint8 center_chan;
++	uint8 primary_chan;
++	/* set witdh to 20MHZ for 2.4G HZ */
++	if (channel.center_freq >= 2400 && channel.center_freq <= 2500) {
++		channel.width = WIFI_CHAN_WIDTH_20;
++	}
++	switch (channel.width) {
++	case WIFI_CHAN_WIDTH_20:
++		bw = WL_CHANSPEC_BW_20;
++		primary_chan = wf_mhz2channel(channel.center_freq, 0);
++		chanspec = wf_channel2chspec(primary_chan, bw);
++		break;
++	case WIFI_CHAN_WIDTH_40:
++		bw = WL_CHANSPEC_BW_40;
++		primary_chan = wf_mhz2channel(channel.center_freq, 0);
++		chanspec = wf_channel2chspec(primary_chan, bw);
++		break;
++	case WIFI_CHAN_WIDTH_80:
++		bw = WL_CHANSPEC_BW_80;
++		primary_chan = wf_mhz2channel(channel.center_freq, 0);
++		center_chan = wf_mhz2channel(channel.center_freq0, 0);
++		chanspec = wf_chspec_80(center_chan, primary_chan);
++		break;
++	default:
++		DHD_ERROR(("doesn't support this bandwith : %d", channel.width));
++		bw = -1;
++		break;
++	}
++	return chanspec;
++}
++
++int
++dhd_rtt_idx_to_burst_duration(uint idx)
++{
++	if (idx >= ARRAY_SIZE(burst_duration_idx)) {
++		return -1;
++	}
++	return burst_duration_idx[idx];
++}
++
++int
++dhd_rtt_set_cfg(dhd_pub_t *dhd, rtt_config_params_t *params)
++{
++	int err = BCME_OK;
++	int idx;
++	rtt_status_info_t *rtt_status;
++	NULL_CHECK(params, "params is NULL", err);
++
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", err);
++	if (!HAS_11MC_CAP(rtt_status->rtt_capa.proto)) {
++		DHD_ERROR(("doesn't support RTT \n"));
++		return BCME_ERROR;
++	}
++	if (rtt_status->status != RTT_STOPPED) {
++		DHD_ERROR(("rtt is already started\n"));
++		return BCME_BUSY;
++	}
++	DHD_RTT(("%s enter\n", __FUNCTION__));
++
++	memset(rtt_status->rtt_config.target_info, 0, TARGET_INFO_SIZE(RTT_MAX_TARGET_CNT));
++	rtt_status->rtt_config.rtt_target_cnt = params->rtt_target_cnt;
++	memcpy(rtt_status->rtt_config.target_info,
++		params->target_info, TARGET_INFO_SIZE(params->rtt_target_cnt));
++	rtt_status->status = RTT_STARTED;
++	/* start to measure RTT from first device */
++	/* find next target to trigger RTT */
++	for (idx = rtt_status->cur_idx; idx < rtt_status->rtt_config.rtt_target_cnt; idx++) {
++		/* skip the disabled device */
++		if (rtt_status->rtt_config.target_info[idx].disable) {
++			continue;
++		} else {
++			/* set the idx to cur_idx */
++			rtt_status->cur_idx = idx;
++			break;
++		}
++	}
++	if (idx < rtt_status->rtt_config.rtt_target_cnt) {
++		DHD_RTT(("rtt_status->cur_idx : %d\n", rtt_status->cur_idx));
++		schedule_work(&rtt_status->work);
++	}
++	return err;
++}
++
++int
++dhd_rtt_stop(dhd_pub_t *dhd, struct ether_addr *mac_list, int mac_cnt)
++{
++	int err = BCME_OK;
++	int i = 0, j = 0;
++	rtt_status_info_t *rtt_status;
++	rtt_results_header_t *entry, *next;
++	rtt_result_t *rtt_result, *next2;
++	struct rtt_noti_callback *iter;
++
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", err);
++	if (rtt_status->status == RTT_STOPPED) {
++		DHD_ERROR(("rtt is not started\n"));
++		return BCME_OK;
++	}
++	DHD_RTT(("%s enter\n", __FUNCTION__));
++	mutex_lock(&rtt_status->rtt_mutex);
++	for (i = 0; i < mac_cnt; i++) {
++		for (j = 0; j < rtt_status->rtt_config.rtt_target_cnt; j++) {
++			if (!bcmp(&mac_list[i], &rtt_status->rtt_config.target_info[j].addr,
++				ETHER_ADDR_LEN)) {
++				rtt_status->rtt_config.target_info[j].disable = TRUE;
++			}
++		}
++	}
++	if (rtt_status->all_cancel) {
++		/* cancel all of request */
++		rtt_status->status = RTT_STOPPED;
++		DHD_RTT(("current RTT process is cancelled\n"));
++		/* remove the rtt results in cache */
++		if (!list_empty(&rtt_status->rtt_results_cache)) {
++			/* Iterate rtt_results_header list */
++			list_for_each_entry_safe(entry, next,
++				&rtt_status->rtt_results_cache, list) {
++				list_del(&entry->list);
++				/* Iterate rtt_result list */
++				list_for_each_entry_safe(rtt_result, next2,
++					&entry->result_list, list) {
++					list_del(&rtt_result->list);
++					kfree(rtt_result);
++				}
++				kfree(entry);
++			}
++		}
++		/* send the rtt complete event to wake up the user process */
++		list_for_each_entry(iter, &rtt_status->noti_fn_list, list) {
++			iter->noti_fn(iter->ctx, &rtt_status->rtt_results_cache);
++		}
++
++		/* reinitialize the HEAD */
++		INIT_LIST_HEAD(&rtt_status->rtt_results_cache);
++		/* clear information for rtt_config */
++		rtt_status->rtt_config.rtt_target_cnt = 0;
++		memset(rtt_status->rtt_config.target_info, 0,
++			TARGET_INFO_SIZE(RTT_MAX_TARGET_CNT));
++		rtt_status->cur_idx = 0;
++		dhd_rtt_delete_session(dhd, FTM_DEFAULT_SESSION);
++		dhd_rtt_ftm_enable(dhd, FALSE);
++	}
++	mutex_unlock(&rtt_status->rtt_mutex);
++	return err;
++}
++
++static int
++dhd_rtt_start(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	char eabuf[ETHER_ADDR_STR_LEN];
++	char chanbuf[CHANSPEC_STR_LEN];
++	int mpc = 0;
++	int ftm_cfg_cnt = 0;
++	int ftm_param_cnt = 0;
++	uint32 rspec = 0;
++	ftm_config_options_info_t ftm_configs[FTM_MAX_CONFIGS];
++	ftm_config_param_info_t ftm_params[FTM_MAX_PARAMS];
++	rtt_target_info_t *rtt_target;
++	rtt_status_info_t *rtt_status;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", err);
++	if (rtt_status->cur_idx >= rtt_status->rtt_config.rtt_target_cnt) {
++		err = BCME_RANGE;
++		DHD_ERROR(("%s : idx %d is out of range\n", __FUNCTION__, rtt_status->cur_idx));
++		goto exit;
++	}
++	if (RTT_IS_STOPPED(rtt_status)) {
++		DHD_ERROR(("RTT is stopped\n"));
++		goto exit;
++	}
++	/* turn off mpc in case of non-associted */
++	if (!dhd_is_associated(dhd, NULL, NULL)) {
++		err = dhd_iovar(dhd, 0, "mpc", (char *)&mpc, sizeof(mpc), NULL, 0, TRUE);
++		if (err) {
++			DHD_ERROR(("%s : failed to set mpc\n", __FUNCTION__));
++			goto exit;
++		}
++		rtt_status->mpc = 1; /* Either failure or complete, we need to enable mpc */
++	}
++
++	mutex_lock(&rtt_status->rtt_mutex);
++	/* Get a target information */
++	rtt_target = &rtt_status->rtt_config.target_info[rtt_status->cur_idx];
++	mutex_unlock(&rtt_status->rtt_mutex);
++	DHD_ERROR(("%s enter\n", __FUNCTION__));
++	if (!RTT_IS_ENABLED(rtt_status)) {
++		/* enable ftm */
++		err = dhd_rtt_ftm_enable(dhd, TRUE);
++		if (err) {
++			DHD_ERROR(("failed to enable FTM (%d)\n", err));
++			goto exit;
++		}
++	}
++
++	/* delete session of index default sesession  */
++	err = dhd_rtt_delete_session(dhd, FTM_DEFAULT_SESSION);
++	if (err < 0 && err != BCME_NOTFOUND) {
++		DHD_ERROR(("failed to delete session of FTM (%d)\n", err));
++		goto exit;
++	}
++	rtt_status->status = RTT_ENABLED;
++	memset(ftm_configs, 0, sizeof(ftm_configs));
++	memset(ftm_params, 0, sizeof(ftm_params));
++
++	/* configure the session 1 as initiator */
++	ftm_configs[ftm_cfg_cnt].enable = TRUE;
++	ftm_configs[ftm_cfg_cnt++].flags = WL_PROXD_SESSION_FLAG_INITIATOR;
++	dhd_rtt_ftm_config(dhd, FTM_DEFAULT_SESSION, FTM_CONFIG_CAT_OPTIONS,
++		ftm_configs, ftm_cfg_cnt);
++	/* target's mac address */
++	if (!ETHER_ISNULLADDR(rtt_target->addr.octet)) {
++		ftm_params[ftm_param_cnt].mac_addr = rtt_target->addr;
++		ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_PEER_MAC;
++		DHD_ERROR((">\t target %s\n", bcm_ether_ntoa(&rtt_target->addr, eabuf)));
++	}
++	/* target's chanspec */
++	if (rtt_target->chanspec) {
++		ftm_params[ftm_param_cnt].chanspec = htol32((uint32)rtt_target->chanspec);
++		ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_CHANSPEC;
++		DHD_ERROR((">\t chanspec : %s\n", wf_chspec_ntoa(rtt_target->chanspec, chanbuf)));
++	}
++	/* num-burst */
++	if (rtt_target->num_burst) {
++		ftm_params[ftm_param_cnt].data16 = htol16(rtt_target->num_burst);
++		ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_NUM_BURST;
++		DHD_ERROR((">\t num of burst : %d\n", rtt_target->num_burst));
++	}
++	/* number of frame per burst */
++	if (rtt_target->num_frames_per_burst == 0) {
++		rtt_target->num_frames_per_burst =
++			CHSPEC_IS20(rtt_target->chanspec) ? FTM_DEFAULT_CNT_20M :
++			CHSPEC_IS40(rtt_target->chanspec) ? FTM_DEFAULT_CNT_40M :
++			FTM_DEFAULT_CNT_80M;
++	}
++	ftm_params[ftm_param_cnt].data16 = htol16(rtt_target->num_frames_per_burst);
++	ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_BURST_NUM_FTM;
++	DHD_ERROR((">\t number of frame per burst : %d\n", rtt_target->num_frames_per_burst));
++	/* FTM retry count */
++	if (rtt_target->num_retries_per_ftm) {
++		ftm_params[ftm_param_cnt].data8 = rtt_target->num_retries_per_ftm;
++		ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_FTM_RETRIES;
++		DHD_ERROR((">\t retry count of FTM  : %d\n", rtt_target->num_retries_per_ftm));
++	}
++	/* FTM Request retry count */
++	if (rtt_target->num_retries_per_ftmr) {
++		ftm_params[ftm_param_cnt].data8 = rtt_target->num_retries_per_ftmr;
++		ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_FTM_REQ_RETRIES;
++		DHD_ERROR((">\t retry count of FTM Req : %d\n", rtt_target->num_retries_per_ftm));
++	}
++	/* burst-period */
++	if (rtt_target->burst_period) {
++		ftm_params[ftm_param_cnt].data_intvl.intvl =
++			htol32(rtt_target->burst_period); /* ms */
++		ftm_params[ftm_param_cnt].data_intvl.tmu = WL_PROXD_TMU_MILLI_SEC;
++		ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_BURST_PERIOD;
++		DHD_ERROR((">\t burst period : %d ms\n", rtt_target->burst_period));
++	}
++	/* burst-duration */
++	if (rtt_target->burst_duration) {
++		ftm_params[ftm_param_cnt].data_intvl.intvl =
++			htol32(rtt_target->burst_period); /* ms */
++		ftm_params[ftm_param_cnt].data_intvl.tmu = WL_PROXD_TMU_MILLI_SEC;
++		ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_BURST_DURATION;
++		DHD_ERROR((">\t burst duration : %d ms\n",
++			rtt_target->burst_duration));
++	}
++	if (rtt_target->bw && rtt_target->preamble) {
++		bool use_default = FALSE;
++		int nss;
++		int mcs;
++		switch (rtt_target->preamble) {
++		case RTT_PREAMBLE_LEGACY:
++			rspec |= WL_RSPEC_ENCODE_RATE; /* 11abg */
++			rspec |= WL_RATE_6M;
++			break;
++		case RTT_PREAMBLE_HT:
++			rspec |= WL_RSPEC_ENCODE_HT; /* 11n HT */
++			mcs = 0; /* default MCS 0 */
++			rspec |= mcs;
++			break;
++		case RTT_PREAMBLE_VHT:
++			rspec |= WL_RSPEC_ENCODE_VHT; /* 11ac VHT */
++			mcs = 0; /* default MCS 0 */
++			nss = 1; /* default Nss = 1  */
++			rspec |= (nss << WL_RSPEC_VHT_NSS_SHIFT) | mcs;
++			break;
++		default:
++			DHD_ERROR(("doesn't support this preamble : %d\n", rtt_target->preamble));
++			use_default = TRUE;
++			break;
++		}
++		switch (rtt_target->bw) {
++		case RTT_BW_20:
++			rspec |= WL_RSPEC_BW_20MHZ;
++			break;
++		case RTT_BW_40:
++			rspec |= WL_RSPEC_BW_40MHZ;
++			break;
++		case RTT_BW_80:
++			rspec |= WL_RSPEC_BW_80MHZ;
++			break;
++		default:
++			DHD_ERROR(("doesn't support this BW : %d\n", rtt_target->bw));
++			use_default = TRUE;
++			break;
++		}
++		if (!use_default) {
++			ftm_params[ftm_param_cnt].data32 = htol32(rspec);
++			ftm_params[ftm_param_cnt++].tlvid = WL_PROXD_TLV_ID_RATESPEC;
++			DHD_ERROR((">\t ratespec : %d\n", rspec));
++		}
++
++	}
++	dhd_rtt_ftm_config(dhd, FTM_DEFAULT_SESSION, FTM_CONFIG_CAT_GENERAL,
++		ftm_params, ftm_param_cnt);
++
++	err = dhd_rtt_start_session(dhd, FTM_DEFAULT_SESSION, TRUE);
++	if (err) {
++		DHD_ERROR(("failed to start session of FTM : error %d\n", err));
++	}
++exit:
++	if (err) {
++		rtt_status->status = RTT_STOPPED;
++		/* disable FTM */
++		dhd_rtt_ftm_enable(dhd, FALSE);
++		if (rtt_status->mpc) {
++			/* enable mpc again in case of error */
++			mpc = 1;
++			rtt_status->mpc = 0;
++			err = dhd_iovar(dhd, 0, "mpc", (char *)&mpc, sizeof(mpc),
++				NULL, 0, TRUE);
++		}
++	}
++	return err;
++}
++
++int
++dhd_rtt_register_noti_callback(dhd_pub_t *dhd, void *ctx, dhd_rtt_compl_noti_fn noti_fn)
++{
++	int err = BCME_OK;
++	struct rtt_noti_callback *cb = NULL, *iter;
++	rtt_status_info_t *rtt_status;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(noti_fn, "noti_fn is NULL", err);
++
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", err);
++	spin_lock_bh(&noti_list_lock);
++	list_for_each_entry(iter, &rtt_status->noti_fn_list, list) {
++		if (iter->noti_fn == noti_fn) {
++			goto exit;
++		}
++	}
++	cb = kmalloc(sizeof(struct rtt_noti_callback), GFP_ATOMIC);
++	if (!cb) {
++		err = -ENOMEM;
++		goto exit;
++	}
++	cb->noti_fn = noti_fn;
++	cb->ctx = ctx;
++	list_add(&cb->list, &rtt_status->noti_fn_list);
++exit:
++	spin_unlock_bh(&noti_list_lock);
++	return err;
++}
++
++int
++dhd_rtt_unregister_noti_callback(dhd_pub_t *dhd, dhd_rtt_compl_noti_fn noti_fn)
++{
++	int err = BCME_OK;
++	struct rtt_noti_callback *cb = NULL, *iter;
++	rtt_status_info_t *rtt_status;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	NULL_CHECK(noti_fn, "noti_fn is NULL", err);
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", err);
++	spin_lock_bh(&noti_list_lock);
++	list_for_each_entry(iter, &rtt_status->noti_fn_list, list) {
++		if (iter->noti_fn == noti_fn) {
++			cb = iter;
++			list_del(&cb->list);
++			break;
++		}
++	}
++	spin_unlock_bh(&noti_list_lock);
++	if (cb) {
++		kfree(cb);
++	}
++	return err;
++}
++
++static wifi_rate_t
++dhd_rtt_convert_rate_to_host(uint32 rspec)
++{
++	wifi_rate_t host_rate;
++	memset(&host_rate, 0, sizeof(wifi_rate_t));
++	if ((rspec & WL_RSPEC_ENCODING_MASK) == WL_RSPEC_ENCODE_RATE) {
++		host_rate.preamble = 0;
++	} else if ((rspec & WL_RSPEC_ENCODING_MASK) == WL_RSPEC_ENCODE_HT) {
++		host_rate.preamble = 2;
++		host_rate.rateMcsIdx = rspec & WL_RSPEC_RATE_MASK;
++	} else if ((rspec & WL_RSPEC_ENCODING_MASK) == WL_RSPEC_ENCODE_VHT) {
++		host_rate.preamble = 3;
++		host_rate.rateMcsIdx = rspec & WL_RSPEC_VHT_MCS_MASK;
++		host_rate.nss = (rspec & WL_RSPEC_VHT_NSS_MASK) >> WL_RSPEC_VHT_NSS_SHIFT;
++	}
++	host_rate.bw = (rspec & WL_RSPEC_BW_MASK) - 1;
++	host_rate.bitrate = rate_rspec2rate(rspec) / 100; /* 100kbps */
++	DHD_RTT(("bit rate : %d\n", host_rate.bitrate));
++	return host_rate;
++}
++
++
++static int
++dhd_rtt_convert_results_to_host(rtt_report_t *rtt_report, uint8 *p_data, uint16 tlvid, uint16 len)
++{
++	int err = BCME_OK;
++	char eabuf[ETHER_ADDR_STR_LEN];
++	wl_proxd_rtt_result_t *p_data_info;
++	wl_proxd_result_flags_t flags;
++	wl_proxd_session_state_t session_state;
++	wl_proxd_status_t proxd_status;
++	struct timespec64 ts;
++	uint32 ratespec;
++	uint32 avg_dist;
++	wl_proxd_rtt_sample_t *p_sample;
++	wl_proxd_intvl_t rtt;
++	wl_proxd_intvl_t p_time;
++
++	NULL_CHECK(rtt_report, "rtt_report is NULL", err);
++	NULL_CHECK(p_data, "p_data is NULL", err);
++	DHD_RTT(("%s enter\n", __FUNCTION__));
++	p_data_info = (wl_proxd_rtt_result_t *) p_data;
++	/* unpack and format 'flags' for display */
++	flags = ltoh16_ua(&p_data_info->flags);
++
++	/* session state and status */
++	session_state = ltoh16_ua(&p_data_info->state);
++	proxd_status = ltoh32_ua(&p_data_info->status);
++	DHD_RTT((">\tTarget(%s) session state=%d(%s), status=%d(%s)\n",
++		bcm_ether_ntoa((&(p_data_info->peer)), eabuf),
++		session_state,
++		ftm_session_state_value_to_logstr(session_state),
++		proxd_status,
++		ftm_status_value_to_logstr(proxd_status)));
++
++	/* show avg_dist (1/256m units), burst_num */
++	avg_dist = ltoh32_ua(&p_data_info->avg_dist);
++	if (avg_dist == 0xffffffff) {	/* report 'failure' case */
++		DHD_RTT((">\tavg_dist=-1m, burst_num=%d, valid_measure_cnt=%d\n",
++		ltoh16_ua(&p_data_info->burst_num),
++		p_data_info->num_valid_rtt)); /* in a session */
++		avg_dist = FTM_INVALID;
++	}
++	else {
++		DHD_RTT((">\tavg_dist=%d.%04dm, burst_num=%d, valid_measure_cnt=%d num_ftm=%d\n",
++			avg_dist >> 8, /* 1/256m units */
++			((avg_dist & 0xff) * 625) >> 4,
++			ltoh16_ua(&p_data_info->burst_num),
++			p_data_info->num_valid_rtt,
++			p_data_info->num_ftm)); /* in a session */
++	}
++	/* show 'avg_rtt' sample */
++	p_sample = &p_data_info->avg_rtt;
++	DHD_RTT((">\tavg_rtt sample: rssi=%d rtt=%d%s std_deviation =%d.%d ratespec=0x%08x\n",
++		(int16) ltoh16_ua(&p_sample->rssi),
++		ltoh32_ua(&p_sample->rtt.intvl),
++		ftm_tmu_value_to_logstr(ltoh16_ua(&p_sample->rtt.tmu)),
++		ltoh16_ua(&p_data_info->sd_rtt)/10, ltoh16_ua(&p_data_info->sd_rtt)%10,
++		ltoh32_ua(&p_sample->ratespec)));
++
++	/* set peer address */
++	rtt_report->addr = p_data_info->peer;
++	/* burst num */
++	rtt_report->burst_num = ltoh16_ua(&p_data_info->burst_num);
++	/* success num */
++	rtt_report->success_num = p_data_info->num_valid_rtt;
++	/* actual number of FTM supported by peer */
++	rtt_report->num_per_burst_peer = p_data_info->num_ftm;
++	rtt_report->negotiated_burst_num = p_data_info->num_ftm;
++	/* status */
++	rtt_report->status = ftm_get_statusmap_info(proxd_status,
++			&ftm_status_map_info[0], ARRAYSIZE(ftm_status_map_info));
++	/* rssi (0.5db) */
++	rtt_report->rssi = (int16)ltoh16_ua(&p_data_info->avg_rtt.rssi) * 2;
++	/* rx rate */
++	ratespec = ltoh32_ua(&p_data_info->avg_rtt.ratespec);
++	rtt_report->rx_rate = dhd_rtt_convert_rate_to_host(ratespec);
++	/* tx rate */
++	if (flags & WL_PROXD_RESULT_FLAG_VHTACK) {
++		rtt_report->tx_rate = dhd_rtt_convert_rate_to_host(0x2010010);
++	} else {
++		rtt_report->tx_rate = dhd_rtt_convert_rate_to_host(0xc);
++	}
++	/* rtt_sd */
++	rtt.tmu = ltoh16_ua(&p_data_info->avg_rtt.rtt.tmu);
++	rtt.intvl = ltoh32_ua(&p_data_info->avg_rtt.rtt.intvl);
++	rtt_report->rtt = FTM_INTVL2NSEC(&rtt) * 10; /* nano -> 0.1 nano */
++	rtt_report->rtt_sd = ltoh16_ua(&p_data_info->sd_rtt); /* nano -> 0.1 nano */
++	DHD_RTT(("rtt_report->rtt : %llu\n", rtt_report->rtt));
++	DHD_RTT(("rtt_report->rssi : %d (0.5db)\n", rtt_report->rssi));
++
++	/* average distance */
++	if (avg_dist != FTM_INVALID) {
++		rtt_report->distance = (avg_dist >> 8) * 100; /* meter -> cm */
++		rtt_report->distance += (avg_dist & 0xff) * 100 / 256;
++	} else {
++		rtt_report->distance = FTM_INVALID;
++	}
++	/* time stamp */
++	/* get the time elapsed from boot time */
++        getboottime64(&ts);
++	rtt_report->ts = (uint64)TIMESPEC_TO_US(ts);
++
++	if (proxd_status == WL_PROXD_E_REMOTE_FAIL) {
++		/* retry time  after failure */
++		p_time.intvl = ltoh32_ua(&p_data_info->u.retry_after.intvl);
++		p_time.tmu = ltoh16_ua(&p_data_info->u.retry_after.tmu);
++		rtt_report->retry_after_duration = FTM_INTVL2SEC(&p_time); /* s -> s */
++		DHD_RTT((">\tretry_after: %d%s\n",
++			ltoh32_ua(&p_data_info->u.retry_after.intvl),
++			ftm_tmu_value_to_logstr(ltoh16_ua(&p_data_info->u.retry_after.tmu))));
++	} else {
++		/* burst duration */
++		p_time.intvl = ltoh32_ua(&p_data_info->u.retry_after.intvl);
++		p_time.tmu = ltoh16_ua(&p_data_info->u.retry_after.tmu);
++		rtt_report->burst_duration =  FTM_INTVL2MSEC(&p_time); /* s -> ms */
++		DHD_RTT((">\tburst_duration: %d%s\n",
++			ltoh32_ua(&p_data_info->u.burst_duration.intvl),
++			ftm_tmu_value_to_logstr(ltoh16_ua(&p_data_info->u.burst_duration.tmu))));
++		DHD_RTT(("rtt_report->burst_duration : %d\n", rtt_report->burst_duration));
++	}
++	return err;
++}
++
++int
++dhd_rtt_event_handler(dhd_pub_t *dhd, wl_event_msg_t *event, void *event_data)
++{
++	int ret = BCME_OK;
++	int tlvs_len;
++	int idx;
++	uint16 version;
++	wl_proxd_event_t *p_event;
++	wl_proxd_event_type_t event_type;
++	wl_proxd_ftm_session_status_t session_status;
++	const ftm_strmap_entry_t *p_loginfo;
++	rtt_status_info_t *rtt_status;
++	rtt_target_info_t *rtt_target_info;
++	struct rtt_noti_callback *iter;
++	rtt_results_header_t *entry, *next, *rtt_results_header = NULL;
++	rtt_result_t *rtt_result, *next2;
++	gfp_t kflags;
++	bool is_new = TRUE;
++
++	NULL_CHECK(dhd, "dhd is NULL", ret);
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", ret);
++
++	if (ntoh32_ua((void *)&event->datalen) < OFFSETOF(wl_proxd_event_t, tlvs)) {
++		DHD_RTT(("%s: wrong datalen:%d\n", __FUNCTION__,
++			ntoh32_ua((void *)&event->datalen)));
++		return -EINVAL;
++	}
++	event_type = ntoh32_ua((void *)&event->event_type);
++	if (event_type != WLC_E_PROXD) {
++		DHD_ERROR((" failed event \n"));
++		return -EINVAL;
++	}
++
++	if (!event_data) {
++		DHD_ERROR(("%s: event_data:NULL\n", __FUNCTION__));
++		return -EINVAL;
++	}
++
++	if (RTT_IS_STOPPED(rtt_status)) {
++		/* Ignore the Proxd event */
++		return ret;
++	}
++	p_event = (wl_proxd_event_t *) event_data;
++	version = ltoh16(p_event->version);
++	if (version < WL_PROXD_API_VERSION) {
++		DHD_ERROR(("ignore non-ftm event version = 0x%0x < WL_PROXD_API_VERSION (0x%x)\n",
++			version, WL_PROXD_API_VERSION));
++		return ret;
++	}
++	if (!in_atomic()) {
++		mutex_lock(&rtt_status->rtt_mutex);
++	}
++	event_type = (wl_proxd_event_type_t) ltoh16(p_event->type);
++
++	kflags = in_softirq()? GFP_ATOMIC : GFP_KERNEL;
++
++	DHD_RTT(("event_type=0x%x, ntoh16()=0x%x, ltoh16()=0x%x\n",
++		p_event->type, ntoh16(p_event->type), ltoh16(p_event->type)));
++	p_loginfo = ftm_get_event_type_loginfo(event_type);
++	if (p_loginfo == NULL) {
++		DHD_ERROR(("receive an invalid FTM event %d\n", event_type));
++		ret = -EINVAL;
++		goto exit;	/* ignore this event */
++	}
++	/* get TLVs len, skip over event header */
++	if (ltoh16(p_event->len) < OFFSETOF(wl_proxd_event_t, tlvs)) {
++		DHD_ERROR(("invalid FTM event length:%d\n", ltoh16(p_event->len)));
++		ret = -EINVAL;
++		goto exit;
++	}
++	tlvs_len = ltoh16(p_event->len) - OFFSETOF(wl_proxd_event_t, tlvs);
++	DHD_RTT(("receive '%s' event: version=0x%x len=%d method=%d sid=%d tlvs_len=%d\n",
++		p_loginfo->text,
++		version,
++		ltoh16(p_event->len),
++		ltoh16(p_event->method),
++		ltoh16(p_event->sid),
++		tlvs_len));
++	rtt_target_info = &rtt_status->rtt_config.target_info[rtt_status->cur_idx];
++	/* find a rtt_report_header for this mac address */
++	list_for_each_entry(entry, &rtt_status->rtt_results_cache, list) {
++		 if (!memcmp(&entry->peer_mac, &event->addr, ETHER_ADDR_LEN))  {
++			/* found a rtt_report_header for peer_mac in the list */
++			is_new = FALSE;
++			rtt_results_header = entry;
++			break;
++		 }
++	}
++
++	switch (event_type) {
++	case WL_PROXD_EVENT_SESSION_CREATE:
++		DHD_RTT(("WL_PROXD_EVENT_SESSION_CREATE\n"));
++		break;
++	case WL_PROXD_EVENT_SESSION_START:
++		DHD_RTT(("WL_PROXD_EVENT_SESSION_START\n"));
++		break;
++	case WL_PROXD_EVENT_BURST_START:
++		DHD_RTT(("WL_PROXD_EVENT_BURST_START\n"));
++		break;
++	case WL_PROXD_EVENT_BURST_END:
++		DHD_RTT(("WL_PROXD_EVENT_BURST_END\n"));
++		if (is_new) {
++			/* allocate new header for rtt_results */
++			rtt_results_header = kzalloc(sizeof(rtt_results_header_t), kflags);
++			if (!rtt_results_header) {
++				ret = -ENOMEM;
++				goto exit;
++			}
++			/* Initialize the head of list for rtt result */
++			INIT_LIST_HEAD(&rtt_results_header->result_list);
++			rtt_results_header->peer_mac = event->addr;
++			list_add_tail(&rtt_results_header->list, &rtt_status->rtt_results_cache);
++		}
++		if (tlvs_len > 0) {
++			/* allocate rtt_results for new results */
++			rtt_result = kzalloc(sizeof(rtt_result_t), kflags);
++			if (!rtt_result) {
++				ret = -ENOMEM;
++				goto exit;
++			}
++			/* unpack TLVs and invokes the cbfn to print the event content TLVs */
++			ret = bcm_unpack_xtlv_buf((void *) &(rtt_result->report),
++				(uint8 *)&p_event->tlvs[0], tlvs_len,
++				BCM_XTLV_OPTION_ALIGN32, rtt_unpack_xtlv_cbfn);
++			if (ret != BCME_OK) {
++				DHD_ERROR(("%s : Failed to unpack xtlv for an event\n",
++					__FUNCTION__));
++				goto exit;
++			}
++			/* fill out the results from the configuration param */
++			rtt_result->report.ftm_num = rtt_target_info->num_frames_per_burst;
++			rtt_result->report.type = RTT_TWO_WAY;
++			DHD_RTT(("report->ftm_num : %d\n", rtt_result->report.ftm_num));
++			rtt_result->report_len = RTT_REPORT_SIZE;
++
++			list_add_tail(&rtt_result->list, &rtt_results_header->result_list);
++			rtt_results_header->result_cnt++;
++			rtt_results_header->result_tot_len += rtt_result->report_len;
++		}
++		break;
++	case WL_PROXD_EVENT_SESSION_END:
++			DHD_RTT(("WL_PROXD_EVENT_SESSION_END\n"));
++		if (!RTT_IS_ENABLED(rtt_status)) {
++			DHD_RTT(("Ignore the session end evt\n"));
++			goto exit;
++		}
++		if (tlvs_len > 0) {
++			/* unpack TLVs and invokes the cbfn to print the event content TLVs */
++			ret = bcm_unpack_xtlv_buf((void *) &session_status,
++				(uint8 *)&p_event->tlvs[0], tlvs_len,
++				BCM_XTLV_OPTION_ALIGN32, rtt_unpack_xtlv_cbfn);
++			if (ret != BCME_OK) {
++				DHD_ERROR(("%s : Failed to unpack xtlv for an event\n",
++					__FUNCTION__));
++				goto exit;
++			}
++		}
++		/* In case of no result for the peer device, make fake result for error case */
++		if (is_new) {
++			/* allocate new header for rtt_results */
++			rtt_results_header = kzalloc(sizeof(rtt_results_header_t), GFP_KERNEL);
++			if (!rtt_results_header) {
++				ret = -ENOMEM;
++				goto exit;
++			}
++			/* Initialize the head of list for rtt result */
++			INIT_LIST_HEAD(&rtt_results_header->result_list);
++			rtt_results_header->peer_mac = event->addr;
++			list_add_tail(&rtt_results_header->list, &rtt_status->rtt_results_cache);
++
++			/* allocate rtt_results for new results */
++			rtt_result = kzalloc(sizeof(rtt_result_t), kflags);
++			if (!rtt_result) {
++				ret = -ENOMEM;
++				kfree(rtt_results_header);
++				goto exit;
++			}
++			/* fill out the results from the configuration param */
++			rtt_result->report.ftm_num = rtt_target_info->num_frames_per_burst;
++			rtt_result->report.type = RTT_TWO_WAY;
++			DHD_RTT(("report->ftm_num : %d\n", rtt_result->report.ftm_num));
++			rtt_result->report_len = RTT_REPORT_SIZE;
++			rtt_result->report.status = RTT_REASON_FAIL_NO_RSP;
++			rtt_result->report.addr = rtt_target_info->addr;
++			rtt_result->report.distance = FTM_INVALID;
++			list_add_tail(&rtt_result->list, &rtt_results_header->result_list);
++			rtt_results_header->result_cnt++;
++			rtt_results_header->result_tot_len += rtt_result->report_len;
++		}
++		/* find next target to trigger RTT */
++		for (idx = (rtt_status->cur_idx + 1);
++			idx < rtt_status->rtt_config.rtt_target_cnt; idx++) {
++			/* skip the disabled device */
++			if (rtt_status->rtt_config.target_info[idx].disable) {
++				continue;
++			} else {
++				/* set the idx to cur_idx */
++				rtt_status->cur_idx = idx;
++				break;
++			}
++		}
++		if (idx < rtt_status->rtt_config.rtt_target_cnt) {
++			/* restart to measure RTT from next device */
++			schedule_work(&rtt_status->work);
++		} else {
++			DHD_RTT(("RTT_STOPPED\n"));
++			rtt_status->status = RTT_STOPPED;
++			/* to turn on mpc mode */
++			schedule_work(&rtt_status->work);
++			/* notify the completed information to others */
++			list_for_each_entry(iter, &rtt_status->noti_fn_list, list) {
++				iter->noti_fn(iter->ctx, &rtt_status->rtt_results_cache);
++			}
++			/* remove the rtt results in cache */
++			if (!list_empty(&rtt_status->rtt_results_cache)) {
++				/* Iterate rtt_results_header list */
++				list_for_each_entry_safe(entry, next,
++					&rtt_status->rtt_results_cache, list) {
++					list_del(&entry->list);
++					/* Iterate rtt_result list */
++					list_for_each_entry_safe(rtt_result, next2,
++						&entry->result_list, list) {
++						list_del(&rtt_result->list);
++						kfree(rtt_result);
++					}
++					kfree(entry);
++				}
++			}
++
++			/* reinitialize the HEAD */
++			INIT_LIST_HEAD(&rtt_status->rtt_results_cache);
++			/* clear information for rtt_config */
++			rtt_status->rtt_config.rtt_target_cnt = 0;
++			memset(rtt_status->rtt_config.target_info, 0,
++				TARGET_INFO_SIZE(RTT_MAX_TARGET_CNT));
++			rtt_status->cur_idx = 0;
++		}
++		break;
++	case WL_PROXD_EVENT_SESSION_RESTART:
++		DHD_RTT(("WL_PROXD_EVENT_SESSION_RESTART\n"));
++		break;
++	case WL_PROXD_EVENT_BURST_RESCHED:
++		DHD_RTT(("WL_PROXD_EVENT_BURST_RESCHED\n"));
++		break;
++	case WL_PROXD_EVENT_SESSION_DESTROY:
++		DHD_RTT(("WL_PROXD_EVENT_SESSION_DESTROY\n"));
++		break;
++	case WL_PROXD_EVENT_FTM_FRAME:
++		DHD_RTT(("WL_PROXD_EVENT_FTM_FRAME\n"));
++		break;
++	case WL_PROXD_EVENT_DELAY:
++		DHD_RTT(("WL_PROXD_EVENT_DELAY\n"));
++		break;
++	case WL_PROXD_EVENT_VS_INITIATOR_RPT:
++		DHD_RTT(("WL_PROXD_EVENT_VS_INITIATOR_RPT\n "));
++		break;
++	case WL_PROXD_EVENT_RANGING:
++		DHD_RTT(("WL_PROXD_EVENT_RANGING\n"));
++		break;
++
++	default:
++		DHD_ERROR(("WLC_E_PROXD: not supported EVENT Type:%d\n", event_type));
++		break;
++	}
++exit:
++	if (!in_atomic()) {
++		mutex_unlock(&rtt_status->rtt_mutex);
++	}
++
++	return ret;
++}
++
++static void
++dhd_rtt_work(struct work_struct *work)
++{
++	rtt_status_info_t *rtt_status;
++	dhd_pub_t *dhd;
++	rtt_status = container_of(work, rtt_status_info_t, work);
++	if (rtt_status == NULL) {
++		DHD_ERROR(("%s : rtt_status is NULL\n", __FUNCTION__));
++		return;
++	}
++	dhd = rtt_status->dhd;
++	if (dhd == NULL) {
++		DHD_ERROR(("%s : dhd is NULL\n", __FUNCTION__));
++		return;
++	}
++	(void) dhd_rtt_start(dhd);
++}
++
++int
++dhd_rtt_capability(dhd_pub_t *dhd, rtt_capabilities_t *capa)
++{
++	rtt_status_info_t *rtt_status;
++	int err = BCME_OK;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", err);
++	NULL_CHECK(capa, "capa is NULL", err);
++	bzero(capa, sizeof(rtt_capabilities_t));
++	switch (rtt_status->rtt_capa.proto) {
++	case RTT_CAP_ONE_WAY:
++		capa->rtt_one_sided_supported = 1;
++		break;
++	case RTT_CAP_FTM_WAY:
++		capa->rtt_ftm_supported = 1;
++		break;
++	}
++
++	switch (rtt_status->rtt_capa.feature) {
++	case RTT_FEATURE_LCI:
++		capa->lci_support = 1;
++		break;
++	case RTT_FEATURE_LCR:
++		capa->lcr_support = 1;
++		break;
++	case RTT_FEATURE_PREAMBLE:
++		capa->preamble_support = 1;
++		break;
++	case RTT_FEATURE_BW:
++		capa->bw_support = 1;
++		break;
++	}
++	/* bit mask */
++	capa->preamble_support = rtt_status->rtt_capa.preamble;
++	capa->bw_support = rtt_status->rtt_capa.bw;
++
++	return err;
++}
++
++int
++dhd_rtt_init(dhd_pub_t *dhd)
++{
++	int err = BCME_OK, ret;
++	int32 up = 1;
++	int32 version;
++	rtt_status_info_t *rtt_status;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	if (dhd->rtt_state) {
++		return err;
++	}
++	dhd->rtt_state = kzalloc(sizeof(rtt_status_info_t), GFP_KERNEL);
++	if (dhd->rtt_state == NULL) {
++		err = BCME_NOMEM;
++		DHD_ERROR(("%s : failed to create rtt_state\n", __FUNCTION__));
++		return err;
++	}
++	bzero(dhd->rtt_state, sizeof(rtt_status_info_t));
++	rtt_status = GET_RTTSTATE(dhd);
++	rtt_status->rtt_config.target_info =
++			kzalloc(TARGET_INFO_SIZE(RTT_MAX_TARGET_CNT), GFP_KERNEL);
++	if (rtt_status->rtt_config.target_info == NULL) {
++		DHD_ERROR(("%s failed to allocate the target info for %d\n",
++			__FUNCTION__, RTT_MAX_TARGET_CNT));
++		err = BCME_NOMEM;
++		goto exit;
++	}
++	rtt_status->dhd = dhd;
++	/* need to do WLC_UP  */
++	dhd_wl_ioctl_cmd(dhd, WLC_UP, (char *)&up, sizeof(int32), TRUE, 0);
++
++	ret = dhd_rtt_get_version(dhd, &version);
++	if (ret == BCME_OK && (version == WL_PROXD_API_VERSION)) {
++		DHD_ERROR(("%s : FTM is supported\n", __FUNCTION__));
++		/* rtt_status->rtt_capa.proto |= RTT_CAP_ONE_WAY; */
++		rtt_status->rtt_capa.proto |= RTT_CAP_FTM_WAY;
++
++		/* indicate to set tx rate */
++		rtt_status->rtt_capa.feature |= RTT_FEATURE_PREAMBLE;
++		rtt_status->rtt_capa.preamble |= RTT_PREAMBLE_VHT;
++		rtt_status->rtt_capa.preamble |= RTT_PREAMBLE_HT;
++
++		/* indicate to set bandwith */
++		rtt_status->rtt_capa.feature |= RTT_FEATURE_BW;
++		rtt_status->rtt_capa.bw |= RTT_BW_20;
++		rtt_status->rtt_capa.bw |= RTT_BW_40;
++		rtt_status->rtt_capa.bw |= RTT_BW_80;
++	} else {
++		if ((ret != BCME_OK) || (version == 0)) {
++			DHD_ERROR(("%s : FTM is not supported\n", __FUNCTION__));
++		} else {
++			DHD_ERROR(("%s : FTM version mismatch between HOST (%d) and FW (%d)\n",
++				__FUNCTION__, WL_PROXD_API_VERSION, version));
++		}
++	}
++	/* cancel all of RTT request once we got the cancel request */
++	rtt_status->all_cancel = TRUE;
++	mutex_init(&rtt_status->rtt_mutex);
++	INIT_LIST_HEAD(&rtt_status->noti_fn_list);
++	INIT_LIST_HEAD(&rtt_status->rtt_results_cache);
++	INIT_WORK(&rtt_status->work, dhd_rtt_work);
++exit:
++	if (err < 0) {
++		kfree(rtt_status->rtt_config.target_info);
++		kfree(dhd->rtt_state);
++	}
++	return err;
++}
++
++int
++dhd_rtt_deinit(dhd_pub_t *dhd)
++{
++	int err = BCME_OK;
++	rtt_status_info_t *rtt_status;
++	rtt_results_header_t *rtt_header, *next;
++	rtt_result_t *rtt_result, *next2;
++	struct rtt_noti_callback *iter, *iter2;
++	NULL_CHECK(dhd, "dhd is NULL", err);
++	rtt_status = GET_RTTSTATE(dhd);
++	NULL_CHECK(rtt_status, "rtt_status is NULL", err);
++	rtt_status->status = RTT_STOPPED;
++	/* clear evt callback list */
++	if (!list_empty(&rtt_status->noti_fn_list)) {
++		list_for_each_entry_safe(iter, iter2, &rtt_status->noti_fn_list, list) {
++			list_del(&iter->list);
++			kfree(iter);
++		}
++	}
++	/* remove the rtt results */
++	if (!list_empty(&rtt_status->rtt_results_cache)) {
++		list_for_each_entry_safe(rtt_header, next, &rtt_status->rtt_results_cache, list) {
++			list_del(&rtt_header->list);
++			list_for_each_entry_safe(rtt_result, next2,
++				&rtt_header->result_list, list) {
++				list_del(&rtt_result->list);
++				kfree(rtt_result);
++			}
++			kfree(rtt_header);
++		}
++	}
++	kfree(rtt_status->rtt_config.target_info);
++	kfree(dhd->rtt_state);
++	dhd->rtt_state = NULL;
++	return err;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_rtt.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_rtt.h
+new file mode 100644
+index 000000000..9d20d55cf
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_rtt.h
+@@ -0,0 +1,338 @@
++/*
++ * Broadcom Dongle Host Driver (DHD), RTT
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * $Id: dhd_rtt.h 578013 2015-08-10 05:56:41Z $
++ */
++#ifndef __DHD_RTT_H__
++#define __DHD_RTT_H__
++
++#include "dngl_stats.h"
++
++#define RTT_MAX_TARGET_CNT	50
++#define RTT_MAX_FRAME_CNT	25
++#define RTT_MAX_RETRY_CNT	10
++#define DEFAULT_FTM_CNT		6
++#define DEFAULT_RETRY_CNT	6
++#define TARGET_INFO_SIZE(count) (sizeof(rtt_target_info_t) * count)
++
++#define TARGET_TYPE(target) (target->type)
++
++#ifndef BIT
++#define BIT(x) (1 << (x))
++#endif
++
++/* DSSS, CCK and 802.11n rates in [500kbps] units */
++#define WL_MAXRATE	108	/* in 500kbps units */
++#define WL_RATE_1M	2	/* in 500kbps units */
++#define WL_RATE_2M	4	/* in 500kbps units */
++#define WL_RATE_5M5	11	/* in 500kbps units */
++#define WL_RATE_11M	22	/* in 500kbps units */
++#define WL_RATE_6M	12	/* in 500kbps units */
++#define WL_RATE_9M	18	/* in 500kbps units */
++#define WL_RATE_12M	24	/* in 500kbps units */
++#define WL_RATE_18M	36	/* in 500kbps units */
++#define WL_RATE_24M	48	/* in 500kbps units */
++#define WL_RATE_36M	72	/* in 500kbps units */
++#define WL_RATE_48M	96	/* in 500kbps units */
++#define WL_RATE_54M	108	/* in 500kbps units */
++
++
++enum rtt_role {
++	RTT_INITIATOR = 0,
++	RTT_TARGET = 1
++};
++
++enum rtt_status {
++	RTT_STOPPED = 0,
++	RTT_STARTED = 1,
++	RTT_ENABLED = 2
++};
++
++typedef int64_t wifi_timestamp; /* In microseconds (us) */
++typedef int64_t wifi_timespan;
++typedef int32 wifi_rssi;
++
++typedef enum {
++	RTT_INVALID,
++	RTT_ONE_WAY,
++	RTT_TWO_WAY,
++	RTT_AUTO
++} rtt_type_t;
++
++typedef enum {
++	RTT_PEER_STA,
++	RTT_PEER_AP,
++	RTT_PEER_P2P,
++	RTT_PEER_NAN,
++	RTT_PEER_INVALID
++} rtt_peer_type_t;
++
++typedef enum rtt_reason {
++	RTT_REASON_SUCCESS,
++	RTT_REASON_FAILURE,
++	RTT_REASON_FAIL_NO_RSP,
++	RTT_REASON_FAIL_INVALID_TS, /* Invalid timestamp */
++	RTT_REASON_FAIL_PROTOCOL, /* 11mc protocol failed */
++	RTT_REASON_FAIL_REJECTED,
++	RTT_REASON_FAIL_NOT_SCHEDULED_YET,
++	RTT_REASON_FAIL_SCHEDULE, /* schedule failed */
++	RTT_REASON_FAIL_TM_TIMEOUT,
++	RTT_REASON_FAIL_AP_ON_DIFF_CHANNEL,
++	RTT_REASON_FAIL_NO_CAPABILITY,
++	RTT_REASON_FAIL_BUSY_TRY_LATER,
++	RTT_REASON_ABORTED
++} rtt_reason_t;
++
++enum {
++	RTT_CAP_ONE_WAY	 = BIT(0),
++	/* IEEE802.11mc */
++	RTT_CAP_FTM_WAY  = BIT(1)
++};
++
++enum {
++	RTT_FEATURE_LCI = BIT(0),
++	RTT_FEATURE_LCR = BIT(1),
++	RTT_FEATURE_PREAMBLE = BIT(2),
++	RTT_FEATURE_BW = BIT(3)
++};
++
++enum {
++	RTT_PREAMBLE_LEGACY = BIT(0),
++	RTT_PREAMBLE_HT = BIT(1),
++	RTT_PREAMBLE_VHT = BIT(2)
++};
++
++enum {
++	RTT_BW_5 = BIT(0),
++	RTT_BW_10 = BIT(1),
++	RTT_BW_20 = BIT(2),
++	RTT_BW_40 = BIT(3),
++	RTT_BW_80 = BIT(4),
++	RTT_BW_160 = BIT(5)
++};
++
++#define FTM_MAX_NUM_BURST_EXP	14
++#define HAS_11MC_CAP(cap) (cap & RTT_CAP_FTM_WAY)
++#define HAS_ONEWAY_CAP(cap) (cap & RTT_CAP_ONE_WAY)
++#define HAS_RTT_CAP(cap) (HAS_ONEWAY_CAP(cap) || HAS_11MC_CAP(cap))
++
++typedef struct wifi_channel_info {
++	wifi_channel_width_t width;
++	wifi_channel center_freq; /* primary 20 MHz channel */
++	wifi_channel center_freq0; /* center freq (MHz) first segment */
++	wifi_channel center_freq1; /* center freq (MHz) second segment valid for 80 + 80 */
++} wifi_channel_info_t;
++
++typedef struct wifi_rate {
++	uint32 preamble		:3; /* 0: OFDM, 1: CCK, 2 : HT, 3: VHT, 4..7 reserved */
++	uint32 nss		:2; /* 1 : 1x1, 2: 2x2, 3: 3x3, 4: 4x4 */
++	uint32 bw		:3; /* 0: 20Mhz, 1: 40Mhz, 2: 80Mhz, 3: 160Mhz */
++	/* OFDM/CCK rate code would be as per IEEE std in the unit of 0.5 mb
++	* HT/VHT it would be mcs index
++	*/
++	uint32 rateMcsIdx :8;
++	uint32 reserved :16; /* reserved */
++	uint32 bitrate;	/* unit of 100 Kbps */
++} wifi_rate_t;
++
++typedef struct rtt_target_info {
++	struct ether_addr addr;
++	rtt_type_t type; /* rtt_type */
++	rtt_peer_type_t peer; /* peer type */
++	wifi_channel_info_t channel; /* channel information */
++	chanspec_t chanspec; /* chanspec for channel */
++	bool	disable; /* disable for RTT measurement */
++	/*
++	* Time interval between bursts (units: 100 ms).
++	* Applies to 1-sided and 2-sided RTT multi-burst requests.
++	* Range: 0-31, 0: no preference by initiator (2-sided RTT)
++	*/
++	uint32	burst_period;
++	/*
++	* Total number of RTT bursts to be executed. It will be
++	* specified in the same way as the parameter "Number of
++	* Burst Exponent" found in the FTM frame format. It
++	* applies to both: 1-sided RTT and 2-sided RTT. Valid
++	* values are 0 to 15 as defined in 802.11mc std.
++	* 0 means single shot
++	* The implication of this parameter on the maximum
++	* number of RTT results is the following:
++	* for 1-sided RTT: max num of RTT results = (2^num_burst)*(num_frames_per_burst)
++	* for 2-sided RTT: max num of RTT results = (2^num_burst)*(num_frames_per_burst - 1)
++	*/
++	uint16 num_burst;
++	/*
++	* num of frames per burst.
++	* Minimum value = 1, Maximum value = 31
++	* For 2-sided this equals the number of FTM frames
++	* to be attempted in a single burst. This also
++	* equals the number of FTM frames that the
++	* initiator will request that the responder send
++	* in a single frame
++	*/
++	uint32 num_frames_per_burst;
++	/* num of frames in each RTT burst
++	 * for single side, measurement result num = frame number
++	 * for 2 side RTT, measurement result num  = frame number - 1
++	 */
++	uint32 num_retries_per_ftm; /* retry time for RTT measurment frame */
++	/* following fields are only valid for 2 side RTT */
++	uint32 num_retries_per_ftmr;
++	uint8  LCI_request;
++	uint8  LCR_request;
++	/*
++	* Applies to 1-sided and 2-sided RTT. Valid values will
++	* be 2-11 and 15 as specified by the 802.11mc std for
++	* the FTM parameter burst duration. In a multi-burst
++	* request, if responder overrides with larger value,
++	* the initiator will return failure. In a single-burst
++	* request if responder overrides with larger value,
++	* the initiator will sent TMR_STOP to terminate RTT
++	* at the end of the burst_duration it requested.
++	*/
++	uint32 burst_duration;
++	uint8  preamble; /* 1 - Legacy, 2 - HT, 4 - VHT */
++	uint8  bw;  /* 5, 10, 20, 40, 80, 160 */
++} rtt_target_info_t;
++
++typedef struct rtt_report {
++	struct ether_addr addr;
++	unsigned int burst_num; /* # of burst inside a multi-burst request */
++	unsigned int ftm_num; /* total RTT measurement frames attempted */
++	unsigned int success_num; /* total successful RTT measurement frames */
++	uint8  num_per_burst_peer; /* max number of FTM number per burst the peer support */
++	rtt_reason_t status; /* raging status */
++	/* in s, 11mc only, only for RTT_REASON_FAIL_BUSY_TRY_LATER, 1- 31s */
++	uint8 retry_after_duration;
++	rtt_type_t type; /* rtt type */
++	wifi_rssi  rssi; /* average rssi in 0.5 dB steps e.g. 143 implies -71.5 dB */
++	wifi_rssi  rssi_spread; /* rssi spread in 0.5 db steps e.g. 5 implies 2.5 spread */
++	/*
++	* 1-sided RTT: TX rate of RTT frame.
++	* 2-sided RTT: TX rate of initiator's Ack in response to FTM frame.
++	*/
++	wifi_rate_t tx_rate;
++	/*
++	* 1-sided RTT: TX rate of Ack from other side.
++	* 2-sided RTT: TX rate of FTM frame coming from responder.
++	*/
++	wifi_rate_t rx_rate;
++	wifi_timespan rtt;	/*  round trip time in 0.1 nanoseconds */
++	wifi_timespan rtt_sd;	/* rtt standard deviation in 0.1 nanoseconds */
++	wifi_timespan rtt_spread; /* difference between max and min rtt times recorded */
++	int distance; /* distance in cm (optional) */
++	int distance_sd; /* standard deviation in cm (optional) */
++	int distance_spread; /* difference between max and min distance recorded (optional) */
++	wifi_timestamp ts; /* time of the measurement (in microseconds since boot) */
++	int burst_duration; /* in ms, how long the FW time is to fininish one burst measurement */
++	int negotiated_burst_num; /* Number of bursts allowed by the responder */
++	bcm_tlv_t *LCI; /* LCI Report */
++	bcm_tlv_t *LCR; /* Location Civic Report */
++} rtt_report_t;
++
++#define RTT_REPORT_SIZE (sizeof(rtt_report_t))
++
++/* rtt_results_header to maintain rtt result list per mac address */
++typedef struct rtt_results_header {
++	struct ether_addr peer_mac;
++	uint32 result_cnt;
++	uint32 result_tot_len; /* sum of report_len of rtt_result */
++	struct list_head list;
++	struct list_head result_list;
++} rtt_results_header_t;
++
++/* rtt_result to link all of rtt_report */
++typedef struct rtt_result {
++	struct list_head list;
++	struct rtt_report report;
++	int32 report_len; /* total length of rtt_report */
++} rtt_result_t;
++
++/* RTT Capabilities */
++typedef struct rtt_capabilities {
++	uint8 rtt_one_sided_supported;  /* if 1-sided rtt data collection is supported */
++	uint8 rtt_ftm_supported;        /* if ftm rtt data collection is supported */
++	uint8 lci_support;		/* location configuration information */
++	uint8 lcr_support;		/* Civic Location */
++	uint8 preamble_support;         /* bit mask indicate what preamble is supported */
++	uint8 bw_support;               /* bit mask indicate what BW is supported */
++} rtt_capabilities_t;
++
++typedef struct rtt_config_params {
++	int8 rtt_target_cnt;
++	rtt_target_info_t *target_info;
++} rtt_config_params_t;
++
++typedef void (*dhd_rtt_compl_noti_fn)(void *ctx, void *rtt_data);
++
++#ifdef RTT_SUPPORT
++/* Linux wrapper to call common dhd_rtt_set_cfg */
++int
++dhd_dev_rtt_set_cfg(struct net_device *dev, void *buf);
++
++int
++dhd_dev_rtt_cancel_cfg(struct net_device *dev, struct ether_addr *mac_list, int mac_cnt);
++
++int
++dhd_dev_rtt_register_noti_callback(struct net_device *dev, void *ctx,
++	dhd_rtt_compl_noti_fn noti_fn);
++
++int
++dhd_dev_rtt_unregister_noti_callback(struct net_device *dev, dhd_rtt_compl_noti_fn noti_fn);
++
++int
++dhd_dev_rtt_capability(struct net_device *dev, rtt_capabilities_t *capa);
++
++/* export to upper layer */
++chanspec_t
++dhd_rtt_convert_to_chspec(wifi_channel_info_t channel);
++
++int
++dhd_rtt_idx_to_burst_duration(uint idx);
++
++int
++dhd_rtt_set_cfg(dhd_pub_t *dhd, rtt_config_params_t *params);
++
++int
++dhd_rtt_stop(dhd_pub_t *dhd, struct ether_addr *mac_list, int mac_cnt);
++
++
++int
++dhd_rtt_register_noti_callback(dhd_pub_t *dhd, void *ctx, dhd_rtt_compl_noti_fn noti_fn);
++
++int
++dhd_rtt_unregister_noti_callback(dhd_pub_t *dhd, dhd_rtt_compl_noti_fn noti_fn);
++
++int
++dhd_rtt_event_handler(dhd_pub_t *dhd, wl_event_msg_t *event, void *event_data);
++
++int
++dhd_rtt_capability(dhd_pub_t *dhd, rtt_capabilities_t *capa);
++
++int
++dhd_rtt_init(dhd_pub_t *dhd);
++
++int
++dhd_rtt_deinit(dhd_pub_t *dhd);
++#endif /* RTT_SUPPORT */
++#endif /* __DHD_RTT_H__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_sdio.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_sdio.c
+new file mode 100644
+index 000000000..7d1cc0842
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_sdio.c
+@@ -0,0 +1,8736 @@
++/*
++ * DHD Bus Module for SDIO
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_sdio.c 712404 2019-03-20 06:20:25Z $
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++#include <bcmsdh.h>
++
++#ifdef BCMEMBEDIMAGE
++#include BCMEMBEDIMAGE
++#endif /* BCMEMBEDIMAGE */
++
++#include <bcmdefs.h>
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <bcmdevs.h>
++
++#include <siutils.h>
++#include <hndpmu.h>
++#include <hndsoc.h>
++#include <bcmsdpcm.h>
++#include <hnd_armtrap.h>
++#include <hnd_cons.h>
++#include <sbchipc.h>
++#include <sbhnddma.h>
++
++#include <sdio.h>
++#include <sbsdio.h>
++#include <sbsdpcmdev.h>
++#include <bcmsdpcm.h>
++#include <bcmsdbus.h>
++
++#include <proto/ethernet.h>
++#include <proto/802.1d.h>
++#include <proto/802.11.h>
++
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_bus.h>
++#include <dhd_proto.h>
++#include <dhd_dbg.h>
++#include <dhdioctl.h>
++#include <sdiovar.h>
++
++#ifdef LOAD_DHD_WITH_FW_ALIVE
++#include <dhd_chip_info.h>
++#endif
++
++#ifdef PROP_TXSTATUS
++#include <dhd_wlfc.h>
++#endif
++#ifdef DHDTCPACK_SUPPRESS
++#include <dhd_ip.h>
++#endif /* DHDTCPACK_SUPPRESS */
++
++bool dhd_mp_halting(dhd_pub_t *dhdp);
++extern void bcmsdh_waitfor_iodrain(void *sdh);
++extern void bcmsdh_reject_ioreqs(void *sdh, bool reject);
++extern bool  bcmsdh_fatal_error(void *sdh);
++
++#ifndef DHDSDIO_MEM_DUMP_FNAME
++#define DHDSDIO_MEM_DUMP_FNAME         "mem_dump"
++#endif
++
++#define QLEN		(1024) /* bulk rx and tx queue lengths */
++#define FCHI		(QLEN - 10)
++#define FCLOW		(FCHI / 2)
++#define PRIOMASK	7
++
++#define TXRETRIES	2	/* # of retries for tx frames */
++#define READ_FRM_CNT_RETRIES	3
++#ifndef DHD_RXBOUND
++#define DHD_RXBOUND	50	/* Default for max rx frames in one scheduling */
++#endif
++
++#ifndef DHD_TXBOUND
++#define DHD_TXBOUND	20	/* Default for max tx frames in one scheduling */
++#endif
++
++#define DHD_TXMINMAX	DHD_TXBOUND	/* Max tx frames if rx still pending */
++
++#define MEMBLOCK	2048		/* Block size used for downloading of dongle image */
++#define MAX_MEMBLOCK  (32 * 1024)	/* Block size used for downloading of dongle image */
++
++#define MAX_DATA_BUF	(64 * 1024)	/* Must be large enough to hold biggest possible glom */
++
++#ifndef DHD_FIRSTREAD
++#define DHD_FIRSTREAD   32
++#endif
++#if !ISPOWEROF2(DHD_FIRSTREAD)
++#error DHD_FIRSTREAD is not a power of 2!
++#endif
++
++/* Total length of frame header for dongle protocol */
++#define SDPCM_HDRLEN	(SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
++#define SDPCM_HDRLEN_TXGLOM	(SDPCM_HDRLEN + SDPCM_HWEXT_LEN)
++#define MAX_TX_PKTCHAIN_CNT	SDPCM_MAXGLOM_SIZE
++
++#ifdef SDTEST
++#define SDPCM_RESERVE	(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
++#else
++#define SDPCM_RESERVE	(SDPCM_HDRLEN + DHD_SDALIGN)
++#endif
++
++/* Space for header read, limit for data packets */
++#ifndef MAX_HDR_READ
++#define MAX_HDR_READ	32
++#endif
++#if !ISPOWEROF2(MAX_HDR_READ)
++#error MAX_HDR_READ is not a power of 2!
++#endif
++
++#define MAX_RX_DATASZ	2048
++
++/* Maximum milliseconds to wait for F2 to come up */
++#define DHD_WAIT_F2RDY	3000
++
++/* Bump up limit on waiting for HT to account for first startup;
++ * if the image is doing a CRC calculation before programming the PMU
++ * for HT availability, it could take a couple hundred ms more, so
++ * max out at a 1 second (1000000us).
++ */
++#if (PMU_MAX_TRANSITION_DLY <= 1000000)
++#undef PMU_MAX_TRANSITION_DLY
++#define PMU_MAX_TRANSITION_DLY 1000000
++#endif
++
++/* hooks for limiting threshold custom tx num in rx processing */
++#define DEFAULT_TXINRX_THRES    0
++#ifndef CUSTOM_TXINRX_THRES
++#define CUSTOM_TXINRX_THRES     DEFAULT_TXINRX_THRES
++#endif
++
++/* Value for ChipClockCSR during initial setup */
++#define DHD_INIT_CLKCTL1	(SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ)
++#define DHD_INIT_CLKCTL2	(SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
++
++/* Flags for SDH calls */
++#define F2SYNC	(SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
++
++/* Packet free applicable unconditionally for sdio and sdspi.  Conditional if
++ * bufpool was present for gspi bus.
++ */
++#define PKTFREE2()		if ((bus->bus != SPI_BUS) || bus->usebufpool) \
++					PKTFREE(bus->dhd->osh, pkt, FALSE);
++DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
++
++
++/* Device console log buffer state */
++#define CONSOLE_LINE_MAX	192
++#define CONSOLE_BUFFER_MAX	2024
++typedef struct dhd_console {
++	uint		count;			/* Poll interval msec counter */
++	uint		log_addr;		/* Log struct address (fixed) */
++	hnd_log_t	log;			/* Log struct (host copy) */
++	uint		bufsize;		/* Size of log buffer */
++	uint8		*buf;			/* Log buffer (host copy) */
++	uint		last;			/* Last buffer read index */
++} dhd_console_t;
++
++#define	REMAP_ENAB(bus)			((bus)->remap)
++#define	REMAP_ISADDR(bus, a)		(((a) >= ((bus)->orig_ramsize)) && ((a) < ((bus)->ramsize)))
++#define	KSO_ENAB(bus)			((bus)->kso)
++#define	SR_ENAB(bus)			((bus)->_srenab)
++#define	SLPAUTO_ENAB(bus)		((SR_ENAB(bus)) && ((bus)->_slpauto))
++
++#define	MIN_RSRC_SR			0x3
++#define	CORE_CAPEXT_ADDR_OFFSET		(0x64c)
++#define	CORE_CAPEXT_SR_SUPPORTED_MASK	(1 << 1)
++#define RCTL_MACPHY_DISABLE_MASK	(1 << 26)
++#define RCTL_LOGIC_DISABLE_MASK		(1 << 27)
++
++#define	OOB_WAKEUP_ENAB(bus)		((bus)->_oobwakeup)
++#define	GPIO_DEV_SRSTATE		16	/* Host gpio17 mapped to device gpio0 SR state */
++#define	GPIO_DEV_SRSTATE_TIMEOUT	320000	/* 320ms */
++#define	GPIO_DEV_WAKEUP			17	/* Host gpio17 mapped to device gpio1 wakeup */
++#define	CC_CHIPCTRL2_GPIO1_WAKEUP	(1  << 0)
++#define	CC_CHIPCTRL3_SR_ENG_ENABLE	(1  << 2)
++#define OVERFLOW_BLKSZ512_WM		96
++#define OVERFLOW_BLKSZ512_MES		80
++
++#define CC_PMUCC3	(0x3)
++/* Private data for SDIO bus interaction */
++typedef struct dhd_bus {
++	dhd_pub_t	*dhd;
++
++	bcmsdh_info_t	*sdh;			/* Handle for BCMSDH calls */
++	si_t		*sih;			/* Handle for SI calls */
++	char		*vars;			/* Variables (from CIS and/or other) */
++	uint		varsz;			/* Size of variables buffer */
++	uint32		sbaddr;			/* Current SB window pointer (-1, invalid) */
++
++	sdpcmd_regs_t	*regs;			/* Registers for SDIO core */
++	uint		sdpcmrev;		/* SDIO core revision */
++	uint		armrev;			/* CPU core revision */
++	uint		ramrev;			/* SOCRAM core revision */
++	uint32		ramsize;		/* Size of RAM in SOCRAM (bytes) */
++	uint32		orig_ramsize;		/* Size of RAM in SOCRAM (bytes) */
++	uint32		srmemsize;		/* Size of SRMEM */
++
++	uint32		bus;			/* gSPI or SDIO bus */
++	uint32		bus_num;		/* bus number */
++	uint32		slot_num;		/* slot ID */
++	uint32		hostintmask;	/* Copy of Host Interrupt Mask */
++	uint32		intstatus;		/* Intstatus bits (events) pending */
++	bool		dpc_sched;		/* Indicates DPC schedule (intrpt rcvd) */
++	bool		fcstate;		/* State of dongle flow-control */
++
++	uint16		cl_devid;		/* cached devid for dhdsdio_probe_attach() */
++	char		*fw_path;		/* module_param: path to firmware image */
++	char		*nv_path;		/* module_param: path to nvram vars file */
++
++	uint		blocksize;		/* Block size of SDIO transfers */
++	uint		roundup;		/* Max roundup limit */
++
++	struct pktq	txq;			/* Queue length used for flow-control */
++	uint8		flowcontrol;		/* per prio flow control bitmask */
++	uint8		tx_seq;			/* Transmit sequence number (next) */
++	uint8		tx_max;			/* Maximum transmit sequence allowed */
++
++	uint8		hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
++	uint8		*rxhdr;			/* Header of current rx frame (in hdrbuf) */
++	uint16		nextlen;		/* Next Read Len from last header */
++	uint8		rx_seq;			/* Receive sequence number (expected) */
++	bool		rxskip;			/* Skip receive (awaiting NAK ACK) */
++
++	void		*glomd;			/* Packet containing glomming descriptor */
++	void		*glom;			/* Packet chain for glommed superframe */
++	uint		glomerr;		/* Glom packet read errors */
++
++	uint8		*rxbuf;			/* Buffer for receiving control packets */
++	uint		rxblen;			/* Allocated length of rxbuf */
++	uint8		*rxctl;			/* Aligned pointer into rxbuf */
++	uint8		*databuf;		/* Buffer for receiving big glom packet */
++	uint8		*dataptr;		/* Aligned pointer into databuf */
++	uint		rxlen;			/* Length of valid data in buffer */
++
++	uint8		sdpcm_ver;		/* Bus protocol reported by dongle */
++
++	bool		intr;			/* Use interrupts */
++	bool		poll;			/* Use polling */
++	bool		ipend;			/* Device interrupt is pending */
++	bool		intdis;			/* Interrupts disabled by isr */
++	uint 		intrcount;		/* Count of device interrupt callbacks */
++	uint		lastintrs;		/* Count as of last watchdog timer */
++	uint		spurious;		/* Count of spurious interrupts */
++	uint		pollrate;		/* Ticks between device polls */
++	uint		polltick;		/* Tick counter */
++	uint		pollcnt;		/* Count of active polls */
++
++#ifdef DHD_DEBUG
++	dhd_console_t	console;		/* Console output polling support */
++	uint		console_addr;		/* Console address from shared struct */
++#endif /* DHD_DEBUG */
++
++	uint		regfails;		/* Count of R_REG/W_REG failures */
++
++	uint		clkstate;		/* State of sd and backplane clock(s) */
++	bool		activity;		/* Activity flag for clock down */
++	int32		idletime;		/* Control for activity timeout */
++	int32		idlecount;		/* Activity timeout counter */
++	int32		idleclock;		/* How to set bus driver when idle */
++	int32		sd_divisor;		/* Speed control to bus driver */
++	int32		sd_mode;		/* Mode control to bus driver */
++	int32		sd_rxchain;		/* If bcmsdh api accepts PKT chains */
++	bool		use_rxchain;		/* If dhd should use PKT chains */
++	bool		sleeping;		/* Is SDIO bus sleeping? */
++#if (defined(SUPPORT_P2P_GO_PS) || defined(SUSPEND16))
++	wait_queue_head_t bus_sleep;
++#endif /* LINUX && SUPPORT_P2P_GO_PS */
++	uint		rxflow_mode;		/* Rx flow control mode */
++	bool		rxflow;			/* Is rx flow control on */
++	uint		prev_rxlim_hit;		/* Is prev rx limit exceeded (per dpc schedule) */
++	bool		alp_only;		/* Don't use HT clock (ALP only) */
++	/* Field to decide if rx of control frames happen in rxbuf or lb-pool */
++	bool		usebufpool;
++	int32		txinrx_thres;	/* num of in-queued pkts */
++	int32		dotxinrx;	/* tx first in dhdsdio_readframes */
++#ifdef SDTEST
++	/* external loopback */
++	bool		ext_loop;
++	uint8		loopid;
++
++	/* pktgen configuration */
++	uint		pktgen_freq;		/* Ticks between bursts */
++	uint		pktgen_count;		/* Packets to send each burst */
++	uint		pktgen_print;		/* Bursts between count displays */
++	uint		pktgen_total;		/* Stop after this many */
++	uint		pktgen_minlen;		/* Minimum packet data len */
++	uint		pktgen_maxlen;		/* Maximum packet data len */
++	uint		pktgen_mode;		/* Configured mode: tx, rx, or echo */
++	uint		pktgen_stop;		/* Number of tx failures causing stop */
++
++	/* active pktgen fields */
++	uint		pktgen_tick;		/* Tick counter for bursts */
++	uint		pktgen_ptick;		/* Burst counter for printing */
++	uint		pktgen_sent;		/* Number of test packets generated */
++	uint		pktgen_rcvd;		/* Number of test packets received */
++	uint		pktgen_prev_time;	/* Time at which previous stats where printed */
++	uint		pktgen_prev_sent;	/* Number of test packets generated when
++						 * previous stats were printed
++						 */
++	uint		pktgen_prev_rcvd;	/* Number of test packets received when
++						 * previous stats were printed
++						 */
++	uint		pktgen_fail;		/* Number of failed send attempts */
++	uint16		pktgen_len;		/* Length of next packet to send */
++#define PKTGEN_RCV_IDLE     (0)
++#define PKTGEN_RCV_ONGOING  (1)
++	uint16		pktgen_rcv_state;		/* receive state */
++	uint		pktgen_rcvd_rcvsession;	/* test pkts rcvd per rcv session. */
++#endif /* SDTEST */
++
++	/* Some additional counters */
++	uint		tx_sderrs;		/* Count of tx attempts with sd errors */
++	uint		fcqueued;		/* Tx packets that got queued */
++	uint		rxrtx;			/* Count of rtx requests (NAK to dongle) */
++	uint		rx_toolong;		/* Receive frames too long to receive */
++	uint		rxc_errors;		/* SDIO errors when reading control frames */
++	uint		rx_hdrfail;		/* SDIO errors on header reads */
++	uint		rx_badhdr;		/* Bad received headers (roosync?) */
++	uint		rx_badseq;		/* Mismatched rx sequence number */
++	uint		fc_rcvd;		/* Number of flow-control events received */
++	uint		fc_xoff;		/* Number which turned on flow-control */
++	uint		fc_xon;			/* Number which turned off flow-control */
++	uint		rxglomfail;		/* Failed deglom attempts */
++	uint		rxglomframes;		/* Number of glom frames (superframes) */
++	uint		rxglompkts;		/* Number of packets from glom frames */
++	uint		f2rxhdrs;		/* Number of header reads */
++	uint		f2rxdata;		/* Number of frame data reads */
++	uint		f2txdata;		/* Number of f2 frame writes */
++	uint		f1regdata;		/* Number of f1 register accesses */
++#ifdef DHDENABLE_TAILPAD
++	uint		tx_tailpad_chain;	/* Number of tail padding by chaining pad_pkt */
++	uint		tx_tailpad_pktget;	/* Number of tail padding by new PKTGET */
++#endif /* DHDENABLE_TAILPAD */
++	uint8		*ctrl_frame_buf;
++	uint32		ctrl_frame_len;
++	bool		ctrl_frame_stat;
++	uint32		rxint_mode;	/* rx interrupt mode */
++	bool		remap;		/* Contiguous 1MB RAM: 512K socram + 512K devram
++					 * Available with socram rev 16
++					 * Remap region not DMA-able
++					 */
++	bool		kso;
++	bool		_slpauto;
++	bool		_oobwakeup;
++	bool		_srenab;
++	bool        readframes;
++	bool        reqbussleep;
++	uint32		resetinstr;
++	uint32		dongle_ram_base;
++
++	void		*glom_pkt_arr[SDPCM_MAXGLOM_SIZE];	/* Array of pkts for glomming */
++	uint32		txglom_cnt;	/* Number of pkts in the glom array */
++	uint32		txglom_total_len;	/* Total length of pkts in glom array */
++	bool		txglom_enable;	/* Flag to indicate whether tx glom is enabled/disabled */
++	uint32		txglomsize;	/* Glom size limitation */
++#ifdef DHDENABLE_TAILPAD
++	void		*pad_pkt;
++#endif /* DHDENABLE_TAILPAD */
++} dhd_bus_t;
++
++/* clkstate */
++#define CLK_NONE	0
++#define CLK_SDONLY	1
++#define CLK_PENDING	2	/* Not used yet */
++#define CLK_AVAIL	3
++
++#define DHD_NOPMU(dhd)	(FALSE)
++
++#if defined(BCMSDIOH_STD)
++#define BLK_64_MAXTXGLOM 20
++#endif /* BCMSDIOH_STD */
++
++#ifdef DHD_DEBUG
++static int qcount[NUMPRIO];
++static int tx_packets[NUMPRIO];
++#endif /* DHD_DEBUG */
++
++/* Deferred transmit */
++const uint dhd_deferred_tx = 1;
++
++extern uint dhd_watchdog_ms;
++extern uint sd_f1_blocksize;
++
++
++extern void dhd_os_wd_timer(void *bus, uint wdtick);
++int dhd_enableOOB(dhd_pub_t *dhd, bool sleep);
++
++/* Tx/Rx bounds */
++uint dhd_txbound;
++uint dhd_rxbound;
++uint dhd_txminmax = DHD_TXMINMAX;
++
++/* override the RAM size if possible */
++#define DONGLE_MIN_RAMSIZE (128 *1024)
++int dhd_dongle_ramsize;
++
++uint dhd_doflow = TRUE;
++uint dhd_dpcpoll = FALSE;
++
++module_param(dhd_doflow, uint, 0644);
++module_param(dhd_dpcpoll, uint, 0644);
++
++static bool dhd_alignctl;
++
++static bool sd1idle;
++
++static bool retrydata;
++#define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
++
++static uint watermark = 8;
++static uint mesbusyctrl = 0;
++static const uint firstread = DHD_FIRSTREAD;
++
++/* Retry count for register access failures */
++static const uint retry_limit = 2;
++
++/* Force even SD lengths (some host controllers mess up on odd bytes) */
++static bool forcealign;
++
++#define ALIGNMENT  4
++
++#if defined(OOB_INTR_ONLY) && defined(HW_OOB)
++extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
++#endif
++
++#if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
++#error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
++#endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
++#define PKTALIGN(osh, p, len, align)					\
++	do {								\
++		uintptr datalign;						\
++		datalign = (uintptr)PKTDATA((osh), (p));		\
++		datalign = ROUNDUP(datalign, (align)) - datalign;	\
++		ASSERT(datalign < (align));				\
++		ASSERT(PKTLEN((osh), (p)) >= ((len) + datalign));	\
++		if (datalign)						\
++			PKTPULL((osh), (p), (uint)datalign);			\
++		PKTSETLEN((osh), (p), (len));				\
++	} while (0)
++
++/* Limit on rounding up frames */
++static const uint max_roundup = 512;
++
++/* Try doing readahead */
++static bool dhd_readahead;
++
++/* To check if there's window offered */
++#define DATAOK(bus) \
++	(((uint8)(bus->tx_max - bus->tx_seq) > 1) && \
++	(((uint8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
++
++/* To check if there's window offered for ctrl frame */
++#define TXCTLOK(bus) \
++	(((uint8)(bus->tx_max - bus->tx_seq) != 0) && \
++	(((uint8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
++
++/* Number of pkts available in dongle for data RX */
++#define DATABUFCNT(bus) \
++	((uint8)(bus->tx_max - bus->tx_seq) - 1)
++
++/* Macros to get register read/write status */
++/* NOTE: these assume a local dhdsdio_bus_t *bus! */
++#define R_SDREG(regvar, regaddr, retryvar) \
++do { \
++	retryvar = 0; \
++	do { \
++		regvar = R_REG(bus->dhd->osh, regaddr); \
++	} while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
++	if (retryvar) { \
++		bus->regfails += (retryvar-1); \
++		if (retryvar > retry_limit) { \
++			DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
++			           __FUNCTION__, __LINE__)); \
++			regvar = 0; \
++		} \
++	} \
++} while (0)
++
++#define W_SDREG(regval, regaddr, retryvar) \
++do { \
++	retryvar = 0; \
++	do { \
++		W_REG(bus->dhd->osh, regaddr, regval); \
++	} while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
++	if (retryvar) { \
++		bus->regfails += (retryvar-1); \
++		if (retryvar > retry_limit) \
++			DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
++			           __FUNCTION__, __LINE__)); \
++	} \
++} while (0)
++
++#define BUS_WAKE(bus) \
++	do { \
++		bus->idlecount = 0; \
++		if ((bus)->sleeping) \
++			dhdsdio_bussleep((bus), FALSE); \
++	} while (0);
++
++/*
++ * pktavail interrupts from dongle to host can be managed in 3 different ways
++ * whenever there is a packet available in dongle to transmit to host.
++ *
++ * Mode 0:	Dongle writes the software host mailbox and host is interrupted.
++ * Mode 1:	(sdiod core rev >= 4)
++ *		Device sets a new bit in the intstatus whenever there is a packet
++ *		available in fifo.  Host can't clear this specific status bit until all the
++ *		packets are read from the FIFO.  No need to ack dongle intstatus.
++ * Mode 2:	(sdiod core rev >= 4)
++ *		Device sets a bit in the intstatus, and host acks this by writing
++ *		one to this bit.  Dongle won't generate anymore packet interrupts
++ *		until host reads all the packets from the dongle and reads a zero to
++ *		figure that there are no more packets.  No need to disable host ints.
++ *		Need to ack the intstatus.
++ */
++
++#define SDIO_DEVICE_HMB_RXINT		0	/* default old way */
++#define SDIO_DEVICE_RXDATAINT_MODE_0	1	/* from sdiod rev 4 */
++#define SDIO_DEVICE_RXDATAINT_MODE_1	2	/* from sdiod rev 4 */
++
++
++#define FRAME_AVAIL_MASK(bus) 	\
++	((bus->rxint_mode == SDIO_DEVICE_HMB_RXINT) ? I_HMB_FRAME_IND : I_XMTDATA_AVAIL)
++
++#define DHD_BUS			SDIO_BUS
++
++#define PKT_AVAILABLE(bus, intstatus)	((intstatus) & (FRAME_AVAIL_MASK(bus)))
++
++#define HOSTINTMASK		(I_HMB_SW_MASK | I_CHIPACTIVE)
++
++#define GSPI_PR55150_BAILOUT
++
++#ifdef SDTEST
++static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
++static void dhdsdio_sdtest_set(dhd_bus_t *bus, uint count);
++#endif
++
++static int dhdsdio_checkdied(dhd_bus_t *bus, char *data, uint size);
++#ifdef DHD_DEBUG
++static int dhd_serialconsole(dhd_bus_t *bus, bool get, bool enable, int *bcmerror);
++#endif /* DHD_DEBUG */
++
++#if defined(DHD_FW_COREDUMP)
++static int dhdsdio_mem_dump(dhd_bus_t *bus);
++#endif /* DHD_FW_COREDUMP */
++static int dhdsdio_devcap_set(dhd_bus_t *bus, uint8 cap);
++static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
++
++static void dhdsdio_release(dhd_bus_t *bus, osl_t *osh);
++static void dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh);
++static void dhdsdio_disconnect(void *ptr);
++static bool dhdsdio_chipmatch(uint16 chipid);
++static bool dhdsdio_probe_attach(dhd_bus_t *bus, osl_t *osh, void *sdh,
++                                 void * regsva, uint16  devid);
++static bool dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh);
++static bool dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh);
++static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t *osh, bool dongle_isolation,
++	bool reset_flag);
++
++static void dhd_dongle_setramsize(struct dhd_bus *bus, int mem_size);
++static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags,
++	uint8 *buf, uint nbytes,
++	void *pkt, bcmsdh_cmplt_fn_t complete, void *handle);
++static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags,
++	uint8 *buf, uint nbytes,
++	void *pkt, bcmsdh_cmplt_fn_t complete, void *handle, int max_retry);
++static int dhdsdio_txpkt(dhd_bus_t *bus, uint chan, void** pkts, int num_pkt, bool free_pkt);
++static int dhdsdio_txpkt_preprocess(dhd_bus_t *bus, void *pkt, int chan, int txseq,
++	int prev_chain_total_len, bool last_chained_pkt,
++	int *pad_pkt_len, void **new_pkt);
++static int dhdsdio_txpkt_postprocess(dhd_bus_t *bus, void *pkt);
++
++static int dhdsdio_download_firmware(dhd_bus_t *bus, osl_t *osh, void *sdh);
++static int _dhdsdio_download_firmware(dhd_bus_t *bus);
++
++static int dhdsdio_download_code_file(dhd_bus_t *bus, char *image_path);
++static int dhdsdio_download_nvram(dhd_bus_t *bus);
++#ifdef BCMEMBEDIMAGE
++static int dhdsdio_download_code_array(dhd_bus_t *bus);
++#endif
++static int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep);
++static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok);
++static uint8 dhdsdio_sleepcsr_get(dhd_bus_t *bus);
++static bool dhdsdio_dpc(dhd_bus_t *bus);
++
++#ifdef WLMEDIA_HTSF
++#include <htsf.h>
++extern uint32 dhd_get_htsf(void *dhd, int ifidx);
++#endif /* WLMEDIA_HTSF */
++
++int dhd_bcmsdh_send_buffer(void *bus, uint8 *frame, uint16 len);
++#ifdef DHD_ULP
++#include <dhd_ulp.h>
++static int dhd_bus_ulp_reinit_fw(dhd_bus_t *bus);
++#endif /* DHD_ULP */
++
++static void
++dhdsdio_tune_fifoparam(struct dhd_bus *bus)
++{
++	int err;
++	uint8 devctl, wm, mes;
++
++	if (bus->sih->buscorerev >= 15) {
++		/* See .ppt in PR for these recommended values */
++		if (bus->blocksize == 512) {
++			wm = OVERFLOW_BLKSZ512_WM;
++			mes = OVERFLOW_BLKSZ512_MES;
++		} else {
++			mes = bus->blocksize/4;
++			wm = bus->blocksize/4;
++		}
++
++		watermark = wm;
++		mesbusyctrl = mes;
++	} else {
++		DHD_INFO(("skip fifotune: SdioRev(%d) is lower than minimal requested ver\n",
++			bus->sih->buscorerev));
++		return;
++	}
++
++	/* Update watermark */
++	if (wm > 0) {
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK, wm, &err);
++
++		devctl = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
++		devctl |= SBSDIO_DEVCTL_F2WM_ENAB;
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
++	}
++
++	/* Update MES */
++	if (mes > 0) {
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_MESBUSYCTRL,
++			(mes | SBSDIO_MESBUSYCTRL_ENAB), &err);
++	}
++
++	DHD_INFO(("Apply overflow WAR: 0x%02x 0x%02x 0x%02x\n",
++		bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err),
++		bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK, &err),
++		bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_MESBUSYCTRL, &err)));
++}
++
++static void
++dhd_dongle_setramsize(struct dhd_bus *bus, int mem_size)
++{
++	int32 min_size =  DONGLE_MIN_RAMSIZE;
++	/* Restrict the ramsize to user specified limit */
++	DHD_ERROR(("user: Restrict the dongle ram size to %d, min accepted %d\n",
++		dhd_dongle_ramsize, min_size));
++	if ((dhd_dongle_ramsize > min_size) &&
++		(dhd_dongle_ramsize < (int32)bus->orig_ramsize))
++		bus->ramsize = dhd_dongle_ramsize;
++}
++
++static int
++dhdsdio_set_siaddr_window(dhd_bus_t *bus, uint32 address)
++{
++	int err = 0;
++	bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
++	                 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
++	if (!err)
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
++		                 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
++	if (!err)
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
++		                 (address >> 24) & SBSDIO_SBADDRHIGH_MASK, &err);
++	return err;
++}
++
++
++#ifdef USE_OOB_GPIO1
++static int
++dhdsdio_oobwakeup_init(dhd_bus_t *bus)
++{
++	uint32 val, addr, data;
++
++	bcmsdh_gpioouten(bus->sdh, GPIO_DEV_WAKEUP);
++
++	addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_addr);
++	data = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_data);
++
++	/* Set device for gpio1 wakeup */
++	bcmsdh_reg_write(bus->sdh, addr, 4, 2);
++	val = bcmsdh_reg_read(bus->sdh, data, 4);
++	val |= CC_CHIPCTRL2_GPIO1_WAKEUP;
++	bcmsdh_reg_write(bus->sdh, data, 4, val);
++
++	bus->_oobwakeup = TRUE;
++
++	return 0;
++}
++#endif /* USE_OOB_GPIO1 */
++
++/*
++ * Query if FW is in SR mode
++ */
++static bool
++dhdsdio_sr_cap(dhd_bus_t *bus)
++{
++	bool cap = FALSE;
++	uint32  core_capext, addr, data;
++
++	if (bus->sih->chip == BCM43430_CHIP_ID ||
++		bus->sih->chip == BCM43018_CHIP_ID) {
++		/* check if fw initialized sr engine */
++		addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, sr_control1);
++		if (bcmsdh_reg_read(bus->sdh, addr, 4) != 0)
++			cap = TRUE;
++
++		return cap;
++	}
++	if (bus->sih->chip == BCM4324_CHIP_ID) {
++			addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_addr);
++			data = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_data);
++			bcmsdh_reg_write(bus->sdh, addr, 4, 3);
++			core_capext = bcmsdh_reg_read(bus->sdh, data, 4);
++	} else if (bus->sih->chip == BCM4330_CHIP_ID) {
++			core_capext = FALSE;
++	} else if ((bus->sih->chip == BCM4335_CHIP_ID) ||
++		(bus->sih->chip == BCM4339_CHIP_ID) ||
++		(bus->sih->chip == BCM43349_CHIP_ID) ||
++		(bus->sih->chip == BCM4345_CHIP_ID) ||
++		(bus->sih->chip == BCM43454_CHIP_ID) ||
++		(bus->sih->chip == BCM4354_CHIP_ID) ||
++		(bus->sih->chip == BCM4356_CHIP_ID) ||
++		(bus->sih->chip == BCM4358_CHIP_ID) ||
++		(BCM4349_CHIP(bus->sih->chip))		||
++		(bus->sih->chip == BCM4350_CHIP_ID) ||
++		(bus->sih->chip == BCM43012_CHIP_ID)) {
++		core_capext = TRUE;
++	} else {
++			core_capext = bcmsdh_reg_read(bus->sdh,
++				si_get_pmu_reg_addr(bus->sih, OFFSETOF(chipcregs_t, core_cap_ext)),
++				4);
++			core_capext = (core_capext & CORE_CAPEXT_SR_SUPPORTED_MASK);
++	}
++	if (!(core_capext))
++		return FALSE;
++
++	if (bus->sih->chip == BCM4324_CHIP_ID) {
++		/* FIX: Should change to query SR control register instead */
++		cap = TRUE;
++	} else if ((bus->sih->chip == BCM4335_CHIP_ID) ||
++		(bus->sih->chip == BCM4339_CHIP_ID) ||
++		(bus->sih->chip == BCM43349_CHIP_ID) ||
++		(bus->sih->chip == BCM4345_CHIP_ID) ||
++		(bus->sih->chip == BCM43454_CHIP_ID) ||
++		(bus->sih->chip == BCM4354_CHIP_ID) ||
++		(bus->sih->chip == BCM4356_CHIP_ID) ||
++		(bus->sih->chip == BCM4358_CHIP_ID) ||
++		(bus->sih->chip == BCM4350_CHIP_ID)) {
++		uint32 enabval = 0;
++		addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_addr);
++		data = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_data);
++		bcmsdh_reg_write(bus->sdh, addr, 4, CC_PMUCC3);
++		enabval = bcmsdh_reg_read(bus->sdh, data, 4);
++
++		if ((bus->sih->chip == BCM4350_CHIP_ID) ||
++			(bus->sih->chip == BCM4345_CHIP_ID) ||
++			(bus->sih->chip == BCM43454_CHIP_ID) ||
++			(bus->sih->chip == BCM4354_CHIP_ID) ||
++			(bus->sih->chip == BCM4356_CHIP_ID) ||
++			(bus->sih->chip == BCM4358_CHIP_ID))
++			enabval &= CC_CHIPCTRL3_SR_ENG_ENABLE;
++
++		if (enabval)
++			cap = TRUE;
++	} else {
++		data = bcmsdh_reg_read(bus->sdh,
++			si_get_pmu_reg_addr(bus->sih, OFFSETOF(chipcregs_t, retention_ctl)),
++			4);
++		if ((data & (RCTL_MACPHY_DISABLE_MASK | RCTL_LOGIC_DISABLE_MASK)) == 0)
++			cap = TRUE;
++	}
++
++	return cap;
++}
++
++static int
++dhdsdio_srwar_init(dhd_bus_t *bus)
++{
++	bcmsdh_gpio_init(bus->sdh);
++
++#ifdef USE_OOB_GPIO1
++	dhdsdio_oobwakeup_init(bus);
++#endif
++
++
++	return 0;
++}
++
++static int
++dhdsdio_sr_init(dhd_bus_t *bus)
++{
++	uint8 val;
++	int err = 0;
++
++	if ((bus->sih->chip == BCM4334_CHIP_ID) && (bus->sih->chiprev == 2))
++		dhdsdio_srwar_init(bus);
++
++
++	if (bus->sih->chip == BCM43012_CHIP_ID) {
++		val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, NULL);
++		val |= 1 << SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT;
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL,
++			1 << SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT, &err);
++		val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, NULL);
++	} else {
++		val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, NULL);
++		val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL,
++			1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT, &err);
++		val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, NULL);
++	}
++
++#ifdef USE_CMD14
++	/* Add CMD14 Support */
++	dhdsdio_devcap_set(bus,
++		(SDIOD_CCCR_BRCM_CARDCAP_CMD14_SUPPORT | SDIOD_CCCR_BRCM_CARDCAP_CMD14_EXT));
++#endif /* USE_CMD14 */
++
++	dhdsdio_devcap_set(bus, SDIOD_CCCR_BRCM_CARDCAP_CMD_NODEC);
++
++	if (bus->sih->chip == BCM43012_CHIP_ID) {
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
++			SBSDIO_FUNC1_CHIPCLKCSR, SBSDIO_HT_AVAIL_REQ, &err);
++	} else {
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
++			SBSDIO_FUNC1_CHIPCLKCSR, SBSDIO_FORCE_HT, &err);
++	}
++	bus->_slpauto = dhd_slpauto ? TRUE : FALSE;
++
++	bus->_srenab = TRUE;
++
++	return 0;
++}
++
++/*
++ * FIX: Be sure KSO bit is enabled
++ * Currently, it's defaulting to 0 which should be 1.
++ */
++static int
++dhdsdio_clk_kso_init(dhd_bus_t *bus)
++{
++	uint8 val;
++	int err = 0;
++
++	/* set flag */
++	bus->kso = TRUE;
++
++	/*
++	 * Enable KeepSdioOn (KSO) bit for normal operation
++	 * Default is 0 (4334A0) so set it. Fixed in B0.
++	 */
++	val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, NULL);
++	if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
++		val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, val, &err);
++		if (err)
++			DHD_ERROR(("%s: SBSDIO_FUNC1_SLEEPCSR err: 0x%x\n", __FUNCTION__, err));
++	}
++
++	return 0;
++}
++
++#define KSO_DBG(x)
++#define KSO_WAIT_US 50
++#define KSO_WAIT_MS 1
++#define KSO_SLEEP_RETRY_COUNT 20
++#define KSO_WAKE_RETRY_COUNT 100
++#define ERROR_BCME_NODEVICE_MAX 1
++
++#define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
++static int
++dhdsdio_clk_kso_enab(dhd_bus_t *bus, bool on)
++{
++	uint8 wr_val = 0, rd_val, cmp_val, bmask;
++	int err = 0;
++	int try_cnt = 0;
++
++	KSO_DBG(("%s> op:%s\n", __FUNCTION__, (on ? "KSO_SET" : "KSO_CLR")));
++
++	wr_val |= (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
++
++	bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err);
++
++
++	/* In case of 43012 chip, the chip could go down immediately after KSO bit is cleared.
++	 * So the further reads of KSO register could fail. Thereby just bailing out immediately
++	 * after clearing KSO bit, to avoid polling of KSO bit.
++	 */
++	if ((!on) && (bus->sih->chip == BCM43012_CHIP_ID)) {
++		return err;
++	}
++
++	if (on) {
++		cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |  SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
++		bmask = cmp_val;
++
++		OSL_SLEEP(3);
++
++	} else {
++		/* Put device to sleep, turn off  KSO  */
++		cmp_val = 0;
++		bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
++	}
++
++	do {
++		rd_val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, &err);
++		if (((rd_val & bmask) == cmp_val) && !err)
++			break;
++
++		KSO_DBG(("%s> KSO wr/rd retry:%d, ERR:%x \n", __FUNCTION__, try_cnt, err));
++
++		if (((try_cnt + 1) % KSO_SLEEP_RETRY_COUNT) == 0) {
++			OSL_SLEEP(KSO_WAIT_MS);
++		} else
++			OSL_DELAY(KSO_WAIT_US);
++
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err);
++	} while (try_cnt++ < MAX_KSO_ATTEMPTS);
++
++
++	if (try_cnt > 2)
++		KSO_DBG(("%s> op:%s, try_cnt:%d, rd_val:%x, ERR:%x \n",
++			__FUNCTION__, (on ? "KSO_SET" : "KSO_CLR"), try_cnt, rd_val, err));
++
++	if (try_cnt > MAX_KSO_ATTEMPTS)  {
++		DHD_ERROR(("%s> op:%s, ERROR: try_cnt:%d, rd_val:%x, ERR:%x \n",
++			__FUNCTION__, (on ? "KSO_SET" : "KSO_CLR"), try_cnt, rd_val, err));
++	}
++
++	return err;
++}
++
++static int
++dhdsdio_clk_kso_iovar(dhd_bus_t *bus, bool on)
++{
++	int err = 0;
++
++	if (on == FALSE) {
++
++		BUS_WAKE(bus);
++		dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++		DHD_ERROR(("%s: KSO disable clk: 0x%x\n", __FUNCTION__,
++			bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
++			SBSDIO_FUNC1_CHIPCLKCSR, &err)));
++		dhdsdio_clk_kso_enab(bus, FALSE);
++	} else {
++		DHD_ERROR(("%s: KSO enable\n", __FUNCTION__));
++
++		/* Make sure we have SD bus access */
++		if (bus->clkstate == CLK_NONE) {
++			DHD_ERROR(("%s: Request SD clk\n", __FUNCTION__));
++			dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++		}
++
++		dhdsdio_clk_kso_enab(bus, TRUE);
++
++		DHD_ERROR(("%s: sleepcsr: 0x%x\n", __FUNCTION__,
++			dhdsdio_sleepcsr_get(bus)));
++	}
++
++	bus->kso = on;
++	BCM_REFERENCE(err);
++
++	return 0;
++}
++
++static uint8
++dhdsdio_sleepcsr_get(dhd_bus_t *bus)
++{
++	int err = 0;
++	uint8 val = 0;
++
++	val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, &err);
++	if (err)
++		DHD_TRACE(("Failed to read SLEEPCSR: %d\n", err));
++
++	return val;
++}
++
++uint8
++dhdsdio_devcap_get(dhd_bus_t *bus)
++{
++	return bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_BRCM_CARDCAP, NULL);
++}
++
++static int
++dhdsdio_devcap_set(dhd_bus_t *bus, uint8 cap)
++{
++	int err = 0;
++
++	bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_BRCM_CARDCAP, cap, &err);
++	if (err)
++		DHD_ERROR(("%s: devcap set err: 0x%x\n", __FUNCTION__, err));
++
++	return 0;
++}
++
++static int
++dhdsdio_clk_devsleep_iovar(dhd_bus_t *bus, bool on)
++{
++	int err = 0, retry;
++	uint8 val;
++
++	retry = 0;
++	if (on == TRUE) {
++		/* Enter Sleep */
++
++		/* Be sure we request clk before going to sleep
++		 * so we can wake-up with clk request already set
++		 * else device can go back to sleep immediately
++		 */
++		if (!SLPAUTO_ENAB(bus))
++			dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++		else {
++			val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
++			if ((val & SBSDIO_CSR_MASK) == 0) {
++				DHD_ERROR(("%s: No clock before enter sleep:0x%x\n",
++					__FUNCTION__, val));
++
++				/* Reset clock request */
++				bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
++					SBSDIO_ALP_AVAIL_REQ, &err);
++				DHD_ERROR(("%s: clock before sleep:0x%x\n", __FUNCTION__,
++					bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
++					SBSDIO_FUNC1_CHIPCLKCSR, &err)));
++			}
++		}
++
++		DHD_TRACE(("%s: clk before sleep: 0x%x\n", __FUNCTION__,
++			bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
++			SBSDIO_FUNC1_CHIPCLKCSR, &err)));
++#ifdef USE_CMD14
++		err = bcmsdh_sleep(bus->sdh, TRUE);
++#else
++
++
++		err = dhdsdio_clk_kso_enab(bus, FALSE);
++		if (OOB_WAKEUP_ENAB(bus))
++		{
++			err = bcmsdh_gpioout(bus->sdh, GPIO_DEV_WAKEUP, FALSE);  /* GPIO_1 is off */
++		}
++#endif /* USE_CMD14 */
++
++		if ((SLPAUTO_ENAB(bus)) && (bus->idleclock != DHD_IDLE_ACTIVE)) {
++			DHD_TRACE(("%s: Turnoff SD clk\n", __FUNCTION__));
++			dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++		}
++	} else {
++		/* Exit Sleep */
++		/* Make sure we have SD bus access */
++		if (bus->clkstate == CLK_NONE) {
++			DHD_TRACE(("%s: Request SD clk\n", __FUNCTION__));
++			dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++		}
++
++		if ((bus->sih->chip == BCM4334_CHIP_ID) && (bus->sih->chiprev == 2)) {
++			SPINWAIT_SLEEP(sdioh_spinwait_sleep,
++				(bcmsdh_gpioin(bus->sdh, GPIO_DEV_SRSTATE) != TRUE),
++				GPIO_DEV_SRSTATE_TIMEOUT);
++
++			if (bcmsdh_gpioin(bus->sdh, GPIO_DEV_SRSTATE) == FALSE) {
++				DHD_ERROR(("ERROR: GPIO_DEV_SRSTATE still low!\n"));
++			}
++		}
++#ifdef USE_CMD14
++		err = bcmsdh_sleep(bus->sdh, FALSE);
++		if (SLPAUTO_ENAB(bus) && (err != 0)) {
++			OSL_DELAY(10000);
++			DHD_TRACE(("%s: Resync device sleep\n", __FUNCTION__));
++
++			/* Toggle sleep to resync with host and device */
++			err = bcmsdh_sleep(bus->sdh, TRUE);
++			OSL_DELAY(10000);
++			err = bcmsdh_sleep(bus->sdh, FALSE);
++
++			if (err) {
++				OSL_DELAY(10000);
++				DHD_ERROR(("%s: CMD14 exit failed again!\n", __FUNCTION__));
++
++				/* Toggle sleep to resync with host and device */
++				err = bcmsdh_sleep(bus->sdh, TRUE);
++				OSL_DELAY(10000);
++				err = bcmsdh_sleep(bus->sdh, FALSE);
++				if (err) {
++					DHD_ERROR(("%s: CMD14 exit failed twice!\n", __FUNCTION__));
++					DHD_ERROR(("%s: FATAL: Device non-response!\n",
++						__FUNCTION__));
++					err = 0;
++				}
++			}
++		}
++#else
++		if (OOB_WAKEUP_ENAB(bus))
++		{
++			err = bcmsdh_gpioout(bus->sdh, GPIO_DEV_WAKEUP, TRUE);  /* GPIO_1 is on */
++		}
++		do {
++			err = dhdsdio_clk_kso_enab(bus, TRUE);
++			if (err)
++				OSL_SLEEP(10);
++		} while ((err != 0) && (++retry < 3));
++
++		if (err != 0) {
++			DHD_ERROR(("ERROR: kso set failed retry: %d\n", retry));
++			err = 0; /* continue anyway */
++		}
++
++
++#endif /* !USE_CMD14 */
++
++		if (err == 0) {
++			uint8 csr;
++
++			/* Wait for device ready during transition to wake-up */
++			SPINWAIT_SLEEP(sdioh_spinwait_sleep,
++				(((csr = dhdsdio_sleepcsr_get(bus)) &
++				SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK) !=
++				(SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK)), (20000));
++
++			DHD_TRACE(("%s: ExitSleep sleepcsr: 0x%x\n", __FUNCTION__, csr));
++
++			if (!(csr & SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK)) {
++				DHD_ERROR(("%s:ERROR: ExitSleep device NOT Ready! 0x%x\n",
++					__FUNCTION__, csr));
++				err = BCME_NODEVICE;
++			}
++
++			SPINWAIT_SLEEP(sdioh_spinwait_sleep,
++				(((csr = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
++				SBSDIO_FUNC1_CHIPCLKCSR, &err)) & SBSDIO_HT_AVAIL) !=
++				(SBSDIO_HT_AVAIL)), (10000));
++
++			DHD_TRACE(("%s: SBSDIO_FUNC1_CHIPCLKCSR : 0x%x\n", __FUNCTION__, csr));
++			if (!err && ((csr & SBSDIO_HT_AVAIL) != SBSDIO_HT_AVAIL)) {
++				DHD_ERROR(("%s:ERROR: device NOT Ready! 0x%x\n",
++					__FUNCTION__, csr));
++				err = BCME_NODEVICE;
++			}
++		}
++	}
++
++	/* Update if successful */
++	if (err == 0)
++		bus->kso = on ? FALSE : TRUE;
++	else {
++		DHD_ERROR(("%s: Sleep request failed: kso:%d on:%d err:%d\n",
++			__FUNCTION__, bus->kso, on, err));
++		if (!on && retry > 2)
++			bus->kso = FALSE;
++	}
++
++	return err;
++}
++
++/* Turn backplane clock on or off */
++static int
++dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
++{
++#define HT_AVAIL_ERROR_MAX 10
++	static int ht_avail_error = 0;
++	int err;
++	uint8 clkctl, clkreq, devctl;
++	bcmsdh_info_t *sdh;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	clkctl = 0;
++	sdh = bus->sdh;
++
++
++	if (!KSO_ENAB(bus))
++		return BCME_OK;
++
++	if (SLPAUTO_ENAB(bus)) {
++		bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
++		return BCME_OK;
++	}
++
++	if (on) {
++		/* Request HT Avail */
++		clkreq = bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
++
++
++
++		bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
++		if (err) {
++			ht_avail_error++;
++			if (ht_avail_error < HT_AVAIL_ERROR_MAX) {
++				DHD_ERROR(("%s: HT Avail request error: %d\n", __FUNCTION__, err));
++			}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++			else if (ht_avail_error == HT_AVAIL_ERROR_MAX) {
++				dhd_os_send_hang_message(bus->dhd);
++			}
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27) */
++			return BCME_ERROR;
++		} else {
++			ht_avail_error = 0;
++		}
++
++
++		/* Check current status */
++		clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
++		if (err) {
++			DHD_ERROR(("%s: HT Avail read error: %d\n", __FUNCTION__, err));
++			return BCME_ERROR;
++		}
++
++#if !defined(OOB_INTR_ONLY)
++		/* Go to pending and await interrupt if appropriate */
++		if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
++			/* Allow only clock-available interrupt */
++			devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
++			if (err) {
++				DHD_ERROR(("%s: Devctl access error setting CA: %d\n",
++				           __FUNCTION__, err));
++				return BCME_ERROR;
++			}
++
++			devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
++			bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
++			DHD_INFO(("CLKCTL: set PENDING\n"));
++			bus->clkstate = CLK_PENDING;
++			return BCME_OK;
++		} else
++#endif /* !defined (OOB_INTR_ONLY) */
++		{
++			if (bus->clkstate == CLK_PENDING) {
++				/* Cancel CA-only interrupt filter */
++				devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
++				devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
++				bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
++			}
++		}
++
++		/* Otherwise, wait here (polling) for HT Avail */
++		if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
++			SPINWAIT_SLEEP(sdioh_spinwait_sleep,
++				((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
++			                                    SBSDIO_FUNC1_CHIPCLKCSR, &err)),
++			          !SBSDIO_CLKAV(clkctl, bus->alp_only)), PMU_MAX_TRANSITION_DLY);
++		}
++		if (err) {
++			DHD_ERROR(("%s: HT Avail request error: %d\n", __FUNCTION__, err));
++			return BCME_ERROR;
++		}
++		if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
++			DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
++			           __FUNCTION__, PMU_MAX_TRANSITION_DLY, clkctl));
++			return BCME_ERROR;
++		}
++
++		/* Mark clock available */
++		bus->clkstate = CLK_AVAIL;
++		DHD_INFO(("CLKCTL: turned ON\n"));
++
++#if defined(DHD_DEBUG)
++		if (bus->alp_only == TRUE) {
++#if !defined(BCMLXSDMMC)
++			if (!SBSDIO_ALPONLY(clkctl)) {
++				DHD_ERROR(("%s: HT Clock, when ALP Only\n", __FUNCTION__));
++			}
++#endif /* !defined(BCMLXSDMMC) */
++		} else {
++			if (SBSDIO_ALPONLY(clkctl)) {
++				DHD_ERROR(("%s: HT Clock should be on.\n", __FUNCTION__));
++			}
++		}
++#endif /* defined (DHD_DEBUG) */
++
++		bus->activity = TRUE;
++#ifdef DHD_USE_IDLECOUNT
++		bus->idlecount = 0;
++#endif /* DHD_USE_IDLECOUNT */
++	} else {
++		clkreq = 0;
++
++		if (bus->clkstate == CLK_PENDING) {
++			/* Cancel CA-only interrupt filter */
++			devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
++			devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
++			bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
++		}
++
++		bus->clkstate = CLK_SDONLY;
++		if (!SR_ENAB(bus)) {
++			bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
++			DHD_INFO(("CLKCTL: turned OFF\n"));
++			if (err) {
++				DHD_ERROR(("%s: Failed access turning clock off: %d\n",
++				           __FUNCTION__, err));
++				return BCME_ERROR;
++			}
++		}
++	}
++	return BCME_OK;
++}
++
++/* Change idle/active SD state */
++static int
++dhdsdio_sdclk(dhd_bus_t *bus, bool on)
++{
++	int err;
++	int32 iovalue;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (on) {
++		if (bus->idleclock == DHD_IDLE_STOP) {
++			/* Turn on clock and restore mode */
++			iovalue = 1;
++			err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
++			                      &iovalue, sizeof(iovalue), TRUE);
++			if (err) {
++				DHD_ERROR(("%s: error enabling sd_clock: %d\n",
++				           __FUNCTION__, err));
++				return BCME_ERROR;
++			}
++
++			iovalue = bus->sd_mode;
++			err = bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
++			                      &iovalue, sizeof(iovalue), TRUE);
++			if (err) {
++				DHD_ERROR(("%s: error changing sd_mode: %d\n",
++				           __FUNCTION__, err));
++				return BCME_ERROR;
++			}
++		} else if (bus->idleclock != DHD_IDLE_ACTIVE) {
++			/* Restore clock speed */
++			iovalue = bus->sd_divisor;
++			err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
++			                      &iovalue, sizeof(iovalue), TRUE);
++			if (err) {
++				DHD_ERROR(("%s: error restoring sd_divisor: %d\n",
++				           __FUNCTION__, err));
++				return BCME_ERROR;
++			}
++		}
++		bus->clkstate = CLK_SDONLY;
++	} else {
++		/* Stop or slow the SD clock itself */
++		if ((bus->sd_divisor == -1) || (bus->sd_mode == -1)) {
++			DHD_TRACE(("%s: can't idle clock, divisor %d mode %d\n",
++			           __FUNCTION__, bus->sd_divisor, bus->sd_mode));
++			return BCME_ERROR;
++		}
++		if (bus->idleclock == DHD_IDLE_STOP) {
++			if (sd1idle) {
++				/* Change to SD1 mode and turn off clock */
++				iovalue = 1;
++				err = bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
++				                      &iovalue, sizeof(iovalue), TRUE);
++				if (err) {
++					DHD_ERROR(("%s: error changing sd_clock: %d\n",
++					           __FUNCTION__, err));
++					return BCME_ERROR;
++				}
++			}
++
++			iovalue = 0;
++			err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
++			                      &iovalue, sizeof(iovalue), TRUE);
++			if (err) {
++				DHD_ERROR(("%s: error disabling sd_clock: %d\n",
++				           __FUNCTION__, err));
++				return BCME_ERROR;
++			}
++		} else if (bus->idleclock != DHD_IDLE_ACTIVE) {
++			/* Set divisor to idle value */
++			iovalue = bus->idleclock;
++			err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
++			                      &iovalue, sizeof(iovalue), TRUE);
++			if (err) {
++				DHD_ERROR(("%s: error changing sd_divisor: %d\n",
++				           __FUNCTION__, err));
++				return BCME_ERROR;
++			}
++		}
++		bus->clkstate = CLK_NONE;
++	}
++
++	return BCME_OK;
++}
++
++/* Transition SD and backplane clock readiness */
++static int
++dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
++{
++	int ret = BCME_OK;
++#ifdef DHD_DEBUG
++	uint oldstate = bus->clkstate;
++#endif /* DHD_DEBUG */
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	/* Early exit if we're already there */
++	if (bus->clkstate == target) {
++		if (target == CLK_AVAIL) {
++			dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
++			bus->activity = TRUE;
++#ifdef DHD_USE_IDLECOUNT
++			bus->idlecount = 0;
++#endif /* DHD_USE_IDLECOUNT */
++		}
++		return ret;
++	}
++
++	switch (target) {
++	case CLK_AVAIL:
++		/* Make sure SD clock is available */
++		if (bus->clkstate == CLK_NONE)
++			dhdsdio_sdclk(bus, TRUE);
++		/* Now request HT Avail on the backplane */
++		ret = dhdsdio_htclk(bus, TRUE, pendok);
++		if (ret == BCME_OK) {
++			dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
++		bus->activity = TRUE;
++#ifdef DHD_USE_IDLECOUNT
++			bus->idlecount = 0;
++#endif /* DHD_USE_IDLECOUNT */
++		}
++		break;
++
++	case CLK_SDONLY:
++		/* Remove HT request, or bring up SD clock */
++		if (bus->clkstate == CLK_NONE)
++			ret = dhdsdio_sdclk(bus, TRUE);
++		else if (bus->clkstate == CLK_AVAIL)
++			ret = dhdsdio_htclk(bus, FALSE, FALSE);
++		else
++			DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
++			           bus->clkstate, target));
++		if (ret == BCME_OK) {
++			dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
++		}
++		break;
++
++	case CLK_NONE:
++		/* Make sure to remove HT request */
++		if (bus->clkstate == CLK_AVAIL)
++			ret = dhdsdio_htclk(bus, FALSE, FALSE);
++		/* Now remove the SD clock */
++		ret = dhdsdio_sdclk(bus, FALSE);
++#ifdef DHD_DEBUG
++		if (dhd_console_ms == 0)
++#endif /* DHD_DEBUG */
++		if (bus->poll == 0)
++			dhd_os_wd_timer(bus->dhd, 0);
++		break;
++	}
++#ifdef DHD_DEBUG
++	DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
++#endif /* DHD_DEBUG */
++
++	return ret;
++}
++
++static int
++dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
++{
++	int err = 0;
++	bcmsdh_info_t *sdh = bus->sdh;
++	sdpcmd_regs_t *regs = bus->regs;
++	uint retries = 0;
++
++	DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
++	         (sleep ? "SLEEP" : "WAKE"),
++	          (bus->sleeping ? "SLEEP" : "WAKE")));
++
++	if (bus->dhd->hang_was_sent)
++		return BCME_ERROR;
++
++	/* Done if we're already in the requested state */
++	if (sleep == bus->sleeping)
++		return BCME_OK;
++
++	/* Going to sleep: set the alarm and turn off the lights... */
++	if (sleep) {
++		/* Don't sleep if something is pending */
++		if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
++			return BCME_BUSY;
++
++
++		if (!SLPAUTO_ENAB(bus)) {
++			/* Disable SDIO interrupts (no longer interested) */
++			bcmsdh_intr_disable(bus->sdh);
++
++			/* Make sure the controller has the bus up */
++			dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++			/* Tell device to start using OOB wakeup */
++			W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
++			if (retries > retry_limit)
++				DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
++
++			/* Turn off our contribution to the HT clock request */
++			dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++
++			bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
++				SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
++
++			/* Isolate the bus */
++			if (bus->sih->chip != BCM4329_CHIP_ID &&
++				bus->sih->chip != BCM4319_CHIP_ID) {
++				bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
++					SBSDIO_DEVCTL_PADS_ISO, NULL);
++			}
++		} else {
++			/* Leave interrupts enabled since device can exit sleep and
++			 * interrupt host
++			 */
++			err = dhdsdio_clk_devsleep_iovar(bus, TRUE /* sleep */);
++		}
++
++		/* Change state */
++		bus->sleeping = TRUE;
++#if defined(SUPPORT_P2P_GO_PS) || defined(SUSPEND16)
++		wake_up(&bus->bus_sleep);
++#endif /* LINUX && SUPPORT_P2P_GO_PS */
++	} else {
++		/* Waking up: bus power up is ok, set local state */
++
++		if (!SLPAUTO_ENAB(bus)) {
++			bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, &err);
++
++			/* Force pad isolation off if possible (in case power never toggled) */
++			bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0, NULL);
++
++
++			/* Make sure the controller has the bus up */
++			dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++			/* Send misc interrupt to indicate OOB not needed */
++			W_SDREG(0, &regs->tosbmailboxdata, retries);
++			if (retries <= retry_limit)
++				W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
++
++			if (retries > retry_limit)
++				DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
++
++			/* Make sure we have SD bus access */
++			dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++
++			/* Enable interrupts again */
++			if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
++				bus->intdis = FALSE;
++				bcmsdh_intr_enable(bus->sdh);
++			}
++		} else {
++			err = dhdsdio_clk_devsleep_iovar(bus, FALSE /* wake */);
++		}
++
++		if (err == 0) {
++			/* Change state */
++			bus->sleeping = FALSE;
++		}
++	}
++
++	return err;
++}
++
++
++#if defined(OOB_INTR_ONLY)
++void
++dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
++{
++#if defined(HW_OOB)
++	bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
++#else
++	sdpcmd_regs_t *regs = bus->regs;
++	uint retries = 0;
++
++	dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++	if (enable == TRUE) {
++
++		/* Tell device to start using OOB wakeup */
++		W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
++		if (retries > retry_limit)
++			DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
++
++	} else {
++		/* Send misc interrupt to indicate OOB not needed */
++		W_SDREG(0, &regs->tosbmailboxdata, retries);
++		if (retries <= retry_limit)
++			W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
++	}
++
++	/* Turn off our contribution to the HT clock request */
++	dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++#endif /* !defined(HW_OOB) */
++}
++#endif 
++
++int
++dhd_bus_txdata(struct dhd_bus *bus, void *pkt)
++{
++	int ret = BCME_ERROR;
++	osl_t *osh;
++	uint datalen, prec;
++#if defined(DHD_TX_DUMP)
++	uint8 *dump_data;
++	uint16 protocol;
++#endif /* DHD_TX_DUMP */
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	osh = bus->dhd->osh;
++	datalen = PKTLEN(osh, pkt);
++
++#ifdef SDTEST
++	/* Push the test header if doing loopback */
++	if (bus->ext_loop) {
++		uint8* data;
++		PKTPUSH(osh, pkt, SDPCM_TEST_HDRLEN);
++		data = PKTDATA(osh, pkt);
++		*data++ = SDPCM_TEST_ECHOREQ;
++		*data++ = (uint8)bus->loopid++;
++		*data++ = (datalen >> 0);
++		*data++ = (datalen >> 8);
++		datalen += SDPCM_TEST_HDRLEN;
++	}
++#else /* SDTEST */
++	BCM_REFERENCE(datalen);
++#endif /* SDTEST */
++
++#ifdef DHD_ULP
++	dhd_ulp_set_path(bus->dhd, DHD_ULP_TX_DATA);
++#endif /* DHD_ULP */
++
++#if defined(DHD_TX_DUMP)
++	dump_data = PKTDATA(osh, pkt);
++	dump_data += 4; /* skip 4 bytes header */
++	protocol = (dump_data[12] << 8) | dump_data[13];
++
++	if (protocol == ETHER_TYPE_802_1X) {
++		DHD_ERROR(("ETHER_TYPE_802_1X [TX]: ver %d, type %d, replay %d\n",
++			dump_data[14], dump_data[15], dump_data[30]));
++	}
++#endif /* DHD_TX_DUMP */
++
++#if defined(DHD_TX_DUMP) && defined(DHD_TX_FULL_DUMP)
++	{
++		int i;
++		DHD_ERROR(("TX DUMP\n"));
++
++		for (i = 0; i < (datalen - 4); i++) {
++			DHD_ERROR(("%02X ", dump_data[i]));
++			if ((i & 15) == 15)
++				printk("\n");
++		}
++		DHD_ERROR(("\n"));
++	}
++#endif /* DHD_TX_DUMP && DHD_TX_FULL_DUMP */
++
++	prec = PRIO2PREC((PKTPRIO(pkt) & PRIOMASK));
++
++	/* Check for existing queue, current flow-control, pending event, or pending clock */
++	if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq) || bus->dpc_sched ||
++	    (!DATAOK(bus)) || (bus->flowcontrol & NBITVAL(prec)) ||
++	    (bus->clkstate != CLK_AVAIL)) {
++		bool deq_ret;
++		int pkq_len;
++
++		DHD_TRACE(("%s: deferring pktq len %d\n", __FUNCTION__, pktq_len(&bus->txq)));
++		bus->fcqueued++;
++
++		/* Priority based enq */
++		dhd_os_sdlock_txq(bus->dhd);
++		deq_ret = dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec);
++		dhd_os_sdunlock_txq(bus->dhd);
++
++		if (!deq_ret) {
++#ifdef PROP_TXSTATUS
++			if (DHD_PKTTAG_WLFCPKT(PKTTAG(pkt)) == 0)
++#endif /* PROP_TXSTATUS */
++			{
++#ifdef DHDTCPACK_SUPPRESS
++				if (dhd_tcpack_check_xmit(bus->dhd, pkt) == BCME_ERROR) {
++					DHD_ERROR(("%s %d: tcpack_suppress ERROR!!! Stop using\n",
++						__FUNCTION__, __LINE__));
++					dhd_tcpack_suppress_set(bus->dhd, TCPACK_SUP_OFF);
++				}
++#endif /* DHDTCPACK_SUPPRESS */
++				dhd_txcomplete(bus->dhd, pkt, FALSE);
++				PKTFREE(osh, pkt, TRUE);
++			}
++			ret = BCME_NORESOURCE;
++		} else
++			ret = BCME_OK;
++
++		dhd_os_sdlock_txq(bus->dhd);
++		pkq_len = pktq_len(&bus->txq);
++		dhd_os_sdunlock_txq(bus->dhd);
++		if (pkq_len >= FCHI) {
++			bool wlfc_enabled = FALSE;
++#ifdef PROP_TXSTATUS
++			wlfc_enabled = (dhd_wlfc_flowcontrol(bus->dhd, ON, FALSE) !=
++				WLFC_UNSUPPORTED);
++#endif
++			if (!wlfc_enabled && dhd_doflow) {
++				dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, ON);
++			}
++		}
++
++#ifdef DHD_DEBUG
++		dhd_os_sdlock_txq(bus->dhd);
++		if (pktq_plen(&bus->txq, prec) > qcount[prec])
++			qcount[prec] = pktq_plen(&bus->txq, prec);
++		dhd_os_sdunlock_txq(bus->dhd);
++#endif
++
++		/* Schedule DPC if needed to send queued packet(s) */
++		if (dhd_deferred_tx && !bus->dpc_sched) {
++			bus->dpc_sched = TRUE;
++			dhd_sched_dpc(bus->dhd);
++		}
++	} else {
++		int chan = SDPCM_DATA_CHANNEL;
++
++#ifdef SDTEST
++		chan = (bus->ext_loop ? SDPCM_TEST_CHANNEL : SDPCM_DATA_CHANNEL);
++#endif
++		/* Lock: we're about to use shared data/code (and SDIO) */
++		dhd_os_sdlock(bus->dhd);
++
++		/* Otherwise, send it now */
++		BUS_WAKE(bus);
++		/* Make sure back plane ht clk is on, no pending allowed */
++		dhdsdio_clkctl(bus, CLK_AVAIL, TRUE);
++
++		ret = dhdsdio_txpkt(bus, chan, &pkt, 1, TRUE);
++
++		if (ret != BCME_OK)
++			bus->dhd->tx_errors++;
++		else
++			bus->dhd->dstats.tx_bytes += datalen;
++
++		if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
++			bus->activity = FALSE;
++			dhdsdio_bussleep(bus, TRUE);
++			dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++		}
++
++		dhd_os_sdunlock(bus->dhd);
++	}
++
++	return ret;
++}
++
++/* align packet data pointer and packet length to n-byte boundary, process packet headers,
++ * a new packet may be allocated if there is not enough head and/or tail from for padding.
++ * the caller is responsible for updating the glom size in the head packet (when glom is
++ * used)
++ *
++ * pad_pkt_len: returns the length of extra padding needed from the padding packet, this parameter
++ * is taken in tx glom mode only
++ *
++ * new_pkt: out, pointer of the new packet allocated due to insufficient head room for alignment
++ * padding, NULL if not needed, the caller is responsible for freeing the new packet
++ *
++ * return: positive value - length of the packet, including head and tail padding
++ *		   negative value - errors
++ */
++static int dhdsdio_txpkt_preprocess(dhd_bus_t *bus, void *pkt, int chan, int txseq,
++	int prev_chain_total_len, bool last_chained_pkt,
++	int *pad_pkt_len, void **new_pkt)
++{
++	osl_t *osh;
++	uint8 *frame;
++	int pkt_len;
++	int modulo;
++	int head_padding;
++	int tail_padding = 0;
++	uint32 swheader;
++	uint32 swhdr_offset;
++	bool alloc_new_pkt = FALSE;
++	uint8 sdpcm_hdrlen = bus->txglom_enable ? SDPCM_HDRLEN_TXGLOM : SDPCM_HDRLEN;
++
++	*new_pkt = NULL;
++	osh = bus->dhd->osh;
++
++#ifdef DHDTCPACK_SUPPRESS
++	if (dhd_tcpack_check_xmit(bus->dhd, pkt) == BCME_ERROR) {
++		DHD_ERROR(("%s %d: tcpack_suppress ERROR!!! Stop using it\n",
++			__FUNCTION__, __LINE__));
++		dhd_tcpack_suppress_set(bus->dhd, TCPACK_SUP_OFF);
++	}
++#endif /* DHDTCPACK_SUPPRESS */
++
++	/* Add space for the SDPCM hardware/software headers */
++	PKTPUSH(osh, pkt, sdpcm_hdrlen);
++	ASSERT(ISALIGNED((uintptr)PKTDATA(osh, pkt), 2));
++
++	frame = (uint8*)PKTDATA(osh, pkt);
++	pkt_len = (uint16)PKTLEN(osh, pkt);
++
++#ifdef WLMEDIA_HTSF
++	frame = (uint8*)PKTDATA(osh, pkt);
++	if (PKTLEN(osh, pkt) >= 100) {
++		htsf_ts = (htsfts_t*) (frame + HTSF_HOSTOFFSET + 12);
++		if (htsf_ts->magic == HTSFMAGIC) {
++			htsf_ts->c20 = get_cycles();
++			htsf_ts->t20 = dhd_get_htsf(bus->dhd->info, 0);
++		}
++	}
++#endif /* WLMEDIA_HTSF */
++#ifdef DHD_DEBUG
++	if (PKTPRIO(pkt) < ARRAYSIZE(tx_packets))
++		tx_packets[PKTPRIO(pkt)]++;
++#endif /* DHD_DEBUG */
++
++	/* align the data pointer, allocate a new packet if there is not enough space (new
++	 * packet data pointer will be aligned thus no padding will be needed)
++	 */
++	head_padding = (ulong)frame % DHD_SDALIGN;
++	if (PKTHEADROOM(osh, pkt) < head_padding) {
++		head_padding = 0;
++		alloc_new_pkt = TRUE;
++	} else {
++		uint cur_chain_total_len;
++		int chain_tail_padding = 0;
++
++		/* All packets need to be aligned by DHD_SDALIGN */
++		modulo = (pkt_len + head_padding) % DHD_SDALIGN;
++		tail_padding = modulo > 0 ? (DHD_SDALIGN - modulo) : 0;
++
++		/* Total pkt chain length needs to be aligned by block size,
++		 * unless it is a single pkt chain with total length less than one block size,
++		 * which we prefer sending by byte mode.
++		 *
++		 * Do the chain alignment here if
++		 * 1. This is the last pkt of the chain of multiple pkts or a single pkt.
++		 * 2-1. This chain is of multiple pkts, or
++		 * 2-2. This is a single pkt whose size is longer than one block size.
++		 */
++		cur_chain_total_len = prev_chain_total_len +
++			(head_padding + pkt_len + tail_padding);
++		if (last_chained_pkt && bus->blocksize != 0 &&
++			(cur_chain_total_len > (int)bus->blocksize || prev_chain_total_len > 0)) {
++			modulo = cur_chain_total_len % bus->blocksize;
++			chain_tail_padding = modulo > 0 ? (bus->blocksize - modulo) : 0;
++		}
++
++#ifdef DHDENABLE_TAILPAD
++		if (PKTTAILROOM(osh, pkt) < tail_padding) {
++			/* We don't have tail room to align by DHD_SDALIGN */
++			alloc_new_pkt = TRUE;
++			bus->tx_tailpad_pktget++;
++		} else if (PKTTAILROOM(osh, pkt) < tail_padding + chain_tail_padding) {
++			/* We have tail room for tail_padding of this pkt itself, but not for
++			 * total pkt chain alignment by block size.
++			 * Use the padding packet to avoid memory copy if applicable,
++			 * otherwise, just allocate a new pkt.
++			 */
++			if (bus->pad_pkt) {
++				*pad_pkt_len = chain_tail_padding;
++				bus->tx_tailpad_chain++;
++			} else {
++				alloc_new_pkt = TRUE;
++				bus->tx_tailpad_pktget++;
++			}
++		} else
++		/* This last pkt's tailroom is sufficient to hold both tail_padding
++		 * of the pkt itself and chain_tail_padding of total pkt chain
++		 */
++#endif /* DHDENABLE_TAILPAD */
++		tail_padding += chain_tail_padding;
++	}
++
++	DHD_INFO(("%s sdhdr len + orig_pkt_len %d h_pad %d t_pad %d pad_pkt_len %d\n",
++		__FUNCTION__, pkt_len, head_padding, tail_padding, *pad_pkt_len));
++
++	if (alloc_new_pkt) {
++		void *tmp_pkt;
++		int newpkt_size;
++		int cur_total_len;
++
++		ASSERT(*pad_pkt_len == 0);
++
++		DHD_INFO(("%s allocating new packet for padding\n", __FUNCTION__));
++
++		/* head pointer is aligned now, no padding needed */
++		head_padding = 0;
++
++		/* update the tail padding as it depends on the head padding, since a new packet is
++		 * allocated, the head padding is non longer needed and packet length is chagned
++		 */
++
++		cur_total_len = prev_chain_total_len + pkt_len;
++		if (last_chained_pkt && bus->blocksize != 0 &&
++			(cur_total_len > (int)bus->blocksize || prev_chain_total_len > 0)) {
++			modulo = cur_total_len % bus->blocksize;
++			tail_padding = modulo > 0 ? (bus->blocksize - modulo) : 0;
++		}
++		else {
++			modulo = pkt_len % DHD_SDALIGN;
++			tail_padding = modulo > 0 ? (DHD_SDALIGN - modulo) : 0;
++		}
++
++		newpkt_size = PKTLEN(osh, pkt) + bus->blocksize + DHD_SDALIGN;
++		bus->dhd->tx_realloc++;
++		tmp_pkt = PKTGET(osh, newpkt_size, TRUE);
++		if (tmp_pkt == NULL) {
++			DHD_ERROR(("failed to alloc new %d byte packet\n", newpkt_size));
++			return BCME_NOMEM;
++		}
++		PKTALIGN(osh, tmp_pkt, PKTLEN(osh, pkt), DHD_SDALIGN);
++		bcopy(PKTDATA(osh, pkt), PKTDATA(osh, tmp_pkt), PKTLEN(osh, pkt));
++		*new_pkt = tmp_pkt;
++		pkt = tmp_pkt;
++	}
++
++	if (head_padding)
++		PKTPUSH(osh, pkt, head_padding);
++
++	frame = (uint8*)PKTDATA(osh, pkt);
++	bzero(frame, head_padding + sdpcm_hdrlen);
++	pkt_len = (uint16)PKTLEN(osh, pkt);
++
++	/* the header has the followming format
++	 * 4-byte HW frame tag: length, ~length (for glom this is the total length)
++	 *
++	 * 8-byte HW extesion flags (glom mode only) as the following:
++	 *			2-byte packet length, excluding HW tag and padding
++	 *			2-byte frame channel and frame flags (e.g. next frame following)
++	 *			2-byte header length
++	 *			2-byte tail padding size
++	 *
++	 * 8-byte SW frame tags as the following
++	 *			4-byte flags: host tx seq, channel, data offset
++	 *			4-byte flags: TBD
++	 */
++
++	swhdr_offset = SDPCM_FRAMETAG_LEN;
++
++	/* hardware frame tag:
++	 *
++	 * in tx-glom mode, dongle only checks the hardware frame tag in the first
++	 * packet and sees it as the total lenght of the glom (including tail padding),
++	 * for each packet in the glom, the packet length needs to be updated, (see
++	 * below PKTSETLEN)
++	 *
++	 * in non tx-glom mode, PKTLEN still need to include tail padding as to be
++	 * referred to in sdioh_request_buffer(). The tail length will be excluded in
++	 * dhdsdio_txpkt_postprocess().
++	 */
++	*(uint16*)frame = (uint16)htol16(pkt_len);
++	*(((uint16*)frame) + 1) = (uint16)htol16(~pkt_len);
++	pkt_len += tail_padding;
++
++	/* hardware extesion flags */
++	if (bus->txglom_enable) {
++		uint32 hwheader1;
++		uint32 hwheader2;
++
++		swhdr_offset += SDPCM_HWEXT_LEN;
++		hwheader1 = (pkt_len - SDPCM_FRAMETAG_LEN - tail_padding) |
++			(last_chained_pkt << 24);
++		hwheader2 = (tail_padding) << 16;
++		htol32_ua_store(hwheader1, frame + SDPCM_FRAMETAG_LEN);
++		htol32_ua_store(hwheader2, frame + SDPCM_FRAMETAG_LEN + 4);
++	}
++	PKTSETLEN((osh), (pkt), (pkt_len));
++
++	/* software frame tags */
++	swheader = ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK)
++		| (txseq % SDPCM_SEQUENCE_WRAP) |
++		(((head_padding + sdpcm_hdrlen) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
++	htol32_ua_store(swheader, frame + swhdr_offset);
++	htol32_ua_store(0, frame + swhdr_offset + sizeof(swheader));
++
++	return pkt_len;
++}
++
++static int dhdsdio_txpkt_postprocess(dhd_bus_t *bus, void *pkt)
++{
++	osl_t *osh;
++	uint8 *frame;
++	int data_offset;
++	int tail_padding;
++	int swhdr_offset = SDPCM_FRAMETAG_LEN + (bus->txglom_enable ? SDPCM_HWEXT_LEN : 0);
++
++	(void)osh;
++	osh = bus->dhd->osh;
++
++	/* restore pkt buffer pointer, but keeps the header pushed by dhd_prot_hdrpush */
++	frame = (uint8*)PKTDATA(osh, pkt);
++
++	DHD_INFO(("%s PKTLEN before postprocess %d",
++		__FUNCTION__, PKTLEN(osh, pkt)));
++
++	/* PKTLEN still includes tail_padding, so exclude it.
++	 * We shall have head_padding + original pkt_len for PKTLEN afterwards.
++	 */
++	if (bus->txglom_enable) {
++		/* txglom pkts have tail_padding length in HW ext header */
++		tail_padding = ltoh32_ua(frame + SDPCM_FRAMETAG_LEN + 4) >> 16;
++		PKTSETLEN(osh, pkt, PKTLEN(osh, pkt) - tail_padding);
++		DHD_INFO((" txglom pkt: tail_padding %d PKTLEN %d\n",
++			tail_padding, PKTLEN(osh, pkt)));
++	} else {
++		/* non-txglom pkts have head_padding + original pkt length in HW frame tag.
++		 * We cannot refer to this field for txglom pkts as the first pkt of the chain will
++		 * have the field for the total length of the chain.
++		 */
++		PKTSETLEN(osh, pkt, *(uint16*)frame);
++		DHD_INFO((" non-txglom pkt: HW frame tag len %d after PKTLEN %d\n",
++			*(uint16*)frame, PKTLEN(osh, pkt)));
++	}
++
++	data_offset = ltoh32_ua(frame + swhdr_offset);
++	data_offset = (data_offset & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT;
++	/* Get rid of sdpcm header + head_padding */
++	PKTPULL(osh, pkt, data_offset);
++
++	DHD_INFO(("%s data_offset %d, PKTLEN %d\n",
++		__FUNCTION__, data_offset, PKTLEN(osh, pkt)));
++
++	return BCME_OK;
++}
++
++static int dhdsdio_txpkt(dhd_bus_t *bus, uint chan, void** pkts, int num_pkt, bool free_pkt)
++{
++	int i;
++	int ret = 0;
++	osl_t *osh;
++	bcmsdh_info_t *sdh;
++	void *pkt = NULL;
++	void *pkt_chain;
++	int total_len = 0;
++	void *head_pkt = NULL;
++	void *prev_pkt = NULL;
++	int pad_pkt_len = 0;
++	int new_pkt_num = 0;
++	void *new_pkts[MAX_TX_PKTCHAIN_CNT];
++	bool wlfc_enabled = FALSE;
++
++	if (bus->dhd->dongle_reset)
++		return BCME_NOTREADY;
++
++	sdh = bus->sdh;
++	osh = bus->dhd->osh;
++	/* init new_pkts[0] to make some compiler happy, not necessary as we check new_pkt_num */
++	new_pkts[0] = NULL;
++
++	for (i = 0; i < num_pkt; i++) {
++		int pkt_len;
++		bool last_pkt;
++		void *new_pkt = NULL;
++
++		pkt = pkts[i];
++		ASSERT(pkt);
++		last_pkt = (i == num_pkt - 1);
++		pkt_len = dhdsdio_txpkt_preprocess(bus, pkt, chan, bus->tx_seq + i,
++			total_len, last_pkt, &pad_pkt_len, &new_pkt);
++		if (pkt_len <= 0)
++			goto done;
++		if (new_pkt) {
++			pkt = new_pkt;
++			new_pkts[new_pkt_num++] = new_pkt;
++		}
++		total_len += pkt_len;
++
++		PKTSETNEXT(osh, pkt, NULL);
++		/* insert the packet into the list */
++		head_pkt ? PKTSETNEXT(osh, prev_pkt, pkt) : (head_pkt = pkt);
++		prev_pkt = pkt;
++
++	}
++
++	/* Update the HW frame tag (total length) in the first pkt of the glom */
++	if (bus->txglom_enable) {
++		uint8 *frame;
++
++		total_len += pad_pkt_len;
++		frame = (uint8*)PKTDATA(osh, head_pkt);
++		*(uint16*)frame = (uint16)htol16(total_len);
++		*(((uint16*)frame) + 1) = (uint16)htol16(~total_len);
++
++	}
++
++#ifdef DHDENABLE_TAILPAD
++	/* if a padding packet if needed, insert it to the end of the link list */
++	if (pad_pkt_len) {
++		PKTSETLEN(osh, bus->pad_pkt, pad_pkt_len);
++		PKTSETNEXT(osh, pkt, bus->pad_pkt);
++	}
++#endif /* DHDENABLE_TAILPAD */
++
++	/* dhd_bcmsdh_send_buf ignores the buffer pointer if he packet
++	 * parameter is not NULL, for non packet chian we pass NULL pkt pointer
++	 * so it will take the aligned length and buffer pointer.
++	 */
++	pkt_chain = PKTNEXT(osh, head_pkt) ? head_pkt : NULL;
++	ret = dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
++		PKTDATA(osh, head_pkt), total_len, pkt_chain, NULL, NULL, TXRETRIES);
++	if (ret == BCME_OK)
++		bus->tx_seq = (bus->tx_seq + num_pkt) % SDPCM_SEQUENCE_WRAP;
++
++	/* if a padding packet was needed, remove it from the link list as it not a data pkt */
++	if (pad_pkt_len && pkt)
++		PKTSETNEXT(osh, pkt, NULL);
++
++done:
++	pkt = head_pkt;
++	while (pkt) {
++		void *pkt_next = PKTNEXT(osh, pkt);
++		PKTSETNEXT(osh, pkt, NULL);
++		dhdsdio_txpkt_postprocess(bus, pkt);
++		pkt = pkt_next;
++	}
++
++	/* new packets might be allocated due to insufficient room for padding, but we
++	 * still have to indicate the original packets to upper layer
++	 */
++	for (i = 0; i < num_pkt; i++) {
++		pkt = pkts[i];
++		wlfc_enabled = FALSE;
++#ifdef PROP_TXSTATUS
++		if (DHD_PKTTAG_WLFCPKT(PKTTAG(pkt))) {
++			wlfc_enabled = (dhd_wlfc_txcomplete(bus->dhd, pkt, ret == 0) !=
++				WLFC_UNSUPPORTED);
++		}
++#endif /* PROP_TXSTATUS */
++		if (!wlfc_enabled) {
++			PKTSETNEXT(osh, pkt, NULL);
++			dhd_txcomplete(bus->dhd, pkt, ret != 0);
++			if (free_pkt)
++				PKTFREE(osh, pkt, TRUE);
++		}
++	}
++
++	for (i = 0; i < new_pkt_num; i++)
++		PKTFREE(osh, new_pkts[i], TRUE);
++
++	return ret;
++}
++
++static uint
++dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
++{
++	uint cnt = 0;
++	uint8 tx_prec_map;
++	uint16 txpktqlen = 0;
++	uint32 intstatus = 0;
++	uint retries = 0;
++	osl_t *osh;
++	uint datalen = 0;
++	dhd_pub_t *dhd = bus->dhd;
++	sdpcmd_regs_t *regs = bus->regs;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (!KSO_ENAB(bus)) {
++		DHD_ERROR(("%s: Device asleep\n", __FUNCTION__));
++		return BCME_NODEVICE;
++	}
++
++	osh = dhd->osh;
++	tx_prec_map = ~bus->flowcontrol;
++#ifdef DHD_LOSSLESS_ROAMING
++	tx_prec_map &= dhd->dequeue_prec_map;
++#endif
++	for (cnt = 0; (cnt < maxframes) && DATAOK(bus);) {
++		int i;
++		int num_pkt = 1;
++		void *pkts[MAX_TX_PKTCHAIN_CNT];
++		int prec_out;
++
++		dhd_os_sdlock_txq(bus->dhd);
++		if (bus->txglom_enable) {
++			uint32 glomlimit = (uint32)bus->txglomsize;
++#if defined(BCMSDIOH_STD)
++			if (bus->blocksize == 64) {
++				glomlimit = MIN((uint32)bus->txglomsize, BLK_64_MAXTXGLOM);
++			}
++#endif /* BCMSDIOH_STD */
++			num_pkt = MIN((uint32)DATABUFCNT(bus), glomlimit);
++			num_pkt = MIN(num_pkt, ARRAYSIZE(pkts));
++		}
++		num_pkt = MIN(num_pkt, pktq_mlen(&bus->txq, tx_prec_map));
++		for (i = 0; i < num_pkt; i++) {
++			pkts[i] = pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
++			if (!pkts[i]) {
++				DHD_ERROR(("%s: pktq_mlen non-zero when no pkt\n",
++					__FUNCTION__));
++				ASSERT(0);
++				break;
++			}
++			PKTORPHAN(pkts[i]);
++			datalen += PKTLEN(osh, pkts[i]);
++		}
++		dhd_os_sdunlock_txq(bus->dhd);
++
++		if (i == 0)
++			break;
++		if (dhdsdio_txpkt(bus, SDPCM_DATA_CHANNEL, pkts, i, TRUE) != BCME_OK)
++			dhd->tx_errors++;
++		else
++			dhd->dstats.tx_bytes += datalen;
++		cnt += i;
++
++		/* In poll mode, need to check for other events */
++		if (!bus->intr && cnt)
++		{
++			/* Check device status, signal pending interrupt */
++			R_SDREG(intstatus, &regs->intstatus, retries);
++			bus->f2txdata++;
++			if (bcmsdh_regfail(bus->sdh))
++				break;
++			if (intstatus & bus->hostintmask)
++				bus->ipend = TRUE;
++		}
++
++	}
++
++	dhd_os_sdlock_txq(bus->dhd);
++	txpktqlen = pktq_len(&bus->txq);
++	dhd_os_sdunlock_txq(bus->dhd);
++
++	/* Do flow-control if needed */
++	if (dhd->up && (dhd->busstate == DHD_BUS_DATA) && (txpktqlen < FCLOW)) {
++		bool wlfc_enabled = FALSE;
++#ifdef PROP_TXSTATUS
++		wlfc_enabled = (dhd_wlfc_flowcontrol(dhd, OFF, TRUE) != WLFC_UNSUPPORTED);
++#endif
++		if (!wlfc_enabled && dhd_doflow && dhd->txoff) {
++			dhd_txflowcontrol(dhd, ALL_INTERFACES, OFF);
++		}
++	}
++
++	return cnt;
++}
++
++static void
++dhdsdio_sendpendctl(dhd_bus_t *bus)
++{
++	bcmsdh_info_t *sdh = bus->sdh;
++	int ret;
++	uint8* frame_seq = bus->ctrl_frame_buf + SDPCM_FRAMETAG_LEN;
++
++	if (bus->txglom_enable)
++		frame_seq += SDPCM_HWEXT_LEN;
++
++	if (*frame_seq != bus->tx_seq) {
++		DHD_INFO(("%s IOCTL frame seq lag detected!"
++			" frm_seq:%d != bus->tx_seq:%d, corrected\n",
++			__FUNCTION__, *frame_seq, bus->tx_seq));
++		*frame_seq = bus->tx_seq;
++	}
++
++	ret = dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
++		(uint8 *)bus->ctrl_frame_buf, (uint32)bus->ctrl_frame_len,
++		NULL, NULL, NULL, 1);
++	if (ret == BCME_OK)
++		bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
++
++	bus->ctrl_frame_stat = FALSE;
++	dhd_wait_event_wakeup(bus->dhd);
++}
++
++int
++dhd_bus_txctl(struct dhd_bus *bus, uchar *msg, uint msglen)
++{
++	static int err_nodevice = 0;
++	uint8 *frame;
++	uint16 len;
++	uint32 swheader;
++	uint8 doff = 0;
++	int ret = -1;
++	uint8 sdpcm_hdrlen = bus->txglom_enable ? SDPCM_HDRLEN_TXGLOM : SDPCM_HDRLEN;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus->dhd->dongle_reset)
++		return -EIO;
++
++	/* Back the pointer to make a room for bus header */
++	frame = msg - sdpcm_hdrlen;
++	len = (msglen += sdpcm_hdrlen);
++
++	/* Add alignment padding (optional for ctl frames) */
++	if (dhd_alignctl) {
++		if ((doff = ((uintptr)frame % DHD_SDALIGN))) {
++			frame -= doff;
++			len += doff;
++			msglen += doff;
++			bzero(frame, doff + sdpcm_hdrlen);
++		}
++		ASSERT(doff < DHD_SDALIGN);
++	}
++	doff += sdpcm_hdrlen;
++
++	/* Round send length to next SDIO block */
++	if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
++		uint16 pad = bus->blocksize - (len % bus->blocksize);
++		if ((pad <= bus->roundup) && (pad < bus->blocksize))
++			len += pad;
++	} else if (len % DHD_SDALIGN) {
++		len += DHD_SDALIGN - (len % DHD_SDALIGN);
++	}
++
++	/* Satisfy length-alignment requirements */
++	if (forcealign && (len & (ALIGNMENT - 1)))
++		len = ROUNDUP(len, ALIGNMENT);
++
++	ASSERT(ISALIGNED((uintptr)frame, 2));
++
++
++	/* Need to lock here to protect txseq and SDIO tx calls */
++	dhd_os_sdlock(bus->dhd);
++
++	BUS_WAKE(bus);
++
++	/* Make sure backplane clock is on */
++	dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++	/* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
++	*(uint16*)frame = htol16((uint16)msglen);
++	*(((uint16*)frame) + 1) = htol16(~msglen);
++
++	if (bus->txglom_enable) {
++		uint32 hwheader1, hwheader2;
++		/* Software tag: channel, sequence number, data offset */
++		swheader = ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK)
++				| bus->tx_seq
++				| ((doff << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
++		htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN + SDPCM_HWEXT_LEN);
++		htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN
++			+ SDPCM_HWEXT_LEN + sizeof(swheader));
++
++		hwheader1 = (msglen - SDPCM_FRAMETAG_LEN) | (1 << 24);
++		hwheader2 = (len - (msglen)) << 16;
++		htol32_ua_store(hwheader1, frame + SDPCM_FRAMETAG_LEN);
++		htol32_ua_store(hwheader2, frame + SDPCM_FRAMETAG_LEN + 4);
++
++		*(uint16*)frame = htol16(len);
++		*(((uint16*)frame) + 1) = htol16(~(len));
++	} else {
++		/* Software tag: channel, sequence number, data offset */
++		swheader = ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK)
++		        | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
++		htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN);
++		htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
++	}
++
++#ifdef DHD_ULP
++	dhd_ulp_set_path(bus->dhd, DHD_ULP_TX_CTRL);
++
++	if (!TXCTLOK(bus) || !dhd_ulp_f2_ready(bus->dhd, bus->sdh))
++#else
++	if (!TXCTLOK(bus))
++#endif
++	{
++		DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
++			__FUNCTION__, bus->tx_max, bus->tx_seq));
++		bus->ctrl_frame_stat = TRUE;
++		/* Send from dpc */
++		bus->ctrl_frame_buf = frame;
++		bus->ctrl_frame_len = len;
++
++		if (!bus->dpc_sched) {
++			bus->dpc_sched = TRUE;
++			dhd_sched_dpc(bus->dhd);
++		}
++		if (bus->ctrl_frame_stat) {
++			dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
++		}
++
++		if (bus->ctrl_frame_stat == FALSE) {
++			DHD_INFO(("%s: ctrl_frame_stat == FALSE\n", __FUNCTION__));
++			ret = 0;
++		} else {
++			bus->dhd->txcnt_timeout++;
++			if (!bus->dhd->hang_was_sent) {
++				DHD_ERROR(("%s: ctrl_frame_stat == TRUE txcnt_timeout=%d\n",
++					__FUNCTION__, bus->dhd->txcnt_timeout));
++			}
++			ret = -1;
++			bus->ctrl_frame_stat = FALSE;
++			goto done;
++		}
++	}
++
++	bus->dhd->txcnt_timeout = 0;
++	bus->ctrl_frame_stat = TRUE;
++
++	if (ret == -1) {
++#ifdef DHD_DEBUG
++		if (DHD_BYTES_ON() && DHD_CTL_ON()) {
++			prhex("Tx Frame", frame, len);
++		} else if (DHD_HDRS_ON()) {
++			prhex("TxHdr", frame, MIN(len, 16));
++		}
++#endif
++		ret = dhd_bcmsdh_send_buffer(bus, frame, len);
++
++	}
++	bus->ctrl_frame_stat = FALSE;
++#ifdef DHD_ULP
++	dhd_ulp_enable_cached_sbwad(bus->dhd, bus->sdh);
++#endif /* DHD_ULP */
++
++done:
++	if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
++		bus->activity = FALSE;
++		dhdsdio_bussleep(bus, TRUE);
++		dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++	}
++
++	dhd_os_sdunlock(bus->dhd);
++
++	if (ret)
++		bus->dhd->tx_ctlerrs++;
++	else
++		bus->dhd->tx_ctlpkts++;
++
++	if (bus->dhd->txcnt_timeout >= MAX_CNTL_TX_TIMEOUT)
++		return -ETIMEDOUT;
++
++	if (ret == BCME_NODEVICE)
++		err_nodevice++;
++	else
++		err_nodevice = 0;
++
++	return ret ? err_nodevice >= ERROR_BCME_NODEVICE_MAX ? -ETIMEDOUT : -EIO : 0;
++}
++
++int
++dhd_bus_rxctl(struct dhd_bus *bus, uchar *msg, uint msglen)
++{
++	int timeleft;
++	uint rxlen = 0;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus->dhd->dongle_reset)
++		return -EIO;
++
++	/* Wait until control frame is available */
++	timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen);
++
++	dhd_os_sdlock(bus->dhd);
++	rxlen = bus->rxlen;
++	bcopy(bus->rxctl, msg, MIN(msglen, rxlen));
++	bus->rxlen = 0;
++	dhd_os_sdunlock(bus->dhd);
++
++	if (rxlen) {
++		DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
++			__FUNCTION__, rxlen, msglen));
++	} else if (timeleft == 0) {
++#ifdef DHD_DEBUG
++		uint32 status, retry = 0;
++		R_SDREG(status, &bus->regs->intstatus, retry);
++		DHD_ERROR(("%s: resumed on timeout, INT status=0x%08X\n",
++			__FUNCTION__, status));
++#else
++		DHD_ERROR(("%s: resumed on timeout\n", __FUNCTION__));
++#endif /* DHD_DEBUG */
++		dhd_os_sdlock(bus->dhd);
++		dhdsdio_checkdied(bus, NULL, 0);
++		dhd_os_sdunlock(bus->dhd);
++	} else {
++		DHD_CTL(("%s: resumed for unknown reason?\n", __FUNCTION__));
++		dhd_os_sdlock(bus->dhd);
++		dhdsdio_checkdied(bus, NULL, 0);
++		dhd_os_sdunlock(bus->dhd);
++	}
++	if (timeleft == 0) {
++		if (rxlen == 0)
++			bus->dhd->rxcnt_timeout++;
++		DHD_ERROR(("%s: rxcnt_timeout=%d, rxlen=%d\n", __FUNCTION__,
++			bus->dhd->rxcnt_timeout, rxlen));
++	}
++	else
++		bus->dhd->rxcnt_timeout = 0;
++
++	if (rxlen)
++		bus->dhd->rx_ctlpkts++;
++	else
++		bus->dhd->rx_ctlerrs++;
++
++	if (bus->dhd->rxcnt_timeout >= MAX_CNTL_RX_TIMEOUT)
++		return -ETIMEDOUT;
++
++	if (bus->dhd->dongle_trap_occured)
++		return -EREMOTEIO;
++
++	return rxlen ? (int)rxlen : -EIO;
++}
++
++/* IOVar table */
++enum {
++	IOV_INTR = 1,
++	IOV_POLLRATE,
++	IOV_SDREG,
++	IOV_SBREG,
++	IOV_SDCIS,
++	IOV_MEMBYTES,
++	IOV_RAMSIZE,
++	IOV_RAMSTART,
++#ifdef DHD_DEBUG
++	IOV_CHECKDIED,
++	IOV_SERIALCONS,
++#endif /* DHD_DEBUG */
++	IOV_SET_DOWNLOAD_STATE,
++	IOV_SOCRAM_STATE,
++	IOV_FORCEEVEN,
++	IOV_SDIOD_DRIVE,
++	IOV_READAHEAD,
++	IOV_SDRXCHAIN,
++	IOV_ALIGNCTL,
++	IOV_SDALIGN,
++	IOV_DEVRESET,
++	IOV_CPU,
++#if defined(USE_SDIOFIFO_IOVAR)
++	IOV_WATERMARK,
++	IOV_MESBUSYCTRL,
++#endif /* USE_SDIOFIFO_IOVAR */
++#ifdef SDTEST
++	IOV_PKTGEN,
++	IOV_EXTLOOP,
++#endif /* SDTEST */
++	IOV_SPROM,
++	IOV_TXBOUND,
++	IOV_RXBOUND,
++	IOV_TXMINMAX,
++	IOV_IDLETIME,
++	IOV_IDLECLOCK,
++	IOV_SD1IDLE,
++	IOV_SLEEP,
++	IOV_DONGLEISOLATION,
++	IOV_KSO,
++	IOV_DEVSLEEP,
++	IOV_DEVCAP,
++	IOV_VARS,
++#ifdef SOFTAP
++	IOV_FWPATH,
++#endif
++	IOV_TXGLOMSIZE,
++	IOV_TXGLOMMODE,
++	IOV_HANGREPORT,
++	IOV_TXINRX_THRES
++};
++
++const bcm_iovar_t dhdsdio_iovars[] = {
++	{"intr",	IOV_INTR,	0,	IOVT_BOOL,	0 },
++	{"sleep",	IOV_SLEEP,	0,	IOVT_BOOL,	0 },
++	{"pollrate",	IOV_POLLRATE,	0,	IOVT_UINT32,	0 },
++	{"idletime",	IOV_IDLETIME,	0,	IOVT_INT32,	0 },
++	{"idleclock",	IOV_IDLECLOCK,	0,	IOVT_INT32,	0 },
++	{"sd1idle",	IOV_SD1IDLE,	0,	IOVT_BOOL,	0 },
++	{"membytes",	IOV_MEMBYTES,	0,	IOVT_BUFFER,	2 * sizeof(int) },
++	{"ramsize",	IOV_RAMSIZE,	0,	IOVT_UINT32,	0 },
++	{"ramstart",	IOV_RAMSTART,	0,	IOVT_UINT32,	0 },
++	{"dwnldstate",	IOV_SET_DOWNLOAD_STATE,	0,	IOVT_BOOL,	0 },
++	{"socram_state",	IOV_SOCRAM_STATE,	0,	IOVT_BOOL,	0 },
++	{"vars",	IOV_VARS,	0,	IOVT_BUFFER,	0 },
++	{"sdiod_drive",	IOV_SDIOD_DRIVE, 0,	IOVT_UINT32,	0 },
++	{"readahead",	IOV_READAHEAD,	0,	IOVT_BOOL,	0 },
++	{"sdrxchain",	IOV_SDRXCHAIN,	0,	IOVT_BOOL,	0 },
++	{"alignctl",	IOV_ALIGNCTL,	0,	IOVT_BOOL,	0 },
++	{"sdalign",	IOV_SDALIGN,	0,	IOVT_BOOL,	0 },
++	{"devreset",	IOV_DEVRESET,	0,	IOVT_BOOL,	0 },
++#ifdef DHD_DEBUG
++	{"sdreg",	IOV_SDREG,	0,	IOVT_BUFFER,	sizeof(sdreg_t) },
++	{"sbreg",	IOV_SBREG,	0,	IOVT_BUFFER,	sizeof(sdreg_t) },
++	{"sd_cis",	IOV_SDCIS,	0,	IOVT_BUFFER,	DHD_IOCTL_MAXLEN },
++	{"forcealign",	IOV_FORCEEVEN,	0,	IOVT_BOOL,	0 },
++	{"txbound",	IOV_TXBOUND,	0,	IOVT_UINT32,	0 },
++	{"rxbound",	IOV_RXBOUND,	0,	IOVT_UINT32,	0 },
++	{"txminmax",	IOV_TXMINMAX,	0,	IOVT_UINT32,	0 },
++	{"cpu",		IOV_CPU,	0,	IOVT_BOOL,	0 },
++#ifdef DHD_DEBUG
++	{"checkdied",	IOV_CHECKDIED,	0,	IOVT_BUFFER,	0 },
++	{"serial",	IOV_SERIALCONS,	0,	IOVT_UINT32,	0 },
++#endif /* DHD_DEBUG  */
++#endif /* DHD_DEBUG */
++#ifdef SDTEST
++	{"extloop",	IOV_EXTLOOP,	0,	IOVT_BOOL,	0 },
++	{"pktgen",	IOV_PKTGEN,	0,	IOVT_BUFFER,	sizeof(dhd_pktgen_t) },
++#endif /* SDTEST */
++#if defined(USE_SDIOFIFO_IOVAR)
++	{"watermark",	IOV_WATERMARK,	0,	IOVT_UINT32,	0 },
++	{"mesbusyctrl",	IOV_MESBUSYCTRL,	0,	IOVT_UINT32,	0 },
++#endif /* USE_SDIOFIFO_IOVAR */
++	{"devcap", IOV_DEVCAP,	0,	IOVT_UINT32,	0 },
++	{"dngl_isolation", IOV_DONGLEISOLATION,	0,	IOVT_UINT32,	0 },
++	{"kso",	IOV_KSO,	0,	IOVT_UINT32,	0 },
++	{"devsleep", IOV_DEVSLEEP,	0,	IOVT_UINT32,	0 },
++#ifdef SOFTAP
++	{"fwpath", IOV_FWPATH, 0, IOVT_BUFFER, 0 },
++#endif
++	{"txglomsize", IOV_TXGLOMSIZE, 0, IOVT_UINT32, 0 },
++	{"fw_hang_report", IOV_HANGREPORT, 0, IOVT_BOOL, 0 },
++	{"txinrx_thres", IOV_TXINRX_THRES, 0, IOVT_INT32, 0 },
++	{NULL, 0, 0, 0, 0 }
++};
++
++static void
++dhd_dump_pct(struct bcmstrbuf *strbuf, char *desc, uint num, uint div)
++{
++	uint q1, q2;
++
++	if (!div) {
++		bcm_bprintf(strbuf, "%s N/A", desc);
++	} else {
++		q1 = num / div;
++		q2 = (100 * (num - (q1 * div))) / div;
++		bcm_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
++	}
++}
++
++void
++dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
++{
++	dhd_bus_t *bus = dhdp->bus;
++
++	bcm_bprintf(strbuf, "Bus SDIO structure:\n");
++	bcm_bprintf(strbuf, "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
++	            bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
++	bcm_bprintf(strbuf, "fcstate %d qlen %u tx_seq %d, max %d, rxskip %d rxlen %u rx_seq %d\n",
++	            bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max, bus->rxskip,
++	            bus->rxlen, bus->rx_seq);
++	bcm_bprintf(strbuf, "intr %d intrcount %u lastintrs %u spurious %u\n",
++	            bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
++	bcm_bprintf(strbuf, "pollrate %u pollcnt %u regfails %u\n",
++	            bus->pollrate, bus->pollcnt, bus->regfails);
++
++	bcm_bprintf(strbuf, "\nAdditional counters:\n");
++#ifdef DHDENABLE_TAILPAD
++	bcm_bprintf(strbuf, "tx_tailpad_chain %u tx_tailpad_pktget %u\n",
++	            bus->tx_tailpad_chain, bus->tx_tailpad_pktget);
++#endif /* DHDENABLE_TAILPAD */
++	bcm_bprintf(strbuf, "tx_sderrs %u fcqueued %u rxrtx %u rx_toolong %u rxc_errors %u\n",
++	            bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
++	            bus->rxc_errors);
++	bcm_bprintf(strbuf, "rx_hdrfail %u badhdr %u badseq %u\n",
++	            bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
++	bcm_bprintf(strbuf, "fc_rcvd %u, fc_xoff %u, fc_xon %u\n",
++	            bus->fc_rcvd, bus->fc_xoff, bus->fc_xon);
++	bcm_bprintf(strbuf, "rxglomfail %u, rxglomframes %u, rxglompkts %u\n",
++	            bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
++	bcm_bprintf(strbuf, "f2rx (hdrs/data) %u (%u/%u), f2tx %u f1regs %u\n",
++	            (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs, bus->f2rxdata,
++	            bus->f2txdata, bus->f1regdata);
++	{
++		dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
++		             (bus->f2rxhdrs + bus->f2rxdata));
++		dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets, bus->f1regdata);
++		dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
++		             (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
++		dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets, bus->intrcount);
++		bcm_bprintf(strbuf, "\n");
++
++		dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
++		             bus->dhd->rx_packets);
++		dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts, bus->rxglomframes);
++		bcm_bprintf(strbuf, "\n");
++
++		dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets, bus->f2txdata);
++		dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets, bus->f1regdata);
++		dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
++		             (bus->f2txdata + bus->f1regdata));
++		dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets, bus->intrcount);
++		bcm_bprintf(strbuf, "\n");
++
++		dhd_dump_pct(strbuf, "Total: pkts/f2rw",
++		             (bus->dhd->tx_packets + bus->dhd->rx_packets),
++		             (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
++		dhd_dump_pct(strbuf, ", pkts/f1sd",
++		             (bus->dhd->tx_packets + bus->dhd->rx_packets), bus->f1regdata);
++		dhd_dump_pct(strbuf, ", pkts/sd",
++		             (bus->dhd->tx_packets + bus->dhd->rx_packets),
++		             (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
++		dhd_dump_pct(strbuf, ", pkts/int",
++		             (bus->dhd->tx_packets + bus->dhd->rx_packets), bus->intrcount);
++		bcm_bprintf(strbuf, "\n\n");
++	}
++
++#ifdef SDTEST
++	if (bus->pktgen_count) {
++		bcm_bprintf(strbuf, "pktgen config and count:\n");
++		bcm_bprintf(strbuf, "freq %u count %u print %u total %u min %u len %u\n",
++		            bus->pktgen_freq, bus->pktgen_count, bus->pktgen_print,
++		            bus->pktgen_total, bus->pktgen_minlen, bus->pktgen_maxlen);
++		bcm_bprintf(strbuf, "send attempts %u rcvd %u fail %u\n",
++		            bus->pktgen_sent, bus->pktgen_rcvd, bus->pktgen_fail);
++	}
++#endif /* SDTEST */
++#ifdef DHD_DEBUG
++	bcm_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
++	            bus->dpc_sched, (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
++	bcm_bprintf(strbuf, "blocksize %u roundup %u\n", bus->blocksize, bus->roundup);
++#endif /* DHD_DEBUG */
++	bcm_bprintf(strbuf, "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
++	            bus->clkstate, bus->activity, bus->idletime, bus->idlecount, bus->sleeping);
++}
++
++void
++dhd_bus_clearcounts(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = (dhd_bus_t *)dhdp->bus;
++
++	bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
++	bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
++	bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
++#ifdef DHDENABLE_TAILPAD
++	bus->tx_tailpad_chain = bus->tx_tailpad_pktget = 0;
++#endif /* DHDENABLE_TAILPAD */
++	bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
++	bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
++	bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
++}
++
++#ifdef SDTEST
++static int
++dhdsdio_pktgen_get(dhd_bus_t *bus, uint8 *arg)
++{
++	dhd_pktgen_t pktgen;
++
++	pktgen.version = DHD_PKTGEN_VERSION;
++	pktgen.freq = bus->pktgen_freq;
++	pktgen.count = bus->pktgen_count;
++	pktgen.print = bus->pktgen_print;
++	pktgen.total = bus->pktgen_total;
++	pktgen.minlen = bus->pktgen_minlen;
++	pktgen.maxlen = bus->pktgen_maxlen;
++	pktgen.numsent = bus->pktgen_sent;
++	pktgen.numrcvd = bus->pktgen_rcvd;
++	pktgen.numfail = bus->pktgen_fail;
++	pktgen.mode = bus->pktgen_mode;
++	pktgen.stop = bus->pktgen_stop;
++
++	bcopy(&pktgen, arg, sizeof(pktgen));
++
++	return 0;
++}
++
++static int
++dhdsdio_pktgen_set(dhd_bus_t *bus, uint8 *arg)
++{
++	dhd_pktgen_t pktgen;
++	uint oldcnt, oldmode;
++
++	bcopy(arg, &pktgen, sizeof(pktgen));
++	if (pktgen.version != DHD_PKTGEN_VERSION)
++		return BCME_BADARG;
++
++	oldcnt = bus->pktgen_count;
++	oldmode = bus->pktgen_mode;
++
++	bus->pktgen_freq = pktgen.freq;
++	bus->pktgen_count = pktgen.count;
++	bus->pktgen_print = pktgen.print;
++	bus->pktgen_total = pktgen.total;
++	bus->pktgen_minlen = pktgen.minlen;
++	bus->pktgen_maxlen = pktgen.maxlen;
++	bus->pktgen_mode = pktgen.mode;
++	bus->pktgen_stop = pktgen.stop;
++
++	bus->pktgen_tick = bus->pktgen_ptick = 0;
++	bus->pktgen_prev_time = jiffies;
++	bus->pktgen_len = MAX(bus->pktgen_len, bus->pktgen_minlen);
++	bus->pktgen_len = MIN(bus->pktgen_len, bus->pktgen_maxlen);
++
++	/* Clear counts for a new pktgen (mode change, or was stopped) */
++	if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode)) {
++		bus->pktgen_sent = bus->pktgen_prev_sent = bus->pktgen_rcvd = 0;
++		bus->pktgen_prev_rcvd = bus->pktgen_fail = 0;
++	}
++
++	return 0;
++}
++#endif /* SDTEST */
++
++static void
++dhdsdio_devram_remap(dhd_bus_t *bus, bool val)
++{
++	uint8 enable, protect, remap;
++
++	si_socdevram(bus->sih, FALSE, &enable, &protect, &remap);
++	remap = val ? TRUE : FALSE;
++	si_socdevram(bus->sih, TRUE, &enable, &protect, &remap);
++}
++
++static int
++dhdsdio_membytes(dhd_bus_t *bus, bool write, uint32 address, uint8 *data, uint size)
++{
++	int bcmerror = 0;
++	uint32 sdaddr;
++	uint dsize;
++
++	/* In remap mode, adjust address beyond socram and redirect
++	 * to devram at SOCDEVRAM_BP_ADDR since remap address > orig_ramsize
++	 * is not backplane accessible
++	 */
++	if (REMAP_ENAB(bus) && REMAP_ISADDR(bus, address)) {
++		address -= bus->orig_ramsize;
++		address += SOCDEVRAM_BP_ADDR;
++	}
++
++	/* Determine initial transfer parameters */
++	sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
++	if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
++		dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
++	else
++		dsize = size;
++
++	/* Set the backplane window to include the start address */
++	if ((bcmerror = dhdsdio_set_siaddr_window(bus, address))) {
++		DHD_ERROR(("%s: window change failed\n", __FUNCTION__));
++		goto xfer_done;
++	}
++
++	/* Do the transfer(s) */
++	while (size) {
++		DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
++		          __FUNCTION__, (write ? "write" : "read"), dsize, sdaddr,
++		          (address & SBSDIO_SBWINDOW_MASK)));
++		if ((bcmerror = bcmsdh_rwdata(bus->sdh, write, sdaddr, data, dsize))) {
++			DHD_ERROR(("%s: membytes transfer failed\n", __FUNCTION__));
++			break;
++		}
++
++		/* Adjust for next transfer (if any) */
++		if ((size -= dsize)) {
++			data += dsize;
++			address += dsize;
++			if ((bcmerror = dhdsdio_set_siaddr_window(bus, address))) {
++				DHD_ERROR(("%s: window change failed\n", __FUNCTION__));
++				break;
++			}
++			sdaddr = 0;
++			dsize = MIN(SBSDIO_SB_OFT_ADDR_LIMIT, size);
++		}
++
++	}
++
++xfer_done:
++	/* Return the window to backplane enumeration space for core access */
++	if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
++		DHD_ERROR(("%s: FAILED to set window back to 0x%x\n", __FUNCTION__,
++			bcmsdh_cur_sbwad(bus->sdh)));
++	}
++
++	return bcmerror;
++}
++
++static int
++dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
++{
++	uint32 addr;
++	int rv, i;
++	uint32 shaddr = 0;
++
++	if (bus->sih == NULL) {
++		if (bus->dhd && bus->dhd->dongle_reset) {
++			DHD_ERROR(("%s: Dongle is in reset state\n", __FUNCTION__));
++			return BCME_NOTREADY;
++		} else {
++			ASSERT(bus->dhd);
++			ASSERT(bus->sih);
++			DHD_ERROR(("%s: The address of sih is invalid\n", __FUNCTION__));
++			return BCME_ERROR;
++		}
++	}
++	if ((CHIPID(bus->sih->chip) == BCM43430_CHIP_ID ||
++		CHIPID(bus->sih->chip) == BCM43018_CHIP_ID) && !dhdsdio_sr_cap(bus))
++		bus->srmemsize = 0;
++
++	shaddr = bus->dongle_ram_base + bus->ramsize - 4;
++	i = 0;
++	do {
++		/* Read last word in memory to determine address of sdpcm_shared structure */
++		if ((rv = dhdsdio_membytes(bus, FALSE, shaddr, (uint8 *)&addr, 4)) < 0)
++			return rv;
++
++		addr = ltoh32(addr);
++
++		DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
++
++		/*
++		 * Check if addr is valid.
++		 * NVRAM length at the end of memory should have been overwritten.
++		 */
++		if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
++			if ((bus->srmemsize > 0) && (i++ == 0)) {
++				shaddr -= bus->srmemsize;
++			} else {
++				DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
++					__FUNCTION__, addr));
++				return BCME_ERROR;
++			}
++		} else
++			break;
++	} while (i < 2);
++
++	/* Read hndrte_shared structure */
++	if ((rv = dhdsdio_membytes(bus, FALSE, addr, (uint8 *)sh, sizeof(sdpcm_shared_t))) < 0)
++		return rv;
++
++	/* Endianness */
++	sh->flags = ltoh32(sh->flags);
++	sh->trap_addr = ltoh32(sh->trap_addr);
++	sh->assert_exp_addr = ltoh32(sh->assert_exp_addr);
++	sh->assert_file_addr = ltoh32(sh->assert_file_addr);
++	sh->assert_line = ltoh32(sh->assert_line);
++	sh->console_addr = ltoh32(sh->console_addr);
++	sh->msgtrace_addr = ltoh32(sh->msgtrace_addr);
++
++	if ((sh->flags & SDPCM_SHARED_VERSION_MASK) == 3 && SDPCM_SHARED_VERSION == 1)
++		return BCME_OK;
++
++	if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
++		DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
++		           "is different than sdpcm_shared version %d in dongle\n",
++		           __FUNCTION__, SDPCM_SHARED_VERSION,
++		           sh->flags & SDPCM_SHARED_VERSION_MASK));
++		return BCME_ERROR;
++	}
++
++	return BCME_OK;
++}
++
++#define CONSOLE_LINE_MAX	192
++
++#ifdef DHD_DEBUG
++static int
++dhdsdio_readconsole(dhd_bus_t *bus)
++{
++	dhd_console_t *c = &bus->console;
++	uint8 line[CONSOLE_LINE_MAX], ch;
++	uint32 n, idx, addr;
++	int rv;
++
++	/* Don't do anything until FWREADY updates console address */
++	if (bus->console_addr == 0)
++		return 0;
++
++	if (!KSO_ENAB(bus))
++		return 0;
++
++	/* Read console log struct */
++	addr = bus->console_addr + OFFSETOF(hnd_cons_t, log);
++	if ((rv = dhdsdio_membytes(bus, FALSE, addr, (uint8 *)&c->log, sizeof(c->log))) < 0)
++		return rv;
++
++	/* Allocate console buffer (one time only) */
++	if (c->buf == NULL) {
++		c->bufsize = ltoh32(c->log.buf_size);
++		if ((c->buf = MALLOC(bus->dhd->osh, c->bufsize)) == NULL)
++			return BCME_NOMEM;
++	}
++
++	idx = ltoh32(c->log.idx);
++
++	/* Protect against corrupt value */
++	if (idx > c->bufsize)
++		return BCME_ERROR;
++
++	/* Skip reading the console buffer if the index pointer has not moved */
++	if (idx == c->last)
++		return BCME_OK;
++
++	/* Read the console buffer */
++	addr = ltoh32(c->log.buf);
++	if ((rv = dhdsdio_membytes(bus, FALSE, addr, c->buf, c->bufsize)) < 0)
++		return rv;
++
++	while (c->last != idx) {
++		for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
++			if (c->last == idx) {
++				/* This would output a partial line.  Instead, back up
++				 * the buffer pointer and output this line next time around.
++				 */
++				if (c->last >= n)
++					c->last -= n;
++				else
++					c->last = c->bufsize - n;
++				goto break2;
++			}
++			ch = c->buf[c->last];
++			c->last = (c->last + 1) % c->bufsize;
++			if (ch == '\n')
++				break;
++			line[n] = ch;
++		}
++
++		if (n > 0) {
++			if (line[n - 1] == '\r')
++				n--;
++			line[n] = 0;
++			printf("CONSOLE: %s\n", line);
++#ifdef LOG_INTO_TCPDUMP
++			dhd_sendup_log(bus->dhd, line, n);
++#endif /* LOG_INTO_TCPDUMP */
++		}
++	}
++break2:
++
++	return BCME_OK;
++}
++#endif /* DHD_DEBUG */
++
++static int
++dhdsdio_checkdied(dhd_bus_t *bus, char *data, uint size)
++{
++	int bcmerror = 0;
++	uint msize = 512;
++	char *mbuffer = NULL;
++	char *console_buffer = NULL;
++	uint maxstrlen = 256;
++	char *str = NULL;
++	trap_t tr;
++	sdpcm_shared_t sdpcm_shared;
++	struct bcmstrbuf strbuf;
++	uint32 console_ptr, console_size, console_index;
++	uint8 line[CONSOLE_LINE_MAX], ch;
++	uint32 n, i, addr;
++	int rv;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (DHD_NOCHECKDIED_ON())
++		return 0;
++
++	if (data == NULL) {
++		/*
++		 * Called after a rx ctrl timeout. "data" is NULL.
++		 * allocate memory to trace the trap or assert.
++		 */
++		size = msize;
++		mbuffer = data = MALLOC(bus->dhd->osh, msize);
++		if (mbuffer == NULL) {
++			DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, msize));
++			bcmerror = BCME_NOMEM;
++			goto done;
++		}
++	}
++
++	if ((str = MALLOC(bus->dhd->osh, maxstrlen)) == NULL) {
++		DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, maxstrlen));
++		bcmerror = BCME_NOMEM;
++		goto done;
++	}
++
++	if ((bcmerror = dhdsdio_readshared(bus, &sdpcm_shared)) < 0)
++		goto done;
++
++	bcm_binit(&strbuf, data, size);
++
++	bcm_bprintf(&strbuf, "msgtrace address : 0x%08X\nconsole address  : 0x%08X\n",
++	            sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
++
++	if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
++		/* NOTE: Misspelled assert is intentional - DO NOT FIX.
++		 * (Avoids conflict with real asserts for programmatic parsing of output.)
++		 */
++		bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
++	}
++
++	if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT|SDPCM_SHARED_TRAP)) == 0) {
++		/* NOTE: Misspelled assert is intentional - DO NOT FIX.
++		 * (Avoids conflict with real asserts for programmatic parsing of output.)
++		 */
++		bcm_bprintf(&strbuf, "No trap%s in dongle",
++		          (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
++		          ?"/assrt" :"");
++	} else {
++		if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
++			/* Download assert */
++			bcm_bprintf(&strbuf, "Dongle assert");
++			if (sdpcm_shared.assert_exp_addr != 0) {
++				str[0] = '\0';
++				if ((bcmerror = dhdsdio_membytes(bus, FALSE,
++				                                 sdpcm_shared.assert_exp_addr,
++				                                 (uint8 *)str, maxstrlen)) < 0)
++					goto done;
++
++				str[maxstrlen - 1] = '\0';
++				bcm_bprintf(&strbuf, " expr \"%s\"", str);
++			}
++
++			if (sdpcm_shared.assert_file_addr != 0) {
++				str[0] = '\0';
++				if ((bcmerror = dhdsdio_membytes(bus, FALSE,
++				                                 sdpcm_shared.assert_file_addr,
++				                                 (uint8 *)str, maxstrlen)) < 0)
++					goto done;
++
++				str[maxstrlen - 1] = '\0';
++				bcm_bprintf(&strbuf, " file \"%s\"", str);
++			}
++
++			bcm_bprintf(&strbuf, " line %d ", sdpcm_shared.assert_line);
++		}
++
++		if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
++			bus->dhd->dongle_trap_occured = TRUE;
++			if ((bcmerror = dhdsdio_membytes(bus, FALSE,
++			                                 sdpcm_shared.trap_addr,
++			                                 (uint8*)&tr, sizeof(trap_t))) < 0)
++				goto done;
++
++			bcm_bprintf(&strbuf,
++			"Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
++			            "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
++			"r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, "
++			"r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n\n",
++			ltoh32(tr.type), ltoh32(tr.epc), ltoh32(tr.cpsr), ltoh32(tr.spsr),
++			ltoh32(tr.r13), ltoh32(tr.r14), ltoh32(tr.pc),
++			ltoh32(sdpcm_shared.trap_addr),
++			ltoh32(tr.r0), ltoh32(tr.r1), ltoh32(tr.r2), ltoh32(tr.r3),
++			ltoh32(tr.r4), ltoh32(tr.r5), ltoh32(tr.r6), ltoh32(tr.r7));
++
++			addr = sdpcm_shared.console_addr + OFFSETOF(hnd_cons_t, log);
++			if ((rv = dhdsdio_membytes(bus, FALSE, addr,
++				(uint8 *)&console_ptr, sizeof(console_ptr))) < 0)
++				goto printbuf;
++
++			addr = sdpcm_shared.console_addr + OFFSETOF(hnd_cons_t, log.buf_size);
++			if ((rv = dhdsdio_membytes(bus, FALSE, addr,
++				(uint8 *)&console_size, sizeof(console_size))) < 0)
++				goto printbuf;
++
++			addr = sdpcm_shared.console_addr + OFFSETOF(hnd_cons_t, log.idx);
++			if ((rv = dhdsdio_membytes(bus, FALSE, addr,
++				(uint8 *)&console_index, sizeof(console_index))) < 0)
++				goto printbuf;
++
++			console_ptr = ltoh32(console_ptr);
++			console_size = ltoh32(console_size);
++			console_index = ltoh32(console_index);
++
++			if (console_size > CONSOLE_BUFFER_MAX ||
++				!(console_buffer = MALLOC(bus->dhd->osh, console_size)))
++				goto printbuf;
++
++			if ((rv = dhdsdio_membytes(bus, FALSE, console_ptr,
++				(uint8 *)console_buffer, console_size)) < 0)
++				goto printbuf;
++
++			for (i = 0, n = 0; i < console_size; i += n + 1) {
++				for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
++					ch = console_buffer[(console_index + i + n) % console_size];
++					if (ch == '\n')
++						break;
++					line[n] = ch;
++				}
++
++
++				if (n > 0) {
++					if (line[n - 1] == '\r')
++						n--;
++					line[n] = 0;
++					/* Don't use DHD_ERROR macro since we print
++					 * a lot of information quickly. The macro
++					 * will truncate a lot of the printfs
++					 */
++
++					if (dhd_msg_level & DHD_ERROR_VAL)
++						printf("CONSOLE: %s\n", line);
++				}
++			}
++		}
++	}
++
++printbuf:
++	if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) {
++		DHD_ERROR(("%s: %s\n", __FUNCTION__, strbuf.origbuf));
++	}
++
++#if defined(DHD_FW_COREDUMP)
++	if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
++		/* Mem dump to a file on device */
++		dhdsdio_mem_dump(bus);
++	}
++#endif /* #if defined(DHD_FW_COREDUMP) */
++
++done:
++	if (mbuffer)
++		MFREE(bus->dhd->osh, mbuffer, msize);
++	if (str)
++		MFREE(bus->dhd->osh, str, maxstrlen);
++	if (console_buffer)
++		MFREE(bus->dhd->osh, console_buffer, console_size);
++
++	return bcmerror;
++}
++
++#if defined(DHD_FW_COREDUMP)
++static int
++dhdsdio_mem_dump(dhd_bus_t *bus)
++{
++	int ret = 0;
++	int size; /* Full mem size */
++	int start = bus->dongle_ram_base; /* Start address */
++	int read_size = 0; /* Read size of each iteration */
++	uint8 *buf = NULL, *databuf = NULL;
++
++	/* Get full mem size */
++	size = bus->ramsize;
++	buf = dhd_get_fwdump_buf(bus->dhd, size);
++	if (!buf) {
++		printf("%s: Out of memory (%d bytes)\n", __FUNCTION__, size);
++		return -1;
++	}
++
++	/* Read mem content */
++	printf("Dump dongle memory");
++	databuf = buf;
++	while (size)
++	{
++		read_size = MIN(MEMBLOCK, size);
++		if ((ret = dhdsdio_membytes(bus, FALSE, start, databuf, read_size)))
++		{
++			printf("%s: Error membytes %d\n", __FUNCTION__, ret);
++			return -1;
++		}
++		/* Decrement size and increment start address */
++		size -= read_size;
++		start += read_size;
++		databuf += read_size;
++	}
++	printf("Done\n");
++
++	/* buf, actually soc_ram free handled in dhd_{free,clear} */
++	if (write_to_file(bus->dhd, buf, bus->ramsize))
++	{
++		printf("%s: Error writing to files\n", __FUNCTION__);
++		return -1;
++	}
++
++	return 0;
++}
++#endif /* DHD_FW_COREDUMP */
++
++int
++dhd_socram_dump(dhd_bus_t * bus)
++{
++#if defined(DHD_FW_COREDUMP)
++	return (dhdsdio_mem_dump(bus));
++#else
++	return -1;
++#endif
++}
++
++int
++dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
++{
++	int bcmerror = BCME_OK;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus->dhd->up &&
++#ifdef DHD_ULP
++		(DHD_ULP_DISABLED == dhd_ulp_get_ulp_state(bus->dhd)) &&
++#endif /* DHD_ULP */
++		1) {
++		bcmerror = BCME_NOTDOWN;
++		goto err;
++	}
++	if (!len) {
++		bcmerror = BCME_BUFTOOSHORT;
++		goto err;
++	}
++
++	/* Free the old ones and replace with passed variables */
++	if (bus->vars)
++		MFREE(bus->dhd->osh, bus->vars, bus->varsz);
++
++	bus->vars = MALLOC(bus->dhd->osh, len);
++	bus->varsz = bus->vars ? len : 0;
++	if (bus->vars == NULL) {
++		bcmerror = BCME_NOMEM;
++		goto err;
++	}
++
++	/* Copy the passed variables, which should include the terminating double-null */
++	bcopy(arg, bus->vars, bus->varsz);
++err:
++	return bcmerror;
++}
++
++#ifdef DHD_DEBUG
++
++#define CC_PLL_CHIPCTRL_SERIAL_ENAB		(1  << 24)
++#define CC_CHIPCTRL_JTAG_SEL			(1  << 3)
++#define CC_CHIPCTRL_GPIO_SEL				(0x3)
++#define CC_PLL_CHIPCTRL_SERIAL_ENAB_4334	(1  << 28)
++
++static int
++dhd_serialconsole(dhd_bus_t *bus, bool set, bool enable, int *bcmerror)
++{
++	int int_val;
++	uint32 addr, data, uart_enab = 0;
++	uint32 jtag_sel = CC_CHIPCTRL_JTAG_SEL;
++	uint32 gpio_sel = CC_CHIPCTRL_GPIO_SEL;
++
++	addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_addr);
++	data = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_data);
++	*bcmerror = 0;
++
++	bcmsdh_reg_write(bus->sdh, addr, 4, 1);
++	if (bcmsdh_regfail(bus->sdh)) {
++		*bcmerror = BCME_SDIO_ERROR;
++		return -1;
++	}
++	int_val = bcmsdh_reg_read(bus->sdh, data, 4);
++	if (bcmsdh_regfail(bus->sdh)) {
++		*bcmerror = BCME_SDIO_ERROR;
++		return -1;
++	}
++	if (bus->sih->chip == BCM4330_CHIP_ID) {
++		uart_enab = CC_PLL_CHIPCTRL_SERIAL_ENAB;
++	}
++	else if (bus->sih->chip == BCM4334_CHIP_ID ||
++		bus->sih->chip == BCM43340_CHIP_ID ||
++		bus->sih->chip == BCM43341_CHIP_ID ||
++		bus->sih->chip == BCM43342_CHIP_ID ||
++		0) {
++		if (enable) {
++			/* Moved to PMU chipcontrol 1 from 4330 */
++			int_val &= ~gpio_sel;
++			int_val |= jtag_sel;
++		} else {
++			int_val |= gpio_sel;
++			int_val &= ~jtag_sel;
++		}
++		uart_enab = CC_PLL_CHIPCTRL_SERIAL_ENAB_4334;
++	}
++
++	if (!set)
++		return (int_val & uart_enab);
++	if (enable)
++		int_val |= uart_enab;
++	else
++		int_val &= ~uart_enab;
++	bcmsdh_reg_write(bus->sdh, data, 4, int_val);
++	if (bcmsdh_regfail(bus->sdh)) {
++		*bcmerror = BCME_SDIO_ERROR;
++		return -1;
++	}
++	if (bus->sih->chip == BCM4330_CHIP_ID) {
++		uint32 chipcontrol;
++		addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol);
++		chipcontrol = bcmsdh_reg_read(bus->sdh, addr, 4);
++		chipcontrol &= ~jtag_sel;
++		if (enable) {
++			chipcontrol |=  jtag_sel;
++			chipcontrol &= ~gpio_sel;
++		}
++		bcmsdh_reg_write(bus->sdh, addr, 4, chipcontrol);
++	}
++
++	return (int_val & uart_enab);
++}
++#endif 
++
++static int
++dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, const char *name,
++                void *params, int plen, void *arg, int len, int val_size)
++{
++	int bcmerror = 0;
++	int32 int_val = 0;
++	bool bool_val = 0;
++
++	DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p len %d val_size %d\n",
++	           __FUNCTION__, actionid, name, params, plen, arg, len, val_size));
++
++	if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid))) != 0)
++		goto exit;
++
++	if (plen >= (int)sizeof(int_val))
++		bcopy(params, &int_val, sizeof(int_val));
++
++	bool_val = (int_val != 0) ? TRUE : FALSE;
++
++
++	/* Some ioctls use the bus */
++	dhd_os_sdlock(bus->dhd);
++
++	/* Check if dongle is in reset. If so, only allow DEVRESET iovars */
++	if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
++	                                actionid == IOV_GVAL(IOV_DEVRESET))) {
++		bcmerror = BCME_NOTREADY;
++		goto exit;
++	}
++
++	/*
++	 * Special handling for keepSdioOn: New SDIO Wake-up Mechanism
++	 */
++	if ((vi->varid == IOV_KSO) && (IOV_ISSET(actionid))) {
++		dhdsdio_clk_kso_iovar(bus, bool_val);
++		goto exit;
++	} else if ((vi->varid == IOV_DEVSLEEP) && (IOV_ISSET(actionid))) {
++		{
++			dhdsdio_clk_devsleep_iovar(bus, bool_val);
++			if (!SLPAUTO_ENAB(bus) && (bool_val == FALSE) && (bus->ipend)) {
++				DHD_ERROR(("INT pending in devsleep 1, dpc_sched: %d\n",
++					bus->dpc_sched));
++				if (!bus->dpc_sched) {
++					bus->dpc_sched = TRUE;
++					dhd_sched_dpc(bus->dhd);
++				}
++			}
++		}
++		goto exit;
++	}
++
++	/* Handle sleep stuff before any clock mucking */
++	if (vi->varid == IOV_SLEEP) {
++		if (IOV_ISSET(actionid)) {
++			bcmerror = dhdsdio_bussleep(bus, bool_val);
++		} else {
++			int_val = (int32)bus->sleeping;
++			bcopy(&int_val, arg, val_size);
++		}
++		goto exit;
++	}
++
++	/* Request clock to allow SDIO accesses */
++	if (!bus->dhd->dongle_reset) {
++		BUS_WAKE(bus);
++		dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++	}
++
++	switch (actionid) {
++	case IOV_GVAL(IOV_INTR):
++		int_val = (int32)bus->intr;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_INTR):
++		bus->intr = bool_val;
++		bus->intdis = FALSE;
++		if (bus->dhd->up) {
++			if (bus->intr) {
++				DHD_INTR(("%s: enable SDIO device interrupts\n", __FUNCTION__));
++				bcmsdh_intr_enable(bus->sdh);
++			} else {
++				DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__));
++				bcmsdh_intr_disable(bus->sdh);
++			}
++		}
++		break;
++
++	case IOV_GVAL(IOV_POLLRATE):
++		int_val = (int32)bus->pollrate;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_POLLRATE):
++		bus->pollrate = (uint)int_val;
++		bus->poll = (bus->pollrate != 0);
++		break;
++
++	case IOV_GVAL(IOV_IDLETIME):
++		int_val = bus->idletime;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_IDLETIME):
++		if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE)) {
++			bcmerror = BCME_BADARG;
++		} else {
++			bus->idletime = int_val;
++		}
++		break;
++
++	case IOV_GVAL(IOV_IDLECLOCK):
++		int_val = (int32)bus->idleclock;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_IDLECLOCK):
++		bus->idleclock = int_val;
++		break;
++
++	case IOV_GVAL(IOV_SD1IDLE):
++		int_val = (int32)sd1idle;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_SD1IDLE):
++		sd1idle = bool_val;
++		break;
++
++
++	case IOV_SVAL(IOV_MEMBYTES):
++	case IOV_GVAL(IOV_MEMBYTES):
++	{
++		uint32 address;
++		uint size, dsize;
++		uint8 *data;
++
++		bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
++
++		ASSERT(plen >= 2*sizeof(int));
++
++		address = (uint32)int_val;
++		bcopy((char *)params + sizeof(int_val), &int_val, sizeof(int_val));
++		size = (uint)int_val;
++
++		/* Do some validation */
++		dsize = set ? plen - (2 * sizeof(int)) : len;
++		if (dsize < size) {
++			DHD_ERROR(("%s: error on %s membytes, addr 0x%08x size %d dsize %d\n",
++			           __FUNCTION__, (set ? "set" : "get"), address, size, dsize));
++			bcmerror = BCME_BADARG;
++			break;
++		}
++
++		DHD_INFO(("%s: Request to %s %d bytes at address 0x%08x\n", __FUNCTION__,
++		          (set ? "write" : "read"), size, address));
++
++		/* check if CR4 */
++		if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
++			/*
++			 * If address is start of RAM (i.e. a downloaded image),
++			 * store the reset instruction to be written in 0
++			 */
++			if (set && address == bus->dongle_ram_base) {
++				bus->resetinstr = *(((uint32*)params) + 2);
++			}
++		} else {
++		/* If we know about SOCRAM, check for a fit */
++		if ((bus->orig_ramsize) &&
++		    ((address > bus->orig_ramsize) || (address + size > bus->orig_ramsize)))
++		{
++			uint8 enable, protect, remap;
++			si_socdevram(bus->sih, FALSE, &enable, &protect, &remap);
++			if (!enable || protect) {
++				DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d bytes at 0x%08x\n",
++					__FUNCTION__, bus->orig_ramsize, size, address));
++				DHD_ERROR(("%s: socram enable %d, protect %d\n",
++					__FUNCTION__, enable, protect));
++				bcmerror = BCME_BADARG;
++				break;
++			}
++
++			if (!REMAP_ENAB(bus) && (address >= SOCDEVRAM_ARM_ADDR)) {
++				uint32 devramsize = si_socdevram_size(bus->sih);
++				if ((address < SOCDEVRAM_ARM_ADDR) ||
++					(address + size > (SOCDEVRAM_ARM_ADDR + devramsize))) {
++					DHD_ERROR(("%s: bad address 0x%08x, size 0x%08x\n",
++						__FUNCTION__, address, size));
++					DHD_ERROR(("%s: socram range 0x%08x,size 0x%08x\n",
++						__FUNCTION__, SOCDEVRAM_ARM_ADDR, devramsize));
++					bcmerror = BCME_BADARG;
++					break;
++				}
++				/* move it such that address is real now */
++				address -= SOCDEVRAM_ARM_ADDR;
++				address += SOCDEVRAM_BP_ADDR;
++				DHD_INFO(("%s: Request to %s %d bytes @ Mapped address 0x%08x\n",
++					__FUNCTION__, (set ? "write" : "read"), size, address));
++			} else if (REMAP_ENAB(bus) && REMAP_ISADDR(bus, address) && remap) {
++				/* Can not access remap region while devram remap bit is set
++				 * ROM content would be returned in this case
++				 */
++				DHD_ERROR(("%s: Need to disable remap for address 0x%08x\n",
++					__FUNCTION__, address));
++				bcmerror = BCME_ERROR;
++				break;
++			}
++		}
++		}
++
++		/* Generate the actual data pointer */
++		data = set ? (uint8*)params + 2 * sizeof(int): (uint8*)arg;
++
++		/* Call to do the transfer */
++		bcmerror = dhdsdio_membytes(bus, set, address, data, size);
++
++		break;
++	}
++
++	case IOV_GVAL(IOV_RAMSIZE):
++		int_val = (int32)bus->ramsize;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_RAMSTART):
++		int_val = (int32)bus->dongle_ram_base;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_SDIOD_DRIVE):
++		int_val = (int32)dhd_sdiod_drive_strength;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_SDIOD_DRIVE):
++		dhd_sdiod_drive_strength = int_val;
++		si_sdiod_drive_strength_init(bus->sih, bus->dhd->osh, dhd_sdiod_drive_strength);
++		break;
++
++	case IOV_SVAL(IOV_SET_DOWNLOAD_STATE):
++		bcmerror = dhdsdio_download_state(bus, bool_val);
++		break;
++
++	case IOV_SVAL(IOV_SOCRAM_STATE):
++		bcmerror = dhdsdio_download_state(bus, bool_val);
++		break;
++
++	case IOV_SVAL(IOV_VARS):
++		bcmerror = dhdsdio_downloadvars(bus, arg, len);
++		break;
++
++	case IOV_GVAL(IOV_READAHEAD):
++		int_val = (int32)dhd_readahead;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_READAHEAD):
++		if (bool_val && !dhd_readahead)
++			bus->nextlen = 0;
++		dhd_readahead = bool_val;
++		break;
++
++	case IOV_GVAL(IOV_SDRXCHAIN):
++		int_val = (int32)bus->use_rxchain;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_SDRXCHAIN):
++		if (bool_val && !bus->sd_rxchain)
++			bcmerror = BCME_UNSUPPORTED;
++		else
++			bus->use_rxchain = bool_val;
++		break;
++	case IOV_GVAL(IOV_ALIGNCTL):
++		int_val = (int32)dhd_alignctl;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_ALIGNCTL):
++		dhd_alignctl = bool_val;
++		break;
++
++	case IOV_GVAL(IOV_SDALIGN):
++		int_val = DHD_SDALIGN;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++#ifdef DHD_DEBUG
++	case IOV_GVAL(IOV_VARS):
++		if (bus->varsz < (uint)len)
++			bcopy(bus->vars, arg, bus->varsz);
++		else
++			bcmerror = BCME_BUFTOOSHORT;
++		break;
++#endif /* DHD_DEBUG */
++
++#ifdef DHD_DEBUG
++	case IOV_GVAL(IOV_SDREG):
++	{
++		sdreg_t *sd_ptr;
++		uint32 addr, size;
++
++		sd_ptr = (sdreg_t *)params;
++
++		addr = (uint32)((ulong)bus->regs + sd_ptr->offset);
++		size = sd_ptr->func;
++		int_val = (int32)bcmsdh_reg_read(bus->sdh, addr, size);
++		if (bcmsdh_regfail(bus->sdh))
++			bcmerror = BCME_SDIO_ERROR;
++		bcopy(&int_val, arg, sizeof(int32));
++		break;
++	}
++
++	case IOV_SVAL(IOV_SDREG):
++	{
++		sdreg_t *sd_ptr;
++		uint32 addr, size;
++
++		sd_ptr = (sdreg_t *)params;
++
++		addr = (uint32)((ulong)bus->regs + sd_ptr->offset);
++		size = sd_ptr->func;
++		bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
++		if (bcmsdh_regfail(bus->sdh))
++			bcmerror = BCME_SDIO_ERROR;
++		break;
++	}
++
++	/* Same as above, but offset is not backplane (not SDIO core) */
++	case IOV_GVAL(IOV_SBREG):
++	{
++		sdreg_t sdreg;
++		uint32 addr, size;
++
++		bcopy(params, &sdreg, sizeof(sdreg));
++
++		addr = SI_ENUM_BASE + sdreg.offset;
++		size = sdreg.func;
++		int_val = (int32)bcmsdh_reg_read(bus->sdh, addr, size);
++		if (bcmsdh_regfail(bus->sdh))
++			bcmerror = BCME_SDIO_ERROR;
++		bcopy(&int_val, arg, sizeof(int32));
++		break;
++	}
++
++	case IOV_SVAL(IOV_SBREG):
++	{
++		sdreg_t sdreg;
++		uint32 addr, size;
++
++		bcopy(params, &sdreg, sizeof(sdreg));
++
++		addr = SI_ENUM_BASE + sdreg.offset;
++		size = sdreg.func;
++		bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
++		if (bcmsdh_regfail(bus->sdh))
++			bcmerror = BCME_SDIO_ERROR;
++		break;
++	}
++
++	case IOV_GVAL(IOV_SDCIS):
++	{
++		*(char *)arg = 0;
++
++		bcmstrcat(arg, "\nFunc 0\n");
++		bcmsdh_cis_read(bus->sdh, 0x10, (uint8 *)arg + strlen(arg), SBSDIO_CIS_SIZE_LIMIT);
++		bcmstrcat(arg, "\nFunc 1\n");
++		bcmsdh_cis_read(bus->sdh, 0x11, (uint8 *)arg + strlen(arg), SBSDIO_CIS_SIZE_LIMIT);
++		bcmstrcat(arg, "\nFunc 2\n");
++		bcmsdh_cis_read(bus->sdh, 0x12, (uint8 *)arg + strlen(arg), SBSDIO_CIS_SIZE_LIMIT);
++		break;
++	}
++
++	case IOV_GVAL(IOV_FORCEEVEN):
++		int_val = (int32)forcealign;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_FORCEEVEN):
++		forcealign = bool_val;
++		break;
++
++	case IOV_GVAL(IOV_TXBOUND):
++		int_val = (int32)dhd_txbound;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_TXBOUND):
++		dhd_txbound = (uint)int_val;
++		break;
++
++	case IOV_GVAL(IOV_RXBOUND):
++		int_val = (int32)dhd_rxbound;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_RXBOUND):
++		dhd_rxbound = (uint)int_val;
++		break;
++
++	case IOV_GVAL(IOV_TXMINMAX):
++		int_val = (int32)dhd_txminmax;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_TXMINMAX):
++		dhd_txminmax = (uint)int_val;
++		break;
++
++	case IOV_GVAL(IOV_SERIALCONS):
++		int_val = dhd_serialconsole(bus, FALSE, 0, &bcmerror);
++		if (bcmerror != 0)
++			break;
++
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_SERIALCONS):
++		dhd_serialconsole(bus, TRUE, bool_val, &bcmerror);
++		break;
++
++
++#endif /* DHD_DEBUG */
++
++
++#ifdef SDTEST
++	case IOV_GVAL(IOV_EXTLOOP):
++		int_val = (int32)bus->ext_loop;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_EXTLOOP):
++		bus->ext_loop = bool_val;
++		break;
++
++	case IOV_GVAL(IOV_PKTGEN):
++		bcmerror = dhdsdio_pktgen_get(bus, arg);
++		break;
++
++	case IOV_SVAL(IOV_PKTGEN):
++		bcmerror = dhdsdio_pktgen_set(bus, arg);
++		break;
++#endif /* SDTEST */
++
++#if defined(USE_SDIOFIFO_IOVAR)
++	case IOV_GVAL(IOV_WATERMARK):
++		int_val = (int32)watermark;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_WATERMARK):
++		watermark = (uint)int_val;
++		watermark = (watermark > SBSDIO_WATERMARK_MASK) ? SBSDIO_WATERMARK_MASK : watermark;
++		DHD_ERROR(("Setting watermark as 0x%x.\n", watermark));
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK, (uint8)watermark, NULL);
++		break;
++
++	case IOV_GVAL(IOV_MESBUSYCTRL):
++		int_val = (int32)mesbusyctrl;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_MESBUSYCTRL):
++		mesbusyctrl = (uint)int_val;
++		mesbusyctrl = (mesbusyctrl > SBSDIO_MESBUSYCTRL_MASK)
++			? SBSDIO_MESBUSYCTRL_MASK : mesbusyctrl;
++		DHD_ERROR(("Setting mesbusyctrl as 0x%x.\n", mesbusyctrl));
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_MESBUSYCTRL,
++			((uint8)mesbusyctrl | 0x80), NULL);
++		break;
++#endif 
++
++
++	case IOV_GVAL(IOV_DONGLEISOLATION):
++		int_val = bus->dhd->dongle_isolation;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DONGLEISOLATION):
++		bus->dhd->dongle_isolation = bool_val;
++		break;
++
++	case IOV_SVAL(IOV_DEVRESET):
++		DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d busstate=%d\n",
++		           __FUNCTION__, bool_val, bus->dhd->dongle_reset,
++		           bus->dhd->busstate));
++
++		ASSERT(bus->dhd->osh);
++		/* ASSERT(bus->cl_devid); */
++
++		dhd_bus_devreset(bus->dhd, (uint8)bool_val);
++
++		break;
++	/*
++	 * softap firmware is updated through module parameter or android private command
++	 */
++
++	case IOV_GVAL(IOV_DEVRESET):
++		DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __FUNCTION__));
++
++		/* Get its status */
++		int_val = (bool) bus->dhd->dongle_reset;
++		bcopy(&int_val, arg, val_size);
++
++		break;
++
++	case IOV_GVAL(IOV_KSO):
++		int_val = dhdsdio_sleepcsr_get(bus);
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_DEVCAP):
++		int_val = dhdsdio_devcap_get(bus);
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_DEVCAP):
++		dhdsdio_devcap_set(bus, (uint8) int_val);
++		break;
++	case IOV_GVAL(IOV_TXGLOMSIZE):
++		int_val = (int32)bus->txglomsize;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_SVAL(IOV_TXGLOMSIZE):
++		if (int_val > SDPCM_MAXGLOM_SIZE) {
++			bcmerror = BCME_ERROR;
++		} else {
++			bus->txglomsize = (uint)int_val;
++		}
++		break;
++	case IOV_SVAL(IOV_HANGREPORT):
++		bus->dhd->hang_report = bool_val;
++		DHD_ERROR(("%s: Set hang_report as %d\n", __FUNCTION__, bus->dhd->hang_report));
++		break;
++
++	case IOV_GVAL(IOV_HANGREPORT):
++		int_val = (int32)bus->dhd->hang_report;
++		bcopy(&int_val, arg, val_size);
++		break;
++
++	case IOV_GVAL(IOV_TXINRX_THRES):
++		int_val = bus->txinrx_thres;
++		bcopy(&int_val, arg, val_size);
++		break;
++	case IOV_SVAL(IOV_TXINRX_THRES):
++		if (int_val < 0) {
++			bcmerror = BCME_BADARG;
++		} else {
++			bus->txinrx_thres = int_val;
++		}
++		break;
++
++	default:
++		bcmerror = BCME_UNSUPPORTED;
++		break;
++	}
++
++exit:
++	if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
++		bus->activity = FALSE;
++		dhdsdio_bussleep(bus, TRUE);
++		dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++	}
++
++	dhd_os_sdunlock(bus->dhd);
++
++	return bcmerror;
++}
++
++static int
++dhdsdio_write_vars(dhd_bus_t *bus)
++{
++	int bcmerror = 0;
++	uint32 varsize, phys_size;
++	uint32 varaddr;
++	uint8 *vbuffer;
++	uint32 varsizew;
++#ifdef DHD_DEBUG
++	uint8 *nvram_ularray;
++#endif /* DHD_DEBUG */
++
++	/* Even if there are no vars are to be written, we still need to set the ramsize. */
++	varsize = bus->varsz ? ROUNDUP(bus->varsz, 4) : 0;
++	varaddr = (bus->ramsize - 4) - varsize;
++
++	varaddr += bus->dongle_ram_base;
++
++	if (bus->vars) {
++		if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev == 7)) {
++			if (((varaddr & 0x3C) == 0x3C) && (varsize > 4)) {
++				DHD_ERROR(("PR85623WAR in place\n"));
++				varsize += 4;
++				varaddr -= 4;
++			}
++		}
++
++		vbuffer = (uint8 *)MALLOC(bus->dhd->osh, varsize);
++		if (!vbuffer)
++			return BCME_NOMEM;
++
++		bzero(vbuffer, varsize);
++		bcopy(bus->vars, vbuffer, bus->varsz);
++
++		/* Write the vars list */
++		bcmerror = dhdsdio_membytes(bus, TRUE, varaddr, vbuffer, varsize);
++#ifdef DHD_DEBUG
++		/* Verify NVRAM bytes */
++		DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
++		nvram_ularray = (uint8*)MALLOC(bus->dhd->osh, varsize);
++		if (!nvram_ularray)
++			return BCME_NOMEM;
++
++		/* Upload image to verify downloaded contents. */
++		memset(nvram_ularray, 0xaa, varsize);
++
++		/* Read the vars list to temp buffer for comparison */
++		bcmerror = dhdsdio_membytes(bus, FALSE, varaddr, nvram_ularray, varsize);
++		if (bcmerror) {
++				DHD_ERROR(("%s: error %d on reading %d nvram bytes at 0x%08x\n",
++					__FUNCTION__, bcmerror, varsize, varaddr));
++		}
++		/* Compare the org NVRAM with the one read from RAM */
++		if (memcmp(vbuffer, nvram_ularray, varsize)) {
++			DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n", __FUNCTION__));
++		} else
++			DHD_ERROR(("%s: Download, Upload and compare of NVRAM succeeded.\n",
++			__FUNCTION__));
++
++		MFREE(bus->dhd->osh, nvram_ularray, varsize);
++#endif /* DHD_DEBUG */
++
++		MFREE(bus->dhd->osh, vbuffer, varsize);
++	}
++
++	phys_size = REMAP_ENAB(bus) ? bus->ramsize : bus->orig_ramsize;
++
++	phys_size += bus->dongle_ram_base;
++
++	/* adjust to the user specified RAM */
++	DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
++		phys_size, bus->ramsize));
++	DHD_INFO(("Vars are at %d, orig varsize is %d\n",
++		varaddr, varsize));
++	varsize = ((phys_size - 4) - varaddr);
++
++	/*
++	 * Determine the length token:
++	 * Varsize, converted to words, in lower 16-bits, checksum in upper 16-bits.
++	 */
++	if (bcmerror) {
++		varsizew = 0;
++	} else {
++		varsizew = varsize / 4;
++		varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
++		varsizew = htol32(varsizew);
++	}
++
++	DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize, varsizew));
++
++	/* Write the length token to the last word */
++	bcmerror = dhdsdio_membytes(bus, TRUE, (phys_size - 4),
++		(uint8*)&varsizew, 4);
++
++	return bcmerror;
++}
++
++static int
++dhdsdio_download_state(dhd_bus_t *bus, bool enter)
++{
++	uint retries;
++	int bcmerror = 0;
++	int foundcr4 = 0;
++
++	if (!bus->sih)
++		return BCME_ERROR;
++	/* To enter download state, disable ARM and reset SOCRAM.
++	 * To exit download state, simply reset ARM (default is RAM boot).
++	 */
++	if (enter) {
++		bus->alp_only = TRUE;
++
++		if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
++		    !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
++			if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
++				foundcr4 = 1;
++			} else {
++				DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++		}
++
++		if (!foundcr4) {
++			si_core_disable(bus->sih, 0);
++			if (bcmsdh_regfail(bus->sdh)) {
++				bcmerror = BCME_SDIO_ERROR;
++				goto fail;
++			}
++
++			if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++
++			si_core_reset(bus->sih, 0, 0);
++			if (bcmsdh_regfail(bus->sdh)) {
++				DHD_ERROR(("%s: Failure trying reset SOCRAM core?\n",
++				           __FUNCTION__));
++				bcmerror = BCME_SDIO_ERROR;
++				goto fail;
++			}
++
++			/* Disable remap for download */
++			if (REMAP_ENAB(bus) && si_socdevram_remap_isenb(bus->sih))
++				dhdsdio_devram_remap(bus, FALSE);
++
++			if (CHIPID(bus->sih->chip) == BCM43430_CHIP_ID ||
++				CHIPID(bus->sih->chip) == BCM43018_CHIP_ID) {
++				/* Disabling Remap for SRAM_3 */
++				si_socram_set_bankpda(bus->sih, 0x3, 0x0);
++			}
++
++			/* Clear the top bit of memory */
++			if (bus->ramsize) {
++				uint32 zeros = 0;
++				if (dhdsdio_membytes(bus, TRUE, bus->ramsize - 4,
++				                     (uint8*)&zeros, 4) < 0) {
++					bcmerror = BCME_SDIO_ERROR;
++					goto fail;
++				}
++			}
++		} else {
++			/* For CR4,
++			 * Halt ARM
++			 * Remove ARM reset
++			 * Read RAM base address [0x18_0000]
++			 * [next] Download firmware
++			 * [done at else] Populate the reset vector
++			 * [done at else] Remove ARM halt
++			*/
++			/* Halt ARM & remove reset */
++			si_core_reset(bus->sih, SICF_CPUHALT, SICF_CPUHALT);
++		}
++	} else {
++		if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
++			if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++
++			if (!si_iscoreup(bus->sih)) {
++				DHD_ERROR(("%s: SOCRAM core is down after reset?\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++
++			if ((bcmerror = dhdsdio_write_vars(bus))) {
++				DHD_ERROR(("%s: could not write vars to RAM\n", __FUNCTION__));
++				goto fail;
++			}
++
++			/* Enable remap before ARM reset but after vars.
++			 * No backplane access in remap mode
++			 */
++			if (REMAP_ENAB(bus) && !si_socdevram_remap_isenb(bus->sih))
++				dhdsdio_devram_remap(bus, TRUE);
++
++			if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
++			    !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
++				DHD_ERROR(("%s: Can't change back to SDIO core?\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++			W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
++
++
++			if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
++			    !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++		} else {
++			/* cr4 has no socram, but tcm's */
++			/* write vars */
++			if ((bcmerror = dhdsdio_write_vars(bus))) {
++				DHD_ERROR(("%s: could not write vars to RAM\n", __FUNCTION__));
++				goto fail;
++			}
++
++			if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
++			    !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
++				DHD_ERROR(("%s: Can't change back to SDIO core?\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++			W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
++
++			/* switch back to arm core again */
++			if (!(si_setcore(bus->sih, ARMCR4_CORE_ID, 0))) {
++				DHD_ERROR(("%s: Failed to find ARM CR4 core!\n", __FUNCTION__));
++				bcmerror = BCME_ERROR;
++				goto fail;
++			}
++			/* write address 0 with reset instruction */
++			bcmerror = dhdsdio_membytes(bus, TRUE, 0,
++				(uint8 *)&bus->resetinstr, sizeof(bus->resetinstr));
++
++			if (bcmerror == BCME_OK) {
++				uint32 tmp;
++
++				/* verify write */
++				bcmerror = dhdsdio_membytes(bus, FALSE, 0,
++				                            (uint8 *)&tmp, sizeof(tmp));
++
++				if (bcmerror == BCME_OK && tmp != bus->resetinstr) {
++					DHD_ERROR(("%s: Failed to write 0x%08x to addr 0\n",
++					          __FUNCTION__, bus->resetinstr));
++					DHD_ERROR(("%s: contents of addr 0 is 0x%08x\n",
++					          __FUNCTION__, tmp));
++					bcmerror = BCME_SDIO_ERROR;
++					goto fail;
++				}
++			}
++
++			/* now remove reset and halt and continue to run CR4 */
++		}
++
++		si_core_reset(bus->sih, 0, 0);
++		if (bcmsdh_regfail(bus->sdh)) {
++			DHD_ERROR(("%s: Failure trying to reset ARM core?\n", __FUNCTION__));
++			bcmerror = BCME_SDIO_ERROR;
++			goto fail;
++		}
++
++		/* Allow HT Clock now that the ARM is running. */
++		bus->alp_only = FALSE;
++
++		bus->dhd->busstate = DHD_BUS_LOAD;
++	}
++
++fail:
++	/* Always return to SDIOD core */
++	if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0))
++		si_setcore(bus->sih, SDIOD_CORE_ID, 0);
++
++	return bcmerror;
++}
++
++int
++dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
++                 void *params, int plen, void *arg, int len, bool set)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	const bcm_iovar_t *vi = NULL;
++	int bcmerror = 0;
++	int val_size;
++	uint32 actionid;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	ASSERT(name);
++	ASSERT(len >= 0);
++
++	/* Get MUST have return space */
++	ASSERT(set || (arg && len));
++
++	/* Set does NOT take qualifiers */
++	ASSERT(!set || (!params && !plen));
++
++	/* Look up var locally; if not found pass to host driver */
++	if ((vi = bcm_iovar_lookup(dhdsdio_iovars, name)) == NULL) {
++		dhd_os_sdlock(bus->dhd);
++
++		BUS_WAKE(bus);
++
++		/* Turn on clock in case SD command needs backplane */
++		dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++		bcmerror = bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len, set);
++
++		/* Check for bus configuration changes of interest */
++
++		/* If it was divisor change, read the new one */
++		if (set && strcmp(name, "sd_divisor") == 0) {
++			if (bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
++			                    &bus->sd_divisor, sizeof(int32), FALSE) != BCME_OK) {
++				bus->sd_divisor = -1;
++				DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, name));
++			} else {
++				DHD_INFO(("%s: noted %s update, value now %d\n",
++				          __FUNCTION__, name, bus->sd_divisor));
++			}
++		}
++		/* If it was a mode change, read the new one */
++		if (set && strcmp(name, "sd_mode") == 0) {
++			if (bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
++			                    &bus->sd_mode, sizeof(int32), FALSE) != BCME_OK) {
++				bus->sd_mode = -1;
++				DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, name));
++			} else {
++				DHD_INFO(("%s: noted %s update, value now %d\n",
++				          __FUNCTION__, name, bus->sd_mode));
++			}
++		}
++		/* Similar check for blocksize change */
++		if (set && strcmp(name, "sd_blocksize") == 0) {
++			int32 fnum = 2;
++			if (bcmsdh_iovar_op(bus->sdh, "sd_blocksize", &fnum, sizeof(int32),
++			                    &bus->blocksize, sizeof(int32), FALSE) != BCME_OK) {
++				bus->blocksize = 0;
++				DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_blocksize"));
++			} else {
++				DHD_INFO(("%s: noted %s update, value now %d\n",
++				          __FUNCTION__, "sd_blocksize", bus->blocksize));
++
++				dhdsdio_tune_fifoparam(bus);
++			}
++		}
++		bus->roundup = MIN(max_roundup, bus->blocksize);
++
++		if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
++			bus->activity = FALSE;
++			dhdsdio_bussleep(bus, TRUE);
++			dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++		}
++
++		dhd_os_sdunlock(bus->dhd);
++		goto exit;
++	}
++
++	DHD_CTL(("%s: %s %s, len %d plen %d\n", __FUNCTION__,
++	         name, (set ? "set" : "get"), len, plen));
++
++	/* set up 'params' pointer in case this is a set command so that
++	 * the convenience int and bool code can be common to set and get
++	 */
++	if (params == NULL) {
++		params = arg;
++		plen = len;
++	}
++
++	if (vi->type == IOVT_VOID)
++		val_size = 0;
++	else if (vi->type == IOVT_BUFFER)
++		val_size = len;
++	else
++		/* all other types are integer sized */
++		val_size = sizeof(int);
++
++	actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
++	bcmerror = dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len, val_size);
++
++exit:
++	return bcmerror;
++}
++
++void
++dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
++{
++	osl_t *osh;
++	uint32 local_hostintmask;
++	uint8 saveclk;
++	uint retries;
++	int err;
++	bool wlfc_enabled = FALSE;
++	unsigned long flags;
++
++	if (!bus->dhd)
++		return;
++
++	osh = bus->dhd->osh;
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	bcmsdh_waitlockfree(bus->sdh);
++
++	if (enforce_mutex)
++		dhd_os_sdlock(bus->dhd);
++
++	if ((bus->dhd->busstate == DHD_BUS_DOWN) || bus->dhd->hang_was_sent) {
++		/* if Firmware already hangs disbale any interrupt */
++		bus->dhd->busstate = DHD_BUS_DOWN;
++		bus->hostintmask = 0;
++		bcmsdh_intr_disable(bus->sdh);
++	} else {
++
++		BUS_WAKE(bus);
++
++		if (KSO_ENAB(bus)) {
++
++		/* Enable clock for device interrupts */
++		dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++		/* Disable and clear interrupts at the chip level also */
++		W_SDREG(0, &bus->regs->hostintmask, retries);
++		local_hostintmask = bus->hostintmask;
++		bus->hostintmask = 0;
++
++		/* Change our idea of bus state */
++		DHD_GENERAL_LOCK(bus->dhd, flags);
++		bus->dhd->busstate = DHD_BUS_DOWN;
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++		/* Force clocks on backplane to be sure F2 interrupt propagates */
++		saveclk = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
++		if (!err) {
++			bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
++			                 (saveclk | SBSDIO_FORCE_HT), &err);
++		}
++		if (err) {
++			DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
++			            __FUNCTION__, err));
++		}
++
++		/* Turn off the bus (F2), free any pending packets */
++		DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__));
++		bcmsdh_intr_disable(bus->sdh);
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1, NULL);
++
++		/* Clear any pending interrupts now that F2 is disabled */
++		W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
++		}
++
++		/* Turn off the backplane clock (only) */
++		dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++	}
++
++#ifdef PROP_TXSTATUS
++	wlfc_enabled = (dhd_wlfc_cleanup_txq(bus->dhd, NULL, 0) != WLFC_UNSUPPORTED);
++#endif
++	if (!wlfc_enabled) {
++#ifdef DHDTCPACK_SUPPRESS
++		/* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt,
++		 * when there is a newly coming packet from network stack.
++		 */
++		dhd_tcpack_info_tbl_clean(bus->dhd);
++#endif /* DHDTCPACK_SUPPRESS */
++		/* Clear the data packet queues */
++		pktq_flush(osh, &bus->txq, TRUE, NULL, 0);
++	}
++
++	/* Clear any held glomming stuff */
++	if (bus->glomd)
++		PKTFREE(osh, bus->glomd, FALSE);
++
++	if (bus->glom)
++		PKTFREE(osh, bus->glom, FALSE);
++
++	bus->glom = bus->glomd = NULL;
++
++	/* Clear rx control and wake any waiters */
++	bus->rxlen = 0;
++	dhd_os_ioctl_resp_wake(bus->dhd);
++
++	/* Reset some F2 state stuff */
++	bus->rxskip = FALSE;
++	bus->tx_seq = bus->rx_seq = 0;
++
++	bus->tx_max = 4;
++
++	if (enforce_mutex)
++		dhd_os_sdunlock(bus->dhd);
++}
++
++#if defined(BCMSDIOH_TXGLOM) && (defined(BCMSDIOH_STD) || defined(BCMLXSDMMC))
++extern uint sd_txglom;
++#endif
++void
++dhd_txglom_enable(dhd_pub_t *dhdp, bool enable)
++{
++	/* can't enable host txglom by default, some platforms have no
++	 * (or crappy) ADMA support and txglom will cause kernel assertions (e.g.
++	 * panda board)
++	 */
++	dhd_bus_t *bus = dhdp->bus;
++#ifdef BCMSDIOH_TXGLOM
++	uint32 rxglom;
++	int32 ret;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++#if defined(BCMSDIOH_STD) || defined(BCMLXSDMMC)
++	if (enable)
++		enable = sd_txglom;
++#endif /* defined(BCMSDIOH_STD) || defined(BCMLXSDMMC) */
++
++	if (enable) {
++		rxglom = 1;
++		ret = dhd_iovar(dhdp, 0, "bus:rxglom", (char *)&rxglom, sizeof(rxglom), NULL, 0,
++			TRUE);
++		if (ret >= 0)
++			bus->txglom_enable = TRUE;
++		else {
++#if defined(BCMSDIOH_STD) || defined(BCMLXSDMMC)
++			sd_txglom = 0;
++#endif /* defined(BCMSDIOH_STD) || defined(BCMLXSDMMC) */
++			bus->txglom_enable = FALSE;
++		}
++	} else
++#endif /* BCMSDIOH_TXGLOM */
++		bus->txglom_enable = FALSE;
++}
++
++int
++dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	dhd_timeout_t tmo;
++	uint retries = 0;
++	uint8 ready, enable;
++	int err, ret = 0;
++	uint8 saveclk;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	ASSERT(bus->dhd);
++	if (!bus->dhd)
++		return 0;
++
++	if (enforce_mutex)
++		dhd_os_sdlock(bus->dhd);
++
++	/* Make sure backplane clock is on, needed to generate F2 interrupt */
++	dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++	if (bus->clkstate != CLK_AVAIL) {
++		DHD_ERROR(("%s: clock state is wrong. state = %d\n", __FUNCTION__, bus->clkstate));
++		ret = -1;
++		goto exit;
++	}
++
++	/* Force clocks on backplane to be sure F2 interrupt propagates */
++	saveclk = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
++
++	if (!err) {
++		if (bus->sih->chip == BCM43012_CHIP_ID) {
++			bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
++				(saveclk | SBSDIO_HT_AVAIL_REQ), &err);
++		} else {
++			bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
++				(saveclk | SBSDIO_FORCE_HT), &err);
++		}
++	}
++
++	if (err) {
++		DHD_ERROR(("%s: Failed to force clock for F2: err %d\n", __FUNCTION__, err));
++		ret = -1;
++		goto exit;
++	}
++
++	/* Enable function 2 (frame transfers) */
++	W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
++	        &bus->regs->tosbmailboxdata, retries);
++	enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
++
++	bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
++
++	/* Give the dongle some time to do its thing and set IOR2 */
++	dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
++
++	ready = 0;
++	while (ready != enable && !dhd_timeout_expired(&tmo))
++	        ready = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY, NULL);
++
++	DHD_ERROR(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
++	          __FUNCTION__, enable, ready, tmo.elapsed));
++
++
++	/* If F2 successfully enabled, set core and enable interrupts */
++	if (ready == enable) {
++		/* Make sure we're talking to the core. */
++		if (!(bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0)))
++			bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
++		ASSERT(bus->regs != NULL);
++
++		/* Set up the interrupt mask and enable interrupts */
++		bus->hostintmask = HOSTINTMASK;
++		/* corerev 4 could use the newer interrupt logic to detect the frames */
++		if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev == 4) &&
++			(bus->rxint_mode != SDIO_DEVICE_HMB_RXINT)) {
++			bus->hostintmask &= ~I_HMB_FRAME_IND;
++			bus->hostintmask |= I_XMTDATA_AVAIL;
++		}
++		W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
++
++		if (bus->sih->buscorerev < 15) {
++			bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
++				(uint8)watermark, &err);
++		}
++
++		/* Set bus state according to enable result */
++		dhdp->busstate = DHD_BUS_DATA;
++
++		/* Need to set fn2 block size to match fn1 block size.
++		 * Requests to fn2 go thru fn1. *
++		 * faltwig has this code contitioned with #if !BCMSPI_ANDROID.
++		 * It would be cleaner to use the ->sdh->block_sz[fno] instead of
++		 * 64, but this layer has no access to sdh types.
++		 */
++
++		/* bcmsdh_intr_unmask(bus->sdh); */
++
++		bus->intdis = FALSE;
++		if (bus->intr) {
++			DHD_INTR(("%s: enable SDIO device interrupts\n", __FUNCTION__));
++			bcmsdh_intr_enable(bus->sdh);
++		} else {
++			DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__));
++			bcmsdh_intr_disable(bus->sdh);
++		}
++
++	}
++
++
++	else {
++		/* Disable F2 again */
++		enable = SDIO_FUNC_ENABLE_1;
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
++	}
++
++	if (dhdsdio_sr_cap(bus)) {
++		dhdsdio_sr_init(bus);
++		/* Masking the chip active interrupt  permanantly */
++		bus->hostintmask &= ~I_CHIPACTIVE;
++		W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
++		DHD_INFO(("%s: disable I_CHIPACTIVE in hostintmask[0x%08x]\n",
++		__FUNCTION__, bus->hostintmask));
++	}
++	else
++		bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
++			SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
++
++	/* If we didn't come up, turn off backplane clock */
++	if (dhdp->busstate != DHD_BUS_DATA)
++		dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++
++exit:
++	if (enforce_mutex)
++		dhd_os_sdunlock(bus->dhd);
++
++	return ret;
++}
++
++static void
++dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
++{
++	bcmsdh_info_t *sdh = bus->sdh;
++	sdpcmd_regs_t *regs = bus->regs;
++	uint retries = 0;
++	uint16 lastrbc;
++	uint8 hi, lo;
++	int err;
++
++	DHD_ERROR(("%s: %sterminate frame%s\n", __FUNCTION__,
++	           (abort ? "abort command, " : ""), (rtx ? ", send NAK" : "")));
++
++	if (!KSO_ENAB(bus)) {
++		DHD_ERROR(("%s: Device asleep\n", __FUNCTION__));
++		return;
++	}
++
++	if (abort) {
++		bcmsdh_abort(sdh, SDIO_FUNC_2);
++	}
++
++	bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM, &err);
++	if (err) {
++		DHD_ERROR(("%s: SBSDIO_FUNC1_FRAMECTRL cmd err\n", __FUNCTION__));
++		goto fail;
++	}
++	bus->f1regdata++;
++
++	/* Wait until the packet has been flushed (device/FIFO stable) */
++	for (lastrbc = retries = 0xffff; retries > 0; retries--) {
++		hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI, NULL);
++		lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO, &err);
++		if (err) {
++			DHD_ERROR(("%s: SBSDIO_FUNC1_RFAMEBCLO cmd err\n", __FUNCTION__));
++			goto fail;
++		}
++
++		bus->f1regdata += 2;
++
++		if ((hi == 0) && (lo == 0))
++			break;
++
++		if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
++			DHD_ERROR(("%s: count growing: last 0x%04x now 0x%04x\n",
++			           __FUNCTION__, lastrbc, ((hi << 8) + lo)));
++		}
++		lastrbc = (hi << 8) + lo;
++	}
++
++	if (!retries) {
++		DHD_ERROR(("%s: count never zeroed: last 0x%04x\n", __FUNCTION__, lastrbc));
++	} else {
++		DHD_INFO(("%s: flush took %d iterations\n", __FUNCTION__, (0xffff - retries)));
++	}
++
++	if (rtx) {
++		bus->rxrtx++;
++		W_SDREG(SMB_NAK, &regs->tosbmailbox, retries);
++		bus->f1regdata++;
++		if (retries <= retry_limit) {
++			bus->rxskip = TRUE;
++		}
++	}
++
++	/* Clear partial in any case */
++	bus->nextlen = 0;
++
++fail:
++	/* If we can't reach the device, signal failure */
++	if (err || bcmsdh_regfail(sdh))
++		bus->dhd->busstate = DHD_BUS_DOWN;
++}
++
++static void
++dhdsdio_read_control(dhd_bus_t *bus, uint8 *hdr, uint len, uint doff)
++{
++	bcmsdh_info_t *sdh = bus->sdh;
++	uint rdlen, pad;
++
++	int sdret;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	/* Control data already received in aligned rxctl */
++	if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
++		goto gotpkt;
++
++	ASSERT(bus->rxbuf);
++	/* Set rxctl for frame (w/optional alignment) */
++	bus->rxctl = bus->rxbuf;
++	if (dhd_alignctl) {
++		bus->rxctl += firstread;
++		if ((pad = ((uintptr)bus->rxctl % DHD_SDALIGN)))
++			bus->rxctl += (DHD_SDALIGN - pad);
++		bus->rxctl -= firstread;
++	}
++	ASSERT(bus->rxctl >= bus->rxbuf);
++
++	/* Copy the already-read portion over */
++	bcopy(hdr, bus->rxctl, firstread);
++	if (len <= firstread)
++		goto gotpkt;
++
++	/* Copy the full data pkt in gSPI case and process ioctl. */
++	if (bus->bus == SPI_BUS) {
++		bcopy(hdr, bus->rxctl, len);
++		goto gotpkt;
++	}
++
++	/* Raise rdlen to next SDIO block to avoid tail command */
++	rdlen = len - firstread;
++	if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
++		pad = bus->blocksize - (rdlen % bus->blocksize);
++		if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
++		    ((len + pad) < bus->dhd->maxctl))
++			rdlen += pad;
++	} else if (rdlen % DHD_SDALIGN) {
++		rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
++	}
++
++	/* Satisfy length-alignment requirements */
++	if (forcealign && (rdlen & (ALIGNMENT - 1)))
++		rdlen = ROUNDUP(rdlen, ALIGNMENT);
++
++	/* Drop if the read is too big or it exceeds our maximum */
++	if ((rdlen + firstread) > bus->dhd->maxctl) {
++		DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
++		           __FUNCTION__, rdlen, bus->dhd->maxctl));
++		bus->dhd->rx_errors++;
++		dhdsdio_rxfail(bus, FALSE, FALSE);
++		goto done;
++	}
++
++	if ((len - doff) > bus->dhd->maxctl) {
++		DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
++		           __FUNCTION__, len, (len - doff), bus->dhd->maxctl));
++		bus->dhd->rx_errors++; bus->rx_toolong++;
++		dhdsdio_rxfail(bus, FALSE, FALSE);
++		goto done;
++	}
++
++
++	/* Read remainder of frame body into the rxctl buffer */
++	sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
++	                            (bus->rxctl + firstread), rdlen, NULL, NULL, NULL);
++	bus->f2rxdata++;
++	ASSERT(sdret != BCME_PENDING);
++
++	/* Control frame failures need retransmission */
++	if (sdret < 0) {
++		DHD_ERROR(("%s: read %d control bytes failed: %d\n", __FUNCTION__, rdlen, sdret));
++		bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
++		dhdsdio_rxfail(bus, TRUE, TRUE);
++		goto done;
++	}
++
++gotpkt:
++
++#ifdef DHD_DEBUG
++	if (DHD_BYTES_ON() && DHD_CTL_ON()) {
++		prhex("RxCtrl", bus->rxctl, len);
++	}
++#endif
++
++	/* Point to valid data and indicate its length */
++	bus->rxctl += doff;
++	bus->rxlen = len - doff;
++
++done:
++	/* Awake any waiters */
++	dhd_os_ioctl_resp_wake(bus->dhd);
++}
++int
++dhd_process_pkt_reorder_info(dhd_pub_t *dhd, uchar *reorder_info_buf, uint reorder_info_len,
++	void **pkt, uint32 *pkt_count);
++
++static uint8
++dhdsdio_rxglom(dhd_bus_t *bus, uint8 rxseq)
++{
++	uint16 dlen, totlen;
++	uint8 *dptr, num = 0;
++
++	uint16 sublen, check;
++	void *pfirst, *plast, *pnext;
++	void * list_tail[DHD_MAX_IFS] = { NULL };
++	void * list_head[DHD_MAX_IFS] = { NULL };
++	uint8 idx;
++	osl_t *osh = bus->dhd->osh;
++
++	int errcode;
++	uint8 chan, seq, doff, sfdoff;
++	uint8 txmax;
++	uchar reorder_info_buf[WLHOST_REORDERDATA_TOTLEN];
++	uint reorder_info_len;
++
++	int ifidx = 0;
++	bool usechain = bus->use_rxchain;
++
++	/* If packets, issue read(s) and send up packet chain */
++	/* Return sequence numbers consumed? */
++
++	DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd, bus->glom));
++
++	/* If there's a descriptor, generate the packet chain */
++	if (bus->glomd) {
++		dhd_os_sdlock_rxq(bus->dhd);
++
++		pfirst = plast = pnext = NULL;
++		dlen = (uint16)PKTLEN(osh, bus->glomd);
++		dptr = PKTDATA(osh, bus->glomd);
++		if (!dlen || (dlen & 1)) {
++			DHD_ERROR(("%s: bad glomd len (%d), ignore descriptor\n",
++			           __FUNCTION__, dlen));
++			dlen = 0;
++		}
++
++		for (totlen = num = 0; dlen; num++) {
++			/* Get (and move past) next length */
++			sublen = ltoh16_ua(dptr);
++			dlen -= sizeof(uint16);
++			dptr += sizeof(uint16);
++			if ((sublen < SDPCM_HDRLEN) ||
++			    ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
++				DHD_ERROR(("%s: descriptor len %d bad: %d\n",
++				           __FUNCTION__, num, sublen));
++				pnext = NULL;
++				break;
++			}
++			if (sublen % DHD_SDALIGN) {
++				DHD_ERROR(("%s: sublen %d not a multiple of %d\n",
++				           __FUNCTION__, sublen, DHD_SDALIGN));
++				usechain = FALSE;
++			}
++			totlen += sublen;
++
++			/* For last frame, adjust read len so total is a block multiple */
++			if (!dlen) {
++				sublen += (ROUNDUP(totlen, bus->blocksize) - totlen);
++				totlen = ROUNDUP(totlen, bus->blocksize);
++			}
++
++			/* Allocate/chain packet for next subframe */
++			if ((pnext = PKTGET(osh, sublen + DHD_SDALIGN, FALSE)) == NULL) {
++				DHD_ERROR(("%s: PKTGET failed, num %d len %d\n",
++				           __FUNCTION__, num, sublen));
++				break;
++			}
++			ASSERT(!PKTLINK(pnext));
++			if (!pfirst) {
++				ASSERT(!plast);
++				pfirst = plast = pnext;
++			} else {
++				ASSERT(plast);
++				PKTSETNEXT(osh, plast, pnext);
++				plast = pnext;
++			}
++
++			/* Adhere to start alignment requirements */
++			PKTALIGN(osh, pnext, sublen, DHD_SDALIGN);
++		}
++
++		/* If all allocations succeeded, save packet chain in bus structure */
++		if (pnext) {
++			DHD_GLOM(("%s: allocated %d-byte packet chain for %d subframes\n",
++			          __FUNCTION__, totlen, num));
++			if (DHD_GLOM_ON() && bus->nextlen) {
++				if (totlen != bus->nextlen) {
++					DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d "
++					          "rxseq %d\n", __FUNCTION__, bus->nextlen,
++					          totlen, rxseq));
++				}
++			}
++			bus->glom = pfirst;
++			pfirst = pnext = NULL;
++		} else {
++			if (pfirst)
++				PKTFREE(osh, pfirst, FALSE);
++			bus->glom = NULL;
++			num = 0;
++		}
++
++		/* Done with descriptor packet */
++		PKTFREE(osh, bus->glomd, FALSE);
++		bus->glomd = NULL;
++		bus->nextlen = 0;
++
++		dhd_os_sdunlock_rxq(bus->dhd);
++	}
++
++	/* Ok -- either we just generated a packet chain, or had one from before */
++	if (bus->glom) {
++		if (DHD_GLOM_ON()) {
++			DHD_GLOM(("%s: attempt superframe read, packet chain:\n", __FUNCTION__));
++			for (pnext = bus->glom; pnext; pnext = PKTNEXT(osh, pnext)) {
++				DHD_GLOM(("    %p: %p len 0x%04x (%d)\n",
++				          pnext, (uint8*)PKTDATA(osh, pnext),
++				          PKTLEN(osh, pnext), PKTLEN(osh, pnext)));
++			}
++		}
++
++		pfirst = bus->glom;
++		dlen = (uint16)pkttotlen(osh, pfirst);
++
++		/* Do an SDIO read for the superframe.  Configurable iovar to
++		 * read directly into the chained packet, or allocate a large
++		 * packet and and copy into the chain.
++		 */
++		if (usechain) {
++			errcode = dhd_bcmsdh_recv_buf(bus,
++			                              bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
++			                              F2SYNC, (uint8*)PKTDATA(osh, pfirst),
++			                              dlen, pfirst, NULL, NULL);
++		} else if (bus->dataptr) {
++			errcode = dhd_bcmsdh_recv_buf(bus,
++			                              bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
++			                              F2SYNC, bus->dataptr,
++			                              dlen, NULL, NULL, NULL);
++			sublen = (uint16)pktfrombuf(osh, pfirst, 0, dlen, bus->dataptr);
++			if (sublen != dlen) {
++				DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
++				           __FUNCTION__, dlen, sublen));
++				errcode = -1;
++			}
++			pnext = NULL;
++		} else {
++			DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n", dlen));
++			errcode = -1;
++		}
++		bus->f2rxdata++;
++		ASSERT(errcode != BCME_PENDING);
++
++		/* On failure, kill the superframe, allow a couple retries */
++		if (errcode < 0) {
++			DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
++			           __FUNCTION__, dlen, errcode));
++			bus->dhd->rx_errors++;
++
++			if (bus->glomerr++ < 3) {
++				dhdsdio_rxfail(bus, TRUE, TRUE);
++			} else {
++				bus->glomerr = 0;
++				dhdsdio_rxfail(bus, TRUE, FALSE);
++				dhd_os_sdlock_rxq(bus->dhd);
++				PKTFREE(osh, bus->glom, FALSE);
++				dhd_os_sdunlock_rxq(bus->dhd);
++				bus->rxglomfail++;
++				bus->glom = NULL;
++			}
++			return 0;
++		}
++
++#ifdef DHD_DEBUG
++		if (DHD_GLOM_ON()) {
++			prhex("SUPERFRAME", PKTDATA(osh, pfirst),
++			      MIN(PKTLEN(osh, pfirst), 48));
++		}
++#endif
++
++
++		/* Validate the superframe header */
++		dptr = (uint8 *)PKTDATA(osh, pfirst);
++		sublen = ltoh16_ua(dptr);
++		check = ltoh16_ua(dptr + sizeof(uint16));
++
++		chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
++		seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
++		bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
++		if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
++			DHD_INFO(("%s: got frame w/nextlen too large (%d) seq %d\n",
++			          __FUNCTION__, bus->nextlen, seq));
++			bus->nextlen = 0;
++		}
++		doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
++		txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
++
++		errcode = 0;
++		if ((uint16)~(sublen^check)) {
++			DHD_ERROR(("%s (superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
++			           __FUNCTION__, sublen, check));
++			errcode = -1;
++		} else if (ROUNDUP(sublen, bus->blocksize) != dlen) {
++			DHD_ERROR(("%s (superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
++			           __FUNCTION__, sublen, ROUNDUP(sublen, bus->blocksize), dlen));
++			errcode = -1;
++		} else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) != SDPCM_GLOM_CHANNEL) {
++			DHD_ERROR(("%s (superframe): bad channel %d\n", __FUNCTION__,
++			           SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN])));
++			errcode = -1;
++		} else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
++			DHD_ERROR(("%s (superframe): got second descriptor?\n", __FUNCTION__));
++			errcode = -1;
++		} else if ((doff < SDPCM_HDRLEN) ||
++		           (doff > (PKTLEN(osh, pfirst) - SDPCM_HDRLEN))) {
++			DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d pkt %d min %d\n",
++				__FUNCTION__, doff, sublen, PKTLEN(osh, pfirst),
++				SDPCM_HDRLEN));
++			errcode = -1;
++		}
++
++		/* Check sequence number of superframe SW header */
++		if (rxseq != seq) {
++			DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
++			          __FUNCTION__, seq, rxseq));
++			bus->rx_badseq++;
++			rxseq = seq;
++		}
++
++		/* Check window for sanity */
++		if ((uint8)(txmax - bus->tx_seq) > 0x70) {
++			DHD_ERROR(("%s: got unlikely tx max %d with tx_seq %d\n",
++			           __FUNCTION__, txmax, bus->tx_seq));
++			txmax = bus->tx_max;
++		}
++		bus->tx_max = txmax;
++
++		/* Remove superframe header, remember offset */
++		PKTPULL(osh, pfirst, doff);
++		sfdoff = doff;
++
++		/* Validate all the subframe headers */
++		for (num = 0, pnext = pfirst; pnext && !errcode;
++		     num++, pnext = PKTNEXT(osh, pnext)) {
++			dptr = (uint8 *)PKTDATA(osh, pnext);
++			dlen = (uint16)PKTLEN(osh, pnext);
++			sublen = ltoh16_ua(dptr);
++			check = ltoh16_ua(dptr + sizeof(uint16));
++			chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
++			doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
++#ifdef DHD_DEBUG
++			if (DHD_GLOM_ON()) {
++				prhex("subframe", dptr, 32);
++			}
++#endif
++
++			if ((uint16)~(sublen^check)) {
++				DHD_ERROR(("%s (subframe %d): HW hdr error: "
++				           "len/check 0x%04x/0x%04x\n",
++				           __FUNCTION__, num, sublen, check));
++				errcode = -1;
++			} else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
++				DHD_ERROR(("%s (subframe %d): length mismatch: "
++				           "len 0x%04x, expect 0x%04x\n",
++				           __FUNCTION__, num, sublen, dlen));
++				errcode = -1;
++			} else if ((chan != SDPCM_DATA_CHANNEL) &&
++			           (chan != SDPCM_EVENT_CHANNEL)) {
++				DHD_ERROR(("%s (subframe %d): bad channel %d\n",
++				           __FUNCTION__, num, chan));
++				errcode = -1;
++			} else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
++				DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
++				           __FUNCTION__, num, doff, sublen, SDPCM_HDRLEN));
++				errcode = -1;
++			}
++		}
++
++		if (errcode) {
++			/* Terminate frame on error, request a couple retries */
++			if (bus->glomerr++ < 3) {
++				/* Restore superframe header space */
++				PKTPUSH(osh, pfirst, sfdoff);
++				dhdsdio_rxfail(bus, TRUE, TRUE);
++			} else {
++				bus->glomerr = 0;
++				dhdsdio_rxfail(bus, TRUE, FALSE);
++				dhd_os_sdlock_rxq(bus->dhd);
++				PKTFREE(osh, bus->glom, FALSE);
++				dhd_os_sdunlock_rxq(bus->dhd);
++				bus->rxglomfail++;
++				bus->glom = NULL;
++			}
++			bus->nextlen = 0;
++			return 0;
++		}
++
++		/* Basic SD framing looks ok - process each packet (header) */
++		bus->glom = NULL;
++		plast = NULL;
++
++		dhd_os_sdlock_rxq(bus->dhd);
++		for (num = 0; pfirst; rxseq++, pfirst = pnext) {
++			pnext = PKTNEXT(osh, pfirst);
++			PKTSETNEXT(osh, pfirst, NULL);
++
++			dptr = (uint8 *)PKTDATA(osh, pfirst);
++			sublen = ltoh16_ua(dptr);
++			chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
++			seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
++			doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
++
++			DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
++			          __FUNCTION__, num, pfirst, PKTDATA(osh, pfirst),
++			          PKTLEN(osh, pfirst), sublen, chan, seq));
++
++			ASSERT((chan == SDPCM_DATA_CHANNEL) || (chan == SDPCM_EVENT_CHANNEL));
++
++			if (rxseq != seq) {
++				DHD_GLOM(("%s: rx_seq %d, expected %d\n",
++				          __FUNCTION__, seq, rxseq));
++				bus->rx_badseq++;
++				rxseq = seq;
++			}
++
++#ifdef DHD_DEBUG
++			if (DHD_BYTES_ON() && DHD_DATA_ON()) {
++				prhex("Rx Subframe Data", dptr, dlen);
++			}
++#endif
++
++			PKTSETLEN(osh, pfirst, sublen);
++			PKTPULL(osh, pfirst, doff);
++
++			reorder_info_len = sizeof(reorder_info_buf);
++
++			if (PKTLEN(osh, pfirst) == 0) {
++				PKTFREE(bus->dhd->osh, pfirst, FALSE);
++				continue;
++			} else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst, reorder_info_buf,
++				&reorder_info_len) != 0) {
++				DHD_ERROR(("%s: rx protocol error\n", __FUNCTION__));
++				bus->dhd->rx_errors++;
++				PKTFREE(osh, pfirst, FALSE);
++				continue;
++			}
++			if (reorder_info_len) {
++				uint32 free_buf_count;
++				void *ppfirst;
++
++				ppfirst = pfirst;
++				/* Reordering info from the firmware */
++				dhd_process_pkt_reorder_info(bus->dhd, reorder_info_buf,
++					reorder_info_len, &ppfirst, &free_buf_count);
++
++				if (free_buf_count == 0) {
++					continue;
++				}
++				else {
++					void *temp;
++
++					/*  go to the end of the chain and attach the pnext there */
++					temp = ppfirst;
++					while (PKTNEXT(osh, temp) != NULL) {
++						temp = PKTNEXT(osh, temp);
++					}
++					pfirst = temp;
++					if (list_tail[ifidx] == NULL)
++						list_head[ifidx] = ppfirst;
++					else
++						PKTSETNEXT(osh, list_tail[ifidx], ppfirst);
++					list_tail[ifidx] = pfirst;
++				}
++
++				num += (uint8)free_buf_count;
++			}
++			else {
++				/* this packet will go up, link back into chain and count it */
++
++				if (list_tail[ifidx] == NULL) {
++					list_head[ifidx] = list_tail[ifidx] = pfirst;
++				}
++				else {
++					PKTSETNEXT(osh, list_tail[ifidx], pfirst);
++					list_tail[ifidx] = pfirst;
++				}
++				num++;
++			}
++#ifdef DHD_DEBUG
++			if (DHD_GLOM_ON()) {
++				DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) nxt/lnk %p/%p\n",
++				          __FUNCTION__, num, pfirst,
++				          PKTDATA(osh, pfirst), PKTLEN(osh, pfirst),
++				          PKTNEXT(osh, pfirst), PKTLINK(pfirst)));
++				prhex("", (uint8 *)PKTDATA(osh, pfirst),
++				      MIN(PKTLEN(osh, pfirst), 32));
++			}
++#endif /* DHD_DEBUG */
++		}
++		dhd_os_sdunlock_rxq(bus->dhd);
++
++		for (idx = 0; idx < DHD_MAX_IFS; idx++) {
++			if (list_head[idx]) {
++				void *temp;
++				uint8 cnt = 0;
++				temp = list_head[idx];
++				do {
++					temp = PKTNEXT(osh, temp);
++					cnt++;
++				} while (temp);
++				if (cnt) {
++					dhd_os_sdunlock(bus->dhd);
++					dhd_rx_frame(bus->dhd, idx, list_head[idx], cnt, 0);
++					dhd_os_sdlock(bus->dhd);
++				}
++			}
++		}
++		bus->rxglomframes++;
++		bus->rxglompkts += num;
++	}
++	return num;
++}
++
++
++/* Return TRUE if there may be more frames to read */
++static uint
++dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
++{
++	osl_t *osh = bus->dhd->osh;
++	bcmsdh_info_t *sdh = bus->sdh;
++
++	uint16 len, check;	/* Extracted hardware header fields */
++	uint8 chan, seq, doff;	/* Extracted software header fields */
++	uint8 fcbits;		/* Extracted fcbits from software header */
++	uint8 delta;
++
++	void *pkt;	/* Packet for event or data frames */
++	uint16 pad;	/* Number of pad bytes to read */
++	uint16 rdlen;	/* Total number of bytes to read */
++	uint8 rxseq;	/* Next sequence number to expect */
++	uint rxleft = 0;	/* Remaining number of frames allowed */
++	int sdret;	/* Return code from bcmsdh calls */
++	uint8 txmax;	/* Maximum tx sequence offered */
++	bool len_consistent; /* Result of comparing readahead len and len from hw-hdr */
++	uint8 *rxbuf;
++	int ifidx = 0;
++	uint rxcount = 0; /* Total frames read */
++	uchar reorder_info_buf[WLHOST_REORDERDATA_TOTLEN];
++	uint reorder_info_len;
++	uint pkt_count;
++
++#if defined(DHD_DEBUG) || defined(SDTEST)
++	bool sdtest = FALSE;	/* To limit message spew from test mode */
++#endif
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	bus->readframes = TRUE;
++
++	if (!KSO_ENAB(bus)) {
++		DHD_ERROR(("%s: KSO off\n", __FUNCTION__));
++		bus->readframes = FALSE;
++		return 0;
++	}
++
++	ASSERT(maxframes);
++
++#ifdef SDTEST
++	/* Allow pktgen to override maxframes */
++	if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
++		maxframes = bus->pktgen_count;
++		sdtest = TRUE;
++	}
++#endif
++
++	/* Not finished unless we encounter no more frames indication */
++	*finished = FALSE;
++
++
++	for (rxseq = bus->rx_seq, rxleft = maxframes;
++	     !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
++	     rxseq++, rxleft--) {
++#ifdef DHDTCPACK_SUP_DBG
++		if (bus->dhd->tcpack_sup_mode != TCPACK_SUP_DELAYTX) {
++			if (bus->dotxinrx == FALSE)
++				DHD_ERROR(("%s %d: dotxinrx FALSE with tcpack_sub_mode %d\n",
++					__FUNCTION__, __LINE__, bus->dhd->tcpack_sup_mode));
++		}
++#ifdef DEBUG_COUNTER
++		else if (pktq_mlen(&bus->txq, ~bus->flowcontrol) > 0) {
++			tack_tbl.cnt[bus->dotxinrx ? 6 : 7]++;
++		}
++#endif /* DEBUG_COUNTER */
++#endif /* DHDTCPACK_SUP_DBG */
++		/* tx more to improve rx performance */
++		if (TXCTLOK(bus) && bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL)) {
++			dhdsdio_sendpendctl(bus);
++		} else if (bus->dotxinrx && (bus->clkstate == CLK_AVAIL) &&
++			!bus->fcstate && DATAOK(bus) &&
++			(pktq_mlen(&bus->txq, ~bus->flowcontrol) > bus->txinrx_thres)) {
++			dhdsdio_sendfromq(bus, dhd_txbound);
++#ifdef DHDTCPACK_SUPPRESS
++			/* In TCPACK_SUP_DELAYTX mode, do txinrx only if
++			 * 1. Any DATA packet to TX
++			 * 2. TCPACK to TCPDATA PSH packets.
++			 * in bus txq.
++			 */
++			bus->dotxinrx = (bus->dhd->tcpack_sup_mode == TCPACK_SUP_DELAYTX) ?
++				FALSE : TRUE;
++#endif
++		}
++
++		/* Handle glomming separately */
++		if (bus->glom || bus->glomd) {
++			uint8 cnt;
++			DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
++			          __FUNCTION__, bus->glomd, bus->glom));
++			cnt = dhdsdio_rxglom(bus, rxseq);
++			DHD_GLOM(("%s: rxglom returned %d\n", __FUNCTION__, cnt));
++			rxseq += cnt - 1;
++			rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
++			continue;
++		}
++
++		/* Try doing single read if we can */
++		if (dhd_readahead && bus->nextlen) {
++			uint16 nextlen = bus->nextlen;
++			bus->nextlen = 0;
++
++			if (bus->bus == SPI_BUS) {
++				rdlen = len = nextlen;
++			}
++			else {
++				rdlen = len = nextlen << 4;
++
++				/* Pad read to blocksize for efficiency */
++				if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
++					pad = bus->blocksize - (rdlen % bus->blocksize);
++					if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
++						((rdlen + pad + firstread) < MAX_RX_DATASZ))
++						rdlen += pad;
++				} else if (rdlen % DHD_SDALIGN) {
++					rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
++				}
++			}
++
++			/* We use bus->rxctl buffer in WinXP for initial control pkt receives.
++			 * Later we use buffer-poll for data as well as control packets.
++			 * This is required because dhd receives full frame in gSPI unlike SDIO.
++			 * After the frame is received we have to distinguish whether it is data
++			 * or non-data frame.
++			 */
++			/* Allocate a packet buffer */
++			dhd_os_sdlock_rxq(bus->dhd);
++			if (!(pkt = PKTGET(osh, rdlen + DHD_SDALIGN, FALSE))) {
++				if (bus->bus == SPI_BUS) {
++					bus->usebufpool = FALSE;
++					bus->rxctl = bus->rxbuf;
++					if (dhd_alignctl) {
++						bus->rxctl += firstread;
++						if ((pad = ((uintptr)bus->rxctl % DHD_SDALIGN)))
++							bus->rxctl += (DHD_SDALIGN - pad);
++						bus->rxctl -= firstread;
++					}
++					ASSERT(bus->rxctl >= bus->rxbuf);
++					rxbuf = bus->rxctl;
++					/* Read the entire frame */
++					sdret = dhd_bcmsdh_recv_buf(bus,
++					                            bcmsdh_cur_sbwad(sdh),
++					                            SDIO_FUNC_2,
++					                            F2SYNC, rxbuf, rdlen,
++					                            NULL, NULL, NULL);
++					bus->f2rxdata++;
++					ASSERT(sdret != BCME_PENDING);
++
++
++					/* Control frame failures need retransmission */
++					if (sdret < 0) {
++						DHD_ERROR(("%s: read %d control bytes failed: %d\n",
++						   __FUNCTION__, rdlen, sdret));
++						/* dhd.rx_ctlerrs is higher level */
++						bus->rxc_errors++;
++						dhd_os_sdunlock_rxq(bus->dhd);
++						dhdsdio_rxfail(bus, TRUE,
++						    (bus->bus == SPI_BUS) ? FALSE : TRUE);
++						continue;
++					}
++				} else {
++					/* Give up on data, request rtx of events */
++					DHD_ERROR(("%s (nextlen): PKTGET failed: len %d rdlen %d "
++					           "expected rxseq %d\n",
++					           __FUNCTION__, len, rdlen, rxseq));
++					/* Just go try again w/normal header read */
++					dhd_os_sdunlock_rxq(bus->dhd);
++					continue;
++				}
++			} else {
++				if (bus->bus == SPI_BUS)
++					bus->usebufpool = TRUE;
++
++				ASSERT(!PKTLINK(pkt));
++				PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
++				rxbuf = (uint8 *)PKTDATA(osh, pkt);
++				/* Read the entire frame */
++				sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh),
++				                            SDIO_FUNC_2,
++				                            F2SYNC, rxbuf, rdlen,
++				                            pkt, NULL, NULL);
++				bus->f2rxdata++;
++				ASSERT(sdret != BCME_PENDING);
++
++				if (sdret < 0) {
++					DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
++					   __FUNCTION__, rdlen, sdret));
++					PKTFREE(bus->dhd->osh, pkt, FALSE);
++					bus->dhd->rx_errors++;
++					dhd_os_sdunlock_rxq(bus->dhd);
++					/* Force retry w/normal header read.  Don't attempt NAK for
++					 * gSPI
++					 */
++					dhdsdio_rxfail(bus, TRUE,
++					      (bus->bus == SPI_BUS) ? FALSE : TRUE);
++					continue;
++				}
++			}
++			dhd_os_sdunlock_rxq(bus->dhd);
++
++			/* Now check the header */
++			bcopy(rxbuf, bus->rxhdr, SDPCM_HDRLEN);
++
++			/* Extract hardware header fields */
++			len = ltoh16_ua(bus->rxhdr);
++			check = ltoh16_ua(bus->rxhdr + sizeof(uint16));
++
++			/* All zeros means readahead info was bad */
++			if (!(len|check)) {
++				DHD_INFO(("%s (nextlen): read zeros in HW header???\n",
++				           __FUNCTION__));
++				dhd_os_sdlock_rxq(bus->dhd);
++				PKTFREE2();
++				dhd_os_sdunlock_rxq(bus->dhd);
++				GSPI_PR55150_BAILOUT;
++				continue;
++			}
++
++			/* Validate check bytes */
++			if ((uint16)~(len^check)) {
++				DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check"
++				           " 0x%04x/0x%04x/0x%04x\n", __FUNCTION__, nextlen,
++				           len, check));
++				dhd_os_sdlock_rxq(bus->dhd);
++				PKTFREE2();
++				dhd_os_sdunlock_rxq(bus->dhd);
++				bus->rx_badhdr++;
++				dhdsdio_rxfail(bus, FALSE, FALSE);
++				GSPI_PR55150_BAILOUT;
++				continue;
++			}
++
++			/* Validate frame length */
++			if (len < SDPCM_HDRLEN) {
++				DHD_ERROR(("%s (nextlen): HW hdr length invalid: %d\n",
++				           __FUNCTION__, len));
++				dhd_os_sdlock_rxq(bus->dhd);
++				PKTFREE2();
++				dhd_os_sdunlock_rxq(bus->dhd);
++				GSPI_PR55150_BAILOUT;
++				continue;
++			}
++
++			/* Check for consistency with readahead info */
++				len_consistent = (nextlen != (ROUNDUP(len, 16) >> 4));
++			if (len_consistent) {
++				/* Mismatch, force retry w/normal header (may be >4K) */
++				DHD_ERROR(("%s (nextlen): mismatch, nextlen %d len %d rnd %d; "
++				           "expected rxseq %d\n",
++				           __FUNCTION__, nextlen, len, ROUNDUP(len, 16), rxseq));
++				dhd_os_sdlock_rxq(bus->dhd);
++				PKTFREE2();
++				dhd_os_sdunlock_rxq(bus->dhd);
++				dhdsdio_rxfail(bus, TRUE, (bus->bus == SPI_BUS) ? FALSE : TRUE);
++				GSPI_PR55150_BAILOUT;
++				continue;
++			}
++
++
++			/* Extract software header fields */
++			chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++			seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++			doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++			txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++
++				bus->nextlen =
++				         bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
++				if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
++					DHD_INFO(("%s (nextlen): got frame w/nextlen too large"
++					          " (%d), seq %d\n", __FUNCTION__, bus->nextlen,
++					          seq));
++					bus->nextlen = 0;
++				}
++
++				bus->dhd->rx_readahead_cnt ++;
++			/* Handle Flow Control */
++			fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++
++			delta = 0;
++			if (~bus->flowcontrol & fcbits) {
++				bus->fc_xoff++;
++				delta = 1;
++			}
++			if (bus->flowcontrol & ~fcbits) {
++				bus->fc_xon++;
++				delta = 1;
++			}
++
++			if (delta) {
++				bus->fc_rcvd++;
++				bus->flowcontrol = fcbits;
++			}
++
++			/* Check and update sequence number */
++			if (rxseq != seq) {
++				DHD_INFO(("%s (nextlen): rx_seq %d, expected %d\n",
++				          __FUNCTION__, seq, rxseq));
++				bus->rx_badseq++;
++				rxseq = seq;
++			}
++
++			/* Check window for sanity */
++			if ((uint8)(txmax - bus->tx_seq) > 0x70) {
++					DHD_ERROR(("%s: got unlikely tx max %d with tx_seq %d\n",
++						__FUNCTION__, txmax, bus->tx_seq));
++					txmax = bus->tx_max;
++			}
++			bus->tx_max = txmax;
++
++#ifdef DHD_DEBUG
++			if (DHD_BYTES_ON() && DHD_DATA_ON()) {
++				prhex("Rx Data", rxbuf, len);
++			} else if (DHD_HDRS_ON()) {
++				prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
++			}
++#endif
++
++			if (chan == SDPCM_CONTROL_CHANNEL) {
++				if (bus->bus == SPI_BUS) {
++					dhdsdio_read_control(bus, rxbuf, len, doff);
++					if (bus->usebufpool) {
++						dhd_os_sdlock_rxq(bus->dhd);
++						PKTFREE(bus->dhd->osh, pkt, FALSE);
++						dhd_os_sdunlock_rxq(bus->dhd);
++					}
++					continue;
++				} else {
++					DHD_ERROR(("%s (nextlen): readahead on control"
++					           " packet %d?\n", __FUNCTION__, seq));
++					/* Force retry w/normal header read */
++					bus->nextlen = 0;
++					dhdsdio_rxfail(bus, FALSE, TRUE);
++					dhd_os_sdlock_rxq(bus->dhd);
++					PKTFREE2();
++					dhd_os_sdunlock_rxq(bus->dhd);
++					continue;
++				}
++			}
++
++			if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
++				DHD_ERROR(("Received %d bytes on %d channel. Running out of "
++				           "rx pktbuf's or not yet malloced.\n", len, chan));
++				continue;
++			}
++
++			/* Validate data offset */
++			if ((doff < SDPCM_HDRLEN) || (doff > len)) {
++				DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
++				           __FUNCTION__, doff, len, SDPCM_HDRLEN));
++				dhd_os_sdlock_rxq(bus->dhd);
++				PKTFREE2();
++				dhd_os_sdunlock_rxq(bus->dhd);
++				ASSERT(0);
++				dhdsdio_rxfail(bus, FALSE, FALSE);
++				continue;
++			}
++
++			/* All done with this one -- now deliver the packet */
++			goto deliver;
++		}
++		/* gSPI frames should not be handled in fractions */
++		if (bus->bus == SPI_BUS) {
++			break;
++		}
++
++		/* Read frame header (hardware and software) */
++		sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
++		                            bus->rxhdr, firstread, NULL, NULL, NULL);
++		bus->f2rxhdrs++;
++		ASSERT(sdret != BCME_PENDING);
++
++		if (sdret < 0) {
++			DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __FUNCTION__, sdret));
++			bus->rx_hdrfail++;
++			dhdsdio_rxfail(bus, TRUE, TRUE);
++			continue;
++		}
++
++#ifdef DHD_DEBUG
++		if (DHD_BYTES_ON() || DHD_HDRS_ON()) {
++			prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
++		}
++#endif
++
++		/* Extract hardware header fields */
++		len = ltoh16_ua(bus->rxhdr);
++		check = ltoh16_ua(bus->rxhdr + sizeof(uint16));
++
++		/* All zeros means no more frames */
++		if (!(len|check)) {
++			*finished = TRUE;
++			break;
++		}
++
++		/* Validate check bytes */
++		if ((uint16)~(len^check)) {
++			DHD_ERROR(("%s: HW hdr error: len/check 0x%04x/0x%04x\n",
++			           __FUNCTION__, len, check));
++			bus->rx_badhdr++;
++			dhdsdio_rxfail(bus, FALSE, FALSE);
++			continue;
++		}
++
++		/* Validate frame length */
++		if (len < SDPCM_HDRLEN) {
++			DHD_ERROR(("%s: HW hdr length invalid: %d\n", __FUNCTION__, len));
++			continue;
++		}
++
++		/* Extract software header fields */
++		chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++		seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++		doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++		txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++
++		/* Validate data offset */
++		if ((doff < SDPCM_HDRLEN) || (doff > len)) {
++			DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d seq %d\n",
++			           __FUNCTION__, doff, len, SDPCM_HDRLEN, seq));
++			bus->rx_badhdr++;
++			ASSERT(0);
++			dhdsdio_rxfail(bus, FALSE, FALSE);
++			continue;
++		}
++
++		/* Save the readahead length if there is one */
++		bus->nextlen = bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
++		if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
++			DHD_INFO(("%s (nextlen): got frame w/nextlen too large (%d), seq %d\n",
++			          __FUNCTION__, bus->nextlen, seq));
++			bus->nextlen = 0;
++		}
++
++		/* Handle Flow Control */
++		fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
++
++		delta = 0;
++		if (~bus->flowcontrol & fcbits) {
++			bus->fc_xoff++;
++			delta = 1;
++		}
++		if (bus->flowcontrol & ~fcbits) {
++			bus->fc_xon++;
++			delta = 1;
++		}
++
++		if (delta) {
++			bus->fc_rcvd++;
++			bus->flowcontrol = fcbits;
++		}
++
++		/* Check and update sequence number */
++		if (rxseq != seq) {
++			DHD_INFO(("%s: rx_seq %d, expected %d\n", __FUNCTION__, seq, rxseq));
++			bus->rx_badseq++;
++			rxseq = seq;
++		}
++
++		/* Check window for sanity */
++		if ((uint8)(txmax - bus->tx_seq) > 0x70) {
++			DHD_ERROR(("%s: got unlikely tx max %d with tx_seq %d\n",
++			           __FUNCTION__, txmax, bus->tx_seq));
++			txmax = bus->tx_max;
++		}
++		bus->tx_max = txmax;
++
++		/* Call a separate function for control frames */
++		if (chan == SDPCM_CONTROL_CHANNEL) {
++			dhdsdio_read_control(bus, bus->rxhdr, len, doff);
++			continue;
++		}
++
++		ASSERT((chan == SDPCM_DATA_CHANNEL) || (chan == SDPCM_EVENT_CHANNEL) ||
++		       (chan == SDPCM_TEST_CHANNEL) || (chan == SDPCM_GLOM_CHANNEL));
++
++		/* Length to read */
++		rdlen = (len > firstread) ? (len - firstread) : 0;
++
++		/* May pad read to blocksize for efficiency */
++		if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
++			pad = bus->blocksize - (rdlen % bus->blocksize);
++			if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
++			    ((rdlen + pad + firstread) < MAX_RX_DATASZ))
++				rdlen += pad;
++		} else if (rdlen % DHD_SDALIGN) {
++			rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
++		}
++
++		/* Satisfy length-alignment requirements */
++		if (forcealign && (rdlen & (ALIGNMENT - 1)))
++			rdlen = ROUNDUP(rdlen, ALIGNMENT);
++
++		if ((rdlen + firstread) > MAX_RX_DATASZ) {
++			/* Too long -- skip this frame */
++			DHD_ERROR(("%s: too long: len %d rdlen %d\n", __FUNCTION__, len, rdlen));
++			bus->dhd->rx_errors++; bus->rx_toolong++;
++			dhdsdio_rxfail(bus, FALSE, FALSE);
++			continue;
++		}
++
++		dhd_os_sdlock_rxq(bus->dhd);
++		if (!(pkt = PKTGET(osh, (rdlen + firstread + DHD_SDALIGN), FALSE))) {
++			/* Give up on data, request rtx of events */
++			DHD_ERROR(("%s: PKTGET failed: rdlen %d chan %d\n",
++			           __FUNCTION__, rdlen, chan));
++			bus->dhd->rx_dropped++;
++			dhd_os_sdunlock_rxq(bus->dhd);
++			dhdsdio_rxfail(bus, FALSE, RETRYCHAN(chan));
++			continue;
++		}
++		dhd_os_sdunlock_rxq(bus->dhd);
++
++		ASSERT(!PKTLINK(pkt));
++
++		/* Leave room for what we already read, and align remainder */
++		ASSERT(firstread < (PKTLEN(osh, pkt)));
++		PKTPULL(osh, pkt, firstread);
++		PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
++
++		/* Read the remaining frame data */
++		sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
++		                            ((uint8 *)PKTDATA(osh, pkt)), rdlen, pkt, NULL, NULL);
++		bus->f2rxdata++;
++		ASSERT(sdret != BCME_PENDING);
++
++		if (sdret < 0) {
++			DHD_ERROR(("%s: read %d %s bytes failed: %d\n", __FUNCTION__, rdlen,
++			           ((chan == SDPCM_EVENT_CHANNEL) ? "event" :
++			            ((chan == SDPCM_DATA_CHANNEL) ? "data" : "test")), sdret));
++			dhd_os_sdlock_rxq(bus->dhd);
++			PKTFREE(bus->dhd->osh, pkt, FALSE);
++			dhd_os_sdunlock_rxq(bus->dhd);
++			bus->dhd->rx_errors++;
++			dhdsdio_rxfail(bus, TRUE, RETRYCHAN(chan));
++			continue;
++		}
++
++		/* Copy the already-read portion */
++		PKTPUSH(osh, pkt, firstread);
++		bcopy(bus->rxhdr, PKTDATA(osh, pkt), firstread);
++
++#ifdef DHD_DEBUG
++		if (DHD_BYTES_ON() && DHD_DATA_ON()) {
++			prhex("Rx Data", PKTDATA(osh, pkt), len);
++		}
++#endif
++
++deliver:
++		/* Save superframe descriptor and allocate packet frame */
++		if (chan == SDPCM_GLOM_CHANNEL) {
++			if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
++				DHD_GLOM(("%s: got glom descriptor, %d bytes:\n",
++				          __FUNCTION__, len));
++#ifdef DHD_DEBUG
++				if (DHD_GLOM_ON()) {
++					prhex("Glom Data", PKTDATA(osh, pkt), len);
++				}
++#endif
++				PKTSETLEN(osh, pkt, len);
++				ASSERT(doff == SDPCM_HDRLEN);
++				PKTPULL(osh, pkt, SDPCM_HDRLEN);
++				bus->glomd = pkt;
++			} else {
++				DHD_ERROR(("%s: glom superframe w/o descriptor!\n", __FUNCTION__));
++				dhdsdio_rxfail(bus, FALSE, FALSE);
++			}
++			continue;
++		}
++
++		/* Fill in packet len and prio, deliver upward */
++		PKTSETLEN(osh, pkt, len);
++		PKTPULL(osh, pkt, doff);
++
++#ifdef SDTEST
++		/* Test channel packets are processed separately */
++		if (chan == SDPCM_TEST_CHANNEL) {
++			dhdsdio_testrcv(bus, pkt, seq);
++			continue;
++		}
++#endif /* SDTEST */
++
++		if (PKTLEN(osh, pkt) == 0) {
++			dhd_os_sdlock_rxq(bus->dhd);
++			PKTFREE(bus->dhd->osh, pkt, FALSE);
++			dhd_os_sdunlock_rxq(bus->dhd);
++			continue;
++		} else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt, reorder_info_buf,
++			&reorder_info_len) != 0) {
++			DHD_ERROR(("%s: rx protocol error\n", __FUNCTION__));
++			dhd_os_sdlock_rxq(bus->dhd);
++			PKTFREE(bus->dhd->osh, pkt, FALSE);
++			dhd_os_sdunlock_rxq(bus->dhd);
++			bus->dhd->rx_errors++;
++			continue;
++		}
++		if (reorder_info_len) {
++			/* Reordering info from the firmware */
++			dhd_process_pkt_reorder_info(bus->dhd, reorder_info_buf, reorder_info_len,
++				&pkt, &pkt_count);
++			if (pkt_count == 0)
++				continue;
++		}
++		else
++			pkt_count = 1;
++
++		/* Unlock during rx call */
++		dhd_os_sdunlock(bus->dhd);
++		dhd_rx_frame(bus->dhd, ifidx, pkt, pkt_count, chan);
++		dhd_os_sdlock(bus->dhd);
++	}
++	rxcount = maxframes - rxleft;
++#ifdef DHD_DEBUG
++	/* Message if we hit the limit */
++	if (!rxleft && !sdtest)
++		DHD_DATA(("%s: hit rx limit of %d frames\n", __FUNCTION__, maxframes));
++	else
++#endif /* DHD_DEBUG */
++	DHD_DATA(("%s: processed %d frames\n", __FUNCTION__, rxcount));
++	/* Back off rxseq if awaiting rtx, update rx_seq */
++	if (bus->rxskip)
++		rxseq--;
++	bus->rx_seq = rxseq;
++
++	if (bus->reqbussleep)
++	{
++	    dhdsdio_bussleep(bus, TRUE);
++		bus->reqbussleep = FALSE;
++	}
++	bus->readframes = FALSE;
++
++	return rxcount;
++}
++
++static uint32
++dhdsdio_hostmail(dhd_bus_t *bus, uint32 *hmbd)
++{
++	sdpcmd_regs_t *regs = bus->regs;
++	uint32 intstatus = 0;
++	uint32 hmb_data;
++	uint8 fcbits;
++	uint retries = 0;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	/* Read mailbox data and ack that we did so */
++	R_SDREG(hmb_data, &regs->tohostmailboxdata, retries);
++	if (retries <= retry_limit)
++		W_SDREG(SMB_INT_ACK, &regs->tosbmailbox, retries);
++	bus->f1regdata += 2;
++
++	/* Dongle recomposed rx frames, accept them again */
++	if (hmb_data & HMB_DATA_NAKHANDLED) {
++		DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n", bus->rx_seq));
++		if (!bus->rxskip) {
++			DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __FUNCTION__));
++		}
++		bus->rxskip = FALSE;
++		intstatus |= FRAME_AVAIL_MASK(bus);
++	}
++
++	/*
++	 * DEVREADY does not occur with gSPI.
++	 */
++	if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
++		bus->sdpcm_ver = (hmb_data & HMB_DATA_VERSION_MASK) >> HMB_DATA_VERSION_SHIFT;
++		if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
++			DHD_ERROR(("Version mismatch, dongle reports %d, expecting %d\n",
++			           bus->sdpcm_ver, SDPCM_PROT_VERSION));
++		else
++			DHD_INFO(("Dongle ready, protocol version %d\n", bus->sdpcm_ver));
++		/* make sure for the SDIO_DEVICE_RXDATAINT_MODE_1 corecontrol is proper */
++		if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev >= 4) &&
++		    (bus->rxint_mode  == SDIO_DEVICE_RXDATAINT_MODE_1)) {
++			uint32 val;
++
++			val = R_REG(bus->dhd->osh, &bus->regs->corecontrol);
++			val &= ~CC_XMTDATAAVAIL_MODE;
++			val |= CC_XMTDATAAVAIL_CTRL;
++			W_REG(bus->dhd->osh, &bus->regs->corecontrol, val);
++
++			val = R_REG(bus->dhd->osh, &bus->regs->corecontrol);
++		}
++
++#ifdef DHD_DEBUG
++		/* Retrieve console state address now that firmware should have updated it */
++		{
++			sdpcm_shared_t shared;
++			if (dhdsdio_readshared(bus, &shared) == 0)
++				bus->console_addr = shared.console_addr;
++		}
++#endif /* DHD_DEBUG */
++	}
++
++	/*
++	 * Flow Control has been moved into the RX headers and this out of band
++	 * method isn't used any more.  Leave this here for possibly remaining backward
++	 * compatible with older dongles
++	 */
++	if (hmb_data & HMB_DATA_FC) {
++		fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> HMB_DATA_FCDATA_SHIFT;
++
++		if (fcbits & ~bus->flowcontrol)
++			bus->fc_xoff++;
++		if (bus->flowcontrol & ~fcbits)
++			bus->fc_xon++;
++
++		bus->fc_rcvd++;
++		bus->flowcontrol = fcbits;
++	}
++
++	/* At least print a message if FW halted */
++	if (hmb_data & HMB_DATA_FWHALT) {
++		DHD_ERROR(("INTERNAL ERROR: FIRMWARE HALTED : set BUS DOWN\n"));
++		dhdsdio_checkdied(bus, NULL, 0);
++		bus->dhd->busstate = DHD_BUS_DOWN;
++	}
++
++	/* Shouldn't be any others */
++	if (hmb_data & ~(HMB_DATA_DEVREADY |
++	                 HMB_DATA_FWHALT |
++	                 HMB_DATA_NAKHANDLED |
++	                 HMB_DATA_FC |
++	                 HMB_DATA_FWREADY |
++	                 HMB_DATA_FCDATA_MASK |
++	                 HMB_DATA_VERSION_MASK)) {
++		DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
++	}
++
++	if (hmbd) {
++		*hmbd = hmb_data;
++	}
++
++	return intstatus;
++}
++
++void
++dhdsdio_isr(void *arg)
++{
++	dhd_bus_t *bus = (dhd_bus_t*)arg;
++	bcmsdh_info_t *sdh;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (!bus) {
++		DHD_ERROR(("%s : bus is null pointer , exit \n", __FUNCTION__));
++		return;
++	}
++	sdh = bus->sdh;
++
++	if (bus->dhd->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s : bus is down. we have nothing to do\n", __FUNCTION__));
++		return;
++	}
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	/* Count the interrupt call */
++	bus->intrcount++;
++	bus->ipend = TRUE;
++
++	/* Shouldn't get this interrupt if we're sleeping? */
++	if (!SLPAUTO_ENAB(bus)) {
++		if (bus->sleeping) {
++			DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
++			return;
++		} else if (!KSO_ENAB(bus)) {
++			DHD_ERROR(("ISR in devsleep 1\n"));
++		}
++	}
++
++	/* Disable additional interrupts (is this needed now)? */
++	if (bus->intr) {
++		DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__));
++	} else {
++		DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
++	}
++
++	bcmsdh_intr_disable(sdh);
++	bus->intdis = TRUE;
++
++	DHD_OS_WAKE_LOCK(bus->dhd);
++	if (dhdsdio_dpc(bus)) {
++		bus->dpc_sched = TRUE;
++		dhd_sched_dpc(bus->dhd);
++	}
++	DHD_OS_WAKE_UNLOCK(bus->dhd);
++
++}
++
++static bool
++dhdsdio_dpc(dhd_bus_t *bus)
++{
++	bcmsdh_info_t *sdh = bus->sdh;
++	sdpcmd_regs_t *regs = bus->regs;
++	uint32 intstatus, newstatus = 0;
++	uint retries = 0;
++	uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
++	uint txlimit = dhd_txbound; /* Tx frames to send before resched */
++	uint framecnt = 0;		  /* Temporary counter of tx/rx frames */
++	bool rxdone = TRUE;		  /* Flag for no more read data */
++	bool resched = FALSE;	  /* Flag indicating resched wanted */
++	unsigned long flags;
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (in_irq())
++		return TRUE;
++
++	dhd_os_sdlock(bus->dhd);
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	if (bus->dhd->busstate == DHD_BUS_DOWN) {
++		DHD_ERROR(("%s: Bus down, ret\n", __FUNCTION__));
++		bus->intstatus = 0;
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++		dhd_os_sdunlock(bus->dhd);
++		return 0;
++	}
++
++	bus->dhd->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_DPC;
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	/* Start with leftover status bits */
++	intstatus = bus->intstatus;
++
++	if (!SLPAUTO_ENAB(bus) && !KSO_ENAB(bus)) {
++		DHD_ERROR(("%s: Device asleep\n", __FUNCTION__));
++		goto exit;
++	}
++
++	/* If waiting for HTAVAIL, check status */
++	if (!SLPAUTO_ENAB(bus) && (bus->clkstate == CLK_PENDING)) {
++		int err;
++		uint8 clkctl, devctl = 0;
++
++#ifdef DHD_DEBUG
++		/* Check for inconsistent device control */
++		devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
++		if (err) {
++			DHD_ERROR(("%s: error reading DEVCTL: %d\n", __FUNCTION__, err));
++			bus->dhd->busstate = DHD_BUS_DOWN;
++		} else {
++			ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
++		}
++#endif /* DHD_DEBUG */
++
++		/* Read CSR, if clock on switch to AVAIL, else ignore */
++		clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
++		if (err) {
++			DHD_ERROR(("%s: error reading CSR: %d\n", __FUNCTION__, err));
++			bus->dhd->busstate = DHD_BUS_DOWN;
++		}
++
++		DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl, clkctl));
++
++		if (SBSDIO_HTAV(clkctl)) {
++			devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
++			if (err) {
++				DHD_ERROR(("%s: error reading DEVCTL: %d\n",
++				           __FUNCTION__, err));
++				bus->dhd->busstate = DHD_BUS_DOWN;
++			}
++			devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
++			bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
++			if (err) {
++				DHD_ERROR(("%s: error writing DEVCTL: %d\n",
++				           __FUNCTION__, err));
++				bus->dhd->busstate = DHD_BUS_DOWN;
++			}
++			bus->clkstate = CLK_AVAIL;
++		} else {
++			goto clkwait;
++		}
++	}
++
++	BUS_WAKE(bus);
++
++	/* Make sure backplane clock is on */
++	dhdsdio_clkctl(bus, CLK_AVAIL, TRUE);
++	if (bus->clkstate != CLK_AVAIL)
++		goto clkwait;
++
++	/* Pending interrupt indicates new device status */
++	if (bus->ipend) {
++		bus->ipend = FALSE;
++		R_SDREG(newstatus, &regs->intstatus, retries);
++		bus->f1regdata++;
++		if (bcmsdh_regfail(bus->sdh))
++			newstatus = 0;
++		newstatus &= bus->hostintmask;
++		bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
++		if (newstatus) {
++			bus->f1regdata++;
++			if ((bus->rxint_mode == SDIO_DEVICE_RXDATAINT_MODE_0) &&
++				(newstatus == I_XMTDATA_AVAIL)) {
++			}
++			else
++				W_SDREG(newstatus, &regs->intstatus, retries);
++		}
++	}
++
++	/* Merge new bits with previous */
++	intstatus |= newstatus;
++	bus->intstatus = 0;
++
++	/* Handle flow-control change: read new state in case our ack
++	 * crossed another change interrupt.  If change still set, assume
++	 * FC ON for safety, let next loop through do the debounce.
++	 */
++	if (intstatus & I_HMB_FC_CHANGE) {
++		intstatus &= ~I_HMB_FC_CHANGE;
++		W_SDREG(I_HMB_FC_CHANGE, &regs->intstatus, retries);
++		R_SDREG(newstatus, &regs->intstatus, retries);
++		bus->f1regdata += 2;
++		bus->fcstate = !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
++		intstatus |= (newstatus & bus->hostintmask);
++	}
++
++	/* Handle host mailbox indication */
++	if (intstatus & I_HMB_HOST_INT) {
++		uint32 hmbdata = 0;
++		intstatus &= ~I_HMB_HOST_INT;
++		intstatus |= dhdsdio_hostmail(bus, &hmbdata);
++		/* ULP prototyping. Redowload fw on oob interupt */
++#ifdef DHD_ULP
++		/* all the writes after this point CAN use cached sbwad value */
++		bcmsdh_force_sbwad_calc(bus->sdh, FALSE);
++
++		if (dhd_ulp_pre_redownload_check(bus->dhd, bus->sdh, (void*)bus->sih, hmbdata)) {
++			if (dhd_bus_ulp_reinit_fw(bus) < 0) {
++				DHD_ERROR(("%s:%d FW redownload failed\n",
++					__FUNCTION__, __LINE__));
++				goto exit;
++			}
++		}
++#endif
++
++	}
++
++	/* Just being here means nothing more to do for chipactive */
++	if (intstatus & I_CHIPACTIVE) {
++		/* ASSERT(bus->clkstate == CLK_AVAIL); */
++		intstatus &= ~I_CHIPACTIVE;
++	}
++
++	/* Handle host mailbox indication */
++	if (intstatus & I_HMB_HOST_INT) {
++		intstatus &= ~I_HMB_HOST_INT;
++		intstatus |= dhdsdio_hostmail(bus, NULL);
++	}
++
++	/* Generally don't ask for these, can get CRC errors... */
++	if (intstatus & I_WR_OOSYNC) {
++		DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
++		intstatus &= ~I_WR_OOSYNC;
++	}
++
++	if (intstatus & I_RD_OOSYNC) {
++		DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
++		intstatus &= ~I_RD_OOSYNC;
++	}
++
++	if (intstatus & I_SBINT) {
++		DHD_ERROR(("Dongle reports SBINT\n"));
++		intstatus &= ~I_SBINT;
++	}
++
++	/* Would be active due to wake-wlan in gSPI */
++	if (intstatus & I_CHIPACTIVE) {
++		DHD_INFO(("Dongle reports CHIPACTIVE\n"));
++		intstatus &= ~I_CHIPACTIVE;
++	}
++
++	if (intstatus & I_HMB_FC_STATE) {
++		DHD_INFO(("Dongle reports HMB_FC_STATE\n"));
++		intstatus &= ~I_HMB_FC_STATE;
++	}
++
++	/* Ignore frame indications if rxskip is set */
++	if (bus->rxskip) {
++		intstatus &= ~FRAME_AVAIL_MASK(bus);
++	}
++
++	/* On frame indication, read available frames */
++	if (PKT_AVAILABLE(bus, intstatus)) {
++
++			framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
++			if (rxdone || bus->rxskip)
++				intstatus  &= ~FRAME_AVAIL_MASK(bus);
++			rxlimit -= MIN(framecnt, rxlimit);
++	}
++
++	/* Keep still-pending events for next scheduling */
++	bus->intstatus = intstatus;
++
++clkwait:
++	/* Re-enable interrupts to detect new device events (mailbox, rx frame)
++	 * or clock availability.  (Allows tx loop to check ipend if desired.)
++	 * (Unless register access seems hosed, as we may not be able to ACK...)
++	 */
++	if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
++		DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
++		          __FUNCTION__, rxdone, framecnt));
++		bus->intdis = FALSE;
++#if defined(OOB_INTR_ONLY)
++		bcmsdh_oob_intr_set(bus->sdh, TRUE);
++#endif /* defined(OOB_INTR_ONLY) */
++		bcmsdh_intr_enable(sdh);
++	}
++
++#if defined(OOB_INTR_ONLY) && !defined(HW_OOB)
++	/* In case of SW-OOB(using edge trigger),
++	 * Check interrupt status in the dongle again after enable irq on the host.
++	 * and rechedule dpc if interrupt is pended in the dongle.
++	 * There is a chance to miss OOB interrupt while irq is disabled on the host.
++	 * No need to do this with HW-OOB(level trigger)
++	 */
++	R_SDREG(newstatus, &regs->intstatus, retries);
++	if (bcmsdh_regfail(bus->sdh))
++		newstatus = 0;
++	if (newstatus & bus->hostintmask) {
++		bus->ipend = TRUE;
++		resched = TRUE;
++	}
++#endif /* defined(OOB_INTR_ONLY) && !defined(HW_OOB) */
++
++#ifdef PROP_TXSTATUS
++	dhd_wlfc_commit_packets(bus->dhd, (f_commitpkt_t)dhd_bus_txdata, (void *)bus, NULL, FALSE);
++#endif
++
++	if (TXCTLOK(bus) && bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL))
++		dhdsdio_sendpendctl(bus);
++
++	/* Send queued frames (limit 1 if rx may still be pending) */
++	else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
++	    pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit && DATAOK(bus)) {
++
++#ifdef DHD_ULP
++		if (dhd_ulp_f2_ready(bus->dhd, bus->sdh)) {
++#endif /* DHD_ULP */
++			framecnt = rxdone ? txlimit : MIN(txlimit, dhd_txminmax);
++			framecnt = dhdsdio_sendfromq(bus, framecnt);
++			txlimit -= framecnt;
++#ifdef DHD_ULP
++		} else {
++			/* In other transient states like DHD_ULP_, after the states are
++			* DHD_ULP_F2ENAB_CLEARING and DHD_ULP_F2ENAB_SETTING,
++			* dpc is scheduled after steady-state and dhdsdio_sendfromq() will
++			* execute again
++			*/
++		}
++#endif /* DHD_ULP */
++	}
++	/* Resched the DPC if ctrl cmd is pending on bus credit */
++	if (bus->ctrl_frame_stat)
++		resched = TRUE;
++
++	/* Resched if events or tx frames are pending, else await next interrupt */
++	/* On failed register access, all bets are off: no resched or interrupts */
++	if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
++		if ((bus->sih && bus->sih->buscorerev >= 12) && !(dhdsdio_sleepcsr_get(bus) &
++			SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
++			/* Bus failed because of KSO */
++			DHD_ERROR(("%s: Bus failed due to KSO\n", __FUNCTION__));
++			bus->kso = FALSE;
++		} else {
++			DHD_ERROR(("%s: failed backplane access over SDIO, halting operation\n",
++				__FUNCTION__));
++			bus->dhd->busstate = DHD_BUS_DOWN;
++			bus->intstatus = 0;
++		}
++	} else if (bus->clkstate == CLK_PENDING) {
++		/* Awaiting I_CHIPACTIVE; don't resched */
++	} else if (bus->intstatus || bus->ipend ||
++	           (!bus->fcstate && pktq_mlen(&bus->txq, ~bus->flowcontrol) && DATAOK(bus)) ||
++			PKT_AVAILABLE(bus, bus->intstatus)) {  /* Read multiple frames */
++		resched = TRUE;
++	}
++
++	bus->dpc_sched = resched;
++
++	/* If we're done for now, turn off clock request. */
++	if ((bus->idletime == DHD_IDLE_IMMEDIATE) && (bus->clkstate != CLK_PENDING)) {
++		bus->activity = FALSE;
++		dhdsdio_bussleep(bus, TRUE);
++		dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++	}
++
++exit:
++
++	if (!resched && dhd_dpcpoll) {
++		if (dhdsdio_readframes(bus, dhd_rxbound, &rxdone) != 0) {
++			resched = TRUE;
++		}
++	}
++
++	dhd_os_sdunlock(bus->dhd);
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	bus->dhd->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_DPC;
++	dhd_os_busbusy_wake(bus->dhd);
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++	return resched;
++}
++
++bool
++dhd_bus_dpc(struct dhd_bus *bus)
++{
++	bool resched;
++
++	/* Call the DPC directly. */
++	DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __FUNCTION__));
++	resched = dhdsdio_dpc(bus);
++
++	return resched;
++}
++
++#ifdef SDTEST
++static void
++dhdsdio_pktgen_init(dhd_bus_t *bus)
++{
++	/* Default to specified length, or full range */
++	if (dhd_pktgen_len) {
++		bus->pktgen_maxlen = MIN(dhd_pktgen_len, MAX_PKTGEN_LEN);
++		bus->pktgen_minlen = bus->pktgen_maxlen;
++	} else {
++		bus->pktgen_maxlen = MAX_PKTGEN_LEN;
++		bus->pktgen_minlen = 0;
++	}
++	bus->pktgen_len = (uint16)bus->pktgen_minlen;
++
++	/* Default to per-watchdog burst with 10s print time */
++	bus->pktgen_freq = 1;
++	bus->pktgen_print = dhd_watchdog_ms ? (10000 / dhd_watchdog_ms) : 0;
++	bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
++
++	/* Default to echo mode */
++	bus->pktgen_mode = DHD_PKTGEN_ECHO;
++	bus->pktgen_stop = 1;
++}
++
++static void
++dhdsdio_pktgen(dhd_bus_t *bus)
++{
++	void *pkt;
++	uint8 *data;
++	uint pktcount;
++	uint fillbyte;
++	osl_t *osh = bus->dhd->osh;
++	uint16 len;
++	ulong time_lapse;
++	uint sent_pkts;
++	uint rcvd_pkts;
++
++	/* Display current count if appropriate */
++	if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
++		bus->pktgen_ptick = 0;
++		printf("%s: send attempts %d, rcvd %d, errors %d\n",
++		       __FUNCTION__, bus->pktgen_sent, bus->pktgen_rcvd, bus->pktgen_fail);
++
++		/* Print throughput stats only for constant length packet runs */
++		if (bus->pktgen_minlen == bus->pktgen_maxlen) {
++			time_lapse = jiffies - bus->pktgen_prev_time;
++			bus->pktgen_prev_time = jiffies;
++			sent_pkts = bus->pktgen_sent - bus->pktgen_prev_sent;
++			bus->pktgen_prev_sent = bus->pktgen_sent;
++			rcvd_pkts = bus->pktgen_rcvd - bus->pktgen_prev_rcvd;
++			bus->pktgen_prev_rcvd = bus->pktgen_rcvd;
++
++			printf("%s: Tx Throughput %d kbps, Rx Throughput %d kbps\n",
++			  __FUNCTION__,
++			  (sent_pkts * bus->pktgen_len / jiffies_to_msecs(time_lapse)) * 8,
++			  (rcvd_pkts * bus->pktgen_len  / jiffies_to_msecs(time_lapse)) * 8);
++		}
++	}
++
++	/* For recv mode, just make sure dongle has started sending */
++	if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
++		if (bus->pktgen_rcv_state == PKTGEN_RCV_IDLE) {
++			bus->pktgen_rcv_state = PKTGEN_RCV_ONGOING;
++			dhdsdio_sdtest_set(bus, bus->pktgen_total);
++		}
++		return;
++	}
++
++	/* Otherwise, generate or request the specified number of packets */
++	for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
++		/* Stop if total has been reached */
++		if (bus->pktgen_total && (bus->pktgen_sent >= bus->pktgen_total)) {
++			bus->pktgen_count = 0;
++			break;
++		}
++
++		/* Allocate an appropriate-sized packet */
++		if (bus->pktgen_mode == DHD_PKTGEN_RXBURST) {
++			len = SDPCM_TEST_PKT_CNT_FLD_LEN;
++		} else {
++			len = bus->pktgen_len;
++		}
++		if (!(pkt = PKTGET(osh, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
++		                   TRUE))) {;
++			DHD_ERROR(("%s: PKTGET failed!\n", __FUNCTION__));
++			break;
++		}
++		PKTALIGN(osh, pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
++		data = (uint8*)PKTDATA(osh, pkt) + SDPCM_HDRLEN;
++
++		/* Write test header cmd and extra based on mode */
++		switch (bus->pktgen_mode) {
++		case DHD_PKTGEN_ECHO:
++			*data++ = SDPCM_TEST_ECHOREQ;
++			*data++ = (uint8)bus->pktgen_sent;
++			break;
++
++		case DHD_PKTGEN_SEND:
++			*data++ = SDPCM_TEST_DISCARD;
++			*data++ = (uint8)bus->pktgen_sent;
++			break;
++
++		case DHD_PKTGEN_RXBURST:
++			*data++ = SDPCM_TEST_BURST;
++			*data++ = (uint8)bus->pktgen_count; /* Just for backward compatability */
++			break;
++
++		default:
++			DHD_ERROR(("Unrecognized pktgen mode %d\n", bus->pktgen_mode));
++			PKTFREE(osh, pkt, TRUE);
++			bus->pktgen_count = 0;
++			return;
++		}
++
++		/* Write test header length field */
++		*data++ = (bus->pktgen_len >> 0);
++		*data++ = (bus->pktgen_len >> 8);
++
++		/* Write frame count in a 4 byte field adjucent to SDPCM test header for
++		 * burst mode
++		 */
++		if (bus->pktgen_mode == DHD_PKTGEN_RXBURST) {
++			*data++ = (uint8)(bus->pktgen_count >> 0);
++			*data++ = (uint8)(bus->pktgen_count >> 8);
++			*data++ = (uint8)(bus->pktgen_count >> 16);
++			*data++ = (uint8)(bus->pktgen_count >> 24);
++		} else {
++
++			/* Then fill in the remainder -- N/A for burst */
++			for (fillbyte = 0; fillbyte < len; fillbyte++)
++				*data++ = SDPCM_TEST_FILL(fillbyte, (uint8)bus->pktgen_sent);
++		}
++
++#ifdef DHD_DEBUG
++		if (DHD_BYTES_ON() && DHD_DATA_ON()) {
++			data = (uint8*)PKTDATA(osh, pkt) + SDPCM_HDRLEN;
++			prhex("dhdsdio_pktgen: Tx Data", data, PKTLEN(osh, pkt) - SDPCM_HDRLEN);
++		}
++#endif
++
++		/* Send it */
++		if (dhdsdio_txpkt(bus, SDPCM_TEST_CHANNEL, &pkt, 1, TRUE) != BCME_OK) {
++			bus->pktgen_fail++;
++			if (bus->pktgen_stop && bus->pktgen_stop == bus->pktgen_fail)
++				bus->pktgen_count = 0;
++		}
++		bus->pktgen_sent++;
++
++		/* Bump length if not fixed, wrap at max */
++		if (++bus->pktgen_len > bus->pktgen_maxlen)
++			bus->pktgen_len = (uint16)bus->pktgen_minlen;
++
++		/* Special case for burst mode: just send one request! */
++		if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
++			break;
++	}
++}
++
++static void
++dhdsdio_sdtest_set(dhd_bus_t *bus, uint count)
++{
++	void *pkt;
++	uint8 *data;
++	osl_t *osh = bus->dhd->osh;
++
++	/* Allocate the packet */
++	if (!(pkt = PKTGET(osh, SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
++		SDPCM_TEST_PKT_CNT_FLD_LEN + DHD_SDALIGN, TRUE))) {
++		DHD_ERROR(("%s: PKTGET failed!\n", __FUNCTION__));
++		return;
++	}
++	PKTALIGN(osh, pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
++		SDPCM_TEST_PKT_CNT_FLD_LEN), DHD_SDALIGN);
++	data = (uint8*)PKTDATA(osh, pkt) + SDPCM_HDRLEN;
++
++	/* Fill in the test header */
++	*data++ = SDPCM_TEST_SEND;
++	*data++ = (count > 0)?TRUE:FALSE;
++	*data++ = (bus->pktgen_maxlen >> 0);
++	*data++ = (bus->pktgen_maxlen >> 8);
++	*data++ = (uint8)(count >> 0);
++	*data++ = (uint8)(count >> 8);
++	*data++ = (uint8)(count >> 16);
++	*data++ = (uint8)(count >> 24);
++
++	/* Send it */
++	if (dhdsdio_txpkt(bus, SDPCM_TEST_CHANNEL, &pkt, 1, TRUE) != BCME_OK)
++		bus->pktgen_fail++;
++}
++
++
++static void
++dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq)
++{
++	osl_t *osh = bus->dhd->osh;
++	uint8 *data;
++	uint pktlen;
++
++	uint8 cmd;
++	uint8 extra;
++	uint16 len;
++	uint16 offset;
++
++	/* Check for min length */
++	if ((pktlen = PKTLEN(osh, pkt)) < SDPCM_TEST_HDRLEN) {
++		DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n", pktlen));
++		PKTFREE(osh, pkt, FALSE);
++		return;
++	}
++
++	/* Extract header fields */
++	data = PKTDATA(osh, pkt);
++	cmd = *data++;
++	extra = *data++;
++	len = *data++; len += *data++ << 8;
++	DHD_TRACE(("%s:cmd:%d, xtra:%d,len:%d\n", __FUNCTION__, cmd, extra, len));
++	/* Check length for relevant commands */
++	if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ || cmd == SDPCM_TEST_ECHORSP) {
++		if (pktlen != len + SDPCM_TEST_HDRLEN) {
++			DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, pktlen %d seq %d"
++			           " cmd %d extra %d len %d\n", pktlen, seq, cmd, extra, len));
++			PKTFREE(osh, pkt, FALSE);
++			return;
++		}
++	}
++
++	/* Process as per command */
++	switch (cmd) {
++	case SDPCM_TEST_ECHOREQ:
++		/* Rx->Tx turnaround ok (even on NDIS w/current implementation) */
++		*(uint8 *)(PKTDATA(osh, pkt)) = SDPCM_TEST_ECHORSP;
++		if (dhdsdio_txpkt(bus, SDPCM_TEST_CHANNEL, &pkt, 1, TRUE) == BCME_OK) {
++			bus->pktgen_sent++;
++		} else {
++			bus->pktgen_fail++;
++			PKTFREE(osh, pkt, FALSE);
++		}
++		bus->pktgen_rcvd++;
++		break;
++
++	case SDPCM_TEST_ECHORSP:
++		if (bus->ext_loop) {
++			PKTFREE(osh, pkt, FALSE);
++			bus->pktgen_rcvd++;
++			break;
++		}
++
++		for (offset = 0; offset < len; offset++, data++) {
++			if (*data != SDPCM_TEST_FILL(offset, extra)) {
++				DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: "
++				           "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
++				           offset, len, SDPCM_TEST_FILL(offset, extra), *data));
++				break;
++			}
++		}
++		PKTFREE(osh, pkt, FALSE);
++		bus->pktgen_rcvd++;
++		break;
++
++	case SDPCM_TEST_DISCARD:
++		{
++			int i = 0;
++			uint8 *prn = data;
++			uint8 testval = extra;
++			for (i = 0; i < len; i++) {
++				if (*prn != testval) {
++					DHD_ERROR(("DIErr@Pkt#:%d,Ix:%d, expected:0x%x, got:0x%x\n",
++						i, bus->pktgen_rcvd_rcvsession, testval, *prn));
++					prn++; testval++;
++				}
++			}
++		}
++		PKTFREE(osh, pkt, FALSE);
++		bus->pktgen_rcvd++;
++		break;
++
++	case SDPCM_TEST_BURST:
++	case SDPCM_TEST_SEND:
++	default:
++		DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, pktlen %d seq %d"
++		          " cmd %d extra %d len %d\n", pktlen, seq, cmd, extra, len));
++		PKTFREE(osh, pkt, FALSE);
++		break;
++	}
++
++	/* For recv mode, stop at limit (and tell dongle to stop sending) */
++	if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
++		if (bus->pktgen_rcv_state != PKTGEN_RCV_IDLE) {
++			bus->pktgen_rcvd_rcvsession++;
++
++			if (bus->pktgen_total &&
++				(bus->pktgen_rcvd_rcvsession >= bus->pktgen_total)) {
++			bus->pktgen_count = 0;
++			DHD_ERROR(("Pktgen:rcv test complete!\n"));
++			bus->pktgen_rcv_state = PKTGEN_RCV_IDLE;
++			dhdsdio_sdtest_set(bus, FALSE);
++				bus->pktgen_rcvd_rcvsession = 0;
++			}
++		}
++	}
++}
++#endif /* SDTEST */
++
++int dhd_bus_oob_intr_register(dhd_pub_t *dhdp)
++{
++	int err = 0;
++
++#if defined(OOB_INTR_ONLY)
++	err = bcmsdh_oob_intr_register(dhdp->bus->sdh, dhdsdio_isr, dhdp->bus);
++#endif
++	return err;
++}
++
++void dhd_bus_oob_intr_unregister(dhd_pub_t *dhdp)
++{
++#if defined(OOB_INTR_ONLY)
++	bcmsdh_oob_intr_unregister(dhdp->bus->sdh);
++#endif
++}
++
++void dhd_bus_oob_intr_set(dhd_pub_t *dhdp, bool enable)
++{
++#if defined(OOB_INTR_ONLY)
++	bcmsdh_oob_intr_set(dhdp->bus->sdh, enable);
++#endif
++}
++
++void dhd_bus_dev_pm_stay_awake(dhd_pub_t *dhdpub)
++{
++	bcmsdh_dev_pm_stay_awake(dhdpub->bus->sdh);
++}
++
++void dhd_bus_dev_pm_relax(dhd_pub_t *dhdpub)
++{
++	bcmsdh_dev_relax(dhdpub->bus->sdh);
++}
++
++bool dhd_bus_dev_pm_enabled(dhd_pub_t *dhdpub)
++{
++	bool enabled = FALSE;
++
++	enabled = bcmsdh_dev_pm_enabled(dhdpub->bus->sdh);
++	return enabled;
++}
++
++extern bool
++dhd_bus_watchdog(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus;
++	unsigned long flags;
++
++	DHD_TIMER(("%s: Enter\n", __FUNCTION__));
++
++	bus = dhdp->bus;
++
++	if (bus->dhd->dongle_reset)
++		return FALSE;
++
++	if (bus->dhd->hang_was_sent) {
++		dhd_os_wd_timer(bus->dhd, 0);
++		return FALSE;
++	}
++
++	/* Ignore the timer if simulating bus down */
++	if (!SLPAUTO_ENAB(bus) && bus->sleeping)
++		return FALSE;
++
++	DHD_GENERAL_LOCK(dhdp, flags);
++	if (dhdp->busstate == DHD_BUS_DOWN ||
++			dhdp->busstate == DHD_BUS_DOWN_IN_PROGRESS) {
++		DHD_GENERAL_UNLOCK(dhdp, flags);
++		return FALSE;
++	}
++	dhdp->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_WD;
++	DHD_GENERAL_UNLOCK(dhdp, flags);
++
++	dhd_os_sdlock(bus->dhd);
++
++	/* Poll period: check device if appropriate. */
++	if (!SLPAUTO_ENAB(bus) && (bus->poll && (++bus->polltick >= bus->pollrate))) {
++		uint32 intstatus = 0;
++
++		/* Reset poll tick */
++		bus->polltick = 0;
++
++		/* Check device if no interrupts */
++		if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
++
++			if (!bus->dpc_sched) {
++				uint8 devpend;
++				devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
++				                          SDIOD_CCCR_INTPEND, NULL);
++				intstatus = devpend & (INTR_STATUS_FUNC1 | INTR_STATUS_FUNC2);
++			}
++
++			/* If there is something, make like the ISR and schedule the DPC */
++			if (intstatus) {
++				bus->pollcnt++;
++				bus->ipend = TRUE;
++				if (bus->intr) {
++					bcmsdh_intr_disable(bus->sdh);
++				}
++				bus->dpc_sched = TRUE;
++				dhd_sched_dpc(bus->dhd);
++			}
++		}
++
++		/* Update interrupt tracking */
++		bus->lastintrs = bus->intrcount;
++	}
++
++#ifdef DHD_DEBUG
++	/* Poll for console output periodically */
++	if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
++		bus->console.count += dhd_watchdog_ms;
++		if (bus->console.count >= dhd_console_ms) {
++			bus->console.count -= dhd_console_ms;
++			/* Make sure backplane clock is on */
++			if (SLPAUTO_ENAB(bus))
++				dhdsdio_bussleep(bus, FALSE);
++			else
++			dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++			if (dhdsdio_readconsole(bus) < 0)
++				dhd_console_ms = 0;	/* On error, stop trying */
++		}
++	}
++#endif /* DHD_DEBUG */
++
++#ifdef SDTEST
++	/* Generate packets if configured */
++	if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
++		/* Make sure backplane clock is on */
++		if (SLPAUTO_ENAB(bus))
++			dhdsdio_bussleep(bus, FALSE);
++		else
++			dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++		bus->pktgen_tick = 0;
++		dhdsdio_pktgen(bus);
++	}
++#endif
++
++	/* On idle timeout clear activity flag and/or turn off clock */
++#ifdef DHD_USE_IDLECOUNT
++	if (bus->activity)
++		bus->activity = FALSE;
++	else {
++		bus->idlecount++;
++
++		if ((bus->idletime > 0) && (bus->idlecount >= bus->idletime)) {
++
++			DHD_TIMER(("%s: DHD Idle state!!\n", __FUNCTION__));
++			if (SLPAUTO_ENAB(bus)) {
++				if (dhdsdio_bussleep(bus, TRUE) != BCME_BUSY)
++					dhd_os_wd_timer(bus->dhd, 0);
++			} else
++				dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++
++			bus->idlecount = 0;
++		}
++	}
++#else
++	if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
++		if (++bus->idlecount >= bus->idletime) {
++			bus->idlecount = 0;
++			if (bus->activity) {
++				bus->activity = FALSE;
++				if (SLPAUTO_ENAB(bus)) {
++					if (!bus->readframes)
++						dhdsdio_bussleep(bus, TRUE);
++					else
++						bus->reqbussleep = TRUE;
++				}
++				else
++					dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++			}
++		}
++	}
++#endif /* DHD_USE_IDLECOUNT */
++
++	dhd_os_sdunlock(bus->dhd);
++
++	DHD_GENERAL_LOCK(dhdp, flags);
++	dhdp->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_WD;
++	DHD_GENERAL_UNLOCK(dhdp, flags);
++
++	return bus->ipend;
++}
++
++#ifdef DHD_DEBUG
++extern int
++dhd_bus_console_in(dhd_pub_t *dhdp, uchar *msg, uint msglen)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	uint32 addr, val;
++	int rv;
++	void *pkt;
++
++	/* Address could be zero if CONSOLE := 0 in dongle Makefile */
++	if (bus->console_addr == 0)
++		return BCME_UNSUPPORTED;
++
++	/* Exclusive bus access */
++	dhd_os_sdlock(bus->dhd);
++
++	/* Don't allow input if dongle is in reset */
++	if (bus->dhd->dongle_reset) {
++		dhd_os_sdunlock(bus->dhd);
++		return BCME_NOTREADY;
++	}
++
++	/* Request clock to allow SDIO accesses */
++	BUS_WAKE(bus);
++	/* No pend allowed since txpkt is called later, ht clk has to be on */
++	dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++	/* Zero cbuf_index */
++	addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf_idx);
++	val = htol32(0);
++	if ((rv = dhdsdio_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0)
++		goto done;
++
++	/* Write message into cbuf */
++	addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf);
++	if ((rv = dhdsdio_membytes(bus, TRUE, addr, (uint8 *)msg, msglen)) < 0)
++		goto done;
++
++	/* Write length into vcons_in */
++	addr = bus->console_addr + OFFSETOF(hnd_cons_t, vcons_in);
++	val = htol32(msglen);
++	if ((rv = dhdsdio_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0)
++		goto done;
++
++	/* Bump dongle by sending an empty packet on the event channel.
++	 * sdpcm_sendup (RX) checks for virtual console input.
++	 */
++	if ((pkt = PKTGET(bus->dhd->osh, 4 + SDPCM_RESERVE, TRUE)) != NULL)
++		rv = dhdsdio_txpkt(bus, SDPCM_EVENT_CHANNEL, &pkt, 1, TRUE);
++
++done:
++	if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
++		bus->activity = FALSE;
++		dhdsdio_bussleep(bus, TRUE);
++		dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++	}
++
++	dhd_os_sdunlock(bus->dhd);
++
++	return rv;
++}
++#endif /* DHD_DEBUG */
++
++#ifdef DHD_DEBUG
++static void
++dhd_dump_cis(uint fn, uint8 *cis)
++{
++	uint byte, tag, tdata;
++	DHD_INFO(("Function %d CIS:\n", fn));
++
++	for (tdata = byte = 0; byte < SBSDIO_CIS_SIZE_LIMIT; byte++) {
++		if ((byte % 16) == 0)
++			DHD_INFO(("    "));
++		DHD_INFO(("%02x ", cis[byte]));
++		if ((byte % 16) == 15)
++			DHD_INFO(("\n"));
++		if (!tdata--) {
++			tag = cis[byte];
++			if (tag == 0xff)
++				break;
++			else if (!tag)
++				tdata = 0;
++			else if ((byte + 1) < SBSDIO_CIS_SIZE_LIMIT)
++				tdata = cis[byte + 1] + 1;
++			else
++				DHD_INFO(("]"));
++		}
++	}
++	if ((byte % 16) != 15)
++		DHD_INFO(("\n"));
++}
++#endif /* DHD_DEBUG */
++
++static bool
++dhdsdio_chipmatch(uint16 chipid)
++{
++	if (chipid == BCM4325_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4329_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4315_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4319_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4336_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4330_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43237_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43362_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4314_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43242_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43340_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43341_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43143_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43342_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4334_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43239_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4324_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4335_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4339_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43349_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4345_CHIP_ID || chipid == BCM43454_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4350_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4354_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4356_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM4358_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43430_CHIP_ID)
++		return TRUE;
++	if (chipid == BCM43018_CHIP_ID)
++		return TRUE;
++	if (BCM4349_CHIP(chipid))
++		return TRUE;
++	if (chipid == BCM43012_CHIP_ID)
++		return TRUE;
++	return FALSE;
++}
++
++static void *
++dhdsdio_probe(uint16 venid, uint16 devid, uint16 bus_no, uint16 slot,
++	uint16 func, uint bustype, void *regsva, osl_t * osh, void *sdh)
++{
++	int ret;
++	dhd_bus_t *bus;
++
++
++	/* Init global variables at run-time, not as part of the declaration.
++	 * This is required to support init/de-init of the driver. Initialization
++	 * of globals as part of the declaration results in non-deterministic
++	 * behavior since the value of the globals may be different on the
++	 * first time that the driver is initialized vs subsequent initializations.
++	 */
++	dhd_txbound = DHD_TXBOUND;
++	dhd_rxbound = DHD_RXBOUND;
++	dhd_alignctl = TRUE;
++	sd1idle = TRUE;
++	dhd_readahead = TRUE;
++	retrydata = FALSE;
++
++	dhd_doflow = FALSE;
++	dhd_dongle_ramsize = 0;
++	dhd_txminmax = DHD_TXMINMAX;
++
++	forcealign = TRUE;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++	DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __FUNCTION__, venid, devid));
++
++	/* We make assumptions about address window mappings */
++	ASSERT((uintptr)regsva == SI_ENUM_BASE);
++
++	/* BCMSDH passes venid and devid based on CIS parsing -- but low-power start
++	 * means early parse could fail, so here we should get either an ID
++	 * we recognize OR (-1) indicating we must request power first.
++	 */
++	/* Check the Vendor ID */
++	switch (venid) {
++		case 0x0000:
++		case VENDOR_BROADCOM:
++			break;
++		default:
++			DHD_ERROR(("%s: unknown vendor: 0x%04x\n",
++			           __FUNCTION__, venid));
++			goto forcereturn;
++	}
++
++	/* Check the Device ID and make sure it's one that we support */
++	switch (devid) {
++		case BCM4325_D11DUAL_ID:		/* 4325 802.11a/g id */
++		case BCM4325_D11G_ID:			/* 4325 802.11g 2.4Ghz band id */
++		case BCM4325_D11A_ID:			/* 4325 802.11a 5Ghz band id */
++			DHD_INFO(("%s: found 4325 Dongle\n", __FUNCTION__));
++			break;
++		case BCM4329_D11N_ID:		/* 4329 802.11n dualband device */
++		case BCM4329_D11N2G_ID:		/* 4329 802.11n 2.4G device */
++		case BCM4329_D11N5G_ID:		/* 4329 802.11n 5G device */
++		case 0x4329:
++			DHD_INFO(("%s: found 4329 Dongle\n", __FUNCTION__));
++			break;
++		case BCM4315_D11DUAL_ID:		/* 4315 802.11a/g id */
++		case BCM4315_D11G_ID:			/* 4315 802.11g id */
++		case BCM4315_D11A_ID:			/* 4315 802.11a id */
++			DHD_INFO(("%s: found 4315 Dongle\n", __FUNCTION__));
++			break;
++		case BCM4319_D11N_ID:			/* 4319 802.11n id */
++		case BCM4319_D11N2G_ID:			/* 4319 802.11n2g id */
++		case BCM4319_D11N5G_ID:			/* 4319 802.11n5g id */
++			DHD_INFO(("%s: found 4319 Dongle\n", __FUNCTION__));
++			break;
++		case 0:
++			DHD_INFO(("%s: allow device id 0, will check chip internals\n",
++			          __FUNCTION__));
++			break;
++
++		default:
++			DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
++			           __FUNCTION__, venid, devid));
++			goto forcereturn;
++	}
++
++	if (osh == NULL) {
++		DHD_ERROR(("%s: osh is NULL!\n", __FUNCTION__));
++		goto forcereturn;
++	}
++
++	/* Allocate private bus interface state */
++	if (!(bus = MALLOC(osh, sizeof(dhd_bus_t)))) {
++		DHD_ERROR(("%s: MALLOC of dhd_bus_t failed\n", __FUNCTION__));
++		goto fail;
++	}
++	bzero(bus, sizeof(dhd_bus_t));
++	bus->sdh = sdh;
++	bus->cl_devid = (uint16)devid;
++	bus->bus = DHD_BUS;
++	bus->bus_num = bus_no;
++	bus->slot_num = slot;
++	bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
++	bus->usebufpool = FALSE; /* Use bufpool if allocated, else use locally malloced rxbuf */
++
++#if defined(SUPPORT_P2P_GO_PS) || defined(SUSPEND16)
++	init_waitqueue_head(&bus->bus_sleep);
++#endif /* LINUX && SUPPORT_P2P_GO_PS */
++
++	/* attempt to attach to the dongle */
++	if (!(dhdsdio_probe_attach(bus, osh, sdh, regsva, devid))) {
++		DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __FUNCTION__));
++		goto fail;
++	}
++
++	/* Attach to the dhd/OS/network interface */
++	if (!(bus->dhd = dhd_attach(osh, bus, SDPCM_RESERVE))) {
++		DHD_ERROR(("%s: dhd_attach failed\n", __FUNCTION__));
++		goto fail;
++	}
++
++	/* Allocate buffers */
++	if (!(dhdsdio_probe_malloc(bus, osh, sdh))) {
++		DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __FUNCTION__));
++		goto fail;
++	}
++
++	if (!(dhdsdio_probe_init(bus, osh, sdh))) {
++		DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __FUNCTION__));
++		goto fail;
++	}
++
++	if (bus->intr) {
++		/* Register interrupt callback, but mask it (not operational yet). */
++		DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n", __FUNCTION__));
++		bcmsdh_intr_disable(sdh);
++		if ((ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus)) != 0) {
++			DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
++			           __FUNCTION__, ret));
++			goto fail;
++		}
++		DHD_INTR(("%s: registered SDIO interrupt function ok\n", __FUNCTION__));
++	} else {
++		DHD_INFO(("%s: SDIO interrupt function is NOT registered due to polling mode\n",
++		           __FUNCTION__));
++	}
++
++	DHD_INFO(("%s: completed!!\n", __FUNCTION__));
++
++	/* if firmware path present try to download and bring up bus */
++	bus->dhd->hang_report  = TRUE;
++	if (dhd_download_fw_on_driverload) {
++		if ((ret = dhd_bus_start(bus->dhd)) != 0) {
++			DHD_ERROR(("%s: dhd_bus_start failed\n", __FUNCTION__));
++				goto fail;
++		}
++	}
++	/* Ok, have the per-port tell the stack we're open for business */
++	if (dhd_register_if(bus->dhd, 0, TRUE) != 0) {
++		DHD_ERROR(("%s: Net attach failed!!\n", __FUNCTION__));
++		goto fail;
++	}
++
++
++
++	return bus;
++
++fail:
++	dhdsdio_release(bus, osh);
++
++forcereturn:
++
++	return NULL;
++}
++
++static bool
++dhdsdio_probe_attach(struct dhd_bus *bus, osl_t *osh, void *sdh, void *regsva,
++                     uint16 devid)
++{
++	int err = 0;
++	uint8 clkctl = 0;
++
++	bus->alp_only = TRUE;
++	bus->sih = NULL;
++
++	/* Return the window to backplane enumeration space for core access */
++	if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE)) {
++		DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __FUNCTION__));
++	}
++
++#if defined(DHD_DEBUG)
++	DHD_ERROR(("F1 signature read @0x18000000=0x%4x\n",
++		bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4)));
++#endif 
++
++
++	/* Force PLL off until si_attach() programs PLL control regs */
++
++
++
++#ifdef LOAD_DHD_WITH_FW_ALIVE
++	if(alive != FW_ALIVE_MAGIC)
++#endif
++	{
++		bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, DHD_INIT_CLKCTL1, &err);
++		if (!err)
++			clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
++
++		if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
++			DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
++				   err, DHD_INIT_CLKCTL1, clkctl));
++			goto fail;
++		}
++	}
++
++#ifdef DHD_DEBUG
++	if (DHD_INFO_ON()) {
++		uint fn, numfn;
++		uint8 *cis[SDIOD_MAX_IOFUNCS];
++		int err = 0;
++
++		numfn = bcmsdh_query_iofnum(sdh);
++		ASSERT(numfn <= SDIOD_MAX_IOFUNCS);
++
++		/* Make sure ALP is available before trying to read CIS */
++		SPINWAIT(((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
++		                                    SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
++		          !SBSDIO_ALPAV(clkctl)), PMU_MAX_TRANSITION_DLY);
++
++		/* Now request ALP be put on the bus */
++		bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
++		                 DHD_INIT_CLKCTL2, &err);
++		OSL_DELAY(65);
++
++		for (fn = 0; fn <= numfn; fn++) {
++			if (!(cis[fn] = MALLOC(osh, SBSDIO_CIS_SIZE_LIMIT))) {
++				DHD_INFO(("dhdsdio_probe: fn %d cis malloc failed\n", fn));
++				break;
++			}
++			bzero(cis[fn], SBSDIO_CIS_SIZE_LIMIT);
++
++			if ((err = bcmsdh_cis_read(sdh, fn, cis[fn], SBSDIO_CIS_SIZE_LIMIT))) {
++				DHD_INFO(("dhdsdio_probe: fn %d cis read err %d\n", fn, err));
++				MFREE(osh, cis[fn], SBSDIO_CIS_SIZE_LIMIT);
++				break;
++			}
++			dhd_dump_cis(fn, cis[fn]);
++		}
++
++		while (fn-- > 0) {
++			ASSERT(cis[fn]);
++			MFREE(osh, cis[fn], SBSDIO_CIS_SIZE_LIMIT);
++		}
++
++		if (err) {
++			DHD_ERROR(("dhdsdio_probe: failure reading or parsing CIS\n"));
++			goto fail;
++		}
++	}
++#endif /* DHD_DEBUG */
++
++	/* si_attach() will provide an SI handle and scan the backplane */
++	if (!(bus->sih = si_attach((uint)devid, osh, regsva, DHD_BUS, sdh,
++	                           &bus->vars, &bus->varsz))) {
++		DHD_ERROR(("%s: si_attach failed!\n", __FUNCTION__));
++		goto fail;
++	}
++
++#ifdef DHD_DEBUG
++	DHD_ERROR(("F1 signature OK, socitype:0x%x chip:0x%4x rev:0x%x pkg:0x%x\n",
++		bus->sih->socitype, bus->sih->chip, bus->sih->chiprev, bus->sih->chippkg));
++#endif /* DHD_DEBUG */
++
++#ifdef LOAD_DHD_WITH_FW_ALIVE
++	card_dev = bus->sih->chip;
++	card_rev = bus->sih->chiprev;
++#endif
++
++
++	bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev);
++
++	if (!dhdsdio_chipmatch((uint16)bus->sih->chip)) {
++		DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
++		           __FUNCTION__, bus->sih->chip));
++		goto fail;
++	}
++
++	if (bus->sih->buscorerev >= 12)
++		dhdsdio_clk_kso_init(bus);
++	else
++		bus->kso = TRUE;
++
++	if (CST4330_CHIPMODE_SDIOD(bus->sih->chipst)) {
++	}
++
++	si_sdiod_drive_strength_init(bus->sih, osh, dhd_sdiod_drive_strength);
++
++
++	/* Get info on the ARM and SOCRAM cores... */
++	if (!DHD_NOPMU(bus)) {
++		if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
++		    (si_setcore(bus->sih, ARMCM3_CORE_ID, 0)) ||
++		    (si_setcore(bus->sih, ARMCR4_CORE_ID, 0))) {
++			bus->armrev = si_corerev(bus->sih);
++		} else {
++			DHD_ERROR(("%s: failed to find ARM core!\n", __FUNCTION__));
++			goto fail;
++		}
++
++		if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
++			if (!(bus->orig_ramsize = si_socram_size(bus->sih))) {
++				DHD_ERROR(("%s: failed to find SOCRAM memory!\n", __FUNCTION__));
++				goto fail;
++			}
++		} else {
++			/* cr4 has a different way to find the RAM size from TCM's */
++			if (!(bus->orig_ramsize = si_tcm_size(bus->sih))) {
++				DHD_ERROR(("%s: failed to find CR4-TCM memory!\n", __FUNCTION__));
++				goto fail;
++			}
++			/* also populate base address */
++			switch ((uint16)bus->sih->chip) {
++			case BCM4335_CHIP_ID:
++			case BCM4339_CHIP_ID:
++			case BCM43349_CHIP_ID:
++				bus->dongle_ram_base = CR4_4335_RAM_BASE;
++				break;
++			case BCM4350_CHIP_ID:
++			case BCM4354_CHIP_ID:
++			case BCM4356_CHIP_ID:
++			case BCM4358_CHIP_ID:
++				bus->dongle_ram_base = CR4_4350_RAM_BASE;
++				break;
++			case BCM4360_CHIP_ID:
++				bus->dongle_ram_base = CR4_4360_RAM_BASE;
++				break;
++			case BCM4345_CHIP_ID:
++			case BCM43454_CHIP_ID:
++				bus->dongle_ram_base = (bus->sih->chiprev < 6)  /* from 4345C0 */
++					? CR4_4345_LT_C0_RAM_BASE : CR4_4345_GE_C0_RAM_BASE;
++				break;
++			case BCM4349_CHIP_GRPID:
++				/* RAM base changed from 4349c0(revid=9) onwards */
++				bus->dongle_ram_base = ((bus->sih->chiprev < 9) ?
++				CR4_4349_RAM_BASE: CR4_4349_RAM_BASE_FROM_REV_9);
++				break;
++			default:
++				bus->dongle_ram_base = 0;
++				DHD_ERROR(("%s: WARNING: Using default ram base at 0x%x\n",
++				           __FUNCTION__, bus->dongle_ram_base));
++			}
++		}
++		bus->ramsize = bus->orig_ramsize;
++		if (dhd_dongle_ramsize)
++			dhd_dongle_setramsize(bus, dhd_dongle_ramsize);
++
++		DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d) at 0x%x\n",
++		           bus->ramsize, bus->orig_ramsize, bus->dongle_ram_base));
++
++		bus->srmemsize = si_socram_srmem_size(bus->sih);
++	}
++
++	/* ...but normally deal with the SDPCMDEV core */
++	if (!(bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0)) &&
++	    !(bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0))) {
++		DHD_ERROR(("%s: failed to find SDIODEV core!\n", __FUNCTION__));
++		goto fail;
++	}
++	bus->sdpcmrev = si_corerev(bus->sih);
++
++	/* Set core control so an SDIO reset does a backplane reset */
++	OR_REG(osh, &bus->regs->corecontrol, CC_BPRESEN);
++	bus->rxint_mode = SDIO_DEVICE_HMB_RXINT;
++
++	if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev >= 4) &&
++		(bus->rxint_mode  == SDIO_DEVICE_RXDATAINT_MODE_1))
++	{
++		uint32 val;
++
++		val = R_REG(osh, &bus->regs->corecontrol);
++		val &= ~CC_XMTDATAAVAIL_MODE;
++		val |= CC_XMTDATAAVAIL_CTRL;
++		W_REG(osh, &bus->regs->corecontrol, val);
++	}
++
++
++	pktq_init(&bus->txq, (PRIOMASK + 1), QLEN);
++
++	/* Locate an appropriately-aligned portion of hdrbuf */
++	bus->rxhdr = (uint8 *)ROUNDUP((uintptr)&bus->hdrbuf[0], DHD_SDALIGN);
++
++	/* Set the poll and/or interrupt flags */
++	bus->intr = (bool)dhd_intr;
++	if ((bus->poll = (bool)dhd_poll))
++		bus->pollrate = 1;
++
++	/* Setting default Glom size */
++	bus->txglomsize = SDPCM_DEFGLOM_SIZE;
++
++	return TRUE;
++
++fail:
++	if (bus->sih != NULL) {
++		si_detach(bus->sih);
++		bus->sih = NULL;
++	}
++	return FALSE;
++}
++
++static bool
++dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh)
++{
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus->dhd->maxctl) {
++		bus->rxblen = ROUNDUP((bus->dhd->maxctl+SDPCM_HDRLEN), ALIGNMENT) + DHD_SDALIGN;
++		if (!(bus->rxbuf = DHD_OS_PREALLOC(bus->dhd, DHD_PREALLOC_RXBUF, bus->rxblen))) {
++			DHD_ERROR(("%s: MALLOC of %d-byte rxbuf failed\n",
++			           __FUNCTION__, bus->rxblen));
++			goto fail;
++		}
++	}
++	/* Allocate buffer to receive glomed packet */
++	if (!(bus->databuf = DHD_OS_PREALLOC(bus->dhd, DHD_PREALLOC_DATABUF, MAX_DATA_BUF))) {
++		DHD_ERROR(("%s: MALLOC of %d-byte databuf failed\n",
++			__FUNCTION__, MAX_DATA_BUF));
++		/* release rxbuf which was already located as above */
++		if (!bus->rxblen)
++			DHD_OS_PREFREE(bus->dhd, bus->rxbuf, bus->rxblen);
++		goto fail;
++	}
++
++	/* Align the buffer */
++	if ((uintptr)bus->databuf % DHD_SDALIGN)
++		bus->dataptr = bus->databuf + (DHD_SDALIGN - ((uintptr)bus->databuf % DHD_SDALIGN));
++	else
++		bus->dataptr = bus->databuf;
++
++	return TRUE;
++
++fail:
++	return FALSE;
++}
++
++static bool
++dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh)
++{
++	int32 fnum;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	bus->_srenab = FALSE;
++
++#ifdef SDTEST
++	dhdsdio_pktgen_init(bus);
++#endif /* SDTEST */
++
++	/* Disable F2 to clear any intermediate frame state on the dongle */
++	bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1, NULL);
++
++	bus->dhd->busstate = DHD_BUS_DOWN;
++	bus->sleeping = FALSE;
++	bus->rxflow = FALSE;
++	bus->prev_rxlim_hit = 0;
++
++	/* Done with backplane-dependent accesses, can drop clock... */
++	bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
++
++	/* ...and initialize clock/power states */
++	bus->clkstate = CLK_SDONLY;
++	bus->idletime = (int32)dhd_idletime;
++	bus->idleclock = DHD_IDLE_ACTIVE;
++
++	/* Query the SD clock speed */
++	if (bcmsdh_iovar_op(sdh, "sd_divisor", NULL, 0,
++	                    &bus->sd_divisor, sizeof(int32), FALSE) != BCME_OK) {
++		DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_divisor"));
++		bus->sd_divisor = -1;
++	} else {
++		DHD_INFO(("%s: Initial value for %s is %d\n",
++		          __FUNCTION__, "sd_divisor", bus->sd_divisor));
++	}
++
++	/* Query the SD bus mode */
++	if (bcmsdh_iovar_op(sdh, "sd_mode", NULL, 0,
++	                    &bus->sd_mode, sizeof(int32), FALSE) != BCME_OK) {
++		DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_mode"));
++		bus->sd_mode = -1;
++	} else {
++		DHD_INFO(("%s: Initial value for %s is %d\n",
++		          __FUNCTION__, "sd_mode", bus->sd_mode));
++	}
++
++	/* Query the F2 block size, set roundup accordingly */
++	fnum = 2;
++	if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(int32),
++	                    &bus->blocksize, sizeof(int32), FALSE) != BCME_OK) {
++		bus->blocksize = 0;
++		DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_blocksize"));
++	} else {
++		DHD_INFO(("%s: Initial value for %s is %d\n",
++		          __FUNCTION__, "sd_blocksize", bus->blocksize));
++
++		dhdsdio_tune_fifoparam(bus);
++	}
++	bus->roundup = MIN(max_roundup, bus->blocksize);
++
++#ifdef DHDENABLE_TAILPAD
++	if (bus->pad_pkt)
++		PKTFREE(osh, bus->pad_pkt, FALSE);
++	bus->pad_pkt = PKTGET(osh, SDIO_MAX_BLOCK_SIZE, FALSE);
++	if (bus->pad_pkt == NULL)
++		DHD_ERROR(("failed to allocate padding packet\n"));
++	else {
++		int alignment_offset = 0;
++		uintptr pktprt = (uintptr)PKTDATA(osh, bus->pad_pkt);
++		if (!(pktprt&1) && (pktprt = (pktprt % DHD_SDALIGN)))
++			PKTPUSH(osh, bus->pad_pkt, alignment_offset);
++		PKTSETNEXT(osh, bus->pad_pkt, NULL);
++	}
++#endif /* DHDENABLE_TAILPAD */
++
++	/* Query if bus module supports packet chaining, default to use if supported */
++	if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
++	                    &bus->sd_rxchain, sizeof(int32), FALSE) != BCME_OK) {
++		bus->sd_rxchain = FALSE;
++	} else {
++		DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
++		          __FUNCTION__, (bus->sd_rxchain ? "supports" : "does not support")));
++	}
++	bus->use_rxchain = (bool)bus->sd_rxchain;
++	bus->txinrx_thres = CUSTOM_TXINRX_THRES;
++	/* TX first in dhdsdio_readframes() */
++	bus->dotxinrx = TRUE;
++
++	return TRUE;
++}
++
++int
++dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh,
++                          char *pfw_path, char *pnv_path)
++{
++	int ret;
++
++	bus->fw_path = pfw_path;
++	bus->nv_path = pnv_path;
++
++	ret = dhdsdio_download_firmware(bus, osh, bus->sdh);
++
++
++	return ret;
++}
++
++static int
++dhdsdio_download_firmware(struct dhd_bus *bus, osl_t *osh, void *sdh)
++{
++	int ret;
++
++
++	DHD_TRACE_HW4(("%s: firmware path=%s, nvram path=%s\n",
++		__FUNCTION__, bus->fw_path, bus->nv_path));
++	DHD_OS_WAKE_LOCK(bus->dhd);
++
++	/* Download the firmware */
++	dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++#ifdef LOAD_DHD_WITH_FW_ALIVE
++	if(alive == FW_ALIVE_MAGIC) {
++		ret = 0;
++		bus->alp_only = FALSE;
++		bus->dhd->busstate = DHD_BUS_LOAD;
++		DHD_ERROR(("skip download FW and nv\n"));
++	}
++	else
++#endif
++		ret = _dhdsdio_download_firmware(bus);
++
++	dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++
++	DHD_OS_WAKE_UNLOCK(bus->dhd);
++	return ret;
++}
++
++/* Detach and free everything */
++static void
++dhdsdio_release(dhd_bus_t *bus, osl_t *osh)
++{
++	bool dongle_isolation = FALSE;
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus) {
++		ASSERT(osh);
++
++		if (bus->dhd) {
++			dongle_isolation = bus->dhd->dongle_isolation;
++			dhd_detach(bus->dhd);
++		}
++
++		/* De-register interrupt handler */
++		bcmsdh_intr_disable(bus->sdh);
++		bcmsdh_intr_dereg(bus->sdh);
++
++		if (bus->dhd) {
++			dhdsdio_release_dongle(bus, osh, dongle_isolation, TRUE);
++			dhd_free(bus->dhd);
++			bus->dhd = NULL;
++		}
++
++		dhdsdio_release_malloc(bus, osh);
++
++#ifdef DHD_DEBUG
++		if (bus->console.buf != NULL)
++			MFREE(osh, bus->console.buf, bus->console.bufsize);
++#endif
++
++#ifdef DHDENABLE_TAILPAD
++		if (bus->pad_pkt)
++			PKTFREE(osh, bus->pad_pkt, FALSE);
++#endif /* DHDENABLE_TAILPAD */
++
++		MFREE(osh, bus, sizeof(dhd_bus_t));
++	}
++
++	DHD_TRACE(("%s: Disconnected\n", __FUNCTION__));
++}
++
++static void
++dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh)
++{
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	if (bus->dhd && bus->dhd->dongle_reset)
++		return;
++
++	if (bus->rxbuf) {
++#ifndef CONFIG_DHD_USE_STATIC_BUF
++		MFREE(osh, bus->rxbuf, bus->rxblen);
++#endif
++		bus->rxctl = bus->rxbuf = NULL;
++		bus->rxlen = 0;
++	}
++
++	if (bus->databuf) {
++#ifndef CONFIG_DHD_USE_STATIC_BUF
++		MFREE(osh, bus->databuf, MAX_DATA_BUF);
++#endif
++		bus->databuf = NULL;
++	}
++
++	if (bus->vars && bus->varsz) {
++		MFREE(osh, bus->vars, bus->varsz);
++		bus->vars = NULL;
++	}
++
++}
++
++
++static void
++dhdsdio_release_dongle(dhd_bus_t *bus, osl_t *osh, bool dongle_isolation, bool reset_flag)
++{
++	DHD_TRACE(("%s: Enter bus->dhd %p bus->dhd->dongle_reset %d \n", __FUNCTION__,
++		bus->dhd, bus->dhd->dongle_reset));
++
++	if ((bus->dhd && bus->dhd->dongle_reset) && reset_flag)
++		return;
++
++	if (bus->sih) {
++#if !defined(BCMLXSDMMC)
++		if (bus->dhd) {
++			dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++		}
++		if (KSO_ENAB(bus) && (dongle_isolation == FALSE))
++			si_watchdog(bus->sih, 4);
++#endif /* !defined(BCMLXSDMMC) */
++		if (bus->dhd) {
++			dhdsdio_clkctl(bus, CLK_NONE, FALSE);
++		}
++		si_detach(bus->sih);
++		bus->sih = NULL;
++		if (bus->vars && bus->varsz)
++			MFREE(osh, bus->vars, bus->varsz);
++		bus->vars = NULL;
++	}
++
++	DHD_TRACE(("%s: Disconnected\n", __FUNCTION__));
++}
++
++static void
++dhdsdio_disconnect(void *ptr)
++{
++	dhd_bus_t *bus = (dhd_bus_t *)ptr;
++
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++
++
++	if (bus) {
++		ASSERT(bus->dhd);
++		dhdsdio_release(bus, bus->dhd->osh);
++	}
++
++
++
++	DHD_TRACE(("%s: Disconnected\n", __FUNCTION__));
++}
++
++static int
++dhdsdio_suspend(void *context)
++{
++	int ret = 0;
++#if defined(SUPPORT_P2P_GO_PS) || defined(SUSPEND16)
++	int wait_time = 0;
++#endif /* SUPPORT_P2P_GO_PS */
++
++	dhd_bus_t *bus = (dhd_bus_t*)context;
++	unsigned long flags;
++
++	if (bus->dhd == NULL) {
++		DHD_ERROR(("bus not inited\n"));
++		return BCME_ERROR;
++	}
++	if (bus->dhd->prot == NULL) {
++		DHD_ERROR(("prot is not inited\n"));
++		return BCME_ERROR;
++	}
++	/*=============added by May 20210204==================*/
++	if (bus->dhd->up == FALSE) {
++		return BCME_OK;
++	}
++	/*=============added by May 20210204==================*/
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	if (bus->dhd->busstate != DHD_BUS_DATA && bus->dhd->busstate != DHD_BUS_SUSPEND) {
++		DHD_ERROR(("not in a readystate to LPBK  is not inited\n"));
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++		return BCME_ERROR;
++	}
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++	if (bus->dhd->dongle_reset) {
++		DHD_ERROR(("Dongle is in reset state.\n"));
++		return -EIO;
++	}
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	bus->dhd->busstate = DHD_BUS_SUSPEND;
++	if (bus->dhd->dhd_bus_busy_state & DHD_BUS_BUSY_IN_TX) {
++		DHD_ERROR(("Tx Request is not ended\n"));
++		bus->dhd->busstate = DHD_BUS_DATA;
++		DHD_GENERAL_UNLOCK(bus->dhd, flags);
++		return -EBUSY;
++	}
++	bus->dhd->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_SUSPEND;
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++#if defined(SUPPORT_P2P_GO_PS) || defined(SUSPEND16)
++	if (bus->idletime > 0) {
++		wait_time = msecs_to_jiffies(bus->idletime * dhd_watchdog_ms);
++	}
++#endif /* SUPPORT_P2P_GO_PS */
++	ret = dhd_os_check_wakelock(bus->dhd);
++#if defined(SUPPORT_P2P_GO_PS) || defined(SUSPEND16)
++	if ((ret) && (bus->dhd->up) && (bus->dhd->op_mode != DHD_FLAG_HOSTAP_MODE)) {
++		if (wait_event_timeout(bus->bus_sleep, bus->sleeping, wait_time) == 0) {
++			if (!bus->sleeping) {
++				return 1;
++			}
++		}
++		return 0;
++	}
++#endif /* SUPPORT_P2P_GO_PS */
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	bus->dhd->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_SUSPEND;
++	dhd_os_busbusy_wake(bus->dhd);
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++	return ret;
++}
++
++static int
++dhdsdio_resume(void *context)
++{
++	dhd_bus_t *bus = (dhd_bus_t*)context;
++	unsigned long flags;
++
++	DHD_GENERAL_LOCK(bus->dhd, flags);
++	bus->dhd->busstate = DHD_BUS_DATA;
++	DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++#if defined(OOB_INTR_ONLY)
++	if (dhd_os_check_if_up(bus->dhd))
++		bcmsdh_oob_intr_set(bus->sdh, TRUE);
++#endif 
++	return 0;
++}
++
++
++/* Register/Unregister functions are called by the main DHD entry
++ * point (e.g. module insertion) to link with the bus driver, in
++ * order to look for or await the device.
++ */
++
++static bcmsdh_driver_t dhd_sdio = {
++	dhdsdio_probe,
++	dhdsdio_disconnect,
++	dhdsdio_suspend,
++	dhdsdio_resume
++};
++
++int
++dhd_bus_register(void)
++{
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	return bcmsdh_register(&dhd_sdio);
++}
++
++void
++dhd_bus_unregister(void)
++{
++	DHD_TRACE(("%s: Enter\n", __FUNCTION__));
++
++	bcmsdh_unregister();
++}
++
++#if defined(BCMLXSDMMC)
++/* Register a dummy SDIO client driver in order to be notified of new SDIO device */
++int dhd_bus_reg_sdio_notify(void* semaphore)
++{
++	return bcmsdh_reg_sdio_notify(semaphore);
++}
++
++void dhd_bus_unreg_sdio_notify(void)
++{
++	bcmsdh_unreg_sdio_notify();
++}
++#endif /* defined(BCMLXSDMMC) */
++
++#ifdef BCMEMBEDIMAGE
++static int
++dhdsdio_download_code_array(struct dhd_bus *bus)
++{
++	int bcmerror = -1;
++	int offset = 0;
++	unsigned char *ularray = NULL;
++
++	DHD_INFO(("%s: download embedded firmware...\n", __FUNCTION__));
++
++	/* Download image */
++	while ((offset + MEMBLOCK) < sizeof(dlarray)) {
++		/* check if CR4 */
++		if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
++			/* if address is 0, store the reset instruction to be written in 0 */
++
++			if (offset == 0) {
++				bus->resetinstr = *(((uint32*)dlarray));
++				/* Add start of RAM address to the address given by user */
++				offset += bus->dongle_ram_base;
++			}
++		}
++
++		bcmerror = dhdsdio_membytes(bus, TRUE, offset,
++			(uint8 *) (dlarray + offset), MEMBLOCK);
++		if (bcmerror) {
++			DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
++			        __FUNCTION__, bcmerror, MEMBLOCK, offset));
++			goto err;
++		}
++
++		offset += MEMBLOCK;
++	}
++
++	if (offset < sizeof(dlarray)) {
++		bcmerror = dhdsdio_membytes(bus, TRUE, offset,
++			(uint8 *) (dlarray + offset), sizeof(dlarray) - offset);
++		if (bcmerror) {
++			DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
++			        __FUNCTION__, bcmerror, sizeof(dlarray) - offset, offset));
++			goto err;
++		}
++	}
++
++#ifdef DHD_DEBUG
++	/* Upload and compare the downloaded code */
++	{
++		ularray = MALLOC(bus->dhd->osh, bus->ramsize);
++		/* Upload image to verify downloaded contents. */
++		offset = 0;
++		memset(ularray, 0xaa, bus->ramsize);
++		while ((offset + MEMBLOCK) < sizeof(dlarray)) {
++			bcmerror = dhdsdio_membytes(bus, FALSE, offset, ularray + offset, MEMBLOCK);
++			if (bcmerror) {
++				DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
++					__FUNCTION__, bcmerror, MEMBLOCK, offset));
++				goto err;
++			}
++
++			offset += MEMBLOCK;
++		}
++
++		if (offset < sizeof(dlarray)) {
++			bcmerror = dhdsdio_membytes(bus, FALSE, offset,
++				ularray + offset, sizeof(dlarray) - offset);
++			if (bcmerror) {
++				DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
++					__FUNCTION__, bcmerror, sizeof(dlarray) - offset, offset));
++				goto err;
++			}
++		}
++
++		if (memcmp(dlarray, ularray, sizeof(dlarray))) {
++			DHD_ERROR(("%s: Downloaded image is corrupted (%s, %s, %s).\n",
++			           __FUNCTION__, dlimagename, dlimagever, dlimagedate));
++			goto err;
++		} else
++			DHD_ERROR(("%s: Download, Upload and compare succeeded (%s, %s, %s).\n",
++			           __FUNCTION__, dlimagename, dlimagever, dlimagedate));
++
++	}
++#endif /* DHD_DEBUG */
++
++err:
++	if (ularray)
++		MFREE(bus->dhd->osh, ularray, bus->ramsize);
++	return bcmerror;
++}
++#endif /* BCMEMBEDIMAGE */
++
++static int
++dhdsdio_download_code_file(struct dhd_bus *bus, char *pfw_path)
++{
++	int bcmerror = -1;
++	int offset = 0;
++	int len;
++	void *image = NULL;
++	uint8 *memblock = NULL, *memptr;
++	uint memblock_size = MEMBLOCK;
++#ifdef DHD_DEBUG_DOWNLOADTIME
++	unsigned long initial_jiffies = 0;
++	uint firmware_sz = 0;
++#endif
++
++	DHD_INFO(("%s: download firmware %s\n", __FUNCTION__, pfw_path));
++
++	image = dhd_os_open_image(pfw_path);
++	if (image == NULL)
++		goto err;
++
++	/* Update the dongle image download block size depending on the F1 block size */
++	if (sd_f1_blocksize == 512)
++		memblock_size = MAX_MEMBLOCK;
++
++	memptr = memblock = MALLOC(bus->dhd->osh, memblock_size + DHD_SDALIGN);
++	if (memblock == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__,
++			memblock_size));
++		goto err;
++	}
++	if ((uint32)(uintptr)memblock % DHD_SDALIGN)
++		memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN));
++
++#ifdef DHD_DEBUG_DOWNLOADTIME
++	initial_jiffies = jiffies;
++#endif
++
++	/* Download image */
++	while ((len = dhd_os_get_image_block((char*)memptr, memblock_size, image))) {
++		if (len < 0) {
++			DHD_ERROR(("%s: dhd_os_get_image_block failed (%d)\n", __FUNCTION__, len));
++			bcmerror = BCME_ERROR;
++			goto err;
++		}
++		/* check if CR4 */
++		if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
++			/* if address is 0, store the reset instruction to be written in 0 */
++
++			if (offset == 0) {
++				bus->resetinstr = *(((uint32*)memptr));
++				/* Add start of RAM address to the address given by user */
++				offset += bus->dongle_ram_base;
++			}
++		}
++
++		bcmerror = dhdsdio_membytes(bus, TRUE, offset, memptr, len);
++		if (bcmerror) {
++			DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
++			        __FUNCTION__, bcmerror, memblock_size, offset));
++			goto err;
++		}
++
++		offset += memblock_size;
++#ifdef DHD_DEBUG_DOWNLOADTIME
++		firmware_sz += len;
++#endif
++	}
++
++#ifdef DHD_DEBUG_DOWNLOADTIME
++	DHD_ERROR(("Firmware download time for %u bytes: %u ms\n",
++			firmware_sz, jiffies_to_msecs(jiffies - initial_jiffies)));
++#endif
++
++err:
++	if (memblock)
++		MFREE(bus->dhd->osh, memblock, memblock_size + DHD_SDALIGN);
++
++	if (image)
++		dhd_os_close_image(image);
++
++	return bcmerror;
++}
++
++
++static int
++dhdsdio_download_nvram(struct dhd_bus *bus)
++{
++	int bcmerror = -1;
++	uint len;
++	void * image = NULL;
++	char * memblock = NULL;
++	char *bufp;
++	char *pnv_path;
++	bool nvram_file_exists;
++
++	pnv_path = bus->nv_path;
++
++	nvram_file_exists = ((pnv_path != NULL) && (pnv_path[0] != '\0'));
++
++	/* For Get nvram from UEFI */
++	if (nvram_file_exists)
++		image = dhd_os_open_image(pnv_path);
++
++	memblock = MALLOC(bus->dhd->osh, MAX_NVRAMBUF_SIZE);
++	if (memblock == NULL) {
++		DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
++		           __FUNCTION__, MAX_NVRAMBUF_SIZE));
++		goto err;
++	}
++
++	/* For Get nvram from image or UEFI (when image == NULL ) */
++	len = dhd_os_get_image_block(memblock, MAX_NVRAMBUF_SIZE, image);
++
++	if (len > 0 && len < MAX_NVRAMBUF_SIZE) {
++		bufp = (char *)memblock;
++		bufp[len] = 0;
++		len = process_nvram_vars(bufp, len);
++		if (len % 4) {
++			len += 4 - (len % 4);
++		}
++		bufp += len;
++		*bufp++ = 0;
++		if (len)
++			bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
++		if (bcmerror) {
++			DHD_ERROR(("%s: error downloading vars: %d\n",
++			           __FUNCTION__, bcmerror));
++		}
++	}
++	else {
++		DHD_ERROR(("%s: error reading nvram file: %d\n",
++		           __FUNCTION__, len));
++		bcmerror = BCME_SDIO_ERROR;
++	}
++
++err:
++	if (memblock)
++		MFREE(bus->dhd->osh, memblock, MAX_NVRAMBUF_SIZE);
++
++	if (image)
++		dhd_os_close_image(image);
++
++	return bcmerror;
++}
++
++static int
++_dhdsdio_download_firmware(struct dhd_bus *bus)
++{
++	int bcmerror = -1;
++
++	bool embed = FALSE;	/* download embedded firmware */
++	bool dlok = FALSE;	/* download firmware succeeded */
++
++	/* Out immediately if no image to download */
++	if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
++#ifdef BCMEMBEDIMAGE
++		embed = TRUE;
++#else
++		return 0;
++#endif
++	}
++
++	/* Keep arm in reset */
++	if (dhdsdio_download_state(bus, TRUE)) {
++		DHD_ERROR(("%s: error placing ARM core in reset\n", __FUNCTION__));
++		goto err;
++	}
++
++	/* External image takes precedence if specified */
++	if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
++		if (dhdsdio_download_code_file(bus, bus->fw_path)) {
++			DHD_ERROR(("%s: dongle image file download failed\n", __FUNCTION__));
++#ifdef BCMEMBEDIMAGE
++			embed = TRUE;
++#else
++			goto err;
++#endif
++		}
++		else {
++			embed = FALSE;
++			dlok = TRUE;
++		}
++	}
++
++#ifdef BCMEMBEDIMAGE
++	if (embed) {
++		if (dhdsdio_download_code_array(bus)) {
++			DHD_ERROR(("%s: dongle image array download failed\n", __FUNCTION__));
++			goto err;
++		}
++		else {
++			dlok = TRUE;
++		}
++	}
++#else
++	BCM_REFERENCE(embed);
++#endif
++	if (!dlok) {
++		DHD_ERROR(("%s: dongle image download failed\n", __FUNCTION__));
++		goto err;
++	}
++
++	/* External nvram takes precedence if specified */
++	if (dhdsdio_download_nvram(bus)) {
++		DHD_ERROR(("%s: dongle nvram file download failed\n", __FUNCTION__));
++		goto err;
++	}
++
++	/* Take arm out of reset */
++	if (dhdsdio_download_state(bus, FALSE)) {
++		DHD_ERROR(("%s: error getting out of ARM core reset\n", __FUNCTION__));
++		goto err;
++	}
++
++	bcmerror = 0;
++
++err:
++	return bcmerror;
++}
++
++static int
++dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags, uint8 *buf, uint nbytes,
++	void *pkt, bcmsdh_cmplt_fn_t complete, void *handle)
++{
++	int status;
++
++	if (!KSO_ENAB(bus)) {
++		DHD_ERROR(("%s: Device asleep\n", __FUNCTION__));
++		return BCME_NODEVICE;
++	}
++
++	status = bcmsdh_recv_buf(bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete, handle);
++
++	return status;
++}
++
++static int
++dhd_bcmsdh_send_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags, uint8 *buf, uint nbytes,
++	void *pkt, bcmsdh_cmplt_fn_t complete, void *handle, int max_retry)
++{
++	int ret;
++	int i = 0;
++	int retries = 0;
++	bcmsdh_info_t *sdh;
++
++	if (!KSO_ENAB(bus)) {
++		DHD_ERROR(("%s: Device asleep\n", __FUNCTION__));
++		return BCME_NODEVICE;
++	}
++
++	sdh = bus->sdh;
++	do {
++		ret = bcmsdh_send_buf(bus->sdh, addr, fn, flags, buf, nbytes,
++			pkt, complete, handle);
++
++		bus->f2txdata++;
++		ASSERT(ret != BCME_PENDING);
++
++		if (ret == BCME_NODEVICE) {
++			DHD_ERROR(("%s: Device asleep already\n", __FUNCTION__));
++		} else if (ret < 0) {
++			/* On failure, abort the command and terminate the frame */
++			DHD_ERROR(("%s: sdio error %d, abort command and terminate frame.\n",
++				__FUNCTION__, ret));
++			bus->tx_sderrs++;
++			bus->f1regdata++;
++			bus->dhd->tx_errors++;
++			bcmsdh_abort(sdh, SDIO_FUNC_2);
++			bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL,
++				SFC_WF_TERM, NULL);
++			for (i = 0; i < READ_FRM_CNT_RETRIES; i++) {
++				uint8 hi, lo;
++				hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WFRAMEBCHI,
++					NULL);
++				lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WFRAMEBCLO,
++					NULL);
++				bus->f1regdata += 2;
++				if ((hi == 0) && (lo == 0))
++					break;
++			}
++		}
++	} while ((ret < 0) && retrydata && ++retries < max_retry);
++
++	return ret;
++}
++
++uint8
++dhd_bus_is_ioready(struct dhd_bus *bus)
++{
++	uint8 enable;
++	bcmsdh_info_t *sdh;
++	ASSERT(bus);
++	ASSERT(bus->sih != NULL);
++	enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
++	sdh = bus->sdh;
++	return (enable == bcmsdh_cfg_read(sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY, NULL));
++}
++
++uint
++dhd_bus_chip(struct dhd_bus *bus)
++{
++	ASSERT(bus->sih != NULL);
++	return bus->sih->chip;
++}
++
++uint
++dhd_bus_chiprev(struct dhd_bus *bus)
++{
++	ASSERT(bus);
++	ASSERT(bus->sih != NULL);
++	return bus->sih->chiprev;
++}
++
++void *
++dhd_bus_pub(struct dhd_bus *bus)
++{
++	return bus->dhd;
++}
++
++void *
++dhd_bus_sih(struct dhd_bus *bus)
++{
++	return (void *)bus->sih;
++}
++
++void *
++dhd_bus_txq(struct dhd_bus *bus)
++{
++	return &bus->txq;
++}
++
++uint
++dhd_bus_hdrlen(struct dhd_bus *bus)
++{
++	return (bus->txglom_enable) ? SDPCM_HDRLEN_TXGLOM : SDPCM_HDRLEN;
++}
++
++void
++dhd_bus_set_dotxinrx(struct dhd_bus *bus, bool val)
++{
++	bus->dotxinrx = val;
++}
++
++/*
++ *  dhdsdio_advertise_bus_cleanup advertises that clean up is under progress
++ * to other bus user contexts like Tx, Rx, IOVAR, WD etc and it waits for other contexts
++ * to gracefully exit. All the bus usage contexts before marking busstate as busy, will check for
++ * whether the busstate is DHD_BUS_DOWN or DHD_BUS_DOWN_IN_PROGRESS, if so
++ * they will exit from there itself without marking dhd_bus_busy_state as BUSY.
++ */
++static void
++dhdsdio_advertise_bus_cleanup(dhd_pub_t	 *dhdp)
++{
++	unsigned long flags;
++	int timeleft;
++
++	DHD_GENERAL_LOCK(dhdp, flags);
++	dhdp->busstate = DHD_BUS_DOWN_IN_PROGRESS;
++	DHD_GENERAL_UNLOCK(dhdp, flags);
++
++	timeleft = dhd_os_busbusy_wait_negation(dhdp, &dhdp->dhd_bus_busy_state);
++	if (timeleft == 0) {
++		DHD_ERROR(("%s : Timeout due to dhd_bus_busy_state=0x%x\n",
++				__FUNCTION__, dhdp->dhd_bus_busy_state));
++		BUG_ON(1);
++	}
++
++	return;
++}
++
++int
++dhd_bus_devreset(dhd_pub_t *dhdp, uint8 flag)
++{
++	int bcmerror = 0;
++	dhd_bus_t *bus;
++	unsigned long flags;
++
++	bus = dhdp->bus;
++
++	if (flag == TRUE) {
++		if (!bus->dhd->dongle_reset) {
++			DHD_ERROR(("%s: == Power OFF ==\n", __FUNCTION__));
++			dhdsdio_advertise_bus_cleanup(bus->dhd);
++			dhd_os_sdlock(dhdp);
++			dhd_os_wd_timer(dhdp, 0);
++#if !defined(IGNORE_ETH0_DOWN)
++			/* Force flow control as protection when stop come before ifconfig_down */
++			dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, ON);
++#endif /* !defined(IGNORE_ETH0_DOWN) */
++			/* Expect app to have torn down any connection before calling */
++			/* Stop the bus, disable F2 */
++			dhd_bus_stop(bus, FALSE);
++
++#if defined(OOB_INTR_ONLY)
++			/* Clean up any pending IRQ */
++			dhd_enable_oob_intr(bus, FALSE);
++			bcmsdh_oob_intr_set(bus->sdh, FALSE);
++			bcmsdh_oob_intr_unregister(bus->sdh);
++#endif 
++
++			/* Clean tx/rx buffer pointers, detach from the dongle */
++			dhdsdio_release_dongle(bus, bus->dhd->osh, TRUE, TRUE);
++
++			bus->dhd->dongle_reset = TRUE;
++			bus->dhd->up = FALSE;
++			dhd_txglom_enable(dhdp, FALSE);
++			dhd_os_sdunlock(dhdp);
++
++			DHD_GENERAL_LOCK(bus->dhd, flags);
++			bus->dhd->busstate = DHD_BUS_DOWN;
++			DHD_GENERAL_UNLOCK(bus->dhd, flags);
++
++			DHD_ERROR(("%s:  WLAN OFF DONE\n", __FUNCTION__));
++			/* App can now remove power from device */
++		} else
++			bcmerror = BCME_SDIO_ERROR;
++	} else {
++		/* App must have restored power to device before calling */
++
++		DHD_ERROR(("\n\n%s: == WLAN ON ==\n", __FUNCTION__));
++
++		if (bus->dhd->dongle_reset) {
++			/* Turn on WLAN */
++			dhd_os_sdlock(dhdp);
++			/* Reset SD client */
++			bcmsdh_reset(bus->sdh);
++
++			/* Attempt to re-attach & download */
++			if (dhdsdio_probe_attach(bus, bus->dhd->osh, bus->sdh,
++				(uint32 *)SI_ENUM_BASE,
++				bus->cl_devid)) {
++
++				DHD_GENERAL_LOCK(bus->dhd, flags);
++				bus->dhd->busstate = DHD_BUS_DOWN;
++				DHD_GENERAL_UNLOCK(bus->dhd, flags);
++				/* Attempt to download binary to the dongle */
++				if (dhdsdio_probe_init(bus, bus->dhd->osh, bus->sdh) &&
++				    dhdsdio_download_firmware(bus, bus->dhd->osh, bus->sdh) >= 0) {
++
++					/* Re-init bus, enable F2 transfer */
++					bcmerror = dhd_bus_init((dhd_pub_t *) bus->dhd, FALSE);
++					if (bcmerror == BCME_OK) {
++#if defined(OOB_INTR_ONLY)
++						dhd_enable_oob_intr(bus, TRUE);
++						bcmsdh_oob_intr_register(bus->sdh,
++							dhdsdio_isr, bus);
++						bcmsdh_oob_intr_set(bus->sdh, TRUE);
++#endif 
++
++						bus->dhd->dongle_reset = FALSE;
++						bus->dhd->up = TRUE;
++
++#if !defined(IGNORE_ETH0_DOWN)
++						/* Restore flow control  */
++						dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, OFF);
++#endif 
++						dhd_os_wd_timer(dhdp, dhd_watchdog_ms);
++
++						DHD_TRACE(("%s: WLAN ON DONE\n", __FUNCTION__));
++					} else {
++						dhd_bus_stop(bus, FALSE);
++						dhdsdio_release_dongle(bus, bus->dhd->osh,
++							TRUE, FALSE);
++					}
++				} else {
++					DHD_ERROR(("%s Failed to download binary to the dongle\n",
++						__FUNCTION__));
++					if (bus->sih != NULL) {
++						si_detach(bus->sih);
++						bus->sih = NULL;
++					}
++					bcmerror = BCME_SDIO_ERROR;
++				}
++			} else {
++				bcmerror = BCME_SDIO_ERROR;
++			}
++
++				dhd_os_sdunlock(dhdp);
++		} else {
++			bcmerror = BCME_SDIO_ERROR;
++			DHD_INFO(("%s called when dongle is not in reset\n",
++				__FUNCTION__));
++			DHD_INFO(("Will call dhd_bus_start instead\n"));
++			dhd_bus_resume(dhdp, 1);
++			if ((bcmerror = dhd_bus_start(dhdp)) != 0)
++				DHD_ERROR(("%s: dhd_bus_start fail with %d\n",
++					__FUNCTION__, bcmerror));
++		}
++	}
++	return bcmerror;
++}
++
++int dhd_bus_suspend(dhd_pub_t *dhdpub)
++{
++	return bcmsdh_stop(dhdpub->bus->sdh);
++}
++
++int dhd_bus_resume(dhd_pub_t *dhdpub, int stage)
++{
++	return bcmsdh_start(dhdpub->bus->sdh, stage);
++}
++
++/* Get Chip ID version */
++uint dhd_bus_chip_id(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++
++	return  bus->sih->chip;
++}
++
++/* Get Chip Rev ID version */
++uint dhd_bus_chiprev_id(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++
++	return bus->sih->chiprev;
++}
++
++/* Get Chip Pkg ID version */
++uint dhd_bus_chippkg_id(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++
++	return bus->sih->chippkg;
++}
++
++int dhd_bus_get_ids(struct dhd_bus *bus, uint32 *bus_type, uint32 *bus_num, uint32 *slot_num)
++{
++	*bus_type = bus->bus;
++	*bus_num = bus->bus_num;
++	*slot_num = bus->slot_num;
++	return 0;
++}
++
++int
++dhd_bus_membytes(dhd_pub_t *dhdp, bool set, uint32 address, uint8 *data, uint size)
++{
++	dhd_bus_t *bus;
++
++	bus = dhdp->bus;
++	return dhdsdio_membytes(bus, set, address, data, size);
++}
++
++
++void
++dhd_bus_update_fw_nv_path(struct dhd_bus *bus, char *pfw_path, char *pnv_path)
++{
++	bus->fw_path = pfw_path;
++	bus->nv_path = pnv_path;
++}
++
++int
++dhd_enableOOB(dhd_pub_t *dhd, bool sleep)
++{
++	dhd_bus_t *bus = dhd->bus;
++	sdpcmd_regs_t *regs = bus->regs;
++	uint retries = 0;
++
++	if (sleep) {
++		dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++		/* Tell device to start using OOB wakeup */
++		W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
++		if (retries > retry_limit) {
++			DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
++			return BCME_BUSY;
++		}
++		/* Turn off our contribution to the HT clock request */
++		dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++	} else {
++		/* Make sure the controller has the bus up */
++		dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++		/* Send misc interrupt to indicate OOB not needed */
++		W_SDREG(0, &regs->tosbmailboxdata, retries);
++		if (retries <= retry_limit)
++			W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
++
++		if (retries > retry_limit)
++			DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
++
++		/* Make sure we have SD bus access */
++		dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
++	}
++	return BCME_OK;
++}
++
++void
++dhd_bus_pktq_flush(dhd_pub_t *dhdp)
++{
++	dhd_bus_t *bus = dhdp->bus;
++	bool wlfc_enabled = FALSE;
++
++#ifdef PROP_TXSTATUS
++	wlfc_enabled = (dhd_wlfc_cleanup_txq(dhdp, NULL, 0) != WLFC_UNSUPPORTED);
++#endif
++	if (!wlfc_enabled) {
++#ifdef DHDTCPACK_SUPPRESS
++		/* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt,
++		 * when there is a newly coming packet from network stack.
++		 */
++		dhd_tcpack_info_tbl_clean(bus->dhd);
++#endif /* DHDTCPACK_SUPPRESS */
++		/* Clear the data packet queues */
++		pktq_flush(dhdp->osh, &bus->txq, TRUE, NULL, 0);
++	}
++}
++
++#ifdef BCMSDIO
++int
++dhd_sr_config(dhd_pub_t *dhd, bool on)
++{
++	dhd_bus_t *bus = dhd->bus;
++
++	if (!bus->_srenab)
++		return -1;
++
++	return dhdsdio_clk_devsleep_iovar(bus, on);
++}
++
++uint16
++dhd_get_chipid(dhd_pub_t *dhd)
++{
++	dhd_bus_t *bus = dhd->bus;
++
++	if (bus && bus->sih)
++		return (uint16)bus->sih->chip;
++	else
++		return 0;
++}
++#endif /* BCMSDIO */
++
++#ifdef DEBUGGER
++uint32 dhd_sdio_reg_read(void *h, uint32 addr)
++{
++	uint32 rval;
++	struct dhd_bus *bus = (struct dhd_bus *) h;
++
++	dhd_os_sdlock(bus->dhd);
++
++	BUS_WAKE(bus);
++
++	dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++	rval = bcmsdh_reg_read(bus->sdh, addr, 4);
++
++	dhd_os_sdunlock(bus->dhd);
++
++	return rval;
++}
++
++void dhd_sdio_reg_write(void *h, uint32 addr, uint32 val)
++{
++	struct dhd_bus *bus = (struct dhd_bus *) h;
++
++	dhd_os_sdlock(bus->dhd);
++
++	BUS_WAKE(bus);
++
++	dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
++
++	bcmsdh_reg_write(bus->sdh, addr, 4, val);
++
++	dhd_os_sdunlock(bus->dhd);
++}
++#endif /* DEBUGGER */
++
++
++int
++dhd_bcmsdh_send_buffer(void *bus, uint8 *frame, uint16 len)
++{
++	int ret = -1;
++
++	ret = dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(((dhd_bus_t*)bus)->sdh),
++		SDIO_FUNC_2, F2SYNC, frame, len, NULL, NULL, NULL, TXRETRIES);
++
++	if (ret == BCME_OK)
++		((dhd_bus_t*)bus)->tx_seq = (((dhd_bus_t*)bus)->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
++
++	return ret;
++}
++
++#ifdef DHD_ULP
++/* Function to disable console messages on entering ULP mode */
++void
++dhd_bus_ulp_disable_console(dhd_pub_t *dhdp)
++{
++#ifdef DHD_DEBUG
++	DHD_ERROR(("Flushing and disabling console messages\n"));
++
++	/* Save the console print interval */
++	dhd_ulp_save_console_interval(dhdp);
++
++	/* Flush the console buffer before disabling */
++	dhdsdio_readconsole(dhdp->bus);
++	dhd_console_ms = 0;
++#endif /* DHD_DEBUG */
++}
++
++/* Function for redownloading firmaware */
++static int
++dhd_bus_ulp_reinit_fw(dhd_bus_t *bus)
++{
++	int bcmerror = 0;
++
++	/* After firmware redownload tx/rx seq are reset accordingly these values are
++	reset on DHD side tx_max is initially set to 4, which later is updated by FW
++	*/
++	bus->tx_seq = bus->rx_seq = 0;
++	bus->tx_max = 4;
++
++	if (dhd_bus_download_firmware(bus, bus->dhd->osh,
++		bus->fw_path, bus->nv_path) >= 0) {
++
++		/* Re-init bus, enable F2 transfer */
++		bcmerror = dhd_bus_init((dhd_pub_t *) bus->dhd, FALSE);
++		if (bcmerror == BCME_OK) {
++			bus->dhd->up = TRUE;
++			dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
++
++			dhd_ulp_set_ulp_state(bus->dhd, DHD_ULP_READY);
++#if defined(OOB_INTR_ONLY)
++			dhd_enable_oob_intr(bus, TRUE);
++			bcmsdh_oob_intr_set(bus->sdh, TRUE);
++#endif 
++#ifdef DHD_DEBUG
++		/* Re-enable the console messages on FW redownload to default value */
++		dhd_ulp_restore_console_interval(bus->dhd);
++#endif /* DHD_DEBUG */
++		} else {
++			DHD_ERROR(("bus init failed\n"));
++			dhd_bus_stop(bus, FALSE);
++			dhdsdio_release_dongle(bus, bus->dhd->osh,
++				TRUE, FALSE);
++		}
++	} else
++		bcmerror = BCME_SDIO_ERROR;
++
++	return bcmerror;
++}
++
++/* Utility function for bus wake */
++void
++dhd_bus_ulp_bus_wake(void *bus)
++{
++	dhd_bus_t *ptrbus = (dhd_bus_t *)bus;
++	BUS_WAKE(ptrbus);
++}
++
++/* Utility function to read the SDIO configuration space */
++int
++dhd_bus_read_sdh_config(void *bus)
++{
++	int ret = 0;
++	dhd_bus_t *ptrbus = (dhd_bus_t *)bus;
++	ret = bcmsdh_cfg_read(ptrbus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY, NULL);
++
++	return ret;
++}
++
++void
++dhd_bus_schedule_dpc(void *bus)
++{	dhd_bus_t *ptrbus = (dhd_bus_t *)bus;
++
++	ptrbus->dpc_sched = TRUE;
++	dhd_sched_dpc(ptrbus->dhd);
++}
++
++/* Function to set the min res mask depending on the chip ID used */
++bool
++dhd_bus_set_default_min_res_mask(struct dhd_bus *bus)
++{
++	switch (bus->sih->chip) {
++	case BCM4339_CHIP_ID:
++		bcmsdh_reg_write(bus->sdh, SI_ENUM_BASE + 0x618, 4, 0x3fcaf377);
++		if (bcmsdh_regfail(bus->sdh)) {
++			DHD_ERROR(("%s:%d Setting min_res_mask failed\n", __FUNCTION__, __LINE__));
++			return FALSE;
++		}
++		break;
++
++	case BCM43012_CHIP_ID:
++		bcmsdh_reg_write(bus->sdh,
++			si_get_pmu_reg_addr(bus->sih, OFFSETOF(pmuregs_t, min_res_mask)),
++			4, DEFAULT_43012_MIN_RES_MASK);
++		if (bcmsdh_regfail(bus->sdh)) {
++			DHD_ERROR(("%s:%d Setting min_res_mask failed\n", __FUNCTION__, __LINE__));
++			return FALSE;
++		}
++		break;
++
++	default:
++		DHD_ERROR(("%s: Unhandled chip id\n", __FUNCTION__));
++		return FALSE;
++	}
++
++	return TRUE;
++}
++
++void
++dhd_bus_pmu_reg_reset(dhd_pub_t *dhdp)
++{
++	struct dhd_bus *bus = dhdp->bus;
++	bcmsdh_reg_write(bus->sdh, si_get_pmu_reg_addr(bus->sih,
++		OFFSETOF(pmuregs_t, swscratch)), 4, 0x0);
++	if (bcmsdh_regfail(bus->sdh)) {
++		DHD_ERROR(("%s:%d Setting min_res_mask failed\n", __FUNCTION__, __LINE__));
++	}
++}
++#endif /* DHD_ULP */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_wlfc.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_wlfc.c
+new file mode 100644
+index 000000000..9366a1fb6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_wlfc.c
+@@ -0,0 +1,4566 @@
++/*
++ * DHD PROP_TXSTATUS Module.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_wlfc.c 606400 2015-12-15 09:59:42Z $
++ *
++ */
++
++
++#include <typedefs.h>
++#include <osl.h>
++
++#include <bcmutils.h>
++#include <bcmendian.h>
++
++#include <dngl_stats.h>
++#include <dhd.h>
++
++#ifdef BCMDBUS /* an abstraction layer that hides details of the underlying bus, eg \
++	Linux USB */
++#include <dbus.h>
++#else
++#include <dhd_bus.h>
++#endif /* BCMDBUS */
++
++#include <dhd_dbg.h>
++
++#ifdef PROP_TXSTATUS /* a form of flow control between host and dongle */
++#include <wlfc_proto.h>
++#include <dhd_wlfc.h>
++#endif
++
++#ifdef DHDTCPACK_SUPPRESS
++#include <dhd_ip.h>
++#endif /* DHDTCPACK_SUPPRESS */
++
++
++/*
++ * wlfc naming and lock rules:
++ *
++ * 1. Private functions name like _dhd_wlfc_XXX, declared as static and avoid wlfc lock operation.
++ * 2. Public functions name like dhd_wlfc_XXX, use wlfc lock if needed.
++ * 3. Non-Proptxstatus module call public functions only and avoid wlfc lock operation.
++ *
++ */
++
++#if defined(DHD_WLFC_THREAD)
++#define WLFC_THREAD_QUICK_RETRY_WAIT_MS    10      /* 10 msec */
++#define WLFC_THREAD_RETRY_WAIT_MS          10000   /* 10 sec */
++#endif /* defined (DHD_WLFC_THREAD) */
++
++#if defined(BCMDBUS)
++extern int dhd_dbus_txdata(dhd_pub_t *dhdp, void *pktbuf);
++#endif
++
++#ifdef PROP_TXSTATUS
++
++#define DHD_WLFC_QMON_COMPLETE(entry)
++
++
++/** reordering related */
++
++#if defined(DHD_WLFC_THREAD)
++static void
++_dhd_wlfc_thread_wakeup(dhd_pub_t *dhdp)
++{
++	dhdp->wlfc_thread_go = TRUE;
++	wake_up_interruptible(&dhdp->wlfc_wqhead);
++}
++#endif /* DHD_WLFC_THREAD */
++
++static uint16
++_dhd_wlfc_adjusted_seq(void* p, uint8 current_seq)
++{
++	uint16 seq;
++
++	if (!p) {
++		return 0xffff;
++	}
++
++	seq = WL_TXSTATUS_GET_FREERUNCTR(DHD_PKTTAG_H2DTAG(PKTTAG(p)));
++	if (seq < current_seq) {
++		/* wrap around */
++		seq += 256;
++	}
++
++	return seq;
++}
++
++/**
++ * Enqueue a caller supplied packet on a caller supplied precedence queue, optionally reorder
++ * suppressed packets.
++ *    @param[in] pq       caller supplied packet queue to enqueue the packet on
++ *    @param[in] prec     precedence of the to-be-queued packet
++ *    @param[in] p        transmit packet to enqueue
++ *    @param[in] qHead    if TRUE, enqueue to head instead of tail. Used to maintain d11 seq order.
++ *    @param[in] current_seq
++ *    @param[in] reOrder  reOrder on odd precedence (=suppress queue)
++ */
++static void
++_dhd_wlfc_prec_enque(struct pktq *pq, int prec, void* p, bool qHead,
++	uint8 current_seq, bool reOrder)
++{
++	struct pktq_prec *q;
++	uint16 seq, seq2;
++	void *p2, *p2_prev;
++
++	if (!p)
++		return;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++	/* queueing chains not allowed and no segmented SKB (Kernel-3.18.y) */
++	ASSERT(!((PKTLINK(p) != NULL) && (PKTLINK(p) != p)));
++
++	ASSERT(!pktq_full(pq));
++	ASSERT(!pktq_pfull(pq, prec));
++
++	q = &pq->q[prec];
++
++	PKTSETLINK(p, NULL);
++	if (q->head == NULL) {
++		/* empty queue */
++		q->head = p;
++		q->tail = p;
++	} else {
++		if (reOrder && (prec & 1)) {
++			seq = _dhd_wlfc_adjusted_seq(p, current_seq);
++			p2 = qHead ? q->head : q->tail;
++			seq2 = _dhd_wlfc_adjusted_seq(p2, current_seq);
++
++			if ((qHead &&((seq+1) > seq2)) || (!qHead && ((seq2+1) > seq))) {
++				/* need reorder */
++				p2 = q->head;
++				p2_prev = NULL;
++				seq2 = _dhd_wlfc_adjusted_seq(p2, current_seq);
++
++				while (seq > seq2) {
++					p2_prev = p2;
++					p2 = PKTLINK(p2);
++					if (!p2) {
++						break;
++					}
++					seq2 = _dhd_wlfc_adjusted_seq(p2, current_seq);
++				}
++
++				if (p2_prev == NULL) {
++					/* insert head */
++					PKTSETLINK(p, q->head);
++					q->head = p;
++				} else if (p2 == NULL) {
++					/* insert tail */
++					PKTSETLINK(p2_prev, p);
++					q->tail = p;
++				} else {
++					/* insert after p2_prev */
++					PKTSETLINK(p, PKTLINK(p2_prev));
++					PKTSETLINK(p2_prev, p);
++				}
++				goto exit;
++			}
++		}
++
++		if (qHead) {
++			PKTSETLINK(p, q->head);
++			q->head = p;
++		} else {
++			PKTSETLINK(q->tail, p);
++			q->tail = p;
++		}
++	}
++
++exit:
++
++	q->len++;
++	pq->len++;
++
++	if (pq->hi_prec < prec)
++		pq->hi_prec = (uint8)prec;
++} /* _dhd_wlfc_prec_enque */
++
++/**
++ * Create a place to store all packet pointers submitted to the firmware until a status comes back,
++ * suppress or otherwise.
++ *
++ * hang-er: noun, a contrivance on which things are hung, as a hook.
++ */
++/** @deprecated soon */
++static void*
++_dhd_wlfc_hanger_create(dhd_pub_t *dhd, int max_items)
++{
++	int i;
++	wlfc_hanger_t* hanger;
++
++	/* allow only up to a specific size for now */
++	ASSERT(max_items == WLFC_HANGER_MAXITEMS);
++
++	if ((hanger = (wlfc_hanger_t*)DHD_OS_PREALLOC(dhd, DHD_PREALLOC_DHD_WLFC_HANGER,
++		WLFC_HANGER_SIZE(max_items))) == NULL) {
++		return NULL;
++	}
++	memset(hanger, 0, WLFC_HANGER_SIZE(max_items));
++	hanger->max_items = max_items;
++
++	for (i = 0; i < hanger->max_items; i++) {
++		hanger->items[i].state = WLFC_HANGER_ITEM_STATE_FREE;
++	}
++	return hanger;
++}
++
++/** @deprecated soon */
++static int
++_dhd_wlfc_hanger_delete(dhd_pub_t *dhd, void* hanger)
++{
++	wlfc_hanger_t* h = (wlfc_hanger_t*)hanger;
++
++	if (h) {
++		DHD_OS_PREFREE(dhd, h, WLFC_HANGER_SIZE(h->max_items));
++		return BCME_OK;
++	}
++	return BCME_BADARG;
++}
++
++/** @deprecated soon */
++static uint16
++_dhd_wlfc_hanger_get_free_slot(void* hanger)
++{
++	uint32 i;
++	wlfc_hanger_t* h = (wlfc_hanger_t*)hanger;
++
++	if (h) {
++		i = h->slot_pos + 1;
++		if (i == h->max_items) {
++			i = 0;
++		}
++		while (i != h->slot_pos) {
++			if (h->items[i].state == WLFC_HANGER_ITEM_STATE_FREE) {
++				h->slot_pos = i;
++				return (uint16)i;
++			}
++			i++;
++			if (i == h->max_items)
++				i = 0;
++		}
++		h->failed_slotfind++;
++	}
++	return WLFC_HANGER_MAXITEMS;
++}
++
++/** @deprecated soon */
++static int
++_dhd_wlfc_hanger_get_genbit(void* hanger, void* pkt, uint32 slot_id, int* gen)
++{
++	int rc = BCME_OK;
++	wlfc_hanger_t* h = (wlfc_hanger_t*)hanger;
++
++	*gen = 0xff;
++
++	/* this packet was not pushed at the time it went to the firmware */
++	if (slot_id == WLFC_HANGER_MAXITEMS)
++		return BCME_NOTFOUND;
++
++	if (h) {
++		if (h->items[slot_id].state != WLFC_HANGER_ITEM_STATE_FREE) {
++			*gen = h->items[slot_id].gen;
++		}
++		else {
++			DHD_ERROR(("Error: %s():%d item not used\n",
++				__FUNCTION__, __LINE__));
++			rc = BCME_NOTFOUND;
++		}
++
++	} else {
++		rc = BCME_BADARG;
++	}
++
++	return rc;
++}
++
++/** @deprecated soon */
++static int
++_dhd_wlfc_hanger_pushpkt(void* hanger, void* pkt, uint32 slot_id)
++{
++	int rc = BCME_OK;
++	wlfc_hanger_t* h = (wlfc_hanger_t*)hanger;
++
++	if (h && (slot_id < WLFC_HANGER_MAXITEMS)) {
++		if (h->items[slot_id].state == WLFC_HANGER_ITEM_STATE_FREE) {
++			h->items[slot_id].state = WLFC_HANGER_ITEM_STATE_INUSE;
++			h->items[slot_id].pkt = pkt;
++			h->items[slot_id].pkt_state = 0;
++			h->items[slot_id].pkt_txstatus = 0;
++			h->pushed++;
++		} else {
++			h->failed_to_push++;
++			rc = BCME_NOTFOUND;
++		}
++	} else {
++		rc = BCME_BADARG;
++	}
++
++	return rc;
++}
++
++/** @deprecated soon */
++static int
++_dhd_wlfc_hanger_poppkt(void* hanger, uint32 slot_id, void** pktout, bool remove_from_hanger)
++{
++	int rc = BCME_OK;
++	wlfc_hanger_t* h = (wlfc_hanger_t*)hanger;
++
++	*pktout = NULL;
++
++	/* this packet was not pushed at the time it went to the firmware */
++	if (slot_id == WLFC_HANGER_MAXITEMS)
++		return BCME_NOTFOUND;
++
++	if (h) {
++		if (h->items[slot_id].state != WLFC_HANGER_ITEM_STATE_FREE) {
++			*pktout = h->items[slot_id].pkt;
++			if (remove_from_hanger) {
++				h->items[slot_id].state =
++					WLFC_HANGER_ITEM_STATE_FREE;
++				h->items[slot_id].pkt = NULL;
++				h->items[slot_id].gen = 0xff;
++				h->items[slot_id].identifier = 0;
++				h->popped++;
++			}
++		} else {
++			h->failed_to_pop++;
++			rc = BCME_NOTFOUND;
++		}
++	} else {
++		rc = BCME_BADARG;
++	}
++
++	return rc;
++}
++
++/** @deprecated soon */
++static int
++_dhd_wlfc_hanger_mark_suppressed(void* hanger, uint32 slot_id, uint8 gen)
++{
++	int rc = BCME_OK;
++	wlfc_hanger_t* h = (wlfc_hanger_t*)hanger;
++
++	/* this packet was not pushed at the time it went to the firmware */
++	if (slot_id == WLFC_HANGER_MAXITEMS)
++		return BCME_NOTFOUND;
++	if (h) {
++		h->items[slot_id].gen = gen;
++		if (h->items[slot_id].state == WLFC_HANGER_ITEM_STATE_INUSE) {
++			h->items[slot_id].state = WLFC_HANGER_ITEM_STATE_INUSE_SUPPRESSED;
++		} else {
++			rc = BCME_BADARG;
++		}
++	} else {
++		rc = BCME_BADARG;
++	}
++
++	return rc;
++}
++
++/** remove reference of specific packet in hanger */
++/** @deprecated soon */
++static bool
++_dhd_wlfc_hanger_remove_reference(wlfc_hanger_t* h, void* pkt)
++{
++	int i;
++
++	if (!h || !pkt) {
++		return FALSE;
++	}
++
++	i = WL_TXSTATUS_GET_HSLOT(DHD_PKTTAG_H2DTAG(PKTTAG(pkt)));
++
++	if ((i < h->max_items) && (pkt == h->items[i].pkt)) {
++		if (h->items[i].state == WLFC_HANGER_ITEM_STATE_INUSE_SUPPRESSED) {
++			h->items[i].state = WLFC_HANGER_ITEM_STATE_FREE;
++			h->items[i].pkt = NULL;
++			h->items[i].gen = 0xff;
++			h->items[i].identifier = 0;
++			return TRUE;
++		} else {
++			DHD_ERROR(("Error: %s():%d item not suppressed\n",
++				__FUNCTION__, __LINE__));
++		}
++	}
++
++	return FALSE;
++}
++
++/** afq = At Firmware Queue, queue containing packets pending in the dongle */
++static int
++_dhd_wlfc_enque_afq(athost_wl_status_info_t* ctx, void *p)
++{
++	wlfc_mac_descriptor_t* entry;
++	uint16 entry_idx = WL_TXSTATUS_GET_HSLOT(DHD_PKTTAG_H2DTAG(PKTTAG(p)));
++	uint8 prec = DHD_PKTTAG_FIFO(PKTTAG(p));
++
++	if (entry_idx < WLFC_MAC_DESC_TABLE_SIZE)
++		entry  = &ctx->destination_entries.nodes[entry_idx];
++	else if (entry_idx < (WLFC_MAC_DESC_TABLE_SIZE + WLFC_MAX_IFNUM))
++		entry = &ctx->destination_entries.interfaces[entry_idx - WLFC_MAC_DESC_TABLE_SIZE];
++	else
++		entry = &ctx->destination_entries.other;
++
++	pktq_penq(&entry->afq, prec, p);
++
++	return BCME_OK;
++}
++
++/** afq = At Firmware Queue, queue containing packets pending in the dongle */
++static int
++_dhd_wlfc_deque_afq(athost_wl_status_info_t* ctx, uint16 hslot, uint8 hcnt, uint8 prec,
++	void **pktout)
++{
++	wlfc_mac_descriptor_t *entry;
++	struct pktq *pq;
++	struct pktq_prec *q;
++	void *p, *b;
++
++	if (!ctx) {
++		DHD_ERROR(("%s: ctx(%p), pktout(%p)\n", __FUNCTION__, ctx, pktout));
++		return BCME_BADARG;
++	}
++
++	if (pktout) {
++		*pktout = NULL;
++	}
++
++	ASSERT(hslot < (WLFC_MAC_DESC_TABLE_SIZE + WLFC_MAX_IFNUM + 1));
++
++	if (hslot < WLFC_MAC_DESC_TABLE_SIZE)
++		entry  = &ctx->destination_entries.nodes[hslot];
++	else if (hslot < (WLFC_MAC_DESC_TABLE_SIZE + WLFC_MAX_IFNUM))
++		entry = &ctx->destination_entries.interfaces[hslot - WLFC_MAC_DESC_TABLE_SIZE];
++	else
++		entry = &ctx->destination_entries.other;
++
++	pq = &entry->afq;
++
++	ASSERT(prec < pq->num_prec);
++
++	q = &pq->q[prec];
++
++	b = NULL;
++	p = q->head;
++
++	while (p && (hcnt != WL_TXSTATUS_GET_FREERUNCTR(DHD_PKTTAG_H2DTAG(PKTTAG(p)))))
++	{
++		b = p;
++		p = PKTLINK(p);
++	}
++
++	if (p == NULL) {
++		/* none is matched */
++		if (b) {
++			DHD_ERROR(("%s: can't find matching seq(%d)\n", __FUNCTION__, hcnt));
++		} else {
++			DHD_ERROR(("%s: queue is empty\n", __FUNCTION__));
++		}
++
++		return BCME_ERROR;
++	}
++
++	bcm_pkt_validate_chk(p);
++
++	if (!b) {
++		/* head packet is matched */
++		if ((q->head = PKTLINK(p)) == NULL) {
++			q->tail = NULL;
++		}
++	} else {
++		/* middle packet is matched */
++		DHD_INFO(("%s: out of order, seq(%d), head_seq(%d)\n", __FUNCTION__, hcnt,
++			WL_TXSTATUS_GET_FREERUNCTR(DHD_PKTTAG_H2DTAG(PKTTAG(q->head)))));
++		ctx->stats.ooo_pkts[prec]++;
++		PKTSETLINK(b, PKTLINK(p));
++		if (PKTLINK(p) == NULL) {
++			q->tail = b;
++		}
++	}
++
++	q->len--;
++	pq->len--;
++
++	PKTSETLINK(p, NULL);
++
++	if (pktout) {
++		*pktout = p;
++	}
++
++	return BCME_OK;
++} /* _dhd_wlfc_deque_afq */
++
++/**
++ * Flow control information piggy backs on packets, in the form of one or more TLVs. This function
++ * pushes one or more TLVs onto a packet that is going to be sent towards the dongle.
++ *
++ *     @param[in]     ctx
++ *     @param[in/out] packet
++ *     @param[in]     tim_signal TRUE if parameter 'tim_bmp' is valid
++ *     @param[in]     tim_bmp
++ *     @param[in]     mac_handle
++ *     @param[in]     htodtag
++ *     @param[in]     htodseq d11 seqno for seqno reuse, only used if 'seq reuse' was agreed upon
++ *                    earlier between host and firmware.
++ *     @param[in]     skip_wlfc_hdr
++ */
++static int
++_dhd_wlfc_pushheader(athost_wl_status_info_t* ctx, void** packet, bool tim_signal,
++	uint8 tim_bmp, uint8 mac_handle, uint32 htodtag, uint16 htodseq, bool skip_wlfc_hdr)
++{
++	uint32 wl_pktinfo = 0;
++	uint8* wlh;
++	uint8 dataOffset = 0;
++	uint8 fillers;
++	uint8 tim_signal_len = 0;
++	dhd_pub_t *dhdp = (dhd_pub_t *)ctx->dhdp;
++
++	struct bdc_header *h;
++	void *p = *packet;
++
++	if (skip_wlfc_hdr)
++		goto push_bdc_hdr;
++
++	if (tim_signal) {
++		tim_signal_len = TLV_HDR_LEN + WLFC_CTL_VALUE_LEN_PENDING_TRAFFIC_BMP;
++	}
++
++	/* +2 is for Type[1] and Len[1] in TLV, plus TIM signal */
++	dataOffset = WLFC_CTL_VALUE_LEN_PKTTAG + TLV_HDR_LEN + tim_signal_len;
++	if (WLFC_GET_REUSESEQ(dhdp->wlfc_mode)) {
++		dataOffset += WLFC_CTL_VALUE_LEN_SEQ;
++	}
++
++	fillers = ROUNDUP(dataOffset, 4) - dataOffset;
++	dataOffset += fillers;
++
++	PKTPUSH(ctx->osh, p, dataOffset);
++	wlh = (uint8*) PKTDATA(ctx->osh, p);
++
++	wl_pktinfo = htol32(htodtag);
++
++	wlh[TLV_TAG_OFF] = WLFC_CTL_TYPE_PKTTAG;
++	wlh[TLV_LEN_OFF] = WLFC_CTL_VALUE_LEN_PKTTAG;
++	memcpy(&wlh[TLV_HDR_LEN] /* dst */, &wl_pktinfo, sizeof(uint32));
++
++	if (WLFC_GET_REUSESEQ(dhdp->wlfc_mode)) {
++		uint16 wl_seqinfo = htol16(htodseq);
++		wlh[TLV_LEN_OFF] += WLFC_CTL_VALUE_LEN_SEQ;
++		memcpy(&wlh[TLV_HDR_LEN + WLFC_CTL_VALUE_LEN_PKTTAG], &wl_seqinfo,
++			WLFC_CTL_VALUE_LEN_SEQ);
++	}
++
++	if (tim_signal_len) {
++		wlh[dataOffset - fillers - tim_signal_len ] =
++			WLFC_CTL_TYPE_PENDING_TRAFFIC_BMP;
++		wlh[dataOffset - fillers - tim_signal_len + 1] =
++			WLFC_CTL_VALUE_LEN_PENDING_TRAFFIC_BMP;
++		wlh[dataOffset - fillers - tim_signal_len + 2] = mac_handle;
++		wlh[dataOffset - fillers - tim_signal_len + 3] = tim_bmp;
++	}
++	if (fillers)
++		memset(&wlh[dataOffset - fillers], WLFC_CTL_TYPE_FILLER, fillers);
++
++push_bdc_hdr:
++	PKTPUSH(ctx->osh, p, BDC_HEADER_LEN);
++	h = (struct bdc_header *)PKTDATA(ctx->osh, p);
++	h->flags = (BDC_PROTO_VER << BDC_FLAG_VER_SHIFT);
++	if (PKTSUMNEEDED(p))
++		h->flags |= BDC_FLAG_SUM_NEEDED;
++
++
++	h->priority = (PKTPRIO(p) & BDC_PRIORITY_MASK);
++	h->flags2 = 0;
++	h->dataOffset = dataOffset >> 2;
++	BDC_SET_IF_IDX(h, DHD_PKTTAG_IF(PKTTAG(p)));
++	*packet = p;
++	return BCME_OK;
++} /* _dhd_wlfc_pushheader */
++
++/**
++ * Removes (PULLs) flow control related headers from the caller supplied packet, is invoked eg
++ * when a packet is about to be freed.
++ */
++static int
++_dhd_wlfc_pullheader(athost_wl_status_info_t* ctx, void* pktbuf)
++{
++	struct bdc_header *h;
++
++	if (PKTLEN(ctx->osh, pktbuf) < BDC_HEADER_LEN) {
++		DHD_ERROR(("%s: rx data too short (%d < %d)\n", __FUNCTION__,
++		           PKTLEN(ctx->osh, pktbuf), BDC_HEADER_LEN));
++		return BCME_ERROR;
++	}
++	h = (struct bdc_header *)PKTDATA(ctx->osh, pktbuf);
++
++	/* pull BDC header */
++	PKTPULL(ctx->osh, pktbuf, BDC_HEADER_LEN);
++
++	if (PKTLEN(ctx->osh, pktbuf) < (uint)(h->dataOffset << 2)) {
++		DHD_ERROR(("%s: rx data too short (%d < %d)\n", __FUNCTION__,
++		           PKTLEN(ctx->osh, pktbuf), (h->dataOffset << 2)));
++		return BCME_ERROR;
++	}
++
++	/* pull wl-header */
++	PKTPULL(ctx->osh, pktbuf, (h->dataOffset << 2));
++	return BCME_OK;
++}
++
++/**
++ * @param[in/out] p packet
++ */
++static wlfc_mac_descriptor_t*
++_dhd_wlfc_find_table_entry(athost_wl_status_info_t* ctx, void* p)
++{
++	int i;
++	wlfc_mac_descriptor_t* table = ctx->destination_entries.nodes;
++	uint8 ifid = DHD_PKTTAG_IF(PKTTAG(p));
++	uint8* dstn = DHD_PKTTAG_DSTN(PKTTAG(p));
++	wlfc_mac_descriptor_t* entry = DHD_PKTTAG_ENTRY(PKTTAG(p));
++	int iftype = ctx->destination_entries.interfaces[ifid].iftype;
++
++	/* saved one exists, return it */
++	if (entry)
++		return entry;
++
++	/* Multicast destination, STA and P2P clients get the interface entry.
++	 * STA/GC gets the Mac Entry for TDLS destinations, TDLS destinations
++	 * have their own entry.
++	 */
++	if ((iftype == WLC_E_IF_ROLE_STA || ETHER_ISMULTI(dstn) ||
++		iftype == WLC_E_IF_ROLE_P2P_CLIENT) &&
++		(ctx->destination_entries.interfaces[ifid].occupied)) {
++			entry = &ctx->destination_entries.interfaces[ifid];
++	}
++
++	if (entry && ETHER_ISMULTI(dstn)) {
++		DHD_PKTTAG_SET_ENTRY(PKTTAG(p), entry);
++		return entry;
++	}
++
++	for (i = 0; i < WLFC_MAC_DESC_TABLE_SIZE; i++) {
++		if (table[i].occupied) {
++			if (table[i].interface_id == ifid) {
++				if (!memcmp(table[i].ea, dstn, ETHER_ADDR_LEN)) {
++					entry = &table[i];
++					break;
++				}
++			}
++		}
++	}
++
++	if (entry == NULL)
++		entry = &ctx->destination_entries.other;
++
++	DHD_PKTTAG_SET_ENTRY(PKTTAG(p), entry);
++
++	return entry;
++} /* _dhd_wlfc_find_table_entry */
++
++/**
++ * In case a packet must be dropped (because eg the queues are full), various tallies have to be
++ * be updated. Called from several other functions.
++ *     @param[in] dhdp pointer to public DHD structure
++ *     @param[in] prec precedence of the packet
++ *     @param[in] p    the packet to be dropped
++ *     @param[in] bPktInQ TRUE if packet is part of a queue
++ */
++static int
++_dhd_wlfc_prec_drop(dhd_pub_t *dhdp, int prec, void* p, bool bPktInQ)
++{
++	athost_wl_status_info_t* ctx;
++	void *pout = NULL;
++
++	ASSERT(dhdp && p);
++	ASSERT(prec >= 0 && prec <= WLFC_PSQ_PREC_COUNT);
++
++	ctx = (athost_wl_status_info_t*)dhdp->wlfc_state;
++
++	if (!WLFC_GET_AFQ(dhdp->wlfc_mode) && (prec & 1)) {
++		/* suppressed queue, need pop from hanger */
++		_dhd_wlfc_hanger_poppkt(ctx->hanger, WL_TXSTATUS_GET_HSLOT(DHD_PKTTAG_H2DTAG
++					(PKTTAG(p))), &pout, TRUE);
++		ASSERT(p == pout);
++	}
++
++	if (!(prec & 1)) {
++#ifdef DHDTCPACK_SUPPRESS
++		/* pkt in delayed q, so fake push BDC header for
++		 * dhd_tcpack_check_xmit() and dhd_txcomplete().
++		 */
++		_dhd_wlfc_pushheader(ctx, &p, FALSE, 0, 0, 0, 0, TRUE);
++
++		/* This packet is about to be freed, so remove it from tcp_ack_info_tbl
++		 * This must be one of...
++		 * 1. A pkt already in delayQ is evicted by another pkt with higher precedence
++		 * in _dhd_wlfc_prec_enq_with_drop()
++		 * 2. A pkt could not be enqueued to delayQ because it is full,
++		 * in _dhd_wlfc_enque_delayq().
++		 * 3. A pkt could not be enqueued to delayQ because it is full,
++		 * in _dhd_wlfc_rollback_packet_toq().
++		 */
++		if (dhd_tcpack_check_xmit(dhdp, p) == BCME_ERROR) {
++			DHD_ERROR(("%s %d: tcpack_suppress ERROR!!!"
++				" Stop using it\n",
++				__FUNCTION__, __LINE__));
++			dhd_tcpack_suppress_set(dhdp, TCPACK_SUP_OFF);
++		}
++#endif /* DHDTCPACK_SUPPRESS */
++	}
++
++	if (bPktInQ) {
++		ctx->pkt_cnt_in_q[DHD_PKTTAG_IF(PKTTAG(p))][prec>>1]--;
++		ctx->pkt_cnt_per_ac[prec>>1]--;
++		ctx->pkt_cnt_in_psq--;
++	}
++
++	ctx->pkt_cnt_in_drv[DHD_PKTTAG_IF(PKTTAG(p))][DHD_PKTTAG_FIFO(PKTTAG(p))]--;
++	ctx->stats.pktout++;
++	ctx->stats.drop_pkts[prec]++;
++
++	dhd_txcomplete(dhdp, p, FALSE);
++	PKTFREE(ctx->osh, p, TRUE);
++
++	return 0;
++} /* _dhd_wlfc_prec_drop */
++
++/**
++ * Called when eg the host handed a new packet over to the driver, or when the dongle reported
++ * that a packet could currently not be transmitted (=suppressed). This function enqueues a transmit
++ * packet in the host driver to be (re)transmitted at a later opportunity.
++ *     @param[in] dhdp pointer to public DHD structure
++ *     @param[in] qHead When TRUE, queue packet at head instead of tail, to preserve d11 sequence
++ */
++static bool
++_dhd_wlfc_prec_enq_with_drop(dhd_pub_t *dhdp, struct pktq *pq, void *pkt, int prec, bool qHead,
++	uint8 current_seq)
++{
++	void *p = NULL;
++	int eprec = -1;		/* precedence to evict from */
++	athost_wl_status_info_t* ctx;
++
++	ASSERT(dhdp && pq && pkt);
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	ctx = (athost_wl_status_info_t*)dhdp->wlfc_state;
++
++	/* Fast case, precedence queue is not full and we are also not
++	 * exceeding total queue length
++	 */
++	if (!pktq_pfull(pq, prec) && !pktq_full(pq)) {
++		goto exit;
++	}
++
++	/* Determine precedence from which to evict packet, if any */
++	if (pktq_pfull(pq, prec)) {
++		eprec = prec;
++	} else if (pktq_full(pq)) {
++		p = pktq_peek_tail(pq, &eprec);
++		if (!p) {
++			DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++			return FALSE;
++		}
++		if ((eprec > prec) || (eprec < 0)) {
++			if (!pktq_pempty(pq, prec)) {
++				eprec = prec;
++			} else {
++				return FALSE;
++			}
++		}
++	}
++
++	/* Evict if needed */
++	if (eprec >= 0) {
++		/* Detect queueing to unconfigured precedence */
++		ASSERT(!pktq_pempty(pq, eprec));
++		/* Evict all fragmented frames */
++		dhd_prec_drop_pkts(dhdp, pq, eprec, _dhd_wlfc_prec_drop);
++	}
++
++exit:
++	/* Enqueue */
++	_dhd_wlfc_prec_enque(pq, prec, pkt, qHead, current_seq,
++		WLFC_GET_REORDERSUPP(dhdp->wlfc_mode));
++	ctx->pkt_cnt_in_q[DHD_PKTTAG_IF(PKTTAG(pkt))][prec>>1]++;
++	ctx->pkt_cnt_per_ac[prec>>1]++;
++	ctx->pkt_cnt_in_psq++;
++
++	return TRUE;
++} /* _dhd_wlfc_prec_enq_with_drop */
++
++/**
++ * Called during eg the 'committing' of a transmit packet from the OS layer to a lower layer, in
++ * the event that this 'commit' failed.
++ */
++static int
++_dhd_wlfc_rollback_packet_toq(athost_wl_status_info_t* ctx,
++	void* p, ewlfc_packet_state_t pkt_type, uint32 hslot)
++{
++	/*
++	 * put the packet back to the head of queue
++	 * - suppressed packet goes back to suppress sub-queue
++	 * - pull out the header, if new or delayed packet
++	 *
++	 * Note: hslot is used only when header removal is done.
++	 */
++	wlfc_mac_descriptor_t* entry;
++	int rc = BCME_OK;
++	int prec, fifo_id;
++
++	entry = _dhd_wlfc_find_table_entry(ctx, p);
++	prec = DHD_PKTTAG_FIFO(PKTTAG(p));
++	fifo_id = prec << 1;
++	if (pkt_type == eWLFC_PKTTYPE_SUPPRESSED)
++		fifo_id += 1;
++	if (entry != NULL) {
++		/*
++		if this packet did not count against FIFO credit, it must have
++		taken a requested_credit from the firmware (for pspoll etc.)
++		*/
++		if ((prec != AC_COUNT) && !DHD_PKTTAG_CREDITCHECK(PKTTAG(p)))
++			entry->requested_credit++;
++
++		if (pkt_type == eWLFC_PKTTYPE_DELAYED) {
++			/* decrement sequence count */
++			WLFC_DECR_SEQCOUNT(entry, prec);
++			/* remove header first */
++			rc = _dhd_wlfc_pullheader(ctx, p);
++			if (rc != BCME_OK) {
++				DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++				goto exit;
++			}
++		}
++
++		if (_dhd_wlfc_prec_enq_with_drop(ctx->dhdp, &entry->psq, p, fifo_id, TRUE,
++			WLFC_SEQCOUNT(entry, fifo_id>>1))
++			== FALSE) {
++			/* enque failed */
++			DHD_ERROR(("Error: %s():%d, fifo_id(%d)\n",
++				__FUNCTION__, __LINE__, fifo_id));
++			rc = BCME_ERROR;
++		}
++	} else {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		rc = BCME_ERROR;
++	}
++
++exit:
++	if (rc != BCME_OK) {
++		ctx->stats.rollback_failed++;
++		_dhd_wlfc_prec_drop(ctx->dhdp, fifo_id, p, FALSE);
++	} else {
++		ctx->stats.rollback++;
++	}
++
++	return rc;
++} /* _dhd_wlfc_rollback_packet_toq */
++
++/** Returns TRUE if host OS -> DHD flow control is allowed on the caller supplied interface */
++static bool
++_dhd_wlfc_allow_fc(athost_wl_status_info_t* ctx, uint8 ifid)
++{
++	int prec, ac_traffic = WLFC_NO_TRAFFIC;
++
++	for (prec = 0; prec < AC_COUNT; prec++) {
++		if (ctx->pkt_cnt_in_drv[ifid][prec] > 0) {
++			if (ac_traffic == WLFC_NO_TRAFFIC)
++				ac_traffic = prec + 1;
++			else if (ac_traffic != (prec + 1))
++				ac_traffic = WLFC_MULTI_TRAFFIC;
++		}
++	}
++
++	if (ac_traffic >= 1 && ac_traffic <= AC_COUNT) {
++		/* single AC (BE/BK/VI/VO) in queue */
++		if (ctx->allow_fc) {
++			return TRUE;
++		} else {
++			uint32 delta;
++			uint32 curr_t = OSL_SYSUPTIME();
++
++			if (ctx->fc_defer_timestamp == 0) {
++				/* first single ac scenario */
++				ctx->fc_defer_timestamp = curr_t;
++				return FALSE;
++			}
++
++			/* single AC duration, this handles wrap around, e.g. 1 - ~0 = 2. */
++			delta = curr_t - ctx->fc_defer_timestamp;
++			if (delta >= WLFC_FC_DEFER_PERIOD_MS) {
++				ctx->allow_fc = TRUE;
++			}
++		}
++	} else {
++		/* multiple ACs or BCMC in queue */
++		ctx->allow_fc = FALSE;
++		ctx->fc_defer_timestamp = 0;
++	}
++
++	return ctx->allow_fc;
++} /* _dhd_wlfc_allow_fc */
++
++/**
++ * Starts or stops the flow of transmit packets from the host OS towards the DHD, depending on
++ * low/high watermarks.
++ */
++static void
++_dhd_wlfc_flow_control_check(athost_wl_status_info_t* ctx, struct pktq* pq, uint8 if_id)
++{
++	dhd_pub_t *dhdp;
++
++	ASSERT(ctx);
++
++	dhdp = (dhd_pub_t *)ctx->dhdp;
++	ASSERT(dhdp);
++
++	if (dhdp->skip_fc && dhdp->skip_fc())
++		return;
++
++	if ((ctx->hostif_flow_state[if_id] == OFF) && !_dhd_wlfc_allow_fc(ctx, if_id))
++		return;
++
++	if ((pq->len <= WLFC_FLOWCONTROL_LOWATER) && (ctx->hostif_flow_state[if_id] == ON)) {
++		/* start traffic */
++		ctx->hostif_flow_state[if_id] = OFF;
++		/*
++		WLFC_DBGMESG(("qlen:%02d, if:%02d, ->OFF, start traffic %s()\n",
++		pq->len, if_id, __FUNCTION__));
++		*/
++		WLFC_DBGMESG(("F"));
++
++		dhd_txflowcontrol(dhdp, if_id, OFF);
++
++		ctx->toggle_host_if = 0;
++	}
++
++	if ((pq->len >= WLFC_FLOWCONTROL_HIWATER) && (ctx->hostif_flow_state[if_id] == OFF)) {
++		/* stop traffic */
++		ctx->hostif_flow_state[if_id] = ON;
++		/*
++		WLFC_DBGMESG(("qlen:%02d, if:%02d, ->ON, stop traffic   %s()\n",
++		pq->len, if_id, __FUNCTION__));
++		*/
++		WLFC_DBGMESG(("N"));
++
++		dhd_txflowcontrol(dhdp, if_id, ON);
++
++		ctx->host_ifidx = if_id;
++		ctx->toggle_host_if = 1;
++	}
++
++	return;
++} /* _dhd_wlfc_flow_control_check */
++
++static int
++_dhd_wlfc_send_signalonly_packet(athost_wl_status_info_t* ctx, wlfc_mac_descriptor_t* entry,
++	uint8 ta_bmp)
++{
++	int rc = BCME_OK;
++	void* p = NULL;
++	int dummylen = ((dhd_pub_t *)ctx->dhdp)->hdrlen+ 16;
++	dhd_pub_t *dhdp = (dhd_pub_t *)ctx->dhdp;
++
++	if (dhdp->proptxstatus_txoff) {
++		rc = BCME_NORESOURCE;
++		return rc;
++	}
++
++	/* allocate a dummy packet */
++	p = PKTGET(ctx->osh, dummylen, TRUE);
++	if (p) {
++		PKTPULL(ctx->osh, p, dummylen);
++		DHD_PKTTAG_SET_H2DTAG(PKTTAG(p), 0);
++		_dhd_wlfc_pushheader(ctx, &p, TRUE, ta_bmp, entry->mac_handle, 0, 0, FALSE);
++		DHD_PKTTAG_SETSIGNALONLY(PKTTAG(p), 1);
++		DHD_PKTTAG_WLFCPKT_SET(PKTTAG(p), 1);
++#ifdef PROP_TXSTATUS_DEBUG
++		ctx->stats.signal_only_pkts_sent++;
++#endif
++
++#if defined(BCMPCIE)
++		rc = dhd_bus_txdata(dhdp->bus, p, ctx->host_ifidx);
++#elif defined(BCMDBUS)
++		rc = dhd_dbus_txdata(dhdp, p);
++#else
++		rc = dhd_bus_txdata(dhdp->bus, p);
++#endif
++		if (rc != BCME_OK) {
++			_dhd_wlfc_pullheader(ctx, p);
++			PKTFREE(ctx->osh, p, TRUE);
++		}
++	} else {
++		DHD_ERROR(("%s: couldn't allocate new %d-byte packet\n",
++		           __FUNCTION__, dummylen));
++		rc = BCME_NOMEM;
++		dhdp->tx_pktgetfail++;
++	}
++
++	return rc;
++} /* _dhd_wlfc_send_signalonly_packet */
++
++/**
++ * Called on eg receiving 'mac close' indication from dongle. Updates the per-MAC administration
++ * maintained in caller supplied parameter 'entry'.
++ *
++ *    @param[in/out] entry  administration about a remote MAC entity
++ *    @param[in]     prec   precedence queue for this remote MAC entitity
++ *
++ * Return value: TRUE if traffic availability changed
++ */
++static bool
++_dhd_wlfc_traffic_pending_check(athost_wl_status_info_t* ctx, wlfc_mac_descriptor_t* entry,
++	int prec)
++{
++	bool rc = FALSE;
++
++	if (entry->state == WLFC_STATE_CLOSE) {
++		if ((pktq_plen(&entry->psq, (prec << 1)) == 0) &&
++			(pktq_plen(&entry->psq, ((prec << 1) + 1)) == 0)) {
++			/* no packets in both 'normal' and 'suspended' queues */
++			if (entry->traffic_pending_bmp & NBITVAL(prec)) {
++				rc = TRUE;
++				entry->traffic_pending_bmp =
++					entry->traffic_pending_bmp & ~ NBITVAL(prec);
++			}
++		} else {
++			/* packets are queued in host for transmission to dongle */
++			if (!(entry->traffic_pending_bmp & NBITVAL(prec))) {
++				rc = TRUE;
++				entry->traffic_pending_bmp =
++					entry->traffic_pending_bmp | NBITVAL(prec);
++			}
++		}
++	}
++
++	if (rc) {
++		/* request a TIM update to firmware at the next piggyback opportunity */
++		if (entry->traffic_lastreported_bmp != entry->traffic_pending_bmp) {
++			entry->send_tim_signal = 1;
++			_dhd_wlfc_send_signalonly_packet(ctx, entry, entry->traffic_pending_bmp);
++			entry->traffic_lastreported_bmp = entry->traffic_pending_bmp;
++			entry->send_tim_signal = 0;
++		} else {
++			rc = FALSE;
++		}
++	}
++
++	return rc;
++} /* _dhd_wlfc_traffic_pending_check */
++
++/**
++ * Called on receiving a 'd11 suppressed' or 'wl suppressed' tx status from the firmware. Enqueues
++ * the packet to transmit to firmware again at a later opportunity.
++ */
++static int
++_dhd_wlfc_enque_suppressed(athost_wl_status_info_t* ctx, int prec, void* p)
++{
++	wlfc_mac_descriptor_t* entry;
++
++	entry = _dhd_wlfc_find_table_entry(ctx, p);
++	if (entry == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_NOTFOUND;
++	}
++	/*
++	- suppressed packets go to sub_queue[2*prec + 1] AND
++	- delayed packets go to sub_queue[2*prec + 0] to ensure
++	order of delivery.
++	*/
++	if (_dhd_wlfc_prec_enq_with_drop(ctx->dhdp, &entry->psq, p, ((prec << 1) + 1), FALSE,
++		WLFC_SEQCOUNT(entry, prec))
++		== FALSE) {
++		ctx->stats.delayq_full_error++;
++		/* WLFC_DBGMESG(("Error: %s():%d\n", __FUNCTION__, __LINE__)); */
++		WLFC_DBGMESG(("s"));
++		return BCME_ERROR;
++	}
++
++	/* A packet has been pushed, update traffic availability bitmap, if applicable */
++	_dhd_wlfc_traffic_pending_check(ctx, entry, prec);
++	_dhd_wlfc_flow_control_check(ctx, &entry->psq, DHD_PKTTAG_IF(PKTTAG(p)));
++	return BCME_OK;
++}
++
++/**
++ * Called when a transmit packet is about to be 'committed' from the OS layer to a lower layer
++ * towards the dongle (eg the DBUS layer). Updates wlfc administration. May modify packet.
++ *
++ *     @param[in/out] ctx    driver specific flow control administration
++ *     @param[in/out] entry  The remote MAC entity for which the packet is destined.
++ *     @param[in/out] packet Packet to send. This function optionally adds TLVs to the packet.
++ *     @param[in] header_needed True if packet is 'new' to flow control
++ *     @param[out] slot Handle to container in which the packet was 'parked'
++ */
++static int
++_dhd_wlfc_pretx_pktprocess(athost_wl_status_info_t* ctx,
++	wlfc_mac_descriptor_t* entry, void** packet, int header_needed, uint32* slot)
++{
++	int rc = BCME_OK;
++	int hslot = WLFC_HANGER_MAXITEMS;
++	bool send_tim_update = FALSE;
++	uint32 htod = 0;
++	uint16 htodseq = 0;
++	uint8 free_ctr;
++	int gen = 0xff;
++	dhd_pub_t *dhdp = (dhd_pub_t *)ctx->dhdp;
++	void * p = *packet;
++
++	*slot = hslot;
++
++	if (entry == NULL) {
++		entry = _dhd_wlfc_find_table_entry(ctx, p);
++	}
++
++	if (entry == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_ERROR;
++	}
++
++	if (entry->send_tim_signal) {
++		/* sends a traffic indication bitmap to the dongle */
++		send_tim_update = TRUE;
++		entry->send_tim_signal = 0;
++		entry->traffic_lastreported_bmp = entry->traffic_pending_bmp;
++	}
++
++	if (header_needed) {
++		if (WLFC_GET_AFQ(dhdp->wlfc_mode)) {
++			hslot = (uint)(entry - &ctx->destination_entries.nodes[0]);
++		} else {
++			hslot = _dhd_wlfc_hanger_get_free_slot(ctx->hanger);
++		}
++		gen = entry->generation;
++		free_ctr = WLFC_SEQCOUNT(entry, DHD_PKTTAG_FIFO(PKTTAG(p)));
++	} else {
++		if (WLFC_GET_REUSESEQ(dhdp->wlfc_mode)) {
++			htodseq = DHD_PKTTAG_H2DSEQ(PKTTAG(p));
++		}
++
++		hslot = WL_TXSTATUS_GET_HSLOT(DHD_PKTTAG_H2DTAG(PKTTAG(p)));
++
++		if (WLFC_GET_REORDERSUPP(dhdp->wlfc_mode)) {
++			gen = entry->generation;
++		} else if (WLFC_GET_AFQ(dhdp->wlfc_mode)) {
++			gen = WL_TXSTATUS_GET_GENERATION(DHD_PKTTAG_H2DTAG(PKTTAG(p)));
++		} else {
++			_dhd_wlfc_hanger_get_genbit(ctx->hanger, p, hslot, &gen);
++		}
++
++		free_ctr = WL_TXSTATUS_GET_FREERUNCTR(DHD_PKTTAG_H2DTAG(PKTTAG(p)));
++		/* remove old header */
++		_dhd_wlfc_pullheader(ctx, p);
++	}
++
++	if (hslot >= WLFC_HANGER_MAXITEMS) {
++		DHD_ERROR(("Error: %s():no hanger slot available\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	WL_TXSTATUS_SET_FREERUNCTR(htod, free_ctr);
++	WL_TXSTATUS_SET_HSLOT(htod, hslot);
++	WL_TXSTATUS_SET_FIFO(htod, DHD_PKTTAG_FIFO(PKTTAG(p)));
++	WL_TXSTATUS_SET_FLAGS(htod, WLFC_PKTFLAG_PKTFROMHOST);
++	WL_TXSTATUS_SET_GENERATION(htod, gen);
++	DHD_PKTTAG_SETPKTDIR(PKTTAG(p), 1);
++
++	if (!DHD_PKTTAG_CREDITCHECK(PKTTAG(p))) {
++		/*
++		Indicate that this packet is being sent in response to an
++		explicit request from the firmware side.
++		*/
++		WLFC_PKTFLAG_SET_PKTREQUESTED(htod);
++	} else {
++		WLFC_PKTFLAG_CLR_PKTREQUESTED(htod);
++	}
++
++	rc = _dhd_wlfc_pushheader(ctx, &p, send_tim_update,
++		entry->traffic_lastreported_bmp, entry->mac_handle, htod, htodseq, FALSE);
++	if (rc == BCME_OK) {
++		DHD_PKTTAG_SET_H2DTAG(PKTTAG(p), htod);
++
++		if (!WLFC_GET_AFQ(dhdp->wlfc_mode)) {
++			wlfc_hanger_t *h = (wlfc_hanger_t*)(ctx->hanger);
++			if (header_needed) {
++				/*
++				a new header was created for this packet.
++				push to hanger slot and scrub q. Since bus
++				send succeeded, increment seq number as well.
++				*/
++				rc = _dhd_wlfc_hanger_pushpkt(ctx->hanger, p, hslot);
++				if (rc == BCME_OK) {
++#ifdef PROP_TXSTATUS_DEBUG
++					h->items[hslot].push_time =
++						OSL_SYSUPTIME();
++#endif
++				} else {
++					DHD_ERROR(("%s() hanger_pushpkt() failed, rc: %d\n",
++						__FUNCTION__, rc));
++				}
++			} else {
++				/* clear hanger state */
++				if (((wlfc_hanger_t*)(ctx->hanger))->items[hslot].pkt != p)
++					DHD_ERROR(("%s() pkt not match: cur %p, hanger pkt %p\n",
++						__FUNCTION__, p, h->items[hslot].pkt));
++				ASSERT(h->items[hslot].pkt == p);
++				bcm_object_feature_set(h->items[hslot].pkt,
++					BCM_OBJECT_FEATURE_PKT_STATE, 0);
++				h->items[hslot].pkt_state = 0;
++				h->items[hslot].pkt_txstatus = 0;
++				h->items[hslot].state = WLFC_HANGER_ITEM_STATE_INUSE;
++			}
++		} else if (!WLFC_GET_AFQ(dhdp->wlfc_mode)) {
++			/* clear hanger state */
++			((wlfc_hanger_t*)(ctx->hanger))->items[hslot].pkt_state = 0;
++			((wlfc_hanger_t*)(ctx->hanger))->items[hslot].pkt_txstatus = 0;
++		}
++
++		if ((rc == BCME_OK) && header_needed) {
++			/* increment free running sequence count */
++			WLFC_INCR_SEQCOUNT(entry, DHD_PKTTAG_FIFO(PKTTAG(p)));
++		}
++	}
++	*slot = hslot;
++	*packet = p;
++	return rc;
++} /* _dhd_wlfc_pretx_pktprocess */
++
++/**
++ * A remote wireless mac may be temporarily 'closed' due to power management. Returns '1' if remote
++ * mac is in the 'open' state, otherwise '0'.
++ */
++static int
++_dhd_wlfc_is_destination_open(athost_wl_status_info_t* ctx,
++	wlfc_mac_descriptor_t* entry, int prec)
++{
++	if (entry->interface_id >= WLFC_MAX_IFNUM) {
++		ASSERT(&ctx->destination_entries.other == entry);
++		return 1;
++	}
++
++	if (ctx->destination_entries.interfaces[entry->interface_id].iftype ==
++		WLC_E_IF_ROLE_P2P_GO) {
++		/* - destination interface is of type p2p GO.
++		For a p2pGO interface, if the destination is OPEN but the interface is
++		CLOSEd, do not send traffic. But if the dstn is CLOSEd while there is
++		destination-specific-credit left send packets. This is because the
++		firmware storing the destination-specific-requested packet in queue.
++		*/
++		if ((entry->state == WLFC_STATE_CLOSE) && (entry->requested_credit == 0) &&
++			(entry->requested_packet == 0)) {
++			return 0;
++		}
++	}
++
++	/* AP, p2p_go -> unicast desc entry, STA/p2p_cl -> interface desc. entry */
++	if (((entry->state == WLFC_STATE_CLOSE) && (entry->requested_credit == 0) &&
++		(entry->requested_packet == 0)) ||
++		(!(entry->ac_bitmap & (1 << prec)))) {
++		return 0;
++	}
++
++	return 1;
++} /* _dhd_wlfc_is_destination_open */
++
++/**
++ * Dequeues a suppressed or delayed packet from a queue
++ *    @param[in/out] ctx          Driver specific flow control administration
++ *    @param[in]  prec            Precedence of queue to dequeue from
++ *    @param[out] ac_credit_spent Boolean, returns 0 or 1
++ *    @param[out] needs_hdr       Boolean, returns 0 or 1
++ *    @param[out] entry_out       The remote MAC for which the packet is destined
++ *    @param[in]  only_no_credit  If TRUE, searches all entries instead of just the active ones
++ *
++ * Return value: the dequeued packet
++ */
++static void*
++_dhd_wlfc_deque_delayedq(athost_wl_status_info_t* ctx, int prec,
++	uint8* ac_credit_spent, uint8* needs_hdr, wlfc_mac_descriptor_t** entry_out,
++	bool only_no_credit)
++{
++	wlfc_mac_descriptor_t* entry;
++	int total_entries;
++	void* p = NULL;
++	int i;
++	uint8 credit_spent = ((prec == AC_COUNT) && !ctx->bcmc_credit_supported) ? 0 : 1;
++
++	*entry_out = NULL;
++	/* most cases a packet will count against FIFO credit */
++	*ac_credit_spent = credit_spent;
++
++	/* search all entries, include nodes as well as interfaces */
++	if (only_no_credit) {
++		total_entries = ctx->requested_entry_count;
++	} else {
++		total_entries = ctx->active_entry_count;
++	}
++
++	for (i = 0; i < total_entries; i++) {
++		if (only_no_credit) {
++			entry = ctx->requested_entry[i];
++		} else {
++			entry = ctx->active_entry_head;
++			/* move head to ensure fair round-robin */
++			ctx->active_entry_head = ctx->active_entry_head->next;
++		}
++		ASSERT(entry);
++
++		if (entry->occupied && _dhd_wlfc_is_destination_open(ctx, entry, prec) &&
++			(entry->transit_count < WL_TXSTATUS_FREERUNCTR_MASK) &&
++			(!entry->suppressed)) {
++			*ac_credit_spent = credit_spent;
++			if (entry->state == WLFC_STATE_CLOSE) {
++				*ac_credit_spent = 0;
++			}
++
++			/* higher precedence will be picked up first,
++			 * i.e. suppressed packets before delayed ones
++			 */
++			p = pktq_pdeq(&entry->psq, PSQ_SUP_IDX(prec));
++			*needs_hdr = 0;
++			if (p == NULL) {
++				/* De-Q from delay Q */
++				p = pktq_pdeq(&entry->psq, PSQ_DLY_IDX(prec));
++				*needs_hdr = 1;
++			}
++
++			if (p != NULL) {
++				bcm_pkt_validate_chk(p);
++				/* did the packet come from suppress sub-queue? */
++				if (entry->requested_credit > 0) {
++					entry->requested_credit--;
++#ifdef PROP_TXSTATUS_DEBUG
++					entry->dstncredit_sent_packets++;
++#endif
++				} else if (entry->requested_packet > 0) {
++					entry->requested_packet--;
++					DHD_PKTTAG_SETONETIMEPKTRQST(PKTTAG(p));
++				}
++
++				*entry_out = entry;
++				ctx->pkt_cnt_in_q[DHD_PKTTAG_IF(PKTTAG(p))][prec]--;
++				ctx->pkt_cnt_per_ac[prec]--;
++				ctx->pkt_cnt_in_psq--;
++				_dhd_wlfc_flow_control_check(ctx, &entry->psq,
++					DHD_PKTTAG_IF(PKTTAG(p)));
++				/*
++				 * A packet has been picked up, update traffic availability bitmap,
++				 * if applicable.
++				 */
++				_dhd_wlfc_traffic_pending_check(ctx, entry, prec);
++				return p;
++			}
++		}
++	}
++	return NULL;
++} /* _dhd_wlfc_deque_delayedq */
++
++/** Enqueues caller supplied packet on either a 'suppressed' or 'delayed' queue */
++static int
++_dhd_wlfc_enque_delayq(athost_wl_status_info_t* ctx, void* pktbuf, int prec)
++{
++	wlfc_mac_descriptor_t* entry;
++
++	if (pktbuf != NULL) {
++		entry = _dhd_wlfc_find_table_entry(ctx, pktbuf);
++		if (entry == NULL) {
++			DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++			return BCME_ERROR;
++		}
++
++		/*
++		- suppressed packets go to sub_queue[2*prec + 1] AND
++		- delayed packets go to sub_queue[2*prec + 0] to ensure
++		order of delivery.
++		*/
++		if (_dhd_wlfc_prec_enq_with_drop(ctx->dhdp, &entry->psq, pktbuf, (prec << 1),
++			FALSE, WLFC_SEQCOUNT(entry, prec))
++			== FALSE) {
++			WLFC_DBGMESG(("D"));
++			ctx->stats.delayq_full_error++;
++			return BCME_ERROR;
++		}
++
++
++		/* A packet has been pushed, update traffic availability bitmap, if applicable */
++		_dhd_wlfc_traffic_pending_check(ctx, entry, prec);
++	}
++
++	return BCME_OK;
++} /* _dhd_wlfc_enque_delayq */
++
++/** Returns TRUE if caller supplied packet is destined for caller supplied interface */
++static bool _dhd_wlfc_ifpkt_fn(void* p, void *p_ifid)
++{
++	if (!p || !p_ifid)
++		return FALSE;
++
++	return (DHD_PKTTAG_WLFCPKT(PKTTAG(p))&& (*((uint8 *)p_ifid) == DHD_PKTTAG_IF(PKTTAG(p))));
++}
++
++/** Returns TRUE if caller supplied packet is destined for caller supplied remote MAC */
++static bool _dhd_wlfc_entrypkt_fn(void* p, void *entry)
++{
++	if (!p || !entry)
++		return FALSE;
++
++	return (DHD_PKTTAG_WLFCPKT(PKTTAG(p))&& (entry == DHD_PKTTAG_ENTRY(PKTTAG(p))));
++}
++
++static void
++_dhd_wlfc_return_implied_credit(athost_wl_status_info_t* wlfc, void* pkt)
++{
++	dhd_pub_t *dhdp;
++	bool credit_return = FALSE;
++
++	if (!wlfc || !pkt) {
++		return;
++	}
++
++	dhdp = (dhd_pub_t *)(wlfc->dhdp);
++	if (dhdp && (dhdp->proptxstatus_mode == WLFC_FCMODE_IMPLIED_CREDIT) &&
++		DHD_PKTTAG_CREDITCHECK(PKTTAG(pkt))) {
++		int lender, credit_returned = 0;
++		uint8 fifo_id = DHD_PKTTAG_FIFO(PKTTAG(pkt));
++
++		credit_return = TRUE;
++
++		/* Note that borrower is fifo_id */
++		/* Return credits to highest priority lender first */
++		for (lender = AC_COUNT; lender >= 0; lender--) {
++			if (wlfc->credits_borrowed[fifo_id][lender] > 0) {
++				wlfc->FIFO_credit[lender]++;
++				wlfc->credits_borrowed[fifo_id][lender]--;
++				credit_returned = 1;
++				break;
++			}
++		}
++
++		if (!credit_returned) {
++			wlfc->FIFO_credit[fifo_id]++;
++		}
++	}
++
++	BCM_REFERENCE(credit_return);
++#if defined(DHD_WLFC_THREAD)
++	if (credit_return) {
++		_dhd_wlfc_thread_wakeup(dhdp);
++	}
++#endif /* defined(DHD_WLFC_THREAD) */
++}
++
++/** Removes and frees a packet from the hanger. Called during eg tx complete. */
++static void
++_dhd_wlfc_hanger_free_pkt(athost_wl_status_info_t* wlfc, uint32 slot_id, uint8 pkt_state,
++	int pkt_txstatus)
++{
++	wlfc_hanger_t* hanger;
++	wlfc_hanger_item_t* item;
++
++	if (!wlfc)
++		return;
++
++	hanger = (wlfc_hanger_t*)wlfc->hanger;
++	if (!hanger)
++		return;
++
++	if (slot_id == WLFC_HANGER_MAXITEMS)
++		return;
++
++	item = &hanger->items[slot_id];
++
++	if (item->pkt) {
++		item->pkt_state |= pkt_state;
++		if (pkt_txstatus != -1)
++			item->pkt_txstatus = (uint8)pkt_txstatus;
++		bcm_object_feature_set(item->pkt, BCM_OBJECT_FEATURE_PKT_STATE, item->pkt_state);
++		if (item->pkt_state == WLFC_HANGER_PKT_STATE_COMPLETE) {
++			void *p = NULL;
++			void *pkt = item->pkt;
++			uint8 old_state = item->state;
++			int ret = _dhd_wlfc_hanger_poppkt(wlfc->hanger, slot_id, &p, TRUE);
++			BCM_REFERENCE(ret);
++			BCM_REFERENCE(pkt);
++			ASSERT((ret == BCME_OK) && p && (pkt == p));
++			if (old_state == WLFC_HANGER_ITEM_STATE_INUSE_SUPPRESSED) {
++				printf("ERROR: free a suppressed pkt %p state %d pkt_state %d\n",
++					pkt, old_state, item->pkt_state);
++			}
++			ASSERT(old_state != WLFC_HANGER_ITEM_STATE_INUSE_SUPPRESSED);
++
++			/* free packet */
++			wlfc->pkt_cnt_in_drv[DHD_PKTTAG_IF(PKTTAG(p))]
++				[DHD_PKTTAG_FIFO(PKTTAG(p))]--;
++			wlfc->stats.pktout++;
++			dhd_txcomplete((dhd_pub_t *)wlfc->dhdp, p, item->pkt_txstatus);
++			PKTFREE(wlfc->osh, p, TRUE);
++		}
++	} else {
++		/* free slot */
++		if (item->state == WLFC_HANGER_ITEM_STATE_FREE)
++			DHD_ERROR(("Error: %s():%d Multiple TXSTATUS or BUSRETURNED: %d (%d)\n",
++			    __FUNCTION__, __LINE__, item->pkt_state, pkt_state));
++		item->state = WLFC_HANGER_ITEM_STATE_FREE;
++	}
++} /* _dhd_wlfc_hanger_free_pkt */
++
++/** Called during eg detach() */
++static void
++_dhd_wlfc_pktq_flush(athost_wl_status_info_t* ctx, struct pktq *pq,
++	bool dir, f_processpkt_t fn, void *arg, q_type_t q_type)
++{
++	int prec;
++	dhd_pub_t *dhdp = (dhd_pub_t *)ctx->dhdp;
++
++	ASSERT(dhdp);
++
++	/* Optimize flush, if pktq len = 0, just return.
++	 * pktq len of 0 means pktq's prec q's are all empty.
++	 */
++	if (pq->len == 0) {
++		return;
++	}
++
++	for (prec = 0; prec < pq->num_prec; prec++) {
++		struct pktq_prec *q;
++		void *p, *prev = NULL;
++
++		q = &pq->q[prec];
++		p = q->head;
++		while (p) {
++			bcm_pkt_validate_chk(p);
++			if (fn == NULL || (*fn)(p, arg)) {
++				bool head = (p == q->head);
++				if (head)
++					q->head = PKTLINK(p);
++				else
++					PKTSETLINK(prev, PKTLINK(p));
++				if (q_type == Q_TYPE_PSQ) {
++					if (!WLFC_GET_AFQ(dhdp->wlfc_mode) && (prec & 1)) {
++						_dhd_wlfc_hanger_remove_reference(ctx->hanger, p);
++					}
++					ctx->pkt_cnt_in_q[DHD_PKTTAG_IF(PKTTAG(p))][prec>>1]--;
++					ctx->pkt_cnt_per_ac[prec>>1]--;
++					ctx->pkt_cnt_in_psq--;
++					ctx->stats.cleanup_psq_cnt++;
++					if (!(prec & 1)) {
++						/* pkt in delayed q, so fake push BDC header for
++						 * dhd_tcpack_check_xmit() and dhd_txcomplete().
++						 */
++						_dhd_wlfc_pushheader(ctx, &p, FALSE, 0, 0,
++							0, 0, TRUE);
++#ifdef DHDTCPACK_SUPPRESS
++						if (dhd_tcpack_check_xmit(dhdp, p) == BCME_ERROR) {
++							DHD_ERROR(("%s %d: tcpack_suppress ERROR!!!"
++								" Stop using it\n",
++								__FUNCTION__, __LINE__));
++							dhd_tcpack_suppress_set(dhdp,
++								TCPACK_SUP_OFF);
++						}
++#endif /* DHDTCPACK_SUPPRESS */
++					}
++				} else if (q_type == Q_TYPE_AFQ) {
++					wlfc_mac_descriptor_t* entry =
++						_dhd_wlfc_find_table_entry(ctx, p);
++					if (entry->transit_count)
++						entry->transit_count--;
++					if (entry->suppr_transit_count) {
++						entry->suppr_transit_count--;
++						if (entry->suppressed &&
++							(!entry->onbus_pkts_count) &&
++							(!entry->suppr_transit_count))
++							entry->suppressed = FALSE;
++					}
++					_dhd_wlfc_return_implied_credit(ctx, p);
++					ctx->stats.cleanup_fw_cnt++;
++				}
++				PKTSETLINK(p, NULL);
++				if (dir) {
++					ctx->pkt_cnt_in_drv[DHD_PKTTAG_IF(PKTTAG(p))][prec>>1]--;
++					ctx->stats.pktout++;
++					dhd_txcomplete(dhdp, p, FALSE);
++				}
++				PKTFREE(ctx->osh, p, dir);
++
++				q->len--;
++				pq->len--;
++				p = (head ? q->head : PKTLINK(prev));
++			} else {
++				prev = p;
++				p = PKTLINK(p);
++			}
++		}
++
++		if (q->head == NULL) {
++			ASSERT(q->len == 0);
++			q->tail = NULL;
++		}
++
++	}
++
++	if (fn == NULL)
++		ASSERT(pq->len == 0);
++} /* _dhd_wlfc_pktq_flush */
++
++#ifndef BCMDBUS
++
++/** !BCMDBUS specific function. Dequeues a packet from the caller supplied queue. */
++static void*
++_dhd_wlfc_pktq_pdeq_with_fn(struct pktq *pq, int prec, f_processpkt_t fn, void *arg)
++{
++	struct pktq_prec *q;
++	void *p, *prev = NULL;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	q = &pq->q[prec];
++	p = q->head;
++
++	while (p) {
++		if (fn == NULL || (*fn)(p, arg)) {
++			break;
++		} else {
++			prev = p;
++			p = PKTLINK(p);
++		}
++	}
++	if (p == NULL)
++		return NULL;
++
++	bcm_pkt_validate_chk(p);
++
++	if (prev == NULL) {
++		if ((q->head = PKTLINK(p)) == NULL) {
++			q->tail = NULL;
++		}
++	} else {
++		PKTSETLINK(prev, PKTLINK(p));
++		if (q->tail == p) {
++			q->tail = prev;
++		}
++	}
++
++	q->len--;
++
++	pq->len--;
++
++	PKTSETLINK(p, NULL);
++
++	return p;
++}
++
++/** !BCMDBUS specific function */
++static void
++_dhd_wlfc_cleanup_txq(dhd_pub_t *dhd, f_processpkt_t fn, void *arg)
++{
++	int prec;
++	void *pkt = NULL, *head = NULL, *tail = NULL;
++	struct pktq *txq = (struct pktq *)dhd_bus_txq(dhd->bus);
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	wlfc_hanger_t* h = (wlfc_hanger_t*)wlfc->hanger;
++	wlfc_mac_descriptor_t* entry;
++
++	dhd_os_sdlock_txq(dhd);
++	for (prec = 0; prec < txq->num_prec; prec++) {
++		while ((pkt = _dhd_wlfc_pktq_pdeq_with_fn(txq, prec, fn, arg))) {
++#ifdef DHDTCPACK_SUPPRESS
++			if (dhd_tcpack_check_xmit(dhd, pkt) == BCME_ERROR) {
++				DHD_ERROR(("%s %d: tcpack_suppress ERROR!!! Stop using it\n",
++					__FUNCTION__, __LINE__));
++				dhd_tcpack_suppress_set(dhd, TCPACK_SUP_OFF);
++			}
++#endif /* DHDTCPACK_SUPPRESS */
++			if (!head) {
++				head = pkt;
++			}
++			if (tail) {
++				PKTSETLINK(tail, pkt);
++			}
++			tail = pkt;
++		}
++	}
++	dhd_os_sdunlock_txq(dhd);
++
++
++	while ((pkt = head)) {
++		head = PKTLINK(pkt);
++		PKTSETLINK(pkt, NULL);
++		entry = _dhd_wlfc_find_table_entry(wlfc, pkt);
++
++		if (!WLFC_GET_AFQ(dhd->wlfc_mode) &&
++			!_dhd_wlfc_hanger_remove_reference(h, pkt)) {
++			DHD_ERROR(("%s: can't find pkt(%p) in hanger, free it anyway\n",
++				__FUNCTION__, pkt));
++		}
++		if (entry->transit_count)
++			entry->transit_count--;
++		if (entry->suppr_transit_count) {
++			entry->suppr_transit_count--;
++			if (entry->suppressed &&
++				(!entry->onbus_pkts_count) &&
++				(!entry->suppr_transit_count))
++				entry->suppressed = FALSE;
++		}
++		_dhd_wlfc_return_implied_credit(wlfc, pkt);
++		wlfc->pkt_cnt_in_drv[DHD_PKTTAG_IF(PKTTAG(pkt))][DHD_PKTTAG_FIFO(PKTTAG(pkt))]--;
++		wlfc->stats.pktout++;
++		wlfc->stats.cleanup_txq_cnt++;
++		dhd_txcomplete(dhd, pkt, FALSE);
++		PKTFREE(wlfc->osh, pkt, TRUE);
++	}
++} /* _dhd_wlfc_cleanup_txq */
++
++#endif /* !BCMDBUS */
++
++/** called during eg detach */
++void
++_dhd_wlfc_cleanup(dhd_pub_t *dhd, f_processpkt_t fn, void *arg)
++{
++	int i;
++	int total_entries;
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	wlfc_mac_descriptor_t* table;
++	wlfc_hanger_t* h = (wlfc_hanger_t*)wlfc->hanger;
++
++	wlfc->stats.cleanup_txq_cnt = 0;
++	wlfc->stats.cleanup_psq_cnt = 0;
++	wlfc->stats.cleanup_fw_cnt = 0;
++
++	/*
++	*  flush sequence should be txq -> psq -> hanger/afq, hanger has to be last one
++	*/
++#ifndef BCMDBUS
++	/* flush bus->txq */
++	_dhd_wlfc_cleanup_txq(dhd, fn, arg);
++#endif /* BCMDBUS */
++
++	/* flush psq, search all entries, include nodes as well as interfaces */
++	total_entries = sizeof(wlfc->destination_entries)/sizeof(wlfc_mac_descriptor_t);
++	table = (wlfc_mac_descriptor_t*)&wlfc->destination_entries;
++
++	for (i = 0; i < total_entries; i++) {
++		if (table[i].occupied) {
++			/* release packets held in PSQ (both delayed and suppressed) */
++			if (table[i].psq.len) {
++				WLFC_DBGMESG(("%s(): PSQ[%d].len = %d\n",
++					__FUNCTION__, i, table[i].psq.len));
++				_dhd_wlfc_pktq_flush(wlfc, &table[i].psq, TRUE,
++					fn, arg, Q_TYPE_PSQ);
++			}
++
++			/* free packets held in AFQ */
++			if (WLFC_GET_AFQ(dhd->wlfc_mode) && (table[i].afq.len)) {
++				_dhd_wlfc_pktq_flush(wlfc, &table[i].afq, TRUE,
++					fn, arg, Q_TYPE_AFQ);
++			}
++
++			if ((fn == NULL) && (&table[i] != &wlfc->destination_entries.other)) {
++				table[i].occupied = 0;
++				if (table[i].transit_count || table[i].suppr_transit_count) {
++					DHD_ERROR(("%s: table[%d] transit(%d), suppr_tansit(%d)\n",
++						__FUNCTION__, i,
++						table[i].transit_count,
++						table[i].suppr_transit_count));
++				}
++			}
++		}
++	}
++
++	/*
++		. flush remained pkt in hanger queue, not in bus->txq nor psq.
++		. the remained pkt was successfully downloaded to dongle already.
++		. hanger slot state cannot be set to free until receive txstatus update.
++	*/
++	if (!WLFC_GET_AFQ(dhd->wlfc_mode)) {
++		for (i = 0; i < h->max_items; i++) {
++			if ((h->items[i].state == WLFC_HANGER_ITEM_STATE_INUSE) ||
++				(h->items[i].state == WLFC_HANGER_ITEM_STATE_INUSE_SUPPRESSED)) {
++				if (fn == NULL || (*fn)(h->items[i].pkt, arg)) {
++					h->items[i].state = WLFC_HANGER_ITEM_STATE_FLUSHED;
++				}
++			}
++		}
++	}
++
++	return;
++} /* _dhd_wlfc_cleanup */
++
++/** Called after eg the dongle signalled a new remote MAC that it connected with to the DHD */
++static int
++_dhd_wlfc_mac_entry_update(athost_wl_status_info_t* ctx, wlfc_mac_descriptor_t* entry,
++	uint8 action, uint8 ifid, uint8 iftype, uint8* ea,
++	f_processpkt_t fn, void *arg)
++{
++	int rc = BCME_OK;
++
++
++	if ((action == eWLFC_MAC_ENTRY_ACTION_ADD) || (action == eWLFC_MAC_ENTRY_ACTION_UPDATE)) {
++		entry->occupied = 1;
++		entry->state = WLFC_STATE_OPEN;
++		entry->requested_credit = 0;
++		entry->interface_id = ifid;
++		entry->iftype = iftype;
++		entry->ac_bitmap = 0xff; /* update this when handling APSD */
++
++		/* for an interface entry we may not care about the MAC address */
++		if (ea != NULL)
++			memcpy(&entry->ea[0], ea, ETHER_ADDR_LEN);
++
++		if (action == eWLFC_MAC_ENTRY_ACTION_ADD) {
++			entry->suppressed = FALSE;
++			entry->transit_count = 0;
++			entry->suppr_transit_count = 0;
++			entry->onbus_pkts_count = 0;
++		}
++
++		if (action == eWLFC_MAC_ENTRY_ACTION_ADD) {
++			dhd_pub_t *dhdp = (dhd_pub_t *)(ctx->dhdp);
++
++			pktq_init(&entry->psq, WLFC_PSQ_PREC_COUNT, WLFC_PSQ_LEN);
++
++			if (WLFC_GET_AFQ(dhdp->wlfc_mode)) {
++				pktq_init(&entry->afq, WLFC_AFQ_PREC_COUNT, WLFC_PSQ_LEN);
++			}
++
++			if (entry->next == NULL) {
++				/* not linked to anywhere, add to tail */
++				if (ctx->active_entry_head) {
++					entry->prev = ctx->active_entry_head->prev;
++					ctx->active_entry_head->prev->next = entry;
++					ctx->active_entry_head->prev = entry;
++					entry->next = ctx->active_entry_head;
++				} else {
++					ASSERT(ctx->active_entry_count == 0);
++					entry->prev = entry->next = entry;
++					ctx->active_entry_head = entry;
++				}
++				ctx->active_entry_count++;
++			} else {
++				DHD_ERROR(("%s():%d, entry(%d)\n", __FUNCTION__, __LINE__,
++					(int)(entry - &ctx->destination_entries.nodes[0])));
++			}
++		}
++	} else if (action == eWLFC_MAC_ENTRY_ACTION_DEL) {
++		/* When the entry is deleted, the packets that are queued in the entry must be
++		   cleanup. The cleanup action should be before the occupied is set as 0.
++		*/
++		_dhd_wlfc_cleanup(ctx->dhdp, fn, arg);
++		_dhd_wlfc_flow_control_check(ctx, &entry->psq, ifid);
++
++		entry->occupied = 0;
++		entry->state = WLFC_STATE_CLOSE;
++		memset(&entry->ea[0], 0, ETHER_ADDR_LEN);
++
++		if (entry->next) {
++			/* not floating, remove from Q */
++			if (ctx->active_entry_count <= 1) {
++				/* last item */
++				ctx->active_entry_head = NULL;
++				ctx->active_entry_count = 0;
++			} else {
++				entry->prev->next = entry->next;
++				entry->next->prev = entry->prev;
++				if (entry == ctx->active_entry_head) {
++					ctx->active_entry_head = entry->next;
++				}
++				ctx->active_entry_count--;
++			}
++			entry->next = entry->prev = NULL;
++		} else {
++			DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		}
++	}
++	return rc;
++} /* _dhd_wlfc_mac_entry_update */
++
++
++#ifdef LIMIT_BORROW
++
++/** LIMIT_BORROW specific function */
++static int
++_dhd_wlfc_borrow_credit(athost_wl_status_info_t* ctx, int highest_lender_ac, int borrower_ac,
++	bool bBorrowAll)
++{
++	int lender_ac, borrow_limit = 0;
++	int rc = -1;
++
++	if (ctx == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return -1;
++	}
++
++	/* Borrow from lowest priority available AC (including BC/MC credits) */
++	for (lender_ac = 0; lender_ac <= highest_lender_ac; lender_ac++) {
++		if (!bBorrowAll) {
++			borrow_limit = ctx->Init_FIFO_credit[lender_ac]/WLFC_BORROW_LIMIT_RATIO;
++		} else {
++			borrow_limit = 0;
++		}
++
++		if (ctx->FIFO_credit[lender_ac] > borrow_limit) {
++			ctx->credits_borrowed[borrower_ac][lender_ac]++;
++			ctx->FIFO_credit[lender_ac]--;
++			rc = lender_ac;
++			break;
++		}
++	}
++
++	return rc;
++}
++
++/** LIMIT_BORROW specific function */
++static int _dhd_wlfc_return_credit(athost_wl_status_info_t* ctx, int lender_ac, int borrower_ac)
++{
++	if ((ctx == NULL) || (lender_ac < 0) || (lender_ac > AC_COUNT) ||
++		(borrower_ac < 0) || (borrower_ac > AC_COUNT)) {
++		DHD_ERROR(("Error: %s():%d, ctx(%p), lender_ac(%d), borrower_ac(%d)\n",
++			__FUNCTION__, __LINE__, ctx, lender_ac, borrower_ac));
++
++		return BCME_BADARG;
++	}
++
++	ctx->credits_borrowed[borrower_ac][lender_ac]--;
++	ctx->FIFO_credit[lender_ac]++;
++
++	return BCME_OK;
++}
++
++#endif /* LIMIT_BORROW */
++
++/**
++ * Called on an interface event (WLC_E_IF) indicated by firmware.
++ *     @param action : eg eWLFC_MAC_ENTRY_ACTION_UPDATE or eWLFC_MAC_ENTRY_ACTION_ADD
++ */
++static int
++_dhd_wlfc_interface_entry_update(void* state,
++	uint8 action, uint8 ifid, uint8 iftype, uint8* ea)
++{
++	athost_wl_status_info_t* ctx = (athost_wl_status_info_t*)state;
++	wlfc_mac_descriptor_t* entry;
++
++	if (ifid >= WLFC_MAX_IFNUM)
++		return BCME_BADARG;
++
++	entry = &ctx->destination_entries.interfaces[ifid];
++
++	return _dhd_wlfc_mac_entry_update(ctx, entry, action, ifid, iftype, ea,
++		_dhd_wlfc_ifpkt_fn, &ifid);
++}
++
++/**
++ * Called eg on receiving a WLC_E_BCMC_CREDIT_SUPPORT event from the dongle (broadcast/multicast
++ * specific)
++ */
++static int
++_dhd_wlfc_BCMCCredit_support_update(void* state)
++{
++	athost_wl_status_info_t* ctx = (athost_wl_status_info_t*)state;
++
++	ctx->bcmc_credit_supported = TRUE;
++	return BCME_OK;
++}
++
++/** Called eg on receiving a WLC_E_FIFO_CREDIT_MAP event from the dongle */
++static int
++_dhd_wlfc_FIFOcreditmap_update(void* state, uint8* credits)
++{
++	athost_wl_status_info_t* ctx = (athost_wl_status_info_t*)state;
++	int i;
++
++	for (i = 0; i <= 4; i++) {
++		if (ctx->Init_FIFO_credit[i] != ctx->FIFO_credit[i]) {
++			DHD_ERROR(("%s: credit[i] is not returned, (%d %d)\n",
++				__FUNCTION__, ctx->Init_FIFO_credit[i], ctx->FIFO_credit[i]));
++		}
++	}
++
++	/* update the AC FIFO credit map */
++	ctx->FIFO_credit[0] += (credits[0] - ctx->Init_FIFO_credit[0]);
++	ctx->FIFO_credit[1] += (credits[1] - ctx->Init_FIFO_credit[1]);
++	ctx->FIFO_credit[2] += (credits[2] - ctx->Init_FIFO_credit[2]);
++	ctx->FIFO_credit[3] += (credits[3] - ctx->Init_FIFO_credit[3]);
++	ctx->FIFO_credit[4] += (credits[4] - ctx->Init_FIFO_credit[4]);
++
++	ctx->Init_FIFO_credit[0] = credits[0];
++	ctx->Init_FIFO_credit[1] = credits[1];
++	ctx->Init_FIFO_credit[2] = credits[2];
++	ctx->Init_FIFO_credit[3] = credits[3];
++	ctx->Init_FIFO_credit[4] = credits[4];
++
++	/* credit for ATIM FIFO is not used yet. */
++	ctx->Init_FIFO_credit[5] = ctx->FIFO_credit[5] = 0;
++
++	return BCME_OK;
++}
++
++/**
++ * Called during committing of a transmit packet from the OS DHD layer to the next layer towards
++ * the dongle (eg the DBUS layer). All transmit packets flow via this function to the next layer.
++ *
++ *     @param[in/out] ctx      Driver specific flow control administration
++ *     @param[in] ac           Access Category (QoS) of called supplied packet
++ *     @param[in] commit_info  Contains eg the packet to send
++ *     @param[in] fcommit      Function pointer to transmit function of next software layer
++ *     @param[in] commit_ctx   Opaque context used when calling next layer
++ */
++static int
++_dhd_wlfc_handle_packet_commit(athost_wl_status_info_t* ctx, int ac,
++    dhd_wlfc_commit_info_t *commit_info, f_commitpkt_t fcommit, void* commit_ctx)
++{
++	uint32 hslot;
++	int	rc;
++	dhd_pub_t *dhdp = (dhd_pub_t *)(ctx->dhdp);
++
++	/*
++		if ac_fifo_credit_spent = 0
++
++		This packet will not count against the FIFO credit.
++		To ensure the txstatus corresponding to this packet
++		does not provide an implied credit (default behavior)
++		mark the packet accordingly.
++
++		if ac_fifo_credit_spent = 1
++
++		This is a normal packet and it counts against the FIFO
++		credit count.
++	*/
++	DHD_PKTTAG_SETCREDITCHECK(PKTTAG(commit_info->p), commit_info->ac_fifo_credit_spent);
++	rc = _dhd_wlfc_pretx_pktprocess(ctx, commit_info->mac_entry, &commit_info->p,
++	     commit_info->needs_hdr, &hslot);
++
++	if (rc == BCME_OK) {
++		rc = fcommit(commit_ctx, commit_info->p);
++		if (rc == BCME_OK) {
++			uint8 gen = WL_TXSTATUS_GET_GENERATION(
++				DHD_PKTTAG_H2DTAG(PKTTAG(commit_info->p)));
++			ctx->stats.pkt2bus++;
++			if (commit_info->ac_fifo_credit_spent || (ac == AC_COUNT)) {
++				ctx->stats.send_pkts[ac]++;
++				WLFC_HOST_FIFO_CREDIT_INC_SENTCTRS(ctx, ac);
++			}
++
++			if (gen != commit_info->mac_entry->generation) {
++				/* will be suppressed back by design */
++				if (!commit_info->mac_entry->suppressed) {
++					commit_info->mac_entry->suppressed = TRUE;
++				}
++				commit_info->mac_entry->suppr_transit_count++;
++			}
++			commit_info->mac_entry->transit_count++;
++			commit_info->mac_entry->onbus_pkts_count++;
++		} else if (commit_info->needs_hdr) {
++			if (!WLFC_GET_AFQ(dhdp->wlfc_mode)) {
++				void *pout = NULL;
++				/* pop hanger for delayed packet */
++				_dhd_wlfc_hanger_poppkt(ctx->hanger, WL_TXSTATUS_GET_HSLOT(
++					DHD_PKTTAG_H2DTAG(PKTTAG(commit_info->p))), &pout, TRUE);
++				ASSERT(commit_info->p == pout);
++			}
++		}
++	} else {
++		ctx->stats.generic_error++;
++	}
++
++	if (rc != BCME_OK) {
++		/*
++		   pretx pkt process or bus commit has failed, rollback.
++		   - remove wl-header for a delayed packet
++		   - save wl-header header for suppressed packets
++		   - reset credit check flag
++		*/
++		_dhd_wlfc_rollback_packet_toq(ctx, commit_info->p, commit_info->pkt_type, hslot);
++		DHD_PKTTAG_SETCREDITCHECK(PKTTAG(commit_info->p), 0);
++	}
++
++	return rc;
++} /* _dhd_wlfc_handle_packet_commit */
++
++/** Returns remote MAC descriptor for caller supplied MAC address */
++static uint8
++_dhd_wlfc_find_mac_desc_id_from_mac(dhd_pub_t *dhdp, uint8 *ea)
++{
++	wlfc_mac_descriptor_t* table =
++		((athost_wl_status_info_t*)dhdp->wlfc_state)->destination_entries.nodes;
++	uint8 table_index;
++
++	if (ea != NULL) {
++		for (table_index = 0; table_index < WLFC_MAC_DESC_TABLE_SIZE; table_index++) {
++			if ((memcmp(ea, &table[table_index].ea[0], ETHER_ADDR_LEN) == 0) &&
++				table[table_index].occupied)
++				return table_index;
++		}
++	}
++	return WLFC_MAC_DESC_ID_INVALID;
++}
++
++/**
++ * Called when the host receives a WLFC_CTL_TYPE_TXSTATUS event from the dongle, indicating the
++ * status of a frame that the dongle attempted to transmit over the wireless medium.
++ */
++static int
++dhd_wlfc_suppressed_acked_update(dhd_pub_t *dhd, uint16 hslot, uint8 prec, uint8 hcnt)
++{
++	athost_wl_status_info_t* ctx;
++	wlfc_mac_descriptor_t* entry = NULL;
++	struct pktq *pq;
++	struct pktq_prec *q;
++	void *p, *b;
++
++	if (!dhd) {
++		DHD_ERROR(("%s: dhd(%p)\n", __FUNCTION__, dhd));
++		return BCME_BADARG;
++	}
++	ctx = (athost_wl_status_info_t*)dhd->wlfc_state;
++	if (!ctx) {
++		DHD_ERROR(("%s: ctx(%p)\n", __FUNCTION__, ctx));
++		return BCME_ERROR;
++	}
++
++	ASSERT(hslot < (WLFC_MAC_DESC_TABLE_SIZE + WLFC_MAX_IFNUM + 1));
++
++	if (hslot < WLFC_MAC_DESC_TABLE_SIZE)
++		entry  = &ctx->destination_entries.nodes[hslot];
++	else if (hslot < (WLFC_MAC_DESC_TABLE_SIZE + WLFC_MAX_IFNUM))
++		entry = &ctx->destination_entries.interfaces[hslot - WLFC_MAC_DESC_TABLE_SIZE];
++	else
++		entry = &ctx->destination_entries.other;
++
++	pq = &entry->psq;
++
++	ASSERT(((prec << 1) + 1) < pq->num_prec);
++
++	q = &pq->q[((prec << 1) + 1)];
++
++	b = NULL;
++	p = q->head;
++
++	while (p && (hcnt != WL_TXSTATUS_GET_FREERUNCTR(DHD_PKTTAG_H2DTAG(PKTTAG(p))))) {
++		b = p;
++		p = PKTLINK(p);
++	}
++
++	if (p == NULL) {
++		/* none is matched */
++		if (b) {
++			DHD_ERROR(("%s: can't find matching seq(%d)\n", __FUNCTION__, hcnt));
++		} else {
++			DHD_ERROR(("%s: queue is empty\n", __FUNCTION__));
++		}
++
++		return BCME_ERROR;
++	}
++
++	if (!b) {
++		/* head packet is matched */
++		if ((q->head = PKTLINK(p)) == NULL) {
++			q->tail = NULL;
++		}
++	} else {
++		/* middle packet is matched */
++		PKTSETLINK(b, PKTLINK(p));
++		if (PKTLINK(p) == NULL) {
++			q->tail = b;
++		}
++	}
++
++	q->len--;
++	pq->len--;
++	ctx->pkt_cnt_in_q[DHD_PKTTAG_IF(PKTTAG(p))][prec]--;
++	ctx->pkt_cnt_per_ac[prec]--;
++
++	PKTSETLINK(p, NULL);
++
++	if (WLFC_GET_AFQ(dhd->wlfc_mode)) {
++		_dhd_wlfc_enque_afq(ctx, p);
++	} else {
++		_dhd_wlfc_hanger_pushpkt(ctx->hanger, p, hslot);
++	}
++
++	entry->transit_count++;
++
++	return BCME_OK;
++}
++
++static int
++_dhd_wlfc_compressed_txstatus_update(dhd_pub_t *dhd, uint8* pkt_info, uint8 len, void** p_mac)
++{
++	uint8 status_flag_ori, status_flag;
++	uint32 status;
++	int ret = BCME_OK;
++	int remove_from_hanger_ori, remove_from_hanger = 1;
++	void* pktbuf = NULL;
++	uint8 fifo_id = 0, gen = 0, count = 0, hcnt;
++	uint16 hslot;
++	wlfc_mac_descriptor_t* entry = NULL;
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	uint16 seq = 0, seq_fromfw = 0, seq_num = 0;
++
++	memcpy(&status, pkt_info, sizeof(uint32));
++	status = ltoh32(status);
++	status_flag = WL_TXSTATUS_GET_FLAGS(status);
++	hcnt = WL_TXSTATUS_GET_FREERUNCTR(status);
++	hslot = WL_TXSTATUS_GET_HSLOT(status);
++	fifo_id = WL_TXSTATUS_GET_FIFO(status);
++	gen = WL_TXSTATUS_GET_GENERATION(status);
++
++	if (WLFC_GET_REUSESEQ(dhd->wlfc_mode)) {
++		memcpy(&seq, pkt_info + WLFC_CTL_VALUE_LEN_TXSTATUS, WLFC_CTL_VALUE_LEN_SEQ);
++		seq = ltoh16(seq);
++		seq_fromfw = WL_SEQ_GET_FROMFW(seq);
++		seq_num = WL_SEQ_GET_NUM(seq);
++	}
++
++	wlfc->stats.txstatus_in += len;
++
++	if (status_flag == WLFC_CTL_PKTFLAG_DISCARD) {
++		wlfc->stats.pkt_freed += len;
++	} else if (status_flag == WLFC_CTL_PKTFLAG_DISCARD_NOACK) {
++		wlfc->stats.pkt_freed += len;
++	} else if (status_flag == WLFC_CTL_PKTFLAG_D11SUPPRESS) {
++		wlfc->stats.d11_suppress += len;
++		remove_from_hanger = 0;
++	} else if (status_flag == WLFC_CTL_PKTFLAG_WLSUPPRESS) {
++		wlfc->stats.wl_suppress += len;
++		remove_from_hanger = 0;
++	} else if (status_flag == WLFC_CTL_PKTFLAG_TOSSED_BYWLC) {
++		wlfc->stats.wlc_tossed_pkts += len;
++	}
++
++	else if (status_flag == WLFC_CTL_PKTFLAG_SUPPRESS_ACKED) {
++		wlfc->stats.pkt_freed += len;
++	}
++
++	if (dhd->proptxstatus_txstatus_ignore) {
++		if (!remove_from_hanger) {
++			DHD_ERROR(("suppress txstatus: %d\n", status_flag));
++		}
++		return BCME_OK;
++	}
++
++	status_flag_ori = status_flag;
++	remove_from_hanger_ori = remove_from_hanger;
++
++	while (count < len) {
++		if (status_flag == WLFC_CTL_PKTFLAG_SUPPRESS_ACKED) {
++			dhd_wlfc_suppressed_acked_update(dhd, hslot, fifo_id, hcnt);
++		}
++		if (WLFC_GET_AFQ(dhd->wlfc_mode)) {
++			ret = _dhd_wlfc_deque_afq(wlfc, hslot, hcnt, fifo_id, &pktbuf);
++		} else {
++			status_flag = status_flag_ori;
++			remove_from_hanger = remove_from_hanger_ori;
++			ret = _dhd_wlfc_hanger_poppkt(wlfc->hanger, hslot, &pktbuf, FALSE);
++			if (!pktbuf) {
++				_dhd_wlfc_hanger_free_pkt(wlfc, hslot,
++					WLFC_HANGER_PKT_STATE_TXSTATUS, -1);
++				goto cont;
++			} else {
++				wlfc_hanger_t* h = (wlfc_hanger_t*)wlfc->hanger;
++				if (h->items[hslot].state == WLFC_HANGER_ITEM_STATE_FLUSHED) {
++					status_flag = WLFC_CTL_PKTFLAG_DISCARD;
++					remove_from_hanger = 1;
++				}
++			}
++		}
++
++		if ((ret != BCME_OK) || !pktbuf) {
++			goto cont;
++		}
++
++		bcm_pkt_validate_chk(pktbuf);
++
++		/* set fifo_id to correct value because not all FW does that */
++		fifo_id = DHD_PKTTAG_FIFO(PKTTAG(pktbuf));
++
++		entry = _dhd_wlfc_find_table_entry(wlfc, pktbuf);
++
++		if (!remove_from_hanger) {
++			/* this packet was suppressed */
++			if (!entry->suppressed || (entry->generation != gen)) {
++				if (!entry->suppressed) {
++					entry->suppr_transit_count = entry->transit_count;
++					if (p_mac) {
++						*p_mac = entry;
++					}
++				} else {
++					DHD_ERROR(("gen(%d), entry->generation(%d)\n",
++						gen, entry->generation));
++				}
++				entry->suppressed = TRUE;
++
++			}
++			entry->generation = gen;
++		}
++
++#ifdef PROP_TXSTATUS_DEBUG
++		if (!WLFC_GET_AFQ(dhd->wlfc_mode))
++		{
++			uint32 new_t = OSL_SYSUPTIME();
++			uint32 old_t;
++			uint32 delta;
++			old_t = ((wlfc_hanger_t*)(wlfc->hanger))->items[hslot].push_time;
++
++
++			wlfc->stats.latency_sample_count++;
++			if (new_t > old_t)
++				delta = new_t - old_t;
++			else
++				delta = 0xffffffff + new_t - old_t;
++			wlfc->stats.total_status_latency += delta;
++			wlfc->stats.latency_most_recent = delta;
++
++			wlfc->stats.deltas[wlfc->stats.idx_delta++] = delta;
++			if (wlfc->stats.idx_delta == sizeof(wlfc->stats.deltas)/sizeof(uint32))
++				wlfc->stats.idx_delta = 0;
++		}
++#endif /* PROP_TXSTATUS_DEBUG */
++
++		/* pick up the implicit credit from this packet */
++		if (DHD_PKTTAG_CREDITCHECK(PKTTAG(pktbuf))) {
++			_dhd_wlfc_return_implied_credit(wlfc, pktbuf);
++		} else {
++			/*
++			if this packet did not count against FIFO credit, it must have
++			taken a requested_credit from the destination entry (for pspoll etc.)
++			*/
++			if (!DHD_PKTTAG_ONETIMEPKTRQST(PKTTAG(pktbuf))) {
++				entry->requested_credit++;
++#if defined(DHD_WLFC_THREAD)
++				_dhd_wlfc_thread_wakeup(dhd);
++#endif /* DHD_WLFC_THREAD */
++			}
++#ifdef PROP_TXSTATUS_DEBUG
++			entry->dstncredit_acks++;
++#endif
++		}
++
++		if ((status_flag == WLFC_CTL_PKTFLAG_D11SUPPRESS) ||
++			(status_flag == WLFC_CTL_PKTFLAG_WLSUPPRESS)) {
++			/* save generation bit inside packet */
++			WL_TXSTATUS_SET_GENERATION(DHD_PKTTAG_H2DTAG(PKTTAG(pktbuf)), gen);
++
++			if (WLFC_GET_REUSESEQ(dhd->wlfc_mode)) {
++				WL_SEQ_SET_FROMDRV(DHD_PKTTAG_H2DSEQ(PKTTAG(pktbuf)), seq_fromfw);
++				WL_SEQ_SET_NUM(DHD_PKTTAG_H2DSEQ(PKTTAG(pktbuf)), seq_num);
++			}
++
++			ret = _dhd_wlfc_enque_suppressed(wlfc, fifo_id, pktbuf);
++			if (ret != BCME_OK) {
++				/* delay q is full, drop this packet */
++				DHD_WLFC_QMON_COMPLETE(entry);
++				_dhd_wlfc_prec_drop(dhd, (fifo_id << 1) + 1, pktbuf, FALSE);
++			} else {
++				if (!WLFC_GET_AFQ(dhd->wlfc_mode)) {
++					/* Mark suppressed to avoid a double free
++					during wlfc cleanup
++					*/
++					_dhd_wlfc_hanger_mark_suppressed(wlfc->hanger, hslot, gen);
++				}
++			}
++		} else {
++
++			DHD_WLFC_QMON_COMPLETE(entry);
++
++			if (!WLFC_GET_AFQ(dhd->wlfc_mode)) {
++				_dhd_wlfc_hanger_free_pkt(wlfc, hslot,
++					WLFC_HANGER_PKT_STATE_TXSTATUS, TRUE);
++			} else {
++				dhd_txcomplete(dhd, pktbuf, TRUE);
++				wlfc->pkt_cnt_in_drv[DHD_PKTTAG_IF(PKTTAG(pktbuf))]
++					[DHD_PKTTAG_FIFO(PKTTAG(pktbuf))]--;
++				wlfc->stats.pktout++;
++				/* free the packet */
++				PKTFREE(wlfc->osh, pktbuf, TRUE);
++			}
++		}
++		/* pkt back from firmware side */
++		if (entry->transit_count)
++			entry->transit_count--;
++		if (entry->suppr_transit_count) {
++			entry->suppr_transit_count--;
++			if (entry->suppressed &&
++				(!entry->onbus_pkts_count) &&
++				(!entry->suppr_transit_count))
++				entry->suppressed = FALSE;
++		}
++
++cont:
++		hcnt = (hcnt + 1) & WL_TXSTATUS_FREERUNCTR_MASK;
++		if (!WLFC_GET_AFQ(dhd->wlfc_mode)) {
++			hslot = (hslot + 1) & WL_TXSTATUS_HSLOT_MASK;
++		}
++
++		if (WLFC_GET_REUSESEQ(dhd->wlfc_mode) && seq_fromfw) {
++			seq_num = (seq_num + 1) & WL_SEQ_NUM_MASK;
++		}
++
++		count++;
++	}
++
++	return BCME_OK;
++} /* _dhd_wlfc_compressed_txstatus_update */
++
++/**
++ * Called when eg host receives a 'WLFC_CTL_TYPE_FIFO_CREDITBACK' event from the dongle.
++ *    @param[in] credits caller supplied credit that will be added to the host credit.
++ */
++static int
++_dhd_wlfc_fifocreditback_indicate(dhd_pub_t *dhd, uint8* credits)
++{
++	int i;
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	for (i = 0; i < WLFC_CTL_VALUE_LEN_FIFO_CREDITBACK; i++) {
++#ifdef PROP_TXSTATUS_DEBUG
++		wlfc->stats.fifo_credits_back[i] += credits[i];
++#endif
++
++		/* update FIFO credits */
++		if (dhd->proptxstatus_mode == WLFC_FCMODE_EXPLICIT_CREDIT)
++		{
++			int lender; /* Note that borrower is i */
++
++			/* Return credits to highest priority lender first */
++			for (lender = AC_COUNT; (lender >= 0) && (credits[i] > 0); lender--) {
++				if (wlfc->credits_borrowed[i][lender] > 0) {
++					if (credits[i] >= wlfc->credits_borrowed[i][lender]) {
++						credits[i] -=
++							(uint8)wlfc->credits_borrowed[i][lender];
++						wlfc->FIFO_credit[lender] +=
++						    wlfc->credits_borrowed[i][lender];
++						wlfc->credits_borrowed[i][lender] = 0;
++					} else {
++						wlfc->credits_borrowed[i][lender] -= credits[i];
++						wlfc->FIFO_credit[lender] += credits[i];
++						credits[i] = 0;
++					}
++				}
++			}
++
++			/* If we have more credits left over, these must belong to the AC */
++			if (credits[i] > 0) {
++				wlfc->FIFO_credit[i] += credits[i];
++			}
++
++			if (wlfc->FIFO_credit[i] > wlfc->Init_FIFO_credit[i]) {
++				wlfc->FIFO_credit[i] = wlfc->Init_FIFO_credit[i];
++			}
++		}
++	}
++
++#if defined(DHD_WLFC_THREAD)
++	_dhd_wlfc_thread_wakeup(dhd);
++#endif /* defined(DHD_WLFC_THREAD) */
++
++	return BCME_OK;
++} /* _dhd_wlfc_fifocreditback_indicate */
++
++#ifndef BCMDBUS
++
++/** !BCMDBUS specific function */
++static void
++_dhd_wlfc_suppress_txq(dhd_pub_t *dhd, f_processpkt_t fn, void *arg)
++{
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	wlfc_mac_descriptor_t* entry;
++	int prec;
++	void *pkt = NULL, *head = NULL, *tail = NULL;
++	struct pktq *txq = (struct pktq *)dhd_bus_txq(dhd->bus);
++	uint8	results[WLFC_CTL_VALUE_LEN_TXSTATUS+WLFC_CTL_VALUE_LEN_SEQ];
++	uint8 credits[WLFC_CTL_VALUE_LEN_FIFO_CREDITBACK] = {0};
++	uint32 htod = 0;
++	uint16 htodseq = 0;
++	bool bCreditUpdate = FALSE;
++
++	dhd_os_sdlock_txq(dhd);
++	for (prec = 0; prec < txq->num_prec; prec++) {
++		while ((pkt = _dhd_wlfc_pktq_pdeq_with_fn(txq, prec, fn, arg))) {
++			if (!head) {
++				head = pkt;
++			}
++			if (tail) {
++				PKTSETLINK(tail, pkt);
++			}
++			tail = pkt;
++		}
++	}
++	dhd_os_sdunlock_txq(dhd);
++
++	while ((pkt = head)) {
++		head = PKTLINK(pkt);
++		PKTSETLINK(pkt, NULL);
++
++		entry = _dhd_wlfc_find_table_entry(wlfc, pkt);
++		if (entry) {
++			if (entry->onbus_pkts_count > 0)
++				entry->onbus_pkts_count--;
++			if (entry->suppressed &&
++				(!entry->onbus_pkts_count) &&
++				(!entry->suppr_transit_count))
++				entry->suppressed = FALSE;
++		}
++
++		/* fake a suppression txstatus */
++		htod = DHD_PKTTAG_H2DTAG(PKTTAG(pkt));
++		WL_TXSTATUS_SET_FLAGS(htod, WLFC_CTL_PKTFLAG_WLSUPPRESS);
++		WL_TXSTATUS_SET_GENERATION(htod, entry->generation);
++		htod = htol32(htod);
++		memcpy(results, &htod, WLFC_CTL_VALUE_LEN_TXSTATUS);
++		if (WLFC_GET_REUSESEQ(dhd->wlfc_mode)) {
++			htodseq = DHD_PKTTAG_H2DSEQ(PKTTAG(pkt));
++			if (WL_SEQ_GET_FROMDRV(htodseq)) {
++				WL_SEQ_SET_FROMFW(htodseq, 1);
++				WL_SEQ_SET_FROMDRV(htodseq, 0);
++			}
++			htodseq = htol16(htodseq);
++			memcpy(results + WLFC_CTL_VALUE_LEN_TXSTATUS, &htodseq,
++				WLFC_CTL_VALUE_LEN_SEQ);
++		}
++		if (WLFC_GET_AFQ(dhd->wlfc_mode)) {
++			_dhd_wlfc_enque_afq(wlfc, pkt);
++		}
++		_dhd_wlfc_compressed_txstatus_update(dhd, results, 1, NULL);
++
++		/* fake a fifo credit back */
++		if (DHD_PKTTAG_CREDITCHECK(PKTTAG(pkt))) {
++			credits[DHD_PKTTAG_FIFO(PKTTAG(pkt))]++;
++			bCreditUpdate = TRUE;
++		}
++	}
++
++	if (bCreditUpdate) {
++		_dhd_wlfc_fifocreditback_indicate(dhd, credits);
++	}
++} /* _dhd_wlfc_suppress_txq */
++
++#endif /* !BCMDBUS */
++
++static int
++_dhd_wlfc_dbg_senum_check(dhd_pub_t *dhd, uint8 *value)
++{
++	uint32 timestamp;
++
++	(void)dhd;
++
++	bcopy(&value[2], &timestamp, sizeof(uint32));
++	timestamp = ltoh32(timestamp);
++	DHD_INFO(("RXPKT: SEQ: %d, timestamp %d\n", value[1], timestamp));
++	return BCME_OK;
++}
++
++static int
++_dhd_wlfc_rssi_indicate(dhd_pub_t *dhd, uint8* rssi)
++{
++	(void)dhd;
++	(void)rssi;
++	return BCME_OK;
++}
++
++static void
++_dhd_wlfc_add_requested_entry(athost_wl_status_info_t* wlfc, wlfc_mac_descriptor_t* entry)
++{
++	int i;
++
++	if (!wlfc || !entry) {
++		return;
++	}
++
++	for (i = 0; i < wlfc->requested_entry_count; i++) {
++		if (entry == wlfc->requested_entry[i]) {
++			break;
++		}
++	}
++
++	if (i == wlfc->requested_entry_count) {
++		/* no match entry found */
++		ASSERT(wlfc->requested_entry_count <= (WLFC_MAC_DESC_TABLE_SIZE-1));
++		wlfc->requested_entry[wlfc->requested_entry_count++] = entry;
++	}
++}
++
++/** called on eg receiving 'mac open' event from the dongle. */
++static void
++_dhd_wlfc_remove_requested_entry(athost_wl_status_info_t* wlfc, wlfc_mac_descriptor_t* entry)
++{
++	int i;
++
++	if (!wlfc || !entry) {
++		return;
++	}
++
++	for (i = 0; i < wlfc->requested_entry_count; i++) {
++		if (entry == wlfc->requested_entry[i]) {
++			break;
++		}
++	}
++
++	if (i < wlfc->requested_entry_count) {
++		/* found */
++		ASSERT(wlfc->requested_entry_count > 0);
++		wlfc->requested_entry_count--;
++		if (i != wlfc->requested_entry_count) {
++			wlfc->requested_entry[i] =
++				wlfc->requested_entry[wlfc->requested_entry_count];
++		}
++		wlfc->requested_entry[wlfc->requested_entry_count] = NULL;
++	}
++}
++
++/** called on eg receiving a WLFC_CTL_TYPE_MACDESC_ADD TLV from the dongle */
++static int
++_dhd_wlfc_mac_table_update(dhd_pub_t *dhd, uint8* value, uint8 type)
++{
++	int rc;
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	wlfc_mac_descriptor_t* table;
++	uint8 existing_index;
++	uint8 table_index;
++	uint8 ifid;
++	uint8* ea;
++
++	WLFC_DBGMESG(("%s(), mac [%02x:%02x:%02x:%02x:%02x:%02x],%s,idx:%d,id:0x%02x\n",
++		__FUNCTION__, value[2], value[3], value[4], value[5], value[6], value[7],
++		((type == WLFC_CTL_TYPE_MACDESC_ADD) ? "ADD":"DEL"),
++		WLFC_MAC_DESC_GET_LOOKUP_INDEX(value[0]), value[0]));
++
++	table = wlfc->destination_entries.nodes;
++	table_index = WLFC_MAC_DESC_GET_LOOKUP_INDEX(value[0]);
++	ifid = value[1];
++	ea = &value[2];
++
++	_dhd_wlfc_remove_requested_entry(wlfc, &table[table_index]);
++	if (type == WLFC_CTL_TYPE_MACDESC_ADD) {
++		existing_index = _dhd_wlfc_find_mac_desc_id_from_mac(dhd, &value[2]);
++		if ((existing_index != WLFC_MAC_DESC_ID_INVALID) &&
++			(existing_index != table_index) && table[existing_index].occupied) {
++			/*
++			there is an existing different entry, free the old one
++			and move it to new index if necessary.
++			*/
++			rc = _dhd_wlfc_mac_entry_update(wlfc, &table[existing_index],
++				eWLFC_MAC_ENTRY_ACTION_DEL, table[existing_index].interface_id,
++				table[existing_index].iftype, NULL, _dhd_wlfc_entrypkt_fn,
++				&table[existing_index]);
++		}
++
++		if (!table[table_index].occupied) {
++			/* this new MAC entry does not exist, create one */
++			table[table_index].mac_handle = value[0];
++			rc = _dhd_wlfc_mac_entry_update(wlfc, &table[table_index],
++				eWLFC_MAC_ENTRY_ACTION_ADD, ifid,
++				wlfc->destination_entries.interfaces[ifid].iftype,
++				ea, NULL, NULL);
++		} else {
++			/* the space should have been empty, but it's not */
++			wlfc->stats.mac_update_failed++;
++		}
++	}
++
++	if (type == WLFC_CTL_TYPE_MACDESC_DEL) {
++		if (table[table_index].occupied) {
++				rc = _dhd_wlfc_mac_entry_update(wlfc, &table[table_index],
++					eWLFC_MAC_ENTRY_ACTION_DEL, ifid,
++					wlfc->destination_entries.interfaces[ifid].iftype,
++					ea, _dhd_wlfc_entrypkt_fn, &table[table_index]);
++		} else {
++			/* the space should have been occupied, but it's not */
++			wlfc->stats.mac_update_failed++;
++		}
++	}
++	BCM_REFERENCE(rc);
++	return BCME_OK;
++} /* _dhd_wlfc_mac_table_update */
++
++/** Called on a 'mac open' or 'mac close' event indicated by the dongle */
++static int
++_dhd_wlfc_psmode_update(dhd_pub_t *dhd, uint8* value, uint8 type)
++{
++	/* Handle PS on/off indication */
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	wlfc_mac_descriptor_t* table;
++	wlfc_mac_descriptor_t* desc; /* a table maps from mac handle to mac descriptor */
++	uint8 mac_handle = value[0];
++	int i;
++
++	table = wlfc->destination_entries.nodes;
++	desc = &table[WLFC_MAC_DESC_GET_LOOKUP_INDEX(mac_handle)];
++	if (desc->occupied) {
++		if (type == WLFC_CTL_TYPE_MAC_OPEN) {
++			desc->state = WLFC_STATE_OPEN;
++			desc->ac_bitmap = 0xff;
++			DHD_WLFC_CTRINC_MAC_OPEN(desc);
++			desc->requested_credit = 0;
++			desc->requested_packet = 0;
++			_dhd_wlfc_remove_requested_entry(wlfc, desc);
++		} else {
++			desc->state = WLFC_STATE_CLOSE;
++			DHD_WLFC_CTRINC_MAC_CLOSE(desc);
++			/* Indicate to firmware if there is any traffic pending. */
++			for (i = 0; i < AC_COUNT; i++) {
++				_dhd_wlfc_traffic_pending_check(wlfc, desc, i);
++			}
++		}
++	} else {
++		wlfc->stats.psmode_update_failed++;
++	}
++
++	return BCME_OK;
++} /* _dhd_wlfc_psmode_update */
++
++/** called upon receiving 'interface open' or 'interface close' event from the dongle */
++static int
++_dhd_wlfc_interface_update(dhd_pub_t *dhd, uint8* value, uint8 type)
++{
++	/* Handle PS on/off indication */
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	wlfc_mac_descriptor_t* table;
++	uint8 if_id = value[0];
++
++	if (if_id < WLFC_MAX_IFNUM) {
++		table = wlfc->destination_entries.interfaces;
++		if (table[if_id].occupied) {
++			if (type == WLFC_CTL_TYPE_INTERFACE_OPEN) {
++				table[if_id].state = WLFC_STATE_OPEN;
++				/* WLFC_DBGMESG(("INTERFACE[%d] OPEN\n", if_id)); */
++			} else {
++				table[if_id].state = WLFC_STATE_CLOSE;
++				/* WLFC_DBGMESG(("INTERFACE[%d] CLOSE\n", if_id)); */
++			}
++			return BCME_OK;
++		}
++	}
++	wlfc->stats.interface_update_failed++;
++
++	return BCME_OK;
++}
++
++/** Called on receiving a WLFC_CTL_TYPE_MAC_REQUEST_CREDIT TLV from the dongle */
++static int
++_dhd_wlfc_credit_request(dhd_pub_t *dhd, uint8* value)
++{
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	wlfc_mac_descriptor_t* table;
++	wlfc_mac_descriptor_t* desc;
++	uint8 mac_handle;
++	uint8 credit;
++
++	table = wlfc->destination_entries.nodes;
++	mac_handle = value[1];
++	credit = value[0];
++
++	desc = &table[WLFC_MAC_DESC_GET_LOOKUP_INDEX(mac_handle)];
++	if (desc->occupied) {
++		desc->requested_credit = credit;
++
++		desc->ac_bitmap = value[2] & (~(1<<AC_COUNT));
++		_dhd_wlfc_add_requested_entry(wlfc, desc);
++#if defined(DHD_WLFC_THREAD)
++		if (credit) {
++			_dhd_wlfc_thread_wakeup(dhd);
++		}
++#endif /* DHD_WLFC_THREAD */
++	} else {
++		wlfc->stats.credit_request_failed++;
++	}
++
++	return BCME_OK;
++}
++
++/** Called on receiving a WLFC_CTL_TYPE_MAC_REQUEST_PACKET TLV from the dongle */
++static int
++_dhd_wlfc_packet_request(dhd_pub_t *dhd, uint8* value)
++{
++	athost_wl_status_info_t* wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	wlfc_mac_descriptor_t* table;
++	wlfc_mac_descriptor_t* desc;
++	uint8 mac_handle;
++	uint8 packet_count;
++
++	table = wlfc->destination_entries.nodes;
++	mac_handle = value[1];
++	packet_count = value[0];
++
++	desc = &table[WLFC_MAC_DESC_GET_LOOKUP_INDEX(mac_handle)];
++	if (desc->occupied) {
++		desc->requested_packet = packet_count;
++
++		desc->ac_bitmap = value[2] & (~(1<<AC_COUNT));
++		_dhd_wlfc_add_requested_entry(wlfc, desc);
++#if defined(DHD_WLFC_THREAD)
++		if (packet_count) {
++			_dhd_wlfc_thread_wakeup(dhd);
++		}
++#endif /* DHD_WLFC_THREAD */
++	} else {
++		wlfc->stats.packet_request_failed++;
++	}
++
++	return BCME_OK;
++}
++
++/** Called when host receives a WLFC_CTL_TYPE_HOST_REORDER_RXPKTS TLV from the dongle */
++static void
++_dhd_wlfc_reorderinfo_indicate(uint8 *val, uint8 len, uchar *info_buf, uint *info_len)
++{
++	if (info_len) {
++		if (info_buf) {
++			bcopy(val, info_buf, len);
++			*info_len = len;
++		} else {
++			*info_len = 0;
++		}
++	}
++}
++
++/*
++ * public functions
++ */
++
++bool dhd_wlfc_is_supported(dhd_pub_t *dhd)
++{
++	bool rc = TRUE;
++
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return FALSE;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		rc =  FALSE;
++	}
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return rc;
++}
++
++int dhd_wlfc_enable(dhd_pub_t *dhd)
++{
++	int i, rc = BCME_OK;
++	athost_wl_status_info_t* wlfc;
++
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_enabled || dhd->wlfc_state) {
++		rc = BCME_OK;
++		goto exit;
++	}
++
++	/* allocate space to track txstatus propagated from firmware */
++	dhd->wlfc_state = DHD_OS_PREALLOC(dhd, DHD_PREALLOC_DHD_WLFC_INFO,
++		sizeof(athost_wl_status_info_t));
++	if (dhd->wlfc_state == NULL) {
++		rc = BCME_NOMEM;
++		goto exit;
++	}
++
++	/* initialize state space */
++	wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	memset(wlfc, 0, sizeof(athost_wl_status_info_t));
++
++	/* remember osh & dhdp */
++	wlfc->osh = dhd->osh;
++	wlfc->dhdp = dhd;
++
++	if (!WLFC_GET_AFQ(dhd->wlfc_mode)) {
++		wlfc->hanger = _dhd_wlfc_hanger_create(dhd, WLFC_HANGER_MAXITEMS);
++		if (wlfc->hanger == NULL) {
++			DHD_OS_PREFREE(dhd, dhd->wlfc_state,
++				sizeof(athost_wl_status_info_t));
++			dhd->wlfc_state = NULL;
++			rc = BCME_NOMEM;
++			goto exit;
++		}
++	}
++
++	dhd->proptxstatus_mode = WLFC_FCMODE_EXPLICIT_CREDIT;
++	/* default to check rx pkt */
++	dhd->wlfc_rxpkt_chk = TRUE;
++	if (dhd->op_mode & DHD_FLAG_IBSS_MODE) {
++		dhd->wlfc_rxpkt_chk = FALSE;
++	}
++
++	/* initialize all interfaces to accept traffic */
++	for (i = 0; i < WLFC_MAX_IFNUM; i++) {
++		wlfc->hostif_flow_state[i] = OFF;
++	}
++
++	_dhd_wlfc_mac_entry_update(wlfc, &wlfc->destination_entries.other,
++		eWLFC_MAC_ENTRY_ACTION_ADD, 0xff, 0, NULL, NULL, NULL);
++
++	wlfc->allow_credit_borrow = 0;
++	wlfc->single_ac = 0;
++	wlfc->single_ac_timestamp = 0;
++
++
++exit:
++	dhd_os_wlfc_unblock(dhd);
++
++	return rc;
++} /* dhd_wlfc_enable */
++
++#ifdef SUPPORT_P2P_GO_PS
++
++/**
++ * Called when the host platform enters a lower power mode, eg right before a system hibernate.
++ * SUPPORT_P2P_GO_PS specific function.
++ */
++int
++dhd_wlfc_suspend(dhd_pub_t *dhd)
++{
++	uint32 tlv = 0;
++
++	DHD_TRACE(("%s: masking wlfc events\n", __FUNCTION__));
++	if (!dhd->wlfc_enabled)
++		return -1;
++
++	if (!dhd_wl_ioctl_get_intiovar(dhd, "tlv", &tlv, WLC_GET_VAR, FALSE, 0))
++		return -1;
++	if ((tlv & (WLFC_FLAGS_RSSI_SIGNALS | WLFC_FLAGS_XONXOFF_SIGNALS)) == 0)
++		return 0;
++	tlv &= ~(WLFC_FLAGS_RSSI_SIGNALS | WLFC_FLAGS_XONXOFF_SIGNALS);
++	if (!dhd_wl_ioctl_set_intiovar(dhd, "tlv", tlv, WLC_SET_VAR, TRUE, 0))
++		return -1;
++
++	return 0;
++}
++
++/**
++ * Called when the host platform resumes from a power management operation, eg resume after a
++ * system hibernate. SUPPORT_P2P_GO_PS specific function.
++ */
++int
++dhd_wlfc_resume(dhd_pub_t *dhd)
++{
++	uint32 tlv = 0;
++
++	DHD_TRACE(("%s: unmasking wlfc events\n", __FUNCTION__));
++	if (!dhd->wlfc_enabled)
++		return -1;
++
++	if (!dhd_wl_ioctl_get_intiovar(dhd, "tlv", &tlv, WLC_GET_VAR, FALSE, 0))
++		return -1;
++	if ((tlv & (WLFC_FLAGS_RSSI_SIGNALS | WLFC_FLAGS_XONXOFF_SIGNALS)) ==
++		(WLFC_FLAGS_RSSI_SIGNALS | WLFC_FLAGS_XONXOFF_SIGNALS))
++		return 0;
++	tlv |= (WLFC_FLAGS_RSSI_SIGNALS | WLFC_FLAGS_XONXOFF_SIGNALS);
++	if (!dhd_wl_ioctl_set_intiovar(dhd, "tlv", tlv, WLC_SET_VAR, TRUE, 0))
++		return -1;
++
++	return 0;
++}
++
++#endif /* SUPPORT_P2P_GO_PS */
++
++/** A flow control header was received from firmware, containing one or more TLVs */
++int
++dhd_wlfc_parse_header_info(dhd_pub_t *dhd, void* pktbuf, int tlv_hdr_len, uchar *reorder_info_buf,
++	uint *reorder_info_len)
++{
++	uint8 type, len;
++	uint8* value;
++	uint8* tmpbuf;
++	uint16 remainder = (uint16)tlv_hdr_len;
++	uint16 processed = 0;
++	athost_wl_status_info_t* wlfc = NULL;
++	void* entry;
++
++	if ((dhd == NULL) || (pktbuf == NULL)) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (dhd->proptxstatus_mode != WLFC_ONLY_AMPDU_HOSTREORDER) {
++		if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++			dhd_os_wlfc_unblock(dhd);
++			return WLFC_UNSUPPORTED;
++		}
++		wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	}
++
++	tmpbuf = (uint8*)PKTDATA(dhd->osh, pktbuf);
++
++	if (remainder) {
++		while ((processed < (WLFC_MAX_PENDING_DATALEN * 2)) && (remainder > 0)) {
++			type = tmpbuf[processed];
++			if (type == WLFC_CTL_TYPE_FILLER) {
++				remainder -= 1;
++				processed += 1;
++				continue;
++			}
++
++			len  = tmpbuf[processed + 1];
++			value = &tmpbuf[processed + 2];
++
++			if (remainder < (2 + len))
++				break;
++
++			remainder -= 2 + len;
++			processed += 2 + len;
++			entry = NULL;
++
++			DHD_INFO(("%s():%d type %d remainder %d processed %d\n",
++				__FUNCTION__, __LINE__, type, remainder, processed));
++
++			if (type == WLFC_CTL_TYPE_HOST_REORDER_RXPKTS)
++				_dhd_wlfc_reorderinfo_indicate(value, len, reorder_info_buf,
++					reorder_info_len);
++
++			if (wlfc == NULL) {
++				ASSERT(dhd->proptxstatus_mode == WLFC_ONLY_AMPDU_HOSTREORDER);
++
++				if (type != WLFC_CTL_TYPE_HOST_REORDER_RXPKTS &&
++					type != WLFC_CTL_TYPE_TRANS_ID)
++					DHD_INFO(("%s():%d dhd->wlfc_state is NULL yet!"
++					" type %d remainder %d processed %d\n",
++					__FUNCTION__, __LINE__, type, remainder, processed));
++				continue;
++			}
++
++			if (type == WLFC_CTL_TYPE_TXSTATUS) {
++				_dhd_wlfc_compressed_txstatus_update(dhd, value, 1, &entry);
++			} else if (type == WLFC_CTL_TYPE_COMP_TXSTATUS) {
++				uint8 compcnt_offset = WLFC_CTL_VALUE_LEN_TXSTATUS;
++
++				if (WLFC_GET_REUSESEQ(dhd->wlfc_mode)) {
++					compcnt_offset += WLFC_CTL_VALUE_LEN_SEQ;
++				}
++				_dhd_wlfc_compressed_txstatus_update(dhd, value,
++					value[compcnt_offset], &entry);
++			} else if (type == WLFC_CTL_TYPE_FIFO_CREDITBACK) {
++				_dhd_wlfc_fifocreditback_indicate(dhd, value);
++			} else if (type == WLFC_CTL_TYPE_RSSI) {
++				_dhd_wlfc_rssi_indicate(dhd, value);
++			} else if (type == WLFC_CTL_TYPE_MAC_REQUEST_CREDIT) {
++				_dhd_wlfc_credit_request(dhd, value);
++			} else if (type == WLFC_CTL_TYPE_MAC_REQUEST_PACKET) {
++				_dhd_wlfc_packet_request(dhd, value);
++			} else if ((type == WLFC_CTL_TYPE_MAC_OPEN) ||
++				(type == WLFC_CTL_TYPE_MAC_CLOSE)) {
++				_dhd_wlfc_psmode_update(dhd, value, type);
++			} else if ((type == WLFC_CTL_TYPE_MACDESC_ADD) ||
++				(type == WLFC_CTL_TYPE_MACDESC_DEL)) {
++				_dhd_wlfc_mac_table_update(dhd, value, type);
++			} else if (type == WLFC_CTL_TYPE_TRANS_ID) {
++				_dhd_wlfc_dbg_senum_check(dhd, value);
++			} else if ((type == WLFC_CTL_TYPE_INTERFACE_OPEN) ||
++				(type == WLFC_CTL_TYPE_INTERFACE_CLOSE)) {
++				_dhd_wlfc_interface_update(dhd, value, type);
++			}
++
++#ifndef BCMDBUS
++			if (entry && WLFC_GET_REORDERSUPP(dhd->wlfc_mode)) {
++				/* suppress all packets for this mac entry from bus->txq */
++				_dhd_wlfc_suppress_txq(dhd, _dhd_wlfc_entrypkt_fn, entry);
++			}
++#endif /* !BCMDBUS */
++		} /* while */
++
++		if (remainder != 0 && wlfc) {
++			/* trouble..., something is not right */
++			wlfc->stats.tlv_parse_failed++;
++		}
++	} /* if */
++
++	if (wlfc)
++		wlfc->stats.dhd_hdrpulls++;
++
++	dhd_os_wlfc_unblock(dhd);
++	return BCME_OK;
++} /* dhd_wlfc_parse_header_info */
++
++KERNEL_THREAD_RETURN_TYPE
++dhd_wlfc_transfer_packets(void *data)
++{
++	dhd_pub_t *dhdp = (dhd_pub_t *)data;
++	int ac, single_ac = 0, rc = BCME_OK;
++	dhd_wlfc_commit_info_t  commit_info;
++	athost_wl_status_info_t* ctx;
++	int bus_retry_count = 0;
++	int pkt_send = 0;
++
++	uint8 tx_map = 0; /* packets (send + in queue), Bitmask for 4 ACs + BC/MC */
++	uint8 rx_map = 0; /* received packets, Bitmask for 4 ACs + BC/MC */
++	uint8 packets_map = 0; /* packets in queue, Bitmask for 4 ACs + BC/MC */
++	bool no_credit = FALSE;
++
++	int lender;
++
++#if defined(DHD_WLFC_THREAD)
++	/* wait till someone wakeup me up, will change it at running time */
++	int wait_msec = msecs_to_jiffies(0xFFFFFFFF);
++#endif /* defined(DHD_WLFC_THREAD) */
++
++#if defined(DHD_WLFC_THREAD)
++	while (1) {
++		bus_retry_count = 0;
++		pkt_send = 0;
++		tx_map = 0;
++		rx_map = 0;
++		packets_map = 0;
++		wait_msec = wait_event_interruptible_timeout(dhdp->wlfc_wqhead,
++			dhdp->wlfc_thread_go, wait_msec);
++		if (kthread_should_stop()) {
++			break;
++		}
++		dhdp->wlfc_thread_go = FALSE;
++
++		dhd_os_wlfc_block(dhdp);
++#endif /* defined(DHD_WLFC_THREAD) */
++		ctx = (athost_wl_status_info_t*)dhdp->wlfc_state;
++#if defined(DHD_WLFC_THREAD)
++		if (!ctx)
++			goto exit;
++#endif /* defined(DHD_WLFC_THREAD) */
++
++	memset(&commit_info, 0, sizeof(commit_info));
++
++	/*
++	Commit packets for regular AC traffic. Higher priority first.
++	First, use up FIFO credits available to each AC. Based on distribution
++	and credits left, borrow from other ACs as applicable
++
++	-NOTE:
++	If the bus between the host and firmware is overwhelmed by the
++	traffic from host, it is possible that higher priority traffic
++	starves the lower priority queue. If that occurs often, we may
++	have to employ weighted round-robin or ucode scheme to avoid
++	low priority packet starvation.
++	*/
++
++	for (ac = AC_COUNT; ac >= 0; ac--) {
++		if (dhdp->wlfc_rxpkt_chk) {
++			/* check rx packet */
++			uint32 curr_t = OSL_SYSUPTIME(), delta;
++
++			delta = curr_t - ctx->rx_timestamp[ac];
++			if (delta < WLFC_RX_DETECTION_THRESHOLD_MS) {
++				rx_map |= (1 << ac);
++			}
++		}
++
++		if (ctx->pkt_cnt_per_ac[ac] == 0) {
++			continue;
++		}
++
++		tx_map |= (1 << ac);
++		single_ac = ac + 1;
++		while (FALSE == dhdp->proptxstatus_txoff) {
++			/* packets from delayQ with less priority are fresh and
++			 * they'd need header and have no MAC entry
++			 */
++			no_credit = (ctx->FIFO_credit[ac] < 1);
++			if (dhdp->proptxstatus_credit_ignore ||
++				((ac == AC_COUNT) && !ctx->bcmc_credit_supported)) {
++				no_credit = FALSE;
++			}
++
++			lender = -1;
++#ifdef LIMIT_BORROW
++			if (no_credit && (ac < AC_COUNT) && (tx_map >= rx_map) &&
++				dhdp->wlfc_borrow_allowed) {
++				/* try borrow from lower priority */
++				lender = _dhd_wlfc_borrow_credit(ctx, ac - 1, ac, FALSE);
++				if (lender != -1) {
++					no_credit = FALSE;
++				}
++			}
++#endif
++			commit_info.needs_hdr = 1;
++			commit_info.mac_entry = NULL;
++			commit_info.p = _dhd_wlfc_deque_delayedq(ctx, ac,
++				&(commit_info.ac_fifo_credit_spent),
++				&(commit_info.needs_hdr),
++				&(commit_info.mac_entry),
++				no_credit);
++			commit_info.pkt_type = (commit_info.needs_hdr) ? eWLFC_PKTTYPE_DELAYED :
++				eWLFC_PKTTYPE_SUPPRESSED;
++
++			if (commit_info.p == NULL) {
++#ifdef LIMIT_BORROW
++				if (lender != -1 && dhdp->wlfc_borrow_allowed) {
++					_dhd_wlfc_return_credit(ctx, lender, ac);
++				}
++#endif
++				break;
++			}
++
++			if (!dhdp->proptxstatus_credit_ignore && (lender == -1)) {
++				ASSERT(ctx->FIFO_credit[ac] >= commit_info.ac_fifo_credit_spent);
++			}
++			/* here we can ensure have credit or no credit needed */
++			rc = _dhd_wlfc_handle_packet_commit(ctx, ac, &commit_info,
++				ctx->fcommit, ctx->commit_ctx);
++
++			/* Bus commits may fail (e.g. flow control); abort after retries */
++			if (rc == BCME_OK) {
++				pkt_send++;
++				if (commit_info.ac_fifo_credit_spent && (lender == -1)) {
++					ctx->FIFO_credit[ac]--;
++				}
++#ifdef LIMIT_BORROW
++				else if (!commit_info.ac_fifo_credit_spent && (lender != -1) &&
++					dhdp->wlfc_borrow_allowed) {
++					_dhd_wlfc_return_credit(ctx, lender, ac);
++				}
++#endif
++			} else {
++#ifdef LIMIT_BORROW
++				if (lender != -1 && dhdp->wlfc_borrow_allowed) {
++					_dhd_wlfc_return_credit(ctx, lender, ac);
++				}
++#endif
++				bus_retry_count++;
++				if (bus_retry_count >= BUS_RETRIES) {
++					DHD_ERROR(("%s: bus error %d\n", __FUNCTION__, rc));
++					goto exit;
++				}
++			}
++		}
++
++		if (ctx->pkt_cnt_per_ac[ac]) {
++			packets_map |= (1 << ac);
++		}
++	}
++
++	if ((tx_map == 0) || dhdp->proptxstatus_credit_ignore) {
++		/* nothing send out or remain in queue */
++		rc = BCME_OK;
++		goto exit;
++	}
++
++	if (((tx_map & (tx_map - 1)) == 0) && (tx_map >= rx_map)) {
++		/* only one tx ac exist and no higher rx ac */
++		if ((single_ac == ctx->single_ac) && ctx->allow_credit_borrow) {
++			ac = single_ac - 1;
++		} else {
++			uint32 delta;
++			uint32 curr_t = OSL_SYSUPTIME();
++
++			if (single_ac != ctx->single_ac) {
++				/* new single ac traffic (first single ac or different single ac) */
++				ctx->allow_credit_borrow = 0;
++				ctx->single_ac_timestamp = curr_t;
++				ctx->single_ac = (uint8)single_ac;
++				rc = BCME_OK;
++				goto exit;
++			}
++			/* same ac traffic, check if it lasts enough time */
++			delta = curr_t - ctx->single_ac_timestamp;
++
++			if (delta >= WLFC_BORROW_DEFER_PERIOD_MS) {
++				/* wait enough time, can borrow now */
++				ctx->allow_credit_borrow = 1;
++				ac = single_ac - 1;
++			} else {
++				rc = BCME_OK;
++				goto exit;
++			}
++		}
++	} else {
++		/* If we have multiple AC traffic, turn off borrowing, mark time and bail out */
++		ctx->allow_credit_borrow = 0;
++		ctx->single_ac_timestamp = 0;
++		ctx->single_ac = 0;
++		rc = BCME_OK;
++		goto exit;
++	}
++
++	if (packets_map == 0) {
++		/* nothing to send, skip borrow */
++		rc = BCME_OK;
++		goto exit;
++	}
++
++	/* At this point, borrow all credits only for ac */
++	while (FALSE == dhdp->proptxstatus_txoff) {
++#ifdef LIMIT_BORROW
++		if (dhdp->wlfc_borrow_allowed) {
++			if ((lender = _dhd_wlfc_borrow_credit(ctx, AC_COUNT, ac, TRUE)) == -1) {
++				break;
++			}
++		}
++		else
++			break;
++#endif
++		commit_info.p = _dhd_wlfc_deque_delayedq(ctx, ac,
++			&(commit_info.ac_fifo_credit_spent),
++			&(commit_info.needs_hdr),
++			&(commit_info.mac_entry),
++			FALSE);
++		if (commit_info.p == NULL) {
++			/* before borrow only one ac exists and now this only ac is empty */
++#ifdef LIMIT_BORROW
++			_dhd_wlfc_return_credit(ctx, lender, ac);
++#endif
++			break;
++		}
++
++		commit_info.pkt_type = (commit_info.needs_hdr) ? eWLFC_PKTTYPE_DELAYED :
++			eWLFC_PKTTYPE_SUPPRESSED;
++
++		rc = _dhd_wlfc_handle_packet_commit(ctx, ac, &commit_info,
++		     ctx->fcommit, ctx->commit_ctx);
++
++		/* Bus commits may fail (e.g. flow control); abort after retries */
++		if (rc == BCME_OK) {
++			pkt_send++;
++			if (commit_info.ac_fifo_credit_spent) {
++#ifndef LIMIT_BORROW
++				ctx->FIFO_credit[ac]--;
++#endif
++			} else {
++#ifdef LIMIT_BORROW
++				_dhd_wlfc_return_credit(ctx, lender, ac);
++#endif
++			}
++		} else {
++#ifdef LIMIT_BORROW
++			_dhd_wlfc_return_credit(ctx, lender, ac);
++#endif
++			bus_retry_count++;
++			if (bus_retry_count >= BUS_RETRIES) {
++				DHD_ERROR(("%s: bus error %d\n", __FUNCTION__, rc));
++				goto exit;
++			}
++		}
++	}
++
++	BCM_REFERENCE(pkt_send);
++
++exit:
++#if defined(DHD_WLFC_THREAD)
++		dhd_os_wlfc_unblock(dhdp);
++		if (ctx && ctx->pkt_cnt_in_psq && pkt_send) {
++			wait_msec = msecs_to_jiffies(WLFC_THREAD_QUICK_RETRY_WAIT_MS);
++		} else {
++			wait_msec = msecs_to_jiffies(WLFC_THREAD_RETRY_WAIT_MS);
++		}
++	}
++	return 0;
++#else
++	return rc;
++#endif /* defined(DHD_WLFC_THREAD) */
++}
++
++/**
++ * Enqueues a transmit packet in the next layer towards the dongle, eg the DBUS layer. Called by
++ * eg dhd_sendpkt().
++ *     @param[in] dhdp                  Pointer to public DHD structure
++ *     @param[in] fcommit               Pointer to transmit function of next layer
++ *     @param[in] commit_ctx            Opaque context used when calling next layer
++ *     @param[in] pktbuf                Packet to send
++ *     @param[in] need_toggle_host_if   If TRUE, resets flag ctx->toggle_host_if
++ */
++int
++dhd_wlfc_commit_packets(dhd_pub_t *dhdp, f_commitpkt_t fcommit, void* commit_ctx, void *pktbuf,
++	bool need_toggle_host_if)
++{
++	int rc = BCME_OK;
++	athost_wl_status_info_t* ctx;
++
++#if defined(DHD_WLFC_THREAD)
++	if (!pktbuf)
++		return BCME_OK;
++#endif /* defined(DHD_WLFC_THREAD) */
++
++	if ((dhdp == NULL) || (fcommit == NULL)) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhdp);
++
++	if (!dhdp->wlfc_state || (dhdp->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		if (pktbuf) {
++			DHD_PKTTAG_WLFCPKT_SET(PKTTAG(pktbuf), 0);
++		}
++		rc =  WLFC_UNSUPPORTED;
++		goto exit;
++	}
++
++	ctx = (athost_wl_status_info_t*)dhdp->wlfc_state;
++
++#ifdef BCMDBUS
++	if (!dhdp->up || (dhdp->busstate == DHD_BUS_DOWN)) {
++		if (pktbuf) {
++			PKTFREE(ctx->osh, pktbuf, TRUE);
++			rc = BCME_OK;
++		}
++		goto exit;
++	}
++#endif
++
++	if (dhdp->proptxstatus_module_ignore) {
++		if (pktbuf) {
++			uint32 htod = 0;
++			WL_TXSTATUS_SET_FLAGS(htod, WLFC_PKTFLAG_PKTFROMHOST);
++			_dhd_wlfc_pushheader(ctx, &pktbuf, FALSE, 0, 0, htod, 0, FALSE);
++			if (fcommit(commit_ctx, pktbuf)) {
++				/* free it if failed, otherwise do it in tx complete cb */
++				PKTFREE(ctx->osh, pktbuf, TRUE);
++			}
++			rc = BCME_OK;
++		}
++		goto exit;
++	}
++
++	if (pktbuf) {
++		int ac = DHD_PKTTAG_FIFO(PKTTAG(pktbuf));
++		ASSERT(ac <= AC_COUNT);
++		DHD_PKTTAG_WLFCPKT_SET(PKTTAG(pktbuf), 1);
++		/* en-queue the packets to respective queue. */
++		rc = _dhd_wlfc_enque_delayq(ctx, pktbuf, ac);
++		if (rc) {
++			_dhd_wlfc_prec_drop(ctx->dhdp, (ac << 1), pktbuf, FALSE);
++		} else {
++			ctx->stats.pktin++;
++			ctx->pkt_cnt_in_drv[DHD_PKTTAG_IF(PKTTAG(pktbuf))][ac]++;
++		}
++	}
++
++	if (!ctx->fcommit) {
++		ctx->fcommit = fcommit;
++	} else {
++		ASSERT(ctx->fcommit == fcommit);
++	}
++	if (!ctx->commit_ctx) {
++		ctx->commit_ctx = commit_ctx;
++	} else {
++		ASSERT(ctx->commit_ctx == commit_ctx);
++	}
++
++#if defined(DHD_WLFC_THREAD)
++	_dhd_wlfc_thread_wakeup(dhdp);
++#else
++	dhd_wlfc_transfer_packets(dhdp);
++#endif /* defined(DHD_WLFC_THREAD) */
++
++exit:
++	dhd_os_wlfc_unblock(dhdp);
++	return rc;
++} /* dhd_wlfc_commit_packets */
++
++/**
++ * Called when the (lower) DBUS layer indicates completion (succesfull or not) of a transmit packet
++ */
++int
++dhd_wlfc_txcomplete(dhd_pub_t *dhd, void *txp, bool success)
++{
++	athost_wl_status_info_t* wlfc;
++	wlfc_mac_descriptor_t *entry;
++	void* pout = NULL;
++	int rtn = BCME_OK;
++	if ((dhd == NULL) || (txp == NULL)) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	bcm_pkt_validate_chk(txp);
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		rtn = WLFC_UNSUPPORTED;
++		goto EXIT;
++	}
++
++	wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++	if (DHD_PKTTAG_SIGNALONLY(PKTTAG(txp))) {
++#ifdef PROP_TXSTATUS_DEBUG
++		wlfc->stats.signal_only_pkts_freed++;
++#endif
++		/* is this a signal-only packet? */
++		_dhd_wlfc_pullheader(wlfc, txp);
++		PKTFREE(wlfc->osh, txp, TRUE);
++		goto EXIT;
++	}
++
++	entry = _dhd_wlfc_find_table_entry(wlfc, txp);
++	ASSERT(entry);
++
++	if (!success || dhd->proptxstatus_txstatus_ignore) {
++		WLFC_DBGMESG(("At: %s():%d, bus_complete() failure for %p, htod_tag:0x%08x\n",
++			__FUNCTION__, __LINE__, txp, DHD_PKTTAG_H2DTAG(PKTTAG(txp))));
++		if (!WLFC_GET_AFQ(dhd->wlfc_mode)) {
++			_dhd_wlfc_hanger_poppkt(wlfc->hanger, WL_TXSTATUS_GET_HSLOT(
++				DHD_PKTTAG_H2DTAG(PKTTAG(txp))), &pout, TRUE);
++			ASSERT(txp == pout);
++		}
++
++		/* indicate failure and free the packet */
++		dhd_txcomplete(dhd, txp, success);
++
++		/* return the credit, if necessary */
++		_dhd_wlfc_return_implied_credit(wlfc, txp);
++
++		if (entry->transit_count)
++			entry->transit_count--;
++		if (entry->suppr_transit_count)
++			entry->suppr_transit_count--;
++		wlfc->pkt_cnt_in_drv[DHD_PKTTAG_IF(PKTTAG(txp))][DHD_PKTTAG_FIFO(PKTTAG(txp))]--;
++		wlfc->stats.pktout++;
++		PKTFREE(wlfc->osh, txp, TRUE);
++	} else {
++		/* bus confirmed pkt went to firmware side */
++		if (WLFC_GET_AFQ(dhd->wlfc_mode)) {
++			_dhd_wlfc_enque_afq(wlfc, txp);
++		} else {
++			int hslot = WL_TXSTATUS_GET_HSLOT(DHD_PKTTAG_H2DTAG(PKTTAG(txp)));
++			_dhd_wlfc_hanger_free_pkt(wlfc, hslot,
++				WLFC_HANGER_PKT_STATE_BUSRETURNED, -1);
++		}
++	}
++
++	ASSERT(entry->onbus_pkts_count > 0);
++	if (entry->onbus_pkts_count > 0)
++		entry->onbus_pkts_count--;
++	if (entry->suppressed &&
++		(!entry->onbus_pkts_count) &&
++		(!entry->suppr_transit_count))
++		entry->suppressed = FALSE;
++EXIT:
++	dhd_os_wlfc_unblock(dhd);
++	return rtn;
++} /* dhd_wlfc_txcomplete */
++
++int
++dhd_wlfc_init(dhd_pub_t *dhd)
++{
++	/* enable all signals & indicate host proptxstatus logic is active */
++	uint32 tlv, mode, fw_caps;
++	int ret = 0;
++
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++	if (dhd->wlfc_enabled) {
++		DHD_INFO(("%s():%d, Already enabled!\n", __FUNCTION__, __LINE__));
++		dhd_os_wlfc_unblock(dhd);
++		return BCME_OK;
++	}
++	dhd->wlfc_enabled = TRUE;
++	dhd_os_wlfc_unblock(dhd);
++
++	tlv = WLFC_FLAGS_RSSI_SIGNALS |
++		WLFC_FLAGS_XONXOFF_SIGNALS |
++		WLFC_FLAGS_CREDIT_STATUS_SIGNALS |
++		WLFC_FLAGS_HOST_PROPTXSTATUS_ACTIVE |
++		WLFC_FLAGS_HOST_RXRERODER_ACTIVE;
++
++
++	/*
++	try to enable/disable signaling by sending "tlv" iovar. if that fails,
++	fallback to no flow control? Print a message for now.
++	*/
++
++	/* enable proptxtstatus signaling by default */
++	if (!dhd_wl_ioctl_set_intiovar(dhd, "tlv", tlv, WLC_SET_VAR, TRUE, 0)) {
++		/*
++		Leaving the message for now, it should be removed after a while; once
++		the tlv situation is stable.
++		*/
++		DHD_INFO(("dhd_wlfc_init(): successfully %s bdcv2 tlv signaling, %d\n",
++			dhd->wlfc_enabled?"enabled":"disabled", tlv));
++	}
++
++	mode = 0;
++
++	/* query caps */
++	ret = dhd_wl_ioctl_get_intiovar(dhd, "wlfc_mode", &fw_caps, WLC_GET_VAR, FALSE, 0);
++
++	if (!ret) {
++		DHD_INFO(("%s: query wlfc_mode succeed, fw_caps=0x%x\n", __FUNCTION__, fw_caps));
++
++		if (WLFC_IS_OLD_DEF(fw_caps)) {
++#ifdef BCMDBUS
++			mode = WLFC_MODE_HANGER;
++#else
++			/* enable proptxtstatus v2 by default */
++			mode = WLFC_MODE_AFQ;
++#endif /* BCMDBUS */
++		} else {
++			WLFC_SET_AFQ(mode, WLFC_GET_AFQ(fw_caps));
++#ifdef BCMDBUS
++			WLFC_SET_AFQ(mode, 0);
++#endif /* BCMDBUS */
++			WLFC_SET_REUSESEQ(mode, WLFC_GET_REUSESEQ(fw_caps));
++			WLFC_SET_REORDERSUPP(mode, WLFC_GET_REORDERSUPP(fw_caps));
++		}
++		ret = dhd_wl_ioctl_set_intiovar(dhd, "wlfc_mode", mode, WLC_SET_VAR, TRUE, 0);
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	dhd->wlfc_mode = 0;
++	if (ret >= 0) {
++		if (WLFC_IS_OLD_DEF(mode)) {
++			WLFC_SET_AFQ(dhd->wlfc_mode, (mode == WLFC_MODE_AFQ));
++		} else {
++			dhd->wlfc_mode = mode;
++		}
++	}
++
++	DHD_INFO(("dhd_wlfc_init(): wlfc_mode=0x%x, ret=%d\n", dhd->wlfc_mode, ret));
++#ifdef LIMIT_BORROW
++	dhd->wlfc_borrow_allowed = TRUE;
++#endif
++	dhd_os_wlfc_unblock(dhd);
++
++	if (dhd->plat_init)
++		dhd->plat_init((void *)dhd);
++
++	return BCME_OK;
++} /* dhd_wlfc_init */
++
++/** AMPDU host reorder specific function */
++int
++dhd_wlfc_hostreorder_init(dhd_pub_t *dhd)
++{
++	/* enable only ampdu hostreorder here */
++	uint32 tlv;
++
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	DHD_TRACE(("%s():%d Enter\n", __FUNCTION__, __LINE__));
++
++	tlv = WLFC_FLAGS_HOST_RXRERODER_ACTIVE;
++
++	/* enable proptxtstatus signaling by default */
++	if (dhd_wl_ioctl_set_intiovar(dhd, "tlv", tlv, WLC_SET_VAR, TRUE, 0)) {
++		DHD_ERROR(("%s(): failed to enable/disable bdcv2 tlv signaling\n",
++			__FUNCTION__));
++	} else {
++		/*
++		Leaving the message for now, it should be removed after a while; once
++		the tlv situation is stable.
++		*/
++		DHD_ERROR(("%s(): successful bdcv2 tlv signaling, %d\n",
++			__FUNCTION__, tlv));
++	}
++
++	dhd_os_wlfc_block(dhd);
++	dhd->proptxstatus_mode = WLFC_ONLY_AMPDU_HOSTREORDER;
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++int
++dhd_wlfc_cleanup_txq(dhd_pub_t *dhd, f_processpkt_t fn, void *arg)
++{
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhd);
++		return WLFC_UNSUPPORTED;
++	}
++
++#ifndef BCMDBUS
++	_dhd_wlfc_cleanup_txq(dhd, fn, arg);
++#endif /* !BCMDBUS */
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** release all packet resources */
++int
++dhd_wlfc_cleanup(dhd_pub_t *dhd, f_processpkt_t fn, void *arg)
++{
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhd);
++		return WLFC_UNSUPPORTED;
++	}
++
++	_dhd_wlfc_cleanup(dhd, fn, arg);
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++int
++dhd_wlfc_deinit(dhd_pub_t *dhd)
++{
++	/* cleanup all psq related resources */
++	athost_wl_status_info_t* wlfc;
++	uint32 tlv = 0;
++	uint32 hostreorder = 0;
++
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++	if (!dhd->wlfc_enabled) {
++		DHD_ERROR(("%s():%d, Already disabled!\n", __FUNCTION__, __LINE__));
++		dhd_os_wlfc_unblock(dhd);
++		return BCME_OK;
++	}
++
++	dhd->wlfc_enabled = FALSE;
++	dhd_os_wlfc_unblock(dhd);
++
++	/* query ampdu hostreorder */
++	(void) dhd_wl_ioctl_get_intiovar(dhd, "ampdu_hostreorder",
++		&hostreorder, WLC_GET_VAR, FALSE, 0);
++
++	if (hostreorder) {
++		tlv = WLFC_FLAGS_HOST_RXRERODER_ACTIVE;
++		DHD_ERROR(("%s():%d, maintain HOST RXRERODER flag in tvl\n",
++			__FUNCTION__, __LINE__));
++	}
++
++	/* Disable proptxtstatus signaling for deinit */
++	(void) dhd_wl_ioctl_set_intiovar(dhd, "tlv", tlv, WLC_SET_VAR, TRUE, 0);
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhd);
++		return WLFC_UNSUPPORTED;
++	}
++
++	wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++
++	_dhd_wlfc_cleanup(dhd, NULL, NULL);
++
++	if (!WLFC_GET_AFQ(dhd->wlfc_mode)) {
++		int i;
++		wlfc_hanger_t* h = (wlfc_hanger_t*)wlfc->hanger;
++		for (i = 0; i < h->max_items; i++) {
++			if (h->items[i].state != WLFC_HANGER_ITEM_STATE_FREE) {
++				_dhd_wlfc_hanger_free_pkt(wlfc, i,
++					WLFC_HANGER_PKT_STATE_COMPLETE, TRUE);
++			}
++		}
++
++		/* delete hanger */
++		_dhd_wlfc_hanger_delete(dhd, h);
++	}
++
++
++	/* free top structure */
++	DHD_OS_PREFREE(dhd, dhd->wlfc_state,
++		sizeof(athost_wl_status_info_t));
++	dhd->wlfc_state = NULL;
++	dhd->proptxstatus_mode = hostreorder ?
++		WLFC_ONLY_AMPDU_HOSTREORDER : WLFC_FCMODE_NONE;
++
++	dhd_os_wlfc_unblock(dhd);
++
++	if (dhd->plat_deinit)
++		dhd->plat_deinit((void *)dhd);
++	return BCME_OK;
++} /* dhd_wlfc_init */
++
++/**
++ * Called on an interface event (WLC_E_IF) indicated by firmware
++ *     @param[in] dhdp   Pointer to public DHD structure
++ *     @param[in] action eg eWLFC_MAC_ENTRY_ACTION_UPDATE or eWLFC_MAC_ENTRY_ACTION_ADD
++ */
++int dhd_wlfc_interface_event(dhd_pub_t *dhdp, uint8 action, uint8 ifid, uint8 iftype, uint8* ea)
++{
++	int rc;
++
++	if (dhdp == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhdp);
++
++	if (!dhdp->wlfc_state || (dhdp->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhdp);
++		return WLFC_UNSUPPORTED;
++	}
++
++	rc = _dhd_wlfc_interface_entry_update(dhdp->wlfc_state, action, ifid, iftype, ea);
++
++	dhd_os_wlfc_unblock(dhdp);
++	return rc;
++}
++
++/** Called eg on receiving a WLC_E_FIFO_CREDIT_MAP event from the dongle */
++int dhd_wlfc_FIFOcreditmap_event(dhd_pub_t *dhdp, uint8* event_data)
++{
++	int rc;
++
++	if (dhdp == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhdp);
++
++	if (!dhdp->wlfc_state || (dhdp->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhdp);
++		return WLFC_UNSUPPORTED;
++	}
++
++	rc = _dhd_wlfc_FIFOcreditmap_update(dhdp->wlfc_state, event_data);
++
++	dhd_os_wlfc_unblock(dhdp);
++
++	return rc;
++}
++#ifdef LIMIT_BORROW
++int dhd_wlfc_disable_credit_borrow_event(dhd_pub_t *dhdp, uint8* event_data)
++{
++	int rc;
++	if (dhdp == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++	dhd_os_wlfc_block(dhdp);
++	dhdp->wlfc_borrow_allowed = (bool)(*(uint32 *)event_data);
++	dhd_os_wlfc_unblock(dhdp);
++
++	return rc;
++}
++#endif /* LIMIT_BORROW */
++
++/**
++ * Called eg on receiving a WLC_E_BCMC_CREDIT_SUPPORT event from the dongle (broadcast/multicast
++ * specific)
++ */
++int dhd_wlfc_BCMCCredit_support_event(dhd_pub_t *dhdp)
++{
++	int rc;
++
++	if (dhdp == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhdp);
++
++	if (!dhdp->wlfc_state || (dhdp->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhdp);
++		return WLFC_UNSUPPORTED;
++	}
++
++	rc = _dhd_wlfc_BCMCCredit_support_update(dhdp->wlfc_state);
++
++	dhd_os_wlfc_unblock(dhdp);
++	return rc;
++}
++
++/** debug specific function */
++int
++dhd_wlfc_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
++{
++	int i;
++	uint8* ea;
++	athost_wl_status_info_t* wlfc;
++	wlfc_hanger_t* h;
++	wlfc_mac_descriptor_t* mac_table;
++	wlfc_mac_descriptor_t* interfaces;
++	char* iftypes[] = {"STA", "AP", "WDS", "p2pGO", "p2pCL"};
++
++	if (!dhdp || !strbuf) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhdp);
++
++	if (!dhdp->wlfc_state || (dhdp->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhdp);
++		return WLFC_UNSUPPORTED;
++	}
++
++	wlfc = (athost_wl_status_info_t*)dhdp->wlfc_state;
++
++	h = (wlfc_hanger_t*)wlfc->hanger;
++	if (h == NULL) {
++		bcm_bprintf(strbuf, "wlfc-hanger not initialized yet\n");
++	}
++
++	mac_table = wlfc->destination_entries.nodes;
++	interfaces = wlfc->destination_entries.interfaces;
++	bcm_bprintf(strbuf, "---- wlfc stats ----\n");
++
++	if (!WLFC_GET_AFQ(dhdp->wlfc_mode)) {
++		h = (wlfc_hanger_t*)wlfc->hanger;
++		if (h == NULL) {
++			bcm_bprintf(strbuf, "wlfc-hanger not initialized yet\n");
++		} else {
++			bcm_bprintf(strbuf, "wlfc hanger (pushed,popped,f_push,"
++				"f_pop,f_slot, pending) = (%d,%d,%d,%d,%d,%d)\n",
++				h->pushed,
++				h->popped,
++				h->failed_to_push,
++				h->failed_to_pop,
++				h->failed_slotfind,
++				(h->pushed - h->popped));
++		}
++	}
++
++	bcm_bprintf(strbuf, "wlfc fail(tlv,credit_rqst,mac_update,psmode_update), "
++		"(dq_full,rollback_fail) = (%d,%d,%d,%d), (%d,%d)\n",
++		wlfc->stats.tlv_parse_failed,
++		wlfc->stats.credit_request_failed,
++		wlfc->stats.mac_update_failed,
++		wlfc->stats.psmode_update_failed,
++		wlfc->stats.delayq_full_error,
++		wlfc->stats.rollback_failed);
++
++	bcm_bprintf(strbuf, "PKTS (init_credit,credit,sent,drop_d,drop_s,outoforder) "
++		"(AC0[%d,%d,%d,%d,%d,%d],AC1[%d,%d,%d,%d,%d,%d],AC2[%d,%d,%d,%d,%d,%d],"
++		"AC3[%d,%d,%d,%d,%d,%d],BC_MC[%d,%d,%d,%d,%d,%d])\n",
++		wlfc->Init_FIFO_credit[0], wlfc->FIFO_credit[0], wlfc->stats.send_pkts[0],
++		wlfc->stats.drop_pkts[0], wlfc->stats.drop_pkts[1], wlfc->stats.ooo_pkts[0],
++		wlfc->Init_FIFO_credit[1], wlfc->FIFO_credit[1], wlfc->stats.send_pkts[1],
++		wlfc->stats.drop_pkts[2], wlfc->stats.drop_pkts[3], wlfc->stats.ooo_pkts[1],
++		wlfc->Init_FIFO_credit[2], wlfc->FIFO_credit[2], wlfc->stats.send_pkts[2],
++		wlfc->stats.drop_pkts[4], wlfc->stats.drop_pkts[5], wlfc->stats.ooo_pkts[2],
++		wlfc->Init_FIFO_credit[3], wlfc->FIFO_credit[3], wlfc->stats.send_pkts[3],
++		wlfc->stats.drop_pkts[6], wlfc->stats.drop_pkts[7], wlfc->stats.ooo_pkts[3],
++		wlfc->Init_FIFO_credit[4], wlfc->FIFO_credit[4], wlfc->stats.send_pkts[4],
++		wlfc->stats.drop_pkts[8], wlfc->stats.drop_pkts[9], wlfc->stats.ooo_pkts[4]);
++
++	bcm_bprintf(strbuf, "\n");
++	for (i = 0; i < WLFC_MAX_IFNUM; i++) {
++		if (interfaces[i].occupied) {
++			char* iftype_desc;
++
++			if (interfaces[i].iftype > WLC_E_IF_ROLE_P2P_CLIENT)
++				iftype_desc = "<Unknown";
++			else
++				iftype_desc = iftypes[interfaces[i].iftype];
++
++			ea = interfaces[i].ea;
++			bcm_bprintf(strbuf, "INTERFACE[%d].ea = "
++				"[%02x:%02x:%02x:%02x:%02x:%02x], if:%d, type: %s "
++				"netif_flow_control:%s\n", i,
++				ea[0], ea[1], ea[2], ea[3], ea[4], ea[5],
++				interfaces[i].interface_id,
++				iftype_desc, ((wlfc->hostif_flow_state[i] == OFF)
++				? " OFF":" ON"));
++
++			bcm_bprintf(strbuf, "INTERFACE[%d].PSQ(len,state,credit),"
++				"(trans,supp_trans,onbus)"
++				"= (%d,%s,%d),(%d,%d,%d)\n",
++				i,
++				interfaces[i].psq.len,
++				((interfaces[i].state ==
++				WLFC_STATE_OPEN) ? "OPEN":"CLOSE"),
++				interfaces[i].requested_credit,
++				interfaces[i].transit_count,
++				interfaces[i].suppr_transit_count,
++				interfaces[i].onbus_pkts_count);
++
++			bcm_bprintf(strbuf, "INTERFACE[%d].PSQ"
++				"(delay0,sup0,afq0),(delay1,sup1,afq1),(delay2,sup2,afq2),"
++				"(delay3,sup3,afq3),(delay4,sup4,afq4) = (%d,%d,%d),"
++				"(%d,%d,%d),(%d,%d,%d),(%d,%d,%d),(%d,%d,%d)\n",
++				i,
++				interfaces[i].psq.q[0].len,
++				interfaces[i].psq.q[1].len,
++				interfaces[i].afq.q[0].len,
++				interfaces[i].psq.q[2].len,
++				interfaces[i].psq.q[3].len,
++				interfaces[i].afq.q[1].len,
++				interfaces[i].psq.q[4].len,
++				interfaces[i].psq.q[5].len,
++				interfaces[i].afq.q[2].len,
++				interfaces[i].psq.q[6].len,
++				interfaces[i].psq.q[7].len,
++				interfaces[i].afq.q[3].len,
++				interfaces[i].psq.q[8].len,
++				interfaces[i].psq.q[9].len,
++				interfaces[i].afq.q[4].len);
++		}
++	}
++
++	bcm_bprintf(strbuf, "\n");
++	for (i = 0; i < WLFC_MAC_DESC_TABLE_SIZE; i++) {
++		if (mac_table[i].occupied) {
++			ea = mac_table[i].ea;
++			bcm_bprintf(strbuf, "MAC_table[%d].ea = "
++				"[%02x:%02x:%02x:%02x:%02x:%02x], if:%d \n", i,
++				ea[0], ea[1], ea[2], ea[3], ea[4], ea[5],
++				mac_table[i].interface_id);
++
++			bcm_bprintf(strbuf, "MAC_table[%d].PSQ(len,state,credit),"
++				"(trans,supp_trans,onbus)"
++				"= (%d,%s,%d),(%d,%d,%d)\n",
++				i,
++				mac_table[i].psq.len,
++				((mac_table[i].state ==
++				WLFC_STATE_OPEN) ? " OPEN":"CLOSE"),
++				mac_table[i].requested_credit,
++				mac_table[i].transit_count,
++				mac_table[i].suppr_transit_count,
++				mac_table[i].onbus_pkts_count);
++#ifdef PROP_TXSTATUS_DEBUG
++			bcm_bprintf(strbuf, "MAC_table[%d]: (opened, closed) = (%d, %d)\n",
++				i, mac_table[i].opened_ct, mac_table[i].closed_ct);
++#endif
++			bcm_bprintf(strbuf, "MAC_table[%d].PSQ"
++				"(delay0,sup0,afq0),(delay1,sup1,afq1),(delay2,sup2,afq2),"
++				"(delay3,sup3,afq3),(delay4,sup4,afq4) =(%d,%d,%d),"
++				"(%d,%d,%d),(%d,%d,%d),(%d,%d,%d),(%d,%d,%d)\n",
++				i,
++				mac_table[i].psq.q[0].len,
++				mac_table[i].psq.q[1].len,
++				mac_table[i].afq.q[0].len,
++				mac_table[i].psq.q[2].len,
++				mac_table[i].psq.q[3].len,
++				mac_table[i].afq.q[1].len,
++				mac_table[i].psq.q[4].len,
++				mac_table[i].psq.q[5].len,
++				mac_table[i].afq.q[2].len,
++				mac_table[i].psq.q[6].len,
++				mac_table[i].psq.q[7].len,
++				mac_table[i].afq.q[3].len,
++				mac_table[i].psq.q[8].len,
++				mac_table[i].psq.q[9].len,
++				mac_table[i].afq.q[4].len);
++
++		}
++	}
++
++#ifdef PROP_TXSTATUS_DEBUG
++	{
++		int avg;
++		int moving_avg = 0;
++		int moving_samples;
++
++		if (wlfc->stats.latency_sample_count) {
++			moving_samples = sizeof(wlfc->stats.deltas)/sizeof(uint32);
++
++			for (i = 0; i < moving_samples; i++)
++				moving_avg += wlfc->stats.deltas[i];
++			moving_avg /= moving_samples;
++
++			avg = (100 * wlfc->stats.total_status_latency) /
++				wlfc->stats.latency_sample_count;
++			bcm_bprintf(strbuf, "txstatus latency (average, last, moving[%d]) = "
++				"(%d.%d, %03d, %03d)\n",
++				moving_samples, avg/100, (avg - (avg/100)*100),
++				wlfc->stats.latency_most_recent,
++				moving_avg);
++		}
++	}
++
++	bcm_bprintf(strbuf, "wlfc- fifo[0-5] credit stats: sent = (%d,%d,%d,%d,%d,%d), "
++		"back = (%d,%d,%d,%d,%d,%d)\n",
++		wlfc->stats.fifo_credits_sent[0],
++		wlfc->stats.fifo_credits_sent[1],
++		wlfc->stats.fifo_credits_sent[2],
++		wlfc->stats.fifo_credits_sent[3],
++		wlfc->stats.fifo_credits_sent[4],
++		wlfc->stats.fifo_credits_sent[5],
++
++		wlfc->stats.fifo_credits_back[0],
++		wlfc->stats.fifo_credits_back[1],
++		wlfc->stats.fifo_credits_back[2],
++		wlfc->stats.fifo_credits_back[3],
++		wlfc->stats.fifo_credits_back[4],
++		wlfc->stats.fifo_credits_back[5]);
++	{
++		uint32 fifo_cr_sent = 0;
++		uint32 fifo_cr_acked = 0;
++		uint32 request_cr_sent = 0;
++		uint32 request_cr_ack = 0;
++		uint32 bc_mc_cr_ack = 0;
++
++		for (i = 0; i < sizeof(wlfc->stats.fifo_credits_sent)/sizeof(uint32); i++) {
++			fifo_cr_sent += wlfc->stats.fifo_credits_sent[i];
++		}
++
++		for (i = 0; i < sizeof(wlfc->stats.fifo_credits_back)/sizeof(uint32); i++) {
++			fifo_cr_acked += wlfc->stats.fifo_credits_back[i];
++		}
++
++		for (i = 0; i < WLFC_MAC_DESC_TABLE_SIZE; i++) {
++			if (wlfc->destination_entries.nodes[i].occupied) {
++				request_cr_sent +=
++					wlfc->destination_entries.nodes[i].dstncredit_sent_packets;
++			}
++		}
++		for (i = 0; i < WLFC_MAX_IFNUM; i++) {
++			if (wlfc->destination_entries.interfaces[i].occupied) {
++				request_cr_sent +=
++				wlfc->destination_entries.interfaces[i].dstncredit_sent_packets;
++			}
++		}
++		for (i = 0; i < WLFC_MAC_DESC_TABLE_SIZE; i++) {
++			if (wlfc->destination_entries.nodes[i].occupied) {
++				request_cr_ack +=
++					wlfc->destination_entries.nodes[i].dstncredit_acks;
++			}
++		}
++		for (i = 0; i < WLFC_MAX_IFNUM; i++) {
++			if (wlfc->destination_entries.interfaces[i].occupied) {
++				request_cr_ack +=
++					wlfc->destination_entries.interfaces[i].dstncredit_acks;
++			}
++		}
++		bcm_bprintf(strbuf, "wlfc- (sent, status) => pq(%d,%d), vq(%d,%d),"
++			"other:%d, bc_mc:%d, signal-only, (sent,freed): (%d,%d)",
++			fifo_cr_sent, fifo_cr_acked,
++			request_cr_sent, request_cr_ack,
++			wlfc->destination_entries.other.dstncredit_acks,
++			bc_mc_cr_ack,
++			wlfc->stats.signal_only_pkts_sent, wlfc->stats.signal_only_pkts_freed);
++	}
++#endif /* PROP_TXSTATUS_DEBUG */
++	bcm_bprintf(strbuf, "\n");
++	bcm_bprintf(strbuf, "wlfc- pkt((in,2bus,txstats,hdrpull,out),(dropped,hdr_only,wlc_tossed)"
++		"(freed,free_err,rollback)) = "
++		"((%d,%d,%d,%d,%d),(%d,%d,%d),(%d,%d,%d))\n",
++		wlfc->stats.pktin,
++		wlfc->stats.pkt2bus,
++		wlfc->stats.txstatus_in,
++		wlfc->stats.dhd_hdrpulls,
++		wlfc->stats.pktout,
++
++		wlfc->stats.pktdropped,
++		wlfc->stats.wlfc_header_only_pkt,
++		wlfc->stats.wlc_tossed_pkts,
++
++		wlfc->stats.pkt_freed,
++		wlfc->stats.pkt_free_err, wlfc->stats.rollback);
++
++	bcm_bprintf(strbuf, "wlfc- suppress((d11,wlc,err),enq(d11,wl,hq,mac?),retx(d11,wlc,hq)) = "
++		"((%d,%d,%d),(%d,%d,%d,%d),(%d,%d,%d))\n",
++		wlfc->stats.d11_suppress,
++		wlfc->stats.wl_suppress,
++		wlfc->stats.bad_suppress,
++
++		wlfc->stats.psq_d11sup_enq,
++		wlfc->stats.psq_wlsup_enq,
++		wlfc->stats.psq_hostq_enq,
++		wlfc->stats.mac_handle_notfound,
++
++		wlfc->stats.psq_d11sup_retx,
++		wlfc->stats.psq_wlsup_retx,
++		wlfc->stats.psq_hostq_retx);
++
++	bcm_bprintf(strbuf, "wlfc- cleanup(txq,psq,fw) = (%d,%d,%d)\n",
++		wlfc->stats.cleanup_txq_cnt,
++		wlfc->stats.cleanup_psq_cnt,
++		wlfc->stats.cleanup_fw_cnt);
++
++	bcm_bprintf(strbuf, "wlfc- generic error: %d\n", wlfc->stats.generic_error);
++
++	for (i = 0; i < WLFC_MAX_IFNUM; i++) {
++		bcm_bprintf(strbuf, "wlfc- if[%d], pkt_cnt_in_q/AC[0-4] = (%d,%d,%d,%d,%d)\n", i,
++			wlfc->pkt_cnt_in_q[i][0],
++			wlfc->pkt_cnt_in_q[i][1],
++			wlfc->pkt_cnt_in_q[i][2],
++			wlfc->pkt_cnt_in_q[i][3],
++			wlfc->pkt_cnt_in_q[i][4]);
++	}
++	bcm_bprintf(strbuf, "\n");
++
++	dhd_os_wlfc_unblock(dhdp);
++	return BCME_OK;
++} /* dhd_wlfc_dump */
++
++int dhd_wlfc_clear_counts(dhd_pub_t *dhd)
++{
++	athost_wl_status_info_t* wlfc;
++	wlfc_hanger_t* hanger;
++
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhd);
++		return WLFC_UNSUPPORTED;
++	}
++
++	wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++
++	memset(&wlfc->stats, 0, sizeof(athost_wl_stat_counters_t));
++
++	if (!WLFC_GET_AFQ(dhd->wlfc_mode)) {
++		hanger = (wlfc_hanger_t*)wlfc->hanger;
++
++		hanger->pushed = 0;
++		hanger->popped = 0;
++		hanger->failed_slotfind = 0;
++		hanger->failed_to_pop = 0;
++		hanger->failed_to_push = 0;
++	}
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** returns TRUE if flow control is enabled */
++int dhd_wlfc_get_enable(dhd_pub_t *dhd, bool *val)
++{
++	if (!dhd || !val) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	*val = dhd->wlfc_enabled;
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** Called via an IOVAR */
++int dhd_wlfc_get_mode(dhd_pub_t *dhd, int *val)
++{
++	if (!dhd || !val) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	*val = dhd->wlfc_state ? dhd->proptxstatus_mode : 0;
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** Called via an IOVAR */
++int dhd_wlfc_set_mode(dhd_pub_t *dhd, int val)
++{
++	if (!dhd) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (dhd->wlfc_state) {
++		dhd->proptxstatus_mode = val & 0xff;
++	}
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** Called when rx frame is received from the dongle */
++bool dhd_wlfc_is_header_only_pkt(dhd_pub_t * dhd, void *pktbuf)
++{
++	athost_wl_status_info_t* wlfc;
++	bool rc = FALSE;
++
++	if (dhd == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return FALSE;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhd);
++		return FALSE;
++	}
++
++	wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++
++	if (PKTLEN(wlfc->osh, pktbuf) == 0) {
++		wlfc->stats.wlfc_header_only_pkt++;
++		rc = TRUE;
++	}
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return rc;
++}
++
++int dhd_wlfc_flowcontrol(dhd_pub_t *dhdp, bool state, bool bAcquireLock)
++{
++	if (dhdp == NULL) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	if (bAcquireLock) {
++		dhd_os_wlfc_block(dhdp);
++	}
++
++	if (!dhdp->wlfc_state || (dhdp->proptxstatus_mode == WLFC_FCMODE_NONE) ||
++		dhdp->proptxstatus_module_ignore) {
++		if (bAcquireLock) {
++			dhd_os_wlfc_unblock(dhdp);
++		}
++		return WLFC_UNSUPPORTED;
++	}
++
++	if (state != dhdp->proptxstatus_txoff) {
++		dhdp->proptxstatus_txoff = state;
++	}
++
++	if (bAcquireLock) {
++		dhd_os_wlfc_unblock(dhdp);
++	}
++
++#if defined(DHD_WLFC_THREAD)
++	_dhd_wlfc_thread_wakeup(dhd);
++#endif /* defined(DHD_WLFC_THREAD) */
++
++	return BCME_OK;
++}
++
++/** Called when eg an rx frame is received from the dongle */
++int dhd_wlfc_save_rxpath_ac_time(dhd_pub_t * dhd, uint8 prio)
++{
++	athost_wl_status_info_t* wlfc;
++	int rx_path_ac = -1;
++
++	if ((dhd == NULL) || (prio >= NUMPRIO)) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if (!dhd->wlfc_rxpkt_chk) {
++		dhd_os_wlfc_unblock(dhd);
++		return BCME_OK;
++	}
++
++	if (!dhd->wlfc_state || (dhd->proptxstatus_mode == WLFC_FCMODE_NONE)) {
++		dhd_os_wlfc_unblock(dhd);
++		return WLFC_UNSUPPORTED;
++	}
++
++	wlfc = (athost_wl_status_info_t*)dhd->wlfc_state;
++
++	rx_path_ac = prio2fifo[prio];
++	wlfc->rx_timestamp[rx_path_ac] = OSL_SYSUPTIME();
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** called via an IOVAR */
++int dhd_wlfc_get_module_ignore(dhd_pub_t *dhd, int *val)
++{
++	if (!dhd || !val) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	*val = dhd->proptxstatus_module_ignore;
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** called via an IOVAR */
++int dhd_wlfc_set_module_ignore(dhd_pub_t *dhd, int val)
++{
++	uint32 tlv = 0;
++	bool bChanged = FALSE;
++
++	if (!dhd) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	if ((bool)val != dhd->proptxstatus_module_ignore) {
++		dhd->proptxstatus_module_ignore = (val != 0);
++		/* force txstatus_ignore sync with proptxstatus_module_ignore */
++		dhd->proptxstatus_txstatus_ignore = dhd->proptxstatus_module_ignore;
++		if (FALSE == dhd->proptxstatus_module_ignore) {
++			tlv = WLFC_FLAGS_RSSI_SIGNALS |
++				WLFC_FLAGS_XONXOFF_SIGNALS |
++				WLFC_FLAGS_CREDIT_STATUS_SIGNALS |
++				WLFC_FLAGS_HOST_PROPTXSTATUS_ACTIVE;
++		}
++		/* always enable host reorder */
++		tlv |= WLFC_FLAGS_HOST_RXRERODER_ACTIVE;
++		bChanged = TRUE;
++	}
++
++	dhd_os_wlfc_unblock(dhd);
++
++	if (bChanged) {
++		/* select enable proptxtstatus signaling */
++		if (dhd_wl_ioctl_set_intiovar(dhd, "tlv", tlv, WLC_SET_VAR, TRUE, 0)) {
++			DHD_ERROR(("%s: failed to set bdcv2 tlv signaling to 0x%x\n",
++				__FUNCTION__, tlv));
++		} else {
++			DHD_ERROR(("%s: successfully set bdcv2 tlv signaling to 0x%x\n",
++				__FUNCTION__, tlv));
++		}
++	}
++	return BCME_OK;
++}
++
++/** called via an IOVAR */
++int dhd_wlfc_get_credit_ignore(dhd_pub_t *dhd, int *val)
++{
++	if (!dhd || !val) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	*val = dhd->proptxstatus_credit_ignore;
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** called via an IOVAR */
++int dhd_wlfc_set_credit_ignore(dhd_pub_t *dhd, int val)
++{
++	if (!dhd) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	dhd->proptxstatus_credit_ignore = (val != 0);
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** called via an IOVAR */
++int dhd_wlfc_get_txstatus_ignore(dhd_pub_t *dhd, int *val)
++{
++	if (!dhd || !val) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	*val = dhd->proptxstatus_txstatus_ignore;
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** called via an IOVAR */
++int dhd_wlfc_set_txstatus_ignore(dhd_pub_t *dhd, int val)
++{
++	if (!dhd) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	dhd->proptxstatus_txstatus_ignore = (val != 0);
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** called via an IOVAR */
++int dhd_wlfc_get_rxpkt_chk(dhd_pub_t *dhd, int *val)
++{
++	if (!dhd || !val) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	*val = dhd->wlfc_rxpkt_chk;
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++/** called via an IOVAR */
++int dhd_wlfc_set_rxpkt_chk(dhd_pub_t *dhd, int val)
++{
++	if (!dhd) {
++		DHD_ERROR(("Error: %s():%d\n", __FUNCTION__, __LINE__));
++		return BCME_BADARG;
++	}
++
++	dhd_os_wlfc_block(dhd);
++
++	dhd->wlfc_rxpkt_chk = (val != 0);
++
++	dhd_os_wlfc_unblock(dhd);
++
++	return BCME_OK;
++}
++
++#endif /* PROP_TXSTATUS */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_wlfc.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_wlfc.h
+new file mode 100644
+index 000000000..d5643fc4d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dhd_wlfc.h
+@@ -0,0 +1,562 @@
++/*
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dhd_wlfc.h 606400 2015-12-15 09:59:42Z $
++ *
++ */
++#ifndef __wlfc_host_driver_definitions_h__
++#define __wlfc_host_driver_definitions_h__
++
++
++/* #define OOO_DEBUG */
++
++#define KERNEL_THREAD_RETURN_TYPE int
++
++typedef int (*f_commitpkt_t)(void* ctx, void* p);
++typedef bool (*f_processpkt_t)(void* p, void* arg);
++
++#define WLFC_UNSUPPORTED -9999
++
++#define WLFC_NO_TRAFFIC	-1
++#define WLFC_MULTI_TRAFFIC 0
++
++#define BUS_RETRIES 1	/* # of retries before aborting a bus tx operation */
++
++/** 16 bits will provide an absolute max of 65536 slots */
++#define WLFC_HANGER_MAXITEMS 3072
++
++#define WLFC_HANGER_ITEM_STATE_FREE			1
++#define WLFC_HANGER_ITEM_STATE_INUSE			2
++#define WLFC_HANGER_ITEM_STATE_INUSE_SUPPRESSED		3
++#define WLFC_HANGER_ITEM_STATE_FLUSHED			4
++
++#define WLFC_HANGER_PKT_STATE_TXSTATUS			1
++#define WLFC_HANGER_PKT_STATE_BUSRETURNED		2
++#define WLFC_HANGER_PKT_STATE_COMPLETE			\
++	(WLFC_HANGER_PKT_STATE_TXSTATUS | WLFC_HANGER_PKT_STATE_BUSRETURNED)
++
++typedef enum {
++	Q_TYPE_PSQ, /**< Power Save Queue, contains both delayed and suppressed packets */
++	Q_TYPE_AFQ  /**< At Firmware Queue */
++} q_type_t;
++
++typedef enum ewlfc_packet_state {
++	eWLFC_PKTTYPE_NEW,        /**< unused in the code (Jan 2015) */
++	eWLFC_PKTTYPE_DELAYED,    /**< packet did not enter wlfc yet */
++	eWLFC_PKTTYPE_SUPPRESSED, /**< packet entered wlfc and was suppressed by the dongle */
++	eWLFC_PKTTYPE_MAX
++} ewlfc_packet_state_t;
++
++typedef enum ewlfc_mac_entry_action {
++	eWLFC_MAC_ENTRY_ACTION_ADD,
++	eWLFC_MAC_ENTRY_ACTION_DEL,
++	eWLFC_MAC_ENTRY_ACTION_UPDATE,
++	eWLFC_MAC_ENTRY_ACTION_MAX
++} ewlfc_mac_entry_action_t;
++
++typedef struct wlfc_hanger_item {
++	uint8	state;
++	uint8   gen;
++	uint8	pkt_state;     /**< bitmask containing eg WLFC_HANGER_PKT_STATE_TXCOMPLETE */
++	uint8	pkt_txstatus;
++	uint32	identifier;
++	void*	pkt;
++#ifdef PROP_TXSTATUS_DEBUG
++	uint32	push_time;
++#endif
++	struct wlfc_hanger_item *next;
++} wlfc_hanger_item_t;
++
++/** hanger contains packets that have been posted by the dhd to the dongle and are expected back */
++typedef struct wlfc_hanger {
++	int max_items;
++	uint32 pushed;
++	uint32 popped;
++	uint32 failed_to_push;
++	uint32 failed_to_pop;
++	uint32 failed_slotfind;
++	uint32 slot_pos;
++	wlfc_hanger_item_t items[1];
++} wlfc_hanger_t;
++
++#define WLFC_HANGER_SIZE(n)	((sizeof(wlfc_hanger_t) - \
++	sizeof(wlfc_hanger_item_t)) + ((n)*sizeof(wlfc_hanger_item_t)))
++
++#define WLFC_STATE_OPEN		1	/**< remote MAC is able to receive packets */
++#define WLFC_STATE_CLOSE	2	/**< remote MAC is in power save mode */
++
++#define WLFC_PSQ_PREC_COUNT		((AC_COUNT + 1) * 2) /**< 2 for each AC traffic and bc/mc */
++#define WLFC_AFQ_PREC_COUNT		(AC_COUNT + 1)
++
++#define WLFC_PSQ_LEN			2048
++
++#ifdef BCMDBUS
++#define WLFC_FLOWCONTROL_HIWATER	512
++#define WLFC_FLOWCONTROL_LOWATER	(WLFC_FLOWCONTROL_HIWATER / 4)
++#else
++#define WLFC_FLOWCONTROL_HIWATER	(2048 - 256)
++#define WLFC_FLOWCONTROL_LOWATER	256
++#endif
++
++#if (WLFC_FLOWCONTROL_HIWATER >= (WLFC_PSQ_LEN - 256))
++#undef WLFC_FLOWCONTROL_HIWATER
++#define WLFC_FLOWCONTROL_HIWATER	(WLFC_PSQ_LEN - 256)
++#undef WLFC_FLOWCONTROL_LOWATER
++#define WLFC_FLOWCONTROL_LOWATER	(WLFC_FLOWCONTROL_HIWATER / 4)
++#endif
++
++#define WLFC_LOG_BUF_SIZE		(1024*1024)
++
++/** Properties related to a remote MAC entity */
++typedef struct wlfc_mac_descriptor {
++	uint8 occupied;         /**< if 0, this descriptor is unused and thus can be (re)used */
++	uint8 interface_id;
++	uint8 iftype;           /**< eg WLC_E_IF_ROLE_STA */
++	uint8 state;            /**< eg WLFC_STATE_OPEN */
++	uint8 ac_bitmap;        /**< automatic power save delivery (APSD) */
++	uint8 requested_credit;
++	uint8 requested_packet; /**< unit: [number of packets] */
++	uint8 ea[ETHER_ADDR_LEN];
++
++	/** maintain (MAC,AC) based seq count for packets going to the device. As well as bc/mc. */
++	uint8 seq[AC_COUNT + 1];
++	uint8 generation;       /**< toggles between 0 and 1 */
++	struct pktq	psq;    /**< contains both 'delayed' and 'suppressed' packets */
++	/** packets at firmware queue */
++	struct pktq	afq;
++	/** The AC pending bitmap that was reported to the fw at last change */
++	uint8 traffic_lastreported_bmp;
++	/** The new AC pending bitmap */
++	uint8 traffic_pending_bmp;
++	/** 1= send on next opportunity */
++	uint8 send_tim_signal;
++	uint8 mac_handle;          /**< mac handles are assigned by the dongle */
++	/** Number of packets at dongle for this entry. */
++	int transit_count;
++	/** Number of suppression to wait before evict from delayQ */
++	int suppr_transit_count;
++	/** pkt sent to bus but no bus TX complete yet */
++	int onbus_pkts_count;
++	/** flag. TRUE when remote MAC is in suppressed state */
++	uint8 suppressed;
++
++
++#ifdef PROP_TXSTATUS_DEBUG
++	uint32 dstncredit_sent_packets;
++	uint32 dstncredit_acks;
++	uint32 opened_ct;
++	uint32 closed_ct;
++#endif
++	struct wlfc_mac_descriptor* prev;
++	struct wlfc_mac_descriptor* next;
++} wlfc_mac_descriptor_t;
++
++/** A 'commit' is the hand over of a packet from the host OS layer to the layer below (eg DBUS) */
++typedef struct dhd_wlfc_commit_info {
++	uint8					needs_hdr;
++	uint8					ac_fifo_credit_spent;
++	ewlfc_packet_state_t	pkt_type;
++	wlfc_mac_descriptor_t*	mac_entry;
++	void*					p;
++} dhd_wlfc_commit_info_t;
++
++#define WLFC_DECR_SEQCOUNT(entry, prec) do { if (entry->seq[(prec)] == 0) {\
++	entry->seq[prec] = 0xff; } else entry->seq[prec]--;} while (0)
++
++#define WLFC_INCR_SEQCOUNT(entry, prec) entry->seq[(prec)]++
++#define WLFC_SEQCOUNT(entry, prec) entry->seq[(prec)]
++
++typedef struct athost_wl_stat_counters {
++	uint32	pktin;
++	uint32	pktout;
++	uint32	pkt2bus;
++	uint32	pktdropped;
++	uint32	tlv_parse_failed;
++	uint32	rollback;
++	uint32	rollback_failed;
++	uint32	delayq_full_error;
++	uint32	credit_request_failed;
++	uint32	packet_request_failed;
++	uint32	mac_update_failed;
++	uint32	psmode_update_failed;
++	uint32	interface_update_failed;
++	uint32	wlfc_header_only_pkt;
++	uint32	txstatus_in;
++	uint32	d11_suppress;
++	uint32	wl_suppress;
++	uint32	bad_suppress;
++	uint32	pkt_freed;
++	uint32	pkt_free_err;
++	uint32	psq_wlsup_retx;
++	uint32	psq_wlsup_enq;
++	uint32	psq_d11sup_retx;
++	uint32	psq_d11sup_enq;
++	uint32	psq_hostq_retx;
++	uint32	psq_hostq_enq;
++	uint32	mac_handle_notfound;
++	uint32	wlc_tossed_pkts;
++	uint32	dhd_hdrpulls;
++	uint32	generic_error;
++	/* an extra one for bc/mc traffic */
++	uint32	send_pkts[AC_COUNT + 1];
++	uint32	drop_pkts[WLFC_PSQ_PREC_COUNT];
++	uint32	ooo_pkts[AC_COUNT + 1];
++#ifdef PROP_TXSTATUS_DEBUG
++	/** all pkt2bus -> txstatus latency accumulated */
++	uint32	latency_sample_count;
++	uint32	total_status_latency;
++	uint32	latency_most_recent;
++	int	idx_delta;
++	uint32	deltas[10];
++	uint32	fifo_credits_sent[6];
++	uint32	fifo_credits_back[6];
++	uint32	dropped_qfull[6];
++	uint32	signal_only_pkts_sent;
++	uint32	signal_only_pkts_freed;
++#endif
++	uint32	cleanup_txq_cnt;
++	uint32	cleanup_psq_cnt;
++	uint32	cleanup_fw_cnt;
++} athost_wl_stat_counters_t;
++
++#ifdef PROP_TXSTATUS_DEBUG
++#define WLFC_HOST_FIFO_CREDIT_INC_SENTCTRS(ctx, ac) do { \
++	(ctx)->stats.fifo_credits_sent[(ac)]++;} while (0)
++#define WLFC_HOST_FIFO_CREDIT_INC_BACKCTRS(ctx, ac) do { \
++	(ctx)->stats.fifo_credits_back[(ac)]++;} while (0)
++#define WLFC_HOST_FIFO_DROPPEDCTR_INC(ctx, ac) do { \
++	(ctx)->stats.dropped_qfull[(ac)]++;} while (0)
++#else
++#define WLFC_HOST_FIFO_CREDIT_INC_SENTCTRS(ctx, ac) do {} while (0)
++#define WLFC_HOST_FIFO_CREDIT_INC_BACKCTRS(ctx, ac) do {} while (0)
++#define WLFC_HOST_FIFO_DROPPEDCTR_INC(ctx, ac) do {} while (0)
++#endif
++
++#define WLFC_FCMODE_NONE				0
++#define WLFC_FCMODE_IMPLIED_CREDIT		1
++#define WLFC_FCMODE_EXPLICIT_CREDIT		2
++#define WLFC_ONLY_AMPDU_HOSTREORDER		3
++
++/** Reserved credits ratio when borrowed by hihger priority */
++#define WLFC_BORROW_LIMIT_RATIO		4
++
++/** How long to defer borrowing in milliseconds */
++#define WLFC_BORROW_DEFER_PERIOD_MS 100
++
++/** How long to defer flow control in milliseconds */
++#define WLFC_FC_DEFER_PERIOD_MS 200
++
++/** How long to detect occurance per AC in miliseconds */
++#define WLFC_RX_DETECTION_THRESHOLD_MS	100
++
++/** Mask to represent available ACs (note: BC/MC is ignored) */
++#define WLFC_AC_MASK 0xF
++
++/** flow control specific information, only 1 instance during driver lifetime */
++typedef struct athost_wl_status_info {
++	uint8	last_seqid_to_wlc;
++
++	/** OSL handle */
++	osl_t *osh;
++	/** dhd public struct pointer */
++	void *dhdp;
++
++	f_commitpkt_t fcommit;
++	void* commit_ctx;
++
++	/** statistics */
++	athost_wl_stat_counters_t stats;
++
++	/** incremented on eg receiving a credit map event from the dongle */
++	int		Init_FIFO_credit[AC_COUNT + 2];
++	/** the additional ones are for bc/mc and ATIM FIFO */
++	int		FIFO_credit[AC_COUNT + 2];
++	/** Credit borrow counts for each FIFO from each of the other FIFOs */
++	int		credits_borrowed[AC_COUNT + 2][AC_COUNT + 2];
++
++	/** packet hanger and MAC->handle lookup table */
++	void *hanger;
++
++	struct {
++		/** table for individual nodes */
++		wlfc_mac_descriptor_t	nodes[WLFC_MAC_DESC_TABLE_SIZE];
++		/** table for interfaces */
++		wlfc_mac_descriptor_t	interfaces[WLFC_MAX_IFNUM];
++		/* OS may send packets to unknown (unassociated) destinations */
++		/** A place holder for bc/mc and packets to unknown destinations */
++		wlfc_mac_descriptor_t	other;
++	} destination_entries;
++
++	wlfc_mac_descriptor_t *active_entry_head; /**< a chain of MAC descriptors */
++	int active_entry_count;
++
++	wlfc_mac_descriptor_t *requested_entry[WLFC_MAC_DESC_TABLE_SIZE];
++	int requested_entry_count;
++
++	/* pkt counts for each interface and ac */
++	int	pkt_cnt_in_q[WLFC_MAX_IFNUM][AC_COUNT+1];
++	int	pkt_cnt_per_ac[AC_COUNT+1];
++	int	pkt_cnt_in_drv[WLFC_MAX_IFNUM][AC_COUNT+1];
++	int	pkt_cnt_in_psq;
++	uint8	allow_fc;              /**< Boolean */
++	uint32  fc_defer_timestamp;
++	uint32	rx_timestamp[AC_COUNT+1];
++
++	/** ON/OFF state for flow control to the host network interface */
++	uint8	hostif_flow_state[WLFC_MAX_IFNUM];
++	uint8	host_ifidx;
++
++	/** to flow control an OS interface */
++	uint8	toggle_host_if;
++
++	/** To borrow credits */
++	uint8   allow_credit_borrow;
++
++	/** ac number for the first single ac traffic */
++	uint8	single_ac;
++
++	/** Timestamp for the first single ac traffic */
++	uint32  single_ac_timestamp;
++
++	bool	bcmc_credit_supported;
++
++} athost_wl_status_info_t;
++
++/** Please be mindful that total pkttag space is 32 octets only */
++typedef struct dhd_pkttag {
++
++#ifdef BCM_OBJECT_TRACE
++	/* if use this field, keep it at the first 4 bytes */
++	uint32 sn;
++#endif /* BCM_OBJECT_TRACE */
++
++	/**
++	b[15]  - 1 = wlfc packet
++	b[14:13]  - encryption exemption
++	b[12 ] - 1 = event channel
++	b[11 ] - 1 = this packet was sent in response to one time packet request,
++	do not increment credit on status for this one. [WLFC_CTL_TYPE_MAC_REQUEST_PACKET].
++	b[10 ] - 1 = signal-only-packet to firmware [i.e. nothing to piggyback on]
++	b[9  ] - 1 = packet is host->firmware (transmit direction)
++	       - 0 = packet received from firmware (firmware->host)
++	b[8  ] - 1 = packet was sent due to credit_request (pspoll),
++	             packet does not count against FIFO credit.
++	       - 0 = normal transaction, packet counts against FIFO credit
++	b[7  ] - 1 = AP, 0 = STA
++	b[6:4] - AC FIFO number
++	b[3:0] - interface index
++	*/
++	uint16	if_flags;
++
++	/**
++	 * destination MAC address for this packet so that not every module needs to open the packet
++	 * to find this
++	 */
++	uint8	dstn_ether[ETHER_ADDR_LEN];
++
++	/** This 32-bit goes from host to device for every packet. */
++	uint32	htod_tag;
++
++	/** This 16-bit is original seq number for every suppress packet. */
++	uint16	htod_seq;
++
++	/** This address is mac entry for every packet. */
++	void *entry;
++
++	/** bus specific stuff */
++	union {
++		struct {
++			void *stuff;
++			uint32 thing1;
++			uint32 thing2;
++		} sd;
++
++		struct {
++			void *bus;
++			void *urb;
++		} usb;
++	} bus_specific;
++} dhd_pkttag_t;
++
++#define DHD_PKTTAG_WLFCPKT_MASK			0x1
++#define DHD_PKTTAG_WLFCPKT_SHIFT		15
++#define DHD_PKTTAG_WLFCPKT_SET(tag, value)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & \
++	~(DHD_PKTTAG_WLFCPKT_MASK << DHD_PKTTAG_WLFCPKT_SHIFT)) | \
++	(((value) & DHD_PKTTAG_WLFCPKT_MASK) << DHD_PKTTAG_WLFCPKT_SHIFT)
++#define DHD_PKTTAG_WLFCPKT(tag)	((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_WLFCPKT_SHIFT) & DHD_PKTTAG_WLFCPKT_MASK)
++
++#define DHD_PKTTAG_EXEMPT_MASK			0x3
++#define DHD_PKTTAG_EXEMPT_SHIFT			13
++#define DHD_PKTTAG_EXEMPT_SET(tag, value)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & \
++	~(DHD_PKTTAG_EXEMPT_MASK << DHD_PKTTAG_EXEMPT_SHIFT)) | \
++	(((value) & DHD_PKTTAG_EXEMPT_MASK) << DHD_PKTTAG_EXEMPT_SHIFT)
++#define DHD_PKTTAG_EXEMPT(tag)	((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_EXEMPT_SHIFT) & DHD_PKTTAG_EXEMPT_MASK)
++
++#define DHD_PKTTAG_EVENT_MASK			0x1
++#define DHD_PKTTAG_EVENT_SHIFT			12
++#define DHD_PKTTAG_SETEVENT(tag, event)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & \
++	~(DHD_PKTTAG_EVENT_MASK << DHD_PKTTAG_EVENT_SHIFT)) | \
++	(((event) & DHD_PKTTAG_EVENT_MASK) << DHD_PKTTAG_EVENT_SHIFT)
++#define DHD_PKTTAG_EVENT(tag)	((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_EVENT_SHIFT) & DHD_PKTTAG_EVENT_MASK)
++
++#define DHD_PKTTAG_ONETIMEPKTRQST_MASK		0x1
++#define DHD_PKTTAG_ONETIMEPKTRQST_SHIFT		11
++#define DHD_PKTTAG_SETONETIMEPKTRQST(tag)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & \
++	~(DHD_PKTTAG_ONETIMEPKTRQST_MASK << DHD_PKTTAG_ONETIMEPKTRQST_SHIFT)) | \
++	(1 << DHD_PKTTAG_ONETIMEPKTRQST_SHIFT)
++#define DHD_PKTTAG_ONETIMEPKTRQST(tag)	((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_ONETIMEPKTRQST_SHIFT) & DHD_PKTTAG_ONETIMEPKTRQST_MASK)
++
++#define DHD_PKTTAG_SIGNALONLY_MASK		0x1
++#define DHD_PKTTAG_SIGNALONLY_SHIFT		10
++#define DHD_PKTTAG_SETSIGNALONLY(tag, signalonly)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & \
++	~(DHD_PKTTAG_SIGNALONLY_MASK << DHD_PKTTAG_SIGNALONLY_SHIFT)) | \
++	(((signalonly) & DHD_PKTTAG_SIGNALONLY_MASK) << DHD_PKTTAG_SIGNALONLY_SHIFT)
++#define DHD_PKTTAG_SIGNALONLY(tag)	((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_SIGNALONLY_SHIFT) & DHD_PKTTAG_SIGNALONLY_MASK)
++
++#define DHD_PKTTAG_PKTDIR_MASK			0x1
++#define DHD_PKTTAG_PKTDIR_SHIFT			9
++#define DHD_PKTTAG_SETPKTDIR(tag, dir)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & \
++	~(DHD_PKTTAG_PKTDIR_MASK << DHD_PKTTAG_PKTDIR_SHIFT)) | \
++	(((dir) & DHD_PKTTAG_PKTDIR_MASK) << DHD_PKTTAG_PKTDIR_SHIFT)
++#define DHD_PKTTAG_PKTDIR(tag)	((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_PKTDIR_SHIFT) & DHD_PKTTAG_PKTDIR_MASK)
++
++#define DHD_PKTTAG_CREDITCHECK_MASK		0x1
++#define DHD_PKTTAG_CREDITCHECK_SHIFT		8
++#define DHD_PKTTAG_SETCREDITCHECK(tag, check)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & \
++	~(DHD_PKTTAG_CREDITCHECK_MASK << DHD_PKTTAG_CREDITCHECK_SHIFT)) | \
++	(((check) & DHD_PKTTAG_CREDITCHECK_MASK) << DHD_PKTTAG_CREDITCHECK_SHIFT)
++#define DHD_PKTTAG_CREDITCHECK(tag)	((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_CREDITCHECK_SHIFT) & DHD_PKTTAG_CREDITCHECK_MASK)
++
++#define DHD_PKTTAG_IFTYPE_MASK			0x1
++#define DHD_PKTTAG_IFTYPE_SHIFT			7
++#define DHD_PKTTAG_SETIFTYPE(tag, isAP)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & \
++	~(DHD_PKTTAG_IFTYPE_MASK << DHD_PKTTAG_IFTYPE_SHIFT)) | \
++	(((isAP) & DHD_PKTTAG_IFTYPE_MASK) << DHD_PKTTAG_IFTYPE_SHIFT)
++#define DHD_PKTTAG_IFTYPE(tag)	((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_IFTYPE_SHIFT) & DHD_PKTTAG_IFTYPE_MASK)
++
++#define DHD_PKTTAG_FIFO_MASK			0x7
++#define DHD_PKTTAG_FIFO_SHIFT			4
++#define DHD_PKTTAG_SETFIFO(tag, fifo)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & ~(DHD_PKTTAG_FIFO_MASK << DHD_PKTTAG_FIFO_SHIFT)) | \
++	(((fifo) & DHD_PKTTAG_FIFO_MASK) << DHD_PKTTAG_FIFO_SHIFT)
++#define DHD_PKTTAG_FIFO(tag)		((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_FIFO_SHIFT) & DHD_PKTTAG_FIFO_MASK)
++
++#define DHD_PKTTAG_IF_MASK			0xf
++#define DHD_PKTTAG_IF_SHIFT			0
++#define DHD_PKTTAG_SETIF(tag, if)	((dhd_pkttag_t*)(tag))->if_flags = \
++	(((dhd_pkttag_t*)(tag))->if_flags & ~(DHD_PKTTAG_IF_MASK << DHD_PKTTAG_IF_SHIFT)) | \
++	(((if) & DHD_PKTTAG_IF_MASK) << DHD_PKTTAG_IF_SHIFT)
++#define DHD_PKTTAG_IF(tag)		((((dhd_pkttag_t*)(tag))->if_flags >> \
++	DHD_PKTTAG_IF_SHIFT) & DHD_PKTTAG_IF_MASK)
++
++#define DHD_PKTTAG_SETDSTN(tag, dstn_MAC_ea)	memcpy(((dhd_pkttag_t*)((tag)))->dstn_ether, \
++	(dstn_MAC_ea), ETHER_ADDR_LEN)
++#define DHD_PKTTAG_DSTN(tag)	((dhd_pkttag_t*)(tag))->dstn_ether
++
++#define DHD_PKTTAG_SET_H2DTAG(tag, h2dvalue)	((dhd_pkttag_t*)(tag))->htod_tag = (h2dvalue)
++#define DHD_PKTTAG_H2DTAG(tag)			(((dhd_pkttag_t*)(tag))->htod_tag)
++
++#define DHD_PKTTAG_SET_H2DSEQ(tag, seq)		((dhd_pkttag_t*)(tag))->htod_seq = (seq)
++#define DHD_PKTTAG_H2DSEQ(tag)			(((dhd_pkttag_t*)(tag))->htod_seq)
++
++#define DHD_PKTTAG_SET_ENTRY(tag, entry)	((dhd_pkttag_t*)(tag))->entry = (entry)
++#define DHD_PKTTAG_ENTRY(tag)			(((dhd_pkttag_t*)(tag))->entry)
++
++#define PSQ_SUP_IDX(x) (x * 2 + 1)
++#define PSQ_DLY_IDX(x) (x * 2)
++
++#ifdef PROP_TXSTATUS_DEBUG
++#define DHD_WLFC_CTRINC_MAC_CLOSE(entry)	do { (entry)->closed_ct++; } while (0)
++#define DHD_WLFC_CTRINC_MAC_OPEN(entry)		do { (entry)->opened_ct++; } while (0)
++#else
++#define DHD_WLFC_CTRINC_MAC_CLOSE(entry)	do {} while (0)
++#define DHD_WLFC_CTRINC_MAC_OPEN(entry)		do {} while (0)
++#endif
++
++#ifdef BCM_OBJECT_TRACE
++#define DHD_PKTTAG_SET_SN(tag, val)		((dhd_pkttag_t*)(tag))->sn = (val)
++#define DHD_PKTTAG_SN(tag)			(((dhd_pkttag_t*)(tag))->sn)
++#endif /* BCM_OBJECT_TRACE */
++
++/* public functions */
++int dhd_wlfc_parse_header_info(dhd_pub_t *dhd, void* pktbuf, int tlv_hdr_len,
++	uchar *reorder_info_buf, uint *reorder_info_len);
++KERNEL_THREAD_RETURN_TYPE dhd_wlfc_transfer_packets(void *data);
++int dhd_wlfc_commit_packets(dhd_pub_t *dhdp, f_commitpkt_t fcommit,
++	void* commit_ctx, void *pktbuf, bool need_toggle_host_if);
++int dhd_wlfc_txcomplete(dhd_pub_t *dhd, void *txp, bool success);
++int dhd_wlfc_init(dhd_pub_t *dhd);
++#ifdef SUPPORT_P2P_GO_PS
++int dhd_wlfc_suspend(dhd_pub_t *dhd);
++int dhd_wlfc_resume(dhd_pub_t *dhd);
++#endif /* SUPPORT_P2P_GO_PS */
++int dhd_wlfc_hostreorder_init(dhd_pub_t *dhd);
++int dhd_wlfc_cleanup_txq(dhd_pub_t *dhd, f_processpkt_t fn, void *arg);
++int dhd_wlfc_cleanup(dhd_pub_t *dhd, f_processpkt_t fn, void* arg);
++int dhd_wlfc_deinit(dhd_pub_t *dhd);
++int dhd_wlfc_interface_event(dhd_pub_t *dhdp, uint8 action, uint8 ifid, uint8 iftype, uint8* ea);
++int dhd_wlfc_FIFOcreditmap_event(dhd_pub_t *dhdp, uint8* event_data);
++#ifdef LIMIT_BORROW
++int dhd_wlfc_disable_credit_borrow_event(dhd_pub_t *dhdp, uint8* event_data);
++#endif /* LIMIT_BORROW */
++int dhd_wlfc_BCMCCredit_support_event(dhd_pub_t *dhdp);
++int dhd_wlfc_enable(dhd_pub_t *dhdp);
++int dhd_wlfc_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf);
++int dhd_wlfc_clear_counts(dhd_pub_t *dhd);
++int dhd_wlfc_get_enable(dhd_pub_t *dhd, bool *val);
++int dhd_wlfc_get_mode(dhd_pub_t *dhd, int *val);
++int dhd_wlfc_set_mode(dhd_pub_t *dhd, int val);
++bool dhd_wlfc_is_supported(dhd_pub_t *dhd);
++bool dhd_wlfc_is_header_only_pkt(dhd_pub_t * dhd, void *pktbuf);
++int dhd_wlfc_flowcontrol(dhd_pub_t *dhdp, bool state, bool bAcquireLock);
++int dhd_wlfc_save_rxpath_ac_time(dhd_pub_t * dhd, uint8 prio);
++
++int dhd_wlfc_get_module_ignore(dhd_pub_t *dhd, int *val);
++int dhd_wlfc_set_module_ignore(dhd_pub_t *dhd, int val);
++int dhd_wlfc_get_credit_ignore(dhd_pub_t *dhd, int *val);
++int dhd_wlfc_set_credit_ignore(dhd_pub_t *dhd, int val);
++int dhd_wlfc_get_txstatus_ignore(dhd_pub_t *dhd, int *val);
++int dhd_wlfc_set_txstatus_ignore(dhd_pub_t *dhd, int val);
++
++int dhd_wlfc_get_rxpkt_chk(dhd_pub_t *dhd, int *val);
++int dhd_wlfc_set_rxpkt_chk(dhd_pub_t *dhd, int val);
++
++#endif /* __wlfc_host_driver_definitions_h__ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dngl_stats.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dngl_stats.h
+new file mode 100644
+index 000000000..4c7aac1c5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dngl_stats.h
+@@ -0,0 +1,285 @@
++/*
++ * Common stats definitions for clients of dongle
++ * ports
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dngl_stats.h 598879 2015-11-11 09:05:57Z $
++ */
++
++#ifndef _dngl_stats_h_
++#define _dngl_stats_h_
++
++#include <proto/ethernet.h>
++#include <proto/802.11.h>
++
++typedef struct {
++	unsigned long	rx_packets;		/* total packets received */
++	unsigned long	tx_packets;		/* total packets transmitted */
++	unsigned long	rx_bytes;		/* total bytes received */
++	unsigned long	tx_bytes;		/* total bytes transmitted */
++	unsigned long	rx_errors;		/* bad packets received */
++	unsigned long	tx_errors;		/* packet transmit problems */
++	unsigned long	rx_dropped;		/* packets dropped by dongle */
++	unsigned long	tx_dropped;		/* packets dropped by dongle */
++	unsigned long   multicast;      /* multicast packets received */
++} dngl_stats_t;
++
++#ifdef LINKSTAT_SUPPORT
++typedef int32 wifi_radio;
++typedef int32 wifi_channel;
++typedef int32 wifi_rssi;
++typedef struct { uint16 version; uint16 length; } ver_len;
++
++typedef enum wifi_channel_width {
++	WIFI_CHAN_WIDTH_20	  = 0,
++	WIFI_CHAN_WIDTH_40	  = 1,
++	WIFI_CHAN_WIDTH_80	  = 2,
++	WIFI_CHAN_WIDTH_160   = 3,
++	WIFI_CHAN_WIDTH_80P80 = 4,
++	WIFI_CHAN_WIDTH_5	  = 5,
++	WIFI_CHAN_WIDTH_10	  = 6,
++	WIFI_CHAN_WIDTH_INVALID = -1
++} wifi_channel_width_t;
++
++typedef enum {
++	WIFI_DISCONNECTED = 0,
++	WIFI_AUTHENTICATING = 1,
++	WIFI_ASSOCIATING = 2,
++	WIFI_ASSOCIATED = 3,
++	WIFI_EAPOL_STARTED = 4,   /* if done by firmware/driver */
++	WIFI_EAPOL_COMPLETED = 5, /* if done by firmware/driver */
++} wifi_connection_state;
++
++typedef enum {
++	WIFI_ROAMING_IDLE = 0,
++	WIFI_ROAMING_ACTIVE = 1
++} wifi_roam_state;
++
++typedef enum {
++	WIFI_INTERFACE_STA = 0,
++	WIFI_INTERFACE_SOFTAP = 1,
++	WIFI_INTERFACE_IBSS = 2,
++	WIFI_INTERFACE_P2P_CLIENT = 3,
++	WIFI_INTERFACE_P2P_GO = 4,
++	WIFI_INTERFACE_NAN = 5,
++	WIFI_INTERFACE_MESH = 6
++} wifi_interface_mode;
++
++#define WIFI_CAPABILITY_QOS          0x00000001     /* set for QOS association */
++#define WIFI_CAPABILITY_PROTECTED    0x00000002     /* set for protected association (802.11
++						     * beacon frame control protected bit set)
++						     */
++#define WIFI_CAPABILITY_INTERWORKING 0x00000004     /* set if 802.11 Extended Capabilities
++						     * element interworking bit is set
++						     */
++#define WIFI_CAPABILITY_HS20         0x00000008     /* set for HS20 association */
++#define WIFI_CAPABILITY_SSID_UTF8    0x00000010     /* set is 802.11 Extended Capabilities
++						     * element UTF-8 SSID bit is set
++						     */
++#define WIFI_CAPABILITY_COUNTRY      0x00000020     /* set is 802.11 Country Element is present */
++
++typedef struct {
++	wifi_interface_mode mode;     /* interface mode */
++	uint8 mac_addr[6];               /* interface mac address (self) */
++	wifi_connection_state state;  /* connection state (valid for STA, CLI only) */
++	wifi_roam_state roaming;      /* roaming state */
++	uint32 capabilities;             /* WIFI_CAPABILITY_XXX (self) */
++	uint8 ssid[DOT11_MAX_SSID_LEN+1]; /* null terminated SSID */
++	uint8 bssid[ETHER_ADDR_LEN];     /* bssid */
++	uint8 ap_country_str[3];         /* country string advertised by AP */
++	uint8 country_str[3];            /* country string for this association */
++} wifi_interface_info;
++
++typedef wifi_interface_info *wifi_interface_handle;
++
++/* channel information */
++typedef struct {
++	wifi_channel_width_t width;   /* channel width (20, 40, 80, 80+80, 160) */
++	wifi_channel center_freq;   /* primary 20 MHz channel */
++	wifi_channel center_freq0;  /* center frequency (MHz) first segment */
++	wifi_channel center_freq1;  /* center frequency (MHz) second segment */
++} wifi_channel_info;
++
++/* wifi rate */
++typedef struct {
++	uint32 preamble;   /* 0: OFDM, 1:CCK, 2:HT 3:VHT 4..7 reserved */
++	uint32 nss;   	/* 0:1x1, 1:2x2, 3:3x3, 4:4x4 */
++	uint32 bw;   	/* 0:20MHz, 1:40Mhz, 2:80Mhz, 3:160Mhz */
++	uint32 rateMcsIdx; /* OFDM/CCK rate code would be as per ieee std
++			    * in the units of 0.5mbps
++			    */
++			/* HT/VHT it would be mcs index */
++	uint32 reserved;   /* reserved */
++	uint32 bitrate;    /* units of 100 Kbps */
++} wifi_rate;
++
++/* channel statistics */
++typedef struct {
++	wifi_channel_info channel;  /* channel */
++	uint32 on_time;         	/* msecs the radio is awake (32 bits number
++				         * accruing over time)
++					 */
++	uint32 cca_busy_time;          /* msecs the CCA register is busy (32 bits number
++					* accruing over time)
++					*/
++} wifi_channel_stat;
++
++/* radio statistics */
++typedef struct {
++	struct {
++		uint16 version;
++		uint16 length;
++	};
++	wifi_radio radio;               /* wifi radio (if multiple radio supported) */
++	uint32 on_time;                    /* msecs the radio is awake (32 bits number
++					    * accruing over time)
++					    */
++	uint32 tx_time;                    /* msecs the radio is transmitting (32 bits
++					    * number accruing over time)
++					    */
++	uint32 rx_time;                    /* msecs the radio is in active receive (32 bits
++					    * number accruing over time)
++					    */
++	uint32 on_time_scan;               /* msecs the radio is awake due to all scan (32 bits
++					    * number accruing over time)
++					    */
++	uint32 on_time_nbd;                /* msecs the radio is awake due to NAN (32 bits
++					    * number accruing over time)
++					    */
++	uint32 on_time_gscan;              /* msecs the radio is awake due to G?scan (32 bits
++					    * number accruing over time)
++					    */
++	uint32 on_time_roam_scan;          /* msecs the radio is awake due to roam?scan (32 bits
++					    * number accruing over time)
++					    */
++	uint32 on_time_pno_scan;           /* msecs the radio is awake due to PNO scan (32 bits
++					    * number accruing over time)
++					    */
++	uint32 on_time_hs20;               /* msecs the radio is awake due to HS2.0 scans and
++					    * GAS exchange (32 bits number accruing over time)
++					    */
++	uint32 num_channels;               /* number of channels */
++	wifi_channel_stat channels[1];   /* channel statistics */
++} wifi_radio_stat;
++
++/* per rate statistics */
++typedef struct {
++	struct {
++		uint16 version;
++		uint16 length;
++	};
++	uint32 tx_mpdu;        /* number of successfully transmitted data pkts (ACK rcvd) */
++	uint32 rx_mpdu;        /* number of received data pkts */
++	uint32 mpdu_lost;      /* number of data packet losses (no ACK) */
++	uint32 retries;        /* total number of data pkt retries */
++	uint32 retries_short;  /* number of short data pkt retries */
++	uint32 retries_long;   /* number of long data pkt retries */
++	wifi_rate rate;     /* rate information */
++} wifi_rate_stat;
++
++/* access categories */
++typedef enum {
++	WIFI_AC_VO  = 0,
++	WIFI_AC_VI  = 1,
++	WIFI_AC_BE  = 2,
++	WIFI_AC_BK  = 3,
++	WIFI_AC_MAX = 4
++} wifi_traffic_ac;
++
++/* wifi peer type */
++typedef enum
++{
++	WIFI_PEER_STA,
++	WIFI_PEER_AP,
++	WIFI_PEER_P2P_GO,
++	WIFI_PEER_P2P_CLIENT,
++	WIFI_PEER_NAN,
++	WIFI_PEER_TDLS,
++	WIFI_PEER_INVALID
++} wifi_peer_type;
++
++/* per peer statistics */
++typedef struct {
++	wifi_peer_type type;           /* peer type (AP, TDLS, GO etc.) */
++	uint8 peer_mac_address[6];        /* mac address */
++	uint32 capabilities;              /* peer WIFI_CAPABILITY_XXX */
++	uint32 num_rate;                  /* number of rates */
++	wifi_rate_stat rate_stats[1];   /* per rate statistics, number of entries  = num_rate */
++} wifi_peer_info;
++
++/* per access category statistics */
++typedef struct {
++	wifi_traffic_ac ac;             /* access category (VI, VO, BE, BK) */
++	uint32 tx_mpdu;                    /* number of successfully transmitted unicast data pkts
++					    * (ACK rcvd)
++					    */
++	uint32 rx_mpdu;                    /* number of received unicast mpdus */
++	uint32 tx_mcast;                   /* number of succesfully transmitted multicast
++					    * data packets
++					    */
++					   /* STA case: implies ACK received from AP for the
++					    * unicast packet in which mcast pkt was sent
++					    */
++	uint32 rx_mcast;                   /* number of received multicast data packets */
++	uint32 rx_ampdu;                   /* number of received unicast a-mpdus */
++	uint32 tx_ampdu;                   /* number of transmitted unicast a-mpdus */
++	uint32 mpdu_lost;                  /* number of data pkt losses (no ACK) */
++	uint32 retries;                    /* total number of data pkt retries */
++	uint32 retries_short;              /* number of short data pkt retries */
++	uint32 retries_long;               /* number of long data pkt retries */
++	uint32 contention_time_min;        /* data pkt min contention time (usecs) */
++	uint32 contention_time_max;        /* data pkt max contention time (usecs) */
++	uint32 contention_time_avg;        /* data pkt avg contention time (usecs) */
++	uint32 contention_num_samples;     /* num of data pkts used for contention statistics */
++} wifi_wmm_ac_stat;
++
++/* interface statistics */
++typedef struct {
++	wifi_interface_handle iface;          /* wifi interface */
++	wifi_interface_info info;             /* current state of the interface */
++	uint32 beacon_rx;                     /* access point beacon received count from
++					       * connected AP
++					       */
++	uint32 mgmt_rx;                       /* access point mgmt frames received count from
++					       * connected AP (including Beacon)
++					       */
++	uint32 mgmt_action_rx;                /* action frames received count */
++	uint32 mgmt_action_tx;                /* action frames transmit count */
++	wifi_rssi rssi_mgmt;                  /* access Point Beacon and Management frames RSSI
++					       * (averaged)
++					       */
++	wifi_rssi rssi_data;                  /* access Point Data Frames RSSI (averaged) from
++					       * connected AP
++					       */
++	wifi_rssi rssi_ack;                   /* access Point ACK RSSI (averaged) from
++					       * connected AP
++					       */
++	wifi_wmm_ac_stat ac[WIFI_AC_MAX];     /* per ac data packet statistics */
++	uint32 num_peers;                        /* number of peers */
++	wifi_peer_info peer_info[1];           /* per peer statistics */
++} wifi_iface_stat;
++#endif /* LINKSTAT_SUPPORT */
++
++#endif /* _dngl_stats_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dngl_wlhdr.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dngl_wlhdr.h
+new file mode 100644
+index 000000000..0cdcd670e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/dngl_wlhdr.h
+@@ -0,0 +1,43 @@
++/*
++ * Dongle WL Header definitions
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: dngl_wlhdr.h 514727 2014-11-12 03:02:48Z $
++ */
++
++#ifndef _dngl_wlhdr_h_
++#define _dngl_wlhdr_h_
++
++typedef struct wl_header {
++    uint8   type;           /* Header type */
++    uint8   version;        /* Header version */
++	int8	rssi;			/* RSSI */
++	uint8	pad;			/* Unused */
++} wl_header_t;
++
++#define WL_HEADER_LEN   sizeof(wl_header_t)
++#define WL_HEADER_TYPE  0
++#define WL_HEADER_VER   1
++#endif /* _dngl_wlhdr_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/hnd_pktpool.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/hnd_pktpool.c
+new file mode 100644
+index 000000000..04f591a16
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/hnd_pktpool.c
+@@ -0,0 +1,1131 @@
++/*
++ * HND generic packet pool operation primitives
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: $
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++#include <osl_ext.h>
++#include <bcmutils.h>
++#include <hnd_pktpool.h>
++
++/* mutex macros for thread safe */
++#ifdef HND_PKTPOOL_THREAD_SAFE
++#define HND_PKTPOOL_MUTEX_CREATE(name, mutex)	osl_ext_mutex_create(name, mutex)
++#define HND_PKTPOOL_MUTEX_DELETE(mutex)		osl_ext_mutex_delete(mutex)
++#define HND_PKTPOOL_MUTEX_ACQUIRE(mutex, msec)	osl_ext_mutex_acquire(mutex, msec)
++#define HND_PKTPOOL_MUTEX_RELEASE(mutex)	osl_ext_mutex_release(mutex)
++#else
++#define HND_PKTPOOL_MUTEX_CREATE(name, mutex)	OSL_EXT_SUCCESS
++#define HND_PKTPOOL_MUTEX_DELETE(mutex)		OSL_EXT_SUCCESS
++#define HND_PKTPOOL_MUTEX_ACQUIRE(mutex, msec)	OSL_EXT_SUCCESS
++#define HND_PKTPOOL_MUTEX_RELEASE(mutex)	OSL_EXT_SUCCESS
++#endif
++
++/* Registry size is one larger than max pools, as slot #0 is reserved */
++#define PKTPOOLREG_RSVD_ID				(0U)
++#define PKTPOOLREG_RSVD_PTR				(POOLPTR(0xdeaddead))
++#define PKTPOOLREG_FREE_PTR				(POOLPTR(NULL))
++
++#define PKTPOOL_REGISTRY_SET(id, pp)	(pktpool_registry_set((id), (pp)))
++#define PKTPOOL_REGISTRY_CMP(id, pp)	(pktpool_registry_cmp((id), (pp)))
++
++/* Tag a registry entry as free for use */
++#define PKTPOOL_REGISTRY_CLR(id)		\
++		PKTPOOL_REGISTRY_SET((id), PKTPOOLREG_FREE_PTR)
++#define PKTPOOL_REGISTRY_ISCLR(id)		\
++		(PKTPOOL_REGISTRY_CMP((id), PKTPOOLREG_FREE_PTR))
++
++/* Tag registry entry 0 as reserved */
++#define PKTPOOL_REGISTRY_RSV()			\
++		PKTPOOL_REGISTRY_SET(PKTPOOLREG_RSVD_ID, PKTPOOLREG_RSVD_PTR)
++#define PKTPOOL_REGISTRY_ISRSVD()		\
++		(PKTPOOL_REGISTRY_CMP(PKTPOOLREG_RSVD_ID, PKTPOOLREG_RSVD_PTR))
++
++/* Walk all un-reserved entries in registry */
++#define PKTPOOL_REGISTRY_FOREACH(id)	\
++		for ((id) = 1U; (id) <= pktpools_max; (id)++)
++
++enum pktpool_empty_cb_state {
++	EMPTYCB_ENABLED = 0,	/* Enable callback when new packets are added to pool */
++	EMPTYCB_DISABLED,	/* Disable callback when new packets are added to pool */
++	EMPTYCB_SKIPPED		/* Packet was added to pool when callback was disabled */
++};
++
++uint32 pktpools_max = 0U; /* maximum number of pools that may be initialized */
++pktpool_t *pktpools_registry[PKTPOOL_MAXIMUM_ID + 1]; /* Pktpool registry */
++
++/* Register/Deregister a pktpool with registry during pktpool_init/deinit */
++static int pktpool_register(pktpool_t * poolptr);
++static int pktpool_deregister(pktpool_t * poolptr);
++
++/** add declaration */
++static int pktpool_avail_notify(pktpool_t *pktp);
++
++/** accessor functions required when ROMming this file, forced into RAM */
++
++
++pktpool_t *
++BCMRAMFN(get_pktpools_registry)(int id)
++{
++	return pktpools_registry[id];
++}
++
++static void
++BCMRAMFN(pktpool_registry_set)(int id, pktpool_t *pp)
++{
++	pktpools_registry[id] = pp;
++}
++
++static bool
++BCMRAMFN(pktpool_registry_cmp)(int id, pktpool_t *pp)
++{
++	return pktpools_registry[id] == pp;
++}
++
++int /* Construct a pool registry to serve a maximum of total_pools */
++pktpool_attach(osl_t *osh, uint32 total_pools)
++{
++	uint32 poolid;
++
++	if (pktpools_max != 0U) {
++		return BCME_ERROR;
++	}
++
++	ASSERT(total_pools <= PKTPOOL_MAXIMUM_ID);
++
++	/* Initialize registry: reserve slot#0 and tag others as free */
++	PKTPOOL_REGISTRY_RSV();		/* reserve slot#0 */
++
++	PKTPOOL_REGISTRY_FOREACH(poolid) {	/* tag all unreserved entries as free */
++		PKTPOOL_REGISTRY_CLR(poolid);
++	}
++
++	pktpools_max = total_pools;
++
++	return (int)pktpools_max;
++}
++
++int /* Destruct the pool registry. Ascertain all pools were first de-inited */
++pktpool_dettach(osl_t *osh)
++{
++	uint32 poolid;
++
++	if (pktpools_max == 0U) {
++		return BCME_OK;
++	}
++
++	/* Ascertain that no pools are still registered */
++	ASSERT(PKTPOOL_REGISTRY_ISRSVD()); /* assert reserved slot */
++
++	PKTPOOL_REGISTRY_FOREACH(poolid) {	/* ascertain all others are free */
++		ASSERT(PKTPOOL_REGISTRY_ISCLR(poolid));
++	}
++
++	pktpools_max = 0U; /* restore boot state */
++
++	return BCME_OK;
++}
++
++static int	/* Register a pool in a free slot; return the registry slot index */
++pktpool_register(pktpool_t * poolptr)
++{
++	uint32 poolid;
++
++	if (pktpools_max == 0U) {
++		return PKTPOOL_INVALID_ID; /* registry has not yet been constructed */
++	}
++
++	ASSERT(pktpools_max != 0U);
++
++	/* find an empty slot in pktpools_registry */
++	PKTPOOL_REGISTRY_FOREACH(poolid) {
++		if (PKTPOOL_REGISTRY_ISCLR(poolid)) {
++			PKTPOOL_REGISTRY_SET(poolid, POOLPTR(poolptr)); /* register pool */
++			return (int)poolid; /* return pool ID */
++		}
++	} /* FOREACH */
++
++	return PKTPOOL_INVALID_ID;	/* error: registry is full */
++}
++
++static int	/* Deregister a pktpool, given the pool pointer; tag slot as free */
++pktpool_deregister(pktpool_t * poolptr)
++{
++	uint32 poolid;
++
++	ASSERT(POOLPTR(poolptr) != POOLPTR(NULL));
++
++	poolid = POOLID(poolptr);
++	ASSERT(poolid <= pktpools_max);
++
++	/* Asertain that a previously registered poolptr is being de-registered */
++	if (PKTPOOL_REGISTRY_CMP(poolid, POOLPTR(poolptr))) {
++		PKTPOOL_REGISTRY_CLR(poolid); /* mark as free */
++	} else {
++		ASSERT(0);
++		return BCME_ERROR; /* mismatch in registry */
++	}
++
++	return BCME_OK;
++}
++
++
++/*
++ * pktpool_init:
++ * User provides a pktpool_t sturcture and specifies the number of packets to
++ * be pre-filled into the pool (pplen). The size of all packets in a pool must
++ * be the same and is specified by plen.
++ * pktpool_init first attempts to register the pool and fetch a unique poolid.
++ * If registration fails, it is considered an BCME_ERR, caused by either the
++ * registry was not pre-created (pktpool_attach) or the registry is full.
++ * If registration succeeds, then the requested number of packets will be filled
++ * into the pool as part of initialization. In the event that there is no
++ * available memory to service the request, then BCME_NOMEM will be returned
++ * along with the count of how many packets were successfully allocated.
++ * In dongle builds, prior to memory reclaimation, one should limit the number
++ * of packets to be allocated during pktpool_init and fill the pool up after
++ * reclaim stage.
++ */
++int
++pktpool_init(osl_t *osh, pktpool_t *pktp, int *pplen, int plen, bool istx, uint8 type)
++{
++	int i, err = BCME_OK;
++	int pktplen;
++	uint8 pktp_id;
++
++	ASSERT(pktp != NULL);
++	ASSERT(osh != NULL);
++	ASSERT(pplen != NULL);
++
++	pktplen = *pplen;
++
++	bzero(pktp, sizeof(pktpool_t));
++
++	/* assign a unique pktpool id */
++	if ((pktp_id = (uint8) pktpool_register(pktp)) == PKTPOOL_INVALID_ID) {
++		return BCME_ERROR;
++	}
++	POOLSETID(pktp, pktp_id);
++
++	pktp->inited = TRUE;
++	pktp->istx = istx ? TRUE : FALSE;
++	pktp->plen = (uint16)plen;
++	pktp->type = type;
++
++	if (HND_PKTPOOL_MUTEX_CREATE("pktpool", &pktp->mutex) != OSL_EXT_SUCCESS) {
++		return BCME_ERROR;
++	}
++
++	pktp->maxlen = PKTPOOL_LEN_MAX;
++	pktplen = LIMIT_TO_MAX(pktplen, pktp->maxlen);
++
++	for (i = 0; i < pktplen; i++) {
++		void *p;
++		p = PKTGET(osh, plen, TRUE);
++
++		if (p == NULL) {
++			/* Not able to allocate all requested pkts
++			 * so just return what was actually allocated
++			 * We can add to the pool later
++			 */
++			if (pktp->freelist == NULL) /* pktpool free list is empty */
++				err = BCME_NOMEM;
++
++			goto exit;
++		}
++
++		PKTSETPOOL(osh, p, TRUE, pktp); /* Tag packet with pool ID */
++
++		PKTSETFREELIST(p, pktp->freelist); /* insert p at head of free list */
++		pktp->freelist = p;
++
++		pktp->avail++;
++
++#ifdef BCMDBG_POOL
++		pktp->dbg_q[pktp->dbg_qlen++].p = p;
++#endif
++	}
++
++exit:
++	pktp->len = pktp->avail;
++
++	*pplen = pktp->len;
++	return err;
++}
++
++/*
++ * pktpool_deinit:
++ * Prior to freeing a pktpool, all packets must be first freed into the pktpool.
++ * Upon pktpool_deinit, all packets in the free pool will be freed to the heap.
++ * An assert is in place to ensure that there are no packets still lingering
++ * around. Packets freed to a pool after the deinit will cause a memory
++ * corruption as the pktpool_t structure no longer exists.
++ */
++int
++pktpool_deinit(osl_t *osh, pktpool_t *pktp)
++{
++	uint16 freed = 0;
++
++	ASSERT(osh != NULL);
++	ASSERT(pktp != NULL);
++
++#ifdef BCMDBG_POOL
++	{
++		int i;
++		for (i = 0; i <= pktp->len; i++) {
++			pktp->dbg_q[i].p = NULL;
++		}
++	}
++#endif
++
++	while (pktp->freelist != NULL) {
++		void * p = pktp->freelist;
++
++		pktp->freelist = PKTFREELIST(p); /* unlink head packet from free list */
++		PKTSETFREELIST(p, NULL);
++
++		PKTSETPOOL(osh, p, FALSE, NULL); /* clear pool ID tag in pkt */
++
++		PKTFREE(osh, p, pktp->istx); /* free the packet */
++
++		freed++;
++		ASSERT(freed <= pktp->len);
++	}
++
++	pktp->avail -= freed;
++	ASSERT(pktp->avail == 0);
++
++	pktp->len -= freed;
++
++	pktpool_deregister(pktp); /* release previously acquired unique pool id */
++	POOLSETID(pktp, PKTPOOL_INVALID_ID);
++
++	if (HND_PKTPOOL_MUTEX_DELETE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	pktp->inited = FALSE;
++
++	/* Are there still pending pkts? */
++	ASSERT(pktp->len == 0);
++
++	return 0;
++}
++
++int
++pktpool_fill(osl_t *osh, pktpool_t *pktp, bool minimal)
++{
++	void *p;
++	int err = 0;
++	int len, psize, maxlen;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	ASSERT(pktp->plen != 0);
++
++	maxlen = pktp->maxlen;
++	psize = minimal ? (maxlen >> 2) : maxlen;
++	for (len = (int)pktp->len; len < psize; len++) {
++
++		p = PKTGET(osh, pktp->len, TRUE);
++
++		if (p == NULL) {
++			err = BCME_NOMEM;
++			break;
++		}
++
++		if (pktpool_add(pktp, p) != BCME_OK) {
++			PKTFREE(osh, p, FALSE);
++			err = BCME_ERROR;
++			break;
++		}
++	}
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	if (pktp->cbcnt) {
++		if (pktp->empty == FALSE)
++			pktpool_avail_notify(pktp);
++	}
++
++	return err;
++}
++
++static void *
++pktpool_deq(pktpool_t *pktp)
++{
++	void *p = NULL;
++
++	if (pktp->avail == 0)
++		return NULL;
++
++	ASSERT(pktp->freelist != NULL);
++
++	p = pktp->freelist;  /* dequeue packet from head of pktpool free list */
++	pktp->freelist = PKTFREELIST(p); /* free list points to next packet */
++	PKTSETFREELIST(p, NULL);
++
++	pktp->avail--;
++
++	return p;
++}
++
++static void
++pktpool_enq(pktpool_t *pktp, void *p)
++{
++	ASSERT(p != NULL);
++
++	PKTSETFREELIST(p, pktp->freelist); /* insert at head of pktpool free list */
++	pktp->freelist = p; /* free list points to newly inserted packet */
++
++	pktp->avail++;
++	ASSERT(pktp->avail <= pktp->len);
++}
++
++/* utility for registering host addr fill function called from pciedev */
++int
++/* BCMATTACHFN */
++(pktpool_hostaddr_fill_register)(pktpool_t *pktp, pktpool_cb_extn_t cb, void *arg)
++{
++
++	ASSERT(cb != NULL);
++
++	ASSERT(pktp->cbext.cb == NULL);
++	pktp->cbext.cb = cb;
++	pktp->cbext.arg = arg;
++	return 0;
++}
++
++int
++pktpool_rxcplid_fill_register(pktpool_t *pktp, pktpool_cb_extn_t cb, void *arg)
++{
++
++	ASSERT(cb != NULL);
++
++	if (pktp == NULL)
++		return BCME_ERROR;
++	ASSERT(pktp->rxcplidfn.cb == NULL);
++	pktp->rxcplidfn.cb = cb;
++	pktp->rxcplidfn.arg = arg;
++	return 0;
++}
++/* Callback functions for split rx modes */
++/* when evr host posts rxbuffer, invike dma_rxfill from pciedev layer */
++void
++pktpool_invoke_dmarxfill(pktpool_t *pktp)
++{
++	ASSERT(pktp->dmarxfill.cb);
++	ASSERT(pktp->dmarxfill.arg);
++
++	if (pktp->dmarxfill.cb)
++		pktp->dmarxfill.cb(pktp, pktp->dmarxfill.arg);
++}
++int
++pkpool_haddr_avail_register_cb(pktpool_t *pktp, pktpool_cb_t cb, void *arg)
++{
++
++	ASSERT(cb != NULL);
++
++	pktp->dmarxfill.cb = cb;
++	pktp->dmarxfill.arg = arg;
++
++	return 0;
++}
++/* No BCMATTACHFN as it is used in xdc_enable_ep which is not an attach function */
++int
++pktpool_avail_register(pktpool_t *pktp, pktpool_cb_t cb, void *arg)
++{
++	int err = 0;
++	int i;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	ASSERT(cb != NULL);
++
++	i = pktp->cbcnt;
++	if (i == PKTPOOL_CB_MAX_AVL) {
++		err = BCME_ERROR;
++		goto done;
++	}
++
++	ASSERT(pktp->cbs[i].cb == NULL);
++	pktp->cbs[i].cb = cb;
++	pktp->cbs[i].arg = arg;
++	pktp->cbcnt++;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return err;
++}
++
++int
++pktpool_empty_register(pktpool_t *pktp, pktpool_cb_t cb, void *arg)
++{
++	int err = 0;
++	int i;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	ASSERT(cb != NULL);
++
++	i = pktp->ecbcnt;
++	if (i == PKTPOOL_CB_MAX) {
++		err = BCME_ERROR;
++		goto done;
++	}
++
++	ASSERT(pktp->ecbs[i].cb == NULL);
++	pktp->ecbs[i].cb = cb;
++	pktp->ecbs[i].arg = arg;
++	pktp->ecbcnt++;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return err;
++}
++
++static int
++pktpool_empty_notify(pktpool_t *pktp)
++{
++	int i;
++
++	pktp->empty = TRUE;
++	for (i = 0; i < pktp->ecbcnt; i++) {
++		ASSERT(pktp->ecbs[i].cb != NULL);
++		pktp->ecbs[i].cb(pktp, pktp->ecbs[i].arg);
++	}
++	pktp->empty = FALSE;
++
++	return 0;
++}
++
++#ifdef BCMDBG_POOL
++int
++pktpool_dbg_register(pktpool_t *pktp, pktpool_cb_t cb, void *arg)
++{
++	int err = 0;
++	int i;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	ASSERT(cb);
++
++	i = pktp->dbg_cbcnt;
++	if (i == PKTPOOL_CB_MAX) {
++		err = BCME_ERROR;
++		goto done;
++	}
++
++	ASSERT(pktp->dbg_cbs[i].cb == NULL);
++	pktp->dbg_cbs[i].cb = cb;
++	pktp->dbg_cbs[i].arg = arg;
++	pktp->dbg_cbcnt++;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return err;
++}
++
++int pktpool_dbg_notify(pktpool_t *pktp);
++
++int
++pktpool_dbg_notify(pktpool_t *pktp)
++{
++	int i;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	for (i = 0; i < pktp->dbg_cbcnt; i++) {
++		ASSERT(pktp->dbg_cbs[i].cb);
++		pktp->dbg_cbs[i].cb(pktp, pktp->dbg_cbs[i].arg);
++	}
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return 0;
++}
++
++int
++pktpool_dbg_dump(pktpool_t *pktp)
++{
++	int i;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	printf("pool len=%d maxlen=%d\n",  pktp->dbg_qlen, pktp->maxlen);
++	for (i = 0; i < pktp->dbg_qlen; i++) {
++		ASSERT(pktp->dbg_q[i].p);
++		printf("%d, p: 0x%x dur:%lu us state:%d\n", i,
++			pktp->dbg_q[i].p, pktp->dbg_q[i].dur/100, PKTPOOLSTATE(pktp->dbg_q[i].p));
++	}
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return 0;
++}
++
++int
++pktpool_stats_dump(pktpool_t *pktp, pktpool_stats_t *stats)
++{
++	int i;
++	int state;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	bzero(stats, sizeof(pktpool_stats_t));
++	for (i = 0; i < pktp->dbg_qlen; i++) {
++		ASSERT(pktp->dbg_q[i].p != NULL);
++
++		state = PKTPOOLSTATE(pktp->dbg_q[i].p);
++		switch (state) {
++			case POOL_TXENQ:
++				stats->enq++; break;
++			case POOL_TXDH:
++				stats->txdh++; break;
++			case POOL_TXD11:
++				stats->txd11++; break;
++			case POOL_RXDH:
++				stats->rxdh++; break;
++			case POOL_RXD11:
++				stats->rxd11++; break;
++			case POOL_RXFILL:
++				stats->rxfill++; break;
++			case POOL_IDLE:
++				stats->idle++; break;
++		}
++	}
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return 0;
++}
++
++int
++pktpool_start_trigger(pktpool_t *pktp, void *p)
++{
++	uint32 cycles, i;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	if (!PKTPOOL(OSH_NULL, p))
++		goto done;
++
++	OSL_GETCYCLES(cycles);
++
++	for (i = 0; i < pktp->dbg_qlen; i++) {
++		ASSERT(pktp->dbg_q[i].p != NULL);
++
++		if (pktp->dbg_q[i].p == p) {
++			pktp->dbg_q[i].cycles = cycles;
++			break;
++		}
++	}
++
++done:
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return 0;
++}
++
++int pktpool_stop_trigger(pktpool_t *pktp, void *p);
++int
++pktpool_stop_trigger(pktpool_t *pktp, void *p)
++{
++	uint32 cycles, i;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	if (!PKTPOOL(OSH_NULL, p))
++		goto done;
++
++	OSL_GETCYCLES(cycles);
++
++	for (i = 0; i < pktp->dbg_qlen; i++) {
++		ASSERT(pktp->dbg_q[i].p != NULL);
++
++		if (pktp->dbg_q[i].p == p) {
++			if (pktp->dbg_q[i].cycles == 0)
++				break;
++
++			if (cycles >= pktp->dbg_q[i].cycles)
++				pktp->dbg_q[i].dur = cycles - pktp->dbg_q[i].cycles;
++			else
++				pktp->dbg_q[i].dur =
++					(((uint32)-1) - pktp->dbg_q[i].cycles) + cycles + 1;
++
++			pktp->dbg_q[i].cycles = 0;
++			break;
++		}
++	}
++
++done:
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return 0;
++}
++#endif /* BCMDBG_POOL */
++
++int
++pktpool_avail_notify_normal(osl_t *osh, pktpool_t *pktp)
++{
++	ASSERT(pktp);
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	pktp->availcb_excl = NULL;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return 0;
++}
++
++int
++pktpool_avail_notify_exclusive(osl_t *osh, pktpool_t *pktp, pktpool_cb_t cb)
++{
++	int i;
++	int err;
++
++	ASSERT(pktp);
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	ASSERT(pktp->availcb_excl == NULL);
++	for (i = 0; i < pktp->cbcnt; i++) {
++		if (cb == pktp->cbs[i].cb) {
++			pktp->availcb_excl = &pktp->cbs[i];
++			break;
++		}
++	}
++
++	if (pktp->availcb_excl == NULL)
++		err = BCME_ERROR;
++	else
++		err = 0;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return err;
++}
++
++static int
++pktpool_avail_notify(pktpool_t *pktp)
++{
++	int i, k, idx;
++	int avail;
++
++	ASSERT(pktp);
++	if (pktp->availcb_excl != NULL) {
++		pktp->availcb_excl->cb(pktp, pktp->availcb_excl->arg);
++		return 0;
++	}
++
++	k = pktp->cbcnt - 1;
++	for (i = 0; i < pktp->cbcnt; i++) {
++		avail = pktp->avail;
++
++		if (avail) {
++			if (pktp->cbtoggle)
++				idx = i;
++			else
++				idx = k--;
++
++			ASSERT(pktp->cbs[idx].cb != NULL);
++			pktp->cbs[idx].cb(pktp, pktp->cbs[idx].arg);
++		}
++	}
++
++	/* Alternate between filling from head or tail
++	 */
++	pktp->cbtoggle ^= 1;
++
++	return 0;
++}
++
++void *
++pktpool_get(pktpool_t *pktp)
++{
++	void *p;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++
++	p = pktpool_deq(pktp);
++
++	if (p == NULL) {
++		/* Notify and try to reclaim tx pkts */
++		if (pktp->ecbcnt)
++			pktpool_empty_notify(pktp);
++
++		p = pktpool_deq(pktp);
++		if (p == NULL)
++			goto done;
++	}
++
++
++done:
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void
++pktpool_free(pktpool_t *pktp, void *p)
++{
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return;
++
++	ASSERT(p != NULL);
++#ifdef BCMDBG_POOL
++	/* pktpool_stop_trigger(pktp, p); */
++#endif
++
++	pktpool_enq(pktp, p);
++
++	/**
++	 * Feed critical DMA with freshly freed packets, to avoid DMA starvation.
++	 * If any avail callback functions are registered, send a notification
++	 * that a new packet is available in the pool.
++	 */
++	if (pktp->cbcnt) {
++		/* To more efficiently use the cpu cycles, callbacks can be temporarily disabled.
++		 * This allows to feed on burst basis as opposed to inefficient per-packet basis.
++		 */
++		if (pktp->emptycb_disable == EMPTYCB_ENABLED) {
++			/**
++			 * If the call originated from pktpool_empty_notify, the just freed packet
++			 * is needed in pktpool_get.
++			 * Therefore don't call pktpool_avail_notify.
++			 */
++			if (pktp->empty == FALSE)
++				pktpool_avail_notify(pktp);
++		} else {
++			/**
++			 * The callback is temporarily disabled, log that a packet has been freed.
++			 */
++			pktp->emptycb_disable = EMPTYCB_SKIPPED;
++		}
++	}
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return;
++}
++
++int
++pktpool_add(pktpool_t *pktp, void *p)
++{
++	int err = 0;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	ASSERT(p != NULL);
++
++	if (pktp->len == pktp->maxlen) {
++		err = BCME_RANGE;
++		goto done;
++	}
++
++	/* pkts in pool have same length */
++	ASSERT(pktp->plen == PKTLEN(OSH_NULL, p));
++	PKTSETPOOL(OSH_NULL, p, TRUE, pktp);
++
++	pktp->len++;
++	pktpool_enq(pktp, p);
++
++#ifdef BCMDBG_POOL
++	pktp->dbg_q[pktp->dbg_qlen++].p = p;
++#endif
++
++done:
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return err;
++}
++
++/* Force pktpool_setmaxlen () into RAM as it uses a constant
++ * (PKTPOOL_LEN_MAX) that may be changed post tapeout for ROM-based chips.
++ */
++int
++BCMRAMFN(pktpool_setmaxlen)(pktpool_t *pktp, uint16 maxlen)
++{
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_ACQUIRE(&pktp->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	if (maxlen > PKTPOOL_LEN_MAX)
++		maxlen = PKTPOOL_LEN_MAX;
++
++	/* if pool is already beyond maxlen, then just cap it
++	 * since we currently do not reduce the pool len
++	 * already allocated
++	 */
++	pktp->maxlen = (pktp->len > maxlen) ? pktp->len : maxlen;
++
++	/* protect shared resource */
++	if (HND_PKTPOOL_MUTEX_RELEASE(&pktp->mutex) != OSL_EXT_SUCCESS)
++		return BCME_ERROR;
++
++	return pktp->maxlen;
++}
++
++void
++pktpool_emptycb_disable(pktpool_t *pktp, bool disable)
++{
++	ASSERT(pktp);
++
++	/**
++	 * To more efficiently use the cpu cycles, callbacks can be temporarily disabled.
++	 * If callback is going to be re-enabled, check if any packet got
++	 * freed and added back to the pool while callback was disabled.
++	 * When this is the case do the callback now, provided that callback functions
++	 * are registered and this call did not originate from pktpool_empty_notify.
++	 */
++	if ((!disable) && (pktp->cbcnt) && (pktp->empty == FALSE) &&
++		(pktp->emptycb_disable == EMPTYCB_SKIPPED)) {
++			pktpool_avail_notify(pktp);
++	}
++
++	/* Enable or temporarily disable callback when packet becomes available. */
++	pktp->emptycb_disable = disable ? EMPTYCB_DISABLED : EMPTYCB_ENABLED;
++}
++
++bool
++pktpool_emptycb_disabled(pktpool_t *pktp)
++{
++	ASSERT(pktp);
++	return pktp->emptycb_disable != EMPTYCB_ENABLED;
++}
++
++#ifdef BCMPKTPOOL
++#include <hnd_lbuf.h>
++
++pktpool_t *pktpool_shared = NULL;
++
++#ifdef BCMFRAGPOOL
++pktpool_t *pktpool_shared_lfrag = NULL;
++#endif /* BCMFRAGPOOL */
++
++pktpool_t *pktpool_shared_rxlfrag = NULL;
++
++static osl_t *pktpool_osh = NULL;
++
++void
++hnd_pktpool_init(osl_t *osh)
++{
++	int n;
++
++	/* Construct a packet pool registry before initializing packet pools */
++	n = pktpool_attach(osh, PKTPOOL_MAXIMUM_ID);
++	if (n != PKTPOOL_MAXIMUM_ID) {
++		ASSERT(0);
++		return;
++	}
++
++	pktpool_shared = MALLOCZ(osh, sizeof(pktpool_t));
++	if (pktpool_shared == NULL) {
++		ASSERT(0);
++		goto error1;
++	}
++
++#if defined(BCMFRAGPOOL) && !defined(BCMFRAGPOOL_DISABLED)
++	pktpool_shared_lfrag = MALLOCZ(osh, sizeof(pktpool_t));
++	if (pktpool_shared_lfrag == NULL) {
++		ASSERT(0);
++		goto error2;
++	}
++#endif
++
++#if defined(BCMRXFRAGPOOL) && !defined(BCMRXFRAGPOOL_DISABLED)
++	pktpool_shared_rxlfrag = MALLOCZ(osh, sizeof(pktpool_t));
++	if (pktpool_shared_rxlfrag == NULL) {
++		ASSERT(0);
++		goto error3;
++	}
++#endif
++
++
++	/*
++	 * At this early stage, there's not enough memory to allocate all
++	 * requested pkts in the shared pool.  Need to add to the pool
++	 * after reclaim
++	 *
++	 * n = NRXBUFPOST + SDPCMD_RXBUFS;
++	 *
++	 * Initialization of packet pools may fail (BCME_ERROR), if the packet pool
++	 * registry is not initialized or the registry is depleted.
++	 *
++	 * A BCME_NOMEM error only indicates that the requested number of packets
++	 * were not filled into the pool.
++	 */
++	n = 1;
++	if (pktpool_init(osh, pktpool_shared,
++	                 &n, PKTBUFSZ, FALSE, lbuf_basic) == BCME_ERROR) {
++		ASSERT(0);
++		goto error4;
++	}
++	pktpool_setmaxlen(pktpool_shared, SHARED_POOL_LEN);
++
++#if defined(BCMFRAGPOOL) && !defined(BCMFRAGPOOL_DISABLED)
++	n = 1;
++	if (pktpool_init(osh, pktpool_shared_lfrag,
++	                 &n, PKTFRAGSZ, TRUE, lbuf_frag) == BCME_ERROR) {
++		ASSERT(0);
++		goto error5;
++	}
++	pktpool_setmaxlen(pktpool_shared_lfrag, SHARED_FRAG_POOL_LEN);
++#endif
++#if defined(BCMRXFRAGPOOL) && !defined(BCMRXFRAGPOOL_DISABLED)
++	n = 1;
++	if (pktpool_init(osh, pktpool_shared_rxlfrag,
++	                 &n, PKTRXFRAGSZ, TRUE, lbuf_rxfrag) == BCME_ERROR) {
++		ASSERT(0);
++		goto error6;
++	}
++	pktpool_setmaxlen(pktpool_shared_rxlfrag, SHARED_RXFRAG_POOL_LEN);
++#endif
++
++	pktpool_osh = osh;
++
++	return;
++
++#if defined(BCMRXFRAGPOOL) && !defined(BCMRXFRAGPOOL_DISABLED)
++error6:
++#endif
++
++#if defined(BCMFRAGPOOL) && !defined(BCMFRAGPOOL_DISABLED)
++	pktpool_deinit(osh, pktpool_shared_lfrag);
++error5:
++#endif
++
++#if (defined(BCMRXFRAGPOOL) && !defined(BCMRXFRAGPOOL_DISABLED)) || \
++	(defined(BCMFRAGPOOL) && !defined(BCMFRAGPOOL_DISABLED))
++	pktpool_deinit(osh, pktpool_shared);
++#endif
++
++error4:
++#if defined(BCMRXFRAGPOOL) && !defined(BCMRXFRAGPOOL_DISABLED)
++	hnd_free(pktpool_shared_rxlfrag);
++	pktpool_shared_rxlfrag = (pktpool_t *)NULL;
++error3:
++#endif /* BCMRXFRAGPOOL */
++
++#if defined(BCMFRAGPOOL) && !defined(BCMFRAGPOOL_DISABLED)
++	hnd_free(pktpool_shared_lfrag);
++	pktpool_shared_lfrag = (pktpool_t *)NULL;
++error2:
++#endif /* BCMFRAGPOOL */
++
++	hnd_free(pktpool_shared);
++	pktpool_shared = (pktpool_t *)NULL;
++
++error1:
++	pktpool_dettach(osh);
++}
++
++void
++hnd_pktpool_fill(pktpool_t *pktpool, bool minimal)
++{
++	pktpool_fill(pktpool_osh, pktpool, minimal);
++}
++
++/* refill pktpools after reclaim */
++void
++hnd_pktpool_refill(bool minimal)
++{
++	if (POOL_ENAB(pktpool_shared)) {
++		pktpool_fill(pktpool_osh, pktpool_shared, minimal);
++	}
++/* fragpool reclaim */
++#ifdef BCMFRAGPOOL
++	if (POOL_ENAB(pktpool_shared_lfrag)) {
++		pktpool_fill(pktpool_osh, pktpool_shared_lfrag, minimal);
++	}
++#endif /* BCMFRAGPOOL */
++/* rx fragpool reclaim */
++#ifdef BCMRXFRAGPOOL
++	if (POOL_ENAB(pktpool_shared_rxlfrag)) {
++		pktpool_fill(pktpool_osh, pktpool_shared_rxlfrag, minimal);
++	}
++#endif
++}
++#endif /* BCMPKTPOOL */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/hnd_pktq.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/hnd_pktq.c
+new file mode 100644
+index 000000000..abf329417
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/hnd_pktq.c
+@@ -0,0 +1,888 @@
++/*
++ * HND generic pktq operation primitives
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: $
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++#include <osl_ext.h>
++#include <bcmutils.h>
++#include <hnd_pktq.h>
++
++/* mutex macros for thread safe */
++#ifdef HND_PKTQ_THREAD_SAFE
++#define HND_PKTQ_MUTEX_CREATE(name, mutex)	osl_ext_mutex_create(name, mutex)
++#define HND_PKTQ_MUTEX_DELETE(mutex)		osl_ext_mutex_delete(mutex)
++#define HND_PKTQ_MUTEX_ACQUIRE(mutex, msec)	osl_ext_mutex_acquire(mutex, msec)
++#define HND_PKTQ_MUTEX_RELEASE(mutex)		osl_ext_mutex_release(mutex)
++#else
++#define HND_PKTQ_MUTEX_CREATE(name, mutex)	OSL_EXT_SUCCESS
++#define HND_PKTQ_MUTEX_DELETE(mutex)		OSL_EXT_SUCCESS
++#define HND_PKTQ_MUTEX_ACQUIRE(mutex, msec)	OSL_EXT_SUCCESS
++#define HND_PKTQ_MUTEX_RELEASE(mutex)		OSL_EXT_SUCCESS
++#endif
++
++/*
++ * osl multiple-precedence packet queue
++ * hi_prec is always >= the number of the highest non-empty precedence
++ */
++void * BCMFASTPATH
++pktq_penq(struct pktq *pq, int prec, void *p)
++{
++	struct pktq_prec *q;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++	/* queueing chains not allowed and no segmented SKB (Kernel-3.18.y) */
++	ASSERT(!((PKTLINK(p) != NULL) && (PKTLINK(p) != p)));
++
++	ASSERT(!pktq_full(pq));
++	ASSERT(!pktq_pfull(pq, prec));
++	PKTSETLINK(p, NULL);
++
++	q = &pq->q[prec];
++
++	if (q->head)
++		PKTSETLINK(q->tail, p);
++	else
++		q->head = p;
++
++	q->tail = p;
++	q->len++;
++
++	pq->len++;
++
++	if (pq->hi_prec < prec)
++		pq->hi_prec = (uint8)prec;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void * BCMFASTPATH
++pktq_penq_head(struct pktq *pq, int prec, void *p)
++{
++	struct pktq_prec *q;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++	/* queueing chains not allowed and no segmented SKB (Kernel-3.18.y) */
++	ASSERT(!((PKTLINK(p) != NULL) && (PKTLINK(p) != p)));
++
++	ASSERT(!pktq_full(pq));
++	ASSERT(!pktq_pfull(pq, prec));
++	PKTSETLINK(p, NULL);
++
++	q = &pq->q[prec];
++
++	if (q->head == NULL)
++		q->tail = p;
++
++	PKTSETLINK(p, q->head);
++	q->head = p;
++	q->len++;
++
++	pq->len++;
++
++	if (pq->hi_prec < prec)
++		pq->hi_prec = (uint8)prec;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++/*
++ * Append spktq 'list' to the tail of pktq 'pq'
++ */
++void BCMFASTPATH
++pktq_append(struct pktq *pq, int prec, struct spktq *list)
++{
++	struct pktq_prec *q;
++	struct pktq_prec *list_q;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return;
++
++	list_q = &list->q[0];
++
++	/* empty list check */
++	if (list_q->head == NULL)
++		goto done;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++	ASSERT(PKTLINK(list_q->tail) == NULL);         /* terminated list */
++
++	ASSERT(!pktq_full(pq));
++	ASSERT(!pktq_pfull(pq, prec));
++
++	q = &pq->q[prec];
++
++	if (q->head)
++		PKTSETLINK(q->tail, list_q->head);
++	else
++		q->head = list_q->head;
++
++	q->tail = list_q->tail;
++	q->len += list_q->len;
++	pq->len += list_q->len;
++
++	if (pq->hi_prec < prec)
++		pq->hi_prec = (uint8)prec;
++
++	list_q->head = NULL;
++	list_q->tail = NULL;
++	list_q->len = 0;
++	list->len = 0;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return;
++}
++
++/*
++ * Prepend spktq 'list' to the head of pktq 'pq'
++ */
++void BCMFASTPATH
++pktq_prepend(struct pktq *pq, int prec, struct spktq *list)
++{
++	struct pktq_prec *q;
++	struct pktq_prec *list_q;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return;
++
++	list_q = &list->q[0];
++
++	/* empty list check */
++	if (list_q->head == NULL)
++		goto done;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++	ASSERT(PKTLINK(list_q->tail) == NULL);         /* terminated list */
++
++	ASSERT(!pktq_full(pq));
++	ASSERT(!pktq_pfull(pq, prec));
++
++	q = &pq->q[prec];
++
++	/* set the tail packet of list to point at the former pq head */
++	PKTSETLINK(list_q->tail, q->head);
++	/* the new q head is the head of list */
++	q->head = list_q->head;
++
++	/* If the q tail was non-null, then it stays as is.
++	 * If the q tail was null, it is now the tail of list
++	 */
++	if (q->tail == NULL) {
++		q->tail = list_q->tail;
++	}
++
++	q->len += list_q->len;
++	pq->len += list_q->len;
++
++	if (pq->hi_prec < prec)
++		pq->hi_prec = (uint8)prec;
++
++	list_q->head = NULL;
++	list_q->tail = NULL;
++	list_q->len = 0;
++	list->len = 0;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return;
++}
++
++void * BCMFASTPATH
++pktq_pdeq(struct pktq *pq, int prec)
++{
++	struct pktq_prec *q;
++	void *p;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	q = &pq->q[prec];
++
++	if ((p = q->head) == NULL)
++		goto done;
++
++	if ((q->head = PKTLINK(p)) == NULL)
++		q->tail = NULL;
++
++	q->len--;
++
++	pq->len--;
++
++	PKTSETLINK(p, NULL);
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void * BCMFASTPATH
++pktq_pdeq_prev(struct pktq *pq, int prec, void *prev_p)
++{
++	struct pktq_prec *q;
++	void *p = NULL;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	q = &pq->q[prec];
++
++	if (prev_p == NULL)
++		goto done;
++
++	if ((p = PKTLINK(prev_p)) == NULL)
++		goto done;
++
++	q->len--;
++
++	pq->len--;
++
++	PKTSETLINK(prev_p, PKTLINK(p));
++	PKTSETLINK(p, NULL);
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void * BCMFASTPATH
++pktq_pdeq_with_fn(struct pktq *pq, int prec, ifpkt_cb_t fn, int arg)
++{
++	struct pktq_prec *q;
++	void *p, *prev = NULL;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	q = &pq->q[prec];
++	p = q->head;
++
++	while (p) {
++		if (fn == NULL || (*fn)(p, arg)) {
++			break;
++		} else {
++			prev = p;
++			p = PKTLINK(p);
++		}
++	}
++	if (p == NULL)
++		goto done;
++
++	if (prev == NULL) {
++		if ((q->head = PKTLINK(p)) == NULL) {
++			q->tail = NULL;
++		}
++	} else {
++		PKTSETLINK(prev, PKTLINK(p));
++		if (q->tail == p) {
++			q->tail = prev;
++		}
++	}
++
++	q->len--;
++
++	pq->len--;
++
++	PKTSETLINK(p, NULL);
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void * BCMFASTPATH
++pktq_pdeq_tail(struct pktq *pq, int prec)
++{
++	struct pktq_prec *q;
++	void *p, *prev;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	q = &pq->q[prec];
++
++	if ((p = q->head) == NULL)
++		goto done;
++
++	for (prev = NULL; p != q->tail; p = PKTLINK(p))
++		prev = p;
++
++	if (prev)
++		PKTSETLINK(prev, NULL);
++	else
++		q->head = NULL;
++
++	q->tail = prev;
++	q->len--;
++
++	pq->len--;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void
++pktq_pflush(osl_t *osh, struct pktq *pq, int prec, bool dir, ifpkt_cb_t fn, int arg)
++{
++	struct pktq_prec *q;
++	void *p, *prev = NULL;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return;
++
++	q = &pq->q[prec];
++	p = q->head;
++	while (p) {
++		if (fn == NULL || (*fn)(p, arg)) {
++			bool head = (p == q->head);
++			if (head)
++				q->head = PKTLINK(p);
++			else
++				PKTSETLINK(prev, PKTLINK(p));
++			PKTSETLINK(p, NULL);
++			PKTFREE(osh, p, dir);
++			q->len--;
++			pq->len--;
++			p = (head ? q->head : PKTLINK(prev));
++		} else {
++			prev = p;
++			p = PKTLINK(p);
++		}
++	}
++
++	if (q->head == NULL) {
++		ASSERT(q->len == 0);
++		q->tail = NULL;
++	}
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return;
++}
++
++bool BCMFASTPATH
++pktq_pdel(struct pktq *pq, void *pktbuf, int prec)
++{
++	bool ret = FALSE;
++	struct pktq_prec *q;
++	void *p = NULL;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return FALSE;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	/* Should this just assert pktbuf? */
++	if (!pktbuf)
++		goto done;
++
++	q = &pq->q[prec];
++
++	if (q->head == pktbuf) {
++		if ((q->head = PKTLINK(pktbuf)) == NULL)
++			q->tail = NULL;
++	} else {
++		for (p = q->head; p && PKTLINK(p) != pktbuf; p = PKTLINK(p))
++			;
++		if (p == NULL)
++			goto done;
++
++		PKTSETLINK(p, PKTLINK(pktbuf));
++		if (q->tail == pktbuf)
++			q->tail = p;
++	}
++
++	q->len--;
++	pq->len--;
++	PKTSETLINK(pktbuf, NULL);
++	ret = TRUE;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return FALSE;
++
++	return ret;
++}
++
++bool
++pktq_init(struct pktq *pq, int num_prec, int max_len)
++{
++	int prec;
++
++	if (HND_PKTQ_MUTEX_CREATE("pktq", &pq->mutex) != OSL_EXT_SUCCESS)
++		return FALSE;
++
++	ASSERT(num_prec > 0 && num_prec <= PKTQ_MAX_PREC);
++
++	/* pq is variable size; only zero out what's requested */
++	bzero(pq, OFFSETOF(struct pktq, q) + (sizeof(struct pktq_prec) * num_prec));
++
++	pq->num_prec = (uint16)num_prec;
++
++	pq->max = (uint16)max_len;
++
++	for (prec = 0; prec < num_prec; prec++)
++		pq->q[prec].max = pq->max;
++
++	return TRUE;
++}
++
++bool
++pktq_deinit(struct pktq *pq)
++{
++	if (HND_PKTQ_MUTEX_DELETE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return FALSE;
++
++	return TRUE;
++}
++
++void
++pktq_set_max_plen(struct pktq *pq, int prec, int max_len)
++{
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return;
++
++	if (prec < pq->num_prec)
++		pq->q[prec].max = (uint16)max_len;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return;
++}
++
++void * BCMFASTPATH
++pktq_deq(struct pktq *pq, int *prec_out)
++{
++	struct pktq_prec *q;
++	void *p = NULL;
++	int prec;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	if (pq->len == 0)
++		goto done;
++
++	while ((prec = pq->hi_prec) > 0 && pq->q[prec].head == NULL)
++		pq->hi_prec--;
++
++	q = &pq->q[prec];
++
++	if ((p = q->head) == NULL)
++		goto done;
++
++	if ((q->head = PKTLINK(p)) == NULL)
++		q->tail = NULL;
++
++	q->len--;
++
++	pq->len--;
++
++	if (prec_out)
++		*prec_out = prec;
++
++	PKTSETLINK(p, NULL);
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void * BCMFASTPATH
++pktq_deq_tail(struct pktq *pq, int *prec_out)
++{
++	struct pktq_prec *q;
++	void *p = NULL, *prev;
++	int prec;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	if (pq->len == 0)
++		goto done;
++
++	for (prec = 0; prec < pq->hi_prec; prec++)
++		if (pq->q[prec].head)
++			break;
++
++	q = &pq->q[prec];
++
++	if ((p = q->head) == NULL)
++		goto done;
++
++	for (prev = NULL; p != q->tail; p = PKTLINK(p))
++		prev = p;
++
++	if (prev)
++		PKTSETLINK(prev, NULL);
++	else
++		q->head = NULL;
++
++	q->tail = prev;
++	q->len--;
++
++	pq->len--;
++
++	if (prec_out)
++		*prec_out = prec;
++
++	PKTSETLINK(p, NULL);
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void *
++pktq_peek(struct pktq *pq, int *prec_out)
++{
++	int prec;
++	void *p = NULL;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	if (pq->len == 0)
++		goto done;
++
++	while ((prec = pq->hi_prec) > 0 && pq->q[prec].head == NULL)
++		pq->hi_prec--;
++
++	if (prec_out)
++		*prec_out = prec;
++
++	p = pq->q[prec].head;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void *
++pktq_peek_tail(struct pktq *pq, int *prec_out)
++{
++	int prec;
++	void *p = NULL;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	if (pq->len == 0)
++		goto done;
++
++	for (prec = 0; prec < pq->hi_prec; prec++)
++		if (pq->q[prec].head)
++			break;
++
++	if (prec_out)
++		*prec_out = prec;
++
++	p = pq->q[prec].tail;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++void
++pktq_flush(osl_t *osh, struct pktq *pq, bool dir, ifpkt_cb_t fn, int arg)
++{
++	int prec;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return;
++
++	/* Optimize flush, if pktq len = 0, just return.
++	 * pktq len of 0 means pktq's prec q's are all empty.
++	 */
++	if (pq->len == 0)
++		goto done;
++
++	for (prec = 0; prec < pq->num_prec; prec++)
++		pktq_pflush(osh, pq, prec, dir, fn, arg);
++	if (fn == NULL)
++		ASSERT(pq->len == 0);
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return;
++}
++
++/* Return sum of lengths of a specific set of precedences */
++int
++pktq_mlen(struct pktq *pq, uint prec_bmp)
++{
++	int prec, len;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return 0;
++
++	len = 0;
++
++	for (prec = 0; prec <= pq->hi_prec; prec++)
++		if (prec_bmp & (1 << prec))
++			len += pq->q[prec].len;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return 0;
++
++	return len;
++}
++
++/* Priority peek from a specific set of precedences */
++void * BCMFASTPATH
++pktq_mpeek(struct pktq *pq, uint prec_bmp, int *prec_out)
++{
++	struct pktq_prec *q;
++	void *p = NULL;
++	int prec;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	if (pq->len == 0)
++		goto done;
++
++	while ((prec = pq->hi_prec) > 0 && pq->q[prec].head == NULL)
++		pq->hi_prec--;
++
++	while ((prec_bmp & (1 << prec)) == 0 || pq->q[prec].head == NULL)
++		if (prec-- == 0)
++			goto done;
++
++	q = &pq->q[prec];
++
++	if ((p = q->head) == NULL)
++		goto done;
++
++	if (prec_out)
++		*prec_out = prec;
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++/* Priority dequeue from a specific set of precedences */
++void * BCMFASTPATH
++pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out)
++{
++	struct pktq_prec *q;
++	void *p = NULL;
++	int prec;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	if (pq->len == 0)
++		goto done;
++
++	while ((prec = pq->hi_prec) > 0 && pq->q[prec].head == NULL)
++		pq->hi_prec--;
++
++	while ((pq->q[prec].head == NULL) || ((prec_bmp & (1 << prec)) == 0))
++		if (prec-- == 0)
++			goto done;
++
++	q = &pq->q[prec];
++
++	if ((p = q->head) == NULL)
++		goto done;
++
++	if ((q->head = PKTLINK(p)) == NULL)
++		q->tail = NULL;
++
++	q->len--;
++
++	if (prec_out)
++		*prec_out = prec;
++
++	pq->len--;
++
++	PKTSETLINK(p, NULL);
++
++done:
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return NULL;
++
++	return p;
++}
++
++#ifdef HND_PKTQ_THREAD_SAFE
++int
++pktq_pavail(struct pktq *pq, int prec)
++{
++	int ret;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return 0;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	ret = pq->q[prec].max - pq->q[prec].len;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return 0;
++
++	return ret;
++}
++
++bool
++pktq_pfull(struct pktq *pq, int prec)
++{
++	bool ret;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return FALSE;
++
++	ASSERT(prec >= 0 && prec < pq->num_prec);
++
++	ret = pq->q[prec].len >= pq->q[prec].max;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return FALSE;
++
++	return ret;
++}
++
++int
++pktq_avail(struct pktq *pq)
++{
++	int ret;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return 0;
++
++	ret = pq->max - pq->len;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return 0;
++
++	return ret;
++}
++
++bool
++pktq_full(struct pktq *pq)
++{
++	bool ret;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_ACQUIRE(&pq->mutex, OSL_EXT_TIME_FOREVER) != OSL_EXT_SUCCESS)
++		return FALSE;
++
++	ret = pq->len >= pq->max;
++
++	/* protect shared resource */
++	if (HND_PKTQ_MUTEX_RELEASE(&pq->mutex) != OSL_EXT_SUCCESS)
++		return FALSE;
++
++	return ret;
++}
++#endif	/* HND_PKTQ_THREAD_SAFE */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/hndpmu.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/hndpmu.c
+new file mode 100644
+index 000000000..d2ee9462f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/hndpmu.c
+@@ -0,0 +1,292 @@
++/*
++ * Misc utility routines for accessing PMU corerev specific features
++ * of the SiliconBackplane-based Broadcom chips.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: hndpmu.c 530092 2015-01-29 04:44:58Z $
++ */
++
++
++/*
++ * Note: this file contains PLL/FLL related functions. A chip can contain multiple PLLs/FLLs.
++ * However, in the context of this file the baseband ('BB') PLL/FLL is referred to.
++ *
++ * Throughout this code, the prefixes 'pmu0_', 'pmu1_' and 'pmu2_' are used.
++ * They refer to different revisions of the PMU (which is at revision 18 @ Apr 25, 2012)
++ * pmu1_ marks the transition from PLL to ADFLL (Digital Frequency Locked Loop). It supports
++ * fractional frequency generation. pmu2_ does not support fractional frequency generation.
++ */
++
++#include <bcm_cfg.h>
++#include <typedefs.h>
++#include <bcmdefs.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <siutils.h>
++#include <bcmdevs.h>
++#include <hndsoc.h>
++#include <sbchipc.h>
++#include <hndpmu.h>
++
++#define	PMU_ERROR(args)
++
++#define	PMU_MSG(args)
++
++/* To check in verbose debugging messages not intended
++ * to be on except on private builds.
++ */
++#define	PMU_NONE(args)
++
++/** contains resource bit positions for a specific chip */
++struct rsc_per_chip_s {
++	uint8 ht_avail;
++	uint8 macphy_clkavail;
++	uint8 ht_start;
++	uint8 otp_pu;
++};
++
++typedef struct rsc_per_chip_s rsc_per_chip_t;
++
++
++/* SDIO Pad drive strength to select value mappings.
++ * The last strength value in each table must be 0 (the tri-state value).
++ */
++typedef struct {
++	uint8 strength;			/* Pad Drive Strength in mA */
++	uint8 sel;			/* Chip-specific select value */
++} sdiod_drive_str_t;
++
++/* SDIO Drive Strength to sel value table for PMU Rev 1 */
++static const sdiod_drive_str_t sdiod_drive_strength_tab1[] = {
++	{4, 0x2},
++	{2, 0x3},
++	{1, 0x0},
++	{0, 0x0} };
++
++/* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
++static const sdiod_drive_str_t sdiod_drive_strength_tab2[] = {
++	{12, 0x7},
++	{10, 0x6},
++	{8, 0x5},
++	{6, 0x4},
++	{4, 0x2},
++	{2, 0x1},
++	{0, 0x0} };
++
++/* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
++static const sdiod_drive_str_t sdiod_drive_strength_tab3[] = {
++	{32, 0x7},
++	{26, 0x6},
++	{22, 0x5},
++	{16, 0x4},
++	{12, 0x3},
++	{8, 0x2},
++	{4, 0x1},
++	{0, 0x0} };
++
++/* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8v) */
++static const sdiod_drive_str_t sdiod_drive_strength_tab4_1v8[] = {
++	{32, 0x6},
++	{26, 0x7},
++	{22, 0x4},
++	{16, 0x5},
++	{12, 0x2},
++	{8, 0x3},
++	{4, 0x0},
++	{0, 0x1} };
++
++/* SDIO Drive Strength to sel value table for PMU Rev 11 (1.2v) */
++
++/* SDIO Drive Strength to sel value table for PMU Rev 11 (2.5v) */
++
++/* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
++static const sdiod_drive_str_t sdiod_drive_strength_tab5_1v8[] = {
++	{6, 0x7},
++	{5, 0x6},
++	{4, 0x5},
++	{3, 0x4},
++	{2, 0x2},
++	{1, 0x1},
++	{0, 0x0} };
++
++/* SDIO Drive Strength to sel value table for PMU Rev 13 (3.3v) */
++
++/** SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
++static const sdiod_drive_str_t sdiod_drive_strength_tab6_1v8[] = {
++	{3, 0x3},
++	{2, 0x2},
++	{1, 0x1},
++	{0, 0x0} };
++
++
++/**
++ * SDIO Drive Strength to sel value table for 43143 PMU Rev 17, see Confluence 43143 Toplevel
++ * architecture page, section 'PMU Chip Control 1 Register definition', click link to picture
++ * BCM43143_sel_sdio_signals.jpg. Valid after PMU Chip Control 0 Register, bit31 (override) has
++ * been written '1'.
++ */
++#if !defined(BCM_SDIO_VDDIO) || BCM_SDIO_VDDIO == 33
++
++static const sdiod_drive_str_t sdiod_drive_strength_tab7_3v3[] = {
++	/* note: for 14, 10, 6 and 2mA hw timing is not met according to rtl team */
++	{16, 0x7},
++	{12, 0x5},
++	{8,  0x3},
++	{4,  0x1} }; /* note: 43143 does not support tristate */
++
++#else
++
++static const sdiod_drive_str_t sdiod_drive_strength_tab7_1v8[] = {
++	/* note: for 7, 5, 3 and 1mA hw timing is not met according to rtl team */
++	{8, 0x7},
++	{6, 0x5},
++	{4,  0x3},
++	{2,  0x1} }; /* note: 43143 does not support tristate */
++
++#endif /* BCM_SDIO_VDDIO */
++
++#define SDIOD_DRVSTR_KEY(chip, pmu)	(((chip) << 16) | (pmu))
++
++/**
++ * Balance between stable SDIO operation and power consumption is achieved using this function.
++ * Note that each drive strength table is for a specific VDDIO of the SDIO pads, ideally this
++ * function should read the VDDIO itself to select the correct table. For now it has been solved
++ * with the 'BCM_SDIO_VDDIO' preprocessor constant.
++ *
++ * 'drivestrength': desired pad drive strength in mA. Drive strength of 0 requests tri-state (if
++ *		    hardware supports this), if no hw support drive strength is not programmed.
++ */
++void
++si_sdiod_drive_strength_init(si_t *sih, osl_t *osh, uint32 drivestrength)
++{
++	sdiod_drive_str_t *str_tab = NULL;
++	uint32 str_mask = 0;	/* only alter desired bits in PMU chipcontrol 1 register */
++	uint32 str_shift = 0;
++	uint32 str_ovr_pmuctl = PMU_CHIPCTL0; /* PMU chipcontrol register containing override bit */
++	uint32 str_ovr_pmuval = 0;            /* position of bit within this register */
++	pmuregs_t *pmu;
++	uint origidx;
++
++	if (!(sih->cccaps & CC_CAP_PMU)) {
++		return;
++	}
++
++	/* Remember original core before switch to chipc/pmu */
++	origidx = si_coreidx(sih);
++	if (AOB_ENAB(sih)) {
++		pmu = si_setcore(sih, PMU_CORE_ID, 0);
++	} else {
++		pmu = si_setcoreidx(sih, SI_CC_IDX);
++	}
++	ASSERT(pmu != NULL);
++
++	switch (SDIOD_DRVSTR_KEY(CHIPID(sih->chip), sih->pmurev)) {
++	case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
++		str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab1;
++		str_mask = 0x30000000;
++		str_shift = 28;
++		break;
++	case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
++	case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
++	case SDIOD_DRVSTR_KEY(BCM4315_CHIP_ID, 4):
++		str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab2;
++		str_mask = 0x00003800;
++		str_shift = 11;
++		break;
++	case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
++	case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 11):
++		if (sih->pmurev == 8) {
++			str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab3;
++		}
++		else if (sih->pmurev == 11) {
++			str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab4_1v8;
++		}
++		str_mask = 0x00003800;
++		str_shift = 11;
++		break;
++	case SDIOD_DRVSTR_KEY(BCM4330_CHIP_ID, 12):
++		str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab4_1v8;
++		str_mask = 0x00003800;
++		str_shift = 11;
++		break;
++	case SDIOD_DRVSTR_KEY(BCM43362_CHIP_ID, 13):
++		str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab5_1v8;
++		str_mask = 0x00003800;
++		str_shift = 11;
++		break;
++	case SDIOD_DRVSTR_KEY(BCM4334_CHIP_ID, 17):
++		str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab6_1v8;
++		str_mask = 0x00001800;
++		str_shift = 11;
++		break;
++	case SDIOD_DRVSTR_KEY(BCM43143_CHIP_ID, 17):
++#if !defined(BCM_SDIO_VDDIO) || BCM_SDIO_VDDIO == 33
++		if (drivestrength >=  ARRAYLAST(sdiod_drive_strength_tab7_3v3)->strength) {
++			str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab7_3v3;
++		}
++#else
++		if (drivestrength >=  ARRAYLAST(sdiod_drive_strength_tab7_1v8)->strength) {
++			str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab7_1v8;
++		}
++#endif /* BCM_SDIO_VDDIO */
++		str_mask = 0x00000007;
++		str_ovr_pmuval = PMU43143_CC0_SDIO_DRSTR_OVR;
++		break;
++	default:
++		PMU_MSG(("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
++		         bcm_chipname(
++			 CHIPID(sih->chip), chn, 8), CHIPREV(sih->chiprev), sih->pmurev));
++		break;
++	}
++
++	if (str_tab != NULL) {
++		uint32 cc_data_temp;
++		int i;
++
++		/* Pick the lowest available drive strength equal or greater than the
++		 * requested strength.	Drive strength of 0 requests tri-state.
++		 */
++		for (i = 0; drivestrength < str_tab[i].strength; i++)
++			;
++
++		if (i > 0 && drivestrength > str_tab[i].strength)
++			i--;
++
++		W_REG(osh, &pmu->chipcontrol_addr, PMU_CHIPCTL1);
++		cc_data_temp = R_REG(osh, &pmu->chipcontrol_data);
++		cc_data_temp &= ~str_mask;
++		cc_data_temp |= str_tab[i].sel << str_shift;
++		W_REG(osh, &pmu->chipcontrol_data, cc_data_temp);
++		if (str_ovr_pmuval) { /* enables the selected drive strength */
++			W_REG(osh,  &pmu->chipcontrol_addr, str_ovr_pmuctl);
++			OR_REG(osh, &pmu->chipcontrol_data, str_ovr_pmuval);
++		}
++		PMU_MSG(("SDIO: %dmA drive strength requested; set to %dmA\n",
++		         drivestrength, str_tab[i].strength));
++	}
++
++	/* Return to original core */
++	si_setcoreidx(sih, origidx);
++} /* si_sdiod_drive_strength_init */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/linux_osl.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/linux_osl.c
+new file mode 100644
+index 000000000..ba168e469
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/linux_osl.c
+@@ -0,0 +1,2531 @@
++/*
++ * Linux OS Independent Layer
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: linux_osl.c 709309 2019-01-17 09:04:00Z $
++ */
++
++#define LINUX_PORT
++
++#include <typedefs.h>
++#include <bcmendian.h>
++#include <linuxver.h>
++#include <bcmdefs.h>
++
++
++#if !defined(STBLINUX)
++#if defined(__ARM_ARCH_7A__) && !defined(DHD_USE_COHERENT_MEM_FOR_RING)
++#include <asm/cacheflush.h>
++#endif /* __ARM_ARCH_7A__ && !DHD_USE_COHERENT_MEM_FOR_RING */
++#endif /* STBLINUX */
++
++#include <linux/random.h>
++
++#include <osl.h>
++#include <bcmutils.h>
++#include <linux/delay.h>
++#include <pcicfg.h>
++
++
++#ifdef BCM_SECURE_DMA
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/printk.h>
++#include <linux/errno.h>
++#include <linux/mm.h>
++#include <linux/moduleparam.h>
++#include <asm/io.h>
++#include <linux/skbuff.h>
++#include <linux/vmalloc.h>
++#include <stbutils.h>
++#include <linux/highmem.h>
++#include <linux/dma-mapping.h>
++#include <asm/memory.h>
++#if defined(__ARM_ARCH_7A__)
++#include <arch/arm/include/asm/tlbflush.h>
++#endif
++#endif /* BCM_SECURE_DMA */
++
++#include <linux/fs.h>
++
++#if defined(STB)
++#include <linux/spinlock.h>
++extern spinlock_t l2x0_reg_lock;
++#endif 
++
++#ifdef BCM_OBJECT_TRACE
++#include <bcmutils.h>
++#endif /* BCM_OBJECT_TRACE */
++
++#define PCI_CFG_RETRY		10
++
++#define OS_HANDLE_MAGIC		0x1234abcd	/* Magic # to recognize osh */
++#define BCM_MEM_FILENAME_LEN	24		/* Mem. filename length */
++#define DUMPBUFSZ 1024
++
++/* dependancy check */
++#if !defined(BCMPCIE) && defined(DHD_USE_STATIC_CTRLBUF)
++#error "DHD_USE_STATIC_CTRLBUF suppored PCIE target only"
++#endif /* !BCMPCIE && DHD_USE_STATIC_CTRLBUF */
++
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++#ifdef DHD_USE_STATIC_CTRLBUF
++#define DHD_SKB_1PAGE_BUFSIZE	(PAGE_SIZE*1)
++#define DHD_SKB_2PAGE_BUFSIZE	(PAGE_SIZE*2)
++#define DHD_SKB_4PAGE_BUFSIZE	(PAGE_SIZE*4)
++
++#define PREALLOC_FREE_MAGIC	0xFEDC
++#define PREALLOC_USED_MAGIC	0xFCDE
++#else
++#define DHD_SKB_HDRSIZE		336
++#define DHD_SKB_1PAGE_BUFSIZE	((PAGE_SIZE*1)-DHD_SKB_HDRSIZE)
++#define DHD_SKB_2PAGE_BUFSIZE	((PAGE_SIZE*2)-DHD_SKB_HDRSIZE)
++#define DHD_SKB_4PAGE_BUFSIZE	((PAGE_SIZE*4)-DHD_SKB_HDRSIZE)
++#endif /* DHD_USE_STATIC_CTRLBUF */
++
++#define STATIC_BUF_MAX_NUM	16
++#define STATIC_BUF_SIZE	(PAGE_SIZE*2)
++#define STATIC_BUF_TOTAL_LEN	(STATIC_BUF_MAX_NUM * STATIC_BUF_SIZE)
++
++typedef struct bcm_static_buf {
++	spinlock_t static_lock;
++	unsigned char *buf_ptr;
++	unsigned char buf_use[STATIC_BUF_MAX_NUM];
++} bcm_static_buf_t;
++
++static bcm_static_buf_t *bcm_static_buf = 0;
++
++#ifdef DHD_USE_STATIC_CTRLBUF
++#define STATIC_PKT_4PAGE_NUM	0
++#define DHD_SKB_MAX_BUFSIZE	DHD_SKB_2PAGE_BUFSIZE
++#elif defined(ENHANCED_STATIC_BUF)
++#define STATIC_PKT_4PAGE_NUM	1
++#define DHD_SKB_MAX_BUFSIZE	DHD_SKB_4PAGE_BUFSIZE
++#else
++#define STATIC_PKT_4PAGE_NUM	0
++#define DHD_SKB_MAX_BUFSIZE	DHD_SKB_2PAGE_BUFSIZE
++#endif /* DHD_USE_STATIC_CTRLBUF */
++
++#ifdef DHD_USE_STATIC_CTRLBUF
++#define STATIC_PKT_1PAGE_NUM	0
++#define STATIC_PKT_2PAGE_NUM	64
++#else
++#define STATIC_PKT_1PAGE_NUM	8
++#define STATIC_PKT_2PAGE_NUM	8
++#endif /* DHD_USE_STATIC_CTRLBUF */
++
++#define STATIC_PKT_1_2PAGE_NUM	\
++	((STATIC_PKT_1PAGE_NUM) + (STATIC_PKT_2PAGE_NUM))
++#define STATIC_PKT_MAX_NUM	\
++	((STATIC_PKT_1_2PAGE_NUM) + (STATIC_PKT_4PAGE_NUM))
++
++typedef struct bcm_static_pkt {
++#ifdef DHD_USE_STATIC_CTRLBUF
++	struct sk_buff *skb_8k[STATIC_PKT_2PAGE_NUM];
++	unsigned char pkt_invalid[STATIC_PKT_2PAGE_NUM];
++	spinlock_t osl_pkt_lock;
++	uint32 last_allocated_index;
++#else
++	struct sk_buff *skb_4k[STATIC_PKT_1PAGE_NUM];
++	struct sk_buff *skb_8k[STATIC_PKT_2PAGE_NUM];
++#ifdef ENHANCED_STATIC_BUF
++	struct sk_buff *skb_16k;
++#endif /* ENHANCED_STATIC_BUF */
++	struct semaphore osl_pkt_sem;
++#endif /* DHD_USE_STATIC_CTRLBUF */
++	unsigned char pkt_use[STATIC_PKT_MAX_NUM];
++} bcm_static_pkt_t;
++
++static bcm_static_pkt_t *bcm_static_skb = 0;
++
++void* wifi_platform_prealloc(void *adapter, int section, unsigned long size);
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++
++typedef struct bcm_mem_link {
++	struct bcm_mem_link *prev;
++	struct bcm_mem_link *next;
++	uint	size;
++	int	line;
++	void 	*osh;
++	char	file[BCM_MEM_FILENAME_LEN];
++} bcm_mem_link_t;
++
++struct osl_cmn_info {
++	atomic_t malloced;
++	atomic_t pktalloced;    /* Number of allocated packet buffers */
++	spinlock_t dbgmem_lock;
++	bcm_mem_link_t *dbgmem_list;
++	spinlock_t pktalloc_lock;
++	atomic_t refcount; /* Number of references to this shared structure. */
++};
++typedef struct osl_cmn_info osl_cmn_t;
++
++struct osl_info {
++	osl_pubinfo_t pub;
++	uint32  flags;		/* If specific cases to be handled in the OSL */
++#ifdef CTFPOOL
++	ctfpool_t *ctfpool;
++#endif /* CTFPOOL */
++	uint magic;
++	void *pdev;
++	uint failed;
++	uint bustype;
++	osl_cmn_t *cmn; /* Common OSL related data shred between two OSH's */
++
++	void *bus_handle;
++#ifdef BCMDBG_CTRACE
++	spinlock_t ctrace_lock;
++	struct list_head ctrace_list;
++	int ctrace_num;
++#endif /* BCMDBG_CTRACE */
++#ifdef	BCM_SECURE_DMA
++	struct sec_mem_elem *sec_list_4096;
++	struct sec_mem_elem *sec_list_base_4096;
++	phys_addr_t  contig_base;
++	void *contig_base_va;
++	phys_addr_t  contig_base_alloc;
++	void *contig_base_alloc_va;
++	phys_addr_t contig_base_alloc_coherent;
++	void *contig_base_alloc_coherent_va;
++	void *contig_base_coherent_va;
++	phys_addr_t contig_delta_va_pa;
++	struct {
++		phys_addr_t pa;
++		void *va;
++		bool avail;
++	} sec_cma_coherent[SEC_CMA_COHERENT_MAX];
++	int stb_ext_params;
++#endif /* BCM_SECURE_DMA */
++};
++
++#ifdef BCM_SECURE_DMA
++static void * osl_sec_dma_ioremap(osl_t *osh, struct page *page, size_t size,
++	bool iscache, bool isdecr);
++static void osl_sec_dma_iounmap(osl_t *osh, void *contig_base_va, size_t size);
++static int osl_sec_dma_init_elem_mem_block(osl_t *osh, size_t mbsize, int max,
++	sec_mem_elem_t **list);
++static void osl_sec_dma_deinit_elem_mem_block(osl_t *osh, size_t mbsize, int max,
++	void *sec_list_base);
++static sec_mem_elem_t * osl_sec_dma_alloc_mem_elem(osl_t *osh, void *va, uint size,
++	int direction, struct sec_cma_info *ptr_cma_info, uint offset);
++static void osl_sec_dma_free_mem_elem(osl_t *osh, sec_mem_elem_t *sec_mem_elem);
++static void osl_sec_dma_init_consistent(osl_t *osh);
++static void *osl_sec_dma_alloc_consistent(osl_t *osh, uint size, uint16 align_bits,
++	ulong *pap);
++static void osl_sec_dma_free_consistent(osl_t *osh, void *va, uint size, dmaaddr_t pa);
++#endif /* BCM_SECURE_DMA */
++
++#ifdef BCM_OBJECT_TRACE
++/* don't clear the first 4 byte that is the pkt sn */
++#define OSL_PKTTAG_CLEAR(p) \
++do { \
++	struct sk_buff *s = (struct sk_buff *)(p); \
++	ASSERT(OSL_PKTTAG_SZ == 32); \
++	*(uint32 *)(&s->cb[4]) = 0; \
++	*(uint32 *)(&s->cb[8]) = 0; *(uint32 *)(&s->cb[12]) = 0; \
++	*(uint32 *)(&s->cb[16]) = 0; *(uint32 *)(&s->cb[20]) = 0; \
++	*(uint32 *)(&s->cb[24]) = 0; *(uint32 *)(&s->cb[28]) = 0; \
++} while (0)
++#else
++#define OSL_PKTTAG_CLEAR(p) \
++do { \
++	struct sk_buff *s = (struct sk_buff *)(p); \
++	ASSERT(OSL_PKTTAG_SZ == 32); \
++	*(uint32 *)(&s->cb[0]) = 0; *(uint32 *)(&s->cb[4]) = 0; \
++	*(uint32 *)(&s->cb[8]) = 0; *(uint32 *)(&s->cb[12]) = 0; \
++	*(uint32 *)(&s->cb[16]) = 0; *(uint32 *)(&s->cb[20]) = 0; \
++	*(uint32 *)(&s->cb[24]) = 0; *(uint32 *)(&s->cb[28]) = 0; \
++} while (0)
++#endif /* BCM_OBJECT_TRACE */
++
++/* PCMCIA attribute space access macros */
++
++/* Global ASSERT type flag */
++uint32 g_assert_type = 0;
++module_param(g_assert_type, int, 0);
++
++#ifdef	BCM_SECURE_DMA
++#define	SECDMA_MODULE_PARAMS	0
++#define	SECDMA_EXT_FILE	1
++
++unsigned long secdma_addr = 0;
++unsigned long secdma_addr2 = 0;
++u32 secdma_size = 0;
++u32 secdma_size2 = 0;
++module_param(secdma_addr, ulong, 0);
++module_param(secdma_size, int, 0);
++module_param(secdma_addr2, ulong, 0);
++module_param(secdma_size2, int, 0);
++static int secdma_found = 0;
++#endif /* BCM_SECURE_DMA */
++
++static int16 linuxbcmerrormap[] =
++{	0, 			/* 0 */
++	-EINVAL,		/* BCME_ERROR */
++	-EINVAL,		/* BCME_BADARG */
++	-EINVAL,		/* BCME_BADOPTION */
++	-EINVAL,		/* BCME_NOTUP */
++	-EINVAL,		/* BCME_NOTDOWN */
++	-EINVAL,		/* BCME_NOTAP */
++	-EINVAL,		/* BCME_NOTSTA */
++	-EINVAL,		/* BCME_BADKEYIDX */
++	-EINVAL,		/* BCME_RADIOOFF */
++	-EINVAL,		/* BCME_NOTBANDLOCKED */
++	-EINVAL, 		/* BCME_NOCLK */
++	-EINVAL, 		/* BCME_BADRATESET */
++	-EINVAL, 		/* BCME_BADBAND */
++	-E2BIG,			/* BCME_BUFTOOSHORT */
++	-E2BIG,			/* BCME_BUFTOOLONG */
++	-EBUSY, 		/* BCME_BUSY */
++	-EINVAL, 		/* BCME_NOTASSOCIATED */
++	-EINVAL, 		/* BCME_BADSSIDLEN */
++	-EINVAL, 		/* BCME_OUTOFRANGECHAN */
++	-EINVAL, 		/* BCME_BADCHAN */
++	-EFAULT, 		/* BCME_BADADDR */
++	-ENOMEM, 		/* BCME_NORESOURCE */
++	-EOPNOTSUPP,		/* BCME_UNSUPPORTED */
++	-EMSGSIZE,		/* BCME_BADLENGTH */
++	-EINVAL,		/* BCME_NOTREADY */
++	-EPERM,			/* BCME_EPERM */
++	-ENOMEM, 		/* BCME_NOMEM */
++	-EINVAL, 		/* BCME_ASSOCIATED */
++	-ERANGE, 		/* BCME_RANGE */
++	-EINVAL, 		/* BCME_NOTFOUND */
++	-EINVAL, 		/* BCME_WME_NOT_ENABLED */
++	-EINVAL, 		/* BCME_TSPEC_NOTFOUND */
++	-EINVAL, 		/* BCME_ACM_NOTSUPPORTED */
++	-EINVAL,		/* BCME_NOT_WME_ASSOCIATION */
++	-EIO,			/* BCME_SDIO_ERROR */
++	-ENODEV,		/* BCME_DONGLE_DOWN */
++	-EINVAL,		/* BCME_VERSION */
++	-EIO,			/* BCME_TXFAIL */
++	-EIO,			/* BCME_RXFAIL */
++	-ENODEV,		/* BCME_NODEVICE */
++	-EINVAL,		/* BCME_NMODE_DISABLED */
++	-ENODATA,		/* BCME_NONRESIDENT */
++	-EINVAL,		/* BCME_SCANREJECT */
++	-EINVAL,		/* BCME_USAGE_ERROR */
++	-EIO,     		/* BCME_IOCTL_ERROR */
++	-EIO,			/* BCME_SERIAL_PORT_ERR */
++	-EOPNOTSUPP,	/* BCME_DISABLED, BCME_NOTENABLED */
++	-EIO,			/* BCME_DECERR */
++	-EIO,			/* BCME_ENCERR */
++	-EIO,			/* BCME_MICERR */
++	-ERANGE,		/* BCME_REPLAY */
++	-EINVAL,		/* BCME_IE_NOTFOUND */
++	-EINVAL,		/* BCME_DATA_NOTFOUND */
++
++/* When an new error code is added to bcmutils.h, add os
++ * specific error translation here as well
++ */
++/* check if BCME_LAST changed since the last time this function was updated */
++#if BCME_LAST != -53
++#error "You need to add a OS error translation in the linuxbcmerrormap \
++	for new error code defined in bcmutils.h"
++#endif
++};
++uint lmtest = FALSE;
++
++/* translate bcmerrors into linux errors */
++int
++osl_error(int bcmerror)
++{
++	if (bcmerror > 0)
++		bcmerror = 0;
++	else if (bcmerror < BCME_LAST)
++		bcmerror = BCME_ERROR;
++
++	/* Array bounds covered by ASSERT in osl_attach */
++	return linuxbcmerrormap[-bcmerror];
++}
++#ifdef SHARED_OSL_CMN
++osl_t *
++osl_attach(void *pdev, uint bustype, bool pkttag, void **osl_cmn)
++{
++#else
++osl_t *
++osl_attach(void *pdev, uint bustype, bool pkttag)
++{
++	void **osl_cmn = NULL;
++#endif /* SHARED_OSL_CMN */
++	osl_t *osh;
++	gfp_t flags;
++
++#ifdef BCM_SECURE_DMA
++	u32 secdma_memsize;
++#endif
++
++	flags = CAN_SLEEP() ? GFP_KERNEL: GFP_ATOMIC;
++	if (!(osh = kmalloc(sizeof(osl_t), flags)))
++		return osh;
++
++	ASSERT(osh);
++
++	bzero(osh, sizeof(osl_t));
++
++	if (osl_cmn == NULL || *osl_cmn == NULL) {
++		if (!(osh->cmn = kmalloc(sizeof(osl_cmn_t), flags))) {
++			kfree(osh);
++			return NULL;
++		}
++		bzero(osh->cmn, sizeof(osl_cmn_t));
++		if (osl_cmn)
++			*osl_cmn = osh->cmn;
++		atomic_set(&osh->cmn->malloced, 0);
++		osh->cmn->dbgmem_list = NULL;
++		spin_lock_init(&(osh->cmn->dbgmem_lock));
++
++		spin_lock_init(&(osh->cmn->pktalloc_lock));
++
++	} else {
++		osh->cmn = *osl_cmn;
++	}
++	atomic_add(1, &osh->cmn->refcount);
++
++	bcm_object_trace_init();
++
++	/* Check that error map has the right number of entries in it */
++	ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(linuxbcmerrormap) - 1));
++
++	osh->failed = 0;
++	osh->pdev = pdev;
++	osh->pub.pkttag = pkttag;
++	osh->bustype = bustype;
++	osh->magic = OS_HANDLE_MAGIC;
++#ifdef BCM_SECURE_DMA
++
++	if ((secdma_addr != 0) && (secdma_size != 0)) {
++		printk("linux_osl.c: Buffer info passed via module params, using it.\n");
++
++		if (secdma_found == 0) {
++			osh->contig_base_alloc = (phys_addr_t)secdma_addr;
++			secdma_memsize = secdma_size;
++		} else if (secdma_found == 1) {
++			osh->contig_base_alloc = (phys_addr_t)secdma_addr2;
++			secdma_memsize = secdma_size2;
++		} else {
++			printk("linux_osl.c secdma: secDMA instances %d \n", secdma_found);
++			kfree(osh);
++			return NULL;
++		}
++
++		osh->contig_base = (phys_addr_t)osh->contig_base_alloc;
++
++		printf("linux_osl.c: secdma_cma_size = 0x%x\n", secdma_memsize);
++		printf("linux_osl.c: secdma_cma_addr = 0x%x \n",
++			(unsigned int)osh->contig_base_alloc);
++		osh->stb_ext_params = SECDMA_MODULE_PARAMS;
++	}
++	else if (stbpriv_init(osh) == 0) {
++		printk("linux_osl.c: stbpriv.txt found. Get buffer info.\n");
++
++		if (secdma_found == 0) {
++			osh->contig_base_alloc =
++				(phys_addr_t)bcm_strtoul(stbparam_get("secdma_cma_addr"), NULL, 0);
++			secdma_memsize = bcm_strtoul(stbparam_get("secdma_cma_size"), NULL, 0);
++		} else if (secdma_found == 1) {
++			osh->contig_base_alloc =
++				(phys_addr_t)bcm_strtoul(stbparam_get("secdma_cma_addr2"), NULL, 0);
++			secdma_memsize = bcm_strtoul(stbparam_get("secdma_cma_size2"), NULL, 0);
++		} else {
++			printk("linux_osl.c secdma: secDMA instances %d \n", secdma_found);
++			kfree(osh);
++			return NULL;
++		}
++
++		osh->contig_base = (phys_addr_t)osh->contig_base_alloc;
++
++		printf("linux_osl.c: secdma_cma_size = 0x%x\n", secdma_memsize);
++		printf("linux_osl.c: secdma_cma_addr = 0x%x \n",
++			(unsigned int)osh->contig_base_alloc);
++		osh->stb_ext_params = SECDMA_EXT_FILE;
++	}
++	else {
++		printk("linux_osl.c: secDMA no longer supports internal buffer allocation.\n");
++		kfree(osh);
++		return NULL;
++	}
++
++	secdma_found++;
++	osh->contig_base_alloc_coherent_va = osl_sec_dma_ioremap(osh,
++		phys_to_page((u32)osh->contig_base_alloc),
++		CMA_DMA_DESC_MEMBLOCK, FALSE, TRUE);
++
++	if (osh->contig_base_alloc_coherent_va == NULL) {
++		if (osh->cmn)
++			kfree(osh->cmn);
++	    kfree(osh);
++	    return NULL;
++	}
++	osh->contig_base_coherent_va = osh->contig_base_alloc_coherent_va;
++	osh->contig_base_alloc_coherent = osh->contig_base_alloc;
++	osl_sec_dma_init_consistent(osh);
++
++	osh->contig_base_alloc += CMA_DMA_DESC_MEMBLOCK;
++
++	osh->contig_base_alloc_va = osl_sec_dma_ioremap(osh,
++		phys_to_page((u32)osh->contig_base_alloc), CMA_DMA_DATA_MEMBLOCK, TRUE, FALSE);
++	if (osh->contig_base_alloc_va == NULL) {
++		osl_sec_dma_iounmap(osh, osh->contig_base_coherent_va, CMA_DMA_DESC_MEMBLOCK);
++		if (osh->cmn)
++			kfree(osh->cmn);
++		kfree(osh);
++		return NULL;
++	}
++	osh->contig_base_va = osh->contig_base_alloc_va;
++
++	if (BCME_OK != osl_sec_dma_init_elem_mem_block(osh,
++		CMA_BUFSIZE_4K, CMA_BUFNUM, &osh->sec_list_4096)) {
++	    osl_sec_dma_iounmap(osh, osh->contig_base_coherent_va, CMA_DMA_DESC_MEMBLOCK);
++	    osl_sec_dma_iounmap(osh, osh->contig_base_va, CMA_DMA_DATA_MEMBLOCK);
++		if (osh->cmn)
++			kfree(osh->cmn);
++		kfree(osh);
++		return NULL;
++	}
++	osh->sec_list_base_4096 = osh->sec_list_4096;
++
++#endif /* BCM_SECURE_DMA */
++
++	switch (bustype) {
++		case PCI_BUS:
++		case SI_BUS:
++		case PCMCIA_BUS:
++			osh->pub.mmbus = TRUE;
++			break;
++		case JTAG_BUS:
++		case SDIO_BUS:
++		case USB_BUS:
++		case SPI_BUS:
++		case RPC_BUS:
++			osh->pub.mmbus = FALSE;
++			break;
++		default:
++			ASSERT(FALSE);
++			break;
++	}
++
++#ifdef BCMDBG_CTRACE
++	spin_lock_init(&osh->ctrace_lock);
++	INIT_LIST_HEAD(&osh->ctrace_list);
++	osh->ctrace_num = 0;
++#endif /* BCMDBG_CTRACE */
++
++
++	return osh;
++}
++
++int osl_static_mem_init(osl_t *osh, void *adapter)
++{
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++		if (!bcm_static_buf && adapter) {
++			if (!(bcm_static_buf = (bcm_static_buf_t *)wifi_platform_prealloc(adapter,
++				3, STATIC_BUF_SIZE + STATIC_BUF_TOTAL_LEN))) {
++				printk("can not alloc static buf!\n");
++				bcm_static_skb = NULL;
++				ASSERT(osh->magic == OS_HANDLE_MAGIC);
++				return -ENOMEM;
++			} else {
++				printk("alloc static buf at %p!\n", bcm_static_buf);
++			}
++
++			spin_lock_init(&bcm_static_buf->static_lock);
++
++			bcm_static_buf->buf_ptr = (unsigned char *)bcm_static_buf + STATIC_BUF_SIZE;
++		}
++
++#if defined(BCMSDIO) || defined(DHD_USE_STATIC_CTRLBUF)
++		if (!bcm_static_skb && adapter) {
++			int i;
++			void *skb_buff_ptr = 0;
++			bcm_static_skb = (bcm_static_pkt_t *)((char *)bcm_static_buf + 2048);
++			skb_buff_ptr = wifi_platform_prealloc(adapter, 4, 0);
++			if (!skb_buff_ptr) {
++				printk("cannot alloc static buf!\n");
++				bcm_static_buf = NULL;
++				bcm_static_skb = NULL;
++				ASSERT(osh->magic == OS_HANDLE_MAGIC);
++				return -ENOMEM;
++			}
++
++			bcopy(skb_buff_ptr, bcm_static_skb, sizeof(struct sk_buff *) *
++				(STATIC_PKT_MAX_NUM));
++			for (i = 0; i < STATIC_PKT_MAX_NUM; i++) {
++				bcm_static_skb->pkt_use[i] = 0;
++			}
++
++#ifdef DHD_USE_STATIC_CTRLBUF
++			spin_lock_init(&bcm_static_skb->osl_pkt_lock);
++			bcm_static_skb->last_allocated_index = 0;
++#else
++			sema_init(&bcm_static_skb->osl_pkt_sem, 1);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++		}
++#endif /* BCMSDIO || DHD_USE_STATIC_CTRLBUF */
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++
++	return 0;
++}
++
++void osl_set_bus_handle(osl_t *osh, void *bus_handle)
++{
++	osh->bus_handle = bus_handle;
++}
++
++void* osl_get_bus_handle(osl_t *osh)
++{
++	return osh->bus_handle;
++}
++
++void
++osl_detach(osl_t *osh)
++{
++	if (osh == NULL)
++		return;
++
++#ifdef BCM_SECURE_DMA
++	if (osh->stb_ext_params == SECDMA_EXT_FILE)
++		stbpriv_exit(osh);
++	osl_sec_dma_deinit_elem_mem_block(osh, CMA_BUFSIZE_4K, CMA_BUFNUM, osh->sec_list_base_4096);
++	osl_sec_dma_iounmap(osh, osh->contig_base_coherent_va, CMA_DMA_DESC_MEMBLOCK);
++	osl_sec_dma_iounmap(osh, osh->contig_base_va, CMA_DMA_DATA_MEMBLOCK);
++
++	secdma_found--;
++#endif /* BCM_SECURE_DMA */
++
++
++	bcm_object_trace_deinit();
++
++	ASSERT(osh->magic == OS_HANDLE_MAGIC);
++	atomic_sub(1, &osh->cmn->refcount);
++	if (atomic_read(&osh->cmn->refcount) == 0) {
++			kfree(osh->cmn);
++	}
++	kfree(osh);
++}
++
++int osl_static_mem_deinit(osl_t *osh, void *adapter)
++{
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++	if (bcm_static_buf) {
++		bcm_static_buf = 0;
++	}
++#ifdef BCMSDIO
++	if (bcm_static_skb) {
++		bcm_static_skb = 0;
++	}
++#endif /* BCMSDIO */
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++	return 0;
++}
++
++static struct sk_buff *osl_alloc_skb(osl_t *osh, unsigned int len)
++{
++	struct sk_buff *skb;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25)
++	gfp_t flags = (in_atomic() || irqs_disabled()) ? GFP_ATOMIC : GFP_KERNEL;
++#if defined(CONFIG_SPARSEMEM) && defined(CONFIG_ZONE_DMA)
++	flags |= GFP_ATOMIC;
++#endif
++	skb = __dev_alloc_skb(len, flags);
++#else
++	skb = dev_alloc_skb(len);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25) */
++	return skb;
++}
++
++#ifdef CTFPOOL
++
++#ifdef CTFPOOL_SPINLOCK
++#define CTFPOOL_LOCK(ctfpool, flags)	spin_lock_irqsave(&(ctfpool)->lock, flags)
++#define CTFPOOL_UNLOCK(ctfpool, flags)	spin_unlock_irqrestore(&(ctfpool)->lock, flags)
++#else
++#define CTFPOOL_LOCK(ctfpool, flags)	spin_lock_bh(&(ctfpool)->lock)
++#define CTFPOOL_UNLOCK(ctfpool, flags)	spin_unlock_bh(&(ctfpool)->lock)
++#endif /* CTFPOOL_SPINLOCK */
++/*
++ * Allocate and add an object to packet pool.
++ */
++void *
++osl_ctfpool_add(osl_t *osh)
++{
++	struct sk_buff *skb;
++#ifdef CTFPOOL_SPINLOCK
++	unsigned long flags;
++#endif /* CTFPOOL_SPINLOCK */
++
++	if ((osh == NULL) || (osh->ctfpool == NULL))
++		return NULL;
++
++	CTFPOOL_LOCK(osh->ctfpool, flags);
++	ASSERT(osh->ctfpool->curr_obj <= osh->ctfpool->max_obj);
++
++	/* No need to allocate more objects */
++	if (osh->ctfpool->curr_obj == osh->ctfpool->max_obj) {
++		CTFPOOL_UNLOCK(osh->ctfpool, flags);
++		return NULL;
++	}
++
++	/* Allocate a new skb and add it to the ctfpool */
++	skb = osl_alloc_skb(osh, osh->ctfpool->obj_size);
++	if (skb == NULL) {
++		printf("%s: skb alloc of len %d failed\n", __FUNCTION__,
++		       osh->ctfpool->obj_size);
++		CTFPOOL_UNLOCK(osh->ctfpool, flags);
++		return NULL;
++	}
++
++	/* Add to ctfpool */
++	skb->next = (struct sk_buff *)osh->ctfpool->head;
++	osh->ctfpool->head = skb;
++	osh->ctfpool->fast_frees++;
++	osh->ctfpool->curr_obj++;
++
++	/* Hijack a skb member to store ptr to ctfpool */
++	CTFPOOLPTR(osh, skb) = (void *)osh->ctfpool;
++
++	/* Use bit flag to indicate skb from fast ctfpool */
++	PKTFAST(osh, skb) = FASTBUF;
++
++	CTFPOOL_UNLOCK(osh->ctfpool, flags);
++
++	return skb;
++}
++
++/*
++ * Add new objects to the pool.
++ */
++void
++osl_ctfpool_replenish(osl_t *osh, uint thresh)
++{
++	if ((osh == NULL) || (osh->ctfpool == NULL))
++		return;
++
++	/* Do nothing if no refills are required */
++	while ((osh->ctfpool->refills > 0) && (thresh--)) {
++		osl_ctfpool_add(osh);
++		osh->ctfpool->refills--;
++	}
++}
++
++/*
++ * Initialize the packet pool with specified number of objects.
++ */
++int32
++osl_ctfpool_init(osl_t *osh, uint numobj, uint size)
++{
++	gfp_t flags;
++
++	flags = CAN_SLEEP() ? GFP_KERNEL: GFP_ATOMIC;
++	osh->ctfpool = kzalloc(sizeof(ctfpool_t), flags);
++	ASSERT(osh->ctfpool);
++
++	osh->ctfpool->max_obj = numobj;
++	osh->ctfpool->obj_size = size;
++
++	spin_lock_init(&osh->ctfpool->lock);
++
++	while (numobj--) {
++		if (!osl_ctfpool_add(osh))
++			return -1;
++		osh->ctfpool->fast_frees--;
++	}
++
++	return 0;
++}
++
++/*
++ * Cleanup the packet pool objects.
++ */
++void
++osl_ctfpool_cleanup(osl_t *osh)
++{
++	struct sk_buff *skb, *nskb;
++#ifdef CTFPOOL_SPINLOCK
++	unsigned long flags;
++#endif /* CTFPOOL_SPINLOCK */
++
++	if ((osh == NULL) || (osh->ctfpool == NULL))
++		return;
++
++	CTFPOOL_LOCK(osh->ctfpool, flags);
++
++	skb = osh->ctfpool->head;
++
++	while (skb != NULL) {
++		nskb = skb->next;
++		dev_kfree_skb(skb);
++		skb = nskb;
++		osh->ctfpool->curr_obj--;
++	}
++
++	ASSERT(osh->ctfpool->curr_obj == 0);
++	osh->ctfpool->head = NULL;
++	CTFPOOL_UNLOCK(osh->ctfpool, flags);
++
++	kfree(osh->ctfpool);
++	osh->ctfpool = NULL;
++}
++
++void
++osl_ctfpool_stats(osl_t *osh, void *b)
++{
++	struct bcmstrbuf *bb;
++
++	if ((osh == NULL) || (osh->ctfpool == NULL))
++		return;
++
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++	if (bcm_static_buf) {
++		bcm_static_buf = 0;
++	}
++#ifdef BCMSDIO
++	if (bcm_static_skb) {
++		bcm_static_skb = 0;
++	}
++#endif /* BCMSDIO */
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++
++	bb = b;
++
++	ASSERT((osh != NULL) && (bb != NULL));
++
++	bcm_bprintf(bb, "max_obj %d obj_size %d curr_obj %d refills %d\n",
++	            osh->ctfpool->max_obj, osh->ctfpool->obj_size,
++	            osh->ctfpool->curr_obj, osh->ctfpool->refills);
++	bcm_bprintf(bb, "fast_allocs %d fast_frees %d slow_allocs %d\n",
++	            osh->ctfpool->fast_allocs, osh->ctfpool->fast_frees,
++	            osh->ctfpool->slow_allocs);
++}
++
++static inline struct sk_buff *
++osl_pktfastget(osl_t *osh, uint len)
++{
++	struct sk_buff *skb;
++#ifdef CTFPOOL_SPINLOCK
++	unsigned long flags;
++#endif /* CTFPOOL_SPINLOCK */
++
++	/* Try to do fast allocate. Return null if ctfpool is not in use
++	 * or if there are no items in the ctfpool.
++	 */
++	if (osh->ctfpool == NULL)
++		return NULL;
++
++	CTFPOOL_LOCK(osh->ctfpool, flags);
++	if (osh->ctfpool->head == NULL) {
++		ASSERT(osh->ctfpool->curr_obj == 0);
++		osh->ctfpool->slow_allocs++;
++		CTFPOOL_UNLOCK(osh->ctfpool, flags);
++		return NULL;
++	}
++
++	if (len > osh->ctfpool->obj_size) {
++		CTFPOOL_UNLOCK(osh->ctfpool, flags);
++		return NULL;
++	}
++
++	ASSERT(len <= osh->ctfpool->obj_size);
++
++	/* Get an object from ctfpool */
++	skb = (struct sk_buff *)osh->ctfpool->head;
++	osh->ctfpool->head = (void *)skb->next;
++
++	osh->ctfpool->fast_allocs++;
++	osh->ctfpool->curr_obj--;
++	ASSERT(CTFPOOLHEAD(osh, skb) == (struct sock *)osh->ctfpool->head);
++	CTFPOOL_UNLOCK(osh->ctfpool, flags);
++
++	/* Init skb struct */
++	skb->next = skb->prev = NULL;
++#if defined(__ARM_ARCH_7A__)
++	skb->data = skb->head + NET_SKB_PAD;
++	skb->tail = skb->head + NET_SKB_PAD;
++#else
++	skb->data = skb->head + 16;
++	skb->tail = skb->head + 16;
++#endif /* __ARM_ARCH_7A__ */
++	skb->len = 0;
++	skb->cloned = 0;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 14)
++	skb->list = NULL;
++#endif
++	atomic_set(&skb->users, 1);
++
++	PKTSETCLINK(skb, NULL);
++	PKTCCLRATTR(skb);
++	PKTFAST(osh, skb) &= ~(CTFBUF | SKIPCT | CHAINED);
++
++	return skb;
++}
++#endif /* CTFPOOL */
++
++#if defined(BCM_GMAC3)
++/* Account for a packet delivered to downstream forwarder.
++ * Decrement a GMAC forwarder interface's pktalloced count.
++ */
++void BCMFASTPATH
++osl_pkt_tofwder(osl_t *osh, void *skbs, int skb_cnt)
++{
++
++	atomic_sub(skb_cnt, &osh->cmn->pktalloced);
++}
++
++/* Account for a downstream forwarder delivered packet to a WL/DHD driver.
++ * Increment a GMAC forwarder interface's pktalloced count.
++ */
++#ifdef BCMDBG_CTRACE
++void BCMFASTPATH
++osl_pkt_frmfwder(osl_t *osh, void *skbs, int skb_cnt, int line, char *file)
++#else
++void BCMFASTPATH
++osl_pkt_frmfwder(osl_t *osh, void *skbs, int skb_cnt)
++#endif /* BCMDBG_CTRACE */
++{
++#if defined(BCMDBG_CTRACE)
++	int i;
++	struct sk_buff *skb;
++#endif 
++
++#if defined(BCMDBG_CTRACE)
++	if (skb_cnt > 1) {
++		struct sk_buff **skb_array = (struct sk_buff **)skbs;
++		for (i = 0; i < skb_cnt; i++) {
++			skb = skb_array[i];
++#if defined(BCMDBG_CTRACE)
++			ASSERT(!PKTISCHAINED(skb));
++			ADD_CTRACE(osh, skb, file, line);
++#endif /* BCMDBG_CTRACE */
++		}
++	} else {
++		skb = (struct sk_buff *)skbs;
++#if defined(BCMDBG_CTRACE)
++		ASSERT(!PKTISCHAINED(skb));
++		ADD_CTRACE(osh, skb, file, line);
++#endif /* BCMDBG_CTRACE */
++	}
++#endif 
++
++	atomic_add(skb_cnt, &osh->cmn->pktalloced);
++}
++
++#endif /* BCM_GMAC3 */
++
++/* Convert a driver packet to native(OS) packet
++ * In the process, packettag is zeroed out before sending up
++ * IP code depends on skb->cb to be setup correctly with various options
++ * In our case, that means it should be 0
++ */
++struct sk_buff * BCMFASTPATH
++osl_pkt_tonative(osl_t *osh, void *pkt)
++{
++	struct sk_buff *nskb;
++#ifdef BCMDBG_CTRACE
++	struct sk_buff *nskb1, *nskb2;
++#endif
++
++	if (osh->pub.pkttag)
++		OSL_PKTTAG_CLEAR(pkt);
++
++	/* Decrement the packet counter */
++	for (nskb = (struct sk_buff *)pkt; nskb; nskb = nskb->next) {
++		atomic_sub(PKTISCHAINED(nskb) ? PKTCCNT(nskb) : 1, &osh->cmn->pktalloced);
++
++#ifdef BCMDBG_CTRACE
++		for (nskb1 = nskb; nskb1 != NULL; nskb1 = nskb2) {
++			if (PKTISCHAINED(nskb1)) {
++				nskb2 = PKTCLINK(nskb1);
++			}
++			else
++				nskb2 = NULL;
++
++			DEL_CTRACE(osh, nskb1);
++		}
++#endif /* BCMDBG_CTRACE */
++	}
++	return (struct sk_buff *)pkt;
++}
++
++/* Convert a native(OS) packet to driver packet.
++ * In the process, native packet is destroyed, there is no copying
++ * Also, a packettag is zeroed out
++ */
++#ifdef BCMDBG_CTRACE
++void * BCMFASTPATH
++osl_pkt_frmnative(osl_t *osh, void *pkt, int line, char *file)
++#else
++void * BCMFASTPATH
++osl_pkt_frmnative(osl_t *osh, void *pkt)
++#endif /* BCMDBG_CTRACE */
++{
++	struct sk_buff *nskb;
++#ifdef BCMDBG_CTRACE
++	struct sk_buff *nskb1, *nskb2;
++#endif
++
++	if (osh->pub.pkttag)
++		OSL_PKTTAG_CLEAR(pkt);
++
++	/* Increment the packet counter */
++	for (nskb = (struct sk_buff *)pkt; nskb; nskb = nskb->next) {
++		atomic_add(PKTISCHAINED(nskb) ? PKTCCNT(nskb) : 1, &osh->cmn->pktalloced);
++
++#ifdef BCMDBG_CTRACE
++		for (nskb1 = nskb; nskb1 != NULL; nskb1 = nskb2) {
++			if (PKTISCHAINED(nskb1)) {
++				nskb2 = PKTCLINK(nskb1);
++			}
++			else
++				nskb2 = NULL;
++
++			ADD_CTRACE(osh, nskb1, file, line);
++		}
++#endif /* BCMDBG_CTRACE */
++	}
++	return (void *)pkt;
++}
++
++/* Return a new packet. zero out pkttag */
++#ifdef BCMDBG_CTRACE
++void * BCMFASTPATH
++osl_pktget(osl_t *osh, uint len, int line, char *file)
++#else
++#ifdef BCM_OBJECT_TRACE
++void * BCMFASTPATH
++osl_pktget(osl_t *osh, uint len, int line, const char *caller)
++#else
++void * BCMFASTPATH
++osl_pktget(osl_t *osh, uint len)
++#endif /* BCM_OBJECT_TRACE */
++#endif /* BCMDBG_CTRACE */
++{
++	struct sk_buff *skb;
++	uchar num = 0;
++	if (lmtest != FALSE) {
++		get_random_bytes(&num, sizeof(uchar));
++		if ((num + 1) <= (256 * lmtest / 100))
++			return NULL;
++	}
++
++#ifdef CTFPOOL
++	/* Allocate from local pool */
++	skb = osl_pktfastget(osh, len);
++	if ((skb != NULL) || ((skb = osl_alloc_skb(osh, len)) != NULL)) {
++#else /* CTFPOOL */
++	if ((skb = osl_alloc_skb(osh, len))) {
++#endif /* CTFPOOL */
++		skb->tail += len;
++		skb->len  += len;
++		skb->priority = 0;
++
++#ifdef BCMDBG_CTRACE
++		ADD_CTRACE(osh, skb, file, line);
++#endif
++		atomic_inc(&osh->cmn->pktalloced);
++#ifdef BCM_OBJECT_TRACE
++		bcm_object_trace_opr(skb, BCM_OBJDBG_ADD_PKT, caller, line);
++#endif /* BCM_OBJECT_TRACE */
++	}
++
++	return ((void*) skb);
++}
++
++#ifdef CTFPOOL
++static inline void
++osl_pktfastfree(osl_t *osh, struct sk_buff *skb)
++{
++	ctfpool_t *ctfpool;
++#ifdef CTFPOOL_SPINLOCK
++	unsigned long flags;
++#endif /* CTFPOOL_SPINLOCK */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 14)
++	skb->tstamp.tv.sec = 0;
++#else
++	skb->stamp.tv_sec = 0;
++#endif
++
++	/* We only need to init the fields that we change */
++	skb->dev = NULL;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36)
++	skb->dst = NULL;
++#endif
++	OSL_PKTTAG_CLEAR(skb);
++	skb->ip_summed = 0;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
++	skb_orphan(skb);
++#else
++	skb->destructor = NULL;
++#endif
++
++	ctfpool = (ctfpool_t *)CTFPOOLPTR(osh, skb);
++	ASSERT(ctfpool != NULL);
++
++	/* Add object to the ctfpool */
++	CTFPOOL_LOCK(ctfpool, flags);
++	skb->next = (struct sk_buff *)ctfpool->head;
++	ctfpool->head = (void *)skb;
++
++	ctfpool->fast_frees++;
++	ctfpool->curr_obj++;
++
++	ASSERT(ctfpool->curr_obj <= ctfpool->max_obj);
++	CTFPOOL_UNLOCK(ctfpool, flags);
++}
++#endif /* CTFPOOL */
++
++/* Free the driver packet. Free the tag if present */
++#ifdef BCM_OBJECT_TRACE
++void BCMFASTPATH
++osl_pktfree(osl_t *osh, void *p, bool send, int line, const char *caller)
++#else
++void BCMFASTPATH
++osl_pktfree(osl_t *osh, void *p, bool send)
++#endif /* BCM_OBJECT_TRACE */
++{
++	struct sk_buff *skb, *nskb;
++	if (osh == NULL)
++		return;
++
++	skb = (struct sk_buff*) p;
++
++	if (send && osh->pub.tx_fn)
++		osh->pub.tx_fn(osh->pub.tx_ctx, p, 0);
++
++	PKTDBG_TRACE(osh, (void *) skb, PKTLIST_PKTFREE);
++
++#if defined(CONFIG_DHD_USE_STATIC_BUF) && defined(DHD_USE_STATIC_CTRLBUF)
++	if (skb && (skb->mac_len == PREALLOC_USED_MAGIC)) {
++		printk("%s: pkt %p is from static pool\n",
++			__FUNCTION__, p);
++		dump_stack();
++		return;
++	}
++
++	if (skb && (skb->mac_len == PREALLOC_FREE_MAGIC)) {
++		printk("%s: pkt %p is from static pool and not in used\n",
++			__FUNCTION__, p);
++		dump_stack();
++		return;
++	}
++#endif /* CONFIG_DHD_USE_STATIC_BUF && DHD_USE_STATIC_CTRLBUF */
++
++	/* perversion: we use skb->next to chain multi-skb packets */
++	while (skb) {
++		nskb = skb->next;
++		skb->next = NULL;
++
++#ifdef BCMDBG_CTRACE
++		DEL_CTRACE(osh, skb);
++#endif
++
++
++#ifdef BCM_OBJECT_TRACE
++		bcm_object_trace_opr(skb, BCM_OBJDBG_REMOVE, caller, line);
++#endif /* BCM_OBJECT_TRACE */
++
++#ifdef CTFPOOL
++		if (PKTISFAST(osh, skb)) {
++			if (atomic_read(&skb->users) == 1)
++				smp_rmb();
++			else if (!atomic_dec_and_test(&skb->users))
++				goto next_skb;
++			osl_pktfastfree(osh, skb);
++		} else
++#endif
++		{
++			dev_kfree_skb_any(skb);
++		}
++#ifdef CTFPOOL
++next_skb:
++#endif
++		atomic_dec(&osh->cmn->pktalloced);
++		skb = nskb;
++	}
++}
++
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++void*
++osl_pktget_static(osl_t *osh, uint len)
++{
++	int i = 0;
++	struct sk_buff *skb;
++#ifdef DHD_USE_STATIC_CTRLBUF
++	unsigned long flags;
++#endif /* DHD_USE_STATIC_CTRLBUF */
++
++	if (!bcm_static_skb)
++		return osl_pktget(osh, len);
++
++	if (len > DHD_SKB_MAX_BUFSIZE) {
++		printk("%s: attempt to allocate huge packet (0x%x)\n", __FUNCTION__, len);
++		return osl_pktget(osh, len);
++	}
++
++#ifdef DHD_USE_STATIC_CTRLBUF
++	spin_lock_irqsave(&bcm_static_skb->osl_pkt_lock, flags);
++
++	if (len <= DHD_SKB_2PAGE_BUFSIZE) {
++		uint32 index;
++		for (i = 0; i < STATIC_PKT_2PAGE_NUM; i++) {
++			index = bcm_static_skb->last_allocated_index % STATIC_PKT_2PAGE_NUM;
++			bcm_static_skb->last_allocated_index++;
++			if (bcm_static_skb->skb_8k[index] &&
++				bcm_static_skb->pkt_use[index] == 0) {
++				break;
++			}
++		}
++
++		if ((i != STATIC_PKT_2PAGE_NUM) &&
++			(index >= 0) && (index < STATIC_PKT_2PAGE_NUM)) {
++			bcm_static_skb->pkt_use[index] = 1;
++			skb = bcm_static_skb->skb_8k[index];
++			skb->data = skb->head;
++#ifdef NET_SKBUFF_DATA_USES_OFFSET
++			skb_set_tail_pointer(skb, NET_SKB_PAD);
++#else
++			skb->tail = skb->data + NET_SKB_PAD;
++#endif /* NET_SKBUFF_DATA_USES_OFFSET */
++			skb->data += NET_SKB_PAD;
++			skb->cloned = 0;
++			skb->priority = 0;
++#ifdef NET_SKBUFF_DATA_USES_OFFSET
++			skb_set_tail_pointer(skb, len);
++#else
++			skb->tail = skb->data + len;
++#endif /* NET_SKBUFF_DATA_USES_OFFSET */
++			skb->len = len;
++			skb->mac_len = PREALLOC_USED_MAGIC;
++			spin_unlock_irqrestore(&bcm_static_skb->osl_pkt_lock, flags);
++			return skb;
++		}
++	}
++
++	spin_unlock_irqrestore(&bcm_static_skb->osl_pkt_lock, flags);
++	printk("%s: all static pkt in use!\n", __FUNCTION__);
++	return NULL;
++#else
++	down(&bcm_static_skb->osl_pkt_sem);
++
++	if (len <= DHD_SKB_1PAGE_BUFSIZE) {
++		for (i = 0; i < STATIC_PKT_MAX_NUM; i++) {
++			if (bcm_static_skb->skb_4k[i] &&
++				bcm_static_skb->pkt_use[i] == 0) {
++				break;
++			}
++		}
++
++		if (i != STATIC_PKT_MAX_NUM) {
++			bcm_static_skb->pkt_use[i] = 1;
++
++			skb = bcm_static_skb->skb_4k[i];
++#ifdef NET_SKBUFF_DATA_USES_OFFSET
++			skb_set_tail_pointer(skb, len);
++#else
++			skb->tail = skb->data + len;
++#endif /* NET_SKBUFF_DATA_USES_OFFSET */
++			skb->len = len;
++
++			up(&bcm_static_skb->osl_pkt_sem);
++			return skb;
++		}
++	}
++
++	if (len <= DHD_SKB_2PAGE_BUFSIZE) {
++		for (i = STATIC_PKT_1PAGE_NUM; i < STATIC_PKT_1_2PAGE_NUM; i++) {
++			if (bcm_static_skb->skb_8k[i - STATIC_PKT_1PAGE_NUM] &&
++				bcm_static_skb->pkt_use[i] == 0) {
++				break;
++			}
++		}
++
++		if ((i >= STATIC_PKT_1PAGE_NUM) && (i < STATIC_PKT_1_2PAGE_NUM)) {
++			bcm_static_skb->pkt_use[i] = 1;
++			skb = bcm_static_skb->skb_8k[i - STATIC_PKT_1PAGE_NUM];
++#ifdef NET_SKBUFF_DATA_USES_OFFSET
++			skb_set_tail_pointer(skb, len);
++#else
++			skb->tail = skb->data + len;
++#endif /* NET_SKBUFF_DATA_USES_OFFSET */
++			skb->len = len;
++
++			up(&bcm_static_skb->osl_pkt_sem);
++			return skb;
++		}
++	}
++
++#if defined(ENHANCED_STATIC_BUF)
++	if (bcm_static_skb->skb_16k &&
++		bcm_static_skb->pkt_use[STATIC_PKT_MAX_NUM - 1] == 0) {
++		bcm_static_skb->pkt_use[STATIC_PKT_MAX_NUM - 1] = 1;
++
++		skb = bcm_static_skb->skb_16k;
++#ifdef NET_SKBUFF_DATA_USES_OFFSET
++		skb_set_tail_pointer(skb, len);
++#else
++		skb->tail = skb->data + len;
++#endif /* NET_SKBUFF_DATA_USES_OFFSET */
++		skb->len = len;
++
++		up(&bcm_static_skb->osl_pkt_sem);
++		return skb;
++	}
++#endif /* ENHANCED_STATIC_BUF */
++
++	up(&bcm_static_skb->osl_pkt_sem);
++	printk("%s: all static pkt in use!\n", __FUNCTION__);
++	return osl_pktget(osh, len);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++}
++
++void
++osl_pktfree_static(osl_t *osh, void *p, bool send)
++{
++	int i;
++#ifdef DHD_USE_STATIC_CTRLBUF
++	struct sk_buff *skb = (struct sk_buff *)p;
++	unsigned long flags;
++#endif /* DHD_USE_STATIC_CTRLBUF */
++
++	if (!p) {
++		return;
++	}
++
++	if (!bcm_static_skb) {
++		osl_pktfree(osh, p, send);
++		return;
++	}
++
++#ifdef DHD_USE_STATIC_CTRLBUF
++	spin_lock_irqsave(&bcm_static_skb->osl_pkt_lock, flags);
++
++	for (i = 0; i < STATIC_PKT_2PAGE_NUM; i++) {
++		if (p == bcm_static_skb->skb_8k[i]) {
++			if (bcm_static_skb->pkt_use[i] == 0) {
++				printk("%s: static pkt idx %d(%p) is double free\n",
++					__FUNCTION__, i, p);
++			} else {
++				bcm_static_skb->pkt_use[i] = 0;
++			}
++
++			if (skb->mac_len != PREALLOC_USED_MAGIC) {
++				printk("%s: static pkt idx %d(%p) is not in used\n",
++					__FUNCTION__, i, p);
++			}
++
++			skb->mac_len = PREALLOC_FREE_MAGIC;
++			spin_unlock_irqrestore(&bcm_static_skb->osl_pkt_lock, flags);
++			return;
++		}
++	}
++
++	spin_unlock_irqrestore(&bcm_static_skb->osl_pkt_lock, flags);
++	printk("%s: packet %p does not exist in the pool\n", __FUNCTION__, p);
++#else
++	down(&bcm_static_skb->osl_pkt_sem);
++	for (i = 0; i < STATIC_PKT_1PAGE_NUM; i++) {
++		if (p == bcm_static_skb->skb_4k[i]) {
++			bcm_static_skb->pkt_use[i] = 0;
++			up(&bcm_static_skb->osl_pkt_sem);
++			return;
++		}
++	}
++
++	for (i = STATIC_PKT_1PAGE_NUM; i < STATIC_PKT_1_2PAGE_NUM; i++) {
++		if (p == bcm_static_skb->skb_8k[i - STATIC_PKT_1PAGE_NUM]) {
++			bcm_static_skb->pkt_use[i] = 0;
++			up(&bcm_static_skb->osl_pkt_sem);
++			return;
++		}
++	}
++#ifdef ENHANCED_STATIC_BUF
++	if (p == bcm_static_skb->skb_16k) {
++		bcm_static_skb->pkt_use[STATIC_PKT_MAX_NUM - 1] = 0;
++		up(&bcm_static_skb->osl_pkt_sem);
++		return;
++	}
++#endif
++	up(&bcm_static_skb->osl_pkt_sem);
++	osl_pktfree(osh, p, send);
++#endif /* DHD_USE_STATIC_CTRLBUF */
++}
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++
++uint32
++osl_pci_read_config(osl_t *osh, uint offset, uint size)
++{
++	uint val = 0;
++	uint retry = PCI_CFG_RETRY;
++
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++	/* only 4byte access supported */
++	ASSERT(size == 4);
++
++	do {
++		pci_read_config_dword(osh->pdev, offset, &val);
++		if (val != 0xffffffff)
++			break;
++	} while (retry--);
++
++
++	return (val);
++}
++
++void
++osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
++{
++	uint retry = PCI_CFG_RETRY;
++
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++	/* only 4byte access supported */
++	ASSERT(size == 4);
++
++	do {
++		pci_write_config_dword(osh->pdev, offset, val);
++		if (offset != PCI_BAR0_WIN)
++			break;
++		if (osl_pci_read_config(osh, offset, size) == val)
++			break;
++	} while (retry--);
++
++}
++
++/* return bus # for the pci device pointed by osh->pdev */
++uint
++osl_pci_bus(osl_t *osh)
++{
++	ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
++
++#if defined(__ARM_ARCH_7A__) && LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)
++	return pci_domain_nr(((struct pci_dev *)osh->pdev)->bus);
++#else
++	return ((struct pci_dev *)osh->pdev)->bus->number;
++#endif
++}
++
++/* return slot # for the pci device pointed by osh->pdev */
++uint
++osl_pci_slot(osl_t *osh)
++{
++	ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
++
++#if defined(__ARM_ARCH_7A__) && LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)
++	return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn) + 1;
++#else
++	return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
++#endif
++}
++
++/* return domain # for the pci device pointed by osh->pdev */
++uint
++osl_pcie_domain(osl_t *osh)
++{
++	ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
++
++	return pci_domain_nr(((struct pci_dev *)osh->pdev)->bus);
++}
++
++/* return bus # for the pci device pointed by osh->pdev */
++uint
++osl_pcie_bus(osl_t *osh)
++{
++	ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
++
++	return ((struct pci_dev *)osh->pdev)->bus->number;
++}
++
++/* return the pci device pointed by osh->pdev */
++struct pci_dev *
++osl_pci_device(osl_t *osh)
++{
++	ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
++
++	return osh->pdev;
++}
++
++static void
++osl_pcmcia_attr(osl_t *osh, uint offset, char *buf, int size, bool write)
++{
++}
++
++void
++osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size)
++{
++	osl_pcmcia_attr(osh, offset, (char *) buf, size, FALSE);
++}
++
++void
++osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size)
++{
++	osl_pcmcia_attr(osh, offset, (char *) buf, size, TRUE);
++}
++
++void *
++osl_malloc(osl_t *osh, uint size)
++{
++	void *addr;
++	gfp_t flags;
++
++	/* only ASSERT if osh is defined */
++	if (osh)
++		ASSERT(osh->magic == OS_HANDLE_MAGIC);
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++	if (bcm_static_buf)
++	{
++		unsigned long irq_flags;
++		int i = 0;
++		if ((size >= PAGE_SIZE)&&(size <= STATIC_BUF_SIZE))
++		{
++			spin_lock_irqsave(&bcm_static_buf->static_lock, irq_flags);
++
++			for (i = 0; i < STATIC_BUF_MAX_NUM; i++)
++			{
++				if (bcm_static_buf->buf_use[i] == 0)
++					break;
++			}
++
++			if (i == STATIC_BUF_MAX_NUM)
++			{
++				spin_unlock_irqrestore(&bcm_static_buf->static_lock, irq_flags);
++				printk("all static buff in use!\n");
++				goto original;
++			}
++
++			bcm_static_buf->buf_use[i] = 1;
++			spin_unlock_irqrestore(&bcm_static_buf->static_lock, irq_flags);
++
++			bzero(bcm_static_buf->buf_ptr+STATIC_BUF_SIZE*i, size);
++			if (osh)
++				atomic_add(size, &osh->cmn->malloced);
++
++			return ((void *)(bcm_static_buf->buf_ptr+STATIC_BUF_SIZE*i));
++		}
++	}
++original:
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++
++	flags = CAN_SLEEP() ? GFP_KERNEL: GFP_ATOMIC;
++	if ((addr = kmalloc(size, flags)) == NULL) {
++		if (osh)
++			osh->failed++;
++		return (NULL);
++	}
++	if (osh && osh->cmn)
++		atomic_add(size, &osh->cmn->malloced);
++
++	return (addr);
++}
++
++void *
++osl_mallocz(osl_t *osh, uint size)
++{
++	void *ptr;
++
++	ptr = osl_malloc(osh, size);
++
++	if (ptr != NULL) {
++		bzero(ptr, size);
++	}
++
++	return ptr;
++}
++
++void
++osl_mfree(osl_t *osh, void *addr, uint size)
++{
++#ifdef CONFIG_DHD_USE_STATIC_BUF
++	unsigned long flags;
++
++	if (bcm_static_buf)
++	{
++		if ((addr > (void *)bcm_static_buf) && ((unsigned char *)addr
++			<= ((unsigned char *)bcm_static_buf + STATIC_BUF_TOTAL_LEN)))
++		{
++			int buf_idx = 0;
++
++			buf_idx = ((unsigned char *)addr - bcm_static_buf->buf_ptr)/STATIC_BUF_SIZE;
++
++			spin_lock_irqsave(&bcm_static_buf->static_lock, flags);
++			bcm_static_buf->buf_use[buf_idx] = 0;
++			spin_unlock_irqrestore(&bcm_static_buf->static_lock, flags);
++
++			if (osh && osh->cmn) {
++				ASSERT(osh->magic == OS_HANDLE_MAGIC);
++				atomic_sub(size, &osh->cmn->malloced);
++			}
++			return;
++		}
++	}
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++	if (osh && osh->cmn) {
++		ASSERT(osh->magic == OS_HANDLE_MAGIC);
++
++		ASSERT(size <= osl_malloced(osh));
++
++		atomic_sub(size, &osh->cmn->malloced);
++	}
++	kfree(addr);
++}
++
++uint
++osl_check_memleak(osl_t *osh)
++{
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++	if (atomic_read(&osh->cmn->refcount) == 1)
++		return (atomic_read(&osh->cmn->malloced));
++	else
++		return 0;
++}
++
++uint
++osl_malloced(osl_t *osh)
++{
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++	return (atomic_read(&osh->cmn->malloced));
++}
++
++uint
++osl_malloc_failed(osl_t *osh)
++{
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++	return (osh->failed);
++}
++
++
++uint
++osl_dma_consistent_align(void)
++{
++	return (PAGE_SIZE);
++}
++
++void*
++osl_dma_alloc_consistent(osl_t *osh, uint size, uint16 align_bits, uint *alloced, dmaaddr_t *pap)
++{
++	void *va;
++	uint16 align = (1 << align_bits);
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++	if (!ISALIGNED(DMA_CONSISTENT_ALIGN, align))
++		size += align;
++	*alloced = size;
++
++#ifndef	BCM_SECURE_DMA
++#if defined(__ARM_ARCH_7A__) && !defined(DHD_USE_COHERENT_MEM_FOR_RING)
++	va = kmalloc(size, GFP_ATOMIC | __GFP_ZERO);
++	if (va)
++		*pap = (ulong)__virt_to_phys((ulong)va);
++#else
++	{
++		dma_addr_t pap_lin;
++		struct pci_dev *hwdev = osh->pdev;
++		gfp_t flags;
++#ifdef DHD_ALLOC_COHERENT_MEM_FROM_ATOMIC_POOL
++		flags = GFP_ATOMIC;
++#else
++		flags = CAN_SLEEP() ? GFP_KERNEL: GFP_ATOMIC;
++#endif /* DHD_ALLOC_COHERENT_MEM_FROM_ATOMIC_POOL */
++		va = dma_alloc_coherent(&hwdev->dev, size, &pap_lin, flags);
++		*pap = (dmaaddr_t)pap_lin;
++	}
++#endif /* __ARM_ARCH_7A__ && !DHD_USE_COHERENT_MEM_FOR_RING */
++#else
++	va = osl_sec_dma_alloc_consistent(osh, size, align_bits, pap);
++#endif /* BCM_SECURE_DMA */
++	return va;
++}
++
++void
++osl_dma_free_consistent(osl_t *osh, void *va, uint size, dmaaddr_t pa)
++{
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++#ifndef BCM_SECURE_DMA
++#if defined(__ARM_ARCH_7A__) && !defined(DHD_USE_COHERENT_MEM_FOR_RING)
++	kfree(va);
++#else
++	pci_free_consistent(osh->pdev, size, va, (dma_addr_t)pa);
++#endif /* __ARM_ARCH_7A__ && !DHD_USE_COHERENT_MEM_FOR_RING */
++#else
++	osl_sec_dma_free_consistent(osh, va, size, pa);
++#endif /* BCM_SECURE_DMA */
++}
++
++dmaaddr_t BCMFASTPATH
++osl_dma_map(osl_t *osh, void *va, uint size, int direction, void *p, hnddma_seg_map_t *dmah)
++{
++	int dir;
++
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++	dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
++
++
++
++
++	return (pci_map_single(osh->pdev, va, size, dir));
++}
++
++void BCMFASTPATH
++osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction)
++{
++	int dir;
++
++	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++
++	dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
++	pci_unmap_single(osh->pdev, (uint32)pa, size, dir);
++}
++
++/* OSL function for CPU relax */
++inline void BCMFASTPATH
++osl_cpu_relax(void)
++{
++	cpu_relax();
++}
++
++
++#if (defined(__ARM_ARCH_7A__) && !defined(DHD_USE_COHERENT_MEM_FOR_RING))
++
++inline void BCMFASTPATH
++osl_cache_flush(void *va, uint size)
++{
++
++	if (size > 0)
++		dma_sync_single_for_device(OSH_NULL, virt_to_dma(OSH_NULL, va), size, DMA_TX);
++}
++
++inline void BCMFASTPATH
++osl_cache_inv(void *va, uint size)
++{
++
++	dma_sync_single_for_cpu(OSH_NULL, virt_to_dma(OSH_NULL, va), size, DMA_RX);
++}
++
++inline void osl_prefetch(const void *ptr)
++{
++	__asm__ __volatile__("pld\t%0" :: "o"(*(const char *)ptr) : "cc");
++}
++
++int osl_arch_is_coherent(void)
++{
++	return 0;
++}
++
++
++inline int osl_acp_war_enab(void)
++{
++	return 0;
++}
++
++#endif 
++
++#if defined(BCMASSERT_LOG)
++void
++osl_assert(const char *exp, const char *file, int line)
++{
++	char tempbuf[256];
++	const char *basename;
++
++	basename = strrchr(file, '/');
++	/* skip the '/' */
++	if (basename)
++		basename++;
++
++	if (!basename)
++		basename = file;
++
++#ifdef BCMASSERT_LOG
++	snprintf(tempbuf, 64, "\"%s\": file \"%s\", line %d\n",
++		exp, basename, line);
++	printk("%s", tempbuf);
++#endif /* BCMASSERT_LOG */
++
++
++}
++#endif 
++
++void
++osl_delay(uint usec)
++{
++	uint d;
++
++	while (usec > 0) {
++		d = MIN(usec, 1000);
++		udelay(d);
++		usec -= d;
++	}
++}
++
++void
++osl_sleep(uint ms)
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
++	if (ms < 20)
++		usleep_range(ms*1000, ms*1000 + 1000);
++	else
++#endif
++	msleep(ms);
++}
++
++
++
++/* Clone a packet.
++ * The pkttag contents are NOT cloned.
++ */
++#ifdef BCMDBG_CTRACE
++void *
++osl_pktdup(osl_t *osh, void *skb, int line, char *file)
++#else
++#ifdef BCM_OBJECT_TRACE
++void *
++osl_pktdup(osl_t *osh, void *skb, int line, const char *caller)
++#else
++void *
++osl_pktdup(osl_t *osh, void *skb)
++#endif /* BCM_OBJECT_TRACE */
++#endif /* BCMDBG_CTRACE */
++{
++	void * p;
++
++	ASSERT(!PKTISCHAINED(skb));
++
++	/* clear the CTFBUF flag if set and map the rest of the buffer
++	 * before cloning.
++	 */
++	PKTCTFMAP(osh, skb);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
++	if ((p = pskb_copy((struct sk_buff *)skb, GFP_ATOMIC)) == NULL)
++#else
++	if ((p = skb_clone((struct sk_buff *)skb, GFP_ATOMIC)) == NULL)
++#endif
++		return NULL;
++
++#ifdef CTFPOOL
++	if (PKTISFAST(osh, skb)) {
++		ctfpool_t *ctfpool;
++
++		/* if the buffer allocated from ctfpool is cloned then
++		 * we can't be sure when it will be freed. since there
++		 * is a chance that we will be losing a buffer
++		 * from our pool, we increment the refill count for the
++		 * object to be alloced later.
++		 */
++		ctfpool = (ctfpool_t *)CTFPOOLPTR(osh, skb);
++		ASSERT(ctfpool != NULL);
++		PKTCLRFAST(osh, p);
++		PKTCLRFAST(osh, skb);
++		ctfpool->refills++;
++	}
++#endif /* CTFPOOL */
++
++	/* Clear PKTC  context */
++	PKTSETCLINK(p, NULL);
++	PKTCCLRFLAGS(p);
++	PKTCSETCNT(p, 1);
++	PKTCSETLEN(p, PKTLEN(osh, skb));
++
++	/* skb_clone copies skb->cb.. we don't want that */
++	if (osh->pub.pkttag)
++		OSL_PKTTAG_CLEAR(p);
++
++	/* Increment the packet counter */
++	atomic_inc(&osh->cmn->pktalloced);
++#ifdef BCM_OBJECT_TRACE
++	bcm_object_trace_opr(p, BCM_OBJDBG_ADD_PKT, caller, line);
++#endif /* BCM_OBJECT_TRACE */
++
++#ifdef BCMDBG_CTRACE
++	ADD_CTRACE(osh, (struct sk_buff *)p, file, line);
++#endif
++	return (p);
++}
++
++#ifdef BCMDBG_CTRACE
++int osl_pkt_is_frmnative(osl_t *osh, struct sk_buff *pkt)
++{
++	unsigned long flags;
++	struct sk_buff *skb;
++	int ck = FALSE;
++
++	spin_lock_irqsave(&osh->ctrace_lock, flags);
++
++	list_for_each_entry(skb, &osh->ctrace_list, ctrace_list) {
++		if (pkt == skb) {
++			ck = TRUE;
++			break;
++		}
++	}
++
++	spin_unlock_irqrestore(&osh->ctrace_lock, flags);
++	return ck;
++}
++
++void osl_ctrace_dump(osl_t *osh, struct bcmstrbuf *b)
++{
++	unsigned long flags;
++	struct sk_buff *skb;
++	int idx = 0;
++	int i, j;
++
++	spin_lock_irqsave(&osh->ctrace_lock, flags);
++
++	if (b != NULL)
++		bcm_bprintf(b, " Total %d sbk not free\n", osh->ctrace_num);
++	else
++		printk(" Total %d sbk not free\n", osh->ctrace_num);
++
++	list_for_each_entry(skb, &osh->ctrace_list, ctrace_list) {
++		if (b != NULL)
++			bcm_bprintf(b, "[%d] skb %p:\n", ++idx, skb);
++		else
++			printk("[%d] skb %p:\n", ++idx, skb);
++
++		for (i = 0; i < skb->ctrace_count; i++) {
++			j = (skb->ctrace_start + i) % CTRACE_NUM;
++			if (b != NULL)
++				bcm_bprintf(b, "    [%s(%d)]\n", skb->func[j], skb->line[j]);
++			else
++				printk("    [%s(%d)]\n", skb->func[j], skb->line[j]);
++		}
++		if (b != NULL)
++			bcm_bprintf(b, "\n");
++		else
++			printk("\n");
++	}
++
++	spin_unlock_irqrestore(&osh->ctrace_lock, flags);
++
++	return;
++}
++#endif /* BCMDBG_CTRACE */
++
++
++/*
++ * OSLREGOPS specifies the use of osl_XXX routines to be used for register access
++ */
++
++/*
++ * BINOSL selects the slightly slower function-call-based binary compatible osl.
++ */
++
++uint
++osl_pktalloced(osl_t *osh)
++{
++	if (atomic_read(&osh->cmn->refcount) == 1)
++		return (atomic_read(&osh->cmn->pktalloced));
++	else
++		return 0;
++}
++
++uint32
++osl_rand(void)
++{
++	uint32 rand;
++
++	get_random_bytes(&rand, sizeof(rand));
++
++	return rand;
++}
++
++/* Linux Kernel: File Operations: start */
++void *
++osl_os_open_image(char *filename)
++{
++	struct file *fp;
++
++	fp = filp_open(filename, O_RDONLY, 0);
++	/*
++	 * 2.6.11 (FC4) supports filp_open() but later revs don't?
++	 * Alternative:
++	 * fp = open_namei(AT_FDCWD, filename, O_RD, 0);
++	 * ???
++	 */
++	 if (IS_ERR(fp))
++		 fp = NULL;
++
++	 return fp;
++}
++
++int
++osl_os_get_image_block(char *buf, int len, void *image)
++{
++	struct file *fp = (struct file *)image;
++	int rdlen;
++	loff_t pos;
++
++	if (!image)
++		return 0;
++
++	pos = fp->f_pos;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
++	rdlen = kernel_read(fp, (void *) buf, (size_t) len, (loff_t *) &pos);
++#else
++	rdlen = kernel_read(fp, pos, buf, len);
++#endif
++	if (rdlen > 0)
++		fp->f_pos += rdlen;
++
++	return rdlen;
++}
++
++void
++osl_os_close_image(void *image)
++{
++	if (image)
++		filp_close((struct file *)image, NULL);
++}
++
++int
++osl_os_image_size(void *image)
++{
++	int len = 0, curroffset;
++
++	if (image) {
++		/* store the current offset */
++		curroffset = generic_file_llseek(image, 0, 1);
++		/* goto end of file to get length */
++		len = generic_file_llseek(image, 0, 2);
++		/* restore back the offset */
++		generic_file_llseek(image, curroffset, 0);
++	}
++	return len;
++}
++
++/* Linux Kernel: File Operations: end */
++
++#if (defined(STB) && defined(__arm__))
++inline void osl_pcie_rreg(osl_t *osh, ulong addr, void *v, uint size)
++{
++	unsigned long flags = 0;
++	int pci_access = 0;
++
++	if (osh && BUSTYPE(osh->bustype) == PCI_BUS)
++		pci_access = 1;
++
++	if (pci_access && ACP_WAR_ENAB())
++		spin_lock_irqsave(&l2x0_reg_lock, flags);
++
++	switch (size) {
++	case sizeof(uint8):
++		*(uint8*)v = readb((volatile uint8*)(addr));
++		break;
++	case sizeof(uint16):
++		*(uint16*)v = readw((volatile uint16*)(addr));
++		break;
++	case sizeof(uint32):
++		*(uint32*)v = readl((volatile uint32*)(addr));
++		break;
++	case sizeof(uint64):
++		*(uint64*)v = *((volatile uint64*)(addr));
++		break;
++	}
++
++	if (pci_access && ACP_WAR_ENAB())
++		spin_unlock_irqrestore(&l2x0_reg_lock, flags);
++}
++#endif 
++
++/* APIs to set/get specific quirks in OSL layer */
++void
++osl_flag_set(osl_t *osh, uint32 mask)
++{
++	osh->flags |= mask;
++}
++
++#if defined(STB)
++inline bool BCMFASTPATH
++#else
++bool
++#endif 
++osl_is_flag_set(osl_t *osh, uint32 mask)
++{
++	return (osh->flags & mask);
++}
++
++#ifdef BCM_SECURE_DMA
++static void *
++osl_sec_dma_ioremap(osl_t *osh, struct page *page, size_t size, bool iscache, bool isdecr)
++{
++
++	struct page **map;
++	int order, i;
++	void *addr = NULL;
++
++	size = PAGE_ALIGN(size);
++	order = get_order(size);
++
++	map = kmalloc(sizeof(struct page *) << order, GFP_ATOMIC);
++
++	if (map == NULL)
++		return NULL;
++
++	for (i = 0; i < (size >> PAGE_SHIFT); i++)
++		map[i] = page + i;
++
++	if (iscache) {
++		addr = vmap(map, size >> PAGE_SHIFT, VM_MAP, __pgprot(PAGE_KERNEL));
++		if (isdecr) {
++			osh->contig_delta_va_pa = (phys_addr_t)(addr - page_to_phys(page));
++		}
++	}
++	else {
++
++#if defined(__ARM_ARCH_7A__)
++		addr = vmap(map, size >> PAGE_SHIFT, VM_MAP,
++			pgprot_noncached(__pgprot(PAGE_KERNEL)));
++#endif
++		if (isdecr) {
++			osh->contig_delta_va_pa = (phys_addr_t)(addr - page_to_phys(page));
++		}
++	}
++
++	kfree(map);
++	return (void *)addr;
++}
++
++static void
++osl_sec_dma_iounmap(osl_t *osh, void *contig_base_va, size_t size)
++{
++	vunmap(contig_base_va);
++}
++
++static int
++osl_sec_dma_init_elem_mem_block(osl_t *osh, size_t mbsize, int max, sec_mem_elem_t **list)
++{
++	int i;
++	int ret = BCME_OK;
++	sec_mem_elem_t *sec_mem_elem;
++
++	if ((sec_mem_elem = kmalloc(sizeof(sec_mem_elem_t)*(max), GFP_ATOMIC)) != NULL) {
++
++		*list = sec_mem_elem;
++		bzero(sec_mem_elem, sizeof(sec_mem_elem_t)*(max));
++		for (i = 0; i < max-1; i++) {
++			sec_mem_elem->next = (sec_mem_elem + 1);
++			sec_mem_elem->size = mbsize;
++			sec_mem_elem->pa_cma = osh->contig_base_alloc;
++			sec_mem_elem->vac = osh->contig_base_alloc_va;
++
++			sec_mem_elem->pa_cma_page = phys_to_page(sec_mem_elem->pa_cma);
++			osh->contig_base_alloc += mbsize;
++			osh->contig_base_alloc_va = ((uint8 *)osh->contig_base_alloc_va +  mbsize);
++
++			sec_mem_elem = sec_mem_elem + 1;
++		}
++		sec_mem_elem->next = NULL;
++		sec_mem_elem->size = mbsize;
++		sec_mem_elem->pa_cma = osh->contig_base_alloc;
++		sec_mem_elem->vac = osh->contig_base_alloc_va;
++
++		sec_mem_elem->pa_cma_page = phys_to_page(sec_mem_elem->pa_cma);
++		osh->contig_base_alloc += mbsize;
++		osh->contig_base_alloc_va = ((uint8 *)osh->contig_base_alloc_va +  mbsize);
++
++	} else {
++		printf("%s sec mem elem kmalloc failed\n", __FUNCTION__);
++		ret = BCME_ERROR;
++	}
++	return ret;
++}
++
++
++static void
++osl_sec_dma_deinit_elem_mem_block(osl_t *osh, size_t mbsize, int max, void *sec_list_base)
++{
++	if (sec_list_base)
++		kfree(sec_list_base);
++}
++
++static sec_mem_elem_t * BCMFASTPATH
++osl_sec_dma_alloc_mem_elem(osl_t *osh, void *va, uint size, int direction,
++	struct sec_cma_info *ptr_cma_info, uint offset)
++{
++	sec_mem_elem_t *sec_mem_elem = NULL;
++
++		ASSERT(osh->sec_list_4096);
++		sec_mem_elem = osh->sec_list_4096;
++		osh->sec_list_4096 = sec_mem_elem->next;
++
++		sec_mem_elem->next = NULL;
++
++	if (ptr_cma_info->sec_alloc_list_tail) {
++		ptr_cma_info->sec_alloc_list_tail->next = sec_mem_elem;
++		ptr_cma_info->sec_alloc_list_tail = sec_mem_elem;
++	}
++	else {
++		/* First allocation: If tail is NULL, sec_alloc_list MUST also be NULL */
++		ASSERT(ptr_cma_info->sec_alloc_list == NULL);
++		ptr_cma_info->sec_alloc_list = sec_mem_elem;
++		ptr_cma_info->sec_alloc_list_tail = sec_mem_elem;
++	}
++	return sec_mem_elem;
++}
++
++static void BCMFASTPATH
++osl_sec_dma_free_mem_elem(osl_t *osh, sec_mem_elem_t *sec_mem_elem)
++{
++	sec_mem_elem->dma_handle = 0x0;
++	sec_mem_elem->va = NULL;
++		sec_mem_elem->next = osh->sec_list_4096;
++		osh->sec_list_4096 = sec_mem_elem;
++}
++
++static sec_mem_elem_t * BCMFASTPATH
++osl_sec_dma_find_rem_elem(osl_t *osh, struct sec_cma_info *ptr_cma_info, dma_addr_t dma_handle)
++{
++	sec_mem_elem_t *sec_mem_elem = ptr_cma_info->sec_alloc_list;
++	sec_mem_elem_t *sec_prv_elem = ptr_cma_info->sec_alloc_list;
++
++	if (!sec_mem_elem) {
++		printk("osl_sec_dma_find_rem_elem ptr_cma_info->sec_alloc_list is NULL \n");
++		return NULL;
++	}
++
++	if (sec_mem_elem->dma_handle == dma_handle) {
++
++		ptr_cma_info->sec_alloc_list = sec_mem_elem->next;
++
++		if (sec_mem_elem == ptr_cma_info->sec_alloc_list_tail) {
++			ptr_cma_info->sec_alloc_list_tail = NULL;
++			ASSERT(ptr_cma_info->sec_alloc_list == NULL);
++		}
++
++		return sec_mem_elem;
++	}
++	sec_mem_elem = sec_mem_elem->next;
++
++	while (sec_mem_elem != NULL) {
++
++		if (sec_mem_elem->dma_handle == dma_handle) {
++
++			sec_prv_elem->next = sec_mem_elem->next;
++			if (sec_mem_elem == ptr_cma_info->sec_alloc_list_tail)
++				ptr_cma_info->sec_alloc_list_tail = sec_prv_elem;
++
++			return sec_mem_elem;
++		}
++		sec_prv_elem = sec_mem_elem;
++		sec_mem_elem = sec_mem_elem->next;
++	}
++	return NULL;
++}
++
++static sec_mem_elem_t *
++osl_sec_dma_rem_first_elem(osl_t *osh, struct sec_cma_info *ptr_cma_info)
++{
++	sec_mem_elem_t *sec_mem_elem = ptr_cma_info->sec_alloc_list;
++
++	if (sec_mem_elem) {
++
++		ptr_cma_info->sec_alloc_list = sec_mem_elem->next;
++
++		if (ptr_cma_info->sec_alloc_list == NULL)
++			ptr_cma_info->sec_alloc_list_tail = NULL;
++
++		return sec_mem_elem;
++
++	} else
++		return NULL;
++}
++
++static void * BCMFASTPATH
++osl_sec_dma_last_elem(osl_t *osh, struct sec_cma_info *ptr_cma_info)
++{
++	return ptr_cma_info->sec_alloc_list_tail;
++}
++
++dma_addr_t BCMFASTPATH
++osl_sec_dma_map_txmeta(osl_t *osh, void *va, uint size, int direction, void *p,
++	hnddma_seg_map_t *dmah, void *ptr_cma_info)
++{
++	sec_mem_elem_t *sec_mem_elem;
++	struct page *pa_cma_page;
++	uint loffset;
++	void *vaorig = ((uint8 *)va + size);
++	dma_addr_t dma_handle = 0x0;
++	/* packet will be the one added with osl_sec_dma_map() just before this call */
++
++	sec_mem_elem = osl_sec_dma_last_elem(osh, ptr_cma_info);
++
++	if (sec_mem_elem && sec_mem_elem->va == vaorig) {
++
++		pa_cma_page = phys_to_page(sec_mem_elem->pa_cma);
++		loffset = sec_mem_elem->pa_cma -(sec_mem_elem->pa_cma & ~(PAGE_SIZE-1));
++
++		dma_handle = dma_map_page(OSH_NULL, pa_cma_page, loffset, size,
++			(direction == DMA_TX ? DMA_TO_DEVICE:DMA_FROM_DEVICE));
++
++	} else {
++		printf("%s: error orig va not found va = 0x%p \n",
++			__FUNCTION__, vaorig);
++	}
++	return dma_handle;
++}
++
++dma_addr_t BCMFASTPATH
++osl_sec_dma_map(osl_t *osh, void *va, uint size, int direction, void *p,
++	hnddma_seg_map_t *dmah, void *ptr_cma_info, uint offset)
++{
++
++	sec_mem_elem_t *sec_mem_elem;
++	struct page *pa_cma_page;
++	void *pa_cma_kmap_va = NULL;
++	uint buflen = 0;
++	dma_addr_t dma_handle = 0x0;
++	uint loffset;
++
++	ASSERT((direction == DMA_RX) || (direction == DMA_TX));
++	sec_mem_elem = osl_sec_dma_alloc_mem_elem(osh, va, size, direction, ptr_cma_info, offset);
++
++	sec_mem_elem->va = va;
++	sec_mem_elem->direction = direction;
++	pa_cma_page = sec_mem_elem->pa_cma_page;
++
++	loffset = sec_mem_elem->pa_cma -(sec_mem_elem->pa_cma & ~(PAGE_SIZE-1));
++	/* pa_cma_kmap_va = kmap_atomic(pa_cma_page);
++	* pa_cma_kmap_va += loffset;
++	*/
++
++	pa_cma_kmap_va = sec_mem_elem->vac;
++	pa_cma_kmap_va = ((uint8 *)pa_cma_kmap_va + offset);
++	buflen = size;
++
++	if (direction == DMA_TX) {
++		memcpy((uint8*)pa_cma_kmap_va+offset, va, size);
++
++		if (dmah) {
++			dmah->nsegs = 1;
++			dmah->origsize = buflen;
++		}
++	}
++	else
++	{
++		if ((p != NULL) && (dmah != NULL)) {
++			dmah->nsegs = 1;
++			dmah->origsize = buflen;
++		}
++	}
++
++		dma_handle = dma_map_page(OSH_NULL, pa_cma_page, loffset+offset, buflen,
++			(direction == DMA_TX ? DMA_TO_DEVICE:DMA_FROM_DEVICE));
++
++	if (dmah) {
++		dmah->segs[0].addr = dma_handle;
++		dmah->segs[0].length = buflen;
++	}
++	sec_mem_elem->dma_handle = dma_handle;
++	/* kunmap_atomic(pa_cma_kmap_va-loffset); */
++	return dma_handle;
++}
++
++dma_addr_t BCMFASTPATH
++osl_sec_dma_dd_map(osl_t *osh, void *va, uint size, int direction, void *p, hnddma_seg_map_t *map)
++{
++
++	struct page *pa_cma_page;
++	phys_addr_t pa_cma;
++	dma_addr_t dma_handle = 0x0;
++	uint loffset;
++
++	pa_cma = (phys_addr_t)(va - osh->contig_delta_va_pa);
++	pa_cma_page = phys_to_page(pa_cma);
++	loffset = pa_cma -(pa_cma & ~(PAGE_SIZE-1));
++
++	dma_handle = dma_map_page(OSH_NULL, pa_cma_page, loffset, size,
++		(direction == DMA_TX ? DMA_TO_DEVICE:DMA_FROM_DEVICE));
++
++	return dma_handle;
++}
++
++void BCMFASTPATH
++osl_sec_dma_unmap(osl_t *osh, dma_addr_t dma_handle, uint size, int direction,
++void *p, hnddma_seg_map_t *map,	void *ptr_cma_info, uint offset)
++{
++	sec_mem_elem_t *sec_mem_elem;
++	struct page *pa_cma_page;
++	void *pa_cma_kmap_va = NULL;
++	uint buflen = 0;
++	dma_addr_t pa_cma;
++	void *va;
++	int read_count = 0;
++	BCM_REFERENCE(buflen);
++	BCM_REFERENCE(read_count);
++
++	sec_mem_elem = osl_sec_dma_find_rem_elem(osh, ptr_cma_info, dma_handle);
++	ASSERT(sec_mem_elem);
++
++	va = sec_mem_elem->va;
++	va = (uint8 *)va - offset;
++	pa_cma = sec_mem_elem->pa_cma;
++
++	pa_cma_page = sec_mem_elem->pa_cma_page;
++
++
++	if (direction == DMA_RX) {
++
++		if (p == NULL) {
++
++			/* pa_cma_kmap_va = kmap_atomic(pa_cma_page);
++			* pa_cma_kmap_va += loffset;
++			*/
++
++			pa_cma_kmap_va = sec_mem_elem->vac;
++
++			dma_unmap_page(OSH_NULL, pa_cma, size, DMA_FROM_DEVICE);
++			memcpy(va, pa_cma_kmap_va, size);
++			/* kunmap_atomic(pa_cma_kmap_va); */
++		}
++	} else {
++		dma_unmap_page(OSH_NULL, pa_cma, size+offset, DMA_TO_DEVICE);
++	}
++
++	osl_sec_dma_free_mem_elem(osh, sec_mem_elem);
++}
++
++void
++osl_sec_dma_unmap_all(osl_t *osh, void *ptr_cma_info)
++{
++
++	sec_mem_elem_t *sec_mem_elem;
++
++	sec_mem_elem = osl_sec_dma_rem_first_elem(osh, ptr_cma_info);
++
++	while (sec_mem_elem != NULL) {
++
++		dma_unmap_page(OSH_NULL, sec_mem_elem->pa_cma, sec_mem_elem->size,
++			sec_mem_elem->direction == DMA_TX ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
++		osl_sec_dma_free_mem_elem(osh, sec_mem_elem);
++
++		sec_mem_elem = osl_sec_dma_rem_first_elem(osh, ptr_cma_info);
++	}
++}
++
++static void
++osl_sec_dma_init_consistent(osl_t *osh)
++{
++	int i;
++	void *temp_va = osh->contig_base_alloc_coherent_va;
++	phys_addr_t temp_pa = osh->contig_base_alloc_coherent;
++
++	for (i = 0; i < SEC_CMA_COHERENT_MAX; i++) {
++		osh->sec_cma_coherent[i].avail = TRUE;
++		osh->sec_cma_coherent[i].va = temp_va;
++		osh->sec_cma_coherent[i].pa = temp_pa;
++		temp_va += SEC_CMA_COHERENT_BLK;
++		temp_pa += SEC_CMA_COHERENT_BLK;
++	}
++}
++
++static void *
++osl_sec_dma_alloc_consistent(osl_t *osh, uint size, uint16 align_bits, ulong *pap)
++{
++
++	void *temp_va = NULL;
++	ulong temp_pa = 0;
++	int i;
++
++	if (size > SEC_CMA_COHERENT_BLK) {
++		printf("%s unsupported size\n", __FUNCTION__);
++		return NULL;
++	}
++
++	for (i = 0; i < SEC_CMA_COHERENT_MAX; i++) {
++		if (osh->sec_cma_coherent[i].avail == TRUE) {
++			temp_va = osh->sec_cma_coherent[i].va;
++			temp_pa = osh->sec_cma_coherent[i].pa;
++			osh->sec_cma_coherent[i].avail = FALSE;
++			break;
++		}
++	}
++
++	if (i == SEC_CMA_COHERENT_MAX)
++		printf("%s:No coherent mem: va = 0x%p pa = 0x%lx size = %d\n", __FUNCTION__,
++			temp_va, (ulong)temp_pa, size);
++
++	*pap = (unsigned long)temp_pa;
++	return temp_va;
++}
++
++static void
++osl_sec_dma_free_consistent(osl_t *osh, void *va, uint size, dmaaddr_t pa)
++{
++	int i = 0;
++
++	for (i = 0; i < SEC_CMA_COHERENT_MAX; i++) {
++		if (osh->sec_cma_coherent[i].va == va) {
++			osh->sec_cma_coherent[i].avail = TRUE;
++			break;
++		}
++	}
++	if (i == SEC_CMA_COHERENT_MAX)
++		printf("%s:Error: va = 0x%p pa = 0x%lx size = %d\n", __FUNCTION__,
++			va, (ulong)pa, size);
++}
++
++#endif /* BCM_SECURE_DMA */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0) && defined(TSQ_MULTIPLIER)
++#include <linux/kallsyms.h>
++#include <net/sock.h>
++void
++osl_pkt_orphan_partial(struct sk_buff *skb)
++{
++	uint32 fraction;
++	static void *p_tcp_wfree = NULL;
++
++	if (!skb->destructor || skb->destructor == sock_wfree)
++		return;
++
++	if (unlikely(!p_tcp_wfree)) {
++		char sym[KSYM_SYMBOL_LEN];
++		sprint_symbol(sym, (unsigned long)skb->destructor);
++		sym[9] = 0;
++		if (!strcmp(sym, "tcp_wfree"))
++			p_tcp_wfree = skb->destructor;
++		else
++			return;
++	}
++
++	if (unlikely(skb->destructor != p_tcp_wfree || !skb->sk))
++		return;
++
++	/* abstract a certain portion of skb truesize from the socket
++	 * sk_wmem_alloc to allow more skb can be allocated for this
++	 * socket for better cusion meeting WiFi device requirement
++	 */
++	fraction = skb->truesize * (TSQ_MULTIPLIER - 1) / TSQ_MULTIPLIER;
++	skb->truesize -= fraction;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 13, 0))
++	WARN_ON(refcount_sub_and_test(fraction, &skb->sk->sk_wmem_alloc));
++#else
++	atomic_sub(fraction, &skb->sk->sk_wmem_alloc);
++#endif
++}
++#endif /* LINUX_VERSION >= 3.6.0 && TSQ_MULTIPLIER */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/pcie_core.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/pcie_core.c
+new file mode 100644
+index 000000000..932630df4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/pcie_core.c
+@@ -0,0 +1,115 @@
++/** @file pcie_core.c
++ *
++ * Contains PCIe related functions that are shared between different driver models (e.g. firmware
++ * builds, DHD builds, BMAC builds), in order to avoid code duplication.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: pcie_core.c 444841 2013-12-21 04:32:29Z $
++ */
++
++#include <bcm_cfg.h>
++#include <typedefs.h>
++#include <bcmutils.h>
++#include <bcmdefs.h>
++#include <osl.h>
++#include <siutils.h>
++#include <hndsoc.h>
++#include <sbchipc.h>
++
++#include "pcie_core.h"
++
++/* local prototypes */
++
++/* local variables */
++
++/* function definitions */
++
++#ifdef BCMDRIVER
++
++void pcie_watchdog_reset(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs)
++{
++	uint32 val, i, lsc;
++	uint16 cfg_offset[] = {PCIECFGREG_STATUS_CMD, PCIECFGREG_PM_CSR,
++		PCIECFGREG_MSI_CAP, PCIECFGREG_MSI_ADDR_L,
++		PCIECFGREG_MSI_ADDR_H, PCIECFGREG_MSI_DATA,
++		PCIECFGREG_LINK_STATUS_CTRL2, PCIECFGREG_RBAR_CTRL,
++		PCIECFGREG_PML1_SUB_CTRL1, PCIECFGREG_REG_BAR2_CONFIG,
++		PCIECFGREG_REG_BAR3_CONFIG};
++	sbpcieregs_t *pcie = NULL;
++	uint32 origidx = si_coreidx(sih);
++
++	/* Switch to PCIE2 core */
++	pcie = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0);
++	BCM_REFERENCE(pcie);
++	ASSERT(pcie != NULL);
++
++	/* Disable/restore ASPM Control to protect the watchdog reset */
++	W_REG(osh, &sbpcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL);
++	lsc = R_REG(osh, &sbpcieregs->configdata);
++	val = lsc & (~PCIE_ASPM_ENAB);
++	W_REG(osh, &sbpcieregs->configdata, val);
++
++	si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, 4);
++	OSL_DELAY(100000);
++
++	W_REG(osh, &sbpcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL);
++	W_REG(osh, &sbpcieregs->configdata, lsc);
++
++	if (sih->buscorerev <= 13) {
++		/* Write configuration registers back to the shadow registers
++		 * cause shadow registers are cleared out after watchdog reset.
++		 */
++		for (i = 0; i < ARRAYSIZE(cfg_offset); i++) {
++			W_REG(osh, &sbpcieregs->configaddr, cfg_offset[i]);
++			val = R_REG(osh, &sbpcieregs->configdata);
++			W_REG(osh, &sbpcieregs->configdata, val);
++		}
++	}
++	si_setcoreidx(sih, origidx);
++}
++
++
++/* CRWLPCIEGEN2-117 pcie_pipe_Iddq should be controlled
++ * by the L12 state from MAC to save power by putting the
++ * SerDes analog in IDDQ mode
++ */
++void  pcie_serdes_iddqdisable(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs)
++{
++	sbpcieregs_t *pcie = NULL;
++	uint crwlpciegen2_117_disable = 0;
++	uint32 origidx = si_coreidx(sih);
++
++	crwlpciegen2_117_disable = PCIE_PipeIddqDisable0 | PCIE_PipeIddqDisable1;
++	/* Switch to PCIE2 core */
++	pcie = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0);
++	BCM_REFERENCE(pcie);
++	ASSERT(pcie != NULL);
++
++	OR_REG(osh, &sbpcieregs->control,
++		crwlpciegen2_117_disable);
++
++	si_setcoreidx(sih, origidx);
++}
++#endif /* BCMDRIVER */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/sbutils.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/sbutils.c
+new file mode 100644
+index 000000000..75fb1ea5b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/sbutils.c
+@@ -0,0 +1,1108 @@
++/*
++ * Misc utility routines for accessing chip-specific features
++ * of the SiliconBackplane-based Broadcom chips.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: sbutils.c 514727 2014-11-12 03:02:48Z $
++ */
++
++#include <bcm_cfg.h>
++#include <typedefs.h>
++#include <bcmdefs.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <siutils.h>
++#include <bcmdevs.h>
++#include <hndsoc.h>
++#include <sbchipc.h>
++#include <pcicfg.h>
++#include <sbpcmcia.h>
++
++#include "siutils_priv.h"
++
++
++/* local prototypes */
++static uint _sb_coreidx(si_info_t *sii, uint32 sba);
++static uint _sb_scan(si_info_t *sii, uint32 sba, void *regs, uint bus, uint32 sbba,
++                     uint ncores);
++static uint32 _sb_coresba(si_info_t *sii);
++static void *_sb_setcoreidx(si_info_t *sii, uint coreidx);
++#define	SET_SBREG(sii, r, mask, val)	\
++		W_SBREG((sii), (r), ((R_SBREG((sii), (r)) & ~(mask)) | (val)))
++#define	REGS2SB(va)	(sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
++
++/* sonicsrev */
++#define	SONICS_2_2	(SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
++#define	SONICS_2_3	(SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
++
++#define	R_SBREG(sii, sbr)	sb_read_sbreg((sii), (sbr))
++#define	W_SBREG(sii, sbr, v)	sb_write_sbreg((sii), (sbr), (v))
++#define	AND_SBREG(sii, sbr, v)	W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) & (v)))
++#define	OR_SBREG(sii, sbr, v)	W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) | (v)))
++
++static uint32
++sb_read_sbreg(si_info_t *sii, volatile uint32 *sbr)
++{
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint8 tmp;
++	uint32 val, intr_val = 0;
++
++
++	/*
++	 * compact flash only has 11 bits address, while we needs 12 bits address.
++	 * MEM_SEG will be OR'd with other 11 bits address in hardware,
++	 * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
++	 * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
++	 */
++	if (PCMCIA(sii)) {
++		INTR_OFF(sii, intr_val);
++		tmp = 1;
++		OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
++		sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
++	}
++
++	val = R_REG(sii->osh, sbr);
++
++	if (PCMCIA(sii)) {
++		tmp = 0;
++		OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
++		INTR_RESTORE(sii, intr_val);
++	}
++
++	return (val);
++}
++
++static void
++sb_write_sbreg(si_info_t *sii, volatile uint32 *sbr, uint32 v)
++{
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint8 tmp;
++	volatile uint32 dummy;
++	uint32 intr_val = 0;
++
++
++	/*
++	 * compact flash only has 11 bits address, while we needs 12 bits address.
++	 * MEM_SEG will be OR'd with other 11 bits address in hardware,
++	 * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
++	 * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
++	 */
++	if (PCMCIA(sii)) {
++		INTR_OFF(sii, intr_val);
++		tmp = 1;
++		OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
++		sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
++	}
++
++	if (BUSTYPE(sii->pub.bustype) == PCMCIA_BUS) {
++		dummy = R_REG(sii->osh, sbr);
++		BCM_REFERENCE(dummy);
++		W_REG(sii->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
++		dummy = R_REG(sii->osh, sbr);
++		BCM_REFERENCE(dummy);
++		W_REG(sii->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
++	} else
++		W_REG(sii->osh, sbr, v);
++
++	if (PCMCIA(sii)) {
++		tmp = 0;
++		OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
++		INTR_RESTORE(sii, intr_val);
++	}
++}
++
++uint
++sb_coreid(si_t *sih)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	return ((R_SBREG(sii, &sb->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
++}
++
++uint
++sb_intflag(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	void *corereg;
++	sbconfig_t *sb;
++	uint origidx, intflag, intr_val = 0;
++
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++	corereg = si_setcore(sih, CC_CORE_ID, 0);
++	ASSERT(corereg != NULL);
++	sb = REGS2SB(corereg);
++	intflag = R_SBREG(sii, &sb->sbflagst);
++	sb_setcoreidx(sih, origidx);
++	INTR_RESTORE(sii, intr_val);
++
++	return intflag;
++}
++
++uint
++sb_flag(si_t *sih)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	return R_SBREG(sii, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
++}
++
++void
++sb_setint(si_t *sih, int siflag)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++	uint32 vec;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	if (siflag == -1)
++		vec = 0;
++	else
++		vec = 1 << siflag;
++	W_SBREG(sii, &sb->sbintvec, vec);
++}
++
++/* return core index of the core with address 'sba' */
++static uint
++_sb_coreidx(si_info_t *sii, uint32 sba)
++{
++	uint i;
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	for (i = 0; i < sii->numcores; i ++)
++		if (sba == cores_info->coresba[i])
++			return i;
++	return BADIDX;
++}
++
++/* return core address of the current core */
++static uint32
++_sb_coresba(si_info_t *sii)
++{
++	uint32 sbaddr;
++
++
++	switch (BUSTYPE(sii->pub.bustype)) {
++	case SI_BUS: {
++		sbconfig_t *sb = REGS2SB(sii->curmap);
++		sbaddr = sb_base(R_SBREG(sii, &sb->sbadmatch0));
++		break;
++	}
++
++	case PCI_BUS:
++		sbaddr = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
++		break;
++
++	case PCMCIA_BUS: {
++		uint8 tmp = 0;
++		OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR0, &tmp, 1);
++		sbaddr  = (uint32)tmp << 12;
++		OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR1, &tmp, 1);
++		sbaddr |= (uint32)tmp << 16;
++		OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR2, &tmp, 1);
++		sbaddr |= (uint32)tmp << 24;
++		break;
++	}
++
++#ifdef BCMSDIO
++	case SPI_BUS:
++	case SDIO_BUS:
++		sbaddr = (uint32)(uintptr)sii->curmap;
++		break;
++#endif
++
++
++	default:
++		sbaddr = BADCOREADDR;
++		break;
++	}
++
++	return sbaddr;
++}
++
++uint
++sb_corevendor(si_t *sih)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	return ((R_SBREG(sii, &sb->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
++}
++
++uint
++sb_corerev(si_t *sih)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++	uint sbidh;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++	sbidh = R_SBREG(sii, &sb->sbidhigh);
++
++	return (SBCOREREV(sbidh));
++}
++
++/* set core-specific control flags */
++void
++sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++	uint32 w;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	ASSERT((val & ~mask) == 0);
++
++	/* mask and set */
++	w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) |
++	        (val << SBTML_SICF_SHIFT);
++	W_SBREG(sii, &sb->sbtmstatelow, w);
++}
++
++/* set/clear core-specific control flags */
++uint32
++sb_core_cflags(si_t *sih, uint32 mask, uint32 val)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++	uint32 w;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	ASSERT((val & ~mask) == 0);
++
++	/* mask and set */
++	if (mask || val) {
++		w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) |
++		        (val << SBTML_SICF_SHIFT);
++		W_SBREG(sii, &sb->sbtmstatelow, w);
++	}
++
++	/* return the new value
++	 * for write operation, the following readback ensures the completion of write opration.
++	 */
++	return (R_SBREG(sii, &sb->sbtmstatelow) >> SBTML_SICF_SHIFT);
++}
++
++/* set/clear core-specific status flags */
++uint32
++sb_core_sflags(si_t *sih, uint32 mask, uint32 val)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++	uint32 w;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	ASSERT((val & ~mask) == 0);
++	ASSERT((mask & ~SISF_CORE_BITS) == 0);
++
++	/* mask and set */
++	if (mask || val) {
++		w = (R_SBREG(sii, &sb->sbtmstatehigh) & ~(mask << SBTMH_SISF_SHIFT)) |
++		        (val << SBTMH_SISF_SHIFT);
++		W_SBREG(sii, &sb->sbtmstatehigh, w);
++	}
++
++	/* return the new value */
++	return (R_SBREG(sii, &sb->sbtmstatehigh) >> SBTMH_SISF_SHIFT);
++}
++
++bool
++sb_iscoreup(si_t *sih)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	return ((R_SBREG(sii, &sb->sbtmstatelow) &
++	         (SBTML_RESET | SBTML_REJ_MASK | (SICF_CLOCK_EN << SBTML_SICF_SHIFT))) ==
++	        (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
++}
++
++/*
++ * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
++ * switch back to the original core, and return the new value.
++ *
++ * When using the silicon backplane, no fidleing with interrupts or core switches are needed.
++ *
++ * Also, when using pci/pcie, we can optimize away the core switching for pci registers
++ * and (on newer pci cores) chipcommon registers.
++ */
++uint
++sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
++{
++	uint origidx = 0;
++	uint32 *r = NULL;
++	uint w;
++	uint intr_val = 0;
++	bool fast = FALSE;
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	ASSERT(GOODIDX(coreidx));
++	ASSERT(regoff < SI_CORE_SIZE);
++	ASSERT((val & ~mask) == 0);
++
++	if (coreidx >= SI_MAXCORES)
++		return 0;
++
++	if (BUSTYPE(sii->pub.bustype) == SI_BUS) {
++		/* If internal bus, we can always get at everything */
++		fast = TRUE;
++		/* map if does not exist */
++		if (!cores_info->regs[coreidx]) {
++			cores_info->regs[coreidx] = REG_MAP(cores_info->coresba[coreidx],
++			                            SI_CORE_SIZE);
++			ASSERT(GOODREGS(cores_info->regs[coreidx]));
++		}
++		r = (uint32 *)((uchar *)cores_info->regs[coreidx] + regoff);
++	} else if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
++		/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
++
++		if ((cores_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
++			/* Chipc registers are mapped at 12KB */
++
++			fast = TRUE;
++			r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
++		} else if (sii->pub.buscoreidx == coreidx) {
++			/* pci registers are at either in the last 2KB of an 8KB window
++			 * or, in pcie and pci rev 13 at 8KB
++			 */
++			fast = TRUE;
++			if (SI_FAST(sii))
++				r = (uint32 *)((char *)sii->curmap +
++				               PCI_16KB0_PCIREGS_OFFSET + regoff);
++			else
++				r = (uint32 *)((char *)sii->curmap +
++				               ((regoff >= SBCONFIGOFF) ?
++				                PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
++				               regoff);
++		}
++	}
++
++	if (!fast) {
++		INTR_OFF(sii, intr_val);
++
++		/* save current core index */
++		origidx = si_coreidx(&sii->pub);
++
++		/* switch core */
++		r = (uint32*) ((uchar*)sb_setcoreidx(&sii->pub, coreidx) + regoff);
++	}
++	ASSERT(r != NULL);
++
++	/* mask and set */
++	if (mask || val) {
++		if (regoff >= SBCONFIGOFF) {
++			w = (R_SBREG(sii, r) & ~mask) | val;
++			W_SBREG(sii, r, w);
++		} else {
++			w = (R_REG(sii->osh, r) & ~mask) | val;
++			W_REG(sii->osh, r, w);
++		}
++	}
++
++	/* readback */
++	if (regoff >= SBCONFIGOFF)
++		w = R_SBREG(sii, r);
++	else {
++		if ((CHIPID(sii->pub.chip) == BCM5354_CHIP_ID) &&
++		    (coreidx == SI_CC_IDX) &&
++		    (regoff == OFFSETOF(chipcregs_t, watchdog))) {
++			w = val;
++		} else
++			w = R_REG(sii->osh, r);
++	}
++
++	if (!fast) {
++		/* restore core index */
++		if (origidx != coreidx)
++			sb_setcoreidx(&sii->pub, origidx);
++
++		INTR_RESTORE(sii, intr_val);
++	}
++
++	return (w);
++}
++
++/*
++ * If there is no need for fiddling with interrupts or core switches (typically silicon
++ * back plane registers, pci registers and chipcommon registers), this function
++ * returns the register offset on this core to a mapped address. This address can
++ * be used for W_REG/R_REG directly.
++ *
++ * For accessing registers that would need a core switch, this function will return
++ * NULL.
++ */
++uint32 *
++sb_corereg_addr(si_t *sih, uint coreidx, uint regoff)
++{
++	uint32 *r = NULL;
++	bool fast = FALSE;
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	ASSERT(GOODIDX(coreidx));
++	ASSERT(regoff < SI_CORE_SIZE);
++
++	if (coreidx >= SI_MAXCORES)
++		return 0;
++
++	if (BUSTYPE(sii->pub.bustype) == SI_BUS) {
++		/* If internal bus, we can always get at everything */
++		fast = TRUE;
++		/* map if does not exist */
++		if (!cores_info->regs[coreidx]) {
++			cores_info->regs[coreidx] = REG_MAP(cores_info->coresba[coreidx],
++			                            SI_CORE_SIZE);
++			ASSERT(GOODREGS(cores_info->regs[coreidx]));
++		}
++		r = (uint32 *)((uchar *)cores_info->regs[coreidx] + regoff);
++	} else if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
++		/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
++
++		if ((cores_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
++			/* Chipc registers are mapped at 12KB */
++
++			fast = TRUE;
++			r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
++		} else if (sii->pub.buscoreidx == coreidx) {
++			/* pci registers are at either in the last 2KB of an 8KB window
++			 * or, in pcie and pci rev 13 at 8KB
++			 */
++			fast = TRUE;
++			if (SI_FAST(sii))
++				r = (uint32 *)((char *)sii->curmap +
++				               PCI_16KB0_PCIREGS_OFFSET + regoff);
++			else
++				r = (uint32 *)((char *)sii->curmap +
++				               ((regoff >= SBCONFIGOFF) ?
++				                PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
++				               regoff);
++		}
++	}
++
++	if (!fast)
++		return 0;
++
++	return (r);
++}
++
++/* Scan the enumeration space to find all cores starting from the given
++ * bus 'sbba'. Append coreid and other info to the lists in 'si'. 'sba'
++ * is the default core address at chip POR time and 'regs' is the virtual
++ * address that the default core is mapped at. 'ncores' is the number of
++ * cores expected on bus 'sbba'. It returns the total number of cores
++ * starting from bus 'sbba', inclusive.
++ */
++#define SB_MAXBUSES	2
++static uint
++_sb_scan(si_info_t *sii, uint32 sba, void *regs, uint bus, uint32 sbba, uint numcores)
++{
++	uint next;
++	uint ncc = 0;
++	uint i;
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	if (bus >= SB_MAXBUSES) {
++		SI_ERROR(("_sb_scan: bus 0x%08x at level %d is too deep to scan\n", sbba, bus));
++		return 0;
++	}
++	SI_MSG(("_sb_scan: scan bus 0x%08x assume %u cores\n", sbba, numcores));
++
++	/* Scan all cores on the bus starting from core 0.
++	 * Core addresses must be contiguous on each bus.
++	 */
++	for (i = 0, next = sii->numcores; i < numcores && next < SB_BUS_MAXCORES; i++, next++) {
++		cores_info->coresba[next] = sbba + (i * SI_CORE_SIZE);
++
++		/* keep and reuse the initial register mapping */
++		if ((BUSTYPE(sii->pub.bustype) == SI_BUS) && (cores_info->coresba[next] == sba)) {
++			SI_VMSG(("_sb_scan: reuse mapped regs %p for core %u\n", regs, next));
++			cores_info->regs[next] = regs;
++		}
++
++		/* change core to 'next' and read its coreid */
++		sii->curmap = _sb_setcoreidx(sii, next);
++		sii->curidx = next;
++
++		cores_info->coreid[next] = sb_coreid(&sii->pub);
++
++		/* core specific processing... */
++		/* chipc provides # cores */
++		if (cores_info->coreid[next] == CC_CORE_ID) {
++			chipcregs_t *cc = (chipcregs_t *)sii->curmap;
++			uint32 ccrev = sb_corerev(&sii->pub);
++
++			/* determine numcores - this is the total # cores in the chip */
++			if (((ccrev == 4) || (ccrev >= 6))) {
++				ASSERT(cc);
++				numcores = (R_REG(sii->osh, &cc->chipid) & CID_CC_MASK) >>
++				        CID_CC_SHIFT;
++			} else {
++				/* Older chips */
++				uint chip = CHIPID(sii->pub.chip);
++
++				if (chip == BCM4306_CHIP_ID)	/* < 4306c0 */
++					numcores = 6;
++				else if (chip == BCM4704_CHIP_ID)
++					numcores = 9;
++				else if (chip == BCM5365_CHIP_ID)
++					numcores = 7;
++				else {
++					SI_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n",
++					          chip));
++					ASSERT(0);
++					numcores = 1;
++				}
++			}
++			SI_VMSG(("_sb_scan: there are %u cores in the chip %s\n", numcores,
++				sii->pub.issim ? "QT" : ""));
++		}
++		/* scan bridged SB(s) and add results to the end of the list */
++		else if (cores_info->coreid[next] == OCP_CORE_ID) {
++			sbconfig_t *sb = REGS2SB(sii->curmap);
++			uint32 nsbba = R_SBREG(sii, &sb->sbadmatch1);
++			uint nsbcc;
++
++			sii->numcores = next + 1;
++
++			if ((nsbba & 0xfff00000) != SI_ENUM_BASE)
++				continue;
++			nsbba &= 0xfffff000;
++			if (_sb_coreidx(sii, nsbba) != BADIDX)
++				continue;
++
++			nsbcc = (R_SBREG(sii, &sb->sbtmstatehigh) & 0x000f0000) >> 16;
++			nsbcc = _sb_scan(sii, sba, regs, bus + 1, nsbba, nsbcc);
++			if (sbba == SI_ENUM_BASE)
++				numcores -= nsbcc;
++			ncc += nsbcc;
++		}
++	}
++
++	SI_MSG(("_sb_scan: found %u cores on bus 0x%08x\n", i, sbba));
++
++	sii->numcores = i + ncc;
++	return sii->numcores;
++}
++
++/* scan the sb enumerated space to identify all cores */
++void
++sb_scan(si_t *sih, void *regs, uint devid)
++{
++	uint32 origsba;
++	sbconfig_t *sb;
++	si_info_t *sii = SI_INFO(sih);
++
++	sb = REGS2SB(sii->curmap);
++
++	sii->pub.socirev = (R_SBREG(sii, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
++
++	/* Save the current core info and validate it later till we know
++	 * for sure what is good and what is bad.
++	 */
++	origsba = _sb_coresba(sii);
++
++	/* scan all SB(s) starting from SI_ENUM_BASE */
++	sii->numcores = _sb_scan(sii, origsba, regs, 0, SI_ENUM_BASE, 1);
++}
++
++/*
++ * This function changes logical "focus" to the indicated core;
++ * must be called with interrupts off.
++ * Moreover, callers should keep interrupts off during switching out of and back to d11 core
++ */
++void *
++sb_setcoreidx(si_t *sih, uint coreidx)
++{
++	si_info_t *sii = SI_INFO(sih);
++
++	if (coreidx >= sii->numcores)
++		return (NULL);
++
++	/*
++	 * If the user has provided an interrupt mask enabled function,
++	 * then assert interrupts are disabled before switching the core.
++	 */
++	ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg));
++
++	sii->curmap = _sb_setcoreidx(sii, coreidx);
++	sii->curidx = coreidx;
++
++	return (sii->curmap);
++}
++
++/* This function changes the logical "focus" to the indicated core.
++ * Return the current core's virtual address.
++ */
++static void *
++_sb_setcoreidx(si_info_t *sii, uint coreidx)
++{
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint32 sbaddr = cores_info->coresba[coreidx];
++	void *regs;
++
++	switch (BUSTYPE(sii->pub.bustype)) {
++	case SI_BUS:
++		/* map new one */
++		if (!cores_info->regs[coreidx]) {
++			cores_info->regs[coreidx] = REG_MAP(sbaddr, SI_CORE_SIZE);
++			ASSERT(GOODREGS(cores_info->regs[coreidx]));
++		}
++		regs = cores_info->regs[coreidx];
++		break;
++
++	case PCI_BUS:
++		/* point bar0 window */
++		OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, sbaddr);
++		regs = sii->curmap;
++		break;
++
++	case PCMCIA_BUS: {
++		uint8 tmp = (sbaddr >> 12) & 0x0f;
++		OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR0, &tmp, 1);
++		tmp = (sbaddr >> 16) & 0xff;
++		OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR1, &tmp, 1);
++		tmp = (sbaddr >> 24) & 0xff;
++		OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR2, &tmp, 1);
++		regs = sii->curmap;
++		break;
++	}
++#ifdef BCMSDIO
++	case SPI_BUS:
++	case SDIO_BUS:
++		/* map new one */
++		if (!cores_info->regs[coreidx]) {
++			cores_info->regs[coreidx] = (void *)(uintptr)sbaddr;
++			ASSERT(GOODREGS(cores_info->regs[coreidx]));
++		}
++		regs = cores_info->regs[coreidx];
++		break;
++#endif	/* BCMSDIO */
++
++
++	default:
++		ASSERT(0);
++		regs = NULL;
++		break;
++	}
++
++	return regs;
++}
++
++/* Return the address of sbadmatch0/1/2/3 register */
++static volatile uint32 *
++sb_admatch(si_info_t *sii, uint asidx)
++{
++	sbconfig_t *sb;
++	volatile uint32 *addrm;
++
++	sb = REGS2SB(sii->curmap);
++
++	switch (asidx) {
++	case 0:
++		addrm =  &sb->sbadmatch0;
++		break;
++
++	case 1:
++		addrm =  &sb->sbadmatch1;
++		break;
++
++	case 2:
++		addrm =  &sb->sbadmatch2;
++		break;
++
++	case 3:
++		addrm =  &sb->sbadmatch3;
++		break;
++
++	default:
++		SI_ERROR(("%s: Address space index (%d) out of range\n", __FUNCTION__, asidx));
++		return 0;
++	}
++
++	return (addrm);
++}
++
++/* Return the number of address spaces in current core */
++int
++sb_numaddrspaces(si_t *sih)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++
++	sii = SI_INFO(sih);
++	sb = REGS2SB(sii->curmap);
++
++	/* + 1 because of enumeration space */
++	return ((R_SBREG(sii, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT) + 1;
++}
++
++/* Return the address of the nth address space in the current core */
++uint32
++sb_addrspace(si_t *sih, uint asidx)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++
++	return (sb_base(R_SBREG(sii, sb_admatch(sii, asidx))));
++}
++
++/* Return the size of the nth address space in the current core */
++uint32
++sb_addrspacesize(si_t *sih, uint asidx)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++
++	return (sb_size(R_SBREG(sii, sb_admatch(sii, asidx))));
++}
++
++
++/* do buffered registers update */
++void
++sb_commit(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint origidx;
++	uint intr_val = 0;
++
++	origidx = sii->curidx;
++	ASSERT(GOODIDX(origidx));
++
++	INTR_OFF(sii, intr_val);
++
++	/* switch over to chipcommon core if there is one, else use pci */
++	if (sii->pub.ccrev != NOREV) {
++		chipcregs_t *ccregs = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
++		ASSERT(ccregs != NULL);
++
++		/* do the buffer registers update */
++		W_REG(sii->osh, &ccregs->broadcastaddress, SB_COMMIT);
++		W_REG(sii->osh, &ccregs->broadcastdata, 0x0);
++	} else
++		ASSERT(0);
++
++	/* restore core index */
++	sb_setcoreidx(sih, origidx);
++	INTR_RESTORE(sii, intr_val);
++}
++
++void
++sb_core_disable(si_t *sih, uint32 bits)
++{
++	si_info_t *sii;
++	volatile uint32 dummy;
++	sbconfig_t *sb;
++
++	sii = SI_INFO(sih);
++
++	ASSERT(GOODREGS(sii->curmap));
++	sb = REGS2SB(sii->curmap);
++
++	/* if core is already in reset, just return */
++	if (R_SBREG(sii, &sb->sbtmstatelow) & SBTML_RESET)
++		return;
++
++	/* if clocks are not enabled, put into reset and return */
++	if ((R_SBREG(sii, &sb->sbtmstatelow) & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) == 0)
++		goto disable;
++
++	/* set target reject and spin until busy is clear (preserve core-specific bits) */
++	OR_SBREG(sii, &sb->sbtmstatelow, SBTML_REJ);
++	dummy = R_SBREG(sii, &sb->sbtmstatelow);
++	BCM_REFERENCE(dummy);
++	OSL_DELAY(1);
++	SPINWAIT((R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
++	if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY)
++		SI_ERROR(("%s: target state still busy\n", __FUNCTION__));
++
++	if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT) {
++		OR_SBREG(sii, &sb->sbimstate, SBIM_RJ);
++		dummy = R_SBREG(sii, &sb->sbimstate);
++		BCM_REFERENCE(dummy);
++		OSL_DELAY(1);
++		SPINWAIT((R_SBREG(sii, &sb->sbimstate) & SBIM_BY), 100000);
++	}
++
++	/* set reset and reject while enabling the clocks */
++	W_SBREG(sii, &sb->sbtmstatelow,
++	        (((bits | SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
++	         SBTML_REJ | SBTML_RESET));
++	dummy = R_SBREG(sii, &sb->sbtmstatelow);
++	BCM_REFERENCE(dummy);
++	OSL_DELAY(10);
++
++	/* don't forget to clear the initiator reject bit */
++	if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT)
++		AND_SBREG(sii, &sb->sbimstate, ~SBIM_RJ);
++
++disable:
++	/* leave reset and reject asserted */
++	W_SBREG(sii, &sb->sbtmstatelow, ((bits << SBTML_SICF_SHIFT) | SBTML_REJ | SBTML_RESET));
++	OSL_DELAY(1);
++}
++
++/* reset and re-enable a core
++ * inputs:
++ * bits - core specific bits that are set during and after reset sequence
++ * resetbits - core specific bits that are set only during reset sequence
++ */
++void
++sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
++{
++	si_info_t *sii;
++	sbconfig_t *sb;
++	volatile uint32 dummy;
++
++	sii = SI_INFO(sih);
++	ASSERT(GOODREGS(sii->curmap));
++	sb = REGS2SB(sii->curmap);
++
++	/*
++	 * Must do the disable sequence first to work for arbitrary current core state.
++	 */
++	sb_core_disable(sih, (bits | resetbits));
++
++	/*
++	 * Now do the initialization sequence.
++	 */
++
++	/* set reset while enabling the clock and forcing them on throughout the core */
++	W_SBREG(sii, &sb->sbtmstatelow,
++	        (((bits | resetbits | SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
++	         SBTML_RESET));
++	dummy = R_SBREG(sii, &sb->sbtmstatelow);
++	BCM_REFERENCE(dummy);
++	OSL_DELAY(1);
++
++	if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_SERR) {
++		W_SBREG(sii, &sb->sbtmstatehigh, 0);
++	}
++	if ((dummy = R_SBREG(sii, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
++		AND_SBREG(sii, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
++	}
++
++	/* clear reset and allow it to propagate throughout the core */
++	W_SBREG(sii, &sb->sbtmstatelow,
++	        ((bits | resetbits | SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT));
++	dummy = R_SBREG(sii, &sb->sbtmstatelow);
++	BCM_REFERENCE(dummy);
++	OSL_DELAY(1);
++
++	/* leave clock enabled */
++	W_SBREG(sii, &sb->sbtmstatelow, ((bits | SICF_CLOCK_EN) << SBTML_SICF_SHIFT));
++	dummy = R_SBREG(sii, &sb->sbtmstatelow);
++	BCM_REFERENCE(dummy);
++	OSL_DELAY(1);
++}
++
++/*
++ * Set the initiator timeout for the "master core".
++ * The master core is defined to be the core in control
++ * of the chip and so it issues accesses to non-memory
++ * locations (Because of dma *any* core can access memeory).
++ *
++ * The routine uses the bus to decide who is the master:
++ *	SI_BUS => mips
++ *	JTAG_BUS => chipc
++ *	PCI_BUS => pci or pcie
++ *	PCMCIA_BUS => pcmcia
++ *	SDIO_BUS => pcmcia
++ *
++ * This routine exists so callers can disable initiator
++ * timeouts so accesses to very slow devices like otp
++ * won't cause an abort. The routine allows arbitrary
++ * settings of the service and request timeouts, though.
++ *
++ * Returns the timeout state before changing it or -1
++ * on error.
++ */
++
++#define	TO_MASK	(SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
++
++uint32
++sb_set_initiator_to(si_t *sih, uint32 to, uint idx)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint origidx;
++	uint intr_val = 0;
++	uint32 tmp, ret = 0xffffffff;
++	sbconfig_t *sb;
++
++
++	if ((to & ~TO_MASK) != 0)
++		return ret;
++
++	/* Figure out the master core */
++	if (idx == BADIDX) {
++		switch (BUSTYPE(sii->pub.bustype)) {
++		case PCI_BUS:
++			idx = sii->pub.buscoreidx;
++			break;
++		case JTAG_BUS:
++			idx = SI_CC_IDX;
++			break;
++		case PCMCIA_BUS:
++#ifdef BCMSDIO
++		case SDIO_BUS:
++#endif
++			idx = si_findcoreidx(sih, PCMCIA_CORE_ID, 0);
++			break;
++		case SI_BUS:
++			idx = si_findcoreidx(sih, MIPS33_CORE_ID, 0);
++			break;
++		default:
++			ASSERT(0);
++		}
++		if (idx == BADIDX)
++			return ret;
++	}
++
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	sb = REGS2SB(sb_setcoreidx(sih, idx));
++
++	tmp = R_SBREG(sii, &sb->sbimconfiglow);
++	ret = tmp & TO_MASK;
++	W_SBREG(sii, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
++
++	sb_commit(sih);
++	sb_setcoreidx(sih, origidx);
++	INTR_RESTORE(sii, intr_val);
++	return ret;
++}
++
++uint32
++sb_base(uint32 admatch)
++{
++	uint32 base;
++	uint type;
++
++	type = admatch & SBAM_TYPE_MASK;
++	ASSERT(type < 3);
++
++	base = 0;
++
++	if (type == 0) {
++		base = admatch & SBAM_BASE0_MASK;
++	} else if (type == 1) {
++		ASSERT(!(admatch & SBAM_ADNEG));	/* neg not supported */
++		base = admatch & SBAM_BASE1_MASK;
++	} else if (type == 2) {
++		ASSERT(!(admatch & SBAM_ADNEG));	/* neg not supported */
++		base = admatch & SBAM_BASE2_MASK;
++	}
++
++	return (base);
++}
++
++uint32
++sb_size(uint32 admatch)
++{
++	uint32 size;
++	uint type;
++
++	type = admatch & SBAM_TYPE_MASK;
++	ASSERT(type < 3);
++
++	size = 0;
++
++	if (type == 0) {
++		size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
++	} else if (type == 1) {
++		ASSERT(!(admatch & SBAM_ADNEG));	/* neg not supported */
++		size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
++	} else if (type == 2) {
++		ASSERT(!(admatch & SBAM_ADNEG));	/* neg not supported */
++		size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
++	}
++
++	return (size);
++}
++
++#if defined(BCMDBG_PHYDUMP)
++/* print interesting sbconfig registers */
++void
++sb_dumpregs(si_t *sih, struct bcmstrbuf *b)
++{
++	sbconfig_t *sb;
++	uint origidx, i, intr_val = 0;
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	origidx = sii->curidx;
++
++	INTR_OFF(sii, intr_val);
++
++	for (i = 0; i < sii->numcores; i++) {
++		sb = REGS2SB(sb_setcoreidx(sih, i));
++
++		bcm_bprintf(b, "core 0x%x: \n", cores_info->coreid[i]);
++
++		if (sii->pub.socirev > SONICS_2_2)
++			bcm_bprintf(b, "sbimerrlog 0x%x sbimerrloga 0x%x\n",
++			          sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOG, 0, 0),
++			          sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOGA, 0, 0));
++
++		bcm_bprintf(b, "sbtmstatelow 0x%x sbtmstatehigh 0x%x sbidhigh 0x%x "
++		            "sbimstate 0x%x\n sbimconfiglow 0x%x sbimconfighigh 0x%x\n",
++		            R_SBREG(sii, &sb->sbtmstatelow), R_SBREG(sii, &sb->sbtmstatehigh),
++		            R_SBREG(sii, &sb->sbidhigh), R_SBREG(sii, &sb->sbimstate),
++		            R_SBREG(sii, &sb->sbimconfiglow), R_SBREG(sii, &sb->sbimconfighigh));
++	}
++
++	sb_setcoreidx(sih, origidx);
++	INTR_RESTORE(sii, intr_val);
++}
++#endif	
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/siutils.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/siutils.c
+new file mode 100644
+index 000000000..857eee92b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/siutils.c
+@@ -0,0 +1,3310 @@
++/*
++ * Misc utility routines for accessing chip-specific features
++ * of the SiliconBackplane-based Broadcom chips.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: siutils.c 708487 2018-10-31 05:33:14Z $
++ */
++
++#include <bcm_cfg.h>
++#include <typedefs.h>
++#include <bcmdefs.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <siutils.h>
++#include <bcmdevs.h>
++#include <hndsoc.h>
++#include <sbchipc.h>
++#ifdef BCMPCIEDEV
++#include <pciedev.h>
++#endif /* BCMPCIEDEV */
++#include <pcicfg.h>
++#include <sbpcmcia.h>
++#include <sbsysmem.h>
++#include <sbsocram.h>
++#ifdef BCMSDIO
++#include <bcmsdh.h>
++#include <sdio.h>
++#include <sbsdio.h>
++#include <sbhnddma.h>
++#include <sbsdpcmdev.h>
++#include <bcmsdpcm.h>
++#endif /* BCMSDIO */
++#include <hndpmu.h>
++
++#ifdef LOAD_DHD_WITH_FW_ALIVE
++#include <dhd_chip_info.h>
++#endif
++
++#ifdef BCM_SDRBL
++#include <hndcpu.h>
++#endif /* BCM_SDRBL */
++#ifdef HNDGCI
++#include <hndgci.h>
++#endif /* HNDGCI */
++
++#include "siutils_priv.h"
++
++/**
++ * A set of PMU registers is clocked in the ILP domain, which has an implication on register write
++ * behavior: if such a register is written, it takes multiple ILP clocks for the PMU block to absorb
++ * the write. During that time the 'SlowWritePending' bit in the PMUStatus register is set.
++ */
++#define PMUREGS_ILP_SENSITIVE(regoff) \
++	((regoff) == OFFSETOF(pmuregs_t, pmutimer) || \
++	 (regoff) == OFFSETOF(pmuregs_t, pmuwatchdog) || \
++	 (regoff) == OFFSETOF(pmuregs_t, res_req_timer))
++
++#define CHIPCREGS_ILP_SENSITIVE(regoff) \
++	((regoff) == OFFSETOF(chipcregs_t, pmutimer) || \
++	 (regoff) == OFFSETOF(chipcregs_t, pmuwatchdog) || \
++	 (regoff) == OFFSETOF(chipcregs_t, res_req_timer))
++
++/* local prototypes */
++static si_info_t *si_doattach(si_info_t *sii, uint devid, osl_t *osh, void *regs,
++                              uint bustype, void *sdh, char **vars, uint *varsz);
++static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid, void *sdh);
++static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin,
++	uint *origidx, void *regs);
++
++
++static bool si_pmu_is_ilp_sensitive(uint32 idx, uint regoff);
++
++#ifdef BCMLTECOEX
++static void si_config_gcigpio(si_t *sih, uint32 gci_pos, uint8 gcigpio,
++	uint8 gpioctl_mask, uint8 gpioctl_val);
++#endif /* BCMLTECOEX */
++
++
++/* global variable to indicate reservation/release of gpio's */
++static uint32 si_gpioreservation = 0;
++
++/* global flag to prevent shared resources from being initialized multiple times in si_attach() */
++#ifdef SR_DEBUG
++static const uint32 si_power_island_test_array[] = {
++	0x0000, 0x0001, 0x0010, 0x0011,
++	0x0100, 0x0101, 0x0110, 0x0111,
++	0x1000, 0x1001, 0x1010, 0x1011,
++	0x1100, 0x1101, 0x1110, 0x1111
++};
++#endif /* SR_DEBUG */
++
++int do_4360_pcie2_war = 0;
++
++/* global kernel resource */
++static si_info_t ksii;
++static si_cores_info_t ksii_cores_info;
++
++/**
++ * Allocate an si handle. This function may be called multiple times.
++ *
++ * devid - pci device id (used to determine chip#)
++ * osh - opaque OS handle
++ * regs - virtual address of initial core registers
++ * bustype - pci/pcmcia/sb/sdio/etc
++ * vars - pointer to a to-be created pointer area for "environment" variables. Some callers of this
++ *        function set 'vars' to NULL, making dereferencing of this parameter undesired.
++ * varsz - pointer to int to return the size of the vars
++ */
++si_t *
++si_attach(uint devid, osl_t *osh, void *regs,
++                       uint bustype, void *sdh, char **vars, uint *varsz)
++{
++	si_info_t *sii;
++	si_cores_info_t *cores_info;
++	/* alloc si_info_t */
++	if ((sii = MALLOCZ(osh, sizeof (si_info_t))) == NULL) {
++		SI_ERROR(("si_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
++		return (NULL);
++	}
++
++	/* alloc si_cores_info_t */
++	if ((cores_info = (si_cores_info_t *)MALLOCZ(osh, sizeof (si_cores_info_t))) == NULL) {
++		SI_ERROR(("si_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
++		MFREE(osh, sii, sizeof(si_info_t));
++		return (NULL);
++	}
++	sii->cores_info = cores_info;
++
++	if (si_doattach(sii, devid, osh, regs, bustype, sdh, vars, varsz) == NULL) {
++		MFREE(osh, sii, sizeof(si_info_t));
++		MFREE(osh, cores_info, sizeof(si_cores_info_t));
++		return (NULL);
++	}
++	sii->vars = vars ? *vars : NULL;
++	sii->varsz = varsz ? *varsz : 0;
++
++	return (si_t *)sii;
++}
++
++
++static uint32	wd_msticks;		/* watchdog timer ticks normalized to ms */
++
++/** generic kernel variant of si_attach() */
++si_t *
++si_kattach(osl_t *osh)
++{
++	static bool ksii_attached = FALSE;
++	si_cores_info_t *cores_info;
++
++	if (!ksii_attached) {
++		void *regs = NULL;
++		regs = REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
++		cores_info = (si_cores_info_t *)&ksii_cores_info;
++		ksii.cores_info = cores_info;
++
++		ASSERT(osh);
++		if (si_doattach(&ksii, BCM4710_DEVICE_ID, osh, regs,
++		                SI_BUS, NULL,
++		                osh != SI_OSH ? &(ksii.vars) : NULL,
++		                osh != SI_OSH ? &(ksii.varsz) : NULL) == NULL) {
++			SI_ERROR(("si_kattach: si_doattach failed\n"));
++			REG_UNMAP(regs);
++			return NULL;
++		}
++		REG_UNMAP(regs);
++
++		/* save ticks normalized to ms for si_watchdog_ms() */
++		if (PMUCTL_ENAB(&ksii.pub)) {
++				/* based on 32KHz ILP clock */
++				wd_msticks = 32;
++		} else {
++			wd_msticks = ALP_CLOCK / 1000;
++		}
++
++		ksii_attached = TRUE;
++		SI_MSG(("si_kattach done. ccrev = %d, wd_msticks = %d\n",
++		        ksii.pub.ccrev, wd_msticks));
++	}
++
++	return &ksii.pub;
++}
++
++
++static bool
++si_buscore_prep(si_info_t *sii, uint bustype, uint devid, void *sdh)
++{
++	/* need to set memseg flag for CF card first before any sb registers access */
++	if (BUSTYPE(bustype) == PCMCIA_BUS)
++		sii->memseg = TRUE;
++
++
++#if defined(BCMSDIO)
++	if (BUSTYPE(bustype) == SDIO_BUS) {
++		int err;
++		uint8 clkset;
++
++		/* Try forcing SDIO core to do ALPAvail request only */
++		clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
++		bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
++		if (!err) {
++			uint8 clkval;
++
++			/* If register supported, wait for ALPAvail and then force ALP */
++			clkval = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, NULL);
++			if ((clkval & ~SBSDIO_AVBITS) == clkset) {
++				SPINWAIT(((clkval = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
++					SBSDIO_FUNC1_CHIPCLKCSR, NULL)), !SBSDIO_ALPAV(clkval)),
++					PMU_MAX_TRANSITION_DLY);
++				if (!SBSDIO_ALPAV(clkval)) {
++					SI_ERROR(("timeout on ALPAV wait, clkval 0x%02x\n",
++						clkval));
++					return FALSE;
++				}
++				clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
++				bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
++					clkset, &err);
++				OSL_DELAY(65);
++			}
++		}
++
++		/* Also, disable the extra SDIO pull-ups */
++		bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
++	}
++
++#endif /* BCMSDIO && BCMDONGLEHOST */
++
++	return TRUE;
++}
++
++uint32
++si_get_pmu_reg_addr(si_t *sih, uint32 offset)
++{
++	si_info_t *sii = SI_INFO(sih);
++	uint32 pmuaddr = INVALID_ADDR;
++	uint origidx = 0;
++
++	SI_MSG(("%s: pmu access, offset: %x\n", __FUNCTION__, offset));
++	if (!(sii->pub.cccaps & CC_CAP_PMU)) {
++		goto done;
++	}
++	if (AOB_ENAB(&sii->pub)) {
++		uint pmucoreidx;
++		pmuregs_t *pmu;
++		SI_MSG(("%s: AOBENAB: %x\n", __FUNCTION__, offset));
++		origidx = sii->curidx;
++		pmucoreidx = si_findcoreidx(&sii->pub, PMU_CORE_ID, 0);
++		pmu = si_setcoreidx(&sii->pub, pmucoreidx);
++		pmuaddr = (uint32)(unsigned long)((uint8*)pmu + offset);
++		si_setcoreidx(sih, origidx);
++	} else
++		pmuaddr = SI_ENUM_BASE + offset;
++
++done:
++	SI_MSG(("%s: addrRET: %x\n", __FUNCTION__, pmuaddr));
++	return pmuaddr;
++}
++
++static bool
++si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin,
++	uint *origidx, void *regs)
++{
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	bool pci, pcie, pcie_gen2 = FALSE;
++	uint i;
++	uint pciidx, pcieidx, pcirev, pcierev;
++
++#ifdef LOAD_DHD_WITH_FW_ALIVE
++	if(alive == FW_ALIVE_MAGIC) {
++		switch(card_dev) {
++			case BCM43430_CHIP_ID:
++				if(card_rev == 2)
++					memcpy(&sii->pub, &sii_pub_43436, sizeof(sii->pub));
++				else
++					memcpy(&sii->pub, &sii_pub_43430, sizeof(sii->pub));
++				break;
++		}
++		return true;
++	}
++#endif
++
++	/* first, enable backplane timeouts */
++	if (CHIPTYPE(sii->pub.socitype) == SOCI_AI)
++		ai_enable_backplane_timeouts(&sii->pub);
++
++	cc = si_setcoreidx(&sii->pub, SI_CC_IDX);
++	ASSERT((uintptr)cc);
++
++	/* get chipcommon rev */
++	sii->pub.ccrev = (int)si_corerev(&sii->pub);
++
++	/* get chipcommon chipstatus */
++	if (sii->pub.ccrev >= 11)
++		sii->pub.chipst = R_REG(sii->osh, &cc->chipstatus);
++
++	/* get chipcommon capabilites */
++	sii->pub.cccaps = R_REG(sii->osh, &cc->capabilities);
++	/* get chipcommon extended capabilities */
++
++	if (sii->pub.ccrev >= 35)
++		sii->pub.cccaps_ext = R_REG(sii->osh, &cc->capabilities_ext);
++
++	/* get pmu rev and caps */
++	if (sii->pub.cccaps & CC_CAP_PMU) {
++		if (AOB_ENAB(&sii->pub)) {
++			uint pmucoreidx;
++			pmuregs_t *pmu;
++			pmucoreidx = si_findcoreidx(&sii->pub, PMU_CORE_ID, 0);
++			pmu = si_setcoreidx(&sii->pub, pmucoreidx);
++			sii->pub.pmucaps = R_REG(sii->osh, &pmu->pmucapabilities);
++			si_setcoreidx(&sii->pub, SI_CC_IDX);
++		} else
++			sii->pub.pmucaps = R_REG(sii->osh, &cc->pmucapabilities);
++
++		sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
++	}
++
++	SI_MSG(("Chipc: rev %d, caps 0x%x, chipst 0x%x pmurev %d, pmucaps 0x%x\n",
++		sii->pub.ccrev, sii->pub.cccaps, sii->pub.chipst, sii->pub.pmurev,
++		sii->pub.pmucaps));
++
++	/* figure out bus/orignal core idx */
++	sii->pub.buscoretype = NODEV_CORE_ID;
++	sii->pub.buscorerev = (uint)NOREV;
++	sii->pub.buscoreidx = BADIDX;
++
++	pci = pcie = FALSE;
++	pcirev = pcierev = (uint)NOREV;
++	pciidx = pcieidx = BADIDX;
++
++	for (i = 0; i < sii->numcores; i++) {
++		uint cid, crev;
++
++		si_setcoreidx(&sii->pub, i);
++		cid = si_coreid(&sii->pub);
++		crev = si_corerev(&sii->pub);
++
++		/* Display cores found */
++		SI_VMSG(("CORE[%d]: id 0x%x rev %d base 0x%x regs 0x%p\n",
++		        i, cid, crev, cores_info->coresba[i], cores_info->regs[i]));
++
++		if (BUSTYPE(bustype) == SI_BUS) {
++			/* now look at the chipstatus register to figure the pacakge */
++			/* for SDIO but downloaded on PCIE dev */
++			if (cid == PCIE2_CORE_ID) {
++				if (BCM43602_CHIP(sii->pub.chip) ||
++					(CHIPID(sii->pub.chip) == BCM4365_CHIP_ID) ||
++					(CHIPID(sii->pub.chip) == BCM4366_CHIP_ID) ||
++					((CHIPID(sii->pub.chip) == BCM4345_CHIP_ID ||
++					CHIPID(sii->pub.chip) == BCM43454_CHIP_ID) &&
++					CST4345_CHIPMODE_PCIE(sii->pub.chipst))) {
++					pcieidx = i;
++					pcierev = crev;
++					pcie = TRUE;
++					pcie_gen2 = TRUE;
++				}
++			}
++
++		}
++		else if (BUSTYPE(bustype) == PCI_BUS) {
++			if (cid == PCI_CORE_ID) {
++				pciidx = i;
++				pcirev = crev;
++				pci = TRUE;
++			} else if ((cid == PCIE_CORE_ID) || (cid == PCIE2_CORE_ID)) {
++				pcieidx = i;
++				pcierev = crev;
++				pcie = TRUE;
++				if (cid == PCIE2_CORE_ID)
++					pcie_gen2 = TRUE;
++			}
++		} else if ((BUSTYPE(bustype) == PCMCIA_BUS) &&
++		           (cid == PCMCIA_CORE_ID)) {
++			sii->pub.buscorerev = crev;
++			sii->pub.buscoretype = cid;
++			sii->pub.buscoreidx = i;
++		}
++#ifdef BCMSDIO
++		else if (((BUSTYPE(bustype) == SDIO_BUS) ||
++		          (BUSTYPE(bustype) == SPI_BUS)) &&
++		         ((cid == PCMCIA_CORE_ID) ||
++		          (cid == SDIOD_CORE_ID))) {
++			sii->pub.buscorerev = crev;
++			sii->pub.buscoretype = cid;
++			sii->pub.buscoreidx = i;
++		}
++#endif /* BCMSDIO */
++
++		/* find the core idx before entering this func. */
++		if ((savewin && (savewin == cores_info->coresba[i])) ||
++		    (regs == cores_info->regs[i]))
++			*origidx = i;
++	}
++
++
++#if defined(PCIE_FULL_DONGLE)
++	if (pcie) {
++		if (pcie_gen2)
++			sii->pub.buscoretype = PCIE2_CORE_ID;
++		else
++			sii->pub.buscoretype = PCIE_CORE_ID;
++		sii->pub.buscorerev = pcierev;
++		sii->pub.buscoreidx = pcieidx;
++	}
++	BCM_REFERENCE(pci);
++	BCM_REFERENCE(pcirev);
++	BCM_REFERENCE(pciidx);
++#else
++	if (pci) {
++		sii->pub.buscoretype = PCI_CORE_ID;
++		sii->pub.buscorerev = pcirev;
++		sii->pub.buscoreidx = pciidx;
++	} else if (pcie) {
++		if (pcie_gen2)
++			sii->pub.buscoretype = PCIE2_CORE_ID;
++		else
++			sii->pub.buscoretype = PCIE_CORE_ID;
++		sii->pub.buscorerev = pcierev;
++		sii->pub.buscoreidx = pcieidx;
++	}
++#endif /* defined(PCIE_FULL_DONGLE) */
++
++	SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx, sii->pub.buscoretype,
++	         sii->pub.buscorerev));
++
++	if (BUSTYPE(sii->pub.bustype) == SI_BUS && (CHIPID(sii->pub.chip) == BCM4712_CHIP_ID) &&
++	    (sii->pub.chippkg != BCM4712LARGE_PKG_ID) && (CHIPREV(sii->pub.chiprev) <= 3))
++		OR_REG(sii->osh, &cc->slow_clk_ctl, SCC_SS_XTAL);
++
++
++#if defined(BCMSDIO)
++	/* Make sure any on-chip ARM is off (in case strapping is wrong), or downloaded code was
++	 * already running.
++	 */
++	if ((BUSTYPE(bustype) == SDIO_BUS) || (BUSTYPE(bustype) == SPI_BUS)) {
++		if (si_setcore(&sii->pub, ARM7S_CORE_ID, 0) ||
++		    si_setcore(&sii->pub, ARMCM3_CORE_ID, 0))
++			si_core_disable(&sii->pub, 0);
++	}
++#endif /* BCMSDIO && BCMDONGLEHOST */
++
++	/* return to the original core */
++	si_setcoreidx(&sii->pub, *origidx);
++
++	return TRUE;
++}
++
++
++
++
++uint16
++si_chipid(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++
++	return (sii->chipnew) ? sii->chipnew : sih->chip;
++}
++
++static void
++si_chipid_fixup(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++
++	ASSERT(sii->chipnew == 0);
++	switch (sih->chip) {
++		case BCM43567_CHIP_ID:
++			sii->chipnew = sih->chip; /* save it */
++			sii->pub.chip = BCM43570_CHIP_ID; /* chip class */
++		break;
++		case BCM4358_CHIP_ID:
++		case BCM43566_CHIP_ID:
++			sii->chipnew = sih->chip; /* save it */
++			sii->pub.chip = BCM43569_CHIP_ID; /* chip class */
++		break;
++		case BCM4356_CHIP_ID:
++			sii->chipnew = sih->chip; /* save it */
++			sii->pub.chip = BCM4354_CHIP_ID; /* chip class */
++		break;
++		default:
++		break;
++	}
++}
++
++/**
++ * Allocate an si handle. This function may be called multiple times.
++ *
++ * vars - pointer to a to-be created pointer area for "environment" variables. Some callers of this
++ *        function set 'vars' to NULL.
++ */
++static si_info_t *
++si_doattach(si_info_t *sii, uint devid, osl_t *osh, void *regs,
++                       uint bustype, void *sdh, char **vars, uint *varsz)
++{
++	struct si_pub *sih = &sii->pub;
++	uint32 w, savewin;
++	chipcregs_t *cc;
++	char *pvars = NULL;
++	uint origidx;
++#if !defined(_CFEZ_) || defined(CFG_WL)
++#endif 
++
++	ASSERT(GOODREGS(regs));
++
++	savewin = 0;
++
++	sih->buscoreidx = BADIDX;
++
++	sii->curmap = regs;
++	sii->sdh = sdh;
++	sii->osh = osh;
++	sii->second_bar0win = ~0x0;
++
++
++	/* check to see if we are a si core mimic'ing a pci core */
++	if ((bustype == PCI_BUS) &&
++	    (OSL_PCI_READ_CONFIG(sii->osh, PCI_SPROM_CONTROL, sizeof(uint32)) == 0xffffffff)) {
++		SI_ERROR(("%s: incoming bus is PCI but it's a lie, switching to SI "
++		          "devid:0x%x\n", __FUNCTION__, devid));
++		bustype = SI_BUS;
++	}
++
++	/* find Chipcommon address */
++	if (bustype == PCI_BUS) {
++		savewin = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
++		if (!GOODCOREADDR(savewin, SI_ENUM_BASE))
++			savewin = SI_ENUM_BASE;
++		OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, SI_ENUM_BASE);
++		if (!regs)
++			return NULL;
++		cc = (chipcregs_t *)regs;
++#ifdef BCMSDIO
++	} else if ((bustype == SDIO_BUS) || (bustype == SPI_BUS)) {
++		cc = (chipcregs_t *)sii->curmap;
++#endif
++	} else {
++		cc = (chipcregs_t *)REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
++	}
++
++	sih->bustype = bustype;
++#ifdef BCMBUSTYPE
++	/* Fix the -Werror=tautological-compare compiling error */
++	if (bustype != BUSTYPE(bustype)) {
++		SI_ERROR(("si_doattach: bus type %d does not match configured bus type %d\n",
++			bustype, BUSTYPE(bustype)));
++		return NULL;
++	}
++#endif
++
++	/* bus/core/clk setup for register access */
++	if (!si_buscore_prep(sii, bustype, devid, sdh)) {
++		SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n", bustype));
++		return NULL;
++	}
++
++	/* ChipID recognition.
++	*   We assume we can read chipid at offset 0 from the regs arg.
++	*   If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon),
++	*   some way of recognizing them needs to be added here.
++	*/
++	if (!cc) {
++		SI_ERROR(("%s: chipcommon register space is null \n", __FUNCTION__));
++		return NULL;
++	}
++	w = R_REG(osh, &cc->chipid);
++	if ((w & 0xfffff) == 148277) w -= 65532;
++	sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
++	/* Might as wll fill in chip id rev & pkg */
++	sih->chip = w & CID_ID_MASK;
++	sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;
++	sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;
++
++	si_chipid_fixup(sih);
++
++	if ((CHIPID(sih->chip) == BCM4329_CHIP_ID) && CHIPREV(sih->chiprev == 0) &&
++		(sih->chippkg != BCM4329_289PIN_PKG_ID)) {
++		sih->chippkg = BCM4329_182PIN_PKG_ID;
++	}
++	sih->issim = IS_SIM(sih->chippkg);
++
++	/* scan for cores */
++	if (CHIPTYPE(sii->pub.socitype) == SOCI_SB) {
++		SI_MSG(("Found chip type SB (0x%08x)\n", w));
++		sb_scan(&sii->pub, regs, devid);
++	} else if ((CHIPTYPE(sii->pub.socitype) == SOCI_AI) ||
++		(CHIPTYPE(sii->pub.socitype) == SOCI_NAI)) {
++		if (CHIPTYPE(sii->pub.socitype) == SOCI_AI)
++			SI_MSG(("Found chip type AI (0x%08x)\n", w));
++		else
++			SI_MSG(("Found chip type NAI (0x%08x)\n", w));
++		/* pass chipc address instead of original core base */
++		ai_scan(&sii->pub, (void *)(uintptr)cc, devid);
++	} else if (CHIPTYPE(sii->pub.socitype) == SOCI_UBUS) {
++		SI_MSG(("Found chip type UBUS (0x%08x), chip id = 0x%4x\n", w, sih->chip));
++		/* pass chipc address instead of original core base */
++		ub_scan(&sii->pub, (void *)(uintptr)cc, devid);
++	} else {
++		SI_ERROR(("Found chip of unknown type (0x%08x)\n", w));
++		return NULL;
++	}
++	/* no cores found, bail out */
++	if (sii->numcores == 0) {
++		SI_ERROR(("si_doattach: could not find any cores\n"));
++		return NULL;
++	}
++	/* bus/core/clk setup */
++	origidx = SI_CC_IDX;
++	if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) {
++		SI_ERROR(("si_doattach: si_buscore_setup failed\n"));
++		goto exit;
++	}
++
++#if !defined(_CFEZ_) || defined(CFG_WL)
++	if (CHIPID(sih->chip) == BCM4322_CHIP_ID && (((sih->chipst & CST4322_SPROM_OTP_SEL_MASK)
++		>> CST4322_SPROM_OTP_SEL_SHIFT) == (CST4322_OTP_PRESENT |
++		CST4322_SPROM_PRESENT))) {
++		SI_ERROR(("%s: Invalid setting: both SPROM and OTP strapped.\n", __FUNCTION__));
++		return NULL;
++	}
++
++	/* assume current core is CC */
++	if ((sii->pub.ccrev == 0x25) && ((CHIPID(sih->chip) == BCM43236_CHIP_ID ||
++	                                  CHIPID(sih->chip) == BCM43235_CHIP_ID ||
++	                                  CHIPID(sih->chip) == BCM43234_CHIP_ID ||
++	                                  CHIPID(sih->chip) == BCM43238_CHIP_ID) &&
++	                                 (CHIPREV(sii->pub.chiprev) <= 2))) {
++
++		if ((cc->chipstatus & CST43236_BP_CLK) != 0) {
++			uint clkdiv;
++			clkdiv = R_REG(osh, &cc->clkdiv);
++			/* otp_clk_div is even number, 120/14 < 9mhz */
++			clkdiv = (clkdiv & ~CLKD_OTP) | (14 << CLKD_OTP_SHIFT);
++			W_REG(osh, &cc->clkdiv, clkdiv);
++			SI_ERROR(("%s: set clkdiv to %x\n", __FUNCTION__, clkdiv));
++		}
++		OSL_DELAY(10);
++	}
++
++	if (bustype == PCI_BUS) {
++
++	}
++#endif 
++#ifdef BCM_SDRBL
++	/* 4360 rom bootloader in PCIE case, if the SDR is enabled, But preotection is
++	 * not turned on, then we want to hold arm in reset.
++	 * Bottomline: In sdrenable case, we allow arm to boot only when protection is
++	 * turned on.
++	 */
++	if (CHIP_HOSTIF_PCIE(&(sii->pub))) {
++		uint32 sflags = si_arm_sflags(&(sii->pub));
++
++		/* If SDR is enabled but protection is not turned on
++		* then we want to force arm to WFI.
++		*/
++		if ((sflags & (SISF_SDRENABLE | SISF_TCMPROT)) == SISF_SDRENABLE) {
++			disable_arm_irq();
++			while (1) {
++				hnd_cpu_wait(sih);
++			}
++		}
++	}
++#endif /* BCM_SDRBL */
++
++	pvars = NULL;
++	BCM_REFERENCE(pvars);
++
++
++
++		if (sii->pub.ccrev >= 20) {
++			uint32 gpiopullup = 0, gpiopulldown = 0;
++			cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
++			ASSERT(cc != NULL);
++
++			/* 4314/43142 has pin muxing, don't clear gpio bits */
++			if ((CHIPID(sih->chip) == BCM4314_CHIP_ID) ||
++				(CHIPID(sih->chip) == BCM43142_CHIP_ID)) {
++				gpiopullup |= 0x402e0;
++				gpiopulldown |= 0x20500;
++			}
++
++
++			W_REG(osh, &cc->gpiopullup, gpiopullup);
++			W_REG(osh, &cc->gpiopulldown, gpiopulldown);
++			si_setcoreidx(sih, origidx);
++		}
++
++
++	/* clear any previous epidiag-induced target abort */
++	ASSERT(!si_taclear(sih, FALSE));
++
++
++#ifdef BOOTLOADER_CONSOLE_OUTPUT
++	/* Enable console prints */
++	si_muxenab(sii, 3);
++#endif
++
++	return (sii);
++
++exit:
++
++	return NULL;
++}
++
++/** may be called with core in reset */
++void
++si_detach(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint idx;
++
++
++	if (BUSTYPE(sih->bustype) == SI_BUS)
++		for (idx = 0; idx < SI_MAXCORES; idx++)
++			if (cores_info->regs[idx]) {
++				REG_UNMAP(cores_info->regs[idx]);
++				cores_info->regs[idx] = NULL;
++			}
++
++
++#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SI_BUS)
++	if (cores_info != &ksii_cores_info)
++#endif	/* !BCMBUSTYPE || (BCMBUSTYPE == SI_BUS) */
++		MFREE(sii->osh, cores_info, sizeof(si_cores_info_t));
++
++#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SI_BUS)
++	if (sii != &ksii)
++#endif	/* !BCMBUSTYPE || (BCMBUSTYPE == SI_BUS) */
++		MFREE(sii->osh, sii, sizeof(si_info_t));
++}
++
++void *
++si_osh(si_t *sih)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++	return sii->osh;
++}
++
++void
++si_setosh(si_t *sih, osl_t *osh)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++	if (sii->osh != NULL) {
++		SI_ERROR(("osh is already set....\n"));
++		ASSERT(!sii->osh);
++	}
++	sii->osh = osh;
++}
++
++/** register driver interrupt disabling and restoring callback functions */
++void
++si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
++                          void *intrsenabled_fn, void *intr_arg)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	sii->intr_arg = intr_arg;
++	sii->intrsoff_fn = (si_intrsoff_t)intrsoff_fn;
++	sii->intrsrestore_fn = (si_intrsrestore_t)intrsrestore_fn;
++	sii->intrsenabled_fn = (si_intrsenabled_t)intrsenabled_fn;
++	/* save current core id.  when this function called, the current core
++	 * must be the core which provides driver functions(il, et, wl, etc.)
++	 */
++	sii->dev_coreid = cores_info->coreid[sii->curidx];
++}
++
++void
++si_deregister_intr_callback(si_t *sih)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++	sii->intrsoff_fn = NULL;
++	sii->intrsrestore_fn = NULL;
++	sii->intrsenabled_fn = NULL;
++}
++
++uint
++si_intflag(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_intflag(sih);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return R_REG(sii->osh, ((uint32 *)(uintptr)
++			    (sii->oob_router + OOB_STATUSA)));
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++uint
++si_flag(si_t *sih)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_flag(sih);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_flag(sih);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_flag(sih);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++uint
++si_flag_alt(si_t *sih)
++{
++	if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_flag_alt(sih);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++void
++si_setint(si_t *sih, int siflag)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		sb_setint(sih, siflag);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		ai_setint(sih, siflag);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		ub_setint(sih, siflag);
++	else
++		ASSERT(0);
++}
++
++uint
++si_coreid(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	return cores_info->coreid[sii->curidx];
++}
++
++uint
++si_coreidx(si_t *sih)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++	return sii->curidx;
++}
++
++void *
++si_d11_switch_addrbase(si_t *sih, uint coreunit)
++{
++	return si_setcore(sih,  D11_CORE_ID, coreunit);
++}
++
++/** return the core-type instantiation # of the current core */
++uint
++si_coreunit(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint idx;
++	uint coreid;
++	uint coreunit;
++	uint i;
++
++	coreunit = 0;
++
++	idx = sii->curidx;
++
++	ASSERT(GOODREGS(sii->curmap));
++	coreid = si_coreid(sih);
++
++	/* count the cores of our type */
++	for (i = 0; i < idx; i++)
++		if (cores_info->coreid[i] == coreid)
++			coreunit++;
++
++	return (coreunit);
++}
++
++uint
++si_corevendor(si_t *sih)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_corevendor(sih);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_corevendor(sih);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_corevendor(sih);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++bool
++si_backplane64(si_t *sih)
++{
++	return ((sih->cccaps & CC_CAP_BKPLN64) != 0);
++}
++
++uint
++si_corerev(si_t *sih)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_corerev(sih);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_corerev(sih);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_corerev(sih);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++
++/* return index of coreid or BADIDX if not found */
++uint
++si_findcoreidx(si_t *sih, uint coreid, uint coreunit)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint found;
++	uint i;
++
++
++	found = 0;
++
++	for (i = 0; i < sii->numcores; i++)
++		if (cores_info->coreid[i] == coreid) {
++			if (found == coreunit)
++				return (i);
++			found++;
++		}
++
++	return (BADIDX);
++}
++
++/** return total coreunit of coreid or zero if not found */
++uint
++si_numcoreunits(si_t *sih, uint coreid)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint found = 0;
++	uint i;
++
++	for (i = 0; i < sii->numcores; i++) {
++		if (cores_info->coreid[i] == coreid) {
++			found++;
++		}
++	}
++
++	return found;
++}
++
++/** return total D11 coreunits */
++uint
++BCMRAMFN(si_numd11coreunits)(si_t *sih)
++{
++	uint found = 0;
++
++	found = si_numcoreunits(sih, D11_CORE_ID);
++
++#if defined(WLRSDB) && defined(WLRSDB_DISABLED)
++	/* If RSDB functionality is compiled out,
++	 * then ignore any D11 cores beyond the first
++	 * Used in norsdb dongle build variants for rsdb chip.
++	 */
++	found = 1;
++#endif /* defined(WLRSDB) && !defined(WLRSDB_DISABLED) */
++
++	return found;
++}
++
++/** return list of found cores */
++uint
++si_corelist(si_t *sih, uint coreid[])
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	bcopy((uchar*)cores_info->coreid, (uchar*)coreid, (sii->numcores * sizeof(uint)));
++	return (sii->numcores);
++}
++
++/** return current wrapper mapping */
++void *
++si_wrapperregs(si_t *sih)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++	ASSERT(GOODREGS(sii->curwrap));
++
++	return (sii->curwrap);
++}
++
++/** return current register mapping */
++void *
++si_coreregs(si_t *sih)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++	ASSERT(GOODREGS(sii->curmap));
++
++	return (sii->curmap);
++}
++
++/**
++ * This function changes logical "focus" to the indicated core;
++ * must be called with interrupts off.
++ * Moreover, callers should keep interrupts off during switching out of and back to d11 core
++ */
++void *
++si_setcore(si_t *sih, uint coreid, uint coreunit)
++{
++	uint idx;
++
++	idx = si_findcoreidx(sih, coreid, coreunit);
++	if (!GOODIDX(idx))
++		return (NULL);
++
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_setcoreidx(sih, idx);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_setcoreidx(sih, idx);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_setcoreidx(sih, idx);
++	else {
++		ASSERT(0);
++		return NULL;
++	}
++}
++
++void *
++si_setcoreidx(si_t *sih, uint coreidx)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_setcoreidx(sih, coreidx);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_setcoreidx(sih, coreidx);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_setcoreidx(sih, coreidx);
++	else {
++		ASSERT(0);
++		return NULL;
++	}
++}
++
++/** Turn off interrupt as required by sb_setcore, before switch core */
++void *
++si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val)
++{
++	void *cc;
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	if (SI_FAST(sii)) {
++		/* Overloading the origidx variable to remember the coreid,
++		 * this works because the core ids cannot be confused with
++		 * core indices.
++		 */
++		*origidx = coreid;
++		if (coreid == CC_CORE_ID)
++			return (void *)CCREGS_FAST(sii);
++		else if (coreid == sih->buscoretype)
++			return (void *)PCIEREGS(sii);
++	}
++	INTR_OFF(sii, *intr_val);
++	*origidx = sii->curidx;
++	cc = si_setcore(sih, coreid, 0);
++	ASSERT(cc != NULL);
++
++	return cc;
++}
++
++/* restore coreidx and restore interrupt */
++void
++si_restore_core(si_t *sih, uint coreid, uint intr_val)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	if (SI_FAST(sii) && ((coreid == CC_CORE_ID) || (coreid == sih->buscoretype)))
++		return;
++
++	si_setcoreidx(sih, coreid);
++	INTR_RESTORE(sii, intr_val);
++}
++
++int
++si_numaddrspaces(si_t *sih)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_numaddrspaces(sih);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_numaddrspaces(sih);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_numaddrspaces(sih);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++uint32
++si_addrspace(si_t *sih, uint asidx)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_addrspace(sih, asidx);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_addrspace(sih, asidx);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_addrspace(sih, asidx);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++uint32
++si_addrspacesize(si_t *sih, uint asidx)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_addrspacesize(sih, asidx);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_addrspacesize(sih, asidx);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_addrspacesize(sih, asidx);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++void
++si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size)
++{
++	/* Only supported for SOCI_AI */
++	if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		ai_coreaddrspaceX(sih, asidx, addr, size);
++	else
++		*size = 0;
++}
++
++uint32
++si_core_cflags(si_t *sih, uint32 mask, uint32 val)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_core_cflags(sih, mask, val);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_core_cflags(sih, mask, val);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_core_cflags(sih, mask, val);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++void
++si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		sb_core_cflags_wo(sih, mask, val);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		ai_core_cflags_wo(sih, mask, val);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		ub_core_cflags_wo(sih, mask, val);
++	else
++		ASSERT(0);
++}
++
++uint32
++si_core_sflags(si_t *sih, uint32 mask, uint32 val)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_core_sflags(sih, mask, val);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_core_sflags(sih, mask, val);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_core_sflags(sih, mask, val);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++bool
++si_iscoreup(si_t *sih)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_iscoreup(sih);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_iscoreup(sih);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_iscoreup(sih);
++	else {
++		ASSERT(0);
++		return FALSE;
++	}
++}
++
++uint
++si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val)
++{
++	/* only for AI back plane chips */
++	if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return (ai_wrap_reg(sih, offset, mask, val));
++	return 0;
++}
++/* si_backplane_access is used to read full backplane address from host for PCIE FD
++ * it uses secondary bar-0 window which lies at an offset of 16K from primary bar-0
++ * Provides support for read/write of 1/2/4 bytes of backplane address
++ * Can be used to read/write
++ *	1. core regs
++ *	2. Wrapper regs
++ *	3. memory
++ *	4. BT area
++ * For accessing any 32 bit backplane address, [31 : 12] of backplane should be given in "region"
++ * [11 : 0] should be the "regoff"
++ * for reading  4 bytes from reg 0x200 of d11 core use it like below
++ * : si_backplane_access(sih, 0x18001000, 0x200, 4, 0, TRUE)
++ */
++static int si_backplane_addr_sane(uint addr, uint size)
++{
++	int bcmerror = BCME_OK;
++
++	/* For 2 byte access, address has to be 2 byte aligned */
++	if (size == 2) {
++		if (addr & 0x1) {
++			bcmerror = BCME_ERROR;
++		}
++	}
++	/* For 4 byte access, address has to be 4 byte aligned */
++	if (size == 4) {
++		if (addr & 0x3) {
++			bcmerror = BCME_ERROR;
++		}
++	}
++
++	return bcmerror;
++}
++uint
++si_backplane_access(si_t *sih, uint addr, uint size, uint *val, bool read)
++{
++	uint32 *r = NULL;
++	uint32 region = 0;
++	si_info_t *sii = SI_INFO(sih);
++
++	/* Valid only for pcie bus */
++	if (BUSTYPE(sih->bustype) != PCI_BUS) {
++		SI_ERROR(("Valid only for pcie bus \n"));
++		return BCME_ERROR;
++	}
++
++	/* Split adrr into region and address offset */
++	region = (addr & (0xFFFFF << 12));
++	addr = addr & 0xFFF;
++
++	/* check for address and size sanity */
++	if (si_backplane_addr_sane(addr, size) != BCME_OK)
++		return BCME_ERROR;
++
++	/* Update window if required */
++	if (sii->second_bar0win != region) {
++		OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_CORE2_WIN, 4, region);
++		sii->second_bar0win = region;
++	}
++
++	/* Estimate effective address
++	 * sii->curmap   : bar-0 virtual address
++	 * PCI_SECOND_BAR0_OFFSET  : secondar bar-0 offset
++	 * regoff : actual reg offset
++	 */
++	r = (uint32 *)((char *)sii->curmap + PCI_SECOND_BAR0_OFFSET + addr);
++
++	SI_VMSG(("si curmap %p  region %x regaddr %x effective addr %p READ %d\n",
++		(char*)sii->curmap, region, addr, r, read));
++
++	switch (size) {
++		case sizeof(uint8) :
++			if (read)
++				*val = R_REG(sii->osh, (uint8*)r);
++			else
++				W_REG(sii->osh, (uint8*)r, *val);
++			break;
++		case sizeof(uint16) :
++			if (read)
++				*val = R_REG(sii->osh, (uint16*)r);
++			else
++				W_REG(sii->osh, (uint16*)r, *val);
++			break;
++		case sizeof(uint32) :
++			if (read)
++				*val = R_REG(sii->osh, (uint32*)r);
++			else
++				W_REG(sii->osh, (uint32*)r, *val);
++			break;
++
++		default :
++			SI_ERROR(("Invalid  size %d \n", size));
++			return (BCME_ERROR);
++			break;
++	}
++
++	return (BCME_OK);
++}
++uint
++si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_corereg(sih, coreidx, regoff, mask, val);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_corereg(sih, coreidx, regoff, mask, val);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		return ub_corereg(sih, coreidx, regoff, mask, val);
++	else {
++		ASSERT(0);
++		return 0;
++	}
++}
++
++/** ILP sensitive register access needs special treatment to avoid backplane stalls */
++bool si_pmu_is_ilp_sensitive(uint32 idx, uint regoff)
++{
++	if (idx == SI_CC_IDX) {
++		if (CHIPCREGS_ILP_SENSITIVE(regoff))
++			return TRUE;
++	} else if (PMUREGS_ILP_SENSITIVE(regoff)) {
++		return TRUE;
++	}
++
++	return FALSE;
++}
++
++/** 'idx' should refer either to the chipcommon core or the PMU core */
++uint
++si_pmu_corereg(si_t *sih, uint32 idx, uint regoff, uint mask, uint val)
++{
++	int pmustatus_offset;
++
++	/* prevent backplane stall on double write to 'ILP domain' registers in the PMU */
++	if (mask != 0 && sih->pmurev >= 22 &&
++	    si_pmu_is_ilp_sensitive(idx, regoff)) {
++		pmustatus_offset = AOB_ENAB(sih) ? OFFSETOF(pmuregs_t, pmustatus) :
++			OFFSETOF(chipcregs_t, pmustatus);
++
++		while (si_corereg(sih, idx, pmustatus_offset, 0, 0) & PST_SLOW_WR_PENDING)
++			{};
++	}
++
++	return si_corereg(sih, idx, regoff, mask, val);
++}
++
++/*
++ * If there is no need for fiddling with interrupts or core switches (typically silicon
++ * back plane registers, pci registers and chipcommon registers), this function
++ * returns the register offset on this core to a mapped address. This address can
++ * be used for W_REG/R_REG directly.
++ *
++ * For accessing registers that would need a core switch, this function will return
++ * NULL.
++ */
++uint32 *
++si_corereg_addr(si_t *sih, uint coreidx, uint regoff)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		return sb_corereg_addr(sih, coreidx, regoff);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		return ai_corereg_addr(sih, coreidx, regoff);
++	else {
++		return 0;
++	}
++}
++
++void
++si_core_disable(si_t *sih, uint32 bits)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		sb_core_disable(sih, bits);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		ai_core_disable(sih, bits);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		ub_core_disable(sih, bits);
++}
++
++void
++si_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
++{
++	if (CHIPTYPE(sih->socitype) == SOCI_SB)
++		sb_core_reset(sih, bits, resetbits);
++	else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
++		ai_core_reset(sih, bits, resetbits);
++	else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
++		ub_core_reset(sih, bits, resetbits);
++}
++
++/** Run bist on current core. Caller needs to take care of core-specific bist hazards */
++int
++si_corebist(si_t *sih)
++{
++	uint32 cflags;
++	int result = 0;
++
++	/* Read core control flags */
++	cflags = si_core_cflags(sih, 0, 0);
++
++	/* Set bist & fgc */
++	si_core_cflags(sih, ~0, (SICF_BIST_EN | SICF_FGC));
++
++	/* Wait for bist done */
++	SPINWAIT(((si_core_sflags(sih, 0, 0) & SISF_BIST_DONE) == 0), 100000);
++
++	if (si_core_sflags(sih, 0, 0) & SISF_BIST_ERROR)
++		result = BCME_ERROR;
++
++	/* Reset core control flags */
++	si_core_cflags(sih, 0xffff, cflags);
++
++	return result;
++}
++
++static uint32
++factor6(uint32 x)
++{
++	switch (x) {
++	case CC_F6_2:	return 2;
++	case CC_F6_3:	return 3;
++	case CC_F6_4:	return 4;
++	case CC_F6_5:	return 5;
++	case CC_F6_6:	return 6;
++	case CC_F6_7:	return 7;
++	default:	return 0;
++	}
++}
++
++/*
++ * Divide the clock by the divisor with protection for
++ * a zero divisor.
++ */
++static uint32
++divide_clock(uint32 clock, uint32 div)
++{
++	return div ? clock / div : 0;
++}
++
++
++/** calculate the speed the SI would run at given a set of clockcontrol values */
++uint32
++si_clock_rate(uint32 pll_type, uint32 n, uint32 m)
++{
++	uint32 n1, n2, clock, m1, m2, m3, mc;
++
++	n1 = n & CN_N1_MASK;
++	n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
++
++	if (pll_type == PLL_TYPE6) {
++		if (m & CC_T6_MMASK)
++			return CC_T6_M1;
++		else
++			return CC_T6_M0;
++	} else if ((pll_type == PLL_TYPE1) ||
++	           (pll_type == PLL_TYPE3) ||
++	           (pll_type == PLL_TYPE4) ||
++	           (pll_type == PLL_TYPE7)) {
++		n1 = factor6(n1);
++		n2 += CC_F5_BIAS;
++	} else if (pll_type == PLL_TYPE2) {
++		n1 += CC_T2_BIAS;
++		n2 += CC_T2_BIAS;
++		ASSERT((n1 >= 2) && (n1 <= 7));
++		ASSERT((n2 >= 5) && (n2 <= 23));
++	} else if (pll_type == PLL_TYPE5) {
++		return (100000000);
++	} else
++		ASSERT(0);
++	/* PLL types 3 and 7 use BASE2 (25Mhz) */
++	if ((pll_type == PLL_TYPE3) ||
++	    (pll_type == PLL_TYPE7)) {
++		clock = CC_CLOCK_BASE2 * n1 * n2;
++	} else
++		clock = CC_CLOCK_BASE1 * n1 * n2;
++
++	if (clock == 0)
++		return 0;
++
++	m1 = m & CC_M1_MASK;
++	m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
++	m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
++	mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
++
++	if ((pll_type == PLL_TYPE1) ||
++	    (pll_type == PLL_TYPE3) ||
++	    (pll_type == PLL_TYPE4) ||
++	    (pll_type == PLL_TYPE7)) {
++		m1 = factor6(m1);
++		if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
++			m2 += CC_F5_BIAS;
++		else
++			m2 = factor6(m2);
++		m3 = factor6(m3);
++
++		switch (mc) {
++		case CC_MC_BYPASS:	return (clock);
++		case CC_MC_M1:		return divide_clock(clock, m1);
++		case CC_MC_M1M2:	return divide_clock(clock, m1 * m2);
++		case CC_MC_M1M2M3:	return divide_clock(clock, m1 * m2 * m3);
++		case CC_MC_M1M3:	return divide_clock(clock, m1 * m3);
++		default:		return (0);
++		}
++	} else {
++		ASSERT(pll_type == PLL_TYPE2);
++
++		m1 += CC_T2_BIAS;
++		m2 += CC_T2M2_BIAS;
++		m3 += CC_T2_BIAS;
++		ASSERT((m1 >= 2) && (m1 <= 7));
++		ASSERT((m2 >= 3) && (m2 <= 10));
++		ASSERT((m3 >= 2) && (m3 <= 7));
++
++		if ((mc & CC_T2MC_M1BYP) == 0)
++			clock /= m1;
++		if ((mc & CC_T2MC_M2BYP) == 0)
++			clock /= m2;
++		if ((mc & CC_T2MC_M3BYP) == 0)
++			clock /= m3;
++
++		return (clock);
++	}
++	return 0;
++}
++
++/**
++ * Some chips could have multiple host interfaces, however only one will be active.
++ * For a given chip. Depending pkgopt and cc_chipst return the active host interface.
++ */
++uint
++si_chip_hostif(si_t *sih)
++{
++	uint hosti = 0;
++
++	switch (CHIPID(sih->chip)) {
++
++	CASE_BCM43602_CHIP:
++		hosti = CHIP_HOSTIF_PCIEMODE;
++		break;
++
++	case BCM4360_CHIP_ID:
++		/* chippkg bit-0 == 0 is PCIE only pkgs
++		 * chippkg bit-0 == 1 has both PCIE and USB cores enabled
++		 */
++		if ((sih->chippkg & 0x1) && (sih->chipst & CST4360_MODE_USB))
++			hosti = CHIP_HOSTIF_USBMODE;
++		else
++			hosti = CHIP_HOSTIF_PCIEMODE;
++
++		break;
++
++	case BCM4335_CHIP_ID:
++		/* TBD: like in 4360, do we need to check pkg? */
++		if (CST4335_CHIPMODE_USB20D(sih->chipst))
++			hosti = CHIP_HOSTIF_USBMODE;
++		else if (CST4335_CHIPMODE_SDIOD(sih->chipst))
++			hosti = CHIP_HOSTIF_SDIOMODE;
++		else
++			hosti = CHIP_HOSTIF_PCIEMODE;
++		break;
++
++	case BCM4345_CHIP_ID:
++	case BCM43454_CHIP_ID:
++		if (CST4345_CHIPMODE_USB20D(sih->chipst) || CST4345_CHIPMODE_HSIC(sih->chipst))
++			hosti = CHIP_HOSTIF_USBMODE;
++		else if (CST4345_CHIPMODE_SDIOD(sih->chipst))
++			hosti = CHIP_HOSTIF_SDIOMODE;
++		else if (CST4345_CHIPMODE_PCIE(sih->chipst))
++			hosti = CHIP_HOSTIF_PCIEMODE;
++		break;
++
++	case BCM4349_CHIP_GRPID:
++		if (CST4349_CHIPMODE_SDIOD(sih->chipst))
++			hosti = CHIP_HOSTIF_SDIOMODE;
++		else if (CST4349_CHIPMODE_PCIE(sih->chipst))
++			hosti = CHIP_HOSTIF_PCIEMODE;
++		break;
++
++	case BCM4350_CHIP_ID:
++	case BCM4354_CHIP_ID:
++	case BCM4356_CHIP_ID:
++	case BCM43556_CHIP_ID:
++	case BCM43558_CHIP_ID:
++	case BCM43566_CHIP_ID:
++	case BCM43568_CHIP_ID:
++	case BCM43569_CHIP_ID:
++	case BCM43570_CHIP_ID:
++	case BCM4358_CHIP_ID:
++		if (CST4350_CHIPMODE_USB20D(sih->chipst) ||
++		    CST4350_CHIPMODE_HSIC20D(sih->chipst) ||
++		    CST4350_CHIPMODE_USB30D(sih->chipst) ||
++		    CST4350_CHIPMODE_USB30D_WL(sih->chipst) ||
++		    CST4350_CHIPMODE_HSIC30D(sih->chipst))
++			hosti = CHIP_HOSTIF_USBMODE;
++		else if (CST4350_CHIPMODE_SDIOD(sih->chipst))
++			hosti = CHIP_HOSTIF_SDIOMODE;
++		else if (CST4350_CHIPMODE_PCIE(sih->chipst))
++			hosti = CHIP_HOSTIF_PCIEMODE;
++		break;
++
++	default:
++		break;
++	}
++
++	return hosti;
++}
++
++
++/** set chip watchdog reset timer to fire in 'ticks' */
++void
++si_watchdog(si_t *sih, uint ticks)
++{
++	uint nb, maxt;
++
++	if (PMUCTL_ENAB(sih)) {
++
++#if !defined(_CFEZ_) || defined(CFG_WL)
++		if ((CHIPID(sih->chip) == BCM4319_CHIP_ID) &&
++		    (CHIPREV(sih->chiprev) == 0) && (ticks != 0)) {
++			si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), ~0, 0x2);
++			si_setcore(sih, USB20D_CORE_ID, 0);
++			si_core_disable(sih, 1);
++			si_setcore(sih, CC_CORE_ID, 0);
++		}
++#endif 
++
++			nb = (sih->ccrev < 26) ? 16 : ((sih->ccrev >= 37) ? 32 : 24);
++		/* The mips compiler uses the sllv instruction,
++		 * so we specially handle the 32-bit case.
++		 */
++		if (nb == 32)
++			maxt = 0xffffffff;
++		else
++			maxt = ((1 << nb) - 1);
++
++		if (ticks == 1)
++			ticks = 2;
++		else if (ticks > maxt)
++			ticks = maxt;
++		if (CHIPID(sih->chip) == BCM43012_CHIP_ID) {
++			PMU_REG_NEW(sih, min_res_mask, ~0, DEFAULT_43012_MIN_RES_MASK);
++			PMU_REG_NEW(sih, watchdog_res_mask, ~0, DEFAULT_43012_MIN_RES_MASK);
++			PMU_REG_NEW(sih, pmustatus, PST_WDRESET, PST_WDRESET);
++			PMU_REG_NEW(sih, pmucontrol_ext, PCTL_EXT_FASTLPO_SWENAB, 0);
++			SPINWAIT((PMU_REG(sih, pmustatus, 0, 0) & PST_ILPFASTLPO),
++				PMU_MAX_TRANSITION_DLY);
++		}
++
++		pmu_corereg(sih, SI_CC_IDX, pmuwatchdog, ~0, ticks);
++	} else {
++		maxt = (1 << 28) - 1;
++		if (ticks > maxt)
++			ticks = maxt;
++
++		si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
++	}
++}
++
++/** trigger watchdog reset after ms milliseconds */
++void
++si_watchdog_ms(si_t *sih, uint32 ms)
++{
++	si_watchdog(sih, wd_msticks * ms);
++}
++
++uint32 si_watchdog_msticks(void)
++{
++	return wd_msticks;
++}
++
++bool
++si_taclear(si_t *sih, bool details)
++{
++	return FALSE;
++}
++
++
++
++/** return the slow clock source - LPO, XTAL, or PCI */
++static uint
++si_slowclk_src(si_info_t *sii)
++{
++	chipcregs_t *cc;
++
++	ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
++
++	if (sii->pub.ccrev < 6) {
++		if ((BUSTYPE(sii->pub.bustype) == PCI_BUS) &&
++		    (OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32)) &
++		     PCI_CFG_GPIO_SCS))
++			return (SCC_SS_PCI);
++		else
++			return (SCC_SS_XTAL);
++	} else if (sii->pub.ccrev < 10) {
++		cc = (chipcregs_t *)si_setcoreidx(&sii->pub, sii->curidx);
++		ASSERT(cc);
++		return (R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK);
++	} else	/* Insta-clock */
++		return (SCC_SS_XTAL);
++}
++
++/** return the ILP (slowclock) min or max frequency */
++static uint
++si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
++{
++	uint32 slowclk;
++	uint div;
++
++	ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
++
++	/* shouldn't be here unless we've established the chip has dynamic clk control */
++	ASSERT(R_REG(sii->osh, &cc->capabilities) & CC_CAP_PWR_CTL);
++
++	slowclk = si_slowclk_src(sii);
++	if (sii->pub.ccrev < 6) {
++		if (slowclk == SCC_SS_PCI)
++			return (max_freq ? (PCIMAXFREQ / 64) : (PCIMINFREQ / 64));
++		else
++			return (max_freq ? (XTALMAXFREQ / 32) : (XTALMINFREQ / 32));
++	} else if (sii->pub.ccrev < 10) {
++		div = 4 *
++		        (((R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
++		if (slowclk == SCC_SS_LPO)
++			return (max_freq ? LPOMAXFREQ : LPOMINFREQ);
++		else if (slowclk == SCC_SS_XTAL)
++			return (max_freq ? (XTALMAXFREQ / div) : (XTALMINFREQ / div));
++		else if (slowclk == SCC_SS_PCI)
++			return (max_freq ? (PCIMAXFREQ / div) : (PCIMINFREQ / div));
++		else
++			ASSERT(0);
++	} else {
++		/* Chipc rev 10 is InstaClock */
++		div = R_REG(sii->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;
++		div = 4 * (div + 1);
++		return (max_freq ? XTALMAXFREQ : (XTALMINFREQ / div));
++	}
++	return (0);
++}
++
++static void
++si_clkctl_setdelay(si_info_t *sii, void *chipcregs)
++{
++	chipcregs_t *cc = (chipcregs_t *)chipcregs;
++	uint slowmaxfreq, pll_delay, slowclk;
++	uint pll_on_delay, fref_sel_delay;
++
++	pll_delay = PLL_DELAY;
++
++	/* If the slow clock is not sourced by the xtal then add the xtal_on_delay
++	 * since the xtal will also be powered down by dynamic clk control logic.
++	 */
++
++	slowclk = si_slowclk_src(sii);
++	if (slowclk != SCC_SS_XTAL)
++		pll_delay += XTAL_ON_DELAY;
++
++	/* Starting with 4318 it is ILP that is used for the delays */
++	slowmaxfreq = si_slowclk_freq(sii, (sii->pub.ccrev >= 10) ? FALSE : TRUE, cc);
++
++	pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
++	fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
++
++	W_REG(sii->osh, &cc->pll_on_delay, pll_on_delay);
++	W_REG(sii->osh, &cc->fref_sel_delay, fref_sel_delay);
++}
++
++/** initialize power control delay registers */
++void
++si_clkctl_init(si_t *sih)
++{
++	si_info_t *sii;
++	uint origidx = 0;
++	chipcregs_t *cc;
++	bool fast;
++
++	if (!CCCTL_ENAB(sih))
++		return;
++
++	sii = SI_INFO(sih);
++	fast = SI_FAST(sii);
++	if (!fast) {
++		origidx = sii->curidx;
++		if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL)
++			return;
++	} else if ((cc = (chipcregs_t *)CCREGS_FAST(sii)) == NULL)
++		return;
++	ASSERT(cc != NULL);
++
++	/* set all Instaclk chip ILP to 1 MHz */
++	if (sih->ccrev >= 10)
++		SET_REG(sii->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
++		        (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
++
++	si_clkctl_setdelay(sii, (void *)(uintptr)cc);
++
++	OSL_DELAY(20000);
++
++	if (!fast)
++		si_setcoreidx(sih, origidx);
++}
++
++
++/** change logical "focus" to the gpio core for optimized access */
++void *
++si_gpiosetcore(si_t *sih)
++{
++	return (si_setcoreidx(sih, SI_CC_IDX));
++}
++
++/**
++ * mask & set gpiocontrol bits.
++ * If a gpiocontrol bit is set to 0, chipcommon controls the corresponding GPIO pin.
++ * If a gpiocontrol bit is set to 1, the GPIO pin is no longer a GPIO and becomes dedicated
++ *   to some chip-specific purpose.
++ */
++uint32
++si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority)
++{
++	uint regoff;
++
++	regoff = 0;
++
++	/* gpios could be shared on router platforms
++	 * ignore reservation if it's high priority (e.g., test apps)
++	 */
++	if ((priority != GPIO_HI_PRIORITY) &&
++	    (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
++		mask = priority ? (si_gpioreservation & mask) :
++			((si_gpioreservation | mask) & ~(si_gpioreservation));
++		val &= mask;
++	}
++
++	regoff = OFFSETOF(chipcregs_t, gpiocontrol);
++	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
++}
++
++/** mask&set gpio output enable bits */
++uint32
++si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority)
++{
++	uint regoff;
++
++	regoff = 0;
++
++	/* gpios could be shared on router platforms
++	 * ignore reservation if it's high priority (e.g., test apps)
++	 */
++	if ((priority != GPIO_HI_PRIORITY) &&
++	    (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
++		mask = priority ? (si_gpioreservation & mask) :
++			((si_gpioreservation | mask) & ~(si_gpioreservation));
++		val &= mask;
++	}
++
++	regoff = OFFSETOF(chipcregs_t, gpioouten);
++	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
++}
++
++/** mask&set gpio output bits */
++uint32
++si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority)
++{
++	uint regoff;
++
++	regoff = 0;
++
++	/* gpios could be shared on router platforms
++	 * ignore reservation if it's high priority (e.g., test apps)
++	 */
++	if ((priority != GPIO_HI_PRIORITY) &&
++	    (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
++		mask = priority ? (si_gpioreservation & mask) :
++			((si_gpioreservation | mask) & ~(si_gpioreservation));
++		val &= mask;
++	}
++
++	regoff = OFFSETOF(chipcregs_t, gpioout);
++	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
++}
++
++/** reserve one gpio */
++uint32
++si_gpioreserve(si_t *sih, uint32 gpio_bitmask, uint8 priority)
++{
++	/* only cores on SI_BUS share GPIO's and only applcation users need to
++	 * reserve/release GPIO
++	 */
++	if ((BUSTYPE(sih->bustype) != SI_BUS) || (!priority)) {
++		ASSERT((BUSTYPE(sih->bustype) == SI_BUS) && (priority));
++		return 0xffffffff;
++	}
++	/* make sure only one bit is set */
++	if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
++		ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
++		return 0xffffffff;
++	}
++
++	/* already reserved */
++	if (si_gpioreservation & gpio_bitmask)
++		return 0xffffffff;
++	/* set reservation */
++	si_gpioreservation |= gpio_bitmask;
++
++	return si_gpioreservation;
++}
++
++/**
++ * release one gpio.
++ *
++ * releasing the gpio doesn't change the current value on the GPIO last write value
++ * persists till someone overwrites it.
++ */
++uint32
++si_gpiorelease(si_t *sih, uint32 gpio_bitmask, uint8 priority)
++{
++	/* only cores on SI_BUS share GPIO's and only applcation users need to
++	 * reserve/release GPIO
++	 */
++	if ((BUSTYPE(sih->bustype) != SI_BUS) || (!priority)) {
++		ASSERT((BUSTYPE(sih->bustype) == SI_BUS) && (priority));
++		return 0xffffffff;
++	}
++	/* make sure only one bit is set */
++	if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
++		ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
++		return 0xffffffff;
++	}
++
++	/* already released */
++	if (!(si_gpioreservation & gpio_bitmask))
++		return 0xffffffff;
++
++	/* clear reservation */
++	si_gpioreservation &= ~gpio_bitmask;
++
++	return si_gpioreservation;
++}
++
++/* return the current gpioin register value */
++uint32
++si_gpioin(si_t *sih)
++{
++	uint regoff;
++
++	regoff = OFFSETOF(chipcregs_t, gpioin);
++	return (si_corereg(sih, SI_CC_IDX, regoff, 0, 0));
++}
++
++/* mask&set gpio interrupt polarity bits */
++uint32
++si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority)
++{
++	uint regoff;
++
++	/* gpios could be shared on router platforms */
++	if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
++		mask = priority ? (si_gpioreservation & mask) :
++			((si_gpioreservation | mask) & ~(si_gpioreservation));
++		val &= mask;
++	}
++
++	regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
++	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
++}
++
++/* mask&set gpio interrupt mask bits */
++uint32
++si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority)
++{
++	uint regoff;
++
++	/* gpios could be shared on router platforms */
++	if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
++		mask = priority ? (si_gpioreservation & mask) :
++			((si_gpioreservation | mask) & ~(si_gpioreservation));
++		val &= mask;
++	}
++
++	regoff = OFFSETOF(chipcregs_t, gpiointmask);
++	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
++}
++
++/* assign the gpio to an led */
++uint32
++si_gpioled(si_t *sih, uint32 mask, uint32 val)
++{
++	if (sih->ccrev < 16)
++		return 0xffffffff;
++
++	/* gpio led powersave reg */
++	return (si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
++}
++
++/* mask&set gpio timer val */
++uint32
++si_gpiotimerval(si_t *sih, uint32 mask, uint32 gpiotimerval)
++{
++	if (sih->ccrev < 16)
++		return 0xffffffff;
++
++	return (si_corereg(sih, SI_CC_IDX,
++		OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
++}
++
++uint32
++si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val)
++{
++	uint offs;
++
++	if (sih->ccrev < 20)
++		return 0xffffffff;
++
++	offs = (updown ? OFFSETOF(chipcregs_t, gpiopulldown) : OFFSETOF(chipcregs_t, gpiopullup));
++	return (si_corereg(sih, SI_CC_IDX, offs, mask, val));
++}
++
++uint32
++si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val)
++{
++	uint offs;
++
++	if (sih->ccrev < 11)
++		return 0xffffffff;
++
++	if (regtype == GPIO_REGEVT)
++		offs = OFFSETOF(chipcregs_t, gpioevent);
++	else if (regtype == GPIO_REGEVT_INTMSK)
++		offs = OFFSETOF(chipcregs_t, gpioeventintmask);
++	else if (regtype == GPIO_REGEVT_INTPOL)
++		offs = OFFSETOF(chipcregs_t, gpioeventintpolarity);
++	else
++		return 0xffffffff;
++
++	return (si_corereg(sih, SI_CC_IDX, offs, mask, val));
++}
++
++uint32
++si_gpio_int_enable(si_t *sih, bool enable)
++{
++	uint offs;
++
++	if (sih->ccrev < 11)
++		return 0xffffffff;
++
++	offs = OFFSETOF(chipcregs_t, intmask);
++	return (si_corereg(sih, SI_CC_IDX, offs, CI_GPIO, (enable ? CI_GPIO : 0)));
++}
++
++/** Return the size of the specified SYSMEM bank */
++static uint
++sysmem_banksize(si_info_t *sii, sysmemregs_t *regs, uint8 idx)
++{
++	uint banksize, bankinfo;
++	uint bankidx = idx;
++
++	W_REG(sii->osh, &regs->bankidx, bankidx);
++	bankinfo = R_REG(sii->osh, &regs->bankinfo);
++	banksize = SYSMEM_BANKINFO_SZBASE * ((bankinfo & SYSMEM_BANKINFO_SZMASK) + 1);
++	return banksize;
++}
++
++/** Return the RAM size of the SYSMEM core */
++uint32
++si_sysmem_size(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint origidx;
++	uint intr_val = 0;
++
++	sysmemregs_t *regs;
++	bool wasup;
++	uint32 coreinfo;
++	uint memsize = 0;
++	uint8 i;
++	uint nb, nrb;
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	/* Switch to SYSMEM core */
++	if (!(regs = si_setcore(sih, SYSMEM_CORE_ID, 0)))
++		goto done;
++
++	/* Get info for determining size */
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, 0, 0);
++	coreinfo = R_REG(sii->osh, &regs->coreinfo);
++
++	/* Number of ROM banks, SW need to skip the ROM banks. */
++	nrb = (coreinfo & SYSMEM_SRCI_ROMNB_MASK) >> SYSMEM_SRCI_ROMNB_SHIFT;
++
++	nb = (coreinfo & SYSMEM_SRCI_SRNB_MASK) >> SYSMEM_SRCI_SRNB_SHIFT;
++	for (i = 0; i < nb; i++)
++		memsize += sysmem_banksize(sii, regs, i + nrb);
++
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++
++	return memsize;
++}
++
++/** Return the size of the specified SOCRAM bank */
++static uint
++socram_banksize(si_info_t *sii, sbsocramregs_t *regs, uint8 idx, uint8 mem_type)
++{
++	uint banksize, bankinfo;
++	uint bankidx = idx | (mem_type << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
++
++	ASSERT(mem_type <= SOCRAM_MEMTYPE_DEVRAM);
++
++	W_REG(sii->osh, &regs->bankidx, bankidx);
++	bankinfo = R_REG(sii->osh, &regs->bankinfo);
++	banksize = SOCRAM_BANKINFO_SZBASE * ((bankinfo & SOCRAM_BANKINFO_SZMASK) + 1);
++	return banksize;
++}
++
++void si_socram_set_bankpda(si_t *sih, uint32 bankidx, uint32 bankpda)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint origidx;
++	uint intr_val = 0;
++	sbsocramregs_t *regs;
++	bool wasup;
++	uint corerev;
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	/* Switch to SOCRAM core */
++	if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
++		goto done;
++
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, 0, 0);
++
++	corerev = si_corerev(sih);
++	if (corerev >= 16) {
++		W_REG(sii->osh, &regs->bankidx, bankidx);
++		W_REG(sii->osh, &regs->bankpda, bankpda);
++	}
++
++	/* Return to previous state and core */
++	if (!wasup)
++		si_core_disable(sih, 0);
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++}
++
++void
++si_socdevram(si_t *sih, bool set, uint8 *enable, uint8 *protect, uint8 *remap)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint origidx;
++	uint intr_val = 0;
++	sbsocramregs_t *regs;
++	bool wasup;
++	uint corerev;
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	if (!set)
++		*enable = *protect = *remap = 0;
++
++	/* Switch to SOCRAM core */
++	if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
++		goto done;
++
++	/* Get info for determining size */
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, 0, 0);
++
++	corerev = si_corerev(sih);
++	if (corerev >= 10) {
++		uint32 extcinfo;
++		uint8 nb;
++		uint8 i;
++		uint32 bankidx, bankinfo;
++
++		extcinfo = R_REG(sii->osh, &regs->extracoreinfo);
++		nb = ((extcinfo & SOCRAM_DEVRAMBANK_MASK) >> SOCRAM_DEVRAMBANK_SHIFT);
++		for (i = 0; i < nb; i++) {
++			bankidx = i | (SOCRAM_MEMTYPE_DEVRAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
++			W_REG(sii->osh, &regs->bankidx, bankidx);
++			bankinfo = R_REG(sii->osh, &regs->bankinfo);
++			if (set) {
++				bankinfo &= ~SOCRAM_BANKINFO_DEVRAMSEL_MASK;
++				bankinfo &= ~SOCRAM_BANKINFO_DEVRAMPRO_MASK;
++				bankinfo &= ~SOCRAM_BANKINFO_DEVRAMREMAP_MASK;
++				if (*enable) {
++					bankinfo |= (1 << SOCRAM_BANKINFO_DEVRAMSEL_SHIFT);
++					if (*protect)
++						bankinfo |= (1 << SOCRAM_BANKINFO_DEVRAMPRO_SHIFT);
++					if ((corerev >= 16) && *remap)
++						bankinfo |=
++							(1 << SOCRAM_BANKINFO_DEVRAMREMAP_SHIFT);
++				}
++				W_REG(sii->osh, &regs->bankinfo, bankinfo);
++			}
++			else if (i == 0) {
++				if (bankinfo & SOCRAM_BANKINFO_DEVRAMSEL_MASK) {
++					*enable = 1;
++					if (bankinfo & SOCRAM_BANKINFO_DEVRAMPRO_MASK)
++						*protect = 1;
++					if (bankinfo & SOCRAM_BANKINFO_DEVRAMREMAP_MASK)
++						*remap = 1;
++				}
++			}
++		}
++	}
++
++	/* Return to previous state and core */
++	if (!wasup)
++		si_core_disable(sih, 0);
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++}
++
++bool
++si_socdevram_remap_isenb(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint origidx;
++	uint intr_val = 0;
++	sbsocramregs_t *regs;
++	bool wasup, remap = FALSE;
++	uint corerev;
++	uint32 extcinfo;
++	uint8 nb;
++	uint8 i;
++	uint32 bankidx, bankinfo;
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	/* Switch to SOCRAM core */
++	if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
++		goto done;
++
++	/* Get info for determining size */
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, 0, 0);
++
++	corerev = si_corerev(sih);
++	if (corerev >= 16) {
++		extcinfo = R_REG(sii->osh, &regs->extracoreinfo);
++		nb = ((extcinfo & SOCRAM_DEVRAMBANK_MASK) >> SOCRAM_DEVRAMBANK_SHIFT);
++		for (i = 0; i < nb; i++) {
++			bankidx = i | (SOCRAM_MEMTYPE_DEVRAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
++			W_REG(sii->osh, &regs->bankidx, bankidx);
++			bankinfo = R_REG(sii->osh, &regs->bankinfo);
++			if (bankinfo & SOCRAM_BANKINFO_DEVRAMREMAP_MASK) {
++				remap = TRUE;
++				break;
++			}
++		}
++	}
++
++	/* Return to previous state and core */
++	if (!wasup)
++		si_core_disable(sih, 0);
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++	return remap;
++}
++
++bool
++si_socdevram_pkg(si_t *sih)
++{
++	if (si_socdevram_size(sih) > 0)
++		return TRUE;
++	else
++		return FALSE;
++}
++
++uint32
++si_socdevram_size(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint origidx;
++	uint intr_val = 0;
++	uint32 memsize = 0;
++	sbsocramregs_t *regs;
++	bool wasup;
++	uint corerev;
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	/* Switch to SOCRAM core */
++	if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
++		goto done;
++
++	/* Get info for determining size */
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, 0, 0);
++
++	corerev = si_corerev(sih);
++	if (corerev >= 10) {
++		uint32 extcinfo;
++		uint8 nb;
++		uint8 i;
++
++		extcinfo = R_REG(sii->osh, &regs->extracoreinfo);
++		nb = (((extcinfo & SOCRAM_DEVRAMBANK_MASK) >> SOCRAM_DEVRAMBANK_SHIFT));
++		for (i = 0; i < nb; i++)
++			memsize += socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_DEVRAM);
++	}
++
++	/* Return to previous state and core */
++	if (!wasup)
++		si_core_disable(sih, 0);
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++
++	return memsize;
++}
++
++uint32
++si_socdevram_remap_size(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint origidx;
++	uint intr_val = 0;
++	uint32 memsize = 0, banksz;
++	sbsocramregs_t *regs;
++	bool wasup;
++	uint corerev;
++	uint32 extcinfo;
++	uint8 nb;
++	uint8 i;
++	uint32 bankidx, bankinfo;
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	/* Switch to SOCRAM core */
++	if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
++		goto done;
++
++	/* Get info for determining size */
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, 0, 0);
++
++	corerev = si_corerev(sih);
++	if (corerev >= 16) {
++		extcinfo = R_REG(sii->osh, &regs->extracoreinfo);
++		nb = (((extcinfo & SOCRAM_DEVRAMBANK_MASK) >> SOCRAM_DEVRAMBANK_SHIFT));
++
++		/*
++		 * FIX: A0 Issue: Max addressable is 512KB, instead 640KB
++		 * Only four banks are accessible to ARM
++		 */
++		if ((corerev == 16) && (nb == 5))
++			nb = 4;
++
++		for (i = 0; i < nb; i++) {
++			bankidx = i | (SOCRAM_MEMTYPE_DEVRAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
++			W_REG(sii->osh, &regs->bankidx, bankidx);
++			bankinfo = R_REG(sii->osh, &regs->bankinfo);
++			if (bankinfo & SOCRAM_BANKINFO_DEVRAMREMAP_MASK) {
++				banksz = socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_DEVRAM);
++				memsize += banksz;
++			} else {
++				/* Account only consecutive banks for now */
++				break;
++			}
++		}
++	}
++
++	/* Return to previous state and core */
++	if (!wasup)
++		si_core_disable(sih, 0);
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++
++	return memsize;
++}
++
++/** Return the RAM size of the SOCRAM core */
++uint32
++si_socram_size(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint origidx;
++	uint intr_val = 0;
++
++	sbsocramregs_t *regs;
++	bool wasup;
++	uint corerev;
++	uint32 coreinfo;
++	uint memsize = 0;
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	/* Switch to SOCRAM core */
++	if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
++		goto done;
++
++	/* Get info for determining size */
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, 0, 0);
++	corerev = si_corerev(sih);
++	coreinfo = R_REG(sii->osh, &regs->coreinfo);
++
++	/* Calculate size from coreinfo based on rev */
++	if (corerev == 0)
++		memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK));
++	else if (corerev < 3) {
++		memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK));
++		memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
++	} else if ((corerev <= 7) || (corerev == 12)) {
++		uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
++		uint bsz = (coreinfo & SRCI_SRBSZ_MASK);
++		uint lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT;
++		if (lss != 0)
++			nb --;
++		memsize = nb * (1 << (bsz + SR_BSZ_BASE));
++		if (lss != 0)
++			memsize += (1 << ((lss - 1) + SR_BSZ_BASE));
++	} else {
++		uint8 i;
++		uint nb;
++		/* length of SRAM Banks increased for corerev greater than 23 */
++		if (corerev >= 23) {
++			nb = (coreinfo & (SRCI_SRNB_MASK | SRCI_SRNB_MASK_EXT)) >> SRCI_SRNB_SHIFT;
++		} else {
++			nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
++		}
++		for (i = 0; i < nb; i++)
++			memsize += socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM);
++	}
++
++	/* Return to previous state and core */
++	if (!wasup)
++		si_core_disable(sih, 0);
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++
++	return memsize;
++}
++
++
++/** Return the TCM-RAM size of the ARMCR4 core. */
++uint32
++si_tcm_size(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint origidx;
++	uint intr_val = 0;
++	uint8 *regs;
++	bool wasup;
++	uint32 corecap;
++	uint memsize = 0;
++	uint32 nab = 0;
++	uint32 nbb = 0;
++	uint32 totb = 0;
++	uint32 bxinfo = 0;
++	uint32 idx = 0;
++	uint32 *arm_cap_reg;
++	uint32 *arm_bidx;
++	uint32 *arm_binfo;
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	/* Switch to CR4 core */
++	if (!(regs = si_setcore(sih, ARMCR4_CORE_ID, 0)))
++		goto done;
++
++	/* Get info for determining size. If in reset, come out of reset,
++	 * but remain in halt
++	 */
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, SICF_CPUHALT, SICF_CPUHALT);
++
++	arm_cap_reg = (uint32 *)(regs + SI_CR4_CAP);
++	corecap = R_REG(sii->osh, arm_cap_reg);
++
++	nab = (corecap & ARMCR4_TCBANB_MASK) >> ARMCR4_TCBANB_SHIFT;
++	nbb = (corecap & ARMCR4_TCBBNB_MASK) >> ARMCR4_TCBBNB_SHIFT;
++	totb = nab + nbb;
++
++	arm_bidx = (uint32 *)(regs + SI_CR4_BANKIDX);
++	arm_binfo = (uint32 *)(regs + SI_CR4_BANKINFO);
++	for (idx = 0; idx < totb; idx++) {
++		W_REG(sii->osh, arm_bidx, idx);
++
++		bxinfo = R_REG(sii->osh, arm_binfo);
++		memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * ARMCR4_BSZ_MULT;
++	}
++
++	/* Return to previous state and core */
++	if (!wasup)
++		si_core_disable(sih, 0);
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++
++	return memsize;
++}
++
++bool
++si_has_flops(si_t *sih)
++{
++	uint origidx, cr4_rev;
++
++	/* Find out CR4 core revision */
++	origidx = si_coreidx(sih);
++	if (si_setcore(sih, ARMCR4_CORE_ID, 0)) {
++		cr4_rev = si_corerev(sih);
++		si_setcoreidx(sih, origidx);
++
++		if (cr4_rev == 1 || cr4_rev >= 3)
++			return TRUE;
++	}
++	return FALSE;
++}
++
++uint32
++si_socram_srmem_size(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint origidx;
++	uint intr_val = 0;
++
++	sbsocramregs_t *regs;
++	bool wasup;
++	uint corerev;
++	uint32 coreinfo;
++	uint memsize = 0;
++
++	if ((CHIPID(sih->chip) == BCM4334_CHIP_ID) && (CHIPREV(sih->chiprev) < 2)) {
++		return (32 * 1024);
++	}
++
++	if (CHIPID(sih->chip) == BCM43430_CHIP_ID ||
++		CHIPID(sih->chip) == BCM43018_CHIP_ID) {
++		return (64 * 1024);
++	}
++
++	/* Block ints and save current core */
++	INTR_OFF(sii, intr_val);
++	origidx = si_coreidx(sih);
++
++	/* Switch to SOCRAM core */
++	if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
++		goto done;
++
++	/* Get info for determining size */
++	if (!(wasup = si_iscoreup(sih)))
++		si_core_reset(sih, 0, 0);
++	corerev = si_corerev(sih);
++	coreinfo = R_REG(sii->osh, &regs->coreinfo);
++
++	/* Calculate size from coreinfo based on rev */
++	if (corerev >= 16) {
++		uint8 i;
++		uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
++		for (i = 0; i < nb; i++) {
++			W_REG(sii->osh, &regs->bankidx, i);
++			if (R_REG(sii->osh, &regs->bankinfo) & SOCRAM_BANKINFO_RETNTRAM_MASK)
++				memsize += socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM);
++		}
++	}
++
++	/* Return to previous state and core */
++	if (!wasup)
++		si_core_disable(sih, 0);
++	si_setcoreidx(sih, origidx);
++
++done:
++	INTR_RESTORE(sii, intr_val);
++
++	return memsize;
++}
++
++
++#if !defined(_CFEZ_) || defined(CFG_WL)
++void
++si_btcgpiowar(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	uint origidx;
++	uint intr_val = 0;
++	chipcregs_t *cc;
++
++	/* Make sure that there is ChipCommon core present &&
++	 * UART_TX is strapped to 1
++	 */
++	if (!(sih->cccaps & CC_CAP_UARTGPIO))
++		return;
++
++	/* si_corereg cannot be used as we have to guarantee 8-bit read/writes */
++	INTR_OFF(sii, intr_val);
++
++	origidx = si_coreidx(sih);
++
++	cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
++	ASSERT(cc != NULL);
++
++	W_REG(sii->osh, &cc->uart0mcr, R_REG(sii->osh, &cc->uart0mcr) | 0x04);
++
++	/* restore the original index */
++	si_setcoreidx(sih, origidx);
++
++	INTR_RESTORE(sii, intr_val);
++}
++
++void
++si_chipcontrl_btshd0_4331(si_t *sih, bool on)
++{
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++	chipcregs_t *cc;
++	uint origidx;
++	uint32 val;
++	uint intr_val = 0;
++
++	INTR_OFF(sii, intr_val);
++
++	origidx = si_coreidx(sih);
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++
++	val = R_REG(sii->osh, &cc->chipcontrol);
++
++	/* bt_shd0 controls are same for 4331 chiprevs 0 and 1, packages 12x9 and 12x12 */
++	if (on) {
++		/* Enable bt_shd0 on gpio4: */
++		val |= (CCTRL4331_BT_SHD0_ON_GPIO4);
++		W_REG(sii->osh, &cc->chipcontrol, val);
++	} else {
++		val &= ~(CCTRL4331_BT_SHD0_ON_GPIO4);
++		W_REG(sii->osh, &cc->chipcontrol, val);
++	}
++
++	/* restore the original index */
++	si_setcoreidx(sih, origidx);
++
++	INTR_RESTORE(sii, intr_val);
++}
++
++void
++si_chipcontrl_restore(si_t *sih, uint32 val)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++	W_REG(sii->osh, &cc->chipcontrol, val);
++	si_setcoreidx(sih, origidx);
++}
++
++uint32
++si_chipcontrl_read(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++	uint32 val;
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return -1;
++	}
++	val = R_REG(sii->osh, &cc->chipcontrol);
++	si_setcoreidx(sih, origidx);
++	return val;
++}
++
++void
++si_chipcontrl_epa4331(si_t *sih, bool on)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++	uint32 val;
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++	val = R_REG(sii->osh, &cc->chipcontrol);
++
++	if (on) {
++		if (sih->chippkg == 9 || sih->chippkg == 0xb) {
++			val |= (CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
++			/* Ext PA Controls for 4331 12x9 Package */
++			W_REG(sii->osh, &cc->chipcontrol, val);
++		} else {
++			/* Ext PA Controls for 4331 12x12 Package */
++			if (CHIPREV(sih->chiprev) > 0) {
++				W_REG(sii->osh, &cc->chipcontrol, val |
++				      (CCTRL4331_EXTPA_EN) | (CCTRL4331_EXTPA_EN2));
++			} else {
++				W_REG(sii->osh, &cc->chipcontrol, val | (CCTRL4331_EXTPA_EN));
++			}
++		}
++	} else {
++		val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_EN2 | CCTRL4331_EXTPA_ON_GPIO2_5);
++		W_REG(sii->osh, &cc->chipcontrol, val);
++	}
++
++	si_setcoreidx(sih, origidx);
++}
++
++/** switch muxed pins, on: SROM, off: FEMCTRL. Called for a family of ac chips, not just 4360. */
++void
++si_chipcontrl_srom4360(si_t *sih, bool on)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++	uint32 val;
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++	val = R_REG(sii->osh, &cc->chipcontrol);
++
++	if (on) {
++		val &= ~(CCTRL4360_SECI_MODE |
++			CCTRL4360_BTSWCTRL_MODE |
++			CCTRL4360_EXTRA_FEMCTRL_MODE |
++			CCTRL4360_BT_LGCY_MODE |
++			CCTRL4360_CORE2FEMCTRL4_ON);
++
++		W_REG(sii->osh, &cc->chipcontrol, val);
++	} else {
++	}
++
++	si_setcoreidx(sih, origidx);
++}
++
++void
++si_clk_srom4365(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++	uint32 val;
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++	val = R_REG(sii->osh, &cc->clkdiv2);
++	W_REG(sii->osh, &cc->clkdiv2, ((val&~0xf) | 0x4));
++
++	si_setcoreidx(sih, origidx);
++}
++
++void
++si_d11rsdb_core1_alt_reg_clk_dis(si_t *sih)
++{
++#if defined(WLRSDB) && !defined(WLRSDB_DISABLED)
++	ai_d11rsdb_core1_alt_reg_clk_dis(sih);
++#endif /* defined(WLRSDB) && !defined(WLRSDB_DISABLED) */
++}
++
++void
++si_d11rsdb_core1_alt_reg_clk_en(si_t *sih)
++{
++#if defined(WLRSDB) && !defined(WLRSDB_DISABLED)
++	ai_d11rsdb_core1_alt_reg_clk_en(sih);
++#endif /* defined(WLRSDB) && !defined(WLRSDB_DISABLED) */
++}
++
++void
++si_chipcontrl_epa4331_wowl(si_t *sih, bool enter_wowl)
++{
++	si_info_t *sii;
++	chipcregs_t *cc;
++	uint origidx;
++	uint32 val;
++	bool sel_chip;
++
++	sel_chip = (CHIPID(sih->chip) == BCM4331_CHIP_ID) ||
++		(CHIPID(sih->chip) == BCM43431_CHIP_ID);
++	sel_chip &= ((sih->chippkg == 9 || sih->chippkg == 0xb));
++
++	if (!sel_chip)
++		return;
++
++	sii = SI_INFO(sih);
++	origidx = si_coreidx(sih);
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++
++	val = R_REG(sii->osh, &cc->chipcontrol);
++
++	if (enter_wowl) {
++		val |= CCTRL4331_EXTPA_EN;
++		W_REG(sii->osh, &cc->chipcontrol, val);
++	} else {
++		val |= (CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
++		W_REG(sii->osh, &cc->chipcontrol, val);
++	}
++	si_setcoreidx(sih, origidx);
++}
++#endif 
++
++uint
++si_pll_reset(si_t *sih)
++{
++	uint err = 0;
++
++	return (err);
++}
++
++/** Enable BT-COEX & Ex-PA for 4313 */
++void
++si_epa_4313war(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++
++	/* EPA Fix */
++	W_REG(sii->osh, &cc->gpiocontrol,
++	R_REG(sii->osh, &cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK);
++
++	si_setcoreidx(sih, origidx);
++}
++
++void
++si_clk_pmu_htavail_set(si_t *sih, bool set_clear)
++{
++}
++
++void
++si_pmu_avb_clk_set(si_t *sih, osl_t *osh, bool set_flag)
++{
++}
++
++/** Re-enable synth_pwrsw resource in min_res_mask for 4313 */
++void
++si_pmu_synth_pwrsw_4313_war(si_t *sih)
++{
++}
++
++/** WL/BT control for 4313 btcombo boards >= P250 */
++void
++si_btcombo_p250_4313_war(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++	W_REG(sii->osh, &cc->gpiocontrol,
++		R_REG(sii->osh, &cc->gpiocontrol) | GPIO_CTRL_5_6_EN_MASK);
++
++	W_REG(sii->osh, &cc->gpioouten,
++		R_REG(sii->osh, &cc->gpioouten) | GPIO_CTRL_5_6_EN_MASK);
++
++	si_setcoreidx(sih, origidx);
++}
++void
++si_btc_enable_chipcontrol(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++
++	/* BT fix */
++	W_REG(sii->osh, &cc->chipcontrol,
++		R_REG(sii->osh, &cc->chipcontrol) | CC_BTCOEX_EN_MASK);
++
++	si_setcoreidx(sih, origidx);
++}
++void
++si_btcombo_43228_war(si_t *sih)
++{
++	si_info_t *sii = SI_INFO(sih);
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++
++	if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) {
++		SI_ERROR(("%s: Failed to find CORE ID!\n", __FUNCTION__));
++		return;
++	}
++
++	W_REG(sii->osh, &cc->gpioouten, GPIO_CTRL_7_6_EN_MASK);
++	W_REG(sii->osh, &cc->gpioout, GPIO_OUT_7_EN_MASK);
++
++	si_setcoreidx(sih, origidx);
++}
++
++/** check if the device is removed */
++bool
++si_deviceremoved(si_t *sih)
++{
++	uint32 w;
++
++	switch (BUSTYPE(sih->bustype)) {
++	case PCI_BUS:
++		ASSERT(SI_INFO(sih)->osh != NULL);
++		w = OSL_PCI_READ_CONFIG(SI_INFO(sih)->osh, PCI_CFG_VID, sizeof(uint32));
++		if ((w & 0xFFFF) != VENDOR_BROADCOM)
++			return TRUE;
++		break;
++	}
++	return FALSE;
++}
++
++bool
++si_is_sprom_available(si_t *sih)
++{
++	if (sih->ccrev >= 31) {
++		si_info_t *sii;
++		uint origidx;
++		chipcregs_t *cc;
++		uint32 sromctrl;
++
++		if ((sih->cccaps & CC_CAP_SROM) == 0)
++			return FALSE;
++
++		sii = SI_INFO(sih);
++		origidx = sii->curidx;
++		cc = si_setcoreidx(sih, SI_CC_IDX);
++		ASSERT(cc);
++		sromctrl = R_REG(sii->osh, &cc->sromcontrol);
++		si_setcoreidx(sih, origidx);
++		return (sromctrl & SRC_PRESENT);
++	}
++
++	switch (CHIPID(sih->chip)) {
++	case BCM4312_CHIP_ID:
++		return ((sih->chipst & CST4312_SPROM_OTP_SEL_MASK) != CST4312_OTP_SEL);
++	case BCM4325_CHIP_ID:
++		return (sih->chipst & CST4325_SPROM_SEL) != 0;
++	case BCM4322_CHIP_ID:	case BCM43221_CHIP_ID:	case BCM43231_CHIP_ID:
++	case BCM43222_CHIP_ID:	case BCM43111_CHIP_ID:	case BCM43112_CHIP_ID:
++	case BCM4342_CHIP_ID: {
++		uint32 spromotp;
++		spromotp = (sih->chipst & CST4322_SPROM_OTP_SEL_MASK) >>
++		        CST4322_SPROM_OTP_SEL_SHIFT;
++		return (spromotp & CST4322_SPROM_PRESENT) != 0;
++	}
++	case BCM4329_CHIP_ID:
++		return (sih->chipst & CST4329_SPROM_SEL) != 0;
++	case BCM4315_CHIP_ID:
++		return (sih->chipst & CST4315_SPROM_SEL) != 0;
++	case BCM4319_CHIP_ID:
++		return (sih->chipst & CST4319_SPROM_SEL) != 0;
++	case BCM4336_CHIP_ID:
++	case BCM43362_CHIP_ID:
++		return (sih->chipst & CST4336_SPROM_PRESENT) != 0;
++	case BCM4330_CHIP_ID:
++		return (sih->chipst & CST4330_SPROM_PRESENT) != 0;
++	case BCM4313_CHIP_ID:
++		return (sih->chipst & CST4313_SPROM_PRESENT) != 0;
++	case BCM4331_CHIP_ID:
++	case BCM43431_CHIP_ID:
++		return (sih->chipst & CST4331_SPROM_PRESENT) != 0;
++	case BCM43239_CHIP_ID:
++		return ((sih->chipst & CST43239_SPROM_MASK) &&
++			!(sih->chipst & CST43239_SFLASH_MASK));
++	case BCM4324_CHIP_ID:
++	case BCM43242_CHIP_ID:
++		return ((sih->chipst & CST4324_SPROM_MASK) &&
++			!(sih->chipst & CST4324_SFLASH_MASK));
++	case BCM4335_CHIP_ID:
++	case BCM4345_CHIP_ID:
++	case BCM43454_CHIP_ID:
++		return ((sih->chipst & CST4335_SPROM_MASK) &&
++			!(sih->chipst & CST4335_SFLASH_MASK));
++	case BCM4349_CHIP_GRPID:
++		return (sih->chipst & CST4349_SPROM_PRESENT) != 0;
++		break;
++	case BCM4350_CHIP_ID:
++	case BCM4354_CHIP_ID:
++	case BCM4356_CHIP_ID:
++	case BCM43556_CHIP_ID:
++	case BCM43558_CHIP_ID:
++	case BCM43566_CHIP_ID:
++	case BCM43568_CHIP_ID:
++	case BCM43569_CHIP_ID:
++	case BCM43570_CHIP_ID:
++	case BCM4358_CHIP_ID:
++		return (sih->chipst & CST4350_SPROM_PRESENT) != 0;
++	CASE_BCM43602_CHIP:
++		return (sih->chipst & CST43602_SPROM_PRESENT) != 0;
++	case BCM43131_CHIP_ID:
++	case BCM43217_CHIP_ID:
++	case BCM43227_CHIP_ID:
++	case BCM43228_CHIP_ID:
++	case BCM43428_CHIP_ID:
++		return (sih->chipst & CST43228_OTP_PRESENT) != CST43228_OTP_PRESENT;
++	default:
++		return TRUE;
++	}
++}
++
++
++uint32 si_get_sromctl(si_t *sih)
++{
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++	uint32 sromctl;
++	osl_t *osh = si_osh(sih);
++
++	cc = si_setcoreidx(sih, SI_CC_IDX);
++	ASSERT((uintptr)cc);
++
++	sromctl = R_REG(osh, &cc->sromcontrol);
++
++	/* return to the original core */
++	si_setcoreidx(sih, origidx);
++	return sromctl;
++}
++
++int si_set_sromctl(si_t *sih, uint32 value)
++{
++	chipcregs_t *cc;
++	uint origidx = si_coreidx(sih);
++	osl_t *osh = si_osh(sih);
++	int ret = BCME_OK;
++
++	cc = si_setcoreidx(sih, SI_CC_IDX);
++	ASSERT((uintptr)cc);
++
++	/* get chipcommon rev */
++	if (si_corerev(sih) >= 32) {
++		/* SpromCtrl is only accessible if CoreCapabilities.SpromSupported and
++		 * SpromPresent is 1.
++		 */
++		if ((R_REG(osh, &cc->capabilities) & CC_CAP_SROM) != 0 &&
++		     (R_REG(osh, &cc->sromcontrol) & SRC_PRESENT)) {
++			W_REG(osh, &cc->sromcontrol, value);
++		} else {
++			ret = BCME_NODEVICE;
++		}
++	} else {
++		ret = BCME_UNSUPPORTED;
++	}
++
++	/* return to the original core */
++	si_setcoreidx(sih, origidx);
++
++	return ret;
++}
++
++uint
++si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val)
++{
++	uint origidx, intr_val = 0;
++	uint ret_val;
++	si_info_t *sii = SI_INFO(sih);
++	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
++
++	origidx = si_coreidx(sih);
++
++	INTR_OFF(sii, intr_val);
++	si_setcoreidx(sih, coreidx);
++
++	ret_val = si_wrapperreg(sih, offset, mask, val);
++
++	/* return to the original core */
++	si_setcoreidx(sih, origidx);
++	INTR_RESTORE(sii, intr_val);
++	return ret_val;
++}
++
++
++/* cleanup the timer from the host when ARM is been halted
++ * without a chance for ARM cleanup its resources
++ * If left not cleanup, Intr from a software timer can still
++ * request HT clk when ARM is halted.
++ */
++uint32
++si_pmu_res_req_timer_clr(si_t *sih)
++{
++	uint32 mask;
++
++	mask = PRRT_REQ_ACTIVE | PRRT_INTEN | PRRT_HT_REQ;
++	if (CHIPID(sih->chip) != BCM4328_CHIP_ID)
++		mask <<= 14;
++	/* clear mask bits */
++	pmu_corereg(sih, SI_CC_IDX, res_req_timer, mask, 0);
++	/* readback to ensure write completes */
++	return pmu_corereg(sih, SI_CC_IDX, res_req_timer, 0, 0);
++}
++
++/** turn on/off rfldo */
++void
++si_pmu_rfldo(si_t *sih, bool on)
++{
++}
++
++
++#ifdef SURVIVE_PERST_ENAB
++static uint32
++si_pcie_survive_perst(si_t *sih, uint32 mask, uint32 val)
++{
++	si_info_t *sii;
++
++	sii = SI_INFO(sih);
++
++	if (!PCIE(sii))
++		return (0);
++
++	return pcie_survive_perst(sii->pch, mask, val);
++}
++
++static void
++si_watchdog_reset(si_t *sih)
++{
++	uint32 i;
++
++	/* issue a watchdog reset */
++	pmu_corereg(sih, SI_CC_IDX, pmuwatchdog, 2, 2);
++	/* do busy wait for 20ms */
++	for (i = 0; i < 2000; i++) {
++		OSL_DELAY(10);
++	}
++}
++#endif /* SURVIVE_PERST_ENAB */
++
++void
++si_survive_perst_war(si_t *sih, bool reset, uint32 sperst_mask, uint32 sperst_val)
++{
++#ifdef SURVIVE_PERST_ENAB
++	if (BUSTYPE(sih->bustype) != PCI_BUS)
++		  return;
++
++	if ((CHIPID(sih->chip) != BCM4360_CHIP_ID && CHIPID(sih->chip) != BCM4352_CHIP_ID) ||
++	    (CHIPREV(sih->chiprev) >= 4))
++		return;
++
++	if (reset) {
++		si_info_t *sii = SI_INFO(sih);
++		uint32 bar0win, bar0win_after;
++
++		/* save the bar0win */
++		bar0win = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
++
++		si_watchdog_reset(sih);
++
++		bar0win_after = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
++		if (bar0win_after != bar0win) {
++			SI_ERROR(("%s: bar0win before %08x, bar0win after %08x\n",
++				__FUNCTION__, bar0win, bar0win_after));
++			OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32), bar0win);
++		}
++	}
++	if (sperst_mask) {
++		/* enable survive perst */
++		si_pcie_survive_perst(sih, sperst_mask, sperst_val);
++	}
++#endif /* SURVIVE_PERST_ENAB */
++}
++
++void
++si_pcie_ltr_war(si_t *sih)
++{
++}
++
++void
++si_pcie_hw_LTR_war(si_t *sih)
++{
++}
++
++void
++si_pciedev_reg_pm_clk_period(si_t *sih)
++{
++}
++
++void
++si_pciedev_crwlpciegen2(si_t *sih)
++{
++}
++
++void
++si_pcie_prep_D3(si_t *sih, bool enter_D3)
++{
++}
++
++
++
++void
++si_pll_sr_reinit(si_t *sih)
++{
++}
++
++void
++si_pll_closeloop(si_t *sih)
++{
++#if defined(SAVERESTORE)
++	uint32 data;
++
++	/* disable PLL open loop operation */
++	switch (CHIPID(sih->chip)) {
++#ifdef SAVERESTORE
++		case BCM43430_CHIP_ID:
++			if (SR_ENAB() && sr_isenab(sih)) {
++				/* read back the pll openloop state */
++				data = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL8, 0, 0);
++				/* current mode is openloop (possible POR) */
++				if ((data & PMU1_PLLCTL8_OPENLOOP_MASK) != 0) {
++					si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL8,
++						PMU1_PLLCTL8_OPENLOOP_MASK, 0);
++					si_pmu_pllupd(sih);
++				}
++			}
++			break;
++#endif /* SAVERESTORE */
++		default:
++			/* any unsupported chip bail */
++			return;
++	}
++#endif 
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/siutils_priv.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/siutils_priv.h
+new file mode 100644
+index 000000000..5e51a9079
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/siutils_priv.h
+@@ -0,0 +1,290 @@
++/*
++ * Include file private to the SOC Interconnect support files.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: siutils_priv.h 520760 2014-12-15 00:54:16Z $
++ */
++
++#ifndef	_siutils_priv_h_
++#define	_siutils_priv_h_
++
++#define	SI_ERROR(args)
++
++#define	SI_MSG(args)
++
++#ifdef BCMDBG_SI
++#define	SI_VMSG(args)	printf args
++#else
++#define	SI_VMSG(args)
++#endif
++
++#define	IS_SIM(chippkg)	((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
++
++typedef uint32 (*si_intrsoff_t)(void *intr_arg);
++typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg);
++typedef bool (*si_intrsenabled_t)(void *intr_arg);
++
++
++#define SI_GPIO_MAX		16
++
++typedef struct gci_gpio_item {
++	void			*arg;
++	uint8			gci_gpio;
++	uint8			status;
++	gci_gpio_handler_t	handler;
++	struct gci_gpio_item	*next;
++} gci_gpio_item_t;
++
++
++typedef struct si_cores_info {
++	void	*regs[SI_MAXCORES];	/* other regs va */
++
++	uint	coreid[SI_MAXCORES];	/* id of each core */
++	uint32	coresba[SI_MAXCORES];	/* backplane address of each core */
++	void	*regs2[SI_MAXCORES];	/* va of each core second register set (usbh20) */
++	uint32	coresba2[SI_MAXCORES];	/* address of each core second register set (usbh20) */
++	uint32	coresba_size[SI_MAXCORES]; /* backplane address space size */
++	uint32	coresba2_size[SI_MAXCORES]; /* second address space size */
++
++	void	*wrappers[SI_MAXCORES];	/* other cores wrapper va */
++	uint32	wrapba[SI_MAXCORES];	/* address of controlling wrapper */
++
++	void	*wrappers2[SI_MAXCORES];	/* other cores wrapper va */
++	uint32	wrapba2[SI_MAXCORES];	/* address of controlling wrapper */
++
++	uint32	cia[SI_MAXCORES];	/* erom cia entry for each core */
++	uint32	cib[SI_MAXCORES];	/* erom cia entry for each core */
++} si_cores_info_t;
++
++/* misc si info needed by some of the routines */
++typedef struct si_info {
++	struct si_pub pub;		/* back plane public state (must be first field) */
++
++	void	*osh;			/* osl os handle */
++	void	*sdh;			/* bcmsdh handle */
++
++	uint	dev_coreid;		/* the core provides driver functions */
++	void	*intr_arg;		/* interrupt callback function arg */
++	si_intrsoff_t intrsoff_fn;	/* turns chip interrupts off */
++	si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
++	si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
++
++	void *pch;			/* PCI/E core handle */
++
++	bool	memseg;			/* flag to toggle MEM_SEG register */
++
++	char *vars;
++	uint varsz;
++
++	void	*curmap;		/* current regs va */
++
++	uint	curidx;			/* current core index */
++	uint	numcores;		/* # discovered cores */
++
++	void	*curwrap;		/* current wrapper va */
++
++	uint32	oob_router;		/* oob router registers for axi */
++
++	void *cores_info;
++	gci_gpio_item_t	*gci_gpio_head;	/* gci gpio interrupts head */
++	uint	chipnew;		/* new chip number */
++	uint second_bar0win;		/* Backplane region */
++	uint	num_br;		/* # discovered bridges */
++	uint32	br_wrapba[SI_MAXBR];	/* address of bridge controlling wrapper */
++	uint32	xtalfreq;
++} si_info_t;
++
++
++#define	SI_INFO(sih)	((si_info_t *)(uintptr)sih)
++
++#define	GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
++		ISALIGNED((x), SI_CORE_SIZE))
++#define	GOODREGS(regs)	((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
++#define BADCOREADDR	0
++#define	GOODIDX(idx)	(((uint)idx) < SI_MAXCORES)
++#define	NOREV		-1		/* Invalid rev */
++
++#define PCI(si)		((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&	\
++			 ((si)->pub.buscoretype == PCI_CORE_ID))
++
++#define PCIE_GEN1(si)	((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&	\
++			 ((si)->pub.buscoretype == PCIE_CORE_ID))
++
++#define PCIE_GEN2(si)	((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&	\
++			 ((si)->pub.buscoretype == PCIE2_CORE_ID))
++
++#define PCIE(si)	(PCIE_GEN1(si) || PCIE_GEN2(si))
++
++#define PCMCIA(si)	((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE))
++
++/* Newer chips can access PCI/PCIE and CC core without requiring to change
++ * PCI BAR0 WIN
++ */
++#define SI_FAST(si) (PCIE(si) || (PCI(si) && ((si)->pub.buscorerev >= 13)))
++
++#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
++#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
++
++/*
++ * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
++ * after core switching to avoid invalid register accesss inside ISR.
++ */
++#define INTR_OFF(si, intr_val) \
++	if ((si)->intrsoff_fn && (cores_info)->coreid[(si)->curidx] == (si)->dev_coreid) {	\
++		intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
++#define INTR_RESTORE(si, intr_val) \
++	if ((si)->intrsrestore_fn && (cores_info)->coreid[(si)->curidx] == (si)->dev_coreid) {	\
++		(*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
++
++/* dynamic clock control defines */
++#define	LPOMINFREQ		25000		/* low power oscillator min */
++#define	LPOMAXFREQ		43000		/* low power oscillator max */
++#define	XTALMINFREQ		19800000	/* 20 MHz - 1% */
++#define	XTALMAXFREQ		20200000	/* 20 MHz + 1% */
++#define	PCIMINFREQ		25000000	/* 25 MHz */
++#define	PCIMAXFREQ		34000000	/* 33 MHz + fudge */
++
++#define	ILP_DIV_5MHZ		0		/* ILP = 5 MHz */
++#define	ILP_DIV_1MHZ		4		/* ILP = 1 MHz */
++
++/* Force fast clock for 4360b0 */
++#define PCI_FORCEHT(si)	\
++	(((PCIE_GEN1(si)) && (CHIPID(si->pub.chip) == BCM4311_CHIP_ID) && \
++	((CHIPREV(si->pub.chiprev) <= 1))) || \
++	((PCI(si) || PCIE_GEN1(si)) && (CHIPID(si->pub.chip) == BCM4321_CHIP_ID)) || \
++	(PCIE_GEN1(si) && (CHIPID(si->pub.chip) == BCM4716_CHIP_ID)) || \
++	(PCIE_GEN1(si) && (CHIPID(si->pub.chip) == BCM4748_CHIP_ID)))
++
++/* GPIO Based LED powersave defines */
++#define DEFAULT_GPIO_ONTIME	10		/* Default: 10% on */
++#define DEFAULT_GPIO_OFFTIME	90		/* Default: 10% on */
++
++#ifndef DEFAULT_GPIOTIMERVAL
++#define DEFAULT_GPIOTIMERVAL  ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
++#endif
++
++/* Silicon Backplane externs */
++extern void sb_scan(si_t *sih, void *regs, uint devid);
++extern uint sb_coreid(si_t *sih);
++extern uint sb_intflag(si_t *sih);
++extern uint sb_flag(si_t *sih);
++extern void sb_setint(si_t *sih, int siflag);
++extern uint sb_corevendor(si_t *sih);
++extern uint sb_corerev(si_t *sih);
++extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
++extern uint32 *sb_corereg_addr(si_t *sih, uint coreidx, uint regoff);
++extern bool sb_iscoreup(si_t *sih);
++extern void *sb_setcoreidx(si_t *sih, uint coreidx);
++extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val);
++extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
++extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val);
++extern void sb_commit(si_t *sih);
++extern uint32 sb_base(uint32 admatch);
++extern uint32 sb_size(uint32 admatch);
++extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
++extern void sb_core_disable(si_t *sih, uint32 bits);
++extern uint32 sb_addrspace(si_t *sih, uint asidx);
++extern uint32 sb_addrspacesize(si_t *sih, uint asidx);
++extern int sb_numaddrspaces(si_t *sih);
++
++extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx);
++
++extern bool sb_taclear(si_t *sih, bool details);
++
++#if defined(BCMDBG_PHYDUMP)
++extern void sb_dumpregs(si_t *sih, struct bcmstrbuf *b);
++#endif 
++
++/* Wake-on-wireless-LAN (WOWL) */
++extern bool sb_pci_pmecap(si_t *sih);
++struct osl_info;
++extern bool sb_pci_fastpmecap(struct osl_info *osh);
++extern bool sb_pci_pmeclr(si_t *sih);
++extern void sb_pci_pmeen(si_t *sih);
++extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset);
++
++/* AMBA Interconnect exported externs */
++extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
++                       void *sdh, char **vars, uint *varsz);
++extern si_t *ai_kattach(osl_t *osh);
++extern void ai_scan(si_t *sih, void *regs, uint devid);
++
++extern uint ai_flag(si_t *sih);
++extern uint ai_flag_alt(si_t *sih);
++extern void ai_setint(si_t *sih, int siflag);
++extern uint ai_coreidx(si_t *sih);
++extern uint ai_corevendor(si_t *sih);
++extern uint ai_corerev(si_t *sih);
++extern uint32 *ai_corereg_addr(si_t *sih, uint coreidx, uint regoff);
++extern bool ai_iscoreup(si_t *sih);
++extern void *ai_setcoreidx(si_t *sih, uint coreidx);
++extern void *ai_setcoreidx_2ndwrap(si_t *sih, uint coreidx);
++extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val);
++extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
++extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val);
++extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
++extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
++extern void ai_d11rsdb_core_reset(si_t *sih, uint32 bits,
++	uint32 resetbits, void *p, void *s);
++extern void ai_d11rsdb_core1_alt_reg_clk_en(si_t *sih);
++extern void ai_d11rsdb_core1_alt_reg_clk_dis(si_t *sih);
++
++extern void ai_core_disable(si_t *sih, uint32 bits);
++extern void ai_d11rsdb_core_disable(const si_info_t *sii, uint32 bits,
++	aidmp_t *pmacai, aidmp_t *smacai);
++extern int ai_numaddrspaces(si_t *sih);
++extern uint32 ai_addrspace(si_t *sih, uint asidx);
++extern uint32 ai_addrspacesize(si_t *sih, uint asidx);
++extern void ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size);
++extern uint ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
++extern void ai_enable_backplane_timeouts(si_t *sih);
++extern void ai_clear_backplane_to(si_t *sih);
++
++#if defined(BCMDBG_PHYDUMP)
++extern void ai_dumpregs(si_t *sih, struct bcmstrbuf *b);
++#endif 
++
++
++#define ub_scan(a, b, c) do {} while (0)
++#define ub_flag(a) (0)
++#define ub_setint(a, b) do {} while (0)
++#define ub_coreidx(a) (0)
++#define ub_corevendor(a) (0)
++#define ub_corerev(a) (0)
++#define ub_iscoreup(a) (0)
++#define ub_setcoreidx(a, b) (0)
++#define ub_core_cflags(a, b, c) (0)
++#define ub_core_cflags_wo(a, b, c) do {} while (0)
++#define ub_core_sflags(a, b, c) (0)
++#define ub_corereg(a, b, c, d, e) (0)
++#define ub_core_reset(a, b, c) do {} while (0)
++#define ub_core_disable(a, b) do {} while (0)
++#define ub_numaddrspaces(a) (0)
++#define ub_addrspace(a, b)  (0)
++#define ub_addrspacesize(a, b) (0)
++#define ub_view(a, b) do {} while (0)
++#define ub_dumpregs(a, b) do {} while (0)
++
++#endif	/* _siutils_priv_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/uamp_api.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/uamp_api.h
+new file mode 100644
+index 000000000..1fd8afa01
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/uamp_api.h
+@@ -0,0 +1,181 @@
++/*
++ *  Name:       uamp_api.h
++ *
++ *  Description: Universal AMP API
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: uamp_api.h 514727 2014-11-12 03:02:48Z $
++ *
++ */
++
++
++#ifndef UAMP_API_H
++#define UAMP_API_H
++
++
++#include "typedefs.h"
++
++
++/*****************************************************************************
++**  Constant and Type Definitions
++******************************************************************************
++*/
++
++#define BT_API
++
++/* Types. */
++typedef bool	BOOLEAN;
++typedef uint8	UINT8;
++typedef uint16	UINT16;
++
++
++/* UAMP identifiers */
++#define UAMP_ID_1   1
++#define UAMP_ID_2   2
++typedef UINT8 tUAMP_ID;
++
++/* UAMP event ids (used by UAMP_CBACK) */
++#define UAMP_EVT_RX_READY           0   /* Data from AMP controller is ready to be read */
++#define UAMP_EVT_CTLR_REMOVED       1   /* Controller removed */
++#define UAMP_EVT_CTLR_READY         2   /* Controller added/ready */
++typedef UINT8 tUAMP_EVT;
++
++
++/* UAMP Channels */
++#define UAMP_CH_HCI_CMD            0   /* HCI Command channel */
++#define UAMP_CH_HCI_EVT            1   /* HCI Event channel */
++#define UAMP_CH_HCI_DATA           2   /* HCI ACL Data channel */
++typedef UINT8 tUAMP_CH;
++
++/* tUAMP_EVT_DATA: union for event-specific data, used by UAMP_CBACK */
++typedef union {
++    tUAMP_CH channel;       /* UAMP_EVT_RX_READY: channel for which rx occured */
++} tUAMP_EVT_DATA;
++
++
++/*****************************************************************************
++**
++** Function:    UAMP_CBACK
++**
++** Description: Callback for events. Register callback using UAMP_Init.
++**
++** Parameters   amp_id:         AMP device identifier that generated the event
++**              amp_evt:        event id
++**              p_amp_evt_data: pointer to event-specific data
++**
++******************************************************************************
++*/
++typedef void (*tUAMP_CBACK)(tUAMP_ID amp_id, tUAMP_EVT amp_evt, tUAMP_EVT_DATA *p_amp_evt_data);
++
++/*****************************************************************************
++**  external function declarations
++******************************************************************************
++*/
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++/*****************************************************************************
++**
++** Function:    UAMP_Init
++**
++** Description: Initialize UAMP driver
++**
++** Parameters   p_cback:    Callback function for UAMP event notification
++**
++******************************************************************************
++*/
++BT_API BOOLEAN UAMP_Init(tUAMP_CBACK p_cback);
++
++
++/*****************************************************************************
++**
++** Function:    UAMP_Open
++**
++** Description: Open connection to local AMP device.
++**
++** Parameters   app_id: Application specific AMP identifer. This value
++**                      will be included in AMP messages sent to the
++**                      BTU task, to identify source of the message
++**
++******************************************************************************
++*/
++BT_API BOOLEAN UAMP_Open(tUAMP_ID amp_id);
++
++/*****************************************************************************
++**
++** Function:    UAMP_Close
++**
++** Description: Close connection to local AMP device.
++**
++** Parameters   app_id: Application specific AMP identifer.
++**
++******************************************************************************
++*/
++BT_API void UAMP_Close(tUAMP_ID amp_id);
++
++
++/*****************************************************************************
++**
++** Function:    UAMP_Write
++**
++** Description: Send buffer to AMP device. Frees GKI buffer when done.
++**
++**
++** Parameters:  app_id:     AMP identifer.
++**              p_buf:      pointer to buffer to write
++**              num_bytes:  number of bytes to write
++**              channel:    UAMP_CH_HCI_ACL, or UAMP_CH_HCI_CMD
++**
++** Returns:     number of bytes written
++**
++******************************************************************************
++*/
++BT_API UINT16 UAMP_Write(tUAMP_ID amp_id, UINT8 *p_buf, UINT16 num_bytes, tUAMP_CH channel);
++
++/*****************************************************************************
++**
++** Function:    UAMP_Read
++**
++** Description: Read incoming data from AMP. Call after receiving a
++**              UAMP_EVT_RX_READY callback event.
++**
++** Parameters:  app_id:     AMP identifer.
++**              p_buf:      pointer to buffer for holding incoming AMP data
++**              buf_size:   size of p_buf
++**              channel:    UAMP_CH_HCI_ACL, or UAMP_CH_HCI_EVT
++**
++** Returns:     number of bytes read
++**
++******************************************************************************
++*/
++BT_API UINT16 UAMP_Read(tUAMP_ID amp_id, UINT8 *p_buf, UINT16 buf_size, tUAMP_CH channel);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* UAMP_API_H */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_android.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_android.c
+new file mode 100644
+index 000000000..6cab3e113
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_android.c
+@@ -0,0 +1,2717 @@
++/*
++ * Linux cfg80211 driver - Android related functions
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_android.c 674374 2017-10-20 07:38:00Z $
++ */
++
++#include <linux/module.h>
++#include <linux/netdevice.h>
++#include <net/netlink.h>
++#ifdef CONFIG_COMPAT
++#include <linux/compat.h>
++#endif
++
++#include <wl_android.h>
++#include <wldev_common.h>
++#include <wlioctl.h>
++#include <wlioctl_utils.h>
++#include <bcmutils.h>
++#include <linux_osl.h>
++#include <dhd_dbg.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <proto/bcmip.h>
++#ifdef PNO_SUPPORT
++#include <dhd_pno.h>
++#endif
++#ifdef BCMSDIO
++#include <bcmsdbus.h>
++#endif
++#ifdef WL_CFG80211
++#include <wl_cfg80211.h>
++#endif
++#ifdef WL_NAN
++#include <wl_cfgnan.h>
++#endif /* WL_NAN */
++#ifdef DHDTCPACK_SUPPRESS
++#include <dhd_ip.h>
++#endif /* DHDTCPACK_SUPPRESS */
++
++/*
++ * Android private command strings, PLEASE define new private commands here
++ * so they can be updated easily in the future (if needed)
++ */
++
++#define CMD_START		"START"
++#define CMD_STOP		"STOP"
++#define	CMD_SCAN_ACTIVE		"SCAN-ACTIVE"
++#define	CMD_SCAN_PASSIVE	"SCAN-PASSIVE"
++#define CMD_RSSI		"RSSI"
++#define CMD_LINKSPEED		"LINKSPEED"
++#define CMD_RXFILTER_START	"RXFILTER-START"
++#define CMD_RXFILTER_STOP	"RXFILTER-STOP"
++#define CMD_RXFILTER_ADD	"RXFILTER-ADD"
++#define CMD_RXFILTER_REMOVE	"RXFILTER-REMOVE"
++#define CMD_BTCOEXSCAN_START	"BTCOEXSCAN-START"
++#define CMD_BTCOEXSCAN_STOP	"BTCOEXSCAN-STOP"
++#define CMD_BTCOEXMODE		"BTCOEXMODE"
++#define CMD_SETSUSPENDOPT	"SETSUSPENDOPT"
++#define CMD_SETSUSPENDMODE      "SETSUSPENDMODE"
++#define CMD_P2P_DEV_ADDR	"P2P_DEV_ADDR"
++#define CMD_SETFWPATH		"SETFWPATH"
++#define CMD_SETBAND		"SETBAND"
++#define CMD_GETBAND		"GETBAND"
++#define CMD_COUNTRY		"COUNTRY"
++#define CMD_P2P_SET_NOA		"P2P_SET_NOA"
++#if !defined WL_ENABLE_P2P_IF
++#define CMD_P2P_GET_NOA			"P2P_GET_NOA"
++#endif /* WL_ENABLE_P2P_IF */
++#define CMD_P2P_SD_OFFLOAD		"P2P_SD_"
++#define CMD_P2P_SET_PS		"P2P_SET_PS"
++#define CMD_P2P_ECSA		"P2P_ECSA"
++#define CMD_SET_AP_WPS_P2P_IE 		"SET_AP_WPS_P2P_IE"
++#define CMD_SETROAMMODE 	"SETROAMMODE"
++#define CMD_SETIBSSBEACONOUIDATA	"SETIBSSBEACONOUIDATA"
++#define CMD_MIRACAST		"MIRACAST"
++#ifdef WL_NAN
++#define CMD_NAN         "NAN_"
++#endif /* WL_NAN */
++#define CMD_COUNTRY_DELIMITER "/"
++#ifdef WL11ULB
++#define CMD_ULB_MODE "ULB_MODE"
++#define CMD_ULB_BW "ULB_BW"
++#endif /* WL11ULB */
++
++#if defined(WL_SUPPORT_AUTO_CHANNEL)
++#define CMD_GET_BEST_CHANNELS	"GET_BEST_CHANNELS"
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++
++#define CMD_80211_MODE    "MODE"  /* 802.11 mode a/b/g/n/ac */
++#define CMD_CHANSPEC      "CHANSPEC"
++#define CMD_DATARATE      "DATARATE"
++#define CMD_ASSOC_CLIENTS "ASSOCLIST"
++#define CMD_SET_CSA       "SETCSA"
++#ifdef WL_SUPPORT_AUTO_CHANNEL
++#define CMD_SET_HAPD_AUTO_CHANNEL	"HAPD_AUTO_CHANNEL"
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++#define CMD_KEEP_ALIVE		"KEEPALIVE"
++
++/* CCX Private Commands */
++
++#ifdef PNO_SUPPORT
++#define CMD_PNOSSIDCLR_SET	"PNOSSIDCLR"
++#define CMD_PNOSETUP_SET	"PNOSETUP "
++#define CMD_PNOENABLE_SET	"PNOFORCE"
++#define CMD_PNODEBUG_SET	"PNODEBUG"
++#define CMD_WLS_BATCHING	"WLS_BATCHING"
++#endif /* PNO_SUPPORT */
++
++#define CMD_OKC_SET_PMK		"SET_PMK"
++#define CMD_OKC_ENABLE		"OKC_ENABLE"
++
++#define	CMD_HAPD_MAC_FILTER	"HAPD_MAC_FILTER"
++
++#ifdef WLFBT
++#define CMD_GET_FTKEY      "GET_FTKEY"
++#endif
++
++
++#define CMD_ROAM_OFFLOAD			"SETROAMOFFLOAD"
++#define CMD_ROAM_OFFLOAD_APLIST			"SETROAMOFFLAPLIST"
++#define CMD_INTERFACE_CREATE			"INTERFACE_CREATE"
++#define CMD_INTERFACE_DELETE			"INTERFACE_DELETE"
++
++#ifdef P2PRESP_WFDIE_SRC
++#define CMD_P2P_SET_WFDIE_RESP      "P2P_SET_WFDIE_RESP"
++#define CMD_P2P_GET_WFDIE_RESP      "P2P_GET_WFDIE_RESP"
++#endif /* P2PRESP_WFDIE_SRC */
++
++#define CMD_DFS_AP_MOVE			"DFS_AP_MOVE"
++#define CMD_WBTEXT_ENABLE		"WBTEXT_ENABLE"
++#define CMD_WBTEXT_PROFILE_CONFIG	"WBTEXT_PROFILE_CONFIG"
++#define CMD_WBTEXT_WEIGHT_CONFIG	"WBTEXT_WEIGHT_CONFIG"
++#define CMD_WBTEXT_TABLE_CONFIG		"WBTEXT_TABLE_CONFIG"
++#define CMD_WBTEXT_DELTA_CONFIG		"WBTEXT_DELTA_CONFIG"
++
++#ifdef WLWFDS
++#define CMD_ADD_WFDS_HASH	"ADD_WFDS_HASH"
++#define CMD_DEL_WFDS_HASH	"DEL_WFDS_HASH"
++#endif /* WLWFDS */
++
++#ifdef SET_RPS_CPUS
++#define CMD_RPSMODE  "RPSMODE"
++#endif /* SET_RPS_CPUS */
++
++#ifdef BT_WIFI_HANDOVER
++#define CMD_TBOW_TEARDOWN "TBOW_TEARDOWN"
++#endif /* BT_WIFI_HANDOVER */
++
++/* miracast related definition */
++#define MIRACAST_MODE_OFF	0
++#define MIRACAST_MODE_SOURCE	1
++#define MIRACAST_MODE_SINK	2
++
++#ifndef MIRACAST_AMPDU_SIZE
++#define MIRACAST_AMPDU_SIZE	8
++#endif
++
++#ifndef MIRACAST_MCHAN_ALGO
++#define MIRACAST_MCHAN_ALGO     1
++#endif
++
++#ifndef MIRACAST_MCHAN_BW
++#define MIRACAST_MCHAN_BW       25
++#endif
++
++#ifdef CONNECTION_STATISTICS
++#define CMD_GET_CONNECTION_STATS	"GET_CONNECTION_STATS"
++
++struct connection_stats {
++	u32 txframe;
++	u32 txbyte;
++	u32 txerror;
++	u32 rxframe;
++	u32 rxbyte;
++	u32 txfail;
++	u32 txretry;
++	u32 txretrie;
++	u32 txrts;
++	u32 txnocts;
++	u32 txexptime;
++	u32 txrate;
++	u8	chan_idle;
++};
++#endif /* CONNECTION_STATISTICS */
++
++static LIST_HEAD(miracast_resume_list);
++static u8 miracast_cur_mode;
++
++struct io_cfg {
++	s8 *iovar;
++	s32 param;
++	u32 ioctl;
++	void *arg;
++	u32 len;
++	struct list_head list;
++};
++
++#if defined(BCMFW_ROAM_ENABLE)
++#define CMD_SET_ROAMPREF	"SET_ROAMPREF"
++
++#define MAX_NUM_SUITES		10
++#define WIDTH_AKM_SUITE		8
++#define JOIN_PREF_RSSI_LEN		0x02
++#define JOIN_PREF_RSSI_SIZE		4	/* RSSI pref header size in bytes */
++#define JOIN_PREF_WPA_HDR_SIZE		4 /* WPA pref header size in bytes */
++#define JOIN_PREF_WPA_TUPLE_SIZE	12	/* Tuple size in bytes */
++#define JOIN_PREF_MAX_WPA_TUPLES	16
++#define MAX_BUF_SIZE		(JOIN_PREF_RSSI_SIZE + JOIN_PREF_WPA_HDR_SIZE +	\
++				           (JOIN_PREF_WPA_TUPLE_SIZE * JOIN_PREF_MAX_WPA_TUPLES))
++#endif /* BCMFW_ROAM_ENABLE */
++
++
++
++/**
++ * Extern function declarations (TODO: move them to dhd_linux.h)
++ */
++int dhd_net_bus_devreset(struct net_device *dev, uint8 flag);
++int dhd_dev_init_ioctl(struct net_device *dev);
++#ifdef WL_CFG80211
++int wl_cfg80211_get_p2p_dev_addr(struct net_device *net, struct ether_addr *p2pdev_addr);
++int wl_cfg80211_set_btcoex_dhcp(struct net_device *dev, dhd_pub_t *dhd, char *command);
++#else
++int wl_cfg80211_get_p2p_dev_addr(struct net_device *net, struct ether_addr *p2pdev_addr)
++{ return 0; }
++int wl_cfg80211_set_p2p_noa(struct net_device *net, char* buf, int len)
++{ return 0; }
++int wl_cfg80211_get_p2p_noa(struct net_device *net, char* buf, int len)
++{ return 0; }
++int wl_cfg80211_set_p2p_ps(struct net_device *net, char* buf, int len)
++{ return 0; }
++int wl_cfg80211_set_p2p_ecsa(struct net_device *net, char* buf, int len)
++{ return 0; }
++#endif /* WK_CFG80211 */
++
++
++#ifdef ENABLE_4335BT_WAR
++extern int bcm_bt_lock(int cookie);
++extern void bcm_bt_unlock(int cookie);
++static int lock_cookie_wifi = 'W' | 'i'<<8 | 'F'<<16 | 'i'<<24;	/* cookie is "WiFi" */
++#endif /* ENABLE_4335BT_WAR */
++
++extern bool ap_fw_loaded;
++extern char iface_name[IFNAMSIZ];
++
++/**
++ * Local (static) functions and variables
++ */
++
++/* Initialize g_wifi_on to 1 so dhd_bus_start will be called for the first
++ * time (only) in dhd_open, subsequential wifi on will be handled by
++ * wl_android_wifi_on
++ */
++static int g_wifi_on = TRUE;
++
++/**
++ * Local (static) function definitions
++ */
++
++#ifdef WLWFDS
++static int wl_android_set_wfds_hash(
++	struct net_device *dev, char *command, int total_len, bool enable)
++{
++	int error = 0;
++	wl_p2p_wfds_hash_t *wfds_hash = NULL;
++	char *smbuf = NULL;
++	smbuf = kmalloc(WLC_IOCTL_MAXLEN, GFP_KERNEL);
++
++	if (smbuf == NULL) {
++		DHD_ERROR(("%s: failed to allocated memory %d bytes\n",
++			__FUNCTION__, WLC_IOCTL_MAXLEN));
++		return -ENOMEM;
++	}
++
++	if (enable) {
++		wfds_hash = (wl_p2p_wfds_hash_t *)(command + strlen(CMD_ADD_WFDS_HASH) + 1);
++		error = wldev_iovar_setbuf(dev, "p2p_add_wfds_hash", wfds_hash,
++			sizeof(wl_p2p_wfds_hash_t), smbuf, WLC_IOCTL_MAXLEN, NULL);
++	}
++	else {
++		wfds_hash = (wl_p2p_wfds_hash_t *)(command + strlen(CMD_DEL_WFDS_HASH) + 1);
++		error = wldev_iovar_setbuf(dev, "p2p_del_wfds_hash", wfds_hash,
++			sizeof(wl_p2p_wfds_hash_t), smbuf, WLC_IOCTL_MAXLEN, NULL);
++	}
++
++	if (error) {
++		DHD_ERROR(("%s: failed to %s, error=%d\n", __FUNCTION__, command, error));
++	}
++
++	if (smbuf)
++		kfree(smbuf);
++	return error;
++}
++#endif /* WLWFDS */
++
++static int wl_android_get_link_speed(struct net_device *net, char *command, int total_len)
++{
++	int link_speed;
++	int bytes_written;
++	int error;
++
++	error = wldev_get_link_speed(net, &link_speed);
++	if (error) {
++		DHD_ERROR(("Get linkspeed failed \n"));
++		return -1;
++	}
++
++	/* Convert Kbps to Android Mbps */
++	link_speed = link_speed / 1000;
++	bytes_written = snprintf(command, total_len, "LinkSpeed %d", link_speed);
++	DHD_INFO(("%s: command result is %s\n", __FUNCTION__, command));
++	return bytes_written;
++}
++
++static int wl_android_get_rssi(struct net_device *net, char *command, int total_len)
++{
++	wlc_ssid_t ssid = {0};
++	int bytes_written = 0;
++	int error = 0;
++	scb_val_t scbval;
++	char *delim = NULL;
++
++	delim = strchr(command, ' ');
++	/* For Ap mode rssi command would be
++	 * driver rssi <sta_mac_addr>
++	 * for STA/GC mode
++	 * driver rssi
++	*/
++	if (delim) {
++		/* Ap/GO mode
++		* driver rssi <sta_mac_addr>
++		*/
++		DHD_TRACE(("%s: cmd:%s\n", __FUNCTION__, delim));
++		/* skip space from delim after finding char */
++		delim++;
++		if (!(bcm_ether_atoe((delim), &scbval.ea)))
++		{
++			DHD_ERROR(("%s:address err\n", __FUNCTION__));
++			return -1;
++		}
++	        scbval.val = htod32(0);
++		DHD_TRACE(("%s: address:"MACDBG, __FUNCTION__, MAC2STRDBG(scbval.ea.octet)));
++	}
++	else {
++		/* STA/GC mode */
++		memset(&scbval, 0, sizeof(scb_val_t));
++	}
++
++	error = wldev_get_rssi(net, &scbval);
++	if (error)
++		return -1;
++
++	error = wldev_get_ssid(net, &ssid);
++	if (error)
++		return -1;
++	if ((ssid.SSID_len == 0) || (ssid.SSID_len > DOT11_MAX_SSID_LEN)) {
++		DHD_ERROR(("%s: wldev_get_ssid failed\n", __FUNCTION__));
++	} else {
++		memcpy(command, ssid.SSID, ssid.SSID_len);
++		bytes_written = ssid.SSID_len;
++	}
++	bytes_written += snprintf(&command[bytes_written], total_len, " rssi %d", scbval.val);
++	DHD_TRACE(("%s: command result is %s (%d)\n", __FUNCTION__, command, bytes_written));
++	return bytes_written;
++}
++
++static int wl_android_set_suspendopt(struct net_device *dev, char *command, int total_len)
++{
++	int suspend_flag;
++	int ret_now;
++	int ret = 0;
++
++		suspend_flag = *(command + strlen(CMD_SETSUSPENDOPT) + 1) - '0';
++
++		if (suspend_flag != 0)
++			suspend_flag = 1;
++		ret_now = net_os_set_suspend_disable(dev, suspend_flag);
++
++		if (ret_now != suspend_flag) {
++			if (!(ret = net_os_set_suspend(dev, ret_now, 1)))
++				DHD_INFO(("%s: Suspend Flag %d -> %d\n",
++					__FUNCTION__, ret_now, suspend_flag));
++			else
++				DHD_ERROR(("%s: failed %d\n", __FUNCTION__, ret));
++		}
++	return ret;
++}
++
++static int wl_android_set_suspendmode(struct net_device *dev, char *command, int total_len)
++{
++	int ret = 0;
++
++#if !defined(CONFIG_HAS_EARLYSUSPEND) || !defined(DHD_USE_EARLYSUSPEND)
++	int suspend_flag;
++
++	suspend_flag = *(command + strlen(CMD_SETSUSPENDMODE) + 1) - '0';
++	if (suspend_flag != 0)
++		suspend_flag = 1;
++
++	if (!(ret = net_os_set_suspend(dev, suspend_flag, 0)))
++		DHD_INFO(("%s: Suspend Mode %d\n", __FUNCTION__, suspend_flag));
++	else
++		DHD_ERROR(("%s: failed %d\n", __FUNCTION__, ret));
++#endif
++
++	return ret;
++}
++
++int wl_android_get_80211_mode(struct net_device *dev, char *command, int total_len)
++{
++	uint8 mode[4];
++	int  error = 0;
++	int bytes_written = 0;
++
++	error = wldev_get_mode(dev, mode);
++	if (error)
++		return -1;
++
++	DHD_INFO(("%s: mode:%s\n", __FUNCTION__, mode));
++	bytes_written = snprintf(command, total_len, "%s %s", CMD_80211_MODE, mode);
++	DHD_INFO(("%s: command:%s EXIT\n", __FUNCTION__, command));
++	return bytes_written;
++
++}
++
++extern chanspec_t
++wl_chspec_driver_to_host(chanspec_t chanspec);
++int wl_android_get_chanspec(struct net_device *dev, char *command, int total_len)
++{
++	int error = 0;
++	int bytes_written = 0;
++	int chsp = {0};
++	uint16 band = 0;
++	uint16 bw = 0;
++	uint16 channel = 0;
++	u32 sb = 0;
++	chanspec_t chanspec;
++
++	/* command is
++	 * driver chanspec
++	 */
++	error = wldev_iovar_getint(dev, "chanspec", &chsp);
++	if (error)
++		return -1;
++
++	chanspec = wl_chspec_driver_to_host(chsp);
++	DHD_INFO(("%s:return value of chanspec:%x\n", __FUNCTION__, chanspec));
++
++	channel = chanspec & WL_CHANSPEC_CHAN_MASK;
++	band = chanspec & WL_CHANSPEC_BAND_MASK;
++	bw = chanspec & WL_CHANSPEC_BW_MASK;
++
++	DHD_INFO(("%s:channel:%d band:%d bandwidth:%d\n", __FUNCTION__, channel, band, bw));
++
++	if (bw == WL_CHANSPEC_BW_80)
++		bw = WL_CH_BANDWIDTH_80MHZ;
++	else if (bw == WL_CHANSPEC_BW_40)
++		bw = WL_CH_BANDWIDTH_40MHZ;
++	else if	(bw == WL_CHANSPEC_BW_20)
++		bw = WL_CH_BANDWIDTH_20MHZ;
++	else
++		bw = WL_CH_BANDWIDTH_20MHZ;
++
++	if (bw == WL_CH_BANDWIDTH_40MHZ) {
++		if (CHSPEC_SB_UPPER(chanspec)) {
++			channel += CH_10MHZ_APART;
++		} else {
++			channel -= CH_10MHZ_APART;
++		}
++	}
++	else if (bw == WL_CH_BANDWIDTH_80MHZ) {
++		sb = chanspec & WL_CHANSPEC_CTL_SB_MASK;
++		if (sb == WL_CHANSPEC_CTL_SB_LL) {
++			channel -= (CH_10MHZ_APART + CH_20MHZ_APART);
++		} else if (sb == WL_CHANSPEC_CTL_SB_LU) {
++			channel -= CH_10MHZ_APART;
++		} else if (sb == WL_CHANSPEC_CTL_SB_UL) {
++			channel += CH_10MHZ_APART;
++		} else {
++			/* WL_CHANSPEC_CTL_SB_UU */
++			channel += (CH_10MHZ_APART + CH_20MHZ_APART);
++		}
++	}
++	bytes_written = snprintf(command, total_len, "%s channel %d band %s bw %d", CMD_CHANSPEC,
++		channel, band == WL_CHANSPEC_BAND_5G ? "5G":"2G", bw);
++
++	DHD_INFO(("%s: command:%s EXIT\n", __FUNCTION__, command));
++	return bytes_written;
++
++}
++
++/* returns current datarate datarate returned from firmware are in 500kbps */
++int wl_android_get_datarate(struct net_device *dev, char *command, int total_len)
++{
++	int  error = 0;
++	int datarate = 0;
++	int bytes_written = 0;
++
++	error = wldev_get_datarate(dev, &datarate);
++	if (error)
++		return -1;
++
++	DHD_INFO(("%s:datarate:%d\n", __FUNCTION__, datarate));
++
++	bytes_written = snprintf(command, total_len, "%s %d", CMD_DATARATE, (datarate/2));
++	return bytes_written;
++}
++int wl_android_get_assoclist(struct net_device *dev, char *command, int total_len)
++{
++	int  error = 0;
++	int bytes_written = 0;
++	uint i;
++	char mac_buf[MAX_NUM_OF_ASSOCLIST *
++		sizeof(struct ether_addr) + sizeof(uint)] = {0};
++	struct maclist *assoc_maclist = (struct maclist *)mac_buf;
++
++	DHD_TRACE(("%s: ENTER\n", __FUNCTION__));
++
++	assoc_maclist->count = htod32(MAX_NUM_OF_ASSOCLIST);
++
++	error = wldev_ioctl(dev, WLC_GET_ASSOCLIST, assoc_maclist, sizeof(mac_buf), false);
++	if (error)
++		return -1;
++
++	assoc_maclist->count = dtoh32(assoc_maclist->count);
++	bytes_written = snprintf(command, total_len, "%s listcount: %d Stations:",
++		CMD_ASSOC_CLIENTS, assoc_maclist->count);
++
++	for (i = 0; i < assoc_maclist->count; i++) {
++		bytes_written += snprintf(command + bytes_written, total_len, " " MACDBG,
++			MAC2STRDBG(assoc_maclist->ea[i].octet));
++	}
++	return bytes_written;
++
++}
++extern chanspec_t
++wl_chspec_host_to_driver(chanspec_t chanspec);
++static int wl_android_set_csa(struct net_device *dev, char *command, int total_len)
++{
++	int error = 0;
++	char smbuf[WLC_IOCTL_SMLEN];
++	wl_chan_switch_t csa_arg;
++	u32 chnsp = 0;
++	int err = 0;
++
++	DHD_INFO(("%s: command:%s\n", __FUNCTION__, command));
++
++	command = (command + strlen(CMD_SET_CSA));
++	/* Order is mode, count channel */
++	if (!*++command) {
++		DHD_ERROR(("%s:error missing arguments\n", __FUNCTION__));
++		return -1;
++	}
++	csa_arg.mode = bcm_atoi(command);
++
++	if (csa_arg.mode != 0 && csa_arg.mode != 1) {
++		DHD_ERROR(("Invalid mode\n"));
++		return -1;
++	}
++
++	if (!*++command) {
++		DHD_ERROR(("%s:error missing count\n", __FUNCTION__));
++		return -1;
++	}
++	command++;
++	csa_arg.count = bcm_atoi(command);
++
++	csa_arg.reg = 0;
++	csa_arg.chspec = 0;
++	command += 2;
++	if (!*command) {
++		DHD_ERROR(("%s:error missing channel\n", __FUNCTION__));
++		return -1;
++	}
++
++	chnsp = wf_chspec_aton(command);
++	if (chnsp == 0)	{
++		DHD_ERROR(("%s:chsp is not correct\n", __FUNCTION__));
++		return -1;
++	}
++	chnsp = wl_chspec_host_to_driver(chnsp);
++	csa_arg.chspec = chnsp;
++
++	if (chnsp & WL_CHANSPEC_BAND_5G) {
++		u32 chanspec = chnsp;
++		err = wldev_iovar_getint(dev, "per_chan_info", &chanspec);
++		if (!err) {
++			if ((chanspec & WL_CHAN_RADAR) || (chanspec & WL_CHAN_PASSIVE)) {
++				DHD_ERROR(("Channel is radar sensitive\n"));
++				return -1;
++			}
++			if (chanspec == 0) {
++				DHD_ERROR(("Invalid hw channel\n"));
++				return -1;
++			}
++		} else  {
++			DHD_ERROR(("does not support per_chan_info\n"));
++			return -1;
++		}
++		DHD_INFO(("non radar sensitivity\n"));
++	}
++	error = wldev_iovar_setbuf(dev, "csa", &csa_arg, sizeof(csa_arg),
++		smbuf, sizeof(smbuf), NULL);
++	if (error) {
++		DHD_ERROR(("%s:set csa failed:%d\n", __FUNCTION__, error));
++		return -1;
++	}
++	return 0;
++}
++static int wl_android_get_band(struct net_device *dev, char *command, int total_len)
++{
++	uint band;
++	int bytes_written;
++	int error;
++
++	error = wldev_get_band(dev, &band);
++	if (error)
++		return -1;
++	bytes_written = snprintf(command, total_len, "Band %d", band);
++	return bytes_written;
++}
++
++static int wl_android_wbtext(struct net_device *dev, char *command, int total_len)
++{
++	int error = 0;
++	int data;
++
++	sscanf(command+sizeof("WBTEXT_ENABLE"), "%d", &data);
++
++	if (data)
++		data = WL_BSSTRANS_POLICY_PRODUCT;
++
++	error = wldev_iovar_setint(dev, "wnm_bsstrans_resp", data);
++	if (error) {
++		DHD_ERROR(("%s: Failed to set wnm_bsstrans_resp error = %d\n",
++			__FUNCTION__, error));
++	}
++	return error;
++}
++
++#ifdef PNO_SUPPORT
++#define PNO_PARAM_SIZE 50
++#define VALUE_SIZE 50
++#define LIMIT_STR_FMT  ("%50s %50s")
++static int
++wls_parse_batching_cmd(struct net_device *dev, char *command, int total_len)
++{
++	int err = BCME_OK;
++	uint i, tokens;
++	char *pos, *pos2, *token, *token2, *delim;
++	char param[PNO_PARAM_SIZE], value[VALUE_SIZE];
++	struct dhd_pno_batch_params batch_params;
++	DHD_PNO(("%s: command=%s, len=%d\n", __FUNCTION__, command, total_len));
++	if (total_len < strlen(CMD_WLS_BATCHING)) {
++		DHD_ERROR(("%s argument=%d less min size\n", __FUNCTION__, total_len));
++		err = BCME_ERROR;
++		goto exit;
++	}
++	pos = command + strlen(CMD_WLS_BATCHING) + 1;
++	memset(&batch_params, 0, sizeof(struct dhd_pno_batch_params));
++
++	if (!strncmp(pos, PNO_BATCHING_SET, strlen(PNO_BATCHING_SET))) {
++		pos += strlen(PNO_BATCHING_SET) + 1;
++		while ((token = strsep(&pos, PNO_PARAMS_DELIMETER)) != NULL) {
++			memset(param, 0, sizeof(param));
++			memset(value, 0, sizeof(value));
++			if (token == NULL || !*token)
++				break;
++			if (*token == '\0')
++				continue;
++			delim = strchr(token, PNO_PARAM_VALUE_DELLIMETER);
++			if (delim != NULL)
++				*delim = ' ';
++
++			tokens = sscanf(token, LIMIT_STR_FMT, param, value);
++			if (!strncmp(param, PNO_PARAM_SCANFREQ, strlen(PNO_PARAM_SCANFREQ))) {
++				batch_params.scan_fr = simple_strtol(value, NULL, 0);
++				DHD_PNO(("scan_freq : %d\n", batch_params.scan_fr));
++			} else if (!strncmp(param, PNO_PARAM_BESTN, strlen(PNO_PARAM_BESTN))) {
++				batch_params.bestn = simple_strtol(value, NULL, 0);
++				DHD_PNO(("bestn : %d\n", batch_params.bestn));
++			} else if (!strncmp(param, PNO_PARAM_MSCAN, strlen(PNO_PARAM_MSCAN))) {
++				batch_params.mscan = simple_strtol(value, NULL, 0);
++				DHD_PNO(("mscan : %d\n", batch_params.mscan));
++			} else if (!strncmp(param, PNO_PARAM_CHANNEL, strlen(PNO_PARAM_CHANNEL))) {
++				i = 0;
++				pos2 = value;
++				tokens = sscanf(value, "<%s>", value);
++				if (tokens != 1) {
++					err = BCME_ERROR;
++					DHD_ERROR(("%s : invalid format for channel"
++					" <> params\n", __FUNCTION__));
++					goto exit;
++				}
++					while ((token2 = strsep(&pos2,
++					PNO_PARAM_CHANNEL_DELIMETER)) != NULL) {
++					if (token2 == NULL || !*token2)
++						break;
++					if (*token2 == '\0')
++						continue;
++					if (*token2 == 'A' || *token2 == 'B') {
++						batch_params.band = (*token2 == 'A')?
++							WLC_BAND_5G : WLC_BAND_2G;
++						DHD_PNO(("band : %s\n",
++							(*token2 == 'A')? "A" : "B"));
++					} else {
++						batch_params.chan_list[i++] =
++						simple_strtol(token2, NULL, 0);
++						batch_params.nchan++;
++						DHD_PNO(("channel :%d\n",
++						batch_params.chan_list[i-1]));
++					}
++				 }
++			} else if (!strncmp(param, PNO_PARAM_RTT, strlen(PNO_PARAM_RTT))) {
++				batch_params.rtt = simple_strtol(value, NULL, 0);
++				DHD_PNO(("rtt : %d\n", batch_params.rtt));
++			} else {
++				DHD_ERROR(("%s : unknown param: %s\n", __FUNCTION__, param));
++				err = BCME_ERROR;
++				goto exit;
++			}
++		}
++		err = dhd_dev_pno_set_for_batch(dev, &batch_params);
++		if (err < 0) {
++			DHD_ERROR(("failed to configure batch scan\n"));
++		} else {
++			memset(command, 0, total_len);
++			err = snprintf(command, total_len, "%d", err);
++		}
++	} else if (!strncmp(pos, PNO_BATCHING_GET, strlen(PNO_BATCHING_GET))) {
++		err = dhd_dev_pno_get_for_batch(dev, command, total_len);
++		if (err < 0) {
++			DHD_ERROR(("failed to getting batching results\n"));
++		} else {
++			err = strlen(command);
++		}
++	} else if (!strncmp(pos, PNO_BATCHING_STOP, strlen(PNO_BATCHING_STOP))) {
++		err = dhd_dev_pno_stop_for_batch(dev);
++		if (err < 0) {
++			DHD_ERROR(("failed to stop batching scan\n"));
++		} else {
++			memset(command, 0, total_len);
++			err = snprintf(command, total_len, "OK");
++		}
++	} else {
++		DHD_ERROR(("%s : unknown command\n", __FUNCTION__));
++		err = BCME_ERROR;
++		goto exit;
++	}
++exit:
++	return err;
++}
++#if !defined(WL_SCHED_SCAN) && defined(WL_WIRELESS_EXT)
++static int wl_android_set_pno_setup(struct net_device *dev, char *command, int total_len)
++{
++	wlc_ssid_ext_t ssids_local[MAX_PFN_LIST_COUNT];
++	int res = -1;
++	int nssid = 0;
++	cmd_tlv_t *cmd_tlv_temp;
++	char *str_ptr;
++	int tlv_size_left;
++	int pno_time = 0;
++	int pno_repeat = 0;
++	int pno_freq_expo_max = 0;
++
++#ifdef PNO_SET_DEBUG
++	int i;
++	char pno_in_example[] = {
++		'P', 'N', 'O', 'S', 'E', 'T', 'U', 'P', ' ',
++		'S', '1', '2', '0',
++		'S',
++		0x05,
++		'd', 'l', 'i', 'n', 'k',
++		'S',
++		0x04,
++		'G', 'O', 'O', 'G',
++		'T',
++		'0', 'B',
++		'R',
++		'2',
++		'M',
++		'2',
++		0x00
++		};
++#endif /* PNO_SET_DEBUG */
++	DHD_PNO(("%s: command=%s, len=%d\n", __FUNCTION__, command, total_len));
++
++	if (total_len < (strlen(CMD_PNOSETUP_SET) + sizeof(cmd_tlv_t))) {
++		DHD_ERROR(("%s argument=%d less min size\n", __FUNCTION__, total_len));
++		goto exit_proc;
++	}
++#ifdef PNO_SET_DEBUG
++	memcpy(command, pno_in_example, sizeof(pno_in_example));
++	total_len = sizeof(pno_in_example);
++#endif
++	str_ptr = command + strlen(CMD_PNOSETUP_SET);
++	tlv_size_left = total_len - strlen(CMD_PNOSETUP_SET);
++
++	cmd_tlv_temp = (cmd_tlv_t *)str_ptr;
++	memset(ssids_local, 0, sizeof(ssids_local));
++
++	if ((cmd_tlv_temp->prefix == PNO_TLV_PREFIX) &&
++		(cmd_tlv_temp->version == PNO_TLV_VERSION) &&
++		(cmd_tlv_temp->subtype == PNO_TLV_SUBTYPE_LEGACY_PNO)) {
++
++		str_ptr += sizeof(cmd_tlv_t);
++		tlv_size_left -= sizeof(cmd_tlv_t);
++
++		if ((nssid = wl_iw_parse_ssid_list_tlv(&str_ptr, ssids_local,
++			MAX_PFN_LIST_COUNT, &tlv_size_left)) <= 0) {
++			DHD_ERROR(("SSID is not presented or corrupted ret=%d\n", nssid));
++			goto exit_proc;
++		} else {
++			if ((str_ptr[0] != PNO_TLV_TYPE_TIME) || (tlv_size_left <= 1)) {
++				DHD_ERROR(("%s scan duration corrupted field size %d\n",
++					__FUNCTION__, tlv_size_left));
++				goto exit_proc;
++			}
++			str_ptr++;
++			pno_time = simple_strtoul(str_ptr, &str_ptr, 16);
++			DHD_PNO(("%s: pno_time=%d\n", __FUNCTION__, pno_time));
++
++			if (str_ptr[0] != 0) {
++				if ((str_ptr[0] != PNO_TLV_FREQ_REPEAT)) {
++					DHD_ERROR(("%s pno repeat : corrupted field\n",
++						__FUNCTION__));
++					goto exit_proc;
++				}
++				str_ptr++;
++				pno_repeat = simple_strtoul(str_ptr, &str_ptr, 16);
++				DHD_PNO(("%s :got pno_repeat=%d\n", __FUNCTION__, pno_repeat));
++				if (str_ptr[0] != PNO_TLV_FREQ_EXPO_MAX) {
++					DHD_ERROR(("%s FREQ_EXPO_MAX corrupted field size\n",
++						__FUNCTION__));
++					goto exit_proc;
++				}
++				str_ptr++;
++				pno_freq_expo_max = simple_strtoul(str_ptr, &str_ptr, 16);
++				DHD_PNO(("%s: pno_freq_expo_max=%d\n",
++					__FUNCTION__, pno_freq_expo_max));
++			}
++		}
++	} else {
++		DHD_ERROR(("%s get wrong TLV command\n", __FUNCTION__));
++		goto exit_proc;
++	}
++
++	res = dhd_dev_pno_set_for_ssid(dev, ssids_local, nssid, pno_time, pno_repeat,
++		pno_freq_expo_max, NULL, 0);
++exit_proc:
++	return res;
++}
++#endif /* !WL_SCHED_SCAN && OEM_ANDROID && WL_WIRELESS_EXT */
++#endif /* PNO_SUPPORT  */
++
++static int wl_android_get_p2p_dev_addr(struct net_device *ndev, char *command, int total_len)
++{
++	int ret;
++	int bytes_written = 0;
++
++	ret = wl_cfg80211_get_p2p_dev_addr(ndev, (struct ether_addr*)command);
++	if (ret)
++		return 0;
++	bytes_written = sizeof(struct ether_addr);
++	return bytes_written;
++}
++
++
++int
++wl_android_set_ap_mac_list(struct net_device *dev, int macmode, struct maclist *maclist)
++{
++	int i, j, match;
++	int ret	= 0;
++	char mac_buf[MAX_NUM_OF_ASSOCLIST *
++		sizeof(struct ether_addr) + sizeof(uint)] = {0};
++	struct maclist *assoc_maclist = (struct maclist *)mac_buf;
++
++	/* set filtering mode */
++	if ((ret = wldev_ioctl(dev, WLC_SET_MACMODE, &macmode, sizeof(macmode), true)) != 0) {
++		DHD_ERROR(("%s : WLC_SET_MACMODE error=%d\n", __FUNCTION__, ret));
++		return ret;
++	}
++	if (macmode != MACLIST_MODE_DISABLED) {
++		/* set the MAC filter list */
++		if ((ret = wldev_ioctl(dev, WLC_SET_MACLIST, maclist,
++			sizeof(int) + sizeof(struct ether_addr) * maclist->count, true)) != 0) {
++			DHD_ERROR(("%s : WLC_SET_MACLIST error=%d\n", __FUNCTION__, ret));
++			return ret;
++		}
++		/* get the current list of associated STAs */
++		assoc_maclist->count = MAX_NUM_OF_ASSOCLIST;
++		if ((ret = wldev_ioctl(dev, WLC_GET_ASSOCLIST, assoc_maclist,
++			sizeof(mac_buf), false)) != 0) {
++			DHD_ERROR(("%s : WLC_GET_ASSOCLIST error=%d\n", __FUNCTION__, ret));
++			return ret;
++		}
++		/* do we have any STA associated?  */
++		if (assoc_maclist->count) {
++			/* iterate each associated STA */
++			for (i = 0; i < assoc_maclist->count; i++) {
++				match = 0;
++				/* compare with each entry */
++				for (j = 0; j < maclist->count; j++) {
++					DHD_INFO(("%s : associated="MACDBG " list="MACDBG "\n",
++					__FUNCTION__, MAC2STRDBG(assoc_maclist->ea[i].octet),
++					MAC2STRDBG(maclist->ea[j].octet)));
++					if (memcmp(assoc_maclist->ea[i].octet,
++						maclist->ea[j].octet, ETHER_ADDR_LEN) == 0) {
++						match = 1;
++						break;
++					}
++				}
++				/* do conditional deauth */
++				/*   "if not in the allow list" or "if in the deny list" */
++				if ((macmode == MACLIST_MODE_ALLOW && !match) ||
++					(macmode == MACLIST_MODE_DENY && match)) {
++					scb_val_t scbval;
++
++					scbval.val = htod32(1);
++					memcpy(&scbval.ea, &assoc_maclist->ea[i],
++						ETHER_ADDR_LEN);
++					if ((ret = wldev_ioctl(dev,
++						WLC_SCB_DEAUTHENTICATE_FOR_REASON,
++						&scbval, sizeof(scb_val_t), true)) != 0)
++						DHD_ERROR(("%s WLC_SCB_DEAUTHENTICATE error=%d\n",
++							__FUNCTION__, ret));
++				}
++			}
++		}
++	}
++	return ret;
++}
++
++/*
++ * HAPD_MAC_FILTER mac_mode mac_cnt mac_addr1 mac_addr2
++ *
++ */
++static int
++wl_android_set_mac_address_filter(struct net_device *dev, const char* str)
++{
++	int i;
++	int ret = 0;
++	int macnum = 0;
++	int macmode = MACLIST_MODE_DISABLED;
++	struct maclist *list;
++	char eabuf[ETHER_ADDR_STR_LEN];
++	char *token;
++
++	/* string should look like below (macmode/macnum/maclist) */
++	/*   1 2 00:11:22:33:44:55 00:11:22:33:44:ff  */
++
++	/* get the MAC filter mode */
++	token = strsep((char**)&str, " ");
++	if (!token) {
++		return -1;
++	}
++	macmode = bcm_atoi(token);
++
++	if (macmode < MACLIST_MODE_DISABLED || macmode > MACLIST_MODE_ALLOW) {
++		DHD_ERROR(("%s : invalid macmode %d\n", __FUNCTION__, macmode));
++		return -1;
++	}
++
++	token = strsep((char**)&str, " ");
++	if (!token) {
++		return -1;
++	}
++	macnum = bcm_atoi(token);
++	if (macnum < 0 || macnum > MAX_NUM_MAC_FILT) {
++		DHD_ERROR(("%s : invalid number of MAC address entries %d\n",
++			__FUNCTION__, macnum));
++		return -1;
++	}
++	/* allocate memory for the MAC list */
++	list = (struct maclist*)kmalloc(sizeof(int) +
++		sizeof(struct ether_addr) * macnum, GFP_KERNEL);
++	if (!list) {
++		DHD_ERROR(("%s : failed to allocate memory\n", __FUNCTION__));
++		return -1;
++	}
++	/* prepare the MAC list */
++	list->count = htod32(macnum);
++	bzero((char *)eabuf, ETHER_ADDR_STR_LEN);
++	for (i = 0; i < list->count; i++) {
++		strncpy(eabuf, strsep((char**)&str, " "), ETHER_ADDR_STR_LEN - 1);
++		if (!(ret = bcm_ether_atoe(eabuf, &list->ea[i]))) {
++			DHD_ERROR(("%s : mac parsing err index=%d, addr=%s\n",
++				__FUNCTION__, i, eabuf));
++			list->count--;
++			break;
++		}
++		DHD_INFO(("%s : %d/%d MACADDR=%s", __FUNCTION__, i, list->count, eabuf));
++	}
++	/* set the list */
++	if ((ret = wl_android_set_ap_mac_list(dev, macmode, list)) != 0)
++		DHD_ERROR(("%s : Setting MAC list failed error=%d\n", __FUNCTION__, ret));
++
++	kfree(list);
++
++	return 0;
++}
++
++/**
++ * Global function definitions (declared in wl_android.h)
++ */
++
++int wl_android_wifi_on(struct net_device *dev)
++{
++	int ret = 0;
++	int retry = POWERUP_MAX_RETRY;
++
++	DHD_ERROR(("%s in\n", __FUNCTION__));
++	if (!dev) {
++		DHD_ERROR(("%s: dev is null\n", __FUNCTION__));
++		return -EINVAL;
++	}
++
++	dhd_net_if_lock(dev);
++	if (!g_wifi_on) {
++		do {
++			dhd_net_wifi_platform_set_power(dev, TRUE, WIFI_TURNON_DELAY);
++#ifdef BCMSDIO
++			ret = dhd_net_bus_resume(dev, 0);
++#endif /* BCMSDIO */
++#ifdef BCMPCIE
++			ret = dhd_net_bus_devreset(dev, FALSE);
++#endif /* BCMPCIE */
++			if (ret == 0) {
++				break;
++			}
++			DHD_ERROR(("\nfailed to power up wifi chip, retry again (%d left) **\n\n",
++				retry));
++#ifdef BCMPCIE
++			dhd_net_bus_devreset(dev, TRUE);
++#endif /* BCMPCIE */
++			dhd_net_wifi_platform_set_power(dev, FALSE, WIFI_TURNOFF_DELAY);
++		} while (retry-- > 0);
++		if (ret != 0) {
++			DHD_ERROR(("\nfailed to power up wifi chip, max retry reached **\n\n"));
++			goto exit;
++		}
++#ifdef BCMSDIO
++		ret = dhd_net_bus_devreset(dev, FALSE);
++		dhd_net_bus_resume(dev, 1);
++#endif /* BCMSDIO */
++
++#ifndef BCMPCIE
++		if (!ret) {
++			if (dhd_dev_init_ioctl(dev) < 0) {
++				ret = -EFAULT;
++			}
++		}
++#endif /* !BCMPCIE */
++		g_wifi_on = TRUE;
++	}
++
++exit:
++	dhd_net_if_unlock(dev);
++
++	return ret;
++}
++
++int wl_android_wifi_off(struct net_device *dev, bool on_failure)
++{
++	int ret = 0;
++
++	DHD_ERROR(("%s in\n", __FUNCTION__));
++	if (!dev) {
++		DHD_TRACE(("%s: dev is null\n", __FUNCTION__));
++		return -EINVAL;
++	}
++
++	dhd_net_if_lock(dev);
++	if (g_wifi_on || on_failure) {
++#if defined(BCMSDIO) || defined(BCMPCIE)
++		ret = dhd_net_bus_devreset(dev, TRUE);
++#ifdef BCMSDIO
++		dhd_net_bus_suspend(dev);
++#endif /* BCMSDIO */
++#endif /* BCMSDIO || BCMPCIE */
++		dhd_net_wifi_platform_set_power(dev, FALSE, WIFI_TURNOFF_DELAY);
++		g_wifi_on = FALSE;
++	}
++	dhd_net_if_unlock(dev);
++
++	return ret;
++}
++
++static int wl_android_set_fwpath(struct net_device *net, char *command, int total_len)
++{
++	if ((strlen(command) - strlen(CMD_SETFWPATH)) > MOD_PARAM_PATHLEN)
++		return -1;
++	return dhd_net_set_fw_path(net, command + strlen(CMD_SETFWPATH) + 1);
++}
++
++#ifdef CONNECTION_STATISTICS
++static int
++wl_chanim_stats(struct net_device *dev, u8 *chan_idle)
++{
++	int err;
++	wl_chanim_stats_t *list;
++	/* Parameter _and_ returned buffer of chanim_stats. */
++	wl_chanim_stats_t param;
++	u8 result[WLC_IOCTL_SMLEN];
++	chanim_stats_t *stats;
++
++	memset(&param, 0, sizeof(param));
++
++	param.buflen = htod32(sizeof(wl_chanim_stats_t));
++	param.count = htod32(WL_CHANIM_COUNT_ONE);
++
++	if ((err = wldev_iovar_getbuf(dev, "chanim_stats", (char*)&param, sizeof(wl_chanim_stats_t),
++		(char*)result, sizeof(result), 0)) < 0) {
++		WL_ERR(("Failed to get chanim results %d \n", err));
++		return err;
++	}
++
++	list = (wl_chanim_stats_t*)result;
++
++	list->buflen = dtoh32(list->buflen);
++	list->version = dtoh32(list->version);
++	list->count = dtoh32(list->count);
++
++	if (list->buflen == 0) {
++		list->version = 0;
++		list->count = 0;
++	} else if (list->version != WL_CHANIM_STATS_VERSION) {
++		WL_ERR(("Sorry, firmware has wl_chanim_stats version %d "
++			"but driver supports only version %d.\n",
++				list->version, WL_CHANIM_STATS_VERSION));
++		list->buflen = 0;
++		list->count = 0;
++	}
++
++	stats = list->stats;
++	stats->glitchcnt = dtoh32(stats->glitchcnt);
++	stats->badplcp = dtoh32(stats->badplcp);
++	stats->chanspec = dtoh16(stats->chanspec);
++	stats->timestamp = dtoh32(stats->timestamp);
++	stats->chan_idle = dtoh32(stats->chan_idle);
++
++	WL_INFORM(("chanspec: 0x%4x glitch: %d badplcp: %d idle: %d timestamp: %d\n",
++		stats->chanspec, stats->glitchcnt, stats->badplcp, stats->chan_idle,
++		stats->timestamp));
++
++	*chan_idle = stats->chan_idle;
++
++	return (err);
++}
++
++static int
++wl_android_get_connection_stats(struct net_device *dev, char *command, int total_len)
++{
++	static char iovar_buf[WLC_IOCTL_MAXLEN];
++	wl_cnt_wlc_t* wlc_cnt = NULL;
++#ifndef DISABLE_IF_COUNTERS
++	wl_if_stats_t* if_stats = NULL;
++#endif /* DISABLE_IF_COUNTERS */
++
++	int link_speed = 0;
++	struct connection_stats *output;
++	unsigned int bufsize = 0;
++	int bytes_written = -1;
++	int ret = 0;
++
++	WL_INFORM(("%s: enter Get Connection Stats\n", __FUNCTION__));
++
++	if (total_len <= 0) {
++		WL_ERR(("%s: invalid buffer size %d\n", __FUNCTION__, total_len));
++		goto error;
++	}
++
++	bufsize = total_len;
++	if (bufsize < sizeof(struct connection_stats)) {
++		WL_ERR(("%s: not enough buffer size, provided=%u, requires=%zu\n",
++			__FUNCTION__, bufsize,
++			sizeof(struct connection_stats)));
++		goto error;
++	}
++
++	output = (struct connection_stats *)command;
++
++#ifndef DISABLE_IF_COUNTERS
++	if ((if_stats = kmalloc(sizeof(*if_stats), GFP_KERNEL)) == NULL) {
++		WL_ERR(("%s(%d): kmalloc failed\n", __FUNCTION__, __LINE__));
++		goto error;
++	}
++	memset(if_stats, 0, sizeof(*if_stats));
++
++	ret = wldev_iovar_getbuf(dev, "if_counters", NULL, 0,
++		(char *)if_stats, sizeof(*if_stats), NULL);
++	if (ret) {
++		WL_ERR(("%s: if_counters not supported ret=%d\n",
++			__FUNCTION__, ret));
++
++		/* In case if_stats IOVAR is not supported, get information from counters. */
++#endif /* DISABLE_IF_COUNTERS */
++		ret = wldev_iovar_getbuf(dev, "counters", NULL, 0,
++			iovar_buf, WLC_IOCTL_MAXLEN, NULL);
++		if (unlikely(ret)) {
++			WL_ERR(("counters error (%d) - size = %zu\n", ret, sizeof(wl_cnt_wlc_t)));
++			goto error;
++		}
++		ret = wl_cntbuf_to_xtlv_format(NULL, iovar_buf, WL_CNTBUF_MAX_SIZE, 0);
++		if (ret != BCME_OK) {
++			WL_ERR(("%s wl_cntbuf_to_xtlv_format ERR %d\n",
++			__FUNCTION__, ret));
++			goto error;
++		}
++
++		if (!(wlc_cnt = GET_WLCCNT_FROM_CNTBUF(iovar_buf))) {
++			WL_ERR(("%s wlc_cnt NULL!\n", __FUNCTION__));
++			goto error;
++		}
++
++		output->txframe   = dtoh32(wlc_cnt->txframe);
++		output->txbyte    = dtoh32(wlc_cnt->txbyte);
++		output->txerror   = dtoh32(wlc_cnt->txerror);
++		output->rxframe   = dtoh32(wlc_cnt->rxframe);
++		output->rxbyte    = dtoh32(wlc_cnt->rxbyte);
++		output->txfail    = dtoh32(wlc_cnt->txfail);
++		output->txretry   = dtoh32(wlc_cnt->txretry);
++		output->txretrie  = dtoh32(wlc_cnt->txretrie);
++		output->txrts     = dtoh32(wlc_cnt->txrts);
++		output->txnocts   = dtoh32(wlc_cnt->txnocts);
++		output->txexptime = dtoh32(wlc_cnt->txexptime);
++#ifndef DISABLE_IF_COUNTERS
++	} else {
++		/* Populate from if_stats. */
++		if (dtoh16(if_stats->version) > WL_IF_STATS_T_VERSION) {
++			WL_ERR(("%s: incorrect version of wl_if_stats_t, expected=%u got=%u\n",
++				__FUNCTION__,  WL_IF_STATS_T_VERSION, if_stats->version));
++			goto error;
++		}
++
++		output->txframe   = (uint32)dtoh64(if_stats->txframe);
++		output->txbyte    = (uint32)dtoh64(if_stats->txbyte);
++		output->txerror   = (uint32)dtoh64(if_stats->txerror);
++		output->rxframe   = (uint32)dtoh64(if_stats->rxframe);
++		output->rxbyte    = (uint32)dtoh64(if_stats->rxbyte);
++		output->txfail    = (uint32)dtoh64(if_stats->txfail);
++		output->txretry   = (uint32)dtoh64(if_stats->txretry);
++		output->txretrie  = (uint32)dtoh64(if_stats->txretrie);
++		if (dtoh16(if_stats->length) > OFFSETOF(wl_if_stats_t, txexptime)) {
++			output->txexptime = (uint32)dtoh64(if_stats->txexptime);
++			output->txrts     = (uint32)dtoh64(if_stats->txrts);
++			output->txnocts   = (uint32)dtoh64(if_stats->txnocts);
++		} else {
++			output->txexptime = 0;
++			output->txrts     = 0;
++			output->txnocts   = 0;
++		}
++	}
++#endif /* DISABLE_IF_COUNTERS */
++
++	/* link_speed is in kbps */
++	ret = wldev_get_link_speed(dev, &link_speed);
++	if (ret || link_speed < 0) {
++		WL_ERR(("%s: wldev_get_link_speed() failed, ret=%d, speed=%d\n",
++			__FUNCTION__, ret, link_speed));
++		goto error;
++	}
++
++	output->txrate    = link_speed;
++
++	/* Channel idle ratio. */
++	if (wl_chanim_stats(dev, &(output->chan_idle)) < 0) {
++		output->chan_idle = 0;
++	};
++
++	bytes_written = sizeof(struct connection_stats);
++
++error:
++#ifndef DISABLE_IF_COUNTERS
++	if (if_stats) {
++		kfree(if_stats);
++	}
++#endif /* DISABLE_IF_COUNTERS */
++
++	return bytes_written;
++}
++#endif /* CONNECTION_STATISTICS */
++
++static int
++wl_android_set_pmk(struct net_device *dev, char *command, int total_len)
++{
++	uchar pmk[33];
++	int error = 0;
++	char smbuf[WLC_IOCTL_SMLEN];
++#ifdef OKC_DEBUG
++	int i = 0;
++#endif
++
++	bzero(pmk, sizeof(pmk));
++	memcpy((char *)pmk, command + strlen("SET_PMK "), 32);
++	error = wldev_iovar_setbuf(dev, "okc_info_pmk", pmk, 32, smbuf, sizeof(smbuf), NULL);
++	if (error) {
++		DHD_ERROR(("Failed to set PMK for OKC, error = %d\n", error));
++	}
++#ifdef OKC_DEBUG
++	DHD_ERROR(("PMK is "));
++	for (i = 0; i < 32; i++)
++		DHD_ERROR(("%02X ", pmk[i]));
++
++	DHD_ERROR(("\n"));
++#endif
++	return error;
++}
++
++static int
++wl_android_okc_enable(struct net_device *dev, char *command, int total_len)
++{
++	int error = 0;
++	char okc_enable = 0;
++
++	okc_enable = command[strlen(CMD_OKC_ENABLE) + 1] - '0';
++	error = wldev_iovar_setint(dev, "okc_enable", okc_enable);
++	if (error) {
++		DHD_ERROR(("Failed to %s OKC, error = %d\n",
++			okc_enable ? "enable" : "disable", error));
++		return error;
++	}
++
++	error = wldev_iovar_setint(dev, "ccx_enable", 0);
++	if (error) {
++		DHD_ERROR(("Failed to disable CCX %d\n", error));
++	}
++
++	return error;
++}
++
++
++
++/* SoftAP feature */
++#define APCS_BAND_2G_LEGACY1	20
++#define APCS_BAND_2G_LEGACY2	0
++#define APCS_BAND_AUTO		"band=auto"
++#define APCS_BAND_2G		"band=2g"
++#define APCS_BAND_5G		"band=5g"
++#define APCS_MAX_2G_CHANNELS	11
++#if defined(WL_SUPPORT_AUTO_CHANNEL)
++static int
++wl_android_set_auto_channel(struct net_device *dev, const char* cmd_str,
++	char* command, int total_len)
++{
++	int channel = 0;
++	int chosen = 0;
++	int retry = 0;
++	int ret = 0;
++	int spect = 0;
++	u8 *reqbuf = NULL;
++	uint32 band = WLC_BAND_2G;
++	uint32 buf_size;
++
++	if (cmd_str) {
++		DHD_INFO(("Command: %s len:%d \n", cmd_str, (int)strlen(cmd_str)));
++		if (strncmp(cmd_str, APCS_BAND_AUTO, strlen(APCS_BAND_AUTO)) == 0) {
++			band = WLC_BAND_AUTO;
++		} else if (strncmp(cmd_str, APCS_BAND_5G, strlen(APCS_BAND_5G)) == 0) {
++			band = WLC_BAND_5G;
++		} else if (strncmp(cmd_str, APCS_BAND_2G, strlen(APCS_BAND_2G)) == 0) {
++			band = WLC_BAND_2G;
++		} else {
++			/*
++			 * For backward compatibility: Some platforms used to issue argument 20 or 0
++			 * to enforce the 2G channel selection
++			 */
++			channel = bcm_atoi(cmd_str);
++			if ((channel == APCS_BAND_2G_LEGACY1) ||
++				(channel == APCS_BAND_2G_LEGACY2))
++				band = WLC_BAND_2G;
++			else {
++				DHD_ERROR(("ACS: Invalid argument\n"));
++				return -EINVAL;
++			}
++		}
++	} else {
++		/* If no argument is provided, default to 2G */
++		DHD_ERROR(("%s: No argument given default to 2.4G scan", __func__));
++		band = WLC_BAND_2G;
++	}
++	DHD_INFO(("%s : HAPD_AUTO_CHANNEL = %d, band=%d \n", __FUNCTION__, channel, band));
++
++	reqbuf = kzalloc(CHANSPEC_BUF_SIZE, GFP_KERNEL);
++	if (reqbuf == NULL) {
++		WL_ERR(("failed to allocate chanspec buffer\n"));
++		return -ENOMEM;
++	}
++
++	if ((ret = wldev_ioctl(dev, WLC_GET_SPECT_MANAGMENT, &spect, sizeof(spect), false)) < 0) {
++		WL_ERR(("ACS:error getting the spect\n"));
++		goto done;
++	}
++
++	if (spect > 0) {
++		/* If STA is connected, return is STA channel, else ACS can be issued,
++		 * set spect to 0 and proceed with ACS
++		 */
++		channel = 0;
++		if ((channel = wl_cfg80211_get_sta_channel(dev)) > 0) {
++			goto done2;
++		} else if ((ret = wl_cfg80211_set_spect(dev, 0) < 0)) {
++			WL_ERR(("ACS: error while setting spect\n"));
++			goto done;
++		}
++	}
++
++	if (band == WLC_BAND_AUTO) {
++		DHD_INFO(("%s: ACS full channel scan \n", __func__));
++		reqbuf[0] = htod32(0);
++	} else if (band == WLC_BAND_5G) {
++		DHD_INFO(("%s: ACS 5G band scan \n", __func__));
++		if ((ret = wl_cfg80211_get_chanspecs_5g(dev, reqbuf, CHANSPEC_BUF_SIZE)) < 0) {
++			WL_ERR(("ACS 5g chanspec retreival failed! \n"));
++			goto done;
++		}
++	} else if (band == WLC_BAND_2G) {
++		/*
++		 * If channel argument is not provided/ argument 20 is provided,
++		 * Restrict channel to 2GHz, 20MHz BW, No SB
++		 */
++		DHD_INFO(("%s: ACS 2G band scan \n", __func__));
++		if ((ret = wl_cfg80211_get_chanspecs_2g(dev, reqbuf, CHANSPEC_BUF_SIZE)) < 0) {
++			WL_ERR(("ACS 2g chanspec retreival failed! \n"));
++			goto done;
++		}
++	} else {
++		DHD_ERROR(("ACS: No band chosen\n"));
++		goto done2;
++	}
++
++	buf_size = (band == WLC_BAND_AUTO) ? sizeof(int) : CHANSPEC_BUF_SIZE;
++	ret = wldev_ioctl(dev, WLC_START_CHANNEL_SEL, (void *)reqbuf,
++		buf_size, true);
++	if (ret < 0) {
++		DHD_ERROR(("%s: can't start auto channel scan, err = %d\n",
++			__FUNCTION__, ret));
++		channel = 0;
++		goto done;
++	}
++
++	/* Wait for auto channel selection, max 3000 ms */
++	if ((band == WLC_BAND_2G) || (band == WLC_BAND_5G)) {
++		OSL_SLEEP(500);
++	} else {
++		/*
++		 * Full channel scan at the minimum takes 1.2secs
++		 * even with parallel scan. max wait time: 3500ms
++		 */
++		OSL_SLEEP(1000);
++	}
++
++	retry = 10;
++	while (retry--) {
++		ret = wldev_ioctl(dev, WLC_GET_CHANNEL_SEL, &chosen,
++			sizeof(chosen), false);
++		if (ret < 0 || dtoh32(chosen) == 0) {
++			DHD_INFO(("%s: %d tried, ret = %d, chosen = %d\n",
++				__FUNCTION__, (10 - retry), ret, chosen));
++			OSL_SLEEP(250);
++		} else {
++#ifdef D11AC_IOTYPES
++			if (wl_cfg80211_get_ioctl_version() == 1)
++				channel = LCHSPEC_CHANNEL((u16)chosen);
++			else
++				channel = CHSPEC_CHANNEL((u16)chosen);
++#else
++			channel = CHSPEC_CHANNEL((u16)chosen);
++#endif /* D11AC_IOTYPES */
++			DHD_ERROR(("%s: selected channel = %d\n", __FUNCTION__, channel));
++			break;
++		}
++	}
++
++done:
++	if ((retry == 0) || (ret < 0)) {
++		/* On failure, fallback to a default channel */
++		if ((band == WLC_BAND_5G)) {
++			channel = 36;
++		} else {
++			channel = 1;
++		}
++		DHD_ERROR(("%s: ACS failed."
++			" Fall back to default channel (%d) \n", __FUNCTION__, channel));
++	}
++done2:
++	if (spect) {
++		if ((ret = wl_cfg80211_set_spect(dev, spect) < 0)) {
++			WL_ERR(("ACS: error while setting spect\n"));
++		}
++	}
++	if (reqbuf)
++		kfree(reqbuf);
++
++	if (channel) {
++		snprintf(command, 4, "%d", channel);
++		DHD_INFO(("%s: command result is %s \n", __FUNCTION__, command));
++		return strlen(command);
++	} else {
++		return ret;
++	}
++}
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++
++
++int wl_android_set_roam_mode(struct net_device *dev, char *command, int total_len)
++{
++	int error = 0;
++	int mode = 0;
++
++	if (sscanf(command, "%*s %d", &mode) != 1) {
++		DHD_ERROR(("%s: Failed to get Parameter\n", __FUNCTION__));
++		return -1;
++	}
++
++	error = wldev_iovar_setint(dev, "roam_off", mode);
++	if (error) {
++		DHD_ERROR(("%s: Failed to set roaming Mode %d, error = %d\n",
++		__FUNCTION__, mode, error));
++		return -1;
++	}
++	else
++		DHD_ERROR(("%s: succeeded to set roaming Mode %d, error = %d\n",
++		__FUNCTION__, mode, error));
++	return 0;
++}
++
++int wl_android_set_ibss_beacon_ouidata(struct net_device *dev, char *command, int total_len)
++{
++	char ie_buf[VNDR_IE_MAX_LEN];
++	char *ioctl_buf = NULL;
++	char hex[] = "XX";
++	char *pcmd = NULL;
++	int ielen = 0, datalen = 0, idx = 0, tot_len = 0;
++	vndr_ie_setbuf_t *vndr_ie = NULL;
++	s32 iecount;
++	uint32 pktflag;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	s32 err = BCME_OK;
++
++	/* Check the VSIE (Vendor Specific IE) which was added.
++	 *  If exist then send IOVAR to delete it
++	 */
++	if (wl_cfg80211_ibss_vsie_delete(dev) != BCME_OK) {
++		return -EINVAL;
++	}
++
++	pcmd = command + strlen(CMD_SETIBSSBEACONOUIDATA) + 1;
++	for (idx = 0; idx < DOT11_OUI_LEN; idx++) {
++		hex[0] = *pcmd++;
++		hex[1] = *pcmd++;
++		ie_buf[idx] =  (uint8)simple_strtoul(hex, NULL, 16);
++	}
++	pcmd++;
++	while ((*pcmd != '\0') && (idx < VNDR_IE_MAX_LEN)) {
++		hex[0] = *pcmd++;
++		hex[1] = *pcmd++;
++		ie_buf[idx++] =  (uint8)simple_strtoul(hex, NULL, 16);
++		datalen++;
++	}
++	tot_len = sizeof(vndr_ie_setbuf_t) + (datalen - 1);
++	vndr_ie = (vndr_ie_setbuf_t *) kzalloc(tot_len, kflags);
++	if (!vndr_ie) {
++		WL_ERR(("IE memory alloc failed\n"));
++		return -ENOMEM;
++	}
++	/* Copy the vndr_ie SET command ("add"/"del") to the buffer */
++	strncpy(vndr_ie->cmd, "add", VNDR_IE_CMD_LEN - 1);
++	vndr_ie->cmd[VNDR_IE_CMD_LEN - 1] = '\0';
++
++	/* Set the IE count - the buffer contains only 1 IE */
++	iecount = htod32(1);
++	memcpy((void *)&vndr_ie->vndr_ie_buffer.iecount, &iecount, sizeof(s32));
++
++	/* Set packet flag to indicate that BEACON's will contain this IE */
++	pktflag = htod32(VNDR_IE_BEACON_FLAG | VNDR_IE_PRBRSP_FLAG);
++	memcpy((void *)&vndr_ie->vndr_ie_buffer.vndr_ie_list[0].pktflag, &pktflag,
++		sizeof(u32));
++	/* Set the IE ID */
++	vndr_ie->vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.id = (uchar) DOT11_MNG_PROPR_ID;
++
++	memcpy(&vndr_ie->vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.oui, &ie_buf,
++		DOT11_OUI_LEN);
++	memcpy(&vndr_ie->vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.data,
++		&ie_buf[DOT11_OUI_LEN], datalen);
++
++	ielen = DOT11_OUI_LEN + datalen;
++	vndr_ie->vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.len = (uchar) ielen;
++
++	ioctl_buf = kmalloc(WLC_IOCTL_MEDLEN, GFP_KERNEL);
++	if (!ioctl_buf) {
++		WL_ERR(("ioctl memory alloc failed\n"));
++		if (vndr_ie) {
++			kfree(vndr_ie);
++		}
++		return -ENOMEM;
++	}
++	memset(ioctl_buf, 0, WLC_IOCTL_MEDLEN);	/* init the buffer */
++	err = wldev_iovar_setbuf(dev, "ie", vndr_ie, tot_len, ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++
++
++	if (err != BCME_OK) {
++		err = -EINVAL;
++		if (vndr_ie) {
++			kfree(vndr_ie);
++		}
++	}
++	else {
++		/* do NOT free 'vndr_ie' for the next process */
++		wl_cfg80211_ibss_vsie_set_buffer(vndr_ie, tot_len);
++	}
++
++	if (ioctl_buf) {
++		kfree(ioctl_buf);
++	}
++
++	return err;
++}
++
++#if defined(BCMFW_ROAM_ENABLE)
++static int
++wl_android_set_roampref(struct net_device *dev, char *command, int total_len)
++{
++	int error = 0;
++	char smbuf[WLC_IOCTL_SMLEN];
++	uint8 buf[MAX_BUF_SIZE];
++	uint8 *pref = buf;
++	char *pcmd;
++	int num_ucipher_suites = 0;
++	int num_akm_suites = 0;
++	wpa_suite_t ucipher_suites[MAX_NUM_SUITES];
++	wpa_suite_t akm_suites[MAX_NUM_SUITES];
++	int num_tuples = 0;
++	int total_bytes = 0;
++	int total_len_left;
++	int i, j;
++	char hex[] = "XX";
++
++	pcmd = command + strlen(CMD_SET_ROAMPREF) + 1;
++	total_len_left = total_len - strlen(CMD_SET_ROAMPREF) + 1;
++
++	num_akm_suites = simple_strtoul(pcmd, NULL, 16);
++	/* Increment for number of AKM suites field + space */
++	pcmd += 3;
++	total_len_left -= 3;
++
++	/* check to make sure pcmd does not overrun */
++	if (total_len_left < (num_akm_suites * WIDTH_AKM_SUITE))
++		return -1;
++
++	memset(buf, 0, sizeof(buf));
++	memset(akm_suites, 0, sizeof(akm_suites));
++	memset(ucipher_suites, 0, sizeof(ucipher_suites));
++
++	/* Save the AKM suites passed in the command */
++	for (i = 0; i < num_akm_suites; i++) {
++		/* Store the MSB first, as required by join_pref */
++		for (j = 0; j < 4; j++) {
++			hex[0] = *pcmd++;
++			hex[1] = *pcmd++;
++			buf[j] = (uint8)simple_strtoul(hex, NULL, 16);
++		}
++		memcpy((uint8 *)&akm_suites[i], buf, sizeof(uint32));
++	}
++
++	total_len_left -= (num_akm_suites * WIDTH_AKM_SUITE);
++	num_ucipher_suites = simple_strtoul(pcmd, NULL, 16);
++	/* Increment for number of cipher suites field + space */
++	pcmd += 3;
++	total_len_left -= 3;
++
++	if (total_len_left < (num_ucipher_suites * WIDTH_AKM_SUITE))
++		return -1;
++
++	/* Save the cipher suites passed in the command */
++	for (i = 0; i < num_ucipher_suites; i++) {
++		/* Store the MSB first, as required by join_pref */
++		for (j = 0; j < 4; j++) {
++			hex[0] = *pcmd++;
++			hex[1] = *pcmd++;
++			buf[j] = (uint8)simple_strtoul(hex, NULL, 16);
++		}
++		memcpy((uint8 *)&ucipher_suites[i], buf, sizeof(uint32));
++	}
++
++	/* Join preference for RSSI
++	 * Type	  : 1 byte (0x01)
++	 * Length : 1 byte (0x02)
++	 * Value  : 2 bytes	(reserved)
++	 */
++	*pref++ = WL_JOIN_PREF_RSSI;
++	*pref++ = JOIN_PREF_RSSI_LEN;
++	*pref++ = 0;
++	*pref++ = 0;
++
++	/* Join preference for WPA
++	 * Type	  : 1 byte (0x02)
++	 * Length : 1 byte (not used)
++	 * Value  : (variable length)
++	 *		reserved: 1 byte
++	 *      count	: 1 byte (no of tuples)
++	 *		Tuple1	: 12 bytes
++	 *			akm[4]
++	 *			ucipher[4]
++	 *			mcipher[4]
++	 *		Tuple2	: 12 bytes
++	 *		Tuplen	: 12 bytes
++	 */
++	num_tuples = num_akm_suites * num_ucipher_suites;
++	if (num_tuples != 0) {
++		if (num_tuples <= JOIN_PREF_MAX_WPA_TUPLES) {
++			*pref++ = WL_JOIN_PREF_WPA;
++			*pref++ = 0;
++			*pref++ = 0;
++			*pref++ = (uint8)num_tuples;
++			total_bytes = JOIN_PREF_RSSI_SIZE + JOIN_PREF_WPA_HDR_SIZE +
++				(JOIN_PREF_WPA_TUPLE_SIZE * num_tuples);
++		} else {
++			DHD_ERROR(("%s: Too many wpa configs for join_pref \n", __FUNCTION__));
++			return -1;
++		}
++	} else {
++		/* No WPA config, configure only RSSI preference */
++		total_bytes = JOIN_PREF_RSSI_SIZE;
++	}
++
++	/* akm-ucipher-mcipher tuples in the format required for join_pref */
++	for (i = 0; i < num_ucipher_suites; i++) {
++		for (j = 0; j < num_akm_suites; j++) {
++			memcpy(pref, (uint8 *)&akm_suites[j], WPA_SUITE_LEN);
++			pref += WPA_SUITE_LEN;
++			memcpy(pref, (uint8 *)&ucipher_suites[i], WPA_SUITE_LEN);
++			pref += WPA_SUITE_LEN;
++			/* Set to 0 to match any available multicast cipher */
++			memset(pref, 0, WPA_SUITE_LEN);
++			pref += WPA_SUITE_LEN;
++		}
++	}
++
++	prhex("join pref", (uint8 *)buf, total_bytes);
++	error = wldev_iovar_setbuf(dev, "join_pref", buf, total_bytes, smbuf, sizeof(smbuf), NULL);
++	if (error) {
++		DHD_ERROR(("Failed to set join_pref, error = %d\n", error));
++	}
++	return error;
++}
++#endif /* defined(BCMFW_ROAM_ENABLE */
++
++static int
++wl_android_iolist_add(struct net_device *dev, struct list_head *head, struct io_cfg *config)
++{
++	struct io_cfg *resume_cfg;
++	s32 ret;
++
++	resume_cfg = kzalloc(sizeof(struct io_cfg), GFP_KERNEL);
++	if (!resume_cfg)
++		return -ENOMEM;
++
++	if (config->iovar) {
++		ret = wldev_iovar_getint(dev, config->iovar, &resume_cfg->param);
++		if (ret) {
++			DHD_ERROR(("%s: Failed to get current %s value\n",
++				__FUNCTION__, config->iovar));
++			goto error;
++		}
++
++		ret = wldev_iovar_setint(dev, config->iovar, config->param);
++		if (ret) {
++			DHD_ERROR(("%s: Failed to set %s to %d\n", __FUNCTION__,
++				config->iovar, config->param));
++			goto error;
++		}
++
++		resume_cfg->iovar = config->iovar;
++	} else {
++		resume_cfg->arg = kzalloc(config->len, GFP_KERNEL);
++		if (!resume_cfg->arg) {
++			ret = -ENOMEM;
++			goto error;
++		}
++		ret = wldev_ioctl(dev, config->ioctl, resume_cfg->arg, config->len, false);
++		if (ret) {
++			DHD_ERROR(("%s: Failed to get ioctl %d\n", __FUNCTION__,
++				config->ioctl));
++			goto error;
++		}
++		ret = wldev_ioctl(dev, config->ioctl + 1, config->arg, config->len, true);
++		if (ret) {
++			DHD_ERROR(("%s: Failed to set %s to %d\n", __FUNCTION__,
++				config->iovar, config->param));
++			goto error;
++		}
++		if (config->ioctl + 1 == WLC_SET_PM)
++			wl_cfg80211_update_power_mode(dev);
++		resume_cfg->ioctl = config->ioctl;
++		resume_cfg->len = config->len;
++	}
++
++	list_add(&resume_cfg->list, head);
++
++	return 0;
++error:
++	kfree(resume_cfg->arg);
++	kfree(resume_cfg);
++	return ret;
++}
++
++static void
++wl_android_iolist_resume(struct net_device *dev, struct list_head *head)
++{
++	struct io_cfg *config;
++	struct list_head *cur, *q;
++	s32 ret = 0;
++
++	list_for_each_safe(cur, q, head) {
++		config = list_entry(cur, struct io_cfg, list);
++		if (config->iovar) {
++			if (!ret)
++				ret = wldev_iovar_setint(dev, config->iovar,
++					config->param);
++		} else {
++			if (!ret)
++				ret = wldev_ioctl(dev, config->ioctl + 1,
++					config->arg, config->len, true);
++			if (config->ioctl + 1 == WLC_SET_PM)
++				wl_cfg80211_update_power_mode(dev);
++			kfree(config->arg);
++		}
++		list_del(cur);
++		kfree(config);
++	}
++}
++#ifdef WL11ULB
++static int
++wl_android_set_ulb_mode(struct net_device *dev, char *command, int total_len)
++{
++	int mode = 0;
++
++	DHD_INFO(("set ulb mode (%s) \n", command));
++	if (sscanf(command, "%*s %d", &mode) != 1) {
++		DHD_ERROR(("%s: Failed to get Parameter\n", __FUNCTION__));
++		return -1;
++	}
++	return wl_cfg80211_set_ulb_mode(dev, mode);
++}
++static int
++wl_android_set_ulb_bw(struct net_device *dev, char *command, int total_len)
++{
++	int bw = 0;
++	u8 *pos;
++	char *ifname = NULL;
++	DHD_INFO(("set ulb bw (%s) \n", command));
++
++	/*
++	 * For sta/ap: IFNAME=<ifname> DRIVER ULB_BW <bw> ifname
++	 * For p2p:    IFNAME=wlan0 DRIVER ULB_BW <bw> p2p-dev-wlan0
++	 */
++	if (total_len < strlen(CMD_ULB_BW) + 2)
++		return -EINVAL;
++
++	pos = command + strlen(CMD_ULB_BW) + 1;
++	bw = bcm_atoi(pos);
++
++	if ((strlen(pos) >= 5)) {
++		ifname = pos + 2;
++	}
++
++	DHD_INFO(("[ULB] ifname:%s ulb_bw:%d \n", ifname, bw));
++	return wl_cfg80211_set_ulb_bw(dev, bw, ifname);
++}
++#endif /* WL11ULB */
++static int
++wl_android_set_miracast(struct net_device *dev, char *command, int total_len)
++{
++	int mode, val = 0;
++	int ret = 0;
++	struct io_cfg config;
++
++	if (sscanf(command, "%*s %d", &mode) != 1) {
++		DHD_ERROR(("%s: Failed to get Parameter\n", __FUNCTION__));
++		return -1;
++	}
++
++	DHD_INFO(("%s: enter miracast mode %d\n", __FUNCTION__, mode));
++
++	if (miracast_cur_mode == mode) {
++		return 0;
++	}
++
++	wl_android_iolist_resume(dev, &miracast_resume_list);
++	miracast_cur_mode = MIRACAST_MODE_OFF;
++
++	switch (mode) {
++	case MIRACAST_MODE_SOURCE:
++		/* setting mchan_algo to platform specific value */
++		config.iovar = "mchan_algo";
++
++		ret = wldev_ioctl(dev, WLC_GET_BCNPRD, &val, sizeof(int), false);
++		if (!ret && val > 100) {
++			config.param = 0;
++			DHD_ERROR(("%s: Connected station's beacon interval: "
++				"%d and set mchan_algo to %d \n",
++				__FUNCTION__, val, config.param));
++		} else {
++			config.param = MIRACAST_MCHAN_ALGO;
++		}
++		ret = wl_android_iolist_add(dev, &miracast_resume_list, &config);
++		if (ret) {
++			goto resume;
++		}
++
++		/* setting mchan_bw to platform specific value */
++		config.iovar = "mchan_bw";
++		config.param = MIRACAST_MCHAN_BW;
++		ret = wl_android_iolist_add(dev, &miracast_resume_list, &config);
++		if (ret) {
++			goto resume;
++		}
++
++		/* setting apmdu to platform specific value */
++		config.iovar = "ampdu_mpdu";
++		config.param = MIRACAST_AMPDU_SIZE;
++		ret = wl_android_iolist_add(dev, &miracast_resume_list, &config);
++		if (ret) {
++			goto resume;
++		}
++		/* FALLTROUGH */
++		/* Source mode shares most configurations with sink mode.
++		 * Fall through here to avoid code duplication
++		 */
++	case MIRACAST_MODE_SINK:
++		/* disable internal roaming */
++		config.iovar = "roam_off";
++		config.param = 1;
++		ret = wl_android_iolist_add(dev, &miracast_resume_list, &config);
++		if (ret) {
++			goto resume;
++		}
++
++		/* tunr off pm */
++		ret = wldev_ioctl(dev, WLC_GET_PM, &val, sizeof(val), false);
++		if (ret) {
++			goto resume;
++		}
++
++		if (val != PM_OFF) {
++			val = PM_OFF;
++			config.iovar = NULL;
++			config.ioctl = WLC_GET_PM;
++			config.arg = &val;
++			config.len = sizeof(int);
++			ret = wl_android_iolist_add(dev, &miracast_resume_list, &config);
++			if (ret) {
++				goto resume;
++			}
++		}
++		break;
++	case MIRACAST_MODE_OFF:
++	default:
++		break;
++	}
++	miracast_cur_mode = mode;
++
++	return 0;
++
++resume:
++	DHD_ERROR(("%s: turnoff miracast mode because of err%d\n", __FUNCTION__, ret));
++	wl_android_iolist_resume(dev, &miracast_resume_list);
++	return ret;
++}
++
++#define NETLINK_OXYGEN     30
++#define AIBSS_BEACON_TIMEOUT	10
++
++static struct sock *nl_sk = NULL;
++
++static void wl_netlink_recv(struct sk_buff *skb)
++{
++	WL_ERR(("netlink_recv called\n"));
++}
++
++static int wl_netlink_init(void)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	struct netlink_kernel_cfg cfg = {
++		.input	= wl_netlink_recv,
++	};
++#endif
++
++	if (nl_sk != NULL) {
++		WL_ERR(("nl_sk already exist\n"));
++		return BCME_ERROR;
++	}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++	nl_sk = netlink_kernel_create(&init_net, NETLINK_OXYGEN,
++		0, wl_netlink_recv, NULL, THIS_MODULE);
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0))
++	nl_sk = netlink_kernel_create(&init_net, NETLINK_OXYGEN, THIS_MODULE, &cfg);
++#else
++	nl_sk = netlink_kernel_create(&init_net, NETLINK_OXYGEN, &cfg);
++#endif
++
++	if (nl_sk == NULL) {
++		WL_ERR(("nl_sk is not ready\n"));
++		return BCME_ERROR;
++	}
++
++	return BCME_OK;
++}
++
++static void wl_netlink_deinit(void)
++{
++	if (nl_sk) {
++		netlink_kernel_release(nl_sk);
++		nl_sk = NULL;
++	}
++}
++
++s32
++wl_netlink_send_msg(int pid, int type, int seq, void *data, size_t size)
++{
++	struct sk_buff *skb = NULL;
++	struct nlmsghdr *nlh = NULL;
++	int ret = -1;
++
++	if (nl_sk == NULL) {
++		WL_ERR(("nl_sk was not initialized\n"));
++		goto nlmsg_failure;
++	}
++
++	skb = alloc_skb(NLMSG_SPACE(size), GFP_ATOMIC);
++	if (skb == NULL) {
++		WL_ERR(("failed to allocate memory\n"));
++		goto nlmsg_failure;
++	}
++
++	nlh = nlmsg_put(skb, 0, 0, 0, size, 0);
++	if (nlh == NULL) {
++		WL_ERR(("failed to build nlmsg, skb_tailroom:%d, nlmsg_total_size:%d\n",
++			skb_tailroom(skb), nlmsg_total_size(size)));
++		dev_kfree_skb(skb);
++		goto nlmsg_failure;
++	}
++
++	memcpy(nlmsg_data(nlh), data, size);
++	nlh->nlmsg_seq = seq;
++	nlh->nlmsg_type = type;
++
++	/* netlink_unicast() takes ownership of the skb and frees it itself. */
++	ret = netlink_unicast(nl_sk, skb, pid, 0);
++	WL_DBG(("netlink_unicast() pid=%d, ret=%d\n", pid, ret));
++
++nlmsg_failure:
++	return ret;
++}
++
++
++int wl_keep_alive_set(struct net_device *dev, char* extra, int total_len)
++{
++	wl_mkeep_alive_pkt_t	mkeep_alive_pkt;
++	int ret;
++	uint period_msec = 0;
++	char *buf;
++
++	if (extra == NULL)
++	{
++		 DHD_ERROR(("%s: extra is NULL\n", __FUNCTION__));
++		 return -1;
++	}
++	if (sscanf(extra, "%d", &period_msec) != 1)
++	{
++		 DHD_ERROR(("%s: sscanf error. check period_msec value\n", __FUNCTION__));
++		 return -EINVAL;
++	}
++	DHD_ERROR(("%s: period_msec is %d\n", __FUNCTION__, period_msec));
++
++	memset(&mkeep_alive_pkt, 0, sizeof(wl_mkeep_alive_pkt_t));
++
++	mkeep_alive_pkt.period_msec = period_msec;
++	mkeep_alive_pkt.version = htod16(WL_MKEEP_ALIVE_VERSION);
++	mkeep_alive_pkt.length = htod16(WL_MKEEP_ALIVE_FIXED_LEN);
++
++	/* Setup keep alive zero for null packet generation */
++	mkeep_alive_pkt.keep_alive_id = 0;
++	mkeep_alive_pkt.len_bytes = 0;
++
++	buf = kmalloc(WLC_IOCTL_SMLEN, GFP_KERNEL);
++	if (!buf) {
++		DHD_ERROR(("%s: buffer alloc failed\n", __FUNCTION__));
++		return BCME_NOMEM;
++	}
++
++	ret = wldev_iovar_setbuf(dev, "mkeep_alive", (char *)&mkeep_alive_pkt,
++		WL_MKEEP_ALIVE_FIXED_LEN, buf, WLC_IOCTL_SMLEN, NULL);
++	if (ret < 0)
++		DHD_ERROR(("%s:keep_alive set failed:%d\n", __FUNCTION__, ret));
++	else
++		DHD_TRACE(("%s:keep_alive set ok\n", __FUNCTION__));
++	kfree(buf);
++	return ret;
++}
++
++static const char *
++get_string_by_separator(char *result, int result_len, const char *src, char separator)
++{
++	char *end = result + result_len - 1;
++	while ((result != end) && (*src != separator) && (*src)) {
++		*result++ = *src++;
++	}
++	*result = 0;
++	if (*src == separator) {
++		++src;
++	}
++	return src;
++}
++
++int
++wl_android_set_roam_offload_bssid_list(struct net_device *dev, const char *cmd)
++{
++	char sbuf[32];
++	int i, cnt, size, err, ioctl_buf_len;
++	roamoffl_bssid_list_t *bssid_list;
++	const char *str = cmd;
++	char *ioctl_buf;
++
++	str = get_string_by_separator(sbuf, 32, str, ',');
++	cnt = bcm_atoi(sbuf);
++	if (cnt < 0 || cnt >= MAX_ROAMOFFL_BSSID_NUM) {
++		WL_ERR(("BSSID List count (%d) invalid\n", cnt));
++		return -EINVAL;
++	}
++	size = sizeof(int32) + sizeof(struct ether_addr) * cnt;
++	WL_ERR(("ROAM OFFLOAD BSSID LIST %d BSSIDs, size %d\n", cnt, size));
++	bssid_list = kmalloc(size, GFP_KERNEL);
++	if (bssid_list == NULL) {
++		WL_ERR(("%s: memory alloc for bssid list(%d) failed\n",
++			__FUNCTION__, size));
++		return -ENOMEM;
++	}
++	ioctl_buf_len = size + 64;
++	ioctl_buf = kmalloc(ioctl_buf_len, GFP_KERNEL);
++	if (ioctl_buf == NULL) {
++		WL_ERR(("%s: memory alloc for ioctl_buf(%d) failed\n",
++			__FUNCTION__, ioctl_buf_len));
++		kfree(bssid_list);
++		return -ENOMEM;
++	}
++
++	for (i = 0; i < cnt; i++) {
++		str = get_string_by_separator(sbuf, 32, str, ',');
++		bcm_ether_atoe(sbuf, &bssid_list->bssid[i]);
++	}
++
++	bssid_list->cnt = (int32)cnt;
++	err = wldev_iovar_setbuf(dev, "roamoffl_bssid_list",
++			bssid_list, size, ioctl_buf, ioctl_buf_len, NULL);
++	kfree(bssid_list);
++	kfree(ioctl_buf);
++
++	return err;
++}
++
++#ifdef P2PRESP_WFDIE_SRC
++static int wl_android_get_wfdie_resp(struct net_device *dev, char *command, int total_len)
++{
++	int error = 0;
++	int bytes_written = 0;
++	int only_resp_wfdsrc = 0;
++
++	error = wldev_iovar_getint(dev, "p2p_only_resp_wfdsrc", &only_resp_wfdsrc);
++	if (error) {
++		DHD_ERROR(("%s: Failed to get the mode for only_resp_wfdsrc, error = %d\n",
++			__FUNCTION__, error));
++		return -1;
++	}
++
++	bytes_written = snprintf(command, total_len, "%s %d",
++		CMD_P2P_GET_WFDIE_RESP, only_resp_wfdsrc);
++
++	return bytes_written;
++}
++
++static int wl_android_set_wfdie_resp(struct net_device *dev, int only_resp_wfdsrc)
++{
++	int error = 0;
++
++	error = wldev_iovar_setint(dev, "p2p_only_resp_wfdsrc", only_resp_wfdsrc);
++	if (error) {
++		DHD_ERROR(("%s: Failed to set only_resp_wfdsrc %d, error = %d\n",
++			__FUNCTION__, only_resp_wfdsrc, error));
++		return -1;
++	}
++
++	return 0;
++}
++#endif /* P2PRESP_WFDIE_SRC */
++
++#ifdef BT_WIFI_HANDOVER
++static int
++wl_tbow_teardown(struct net_device *dev, char *command, int total_len)
++{
++	int err = BCME_OK;
++	char buf[WLC_IOCTL_SMLEN];
++	tbow_setup_netinfo_t netinfo;
++	memset(&netinfo, 0, sizeof(netinfo));
++	netinfo.opmode = TBOW_HO_MODE_TEARDOWN;
++
++	err = wldev_iovar_setbuf_bsscfg(dev, "tbow_doho", &netinfo,
++			sizeof(tbow_setup_netinfo_t), buf, WLC_IOCTL_SMLEN, 0, NULL);
++	if (err < 0) {
++		WL_ERR(("tbow_doho iovar error %d\n", err));
++			return err;
++	}
++	return err;
++}
++#endif /* BT_WIFI_HANOVER */
++
++#ifdef SET_RPS_CPUS
++static int
++wl_android_set_rps_cpus(struct net_device *dev, char *command, int total_len)
++{
++	int error, enable;
++
++	enable = command[strlen(CMD_RPSMODE) + 1] - '0';
++	error = dhd_rps_cpus_enable(dev, enable);
++
++#if defined(DHDTCPACK_SUPPRESS) && defined(BCMPCIE) && defined(WL_CFG80211)
++	if (!error) {
++		void *dhdp = wl_cfg80211_get_dhdp();
++		if (enable) {
++			DHD_TRACE(("%s : set ack suppress. TCPACK_SUP_HOLD.\n", __FUNCTION__));
++			dhd_tcpack_suppress_set(dhdp, TCPACK_SUP_HOLD);
++		} else {
++			DHD_TRACE(("%s : clear ack suppress.\n", __FUNCTION__));
++			dhd_tcpack_suppress_set(dhdp, TCPACK_SUP_OFF);
++		}
++	}
++#endif /* DHDTCPACK_SUPPRESS && BCMPCIE && WL_CFG80211 */
++
++	return error;
++}
++#endif /* SET_RPS_CPUS */
++int wl_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd)
++{
++#define PRIVATE_COMMAND_MAX_LEN	8192
++	int ret = 0;
++	char *command = NULL;
++	int bytes_written = 0;
++	android_wifi_priv_cmd priv_cmd;
++
++	net_os_wake_lock(net);
++
++	if (!ifr->ifr_data) {
++		ret = -EINVAL;
++		goto exit;
++	}
++
++#ifdef CONFIG_COMPAT
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
++	if (in_compat_syscall()) {
++#else
++	if (is_compat_task()) {
++#endif
++		compat_android_wifi_priv_cmd compat_priv_cmd;
++		if (copy_from_user(&compat_priv_cmd, ifr->ifr_data,
++			sizeof(compat_android_wifi_priv_cmd))) {
++			ret = -EFAULT;
++			goto exit;
++
++		}
++		priv_cmd.buf = compat_ptr(compat_priv_cmd.buf);
++		priv_cmd.used_len = compat_priv_cmd.used_len;
++		priv_cmd.total_len = compat_priv_cmd.total_len;
++	} else
++#endif /* CONFIG_COMPAT */
++	{
++		if (copy_from_user(&priv_cmd, ifr->ifr_data, sizeof(android_wifi_priv_cmd))) {
++			ret = -EFAULT;
++			goto exit;
++		}
++	}
++	if ((priv_cmd.total_len > PRIVATE_COMMAND_MAX_LEN) || (priv_cmd.total_len < 0)) {
++		DHD_ERROR(("%s: too long priavte command\n", __FUNCTION__));
++		ret = -EINVAL;
++		goto exit;
++	}
++	command = kmalloc((priv_cmd.total_len + 1), GFP_KERNEL);
++	if (!command)
++	{
++		DHD_ERROR(("%s: failed to allocate memory\n", __FUNCTION__));
++		ret = -ENOMEM;
++		goto exit;
++	}
++	if (copy_from_user(command, priv_cmd.buf, priv_cmd.total_len)) {
++		ret = -EFAULT;
++		goto exit;
++	}
++	command[priv_cmd.total_len] = '\0';
++
++	DHD_INFO(("%s: Android private cmd \"%s\" on %s\n", __FUNCTION__, command, ifr->ifr_name));
++
++	bytes_written = wl_handle_private_cmd(net, command, priv_cmd.total_len);
++	if (bytes_written >= 0) {
++		if ((bytes_written == 0) && (priv_cmd.total_len > 0)) {
++			command[0] = '\0';
++		}
++		if (bytes_written >= priv_cmd.total_len) {
++			DHD_ERROR(("%s: bytes_written = %d\n", __FUNCTION__, bytes_written));
++			bytes_written = priv_cmd.total_len;
++		} else {
++			bytes_written++;
++		}
++		priv_cmd.used_len = bytes_written;
++		if (copy_to_user(priv_cmd.buf, command, bytes_written)) {
++			DHD_ERROR(("%s: failed to copy data to user buffer\n", __FUNCTION__));
++			ret = -EFAULT;
++		}
++	}
++	else {
++		/* Propagate the error */
++		ret = bytes_written;
++	}
++
++exit:
++	net_os_wake_unlock(net);
++	if (command) {
++		kfree(command);
++	}
++
++	return ret;
++}
++
++int
++wl_handle_private_cmd(struct net_device *net, char *command, u32 cmd_len)
++{
++	int bytes_written = 0;
++	android_wifi_priv_cmd priv_cmd = {0};
++
++	priv_cmd.total_len = cmd_len;
++
++	if (strnicmp(command, CMD_START, strlen(CMD_START)) == 0) {
++		DHD_INFO(("%s, Received regular START command\n", __FUNCTION__));
++		bytes_written = wl_android_wifi_on(net);
++	}
++	else if (strnicmp(command, CMD_SETFWPATH, strlen(CMD_SETFWPATH)) == 0) {
++		bytes_written = wl_android_set_fwpath(net, command, priv_cmd.total_len);
++	}
++
++	if (!g_wifi_on) {
++		DHD_ERROR(("%s: Ignore private cmd \"%s\" - iface is down\n",
++			__FUNCTION__, command));
++		return 0;
++	}
++
++	if (strnicmp(command, CMD_STOP, strlen(CMD_STOP)) == 0) {
++		bytes_written = wl_android_wifi_off(net, FALSE);
++	}
++	else if (strnicmp(command, CMD_SCAN_ACTIVE, strlen(CMD_SCAN_ACTIVE)) == 0) {
++		wl_cfg80211_set_passive_scan(net, command);
++	}
++	else if (strnicmp(command, CMD_SCAN_PASSIVE, strlen(CMD_SCAN_PASSIVE)) == 0) {
++		wl_cfg80211_set_passive_scan(net, command);
++	}
++	else if (strnicmp(command, CMD_RSSI, strlen(CMD_RSSI)) == 0) {
++		bytes_written = wl_android_get_rssi(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_LINKSPEED, strlen(CMD_LINKSPEED)) == 0) {
++		bytes_written = wl_android_get_link_speed(net, command, priv_cmd.total_len);
++	}
++#ifdef PKT_FILTER_SUPPORT
++	else if (strnicmp(command, CMD_RXFILTER_START, strlen(CMD_RXFILTER_START)) == 0) {
++		bytes_written = net_os_enable_packet_filter(net, 1);
++	}
++	else if (strnicmp(command, CMD_RXFILTER_STOP, strlen(CMD_RXFILTER_STOP)) == 0) {
++		bytes_written = net_os_enable_packet_filter(net, 0);
++	}
++	else if (strnicmp(command, CMD_RXFILTER_ADD, strlen(CMD_RXFILTER_ADD)) == 0) {
++		int filter_num = *(command + strlen(CMD_RXFILTER_ADD) + 1) - '0';
++		bytes_written = net_os_rxfilter_add_remove(net, TRUE, filter_num);
++	}
++	else if (strnicmp(command, CMD_RXFILTER_REMOVE, strlen(CMD_RXFILTER_REMOVE)) == 0) {
++		int filter_num = *(command + strlen(CMD_RXFILTER_REMOVE) + 1) - '0';
++		bytes_written = net_os_rxfilter_add_remove(net, FALSE, filter_num);
++	}
++#endif /* PKT_FILTER_SUPPORT */
++	else if (strnicmp(command, CMD_BTCOEXSCAN_START, strlen(CMD_BTCOEXSCAN_START)) == 0) {
++		/* TBD: BTCOEXSCAN-START */
++	}
++	else if (strnicmp(command, CMD_BTCOEXSCAN_STOP, strlen(CMD_BTCOEXSCAN_STOP)) == 0) {
++		/* TBD: BTCOEXSCAN-STOP */
++	}
++	else if (strnicmp(command, CMD_BTCOEXMODE, strlen(CMD_BTCOEXMODE)) == 0) {
++#ifdef WL_CFG80211
++		void *dhdp = wl_cfg80211_get_dhdp();
++		bytes_written = wl_cfg80211_set_btcoex_dhcp(net, dhdp, command);
++#else
++#ifdef PKT_FILTER_SUPPORT
++		uint mode = *(command + strlen(CMD_BTCOEXMODE) + 1) - '0';
++
++		if (mode == 1)
++			net_os_enable_packet_filter(net, 0); /* DHCP starts */
++		else
++			net_os_enable_packet_filter(net, 1); /* DHCP ends */
++#endif /* PKT_FILTER_SUPPORT */
++#endif /* WL_CFG80211 */
++	}
++	else if (strnicmp(command, CMD_SETSUSPENDOPT, strlen(CMD_SETSUSPENDOPT)) == 0) {
++		bytes_written = wl_android_set_suspendopt(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_SETSUSPENDMODE, strlen(CMD_SETSUSPENDMODE)) == 0) {
++		bytes_written = wl_android_set_suspendmode(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_SETBAND, strlen(CMD_SETBAND)) == 0) {
++		uint band = *(command + strlen(CMD_SETBAND) + 1) - '0';
++		bytes_written = wldev_set_band(net, band);
++	}
++	else if (strnicmp(command, CMD_GETBAND, strlen(CMD_GETBAND)) == 0) {
++		bytes_written = wl_android_get_band(net, command, priv_cmd.total_len);
++	}
++#ifdef WL_CFG80211
++	/* CUSTOMER_SET_COUNTRY feature is define for only GGSM model */
++	else if (strnicmp(command, CMD_COUNTRY, strlen(CMD_COUNTRY)) == 0) {
++		/*
++		 * Usage examples:
++		 * DRIVER COUNTRY US
++		 * DRIVER COUNTRY US/7
++		 */
++		char *country_code = command + strlen(CMD_COUNTRY) + 1;
++		char *rev_info_delim = country_code + 2; /* 2 bytes of country code */
++		int revinfo = -1;
++		if ((rev_info_delim) &&
++			(strnicmp(rev_info_delim, CMD_COUNTRY_DELIMITER,
++			strlen(CMD_COUNTRY_DELIMITER)) == 0) &&
++			(rev_info_delim + 1)) {
++			revinfo  = bcm_atoi(rev_info_delim + 1);
++		}
++		bytes_written = wldev_set_country(net, country_code, true, true, revinfo);
++	}
++#endif /* WL_CFG80211 */
++	else if (strnicmp(command, CMD_SET_CSA, strlen(CMD_SET_CSA)) == 0) {
++		bytes_written = wl_android_set_csa(net, command, priv_cmd.total_len);
++	} else if (strnicmp(command, CMD_80211_MODE, strlen(CMD_80211_MODE)) == 0) {
++		bytes_written = wl_android_get_80211_mode(net, command, priv_cmd.total_len);
++	} else if (strnicmp(command, CMD_CHANSPEC, strlen(CMD_CHANSPEC)) == 0) {
++		bytes_written = wl_android_get_chanspec(net, command, priv_cmd.total_len);
++	} else if (strnicmp(command, CMD_DATARATE, strlen(CMD_DATARATE)) == 0) {
++		bytes_written = wl_android_get_datarate(net, command, priv_cmd.total_len);
++	} else if (strnicmp(command, CMD_ASSOC_CLIENTS,	strlen(CMD_ASSOC_CLIENTS)) == 0) {
++		bytes_written = wl_android_get_assoclist(net, command, priv_cmd.total_len);
++	}
++
++
++#ifdef PNO_SUPPORT
++	else if (strnicmp(command, CMD_PNOSSIDCLR_SET, strlen(CMD_PNOSSIDCLR_SET)) == 0) {
++		bytes_written = dhd_dev_pno_stop_for_ssid(net);
++	}
++#if !defined(WL_SCHED_SCAN) && defined(WL_WIRELESS_EXT)
++	else if (strnicmp(command, CMD_PNOSETUP_SET, strlen(CMD_PNOSETUP_SET)) == 0) {
++		bytes_written = wl_android_set_pno_setup(net, command, priv_cmd.total_len);
++	}
++#endif /* !WL_SCHED_SCAN && OEM_ANDROID && WL_WIRELESS_EXT */
++	else if (strnicmp(command, CMD_PNOENABLE_SET, strlen(CMD_PNOENABLE_SET)) == 0) {
++		int enable = *(command + strlen(CMD_PNOENABLE_SET) + 1) - '0';
++		bytes_written = (enable)? 0 : dhd_dev_pno_stop_for_ssid(net);
++	}
++	else if (strnicmp(command, CMD_WLS_BATCHING, strlen(CMD_WLS_BATCHING)) == 0) {
++		bytes_written = wls_parse_batching_cmd(net, command, priv_cmd.total_len);
++	}
++#endif /* PNO_SUPPORT */
++	else if (strnicmp(command, CMD_P2P_DEV_ADDR, strlen(CMD_P2P_DEV_ADDR)) == 0) {
++		bytes_written = wl_android_get_p2p_dev_addr(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_P2P_SET_NOA, strlen(CMD_P2P_SET_NOA)) == 0) {
++		int skip = strlen(CMD_P2P_SET_NOA) + 1;
++		bytes_written = wl_cfg80211_set_p2p_noa(net, command + skip,
++			priv_cmd.total_len - skip);
++	}
++#ifdef WL_NAN
++	else if (strnicmp(command, CMD_NAN, strlen(CMD_NAN)) == 0) {
++		bytes_written = wl_cfg80211_nan_cmd_handler(net, command,
++			priv_cmd.total_len);
++	}
++#endif /* WL_NAN */
++#if !defined WL_ENABLE_P2P_IF
++	else if (strnicmp(command, CMD_P2P_GET_NOA, strlen(CMD_P2P_GET_NOA)) == 0) {
++		bytes_written = wl_cfg80211_get_p2p_noa(net, command, priv_cmd.total_len);
++	}
++#endif /* WL_ENABLE_P2P_IF */
++	else if (strnicmp(command, CMD_P2P_SET_PS, strlen(CMD_P2P_SET_PS)) == 0) {
++		int skip = strlen(CMD_P2P_SET_PS) + 1;
++		bytes_written = wl_cfg80211_set_p2p_ps(net, command + skip,
++			priv_cmd.total_len - skip);
++	}
++	else if (strnicmp(command, CMD_P2P_ECSA, strlen(CMD_P2P_ECSA)) == 0) {
++		int skip = strlen(CMD_P2P_ECSA) + 1;
++		bytes_written = wl_cfg80211_set_p2p_ecsa(net, command + skip,
++			priv_cmd.total_len - skip);
++	}
++#ifdef WL_CFG80211
++	else if (strnicmp(command, CMD_SET_AP_WPS_P2P_IE,
++		strlen(CMD_SET_AP_WPS_P2P_IE)) == 0) {
++		int skip = strlen(CMD_SET_AP_WPS_P2P_IE) + 3;
++		bytes_written = wl_cfg80211_set_wps_p2p_ie(net, command + skip,
++			priv_cmd.total_len - skip, *(command + skip - 2) - '0');
++	}
++#ifdef WLFBT
++	else if (strnicmp(command, CMD_GET_FTKEY, strlen(CMD_GET_FTKEY)) == 0) {
++		wl_cfg80211_get_fbt_key(command);
++		bytes_written = FBT_KEYLEN;
++	}
++#endif /* WLFBT */
++#endif /* WL_CFG80211 */
++	else if (strnicmp(command, CMD_OKC_SET_PMK, strlen(CMD_OKC_SET_PMK)) == 0)
++		bytes_written = wl_android_set_pmk(net, command, priv_cmd.total_len);
++	else if (strnicmp(command, CMD_OKC_ENABLE, strlen(CMD_OKC_ENABLE)) == 0)
++		bytes_written = wl_android_okc_enable(net, command, priv_cmd.total_len);
++#if defined(WL_SUPPORT_AUTO_CHANNEL)
++	else if (strnicmp(command, CMD_GET_BEST_CHANNELS,
++		strlen(CMD_GET_BEST_CHANNELS)) == 0) {
++		bytes_written = wl_cfg80211_get_best_channels(net, command,
++			priv_cmd.total_len);
++	}
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++#if defined(WL_SUPPORT_AUTO_CHANNEL)
++	else if (strnicmp(command, CMD_SET_HAPD_AUTO_CHANNEL,
++		strlen(CMD_SET_HAPD_AUTO_CHANNEL)) == 0) {
++		int skip = strlen(CMD_SET_HAPD_AUTO_CHANNEL) + 1;
++		bytes_written = wl_android_set_auto_channel(net, (const char*)command+skip, command,
++			priv_cmd.total_len);
++	}
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++	else if (strnicmp(command, CMD_HAPD_MAC_FILTER, strlen(CMD_HAPD_MAC_FILTER)) == 0) {
++		int skip = strlen(CMD_HAPD_MAC_FILTER) + 1;
++		wl_android_set_mac_address_filter(net, (const char*)command+skip);
++	}
++	else if (strnicmp(command, CMD_SETROAMMODE, strlen(CMD_SETROAMMODE)) == 0)
++		bytes_written = wl_android_set_roam_mode(net, command, priv_cmd.total_len);
++#if defined(BCMFW_ROAM_ENABLE)
++	else if (strnicmp(command, CMD_SET_ROAMPREF, strlen(CMD_SET_ROAMPREF)) == 0) {
++		bytes_written = wl_android_set_roampref(net, command, priv_cmd.total_len);
++	}
++#endif /* BCMFW_ROAM_ENABLE */
++	else if (strnicmp(command, CMD_MIRACAST, strlen(CMD_MIRACAST)) == 0)
++		bytes_written = wl_android_set_miracast(net, command, priv_cmd.total_len);
++#ifdef WL11ULB
++	else if (strnicmp(command, CMD_ULB_MODE, strlen(CMD_ULB_MODE)) == 0)
++		bytes_written = wl_android_set_ulb_mode(net, command, priv_cmd.total_len);
++	else if (strnicmp(command, CMD_ULB_BW, strlen(CMD_ULB_BW)) == 0)
++		bytes_written = wl_android_set_ulb_bw(net, command, priv_cmd.total_len);
++#endif /* WL11ULB */
++	else if (strnicmp(command, CMD_SETIBSSBEACONOUIDATA, strlen(CMD_SETIBSSBEACONOUIDATA)) == 0)
++		bytes_written = wl_android_set_ibss_beacon_ouidata(net,
++		command, priv_cmd.total_len);
++	else if (strnicmp(command, CMD_KEEP_ALIVE, strlen(CMD_KEEP_ALIVE)) == 0) {
++		int skip = strlen(CMD_KEEP_ALIVE) + 1;
++		bytes_written = wl_keep_alive_set(net, command + skip, priv_cmd.total_len - skip);
++	}
++	else if (strnicmp(command, CMD_ROAM_OFFLOAD, strlen(CMD_ROAM_OFFLOAD)) == 0) {
++		int enable = *(command + strlen(CMD_ROAM_OFFLOAD) + 1) - '0';
++		bytes_written = wl_cfg80211_enable_roam_offload(net, enable);
++	}
++	else if (strnicmp(command, CMD_ROAM_OFFLOAD_APLIST, strlen(CMD_ROAM_OFFLOAD_APLIST)) == 0) {
++		bytes_written = wl_android_set_roam_offload_bssid_list(net,
++			command + strlen(CMD_ROAM_OFFLOAD_APLIST) + 1);
++	}
++#if defined(WL_VIRTUAL_APSTA)
++	else if (strnicmp(command, CMD_INTERFACE_CREATE, strlen(CMD_INTERFACE_CREATE)) == 0) {
++		char *name = (command + strlen(CMD_INTERFACE_CREATE) +1);
++		WL_INFORM(("Creating %s interface\n", name));
++		bytes_written = wl_cfg80211_interface_create(net, name);
++	}
++	else if (strnicmp(command, CMD_INTERFACE_DELETE, strlen(CMD_INTERFACE_DELETE)) == 0) {
++		char *name = (command + strlen(CMD_INTERFACE_DELETE) +1);
++		WL_INFORM(("Deleteing %s interface\n", name));
++		bytes_written = wl_cfg80211_interface_delete(net, name);
++	}
++#endif /* defined (WL_VIRTUAL_APSTA) */
++#ifdef P2PRESP_WFDIE_SRC
++	else if (strnicmp(command, CMD_P2P_SET_WFDIE_RESP,
++		strlen(CMD_P2P_SET_WFDIE_RESP)) == 0) {
++		int mode = *(command + strlen(CMD_P2P_SET_WFDIE_RESP) + 1) - '0';
++		bytes_written = wl_android_set_wfdie_resp(net, mode);
++	} else if (strnicmp(command, CMD_P2P_GET_WFDIE_RESP,
++		strlen(CMD_P2P_GET_WFDIE_RESP)) == 0) {
++		bytes_written = wl_android_get_wfdie_resp(net, command, priv_cmd.total_len);
++	}
++#endif /* P2PRESP_WFDIE_SRC */
++	else if (strnicmp(command, CMD_DFS_AP_MOVE, strlen(CMD_DFS_AP_MOVE)) == 0) {
++		char *data = (command + strlen(CMD_DFS_AP_MOVE) +1);
++		bytes_written = wl_cfg80211_dfs_ap_move(net, data, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_WBTEXT_ENABLE, strlen(CMD_WBTEXT_ENABLE)) == 0) {
++		bytes_written = wl_android_wbtext(net, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_WBTEXT_PROFILE_CONFIG,
++			strlen(CMD_WBTEXT_PROFILE_CONFIG)) == 0) {
++		char *data = (command + strlen(CMD_WBTEXT_PROFILE_CONFIG) + 1);
++		bytes_written = wl_cfg80211_wbtext_config(net, data, command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_WBTEXT_WEIGHT_CONFIG,
++			strlen(CMD_WBTEXT_WEIGHT_CONFIG)) == 0) {
++		char *data = (command + strlen(CMD_WBTEXT_WEIGHT_CONFIG) + 1);
++		bytes_written = wl_cfg80211_wbtext_weight_config(net, data,
++				command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_WBTEXT_TABLE_CONFIG,
++			strlen(CMD_WBTEXT_TABLE_CONFIG)) == 0) {
++		char *data = (command + strlen(CMD_WBTEXT_TABLE_CONFIG) + 1);
++		bytes_written = wl_cfg80211_wbtext_table_config(net, data,
++				command, priv_cmd.total_len);
++	}
++	else if (strnicmp(command, CMD_WBTEXT_DELTA_CONFIG,
++			strlen(CMD_WBTEXT_DELTA_CONFIG)) == 0) {
++		char *data = (command + strlen(CMD_WBTEXT_DELTA_CONFIG) + 1);
++		bytes_written = wl_cfg80211_wbtext_delta_config(net, data,
++				command, priv_cmd.total_len);
++	}
++#ifdef SET_RPS_CPUS
++	else if (strnicmp(command, CMD_RPSMODE, strlen(CMD_RPSMODE)) == 0) {
++		bytes_written = wl_android_set_rps_cpus(net, command, priv_cmd.total_len);
++	}
++#endif /* SET_RPS_CPUS */
++#ifdef WLWFDS
++	else if (strnicmp(command, CMD_ADD_WFDS_HASH, strlen(CMD_ADD_WFDS_HASH)) == 0) {
++		bytes_written = wl_android_set_wfds_hash(net, command, priv_cmd.total_len, 1);
++	}
++	else if (strnicmp(command, CMD_DEL_WFDS_HASH, strlen(CMD_DEL_WFDS_HASH)) == 0) {
++		bytes_written = wl_android_set_wfds_hash(net, command, priv_cmd.total_len, 0);
++	}
++#endif /* WLWFDS */
++#ifdef BT_WIFI_HANDOVER
++	else if (strnicmp(command, CMD_TBOW_TEARDOWN, strlen(CMD_TBOW_TEARDOWN)) == 0) {
++	    bytes_written = wl_tbow_teardown(net, command, priv_cmd.total_len);
++	}
++#endif /* BT_WIFI_HANDOVER */
++#ifdef CONNECTION_STATISTICS
++	else if (strnicmp(command, CMD_GET_CONNECTION_STATS,
++		strlen(CMD_GET_CONNECTION_STATS)) == 0) {
++		bytes_written = wl_android_get_connection_stats(net, command,
++			priv_cmd.total_len);
++	}
++#endif
++	else {
++		DHD_ERROR(("Unknown PRIVATE command %s - ignored\n", command));
++		snprintf(command, 5, "FAIL");
++		bytes_written = strlen("FAIL");
++	}
++
++	return bytes_written;
++}
++
++int wl_android_init(void)
++{
++	int ret = 0;
++
++#ifdef ENABLE_INSMOD_NO_FW_LOAD
++	dhd_download_fw_on_driverload = FALSE;
++#endif /* ENABLE_INSMOD_NO_FW_LOAD */
++	if (!iface_name[0]) {
++		memset(iface_name, 0, IFNAMSIZ);
++		bcm_strncpy_s(iface_name, IFNAMSIZ, "wlan", IFNAMSIZ);
++	}
++
++	wl_netlink_init();
++
++	return ret;
++}
++
++int wl_android_exit(void)
++{
++	int ret = 0;
++	struct io_cfg *cur, *q;
++
++	wl_netlink_deinit();
++
++	list_for_each_entry_safe(cur, q, &miracast_resume_list, list) {
++		list_del(&cur->list);
++		kfree(cur);
++	}
++
++	return ret;
++}
++
++void wl_android_post_init(void)
++{
++
++#ifdef ENABLE_4335BT_WAR
++	bcm_bt_unlock(lock_cookie_wifi);
++	printk("%s: btlock released\n", __FUNCTION__);
++#endif /* ENABLE_4335BT_WAR */
++
++	if (!dhd_download_fw_on_driverload)
++		g_wifi_on = FALSE;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_android.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_android.h
+new file mode 100644
+index 000000000..9be0146ef
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_android.h
+@@ -0,0 +1,94 @@
++/*
++ * Linux cfg80211 driver - Android related functions
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_android.h 587146 2015-09-18 03:50:09Z $
++ */
++
++#include <linux/module.h>
++#include <linux/netdevice.h>
++#include <wldev_common.h>
++
++/* If any feature uses the Generic Netlink Interface, put it here to enable WL_GENL
++ * automatically
++ */
++#if defined(BT_WIFI_HANDOVER) || defined(WL_NAN)
++#define WL_GENL
++#endif
++
++
++
++typedef struct _android_wifi_priv_cmd {
++    char *buf;
++    int used_len;
++    int total_len;
++} android_wifi_priv_cmd;
++
++#ifdef CONFIG_COMPAT
++typedef struct _compat_android_wifi_priv_cmd {
++    compat_caddr_t buf;
++    int used_len;
++    int total_len;
++} compat_android_wifi_priv_cmd;
++#endif /* CONFIG_COMPAT */
++
++/**
++ * Android platform dependent functions, feel free to add Android specific functions here
++ * (save the macros in dhd). Please do NOT declare functions that are NOT exposed to dhd
++ * or cfg, define them as static in wl_android.c
++ */
++
++/**
++ * wl_android_init will be called from module init function (dhd_module_init now), similarly
++ * wl_android_exit will be called from module exit function (dhd_module_cleanup now)
++ */
++int wl_android_init(void);
++int wl_android_exit(void);
++void wl_android_post_init(void);
++int wl_android_wifi_on(struct net_device *dev);
++int wl_android_wifi_off(struct net_device *dev, bool on_failure);
++int wl_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd);
++int wl_handle_private_cmd(struct net_device *net, char *command, u32 cmd_len);
++
++s32 wl_netlink_send_msg(int pid, int type, int seq, void *data, size_t size);
++
++/* hostap mac mode */
++#define MACLIST_MODE_DISABLED   0
++#define MACLIST_MODE_DENY       1
++#define MACLIST_MODE_ALLOW      2
++
++/* max number of assoc list */
++#define MAX_NUM_OF_ASSOCLIST    64
++
++/* Bandwidth */
++#define WL_CH_BANDWIDTH_20MHZ 20
++#define WL_CH_BANDWIDTH_40MHZ 40
++#define WL_CH_BANDWIDTH_80MHZ 80
++/* max number of mac filter list
++ * restrict max number to 10 as maximum cmd string size is 255
++ */
++#define MAX_NUM_MAC_FILT        10
++
++int wl_android_set_ap_mac_list(struct net_device *dev, int macmode, struct maclist *maclist);
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfg80211.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfg80211.c
+new file mode 100644
+index 000000000..2f42ccbf0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfg80211.c
+@@ -0,0 +1,16532 @@
++/*
++ * Linux cfg80211 driver
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfg80211.c 709616 2019-02-15 07:52:56Z $
++ */
++/* */
++#include <typedefs.h>
++#include <linuxver.h>
++#include <osl.h>
++#include <linux/kernel.h>
++
++#include <bcmutils.h>
++#include <bcmwifi_channels.h>
++#include <bcmendian.h>
++#include <proto/ethernet.h>
++#include <proto/802.11.h>
++#include <linux/if_arp.h>
++#include <asm/uaccess.h>
++
++#include <proto/ethernet.h>
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/netdevice.h>
++#include <linux/sched.h>
++#include <linux/etherdevice.h>
++#include <linux/wireless.h>
++#include <linux/ieee80211.h>
++#include <linux/wait.h>
++#include <net/cfg80211.h>
++#include <net/rtnetlink.h>
++
++#include <wlioctl.h>
++#include <wldev_common.h>
++#include <wl_cfg80211.h>
++#include <wl_cfgp2p.h>
++#include <wl_android.h>
++#include <bcmdevs.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_linux.h>
++#include <dhd_debug.h>
++#include <dhdioctl.h>
++#include <wlioctl.h>
++#include <dhd_cfg80211.h>
++#include <dhd_bus.h>
++#ifdef PNO_SUPPORT
++#include <dhd_pno.h>
++#endif /* PNO_SUPPORT */
++
++#if defined(WL_VENDOR_EXT_SUPPORT)
++#include <wl_cfgvendor.h>
++#endif /* defined(WL_VENDOR_EXT_SUPPORT) */
++
++#ifdef WL_NAN
++#include <wl_cfgnan.h>
++#endif /* WL_NAN */
++#ifdef PROP_TXSTATUS
++#include <dhd_wlfc.h>
++#endif
++
++#ifdef BCMPCIE
++#include <dhd_flowring.h>
++#endif
++
++#ifdef WL11U
++#if !defined(WL_ENABLE_P2P_IF) && !defined(WL_CFG80211_P2P_DEV_IF)
++#error You should enable 'WL_ENABLE_P2P_IF' or 'WL_CFG80211_P2P_DEV_IF' \
++	according to Kernel version and is supported only in Android-JB
++#endif /* !WL_ENABLE_P2P_IF && !WL_CFG80211_P2P_DEV_IF */
++#endif /* WL11U */
++
++
++#define IW_WSEC_ENABLED(wsec)   ((wsec) & (WEP_ENABLED | TKIP_ENABLED | AES_ENABLED))
++
++static struct device *cfg80211_parent_dev = NULL;
++/* g_bcm_cfg should be static. Do not change */
++static struct bcm_cfg80211 *g_bcm_cfg = NULL;
++u32 wl_dbg_level = WL_DBG_ERR;
++
++#define MAX_WAIT_TIME 1500
++#ifdef WLAIBSS_MCHAN
++#define IBSS_IF_NAME "ibss%d"
++#endif /* WLAIBSS_MCHAN */
++
++#ifdef VSDB
++/* sleep time to keep STA's connecting or connection for continuous af tx or finding a peer */
++#define DEFAULT_SLEEP_TIME_VSDB		120
++#define OFF_CHAN_TIME_THRESHOLD_MS	200
++#define AF_RETRY_DELAY_TIME			40
++
++/* if sta is connected or connecting, sleep for a while before retry af tx or finding a peer */
++#define WL_AF_TX_KEEP_PRI_CONNECTION_VSDB(cfg)	\
++	do {	\
++		if (wl_get_drv_status(cfg, CONNECTED, bcmcfg_to_prmry_ndev(cfg)) ||	\
++			wl_get_drv_status(cfg, CONNECTING, bcmcfg_to_prmry_ndev(cfg))) {	\
++			OSL_SLEEP(DEFAULT_SLEEP_TIME_VSDB);			\
++		}	\
++	} while (0)
++#else /* VSDB */
++/* if not VSDB, do nothing */
++#define WL_AF_TX_KEEP_PRI_CONNECTION_VSDB(cfg)
++#endif /* VSDB */
++
++#ifdef WL_CFG80211_SYNC_GON
++#define WL_DRV_STATUS_SENDING_AF_FRM_EXT(cfg) \
++	(wl_get_drv_status_all(cfg, SENDING_ACT_FRM) || \
++		wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM_LISTEN))
++#else
++#define WL_DRV_STATUS_SENDING_AF_FRM_EXT(cfg) wl_get_drv_status_all(cfg, SENDING_ACT_FRM)
++#endif /* WL_CFG80211_SYNC_GON */
++
++#define DNGL_FUNC(func, parameters) func parameters
++#define COEX_DHCP
++
++#define WLAN_EID_SSID	0
++#define CH_MIN_5G_CHANNEL 34
++#define CH_MIN_2G_CHANNEL 1
++#define ACTIVE_SCAN 1
++#define PASSIVE_SCAN 0
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++#define BCM_SET_LIST_FIRST_ENTRY(entry, ptr, type, member) \
++_Pragma("GCC diagnostic push") \
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"") \
++(entry) = list_first_entry((ptr), type, member); \
++_Pragma("GCC diagnostic pop") \
++
++#define BCM_SET_CONTAINER_OF(entry, ptr, type, member) \
++_Pragma("GCC diagnostic push") \
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"") \
++entry = container_of((ptr), type, member); \
++_Pragma("GCC diagnostic pop") \
++
++#else
++#define BCM_SET_LIST_FIRST_ENTRY(entry, ptr, type, member) \
++(entry) = list_first_entry((ptr), type, member); \
++
++#define BCM_SET_CONTAINER_OF(entry, ptr, type, member) \
++entry = container_of((ptr), type, member); \
++
++#endif /* STRICT_GCC_WARNINGS */
++
++enum rmc_event_type {
++	RMC_EVENT_NONE,
++	RMC_EVENT_LEADER_CHECK_FAIL
++};
++
++/* This is to override regulatory domains defined in cfg80211 module (reg.c)
++ * By default world regulatory domain defined in reg.c puts the flags NL80211_RRF_PASSIVE_SCAN
++ * and NL80211_RRF_NO_IBSS for 5GHz channels (for 36..48 and 149..165).
++ * With respect to these flags, wpa_supplicant doesn't start p2p operations on 5GHz channels.
++ * All the chnages in world regulatory domain are to be done here.
++ *
++ * this definition reuires disabling missing-field-initializer warning
++ * as the ieee80211_regdomain definition differs in plain linux and in Android
++ */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wmissing-field-initializers\"")
++#endif
++static const struct ieee80211_regdomain brcm_regdom = {
++	.n_reg_rules = 4,
++	.alpha2 =  "99",
++	.reg_rules = {
++		/* IEEE 802.11b/g, channels 1..11 */
++		REG_RULE(2412-10, 2472+10, 40, 6, 20, 0),
++		/* If any */
++		/* IEEE 802.11 channel 14 - Only JP enables
++		 * this and for 802.11b only
++		 */
++		REG_RULE(2484-10, 2484+10, 20, 6, 20, 0),
++		/* IEEE 802.11a, channel 36..64 */
++		REG_RULE(5150-10, 5350+10, 40, 6, 20, 0),
++		/* IEEE 802.11a, channel 100..165 */
++		REG_RULE(5470-10, 5850+10, 40, 6, 20, 0), }
++};
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) && \
++	(defined(WL_IFACE_COMB_NUM_CHANNELS) || defined(WL_CFG80211_P2P_DEV_IF))
++static const struct ieee80211_iface_limit common_if_limits[] = {
++	{
++	/*
++	 * Driver can support up to 2 AP's
++	 */
++	.max = 2,
++	.types = BIT(NL80211_IFTYPE_AP),
++	},
++	{
++	/*
++	 * During P2P-GO removal, P2P-GO is first changed to STA and later only
++	 * removed. So setting maximum possible number of STA interfaces according
++	 * to kernel version.
++	 *
++	 * less than linux-3.8 - max:3 (wlan0 + p2p0 + group removal of p2p-p2p0-x)
++	 * linux-3.8 and above - max:2 (wlan0 + group removal of p2p-wlan0-x)
++	 */
++#ifdef WL_ENABLE_P2P_IF
++	.max = 3,
++#else
++	.max = 2,
++#endif /* WL_ENABLE_P2P_IF */
++	.types = BIT(NL80211_IFTYPE_STATION),
++	},
++	{
++	.max = 2,
++	.types = BIT(NL80211_IFTYPE_P2P_GO) | BIT(NL80211_IFTYPE_P2P_CLIENT),
++	},
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	{
++	.max = 1,
++	.types = BIT(NL80211_IFTYPE_P2P_DEVICE),
++	},
++#endif /* WL_CFG80211_P2P_DEV_IF */
++	{
++	.max = 1,
++	.types = BIT(NL80211_IFTYPE_ADHOC),
++	},
++};
++#ifdef BCM4330_CHIP
++#define NUM_DIFF_CHANNELS 1
++#else
++#define NUM_DIFF_CHANNELS 2
++#endif
++static const struct ieee80211_iface_combination
++common_iface_combinations[] = {
++	{
++	.num_different_channels = NUM_DIFF_CHANNELS,
++	/*
++	 * max_interfaces = 4
++	 * The max no of interfaces will be used in dual p2p case.
++	 * {STA, P2P Device, P2P Group 1, P2P Group 2}. Though we
++	 * will not be using the STA functionality in this case, it
++	 * will remain registered as it is the primary interface.
++	 */
++	.max_interfaces = 4,
++	.limits = common_if_limits,
++	.n_limits = ARRAY_SIZE(common_if_limits),
++	},
++};
++#endif /* LINUX_VER >= 3.0 && (WL_IFACE_COMB_NUM_CHANNELS || WL_CFG80211_P2P_DEV_IF) */
++
++
++/* Data Element Definitions */
++#define WPS_ID_CONFIG_METHODS     0x1008
++#define WPS_ID_REQ_TYPE           0x103A
++#define WPS_ID_DEVICE_NAME        0x1011
++#define WPS_ID_VERSION            0x104A
++#define WPS_ID_DEVICE_PWD_ID      0x1012
++#define WPS_ID_REQ_DEV_TYPE       0x106A
++#define WPS_ID_SELECTED_REGISTRAR_CONFIG_METHODS 0x1053
++#define WPS_ID_PRIM_DEV_TYPE      0x1054
++
++/* Device Password ID */
++#define DEV_PW_DEFAULT 0x0000
++#define DEV_PW_USER_SPECIFIED 0x0001,
++#define DEV_PW_MACHINE_SPECIFIED 0x0002
++#define DEV_PW_REKEY 0x0003
++#define DEV_PW_PUSHBUTTON 0x0004
++#define DEV_PW_REGISTRAR_SPECIFIED 0x0005
++
++/* Config Methods */
++#define WPS_CONFIG_USBA 0x0001
++#define WPS_CONFIG_ETHERNET 0x0002
++#define WPS_CONFIG_LABEL 0x0004
++#define WPS_CONFIG_DISPLAY 0x0008
++#define WPS_CONFIG_EXT_NFC_TOKEN 0x0010
++#define WPS_CONFIG_INT_NFC_TOKEN 0x0020
++#define WPS_CONFIG_NFC_INTERFACE 0x0040
++#define WPS_CONFIG_PUSHBUTTON 0x0080
++#define WPS_CONFIG_KEYPAD 0x0100
++#define WPS_CONFIG_VIRT_PUSHBUTTON 0x0280
++#define WPS_CONFIG_PHY_PUSHBUTTON 0x0480
++#define WPS_CONFIG_VIRT_DISPLAY 0x2008
++#define WPS_CONFIG_PHY_DISPLAY 0x4008
++
++#define PM_BLOCK 1
++#define PM_ENABLE 0
++
++
++#define WL_AKM_SUITE_SHA256_1X  0x000FAC05
++#define WL_AKM_SUITE_SHA256_PSK 0x000FAC06
++
++#ifndef IBSS_COALESCE_ALLOWED
++#define IBSS_COALESCE_ALLOWED 0
++#endif
++
++#ifndef IBSS_INITIAL_SCAN_ALLOWED
++#define IBSS_INITIAL_SCAN_ALLOWED 0
++#endif
++
++
++#define CUSTOM_RETRY_MASK 0xff000000 /* Mask for retry counter of custom dwell time */
++#define LONG_LISTEN_TIME 2000
++/*
++ * cfg80211_ops api/callback list
++ */
++static s32 wl_frame_get_mgmt(u16 fc, const struct ether_addr *da,
++	const struct ether_addr *sa, const struct ether_addr *bssid,
++	u8 **pheader, u32 *body_len, u8 *pbody);
++static s32 __wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
++	struct cfg80211_scan_request *request,
++	struct cfg80211_ssid *this_ssid);
++#if defined(WL_CFG80211_P2P_DEV_IF)
++static s32
++wl_cfg80211_scan(struct wiphy *wiphy, struct cfg80211_scan_request *request);
++#else
++static s32
++wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
++	struct cfg80211_scan_request *request);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++static s32 wl_cfg80211_set_wiphy_params(struct wiphy *wiphy, u32 changed);
++#ifdef WLAIBSS_MCHAN
++static bcm_struct_cfgdev* bcm_cfg80211_add_ibss_if(struct wiphy *wiphy, char *name);
++static s32 bcm_cfg80211_del_ibss_if(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev);
++#endif /* WLAIBSS_MCHAN */
++static s32 wl_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_ibss_params *params);
++static s32 wl_cfg80211_leave_ibss(struct wiphy *wiphy,
++	struct net_device *dev);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++static s32 wl_cfg80211_get_station(struct wiphy *wiphy,
++	struct net_device *dev, const u8 *mac,
++	struct station_info *sinfo);
++#else
++static s32 wl_cfg80211_get_station(struct wiphy *wiphy,
++	struct net_device *dev, u8 *mac,
++	struct station_info *sinfo);
++#endif
++static s32 wl_cfg80211_set_power_mgmt(struct wiphy *wiphy,
++	struct net_device *dev, bool enabled,
++	s32 timeout);
++static int wl_cfg80211_connect(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_connect_params *sme);
++static s32 wl_cfg80211_disconnect(struct wiphy *wiphy, struct net_device *dev,
++	u16 reason_code);
++#if defined(WL_CFG80211_P2P_DEV_IF)
++static s32
++wl_cfg80211_set_tx_power(struct wiphy *wiphy, struct wireless_dev *wdev,
++	enum nl80211_tx_power_setting type, s32 mbm);
++#else
++static s32
++wl_cfg80211_set_tx_power(struct wiphy *wiphy,
++	enum nl80211_tx_power_setting type, s32 dbm);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++#if defined(WL_CFG80211_P2P_DEV_IF)
++static s32 wl_cfg80211_get_tx_power(struct wiphy *wiphy,
++	struct wireless_dev *wdev, s32 *dbm);
++#else
++static s32 wl_cfg80211_get_tx_power(struct wiphy *wiphy, s32 *dbm);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++static s32 wl_cfg80211_config_default_key(struct wiphy *wiphy,
++	struct net_device *dev,
++	u8 key_idx, bool unicast, bool multicast);
++static s32 wl_cfg80211_add_key(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, bool pairwise, const u8 *mac_addr,
++	struct key_params *params);
++static s32 wl_cfg80211_del_key(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, bool pairwise, const u8 *mac_addr);
++static s32 wl_cfg80211_get_key(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, bool pairwise, const u8 *mac_addr,
++	void *cookie, void (*callback) (void *cookie,
++	struct key_params *params));
++static s32 wl_cfg80211_config_default_mgmt_key(struct wiphy *wiphy,
++	struct net_device *dev,	u8 key_idx);
++static s32 wl_cfg80211_resume(struct wiphy *wiphy);
++#if defined(WL_SUPPORT_BACKPORTED_KPATCHES) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, \
++	2, 0))
++static s32 wl_cfg80211_mgmt_tx_cancel_wait(struct wiphy *wiphy,
++	bcm_struct_cfgdev *cfgdev, u64 cookie);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++static s32 wl_cfg80211_del_station(
++		struct wiphy *wiphy, struct net_device *ndev,
++		struct station_del_parameters *params);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++static s32 wl_cfg80211_del_station(struct wiphy *wiphy,
++	struct net_device *ndev, const u8* mac_addr);
++#else
++static s32 wl_cfg80211_del_station(struct wiphy *wiphy,
++	struct net_device *ndev, u8* mac_addr);
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++static s32 wl_cfg80211_change_station(struct wiphy *wiphy,
++	struct net_device *dev, const u8 *mac, struct station_parameters *params);
++#else
++static s32 wl_cfg80211_change_station(struct wiphy *wiphy,
++	struct net_device *dev, u8 *mac, struct station_parameters *params);
++#endif
++#endif /* WL_SUPPORT_BACKPORTED_KPATCHES || KERNEL_VER >= KERNEL_VERSION(3, 2, 0)) */
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39))
++static s32 wl_cfg80211_suspend(struct wiphy *wiphy, struct cfg80211_wowlan *wow);
++#else
++static s32 wl_cfg80211_suspend(struct wiphy *wiphy);
++#endif
++static s32 wl_cfg80211_set_pmksa(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_pmksa *pmksa);
++static s32 wl_cfg80211_del_pmksa(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_pmksa *pmksa);
++static s32 wl_cfg80211_flush_pmksa(struct wiphy *wiphy,
++	struct net_device *dev);
++static void wl_cfg80211_scan_abort(struct bcm_cfg80211 *cfg);
++static void wl_cfg80211_cancel_scan(struct bcm_cfg80211 *cfg);
++static s32 wl_notify_escan_complete(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev, bool aborted, bool fw_abort);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++#if (defined(CONFIG_ARCH_MSM) && defined(TDLS_MGMT_VERSION2)) || (LINUX_VERSION_CODE < \
++	KERNEL_VERSION(3, 16, 0) && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))
++static s32 wl_cfg80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev,
++	u8 *peer, u8 action_code, u8 dialog_token, u16 status_code,
++	u32 peer_capability, const u8 *data, size_t len);
++#elif ((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) && \
++		(LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0)))
++static s32 wl_cfg80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev,
++	const u8 *peer, u8 action_code, u8 dialog_token, u16 status_code,
++	u32 peer_capability, const u8 *data, size_t len);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
++static s32 wl_cfg80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev,
++	const u8 *peer, u8 action_code, u8 dialog_token, u16 status_code,
++	u32 peer_capability, bool initiator, const u8 *data, size_t len);
++#else
++static s32 wl_cfg80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev,
++	u8 *peer, u8 action_code, u8 dialog_token, u16 status_code, const u8 *data,
++	size_t len);
++#endif /* CONFIG_ARCH_MSM && TDLS_MGMT_VERSION2 */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++static s32 wl_cfg80211_tdls_oper(struct wiphy *wiphy, struct net_device *dev,
++	const u8 *peer, enum nl80211_tdls_operation oper);
++#else
++static s32 wl_cfg80211_tdls_oper(struct wiphy *wiphy, struct net_device *dev,
++	u8 *peer, enum nl80211_tdls_operation oper);
++#endif
++#endif 
++#ifdef WL_SCHED_SCAN
++static int wl_cfg80211_sched_scan_stop(struct wiphy *wiphy, struct net_device *dev);
++#endif
++#if defined(WL_VIRTUAL_APSTA) || defined(DUAL_STA_STATIC_IF)
++bcm_struct_cfgdev*
++wl_cfg80211_create_iface(struct wiphy *wiphy, enum nl80211_iftype
++		 iface_type, u8 *mac_addr, const char *name);
++s32
++wl_cfg80211_del_iface(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev);
++#endif /* defined(WL_VIRTUAL_APSTA) || defined(DUAL_STA_STATIC_IF) */
++
++s32 wl_cfg80211_interface_ops(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev, s32 bsscfg_idx,
++	enum nl80211_iftype iface_type, s32 del, u8 *addr);
++s32 wl_cfg80211_add_del_bss(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev, s32 bsscfg_idx,
++	enum nl80211_iftype iface_type, s32 del, u8 *addr);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
++static s32 wl_cfg80211_set_rekey_data(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_gtk_rekey_data *data);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0) */
++chanspec_t wl_chspec_driver_to_host(chanspec_t chanspec);
++chanspec_t wl_chspec_host_to_driver(chanspec_t chanspec);
++#ifdef WL11ULB
++static s32 wl_cfg80211_get_ulb_bw(struct wireless_dev *wdev);
++static chanspec_t wl_cfg80211_ulb_get_min_bw_chspec(struct wireless_dev *wdev, s32 bssidx);
++static s32 wl_cfg80211_ulbbw_to_ulbchspec(u32 ulb_bw);
++#else
++static inline chanspec_t wl_cfg80211_ulb_get_min_bw_chspec(
++		struct wireless_dev *wdev, s32 bssidx)
++{
++	return WL_CHANSPEC_BW_20;
++}
++#endif /* WL11ULB */
++
++/*
++ * event & event Q handlers for cfg80211 interfaces
++ */
++static s32 wl_create_event_handler(struct bcm_cfg80211 *cfg);
++static void wl_destroy_event_handler(struct bcm_cfg80211 *cfg);
++static s32 wl_event_handler(void *data);
++static void wl_init_eq(struct bcm_cfg80211 *cfg);
++static void wl_flush_eq(struct bcm_cfg80211 *cfg);
++static unsigned long wl_lock_eq(struct bcm_cfg80211 *cfg);
++static void wl_unlock_eq(struct bcm_cfg80211 *cfg, unsigned long flags);
++static void wl_init_eq_lock(struct bcm_cfg80211 *cfg);
++static void wl_init_event_handler(struct bcm_cfg80211 *cfg);
++static struct wl_event_q *wl_deq_event(struct bcm_cfg80211 *cfg);
++static s32 wl_enq_event(struct bcm_cfg80211 *cfg, struct net_device *ndev, u32 type,
++	const wl_event_msg_t *msg, void *data);
++static void wl_put_event(struct wl_event_q *e);
++static void wl_wakeup_event(struct bcm_cfg80211 *cfg);
++static s32 wl_notify_connect_status_ap(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data);
++static s32 wl_notify_connect_status(struct bcm_cfg80211 *cfg,
++	bcm_struct_cfgdev *cfgdev, const wl_event_msg_t *e, void *data);
++static s32 wl_notify_roaming_status(struct bcm_cfg80211 *cfg,
++	bcm_struct_cfgdev *cfgdev, const wl_event_msg_t *e, void *data);
++static s32 wl_notify_scan_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++static s32 wl_bss_connect_done(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data, bool completed);
++static s32 wl_bss_roaming_done(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data);
++static s32 wl_notify_mic_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++#ifdef BT_WIFI_HANDOVER
++static s32 wl_notify_bt_wifi_handover_req(struct bcm_cfg80211 *cfg,
++	bcm_struct_cfgdev *cfgdev, const wl_event_msg_t *e, void *data);
++#endif /* BT_WIFI_HANDOVER */
++#ifdef WL_SCHED_SCAN
++static s32
++wl_notify_sched_scan_results(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data);
++#endif /* WL_SCHED_SCAN */
++#ifdef PNO_SUPPORT
++static s32 wl_notify_pfn_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++#endif /* PNO_SUPPORT */
++#ifdef GSCAN_SUPPORT
++static s32 wl_notify_gscan_event(struct bcm_cfg80211 *wl, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++static s32 wl_handle_roam_exp_event(struct bcm_cfg80211 *wl, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++#endif /* GSCAN_SUPPORT */
++static s32 wl_handle_rssi_monitor_event(struct bcm_cfg80211 *wl, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++static s32 wl_notifier_change_state(struct bcm_cfg80211 *cfg, struct net_info *_net_info,
++	enum wl_status state, bool set);
++#ifdef DHD_LOSSLESS_ROAMING
++static s32 wl_notify_roam_prep_status(struct bcm_cfg80211 *cfg,
++	bcm_struct_cfgdev *cfgdev, const wl_event_msg_t *e, void *data);
++static void wl_del_roam_timeout(struct bcm_cfg80211 *cfg);
++#endif /* DHD_LOSSLESS_ROAMING */
++
++#ifdef WLTDLS
++static s32 wl_tdls_event_handler(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++#endif /* WLTDLS */
++/*
++ * register/deregister parent device
++ */
++static void wl_cfg80211_clear_parent_dev(void);
++/*
++ * ioctl utilites
++ */
++
++/*
++ * cfg80211 set_wiphy_params utilities
++ */
++static s32 wl_set_frag(struct net_device *dev, u32 frag_threshold);
++static s32 wl_set_rts(struct net_device *dev, u32 frag_threshold);
++static s32 wl_set_retry(struct net_device *dev, u32 retry, bool l);
++
++/*
++ * cfg profile utilities
++ */
++static s32 wl_update_prof(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, const void *data, s32 item);
++static void *wl_read_prof(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 item);
++static void wl_init_prof(struct bcm_cfg80211 *cfg, struct net_device *ndev);
++
++/*
++ * cfg80211 connect utilites
++ */
++static s32 wl_set_wpa_version(struct net_device *dev,
++	struct cfg80211_connect_params *sme);
++static s32 wl_set_auth_type(struct net_device *dev,
++	struct cfg80211_connect_params *sme);
++static s32 wl_set_set_cipher(struct net_device *dev,
++	struct cfg80211_connect_params *sme);
++static s32 wl_set_key_mgmt(struct net_device *dev,
++	struct cfg80211_connect_params *sme);
++static s32 wl_set_set_sharedkey(struct net_device *dev,
++	struct cfg80211_connect_params *sme);
++static s32 wl_get_assoc_ies(struct bcm_cfg80211 *cfg, struct net_device *ndev);
++static s32 wl_ch_to_chanspec(struct net_device *dev, int ch,
++	struct wl_join_params *join_params, size_t *join_params_size);
++void wl_cfg80211_clear_security(struct bcm_cfg80211 *cfg);
++
++/*
++ * information element utilities
++ */
++static void wl_rst_ie(struct bcm_cfg80211 *cfg);
++static __used s32 wl_add_ie(struct bcm_cfg80211 *cfg, u8 t, u8 l, u8 *v);
++static void wl_update_hidden_ap_ie(struct wl_bss_info *bi, const u8 *ie_stream, u32 *ie_size,
++	bool roam);
++static s32 wl_mrg_ie(struct bcm_cfg80211 *cfg, u8 *ie_stream, u16 ie_size);
++static s32 wl_cp_ie(struct bcm_cfg80211 *cfg, u8 *dst, u16 dst_size);
++static u32 wl_get_ielen(struct bcm_cfg80211 *cfg);
++#ifdef MFP
++static int wl_cfg80211_get_rsn_capa(bcm_tlv_t *wpa2ie, u8* capa);
++#endif
++
++#ifdef WL11U
++bcm_tlv_t *
++wl_cfg80211_find_interworking_ie(u8 *parse, u32 len);
++static s32
++wl_cfg80211_add_iw_ie(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 bssidx, s32 pktflag,
++            uint8 ie_id, uint8 *data, uint8 data_len);
++#endif /* WL11U */
++
++static s32 wl_setup_wiphy(struct wireless_dev *wdev, struct device *dev, void *data);
++static void wl_free_wdev(struct bcm_cfg80211 *cfg);
++#ifdef CONFIG_CFG80211_INTERNAL_REGDB
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
++static int
++#else
++static void
++#endif /* kernel version < 3.10.11 */
++wl_cfg80211_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request);
++#endif /* CONFIG_CFG80211_INTERNAL_REGDB */
++
++static s32 wl_inform_bss(struct bcm_cfg80211 *cfg);
++static s32 wl_inform_single_bss(struct bcm_cfg80211 *cfg, struct wl_bss_info *bi, bool roam);
++static s32 wl_update_bss_info(struct bcm_cfg80211 *cfg, struct net_device *ndev, bool roam);
++static chanspec_t wl_cfg80211_get_shared_freq(struct wiphy *wiphy);
++s32 wl_cfg80211_channel_to_freq(u32 channel);
++
++
++static void wl_cfg80211_work_handler(struct work_struct *work);
++static s32 wl_add_keyext(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, const u8 *mac_addr,
++	struct key_params *params);
++/*
++ * key indianess swap utilities
++ */
++static void swap_key_from_BE(struct wl_wsec_key *key);
++static void swap_key_to_BE(struct wl_wsec_key *key);
++
++/*
++ * bcm_cfg80211 memory init/deinit utilities
++ */
++static s32 wl_init_priv_mem(struct bcm_cfg80211 *cfg);
++static void wl_deinit_priv_mem(struct bcm_cfg80211 *cfg);
++
++static void wl_delay(u32 ms);
++
++/*
++ * ibss mode utilities
++ */
++static bool wl_is_ibssmode(struct bcm_cfg80211 *cfg, struct net_device *ndev);
++static __used bool wl_is_ibssstarter(struct bcm_cfg80211 *cfg);
++
++/*
++ * link up/down , default configuration utilities
++ */
++static s32 __wl_cfg80211_up(struct bcm_cfg80211 *cfg);
++static s32 __wl_cfg80211_down(struct bcm_cfg80211 *cfg);
++static bool wl_is_linkdown(struct bcm_cfg80211 *cfg, const wl_event_msg_t *e);
++static bool wl_is_linkup(struct bcm_cfg80211 *cfg, const wl_event_msg_t *e,
++	struct net_device *ndev);
++static bool wl_is_nonetwork(struct bcm_cfg80211 *cfg, const wl_event_msg_t *e);
++static void wl_link_up(struct bcm_cfg80211 *cfg);
++static void wl_link_down(struct bcm_cfg80211 *cfg);
++static s32 wl_config_ifmode(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 iftype);
++static void wl_init_conf(struct wl_conf *conf);
++static s32 wl_cfg80211_handle_ifdel(struct bcm_cfg80211 *cfg, wl_if_event_info *if_event_info,
++	struct net_device* ndev);
++
++int wl_cfg80211_get_ioctl_version(void);
++
++/*
++ * find most significant bit set
++ */
++static __used u32 wl_find_msb(u16 bit16);
++
++/*
++ * rfkill support
++ */
++static int wl_setup_rfkill(struct bcm_cfg80211 *cfg, bool setup);
++static int wl_rfkill_set(void *data, bool blocked);
++#ifdef DEBUGFS_CFG80211
++static s32 wl_setup_debugfs(struct bcm_cfg80211 *cfg);
++static s32 wl_free_debugfs(struct bcm_cfg80211 *cfg);
++#endif
++
++static wl_scan_params_t *wl_cfg80211_scan_alloc_params(int channel,
++	int nprobes, int *out_params_size);
++static bool check_dev_role_integrity(struct bcm_cfg80211 *cfg, u32 dev_role);
++
++#ifdef WL_CFG80211_ACL
++/* ACL */
++static int wl_cfg80211_set_mac_acl(struct wiphy *wiphy, struct net_device *cfgdev,
++	const struct cfg80211_acl_data *acl);
++#endif /* WL_CFG80211_ACL */
++
++/*
++ * Some external functions, TODO: move them to dhd_linux.h
++ */
++int dhd_add_monitor(char *name, struct net_device **new_ndev);
++int dhd_del_monitor(struct net_device *ndev);
++int dhd_monitor_init(void *dhd_pub);
++int dhd_monitor_uninit(void);
++int dhd_start_xmit(struct sk_buff *skb, struct net_device *net);
++#ifdef BCMSDIO
++extern uint16 dhd_get_chipid(dhd_pub_t * dhd);
++#endif
++
++
++static int wl_cfg80211_delayed_roam(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const struct ether_addr *bssid);
++
++static int bw2cap[] = { 0, 0, WLC_BW_CAP_20MHZ, WLC_BW_CAP_40MHZ, WLC_BW_CAP_80MHZ,
++	WLC_BW_CAP_160MHZ, WLC_BW_CAP_160MHZ };
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0))
++#define CFG80211_DISCONNECTED(dev, reason, ie, len, loc_gen, gfp) \
++	cfg80211_disconnected(dev, reason, ie, len, gfp);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0))
++#define CFG80211_DISCONNECTED(dev, reason, ie, len, loc_gen, gfp) \
++	cfg80211_disconnected(dev, reason, ie, len, loc_gen, gfp);
++#endif
++
++#ifdef RSSI_OFFSET
++static s32 wl_rssi_offset(s32 rssi)
++{
++	rssi += RSSI_OFFSET;
++	if (rssi > 0)
++		rssi = 0;
++	return rssi;
++}
++#else
++#define wl_rssi_offset(x)	x
++#endif
++
++#define IS_WPA_AKM(akm) ((akm) == RSN_AKM_NONE || 			\
++				 (akm) == RSN_AKM_UNSPECIFIED || 	\
++				 (akm) == RSN_AKM_PSK)
++
++
++extern int dhd_wait_pend8021x(struct net_device *dev);
++#ifdef PROP_TXSTATUS_VSDB
++extern int disable_proptx;
++#endif /* PROP_TXSTATUS_VSDB */
++
++
++extern int passive_channel_skip;
++
++static s32
++wl_csa_complete_ind(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++#if ((LINUX_VERSION_CODE >= KERNEL_VERSION (3, 5, 0)) && (LINUX_VERSION_CODE <= (3, 7, \
++	0)))
++struct chan_info {
++	int freq;
++	int chan_type;
++};
++#endif
++
++
++#if (WL_DBG_LEVEL > 0)
++#define WL_DBG_ESTR_MAX	50
++static s8 wl_dbg_estr[][WL_DBG_ESTR_MAX] = {
++	"SET_SSID", "JOIN", "START", "AUTH", "AUTH_IND",
++	"DEAUTH", "DEAUTH_IND", "ASSOC", "ASSOC_IND", "REASSOC",
++	"REASSOC_IND", "DISASSOC", "DISASSOC_IND", "QUIET_START", "QUIET_END",
++	"BEACON_RX", "LINK", "MIC_ERROR", "NDIS_LINK", "ROAM",
++	"TXFAIL", "PMKID_CACHE", "RETROGRADE_TSF", "PRUNE", "AUTOAUTH",
++	"EAPOL_MSG", "SCAN_COMPLETE", "ADDTS_IND", "DELTS_IND", "BCNSENT_IND",
++	"BCNRX_MSG", "BCNLOST_MSG", "ROAM_PREP", "PFN_NET_FOUND",
++	"PFN_NET_LOST",
++	"RESET_COMPLETE", "JOIN_START", "ROAM_START", "ASSOC_START",
++	"IBSS_ASSOC",
++	"RADIO", "PSM_WATCHDOG", "WLC_E_CCX_ASSOC_START", "WLC_E_CCX_ASSOC_ABORT",
++	"PROBREQ_MSG",
++	"SCAN_CONFIRM_IND", "PSK_SUP", "COUNTRY_CODE_CHANGED",
++	"EXCEEDED_MEDIUM_TIME", "ICV_ERROR",
++	"UNICAST_DECODE_ERROR", "MULTICAST_DECODE_ERROR", "TRACE",
++	"WLC_E_BTA_HCI_EVENT", "IF", "WLC_E_P2P_DISC_LISTEN_COMPLETE",
++	"RSSI", "PFN_SCAN_COMPLETE", "WLC_E_EXTLOG_MSG",
++	"ACTION_FRAME", "ACTION_FRAME_COMPLETE", "WLC_E_PRE_ASSOC_IND",
++	"WLC_E_PRE_REASSOC_IND", "WLC_E_CHANNEL_ADOPTED", "WLC_E_AP_STARTED",
++	"WLC_E_DFS_AP_STOP", "WLC_E_DFS_AP_RESUME", "WLC_E_WAI_STA_EVENT",
++	"WLC_E_WAI_MSG", "WLC_E_ESCAN_RESULT", "WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE",
++	"WLC_E_PROBRESP_MSG", "WLC_E_P2P_PROBREQ_MSG", "WLC_E_DCS_REQUEST", "WLC_E_FIFO_CREDIT_MAP",
++	"WLC_E_ACTION_FRAME_RX", "WLC_E_WAKE_EVENT", "WLC_E_RM_COMPLETE"
++};
++#endif				/* WL_DBG_LEVEL */
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0))
++#define CHAN2G(_channel, _freq, _flags) {			\
++	.band			= IEEE80211_BAND_2GHZ,		\
++	.center_freq		= (_freq),			\
++	.hw_value		= (_channel),			\
++	.flags			= (_flags),			\
++	.max_antenna_gain	= 0,				\
++	.max_power		= 30,				\
++}
++
++#define CHAN5G(_channel, _flags) {				\
++	.band			= IEEE80211_BAND_5GHZ,		\
++	.center_freq		= 5000 + (5 * (_channel)),	\
++	.hw_value		= (_channel),			\
++	.flags			= (_flags),			\
++	.max_antenna_gain	= 0,				\
++	.max_power		= 30,				\
++}
++#else
++#define CHAN2G(_channel, _freq, _flags) {			\
++	.band			= NL80211_BAND_2GHZ,		\
++	.center_freq		= (_freq),			\
++	.hw_value		= (_channel),			\
++	.flags			= (_flags),			\
++	.max_antenna_gain	= 0,				\
++	.max_power		= 30,				\
++}
++
++#define CHAN5G(_channel, _flags) {				\
++	.band			= NL80211_BAND_5GHZ,		\
++	.center_freq		= 5000 + (5 * (_channel)),	\
++	.hw_value		= (_channel),			\
++	.flags			= (_flags),			\
++	.max_antenna_gain	= 0,				\
++	.max_power		= 30,				\
++}
++#endif /* if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0) */
++
++#define RATE_TO_BASE100KBPS(rate)   (((rate) * 10) / 2)
++#define RATETAB_ENT(_rateid, _flags) \
++	{								\
++		.bitrate	= RATE_TO_BASE100KBPS(_rateid),     \
++		.hw_value	= (_rateid),			    \
++		.flags	  = (_flags),			     \
++	}
++
++static struct ieee80211_rate __wl_rates[] = {
++	RATETAB_ENT(DOT11_RATE_1M, 0),
++	RATETAB_ENT(DOT11_RATE_2M, IEEE80211_RATE_SHORT_PREAMBLE),
++	RATETAB_ENT(DOT11_RATE_5M5, IEEE80211_RATE_SHORT_PREAMBLE),
++	RATETAB_ENT(DOT11_RATE_11M, IEEE80211_RATE_SHORT_PREAMBLE),
++	RATETAB_ENT(DOT11_RATE_6M, 0),
++	RATETAB_ENT(DOT11_RATE_9M, 0),
++	RATETAB_ENT(DOT11_RATE_12M, 0),
++	RATETAB_ENT(DOT11_RATE_18M, 0),
++	RATETAB_ENT(DOT11_RATE_24M, 0),
++	RATETAB_ENT(DOT11_RATE_36M, 0),
++	RATETAB_ENT(DOT11_RATE_48M, 0),
++	RATETAB_ENT(DOT11_RATE_54M, 0)
++};
++
++#define wl_a_rates		(__wl_rates + 4)
++#define wl_a_rates_size	8
++#define wl_g_rates		(__wl_rates + 0)
++#define wl_g_rates_size	12
++
++static struct ieee80211_channel __wl_2ghz_channels[] = {
++	CHAN2G(1, 2412, 0),
++	CHAN2G(2, 2417, 0),
++	CHAN2G(3, 2422, 0),
++	CHAN2G(4, 2427, 0),
++	CHAN2G(5, 2432, 0),
++	CHAN2G(6, 2437, 0),
++	CHAN2G(7, 2442, 0),
++	CHAN2G(8, 2447, 0),
++	CHAN2G(9, 2452, 0),
++	CHAN2G(10, 2457, 0),
++	CHAN2G(11, 2462, 0),
++	CHAN2G(12, 2467, 0),
++	CHAN2G(13, 2472, 0),
++	CHAN2G(14, 2484, 0)
++};
++
++static struct ieee80211_channel __wl_5ghz_a_channels[] = {
++	CHAN5G(34, 0), CHAN5G(36, 0),
++	CHAN5G(38, 0), CHAN5G(40, 0),
++	CHAN5G(42, 0), CHAN5G(44, 0),
++	CHAN5G(46, 0), CHAN5G(48, 0),
++	CHAN5G(52, 0), CHAN5G(56, 0),
++	CHAN5G(60, 0), CHAN5G(64, 0),
++	CHAN5G(100, 0), CHAN5G(104, 0),
++	CHAN5G(108, 0), CHAN5G(112, 0),
++	CHAN5G(116, 0), CHAN5G(120, 0),
++	CHAN5G(124, 0), CHAN5G(128, 0),
++	CHAN5G(132, 0), CHAN5G(136, 0),
++	CHAN5G(140, 0), CHAN5G(144, 0),
++	CHAN5G(149, 0), CHAN5G(153, 0),
++	CHAN5G(157, 0), CHAN5G(161, 0),
++	CHAN5G(165, 0)
++};
++
++/* Global define the IEEE80211_BAND_XX to NL80211_BAND_xx here
++ * to prevent the verbosely #if #else for KERNEL VERSION
++ * Except the ones in CHAN2G()/CHAN5G which cannot be changed from here
++ */
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(4, 7, 0))
++#define IEEE80211_BAND_2GHZ NL80211_BAND_2GHZ
++#define IEEE80211_BAND_5GHZ NL80211_BAND_5GHZ
++#endif
++static struct ieee80211_supported_band __wl_band_2ghz = {
++	.band = IEEE80211_BAND_2GHZ,
++	.channels = __wl_2ghz_channels,
++	.n_channels = ARRAY_SIZE(__wl_2ghz_channels),
++	.bitrates = wl_g_rates,
++	.n_bitrates = wl_g_rates_size
++};
++
++static struct ieee80211_supported_band __wl_band_5ghz_a = {
++	.band = IEEE80211_BAND_5GHZ,
++	.channels = __wl_5ghz_a_channels,
++	.n_channels = ARRAY_SIZE(__wl_5ghz_a_channels),
++	.bitrates = wl_a_rates,
++	.n_bitrates = wl_a_rates_size
++};
++
++#if defined(WLFBT)
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
++#define WLAN_AKM_SUITE_FT_8021X         0x000FAC03
++#define WLAN_AKM_SUITE_FT_PSK           0x000FAC04
++#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) */
++#define WLAN_CIPHER_SUITE_PMK           0x00904C00
++#endif /* WLFBT */
++
++static const u32 __wl_cipher_suites[] = {
++	WLAN_CIPHER_SUITE_WEP40,
++	WLAN_CIPHER_SUITE_WEP104,
++	WLAN_CIPHER_SUITE_TKIP,
++	WLAN_CIPHER_SUITE_CCMP,
++	WLAN_CIPHER_SUITE_AES_CMAC,
++#if defined(WLFBT) && defined(WLAN_CIPHER_SUITE_PMK)
++	WLAN_CIPHER_SUITE_PMK,
++#endif
++};
++
++#ifdef WL_SUPPORT_ACS
++/*
++ * The firmware code required for this feature to work is currently under
++ * BCMINTERNAL flag. In future if this is to enabled we need to bring the
++ * required firmware code out of the BCMINTERNAL flag.
++ */
++struct wl_dump_survey {
++	u32 obss;
++	u32 ibss;
++	u32 no_ctg;
++	u32 no_pckt;
++	u32 tx;
++	u32 idle;
++};
++#endif /* WL_SUPPORT_ACS */
++
++
++#if defined(USE_DYNAMIC_MAXPKT_RXGLOM)
++static int maxrxpktglom = 0;
++#endif
++
++/* IOCtl version read from targeted driver */
++static int ioctl_version;
++#ifdef DEBUGFS_CFG80211
++#define S_SUBLOGLEVEL 20
++static const struct {
++	u32 log_level;
++	char *sublogname;
++} sublogname_map[] = {
++	{WL_DBG_ERR, "ERR"},
++	{WL_DBG_INFO, "INFO"},
++	{WL_DBG_DBG, "DBG"},
++	{WL_DBG_SCAN, "SCAN"},
++	{WL_DBG_TRACE, "TRACE"},
++	{WL_DBG_P2P_ACTION, "P2PACTION"}
++};
++#endif
++
++
++static void wl_add_remove_pm_enable_work(struct bcm_cfg80211 *cfg, bool add_remove,
++	enum wl_handler_del_type type)
++{
++	if (cfg == NULL)
++		return;
++
++	if (cfg->pm_enable_work_on) {
++		if (add_remove) {
++			schedule_delayed_work(&cfg->pm_enable_work,
++				msecs_to_jiffies(WL_PM_ENABLE_TIMEOUT));
++		} else {
++			cancel_delayed_work_sync(&cfg->pm_enable_work);
++
++			switch (type) {
++				case WL_HANDLER_MAINTAIN:
++					schedule_delayed_work(&cfg->pm_enable_work,
++						msecs_to_jiffies(WL_PM_ENABLE_TIMEOUT));
++					break;
++				case WL_HANDLER_PEND:
++					schedule_delayed_work(&cfg->pm_enable_work,
++						msecs_to_jiffies(WL_PM_ENABLE_TIMEOUT*2));
++					break;
++				case WL_HANDLER_DEL:
++				default:
++					cfg->pm_enable_work_on = false;
++					break;
++			}
++		}
++	}
++}
++
++/* Return a new chanspec given a legacy chanspec
++ * Returns INVCHANSPEC on error
++ */
++static chanspec_t
++wl_chspec_from_legacy(chanspec_t legacy_chspec)
++{
++	chanspec_t chspec;
++
++	/* get the channel number */
++	chspec = LCHSPEC_CHANNEL(legacy_chspec);
++
++	/* convert the band */
++	if (LCHSPEC_IS2G(legacy_chspec)) {
++		chspec |= WL_CHANSPEC_BAND_2G;
++	} else {
++		chspec |= WL_CHANSPEC_BAND_5G;
++	}
++
++	/* convert the bw and sideband */
++	if (LCHSPEC_IS20(legacy_chspec)) {
++		chspec |= WL_CHANSPEC_BW_20;
++	} else {
++		chspec |= WL_CHANSPEC_BW_40;
++		if (LCHSPEC_CTL_SB(legacy_chspec) == WL_LCHANSPEC_CTL_SB_LOWER) {
++			chspec |= WL_CHANSPEC_CTL_SB_L;
++		} else {
++			chspec |= WL_CHANSPEC_CTL_SB_U;
++		}
++	}
++
++	if (wf_chspec_malformed(chspec)) {
++		WL_ERR(("wl_chspec_from_legacy: output chanspec (0x%04X) malformed\n",
++		        chspec));
++		return INVCHANSPEC;
++	}
++
++	return chspec;
++}
++
++/* Return a legacy chanspec given a new chanspec
++ * Returns INVCHANSPEC on error
++ */
++static chanspec_t
++wl_chspec_to_legacy(chanspec_t chspec)
++{
++	chanspec_t lchspec;
++
++	if (wf_chspec_malformed(chspec)) {
++		WL_ERR(("wl_chspec_to_legacy: input chanspec (0x%04X) malformed\n",
++		        chspec));
++		return INVCHANSPEC;
++	}
++
++	/* get the channel number */
++	lchspec = CHSPEC_CHANNEL(chspec);
++
++	/* convert the band */
++	if (CHSPEC_IS2G(chspec)) {
++		lchspec |= WL_LCHANSPEC_BAND_2G;
++	} else {
++		lchspec |= WL_LCHANSPEC_BAND_5G;
++	}
++
++	/* convert the bw and sideband */
++	if (CHSPEC_IS20(chspec)) {
++		lchspec |= WL_LCHANSPEC_BW_20;
++		lchspec |= WL_LCHANSPEC_CTL_SB_NONE;
++	} else if (CHSPEC_IS40(chspec)) {
++		lchspec |= WL_LCHANSPEC_BW_40;
++		if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_L) {
++			lchspec |= WL_LCHANSPEC_CTL_SB_LOWER;
++		} else {
++			lchspec |= WL_LCHANSPEC_CTL_SB_UPPER;
++		}
++	} else {
++		/* cannot express the bandwidth */
++		char chanbuf[CHANSPEC_STR_LEN];
++		WL_ERR((
++		        "wl_chspec_to_legacy: unable to convert chanspec %s (0x%04X) "
++		        "to pre-11ac format\n",
++		        wf_chspec_ntoa(chspec, chanbuf), chspec));
++		return INVCHANSPEC;
++	}
++
++	return lchspec;
++}
++
++/* given a chanspec value, do the endian and chanspec version conversion to
++ * a chanspec_t value
++ * Returns INVCHANSPEC on error
++ */
++chanspec_t
++wl_chspec_host_to_driver(chanspec_t chanspec)
++{
++	if (ioctl_version == 1) {
++		chanspec = wl_chspec_to_legacy(chanspec);
++		if (chanspec == INVCHANSPEC) {
++			return chanspec;
++		}
++	}
++	chanspec = htodchanspec(chanspec);
++
++	return chanspec;
++}
++
++/* given a channel value, do the endian and chanspec version conversion to
++ * a chanspec_t value
++ * Returns INVCHANSPEC on error
++ */
++chanspec_t
++wl_ch_host_to_driver(s32 bssidx, u16 channel)
++{
++	chanspec_t chanspec;
++
++	chanspec = channel & WL_CHANSPEC_CHAN_MASK;
++
++	if (channel <= CH_MAX_2G_CHANNEL)
++		chanspec |= WL_CHANSPEC_BAND_2G;
++	else
++		chanspec |= WL_CHANSPEC_BAND_5G;
++
++	chanspec |= wl_cfg80211_ulb_get_min_bw_chspec(NULL, bssidx);
++
++	chanspec |= WL_CHANSPEC_CTL_SB_NONE;
++
++	return wl_chspec_host_to_driver(chanspec);
++}
++
++/* given a chanspec value from the driver, do the endian and chanspec version conversion to
++ * a chanspec_t value
++ * Returns INVCHANSPEC on error
++ */
++chanspec_t
++wl_chspec_driver_to_host(chanspec_t chanspec)
++{
++	chanspec = dtohchanspec(chanspec);
++	if (ioctl_version == 1) {
++		chanspec = wl_chspec_from_legacy(chanspec);
++	}
++
++	return chanspec;
++}
++
++/*
++ * convert ASCII string to MAC address (colon-delimited format)
++ * eg: 00:11:22:33:44:55
++ */
++int
++wl_cfg80211_ether_atoe(const char *a, struct ether_addr *n)
++{
++	char *c = NULL;
++	int count = 0;
++
++	memset(n, 0, ETHER_ADDR_LEN);
++	for (;;) {
++		n->octet[count++] = (uint8)simple_strtoul(a, &c, 16);
++		if (!*c++ || count == ETHER_ADDR_LEN)
++			break;
++		a = c;
++	}
++	return (count == ETHER_ADDR_LEN);
++}
++
++/* There isn't a lot of sense in it, but you can transmit anything you like */
++static const struct ieee80211_txrx_stypes
++wl_cfg80211_default_mgmt_stypes[NUM_NL80211_IFTYPES] = {
++	[NL80211_IFTYPE_ADHOC] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ACTION >> 4)
++	},
++	[NL80211_IFTYPE_STATION] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
++		BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
++	},
++	[NL80211_IFTYPE_AP] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
++		BIT(IEEE80211_STYPE_DISASSOC >> 4) |
++		BIT(IEEE80211_STYPE_AUTH >> 4) |
++		BIT(IEEE80211_STYPE_DEAUTH >> 4) |
++		BIT(IEEE80211_STYPE_ACTION >> 4)
++	},
++	[NL80211_IFTYPE_AP_VLAN] = {
++		/* copy AP */
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
++		BIT(IEEE80211_STYPE_DISASSOC >> 4) |
++		BIT(IEEE80211_STYPE_AUTH >> 4) |
++		BIT(IEEE80211_STYPE_DEAUTH >> 4) |
++		BIT(IEEE80211_STYPE_ACTION >> 4)
++	},
++	[NL80211_IFTYPE_P2P_CLIENT] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
++		BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
++	},
++	[NL80211_IFTYPE_P2P_GO] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
++		BIT(IEEE80211_STYPE_DISASSOC >> 4) |
++		BIT(IEEE80211_STYPE_AUTH >> 4) |
++		BIT(IEEE80211_STYPE_DEAUTH >> 4) |
++		BIT(IEEE80211_STYPE_ACTION >> 4)
++	},
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	[NL80211_IFTYPE_P2P_DEVICE] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
++		BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
++	},
++#endif /* WL_CFG80211_P2P_DEV_IF */
++};
++
++static void swap_key_from_BE(struct wl_wsec_key *key)
++{
++	key->index = htod32(key->index);
++	key->len = htod32(key->len);
++	key->algo = htod32(key->algo);
++	key->flags = htod32(key->flags);
++	key->rxiv.hi = htod32(key->rxiv.hi);
++	key->rxiv.lo = htod16(key->rxiv.lo);
++	key->iv_initialized = htod32(key->iv_initialized);
++}
++
++static void swap_key_to_BE(struct wl_wsec_key *key)
++{
++	key->index = dtoh32(key->index);
++	key->len = dtoh32(key->len);
++	key->algo = dtoh32(key->algo);
++	key->flags = dtoh32(key->flags);
++	key->rxiv.hi = dtoh32(key->rxiv.hi);
++	key->rxiv.lo = dtoh16(key->rxiv.lo);
++	key->iv_initialized = dtoh32(key->iv_initialized);
++}
++
++/* Dump the contents of the encoded wps ie buffer and get pbc value */
++static void
++wl_validate_wps_ie(char *wps_ie, s32 wps_ie_len, bool *pbc)
++{
++	#define WPS_IE_FIXED_LEN 6
++	u16 len;
++	u8 *subel = NULL;
++	u16 subelt_id;
++	u16 subelt_len;
++	u16 val;
++	u8 *valptr = (uint8*) &val;
++	if (wps_ie == NULL || wps_ie_len < WPS_IE_FIXED_LEN) {
++		WL_ERR(("invalid argument : NULL\n"));
++		return;
++	}
++	len = (u16)wps_ie[TLV_LEN_OFF];
++
++	if (len > wps_ie_len) {
++		WL_ERR(("invalid length len %d, wps ie len %d\n", len, wps_ie_len));
++		return;
++	}
++	WL_DBG(("wps_ie len=%d\n", len));
++	len -= 4;	/* for the WPS IE's OUI, oui_type fields */
++	subel = wps_ie + WPS_IE_FIXED_LEN;
++	while (len >= 4) {		/* must have attr id, attr len fields */
++		valptr[0] = *subel++;
++		valptr[1] = *subel++;
++		subelt_id = HTON16(val);
++
++		valptr[0] = *subel++;
++		valptr[1] = *subel++;
++		subelt_len = HTON16(val);
++
++		len -= 4;			/* for the attr id, attr len fields */
++		len -= subelt_len;	/* for the remaining fields in this attribute */
++		WL_DBG((" subel=%p, subelt_id=0x%x subelt_len=%u\n",
++			subel, subelt_id, subelt_len));
++
++		if (subelt_id == WPS_ID_VERSION) {
++			WL_DBG(("  attr WPS_ID_VERSION: %u\n", *subel));
++		} else if (subelt_id == WPS_ID_REQ_TYPE) {
++			WL_DBG(("  attr WPS_ID_REQ_TYPE: %u\n", *subel));
++		} else if (subelt_id == WPS_ID_CONFIG_METHODS) {
++			valptr[0] = *subel;
++			valptr[1] = *(subel + 1);
++			WL_DBG(("  attr WPS_ID_CONFIG_METHODS: %x\n", HTON16(val)));
++		} else if (subelt_id == WPS_ID_DEVICE_NAME) {
++			char devname[100];
++			memcpy(devname, subel, subelt_len);
++			devname[subelt_len] = '\0';
++			WL_DBG(("  attr WPS_ID_DEVICE_NAME: %s (len %u)\n",
++				devname, subelt_len));
++		} else if (subelt_id == WPS_ID_DEVICE_PWD_ID) {
++			valptr[0] = *subel;
++			valptr[1] = *(subel + 1);
++			WL_DBG(("  attr WPS_ID_DEVICE_PWD_ID: %u\n", HTON16(val)));
++			*pbc = (HTON16(val) == DEV_PW_PUSHBUTTON) ? true : false;
++		} else if (subelt_id == WPS_ID_PRIM_DEV_TYPE) {
++			valptr[0] = *subel;
++			valptr[1] = *(subel + 1);
++			WL_DBG(("  attr WPS_ID_PRIM_DEV_TYPE: cat=%u \n", HTON16(val)));
++			valptr[0] = *(subel + 6);
++			valptr[1] = *(subel + 7);
++			WL_DBG(("  attr WPS_ID_PRIM_DEV_TYPE: subcat=%u\n", HTON16(val)));
++		} else if (subelt_id == WPS_ID_REQ_DEV_TYPE) {
++			valptr[0] = *subel;
++			valptr[1] = *(subel + 1);
++			WL_DBG(("  attr WPS_ID_REQ_DEV_TYPE: cat=%u\n", HTON16(val)));
++			valptr[0] = *(subel + 6);
++			valptr[1] = *(subel + 7);
++			WL_DBG(("  attr WPS_ID_REQ_DEV_TYPE: subcat=%u\n", HTON16(val)));
++		} else if (subelt_id == WPS_ID_SELECTED_REGISTRAR_CONFIG_METHODS) {
++			valptr[0] = *subel;
++			valptr[1] = *(subel + 1);
++			WL_DBG(("  attr WPS_ID_SELECTED_REGISTRAR_CONFIG_METHODS"
++				": cat=%u\n", HTON16(val)));
++		} else {
++			WL_DBG(("  unknown attr 0x%x\n", subelt_id));
++		}
++
++		subel += subelt_len;
++	}
++}
++
++s32 wl_set_tx_power(struct net_device *dev,
++	enum nl80211_tx_power_setting type, s32 dbm)
++{
++	s32 err = 0;
++	s32 disable = 0;
++	s32 txpwrqdbm;
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++
++	/* Make sure radio is off or on as far as software is concerned */
++	disable = WL_RADIO_SW_DISABLE << 16;
++	disable = htod32(disable);
++	err = wldev_ioctl(dev, WLC_SET_RADIO, &disable, sizeof(disable), true);
++	if (unlikely(err)) {
++		WL_ERR(("WLC_SET_RADIO error (%d)\n", err));
++		return err;
++	}
++
++	if (dbm > 0xffff)
++		dbm = 0xffff;
++	txpwrqdbm = dbm * 4;
++	err = wldev_iovar_setbuf_bsscfg(dev, "qtxpower", (void *)&txpwrqdbm,
++		sizeof(txpwrqdbm), cfg->ioctl_buf, WLC_IOCTL_SMLEN, 0,
++		&cfg->ioctl_buf_sync);
++	if (unlikely(err))
++		WL_ERR(("qtxpower error (%d)\n", err));
++	else
++		WL_ERR(("dBm=%d, txpwrqdbm=0x%x\n", dbm, txpwrqdbm));
++
++	return err;
++}
++
++s32 wl_get_tx_power(struct net_device *dev, s32 *dbm)
++{
++	s32 err = 0;
++	s32 txpwrdbm;
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++
++	err = wldev_iovar_getbuf_bsscfg(dev, "qtxpower",
++		NULL, 0, cfg->ioctl_buf, WLC_IOCTL_SMLEN, 0, &cfg->ioctl_buf_sync);
++	if (unlikely(err)) {
++		WL_ERR(("error (%d)\n", err));
++		return err;
++	}
++
++	memcpy(&txpwrdbm, cfg->ioctl_buf, sizeof(txpwrdbm));
++	txpwrdbm = dtoh32(txpwrdbm);
++	*dbm = (txpwrdbm & ~WL_TXPWR_OVERRIDE) / 4;
++
++	WL_INFORM(("dBm=%d, txpwrdbm=0x%x\n", *dbm, txpwrdbm));
++
++	return err;
++}
++
++static chanspec_t wl_cfg80211_get_shared_freq(struct wiphy *wiphy)
++{
++	chanspec_t chspec;
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *dev = bcmcfg_to_prmry_ndev(cfg);
++	struct ether_addr bssid;
++	struct wl_bss_info *bss = NULL;
++	s32 bssidx = 0; /* Explicitly set to primary bssidx */
++	char *buf;
++
++	memset(&bssid, 0, sizeof(bssid));
++	if ((err = wldev_ioctl(dev, WLC_GET_BSSID, &bssid, sizeof(bssid), false))) {
++		/* STA interface is not associated. So start the new interface on a temp
++		 * channel . Later proper channel will be applied by the above framework
++		 * via set_channel (cfg80211 API).
++		 */
++		WL_DBG(("Not associated. Return first channel from supported channel list. \n"));
++
++		if (!wldev_iovar_getint(dev, "chanspec", (s32*) &chspec)) {
++			return chspec;
++		} else {
++			return wl_ch_host_to_driver(bssidx, WL_P2P_TEMP_CHAN);
++		}
++	}
++	
++	buf = kzalloc(WL_EXTRA_BUF_MAX, GFP_KERNEL);
++	if (!buf) {
++		WL_ERR(("buf alloc failed. use temp channel\n"));
++		return wl_ch_host_to_driver(bssidx, WL_P2P_TEMP_CHAN);
++	}
++
++	*(u32 *)buf = htod32(WL_EXTRA_BUF_MAX);
++	if ((err = wldev_ioctl(dev, WLC_GET_BSS_INFO, buf,
++		WL_EXTRA_BUF_MAX, false))) {
++			WL_ERR(("Failed to get associated bss info, use temp channel \n"));
++			chspec = wl_ch_host_to_driver(bssidx, WL_P2P_TEMP_CHAN);
++	}
++	else {
++		bss = (struct wl_bss_info *) (buf + 4);
++		chspec =  bss->chanspec;
++
++			WL_DBG(("Valid BSS Found. chanspec:%d \n", chspec));
++	}
++
++	kfree(buf);
++	return chspec;
++}
++
++static bcm_struct_cfgdev *
++wl_cfg80211_add_monitor_if(char *name)
++{
++#if defined(WL_ENABLE_P2P_IF) || defined(WL_CFG80211_P2P_DEV_IF)
++	WL_INFORM(("wl_cfg80211_add_monitor_if: No more support monitor interface\n"));
++	return ERR_PTR(-EOPNOTSUPP);
++#else
++	struct net_device* ndev = NULL;
++
++	dhd_add_monitor(name, &ndev);
++	WL_INFORM(("wl_cfg80211_add_monitor_if net device returned: 0x%p\n", ndev));
++	return ndev_to_cfgdev(ndev);
++#endif /* WL_ENABLE_P2P_IF || WL_CFG80211_P2P_DEV_IF */
++}
++
++static bcm_struct_cfgdev *
++wl_cfg80211_add_virtual_iface(struct wiphy *wiphy,
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	const char *name,
++#else
++	char *name,
++#endif /* WL_CFG80211_P2P_DEV_IF */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
++	unsigned char name_assign_type,
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++	enum nl80211_iftype type,
++#else
++	enum nl80211_iftype type, u32 *flags,
++#endif
++	struct vif_params *params)
++{
++	s32 err = -ENODEV;
++	s32 timeout = -1;
++	s32 wlif_type = -1;
++	s32 mode = 0;
++	s32 val = 0;
++	s32 cfg_type;
++	s32 dhd_mode = 0;
++	chanspec_t chspec;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *primary_ndev;
++	struct net_device *new_ndev;
++	struct ether_addr primary_mac;
++#ifdef WL_VIRTUAL_APSTA
++	bcm_struct_cfgdev *new_cfgdev;
++#endif /* WL_VIRTUAL_APSTA */
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO) || defined(BCMDBUS)
++	s32 up = 1;
++	dhd_pub_t *dhd;
++	bool enabled;
++#endif /* defined(BCMSDIO) || defined(BCMDBUS) */
++#endif /* PROP_TXSTATUS_VSDB */
++#if defined(SUPPORT_AP_POWERSAVE)
++	dhd_pub_t *dhd;
++#endif /* SUPPORT_AP_POWERSAVE */
++
++	if (!cfg)
++		return ERR_PTR(-EINVAL);
++
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO) || defined(BCMDBUS)
++	dhd = (dhd_pub_t *)(cfg->pub);
++#endif /* defined(BCMSDIO) || defined(BCMDBUS) */
++#endif /* PROP_TXSTATUS_VSDB */
++#if defined(SUPPORT_AP_POWERSAVE)
++	dhd = (dhd_pub_t *)(cfg->pub);
++#endif /* SUPPORT_AP_POWERSAVE */
++
++	/* Use primary I/F for sending cmds down to firmware */
++	primary_ndev = bcmcfg_to_prmry_ndev(cfg);
++
++	if (unlikely(!wl_get_drv_status(cfg, READY, primary_ndev))) {
++		WL_ERR(("device is not ready\n"));
++		return ERR_PTR(-ENODEV);
++	}
++
++	WL_DBG(("if name: %s, type: %d\n", name, type));
++	switch (type) {
++	case NL80211_IFTYPE_ADHOC:
++#ifdef WLAIBSS_MCHAN
++		return bcm_cfg80211_add_ibss_if(wiphy, (char *)name);
++#endif /* WLAIBSS_MCHAN */
++	case NL80211_IFTYPE_AP_VLAN:
++	case NL80211_IFTYPE_WDS:
++	case NL80211_IFTYPE_MESH_POINT:
++		WL_ERR(("Unsupported interface type\n"));
++		mode = WL_MODE_IBSS;
++		return NULL;
++	case NL80211_IFTYPE_MONITOR:
++		return wl_cfg80211_add_monitor_if((char *)name);
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	case NL80211_IFTYPE_P2P_DEVICE:
++		return wl_cfgp2p_add_p2p_disc_if(cfg);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++	case NL80211_IFTYPE_STATION:
++#ifdef WL_VIRTUAL_APSTA
++#ifdef WLAIBSS_MCHAN
++		if (cfg->ibss_cfgdev) {
++			WL_ERR(("AIBSS is already operational. "
++					" AIBSS & DUALSTA can't be used together \n"));
++			return ERR_PTR(-ENOMEM);
++		}
++#endif /* WLAIBSS_MCHAN */
++		if (!name) {
++			WL_ERR(("Interface name not provided \n"));
++			return ERR_PTR(-ENODEV);
++		}
++
++		if (wl_cfgp2p_vif_created(cfg)) {
++			WL_ERR(("Could not create new iface."
++				"Already one p2p interface is running"));
++			return ERR_PTR(-ENODEV);
++		}
++		new_cfgdev = wl_cfg80211_create_iface(cfg->wdev->wiphy,
++			NL80211_IFTYPE_STATION, NULL, name);
++		if (!new_cfgdev)
++			return ERR_PTR(-ENOMEM);
++		else
++			return new_cfgdev;
++#endif /* WL_VIRTUAL_APSTA */
++	case NL80211_IFTYPE_P2P_CLIENT:
++		wlif_type = WL_P2P_IF_CLIENT;
++		mode = WL_MODE_BSS;
++		break;
++	case NL80211_IFTYPE_P2P_GO:
++	case NL80211_IFTYPE_AP:
++		wlif_type = WL_P2P_IF_GO;
++		mode = WL_MODE_AP;
++		break;
++	default:
++		WL_ERR(("Unsupported interface type\n"));
++		return ERR_PTR(-ENODEV);
++		break;
++	}
++
++	if (!name) {
++		WL_ERR(("name is NULL\n"));
++		return ERR_PTR(-ENODEV);
++	}
++	if (cfg->p2p_supported && (wlif_type != -1)) {
++		ASSERT(cfg->p2p); /* ensure expectation of p2p initialization */
++
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO) || defined(BCMDBUS)
++		if (!dhd)
++			return ERR_PTR(-ENODEV);
++#endif /* defined(BCMSDIO) || defined(BCMDBUS) */
++#endif /* PROP_TXSTATUS_VSDB */
++		if (!cfg->p2p)
++			return ERR_PTR(-ENODEV);
++
++		if (cfg->cfgdev_bssidx != -1) {
++			WL_ERR(("Failed to start p2p, Maximum no of interface reached"));
++			return ERR_PTR(-ENODEV);
++		}
++
++		if (cfg->p2p && !cfg->p2p->on && strstr(name, WL_P2P_INTERFACE_PREFIX)) {
++			p2p_on(cfg) = true;
++			wl_cfgp2p_set_firm_p2p(cfg);
++			wl_cfgp2p_init_discovery(cfg);
++			get_primary_mac(cfg, &primary_mac);
++			wl_cfgp2p_generate_bss_mac(cfg, &primary_mac);
++		}
++
++		strncpy(cfg->p2p->vir_ifname, name, IFNAMSIZ - 1);
++		cfg->p2p->vir_ifname[IFNAMSIZ - 1] = '\0';
++
++		wl_cfg80211_scan_abort(cfg);
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO) || defined(BCMDBUS)
++		if (!cfg->wlfc_on && !disable_proptx) {
++			dhd_wlfc_get_enable(dhd, &enabled);
++			if (!enabled && dhd->op_mode != DHD_FLAG_HOSTAP_MODE &&
++				dhd->op_mode != DHD_FLAG_IBSS_MODE) {
++				dhd_wlfc_init(dhd);
++				err = wldev_ioctl(primary_ndev, WLC_UP, &up, sizeof(s32), true);
++				if (err < 0)
++					WL_ERR(("WLC_UP return err:%d\n", err));
++			}
++			cfg->wlfc_on = true;
++		}
++#endif /* defined(BCMSDIO) || defined(BCMDBUS) */
++#endif /* PROP_TXSTATUS_VSDB */
++
++		/* Dual p2p doesn't support multiple P2PGO interfaces,
++		 * p2p_go_count is the counter for GO creation
++		 * requests.
++		 */
++		if ((cfg->p2p->p2p_go_count > 0) && (type == NL80211_IFTYPE_P2P_GO)) {
++			WL_ERR(("Fw doesnot support  multiple Go"));
++			return ERR_PTR(-ENOMEM);
++		}
++		/* In concurrency case, STA may be already associated in a particular channel.
++		 * so retrieve the current channel of primary interface and then start the virtual
++		 * interface on that.
++		 */
++		 chspec = wl_cfg80211_get_shared_freq(wiphy);
++
++		/* For P2P mode, use P2P-specific driver features to create the
++		 * bss: "cfg p2p_ifadd"
++		 */
++		wl_set_p2p_status(cfg, IF_ADDING);
++		memset(&cfg->if_event_info, 0, sizeof(cfg->if_event_info));
++		if (wlif_type == WL_P2P_IF_GO)
++			wldev_iovar_setint(primary_ndev, "mpc", 0);
++		cfg_type = wl_cfgp2p_get_conn_idx(cfg);
++		if (cfg_type == BCME_ERROR) {
++			wl_clr_p2p_status(cfg, IF_ADDING);
++			WL_ERR(("Failed to get connection idx for p2p interface"));
++			goto fail;
++		}
++		err = wl_cfgp2p_ifadd(cfg, wl_to_p2p_bss_macaddr(cfg, cfg_type),
++			htod32(wlif_type), chspec);
++		if (unlikely(err)) {
++			wl_clr_p2p_status(cfg, IF_ADDING);
++			WL_ERR((" virtual iface add failed (%d) \n", err));
++			return ERR_PTR(-ENOMEM);
++		}
++
++		timeout = wait_event_interruptible_timeout(cfg->netif_change_event,
++			((wl_get_p2p_status(cfg, IF_ADDING) == false) &&
++			(cfg->if_event_info.valid)), msecs_to_jiffies(MAX_WAIT_TIME));
++
++		if (timeout > 0 && !wl_get_p2p_status(cfg, IF_ADDING) && cfg->if_event_info.valid) {
++			struct wireless_dev *vwdev;
++			int pm_mode = PM_ENABLE;
++			wl_if_event_info *event = &cfg->if_event_info;
++			/* IF_ADD event has come back, we can proceed to to register
++			 * the new interface now, use the interface name provided by caller (thus
++			 * ignore the one from wlc)
++			 */
++			new_ndev = wl_cfg80211_allocate_if(cfg, event->ifidx, cfg->p2p->vir_ifname,
++				event->mac, event->bssidx, event->name);
++			if (new_ndev == NULL)
++				goto fail;
++
++			wl_to_p2p_bss_ndev(cfg, cfg_type) = new_ndev;
++			wl_to_p2p_bss_bssidx(cfg, cfg_type) = event->bssidx;
++			vwdev = kzalloc(sizeof(*vwdev), GFP_KERNEL);
++			if (unlikely(!vwdev)) {
++				WL_ERR(("Could not allocate wireless device\n"));
++				err = -ENOMEM;
++				goto fail;
++			}
++			vwdev->wiphy = cfg->wdev->wiphy;
++			WL_INFORM(("virtual interface(%s) is created\n", cfg->p2p->vir_ifname));
++			if (type == NL80211_IFTYPE_P2P_GO) {
++				cfg->p2p->p2p_go_count++;
++			}
++			vwdev->iftype = type;
++			vwdev->netdev = new_ndev;
++			new_ndev->ieee80211_ptr = vwdev;
++			SET_NETDEV_DEV(new_ndev, wiphy_dev(vwdev->wiphy));
++			wl_set_drv_status(cfg, READY, new_ndev);
++			wl_set_mode_by_netdev(cfg, new_ndev, mode);
++
++			if (wl_cfg80211_register_if(cfg, event->ifidx, new_ndev) != BCME_OK) {
++				wl_cfg80211_remove_if(cfg, event->ifidx, new_ndev);
++				err = -ENODEV;
++				goto fail;
++			}
++			err = wl_alloc_netinfo(cfg, new_ndev, vwdev, mode, pm_mode, event->bssidx);
++			if (unlikely(err != 0)) {
++				WL_ERR(("Allocation of netinfo failed (%d) \n", err));
++				goto fail;
++			}
++			val = 1;
++			/* Disable firmware roaming for P2P interface  */
++			wldev_iovar_setint(new_ndev, "roam_off", val);
++#ifdef WL11ULB
++			if (cfg->p2p_wdev && is_p2p_group_iface(new_ndev->ieee80211_ptr)) {
++				u32 ulb_bw = wl_cfg80211_get_ulb_bw(cfg->p2p_wdev);
++				if (ulb_bw) {
++					/* Apply ULB BW settings on the newly spawned interface */
++					WL_DBG(("[ULB] Applying ULB BW for the newly"
++						"created P2P interface \n"));
++					if (wl_cfg80211_set_ulb_bw(new_ndev,
++						ulb_bw, new_ndev->name) < 0) {
++						/*
++						 * If ulb_bw set failed, fail the iface creation.
++						 * wl_dealloc_netinfo_by_wdev will be called by the
++						 * unregister notifier.
++						 */
++						wl_cfg80211_remove_if(cfg, event->ifidx, new_ndev);
++						err = -EINVAL;
++						goto fail;
++					}
++				}
++			}
++#endif /* WL11ULB */
++
++			if (mode != WL_MODE_AP)
++				wldev_iovar_setint(new_ndev, "buf_key_b4_m4", 1);
++
++			WL_ERR((" virtual interface(%s) is "
++				"created net attach done\n", cfg->p2p->vir_ifname));
++#ifdef SUPPORT_AP_POWERSAVE
++			if (mode == WL_MODE_AP) {
++				dhd_set_ap_powersave(dhd, 0, TRUE);
++			}
++#endif /* SUPPORT_AP_POWERSAVE */
++			if (type == NL80211_IFTYPE_P2P_CLIENT)
++				dhd_mode = DHD_FLAG_P2P_GC_MODE;
++			else if (type == NL80211_IFTYPE_P2P_GO)
++				dhd_mode = DHD_FLAG_P2P_GO_MODE;
++			DNGL_FUNC(dhd_cfg80211_set_p2p_info, (cfg, dhd_mode));
++			/* reinitialize completion to clear previous count */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0))
++			INIT_COMPLETION(cfg->iface_disable);
++#else
++			init_completion(&cfg->iface_disable);
++#endif
++			return ndev_to_cfgdev(new_ndev);
++		} else {
++			wl_clr_p2p_status(cfg, IF_ADDING);
++			WL_ERR((" virtual interface(%s) is not created \n", cfg->p2p->vir_ifname));
++
++			WL_ERR(("left timeout : %d\n", timeout));
++			WL_ERR(("IF_ADDING status : %d\n", wl_get_p2p_status(cfg, IF_ADDING)));
++			WL_ERR(("event valid : %d\n", cfg->if_event_info.valid));
++
++			wl_clr_p2p_status(cfg, GO_NEG_PHASE);
++			wl_set_p2p_status(cfg, IF_DELETING);
++
++			err = wl_cfgp2p_ifdel(cfg, wl_to_p2p_bss_macaddr(cfg, cfg_type));
++			if (err == BCME_OK) {
++				timeout = wait_event_interruptible_timeout(cfg->netif_change_event,
++					((wl_get_p2p_status(cfg, IF_DELETING) == false) &&
++					(cfg->if_event_info.valid)),
++					msecs_to_jiffies(MAX_WAIT_TIME));
++				if (timeout > 0 && !wl_get_p2p_status(cfg, IF_DELETING) &&
++					cfg->if_event_info.valid) {
++					WL_ERR(("IFDEL operation done\n"));
++				} else {
++					WL_ERR(("IFDEL didn't complete properly\n"));
++					err = BCME_ERROR;
++				}
++			}
++			if (err != BCME_OK) {
++				struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++
++				WL_ERR(("p2p_ifdel failed, error %d, sent HANG event to %s\n",
++					err, ndev->name));
++				net_os_send_hang_message(ndev);
++			}
++
++			memset(cfg->p2p->vir_ifname, '\0', IFNAMSIZ);
++			wl_to_p2p_bss_bssidx(cfg, cfg_type) = -1;
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO) || defined(BCMDBUS)
++			dhd_wlfc_get_enable(dhd, &enabled);
++		if (enabled && cfg->wlfc_on && dhd->op_mode != DHD_FLAG_HOSTAP_MODE &&
++			dhd->op_mode != DHD_FLAG_IBSS_MODE) {
++			dhd_wlfc_deinit(dhd);
++			cfg->wlfc_on = false;
++		}
++#endif /* defined(BCMSDIO) || defined(BCMDBUS) */
++#endif /* PROP_TXSTATUS_VSDB */
++		}
++	}
++fail:
++	if (wlif_type == WL_P2P_IF_GO)
++		wldev_iovar_setint(primary_ndev, "mpc", 1);
++	return ERR_PTR(err);
++}
++
++static s32
++wl_cfg80211_del_virtual_iface(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev)
++{
++	struct net_device *dev = NULL;
++	struct ether_addr p2p_mac;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 timeout = -1;
++	s32 ret = 0;
++	s32 index = -1;
++	s32 type = -1;
++#ifdef CUSTOM_SET_CPUCORE
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++#endif /* CUSTOM_SET_CPUCORE */
++	WL_DBG(("Enter\n"));
++
++#ifdef CUSTOM_SET_CPUCORE
++	dhd->chan_isvht80 &= ~DHD_FLAG_P2P_MODE;
++	if (!(dhd->chan_isvht80))
++		dhd_set_cpucore(dhd, FALSE);
++#endif /* CUSTOM_SET_CPUCORE */
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	if (cfgdev->iftype == NL80211_IFTYPE_P2P_DEVICE) {
++		return wl_cfgp2p_del_p2p_disc_if(cfgdev, cfg);
++	}
++#endif /* WL_CFG80211_P2P_DEV_IF */
++	dev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++#ifdef WLAIBSS_MCHAN
++	if (cfgdev == cfg->ibss_cfgdev)
++		return bcm_cfg80211_del_ibss_if(wiphy, cfgdev);
++#endif /* WLAIBSS_MCHAN */
++
++#ifdef WL_VIRTUAL_APSTA
++	if (cfgdev == cfg->bss_cfgdev)
++		return wl_cfg80211_del_iface(wiphy, cfgdev);
++#endif /* WL_VIRTUAL_APSTA */
++	if ((index = wl_get_bssidx_by_wdev(cfg, cfgdev_to_wdev(cfgdev))) < 0) {
++		WL_ERR(("Find p2p index from wdev failed\n"));
++		return BCME_ERROR;
++	}
++	if (cfg->p2p_supported) {
++		if (wl_cfgp2p_find_type(cfg, index, &type) != BCME_OK)
++			return BCME_ERROR;
++		memcpy(p2p_mac.octet, wl_to_p2p_bss_macaddr(cfg, type).octet, ETHER_ADDR_LEN);
++
++		/* Clear GO_NEG_PHASE bit to take care of GO-NEG-FAIL cases
++		 */
++		WL_DBG(("P2P: GO_NEG_PHASE status cleared "));
++		wl_clr_p2p_status(cfg, GO_NEG_PHASE);
++		if (wl_cfgp2p_vif_created(cfg)) {
++			if (wl_get_drv_status(cfg, SCANNING, dev)) {
++				wl_notify_escan_complete(cfg, dev, true, true);
++			}
++			wldev_iovar_setint(dev, "mpc", 1);
++			/* Delete pm_enable_work */
++			wl_add_remove_pm_enable_work(cfg, FALSE, WL_HANDLER_DEL);
++
++			/* for GC */
++			if (wl_get_drv_status(cfg, DISCONNECTING, dev) &&
++				(wl_get_mode_by_netdev(cfg, dev) != WL_MODE_AP)) {
++				WL_ERR(("Wait for Link Down event for GC !\n"));
++				wait_for_completion_timeout
++					(&cfg->iface_disable, msecs_to_jiffies(500));
++			}
++
++			memset(&cfg->if_event_info, 0, sizeof(cfg->if_event_info));
++			wl_set_p2p_status(cfg, IF_DELETING);
++			DNGL_FUNC(dhd_cfg80211_clean_p2p_info, (cfg));
++
++			/* for GO */
++			if (wl_get_mode_by_netdev(cfg, dev) == WL_MODE_AP) {
++				wl_add_remove_eventmsg(dev, WLC_E_PROBREQ_MSG, false);
++				cfg->p2p->p2p_go_count--;
++				/* disable interface before bsscfg free */
++				ret = wl_cfgp2p_ifdisable(cfg, &p2p_mac);
++				/* if fw doesn't support "ifdis",
++				   do not wait for link down of ap mode
++				 */
++				if (ret == 0) {
++					WL_ERR(("Wait for Link Down event for GO !!!\n"));
++					wait_for_completion_timeout(&cfg->iface_disable,
++						msecs_to_jiffies(500));
++				} else if (ret != BCME_UNSUPPORTED) {
++					msleep(300);
++				}
++			}
++			wl_cfg80211_clear_per_bss_ies(cfg, index);
++
++			if (wl_get_mode_by_netdev(cfg, dev) != WL_MODE_AP)
++				wldev_iovar_setint(dev, "buf_key_b4_m4", 0);
++			memcpy(p2p_mac.octet, wl_to_p2p_bss_macaddr(cfg, type).octet,
++			ETHER_ADDR_LEN);
++			CFGP2P_INFO(("primary idx %d : cfg p2p_ifdis "MACDBG"\n",
++			       dev->ifindex, MAC2STRDBG(p2p_mac.octet)));
++
++			/* delete interface after link down */
++			ret = wl_cfgp2p_ifdel(cfg, &p2p_mac);
++			if (ret != BCME_OK) {
++				struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++
++				WL_ERR(("p2p_ifdel failed, error %d, sent HANG event to %s\n",
++					ret, ndev->name));
++				net_os_send_hang_message(ndev);
++			} else {
++				/* Wait for IF_DEL operation to be finished */
++				timeout = wait_event_interruptible_timeout(cfg->netif_change_event,
++					((wl_get_p2p_status(cfg, IF_DELETING) == false) &&
++					(cfg->if_event_info.valid)),
++					msecs_to_jiffies(MAX_WAIT_TIME));
++				if (timeout > 0 && !wl_get_p2p_status(cfg, IF_DELETING) &&
++					cfg->if_event_info.valid) {
++
++					WL_DBG(("IFDEL operation done\n"));
++					wl_cfg80211_handle_ifdel(cfg, &cfg->if_event_info, dev);
++				} else {
++					WL_ERR(("IFDEL didn't complete properly\n"));
++				}
++			}
++
++			ret = dhd_del_monitor(dev);
++			if (wl_get_mode_by_netdev(cfg, dev) == WL_MODE_AP) {
++				DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_CANCEL((dhd_pub_t *)(cfg->pub));
++			}
++		}
++	}
++	return ret;
++}
++
++static s32
++wl_cfg80211_change_virtual_iface(struct wiphy *wiphy, struct net_device *ndev,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++	enum nl80211_iftype type,
++#else
++	enum nl80211_iftype type, u32 *flags,
++#endif
++	struct vif_params *params)
++{
++	s32 ap = 0;
++	s32 infra = 0;
++	s32 ibss = 0;
++	s32 wlif_type;
++	s32 mode = 0;
++	s32 err = BCME_OK;
++	s32 index;
++	s32 conn_idx = -1;
++	chanspec_t chspec;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *primary_ndev = bcmcfg_to_prmry_ndev(cfg);
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++
++	WL_DBG(("Enter type %d\n", type));
++	switch (type) {
++	case NL80211_IFTYPE_MONITOR:
++	case NL80211_IFTYPE_WDS:
++	case NL80211_IFTYPE_MESH_POINT:
++		ap = 1;
++		WL_ERR(("type (%d) : currently we do not support this type\n",
++			type));
++		break;
++	case NL80211_IFTYPE_ADHOC:
++		mode = WL_MODE_IBSS;
++		ibss = 1;
++		break;
++	case NL80211_IFTYPE_STATION:
++	case NL80211_IFTYPE_P2P_CLIENT:
++		mode = WL_MODE_BSS;
++		infra = 1;
++		break;
++	case NL80211_IFTYPE_AP:
++		dhd->op_mode |= DHD_FLAG_HOSTAP_MODE;
++		/* intentional fall through */
++	case NL80211_IFTYPE_AP_VLAN:
++	case NL80211_IFTYPE_P2P_GO:
++		mode = WL_MODE_AP;
++		ap = 1;
++		break;
++	default:
++		return -EINVAL;
++	}
++	if (!dhd)
++		return -EINVAL;
++	if (ap) {
++		wl_set_mode_by_netdev(cfg, ndev, mode);
++		if (is_p2p_group_iface(ndev->ieee80211_ptr) &&
++			cfg->p2p && wl_cfgp2p_vif_created(cfg)) {
++			WL_DBG(("p2p_vif_created p2p_on (%d)\n", p2p_on(cfg)));
++			wldev_iovar_setint(ndev, "mpc", 0);
++			wl_notify_escan_complete(cfg, ndev, true, true);
++
++			/* Dual p2p doesn't support multiple P2PGO interfaces,
++			 * p2p_go_count is the counter for GO creation
++			 * requests.
++			 */
++			if ((cfg->p2p->p2p_go_count > 0) && (type == NL80211_IFTYPE_P2P_GO)) {
++				wl_set_mode_by_netdev(cfg, ndev, WL_MODE_BSS);
++				WL_ERR(("Fw doesnot support  multiple GO "));
++				return BCME_ERROR;
++			}
++			/* In concurrency case, STA may be already associated in a particular
++			 * channel. so retrieve the current channel of primary interface and
++			 * then start the virtual interface on that.
++			 */
++			chspec = wl_cfg80211_get_shared_freq(wiphy);
++			index = wl_get_bssidx_by_wdev(cfg, ndev->ieee80211_ptr);
++			if (index < 0) {
++				WL_ERR(("Find p2p index from ndev(%p) failed\n", ndev));
++				return BCME_ERROR;
++			}
++			if (wl_cfgp2p_find_type(cfg, index, &conn_idx) != BCME_OK)
++				return BCME_ERROR;
++
++			wlif_type = WL_P2P_IF_GO;
++			WL_DBG(("%s : ap (%d), infra (%d), iftype (%d) conn_idx (%d)\n",
++				ndev->name, ap, infra, type, conn_idx));
++			wl_set_p2p_status(cfg, IF_CHANGING);
++			wl_clr_p2p_status(cfg, IF_CHANGED);
++			wl_cfgp2p_ifchange(cfg, wl_to_p2p_bss_macaddr(cfg, conn_idx),
++				htod32(wlif_type), chspec, conn_idx);
++			wait_event_interruptible_timeout(cfg->netif_change_event,
++				(wl_get_p2p_status(cfg, IF_CHANGED) == true),
++				msecs_to_jiffies(MAX_WAIT_TIME));
++			wl_set_mode_by_netdev(cfg, ndev, mode);
++			dhd->op_mode &= ~DHD_FLAG_P2P_GC_MODE;
++			dhd->op_mode |= DHD_FLAG_P2P_GO_MODE;
++			wl_clr_p2p_status(cfg, IF_CHANGING);
++			wl_clr_p2p_status(cfg, IF_CHANGED);
++#ifdef SUPPORT_AP_POWERSAVE
++			dhd_set_ap_powersave(dhd, 0, TRUE);
++#endif /* SUPPORT_AP_POWERSAVE */
++		} else if (((ndev == primary_ndev) ||
++			(ndev == ((struct net_device *)cfgdev_to_ndev(cfg->bss_cfgdev)))) &&
++			!wl_get_drv_status(cfg, AP_CREATED, ndev)) {
++			wl_set_drv_status(cfg, AP_CREATING, ndev);
++		} else {
++			WL_ERR(("Cannot change the interface for GO or SOFTAP\n"));
++			return -EINVAL;
++		}
++	} else {
++		/* P2P GO interface deletion is handled on the basis of role type (AP).
++		 * So avoid changing role for p2p type.
++		 */
++		if (ndev->ieee80211_ptr->iftype != NL80211_IFTYPE_P2P_GO)
++			wl_set_mode_by_netdev(cfg, ndev, mode);
++		WL_DBG(("Change_virtual_iface for transition from GO/AP to client/STA"));
++#ifdef SUPPORT_AP_POWERSAVE
++		dhd_set_ap_powersave(dhd, 0, FALSE);
++#endif /* SUPPORT_AP_POWERSAVE */
++	}
++
++	if (ibss) {
++		infra = 0;
++		wl_set_mode_by_netdev(cfg, ndev, mode);
++		err = wldev_ioctl(ndev, WLC_SET_INFRA, &infra, sizeof(s32), true);
++		if (err < 0) {
++			WL_ERR(("SET Adhoc error %d\n", err));
++			return -EINVAL;
++		}
++	}
++
++	ndev->ieee80211_ptr->iftype = type;
++	return 0;
++}
++
++s32
++wl_cfg80211_notify_ifadd(int ifidx, char *name, uint8 *mac, uint8 bssidx)
++{
++	bool ifadd_expected = FALSE;
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++
++	/* P2P may send WLC_E_IF_ADD and/or WLC_E_IF_CHANGE during IF updating ("p2p_ifupd")
++	 * redirect the IF_ADD event to ifchange as it is not a real "new" interface
++	 */
++	if (wl_get_p2p_status(cfg, IF_CHANGING))
++		return wl_cfg80211_notify_ifchange(ifidx, name, mac, bssidx);
++
++	/* Okay, we are expecting IF_ADD (as IF_ADDING is true) */
++	if (wl_get_p2p_status(cfg, IF_ADDING)) {
++		ifadd_expected = TRUE;
++		wl_clr_p2p_status(cfg, IF_ADDING);
++	} else if (cfg->bss_pending_op) {
++		ifadd_expected = TRUE;
++		cfg->bss_pending_op = FALSE;
++	}
++
++	if (ifadd_expected) {
++		wl_if_event_info *if_event_info = &cfg->if_event_info;
++
++		if_event_info->valid = TRUE;
++		if_event_info->ifidx = ifidx;
++		if_event_info->bssidx = bssidx;
++		strncpy(if_event_info->name, name, IFNAMSIZ);
++		if_event_info->name[IFNAMSIZ] = '\0';
++		if (mac)
++			memcpy(if_event_info->mac, mac, ETHER_ADDR_LEN);
++		wake_up_interruptible(&cfg->netif_change_event);
++		return BCME_OK;
++	}
++
++	return BCME_ERROR;
++}
++
++s32
++wl_cfg80211_notify_ifdel(int ifidx, char *name, uint8 *mac, uint8 bssidx)
++{
++	bool ifdel_expected = FALSE;
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	wl_if_event_info *if_event_info = &cfg->if_event_info;
++
++	if (wl_get_p2p_status(cfg, IF_DELETING)) {
++		ifdel_expected = TRUE;
++		wl_clr_p2p_status(cfg, IF_DELETING);
++	} else if (cfg->bss_pending_op) {
++		ifdel_expected = TRUE;
++		cfg->bss_pending_op = FALSE;
++	}
++
++	if (ifdel_expected) {
++		if_event_info->valid = TRUE;
++		if_event_info->ifidx = ifidx;
++		if_event_info->bssidx = bssidx;
++		wake_up_interruptible(&cfg->netif_change_event);
++		return BCME_OK;
++	}
++
++	return BCME_ERROR;
++}
++
++s32
++wl_cfg80211_notify_ifchange(int ifidx, char *name, uint8 *mac, uint8 bssidx)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++
++	if (wl_get_p2p_status(cfg, IF_CHANGING)) {
++		wl_set_p2p_status(cfg, IF_CHANGED);
++		wake_up_interruptible(&cfg->netif_change_event);
++		return BCME_OK;
++	}
++
++	return BCME_ERROR;
++}
++
++static s32 wl_cfg80211_handle_ifdel(struct bcm_cfg80211 *cfg, wl_if_event_info *if_event_info,
++	struct net_device* ndev)
++{
++	s32 type = -1;
++	s32 bssidx = -1;
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO) || defined(BCMDBUS)
++	dhd_pub_t *dhd =  (dhd_pub_t *)(cfg->pub);
++	bool enabled;
++#endif /* defined(BCMSDIO) || defined(BCMDBUS) */
++#endif /* PROP_TXSTATUS_VSDB */
++
++	bssidx = if_event_info->bssidx;
++	if (bssidx != wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_CONNECTION1) &&
++		bssidx != wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_CONNECTION2)) {
++		WL_ERR(("got IF_DEL for if %d, not owned by cfg driver\n", bssidx));
++		return BCME_ERROR;
++	}
++
++	if (p2p_is_on(cfg) && wl_cfgp2p_vif_created(cfg)) {
++		if (cfg->scan_request && (cfg->escan_info.ndev == ndev)) {
++			/* Abort any pending scan requests */
++			cfg->escan_info.escan_state = WL_ESCAN_STATE_IDLE;
++			WL_DBG(("ESCAN COMPLETED\n"));
++			wl_notify_escan_complete(cfg, cfg->escan_info.ndev, true, false);
++		}
++
++		memset(cfg->p2p->vir_ifname, '\0', IFNAMSIZ);
++		if (wl_cfgp2p_find_type(cfg, bssidx, &type) == BCME_OK) {
++			/* Update P2P data */
++			wl_clr_drv_status(cfg, CONNECTED, wl_to_p2p_bss_ndev(cfg, type));
++			wl_to_p2p_bss_ndev(cfg, type) = NULL;
++			wl_to_p2p_bss_bssidx(cfg, type) = -1;
++		} else if (wl_get_bssidx_by_wdev(cfg, ndev->ieee80211_ptr) < 0) {
++			WL_ERR(("bssidx not known for the given ndev as per net_info data \n"));
++			return BCME_ERROR;
++		}
++
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO) || defined(BCMDBUS)
++		dhd_wlfc_get_enable(dhd, &enabled);
++		if (enabled && cfg->wlfc_on && dhd->op_mode != DHD_FLAG_HOSTAP_MODE &&
++			dhd->op_mode != DHD_FLAG_IBSS_MODE) {
++			dhd_wlfc_deinit(dhd);
++			cfg->wlfc_on = false;
++		}
++#endif /* defined(BCMSDIO) || defined(BCMDBUS) */
++#endif /* PROP_TXSTATUS_VSDB */
++	}
++
++	dhd_net_if_lock(ndev);
++	wl_cfg80211_remove_if(cfg, if_event_info->ifidx, ndev);
++	dhd_net_if_unlock(ndev);
++
++	return BCME_OK;
++}
++
++/* Find listen channel */
++static s32 wl_find_listen_channel(struct bcm_cfg80211 *cfg,
++	const u8 *ie, u32 ie_len)
++{
++	wifi_p2p_ie_t *p2p_ie;
++	u8 *end, *pos;
++	s32 listen_channel;
++
++/* unfortunately const cast required here - function is
++ * a callback so its signature must not be changed
++ * and cascade of changing wl_cfgp2p_find_p2pie
++ * causes need for const cast in other places
++ */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++	pos = (u8 *)ie;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	p2p_ie = wl_cfgp2p_find_p2pie(pos, ie_len);
++
++	if (p2p_ie == NULL)
++		return 0;
++
++	pos = p2p_ie->subelts;
++	end = p2p_ie->subelts + (p2p_ie->len - 4);
++
++	CFGP2P_DBG((" found p2p ie ! lenth %d \n",
++		p2p_ie->len));
++
++	while (pos < end) {
++		uint16 attr_len;
++		if (pos + 2 >= end) {
++			CFGP2P_DBG((" -- Invalid P2P attribute"));
++			return 0;
++		}
++		attr_len = ((uint16) (((pos + 1)[1] << 8) | (pos + 1)[0]));
++
++		if (pos + 3 + attr_len > end) {
++			CFGP2P_DBG(("P2P: Attribute underflow "
++				   "(len=%u left=%d)",
++				   attr_len, (int) (end - pos - 3)));
++			return 0;
++		}
++
++		/* if Listen Channel att id is 6 and the vailue is valid,
++		 * return the listen channel
++		 */
++		if (pos[0] == 6) {
++			/* listen channel subel length format
++			 * 1(id) + 2(len) + 3(country) + 1(op. class) + 1(chan num)
++			 */
++			listen_channel = pos[1 + 2 + 3 + 1];
++
++			if (listen_channel == SOCIAL_CHAN_1 ||
++				listen_channel == SOCIAL_CHAN_2 ||
++				listen_channel == SOCIAL_CHAN_3) {
++				CFGP2P_DBG((" Found my Listen Channel %d \n", listen_channel));
++				return listen_channel;
++			}
++		}
++		pos += 3 + attr_len;
++	}
++	return 0;
++}
++
++static void wl_scan_prep(struct wl_scan_params *params, struct cfg80211_scan_request *request)
++{
++	u32 n_ssids;
++	u32 n_channels;
++	u16 channel;
++	chanspec_t chanspec;
++	s32 i = 0, j = 0, offset;
++	char *ptr;
++	wlc_ssid_t ssid;
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	struct wireless_dev *wdev;
++
++	memcpy(&params->bssid, &ether_bcast, ETHER_ADDR_LEN);
++	params->bss_type = DOT11_BSSTYPE_ANY;
++	params->scan_type = 0;
++	params->nprobes = -1;
++	params->active_time = -1;
++	params->passive_time = -1;
++	params->home_time = -1;
++	params->channel_num = 0;
++	memset(&params->ssid, 0, sizeof(wlc_ssid_t));
++
++	WL_SCAN(("Preparing Scan request\n"));
++	WL_SCAN(("nprobes=%d\n", params->nprobes));
++	WL_SCAN(("active_time=%d\n", params->active_time));
++	WL_SCAN(("passive_time=%d\n", params->passive_time));
++	WL_SCAN(("home_time=%d\n", params->home_time));
++	WL_SCAN(("scan_type=%d\n", params->scan_type));
++
++	params->nprobes = htod32(params->nprobes);
++	params->active_time = htod32(params->active_time);
++	params->passive_time = htod32(params->passive_time);
++	params->home_time = htod32(params->home_time);
++
++	/* if request is null just exit so it will be all channel broadcast scan */
++	if (!request)
++		return;
++
++	n_ssids = request->n_ssids;
++	n_channels = request->n_channels;
++
++	/* Copy channel array if applicable */
++	WL_SCAN(("### List of channelspecs to scan ###\n"));
++	if (n_channels > 0) {
++		for (i = 0; i < n_channels; i++) {
++			chanspec = 0;
++			channel = ieee80211_frequency_to_channel(request->channels[i]->center_freq);
++			/* SKIP DFS channels for Secondary interface */
++			if ((cfg->escan_info.ndev != bcmcfg_to_prmry_ndev(cfg)) &&
++				(request->channels[i]->flags &
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
++				(IEEE80211_CHAN_RADAR | IEEE80211_CHAN_PASSIVE_SCAN)))
++#else
++				(IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR)))
++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0) */
++				continue;
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++			wdev = request->wdev;
++#else
++			wdev = request->dev->ieee80211_ptr;
++#endif /* WL_CFG80211_P2P_DEV_IF */
++			chanspec = wl_cfg80211_ulb_get_min_bw_chspec(wdev, -1);
++			if (chanspec == INVCHANSPEC) {
++				WL_ERR(("Invalid chanspec! Skipping channel\n"));
++				continue;
++			}
++
++			if (request->channels[i]->band == IEEE80211_BAND_2GHZ) {
++				chanspec |= WL_CHANSPEC_BAND_2G;
++			} else {
++				chanspec |= WL_CHANSPEC_BAND_5G;
++			}
++			params->channel_list[j] = channel;
++			params->channel_list[j] &= WL_CHANSPEC_CHAN_MASK;
++			params->channel_list[j] |= chanspec;
++			WL_SCAN(("Chan : %d, Channel spec: %x \n",
++				channel, params->channel_list[j]));
++			params->channel_list[j] = wl_chspec_host_to_driver(params->channel_list[j]);
++			j++;
++		}
++	} else {
++		WL_SCAN(("Scanning all channels\n"));
++	}
++	n_channels = j;
++	/* Copy ssid array if applicable */
++	WL_SCAN(("### List of SSIDs to scan ###\n"));
++	if (n_ssids > 0) {
++		offset = offsetof(wl_scan_params_t, channel_list) + n_channels * sizeof(u16);
++		offset = roundup(offset, sizeof(u32));
++		ptr = (char*)params + offset;
++		for (i = 0; i < n_ssids; i++) {
++			memset(&ssid, 0, sizeof(wlc_ssid_t));
++			ssid.SSID_len = request->ssids[i].ssid_len;
++			memcpy(ssid.SSID, request->ssids[i].ssid, ssid.SSID_len);
++			if (!ssid.SSID_len)
++				WL_SCAN(("%d: Broadcast scan\n", i));
++			else
++				WL_SCAN(("%d: scan  for  %s size =%d\n", i,
++				ssid.SSID, ssid.SSID_len));
++			memcpy(ptr, &ssid, sizeof(wlc_ssid_t));
++			ptr += sizeof(wlc_ssid_t);
++		}
++	} else {
++		WL_SCAN(("Broadcast scan\n"));
++	}
++	/* Adding mask to channel numbers */
++	params->channel_num =
++	        htod32((n_ssids << WL_SCAN_PARAMS_NSSID_SHIFT) |
++	               (n_channels & WL_SCAN_PARAMS_COUNT_MASK));
++
++	if (n_channels == 1) {
++		params->active_time = htod32(WL_SCAN_CONNECT_DWELL_TIME_MS);
++		params->nprobes = htod32(params->active_time / WL_SCAN_JOIN_PROBE_INTERVAL_MS);
++	}
++}
++
++static s32
++wl_get_valid_channels(struct net_device *ndev, u8 *valid_chan_list, s32 size)
++{
++	wl_uint32_list_t *list;
++	s32 err = BCME_OK;
++	if (valid_chan_list == NULL || size <= 0)
++		return -ENOMEM;
++
++	memset(valid_chan_list, 0, size);
++	list = (wl_uint32_list_t *)(void *) valid_chan_list;
++	list->count = htod32(WL_NUMCHANNELS);
++	err = wldev_ioctl(ndev, WLC_GET_VALID_CHANNELS, valid_chan_list, size, false);
++	if (err != 0) {
++		WL_ERR(("get channels failed with %d\n", err));
++	}
++
++	return err;
++}
++
++#if defined(USE_INITIAL_SHORT_DWELL_TIME)
++#define FIRST_SCAN_ACTIVE_DWELL_TIME_MS 40
++bool g_first_broadcast_scan = TRUE;
++#endif 
++
++static s32
++wl_run_escan(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	struct cfg80211_scan_request *request, uint16 action)
++{
++	s32 err = BCME_OK;
++	u32 n_channels;
++	u32 n_ssids;
++	s32 params_size = (WL_SCAN_PARAMS_FIXED_SIZE + OFFSETOF(wl_escan_params_t, params));
++	wl_escan_params_t *params = NULL;
++	u8 chan_buf[sizeof(u32)*(WL_NUMCHANNELS + 1)];
++	u32 num_chans = 0;
++	s32 channel;
++	u32 n_valid_chan;
++	s32 search_state = WL_P2P_DISC_ST_SCAN;
++	u32 i, j, n_nodfs = 0;
++	u16 *default_chan_list = NULL;
++	wl_uint32_list_t *list;
++	s32 bssidx = -1;
++	struct net_device *dev = NULL;
++#if defined(USE_INITIAL_SHORT_DWELL_TIME)
++	bool is_first_init_2g_scan = false;
++#endif 
++	p2p_scan_purpose_t	p2p_scan_purpose = P2P_SCAN_PURPOSE_MIN;
++
++	WL_DBG(("Enter \n"));
++
++	/* scan request can come with empty request : perform all default scan */
++	if (!cfg) {
++		err = -EINVAL;
++		goto exit;
++	}
++	if (!cfg->p2p_supported || !p2p_scan(cfg)) {
++		/* LEGACY SCAN TRIGGER */
++		WL_SCAN((" LEGACY E-SCAN START\n"));
++
++#if defined(USE_INITIAL_SHORT_DWELL_TIME)
++		if (!request) {
++			err = -EINVAL;
++			goto exit;
++		}
++		if (ndev == bcmcfg_to_prmry_ndev(cfg) && g_first_broadcast_scan == true) {
++			is_first_init_2g_scan = true;
++			g_first_broadcast_scan = false;
++		}
++#endif 
++
++		/* if scan request is not empty parse scan request paramters */
++		if (request != NULL) {
++			n_channels = request->n_channels;
++			n_ssids = request->n_ssids;
++			if (n_channels % 2)
++				/* If n_channels is odd, add a padd of u16 */
++				params_size += sizeof(u16) * (n_channels + 1);
++			else
++				params_size += sizeof(u16) * n_channels;
++
++			/* Allocate space for populating ssids in wl_escan_params_t struct */
++			params_size += sizeof(struct wlc_ssid) * n_ssids;
++		}
++		params = (wl_escan_params_t *) kzalloc(params_size, GFP_KERNEL);
++		if (params == NULL) {
++			err = -ENOMEM;
++			goto exit;
++		}
++		wl_scan_prep(&params->params, request);
++
++#if defined(USE_INITIAL_SHORT_DWELL_TIME)
++		/* Override active_time to reduce scan time if it's first bradcast scan. */
++		if (is_first_init_2g_scan)
++			params->params.active_time = FIRST_SCAN_ACTIVE_DWELL_TIME_MS;
++#endif 
++
++		params->version = htod32(ESCAN_REQ_VERSION);
++		params->action =  htod16(action);
++		wl_escan_set_sync_id(params->sync_id, cfg);
++		wl_escan_set_type(cfg, WL_SCANTYPE_LEGACY);
++		if (params_size + sizeof("escan") >= WLC_IOCTL_MEDLEN) {
++			WL_ERR(("ioctl buffer length not sufficient\n"));
++			kfree(params);
++			err = -ENOMEM;
++			goto exit;
++		}
++		if (cfg->active_scan == PASSIVE_SCAN) {
++			params->params.scan_type = DOT11_SCANTYPE_PASSIVE;
++			WL_DBG(("Passive scan_type %d \n", params->params.scan_type));
++		}
++
++		bssidx = wl_get_bssidx_by_wdev(cfg, ndev->ieee80211_ptr);
++
++		err = wldev_iovar_setbuf(ndev, "escan", params, params_size,
++			cfg->escan_ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++		WL_ERR(("LEGACY_SCAN sync ID: %d, bssidx: %d\n", params->sync_id, bssidx));
++		if (unlikely(err)) {
++			if (err == BCME_EPERM)
++				/* Scan Not permitted at this point of time */
++				WL_DBG((" Escan not permitted at this time (%d)\n", err));
++			else
++				WL_ERR((" Escan set error (%d)\n", err));
++		} else {
++			DBG_EVENT_LOG(cfg->pub, WIFI_EVENT_DRIVER_SCAN_REQUESTED);
++		}
++		kfree(params);
++	}
++	else if (p2p_is_on(cfg) && p2p_scan(cfg)) {
++		/* P2P SCAN TRIGGER */
++		s32 _freq = 0;
++		n_nodfs = 0;
++		if (request && request->n_channels) {
++			num_chans = request->n_channels;
++			WL_SCAN((" chann number : %d\n", num_chans));
++			default_chan_list = kzalloc(num_chans * sizeof(*default_chan_list),
++				GFP_KERNEL);
++			if (default_chan_list == NULL) {
++				WL_ERR(("channel list allocation failed \n"));
++				err = -ENOMEM;
++				goto exit;
++			}
++			if (!wl_get_valid_channels(ndev, chan_buf, sizeof(chan_buf))) {
++				list = (wl_uint32_list_t *) chan_buf;
++				n_valid_chan = dtoh32(list->count);
++				for (i = 0; i < num_chans; i++)
++				{
++					_freq = request->channels[i]->center_freq;
++					channel = ieee80211_frequency_to_channel(_freq);
++
++					/* ignore DFS channels */
++					if (request->channels[i]->flags &
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
++						(IEEE80211_CHAN_NO_IR
++						| IEEE80211_CHAN_RADAR))
++#else
++						(IEEE80211_CHAN_RADAR
++						| IEEE80211_CHAN_PASSIVE_SCAN))
++#endif
++						continue;
++
++					for (j = 0; j < n_valid_chan; j++) {
++						/* allows only supported channel on
++						*  current reguatory
++						*/
++						if (channel == (dtoh32(list->element[j])))
++							default_chan_list[n_nodfs++] =
++								channel;
++					}
++
++				}
++			}
++			if (num_chans == SOCIAL_CHAN_CNT && (
++						(default_chan_list[0] == SOCIAL_CHAN_1) &&
++						(default_chan_list[1] == SOCIAL_CHAN_2) &&
++						(default_chan_list[2] == SOCIAL_CHAN_3))) {
++				/* SOCIAL CHANNELS 1, 6, 11 */
++				search_state = WL_P2P_DISC_ST_SEARCH;
++				p2p_scan_purpose = P2P_SCAN_SOCIAL_CHANNEL;
++				WL_INFORM(("P2P SEARCH PHASE START \n"));
++			} else if (((dev = wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_CONNECTION1)) &&
++				(wl_get_mode_by_netdev(cfg, dev) == WL_MODE_AP)) ||
++				((dev = wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_CONNECTION2)) &&
++				(wl_get_mode_by_netdev(cfg, dev) == WL_MODE_AP))) {
++				/* If you are already a GO, then do SEARCH only */
++				WL_INFORM(("Already a GO. Do SEARCH Only"));
++				search_state = WL_P2P_DISC_ST_SEARCH;
++				num_chans = n_nodfs;
++				p2p_scan_purpose = P2P_SCAN_NORMAL;
++
++			} else if (num_chans == 1) {
++				p2p_scan_purpose = P2P_SCAN_CONNECT_TRY;
++			} else if (num_chans == SOCIAL_CHAN_CNT + 1) {
++			/* SOCIAL_CHAN_CNT + 1 takes care of the Progressive scan supported by
++			 * the supplicant
++			 */
++				p2p_scan_purpose = P2P_SCAN_SOCIAL_CHANNEL;
++			} else {
++				WL_INFORM(("P2P SCAN STATE START \n"));
++				num_chans = n_nodfs;
++				p2p_scan_purpose = P2P_SCAN_NORMAL;
++			}
++		} else {
++			err = -EINVAL;
++			goto exit;
++		}
++		err = wl_cfgp2p_escan(cfg, ndev, ACTIVE_SCAN, num_chans, default_chan_list,
++			search_state, action,
++			wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE), NULL,
++			p2p_scan_purpose);
++
++		if (!err)
++			cfg->p2p->search_state = search_state;
++
++		kfree(default_chan_list);
++	}
++exit:
++	if (unlikely(err)) {
++		/* Don't print Error incase of Scan suppress */
++		if ((err == BCME_EPERM) && cfg->scan_suppressed)
++			WL_DBG(("Escan failed: Scan Suppressed \n"));
++		else
++			WL_ERR(("error (%d)\n", err));
++	}
++	return err;
++}
++
++
++static s32
++wl_do_escan(struct bcm_cfg80211 *cfg, struct wiphy *wiphy, struct net_device *ndev,
++	struct cfg80211_scan_request *request)
++{
++	s32 err = BCME_OK;
++	s32 passive_scan;
++	s32 passive_scan_time;
++	s32 passive_scan_time_org;
++	wl_scan_results_t *results;
++	WL_SCAN(("Enter \n"));
++	mutex_lock(&cfg->usr_sync);
++
++	results = wl_escan_get_buf(cfg, FALSE);
++	results->version = 0;
++	results->count = 0;
++	results->buflen = WL_SCAN_RESULTS_FIXED_SIZE;
++
++	cfg->escan_info.ndev = ndev;
++	cfg->escan_info.wiphy = wiphy;
++	cfg->escan_info.escan_state = WL_ESCAN_STATE_SCANING;
++	passive_scan = cfg->active_scan ? 0 : 1;
++	err = wldev_ioctl(ndev, WLC_SET_PASSIVE_SCAN,
++		&passive_scan, sizeof(passive_scan), true);
++	if (unlikely(err)) {
++		WL_ERR(("error (%d)\n", err));
++		goto exit;
++	}
++
++	if (passive_channel_skip) {
++
++		err = wldev_ioctl(ndev, WLC_GET_SCAN_PASSIVE_TIME,
++			&passive_scan_time_org, sizeof(passive_scan_time_org), false);
++		if (unlikely(err)) {
++			WL_ERR(("== error (%d)\n", err));
++			goto exit;
++		}
++
++		WL_SCAN(("PASSIVE SCAN time : %d \n", passive_scan_time_org));
++
++		passive_scan_time = 0;
++		err = wldev_ioctl(ndev, WLC_SET_SCAN_PASSIVE_TIME,
++			&passive_scan_time, sizeof(passive_scan_time), true);
++		if (unlikely(err)) {
++			WL_ERR(("== error (%d)\n", err));
++			goto exit;
++		}
++
++		WL_SCAN(("PASSIVE SCAN SKIPED!! (passive_channel_skip:%d) \n",
++			passive_channel_skip));
++	}
++
++	err = wl_run_escan(cfg, ndev, request, WL_SCAN_ACTION_START);
++
++	if (passive_channel_skip) {
++		err = wldev_ioctl(ndev, WLC_SET_SCAN_PASSIVE_TIME,
++			&passive_scan_time_org, sizeof(passive_scan_time_org), true);
++		if (unlikely(err)) {
++			WL_ERR(("== error (%d)\n", err));
++			goto exit;
++		}
++
++		WL_SCAN(("PASSIVE SCAN RECOVERED!! (passive_scan_time_org:%d) \n",
++			passive_scan_time_org));
++	}
++
++exit:
++	mutex_unlock(&cfg->usr_sync);
++	return err;
++}
++
++static s32
++__wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
++	struct cfg80211_scan_request *request,
++	struct cfg80211_ssid *this_ssid)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct cfg80211_ssid *ssids;
++	struct ether_addr primary_mac;
++	bool p2p_ssid;
++#ifdef WL11U
++	bcm_tlv_t *interworking_ie;
++#endif
++	s32 err = 0;
++	s32 bssidx = -1;
++	s32 i;
++
++	unsigned long flags;
++	static s32 busy_count = 0;
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++	struct net_device *remain_on_channel_ndev = NULL;
++#endif
++
++	/*
++	 * Hostapd triggers scan before starting automatic channel selection
++	 * to collect channel characteristics. However firmware scan engine
++	 * doesn't support any channel characteristics collection along with
++	 * scan. Hence return scan success.
++	 */
++	if (request && (scan_req_iftype(request) == NL80211_IFTYPE_AP)) {
++		WL_INFORM(("Scan Command on SoftAP Interface. Ignoring...\n"));
++		return 0;
++	}
++
++	ndev = ndev_to_wlc_ndev(ndev, cfg);
++
++	if (WL_DRV_STATUS_SENDING_AF_FRM_EXT(cfg)) {
++		WL_ERR(("Sending Action Frames. Try it again.\n"));
++		return -EAGAIN;
++	}
++
++	WL_DBG(("Enter wiphy (%p)\n", wiphy));
++	if (wl_get_drv_status_all(cfg, SCANNING)) {
++		if (cfg->scan_request == NULL) {
++			wl_clr_drv_status_all(cfg, SCANNING);
++			WL_DBG(("<<<<<<<<<<<Force Clear Scanning Status>>>>>>>>>>>\n"));
++		} else {
++			WL_ERR(("Scanning already\n"));
++			return -EAGAIN;
++		}
++	}
++	if (wl_get_drv_status(cfg, SCAN_ABORTING, ndev)) {
++		WL_ERR(("Scanning being aborted\n"));
++		return -EAGAIN;
++	}
++	if (request && request->n_ssids > WL_SCAN_PARAMS_SSID_MAX) {
++		WL_ERR(("request null or n_ssids > WL_SCAN_PARAMS_SSID_MAX\n"));
++		return -EOPNOTSUPP;
++	}
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++	remain_on_channel_ndev = wl_cfg80211_get_remain_on_channel_ndev(cfg);
++	if (remain_on_channel_ndev) {
++		WL_DBG(("Remain_on_channel bit is set, somehow it didn't get cleared\n"));
++		wl_notify_escan_complete(cfg, remain_on_channel_ndev, true, true);
++	}
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++
++
++	/* Arm scan timeout timer */
++	mod_timer(&cfg->scan_timeout, jiffies + msecs_to_jiffies(WL_SCAN_TIMER_INTERVAL_MS));
++	if (request) {		/* scan bss */
++		ssids = request->ssids;
++		p2p_ssid = false;
++		for (i = 0; i < request->n_ssids; i++) {
++			if (ssids[i].ssid_len &&
++				IS_P2P_SSID(ssids[i].ssid, ssids[i].ssid_len)) {
++				p2p_ssid = true;
++				break;
++			}
++		}
++		if (p2p_ssid) {
++			if (cfg->p2p_supported) {
++				/* p2p scan trigger */
++				if (p2p_on(cfg) == false) {
++					/* p2p on at the first time */
++					p2p_on(cfg) = true;
++					wl_cfgp2p_set_firm_p2p(cfg);
++					get_primary_mac(cfg, &primary_mac);
++					wl_cfgp2p_generate_bss_mac(cfg, &primary_mac);
++#if defined(P2P_IE_MISSING_FIX)
++					cfg->p2p_prb_noti = false;
++#endif
++				}
++				wl_clr_p2p_status(cfg, GO_NEG_PHASE);
++				WL_DBG(("P2P: GO_NEG_PHASE status cleared \n"));
++				p2p_scan(cfg) = true;
++			}
++		} else {
++			/* legacy scan trigger
++			 * So, we have to disable p2p discovery if p2p discovery is on
++			 */
++			if (cfg->p2p_supported) {
++				p2p_scan(cfg) = false;
++				/* If Netdevice is not equals to primary and p2p is on
++				*  , we will do p2p scan using P2PAPI_BSSCFG_DEVICE.
++				*/
++
++				if (p2p_scan(cfg) == false) {
++					if (wl_get_p2p_status(cfg, DISCOVERY_ON)) {
++						err = wl_cfgp2p_discover_enable_search(cfg,
++						false);
++						if (unlikely(err)) {
++							goto scan_out;
++						}
++
++					}
++				}
++			}
++			if (!cfg->p2p_supported || !p2p_scan(cfg)) {
++				if ((bssidx = wl_get_bssidx_by_wdev(cfg,
++					ndev->ieee80211_ptr)) < 0) {
++					WL_ERR(("Find p2p index from ndev(%p) failed\n",
++						ndev));
++					err = BCME_ERROR;
++					goto scan_out;
++				}
++#ifdef WL11U
++				if ((interworking_ie = wl_cfg80211_find_interworking_ie(
++					(u8 *)request->ie, request->ie_len)) != NULL) {
++					err = wl_cfg80211_add_iw_ie(cfg, ndev, bssidx,
++					       VNDR_IE_CUSTOM_FLAG, interworking_ie->id,
++					       interworking_ie->data, interworking_ie->len);
++
++					if (unlikely(err)) {
++						goto scan_out;
++					}
++				} else if (cfg->iw_ie_len != 0) {
++				/* we have to clear IW IE and disable gratuitous APR */
++					wl_cfg80211_add_iw_ie(cfg, ndev, bssidx,
++						VNDR_IE_CUSTOM_FLAG,
++						DOT11_MNG_INTERWORKING_ID,
++						0, 0);
++
++					(void)wldev_iovar_setint_bsscfg(ndev, "grat_arp", 0,
++						bssidx);
++					cfg->wl11u = FALSE;
++					cfg->iw_ie_len = 0;
++					memset(cfg->iw_ie, 0, IW_IES_MAX_BUF_LEN);
++					/* we don't care about error */
++				}
++#endif /* WL11U */
++				err = wl_cfg80211_set_mgmt_vndr_ies(cfg, ndev_to_cfgdev(ndev),
++					bssidx, VNDR_IE_PRBREQ_FLAG, request->ie,
++					request->ie_len);
++
++				if (unlikely(err)) {
++					goto scan_out;
++				}
++
++			}
++		}
++	} else {		/* scan in ibss */
++		ssids = this_ssid;
++	}
++
++	if (request && cfg->p2p_supported && !p2p_scan(cfg)) {
++		WL_TRACE_HW4(("START SCAN\n"));
++		DHD_OS_SCAN_WAKE_LOCK_TIMEOUT((dhd_pub_t *)(cfg->pub),
++			SCAN_WAKE_LOCK_TIMEOUT);
++	}
++
++	if (cfg->p2p_supported) {
++		if (p2p_on(cfg) && p2p_scan(cfg)) {
++
++			/* find my listen channel */
++			cfg->afx_hdl->my_listen_chan =
++				wl_find_listen_channel(cfg, request->ie,
++				request->ie_len);
++			err = wl_cfgp2p_enable_discovery(cfg, ndev,
++			request->ie, request->ie_len);
++
++			if (unlikely(err)) {
++				goto scan_out;
++			}
++		}
++	}
++	err = wl_do_escan(cfg, wiphy, ndev, request);
++	if (likely(!err))
++		goto scan_success;
++	else
++		goto scan_out;
++
++scan_success:
++	busy_count = 0;
++	cfg->scan_request = request;
++	wl_set_drv_status(cfg, SCANNING, ndev);
++
++	return 0;
++
++scan_out:
++	if (err == BCME_BUSY || err == BCME_NOTREADY) {
++		WL_ERR(("Scan err = (%d), busy?%d", err, -EBUSY));
++		err = -EBUSY;
++	} else if ((err == BCME_EPERM) && cfg->scan_suppressed) {
++		WL_ERR(("Scan not permitted due to scan suppress\n"));
++		err = -EPERM;
++	} else {
++		/* For all other fw errors, use a generic error code as return
++		 * value to cfg80211 stack
++		 */
++		err = -EAGAIN;
++	}
++
++#define SCAN_EBUSY_RETRY_LIMIT 10
++	if (err == -EBUSY) {
++		if (busy_count++ > SCAN_EBUSY_RETRY_LIMIT) {
++			struct ether_addr bssid;
++			s32 ret = 0;
++			busy_count = 0;
++			WL_ERR(("Unusual continuous EBUSY error, %d %d %d %d %d %d %d %d %d\n",
++				wl_get_drv_status(cfg, SCANNING, ndev),
++				wl_get_drv_status(cfg, SCAN_ABORTING, ndev),
++				wl_get_drv_status(cfg, CONNECTING, ndev),
++				wl_get_drv_status(cfg, CONNECTED, ndev),
++				wl_get_drv_status(cfg, DISCONNECTING, ndev),
++				wl_get_drv_status(cfg, AP_CREATING, ndev),
++				wl_get_drv_status(cfg, AP_CREATED, ndev),
++				wl_get_drv_status(cfg, SENDING_ACT_FRM, ndev),
++				wl_get_drv_status(cfg, SENDING_ACT_FRM, ndev)));
++
++			bzero(&bssid, sizeof(bssid));
++			if ((ret = wldev_ioctl(ndev, WLC_GET_BSSID,
++				&bssid, ETHER_ADDR_LEN, false)) == 0)
++				WL_ERR(("FW is connected with " MACDBG "/n",
++					MAC2STRDBG(bssid.octet)));
++			else
++				WL_ERR(("GET BSSID failed with %d\n", ret));
++
++			wl_cfg80211_scan_abort(cfg);
++
++		}
++	} else {
++		busy_count = 0;
++	}
++
++	wl_clr_drv_status(cfg, SCANNING, ndev);
++	if (timer_pending(&cfg->scan_timeout))
++		del_timer_sync(&cfg->scan_timeout);
++	DHD_OS_SCAN_WAKE_UNLOCK((dhd_pub_t *)(cfg->pub));
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++	cfg->scan_request = NULL;
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++
++	return err;
++}
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++static s32
++wl_cfg80211_scan(struct wiphy *wiphy, struct cfg80211_scan_request *request)
++#else
++static s32
++wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
++	struct cfg80211_scan_request *request)
++#endif /* WL_CFG80211_P2P_DEV_IF */
++{
++	s32 err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	struct net_device *ndev = wdev_to_wlc_ndev(request->wdev, cfg);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++	WL_DBG(("Enter\n"));
++	RETURN_EIO_IF_NOT_UP(cfg);
++
++	if (ndev == bcmcfg_to_prmry_ndev(cfg)) {
++		if (wl_cfg_multip2p_operational(cfg)) {
++			WL_ERR(("wlan0 scan failed, p2p devices are operational"));
++			 return -ENODEV;
++		}
++	}
++
++	err = __wl_cfg80211_scan(wiphy, ndev, request, NULL);
++	if (unlikely(err)) {
++		WL_ERR(("scan error (%d)\n", err));
++		return err;
++	}
++
++	return err;
++}
++
++static s32 wl_set_rts(struct net_device *dev, u32 rts_threshold)
++{
++	s32 err = 0;
++
++	err = wldev_iovar_setint(dev, "rtsthresh", rts_threshold);
++	if (unlikely(err)) {
++		WL_ERR(("Error (%d)\n", err));
++		return err;
++	}
++	return err;
++}
++
++static s32 wl_set_frag(struct net_device *dev, u32 frag_threshold)
++{
++	s32 err = 0;
++
++	err = wldev_iovar_setint_bsscfg(dev, "fragthresh", frag_threshold, 0);
++	if (unlikely(err)) {
++		WL_ERR(("Error (%d)\n", err));
++		return err;
++	}
++	return err;
++}
++
++static s32 wl_set_retry(struct net_device *dev, u32 retry, bool l)
++{
++	s32 err = 0;
++	u32 cmd = (l ? WLC_SET_LRL : WLC_SET_SRL);
++
++	retry = htod32(retry);
++	err = wldev_ioctl(dev, cmd, &retry, sizeof(retry), true);
++	if (unlikely(err)) {
++		WL_ERR(("cmd (%d) , error (%d)\n", cmd, err));
++		return err;
++	}
++	return err;
++}
++
++static s32 wl_cfg80211_set_wiphy_params(struct wiphy *wiphy, u32 changed)
++{
++	struct bcm_cfg80211 *cfg = (struct bcm_cfg80211 *)wiphy_priv(wiphy);
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	s32 err = 0;
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	WL_DBG(("Enter\n"));
++	if (changed & WIPHY_PARAM_RTS_THRESHOLD &&
++		(cfg->conf->rts_threshold != wiphy->rts_threshold)) {
++		cfg->conf->rts_threshold = wiphy->rts_threshold;
++		err = wl_set_rts(ndev, cfg->conf->rts_threshold);
++		if (err != BCME_OK)
++			return err;
++	}
++	if (changed & WIPHY_PARAM_FRAG_THRESHOLD &&
++		(cfg->conf->frag_threshold != wiphy->frag_threshold)) {
++		cfg->conf->frag_threshold = wiphy->frag_threshold;
++		err = wl_set_frag(ndev, cfg->conf->frag_threshold);
++		if (err != BCME_OK)
++			return err;
++	}
++	if (changed & WIPHY_PARAM_RETRY_LONG &&
++		(cfg->conf->retry_long != wiphy->retry_long)) {
++		cfg->conf->retry_long = wiphy->retry_long;
++		err = wl_set_retry(ndev, cfg->conf->retry_long, true);
++		if (err != BCME_OK)
++			return err;
++	}
++	if (changed & WIPHY_PARAM_RETRY_SHORT &&
++		(cfg->conf->retry_short != wiphy->retry_short)) {
++		cfg->conf->retry_short = wiphy->retry_short;
++		err = wl_set_retry(ndev, cfg->conf->retry_short, false);
++		if (err != BCME_OK) {
++			return err;
++		}
++	}
++
++	return err;
++}
++static chanspec_t
++channel_to_chanspec(struct wiphy *wiphy, struct net_device *dev, u32 channel, u32 bw_cap)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	u8 *buf = NULL;
++	wl_uint32_list_t *list;
++	int err = BCME_OK;
++	chanspec_t c = 0, ret_c = 0;
++	int bw = 0, tmp_bw = 0;
++	int i;
++	u32 tmp_c;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++#define LOCAL_BUF_SIZE	1024
++	buf = (u8 *) kzalloc(LOCAL_BUF_SIZE, kflags);
++	if (!buf) {
++		WL_ERR(("buf memory alloc failed\n"));
++		goto exit;
++	}
++
++	err = wldev_iovar_getbuf_bsscfg(dev, "chanspecs", NULL,
++		0, buf, LOCAL_BUF_SIZE, 0, &cfg->ioctl_buf_sync);
++	if (err != BCME_OK) {
++		WL_ERR(("get chanspecs failed with %d\n", err));
++		goto exit;
++	}
++
++	list = (wl_uint32_list_t *)(void *)buf;
++	for (i = 0; i < dtoh32(list->count); i++) {
++		c = dtoh32(list->element[i]);
++		if (channel <= CH_MAX_2G_CHANNEL) {
++			if (!CHSPEC_IS20(c))
++				continue;
++			if (channel == CHSPEC_CHANNEL(c)) {
++				ret_c = c;
++				bw = 20;
++				goto exit;
++			}
++		}
++		tmp_c = wf_chspec_ctlchan(c);
++		tmp_bw = bw2cap[CHSPEC_BW(c) >> WL_CHANSPEC_BW_SHIFT];
++		if (tmp_c != channel)
++			continue;
++
++		if ((tmp_bw > bw) && (tmp_bw <= bw_cap)) {
++			bw = tmp_bw;
++			ret_c = c;
++			if (bw == bw_cap)
++				goto exit;
++		}
++	}
++exit:
++	if (buf)
++		kfree(buf);
++#undef LOCAL_BUF_SIZE
++	WL_INFORM(("return chanspec %x %d\n", ret_c, bw));
++	return ret_c;
++}
++
++void
++wl_cfg80211_ibss_vsie_set_buffer(vndr_ie_setbuf_t *ibss_vsie, int ibss_vsie_len)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++
++	if (cfg != NULL && ibss_vsie != NULL) {
++		if (cfg->ibss_vsie != NULL) {
++			kfree(cfg->ibss_vsie);
++		}
++		cfg->ibss_vsie = ibss_vsie;
++		cfg->ibss_vsie_len = ibss_vsie_len;
++	}
++}
++
++static void
++wl_cfg80211_ibss_vsie_free(struct bcm_cfg80211 *cfg)
++{
++	/* free & initiralize VSIE (Vendor Specific IE) */
++	if (cfg->ibss_vsie != NULL) {
++		kfree(cfg->ibss_vsie);
++		cfg->ibss_vsie = NULL;
++		cfg->ibss_vsie_len = 0;
++	}
++}
++
++s32
++wl_cfg80211_ibss_vsie_delete(struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	char *ioctl_buf = NULL;
++	s32 ret = BCME_OK;
++
++	if (cfg != NULL && cfg->ibss_vsie != NULL) {
++		ioctl_buf = kmalloc(WLC_IOCTL_MEDLEN, GFP_KERNEL);
++		if (!ioctl_buf) {
++			WL_ERR(("ioctl memory alloc failed\n"));
++			return -ENOMEM;
++		}
++
++		/* change the command from "add" to "del" */
++		strncpy(cfg->ibss_vsie->cmd, "del", VNDR_IE_CMD_LEN - 1);
++		cfg->ibss_vsie->cmd[VNDR_IE_CMD_LEN - 1] = '\0';
++
++		ret = wldev_iovar_setbuf(dev, "ie",
++			cfg->ibss_vsie, cfg->ibss_vsie_len,
++			ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++		WL_ERR(("ret=%d\n", ret));
++
++		if (ret == BCME_OK) {
++			/* free & initiralize VSIE */
++			kfree(cfg->ibss_vsie);
++			cfg->ibss_vsie = NULL;
++			cfg->ibss_vsie_len = 0;
++		}
++
++		if (ioctl_buf) {
++			kfree(ioctl_buf);
++		}
++	}
++
++	return ret;
++}
++
++#ifdef WLAIBSS_MCHAN
++static bcm_struct_cfgdev*
++bcm_cfg80211_add_ibss_if(struct wiphy *wiphy, char *name)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct wireless_dev* wdev = NULL;
++	struct net_device *new_ndev = NULL;
++	struct net_device *primary_ndev = NULL;
++	s32 timeout;
++	wl_aibss_if_t aibss_if;
++	wl_if_event_info *event = NULL;
++
++	if (cfg->ibss_cfgdev != NULL) {
++		WL_ERR(("IBSS interface %s already exists\n", name));
++		return NULL;
++	}
++
++	WL_ERR(("Try to create IBSS interface %s\n", name));
++	primary_ndev = bcmcfg_to_prmry_ndev(cfg);
++	/* generate a new MAC address for the IBSS interface */
++	get_primary_mac(cfg, &cfg->ibss_if_addr);
++	cfg->ibss_if_addr.octet[4] ^= 0x40;
++	memset(&aibss_if, sizeof(aibss_if), 0);
++	memcpy(&aibss_if.addr, &cfg->ibss_if_addr, sizeof(aibss_if.addr));
++	aibss_if.chspec = 0;
++	aibss_if.len = sizeof(aibss_if);
++
++	cfg->bss_pending_op = TRUE;
++	memset(&cfg->if_event_info, 0, sizeof(cfg->if_event_info));
++	err = wldev_iovar_setbuf(primary_ndev, "aibss_ifadd", &aibss_if,
++		sizeof(aibss_if), cfg->ioctl_buf, WLC_IOCTL_MAXLEN, NULL);
++	if (err) {
++		WL_ERR(("IOVAR aibss_ifadd failed with error %d\n", err));
++		goto fail;
++	}
++	timeout = wait_event_interruptible_timeout(cfg->netif_change_event,
++		!cfg->bss_pending_op, msecs_to_jiffies(MAX_WAIT_TIME));
++	if (timeout <= 0 || cfg->bss_pending_op)
++		goto fail;
++
++	event = &cfg->if_event_info;
++	/* By calling wl_cfg80211_allocate_if (dhd_allocate_if eventually) we give the control
++	 * over this net_device interface to dhd_linux, hence the interface is managed by dhd_liux
++	 * and will be freed by dhd_detach unless it gets unregistered before that. The
++	 * wireless_dev instance new_ndev->ieee80211_ptr associated with this net_device will
++	 * be freed by wl_dealloc_netinfo
++	 */
++	new_ndev = wl_cfg80211_allocate_if(cfg, event->ifidx, event->name,
++		event->mac, event->bssidx, event->name);
++	if (new_ndev == NULL)
++		goto fail;
++	wdev = kzalloc(sizeof(*wdev), GFP_KERNEL);
++	if (wdev == NULL)
++		goto fail;
++	wdev->wiphy = wiphy;
++	wdev->iftype = NL80211_IFTYPE_ADHOC;
++	wdev->netdev = new_ndev;
++	new_ndev->ieee80211_ptr = wdev;
++	SET_NETDEV_DEV(new_ndev, wiphy_dev(wdev->wiphy));
++
++	/* rtnl lock must have been acquired, if this is not the case, wl_cfg80211_register_if
++	* needs to be modified to take one parameter (bool need_rtnl_lock)
++	 */
++	ASSERT_RTNL();
++	if (wl_cfg80211_register_if(cfg, event->ifidx, new_ndev) != BCME_OK)
++		goto fail;
++
++	wl_alloc_netinfo(cfg, new_ndev, wdev, WL_MODE_IBSS, PM_ENABLE, event->bssidx);
++	cfg->ibss_cfgdev = ndev_to_cfgdev(new_ndev);
++	WL_ERR(("IBSS interface %s created\n", new_ndev->name));
++	return cfg->ibss_cfgdev;
++
++fail:
++	WL_ERR(("failed to create IBSS interface %s \n", name));
++	cfg->bss_pending_op = FALSE;
++	if (new_ndev)
++		wl_cfg80211_remove_if(cfg, event->ifidx, new_ndev);
++	if (wdev)
++		kfree(wdev);
++	return NULL;
++}
++
++static s32
++bcm_cfg80211_del_ibss_if(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *ndev = NULL;
++	struct net_device *primary_ndev = NULL;
++	s32 timeout;
++
++	if (!cfgdev || cfg->ibss_cfgdev != cfgdev || ETHER_ISNULLADDR(&cfg->ibss_if_addr.octet))
++		return -EINVAL;
++	ndev = (struct net_device *)cfgdev_to_ndev(cfg->ibss_cfgdev);
++	primary_ndev = bcmcfg_to_prmry_ndev(cfg);
++
++	cfg->bss_pending_op = TRUE;
++	memset(&cfg->if_event_info, 0, sizeof(cfg->if_event_info));
++	err = wldev_iovar_setbuf(primary_ndev, "aibss_ifdel", &cfg->ibss_if_addr,
++		sizeof(cfg->ibss_if_addr), cfg->ioctl_buf, WLC_IOCTL_MAXLEN, NULL);
++	if (err) {
++		WL_ERR(("IOVAR aibss_ifdel failed with error %d\n", err));
++		goto fail;
++	}
++	timeout = wait_event_interruptible_timeout(cfg->netif_change_event,
++		!cfg->bss_pending_op, msecs_to_jiffies(MAX_WAIT_TIME));
++	if (timeout <= 0 || cfg->bss_pending_op) {
++		WL_ERR(("timeout in waiting IF_DEL event\n"));
++		goto fail;
++	}
++
++	wl_cfg80211_remove_if(cfg, cfg->if_event_info.ifidx, ndev);
++	cfg->ibss_cfgdev = NULL;
++	return 0;
++
++fail:
++	cfg->bss_pending_op = FALSE;
++	return -1;
++}
++#endif /* WLAIBSS_MCHAN */
++
++s32
++wl_cfg80211_interface_ops(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev, s32 bsscfg_idx,
++	enum nl80211_iftype iface_type, s32 del, u8 *addr)
++{
++	wl_interface_create_t iface;
++	s32 ret;
++	wl_interface_info_t *info;
++
++	bzero(&iface, sizeof(wl_interface_create_t));
++
++	iface.ver = WL_INTERFACE_CREATE_VER;
++
++	if (iface_type == NL80211_IFTYPE_AP)
++		iface.flags = WL_INTERFACE_CREATE_AP;
++	else
++		iface.flags = WL_INTERFACE_CREATE_STA;
++
++	if (del) {
++		ret = wldev_iovar_setbuf(ndev, "interface_remove",
++			NULL, 0, cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	} else {
++		if (addr) {
++			memcpy(&iface.mac_addr.octet, addr, ETH_ALEN);
++			iface.flags |= WL_INTERFACE_MAC_USE;
++		}
++		ret = wldev_iovar_getbuf(ndev, "interface_create",
++			&iface, sizeof(wl_interface_create_t),
++			cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++		if (ret == 0) {
++			/* success */
++			info = (wl_interface_info_t *)cfg->ioctl_buf;
++			WL_DBG(("wl interface create success!! bssidx:%d \n",
++				info->bsscfgidx));
++			ret = info->bsscfgidx;
++		}
++	}
++
++	if (ret < 0)
++		WL_ERR(("Interface %s failed!! ret %d\n",
++			del ? "remove" : "create", ret));
++
++	return ret;
++}
++
++
++s32
++wl_cfg80211_add_del_bss(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev, s32 bsscfg_idx,
++	enum nl80211_iftype iface_type, s32 del, u8 *addr)
++{
++	s32 ret = BCME_OK;
++	s32 val = 0;
++
++	struct {
++		s32 cfg;
++		s32 val;
++		struct ether_addr ea;
++	} bss_setbuf;
++
++	WL_INFORM(("iface_type:%d del:%d \n", iface_type, del));
++
++	bzero(&bss_setbuf, sizeof(bss_setbuf));
++
++	/* AP=3, STA=2, up=1, down=0, val=-1 */
++	if (del) {
++		val = -1;
++	} else if (iface_type == NL80211_IFTYPE_AP) {
++		/* AP Interface */
++		WL_DBG(("Adding AP Interface \n"));
++		val = 3;
++	} else if (iface_type == NL80211_IFTYPE_STATION) {
++		WL_DBG(("Adding STA Interface \n"));
++		val = 2;
++	} else {
++		WL_ERR((" add_del_bss NOT supported for IFACE type:0x%x", iface_type));
++		return -EINVAL;
++	}
++
++	bss_setbuf.cfg = htod32(bsscfg_idx);
++	bss_setbuf.val = htod32(val);
++
++	if (addr) {
++		memcpy(&bss_setbuf.ea.octet, addr, ETH_ALEN);
++	}
++
++	ret = wldev_iovar_setbuf(ndev, "bss", &bss_setbuf, sizeof(bss_setbuf),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++	if (ret != 0)
++		WL_ERR(("'bss %d' failed with %d\n", val, ret));
++
++	return ret;
++}
++
++#if defined(WL_VIRTUAL_APSTA) || defined(DUAL_STA_STATIC_IF)
++/* Create a Generic Network Interface and initialize it depending up on
++ * the interface type
++ */
++bcm_struct_cfgdev*
++wl_cfg80211_create_iface(struct wiphy *wiphy,
++	enum nl80211_iftype iface_type,
++	u8 *mac_addr, const char *name)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *new_ndev = NULL;
++	struct net_device *primary_ndev = NULL;
++	s32 ret = BCME_OK;
++	s32 bsscfg_idx = 0;
++	u32 timeout;
++	wl_if_event_info *event = NULL;
++	struct wireless_dev *wdev = NULL;
++	u8 addr[ETH_ALEN];
++
++	WL_DBG(("Enter\n"));
++
++	if (!name) {
++		WL_ERR(("Interface name not provided\n"));
++		return NULL;
++	}
++
++	primary_ndev = bcmcfg_to_prmry_ndev(cfg);
++
++	if (likely(!mac_addr)) {
++		/* Use primary MAC with the locally administered bit for the
++		 *  Secondary STA I/F
++		 */
++		memcpy(addr, primary_ndev->dev_addr, ETH_ALEN);
++		addr[0] |= 0x02;
++	} else {
++		/* Use the application provided mac address (if any) */
++		memcpy(addr, mac_addr, ETH_ALEN);
++	}
++
++	if ((iface_type != NL80211_IFTYPE_STATION) && (iface_type != NL80211_IFTYPE_AP)) {
++		WL_ERR(("IFACE type:%d not supported. STA "
++					"or AP IFACE is only supported\n", iface_type));
++		return NULL;
++	}
++
++	cfg->bss_pending_op = TRUE;
++	memset(&cfg->if_event_info, 0, sizeof(cfg->if_event_info));
++
++	/* De-initialize the p2p discovery interface, if operational */
++	if (p2p_is_on(cfg)) {
++		WL_DBG(("Disabling P2P Discovery Interface \n"));
++#ifdef WL_CFG80211_P2P_DEV_IF
++		ret = wl_cfg80211_scan_stop(bcmcfg_to_p2p_wdev(cfg));
++#else
++		ret = wl_cfg80211_scan_stop(cfg->p2p_net);
++#endif
++		if (unlikely(ret < 0)) {
++			CFGP2P_ERR(("P2P scan stop failed, ret=%d\n", ret));
++		}
++
++		wl_cfgp2p_disable_discovery(cfg);
++		wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE) = 0;
++		p2p_on(cfg) = false;
++	}
++
++	/*
++	 * Intialize the firmware I/F.
++	 */
++	ret = wl_cfg80211_interface_ops(cfg, primary_ndev, bsscfg_idx,
++		NL80211_IFTYPE_STATION, 0, addr);
++	if (ret == BCME_UNSUPPORTED) {
++		/* Use bssidx 1 by default */
++		bsscfg_idx = 1;
++		if ((ret = wl_cfg80211_add_del_bss(cfg, primary_ndev,
++			bsscfg_idx, iface_type, 0, addr)) < 0) {
++			return NULL;
++		}
++	} else if (ret < 0) {
++		WL_ERR(("Interface create failed!! ret:%d \n", ret));
++		goto fail;
++	} else {
++		/* Success */
++		bsscfg_idx = ret;
++	}
++
++	WL_DBG(("Interface created!! bssidx:%d \n", bsscfg_idx));
++
++	/*
++	 * Wait till the firmware send a confirmation event back.
++	 */
++	WL_DBG(("Wait for the FW I/F Event\n"));
++	timeout = wait_event_interruptible_timeout(cfg->netif_change_event,
++		!cfg->bss_pending_op, msecs_to_jiffies(MAX_WAIT_TIME));
++	if (timeout <= 0 || cfg->bss_pending_op) {
++		WL_ERR(("ADD_IF event, didn't come. Return \n"));
++		goto fail;
++	}
++
++	/*
++	 * Since FW operation is successful,we can go ahead with the
++	 * the host interface creation.
++	 */
++	event = &cfg->if_event_info;
++	new_ndev = wl_cfg80211_allocate_if(cfg, event->ifidx,
++		(char*)name, addr, event->bssidx, event->name);
++	if (!new_ndev) {
++		WL_ERR(("I/F allocation failed! \n"));
++		goto fail;
++	} else
++		WL_DBG(("I/F allocation succeeded! ifidx:0x%x bssidx:0x%x \n",
++		 event->ifidx, event->bssidx));
++
++	wdev = kzalloc(sizeof(*wdev), GFP_KERNEL);
++	if (!wdev) {
++		WL_ERR(("wireless_dev alloc failed! \n"));
++		goto fail;
++	}
++
++	wdev->wiphy = wiphy;
++	wdev->iftype = iface_type;
++	new_ndev->ieee80211_ptr = wdev;
++	SET_NETDEV_DEV(new_ndev, wiphy_dev(wdev->wiphy));
++
++	/* RTNL lock must have been acquired. */
++	ASSERT_RTNL();
++
++	/* Set the locally administed mac addr, if not applied already */
++	if (memcmp(addr, event->mac, ETH_ALEN) != 0) {
++		ret = wldev_iovar_setbuf_bsscfg(primary_ndev, "cur_etheraddr",
++			addr, ETH_ALEN, cfg->ioctl_buf, WLC_IOCTL_MAXLEN,
++			event->bssidx, &cfg->ioctl_buf_sync);
++		if (unlikely(ret)) {
++				WL_ERR(("set cur_etheraddr Error (%d)\n", ret));
++				goto fail;
++		}
++		memcpy(new_ndev->dev_addr, addr, ETH_ALEN);
++	}
++
++	if (wl_cfg80211_register_if(cfg, event->ifidx, new_ndev) != BCME_OK) {
++		WL_ERR(("IFACE register failed \n"));
++		goto fail;
++	}
++
++	/* Initialize with the station mode params */
++	wl_alloc_netinfo(cfg, new_ndev, wdev,
++		(iface_type == NL80211_IFTYPE_STATION) ?
++		WL_MODE_BSS : WL_MODE_AP, PM_ENABLE, event->bssidx);
++	cfg->bss_cfgdev = ndev_to_cfgdev(new_ndev);
++	cfg->cfgdev_bssidx = event->bssidx;
++
++	WL_DBG(("Host Network Interface for Secondary I/F created"));
++
++	return cfg->bss_cfgdev;
++
++fail:
++	cfg->bss_pending_op = FALSE;
++	cfg->cfgdev_bssidx = -1;
++	if (wdev)
++		kfree(wdev);
++	if (new_ndev)
++		wl_cfg80211_remove_if(cfg, event->ifidx, new_ndev);
++
++	return NULL;
++}
++
++s32
++wl_cfg80211_del_iface(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *ndev = NULL;
++	struct net_device *primary_ndev = NULL;
++	s32 ret = BCME_OK;
++	s32 bsscfg_idx = 1;
++	u32 timeout;
++	u32 ifidx;
++	enum nl80211_iftype iface_type = NL80211_IFTYPE_STATION;
++
++	WL_DBG(("Enter\n"));
++
++	if (!cfg->bss_cfgdev)
++		return 0;
++
++	/* If any scan is going on, abort it */
++	if (wl_get_drv_status_all(cfg, SCANNING)) {
++		WL_DBG(("Scan in progress. Aborting the scan!\n"));
++		wl_notify_escan_complete(cfg, cfg->escan_info.ndev, true, true);
++	}
++
++	ndev = (struct net_device *)cfgdev_to_ndev(cfg->bss_cfgdev);
++	primary_ndev = bcmcfg_to_prmry_ndev(cfg);
++
++	cfg->bss_pending_op = TRUE;
++	memset(&cfg->if_event_info, 0, sizeof(cfg->if_event_info));
++
++	/* Delete the firmware interface. "interface_remove" command
++	 * should go on the interface to be deleted
++	 */
++	ret = wl_cfg80211_interface_ops(cfg, ndev, cfg->cfgdev_bssidx,
++		NL80211_IFTYPE_STATION, 1, NULL);
++	if (ret == BCME_UNSUPPORTED) {
++		if ((ret = wl_cfg80211_add_del_bss(cfg, ndev,
++			bsscfg_idx, iface_type, true, NULL)) < 0) {
++			WL_ERR(("DEL bss failed ret:%d \n", ret));
++			goto exit;
++		}
++	} else if (ret < 0) {
++		WL_ERR(("Interface DEL failed ret:%d \n", ret));
++		goto exit;
++	}
++
++	timeout = wait_event_interruptible_timeout(cfg->netif_change_event,
++		!cfg->bss_pending_op, msecs_to_jiffies(MAX_WAIT_TIME));
++	if (timeout <= 0 || cfg->bss_pending_op) {
++		WL_ERR(("timeout in waiting IF_DEL event\n"));
++	}
++
++exit:
++	ifidx = dhd_net2idx(((struct dhd_pub *)(cfg->pub))->info, ndev);
++	wl_cfg80211_remove_if(cfg, ifidx, ndev);
++	cfg->bss_cfgdev = NULL;
++	cfg->cfgdev_bssidx = -1;
++	cfg->bss_pending_op = FALSE;
++
++	WL_DBG(("IF_DEL Done.\n"));
++
++	return ret;
++}
++#endif /* defined(WL_VIRTUAL_APSTA) || defined(DUAL_STA_STATIC_IF) */
++
++static s32
++wl_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_ibss_params *params)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct cfg80211_bss *bss;
++	struct ieee80211_channel *chan;
++	struct wl_join_params join_params;
++	int scan_suppress;
++	struct cfg80211_ssid ssid;
++	s32 scan_retry = 0;
++	s32 err = 0;
++	size_t join_params_size;
++	chanspec_t chanspec = 0;
++	u32 param[2] = {0, 0};
++	u32 bw_cap = 0;
++
++	WL_TRACE(("In\n"));
++	RETURN_EIO_IF_NOT_UP(cfg);
++	WL_INFORM(("JOIN BSSID:" MACDBG "\n", MAC2STRDBG(params->bssid)));
++	if (!params->ssid || params->ssid_len <= 0) {
++		WL_ERR(("Invalid parameter\n"));
++		return -EINVAL;
++	}
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	chan = params->chandef.chan;
++#else
++	chan = params->channel;
++#endif /* WL_CFG80211_P2P_DEV_IF */
++	if (chan)
++		cfg->channel = ieee80211_frequency_to_channel(chan->center_freq);
++	if (wl_get_drv_status(cfg, CONNECTED, dev)) {
++		struct wlc_ssid *lssid = (struct wlc_ssid *)wl_read_prof(cfg, dev, WL_PROF_SSID);
++		u8 *bssid = (u8 *)wl_read_prof(cfg, dev, WL_PROF_BSSID);
++		u32 *channel = (u32 *)wl_read_prof(cfg, dev, WL_PROF_CHAN);
++		if (!params->bssid || ((memcmp(params->bssid, bssid, ETHER_ADDR_LEN) == 0) &&
++			(memcmp(params->ssid, lssid->SSID, lssid->SSID_len) == 0) &&
++			(*channel == cfg->channel))) {
++			WL_ERR(("Connection already existed to " MACDBG "\n",
++				MAC2STRDBG((u8 *)wl_read_prof(cfg, dev, WL_PROF_BSSID))));
++			return -EISCONN;
++		}
++		WL_ERR(("Ignore Previous connecton to %s (" MACDBG ")\n",
++			lssid->SSID, MAC2STRDBG(bssid)));
++	}
++
++	/* remove the VSIE */
++	wl_cfg80211_ibss_vsie_delete(dev);
++
++	bss = cfg80211_get_ibss(wiphy, NULL, params->ssid, params->ssid_len);
++	if (!bss) {
++		if (IBSS_INITIAL_SCAN_ALLOWED == TRUE) {
++			memcpy(ssid.ssid, params->ssid, params->ssid_len);
++			ssid.ssid_len = params->ssid_len;
++			do {
++				if (unlikely
++					(__wl_cfg80211_scan(wiphy, dev, NULL, &ssid) ==
++					 -EBUSY)) {
++					wl_delay(150);
++				} else {
++					break;
++				}
++			} while (++scan_retry < WL_SCAN_RETRY_MAX);
++
++			/* rtnl lock code is removed here. don't see why rtnl lock
++			 * needs to be released.
++			 */
++
++			/* wait 4 secons till scan done.... */
++			schedule_timeout_interruptible(msecs_to_jiffies(4000));
++
++			bss = cfg80211_get_ibss(wiphy, NULL,
++				params->ssid, params->ssid_len);
++		}
++	}
++	if (bss && ((IBSS_COALESCE_ALLOWED == TRUE) ||
++		((IBSS_COALESCE_ALLOWED == FALSE) && params->bssid &&
++		!memcmp(bss->bssid, params->bssid, ETHER_ADDR_LEN)))) {
++		cfg->ibss_starter = false;
++		WL_DBG(("Found IBSS\n"));
++	} else {
++		cfg->ibss_starter = true;
++	}
++	if (chan) {
++		if (chan->band == IEEE80211_BAND_5GHZ)
++			param[0] = WLC_BAND_5G;
++		else if (chan->band == IEEE80211_BAND_2GHZ)
++			param[0] = WLC_BAND_2G;
++		err = wldev_iovar_getint(dev, "bw_cap", param);
++		if (unlikely(err)) {
++			WL_ERR(("Get bw_cap Failed (%d)\n", err));
++			return err;
++		}
++		bw_cap = param[0];
++		chanspec = channel_to_chanspec(wiphy, dev, cfg->channel, bw_cap);
++	}
++	/*
++	 * Join with specific BSSID and cached SSID
++	 * If SSID is zero join based on BSSID only
++	 */
++	memset(&join_params, 0, sizeof(join_params));
++	memcpy((void *)join_params.ssid.SSID, (void *)params->ssid,
++		params->ssid_len);
++	join_params.ssid.SSID_len = htod32(params->ssid_len);
++	if (params->bssid) {
++		memcpy(&join_params.params.bssid, params->bssid, ETHER_ADDR_LEN);
++		err = wldev_ioctl(dev, WLC_SET_DESIRED_BSSID, &join_params.params.bssid,
++			ETHER_ADDR_LEN, true);
++		if (unlikely(err)) {
++			WL_ERR(("Error (%d)\n", err));
++			return err;
++		}
++	} else
++		memset(&join_params.params.bssid, 0, ETHER_ADDR_LEN);
++	wldev_iovar_setint(dev, "ibss_coalesce_allowed", IBSS_COALESCE_ALLOWED);
++
++	if (IBSS_INITIAL_SCAN_ALLOWED == FALSE) {
++		scan_suppress = TRUE;
++		/* Set the SCAN SUPPRESS Flag in the firmware to skip join scan */
++		err = wldev_ioctl(dev, WLC_SET_SCANSUPPRESS,
++			&scan_suppress, sizeof(int), true);
++		if (unlikely(err)) {
++			WL_ERR(("Scan Suppress Setting Failed (%d)\n", err));
++			return err;
++		}
++	}
++
++	join_params.params.chanspec_list[0] = chanspec;
++	join_params.params.chanspec_num = 1;
++	wldev_iovar_setint(dev, "chanspec", chanspec);
++	join_params_size = sizeof(join_params);
++
++	/* Disable Authentication, IBSS will add key if it required */
++	wldev_iovar_setint(dev, "wpa_auth", WPA_AUTH_DISABLED);
++	wldev_iovar_setint(dev, "wsec", 0);
++
++
++	err = wldev_ioctl(dev, WLC_SET_SSID, &join_params,
++		join_params_size, true);
++	if (unlikely(err)) {
++		WL_ERR(("Error (%d)\n", err));
++		return err;
++	}
++
++	if (IBSS_INITIAL_SCAN_ALLOWED == FALSE) {
++		scan_suppress = FALSE;
++		/* Reset the SCAN SUPPRESS Flag */
++		err = wldev_ioctl(dev, WLC_SET_SCANSUPPRESS,
++			&scan_suppress, sizeof(int), true);
++		if (unlikely(err)) {
++			WL_ERR(("Reset Scan Suppress Flag Failed (%d)\n", err));
++			return err;
++		}
++	}
++	wl_update_prof(cfg, dev, NULL, &join_params.ssid, WL_PROF_SSID);
++	wl_update_prof(cfg, dev, NULL, &cfg->channel, WL_PROF_CHAN);
++	cfg->rmc_event_seq = 0; /* initialize rmcfail sequence */
++	return err;
++}
++
++static s32 wl_cfg80211_leave_ibss(struct wiphy *wiphy, struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 err = 0;
++	scb_val_t scbval;
++	u8 *curbssid;
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	wl_link_down(cfg);
++
++	WL_ERR(("Leave IBSS\n"));
++	curbssid = wl_read_prof(cfg, dev, WL_PROF_BSSID);
++	wl_set_drv_status(cfg, DISCONNECTING, dev);
++	scbval.val = 0;
++	memcpy(&scbval.ea, curbssid, ETHER_ADDR_LEN);
++	err = wldev_ioctl(dev, WLC_DISASSOC, &scbval,
++		sizeof(scb_val_t), true);
++	if (unlikely(err)) {
++		wl_clr_drv_status(cfg, DISCONNECTING, dev);
++		WL_ERR(("error(%d)\n", err));
++		return err;
++	}
++
++	/* remove the VSIE */
++	wl_cfg80211_ibss_vsie_delete(dev);
++
++	return err;
++}
++
++#ifdef MFP
++static int wl_cfg80211_get_rsn_capa(bcm_tlv_t *wpa2ie, u8* capa)
++{
++	u16 suite_count;
++	wpa_suite_mcast_t *mcast;
++	wpa_suite_ucast_t *ucast;
++	u16 len;
++	wpa_suite_auth_key_mgmt_t *mgmt;
++
++	if (!wpa2ie)
++		return -1;
++
++	len = wpa2ie->len;
++	mcast = (wpa_suite_mcast_t *)&wpa2ie->data[WPA2_VERSION_LEN];
++	if ((len -= WPA_SUITE_LEN) <= 0)
++		return BCME_BADLEN;
++	ucast = (wpa_suite_ucast_t *)&mcast[1];
++	suite_count = ltoh16_ua(&ucast->count);
++	if ((suite_count > NL80211_MAX_NR_CIPHER_SUITES) ||
++		(len -= (WPA_IE_SUITE_COUNT_LEN +
++		(WPA_SUITE_LEN * suite_count))) <= 0)
++		return BCME_BADLEN;
++	mgmt = (wpa_suite_auth_key_mgmt_t *)&ucast->list[suite_count];
++	suite_count = ltoh16_ua(&mgmt->count);
++
++	if ((suite_count > NL80211_MAX_NR_CIPHER_SUITES) ||
++		(len -= (WPA_IE_SUITE_COUNT_LEN +
++		(WPA_SUITE_LEN * suite_count))) >= RSN_CAP_LEN) {
++		capa[0] = *(u8 *)&mgmt->list[suite_count];
++		capa[1] = *((u8 *)&mgmt->list[suite_count] + 1);
++	} else
++		return BCME_BADLEN;
++
++	return 0;
++}
++#endif /* MFP */
++
++static s32
++wl_set_wpa_version(struct net_device *dev, struct cfg80211_connect_params *sme)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	struct wl_security *sec;
++	s32 val = 0;
++	s32 err = 0;
++	s32 bssidx;
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	if (sme->crypto.wpa_versions & NL80211_WPA_VERSION_1)
++		val = WPA_AUTH_PSK |
++			WPA_AUTH_UNSPECIFIED;
++	else if (sme->crypto.wpa_versions & NL80211_WPA_VERSION_2)
++		val = WPA2_AUTH_PSK|
++			WPA2_AUTH_UNSPECIFIED;
++	else
++		val = WPA_AUTH_DISABLED;
++
++	if (is_wps_conn(sme))
++		val = WPA_AUTH_DISABLED;
++
++	WL_DBG(("setting wpa_auth to 0x%0x\n", val));
++	err = wldev_iovar_setint_bsscfg(dev, "wpa_auth", val, bssidx);
++	if (unlikely(err)) {
++		WL_ERR(("set wpa_auth failed (%d)\n", err));
++		return err;
++	}
++	sec = wl_read_prof(cfg, dev, WL_PROF_SEC);
++	sec->wpa_versions = sme->crypto.wpa_versions;
++	return err;
++}
++
++
++static s32
++wl_set_auth_type(struct net_device *dev, struct cfg80211_connect_params *sme)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	struct wl_security *sec;
++	s32 val = 0;
++	s32 err = 0;
++	s32 bssidx;
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	switch (sme->auth_type) {
++	case NL80211_AUTHTYPE_OPEN_SYSTEM:
++		val = WL_AUTH_OPEN_SYSTEM;
++		WL_DBG(("open system\n"));
++		break;
++	case NL80211_AUTHTYPE_SHARED_KEY:
++		val = WL_AUTH_SHARED_KEY;
++		WL_DBG(("shared key\n"));
++		break;
++	case NL80211_AUTHTYPE_AUTOMATIC:
++		val = WL_AUTH_OPEN_SHARED;
++		WL_DBG(("automatic\n"));
++		break;
++	default:
++		val = 2;
++		WL_ERR(("invalid auth type (%d)\n", sme->auth_type));
++		break;
++	}
++
++	err = wldev_iovar_setint_bsscfg(dev, "auth", val, bssidx);
++	if (unlikely(err)) {
++		WL_ERR(("set auth failed (%d)\n", err));
++		return err;
++	}
++	sec = wl_read_prof(cfg, dev, WL_PROF_SEC);
++	sec->auth_type = sme->auth_type;
++	return err;
++}
++
++static s32
++wl_set_set_cipher(struct net_device *dev, struct cfg80211_connect_params *sme)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	struct wl_security *sec;
++	s32 pval = 0;
++	s32 gval = 0;
++	s32 err = 0;
++	s32 wsec_val = 0;
++
++	s32 bssidx;
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	if (sme->crypto.n_ciphers_pairwise) {
++		switch (sme->crypto.ciphers_pairwise[0]) {
++		case WLAN_CIPHER_SUITE_WEP40:
++		case WLAN_CIPHER_SUITE_WEP104:
++			pval = WEP_ENABLED;
++			break;
++		case WLAN_CIPHER_SUITE_TKIP:
++			pval = TKIP_ENABLED;
++			break;
++		case WLAN_CIPHER_SUITE_CCMP:
++		case WLAN_CIPHER_SUITE_AES_CMAC:
++			pval = AES_ENABLED;
++			break;
++		default:
++			WL_ERR(("invalid cipher pairwise (%d)\n",
++				sme->crypto.ciphers_pairwise[0]));
++			return -EINVAL;
++		}
++	}
++	if (sme->crypto.cipher_group) {
++		switch (sme->crypto.cipher_group) {
++		case WLAN_CIPHER_SUITE_WEP40:
++		case WLAN_CIPHER_SUITE_WEP104:
++			gval = WEP_ENABLED;
++			break;
++		case WLAN_CIPHER_SUITE_TKIP:
++			gval = TKIP_ENABLED;
++			break;
++		case WLAN_CIPHER_SUITE_CCMP:
++			gval = AES_ENABLED;
++			break;
++		case WLAN_CIPHER_SUITE_AES_CMAC:
++			gval = AES_ENABLED;
++			break;
++		default:
++			WL_ERR(("invalid cipher group (%d)\n",
++				sme->crypto.cipher_group));
++			return -EINVAL;
++		}
++	}
++
++	WL_DBG(("pval (%d) gval (%d)\n", pval, gval));
++
++	if (is_wps_conn(sme)) {
++		if (sme->privacy)
++			err = wldev_iovar_setint_bsscfg(dev, "wsec", 4, bssidx);
++		else
++			/* WPS-2.0 allows no security */
++			err = wldev_iovar_setint_bsscfg(dev, "wsec", 0, bssidx);
++	} else {
++			WL_DBG((" NO, is_wps_conn, Set pval | gval to WSEC"));
++			wsec_val = pval | gval;
++
++			WL_DBG((" Set WSEC to fW 0x%x \n", wsec_val));
++			err = wldev_iovar_setint_bsscfg(dev, "wsec",
++				wsec_val, bssidx);
++	}
++	if (unlikely(err)) {
++		WL_ERR(("error (%d)\n", err));
++		return err;
++	}
++
++	sec = wl_read_prof(cfg, dev, WL_PROF_SEC);
++	sec->cipher_pairwise = sme->crypto.ciphers_pairwise[0];
++	sec->cipher_group = sme->crypto.cipher_group;
++
++	return err;
++}
++
++static s32
++wl_set_key_mgmt(struct net_device *dev, struct cfg80211_connect_params *sme)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	struct wl_security *sec;
++	s32 val = 0;
++	s32 err = 0;
++	s32 bssidx;
++#ifdef MFP
++	s32 mfp = WL_MFP_NONE;
++	bcm_tlv_t *wpa2_ie;
++	u8 rsn_cap[2];
++#endif /* MFP */
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	if (sme->crypto.n_akm_suites) {
++		err = wldev_iovar_getint(dev, "wpa_auth", &val);
++		if (unlikely(err)) {
++			WL_ERR(("could not get wpa_auth (%d)\n", err));
++			return err;
++		}
++		if (val & (WPA_AUTH_PSK |
++			WPA_AUTH_UNSPECIFIED)) {
++			switch (sme->crypto.akm_suites[0]) {
++			case WLAN_AKM_SUITE_8021X:
++				val = WPA_AUTH_UNSPECIFIED;
++				break;
++			case WLAN_AKM_SUITE_PSK:
++				val = WPA_AUTH_PSK;
++				break;
++			default:
++				WL_ERR(("invalid cipher group (%d)\n",
++					sme->crypto.cipher_group));
++				return -EINVAL;
++			}
++		} else if (val & (WPA2_AUTH_PSK |
++			WPA2_AUTH_UNSPECIFIED)) {
++			switch (sme->crypto.akm_suites[0]) {
++			case WLAN_AKM_SUITE_8021X:
++				val = WPA2_AUTH_UNSPECIFIED;
++				break;
++#ifdef MFP
++			case WL_AKM_SUITE_SHA256_1X:
++				val = WPA2_AUTH_1X_SHA256;
++				break;
++			case WL_AKM_SUITE_SHA256_PSK:
++				val = WPA2_AUTH_PSK_SHA256;
++				break;
++#endif /* MFP */
++			case WLAN_AKM_SUITE_PSK:
++				val = WPA2_AUTH_PSK;
++				break;
++#if defined(WLFBT) && defined(WLAN_AKM_SUITE_FT_8021X)
++			case WLAN_AKM_SUITE_FT_8021X:
++				val = WPA2_AUTH_UNSPECIFIED | WPA2_AUTH_FT;
++				break;
++#endif
++#if defined(WLFBT) && defined(WLAN_AKM_SUITE_FT_PSK)
++			case WLAN_AKM_SUITE_FT_PSK:
++				val = WPA2_AUTH_PSK | WPA2_AUTH_FT;
++				break;
++#endif
++			default:
++				WL_ERR(("invalid cipher group (%d)\n",
++					sme->crypto.cipher_group));
++				return -EINVAL;
++			}
++		}
++
++#ifdef MFP
++		if (((wpa2_ie = bcm_parse_tlvs((u8 *)sme->ie, sme->ie_len,
++			DOT11_MNG_RSN_ID)) != NULL) &&
++			(wl_cfg80211_get_rsn_capa(wpa2_ie, rsn_cap) == 0)) {
++				/* Check for MFP cap in the RSN capability field */
++				if (rsn_cap[0] & RSN_CAP_MFPR) {
++					mfp = WL_MFP_REQUIRED;
++				} else if (rsn_cap[0] & RSN_CAP_MFPC) {
++					mfp = WL_MFP_CAPABLE;
++				}
++		}
++		err = wldev_iovar_setint(dev, "mfp", mfp);
++		if (unlikely(err)) {
++			if (!mfp && (err == BCME_UNSUPPORTED)) {
++				/* For non-mfp cases, if firmware doesn't support MFP
++				 * ignore the failure and proceed ahead.
++				 */
++				WL_DBG(("fw doesn't support mfp \n"));
++				err = 0;
++			} else {
++				WL_ERR(("mfp set failed ret:%d \n", err));
++				return err;
++			}
++		} else {
++			WL_DBG(("mfp set to 0x%x \n", mfp));
++		}
++#endif /* MFP */
++
++		WL_DBG(("setting wpa_auth to 0x%x\n", val));
++
++		err = wldev_iovar_setint_bsscfg(dev, "wpa_auth", val, bssidx);
++		if (unlikely(err)) {
++			WL_ERR(("could not set wpa_auth (%d)\n", err));
++			return err;
++		}
++	}
++	sec = wl_read_prof(cfg, dev, WL_PROF_SEC);
++	sec->wpa_auth = sme->crypto.akm_suites[0];
++
++	return err;
++}
++
++static s32
++wl_set_set_sharedkey(struct net_device *dev,
++	struct cfg80211_connect_params *sme)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	struct wl_security *sec;
++	struct wl_wsec_key key;
++	s32 val;
++	s32 err = 0;
++	s32 bssidx;
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	WL_DBG(("key len (%d)\n", sme->key_len));
++	if (sme->key_len) {
++		sec = wl_read_prof(cfg, dev, WL_PROF_SEC);
++		WL_DBG(("wpa_versions 0x%x cipher_pairwise 0x%x\n",
++			sec->wpa_versions, sec->cipher_pairwise));
++		if (!(sec->wpa_versions & (NL80211_WPA_VERSION_1 |
++			NL80211_WPA_VERSION_2)) &&
++			(sec->cipher_pairwise & (WLAN_CIPHER_SUITE_WEP40 |
++			WLAN_CIPHER_SUITE_WEP104)))
++		{
++			memset(&key, 0, sizeof(key));
++			key.len = (u32) sme->key_len;
++			key.index = (u32) sme->key_idx;
++			if (unlikely(key.len > sizeof(key.data))) {
++				WL_ERR(("Too long key length (%u)\n", key.len));
++				return -EINVAL;
++			}
++			memcpy(key.data, sme->key, key.len);
++			key.flags = WL_PRIMARY_KEY;
++			switch (sec->cipher_pairwise) {
++			case WLAN_CIPHER_SUITE_WEP40:
++				key.algo = CRYPTO_ALGO_WEP1;
++				break;
++			case WLAN_CIPHER_SUITE_WEP104:
++				key.algo = CRYPTO_ALGO_WEP128;
++				break;
++			default:
++				WL_ERR(("Invalid algorithm (%d)\n",
++					sme->crypto.ciphers_pairwise[0]));
++				return -EINVAL;
++			}
++			/* Set the new key/index */
++			WL_DBG(("key length (%d) key index (%d) algo (%d)\n",
++				key.len, key.index, key.algo));
++			WL_DBG(("key \"%s\"\n", key.data));
++			swap_key_from_BE(&key);
++			err = wldev_iovar_setbuf_bsscfg(dev, "wsec_key", &key, sizeof(key),
++				cfg->ioctl_buf, WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++			if (unlikely(err)) {
++				WL_ERR(("WLC_SET_KEY error (%d)\n", err));
++				return err;
++			}
++			if (sec->auth_type == NL80211_AUTHTYPE_SHARED_KEY) {
++				WL_DBG(("set auth_type to shared key\n"));
++				val = WL_AUTH_SHARED_KEY;	/* shared key */
++				err = wldev_iovar_setint_bsscfg(dev, "auth", val, bssidx);
++				if (unlikely(err)) {
++					WL_ERR(("set auth failed (%d)\n", err));
++					return err;
++				}
++			}
++		}
++	}
++	return err;
++}
++
++#if defined(ESCAN_RESULT_PATCH)
++static u8 connect_req_bssid[6];
++static u8 broad_bssid[6];
++#endif /* ESCAN_RESULT_PATCH */
++
++
++
++#if defined(CUSTOM_SET_CPUCORE) || defined(CONFIG_TCPACK_FASTTX)
++static bool wl_get_chan_isvht80(struct net_device *net, dhd_pub_t *dhd)
++{
++	u32 chanspec = 0;
++	bool isvht80 = 0;
++
++	if (wldev_iovar_getint(net, "chanspec", (s32 *)&chanspec) == BCME_OK)
++		chanspec = wl_chspec_driver_to_host(chanspec);
++
++	isvht80 = chanspec & WL_CHANSPEC_BW_80;
++	WL_INFO(("%s: chanspec(%x:%d)\n", __FUNCTION__, chanspec, isvht80));
++
++	return isvht80;
++}
++#endif /* CUSTOM_SET_CPUCORE || CONFIG_TCPACK_FASTTX */
++
++static s32
++wl_cfg80211_connect(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_connect_params *sme)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct ieee80211_channel *chan = sme->channel;
++	wl_extjoin_params_t *ext_join_params;
++	struct wl_join_params join_params;
++	size_t join_params_size;
++	s32 err = 0;
++	wpa_ie_fixed_t *wpa_ie;
++	bcm_tlv_t *wpa2_ie;
++	u8* wpaie  = 0;
++	u32 wpaie_len = 0;
++	u32 chan_cnt = 0;
++	struct ether_addr bssid;
++	s32 bssidx = -1;
++	int ret;
++	int wait_cnt;
++
++	WL_DBG(("In\n"));
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))
++	if (sme->channel_hint) {
++		chan = sme->channel_hint;
++		WL_DBG(("channel_hint (%d), channel_hint center_freq (%d)\n",
++			ieee80211_frequency_to_channel(sme->channel_hint->center_freq),
++			sme->channel_hint->center_freq));
++	}
++	if (sme->bssid_hint) {
++		sme->bssid = sme->bssid_hint;
++		WL_DBG(("bssid_hint "MACDBG" \n", MAC2STRDBG(sme->bssid_hint)));
++	}
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0) */
++
++	if (unlikely(!sme->ssid)) {
++		WL_ERR(("Invalid ssid\n"));
++		return -EOPNOTSUPP;
++	}
++
++	if (unlikely(sme->ssid_len > DOT11_MAX_SSID_LEN)) {
++		WL_ERR(("Invalid SSID info: SSID=%s, length=%zd\n",
++			sme->ssid, sme->ssid_len));
++		return -EINVAL;
++	}
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++
++	/*
++	 * Cancel ongoing scan to sync up with sme state machine of cfg80211.
++	 */
++#if !defined(ESCAN_RESULT_PATCH)
++	if (cfg->scan_request) {
++		wl_notify_escan_complete(cfg, dev, true, true);
++	}
++#endif
++#ifdef WL_SCHED_SCAN
++	if (cfg->sched_scan_req) {
++		wl_cfg80211_sched_scan_stop(wiphy, bcmcfg_to_prmry_ndev(cfg));
++	}
++#endif
++#if defined(ESCAN_RESULT_PATCH)
++	if (sme->bssid)
++		memcpy(connect_req_bssid, sme->bssid, ETHER_ADDR_LEN);
++	else
++		bzero(connect_req_bssid, ETHER_ADDR_LEN);
++	bzero(broad_bssid, ETHER_ADDR_LEN);
++#endif
++#if defined(USE_DYNAMIC_MAXPKT_RXGLOM)
++	maxrxpktglom = 0;
++#endif
++	bzero(&bssid, sizeof(bssid));
++	if (!wl_get_drv_status(cfg, CONNECTED, dev)&&
++		(ret = wldev_ioctl(dev, WLC_GET_BSSID, &bssid, ETHER_ADDR_LEN, false)) == 0) {
++		if (!ETHER_ISNULLADDR(&bssid)) {
++			scb_val_t scbval;
++			wl_set_drv_status(cfg, DISCONNECTING, dev);
++			scbval.val = DOT11_RC_DISASSOC_LEAVING;
++			memcpy(&scbval.ea, &bssid, ETHER_ADDR_LEN);
++			scbval.val = htod32(scbval.val);
++
++			WL_DBG(("drv status CONNECTED is not set, but connected in FW!" MACDBG "/n",
++				MAC2STRDBG(bssid.octet)));
++			err = wldev_ioctl(dev, WLC_DISASSOC, &scbval,
++				sizeof(scb_val_t), true);
++			if (unlikely(err)) {
++				wl_clr_drv_status(cfg, DISCONNECTING, dev);
++				WL_ERR(("error (%d)\n", err));
++				return err;
++			}
++			wait_cnt = 500/10;
++			while (wl_get_drv_status(cfg, DISCONNECTING, dev) && wait_cnt) {
++				WL_DBG(("Waiting for disconnection terminated, wait_cnt: %d\n",
++					wait_cnt));
++				wait_cnt--;
++				OSL_SLEEP(10);
++			}
++		} else
++			WL_DBG(("Currently not associated!\n"));
++	} else {
++		/* if status is DISCONNECTING, wait for disconnection terminated max 500 ms */
++		wait_cnt = 500/10;
++		while (wl_get_drv_status(cfg, DISCONNECTING, dev) && wait_cnt) {
++			WL_DBG(("Waiting for disconnection terminated, wait_cnt: %d\n", wait_cnt));
++			wait_cnt--;
++			OSL_SLEEP(10);
++		}
++	}
++
++	/* Clean BSSID */
++	bzero(&bssid, sizeof(bssid));
++	if (!wl_get_drv_status(cfg, DISCONNECTING, dev))
++		wl_update_prof(cfg, dev, NULL, (void *)&bssid, WL_PROF_BSSID);
++
++	if (p2p_is_on(cfg) && (dev != bcmcfg_to_prmry_ndev(cfg))) {
++		/* we only allow to connect using virtual interface in case of P2P */
++			if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++				WL_ERR(("Find p2p index from wdev(%p) failed\n",
++					dev->ieee80211_ptr));
++				return BCME_ERROR;
++			}
++			wl_cfg80211_set_mgmt_vndr_ies(cfg, ndev_to_cfgdev(dev), bssidx,
++				VNDR_IE_ASSOCREQ_FLAG, sme->ie, sme->ie_len);
++	} else if (dev == bcmcfg_to_prmry_ndev(cfg)) {
++		/* find the RSN_IE */
++		if ((wpa2_ie = bcm_parse_tlvs((u8 *)sme->ie, sme->ie_len,
++			DOT11_MNG_RSN_ID)) != NULL) {
++			WL_DBG((" WPA2 IE is found\n"));
++		}
++		/* find the WPA_IE */
++		if ((wpa_ie = wl_cfgp2p_find_wpaie((u8 *)sme->ie,
++			sme->ie_len)) != NULL) {
++			WL_DBG((" WPA IE is found\n"));
++		}
++		if (wpa_ie != NULL || wpa2_ie != NULL) {
++			wpaie = (wpa_ie != NULL) ? (u8 *)wpa_ie : (u8 *)wpa2_ie;
++			wpaie_len = (wpa_ie != NULL) ? wpa_ie->length : wpa2_ie->len;
++			wpaie_len += WPA_RSN_IE_TAG_FIXED_LEN;
++			err = wldev_iovar_setbuf(dev, "wpaie", wpaie, wpaie_len,
++				cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++			if (unlikely(err)) {
++				WL_ERR(("wpaie set error (%d)\n", err));
++				return err;
++			}
++		} else {
++			err = wldev_iovar_setbuf(dev, "wpaie", NULL, 0,
++				cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++			if (unlikely(err)) {
++				WL_ERR(("wpaie set error (%d)\n", err));
++				return err;
++			}
++		}
++
++		if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++			WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++			return BCME_ERROR;
++		}
++		err = wl_cfg80211_set_mgmt_vndr_ies(cfg, ndev_to_cfgdev(dev), bssidx,
++			VNDR_IE_ASSOCREQ_FLAG, (const u8 *)sme->ie, sme->ie_len);
++		if (unlikely(err)) {
++			return err;
++		}
++	}
++	if (chan) {
++		/* If RCC is not enabled, use the channel provided by userspace */
++		cfg->channel = ieee80211_frequency_to_channel(chan->center_freq);
++		chan_cnt = 1;
++		WL_DBG(("channel (%d), center_req (%d), %d channels\n", cfg->channel,
++			chan->center_freq, chan_cnt));
++	} else {
++		/*
++		 * No channel information from user space. if RCC is enabled, the RCC
++		 * would prepare the channel list, else no channel would be provided
++		 * and firmware would need to do a full channel scan.
++		 */
++		WL_DBG(("No channel info from user space\n"));
++		cfg->channel = 0;
++	}
++	WL_DBG(("3. set wapi version \n"));
++	err = wl_set_wpa_version(dev, sme);
++	if (unlikely(err)) {
++		WL_ERR(("Invalid wpa_version\n"));
++		return err;
++	}
++		err = wl_set_auth_type(dev, sme);
++		if (unlikely(err)) {
++			WL_ERR(("Invalid auth type\n"));
++			return err;
++		}
++
++	err = wl_set_set_cipher(dev, sme);
++	if (unlikely(err)) {
++		WL_ERR(("Invalid ciper\n"));
++		return err;
++	}
++
++	err = wl_set_key_mgmt(dev, sme);
++	if (unlikely(err)) {
++		WL_ERR(("Invalid key mgmt\n"));
++		return err;
++	}
++
++	err = wl_set_set_sharedkey(dev, sme);
++	if (unlikely(err)) {
++		WL_ERR(("Invalid shared key\n"));
++		return err;
++	}
++
++	/*
++	 *  Join with specific BSSID and cached SSID
++	 *  If SSID is zero join based on BSSID only
++	 */
++	join_params_size = WL_EXTJOIN_PARAMS_FIXED_SIZE +
++		chan_cnt * sizeof(chanspec_t);
++	ext_join_params =  (wl_extjoin_params_t*)kzalloc(join_params_size, GFP_KERNEL);
++	if (ext_join_params == NULL) {
++		err = -ENOMEM;
++		wl_clr_drv_status(cfg, CONNECTING, dev);
++		goto exit;
++	}
++	ext_join_params->ssid.SSID_len = min(sizeof(ext_join_params->ssid.SSID), sme->ssid_len);
++	memcpy(&ext_join_params->ssid.SSID, sme->ssid, ext_join_params->ssid.SSID_len);
++	wl_update_prof(cfg, dev, NULL, &ext_join_params->ssid, WL_PROF_SSID);
++	ext_join_params->ssid.SSID_len = htod32(ext_join_params->ssid.SSID_len);
++	/* increate dwell time to receive probe response or detect Beacon
++	* from target AP at a noisy air only during connect command
++	*/
++	ext_join_params->scan.active_time = chan_cnt ? WL_SCAN_JOIN_ACTIVE_DWELL_TIME_MS : -1;
++	ext_join_params->scan.passive_time = chan_cnt ? WL_SCAN_JOIN_PASSIVE_DWELL_TIME_MS : -1;
++	/* Set up join scan parameters */
++	ext_join_params->scan.scan_type = -1;
++	ext_join_params->scan.nprobes = chan_cnt ?
++		(ext_join_params->scan.active_time/WL_SCAN_JOIN_PROBE_INTERVAL_MS) : -1;
++	ext_join_params->scan.home_time = -1;
++
++	if (sme->bssid)
++		memcpy(&ext_join_params->assoc.bssid, sme->bssid, ETH_ALEN);
++	else
++		memcpy(&ext_join_params->assoc.bssid, &ether_bcast, ETH_ALEN);
++	ext_join_params->assoc.chanspec_num = chan_cnt;
++	if (chan_cnt) {
++		if (cfg->channel) {
++			/*
++			 * Use the channel provided by userspace
++			 */
++			u16 channel, band, bw, ctl_sb;
++			chanspec_t chspec;
++			channel = cfg->channel;
++			band = (channel <= CH_MAX_2G_CHANNEL) ? WL_CHANSPEC_BAND_2G
++				: WL_CHANSPEC_BAND_5G;
++
++			/* Get min_bw set for the interface */
++			bw = wl_cfg80211_ulb_get_min_bw_chspec(dev->ieee80211_ptr, bssidx);
++			if (bw == INVCHANSPEC) {
++				WL_ERR(("Invalid chanspec \n"));
++				kfree(ext_join_params);
++				return BCME_ERROR;
++			}
++
++			ctl_sb = WL_CHANSPEC_CTL_SB_NONE;
++			chspec = (channel | band | bw | ctl_sb);
++			ext_join_params->assoc.chanspec_list[0]  &= WL_CHANSPEC_CHAN_MASK;
++			ext_join_params->assoc.chanspec_list[0] |= chspec;
++			ext_join_params->assoc.chanspec_list[0] =
++				wl_chspec_host_to_driver(ext_join_params->assoc.chanspec_list[0]);
++		}
++	}
++	ext_join_params->assoc.chanspec_num = htod32(ext_join_params->assoc.chanspec_num);
++	if (ext_join_params->ssid.SSID_len < IEEE80211_MAX_SSID_LEN) {
++		WL_INFORM(("ssid \"%s\", len (%d)\n", ext_join_params->ssid.SSID,
++			ext_join_params->ssid.SSID_len));
++	}
++	wl_set_drv_status(cfg, CONNECTING, dev);
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		kfree(ext_join_params);
++		return BCME_ERROR;
++	}
++	err = wldev_iovar_setbuf_bsscfg(dev, "join", ext_join_params, join_params_size,
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++
++	if (cfg->rcc_enabled) {
++		WL_ERR(("Connecting with" MACDBG " ssid \"%s\", len (%d) with rcc channels \n\n",
++			MAC2STRDBG((u8*)(&ext_join_params->assoc.bssid)),
++			ext_join_params->ssid.SSID, ext_join_params->ssid.SSID_len));
++	} else {
++		WL_ERR(("Connecting with" MACDBG " ssid \"%s\", len (%d) channel=%d\n\n",
++			MAC2STRDBG((u8*)(&ext_join_params->assoc.bssid)),
++			ext_join_params->ssid.SSID, ext_join_params->ssid.SSID_len, cfg->channel));
++	}
++
++	kfree(ext_join_params);
++	if (err) {
++		wl_clr_drv_status(cfg, CONNECTING, dev);
++		if (err == BCME_UNSUPPORTED) {
++			WL_DBG(("join iovar is not supported\n"));
++			goto set_ssid;
++		} else {
++			WL_ERR(("error (%d)\n", err));
++			goto exit;
++		}
++	} else
++		goto exit;
++
++set_ssid:
++	memset(&join_params, 0, sizeof(join_params));
++	join_params_size = sizeof(join_params.ssid);
++
++	join_params.ssid.SSID_len = min(sizeof(join_params.ssid.SSID), sme->ssid_len);
++	memcpy(&join_params.ssid.SSID, sme->ssid, join_params.ssid.SSID_len);
++	join_params.ssid.SSID_len = htod32(join_params.ssid.SSID_len);
++	wl_update_prof(cfg, dev, NULL, &join_params.ssid, WL_PROF_SSID);
++	if (sme->bssid)
++		memcpy(&join_params.params.bssid, sme->bssid, ETH_ALEN);
++	else
++		memcpy(&join_params.params.bssid, &ether_bcast, ETH_ALEN);
++
++	if (wl_ch_to_chanspec(dev, cfg->channel, &join_params, &join_params_size) < 0) {
++		WL_ERR(("Invalid chanspec\n"));
++		return -EINVAL;
++	}
++
++	WL_DBG(("join_param_size %zu\n", join_params_size));
++
++	if (join_params.ssid.SSID_len < IEEE80211_MAX_SSID_LEN) {
++		WL_INFORM(("ssid \"%s\", len (%d)\n", join_params.ssid.SSID,
++			join_params.ssid.SSID_len));
++	}
++	wl_set_drv_status(cfg, CONNECTING, dev);
++	err = wldev_ioctl(dev, WLC_SET_SSID, &join_params, join_params_size, true);
++	if (err) {
++		WL_ERR(("error (%d)\n", err));
++		wl_clr_drv_status(cfg, CONNECTING, dev);
++	}
++exit:
++	return err;
++}
++
++static s32
++wl_cfg80211_disconnect(struct wiphy *wiphy, struct net_device *dev,
++	u16 reason_code)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	scb_val_t scbval;
++	bool act = false;
++	s32 err = 0;
++	u8 *curbssid;
++#ifdef CUSTOM_SET_CPUCORE
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++#endif /* CUSTOM_SET_CPUCORE */
++	WL_ERR(("Reason %d\n", reason_code));
++	RETURN_EIO_IF_NOT_UP(cfg);
++	act = *(bool *) wl_read_prof(cfg, dev, WL_PROF_ACT);
++	curbssid = wl_read_prof(cfg, dev, WL_PROF_BSSID);
++#ifdef ESCAN_RESULT_PATCH
++	if (wl_get_drv_status(cfg, CONNECTING, dev) && curbssid &&
++		(memcmp(curbssid, connect_req_bssid, ETHER_ADDR_LEN) == 0)) {
++		WL_ERR(("Disconnecting from connecting device: " MACDBG "\n",
++			MAC2STRDBG(curbssid)));
++		act = true;
++	}
++#endif /* ESCAN_RESULT_PATCH */
++	if (act) {
++		/*
++		* Cancel ongoing scan to sync up with sme state machine of cfg80211.
++		*/
++#if !defined(ESCAN_RESULT_PATCH)
++		/* Let scan aborted by F/W */
++		if (cfg->scan_request) {
++			wl_notify_escan_complete(cfg, dev, true, true);
++		}
++#endif /* ESCAN_RESULT_PATCH */
++		wl_set_drv_status(cfg, DISCONNECTING, dev);
++		scbval.val = reason_code;
++		memcpy(&scbval.ea, curbssid, ETHER_ADDR_LEN);
++		scbval.val = htod32(scbval.val);
++		err = wldev_ioctl(dev, WLC_DISASSOC, &scbval,
++			sizeof(scb_val_t), true);
++		if (unlikely(err)) {
++			wl_clr_drv_status(cfg, DISCONNECTING, dev);
++			WL_ERR(("error (%d)\n", err));
++			return err;
++		}
++	}
++#ifdef CUSTOM_SET_CPUCORE
++	/* set default cpucore */
++	if (dev == bcmcfg_to_prmry_ndev(cfg)) {
++		dhd->chan_isvht80 &= ~DHD_FLAG_STA_MODE;
++		if (!(dhd->chan_isvht80))
++			dhd_set_cpucore(dhd, FALSE);
++	}
++#endif /* CUSTOM_SET_CPUCORE */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
++	/* cfg80211 expects disconnect event from DHD to release wdev->current_bss */
++	CFG80211_DISCONNECTED(dev, reason_code, NULL, 0, false, GFP_KERNEL);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) */
++
++	return err;
++}
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++static s32
++wl_cfg80211_set_tx_power(struct wiphy *wiphy, struct wireless_dev *wdev,
++	enum nl80211_tx_power_setting type, s32 mbm)
++#else
++static s32
++wl_cfg80211_set_tx_power(struct wiphy *wiphy,
++	enum nl80211_tx_power_setting type, s32 dbm)
++#endif /* WL_CFG80211_P2P_DEV_IF */
++{
++
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	s32 err = 0;
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	s32 dbm = MBM_TO_DBM(mbm);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) || \
++	defined(WL_COMPAT_WIRELESS) || defined(WL_SUPPORT_BACKPORTED_KPATCHES)
++	dbm = MBM_TO_DBM(dbm);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	switch (type) {
++	case NL80211_TX_POWER_AUTOMATIC:
++		break;
++	case NL80211_TX_POWER_LIMITED:
++		if (dbm < 0) {
++			WL_ERR(("TX_POWER_LIMITTED - dbm is negative\n"));
++			return -EINVAL;
++		}
++		break;
++	case NL80211_TX_POWER_FIXED:
++		if (dbm < 0) {
++			WL_ERR(("TX_POWER_FIXED - dbm is negative..\n"));
++			return -EINVAL;
++		}
++		break;
++	}
++
++	err = wl_set_tx_power(ndev, type, dbm);
++	if (unlikely(err)) {
++		WL_ERR(("error (%d)\n", err));
++		return err;
++	}
++
++	cfg->conf->tx_power = dbm;
++
++	return err;
++}
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++static s32 wl_cfg80211_get_tx_power(struct wiphy *wiphy,
++	struct wireless_dev *wdev, s32 *dbm)
++#else
++static s32 wl_cfg80211_get_tx_power(struct wiphy *wiphy, s32 *dbm)
++#endif /* WL_CFG80211_P2P_DEV_IF */
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	s32 err = 0;
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	err = wl_get_tx_power(ndev, dbm);
++	if (unlikely(err))
++		WL_ERR(("error (%d)\n", err));
++
++	return err;
++}
++
++static s32
++wl_cfg80211_config_default_key(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, bool unicast, bool multicast)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	u32 index;
++	s32 wsec;
++	s32 err = 0;
++	s32 bssidx;
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from dev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	WL_DBG(("key index (%d)\n", key_idx));
++	RETURN_EIO_IF_NOT_UP(cfg);
++	err = wldev_iovar_getint_bsscfg(dev, "wsec", &wsec, bssidx);
++	if (unlikely(err)) {
++		WL_ERR(("WLC_GET_WSEC error (%d)\n", err));
++		return err;
++	}
++	if (wsec == WEP_ENABLED) {
++		/* Just select a new current key */
++		index = (u32) key_idx;
++		index = htod32(index);
++		err = wldev_ioctl(dev, WLC_SET_KEY_PRIMARY, &index,
++			sizeof(index), true);
++		if (unlikely(err)) {
++			WL_ERR(("error (%d)\n", err));
++		}
++	}
++	return err;
++}
++
++static s32
++wl_add_keyext(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, const u8 *mac_addr, struct key_params *params)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct wl_wsec_key key;
++	s32 err = 0;
++	s32 bssidx;
++	s32 mode = wl_get_mode_by_netdev(cfg, dev);
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++	memset(&key, 0, sizeof(key));
++	key.index = (u32) key_idx;
++
++	if (!ETHER_ISMULTI(mac_addr))
++		memcpy((char *)&key.ea, (const void *)mac_addr, ETHER_ADDR_LEN);
++	key.len = (u32) params->key_len;
++
++	/* check for key index change */
++	if (key.len == 0) {
++		/* key delete */
++		swap_key_from_BE(&key);
++		err = wldev_iovar_setbuf_bsscfg(dev, "wsec_key", &key, sizeof(key),
++			cfg->ioctl_buf, WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++		if (unlikely(err)) {
++			WL_ERR(("key delete error (%d)\n", err));
++			return err;
++		}
++	} else {
++		if (key.len > sizeof(key.data)) {
++			WL_ERR(("Invalid key length (%d)\n", key.len));
++			return -EINVAL;
++		}
++		WL_DBG(("Setting the key index %d\n", key.index));
++		memcpy(key.data, params->key, key.len);
++
++		if ((mode == WL_MODE_BSS) &&
++			(params->cipher == WLAN_CIPHER_SUITE_TKIP)) {
++			u8 keybuf[8];
++			memcpy(keybuf, &key.data[24], sizeof(keybuf));
++			memcpy(&key.data[24], &key.data[16], sizeof(keybuf));
++			memcpy(&key.data[16], keybuf, sizeof(keybuf));
++		}
++
++		/* if IW_ENCODE_EXT_RX_SEQ_VALID set */
++		if (params->seq && params->seq_len == 6) {
++			/* rx iv */
++			u8 *ivptr;
++			ivptr = (u8 *) params->seq;
++			key.rxiv.hi = (ivptr[5] << 24) | (ivptr[4] << 16) |
++				(ivptr[3] << 8) | ivptr[2];
++			key.rxiv.lo = (ivptr[1] << 8) | ivptr[0];
++			key.iv_initialized = true;
++		}
++
++		switch (params->cipher) {
++		case WLAN_CIPHER_SUITE_WEP40:
++			key.algo = CRYPTO_ALGO_WEP1;
++			WL_DBG(("WLAN_CIPHER_SUITE_WEP40\n"));
++			break;
++		case WLAN_CIPHER_SUITE_WEP104:
++			key.algo = CRYPTO_ALGO_WEP128;
++			WL_DBG(("WLAN_CIPHER_SUITE_WEP104\n"));
++			break;
++		case WLAN_CIPHER_SUITE_TKIP:
++			key.algo = CRYPTO_ALGO_TKIP;
++			WL_DBG(("WLAN_CIPHER_SUITE_TKIP\n"));
++			break;
++		case WLAN_CIPHER_SUITE_AES_CMAC:
++			key.algo = CRYPTO_ALGO_AES_CCM;
++			WL_DBG(("WLAN_CIPHER_SUITE_AES_CMAC\n"));
++			break;
++		case WLAN_CIPHER_SUITE_CCMP:
++			key.algo = CRYPTO_ALGO_AES_CCM;
++			WL_DBG(("WLAN_CIPHER_SUITE_CCMP\n"));
++			break;
++		default:
++			WL_ERR(("Invalid cipher (0x%x)\n", params->cipher));
++			return -EINVAL;
++		}
++		swap_key_from_BE(&key);
++		/* need to guarantee EAPOL 4/4 send out before set key */
++		dhd_wait_pend8021x(dev);
++		err = wldev_iovar_setbuf_bsscfg(dev, "wsec_key", &key, sizeof(key),
++			cfg->ioctl_buf, WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++		if (unlikely(err)) {
++			WL_ERR(("WLC_SET_KEY error (%d)\n", err));
++			return err;
++		}
++	}
++	return err;
++}
++
++int
++wl_cfg80211_enable_roam_offload(struct net_device *dev, int enable)
++{
++	int err;
++	wl_eventmsg_buf_t ev_buf;
++
++	if (dev != bcmcfg_to_prmry_ndev(g_bcm_cfg)) {
++		/* roam offload is only for the primary device */
++		return -1;
++	}
++	err = wldev_iovar_setint(dev, "roam_offload", enable);
++	if (err)
++		return err;
++
++	bzero(&ev_buf, sizeof(wl_eventmsg_buf_t));
++	wl_cfg80211_add_to_eventbuffer(&ev_buf, WLC_E_PSK_SUP, !enable);
++	wl_cfg80211_add_to_eventbuffer(&ev_buf, WLC_E_ASSOC_REQ_IE, !enable);
++	wl_cfg80211_add_to_eventbuffer(&ev_buf, WLC_E_ASSOC_RESP_IE, !enable);
++	wl_cfg80211_add_to_eventbuffer(&ev_buf, WLC_E_REASSOC, !enable);
++	wl_cfg80211_add_to_eventbuffer(&ev_buf, WLC_E_JOIN, !enable);
++	wl_cfg80211_add_to_eventbuffer(&ev_buf, WLC_E_ROAM, !enable);
++	err = wl_cfg80211_apply_eventbuffer(dev, g_bcm_cfg, &ev_buf);
++	if (!err) {
++		g_bcm_cfg->roam_offload = enable;
++	}
++	return err;
++}
++
++#if defined(WL_VIRTUAL_APSTA)
++int
++wl_cfg80211_interface_create(struct net_device *dev, char *name)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	bcm_struct_cfgdev *new_cfgdev;
++
++	new_cfgdev = wl_cfg80211_create_iface(cfg->wdev->wiphy,
++			NL80211_IFTYPE_STATION, NULL, name);
++	if (!new_cfgdev) {
++		return BCME_ERROR;
++	}
++	else {
++		WL_DBG(("Iface %s created successfuly\n", name));
++		return BCME_OK;
++	}
++}
++
++int
++wl_cfg80211_interface_delete(struct net_device *dev, char *name)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	struct net_info *iter, *next;
++	int err = BCME_ERROR;
++
++	if (name == NULL) {
++		return BCME_ERROR;
++	}
++
++	for_each_ndev(cfg, iter, next) {
++		if (iter->ndev) {
++			if (strcmp(iter->ndev->name, name) == 0) {
++				err =  wl_cfg80211_del_iface(cfg->wdev->wiphy, cfg->bss_cfgdev);
++				break;
++			}
++		}
++	}
++	if (!err) {
++		WL_DBG(("Iface %s deleted successfuly", name));
++	}
++	return err;
++}
++#endif /* defined (WL_VIRTUAL_APSTA) */
++
++static s32
++wl_cfg80211_add_key(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, bool pairwise, const u8 *mac_addr,
++	struct key_params *params)
++{
++	struct wl_wsec_key key;
++	s32 val = 0;
++	s32 wsec = 0;
++	s32 err = 0;
++	u8 keybuf[8];
++	s32 bssidx = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 mode = wl_get_mode_by_netdev(cfg, dev);
++	WL_DBG(("key index (%d)\n", key_idx));
++	RETURN_EIO_IF_NOT_UP(cfg);
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from dev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	if (mac_addr &&
++		((params->cipher != WLAN_CIPHER_SUITE_WEP40) &&
++		(params->cipher != WLAN_CIPHER_SUITE_WEP104))) {
++			wl_add_keyext(wiphy, dev, key_idx, mac_addr, params);
++			goto exit;
++	}
++	memset(&key, 0, sizeof(key));
++	/* Clear any buffered wep key */
++	memset(&cfg->wep_key, 0, sizeof(struct wl_wsec_key));
++
++	key.len = (u32) params->key_len;
++	key.index = (u32) key_idx;
++
++	if (unlikely(key.len > sizeof(key.data))) {
++		WL_ERR(("Too long key length (%u)\n", key.len));
++		return -EINVAL;
++	}
++	memcpy(key.data, params->key, key.len);
++
++	key.flags = WL_PRIMARY_KEY;
++	switch (params->cipher) {
++	case WLAN_CIPHER_SUITE_WEP40:
++		key.algo = CRYPTO_ALGO_WEP1;
++		val = WEP_ENABLED;
++		WL_DBG(("WLAN_CIPHER_SUITE_WEP40\n"));
++		break;
++	case WLAN_CIPHER_SUITE_WEP104:
++		key.algo = CRYPTO_ALGO_WEP128;
++		val = WEP_ENABLED;
++		WL_DBG(("WLAN_CIPHER_SUITE_WEP104\n"));
++		break;
++	case WLAN_CIPHER_SUITE_TKIP:
++		key.algo = CRYPTO_ALGO_TKIP;
++		val = TKIP_ENABLED;
++		/* wpa_supplicant switches the third and fourth quarters of the TKIP key */
++		if (mode == WL_MODE_BSS) {
++			bcopy(&key.data[24], keybuf, sizeof(keybuf));
++			bcopy(&key.data[16], &key.data[24], sizeof(keybuf));
++			bcopy(keybuf, &key.data[16], sizeof(keybuf));
++		}
++		WL_DBG(("WLAN_CIPHER_SUITE_TKIP\n"));
++		break;
++	case WLAN_CIPHER_SUITE_AES_CMAC:
++		key.algo = CRYPTO_ALGO_AES_CCM;
++		val = AES_ENABLED;
++		WL_DBG(("WLAN_CIPHER_SUITE_AES_CMAC\n"));
++		break;
++	case WLAN_CIPHER_SUITE_CCMP:
++		key.algo = CRYPTO_ALGO_AES_CCM;
++		val = AES_ENABLED;
++		WL_DBG(("WLAN_CIPHER_SUITE_CCMP\n"));
++		break;
++#if defined(WLFBT) && defined(WLAN_CIPHER_SUITE_PMK)
++	case WLAN_CIPHER_SUITE_PMK: {
++		int j;
++		wsec_pmk_t pmk;
++		char keystring[WSEC_MAX_PSK_LEN + 1];
++		char* charptr = keystring;
++		uint len;
++		struct wl_security *sec;
++
++		sec = wl_read_prof(cfg, dev, WL_PROF_SEC);
++		if (sec->wpa_auth == WLAN_AKM_SUITE_8021X) {
++			err = wldev_iovar_setbuf(dev, "okc_info_pmk", (void *)params->key,
++				WSEC_MAX_PSK_LEN / 2, keystring, sizeof(keystring), NULL);
++			if (err) {
++				/* could fail in case that 'okc' is not supported */
++				WL_INFORM(("Setting 'okc_info_pmk' failed, err=%d\n", err));
++			}
++		}
++		/* copy the raw hex key to the appropriate format */
++		for (j = 0; j < (WSEC_MAX_PSK_LEN / 2); j++) {
++			charptr += snprintf(charptr, sizeof(keystring), "%02x", params->key[j]);
++		}
++		len = strlen(keystring);
++		pmk.key_len = htod16(len);
++		bcopy(keystring, pmk.key, len);
++		pmk.flags = htod16(WSEC_PASSPHRASE);
++		err = wldev_ioctl(dev, WLC_SET_WSEC_PMK, &pmk, sizeof(pmk), true);
++		if (err)
++			return err;
++	} break;
++#endif /* WLFBT && WLAN_CIPHER_SUITE_PMK */
++	default:
++		WL_ERR(("Invalid cipher (0x%x)\n", params->cipher));
++		return -EINVAL;
++	}
++
++	/* Set the new key/index */
++	if ((mode == WL_MODE_IBSS) && (val & (TKIP_ENABLED | AES_ENABLED))) {
++		WL_ERR(("IBSS KEY setted\n"));
++		wldev_iovar_setint(dev, "wpa_auth", WPA_AUTH_NONE);
++	}
++	swap_key_from_BE(&key);
++	if ((params->cipher == WLAN_CIPHER_SUITE_WEP40) ||
++		(params->cipher == WLAN_CIPHER_SUITE_WEP104)) {
++		/*
++		 * For AP role, since we are doing a wl down before bringing up AP,
++		 * the plumbed keys will be lost. So for AP once we bring up AP, we
++		 * need to plumb keys again. So buffer the keys for future use. This
++		 * is more like a WAR. If firmware later has the capability to do
++		 * interface upgrade without doing a "wl down" and "wl apsta 0", then
++		 * this will not be required.
++		 */
++		WL_DBG(("Buffering WEP Keys \n"));
++		memcpy(&cfg->wep_key, &key, sizeof(struct wl_wsec_key));
++	}
++	err = wldev_iovar_setbuf_bsscfg(dev, "wsec_key", &key, sizeof(key), cfg->ioctl_buf,
++		WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++	if (unlikely(err)) {
++		WL_ERR(("WLC_SET_KEY error (%d)\n", err));
++		return err;
++	}
++
++exit:
++	err = wldev_iovar_getint_bsscfg(dev, "wsec", &wsec, bssidx);
++	if (unlikely(err)) {
++		WL_ERR(("get wsec error (%d)\n", err));
++		return err;
++	}
++
++	wsec |= val;
++	err = wldev_iovar_setint_bsscfg(dev, "wsec", wsec, bssidx);
++	if (unlikely(err)) {
++		WL_ERR(("set wsec error (%d)\n", err));
++		return err;
++	}
++
++	return err;
++}
++
++static s32
++wl_cfg80211_del_key(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, bool pairwise, const u8 *mac_addr)
++{
++	struct wl_wsec_key key;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 err = 0;
++	s32 bssidx;
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++	WL_DBG(("Enter\n"));
++
++#ifndef MFP
++	if ((key_idx >= DOT11_MAX_DEFAULT_KEYS) && (key_idx < DOT11_MAX_DEFAULT_KEYS+2))
++		return -EINVAL;
++#endif
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	memset(&key, 0, sizeof(key));
++
++	key.flags = WL_PRIMARY_KEY;
++	key.algo = CRYPTO_ALGO_OFF;
++	key.index = (u32) key_idx;
++
++	WL_DBG(("key index (%d)\n", key_idx));
++	/* Set the new key/index */
++	swap_key_from_BE(&key);
++	err = wldev_iovar_setbuf_bsscfg(dev, "wsec_key", &key, sizeof(key), cfg->ioctl_buf,
++		WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++	if (unlikely(err)) {
++		if (err == -EINVAL) {
++			if (key.index >= DOT11_MAX_DEFAULT_KEYS) {
++				/* we ignore this key index in this case */
++				WL_DBG(("invalid key index (%d)\n", key_idx));
++			}
++		} else {
++			WL_ERR(("WLC_SET_KEY error (%d)\n", err));
++		}
++		return err;
++	}
++	return err;
++}
++
++static s32
++wl_cfg80211_get_key(struct wiphy *wiphy, struct net_device *dev,
++	u8 key_idx, bool pairwise, const u8 *mac_addr, void *cookie,
++	void (*callback) (void *cookie, struct key_params * params))
++{
++	struct key_params params;
++	struct wl_wsec_key key;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct wl_security *sec;
++	s32 wsec;
++	s32 err = 0;
++	s32 bssidx;
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++	WL_DBG(("key index (%d)\n", key_idx));
++	RETURN_EIO_IF_NOT_UP(cfg);
++	memset(&key, 0, sizeof(key));
++	key.index = key_idx;
++	swap_key_to_BE(&key);
++	memset(&params, 0, sizeof(params));
++	params.key_len = (u8) min_t(u8, DOT11_MAX_KEY_SIZE, key.len);
++	memcpy((void *)params.key, key.data, params.key_len);
++
++	err = wldev_iovar_getint_bsscfg(dev, "wsec", &wsec, bssidx);
++	if (unlikely(err)) {
++		WL_ERR(("WLC_GET_WSEC error (%d)\n", err));
++		return err;
++	}
++	switch (WSEC_ENABLED(wsec)) {
++		case WEP_ENABLED:
++			sec = wl_read_prof(cfg, dev, WL_PROF_SEC);
++			if (sec->cipher_pairwise & WLAN_CIPHER_SUITE_WEP40) {
++				params.cipher = WLAN_CIPHER_SUITE_WEP40;
++				WL_DBG(("WLAN_CIPHER_SUITE_WEP40\n"));
++			} else if (sec->cipher_pairwise & WLAN_CIPHER_SUITE_WEP104) {
++				params.cipher = WLAN_CIPHER_SUITE_WEP104;
++				WL_DBG(("WLAN_CIPHER_SUITE_WEP104\n"));
++			}
++			break;
++		case TKIP_ENABLED:
++			params.cipher = WLAN_CIPHER_SUITE_TKIP;
++			WL_DBG(("WLAN_CIPHER_SUITE_TKIP\n"));
++			break;
++		case AES_ENABLED:
++			params.cipher = WLAN_CIPHER_SUITE_AES_CMAC;
++			WL_DBG(("WLAN_CIPHER_SUITE_AES_CMAC\n"));
++			break;
++		default:
++			WL_ERR(("Invalid algo (0x%x)\n", wsec));
++			return -EINVAL;
++	}
++
++	callback(cookie, &params);
++	return err;
++}
++
++static s32
++wl_cfg80211_config_default_mgmt_key(struct wiphy *wiphy,
++	struct net_device *dev, u8 key_idx)
++{
++#ifdef MFP
++	return 0;
++#else
++	WL_INFORM(("Not supported\n"));
++	return -EOPNOTSUPP;
++#endif /* MFP */
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++static s32
++wl_cfg80211_get_station(struct wiphy *wiphy, struct net_device *dev,
++	const u8 *mac, struct station_info *sinfo)
++#else
++static s32
++wl_cfg80211_get_station(struct wiphy *wiphy, struct net_device *dev,
++	u8 *mac, struct station_info *sinfo)
++#endif
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	scb_val_t scb_val;
++	s32 rssi;
++	s32 rate;
++	s32 err = 0;
++	sta_info_t *sta;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	s8 eabuf[ETHER_ADDR_STR_LEN];
++#endif
++	dhd_pub_t *dhd =  (dhd_pub_t *)(cfg->pub);
++	RETURN_EIO_IF_NOT_UP(cfg);
++	if (wl_get_mode_by_netdev(cfg, dev) == WL_MODE_AP) {
++		err = wldev_iovar_getbuf(dev, "sta_info", (struct ether_addr *)mac,
++			ETHER_ADDR_LEN, cfg->ioctl_buf, WLC_IOCTL_SMLEN, &cfg->ioctl_buf_sync);
++		if (err < 0) {
++			WL_ERR(("GET STA INFO failed, %d\n", err));
++			return err;
++		}
++		sinfo->filled = STA_INFO_BIT(INFO_INACTIVE_TIME);
++		sta = (sta_info_t *)cfg->ioctl_buf;
++		sta->len = dtoh16(sta->len);
++		sta->cap = dtoh16(sta->cap);
++		sta->flags = dtoh32(sta->flags);
++		sta->idle = dtoh32(sta->idle);
++		sta->in = dtoh32(sta->in);
++		sinfo->inactive_time = sta->idle * 1000;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++		if (sta->flags & WL_STA_ASSOC) {
++			sinfo->filled |= STA_INFO_BIT(INFO_CONNECTED_TIME);
++			sinfo->connected_time = sta->in;
++		}
++		WL_INFORM(("STA %s : idle time : %d sec, connected time :%d ms\n",
++			bcm_ether_ntoa((const struct ether_addr *)mac, eabuf), sinfo->inactive_time,
++			sta->idle * 1000));
++#endif
++	} else if (wl_get_mode_by_netdev(cfg, dev) == WL_MODE_BSS ||
++		wl_get_mode_by_netdev(cfg, dev) == WL_MODE_IBSS) {
++		get_pktcnt_t pktcnt;
++		u8 *curmacp;
++
++		if (cfg->roam_offload) {
++			struct ether_addr bssid;
++			memset(&bssid, 0, sizeof(bssid));
++			err = wldev_ioctl(dev, WLC_GET_BSSID, &bssid, ETHER_ADDR_LEN, false);
++			if (err) {
++				WL_ERR(("Failed to get current BSSID\n"));
++			} else {
++				if (!ETHER_ISNULLADDR(&bssid.octet) &&
++						memcmp(mac, &bssid.octet, ETHER_ADDR_LEN) != 0) {
++					/* roaming is detected */
++					err = wl_cfg80211_delayed_roam(cfg, dev, &bssid);
++					if (err)
++						WL_ERR(("Failed to handle the delayed roam, "
++							"err=%d", err));
++					mac = (u8 *)bssid.octet;
++				}
++			}
++		}
++		if (!wl_get_drv_status(cfg, CONNECTED, dev) ||
++			(dhd_is_associated(dhd, NULL, &err) == FALSE)) {
++			WL_ERR(("NOT assoc\n"));
++			if (err == -ERESTARTSYS)
++				return err;
++			err = -ENODEV;
++			return err;
++		}
++		curmacp = wl_read_prof(cfg, dev, WL_PROF_BSSID);
++		if (memcmp(mac, curmacp, ETHER_ADDR_LEN)) {
++			WL_ERR(("Wrong Mac address: "MACDBG" != "MACDBG"\n",
++				MAC2STRDBG(mac), MAC2STRDBG(curmacp)));
++		}
++
++		/* Report the current tx rate */
++		rate = 0;
++		err = wldev_ioctl(dev, WLC_GET_RATE, &rate, sizeof(rate), false);
++		if (err) {
++			WL_ERR(("Could not get rate (%d)\n", err));
++		} else {
++#if defined(USE_DYNAMIC_MAXPKT_RXGLOM)
++			int rxpktglom;
++#endif
++			rate = dtoh32(rate);
++			sinfo->filled |= STA_INFO_BIT(INFO_TX_BITRATE);
++			sinfo->txrate.legacy = rate * 5;
++			WL_DBG(("Rate %d Mbps\n", (rate / 2)));
++#if defined(USE_DYNAMIC_MAXPKT_RXGLOM)
++			rxpktglom = ((rate/2) > 150) ? 20 : 10;
++
++			if (maxrxpktglom != rxpktglom) {
++				maxrxpktglom = rxpktglom;
++				WL_DBG(("Rate %d Mbps, update bus:maxtxpktglom=%d\n", (rate/2),
++					maxrxpktglom));
++				err = wldev_iovar_setbuf(dev, "bus:maxtxpktglom",
++					(char*)&maxrxpktglom, 4, cfg->ioctl_buf,
++					WLC_IOCTL_MAXLEN, NULL);
++				if (err < 0) {
++					WL_ERR(("set bus:maxtxpktglom failed, %d\n", err));
++				}
++			}
++#endif
++		}
++
++		memset(&scb_val, 0, sizeof(scb_val));
++		scb_val.val = 0;
++		err = wldev_ioctl(dev, WLC_GET_RSSI, &scb_val,
++			sizeof(scb_val_t), false);
++		if (err) {
++			WL_ERR(("Could not get rssi (%d)\n", err));
++			goto get_station_err;
++		}
++		rssi = wl_rssi_offset(dtoh32(scb_val.val));
++		sinfo->filled |= STA_INFO_BIT(INFO_SIGNAL);
++		sinfo->signal = rssi;
++		WL_DBG(("RSSI %d dBm\n", rssi));
++		memset(&pktcnt, 0, sizeof(pktcnt));
++		err = wldev_ioctl(dev, WLC_GET_PKTCNTS, &pktcnt,
++			sizeof(pktcnt), false);
++		if (!err) {
++			sinfo->filled |= (STA_INFO_BIT(INFO_RX_PACKETS) |
++				STA_INFO_BIT(INFO_RX_DROP_MISC) |
++				STA_INFO_BIT(INFO_TX_PACKETS) |
++				STA_INFO_BIT(INFO_TX_FAILED));
++			sinfo->rx_packets = pktcnt.rx_good_pkt;
++			sinfo->rx_dropped_misc = pktcnt.rx_bad_pkt;
++			sinfo->tx_packets = pktcnt.tx_good_pkt;
++			sinfo->tx_failed  = pktcnt.tx_bad_pkt;
++		}
++get_station_err:
++		if (err && (err != -ERESTARTSYS)) {
++			/* Disconnect due to zero BSSID or error to get RSSI */
++			WL_ERR(("force cfg80211_disconnected: %d\n", err));
++			wl_clr_drv_status(cfg, CONNECTED, dev);
++			CFG80211_DISCONNECTED(dev, 0, NULL, 0, false, GFP_KERNEL);
++			wl_link_down(cfg);
++		}
++	}
++	else {
++		WL_ERR(("Invalid device mode %d\n", wl_get_mode_by_netdev(cfg, dev)));
++	}
++
++	return err;
++}
++
++static s32
++wl_cfg80211_set_power_mgmt(struct wiphy *wiphy, struct net_device *dev,
++	bool enabled, s32 timeout)
++{
++	s32 pm;
++	s32 err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_info *_net_info = wl_get_netinfo_by_netdev(cfg, dev);
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	WL_DBG(("Enter\n"));
++	if (cfg->p2p_net == dev || _net_info == NULL ||
++		!wl_get_drv_status(cfg, CONNECTED, dev)) {
++		return err;
++	}
++	/* Delete pm_enable_work */
++	wl_add_remove_pm_enable_work(cfg, FALSE, WL_HANDLER_PEND);
++
++	pm = enabled ? PM_FAST : PM_OFF;
++	if (_net_info->pm_block) {
++		WL_ERR(("%s:Do not enable the power save for pm_block %d\n",
++			dev->name, _net_info->pm_block));
++		pm = PM_OFF;
++	}
++	pm = htod32(pm);
++	WL_DBG(("%s:power save %s\n", dev->name, (pm ? "enabled" : "disabled")));
++	err = wldev_ioctl(dev, WLC_SET_PM, &pm, sizeof(pm), true);
++	if (unlikely(err)) {
++		if (err == -ENODEV)
++			WL_DBG(("net_device is not ready yet\n"));
++		else
++			WL_ERR(("error (%d)\n", err));
++		return err;
++	}
++	wl_cfg80211_update_power_mode(dev);
++	return err;
++}
++
++void wl_cfg80211_update_power_mode(struct net_device *dev)
++{
++	int err, pm = -1;
++
++	err = wldev_ioctl(dev, WLC_GET_PM, &pm, sizeof(pm), true);
++	if (err)
++		WL_ERR(("%s:error (%d)\n", __FUNCTION__, err));
++	else if (pm != -1 && dev->ieee80211_ptr)
++		dev->ieee80211_ptr->ps = (pm == PM_OFF) ? false : true;
++}
++
++void wl_cfg80211_set_passive_scan(struct net_device *dev, char *command)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++
++	if (strcmp(command, "SCAN-ACTIVE") == 0) {
++		cfg->active_scan = 1;
++	} else if (strcmp(command, "SCAN-PASSIVE") == 0) {
++		cfg->active_scan = 0;
++	} else
++		WL_ERR(("Unknown command \n"));
++}
++
++static __used u32 wl_find_msb(u16 bit16)
++{
++	u32 ret = 0;
++
++	if (bit16 & 0xff00) {
++		ret += 8;
++		bit16 >>= 8;
++	}
++
++	if (bit16 & 0xf0) {
++		ret += 4;
++		bit16 >>= 4;
++	}
++
++	if (bit16 & 0xc) {
++		ret += 2;
++		bit16 >>= 2;
++	}
++
++	if (bit16 & 2)
++		ret += bit16 & 2;
++	else if (bit16)
++		ret += bit16;
++
++	return ret;
++}
++
++static s32 wl_cfg80211_resume(struct wiphy *wiphy)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	s32 err = BCME_OK;
++
++	if (unlikely(!wl_get_drv_status(cfg, READY, ndev))) {
++		WL_INFORM(("device is not ready\n"));
++		return err;
++	}
++
++
++	return err;
++}
++
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39))
++static s32 wl_cfg80211_suspend(struct wiphy *wiphy, struct cfg80211_wowlan *wow)
++#else
++static s32 wl_cfg80211_suspend(struct wiphy *wiphy)
++#endif
++{
++	s32 err = BCME_OK;
++#ifdef DHD_CLEAR_ON_SUSPEND
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_info *iter, *next;
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	unsigned long flags;
++	if (unlikely(!wl_get_drv_status(cfg, READY, ndev))) {
++		WL_INFORM(("device is not ready : status (%d)\n",
++			(int)cfg->status));
++		return err;
++	}
++	for_each_ndev(cfg, iter, next) {
++		/* p2p discovery iface doesn't have a ndev associated with it (for kernel > 3.8) */
++		if (iter->ndev)
++			wl_set_drv_status(cfg, SCAN_ABORTING, iter->ndev);
++		}
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++	if (cfg->scan_request) {
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(4, 8, 0))
++		struct cfg80211_scan_info info = { .aborted = true };
++		cfg80211_scan_done(cfg->scan_request, &info);
++#else
++		cfg80211_scan_done(cfg->scan_request, true);
++#endif
++		cfg->scan_request = NULL;
++	}
++	for_each_ndev(cfg, iter, next) {
++		if (iter->ndev) {
++			wl_clr_drv_status(cfg, SCANNING, iter->ndev);
++			wl_clr_drv_status(cfg, SCAN_ABORTING, iter->ndev);
++		}
++	}
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++	for_each_ndev(cfg, iter, next) {
++		if (iter->ndev) {
++			if (wl_get_drv_status(cfg, CONNECTING, iter->ndev)) {
++				wl_bss_connect_done(cfg, iter->ndev, NULL, NULL, false);
++			}
++		}
++	}
++#endif /* DHD_CLEAR_ON_SUSPEND */
++
++
++#ifdef CUS_11321
++	{
++		struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++		struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++		u8 gpiopol = 0; // 0:Set active high when wake up, 1:Set active low when wake up
++		char strclear[6] = "clear";
++		u32 wowl = WL_WOWL_DIS | WL_WOWL_BCN | WL_WOWL_GTK_FAILURE | WL_WOWL_RETR |
++			WL_WOWL_TCPKEEP_TIME | WL_WOWL_TCPKEEP_DATA;
++
++		/* enable ARPOE */
++		wldev_iovar_setint(ndev, "arpoe", 1);
++		wldev_iovar_setint(ndev, "arp_ol", 0xf);
++		wldev_iovar_setint(ndev, "arp_peerage", 1000000);
++
++		/* enable GTKOE */
++		wldev_iovar_setint(ndev, "wake_event_enable", 4);
++
++		/* enable WOWL */
++		wldev_iovar_setint(ndev, "wowl_gpiopol", gpiopol);
++		wldev_iovar_setbuf(ndev, "wowl_wakeind", strclear, sizeof(strclear),
++			cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++		wldev_iovar_setint(ndev, "wowl", wowl);
++		wldev_iovar_setint(ndev, "wowl_activate", 1);
++	}
++#endif
++
++	return err;
++}
++
++static s32
++wl_update_pmklist(struct net_device *dev, struct wl_pmk_list *pmk_list,
++	s32 err)
++{
++	int i, j;
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	struct net_device *primary_dev = bcmcfg_to_prmry_ndev(cfg);
++
++	if (!pmk_list) {
++		printk("pmk_list is NULL\n");
++		return -EINVAL;
++	}
++	/* pmk list is supported only for STA interface i.e. primary interface
++	 * Refer code wlc_bsscfg.c->wlc_bsscfg_sta_init
++	 */
++	if (primary_dev != dev) {
++		WL_INFORM(("Not supporting Flushing pmklist on virtual"
++			" interfaces than primary interface\n"));
++		return err;
++	}
++
++	WL_DBG(("No of elements %d\n", pmk_list->pmkids.npmkid));
++	for (i = 0; i < pmk_list->pmkids.npmkid; i++) {
++		WL_DBG(("PMKID[%d]: %pM =\n", i,
++			&pmk_list->pmkids.pmkid[i].BSSID));
++		for (j = 0; j < WPA2_PMKID_LEN; j++) {
++			WL_DBG(("%02x\n", pmk_list->pmkids.pmkid[i].PMKID[j]));
++		}
++	}
++	if (likely(!err)) {
++		err = wldev_iovar_setbuf(dev, "pmkid_info", (char *)pmk_list,
++			sizeof(*pmk_list), cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++	}
++
++	return err;
++}
++
++static s32
++wl_cfg80211_set_pmksa(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_pmksa *pmksa)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 err = 0;
++	int i;
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	for (i = 0; i < cfg->pmk_list->pmkids.npmkid; i++)
++		if (!memcmp(pmksa->bssid, &cfg->pmk_list->pmkids.pmkid[i].BSSID,
++			ETHER_ADDR_LEN))
++			break;
++	if (i < WL_NUM_PMKIDS_MAX) {
++		memcpy(&cfg->pmk_list->pmkids.pmkid[i].BSSID, pmksa->bssid,
++			ETHER_ADDR_LEN);
++		memcpy(&cfg->pmk_list->pmkids.pmkid[i].PMKID, pmksa->pmkid,
++			WPA2_PMKID_LEN);
++		if (i == cfg->pmk_list->pmkids.npmkid)
++			cfg->pmk_list->pmkids.npmkid++;
++	} else {
++		err = -EINVAL;
++	}
++	WL_DBG(("set_pmksa,IW_PMKSA_ADD - PMKID: %pM =\n",
++		&cfg->pmk_list->pmkids.pmkid[cfg->pmk_list->pmkids.npmkid - 1].BSSID));
++	for (i = 0; i < WPA2_PMKID_LEN; i++) {
++		WL_DBG(("%02x\n",
++			cfg->pmk_list->pmkids.pmkid[cfg->pmk_list->pmkids.npmkid - 1].
++			PMKID[i]));
++	}
++
++	err = wl_update_pmklist(dev, cfg->pmk_list, err);
++
++	return err;
++}
++
++static s32
++wl_cfg80211_del_pmksa(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_pmksa *pmksa)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	struct _pmkid_list pmkid = {.npmkid = 0};
++	s32 err = 0;
++	int i;
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++	memcpy(&pmkid.pmkid[0].BSSID, pmksa->bssid, ETHER_ADDR_LEN);
++	memcpy(pmkid.pmkid[0].PMKID, pmksa->pmkid, WPA2_PMKID_LEN);
++
++	WL_DBG(("del_pmksa,IW_PMKSA_REMOVE - PMKID: %pM =\n",
++		&pmkid.pmkid[0].BSSID));
++	for (i = 0; i < WPA2_PMKID_LEN; i++) {
++		WL_DBG(("%02x\n", pmkid.pmkid[0].PMKID[i]));
++	}
++
++	for (i = 0; i < cfg->pmk_list->pmkids.npmkid; i++)
++		if (!memcmp
++		    (pmksa->bssid, &cfg->pmk_list->pmkids.pmkid[i].BSSID,
++		     ETHER_ADDR_LEN))
++			break;
++
++	if ((cfg->pmk_list->pmkids.npmkid > 0) &&
++		(i < cfg->pmk_list->pmkids.npmkid)) {
++		memset(&cfg->pmk_list->pmkids.pmkid[i], 0, sizeof(pmkid_t));
++		for (; i < (cfg->pmk_list->pmkids.npmkid - 1); i++) {
++			memcpy(&cfg->pmk_list->pmkids.pmkid[i].BSSID,
++				&cfg->pmk_list->pmkids.pmkid[i + 1].BSSID,
++				ETHER_ADDR_LEN);
++			memcpy(&cfg->pmk_list->pmkids.pmkid[i].PMKID,
++				&cfg->pmk_list->pmkids.pmkid[i + 1].PMKID,
++				WPA2_PMKID_LEN);
++		}
++		cfg->pmk_list->pmkids.npmkid--;
++	} else {
++		err = -EINVAL;
++	}
++
++	err = wl_update_pmklist(dev, cfg->pmk_list, err);
++
++	return err;
++
++}
++
++static s32
++wl_cfg80211_flush_pmksa(struct wiphy *wiphy, struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 err = 0;
++	RETURN_EIO_IF_NOT_UP(cfg);
++	memset(cfg->pmk_list, 0, sizeof(*cfg->pmk_list));
++	err = wl_update_pmklist(dev, cfg->pmk_list, err);
++	return err;
++
++}
++
++static wl_scan_params_t *
++wl_cfg80211_scan_alloc_params(int channel, int nprobes, int *out_params_size)
++{
++	wl_scan_params_t *params;
++	int params_size;
++	int num_chans;
++	int bssidx = 0;
++
++	*out_params_size = 0;
++
++	/* Our scan params only need space for 1 channel and 0 ssids */
++	params_size = WL_SCAN_PARAMS_FIXED_SIZE + 1 * sizeof(uint16);
++	params = (wl_scan_params_t*) kzalloc(params_size, GFP_KERNEL);
++	if (params == NULL) {
++		WL_ERR(("mem alloc failed (%d bytes)\n", params_size));
++		return params;
++	}
++	memset(params, 0, params_size);
++	params->nprobes = nprobes;
++
++	num_chans = (channel == 0) ? 0 : 1;
++
++	memcpy(&params->bssid, &ether_bcast, ETHER_ADDR_LEN);
++	params->bss_type = DOT11_BSSTYPE_ANY;
++	params->scan_type = DOT11_SCANTYPE_ACTIVE;
++	params->nprobes = htod32(1);
++	params->active_time = htod32(-1);
++	params->passive_time = htod32(-1);
++	params->home_time = htod32(10);
++	if (channel == -1)
++		params->channel_list[0] = htodchanspec(channel);
++	else
++		params->channel_list[0] = wl_ch_host_to_driver(bssidx, channel);
++
++	/* Our scan params have 1 channel and 0 ssids */
++	params->channel_num = htod32((0 << WL_SCAN_PARAMS_NSSID_SHIFT) |
++		(num_chans & WL_SCAN_PARAMS_COUNT_MASK));
++
++	*out_params_size = params_size;	/* rtn size to the caller */
++	return params;
++}
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++static s32
++wl_cfg80211_remain_on_channel(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev,
++	struct ieee80211_channel *channel, unsigned int duration, u64 *cookie)
++#else
++static s32
++wl_cfg80211_remain_on_channel(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev,
++	struct ieee80211_channel * channel,
++	enum nl80211_channel_type channel_type,
++	unsigned int duration, u64 *cookie)
++#endif /* WL_CFG80211_P2P_DEV_IF */
++{
++	s32 target_channel;
++	u32 id;
++	s32 err = BCME_OK;
++	struct ether_addr primary_mac;
++	struct net_device *ndev = NULL;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	WL_DBG(("Enter, channel: %d, duration ms (%d) SCANNING ?? %s \n",
++		ieee80211_frequency_to_channel(channel->center_freq),
++		duration, (wl_get_drv_status(cfg, SCANNING, ndev)) ? "YES":"NO"));
++
++	if (!cfg->p2p) {
++		WL_ERR(("cfg->p2p is not initialized\n"));
++		err = BCME_ERROR;
++		goto exit;
++	}
++
++#ifndef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++	if (wl_get_drv_status_all(cfg, SCANNING)) {
++		wl_notify_escan_complete(cfg, cfg->escan_info.ndev, true, true);
++	}
++#endif /* not WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++
++	target_channel = ieee80211_frequency_to_channel(channel->center_freq);
++	memcpy(&cfg->remain_on_chan, channel, sizeof(struct ieee80211_channel));
++#if defined(WL_ENABLE_P2P_IF)
++	cfg->remain_on_chan_type = channel_type;
++#endif /* WL_ENABLE_P2P_IF */
++	id = ++cfg->last_roc_id;
++	if (id == 0)
++		id = ++cfg->last_roc_id;
++	*cookie = id;
++
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++	if (wl_get_drv_status(cfg, SCANNING, ndev)) {
++		struct timer_list *_timer;
++		WL_DBG(("scan is running. go to fake listen state\n"));
++
++		if (duration > LONG_LISTEN_TIME) {
++			wl_cfg80211_scan_abort(cfg);
++		} else {
++			wl_set_drv_status(cfg, FAKE_REMAINING_ON_CHANNEL, ndev);
++
++			if (timer_pending(&cfg->p2p->listen_timer)) {
++				WL_DBG(("cancel current listen timer \n"));
++				del_timer_sync(&cfg->p2p->listen_timer);
++			}
++
++			_timer = (struct timer_list *) &cfg->p2p->listen_timer;
++			wl_clr_p2p_status(cfg, LISTEN_EXPIRED);
++
++			INIT_TIMER(_timer, wl_cfgp2p_listen_expired, duration, 0);
++
++			err = BCME_OK;
++			goto exit;
++		}
++	}
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++
++#ifdef WL_CFG80211_SYNC_GON
++	if (wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM_LISTEN)) {
++		/* do not enter listen mode again if we are in listen mode already for next af.
++		 * remain on channel completion will be returned by waiting next af completion.
++		 */
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++		wl_set_drv_status(cfg, FAKE_REMAINING_ON_CHANNEL, ndev);
++#else
++		wl_set_drv_status(cfg, REMAINING_ON_CHANNEL, ndev);
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++		goto exit;
++	}
++#endif /* WL_CFG80211_SYNC_GON */
++	if (cfg->p2p && !cfg->p2p->on) {
++		/* In case of p2p_listen command, supplicant send remain_on_channel
++		 * without turning on P2P
++		 */
++		get_primary_mac(cfg, &primary_mac);
++		wl_cfgp2p_generate_bss_mac(cfg, &primary_mac);
++		p2p_on(cfg) = true;
++	}
++
++	if (p2p_is_on(cfg)) {
++		err = wl_cfgp2p_enable_discovery(cfg, ndev, NULL, 0);
++		if (unlikely(err)) {
++			goto exit;
++		}
++#ifndef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++		wl_set_drv_status(cfg, REMAINING_ON_CHANNEL, ndev);
++#endif /* not WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++		err = wl_cfgp2p_discover_listen(cfg, target_channel, duration);
++
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++		if (err == BCME_OK) {
++			wl_set_drv_status(cfg, REMAINING_ON_CHANNEL, ndev);
++		} else {
++			/* if failed, firmware may be internal scanning state.
++			 * so other scan request shall not abort it
++			 */
++			wl_set_drv_status(cfg, FAKE_REMAINING_ON_CHANNEL, ndev);
++		}
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++		/* WAR: set err = ok to prevent cookie mismatch in wpa_supplicant
++		 * and expire timer will send a completion to the upper layer
++		 */
++		err = BCME_OK;
++	}
++
++exit:
++	if (err == BCME_OK) {
++		WL_INFORM(("Success\n"));
++#if defined(WL_CFG80211_P2P_DEV_IF)
++		cfg80211_ready_on_channel(cfgdev, *cookie, channel,
++			duration, GFP_KERNEL);
++#else
++		cfg80211_ready_on_channel(cfgdev, *cookie, channel,
++			channel_type, duration, GFP_KERNEL);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++	} else {
++		WL_ERR(("Fail to Set (err=%d cookie:%llu)\n", err, *cookie));
++	}
++	return err;
++}
++
++static s32
++wl_cfg80211_cancel_remain_on_channel(struct wiphy *wiphy,
++	bcm_struct_cfgdev *cfgdev, u64 cookie)
++{
++	s32 err = 0;
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++
++#ifdef P2PLISTEN_AP_SAMECHN
++	struct net_device *dev;
++#endif /* P2PLISTEN_AP_SAMECHN */
++
++	RETURN_EIO_IF_NOT_UP(cfg);
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	if (cfgdev->iftype == NL80211_IFTYPE_P2P_DEVICE) {
++		WL_DBG((" enter ) on P2P dedicated discover interface\n"));
++	}
++#else
++	WL_DBG((" enter ) netdev_ifidx: %d \n", cfgdev->ifindex));
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++#ifdef P2PLISTEN_AP_SAMECHN
++	if (cfg && cfg->p2p_resp_apchn_status) {
++		dev = bcmcfg_to_prmry_ndev(cfg);
++		wl_cfg80211_set_p2p_resp_ap_chn(dev, 0);
++		cfg->p2p_resp_apchn_status = false;
++		WL_DBG(("p2p_resp_apchn_status Turn OFF \n"));
++	}
++#endif /* P2PLISTEN_AP_SAMECHN */
++
++	if (cfg->last_roc_id == cookie) {
++		wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_SCAN, 0, 0,
++			wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE));
++	} else {
++		WL_ERR(("%s : ignore, request cookie(%llu) is not matched. (cur : %llu)\n",
++			__FUNCTION__, cookie, cfg->last_roc_id));
++	}
++
++	return err;
++}
++
++static void
++wl_cfg80211_afx_handler(struct work_struct *work)
++{
++	struct afx_hdl *afx_instance;
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	s32 ret = BCME_OK;
++
++	BCM_SET_CONTAINER_OF(afx_instance, work, struct afx_hdl, work);
++	if (afx_instance != NULL && cfg->afx_hdl->is_active) {
++		if (cfg->afx_hdl->is_listen && cfg->afx_hdl->my_listen_chan) {
++			ret = wl_cfgp2p_discover_listen(cfg, cfg->afx_hdl->my_listen_chan,
++				(100 * (1 + (RANDOM32() % 3)))); /* 100ms ~ 300ms */
++		} else {
++			ret = wl_cfgp2p_act_frm_search(cfg, cfg->afx_hdl->dev,
++				cfg->afx_hdl->bssidx, cfg->afx_hdl->peer_listen_chan,
++				NULL);
++		}
++		if (unlikely(ret != BCME_OK)) {
++			WL_ERR(("ERROR occurred! returned value is (%d)\n", ret));
++			if (wl_get_drv_status_all(cfg, FINDING_COMMON_CHANNEL))
++				complete(&cfg->act_frm_scan);
++		}
++	}
++}
++
++static s32
++wl_cfg80211_af_searching_channel(struct bcm_cfg80211 *cfg, struct net_device *dev)
++{
++	u32 max_retry = WL_CHANNEL_SYNC_RETRY;
++
++	if (dev == NULL)
++		return -1;
++
++	WL_DBG((" enter ) \n"));
++
++	wl_set_drv_status(cfg, FINDING_COMMON_CHANNEL, dev);
++	cfg->afx_hdl->is_active = TRUE;
++
++	/* Loop to wait until we find a peer's channel or the
++	 * pending action frame tx is cancelled.
++	 */
++	while ((cfg->afx_hdl->retry < max_retry) &&
++		(cfg->afx_hdl->peer_chan == WL_INVALID)) {
++		cfg->afx_hdl->is_listen = FALSE;
++		wl_set_drv_status(cfg, SCANNING, dev);
++		WL_DBG(("Scheduling the action frame for sending.. retry %d\n",
++			cfg->afx_hdl->retry));
++		/* search peer on peer's listen channel */
++		schedule_work(&cfg->afx_hdl->work);
++		wait_for_completion_timeout(&cfg->act_frm_scan,
++			msecs_to_jiffies(WL_AF_SEARCH_TIME_MAX));
++
++		if ((cfg->afx_hdl->peer_chan != WL_INVALID) ||
++			!(wl_get_drv_status(cfg, FINDING_COMMON_CHANNEL, dev)))
++			break;
++
++		if (cfg->afx_hdl->my_listen_chan) {
++			WL_DBG(("Scheduling Listen peer in my listen channel = %d\n",
++				cfg->afx_hdl->my_listen_chan));
++			/* listen on my listen channel */
++			cfg->afx_hdl->is_listen = TRUE;
++			schedule_work(&cfg->afx_hdl->work);
++			wait_for_completion_timeout(&cfg->act_frm_scan,
++				msecs_to_jiffies(WL_AF_SEARCH_TIME_MAX));
++		}
++		if ((cfg->afx_hdl->peer_chan != WL_INVALID) ||
++			!(wl_get_drv_status(cfg, FINDING_COMMON_CHANNEL, dev)))
++			break;
++
++		cfg->afx_hdl->retry++;
++
++		WL_AF_TX_KEEP_PRI_CONNECTION_VSDB(cfg);
++	}
++
++	cfg->afx_hdl->is_active = FALSE;
++
++	wl_clr_drv_status(cfg, SCANNING, dev);
++	wl_clr_drv_status(cfg, FINDING_COMMON_CHANNEL, dev);
++
++	return (cfg->afx_hdl->peer_chan);
++}
++
++struct p2p_config_af_params {
++	s32 max_tx_retry;	/* max tx retry count if tx no ack */
++	/* To make sure to send successfully action frame, we have to turn off mpc
++	 * 0: off, 1: on,  (-1): do nothing
++	 */
++	s32 mpc_onoff;
++#ifdef WL_CFG80211_SYNC_GON
++	bool extra_listen;
++#endif
++	bool search_channel;	/* 1: search peer's channel to send af */
++};
++
++static s32
++wl_cfg80211_config_p2p_pub_af_tx(struct wiphy *wiphy,
++	wl_action_frame_t *action_frame, wl_af_params_t *af_params,
++	struct p2p_config_af_params *config_af_params)
++{
++	s32 err = BCME_OK;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	wifi_p2p_pub_act_frame_t *act_frm =
++		(wifi_p2p_pub_act_frame_t *) (action_frame->data);
++
++	/* initialize default value */
++#ifdef WL_CFG80211_SYNC_GON
++	config_af_params->extra_listen = true;
++#endif
++	config_af_params->search_channel = false;
++	config_af_params->max_tx_retry = WL_AF_TX_MAX_RETRY;
++	config_af_params->mpc_onoff = -1;
++	cfg->next_af_subtype = P2P_PAF_SUBTYPE_INVALID;
++
++	switch (act_frm->subtype) {
++	case P2P_PAF_GON_REQ: {
++		WL_DBG(("P2P: GO_NEG_PHASE status set \n"));
++		wl_set_p2p_status(cfg, GO_NEG_PHASE);
++
++		config_af_params->mpc_onoff = 0;
++		config_af_params->search_channel = true;
++		cfg->next_af_subtype = act_frm->subtype + 1;
++
++		/* increase dwell time to wait for RESP frame */
++		af_params->dwell_time = WL_MED_DWELL_TIME;
++
++		break;
++	}
++	case P2P_PAF_GON_RSP: {
++		cfg->next_af_subtype = act_frm->subtype + 1;
++		/* increase dwell time to wait for CONF frame */
++		af_params->dwell_time = WL_MED_DWELL_TIME + 100;
++		break;
++	}
++	case P2P_PAF_GON_CONF: {
++		/* If we reached till GO Neg confirmation reset the filter */
++		WL_DBG(("P2P: GO_NEG_PHASE status cleared \n"));
++		wl_clr_p2p_status(cfg, GO_NEG_PHASE);
++
++		/* turn on mpc again if go nego is done */
++		config_af_params->mpc_onoff = 1;
++
++		/* minimize dwell time */
++		af_params->dwell_time = WL_MIN_DWELL_TIME;
++
++#ifdef WL_CFG80211_SYNC_GON
++		config_af_params->extra_listen = false;
++#endif /* WL_CFG80211_SYNC_GON */
++		break;
++	}
++	case P2P_PAF_INVITE_REQ: {
++		config_af_params->search_channel = true;
++		cfg->next_af_subtype = act_frm->subtype + 1;
++
++		/* increase dwell time */
++		af_params->dwell_time = WL_MED_DWELL_TIME;
++		break;
++	}
++	case P2P_PAF_INVITE_RSP:
++		/* minimize dwell time */
++		af_params->dwell_time = WL_MIN_DWELL_TIME;
++#ifdef WL_CFG80211_SYNC_GON
++		config_af_params->extra_listen = false;
++#endif /* WL_CFG80211_SYNC_GON */
++		break;
++	case P2P_PAF_DEVDIS_REQ: {
++		if (IS_ACTPUB_WITHOUT_GROUP_ID(&act_frm->elts[0],
++			action_frame->len)) {
++			config_af_params->search_channel = true;
++		}
++
++		cfg->next_af_subtype = act_frm->subtype + 1;
++		/* maximize dwell time to wait for RESP frame */
++		af_params->dwell_time = WL_LONG_DWELL_TIME;
++		break;
++	}
++	case P2P_PAF_DEVDIS_RSP:
++		/* minimize dwell time */
++		af_params->dwell_time = WL_MIN_DWELL_TIME;
++#ifdef WL_CFG80211_SYNC_GON
++		config_af_params->extra_listen = false;
++#endif /* WL_CFG80211_SYNC_GON */
++		break;
++	case P2P_PAF_PROVDIS_REQ: {
++		if (IS_ACTPUB_WITHOUT_GROUP_ID(&act_frm->elts[0],
++			action_frame->len)) {
++			config_af_params->search_channel = true;
++		}
++
++		config_af_params->mpc_onoff = 0;
++		cfg->next_af_subtype = act_frm->subtype + 1;
++		/* increase dwell time to wait for RESP frame */
++		af_params->dwell_time = WL_MED_DWELL_TIME;
++		break;
++	}
++	case P2P_PAF_PROVDIS_RSP: {
++		cfg->next_af_subtype = P2P_PAF_GON_REQ;
++		af_params->dwell_time = WL_MIN_DWELL_TIME;
++#ifdef WL_CFG80211_SYNC_GON
++		config_af_params->extra_listen = false;
++#endif /* WL_CFG80211_SYNC_GON */
++		break;
++	}
++	default:
++		WL_DBG(("Unknown p2p pub act frame subtype: %d\n",
++			act_frm->subtype));
++		err = BCME_BADARG;
++	}
++	return err;
++}
++
++#ifdef WL11U
++static bool
++wl_cfg80211_check_DFS_channel(struct bcm_cfg80211 *cfg, wl_af_params_t *af_params,
++	void *frame, u16 frame_len)
++{
++	struct wl_scan_results *bss_list;
++	struct wl_bss_info *bi = NULL;
++	bool result = false;
++	s32 i;
++	chanspec_t chanspec;
++
++	/* If DFS channel is 52~148, check to block it or not */
++	if (af_params &&
++		(af_params->channel >= 52 && af_params->channel <= 148)) {
++		if (!wl_cfgp2p_is_p2p_action(frame, frame_len)) {
++			bss_list = cfg->bss_list;
++			bi = next_bss(bss_list, bi);
++			for_each_bss(bss_list, bi, i) {
++				chanspec = wl_chspec_driver_to_host(bi->chanspec);
++				if (CHSPEC_IS5G(chanspec) &&
++					((bi->ctl_ch ? bi->ctl_ch : CHSPEC_CHANNEL(chanspec))
++					== af_params->channel)) {
++					result = true;	/* do not block the action frame */
++					break;
++				}
++			}
++		}
++	}
++	else {
++		result = true;
++	}
++
++	WL_DBG(("result=%s", result?"true":"false"));
++	return result;
++}
++#endif /* WL11U */
++
++
++static bool
++wl_cfg80211_send_action_frame(struct wiphy *wiphy, struct net_device *dev,
++	bcm_struct_cfgdev *cfgdev, wl_af_params_t *af_params,
++	wl_action_frame_t *action_frame, u16 action_frame_len, s32 bssidx)
++{
++#ifdef WL11U
++	struct net_device *ndev = NULL;
++#endif /* WL11U */
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	bool ack = false;
++	u8 category, action;
++	s32 tx_retry;
++	struct p2p_config_af_params config_af_params;
++	struct net_info *netinfo;
++#ifdef VSDB
++	ulong off_chan_started_jiffies = 0;
++#endif
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++
++
++	/* Add the default dwell time
++	 * Dwell time to stay off-channel to wait for a response action frame
++	 * after transmitting an GO Negotiation action frame
++	 */
++	af_params->dwell_time = WL_DWELL_TIME;
++
++#ifdef WL11U
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	ndev = dev;
++#else
++	ndev = ndev_to_cfgdev(cfgdev);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++#endif /* WL11U */
++
++	category = action_frame->data[DOT11_ACTION_CAT_OFF];
++	action = action_frame->data[DOT11_ACTION_ACT_OFF];
++
++	/* initialize variables */
++	tx_retry = 0;
++	cfg->next_af_subtype = P2P_PAF_SUBTYPE_INVALID;
++	config_af_params.max_tx_retry = WL_AF_TX_MAX_RETRY;
++	config_af_params.mpc_onoff = -1;
++	config_af_params.search_channel = false;
++#ifdef WL_CFG80211_SYNC_GON
++	config_af_params.extra_listen = false;
++#endif
++
++	/* config parameters */
++	/* Public Action Frame Process - DOT11_ACTION_CAT_PUBLIC */
++	if (category == DOT11_ACTION_CAT_PUBLIC) {
++		if ((action == P2P_PUB_AF_ACTION) &&
++			(action_frame_len >= sizeof(wifi_p2p_pub_act_frame_t))) {
++			/* p2p public action frame process */
++			if (BCME_OK != wl_cfg80211_config_p2p_pub_af_tx(wiphy,
++				action_frame, af_params, &config_af_params)) {
++				WL_DBG(("Unknown subtype.\n"));
++			}
++
++		} else if (action_frame_len >= sizeof(wifi_p2psd_gas_pub_act_frame_t)) {
++			/* service discovery process */
++			if (action == P2PSD_ACTION_ID_GAS_IREQ ||
++				action == P2PSD_ACTION_ID_GAS_CREQ) {
++				/* configure service discovery query frame */
++
++				config_af_params.search_channel = true;
++
++				/* save next af suptype to cancel remained dwell time */
++				cfg->next_af_subtype = action + 1;
++
++				af_params->dwell_time = WL_MED_DWELL_TIME;
++			} else if (action == P2PSD_ACTION_ID_GAS_IRESP ||
++				action == P2PSD_ACTION_ID_GAS_CRESP) {
++				/* configure service discovery response frame */
++				af_params->dwell_time = WL_MIN_DWELL_TIME;
++			} else {
++				WL_DBG(("Unknown action type: %d\n", action));
++			}
++		} else {
++			WL_DBG(("Unknown Frame: category 0x%x, action 0x%x, length %d\n",
++				category, action, action_frame_len));
++	}
++	} else if (category == P2P_AF_CATEGORY) {
++		/* do not configure anything. it will be sent with a default configuration */
++	} else {
++		WL_DBG(("Unknown Frame: category 0x%x, action 0x%x\n",
++			category, action));
++		if (dhd->op_mode & DHD_FLAG_HOSTAP_MODE) {
++			wl_clr_drv_status(cfg, SENDING_ACT_FRM, dev);
++			return false;
++		}
++	}
++
++	/* To make sure to send successfully action frame, we have to turn off mpc */
++	if (config_af_params.mpc_onoff == 0) {
++		wldev_iovar_setint(dev, "mpc", 0);
++	}
++
++	netinfo = wl_get_netinfo_by_bssidx(cfg, bssidx);
++	/* validate channel and p2p ies */
++	if (config_af_params.search_channel && IS_P2P_SOCIAL(af_params->channel) &&
++		netinfo && netinfo->bss.ies.probe_req_ie_len) {
++		config_af_params.search_channel = true;
++	} else {
++		config_af_params.search_channel = false;
++	}
++#ifdef WL11U
++	if (ndev == bcmcfg_to_prmry_ndev(cfg))
++		config_af_params.search_channel = false;
++#endif /* WL11U */
++
++#ifdef VSDB
++	/* if connecting on primary iface, sleep for a while before sending af tx for VSDB */
++	if (wl_get_drv_status(cfg, CONNECTING, bcmcfg_to_prmry_ndev(cfg))) {
++		OSL_SLEEP(50);
++	}
++#endif
++
++	/* if scan is ongoing, abort current scan. */
++	if (wl_get_drv_status_all(cfg, SCANNING)) {
++		wl_notify_escan_complete(cfg, cfg->escan_info.ndev, true, true);
++	}
++
++	/* Abort P2P listen */
++	if (discover_cfgdev(cfgdev, cfg)) {
++		if (cfg->p2p_supported && cfg->p2p) {
++			wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_SCAN, 0, 0,
++				wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE));
++		}
++	}
++
++#ifdef WL11U
++	/* handling DFS channel exceptions */
++	if (!wl_cfg80211_check_DFS_channel(cfg, af_params, action_frame->data, action_frame->len)) {
++		return false;	/* the action frame was blocked */
++	}
++#endif /* WL11U */
++
++	/* set status and destination address before sending af */
++	if (cfg->next_af_subtype != P2P_PAF_SUBTYPE_INVALID) {
++		/* set this status to cancel the remained dwell time in rx process */
++		wl_set_drv_status(cfg, WAITING_NEXT_ACT_FRM, dev);
++	}
++	wl_set_drv_status(cfg, SENDING_ACT_FRM, dev);
++	memcpy(cfg->afx_hdl->tx_dst_addr.octet,
++		af_params->action_frame.da.octet,
++		sizeof(cfg->afx_hdl->tx_dst_addr.octet));
++
++	/* save af_params for rx process */
++	cfg->afx_hdl->pending_tx_act_frm = af_params;
++
++	if (wl_cfgp2p_is_p2p_gas_action(action_frame->data, action_frame->len)) {
++		WL_DBG(("Set GAS action frame config.\n"));
++		config_af_params.search_channel = false;
++		config_af_params.max_tx_retry = 1;
++	}
++
++	/* search peer's channel */
++	if (config_af_params.search_channel) {
++		/* initialize afx_hdl */
++		if ((cfg->afx_hdl->bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++			WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++			goto exit;
++		}
++		cfg->afx_hdl->dev = dev;
++		cfg->afx_hdl->retry = 0;
++		cfg->afx_hdl->peer_chan = WL_INVALID;
++
++		if (wl_cfg80211_af_searching_channel(cfg, dev) == WL_INVALID) {
++			WL_ERR(("couldn't find peer's channel.\n"));
++			wl_cfgp2p_print_actframe(true, action_frame->data, action_frame->len,
++				af_params->channel);
++			goto exit;
++		}
++
++		wl_clr_drv_status(cfg, SCANNING, cfg->afx_hdl->dev);
++		/*
++		 * Abort scan even for VSDB scenarios. Scan gets aborted in firmware
++		 * but after the check of piggyback algorithm.
++		 * To take care of current piggback algo, lets abort the scan here itself.
++		 */
++		wl_notify_escan_complete(cfg, dev, true, true);
++		/* Suspend P2P discovery's search-listen to prevent it from
++		 * starting a scan or changing the channel.
++		 */
++		if ((wl_cfgp2p_discover_enable_search(cfg, false)) < 0) {
++			WL_ERR(("Can not disable discovery mode\n"));
++			goto exit;
++		}
++
++		/* update channel */
++		af_params->channel = cfg->afx_hdl->peer_chan;
++	}
++
++#ifdef VSDB
++	off_chan_started_jiffies = jiffies;
++#endif /* VSDB */
++
++	wl_cfgp2p_print_actframe(true, action_frame->data, action_frame->len, af_params->channel);
++
++	wl_cfgp2p_need_wait_actfrmae(cfg, action_frame->data, action_frame->len, true);
++
++	/* Now send a tx action frame */
++	ack = wl_cfgp2p_tx_action_frame(cfg, dev, af_params, bssidx) ? false : true;
++
++	/* if failed, retry it. tx_retry_max value is configure by .... */
++	while ((ack == false) && (tx_retry++ < config_af_params.max_tx_retry)) {
++#ifdef VSDB
++		if (af_params->channel) {
++			if (jiffies_to_msecs(jiffies - off_chan_started_jiffies) >
++				OFF_CHAN_TIME_THRESHOLD_MS) {
++				WL_AF_TX_KEEP_PRI_CONNECTION_VSDB(cfg);
++				off_chan_started_jiffies = jiffies;
++			} else
++				OSL_SLEEP(AF_RETRY_DELAY_TIME);
++		}
++#endif /* VSDB */
++		ack = wl_cfgp2p_tx_action_frame(cfg, dev, af_params, bssidx) ?
++			false : true;
++	}
++
++	if (ack == false) {
++		WL_ERR(("Failed to send Action Frame(retry %d)\n", tx_retry));
++	}
++	WL_DBG(("Complete to send action frame\n"));
++exit:
++	/* Clear SENDING_ACT_FRM after all sending af is done */
++	wl_clr_drv_status(cfg, SENDING_ACT_FRM, dev);
++
++#ifdef WL_CFG80211_SYNC_GON
++	/* WAR: sometimes dongle does not keep the dwell time of 'actframe'.
++	 * if we coundn't get the next action response frame and dongle does not keep
++	 * the dwell time, go to listen state again to get next action response frame.
++	 */
++	if (ack && config_af_params.extra_listen &&
++		wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM) &&
++		cfg->af_sent_channel == cfg->afx_hdl->my_listen_chan) {
++		s32 extar_listen_time;
++
++		extar_listen_time = af_params->dwell_time -
++			jiffies_to_msecs(jiffies - cfg->af_tx_sent_jiffies);
++
++		if (extar_listen_time > 50) {
++			wl_set_drv_status(cfg, WAITING_NEXT_ACT_FRM_LISTEN, dev);
++			WL_DBG(("Wait more time! actual af time:%d,"
++				"calculated extar listen:%d\n",
++				af_params->dwell_time, extar_listen_time));
++			if (wl_cfgp2p_discover_listen(cfg, cfg->af_sent_channel,
++				extar_listen_time + 100) == BCME_OK) {
++				wait_for_completion_timeout(&cfg->wait_next_af,
++					msecs_to_jiffies(extar_listen_time + 100 + 300));
++			}
++			wl_clr_drv_status(cfg, WAITING_NEXT_ACT_FRM_LISTEN, dev);
++		}
++	}
++#endif /* WL_CFG80211_SYNC_GON */
++	wl_clr_drv_status(cfg, WAITING_NEXT_ACT_FRM, dev);
++
++	if (cfg->afx_hdl->pending_tx_act_frm)
++		cfg->afx_hdl->pending_tx_act_frm = NULL;
++
++	WL_INFORM(("-- sending Action Frame is %s, listen chan: %d\n",
++		(ack) ? "Succeeded!!":"Failed!!", cfg->afx_hdl->my_listen_chan));
++
++
++	/* if all done, turn mpc on again */
++	if (config_af_params.mpc_onoff == 1) {
++		wldev_iovar_setint(dev, "mpc", 1);
++	}
++
++	return ack;
++}
++
++#define MAX_NUM_OF_ASSOCIATED_DEV       64
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
++static s32
++wl_cfg80211_mgmt_tx(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev,
++	struct cfg80211_mgmt_tx_params *params, u64 *cookie)
++#else
++static s32
++wl_cfg80211_mgmt_tx(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev,
++	struct ieee80211_channel *channel, bool offchan,
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 7, 0))
++	enum nl80211_channel_type channel_type,
++	bool channel_type_valid,
++#endif /* LINUX_VERSION_CODE <= KERNEL_VERSION(3, 7, 0) */
++	unsigned int wait, const u8* buf, size_t len,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	bool no_cck,
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
++	bool dont_wait_for_ack,
++#endif
++	u64 *cookie)
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) */
++{
++	wl_action_frame_t *action_frame;
++	wl_af_params_t *af_params;
++	scb_val_t scb_val;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
++	struct ieee80211_channel *channel = params->chan;
++	const u8 *buf = params->buf;
++	size_t len = params->len;
++#endif
++	const struct ieee80211_mgmt *mgmt;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *dev = NULL;
++	s32 err = BCME_OK;
++	s32 bssidx = 0;
++	u32 id;
++	bool ack = false;
++	s8 eabuf[ETHER_ADDR_STR_LEN];
++
++	WL_DBG(("Enter \n"));
++
++	/* The CVE-2017-0706.dff patched here manually */
++	if (len > ACTION_FRAME_SIZE) {
++		WL_ERR(("bad length:%zu\n", len));
++		return BCME_BADLEN;
++	}
++
++	dev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	if (!dev) {
++		WL_ERR(("dev is NULL\n"));
++		return -EINVAL;
++	}
++
++	if (len > ACTION_FRAME_SIZE) {
++		WL_ERR(("bad length:%zu\n", len));
++		return BCME_BADLEN;
++	}
++
++	/* set bsscfg idx for iovar (wlan0: P2PAPI_BSSCFG_PRIMARY, p2p: P2PAPI_BSSCFG_DEVICE)	*/
++	if (discover_cfgdev(cfgdev, cfg)) {
++		if (!cfg->p2p_supported || !cfg->p2p) {
++			WL_ERR(("P2P doesn't setup completed yet\n"));
++			return -EINVAL;
++		}
++		bssidx = wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++	}
++	else {
++		if ((bssidx = wl_get_bssidx_by_wdev(cfg, cfgdev_to_wdev(cfgdev))) < 0) {
++			WL_ERR(("Find p2p index failed\n"));
++			return BCME_ERROR;
++		}
++	}
++
++	WL_DBG(("TX target bssidx=%d\n", bssidx));
++
++	if (p2p_is_on(cfg)) {
++		/* Suspend P2P discovery search-listen to prevent it from changing the
++		 * channel.
++		 */
++		if ((err = wl_cfgp2p_discover_enable_search(cfg, false)) < 0) {
++			WL_ERR(("Can not disable discovery mode\n"));
++			return -EFAULT;
++		}
++	}
++	*cookie = 0;
++	id = cfg->send_action_id++;
++	if (id == 0)
++		id = cfg->send_action_id++;
++	*cookie = id;
++	mgmt = (const struct ieee80211_mgmt *)buf;
++	if (ieee80211_is_mgmt(mgmt->frame_control)) {
++		if (ieee80211_is_probe_resp(mgmt->frame_control)) {
++			s32 ie_offset =  DOT11_MGMT_HDR_LEN + DOT11_BCN_PRB_FIXED_LEN;
++			s32 ie_len = len - ie_offset;
++			if ((dev == bcmcfg_to_prmry_ndev(cfg)) && cfg->p2p) {
++				bssidx = wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++			}
++			wl_cfg80211_set_mgmt_vndr_ies(cfg, ndev_to_cfgdev(dev), bssidx,
++				VNDR_IE_PRBRSP_FLAG, (const u8 *)(buf + ie_offset), ie_len);
++			cfg80211_mgmt_tx_status(cfgdev, *cookie, buf, len, true, GFP_KERNEL);
++#if defined(P2P_IE_MISSING_FIX)
++			if (!cfg->p2p_prb_noti) {
++				cfg->p2p_prb_noti = true;
++				WL_DBG(("%s: TX 802_1X Probe Response first time.\n",
++					__FUNCTION__));
++			}
++#endif
++			goto exit;
++		} else if (ieee80211_is_disassoc(mgmt->frame_control) ||
++			ieee80211_is_deauth(mgmt->frame_control)) {
++			char mac_buf[MAX_NUM_OF_ASSOCIATED_DEV *
++				sizeof(struct ether_addr) + sizeof(uint)] = {0};
++			int num_associated = 0;
++			struct maclist *assoc_maclist = (struct maclist *)mac_buf;
++			if (!bcmp((const uint8 *)BSSID_BROADCAST,
++				(const struct ether_addr *)mgmt->da, ETHER_ADDR_LEN)) {
++				assoc_maclist->count = MAX_NUM_OF_ASSOCIATED_DEV;
++				err = wldev_ioctl(dev, WLC_GET_ASSOCLIST,
++					assoc_maclist, sizeof(mac_buf), false);
++				if (err < 0)
++					WL_ERR(("WLC_GET_ASSOCLIST error %d\n", err));
++				else
++					num_associated = assoc_maclist->count;
++			}
++			memcpy(scb_val.ea.octet, mgmt->da, ETH_ALEN);
++			scb_val.val = mgmt->u.disassoc.reason_code;
++			err = wldev_ioctl(dev, WLC_SCB_DEAUTHENTICATE_FOR_REASON, &scb_val,
++				sizeof(scb_val_t), true);
++			if (err < 0)
++				WL_ERR(("WLC_SCB_DEAUTHENTICATE_FOR_REASON error %d\n", err));
++			WL_ERR(("Disconnect STA : %s scb_val.val %d\n",
++				bcm_ether_ntoa((const struct ether_addr *)mgmt->da, eabuf),
++				scb_val.val));
++
++			if (num_associated > 0 && ETHER_ISBCAST(mgmt->da))
++				wl_delay(400);
++
++			cfg80211_mgmt_tx_status(cfgdev, *cookie, buf, len, true, GFP_KERNEL);
++			goto exit;
++
++		} else if (ieee80211_is_action(mgmt->frame_control)) {
++			/* Abort the dwell time of any previous off-channel
++			* action frame that may be still in effect.  Sending
++			* off-channel action frames relies on the driver's
++			* scan engine.  If a previous off-channel action frame
++			* tx is still in progress (including the dwell time),
++			* then this new action frame will not be sent out.
++			*/
++/* Do not abort scan for VSDB. Scan will be aborted in firmware if necessary.
++ * And previous off-channel action frame must be ended before new af tx.
++ */
++#ifndef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++			wl_notify_escan_complete(cfg, dev, true, true);
++#endif /* not WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++		}
++
++	} else {
++		WL_ERR(("Driver only allows MGMT packet type\n"));
++		goto exit;
++	}
++
++	af_params = (wl_af_params_t *) kzalloc(WL_WIFI_AF_PARAMS_SIZE, GFP_KERNEL);
++
++	if (af_params == NULL)
++	{
++		WL_ERR(("unable to allocate frame\n"));
++		return -ENOMEM;
++	}
++
++	action_frame = &af_params->action_frame;
++
++	/* Add the packet Id */
++	action_frame->packetId = *cookie;
++	WL_DBG(("action frame %d\n", action_frame->packetId));
++	/* Add BSSID */
++	memcpy(&action_frame->da, &mgmt->da[0], ETHER_ADDR_LEN);
++	memcpy(&af_params->BSSID, &mgmt->bssid[0], ETHER_ADDR_LEN);
++
++	/* Add the length exepted for 802.11 header  */
++	action_frame->len = len - DOT11_MGMT_HDR_LEN;
++	WL_DBG(("action_frame->len: %d\n", action_frame->len));
++
++	/* Add the channel */
++	af_params->channel =
++		ieee80211_frequency_to_channel(channel->center_freq);
++	/* Save listen_chan for searching common channel */
++	cfg->afx_hdl->peer_listen_chan = af_params->channel;
++	WL_DBG(("channel from upper layer %d\n", cfg->afx_hdl->peer_listen_chan));
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
++	af_params->dwell_time = params->wait;
++#else
++	af_params->dwell_time = wait;
++#endif
++
++	memcpy(action_frame->data, &buf[DOT11_MGMT_HDR_LEN], action_frame->len);
++
++	ack = wl_cfg80211_send_action_frame(wiphy, dev, cfgdev, af_params,
++		action_frame, action_frame->len, bssidx);
++	cfg80211_mgmt_tx_status(cfgdev, *cookie, buf, len, ack, GFP_KERNEL);
++
++	kfree(af_params);
++exit:
++	return err;
++}
++
++
++#if 0
++static void
++wl_cfg80211_mgmt_frame_register(struct wiphy *wiphy, bcm_struct_cfgdev *cfgdev,
++	u16 frame_type, bool reg)
++{
++
++	WL_DBG(("frame_type: %x, reg: %d\n", frame_type, reg));
++
++	if (frame_type != (IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_PROBE_REQ))
++		return;
++
++	return;
++}
++#else
++static void
++wl_cfg80211_mgmt_frame_register(struct wiphy *wiphy, struct wireless_dev *wdev,
++	struct mgmt_frame_regs *upd)
++{
++
++//	WL_DBG(("frame_type: %x, reg: %d\n", frame_type, reg));
++
++//	if (frame_type != (IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_PROBE_REQ))
++//		return;
++
++	return;
++}
++#endif
++
++
++static s32
++wl_cfg80211_change_bss(struct wiphy *wiphy,
++	struct net_device *dev,
++	struct bss_parameters *params)
++{
++	s32 err = 0;
++	s32 ap_isolate = 0;
++#ifdef PCIE_FULL_DONGLE
++	s32 ifidx = DHD_BAD_IF;
++#endif
++#if defined(PCIE_FULL_DONGLE)
++	dhd_pub_t *dhd;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd = (dhd_pub_t *)(cfg->pub);
++#if defined(WL_ENABLE_P2P_IF)
++	if (cfg->p2p_net == dev)
++		dev = bcmcfg_to_prmry_ndev(cfg);
++#endif
++#endif 
++
++	if (params->use_cts_prot >= 0) {
++	}
++
++	if (params->use_short_preamble >= 0) {
++	}
++
++	if (params->use_short_slot_time >= 0) {
++	}
++
++	if (params->basic_rates) {
++	}
++
++	if (params->ap_isolate >= 0) {
++		ap_isolate = params->ap_isolate;
++#ifdef PCIE_FULL_DONGLE
++		ifidx = dhd_net2idx(dhd->info, dev);
++
++		if (ifidx != DHD_BAD_IF) {
++			err = dhd_set_ap_isolate(dhd, ifidx, ap_isolate);
++		} else {
++			WL_ERR(("Failed to set ap_isolate\n"));
++		}
++#else
++		err = wldev_iovar_setint(dev, "ap_isolate", ap_isolate);
++		if (unlikely(err))
++		{
++			WL_ERR(("set ap_isolate Error (%d)\n", err));
++		}
++#endif /* PCIE_FULL_DONGLE */
++	}
++
++	if (params->ht_opmode >= 0) {
++	}
++
++
++	return err;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++static s32
++wl_cfg80211_set_channel(struct wiphy *wiphy, struct net_device *dev,
++	struct ieee80211_channel *chan,
++	struct cfg80211_chan_def chandef)
++#else
++static s32
++wl_cfg80211_set_channel(struct wiphy *wiphy, struct net_device *dev,
++	struct ieee80211_channel *chan,
++	enum nl80211_channel_type channel_type)
++#endif 
++{
++	s32 _chan;
++	chanspec_t chspec = 0;
++	chanspec_t fw_chspec = 0;
++	u32 bw = WL_CHANSPEC_BW_20;
++#ifdef WL11ULB
++	u32 ulb_bw = wl_cfg80211_get_ulb_bw(dev->ieee80211_ptr);
++#endif /* WL11ULB */
++
++	s32 err = BCME_OK;
++	s32 bw_cap = 0;
++	struct {
++		u32 band;
++		u32 bw_cap;
++	} param = {0, 0};
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++#ifdef CUSTOM_SET_CPUCORE
++	dhd_pub_t *dhd =  (dhd_pub_t *)(cfg->pub);
++#endif /* CUSTOM_SET_CPUCORE */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	enum nl80211_channel_type channel_type = NL80211_CHAN_HT20;
++#endif 
++
++	dev = ndev_to_wlc_ndev(dev, cfg);
++	_chan = ieee80211_frequency_to_channel(chan->center_freq);
++	WL_ERR(("netdev_ifidx(%d), chan_type(%d) target channel(%d) \n",
++		dev->ifindex, channel_type, _chan));
++
++#if defined(CUSTOM_PLATFORM_NV_TEGRA)
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	WL_ERR(("chan_width = %d\n", chandef.width));
++	switch (chandef.width) {
++		case NL80211_CHAN_WIDTH_40:
++			bw = WL_CHANSPEC_BW_40;
++			break;
++		case NL80211_CHAN_WIDTH_80:
++			bw = WL_CHANSPEC_BW_80;
++			break;
++		case NL80211_CHAN_WIDTH_80P80:
++			bw = WL_CHANSPEC_BW_8080;
++			break;
++		case NL80211_CHAN_WIDTH_160:
++			bw = WL_CHANSPEC_BW_160;
++			break;
++		default:
++			bw = WL_CHANSPEC_BW_20;
++			break;
++	}
++	goto set_channel;
++#endif 
++#endif 
++
++
++#ifdef WL11ULB
++	if (ulb_bw) {
++		WL_DBG(("[ULB] setting AP/GO BW to ulb_bw 0x%x \n", ulb_bw));
++		bw = wl_cfg80211_ulbbw_to_ulbchspec(ulb_bw);
++		goto set_channel;
++	}
++#endif /* WL11ULB */
++	if (chan->band == IEEE80211_BAND_5GHZ) {
++		param.band = WLC_BAND_5G;
++		err = wldev_iovar_getbuf(dev, "bw_cap", &param, sizeof(param),
++			cfg->ioctl_buf, WLC_IOCTL_SMLEN, &cfg->ioctl_buf_sync);
++		if (err) {
++			if (err != BCME_UNSUPPORTED) {
++				WL_ERR(("bw_cap failed, %d\n", err));
++				return err;
++			} else {
++				err = wldev_iovar_getint(dev, "mimo_bw_cap", &bw_cap);
++				if (err) {
++					WL_ERR(("error get mimo_bw_cap (%d)\n", err));
++				}
++				if (bw_cap != WLC_N_BW_20ALL)
++					bw = WL_CHANSPEC_BW_40;
++			}
++		} else {
++			if (WL_BW_CAP_80MHZ(cfg->ioctl_buf[0]))
++				bw = WL_CHANSPEC_BW_80;
++			else if (WL_BW_CAP_40MHZ(cfg->ioctl_buf[0]))
++				bw = WL_CHANSPEC_BW_40;
++			else
++				bw = WL_CHANSPEC_BW_20;
++
++		}
++
++	} else if (chan->band == IEEE80211_BAND_2GHZ)
++		bw = WL_CHANSPEC_BW_20;
++set_channel:
++	chspec = wf_channel2chspec(_chan, bw);
++	if (wf_chspec_valid(chspec)) {
++		fw_chspec = wl_chspec_host_to_driver(chspec);
++		if (fw_chspec != INVCHANSPEC) {
++			if ((err = wldev_iovar_setint(dev, "chanspec",
++				fw_chspec)) == BCME_BADCHAN) {
++				if (bw == WL_CHANSPEC_BW_80)
++					goto change_bw;
++				err = wldev_ioctl(dev, WLC_SET_CHANNEL,
++					&_chan, sizeof(_chan), true);
++				if (err < 0) {
++					WL_ERR(("WLC_SET_CHANNEL error %d"
++					"chip may not be supporting this channel\n", err));
++				}
++			} else if (err) {
++				WL_ERR(("failed to set chanspec error %d\n", err));
++			}
++		} else {
++			WL_ERR(("failed to convert host chanspec to fw chanspec\n"));
++			err = BCME_ERROR;
++		}
++	} else {
++change_bw:
++		if (bw == WL_CHANSPEC_BW_80)
++			bw = WL_CHANSPEC_BW_40;
++		else if (bw == WL_CHANSPEC_BW_40)
++			bw = WL_CHANSPEC_BW_20;
++		else
++			bw = 0;
++		if (bw)
++			goto set_channel;
++		WL_ERR(("Invalid chanspec 0x%x\n", chspec));
++		err = BCME_ERROR;
++	}
++#ifdef CUSTOM_SET_CPUCORE
++	if (dhd->op_mode == DHD_FLAG_HOSTAP_MODE) {
++		WL_DBG(("SoftAP mode do not need to set cpucore\n"));
++	} else if (chspec & WL_CHANSPEC_BW_80) {
++		/* SoftAp only mode do not need to set cpucore */
++		if ((dev->ieee80211_ptr->iftype == NL80211_IFTYPE_AP) &&
++			dev != bcmcfg_to_prmry_ndev(cfg)) {
++			/* Soft AP on virtual Iface (AP+STA case) */
++			dhd->chan_isvht80 |= DHD_FLAG_HOSTAP_MODE;
++			dhd_set_cpucore(dhd, TRUE);
++		} else if (is_p2p_group_iface(dev->ieee80211_ptr)) {
++			/* If P2P IF is vht80 */
++			dhd->chan_isvht80 |= DHD_FLAG_P2P_MODE;
++			dhd_set_cpucore(dhd, TRUE);
++		}
++	}
++#endif /* CUSTOM_SET_CPUCORE */
++	return err;
++}
++
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++struct net_device *
++wl_cfg80211_get_remain_on_channel_ndev(struct bcm_cfg80211 *cfg)
++{
++	struct net_info *_net_info, *next;
++	list_for_each_entry_safe(_net_info, next, &cfg->net_list, list) {
++		if (_net_info->ndev &&
++			test_bit(WL_STATUS_REMAINING_ON_CHANNEL, &_net_info->sme_state))
++			return _net_info->ndev;
++	}
++	return NULL;
++}
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++
++static s32
++wl_validate_opensecurity(struct net_device *dev, s32 bssidx, bool privacy)
++{
++	s32 err = BCME_OK;
++	u32 wpa_val;
++	s32 wsec = 0;
++
++	/* set auth */
++	err = wldev_iovar_setint_bsscfg(dev, "auth", 0, bssidx);
++	if (err < 0) {
++		WL_ERR(("auth error %d\n", err));
++		return BCME_ERROR;
++	}
++
++	if (privacy) {
++		/* If privacy bit is set in open mode, then WEP would be enabled */
++		wsec = WEP_ENABLED;
++		WL_DBG(("Setting wsec to %d for WEP \n", wsec));
++	}
++
++	/* set wsec */
++	err = wldev_iovar_setint_bsscfg(dev, "wsec", wsec, bssidx);
++	if (err < 0) {
++		WL_ERR(("wsec error %d\n", err));
++		return BCME_ERROR;
++	}
++
++	/* set upper-layer auth */
++	if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_ADHOC)
++		wpa_val = WPA_AUTH_NONE;
++	else
++		wpa_val = WPA_AUTH_DISABLED;
++	err = wldev_iovar_setint_bsscfg(dev, "wpa_auth", wpa_val, bssidx);
++	if (err < 0) {
++		WL_ERR(("wpa_auth error %d\n", err));
++		return BCME_ERROR;
++	}
++
++	return 0;
++}
++
++static s32
++wl_validate_wpa2ie(struct net_device *dev, bcm_tlv_t *wpa2ie, s32 bssidx)
++{
++	s32 len = 0;
++	s32 err = BCME_OK;
++	u16 auth = 0; /* d11 open authentication */
++	u32 wsec;
++	u32 pval = 0;
++	u32 gval = 0;
++	u32 wpa_auth = 0;
++	wpa_suite_mcast_t *mcast;
++	wpa_suite_ucast_t *ucast;
++	wpa_suite_auth_key_mgmt_t *mgmt;
++	wpa_pmkid_list_t *pmkid;
++	int cnt = 0;
++#ifdef MFP
++	int mfp = 0;
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++#endif /* MFP */
++
++	u16 suite_count;
++	u8 rsn_cap[2];
++	u32 wme_bss_disable;
++
++	if (wpa2ie == NULL)
++		goto exit;
++
++	WL_DBG(("Enter \n"));
++	len =  wpa2ie->len - WPA2_VERSION_LEN;
++	/* check the mcast cipher */
++	mcast = (wpa_suite_mcast_t *)&wpa2ie->data[WPA2_VERSION_LEN];
++	switch (mcast->type) {
++		case WPA_CIPHER_NONE:
++			gval = 0;
++			break;
++		case WPA_CIPHER_WEP_40:
++		case WPA_CIPHER_WEP_104:
++			gval = WEP_ENABLED;
++			break;
++		case WPA_CIPHER_TKIP:
++			gval = TKIP_ENABLED;
++			break;
++		case WPA_CIPHER_AES_CCM:
++			gval = AES_ENABLED;
++			break;
++		default:
++			WL_ERR(("No Security Info\n"));
++			break;
++	}
++	if ((len -= WPA_SUITE_LEN) <= 0)
++		return BCME_BADLEN;
++
++	/* check the unicast cipher */
++	ucast = (wpa_suite_ucast_t *)&mcast[1];
++	suite_count = ltoh16_ua(&ucast->count);
++	switch (ucast->list[0].type) {
++		case WPA_CIPHER_NONE:
++			pval = 0;
++			break;
++		case WPA_CIPHER_WEP_40:
++		case WPA_CIPHER_WEP_104:
++			pval = WEP_ENABLED;
++			break;
++		case WPA_CIPHER_TKIP:
++			pval = TKIP_ENABLED;
++			break;
++		case WPA_CIPHER_AES_CCM:
++			pval = AES_ENABLED;
++			break;
++		default:
++			WL_ERR(("No Security Info\n"));
++	}
++	if ((len -= (WPA_IE_SUITE_COUNT_LEN + (WPA_SUITE_LEN * suite_count))) <= 0)
++		return BCME_BADLEN;
++
++	/* FOR WPS , set SEC_OW_ENABLED */
++	wsec = (pval | gval | SES_OW_ENABLED);
++	/* check the AKM */
++	mgmt = (wpa_suite_auth_key_mgmt_t *)&ucast->list[suite_count];
++	suite_count = cnt = ltoh16_ua(&mgmt->count);
++	while (cnt--) {
++		switch (mgmt->list[cnt].type) {
++		case RSN_AKM_NONE:
++				wpa_auth |= WPA_AUTH_NONE;
++			break;
++		case RSN_AKM_UNSPECIFIED:
++				wpa_auth |= WPA2_AUTH_UNSPECIFIED;
++			break;
++		case RSN_AKM_PSK:
++				wpa_auth |= WPA2_AUTH_PSK;
++				break;
++#ifdef MFP
++			case RSN_AKM_MFP_PSK:
++				wpa_auth |= WPA2_AUTH_PSK_SHA256;
++				break;
++			case RSN_AKM_MFP_1X:
++				wpa_auth |= WPA2_AUTH_1X_SHA256;
++			break;
++#endif /* MFP */
++		default:
++			WL_ERR(("No Key Mgmt Info\n"));
++		}
++	}
++
++	if ((len -= (WPA_IE_SUITE_COUNT_LEN + (WPA_SUITE_LEN * suite_count))) >= RSN_CAP_LEN) {
++		rsn_cap[0] = *(u8 *)&mgmt->list[suite_count];
++		rsn_cap[1] = *((u8 *)&mgmt->list[suite_count] + 1);
++
++		if (rsn_cap[0] & (RSN_CAP_16_REPLAY_CNTRS << RSN_CAP_PTK_REPLAY_CNTR_SHIFT)) {
++			wme_bss_disable = 0;
++		} else {
++			wme_bss_disable = 1;
++		}
++
++#ifdef MFP
++	if (rsn_cap[0] & RSN_CAP_MFPR) {
++		WL_DBG(("MFP Required \n"));
++		mfp = WL_MFP_REQUIRED;
++		/* Our firmware has requirement that WPA2_AUTH_PSK/WPA2_AUTH_UNSPECIFIED
++		 * be set, if SHA256 OUI is to be included in the rsn ie.
++		 */
++		if (wpa_auth & WPA2_AUTH_PSK_SHA256) {
++			wpa_auth |= WPA2_AUTH_PSK;
++		} else if (wpa_auth & WPA2_AUTH_1X_SHA256) {
++			wpa_auth |= WPA2_AUTH_UNSPECIFIED;
++		}
++	} else if (rsn_cap[0] & RSN_CAP_MFPC) {
++		WL_DBG(("MFP Capable \n"));
++		mfp = WL_MFP_CAPABLE;
++	}
++#endif /* MFP */
++
++		/* set wme_bss_disable to sync RSN Capabilities */
++		err = wldev_iovar_setint_bsscfg(dev, "wme_bss_disable", wme_bss_disable, bssidx);
++		if (err < 0) {
++			WL_ERR(("wme_bss_disable error %d\n", err));
++			return BCME_ERROR;
++		}
++	} else {
++		WL_DBG(("There is no RSN Capabilities. remained len %d\n", len));
++	}
++
++	len -= RSN_CAP_LEN;
++	if (len >= WPA2_PMKID_COUNT_LEN) {
++		pmkid = (wpa_pmkid_list_t *)((u8 *)&mgmt->list[suite_count] + RSN_CAP_LEN);
++		cnt = ltoh16_ua(&pmkid->count);
++		if (cnt != 0) {
++			WL_ERR(("AP has non-zero PMKID count. Wrong!\n"));
++			return BCME_ERROR;
++		}
++		/* since PMKID cnt is known to be 0 for AP, */
++		/* so don't bother to send down this info to firmware */
++	}
++
++#ifdef MFP
++	len -= WPA2_PMKID_COUNT_LEN;
++	if (len >= WPA_SUITE_LEN) {
++		err = wldev_iovar_setbuf_bsscfg(dev, "bip",
++		(void *)((u8 *)&mgmt->list[suite_count] + RSN_CAP_LEN + WPA2_PMKID_COUNT_LEN),
++		WPA_SUITE_LEN,
++		cfg->ioctl_buf, WLC_IOCTL_SMLEN, bssidx, &cfg->ioctl_buf_sync);
++		if (err < 0) {
++			WL_ERR(("bip set error %d\n", err));
++			return BCME_ERROR;
++		}
++	}
++#endif
++
++	/* set auth */
++	err = wldev_iovar_setint_bsscfg(dev, "auth", auth, bssidx);
++	if (err < 0) {
++		WL_ERR(("auth error %d\n", err));
++		return BCME_ERROR;
++	}
++
++	/* set wsec */
++	err = wldev_iovar_setint_bsscfg(dev, "wsec", wsec, bssidx);
++	if (err < 0) {
++		WL_ERR(("wsec error %d\n", err));
++		return BCME_ERROR;
++	}
++
++#ifdef MFP
++	if (mfp) {
++		/* This needs to go after wsec otherwise the wsec command will
++		 * overwrite the values set by MFP
++		 */
++		if ((err = wldev_iovar_setint_bsscfg(dev, "mfp", mfp, bssidx)) < 0) {
++			WL_ERR(("MFP Setting failed. ret = %d \n", err));
++			return err;
++		}
++	}
++#endif /* MFP */
++
++	/* set upper-layer auth */
++	err = wldev_iovar_setint_bsscfg(dev, "wpa_auth", wpa_auth, bssidx);
++	if (err < 0) {
++		WL_ERR(("wpa_auth error %d\n", err));
++		return BCME_ERROR;
++	}
++exit:
++	return 0;
++}
++
++static s32
++wl_validate_wpaie(struct net_device *dev, wpa_ie_fixed_t *wpaie, s32 bssidx)
++{
++	wpa_suite_mcast_t *mcast;
++	wpa_suite_ucast_t *ucast;
++	wpa_suite_auth_key_mgmt_t *mgmt;
++	u16 auth = 0; /* d11 open authentication */
++	u16 count;
++	s32 err = BCME_OK;
++	s32 len = 0;
++	u32 i;
++	u32 wsec;
++	u32 pval = 0;
++	u32 gval = 0;
++	u32 wpa_auth = 0;
++	u32 tmp = 0;
++
++	if (wpaie == NULL)
++		goto exit;
++	WL_DBG(("Enter \n"));
++	len = wpaie->length;    /* value length */
++	len -= WPA_IE_TAG_FIXED_LEN;
++	/* check for multicast cipher suite */
++	if (len < WPA_SUITE_LEN) {
++		WL_INFORM(("no multicast cipher suite\n"));
++		goto exit;
++	}
++
++	/* pick up multicast cipher */
++	mcast = (wpa_suite_mcast_t *)&wpaie[1];
++	len -= WPA_SUITE_LEN;
++	if (!bcmp(mcast->oui, WPA_OUI, WPA_OUI_LEN)) {
++		if (IS_WPA_CIPHER(mcast->type)) {
++			tmp = 0;
++			switch (mcast->type) {
++				case WPA_CIPHER_NONE:
++					tmp = 0;
++					break;
++				case WPA_CIPHER_WEP_40:
++				case WPA_CIPHER_WEP_104:
++					tmp = WEP_ENABLED;
++					break;
++				case WPA_CIPHER_TKIP:
++					tmp = TKIP_ENABLED;
++					break;
++				case WPA_CIPHER_AES_CCM:
++					tmp = AES_ENABLED;
++					break;
++				default:
++					WL_ERR(("No Security Info\n"));
++			}
++			gval |= tmp;
++		}
++	}
++	/* Check for unicast suite(s) */
++	if (len < WPA_IE_SUITE_COUNT_LEN) {
++		WL_INFORM(("no unicast suite\n"));
++		goto exit;
++	}
++	/* walk thru unicast cipher list and pick up what we recognize */
++	ucast = (wpa_suite_ucast_t *)&mcast[1];
++	count = ltoh16_ua(&ucast->count);
++	len -= WPA_IE_SUITE_COUNT_LEN;
++	for (i = 0; i < count && len >= WPA_SUITE_LEN;
++		i++, len -= WPA_SUITE_LEN) {
++		if (!bcmp(ucast->list[i].oui, WPA_OUI, WPA_OUI_LEN)) {
++			if (IS_WPA_CIPHER(ucast->list[i].type)) {
++				tmp = 0;
++				switch (ucast->list[i].type) {
++					case WPA_CIPHER_NONE:
++						tmp = 0;
++						break;
++					case WPA_CIPHER_WEP_40:
++					case WPA_CIPHER_WEP_104:
++						tmp = WEP_ENABLED;
++						break;
++					case WPA_CIPHER_TKIP:
++						tmp = TKIP_ENABLED;
++						break;
++					case WPA_CIPHER_AES_CCM:
++						tmp = AES_ENABLED;
++						break;
++					default:
++						WL_ERR(("No Security Info\n"));
++				}
++				pval |= tmp;
++			}
++		}
++	}
++	len -= (count - i) * WPA_SUITE_LEN;
++	/* Check for auth key management suite(s) */
++	if (len < WPA_IE_SUITE_COUNT_LEN) {
++		WL_INFORM((" no auth key mgmt suite\n"));
++		goto exit;
++	}
++	/* walk thru auth management suite list and pick up what we recognize */
++	mgmt = (wpa_suite_auth_key_mgmt_t *)&ucast->list[count];
++	count = ltoh16_ua(&mgmt->count);
++	len -= WPA_IE_SUITE_COUNT_LEN;
++	for (i = 0; i < count && len >= WPA_SUITE_LEN;
++		i++, len -= WPA_SUITE_LEN) {
++		if (!bcmp(mgmt->list[i].oui, WPA_OUI, WPA_OUI_LEN)) {
++			if (IS_WPA_AKM(mgmt->list[i].type)) {
++				tmp = 0;
++				switch (mgmt->list[i].type) {
++					case RSN_AKM_NONE:
++						tmp = WPA_AUTH_NONE;
++						break;
++					case RSN_AKM_UNSPECIFIED:
++						tmp = WPA_AUTH_UNSPECIFIED;
++						break;
++					case RSN_AKM_PSK:
++						tmp = WPA_AUTH_PSK;
++						break;
++					default:
++						WL_ERR(("No Key Mgmt Info\n"));
++				}
++				wpa_auth |= tmp;
++			}
++		}
++
++	}
++	/* FOR WPS , set SEC_OW_ENABLED */
++	wsec = (pval | gval | SES_OW_ENABLED);
++	/* set auth */
++	err = wldev_iovar_setint_bsscfg(dev, "auth", auth, bssidx);
++	if (err < 0) {
++		WL_ERR(("auth error %d\n", err));
++		return BCME_ERROR;
++	}
++	/* set wsec */
++	err = wldev_iovar_setint_bsscfg(dev, "wsec", wsec, bssidx);
++	if (err < 0) {
++		WL_ERR(("wsec error %d\n", err));
++		return BCME_ERROR;
++	}
++	/* set upper-layer auth */
++	err = wldev_iovar_setint_bsscfg(dev, "wpa_auth", wpa_auth, bssidx);
++	if (err < 0) {
++		WL_ERR(("wpa_auth error %d\n", err));
++		return BCME_ERROR;
++	}
++exit:
++	return 0;
++}
++
++
++static s32
++wl_cfg80211_bcn_validate_sec(
++	struct net_device *dev,
++	struct parsed_ies *ies,
++	u32 dev_role,
++	s32 bssidx,
++	bool privacy)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	wl_cfgbss_t *bss = wl_get_cfgbss_by_wdev(cfg, dev->ieee80211_ptr);
++
++	if (!bss) {
++		WL_ERR(("cfgbss is NULL \n"));
++		return BCME_ERROR;
++	}
++
++	if (dev_role == NL80211_IFTYPE_P2P_GO && (ies->wpa2_ie)) {
++		/* For P2P GO, the sec type is WPA2-PSK */
++		WL_DBG(("P2P GO: validating wpa2_ie"));
++		if (wl_validate_wpa2ie(dev, ies->wpa2_ie, bssidx)  < 0)
++			return BCME_ERROR;
++
++	} else if (dev_role == NL80211_IFTYPE_AP) {
++
++		WL_DBG(("SoftAP: validating security"));
++		/* If wpa2_ie or wpa_ie is present validate it */
++
++		if ((ies->wpa2_ie || ies->wpa_ie) &&
++			((wl_validate_wpa2ie(dev, ies->wpa2_ie, bssidx)  < 0 ||
++			wl_validate_wpaie(dev, ies->wpa_ie, bssidx) < 0))) {
++			bss->security_mode = false;
++			return BCME_ERROR;
++		}
++
++		bss->security_mode = true;
++		if (bss->rsn_ie) {
++			kfree(bss->rsn_ie);
++			bss->rsn_ie = NULL;
++		}
++		if (bss->wpa_ie) {
++			kfree(bss->wpa_ie);
++			bss->wpa_ie = NULL;
++		}
++		if (bss->wps_ie) {
++			kfree(bss->wps_ie);
++			bss->wps_ie = NULL;
++		}
++		if (ies->wpa_ie != NULL) {
++			/* WPAIE */
++			bss->rsn_ie = NULL;
++			bss->wpa_ie = kmemdup(ies->wpa_ie,
++				ies->wpa_ie->length + WPA_RSN_IE_TAG_FIXED_LEN,
++				GFP_KERNEL);
++		} else if (ies->wpa2_ie != NULL) {
++			/* RSNIE */
++			bss->wpa_ie = NULL;
++			bss->rsn_ie = kmemdup(ies->wpa2_ie,
++				ies->wpa2_ie->len + WPA_RSN_IE_TAG_FIXED_LEN,
++				GFP_KERNEL);
++		}
++		if (!ies->wpa2_ie && !ies->wpa_ie) {
++			wl_validate_opensecurity(dev, bssidx, privacy);
++			bss->security_mode = false;
++		}
++
++		if (ies->wps_ie) {
++			bss->wps_ie = kmemdup(ies->wps_ie, ies->wps_ie_len, GFP_KERNEL);
++		}
++	}
++
++	return 0;
++
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
++static s32 wl_cfg80211_bcn_set_params(
++	struct cfg80211_ap_settings *info,
++	struct net_device *dev,
++	u32 dev_role, s32 bssidx)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	s32 err = BCME_OK;
++
++	WL_DBG(("interval (%d) \ndtim_period (%d) \n",
++		info->beacon_interval, info->dtim_period));
++
++	if (info->beacon_interval) {
++		if ((err = wldev_ioctl(dev, WLC_SET_BCNPRD,
++			&info->beacon_interval, sizeof(s32), true)) < 0) {
++			WL_ERR(("Beacon Interval Set Error, %d\n", err));
++			return err;
++		}
++	}
++
++	if (info->dtim_period) {
++		if ((err = wldev_ioctl(dev, WLC_SET_DTIMPRD,
++			&info->dtim_period, sizeof(s32), true)) < 0) {
++			WL_ERR(("DTIM Interval Set Error, %d\n", err));
++			return err;
++		}
++	}
++
++	if ((info->ssid) && (info->ssid_len > 0) &&
++		(info->ssid_len <= 32)) {
++		WL_DBG(("SSID (%s) len:%zd \n", info->ssid, info->ssid_len));
++		if (dev_role == NL80211_IFTYPE_AP) {
++			/* Store the hostapd SSID */
++			memset(cfg->hostapd_ssid.SSID, 0x00, 32);
++			memcpy(cfg->hostapd_ssid.SSID, info->ssid, info->ssid_len);
++			cfg->hostapd_ssid.SSID_len = info->ssid_len;
++		} else {
++				/* P2P GO */
++			memset(cfg->p2p->ssid.SSID, 0x00, 32);
++			memcpy(cfg->p2p->ssid.SSID, info->ssid, info->ssid_len);
++			cfg->p2p->ssid.SSID_len = info->ssid_len;
++		}
++	}
++
++	if (info->hidden_ssid) {
++		if ((err = wldev_iovar_setint(dev, "closednet", 1)) < 0)
++			WL_ERR(("failed to set hidden : %d\n", err));
++		WL_DBG(("hidden_ssid_enum_val: %d \n", info->hidden_ssid));
++	}
++
++	return err;
++}
++#endif 
++
++static s32
++wl_cfg80211_parse_ies(u8 *ptr, u32 len, struct parsed_ies *ies)
++{
++	s32 err = BCME_OK;
++
++	memset(ies, 0, sizeof(struct parsed_ies));
++
++	/* find the WPSIE */
++	if ((ies->wps_ie = wl_cfgp2p_find_wpsie(ptr, len)) != NULL) {
++		WL_DBG(("WPSIE in beacon \n"));
++		ies->wps_ie_len = ies->wps_ie->length + WPA_RSN_IE_TAG_FIXED_LEN;
++	} else {
++		WL_ERR(("No WPSIE in beacon \n"));
++	}
++
++	/* find the RSN_IE */
++	if ((ies->wpa2_ie = bcm_parse_tlvs(ptr, len,
++		DOT11_MNG_RSN_ID)) != NULL) {
++		WL_DBG((" WPA2 IE found\n"));
++		ies->wpa2_ie_len = ies->wpa2_ie->len;
++	}
++
++	/* find the WPA_IE */
++	if ((ies->wpa_ie = wl_cfgp2p_find_wpaie(ptr, len)) != NULL) {
++		WL_DBG((" WPA found\n"));
++		ies->wpa_ie_len = ies->wpa_ie->length;
++	}
++
++	return err;
++
++}
++
++static s32
++wl_cfg80211_bcn_bringup_ap(
++	struct net_device *dev,
++	struct parsed_ies *ies,
++	u32 dev_role, s32 bssidx)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	struct wl_join_params join_params;
++	bool is_bssup = false;
++	s32 infra = 1;
++	s32 join_params_size = 0;
++	s32 ap = 1;
++	s32 pm;
++	s32 wsec;
++	s32 err = BCME_OK;
++	s32 is_rsdb_supported = BCME_ERROR;
++
++	is_rsdb_supported = DHD_OPMODE_SUPPORTED(cfg->pub, DHD_FLAG_RSDB_MODE);
++	if (is_rsdb_supported < 0)
++		return (-ENODEV);
++
++	WL_DBG(("Enter dev_role:%d bssidx:%d\n", dev_role, bssidx));
++
++	/* Common code for SoftAP and P2P GO */
++	wldev_iovar_setint(dev, "mpc", 0);
++
++	if (dev_role == NL80211_IFTYPE_P2P_GO) {
++		is_bssup = wl_cfgp2p_bss_isup(dev, bssidx);
++		if (!is_bssup && (ies->wpa2_ie != NULL)) {
++
++			err = wldev_ioctl(dev, WLC_SET_INFRA, &infra, sizeof(s32), true);
++			if (err < 0) {
++				WL_ERR(("SET INFRA error %d\n", err));
++				goto exit;
++			}
++
++			err = wldev_iovar_setbuf_bsscfg(dev, "ssid", &cfg->p2p->ssid,
++				sizeof(cfg->p2p->ssid), cfg->ioctl_buf, WLC_IOCTL_MAXLEN,
++				bssidx, &cfg->ioctl_buf_sync);
++			if (err < 0) {
++				WL_ERR(("GO SSID setting error %d\n", err));
++				goto exit;
++			}
++
++			/* Do abort scan before creating GO */
++			wl_cfg80211_scan_abort(cfg);
++
++			if ((err = wl_cfgp2p_bss(cfg, dev, bssidx, 1)) < 0) {
++				WL_ERR(("GO Bring up error %d\n", err));
++				goto exit;
++			}
++		} else
++			WL_DBG(("Bss is already up\n"));
++	} else if ((dev_role == NL80211_IFTYPE_AP) &&
++		(wl_get_drv_status(cfg, AP_CREATING, dev))) {
++		/* Device role SoftAP */
++
++		WL_DBG(("Creating AP bssidx:%d dev_role:%d\n", bssidx, dev_role));
++
++		if (bssidx == 0) {
++				/* AP on primary Interface */
++			if (is_rsdb_supported) {
++				if ((err = wl_cfg80211_add_del_bss(cfg, dev, bssidx,
++					NL80211_IFTYPE_AP, 0, NULL)) < 0) {
++					WL_ERR(("wl add_del_bss returned error:%d\n", err));
++					goto exit;
++				}
++			} else if (is_rsdb_supported == 0) {
++			/* AP mode switch not supported. Try setting up AP explicitly */
++				err = wldev_ioctl(dev, WLC_DOWN, &ap, sizeof(s32), true);
++				if (err < 0) {
++					WL_ERR(("WLC_DOWN error %d\n", err));
++					goto exit;
++				}
++				err = wldev_iovar_setint(dev, "apsta", 0);
++				if (err < 0) {
++					WL_ERR(("wl apsta 0 error %d\n", err));
++					goto exit;
++				}
++
++				if ((err = wldev_ioctl(dev,
++					WLC_SET_AP, &ap, sizeof(s32), true)) < 0) {
++					WL_ERR(("setting AP mode failed %d \n", err));
++					goto exit;
++				}
++
++			}
++
++			pm = 0;
++			if ((err = wldev_ioctl(dev, WLC_SET_PM, &pm, sizeof(pm), true)) != 0) {
++				WL_ERR(("wl PM 0 returned error:%d\n", err));
++				goto exit;
++			}
++
++			err = wldev_ioctl(dev, WLC_SET_INFRA, &infra, sizeof(s32), true);
++			if (err < 0) {
++				WL_ERR(("SET INFRA error %d\n", err));
++				goto exit;
++			}
++		} else if (cfg->cfgdev_bssidx && (bssidx == cfg->cfgdev_bssidx)) {
++
++			WL_DBG(("Bringup SoftAP on virtual Interface bssidx:%d \n", bssidx));
++
++			if ((err = wl_cfg80211_add_del_bss(cfg, dev,
++				bssidx, NL80211_IFTYPE_AP, 0, NULL)) < 0) {
++				WL_ERR(("wl bss ap returned error:%d\n", err));
++				goto exit;
++			}
++
++		}
++
++		err = wldev_ioctl(dev, WLC_UP, &ap, sizeof(s32), true);
++		if (unlikely(err)) {
++			WL_ERR(("WLC_UP error (%d)\n", err));
++			goto exit;
++		}
++
++		err = wldev_iovar_getint(dev, "wsec", (s32 *)&wsec);
++		if (unlikely(err)) {
++			WL_ERR(("Could not get wsec %d\n", err));
++			goto exit;
++		}
++		if ((wsec == WEP_ENABLED) && cfg->wep_key.len) {
++			WL_DBG(("Applying buffered WEP KEY \n"));
++			err = wldev_iovar_setbuf_bsscfg(dev, "wsec_key", &cfg->wep_key,
++				sizeof(struct wl_wsec_key), cfg->ioctl_buf,
++				WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++			/* clear the key after use */
++			memset(&cfg->wep_key, 0, sizeof(struct wl_wsec_key));
++			if (unlikely(err)) {
++				WL_ERR(("WLC_SET_KEY error (%d)\n", err));
++				goto exit;
++			}
++		}
++
++		memset(&join_params, 0, sizeof(join_params));
++		/* join parameters starts with ssid */
++		join_params_size = sizeof(join_params.ssid);
++		memcpy(join_params.ssid.SSID, cfg->hostapd_ssid.SSID,
++			cfg->hostapd_ssid.SSID_len);
++		join_params.ssid.SSID_len = htod32(cfg->hostapd_ssid.SSID_len);
++
++		/* create softap */
++		if ((err = wldev_ioctl(dev, WLC_SET_SSID, &join_params,
++			join_params_size, true)) == 0) {
++			WL_DBG(("SoftAP set SSID (%s) success\n", join_params.ssid.SSID));
++			wl_clr_drv_status(cfg, AP_CREATING, dev);
++			wl_set_drv_status(cfg, AP_CREATED, dev);
++		} else {
++			WL_ERR(("SoftAP/GO set ssid failed! \n"));
++			goto exit;
++		}
++
++		if (bssidx != 0) {
++			/* AP on Virtual Interface */
++			if ((err = wl_cfgp2p_bss(cfg, dev, bssidx, 1)) < 0) {
++				WL_ERR(("Virtual AP Bring up error %d\n", err));
++				goto exit;
++			}
++		}
++	}
++
++	/* Mark AP/GO iface status to connected */
++	wl_set_drv_status(cfg, CONNECTED, dev);
++
++exit:
++	if (cfg->wep_key.len)
++		memset(&cfg->wep_key, 0, sizeof(struct wl_wsec_key));
++	return err;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
++s32
++wl_cfg80211_parse_ap_ies(
++	struct net_device *dev,
++	struct cfg80211_beacon_data *info,
++	struct parsed_ies *ies)
++{
++	struct parsed_ies prb_ies;
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++	u8 *vndr = NULL;
++	u32 vndr_ie_len = 0;
++	s32 err = BCME_OK;
++
++	/* Parse Beacon IEs */
++	if (wl_cfg80211_parse_ies((u8 *)info->tail,
++		info->tail_len, ies) < 0) {
++		WL_ERR(("Beacon get IEs failed \n"));
++		err = -EINVAL;
++		goto fail;
++	}
++
++	vndr = (u8 *)info->proberesp_ies;
++	vndr_ie_len = info->proberesp_ies_len;
++
++	if (dhd->op_mode & DHD_FLAG_HOSTAP_MODE) {
++		/* SoftAP mode */
++		struct ieee80211_mgmt *mgmt;
++		mgmt = (struct ieee80211_mgmt *)info->probe_resp;
++		if (mgmt != NULL) {
++			vndr = (u8 *)&mgmt->u.probe_resp.variable;
++			vndr_ie_len = info->probe_resp_len -
++				offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
++		}
++	}
++
++	/* Parse Probe Response IEs */
++	if (wl_cfg80211_parse_ies(vndr, vndr_ie_len, &prb_ies) < 0) {
++		WL_ERR(("PROBE RESP get IEs failed \n"));
++		err = -EINVAL;
++	}
++
++fail:
++
++	return err;
++}
++
++s32
++wl_cfg80211_set_ies(
++	struct net_device *dev,
++	struct cfg80211_beacon_data *info,
++	s32 bssidx)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++	u8 *vndr = NULL;
++	u32 vndr_ie_len = 0;
++	s32 err = BCME_OK;
++
++	/* Set Beacon IEs to FW */
++	if ((err = wl_cfg80211_set_mgmt_vndr_ies(cfg, ndev_to_cfgdev(dev), bssidx,
++		VNDR_IE_BEACON_FLAG, (const u8 *)info->tail,
++		info->tail_len)) < 0) {
++		WL_ERR(("Set Beacon IE Failed \n"));
++	} else {
++		WL_DBG(("Applied Vndr IEs for Beacon \n"));
++	}
++
++	vndr = (u8 *)info->proberesp_ies;
++	vndr_ie_len = info->proberesp_ies_len;
++
++	if (dhd->op_mode & DHD_FLAG_HOSTAP_MODE) {
++		/* SoftAP mode */
++		struct ieee80211_mgmt *mgmt;
++		mgmt = (struct ieee80211_mgmt *)info->probe_resp;
++		if (mgmt != NULL) {
++			vndr = (u8 *)&mgmt->u.probe_resp.variable;
++			vndr_ie_len = info->probe_resp_len -
++				offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
++		}
++	}
++
++	/* Set Probe Response IEs to FW */
++	if ((err = wl_cfg80211_set_mgmt_vndr_ies(cfg, ndev_to_cfgdev(dev), bssidx,
++		VNDR_IE_PRBRSP_FLAG, vndr, vndr_ie_len)) < 0) {
++		WL_ERR(("Set Probe Resp IE Failed \n"));
++	} else {
++		WL_DBG(("Applied Vndr IEs for Probe Resp \n"));
++	}
++
++	return err;
++}
++#endif 
++
++static s32 wl_cfg80211_hostapd_sec(
++	struct net_device *dev,
++	struct parsed_ies *ies,
++	s32 bssidx)
++{
++	bool update_bss = 0;
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	wl_cfgbss_t *bss = wl_get_cfgbss_by_wdev(cfg, dev->ieee80211_ptr);
++
++	if (!bss) {
++		WL_ERR(("cfgbss is NULL \n"));
++		return -EINVAL;
++	}
++
++	if (ies->wps_ie) {
++		if (bss->wps_ie &&
++			memcmp(bss->wps_ie, ies->wps_ie, ies->wps_ie_len)) {
++			WL_DBG((" WPS IE is changed\n"));
++			kfree(bss->wps_ie);
++			bss->wps_ie = kmemdup(ies->wps_ie, ies->wps_ie_len, GFP_KERNEL);
++		} else if (bss->wps_ie == NULL) {
++			WL_DBG((" WPS IE is added\n"));
++			bss->wps_ie = kmemdup(ies->wps_ie, ies->wps_ie_len, GFP_KERNEL);
++		}
++
++		if ((ies->wpa_ie != NULL || ies->wpa2_ie != NULL)) {
++			if (!bss->security_mode) {
++				/* change from open mode to security mode */
++				update_bss = true;
++				if (ies->wpa_ie != NULL) {
++					bss->wpa_ie = kmemdup(ies->wpa_ie,
++					ies->wpa_ie->length + WPA_RSN_IE_TAG_FIXED_LEN,
++					GFP_KERNEL);
++				} else {
++					bss->rsn_ie = kmemdup(ies->wpa2_ie,
++					ies->wpa2_ie->len + WPA_RSN_IE_TAG_FIXED_LEN,
++					GFP_KERNEL);
++				}
++			} else if (bss->wpa_ie) {
++				/* change from WPA2 mode to WPA mode */
++				if (ies->wpa_ie != NULL) {
++					update_bss = true;
++					kfree(bss->rsn_ie);
++					bss->rsn_ie = NULL;
++					bss->wpa_ie = kmemdup(ies->wpa_ie,
++					ies->wpa_ie->length + WPA_RSN_IE_TAG_FIXED_LEN,
++					GFP_KERNEL);
++				} else if (memcmp(bss->rsn_ie,
++					ies->wpa2_ie, ies->wpa2_ie->len
++					+ WPA_RSN_IE_TAG_FIXED_LEN)) {
++					update_bss = true;
++					kfree(bss->rsn_ie);
++					bss->rsn_ie = kmemdup(ies->wpa2_ie,
++					ies->wpa2_ie->len + WPA_RSN_IE_TAG_FIXED_LEN,
++					GFP_KERNEL);
++					bss->wpa_ie = NULL;
++				}
++			}
++			if (update_bss) {
++				bss->security_mode = true;
++				wl_cfgp2p_bss(cfg, dev, bssidx, 0);
++				if (wl_validate_wpa2ie(dev, ies->wpa2_ie, bssidx)  < 0 ||
++					wl_validate_wpaie(dev, ies->wpa_ie, bssidx) < 0) {
++					return BCME_ERROR;
++				}
++				wl_cfgp2p_bss(cfg, dev, bssidx, 1);
++			}
++		}
++	} else {
++		WL_ERR(("No WPSIE in beacon \n"));
++	}
++	return 0;
++}
++
++#if defined(WL_SUPPORT_BACKPORTED_KPATCHES) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, \
++	2, 0))
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++static s32
++wl_cfg80211_del_station(
++		struct wiphy *wiphy, struct net_device *ndev,
++		struct station_del_parameters *params)
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++static s32
++wl_cfg80211_del_station(
++	struct wiphy *wiphy,
++	struct net_device *ndev,
++	const u8* mac_addr)
++#else
++static s32
++wl_cfg80211_del_station(
++	struct wiphy *wiphy,
++	struct net_device *ndev,
++	u8* mac_addr)
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) */
++{
++	struct net_device *dev;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	scb_val_t scb_val;
++	s8 eabuf[ETHER_ADDR_STR_LEN];
++	int err;
++	char mac_buf[MAX_NUM_OF_ASSOCIATED_DEV *
++		sizeof(struct ether_addr) + sizeof(uint)] = {0};
++	struct maclist *assoc_maclist = (struct maclist *)mac_buf;
++	int num_associated = 0;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++	const u8 *mac_addr = params->mac;
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) */
++
++	WL_DBG(("Entry\n"));
++	if (mac_addr == NULL) {
++		WL_DBG(("mac_addr is NULL ignore it\n"));
++		return 0;
++	}
++
++	dev = ndev_to_wlc_ndev(ndev, cfg);
++
++	if (p2p_is_on(cfg)) {
++		/* Suspend P2P discovery search-listen to prevent it from changing the
++		 * channel.
++		 */
++		if ((wl_cfgp2p_discover_enable_search(cfg, false)) < 0) {
++			WL_ERR(("Can not disable discovery mode\n"));
++			return -EFAULT;
++		}
++	}
++
++	assoc_maclist->count = MAX_NUM_OF_ASSOCIATED_DEV;
++	err = wldev_ioctl(ndev, WLC_GET_ASSOCLIST,
++		assoc_maclist, sizeof(mac_buf), false);
++	if (err < 0)
++		WL_ERR(("WLC_GET_ASSOCLIST error %d\n", err));
++	else
++		num_associated = assoc_maclist->count;
++
++	memcpy(scb_val.ea.octet, mac_addr, ETHER_ADDR_LEN);
++	scb_val.val = DOT11_RC_DEAUTH_LEAVING;
++	err = wldev_ioctl(dev, WLC_SCB_DEAUTHENTICATE_FOR_REASON, &scb_val,
++		sizeof(scb_val_t), true);
++	if (err < 0)
++		WL_ERR(("WLC_SCB_DEAUTHENTICATE_FOR_REASON err %d\n", err));
++	WL_ERR(("Disconnect STA : %s scb_val.val %d\n",
++		bcm_ether_ntoa((const struct ether_addr *)mac_addr, eabuf),
++		scb_val.val));
++
++	if (num_associated > 0 && ETHER_ISBCAST(mac_addr))
++		wl_delay(400);
++
++	return 0;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++static s32
++wl_cfg80211_change_station(
++	struct wiphy *wiphy,
++	struct net_device *dev,
++	const u8 *mac,
++	struct station_parameters *params)
++#else
++static s32
++wl_cfg80211_change_station(
++	struct wiphy *wiphy,
++	struct net_device *dev,
++	u8 *mac,
++	struct station_parameters *params)
++#endif
++{
++	int err;
++#ifdef DHD_LOSSLESS_ROAMING
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++#endif
++
++	WL_DBG(("SCB_AUTHORIZE mac_addr:"MACDBG" sta_flags_mask:0x%x "
++				"sta_flags_set:0x%x iface:%s \n", MAC2STRDBG(mac),
++				params->sta_flags_mask, params->sta_flags_set, dev->name));
++
++	/* Processing only authorize/de-authorize flag for now */
++	if (!(params->sta_flags_mask & BIT(NL80211_STA_FLAG_AUTHORIZED))) {
++		WL_ERR(("WLC_SCB_AUTHORIZE sta_flags_mask not set \n"));
++		return -ENOTSUPP;
++	}
++
++	if (!(params->sta_flags_set & BIT(NL80211_STA_FLAG_AUTHORIZED))) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++		err = wldev_ioctl(dev, WLC_SCB_DEAUTHORIZE, (u8 *)mac, ETH_ALEN, true);
++#else
++		err = wldev_ioctl(dev, WLC_SCB_DEAUTHORIZE, mac, ETH_ALEN, true);
++#endif
++		if (err)
++			WL_ERR(("WLC_SCB_DEAUTHORIZE error (%d)\n", err));
++		return err;
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++	err = wldev_ioctl(dev, WLC_SCB_AUTHORIZE, (u8 *)mac, ETH_ALEN, true);
++#else
++	err = wldev_ioctl(dev, WLC_SCB_AUTHORIZE, mac, ETH_ALEN, true);
++#endif
++	if (err)
++		WL_ERR(("WLC_SCB_AUTHORIZE error (%d)\n", err));
++#ifdef DHD_LOSSLESS_ROAMING
++	wl_del_roam_timeout(cfg);
++#endif
++	return err;
++}
++#endif /* WL_SUPPORT_BACKPORTED_KPATCHES || KERNEL_VER >= KERNEL_VERSION(3, 2, 0)) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
++static s32
++wl_cfg80211_start_ap(
++	struct wiphy *wiphy,
++	struct net_device *dev,
++	struct cfg80211_ap_settings *info)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 err = BCME_OK;
++	struct parsed_ies ies;
++	s32 bssidx = 0;
++	u32 dev_role = 0;
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++	WL_DBG(("Enter \n"));
++	if ((dev == bcmcfg_to_prmry_ndev(cfg)) ||
++		(dev == ((struct net_device *)cfgdev_to_ndev(cfg->bss_cfgdev)))) {
++		WL_DBG(("Start AP req on iface: %s \n", dev->name));
++		dev_role = NL80211_IFTYPE_AP;
++	}
++#if defined(WL_ENABLE_P2P_IF)
++	else if (dev == cfg->p2p_net) {
++		/* Group Add request on p2p0 */
++		WL_DBG(("Start AP req on P2P iface: GO\n"));
++		dev = bcmcfg_to_prmry_ndev(cfg);
++		dev_role = NL80211_IFTYPE_P2P_GO;
++	}
++#endif /* WL_ENABLE_P2P_IF */
++		if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	if (p2p_is_on(cfg) && (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_P2P_GO)) {
++		dev_role = NL80211_IFTYPE_P2P_GO;
++	} else if (dev_role == NL80211_IFTYPE_AP) {
++		dhd->op_mode |= DHD_FLAG_HOSTAP_MODE;
++	} else {
++		/* only AP or GO role need to be handled here. */
++		err = -EINVAL;
++		goto fail;
++	}
++
++	if (!check_dev_role_integrity(cfg, dev_role)) {
++		err = -EINVAL;
++		goto fail;
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	if ((err = wl_cfg80211_set_channel(wiphy, dev,
++		dev->ieee80211_ptr->preset_chandef.chan,
++		dev->ieee80211_ptr->preset_chandef) < 0)) {
++		WL_ERR(("Set channel failed \n"));
++		goto fail;
++	}
++#endif 
++
++	if ((err = wl_cfg80211_bcn_set_params(info, dev,
++		dev_role, bssidx)) < 0) {
++		WL_ERR(("Beacon params set failed \n"));
++		goto fail;
++	}
++
++	/* Parse IEs */
++	if ((err = wl_cfg80211_parse_ap_ies(dev, &info->beacon, &ies)) < 0) {
++		WL_ERR(("Set IEs failed \n"));
++		goto fail;
++	}
++	if ((err = wl_cfg80211_bcn_validate_sec(dev, &ies,
++		dev_role, bssidx, info->privacy)) < 0)
++	{
++		WL_ERR(("Beacon set security failed \n"));
++		goto fail;
++	}
++	if ((err = wl_cfg80211_bcn_bringup_ap(dev, &ies,
++		dev_role, bssidx)) < 0) {
++		WL_ERR(("Beacon bring up AP/GO failed \n"));
++		goto fail;
++	}
++
++	WL_DBG(("** AP/GO Created **\n"));
++#ifdef WL_CFG80211_ACL
++	/* Enfoce Admission Control. */
++	if ((err = wl_cfg80211_set_mac_acl(wiphy, dev, info->acl)) < 0) {
++		WL_ERR(("Set ACL failed\n"));
++	}
++#endif /* WL_CFG80211_ACL */
++
++	/* Set IEs to FW */
++	if ((err = wl_cfg80211_set_ies(dev, &info->beacon, bssidx)) < 0)
++		WL_ERR(("Set IEs failed \n"));
++
++	/* Enable Probe Req filter, WPS-AP certification 4.2.13 */
++	if ((dev_role == NL80211_IFTYPE_AP) && (ies.wps_ie != NULL)) {
++		bool pbc = 0;
++		wl_validate_wps_ie((char *) ies.wps_ie, ies.wps_ie_len, &pbc);
++		if (pbc) {
++			WL_DBG(("set WLC_E_PROBREQ_MSG\n"));
++			wl_add_remove_eventmsg(dev, WLC_E_PROBREQ_MSG, true);
++		}
++	}
++
++fail:
++	if (err) {
++		WL_ERR(("ADD/SET beacon failed\n"));
++		wldev_iovar_setint(dev, "mpc", 1);
++		if (dev_role == NL80211_IFTYPE_AP) {
++			dhd->op_mode &= ~DHD_FLAG_HOSTAP_MODE;
++		}
++	}
++
++	return err;
++}
++
++static s32
++wl_cfg80211_stop_ap(
++	struct wiphy *wiphy,
++	struct net_device *dev)
++{
++	int err = 0;
++	u32 dev_role = 0;
++	int infra = 0;
++	int ap = 0;
++	s32 bssidx = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct net_device *primary_ndev = bcmcfg_to_prmry_ndev(cfg);
++	s32 is_rsdb_supported = BCME_ERROR;
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++
++	WL_DBG(("Enter \n"));
++
++	is_rsdb_supported = DHD_OPMODE_SUPPORTED(cfg->pub, DHD_FLAG_RSDB_MODE);
++	if (is_rsdb_supported < 0)
++		return (-ENODEV);
++	if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_AP) {
++		dev_role = NL80211_IFTYPE_AP;
++		WL_DBG(("stopping AP operation\n"));
++	} else if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_P2P_GO) {
++		dev_role = NL80211_IFTYPE_P2P_GO;
++		WL_DBG(("stopping P2P GO operation\n"));
++	} else {
++		WL_ERR(("no AP/P2P GO interface is operational.\n"));
++		return -EINVAL;
++	}
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	if (!check_dev_role_integrity(cfg, dev_role)) {
++		WL_ERR(("role integrity check failed \n"));
++		err = -EINVAL;
++		goto exit;
++	}
++
++	/* Clear AP/GO connected status */
++	wl_clr_drv_status(cfg, CONNECTED, dev);
++
++	if ((err = wl_cfgp2p_bss(cfg, dev, bssidx, 0)) < 0) {
++		WL_ERR(("bss down error %d\n", err));
++	}
++
++	if (dev_role == NL80211_IFTYPE_AP) {
++		/*
++		 * Bring down the AP interface by changing role to STA.
++		 * Don't do a down or "WLC_SET_AP 0" since the shared
++		 * interface may be still running
++		 */
++		if (is_rsdb_supported) {
++			if ((err = wl_cfg80211_add_del_bss(cfg, dev,
++				bssidx, NL80211_IFTYPE_STATION, 0, NULL)) < 0) {
++				if ((err = wldev_ioctl(dev, WLC_SET_AP, &ap, sizeof(s32),
++					true)) < 0) {
++					WL_ERR(("setting AP mode failed %d \n", err));
++					err = -ENOTSUPP;
++					goto exit;
++				}
++			}
++		} else if (is_rsdb_supported == 0) {
++			if (dev == primary_ndev) {
++				err = wldev_ioctl(dev, WLC_DOWN, &ap, sizeof(s32), true);
++				if (err < 0) {
++					WL_ERR(("WLC_DOWN error (%d)\n", err));
++					err = -ENOTSUPP;
++					goto exit;
++				}
++
++				err = wldev_ioctl(dev, WLC_SET_AP, &ap, sizeof(s32), true);
++				if (err < 0) {
++					WL_ERR(("SET AP error %d\n", err));
++					err = -ENOTSUPP;
++					goto exit;
++				}
++
++				err = wldev_ioctl(dev, WLC_UP, &ap, sizeof(s32), true);
++				if (err < 0) {
++					WL_ERR(("WLC_UP error (%d)\n", err));
++					err = -ENOTSUPP;
++					goto exit;
++				}
++			}
++
++			err = wldev_ioctl(dev, WLC_SET_INFRA, &infra, sizeof(s32), true);
++			if (err < 0) {
++				WL_ERR(("SET INFRA error %d\n", err));
++				err = -ENOTSUPP;
++				goto exit;
++			}
++			err = wldev_ioctl(dev, WLC_UP, &ap, sizeof(s32), true);
++			if (unlikely(err)) {
++				WL_ERR(("WLC_UP error (%d)\n", err));
++				err = -EINVAL;
++				goto exit;
++			}
++		}
++
++		wl_clr_drv_status(cfg, AP_CREATED, dev);
++		/* Turn on the MPC */
++		wldev_iovar_setint(dev, "mpc", 1);
++
++		 wl_cfg80211_clear_per_bss_ies(cfg, bssidx);
++	} else {
++		WL_DBG(("Stopping P2P GO \n"));
++		DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_ENABLE((dhd_pub_t *)(cfg->pub),
++			DHD_EVENT_TIMEOUT_MS*3);
++		DHD_OS_WAKE_LOCK_TIMEOUT((dhd_pub_t *)(cfg->pub));
++	}
++
++exit:
++
++	if (dev_role == NL80211_IFTYPE_AP) {
++		/* clear the AP mode */
++		dhd->op_mode &= ~DHD_FLAG_HOSTAP_MODE;
++	}
++	return err;
++}
++
++static s32
++wl_cfg80211_change_beacon(
++	struct wiphy *wiphy,
++	struct net_device *dev,
++	struct cfg80211_beacon_data *info)
++{
++	s32 err = BCME_OK;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct parsed_ies ies;
++	u32 dev_role = 0;
++	s32 bssidx = 0;
++	bool pbc = 0;
++
++	WL_DBG(("Enter \n"));
++
++	if (dev == bcmcfg_to_prmry_ndev(cfg)) {
++		dev_role = NL80211_IFTYPE_AP;
++	}
++#if defined(WL_ENABLE_P2P_IF)
++	else if (dev == cfg->p2p_net) {
++		/* Group Add request on p2p0 */
++		dev = bcmcfg_to_prmry_ndev(cfg);
++		dev_role = NL80211_IFTYPE_P2P_GO;
++	}
++#endif /* WL_ENABLE_P2P_IF */
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_P2P_GO) {
++		dev_role = NL80211_IFTYPE_P2P_GO;
++	}
++
++	if (!check_dev_role_integrity(cfg, dev_role)) {
++		err = -EINVAL;
++		goto fail;
++	}
++
++	if ((dev_role == NL80211_IFTYPE_P2P_GO) && (cfg->p2p_wdev == NULL)) {
++		WL_ERR(("P2P already down status!\n"));
++		err = BCME_ERROR;
++		goto fail;
++	}
++
++	/* Parse IEs */
++	if ((err = wl_cfg80211_parse_ap_ies(dev, info, &ies)) < 0) {
++		WL_ERR(("Parse IEs failed \n"));
++		goto fail;
++	}
++
++	/* Set IEs to FW */
++	if ((err = wl_cfg80211_set_ies(dev, info, bssidx)) < 0) {
++		WL_ERR(("Set IEs failed \n"));
++		goto fail;
++	}
++
++	if (dev_role == NL80211_IFTYPE_AP) {
++		if (wl_cfg80211_hostapd_sec(dev, &ies, bssidx) < 0) {
++			WL_ERR(("Hostapd update sec failed \n"));
++			err = -EINVAL;
++			goto fail;
++		}
++		/* Enable Probe Req filter, WPS-AP certification 4.2.13 */
++		if ((dev_role == NL80211_IFTYPE_AP) && (ies.wps_ie != NULL)) {
++			wl_validate_wps_ie((char *) ies.wps_ie, ies.wps_ie_len, &pbc);
++			WL_DBG((" WPS AP, wps_ie is exists pbc=%d\n", pbc));
++			if (pbc)
++				wl_add_remove_eventmsg(dev, WLC_E_PROBREQ_MSG, true);
++			else
++				wl_add_remove_eventmsg(dev, WLC_E_PROBREQ_MSG, false);
++		}
++	}
++
++fail:
++	return err;
++}
++#else
++static s32
++wl_cfg80211_add_set_beacon(struct wiphy *wiphy, struct net_device *dev,
++	struct beacon_parameters *info)
++{
++	s32 err = BCME_OK;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 ie_offset = 0;
++	s32 bssidx = 0;
++	u32 dev_role = NL80211_IFTYPE_AP;
++	struct parsed_ies ies;
++	bcm_tlv_t *ssid_ie;
++	bool pbc = 0;
++	bool privacy;
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++
++	WL_DBG(("interval (%d) dtim_period (%d) head_len (%d) tail_len (%d)\n",
++		info->interval, info->dtim_period, info->head_len, info->tail_len));
++
++	if (dev == bcmcfg_to_prmry_ndev(cfg)) {
++		dev_role = NL80211_IFTYPE_AP;
++	}
++#if defined(WL_ENABLE_P2P_IF)
++	else if (dev == cfg->p2p_net) {
++		/* Group Add request on p2p0 */
++		dev = bcmcfg_to_prmry_ndev(cfg);
++		dev_role = NL80211_IFTYPE_P2P_GO;
++	}
++#endif /* WL_ENABLE_P2P_IF */
++
++	if ((bssidx = wl_get_bssidx_by_wdev(cfg, dev->ieee80211_ptr)) < 0) {
++		WL_ERR(("Find p2p index from wdev(%p) failed\n", dev->ieee80211_ptr));
++		return BCME_ERROR;
++	}
++
++	if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_P2P_GO) {
++		dev_role = NL80211_IFTYPE_P2P_GO;
++	} else if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_AP) {
++		dhd->op_mode |= DHD_FLAG_HOSTAP_MODE;
++	}
++
++	if (!check_dev_role_integrity(cfg, dev_role)) {
++		err = -ENODEV;
++		goto fail;
++	}
++
++	if ((dev_role == NL80211_IFTYPE_P2P_GO) && (cfg->p2p_wdev == NULL)) {
++		WL_ERR(("P2P already down status!\n"));
++		err = BCME_ERROR;
++		goto fail;
++	}
++
++	ie_offset = DOT11_MGMT_HDR_LEN + DOT11_BCN_PRB_FIXED_LEN;
++	/* find the SSID */
++	if ((ssid_ie = bcm_parse_tlvs((u8 *)&info->head[ie_offset],
++		info->head_len - ie_offset,
++		DOT11_MNG_SSID_ID)) != NULL) {
++		if (dev_role == NL80211_IFTYPE_AP) {
++			/* Store the hostapd SSID */
++			memset(&cfg->hostapd_ssid.SSID[0], 0x00, 32);
++			memcpy(&cfg->hostapd_ssid.SSID[0], ssid_ie->data, ssid_ie->len);
++			cfg->hostapd_ssid.SSID_len = ssid_ie->len;
++		} else {
++				/* P2P GO */
++			memset(&cfg->p2p->ssid.SSID[0], 0x00, 32);
++			memcpy(cfg->p2p->ssid.SSID, ssid_ie->data, ssid_ie->len);
++			cfg->p2p->ssid.SSID_len = ssid_ie->len;
++		}
++	}
++
++	if (wl_cfg80211_parse_ies((u8 *)info->tail,
++		info->tail_len, &ies) < 0) {
++		WL_ERR(("Beacon get IEs failed \n"));
++		err = -EINVAL;
++		goto fail;
++	}
++
++	if ((err = wl_cfg80211_set_mgmt_vndr_ies(cfg, ndev_to_cfgdev(dev), bssidx,
++		VNDR_IE_BEACON_FLAG, (u8 *)info->tail,
++		info->tail_len)) < 0) {
++		WL_ERR(("Beacon set IEs failed \n"));
++		goto fail;
++	} else {
++		WL_DBG(("Applied Vndr IEs for Beacon \n"));
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	if ((err = wl_cfg80211_set_mgmt_vndr_ies(cfg, ndev_to_cfgdev(dev), bssidx,
++		VNDR_IE_PRBRSP_FLAG, (u8 *)info->proberesp_ies,
++		info->proberesp_ies_len)) < 0) {
++		WL_ERR(("ProbeRsp set IEs failed \n"));
++		goto fail;
++	} else {
++		WL_DBG(("Applied Vndr IEs for ProbeRsp \n"));
++	}
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	privacy = info->privacy;
++#else
++	privacy = 0;
++#endif
++	if (!wl_cfgp2p_bss_isup(dev, bssidx) &&
++		(wl_cfg80211_bcn_validate_sec(dev, &ies, dev_role, bssidx, privacy) < 0))
++	{
++		WL_ERR(("Beacon set security failed \n"));
++		err = -EINVAL;
++		goto fail;
++	}
++
++	/* Set BI and DTIM period */
++	if (info->interval) {
++		if ((err = wldev_ioctl(dev, WLC_SET_BCNPRD,
++			&info->interval, sizeof(s32), true)) < 0) {
++			WL_ERR(("Beacon Interval Set Error, %d\n", err));
++			return err;
++		}
++	}
++	if (info->dtim_period) {
++		if ((err = wldev_ioctl(dev, WLC_SET_DTIMPRD,
++			&info->dtim_period, sizeof(s32), true)) < 0) {
++			WL_ERR(("DTIM Interval Set Error, %d\n", err));
++			return err;
++		}
++	}
++
++	if ((err = wl_cfg80211_bcn_bringup_ap(dev, &ies, dev_role, bssidx)) < 0) {
++		WL_ERR(("Beacon bring up AP/GO failed \n"));
++		goto fail;
++	}
++
++	if (wl_get_drv_status(cfg, AP_CREATED, dev)) {
++		/* Soft AP already running. Update changed params */
++		if (wl_cfg80211_hostapd_sec(dev, &ies, bssidx) < 0) {
++			WL_ERR(("Hostapd update sec failed \n"));
++			err = -EINVAL;
++			goto fail;
++		}
++	}
++
++	/* Enable Probe Req filter */
++	if (((dev_role == NL80211_IFTYPE_P2P_GO) ||
++		(dev_role == NL80211_IFTYPE_AP)) && (ies.wps_ie != NULL)) {
++		wl_validate_wps_ie((char *) ies.wps_ie, ies.wps_ie_len, &pbc);
++		if (pbc)
++			wl_add_remove_eventmsg(dev, WLC_E_PROBREQ_MSG, true);
++	}
++
++	WL_DBG(("** ADD/SET beacon done **\n"));
++
++fail:
++	if (err) {
++		WL_ERR(("ADD/SET beacon failed\n"));
++		wldev_iovar_setint(dev, "mpc", 1);
++		if (dev_role == NL80211_IFTYPE_AP) {
++			/* clear the AP mode */
++			dhd->op_mode &= ~DHD_FLAG_HOSTAP_MODE;
++		}
++	}
++	return err;
++
++}
++#endif 
++
++#ifdef WL_SCHED_SCAN
++#define PNO_TIME		30
++#define PNO_REPEAT		4
++#define PNO_FREQ_EXPO_MAX	2
++static bool
++is_ssid_in_list(struct cfg80211_ssid *ssid, struct cfg80211_ssid *ssid_list, int count)
++{
++	int i;
++
++	if (!ssid || !ssid_list)
++		return FALSE;
++
++	for (i = 0; i < count; i++) {
++		if (ssid->ssid_len == ssid_list[i].ssid_len) {
++			if (strncmp(ssid->ssid, ssid_list[i].ssid, ssid->ssid_len) == 0)
++				return TRUE;
++		}
++	}
++	return FALSE;
++}
++
++static int
++wl_cfg80211_sched_scan_start(struct wiphy *wiphy,
++                             struct net_device *dev,
++                             struct cfg80211_sched_scan_request *request)
++{
++	ushort pno_time = PNO_TIME;
++	int pno_repeat = PNO_REPEAT;
++	int pno_freq_expo_max = PNO_FREQ_EXPO_MAX;
++	wlc_ssid_ext_t ssids_local[MAX_PFN_LIST_COUNT];
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct cfg80211_ssid *ssid = NULL;
++	struct cfg80211_ssid *hidden_ssid_list = NULL;
++	int ssid_cnt = 0;
++	int i;
++	int ret = 0;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	s32 rssi_thold = 0;
++#endif /* LINUX_KERNEL_VER >= 3.6 */
++
++	if (!request) {
++		WL_ERR(("Sched scan request was NULL\n"));
++		return -EINVAL;
++	}
++
++	WL_DBG(("Enter \n"));
++	WL_PNO((">>> SCHED SCAN START\n"));
++	WL_PNO(("Enter n_match_sets:%d   n_ssids:%d \n",
++		request->n_match_sets, request->n_ssids));
++	WL_PNO(("ssids:%d pno_time:%d pno_repeat:%d pno_freq:%d \n",
++		request->n_ssids, pno_time, pno_repeat, pno_freq_expo_max));
++
++
++	if (!request->n_ssids || !request->n_match_sets) {
++		WL_ERR(("Invalid sched scan req!! n_ssids:%d \n", request->n_ssids));
++		return -EINVAL;
++	}
++
++	memset(&ssids_local, 0, sizeof(ssids_local));
++
++	if (request->n_ssids > 0) {
++		hidden_ssid_list = request->ssids;
++	}
++
++	for (i = 0; i < request->n_match_sets && ssid_cnt < MAX_PFN_LIST_COUNT; i++) {
++		ssid = &request->match_sets[i].ssid;
++		/* No need to include null ssid */
++		if (ssid->ssid_len) {
++			memcpy(ssids_local[ssid_cnt].SSID, ssid->ssid, ssid->ssid_len);
++			ssids_local[ssid_cnt].SSID_len = ssid->ssid_len;
++			if (is_ssid_in_list(ssid, hidden_ssid_list, request->n_ssids)) {
++				ssids_local[ssid_cnt].hidden = TRUE;
++				WL_PNO((">>> PNO hidden SSID (%s) \n", ssid->ssid));
++			} else {
++				ssids_local[ssid_cnt].hidden = FALSE;
++				WL_PNO((">>> PNO non-hidden SSID (%s) \n", ssid->ssid));
++			}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))
++			/* Per BSS rssi threshold is available from kernel >= 3.15 */
++			rssi_thold = request->match_sets[i].rssi_thold;
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++			/* Blanket rssi threshold only available from cfg80211 */
++			rssi_thold = request->rssi_thold;
++#endif /* KERNEL_VER >= 3.15 */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++			if (rssi_thold != NL80211_SCAN_RSSI_THOLD_OFF) {
++				ssids_local[ssid_cnt].rssi_thresh =
++				      (int8)rssi_thold;
++			}
++#endif /* KERNEL_VER >= 3.6 */
++			ssid_cnt++;
++		}
++	}
++
++	if (ssid_cnt) {
++		if ((ret = dhd_dev_pno_set_for_ssid(dev, ssids_local, ssid_cnt,
++			pno_time, pno_repeat, pno_freq_expo_max, NULL, 0)) < 0) {
++			WL_ERR(("PNO setup failed!! ret=%d \n", ret));
++			return -EINVAL;
++		}
++		cfg->sched_scan_req = request;
++	} else {
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int
++wl_cfg80211_sched_scan_stop(struct wiphy *wiphy, struct net_device *dev)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	WL_DBG(("Enter \n"));
++	WL_PNO((">>> SCHED SCAN STOP\n"));
++
++	if (dhd_dev_pno_stop_for_ssid(dev) < 0)
++		WL_ERR(("PNO Stop for SSID failed"));
++
++	if (cfg->scan_request && cfg->sched_scan_running) {
++		WL_PNO((">>> Sched scan running. Aborting it..\n"));
++		wl_notify_escan_complete(cfg, dev, true, true);
++	}
++
++	 cfg->sched_scan_req = NULL;
++	 cfg->sched_scan_running = FALSE;
++
++	return 0;
++}
++#endif /* WL_SCHED_SCAN */
++
++#ifdef WL_SUPPORT_ACS
++/*
++ * Currently the dump_obss IOVAR is returning string as output so we need to
++ * parse the output buffer in an unoptimized way. Going forward if we get the
++ * IOVAR output in binary format this method can be optimized
++ */
++static int wl_parse_dump_obss(char *buf, struct wl_dump_survey *survey)
++{
++	int i;
++	char *token;
++	char delim[] = " \n";
++
++	token = strsep(&buf, delim);
++	while (token != NULL) {
++		if (!strcmp(token, "OBSS")) {
++			for (i = 0; i < OBSS_TOKEN_IDX; i++)
++				token = strsep(&buf, delim);
++			survey->obss = simple_strtoul(token, NULL, 10);
++		}
++
++		if (!strcmp(token, "IBSS")) {
++			for (i = 0; i < IBSS_TOKEN_IDX; i++)
++				token = strsep(&buf, delim);
++			survey->ibss = simple_strtoul(token, NULL, 10);
++		}
++
++		if (!strcmp(token, "TXDur")) {
++			for (i = 0; i < TX_TOKEN_IDX; i++)
++				token = strsep(&buf, delim);
++			survey->tx = simple_strtoul(token, NULL, 10);
++		}
++
++		if (!strcmp(token, "Category")) {
++			for (i = 0; i < CTG_TOKEN_IDX; i++)
++				token = strsep(&buf, delim);
++			survey->no_ctg = simple_strtoul(token, NULL, 10);
++		}
++
++		if (!strcmp(token, "Packet")) {
++			for (i = 0; i < PKT_TOKEN_IDX; i++)
++				token = strsep(&buf, delim);
++			survey->no_pckt = simple_strtoul(token, NULL, 10);
++		}
++
++		if (!strcmp(token, "Opp(time):")) {
++			for (i = 0; i < IDLE_TOKEN_IDX; i++)
++				token = strsep(&buf, delim);
++			survey->idle = simple_strtoul(token, NULL, 10);
++		}
++
++		token = strsep(&buf, delim);
++	}
++
++	return 0;
++}
++
++static int wl_dump_obss(struct net_device *ndev, cca_msrmnt_query req,
++	struct wl_dump_survey *survey)
++{
++	cca_stats_n_flags *results;
++	char *buf;
++	int retry, err;
++
++	buf = kzalloc(sizeof(char) * WLC_IOCTL_MAXLEN, GFP_KERNEL);
++	if (unlikely(!buf)) {
++		WL_ERR(("%s: buf alloc failed\n", __func__));
++		return -ENOMEM;
++	}
++
++	retry = IOCTL_RETRY_COUNT;
++	while (retry--) {
++		err = wldev_iovar_getbuf(ndev, "dump_obss", &req, sizeof(req),
++			buf, WLC_IOCTL_MAXLEN, NULL);
++		if (err >=  0) {
++			break;
++		}
++		WL_DBG(("attempt = %d, err = %d, \n",
++			(IOCTL_RETRY_COUNT - retry), err));
++	}
++
++	if (retry <= 0)	{
++		WL_ERR(("failure, dump_obss IOVAR failed\n"));
++		err = -EINVAL;
++		goto exit;
++	}
++
++	results = (cca_stats_n_flags *)(buf);
++	wl_parse_dump_obss(results->buf, survey);
++	kfree(buf);
++
++	return 0;
++exit:
++	kfree(buf);
++	return err;
++}
++
++static int wl_cfg80211_dump_survey(struct wiphy *wiphy, struct net_device *ndev,
++	int idx, struct survey_info *info)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct wl_dump_survey *survey;
++	struct ieee80211_supported_band *band;
++	struct ieee80211_channel*chan;
++	cca_msrmnt_query req;
++	int val, err, noise, retry;
++
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++	if (!(dhd->op_mode & DHD_FLAG_HOSTAP_MODE)) {
++		return -ENOENT;
++	}
++	band = wiphy->bands[IEEE80211_BAND_2GHZ];
++	if (band && idx >= band->n_channels) {
++		idx -= band->n_channels;
++		band = NULL;
++	}
++
++	if (!band || idx >= band->n_channels) {
++		/* Move to 5G band */
++		band = wiphy->bands[IEEE80211_BAND_5GHZ];
++		if (idx >= band->n_channels) {
++			return -ENOENT;
++		}
++	}
++
++	chan = &band->channels[idx];
++	/* Setting current channel to the requested channel */
++	if ((err = wl_cfg80211_set_channel(wiphy, ndev, chan,
++		NL80211_CHAN_HT20) < 0)) {
++		WL_ERR(("Set channel failed \n"));
++	}
++
++	if (!idx) {
++		/* Disable mpc */
++		val = 0;
++		err = wldev_iovar_setbuf_bsscfg(ndev, "mpc", (void *)&val,
++			sizeof(val), cfg->ioctl_buf, WLC_IOCTL_SMLEN, 0,
++			&cfg->ioctl_buf_sync);
++		if (err < 0) {
++			WL_ERR(("set 'mpc' failed, error = %d\n", err));
++		}
++
++		/* Set interface up, explicitly. */
++		val = 1;
++		err = wldev_ioctl(ndev, WLC_UP, (void *)&val, sizeof(val), true);
++		if (err < 0) {
++			WL_ERR(("set interface up failed, error = %d\n", err));
++		}
++	}
++
++	/* Get noise value */
++	retry = IOCTL_RETRY_COUNT;
++	while (retry--) {
++		noise = 0;
++		err = wldev_ioctl(ndev, WLC_GET_PHY_NOISE, &noise,
++			sizeof(noise), false);
++		if (err >=  0) {
++			break;
++		}
++		WL_DBG(("attempt = %d, err = %d, \n",
++			(IOCTL_RETRY_COUNT - retry), err));
++	}
++
++	if (retry <= 0)	{
++		WL_ERR(("Get Phy Noise failed, error = %d\n", err));
++		noise = CHAN_NOISE_DUMMY;
++	}
++
++	survey = (struct wl_dump_survey *) kzalloc(sizeof(struct wl_dump_survey),
++		GFP_KERNEL);
++	if (unlikely(!survey)) {
++		WL_ERR(("%s: alloc failed\n", __func__));
++		return -ENOMEM;
++	}
++
++	/* Start Measurement for obss stats on current channel */
++	req.msrmnt_query = 0;
++	req.time_req = ACS_MSRMNT_DELAY;
++	if ((err = wl_dump_obss(ndev, req, survey)) < 0) {
++		goto exit;
++	}
++
++	/*
++	 * Wait for the meaurement to complete, adding a buffer value of 10 to take
++	 * into consideration any delay in IOVAR completion
++	 */
++	msleep(ACS_MSRMNT_DELAY + 10);
++
++	/* Issue IOVAR to collect measurement results */
++	req.msrmnt_query = 1;
++	if ((err = wl_dump_obss(ndev, req, survey)) < 0) {
++		goto exit;
++	}
++
++	info->channel = chan;
++	info->noise = noise;
++	info->channel_time = ACS_MSRMNT_DELAY;
++	info->channel_time_busy = ACS_MSRMNT_DELAY - survey->idle;
++	info->channel_time_rx = survey->obss + survey->ibss + survey->no_ctg +
++		survey->no_pckt;
++	info->channel_time_tx = survey->tx;
++	info->filled = SURVEY_INFO_NOISE_DBM |SURVEY_INFO_CHANNEL_TIME |
++		SURVEY_INFO_CHANNEL_TIME_BUSY |	SURVEY_INFO_CHANNEL_TIME_RX |
++		SURVEY_INFO_CHANNEL_TIME_TX;
++	kfree(survey);
++
++	return 0;
++exit:
++	kfree(survey);
++	return err;
++}
++#endif /* WL_SUPPORT_ACS */
++
++static struct cfg80211_ops wl_cfg80211_ops = {
++	.add_virtual_intf = wl_cfg80211_add_virtual_iface,
++	.del_virtual_intf = wl_cfg80211_del_virtual_iface,
++	.change_virtual_intf = wl_cfg80211_change_virtual_iface,
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	.start_p2p_device = wl_cfgp2p_start_p2p_device,
++	.stop_p2p_device = wl_cfgp2p_stop_p2p_device,
++#endif /* WL_CFG80211_P2P_DEV_IF */
++	.scan = wl_cfg80211_scan,
++	.set_wiphy_params = wl_cfg80211_set_wiphy_params,
++	.join_ibss = wl_cfg80211_join_ibss,
++	.leave_ibss = wl_cfg80211_leave_ibss,
++	.get_station = wl_cfg80211_get_station,
++	.set_tx_power = wl_cfg80211_set_tx_power,
++	.get_tx_power = wl_cfg80211_get_tx_power,
++	.add_key = wl_cfg80211_add_key,
++	.del_key = wl_cfg80211_del_key,
++	.get_key = wl_cfg80211_get_key,
++	.set_default_key = wl_cfg80211_config_default_key,
++	.set_default_mgmt_key = wl_cfg80211_config_default_mgmt_key,
++	.set_power_mgmt = wl_cfg80211_set_power_mgmt,
++	.connect = wl_cfg80211_connect,
++	.disconnect = wl_cfg80211_disconnect,
++	.suspend = wl_cfg80211_suspend,
++	.resume = wl_cfg80211_resume,
++	.set_pmksa = wl_cfg80211_set_pmksa,
++	.del_pmksa = wl_cfg80211_del_pmksa,
++	.flush_pmksa = wl_cfg80211_flush_pmksa,
++	.remain_on_channel = wl_cfg80211_remain_on_channel,
++	.cancel_remain_on_channel = wl_cfg80211_cancel_remain_on_channel,
++	.mgmt_tx = wl_cfg80211_mgmt_tx,
++	/*.mgmt_frame_register = wl_cfg80211_mgmt_frame_register,*/
++        .update_mgmt_frame_registrations = wl_cfg80211_mgmt_frame_register,
++	.change_bss = wl_cfg80211_change_bss,
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++	.set_channel = wl_cfg80211_set_channel,
++#endif 
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0))
++	.set_beacon = wl_cfg80211_add_set_beacon,
++	.add_beacon = wl_cfg80211_add_set_beacon,
++#else
++	.change_beacon = wl_cfg80211_change_beacon,
++	.start_ap = wl_cfg80211_start_ap,
++	.stop_ap = wl_cfg80211_stop_ap,
++#endif 
++#ifdef WL_SCHED_SCAN
++	.sched_scan_start = wl_cfg80211_sched_scan_start,
++	.sched_scan_stop = wl_cfg80211_sched_scan_stop,
++#endif /* WL_SCHED_SCAN */
++#if defined(WL_SUPPORT_BACKPORTED_KPATCHES) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, \
++	2, 0))
++	.del_station = wl_cfg80211_del_station,
++	.change_station = wl_cfg80211_change_station,
++	.mgmt_tx_cancel_wait = wl_cfg80211_mgmt_tx_cancel_wait,
++#endif /* WL_SUPPORT_BACKPORTED_KPATCHES || KERNEL_VERSION >= (3,2,0) */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	.tdls_mgmt = wl_cfg80211_tdls_mgmt,
++	.tdls_oper = wl_cfg80211_tdls_oper,
++#endif 
++#ifdef WL_SUPPORT_ACS
++	.dump_survey = wl_cfg80211_dump_survey,
++#endif /* WL_SUPPORT_ACS */
++#ifdef WL_CFG80211_ACL
++	.set_mac_acl = wl_cfg80211_set_mac_acl,
++#endif /* WL_CFG80211_ACL */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
++	.set_rekey_data = wl_cfg80211_set_rekey_data,
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0) */
++};
++
++s32 wl_mode_to_nl80211_iftype(s32 mode)
++{
++	s32 err = 0;
++
++	switch (mode) {
++	case WL_MODE_BSS:
++		return NL80211_IFTYPE_STATION;
++	case WL_MODE_IBSS:
++		return NL80211_IFTYPE_ADHOC;
++	case WL_MODE_AP:
++		return NL80211_IFTYPE_AP;
++	default:
++		return NL80211_IFTYPE_UNSPECIFIED;
++	}
++
++	return err;
++}
++
++#ifdef CONFIG_CFG80211_INTERNAL_REGDB
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
++static int
++#else
++static void
++#endif /* kernel version < 3.9.0 */
++wl_cfg80211_reg_notifier(
++	struct wiphy *wiphy,
++	struct regulatory_request *request)
++{
++	struct bcm_cfg80211 *cfg = (struct bcm_cfg80211 *)wiphy_priv(wiphy);
++	int ret = 0;
++	int revinfo = -1;
++
++	if (!request || !cfg) {
++		WL_ERR(("Invalid arg\n"));
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
++		return -EINVAL;
++#else
++		return;
++#endif /* kernel version < 3.9.0 */
++	}
++
++	WL_DBG(("ccode: %c%c Initiator: %d\n",
++		request->alpha2[0], request->alpha2[1], request->initiator));
++
++	/* We support only REGDOM_SET_BY_USER as of now */
++	if ((request->initiator != NL80211_REGDOM_SET_BY_USER) &&
++		(request->initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE)) {
++		WL_ERR(("reg_notifier for intiator:%d not supported : set default\n",
++			request->initiator));
++		/* in case of no supported country by regdb
++		     lets driver setup platform default Locale
++		*/
++	}
++
++	WL_ERR(("Set country code %c%c from %s\n",
++		request->alpha2[0], request->alpha2[1],
++		((request->initiator == NL80211_REGDOM_SET_BY_COUNTRY_IE) ? " 11d AP" : "User")));
++
++	if ((ret = wldev_set_country(bcmcfg_to_prmry_ndev(cfg), request->alpha2,
++		false, (request->initiator == NL80211_REGDOM_SET_BY_USER ? true : false),
++		revinfo)) < 0) {
++		WL_ERR(("set country Failed :%d\n", ret));
++	}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
++	return ret;
++#else
++	return;
++#endif /* kernel version < 3.9.0 */
++}
++#endif /* CONFIG_CFG80211_INTERNAL_REGDB */
++
++#ifdef CONFIG_PM
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++static const struct wiphy_wowlan_support brcm_wowlan_support = {
++	.flags = WIPHY_WOWLAN_ANY,
++	.n_patterns = WL_WOWLAN_MAX_PATTERNS,
++	.pattern_min_len = WL_WOWLAN_MIN_PATTERN_LEN,
++	.pattern_max_len = WL_WOWLAN_MAX_PATTERN_LEN,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++	.max_pkt_offset = WL_WOWLAN_MAX_PATTERN_LEN,
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) */
++};
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0) */
++#endif /* CONFIG_PM */
++
++static s32 wl_setup_wiphy(struct wireless_dev *wdev, struct device *sdiofunc_dev, void *context)
++{
++	s32 err = 0;
++#ifdef CONFIG_PM
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++	struct cfg80211_wowlan *brcm_wowlan_config = NULL;
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0) */
++#endif /* CONFIG_PM */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
++	dhd_pub_t *dhd = (dhd_pub_t *)context;
++	BCM_REFERENCE(dhd);
++
++	if (!dhd) {
++		WL_ERR(("DHD is NULL!!"));
++		err = -ENODEV;
++		return err;
++	}
++#endif 
++
++	wdev->wiphy =
++	    wiphy_new(&wl_cfg80211_ops, sizeof(struct bcm_cfg80211));
++	if (unlikely(!wdev->wiphy)) {
++		WL_ERR(("Couldn not allocate wiphy device\n"));
++		err = -ENOMEM;
++		return err;
++	}
++	set_wiphy_dev(wdev->wiphy, sdiofunc_dev);
++	wdev->wiphy->max_scan_ie_len = WL_SCAN_IE_LEN_MAX;
++	/* Report  how many SSIDs Driver can support per Scan request */
++	wdev->wiphy->max_scan_ssids = WL_SCAN_PARAMS_SSID_MAX;
++	wdev->wiphy->max_num_pmkids = WL_NUM_PMKIDS_MAX;
++#ifdef WL_SCHED_SCAN
++	wdev->wiphy->max_sched_scan_ssids = MAX_PFN_LIST_COUNT;
++	wdev->wiphy->max_match_sets = MAX_PFN_LIST_COUNT;
++	wdev->wiphy->max_sched_scan_ie_len = WL_SCAN_IE_LEN_MAX;
++	wdev->wiphy->flags |= WIPHY_FLAG_SUPPORTS_SCHED_SCAN;
++#endif /* WL_SCHED_SCAN */
++	wdev->wiphy->interface_modes =
++		BIT(NL80211_IFTYPE_STATION)
++		| BIT(NL80211_IFTYPE_ADHOC)
++#if !defined(WL_ENABLE_P2P_IF) && !defined(WL_CFG80211_P2P_DEV_IF)
++		| BIT(NL80211_IFTYPE_MONITOR)
++#endif /* !WL_ENABLE_P2P_IF && !WL_CFG80211_P2P_DEV_IF */
++#if defined(WL_IFACE_COMB_NUM_CHANNELS) || defined(WL_CFG80211_P2P_DEV_IF)
++		| BIT(NL80211_IFTYPE_P2P_CLIENT)
++		| BIT(NL80211_IFTYPE_P2P_GO)
++#endif /* WL_IFACE_COMB_NUM_CHANNELS || WL_CFG80211_P2P_DEV_IF */
++#if defined(WL_CFG80211_P2P_DEV_IF)
++		| BIT(NL80211_IFTYPE_P2P_DEVICE)
++#endif /* WL_CFG80211_P2P_DEV_IF */
++		| BIT(NL80211_IFTYPE_AP);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) && \
++	(defined(WL_IFACE_COMB_NUM_CHANNELS) || defined(WL_CFG80211_P2P_DEV_IF))
++	WL_DBG(("Setting interface combinations for common mode\n"));
++	wdev->wiphy->iface_combinations = common_iface_combinations;
++	wdev->wiphy->n_iface_combinations =
++		ARRAY_SIZE(common_iface_combinations);
++#endif /* LINUX_VER >= 3.0 && (WL_IFACE_COMB_NUM_CHANNELS || WL_CFG80211_P2P_DEV_IF) */
++
++	wdev->wiphy->bands[IEEE80211_BAND_2GHZ] = &__wl_band_2ghz;
++
++	wdev->wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
++	wdev->wiphy->cipher_suites = __wl_cipher_suites;
++	wdev->wiphy->n_cipher_suites = ARRAY_SIZE(__wl_cipher_suites);
++	wdev->wiphy->max_remain_on_channel_duration = 5000;
++	wdev->wiphy->mgmt_stypes = wl_cfg80211_default_mgmt_stypes;
++#ifndef WL_POWERSAVE_DISABLED
++	wdev->wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT;
++#else
++	wdev->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
++#endif				/* !WL_POWERSAVE_DISABLED */
++	wdev->wiphy->flags |= WIPHY_FLAG_NETNS_OK |
++		WIPHY_FLAG_4ADDR_AP |
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39))
++		WIPHY_FLAG_SUPPORTS_SEPARATE_DEFAULT_KEYS |
++#endif
++		WIPHY_FLAG_4ADDR_STATION;
++#if ((defined(ROAM_ENABLE) || defined(BCMFW_ROAM_ENABLE)) && (LINUX_VERSION_CODE >= \
++	KERNEL_VERSION(3, 2, 0)))
++	/*
++	 * If FW ROAM flag is advertised, upper layer wouldn't provide
++	 * the bssid & freq in the connect command. This will result a
++	 * delay in initial connection time due to firmware doing a full
++	 * channel scan to figure out the channel & bssid. However kernel
++	 * ver >= 3.15, provides bssid_hint & freq_hint and hence kernel
++	 * ver >= 3.15 won't have any issue. So if this flags need to be
++	 * advertised for kernel < 3.15, suggest to use RCC along with it
++	 * to avoid the initial connection delay.
++	 */
++	wdev->wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM;
++#endif 
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
++	wdev->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL |
++		WIPHY_FLAG_OFFCHAN_TX;
++#endif
++#if defined(WL_SUPPORT_BACKPORTED_KPATCHES) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, \
++	4, 0))
++	/* From 3.4 kernel ownards AP_SME flag can be advertised
++	 * to remove the patch from supplicant
++	 */
++	wdev->wiphy->flags |= WIPHY_FLAG_HAVE_AP_SME;
++
++#ifdef WL_CFG80211_ACL
++	/* Configure ACL capabilities. */
++	wdev->wiphy->max_acl_mac_addrs = MAX_NUM_MAC_FILT;
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
++	/* Supplicant distinguish between the SoftAP mode and other
++	 * modes (e.g. P2P, WPS, HS2.0) when it builds the probe
++	 * response frame from Supplicant MR1 and Kernel 3.4.0 or
++	 * later version. To add Vendor specific IE into the
++	 * probe response frame in case of SoftAP mode,
++	 * AP_PROBE_RESP_OFFLOAD flag is set to wiphy->flags variable.
++	 */
++	if (dhd_get_fw_mode(dhd->info) == DHD_FLAG_HOSTAP_MODE) {
++		wdev->wiphy->flags |= WIPHY_FLAG_AP_PROBE_RESP_OFFLOAD;
++		wdev->wiphy->probe_resp_offload = 0;
++	}
++#endif 
++#endif /* WL_SUPPORT_BACKPORTED_KPATCHES) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	wdev->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
++#endif
++
++#if defined(CONFIG_PM) && defined(WL_CFG80211_P2P_DEV_IF)
++	/*
++	 * From linux-3.10 kernel, wowlan packet filter is mandated to avoid the
++	 * disconnection of connected network before suspend. So a dummy wowlan
++	 * filter is configured for kernels linux-3.8 and above.
++	 */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++	wdev->wiphy->wowlan = &brcm_wowlan_support;
++	/* If this is not provided cfg stack will get disconnect
++	 * during suspend.
++	 */
++	brcm_wowlan_config = kmalloc(sizeof(struct cfg80211_wowlan), GFP_KERNEL);
++	if (brcm_wowlan_config) {
++		brcm_wowlan_config->disconnect = true;
++		brcm_wowlan_config->gtk_rekey_failure = true;
++		brcm_wowlan_config->eap_identity_req = true;
++		brcm_wowlan_config->four_way_handshake = true;
++		brcm_wowlan_config->patterns = NULL;
++		brcm_wowlan_config->n_patterns = 0;
++		brcm_wowlan_config->tcp = NULL;
++	} else {
++		WL_ERR(("Can not allocate memory for brcm_wowlan_config,"
++					" So wiphy->wowlan_config is set to NULL\n"));
++	}
++	wdev->wiphy->wowlan_config = brcm_wowlan_config;
++#else
++	wdev->wiphy->wowlan.flags = WIPHY_WOWLAN_ANY;
++	wdev->wiphy->wowlan.n_patterns = WL_WOWLAN_MAX_PATTERNS;
++	wdev->wiphy->wowlan.pattern_min_len = WL_WOWLAN_MIN_PATTERN_LEN;
++	wdev->wiphy->wowlan.pattern_max_len = WL_WOWLAN_MAX_PATTERN_LEN;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++	wdev->wiphy->wowlan.max_pkt_offset = WL_WOWLAN_MAX_PATTERN_LEN;
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) */
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0) */
++#endif /* CONFIG_PM && WL_CFG80211_P2P_DEV_IF */
++
++	WL_DBG(("Registering custom regulatory)\n"));
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
++	wdev->wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG;
++#else
++	wdev->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY;
++#endif
++	wiphy_apply_custom_regulatory(wdev->wiphy, &brcm_regdom);
++#if defined(WL_VENDOR_EXT_SUPPORT)
++	WL_ERR(("Registering Vendor80211\n"));
++	err = wl_cfgvendor_attach(wdev->wiphy, dhd);
++	if (unlikely(err < 0)) {
++		WL_ERR(("Couldn not attach vendor commands (%d)\n", err));
++	}
++#endif /* defined(WL_VENDOR_EXT_SUPPORT) */
++	/* Now we can register wiphy with cfg80211 module */
++	err = wiphy_register(wdev->wiphy);
++	if (unlikely(err < 0)) {
++		WL_ERR(("Couldn not register wiphy device (%d)\n", err));
++		wiphy_free(wdev->wiphy);
++	}
++
++#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) && (LINUX_VERSION_CODE <= \
++	KERNEL_VERSION(3, 3, 0))) && defined(WL_IFACE_COMB_NUM_CHANNELS)
++	wdev->wiphy->flags &= ~WIPHY_FLAG_ENFORCE_COMBINATIONS;
++#endif
++
++	return err;
++}
++
++static void wl_free_wdev(struct bcm_cfg80211 *cfg)
++{
++	struct wireless_dev *wdev = cfg->wdev;
++	struct wiphy *wiphy = NULL;
++	if (!wdev) {
++		WL_ERR(("wdev is invalid\n"));
++		return;
++	}
++	if (wdev->wiphy) {
++		wiphy = wdev->wiphy;
++
++#if defined(WL_VENDOR_EXT_SUPPORT)
++		wl_cfgvendor_detach(wdev->wiphy);
++#endif /* if defined(WL_VENDOR_EXT_SUPPORT) */
++#ifdef CONFIG_PM
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++		/* Reset wowlan & wowlan_config before Unregister to avoid  Kernel Panic */
++		WL_DBG(("wl_free_wdev Clearing wowlan Config \n"));
++		wdev->wiphy->wowlan = NULL;
++		if (wdev->wiphy->wowlan_config) {
++			kfree(wdev->wiphy->wowlan_config);
++			wdev->wiphy->wowlan_config = NULL;
++		}
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0) */
++#endif /* CONFIG_PM */
++		wiphy_unregister(wdev->wiphy);
++		wdev->wiphy->dev.parent = NULL;
++		wdev->wiphy = NULL;
++	}
++
++	wl_delete_all_netinfo(cfg);
++	if (wiphy)
++		wiphy_free(wiphy);
++
++	/* PLEASE do NOT call any function after wiphy_free, the driver's private structure "cfg",
++	 * which is the private part of wiphy, has been freed in wiphy_free !!!!!!!!!!!
++	 */
++}
++
++static s32 wl_inform_bss(struct bcm_cfg80211 *cfg)
++{
++	struct wl_scan_results *bss_list;
++	struct wl_bss_info *bi = NULL;	/* must be initialized */
++	s32 err = 0;
++	s32 i;
++
++	bss_list = cfg->bss_list;
++	WL_DBG(("scanned AP count (%d)\n", bss_list->count));
++	bi = next_bss(bss_list, bi);
++	for_each_bss(bss_list, bi, i) {
++		err = wl_inform_single_bss(cfg, bi, false);
++		if (unlikely(err))
++			break;
++	}
++	return err;
++}
++
++static s32 wl_inform_single_bss(struct bcm_cfg80211 *cfg, struct wl_bss_info *bi, bool roam)
++{
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	struct ieee80211_mgmt *mgmt;
++	struct ieee80211_channel *channel;
++	struct ieee80211_supported_band *band;
++	struct wl_cfg80211_bss_info *notif_bss_info;
++	struct wl_scan_req *sr = wl_to_sr(cfg);
++	struct beacon_proberesp *beacon_proberesp;
++	struct cfg80211_bss *cbss = NULL;
++	s32 mgmt_type;
++	s32 signal;
++	u32 freq;
++	s32 err = 0;
++	gfp_t aflags;
++
++	if (unlikely(dtoh32(bi->length) > WL_BSS_INFO_MAX)) {
++		WL_DBG(("Beacon is larger than buffer. Discarding\n"));
++		return err;
++	}
++	aflags = (in_atomic()) ? GFP_ATOMIC : GFP_KERNEL;
++	notif_bss_info = kzalloc(sizeof(*notif_bss_info) + sizeof(*mgmt)
++		- sizeof(u8) + WL_BSS_INFO_MAX, aflags);
++	if (unlikely(!notif_bss_info)) {
++		WL_ERR(("notif_bss_info alloc failed\n"));
++		return -ENOMEM;
++	}
++	mgmt = (struct ieee80211_mgmt *)notif_bss_info->frame_buf;
++	notif_bss_info->channel =
++		wf_chspec_ctlchan(wl_chspec_driver_to_host(bi->chanspec));
++
++	if (notif_bss_info->channel <= CH_MAX_2G_CHANNEL)
++		band = wiphy->bands[IEEE80211_BAND_2GHZ];
++	else
++		band = wiphy->bands[IEEE80211_BAND_5GHZ];
++	if (!band) {
++		WL_ERR(("No valid band"));
++		kfree(notif_bss_info);
++		return -EINVAL;
++	}
++	notif_bss_info->rssi = wl_rssi_offset(dtoh16(bi->RSSI));
++	memcpy(mgmt->bssid, &bi->BSSID, ETHER_ADDR_LEN);
++	mgmt_type = cfg->active_scan ?
++		IEEE80211_STYPE_PROBE_RESP : IEEE80211_STYPE_BEACON;
++	if (!memcmp(bi->SSID, sr->ssid.SSID, bi->SSID_len)) {
++	    mgmt->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | mgmt_type);
++	}
++	beacon_proberesp = cfg->active_scan ?
++		(struct beacon_proberesp *)&mgmt->u.probe_resp :
++		(struct beacon_proberesp *)&mgmt->u.beacon;
++	beacon_proberesp->timestamp = 0;
++	beacon_proberesp->beacon_int = cpu_to_le16(bi->beacon_period);
++	beacon_proberesp->capab_info = cpu_to_le16(bi->capability);
++	wl_rst_ie(cfg);
++	wl_update_hidden_ap_ie(bi, ((u8 *) bi) + bi->ie_offset, &bi->ie_length, roam);
++	wl_mrg_ie(cfg, ((u8 *) bi) + bi->ie_offset, bi->ie_length);
++	wl_cp_ie(cfg, beacon_proberesp->variable, WL_BSS_INFO_MAX -
++		offsetof(struct wl_cfg80211_bss_info, frame_buf));
++	notif_bss_info->frame_len = offsetof(struct ieee80211_mgmt,
++		u.beacon.variable) + wl_get_ielen(cfg);
++#if LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 38)
++	freq = ieee80211_channel_to_frequency(notif_bss_info->channel);
++	(void)band->band;
++#else
++	freq = ieee80211_channel_to_frequency(notif_bss_info->channel, band->band);
++#endif
++	if (freq == 0) {
++		WL_ERR(("Invalid channel, fail to chcnage channel to freq\n"));
++		kfree(notif_bss_info);
++		return -EINVAL;
++	}
++	channel = ieee80211_get_channel(wiphy, freq);
++	if (unlikely(!channel)) {
++		WL_ERR(("ieee80211_get_channel error\n"));
++		kfree(notif_bss_info);
++		return -EINVAL;
++	}
++	WL_DBG(("SSID : \"%s\", rssi %d, channel %d, capability : 0x04%x, bssid %pM"
++			"mgmt_type %d frame_len %d\n", bi->SSID,
++			notif_bss_info->rssi, notif_bss_info->channel,
++			mgmt->u.beacon.capab_info, &bi->BSSID, mgmt_type,
++			notif_bss_info->frame_len));
++
++	signal = notif_bss_info->rssi * 100;
++	if (!mgmt->u.probe_resp.timestamp) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39))
++		struct timespec64 ts;
++                getboottime64(&ts);
++		mgmt->u.probe_resp.timestamp = ((u64)ts.tv_sec*1000000)
++				+ ts.tv_nsec / 1000;
++#else
++		struct timeval tv;
++		do_gettimeofday(&tv);
++		mgmt->u.probe_resp.timestamp = ((u64)tv.tv_sec*1000000)
++				+ tv.tv_usec;
++#endif
++	}
++
++
++	cbss = cfg80211_inform_bss_frame(wiphy, channel, mgmt,
++		le16_to_cpu(notif_bss_info->frame_len), signal, aflags);
++	if (unlikely(!cbss)) {
++		WL_ERR(("cfg80211_inform_bss_frame error\n"));
++		kfree(notif_bss_info);
++		return -EINVAL;
++	}
++
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++	cfg80211_put_bss(wiphy, cbss);
++#else
++	cfg80211_put_bss(cbss);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) */
++	kfree(notif_bss_info);
++	return err;
++}
++
++static bool wl_is_linkup(struct bcm_cfg80211 *cfg, const wl_event_msg_t *e, struct net_device *ndev)
++{
++	u32 event = ntoh32(e->event_type);
++	u32 status =  ntoh32(e->status);
++	u16 flags = ntoh16(e->flags);
++
++	WL_DBG(("event %d, status %d flags %x\n", event, status, flags));
++	if (event == WLC_E_SET_SSID) {
++		if (status == WLC_E_STATUS_SUCCESS) {
++			if (!wl_is_ibssmode(cfg, ndev))
++				return true;
++		}
++	} else if (event == WLC_E_LINK) {
++		if (flags & WLC_EVENT_MSG_LINK)
++			return true;
++	}
++
++	WL_DBG(("wl_is_linkup false\n"));
++	return false;
++}
++
++static bool wl_is_linkdown(struct bcm_cfg80211 *cfg, const wl_event_msg_t *e)
++{
++	u32 event = ntoh32(e->event_type);
++	u16 flags = ntoh16(e->flags);
++
++	if (event == WLC_E_DEAUTH_IND ||
++	event == WLC_E_DISASSOC_IND ||
++	event == WLC_E_DISASSOC ||
++	event == WLC_E_DEAUTH) {
++#if (WL_DBG_LEVEL > 0)
++	WL_ERR(("Link down Reason : WLC_E_%s\n", wl_dbg_estr[event]));
++#endif /* (WL_DBG_LEVEL > 0) */
++		return true;
++	} else if (event == WLC_E_LINK) {
++		if (!(flags & WLC_EVENT_MSG_LINK)) {
++#if (WL_DBG_LEVEL > 0)
++	WL_ERR(("Link down Reason : WLC_E_%s\n", wl_dbg_estr[event]));
++#endif /* (WL_DBG_LEVEL > 0) */
++			return true;
++		}
++	}
++
++	return false;
++}
++
++static bool wl_is_nonetwork(struct bcm_cfg80211 *cfg, const wl_event_msg_t *e)
++{
++	u32 event = ntoh32(e->event_type);
++	u32 status = ntoh32(e->status);
++
++	if (event == WLC_E_LINK && status == WLC_E_STATUS_NO_NETWORKS)
++		return true;
++	if (event == WLC_E_SET_SSID && status != WLC_E_STATUS_SUCCESS)
++		return true;
++
++	return false;
++}
++
++/* The mainline kernel >= 3.2.0 has support for indicating new/del station
++ * to AP/P2P GO via events. If this change is backported to kernel for which
++ * this driver is being built, then define WL_CFG80211_STA_EVENT. You
++ * should use this new/del sta event mechanism for BRCM supplicant >= 22.
++ */
++static s32
++wl_notify_connect_status_ap(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data)
++{
++	s32 err = 0;
++	u32 event = ntoh32(e->event_type);
++	u32 reason = ntoh32(e->reason);
++	u32 len = ntoh32(e->datalen);
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0)) && !defined(WL_CFG80211_STA_EVENT)
++	bool isfree = false;
++	u8 *mgmt_frame;
++	u8 bsscfgidx = e->bsscfgidx;
++	s32 freq;
++	s32 channel;
++	u8 *body = NULL;
++	u16 fc = 0;
++
++	struct ieee80211_supported_band *band;
++	struct ether_addr da;
++	struct ether_addr bssid;
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	channel_info_t ci;
++#else
++	struct station_info sinfo;
++#endif 
++
++	WL_DBG(("event %d status %d reason %d\n", event, ntoh32(e->status), reason));
++	/* if link down, bsscfg is disabled. */
++	if (event == WLC_E_LINK && reason == WLC_E_LINK_BSSCFG_DIS &&
++		wl_get_p2p_status(cfg, IF_DELETING) && (ndev != bcmcfg_to_prmry_ndev(cfg))) {
++		wl_add_remove_eventmsg(ndev, WLC_E_PROBREQ_MSG, false);
++		WL_INFORM(("AP mode link down !! \n"));
++		complete(&cfg->iface_disable);
++		return 0;
++	}
++
++	if (event == WLC_E_DISASSOC_IND || event == WLC_E_DEAUTH_IND || event == WLC_E_DEAUTH) {
++		WL_ERR(("event %s(%d) status %d reason %d\n",
++		bcmevent_get_name(event), event, ntoh32(e->status), reason));
++	}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0)) && !defined(WL_CFG80211_STA_EVENT)
++	WL_DBG(("Enter \n"));
++	if (!len && (event == WLC_E_DEAUTH)) {
++		len = 2; /* reason code field */
++		data = &reason;
++	}
++	if (len) {
++		body = kzalloc(len, GFP_KERNEL);
++
++		if (body == NULL) {
++			WL_ERR(("wl_notify_connect_status: Failed to allocate body\n"));
++			return WL_INVALID;
++		}
++	}
++	memset(&bssid, 0, ETHER_ADDR_LEN);
++	WL_DBG(("Enter event %d ndev %p\n", event, ndev));
++	if (wl_get_mode_by_netdev(cfg, ndev) == WL_INVALID) {
++		kfree(body);
++		return WL_INVALID;
++	}
++	if (len)
++		memcpy(body, data, len);
++
++	wldev_iovar_getbuf_bsscfg(ndev, "cur_etheraddr",
++		NULL, 0, cfg->ioctl_buf, WLC_IOCTL_SMLEN, bsscfgidx, &cfg->ioctl_buf_sync);
++	memcpy(da.octet, cfg->ioctl_buf, ETHER_ADDR_LEN);
++	memset(&bssid, 0, sizeof(bssid));
++	err = wldev_ioctl(ndev, WLC_GET_BSSID, &bssid, ETHER_ADDR_LEN, false);
++	switch (event) {
++		case WLC_E_ASSOC_IND:
++			fc = FC_ASSOC_REQ;
++			break;
++		case WLC_E_REASSOC_IND:
++			fc = FC_REASSOC_REQ;
++			break;
++		case WLC_E_DISASSOC_IND:
++			fc = FC_DISASSOC;
++			break;
++		case WLC_E_DEAUTH_IND:
++			fc = FC_DISASSOC;
++			break;
++		case WLC_E_DEAUTH:
++			fc = FC_DISASSOC;
++			break;
++		default:
++			fc = 0;
++			goto exit;
++	}
++	memset(&ci, 0, sizeof(ci));
++	if ((err = wldev_ioctl(ndev, WLC_GET_CHANNEL, &ci, sizeof(ci), false))) {
++		kfree(body);
++		return err;
++	}
++
++	channel = dtoh32(ci.hw_channel);
++	if (channel <= CH_MAX_2G_CHANNEL)
++		band = wiphy->bands[IEEE80211_BAND_2GHZ];
++	else
++		band = wiphy->bands[IEEE80211_BAND_5GHZ];
++	if (!band) {
++		WL_ERR(("No valid band"));
++		if (body)
++			kfree(body);
++		return -EINVAL;
++	}
++#if LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 38)
++	freq = ieee80211_channel_to_frequency(channel);
++	(void)band->band;
++#else
++	freq = ieee80211_channel_to_frequency(channel, band->band);
++#endif
++
++	err = wl_frame_get_mgmt(fc, &da, &e->addr, &bssid,
++		&mgmt_frame, &len, body);
++	if (err < 0)
++		goto exit;
++	isfree = true;
++
++	if (event == WLC_E_ASSOC_IND && reason == DOT11_SC_SUCCESS) {
++#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) && (LINUX_VERSION_CODE < \
++	KERNEL_VERSION(3, 18, 0)))
++		cfg80211_rx_mgmt(ndev, freq, 0, mgmt_frame, len, GFP_ATOMIC);
++
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
++		cfg80211_rx_mgmt(ndev, freq, 0, mgmt_frame, len);
++#else
++		cfg80211_rx_mgmt(ndev, freq, mgmt_frame, len, GFP_ATOMIC);
++#endif 
++	} else if (event == WLC_E_DISASSOC_IND) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
++		cfg80211_rx_mgmt(ndev, freq, 0, mgmt_frame, len, GFP_ATOMIC);
++#else
++		cfg80211_rx_mgmt(ndev, freq, mgmt_frame, len, GFP_ATOMIC);
++#endif 
++	} else if ((event == WLC_E_DEAUTH_IND) || (event == WLC_E_DEAUTH)) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
++		cfg80211_rx_mgmt(ndev, freq, 0, mgmt_frame, len, GFP_ATOMIC);
++#else
++		cfg80211_rx_mgmt(ndev, freq, mgmt_frame, len, GFP_ATOMIC);
++#endif 
++	}
++
++exit:
++	if (isfree)
++		kfree(mgmt_frame);
++	if (body)
++		kfree(body);
++#else /* LINUX_VERSION < VERSION(3,2,0) && !WL_CFG80211_STA_EVENT && !WL_COMPAT_WIRELESS */
++	sinfo.filled = 0;
++	if (((event == WLC_E_ASSOC_IND) || (event == WLC_E_REASSOC_IND)) &&
++			reason == DOT11_SC_SUCCESS) {
++		/* Linux ver >= 4.0 assoc_req_ies_len is used instead of
++		 * STATION_INFO_ASSOC_REQ_IES flag
++		 */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))
++		sinfo.filled = STA_INFO_BIT(INFO_ASSOC_REQ_IES);
++#endif /*  (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) */
++		if (!data) {
++			WL_ERR(("No IEs present in ASSOC/REASSOC_IND"));
++			return -EINVAL;
++		}
++		sinfo.assoc_req_ies = data;
++		sinfo.assoc_req_ies_len = len;
++		cfg80211_new_sta(ndev, e->addr.octet, &sinfo, GFP_ATOMIC);
++	} else if (event == WLC_E_DISASSOC_IND) {
++		cfg80211_del_sta(ndev, e->addr.octet, GFP_ATOMIC);
++	} else if ((event == WLC_E_DEAUTH_IND) || (event == WLC_E_DEAUTH)) {
++		cfg80211_del_sta(ndev, e->addr.octet, GFP_ATOMIC);
++	}
++#endif 
++	return err;
++}
++
++static s32
++wl_get_auth_assoc_status(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e)
++{
++	u32 reason = ntoh32(e->reason);
++	u32 event = ntoh32(e->event_type);
++	struct wl_security *sec = wl_read_prof(cfg, ndev, WL_PROF_SEC);
++	WL_DBG(("event type : %d, reason : %d\n", event, reason));
++	if (sec) {
++		switch (event) {
++		case WLC_E_ASSOC:
++		case WLC_E_AUTH:
++				sec->auth_assoc_res_status = reason;
++		default:
++			break;
++		}
++	} else
++		WL_ERR(("sec is NULL\n"));
++	return 0;
++}
++
++static s32
++wl_notify_connect_status_ibss(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data)
++{
++	s32 err = 0;
++	u32 event = ntoh32(e->event_type);
++	u16 flags = ntoh16(e->flags);
++	u32 status =  ntoh32(e->status);
++	bool active;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)
++	struct ieee80211_channel *channel = NULL;
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	u32 chanspec, chan;
++	u32 freq, band;
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0) */
++
++	if (event == WLC_E_JOIN) {
++		WL_DBG(("joined in IBSS network\n"));
++	}
++	if (event == WLC_E_START) {
++		WL_DBG(("started IBSS network\n"));
++	}
++	if (event == WLC_E_JOIN || event == WLC_E_START ||
++		(event == WLC_E_LINK && (flags == WLC_EVENT_MSG_LINK))) {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)
++		err = wldev_iovar_getint(ndev, "chanspec", (s32 *)&chanspec);
++		if (unlikely(err)) {
++			WL_ERR(("Could not get chanspec %d\n", err));
++			return err;
++		}
++		chan = wf_chspec_ctlchan(wl_chspec_driver_to_host(chanspec));
++		band = (chan <= CH_MAX_2G_CHANNEL) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
++		freq = ieee80211_channel_to_frequency(chan, band);
++		channel = ieee80211_get_channel(wiphy, freq);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0) */
++		if (wl_get_drv_status(cfg, CONNECTED, ndev)) {
++			/* ROAM or Redundant */
++			u8 *cur_bssid = wl_read_prof(cfg, ndev, WL_PROF_BSSID);
++			if (memcmp(cur_bssid, &e->addr, ETHER_ADDR_LEN) == 0) {
++				WL_DBG(("IBSS connected event from same BSSID("
++					MACDBG "), ignore it\n", MAC2STRDBG(cur_bssid)));
++				return err;
++			}
++			WL_INFORM(("IBSS BSSID is changed from " MACDBG " to " MACDBG "\n",
++				MAC2STRDBG(cur_bssid), MAC2STRDBG((const u8 *)&e->addr)));
++			wl_get_assoc_ies(cfg, ndev);
++			wl_update_prof(cfg, ndev, NULL, (const void *)&e->addr, WL_PROF_BSSID);
++			wl_update_bss_info(cfg, ndev, false);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)
++			cfg80211_ibss_joined(ndev, (const s8 *)&e->addr, channel, GFP_KERNEL);
++#else
++			cfg80211_ibss_joined(ndev, (const s8 *)&e->addr, GFP_KERNEL);
++#endif
++		}
++		else {
++			/* New connection */
++			WL_INFORM(("IBSS connected to " MACDBG "\n",
++				MAC2STRDBG((const u8 *)&e->addr)));
++			wl_link_up(cfg);
++			wl_get_assoc_ies(cfg, ndev);
++			wl_update_prof(cfg, ndev, NULL, (const void *)&e->addr, WL_PROF_BSSID);
++			wl_update_bss_info(cfg, ndev, false);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)
++			cfg80211_ibss_joined(ndev, (const s8 *)&e->addr, channel, GFP_KERNEL);
++#else
++			cfg80211_ibss_joined(ndev, (const s8 *)&e->addr, GFP_KERNEL);
++#endif
++			wl_set_drv_status(cfg, CONNECTED, ndev);
++			active = true;
++			wl_update_prof(cfg, ndev, NULL, (const void *)&active, WL_PROF_ACT);
++		}
++	} else if ((event == WLC_E_LINK && !(flags & WLC_EVENT_MSG_LINK)) ||
++		event == WLC_E_DEAUTH_IND || event == WLC_E_DISASSOC_IND) {
++		wl_clr_drv_status(cfg, CONNECTED, ndev);
++		wl_link_down(cfg);
++		wl_init_prof(cfg, ndev);
++	}
++	else if (event == WLC_E_SET_SSID && status == WLC_E_STATUS_NO_NETWORKS) {
++		WL_DBG(("no action - join fail (IBSS mode)\n"));
++	}
++	else {
++		WL_DBG(("no action (IBSS mode)\n"));
++}
++	return err;
++}
++
++static s32
++wl_notify_connect_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	bool act;
++	struct net_device *ndev = NULL;
++	s32 err = 0;
++	u32 event = ntoh32(e->event_type);
++	struct wiphy *wiphy = NULL;
++	struct cfg80211_bss *bss = NULL;
++	struct wlc_ssid *ssid = NULL;
++	u8 *bssid = 0;
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	if (wl_get_mode_by_netdev(cfg, ndev) == WL_MODE_AP) {
++		err = wl_notify_connect_status_ap(cfg, ndev, e, data);
++	} else if (wl_get_mode_by_netdev(cfg, ndev) == WL_MODE_IBSS) {
++		err = wl_notify_connect_status_ibss(cfg, ndev, e, data);
++	} else if (wl_get_mode_by_netdev(cfg, ndev) == WL_MODE_BSS) {
++		WL_DBG(("wl_notify_connect_status : event %d status : %d ndev %p\n",
++			ntoh32(e->event_type), ntoh32(e->status), ndev));
++		if (event == WLC_E_ASSOC || event == WLC_E_AUTH) {
++			wl_get_auth_assoc_status(cfg, ndev, e);
++			return 0;
++		}
++		if (wl_is_linkup(cfg, e, ndev)) {
++			wl_link_up(cfg);
++			act = true;
++			if (!wl_get_drv_status(cfg, DISCONNECTING, ndev)) {
++#ifdef DHD_LOSSLESS_ROAMING
++					bool is_connected = wl_get_drv_status(cfg, CONNECTED, ndev);
++#endif
++
++					printk("wl_bss_connect_done succeeded with " MACDBG "\n",
++						MAC2STRDBG((const u8*)(&e->addr)));
++					wl_bss_connect_done(cfg, ndev, e, data, true);
++					WL_DBG(("joined in BSS network \"%s\"\n",
++					((struct wlc_ssid *)
++					 wl_read_prof(cfg, ndev, WL_PROF_SSID))->SSID));
++#ifdef DHD_LOSSLESS_ROAMING
++					if (event == WLC_E_LINK && is_connected &&
++							!cfg->roam_offload) {
++						wl_bss_roaming_done(cfg, ndev, e, data);
++					}
++#endif /* DHD_LOSSLESS_ROAMING */
++
++				}
++			wl_update_prof(cfg, ndev, e, &act, WL_PROF_ACT);
++			wl_update_prof(cfg, ndev, NULL, (const void *)&e->addr, WL_PROF_BSSID);
++
++		} else if (wl_is_linkdown(cfg, e)) {
++#ifdef DHD_LOSSLESS_ROAMING
++			wl_del_roam_timeout(cfg);
++#endif
++#ifdef P2PLISTEN_AP_SAMECHN
++			if (ndev == bcmcfg_to_prmry_ndev(cfg)) {
++				wl_cfg80211_set_p2p_resp_ap_chn(ndev, 0);
++				cfg->p2p_resp_apchn_status = false;
++				WL_DBG(("p2p_resp_apchn_status Turn OFF \n"));
++			}
++#endif /* P2PLISTEN_AP_SAMECHN */
++			wl_cfg80211_cancel_scan(cfg);
++
++			/* Explicitly calling unlink to remove BSS in CFG */
++			if (wl_cfgp2p_vif_created(cfg)) {
++				wiphy = bcmcfg_to_wiphy(cfg);
++				ssid = (struct wlc_ssid *)wl_read_prof(cfg, ndev, WL_PROF_SSID);
++				bssid = (u8 *)wl_read_prof(cfg, ndev, WL_PROF_BSSID);
++				if (ssid && bssid) {
++					bss = cfg80211_get_bss(wiphy, NULL, bssid,
++						ssid->SSID, ssid->SSID_len, WLAN_CAPABILITY_ESS,
++						WLAN_CAPABILITY_ESS);
++					if (bss) {
++						cfg80211_unlink_bss(wiphy, bss);
++					}
++				}
++			}
++
++			if (wl_get_drv_status(cfg, CONNECTED, ndev)) {
++				scb_val_t scbval;
++				u8 *curbssid = wl_read_prof(cfg, ndev, WL_PROF_BSSID);
++				s32 reason = 0;
++				struct ether_addr bssid_dongle;
++
++				if (event == WLC_E_DEAUTH_IND || event == WLC_E_DISASSOC_IND)
++					reason = ntoh32(e->reason);
++				/* WLAN_REASON_UNSPECIFIED is used for hang up event in Android */
++				reason = (reason == WLAN_REASON_UNSPECIFIED)? 0 : reason;
++
++				printk("link down if %s may call cfg80211_disconnected. "
++					"event : %d, reason=%d from " MACDBG "\n",
++					ndev->name, event, ntoh32(e->reason),
++					MAC2STRDBG((const u8*)(&e->addr)));
++
++				/* roam offload does not sync BSSID always, get it from dongle */
++				if (cfg->roam_offload) {
++					memset(&bssid_dongle, 0, sizeof(bssid_dongle));
++					if (wldev_ioctl(ndev, WLC_GET_BSSID, &bssid_dongle,
++							sizeof(bssid_dongle), false) == BCME_OK) {
++						curbssid = (u8 *)&bssid_dongle;
++					}
++				}
++				if (memcmp(curbssid, &e->addr, ETHER_ADDR_LEN) != 0) {
++					WL_ERR(("BSSID of event is not the connected BSSID"
++						"(ignore it) cur: " MACDBG " event: " MACDBG"\n",
++						MAC2STRDBG(curbssid),
++						MAC2STRDBG((const u8*)(&e->addr))));
++					return 0;
++				}
++				wl_clr_drv_status(cfg, CONNECTED, ndev);
++				if (! wl_get_drv_status(cfg, DISCONNECTING, ndev)) {
++					/* To make sure disconnect, explictly send dissassoc
++					*  for BSSID 00:00:00:00:00:00 issue
++					*/
++					scbval.val = WLAN_REASON_DEAUTH_LEAVING;
++
++					memcpy(&scbval.ea, curbssid, ETHER_ADDR_LEN);
++					scbval.val = htod32(scbval.val);
++					err = wldev_ioctl(ndev, WLC_DISASSOC, &scbval,
++						sizeof(scb_val_t), true);
++					if (err < 0) {
++						WL_ERR(("WLC_DISASSOC error %d\n", err));
++						err = 0;
++					}
++					CFG80211_DISCONNECTED(ndev, reason, NULL, 0,
++							false, GFP_KERNEL);
++					wl_link_down(cfg);
++					wl_init_prof(cfg, ndev);
++					memset(&cfg->last_roamed_addr, 0, ETHER_ADDR_LEN);
++				}
++			}
++			else if (wl_get_drv_status(cfg, CONNECTING, ndev)) {
++				printk("link down, during connecting\n");
++#ifdef ESCAN_RESULT_PATCH
++				if ((memcmp(connect_req_bssid, broad_bssid, ETHER_ADDR_LEN) == 0) ||
++					(memcmp(&e->addr, broad_bssid, ETHER_ADDR_LEN) == 0) ||
++					(memcmp(&e->addr, connect_req_bssid, ETHER_ADDR_LEN) == 0))
++					/* In case this event comes while associating another AP */
++#endif /* ESCAN_RESULT_PATCH */
++					wl_bss_connect_done(cfg, ndev, e, data, false);
++			}
++			wl_clr_drv_status(cfg, DISCONNECTING, ndev);
++
++			/* if link down, bsscfg is diabled */
++			if (ndev != bcmcfg_to_prmry_ndev(cfg))
++				complete(&cfg->iface_disable);
++
++		} else if (wl_is_nonetwork(cfg, e)) {
++			printk("connect failed event=%d e->status %d e->reason %d \n",
++				event, (int)ntoh32(e->status), (int)ntoh32(e->reason));
++			/* Clean up any pending scan request */
++			wl_cfg80211_cancel_scan(cfg);
++			if (wl_get_drv_status(cfg, CONNECTING, ndev))
++				wl_bss_connect_done(cfg, ndev, e, data, false);
++		} else {
++			WL_DBG(("%s nothing\n", __FUNCTION__));
++		}
++	}
++		else {
++		WL_ERR(("Invalid ndev status %d\n", wl_get_mode_by_netdev(cfg, ndev)));
++	}
++	return err;
++}
++
++void wl_cfg80211_set_rmc_pid(int pid)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	if (pid > 0)
++		cfg->rmc_event_pid = pid;
++	WL_DBG(("set pid for rmc event : pid=%d\n", pid));
++}
++
++#ifdef WL_RELMCAST
++static s32
++wl_notify_rmc_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	u32 evt = ntoh32(e->event_type);
++	u32 reason = ntoh32(e->reason);
++	int ret = -1;
++
++	switch (reason) {
++		case WLC_E_REASON_RMC_AR_LOST:
++		case WLC_E_REASON_RMC_AR_NO_ACK:
++			if (cfg->rmc_event_pid != 0) {
++				ret = wl_netlink_send_msg(cfg->rmc_event_pid,
++					RMC_EVENT_LEADER_CHECK_FAIL,
++					cfg->rmc_event_seq++, NULL, 0);
++			}
++			break;
++		default:
++			break;
++	}
++	WL_DBG(("rmcevent : evt=%d, pid=%d, ret=%d\n", evt, cfg->rmc_event_pid, ret));
++	return ret;
++}
++#endif /* WL_RELMCAST */
++
++#ifdef GSCAN_SUPPORT
++static s32
++wl_handle_roam_exp_event(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	struct net_device *ndev = NULL;
++	u32 datalen = be32_to_cpu(e->datalen);
++
++	if (datalen) {
++		wl_roam_exp_event_t *evt_data = (wl_roam_exp_event_t *)data;
++		if (evt_data->version == ROAM_EXP_EVENT_VERSION) {
++			wlc_ssid_t *ssid = &evt_data->cur_ssid;
++			struct wireless_dev *wdev;
++			ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++			if (ndev) {
++				wdev = ndev->ieee80211_ptr;
++				wdev->ssid_len = min(ssid->SSID_len, (uint32)DOT11_MAX_SSID_LEN);
++				memcpy(wdev->ssid, ssid->SSID, wdev->ssid_len);
++				WL_ERR(("SSID is %s\n", ssid->SSID));
++				wl_update_prof(cfg, ndev, NULL, ssid, WL_PROF_SSID);
++			} else {
++				WL_ERR(("NULL ndev!\n"));
++			}
++		} else {
++			WL_ERR(("Version mismatch %d, expected %d", evt_data->version,
++			       ROAM_EXP_EVENT_VERSION));
++		}
++	}
++	return BCME_OK;
++}
++#endif /* GSCAN_SUPPORT */
++
++static s32 wl_handle_rssi_monitor_event(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++
++#if defined(WL_VENDOR_EXT_SUPPORT) || defined(CONFIG_BCMDHD_VENDOR_EXT)
++	u32 datalen = be32_to_cpu(e->datalen);
++	struct net_device *ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	if (datalen) {
++		wl_rssi_monitor_evt_t *evt_data = (wl_rssi_monitor_evt_t *)data;
++		if (evt_data->version == RSSI_MONITOR_VERSION) {
++			dhd_rssi_monitor_evt_t monitor_data;
++			monitor_data.version = DHD_RSSI_MONITOR_EVT_VERSION;
++			monitor_data.cur_rssi = evt_data->cur_rssi;
++			memcpy(&monitor_data.BSSID, &e->addr, ETHER_ADDR_LEN);
++			wl_cfgvendor_send_async_event(wiphy, ndev,
++				GOOGLE_RSSI_MONITOR_EVENT,
++				&monitor_data, sizeof(monitor_data));
++		} else {
++			WL_ERR(("Version mismatch %d, expected %d", evt_data->version,
++			       RSSI_MONITOR_VERSION));
++		}
++	}
++#endif /* WL_VENDOR_EXT_SUPPORT || CONFIG_BCMDHD_VENDOR_EXT */
++	return BCME_OK;
++}
++
++static s32
++wl_notify_roaming_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	bool act;
++	struct net_device *ndev = NULL;
++	s32 err = 0;
++	u32 event = be32_to_cpu(e->event_type);
++	u32 status = be32_to_cpu(e->status);
++#ifdef DHD_LOSSLESS_ROAMING
++	struct wl_security *sec;
++#endif
++	WL_DBG(("Enter \n"));
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	if ((!cfg->disable_roam_event) && (event == WLC_E_BSSID)) {
++		wl_add_remove_eventmsg(ndev, WLC_E_ROAM, false);
++		cfg->disable_roam_event = TRUE;
++	}
++
++	if ((cfg->disable_roam_event) && (event == WLC_E_ROAM))
++		return err;
++
++	if ((event == WLC_E_ROAM || event == WLC_E_BSSID) && status == WLC_E_STATUS_SUCCESS) {
++		if (wl_get_drv_status(cfg, CONNECTED, ndev)) {
++			if (cfg->roam_offload &&
++				memcmp(&cfg->last_roamed_addr, &e->addr, ETHER_ADDR_LEN) == 0) {
++				WL_INFORM(("BSSID already updated\n"));
++				return err;
++			}
++#ifdef DHD_LOSSLESS_ROAMING
++			if (cfg->roam_offload) {
++				wl_bss_roaming_done(cfg, ndev, e, data);
++				wl_del_roam_timeout(cfg);
++			}
++			else {
++				sec = wl_read_prof(cfg, ndev, WL_PROF_SEC);
++				/* In order to reduce roaming delay, wl_bss_roaming_done is
++				 * early called with WLC_E_LINK event. It is called from
++				 * here only if WLC_E_LINK event is blocked for specific
++				 * security type.
++				 */
++				if (IS_AKM_SUITE_FT(sec)) {
++					wl_bss_roaming_done(cfg, ndev, e, data);
++				}
++				/* Roam timer is deleted mostly from wl_cfg80211_change_station
++				 * after roaming is finished successfully. We need to delete
++				 * the timer from here only for some security types that aren't
++				 * using wl_cfg80211_change_station to authorize SCB
++				 */
++				if (IS_AKM_SUITE_FT(sec) || IS_AKM_SUITE_CCKM(sec)) {
++					wl_del_roam_timeout(cfg);
++				}
++			}
++#else
++			wl_bss_roaming_done(cfg, ndev, e, data);
++#endif /* DHD_LOSSLESS_ROAMING */
++			memcpy(&cfg->last_roamed_addr, (void *)&e->addr, ETHER_ADDR_LEN);
++		} else {
++			wl_bss_connect_done(cfg, ndev, e, data, true);
++		}
++		act = true;
++		wl_update_prof(cfg, ndev, e, &act, WL_PROF_ACT);
++		wl_update_prof(cfg, ndev, NULL, (const void *)&e->addr, WL_PROF_BSSID);
++	}
++#ifdef DHD_LOSSLESS_ROAMING
++	else if ((event == WLC_E_ROAM || event == WLC_E_BSSID) && status != WLC_E_STATUS_SUCCESS) {
++		wl_del_roam_timeout(cfg);
++	}
++#endif
++	return err;
++}
++
++#ifdef QOS_MAP_SET
++/* get user priority table */
++uint8 *
++wl_get_up_table(void)
++{
++	return (uint8 *)(g_bcm_cfg->up_table);
++}
++#endif /* QOS_MAP_SET */
++
++#ifdef DHD_LOSSLESS_ROAMING
++static s32
++wl_notify_roam_prep_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	s32 err = 0;
++
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++
++	dhdp->dequeue_prec_map = 1 << PRIO_8021D_NC;
++	/* Restore flow control  */
++	dhd_txflowcontrol(dhdp, ALL_INTERFACES, OFF);
++
++	mod_timer(&cfg->roam_timeout, jiffies + msecs_to_jiffies(WL_ROAM_TIMEOUT_MS));
++
++	return err;
++}
++#endif /* DHD_LOSSLESS_ROAMING */
++
++static s32 wl_get_assoc_ies(struct bcm_cfg80211 *cfg, struct net_device *ndev)
++{
++	wl_assoc_info_t assoc_info;
++	struct wl_connect_info *conn_info = wl_to_conn(cfg);
++	s32 err = 0;
++#ifdef QOS_MAP_SET
++	bcm_tlv_t * qos_map_ie = NULL;
++#endif /* QOS_MAP_SET */
++
++	WL_DBG(("Enter \n"));
++	err = wldev_iovar_getbuf(ndev, "assoc_info", NULL, 0, cfg->extra_buf,
++		WL_ASSOC_INFO_MAX, NULL);
++	if (unlikely(err)) {
++		WL_ERR(("could not get assoc info (%d)\n", err));
++		return err;
++	}
++	memcpy(&assoc_info, cfg->extra_buf, sizeof(wl_assoc_info_t));
++	assoc_info.req_len = htod32(assoc_info.req_len);
++	assoc_info.resp_len = htod32(assoc_info.resp_len);
++	assoc_info.flags = htod32(assoc_info.flags);
++	if (conn_info->req_ie_len) {
++		conn_info->req_ie_len = 0;
++		bzero(conn_info->req_ie, sizeof(conn_info->req_ie));
++	}
++	if (conn_info->resp_ie_len) {
++		conn_info->resp_ie_len = 0;
++		bzero(conn_info->resp_ie, sizeof(conn_info->resp_ie));
++	}
++	if (assoc_info.req_len) {
++		err = wldev_iovar_getbuf(ndev, "assoc_req_ies", NULL, 0, cfg->extra_buf,
++			WL_ASSOC_INFO_MAX, NULL);
++		if (unlikely(err)) {
++			WL_ERR(("could not get assoc req (%d)\n", err));
++			return err;
++		}
++		conn_info->req_ie_len = assoc_info.req_len - sizeof(struct dot11_assoc_req);
++		if (assoc_info.flags & WLC_ASSOC_REQ_IS_REASSOC) {
++			conn_info->req_ie_len -= ETHER_ADDR_LEN;
++		}
++		if (conn_info->req_ie_len <= MAX_REQ_LINE)
++			memcpy(conn_info->req_ie, cfg->extra_buf, conn_info->req_ie_len);
++		else {
++			WL_ERR(("IE size %d above max %d size \n",
++				conn_info->req_ie_len, MAX_REQ_LINE));
++			return err;
++		}
++	} else {
++		conn_info->req_ie_len = 0;
++	}
++	if (assoc_info.resp_len) {
++		err = wldev_iovar_getbuf(ndev, "assoc_resp_ies", NULL, 0, cfg->extra_buf,
++			WL_ASSOC_INFO_MAX, NULL);
++		if (unlikely(err)) {
++			WL_ERR(("could not get assoc resp (%d)\n", err));
++			return err;
++		}
++		conn_info->resp_ie_len = assoc_info.resp_len -sizeof(struct dot11_assoc_resp);
++		if (conn_info->resp_ie_len <= MAX_REQ_LINE) {
++			memcpy(conn_info->resp_ie, cfg->extra_buf, conn_info->resp_ie_len);
++		} else {
++			WL_ERR(("IE size %d above max %d size \n",
++				conn_info->resp_ie_len, MAX_REQ_LINE));
++			return err;
++		}
++
++#ifdef QOS_MAP_SET
++		/* find qos map set ie */
++		if ((qos_map_ie = bcm_parse_tlvs(conn_info->resp_ie, conn_info->resp_ie_len,
++				DOT11_MNG_QOS_MAP_ID)) != NULL) {
++			WL_DBG((" QoS map set IE found in assoc response\n"));
++			if (!cfg->up_table) {
++				cfg->up_table = kmalloc(UP_TABLE_MAX, GFP_KERNEL);
++			}
++			wl_set_up_table(cfg->up_table, qos_map_ie);
++		} else {
++			kfree(cfg->up_table);
++			cfg->up_table = NULL;
++		}
++#endif /* QOS_MAP_SET */
++	} else {
++		conn_info->resp_ie_len = 0;
++	}
++	WL_DBG(("req len (%d) resp len (%d)\n", conn_info->req_ie_len,
++		conn_info->resp_ie_len));
++
++	return err;
++}
++
++static s32 wl_ch_to_chanspec(struct net_device *dev, int ch, struct wl_join_params *join_params,
++        size_t *join_params_size)
++{
++	struct bcm_cfg80211 *cfg;
++	s32 bssidx = -1;
++	chanspec_t chanspec = 0, chspec;
++
++	if (ch != 0) {
++		cfg = (struct bcm_cfg80211 *)wiphy_priv(dev->ieee80211_ptr->wiphy);
++			join_params->params.chanspec_num = 1;
++			join_params->params.chanspec_list[0] = ch;
++
++			if (join_params->params.chanspec_list[0] <= CH_MAX_2G_CHANNEL)
++				chanspec |= WL_CHANSPEC_BAND_2G;
++			else
++				chanspec |= WL_CHANSPEC_BAND_5G;
++
++			/* Get the min_bw set for the interface */
++			chspec = wl_cfg80211_ulb_get_min_bw_chspec(dev->ieee80211_ptr, bssidx);
++			if (chspec == INVCHANSPEC) {
++				WL_ERR(("Invalid chanspec \n"));
++				return -EINVAL;
++			}
++			chanspec |= chspec;
++			chanspec |= WL_CHANSPEC_CTL_SB_NONE;
++
++			*join_params_size += WL_ASSOC_PARAMS_FIXED_SIZE +
++				join_params->params.chanspec_num * sizeof(chanspec_t);
++
++			join_params->params.chanspec_list[0]  &= WL_CHANSPEC_CHAN_MASK;
++			join_params->params.chanspec_list[0] |= chanspec;
++			join_params->params.chanspec_list[0] =
++				wl_chspec_host_to_driver(join_params->params.chanspec_list[0]);
++
++			join_params->params.chanspec_num =
++				htod32(join_params->params.chanspec_num);
++
++		WL_DBG(("join_params->params.chanspec_list[0]= %X, %d channels\n",
++			join_params->params.chanspec_list[0],
++			join_params->params.chanspec_num));
++	}
++	return 0;
++}
++
++static s32 wl_update_bss_info(struct bcm_cfg80211 *cfg, struct net_device *ndev, bool roam)
++{
++	struct wl_bss_info *bi;
++	struct wlc_ssid *ssid;
++	struct bcm_tlv *tim;
++	s32 beacon_interval;
++	s32 dtim_period;
++	size_t ie_len;
++	u8 *ie;
++	u8 *curbssid;
++	s32 err = 0;
++	struct wiphy *wiphy;
++	u32 channel;
++	char *buf;
++
++	wiphy = bcmcfg_to_wiphy(cfg);
++
++	ssid = (struct wlc_ssid *)wl_read_prof(cfg, ndev, WL_PROF_SSID);
++	curbssid = wl_read_prof(cfg, ndev, WL_PROF_BSSID);
++
++	mutex_lock(&cfg->usr_sync);
++
++	buf = kzalloc(WL_EXTRA_BUF_MAX, GFP_ATOMIC);
++	if (!buf) {
++		WL_ERR(("buffer alloc failed.\n"));
++		return BCME_NOMEM;
++	}
++	*(u32 *)buf = htod32(WL_EXTRA_BUF_MAX);
++	err = wldev_ioctl(ndev, WLC_GET_BSS_INFO, buf, WL_EXTRA_BUF_MAX, false);
++
++	if (unlikely(err)) {
++		WL_ERR(("Could not get bss info %d\n", err));
++		goto update_bss_info_out;
++	}
++	bi = (struct wl_bss_info *)(buf + 4);
++	channel = wf_chspec_ctlchan(wl_chspec_driver_to_host(bi->chanspec));
++	wl_update_prof(cfg, ndev, NULL, &channel, WL_PROF_CHAN);
++
++	if (memcmp(bi->BSSID.octet, curbssid, ETHER_ADDR_LEN)) {
++		WL_ERR(("Bssid doesn't match\n"));
++		err = -EIO;
++		goto update_bss_info_out;
++	}
++	err = wl_inform_single_bss(cfg, bi, roam);
++	if (unlikely(err))
++		goto update_bss_info_out;
++
++	ie = ((u8 *)bi) + bi->ie_offset;
++	ie_len = bi->ie_length;
++	beacon_interval = cpu_to_le16(bi->beacon_period);
++	tim = bcm_parse_tlvs(ie, ie_len, WLAN_EID_TIM);
++	if (tim) {
++		dtim_period = tim->data[1];
++	} else {
++		/*
++		* active scan was done so we could not get dtim
++		* information out of probe response.
++		* so we speficially query dtim information.
++		*/
++		dtim_period = 0;
++		err = wldev_ioctl(ndev, WLC_GET_DTIMPRD,
++			&dtim_period, sizeof(dtim_period), false);
++		if (unlikely(err)) {
++			WL_ERR(("WLC_GET_DTIMPRD error (%d)\n", err));
++			goto update_bss_info_out;
++		}
++	}
++
++	wl_update_prof(cfg, ndev, NULL, &beacon_interval, WL_PROF_BEACONINT);
++	wl_update_prof(cfg, ndev, NULL, &dtim_period, WL_PROF_DTIMPERIOD);
++
++update_bss_info_out:
++	if (unlikely(err)) {
++		WL_ERR(("Failed with error %d\n", err));
++	}
++
++	kfree(buf);
++	mutex_unlock(&cfg->usr_sync);
++	return err;
++}
++
++static s32
++wl_bss_roaming_done(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data)
++{
++	struct wl_connect_info *conn_info = wl_to_conn(cfg);
++	s32 err = 0;
++	u8 *curbssid;
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39))
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	struct ieee80211_supported_band *band;
++	struct ieee80211_channel *notify_channel = NULL;
++	u32 *channel;
++	u32 freq;
++#endif 
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++	struct cfg80211_roam_info roam_info;
++#endif
++
++
++#ifdef WLFBT
++	uint32 data_len = 0;
++	if (data)
++		data_len = ntoh32(e->datalen);
++#endif /* WLFBT */
++
++	wl_get_assoc_ies(cfg, ndev);
++	wl_update_prof(cfg, ndev, NULL, (const void *)(e->addr.octet), WL_PROF_BSSID);
++	curbssid = wl_read_prof(cfg, ndev, WL_PROF_BSSID);
++	wl_update_bss_info(cfg, ndev, true);
++	wl_update_pmklist(ndev, cfg->pmk_list, err);
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39))
++	/* channel info for cfg80211_roamed introduced in 2.6.39-rc1 */
++	channel = (u32 *)wl_read_prof(cfg, ndev, WL_PROF_CHAN);
++	if (*channel <= CH_MAX_2G_CHANNEL)
++		band = wiphy->bands[IEEE80211_BAND_2GHZ];
++	else
++		band = wiphy->bands[IEEE80211_BAND_5GHZ];
++	freq = ieee80211_channel_to_frequency(*channel, band->band);
++	notify_channel = ieee80211_get_channel(wiphy, freq);
++#endif 
++#ifdef WLFBT
++	/* back up the given FBT key for the further supplicant request,
++	 * currently not checking the FBT is enabled for current BSS in DHD,
++	 * because the supplicant decides to take it or not.
++	 */
++	if (data && (data_len == FBT_KEYLEN)) {
++		memcpy(cfg->fbt_key, data, FBT_KEYLEN);
++	}
++#endif /* WLFBT */
++	printk("wl_bss_roaming_done succeeded to " MACDBG "\n",
++		MAC2STRDBG((const u8*)(&e->addr)));
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++	roam_info.channel = notify_channel;
++	roam_info.bssid = curbssid;
++	roam_info.req_ie = conn_info->req_ie;
++	roam_info.req_ie_len = conn_info->req_ie_len;
++	roam_info.resp_ie = conn_info->resp_ie;
++	roam_info.resp_ie_len = conn_info->resp_ie_len;
++
++	cfg80211_roamed(ndev, &roam_info, GFP_KERNEL);
++#else
++	cfg80211_roamed(ndev,
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39))
++		notify_channel,
++#endif
++		curbssid,
++		conn_info->req_ie, conn_info->req_ie_len,
++		conn_info->resp_ie, conn_info->resp_ie_len, GFP_KERNEL);
++#endif
++	WL_DBG(("Report roaming result\n"));
++
++	wl_set_drv_status(cfg, CONNECTED, ndev);
++
++	return err;
++}
++
++static s32
++wl_bss_connect_done(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data, bool completed)
++{
++	struct wl_connect_info *conn_info = wl_to_conn(cfg);
++	struct wl_security *sec = wl_read_prof(cfg, ndev, WL_PROF_SEC);
++#if defined(CUSTOM_SET_CPUCORE)
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++#endif 
++	s32 err = 0;
++	u8 *curbssid = wl_read_prof(cfg, ndev, WL_PROF_BSSID);
++	if (!sec) {
++		WL_ERR(("sec is NULL\n"));
++		return -ENODEV;
++	}
++	WL_DBG((" enter\n"));
++#ifdef ESCAN_RESULT_PATCH
++	if (wl_get_drv_status(cfg, CONNECTED, ndev)) {
++		if (memcmp(curbssid, connect_req_bssid, ETHER_ADDR_LEN) == 0) {
++			WL_DBG((" Connected event of connected device e=%d s=%d, ignore it\n",
++				ntoh32(e->event_type), ntoh32(e->status)));
++			return err;
++		}
++	}
++	if (memcmp(curbssid, broad_bssid, ETHER_ADDR_LEN) == 0 &&
++		memcmp(broad_bssid, connect_req_bssid, ETHER_ADDR_LEN) != 0) {
++		WL_DBG(("copy bssid\n"));
++		memcpy(curbssid, connect_req_bssid, ETHER_ADDR_LEN);
++	}
++
++#else
++	if (cfg->scan_request) {
++		wl_notify_escan_complete(cfg, ndev, true, true);
++	}
++#endif /* ESCAN_RESULT_PATCH */
++	if (wl_get_drv_status(cfg, CONNECTING, ndev)) {
++		wl_cfg80211_scan_abort(cfg);
++		wl_clr_drv_status(cfg, CONNECTING, ndev);
++		if (completed) {
++			wl_get_assoc_ies(cfg, ndev);
++			wl_update_prof(cfg, ndev, NULL, (const void *)(e->addr.octet),
++				WL_PROF_BSSID);
++			curbssid = wl_read_prof(cfg, ndev, WL_PROF_BSSID);
++			wl_update_bss_info(cfg, ndev, false);
++			wl_update_pmklist(ndev, cfg->pmk_list, err);
++			wl_set_drv_status(cfg, CONNECTED, ndev);
++			if (ndev != bcmcfg_to_prmry_ndev(cfg)) {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)
++				init_completion(&cfg->iface_disable);
++#else
++				/* reinitialize completion to clear previous count */
++				INIT_COMPLETION(cfg->iface_disable);
++#endif
++			}
++#ifdef CUSTOM_SET_CPUCORE
++			if (wl_get_chan_isvht80(ndev, dhd)) {
++				if (ndev == bcmcfg_to_prmry_ndev(cfg))
++					dhd->chan_isvht80 |= DHD_FLAG_STA_MODE; /* STA mode */
++				else if (is_p2p_group_iface(ndev->ieee80211_ptr))
++					dhd->chan_isvht80 |= DHD_FLAG_P2P_MODE; /* p2p mode */
++				dhd_set_cpucore(dhd, TRUE);
++			}
++#endif /* CUSTOM_SET_CPUCORE */
++
++		}
++		cfg80211_connect_result(ndev,
++			curbssid,
++			conn_info->req_ie,
++			conn_info->req_ie_len,
++			conn_info->resp_ie,
++			conn_info->resp_ie_len,
++			completed ? WLAN_STATUS_SUCCESS :
++			(sec->auth_assoc_res_status) ?
++			sec->auth_assoc_res_status :
++			WLAN_STATUS_UNSPECIFIED_FAILURE,
++			GFP_KERNEL);
++		if (completed)
++			WL_INFORM(("Report connect result - connection succeeded\n"));
++		else
++			WL_ERR(("Report connect result - connection failed\n"));
++	}
++#ifdef CONFIG_TCPACK_FASTTX
++	if (wl_get_chan_isvht80(ndev, dhd))
++		wldev_iovar_setint(ndev, "tcpack_fast_tx", 0);
++	else
++		wldev_iovar_setint(ndev, "tcpack_fast_tx", 1);
++#endif /* CONFIG_TCPACK_FASTTX */
++
++	return err;
++}
++
++static s32
++wl_notify_mic_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	struct net_device *ndev = NULL;
++	u16 flags = ntoh16(e->flags);
++	enum nl80211_key_type key_type;
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	mutex_lock(&cfg->usr_sync);
++	if (flags & WLC_EVENT_MSG_GROUP)
++		key_type = NL80211_KEYTYPE_GROUP;
++	else
++		key_type = NL80211_KEYTYPE_PAIRWISE;
++
++	cfg80211_michael_mic_failure(ndev, (const u8 *)&e->addr, key_type, -1,
++		NULL, GFP_KERNEL);
++	mutex_unlock(&cfg->usr_sync);
++
++	return 0;
++}
++
++#ifdef BT_WIFI_HANDOVER
++static s32
++wl_notify_bt_wifi_handover_req(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	struct net_device *ndev = NULL;
++	u32 event = ntoh32(e->event_type);
++	u32 datalen = ntoh32(e->datalen);
++	s32 err;
++
++	WL_ERR(("wl_notify_bt_wifi_handover_req: event_type : %d, datalen : %d\n", event, datalen));
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++	err = wl_genl_send_msg(ndev, event, data, (u16)datalen, 0, 0);
++
++	return err;
++}
++#endif /* BT_WIFI_HANDOVER */
++
++#ifdef PNO_SUPPORT
++static s32
++wl_notify_pfn_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	struct net_device *ndev = NULL;
++
++	WL_ERR((">>> PNO Event\n"));
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++
++#ifndef WL_SCHED_SCAN
++	mutex_lock(&cfg->usr_sync);
++	/* TODO: Use cfg80211_sched_scan_results(wiphy); */
++	CFG80211_DISCONNECTED(ndev, 0, NULL, 0, false, GFP_KERNEL);
++	mutex_unlock(&cfg->usr_sync);
++#else
++	/* If cfg80211 scheduled scan is supported, report the pno results via sched
++	 * scan results
++	 */
++	wl_notify_sched_scan_results(cfg, ndev, e, data);
++#endif /* WL_SCHED_SCAN */
++	return 0;
++}
++#endif /* PNO_SUPPORT */
++
++#ifdef GSCAN_SUPPORT
++static s32
++wl_notify_gscan_event(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	s32 err = 0;
++	u32 event = be32_to_cpu(e->event_type);
++	void *ptr;
++	int send_evt_bytes = 0;
++	int batch_event_result_dummy = 0;
++	struct net_device *ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	u32 len = ntoh32(e->datalen);
++
++	switch (event) {
++		case WLC_E_PFN_SWC:
++			ptr = dhd_dev_swc_scan_event(ndev, data, &send_evt_bytes);
++			if (send_evt_bytes) {
++				wl_cfgvendor_send_async_event(wiphy, ndev,
++				    GOOGLE_GSCAN_SIGNIFICANT_EVENT, ptr, send_evt_bytes);
++				kfree(ptr);
++			}
++			break;
++		case WLC_E_PFN_BEST_BATCHING:
++			err = dhd_dev_retrieve_batch_scan(ndev);
++			if (err < 0) {
++				WL_ERR(("Batch retrieval already in progress %d\n", err));
++			} else {
++				wl_cfgvendor_send_async_event(wiphy, ndev,
++				    GOOGLE_GSCAN_BATCH_SCAN_EVENT,
++				     &batch_event_result_dummy, sizeof(int));
++			}
++			break;
++		case WLC_E_PFN_SCAN_COMPLETE:
++			batch_event_result_dummy = WIFI_SCAN_COMPLETE;
++			wl_cfgvendor_send_async_event(wiphy, ndev,
++				GOOGLE_SCAN_COMPLETE_EVENT,
++				&batch_event_result_dummy, sizeof(int));
++			break;
++		case WLC_E_PFN_BSSID_NET_FOUND:
++			ptr = dhd_dev_hotlist_scan_event(ndev, data, &send_evt_bytes,
++			      HOTLIST_FOUND);
++			if (ptr) {
++				wl_cfgvendor_send_hotlist_event(wiphy, ndev,
++				 ptr, send_evt_bytes, GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT);
++				dhd_dev_gscan_hotlist_cache_cleanup(ndev, HOTLIST_FOUND);
++			} else {
++				err = -ENOMEM;
++			}
++			break;
++		case WLC_E_PFN_BSSID_NET_LOST:
++			/* WLC_E_PFN_BSSID_NET_LOST is conflict shared with WLC_E_PFN_SCAN_ALLGONE
++			 * We currently do not use WLC_E_PFN_SCAN_ALLGONE, so if we get it, ignore
++			 */
++			if (len) {
++				ptr = dhd_dev_hotlist_scan_event(ndev, data, &send_evt_bytes,
++				            HOTLIST_LOST);
++				if (ptr) {
++					wl_cfgvendor_send_hotlist_event(wiphy, ndev,
++					 ptr, send_evt_bytes, GOOGLE_GSCAN_GEOFENCE_LOST_EVENT);
++					dhd_dev_gscan_hotlist_cache_cleanup(ndev, HOTLIST_LOST);
++				} else {
++					err = -ENOMEM;
++				}
++			} else {
++				err = -EINVAL;
++			}
++			break;
++		case WLC_E_PFN_GSCAN_FULL_RESULT:
++			ptr = dhd_dev_process_full_gscan_result(ndev, data, len, &send_evt_bytes);
++			if (ptr) {
++				wl_cfgvendor_send_async_event(wiphy, ndev,
++				    GOOGLE_SCAN_FULL_RESULTS_EVENT, ptr, send_evt_bytes);
++				kfree(ptr);
++			} else {
++				err = -ENOMEM;
++			}
++			break;
++		case WLC_E_PFN_SSID_EXT:
++			ptr = dhd_dev_process_epno_result(ndev, data, event, &send_evt_bytes);
++			if (ptr) {
++				wl_cfgvendor_send_async_event(wiphy, ndev,
++				    GOOGLE_SCAN_EPNO_EVENT, ptr, send_evt_bytes);
++				kfree(ptr);
++			} else {
++				err = -ENOMEM;
++			}
++			break;
++		case WLC_E_PFN_NET_FOUND:
++			break;
++		default:
++			WL_ERR(("Unknown event %d\n", event));
++			break;
++	}
++	return err;
++}
++#endif /* GSCAN_SUPPORT */
++
++static s32
++wl_notify_scan_status(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	struct channel_info channel_inform;
++	struct wl_scan_results *bss_list;
++	struct net_device *ndev = NULL;
++	u32 len = WL_SCAN_BUF_MAX;
++	s32 err = 0;
++	unsigned long flags;
++
++	WL_DBG(("Enter \n"));
++#ifdef STBLINUX
++		ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++	if (!wl_get_drv_status(cfg, SCANNING, ndev)) {
++		/* has been handled by WLC_E_ESCAN_RESULT handler */
++
++		WL_DBG(("scan is not ready \n"));
++		return err;
++	}
++#else
++	if (!wl_get_drv_status(cfg, SCANNING, ndev)) {
++		WL_ERR(("scan is not ready \n"));
++		return err;
++	}
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++#endif /* STBLINUX */
++	mutex_lock(&cfg->usr_sync);
++	wl_clr_drv_status(cfg, SCANNING, ndev);
++	memset(&channel_inform, 0, sizeof(channel_inform));
++	err = wldev_ioctl(ndev, WLC_GET_CHANNEL, &channel_inform,
++		sizeof(channel_inform), false);
++	if (unlikely(err)) {
++		WL_ERR(("scan busy (%d)\n", err));
++		goto scan_done_out;
++	}
++	channel_inform.scan_channel = dtoh32(channel_inform.scan_channel);
++	if (unlikely(channel_inform.scan_channel)) {
++
++		WL_DBG(("channel_inform.scan_channel (%d)\n",
++			channel_inform.scan_channel));
++	}
++	cfg->bss_list = cfg->scan_results;
++	bss_list = cfg->bss_list;
++	memset(bss_list, 0, len);
++	bss_list->buflen = htod32(len);
++	err = wldev_ioctl(ndev, WLC_SCAN_RESULTS, bss_list, len, false);
++	if (unlikely(err) && unlikely(!cfg->scan_suppressed)) {
++		WL_ERR(("%s Scan_results error (%d)\n", ndev->name, err));
++		err = -EINVAL;
++		goto scan_done_out;
++	}
++	bss_list->buflen = dtoh32(bss_list->buflen);
++	bss_list->version = dtoh32(bss_list->version);
++	bss_list->count = dtoh32(bss_list->count);
++
++	err = wl_inform_bss(cfg);
++
++scan_done_out:
++	del_timer_sync(&cfg->scan_timeout);
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++	if (cfg->scan_request) {
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(4, 8, 0))
++		struct cfg80211_scan_info info = { .aborted = false };
++		cfg80211_scan_done(cfg->scan_request, &info);
++#else
++		cfg80211_scan_done(cfg->scan_request, false);
++#endif
++		cfg->scan_request = NULL;
++	}
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++	WL_DBG(("cfg80211_scan_done\n"));
++	mutex_unlock(&cfg->usr_sync);
++	return err;
++}
++
++static s32
++wl_frame_get_mgmt(u16 fc, const struct ether_addr *da,
++	const struct ether_addr *sa, const struct ether_addr *bssid,
++	u8 **pheader, u32 *body_len, u8 *pbody)
++{
++	struct dot11_management_header *hdr;
++	u32 totlen = 0;
++	s32 err = 0;
++	u8 *offset;
++	u32 prebody_len = *body_len;
++	switch (fc) {
++		case FC_ASSOC_REQ:
++			/* capability , listen interval */
++			totlen = DOT11_ASSOC_REQ_FIXED_LEN;
++			*body_len += DOT11_ASSOC_REQ_FIXED_LEN;
++			break;
++
++		case FC_REASSOC_REQ:
++			/* capability, listen inteval, ap address */
++			totlen = DOT11_REASSOC_REQ_FIXED_LEN;
++			*body_len += DOT11_REASSOC_REQ_FIXED_LEN;
++			break;
++	}
++	totlen += DOT11_MGMT_HDR_LEN + prebody_len;
++	*pheader = kzalloc(totlen, GFP_KERNEL);
++	if (*pheader == NULL) {
++		WL_ERR(("memory alloc failed \n"));
++		return -ENOMEM;
++	}
++	hdr = (struct dot11_management_header *) (*pheader);
++	hdr->fc = htol16(fc);
++	hdr->durid = 0;
++	hdr->seq = 0;
++	offset = (u8*)(hdr + 1) + (totlen - DOT11_MGMT_HDR_LEN - prebody_len);
++	bcopy((const char*)da, (u8*)&hdr->da, ETHER_ADDR_LEN);
++	bcopy((const char*)sa, (u8*)&hdr->sa, ETHER_ADDR_LEN);
++	bcopy((const char*)bssid, (u8*)&hdr->bssid, ETHER_ADDR_LEN);
++	if ((pbody != NULL) && prebody_len)
++		bcopy((const char*)pbody, offset, prebody_len);
++	*body_len = totlen;
++	return err;
++}
++
++
++void
++wl_stop_wait_next_action_frame(struct bcm_cfg80211 *cfg, struct net_device *ndev)
++{
++	if (wl_get_drv_status_all(cfg, FINDING_COMMON_CHANNEL)) {
++		if (timer_pending(&cfg->p2p->listen_timer)) {
++			del_timer_sync(&cfg->p2p->listen_timer);
++		}
++		if (cfg->afx_hdl != NULL) {
++			if (cfg->afx_hdl->dev != NULL) {
++				wl_clr_drv_status(cfg, SCANNING, cfg->afx_hdl->dev);
++				wl_clr_drv_status(cfg, FINDING_COMMON_CHANNEL, cfg->afx_hdl->dev);
++			}
++			cfg->afx_hdl->peer_chan = WL_INVALID;
++		}
++		complete(&cfg->act_frm_scan);
++		WL_DBG(("*** Wake UP ** Working afx searching is cleared\n"));
++	} else if (wl_get_drv_status_all(cfg, SENDING_ACT_FRM)) {
++		if (!(wl_get_p2p_status(cfg, ACTION_TX_COMPLETED) ||
++			wl_get_p2p_status(cfg, ACTION_TX_NOACK)))
++			wl_set_p2p_status(cfg, ACTION_TX_COMPLETED);
++
++		WL_DBG(("*** Wake UP ** abort actframe iovar\n"));
++		/* if channel is not zero, "actfame" uses off channel scan.
++		 * So abort scan for off channel completion.
++		 */
++		if (cfg->af_sent_channel)
++			wl_cfg80211_scan_abort(cfg);
++	}
++#ifdef WL_CFG80211_SYNC_GON
++	else if (wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM_LISTEN)) {
++		WL_DBG(("*** Wake UP ** abort listen for next af frame\n"));
++		/* So abort scan to cancel listen */
++		wl_cfg80211_scan_abort(cfg);
++	}
++#endif /* WL_CFG80211_SYNC_GON */
++}
++
++
++int wl_cfg80211_get_ioctl_version(void)
++{
++	return ioctl_version;
++}
++
++static s32
++wl_notify_rx_mgmt_frame(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	struct ieee80211_supported_band *band;
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	struct ether_addr da;
++	struct ether_addr bssid;
++	bool isfree = false;
++	s32 err = 0;
++	s32 freq;
++	struct net_device *ndev = NULL;
++	wifi_p2p_pub_act_frame_t *act_frm = NULL;
++	wifi_p2p_action_frame_t *p2p_act_frm = NULL;
++	wifi_p2psd_gas_pub_act_frame_t *sd_act_frm = NULL;
++	wl_event_rx_frame_data_t *rxframe =
++		(wl_event_rx_frame_data_t*)data;
++	u32 event = ntoh32(e->event_type);
++	u8 *mgmt_frame;
++	u8 bsscfgidx = e->bsscfgidx;
++	u32 mgmt_frame_len = ntoh32(e->datalen);
++	u16 channel = ((ntoh16(rxframe->channel) & WL_CHANSPEC_CHAN_MASK));
++
++	if (mgmt_frame_len < sizeof(wl_event_rx_frame_data_t)) {
++		WL_ERR(("wrong datalen:%d\n", mgmt_frame_len));
++		return -EINVAL;
++	}
++	mgmt_frame_len -= sizeof(wl_event_rx_frame_data_t);
++
++	memset(&bssid, 0, ETHER_ADDR_LEN);
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	if (channel <= CH_MAX_2G_CHANNEL)
++		band = wiphy->bands[IEEE80211_BAND_2GHZ];
++	else
++		band = wiphy->bands[IEEE80211_BAND_5GHZ];
++	if (!band) {
++		WL_ERR(("No valid band"));
++		return -EINVAL;
++	}
++#if LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 38)
++	freq = ieee80211_channel_to_frequency(channel);
++	(void)band->band;
++#else
++	freq = ieee80211_channel_to_frequency(channel, band->band);
++#endif
++	if (event == WLC_E_ACTION_FRAME_RX) {
++		wldev_iovar_getbuf_bsscfg(ndev, "cur_etheraddr",
++			NULL, 0, cfg->ioctl_buf, WLC_IOCTL_SMLEN, bsscfgidx, &cfg->ioctl_buf_sync);
++
++		err = wldev_ioctl(ndev, WLC_GET_BSSID, &bssid, ETHER_ADDR_LEN, false);
++		if (err < 0)
++			 WL_ERR(("WLC_GET_BSSID error %d\n", err));
++		memcpy(da.octet, cfg->ioctl_buf, ETHER_ADDR_LEN);
++		err = wl_frame_get_mgmt(FC_ACTION, &da, &e->addr, &bssid,
++			&mgmt_frame, &mgmt_frame_len,
++			(u8 *)((wl_event_rx_frame_data_t *)rxframe + 1));
++		if (err < 0) {
++			WL_ERR(("Error in receiving action frame len %d channel %d freq %d\n",
++				mgmt_frame_len, channel, freq));
++			goto exit;
++		}
++		isfree = true;
++		if (wl_cfgp2p_is_pub_action(&mgmt_frame[DOT11_MGMT_HDR_LEN],
++			mgmt_frame_len - DOT11_MGMT_HDR_LEN)) {
++			act_frm = (wifi_p2p_pub_act_frame_t *)
++					(&mgmt_frame[DOT11_MGMT_HDR_LEN]);
++		} else if (wl_cfgp2p_is_p2p_action(&mgmt_frame[DOT11_MGMT_HDR_LEN],
++			mgmt_frame_len - DOT11_MGMT_HDR_LEN)) {
++			p2p_act_frm = (wifi_p2p_action_frame_t *)
++					(&mgmt_frame[DOT11_MGMT_HDR_LEN]);
++			(void) p2p_act_frm;
++		} else if (wl_cfgp2p_is_gas_action(&mgmt_frame[DOT11_MGMT_HDR_LEN],
++			mgmt_frame_len - DOT11_MGMT_HDR_LEN)) {
++
++			sd_act_frm = (wifi_p2psd_gas_pub_act_frame_t *)
++					(&mgmt_frame[DOT11_MGMT_HDR_LEN]);
++			if (sd_act_frm && wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM)) {
++				if (cfg->next_af_subtype == sd_act_frm->action) {
++					WL_DBG(("We got a right next frame of SD!(%d)\n",
++						sd_act_frm->action));
++					wl_clr_drv_status(cfg, WAITING_NEXT_ACT_FRM, ndev);
++
++					/* Stop waiting for next AF. */
++					wl_stop_wait_next_action_frame(cfg, ndev);
++				}
++			}
++			(void) sd_act_frm;
++#ifdef WLTDLS
++		} else if (mgmt_frame[DOT11_MGMT_HDR_LEN] == TDLS_AF_CATEGORY) {
++			WL_DBG((" TDLS Action Frame Received type = %d \n",
++				mgmt_frame[DOT11_MGMT_HDR_LEN + 1]));
++
++			if (mgmt_frame[DOT11_MGMT_HDR_LEN + 1] == TDLS_ACTION_SETUP_RESP) {
++				cfg->tdls_mgmt_frame = mgmt_frame;
++				cfg->tdls_mgmt_frame_len = mgmt_frame_len;
++				cfg->tdls_mgmt_freq = freq;
++				return 0;
++			}
++
++		} else if (mgmt_frame[DOT11_MGMT_HDR_LEN] == TDLS_VENDOR_SPECIFIC) {
++			WL_DBG((" TDLS Vendor Specific Received type \n"));
++#endif
++#ifdef QOS_MAP_SET
++		} else if (mgmt_frame[DOT11_MGMT_HDR_LEN] == DOT11_ACTION_CAT_QOS) {
++			/* update QoS map set table */
++			bcm_tlv_t * qos_map_ie = NULL;
++			if ((qos_map_ie = bcm_parse_tlvs(&mgmt_frame[DOT11_MGMT_HDR_LEN],
++					mgmt_frame_len - DOT11_MGMT_HDR_LEN,
++					DOT11_MNG_QOS_MAP_ID)) != NULL) {
++				WL_DBG((" QoS map set IE found in QoS action frame\n"));
++				if (!cfg->up_table) {
++					cfg->up_table = kmalloc(UP_TABLE_MAX, GFP_KERNEL);
++				}
++				wl_set_up_table(cfg->up_table, qos_map_ie);
++			} else {
++				kfree(cfg->up_table);
++				cfg->up_table = NULL;
++			}
++#endif /* QOS_MAP_SET */
++		} else {
++			/*
++			 *  if we got normal action frame and ndev is p2p0,
++			 *  we have to change ndev from p2p0 to wlan0
++			 */
++
++
++			if (cfg->next_af_subtype != P2P_PAF_SUBTYPE_INVALID) {
++				u8 action = 0;
++				if (wl_get_public_action(&mgmt_frame[DOT11_MGMT_HDR_LEN],
++					mgmt_frame_len - DOT11_MGMT_HDR_LEN, &action) != BCME_OK) {
++					WL_DBG(("Recived action is not public action frame\n"));
++				} else if (cfg->next_af_subtype == action) {
++					WL_DBG(("Recived action is the waiting action(%d)\n",
++						action));
++					wl_clr_drv_status(cfg, WAITING_NEXT_ACT_FRM, ndev);
++
++					/* Stop waiting for next AF. */
++					wl_stop_wait_next_action_frame(cfg, ndev);
++				}
++			}
++		}
++
++		if (act_frm) {
++
++			if (wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM)) {
++				if (cfg->next_af_subtype == act_frm->subtype) {
++					WL_DBG(("We got a right next frame!(%d)\n",
++						act_frm->subtype));
++					wl_clr_drv_status(cfg, WAITING_NEXT_ACT_FRM, ndev);
++
++					if (cfg->next_af_subtype == P2P_PAF_GON_CONF) {
++						OSL_SLEEP(20);
++					}
++
++					/* Stop waiting for next AF. */
++					wl_stop_wait_next_action_frame(cfg, ndev);
++				}
++			}
++		}
++
++		wl_cfgp2p_print_actframe(false, &mgmt_frame[DOT11_MGMT_HDR_LEN],
++			mgmt_frame_len - DOT11_MGMT_HDR_LEN, channel);
++		/*
++		 * After complete GO Negotiation, roll back to mpc mode
++		 */
++		if (act_frm && ((act_frm->subtype == P2P_PAF_GON_CONF) ||
++			(act_frm->subtype == P2P_PAF_PROVDIS_RSP))) {
++			wldev_iovar_setint(ndev, "mpc", 1);
++		}
++		if (act_frm && (act_frm->subtype == P2P_PAF_GON_CONF)) {
++			WL_DBG(("P2P: GO_NEG_PHASE status cleared \n"));
++			wl_clr_p2p_status(cfg, GO_NEG_PHASE);
++		}
++	} else if (event == WLC_E_PROBREQ_MSG) {
++
++		/* Handle probe reqs frame
++		 * WPS-AP certification 4.2.13
++		 */
++		struct parsed_ies prbreq_ies;
++		u32 prbreq_ie_len = 0;
++		bool pbc = 0;
++
++		WL_DBG((" Event WLC_E_PROBREQ_MSG received\n"));
++		mgmt_frame = (u8 *)(data);
++		mgmt_frame_len = ntoh32(e->datalen);
++		if (mgmt_frame_len < DOT11_MGMT_HDR_LEN) {
++			WL_ERR(("wrong datalen:%d\n", mgmt_frame_len));
++			return -EINVAL;
++		}
++		prbreq_ie_len = mgmt_frame_len - DOT11_MGMT_HDR_LEN;
++
++		/* Parse prob_req IEs */
++		if (wl_cfg80211_parse_ies(&mgmt_frame[DOT11_MGMT_HDR_LEN],
++			prbreq_ie_len, &prbreq_ies) < 0) {
++			WL_ERR(("Prob req get IEs failed\n"));
++			return 0;
++		}
++		if (prbreq_ies.wps_ie != NULL) {
++			wl_validate_wps_ie((char *)prbreq_ies.wps_ie, prbreq_ies.wps_ie_len, &pbc);
++			WL_DBG((" wps_ie exist pbc = %d\n", pbc));
++			/* if pbc method, send prob_req mgmt frame to upper layer */
++			if (!pbc)
++				return 0;
++		} else
++			return 0;
++	} else {
++		mgmt_frame = (u8 *)((wl_event_rx_frame_data_t *)rxframe + 1);
++
++		/* wpa supplicant use probe request event for restarting another GON Req.
++		 * but it makes GON Req repetition.
++		 * so if src addr of prb req is same as my target device,
++		 * do not send probe request event during sending action frame.
++		 */
++		if (event == WLC_E_P2P_PROBREQ_MSG) {
++			WL_DBG((" Event %s\n", (event == WLC_E_P2P_PROBREQ_MSG) ?
++				"WLC_E_P2P_PROBREQ_MSG":"WLC_E_PROBREQ_MSG"));
++
++
++			/* Filter any P2P probe reqs arriving during the
++			 * GO-NEG Phase
++			 */
++			if (cfg->p2p &&
++#if defined(P2P_IE_MISSING_FIX)
++				cfg->p2p_prb_noti &&
++#endif
++				wl_get_p2p_status(cfg, GO_NEG_PHASE)) {
++				WL_DBG(("Filtering P2P probe_req while "
++					"being in GO-Neg state\n"));
++				return 0;
++			}
++		}
++	}
++
++	if (discover_cfgdev(cfgdev, cfg))
++		WL_DBG(("Rx Managment frame For P2P Discovery Interface \n"));
++	else
++		WL_DBG(("Rx Managment frame For Iface (%s) \n", ndev->name));
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
++	cfg80211_rx_mgmt(cfgdev, freq, 0,  mgmt_frame, mgmt_frame_len, 0);
++#elif(LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0))
++	cfg80211_rx_mgmt(cfgdev, freq, 0,  mgmt_frame, mgmt_frame_len, 0, GFP_ATOMIC);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) || \
++	defined(WL_COMPAT_WIRELESS)
++	cfg80211_rx_mgmt(cfgdev, freq, 0, mgmt_frame, mgmt_frame_len, GFP_ATOMIC);
++#else
++	cfg80211_rx_mgmt(cfgdev, freq, mgmt_frame, mgmt_frame_len, GFP_ATOMIC);
++#endif /* LINUX_VERSION >= VERSION(3, 14, 0) */
++
++	WL_DBG(("mgmt_frame_len (%d) , e->datalen (%d), channel (%d), freq (%d)\n",
++		mgmt_frame_len, ntoh32(e->datalen), channel, freq));
++exit:
++	if (isfree)
++		kfree(mgmt_frame);
++	return 0;
++}
++
++#ifdef WL_SCHED_SCAN
++/* If target scan is not reliable, set the below define to "1" to do a
++ * full escan
++ */
++#define FULL_ESCAN_ON_PFN_NET_FOUND		0
++static s32
++wl_notify_sched_scan_results(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, void *data)
++{
++	wl_pfn_net_info_t *netinfo, *pnetinfo;
++	struct wiphy *wiphy	= bcmcfg_to_wiphy(cfg);
++	int err = 0;
++	struct cfg80211_scan_request *request = NULL;
++	struct cfg80211_ssid ssid[MAX_PFN_LIST_COUNT];
++	struct ieee80211_channel *channel = NULL;
++	int channel_req = 0;
++	int band = 0;
++	struct wl_pfn_scanresults *pfn_result = (struct wl_pfn_scanresults *)data;
++	int n_pfn_results = pfn_result->count;
++
++	WL_DBG(("Enter\n"));
++
++	if (e->event_type == WLC_E_PFN_NET_LOST) {
++		WL_PNO(("PFN NET LOST event. Do Nothing \n"));
++		return 0;
++	}
++	WL_PNO((">>> PFN NET FOUND event. count:%d \n", n_pfn_results));
++	if (n_pfn_results > 0) {
++		int i;
++
++		if (n_pfn_results > MAX_PFN_LIST_COUNT)
++			n_pfn_results = MAX_PFN_LIST_COUNT;
++		pnetinfo = (wl_pfn_net_info_t *)(data + sizeof(wl_pfn_scanresults_t)
++				- sizeof(wl_pfn_net_info_t));
++
++		memset(&ssid, 0x00, sizeof(ssid));
++
++		request = kzalloc(sizeof(*request)
++			+ sizeof(*request->channels) * n_pfn_results,
++			GFP_KERNEL);
++		channel = (struct ieee80211_channel *)kzalloc(
++			(sizeof(struct ieee80211_channel) * n_pfn_results),
++			GFP_KERNEL);
++		if (!request || !channel) {
++			WL_ERR(("No memory"));
++			err = -ENOMEM;
++			goto out_err;
++		}
++
++		request->wiphy = wiphy;
++
++		for (i = 0; i < n_pfn_results; i++) {
++			netinfo = &pnetinfo[i];
++			if (!netinfo) {
++				WL_ERR(("Invalid netinfo ptr. index:%d", i));
++				err = -EINVAL;
++				goto out_err;
++			}
++			WL_PNO((">>> SSID:%s Channel:%d \n",
++				netinfo->pfnsubnet.SSID, netinfo->pfnsubnet.channel));
++			/* PFN result doesn't have all the info which are required by the supplicant
++			 * (For e.g IEs) Do a target Escan so that sched scan results are reported
++			 * via wl_inform_single_bss in the required format. Escan does require the
++			 * scan request in the form of cfg80211_scan_request. For timebeing, create
++			 * cfg80211_scan_request one out of the received PNO event.
++			 */
++			memcpy(ssid[i].ssid, netinfo->pfnsubnet.SSID,
++				netinfo->pfnsubnet.SSID_len);
++			ssid[i].ssid_len = netinfo->pfnsubnet.SSID_len;
++			request->n_ssids++;
++
++			channel_req = netinfo->pfnsubnet.channel;
++			band = (channel_req <= CH_MAX_2G_CHANNEL) ? NL80211_BAND_2GHZ
++				: NL80211_BAND_5GHZ;
++			channel[i].center_freq = ieee80211_channel_to_frequency(channel_req, band);
++			channel[i].band = band;
++			channel[i].flags |= IEEE80211_CHAN_NO_HT40;
++			request->channels[i] = &channel[i];
++			request->n_channels++;
++		}
++
++		/* assign parsed ssid array */
++		if (request->n_ssids)
++			request->ssids = &ssid[0];
++
++		if (wl_get_drv_status_all(cfg, SCANNING)) {
++			/* Abort any on-going scan */
++			wl_notify_escan_complete(cfg, ndev, true, true);
++		}
++
++		if (wl_get_p2p_status(cfg, DISCOVERY_ON)) {
++			WL_PNO((">>> P2P discovery was ON. Disabling it\n"));
++			err = wl_cfgp2p_discover_enable_search(cfg, false);
++			if (unlikely(err)) {
++				wl_clr_drv_status(cfg, SCANNING, ndev);
++				goto out_err;
++			}
++			p2p_scan(cfg) = false;
++		}
++
++		wl_set_drv_status(cfg, SCANNING, ndev);
++#if FULL_ESCAN_ON_PFN_NET_FOUND
++		WL_PNO((">>> Doing Full ESCAN on PNO event\n"));
++		err = wl_do_escan(cfg, wiphy, ndev, NULL);
++#else
++		WL_PNO((">>> Doing targeted ESCAN on PNO event\n"));
++		err = wl_do_escan(cfg, wiphy, ndev, request);
++#endif
++		if (err) {
++			wl_clr_drv_status(cfg, SCANNING, ndev);
++			goto out_err;
++		}
++		cfg->sched_scan_running = TRUE;
++	}
++	else {
++		WL_ERR(("FALSE PNO Event. (pfn_count == 0) \n"));
++	}
++out_err:
++	if (request)
++		kfree(request);
++	if (channel)
++		kfree(channel);
++	return err;
++}
++#endif /* WL_SCHED_SCAN */
++
++static void wl_init_conf(struct wl_conf *conf)
++{
++	WL_DBG(("Enter \n"));
++	conf->frag_threshold = (u32)-1;
++	conf->rts_threshold = (u32)-1;
++	conf->retry_short = (u32)-1;
++	conf->retry_long = (u32)-1;
++	conf->tx_power = -1;
++}
++
++static void wl_init_prof(struct bcm_cfg80211 *cfg, struct net_device *ndev)
++{
++	unsigned long flags;
++	struct wl_profile *profile = wl_get_profile_by_netdev(cfg, ndev);
++
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++	memset(profile, 0, sizeof(struct wl_profile));
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++}
++
++static void wl_init_event_handler(struct bcm_cfg80211 *cfg)
++{
++	memset(cfg->evt_handler, 0, sizeof(cfg->evt_handler));
++
++	cfg->evt_handler[WLC_E_SCAN_COMPLETE] = wl_notify_scan_status;
++	cfg->evt_handler[WLC_E_AUTH] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_ASSOC] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_LINK] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_DEAUTH_IND] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_DEAUTH] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_DISASSOC_IND] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_ASSOC_IND] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_REASSOC_IND] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_ROAM] = wl_notify_roaming_status;
++	cfg->evt_handler[WLC_E_MIC_ERROR] = wl_notify_mic_status;
++	cfg->evt_handler[WLC_E_SET_SSID] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_ACTION_FRAME_RX] = wl_notify_rx_mgmt_frame;
++	cfg->evt_handler[WLC_E_PROBREQ_MSG] = wl_notify_rx_mgmt_frame;
++	cfg->evt_handler[WLC_E_P2P_PROBREQ_MSG] = wl_notify_rx_mgmt_frame;
++	cfg->evt_handler[WLC_E_P2P_DISC_LISTEN_COMPLETE] = wl_cfgp2p_listen_complete;
++	cfg->evt_handler[WLC_E_ACTION_FRAME_COMPLETE] = wl_cfgp2p_action_tx_complete;
++	cfg->evt_handler[WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE] = wl_cfgp2p_action_tx_complete;
++	cfg->evt_handler[WLC_E_JOIN] = wl_notify_connect_status;
++	cfg->evt_handler[WLC_E_START] = wl_notify_connect_status;
++#ifdef PNO_SUPPORT
++	cfg->evt_handler[WLC_E_PFN_NET_FOUND] = wl_notify_pfn_status;
++#endif /* PNO_SUPPORT */
++#ifdef GSCAN_SUPPORT
++	cfg->evt_handler[WLC_E_PFN_BEST_BATCHING] = wl_notify_gscan_event;
++	cfg->evt_handler[WLC_E_PFN_SCAN_COMPLETE] = wl_notify_gscan_event;
++	cfg->evt_handler[WLC_E_PFN_GSCAN_FULL_RESULT] = wl_notify_gscan_event;
++	cfg->evt_handler[WLC_E_PFN_SWC] = wl_notify_gscan_event;
++	cfg->evt_handler[WLC_E_PFN_BSSID_NET_FOUND] = wl_notify_gscan_event;
++	cfg->evt_handler[WLC_E_PFN_BSSID_NET_LOST] = wl_notify_gscan_event;
++	cfg->evt_handler[WLC_E_PFN_SSID_EXT] = wl_notify_gscan_event;
++	cfg->evt_handler[WLC_E_GAS_FRAGMENT_RX] = wl_notify_gscan_event;
++	cfg->evt_handler[WLC_E_ROAM_EXP_EVENT] = wl_handle_roam_exp_event;
++#endif /* GSCAN_SUPPORT */
++	cfg->evt_handler[WLC_E_RSSI_LQM] = wl_handle_rssi_monitor_event;
++#ifdef WLTDLS
++	cfg->evt_handler[WLC_E_TDLS_PEER_EVENT] = wl_tdls_event_handler;
++#endif /* WLTDLS */
++	cfg->evt_handler[WLC_E_BSSID] = wl_notify_roaming_status;
++#ifdef	WL_RELMCAST
++	cfg->evt_handler[WLC_E_RMC_EVENT] = wl_notify_rmc_status;
++#endif
++#ifdef BT_WIFI_HANDOVER
++	cfg->evt_handler[WLC_E_BT_WIFI_HANDOVER_REQ] = wl_notify_bt_wifi_handover_req;
++#endif
++#ifdef WL_NAN
++	cfg->evt_handler[WLC_E_NAN] = wl_cfgnan_notify_nan_status;
++	cfg->evt_handler[WLC_E_PROXD] = wl_cfgnan_notify_proxd_status;
++#endif /* WL_NAN */
++	cfg->evt_handler[WLC_E_CSA_COMPLETE_IND] = wl_csa_complete_ind;
++#ifdef DHD_LOSSLESS_ROAMING
++	cfg->evt_handler[WLC_E_ROAM_PREP] = wl_notify_roam_prep_status;
++#endif
++}
++
++#if defined(STATIC_WL_PRIV_STRUCT)
++static void
++wl_init_escan_result_buf(struct bcm_cfg80211 *cfg)
++{
++	cfg->escan_info.escan_buf = DHD_OS_PREALLOC(cfg->pub,
++		DHD_PREALLOC_WIPHY_ESCAN0, ESCAN_BUF_SIZE);
++	bzero(cfg->escan_info.escan_buf, ESCAN_BUF_SIZE);
++}
++
++static void
++wl_deinit_escan_result_buf(struct bcm_cfg80211 *cfg)
++{
++	cfg->escan_info.escan_buf = NULL;
++
++}
++#endif /* STATIC_WL_PRIV_STRUCT */
++
++static s32 wl_init_priv_mem(struct bcm_cfg80211 *cfg)
++{
++	WL_DBG(("Enter \n"));
++
++	cfg->scan_results = (void *)kzalloc(WL_SCAN_BUF_MAX, GFP_KERNEL);
++	if (unlikely(!cfg->scan_results)) {
++		WL_ERR(("Scan results alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++	cfg->conf = (void *)kzalloc(sizeof(*cfg->conf), GFP_KERNEL);
++	if (unlikely(!cfg->conf)) {
++		WL_ERR(("wl_conf alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++	cfg->scan_req_int =
++	    (void *)kzalloc(sizeof(*cfg->scan_req_int), GFP_KERNEL);
++	if (unlikely(!cfg->scan_req_int)) {
++		WL_ERR(("Scan req alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++	cfg->ioctl_buf = (void *)kzalloc(WLC_IOCTL_MAXLEN, GFP_KERNEL);
++	if (unlikely(!cfg->ioctl_buf)) {
++		WL_ERR(("Ioctl buf alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++	cfg->escan_ioctl_buf = (void *)kzalloc(WLC_IOCTL_MAXLEN, GFP_KERNEL);
++	if (unlikely(!cfg->escan_ioctl_buf)) {
++		WL_ERR(("Ioctl buf alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++	cfg->extra_buf = (void *)kzalloc(WL_EXTRA_BUF_MAX, GFP_KERNEL);
++	if (unlikely(!cfg->extra_buf)) {
++		WL_ERR(("Extra buf alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++	cfg->pmk_list = (void *)kzalloc(sizeof(*cfg->pmk_list), GFP_KERNEL);
++	if (unlikely(!cfg->pmk_list)) {
++		WL_ERR(("pmk list alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++#if defined(STATIC_WL_PRIV_STRUCT)
++	cfg->conn_info = (void *)kzalloc(sizeof(*cfg->conn_info), GFP_KERNEL);
++	if (unlikely(!cfg->conn_info)) {
++		WL_ERR(("cfg->conn_info  alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++	cfg->ie = (void *)kzalloc(sizeof(*cfg->ie), GFP_KERNEL);
++	if (unlikely(!cfg->ie)) {
++		WL_ERR(("cfg->ie  alloc failed\n"));
++		goto init_priv_mem_out;
++	}
++	wl_init_escan_result_buf(cfg);
++#endif /* STATIC_WL_PRIV_STRUCT */
++	cfg->afx_hdl = (void *)kzalloc(sizeof(*cfg->afx_hdl), GFP_KERNEL);
++	if (unlikely(!cfg->afx_hdl)) {
++		WL_ERR(("afx hdl  alloc failed\n"));
++		goto init_priv_mem_out;
++	} else {
++		init_completion(&cfg->act_frm_scan);
++		init_completion(&cfg->wait_next_af);
++
++		INIT_WORK(&cfg->afx_hdl->work, wl_cfg80211_afx_handler);
++	}
++#ifdef WLTDLS
++	if (cfg->tdls_mgmt_frame) {
++		kfree(cfg->tdls_mgmt_frame);
++		cfg->tdls_mgmt_frame = NULL;
++	}
++#endif /* WLTDLS */
++	return 0;
++
++init_priv_mem_out:
++	wl_deinit_priv_mem(cfg);
++
++	return -ENOMEM;
++}
++
++static void wl_deinit_priv_mem(struct bcm_cfg80211 *cfg)
++{
++	kfree(cfg->scan_results);
++	cfg->scan_results = NULL;
++	kfree(cfg->conf);
++	cfg->conf = NULL;
++	kfree(cfg->scan_req_int);
++	cfg->scan_req_int = NULL;
++	kfree(cfg->ioctl_buf);
++	cfg->ioctl_buf = NULL;
++	kfree(cfg->escan_ioctl_buf);
++	cfg->escan_ioctl_buf = NULL;
++	kfree(cfg->extra_buf);
++	cfg->extra_buf = NULL;
++	kfree(cfg->pmk_list);
++	cfg->pmk_list = NULL;
++#if defined(STATIC_WL_PRIV_STRUCT)
++	kfree(cfg->conn_info);
++	cfg->conn_info = NULL;
++	kfree(cfg->ie);
++	cfg->ie = NULL;
++	wl_deinit_escan_result_buf(cfg);
++#endif /* STATIC_WL_PRIV_STRUCT */
++	if (cfg->afx_hdl) {
++		cancel_work_sync(&cfg->afx_hdl->work);
++		kfree(cfg->afx_hdl);
++		cfg->afx_hdl = NULL;
++	}
++
++}
++
++static s32 wl_create_event_handler(struct bcm_cfg80211 *cfg)
++{
++	int ret = 0;
++	WL_DBG(("Enter \n"));
++
++	/* Do not use DHD in cfg driver */
++	cfg->event_tsk.thr_pid = -1;
++
++	PROC_START(wl_event_handler, cfg, &cfg->event_tsk, 0, "wl_event_handler");
++	if (cfg->event_tsk.thr_pid < 0)
++		ret = -ENOMEM;
++	return ret;
++}
++
++static void wl_destroy_event_handler(struct bcm_cfg80211 *cfg)
++{
++	if (cfg->event_tsk.thr_pid >= 0)
++		PROC_STOP(&cfg->event_tsk);
++}
++
++void wl_terminate_event_handler(void)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++
++	if (cfg) {
++		wl_destroy_event_handler(cfg);
++	}
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++static void wl_scan_timeout(struct timer_list *t)
++{
++	struct bcm_cfg80211 *cfg = from_timer(cfg, t, scan_timeout);
++#else
++static void wl_scan_timeout(unsigned long data)
++{
++	struct bcm_cfg80211 *cfg = (struct bcm_cfg80211 *)data;
++#endif
++	wl_event_msg_t msg;
++	struct wireless_dev *wdev = NULL;
++	struct net_device *ndev = NULL;
++	struct wl_scan_results *bss_list;
++	struct wl_bss_info *bi = NULL;
++	s32 i;
++	u32 channel;
++#if defined(DHD_DEBUG) && defined(BCMPCIE) && defined(DHD_FW_COREDUMP)
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++	uint32 prev_memdump_mode = dhdp->memdump_enabled;
++#endif /* DHD_DEBUG && BCMPCIE && DHD_FW_COREDUMP */
++
++	if (!(cfg->scan_request)) {
++		WL_ERR(("timer expired but no scan request\n"));
++		return;
++	}
++
++	bss_list = wl_escan_get_buf(cfg, FALSE);
++	if (!bss_list) {
++		WL_ERR(("bss_list is null. Didn't receive any partial scan results\n"));
++	} else {
++		WL_ERR(("scanned AP count (%d)\n", bss_list->count));
++
++		bi = next_bss(bss_list, bi);
++		for_each_bss(bss_list, bi, i) {
++			channel = wf_chspec_ctlchan(wl_chspec_driver_to_host(bi->chanspec));
++			WL_ERR(("SSID :%s  Channel :%d\n", bi->SSID, channel));
++		}
++	}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++	if (cfg->scan_request->dev)
++		wdev = cfg->scan_request->dev->ieee80211_ptr;
++#else
++	wdev = cfg->scan_request->wdev;
++#endif /* LINUX_VERSION < KERNEL_VERSION(3, 6, 0) */
++	if (!wdev) {
++		WL_ERR(("No wireless_dev present\n"));
++		return;
++	}
++	ndev = wdev_to_wlc_ndev(wdev, cfg);
++
++	bzero(&msg, sizeof(wl_event_msg_t));
++	WL_ERR(("timer expired\n"));
++#if defined(DHD_DEBUG) && defined(BCMPCIE) && defined(DHD_FW_COREDUMP)
++	if (dhdp->memdump_enabled) {
++		dhdp->memdump_enabled = DUMP_MEMFILE;
++		dhdp->memdump_type = DUMP_TYPE_SCAN_TIMEOUT;
++		dhd_bus_mem_dump(dhdp);
++		dhdp->memdump_enabled = prev_memdump_mode;
++	}
++#endif /* DHD_DEBUG && BCMPCIE && DHD_FW_COREDUMP */
++	msg.event_type = hton32(WLC_E_ESCAN_RESULT);
++	msg.status = hton32(WLC_E_STATUS_TIMEOUT);
++	msg.reason = 0xFFFFFFFF;
++	wl_cfg80211_event(ndev, &msg, NULL);
++}
++
++#ifdef DHD_LOSSLESS_ROAMING
++static void wl_del_roam_timeout(struct bcm_cfg80211 *cfg)
++{
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++
++	/* restore prec_map to ALLPRIO */
++	dhdp->dequeue_prec_map = ALLPRIO;
++	if (timer_pending(&cfg->roam_timeout)) {
++		del_timer_sync(&cfg->roam_timeout);
++	}
++
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++static void wl_roam_timeout(struct timer_list *t)
++{
++	struct bcm_cfg80211 *cfg = from_timer(cfg, t, wl_roam_timeout);
++#else
++static void wl_roam_timeout(unsigned long data)
++{
++	struct bcm_cfg80211 *cfg = (struct bcm_cfg80211 *)data;
++#endif
++	dhd_pub_t *dhdp = (dhd_pub_t *)(cfg->pub);
++
++	WL_ERR(("roam timer expired\n"));
++
++	/* restore prec_map to ALLPRIO */
++	dhdp->dequeue_prec_map = ALLPRIO;
++}
++
++#endif /* DHD_LOSSLESS_ROAMING */
++
++static s32
++wl_cfg80211_netdev_notifier_call(struct notifier_block * nb,
++	unsigned long state, void *ptr)
++{
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0))
++	struct net_device *dev = ptr;
++#else
++	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
++#endif /* LINUX_VERSION < VERSION(3, 11, 0) */
++	struct wireless_dev *wdev = ndev_to_wdev(dev);
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++
++	WL_DBG(("Enter \n"));
++
++	if (!wdev || !cfg || dev == bcmcfg_to_prmry_ndev(cfg))
++		return NOTIFY_DONE;
++
++	switch (state) {
++		case NETDEV_DOWN:
++		{
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0))
++			int max_wait_timeout = 2;
++			int max_wait_count = 100;
++			int refcnt = 0;
++			unsigned long limit = jiffies + max_wait_timeout * HZ;
++			while (work_pending(&wdev->cleanup_work)) {
++				if (refcnt%5 == 0) {
++					WL_ERR(("[NETDEV_DOWN] wait for "
++						"complete of cleanup_work"
++						" (%d th)\n", refcnt));
++				}
++				if (!time_before(jiffies, limit)) {
++					WL_ERR(("[NETDEV_DOWN] cleanup_work"
++						" of CFG80211 is not"
++						" completed in %d sec\n",
++						max_wait_timeout));
++					break;
++				}
++				if (refcnt >= max_wait_count) {
++					WL_ERR(("[NETDEV_DOWN] cleanup_work"
++						" of CFG80211 is not"
++						" completed in %d loop\n",
++						max_wait_count));
++					break;
++				}
++				set_current_state(TASK_INTERRUPTIBLE);
++				(void)schedule_timeout(100);
++				set_current_state(TASK_RUNNING);
++				refcnt++;
++			}
++#endif /* LINUX_VERSION < VERSION(3, 14, 0) */
++			break;
++		}
++		case NETDEV_UNREGISTER:
++			/* after calling list_del_rcu(&wdev->list) */
++			wl_cfg80211_clear_per_bss_ies(cfg,
++				wl_get_bssidx_by_wdev(cfg, wdev));
++			wl_dealloc_netinfo_by_wdev(cfg, wdev);
++			break;
++		case NETDEV_GOING_DOWN:
++			/*
++			 * At NETDEV_DOWN state, wdev_cleanup_work work will be called.
++			 * In front of door, the function checks whether current scan
++			 * is working or not. If the scanning is still working,
++			 * wdev_cleanup_work call WARN_ON and make the scan done forcibly.
++			 */
++			if (wl_get_drv_status(cfg, SCANNING, dev))
++				wl_notify_escan_complete(cfg, dev, true, true);
++			break;
++	}
++	return NOTIFY_DONE;
++}
++
++static struct notifier_block wl_cfg80211_netdev_notifier = {
++	.notifier_call = wl_cfg80211_netdev_notifier_call,
++};
++
++/*
++ * to make sure we won't register the same notifier twice, otherwise a loop is likely to be
++ * created in kernel notifier link list (with 'next' pointing to itself)
++ */
++static bool wl_cfg80211_netdev_notifier_registered = FALSE;
++
++static void wl_cfg80211_cancel_scan(struct bcm_cfg80211 *cfg)
++{
++	struct wireless_dev *wdev = NULL;
++	struct net_device *ndev = NULL;
++
++	if (!cfg->scan_request)
++		return;
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++	if (cfg->scan_request->dev)
++		wdev = cfg->scan_request->dev->ieee80211_ptr;
++#else
++	wdev = cfg->scan_request->wdev;
++#endif /* LINUX_VERSION < KERNEL_VERSION(3, 6, 0) */
++
++	if (!wdev) {
++		WL_ERR(("No wireless_dev present\n"));
++		return;
++	}
++
++	ndev = wdev_to_wlc_ndev(wdev, cfg);
++	wl_notify_escan_complete(cfg, ndev, true, true);
++	WL_ERR(("Scan aborted! \n"));
++}
++
++static void wl_cfg80211_scan_abort(struct bcm_cfg80211 *cfg)
++{
++	wl_scan_params_t *params = NULL;
++	s32 params_size = 0;
++	s32 err = BCME_OK;
++	struct net_device *dev = bcmcfg_to_prmry_ndev(cfg);
++	if (!in_atomic()) {
++		/* Our scan params only need space for 1 channel and 0 ssids */
++		params = wl_cfg80211_scan_alloc_params(-1, 0, &params_size);
++		if (params == NULL) {
++			WL_ERR(("scan params allocation failed \n"));
++			err = -ENOMEM;
++		} else {
++			/* Do a scan abort to stop the driver's scan engine */
++			err = wldev_ioctl(dev, WLC_SCAN, params, params_size, true);
++			if (err < 0) {
++				WL_ERR(("scan abort  failed \n"));
++			}
++			kfree(params);
++		}
++	}
++#ifdef WLTDLS
++	if (cfg->tdls_mgmt_frame) {
++		kfree(cfg->tdls_mgmt_frame);
++		cfg->tdls_mgmt_frame = NULL;
++	}
++#endif /* WLTDLS */
++}
++
++static s32 wl_notify_escan_complete(struct bcm_cfg80211 *cfg,
++	struct net_device *ndev,
++	bool aborted, bool fw_abort)
++{
++	s32 err = BCME_OK;
++	unsigned long flags;
++	struct net_device *dev;
++
++	WL_DBG(("Enter \n"));
++
++	mutex_lock(&cfg->scan_complete);
++
++	if (!ndev) {
++		WL_ERR(("ndev is null\n"));
++		err = BCME_ERROR;
++		goto out;
++	}
++
++	if (cfg->escan_info.ndev != ndev) {
++		WL_ERR(("ndev is different %p %p\n", cfg->escan_info.ndev, ndev));
++		err = BCME_ERROR;
++		goto out;
++	}
++
++	if (cfg->scan_request) {
++		dev = bcmcfg_to_prmry_ndev(cfg);
++#if defined(WL_ENABLE_P2P_IF)
++		if (cfg->scan_request->dev != cfg->p2p_net)
++			dev = cfg->scan_request->dev;
++#elif defined(WL_CFG80211_P2P_DEV_IF)
++		if (cfg->scan_request->wdev->iftype != NL80211_IFTYPE_P2P_DEVICE)
++			dev = cfg->scan_request->wdev->netdev;
++#endif /* WL_ENABLE_P2P_IF */
++	}
++	else {
++		WL_DBG(("cfg->scan_request is NULL may be internal scan."
++			"doing scan_abort for ndev %p primary %p",
++				ndev, bcmcfg_to_prmry_ndev(cfg)));
++		dev = ndev;
++	}
++	if (fw_abort && !in_atomic())
++		wl_cfg80211_scan_abort(cfg);
++	if (timer_pending(&cfg->scan_timeout))
++		del_timer_sync(&cfg->scan_timeout);
++#if defined(ESCAN_RESULT_PATCH)
++	if (likely(cfg->scan_request)) {
++		cfg->bss_list = wl_escan_get_buf(cfg, aborted);
++		wl_inform_bss(cfg);
++	}
++#endif /* ESCAN_RESULT_PATCH */
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++#ifdef WL_SCHED_SCAN
++	if (cfg->sched_scan_req && !cfg->scan_request) {
++		WL_PNO((">>> REPORTING SCHED SCAN RESULTS \n"));
++		if (!aborted)
++			cfg80211_sched_scan_results(cfg->sched_scan_req->wiphy);
++		cfg->sched_scan_running = FALSE;
++		cfg->sched_scan_req = NULL;
++	}
++#endif /* WL_SCHED_SCAN */
++	if (likely(cfg->scan_request)) {
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(4, 8, 0))
++		struct cfg80211_scan_info info;
++		info.aborted = aborted;
++		cfg80211_scan_done(cfg->scan_request, &info);
++#else
++		cfg80211_scan_done(cfg->scan_request, aborted);
++#endif
++		cfg->scan_request = NULL;
++		DHD_OS_SCAN_WAKE_UNLOCK((dhd_pub_t *)(cfg->pub));
++	}
++	if (p2p_is_on(cfg))
++		wl_clr_p2p_status(cfg, SCANNING);
++	wl_clr_drv_status(cfg, SCANNING, dev);
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++
++out:
++	mutex_unlock(&cfg->scan_complete);
++	return err;
++}
++
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++static void
++wl_cfg80211_find_removal_candidate(wl_bss_info_t *bss, removal_element_t *candidate)
++{
++	int idx;
++	for (idx = 0; idx < BUF_OVERFLOW_MGMT_COUNT; idx++) {
++		int len = BUF_OVERFLOW_MGMT_COUNT - idx - 1;
++		if (bss->RSSI < candidate[idx].RSSI) {
++			if (len)
++				memcpy(&candidate[idx + 1], &candidate[idx],
++					sizeof(removal_element_t) * len);
++			candidate[idx].RSSI = bss->RSSI;
++			candidate[idx].length = bss->length;
++			memcpy(&candidate[idx].BSSID, &bss->BSSID, ETHER_ADDR_LEN);
++			return;
++		}
++	}
++}
++
++static void
++wl_cfg80211_remove_lowRSSI_info(wl_scan_results_t *list, removal_element_t *candidate,
++	wl_bss_info_t *bi)
++{
++	int idx1, idx2;
++	int total_delete_len = 0;
++	for (idx1 = 0; idx1 < BUF_OVERFLOW_MGMT_COUNT; idx1++) {
++		int cur_len = WL_SCAN_RESULTS_FIXED_SIZE;
++		wl_bss_info_t *bss = NULL;
++		if (candidate[idx1].RSSI >= bi->RSSI)
++			continue;
++		for (idx2 = 0; idx2 < list->count; idx2++) {
++			bss = bss ? (wl_bss_info_t *)((uintptr)bss + dtoh32(bss->length)) :
++				list->bss_info;
++			if (!bcmp(&candidate[idx1].BSSID, &bss->BSSID, ETHER_ADDR_LEN) &&
++				candidate[idx1].RSSI == bss->RSSI &&
++				candidate[idx1].length == dtoh32(bss->length)) {
++				u32 delete_len = dtoh32(bss->length);
++				WL_DBG(("delete scan info of " MACDBG " to add new AP\n",
++					MAC2STRDBG(bss->BSSID.octet)));
++				if (idx2 < list->count -1) {
++					memmove((u8 *)bss, (u8 *)bss + delete_len,
++						list->buflen - cur_len - delete_len);
++				}
++				list->buflen -= delete_len;
++				list->count--;
++				total_delete_len += delete_len;
++				/* if delete_len is greater than or equal to result length */
++				if (total_delete_len >= bi->length) {
++					return;
++				}
++				break;
++			}
++			cur_len += dtoh32(bss->length);
++		}
++	}
++}
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++
++static s32 wl_escan_handler(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	s32 err = BCME_OK;
++	s32 status = ntoh32(e->status);
++	wl_bss_info_t *bi;
++	wl_escan_result_t *escan_result;
++	wl_bss_info_t *bss = NULL;
++	wl_scan_results_t *list;
++	wifi_p2p_ie_t * p2p_ie;
++	struct net_device *ndev = NULL;
++	u32 bi_length;
++	u32 i;
++	u8 *p2p_dev_addr = NULL;
++
++	WL_DBG((" enter event type : %d, status : %d \n",
++		ntoh32(e->event_type), ntoh32(e->status)));
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	mutex_lock(&cfg->usr_sync);
++	/* P2P SCAN is coming from primary interface */
++	if (wl_get_p2p_status(cfg, SCANNING)) {
++		if (wl_get_drv_status_all(cfg, SENDING_ACT_FRM))
++			ndev = cfg->afx_hdl->dev;
++		else
++			ndev = cfg->escan_info.ndev;
++
++	}
++	if (!ndev || (!wl_get_drv_status(cfg, SCANNING, ndev) && !cfg->sched_scan_running)) {
++		WL_ERR(("escan is not ready ndev %p drv_status 0x%x e_type %d e_states %d\n",
++			ndev, wl_get_drv_status(cfg, SCANNING, ndev),
++			ntoh32(e->event_type), ntoh32(e->status)));
++		goto exit;
++	}
++	escan_result = (wl_escan_result_t *)data;
++
++	if (status == WLC_E_STATUS_PARTIAL) {
++		WL_INFORM(("WLC_E_STATUS_PARTIAL \n"));
++		DBG_EVENT_LOG(cfg->pub, WIFI_EVENT_DRIVER_SCAN_RESULT_FOUND);
++		if (!escan_result) {
++			WL_ERR(("Invalid escan result (NULL pointer)\n"));
++			goto exit;
++		}
++		if ((dtoh32(escan_result->buflen) > (int)ESCAN_BUF_SIZE) ||
++		    (dtoh32(escan_result->buflen) < sizeof(wl_escan_result_t))) {
++			WL_ERR(("Invalid escan buffer len:%d\n", dtoh32(escan_result->buflen)));
++			goto exit;
++		}
++		if (dtoh16(escan_result->bss_count) != 1) {
++			WL_ERR(("Invalid bss_count %d: ignoring\n", escan_result->bss_count));
++			goto exit;
++		}
++		bi = escan_result->bss_info;
++		if (!bi) {
++			WL_ERR(("Invalid escan bss info (NULL pointer)\n"));
++			goto exit;
++		}
++		bi_length = dtoh32(bi->length);
++		if (bi_length != (dtoh32(escan_result->buflen) - WL_ESCAN_RESULTS_FIXED_SIZE)) {
++			WL_ERR(("Invalid bss_info length %d: ignoring\n", bi_length));
++			goto exit;
++		}
++		if (wl_escan_check_sync_id(status, escan_result->sync_id,
++			cfg->escan_info.cur_sync_id) < 0)
++			goto exit;
++
++		if (!(bcmcfg_to_wiphy(cfg)->interface_modes & BIT(NL80211_IFTYPE_ADHOC))) {
++			if (dtoh16(bi->capability) & DOT11_CAP_IBSS) {
++				WL_DBG(("Ignoring IBSS result\n"));
++				goto exit;
++			}
++		}
++
++		if (wl_get_drv_status_all(cfg, FINDING_COMMON_CHANNEL)) {
++			p2p_dev_addr = wl_cfgp2p_retreive_p2p_dev_addr(bi, bi_length);
++			if (p2p_dev_addr && !memcmp(p2p_dev_addr,
++				cfg->afx_hdl->tx_dst_addr.octet, ETHER_ADDR_LEN)) {
++				s32 channel = wf_chspec_ctlchan(
++					wl_chspec_driver_to_host(bi->chanspec));
++
++				if ((channel > MAXCHANNEL) || (channel <= 0))
++					channel = WL_INVALID;
++				else
++					WL_ERR(("ACTION FRAME SCAN : Peer " MACDBG " found,"
++						" channel : %d\n",
++						MAC2STRDBG(cfg->afx_hdl->tx_dst_addr.octet),
++						channel));
++
++				wl_clr_p2p_status(cfg, SCANNING);
++				cfg->afx_hdl->peer_chan = channel;
++				complete(&cfg->act_frm_scan);
++				goto exit;
++			}
++
++		} else {
++			int cur_len = WL_SCAN_RESULTS_FIXED_SIZE;
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++			removal_element_t candidate[BUF_OVERFLOW_MGMT_COUNT];
++			int remove_lower_rssi = FALSE;
++
++			bzero(candidate, sizeof(removal_element_t)*BUF_OVERFLOW_MGMT_COUNT);
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++
++			list = wl_escan_get_buf(cfg, FALSE);
++			if (scan_req_match(cfg)) {
++				/* p2p scan && allow only probe response */
++				if ((cfg->p2p->search_state != WL_P2P_DISC_ST_SCAN) &&
++					(bi->flags & WL_BSS_FLAGS_FROM_BEACON))
++					goto exit;
++				if ((p2p_ie = wl_cfgp2p_find_p2pie(((u8 *) bi) + bi->ie_offset,
++					bi->ie_length)) == NULL) {
++						WL_ERR(("Couldn't find P2PIE in probe"
++							" response/beacon\n"));
++						goto exit;
++				}
++			}
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++			if (bi_length > ESCAN_BUF_SIZE - list->buflen)
++				remove_lower_rssi = TRUE;
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++
++			for (i = 0; i < list->count; i++) {
++				bss = bss ? (wl_bss_info_t *)((uintptr)bss + dtoh32(bss->length))
++					: list->bss_info;
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++				WL_TRACE(("%s("MACDBG"), i=%d bss: RSSI %d list->count %d\n",
++					bss->SSID, MAC2STRDBG(bss->BSSID.octet),
++					i, bss->RSSI, list->count));
++
++				if (remove_lower_rssi)
++					wl_cfg80211_find_removal_candidate(bss, candidate);
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++
++				if (!bcmp(&bi->BSSID, &bss->BSSID, ETHER_ADDR_LEN) &&
++					(CHSPEC_BAND(wl_chspec_driver_to_host(bi->chanspec))
++					== CHSPEC_BAND(wl_chspec_driver_to_host(bss->chanspec))) &&
++					bi->SSID_len == bss->SSID_len &&
++					!bcmp(bi->SSID, bss->SSID, bi->SSID_len)) {
++
++					/* do not allow beacon data to update
++					*the data recd from a probe response
++					*/
++					if (!(bss->flags & WL_BSS_FLAGS_FROM_BEACON) &&
++						(bi->flags & WL_BSS_FLAGS_FROM_BEACON))
++						goto exit;
++
++					WL_DBG(("%s("MACDBG"), i=%d prev: RSSI %d"
++						" flags 0x%x, new: RSSI %d flags 0x%x\n",
++						bss->SSID, MAC2STRDBG(bi->BSSID.octet), i,
++						bss->RSSI, bss->flags, bi->RSSI, bi->flags));
++
++					if ((bss->flags & WL_BSS_FLAGS_RSSI_ONCHANNEL) ==
++						(bi->flags & WL_BSS_FLAGS_RSSI_ONCHANNEL)) {
++						/* preserve max RSSI if the measurements are
++						* both on-channel or both off-channel
++						*/
++						WL_SCAN(("%s("MACDBG"), same onchan"
++						", RSSI: prev %d new %d\n",
++						bss->SSID, MAC2STRDBG(bi->BSSID.octet),
++						bss->RSSI, bi->RSSI));
++						bi->RSSI = MAX(bss->RSSI, bi->RSSI);
++					} else if ((bss->flags & WL_BSS_FLAGS_RSSI_ONCHANNEL) &&
++						(bi->flags & WL_BSS_FLAGS_RSSI_ONCHANNEL) == 0) {
++						/* preserve the on-channel rssi measurement
++						* if the new measurement is off channel
++						*/
++						WL_SCAN(("%s("MACDBG"), prev onchan"
++						", RSSI: prev %d new %d\n",
++						bss->SSID, MAC2STRDBG(bi->BSSID.octet),
++						bss->RSSI, bi->RSSI));
++						bi->RSSI = bss->RSSI;
++						bi->flags |= WL_BSS_FLAGS_RSSI_ONCHANNEL;
++					}
++					if (dtoh32(bss->length) != bi_length) {
++						u32 prev_len = dtoh32(bss->length);
++
++						WL_SCAN(("bss info replacement"
++							" is occured(bcast:%d->probresp%d)\n",
++							bss->ie_length, bi->ie_length));
++						WL_DBG(("%s("MACDBG"), replacement!(%d -> %d)\n",
++						bss->SSID, MAC2STRDBG(bi->BSSID.octet),
++						prev_len, bi_length));
++
++						if (list->buflen - prev_len + bi_length
++							> ESCAN_BUF_SIZE) {
++							WL_ERR(("Buffer is too small: keep the"
++								" previous result of this AP\n"));
++							/* Only update RSSI */
++							bss->RSSI = bi->RSSI;
++							bss->flags |= (bi->flags
++								& WL_BSS_FLAGS_RSSI_ONCHANNEL);
++							goto exit;
++						}
++
++						if (i < list->count - 1) {
++							/* memory copy required by this case only */
++							memmove((u8 *)bss + bi_length,
++								(u8 *)bss + prev_len,
++								list->buflen - cur_len - prev_len);
++						}
++						list->buflen -= prev_len;
++						list->buflen += bi_length;
++					}
++					list->version = dtoh32(bi->version);
++					memcpy((u8 *)bss, (u8 *)bi, bi_length);
++					goto exit;
++				}
++				cur_len += dtoh32(bss->length);
++			}
++			if (bi_length > ESCAN_BUF_SIZE - list->buflen) {
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++				wl_cfg80211_remove_lowRSSI_info(list, candidate, bi);
++				if (bi_length > ESCAN_BUF_SIZE - list->buflen) {
++					WL_DBG(("RSSI(" MACDBG ") is too low(%d) to add Buffer\n",
++						MAC2STRDBG(bi->BSSID.octet), bi->RSSI));
++					goto exit;
++				}
++#else
++				WL_ERR(("Buffer is too small: ignoring\n"));
++				goto exit;
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++			}
++
++			memcpy(&(((char *)list)[list->buflen]), bi, bi_length);
++			list->version = dtoh32(bi->version);
++			list->buflen += bi_length;
++			list->count++;
++
++			/*
++			 * !Broadcast && number of ssid = 1 && number of channels =1
++			 * means specific scan to association
++			 */
++			if (wl_cfgp2p_is_p2p_specific_scan(cfg->scan_request)) {
++				WL_ERR(("P2P assoc scan fast aborted.\n"));
++				wl_notify_escan_complete(cfg, cfg->escan_info.ndev, false, true);
++				goto exit;
++			}
++		}
++	}
++	else if (status == WLC_E_STATUS_SUCCESS) {
++		cfg->escan_info.escan_state = WL_ESCAN_STATE_IDLE;
++		wl_escan_print_sync_id(status, cfg->escan_info.cur_sync_id,
++			escan_result->sync_id);
++
++		if (wl_get_drv_status_all(cfg, FINDING_COMMON_CHANNEL)) {
++			WL_INFORM(("ACTION FRAME SCAN DONE\n"));
++			wl_clr_p2p_status(cfg, SCANNING);
++			wl_clr_drv_status(cfg, SCANNING, cfg->afx_hdl->dev);
++			if (cfg->afx_hdl->peer_chan == WL_INVALID)
++				complete(&cfg->act_frm_scan);
++		} else if ((likely(cfg->scan_request)) || (cfg->sched_scan_running)) {
++			WL_INFORM(("ESCAN COMPLETED\n"));
++			DBG_EVENT_LOG(cfg->pub, WIFI_EVENT_DRIVER_SCAN_COMPLETE);
++			cfg->bss_list = wl_escan_get_buf(cfg, FALSE);
++			if (!scan_req_match(cfg)) {
++				WL_TRACE_HW4(("SCAN COMPLETED: scanned AP count=%d\n",
++					cfg->bss_list->count));
++			}
++			wl_inform_bss(cfg);
++			wl_notify_escan_complete(cfg, ndev, false, false);
++		}
++		wl_escan_increment_sync_id(cfg, SCAN_BUF_NEXT);
++	} else if ((status == WLC_E_STATUS_ABORT) || (status == WLC_E_STATUS_NEWSCAN) ||
++		(status == WLC_E_STATUS_11HQUIET) || (status == WLC_E_STATUS_CS_ABORT) ||
++		(status == WLC_E_STATUS_NEWASSOC)) {
++		/* Handle all cases of scan abort */
++		cfg->escan_info.escan_state = WL_ESCAN_STATE_IDLE;
++		wl_escan_print_sync_id(status, escan_result->sync_id,
++			cfg->escan_info.cur_sync_id);
++		WL_DBG(("ESCAN ABORT reason: %d\n", status));
++		if (wl_get_drv_status_all(cfg, FINDING_COMMON_CHANNEL)) {
++			WL_INFORM(("ACTION FRAME SCAN DONE\n"));
++			wl_clr_drv_status(cfg, SCANNING, cfg->afx_hdl->dev);
++			wl_clr_p2p_status(cfg, SCANNING);
++			if (cfg->afx_hdl->peer_chan == WL_INVALID)
++				complete(&cfg->act_frm_scan);
++		} else if ((likely(cfg->scan_request)) || (cfg->sched_scan_running)) {
++			WL_INFORM(("ESCAN ABORTED\n"));
++			cfg->bss_list = wl_escan_get_buf(cfg, TRUE);
++			if (!scan_req_match(cfg)) {
++				WL_TRACE_HW4(("scan_req_match=0: scanned AP count=%d\n",
++					cfg->bss_list->count));
++			}
++
++			wl_inform_bss(cfg);
++			wl_notify_escan_complete(cfg, ndev, true, false);
++		} else {
++			/* If there is no pending host initiated scan, do nothing */
++			WL_DBG(("ESCAN ABORT: No pending scans. Ignoring event.\n"));
++		}
++		wl_escan_increment_sync_id(cfg, SCAN_BUF_CNT);
++	} else if (status == WLC_E_STATUS_TIMEOUT) {
++		WL_ERR(("WLC_E_STATUS_TIMEOUT : scan_request[%p]\n", cfg->scan_request));
++		WL_ERR(("reason[0x%x]\n", e->reason));
++		if (e->reason == 0xFFFFFFFF) {
++			wl_notify_escan_complete(cfg, cfg->escan_info.ndev, true, true);
++		}
++	} else {
++		WL_ERR(("unexpected Escan Event %d : abort\n", status));
++		cfg->escan_info.escan_state = WL_ESCAN_STATE_IDLE;
++		wl_escan_print_sync_id(status, escan_result->sync_id,
++			cfg->escan_info.cur_sync_id);
++		if (wl_get_drv_status_all(cfg, FINDING_COMMON_CHANNEL)) {
++			WL_INFORM(("ACTION FRAME SCAN DONE\n"));
++			wl_clr_p2p_status(cfg, SCANNING);
++			wl_clr_drv_status(cfg, SCANNING, cfg->afx_hdl->dev);
++			if (cfg->afx_hdl->peer_chan == WL_INVALID)
++				complete(&cfg->act_frm_scan);
++		} else if ((likely(cfg->scan_request)) || (cfg->sched_scan_running)) {
++			cfg->bss_list = wl_escan_get_buf(cfg, TRUE);
++			if (!scan_req_match(cfg)) {
++				WL_TRACE_HW4(("SCAN ABORTED(UNEXPECTED): "
++					"scanned AP count=%d\n",
++					cfg->bss_list->count));
++			}
++			wl_inform_bss(cfg);
++			wl_notify_escan_complete(cfg, ndev, true, false);
++		}
++		wl_escan_increment_sync_id(cfg, 2);
++	}
++exit:
++	mutex_unlock(&cfg->usr_sync);
++	return err;
++}
++
++static void wl_cfg80211_concurrent_roam(struct bcm_cfg80211 *cfg, int enable)
++{
++	u32 connected_cnt  = wl_get_drv_status_all(cfg, CONNECTED);
++	bool p2p_connected  = wl_cfgp2p_vif_created(cfg);
++	struct net_info *iter, *next;
++	int err;
++
++	if (!(cfg->roam_flags & WL_ROAM_OFF_ON_CONCURRENT))
++		return;
++
++	WL_DBG(("roam off:%d p2p_connected:%d connected_cnt:%d \n",
++		enable, p2p_connected, connected_cnt));
++
++	/* Disable FW roam when we have a concurrent P2P connection */
++	if (enable && p2p_connected && connected_cnt > 1) {
++		/* Mark it as to be reverted */
++		cfg->roam_flags |= WL_ROAM_OFF_REVERT;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++		for_each_ndev(cfg, iter, next) {
++			if (iter->ndev) {
++				/* Save the current roam setting */
++				if ((err = wldev_iovar_getint(iter->ndev, "roam_off",
++					(s32 *)&iter->roam_off)) != BCME_OK) {
++					WL_ERR(("%s:Failed to get current roam setting err %d\n",
++						iter->ndev->name, err));
++					continue;
++				}
++				if ((err = wldev_iovar_setint(iter->ndev,
++						 "roam_off", 1)) != BCME_OK) {
++					WL_ERR((" %s:failed to set roam_off : %d\n",
++						iter->ndev->name, err));
++				}
++			}
++		}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	}
++	else if (!enable && (cfg->roam_flags & WL_ROAM_OFF_REVERT)) {
++		cfg->roam_flags &= ~WL_ROAM_OFF_REVERT;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++		for_each_ndev(cfg, iter, next) {
++			if (iter->ndev) {
++				if (iter->roam_off != WL_INVALID) {
++					if ((err = wldev_iovar_setint(iter->ndev, "roam_off",
++						iter->roam_off)) == BCME_OK)
++						iter->roam_off = WL_INVALID;
++					else {
++						WL_ERR((" %s:failed to set roam_off : %d\n",
++							iter->ndev->name, err));
++					}
++				}
++			}
++		}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	}
++
++	return;
++}
++
++static void wl_cfg80211_determine_vsdb_mode(struct bcm_cfg80211 *cfg)
++{
++	struct net_info *iter, *next;
++	u32 ctl_chan = 0;
++	u32 chanspec = 0;
++	u32 pre_ctl_chan = 0;
++	u32 connected_cnt  = wl_get_drv_status_all(cfg, CONNECTED);
++	cfg->vsdb_mode = false;
++
++	if (connected_cnt <= 1)  {
++		return;
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++	for_each_ndev(cfg, iter, next) {
++		/* p2p discovery iface ndev could be null */
++		if (iter->ndev) {
++			chanspec = 0;
++			ctl_chan = 0;
++			if (wl_get_drv_status(cfg, CONNECTED, iter->ndev)) {
++				if (wldev_iovar_getint(iter->ndev, "chanspec",
++					(s32 *)&chanspec) == BCME_OK) {
++					chanspec = wl_chspec_driver_to_host(chanspec);
++					ctl_chan = wf_chspec_ctlchan(chanspec);
++					wl_update_prof(cfg, iter->ndev, NULL,
++						&ctl_chan, WL_PROF_CHAN);
++				}
++				if (!cfg->vsdb_mode) {
++					if (!pre_ctl_chan && ctl_chan)
++						pre_ctl_chan = ctl_chan;
++					else if (pre_ctl_chan && (pre_ctl_chan != ctl_chan)) {
++						cfg->vsdb_mode = true;
++					}
++				}
++			}
++		}
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	WL_ERR(("%s concurrency is enabled\n", cfg->vsdb_mode ? "Multi Channel" : "Same Channel"));
++	return;
++}
++
++
++static s32 wl_notifier_change_state(struct bcm_cfg80211 *cfg, struct net_info *_net_info,
++	enum wl_status state, bool set)
++{
++	s32 pm = PM_FAST;
++	s32 err = BCME_OK;
++	u32 mode;
++	u32 chan = 0;
++	struct net_info *iter, *next;
++	struct net_device *primary_dev = bcmcfg_to_prmry_ndev(cfg);
++	dhd_pub_t *dhd =  (dhd_pub_t *)(cfg->pub);
++	if (dhd->busstate == DHD_BUS_DOWN) {
++		WL_ERR(("%s : busstate is DHD_BUS_DOWN!\n", __FUNCTION__));
++		return 0;
++	}
++	WL_DBG(("Enter state %d set %d _net_info->pm_restore %d iface %s\n",
++		state, set, _net_info->pm_restore, _net_info->ndev->name));
++
++	if (state != WL_STATUS_CONNECTED)
++		return 0;
++	mode = wl_get_mode_by_netdev(cfg, _net_info->ndev);
++	if (set) {
++		wl_cfg80211_concurrent_roam(cfg, 1);
++
++		if (mode == WL_MODE_AP) {
++
++			if (wl_add_remove_eventmsg(primary_dev, WLC_E_P2P_PROBREQ_MSG, false))
++				WL_ERR((" failed to unset WLC_E_P2P_PROPREQ_MSG\n"));
++		}
++		wl_cfg80211_determine_vsdb_mode(cfg);
++		if (cfg->vsdb_mode || _net_info->pm_block) {
++			/* Delete pm_enable_work */
++			wl_add_remove_pm_enable_work(cfg, FALSE, WL_HANDLER_MAINTAIN);
++			/* save PM_FAST in _net_info to restore this
++			 * if _net_info->pm_block is false
++			 */
++			if (!_net_info->pm_block && (mode == WL_MODE_BSS)) {
++				_net_info->pm = PM_FAST;
++				_net_info->pm_restore = true;
++			}
++			pm = PM_OFF;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++			for_each_ndev(cfg, iter, next) {
++				if (iter->pm_restore || (iter->ndev == NULL))
++					continue;
++				/* Save the current power mode */
++				err = wldev_ioctl(iter->ndev, WLC_GET_PM, &iter->pm,
++					sizeof(iter->pm), false);
++				WL_DBG(("%s:power save %s\n", iter->ndev->name,
++					iter->pm ? "enabled" : "disabled"));
++				if (!err && iter->pm) {
++					iter->pm_restore = true;
++				}
++			}
++			for_each_ndev(cfg, iter, next) {
++				if (iter->ndev) {
++					if (!wl_get_drv_status(cfg, CONNECTED, iter->ndev))
++						continue;
++					if ((err = wldev_ioctl(iter->ndev, WLC_SET_PM, &pm,
++						sizeof(pm), true)) != 0) {
++						if (err == -ENODEV)
++							WL_DBG(("%s:netdev not ready\n",
++								iter->ndev->name));
++						else
++							WL_ERR(("%s:error (%d)\n",
++								iter->ndev->name, err));
++						wl_cfg80211_update_power_mode(iter->ndev);
++					}
++				}
++			}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++		} else {
++			/* add PM Enable timer to go to power save mode
++			 * if supplicant control pm mode, it will be cleared or
++			 * updated by wl_cfg80211_set_power_mgmt() if not - for static IP & HW4 P2P,
++			 * PM will be configured when timer expired
++			 */
++
++			/*
++			 * before calling pm_enable_timer, we need to set PM -1 for all ndev
++			 */
++			pm = PM_OFF;
++			if (!_net_info->pm_block) {
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++				for_each_ndev(cfg, iter, next) {
++					if (iter->pm_restore || (iter->ndev == NULL))
++						continue;
++					/* Save the current power mode */
++					err = wldev_ioctl(iter->ndev, WLC_GET_PM, &iter->pm,
++						sizeof(iter->pm), false);
++					WL_DBG(("%s:power save %s\n", iter->ndev->name,
++						iter->pm ? "enabled" : "disabled"));
++					if (!err && iter->pm) {
++						iter->pm_restore = true;
++					}
++				}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++			}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++			for_each_ndev(cfg, iter, next) {
++				/* p2p discovery iface ndev ptr could be null */
++				if (iter->ndev) {
++					if (!wl_get_drv_status(cfg, CONNECTED, iter->ndev))
++						continue;
++					if ((err = wldev_ioctl(iter->ndev, WLC_SET_PM, &pm,
++						sizeof(pm), true)) != 0) {
++						if (err == -ENODEV)
++							WL_DBG(("%s:netdev not ready\n",
++								iter->ndev->name));
++						else
++							WL_ERR(("%s:error (%d)\n",
++								iter->ndev->name, err));
++					}
++				}
++			}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++			if (cfg->pm_enable_work_on) {
++				wl_add_remove_pm_enable_work(cfg, FALSE, WL_HANDLER_DEL);
++			}
++
++			cfg->pm_enable_work_on = true;
++#ifdef BCMSDIO
++			/* Temporary WAR: disable PM work till PM is fixed in 43012 */
++			if (dhd_get_chipid(dhd) != BCM43012_CHIP_ID)
++#endif
++				wl_add_remove_pm_enable_work(cfg, TRUE, WL_HANDLER_NOTUSE);
++
++		}
++#if defined(WLTDLS)
++#if defined(DISABLE_TDLS_IN_P2P)
++		if (cfg->vsdb_mode || p2p_is_on(cfg))
++#else
++		if (cfg->vsdb_mode)
++#endif /* defined(DISABLE_TDLS_IN_P2P) */
++		{
++
++			err = wldev_iovar_setint(primary_dev, "tdls_enable", 0);
++		}
++#endif /* defined(WLTDLS) */
++
++	}
++	 else { /* clear */
++		chan = 0;
++		/* clear chan information when the net device is disconnected */
++		wl_update_prof(cfg, _net_info->ndev, NULL, &chan, WL_PROF_CHAN);
++		wl_cfg80211_determine_vsdb_mode(cfg);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++		for_each_ndev(cfg, iter, next) {
++			/* P2P discovery interface ndev ptr could be NULL */
++			if (iter->ndev) {
++				if (iter->pm_restore && iter->pm) {
++					WL_DBG(("%s:restoring power save %s\n", iter->ndev->name,
++						(iter->pm ? "enabled" : "disabled")));
++					err = wldev_ioctl(iter->ndev,
++						WLC_SET_PM, &iter->pm, sizeof(iter->pm), true);
++					if (unlikely(err)) {
++						if (err == -ENODEV)
++							WL_DBG(("%s:netdev not ready\n",
++								iter->ndev->name));
++						else
++							WL_ERR(("%s:error(%d)\n",
++								iter->ndev->name, err));
++						break;
++					}
++					iter->pm_restore = 0;
++					wl_cfg80211_update_power_mode(iter->ndev);
++				}
++			}
++		}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++		wl_cfg80211_concurrent_roam(cfg, 0);
++#if defined(WLTDLS)
++		if (!cfg->vsdb_mode) {
++			err = wldev_iovar_setint(primary_dev, "tdls_enable", 1);
++		}
++#endif /* defined(WLTDLS) */
++
++	}
++	return err;
++}
++static s32 wl_init_scan(struct bcm_cfg80211 *cfg)
++{
++	int err = 0;
++
++	cfg->evt_handler[WLC_E_ESCAN_RESULT] = wl_escan_handler;
++	cfg->escan_info.escan_state = WL_ESCAN_STATE_IDLE;
++	wl_escan_init_sync_id(cfg);
++
++	/* Init scan_timeout timer */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++	timer_setup(&cfg->scan_timeout, wl_scan_timeout, 0);
++#else
++	init_timer(&cfg->scan_timeout);
++	cfg->scan_timeout.data = (unsigned long) cfg;
++	cfg->scan_timeout.function = wl_scan_timeout;
++#endif
++
++	return err;
++}
++
++#ifdef DHD_LOSSLESS_ROAMING
++static s32 wl_init_roam_timeout(struct bcm_cfg80211 *cfg)
++{
++	int err = 0;
++
++	/* Init roam timer */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++	timer_setup(&cfg->roam_timeout, wl_roam_timeout, 0);
++#else
++	init_timer(&cfg->roam_timeout);
++	cfg->roam_timeout.data = (unsigned long) cfg;
++	cfg->roam_timeout.function = wl_roam_timeout;
++#endif
++
++	return err;
++}
++#endif /* DHD_LOSSLESS_ROAMING */
++
++static s32 wl_init_priv(struct bcm_cfg80211 *cfg)
++{
++	struct wiphy *wiphy = bcmcfg_to_wiphy(cfg);
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	s32 err = 0;
++
++	cfg->scan_request = NULL;
++	cfg->pwr_save = !!(wiphy->flags & WIPHY_FLAG_PS_ON_BY_DEFAULT);
++	cfg->roam_on = false;
++	cfg->active_scan = true;
++	cfg->rf_blocked = false;
++	cfg->vsdb_mode = false;
++#if defined(BCMSDIO) || defined(BCMDBUS)
++	cfg->wlfc_on = false;
++#endif /* defined(BCMSDIO) || defined(BCMDBUS) */
++	cfg->roam_flags |= WL_ROAM_OFF_ON_CONCURRENT;
++	cfg->disable_roam_event = false;
++	cfg->cfgdev_bssidx = -1;
++	/* register interested state */
++	set_bit(WL_STATUS_CONNECTED, &cfg->interrested_state);
++	spin_lock_init(&cfg->cfgdrv_lock);
++	mutex_init(&cfg->ioctl_buf_sync);
++	init_waitqueue_head(&cfg->netif_change_event);
++	init_completion(&cfg->send_af_done);
++	init_completion(&cfg->iface_disable);
++	wl_init_eq(cfg);
++	err = wl_init_priv_mem(cfg);
++	if (err)
++		return err;
++	if (wl_create_event_handler(cfg))
++		return -ENOMEM;
++	wl_init_event_handler(cfg);
++	mutex_init(&cfg->usr_sync);
++	mutex_init(&cfg->event_sync);
++	mutex_init(&cfg->scan_complete);
++	err = wl_init_scan(cfg);
++	if (err)
++		return err;
++#ifdef DHD_LOSSLESS_ROAMING
++	err = wl_init_roam_timeout(cfg);
++	if (err) {
++		return err;
++	}
++#endif /* DHD_LOSSLESS_ROAMING */
++	wl_init_conf(cfg->conf);
++	wl_init_prof(cfg, ndev);
++	wl_link_down(cfg);
++	DNGL_FUNC(dhd_cfg80211_init, (cfg));
++
++	return err;
++}
++
++static void wl_deinit_priv(struct bcm_cfg80211 *cfg)
++{
++	DNGL_FUNC(dhd_cfg80211_deinit, (cfg));
++	wl_destroy_event_handler(cfg);
++	wl_flush_eq(cfg);
++	wl_link_down(cfg);
++	del_timer_sync(&cfg->scan_timeout);
++#ifdef DHD_LOSSLESS_ROAMING
++	del_timer_sync(&cfg->roam_timeout);
++#endif
++	wl_deinit_priv_mem(cfg);
++	if (wl_cfg80211_netdev_notifier_registered) {
++		wl_cfg80211_netdev_notifier_registered = FALSE;
++		unregister_netdevice_notifier(&wl_cfg80211_netdev_notifier);
++	}
++}
++
++#if defined(WL_ENABLE_P2P_IF)
++static s32 wl_cfg80211_attach_p2p(void)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++
++	WL_TRACE(("Enter \n"));
++
++	if (wl_cfgp2p_register_ndev(cfg) < 0) {
++		WL_ERR(("P2P attach failed. \n"));
++		return -ENODEV;
++	}
++
++	return 0;
++}
++
++static s32  wl_cfg80211_detach_p2p(void)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	struct wireless_dev *wdev;
++
++	WL_DBG(("Enter \n"));
++	if (!cfg) {
++		WL_ERR(("Invalid Ptr\n"));
++		return -EINVAL;
++	} else
++		wdev = cfg->p2p_wdev;
++
++	if (!wdev) {
++		WL_ERR(("Invalid Ptr\n"));
++		return -EINVAL;
++	}
++
++	wl_cfgp2p_unregister_ndev(cfg);
++
++	cfg->p2p_wdev = NULL;
++	cfg->p2p_net = NULL;
++	WL_DBG(("Freeing 0x%p \n", wdev));
++	kfree(wdev);
++
++	return 0;
++}
++#endif 
++
++s32 wl_cfg80211_attach_post(struct net_device *ndev)
++{
++	struct bcm_cfg80211 * cfg = NULL;
++	s32 err = 0;
++	s32 ret = 0;
++	WL_TRACE(("In\n"));
++	if (unlikely(!ndev)) {
++		WL_ERR(("ndev is invaild\n"));
++		return -ENODEV;
++	}
++	cfg = g_bcm_cfg;
++	if (unlikely(!cfg)) {
++		WL_ERR(("cfg is invaild\n"));
++		return -EINVAL;
++	}
++	if (!wl_get_drv_status(cfg, READY, ndev)) {
++		if (cfg->wdev) {
++			ret = wl_cfgp2p_supported(cfg, ndev);
++			if (ret > 0) {
++#if !defined(WL_ENABLE_P2P_IF)
++				cfg->wdev->wiphy->interface_modes |=
++					(BIT(NL80211_IFTYPE_P2P_CLIENT)|
++					BIT(NL80211_IFTYPE_P2P_GO));
++#endif /* !WL_ENABLE_P2P_IF */
++				if ((err = wl_cfgp2p_init_priv(cfg)) != 0)
++					goto fail;
++
++#if defined(WL_ENABLE_P2P_IF)
++				if (cfg->p2p_net) {
++					/* Update MAC addr for p2p0 interface here. */
++					memcpy(cfg->p2p_net->dev_addr, ndev->dev_addr, ETH_ALEN);
++					cfg->p2p_net->dev_addr[0] |= 0x02;
++					WL_ERR(("%s: p2p_dev_addr="MACDBG "\n",
++						cfg->p2p_net->name,
++						MAC2STRDBG(cfg->p2p_net->dev_addr)));
++				} else {
++					WL_ERR(("p2p_net not yet populated."
++					" Couldn't update the MAC Address for p2p0 \n"));
++					return -ENODEV;
++				}
++#endif /* WL_ENABLE_P2P_IF */
++				cfg->p2p_supported = true;
++			} else if (ret == 0) {
++				if ((err = wl_cfgp2p_init_priv(cfg)) != 0)
++					goto fail;
++			} else {
++				/* SDIO bus timeout */
++				err = -ENODEV;
++				goto fail;
++			}
++		}
++	}
++	wl_set_drv_status(cfg, READY, ndev);
++fail:
++	return err;
++}
++
++s32 wl_cfg80211_attach(struct net_device *ndev, void *context)
++{
++	struct wireless_dev *wdev;
++	struct bcm_cfg80211 *cfg;
++	s32 err = 0;
++	struct device *dev;
++
++	WL_TRACE(("In\n"));
++	if (!ndev) {
++		WL_ERR(("ndev is invaild\n"));
++		return -ENODEV;
++	}
++	WL_DBG(("func %p\n", wl_cfg80211_get_parent_dev()));
++	dev = wl_cfg80211_get_parent_dev();
++
++	wdev = kzalloc(sizeof(*wdev), GFP_KERNEL);
++	if (unlikely(!wdev)) {
++		WL_ERR(("Could not allocate wireless device\n"));
++		return -ENOMEM;
++	}
++	err = wl_setup_wiphy(wdev, dev, context);
++	if (unlikely(err)) {
++		kfree(wdev);
++		return -ENOMEM;
++	}
++	wdev->iftype = wl_mode_to_nl80211_iftype(WL_MODE_BSS);
++	cfg = (struct bcm_cfg80211 *)wiphy_priv(wdev->wiphy);
++	cfg->wdev = wdev;
++	cfg->pub = context;
++	INIT_LIST_HEAD(&cfg->net_list);
++	spin_lock_init(&cfg->net_list_sync);
++	ndev->ieee80211_ptr = wdev;
++	SET_NETDEV_DEV(ndev, wiphy_dev(wdev->wiphy));
++	wdev->netdev = ndev;
++	cfg->state_notifier = wl_notifier_change_state;
++	err = wl_alloc_netinfo(cfg, ndev, wdev, WL_MODE_BSS, PM_ENABLE, 0);
++	if (err) {
++		WL_ERR(("Failed to alloc net_info (%d)\n", err));
++		goto cfg80211_attach_out;
++	}
++	err = wl_init_priv(cfg);
++	if (err) {
++		WL_ERR(("Failed to init iwm_priv (%d)\n", err));
++		goto cfg80211_attach_out;
++	}
++
++	err = wl_setup_rfkill(cfg, TRUE);
++	if (err) {
++		WL_ERR(("Failed to setup rfkill %d\n", err));
++		goto cfg80211_attach_out;
++	}
++#ifdef DEBUGFS_CFG80211
++	err = wl_setup_debugfs(cfg);
++	if (err) {
++		WL_ERR(("Failed to setup debugfs %d\n", err));
++		goto cfg80211_attach_out;
++	}
++#endif
++	if (!wl_cfg80211_netdev_notifier_registered) {
++		wl_cfg80211_netdev_notifier_registered = TRUE;
++		err = register_netdevice_notifier(&wl_cfg80211_netdev_notifier);
++		if (err) {
++			wl_cfg80211_netdev_notifier_registered = FALSE;
++			WL_ERR(("Failed to register notifierl %d\n", err));
++			goto cfg80211_attach_out;
++		}
++	}
++#if defined(COEX_DHCP)
++	cfg->btcoex_info = wl_cfg80211_btcoex_init(cfg->wdev->netdev);
++	if (!cfg->btcoex_info)
++		goto cfg80211_attach_out;
++#endif 
++
++	g_bcm_cfg = cfg;
++
++#ifdef CONFIG_CFG80211_INTERNAL_REGDB
++	wdev->wiphy->reg_notifier = wl_cfg80211_reg_notifier;
++#endif /* CONFIG_CFG80211_INTERNAL_REGDB */
++
++#if defined(WL_ENABLE_P2P_IF)
++	err = wl_cfg80211_attach_p2p();
++	if (err)
++		goto cfg80211_attach_out;
++#endif 
++
++	return err;
++
++cfg80211_attach_out:
++	wl_setup_rfkill(cfg, FALSE);
++	wl_free_wdev(cfg);
++	return err;
++}
++
++void wl_cfg80211_detach(void *para)
++{
++	struct bcm_cfg80211 *cfg;
++
++	(void)para;
++	cfg = g_bcm_cfg;
++
++	WL_TRACE(("In\n"));
++
++	wl_add_remove_pm_enable_work(cfg, FALSE, WL_HANDLER_DEL);
++
++#if defined(COEX_DHCP)
++	wl_cfg80211_btcoex_deinit();
++	cfg->btcoex_info = NULL;
++#endif 
++
++	wl_setup_rfkill(cfg, FALSE);
++#ifdef DEBUGFS_CFG80211
++	wl_free_debugfs(cfg);
++#endif
++	if (cfg->p2p_supported) {
++		if (timer_pending(&cfg->p2p->listen_timer))
++			del_timer_sync(&cfg->p2p->listen_timer);
++		wl_cfgp2p_deinit_priv(cfg);
++	}
++
++	if (timer_pending(&cfg->scan_timeout))
++		del_timer_sync(&cfg->scan_timeout);
++#ifdef DHD_LOSSLESS_ROAMING
++	if (timer_pending(&cfg->roam_timeout)) {
++		del_timer_sync(&cfg->roam_timeout);
++	}
++#endif /* DHD_LOSSLESS_ROAMING */
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	if (cfg->p2p_wdev)
++		wl_cfgp2p_del_p2p_disc_if(cfg->p2p_wdev, cfg);
++#endif /* WL_CFG80211_P2P_DEV_IF  */
++#if defined(WL_ENABLE_P2P_IF)
++	wl_cfg80211_detach_p2p();
++#endif 
++
++	wl_cfg80211_ibss_vsie_free(cfg);
++	wl_cfg80211_clear_mgmt_vndr_ies(cfg);
++	wl_deinit_priv(cfg);
++	g_bcm_cfg = NULL;
++	wl_cfg80211_clear_parent_dev();
++	wl_free_wdev(cfg);
++	/* PLEASE do NOT call any function after wl_free_wdev, the driver's private
++	 * structure "cfg", which is the private part of wiphy, has been freed in
++	 * wl_free_wdev !!!!!!!!!!!
++	 */
++}
++
++static void wl_wakeup_event(struct bcm_cfg80211 *cfg)
++{
++	if (cfg->event_tsk.thr_pid >= 0) {
++		DHD_OS_WAKE_LOCK(cfg->pub);
++		up(&cfg->event_tsk.sema);
++	}
++}
++
++static s32 wl_event_handler(void *data)
++{
++	struct bcm_cfg80211 *cfg = NULL;
++	struct wl_event_q *e;
++	tsk_ctl_t *tsk = (tsk_ctl_t *)data;
++	struct wireless_dev *wdev = NULL;
++
++	cfg = (struct bcm_cfg80211 *)tsk->parent;
++
++	WL_ERR(("tsk Enter, tsk = 0x%p\n", tsk));
++
++	while (down_interruptible (&tsk->sema) == 0) {
++		SMP_RD_BARRIER_DEPENDS();
++		if (tsk->terminated) {
++			DHD_OS_WAKE_UNLOCK(cfg->pub);
++			break;
++		}
++		while ((e = wl_deq_event(cfg))) {
++			WL_DBG(("event type (%d), ifidx: %d bssidx: %d \n",
++				e->etype, e->emsg.ifidx, e->emsg.bsscfgidx));
++
++			if (e->emsg.ifidx > WL_MAX_IFS) {
++				WL_ERR((" Event ifidx not in range. val:%d \n", e->emsg.ifidx));
++				goto fail;
++			}
++			if (e->etype == WLC_E_TDLS_PEER_EVENT)
++				wdev = wl_get_wdev_by_bssidx(cfg, e->emsg.ifidx);
++			else
++				wdev = wl_get_wdev_by_bssidx(cfg, e->emsg.bsscfgidx);
++
++			if (!wdev) {
++				/* For WLC_E_IF would be handled by wl_host_event */
++				if (e->etype != WLC_E_IF)
++					WL_ERR(("No wdev corresponding to bssidx: 0x%x found!"
++						" Ignoring event.\n", e->emsg.bsscfgidx));
++			} else if (e->etype < WLC_E_LAST && cfg->evt_handler[e->etype]) {
++				dhd_pub_t *dhd = (struct dhd_pub *)(cfg->pub);
++				if (dhd->busstate == DHD_BUS_DOWN) {
++					WL_ERR((": BUS is DOWN.\n"));
++				} else
++					cfg->evt_handler[e->etype](cfg, wdev_to_cfgdev(wdev),
++						&e->emsg, e->edata);
++			} else {
++				WL_DBG(("Unknown Event (%d): ignoring\n", e->etype));
++			}
++fail:
++			wl_put_event(e);
++		}
++		DHD_OS_WAKE_UNLOCK(cfg->pub);
++	}
++	WL_ERR(("was terminated\n"));
++	complete_and_exit(&tsk->completed, 0);
++	return 0;
++}
++
++void
++wl_cfg80211_event(struct net_device *ndev, const wl_event_msg_t * e, void *data)
++{
++	u32 event_type = ntoh32(e->event_type);
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	struct net_info *netinfo;
++
++#if (WL_DBG_LEVEL > 0)
++	s8 *estr = (event_type <= sizeof(wl_dbg_estr) / WL_DBG_ESTR_MAX - 1) ?
++	    wl_dbg_estr[event_type] : (s8 *) "Unknown";
++	WL_DBG(("event_type (%d):" "WLC_E_" "%s\n", event_type, estr));
++#endif /* (WL_DBG_LEVEL > 0) */
++
++	if ((cfg == NULL) || (cfg->p2p_supported && cfg->p2p == NULL)) {
++		WL_ERR(("Stale event ignored\n"));
++		return;
++	}
++	if (wl_get_p2p_status(cfg, IF_CHANGING) || wl_get_p2p_status(cfg, IF_ADDING)) {
++		WL_ERR(("during IF change, ignore event %d\n", event_type));
++		return;
++	}
++
++	if (event_type == WLC_E_TDLS_PEER_EVENT)
++		netinfo = wl_get_netinfo_by_netdev(cfg, ndev);
++	else
++		netinfo = wl_get_netinfo_by_bssidx(cfg, e->bsscfgidx);
++
++	if (!netinfo) {
++		/* Since the netinfo entry is not there, the netdev entry is not
++		 * created via cfg80211 interface. so the event is not of interest
++		 * to the cfg80211 layer.
++		 */
++		WL_ERR(("ignore event %d, not interested\n", event_type));
++		return;
++	}
++
++	if (event_type == WLC_E_PFN_NET_FOUND) {
++		WL_DBG((" PNOEVENT: PNO_NET_FOUND\n"));
++	}
++	else if (event_type == WLC_E_PFN_NET_LOST) {
++		WL_DBG((" PNOEVENT: PNO_NET_LOST\n"));
++	}
++
++	if (likely(!wl_enq_event(cfg, ndev, event_type, e, data)))
++		wl_wakeup_event(cfg);
++}
++
++static void wl_init_eq(struct bcm_cfg80211 *cfg)
++{
++	wl_init_eq_lock(cfg);
++	INIT_LIST_HEAD(&cfg->eq_list);
++}
++
++static void wl_flush_eq(struct bcm_cfg80211 *cfg)
++{
++	struct wl_event_q *e;
++	unsigned long flags;
++
++	flags = wl_lock_eq(cfg);
++	while (!list_empty_careful(&cfg->eq_list)) {
++		BCM_SET_LIST_FIRST_ENTRY(e, &cfg->eq_list, struct wl_event_q, eq_list);
++		list_del(&e->eq_list);
++		kfree(e);
++	}
++	wl_unlock_eq(cfg, flags);
++}
++
++/*
++* retrieve first queued event from head
++*/
++
++static struct wl_event_q *wl_deq_event(struct bcm_cfg80211 *cfg)
++{
++	struct wl_event_q *e = NULL;
++	unsigned long flags;
++
++	flags = wl_lock_eq(cfg);
++	if (likely(!list_empty(&cfg->eq_list))) {
++		BCM_SET_LIST_FIRST_ENTRY(e, &cfg->eq_list, struct wl_event_q, eq_list);
++		list_del(&e->eq_list);
++	}
++	wl_unlock_eq(cfg, flags);
++
++	return e;
++}
++
++/*
++ * push event to tail of the queue
++ */
++
++static s32
++wl_enq_event(struct bcm_cfg80211 *cfg, struct net_device *ndev, u32 event,
++	const wl_event_msg_t *msg, void *data)
++{
++	struct wl_event_q *e;
++	s32 err = 0;
++	uint32 evtq_size;
++	uint32 data_len;
++	unsigned long flags;
++	gfp_t aflags;
++
++	data_len = 0;
++	if (data)
++		data_len = ntoh32(msg->datalen);
++	evtq_size = sizeof(struct wl_event_q) + data_len;
++	aflags = (in_atomic()) ? GFP_ATOMIC : GFP_KERNEL;
++	e = kzalloc(evtq_size, aflags);
++	if (unlikely(!e)) {
++		WL_ERR(("event alloc failed\n"));
++		return -ENOMEM;
++	}
++	e->etype = event;
++	memcpy(&e->emsg, msg, sizeof(wl_event_msg_t));
++	if (data)
++		memcpy(e->edata, data, data_len);
++	flags = wl_lock_eq(cfg);
++	list_add_tail(&e->eq_list, &cfg->eq_list);
++	wl_unlock_eq(cfg, flags);
++
++	return err;
++}
++
++static void wl_put_event(struct wl_event_q *e)
++{
++	kfree(e);
++}
++
++static s32 wl_config_ifmode(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 iftype)
++{
++	s32 infra = 0;
++	s32 err = 0;
++	s32 mode = 0;
++	switch (iftype) {
++	case NL80211_IFTYPE_MONITOR:
++	case NL80211_IFTYPE_WDS:
++		WL_ERR(("type (%d) : currently we do not support this mode\n",
++			iftype));
++		err = -EINVAL;
++		return err;
++	case NL80211_IFTYPE_ADHOC:
++		mode = WL_MODE_IBSS;
++		break;
++	case NL80211_IFTYPE_STATION:
++	case NL80211_IFTYPE_P2P_CLIENT:
++		mode = WL_MODE_BSS;
++		infra = 1;
++		break;
++	case NL80211_IFTYPE_AP:
++	case NL80211_IFTYPE_P2P_GO:
++		mode = WL_MODE_AP;
++		infra = 1;
++		break;
++	default:
++		err = -EINVAL;
++		WL_ERR(("invalid type (%d)\n", iftype));
++		return err;
++	}
++	infra = htod32(infra);
++	err = wldev_ioctl(ndev, WLC_SET_INFRA, &infra, sizeof(infra), true);
++	if (unlikely(err)) {
++		WL_ERR(("WLC_SET_INFRA error (%d)\n", err));
++		return err;
++	}
++
++	wl_set_mode_by_netdev(cfg, ndev, mode);
++
++	return 0;
++}
++
++void wl_cfg80211_add_to_eventbuffer(struct wl_eventmsg_buf *ev, u16 event, bool set)
++{
++	if (!ev || (event > WLC_E_LAST))
++		return;
++
++	if (ev->num < MAX_EVENT_BUF_NUM) {
++		ev->event[ev->num].type = event;
++		ev->event[ev->num].set = set;
++		ev->num++;
++	} else {
++		WL_ERR(("evenbuffer doesn't support > %u events. Update"
++			" the define MAX_EVENT_BUF_NUM \n", MAX_EVENT_BUF_NUM));
++		ASSERT(0);
++	}
++}
++
++s32 wl_cfg80211_apply_eventbuffer(
++	struct net_device *ndev,
++	struct bcm_cfg80211 *cfg,
++	wl_eventmsg_buf_t *ev)
++{
++	char eventmask[WL_EVENTING_MASK_LEN];
++	int i, ret = 0;
++	s8 iovbuf[WL_EVENTING_MASK_LEN + 12];
++
++	if (!ev || (!ev->num))
++		return -EINVAL;
++
++	mutex_lock(&cfg->event_sync);
++
++	/* Read event_msgs mask */
++	ret = wldev_iovar_getbuf(ndev, "event_msgs", NULL, 0, iovbuf, sizeof(iovbuf), NULL);
++	if (unlikely(ret)) {
++		WL_ERR(("Get event_msgs error (%d)\n", ret));
++		goto exit;
++	}
++	memcpy(eventmask, iovbuf, WL_EVENTING_MASK_LEN);
++
++	/* apply the set bits */
++	for (i = 0; i < ev->num; i++) {
++		if (ev->event[i].set)
++			setbit(eventmask, ev->event[i].type);
++		else
++			clrbit(eventmask, ev->event[i].type);
++	}
++
++	/* Write updated Event mask */
++	ret = wldev_iovar_setbuf(ndev, "event_msgs", eventmask, sizeof(eventmask), iovbuf,
++		sizeof(iovbuf), NULL);
++	if (unlikely(ret)) {
++		WL_ERR(("Set event_msgs error (%d)\n", ret));
++	}
++
++exit:
++	mutex_unlock(&cfg->event_sync);
++	return ret;
++}
++
++s32 wl_add_remove_eventmsg(struct net_device *ndev, u16 event, bool add)
++{
++	s8 iovbuf[WL_EVENTING_MASK_LEN + 12];
++	s8 eventmask[WL_EVENTING_MASK_LEN];
++	s32 err = 0;
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++
++	if (!ndev || !cfg)
++		return -ENODEV;
++
++	mutex_lock(&cfg->event_sync);
++
++	/* Setup event_msgs */
++	err = wldev_iovar_getbuf(ndev, "event_msgs", NULL, 0, iovbuf, sizeof(iovbuf), NULL);
++	if (unlikely(err)) {
++		WL_ERR(("Get event_msgs error (%d)\n", err));
++		goto eventmsg_out;
++	}
++	memcpy(eventmask, iovbuf, WL_EVENTING_MASK_LEN);
++	if (add) {
++		setbit(eventmask, event);
++	} else {
++		clrbit(eventmask, event);
++	}
++	err = wldev_iovar_setbuf(ndev, "event_msgs", eventmask, WL_EVENTING_MASK_LEN, iovbuf,
++		sizeof(iovbuf), NULL);
++	if (unlikely(err)) {
++		WL_ERR(("Set event_msgs error (%d)\n", err));
++		goto eventmsg_out;
++	}
++
++eventmsg_out:
++	mutex_unlock(&cfg->event_sync);
++	return err;
++}
++
++static int wl_construct_reginfo(struct bcm_cfg80211 *cfg, s32 bw_cap)
++{
++	struct net_device *dev = bcmcfg_to_prmry_ndev(cfg);
++	struct ieee80211_channel *band_chan_arr = NULL;
++	wl_uint32_list_t *list;
++	u32 i, j, index, n_2g, n_5g, band, channel, array_size;
++	u32 *n_cnt = NULL;
++	chanspec_t c = 0;
++	s32 err = BCME_OK;
++	bool update;
++	bool ht40_allowed;
++	u8 *pbuf = NULL;
++	bool dfs_radar_disabled = FALSE;
++
++#define LOCAL_BUF_LEN 1024
++	pbuf = kzalloc(LOCAL_BUF_LEN, GFP_KERNEL);
++
++	if (pbuf == NULL) {
++		WL_ERR(("failed to allocate local buf\n"));
++		return -ENOMEM;
++	}
++
++	err = wldev_iovar_getbuf_bsscfg(dev, "chanspecs", NULL,
++		0, pbuf, LOCAL_BUF_LEN, 0, &cfg->ioctl_buf_sync);
++	if (err != 0) {
++		WL_ERR(("get chanspecs failed with %d\n", err));
++		kfree(pbuf);
++		return err;
++	}
++#undef LOCAL_BUF_LEN
++
++	list = (wl_uint32_list_t *)(void *)pbuf;
++	band = array_size = n_2g = n_5g = 0;
++	for (i = 0; i < dtoh32(list->count); i++) {
++		index = 0;
++		update = false;
++		ht40_allowed = false;
++		c = (chanspec_t)dtoh32(list->element[i]);
++		c = wl_chspec_driver_to_host(c);
++		channel = wf_chspec_ctlchan(c);
++
++		if (!CHSPEC_IS40(c) && ! CHSPEC_IS20(c)) {
++			WL_DBG(("HT80/160/80p80 center channel : %d\n", channel));
++			continue;
++		}
++		if (CHSPEC_IS2G(c) && (channel >= CH_MIN_2G_CHANNEL) &&
++			(channel <= CH_MAX_2G_CHANNEL)) {
++			band_chan_arr = __wl_2ghz_channels;
++			array_size = ARRAYSIZE(__wl_2ghz_channels);
++			n_cnt = &n_2g;
++			band = IEEE80211_BAND_2GHZ;
++			ht40_allowed = (bw_cap  == WLC_N_BW_40ALL)? true : false;
++		} else if (CHSPEC_IS5G(c) && channel >= CH_MIN_5G_CHANNEL) {
++			band_chan_arr = __wl_5ghz_a_channels;
++			array_size = ARRAYSIZE(__wl_5ghz_a_channels);
++			n_cnt = &n_5g;
++			band = IEEE80211_BAND_5GHZ;
++			ht40_allowed = (bw_cap  == WLC_N_BW_20ALL)? false : true;
++		} else {
++			WL_ERR(("Invalid channel Sepc. 0x%x.\n", c));
++			continue;
++		}
++		if (!ht40_allowed && CHSPEC_IS40(c))
++			continue;
++		for (j = 0; (j < *n_cnt && (*n_cnt < array_size)); j++) {
++			if (band_chan_arr[j].hw_value == channel) {
++				update = true;
++				break;
++			}
++		}
++		if (update)
++			index = j;
++		else
++			index = *n_cnt;
++		if (index <  array_size) {
++#if LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 38)
++			band_chan_arr[index].center_freq =
++				ieee80211_channel_to_frequency(channel);
++#else
++			band_chan_arr[index].center_freq =
++				ieee80211_channel_to_frequency(channel, band);
++#endif
++			band_chan_arr[index].hw_value = channel;
++			band_chan_arr[index].beacon_found = false;
++
++			if (CHSPEC_IS40(c) && ht40_allowed) {
++				/* assuming the order is HT20, HT40 Upper,
++				 *  HT40 lower from chanspecs
++				 */
++				u32 ht40_flag = band_chan_arr[index].flags & IEEE80211_CHAN_NO_HT40;
++				if (CHSPEC_SB_UPPER(c)) {
++					if (ht40_flag == IEEE80211_CHAN_NO_HT40)
++						band_chan_arr[index].flags &=
++							~IEEE80211_CHAN_NO_HT40;
++					band_chan_arr[index].flags |= IEEE80211_CHAN_NO_HT40PLUS;
++				} else {
++					/* It should be one of
++					 * IEEE80211_CHAN_NO_HT40 or IEEE80211_CHAN_NO_HT40PLUS
++					 */
++					band_chan_arr[index].flags &= ~IEEE80211_CHAN_NO_HT40;
++					if (ht40_flag == IEEE80211_CHAN_NO_HT40)
++						band_chan_arr[index].flags |=
++							IEEE80211_CHAN_NO_HT40MINUS;
++				}
++			} else {
++				band_chan_arr[index].flags = IEEE80211_CHAN_NO_HT40;
++				if (!dfs_radar_disabled) {
++					if (band == IEEE80211_BAND_2GHZ)
++						channel |= WL_CHANSPEC_BAND_2G;
++					else
++						channel |= WL_CHANSPEC_BAND_5G;
++					channel |= WL_CHANSPEC_BW_20;
++					channel = wl_chspec_host_to_driver(channel);
++					err = wldev_iovar_getint(dev, "per_chan_info", &channel);
++					if (!err) {
++						if (channel & WL_CHAN_RADAR) {
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
++							band_chan_arr[index].flags |=
++								(IEEE80211_CHAN_RADAR
++								| IEEE80211_CHAN_NO_IBSS);
++#else
++							band_chan_arr[index].flags |=
++								IEEE80211_CHAN_RADAR;
++#endif
++						}
++
++						if (channel & WL_CHAN_PASSIVE)
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
++							band_chan_arr[index].flags |=
++								IEEE80211_CHAN_PASSIVE_SCAN;
++#else
++							band_chan_arr[index].flags |=
++								IEEE80211_CHAN_NO_IR;
++#endif
++					} else if (err == BCME_UNSUPPORTED) {
++						dfs_radar_disabled = TRUE;
++						WL_ERR(("does not support per_chan_info\n"));
++					}
++				}
++			}
++			if (!update)
++				(*n_cnt)++;
++		}
++
++	}
++	__wl_band_2ghz.n_channels = n_2g;
++	__wl_band_5ghz_a.n_channels = n_5g;
++	kfree(pbuf);
++	return err;
++}
++
++s32 wl_update_wiphybands(struct bcm_cfg80211 *cfg, bool notify)
++{
++	struct wiphy *wiphy;
++	struct net_device *dev;
++	u32 bandlist[3];
++	u32 nband = 0;
++	u32 i = 0;
++	s32 err = 0;
++	s32 index = 0;
++	s32 nmode = 0;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	u32 j = 0;
++	s32 vhtmode = 0;
++	s32 txstreams = 0;
++	s32 rxstreams = 0;
++	s32 ldpc_cap = 0;
++	s32 stbc_rx = 0;
++	s32 stbc_tx = 0;
++	s32 txbf_bfe_cap = 0;
++	s32 txbf_bfr_cap = 0;
++#endif 
++	bool rollback_lock = false;
++	s32 bw_cap = 0;
++	s32 cur_band = -1;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))
++	struct ieee80211_supported_band *bands[NUM_NL80211_BANDS] = {NULL, };
++#else
++	struct ieee80211_supported_band *bands[IEEE80211_NUM_BANDS] = {NULL, };
++#endif
++
++	if (cfg == NULL) {
++		cfg = g_bcm_cfg;
++		mutex_lock(&cfg->usr_sync);
++		rollback_lock = true;
++	}
++	dev = bcmcfg_to_prmry_ndev(cfg);
++
++	memset(bandlist, 0, sizeof(bandlist));
++	err = wldev_ioctl(dev, WLC_GET_BANDLIST, bandlist,
++		sizeof(bandlist), false);
++	if (unlikely(err)) {
++		WL_ERR(("error read bandlist (%d)\n", err));
++		goto end_bands;
++	}
++	err = wldev_ioctl(dev, WLC_GET_BAND, &cur_band,
++		sizeof(s32), false);
++	if (unlikely(err)) {
++		WL_ERR(("error (%d)\n", err));
++		goto end_bands;
++	}
++
++	err = wldev_iovar_getint(dev, "nmode", &nmode);
++	if (unlikely(err)) {
++		WL_ERR(("error reading nmode (%d)\n", err));
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	err = wldev_iovar_getint(dev, "vhtmode", &vhtmode);
++	if (unlikely(err)) {
++		WL_ERR(("error reading vhtmode (%d)\n", err));
++	}
++
++	if (vhtmode) {
++		err = wldev_iovar_getint(dev, "txstreams", &txstreams);
++		if (unlikely(err)) {
++			WL_ERR(("error reading txstreams (%d)\n", err));
++		}
++
++		err = wldev_iovar_getint(dev, "rxstreams", &rxstreams);
++		if (unlikely(err)) {
++			WL_ERR(("error reading rxstreams (%d)\n", err));
++		}
++
++		err = wldev_iovar_getint(dev, "ldpc_cap", &ldpc_cap);
++		if (unlikely(err)) {
++			WL_ERR(("error reading ldpc_cap (%d)\n", err));
++		}
++
++		err = wldev_iovar_getint(dev, "stbc_rx", &stbc_rx);
++		if (unlikely(err)) {
++			WL_ERR(("error reading stbc_rx (%d)\n", err));
++		}
++
++		err = wldev_iovar_getint(dev, "stbc_tx", &stbc_tx);
++		if (unlikely(err)) {
++			WL_ERR(("error reading stbc_tx (%d)\n", err));
++		}
++
++		err = wldev_iovar_getint(dev, "txbf_bfe_cap", &txbf_bfe_cap);
++		if (unlikely(err)) {
++			WL_ERR(("error reading txbf_bfe_cap (%d)\n", err));
++		}
++
++		err = wldev_iovar_getint(dev, "txbf_bfr_cap", &txbf_bfr_cap);
++		if (unlikely(err)) {
++			WL_ERR(("error reading txbf_bfr_cap (%d)\n", err));
++		}
++	}
++#endif 
++
++	/* For nmode and vhtmode   check bw cap */
++	if (nmode ||
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++		vhtmode ||
++#endif 
++		0) {
++		err = wldev_iovar_getint(dev, "mimo_bw_cap", &bw_cap);
++		if (unlikely(err)) {
++			WL_ERR(("error get mimo_bw_cap (%d)\n", err));
++		}
++	}
++
++	err = wl_construct_reginfo(cfg, bw_cap);
++	if (err) {
++		WL_ERR(("wl_construct_reginfo() fails err=%d\n", err));
++		if (err != BCME_UNSUPPORTED)
++			goto end_bands;
++		err = 0;
++	}
++	wiphy = bcmcfg_to_wiphy(cfg);
++	nband = bandlist[0];
++
++	for (i = 1; i <= nband && i < ARRAYSIZE(bandlist); i++) {
++		index = -1;
++		if (bandlist[i] == WLC_BAND_5G && __wl_band_5ghz_a.n_channels > 0) {
++			bands[IEEE80211_BAND_5GHZ] =
++				&__wl_band_5ghz_a;
++			index = IEEE80211_BAND_5GHZ;
++			if (nmode && (bw_cap == WLC_N_BW_40ALL || bw_cap == WLC_N_BW_20IN2G_40IN5G))
++				bands[index]->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++			/* VHT capabilities. */
++			if (vhtmode) {
++				/* Supported */
++				bands[index]->vht_cap.vht_supported = TRUE;
++
++				for (j = 1; j <= VHT_CAP_MCS_MAP_NSS_MAX; j++) {
++					/* TX stream rates. */
++					if (j <= txstreams) {
++						VHT_MCS_MAP_SET_MCS_PER_SS(j, VHT_CAP_MCS_MAP_0_9,
++							bands[index]->vht_cap.vht_mcs.tx_mcs_map);
++					} else {
++						VHT_MCS_MAP_SET_MCS_PER_SS(j, VHT_CAP_MCS_MAP_NONE,
++							bands[index]->vht_cap.vht_mcs.tx_mcs_map);
++					}
++
++					/* RX stream rates. */
++					if (j <= rxstreams) {
++						VHT_MCS_MAP_SET_MCS_PER_SS(j, VHT_CAP_MCS_MAP_0_9,
++							bands[index]->vht_cap.vht_mcs.rx_mcs_map);
++					} else {
++						VHT_MCS_MAP_SET_MCS_PER_SS(j, VHT_CAP_MCS_MAP_NONE,
++							bands[index]->vht_cap.vht_mcs.rx_mcs_map);
++					}
++				}
++
++
++				/* Capabilities */
++				/* 80 MHz is mandatory */
++				bands[index]->vht_cap.cap |=
++					IEEE80211_VHT_CAP_SHORT_GI_80;
++
++				if (WL_BW_CAP_160MHZ(bw_cap)) {
++					bands[index]->vht_cap.cap |=
++						IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ;
++					bands[index]->vht_cap.cap |=
++						IEEE80211_VHT_CAP_SHORT_GI_160;
++				}
++
++				bands[index]->vht_cap.cap |=
++					IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
++
++				if (ldpc_cap)
++					bands[index]->vht_cap.cap |=
++						IEEE80211_VHT_CAP_RXLDPC;
++
++				if (stbc_tx)
++					bands[index]->vht_cap.cap |=
++						IEEE80211_VHT_CAP_TXSTBC;
++
++				if (stbc_rx)
++					bands[index]->vht_cap.cap |=
++						(stbc_rx << VHT_CAP_INFO_RX_STBC_SHIFT);
++
++				if (txbf_bfe_cap)
++					bands[index]->vht_cap.cap |=
++						IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
++
++				if (txbf_bfr_cap) {
++					bands[index]->vht_cap.cap |=
++						IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE;
++				}
++
++				if (txbf_bfe_cap || txbf_bfr_cap) {
++					bands[index]->vht_cap.cap |=
++						(2 << VHT_CAP_INFO_NUM_BMFMR_ANT_SHIFT);
++					bands[index]->vht_cap.cap |=
++						((txstreams - 1) <<
++							VHT_CAP_INFO_NUM_SOUNDING_DIM_SHIFT);
++					bands[index]->vht_cap.cap |=
++						IEEE80211_VHT_CAP_VHT_LINK_ADAPTATION_VHT_MRQ_MFB;
++				}
++
++				/* AMPDU length limit, support max 1MB (2 ^ (13 + 7)) */
++				bands[index]->vht_cap.cap |=
++					(7 << VHT_CAP_INFO_AMPDU_MAXLEN_EXP_SHIFT);
++				WL_INFORM(("%s band[%d] vht_enab=%d vht_cap=%08x "
++					"vht_rx_mcs_map=%04x vht_tx_mcs_map=%04x\n",
++					__FUNCTION__, index,
++					bands[index]->vht_cap.vht_supported,
++					bands[index]->vht_cap.cap,
++					bands[index]->vht_cap.vht_mcs.rx_mcs_map,
++					bands[index]->vht_cap.vht_mcs.tx_mcs_map));
++			}
++#endif 
++		}
++		else if (bandlist[i] == WLC_BAND_2G && __wl_band_2ghz.n_channels > 0) {
++			bands[IEEE80211_BAND_2GHZ] =
++				&__wl_band_2ghz;
++			index = IEEE80211_BAND_2GHZ;
++			if (bw_cap == WLC_N_BW_40ALL)
++				bands[index]->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
++		}
++
++		if ((index >= 0) && nmode) {
++			bands[index]->ht_cap.cap |=
++				(IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_DSSSCCK40);
++			bands[index]->ht_cap.ht_supported = TRUE;
++			bands[index]->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
++			bands[index]->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
++			/* An HT shall support all EQM rates for one spatial stream */
++			bands[index]->ht_cap.mcs.rx_mask[0] = 0xff;
++		}
++
++	}
++
++	wiphy->bands[IEEE80211_BAND_2GHZ] = bands[IEEE80211_BAND_2GHZ];
++	wiphy->bands[IEEE80211_BAND_5GHZ] = bands[IEEE80211_BAND_5GHZ];
++
++	/* check if any bands populated otherwise makes 2Ghz as default */
++	if (wiphy->bands[IEEE80211_BAND_2GHZ] == NULL &&
++		wiphy->bands[IEEE80211_BAND_5GHZ] == NULL) {
++		/* Setup 2Ghz band as default */
++		wiphy->bands[IEEE80211_BAND_2GHZ] = &__wl_band_2ghz;
++	}
++
++	if (notify)
++		wiphy_apply_custom_regulatory(wiphy, &brcm_regdom);
++
++	end_bands:
++		if (rollback_lock)
++			mutex_unlock(&cfg->usr_sync);
++	return err;
++}
++
++static s32 __wl_cfg80211_up(struct bcm_cfg80211 *cfg)
++{
++	s32 err = 0;
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	struct wireless_dev *wdev = ndev->ieee80211_ptr;
++
++	WL_DBG(("In\n"));
++
++	err = dhd_config_dongle(cfg);
++	if (unlikely(err))
++		return err;
++
++	err = wl_config_ifmode(cfg, ndev, wdev->iftype);
++	if (unlikely(err && err != -EINPROGRESS)) {
++		WL_ERR(("wl_config_ifmode failed\n"));
++		if (err == -1) {
++			WL_ERR(("return error %d\n", err));
++			return err;
++		}
++	}
++	err = wl_update_wiphybands(cfg, true);
++	if (unlikely(err)) {
++		WL_ERR(("wl_update_wiphybands failed\n"));
++		if (err == -1) {
++			WL_ERR(("return error %d\n", err));
++			return err;
++		}
++	}
++
++	err = wl_create_event_handler(cfg);
++	if (err) {
++		WL_ERR(("wl_create_event_handler failed\n"));
++		return err;
++	}
++	wl_init_event_handler(cfg);
++
++	err = wl_init_scan(cfg);
++	if (err) {
++		WL_ERR(("wl_init_scan failed\n"));
++		return err;
++	}
++#ifdef DHD_LOSSLESS_ROAMING
++	if (timer_pending(&cfg->roam_timeout)) {
++		del_timer_sync(&cfg->roam_timeout);
++	}
++#endif /* DHD_LOSSLESS_ROAMING */
++
++	err = dhd_monitor_init(cfg->pub);
++
++	INIT_DELAYED_WORK(&cfg->pm_enable_work, wl_cfg80211_work_handler);
++	wl_set_drv_status(cfg, READY, ndev);
++	return err;
++}
++
++static s32 __wl_cfg80211_down(struct bcm_cfg80211 *cfg)
++{
++	s32 err = 0;
++	unsigned long flags;
++	struct net_info *iter, *next;
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++#if defined(WL_CFG80211) && defined(WL_ENABLE_P2P_IF)
++	struct net_device *p2p_net = cfg->p2p_net;
++#endif 
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO) || defined(BCMDBUS)
++	dhd_pub_t *dhd =  (dhd_pub_t *)(cfg->pub);
++#endif /* defined(BCMSDIO) || defined(BCMDBUS) */
++#endif /* PROP_TXSTATUS_VSDB */
++	WL_DBG(("In\n"));
++	/* Delete pm_enable_work */
++	wl_add_remove_pm_enable_work(cfg, FALSE, WL_HANDLER_DEL);
++
++#ifdef WL_NAN
++	wl_cfgnan_stop_handler(ndev, g_bcm_cfg, NULL, 0, NULL);
++#endif /* WL_NAN */
++
++	if (cfg->p2p_supported) {
++		wl_clr_p2p_status(cfg, GO_NEG_PHASE);
++#ifdef PROP_TXSTATUS_VSDB
++#if defined(BCMSDIO) || defined(BCMDBUS)
++		if (wl_cfgp2p_vif_created(cfg)) {
++			bool enabled = false;
++			dhd_wlfc_get_enable(dhd, &enabled);
++			if (enabled && cfg->wlfc_on && dhd->op_mode != DHD_FLAG_HOSTAP_MODE &&
++				dhd->op_mode != DHD_FLAG_IBSS_MODE) {
++				dhd_wlfc_deinit(dhd);
++				cfg->wlfc_on = false;
++			}
++		}
++#endif /* defined(BCMSDIO) || defined(BCMDBUS) */
++#endif /* PROP_TXSTATUS_VSDB */
++	}
++
++	/* Check if cfg80211 interface is already down */
++	if (!wl_get_drv_status(cfg, READY, ndev)) {
++		WL_DBG(("cfg80211 interface is already down"));
++		return err;     /* it is even not ready */
++	}
++
++
++	/* If primary BSS is operational (for e.g SoftAP), bring it down */
++	if (wl_cfgp2p_bss_isup(ndev, 0)) {
++		if (wl_cfgp2p_bss(cfg, ndev, 0, 0) < 0)
++			WL_ERR(("BSS down failed \n"));
++	}
++
++	/* clear all the security setting on primary Interface */
++	wl_cfg80211_clear_security(cfg);
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++	for_each_ndev(cfg, iter, next) {
++		if (iter->ndev) /* p2p discovery iface is null */
++			wl_set_drv_status(cfg, SCAN_ABORTING, iter->ndev);
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++	if (cfg->scan_request) {
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(4, 8, 0))
++		struct cfg80211_scan_info info = { .aborted = true };
++		cfg80211_scan_done(cfg->scan_request, &info);
++#else
++		cfg80211_scan_done(cfg->scan_request, true);
++#endif
++		cfg->scan_request = NULL;
++	}
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++	for_each_ndev(cfg, iter, next) {
++		/* p2p discovery iface ndev ptr could be null */
++		if (iter->ndev == NULL)
++			continue;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
++		if (wl_get_drv_status(cfg, CONNECTED, iter->ndev)) {
++			CFG80211_DISCONNECTED(iter->ndev, 0, NULL, 0, false, GFP_KERNEL);
++		}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) */
++		wl_clr_drv_status(cfg, READY, iter->ndev);
++		wl_clr_drv_status(cfg, SCANNING, iter->ndev);
++		wl_clr_drv_status(cfg, SCAN_ABORTING, iter->ndev);
++		wl_clr_drv_status(cfg, CONNECTING, iter->ndev);
++		wl_clr_drv_status(cfg, CONNECTED, iter->ndev);
++		wl_clr_drv_status(cfg, DISCONNECTING, iter->ndev);
++		wl_clr_drv_status(cfg, AP_CREATED, iter->ndev);
++		wl_clr_drv_status(cfg, AP_CREATING, iter->ndev);
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	bcmcfg_to_prmry_ndev(cfg)->ieee80211_ptr->iftype =
++		NL80211_IFTYPE_STATION;
++#if defined(WL_CFG80211) && defined(WL_ENABLE_P2P_IF)
++		if (p2p_net)
++			dev_close(p2p_net);
++#endif 
++
++	/* Avoid deadlock from wl_cfg80211_down */
++	mutex_unlock(&cfg->usr_sync);
++	wl_destroy_event_handler(cfg);
++	mutex_lock(&cfg->usr_sync);
++	wl_flush_eq(cfg);
++	wl_link_down(cfg);
++	if (cfg->p2p_supported) {
++		if (timer_pending(&cfg->p2p->listen_timer))
++			del_timer_sync(&cfg->p2p->listen_timer);
++		wl_cfgp2p_down(cfg);
++	}
++
++	if (timer_pending(&cfg->scan_timeout)) {
++		del_timer_sync(&cfg->scan_timeout);
++	}
++
++	DHD_OS_SCAN_WAKE_UNLOCK((dhd_pub_t *)(cfg->pub));
++
++	dhd_monitor_uninit();
++#ifdef WLAIBSS_MCHAN
++	bcm_cfg80211_del_ibss_if(cfg->wdev->wiphy, cfg->ibss_cfgdev);
++#endif /* WLAIBSS_MCHAN */
++
++#if defined(WL_VIRTUAL_APSTA) || defined(DUAL_STA_STATIC_IF)
++	/* Clean up if not removed already */
++	if (cfg->bss_cfgdev)
++		wl_cfg80211_del_iface(cfg->wdev->wiphy, cfg->bss_cfgdev);
++#endif /* defined (WL_VIRTUAL_APSTA) || defined (DUAL_STA_STATIC_IF) */
++
++#ifdef WL11U
++	/* Clear interworking element. */
++	if (cfg->wl11u) {
++		cfg->wl11u = FALSE;
++		cfg->iw_ie_len = 0;
++		memset(cfg->iw_ie, 0, IW_IES_MAX_BUF_LEN);
++	}
++#endif /* WL11U */
++
++
++	DNGL_FUNC(dhd_cfg80211_down, (cfg));
++
++#ifdef DHD_IFDEBUG
++	/* Printout all netinfo entries */
++	wl_probe_wdev_all(cfg);
++#endif /* DHD_IFDEBUG */
++
++	return err;
++}
++
++s32 wl_cfg80211_up(void *para)
++{
++	struct bcm_cfg80211 *cfg;
++	s32 err = 0;
++	int val = 1;
++	dhd_pub_t *dhd;
++#ifdef DISABLE_PM_BCNRX
++	s32 interr = 0;
++	uint param = 0;
++	s8 iovbuf[WLC_IOCTL_SMLEN];
++#endif /* DISABLE_PM_BCNRX */
++
++	(void)para;
++	WL_DBG(("In\n"));
++	cfg = g_bcm_cfg;
++
++	if ((err = wldev_ioctl(bcmcfg_to_prmry_ndev(cfg), WLC_GET_VERSION, &val,
++		sizeof(int), false) < 0)) {
++		WL_ERR(("WLC_GET_VERSION failed, err=%d\n", err));
++		return err;
++	}
++	val = dtoh32(val);
++	if (val != WLC_IOCTL_VERSION && val != 1) {
++		WL_ERR(("Version mismatch, please upgrade. Got %d, expected %d or 1\n",
++			val, WLC_IOCTL_VERSION));
++		return BCME_VERSION;
++	}
++	ioctl_version = val;
++	WL_TRACE(("WLC_GET_VERSION=%d\n", ioctl_version));
++
++	mutex_lock(&cfg->usr_sync);
++	dhd = (dhd_pub_t *)(cfg->pub);
++	if (!(dhd->op_mode & DHD_FLAG_HOSTAP_MODE)) {
++		err = wl_cfg80211_attach_post(bcmcfg_to_prmry_ndev(cfg));
++		if (unlikely(err)) {
++			mutex_unlock(&cfg->usr_sync);
++			return err;
++		}
++	}
++	err = __wl_cfg80211_up(cfg);
++	if (unlikely(err))
++		WL_ERR(("__wl_cfg80211_up failed\n"));
++
++
++
++	/* IOVAR configurations with 'up' condition */
++#ifdef DISABLE_PM_BCNRX
++	interr = wldev_iovar_setbuf(bcmcfg_to_prmry_ndev(cfg), "pm_bcnrx",
++		(char *)&param, sizeof(param), iovbuf, sizeof(iovbuf), &cfg->ioctl_buf_sync);
++
++	if (unlikely(interr))
++		WL_ERR(("Set pm_bcnrx error (%d)\n", interr));
++#endif /* DISABLE_PM_BCNRX */
++
++	mutex_unlock(&cfg->usr_sync);
++
++#ifdef WLAIBSS_MCHAN
++	bcm_cfg80211_add_ibss_if(cfg->wdev->wiphy, IBSS_IF_NAME);
++#endif /* WLAIBSS_MCHAN */
++
++#ifdef DUAL_STA_STATIC_IF
++#ifdef WL_VIRTUAL_APSTA
++#error "Both DUAL STA and DUAL_STA_STATIC_IF can't be enabled together"
++#endif
++	/* Static Interface support is currently supported only for STA only builds (without P2P) */
++	wl_cfg80211_create_iface(cfg->wdev->wiphy, NL80211_IFTYPE_STATION, NULL, "wlan%d");
++#endif /* DUAL_STA_STATIC_IF */
++
++	return err;
++}
++
++/* Private Event to Supplicant with indication that chip hangs */
++int wl_cfg80211_hang(struct net_device *dev, u16 reason)
++{
++	struct bcm_cfg80211 *cfg;
++#if defined(SOFTAP_SEND_HANGEVT)
++	/* specifc mac address used for hang event */
++	uint8 hang_mac[ETHER_ADDR_LEN] = {0x11, 0x11, 0x11, 0x11, 0x11, 0x11};
++	dhd_pub_t *dhd;
++#endif /* SOFTAP_SEND_HANGEVT */
++	if (!g_bcm_cfg) {
++		return BCME_ERROR;
++	}
++
++	cfg = g_bcm_cfg;
++
++	WL_ERR(("In : chip crash eventing\n"));
++	wl_add_remove_pm_enable_work(cfg, FALSE, WL_HANDLER_DEL);
++#if defined(SOFTAP_SEND_HANGEVT)
++	dhd = (dhd_pub_t *)(cfg->pub);
++	if (dhd->op_mode & DHD_FLAG_HOSTAP_MODE) {
++		cfg80211_del_sta(dev, hang_mac, GFP_ATOMIC);
++	} else
++#endif /* SOFTAP_SEND_HANGEVT */
++	{
++		CFG80211_DISCONNECTED(dev, reason, NULL, 0, false, GFP_KERNEL);
++	}
++	if (cfg != NULL) {
++		wl_link_down(cfg);
++	}
++	return 0;
++}
++
++s32 wl_cfg80211_down(void *para)
++{
++	struct bcm_cfg80211 *cfg;
++	s32 err = 0;
++
++	(void)para;
++	WL_DBG(("In\n"));
++	cfg = g_bcm_cfg;
++	mutex_lock(&cfg->usr_sync);
++	err = __wl_cfg80211_down(cfg);
++	mutex_unlock(&cfg->usr_sync);
++
++	return err;
++}
++
++#if (defined(STBLINUX) && defined(WL_CFG80211))
++int wl_cfg80211_cleanup(void)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	struct net_device *ndev;
++	unsigned long flags;
++
++	if (!cfg)
++		return -EINVAL;
++
++	ndev = bcmcfg_to_prmry_ndev(cfg);
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++	if (cfg->scan_request) {
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(4, 8, 0))
++		struct cfg80211_scan_info info = { .aborted = true };
++		cfg80211_scan_done(cfg->scan_request, &info);
++#else
++		cfg80211_scan_done(cfg->scan_request, true);
++#endif
++		cfg->scan_request = NULL;
++	}
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++
++	if (wl_get_drv_status(cfg, CONNECTED, ndev) ||
++		wl_get_drv_status(cfg, CONNECTING, ndev)) {
++		CFG80211_DISCONNECTED(ndev, 0, NULL, 0, false, GFP_KERNEL);
++	}
++
++	/* clear all flags */
++	wl_clr_drv_status(cfg, SCANNING, ndev);
++	wl_clr_drv_status(cfg, CONNECTING, ndev);
++	wl_clr_drv_status(cfg, CONNECTED, ndev);
++
++	/* Let kernel thread to handle the event */
++	cond_resched();
++	mdelay(500);
++
++	return 0;
++}
++#endif /* STBLINUX && WL_CFG80211 */
++
++static void *wl_read_prof(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 item)
++{
++	unsigned long flags;
++	void *rptr = NULL;
++	struct wl_profile *profile = wl_get_profile_by_netdev(cfg, ndev);
++
++	if (!profile)
++		return NULL;
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++	switch (item) {
++	case WL_PROF_SEC:
++		rptr = &profile->sec;
++		break;
++	case WL_PROF_ACT:
++		rptr = &profile->active;
++		break;
++	case WL_PROF_BSSID:
++		rptr = profile->bssid;
++		break;
++	case WL_PROF_SSID:
++		rptr = &profile->ssid;
++		break;
++	case WL_PROF_CHAN:
++		rptr = &profile->channel;
++		break;
++	}
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++	if (!rptr)
++		WL_ERR(("invalid item (%d)\n", item));
++	return rptr;
++}
++
++static s32
++wl_update_prof(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const wl_event_msg_t *e, const void *data, s32 item)
++{
++	s32 err = 0;
++	const struct wlc_ssid *ssid;
++	unsigned long flags;
++	struct wl_profile *profile = wl_get_profile_by_netdev(cfg, ndev);
++
++	if (!profile)
++		return WL_INVALID;
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++	switch (item) {
++	case WL_PROF_SSID:
++		ssid = (const wlc_ssid_t *) data;
++		memset(profile->ssid.SSID, 0,
++			sizeof(profile->ssid.SSID));
++		memcpy(profile->ssid.SSID, ssid->SSID, ssid->SSID_len);
++		profile->ssid.SSID_len = ssid->SSID_len;
++		break;
++	case WL_PROF_BSSID:
++		if (data)
++			memcpy(profile->bssid, data, ETHER_ADDR_LEN);
++		else
++			memset(profile->bssid, 0, ETHER_ADDR_LEN);
++		break;
++	case WL_PROF_SEC:
++		memcpy(&profile->sec, data, sizeof(profile->sec));
++		break;
++	case WL_PROF_ACT:
++		profile->active = *(const bool *)data;
++		break;
++	case WL_PROF_BEACONINT:
++		profile->beacon_interval = *(const u16 *)data;
++		break;
++	case WL_PROF_DTIMPERIOD:
++		profile->dtim_period = *(const u8 *)data;
++		break;
++	case WL_PROF_CHAN:
++		profile->channel = *(const u32*)data;
++		break;
++	default:
++		err = -EOPNOTSUPP;
++		break;
++	}
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++
++	if (err == -EOPNOTSUPP)
++		WL_ERR(("unsupported item (%d)\n", item));
++
++	return err;
++}
++
++void wl_cfg80211_dbg_level(u32 level)
++{
++	/*
++	* prohibit to change debug level
++	* by insmod parameter.
++	* eventually debug level will be configured
++	* in compile time by using CONFIG_XXX
++	*/
++	/* wl_dbg_level = level; */
++}
++
++static bool wl_is_ibssmode(struct bcm_cfg80211 *cfg, struct net_device *ndev)
++{
++	return wl_get_mode_by_netdev(cfg, ndev) == WL_MODE_IBSS;
++}
++
++static __used bool wl_is_ibssstarter(struct bcm_cfg80211 *cfg)
++{
++	return cfg->ibss_starter;
++}
++
++static void wl_rst_ie(struct bcm_cfg80211 *cfg)
++{
++	struct wl_ie *ie = wl_to_ie(cfg);
++
++	ie->offset = 0;
++}
++
++static __used s32 wl_add_ie(struct bcm_cfg80211 *cfg, u8 t, u8 l, u8 *v)
++{
++	struct wl_ie *ie = wl_to_ie(cfg);
++	s32 err = 0;
++
++	if (unlikely(ie->offset + l + 2 > WL_TLV_INFO_MAX)) {
++		WL_ERR(("ei crosses buffer boundary\n"));
++		return -ENOSPC;
++	}
++	ie->buf[ie->offset] = t;
++	ie->buf[ie->offset + 1] = l;
++	memcpy(&ie->buf[ie->offset + 2], v, l);
++	ie->offset += l + 2;
++
++	return err;
++}
++
++static void wl_update_hidden_ap_ie(struct wl_bss_info *bi, const u8 *ie_stream, u32 *ie_size,
++	bool roam)
++{
++	u8 *ssidie;
++	/* cfg80211_find_ie defined in kernel returning const u8 */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++	ssidie = (u8 *)cfg80211_find_ie(WLAN_EID_SSID, ie_stream, *ie_size);
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	if (!ssidie)
++		return;
++	if (ssidie[1] != bi->SSID_len) {
++		if (ssidie[1]) {
++			WL_ERR(("%s: Wrong SSID len: %d != %d\n",
++				__FUNCTION__, ssidie[1], bi->SSID_len));
++		}
++		if (roam) {
++			WL_ERR(("Changing the SSID Info.\n"));
++			memmove(ssidie + bi->SSID_len + 2,
++				(ssidie + 2) + ssidie[1],
++				*ie_size - (ssidie + 2 + ssidie[1] - ie_stream));
++			memcpy(ssidie + 2, bi->SSID, bi->SSID_len);
++			*ie_size = *ie_size + bi->SSID_len - ssidie[1];
++			ssidie[1] = bi->SSID_len;
++		}
++		return;
++	}
++	if (*(ssidie + 2) == '\0')
++		 memcpy(ssidie + 2, bi->SSID, bi->SSID_len);
++	return;
++}
++
++static s32 wl_mrg_ie(struct bcm_cfg80211 *cfg, u8 *ie_stream, u16 ie_size)
++{
++	struct wl_ie *ie = wl_to_ie(cfg);
++	s32 err = 0;
++
++	if (unlikely(ie->offset + ie_size > WL_TLV_INFO_MAX)) {
++		WL_ERR(("ei_stream crosses buffer boundary\n"));
++		return -ENOSPC;
++	}
++	memcpy(&ie->buf[ie->offset], ie_stream, ie_size);
++	ie->offset += ie_size;
++
++	return err;
++}
++
++static s32 wl_cp_ie(struct bcm_cfg80211 *cfg, u8 *dst, u16 dst_size)
++{
++	struct wl_ie *ie = wl_to_ie(cfg);
++	s32 err = 0;
++
++	if (unlikely(ie->offset > dst_size)) {
++		WL_ERR(("dst_size is not enough\n"));
++		return -ENOSPC;
++	}
++	memcpy(dst, &ie->buf[0], ie->offset);
++
++	return err;
++}
++
++static u32 wl_get_ielen(struct bcm_cfg80211 *cfg)
++{
++	struct wl_ie *ie = wl_to_ie(cfg);
++
++	return ie->offset;
++}
++
++static void wl_link_up(struct bcm_cfg80211 *cfg)
++{
++	cfg->link_up = true;
++}
++
++static void wl_link_down(struct bcm_cfg80211 *cfg)
++{
++	struct wl_connect_info *conn_info = wl_to_conn(cfg);
++
++	WL_DBG(("In\n"));
++	cfg->link_up = false;
++	conn_info->req_ie_len = 0;
++	conn_info->resp_ie_len = 0;
++}
++
++static unsigned long wl_lock_eq(struct bcm_cfg80211 *cfg)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&cfg->eq_lock, flags);
++	return flags;
++}
++
++static void wl_unlock_eq(struct bcm_cfg80211 *cfg, unsigned long flags)
++{
++	spin_unlock_irqrestore(&cfg->eq_lock, flags);
++}
++
++static void wl_init_eq_lock(struct bcm_cfg80211 *cfg)
++{
++	spin_lock_init(&cfg->eq_lock);
++}
++
++static void wl_delay(u32 ms)
++{
++	if (in_atomic() || (ms < jiffies_to_msecs(1))) {
++		OSL_DELAY(ms*1000);
++	} else {
++		OSL_SLEEP(ms);
++	}
++}
++
++s32 wl_cfg80211_get_p2p_dev_addr(struct net_device *net, struct ether_addr *p2pdev_addr)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	struct ether_addr primary_mac;
++	if (!cfg->p2p)
++		return -1;
++	if (!p2p_is_on(cfg)) {
++		get_primary_mac(cfg, &primary_mac);
++		wl_cfgp2p_generate_bss_mac(cfg, &primary_mac);
++	} else {
++		memcpy(p2pdev_addr->octet, wl_to_p2p_bss_macaddr(cfg, P2PAPI_BSSCFG_DEVICE).octet,
++			ETHER_ADDR_LEN);
++	}
++
++	return 0;
++}
++s32 wl_cfg80211_set_p2p_noa(struct net_device *net, char* buf, int len)
++{
++	struct bcm_cfg80211 *cfg;
++
++	cfg = g_bcm_cfg;
++
++	return wl_cfgp2p_set_p2p_noa(cfg, net, buf, len);
++}
++
++s32 wl_cfg80211_get_p2p_noa(struct net_device *net, char* buf, int len)
++{
++	struct bcm_cfg80211 *cfg;
++	cfg = g_bcm_cfg;
++
++	return wl_cfgp2p_get_p2p_noa(cfg, net, buf, len);
++}
++
++s32 wl_cfg80211_set_p2p_ps(struct net_device *net, char* buf, int len)
++{
++	struct bcm_cfg80211 *cfg;
++	cfg = g_bcm_cfg;
++
++	return wl_cfgp2p_set_p2p_ps(cfg, net, buf, len);
++}
++
++s32 wl_cfg80211_set_p2p_ecsa(struct net_device *net, char* buf, int len)
++{
++	struct bcm_cfg80211 *cfg;
++	cfg = g_bcm_cfg;
++
++	return wl_cfgp2p_set_p2p_ecsa(cfg, net, buf, len);
++}
++
++#ifdef P2PLISTEN_AP_SAMECHN
++s32 wl_cfg80211_set_p2p_resp_ap_chn(struct net_device *net, s32 enable)
++{
++	s32 ret = wldev_iovar_setint(net, "p2p_resp_ap_chn", enable);
++
++	if ((ret == 0) && enable) {
++		/* disable PM for p2p responding on infra AP channel */
++		s32 pm = PM_OFF;
++
++		ret = wldev_ioctl(net, WLC_SET_PM, &pm, sizeof(pm), true);
++	}
++
++	return ret;
++}
++#endif /* P2PLISTEN_AP_SAMECHN */
++
++s32 wl_cfg80211_channel_to_freq(u32 channel)
++{
++	int freq = 0;
++
++#if LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 38)
++	freq = ieee80211_channel_to_frequency(channel);
++#else
++	{
++		u16 band = 0;
++		if (channel <= CH_MAX_2G_CHANNEL)
++			band = IEEE80211_BAND_2GHZ;
++		else
++			band = IEEE80211_BAND_5GHZ;
++		freq = ieee80211_channel_to_frequency(channel, band);
++	}
++#endif
++	return freq;
++}
++
++
++#ifdef WLTDLS
++static s32
++wl_tdls_event_handler(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data) {
++
++	struct net_device *ndev = NULL;
++	u32 reason = ntoh32(e->reason);
++	s8 *msg = NULL;
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	switch (reason) {
++	case WLC_E_TDLS_PEER_DISCOVERED :
++		msg = " TDLS PEER DISCOVERD ";
++		break;
++	case WLC_E_TDLS_PEER_CONNECTED :
++#ifdef PCIE_FULL_DONGLE
++		dhd_tdls_update_peer_info(ndev, TRUE, (uint8 *)&e->addr.octet[0]);
++#endif /* PCIE_FULL_DONGLE */
++		if (cfg->tdls_mgmt_frame) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
++			cfg80211_rx_mgmt(cfgdev, cfg->tdls_mgmt_freq, 0,
++				cfg->tdls_mgmt_frame, cfg->tdls_mgmt_frame_len,
++				0);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 12, 0))
++			cfg80211_rx_mgmt(cfgdev, cfg->tdls_mgmt_freq, 0,
++				cfg->tdls_mgmt_frame, cfg->tdls_mgmt_frame_len,
++				0, GFP_ATOMIC);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) || \
++	defined(WL_COMPAT_WIRELESS)
++			cfg80211_rx_mgmt(cfgdev, cfg->tdls_mgmt_freq, 0,
++				cfg->tdls_mgmt_frame, cfg->tdls_mgmt_frame_len,
++				GFP_ATOMIC);
++#else
++			cfg80211_rx_mgmt(cfgdev, cfg->tdls_mgmt_freq,
++				cfg->tdls_mgmt_frame, cfg->tdls_mgmt_frame_len,
++				GFP_ATOMIC);
++#endif /* LINUX_VERSION >= VERSION(3, 12, 0) */
++		}
++		msg = " TDLS PEER CONNECTED ";
++		break;
++	case WLC_E_TDLS_PEER_DISCONNECTED :
++#ifdef PCIE_FULL_DONGLE
++		dhd_tdls_update_peer_info(ndev, FALSE, (uint8 *)&e->addr.octet[0]);
++#endif /* PCIE_FULL_DONGLE */
++		if (cfg->tdls_mgmt_frame) {
++			kfree(cfg->tdls_mgmt_frame);
++			cfg->tdls_mgmt_frame = NULL;
++			cfg->tdls_mgmt_freq = 0;
++		}
++		msg = "TDLS PEER DISCONNECTED ";
++		break;
++	}
++	if (msg) {
++		WL_ERR(("%s: " MACDBG " on %s ndev\n", msg, MAC2STRDBG((u8*)(&e->addr)),
++			(bcmcfg_to_prmry_ndev(cfg) == ndev) ? "primary" : "secondary"));
++	}
++	return 0;
++
++}
++#endif  /* WLTDLS */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++static s32
++#if (defined(CONFIG_ARCH_MSM) && defined(TDLS_MGMT_VERSION2)) || (LINUX_VERSION_CODE < \
++	KERNEL_VERSION(3, 16, 0) && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))
++wl_cfg80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev,
++        u8 *peer, u8 action_code, u8 dialog_token, u16 status_code,
++        u32 peer_capability, const u8 *data, size_t len)
++#elif ((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) && \
++		(LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0)))
++wl_cfg80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev,
++	const u8 *peer, u8 action_code, u8 dialog_token, u16 status_code,
++	u32 peer_capability, const u8 *data, size_t len)
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
++wl_cfg80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev,
++	const u8 *peer, u8 action_code, u8 dialog_token, u16 status_code,
++	u32 peer_capability, bool initiator, const u8 *data, size_t len)
++#else
++wl_cfg80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev,
++	u8 *peer, u8 action_code, u8 dialog_token, u16 status_code, const u8 *data,
++	size_t len)
++#endif  /* CONFIG_ARCH_MSM && TDLS_MGMT_VERSION2 */
++{
++	s32 ret = 0;
++#ifdef WLTDLS
++	struct bcm_cfg80211 *cfg;
++	tdls_wfd_ie_iovar_t info;
++	memset(&info, 0, sizeof(tdls_wfd_ie_iovar_t));
++	cfg = g_bcm_cfg;
++
++#if defined(CONFIG_ARCH_MSM) && defined(TDLS_MGMT_VERSION2)
++	/* Some customer platform back ported this feature from kernel 3.15 to kernel 3.10
++	* and that cuases build error
++	*/
++	BCM_REFERENCE(peer_capability);
++#endif  /* CONFIG_ARCH_MSM && TDLS_MGMT_VERSION2 */
++
++	switch (action_code) {
++	/* We need to set TDLS Wifi Display IE to firmware
++	 * using tdls_wfd_ie iovar
++	 */
++	case WLAN_TDLS_SET_PROBE_WFD_IE:
++		WL_ERR(("%s WLAN_TDLS_SET_PROBE_WFD_IE\n", __FUNCTION__));
++		info.mode = TDLS_WFD_PROBE_IE_TX;
++		memcpy(&info.data, data, len);
++		info.length = len;
++		break;
++	case WLAN_TDLS_SET_SETUP_WFD_IE:
++		WL_ERR(("%s WLAN_TDLS_SET_SETUP_WFD_IE\n", __FUNCTION__));
++		info.mode = TDLS_WFD_IE_TX;
++		memcpy(&info.data, data, len);
++		info.length = len;
++		break;
++	case WLAN_TDLS_SET_WFD_ENABLED:
++		WL_ERR(("%s WLAN_TDLS_SET_MODE_WFD_ENABLED\n", __FUNCTION__));
++		dhd_tdls_set_mode((dhd_pub_t *)(cfg->pub), true);
++		goto out;
++	case WLAN_TDLS_SET_WFD_DISABLED:
++		WL_ERR(("%s WLAN_TDLS_SET_MODE_WFD_DISABLED\n", __FUNCTION__));
++		dhd_tdls_set_mode((dhd_pub_t *)(cfg->pub), false);
++		goto out;
++	default:
++		WL_ERR(("Unsupported action code : %d\n", action_code));
++		goto out;
++	}
++
++	ret = wldev_iovar_setbuf(dev, "tdls_wfd_ie", &info, sizeof(info),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++
++	if (ret) {
++		WL_ERR(("tdls_wfd_ie error %d\n", ret));
++	}
++out:
++#endif /* WLTDLS */
++	return ret;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++static s32
++wl_cfg80211_tdls_oper(struct wiphy *wiphy, struct net_device *dev,
++	const u8 *peer, enum nl80211_tdls_operation oper)
++#else
++static s32
++wl_cfg80211_tdls_oper(struct wiphy *wiphy, struct net_device *dev,
++	u8 *peer, enum nl80211_tdls_operation oper)
++#endif
++{
++	s32 ret = 0;
++#ifdef WLTDLS
++	struct bcm_cfg80211 *cfg;
++	tdls_iovar_t info;
++	dhd_pub_t *dhdp;
++	bool tdls_auto_mode = false;
++	cfg = g_bcm_cfg;
++	dhdp = (dhd_pub_t *)(cfg->pub);
++	memset(&info, 0, sizeof(tdls_iovar_t));
++	if (peer) {
++		memcpy(&info.ea, peer, ETHER_ADDR_LEN);
++	} else {
++		return -1;
++	}
++	switch (oper) {
++	case NL80211_TDLS_DISCOVERY_REQ:
++		/* If the discovery request is broadcast then we need to set
++		 * info.mode to Tunneled Probe Request
++		 */
++		if (memcmp(peer, (const uint8 *)BSSID_BROADCAST, ETHER_ADDR_LEN) == 0) {
++			info.mode = TDLS_MANUAL_EP_WFD_TPQ;
++			WL_ERR(("%s TDLS TUNNELED PRBOBE REQUEST\n", __FUNCTION__));
++		} else {
++			info.mode = TDLS_MANUAL_EP_DISCOVERY;
++		}
++		break;
++	case NL80211_TDLS_SETUP:
++		if (dhdp->tdls_mode == true) {
++			info.mode = TDLS_MANUAL_EP_CREATE;
++			tdls_auto_mode = false;
++			ret = dhd_tdls_enable(dev, false, tdls_auto_mode, NULL);
++			if (ret < 0) {
++				return ret;
++			}
++		} else {
++			tdls_auto_mode = true;
++		}
++		break;
++	case NL80211_TDLS_TEARDOWN:
++		info.mode = TDLS_MANUAL_EP_DELETE;
++		break;
++	default:
++		WL_ERR(("Unsupported operation : %d\n", oper));
++		goto out;
++	}
++	/* turn on TDLS */
++	ret = dhd_tdls_enable(dev, true, tdls_auto_mode, NULL);
++	if (ret < 0) {
++		return ret;
++
++	}
++	if (info.mode) {
++		ret = wldev_iovar_setbuf(dev, "tdls_endpoint", &info, sizeof(info),
++			cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++		if (ret) {
++			WL_ERR(("tdls_endpoint error %d\n", ret));
++		}
++	}
++out:
++#endif /* WLTDLS */
++	return ret;
++}
++#endif 
++
++s32 wl_cfg80211_set_wps_p2p_ie(struct net_device *net, char *buf, int len,
++	enum wl_management_type type)
++{
++	struct bcm_cfg80211 *cfg;
++	struct net_device *ndev = NULL;
++	struct ether_addr primary_mac;
++	s32 ret = 0;
++	s32 bssidx = 0;
++	s32 pktflag = 0;
++	cfg = g_bcm_cfg;
++
++	if (wl_get_drv_status(cfg, AP_CREATING, net)) {
++		/* Vendor IEs should be set to FW
++		 * after SoftAP interface is brought up
++		 */
++		goto exit;
++	} else if (wl_get_drv_status(cfg, AP_CREATED, net)) {
++		ndev = net;
++		bssidx = 0;
++	} else if (cfg->p2p) {
++		net = ndev_to_wlc_ndev(net, cfg);
++		if (!cfg->p2p->on) {
++			get_primary_mac(cfg, &primary_mac);
++			wl_cfgp2p_generate_bss_mac(cfg, &primary_mac);
++			/* In case of p2p_listen command, supplicant send remain_on_channel
++			* without turning on P2P
++			*/
++
++			p2p_on(cfg) = true;
++			ret = wl_cfgp2p_enable_discovery(cfg, net, NULL, 0);
++
++			if (unlikely(ret)) {
++				goto exit;
++			}
++		}
++		if (net  == bcmcfg_to_prmry_ndev(cfg)) {
++			ndev = wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_PRIMARY);
++			bssidx = wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++		} else {
++			ndev = net;
++			bssidx = wl_get_bssidx_by_wdev(cfg, ndev->ieee80211_ptr);
++			}
++	}
++	if (ndev != NULL) {
++		switch (type) {
++			case WL_BEACON:
++				pktflag = VNDR_IE_BEACON_FLAG;
++				break;
++			case WL_PROBE_RESP:
++				pktflag = VNDR_IE_PRBRSP_FLAG;
++				break;
++			case WL_ASSOC_RESP:
++				pktflag = VNDR_IE_ASSOCRSP_FLAG;
++				break;
++		}
++		if (pktflag)
++			ret = wl_cfg80211_set_mgmt_vndr_ies(cfg,
++				ndev_to_cfgdev(ndev), bssidx, pktflag, buf, len);
++	}
++exit:
++	return ret;
++}
++
++#ifdef WL_SUPPORT_AUTO_CHANNEL
++static s32
++wl_cfg80211_set_auto_channel_scan_state(struct net_device *ndev)
++{
++	u32 val = 0;
++	s32 ret = BCME_ERROR;
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++
++	/* Disable mpc, to avoid automatic interface down. */
++	val = 0;
++
++	ret = wldev_iovar_setbuf_bsscfg(ndev, "mpc", (void *)&val,
++		sizeof(val), cfg->ioctl_buf, WLC_IOCTL_SMLEN, 0,
++		&cfg->ioctl_buf_sync);
++	if (ret < 0) {
++		WL_ERR(("set 'mpc' failed, error = %d\n", ret));
++		goto done;
++	}
++
++	/* Set interface up, explicitly. */
++	val = 1;
++
++	ret = wldev_ioctl(ndev, WLC_UP, (void *)&val, sizeof(val), true);
++	if (ret < 0) {
++		WL_ERR(("set interface up failed, error = %d\n", ret));
++		goto done;
++	}
++
++	/* Stop all scan explicitly, till auto channel selection complete. */
++	wl_set_drv_status(cfg, SCANNING, ndev);
++	if (cfg->escan_info.ndev == NULL) {
++		ret = BCME_OK;
++		goto done;
++	}
++	ret = wl_notify_escan_complete(cfg, ndev, true, true);
++	if (ret < 0) {
++		WL_ERR(("set scan abort failed, error = %d\n", ret));
++		goto done;
++	}
++
++done:
++	return ret;
++}
++
++static bool
++wl_cfg80211_valid_channel_p2p(int channel)
++{
++	bool valid = false;
++
++	/* channel 1 to 14 */
++	if ((channel >= 1) && (channel <= 14)) {
++		valid = true;
++	}
++	/* channel 36 to 48 */
++	else if ((channel >= 36) && (channel <= 48)) {
++		valid = true;
++	}
++	/* channel 149 to 161 */
++	else if ((channel >= 149) && (channel <= 161)) {
++		valid = true;
++	}
++	else {
++		valid = false;
++		WL_INFORM(("invalid P2P chanspec, channel = %d\n", channel));
++	}
++
++	return valid;
++}
++
++s32
++wl_cfg80211_get_chanspecs_2g(struct net_device *ndev, void *buf, s32 buflen)
++{
++	s32 ret = BCME_ERROR;
++	struct bcm_cfg80211 *cfg = NULL;
++	chanspec_t chanspec = 0;
++
++	cfg = g_bcm_cfg;
++
++	/* Restrict channels to 2.4GHz, 20MHz BW, no SB. */
++	chanspec |= (WL_CHANSPEC_BAND_2G | WL_CHANSPEC_BW_20 |
++		WL_CHANSPEC_CTL_SB_NONE);
++	chanspec = wl_chspec_host_to_driver(chanspec);
++
++	ret = wldev_iovar_getbuf_bsscfg(ndev, "chanspecs", (void *)&chanspec,
++		sizeof(chanspec), buf, buflen, 0, &cfg->ioctl_buf_sync);
++	if (ret < 0) {
++		WL_ERR(("get 'chanspecs' failed, error = %d\n", ret));
++	}
++
++	return ret;
++}
++
++s32
++wl_cfg80211_get_chanspecs_5g(struct net_device *ndev, void *buf, s32 buflen)
++{
++	u32 channel = 0;
++	s32 ret = BCME_ERROR;
++	s32 i = 0;
++	s32 j = 0;
++	struct bcm_cfg80211 *cfg = NULL;
++	wl_uint32_list_t *list = NULL;
++	chanspec_t chanspec = 0;
++
++	cfg = g_bcm_cfg;
++
++	/* Restrict channels to 5GHz, 20MHz BW, no SB. */
++	chanspec |= (WL_CHANSPEC_BAND_5G | WL_CHANSPEC_BW_20 |
++		WL_CHANSPEC_CTL_SB_NONE);
++	chanspec = wl_chspec_host_to_driver(chanspec);
++
++	ret = wldev_iovar_getbuf_bsscfg(ndev, "chanspecs", (void *)&chanspec,
++		sizeof(chanspec), buf, buflen, 0, &cfg->ioctl_buf_sync);
++	if (ret < 0) {
++		WL_ERR(("get 'chanspecs' failed, error = %d\n", ret));
++		goto done;
++	}
++
++	list = (wl_uint32_list_t *)buf;
++	/* Skip DFS and inavlid P2P channel. */
++	for (i = 0, j = 0; i < dtoh32(list->count); i++) {
++		chanspec = (chanspec_t) dtoh32(list->element[i]);
++		channel = CHSPEC_CHANNEL(chanspec);
++
++		ret = wldev_iovar_getint(ndev, "per_chan_info", &channel);
++		if (ret < 0) {
++			WL_ERR(("get 'per_chan_info' failed, error = %d\n", ret));
++			goto done;
++		}
++
++		if (CHANNEL_IS_RADAR(channel) ||
++			!(wl_cfg80211_valid_channel_p2p(CHSPEC_CHANNEL(chanspec)))) {
++			continue;
++		} else {
++			list->element[j] = list->element[i];
++		}
++
++		j++;
++	}
++
++	list->count = j;
++
++done:
++	return ret;
++}
++
++static s32
++wl_cfg80211_get_best_channel(struct net_device *ndev, void *buf, int buflen,
++	int *channel)
++{
++	s32 ret = BCME_ERROR;
++	int chosen = 0;
++	int retry = 0;
++
++	/* Start auto channel selection scan. */
++	ret = wldev_ioctl(ndev, WLC_START_CHANNEL_SEL, buf, buflen, true);
++	if (ret < 0) {
++		WL_ERR(("can't start auto channel scan, error = %d\n", ret));
++		*channel = 0;
++		goto done;
++	}
++
++	/* Wait for auto channel selection, worst case possible delay is 5250ms. */
++	retry = CHAN_SEL_RETRY_COUNT;
++
++	while (retry--) {
++		OSL_SLEEP(CHAN_SEL_IOCTL_DELAY);
++
++		chosen = 0;
++		ret = wldev_ioctl(ndev, WLC_GET_CHANNEL_SEL, &chosen, sizeof(chosen),
++			false);
++		if ((ret == 0) && (dtoh32(chosen) != 0)) {
++			*channel = (u16)(chosen & 0x00FF);
++			WL_INFORM(("selected channel = %d\n", *channel));
++			break;
++		}
++		WL_INFORM(("attempt = %d, ret = %d, chosen = %d\n",
++			(CHAN_SEL_RETRY_COUNT - retry), ret, dtoh32(chosen)));
++	}
++
++	if (retry <= 0)	{
++		WL_ERR(("failure, auto channel selection timed out\n"));
++		*channel = 0;
++		ret = BCME_ERROR;
++	}
++
++done:
++	return ret;
++}
++
++static s32
++wl_cfg80211_restore_auto_channel_scan_state(struct net_device *ndev)
++{
++	u32 val = 0;
++	s32 ret = BCME_ERROR;
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++
++	/* Clear scan stop driver status. */
++	wl_clr_drv_status(cfg, SCANNING, ndev);
++
++	/* Enable mpc back to 1, irrespective of initial state. */
++	val = 1;
++
++	ret = wldev_iovar_setbuf_bsscfg(ndev, "mpc", (void *)&val,
++		sizeof(val), cfg->ioctl_buf, WLC_IOCTL_SMLEN, 0,
++		&cfg->ioctl_buf_sync);
++	if (ret < 0) {
++		WL_ERR(("set 'mpc' failed, error = %d\n", ret));
++	}
++
++	return ret;
++}
++
++s32
++wl_cfg80211_get_best_channels(struct net_device *dev, char* cmd, int total_len)
++{
++	int channel = 0;
++	s32 ret = BCME_ERROR;
++	u8 *buf = NULL;
++	char *pos = cmd;
++	struct bcm_cfg80211 *cfg = NULL;
++	struct net_device *ndev = NULL;
++
++	memset(cmd, 0, total_len);
++
++	buf = kzalloc(CHANSPEC_BUF_SIZE, GFP_KERNEL);
++	if (buf == NULL) {
++		WL_ERR(("failed to allocate chanspec buffer\n"));
++		return -ENOMEM;
++	}
++
++	/*
++	 * Always use primary interface, irrespective of interface on which
++	 * command came.
++	 */
++	cfg = g_bcm_cfg;
++	ndev = bcmcfg_to_prmry_ndev(cfg);
++
++	/*
++	 * Make sure that FW and driver are in right state to do auto channel
++	 * selection scan.
++	 */
++	ret = wl_cfg80211_set_auto_channel_scan_state(ndev);
++	if (ret < 0) {
++		WL_ERR(("can't set auto channel scan state, error = %d\n", ret));
++		goto done;
++	}
++
++	/* Best channel selection in 2.4GHz band. */
++	ret = wl_cfg80211_get_chanspecs_2g(ndev, (void *)buf, CHANSPEC_BUF_SIZE);
++	if (ret < 0) {
++		WL_ERR(("can't get chanspecs in 2.4GHz, error = %d\n", ret));
++		goto done;
++	}
++
++	ret = wl_cfg80211_get_best_channel(ndev, (void *)buf, CHANSPEC_BUF_SIZE,
++		&channel);
++	if (ret < 0) {
++		WL_ERR(("can't select best channel scan in 2.4GHz, error = %d\n", ret));
++		goto done;
++	}
++
++	if (CHANNEL_IS_2G(channel)) {
++		channel = ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ);
++	} else {
++		WL_ERR(("invalid 2.4GHz channel, channel = %d\n", channel));
++		channel = 0;
++	}
++
++	pos += snprintf(pos, total_len, "%04d ", channel);
++
++	/* Best channel selection in 5GHz band. */
++	ret = wl_cfg80211_get_chanspecs_5g(ndev, (void *)buf, CHANSPEC_BUF_SIZE);
++	if (ret < 0) {
++		WL_ERR(("can't get chanspecs in 5GHz, error = %d\n", ret));
++		goto done;
++	}
++
++	ret = wl_cfg80211_get_best_channel(ndev, (void *)buf, CHANSPEC_BUF_SIZE,
++		&channel);
++	if (ret < 0) {
++		WL_ERR(("can't select best channel scan in 5GHz, error = %d\n", ret));
++		goto done;
++	}
++
++	if (CHANNEL_IS_5G(channel)) {
++		channel = ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ);
++	} else {
++		WL_ERR(("invalid 5GHz channel, channel = %d\n", channel));
++		channel = 0;
++	}
++
++	pos += snprintf(pos, total_len, "%04d ", channel);
++
++	/* Set overall best channel same as 5GHz best channel. */
++	pos += snprintf(pos, total_len, "%04d ", channel);
++
++done:
++	if (NULL != buf) {
++		kfree(buf);
++	}
++
++	/* Restore FW and driver back to normal state. */
++	ret = wl_cfg80211_restore_auto_channel_scan_state(ndev);
++	if (ret < 0) {
++		WL_ERR(("can't restore auto channel scan state, error = %d\n", ret));
++	}
++
++	return (pos - cmd);
++}
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++
++static const struct rfkill_ops wl_rfkill_ops = {
++	.set_block = wl_rfkill_set
++};
++
++static int wl_rfkill_set(void *data, bool blocked)
++{
++	struct bcm_cfg80211 *cfg = (struct bcm_cfg80211 *)data;
++
++	WL_DBG(("Enter \n"));
++	WL_DBG(("RF %s\n", blocked ? "blocked" : "unblocked"));
++
++	if (!cfg)
++		return -EINVAL;
++
++	cfg->rf_blocked = blocked;
++
++	return 0;
++}
++
++static int wl_setup_rfkill(struct bcm_cfg80211 *cfg, bool setup)
++{
++	s32 err = 0;
++
++	WL_DBG(("Enter \n"));
++	if (!cfg)
++		return -EINVAL;
++	if (setup) {
++		cfg->rfkill = rfkill_alloc("brcmfmac-wifi",
++			wl_cfg80211_get_parent_dev(),
++			RFKILL_TYPE_WLAN, &wl_rfkill_ops, (void *)cfg);
++
++		if (!cfg->rfkill) {
++			err = -ENOMEM;
++			goto err_out;
++		}
++
++		err = rfkill_register(cfg->rfkill);
++
++		if (err)
++			rfkill_destroy(cfg->rfkill);
++	} else {
++		if (!cfg->rfkill) {
++			err = -ENOMEM;
++			goto err_out;
++		}
++
++		rfkill_unregister(cfg->rfkill);
++		rfkill_destroy(cfg->rfkill);
++	}
++
++err_out:
++	return err;
++}
++
++#ifdef DEBUGFS_CFG80211
++/**
++* Format : echo "SCAN:1 DBG:1" > /sys/kernel/debug/dhd/debug_level
++* to turn on SCAN and DBG log.
++* To turn off SCAN partially, echo "SCAN:0" > /sys/kernel/debug/dhd/debug_level
++* To see current setting of debug level,
++* cat /sys/kernel/debug/dhd/debug_level
++*/
++static ssize_t
++wl_debuglevel_write(struct file *file, const char __user *userbuf,
++	size_t count, loff_t *ppos)
++{
++	char tbuf[S_SUBLOGLEVEL * ARRAYSIZE(sublogname_map)], sublog[S_SUBLOGLEVEL];
++	char *params, *token, *colon;
++	uint i, tokens, log_on = 0;
++	memset(tbuf, 0, sizeof(tbuf));
++	memset(sublog, 0, sizeof(sublog));
++	if (copy_from_user(&tbuf, userbuf, min_t(size_t, (sizeof(tbuf) - 1), count)))
++		return -EFAULT;
++
++	params = &tbuf[0];
++	colon = strchr(params, '\n');
++	if (colon != NULL)
++		*colon = '\0';
++	while ((token = strsep(&params, " ")) != NULL) {
++		memset(sublog, 0, sizeof(sublog));
++		if (token == NULL || !*token)
++			break;
++		if (*token == '\0')
++			continue;
++		colon = strchr(token, ':');
++		if (colon != NULL) {
++			*colon = ' ';
++		}
++		tokens = sscanf(token, "%s %u", sublog, &log_on);
++		if (colon != NULL)
++			*colon = ':';
++
++		if (tokens == 2) {
++				for (i = 0; i < ARRAYSIZE(sublogname_map); i++) {
++					if (!strncmp(sublog, sublogname_map[i].sublogname,
++						strlen(sublogname_map[i].sublogname))) {
++						if (log_on)
++							wl_dbg_level |=
++							(sublogname_map[i].log_level);
++						else
++							wl_dbg_level &=
++							~(sublogname_map[i].log_level);
++					}
++				}
++		} else
++			WL_ERR(("%s: can't parse '%s' as a "
++			       "SUBMODULE:LEVEL (%d tokens)\n",
++			       tbuf, token, tokens));
++
++
++	}
++	return count;
++}
++
++static ssize_t
++wl_debuglevel_read(struct file *file, char __user *user_buf,
++	size_t count, loff_t *ppos)
++{
++	char *param;
++	char tbuf[S_SUBLOGLEVEL * ARRAYSIZE(sublogname_map)];
++	uint i;
++	memset(tbuf, 0, sizeof(tbuf));
++	param = &tbuf[0];
++	for (i = 0; i < ARRAYSIZE(sublogname_map); i++) {
++		param += snprintf(param, sizeof(tbuf) - 1, "%s:%d ",
++			sublogname_map[i].sublogname,
++			(wl_dbg_level & sublogname_map[i].log_level) ? 1 : 0);
++	}
++	*param = '\n';
++	return simple_read_from_buffer(user_buf, count, ppos, tbuf, strlen(&tbuf[0]));
++
++}
++static const struct file_operations fops_debuglevel = {
++	.open = NULL,
++	.write = wl_debuglevel_write,
++	.read = wl_debuglevel_read,
++	.owner = THIS_MODULE,
++	.llseek = NULL,
++};
++
++static s32 wl_setup_debugfs(struct bcm_cfg80211 *cfg)
++{
++	s32 err = 0;
++	struct dentry *_dentry;
++	if (!cfg)
++		return -EINVAL;
++	cfg->debugfs = debugfs_create_dir(KBUILD_MODNAME, NULL);
++	if (!cfg->debugfs || IS_ERR(cfg->debugfs)) {
++		if (cfg->debugfs == ERR_PTR(-ENODEV))
++			WL_ERR(("Debugfs is not enabled on this kernel\n"));
++		else
++			WL_ERR(("Can not create debugfs directory\n"));
++		cfg->debugfs = NULL;
++		goto exit;
++
++	}
++	_dentry = debugfs_create_file("debug_level", S_IRUSR | S_IWUSR,
++		cfg->debugfs, cfg, &fops_debuglevel);
++	if (!_dentry || IS_ERR(_dentry)) {
++		WL_ERR(("failed to create debug_level debug file\n"));
++		wl_free_debugfs(cfg);
++	}
++exit:
++	return err;
++}
++static s32 wl_free_debugfs(struct bcm_cfg80211 *cfg)
++{
++	if (!cfg)
++		return -EINVAL;
++	if (cfg->debugfs)
++		debugfs_remove_recursive(cfg->debugfs);
++	cfg->debugfs = NULL;
++	return 0;
++}
++#endif /* DEBUGFS_CFG80211 */
++
++struct device *wl_cfg80211_get_parent_dev(void)
++{
++	return cfg80211_parent_dev;
++}
++
++void wl_cfg80211_set_parent_dev(void *dev)
++{
++	cfg80211_parent_dev = dev;
++}
++
++static void wl_cfg80211_clear_parent_dev(void)
++{
++	cfg80211_parent_dev = NULL;
++}
++
++void get_primary_mac(struct bcm_cfg80211 *cfg, struct ether_addr *mac)
++{
++	wldev_iovar_getbuf_bsscfg(bcmcfg_to_prmry_ndev(cfg), "cur_etheraddr", NULL,
++		0, cfg->ioctl_buf, WLC_IOCTL_SMLEN, 0, &cfg->ioctl_buf_sync);
++	memcpy(mac->octet, cfg->ioctl_buf, ETHER_ADDR_LEN);
++}
++static bool check_dev_role_integrity(struct bcm_cfg80211 *cfg, u32 dev_role)
++{
++	dhd_pub_t *dhd = (dhd_pub_t *)(cfg->pub);
++	if (((dev_role == NL80211_IFTYPE_AP) &&
++		!(dhd->op_mode & DHD_FLAG_HOSTAP_MODE)) ||
++		((dev_role == NL80211_IFTYPE_P2P_GO) &&
++		!(dhd->op_mode & DHD_FLAG_P2P_GO_MODE)))
++	{
++		WL_ERR(("device role select failed role:%d op_mode:%d \n", dev_role, dhd->op_mode));
++		return false;
++	}
++	return true;
++}
++
++int wl_cfg80211_do_driver_init(struct net_device *net)
++{
++	struct bcm_cfg80211 *cfg = *(struct bcm_cfg80211 **)netdev_priv(net);
++
++	if (!cfg || !cfg->wdev)
++		return -EINVAL;
++
++	if (dhd_do_driver_init(cfg->wdev->netdev) < 0)
++		return -1;
++
++	return 0;
++}
++
++void wl_cfg80211_enable_trace(bool set, u32 level)
++{
++	if (set)
++		wl_dbg_level = level & WL_DBG_LEVEL;
++	else
++		wl_dbg_level |= (WL_DBG_LEVEL & level);
++}
++#if defined(WL_SUPPORT_BACKPORTED_KPATCHES) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, \
++	2, 0))
++static s32
++wl_cfg80211_mgmt_tx_cancel_wait(struct wiphy *wiphy,
++	bcm_struct_cfgdev *cfgdev, u64 cookie)
++{
++	/* CFG80211 checks for tx_cancel_wait callback when ATTR_DURATION
++	 * is passed with CMD_FRAME. This callback is supposed to cancel
++	 * the OFFCHANNEL Wait. Since we are already taking care of that
++	 *  with the tx_mgmt logic, do nothing here.
++	 */
++
++	return 0;
++}
++#endif /* WL_SUPPORT_BACKPORTED_PATCHES || KERNEL >= 3.2.0 */
++
++#ifdef WL11U
++bcm_tlv_t *
++wl_cfg80211_find_interworking_ie(u8 *parse, u32 len)
++{
++	bcm_tlv_t *ie;
++
++	while ((ie = bcm_parse_tlvs(parse, (u32)len, DOT11_MNG_INTERWORKING_ID))) {
++			return (bcm_tlv_t *)ie;
++	}
++	return NULL;
++}
++
++
++static s32
++wl_cfg80211_add_iw_ie(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 bssidx, s32 pktflag,
++            uint8 ie_id, uint8 *data, uint8 data_len)
++{
++	s32 err = BCME_OK;
++	s32 buf_len;
++	s32 iecount;
++	ie_setbuf_t *ie_setbuf;
++
++	if (ie_id != DOT11_MNG_INTERWORKING_ID)
++		return BCME_UNSUPPORTED;
++
++	/* Validate the pktflag parameter */
++	if ((pktflag & ~(VNDR_IE_BEACON_FLAG | VNDR_IE_PRBRSP_FLAG |
++	            VNDR_IE_ASSOCRSP_FLAG | VNDR_IE_AUTHRSP_FLAG |
++	            VNDR_IE_PRBREQ_FLAG | VNDR_IE_ASSOCREQ_FLAG|
++	            VNDR_IE_CUSTOM_FLAG))) {
++		WL_ERR(("cfg80211 Add IE: Invalid packet flag 0x%x\n", pktflag));
++		return -1;
++	}
++
++	/* use VNDR_IE_CUSTOM_FLAG flags for none vendor IE . currently fixed value */
++	pktflag = htod32(pktflag);
++
++	buf_len = sizeof(ie_setbuf_t) + data_len - 1;
++	ie_setbuf = (ie_setbuf_t *) kzalloc(buf_len, GFP_KERNEL);
++
++	if (!ie_setbuf) {
++		WL_ERR(("Error allocating buffer for IE\n"));
++		return -ENOMEM;
++	}
++
++	if (cfg->iw_ie_len == data_len && !memcmp(cfg->iw_ie, data, data_len)) {
++		WL_ERR(("Previous IW IE is equals to current IE\n"));
++		err = BCME_OK;
++		goto exit;
++	}
++
++	strncpy(ie_setbuf->cmd, "add", VNDR_IE_CMD_LEN - 1);
++	ie_setbuf->cmd[VNDR_IE_CMD_LEN - 1] = '\0';
++
++	/* Buffer contains only 1 IE */
++	iecount = htod32(1);
++	memcpy((void *)&ie_setbuf->ie_buffer.iecount, &iecount, sizeof(int));
++	memcpy((void *)&ie_setbuf->ie_buffer.ie_list[0].pktflag, &pktflag, sizeof(uint32));
++
++	/* Now, add the IE to the buffer */
++	ie_setbuf->ie_buffer.ie_list[0].ie_data.id = ie_id;
++
++	/* if already set with previous values, delete it first */
++	if (cfg->iw_ie_len != 0) {
++		WL_DBG(("Different IW_IE was already set. clear first\n"));
++
++		ie_setbuf->ie_buffer.ie_list[0].ie_data.len = 0;
++
++		err = wldev_iovar_setbuf_bsscfg(ndev, "ie", ie_setbuf, buf_len,
++			cfg->ioctl_buf, WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++
++		if (err != BCME_OK)
++			goto exit;
++	}
++
++	ie_setbuf->ie_buffer.ie_list[0].ie_data.len = data_len;
++	memcpy((uchar *)&ie_setbuf->ie_buffer.ie_list[0].ie_data.data[0], data, data_len);
++
++	err = wldev_iovar_setbuf_bsscfg(ndev, "ie", ie_setbuf, buf_len,
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++
++	if (err == BCME_OK) {
++		memcpy(cfg->iw_ie, data, data_len);
++		cfg->iw_ie_len = data_len;
++		cfg->wl11u = TRUE;
++
++		err = wldev_iovar_setint_bsscfg(ndev, "grat_arp", 1, bssidx);
++	}
++
++exit:
++	if (ie_setbuf)
++		kfree(ie_setbuf);
++	return err;
++}
++#endif /* WL11U */
++
++s32
++wl_cfg80211_dfs_ap_move(struct net_device *ndev, char *data, char *command, int total_len)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	char ioctl_buf[50];
++	int err = 0;
++	uint32 val = 0;
++	chanspec_t chanspec = 0;
++	int abort;
++	int bytes_written = 0;
++	wl_dfs_ap_move_status_t *status;
++	char chanbuf[CHANSPEC_STR_LEN];
++	const char *dfs_state_str[DFS_SCAN_S_MAX] = {
++		"Radar Free On Channel",
++		"Radar Found On Channel",
++		"Radar Scan In Progress",
++		"Radar Scan Aborted",
++		"RSDB Mode switch in Progress For Scan"
++	};
++	if (ndev->ieee80211_ptr->iftype != NL80211_IFTYPE_AP) {
++		bytes_written = snprintf(command, total_len, "AP is not UP\n");
++		return bytes_written;
++	}
++	if (!*data) {
++		if ((err = wldev_iovar_getbuf(ndev, "dfs_ap_move", NULL, 0,
++				cfg->ioctl_buf, WLC_IOCTL_MAXLEN,  &cfg->ioctl_buf_sync))) {
++			WL_ERR(("setting dfs_ap_move failed with err=%d \n", err));
++			return err;
++		}
++		status = (wl_dfs_ap_move_status_t *)cfg->ioctl_buf;
++
++		if (status->version != WL_DFS_AP_MOVE_VERSION) {
++			err = BCME_UNSUPPORTED;
++			WL_ERR(("err=%d version=%d\n", err, status->version));
++			return err;
++		}
++
++		if (status->move_status != (int8) DFS_SCAN_S_IDLE) {
++			chanspec = wl_chspec_driver_to_host(status->chanspec);
++			if (chanspec != 0 && chanspec != INVCHANSPEC) {
++				wf_chspec_ntoa(chanspec, chanbuf);
++				bytes_written = snprintf(command, total_len,
++					"AP Target Chanspec %s (0x%x)\n", chanbuf, chanspec);
++			}
++			bytes_written += snprintf(command + bytes_written, total_len,
++					 "%s\n", dfs_state_str[status->move_status]);
++			return bytes_written;
++		} else {
++			bytes_written = snprintf(command, total_len, "dfs AP move in IDLE state\n");
++			return bytes_written;
++		}
++
++	}
++
++	abort = bcm_atoi(data);
++	if (abort == -1) {
++		if ((err = wldev_iovar_setbuf(ndev, "dfs_ap_move", &abort,
++				sizeof(int), ioctl_buf, sizeof(ioctl_buf), NULL)) < 0) {
++			WL_ERR(("seting dfs_ap_move failed with err %d\n", err));
++			return err;
++		}
++	} else {
++		chanspec = wf_chspec_aton(data);
++		if (chanspec != 0) {
++			val = wl_chspec_host_to_driver(chanspec);
++			if (val != INVCHANSPEC) {
++				if ((err = wldev_iovar_setbuf(ndev, "dfs_ap_move", &val,
++					sizeof(int), ioctl_buf, sizeof(ioctl_buf), NULL)) < 0) {
++					WL_ERR(("seting dfs_ap_move failed with err %d\n", err));
++					return err;
++				}
++				WL_DBG((" set dfs_ap_move successfull"));
++			} else {
++				err = BCME_USAGE_ERROR;
++			}
++		}
++	}
++	return err;
++}
++
++s32
++wl_cfg80211_wbtext_config(struct net_device *ndev, char *data, char *command, int total_len)
++{
++	uint i = 0;
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	wl_roam_prof_band_t *rp;
++	int err = -EINVAL, bytes_written = 0;
++	size_t len = strlen(data);
++	data[len] = '\0';
++
++	rp = (wl_roam_prof_band_t *) kzalloc(sizeof(*rp)
++			* WL_MAX_ROAM_PROF_BRACKETS, GFP_KERNEL);
++	if (unlikely(!rp)) {
++		WL_ERR(("%s: failed to allocate memory\n", __func__));
++		err =  -ENOMEM;
++		goto exit;
++	}
++
++	rp->ver = WL_MAX_ROAM_PROF_VER;
++	if (*data && (!strncmp(data, "b", 1))) {
++		rp->band = WLC_BAND_2G;
++	} else if (*data && (!strncmp(data, "a", 1))) {
++		rp->band = WLC_BAND_5G;
++	} else {
++		err = snprintf(command, total_len, "Missing band\n");
++		goto exit;
++	}
++	rp->len = 0;
++	data++;
++	if (!*data) {
++		/* Getting roam profile  from fw */
++		if ((err = wldev_iovar_getbuf(ndev, "roam_prof", rp, sizeof(*rp),
++			cfg->ioctl_buf, WLC_IOCTL_MAXLEN,  &cfg->ioctl_buf_sync))) {
++			WL_ERR(("Getting roam_profile failed with err=%d \n", err));
++			goto exit;
++		}
++		memcpy(rp, cfg->ioctl_buf, sizeof(*rp) * WL_MAX_ROAM_PROF_BRACKETS);
++		/* roam_prof version get */
++		if (rp->ver != WL_MAX_ROAM_PROF_VER) {
++			WL_ERR(("bad version (=%d) in return data\n", rp->ver));
++			err = -EINVAL;
++			goto exit;
++		}
++		if ((rp->len % sizeof(wl_roam_prof_t)) != 0) {
++			WL_ERR(("bad length (=%d) in return data\n", rp->len));
++			err = -EINVAL;
++			goto exit;
++		}
++		for (i = 0; i < WL_MAX_ROAM_PROF_BRACKETS; i++) {
++			/* printing contents of roam profile data from fw and exits
++			 * if code hits any of one of the below condtion.
++			 */
++			if (((i * sizeof(wl_roam_prof_t)) > rp->len) ||
++				(rp->roam_prof[i].fullscan_period == 0)) {
++				break;
++			}
++
++			bytes_written += snprintf(command+bytes_written,
++					total_len, "RSSI[%d,%d] CU(trigger:%d%%: duration:%ds)\n",
++					rp->roam_prof[i].roam_trigger, rp->roam_prof[i].rssi_lower,
++					rp->roam_prof[i].channel_usage,
++					rp->roam_prof[i].cu_avg_calc_dur);
++		}
++		err = bytes_written;
++		goto exit;
++	} else {
++		/* setting roam profile to fw */
++		data++;
++		memset(rp->roam_prof, 0, sizeof(wl_roam_prof_t) * WL_MAX_ROAM_PROF_BRACKETS);
++		for (i = 0; i < WL_MAX_ROAM_PROF_BRACKETS; i++) {
++			rp->roam_prof[i].roam_trigger = simple_strtol(data, &data, 10);
++			data++;
++			rp->roam_prof[i].rssi_lower = simple_strtol(data, &data, 10);
++			data++;
++			rp->roam_prof[i].channel_usage = simple_strtol(data, &data, 10);
++			data++;
++			rp->roam_prof[i].cu_avg_calc_dur = simple_strtol(data, &data, 10);
++			/* filling rows */
++			rp->roam_prof[i].roam_flags = WL_ROAM_PROF_DEFAULT;
++			rp->roam_prof[i].rssi_boost_thresh = WL_JOIN_PREF_RSSI_BOOST_MIN;
++			rp->roam_prof[i].rssi_boost_delta = 0;
++			rp->roam_prof[i].nfscan = WL_ROAM_FULLSCAN_NTIMES;
++			rp->roam_prof[i].fullscan_period = WL_FULLROAM_PERIOD;
++			rp->roam_prof[i].init_scan_period = WL_ROAM_SCAN_PERIOD;
++			rp->roam_prof[i].backoff_multiplier = 1;
++			rp->roam_prof[i].max_scan_period = WL_ROAM_SCAN_PERIOD;
++			if (rp->band == WLC_BAND_2G)
++				rp->roam_prof[i].roam_delta = WL_ROAM_DELTA_2G;
++			else
++				rp->roam_prof[i].roam_delta = WL_ROAM_DELTA_5G;
++
++			/* update roam_delta to default score for cu enabled roam profile entry */
++			if (rp->roam_prof[i].channel_usage != 0) {
++				rp->roam_prof[i].roam_delta = WL_SCORE_DELTA_DEFAULT;
++			}
++
++			rp->len += sizeof(wl_roam_prof_t);
++
++			if (*data == '\0') {
++				break;
++			}
++			data++;
++		}
++		if ((err = wldev_iovar_setbuf(ndev, "roam_prof", rp,
++				8 + rp->len, cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL)) < 0) {
++			WL_ERR(("seting roam_profile failed with err %d\n", err));
++		}
++	}
++exit:
++	if (rp) {
++		kfree(rp);
++	}
++	return err;
++}
++
++int wl_cfg80211_wbtext_weight_config(struct net_device *ndev, char *data,
++		char *command, int total_len)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	int bytes_written = 0, err = -EINVAL, argc = 0;
++	char rssi[5], band[5], weight[5];
++	char *endptr = NULL;
++	wnm_bss_select_weight_cfg_t *bwcfg;
++
++	bwcfg = kzalloc(sizeof(*bwcfg), GFP_KERNEL);
++	if (unlikely(!bwcfg)) {
++		WL_ERR(("%s: failed to allocate memory\n", __func__));
++		err = -ENOMEM;
++		goto exit;
++	}
++	bwcfg->version =  WNM_BSSLOAD_MONITOR_VERSION;
++	bwcfg->type = 0;
++	bwcfg->weight = 0;
++
++	argc = sscanf(data, "%s %s %s", rssi, band, weight);
++
++	if (!strcasecmp(rssi, "rssi"))
++		bwcfg->type = WNM_BSS_SELECT_TYPE_RSSI;
++	else if (!strcasecmp(rssi, "cu"))
++		bwcfg->type = WNM_BSS_SELECT_TYPE_CU;
++	else {
++		/* Usage DRIVER WBTEXT_WEIGHT_CONFIG <rssi/cu> <band> <weight> */
++		WL_ERR(("%s: Command usage error\n", __func__));
++		goto exit;
++	}
++
++	if (!strcasecmp(band, "a"))
++		bwcfg->band = WLC_BAND_5G;
++	else if (!strcasecmp(band, "b"))
++		bwcfg->band = WLC_BAND_2G;
++	else if (!strcasecmp(band, "all"))
++		bwcfg->band = WLC_BAND_ALL;
++	else {
++		WL_ERR(("%s: Command usage error\n", __func__));
++		goto exit;
++	}
++
++	if (argc == 2) {
++		/* If there is no data after band, getting wnm_bss_select_weight from fw */
++		if (bwcfg->band == WLC_BAND_ALL) {
++			WL_ERR(("band option \"all\" is for set only, not get\n"));
++			goto exit;
++		}
++		if ((err = wldev_iovar_getbuf(ndev, "wnm_bss_select_weight", bwcfg,
++				sizeof(*bwcfg),
++				cfg->ioctl_buf, WLC_IOCTL_MAXLEN,  &cfg->ioctl_buf_sync))) {
++			WL_ERR(("Getting wnm_bss_select_weight failed with err=%d \n", err));
++			goto exit;
++		}
++		memcpy(bwcfg, cfg->ioctl_buf, sizeof(*bwcfg));
++		bytes_written = snprintf(command, total_len, "%s %s weight = %d\n",
++			(bwcfg->type == WNM_BSS_SELECT_TYPE_RSSI) ? "RSSI" : "CU",
++			(bwcfg->band == WLC_BAND_2G) ? "2G" : "5G", bwcfg->weight);
++		err = bytes_written;
++		goto exit;
++	} else {
++		/* if weight is non integer returns command usage error */
++		bwcfg->weight = simple_strtol(weight, &endptr, 0);
++		if (*endptr != '\0') {
++			WL_ERR(("%s: Command usage error", __func__));
++			goto exit;
++		}
++		/* setting weight for iovar wnm_bss_select_weight to fw */
++		if ((err = wldev_iovar_setbuf(ndev, "wnm_bss_select_weight", bwcfg,
++				sizeof(*bwcfg),
++				cfg->ioctl_buf, WLC_IOCTL_MAXLEN,  &cfg->ioctl_buf_sync))) {
++			WL_ERR(("Getting wnm_bss_select_weight failed with err=%d\n", err));
++		}
++	}
++exit:
++	if (bwcfg) {
++		kfree(bwcfg);
++	}
++	return err;
++}
++
++/* WBTEXT_TUPLE_MIN_LEN_CHECK :strlen(low)+" "+strlen(high)+" "+strlen(factor) */
++#define WBTEXT_TUPLE_MIN_LEN_CHECK 5
++
++int wl_cfg80211_wbtext_table_config(struct net_device *ndev, char *data,
++	char *command, int total_len)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	int bytes_written = 0, err = -EINVAL;
++	char rssi[5], band[5];
++	int btcfg_len = 0, i = 0, parsed_len = 0;
++	wnm_bss_select_factor_cfg_t *btcfg;
++	size_t slen = strlen(data);
++	char *start_addr = NULL;
++	data[slen] = '\0';
++
++	btcfg = kzalloc((sizeof(*btcfg) + sizeof(*btcfg) *
++			WL_FACTOR_TABLE_MAX_LIMIT), GFP_KERNEL);
++	if (unlikely(!btcfg)) {
++		WL_ERR(("%s: failed to allocate memory\n", __func__));
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	btcfg->version = WNM_BSS_SELECT_FACTOR_VERSION;
++	btcfg->band = WLC_BAND_AUTO;
++	btcfg->type = 0;
++	btcfg->count = 0;
++
++	sscanf(data, "%s %s", rssi, band);
++
++	if (!strcasecmp(rssi, "rssi")) {
++		btcfg->type = WNM_BSS_SELECT_TYPE_RSSI;
++	}
++	else if (!strcasecmp(rssi, "cu")) {
++		btcfg->type = WNM_BSS_SELECT_TYPE_CU;
++	}
++	else {
++		WL_ERR(("%s: Command usage error\n", __func__));
++		goto exit;
++	}
++
++	if (!strcasecmp(band, "a")) {
++		btcfg->band = WLC_BAND_5G;
++	}
++	else if (!strcasecmp(band, "b")) {
++		btcfg->band = WLC_BAND_2G;
++	}
++	else if (!strcasecmp(band, "all")) {
++		btcfg->band = WLC_BAND_ALL;
++	}
++	else {
++		WL_ERR(("%s: Command usage, Wrong band\n", __func__));
++		goto exit;
++	}
++
++	if ((slen - 1) == (strlen(rssi) + strlen(band))) {
++		/* Getting factor table using iovar 'wnm_bss_select_table' from fw */
++		if ((err = wldev_iovar_getbuf(ndev, "wnm_bss_select_table", btcfg,
++				sizeof(*btcfg),
++				cfg->ioctl_buf, WLC_IOCTL_MAXLEN,  &cfg->ioctl_buf_sync))) {
++			WL_ERR(("Getting wnm_bss_select_table failed with err=%d \n", err));
++			goto exit;
++		}
++		memcpy(btcfg, cfg->ioctl_buf, sizeof(*btcfg));
++		memcpy(btcfg, cfg->ioctl_buf, (btcfg->count+1) * sizeof(*btcfg));
++
++		bytes_written += snprintf(command + bytes_written, total_len,
++					"No of entries in table: %d\n", btcfg->count);
++		bytes_written += snprintf(command + bytes_written, total_len, "%s factor table\n",
++				(btcfg->type == WNM_BSS_SELECT_TYPE_RSSI) ? "RSSI" : "CU");
++		bytes_written += snprintf(command + bytes_written, total_len,
++					"low\thigh\tfactor\n");
++		for (i = 0; i <= btcfg->count-1; i++) {
++			bytes_written += snprintf(command + bytes_written, total_len,
++				"%d\t%d\t%d\n", btcfg->params[i].low, btcfg->params[i].high,
++				btcfg->params[i].factor);
++		}
++		err = bytes_written;
++		goto exit;
++	} else {
++		memset(btcfg->params, 0, sizeof(*btcfg) * WL_FACTOR_TABLE_MAX_LIMIT);
++		data += (strlen(rssi) + strlen(band) + 2);
++		start_addr = data;
++		slen = slen - (strlen(rssi) + strlen(band) + 2);
++		for (i = 0; i < WL_FACTOR_TABLE_MAX_LIMIT; i++) {
++			if (parsed_len + WBTEXT_TUPLE_MIN_LEN_CHECK <= slen) {
++				btcfg->params[i].low = simple_strtol(data, &data, 10);
++				data++;
++				btcfg->params[i].high = simple_strtol(data, &data, 10);
++				data++;
++				btcfg->params[i].factor = simple_strtol(data, &data, 10);
++				btcfg->count++;
++				if (*data == '\0') {
++					break;
++				}
++				data++;
++				parsed_len = data - start_addr;
++			} else {
++				WL_ERR(("%s:Command usage:less no of args\n", __func__));
++				goto exit;
++			}
++		}
++		btcfg_len = sizeof(*btcfg) + ((btcfg->count) * sizeof(*btcfg));
++		if ((err = wldev_iovar_setbuf(ndev, "wnm_bss_select_table", btcfg, btcfg_len,
++				cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL)) < 0) {
++			WL_ERR(("seting wnm_bss_select_table failed with err %d\n", err));
++			goto exit;
++		}
++	}
++exit:
++	if (btcfg) {
++		kfree(btcfg);
++	}
++	return err;
++}
++
++s32
++wl_cfg80211_wbtext_delta_config(struct net_device *ndev, char *data, char *command, int total_len)
++{
++	uint i = 0;
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	int err = -EINVAL, bytes_written = 0, argc = 0, val, len = 0;
++	char delta[5], band[5], *endptr = NULL;
++	wl_roam_prof_band_t *rp;
++
++	rp = (wl_roam_prof_band_t *) kzalloc(sizeof(*rp)
++			* WL_MAX_ROAM_PROF_BRACKETS, GFP_KERNEL);
++	if (unlikely(!rp)) {
++		WL_ERR(("%s: failed to allocate memory\n", __func__));
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	argc = sscanf(data, "%s %s", band, delta);
++	if (argc == 2) {
++		if (!strcasecmp(band, "a"))
++			rp->band = WLC_BAND_5G;
++		else if (!strcasecmp(band, "b"))
++			rp->band = WLC_BAND_2G;
++		else {
++			WL_ERR(("%s: Missing band\n", __func__));
++			goto exit;
++		}
++		/* if delta is non integer returns command usage error */
++		val = simple_strtol(delta, &endptr, 0);
++		if (*endptr != '\0') {
++			WL_ERR(("%s: Command usage error", __func__));
++			goto exit;
++		}
++		/* Getting roam profile  from fw */
++		if ((err = wldev_iovar_getbuf(ndev, "roam_prof", rp, sizeof(*rp),
++			cfg->ioctl_buf, WLC_IOCTL_MAXLEN,  &cfg->ioctl_buf_sync))) {
++			WL_ERR(("Getting roam_profile failed with err=%d \n", err));
++			goto exit;
++		}
++		memcpy(rp, cfg->ioctl_buf, sizeof(wl_roam_prof_band_t));
++		if (rp->ver != WL_MAX_ROAM_PROF_VER) {
++			WL_ERR(("bad version (=%d) in return data\n", rp->ver));
++			err = -EINVAL;
++			goto exit;
++		}
++		if ((rp->len % sizeof(wl_roam_prof_t)) != 0) {
++			WL_ERR(("bad length (=%d) in return data\n", rp->len));
++			err = -EINVAL;
++			goto exit;
++		}
++		for (i = 0; i < WL_MAX_ROAM_PROF_BRACKETS; i++) {
++		/* printing contents of roam profile data from fw and exits
++		 * if code hits below condtion.
++		 */
++			if (((i * sizeof(wl_roam_prof_t)) > rp->len) ||
++				(rp->roam_prof[i].fullscan_period == 0)) {
++				break;
++			}
++			if (rp->roam_prof[i].channel_usage != 0) {
++				rp->roam_prof[i].roam_delta = val;
++			}
++			len += sizeof(wl_roam_prof_t);
++		}
++	}
++	else {
++		bytes_written = snprintf(command, total_len, "Usage error, less args\n");
++		err = bytes_written;
++		goto exit;
++	}
++	rp->len = len;
++	if ((err = wldev_iovar_setbuf(ndev, "roam_prof", rp,
++			sizeof(*rp), cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL)) < 0) {
++		WL_ERR(("seting roam_profile failed with err %d\n", err));
++	}
++exit :
++	if (rp) {
++		kfree(rp);
++	}
++	return err;
++}
++
++
++int wl_cfg80211_scan_stop(bcm_struct_cfgdev *cfgdev)
++{
++	struct bcm_cfg80211 *cfg = NULL;
++	struct net_device *ndev = NULL;
++	unsigned long flags;
++	int clear_flag = 0;
++	int ret = 0;
++
++	WL_TRACE(("Enter\n"));
++
++	cfg = g_bcm_cfg;
++	if (!cfg)
++		return -EINVAL;
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	spin_lock_irqsave(&cfg->cfgdrv_lock, flags);
++#ifdef WL_CFG80211_P2P_DEV_IF
++	if (cfg->scan_request && cfg->scan_request->wdev == cfgdev) {
++#else
++	if (cfg->scan_request && cfg->scan_request->dev == cfgdev) {
++#endif
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(4, 8, 0))
++		struct cfg80211_scan_info info = { .aborted = true };
++		cfg80211_scan_done(cfg->scan_request, &info);
++#else
++		cfg80211_scan_done(cfg->scan_request, true);
++#endif
++		cfg->scan_request = NULL;
++		clear_flag = 1;
++	}
++	spin_unlock_irqrestore(&cfg->cfgdrv_lock, flags);
++
++	if (clear_flag)
++		wl_clr_drv_status(cfg, SCANNING, ndev);
++
++	return ret;
++}
++
++bool wl_cfg80211_is_vsdb_mode(void)
++{
++	return (g_bcm_cfg && g_bcm_cfg->vsdb_mode);
++}
++
++void* wl_cfg80211_get_dhdp()
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++
++	return cfg->pub;
++}
++
++bool wl_cfg80211_is_p2p_active(void)
++{
++	return (g_bcm_cfg && g_bcm_cfg->p2p);
++}
++
++bool wl_cfg80211_is_roam_offload(void)
++{
++	return (g_bcm_cfg && g_bcm_cfg->roam_offload);
++}
++
++bool wl_cfg80211_is_event_from_connected_bssid(const wl_event_msg_t *e, int ifidx)
++{
++	dhd_pub_t *dhd = NULL;
++	struct net_device *ndev = NULL;
++	u8 *curbssid = NULL;
++
++	dhd = (dhd_pub_t *)(g_bcm_cfg->pub);
++
++	if (dhd) {
++		ndev = dhd_idx2net(dhd, ifidx);
++	}
++
++	if (!dhd || !ndev) {
++		return false;
++	}
++
++	curbssid = wl_read_prof(g_bcm_cfg, ndev, WL_PROF_BSSID);
++
++	if (memcmp(curbssid, &e->addr, ETHER_ADDR_LEN) == 0) {
++		return true;
++	}
++	return false;
++}
++
++static void wl_cfg80211_work_handler(struct work_struct * work)
++{
++	struct bcm_cfg80211 *cfg = NULL;
++	struct net_info *iter, *next;
++	s32 err = BCME_OK;
++	s32 pm = PM_FAST;
++	BCM_SET_CONTAINER_OF(cfg, work, struct bcm_cfg80211, pm_enable_work.work);
++	WL_DBG(("Enter \n"));
++	if (cfg->pm_enable_work_on) {
++		cfg->pm_enable_work_on = false;
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++		for_each_ndev(cfg, iter, next) {
++			/* p2p discovery iface ndev could be null */
++			if (iter->ndev) {
++				if (!wl_get_drv_status(cfg, CONNECTED, iter->ndev) ||
++					(wl_get_mode_by_netdev(cfg, iter->ndev) != WL_MODE_BSS &&
++					wl_get_mode_by_netdev(cfg, iter->ndev) != WL_MODE_IBSS))
++					continue;
++				if (iter->ndev) {
++					if ((err = wldev_ioctl(iter->ndev, WLC_SET_PM,
++						&pm, sizeof(pm), true)) != 0) {
++						if (err == -ENODEV)
++							WL_DBG(("%s:netdev not ready\n",
++								iter->ndev->name));
++						else
++							WL_ERR(("%s:error (%d)\n",
++								iter->ndev->name, err));
++					} else
++						wl_cfg80211_update_power_mode(iter->ndev);
++				}
++			}
++		}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	}
++}
++
++u8
++wl_get_action_category(void *frame, u32 frame_len)
++{
++	u8 category;
++	u8 *ptr = (u8 *)frame;
++	if (frame == NULL)
++		return DOT11_ACTION_CAT_ERR_MASK;
++	if (frame_len < DOT11_ACTION_HDR_LEN)
++		return DOT11_ACTION_CAT_ERR_MASK;
++	category = ptr[DOT11_ACTION_CAT_OFF];
++	WL_INFORM(("Action Category: %d\n", category));
++	return category;
++}
++
++int
++wl_get_public_action(void *frame, u32 frame_len, u8 *ret_action)
++{
++	u8 *ptr = (u8 *)frame;
++	if (frame == NULL || ret_action == NULL)
++		return BCME_ERROR;
++	if (frame_len < DOT11_ACTION_HDR_LEN)
++		return BCME_ERROR;
++	if (DOT11_ACTION_CAT_PUBLIC != wl_get_action_category(frame, frame_len))
++		return BCME_ERROR;
++	*ret_action = ptr[DOT11_ACTION_ACT_OFF];
++	WL_INFORM(("Public Action : %d\n", *ret_action));
++	return BCME_OK;
++}
++
++#ifdef WLFBT
++void
++wl_cfg80211_get_fbt_key(uint8 *key)
++{
++	memcpy(key, g_bcm_cfg->fbt_key, FBT_KEYLEN);
++}
++#endif /* WLFBT */
++
++static int
++wl_cfg80211_delayed_roam(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	const struct ether_addr *bssid)
++{
++	s32 err;
++	wl_event_msg_t e;
++
++	bzero(&e, sizeof(e));
++	e.event_type = cpu_to_be32(WLC_E_BSSID);
++	memcpy(&e.addr, bssid, ETHER_ADDR_LEN);
++	/* trigger the roam event handler */
++	WL_INFORM(("Delayed roam to " MACDBG "\n", MAC2STRDBG((u8*)(bssid))));
++	err = wl_notify_roaming_status(cfg, ndev_to_cfgdev(ndev), &e, NULL);
++
++	return err;
++}
++
++static s32
++wl_cfg80211_parse_vndr_ies(u8 *parse, u32 len,
++    struct parsed_vndr_ies *vndr_ies)
++{
++	s32 err = BCME_OK;
++	vndr_ie_t *vndrie;
++	bcm_tlv_t *ie;
++	struct parsed_vndr_ie_info *parsed_info;
++	u32 count = 0;
++	s32 remained_len;
++
++	remained_len = (s32)len;
++	memset(vndr_ies, 0, sizeof(*vndr_ies));
++
++	WL_INFORM(("---> len %d\n", len));
++	ie = (bcm_tlv_t *) parse;
++	if (!bcm_valid_tlv(ie, remained_len))
++		ie = NULL;
++	while (ie) {
++		if (count >= MAX_VNDR_IE_NUMBER)
++			break;
++		if (ie->id == DOT11_MNG_VS_ID) {
++			vndrie = (vndr_ie_t *) ie;
++			/* len should be bigger than OUI length + one data length at least */
++			if (vndrie->len < (VNDR_IE_MIN_LEN + 1)) {
++				WL_ERR(("%s: invalid vndr ie. length is too small %d\n",
++					__FUNCTION__, vndrie->len));
++				goto end;
++			}
++			/* if wpa or wme ie, do not add ie */
++			if (!bcmp(vndrie->oui, (u8*)WPA_OUI, WPA_OUI_LEN) &&
++				((vndrie->data[0] == WPA_OUI_TYPE) ||
++				(vndrie->data[0] == WME_OUI_TYPE))) {
++				CFGP2P_DBG(("Found WPA/WME oui. Do not add it\n"));
++				goto end;
++			}
++
++			parsed_info = &vndr_ies->ie_info[count++];
++
++			/* save vndr ie information */
++			parsed_info->ie_ptr = (char *)vndrie;
++			parsed_info->ie_len = (vndrie->len + TLV_HDR_LEN);
++			memcpy(&parsed_info->vndrie, vndrie, sizeof(vndr_ie_t));
++			vndr_ies->count = count;
++
++			WL_DBG(("\t ** OUI %02x %02x %02x, type 0x%02x \n",
++			parsed_info->vndrie.oui[0], parsed_info->vndrie.oui[1],
++			parsed_info->vndrie.oui[2], parsed_info->vndrie.data[0]));
++		}
++end:
++		ie = bcm_next_tlv(ie, &remained_len);
++	}
++	return err;
++}
++
++s32
++wl_cfg80211_clear_per_bss_ies(struct bcm_cfg80211 *cfg, s32 bssidx)
++{
++	s32 index;
++	struct net_info *netinfo;
++	s32 vndrie_flag[] = {VNDR_IE_BEACON_FLAG, VNDR_IE_PRBRSP_FLAG,
++		VNDR_IE_ASSOCRSP_FLAG, VNDR_IE_PRBREQ_FLAG, VNDR_IE_ASSOCREQ_FLAG};
++
++	netinfo = wl_get_netinfo_by_bssidx(cfg, bssidx);
++	if (!netinfo || !netinfo->wdev) {
++		WL_ERR(("netinfo or netinfo->wdev is NULL\n"));
++		return -1;
++	}
++
++	WL_DBG(("clear management vendor IEs for bssidx:%d \n", bssidx));
++	/* Clear the IEs set in the firmware so that host is in sync with firmware */
++	for (index = 0; index < ARRAYSIZE(vndrie_flag); index++) {
++		if (wl_cfg80211_set_mgmt_vndr_ies(cfg, wdev_to_cfgdev(netinfo->wdev),
++			bssidx, vndrie_flag[index], NULL, 0) < 0)
++			WL_ERR(("vndr_ies clear failed. Ignoring.. \n"));
++	}
++
++	return 0;
++}
++
++s32
++wl_cfg80211_clear_mgmt_vndr_ies(struct bcm_cfg80211 *cfg)
++{
++	struct net_info *iter, *next;
++
++	WL_DBG(("clear management vendor IEs \n"));
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++	for_each_ndev(cfg, iter, next) {
++		wl_cfg80211_clear_per_bss_ies(cfg, iter->bssidx);
++	}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++	return 0;
++}
++
++#define WL_VNDR_IE_MAXLEN 2048
++static s8 g_mgmt_ie_buf[WL_VNDR_IE_MAXLEN];
++int
++wl_cfg80211_set_mgmt_vndr_ies(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	s32 bssidx, s32 pktflag, const u8 *vndr_ie, u32 vndr_ie_len)
++{
++	struct net_device *ndev = NULL;
++	s32 ret = BCME_OK;
++	u8  *curr_ie_buf = NULL;
++	u8  *mgmt_ie_buf = NULL;
++	u32 mgmt_ie_buf_len = 0;
++	u32 *mgmt_ie_len = 0;
++	u32 del_add_ie_buf_len = 0;
++	u32 total_ie_buf_len = 0;
++	u32 parsed_ie_buf_len = 0;
++	struct parsed_vndr_ies old_vndr_ies;
++	struct parsed_vndr_ies new_vndr_ies;
++	s32 i;
++	u8 *ptr;
++	s32 remained_buf_len;
++	wl_bss_vndr_ies_t *ies = NULL;
++	struct net_info *netinfo;
++
++	WL_DBG(("Enter. pktflag:0x%x bssidx:%x vnd_ie_len:%d \n",
++		pktflag, bssidx, vndr_ie_len));
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	if (bssidx > WL_MAX_IFS) {
++		WL_ERR(("bssidx > supported concurrent Ifaces \n"));
++		return -EINVAL;
++	}
++
++	netinfo = wl_get_netinfo_by_bssidx(cfg, bssidx);
++	if (!netinfo) {
++		WL_ERR(("net_info ptr is NULL \n"));
++		return -EINVAL;
++	}
++
++	/* Clear the global buffer */
++	memset(g_mgmt_ie_buf, 0, sizeof(g_mgmt_ie_buf));
++	curr_ie_buf = g_mgmt_ie_buf;
++	ies = &netinfo->bss.ies;
++
++	switch (pktflag) {
++		case VNDR_IE_PRBRSP_FLAG :
++			mgmt_ie_buf = ies->probe_res_ie;
++			mgmt_ie_len = &ies->probe_res_ie_len;
++			mgmt_ie_buf_len = sizeof(ies->probe_res_ie);
++			break;
++		case VNDR_IE_ASSOCRSP_FLAG :
++			mgmt_ie_buf = ies->assoc_res_ie;
++			mgmt_ie_len = &ies->assoc_res_ie_len;
++			mgmt_ie_buf_len = sizeof(ies->assoc_res_ie);
++			break;
++		case VNDR_IE_BEACON_FLAG :
++			mgmt_ie_buf = ies->beacon_ie;
++			mgmt_ie_len = &ies->beacon_ie_len;
++			mgmt_ie_buf_len = sizeof(ies->beacon_ie);
++			break;
++		case VNDR_IE_PRBREQ_FLAG :
++			mgmt_ie_buf = ies->probe_req_ie;
++			mgmt_ie_len = &ies->probe_req_ie_len;
++			mgmt_ie_buf_len = sizeof(ies->probe_req_ie);
++			break;
++		case VNDR_IE_ASSOCREQ_FLAG :
++			mgmt_ie_buf = ies->assoc_req_ie;
++			mgmt_ie_len = &ies->assoc_req_ie_len;
++			mgmt_ie_buf_len = sizeof(ies->assoc_req_ie);
++			break;
++		default:
++			mgmt_ie_buf = NULL;
++			mgmt_ie_len = NULL;
++			WL_ERR(("not suitable packet type (%d)\n", pktflag));
++			return BCME_ERROR;
++	}
++
++	if (vndr_ie_len > mgmt_ie_buf_len) {
++		WL_ERR(("extra IE size too big\n"));
++		ret = -ENOMEM;
++	} else {
++		/* parse and save new vndr_ie in curr_ie_buff before comparing it */
++		if (vndr_ie && vndr_ie_len && curr_ie_buf) {
++			ptr = curr_ie_buf;
++/* must discard vndr_ie constness, attempt to change vndr_ie arg to non-const
++ * causes cascade of errors in other places, fix involves const casts there
++ */
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic push")
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"")
++#endif
++			if ((ret = wl_cfg80211_parse_vndr_ies((u8 *)vndr_ie,
++				vndr_ie_len, &new_vndr_ies)) < 0) {
++				WL_ERR(("parse vndr ie failed \n"));
++				goto exit;
++			}
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++_Pragma("GCC diagnostic pop")
++#endif
++			for (i = 0; i < new_vndr_ies.count; i++) {
++				struct parsed_vndr_ie_info *vndrie_info =
++					&new_vndr_ies.ie_info[i];
++
++				if ((parsed_ie_buf_len + vndrie_info->ie_len) > WL_VNDR_IE_MAXLEN) {
++					WL_ERR(("IE size is too big (%d > %d)\n",
++						parsed_ie_buf_len, WL_VNDR_IE_MAXLEN));
++					ret = -EINVAL;
++					goto exit;
++				}
++
++				memcpy(ptr + parsed_ie_buf_len, vndrie_info->ie_ptr,
++					vndrie_info->ie_len);
++				parsed_ie_buf_len += vndrie_info->ie_len;
++			}
++		}
++
++		if (mgmt_ie_buf != NULL) {
++			if (parsed_ie_buf_len && (parsed_ie_buf_len == *mgmt_ie_len) &&
++				(memcmp(mgmt_ie_buf, curr_ie_buf, parsed_ie_buf_len) == 0)) {
++				WL_INFORM(("Previous mgmt IE is equals to current IE"));
++				goto exit;
++			}
++
++			/* parse old vndr_ie */
++			if ((ret = wl_cfg80211_parse_vndr_ies(mgmt_ie_buf, *mgmt_ie_len,
++				&old_vndr_ies)) < 0) {
++				WL_ERR(("parse vndr ie failed \n"));
++				goto exit;
++			}
++			/* make a command to delete old ie */
++			for (i = 0; i < old_vndr_ies.count; i++) {
++				struct parsed_vndr_ie_info *vndrie_info =
++				&old_vndr_ies.ie_info[i];
++
++				WL_INFORM(("DELETED ID : %d, Len: %d , OUI:%02x:%02x:%02x\n",
++					vndrie_info->vndrie.id, vndrie_info->vndrie.len,
++					vndrie_info->vndrie.oui[0], vndrie_info->vndrie.oui[1],
++					vndrie_info->vndrie.oui[2]));
++
++				del_add_ie_buf_len = wl_cfgp2p_vndr_ie(cfg, curr_ie_buf,
++					pktflag, vndrie_info->vndrie.oui,
++					vndrie_info->vndrie.id,
++					vndrie_info->ie_ptr + VNDR_IE_FIXED_LEN,
++					vndrie_info->ie_len - VNDR_IE_FIXED_LEN,
++					"del");
++
++				curr_ie_buf += del_add_ie_buf_len;
++				total_ie_buf_len += del_add_ie_buf_len;
++			}
++		}
++
++		*mgmt_ie_len = 0;
++		/* Add if there is any extra IE */
++		if (mgmt_ie_buf && parsed_ie_buf_len) {
++			ptr = mgmt_ie_buf;
++
++			remained_buf_len = mgmt_ie_buf_len;
++
++			/* make a command to add new ie */
++			for (i = 0; i < new_vndr_ies.count; i++) {
++				struct parsed_vndr_ie_info *vndrie_info =
++					&new_vndr_ies.ie_info[i];
++
++				WL_INFORM(("ADDED ID : %d, Len: %d(%d), OUI:%02x:%02x:%02x\n",
++					vndrie_info->vndrie.id, vndrie_info->vndrie.len,
++					vndrie_info->ie_len - 2,
++					vndrie_info->vndrie.oui[0], vndrie_info->vndrie.oui[1],
++					vndrie_info->vndrie.oui[2]));
++
++				del_add_ie_buf_len = wl_cfgp2p_vndr_ie(cfg, curr_ie_buf,
++					pktflag, vndrie_info->vndrie.oui,
++					vndrie_info->vndrie.id,
++					vndrie_info->ie_ptr + VNDR_IE_FIXED_LEN,
++					vndrie_info->ie_len - VNDR_IE_FIXED_LEN,
++					"add");
++
++				/* verify remained buf size before copy data */
++				if (remained_buf_len >= vndrie_info->ie_len) {
++					remained_buf_len -= vndrie_info->ie_len;
++				} else {
++					WL_ERR(("no space in mgmt_ie_buf: pktflag = %d, "
++					"found vndr ies # = %d(cur %d), remained len %d, "
++					"cur mgmt_ie_len %d, new ie len = %d\n",
++					pktflag, new_vndr_ies.count, i, remained_buf_len,
++					*mgmt_ie_len, vndrie_info->ie_len));
++					break;
++				}
++
++				/* save the parsed IE in cfg struct */
++				memcpy(ptr + (*mgmt_ie_len), vndrie_info->ie_ptr,
++					vndrie_info->ie_len);
++				*mgmt_ie_len += vndrie_info->ie_len;
++				curr_ie_buf += del_add_ie_buf_len;
++				total_ie_buf_len += del_add_ie_buf_len;
++			}
++		}
++
++		if (total_ie_buf_len && cfg->ioctl_buf != NULL) {
++			ret  = wldev_iovar_setbuf_bsscfg(ndev, "vndr_ie", g_mgmt_ie_buf,
++				total_ie_buf_len, cfg->ioctl_buf, WLC_IOCTL_MAXLEN,
++				bssidx, &cfg->ioctl_buf_sync);
++			if (ret)
++				WL_ERR(("vndr ie set error : %d\n", ret));
++		}
++	}
++exit:
++
++return ret;
++}
++
++#ifdef WL_CFG80211_ACL
++static int
++wl_cfg80211_set_mac_acl(struct wiphy *wiphy, struct net_device *cfgdev,
++	const struct cfg80211_acl_data *acl)
++{
++	int i;
++	int ret = 0;
++	int macnum = 0;
++	int macmode = MACLIST_MODE_DISABLED;
++	struct maclist *list;
++
++	/* get the MAC filter mode */
++	if (acl && acl->acl_policy == NL80211_ACL_POLICY_DENY_UNLESS_LISTED) {
++		macmode = MACLIST_MODE_ALLOW;
++	} else if (acl && acl->acl_policy == NL80211_ACL_POLICY_ACCEPT_UNLESS_LISTED &&
++	acl->n_acl_entries) {
++		macmode = MACLIST_MODE_DENY;
++	}
++
++	/* if acl == NULL, macmode is still disabled.. */
++	if (macmode == MACLIST_MODE_DISABLED) {
++		if ((ret = wl_android_set_ap_mac_list(cfgdev, macmode, NULL)) != 0)
++			WL_ERR(("%s : Setting MAC list failed error=%d\n", __FUNCTION__, ret));
++
++		return ret;
++	}
++
++	macnum = acl->n_acl_entries;
++	if (macnum < 0 || macnum > MAX_NUM_MAC_FILT) {
++		WL_ERR(("%s : invalid number of MAC address entries %d\n",
++			__FUNCTION__, macnum));
++		return -1;
++	}
++
++	/* allocate memory for the MAC list */
++	list = (struct maclist*)kmalloc(sizeof(int) +
++		sizeof(struct ether_addr) * macnum, GFP_KERNEL);
++	if (!list) {
++		WL_ERR(("%s : failed to allocate memory\n", __FUNCTION__));
++		return -1;
++	}
++
++	/* prepare the MAC list */
++	list->count = htod32(macnum);
++	for (i = 0; i < macnum; i++) {
++		memcpy(&list->ea[i], &acl->mac_addrs[i], ETHER_ADDR_LEN);
++	}
++	/* set the list */
++	if ((ret = wl_android_set_ap_mac_list(cfgdev, macmode, list)) != 0)
++		WL_ERR(("%s : Setting MAC list failed error=%d\n", __FUNCTION__, ret));
++
++	kfree(list);
++
++	return ret;
++}
++#endif /* WL_CFG80211_ACL */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++int wl_chspec_chandef(chanspec_t chanspec,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	struct cfg80211_chan_def *chandef,
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 5, 0) && (LINUX_VERSION_CODE <= (3, 7, \
++	\
++	\
++	\
++	0)))
++	struct chan_info *chaninfo,
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) */
++struct wiphy *wiphy)
++
++{
++	uint16 freq = 0;
++	int chan_type = 0;
++	int channel = 0;
++
++	if (!chandef) {
++		return -1;
++	}
++	channel = CHSPEC_CHANNEL(chanspec);
++
++	switch (CHSPEC_BW(chanspec)) {
++		case WL_CHANSPEC_BW_20:
++			chan_type = NL80211_CHAN_HT20;
++			break;
++		case WL_CHANSPEC_BW_40:
++		{
++			if (CHSPEC_SB_UPPER(chanspec)) {
++				channel += CH_10MHZ_APART;
++			} else {
++				channel -= CH_10MHZ_APART;
++			}
++		}
++			chan_type = NL80211_CHAN_HT40PLUS;
++			break;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0))
++		case WL_CHANSPEC_BW_80:
++		case WL_CHANSPEC_BW_8080:
++		{
++			uint16 sb = CHSPEC_CTL_SB(chanspec);
++
++			if (sb == WL_CHANSPEC_CTL_SB_LL) {
++				channel -= (CH_10MHZ_APART + CH_20MHZ_APART);
++			} else if (sb == WL_CHANSPEC_CTL_SB_LU) {
++				channel -= CH_10MHZ_APART;
++			} else if (sb == WL_CHANSPEC_CTL_SB_UL) {
++				channel += CH_10MHZ_APART;
++			} else {
++				/* WL_CHANSPEC_CTL_SB_UU */
++				channel += (CH_10MHZ_APART + CH_20MHZ_APART);
++			}
++
++			if (sb == WL_CHANSPEC_CTL_SB_LL || sb == WL_CHANSPEC_CTL_SB_LU)
++				chan_type = NL80211_CHAN_HT40MINUS;
++			else if (sb == WL_CHANSPEC_CTL_SB_UL || sb == WL_CHANSPEC_CTL_SB_UU)
++				chan_type = NL80211_CHAN_HT40PLUS;
++		}
++			break;
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0)) */
++		default:
++			chan_type = NL80211_CHAN_HT20;
++			break;
++
++	}
++
++	if (CHSPEC_IS5G(chanspec))
++		freq = ieee80211_channel_to_frequency(channel, NL80211_BAND_5GHZ);
++	else
++		freq = ieee80211_channel_to_frequency(channel, NL80211_BAND_2GHZ);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0))
++	cfg80211_chandef_create(chandef, ieee80211_get_channel(wiphy, freq), chan_type);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 5, 0) && (LINUX_VERSION_CODE <= (3, 7, \
++	\
++	\
++	\
++	0)))
++	chaninfo->freq = freq;
++	chaninfo->chan_type = chan_type;
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0)) */
++	return 0;
++}
++
++void
++wl_cfg80211_ch_switch_notify(struct net_device *dev, uint16 chanspec, struct wiphy *wiphy)
++{
++	u32 freq;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0))
++	struct cfg80211_chan_def chandef;
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 5, 0) && (LINUX_VERSION_CODE <= (3, 7, \
++	\
++	\
++	\
++	0)))
++	struct chan_info chaninfo;
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0)) */
++
++	if (!wiphy) {
++		WL_ERR(("wiphy is null\n"));
++		return;
++	}
++	/* Channel switch support is only for AP/GO/ADHOC/MESH */
++	if (dev->ieee80211_ptr->iftype == NL80211_IFTYPE_STATION ||
++		dev->ieee80211_ptr->iftype == NL80211_IFTYPE_P2P_CLIENT) {
++		WL_ERR(("No channel switch notify support for STA/GC\n"));
++		return;
++	}
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0))
++	if (wl_chspec_chandef(chanspec, &chandef, wiphy)) {
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 5, 0) && (LINUX_VERSION_CODE <= (3, 7, \
++	\
++	\
++	\
++	0)))
++	if (wl_chspec_chandef(chanspec, &chaninfo, wiphy)) {
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0)) */
++
++		WL_ERR(("chspec_chandef failed\n"));
++		return;
++	}
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0))
++	freq = chandef.chan ? chandef.chan->center_freq : chandef.center_freq1;
++	cfg80211_ch_switch_notify(dev, &chandef);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 5, 0) && (LINUX_VERSION_CODE <= (3, 7, \
++	\
++	\
++	\
++	0)))
++	freq = chan_info.freq;
++	cfg80211_ch_switch_notify(dev, freq, chan_info.chan_type);
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION (3, 8, 0)) */
++
++	WL_ERR(("Channel switch notification for freq: %d chanspec: 0x%x\n", freq, chanspec));
++	return;
++}
++#endif /* LINUX_VERSION_CODE >= (3, 5, 0) */
++
++#ifdef WL11ULB
++s32
++wl_cfg80211_set_ulb_mode(struct net_device *dev, int mode)
++{
++	int ret;
++	int cur_mode;
++
++	ret = wldev_iovar_getint(dev, "ulb_mode", &cur_mode);
++	if (unlikely(ret)) {
++		WL_ERR(("[ULB] ulb_mode get failed. ret:%d \n", ret));
++		return ret;
++	}
++
++	if (cur_mode == mode) {
++		/* If request mode is same as that of the current mode, then
++		 * do nothing (Avoid unnecessary wl down and up).
++		 */
++		WL_INFORM(("[ULB] No change in ulb_mode. Do nothing.\n"));
++		return 0;
++	}
++
++	/* setting of ulb_mode requires wl to be down */
++	ret = wldev_ioctl(dev, WLC_DOWN, NULL, 0, true);
++	if (unlikely(ret)) {
++		WL_ERR(("[ULB] WLC_DOWN command failed:[%d]\n", ret));
++		return ret;
++	}
++
++	if (mode >= MAX_SUPP_ULB_MODES) {
++		WL_ERR(("[ULB] unsupported ulb_mode :[%d]\n", mode));
++		return -EINVAL;
++	}
++
++	ret = wldev_iovar_setint(dev, "ulb_mode", mode);
++	if (unlikely(ret)) {
++		WL_ERR(("[ULB] ulb_mode set failed. ret:%d \n", ret));
++		return ret;
++	}
++
++	ret = wldev_ioctl(dev, WLC_UP, NULL, 0, true);
++	if (unlikely(ret)) {
++		WL_ERR(("[ULB] WLC_DOWN command failed:[%d]\n", ret));
++		return ret;
++	}
++
++	WL_DBG(("[ULB] ulb_mode set to %d successfully \n", mode));
++
++	return ret;
++}
++
++static s32
++wl_cfg80211_ulbbw_to_ulbchspec(u32 bw)
++{
++	if (bw == ULB_BW_DISABLED) {
++		return WL_CHANSPEC_BW_20;
++	} else if (bw == ULB_BW_10MHZ) {
++		return WL_CHANSPEC_BW_10;
++	} else if (bw == ULB_BW_5MHZ) {
++		return WL_CHANSPEC_BW_5;
++	} else if (bw == ULB_BW_2P5MHZ) {
++		return WL_CHANSPEC_BW_2P5;
++	} else {
++		WL_ERR(("[ULB] unsupported value for ulb_bw \n"));
++		return -EINVAL;
++	}
++}
++
++static chanspec_t
++wl_cfg80211_ulb_get_min_bw_chspec(struct wireless_dev *wdev, s32 bssidx)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	struct net_info *_netinfo;
++
++	/*
++	 *  Return the chspec value corresponding to the
++	 *  BW setting for a particular interface
++	 */
++	if (wdev) {
++		/* if wdev is provided, use it */
++		_netinfo = wl_get_netinfo_by_wdev(cfg, wdev);
++	} else if (bssidx >= 0) {
++		/* if wdev is not provided, use it */
++		_netinfo = wl_get_netinfo_by_bssidx(cfg, bssidx);
++	} else {
++		WL_ERR(("[ULB] wdev/bssidx not provided\n"));
++		return INVCHANSPEC;
++	}
++
++	if (unlikely(!_netinfo)) {
++		WL_ERR(("[ULB] net_info is null \n"));
++		return INVCHANSPEC;
++	}
++
++	if (_netinfo->ulb_bw) {
++		WL_DBG(("[ULB] wdev_ptr:%p ulb_bw:0x%x \n", _netinfo->wdev, _netinfo->ulb_bw));
++		return wl_cfg80211_ulbbw_to_ulbchspec(_netinfo->ulb_bw);
++	} else {
++		return WL_CHANSPEC_BW_20;
++	}
++}
++
++static s32
++wl_cfg80211_get_ulb_bw(struct wireless_dev *wdev)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	struct net_info *_netinfo = wl_get_netinfo_by_wdev(cfg, wdev);
++
++	/*
++	 *  Return the ulb_bw setting for a
++	 *  particular interface
++	 */
++	if (unlikely(!_netinfo)) {
++		WL_ERR(("[ULB] net_info is null \n"));
++		return -1;
++	}
++
++	return _netinfo->ulb_bw;
++}
++
++s32
++wl_cfg80211_set_ulb_bw(struct net_device *dev,
++	u32 ulb_bw,  char *ifname)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	int ret;
++	int mode;
++	struct net_info *_netinfo = NULL, *iter, *next;
++	u32 bssidx;
++	enum nl80211_iftype iftype;
++
++	if (!ifname)
++		return -EINVAL;
++
++	WL_DBG(("[ULB] Enter. bw_type:%d \n", ulb_bw));
++
++	ret = wldev_iovar_getint(dev, "ulb_mode", &mode);
++	if (unlikely(ret)) {
++		WL_ERR(("[ULB] ulb_mode not supported \n"));
++		return ret;
++	}
++
++	if (mode != ULB_MODE_STD_ALONE_MODE) {
++		WL_ERR(("[ULB] ulb bw modification allowed only in stand-alone mode\n"));
++		return -EINVAL;
++	}
++
++	if (ulb_bw >= MAX_SUPP_ULB_BW) {
++		WL_ERR(("[ULB] unsupported value (%d) for ulb_bw \n", ulb_bw));
++		return -EINVAL;
++	}
++
++#ifdef WL_CFG80211_P2P_DEV_IF
++	if (strcmp(ifname, "p2p-dev-wlan0") == 0) {
++		iftype = NL80211_IFTYPE_P2P_DEVICE;
++		/* Use wdev corresponding to the dedicated p2p discovery interface */
++		if (likely(cfg->p2p_wdev)) {
++			_netinfo = wl_get_netinfo_by_wdev(cfg, cfg->p2p_wdev);
++		} else {
++			return -ENODEV;
++		}
++	}
++#endif /* WL_CFG80211_P2P_DEV_IF */
++	if (!_netinfo) {
++		for_each_ndev(cfg, iter, next) {
++			if (iter->ndev) {
++				if (strncmp(iter->ndev->name, ifname, strlen(ifname)) == 0) {
++					_netinfo = wl_get_netinfo_by_netdev(cfg, iter->ndev);
++					iftype = NL80211_IFTYPE_STATION;
++				}
++			}
++		}
++	}
++
++	if (!_netinfo)
++		return -ENODEV;
++	bssidx = _netinfo->bssidx;
++	_netinfo->ulb_bw = ulb_bw;
++
++
++	WL_DBG(("[ULB] Applying ulb_bw:%d for bssidx:%d \n", ulb_bw, bssidx));
++	ret = wldev_iovar_setbuf_bsscfg(dev, "ulb_bw", (void *)&ulb_bw, 4,
++		cfg->ioctl_buf, WLC_IOCTL_SMLEN, bssidx,
++		&cfg->ioctl_buf_sync);
++	if (unlikely(ret)) {
++		WL_ERR(("[ULB] ulb_bw set failed. ret:%d \n", ret));
++		return ret;
++	}
++
++	return ret;
++}
++#endif /* WL11ULB */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++static s32
++wl_csa_complete_ind(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++const wl_event_msg_t *e, void *data)
++{
++	int error = 0;
++	int chsp = 0;
++	struct net_device *ndev = NULL;
++	struct wiphy *wiphy = NULL;
++	chanspec_t chanspec;
++
++	WL_DBG(("Enter\n"));
++	if (unlikely(e->status)) {
++		WL_ERR(("status:0x%x \n", e->status));
++		return -1;
++	}
++
++	if (likely(cfgdev)) {
++		ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++		wiphy = bcmcfg_to_wiphy(cfg);
++		error = wldev_iovar_getint(ndev, "chanspec", &chsp);
++		if (unlikely(error)) {
++			WL_ERR(("Get chanspec error: %d \n", error));
++			return -1;
++		}
++		chanspec = wl_chspec_driver_to_host(chsp);
++		wl_cfg80211_ch_switch_notify(ndev, chanspec, wiphy);
++	} else {
++		WL_ERR(("cfgdev is null\n"));
++		return -1;
++	}
++
++	return 0;
++}
++#else
++static s32
++wl_csa_complete_ind(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++const wl_event_msg_t *e, void *data)
++{
++	WL_ERR(("%s:Not sup for kernel < 3.5\n", __FUNCTION__));
++	return 0;
++}
++#endif /* LINUX_VERSION_CODE >= (3, 5, 0) */
++
++
++#ifdef WL_NAN
++int
++wl_cfg80211_nan_cmd_handler(struct net_device *ndev, char *cmd, int cmd_len)
++{
++	return wl_cfgnan_cmd_handler(ndev, g_bcm_cfg, cmd, cmd_len);
++}
++#endif /* WL_NAN */
++
++void wl_cfg80211_clear_security(struct bcm_cfg80211 *cfg)
++{
++	struct net_device *dev = bcmcfg_to_prmry_ndev(cfg);
++	int err;
++
++	/* Clear the security settings on the primary Interface */
++	err = wldev_iovar_setint(dev, "wsec", 0);
++	if (unlikely(err)) {
++		WL_ERR(("wsec clear failed \n"));
++	}
++	err = wldev_iovar_setint(dev, "auth", 0);
++	if (unlikely(err)) {
++		WL_ERR(("auth clear failed \n"));
++	}
++	err = wldev_iovar_setint(dev, "wpa_auth", WPA_AUTH_DISABLED);
++	if (unlikely(err)) {
++		WL_ERR(("wpa_auth clear failed \n"));
++	}
++}
++
++#ifdef WL_CFG80211_P2P_DEV_IF
++void wl_cfg80211_del_p2p_wdev(void)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	struct wireless_dev *wdev = NULL;
++
++	WL_DBG(("Enter \n"));
++	if (!cfg) {
++		WL_ERR(("Invalid Ptr\n"));
++		return;
++	} else {
++		wdev = cfg->p2p_wdev;
++	}
++
++	if (wdev && cfg->down_disc_if) {
++		wl_cfgp2p_del_p2p_disc_if(wdev, cfg);
++		cfg->down_disc_if = FALSE;
++	}
++}
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++#if defined(WL_SUPPORT_AUTO_CHANNEL)
++int
++wl_cfg80211_set_spect(struct net_device *dev, int spect)
++{
++	struct bcm_cfg80211 *cfg = g_bcm_cfg;
++	int down = 1;
++	int up = 1;
++	int err = BCME_OK;
++
++	if (!wl_get_drv_status_all(cfg, CONNECTED)) {
++		err = wldev_ioctl(dev, WLC_DOWN, &down, sizeof(down), true);
++		if (err) {
++			WL_ERR(("%s: WLC_DOWN failed: code: %d\n", __func__, err));
++			return err;
++		}
++
++		err = wldev_ioctl(dev, WLC_SET_SPECT_MANAGMENT, &spect, sizeof(spect), true);
++		if (err) {
++			WL_ERR(("%s: error setting spect: code: %d\n", __func__, err));
++			return err;
++		}
++
++		err = wldev_ioctl(dev, WLC_UP, &up, sizeof(up), true);
++		if (err) {
++			WL_ERR(("%s: WLC_UP failed: code: %d\n", __func__, err));
++			return err;
++		}
++	}
++	return err;
++}
++
++int
++wl_cfg80211_get_sta_channel(struct net_device *dev)
++{
++	if (wl_get_drv_status(g_bcm_cfg, CONNECTED, dev)) {
++		return g_bcm_cfg->channel;
++	}
++	return BCME_OK;
++}
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
++static s32
++wl_cfg80211_set_rekey_data(struct wiphy *wiphy, struct net_device *dev,
++		struct cfg80211_gtk_rekey_data *data)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	s32 err = 0;
++	gtk_keyinfo_t keyinfo;
++
++	WL_DBG(("Enter\n"));
++	if (data == NULL || cfg->p2p_net == dev) {
++		WL_ERR(("data is NULL or wrong net device\n"));
++		return -EINVAL;
++	}
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)
++	prhex("kck", (uchar *) (data->kck), RSN_KCK_LENGTH);
++	prhex("kek", (uchar *) (data->kek), RSN_KEK_LENGTH);
++	prhex("replay_ctr", (uchar *) (data->replay_ctr), RSN_REPLAY_LEN);
++#else
++	prhex("kck", data->kck, RSN_KCK_LENGTH);
++	prhex("kek", data->kek, RSN_KEK_LENGTH);
++	prhex("replay_ctr", data->replay_ctr, RSN_REPLAY_LEN);
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) */
++	bcopy(data->kck, keyinfo.KCK, RSN_KCK_LENGTH);
++	bcopy(data->kek, keyinfo.KEK, RSN_KEK_LENGTH);
++	bcopy(data->replay_ctr, keyinfo.ReplayCounter, RSN_REPLAY_LEN);
++
++	if ((err = wldev_iovar_setbuf(dev, "gtk_key_info", &keyinfo, sizeof(keyinfo),
++		cfg->ioctl_buf, WLC_IOCTL_SMLEN, &cfg->ioctl_buf_sync)) < 0) {
++		WL_ERR(("seting gtk_key_info failed code=%d\n", err));
++		return err;
++	}
++	WL_DBG(("Exit\n"));
++	return err;
++}
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0) */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfg80211.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfg80211.h
+new file mode 100644
+index 000000000..93d2f3a84
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfg80211.h
+@@ -0,0 +1,1380 @@
++/*
++ * Linux cfg80211 driver
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfg80211.h 598406 2015-11-09 13:44:22Z $
++ */
++
++/**
++ * Older Linux versions support the 'iw' interface, more recent ones the 'cfg80211' interface.
++ */
++
++#ifndef _wl_cfg80211_h_
++#define _wl_cfg80211_h_
++
++#include <linux/wireless.h>
++#include <typedefs.h>
++#include <proto/ethernet.h>
++#include <wlioctl.h>
++#include <linux/wireless.h>
++#include <net/cfg80211.h>
++#include <linux/rfkill.h>
++
++#include <wl_cfgp2p.h>
++
++struct wl_conf;
++struct wl_iface;
++struct bcm_cfg80211;
++struct wl_security;
++struct wl_ibss;
++
++
++#define htod32(i) (i)
++#define htod16(i) (i)
++#define dtoh64(i) (i)
++#define dtoh32(i) (i)
++#define dtoh16(i) (i)
++#define htodchanspec(i) (i)
++#define dtohchanspec(i) (i)
++
++#define WL_DBG_NONE	0
++#define WL_DBG_P2P_ACTION (1 << 5)
++#define WL_DBG_TRACE	(1 << 4)
++#define WL_DBG_SCAN 	(1 << 3)
++#define WL_DBG_DBG 	(1 << 2)
++#define WL_DBG_INFO	(1 << 1)
++#define WL_DBG_ERR	(1 << 0)
++
++/* 0 invalidates all debug messages.  default is 1 */
++#define WL_DBG_LEVEL 0xFF
++
++#define CFG80211_ERROR_TEXT		"CFG80211-ERROR) "
++
++#if defined(DHD_DEBUG)
++#define	WL_ERR(args)									\
++do {										\
++	if (wl_dbg_level & WL_DBG_ERR) {				\
++			printk(KERN_INFO CFG80211_ERROR_TEXT "%s : ", __func__);	\
++			printk args;						\
++		}								\
++} while (0)
++#else /* defined(DHD_DEBUG) */
++#define	WL_ERR(args)									\
++do {										\
++	if ((wl_dbg_level & WL_DBG_ERR) && net_ratelimit()) {				\
++			printk(KERN_INFO CFG80211_ERROR_TEXT "%s : ", __func__);	\
++			printk args;						\
++		}								\
++} while (0)
++#endif /* defined(DHD_DEBUG) */
++
++#ifdef WL_INFORM
++#undef WL_INFORM
++#endif
++
++#define	WL_INFORM(args)									\
++do {										\
++	if (wl_dbg_level & WL_DBG_INFO) {				\
++			printk(KERN_INFO "CFG80211-INFO) %s : ", __func__);	\
++			printk args;						\
++		}								\
++} while (0)
++
++
++#ifdef WL_SCAN
++#undef WL_SCAN
++#endif
++#define	WL_SCAN(args)								\
++do {									\
++	if (wl_dbg_level & WL_DBG_SCAN) {			\
++		printk(KERN_INFO "CFG80211-SCAN) %s :", __func__);	\
++		printk args;							\
++	}									\
++} while (0)
++#ifdef WL_TRACE
++#undef WL_TRACE
++#endif
++#define	WL_TRACE(args)								\
++do {									\
++	if (wl_dbg_level & WL_DBG_TRACE) {			\
++		printk(KERN_INFO "CFG80211-TRACE) %s :", __func__);	\
++		printk args;							\
++	}									\
++} while (0)
++#ifdef WL_TRACE_HW4
++#undef WL_TRACE_HW4
++#endif
++#define	WL_TRACE_HW4			WL_TRACE
++#if (WL_DBG_LEVEL > 0)
++#define	WL_DBG(args)								\
++do {									\
++	if (wl_dbg_level & WL_DBG_DBG) {			\
++		printk(KERN_DEBUG "CFG80211-DEBUG) %s :", __func__);	\
++		printk args;							\
++	}									\
++} while (0)
++#else				/* !(WL_DBG_LEVEL > 0) */
++#define	WL_DBG(args)
++#endif				/* (WL_DBG_LEVEL > 0) */
++#define WL_PNO(x)
++#define WL_SD(x)
++
++
++#define WL_SCAN_RETRY_MAX	3
++#define WL_NUM_PMKIDS_MAX	MAXPMKID
++#define WL_SCAN_BUF_MAX 	(1024 * 8)
++#define WL_TLV_INFO_MAX 	1500
++#define WL_SCAN_IE_LEN_MAX      2048
++#define WL_BSS_INFO_MAX		2048
++#define WL_ASSOC_INFO_MAX	512
++#define WL_IOCTL_LEN_MAX	2048
++#define WL_EXTRA_BUF_MAX	2048
++#define WL_SCAN_ERSULTS_LAST 	(WL_SCAN_RESULTS_NO_MEM+1)
++#define WL_AP_MAX			256
++#define WL_FILE_NAME_MAX	256
++#define WL_DWELL_TIME		200
++#define WL_MED_DWELL_TIME	400
++#define WL_MIN_DWELL_TIME	100
++#define WL_LONG_DWELL_TIME	1000
++#define IFACE_MAX_CNT	4
++#define WL_SCAN_CONNECT_DWELL_TIME_MS		200
++#define WL_SCAN_JOIN_PROBE_INTERVAL_MS		20
++#define WL_SCAN_JOIN_ACTIVE_DWELL_TIME_MS	320
++#define WL_SCAN_JOIN_PASSIVE_DWELL_TIME_MS	400
++#define WL_AF_TX_MAX_RETRY	5
++
++#define WL_AF_SEARCH_TIME_MAX		450
++#define WL_AF_TX_EXTRA_TIME_MAX		200
++
++#define WL_SCAN_TIMER_INTERVAL_MS	10000 /* Scan timeout */
++#define WL_CHANNEL_SYNC_RETRY 	5
++#define WL_INVALID 		-1
++
++#ifdef DHD_LOSSLESS_ROAMING
++#define WL_ROAM_TIMEOUT_MS	1000 /* Roam timeout */
++#endif
++/* Bring down SCB Timeout to 20secs from 60secs default */
++#ifndef WL_SCB_TIMEOUT
++#define WL_SCB_TIMEOUT 20
++#endif
++
++/* SCAN_SUPPRESS timer values in ms */
++#define WL_SCAN_SUPPRESS_TIMEOUT 31000 /* default Framwork DHCP timeout is 30 sec */
++#define WL_SCAN_SUPPRESS_RETRY 3000
++
++#define WL_PM_ENABLE_TIMEOUT 10000
++
++/* cfg80211 wowlan definitions */
++#define WL_WOWLAN_MAX_PATTERNS			8
++#define WL_WOWLAN_MIN_PATTERN_LEN		1
++#define WL_WOWLAN_MAX_PATTERN_LEN		255
++#define WL_WOWLAN_PKT_FILTER_ID_FIRST	201
++#define WL_WOWLAN_PKT_FILTER_ID_LAST	(WL_WOWLAN_PKT_FILTER_ID_FIRST + \
++									WL_WOWLAN_MAX_PATTERNS - 1)
++
++
++/* driver status */
++enum wl_status {
++	WL_STATUS_READY = 0,
++	WL_STATUS_SCANNING,
++	WL_STATUS_SCAN_ABORTING,
++	WL_STATUS_CONNECTING,
++	WL_STATUS_CONNECTED,
++	WL_STATUS_DISCONNECTING,
++	WL_STATUS_AP_CREATING,
++	WL_STATUS_AP_CREATED,
++	/* whole sending action frame procedure:
++	 * includes a) 'finding common channel' for public action request frame
++	 * and b) 'sending af via 'actframe' iovar'
++	 */
++	WL_STATUS_SENDING_ACT_FRM,
++	/* find a peer to go to a common channel before sending public action req frame */
++	WL_STATUS_FINDING_COMMON_CHANNEL,
++	/* waiting for next af to sync time of supplicant.
++	 * it includes SENDING_ACT_FRM and WAITING_NEXT_ACT_FRM_LISTEN
++	 */
++	WL_STATUS_WAITING_NEXT_ACT_FRM,
++#ifdef WL_CFG80211_SYNC_GON
++	/* go to listen state to wait for next af after SENDING_ACT_FRM */
++	WL_STATUS_WAITING_NEXT_ACT_FRM_LISTEN,
++#endif /* WL_CFG80211_SYNC_GON */
++	/* it will be set when upper layer requests listen and succeed in setting listen mode.
++	 * if set, other scan request can abort current listen state
++	 */
++	WL_STATUS_REMAINING_ON_CHANNEL,
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++	/* it's fake listen state to keep current scan state.
++	 * it will be set when upper layer requests listen but scan is running. then just run
++	 * a expire timer without actual listen state.
++	 * if set, other scan request does not need to abort scan.
++	 */
++	WL_STATUS_FAKE_REMAINING_ON_CHANNEL
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++};
++
++/* wi-fi mode */
++enum wl_mode {
++	WL_MODE_BSS,
++	WL_MODE_IBSS,
++	WL_MODE_AP
++};
++
++/* driver profile list */
++enum wl_prof_list {
++	WL_PROF_MODE,
++	WL_PROF_SSID,
++	WL_PROF_SEC,
++	WL_PROF_IBSS,
++	WL_PROF_BAND,
++	WL_PROF_CHAN,
++	WL_PROF_BSSID,
++	WL_PROF_ACT,
++	WL_PROF_BEACONINT,
++	WL_PROF_DTIMPERIOD
++};
++
++/* donlge escan state */
++enum wl_escan_state {
++    WL_ESCAN_STATE_IDLE,
++    WL_ESCAN_STATE_SCANING
++};
++/* fw downloading status */
++enum wl_fw_status {
++	WL_FW_LOADING_DONE,
++	WL_NVRAM_LOADING_DONE
++};
++
++enum wl_management_type {
++	WL_BEACON = 0x1,
++	WL_PROBE_RESP = 0x2,
++	WL_ASSOC_RESP = 0x4
++};
++
++enum wl_handler_del_type {
++	WL_HANDLER_NOTUSE,
++	WL_HANDLER_DEL,
++	WL_HANDLER_MAINTAIN,
++	WL_HANDLER_PEND
++};
++
++/* beacon / probe_response */
++struct beacon_proberesp {
++	__le64 timestamp;
++	__le16 beacon_int;
++	__le16 capab_info;
++	u8 variable[0];
++} __attribute__ ((packed));
++
++/* driver configuration */
++struct wl_conf {
++	u32 frag_threshold;
++	u32 rts_threshold;
++	u32 retry_short;
++	u32 retry_long;
++	s32 tx_power;
++	struct ieee80211_channel channel;
++};
++
++typedef s32(*EVENT_HANDLER) (struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++                            const wl_event_msg_t *e, void *data);
++
++/* bss inform structure for cfg80211 interface */
++struct wl_cfg80211_bss_info {
++	u16 band;
++	u16 channel;
++	s16 rssi;
++	u16 frame_len;
++	u8 frame_buf[1];
++};
++
++/* basic structure of scan request */
++struct wl_scan_req {
++	struct wlc_ssid ssid;
++};
++
++/* basic structure of information element */
++struct wl_ie {
++	u16 offset;
++	u8 buf[WL_TLV_INFO_MAX];
++};
++
++/* event queue for cfg80211 main event */
++struct wl_event_q {
++	struct list_head eq_list;
++	u32 etype;
++	wl_event_msg_t emsg;
++	s8 edata[1];
++};
++
++/* security information with currently associated ap */
++struct wl_security {
++	u32 wpa_versions;
++	u32 auth_type;
++	u32 cipher_pairwise;
++	u32 cipher_group;
++	u32 wpa_auth;
++	u32 auth_assoc_res_status;
++};
++
++/* ibss information for currently joined ibss network */
++struct wl_ibss {
++	u8 beacon_interval;	/* in millisecond */
++	u8 atim;		/* in millisecond */
++	s8 join_only;
++	u8 band;
++	u8 channel;
++};
++
++typedef struct wl_bss_vndr_ies {
++	u8  probe_req_ie[VNDR_IES_BUF_LEN];
++	u8  probe_res_ie[VNDR_IES_MAX_BUF_LEN];
++	u8  assoc_req_ie[VNDR_IES_BUF_LEN];
++	u8  assoc_res_ie[VNDR_IES_BUF_LEN];
++	u8  beacon_ie[VNDR_IES_MAX_BUF_LEN];
++	u32 probe_req_ie_len;
++	u32 probe_res_ie_len;
++	u32 assoc_req_ie_len;
++	u32 assoc_res_ie_len;
++	u32 beacon_ie_len;
++} wl_bss_vndr_ies_t;
++
++typedef struct wl_cfgbss {
++	u8 *wpa_ie;
++	u8 *rsn_ie;
++	u8 *wps_ie;
++	bool security_mode;
++    struct wl_bss_vndr_ies ies;	/* Common for STA, P2P GC, GO, AP, P2P Disc Interface */
++} wl_cfgbss_t;
++
++/* cfg driver profile */
++struct wl_profile {
++	u32 mode;
++	s32 band;
++	u32 channel;
++	struct wlc_ssid ssid;
++	struct wl_security sec;
++	struct wl_ibss ibss;
++	u8 bssid[ETHER_ADDR_LEN];
++	u16 beacon_interval;
++	u8 dtim_period;
++	bool active;
++};
++
++struct net_info {
++	struct net_device *ndev;
++	struct wireless_dev *wdev;
++	struct wl_profile profile;
++	s32 mode;
++	s32 roam_off;
++	unsigned long sme_state;
++	bool pm_restore;
++	bool pm_block;
++	s32 pm;
++	s32 bssidx;
++	wl_cfgbss_t bss;
++	u32 ulb_bw;
++	struct list_head list; /* list of all net_info structure */
++};
++
++/* association inform */
++#define MAX_REQ_LINE 1024
++struct wl_connect_info {
++	u8 req_ie[MAX_REQ_LINE];
++	s32 req_ie_len;
++	u8 resp_ie[MAX_REQ_LINE];
++	s32 resp_ie_len;
++};
++
++/* firmware /nvram downloading controller */
++struct wl_fw_ctrl {
++	const struct firmware *fw_entry;
++	unsigned long status;
++	u32 ptr;
++	s8 fw_name[WL_FILE_NAME_MAX];
++	s8 nvram_name[WL_FILE_NAME_MAX];
++};
++
++/* assoc ie length */
++struct wl_assoc_ielen {
++	u32 req_len;
++	u32 resp_len;
++};
++
++/* wpa2 pmk list */
++struct wl_pmk_list {
++	pmkid_list_t pmkids;
++	pmkid_t foo[MAXPMKID - 1];
++};
++
++#ifdef DHD_MAX_IFS
++#define WL_MAX_IFS DHD_MAX_IFS
++#else
++#define WL_MAX_IFS 16
++#endif
++
++#define ESCAN_BUF_SIZE (64 * 1024)
++
++struct escan_info {
++	u32 escan_state;
++#if defined(STATIC_WL_PRIV_STRUCT)
++#ifndef CONFIG_DHD_USE_STATIC_BUF
++#error STATIC_WL_PRIV_STRUCT should be used with CONFIG_DHD_USE_STATIC_BUF
++#endif /* CONFIG_DHD_USE_STATIC_BUF */
++	u8 *escan_buf;
++#else
++	u8 escan_buf[ESCAN_BUF_SIZE];
++#endif /* STATIC_WL_PRIV_STRUCT */
++	struct wiphy *wiphy;
++	struct net_device *ndev;
++};
++
++#ifdef ESCAN_BUF_OVERFLOW_MGMT
++#define BUF_OVERFLOW_MGMT_COUNT 3
++typedef struct {
++	int RSSI;
++	int length;
++	struct ether_addr BSSID;
++} removal_element_t;
++#endif /* ESCAN_BUF_OVERFLOW_MGMT */
++
++struct afx_hdl {
++	wl_af_params_t *pending_tx_act_frm;
++	struct ether_addr	tx_dst_addr;
++	struct net_device *dev;
++	struct work_struct work;
++	s32 bssidx;
++	u32 retry;
++	s32 peer_chan;
++	s32 peer_listen_chan; /* search channel: configured by upper layer */
++	s32 my_listen_chan;	/* listen chanel: extract it from prb req or gon req */
++	bool is_listen;
++	bool ack_recv;
++	bool is_active;
++};
++
++struct parsed_ies {
++	wpa_ie_fixed_t *wps_ie;
++	u32 wps_ie_len;
++	wpa_ie_fixed_t *wpa_ie;
++	u32 wpa_ie_len;
++	bcm_tlv_t *wpa2_ie;
++	u32 wpa2_ie_len;
++};
++
++
++#ifdef WL11U
++/* Max length of Interworking element */
++#define IW_IES_MAX_BUF_LEN 		9
++#endif
++#ifdef WLFBT
++#define FBT_KEYLEN		32
++#endif
++#define MAX_EVENT_BUF_NUM 16
++typedef struct wl_eventmsg_buf {
++    u16 num;
++    struct {
++		u16 type;
++		bool set;
++	} event [MAX_EVENT_BUF_NUM];
++} wl_eventmsg_buf_t;
++
++typedef struct wl_if_event_info {
++	bool valid;
++	int ifidx;
++	int bssidx;
++	uint8 mac[ETHER_ADDR_LEN];
++	char name[IFNAMSIZ+1];
++} wl_if_event_info;
++
++/* private data of cfg80211 interface */
++struct bcm_cfg80211 {
++	struct wireless_dev *wdev;	/* representing cfg cfg80211 device */
++
++	struct wireless_dev *p2p_wdev;	/* representing cfg cfg80211 device for P2P */
++	struct net_device *p2p_net;    /* reference to p2p0 interface */
++
++	struct wl_conf *conf;
++	struct cfg80211_scan_request *scan_request;	/* scan request object */
++	EVENT_HANDLER evt_handler[WLC_E_LAST];
++	struct list_head eq_list;	/* used for event queue */
++	struct list_head net_list;     /* used for struct net_info */
++	spinlock_t net_list_sync;	/* to protect scan status (and others if needed) */
++	spinlock_t eq_lock;	/* for event queue synchronization */
++	spinlock_t cfgdrv_lock;	/* to protect scan status (and others if needed) */
++	struct completion act_frm_scan;
++	struct completion iface_disable;
++	struct completion wait_next_af;
++	struct mutex usr_sync;	/* maily for up/down synchronization */
++	struct mutex scan_complete;	/* serialize scan_complete call */
++	struct wl_scan_results *bss_list;
++	struct wl_scan_results *scan_results;
++
++	/* scan request object for internal purpose */
++	struct wl_scan_req *scan_req_int;
++	/* information element object for internal purpose */
++#if defined(STATIC_WL_PRIV_STRUCT)
++	struct wl_ie *ie;
++#else
++	struct wl_ie ie;
++#endif
++
++	/* association information container */
++#if defined(STATIC_WL_PRIV_STRUCT)
++	struct wl_connect_info *conn_info;
++#else
++	struct wl_connect_info conn_info;
++#endif
++#ifdef DEBUGFS_CFG80211
++	struct dentry		*debugfs;
++#endif /* DEBUGFS_CFG80211 */
++	struct wl_pmk_list *pmk_list;	/* wpa2 pmk list */
++	tsk_ctl_t event_tsk;  		/* task of main event handler thread */
++	void *pub;
++	u32 iface_cnt;
++	u32 channel;		/* current channel */
++	u32 af_sent_channel;	/* channel action frame is sent */
++	/* next af subtype to cancel the remained dwell time in rx process */
++	u8 next_af_subtype;
++#ifdef WL_CFG80211_SYNC_GON
++	ulong af_tx_sent_jiffies;
++#endif /* WL_CFG80211_SYNC_GON */
++	struct escan_info escan_info;   /* escan information */
++	bool active_scan;	/* current scan mode */
++	bool ibss_starter;	/* indicates this sta is ibss starter */
++	bool link_up;		/* link/connection up flag */
++
++	/* indicate whether chip to support power save mode */
++	bool pwr_save;
++	bool roam_on;		/* on/off switch for self-roaming */
++	bool scan_tried;	/* indicates if first scan attempted */
++#if defined(BCMSDIO) || defined(BCMDBUS) || defined(BCMPCIE)
++	bool wlfc_on;
++#endif /* defined(BCMSDIO) || defined(BCMDBUS) */
++	bool vsdb_mode;
++#define WL_ROAM_OFF_ON_CONCURRENT		0x0001
++#define WL_ROAM_OFF_REVERT				0x0002
++	u32 roam_flags;
++	u8 *ioctl_buf;		/* ioctl buffer */
++	struct mutex ioctl_buf_sync;
++	u8 *escan_ioctl_buf;
++	u8 *extra_buf;	/* maily to grab assoc information */
++	struct dentry *debugfsdir;
++	struct rfkill *rfkill;
++	bool rf_blocked;
++	struct ieee80211_channel remain_on_chan;
++	enum nl80211_channel_type remain_on_chan_type;
++	u64 send_action_id;
++	u64 last_roc_id;
++	wait_queue_head_t netif_change_event;
++	wl_if_event_info if_event_info;
++	struct completion send_af_done;
++	struct afx_hdl *afx_hdl;
++	struct p2p_info *p2p;
++	bool p2p_supported;
++	void *btcoex_info;
++	struct timer_list scan_timeout;   /* Timer for catch scan event timeout */
++#if defined(P2P_IE_MISSING_FIX)
++	bool p2p_prb_noti;
++#endif
++	s32(*state_notifier) (struct bcm_cfg80211 *cfg,
++		struct net_info *_net_info, enum wl_status state, bool set);
++	unsigned long interrested_state;
++	wlc_ssid_t hostapd_ssid;
++#ifdef WL11U
++	bool wl11u;
++	u8 iw_ie[IW_IES_MAX_BUF_LEN];
++	u32 iw_ie_len;
++#endif /* WL11U */
++	bool sched_scan_running;	/* scheduled scan req status */
++#ifdef WL_SCHED_SCAN
++	struct cfg80211_sched_scan_request *sched_scan_req;	/* scheduled scan req */
++#endif /* WL_SCHED_SCAN */
++	bool scan_suppressed;
++	struct timer_list scan_supp_timer;
++	struct work_struct wlan_work;
++	struct mutex event_sync;	/* maily for up/down synchronization */
++	bool disable_roam_event;
++	bool pm_enable_work_on;
++	struct delayed_work pm_enable_work;
++	vndr_ie_setbuf_t *ibss_vsie;	/* keep the VSIE for IBSS */
++	int ibss_vsie_len;
++	u32 rmc_event_pid;
++	u32 rmc_event_seq;
++#ifdef WLAIBSS_MCHAN
++	struct ether_addr ibss_if_addr;
++	bcm_struct_cfgdev *ibss_cfgdev; /* For AIBSS */
++#endif /* WLAIBSS_MCHAN */
++	bcm_struct_cfgdev *bss_cfgdev;  /* For DUAL STA/STA+AP */
++	s32 cfgdev_bssidx;
++	bool bss_pending_op;		/* indicate where there is a pending IF operation */
++#ifdef WLFBT
++	uint8 fbt_key[FBT_KEYLEN];
++#endif
++	int roam_offload;
++#ifdef WL_NAN
++	bool nan_enable;
++	bool nan_running;
++#endif /* WL_NAN */
++#ifdef WL_CFG80211_P2P_DEV_IF
++	bool down_disc_if;
++#endif /* WL_CFG80211_P2P_DEV_IF */
++#ifdef P2PLISTEN_AP_SAMECHN
++	bool p2p_resp_apchn_status;
++#endif /* P2PLISTEN_AP_SAMECHN */
++	struct wl_wsec_key wep_key;
++#ifdef WLTDLS
++	u8 *tdls_mgmt_frame;
++	u32 tdls_mgmt_frame_len;
++	s32 tdls_mgmt_freq;
++#endif /* WLTDLS */
++	bool need_wait_afrx;
++#ifdef QOS_MAP_SET
++	uint8	 *up_table;	/* user priority table, size is UP_TABLE_MAX */
++#endif /* QOS_MAP_SET */
++	struct ether_addr last_roamed_addr;
++#ifdef DHD_LOSSLESS_ROAMING
++	struct timer_list roam_timeout;   /* Timer for catch roam timeout */
++#endif
++	bool rcc_enabled;	/* flag for Roam channel cache feature */
++};
++
++#if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == \
++	4 && __GNUC_MINOR__ >= 6))
++
++#define BCM_LIST_FOR_EACH_ENTRY_SAFE(pos, next, head, member) \
++_Pragma("GCC diagnostic push") \
++_Pragma("GCC diagnostic ignored \"-Wcast-qual\"") \
++list_for_each_entry_safe((pos), (next), (head), member) \
++_Pragma("GCC diagnostic pop") \
++
++#else
++#define BCM_LIST_FOR_EACH_ENTRY_SAFE(pos, next, head, member) \
++list_for_each_entry_safe((pos), (next), (head), member) \
++
++#endif /* STRICT_GCC_WARNINGS */
++
++static inline struct wl_bss_info *next_bss(struct wl_scan_results *list, struct wl_bss_info *bss)
++{
++	return bss = bss ? (struct wl_bss_info *)((uintptr) bss + dtoh32(bss->length)) :
++		list->bss_info;
++}
++
++static inline void
++wl_probe_wdev_all(struct bcm_cfg80211 *cfg)
++{
++	struct net_info *_net_info, *next;
++	unsigned long int flags;
++	int idx = 0;
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next,
++		&cfg->net_list, list) {
++		WL_ERR(("%s: net_list[%d] bssidx: %d, "
++			"ndev: %p, wdev: %p \n", __FUNCTION__,
++			idx++, _net_info->bssidx,
++			_net_info->ndev, _net_info->wdev));
++	}
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return;
++}
++
++static inline struct net_info *
++wl_get_netinfo_by_bssidx(struct bcm_cfg80211 *cfg, s32 bssidx)
++{
++	struct net_info *_net_info, *next, *info = NULL;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if ((bssidx >= 0) && (_net_info->bssidx == bssidx)) {
++			info = _net_info;
++			break;
++		}
++	}
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return info;
++}
++
++
++static inline void
++wl_dealloc_netinfo_by_wdev(struct bcm_cfg80211 *cfg, struct wireless_dev *wdev)
++{
++	struct net_info *_net_info, *next;
++	unsigned long int flags;
++
++#ifdef DHD_IFDEBUG
++	WL_ERR(("dealloc_netinfo enter wdev=%p \n", wdev));
++#endif
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (wdev && (_net_info->wdev == wdev)) {
++			wl_cfgbss_t *bss = &_net_info->bss;
++
++			kfree(bss->wpa_ie);
++			bss->wpa_ie = NULL;
++			kfree(bss->rsn_ie);
++			bss->rsn_ie = NULL;
++			kfree(bss->wps_ie);
++			bss->wps_ie = NULL;
++			list_del(&_net_info->list);
++			cfg->iface_cnt--;
++			kfree(_net_info);
++		}
++	}
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++#ifdef DHD_IFDEBUG
++	WL_ERR(("dealloc_netinfo exit iface_cnt=%d \n", cfg->iface_cnt));
++#endif
++}
++
++static inline s32
++wl_alloc_netinfo(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++       struct wireless_dev * wdev, s32 mode, bool pm_block, u8 bssidx)
++{
++	struct net_info *_net_info;
++	s32 err = 0;
++	unsigned long int flags;
++#ifdef DHD_IFDEBUG
++	WL_ERR(("alloc_netinfo enter bssidx=%d wdev=%p ndev=%p\n", bssidx, wdev, ndev));
++#endif
++	/* Check whether there is any duplicate entry for the
++	 * same bssidx.
++	 */
++	if ((_net_info = wl_get_netinfo_by_bssidx(cfg, bssidx))) {
++		/* We have a duplicate entry for the same bssidx
++		* already present which shouldn't have been the case.
++		* Attempt recovery.
++		*/
++		WL_ERR(("Duplicate entry for bssidx=%d present\n", bssidx));
++		wl_probe_wdev_all(cfg);
++#ifdef DHD_DEBUG
++		ASSERT(0);
++#endif /* DHD_DEBUG */
++		WL_ERR(("Removing the Dup entry for bssidx=%d \n", bssidx));
++		wl_dealloc_netinfo_by_wdev(cfg, _net_info->wdev);
++	}
++	if (cfg->iface_cnt == IFACE_MAX_CNT)
++		return -ENOMEM;
++	_net_info = kzalloc(sizeof(struct net_info), GFP_KERNEL);
++	if (!_net_info)
++		err = -ENOMEM;
++	else {
++		_net_info->mode = mode;
++		_net_info->ndev = ndev;
++		_net_info->wdev = wdev;
++		_net_info->pm_restore = 0;
++		_net_info->pm = 0;
++		_net_info->pm_block = pm_block;
++		_net_info->roam_off = WL_INVALID;
++		_net_info->bssidx = bssidx;
++		spin_lock_irqsave(&cfg->net_list_sync, flags);
++		cfg->iface_cnt++;
++		list_add(&_net_info->list, &cfg->net_list);
++		spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	}
++#ifdef DHD_IFDEBUG
++	WL_ERR(("alloc_netinfo exit iface_cnt=%d \n", cfg->iface_cnt));
++#endif
++	return err;
++}
++
++static inline void
++wl_delete_all_netinfo(struct bcm_cfg80211 *cfg)
++{
++	struct net_info *_net_info, *next;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		wl_cfgbss_t *bss = &_net_info->bss;
++
++		kfree(bss->wpa_ie);
++		bss->wpa_ie = NULL;
++		kfree(bss->rsn_ie);
++		bss->rsn_ie = NULL;
++		kfree(bss->wps_ie);
++		bss->wps_ie = NULL;
++		list_del(&_net_info->list);
++		if (_net_info->wdev)
++			kfree(_net_info->wdev);
++		kfree(_net_info);
++	}
++	cfg->iface_cnt = 0;
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++}
++static inline u32
++wl_get_status_all(struct bcm_cfg80211 *cfg, s32 status)
++
++{
++	struct net_info *_net_info, *next;
++	u32 cnt = 0;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (_net_info->ndev &&
++			test_bit(status, &_net_info->sme_state))
++			cnt++;
++	}
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return cnt;
++}
++static inline void
++wl_set_status_all(struct bcm_cfg80211 *cfg, s32 status, u32 op)
++{
++	struct net_info *_net_info, *next;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		switch (op) {
++			case 1:
++				break; /* set all status is not allowed */
++			case 2:
++				/*
++				 * Release the spinlock before calling notifier. Else there
++				 * will be nested calls
++				 */
++				spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++				clear_bit(status, &_net_info->sme_state);
++				if (cfg->state_notifier &&
++					test_bit(status, &(cfg->interrested_state)))
++					cfg->state_notifier(cfg, _net_info, status, false);
++				return;
++			case 4:
++				break; /* change all status is not allowed */
++			default:
++				break; /* unknown operation */
++		}
++	}
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++}
++static inline void
++wl_set_status_by_netdev(struct bcm_cfg80211 *cfg, s32 status,
++	struct net_device *ndev, u32 op)
++{
++
++	struct net_info *_net_info, *next;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (ndev && (_net_info->ndev == ndev)) {
++			switch (op) {
++				case 1:
++					/*
++					 * Release the spinlock before calling notifier. Else there
++					 * will be nested calls
++					 */
++					spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++					set_bit(status, &_net_info->sme_state);
++					if (cfg->state_notifier &&
++						test_bit(status, &(cfg->interrested_state)))
++						cfg->state_notifier(cfg, _net_info, status, true);
++					return;
++				case 2:
++					/*
++					 * Release the spinlock before calling notifier. Else there
++					 * will be nested calls
++					 */
++					spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++					clear_bit(status, &_net_info->sme_state);
++					if (cfg->state_notifier &&
++						test_bit(status, &(cfg->interrested_state)))
++						cfg->state_notifier(cfg, _net_info, status, false);
++					return;
++				case 4:
++					change_bit(status, &_net_info->sme_state);
++					break;
++			}
++		}
++
++	}
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++
++}
++
++static inline wl_cfgbss_t *
++wl_get_cfgbss_by_wdev(struct bcm_cfg80211 *cfg,
++	struct wireless_dev *wdev)
++{
++	struct net_info *_net_info, *next;
++	wl_cfgbss_t *bss = NULL;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (wdev && (_net_info->wdev == wdev)) {
++			bss = &_net_info->bss;
++			break;
++		}
++	}
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return bss;
++}
++
++static inline u32
++wl_get_status_by_netdev(struct bcm_cfg80211 *cfg, s32 status,
++	struct net_device *ndev)
++{
++	struct net_info *_net_info, *next;
++	u32 stat = 0;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (ndev && (_net_info->ndev == ndev)) {
++			stat = test_bit(status, &_net_info->sme_state);
++			break;
++		}
++	}
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return stat;
++}
++
++static inline s32
++wl_get_mode_by_netdev(struct bcm_cfg80211 *cfg, struct net_device *ndev)
++{
++	struct net_info *_net_info, *next;
++	s32 mode = -1;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (ndev && (_net_info->ndev == ndev)) {
++			mode = _net_info->mode;
++			break;
++		}
++	}
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return mode;
++}
++
++static inline void
++wl_set_mode_by_netdev(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	s32 mode)
++{
++	struct net_info *_net_info, *next;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (ndev && (_net_info->ndev == ndev))
++			_net_info->mode = mode;
++	}
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++}
++
++static inline s32
++wl_get_bssidx_by_wdev(struct bcm_cfg80211 *cfg, struct wireless_dev *wdev)
++{
++	struct net_info *_net_info, *next;
++	s32 bssidx = -1;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (_net_info->wdev && (_net_info->wdev == wdev)) {
++			bssidx = _net_info->bssidx;
++			break;
++		}
++	}
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return bssidx;
++}
++
++static inline struct wireless_dev *
++wl_get_wdev_by_bssidx(struct bcm_cfg80211 *cfg, s32 bssidx)
++{
++	struct net_info *_net_info, *next;
++	struct wireless_dev *wdev = NULL;
++	unsigned long int flags;
++
++	if (bssidx < 0)
++		return NULL;
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (_net_info->bssidx == bssidx) {
++				wdev = _net_info->wdev;
++				break;
++		}
++	}
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return wdev;
++}
++
++static inline struct wl_profile *
++wl_get_profile_by_netdev(struct bcm_cfg80211 *cfg, struct net_device *ndev)
++{
++	struct net_info *_net_info, *next;
++	struct wl_profile *prof = NULL;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (ndev && (_net_info->ndev == ndev)) {
++			prof = &_net_info->profile;
++			break;
++		}
++	}
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return prof;
++}
++static inline struct net_info *
++wl_get_netinfo_by_netdev(struct bcm_cfg80211 *cfg, struct net_device *ndev)
++{
++	struct net_info *_net_info, *next, *info = NULL;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (ndev && (_net_info->ndev == ndev)) {
++			info = _net_info;
++			break;
++		}
++	}
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return info;
++}
++
++static inline struct net_info *
++wl_get_netinfo_by_wdev(struct bcm_cfg80211 *cfg, struct wireless_dev *wdev)
++{
++	struct net_info *_net_info, *next, *info = NULL;
++	unsigned long int flags;
++
++	spin_lock_irqsave(&cfg->net_list_sync, flags);
++	BCM_LIST_FOR_EACH_ENTRY_SAFE(_net_info, next, &cfg->net_list, list) {
++		if (wdev && (_net_info->wdev == wdev)) {
++			info = _net_info;
++			break;
++		}
++	}
++	spin_unlock_irqrestore(&cfg->net_list_sync, flags);
++	return info;
++}
++
++#define is_p2p_group_iface(wdev) (((wdev->iftype == NL80211_IFTYPE_P2P_GO) || \
++		(wdev->iftype == NL80211_IFTYPE_P2P_CLIENT)) ? 1 : 0)
++#define bcmcfg_to_wiphy(cfg) (cfg->wdev->wiphy)
++#define bcmcfg_to_prmry_ndev(cfg) (cfg->wdev->netdev)
++#define bcmcfg_to_prmry_wdev(cfg) (cfg->wdev)
++#define bcmcfg_to_p2p_wdev(cfg) (cfg->p2p_wdev)
++#define ndev_to_wl(n) (wdev_to_wl(n->ieee80211_ptr))
++#define ndev_to_wdev(ndev) (ndev->ieee80211_ptr)
++#define wdev_to_ndev(wdev) (wdev->netdev)
++
++#if defined(WL_ENABLE_P2P_IF)
++#define ndev_to_wlc_ndev(ndev, cfg)	((ndev == cfg->p2p_net) ? \
++	bcmcfg_to_prmry_ndev(cfg) : ndev)
++#else
++#define ndev_to_wlc_ndev(ndev, cfg)	(ndev)
++#endif /* WL_ENABLE_P2P_IF */
++
++#define wdev_to_wlc_ndev(wdev, cfg)	\
++	(wdev_to_ndev(wdev) ? \
++	wdev_to_ndev(wdev) : bcmcfg_to_prmry_ndev(cfg))
++#if defined(WL_CFG80211_P2P_DEV_IF)
++#define cfgdev_to_wlc_ndev(cfgdev, cfg)	wdev_to_wlc_ndev(cfgdev, cfg)
++#define bcmcfg_to_prmry_cfgdev(cfgdev, cfg) bcmcfg_to_prmry_wdev(cfg)
++#elif defined(WL_ENABLE_P2P_IF)
++#define cfgdev_to_wlc_ndev(cfgdev, cfg)	ndev_to_wlc_ndev(cfgdev, cfg)
++#define bcmcfg_to_prmry_cfgdev(cfgdev, cfg) bcmcfg_to_prmry_ndev(cfg)
++#else
++#define cfgdev_to_wlc_ndev(cfgdev, cfg)	(cfgdev)
++#define bcmcfg_to_prmry_cfgdev(cfgdev, cfg) (cfgdev)
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++#define cfgdev_to_wdev(cfgdev)	(cfgdev)
++#define ndev_to_cfgdev(ndev)	ndev_to_wdev(ndev)
++#define cfgdev_to_ndev(cfgdev)	(cfgdev ? (cfgdev->netdev) : NULL)
++#define wdev_to_cfgdev(cfgdev)	(cfgdev)
++#define discover_cfgdev(cfgdev, cfg) (cfgdev->iftype == NL80211_IFTYPE_P2P_DEVICE)
++#else
++#define cfgdev_to_wdev(cfgdev)	(cfgdev->ieee80211_ptr)
++#define wdev_to_cfgdev(cfgdev)	cfgdev ? (cfgdev->netdev) : NULL
++#define ndev_to_cfgdev(ndev)	(ndev)
++#define cfgdev_to_ndev(cfgdev)	(cfgdev)
++#define discover_cfgdev(cfgdev, cfg) (cfgdev == cfg->p2p_net)
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++#define scan_req_match(cfg)	(((cfg) && (cfg->scan_request) && \
++	(cfg->scan_request->wdev == cfg->p2p_wdev)) ? true : false)
++#elif defined(WL_ENABLE_P2P_IF)
++#define scan_req_match(cfg)	(((cfg) && (cfg->scan_request) && \
++	(cfg->scan_request->dev == cfg->p2p_net)) ? true : false)
++#else
++#define scan_req_match(cfg)	(((cfg) && p2p_is_on(cfg) && p2p_scan(cfg)) ? \
++	true : false)
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++#define scan_req_iftype(req) (req->dev->ieee80211_ptr->iftype)
++#else
++#define scan_req_iftype(req) (req->wdev->iftype)
++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0) */
++
++#define wl_to_sr(w) (w->scan_req_int)
++#if defined(STATIC_WL_PRIV_STRUCT)
++#define wl_to_ie(w) (w->ie)
++#define wl_to_conn(w) (w->conn_info)
++#else
++#define wl_to_ie(w) (&w->ie)
++#define wl_to_conn(w) (&w->conn_info)
++#endif
++#define wiphy_from_scan(w) (w->escan_info.wiphy)
++#define wl_get_drv_status_all(cfg, stat) \
++	(wl_get_status_all(cfg, WL_STATUS_ ## stat))
++#define wl_get_drv_status(cfg, stat, ndev)  \
++	(wl_get_status_by_netdev(cfg, WL_STATUS_ ## stat, ndev))
++#define wl_set_drv_status(cfg, stat, ndev)  \
++	(wl_set_status_by_netdev(cfg, WL_STATUS_ ## stat, ndev, 1))
++#define wl_clr_drv_status(cfg, stat, ndev)  \
++	(wl_set_status_by_netdev(cfg, WL_STATUS_ ## stat, ndev, 2))
++#define wl_clr_drv_status_all(cfg, stat)  \
++	(wl_set_status_all(cfg, WL_STATUS_ ## stat, 2))
++#define wl_chg_drv_status(cfg, stat, ndev)  \
++	(wl_set_status_by_netdev(cfg, WL_STATUS_ ## stat, ndev, 4))
++
++#define for_each_bss(list, bss, __i)	\
++	for (__i = 0; __i < list->count && __i < WL_AP_MAX; __i++, bss = next_bss(list, bss))
++
++#define for_each_ndev(cfg, iter, next) \
++	list_for_each_entry_safe(iter, next, &cfg->net_list, list)
++
++/* In case of WPS from wpa_supplicant, pairwise siute and group suite is 0.
++ * In addtion to that, wpa_version is WPA_VERSION_1
++ */
++#define is_wps_conn(_sme) \
++	((wl_cfgp2p_find_wpsie((u8 *)_sme->ie, _sme->ie_len) != NULL) && \
++	 (!_sme->crypto.n_ciphers_pairwise) && \
++	 (!_sme->crypto.cipher_group))
++
++#ifdef WLFBT
++#if defined(WLAN_AKM_SUITE_FT_8021X) && defined(WLAN_AKM_SUITE_FT_PSK)
++#define IS_AKM_SUITE_FT(sec) (sec->wpa_auth == WLAN_AKM_SUITE_FT_8021X || \
++	sec->wpa_auth == WLAN_AKM_SUITE_FT_PSK)
++#elif defined(WLAN_AKM_SUITE_FT_8021X)
++#define IS_AKM_SUITE_FT(sec) (sec->wpa_auth == WLAN_AKM_SUITE_FT_8021X)
++#elif defined(WLAN_AKM_SUITE_FT_PSK)
++#define IS_AKM_SUITE_FT(sec) (sec->wpa_auth == WLAN_AKM_SUITE_FT_PSK)
++#else
++#define IS_AKM_SUITE_FT(sec) false
++#endif /* WLAN_AKM_SUITE_FT_8021X && WLAN_AKM_SUITE_FT_PSK */
++#else
++#define IS_AKM_SUITE_FT(sec) false
++#endif /* WLFBT */
++
++#define IS_AKM_SUITE_CCKM(sec) false
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
++#define STA_INFO_BIT(info) (1ul << NL80211_STA_ ## info)
++#define strnicmp(str1, str2, len) strncasecmp((str1), (str2), (len))
++#else
++#define STA_INFO_BIT(info) (STATION_ ## info)
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) */
++
++extern s32 wl_cfg80211_attach(struct net_device *ndev, void *context);
++extern s32 wl_cfg80211_attach_post(struct net_device *ndev);
++extern void wl_cfg80211_detach(void *para);
++
++extern void wl_cfg80211_event(struct net_device *ndev, const wl_event_msg_t *e,
++            void *data);
++void wl_cfg80211_set_parent_dev(void *dev);
++struct device *wl_cfg80211_get_parent_dev(void);
++
++/* clear IEs */
++extern s32 wl_cfg80211_clear_mgmt_vndr_ies(struct bcm_cfg80211 *cfg);
++extern s32 wl_cfg80211_clear_per_bss_ies(struct bcm_cfg80211 *cfg, s32 bssidx);
++
++extern s32 wl_cfg80211_up(void *para);
++extern s32 wl_cfg80211_down(void *para);
++extern s32 wl_cfg80211_notify_ifadd(int ifidx, char *name, uint8 *mac, uint8 bssidx);
++extern s32 wl_cfg80211_notify_ifdel(int ifidx, char *name, uint8 *mac, uint8 bssidx);
++extern s32 wl_cfg80211_notify_ifchange(int ifidx, char *name, uint8 *mac, uint8 bssidx);
++extern struct net_device* wl_cfg80211_allocate_if(struct bcm_cfg80211 *cfg, int ifidx, char *name,
++	uint8 *mac, uint8 bssidx, char *dngl_name);
++extern int wl_cfg80211_register_if(struct bcm_cfg80211 *cfg, int ifidx, struct net_device* ndev);
++extern int wl_cfg80211_remove_if(struct bcm_cfg80211 *cfg, int ifidx, struct net_device* ndev);
++extern int wl_cfg80211_scan_stop(bcm_struct_cfgdev *cfgdev);
++extern bool wl_cfg80211_is_vsdb_mode(void);
++extern void* wl_cfg80211_get_dhdp(void);
++extern bool wl_cfg80211_is_p2p_active(void);
++extern bool wl_cfg80211_is_roam_offload(void);
++extern bool wl_cfg80211_is_event_from_connected_bssid(const wl_event_msg_t *e, int ifidx);
++extern void wl_cfg80211_dbg_level(u32 level);
++extern s32 wl_cfg80211_get_p2p_dev_addr(struct net_device *net, struct ether_addr *p2pdev_addr);
++extern s32 wl_cfg80211_set_p2p_noa(struct net_device *net, char* buf, int len);
++extern s32 wl_cfg80211_get_p2p_noa(struct net_device *net, char* buf, int len);
++extern s32 wl_cfg80211_set_wps_p2p_ie(struct net_device *net, char *buf, int len,
++	enum wl_management_type type);
++extern s32 wl_cfg80211_set_p2p_ps(struct net_device *net, char* buf, int len);
++extern s32 wl_cfg80211_set_p2p_ecsa(struct net_device *net, char* buf, int len);
++#ifdef WL11ULB
++extern s32 wl_cfg80211_set_ulb_mode(struct net_device *dev, int mode);
++extern s32 wl_cfg80211_set_ulb_bw(struct net_device *dev,
++	u32 ulb_bw,  char *ifname);
++#endif /* WL11ULB */
++#ifdef P2PLISTEN_AP_SAMECHN
++extern s32 wl_cfg80211_set_p2p_resp_ap_chn(struct net_device *net, s32 enable);
++#endif /* P2PLISTEN_AP_SAMECHN */
++
++/* btcoex functions */
++void* wl_cfg80211_btcoex_init(struct net_device *ndev);
++void wl_cfg80211_btcoex_deinit(void);
++
++#ifdef WL_SUPPORT_AUTO_CHANNEL
++#define CHANSPEC_BUF_SIZE	1024
++#define CHAN_SEL_IOCTL_DELAY	300
++#define CHAN_SEL_RETRY_COUNT	15
++#define CHANNEL_IS_RADAR(channel)	(((channel & WL_CHAN_RADAR) || \
++	(channel & WL_CHAN_PASSIVE)) ? true : false)
++#define CHANNEL_IS_2G(channel)	(((channel >= 1) && (channel <= 14)) ? \
++	true : false)
++#define CHANNEL_IS_5G(channel)	(((channel >= 36) && (channel <= 165)) ? \
++	true : false)
++extern s32 wl_cfg80211_get_best_channels(struct net_device *dev, char* command,
++	int total_len);
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++extern int wl_cfg80211_ether_atoe(const char *a, struct ether_addr *n);
++extern int wl_cfg80211_hang(struct net_device *dev, u16 reason);
++extern s32 wl_mode_to_nl80211_iftype(s32 mode);
++int wl_cfg80211_do_driver_init(struct net_device *net);
++void wl_cfg80211_enable_trace(bool set, u32 level);
++extern s32 wl_update_wiphybands(struct bcm_cfg80211 *cfg, bool notify);
++extern s32 wl_cfg80211_if_is_group_owner(void);
++extern chanspec_t wl_chspec_host_to_driver(chanspec_t chanspec);
++extern chanspec_t wl_ch_host_to_driver(s32 bssidx, u16 channel);
++extern s32 wl_set_tx_power(struct net_device *dev,
++	enum nl80211_tx_power_setting type, s32 dbm);
++extern s32 wl_get_tx_power(struct net_device *dev, s32 *dbm);
++extern s32 wl_add_remove_eventmsg(struct net_device *ndev, u16 event, bool add);
++extern void wl_stop_wait_next_action_frame(struct bcm_cfg80211 *cfg, struct net_device *ndev);
++extern void wl_cfg80211_add_to_eventbuffer(wl_eventmsg_buf_t *ev, u16 event, bool set);
++extern s32 wl_cfg80211_apply_eventbuffer(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, wl_eventmsg_buf_t *ev);
++extern void get_primary_mac(struct bcm_cfg80211 *cfg, struct ether_addr *mac);
++extern void wl_cfg80211_update_power_mode(struct net_device *dev);
++extern void wl_cfg80211_set_passive_scan(struct net_device *dev, char *command);
++extern void wl_terminate_event_handler(void);
++#define SCAN_BUF_CNT	2
++#define SCAN_BUF_NEXT	1
++#define WL_SCANTYPE_LEGACY	0x1
++#define WL_SCANTYPE_P2P		0x2
++#define wl_escan_set_sync_id(a, b) ((a) = htod16(0x1234))
++#define wl_escan_set_type(a, b)
++#define wl_escan_get_buf(a, b) ((wl_scan_results_t *) (a)->escan_info.escan_buf)
++#define wl_escan_check_sync_id(a, b, c) 0
++#define wl_escan_print_sync_id(a, b, c)
++#define wl_escan_increment_sync_id(a, b)
++#define wl_escan_init_sync_id(a)
++extern void wl_cfg80211_ibss_vsie_set_buffer(vndr_ie_setbuf_t *ibss_vsie, int ibss_vsie_len);
++extern s32 wl_cfg80211_ibss_vsie_delete(struct net_device *dev);
++extern void wl_cfg80211_set_rmc_pid(int pid);
++extern int wl_cfg80211_set_mgmt_vndr_ies(struct bcm_cfg80211 *cfg,
++	bcm_struct_cfgdev *cfgdev, s32 bssidx, s32 pktflag,
++	const u8 *vndr_ie, u32 vndr_ie_len);
++
++#ifdef WLFBT
++extern void wl_cfg80211_get_fbt_key(uint8 *key);
++#endif
++
++/* Action frame specific functions */
++extern u8 wl_get_action_category(void *frame, u32 frame_len);
++extern int wl_get_public_action(void *frame, u32 frame_len, u8 *ret_action);
++
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++struct net_device *wl_cfg80211_get_remain_on_channel_ndev(struct bcm_cfg80211 *cfg);
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++
++#ifdef WL_SUPPORT_ACS
++#define ACS_MSRMNT_DELAY 1000 /* dump_obss delay in ms */
++#define IOCTL_RETRY_COUNT 5
++#define CHAN_NOISE_DUMMY -80
++#define OBSS_TOKEN_IDX 15
++#define IBSS_TOKEN_IDX 15
++#define TX_TOKEN_IDX 14
++#define CTG_TOKEN_IDX 13
++#define PKT_TOKEN_IDX 15
++#define IDLE_TOKEN_IDX 12
++#endif /* WL_SUPPORT_ACS */
++
++
++extern int wl_cfg80211_get_ioctl_version(void);
++extern int wl_cfg80211_enable_roam_offload(struct net_device *dev, int enable);
++extern s32 wl_cfg80211_dfs_ap_move(struct net_device *ndev, char *data,
++		char *command, int total_len);
++extern s32 wl_cfg80211_wbtext_config(struct net_device *ndev, char *data,
++		char *command, int total_len);
++extern int wl_cfg80211_wbtext_weight_config(struct net_device *ndev, char *data,
++		char *command, int total_len);
++extern int wl_cfg80211_wbtext_table_config(struct net_device *ndev, char *data,
++		char *command, int total_len);
++extern s32 wl_cfg80211_wbtext_delta_config(struct net_device *ndev, char *data,
++		char *command, int total_len);
++extern s32 wl_cfg80211_get_chanspecs_2g(struct net_device *ndev,
++		void *buf, s32 buflen);
++extern s32 wl_cfg80211_get_chanspecs_5g(struct net_device *ndev,
++		void *buf, s32 buflen);
++#if defined(WL_VIRTUAL_APSTA)
++extern int wl_cfg80211_interface_create(struct net_device *dev, char *name);
++extern int wl_cfg80211_interface_delete(struct net_device *dev, char *name);
++#endif /* defined (WL_VIRTUAL_APSTA) */
++
++#ifdef WL_NAN
++extern int wl_cfg80211_nan_cmd_handler(struct net_device *ndev, char *cmd,
++	int cmd_len);
++#endif /* WL_NAN */
++
++#ifdef WL_CFG80211_P2P_DEV_IF
++extern void wl_cfg80211_del_p2p_wdev(void);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++#if (defined(STBLINUX) && defined(WL_CFG80211))
++
++int wl_cfg80211_cleanup(void);
++
++#endif /* STBLINUX && WL_CFG80211 */
++
++#if defined(WL_SUPPORT_AUTO_CHANNEL)
++extern int wl_cfg80211_set_spect(struct net_device *dev, int spect);
++extern int wl_cfg80211_get_sta_channel(struct net_device *dev);
++#endif /* WL_SUPPORT_AUTO_CHANNEL */
++
++#define RETURN_EIO_IF_NOT_UP(wlpriv)                        \
++do {                                    \
++	struct net_device *checkSysUpNDev = bcmcfg_to_prmry_ndev(wlpriv);           \
++	if (unlikely(!wl_get_drv_status(wlpriv, READY, checkSysUpNDev))) {  \
++		WL_INFORM(("device is not ready\n"));           \
++		return -EIO;                        \
++	}                               \
++} while (0)
++
++#ifdef QOS_MAP_SET
++extern uint8 *wl_get_up_table(void);
++#endif /* QOS_MAP_SET */
++
++#endif /* _wl_cfg80211_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfg_btcoex.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfg_btcoex.c
+new file mode 100644
+index 000000000..55c22ec06
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfg_btcoex.c
+@@ -0,0 +1,562 @@
++/*
++ * Linux cfg80211 driver - Dongle Host Driver (DHD) related
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfg_btcoex.c 709309 2019-01-17 09:04:00Z $
++ */
++
++#include <net/rtnetlink.h>
++
++#include <bcmutils.h>
++#include <wldev_common.h>
++#include <wl_cfg80211.h>
++#include <dhd_cfg80211.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhdioctl.h>
++#include <wlioctl.h>
++
++#ifdef PKT_FILTER_SUPPORT
++extern uint dhd_pkt_filter_enable;
++extern uint dhd_master_mode;
++extern void dhd_pktfilter_offload_enable(dhd_pub_t * dhd, char *arg, int enable, int master_mode);
++#endif
++
++struct btcoex_info {
++	struct timer_list timer;
++	u32 timer_ms;
++	u32 timer_on;
++	u32 ts_dhcp_start;	/* ms ts ecord time stats */
++	u32 ts_dhcp_ok;		/* ms ts ecord time stats */
++	bool dhcp_done;	/* flag, indicates that host done with
++					 * dhcp before t1/t2 expiration
++					 */
++	s32 bt_state;
++	struct work_struct work;
++	struct net_device *dev;
++};
++
++static struct btcoex_info *btcoex_info_loc = NULL;
++
++/* TODO: clean up the BT-Coex code, it still have some legacy ioctl/iovar functions */
++
++/* use New SCO/eSCO smart YG suppression */
++#define BT_DHCP_eSCO_FIX
++/* this flag boost wifi pkt priority to max, caution: -not fair to sco */
++#define BT_DHCP_USE_FLAGS
++/* T1 start SCO/ESCo priority suppression */
++#define BT_DHCP_OPPR_WIN_TIME	2500
++/* T2 turn off SCO/SCO supperesion is (timeout) */
++#define BT_DHCP_FLAG_FORCE_TIME 5500
++
++enum wl_cfg80211_btcoex_status {
++	BT_DHCP_IDLE,
++	BT_DHCP_START,
++	BT_DHCP_OPPR_WIN,
++	BT_DHCP_FLAG_FORCE_TIMEOUT
++};
++
++/*
++ * get named driver variable to uint register value and return error indication
++ * calling example: dev_wlc_intvar_get_reg(dev, "btc_params",66, &reg_value)
++ */
++static int
++dev_wlc_intvar_get_reg(struct net_device *dev, char *name,
++	uint reg, int *retval)
++{
++	union {
++		char buf[WLC_IOCTL_SMLEN];
++		int val;
++	} var;
++	int error;
++
++	bcm_mkiovar(name, (char *)(&reg), sizeof(reg),
++		(char *)(&var), sizeof(var.buf));
++	error = wldev_ioctl(dev, WLC_GET_VAR, (char *)(&var), sizeof(var.buf), false);
++
++	*retval = dtoh32(var.val);
++	return (error);
++}
++
++static int
++dev_wlc_bufvar_set(struct net_device *dev, char *name, char *buf, int len)
++{
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31)
++	char ioctlbuf_local[1024];
++#else
++	static char ioctlbuf_local[1024];
++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31) */
++
++	bcm_mkiovar(name, buf, len, ioctlbuf_local, sizeof(ioctlbuf_local));
++
++	return (wldev_ioctl(dev, WLC_SET_VAR, ioctlbuf_local, sizeof(ioctlbuf_local), true));
++}
++/*
++get named driver variable to uint register value and return error indication
++calling example: dev_wlc_intvar_set_reg(dev, "btc_params",66, value)
++*/
++static int
++dev_wlc_intvar_set_reg(struct net_device *dev, char *name, char *addr, char * val)
++{
++	char reg_addr[8];
++
++	memset(reg_addr, 0, sizeof(reg_addr));
++	memcpy((char *)&reg_addr[0], (char *)addr, 4);
++	memcpy((char *)&reg_addr[4], (char *)val, 4);
++
++	return (dev_wlc_bufvar_set(dev, name, (char *)&reg_addr[0], sizeof(reg_addr)));
++}
++
++static bool btcoex_is_sco_active(struct net_device *dev)
++{
++	int ioc_res = 0;
++	bool res = FALSE;
++	int sco_id_cnt = 0;
++	int param27;
++	int i;
++
++	for (i = 0; i < 12; i++) {
++
++		ioc_res = dev_wlc_intvar_get_reg(dev, "btc_params", 27, &param27);
++
++		WL_TRACE(("sample[%d], btc params: 27:%x\n", i, param27));
++
++		if (ioc_res < 0) {
++			WL_ERR(("ioc read btc params error\n"));
++			break;
++		}
++
++		if ((param27 & 0x6) == 2) { /* count both sco & esco  */
++			sco_id_cnt++;
++		}
++
++		if (sco_id_cnt > 2) {
++			WL_TRACE(("sco/esco detected, pkt id_cnt:%d  samples:%d\n",
++				sco_id_cnt, i));
++			res = TRUE;
++			break;
++		}
++
++		OSL_SLEEP(5);
++	}
++
++	return res;
++}
++
++#if defined(BT_DHCP_eSCO_FIX)
++/* Enhanced BT COEX settings for eSCO compatibility during DHCP window */
++static int set_btc_esco_params(struct net_device *dev, bool trump_sco)
++{
++	static bool saved_status = FALSE;
++
++	char buf_reg50va_dhcp_on[8] =
++		{ 50, 00, 00, 00, 0x22, 0x80, 0x00, 0x00 };
++	char buf_reg51va_dhcp_on[8] =
++		{ 51, 00, 00, 00, 0x00, 0x00, 0x00, 0x00 };
++	char buf_reg64va_dhcp_on[8] =
++		{ 64, 00, 00, 00, 0x00, 0x00, 0x00, 0x00 };
++	char buf_reg65va_dhcp_on[8] =
++		{ 65, 00, 00, 00, 0x00, 0x00, 0x00, 0x00 };
++	char buf_reg71va_dhcp_on[8] =
++		{ 71, 00, 00, 00, 0x00, 0x00, 0x00, 0x00 };
++	uint32 regaddr;
++	static uint32 saved_reg50;
++	static uint32 saved_reg51;
++	static uint32 saved_reg64;
++	static uint32 saved_reg65;
++	static uint32 saved_reg71;
++
++	if (trump_sco) {
++		/* this should reduce eSCO agressive retransmit
++		 * w/o breaking it
++		 */
++
++		/* 1st save current */
++		WL_TRACE(("Do new SCO/eSCO coex algo {save &"
++			  "override}\n"));
++		if ((!dev_wlc_intvar_get_reg(dev, "btc_params", 50, &saved_reg50)) &&
++			(!dev_wlc_intvar_get_reg(dev, "btc_params", 51, &saved_reg51)) &&
++			(!dev_wlc_intvar_get_reg(dev, "btc_params", 64, &saved_reg64)) &&
++			(!dev_wlc_intvar_get_reg(dev, "btc_params", 65, &saved_reg65)) &&
++			(!dev_wlc_intvar_get_reg(dev, "btc_params", 71, &saved_reg71))) {
++			saved_status = TRUE;
++			WL_TRACE(("saved bt_params[50,51,64,65,71]:"
++				  "0x%x 0x%x 0x%x 0x%x 0x%x\n",
++				  saved_reg50, saved_reg51,
++				  saved_reg64, saved_reg65, saved_reg71));
++		} else {
++			WL_ERR((":%s: save btc_params failed\n",
++				__FUNCTION__));
++			saved_status = FALSE;
++			return -1;
++		}
++
++		WL_TRACE(("override with [50,51,64,65,71]:"
++			  "0x%x 0x%x 0x%x 0x%x 0x%x\n",
++			  *(u32 *)(buf_reg50va_dhcp_on+4),
++			  *(u32 *)(buf_reg51va_dhcp_on+4),
++			  *(u32 *)(buf_reg64va_dhcp_on+4),
++			  *(u32 *)(buf_reg65va_dhcp_on+4),
++			  *(u32 *)(buf_reg71va_dhcp_on+4)));
++
++		dev_wlc_bufvar_set(dev, "btc_params",
++			(char *)&buf_reg50va_dhcp_on[0], 8);
++		dev_wlc_bufvar_set(dev, "btc_params",
++			(char *)&buf_reg51va_dhcp_on[0], 8);
++		dev_wlc_bufvar_set(dev, "btc_params",
++			(char *)&buf_reg64va_dhcp_on[0], 8);
++		dev_wlc_bufvar_set(dev, "btc_params",
++			(char *)&buf_reg65va_dhcp_on[0], 8);
++		dev_wlc_bufvar_set(dev, "btc_params",
++			(char *)&buf_reg71va_dhcp_on[0], 8);
++
++		saved_status = TRUE;
++	} else if (saved_status) {
++		/* restore previously saved bt params */
++		WL_TRACE(("Do new SCO/eSCO coex algo {save &"
++			  "override}\n"));
++
++		regaddr = 50;
++		dev_wlc_intvar_set_reg(dev, "btc_params",
++			(char *)&regaddr, (char *)&saved_reg50);
++		regaddr = 51;
++		dev_wlc_intvar_set_reg(dev, "btc_params",
++			(char *)&regaddr, (char *)&saved_reg51);
++		regaddr = 64;
++		dev_wlc_intvar_set_reg(dev, "btc_params",
++			(char *)&regaddr, (char *)&saved_reg64);
++		regaddr = 65;
++		dev_wlc_intvar_set_reg(dev, "btc_params",
++			(char *)&regaddr, (char *)&saved_reg65);
++		regaddr = 71;
++		dev_wlc_intvar_set_reg(dev, "btc_params",
++			(char *)&regaddr, (char *)&saved_reg71);
++
++		WL_TRACE(("restore bt_params[50,51,64,65,71]:"
++			"0x%x 0x%x 0x%x 0x%x 0x%x\n",
++			saved_reg50, saved_reg51, saved_reg64,
++			saved_reg65, saved_reg71));
++
++		saved_status = FALSE;
++	} else {
++		WL_ERR((":%s att to restore not saved BTCOEX params\n",
++			__FUNCTION__));
++		return -1;
++	}
++	return 0;
++}
++#endif /* BT_DHCP_eSCO_FIX */
++
++static void
++wl_cfg80211_bt_setflag(struct net_device *dev, bool set)
++{
++#if defined(BT_DHCP_USE_FLAGS)
++	char buf_flag7_dhcp_on[8] = { 7, 00, 00, 00, 0x1, 0x0, 0x00, 0x00 };
++	char buf_flag7_default[8]   = { 7, 00, 00, 00, 0x0, 0x00, 0x00, 0x00};
++#endif
++
++
++#if defined(BT_DHCP_eSCO_FIX)
++	/* set = 1, save & turn on  0 - off & restore prev settings */
++	set_btc_esco_params(dev, set);
++#endif
++
++#if defined(BT_DHCP_USE_FLAGS)
++	WL_TRACE(("WI-FI priority boost via bt flags, set:%d\n", set));
++	if (set == TRUE)
++		/* Forcing bt_flag7  */
++		dev_wlc_bufvar_set(dev, "btc_flags",
++			(char *)&buf_flag7_dhcp_on[0],
++			sizeof(buf_flag7_dhcp_on));
++	else
++		/* Restoring default bt flag7 */
++		dev_wlc_bufvar_set(dev, "btc_flags",
++			(char *)&buf_flag7_default[0],
++			sizeof(buf_flag7_default));
++#endif
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++static void wl_cfg80211_bt_timerfunc(struct timer_list *t)
++{
++	struct btcoex_info *bt_local = from_timer(bt_local, t, timer);
++#else
++static void wl_cfg80211_bt_timerfunc(ulong data)
++{
++	struct btcoex_info *bt_local = (struct btcoex_info *)data;
++#endif
++	WL_TRACE(("Enter\n"));
++	bt_local->timer_on = 0;
++	schedule_work(&bt_local->work);
++}
++
++static void wl_cfg80211_bt_handler(struct work_struct *work)
++{
++	struct btcoex_info *btcx_inf;
++
++	btcx_inf = container_of(work, struct btcoex_info, work);
++
++	if (btcx_inf->timer_on) {
++		btcx_inf->timer_on = 0;
++		del_timer_sync(&btcx_inf->timer);
++	}
++
++	switch (btcx_inf->bt_state) {
++		case BT_DHCP_START:
++			/* DHCP started
++			 * provide OPPORTUNITY window to get DHCP address
++			 */
++			WL_TRACE(("bt_dhcp stm: started \n"));
++
++			btcx_inf->bt_state = BT_DHCP_OPPR_WIN;
++			mod_timer(&btcx_inf->timer,
++				jiffies + msecs_to_jiffies(BT_DHCP_OPPR_WIN_TIME));
++			btcx_inf->timer_on = 1;
++			break;
++
++		case BT_DHCP_OPPR_WIN:
++			if (btcx_inf->dhcp_done) {
++				WL_TRACE(("DHCP Done before T1 expiration\n"));
++				goto btc_coex_idle;
++			}
++
++			/* DHCP is not over yet, start lowering BT priority
++			 * enforce btc_params + flags if necessary
++			 */
++			WL_TRACE(("DHCP T1:%d expired\n", BT_DHCP_OPPR_WIN_TIME));
++			if (btcx_inf->dev)
++				wl_cfg80211_bt_setflag(btcx_inf->dev, TRUE);
++			btcx_inf->bt_state = BT_DHCP_FLAG_FORCE_TIMEOUT;
++			mod_timer(&btcx_inf->timer,
++				jiffies + msecs_to_jiffies(BT_DHCP_FLAG_FORCE_TIME));
++			btcx_inf->timer_on = 1;
++			break;
++
++		case BT_DHCP_FLAG_FORCE_TIMEOUT:
++			if (btcx_inf->dhcp_done) {
++				WL_TRACE(("DHCP Done before T2 expiration\n"));
++			} else {
++				/* Noo dhcp during T1+T2, restore BT priority */
++				WL_TRACE(("DHCP wait interval T2:%d msec expired\n",
++					BT_DHCP_FLAG_FORCE_TIME));
++			}
++
++			/* Restoring default bt priority */
++			if (btcx_inf->dev)
++				wl_cfg80211_bt_setflag(btcx_inf->dev, FALSE);
++btc_coex_idle:
++			btcx_inf->bt_state = BT_DHCP_IDLE;
++			btcx_inf->timer_on = 0;
++			break;
++
++		default:
++			WL_ERR(("error g_status=%d !!!\n",	btcx_inf->bt_state));
++			if (btcx_inf->dev)
++				wl_cfg80211_bt_setflag(btcx_inf->dev, FALSE);
++			btcx_inf->bt_state = BT_DHCP_IDLE;
++			btcx_inf->timer_on = 0;
++			break;
++	}
++
++	net_os_wake_unlock(btcx_inf->dev);
++}
++
++void* wl_cfg80211_btcoex_init(struct net_device *ndev)
++{
++	struct btcoex_info *btco_inf = NULL;
++
++	btco_inf = kmalloc(sizeof(struct btcoex_info), GFP_KERNEL);
++	if (!btco_inf)
++		return NULL;
++
++	btco_inf->bt_state = BT_DHCP_IDLE;
++	btco_inf->ts_dhcp_start = 0;
++	btco_inf->ts_dhcp_ok = 0;
++	/* Set up timer for BT  */
++	btco_inf->timer_ms = 10;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++	timer_setup(&btco_inf->timer, wl_cfg80211_bt_timerfunc, 0);
++#else
++	init_timer(&btco_inf->timer);
++	btco_inf->timer.data = (ulong)btco_inf;
++	btco_inf->timer.function = wl_cfg80211_bt_timerfunc;
++#endif
++
++	btco_inf->dev = ndev;
++
++	INIT_WORK(&btco_inf->work, wl_cfg80211_bt_handler);
++
++	btcoex_info_loc = btco_inf;
++	return btco_inf;
++}
++
++void wl_cfg80211_btcoex_deinit()
++{
++	if (!btcoex_info_loc)
++		return;
++
++	if (btcoex_info_loc->timer_on) {
++		btcoex_info_loc->timer_on = 0;
++		del_timer_sync(&btcoex_info_loc->timer);
++	}
++
++	cancel_work_sync(&btcoex_info_loc->work);
++
++	kfree(btcoex_info_loc);
++}
++
++int wl_cfg80211_set_btcoex_dhcp(struct net_device *dev, dhd_pub_t *dhd, char *command)
++{
++
++	struct btcoex_info *btco_inf = btcoex_info_loc;
++	char powermode_val = 0;
++	char buf_reg66va_dhcp_on[8] = { 66, 00, 00, 00, 0x10, 0x27, 0x00, 0x00 };
++	char buf_reg41va_dhcp_on[8] = { 41, 00, 00, 00, 0x33, 0x00, 0x00, 0x00 };
++	char buf_reg68va_dhcp_on[8] = { 68, 00, 00, 00, 0x90, 0x01, 0x00, 0x00 };
++
++	uint32 regaddr;
++	static uint32 saved_reg66;
++	static uint32 saved_reg41;
++	static uint32 saved_reg68;
++	static bool saved_status = FALSE;
++
++	char buf_flag7_default[8] =   { 7, 00, 00, 00, 0x0, 0x00, 0x00, 0x00};
++
++	/* Figure out powermode 1 or o command */
++	strncpy((char *)&powermode_val, command + strlen("BTCOEXMODE") +1, 1);
++
++	if (strnicmp((char *)&powermode_val, "1", strlen("1")) == 0) {
++		WL_TRACE_HW4(("DHCP session starts\n"));
++
++
++#ifdef PKT_FILTER_SUPPORT
++		dhd->dhcp_in_progress = 1;
++
++		if (dhd->early_suspended) {
++			WL_TRACE_HW4(("DHCP in progressing , disable packet filter!!!\n"));
++			dhd_enable_packet_filter(0, dhd);
++		}
++#endif
++
++		/* Retrieve and saved orig regs value */
++		if ((saved_status == FALSE) &&
++			(!dev_wlc_intvar_get_reg(dev, "btc_params", 66,  &saved_reg66)) &&
++			(!dev_wlc_intvar_get_reg(dev, "btc_params", 41,  &saved_reg41)) &&
++			(!dev_wlc_intvar_get_reg(dev, "btc_params", 68,  &saved_reg68)))   {
++				saved_status = TRUE;
++				WL_TRACE(("Saved 0x%x 0x%x 0x%x\n",
++					saved_reg66, saved_reg41, saved_reg68));
++
++				/* Disable PM mode during dhpc session */
++
++				/* Disable PM mode during dhpc session */
++				/* Start  BT timer only for SCO connection */
++				if (btcoex_is_sco_active(dev)) {
++					/* btc_params 66 */
++					dev_wlc_bufvar_set(dev, "btc_params",
++						(char *)&buf_reg66va_dhcp_on[0],
++						sizeof(buf_reg66va_dhcp_on));
++					/* btc_params 41 0x33 */
++					dev_wlc_bufvar_set(dev, "btc_params",
++						(char *)&buf_reg41va_dhcp_on[0],
++						sizeof(buf_reg41va_dhcp_on));
++					/* btc_params 68 0x190 */
++					dev_wlc_bufvar_set(dev, "btc_params",
++						(char *)&buf_reg68va_dhcp_on[0],
++						sizeof(buf_reg68va_dhcp_on));
++					saved_status = TRUE;
++
++					btco_inf->bt_state = BT_DHCP_START;
++					btco_inf->timer_on = 1;
++					mod_timer(&btco_inf->timer, btco_inf->timer.expires);
++					WL_TRACE(("enable BT DHCP Timer\n"));
++				}
++		}
++		else if (saved_status == TRUE) {
++			WL_ERR(("was called w/o DHCP OFF. Continue\n"));
++		}
++	}
++	else if (strnicmp((char *)&powermode_val, "2", strlen("2")) == 0) {
++
++
++
++#ifdef PKT_FILTER_SUPPORT
++		dhd->dhcp_in_progress = 0;
++		WL_TRACE_HW4(("DHCP is complete \n"));
++
++		/* Enable packet filtering */
++		if (dhd->early_suspended) {
++			WL_TRACE_HW4(("DHCP is complete , enable packet filter!!!\n"));
++			dhd_enable_packet_filter(1, dhd);
++		}
++#endif /* PKT_FILTER_SUPPORT */
++
++		/* Restoring PM mode */
++
++		/* Stop any bt timer because DHCP session is done */
++		WL_TRACE(("disable BT DHCP Timer\n"));
++		if (btco_inf->timer_on) {
++			btco_inf->timer_on = 0;
++			del_timer_sync(&btco_inf->timer);
++
++			if (btco_inf->bt_state != BT_DHCP_IDLE) {
++			/* need to restore original btc flags & extra btc params */
++				WL_TRACE(("bt->bt_state:%d\n", btco_inf->bt_state));
++				/* wake up btcoex thread to restore btlags+params  */
++				schedule_work(&btco_inf->work);
++			}
++		}
++
++		/* Restoring btc_flag paramter anyway */
++		if (saved_status == TRUE)
++			dev_wlc_bufvar_set(dev, "btc_flags",
++				(char *)&buf_flag7_default[0], sizeof(buf_flag7_default));
++
++		/* Restore original values */
++		if (saved_status == TRUE) {
++			regaddr = 66;
++			dev_wlc_intvar_set_reg(dev, "btc_params",
++				(char *)&regaddr, (char *)&saved_reg66);
++			regaddr = 41;
++			dev_wlc_intvar_set_reg(dev, "btc_params",
++				(char *)&regaddr, (char *)&saved_reg41);
++			regaddr = 68;
++			dev_wlc_intvar_set_reg(dev, "btc_params",
++				(char *)&regaddr, (char *)&saved_reg68);
++
++			WL_TRACE(("restore regs {66,41,68} <- 0x%x 0x%x 0x%x\n",
++				saved_reg66, saved_reg41, saved_reg68));
++		}
++		saved_status = FALSE;
++
++	}
++	else {
++		WL_ERR(("Unkwown yet power setting, ignored\n"));
++	}
++
++	snprintf(command, 3, "OK");
++
++	return (strlen("OK"));
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgnan.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgnan.c
+new file mode 100644
+index 000000000..16ff88521
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgnan.c
+@@ -0,0 +1,2126 @@
++/*
++ * Neighbor Awareness Networking
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfgnan.c 559906 2015-05-29 02:42:35Z $
++ */
++
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <bcmwifi_channels.h>
++#include <proto/nan.h>
++
++#include <wl_cfg80211.h>
++#include <wl_android.h>
++#include <wl_cfgnan.h>
++
++#ifdef WL_NAN_DEBUG
++static u8 g_nan_debug = true;
++#endif /* WL_NAN_DEBUG */
++
++static nan_cmd_t nan_cmds [] = {
++	{ "NAN_START", wl_cfgnan_start_handler },
++	{ "NAN_STOP", wl_cfgnan_stop_handler },
++	{ "NAN_SUPPORT", wl_cfgnan_support_handler },
++	{ "NAN_STATUS", wl_cfgnan_status_handler },
++	{ "NAN_PUBLISH", wl_cfgnan_pub_handler },
++	{ "NAN_SUBSCRIBE", wl_cfgnan_sub_handler },
++	{ "NAN_CANCEL_PUBLISH", wl_cfgnan_cancel_pub_handler },
++	{ "NAN_CANCEL_SUBSCRIBE", wl_cfgnan_cancel_sub_handler },
++	{ "NAN_TRANSMIT", wl_cfgnan_transmit_handler },
++	{ "NAN_SET_CONFIG", wl_cfgnan_set_config_handler },
++	{ "NAN_GET_CONFIG", NULL },
++	{ "NAN_RTT_CONFIG", wl_cfgnan_rtt_config_handler },
++	{ "NAN_RTT_FIND", wl_cfgnan_rtt_find_handler },
++#ifdef WL_NAN_DEBUG
++	{ "NAN_DEBUG", wl_cfgnan_debug_handler },
++#endif /* WL_NAN_DEBUG */
++#ifdef NAN_P2P_CONFIG
++	{ "NAN_ADD_CONF", wl_cfgnan_p2p_ie_add_handler },
++	{ "NAN_ENABLE_CONF", wl_cfgnan_p2p_ie_enable_handler },
++	{ "NAN_DEL_CONF", wl_cfgnan_p2p_ie_del_handler },
++#endif /* NAN_P2P_CONFIG */
++	{ NULL, NULL },
++};
++
++static nan_config_attr_t nan_config_attrs [] = {
++	{ "ATTR_MASTER", WL_NAN_XTLV_MASTER_PREF },
++	{ "ATTR_ID", WL_NAN_XTLV_CLUSTER_ID },
++	{ "ATTR_ADDR", WL_NAN_XTLV_IF_ADDR },
++	{ "ATTR_ROLE", WL_NAN_XTLV_ROLE },
++	{ "ATTR_BCN_INT", WL_NAN_XTLV_BCN_INTERVAL },
++	{ "ATTR_CHAN", WL_NAN_XTLV_MAC_CHANSPEC },
++	{ "ATTR_TX_RATE", WL_NAN_XTLV_MAC_TXRATE },
++	{ "ATTR_DW_LEN", WL_NAN_XTLV_DW_LEN },
++	{ {0}, 0 }
++};
++
++#ifdef WL_NAN_DEBUG
++void print_event_name(u32 event_num)
++{
++	char *event_name = NULL;
++
++	switch (event_num) {
++	case WL_NAN_EVENT_START:
++		event_name = NAME_TO_STR(WL_NAN_EVENT_START);
++		break;
++	case WL_NAN_EVENT_JOIN:
++		event_name = NAME_TO_STR(WL_NAN_EVENT_JOIN);
++		break;
++	case WL_NAN_EVENT_ROLE:
++		event_name = NAME_TO_STR(WL_NAN_EVENT_ROLE);
++		break;
++	case WL_NAN_EVENT_SCAN_COMPLETE:
++		event_name = NAME_TO_STR(WL_NAN_EVENT_SCAN_COMPLETE);
++		break;
++	case WL_NAN_EVENT_DISCOVERY_RESULT:
++		event_name = NAME_TO_STR(WL_NAN_EVENT_DISCOVERY_RESULT);
++		break;
++	case WL_NAN_EVENT_REPLIED:
++		event_name = NAME_TO_STR(WL_NAN_EVENT_REPLIED);
++		break;
++	case WL_NAN_EVENT_TERMINATED:
++		event_name = NAME_TO_STR(WL_NAN_EVENT_TERMINATED);
++		break;
++	case WL_NAN_EVENT_RECEIVE:
++		event_name = NAME_TO_STR(WL_NAN_EVENT_RECEIVE);
++		break;
++	case WL_NAN_EVENT_STATUS_CHG:
++		event_name = NAME_TO_STR(WL_NAN_EVENT_STATUS_CHG);
++		break;
++	case WL_NAN_EVENT_MERGE:
++		event_name = NAME_TO_STR(WL_NAN_EVENT_MERGE);
++		break;
++	case WL_NAN_EVENT_STOP:
++		event_name = NAME_TO_STR(WL_NAN_EVENT_STOP);
++		break;
++	case WL_NAN_EVENT_P2P:
++		event_name = NAME_TO_STR(WL_NAN_EVENT_P2P);
++		break;
++	case WL_NAN_EVENT_WINDOW_BEGIN_P2P:
++		event_name = NAME_TO_STR(WL_NAN_EVENT_WINDOW_BEGIN_P2P);
++		break;
++	case WL_NAN_EVENT_WINDOW_BEGIN_MESH:
++		event_name = NAME_TO_STR(WL_NAN_EVENT_WINDOW_BEGIN_MESH);
++		break;
++	case WL_NAN_EVENT_WINDOW_BEGIN_IBSS:
++		event_name = NAME_TO_STR(WL_NAN_EVENT_WINDOW_BEGIN_IBSS);
++		break;
++	case WL_NAN_EVENT_WINDOW_BEGIN_RANGING:
++		event_name = NAME_TO_STR(WL_NAN_EVENT_WINDOW_BEGIN_RANGING);
++		break;
++	case WL_NAN_EVENT_INVALID:
++		event_name = NAME_TO_STR(WL_NAN_EVENT_INVALID);
++		break;
++	default:
++		break;
++	}
++	if (event_name) {
++		WL_DBG((" event name: %s \n", event_name));
++	} else {
++		WL_DBG(("Unknown event %d\n", event_num));
++	}
++}
++#endif /* WL_NAN_DEBUG */
++
++int
++wl_cfgnan_set_vars_cbfn(void *ctx, uint8 *buf, uint16 type, uint16 len)
++{
++	wl_nan_tlv_data_t *ndata = ((wl_nan_tlv_data_t *)(ctx));
++	int ret = BCME_OK;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++
++	WL_DBG((" enter, xtlv_type: 0x%x \n", type));
++
++	switch (type) {
++	case WL_NAN_XTLV_ENABLED:
++		memcpy(&ndata->enabled, buf, len);
++		break;
++	case WL_NAN_XTLV_MASTER_PREF:
++		/*
++		 * master role and preference  mac has them as two u8's,
++		 *
++		 * masterpref: val & 0x0ff
++		 * rnd_factor: val >> 8
++		 */
++		memcpy(&ndata->master_pref, buf, len);
++		break;
++	case WL_NAN_XTLV_IF_ADDR:
++		memcpy(&ndata->mac_addr, buf, len);
++		break;
++	case WL_NAN_XTLV_CLUSTER_ID:
++		memcpy(&ndata->clus_id, buf, len);
++		break;
++	case WL_NAN_XTLV_ROLE:
++		/*  nan device role, master, master-sync nosync etc  */
++		memcpy(&ndata->dev_role, buf, len);
++		break;
++	case WL_NAN_XTLV_MAC_CHANSPEC:
++		memcpy(&ndata->chanspec, buf, len);
++		if (wf_chspec_valid(ndata->chanspec)) {
++			wf_chspec_ntoa(ndata->chanspec, buf);
++			WL_DBG((" chanspec: %s 0x%x \n", buf, ndata->chanspec));
++		} else {
++			WL_DBG((" chanspec: 0x%x is not valid \n", ndata->chanspec));
++		}
++		break;
++	case WL_NAN_XTLV_MAC_AMR:
++		memcpy(ndata->amr, buf, len);
++		break;
++	case WL_NAN_XTLV_MAC_AMBTT:
++		memcpy(&ndata->ambtt, buf, len);
++		break;
++	case WL_NAN_XTLV_MAC_HOPCNT:
++		memcpy(&ndata->hop_count, buf, len);
++		break;
++	case WL_NAN_XTLV_INSTANCE_ID:
++		memcpy(&ndata->inst_id, buf, len);
++		break;
++	case WL_NAN_XTLV_SVC_NAME:
++		memcpy(ndata->svc_name, buf, len);
++		break;
++	case WL_NAN_XTLV_SVC_PARAMS:
++		memcpy(&ndata->params, buf, len);
++		break;
++	case WL_NAN_XTLV_MAC_STATUS:
++		memcpy(&ndata->nstatus, buf, len);
++		break;
++	case WL_NAN_XTLV_PUBLR_ID:
++		memcpy(&ndata->pub_id, buf, len);
++		break;
++	case WL_NAN_XTLV_SUBSCR_ID:
++		memcpy(&ndata->sub_id, buf, len);
++		break;
++	case WL_NAN_XTLV_MAC_ADDR:
++		memcpy(&ndata->mac_addr, buf, len);
++		break;
++	case WL_NAN_XTLV_VNDR:
++		ndata->vend_info.dlen = len;
++		ndata->vend_info.data = kzalloc(ndata->vend_info.dlen, kflags);
++		if (!ndata->vend_info.data) {
++			WL_ERR((" memory allocation failed \n"));
++			ret = -ENOMEM;
++			goto fail;
++		}
++		if (ndata->vend_info.data && ndata->vend_info.dlen) {
++			memcpy(ndata->vend_info.data, buf, len);
++		}
++		break;
++	case WL_NAN_XTLV_SVC_INFO:
++		ndata->svc_info.dlen = len;
++		ndata->svc_info.data = kzalloc(ndata->svc_info.dlen, kflags);
++		if (!ndata->svc_info.data) {
++			WL_ERR((" memory allocation failed \n"));
++			ret = -ENOMEM;
++			goto fail;
++		}
++		if (ndata->svc_info.data && ndata->svc_info.dlen) {
++			memcpy(ndata->svc_info.data, buf, len);
++		}
++		break;
++	case WL_NAN_XTLV_PEER_INSTANCE_ID:
++		memcpy(&ndata->peer_inst_id, buf, len);
++		break;
++	case WL_NAN_XTLV_NAN_SCANPARAMS:
++		memcpy(&ndata->scan_params, buf, len);
++		break;
++	case WL_NAN_XTLV_ZERO:
++		/* don't parse empty space in the buffer */
++		ret = BCME_ERROR;
++		break;
++
++	default:
++		break;
++	}
++
++fail:
++	return ret;
++}
++
++int
++wl_cfgnan_enable_events(struct net_device *ndev, struct bcm_cfg80211 *cfg)
++{
++	wl_nan_ioc_t *nanioc = NULL;
++	uint8 *pxtlv;
++	u32 event_mask = 0;
++	s32 ret = BCME_OK;
++	u16 start, end;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	uint16 nanioc_size = sizeof(wl_nan_ioc_t) + NAN_IOCTL_BUF_SIZE;
++
++	nanioc = kzalloc(nanioc_size, kflags);
++	if (!nanioc) {
++		WL_ERR((" memory allocation failed \n"));
++		return -ENOMEM;
++	}
++
++	ret = wl_add_remove_eventmsg(ndev, WLC_E_NAN, true);
++	if (unlikely(ret)) {
++		WL_ERR((" nan event enable failed, error = %d \n", ret));
++		goto fail;
++	}
++#ifdef WL_NAN_DEBUG
++	if (g_nan_debug) {
++		/* enable all nan events */
++		event_mask = NAN_EVENT_MASK_ALL;
++	} else
++#endif /* WL_NAN_DEBUG */
++	{
++		/* enable only selected nan events to avoid unnecessary host wake up */
++		event_mask |= NAN_EVENT_BIT(WL_NAN_EVENT_START);
++		event_mask |= NAN_EVENT_BIT(WL_NAN_EVENT_JOIN);
++		event_mask |= NAN_EVENT_BIT(WL_NAN_EVENT_DISCOVERY_RESULT);
++		event_mask |= NAN_EVENT_BIT(WL_NAN_EVENT_RECEIVE);
++		event_mask |= NAN_EVENT_BIT(WL_NAN_EVENT_TERMINATED);
++		event_mask |= NAN_EVENT_BIT(WL_NAN_EVENT_STOP);
++		event_mask |= NAN_EVENT_BIT(WL_NAN_EVENT_CLEAR_BIT);
++#ifdef NAN_P2P_CONFIG
++		event_mask |= NAN_EVENT_BIT(WL_NAN_EVENT_P2P);
++#endif /* NAN_P2P_CONFIG */
++		event_mask = htod32(event_mask);
++	}
++
++	start = end = NAN_IOCTL_BUF_SIZE;
++	nanioc->version = htod16(WL_NAN_IOCTL_VERSION);
++	nanioc->id = htod16(WL_NAN_CMD_EVENT_MASK);
++	pxtlv = nanioc->data;
++	ret = bcm_pack_xtlv_entry(&pxtlv, &end, WL_NAN_XTLV_EVENT_MASK,
++		sizeof(event_mask), &event_mask, BCM_XTLV_OPTION_ALIGN32);
++	if (unlikely(ret)) {
++		goto fail;
++	}
++	nanioc->len = start - end;
++	nanioc_size = sizeof(wl_nan_ioc_t) + nanioc->len;
++	ret = wldev_iovar_setbuf(ndev, "nan", nanioc, nanioc_size,
++		cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	if (unlikely(ret)) {
++		WL_ERR((" nan event selective enable failed, error = %d \n", ret));
++		goto fail;
++	} else {
++		WL_DBG((" nan event selective enable successful \n"));
++	}
++
++	ret = wl_add_remove_eventmsg(ndev, WLC_E_PROXD, true);
++	if (unlikely(ret)) {
++		WL_ERR((" proxd event enable failed, error = %d \n", ret));
++		goto fail;
++	}
++
++fail:
++	if (nanioc) {
++		kfree(nanioc);
++	}
++
++	return ret;
++}
++
++int
++wl_cfgnan_enable_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, nan_cmd_data_t *cmd_data)
++{
++	wl_nan_ioc_t *nanioc = NULL;
++	uint8 *pxtlv;
++	s32 ret = BCME_OK;
++	u16 start, end;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	uint16 nanioc_size = sizeof(wl_nan_ioc_t) + NAN_IOCTL_BUF_SIZE;
++	uint8 val;
++
++	nanioc = kzalloc(nanioc_size, kflags);
++	if (!nanioc) {
++		WL_ERR((" memory allocation failed \n"));
++		return -ENOMEM;
++	}
++
++	/*
++	 * command to test
++	 *
++	 * wl: wl nan 1
++	 *
++	 * wpa_cli: DRIVER NAN_ENABLE
++	 */
++
++	/* nan enable */
++	val = 1;
++	start = end = NAN_IOCTL_BUF_SIZE;
++	nanioc->version = htod16(WL_NAN_IOCTL_VERSION);
++	nanioc->id = htod16(WL_NAN_CMD_ENABLE);
++	pxtlv = nanioc->data;
++	ret = bcm_pack_xtlv_entry(&pxtlv, &end, WL_NAN_XTLV_ENABLED,
++		sizeof(val), &val, BCM_XTLV_OPTION_ALIGN32);
++	if (unlikely(ret)) {
++		goto fail;
++	}
++	nanioc->len = start - end;
++	nanioc_size = sizeof(wl_nan_ioc_t) + nanioc->len;
++	ret = wldev_iovar_setbuf(ndev, "nan", nanioc, nanioc_size,
++		cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	if (unlikely(ret)) {
++		WL_ERR((" nan enable failed, error = %d \n", ret));
++		goto fail;
++	} else {
++		cfg->nan_enable = true;
++		WL_DBG((" nan enable successful \n"));
++	}
++
++	/* enable nan events */
++	ret = wl_cfgnan_enable_events(ndev, cfg);
++	if (unlikely(ret)) {
++		goto fail;
++	}
++
++fail:
++	if (nanioc) {
++		kfree(nanioc);
++	}
++
++	return ret;
++}
++
++int
++wl_cfgnan_start_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data)
++{
++	wl_nan_ioc_t *nanioc = NULL;
++	struct ether_addr cluster_id = ether_null;
++	uint8 *pxtlv;
++	s32 ret = BCME_OK;
++	u16 start, end;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	uint16 nanioc_size = sizeof(wl_nan_ioc_t) + NAN_IOCTL_BUF_SIZE;
++	uint8 val;
++
++	if (cfg->nan_enable != true) {
++		ret = wl_cfgnan_enable_handler(ndev, cfg, cmd, cmd_data);
++		if (unlikely(ret)) {
++			goto fail;
++		}
++	}
++
++	/*
++	 * command to test
++	 *
++	 * wl: wl nan join -start
++	 *
++	 * wpa_cli: DRIVER NAN_START
++	 */
++
++	/* nan join */
++	nanioc = kzalloc(nanioc_size, kflags);
++	if (!nanioc) {
++		WL_ERR((" memory allocation failed \n"));
++		return -ENOMEM;
++	}
++
++	val = 1;
++	start = end = NAN_IOCTL_BUF_SIZE;
++	nanioc->version = htod16(WL_NAN_IOCTL_VERSION);
++	nanioc->id = htod16(WL_NAN_CMD_NAN_JOIN);
++	pxtlv = nanioc->data;
++	ret = bcm_pack_xtlv_entry(&pxtlv, &end, WL_NAN_XTLV_CLUSTER_ID,
++		ETHER_ADDR_LEN, &cluster_id, BCM_XTLV_OPTION_ALIGN32);
++	if (unlikely(ret)) {
++		goto fail;
++	}
++	ret = bcm_pack_xtlv_entry(&pxtlv, &end, WL_NAN_XTLV_START,
++		sizeof(val), &val, BCM_XTLV_OPTION_ALIGN32);
++	if (unlikely(ret)) {
++		goto fail;
++	}
++	nanioc->len = start - end;
++	nanioc_size = sizeof(wl_nan_ioc_t) + nanioc->len;
++	ret = wldev_iovar_setbuf(ndev, "nan", nanioc, nanioc_size,
++		cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	if (unlikely(ret)) {
++		WL_ERR((" nan join failed, error = %d \n", ret));
++		goto fail;
++	}
++
++	WL_DBG((" nan join successful \n"));
++	cfg->nan_running = true;
++
++fail:
++	if (nanioc) {
++		kfree(nanioc);
++	}
++
++	return ret;
++}
++
++int
++wl_cfgnan_stop_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data)
++{
++	wl_nan_ioc_t *nanioc = NULL;
++	struct ether_addr cluster_id = ether_null;
++	uint8 *pxtlv;
++	s32 ret = BCME_OK;
++	u16 start, end;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	uint16 nanioc_size = sizeof(wl_nan_ioc_t) + NAN_IOCTL_BUF_SIZE;
++	uint8 nan_enable = FALSE;
++
++	/*
++	 * command to test
++	 *
++	 * wl: wl nan stop
++	 *     wl nan 0
++	 *
++	 * wpa_cli: DRIVER NAN_STOP
++	 */
++
++	nanioc = kzalloc(nanioc_size, kflags);
++	if (!nanioc) {
++		WL_ERR((" memory allocation failed \n"));
++		return -ENOMEM;
++	}
++
++	if (cfg->nan_running == true) {
++		/* nan stop */
++
++		start = end = NAN_IOCTL_BUF_SIZE;
++		nanioc->version = htod16(WL_NAN_IOCTL_VERSION);
++		nanioc->id = htod16(WL_NAN_CMD_STOP);
++		pxtlv = nanioc->data;
++		ret = bcm_pack_xtlv_entry(&pxtlv, &end, WL_NAN_XTLV_CLUSTER_ID,
++			ETHER_ADDR_LEN, &cluster_id, BCM_XTLV_OPTION_ALIGN32);
++		if (unlikely(ret)) {
++			goto fail;
++		}
++		nanioc->len = start - end;
++		nanioc_size = sizeof(wl_nan_ioc_t) + nanioc->len;
++		ret = wldev_iovar_setbuf(ndev, "nan", nanioc, nanioc_size,
++			cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++		if (unlikely(ret)) {
++			WL_ERR((" nan stop failed, error = %d \n", ret));
++			goto fail;
++		} else {
++			cfg->nan_running = false;
++			WL_DBG((" nan stop successful \n"));
++		}
++	}
++
++	/* nan disable */
++	if (cfg->nan_enable == true) {
++		memset(nanioc, 0, nanioc_size);
++		start = end = NAN_IOCTL_BUF_SIZE;
++		nanioc->version = htod16(WL_NAN_IOCTL_VERSION);
++		nanioc->id = htod16(WL_NAN_CMD_ENABLE);
++		pxtlv = nanioc->data;
++		ret = bcm_pack_xtlv_entry(&pxtlv, &end, WL_NAN_XTLV_ENABLED,
++			sizeof(nan_enable), &nan_enable, BCM_XTLV_OPTION_ALIGN32);
++		if (unlikely(ret)) {
++			goto fail;
++		}
++		nanioc->len = start - end;
++		nanioc_size = sizeof(wl_nan_ioc_t) + nanioc->len;
++		ret = wldev_iovar_setbuf(ndev, "nan", nanioc, nanioc_size,
++			cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++		if (unlikely(ret)) {
++			WL_ERR((" nan disable failed, error = %d \n", ret));
++			goto fail;
++		} else {
++			cfg->nan_enable = false;
++			WL_DBG((" nan disable successful \n"));
++		}
++	}
++
++fail:
++	if (nanioc) {
++		kfree(nanioc);
++	}
++
++	return ret;
++}
++
++int
++wl_cfgnan_support_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data)
++{
++	wl_nan_ioc_t *nanioc = NULL;
++	uint8 *pxtlv;
++	s32 ret = BCME_OK;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	uint16 nanioc_size = sizeof(wl_nan_ioc_t) + NAN_IOCTL_BUF_SIZE;
++
++	nanioc = kzalloc(nanioc_size, kflags);
++	if (!nanioc) {
++		WL_ERR((" memory allocation failed \n"));
++		return -ENOMEM;
++	}
++
++	/*
++	 * command to test
++	 *
++	 * wl: wl nan
++	 *
++	 * wpa_cli: DRIVER NAN_SUPPORT
++	 */
++
++	/* nan support */
++	nanioc->version = htod16(WL_NAN_IOCTL_VERSION);
++	nanioc->id = htod16(WL_NAN_CMD_ENABLE);
++	pxtlv = nanioc->data;
++	nanioc->len = htod16(BCM_XTLV_HDR_SIZE + 1);
++	nanioc_size = sizeof(wl_nan_ioc_t) + sizeof(bcm_xtlv_t);
++	ret = wldev_iovar_getbuf(ndev, "nan", nanioc, nanioc_size,
++		cfg->ioctl_buf, WLC_IOCTL_SMLEN, &cfg->ioctl_buf_sync);
++	if (unlikely(ret)) {
++		WL_ERR((" nan is not supported, error = %d \n", ret));
++		goto fail;
++	} else {
++		WL_DBG((" nan is supported \n"));
++	}
++
++fail:
++	if (nanioc) {
++		kfree(nanioc);
++	}
++
++	return ret;
++}
++
++int
++wl_cfgnan_status_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data)
++{
++	wl_nan_ioc_t *nanioc = NULL;
++	wl_nan_ioc_t *ioc_ret = NULL;
++	char *ptr = cmd;
++	char *end = cmd + size;
++	wl_nan_tlv_data_t tlv_data;
++	s32 ret = BCME_OK;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	uint16 nanioc_size = sizeof(wl_nan_ioc_t) + NAN_IOCTL_BUF_SIZE;
++
++	nanioc = kzalloc(nanioc_size, kflags);
++	if (!nanioc) {
++		WL_ERR((" memory allocation failed \n"));
++		return -ENOMEM;
++	}
++
++	/*
++	 * command to test
++	 *
++	 * wl: wl nan status
++	 *
++	 * wpa_cli: DRIVER NAN_STATUS
++	 */
++
++	/* nan status */
++	nanioc->version = htod16(WL_NAN_IOCTL_VERSION);
++	nanioc->id = htod16(WL_NAN_CMD_STATUS);
++	nanioc->len = NAN_IOCTL_BUF_SIZE;
++	nanioc_size = sizeof(wl_nan_ioc_t) + sizeof(bcm_xtlv_t);
++	ret = wldev_iovar_getbuf(ndev, "nan", nanioc, nanioc_size,
++		cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	if (unlikely(ret)) {
++		WL_ERR((" nan status failed, error = %d \n", ret));
++		goto fail;
++	} else {
++		WL_DBG((" nan status successful \n"));
++	}
++
++	/* unpack the tlvs */
++	memset(&tlv_data, 0, sizeof(tlv_data));
++	ioc_ret = (wl_nan_ioc_t *)cfg->ioctl_buf;
++	if (!ioc_ret) {
++		goto fail;
++	}
++#ifdef WL_NAN_DEBUG
++	if (g_nan_debug) {
++		prhex(" nanioc->data: ", (uint8 *)ioc_ret->data, ioc_ret->len);
++	}
++#endif /* WL_NAN_DEBUG */
++	bcm_unpack_xtlv_buf(&tlv_data, ioc_ret->data, ioc_ret->len,
++		BCM_XTLV_OPTION_ALIGN32, wl_cfgnan_set_vars_cbfn);
++
++	ptr += snprintf(ptr, end-ptr, ROLE_PREFIX"%d", tlv_data.dev_role);
++	ptr += snprintf(ptr, end-ptr, " " AMR_PREFIX);
++	ptr += bcm_format_hex(ptr, tlv_data.amr, NAN_MASTER_RANK_LEN);
++	ptr += snprintf(ptr, end-ptr, " " CLUS_ID_PREFIX MACF, ETHER_TO_MACF(tlv_data.clus_id));
++	ptr += snprintf(ptr, end-ptr, " " AMBTT_PREFIX"0x%x", tlv_data.ambtt);
++	ptr += snprintf(ptr, end-ptr, " " HOP_COUNT_PREFIX"%d", tlv_data.hop_count);
++
++	/* nan scan param */
++	nanioc->version = htod16(WL_NAN_IOCTL_VERSION);
++	nanioc->id = htod16(WL_NAN_CMD_SCAN_PARAMS);
++	nanioc->len = NAN_IOCTL_BUF_SIZE;
++	nanioc_size = sizeof(wl_nan_ioc_t) + sizeof(bcm_xtlv_t);
++	ret = wldev_iovar_getbuf(ndev, "nan", nanioc, nanioc_size,
++		cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	if (unlikely(ret)) {
++		WL_ERR((" nan scan params failed, error = %d \n", ret));
++		goto fail;
++	} else {
++		WL_DBG((" nan scan params successful \n"));
++	}
++
++	if (tlv_data.svc_info.data) {
++		kfree(tlv_data.svc_info.data);
++		tlv_data.svc_info.data = NULL;
++		tlv_data.svc_info.dlen = 0;
++	}
++	if (tlv_data.vend_info.data) {
++		kfree(tlv_data.vend_info.data);
++		tlv_data.vend_info.data = NULL;
++		tlv_data.vend_info.dlen = 0;
++	}
++	/* unpack the tlvs */
++	memset(&tlv_data, 0, sizeof(tlv_data));
++	ioc_ret = (wl_nan_ioc_t *)cfg->ioctl_buf;
++	ASSERT(ioc_ret != NULL);
++#ifdef WL_NAN_DEBUG
++	if (g_nan_debug) {
++		prhex(" nanioc->data: ", (uint8 *)ioc_ret->data, ioc_ret->len);
++	}
++#endif /* WL_NAN_DEBUG */
++	bcm_unpack_xtlv_buf(&tlv_data, ioc_ret->data, ioc_ret->len,
++		BCM_XTLV_OPTION_ALIGN32, wl_cfgnan_set_vars_cbfn);
++
++	ptr += snprintf(ptr, end-ptr, " " SCAN_PERIOD_PREFIX"%d",
++		tlv_data.scan_params.ms_dur);
++	ptr += snprintf(ptr, end-ptr, " " SCAN_INTERVAL_PREFIX"%d",
++		tlv_data.scan_params.ms_intvl*512);
++
++	if (ptr > end) {
++		WL_ERR(("Buffer overflow. userspace string truncated: %s, len: %zu\n",
++			cmd, strlen(cmd)));
++	}
++
++	WL_DBG((" formatted string for userspace: %s, len: %zu \n",
++		cmd, strlen(cmd)));
++
++fail:
++	if (nanioc) {
++		kfree(nanioc);
++	}
++	if (tlv_data.svc_info.data) {
++		kfree(tlv_data.svc_info.data);
++		tlv_data.svc_info.data = NULL;
++		tlv_data.svc_info.dlen = 0;
++	}
++	if (tlv_data.vend_info.data) {
++		kfree(tlv_data.vend_info.data);
++		tlv_data.vend_info.data = NULL;
++		tlv_data.vend_info.dlen = 0;
++	}
++
++	return ret;
++}
++
++
++#ifdef NAN_P2P_CONFIG
++
++static void
++wl_p2p_nan_ioctl_make_header(wl_p2p_nan_ioc_t *p2p_nanioc, uint16 cmd_id, uint16 len)
++{
++	p2p_nanioc->version = htod16(WL_P2P_NAN_IOCTL_VERSION);
++	p2p_nanioc->id = cmd_id;
++	p2p_nanioc->len = htod16(len);
++}
++
++static int
++wl_p2p_nan_do_get_ioctl(struct net_device *ndev, struct bcm_cfg80211 *cfg,
++	wl_p2p_nan_ioc_t *p2p_nanioc, uint16 alloc_size)
++{
++	wl_p2p_nan_ioc_t *iocresp = NULL;
++	int res;
++	uint8 *val;
++	/*  send getbuf p2p nan iovar */
++	res = wldev_iovar_getbuf(ndev, "p2p_nan", p2p_nanioc, alloc_size,
++		cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++
++	if (res == BCME_OK) {
++		iocresp = (wl_p2p_nan_ioc_t *)cfg->ioctl_buf;
++		if (iocresp == NULL) {
++			res = BCME_ERROR;
++			return res;
++		}
++		switch (iocresp->id) {
++			case WL_P2P_NAN_CMD_ENABLE:
++				val = iocresp->data;
++				WL_ERR(("wl p2p_nan status is %s\n",
++					*val == 1? "Enabled":"Disabled"));
++				break;
++			case WL_P2P_NAN_CMD_CONFIG: {
++				wl_p2p_nan_config_t *p_p2p_nan_cfg =
++					(wl_p2p_nan_config_t *)iocresp->data;
++				WL_ERR(("wl p2p nan ie len = %u\n", p_p2p_nan_cfg->ie_len));
++				prhex("P2P IE", p_p2p_nan_cfg->ie, p_p2p_nan_cfg->ie_len);
++			}
++			break;
++			default:
++			WL_ERR(("Unknown command %d\n", iocresp->id));
++			break;
++		}
++	}
++	return res;
++}
++
++
++int wl_cfgnan_p2p_ie_enable_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char* buf, int size, nan_cmd_data_t *cmd_data)
++{
++	int res = BCME_OK;
++	wl_p2p_nan_ioc_t *p2p_nanioc;
++	uint16 alloc_size = OFFSETOF(wl_p2p_nan_ioc_t, data) + P2P_NAN_IOC_BUFSZ;
++	void *pdata = NULL;
++	uint8 val;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	p2p_nanioc = kzalloc(alloc_size, kflags);
++	if (p2p_nanioc == NULL) {
++		WL_ERR((" memory allocation failed \n"));
++		return BCME_NOMEM;
++	}
++
++	wl_p2p_nan_ioctl_make_header(p2p_nanioc, WL_P2P_NAN_CMD_ENABLE, sizeof(uint8));
++
++	if (cmd_data->p2p_info.data == NULL) { /* get  */
++		res = wl_p2p_nan_do_get_ioctl(ndev, cfg, p2p_nanioc, alloc_size);
++	} else {	/* set */
++
++		val =  (uint8) cmd_data->p2p_info.data[0];
++		pdata = p2p_nanioc->data;
++		memcpy(pdata, &val, sizeof(uint8));
++		res = wldev_iovar_setbuf(ndev, "p2p_nan", p2p_nanioc,
++			alloc_size, cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	}
++
++	kfree(p2p_nanioc);
++	return res;
++}
++int wl_cfgnan_p2p_ie_add_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data)
++{
++	int res = BCME_OK;
++	int ie_len, data_len;
++	wl_p2p_nan_ioc_t *p2p_nanioc;
++	uint16 alloc_size = OFFSETOF(wl_p2p_nan_ioc_t, data) + cmd_data->p2p_info.dlen;
++	wl_p2p_nan_config_t *p_p2p_nan_cfg;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++
++	p2p_nanioc = kzalloc(alloc_size, kflags);
++	if (p2p_nanioc == NULL)
++		return BCME_NOMEM;
++
++	cmd_data->p2p_info.dlen /= 2;	/* Number of hex values will be half of ascii */
++	wl_p2p_nan_ioctl_make_header(p2p_nanioc, WL_P2P_NAN_CMD_CONFIG, P2P_NAN_IOC_BUFSZ);
++
++	if (cmd_data->p2p_info.data == NULL) { /* get */
++		wl_p2p_nan_do_get_ioctl(ndev, cfg, p2p_nanioc, alloc_size);
++	} else {
++		ie_len = cmd_data->p2p_info.dlen;
++		data_len = OFFSETOF(wl_p2p_nan_config_t, ie) + ie_len;
++
++		p_p2p_nan_cfg = (wl_p2p_nan_config_t *)p2p_nanioc->data;
++		p_p2p_nan_cfg->version = WL_P2P_NAN_CONFIG_VERSION;
++		p_p2p_nan_cfg->len = data_len;
++		p_p2p_nan_cfg->ie_len = ie_len;
++
++	if (!wl_cfg80211_hex_str_to_bin
++		(p_p2p_nan_cfg->ie, (int)p_p2p_nan_cfg->ie_len, (uchar*)cmd_data->p2p_info.data)) {
++		res = BCME_BADARG;
++		goto fail;
++	}
++	p2p_nanioc->len = htod16(data_len);
++
++	res = wldev_iovar_setbuf(ndev, "p2p_nan", p2p_nanioc, alloc_size,
++		cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	}
++fail:
++	kfree(p2p_nanioc);
++	return res;
++}
++int wl_cfgnan_p2p_ie_del_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data)
++{
++	int res = BCME_OK;
++	wl_p2p_nan_ioc_t *p2p_nanioc;
++	uint16 alloc_size = OFFSETOF(wl_p2p_nan_ioc_t, data);
++
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	p2p_nanioc = kzalloc(alloc_size, kflags);
++	if (p2p_nanioc == NULL) {
++		WL_ERR((" Memory is not enough\n"));
++		return BCME_NOMEM;
++	}
++	wl_p2p_nan_ioctl_make_header(p2p_nanioc, WL_P2P_NAN_CMD_DEL_CONFIG, 0);
++	res = wldev_iovar_setbuf(ndev, "p2p_nan", p2p_nanioc, alloc_size,
++		cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	kfree(p2p_nanioc);
++	return res;
++}
++
++#endif /* NAN_P2P_CONFIG */
++
++/*
++ *  packs user data (in hex string) into tlv record
++ *  advances tlv pointer to next xtlv slot
++ *  buflen is used for tlv_buf space check
++ */
++static int
++get_ie_data(uchar *data_str, uchar *ie_data, int len)
++{
++	uchar *src, *dest;
++	uchar val;
++	int idx;
++	char hexstr[3];
++
++	src = data_str;
++	dest = ie_data;
++
++	for (idx = 0; idx < len; idx++) {
++		hexstr[0] = src[0];
++		hexstr[1] = src[1];
++		hexstr[2] = '\0';
++
++#ifdef BCMDRIVER
++		val = (uchar) simple_strtoul(hexstr, NULL, 16);
++#else
++		val = (uchar) strtoul(hexstr, NULL, 16);
++#endif
++
++		*dest++ = val;
++		src += 2;
++	}
++
++	return 0;
++}
++
++int
++wl_cfgnan_pub_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data)
++{
++	wl_nan_ioc_t *nanioc = NULL;
++	wl_nan_disc_params_t params;
++	s32 ret = BCME_OK;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	uint16 nanioc_size = sizeof(wl_nan_ioc_t) + NAN_IOCTL_BUF_SIZE;
++	uint8 *pxtlv;
++	u16 start, end;
++	uchar *buf = NULL;
++
++	/*
++	 * proceed only if mandatory arguments are present - publisher id,
++	 * service hash
++	 */
++	if ((!cmd_data->pub_id) || (!cmd_data->svc_hash.data) ||
++		(!cmd_data->svc_hash.dlen)) {
++		WL_ERR((" mandatory arguments are not present \n"));
++		return -EINVAL;
++	}
++
++	nanioc = kzalloc(nanioc_size, kflags);
++	if (!nanioc) {
++		WL_ERR((" memory allocation failed \n"));
++		return -ENOMEM;
++	}
++
++	/*
++	 * command to test
++	 *
++	 * wl: wl nan publish 10 NAN123 -info <hex_string
++	 *     wl nan publish 10 NAN123 -info <hex_string -period 1 -ttl 0xffffffff
++	 *
++	 * wpa_cli: DRIVER NAN_PUBLISH PUB_ID=10 SVC_HASH=NAN123
++	 *          SVC_INFO=<hex_string>
++	 *          DRIVER NAN_PUBLISH PUB_ID=10 SVC_HASH=NAN123
++	 *          SVC_INFO=<hex_string> PUB_PR=1 PUB_INT=0xffffffff
++	 */
++
++	/* nan publish */
++	start = end = NAN_IOCTL_BUF_SIZE;
++	nanioc->version = htod16(WL_NAN_IOCTL_VERSION);
++	nanioc->id = htod16(WL_NAN_CMD_PUBLISH);
++	pxtlv = nanioc->data;
++
++	/* disovery parameters */
++	if (cmd_data->pub_pr) {
++		params.period = cmd_data->pub_pr;
++	} else {
++		params.period = 1;
++	}
++	if (cmd_data->pub_int) {
++		params.ttl = cmd_data->pub_int;
++	} else {
++		params.ttl = WL_NAN_TTL_UNTIL_CANCEL;
++	}
++	params.flags = 0;
++	if (cmd_data->flags & WL_NAN_PUB_UNSOLICIT) {
++		params.flags |= WL_NAN_PUB_UNSOLICIT;
++		WL_DBG((" nan publish type - unsolicited\n"));
++	}
++	if (cmd_data->flags & WL_NAN_PUB_SOLICIT) {
++		params.flags |= WL_NAN_PUB_SOLICIT;
++		WL_DBG((" nan publish type - solicited\n"));
++	}
++	if (!params.flags) {
++		params.flags = WL_NAN_PUB_BOTH; /* default. */
++	}
++	params.instance_id = (wl_nan_instance_id_t)cmd_data->pub_id;
++	memcpy((char *)params.svc_hash, cmd_data->svc_hash.data,
++		cmd_data->svc_hash.dlen);
++	ret = bcm_pack_xtlv_entry(&pxtlv, &end, WL_NAN_XTLV_SVC_PARAMS,
++		sizeof(params), &params, BCM_XTLV_OPTION_ALIGN32);
++	if (unlikely(ret)) {
++		goto fail;
++	}
++	if (cmd_data->svc_info.data && cmd_data->svc_info.dlen) {
++		uint16 len = cmd_data->svc_info.dlen/2;
++
++		WL_DBG((" optional svc_info present, pack it \n"));
++		buf = kzalloc(len, kflags);
++		if (!buf) {
++			WL_ERR((" memory allocation failed \n"));
++			ret = -ENOMEM;
++			goto fail;
++		}
++		if (get_ie_data((uchar*)cmd_data->svc_info.data, buf, len)) {
++			goto fail;
++		}
++
++		ret = bcm_pack_xtlv_entry(&pxtlv,
++			&end, WL_NAN_XTLV_SVC_INFO, len, buf, BCM_XTLV_OPTION_ALIGN32);
++		if (unlikely(ret)) {
++			goto fail;
++		}
++	}
++
++	nanioc->len = start - end;
++	nanioc_size = sizeof(wl_nan_ioc_t) + nanioc->len;
++	ret = wldev_iovar_setbuf(ndev, "nan", nanioc, nanioc_size,
++		cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	if (unlikely(ret)) {
++		WL_ERR((" nan publish failed, error = %d \n", ret));
++		goto fail;
++	} else {
++		WL_DBG((" nan publish successful \n"));
++	}
++
++fail:
++	if (nanioc) {
++		kfree(nanioc);
++	}
++	if (buf) {
++		kfree(buf);
++	}
++
++	return ret;
++}
++
++int
++wl_cfgnan_sub_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data)
++{
++	wl_nan_ioc_t *nanioc = NULL;
++	bcm_xtlvbuf_t tbuf;
++	wl_nan_disc_params_t params;
++	s32 ret = BCME_OK;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	uint16 nanioc_size = sizeof(wl_nan_ioc_t) + NAN_IOCTL_BUF_SIZE;
++
++	/*
++	 * proceed only if mandatory arguments are present - subscriber id,
++	 * service hash
++	 */
++	if ((!cmd_data->sub_id) || (!cmd_data->svc_hash.data) ||
++		(!cmd_data->svc_hash.dlen)) {
++		WL_ERR((" mandatory arguments are not present \n"));
++		return -EINVAL;
++	}
++
++	nanioc = kzalloc(nanioc_size, kflags);
++	if (!nanioc) {
++		WL_ERR((" memory allocation failed \n"));
++		return -ENOMEM;
++	}
++
++	bcm_xtlv_buf_init(&tbuf, nanioc->data,
++		BCM_XTLV_HDR_SIZE + sizeof(params), BCM_XTLV_OPTION_ALIGN32);
++
++	/*
++	 * command to test
++	 *
++	 * wl: wl nan subscribe 10 NAN123
++	 *
++	 * wpa_cli: DRIVER NAN_SUBSCRIBE SUB_ID=10 SVC_HASH=NAN123
++	 */
++
++	/* nan subscribe */
++	params.period = 1;
++	params.ttl = WL_NAN_TTL_UNTIL_CANCEL;
++	params.flags = 0;
++	if (cmd_data->flags & WL_NAN_SUB_ACTIVE) {
++		params.flags = WL_NAN_SUB_ACTIVE;
++		WL_DBG((" nan subscribe type - Active\n"));
++	}
++	params.instance_id = (wl_nan_instance_id_t)cmd_data->sub_id;
++	memcpy((char *)params.svc_hash, cmd_data->svc_hash.data,
++		cmd_data->svc_hash.dlen);
++	bcm_xtlv_put_data(&tbuf, WL_NAN_XTLV_SVC_PARAMS, &params, sizeof(params));
++
++	nanioc->version = htod16(WL_NAN_IOCTL_VERSION);
++	nanioc->id = htod16(WL_NAN_CMD_SUBSCRIBE);
++	nanioc->len = htod16(bcm_xtlv_buf_len(&tbuf));
++	nanioc_size = sizeof(wl_nan_ioc_t) + bcm_xtlv_buf_len(&tbuf);
++	ret = wldev_iovar_setbuf(ndev, "nan", nanioc, nanioc_size,
++		cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	if (unlikely(ret)) {
++		WL_ERR((" nan subscribe failed, error = %d \n", ret));
++		goto fail;
++	} else {
++		WL_DBG((" nan subscribe successful \n"));
++	}
++
++fail:
++	if (nanioc) {
++		kfree(nanioc);
++	}
++
++	return ret;
++}
++
++int
++wl_cfgnan_cancel_pub_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data)
++{
++	wl_nan_ioc_t *nanioc = NULL;
++	bcm_xtlvbuf_t tbuf;
++	wl_nan_disc_params_t params;
++	s32 ret = BCME_OK;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	uint16 nanioc_size = sizeof(wl_nan_ioc_t) + NAN_IOCTL_BUF_SIZE;
++
++	/* proceed only if mandatory argument is present - publisher id */
++	if (!cmd_data->pub_id) {
++		WL_ERR((" mandatory argument is not present \n"));
++		return -EINVAL;
++	}
++
++	nanioc = kzalloc(nanioc_size, kflags);
++	if (!nanioc) {
++		WL_ERR((" memory allocation failed \n"));
++		return -ENOMEM;
++	}
++
++	bcm_xtlv_buf_init(&tbuf, nanioc->data,
++		BCM_XTLV_HDR_SIZE + sizeof(params), BCM_XTLV_OPTION_ALIGN32);
++
++	/*
++	 * command to test
++	 *
++	 * wl: wl nan cancel_publish 10
++	 *
++	 * wpa_cli: DRIVER NAN_CANCEL_PUBLISH PUB_ID=10
++	 */
++
++	bcm_xtlv_put_data(&tbuf, WL_NAN_XTLV_INSTANCE_ID, &cmd_data->pub_id,
++		sizeof(wl_nan_instance_id_t));
++
++	/* nan cancel publish */
++	nanioc->version = htod16(WL_NAN_IOCTL_VERSION);
++	nanioc->id = htod16(WL_NAN_CMD_CANCEL_PUBLISH);
++	nanioc->len = htod16(bcm_xtlv_buf_len(&tbuf));
++	nanioc_size = sizeof(wl_nan_ioc_t) + bcm_xtlv_buf_len(&tbuf);
++	ret = wldev_iovar_setbuf(ndev, "nan", nanioc, nanioc_size,
++		cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	if (unlikely(ret)) {
++		WL_ERR((" nan cancel publish failed, error = %d \n", ret));
++		goto fail;
++	} else {
++		WL_DBG((" nan cancel publish successful \n"));
++	}
++
++fail:
++	if (nanioc) {
++		kfree(nanioc);
++	}
++
++	return ret;
++}
++
++int
++wl_cfgnan_cancel_sub_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data)
++{
++	wl_nan_ioc_t *nanioc = NULL;
++	bcm_xtlvbuf_t tbuf;
++	wl_nan_disc_params_t params;
++	s32 ret = BCME_OK;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	uint16 nanioc_size = sizeof(wl_nan_ioc_t) + NAN_IOCTL_BUF_SIZE;
++
++	/* proceed only if mandatory argument is present - subscriber id */
++	if (!cmd_data->sub_id) {
++		WL_ERR((" mandatory argument is not present \n"));
++		return -EINVAL;
++	}
++
++	nanioc = kzalloc(nanioc_size, kflags);
++	if (!nanioc) {
++		WL_ERR((" memory allocation failed \n"));
++		return -ENOMEM;
++	}
++
++	bcm_xtlv_buf_init(&tbuf, nanioc->data,
++		BCM_XTLV_HDR_SIZE + sizeof(params), BCM_XTLV_OPTION_ALIGN32);
++
++	/*
++	 * command to test
++	 *
++	 * wl: wl nan cancel_subscribe 10
++	 *
++	 * wpa_cli: DRIVER NAN_CANCEL_SUBSCRIBE PUB_ID=10
++	 */
++
++	bcm_xtlv_put_data(&tbuf, WL_NAN_XTLV_INSTANCE_ID, &cmd_data->sub_id,
++		sizeof(wl_nan_instance_id_t));
++
++	/* nan cancel subscribe */
++	nanioc->version = htod16(WL_NAN_IOCTL_VERSION);
++	nanioc->id = htod16(WL_NAN_CMD_CANCEL_SUBSCRIBE);
++	nanioc->len = htod16(bcm_xtlv_buf_len(&tbuf));
++	nanioc_size = sizeof(wl_nan_ioc_t) + bcm_xtlv_buf_len(&tbuf);
++	ret = wldev_iovar_setbuf(ndev, "nan", nanioc, nanioc_size,
++		cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	if (unlikely(ret)) {
++		WL_ERR((" nan cancel subscribe failed, error = %d \n", ret));
++		goto fail;
++	} else {
++		WL_DBG((" nan cancel subscribe successful \n"));
++	}
++
++fail:
++	if (nanioc) {
++		kfree(nanioc);
++	}
++
++	return ret;
++}
++
++int
++wl_cfgnan_transmit_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data)
++{
++	wl_nan_ioc_t *nanioc = NULL;
++	uint8 *pxtlv;
++	s32 ret = BCME_OK;
++	u16 start, end;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	uint16 nanioc_size = sizeof(wl_nan_ioc_t) + NAN_IOCTL_BUF_SIZE;
++	uchar *buf = NULL;
++
++	/*
++	 * proceed only if mandatory arguments are present - subscriber id,
++	 * publisher id, mac address
++	 */
++	if ((!cmd_data->local_id) || (!cmd_data->remote_id) ||
++		ETHER_ISNULLADDR(&cmd_data->mac_addr.octet)) {
++		WL_ERR((" mandatory arguments are not present \n"));
++		return -EINVAL;
++	}
++
++	nanioc = kzalloc(nanioc_size, kflags);
++	if (!nanioc) {
++		WL_ERR((" memory allocation failed \n"));
++		return -ENOMEM;
++	}
++
++	/*
++	 * command to test
++	 *
++	 * wl: wl nan trasnmit <sub_id> <pub_id> <mac_addr> -info <hex_string>
++	 *
++	 * wpa_cli: DRIVER NAN_TRANSMIT SUB_ID=<sub_id> PUB_ID=<pub_id>
++	 *          MAC_ADDR=<mac_addr> SVC_INFO=<hex_string>
++	 */
++
++	/* nan transmit */
++	start = end = NAN_IOCTL_BUF_SIZE;
++	nanioc->version = htod16(WL_NAN_IOCTL_VERSION);
++	nanioc->id = htod16(WL_NAN_CMD_TRANSMIT);
++	pxtlv = nanioc->data;
++
++	ret = bcm_pack_xtlv_entry(&pxtlv, &end, WL_NAN_XTLV_INSTANCE_ID,
++		sizeof(cmd_data->local_id), &cmd_data->local_id,
++		BCM_XTLV_OPTION_ALIGN32);
++	if (unlikely(ret)) {
++		goto fail;
++	}
++	ret = bcm_pack_xtlv_entry(&pxtlv, &end, WL_NAN_XTLV_REQUESTOR_ID,
++		sizeof(cmd_data->remote_id), &cmd_data->remote_id,
++		BCM_XTLV_OPTION_ALIGN32);
++	if (unlikely(ret)) {
++		goto fail;
++	}
++	ret = bcm_pack_xtlv_entry(&pxtlv, &end, WL_NAN_XTLV_MAC_ADDR,
++		ETHER_ADDR_LEN, &cmd_data->mac_addr.octet,
++		BCM_XTLV_OPTION_ALIGN32);
++	if (unlikely(ret)) {
++		goto fail;
++	}
++	if (cmd_data->svc_info.data && cmd_data->svc_info.dlen) {
++		uint16 len = cmd_data->svc_info.dlen/2;
++
++		WL_DBG((" optional svc_info present, pack it \n"));
++		buf = kzalloc(len, kflags);
++		if (!buf) {
++			WL_ERR((" memory allocation failed \n"));
++			ret = -ENOMEM;
++			goto fail;
++		}
++		if (get_ie_data((uchar*)cmd_data->svc_info.data, buf, len)) {
++			goto fail;
++		}
++
++		ret = bcm_pack_xtlv_entry(&pxtlv,
++			&end, WL_NAN_XTLV_SVC_INFO, len, buf,
++			BCM_XTLV_OPTION_ALIGN32);
++		if (unlikely(ret)) {
++			goto fail;
++		}
++	}
++
++	nanioc->len = start - end;
++	nanioc_size = sizeof(wl_nan_ioc_t) + nanioc->len;
++	ret = wldev_iovar_setbuf(ndev, "nan", nanioc, nanioc_size,
++		cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	if (unlikely(ret)) {
++		WL_ERR((" nan transmit failed, error = %d \n", ret));
++		goto fail;
++	} else {
++		WL_DBG((" nan transmit successful \n"));
++	}
++
++fail:
++	if (nanioc) {
++		kfree(nanioc);
++	}
++	if (buf) {
++		kfree(buf);
++	}
++
++	return ret;
++}
++
++int
++wl_cfgnan_set_config_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data)
++{
++	wl_nan_ioc_t *nanioc = NULL;
++	uint8 *pxtlv;
++	s32 ret = BCME_OK;
++	u16 start, end;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	uint16 nanioc_size = sizeof(wl_nan_ioc_t) + NAN_IOCTL_BUF_SIZE;
++
++	if (cfg->nan_running == true) {
++		WL_ERR((" Stop nan (NAN_STOP) before issuing NAN_CONFIG command\n"));
++		return BCME_ERROR;
++	}
++
++	if (cfg->nan_enable != true) {
++		ret = wl_cfgnan_enable_handler(ndev, cfg, cmd, cmd_data);
++		if (unlikely(ret)) {
++			goto fail;
++		}
++	}
++
++	nanioc = kzalloc(nanioc_size, kflags);
++	if (!nanioc) {
++		WL_ERR((" memory allocation failed \n"));
++		return -ENOMEM;
++	}
++
++	/*
++	 * command to test
++	 *
++	 * wl: wl nan <attr> <value> (wl nan role 1)
++	 *
++	 * wpa_cli: DRIVER NAN_CONFIG_SET ATTR=<attr> <value>...<value>
++	 *
++	 * wpa_cli: DRIVER NAN_SET_CONFIG ATTR=ATTR_ROLE ROLE=1
++	 */
++
++	/* nan set config */
++	start = end = NAN_IOCTL_BUF_SIZE;
++	nanioc->version = htod16(WL_NAN_IOCTL_VERSION);
++	nanioc->id = htod16(WL_NAN_CMD_ATTR);
++	pxtlv = nanioc->data;
++
++	switch (cmd_data->attr.type) {
++	case WL_NAN_XTLV_ROLE:
++		WL_DBG((" set nan ROLE = %#x\n", cmd_data->role));
++		ret = bcm_pack_xtlv_entry(&pxtlv, &end, WL_NAN_XTLV_ROLE,
++			sizeof(cmd_data->role), &cmd_data->role,
++			BCM_XTLV_OPTION_ALIGN32);
++		break;
++	case WL_NAN_XTLV_MASTER_PREF:
++		WL_DBG((" set nan MASTER PREF = %#x\n", cmd_data->master_pref));
++		ret = bcm_pack_xtlv_entry(&pxtlv, &end, WL_NAN_XTLV_MASTER_PREF,
++			sizeof(cmd_data->master_pref), &cmd_data->master_pref,
++			BCM_XTLV_OPTION_ALIGN32);
++		break;
++	case WL_NAN_XTLV_DW_LEN:
++		WL_DBG((" set nan DW LEN = %#x\n", cmd_data->dw_len));
++		ret = bcm_pack_xtlv_entry(&pxtlv, &end, WL_NAN_XTLV_DW_LEN,
++			sizeof(cmd_data->dw_len), &cmd_data->dw_len,
++			BCM_XTLV_OPTION_ALIGN32);
++		break;
++	case WL_NAN_XTLV_CLUSTER_ID:
++		WL_DBG((" set nan CLUSTER ID "));
++		ret = bcm_pack_xtlv_entry(&pxtlv, &end, WL_NAN_XTLV_CLUSTER_ID,
++			sizeof(cmd_data->clus_id), &cmd_data->clus_id,
++			BCM_XTLV_OPTION_ALIGN32);
++		break;
++	case WL_NAN_XTLV_IF_ADDR:
++		WL_DBG((" set nan IFADDR "));
++		ret = bcm_pack_xtlv_entry(&pxtlv, &end, WL_NAN_XTLV_IF_ADDR,
++			sizeof(cmd_data->if_addr), &cmd_data->if_addr,
++			BCM_XTLV_OPTION_ALIGN32);
++		break;
++	case WL_NAN_XTLV_MAC_CHANSPEC:
++		WL_DBG((" set nan CHANSPEC = %#x\n", cmd_data->chanspec));
++		ret = bcm_pack_xtlv_entry(&pxtlv, &end, WL_NAN_XTLV_MAC_CHANSPEC,
++			sizeof(cmd_data->chanspec), &cmd_data->chanspec,
++			BCM_XTLV_OPTION_ALIGN32);
++		break;
++	case WL_NAN_XTLV_BCN_INTERVAL:
++		WL_DBG((" set nan BCN_INTERVAL = %#x\n", cmd_data->beacon_int));
++		ret = bcm_pack_xtlv_entry(&pxtlv, &end, WL_NAN_XTLV_BCN_INTERVAL,
++			sizeof(cmd_data->beacon_int), &cmd_data->beacon_int,
++			BCM_XTLV_OPTION_ALIGN32);
++		break;
++	case WL_NAN_XTLV_MAC_TXRATE:
++	default:
++		ret = -EINVAL;
++		break;
++	}
++	if (unlikely(ret)) {
++		WL_ERR((" unsupported attribute, attr = %s (%d) \n",
++			cmd_data->attr.name, cmd_data->attr.type));
++		goto fail;
++	}
++
++	nanioc->len = start - end;
++	nanioc_size = sizeof(wl_nan_ioc_t) + nanioc->len;
++	ret = wldev_iovar_setbuf(ndev, "nan", nanioc, nanioc_size,
++		cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	if (unlikely(ret)) {
++		WL_ERR((" nan set config failed, error = %d \n", ret));
++		goto fail;
++	} else {
++		WL_DBG((" nan set config successful \n"));
++	}
++
++fail:
++	if (nanioc) {
++		kfree(nanioc);
++	}
++
++	return ret;
++}
++
++int
++wl_cfgnan_rtt_config_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data)
++{
++	wl_nan_ranging_config_t rtt_config;
++	s32 ret = BCME_OK;
++
++	/* proceed only if mandatory argument is present - channel */
++	if (!cmd_data->chanspec) {
++		WL_ERR((" mandatory argument is not present \n"));
++		return -EINVAL;
++	}
++
++	/*
++	 * command to test
++	 *
++	 * wl: wl proxd_nancfg 44/80 128 32 ff:ff:ff:ff:ff:ff 1
++	 *
++	 * wpa_cli: DRIVER NAN_RTT_CONFIG CHAN=44/80
++	 */
++
++	memset(&rtt_config, 0, sizeof(rtt_config));
++	rtt_config.chanspec = cmd_data->chanspec;
++	rtt_config.timeslot = 128;
++	rtt_config.duration = 32;
++	memcpy(&rtt_config.allow_mac, &ether_bcast, ETHER_ADDR_LEN);
++	rtt_config.flags = 1;
++
++	ret = wldev_iovar_setbuf(ndev, "proxd_nancfg", &rtt_config,
++		sizeof(wl_nan_ranging_config_t), cfg->ioctl_buf,
++		WLC_IOCTL_MEDLEN, NULL);
++	if (unlikely(ret)) {
++		WL_ERR((" nan rtt config failed, error = %d \n", ret));
++	} else {
++		WL_DBG((" nan rtt config successful \n"));
++	}
++
++	return ret;
++}
++
++int
++wl_cfgnan_rtt_find_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data)
++{
++	void *iovbuf;
++	wl_nan_ranging_list_t *rtt_list;
++	s32 iovbuf_size = NAN_RTT_IOVAR_BUF_SIZE;
++	s32 ret = BCME_OK;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++
++	/*
++	 * proceed only if mandatory arguments are present - channel, bitmap,
++	 * mac address
++	 */
++	if ((!cmd_data->chanspec) || (!cmd_data->bmap) ||
++		ETHER_ISNULLADDR(&cmd_data->mac_addr.octet)) {
++		WL_ERR((" mandatory arguments are not present \n"));
++		return -EINVAL;
++	}
++
++	iovbuf = kzalloc(iovbuf_size, kflags);
++	if (!iovbuf) {
++		WL_ERR((" memory allocation failed \n"));
++		return -ENOMEM;
++	}
++
++	/*
++	 * command to test
++	 *
++	 * wl: wl proxd_nanfind 1 44/80 <mac_addr> 0x300 5 6 1
++	 *
++	 * wpa_cli: DRIVER NAN_RTT_FIND MAC_ADDR=<mac_addr> CHAN=44/80 BMAP=0x300
++	 *
++	 */
++	rtt_list = (wl_nan_ranging_list_t *)iovbuf;
++	rtt_list->count = 1;
++	rtt_list->num_peers_done = 0;
++	rtt_list->num_dws = 1;
++	rtt_list->rp[0].chanspec = cmd_data->chanspec;
++	memcpy(&rtt_list->rp[0].ea, &cmd_data->mac_addr,
++		sizeof(struct ether_addr));
++	rtt_list->rp[0].abitmap = cmd_data->bmap;
++	rtt_list->rp[0].frmcnt = 5;
++	rtt_list->rp[0].retrycnt = 6;
++	rtt_list->rp[0].flags = 1;
++
++	iovbuf_size = sizeof(wl_nan_ranging_list_t) +
++		sizeof(wl_nan_ranging_peer_t);
++	ret = wldev_iovar_setbuf(ndev, "proxd_nanfind", iovbuf,
++		iovbuf_size, cfg->ioctl_buf, WLC_IOCTL_MEDLEN, NULL);
++	if (unlikely(ret)) {
++		WL_ERR((" nan rtt find failed, error = %d \n", ret));
++	} else {
++		WL_DBG((" nan rtt find successful \n"));
++	}
++
++	if (iovbuf) {
++		kfree(iovbuf);
++	}
++
++	return ret;
++}
++
++#ifdef WL_NAN_DEBUG
++int
++wl_cfgnan_debug_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data)
++{
++	/*
++	 * command to test
++	 *
++	 * wpa_cli: DRIVER NAN_DEBUG DEBUG=1
++	 *
++	 */
++
++	g_nan_debug = cmd_data->debug_flag;
++
++	/* reconfigure nan events */
++	return wl_cfgnan_enable_events(ndev, cfg);
++}
++#endif /* WL_NAN_DEBUG */
++
++static int wl_cfgnan_config_attr(char *buf, nan_config_attr_t *attr)
++{
++	s32 ret = BCME_OK;
++	nan_config_attr_t *nanc = NULL;
++
++	/* only one attribute at a time */
++	for (nanc = &nan_config_attrs[0]; strlen(nanc->name) != 0; nanc++) {
++		if (!strncmp(nanc->name, buf, strlen(nanc->name))) {
++			strncpy((char *)attr->name, buf, strlen(nanc->name));
++			attr->type = nanc->type;
++			ret = strlen(nanc->name);
++			break;
++		}
++	}
++
++	return ret;
++}
++
++static int wl_cfgnan_parse_args(char *buf, nan_cmd_data_t *cmd_data)
++{
++	s32 ret = BCME_OK;
++	char *token = buf;
++	char delim[] = " ";
++
++	while ((buf != NULL) && (token != NULL)) {
++		if (!strncmp(buf, PUB_ID_PREFIX, strlen(PUB_ID_PREFIX))) {
++			buf += strlen(PUB_ID_PREFIX);
++			token = strsep(&buf, delim);
++			cmd_data->pub_id = simple_strtoul(token, NULL, 10);
++			cmd_data->local_id ? (cmd_data->remote_id = cmd_data->pub_id) :
++				(cmd_data->local_id = cmd_data->pub_id);
++			if (NAN_INVALID_ID(cmd_data->pub_id)) {
++				WL_ERR((" invalid publisher id, pub_id = %d \n",
++					cmd_data->pub_id));
++				ret = -EINVAL;
++				goto fail;
++			}
++#ifdef NAN_P2P_CONFIG
++		} else if (!strncmp(buf, P2P_IE_PREFIX, strlen(P2P_IE_PREFIX))) {
++			buf += strlen(P2P_IE_PREFIX);
++			token = strsep(&buf, delim);
++			cmd_data->p2p_info.data = token;
++			cmd_data->p2p_info.dlen = strlen(token);
++		} else if (!strncmp(buf, IE_EN_PREFIX, strlen(IE_EN_PREFIX))) {
++			buf += strlen(IE_EN_PREFIX);
++			token = strsep(&buf, delim);
++			cmd_data->p2p_info.data = token;
++			cmd_data->p2p_info.dlen = strlen(token);
++#endif /* NAN_P2P_CONFIG */
++		} else if (!strncmp(buf, SUB_ID_PREFIX, strlen(SUB_ID_PREFIX))) {
++			buf += strlen(SUB_ID_PREFIX);
++			token = strsep(&buf, delim);
++			cmd_data->sub_id = simple_strtoul(token, NULL, 10);
++			cmd_data->local_id ? (cmd_data->remote_id = cmd_data->sub_id) :
++				(cmd_data->local_id = cmd_data->sub_id);
++			if (NAN_INVALID_ID(cmd_data->sub_id)) {
++				WL_ERR((" invalid subscriber id, sub_id = %d \n",
++					cmd_data->sub_id));
++				ret = -EINVAL;
++				goto fail;
++			}
++		} else if (!strncmp(buf, MAC_ADDR_PREFIX, strlen(MAC_ADDR_PREFIX))) {
++			buf += strlen(MAC_ADDR_PREFIX);
++			token = strsep(&buf, delim);
++			if (!wl_cfg80211_ether_atoe(token, &cmd_data->mac_addr)) {
++				WL_ERR((" invalid mac address, mac_addr = "MACDBG "\n",
++					MAC2STRDBG(cmd_data->mac_addr.octet)));
++				ret = -EINVAL;
++				goto fail;
++			}
++		} else if (!strncmp(buf, SVC_HASH_PREFIX, strlen(SVC_HASH_PREFIX))) {
++			buf += strlen(SVC_HASH_PREFIX);
++			token = strsep(&buf, delim);
++			cmd_data->svc_hash.data = token;
++			cmd_data->svc_hash.dlen = WL_NAN_SVC_HASH_LEN;
++		} else if (!strncmp(buf, SVC_INFO_PREFIX, strlen(SVC_INFO_PREFIX))) {
++			buf += strlen(SVC_INFO_PREFIX);
++			token = strsep(&buf, delim);
++			cmd_data->svc_info.data = token;
++			cmd_data->svc_info.dlen = strlen(token);
++		} else if (!strncmp(buf, CHAN_PREFIX, strlen(CHAN_PREFIX))) {
++			buf += strlen(CHAN_PREFIX);
++			token = strsep(&buf, delim);
++			cmd_data->chanspec = wf_chspec_aton(token);
++			cmd_data->chanspec = wl_chspec_host_to_driver(cmd_data->chanspec);
++			if (NAN_INVALID_CHANSPEC(cmd_data->chanspec)) {
++				WL_ERR((" invalid chanspec, chanspec = 0x%04x \n",
++					cmd_data->chanspec));
++				ret = -EINVAL;
++				goto fail;
++			}
++		} else if (!strncmp(buf, BITMAP_PREFIX, strlen(BITMAP_PREFIX))) {
++			buf += strlen(BITMAP_PREFIX);
++			token = strsep(&buf, delim);
++			cmd_data->bmap = simple_strtoul(token, NULL, 16);
++		} else if (!strncmp(buf, ATTR_PREFIX, strlen(ATTR_PREFIX))) {
++			buf += strlen(ATTR_PREFIX);
++			token = strsep(&buf, delim);
++			if (!wl_cfgnan_config_attr(token, &cmd_data->attr)) {
++				WL_ERR((" invalid attribute, attr = %s \n",
++					cmd_data->attr.name));
++				ret = -EINVAL;
++				goto fail;
++			}
++		} else if (!strncmp(buf, ROLE_PREFIX, strlen(ROLE_PREFIX))) {
++			buf += strlen(ROLE_PREFIX);
++			token = strsep(&buf, delim);
++			cmd_data->role = simple_strtoul(token, NULL, 10);
++			if (NAN_INVALID_ROLE(cmd_data->role)) {
++				WL_ERR((" invalid role, role = %d \n", cmd_data->role));
++				ret = -EINVAL;
++				goto fail;
++			}
++		} else if (!strncmp(buf, MASTER_PREF_PREFIX,
++			strlen(MASTER_PREF_PREFIX))) {
++			buf += strlen(MASTER_PREF_PREFIX);
++			token = strsep(&buf, delim);
++			cmd_data->master_pref = simple_strtoul(token, NULL, 10);
++		} else if (!strncmp(buf, CLUS_ID_PREFIX, strlen(CLUS_ID_PREFIX))) {
++			buf += strlen(CLUS_ID_PREFIX);
++			token = strsep(&buf, delim);
++			if (!wl_cfg80211_ether_atoe(token, &cmd_data->clus_id)) {
++				WL_ERR((" invalid cluster id, CLUS_ID = "MACDBG "\n",
++					MAC2STRDBG(cmd_data->clus_id.octet)));
++				ret = -EINVAL;
++				goto fail;
++			}
++		} else if (!strncmp(buf, IF_ADDR_PREFIX, strlen(IF_ADDR_PREFIX))) {
++			buf += strlen(IF_ADDR_PREFIX);
++			token = strsep(&buf, delim);
++			if (!wl_cfg80211_ether_atoe(token, &cmd_data->if_addr)) {
++				WL_ERR((" invalid cluster id, IF_ADDR = "MACDBG "\n",
++					MAC2STRDBG(cmd_data->if_addr.octet)));
++				ret = -EINVAL;
++				goto fail;
++			}
++		} else if (!strncmp(buf, BCN_INTERVAL_PREFIX,
++			strlen(BCN_INTERVAL_PREFIX))) {
++			buf += strlen(BCN_INTERVAL_PREFIX);
++			token = strsep(&buf, delim);
++			cmd_data->beacon_int = simple_strtoul(token, NULL, 10);
++		} else if (!strncmp(buf, PUB_PR_PREFIX, strlen(PUB_PR_PREFIX))) {
++			buf += strlen(PUB_PR_PREFIX);
++			token = strsep(&buf, delim);
++			cmd_data->pub_pr = simple_strtoul(token, NULL, 10);
++		} else if (!strncmp(buf, PUB_INT_PREFIX, strlen(PUB_INT_PREFIX))) {
++			buf += strlen(PUB_INT_PREFIX);
++			token = strsep(&buf, delim);
++			cmd_data->pub_int = simple_strtoul(token, NULL, 10);
++		} else if (!strncmp(buf, DW_LEN_PREFIX, strlen(DW_LEN_PREFIX))) {
++			buf += strlen(DW_LEN_PREFIX);
++			token = strsep(&buf, delim);
++			cmd_data->dw_len = simple_strtoul(token, NULL, 10);
++		} else if (!strncmp(buf, DEBUG_PREFIX, strlen(DEBUG_PREFIX))) {
++			buf += strlen(DEBUG_PREFIX);
++			token = strsep(&buf, delim);
++			cmd_data->debug_flag = simple_strtoul(token, NULL, 10);
++		} else if (!strncmp(buf, ACTIVE_OPTION, strlen(ACTIVE_OPTION))) {
++			buf += strlen(ACTIVE_OPTION);
++			token = strsep(&buf, delim);
++			cmd_data->flags |= WL_NAN_SUB_ACTIVE;
++		} else if (!strncmp(buf, SOLICITED_OPTION, strlen(SOLICITED_OPTION))) {
++			buf += strlen(SOLICITED_OPTION);
++			token = strsep(&buf, delim);
++			cmd_data->flags |= WL_NAN_PUB_SOLICIT;
++		} else if (!strncmp(buf, UNSOLICITED_OPTION, strlen(UNSOLICITED_OPTION))) {
++			buf += strlen(UNSOLICITED_OPTION);
++			token = strsep(&buf, delim);
++			cmd_data->flags |= WL_NAN_PUB_UNSOLICIT;
++		} else {
++			WL_ERR((" unknown token, token = %s, buf = %s \n", token, buf));
++			ret = -EINVAL;
++			goto fail;
++		}
++	}
++
++fail:
++	return ret;
++}
++
++int
++wl_cfgnan_cmd_handler(struct net_device *ndev, struct bcm_cfg80211 *cfg,
++	char *cmd, int cmd_len)
++{
++	nan_cmd_data_t cmd_data;
++	u8 *buf = cmd;
++	u8 *cmd_name = NULL;
++	nan_cmd_t *nanc = NULL;
++	int buf_len = 0;
++	int ret = BCME_OK;
++
++	cmd_name = strsep((char **)&buf, " ");
++	if (buf) {
++		buf_len = strlen(buf);
++	}
++
++	WL_DBG((" cmd_name: %s, buf_len: %d, buf: %s \n", cmd_name, buf_len, buf));
++
++	memset(&cmd_data, 0, sizeof(cmd_data));
++	ret = wl_cfgnan_parse_args(buf, &cmd_data);
++	if (unlikely(ret)) {
++		WL_ERR((" argument parsing failed with error (%d), buf = %s \n",
++			ret, buf));
++		goto fail;
++	}
++
++	for (nanc = nan_cmds; nanc->name; nanc++) {
++		if (strncmp(nanc->name, cmd_name, strlen(nanc->name)) == 0) {
++			ret = (*nanc->func)(ndev, cfg, cmd, cmd_len, &cmd_data);
++			if (ret < BCME_OK) {
++				WL_ERR((" command (%s) failed with error (%d) \n",
++					cmd_name, ret));
++			}
++		}
++	}
++
++fail:
++	return ret;
++}
++
++s32
++wl_cfgnan_notify_proxd_status(struct bcm_cfg80211 *cfg,
++	bcm_struct_cfgdev *cfgdev, const wl_event_msg_t *event, void *data)
++{
++	s32 ret = BCME_OK;
++	wl_nan_ranging_event_data_t *rdata;
++	s32 status;
++	u16 data_len;
++	s32 event_type;
++	s32 event_num;
++	u8 *buf = NULL;
++	u32 buf_len;
++	u8 *ptr, *end;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	s32 i;
++
++	if (!event || !data) {
++		WL_ERR((" event data is NULL \n"));
++		return -EINVAL;
++	}
++
++	status = ntoh32(event->reason);
++	event_type = ntoh32(event->event_type);
++	event_num = ntoh32(event->reason);
++	data_len = ntoh32(event->datalen);
++
++	WL_DBG((" proxd event: type: %d num: %d len: %d \n",
++		event_type, event_num, data_len));
++
++	if (NAN_INVALID_PROXD_EVENT(event_num)) {
++		WL_ERR((" unsupported event, num: %d \n", event_num));
++		return -EINVAL;
++	}
++
++#ifdef WL_NAN_DEBUG
++	if (g_nan_debug) {
++		WL_DBG((" event name: WLC_E_PROXD_NAN_EVENT \n"));
++		WL_DBG((" event data: \n"));
++		prhex(NULL, data, data_len);
++	}
++#endif /* WL_NAN_DEBUG */
++
++	if (data_len < sizeof(wl_nan_ranging_event_data_t)) {
++		WL_ERR((" wrong data len \n"));
++		return -EINVAL;
++	}
++
++	rdata = (wl_nan_ranging_event_data_t *)data;
++
++	WL_DBG((" proxd event: count:%d success_count:%d mode:%d \n",
++		rdata->count, rdata->success_count, rdata->mode));
++
++#ifdef WL_NAN_DEBUG
++	if (g_nan_debug) {
++		prhex(" event data: ", data, data_len);
++	}
++#endif /* WL_NAN_DEBUG */
++
++	buf_len = NAN_IOCTL_BUF_SIZE;
++	buf = kzalloc(buf_len, kflags);
++	if (!buf) {
++		WL_ERR((" memory allocation failed \n"));
++		return -ENOMEM;
++	}
++	end = buf + buf_len;
++
++	for (i = 0; i < rdata->count; i++) {
++		if (&rdata->rr[i] == NULL) {
++			ret = -EINVAL;
++			goto fail;
++		}
++
++		ptr = buf;
++		WL_DBG((" ranging data for mac:"MACDBG" \n",
++			MAC2STRDBG(rdata->rr[i].ea.octet)));
++		ptr += snprintf(ptr, end-ptr, SUPP_EVENT_PREFIX"%s " MAC_ADDR_PREFIX MACF
++			" "STATUS_PREFIX"%s", EVENT_RTT_STATUS_STR,
++			ETHER_TO_MACF(rdata->rr[i].ea), (rdata->rr[i].status == 1) ?
++			"success" : "fail");
++
++		if (rdata->rr[i].status == 1) {
++			/* add tsf and distance only if status is success */
++			ptr += snprintf(ptr, end-ptr, " "TIMESTAMP_PREFIX"0x%x "
++				DISTANCE_PREFIX"%d.%04d", rdata->rr[i].timestamp,
++				rdata->rr[i].distance >> 4,
++				((rdata->rr[i].distance & 0x0f) * 625));
++		}
++		if (ptr > end) {
++			WL_ERR(("Buffer overflow. userspace string truncated: %s, len: %zu\n",
++				buf, strlen(buf)));
++		}
++
++	}
++
++fail:
++	if (buf) {
++		kfree(buf);
++	}
++
++	return ret;
++}
++
++s32
++wl_cfgnan_notify_nan_status(struct bcm_cfg80211 *cfg,
++	bcm_struct_cfgdev *cfgdev, const wl_event_msg_t *event, void *data)
++{
++	s32 ret = BCME_OK;
++	u16 data_len;
++	u32 event_num;
++	s32 event_type;
++	nan_event_hdr_t nan_hdr;
++	wl_nan_tlv_data_t tlv_data;
++	u8 *buf = NULL;
++	u32 buf_len;
++	u8 *ptr, *end;
++	u16 kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++
++	if (!event || !data) {
++		WL_ERR((" event data is NULL \n"));
++		return -EINVAL;
++	}
++
++	event_type = ntoh32(event->event_type);
++	event_num = ntoh32(event->reason);
++	data_len = ntoh32(event->datalen);
++	memset(&nan_hdr, 0, sizeof(nan_event_hdr_t));
++	nan_hdr.event_subtype = event_num;
++
++	WL_DBG((" nan event: type: %d num: %d len: %d \n",
++		event_type, event_num, data_len));
++
++	if (NAN_INVALID_EVENT(event_num)) {
++		WL_ERR((" unsupported event, num: %d \n", event_num));
++		return -EINVAL;
++	}
++
++#ifdef WL_NAN_DEBUG
++	if (g_nan_debug) {
++		print_event_name(event_num);
++		WL_DBG((" event data: \n"));
++		prhex(NULL, data, data_len);
++	}
++#endif /* WL_NAN_DEBUG */
++
++	/* unpack the tlvs */
++	memset(&tlv_data, 0, sizeof(wl_nan_tlv_data_t));
++	bcm_unpack_xtlv_buf(&tlv_data, data, data_len,
++		BCM_XTLV_OPTION_ALIGN32, wl_cfgnan_set_vars_cbfn);
++
++	/*
++	 * send as preformatted hex string
++	 *
++	 * EVENT_NAN <event_type> <tlv_hex_string>
++	 */
++
++	buf_len = NAN_IOCTL_BUF_SIZE;
++	buf = ptr = kzalloc(buf_len, kflags);
++	if (!buf) {
++		WL_ERR((" memory allocation failed \n"));
++		ret = -ENOMEM;
++		goto fail;
++	}
++	end = buf + buf_len;
++
++	switch (event_num) {
++	case WL_NAN_EVENT_START:
++		ptr += snprintf(ptr, end-ptr, SUPP_EVENT_PREFIX"%s " CLUS_ID_PREFIX MACF,
++			NAN_EVENT_STR_STARTED, ETHER_TO_MACF(tlv_data.nstatus.cid));
++		break;
++	case WL_NAN_EVENT_JOIN:
++		ptr += snprintf(ptr, end-ptr, SUPP_EVENT_PREFIX"%s " CLUS_ID_PREFIX MACF,
++			NAN_EVENT_STR_JOINED, ETHER_TO_MACF(tlv_data.nstatus.cid));
++		break;
++	case WL_NAN_EVENT_STOP:
++		ptr += snprintf(ptr, end-ptr, SUPP_EVENT_PREFIX"%s " CLUS_ID_PREFIX MACF,
++			NAN_EVENT_STR_STOPPED, ETHER_TO_MACF(tlv_data.nstatus.cid));
++		break;
++	case WL_NAN_EVENT_ROLE:
++		ptr += snprintf(ptr, end-ptr, SUPP_EVENT_PREFIX"%s "ROLE_PREFIX "%d "
++			CLUS_ID_PREFIX MACF, NAN_EVENT_STR_ROLE_CHANGE,
++			tlv_data.nstatus.role, ETHER_TO_MACF(tlv_data.nstatus.cid));
++		break;
++	case WL_NAN_EVENT_DISCOVERY_RESULT:
++		ptr += snprintf(ptr, end-ptr, SUPP_EVENT_PREFIX"%s " PUB_ID_PREFIX"%d "
++			SUB_ID_PREFIX"%d " MAC_ADDR_PREFIX MACF,
++			NAN_EVENT_STR_SDF_RX, tlv_data.pub_id, tlv_data.sub_id,
++			ETHER_TO_MACF(tlv_data.mac_addr));
++		if (tlv_data.svc_info.data && tlv_data.svc_info.dlen) {
++			WL_DBG((" service info present \n"));
++			if ((strlen(ptr) + tlv_data.svc_info.dlen) >= buf_len) {
++				WL_ERR((" service info length = %d\n",
++					tlv_data.svc_info.dlen));
++				WL_ERR((" insufficent buffer to copy service info \n"));
++				ret = -EOVERFLOW;
++				goto fail;
++			}
++			ptr += snprintf(ptr, end-ptr, " %s", SVC_INFO_PREFIX);
++			ptr += bcm_format_hex(ptr, tlv_data.svc_info.data,
++				tlv_data.svc_info.dlen);
++		} else {
++			WL_DBG((" service info not present \n"));
++		}
++
++		if (tlv_data.vend_info.data && tlv_data.vend_info.dlen) {
++			struct ether_addr *ea;
++			u8 *temp_data = tlv_data.vend_info.data;
++			uint32 bitmap;
++			u16 dlen = tlv_data.vend_info.dlen;
++			chanspec_t chanspec;
++			uint8 mapcontrol;
++			uint8 proto;
++
++			WL_DBG((" vendor info present \n"));
++			if ((*temp_data != NAN_ATTR_VENDOR_SPECIFIC) ||
++				(dlen < NAN_VENDOR_HDR_SIZE)) {
++				WL_ERR((" error in vendor info attribute \n"));
++				ret = -EINVAL;
++				goto fail;
++			} else {
++				WL_DBG((" vendor info not present \n"));
++			}
++
++			if (*(temp_data + 6) == NAN_VENDOR_TYPE_RTT) {
++				temp_data += NAN_VENDOR_HDR_SIZE;
++				ea = (struct ether_addr *)temp_data;
++				temp_data += ETHER_ADDR_LEN;
++				mapcontrol = *temp_data++;
++				proto = *temp_data++;
++				bitmap = *(uint32 *)temp_data;
++				temp_data += 4;
++				chanspec = *(chanspec_t *)temp_data;
++				ptr += snprintf(ptr, end-ptr,
++					" "BITMAP_PREFIX"0x%x "CHAN_PREFIX"%d/%s",
++					bitmap, wf_chspec_ctlchan(chanspec),
++					wf_chspec_to_bw_str(chanspec));
++				WL_DBG((" bitmap: 0x%x channel: %d bandwidth: %s \n", bitmap,
++					wf_chspec_ctlchan(chanspec),
++					wf_chspec_to_bw_str(chanspec)));
++			}
++		}
++		break;
++	case WL_NAN_EVENT_REPLIED:
++		ptr += snprintf(ptr, end-ptr, SUPP_EVENT_PREFIX"%s " PUB_ID_PREFIX"%d "
++				MAC_ADDR_PREFIX MACF, NAN_EVENT_STR_REPLIED,
++				tlv_data.pub_id, ETHER_TO_MACF(tlv_data.mac_addr));
++		break;
++	case WL_NAN_EVENT_TERMINATED:
++		ptr += snprintf(ptr, end-ptr, SUPP_EVENT_PREFIX"%s " PUB_ID_PREFIX"%d ",
++			NAN_EVENT_STR_TERMINATED, tlv_data.pub_id);
++		break;
++	case WL_NAN_EVENT_RECEIVE:
++		ptr += snprintf(ptr, end-ptr,
++			SUPP_EVENT_PREFIX"%s " INSTANCE_ID_PREFIX"%d "
++			REMOTE_INSTANCE_ID_PREFIX"%d " MAC_ADDR_PREFIX MACF,
++			NAN_EVENT_STR_FOLLOWUP_RX, tlv_data.inst_id,
++			tlv_data.peer_inst_id, ETHER_TO_MACF(tlv_data.mac_addr));
++		if (tlv_data.svc_info.data && tlv_data.svc_info.dlen) {
++			WL_DBG((" service info present \n"));
++			if ((strlen(ptr) + tlv_data.svc_info.dlen) >= buf_len) {
++				WL_ERR((" service info length = %d\n",
++					tlv_data.svc_info.dlen));
++				WL_ERR((" insufficent buffer to copy service info \n"));
++				ret = -EOVERFLOW;
++				goto fail;
++			}
++			ptr += snprintf(ptr, end-ptr, " %s", SVC_INFO_PREFIX);
++			ptr += bcm_format_hex(ptr, tlv_data.svc_info.data,
++				tlv_data.svc_info.dlen);
++		} else {
++			WL_DBG((" service info not present \n"));
++		}
++		break;
++	case WL_NAN_EVENT_SCAN_COMPLETE:
++		ptr += snprintf(ptr, end-ptr, SUPP_EVENT_PREFIX"%s " CLUS_ID_PREFIX MACF,
++			NAN_EVENT_STR_SCAN_COMPLETE, ETHER_TO_MACF(tlv_data.nstatus.cid));
++		break;
++	case WL_NAN_EVENT_STATUS_CHG:
++		ptr += snprintf(ptr, end-ptr, SUPP_EVENT_PREFIX"%s " CLUS_ID_PREFIX MACF,
++			NAN_EVENT_STR_STATUS_CHANGE, ETHER_TO_MACF(tlv_data.nstatus.cid));
++		break;
++	case WL_NAN_EVENT_MERGE:
++		ptr += snprintf(ptr, end-ptr, SUPP_EVENT_PREFIX"%s " CLUS_ID_PREFIX MACF,
++			NAN_EVENT_STR_MERGED, ETHER_TO_MACF(tlv_data.nstatus.cid));
++		break;
++#ifdef NAN_P2P_CONFIG
++	case WL_NAN_EVENT_P2P:
++		ptr += snprintf(ptr, end-ptr, SUPP_EVENT_PREFIX"%s "
++				MAC_ADDR_PREFIX MACF, NAN_EVENT_STR_P2P_RX,
++				ETHER_TO_MACF(tlv_data.mac_addr));
++		if (tlv_data.vend_info.data && tlv_data.vend_info.dlen) {
++			u8 *data = tlv_data.vend_info.data;
++			u16 dlen = tlv_data.vend_info.dlen;
++
++			WL_DBG((" vendor info present %d  dlen  = %d\n",
++				*(data + 6), (dlen - (NAN_VENDOR_HDR_SIZE+1))));
++			if ((*data != NAN_ATTR_VENDOR_SPECIFIC) ||
++				(dlen < NAN_VENDOR_HDR_SIZE)) {
++				WL_ERR((" error in vendor info attribute \n"));
++				ret = -EINVAL;
++				goto fail;
++			} else {
++				WL_DBG((" vendor info present \n"));
++			}
++
++			if (*(data + 6) == NAN_VENDOR_TYPE_P2P) {
++				data += NAN_VENDOR_HDR_SIZE;
++				ptr += snprintf(ptr, end-ptr, " %s", P2P_IE_PREFIX);
++				ptr += bcm_format_hex(ptr, data, (dlen - (NAN_VENDOR_HDR_SIZE)));
++			}
++		}
++		break;
++#endif /* NAN_P2P_CONFIG */
++	default:
++		WL_ERR((" unknown event \n"));
++		break;
++	}
++	if (ptr > end) {
++		WL_ERR(("Buffer overflow. userspace string truncated: %s, len: %zu\n",
++			buf, strlen(buf)));
++	}
++
++
++fail:
++	if (buf) {
++		kfree(buf);
++	}
++	if (tlv_data.svc_info.data) {
++		kfree(tlv_data.svc_info.data);
++		tlv_data.svc_info.data = NULL;
++		tlv_data.svc_info.dlen = 0;
++	}
++	if (tlv_data.vend_info.data) {
++		kfree(tlv_data.vend_info.data);
++		tlv_data.vend_info.data = NULL;
++		tlv_data.vend_info.dlen = 0;
++	}
++
++	return ret;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgnan.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgnan.h
+new file mode 100644
+index 000000000..87af3e04d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgnan.h
+@@ -0,0 +1,226 @@
++/*
++ * Neighbor Awareness Networking
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfgnan.h 559906 2015-05-29 02:42:35Z $
++ */
++
++#ifndef _wl_cfgnan_h_
++#define _wl_cfgnan_h_
++
++#define NAN_IOCTL_BUF_SIZE			512
++#define NAN_EVENT_NAME_MAX_LEN		40
++#define NAN_CONFIG_ATTR_MAX_LEN		24
++#define NAN_RTT_IOVAR_BUF_SIZE		1024
++#define WL_NAN_EVENT_CLEAR_BIT		32
++#define NAN_EVENT_MASK_ALL			0x7fffffff
++
++#define NAN_INVALID_ID(id)	(id > 255)
++#define NAN_INVALID_ROLE(role)	(role > WL_NAN_ROLE_ANCHOR_MASTER)
++#define NAN_INVALID_CHANSPEC(chanspec)	((chanspec == INVCHANSPEC) || \
++	(chanspec == 0))
++#define NAN_INVALID_EVENT(num)	((num < WL_NAN_EVENT_START) || \
++	(num >= WL_NAN_EVENT_INVALID))
++#define NAN_INVALID_PROXD_EVENT(num)	(num != WLC_E_PROXD_NAN_EVENT)
++#define NAN_EVENT_BIT(event) (1U << (event - WL_NAN_EVENT_START))
++#define NAME_TO_STR(name) #name
++
++#define SUPP_EVENT_PREFIX		"CTRL-EVENT-"
++#define EVENT_RTT_STATUS_STR	"NAN-RTT-STATUS"
++
++#define TIMESTAMP_PREFIX	"TSF="			/* timestamp */
++#define AMR_PREFIX			"AMR="			/* anchor master rank */
++#define DISTANCE_PREFIX		"DIST="			/* distance */
++#define ATTR_PREFIX			"ATTR="			/* attribute */
++#define ROLE_PREFIX			"ROLE="			/* role */
++#define CHAN_PREFIX			"CHAN="			/* channel */
++#define BITMAP_PREFIX		"BMAP="			/* bitmap */
++#define DEBUG_PREFIX		"DEBUG="		/* debug enable/disable flag */
++#define DW_LEN_PREFIX		"DW_LEN="		/* discovery window length */
++#define DW_INT_PREFIX		"DW_INT="		/* discovery window interval */
++#define STATUS_PREFIX		"STATUS="		/* status */
++#define PUB_ID_PREFIX		"PUB_ID="		/* publisher id */
++#define SUB_ID_PREFIX		"SUB_ID="		/* subscriber id */
++#define INSTANCE_ID_PREFIX		"LOCAL_ID="		/* Instance id */
++#define REMOTE_INSTANCE_ID_PREFIX		"PEER_ID="		/* Peer id */
++
++#ifdef NAN_P2P_CONFIG
++#define P2P_IE_PREFIX		"P2P_IE="		/* p2p ie  id */
++#define IE_EN_PREFIX		"ENBLE_IE="		/* enable p2p ie  */
++#endif
++#define PUB_PR_PREFIX		"PUB_PR="		/* publish period */
++#define PUB_INT_PREFIX		"PUB_INT="		/* publish interval (ttl) */
++#define CLUS_ID_PREFIX		"CLUS_ID="		/* cluster id */
++#define IF_ADDR_PREFIX		"IF_ADDR="		/* IF address */
++#define MAC_ADDR_PREFIX		"MAC_ADDR="		/* mac address */
++#define SVC_HASH_PREFIX		"SVC_HASH="		/* service hash */
++#define SVC_INFO_PREFIX		"SVC_INFO="		/* service information */
++#define HOP_COUNT_PREFIX	"HOP_COUNT="	/* hop count */
++#define MASTER_PREF_PREFIX	"MASTER_PREF="	/* master preference */
++#define ACTIVE_OPTION		"ACTIVE"		/* Active Subscribe. */
++#define SOLICITED_OPTION	"SOLICITED"		/* Solicited Publish. */
++#define UNSOLICITED_OPTION	"UNSOLICITED"	/* Unsolicited Publish. */
++/* anchor master beacon transmission time */
++#define AMBTT_PREFIX		"AMBTT="
++/* passive scan period for cluster merge */
++#define SCAN_PERIOD_PREFIX	"SCAN_PERIOD="
++/* passive scan interval for cluster merge */
++#define SCAN_INTERVAL_PREFIX	"SCAN_INTERVAL="
++#define BCN_INTERVAL_PREFIX		"BCN_INTERVAL="
++
++#define NAN_EVENT_STR_STARTED               "NAN-STARTED"
++#define NAN_EVENT_STR_JOINED                "NAN-JOINED"
++#define NAN_EVENT_STR_ROLE_CHANGE           "NAN-ROLE-CHANGE"
++#define NAN_EVENT_STR_SCAN_COMPLETE         "NAN-SCAN-COMPLETE"
++#define NAN_EVENT_STR_SDF_RX                "NAN-SDF-RX"
++#define NAN_EVENT_STR_REPLIED               "NAN-REPLIED"
++#define NAN_EVENT_STR_TERMINATED            "NAN-TERMINATED"
++#define NAN_EVENT_STR_FOLLOWUP_RX           "NAN-FOLLOWUP-RX"
++#define NAN_EVENT_STR_STATUS_CHANGE         "NAN-STATUS-CHANGE"
++#define NAN_EVENT_STR_MERGED                "NAN-MERGED"
++#define NAN_EVENT_STR_STOPPED               "NAN-STOPPED"
++#define NAN_EVENT_STR_P2P_RX                "NAN-P2P-RX"
++#define NAN_EVENT_STR_WINDOW_BEGUN_P2P      "NAN-WINDOW-BEGUN-P2P"
++#define NAN_EVENT_STR_WINDOW_BEGUN_MESH     "NAN-WINDOW-BEGUN-MESH"
++#define NAN_EVENT_STR_WINDOW_BEGUN_IBSS     "NAN-WINDOW-BEGUN-IBSS"
++#define NAN_EVENT_STR_WINDOW_BEGUN_RANGING  "NAN-WINDOW-BEGUN-RANGING"
++#define NAN_EVENT_STR_INVALID               "NAN-INVALID"
++
++typedef struct nan_str_data {
++	u8 *data;
++	u32 dlen;
++} nan_str_data_t;
++
++typedef struct nan_config_attr {
++	char name[NAN_CONFIG_ATTR_MAX_LEN];	/* attribute name */
++	u16 type;							/* attribute xtlv type */
++} nan_config_attr_t;
++
++typedef struct nan_cmd_data {
++	nan_config_attr_t attr;			/* set config attributes */
++	nan_str_data_t svc_hash;		/* service hash */
++	nan_str_data_t svc_info;		/* service information */
++	nan_str_data_t p2p_info;		/* p2p information */
++	struct ether_addr mac_addr;		/* mac address */
++	struct ether_addr clus_id;		/* cluster id */
++	struct ether_addr if_addr;		/* if addr */
++	u32 beacon_int;					/* beacon interval */
++	u32 pub_int;					/* publish interval (ttl) */
++	u32 pub_pr;						/* publish period */
++	u32 bmap;						/* bitmap */
++	u32 role;						/* role */
++	u16 pub_id;						/* publisher id */
++	u16 sub_id;						/* subscriber id */
++	u16 local_id;					/* Local id */
++	u16 remote_id;					/* Remote id */
++	uint32 flags;					/* Flag bits */
++	u16 dw_len;						/* discovery window length */
++	u16 master_pref;				/* master preference */
++	chanspec_t chanspec;			/* channel */
++	u8 debug_flag;					/* debug enable/disable flag */
++} nan_cmd_data_t;
++
++typedef int (nan_func_t)(struct net_device *ndev, struct bcm_cfg80211 *cfg,
++	char *cmd, int size, nan_cmd_data_t *cmd_data);
++
++typedef struct nan_cmd {
++	const char *name;					/* command name */
++	nan_func_t *func;					/* command hadler */
++} nan_cmd_t;
++
++typedef struct nan_event_hdr {
++	u16 event_subtype;
++	u32 flags;							/* future use */
++} nan_event_hdr_t;
++
++typedef struct wl_nan_tlv_data {
++	wl_nan_status_t nstatus;			/* status data */
++	wl_nan_disc_params_t params;		/* discovery parameters */
++	struct ether_addr mac_addr;			/* peer mac address */
++	struct ether_addr clus_id;			/* cluster id */
++	nan_str_data_t svc_info;			/* service info */
++	nan_str_data_t vend_info;			/* vendor info */
++	/* anchor master beacon transmission time */
++	u32 ambtt;
++	u32 dev_role;						/* device role */
++	u16 inst_id;						/* instance id */
++	u16 peer_inst_id;					/* Peer instance id */
++	u16 pub_id;							/* publisher id */
++	u16 sub_id;							/* subscriber id */
++	u16 master_pref;					/* master preference */
++	chanspec_t chanspec;				/* channel */
++	u8 amr[NAN_MASTER_RANK_LEN];		/* anchor master role */
++	u8 svc_name[WL_NAN_SVC_HASH_LEN];	/* service name */
++	u8 hop_count;						/* hop count */
++	u8 enabled;							/* nan status flag */
++	nan_scan_params_t scan_params;		/* scan_param */
++} wl_nan_tlv_data_t;
++
++extern int wl_cfgnan_set_vars_cbfn(void *ctx, uint8 *tlv_buf,
++	uint16 type, uint16 len);
++extern int wl_cfgnan_enable_events(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg);
++extern int wl_cfgnan_start_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_stop_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_support_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_status_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_pub_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_p2p_ie_add_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_p2p_ie_enable_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_p2p_ie_del_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++
++extern int wl_cfgnan_sub_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_cancel_pub_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_cancel_sub_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_transmit_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_set_config_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_rtt_config_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++extern int wl_cfgnan_rtt_find_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++#ifdef WL_NAN_DEBUG
++extern int wl_cfgnan_debug_handler(struct net_device *ndev,
++	struct bcm_cfg80211 *cfg, char *cmd, int size, nan_cmd_data_t *cmd_data);
++#endif /* WL_NAN_DEBUG */
++extern int wl_cfgnan_cmd_handler(struct net_device *dev,
++	struct bcm_cfg80211 *cfg, char *cmd, int cmd_len);
++extern s32 wl_cfgnan_notify_nan_status(struct bcm_cfg80211 *cfg,
++	bcm_struct_cfgdev *cfgdev, const wl_event_msg_t *e, void *data);
++extern s32 wl_cfgnan_notify_proxd_status(struct bcm_cfg80211 *cfg,
++	bcm_struct_cfgdev *cfgdev, const wl_event_msg_t *e, void *data);
++
++#endif	/* _wl_cfgnan_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgp2p.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgp2p.c
+new file mode 100644
+index 000000000..ebe0dad6d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgp2p.c
+@@ -0,0 +1,2536 @@
++/*
++ * Linux cfgp2p driver
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfgp2p.c 709309 2019-01-17 09:04:00Z $
++ *
++ */
++#include <typedefs.h>
++#include <linuxver.h>
++#include <osl.h>
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/types.h>
++#include <linux/string.h>
++#include <linux/timer.h>
++#include <linux/if_arp.h>
++#include <asm/uaccess.h>
++
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <proto/ethernet.h>
++#include <proto/802.11.h>
++#include <net/rtnetlink.h>
++
++#include <wl_cfg80211.h>
++#include <wl_cfgp2p.h>
++#include <wldev_common.h>
++#include <wl_android.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_linux.h>
++#include <dhdioctl.h>
++#include <wlioctl.h>
++#include <dhd_cfg80211.h>
++
++static s8 scanparambuf[WLC_IOCTL_SMLEN];
++static bool
++wl_cfgp2p_has_ie(u8 *ie, u8 **tlvs, u32 *tlvs_len, const u8 *oui, u32 oui_len, u8 type);
++
++static s32 wl_cfgp2p_cancel_listen(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	struct wireless_dev *wdev, bool notify);
++
++#if defined(WL_ENABLE_P2P_IF)
++static int wl_cfgp2p_start_xmit(struct sk_buff *skb, struct net_device *ndev);
++static int wl_cfgp2p_do_ioctl(struct net_device *net, struct ifreq *ifr, int cmd);
++static int wl_cfgp2p_if_open(struct net_device *net);
++static int wl_cfgp2p_if_stop(struct net_device *net);
++
++static const struct net_device_ops wl_cfgp2p_if_ops = {
++	.ndo_open       = wl_cfgp2p_if_open,
++	.ndo_stop       = wl_cfgp2p_if_stop,
++	.ndo_do_ioctl   = wl_cfgp2p_do_ioctl,
++	.ndo_start_xmit = wl_cfgp2p_start_xmit,
++};
++#endif /* WL_ENABLE_P2P_IF */
++
++
++bool wl_cfgp2p_is_pub_action(void *frame, u32 frame_len)
++{
++	wifi_p2p_pub_act_frame_t *pact_frm;
++
++	if (frame == NULL)
++		return false;
++	pact_frm = (wifi_p2p_pub_act_frame_t *)frame;
++	if (frame_len < sizeof(wifi_p2p_pub_act_frame_t) -1)
++		return false;
++
++	if (pact_frm->category == P2P_PUB_AF_CATEGORY &&
++		pact_frm->action == P2P_PUB_AF_ACTION &&
++		pact_frm->oui_type == P2P_VER &&
++		memcmp(pact_frm->oui, P2P_OUI, sizeof(pact_frm->oui)) == 0) {
++		return true;
++	}
++
++	return false;
++}
++
++bool wl_cfgp2p_is_p2p_action(void *frame, u32 frame_len)
++{
++	wifi_p2p_action_frame_t *act_frm;
++
++	if (frame == NULL)
++		return false;
++	act_frm = (wifi_p2p_action_frame_t *)frame;
++	if (frame_len < sizeof(wifi_p2p_action_frame_t) -1)
++		return false;
++
++	if (act_frm->category == P2P_AF_CATEGORY &&
++		act_frm->type  == P2P_VER &&
++		memcmp(act_frm->OUI, P2P_OUI, DOT11_OUI_LEN) == 0) {
++		return true;
++	}
++
++	return false;
++}
++
++#define GAS_RESP_LEN		2
++#define DOUBLE_TLV_BODY_OFF	4
++#define GAS_RESP_OFFSET		4
++#define GAS_CRESP_OFFSET	5
++
++bool wl_cfgp2p_find_gas_subtype(u8 subtype, u8* data, u32 len)
++{
++	bcm_tlv_t *ie = (bcm_tlv_t *)data;
++	u8 *frame = NULL;
++	u16 id, flen;
++
++	/* Skipped first ANQP Element, if frame has anqp elemnt */
++	ie = bcm_parse_tlvs(ie, (int)len, DOT11_MNG_ADVERTISEMENT_ID);
++
++	if (ie == NULL)
++		return false;
++
++	frame = (uint8 *)ie + ie->len + TLV_HDR_LEN + GAS_RESP_LEN;
++	id = ((u16) (((frame)[1] << 8) | (frame)[0]));
++	flen = ((u16) (((frame)[3] << 8) | (frame)[2]));
++
++	/* If the contents match the OUI and the type */
++	if (flen >= WFA_OUI_LEN + 1 &&
++		id ==  P2PSD_GAS_NQP_INFOID &&
++		!bcmp(&frame[DOUBLE_TLV_BODY_OFF], (const uint8*)WFA_OUI, WFA_OUI_LEN) &&
++		subtype == frame[DOUBLE_TLV_BODY_OFF+WFA_OUI_LEN]) {
++		return true;
++	}
++
++	return false;
++}
++
++bool wl_cfgp2p_is_gas_action(void *frame, u32 frame_len)
++{
++
++	wifi_p2psd_gas_pub_act_frame_t *sd_act_frm;
++
++	if (frame == NULL)
++		return false;
++
++	sd_act_frm = (wifi_p2psd_gas_pub_act_frame_t *)frame;
++	if (frame_len < (sizeof(wifi_p2psd_gas_pub_act_frame_t) - 1))
++		return false;
++	if (sd_act_frm->category != P2PSD_ACTION_CATEGORY)
++		return false;
++
++#ifdef WL11U
++	if (sd_act_frm->action == P2PSD_ACTION_ID_GAS_IRESP)
++		return wl_cfgp2p_find_gas_subtype(P2PSD_GAS_OUI_SUBTYPE,
++			(u8 *)sd_act_frm->query_data + GAS_RESP_OFFSET,
++			frame_len);
++
++	else if (sd_act_frm->action == P2PSD_ACTION_ID_GAS_CRESP)
++		return wl_cfgp2p_find_gas_subtype(P2PSD_GAS_OUI_SUBTYPE,
++			(u8 *)sd_act_frm->query_data + GAS_CRESP_OFFSET,
++			frame_len);
++	else if (sd_act_frm->action == P2PSD_ACTION_ID_GAS_IREQ ||
++		sd_act_frm->action == P2PSD_ACTION_ID_GAS_CREQ)
++		return true;
++	else
++		return false;
++#else
++	if (sd_act_frm->action == P2PSD_ACTION_ID_GAS_IREQ ||
++		sd_act_frm->action == P2PSD_ACTION_ID_GAS_IRESP ||
++		sd_act_frm->action == P2PSD_ACTION_ID_GAS_CREQ ||
++		sd_act_frm->action == P2PSD_ACTION_ID_GAS_CRESP)
++		return true;
++	else
++		return false;
++#endif /* WL11U */
++}
++
++bool wl_cfgp2p_is_p2p_gas_action(void *frame, u32 frame_len)
++{
++
++	wifi_p2psd_gas_pub_act_frame_t *sd_act_frm;
++
++	if (frame == NULL)
++		return false;
++
++	sd_act_frm = (wifi_p2psd_gas_pub_act_frame_t *)frame;
++	if (frame_len < (sizeof(wifi_p2psd_gas_pub_act_frame_t) - 1))
++		return false;
++	if (sd_act_frm->category != P2PSD_ACTION_CATEGORY)
++		return false;
++
++	if (sd_act_frm->action == P2PSD_ACTION_ID_GAS_IREQ)
++		return wl_cfgp2p_find_gas_subtype(P2PSD_GAS_OUI_SUBTYPE,
++			(u8 *)sd_act_frm->query_data,
++			frame_len);
++	else
++		return false;
++}
++
++void wl_cfgp2p_print_actframe(bool tx, void *frame, u32 frame_len, u32 channel)
++{
++	wifi_p2p_pub_act_frame_t *pact_frm;
++	wifi_p2p_action_frame_t *act_frm;
++	wifi_p2psd_gas_pub_act_frame_t *sd_act_frm;
++	if (!frame || frame_len <= 2)
++		return;
++
++	if (wl_cfgp2p_is_pub_action(frame, frame_len)) {
++		pact_frm = (wifi_p2p_pub_act_frame_t *)frame;
++		switch (pact_frm->subtype) {
++			case P2P_PAF_GON_REQ:
++				CFGP2P_ACTION(("%s P2P Group Owner Negotiation Req Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_PAF_GON_RSP:
++				CFGP2P_ACTION(("%s P2P Group Owner Negotiation Rsp Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_PAF_GON_CONF:
++				CFGP2P_ACTION(("%s P2P Group Owner Negotiation Confirm Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_PAF_INVITE_REQ:
++				CFGP2P_ACTION(("%s P2P Invitation Request  Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_PAF_INVITE_RSP:
++				CFGP2P_ACTION(("%s P2P Invitation Response Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_PAF_DEVDIS_REQ:
++				CFGP2P_ACTION(("%s P2P Device Discoverability Request Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_PAF_DEVDIS_RSP:
++				CFGP2P_ACTION(("%s P2P Device Discoverability Response Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_PAF_PROVDIS_REQ:
++				CFGP2P_ACTION(("%s P2P Provision Discovery Request Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_PAF_PROVDIS_RSP:
++				CFGP2P_ACTION(("%s P2P Provision Discovery Response Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			default:
++				CFGP2P_ACTION(("%s Unknown Public Action Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++
++		}
++
++	} else if (wl_cfgp2p_is_p2p_action(frame, frame_len)) {
++		act_frm = (wifi_p2p_action_frame_t *)frame;
++		switch (act_frm->subtype) {
++			case P2P_AF_NOTICE_OF_ABSENCE:
++				CFGP2P_ACTION(("%s P2P Notice of Absence Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_AF_PRESENCE_REQ:
++				CFGP2P_ACTION(("%s P2P Presence Request Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_AF_PRESENCE_RSP:
++				CFGP2P_ACTION(("%s P2P Presence Response Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			case P2P_AF_GO_DISC_REQ:
++				CFGP2P_ACTION(("%s P2P Discoverability Request Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++				break;
++			default:
++				CFGP2P_ACTION(("%s Unknown P2P Action Frame,"
++					" channel=%d\n", (tx)? "TX": "RX", channel));
++		}
++
++	} else if (wl_cfgp2p_is_gas_action(frame, frame_len)) {
++		sd_act_frm = (wifi_p2psd_gas_pub_act_frame_t *)frame;
++		switch (sd_act_frm->action) {
++			case P2PSD_ACTION_ID_GAS_IREQ:
++				CFGP2P_ACTION(("%s GAS Initial Request,"
++					" channel=%d\n", (tx)? "TX" : "RX", channel));
++				break;
++			case P2PSD_ACTION_ID_GAS_IRESP:
++				CFGP2P_ACTION(("%s GAS Initial Response,"
++					" channel=%d\n", (tx)? "TX" : "RX", channel));
++				break;
++			case P2PSD_ACTION_ID_GAS_CREQ:
++				CFGP2P_ACTION(("%s GAS Comback Request,"
++					" channel=%d\n", (tx)? "TX" : "RX", channel));
++				break;
++			case P2PSD_ACTION_ID_GAS_CRESP:
++				CFGP2P_ACTION(("%s GAS Comback Response,"
++					" channel=%d\n", (tx)? "TX" : "RX", channel));
++				break;
++			default:
++				CFGP2P_ACTION(("%s Unknown GAS Frame,"
++					" channel=%d\n", (tx)? "TX" : "RX", channel));
++		}
++
++
++	}
++}
++
++/*
++ *  Initialize variables related to P2P
++ *
++ */
++s32
++wl_cfgp2p_init_priv(struct bcm_cfg80211 *cfg)
++{
++	if (!(cfg->p2p = kzalloc(sizeof(struct p2p_info), GFP_KERNEL))) {
++		CFGP2P_ERR(("struct p2p_info allocation failed\n"));
++		return -ENOMEM;
++	}
++
++	wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_PRIMARY) = bcmcfg_to_prmry_ndev(cfg);
++	wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_PRIMARY) = 0;
++	wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_DEVICE) = NULL;
++	wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE) = 0;
++	wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_CONNECTION1) = NULL;
++	wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_CONNECTION1) = -1;
++	wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_CONNECTION2) = NULL;
++	wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_CONNECTION2) = -1;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++	cfg->p2p->cfg = cfg;
++#endif
++	return BCME_OK;
++
++}
++/*
++ *  Deinitialize variables related to P2P
++ *
++ */
++void
++wl_cfgp2p_deinit_priv(struct bcm_cfg80211 *cfg)
++{
++	CFGP2P_ERR(("In\n"));
++	if (cfg->p2p) {
++		kfree(cfg->p2p);
++		cfg->p2p = NULL;
++	}
++	cfg->p2p_supported = 0;
++}
++/*
++ * Set P2P functions into firmware
++ */
++s32
++wl_cfgp2p_set_firm_p2p(struct bcm_cfg80211 *cfg)
++{
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	struct ether_addr null_eth_addr = { { 0, 0, 0, 0, 0, 0 } };
++	s32 ret = BCME_OK;
++	s32 val = 0;
++	/* Do we have to check whether APSTA is enabled or not ? */
++	ret = wldev_iovar_getint(ndev, "apsta", &val);
++	if (ret < 0) {
++		CFGP2P_ERR(("get apsta error %d\n", ret));
++		return ret;
++	}
++	if (val == 0) {
++		val = 1;
++		ret = wldev_ioctl(ndev, WLC_DOWN, &val, sizeof(s32), true);
++		if (ret < 0) {
++			CFGP2P_ERR(("WLC_DOWN error %d\n", ret));
++			return ret;
++		}
++
++		ret = wldev_iovar_setint(ndev, "apsta", val);
++		if (ret < 0) {
++			/* return error and fail the initialization */
++			CFGP2P_ERR(("wl apsta %d set error. ret: %d\n", val, ret));
++			return ret;
++		}
++
++		ret = wldev_ioctl(ndev, WLC_UP, &val, sizeof(s32), true);
++		if (ret < 0) {
++			CFGP2P_ERR(("WLC_UP error %d\n", ret));
++			return ret;
++		}
++	}
++
++	/* In case of COB type, firmware has default mac address
++	 * After Initializing firmware, we have to set current mac address to
++	 * firmware for P2P device address
++	 */
++	ret = wldev_iovar_setbuf_bsscfg(ndev, "p2p_da_override", &null_eth_addr,
++		sizeof(null_eth_addr), cfg->ioctl_buf, WLC_IOCTL_MAXLEN, 0, &cfg->ioctl_buf_sync);
++	if (ret && ret != BCME_UNSUPPORTED) {
++		CFGP2P_ERR(("failed to update device address ret %d\n", ret));
++	}
++	return ret;
++}
++
++int wl_cfg_multip2p_operational(struct bcm_cfg80211 *cfg)
++{
++	if (!cfg->p2p) {
++		CFGP2P_DBG(("p2p not enabled! \n"));
++		return false;
++	}
++
++	if ((wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_CONNECTION1) != -1) &&
++	    (wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_CONNECTION2) != -1))
++		return true;
++	else
++		return false;
++}
++
++/* Create a new P2P BSS.
++ * Parameters:
++ * @mac      : MAC address of the BSS to create
++ * @if_type  : interface type: WL_P2P_IF_GO or WL_P2P_IF_CLIENT
++ * @chspec   : chspec to use if creating a GO BSS.
++ * Returns 0 if success.
++ */
++s32
++wl_cfgp2p_ifadd(struct bcm_cfg80211 *cfg, struct ether_addr *mac, u8 if_type,
++            chanspec_t chspec)
++{
++	wl_p2p_if_t ifreq;
++	s32 err;
++	u32 scb_timeout = WL_SCB_TIMEOUT;
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++
++	ifreq.type = if_type;
++	ifreq.chspec = chspec;
++	memcpy(ifreq.addr.octet, mac->octet, sizeof(ifreq.addr.octet));
++
++	CFGP2P_DBG(("---cfg p2p_ifadd "MACDBG" %s %u\n",
++		MAC2STRDBG(ifreq.addr.octet),
++		(if_type == WL_P2P_IF_GO) ? "go" : "client",
++	        (chspec & WL_CHANSPEC_CHAN_MASK) >> WL_CHANSPEC_CHAN_SHIFT));
++
++	err = wldev_iovar_setbuf(ndev, "p2p_ifadd", &ifreq, sizeof(ifreq),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++
++	if (unlikely(err < 0))
++		printk("'cfg p2p_ifadd' error %d\n", err);
++	else if (if_type == WL_P2P_IF_GO) {
++		err = wldev_ioctl(ndev, WLC_SET_SCB_TIMEOUT, &scb_timeout, sizeof(u32), true);
++		if (unlikely(err < 0))
++			printk("'cfg scb_timeout' error %d\n", err);
++	}
++
++	return err;
++}
++
++/* Disable a P2P BSS.
++ * Parameters:
++ * @mac      : MAC address of the BSS to disable
++ * Returns 0 if success.
++ */
++s32
++wl_cfgp2p_ifdisable(struct bcm_cfg80211 *cfg, struct ether_addr *mac)
++{
++	s32 ret;
++	struct net_device *netdev = bcmcfg_to_prmry_ndev(cfg);
++
++	CFGP2P_INFO(("------primary idx %d : cfg p2p_ifdis "MACDBG"\n",
++		netdev->ifindex, MAC2STRDBG(mac->octet)));
++	ret = wldev_iovar_setbuf(netdev, "p2p_ifdis", mac, sizeof(*mac),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++	if (unlikely(ret < 0)) {
++		printk("'cfg p2p_ifdis' error %d\n", ret);
++	}
++	return ret;
++}
++
++/* Delete a P2P BSS.
++ * Parameters:
++ * @mac      : MAC address of the BSS to delete
++ * Returns 0 if success.
++ */
++s32
++wl_cfgp2p_ifdel(struct bcm_cfg80211 *cfg, struct ether_addr *mac)
++{
++	s32 ret;
++	struct net_device *netdev = bcmcfg_to_prmry_ndev(cfg);
++
++	CFGP2P_INFO(("------primary idx %d : cfg p2p_ifdel "MACDBG"\n",
++	    netdev->ifindex, MAC2STRDBG(mac->octet)));
++	ret = wldev_iovar_setbuf(netdev, "p2p_ifdel", mac, sizeof(*mac),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++	if (unlikely(ret < 0)) {
++		printk("'cfg p2p_ifdel' error %d\n", ret);
++	}
++	return ret;
++}
++
++/* Change a P2P Role.
++ * Parameters:
++ * @mac      : MAC address of the BSS to change a role
++ * Returns 0 if success.
++ */
++s32
++wl_cfgp2p_ifchange(struct bcm_cfg80211 *cfg, struct ether_addr *mac, u8 if_type,
++            chanspec_t chspec, s32 conn_idx)
++{
++	wl_p2p_if_t ifreq;
++	s32 err;
++	u32 scb_timeout = WL_SCB_TIMEOUT;
++
++	struct net_device *netdev =  wl_to_p2p_bss_ndev(cfg, conn_idx);
++
++	ifreq.type = if_type;
++	ifreq.chspec = chspec;
++	memcpy(ifreq.addr.octet, mac->octet, sizeof(ifreq.addr.octet));
++
++	CFGP2P_INFO(("---cfg p2p_ifchange "MACDBG" %s %u"
++		" chanspec 0x%04x\n", MAC2STRDBG(ifreq.addr.octet),
++		(if_type == WL_P2P_IF_GO) ? "go" : "client",
++		(chspec & WL_CHANSPEC_CHAN_MASK) >> WL_CHANSPEC_CHAN_SHIFT,
++		ifreq.chspec));
++
++	err = wldev_iovar_setbuf(netdev, "p2p_ifupd", &ifreq, sizeof(ifreq),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++
++	if (unlikely(err < 0)) {
++		printk("'cfg p2p_ifupd' error %d\n", err);
++	} else if (if_type == WL_P2P_IF_GO) {
++		cfg->p2p->p2p_go_count++;
++		err = wldev_ioctl(netdev, WLC_SET_SCB_TIMEOUT, &scb_timeout, sizeof(u32), true);
++		if (unlikely(err < 0))
++			printk("'cfg scb_timeout' error %d\n", err);
++	}
++	return err;
++}
++
++
++/* Get the index of a created P2P BSS.
++ * Parameters:
++ * @mac      : MAC address of the created BSS
++ * @index    : output: index of created BSS
++ * Returns 0 if success.
++ */
++s32
++wl_cfgp2p_ifidx(struct bcm_cfg80211 *cfg, struct ether_addr *mac, s32 *index)
++{
++	s32 ret;
++	u8 getbuf[64];
++	struct net_device *dev = bcmcfg_to_prmry_ndev(cfg);
++
++	CFGP2P_INFO(("---cfg p2p_if "MACDBG"\n", MAC2STRDBG(mac->octet)));
++
++	ret = wldev_iovar_getbuf_bsscfg(dev, "p2p_if", mac, sizeof(*mac), getbuf,
++		sizeof(getbuf), wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_PRIMARY), NULL);
++
++	if (ret == 0) {
++		memcpy(index, getbuf, sizeof(s32));
++		CFGP2P_INFO(("---cfg p2p_if   ==> %d\n", *index));
++	}
++
++	return ret;
++}
++
++static s32
++wl_cfgp2p_set_discovery(struct bcm_cfg80211 *cfg, s32 on)
++{
++	s32 ret = BCME_OK;
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++	CFGP2P_DBG(("enter\n"));
++
++	ret = wldev_iovar_setint(ndev, "p2p_disc", on);
++
++	if (unlikely(ret < 0)) {
++		CFGP2P_ERR(("p2p_disc %d error %d\n", on, ret));
++	}
++
++	return ret;
++}
++
++/* Set the WL driver's P2P mode.
++ * Parameters :
++ * @mode      : is one of WL_P2P_DISC_ST_{SCAN,LISTEN,SEARCH}.
++ * @channel   : the channel to listen
++ * @listen_ms : the time (milli seconds) to wait
++ * @bssidx    : bss index for BSSCFG
++ * Returns 0 if success
++ */
++
++s32
++wl_cfgp2p_set_p2p_mode(struct bcm_cfg80211 *cfg, u8 mode, u32 channel, u16 listen_ms, int bssidx)
++{
++	wl_p2p_disc_st_t discovery_mode;
++	s32 ret;
++	struct net_device *dev;
++	CFGP2P_DBG(("enter\n"));
++
++	if (unlikely(bssidx == WL_INVALID)) {
++		CFGP2P_ERR((" %d index out of range\n", bssidx));
++		return -1;
++	}
++
++	dev = wl_cfgp2p_find_ndev(cfg, bssidx);
++	if (unlikely(dev == NULL)) {
++		CFGP2P_ERR(("bssidx %d is not assigned\n", bssidx));
++		return BCME_NOTFOUND;
++	}
++
++#ifdef P2PLISTEN_AP_SAMECHN
++	CFGP2P_DBG(("p2p0 listen channel %d  AP connection chan %d \n",
++		channel, cfg->channel));
++	if ((mode == WL_P2P_DISC_ST_LISTEN) && (cfg->channel == channel)) {
++		struct net_device *primary_ndev = bcmcfg_to_prmry_ndev(cfg);
++
++		if (cfg->p2p_resp_apchn_status) {
++			CFGP2P_DBG(("p2p_resp_apchn_status already ON \n"));
++			return BCME_OK;
++		}
++
++		if (wl_get_drv_status(cfg, CONNECTED, primary_ndev)) {
++			ret = wl_cfg80211_set_p2p_resp_ap_chn(primary_ndev, 1);
++			cfg->p2p_resp_apchn_status = true;
++			CFGP2P_DBG(("p2p_resp_apchn_status ON \n"));
++			return ret;
++		}
++	}
++#endif /* P2PLISTEN_AP_SAMECHN */
++
++	/* Put the WL driver into P2P Listen Mode to respond to P2P probe reqs */
++	discovery_mode.state = mode;
++	discovery_mode.chspec = wl_ch_host_to_driver(bssidx, channel);
++	discovery_mode.dwell = listen_ms;
++	ret = wldev_iovar_setbuf_bsscfg(dev, "p2p_state", &discovery_mode,
++		sizeof(discovery_mode), cfg->ioctl_buf, WLC_IOCTL_MAXLEN,
++		bssidx, &cfg->ioctl_buf_sync);
++
++	return ret;
++}
++
++/* Get the index of the P2P Discovery BSS */
++static s32
++wl_cfgp2p_get_disc_idx(struct bcm_cfg80211 *cfg, s32 *index)
++{
++	s32 ret;
++	struct net_device *dev = wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_PRIMARY);
++
++	ret = wldev_iovar_getint(dev, "p2p_dev", index);
++	CFGP2P_INFO(("p2p_dev bsscfg_idx=%d ret=%d\n", *index, ret));
++
++	if (unlikely(ret <  0)) {
++	    CFGP2P_ERR(("'p2p_dev' error %d\n", ret));
++		return ret;
++	}
++	return ret;
++}
++
++int wl_cfgp2p_get_conn_idx(struct bcm_cfg80211 *cfg)
++{
++	int i;
++	s32 connected_cnt;
++	dhd_pub_t *dhd =  (dhd_pub_t *)(cfg->pub);
++	if (!dhd)
++		return (-ENODEV);
++	for (i = P2PAPI_BSSCFG_CONNECTION1; i < P2PAPI_BSSCFG_MAX; i++) {
++		if (wl_to_p2p_bss_bssidx(cfg, i) == -1) {
++			if (i == P2PAPI_BSSCFG_CONNECTION2) {
++				if (!(dhd->op_mode & DHD_FLAG_MP2P_MODE)) {
++					CFGP2P_ERR(("Multi p2p not supported"));
++					return BCME_ERROR;
++				}
++				if ((connected_cnt = wl_get_drv_status_all(cfg, CONNECTED)) > 1) {
++					CFGP2P_ERR(("Failed to create second p2p interface"
++						"Already one connection exists"));
++					return BCME_ERROR;
++				}
++			}
++		return i;
++		}
++	}
++	return BCME_ERROR;
++}
++
++s32
++wl_cfgp2p_init_discovery(struct bcm_cfg80211 *cfg)
++{
++
++	s32 bssidx = 0;
++	s32 ret = BCME_OK;
++
++	CFGP2P_DBG(("enter\n"));
++
++	if (wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE) > 0) {
++		CFGP2P_ERR(("do nothing, already initialized\n"));
++		return ret;
++	}
++
++	ret = wl_cfgp2p_set_discovery(cfg, 1);
++	if (ret < 0) {
++		CFGP2P_ERR(("set discover error\n"));
++		return ret;
++	}
++	/* Enable P2P Discovery in the WL Driver */
++	ret = wl_cfgp2p_get_disc_idx(cfg, &bssidx);
++
++	if (ret < 0) {
++		return ret;
++	}
++	/* In case of CFG80211 case, check if p2p_discovery interface has allocated p2p_wdev */
++	if (!cfg->p2p_wdev) {
++		CFGP2P_ERR(("p2p_wdev is NULL.\n"));
++		return BCME_NODEVICE;
++	}
++	/* Make an entry in the netinfo */
++	wl_alloc_netinfo(cfg, NULL, cfg->p2p_wdev, WL_MODE_BSS, 0, bssidx);
++
++	wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_DEVICE) =
++	    wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_PRIMARY);
++	wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE) = bssidx;
++
++	/* Set the initial discovery state to SCAN */
++	ret = wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_SCAN, 0, 0,
++		wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE));
++
++	if (unlikely(ret != 0)) {
++		CFGP2P_ERR(("unable to set WL_P2P_DISC_ST_SCAN\n"));
++		wl_cfgp2p_set_discovery(cfg, 0);
++		wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE) = 0;
++		wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_DEVICE) = NULL;
++		return 0;
++	}
++	return ret;
++}
++
++/* Deinitialize P2P Discovery
++ * Parameters :
++ * @cfg        : wl_private data
++ * Returns 0 if succes
++ */
++static s32
++wl_cfgp2p_deinit_discovery(struct bcm_cfg80211 *cfg)
++{
++	s32 ret = BCME_OK;
++	s32 bssidx;
++
++	CFGP2P_DBG(("enter\n"));
++	bssidx = wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++	if (bssidx <= 0) {
++		CFGP2P_ERR(("do nothing, not initialized\n"));
++		return -1;
++	}
++
++	/* Clear our saved WPS and P2P IEs for the discovery BSS */
++	wl_cfg80211_clear_per_bss_ies(cfg, bssidx);
++
++	/* Set the discovery state to SCAN */
++	wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_SCAN, 0, 0,
++	            bssidx);
++	/* Disable P2P discovery in the WL driver (deletes the discovery BSSCFG) */
++	ret = wl_cfgp2p_set_discovery(cfg, 0);
++
++	/* Remove the p2p disc entry in the netinfo */
++	wl_dealloc_netinfo_by_wdev(cfg, cfg->p2p_wdev);
++
++	wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE) = WL_INVALID;
++	wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_DEVICE) = NULL;
++
++	return ret;
++
++}
++/* Enable P2P Discovery
++ * Parameters:
++ * @cfg	: wl_private data
++ * @ie  : probe request ie (WPS IE + P2P IE)
++ * @ie_len   : probe request ie length
++ * Returns 0 if success.
++ */
++s32
++wl_cfgp2p_enable_discovery(struct bcm_cfg80211 *cfg, struct net_device *dev,
++	const u8 *ie, u32 ie_len)
++{
++	s32 ret = BCME_OK;
++	s32 bssidx;
++
++	CFGP2P_DBG(("enter\n"));
++	if (wl_get_p2p_status(cfg, DISCOVERY_ON)) {
++		CFGP2P_INFO((" DISCOVERY is already initialized, we have nothing to do\n"));
++		goto set_ie;
++	}
++
++	ret = wl_cfgp2p_init_discovery(cfg);
++	if (unlikely(ret < 0)) {
++		CFGP2P_ERR((" init discovery error %d\n", ret));
++		goto exit;
++	}
++
++	wl_set_p2p_status(cfg, DISCOVERY_ON);
++	/* Set wsec to any non-zero value in the discovery bsscfg to ensure our
++	 * P2P probe responses have the privacy bit set in the 802.11 WPA IE.
++	 * Some peer devices may not initiate WPS with us if this bit is not set.
++	 */
++	ret = wldev_iovar_setint_bsscfg(wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_DEVICE),
++			"wsec", AES_ENABLED, wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE));
++	if (unlikely(ret < 0)) {
++		CFGP2P_ERR((" wsec error %d\n", ret));
++	}
++set_ie:
++	if (ie_len) {
++
++		if (bcmcfg_to_prmry_ndev(cfg) == dev) {
++			bssidx = wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++		} else if ((bssidx = wl_get_bssidx_by_wdev(cfg, cfg->p2p_wdev)) < 0) {
++			WL_ERR(("Find p2p index from wdev(%p) failed\n", cfg->p2p_wdev));
++			return BCME_ERROR;
++		}
++
++		ret = wl_cfg80211_set_mgmt_vndr_ies(cfg, ndev_to_cfgdev(dev),
++			bssidx,
++			VNDR_IE_PRBREQ_FLAG, ie, ie_len);
++
++		if (unlikely(ret < 0)) {
++			CFGP2P_ERR(("set probreq ie occurs error %d\n", ret));
++			goto exit;
++		}
++	}
++exit:
++	return ret;
++}
++
++/* Disable P2P Discovery
++ * Parameters:
++ * @cfg       : wl_private_data
++ * Returns 0 if success.
++ */
++s32
++wl_cfgp2p_disable_discovery(struct bcm_cfg80211 *cfg)
++{
++	s32 ret = BCME_OK;
++	s32 bssidx;
++	CFGP2P_DBG((" enter\n"));
++	wl_clr_p2p_status(cfg, DISCOVERY_ON);
++
++#ifdef DHD_IFDEBUG
++	WL_ERR(("%s: (cfg)->p2p->bss[type].bssidx: %d\n",
++		__FUNCTION__, (cfg)->p2p->bss[P2PAPI_BSSCFG_DEVICE].bssidx));
++#endif
++	bssidx = wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++	if (bssidx <= 0) {
++		CFGP2P_ERR((" do nothing, not initialized\n"));
++		return 0;
++	}
++
++	ret = wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_SCAN, 0, 0,
++	            bssidx);
++
++	if (unlikely(ret < 0)) {
++
++		CFGP2P_ERR(("unable to set WL_P2P_DISC_ST_SCAN\n"));
++	}
++	/* Do a scan abort to stop the driver's scan engine in case it is still
++	 * waiting out an action frame tx dwell time.
++	 */
++	wl_clr_p2p_status(cfg, DISCOVERY_ON);
++	ret = wl_cfgp2p_deinit_discovery(cfg);
++	return ret;
++}
++
++s32
++wl_cfgp2p_escan(struct bcm_cfg80211 *cfg, struct net_device *dev, u16 active,
++	u32 num_chans, u16 *channels,
++	s32 search_state, u16 action, u32 bssidx, struct ether_addr *tx_dst_addr,
++	p2p_scan_purpose_t p2p_scan_purpose)
++{
++	s32 ret = BCME_OK;
++	s32 memsize;
++	s32 eparams_size;
++	u32 i;
++	s8 *memblk;
++	wl_p2p_scan_t *p2p_params;
++	wl_escan_params_t *eparams;
++	wlc_ssid_t ssid;
++	/* Scan parameters */
++#define P2PAPI_SCAN_NPROBES 1
++#define P2PAPI_SCAN_DWELL_TIME_MS 80
++#define P2PAPI_SCAN_SOCIAL_DWELL_TIME_MS 40
++#define P2PAPI_SCAN_HOME_TIME_MS 60
++#define P2PAPI_SCAN_NPROBS_TIME_MS 30
++#define P2PAPI_SCAN_AF_SEARCH_DWELL_TIME_MS 100
++
++	struct net_device *pri_dev = wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_PRIMARY);
++	/* Allocate scan params which need space for 3 channels and 0 ssids */
++	eparams_size = (WL_SCAN_PARAMS_FIXED_SIZE +
++	    OFFSETOF(wl_escan_params_t, params)) +
++		num_chans * sizeof(eparams->params.channel_list[0]);
++
++	memsize = sizeof(wl_p2p_scan_t) + eparams_size;
++	memblk = scanparambuf;
++	if (memsize > sizeof(scanparambuf)) {
++		CFGP2P_ERR((" scanpar buf too small (%u > %zu)\n",
++		    memsize, sizeof(scanparambuf)));
++		return -1;
++	}
++	memset(memblk, 0, memsize);
++	memset(cfg->ioctl_buf, 0, WLC_IOCTL_MAXLEN);
++	if (search_state == WL_P2P_DISC_ST_SEARCH) {
++		/*
++		 * If we in SEARCH STATE, we don't need to set SSID explictly
++		 * because dongle use P2P WILDCARD internally by default
++		 */
++		wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_SEARCH, 0, 0, bssidx);
++		/* use null ssid */
++		ssid.SSID_len = 0;
++		memset(&ssid.SSID, 0, sizeof(ssid.SSID));
++	} else if (search_state == WL_P2P_DISC_ST_SCAN) {
++		/* SCAN STATE 802.11 SCAN
++		 * WFD Supplicant has p2p_find command with (type=progressive, type= full)
++		 * So if P2P_find command with type=progressive,
++		 * we have to set ssid to P2P WILDCARD because
++		 * we just do broadcast scan unless setting SSID
++		 */
++		wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_SCAN, 0, 0, bssidx);
++		/* use wild card ssid */
++		ssid.SSID_len = WL_P2P_WILDCARD_SSID_LEN;
++		memset(&ssid.SSID, 0, sizeof(ssid.SSID));
++		memcpy(&ssid.SSID, WL_P2P_WILDCARD_SSID, WL_P2P_WILDCARD_SSID_LEN);
++	} else {
++		CFGP2P_ERR((" invalid search state %d\n", search_state));
++		return -1;
++	}
++
++
++	/* Fill in the P2P scan structure at the start of the iovar param block */
++	p2p_params = (wl_p2p_scan_t*) memblk;
++	p2p_params->type = 'E';
++	/* Fill in the Scan structure that follows the P2P scan structure */
++	eparams = (wl_escan_params_t*) (p2p_params + 1);
++	eparams->params.bss_type = DOT11_BSSTYPE_ANY;
++	if (active)
++		eparams->params.scan_type = DOT11_SCANTYPE_ACTIVE;
++	else
++		eparams->params.scan_type = DOT11_SCANTYPE_PASSIVE;
++
++	if (tx_dst_addr == NULL)
++		memcpy(&eparams->params.bssid, &ether_bcast, ETHER_ADDR_LEN);
++	else
++		memcpy(&eparams->params.bssid, tx_dst_addr, ETHER_ADDR_LEN);
++
++	if (ssid.SSID_len)
++		memcpy(&eparams->params.ssid, &ssid, sizeof(wlc_ssid_t));
++
++	eparams->params.home_time = htod32(P2PAPI_SCAN_HOME_TIME_MS);
++
++	switch (p2p_scan_purpose) {
++		case P2P_SCAN_SOCIAL_CHANNEL:
++		eparams->params.active_time = htod32(P2PAPI_SCAN_SOCIAL_DWELL_TIME_MS);
++			break;
++		case P2P_SCAN_AFX_PEER_NORMAL:
++		case P2P_SCAN_AFX_PEER_REDUCED:
++		eparams->params.active_time = htod32(P2PAPI_SCAN_AF_SEARCH_DWELL_TIME_MS);
++			break;
++		case P2P_SCAN_CONNECT_TRY:
++			eparams->params.active_time = htod32(WL_SCAN_CONNECT_DWELL_TIME_MS);
++			break;
++		default :
++			if (wl_get_drv_status_all(cfg, CONNECTED))
++		eparams->params.active_time = -1;
++	else
++		eparams->params.active_time = htod32(P2PAPI_SCAN_DWELL_TIME_MS);
++			break;
++	}
++
++	if (p2p_scan_purpose == P2P_SCAN_CONNECT_TRY)
++		eparams->params.nprobes = htod32(eparams->params.active_time /
++			WL_SCAN_JOIN_PROBE_INTERVAL_MS);
++	else
++	eparams->params.nprobes = htod32((eparams->params.active_time /
++		P2PAPI_SCAN_NPROBS_TIME_MS));
++
++
++	if (eparams->params.nprobes <= 0)
++		eparams->params.nprobes = 1;
++	CFGP2P_DBG(("nprobes # %d, active_time %d\n",
++		eparams->params.nprobes, eparams->params.active_time));
++	eparams->params.passive_time = htod32(-1);
++	eparams->params.channel_num = htod32((0 << WL_SCAN_PARAMS_NSSID_SHIFT) |
++	    (num_chans & WL_SCAN_PARAMS_COUNT_MASK));
++
++	for (i = 0; i < num_chans; i++) {
++		eparams->params.channel_list[i] = wl_ch_host_to_driver(bssidx, channels[i]);
++	}
++	eparams->version = htod32(ESCAN_REQ_VERSION);
++	eparams->action =  htod16(action);
++	wl_escan_set_sync_id(eparams->sync_id, cfg);
++	wl_escan_set_type(cfg, WL_SCANTYPE_P2P);
++	CFGP2P_INFO(("SCAN CHANNELS : "));
++
++	for (i = 0; i < num_chans; i++) {
++		if (i == 0) CFGP2P_INFO(("%d", channels[i]));
++		else CFGP2P_INFO((",%d", channels[i]));
++	}
++
++	CFGP2P_INFO(("\n"));
++
++	ret = wldev_iovar_setbuf_bsscfg(pri_dev, "p2p_scan",
++		memblk, memsize, cfg->ioctl_buf, WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++	WL_ERR(("P2P_SEARCH sync ID: %d, bssidx: %d\n", eparams->sync_id, bssidx));
++	if (ret == BCME_OK)
++		wl_set_p2p_status(cfg, SCANNING);
++	return ret;
++}
++
++/* search function to reach at common channel to send action frame
++ * Parameters:
++ * @cfg       : wl_private data
++ * @ndev     : net device for bssidx
++ * @bssidx   : bssidx for BSS
++ * Returns 0 if success.
++ */
++s32
++wl_cfgp2p_act_frm_search(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	s32 bssidx, s32 channel, struct ether_addr *tx_dst_addr)
++{
++	s32 ret = 0;
++	u32 chan_cnt = 0;
++	u16 *default_chan_list = NULL;
++	p2p_scan_purpose_t p2p_scan_purpose = P2P_SCAN_AFX_PEER_NORMAL;
++	if (!p2p_is_on(cfg) || ndev == NULL || bssidx == WL_INVALID)
++		return -EINVAL;
++	WL_TRACE_HW4((" Enter\n"));
++	if (bssidx == wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_PRIMARY))
++		bssidx = wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++	if (channel)
++		chan_cnt = AF_PEER_SEARCH_CNT;
++	else
++		chan_cnt = SOCIAL_CHAN_CNT;
++	default_chan_list = kzalloc(chan_cnt * sizeof(*default_chan_list), GFP_KERNEL);
++	if (default_chan_list == NULL) {
++		CFGP2P_ERR(("channel list allocation failed \n"));
++		ret = -ENOMEM;
++		goto exit;
++	}
++	if (channel) {
++		u32 i;
++		/* insert same channel to the chan_list */
++		for (i = 0; i < chan_cnt; i++) {
++			default_chan_list[i] = channel;
++		}
++	} else {
++		default_chan_list[0] = SOCIAL_CHAN_1;
++		default_chan_list[1] = SOCIAL_CHAN_2;
++		default_chan_list[2] = SOCIAL_CHAN_3;
++	}
++	ret = wl_cfgp2p_escan(cfg, ndev, true, chan_cnt,
++		default_chan_list, WL_P2P_DISC_ST_SEARCH,
++		WL_SCAN_ACTION_START, bssidx, NULL, p2p_scan_purpose);
++	kfree(default_chan_list);
++exit:
++	return ret;
++}
++
++/* Check whether pointed-to IE looks like WPA. */
++#define wl_cfgp2p_is_wpa_ie(ie, tlvs, len)	wl_cfgp2p_has_ie(ie, tlvs, len, \
++		(const uint8 *)WPS_OUI, WPS_OUI_LEN, WPA_OUI_TYPE)
++/* Check whether pointed-to IE looks like WPS. */
++#define wl_cfgp2p_is_wps_ie(ie, tlvs, len)	wl_cfgp2p_has_ie(ie, tlvs, len, \
++		(const uint8 *)WPS_OUI, WPS_OUI_LEN, WPS_OUI_TYPE)
++/* Check whether the given IE looks like WFA P2P IE. */
++#define wl_cfgp2p_is_p2p_ie(ie, tlvs, len)	wl_cfgp2p_has_ie(ie, tlvs, len, \
++		(const uint8 *)WFA_OUI, WFA_OUI_LEN, WFA_OUI_TYPE_P2P)
++/* Check whether the given IE looks like WFA WFDisplay IE. */
++#ifndef WFA_OUI_TYPE_WFD
++#define WFA_OUI_TYPE_WFD	0x0a			/* WiFi Display OUI TYPE */
++#endif
++#define wl_cfgp2p_is_wfd_ie(ie, tlvs, len)	wl_cfgp2p_has_ie(ie, tlvs, len, \
++		(const uint8 *)WFA_OUI, WFA_OUI_LEN, WFA_OUI_TYPE_WFD)
++
++
++/* Is any of the tlvs the expected entry? If
++ * not update the tlvs buffer pointer/length.
++ */
++static bool
++wl_cfgp2p_has_ie(u8 *ie, u8 **tlvs, u32 *tlvs_len, const u8 *oui, u32 oui_len, u8 type)
++{
++	/* If the contents match the OUI and the type */
++	if (ie[TLV_LEN_OFF] >= oui_len + 1 &&
++		!bcmp(&ie[TLV_BODY_OFF], oui, oui_len) &&
++		type == ie[TLV_BODY_OFF + oui_len]) {
++		return TRUE;
++	}
++
++	if (tlvs == NULL)
++		return FALSE;
++	/* point to the next ie */
++	ie += ie[TLV_LEN_OFF] + TLV_HDR_LEN;
++	/* calculate the length of the rest of the buffer */
++	*tlvs_len -= (int)(ie - *tlvs);
++	/* update the pointer to the start of the buffer */
++	*tlvs = ie;
++
++	return FALSE;
++}
++
++wpa_ie_fixed_t *
++wl_cfgp2p_find_wpaie(u8 *parse, u32 len)
++{
++	bcm_tlv_t *ie;
++
++	while ((ie = bcm_parse_tlvs(parse, (u32)len, DOT11_MNG_VS_ID))) {
++		if (wl_cfgp2p_is_wpa_ie((u8*)ie, &parse, &len)) {
++			return (wpa_ie_fixed_t *)ie;
++		}
++	}
++	return NULL;
++}
++
++wpa_ie_fixed_t *
++wl_cfgp2p_find_wpsie(u8 *parse, u32 len)
++{
++	bcm_tlv_t *ie;
++
++	while ((ie = bcm_parse_tlvs(parse, (u32)len, DOT11_MNG_VS_ID))) {
++		if (wl_cfgp2p_is_wps_ie((u8*)ie, &parse, &len)) {
++			return (wpa_ie_fixed_t *)ie;
++		}
++	}
++	return NULL;
++}
++
++wifi_p2p_ie_t *
++wl_cfgp2p_find_p2pie(u8 *parse, u32 len)
++{
++	bcm_tlv_t *ie;
++
++	while ((ie = bcm_parse_tlvs(parse, (int)len, DOT11_MNG_VS_ID))) {
++		if (wl_cfgp2p_is_p2p_ie((uint8*)ie, &parse, &len)) {
++			return (wifi_p2p_ie_t *)ie;
++		}
++	}
++	return NULL;
++}
++
++wifi_wfd_ie_t *
++wl_cfgp2p_find_wfdie(u8 *parse, u32 len)
++{
++	bcm_tlv_t *ie;
++
++	while ((ie = bcm_parse_tlvs(parse, (int)len, DOT11_MNG_VS_ID))) {
++		if (wl_cfgp2p_is_wfd_ie((uint8*)ie, &parse, &len)) {
++			return (wifi_wfd_ie_t *)ie;
++		}
++	}
++	return NULL;
++}
++u32
++wl_cfgp2p_vndr_ie(struct bcm_cfg80211 *cfg, u8 *iebuf, s32 pktflag,
++            s8 *oui, s32 ie_id, s8 *data, s32 datalen, const s8* add_del_cmd)
++{
++	vndr_ie_setbuf_t hdr;	/* aligned temporary vndr_ie buffer header */
++	s32 iecount;
++	u32 data_offset;
++
++	/* Validate the pktflag parameter */
++	if ((pktflag & ~(VNDR_IE_BEACON_FLAG | VNDR_IE_PRBRSP_FLAG |
++	            VNDR_IE_ASSOCRSP_FLAG | VNDR_IE_AUTHRSP_FLAG |
++	            VNDR_IE_PRBREQ_FLAG | VNDR_IE_ASSOCREQ_FLAG))) {
++		CFGP2P_ERR(("p2pwl_vndr_ie: Invalid packet flag 0x%x\n", pktflag));
++		return -1;
++	}
++
++	/* Copy the vndr_ie SET command ("add"/"del") to the buffer */
++	strncpy(hdr.cmd, add_del_cmd, VNDR_IE_CMD_LEN - 1);
++	hdr.cmd[VNDR_IE_CMD_LEN - 1] = '\0';
++
++	/* Set the IE count - the buffer contains only 1 IE */
++	iecount = htod32(1);
++	memcpy((void *)&hdr.vndr_ie_buffer.iecount, &iecount, sizeof(s32));
++
++	/* Copy packet flags that indicate which packets will contain this IE */
++	pktflag = htod32(pktflag);
++	memcpy((void *)&hdr.vndr_ie_buffer.vndr_ie_list[0].pktflag, &pktflag,
++		sizeof(u32));
++
++	/* Add the IE ID to the buffer */
++	hdr.vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.id = ie_id;
++
++	/* Add the IE length to the buffer */
++	hdr.vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.len =
++		(uint8) VNDR_IE_MIN_LEN + datalen;
++
++	/* Add the IE OUI to the buffer */
++	hdr.vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.oui[0] = oui[0];
++	hdr.vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.oui[1] = oui[1];
++	hdr.vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.oui[2] = oui[2];
++
++	/* Copy the aligned temporary vndr_ie buffer header to the IE buffer */
++	memcpy(iebuf, &hdr, sizeof(hdr) - 1);
++
++	/* Copy the IE data to the IE buffer */
++	data_offset =
++		(u8*)&hdr.vndr_ie_buffer.vndr_ie_list[0].vndr_ie_data.data[0] -
++		(u8*)&hdr;
++	memcpy(iebuf + data_offset, data, datalen);
++	return data_offset + datalen;
++
++}
++
++struct net_device *
++wl_cfgp2p_find_ndev(struct bcm_cfg80211 *cfg, s32 bssidx)
++{
++	u32 i;
++	struct net_device *ndev = NULL;
++	if (bssidx < 0) {
++		CFGP2P_ERR((" bsscfg idx is invalid\n"));
++		goto exit;
++	}
++
++	for (i = 0; i < P2PAPI_BSSCFG_MAX; i++) {
++		if (bssidx == wl_to_p2p_bss_bssidx(cfg, i)) {
++			ndev = wl_to_p2p_bss_ndev(cfg, i);
++			break;
++		}
++	}
++
++exit:
++	return ndev;
++}
++/*
++ * Search the driver array idx based on bssidx argument
++ * Parameters: Note that this idx is applicable only
++ * for primary and P2P interfaces. The virtual AP/STA is not
++ * covered here.
++ * @cfg     : wl_private data
++ * @bssidx : bssidx which indicate bsscfg->idx of firmware.
++ * @type   : output arg to store array idx of p2p->bss.
++ * Returns error
++ */
++
++s32
++wl_cfgp2p_find_type(struct bcm_cfg80211 *cfg, s32 bssidx, s32 *type)
++{
++	u32 i;
++	if (bssidx < 0 || type == NULL) {
++		CFGP2P_ERR((" argument is invalid\n"));
++		goto exit;
++	}
++
++	for (i = 0; i < P2PAPI_BSSCFG_MAX; i++) {
++		if (bssidx == wl_to_p2p_bss_bssidx(cfg, i)) {
++			*type = i;
++			return BCME_OK;
++		}
++	}
++
++exit:
++	return BCME_BADARG;
++}
++
++/*
++ * Callback function for WLC_E_P2P_DISC_LISTEN_COMPLETE
++ */
++s32
++wl_cfgp2p_listen_complete(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data)
++{
++	s32 ret = BCME_OK;
++	struct net_device *ndev = NULL;
++
++	if (!cfg || !cfg->p2p || !cfgdev)
++		return BCME_ERROR;
++
++	CFGP2P_DBG((" Enter\n"));
++#ifdef DHD_IFDEBUG
++	WL_ERR(("%s: cfg: %p, cfgdev: %p, cfg->wdev: %p, cfg->p2p_wdev: %p\n",
++		__FUNCTION__, cfg, cfgdev, cfg->wdev, cfg->p2p_wdev));
++#endif
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	if (wl_get_p2p_status(cfg, LISTEN_EXPIRED) == 0) {
++		wl_set_p2p_status(cfg, LISTEN_EXPIRED);
++		if (timer_pending(&cfg->p2p->listen_timer)) {
++			del_timer_sync(&cfg->p2p->listen_timer);
++		}
++
++		if (cfg->afx_hdl->is_listen == TRUE &&
++			wl_get_drv_status_all(cfg, FINDING_COMMON_CHANNEL)) {
++			WL_DBG(("Listen DONE for action frame\n"));
++			complete(&cfg->act_frm_scan);
++		}
++#ifdef WL_CFG80211_SYNC_GON
++		else if (wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM_LISTEN)) {
++			wl_clr_drv_status(cfg, WAITING_NEXT_ACT_FRM_LISTEN, ndev);
++			WL_DBG(("Listen DONE and wake up wait_next_af !!(%d)\n",
++				jiffies_to_msecs(jiffies - cfg->af_tx_sent_jiffies)));
++
++			if (wl_get_drv_status_all(cfg, WAITING_NEXT_ACT_FRM))
++				wl_clr_drv_status(cfg, WAITING_NEXT_ACT_FRM, ndev);
++
++			complete(&cfg->wait_next_af);
++		}
++#endif /* WL_CFG80211_SYNC_GON */
++
++#ifndef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++		if (wl_get_drv_status_all(cfg, REMAINING_ON_CHANNEL)) {
++#else
++		if (wl_get_drv_status_all(cfg, REMAINING_ON_CHANNEL) ||
++			wl_get_drv_status_all(cfg, FAKE_REMAINING_ON_CHANNEL)) {
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++			WL_DBG(("Listen DONE for remain on channel expired\n"));
++			wl_clr_drv_status(cfg, REMAINING_ON_CHANNEL, ndev);
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++			wl_clr_drv_status(cfg, FAKE_REMAINING_ON_CHANNEL, ndev);
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++			if (ndev && (ndev->ieee80211_ptr != NULL)) {
++#if defined(WL_CFG80211_P2P_DEV_IF)
++				if (cfgdev && ((struct wireless_dev *)cfgdev)->wiphy) {
++					/*
++					 * To prevent kernel panic,
++					 * if cfgdev->wiphy may be invalid, adding explicit check
++					 */
++					cfg80211_remain_on_channel_expired(cfgdev, cfg->last_roc_id,
++						&cfg->remain_on_chan, GFP_KERNEL);
++				} else {
++					CFGP2P_ERR(("Invalid cfgdev. Dropping the"
++						"remain_on_channel_expired event.\n"));
++				}
++#else
++				cfg80211_remain_on_channel_expired(cfgdev, cfg->last_roc_id,
++					&cfg->remain_on_chan, cfg->remain_on_chan_type, GFP_KERNEL);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++			}
++		}
++		if (wl_add_remove_eventmsg(bcmcfg_to_prmry_ndev(cfg),
++			WLC_E_P2P_PROBREQ_MSG, false) != BCME_OK) {
++			CFGP2P_ERR((" failed to unset WLC_E_P2P_PROPREQ_MSG\n"));
++		}
++	} else
++		wl_clr_p2p_status(cfg, LISTEN_EXPIRED);
++
++	return ret;
++
++}
++
++/*
++ *  Timer expire callback function for LISTEN
++ *  We can't report cfg80211_remain_on_channel_expired from Timer ISR context,
++ *  so lets do it from thread context.
++ */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++void wl_cfgp2p_listen_expired(struct timer_list *t)
++{
++	struct p2p_info *p2p = from_timer(p2p, t, listen_timer);
++	struct bcm_cfg80211 *cfg = p2p->cfg;
++#else
++void
++wl_cfgp2p_listen_expired(unsigned long data)
++{
++	struct bcm_cfg80211 *cfg = (struct bcm_cfg80211 *) data;
++#endif
++	wl_event_msg_t msg;
++	CFGP2P_DBG((" Enter\n"));
++	bzero(&msg, sizeof(wl_event_msg_t));
++	msg.event_type =  hton32(WLC_E_P2P_DISC_LISTEN_COMPLETE);
++	msg.bsscfgidx  =  wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE);
++#if defined(WL_ENABLE_P2P_IF)
++	wl_cfg80211_event(cfg->p2p_net ? cfg->p2p_net :
++		wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_DEVICE), &msg, NULL);
++#else
++	wl_cfg80211_event(wl_to_p2p_bss_ndev(cfg, P2PAPI_BSSCFG_DEVICE), &msg,
++		NULL);
++#endif /* WL_ENABLE_P2P_IF */
++}
++/*
++ *  Routine for cancelling the P2P LISTEN
++ */
++static s32
++wl_cfgp2p_cancel_listen(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++                         struct wireless_dev *wdev, bool notify)
++{
++	WL_DBG(("Enter \n"));
++	/* Irrespective of whether timer is running or not, reset
++	 * the LISTEN state.
++	 */
++	if (timer_pending(&cfg->p2p->listen_timer)) {
++		del_timer_sync(&cfg->p2p->listen_timer);
++		if (notify) {
++#if defined(WL_CFG80211_P2P_DEV_IF)
++			if (wdev)
++				cfg80211_remain_on_channel_expired(wdev, cfg->last_roc_id,
++					&cfg->remain_on_chan, GFP_KERNEL);
++#else
++			if (ndev && ndev->ieee80211_ptr)
++				cfg80211_remain_on_channel_expired(ndev, cfg->last_roc_id,
++					&cfg->remain_on_chan, cfg->remain_on_chan_type, GFP_KERNEL);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++		}
++	}
++	return 0;
++}
++/*
++ * Do a P2P Listen on the given channel for the given duration.
++ * A listen consists of sitting idle and responding to P2P probe requests
++ * with a P2P probe response.
++ *
++ * This fn assumes dongle p2p device discovery is already enabled.
++ * Parameters   :
++ * @cfg          : wl_private data
++ * @channel     : channel to listen
++ * @duration_ms : the time (milli seconds) to wait
++ */
++s32
++wl_cfgp2p_discover_listen(struct bcm_cfg80211 *cfg, s32 channel, u32 duration_ms)
++{
++#define EXTRA_DELAY_TIME	100
++	s32 ret = BCME_OK;
++	struct timer_list *_timer;
++	s32 extra_delay;
++	struct net_device *netdev = bcmcfg_to_prmry_ndev(cfg);
++
++	CFGP2P_DBG((" Enter Listen Channel : %d, Duration : %d\n", channel, duration_ms));
++	if (unlikely(wl_get_p2p_status(cfg, DISCOVERY_ON) == 0)) {
++
++		CFGP2P_ERR((" Discovery is not set, so we have noting to do\n"));
++
++		ret = BCME_NOTREADY;
++		goto exit;
++	}
++	if (timer_pending(&cfg->p2p->listen_timer)) {
++		CFGP2P_DBG(("previous LISTEN is not completed yet\n"));
++		goto exit;
++
++	}
++#ifndef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++	else
++		wl_clr_p2p_status(cfg, LISTEN_EXPIRED);
++#endif /* not WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++	if (wl_add_remove_eventmsg(netdev, WLC_E_P2P_PROBREQ_MSG, true) != BCME_OK) {
++			CFGP2P_ERR((" failed to set WLC_E_P2P_PROPREQ_MSG\n"));
++	}
++
++	ret = wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_LISTEN, channel, (u16) duration_ms,
++	            wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE));
++	_timer = &cfg->p2p->listen_timer;
++
++	/*  We will wait to receive WLC_E_P2P_DISC_LISTEN_COMPLETE from dongle ,
++	 *  otherwise we will wait up to duration_ms + 100ms + duration / 10
++	 */
++	if (ret == BCME_OK) {
++		extra_delay = EXTRA_DELAY_TIME + (duration_ms / 10);
++	} else {
++		/* if failed to set listen, it doesn't need to wait whole duration. */
++		duration_ms = 100 + duration_ms / 20;
++		extra_delay = 0;
++	}
++
++	INIT_TIMER(_timer, wl_cfgp2p_listen_expired, duration_ms, extra_delay);
++#ifdef WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST
++	wl_clr_p2p_status(cfg, LISTEN_EXPIRED);
++#endif /* WL_CFG80211_VSDB_PRIORITIZE_SCAN_REQUEST */
++
++#undef EXTRA_DELAY_TIME
++exit:
++	return ret;
++}
++
++
++s32
++wl_cfgp2p_discover_enable_search(struct bcm_cfg80211 *cfg, u8 enable)
++{
++	s32 ret = BCME_OK;
++	CFGP2P_DBG((" Enter\n"));
++	if (!wl_get_p2p_status(cfg, DISCOVERY_ON)) {
++
++		CFGP2P_DBG((" do nothing, discovery is off\n"));
++		return ret;
++	}
++	if (wl_get_p2p_status(cfg, SEARCH_ENABLED) == enable) {
++		CFGP2P_DBG(("already : %d\n", enable));
++		return ret;
++	}
++
++	wl_chg_p2p_status(cfg, SEARCH_ENABLED);
++	/* When disabling Search, reset the WL driver's p2p discovery state to
++	 * WL_P2P_DISC_ST_SCAN.
++	 */
++	if (!enable) {
++		wl_clr_p2p_status(cfg, SCANNING);
++		ret = wl_cfgp2p_set_p2p_mode(cfg, WL_P2P_DISC_ST_SCAN, 0, 0,
++		            wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_DEVICE));
++	}
++
++	return ret;
++}
++
++/*
++ * Callback function for WLC_E_ACTION_FRAME_COMPLETE, WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE
++ */
++s32
++wl_cfgp2p_action_tx_complete(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++            const wl_event_msg_t *e, void *data)
++{
++	s32 ret = BCME_OK;
++	u32 event_type = ntoh32(e->event_type);
++	u32 status = ntoh32(e->status);
++	struct net_device *ndev = NULL;
++	CFGP2P_DBG((" Enter\n"));
++
++	ndev = cfgdev_to_wlc_ndev(cfgdev, cfg);
++
++	if (wl_get_drv_status_all(cfg, SENDING_ACT_FRM)) {
++		if (event_type == WLC_E_ACTION_FRAME_COMPLETE) {
++
++			CFGP2P_INFO((" WLC_E_ACTION_FRAME_COMPLETE is received : %d\n", status));
++			if (status == WLC_E_STATUS_SUCCESS) {
++				wl_set_p2p_status(cfg, ACTION_TX_COMPLETED);
++				CFGP2P_DBG(("WLC_E_ACTION_FRAME_COMPLETE : ACK\n"));
++				if (!cfg->need_wait_afrx && cfg->af_sent_channel) {
++					CFGP2P_DBG(("no need to wait next AF.\n"));
++					wl_stop_wait_next_action_frame(cfg, ndev);
++				}
++			}
++			else if (!wl_get_p2p_status(cfg, ACTION_TX_COMPLETED)) {
++				wl_set_p2p_status(cfg, ACTION_TX_NOACK);
++				CFGP2P_INFO(("WLC_E_ACTION_FRAME_COMPLETE : NO ACK\n"));
++				wl_stop_wait_next_action_frame(cfg, ndev);
++			}
++		} else {
++			CFGP2P_INFO((" WLC_E_ACTION_FRAME_OFFCHAN_COMPLETE is received,"
++						"status : %d\n", status));
++
++			if (wl_get_drv_status_all(cfg, SENDING_ACT_FRM))
++				complete(&cfg->send_af_done);
++		}
++	}
++	return ret;
++}
++/* Send an action frame immediately without doing channel synchronization.
++ *
++ * This function does not wait for a completion event before returning.
++ * The WLC_E_ACTION_FRAME_COMPLETE event will be received when the action
++ * frame is transmitted.
++ * The WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE event will be received when an
++ * 802.11 ack has been received for the sent action frame.
++ */
++s32
++wl_cfgp2p_tx_action_frame(struct bcm_cfg80211 *cfg, struct net_device *dev,
++	wl_af_params_t *af_params, s32 bssidx)
++{
++	s32 ret = BCME_OK;
++	s32 evt_ret = BCME_OK;
++	s32 timeout = 0;
++	wl_eventmsg_buf_t buf;
++
++
++	CFGP2P_INFO(("\n"));
++	CFGP2P_INFO(("channel : %u , dwell time : %u\n",
++	    af_params->channel, af_params->dwell_time));
++
++	wl_clr_p2p_status(cfg, ACTION_TX_COMPLETED);
++	wl_clr_p2p_status(cfg, ACTION_TX_NOACK);
++
++	bzero(&buf, sizeof(wl_eventmsg_buf_t));
++	wl_cfg80211_add_to_eventbuffer(&buf, WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE, true);
++	wl_cfg80211_add_to_eventbuffer(&buf, WLC_E_ACTION_FRAME_COMPLETE, true);
++	if ((evt_ret = wl_cfg80211_apply_eventbuffer(bcmcfg_to_prmry_ndev(cfg), cfg, &buf)) < 0)
++		return evt_ret;
++
++	cfg->af_sent_channel  = af_params->channel;
++#ifdef WL_CFG80211_SYNC_GON
++	cfg->af_tx_sent_jiffies = jiffies;
++#endif /* WL_CFG80211_SYNC_GON */
++
++	ret = wldev_iovar_setbuf_bsscfg(dev, "actframe", af_params, sizeof(*af_params),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, bssidx, &cfg->ioctl_buf_sync);
++
++	if (ret < 0) {
++		CFGP2P_ERR((" sending action frame is failed\n"));
++		goto exit;
++	}
++
++	timeout = wait_for_completion_timeout(&cfg->send_af_done,
++		msecs_to_jiffies(af_params->dwell_time + WL_AF_TX_EXTRA_TIME_MAX));
++
++	if (timeout >= 0 && wl_get_p2p_status(cfg, ACTION_TX_COMPLETED)) {
++		CFGP2P_INFO(("tx action frame operation is completed\n"));
++		ret = BCME_OK;
++	} else if (ETHER_ISBCAST(&cfg->afx_hdl->tx_dst_addr)) {
++		CFGP2P_INFO(("bcast tx action frame operation is completed\n"));
++		ret = BCME_OK;
++	} else {
++		ret = BCME_ERROR;
++		CFGP2P_INFO(("tx action frame operation is failed\n"));
++	}
++	/* clear status bit for action tx */
++	wl_clr_p2p_status(cfg, ACTION_TX_COMPLETED);
++	wl_clr_p2p_status(cfg, ACTION_TX_NOACK);
++
++exit:
++	CFGP2P_INFO((" via act frame iovar : status = %d\n", ret));
++
++	bzero(&buf, sizeof(wl_eventmsg_buf_t));
++	wl_cfg80211_add_to_eventbuffer(&buf, WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE, false);
++	wl_cfg80211_add_to_eventbuffer(&buf, WLC_E_ACTION_FRAME_COMPLETE, false);
++	if ((evt_ret = wl_cfg80211_apply_eventbuffer(bcmcfg_to_prmry_ndev(cfg), cfg, &buf)) < 0) {
++		WL_ERR(("TX frame events revert back failed \n"));
++		return evt_ret;
++	}
++
++	return ret;
++}
++
++/* Generate our P2P Device Address and P2P Interface Address from our primary
++ * MAC address.
++ */
++void
++wl_cfgp2p_generate_bss_mac(struct bcm_cfg80211 *cfg, struct ether_addr *primary_addr)
++{
++	struct ether_addr *mac_addr = wl_to_p2p_bss_macaddr(cfg, P2PAPI_BSSCFG_DEVICE);
++	struct ether_addr *int_addr;
++
++	memcpy(mac_addr, primary_addr, sizeof(struct ether_addr));
++	mac_addr->octet[0] |= 0x02;
++	WL_DBG(("P2P Discovery address:"MACDBG "\n", MAC2STRDBG(mac_addr->octet)));
++
++	int_addr = wl_to_p2p_bss_macaddr(cfg, P2PAPI_BSSCFG_CONNECTION1);
++	memcpy(int_addr, mac_addr, sizeof(struct ether_addr));
++	int_addr->octet[4] ^= 0x80;
++	WL_DBG(("Primary P2P Interface address:"MACDBG "\n", MAC2STRDBG(int_addr->octet)));
++
++	int_addr = wl_to_p2p_bss_macaddr(cfg, P2PAPI_BSSCFG_CONNECTION2);
++	memcpy(int_addr, mac_addr, sizeof(struct ether_addr));
++	int_addr->octet[4] ^= 0x90;
++}
++
++/* P2P IF Address change to Virtual Interface MAC Address */
++void
++wl_cfg80211_change_ifaddr(u8* buf, struct ether_addr *p2p_int_addr, u8 element_id)
++{
++	wifi_p2p_ie_t *ie = (wifi_p2p_ie_t*) buf;
++	u16 len = ie->len;
++	u8 *subel;
++	u8 subelt_id;
++	u16 subelt_len;
++	CFGP2P_DBG((" Enter\n"));
++
++	/* Point subel to the P2P IE's subelt field.
++	 * Subtract the preceding fields (id, len, OUI, oui_type) from the length.
++	 */
++	subel = ie->subelts;
++	len -= 4;	/* exclude OUI + OUI_TYPE */
++
++	while (len >= 3) {
++	/* attribute id */
++		subelt_id = *subel;
++		subel += 1;
++		len -= 1;
++
++		/* 2-byte little endian */
++		subelt_len = *subel++;
++		subelt_len |= *subel++ << 8;
++
++		len -= 2;
++		len -= subelt_len;	/* for the remaining subelt fields */
++
++		if (subelt_id == element_id) {
++			if (subelt_id == P2P_SEID_INTINTADDR) {
++				memcpy(subel, p2p_int_addr->octet, ETHER_ADDR_LEN);
++				CFGP2P_INFO(("Intended P2P Interface Address ATTR FOUND\n"));
++			} else if (subelt_id == P2P_SEID_DEV_ID) {
++				memcpy(subel, p2p_int_addr->octet, ETHER_ADDR_LEN);
++				CFGP2P_INFO(("Device ID ATTR FOUND\n"));
++			} else if (subelt_id == P2P_SEID_DEV_INFO) {
++				memcpy(subel, p2p_int_addr->octet, ETHER_ADDR_LEN);
++				CFGP2P_INFO(("Device INFO ATTR FOUND\n"));
++			} else if (subelt_id == P2P_SEID_GROUP_ID) {
++				memcpy(subel, p2p_int_addr->octet, ETHER_ADDR_LEN);
++				CFGP2P_INFO(("GROUP ID ATTR FOUND\n"));
++			}			return;
++		} else {
++			CFGP2P_DBG(("OTHER id : %d\n", subelt_id));
++		}
++		subel += subelt_len;
++	}
++}
++/*
++ * Check if a BSS is up.
++ * This is a common implementation called by most OSL implementations of
++ * p2posl_bss_isup().  DO NOT call this function directly from the
++ * common code -- call p2posl_bss_isup() instead to allow the OSL to
++ * override the common implementation if necessary.
++ */
++bool
++wl_cfgp2p_bss_isup(struct net_device *ndev, int bsscfg_idx)
++{
++	s32 result, val;
++	bool isup = false;
++	s8 getbuf[64];
++
++	/* Check if the BSS is up */
++	*(int*)getbuf = -1;
++	result = wldev_iovar_getbuf_bsscfg(ndev, "bss", &bsscfg_idx,
++		sizeof(bsscfg_idx), getbuf, sizeof(getbuf), 0, NULL);
++	if (result != 0) {
++		CFGP2P_ERR(("'cfg bss -C %d' failed: %d\n", bsscfg_idx, result));
++		CFGP2P_ERR(("NOTE: this ioctl error is normal "
++					"when the BSS has not been created yet.\n"));
++	} else {
++		val = *(int*)getbuf;
++		val = dtoh32(val);
++		CFGP2P_INFO(("---cfg bss -C %d   ==> %d\n", bsscfg_idx, val));
++		isup = (val ? TRUE : FALSE);
++	}
++	return isup;
++}
++
++
++/* Bring up or down a BSS */
++s32
++wl_cfgp2p_bss(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 bsscfg_idx, s32 is_up)
++{
++	s32 ret = BCME_OK;
++	s32 val = is_up ? 1 : 0;
++
++	struct {
++		s32 cfg;
++		s32 val;
++	} bss_setbuf;
++
++	bss_setbuf.cfg = htod32(bsscfg_idx);
++	bss_setbuf.val = htod32(val);
++	CFGP2P_INFO(("---cfg bss -C %d %s\n", bsscfg_idx, is_up ? "up" : "down"));
++	ret = wldev_iovar_setbuf(ndev, "bss", &bss_setbuf, sizeof(bss_setbuf),
++		cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++
++	if (ret != 0) {
++		CFGP2P_ERR(("'bss %d' failed with %d\n", is_up, ret));
++	}
++
++	return ret;
++}
++
++/* Check if 'p2p' is supported in the driver */
++s32
++wl_cfgp2p_supported(struct bcm_cfg80211 *cfg, struct net_device *ndev)
++{
++	s32 ret = BCME_OK;
++	s32 p2p_supported = 0;
++	ret = wldev_iovar_getint(ndev, "p2p",
++	               &p2p_supported);
++	if (ret < 0) {
++		if (ret == BCME_UNSUPPORTED) {
++			CFGP2P_INFO(("p2p is unsupported\n"));
++			return 0;
++		} else {
++			CFGP2P_ERR(("cfg p2p error %d\n", ret));
++			return ret;
++		}
++	}
++	if (p2p_supported == 1) {
++		CFGP2P_INFO(("p2p is supported\n"));
++	} else {
++		CFGP2P_INFO(("p2p is unsupported\n"));
++		p2p_supported = 0;
++	}
++	return p2p_supported;
++}
++/* Cleanup P2P resources */
++s32
++wl_cfgp2p_down(struct bcm_cfg80211 *cfg)
++{
++	struct net_device *ndev = NULL;
++	struct wireless_dev *wdev = NULL;
++	s32 i = 0, index = -1;
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	ndev = bcmcfg_to_prmry_ndev(cfg);
++	wdev = bcmcfg_to_p2p_wdev(cfg);
++#elif defined(WL_ENABLE_P2P_IF)
++	ndev = cfg->p2p_net ? cfg->p2p_net : bcmcfg_to_prmry_ndev(cfg);
++	wdev = ndev_to_wdev(ndev);
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++	wl_cfgp2p_cancel_listen(cfg, ndev, wdev, TRUE);
++	wl_cfgp2p_disable_discovery(cfg);
++#if defined(WL_CFG80211_P2P_DEV_IF)
++	if (cfg->p2p_wdev) {
++		/* If p2p wdev is left out, clean it up */
++		WL_ERR(("Clean up the p2p discovery IF\n"));
++		wl_cfgp2p_del_p2p_disc_if(cfg->p2p_wdev, cfg);
++	}
++#endif /* WL_CFG80211_P2P_DEV_IF */
++	for (i = 0; i < P2PAPI_BSSCFG_MAX; i++) {
++			index = wl_to_p2p_bss_bssidx(cfg, i);
++			if (index != WL_INVALID)
++				wl_cfg80211_clear_per_bss_ies(cfg, index);
++	}
++	wl_cfgp2p_deinit_priv(cfg);
++	return 0;
++}
++
++int wl_cfgp2p_vif_created(struct bcm_cfg80211 *cfg)
++{
++	if (cfg->p2p && ((wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_CONNECTION1) != -1) ||
++		(wl_to_p2p_bss_bssidx(cfg, P2PAPI_BSSCFG_CONNECTION2) != -1)))
++		return true;
++	else
++		return false;
++
++}
++
++s32
++wl_cfgp2p_set_p2p_noa(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int len)
++{
++	s32 ret = -1;
++	int count, start, duration;
++	wl_p2p_sched_t dongle_noa;
++	s32 bssidx, type;
++	CFGP2P_DBG((" Enter\n"));
++
++	memset(&dongle_noa, 0, sizeof(dongle_noa));
++
++	if (wl_cfgp2p_vif_created(cfg)) {
++		cfg->p2p->noa.desc[0].start = 0;
++
++		sscanf(buf, "%10d %10d %10d", &count, &start, &duration);
++		CFGP2P_DBG(("set_p2p_noa count %d start %d duration %d\n",
++			count, start, duration));
++		if (count != -1)
++			cfg->p2p->noa.desc[0].count = count;
++
++		/* supplicant gives interval as start */
++		if (start != -1)
++			cfg->p2p->noa.desc[0].interval = start;
++
++		if (duration != -1)
++			cfg->p2p->noa.desc[0].duration = duration;
++
++		if (cfg->p2p->noa.desc[0].count != 255 && cfg->p2p->noa.desc[0].count != 0) {
++			cfg->p2p->noa.desc[0].start = 200;
++			dongle_noa.type = WL_P2P_SCHED_TYPE_REQ_ABS;
++			dongle_noa.action = WL_P2P_SCHED_ACTION_GOOFF;
++			dongle_noa.option = WL_P2P_SCHED_OPTION_TSFOFS;
++		}
++		else if (cfg->p2p->noa.desc[0].count == 0) {
++			cfg->p2p->noa.desc[0].start = 0;
++			dongle_noa.type = WL_P2P_SCHED_TYPE_ABS;
++			dongle_noa.option = WL_P2P_SCHED_OPTION_NORMAL;
++			dongle_noa.action = WL_P2P_SCHED_ACTION_RESET;
++		}
++		else {
++			/* Continuous NoA interval. */
++			dongle_noa.action = WL_P2P_SCHED_ACTION_DOZE;
++			dongle_noa.type = WL_P2P_SCHED_TYPE_ABS;
++			if ((cfg->p2p->noa.desc[0].interval == 102) ||
++				(cfg->p2p->noa.desc[0].interval == 100)) {
++				cfg->p2p->noa.desc[0].start = 100 -
++					cfg->p2p->noa.desc[0].duration;
++				dongle_noa.option = WL_P2P_SCHED_OPTION_BCNPCT;
++			}
++			else {
++				dongle_noa.option = WL_P2P_SCHED_OPTION_NORMAL;
++			}
++		}
++		/* Put the noa descriptor in dongle format for dongle */
++		dongle_noa.desc[0].count = htod32(cfg->p2p->noa.desc[0].count);
++		if (dongle_noa.option == WL_P2P_SCHED_OPTION_BCNPCT) {
++			dongle_noa.desc[0].start = htod32(cfg->p2p->noa.desc[0].start);
++			dongle_noa.desc[0].duration = htod32(cfg->p2p->noa.desc[0].duration);
++		}
++		else {
++			dongle_noa.desc[0].start = htod32(cfg->p2p->noa.desc[0].start*1000);
++			dongle_noa.desc[0].duration = htod32(cfg->p2p->noa.desc[0].duration*1000);
++		}
++		dongle_noa.desc[0].interval = htod32(cfg->p2p->noa.desc[0].interval*1000);
++		bssidx = wl_get_bssidx_by_wdev(cfg, ndev->ieee80211_ptr);
++		if (wl_cfgp2p_find_type(cfg, bssidx, &type) != BCME_OK)
++			return BCME_ERROR;
++
++		ret = wldev_iovar_setbuf(wl_to_p2p_bss_ndev(cfg, type),
++			"p2p_noa", &dongle_noa, sizeof(dongle_noa), cfg->ioctl_buf,
++			WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++
++		if (ret < 0) {
++			CFGP2P_ERR(("fw set p2p_noa failed %d\n", ret));
++		}
++	}
++	else {
++		CFGP2P_ERR(("ERROR: set_noa in non-p2p mode\n"));
++	}
++	return ret;
++}
++s32
++wl_cfgp2p_get_p2p_noa(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int buf_len)
++{
++
++	wifi_p2p_noa_desc_t *noa_desc;
++	int len = 0, i;
++	char _buf[200];
++
++	CFGP2P_DBG((" Enter\n"));
++	buf[0] = '\0';
++	if (wl_cfgp2p_vif_created(cfg)) {
++		if (cfg->p2p->noa.desc[0].count || cfg->p2p->ops.ops) {
++			_buf[0] = 1; /* noa index */
++			_buf[1] = (cfg->p2p->ops.ops ? 0x80: 0) |
++				(cfg->p2p->ops.ctw & 0x7f); /* ops + ctw */
++			len += 2;
++			if (cfg->p2p->noa.desc[0].count) {
++				noa_desc = (wifi_p2p_noa_desc_t*)&_buf[len];
++				noa_desc->cnt_type = cfg->p2p->noa.desc[0].count;
++				noa_desc->duration = cfg->p2p->noa.desc[0].duration;
++				noa_desc->interval = cfg->p2p->noa.desc[0].interval;
++				noa_desc->start = cfg->p2p->noa.desc[0].start;
++				len += sizeof(wifi_p2p_noa_desc_t);
++			}
++			if (buf_len <= len * 2) {
++				CFGP2P_ERR(("ERROR: buf_len %d in not enough for"
++					"returning noa in string format\n", buf_len));
++				return -1;
++			}
++			/* We have to convert the buffer data into ASCII strings */
++			for (i = 0; i < len; i++) {
++				snprintf(buf, 3, "%02x", _buf[i]);
++				buf += 2;
++			}
++			buf[i*2] = '\0';
++		}
++	}
++	else {
++		CFGP2P_ERR(("ERROR: get_noa in non-p2p mode\n"));
++		return -1;
++	}
++	return len * 2;
++}
++s32
++wl_cfgp2p_set_p2p_ps(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int len)
++{
++	int ps, ctw;
++	int ret = -1;
++	s32 legacy_ps;
++	s32 conn_idx;
++	s32 bssidx;
++	struct net_device *dev;
++
++	CFGP2P_DBG((" Enter\n"));
++	if (wl_cfgp2p_vif_created(cfg)) {
++		sscanf(buf, "%10d %10d %10d", &legacy_ps, &ps, &ctw);
++		CFGP2P_DBG((" Enter legacy_ps %d ps %d ctw %d\n", legacy_ps, ps, ctw));
++
++		bssidx = wl_get_bssidx_by_wdev(cfg, ndev->ieee80211_ptr);
++		if (wl_cfgp2p_find_type(cfg, bssidx, &conn_idx) != BCME_OK)
++			return BCME_ERROR;
++		dev = wl_to_p2p_bss_ndev(cfg, conn_idx);
++		if (ctw != -1) {
++			cfg->p2p->ops.ctw = ctw;
++			ret = 0;
++		}
++		if (ps != -1) {
++			cfg->p2p->ops.ops = ps;
++			ret = wldev_iovar_setbuf(dev,
++				"p2p_ops", &cfg->p2p->ops, sizeof(cfg->p2p->ops),
++				cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync);
++			if (ret < 0) {
++				CFGP2P_ERR(("fw set p2p_ops failed %d\n", ret));
++			}
++		}
++
++		if ((legacy_ps != -1) && ((legacy_ps == PM_MAX) || (legacy_ps == PM_OFF))) {
++			ret = wldev_ioctl(dev,
++				WLC_SET_PM, &legacy_ps, sizeof(legacy_ps), true);
++			if (unlikely(ret))
++				CFGP2P_ERR(("error (%d)\n", ret));
++			wl_cfg80211_update_power_mode(dev);
++		}
++		else
++			CFGP2P_ERR(("ilegal setting\n"));
++	}
++	else {
++		CFGP2P_ERR(("ERROR: set_p2p_ps in non-p2p mode\n"));
++		ret = -1;
++	}
++	return ret;
++}
++
++s32
++wl_cfgp2p_set_p2p_ecsa(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int len)
++{
++	int ch, bw;
++	s32 conn_idx;
++	s32 bssidx;
++	struct net_device *dev;
++	char smbuf[WLC_IOCTL_SMLEN];
++	wl_chan_switch_t csa_arg;
++	u32 chnsp = 0;
++	int err = 0;
++
++	CFGP2P_DBG((" Enter\n"));
++	if (wl_cfgp2p_vif_created(cfg)) {
++		sscanf(buf, "%10d %10d", &ch, &bw);
++		CFGP2P_DBG(("Enter ch %d bw %d\n", ch, bw));
++
++		bssidx = wl_get_bssidx_by_wdev(cfg, ndev->ieee80211_ptr);
++		if (wl_cfgp2p_find_type(cfg, bssidx, &conn_idx) != BCME_OK) {
++			return BCME_ERROR;
++		}
++		dev = wl_to_p2p_bss_ndev(cfg, conn_idx);
++		if (ch <= 0 || bw <= 0) {
++			CFGP2P_ERR(("Negative value not permitted!\n"));
++			return BCME_ERROR;
++		}
++
++		csa_arg.mode = DOT11_CSA_MODE_ADVISORY;
++		csa_arg.count = P2P_ECSA_CNT;
++		csa_arg.reg = 0;
++
++		sprintf(buf, "%d/%d", ch, bw);
++		chnsp = wf_chspec_aton(buf);
++		if (chnsp == 0) {
++			CFGP2P_ERR(("%s:chsp is not correct\n", __FUNCTION__));
++			return BCME_ERROR;
++		}
++		chnsp = wl_chspec_host_to_driver(chnsp);
++		csa_arg.chspec = chnsp;
++
++		err = wldev_iovar_setbuf(dev, "csa", &csa_arg, sizeof(csa_arg),
++			smbuf, sizeof(smbuf), NULL);
++		if (err) {
++			CFGP2P_ERR(("%s:set p2p_ecsa failed:%d\n", __FUNCTION__, err));
++			return BCME_ERROR;
++		}
++	} else {
++		CFGP2P_ERR(("ERROR: set_p2p_ecsa in non-p2p mode\n"));
++		return BCME_ERROR;
++	}
++	return BCME_OK;
++}
++
++u8 *
++wl_cfgp2p_retreive_p2pattrib(void *buf, u8 element_id)
++{
++	wifi_p2p_ie_t *ie = NULL;
++	u16 len = 0;
++	u8 *subel;
++	u8 subelt_id;
++	u16 subelt_len;
++
++	if (!buf) {
++		WL_ERR(("P2P IE not present"));
++		return 0;
++	}
++
++	ie = (wifi_p2p_ie_t*) buf;
++	len = ie->len;
++
++	/* Point subel to the P2P IE's subelt field.
++	 * Subtract the preceding fields (id, len, OUI, oui_type) from the length.
++	 */
++	subel = ie->subelts;
++	len -= 4;	/* exclude OUI + OUI_TYPE */
++
++	while (len >= 3) {
++		/* attribute id */
++		subelt_id = *subel;
++		subel += 1;
++		len -= 1;
++
++		/* 2-byte little endian */
++		subelt_len = *subel++;
++		subelt_len |= *subel++ << 8;
++
++		len -= 2;
++		len -= subelt_len;	/* for the remaining subelt fields */
++
++		if (subelt_id == element_id) {
++			/* This will point to start of subelement attrib after
++			 * attribute id & len
++			 */
++			return subel;
++		}
++
++		/* Go to next subelement */
++		subel += subelt_len;
++	}
++
++	/* Not Found */
++	return NULL;
++}
++
++#define P2P_GROUP_CAPAB_GO_BIT	0x01
++
++u8*
++wl_cfgp2p_find_attrib_in_all_p2p_Ies(u8 *parse, u32 len, u32 attrib)
++{
++	bcm_tlv_t *ie;
++	u8* pAttrib;
++
++	CFGP2P_INFO(("Starting parsing parse %p attrib %d remaining len %d ", parse, attrib, len));
++	while ((ie = bcm_parse_tlvs(parse, (int)len, DOT11_MNG_VS_ID))) {
++		if (wl_cfgp2p_is_p2p_ie((uint8*)ie, &parse, &len) == TRUE) {
++			/* Have the P2p ie. Now check for attribute */
++			if ((pAttrib = wl_cfgp2p_retreive_p2pattrib(parse, attrib)) != NULL) {
++				CFGP2P_INFO(("P2P attribute %d was found at parse %p",
++					attrib, parse));
++				return pAttrib;
++			}
++			else {
++				parse += (ie->len + TLV_HDR_LEN);
++				len -= (ie->len + TLV_HDR_LEN);
++				CFGP2P_INFO(("P2P Attribute %d not found Moving parse"
++					" to %p len to %d", attrib, parse, len));
++			}
++		}
++		else {
++			/* It was not p2p IE. parse will get updated automatically to next TLV */
++			CFGP2P_INFO(("IT was NOT P2P IE parse %p len %d", parse, len));
++		}
++	}
++	CFGP2P_ERR(("P2P attribute %d was NOT found", attrib));
++	return NULL;
++}
++
++u8 *
++wl_cfgp2p_retreive_p2p_dev_addr(wl_bss_info_t *bi, u32 bi_length)
++{
++	u8 *capability = NULL;
++	bool p2p_go	= 0;
++	u8 *ptr = NULL;
++
++	if ((capability = wl_cfgp2p_find_attrib_in_all_p2p_Ies(((u8 *) bi) + bi->ie_offset,
++	bi->ie_length, P2P_SEID_P2P_INFO)) == NULL) {
++		WL_ERR(("P2P Capability attribute not found"));
++		return NULL;
++	}
++
++	/* Check Group capability for Group Owner bit */
++	p2p_go = capability[1] & P2P_GROUP_CAPAB_GO_BIT;
++	if (!p2p_go) {
++		return bi->BSSID.octet;
++	}
++
++	/* In probe responses, DEVICE INFO attribute will be present */
++	if (!(ptr = wl_cfgp2p_find_attrib_in_all_p2p_Ies(((u8 *) bi) + bi->ie_offset,
++	bi->ie_length,  P2P_SEID_DEV_INFO))) {
++		/* If DEVICE_INFO is not found, this might be a beacon frame.
++		 * check for DEVICE_ID in the beacon frame.
++		 */
++		ptr = wl_cfgp2p_find_attrib_in_all_p2p_Ies(((u8 *) bi) + bi->ie_offset,
++		bi->ie_length,  P2P_SEID_DEV_ID);
++	}
++
++	if (!ptr)
++		WL_ERR((" Both DEVICE_ID & DEVICE_INFO attribute not present in P2P IE "));
++
++	return ptr;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
++static void
++wl_cfgp2p_ethtool_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *info)
++{
++	snprintf(info->driver, sizeof(info->driver), "p2p");
++	snprintf(info->version, sizeof(info->version), "%lu", (unsigned long)(0));
++}
++
++struct ethtool_ops cfgp2p_ethtool_ops = {
++	.get_drvinfo = wl_cfgp2p_ethtool_get_drvinfo
++};
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24) */
++
++#if defined(WL_ENABLE_P2P_IF)
++s32
++wl_cfgp2p_register_ndev(struct bcm_cfg80211 *cfg)
++{
++	int ret = 0;
++	struct net_device* net = NULL;
++	struct wireless_dev *wdev = NULL;
++	uint8 temp_addr[ETHER_ADDR_LEN] = { 0x00, 0x90, 0x4c, 0x33, 0x22, 0x11 };
++
++	if (cfg->p2p_net) {
++		CFGP2P_ERR(("p2p_net defined already.\n"));
++		return -EINVAL;
++	}
++
++	/* Allocate etherdev, including space for private structure */
++	if (!(net = alloc_etherdev(sizeof(struct bcm_cfg80211 *)))) {
++		CFGP2P_ERR(("%s: OOM - alloc_etherdev\n", __FUNCTION__));
++		return -ENODEV;
++	}
++
++	wdev = kzalloc(sizeof(*wdev), GFP_KERNEL);
++	if (unlikely(!wdev)) {
++		WL_ERR(("Could not allocate wireless device\n"));
++		free_netdev(net);
++		return -ENOMEM;
++	}
++
++	strncpy(net->name, "p2p%d", sizeof(net->name) - 1);
++	net->name[IFNAMSIZ - 1] = '\0';
++
++	/* Copy the reference to bcm_cfg80211 */
++	memcpy((void *)netdev_priv(net), &cfg, sizeof(struct bcm_cfg80211 *));
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31))
++	ASSERT(!net->open);
++	net->do_ioctl = wl_cfgp2p_do_ioctl;
++	net->hard_start_xmit = wl_cfgp2p_start_xmit;
++	net->open = wl_cfgp2p_if_open;
++	net->stop = wl_cfgp2p_if_stop;
++#else
++	ASSERT(!net->netdev_ops);
++	net->netdev_ops = &wl_cfgp2p_if_ops;
++#endif
++
++	/* Register with a dummy MAC addr */
++	memcpy(net->dev_addr, temp_addr, ETHER_ADDR_LEN);
++
++	wdev->wiphy = cfg->wdev->wiphy;
++
++	wdev->iftype = wl_mode_to_nl80211_iftype(WL_MODE_BSS);
++
++	net->ieee80211_ptr = wdev;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
++	net->ethtool_ops = &cfgp2p_ethtool_ops;
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24) */
++
++	SET_NETDEV_DEV(net, wiphy_dev(wdev->wiphy));
++
++	/* Associate p2p0 network interface with new wdev */
++	wdev->netdev = net;
++
++	ret = register_netdev(net);
++	if (ret) {
++		CFGP2P_ERR((" register_netdevice failed (%d)\n", ret));
++		free_netdev(net);
++		kfree(wdev);
++		return -ENODEV;
++	}
++
++	/* store p2p net ptr for further reference. Note that iflist won't have this
++	 * entry as there corresponding firmware interface is a "Hidden" interface.
++	 */
++	cfg->p2p_wdev = wdev;
++	cfg->p2p_net = net;
++
++	printk("%s: P2P Interface Registered\n", net->name);
++
++	return ret;
++}
++
++s32
++wl_cfgp2p_unregister_ndev(struct bcm_cfg80211 *cfg)
++{
++
++	if (!cfg || !cfg->p2p_net) {
++		CFGP2P_ERR(("Invalid Ptr\n"));
++		return -EINVAL;
++	}
++
++	unregister_netdev(cfg->p2p_net);
++	free_netdev(cfg->p2p_net);
++
++	return 0;
++}
++static int wl_cfgp2p_start_xmit(struct sk_buff *skb, struct net_device *ndev)
++{
++
++	if (skb)
++	{
++		CFGP2P_DBG(("(%s) is not used for data operations.Droping the packet.\n",
++			ndev->name));
++		dev_kfree_skb_any(skb);
++	}
++
++	return 0;
++}
++
++static int wl_cfgp2p_do_ioctl(struct net_device *net, struct ifreq *ifr, int cmd)
++{
++	int ret = 0;
++	struct bcm_cfg80211 *cfg = *(struct bcm_cfg80211 **)netdev_priv(net);
++	struct net_device *ndev = bcmcfg_to_prmry_ndev(cfg);
++
++	/* There is no ifidx corresponding to p2p0 in our firmware. So we should
++	 * not Handle any IOCTL cmds on p2p0 other than ANDROID PRIVATE CMDs.
++	 * For Android PRIV CMD handling map it to primary I/F
++	 */
++	if (cmd == SIOCDEVPRIVATE+1) {
++		ret = wl_android_priv_cmd(ndev, ifr, cmd);
++
++	} else {
++		CFGP2P_ERR(("%s: IOCTL req 0x%x on p2p0 I/F. Ignoring. \n",
++		__FUNCTION__, cmd));
++		return -1;
++	}
++
++	return ret;
++}
++#endif 
++
++#if defined(WL_ENABLE_P2P_IF)
++static int wl_cfgp2p_if_open(struct net_device *net)
++{
++	struct wireless_dev *wdev = net->ieee80211_ptr;
++
++	if (!wdev || !wl_cfg80211_is_p2p_active())
++		return -EINVAL;
++	WL_TRACE(("Enter\n"));
++#if !defined(WL_IFACE_COMB_NUM_CHANNELS)
++	/* If suppose F/W download (ifconfig wlan0 up) hasn't been done by now,
++	 * do it here. This will make sure that in concurrent mode, supplicant
++	 * is not dependent on a particular order of interface initialization.
++	 * i.e you may give wpa_supp -iwlan0 -N -ip2p0 or wpa_supp -ip2p0 -N
++	 * -iwlan0.
++	 */
++	wdev->wiphy->interface_modes |= (BIT(NL80211_IFTYPE_P2P_CLIENT)
++		| BIT(NL80211_IFTYPE_P2P_GO));
++#endif /* !WL_IFACE_COMB_NUM_CHANNELS */
++	wl_cfg80211_do_driver_init(net);
++
++	return 0;
++}
++
++static int wl_cfgp2p_if_stop(struct net_device *net)
++{
++	struct wireless_dev *wdev = net->ieee80211_ptr;
++
++	if (!wdev)
++		return -EINVAL;
++
++	wl_cfg80211_scan_stop(net);
++
++#if !defined(WL_IFACE_COMB_NUM_CHANNELS)
++	wdev->wiphy->interface_modes = (wdev->wiphy->interface_modes)
++					& (~(BIT(NL80211_IFTYPE_P2P_CLIENT)|
++					BIT(NL80211_IFTYPE_P2P_GO)));
++#endif /* !WL_IFACE_COMB_NUM_CHANNELS */
++	return 0;
++}
++
++bool wl_cfgp2p_is_ifops(const struct net_device_ops *if_ops)
++{
++	return (if_ops == &wl_cfgp2p_if_ops);
++}
++#endif /* WL_ENABLE_P2P_IF */
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++struct wireless_dev *
++wl_cfgp2p_add_p2p_disc_if(struct bcm_cfg80211 *cfg)
++{
++	struct wireless_dev *wdev = NULL;
++	struct ether_addr primary_mac;
++
++	if (!cfg || !cfg->p2p_supported)
++		return ERR_PTR(-EINVAL);
++
++	WL_TRACE(("Enter\n"));
++
++	if (cfg->p2p_wdev) {
++		 /*
++		* This is not expected. This can happen due to
++		* supplicant crash/unclean de-initialization which
++		* didn't free the p2p discovery interface. Indicate
++		* driver hang to user space so that the framework
++		* can rei-init the Wi-Fi.
++		*/
++		CFGP2P_ERR(("p2p_wdev defined already.\n"));
++		wl_probe_wdev_all(cfg);
++
++		net_os_send_hang_message(bcmcfg_to_prmry_ndev(cfg));
++		return ERR_PTR(-ENODEV);
++	}
++
++	wdev = kzalloc(sizeof(*wdev), GFP_KERNEL);
++	if (unlikely(!wdev)) {
++		WL_ERR(("Could not allocate wireless device\n"));
++		return ERR_PTR(-ENOMEM);
++	}
++
++	memset(&primary_mac, 0, sizeof(primary_mac));
++	get_primary_mac(cfg, &primary_mac);
++	wl_cfgp2p_generate_bss_mac(cfg, &primary_mac);
++
++	wdev->wiphy = cfg->wdev->wiphy;
++	wdev->iftype = NL80211_IFTYPE_P2P_DEVICE;
++	memcpy(wdev->address, wl_to_p2p_bss_macaddr(cfg, P2PAPI_BSSCFG_DEVICE), ETHER_ADDR_LEN);
++
++
++	/* store p2p wdev ptr for further reference. */
++	cfg->p2p_wdev = wdev;
++
++	CFGP2P_ERR(("P2P interface registered\n"));
++
++	return wdev;
++}
++
++int
++wl_cfgp2p_start_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev)
++{
++	int ret = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	if (!cfg)
++		return -EINVAL;
++
++	WL_TRACE(("Enter\n"));
++
++	ret = wl_cfgp2p_set_firm_p2p(cfg);
++	if (unlikely(ret < 0)) {
++		CFGP2P_ERR(("Set P2P in firmware failed, ret=%d\n", ret));
++		goto exit;
++	}
++
++	ret = wl_cfgp2p_enable_discovery(cfg, bcmcfg_to_prmry_ndev(cfg), NULL, 0);
++	if (unlikely(ret < 0)) {
++		CFGP2P_ERR(("P2P enable discovery failed, ret=%d\n", ret));
++		goto exit;
++	}
++
++	p2p_on(cfg) = true;
++#if defined(P2P_IE_MISSING_FIX)
++	cfg->p2p_prb_noti = false;
++#endif
++
++	CFGP2P_DBG(("P2P interface started\n"));
++
++exit:
++	return ret;
++}
++
++void
++wl_cfgp2p_stop_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev)
++{
++	int ret = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	if (!cfg)
++		return;
++
++	CFGP2P_DBG(("Enter\n"));
++
++	ret = wl_cfg80211_scan_stop(wdev);
++	if (unlikely(ret < 0)) {
++		CFGP2P_ERR(("P2P scan stop failed, ret=%d\n", ret));
++	}
++
++	if (!cfg->p2p)
++		return;
++
++	ret = wl_cfgp2p_disable_discovery(cfg);
++	if (unlikely(ret < 0)) {
++		CFGP2P_ERR(("P2P disable discovery failed, ret=%d\n", ret));
++	}
++
++	p2p_on(cfg) = false;
++
++	CFGP2P_DBG(("Exit. P2P interface stopped\n"));
++
++	return;
++}
++
++int
++wl_cfgp2p_del_p2p_disc_if(struct wireless_dev *wdev, struct bcm_cfg80211 *cfg)
++{
++	bool rollback_lock = false;
++
++	if (!wdev)
++		return -EINVAL;
++
++	WL_TRACE(("Enter\n"));
++
++	if (!rtnl_is_locked()) {
++		rtnl_lock();
++		rollback_lock = true;
++	}
++
++	cfg80211_unregister_wdev(wdev);
++
++	if (rollback_lock)
++		rtnl_unlock();
++
++	synchronize_rcu();
++
++	kfree(wdev);
++
++	if (cfg)
++		cfg->p2p_wdev = NULL;
++
++	CFGP2P_ERR(("P2P interface unregistered\n"));
++
++	return 0;
++}
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++void
++wl_cfgp2p_need_wait_actfrmae(struct bcm_cfg80211 *cfg, void *frame, u32 frame_len, bool tx)
++{
++	wifi_p2p_pub_act_frame_t *pact_frm;
++	int status = 0;
++
++	if (!frame || (frame_len < (sizeof(*pact_frm) + WL_P2P_AF_STATUS_OFFSET - 1))) {
++		return;
++	}
++
++	if (wl_cfgp2p_is_pub_action(frame, frame_len)) {
++		pact_frm = (wifi_p2p_pub_act_frame_t *)frame;
++		if (pact_frm->subtype == P2P_PAF_GON_RSP && tx) {
++			CFGP2P_ACTION(("Check TX P2P Group Owner Negotiation Rsp Frame status\n"));
++			status = pact_frm->elts[WL_P2P_AF_STATUS_OFFSET];
++			if (status) {
++				cfg->need_wait_afrx = false;
++				return;
++			}
++		}
++	}
++
++	cfg->need_wait_afrx = true;
++	return;
++}
++
++int
++wl_cfgp2p_is_p2p_specific_scan(struct cfg80211_scan_request *request)
++{
++	if (request && (request->n_ssids == 1) &&
++		(request->n_channels == 1) &&
++		IS_P2P_SSID(request->ssids[0].ssid, WL_P2P_WILDCARD_SSID_LEN) &&
++		(request->ssids[0].ssid_len > WL_P2P_WILDCARD_SSID_LEN)) {
++		return true;
++	}
++	return false;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgp2p.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgp2p.h
+new file mode 100644
+index 000000000..417650c61
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgp2p.h
+@@ -0,0 +1,441 @@
++/*
++ * Linux cfgp2p driver
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfgp2p.h 709309 2019-01-17 09:04:00Z $
++ */
++#ifndef _wl_cfgp2p_h_
++#define _wl_cfgp2p_h_
++#include <proto/802.11.h>
++#include <proto/p2p.h>
++
++struct bcm_cfg80211;
++extern u32 wl_dbg_level;
++
++typedef struct wifi_p2p_ie wifi_wfd_ie_t;
++/* Enumeration of the usages of the BSSCFGs used by the P2P Library.  Do not
++ * confuse this with a bsscfg index.  This value is an index into the
++ * saved_ie[] array of structures which in turn contains a bsscfg index field.
++ */
++typedef enum {
++	P2PAPI_BSSCFG_PRIMARY, /* maps to driver's primary bsscfg */
++	P2PAPI_BSSCFG_DEVICE, /* maps to driver's P2P device discovery bsscfg */
++	P2PAPI_BSSCFG_CONNECTION1, /* maps to driver's P2P connection bsscfg */
++	P2PAPI_BSSCFG_CONNECTION2,
++	P2PAPI_BSSCFG_MAX
++} p2p_bsscfg_type_t;
++
++typedef enum {
++	P2P_SCAN_PURPOSE_MIN,
++	P2P_SCAN_SOCIAL_CHANNEL, /* scan for social channel */
++	P2P_SCAN_AFX_PEER_NORMAL, /* scan for action frame search */
++	P2P_SCAN_AFX_PEER_REDUCED, /* scan for action frame search with short time */
++	P2P_SCAN_DURING_CONNECTED, /* scan during connected status */
++	P2P_SCAN_CONNECT_TRY, /* scan for connecting */
++	P2P_SCAN_NORMAL, /* scan during not-connected status */
++	P2P_SCAN_PURPOSE_MAX
++} p2p_scan_purpose_t;
++
++/* vendor ies max buffer length for probe response or beacon */
++#define VNDR_IES_MAX_BUF_LEN	1400
++/* normal vendor ies buffer length */
++#define VNDR_IES_BUF_LEN 		512
++
++struct p2p_bss {
++	s32 bssidx;
++	struct net_device *dev;
++	void *private_data;
++	struct ether_addr mac_addr;
++};
++
++struct p2p_info {
++	bool on;    /* p2p on/off switch */
++	bool scan;
++	int16 search_state;
++	s8 vir_ifname[IFNAMSIZ];
++	unsigned long status;
++	struct p2p_bss bss[P2PAPI_BSSCFG_MAX];
++	struct timer_list listen_timer;
++	wl_p2p_sched_t noa;
++	wl_p2p_ops_t ops;
++	wlc_ssid_t ssid;
++	s8 p2p_go_count;
++	struct bcm_cfg80211 *cfg;
++};
++
++#define MAX_VNDR_IE_NUMBER	5
++
++struct parsed_vndr_ie_info {
++	char *ie_ptr;
++	u32 ie_len;	/* total length including id & length field */
++	vndr_ie_t vndrie;
++};
++
++struct parsed_vndr_ies {
++	u32 count;
++	struct parsed_vndr_ie_info ie_info[MAX_VNDR_IE_NUMBER];
++};
++
++/* dongle status */
++enum wl_cfgp2p_status {
++	WLP2P_STATUS_DISCOVERY_ON = 0,
++	WLP2P_STATUS_SEARCH_ENABLED,
++	WLP2P_STATUS_IF_ADDING,
++	WLP2P_STATUS_IF_DELETING,
++	WLP2P_STATUS_IF_CHANGING,
++	WLP2P_STATUS_IF_CHANGED,
++	WLP2P_STATUS_LISTEN_EXPIRED,
++	WLP2P_STATUS_ACTION_TX_COMPLETED,
++	WLP2P_STATUS_ACTION_TX_NOACK,
++	WLP2P_STATUS_SCANNING,
++	WLP2P_STATUS_GO_NEG_PHASE,
++	WLP2P_STATUS_DISC_IN_PROGRESS
++};
++
++
++#define wl_to_p2p_bss_ndev(cfg, type)		((cfg)->p2p->bss[type].dev)
++#define wl_to_p2p_bss_bssidx(cfg, type)		((cfg)->p2p->bss[type].bssidx)
++#define wl_to_p2p_bss_macaddr(cfg, type)     &((cfg)->p2p->bss[type].mac_addr)
++#define wl_to_p2p_bss_saved_ie(cfg, type)	((cfg)->p2p->bss[type].saved_ie)
++#define wl_to_p2p_bss_private(cfg, type)		((cfg)->p2p->bss[type].private_data)
++#define wl_to_p2p_bss(cfg, type)			((cfg)->p2p->bss[type])
++#define wl_get_p2p_status(cfg, stat) ((!(cfg)->p2p_supported) ? 0 : \
++		test_bit(WLP2P_STATUS_ ## stat, &(cfg)->p2p->status))
++#define wl_set_p2p_status(cfg, stat) ((!(cfg)->p2p_supported) ? 0 : \
++		set_bit(WLP2P_STATUS_ ## stat, &(cfg)->p2p->status))
++#define wl_clr_p2p_status(cfg, stat) ((!(cfg)->p2p_supported) ? 0 : \
++		clear_bit(WLP2P_STATUS_ ## stat, &(cfg)->p2p->status))
++#define wl_chg_p2p_status(cfg, stat) ((!(cfg)->p2p_supported) ? 0 : \
++	change_bit(WLP2P_STATUS_ ## stat, &(cfg)->p2p->status))
++#define p2p_on(cfg) ((cfg)->p2p->on)
++#define p2p_scan(cfg) ((cfg)->p2p->scan)
++#define p2p_is_on(cfg) ((cfg)->p2p && (cfg)->p2p->on)
++
++/* dword align allocation */
++#define WLC_IOCTL_MAXLEN 8192
++
++#define CFGP2P_ERROR_TEXT		"CFGP2P-ERROR) "
++
++
++#define CFGP2P_ERR(args)									\
++	do {										\
++		if (wl_dbg_level & WL_DBG_ERR) {				\
++			printk(KERN_INFO CFGP2P_ERROR_TEXT "%s : ", __func__);	\
++			printk args;						\
++		}									\
++	} while (0)
++#define	CFGP2P_INFO(args)									\
++	do {										\
++		if (wl_dbg_level & WL_DBG_INFO) {				\
++			printk(KERN_INFO "CFGP2P-INFO) %s : ", __func__);	\
++			printk args;						\
++		}									\
++	} while (0)
++#define	CFGP2P_DBG(args)								\
++	do {									\
++		if (wl_dbg_level & WL_DBG_DBG) {			\
++			printk(KERN_DEBUG "CFGP2P-DEBUG) %s :", __func__);	\
++			printk args;							\
++		}									\
++	} while (0)
++
++#define	CFGP2P_ACTION(args)								\
++	do {									\
++		if (wl_dbg_level & WL_DBG_P2P_ACTION) {			\
++			printk(KERN_DEBUG "CFGP2P-ACTION) %s :", __func__);	\
++			printk args;							\
++		}									\
++	} while (0)
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++#define INIT_TIMER(timer, func, duration, extra_delay)	\
++	do {				   \
++		timer_setup(timer, func, 0); \
++		timer->expires = jiffies + msecs_to_jiffies(duration + extra_delay); \
++		add_timer(timer); \
++	} while (0);
++#else
++#define INIT_TIMER(timer, func, duration, extra_delay)	\
++	do {				   \
++		init_timer(timer); \
++		timer->function = func; \
++		timer->expires = jiffies + msecs_to_jiffies(duration + extra_delay); \
++		timer->data = (unsigned long) cfg; \
++		add_timer(timer); \
++	} while (0);
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) && !defined(WL_CFG80211_P2P_DEV_IF)
++#define WL_CFG80211_P2P_DEV_IF
++
++#ifdef WL_ENABLE_P2P_IF
++#undef WL_ENABLE_P2P_IF
++#endif
++
++#ifdef WL_SUPPORT_BACKPORTED_KPATCHES
++#undef WL_SUPPORT_BACKPORTED_KPATCHES
++#endif
++#else
++#ifdef WLP2P
++#ifndef WL_ENABLE_P2P_IF
++/* Enable P2P network Interface if P2P support is enabled */
++#define WL_ENABLE_P2P_IF
++#endif /* WL_ENABLE_P2P_IF */
++#endif /* WLP2P */
++#endif /* (LINUX_VERSION >= VERSION(3, 8, 0)) */
++
++#ifndef WL_CFG80211_P2P_DEV_IF
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++#if defined(WL_ENABLE_P2P_IF) && (defined(WL_CFG80211_P2P_DEV_IF) || \
++	(LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)))
++#error Disable 'WL_ENABLE_P2P_IF', if 'WL_CFG80211_P2P_DEV_IF' is enabled \
++	or kernel version is 3.8.0 or above
++#endif /* WL_ENABLE_P2P_IF && (WL_CFG80211_P2P_DEV_IF || (LINUX_VERSION >= VERSION(3, 8, 0))) */
++
++#if !defined(WLP2P) && (defined(WL_ENABLE_P2P_IF) || defined(WL_CFG80211_P2P_DEV_IF))
++#error WLP2P not defined
++#endif /* !WLP2P && (WL_ENABLE_P2P_IF || WL_CFG80211_P2P_DEV_IF) */
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++#define bcm_struct_cfgdev	struct wireless_dev
++#else
++#define bcm_struct_cfgdev	struct net_device
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++#define P2P_ECSA_CNT 50
++
++extern void
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++wl_cfgp2p_listen_expired(struct timer_list *t);
++#else
++wl_cfgp2p_listen_expired(unsigned long data);
++#endif
++extern bool
++wl_cfgp2p_is_pub_action(void *frame, u32 frame_len);
++extern bool
++wl_cfgp2p_is_p2p_action(void *frame, u32 frame_len);
++extern bool
++wl_cfgp2p_is_gas_action(void *frame, u32 frame_len);
++extern bool
++wl_cfgp2p_find_gas_subtype(u8 subtype, u8* data, u32 len);
++extern bool
++wl_cfgp2p_is_p2p_gas_action(void *frame, u32 frame_len);
++extern void
++wl_cfgp2p_print_actframe(bool tx, void *frame, u32 frame_len, u32 channel);
++extern s32
++wl_cfgp2p_init_priv(struct bcm_cfg80211 *cfg);
++extern void
++wl_cfgp2p_deinit_priv(struct bcm_cfg80211 *cfg);
++extern s32
++wl_cfgp2p_set_firm_p2p(struct bcm_cfg80211 *cfg);
++extern s32
++wl_cfgp2p_set_p2p_mode(struct bcm_cfg80211 *cfg, u8 mode,
++            u32 channel, u16 listen_ms, int bssidx);
++extern s32
++wl_cfgp2p_ifadd(struct bcm_cfg80211 *cfg, struct ether_addr *mac, u8 if_type,
++            chanspec_t chspec);
++extern s32
++wl_cfgp2p_ifdisable(struct bcm_cfg80211 *cfg, struct ether_addr *mac);
++extern s32
++wl_cfgp2p_ifdel(struct bcm_cfg80211 *cfg, struct ether_addr *mac);
++extern s32
++wl_cfgp2p_ifchange(struct bcm_cfg80211 *cfg, struct ether_addr *mac, u8 if_type,
++	chanspec_t chspec, s32 conn_idx);
++
++extern s32
++wl_cfgp2p_ifidx(struct bcm_cfg80211 *cfg, struct ether_addr *mac, s32 *index);
++
++extern s32
++wl_cfgp2p_init_discovery(struct bcm_cfg80211 *cfg);
++extern s32
++wl_cfgp2p_enable_discovery(struct bcm_cfg80211 *cfg, struct net_device *dev, const u8 *ie,
++	u32 ie_len);
++extern s32
++wl_cfgp2p_disable_discovery(struct bcm_cfg80211 *cfg);
++extern s32
++wl_cfgp2p_escan(struct bcm_cfg80211 *cfg, struct net_device *dev, u16 active, u32 num_chans,
++	u16 *channels,
++	s32 search_state, u16 action, u32 bssidx, struct ether_addr *tx_dst_addr,
++	p2p_scan_purpose_t p2p_scan_purpose);
++
++extern s32
++wl_cfgp2p_act_frm_search(struct bcm_cfg80211 *cfg, struct net_device *ndev,
++	s32 bssidx, s32 channel, struct ether_addr *tx_dst_addr);
++
++extern wpa_ie_fixed_t *
++wl_cfgp2p_find_wpaie(u8 *parse, u32 len);
++
++extern wpa_ie_fixed_t *
++wl_cfgp2p_find_wpsie(u8 *parse, u32 len);
++
++extern wifi_p2p_ie_t *
++wl_cfgp2p_find_p2pie(u8 *parse, u32 len);
++
++extern wifi_wfd_ie_t *
++wl_cfgp2p_find_wfdie(u8 *parse, u32 len);
++extern s32
++wl_cfgp2p_set_management_ie(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 bssidx,
++            s32 pktflag, const u8 *vndr_ie, u32 vndr_ie_len);
++extern s32
++wl_cfgp2p_clear_management_ie(struct bcm_cfg80211 *cfg, s32 bssidx);
++
++extern struct net_device *
++wl_cfgp2p_find_ndev(struct bcm_cfg80211 *cfg, s32 bssidx);
++extern s32
++wl_cfgp2p_find_type(struct bcm_cfg80211 *cfg, s32 bssidx, s32 *type);
++
++
++extern s32
++wl_cfgp2p_listen_complete(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++extern s32
++wl_cfgp2p_discover_listen(struct bcm_cfg80211 *cfg, s32 channel, u32 duration_ms);
++
++extern s32
++wl_cfgp2p_discover_enable_search(struct bcm_cfg80211 *cfg, u8 enable);
++
++extern s32
++wl_cfgp2p_action_tx_complete(struct bcm_cfg80211 *cfg, bcm_struct_cfgdev *cfgdev,
++	const wl_event_msg_t *e, void *data);
++
++extern s32
++wl_cfgp2p_tx_action_frame(struct bcm_cfg80211 *cfg, struct net_device *dev,
++	wl_af_params_t *af_params, s32 bssidx);
++
++extern void
++wl_cfgp2p_generate_bss_mac(struct bcm_cfg80211 *cfg, struct ether_addr *primary_addr);
++
++extern void
++wl_cfg80211_change_ifaddr(u8* buf, struct ether_addr *p2p_int_addr, u8 element_id);
++extern bool
++wl_cfgp2p_bss_isup(struct net_device *ndev, int bsscfg_idx);
++
++extern s32
++wl_cfgp2p_bss(struct bcm_cfg80211 *cfg, struct net_device *ndev, s32 bsscfg_idx, s32 up);
++
++
++extern s32
++wl_cfgp2p_supported(struct bcm_cfg80211 *cfg, struct net_device *ndev);
++
++extern s32
++wl_cfgp2p_down(struct bcm_cfg80211 *cfg);
++
++extern s32
++wl_cfgp2p_set_p2p_noa(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int len);
++
++extern s32
++wl_cfgp2p_get_p2p_noa(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int len);
++
++extern s32
++wl_cfgp2p_set_p2p_ps(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int len);
++
++extern s32
++wl_cfgp2p_set_p2p_ecsa(struct bcm_cfg80211 *cfg, struct net_device *ndev, char* buf, int len);
++
++extern u8 *
++wl_cfgp2p_retreive_p2pattrib(void *buf, u8 element_id);
++
++extern u8*
++wl_cfgp2p_find_attrib_in_all_p2p_Ies(u8 *parse, u32 len, u32 attrib);
++
++extern u8 *
++wl_cfgp2p_retreive_p2p_dev_addr(wl_bss_info_t *bi, u32 bi_length);
++
++extern s32
++wl_cfgp2p_register_ndev(struct bcm_cfg80211 *cfg);
++
++extern s32
++wl_cfgp2p_unregister_ndev(struct bcm_cfg80211 *cfg);
++
++extern bool
++wl_cfgp2p_is_ifops(const struct net_device_ops *if_ops);
++
++extern u32
++wl_cfgp2p_vndr_ie(struct bcm_cfg80211 *cfg, u8 *iebuf, s32 pktflag,
++	s8 *oui, s32 ie_id, s8 *data, s32 datalen, const s8* add_del_cmd);
++
++extern int wl_cfgp2p_get_conn_idx(struct bcm_cfg80211 *cfg);
++
++extern
++int wl_cfg_multip2p_operational(struct bcm_cfg80211 *cfg);
++
++extern
++int wl_cfgp2p_vif_created(struct bcm_cfg80211 *cfg);
++
++#if defined(WL_CFG80211_P2P_DEV_IF)
++extern struct wireless_dev *
++wl_cfgp2p_add_p2p_disc_if(struct bcm_cfg80211 *cfg);
++
++extern int
++wl_cfgp2p_start_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev);
++
++extern void
++wl_cfgp2p_stop_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev);
++
++extern int
++wl_cfgp2p_del_p2p_disc_if(struct wireless_dev *wdev, struct bcm_cfg80211 *cfg);
++
++#endif /* WL_CFG80211_P2P_DEV_IF */
++
++extern void
++wl_cfgp2p_need_wait_actfrmae(struct bcm_cfg80211 *cfg, void *frame, u32 frame_len, bool tx);
++
++extern int
++wl_cfgp2p_is_p2p_specific_scan(struct cfg80211_scan_request *request);
++
++/* WiFi Direct */
++#define SOCIAL_CHAN_1 1
++#define SOCIAL_CHAN_2 6
++#define SOCIAL_CHAN_3 11
++#define IS_P2P_SOCIAL_CHANNEL(channel) ((channel == SOCIAL_CHAN_1) || \
++					(channel == SOCIAL_CHAN_2) || \
++					(channel == SOCIAL_CHAN_3))
++#define SOCIAL_CHAN_CNT 3
++#define AF_PEER_SEARCH_CNT 2
++#define WL_P2P_WILDCARD_SSID "DIRECT-"
++#define WL_P2P_WILDCARD_SSID_LEN 7
++#define WL_P2P_INTERFACE_PREFIX "p2p"
++#define WL_P2P_TEMP_CHAN 11
++#define WL_P2P_AF_STATUS_OFFSET 9
++
++/* If the provision discovery is for JOIN operations,
++ * or the device discoverablity frame is destined to GO
++ * then we need not do an internal scan to find GO.
++ */
++#define IS_ACTPUB_WITHOUT_GROUP_ID(p2p_ie, len) \
++	(wl_cfgp2p_retreive_p2pattrib(p2p_ie, P2P_SEID_GROUP_ID) == NULL)
++
++#define IS_GAS_REQ(frame, len) (wl_cfgp2p_is_gas_action(frame, len) && \
++					((frame->action == P2PSD_ACTION_ID_GAS_IREQ) || \
++					(frame->action == P2PSD_ACTION_ID_GAS_CREQ)))
++
++#define IS_P2P_PUB_ACT_RSP_SUBTYPE(subtype) ((subtype == P2P_PAF_GON_RSP) || \
++							((subtype == P2P_PAF_GON_CONF) || \
++							(subtype == P2P_PAF_INVITE_RSP) || \
++							(subtype == P2P_PAF_PROVDIS_RSP)))
++#define IS_P2P_SOCIAL(ch) ((ch == SOCIAL_CHAN_1) || (ch == SOCIAL_CHAN_2) || (ch == SOCIAL_CHAN_3))
++#define IS_P2P_SSID(ssid, len) (!memcmp(ssid, WL_P2P_WILDCARD_SSID, WL_P2P_WILDCARD_SSID_LEN) && \
++					(len == WL_P2P_WILDCARD_SSID_LEN))
++#endif				/* _wl_cfgp2p_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgvendor.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgvendor.c
+new file mode 100644
+index 000000000..bcbee5b0c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgvendor.c
+@@ -0,0 +1,2892 @@
++/*
++ * Linux cfg80211 Vendor Extension Code
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfgvendor.c 455257 2014-02-20 08:10:24Z $
++ */
++
++/*
++ * New vendor interface additon to nl80211/cfg80211 to allow vendors
++ * to implement proprietary features over the cfg80211 stack.
++*/
++
++#include <typedefs.h>
++#include <linuxver.h>
++#include <osl.h>
++#include <linux/kernel.h>
++#include <linux/vmalloc.h>
++
++#include <bcmutils.h>
++#include <bcmwifi_channels.h>
++#include <bcmendian.h>
++#include <proto/ethernet.h>
++#include <proto/802.11.h>
++#include <linux/if_arp.h>
++#include <asm/uaccess.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++#include <dhd_debug.h>
++#include <dhdioctl.h>
++#include <wlioctl.h>
++#include <wlioctl_utils.h>
++#include <dhd_cfg80211.h>
++#ifdef PNO_SUPPORT
++#include <dhd_pno.h>
++#endif /* PNO_SUPPORT */
++#ifdef RTT_SUPPORT
++#include <dhd_rtt.h>
++#endif /* RTT_SUPPORT */
++#include <proto/ethernet.h>
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/netdevice.h>
++#include <linux/sched.h>
++#include <linux/etherdevice.h>
++#include <linux/wireless.h>
++#include <linux/ieee80211.h>
++#include <linux/wait.h>
++#include <net/cfg80211.h>
++#include <net/rtnetlink.h>
++
++#include <wlioctl.h>
++#include <wldev_common.h>
++#include <wl_cfg80211.h>
++#include <wl_cfgp2p.h>
++#include <wl_android.h>
++#include <wl_cfgvendor.h>
++
++#ifdef PROP_TXSTATUS
++#include <dhd_wlfc.h>
++#endif
++#include <brcm_nl80211.h>
++
++#if defined(WL_VENDOR_EXT_SUPPORT)
++/*
++ * This API is to be used for asynchronous vendor events. This
++ * shouldn't be used in response to a vendor command from its
++ * do_it handler context (instead wl_cfgvendor_send_cmd_reply should
++ * be used).
++ */
++int wl_cfgvendor_send_async_event(struct wiphy *wiphy,
++	struct net_device *dev, int event_id, const void  *data, int len)
++{
++	u16 kflags;
++	struct sk_buff *skb;
++
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++
++	/* Alloc the SKB for vendor_event */
++#if (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || \
++	LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
++	skb = cfg80211_vendor_event_alloc(wiphy, NULL, len, event_id, kflags);
++#else
++	skb = cfg80211_vendor_event_alloc(wiphy, len, event_id, kflags);
++#endif /* (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || */
++		/* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) */
++	if (!skb) {
++		WL_ERR(("skb alloc failed"));
++		return -ENOMEM;
++	}
++
++	/* Push the data to the skb */
++	nla_put_nohdr(skb, len, data);
++
++	cfg80211_vendor_event(skb, kflags);
++
++	return 0;
++}
++
++static int
++wl_cfgvendor_send_cmd_reply(struct wiphy *wiphy,
++	struct net_device *dev, const void  *data, int len)
++{
++	struct sk_buff *skb;
++
++	/* Alloc the SKB for vendor_event */
++	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len);
++	if (unlikely(!skb)) {
++		WL_ERR(("skb alloc failed"));
++		return -ENOMEM;
++	}
++
++	/* Push the data to the skb */
++	nla_put_nohdr(skb, len, data);
++
++	return cfg80211_vendor_cmd_reply(skb);
++}
++
++static int
++wl_cfgvendor_get_feature_set(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int reply;
++
++	reply = dhd_dev_get_feature_set(bcmcfg_to_prmry_ndev(cfg));
++
++	err =  wl_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++			&reply, sizeof(int));
++	if (unlikely(err))
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++
++	return err;
++}
++
++static int
++wl_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	struct sk_buff *skb;
++	int *reply;
++	int num, mem_needed, i;
++
++	reply = dhd_dev_get_feature_set_matrix(bcmcfg_to_prmry_ndev(cfg), &num);
++
++	if (!reply) {
++		WL_ERR(("Could not get feature list matrix\n"));
++		err = -EINVAL;
++		return err;
++	}
++	mem_needed = VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * num) +
++	             ATTRIBUTE_U32_LEN;
++
++	/* Alloc the SKB for vendor_event */
++	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		WL_ERR(("skb alloc failed"));
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET, num);
++	for (i = 0; i < num; i++) {
++		nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_FEATURE_SET, reply[i]);
++	}
++
++	err =  cfg80211_vendor_cmd_reply(skb);
++
++	if (unlikely(err))
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++
++exit:
++	kfree(reply);
++	return err;
++}
++
++static int
++wl_cfgvendor_set_rand_mac_oui(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type;
++	uint8 random_mac_oui[DOT11_OUI_LEN];
++
++	type = nla_type(data);
++
++	if (type == ANDR_WIFI_ATTRIBUTE_RANDOM_MAC_OUI) {
++		memcpy(random_mac_oui, nla_data(data), DOT11_OUI_LEN);
++
++		err = dhd_dev_cfg_rand_mac_oui(bcmcfg_to_prmry_ndev(cfg), random_mac_oui);
++
++		if (unlikely(err))
++			WL_ERR(("Bad OUI, could not set:%d \n", err));
++
++	} else {
++		err = -1;
++	}
++
++	return err;
++}
++
++#ifdef CUSTOM_FORCE_NODFS_FLAG
++static int
++wl_cfgvendor_set_nodfs_flag(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type;
++	u32 nodfs;
++
++	type = nla_type(data);
++	if (type == ANDR_WIFI_ATTRIBUTE_NODFS_SET) {
++		nodfs = nla_get_u32(data);
++		err = dhd_dev_set_nodfs(bcmcfg_to_prmry_ndev(cfg), nodfs);
++	} else {
++		err = -1;
++	}
++	return err;
++}
++#endif /* CUSTOM_FORCE_NODFS_FLAG */
++
++#ifdef GSCAN_SUPPORT
++int
++wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
++	struct net_device *dev, void  *data, int len, wl_vendor_event_t event)
++{
++	u16 kflags;
++	const void *ptr;
++	struct sk_buff *skb;
++	int malloc_len, total, iter_cnt_to_send, cnt;
++	gscan_results_cache_t *cache = (gscan_results_cache_t *)data;
++
++	total = len/sizeof(wifi_gscan_result_t);
++	while (total > 0) {
++		malloc_len = (total * sizeof(wifi_gscan_result_t)) + VENDOR_DATA_OVERHEAD;
++		if (malloc_len > NLMSG_DEFAULT_SIZE) {
++			malloc_len = NLMSG_DEFAULT_SIZE;
++		}
++		iter_cnt_to_send =
++		   (malloc_len - VENDOR_DATA_OVERHEAD)/sizeof(wifi_gscan_result_t);
++		total = total - iter_cnt_to_send;
++
++		kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++
++		/* Alloc the SKB for vendor_event */
++#if (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || \
++	LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
++		skb = cfg80211_vendor_event_alloc(wiphy, NULL, malloc_len, event, kflags);
++#else
++		skb = cfg80211_vendor_event_alloc(wiphy, malloc_len, event, kflags);
++#endif /* (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || */
++		/* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) */
++		if (!skb) {
++			WL_ERR(("skb alloc failed"));
++			return -ENOMEM;
++		}
++
++		while (cache && iter_cnt_to_send) {
++			ptr = (const void *) &cache->results[cache->tot_consumed];
++
++			if (iter_cnt_to_send < (cache->tot_count - cache->tot_consumed)) {
++				cnt = iter_cnt_to_send;
++			} else {
++				cnt = (cache->tot_count - cache->tot_consumed);
++			}
++
++			iter_cnt_to_send -= cnt;
++			cache->tot_consumed += cnt;
++			/* Push the data to the skb */
++			nla_append(skb, cnt * sizeof(wifi_gscan_result_t), ptr);
++			if (cache->tot_consumed == cache->tot_count) {
++				cache = cache->next;
++			}
++
++		}
++
++		cfg80211_vendor_event(skb, kflags);
++	}
++
++	return 0;
++}
++
++static int
++wl_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pno_gscan_capabilities_t *reply = NULL;
++	uint32 reply_len = 0;
++
++
++	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++	DHD_PNO_GET_CAPABILITIES, NULL, &reply_len);
++	if (!reply) {
++		WL_ERR(("Could not get capabilities\n"));
++		err = -EINVAL;
++		return err;
++	}
++
++	err =  wl_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++	               reply, reply_len);
++
++	if (unlikely(err)) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++	}
++
++	kfree(reply);
++	return err;
++}
++
++static int
++wl_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0, type, band;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	uint16 *reply = NULL;
++	uint32 reply_len = 0, num_channels, mem_needed;
++	struct sk_buff *skb;
++
++	type = nla_type(data);
++
++	if (type == GSCAN_ATTRIBUTE_BAND) {
++		band = nla_get_u32(data);
++	} else {
++		return -EINVAL;
++	}
++
++	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++	                 DHD_PNO_GET_CHANNEL_LIST, &band, &reply_len);
++
++	if (!reply) {
++		WL_ERR(("Could not get channel list\n"));
++		err = -EINVAL;
++		return err;
++	}
++	num_channels =  reply_len/ sizeof(uint32);
++	mem_needed = reply_len + VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * 2);
++
++	/* Alloc the SKB for vendor_event */
++	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		WL_ERR(("skb alloc failed"));
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_CHANNELS, num_channels);
++	nla_put(skb, GSCAN_ATTRIBUTE_CHANNEL_LIST, reply_len, reply);
++
++	err =  cfg80211_vendor_cmd_reply(skb);
++
++	if (unlikely(err)) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++	}
++exit:
++	kfree(reply);
++	return err;
++}
++
++static int
++wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_results_cache_t *results, *iter;
++	uint32 reply_len, complete = 1;
++	int32 mem_needed, num_results_iter;
++	wifi_gscan_result_t *ptr;
++	uint16 num_scan_ids, num_results;
++	struct sk_buff *skb;
++	struct nlattr *scan_hdr, *complete_flag;
++
++	err = dhd_dev_wait_batch_results_complete(bcmcfg_to_prmry_ndev(cfg));
++	if (err != BCME_OK)
++		return -EBUSY;
++
++	err = dhd_dev_pno_lock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++	if (err != BCME_OK) {
++		WL_ERR(("Can't obtain lock to access batch results %d\n", err));
++		return -EBUSY;
++	}
++	results = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++	             DHD_PNO_GET_BATCH_RESULTS, NULL, &reply_len);
++
++	if (!results) {
++		WL_ERR(("No results to send %d\n", err));
++		err =  wl_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++		        results, 0);
++
++		if (unlikely(err))
++			WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++		return err;
++	}
++	num_scan_ids = reply_len & 0xFFFF;
++	num_results = (reply_len & 0xFFFF0000) >> 16;
++	mem_needed = (num_results * sizeof(wifi_gscan_result_t)) +
++	             (num_scan_ids * GSCAN_BATCH_RESULT_HDR_LEN) +
++	             VENDOR_REPLY_OVERHEAD + SCAN_RESULTS_COMPLETE_FLAG_LEN;
++
++	if (mem_needed > (int32)NLMSG_DEFAULT_SIZE) {
++		mem_needed = (int32)NLMSG_DEFAULT_SIZE;
++	}
++
++	WL_TRACE(("complete %d mem_needed %d max_mem %d\n", complete, mem_needed,
++		(int)NLMSG_DEFAULT_SIZE));
++	/* Alloc the SKB for vendor_event */
++	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		WL_ERR(("skb alloc failed"));
++		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++		return -ENOMEM;
++	}
++	iter = results;
++	complete_flag = nla_reserve(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE,
++	                    sizeof(complete));
++	mem_needed = mem_needed - (SCAN_RESULTS_COMPLETE_FLAG_LEN + VENDOR_REPLY_OVERHEAD);
++
++	while (iter) {
++		num_results_iter = (mem_needed - (int32)GSCAN_BATCH_RESULT_HDR_LEN);
++		num_results_iter /= ((int32)sizeof(wifi_gscan_result_t));
++		if (num_results_iter <= 0 ||
++		    ((iter->tot_count - iter->tot_consumed) > num_results_iter)) {
++			break;
++		}
++		scan_hdr = nla_nest_start(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS);
++		/* no more room? we are done then (for now) */
++		if (scan_hdr == NULL) {
++			complete = 0;
++			break;
++		}
++		nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_ID, iter->scan_id);
++		nla_put_u8(skb, GSCAN_ATTRIBUTE_SCAN_FLAGS, iter->flag);
++		num_results_iter = iter->tot_count - iter->tot_consumed;
++
++		nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_OF_RESULTS, num_results_iter);
++		if (num_results_iter) {
++			ptr = &iter->results[iter->tot_consumed];
++			iter->tot_consumed += num_results_iter;
++			nla_put(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS,
++			 num_results_iter * sizeof(wifi_gscan_result_t), ptr);
++		}
++		nla_nest_end(skb, scan_hdr);
++		mem_needed -= GSCAN_BATCH_RESULT_HDR_LEN +
++			(num_results_iter * sizeof(wifi_gscan_result_t));
++		iter = iter->next;
++	}
++	/* Returns TRUE if all result consumed */
++	complete = dhd_dev_gscan_batch_cache_cleanup(bcmcfg_to_prmry_ndev(cfg));
++	memcpy(nla_data(complete_flag), &complete, sizeof(complete));
++	dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++	return cfg80211_vendor_cmd_reply(skb);
++}
++
++static int
++wl_cfgvendor_initiate_gscan(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type, tmp = len;
++	int run = 0xFF;
++	int flush = 0;
++	const struct nlattr *iter;
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++		if (type == GSCAN_ATTRIBUTE_ENABLE_FEATURE)
++			run = nla_get_u32(iter);
++		else if (type == GSCAN_ATTRIBUTE_FLUSH_FEATURE)
++			flush = nla_get_u32(iter);
++	}
++
++	if (run != 0xFF) {
++		err = dhd_dev_pno_run_gscan(bcmcfg_to_prmry_ndev(cfg), run, flush);
++
++		if (unlikely(err)) {
++			WL_ERR(("Could not run gscan:%d \n", err));
++		}
++		return err;
++	} else {
++		return -EINVAL;
++	}
++
++
++}
++
++static int
++wl_cfgvendor_enable_full_scan_result(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type;
++	bool real_time = FALSE;
++
++	type = nla_type(data);
++
++	if (type == GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS) {
++		real_time = nla_get_u32(data);
++
++		err = dhd_dev_pno_enable_full_scan_result(bcmcfg_to_prmry_ndev(cfg), real_time);
++
++		if (unlikely(err)) {
++			WL_ERR(("Could not run gscan:%d \n", err));
++		}
++
++	} else {
++		err = -EINVAL;
++	}
++
++	return err;
++}
++
++static int
++wl_cfgvendor_set_scan_cfg(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_scan_params_t *scan_param;
++	int j = 0;
++	int type, tmp, tmp1, tmp2, k = 0;
++	const struct nlattr *iter, *iter1, *iter2;
++	struct dhd_pno_gscan_channel_bucket  *ch_bucket;
++
++	scan_param = kzalloc(sizeof(gscan_scan_params_t), GFP_KERNEL);
++	if (!scan_param) {
++		WL_ERR(("Could not set GSCAN scan cfg, mem alloc failure\n"));
++		err = -EINVAL;
++		return err;
++
++	}
++
++	scan_param->scan_fr = PNO_SCAN_MIN_FW_SEC;
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++
++		if (j >= GSCAN_MAX_CH_BUCKETS) {
++			break;
++		}
++
++		switch (type) {
++			case GSCAN_ATTRIBUTE_BASE_PERIOD:
++				scan_param->scan_fr = nla_get_u32(iter)/1000;
++				break;
++			case GSCAN_ATTRIBUTE_NUM_BUCKETS:
++				scan_param->nchannel_buckets = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_CH_BUCKET_1:
++			case GSCAN_ATTRIBUTE_CH_BUCKET_2:
++			case GSCAN_ATTRIBUTE_CH_BUCKET_3:
++			case GSCAN_ATTRIBUTE_CH_BUCKET_4:
++			case GSCAN_ATTRIBUTE_CH_BUCKET_5:
++			case GSCAN_ATTRIBUTE_CH_BUCKET_6:
++			case GSCAN_ATTRIBUTE_CH_BUCKET_7:
++				nla_for_each_nested(iter1, iter, tmp1) {
++					type = nla_type(iter1);
++					ch_bucket =
++					scan_param->channel_bucket;
++
++					switch (type) {
++						case GSCAN_ATTRIBUTE_BUCKET_ID:
++						break;
++						case GSCAN_ATTRIBUTE_BUCKET_PERIOD:
++							ch_bucket[j].bucket_freq_multiple =
++							    nla_get_u32(iter1)/1000;
++							break;
++						case GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS:
++							ch_bucket[j].num_channels =
++							     nla_get_u32(iter1);
++							break;
++						case GSCAN_ATTRIBUTE_BUCKET_CHANNELS:
++							nla_for_each_nested(iter2, iter1, tmp2) {
++								if (k >=
++								 GSCAN_MAX_CHANNELS_IN_BUCKET)
++									break;
++								ch_bucket[j].chan_list[k] =
++								     nla_get_u32(iter2);
++								k++;
++							}
++							k = 0;
++							break;
++						case GSCAN_ATTRIBUTE_BUCKETS_BAND:
++							ch_bucket[j].band = (uint16)
++							     nla_get_u32(iter1);
++							break;
++						case GSCAN_ATTRIBUTE_REPORT_EVENTS:
++							ch_bucket[j].report_flag = (uint8)
++							     nla_get_u32(iter1);
++							break;
++						case GSCAN_ATTRIBUTE_BUCKET_STEP_COUNT:
++							ch_bucket[j].repeat = (uint16)
++							     nla_get_u32(iter1);
++							break;
++						case GSCAN_ATTRIBUTE_BUCKET_MAX_PERIOD:
++							ch_bucket[j].bucket_max_multiple =
++							     nla_get_u32(iter1)/1000;
++						default:
++							WL_ERR(("bucket attribute type error %d\n",
++							             type));
++							break;
++					}
++				}
++				j++;
++				break;
++			default:
++				WL_ERR(("Unknown type %d\n", type));
++				break;
++		}
++	}
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++	     DHD_PNO_SCAN_CFG_ID, scan_param, 0) < 0) {
++		WL_ERR(("Could not set GSCAN scan cfg\n"));
++		err = -EINVAL;
++	}
++
++	kfree(scan_param);
++	return err;
++
++}
++
++static int
++wl_cfgvendor_hotlist_cfg(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_hotlist_scan_params_t *hotlist_params;
++	int tmp, tmp1, tmp2, type, j = 0, dummy;
++	const struct nlattr *outer, *inner, *iter;
++	uint8 flush = 0;
++	struct bssid_t *pbssid;
++
++	hotlist_params = (gscan_hotlist_scan_params_t *)kzalloc(len, GFP_KERNEL);
++	if (!hotlist_params) {
++		WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes \n", len));
++		return -ENOMEM;
++	}
++
++	hotlist_params->lost_ap_window = GSCAN_LOST_AP_WINDOW_DEFAULT;
++	nla_for_each_attr(iter, data, len, tmp2) {
++		type = nla_type(iter);
++		switch (type) {
++			case GSCAN_ATTRIBUTE_HOTLIST_BSSIDS:
++				pbssid = hotlist_params->bssid;
++				nla_for_each_nested(outer, iter, tmp) {
++					nla_for_each_nested(inner, outer, tmp1) {
++						type = nla_type(inner);
++
++						switch (type) {
++							case GSCAN_ATTRIBUTE_BSSID:
++								memcpy(&(pbssid[j].macaddr),
++								  nla_data(inner), ETHER_ADDR_LEN);
++								break;
++							case GSCAN_ATTRIBUTE_RSSI_LOW:
++								pbssid[j].rssi_reporting_threshold =
++								         (int8) nla_get_u8(inner);
++								break;
++							case GSCAN_ATTRIBUTE_RSSI_HIGH:
++								dummy = (int8) nla_get_u8(inner);
++								break;
++							default:
++								WL_ERR(("ATTR unknown %d\n",
++								            type));
++								break;
++						}
++					}
++					j++;
++				}
++				hotlist_params->nbssid = j;
++				break;
++			case GSCAN_ATTRIBUTE_HOTLIST_FLUSH:
++				flush = nla_get_u8(iter);
++				break;
++			case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
++				hotlist_params->lost_ap_window = nla_get_u32(iter);
++				break;
++			default:
++				WL_ERR(("Unknown type %d\n", type));
++				break;
++			}
++
++	}
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++	                DHD_PNO_GEOFENCE_SCAN_CFG_ID,
++	                hotlist_params, flush) < 0) {
++		WL_ERR(("Could not set GSCAN HOTLIST cfg\n"));
++		err = -EINVAL;
++		goto exit;
++	}
++exit:
++	kfree(hotlist_params);
++	return err;
++}
++
++static int wl_cfgvendor_epno_cfg(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_epno_params_t *epno_params;
++	int tmp, tmp1, tmp2, type, num = 0;
++	const struct nlattr *outer, *inner, *iter;
++	uint8 flush = 0, i = 0;
++	uint16 num_visible_ssid = 0;
++
++	nla_for_each_attr(iter, data, len, tmp2) {
++		type = nla_type(iter);
++		switch (type) {
++			case GSCAN_ATTRIBUTE_EPNO_SSID_LIST:
++				nla_for_each_nested(outer, iter, tmp) {
++					epno_params = (dhd_epno_params_t *)
++					          dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++					                 DHD_PNO_GET_EPNO_SSID_ELEM, NULL, &num);
++					if (!epno_params) {
++						WL_ERR(("Failed to get SSID LIST buffer\n"));
++						err = -ENOMEM;
++						goto exit;
++					}
++					i++;
++					nla_for_each_nested(inner, outer, tmp1) {
++						type = nla_type(inner);
++
++						switch (type) {
++							case GSCAN_ATTRIBUTE_EPNO_SSID:
++								memcpy(epno_params->ssid,
++								  nla_data(inner),
++								  DOT11_MAX_SSID_LEN);
++								break;
++							case GSCAN_ATTRIBUTE_EPNO_SSID_LEN:
++								len = nla_get_u8(inner);
++								if (len < DOT11_MAX_SSID_LEN) {
++									epno_params->ssid_len = len;
++								} else {
++									WL_ERR(("SSID too"
++										"long %d\n", len));
++									err = -EINVAL;
++									goto exit;
++								}
++								break;
++							case GSCAN_ATTRIBUTE_EPNO_RSSI:
++								epno_params->rssi_thresh =
++								       (int8) nla_get_u32(inner);
++								break;
++							case GSCAN_ATTRIBUTE_EPNO_FLAGS:
++								epno_params->flags =
++								          nla_get_u8(inner);
++								if (!(epno_params->flags &
++								        DHD_PNO_USE_SSID))
++									num_visible_ssid++;
++								break;
++							case GSCAN_ATTRIBUTE_EPNO_AUTH:
++								epno_params->auth =
++								        nla_get_u8(inner);
++								break;
++						}
++					}
++				}
++				break;
++			case GSCAN_ATTRIBUTE_EPNO_SSID_NUM:
++				num = nla_get_u8(iter);
++				break;
++			case GSCAN_ATTRIBUTE_EPNO_FLUSH:
++				flush = nla_get_u8(iter);
++				dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++				           DHD_PNO_EPNO_CFG_ID, NULL, flush);
++				break;
++			default:
++				WL_ERR(("%s: No such attribute %d\n", __FUNCTION__, type));
++				err = -EINVAL;
++				goto exit;
++			}
++
++	}
++	if (i != num) {
++		WL_ERR(("%s: num_ssid %d does not match ssids sent %d\n", __FUNCTION__,
++		     num, i));
++		err = -EINVAL;
++	}
++exit:
++	/* Flush all configs if error condition */
++	flush = (err < 0) ? TRUE: FALSE;
++	dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++	   DHD_PNO_EPNO_CFG_ID, &num_visible_ssid, flush);
++	return err;
++}
++
++static int
++wl_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0, tmp, type;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_batch_params_t batch_param;
++	const struct nlattr *iter;
++
++	batch_param.mscan = batch_param.bestn = 0;
++	batch_param.buffer_threshold = GSCAN_BATCH_NO_THR_SET;
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++
++		switch (type) {
++			case GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN:
++				batch_param.bestn = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE:
++				batch_param.mscan = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_REPORT_THRESHOLD:
++				batch_param.buffer_threshold = nla_get_u32(iter);
++				break;
++			default:
++				WL_ERR(("Unknown type %d\n", type));
++				break;
++		}
++	}
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++	                DHD_PNO_BATCH_SCAN_CFG_ID,
++	                &batch_param, 0) < 0) {
++		WL_ERR(("Could not set batch cfg\n"));
++		err = -EINVAL;
++		return err;
++	}
++
++	return err;
++}
++
++static int
++wl_cfgvendor_significant_change_cfg(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_swc_params_t *significant_params;
++	int tmp, tmp1, tmp2, type, j = 0;
++	const struct nlattr *outer, *inner, *iter;
++	uint8 flush = 0;
++	wl_pfn_significant_bssid_t *bssid;
++	uint16 num_bssid = 0;
++	uint16 max_buf_size = sizeof(gscan_swc_params_t) +
++		sizeof(wl_pfn_significant_bssid_t) * (PFN_SWC_MAX_NUM_APS - 1);
++
++	significant_params = kzalloc(max_buf_size, GFP_KERNEL);
++	if (!significant_params) {
++		WL_ERR(("Cannot Malloc mem size:%d\n", max_buf_size));
++		return BCME_NOMEM;
++
++	}
++
++	nla_for_each_attr(iter, data, len, tmp2) {
++		type = nla_type(iter);
++		switch (type) {
++			case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH:
++				if (nla_len(iter) != sizeof(uint8)) {
++					WL_ERR(("type:%d length:%d not matching.\n",
++						type, nla_len(iter)));
++					err = -EINVAL;
++					goto exit;
++				}
++			flush = nla_get_u8(iter);
++			break;
++			case GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE:
++				if (nla_len(iter) != sizeof(uint16)) {
++					WL_ERR(("type:%d length:%d not matching.\n",
++						type, nla_len(iter)));
++					err = -EINVAL;
++					goto exit;
++				}
++				significant_params->rssi_window = nla_get_u16(iter);
++				break;
++			case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
++				if (nla_len(iter) != sizeof(uint16)) {
++					WL_ERR(("type:%d length:%d not matching\n",
++						type, nla_len(iter)));
++					err = -EINVAL;
++					goto exit;
++				}
++				significant_params->lost_ap_window = nla_get_u16(iter);
++				break;
++			case GSCAN_ATTRIBUTE_MIN_BREACHING:
++				if (nla_len(iter) != sizeof(uint16)) {
++					WL_ERR(("type:%d length:%d not matching\n",
++						type, nla_len(iter)));
++					err = -EINVAL;
++					goto exit;
++				}
++				significant_params->swc_threshold = nla_get_u16(iter);
++				break;
++			case GSCAN_ATTRIBUTE_NUM_BSSID:
++				num_bssid = nla_get_u16(iter);
++				if (num_bssid > PFN_SWC_MAX_NUM_APS) {
++					WL_ERR(("ovar max SWC bssids:%d\n",
++						num_bssid));
++					err = BCME_BADARG;
++					goto exit;
++				}
++				break;
++			case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS:
++
++				if (num_bssid == 0 || num_bssid > PFN_SWC_MAX_NUM_APS) {
++					WL_ERR(("Invalid num_bssid : %d\n", num_bssid));
++					err = BCME_BADARG;
++					goto exit;
++				}
++				bssid = significant_params->bssid_elem_list;
++				nla_for_each_nested(outer, iter, tmp) {
++					if ((j >= num_bssid) || (j > (PFN_SWC_MAX_NUM_APS - 1))) {
++						j++;
++						break;
++					}
++					nla_for_each_nested(inner, outer, tmp1) {
++						switch (nla_type(inner)) {
++							case GSCAN_ATTRIBUTE_BSSID:
++								if (nla_len(inner) !=
++									sizeof(bssid[j].macaddr)) {
++									WL_ERR((
++									"type:%d length:%d not matching.\n",
++									type, nla_len(inner)));
++									err = -EINVAL;
++									goto exit;
++								}
++								memcpy(&(bssid[j].macaddr),
++								       nla_data(inner),
++								       ETHER_ADDR_LEN);
++								break;
++							case GSCAN_ATTRIBUTE_RSSI_HIGH:
++								if (nla_len(inner) != sizeof(uint8)) {
++									WL_ERR((
++									"type:%d length:%d not matching.\n",
++										type, nla_len(inner)));
++									err = -EINVAL;
++									goto exit;
++								}
++								bssid[j].rssi_high_threshold
++									= (int8) nla_get_u8(inner);
++								break;
++							case GSCAN_ATTRIBUTE_RSSI_LOW:
++								if (nla_len(inner) != sizeof(uint8)) {
++									WL_ERR((
++									"type:%d length:%d not matching.\n",
++									type, nla_len(inner)));
++									err = -EINVAL;
++									goto exit;
++								}
++								bssid[j].rssi_low_threshold
++									 = (int8) nla_get_u8(inner);
++								break;
++							default:
++								WL_ERR(("ATTR unknown %d\n",
++								          type));
++								break;
++						}
++					}
++					j++;
++				}
++				break;
++			default:
++				WL_ERR(("Unknown type %d\n", type));
++				break;
++		}
++	}
++	if (j != num_bssid) {
++		WL_ERR(("swc bssids count:%d not matched to num_bssid:%d\n",
++			j, num_bssid));
++		err = BCME_BADARG;
++		goto exit;
++	}
++	significant_params->nbssid = j;
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++	              DHD_PNO_SIGNIFICANT_SCAN_CFG_ID,
++	              significant_params, flush) < 0) {
++		WL_ERR(("Could not set GSCAN significant cfg\n"));
++		err = BCME_ERROR;
++		goto exit;
++	}
++exit:
++	kfree(significant_params);
++	return err;
++}
++#endif /* GSCAN_SUPPORT */
++#ifdef RTT_SUPPORT
++void
++wl_cfgvendor_rtt_evt(void *ctx, void *rtt_data)
++{
++	struct wireless_dev *wdev = (struct wireless_dev *)ctx;
++	struct wiphy *wiphy;
++	struct sk_buff *skb;
++	uint32 complete = 0;
++	gfp_t kflags;
++	rtt_result_t *rtt_result;
++	rtt_results_header_t *rtt_header;
++	struct list_head *rtt_cache_list;
++	struct nlattr *rtt_nl_hdr;
++	wiphy = wdev->wiphy;
++
++	WL_DBG(("In\n"));
++	/* Push the data to the skb */
++	if (!rtt_data) {
++		WL_ERR(("rtt_data is NULL\n"));
++		return;
++	}
++	rtt_cache_list = (struct list_head *)rtt_data;
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	if (list_empty(rtt_cache_list)) {
++#if (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || \
++	LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
++		skb = cfg80211_vendor_event_alloc(wiphy, NULL, 100,
++			GOOGLE_RTT_COMPLETE_EVENT, kflags);
++#else
++		skb = cfg80211_vendor_event_alloc(wiphy, 100, GOOGLE_RTT_COMPLETE_EVENT, kflags);
++#endif /* (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || */
++		/* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) */
++		if (!skb) {
++			WL_ERR(("skb alloc failed"));
++			return;
++		}
++		complete = 1;
++		nla_put_u32(skb, RTT_ATTRIBUTE_RESULTS_COMPLETE, complete);
++		cfg80211_vendor_event(skb, kflags);
++		return;
++	}
++	list_for_each_entry(rtt_header, rtt_cache_list, list) {
++		/* Alloc the SKB for vendor_event */
++#if (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || \
++	LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
++		skb = cfg80211_vendor_event_alloc(wiphy, NULL, rtt_header->result_tot_len + 100,
++			GOOGLE_RTT_COMPLETE_EVENT, kflags);
++#else
++		skb = cfg80211_vendor_event_alloc(wiphy, rtt_header->result_tot_len + 100,
++			GOOGLE_RTT_COMPLETE_EVENT, kflags);
++#endif /* (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || */
++		/* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) */
++		if (!skb) {
++			WL_ERR(("skb alloc failed"));
++			return;
++		}
++		if (list_is_last(&rtt_header->list, rtt_cache_list)) {
++			complete = 1;
++		}
++		nla_put_u32(skb, RTT_ATTRIBUTE_RESULTS_COMPLETE, complete);
++		rtt_nl_hdr = nla_nest_start(skb, RTT_ATTRIBUTE_RESULTS_PER_TARGET);
++		if (!rtt_nl_hdr) {
++			WL_ERR(("rtt_nl_hdr is NULL\n"));
++			break;
++		}
++		nla_put(skb, RTT_ATTRIBUTE_TARGET_MAC, ETHER_ADDR_LEN, &rtt_header->peer_mac);
++		nla_put_u32(skb, RTT_ATTRIBUTE_RESULT_CNT, rtt_header->result_cnt);
++		list_for_each_entry(rtt_result, &rtt_header->result_list, list) {
++			nla_put(skb, RTT_ATTRIBUTE_RESULT,
++				rtt_result->report_len, &rtt_result->report);
++		}
++		nla_nest_end(skb, rtt_nl_hdr);
++		cfg80211_vendor_event(skb, kflags);
++	}
++}
++
++static int
++wl_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev *wdev,
++	const void *data, int len) {
++	int err = 0, rem, rem1, rem2, type;
++	int target_cnt;
++	rtt_config_params_t rtt_param;
++	rtt_target_info_t* rtt_target = NULL;
++	const struct nlattr *iter, *iter1, *iter2;
++	int8 eabuf[ETHER_ADDR_STR_LEN];
++	int8 chanbuf[CHANSPEC_STR_LEN];
++	int32 feature_set = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	rtt_capabilities_t capability;
++	feature_set = dhd_dev_get_feature_set(bcmcfg_to_prmry_ndev(cfg));
++
++	WL_DBG(("In\n"));
++	err = dhd_dev_rtt_register_noti_callback(wdev->netdev, wdev, wl_cfgvendor_rtt_evt);
++	if (err < 0) {
++		WL_ERR(("failed to register rtt_noti_callback\n"));
++		goto exit;
++	}
++	err = dhd_dev_rtt_capability(bcmcfg_to_prmry_ndev(cfg), &capability);
++	if (err < 0) {
++		WL_ERR(("failed to get the capability\n"));
++		goto exit;
++	}
++	memset(&rtt_param, 0, sizeof(rtt_param));
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++		case RTT_ATTRIBUTE_TARGET_CNT:
++			target_cnt = nla_get_u8(iter);
++			if (rtt_param.rtt_target_cnt > RTT_MAX_TARGET_CNT) {
++				WL_ERR(("exceed max target count : %d\n",
++					target_cnt));
++				err = BCME_RANGE;
++				goto exit;
++			}
++			rtt_param.rtt_target_cnt = target_cnt;
++			rtt_param.target_info = kzalloc(TARGET_INFO_SIZE(target_cnt), GFP_KERNEL);
++			if (rtt_param.target_info == NULL) {
++				WL_ERR(("failed to allocate target info for (%d)\n", target_cnt));
++				err = BCME_NOMEM;
++				goto exit;
++			}
++			break;
++		case RTT_ATTRIBUTE_TARGET_INFO:
++			rtt_target = rtt_param.target_info;
++			nla_for_each_nested(iter1, iter, rem1) {
++				nla_for_each_nested(iter2, iter1, rem2) {
++					type = nla_type(iter2);
++					switch (type) {
++					case RTT_ATTRIBUTE_TARGET_MAC:
++						memcpy(&rtt_target->addr, nla_data(iter2),
++							ETHER_ADDR_LEN);
++						break;
++					case RTT_ATTRIBUTE_TARGET_TYPE:
++						rtt_target->type = nla_get_u8(iter2);
++						if (rtt_target->type == RTT_INVALID ||
++							(rtt_target->type == RTT_ONE_WAY &&
++							!capability.rtt_one_sided_supported)) {
++							WL_ERR(("doesn't support RTT type"
++								" : %d\n",
++								rtt_target->type));
++							err = -EINVAL;
++							goto exit;
++						}
++						break;
++					case RTT_ATTRIBUTE_TARGET_PEER:
++						rtt_target->peer = nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_CHAN:
++						memcpy(&rtt_target->channel, nla_data(iter2),
++							sizeof(rtt_target->channel));
++						break;
++					case RTT_ATTRIBUTE_TARGET_PERIOD:
++						rtt_target->burst_period = nla_get_u32(iter2);
++						if (rtt_target->burst_period < 32) {
++							/* 100ms unit */
++							rtt_target->burst_period *= 100;
++						} else {
++							WL_ERR(("%d value must in (0-31)\n",
++								rtt_target->burst_period));
++							err = EINVAL;
++							goto exit;
++						}
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_BURST:
++						rtt_target->num_burst = nla_get_u32(iter2);
++						if (rtt_target->num_burst > 16) {
++							WL_ERR(("%d value must in (0-15)\n",
++								rtt_target->num_burst));
++							err = -EINVAL;
++							goto exit;
++						}
++						rtt_target->num_burst = BIT(rtt_target->num_burst);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_FTM_BURST:
++						rtt_target->num_frames_per_burst =
++						nla_get_u32(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_RETRY_FTM:
++						rtt_target->num_retries_per_ftm =
++						nla_get_u32(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_RETRY_FTMR:
++						rtt_target->num_retries_per_ftmr =
++						nla_get_u32(iter2);
++						if (rtt_target->num_retries_per_ftmr > 3) {
++							WL_ERR(("%d value must in (0-3)\n",
++								rtt_target->num_retries_per_ftmr));
++							err = -EINVAL;
++							goto exit;
++						}
++						break;
++					case RTT_ATTRIBUTE_TARGET_LCI:
++						rtt_target->LCI_request = nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_LCR:
++						rtt_target->LCI_request = nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_BURST_DURATION:
++						if ((nla_get_u32(iter2) > 1 &&
++							nla_get_u32(iter2) < 12)) {
++							rtt_target->burst_duration =
++							dhd_rtt_idx_to_burst_duration(
++								nla_get_u32(iter2));
++						} else if (nla_get_u32(iter2) == 15) {
++							/* use default value */
++							rtt_target->burst_duration = 0;
++						} else {
++							WL_ERR(("%d value must in (2-11) or 15\n",
++								nla_get_u32(iter2)));
++							err = -EINVAL;
++							goto exit;
++						}
++						break;
++					case RTT_ATTRIBUTE_TARGET_BW:
++						rtt_target->bw = nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_PREAMBLE:
++						rtt_target->preamble = nla_get_u8(iter2);
++						break;
++					}
++				}
++				/* convert to chanspec value */
++				rtt_target->chanspec =
++					dhd_rtt_convert_to_chspec(rtt_target->channel);
++				if (rtt_target->chanspec == 0) {
++					WL_ERR(("Channel is not valid \n"));
++					err = -EINVAL;
++					goto exit;
++				}
++				WL_INFORM(("Target addr %s, Channel : %s for RTT \n",
++					bcm_ether_ntoa((const struct ether_addr *)&rtt_target->addr,
++					eabuf),
++					wf_chspec_ntoa(rtt_target->chanspec, chanbuf)));
++				rtt_target++;
++		}
++			break;
++		}
++	}
++	WL_DBG(("leave :target_cnt : %d\n", rtt_param.rtt_target_cnt));
++	if (dhd_dev_rtt_set_cfg(bcmcfg_to_prmry_ndev(cfg), &rtt_param) < 0) {
++		WL_ERR(("Could not set RTT configuration\n"));
++		err = -EINVAL;
++	}
++exit:
++	/* free the target info list */
++	kfree(rtt_param.target_info);
++	return err;
++}
++
++static int
++wl_cfgvendor_rtt_cancel_config(struct wiphy *wiphy, struct wireless_dev *wdev,
++	const void *data, int len)
++{
++	int err = 0, rem, type, target_cnt = 1;
++	int target_cnt_chk = 0;
++	const struct nlattr *iter;
++	struct ether_addr *mac_list = NULL, *mac_addr = NULL;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++
++		switch (type) {
++		case RTT_ATTRIBUTE_TARGET_CNT:
++			if (mac_list != NULL) {
++				WL_ERR(("mac_list is not NULL\n"));
++				goto exit;
++			}
++			target_cnt = nla_get_u8(iter);
++			if (target_cnt > 0) {
++				mac_list = (struct ether_addr *)kzalloc(target_cnt * ETHER_ADDR_LEN,
++					GFP_KERNEL);
++				if (mac_list == NULL) {
++					WL_ERR(("failed to allocate mem for mac list\n"));
++					goto exit;
++				}
++				mac_addr = &mac_list[0];
++			} else {
++				/* cancel the current whole RTT process */
++				goto cancel;
++			}
++			break;
++		case RTT_ATTRIBUTE_TARGET_MAC:
++			if (mac_addr) {
++				memcpy(mac_addr++, nla_data(iter), ETHER_ADDR_LEN);
++				target_cnt_chk++;
++				if (target_cnt_chk > target_cnt) {
++					WL_ERR(("over target count\n"));
++					goto exit;
++				}
++				break;
++			} else {
++				WL_ERR(("mac_list is NULL\n"));
++				goto exit;
++			}
++
++		}
++	}
++cancel:
++	if (dhd_dev_rtt_cancel_cfg(bcmcfg_to_prmry_ndev(cfg), mac_list, target_cnt) < 0) {
++		WL_ERR(("Could not cancel RTT configuration\n"));
++		err = -EINVAL;
++	}
++exit:
++	if (mac_list) {
++		kfree(mac_list);
++	}
++	return err;
++}
++
++static int
++wl_cfgvendor_rtt_get_capability(struct wiphy *wiphy, struct wireless_dev *wdev,
++	const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	rtt_capabilities_t capability;
++
++	err = dhd_dev_rtt_capability(bcmcfg_to_prmry_ndev(cfg), &capability);
++	if (unlikely(err)) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++		goto exit;
++	}
++	err =  wl_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++	        &capability, sizeof(capability));
++	if (unlikely(err)) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++	}
++exit:
++	return err;
++}
++
++#endif /* RTT_SUPPORT */
++
++#ifdef GSCAN_SUPPORT
++static int wl_cfgvendor_enable_lazy_roam(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = -EINVAL;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type;
++	uint32 lazy_roam_enable_flag;
++
++	type = nla_type(data);
++
++	if (type == GSCAN_ATTRIBUTE_LAZY_ROAM_ENABLE) {
++		lazy_roam_enable_flag = nla_get_u32(data);
++
++		err = dhd_dev_lazy_roam_enable(bcmcfg_to_prmry_ndev(cfg),
++		           lazy_roam_enable_flag);
++
++		if (unlikely(err))
++			WL_ERR(("Could not enable lazy roam:%d \n", err));
++
++	}
++	return err;
++}
++
++static int wl_cfgvendor_set_lazy_roam_cfg(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0, tmp, type;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	wlc_roam_exp_params_t roam_param;
++	const struct nlattr *iter;
++
++	memset(&roam_param, 0, sizeof(roam_param));
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++
++		switch (type) {
++			case GSCAN_ATTRIBUTE_A_BAND_BOOST_THRESHOLD:
++				roam_param.a_band_boost_threshold = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_A_BAND_PENALTY_THRESHOLD:
++				roam_param.a_band_penalty_threshold = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_A_BAND_BOOST_FACTOR:
++				roam_param.a_band_boost_factor = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_A_BAND_PENALTY_FACTOR:
++				roam_param.a_band_penalty_factor = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_A_BAND_MAX_BOOST:
++				roam_param.a_band_max_boost = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_LAZY_ROAM_HYSTERESIS:
++				roam_param.cur_bssid_boost = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_ALERT_ROAM_RSSI_TRIGGER:
++				roam_param.alert_roam_trigger_threshold = nla_get_u32(iter);
++				break;
++		}
++	}
++
++	if (dhd_dev_set_lazy_roam_cfg(bcmcfg_to_prmry_ndev(cfg), &roam_param) < 0) {
++		WL_ERR(("Could not set batch cfg\n"));
++		err = -EINVAL;
++	}
++	return err;
++}
++
++/* small helper function */
++static wl_bssid_pref_cfg_t *
++create_bssid_pref_cfg(uint32 num)
++{
++	uint32 mem_needed;
++	wl_bssid_pref_cfg_t *bssid_pref;
++
++	mem_needed = sizeof(wl_bssid_pref_cfg_t);
++	if (num)
++		mem_needed += (num - 1) * sizeof(wl_bssid_pref_list_t);
++	bssid_pref = (wl_bssid_pref_cfg_t *) kmalloc(mem_needed, GFP_KERNEL);
++	return bssid_pref;
++}
++
++static int
++wl_cfgvendor_set_bssid_pref(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	wl_bssid_pref_cfg_t *bssid_pref = NULL;
++	wl_bssid_pref_list_t *bssids;
++	int tmp, tmp1, tmp2, type;
++	const struct nlattr *outer, *inner, *iter;
++	uint32 flush = 0, i = 0, num = 0;
++
++	/* Assumption: NUM attribute must come first */
++	nla_for_each_attr(iter, data, len, tmp2) {
++		type = nla_type(iter);
++		switch (type) {
++			case GSCAN_ATTRIBUTE_NUM_BSSID:
++				num = nla_get_u32(iter);
++				if (num > MAX_BSSID_PREF_LIST_NUM) {
++					WL_ERR(("Too many Preferred BSSIDs!\n"));
++					err = -EINVAL;
++					goto exit;
++				}
++				break;
++			case GSCAN_ATTRIBUTE_BSSID_PREF_FLUSH:
++				flush = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_BSSID_PREF_LIST:
++				if (!num)
++					return -EINVAL;
++				if ((bssid_pref = create_bssid_pref_cfg(num)) == NULL) {
++					WL_ERR(("%s: Can't malloc memory\n", __FUNCTION__));
++					err = -ENOMEM;
++					goto exit;
++				}
++				bssid_pref->count = num;
++				bssids = bssid_pref->bssids;
++				nla_for_each_nested(outer, iter, tmp) {
++					if (i >= num) {
++						WL_ERR(("CFGs don't seem right!\n"));
++						err = -EINVAL;
++						goto exit;
++					}
++					nla_for_each_nested(inner, outer, tmp1) {
++						type = nla_type(inner);
++						switch (type) {
++							case GSCAN_ATTRIBUTE_BSSID_PREF:
++								memcpy(&(bssids[i].bssid),
++								  nla_data(inner), ETHER_ADDR_LEN);
++								/* not used for now */
++								bssids[i].flags = 0;
++								break;
++							case GSCAN_ATTRIBUTE_RSSI_MODIFIER:
++								bssids[i].rssi_factor =
++								       (int8) nla_get_u32(inner);
++								break;
++						}
++					}
++					i++;
++				}
++				break;
++			default:
++				WL_ERR(("%s: No such attribute %d\n", __FUNCTION__, type));
++				break;
++			}
++	}
++
++	if (!bssid_pref) {
++		/* What if only flush is desired? */
++		if (flush) {
++			if ((bssid_pref = create_bssid_pref_cfg(0)) == NULL) {
++				WL_ERR(("%s: Can't malloc memory\n", __FUNCTION__));
++				err = -ENOMEM;
++				goto exit;
++			}
++			bssid_pref->count = 0;
++		} else {
++			err = -EINVAL;
++			goto exit;
++		}
++	}
++	err = dhd_dev_set_lazy_roam_bssid_pref(bcmcfg_to_prmry_ndev(cfg),
++	          bssid_pref, flush);
++exit:
++	kfree(bssid_pref);
++	return err;
++}
++
++
++static int
++wl_cfgvendor_set_bssid_blacklist(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	maclist_t *blacklist = NULL;
++	int err = 0;
++	int type, tmp;
++	const struct nlattr *iter;
++	uint32 mem_needed = 0, flush = 0, i = 0, num = 0;
++
++	/* Assumption: NUM attribute must come first */
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++		switch (type) {
++			case GSCAN_ATTRIBUTE_NUM_BSSID:
++				num = nla_get_u32(iter);
++				if (num > MAX_BSSID_BLACKLIST_NUM) {
++					WL_ERR(("Too many Blacklist BSSIDs!\n"));
++					err = -EINVAL;
++					goto exit;
++				}
++				break;
++			case GSCAN_ATTRIBUTE_BSSID_BLACKLIST_FLUSH:
++				flush = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_BLACKLIST_BSSID:
++				if (num) {
++					if (!blacklist) {
++						mem_needed = sizeof(maclist_t) +
++						     sizeof(struct ether_addr) * (num - 1);
++						blacklist = (maclist_t *)
++						      kmalloc(mem_needed, GFP_KERNEL);
++						if (!blacklist) {
++							WL_ERR(("%s: Can't malloc %d bytes\n",
++							     __FUNCTION__, mem_needed));
++							err = -ENOMEM;
++							goto exit;
++						}
++						blacklist->count = num;
++					}
++					if (i >= num) {
++						WL_ERR(("CFGs don't seem right!\n"));
++						err = -EINVAL;
++						goto exit;
++					}
++					memcpy(&(blacklist->ea[i]),
++					  nla_data(iter), ETHER_ADDR_LEN);
++					i++;
++				}
++				break;
++			default:
++				WL_ERR(("%s: No such attribute %d\n", __FUNCTION__, type));
++				break;
++			}
++	}
++	err = dhd_dev_set_blacklist_bssid(bcmcfg_to_prmry_ndev(cfg),
++	          blacklist, mem_needed, flush);
++exit:
++	kfree(blacklist);
++	return err;
++}
++
++static int
++wl_cfgvendor_set_ssid_whitelist(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	wl_ssid_whitelist_t *ssid_whitelist = NULL;
++	wlc_ssid_t *ssid_elem;
++	int tmp, tmp2, mem_needed = 0, type;
++	const struct nlattr *inner, *iter;
++	uint32 flush = 0, i = 0, num = 0;
++
++	/* Assumption: NUM attribute must come first */
++	nla_for_each_attr(iter, data, len, tmp2) {
++		type = nla_type(iter);
++		switch (type) {
++			case GSCAN_ATTRIBUTE_NUM_WL_SSID:
++				num = nla_get_u32(iter);
++				if (num > MAX_SSID_WHITELIST_NUM) {
++					WL_ERR(("Too many WL SSIDs!\n"));
++					err = -EINVAL;
++					goto exit;
++				}
++				mem_needed = sizeof(wl_ssid_whitelist_t);
++				if (num)
++					mem_needed += (num - 1) * sizeof(ssid_info_t);
++				ssid_whitelist = (wl_ssid_whitelist_t *)
++				        kzalloc(mem_needed, GFP_KERNEL);
++				if (ssid_whitelist == NULL) {
++					WL_ERR(("%s: Can't malloc %d bytes\n",
++					      __FUNCTION__, mem_needed));
++					err = -ENOMEM;
++					goto exit;
++				}
++				ssid_whitelist->ssid_count = num;
++				break;
++			case GSCAN_ATTRIBUTE_WL_SSID_FLUSH:
++				flush = nla_get_u32(iter);
++				break;
++			case GSCAN_ATTRIBUTE_WHITELIST_SSID_ELEM:
++				if (!num || !ssid_whitelist) {
++					WL_ERR(("num ssid is not set!\n"));
++					return -EINVAL;
++				}
++				if (i >= num) {
++					WL_ERR(("CFGs don't seem right!\n"));
++					err = -EINVAL;
++					goto exit;
++				}
++				ssid_elem = &ssid_whitelist->ssids[i];
++				nla_for_each_nested(inner, iter, tmp) {
++					type = nla_type(inner);
++					switch (type) {
++						case GSCAN_ATTRIBUTE_WHITELIST_SSID:
++							memcpy(ssid_elem->SSID,
++							  nla_data(inner),
++							  DOT11_MAX_SSID_LEN);
++							break;
++						case GSCAN_ATTRIBUTE_WL_SSID_LEN:
++							ssid_elem->SSID_len = (uint8)
++							        nla_get_u32(inner);
++							break;
++					}
++				}
++				i++;
++				break;
++			default:
++				WL_ERR(("%s: No such attribute %d\n", __FUNCTION__, type));
++				break;
++		}
++	}
++
++	err = dhd_dev_set_whitelist_ssid(bcmcfg_to_prmry_ndev(cfg),
++	          ssid_whitelist, mem_needed, flush);
++exit:
++	kfree(ssid_whitelist);
++	return err;
++}
++#endif /* GSCAN_SUPPORT */
++
++#if defined(KEEP_ALIVE)
++static int wl_cfgvendor_start_mkeep_alive(struct wiphy *wiphy, struct wireless_dev *wdev,
++	const void *data, int len)
++{
++	/* max size of IP packet for keep alive */
++	const int MKEEP_ALIVE_IP_PKT_MAX = 256;
++
++	int ret = BCME_OK, rem, type;
++	u8 mkeep_alive_id = 0;
++	u8 *ip_pkt = NULL;
++	u16 ip_pkt_len = 0;
++	u8 src_mac[ETHER_ADDR_LEN];
++	u8 dst_mac[ETHER_ADDR_LEN];
++	u32 period_msec = 0;
++	const struct nlattr *iter;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd_pub = cfg->pub;
++	gfp_t kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case MKEEP_ALIVE_ATTRIBUTE_ID:
++				mkeep_alive_id = nla_get_u8(iter);
++				break;
++			case MKEEP_ALIVE_ATTRIBUTE_IP_PKT_LEN:
++				ip_pkt_len = nla_get_u16(iter);
++				if (ip_pkt_len > MKEEP_ALIVE_IP_PKT_MAX) {
++					ret = BCME_BADARG;
++					goto exit;
++				}
++				break;
++			case MKEEP_ALIVE_ATTRIBUTE_IP_PKT:
++				ip_pkt = (u8 *)kzalloc(ip_pkt_len, kflags);
++				if (ip_pkt == NULL) {
++					ret = BCME_NOMEM;
++					WL_ERR(("Failed to allocate mem for ip packet\n"));
++					goto exit;
++				}
++				memcpy(ip_pkt, (u8*)nla_data(iter), ip_pkt_len);
++				break;
++			case MKEEP_ALIVE_ATTRIBUTE_SRC_MAC_ADDR:
++				memcpy(src_mac, nla_data(iter), ETHER_ADDR_LEN);
++				break;
++			case MKEEP_ALIVE_ATTRIBUTE_DST_MAC_ADDR:
++				memcpy(dst_mac, nla_data(iter), ETHER_ADDR_LEN);
++				break;
++			case MKEEP_ALIVE_ATTRIBUTE_PERIOD_MSEC:
++				period_msec = nla_get_u32(iter);
++				break;
++			default:
++				WL_ERR(("Unknown type: %d\n", type));
++				ret = BCME_BADARG;
++				goto exit;
++		}
++	}
++
++	ret = dhd_dev_start_mkeep_alive(dhd_pub, mkeep_alive_id, ip_pkt, ip_pkt_len, src_mac,
++		dst_mac, period_msec);
++	if (ret < 0) {
++		WL_ERR(("start_mkeep_alive is failed ret: %d\n", ret));
++	}
++
++exit:
++	if (ip_pkt) {
++		kfree(ip_pkt);
++	}
++
++	return ret;
++}
++
++static int wl_cfgvendor_stop_mkeep_alive(struct wiphy *wiphy, struct wireless_dev *wdev,
++	const void *data, int len)
++{
++	int ret = BCME_OK, rem, type;
++	u8 mkeep_alive_id = 0;
++	const struct nlattr *iter;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd_pub = cfg->pub;
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case MKEEP_ALIVE_ATTRIBUTE_ID:
++				mkeep_alive_id = nla_get_u8(iter);
++				break;
++			default:
++				WL_ERR(("Unknown type: %d\n", type));
++				ret = BCME_BADARG;
++				break;
++		}
++	}
++
++	ret = dhd_dev_stop_mkeep_alive(dhd_pub, mkeep_alive_id);
++	if (ret < 0) {
++		WL_ERR(("stop_mkeep_alive is failed ret: %d\n", ret));
++	}
++
++	return ret;
++}
++#endif /* defined(KEEP_ALIVE) */
++
++static int wl_cfgvendor_set_rssi_monitor(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0, tmp, type, start = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int8 max_rssi = 0, min_rssi = 0;
++	const struct nlattr *iter;
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++		switch (type) {
++			case RSSI_MONITOR_ATTRIBUTE_MAX_RSSI:
++				max_rssi = (int8) nla_get_u32(iter);
++				break;
++			case RSSI_MONITOR_ATTRIBUTE_MIN_RSSI:
++				min_rssi = (int8) nla_get_u32(iter);
++				break;
++			case RSSI_MONITOR_ATTRIBUTE_START:
++				start = nla_get_u32(iter);
++		}
++	}
++
++	if (dhd_dev_set_rssi_monitor_cfg(bcmcfg_to_prmry_ndev(cfg),
++	       start, max_rssi, min_rssi) < 0) {
++		WL_ERR(("Could not set rssi monitor cfg\n"));
++		err = -EINVAL;
++	}
++	return err;
++}
++
++static int
++wl_cfgvendor_priv_string_handler(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int ret = 0;
++	int ret_len = 0, payload = 0, msglen;
++	const struct bcm_nlmsg_hdr *nlioc = data;
++	void *buf = NULL, *cur;
++	int maxmsglen = PAGE_SIZE - 0x100;
++	struct sk_buff *reply;
++
++	WL_ERR(("entry: cmd = %d\n", nlioc->cmd));
++
++	len -= sizeof(struct bcm_nlmsg_hdr);
++	ret_len = nlioc->len;
++	if (ret_len > 0 || len > 0) {
++		if (len > DHD_IOCTL_MAXLEN) {
++			WL_ERR(("oversize input buffer %d\n", len));
++			len = DHD_IOCTL_MAXLEN;
++		}
++		if (ret_len > DHD_IOCTL_MAXLEN) {
++			WL_ERR(("oversize return buffer %d\n", ret_len));
++			ret_len = DHD_IOCTL_MAXLEN;
++		}
++		payload = max(ret_len, len) + 1;
++		buf = vzalloc(payload);
++		if (!buf) {
++			return -ENOMEM;
++		}
++		memcpy(buf, (void *)nlioc + nlioc->offset, len);
++		*(char *)(buf + len) = '\0';
++	}
++
++	ret = dhd_cfgvendor_priv_string_handler(cfg, wdev, nlioc, buf);
++	if (ret) {
++		WL_ERR(("dhd_cfgvendor returned error %d", ret));
++		vfree(buf);
++		return ret;
++	}
++	cur = buf;
++	while (ret_len > 0) {
++		msglen = nlioc->len > maxmsglen ? maxmsglen : ret_len;
++		ret_len -= msglen;
++		payload = msglen + sizeof(msglen);
++		reply = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, payload);
++		if (!reply) {
++			WL_ERR(("Failed to allocate reply msg\n"));
++			ret = -ENOMEM;
++			break;
++		}
++
++		if (nla_put(reply, BCM_NLATTR_DATA, msglen, cur) ||
++			nla_put_u16(reply, BCM_NLATTR_LEN, msglen)) {
++			kfree_skb(reply);
++			ret = -ENOBUFS;
++			break;
++		}
++
++		ret = cfg80211_vendor_cmd_reply(reply);
++		if (ret) {
++			WL_ERR(("testmode reply failed:%d\n", ret));
++			break;
++		}
++		cur += msglen;
++	}
++
++	return ret;
++}
++
++struct net_device *
++wl_cfgvendor_get_ndev(struct bcm_cfg80211 *cfg, struct wireless_dev *wdev,
++	const void *data, unsigned long int *out_addr)
++{
++	char *pos, *pos1;
++	char ifname[IFNAMSIZ + 1] = {0};
++	struct net_info *iter, *next;
++	struct net_device *ndev = NULL;
++	*out_addr = (unsigned long int) data; /* point to command str by default */
++
++	/* check whether ifname=<ifname> is provided in the command */
++	pos = strstr(data, "ifname=");
++	if (pos) {
++		pos += strlen("ifname=");
++		pos1 = strstr(pos, " ");
++		if (!pos1) {
++			WL_ERR(("command format error \n"));
++			return NULL;
++		}
++		memcpy(ifname, pos, (pos1 - pos));
++		for_each_ndev(cfg, iter, next) {
++			if (iter->ndev) {
++				if (strncmp(iter->ndev->name, ifname,
++					strlen(iter->ndev->name)) == 0) {
++					/* matching ifname found */
++					WL_DBG(("matching interface (%s) found ndev:%p \n",
++						iter->ndev->name, iter->ndev));
++					*out_addr = (unsigned long int)(pos1 + 1);
++					/* Returns the command portion after ifname=<name> */
++					return iter->ndev;
++				}
++			}
++
++		}
++		WL_ERR(("Couldn't find ifname:%s in the netinfo list \n",
++			ifname));
++		return NULL;
++	}
++
++	/* If ifname=<name> arg is not provided, use default ndev */
++	ndev = wdev->netdev ? wdev->netdev : bcmcfg_to_prmry_ndev(cfg);
++	WL_DBG(("Using default ndev (%s) \n", ndev->name));
++	return ndev;
++}
++
++/* Max length for the reply buffer. For BRCM_ATTR_DRIVER_CMD, the reply
++ * would be a formatted string and reply buf would be the size of the
++ * string.
++ */
++#define WL_DRIVER_PRIV_CMD_LEN 512
++static int
++wl_cfgvendor_priv_bcm_handler(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	const struct nlattr *iter;
++	int err = 0;
++	int data_len = 0, cmd_len = 0, tmp = 0, type = 0;
++	char *cmd = NULL;
++	int bytes_written;
++	char *reply_buf = NULL;
++	struct net_device *net = NULL;
++	struct net_device *ndev = wdev->netdev;
++	unsigned long int cmd_out = 0;
++	u32 reply_len = WL_DRIVER_PRIV_CMD_LEN;
++
++
++	WL_DBG(("%s: Enter \n", __func__));
++
++	/* hold wake lock */
++	net_os_wake_lock(ndev);
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++		cmd = nla_data(iter);
++		cmd_len = nla_len(iter);
++
++		WL_DBG(("%s: type: %d len:%d\n", __func__, type, cmd_len));
++		if (type == BRCM_ATTR_DRIVER_CMD) {
++			if (cmd_len >= WL_DRIVER_PRIV_CMD_LEN) {
++				WL_ERR(("Unexpected command length. Ignore the command\n"));
++				err = -EINVAL;
++				goto exit;
++			}
++			net = wl_cfgvendor_get_ndev(cfg, wdev, cmd, &cmd_out);
++			if (!cmd_out || !net) {
++				err = -ENODEV;
++				goto exit;
++			}
++			cmd = (char *)cmd_out;
++			reply_buf = kzalloc(reply_len, GFP_KERNEL);
++			if (!reply_buf) {
++				WL_ERR(("memory alloc failed for %u \n", cmd_len));
++				err = -ENOMEM;
++				goto exit;
++			}
++			memcpy(reply_buf, cmd, cmd_len);
++			WL_DBG(("vendor_command: %s len: %u \n", cmd, cmd_len));
++			bytes_written = wl_handle_private_cmd(net, reply_buf, reply_len);
++			WL_DBG(("bytes_written: %d \n", bytes_written));
++			if (bytes_written == 0) {
++				sprintf(reply_buf, "%s", "OK");
++				data_len = strlen("OK");
++			} else if (bytes_written > 0) {
++				data_len = bytes_written > reply_len ?
++					reply_len : bytes_written;
++			} else {
++				/* -ve return value. Propagate the error back */
++				err = bytes_written;
++				goto exit;
++			}
++			break;
++		}
++	}
++
++	if ((data_len > 0) && reply_buf) {
++		err =  wl_cfgvendor_send_cmd_reply(wiphy, wdev->netdev,
++			reply_buf, data_len+1);
++		if (unlikely(err))
++			WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++		else
++			WL_DBG(("Vendor Command reply sent successfully!\n"));
++	} else {
++		/* No data to be sent back as reply */
++		WL_ERR(("Vendor_cmd: No reply expected. data_len:%u reply_buf %p \n",
++			data_len, reply_buf));
++	}
++
++exit:
++	if (reply_buf)
++		kfree(reply_buf);
++	net_os_wake_unlock(ndev);
++	return err;
++}
++
++#ifdef LINKSTAT_SUPPORT
++#define NUM_RATE 32
++#define NUM_PEER 1
++#define NUM_CHAN 11
++#define HEADER_SIZE sizeof(ver_len)
++static int wl_cfgvendor_lstats_get_info(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	static char iovar_buf[WLC_IOCTL_MAXLEN];
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int err = 0, i;
++	wifi_iface_stat *iface;
++	wifi_radio_stat *radio;
++	wl_wme_cnt_t *wl_wme_cnt;
++	wl_cnt_v_le10_mcst_t *macstat_cnt;
++	wl_cnt_wlc_t *wlc_cnt;
++	scb_val_t scbval;
++	char *output;
++
++	WL_INFORM(("%s: Enter \n", __func__));
++	RETURN_EIO_IF_NOT_UP(cfg);
++
++	bzero(cfg->ioctl_buf, WLC_IOCTL_MAXLEN);
++	bzero(iovar_buf, WLC_IOCTL_MAXLEN);
++
++	output = cfg->ioctl_buf;
++
++	err = wldev_iovar_getbuf(bcmcfg_to_prmry_ndev(cfg), "radiostat", NULL, 0,
++		iovar_buf, WLC_IOCTL_MAXLEN, NULL);
++	if (err != BCME_OK && err != BCME_UNSUPPORTED) {
++		WL_ERR(("error (%d) - size = %zu\n", err, sizeof(wifi_radio_stat)));
++		return err;
++	}
++	radio = (wifi_radio_stat *)iovar_buf;
++	radio->num_channels = NUM_CHAN;
++	memcpy(output, iovar_buf+HEADER_SIZE, sizeof(wifi_radio_stat)-HEADER_SIZE);
++
++	output += (sizeof(wifi_radio_stat) - HEADER_SIZE);
++	output += (NUM_CHAN*sizeof(wifi_channel_stat));
++
++	err = wldev_iovar_getbuf(bcmcfg_to_prmry_ndev(cfg), "wme_counters", NULL, 0,
++		iovar_buf, WLC_IOCTL_MAXLEN, NULL);
++	if (unlikely(err)) {
++		WL_ERR(("error (%d)\n", err));
++		return err;
++	}
++	wl_wme_cnt = (wl_wme_cnt_t *)iovar_buf;
++	iface = (wifi_iface_stat *)output;
++
++	iface->ac[WIFI_AC_VO].ac = WIFI_AC_VO;
++	iface->ac[WIFI_AC_VO].tx_mpdu = wl_wme_cnt->tx[AC_VO].packets;
++	iface->ac[WIFI_AC_VO].rx_mpdu = wl_wme_cnt->rx[AC_VO].packets;
++	iface->ac[WIFI_AC_VO].mpdu_lost = wl_wme_cnt->tx_failed[WIFI_AC_VO].packets;
++
++	iface->ac[WIFI_AC_VI].ac = WIFI_AC_VI;
++	iface->ac[WIFI_AC_VI].tx_mpdu = wl_wme_cnt->tx[AC_VI].packets;
++	iface->ac[WIFI_AC_VI].rx_mpdu = wl_wme_cnt->rx[AC_VI].packets;
++	iface->ac[WIFI_AC_VI].mpdu_lost = wl_wme_cnt->tx_failed[WIFI_AC_VI].packets;
++
++	iface->ac[WIFI_AC_BE].ac = WIFI_AC_BE;
++	iface->ac[WIFI_AC_BE].tx_mpdu = wl_wme_cnt->tx[AC_BE].packets;
++	iface->ac[WIFI_AC_BE].rx_mpdu = wl_wme_cnt->rx[AC_BE].packets;
++	iface->ac[WIFI_AC_BE].mpdu_lost = wl_wme_cnt->tx_failed[WIFI_AC_BE].packets;
++
++	iface->ac[WIFI_AC_BK].ac = WIFI_AC_BK;
++	iface->ac[WIFI_AC_BK].tx_mpdu = wl_wme_cnt->tx[AC_BK].packets;
++	iface->ac[WIFI_AC_BK].rx_mpdu = wl_wme_cnt->rx[AC_BK].packets;
++	iface->ac[WIFI_AC_BK].mpdu_lost = wl_wme_cnt->tx_failed[WIFI_AC_BK].packets;
++	bzero(iovar_buf, WLC_IOCTL_MAXLEN);
++
++	err = wldev_iovar_getbuf(bcmcfg_to_prmry_ndev(cfg), "counters", NULL, 0,
++		iovar_buf, WLC_IOCTL_MAXLEN, NULL);
++	if (unlikely(err)) {
++		WL_ERR(("error (%d) - size = %zu\n", err, sizeof(wl_cnt_wlc_t)));
++		return err;
++	}
++
++	/* Translate traditional (ver <= 10) counters struct to new xtlv type struct */
++	err = wl_cntbuf_to_xtlv_format(NULL, iovar_buf, WL_CNTBUF_MAX_SIZE, 0);
++	if (err != BCME_OK) {
++		WL_ERR(("%s wl_cntbuf_to_xtlv_format ERR %d\n",
++		__FUNCTION__, err));
++		return err;
++	}
++
++	if (!(wlc_cnt = GET_WLCCNT_FROM_CNTBUF(iovar_buf))) {
++		WL_ERR(("%s wlc_cnt NULL!\n", __FUNCTION__));
++		return BCME_ERROR;
++	}
++
++	iface->ac[WIFI_AC_BE].retries = wlc_cnt->txretry;
++
++	if ((macstat_cnt = bcm_get_data_from_xtlv_buf(((wl_cnt_info_t *)iovar_buf)->data,
++	((wl_cnt_info_t *)iovar_buf)->datalen, WL_CNT_XTLV_CNTV_LE10_UCODE, NULL,
++	BCM_XTLV_OPTION_ALIGN32)) == NULL) {
++		macstat_cnt = bcm_get_data_from_xtlv_buf(((wl_cnt_info_t *)iovar_buf)->data,
++			((wl_cnt_info_t *)iovar_buf)->datalen,
++			WL_CNT_XTLV_LT40_UCODE_V1, NULL,
++			BCM_XTLV_OPTION_ALIGN32);
++	}
++
++	if (macstat_cnt == NULL) {
++		printf("wlmTxGetAckedPackets: macstat_cnt NULL!\n");
++		return FALSE;
++	}
++
++	iface->beacon_rx = macstat_cnt->rxbeaconmbss;
++
++	err = wldev_get_rssi(bcmcfg_to_prmry_ndev(cfg), &scbval);
++	if (unlikely(err)) {
++		WL_ERR(("get_rssi error (%d)\n", err));
++		return err;
++	}
++	iface->rssi_mgmt = scbval.val;
++
++	iface->num_peers = NUM_PEER;
++	iface->peer_info->num_rate = NUM_RATE;
++
++	bzero(iovar_buf, WLC_IOCTL_MAXLEN);
++	output = (char *)iface + sizeof(wifi_iface_stat) + NUM_PEER*sizeof(wifi_peer_info);
++
++	err = wldev_iovar_getbuf(bcmcfg_to_prmry_ndev(cfg), "ratestat", NULL, 0,
++		iovar_buf, WLC_IOCTL_MAXLEN, NULL);
++	if (err != BCME_OK && err != BCME_UNSUPPORTED) {
++		WL_ERR(("error (%d) - size = %zu\n", err, NUM_RATE*sizeof(wifi_rate_stat)));
++		return err;
++	}
++	for (i = 0; i < NUM_RATE; i++)
++		memcpy(output, iovar_buf+HEADER_SIZE+i*sizeof(wifi_rate_stat),
++		sizeof(wifi_rate_stat)-HEADER_SIZE);
++
++	err =  wl_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++		cfg->ioctl_buf,
++		sizeof(wifi_radio_stat)-HEADER_SIZE +
++		NUM_CHAN*sizeof(wifi_channel_stat) +
++		sizeof(wifi_iface_stat)+NUM_PEER*sizeof(wifi_peer_info) +
++		NUM_RATE*(sizeof(wifi_rate_stat)-HEADER_SIZE));
++	if (unlikely(err))
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++
++	return err;
++}
++#endif /* LINKSTAT_SUPPORT */
++
++static int wl_cfgvendor_dbg_start_logging(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = BCME_OK, rem, type;
++	char ring_name[DBGRING_NAME_MAX] = {0};
++	int log_level = 0, flags = 0, time_intval = 0, threshold = 0;
++	const struct nlattr *iter;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd_pub = cfg->pub;
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case DEBUG_ATTRIBUTE_RING_NAME:
++				strncpy(ring_name, nla_data(iter),
++					MIN(sizeof(ring_name) -1, nla_len(iter)));
++				break;
++			case DEBUG_ATTRIBUTE_LOG_LEVEL:
++				log_level = nla_get_u32(iter);
++				break;
++			case DEBUG_ATTRIBUTE_RING_FLAGS:
++				flags = nla_get_u32(iter);
++				break;
++			case DEBUG_ATTRIBUTE_LOG_TIME_INTVAL:
++				time_intval = nla_get_u32(iter);
++				break;
++			case DEBUG_ATTRIBUTE_LOG_MIN_DATA_SIZE:
++				threshold = nla_get_u32(iter);
++				break;
++			default:
++				WL_ERR(("Unknown type: %d\n", type));
++				ret = BCME_BADADDR;
++				goto exit;
++		}
++	}
++
++	ret = dhd_os_start_logging(dhd_pub, ring_name, log_level, flags, time_intval, threshold);
++	if (ret < 0) {
++		WL_ERR(("start_logging is failed ret: %d\n", ret));
++	}
++exit:
++	return ret;
++}
++
++#ifdef DHD_FW_COREDUMP
++static int wl_cfgvendor_dbg_trigger_mem_dump(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = BCME_OK;
++	uint32 alloc_len;
++	struct sk_buff *skb;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	ret = dhd_os_socram_dump(bcmcfg_to_prmry_ndev(cfg), &alloc_len);
++	if (ret) {
++		WL_ERR(("failed to call dhd_os_socram_dump : %d\n", ret));
++		goto exit;
++	}
++	/* Alloc the SKB for vendor_event */
++	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, 100);
++	if (!skb) {
++		WL_ERR(("skb allocation is failed\n"));
++		ret = BCME_NOMEM;
++		goto exit;
++	}
++	nla_put_u32(skb, DEBUG_ATTRIBUTE_FW_DUMP_LEN, alloc_len);
++
++	ret = cfg80211_vendor_cmd_reply(skb);
++
++	if (ret) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", ret));
++	}
++
++exit:
++	return ret;
++}
++
++static int wl_cfgvendor_dbg_get_mem_dump(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void *data, int len)
++{
++	int ret = BCME_OK, rem, type;
++	int buf_len = 0;
++	void __user *user_buf = NULL;
++	const struct nlattr *iter;
++	char *mem_buf;
++	struct sk_buff *skb;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case DEBUG_ATTRIBUTE_FW_DUMP_LEN:
++				buf_len = nla_get_u32(iter);
++				break;
++			case DEBUG_ATTRIBUTE_FW_DUMP_DATA:
++				user_buf = (void __user *) (unsigned long) nla_get_u64(iter);
++				break;
++			default:
++				WL_ERR(("Unknown type: %d\n", type));
++				ret = BCME_ERROR;
++				goto exit;
++		}
++	}
++	if (buf_len > 0 && user_buf) {
++		mem_buf = vmalloc(buf_len);
++		if (!mem_buf) {
++			WL_ERR(("failed to allocate mem_buf with size : %d\n", buf_len));
++			ret = BCME_NOMEM;
++			goto exit;
++		}
++		ret = dhd_os_get_socram_dump(bcmcfg_to_prmry_ndev(cfg), &mem_buf, &buf_len);
++		if (ret) {
++			WL_ERR(("failed to get_socram_dump : %d\n", ret));
++			goto free_mem;
++		}
++		ret = copy_to_user(user_buf, mem_buf, buf_len);
++		if (ret) {
++			WL_ERR(("failed to copy memdump into user buffer : %d\n", ret));
++			goto free_mem;
++		}
++		/* Alloc the SKB for vendor_event */
++		skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, 100);
++		if (!skb) {
++			WL_ERR(("skb allocation is failed\n"));
++			ret = BCME_NOMEM;
++			goto free_mem;
++		}
++		/* Indicate the memdump is succesfully copied */
++		nla_put(skb, DEBUG_ATTRIBUTE_FW_DUMP_DATA, sizeof(ret), &ret);
++
++		ret = cfg80211_vendor_cmd_reply(skb);
++
++		if (ret) {
++			WL_ERR(("Vendor Command reply failed ret:%d \n", ret));
++		}
++	}
++
++free_mem:
++	vfree(mem_buf);
++exit:
++	return ret;
++}
++#endif /* DHD_FW_COREDUMP */
++
++static int wl_cfgvendor_dbg_reset_logging(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = BCME_OK;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd_pub = cfg->pub;
++
++	ret = dhd_os_reset_logging(dhd_pub);
++	if (ret < 0) {
++		WL_ERR(("reset logging is failed ret: %d\n", ret));
++	}
++
++	return ret;
++}
++
++#ifdef DHD_FW_COREDUMP
++static int wl_cfgvendor_dbg_get_version(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void *data, int len)
++{
++	int ret = BCME_OK, rem, type;
++	int buf_len = 1024;
++	bool dhd_ver = FALSE;
++	char *buf_ptr;
++	const struct nlattr *iter;
++	gfp_t kflags;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	buf_ptr = kzalloc(buf_len, kflags);
++	if (!buf_ptr) {
++		WL_ERR(("failed to allocate the buffer for version n"));
++		ret = BCME_NOMEM;
++		goto exit;
++	}
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case DEBUG_ATTRIBUTE_GET_DRIVER:
++				dhd_ver = TRUE;
++				break;
++			case DEBUG_ATTRIBUTE_GET_FW:
++				dhd_ver = FALSE;
++				break;
++			default:
++				WL_ERR(("Unknown type: %d\n", type));
++				ret = BCME_ERROR;
++				goto exit;
++		}
++	}
++	ret = dhd_os_get_version(bcmcfg_to_prmry_ndev(cfg), dhd_ver, &buf_ptr, buf_len);
++	if (ret < 0) {
++		WL_ERR(("failed to get the version %d\n", ret));
++		goto exit;
++	}
++	ret = wl_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++	        buf_ptr, strlen(buf_ptr));
++exit:
++	kfree(buf_ptr);
++	return ret;
++}
++#endif /* DHD_FW_COREDUMP */
++
++static int wl_cfgvendor_dbg_get_ring_status(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = BCME_OK;
++	int ring_id, i;
++	int ring_cnt;
++	struct sk_buff *skb;
++	dhd_dbg_ring_status_t dbg_ring_status[DEBUG_RING_ID_MAX];
++	dhd_dbg_ring_status_t ring_status;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd_pub = cfg->pub;
++	memset(dbg_ring_status, 0, DBG_RING_STATUS_SIZE * DEBUG_RING_ID_MAX);
++	ring_cnt = 0;
++	for (ring_id = DEBUG_RING_ID_INVALID + 1; ring_id < DEBUG_RING_ID_MAX; ring_id++) {
++		ret = dhd_os_get_ring_status(dhd_pub, ring_id, &ring_status);
++		if (ret == BCME_NOTFOUND) {
++			WL_DBG(("The ring (%d) is not found \n", ring_id));
++		} else if (ret == BCME_OK) {
++			dbg_ring_status[ring_cnt++] = ring_status;
++		}
++	}
++	/* Alloc the SKB for vendor_event */
++	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy,
++		(DBG_RING_STATUS_SIZE * ring_cnt) + 100);
++	if (!skb) {
++		WL_ERR(("skb allocation is failed\n"));
++		ret = BCME_NOMEM;
++		goto exit;
++	}
++
++	nla_put_u32(skb, DEBUG_ATTRIBUTE_RING_NUM, ring_cnt);
++	for (i = 0; i < ring_cnt; i++) {
++		nla_put(skb, DEBUG_ATTRIBUTE_RING_STATUS, DBG_RING_STATUS_SIZE,
++				&dbg_ring_status[i]);
++	}
++	ret = cfg80211_vendor_cmd_reply(skb);
++
++	if (ret) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", ret));
++	}
++exit:
++	return ret;
++}
++
++static int wl_cfgvendor_dbg_get_ring_data(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = BCME_OK, rem, type;
++	char ring_name[DBGRING_NAME_MAX] = {0};
++	const struct nlattr *iter;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd_pub = cfg->pub;
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case DEBUG_ATTRIBUTE_RING_NAME:
++				strncpy(ring_name, nla_data(iter),
++					MIN(sizeof(ring_name) -1, nla_len(iter)));
++				break;
++			default:
++				WL_ERR(("Unknown type: %d\n", type));
++				return ret;
++		}
++	}
++
++	ret = dhd_os_trigger_get_ring_data(dhd_pub, ring_name);
++	if (ret < 0) {
++		WL_ERR(("trigger_get_data failed ret:%d\n", ret));
++	}
++
++	return ret;
++}
++
++static int wl_cfgvendor_dbg_get_feature(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = BCME_OK;
++	u32 supported_features;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pub_t *dhd_pub = cfg->pub;
++
++	ret = dhd_os_dbg_get_feature(dhd_pub, &supported_features);
++	if (ret < 0) {
++		WL_ERR(("dbg_get_feature failed ret:%d\n", ret));
++		goto exit;
++	}
++	ret = wl_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++	        &supported_features, sizeof(supported_features));
++exit:
++	return ret;
++}
++
++static void wl_cfgvendor_dbg_ring_send_evt(void *ctx,
++	const int ring_id, const void *data, const uint32 len,
++	const dhd_dbg_ring_status_t ring_status)
++{
++	struct net_device *ndev = ctx;
++	struct wiphy *wiphy;
++	gfp_t kflags;
++	struct sk_buff *skb;
++	if (!ndev) {
++		WL_ERR(("ndev is NULL\n"));
++		return;
++	}
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	wiphy = ndev->ieee80211_ptr->wiphy;
++	/* Alloc the SKB for vendor_event */
++#if (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || \
++	LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
++	skb = cfg80211_vendor_event_alloc(wiphy, NULL, len + 100,
++			GOOGLE_DEBUG_RING_EVENT, kflags);
++#else
++	skb = cfg80211_vendor_event_alloc(wiphy, len + 100,
++			GOOGLE_DEBUG_RING_EVENT, kflags);
++#endif /* (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || */
++		/* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) */
++	if (!skb) {
++		WL_ERR(("skb alloc failed"));
++		return;
++	}
++	nla_put(skb, DEBUG_ATTRIBUTE_RING_STATUS, sizeof(ring_status), &ring_status);
++	nla_put(skb, DEBUG_ATTRIBUTE_RING_DATA, len, data);
++	cfg80211_vendor_event(skb, kflags);
++}
++
++static void wl_cfgvendor_dbg_send_urgent_evt(void *ctx, const void *data,
++	const uint32 len, const uint32 fw_len)
++{
++	struct net_device *ndev = ctx;
++	struct wiphy *wiphy;
++	gfp_t kflags;
++	struct sk_buff *skb;
++	if (!ndev) {
++		WL_ERR(("ndev is NULL\n"));
++		return;
++	}
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	wiphy = ndev->ieee80211_ptr->wiphy;
++	/* Alloc the SKB for vendor_event */
++#if (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || \
++	LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
++	skb = cfg80211_vendor_event_alloc(wiphy, NULL, len + 100,
++			GOOGLE_FW_DUMP_EVENT, kflags);
++#else
++	skb = cfg80211_vendor_event_alloc(wiphy, len + 100,
++			GOOGLE_FW_DUMP_EVENT, kflags);
++#endif /* (defined(CONFIG_ARCH_MSM) && defined(SUPPORT_WDEV_CFG80211_VENDOR_EVENT_ALLOC)) || */
++		/* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) */
++	if (!skb) {
++		WL_ERR(("skb alloc failed"));
++		return;
++	}
++	nla_put_u32(skb, DEBUG_ATTRIBUTE_FW_DUMP_LEN, fw_len);
++	nla_put(skb, DEBUG_ATTRIBUTE_RING_DATA, len, data);
++	cfg80211_vendor_event(skb, kflags);
++}
++
++
++static const struct wiphy_vendor_command wl_vendor_cmds [] = {
++	{
++		{
++			.vendor_id = OUI_BRCM,
++			.subcmd = BRCM_VENDOR_SCMD_PRIV_STR
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_priv_string_handler
++	},
++	{
++		{
++			.vendor_id = OUI_BRCM,
++			.subcmd = BRCM_VENDOR_SCMD_BCM_STR
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_priv_bcm_handler
++	},
++#ifdef GSCAN_SUPPORT
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_GET_CAPABILITIES
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_gscan_get_capabilities
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_SET_CONFIG
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_scan_cfg
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_batch_scan_cfg
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_ENABLE_GSCAN
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_initiate_gscan
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_enable_full_scan_result
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_SET_HOTLIST
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_hotlist_cfg
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_significant_change_cfg
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_gscan_get_batch_results
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_gscan_get_channel_list
++	},
++#endif /* GSCAN_SUPPORT */
++#ifdef RTT_SUPPORT
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = RTT_SUBCMD_SET_CONFIG
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_rtt_set_config
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = RTT_SUBCMD_CANCEL_CONFIG
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_rtt_cancel_config
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = RTT_SUBCMD_GETCAPABILITY
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_rtt_get_capability
++	},
++#endif /* RTT_SUPPORT */
++#ifdef KEEP_ALIVE
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_OFFLOAD_SUBCMD_START_MKEEP_ALIVE
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_start_mkeep_alive
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_OFFLOAD_SUBCMD_STOP_MKEEP_ALIVE
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_stop_mkeep_alive
++	},
++#endif /* KEEP_ALIVE */
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_get_feature_set
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_get_feature_set_matrix
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = ANDR_WIFI_RANDOM_MAC_OUI
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_rand_mac_oui
++	},
++#ifdef CUSTOM_FORCE_NODFS_FLAG
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = ANDR_WIFI_NODFS_CHANNELS
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_nodfs_flag
++
++	},
++#endif /* CUSTOM_FORCE_NODFS_FLAG */
++#ifdef LINKSTAT_SUPPORT
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = LSTATS_SUBCMD_GET_INFO
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_lstats_get_info
++	},
++#endif /* LINKSTAT_SUPPORT */
++#ifdef GSCAN_SUPPORT
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_SET_EPNO_SSID
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_epno_cfg
++
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_SET_SSID_WHITELIST
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_ssid_whitelist
++
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_SET_LAZY_ROAM_PARAMS
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_lazy_roam_cfg
++
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_ENABLE_LAZY_ROAM
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_enable_lazy_roam
++
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_SET_BSSID_PREF
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_bssid_pref
++
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_SET_BSSID_BLACKLIST
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_bssid_blacklist
++	},
++#endif /* GSCAN_SUPPORT */
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_SET_RSSI_MONITOR
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_set_rssi_monitor
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_START_LOGGING
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_start_logging
++	},
++#ifdef DHD_FW_COREDUMP
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_TRIGGER_MEM_DUMP
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_trigger_mem_dump
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_GET_MEM_DUMP
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_get_mem_dump
++	},
++#endif /* DHD_FW_COREDUMP */
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_RESET_LOGGING
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_reset_logging
++	},
++#ifdef DHD_FW_COREDUMP
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_GET_VER
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_get_version
++	},
++#endif /* DHD_FW_COREDUMP */
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_GET_RING_STATUS
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_get_ring_status
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_GET_RING_DATA
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_get_ring_data
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = DEBUG_GET_FEATURE
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = wl_cfgvendor_dbg_get_feature
++	},
++};
++
++static const struct  nl80211_vendor_cmd_info wl_vendor_events [] = {
++		{ OUI_BRCM, BRCM_VENDOR_EVENT_UNSPEC },
++		{ OUI_BRCM, BRCM_VENDOR_EVENT_PRIV_STR },
++#ifdef GSCAN_SUPPORT
++		{ OUI_GOOGLE, GOOGLE_GSCAN_SIGNIFICANT_EVENT },
++		{ OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT },
++		{ OUI_GOOGLE, GOOGLE_GSCAN_BATCH_SCAN_EVENT },
++		{ OUI_GOOGLE, GOOGLE_SCAN_FULL_RESULTS_EVENT },
++#endif /* GSCAN_SUPPORT */
++#ifdef RTT_SUPPORT
++		{ OUI_GOOGLE, GOOGLE_RTT_COMPLETE_EVENT },
++#endif /* RTT_SUPPORT */
++#ifdef GSCAN_SUPPORT
++		{ OUI_GOOGLE, GOOGLE_SCAN_COMPLETE_EVENT },
++		{ OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_LOST_EVENT },
++		{ OUI_GOOGLE, GOOGLE_SCAN_EPNO_EVENT },
++#endif /* GSCAN_SUPPORT */
++		{ OUI_GOOGLE, GOOGLE_DEBUG_RING_EVENT },
++		{ OUI_GOOGLE, GOOGLE_FW_DUMP_EVENT },
++#ifdef GSCAN_SUPPORT
++		{ OUI_GOOGLE, GOOGLE_PNO_HOTSPOT_FOUND_EVENT },
++#endif /* GSCAN_SUPPORT */
++		{ OUI_GOOGLE, GOOGLE_RSSI_MONITOR_EVENT },
++#ifdef KEEP_ALIVE
++		{ OUI_GOOGLE, GOOGLE_MKEEP_ALIVE_EVENT },
++#endif
++		{ OUI_GOOGLE, NAN_EVENT_ENABLED },
++		{ OUI_GOOGLE, NAN_EVENT_DISABLED },
++		{ OUI_GOOGLE, NAN_EVENT_PUBLISH_REPLIED },
++		{ OUI_GOOGLE, NAN_EVENT_PUBLISH_TERMINATED },
++		{ OUI_GOOGLE, NAN_EVENT_SUBSCRIBE_MATCH },
++		{ OUI_GOOGLE, NAN_EVENT_SUBSCRIBE_UNMATCH },
++		{ OUI_GOOGLE, NAN_EVENT_SUBSCRIBE_TERMINATED },
++		{ OUI_GOOGLE, NAN_EVENT_DE_EVENT },
++		{ OUI_GOOGLE, NAN_EVENT_FOLLOWUP },
++		{ OUI_GOOGLE, NAN_EVENT_TCA },
++		{ OUI_GOOGLE, NAN_EVENT_UNKNOWN }
++};
++
++int wl_cfgvendor_attach(struct wiphy *wiphy, dhd_pub_t *dhd)
++{
++
++	WL_INFORM(("Vendor: Register BRCM cfg80211 vendor cmd(0x%x) interface \n",
++		NL80211_CMD_VENDOR));
++
++	wiphy->vendor_commands	= wl_vendor_cmds;
++	wiphy->n_vendor_commands = ARRAY_SIZE(wl_vendor_cmds);
++	wiphy->vendor_events	= wl_vendor_events;
++	wiphy->n_vendor_events	= ARRAY_SIZE(wl_vendor_events);
++
++	dhd_os_dbg_register_callback(FW_VERBOSE_RING_ID, wl_cfgvendor_dbg_ring_send_evt);
++	dhd_os_dbg_register_callback(FW_EVENT_RING_ID, wl_cfgvendor_dbg_ring_send_evt);
++	dhd_os_dbg_register_callback(DHD_EVENT_RING_ID, wl_cfgvendor_dbg_ring_send_evt);
++	dhd_os_dbg_register_callback(NAN_EVENT_RING_ID, wl_cfgvendor_dbg_ring_send_evt);
++	dhd_os_dbg_register_urgent_notifier(dhd, wl_cfgvendor_dbg_send_urgent_evt);
++
++	return 0;
++}
++
++int wl_cfgvendor_detach(struct wiphy *wiphy)
++{
++	WL_INFORM(("Vendor: Unregister BRCM cfg80211 vendor interface \n"));
++
++	wiphy->vendor_commands  = NULL;
++	wiphy->vendor_events    = NULL;
++	wiphy->n_vendor_commands = 0;
++	wiphy->n_vendor_events  = 0;
++
++	return 0;
++}
++#endif /* defined(WL_VENDOR_EXT_SUPPORT) */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgvendor.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgvendor.h
+new file mode 100644
+index 000000000..92bb88565
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_cfgvendor.h
+@@ -0,0 +1,418 @@
++/*
++ * Linux cfg80211 Vendor Extension Code
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_cfgvendor.h 455257 2014-02-20 08:10:24Z $
++ */
++
++
++#ifndef _wl_cfgvendor_h_
++#define _wl_cfgvendor_h_
++
++#define OUI_BRCM    0x001018
++#define OUI_GOOGLE  0x001A11
++#define BRCM_VENDOR_SUBCMD_PRIV_STR	1
++#define ATTRIBUTE_U32_LEN                  (NLA_HDRLEN  + 4)
++#define VENDOR_ID_OVERHEAD                 ATTRIBUTE_U32_LEN
++#define VENDOR_SUBCMD_OVERHEAD             ATTRIBUTE_U32_LEN
++#define VENDOR_DATA_OVERHEAD               (NLA_HDRLEN)
++
++enum brcm_vendor_attr {
++	BRCM_ATTR_DRIVER_CMD,
++	BRCM_ATTR_DRIVER_MAX
++};
++
++#define SCAN_RESULTS_COMPLETE_FLAG_LEN       ATTRIBUTE_U32_LEN
++#define SCAN_INDEX_HDR_LEN                   (NLA_HDRLEN)
++#define SCAN_ID_HDR_LEN                      ATTRIBUTE_U32_LEN
++#define SCAN_FLAGS_HDR_LEN                   ATTRIBUTE_U32_LEN
++#define GSCAN_NUM_RESULTS_HDR_LEN            ATTRIBUTE_U32_LEN
++#define GSCAN_RESULTS_HDR_LEN                (NLA_HDRLEN)
++#define GSCAN_BATCH_RESULT_HDR_LEN  (SCAN_INDEX_HDR_LEN + SCAN_ID_HDR_LEN + \
++									SCAN_FLAGS_HDR_LEN + \
++							        GSCAN_NUM_RESULTS_HDR_LEN + \
++									GSCAN_RESULTS_HDR_LEN)
++
++#define VENDOR_REPLY_OVERHEAD       (VENDOR_ID_OVERHEAD + \
++									VENDOR_SUBCMD_OVERHEAD + \
++									VENDOR_DATA_OVERHEAD)
++
++#define GSCAN_ATTR_SET1				10
++#define GSCAN_ATTR_SET2				20
++#define GSCAN_ATTR_SET3				30
++#define GSCAN_ATTR_SET4				40
++#define GSCAN_ATTR_SET5				50
++#define GSCAN_ATTR_SET6				60
++#define GSCAN_ATTR_SET7				70
++#define GSCAN_ATTR_SET8				80
++#define GSCAN_ATTR_SET9				90
++#define GSCAN_ATTR_SET10			100
++#define GSCAN_ATTR_SET11			110
++#define GSCAN_ATTR_SET12			120
++
++typedef enum {
++	/* don't use 0 as a valid subcommand */
++	VENDOR_NL80211_SUBCMD_UNSPECIFIED,
++
++	/* define all vendor startup commands between 0x0 and 0x0FFF */
++	VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001,
++	VENDOR_NL80211_SUBCMD_RANGE_END   = 0x0FFF,
++
++	/* define all GScan related commands between 0x1000 and 0x10FF */
++	ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000,
++	ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END   = 0x10FF,
++
++
++	/* define all RTT related commands between 0x1100 and 0x11FF */
++	ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100,
++	ANDROID_NL80211_SUBCMD_RTT_RANGE_END   = 0x11FF,
++
++	ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200,
++	ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END   = 0x12FF,
++
++	ANDROID_NL80211_SUBCMD_TDLS_RANGE_START = 0x1300,
++	ANDROID_NL80211_SUBCMD_TDLS_RANGE_END	= 0x13FF,
++
++	ANDROID_NL80211_SUBCMD_DEBUG_RANGE_START = 0x1400,
++	ANDROID_NL80211_SUBCMD_DEBUG_RANGE_END	= 0x14FF,
++
++	/* define all NearbyDiscovery related commands between 0x1500 and 0x15FF */
++	ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1500,
++	ANDROID_NL80211_SUBCMD_NBD_RANGE_END   = 0x15FF,
++
++	/* define all wifi calling related commands between 0x1600 and 0x16FF */
++	ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_START = 0x1600,
++	ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_END   = 0x16FF,
++
++	/* This is reserved for future usage */
++
++} ANDROID_VENDOR_SUB_COMMAND;
++
++enum andr_vendor_subcmd {
++	GSCAN_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START,
++	GSCAN_SUBCMD_SET_CONFIG,
++	GSCAN_SUBCMD_SET_SCAN_CONFIG,
++	GSCAN_SUBCMD_ENABLE_GSCAN,
++	GSCAN_SUBCMD_GET_SCAN_RESULTS,
++	GSCAN_SUBCMD_SCAN_RESULTS,
++	GSCAN_SUBCMD_SET_HOTLIST,
++	GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG,
++	GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS,
++	GSCAN_SUBCMD_GET_CHANNEL_LIST,
++	/* ANDR_WIFI_XXX although not related to gscan are defined here */
++	ANDR_WIFI_SUBCMD_GET_FEATURE_SET,
++	ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX,
++	ANDR_WIFI_RANDOM_MAC_OUI,
++	ANDR_WIFI_NODFS_CHANNELS,
++	ANDR_WIFI_SET_COUNTRY,
++	GSCAN_SUBCMD_SET_EPNO_SSID,
++	WIFI_SUBCMD_SET_SSID_WHITELIST,
++	WIFI_SUBCMD_SET_LAZY_ROAM_PARAMS,
++	WIFI_SUBCMD_ENABLE_LAZY_ROAM,
++	WIFI_SUBCMD_SET_BSSID_PREF,
++	WIFI_SUBCMD_SET_BSSID_BLACKLIST,
++	GSCAN_SUBCMD_ANQPO_CONFIG,
++	WIFI_SUBCMD_SET_RSSI_MONITOR,
++	RTT_SUBCMD_SET_CONFIG = ANDROID_NL80211_SUBCMD_RTT_RANGE_START,
++	RTT_SUBCMD_CANCEL_CONFIG,
++	RTT_SUBCMD_GETCAPABILITY,
++
++	LSTATS_SUBCMD_GET_INFO = ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START,
++
++	DEBUG_START_LOGGING = ANDROID_NL80211_SUBCMD_DEBUG_RANGE_START,
++	DEBUG_TRIGGER_MEM_DUMP,
++	DEBUG_GET_MEM_DUMP,
++	DEBUG_GET_VER,
++	DEBUG_GET_RING_STATUS,
++	DEBUG_GET_RING_DATA,
++	DEBUG_GET_FEATURE,
++	DEBUG_RESET_LOGGING,
++
++	WIFI_OFFLOAD_SUBCMD_START_MKEEP_ALIVE = ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_START,
++	WIFI_OFFLOAD_SUBCMD_STOP_MKEEP_ALIVE,
++    /* Add more sub commands here */
++	VENDOR_SUBCMD_MAX
++};
++
++enum gscan_attributes {
++    GSCAN_ATTRIBUTE_NUM_BUCKETS = GSCAN_ATTR_SET1,
++    GSCAN_ATTRIBUTE_BASE_PERIOD,
++    GSCAN_ATTRIBUTE_BUCKETS_BAND,
++    GSCAN_ATTRIBUTE_BUCKET_ID,
++    GSCAN_ATTRIBUTE_BUCKET_PERIOD,
++    GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS,
++    GSCAN_ATTRIBUTE_BUCKET_CHANNELS,
++    GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN,
++    GSCAN_ATTRIBUTE_REPORT_THRESHOLD,
++    GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE,
++    GSCAN_ATTRIBUTE_BAND = GSCAN_ATTRIBUTE_BUCKETS_BAND,
++
++    GSCAN_ATTRIBUTE_ENABLE_FEATURE = GSCAN_ATTR_SET2,
++    GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE,
++    GSCAN_ATTRIBUTE_FLUSH_FEATURE,
++    GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS,
++    GSCAN_ATTRIBUTE_REPORT_EVENTS,
++    /* remaining reserved for additional attributes */
++    GSCAN_ATTRIBUTE_NUM_OF_RESULTS = GSCAN_ATTR_SET3,
++    GSCAN_ATTRIBUTE_FLUSH_RESULTS,
++    GSCAN_ATTRIBUTE_SCAN_RESULTS,                       /* flat array of wifi_scan_result */
++    GSCAN_ATTRIBUTE_SCAN_ID,                            /* indicates scan number */
++    GSCAN_ATTRIBUTE_SCAN_FLAGS,                         /* indicates if scan was aborted */
++    GSCAN_ATTRIBUTE_AP_FLAGS,                           /* flags on significant change event */
++    GSCAN_ATTRIBUTE_NUM_CHANNELS,
++    GSCAN_ATTRIBUTE_CHANNEL_LIST,
++
++	/* remaining reserved for additional attributes */
++
++    GSCAN_ATTRIBUTE_SSID = GSCAN_ATTR_SET4,
++    GSCAN_ATTRIBUTE_BSSID,
++    GSCAN_ATTRIBUTE_CHANNEL,
++    GSCAN_ATTRIBUTE_RSSI,
++    GSCAN_ATTRIBUTE_TIMESTAMP,
++    GSCAN_ATTRIBUTE_RTT,
++    GSCAN_ATTRIBUTE_RTTSD,
++
++    /* remaining reserved for additional attributes */
++
++    GSCAN_ATTRIBUTE_HOTLIST_BSSIDS = GSCAN_ATTR_SET5,
++    GSCAN_ATTRIBUTE_RSSI_LOW,
++    GSCAN_ATTRIBUTE_RSSI_HIGH,
++    GSCAN_ATTRIBUTE_HOSTLIST_BSSID_ELEM,
++    GSCAN_ATTRIBUTE_HOTLIST_FLUSH,
++
++    /* remaining reserved for additional attributes */
++    GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE = GSCAN_ATTR_SET6,
++    GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE,
++    GSCAN_ATTRIBUTE_MIN_BREACHING,
++    GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS,
++    GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH,
++
++    /* EPNO */
++    GSCAN_ATTRIBUTE_EPNO_SSID_LIST = GSCAN_ATTR_SET7,
++    GSCAN_ATTRIBUTE_EPNO_SSID,
++    GSCAN_ATTRIBUTE_EPNO_SSID_LEN,
++    GSCAN_ATTRIBUTE_EPNO_RSSI,
++    GSCAN_ATTRIBUTE_EPNO_FLAGS,
++    GSCAN_ATTRIBUTE_EPNO_AUTH,
++    GSCAN_ATTRIBUTE_EPNO_SSID_NUM,
++    GSCAN_ATTRIBUTE_EPNO_FLUSH,
++
++    /* Roam SSID Whitelist and BSSID pref */
++    GSCAN_ATTRIBUTE_WHITELIST_SSID = GSCAN_ATTR_SET8,
++    GSCAN_ATTRIBUTE_NUM_WL_SSID,
++    GSCAN_ATTRIBUTE_WL_SSID_LEN,
++    GSCAN_ATTRIBUTE_WL_SSID_FLUSH,
++    GSCAN_ATTRIBUTE_WHITELIST_SSID_ELEM,
++    GSCAN_ATTRIBUTE_NUM_BSSID,
++    GSCAN_ATTRIBUTE_BSSID_PREF_LIST,
++    GSCAN_ATTRIBUTE_BSSID_PREF_FLUSH,
++    GSCAN_ATTRIBUTE_BSSID_PREF,
++    GSCAN_ATTRIBUTE_RSSI_MODIFIER,
++
++
++    /* Roam cfg */
++    GSCAN_ATTRIBUTE_A_BAND_BOOST_THRESHOLD = GSCAN_ATTR_SET9,
++    GSCAN_ATTRIBUTE_A_BAND_PENALTY_THRESHOLD,
++    GSCAN_ATTRIBUTE_A_BAND_BOOST_FACTOR,
++    GSCAN_ATTRIBUTE_A_BAND_PENALTY_FACTOR,
++    GSCAN_ATTRIBUTE_A_BAND_MAX_BOOST,
++    GSCAN_ATTRIBUTE_LAZY_ROAM_HYSTERESIS,
++    GSCAN_ATTRIBUTE_ALERT_ROAM_RSSI_TRIGGER,
++    GSCAN_ATTRIBUTE_LAZY_ROAM_ENABLE,
++
++    /* BSSID blacklist */
++    GSCAN_ATTRIBUTE_BSSID_BLACKLIST_FLUSH = GSCAN_ATTR_SET10,
++    GSCAN_ATTRIBUTE_BLACKLIST_BSSID,
++
++    GSCAN_ATTRIBUTE_ANQPO_HS_LIST = GSCAN_ATTR_SET11,
++    GSCAN_ATTRIBUTE_ANQPO_HS_LIST_SIZE,
++    GSCAN_ATTRIBUTE_ANQPO_HS_NETWORK_ID,
++    GSCAN_ATTRIBUTE_ANQPO_HS_NAI_REALM,
++    GSCAN_ATTRIBUTE_ANQPO_HS_ROAM_CONSORTIUM_ID,
++    GSCAN_ATTRIBUTE_ANQPO_HS_PLMN,
++
++    /* Adaptive scan attributes */
++    GSCAN_ATTRIBUTE_BUCKET_STEP_COUNT = GSCAN_ATTR_SET12,
++    GSCAN_ATTRIBUTE_BUCKET_MAX_PERIOD,
++
++    GSCAN_ATTRIBUTE_MAX
++};
++
++enum gscan_bucket_attributes {
++	GSCAN_ATTRIBUTE_CH_BUCKET_1,
++	GSCAN_ATTRIBUTE_CH_BUCKET_2,
++	GSCAN_ATTRIBUTE_CH_BUCKET_3,
++	GSCAN_ATTRIBUTE_CH_BUCKET_4,
++	GSCAN_ATTRIBUTE_CH_BUCKET_5,
++	GSCAN_ATTRIBUTE_CH_BUCKET_6,
++	GSCAN_ATTRIBUTE_CH_BUCKET_7
++};
++
++enum gscan_ch_attributes {
++	GSCAN_ATTRIBUTE_CH_ID_1,
++	GSCAN_ATTRIBUTE_CH_ID_2,
++	GSCAN_ATTRIBUTE_CH_ID_3,
++	GSCAN_ATTRIBUTE_CH_ID_4,
++	GSCAN_ATTRIBUTE_CH_ID_5,
++	GSCAN_ATTRIBUTE_CH_ID_6,
++	GSCAN_ATTRIBUTE_CH_ID_7
++};
++
++enum rtt_attributes {
++	RTT_ATTRIBUTE_TARGET_CNT,
++	RTT_ATTRIBUTE_TARGET_INFO,
++	RTT_ATTRIBUTE_TARGET_MAC,
++	RTT_ATTRIBUTE_TARGET_TYPE,
++	RTT_ATTRIBUTE_TARGET_PEER,
++	RTT_ATTRIBUTE_TARGET_CHAN,
++	RTT_ATTRIBUTE_TARGET_PERIOD,
++	RTT_ATTRIBUTE_TARGET_NUM_BURST,
++	RTT_ATTRIBUTE_TARGET_NUM_FTM_BURST,
++	RTT_ATTRIBUTE_TARGET_NUM_RETRY_FTM,
++	RTT_ATTRIBUTE_TARGET_NUM_RETRY_FTMR,
++	RTT_ATTRIBUTE_TARGET_LCI,
++	RTT_ATTRIBUTE_TARGET_LCR,
++	RTT_ATTRIBUTE_TARGET_BURST_DURATION,
++	RTT_ATTRIBUTE_TARGET_PREAMBLE,
++	RTT_ATTRIBUTE_TARGET_BW,
++	RTT_ATTRIBUTE_RESULTS_COMPLETE = 30,
++	RTT_ATTRIBUTE_RESULTS_PER_TARGET,
++	RTT_ATTRIBUTE_RESULT_CNT,
++	RTT_ATTRIBUTE_RESULT
++};
++
++enum wifi_rssi_monitor_attr {
++	RSSI_MONITOR_ATTRIBUTE_MAX_RSSI,
++	RSSI_MONITOR_ATTRIBUTE_MIN_RSSI,
++	RSSI_MONITOR_ATTRIBUTE_START
++};
++
++enum debug_attributes {
++	DEBUG_ATTRIBUTE_GET_DRIVER,
++	DEBUG_ATTRIBUTE_GET_FW,
++	DEBUG_ATTRIBUTE_RING_ID,
++	DEBUG_ATTRIBUTE_RING_NAME,
++	DEBUG_ATTRIBUTE_RING_FLAGS,
++	DEBUG_ATTRIBUTE_LOG_LEVEL,
++	DEBUG_ATTRIBUTE_LOG_TIME_INTVAL,
++	DEBUG_ATTRIBUTE_LOG_MIN_DATA_SIZE,
++	DEBUG_ATTRIBUTE_FW_DUMP_LEN,
++	DEBUG_ATTRIBUTE_FW_DUMP_DATA,
++	DEBUG_ATTRIBUTE_RING_DATA,
++	DEBUG_ATTRIBUTE_RING_STATUS,
++	DEBUG_ATTRIBUTE_RING_NUM
++};
++
++enum mkeep_alive_attributes {
++	MKEEP_ALIVE_ATTRIBUTE_ID,
++	MKEEP_ALIVE_ATTRIBUTE_IP_PKT,
++	MKEEP_ALIVE_ATTRIBUTE_IP_PKT_LEN,
++	MKEEP_ALIVE_ATTRIBUTE_SRC_MAC_ADDR,
++	MKEEP_ALIVE_ATTRIBUTE_DST_MAC_ADDR,
++	MKEEP_ALIVE_ATTRIBUTE_PERIOD_MSEC
++};
++
++typedef enum wl_vendor_event {
++	BRCM_VENDOR_EVENT_UNSPEC,
++	BRCM_VENDOR_EVENT_PRIV_STR,
++	GOOGLE_GSCAN_SIGNIFICANT_EVENT,
++	GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT,
++	GOOGLE_GSCAN_BATCH_SCAN_EVENT,
++	GOOGLE_SCAN_FULL_RESULTS_EVENT,
++	GOOGLE_RTT_COMPLETE_EVENT,
++	GOOGLE_SCAN_COMPLETE_EVENT,
++	GOOGLE_GSCAN_GEOFENCE_LOST_EVENT,
++	GOOGLE_SCAN_EPNO_EVENT,
++	GOOGLE_DEBUG_RING_EVENT,
++	GOOGLE_FW_DUMP_EVENT,
++	GOOGLE_PNO_HOTSPOT_FOUND_EVENT,
++	GOOGLE_RSSI_MONITOR_EVENT,
++	GOOGLE_MKEEP_ALIVE_EVENT,
++	NAN_EVENT_ENABLED,
++	NAN_EVENT_DISABLED,
++	NAN_EVENT_PUBLISH_REPLIED,
++	NAN_EVENT_PUBLISH_TERMINATED,
++	NAN_EVENT_SUBSCRIBE_MATCH,
++	NAN_EVENT_SUBSCRIBE_UNMATCH,
++	NAN_EVENT_SUBSCRIBE_TERMINATED,
++	NAN_EVENT_DE_EVENT,
++	NAN_EVENT_FOLLOWUP,
++	NAN_EVENT_TCA,
++	NAN_EVENT_UNKNOWN
++} wl_vendor_event_t;
++
++enum andr_wifi_attr {
++	ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET,
++	ANDR_WIFI_ATTRIBUTE_FEATURE_SET,
++	ANDR_WIFI_ATTRIBUTE_RANDOM_MAC_OUI,
++	ANDR_WIFI_ATTRIBUTE_NODFS_SET
++};
++
++typedef enum wl_vendor_gscan_attribute {
++	ATTR_START_GSCAN,
++	ATTR_STOP_GSCAN,
++	ATTR_SET_SCAN_BATCH_CFG_ID, /* set batch scan params */
++	ATTR_SET_SCAN_GEOFENCE_CFG_ID, /* set list of bssids to track */
++	ATTR_SET_SCAN_SIGNIFICANT_CFG_ID, /* set list of bssids, rssi threshold etc.. */
++	ATTR_SET_SCAN_CFG_ID, /* set common scan config params here */
++	ATTR_GET_GSCAN_CAPABILITIES_ID,
++    /* Add more sub commands here */
++	ATTR_GSCAN_MAX
++} wl_vendor_gscan_attribute_t;
++
++typedef enum gscan_batch_attribute {
++	ATTR_GSCAN_BATCH_BESTN,
++	ATTR_GSCAN_BATCH_MSCAN,
++	ATTR_GSCAN_BATCH_BUFFER_THRESHOLD
++} gscan_batch_attribute_t;
++
++typedef enum gscan_geofence_attribute {
++	ATTR_GSCAN_NUM_HOTLIST_BSSID,
++	ATTR_GSCAN_HOTLIST_BSSID
++} gscan_geofence_attribute_t;
++
++typedef enum gscan_complete_event {
++	WIFI_SCAN_BUFFER_FULL,
++	WIFI_SCAN_COMPLETE
++} gscan_complete_event_t;
++
++/* Capture the BRCM_VENDOR_SUBCMD_PRIV_STRINGS* here */
++#define BRCM_VENDOR_SCMD_CAPA	"cap"
++
++#if defined(WL_VENDOR_EXT_SUPPORT) || defined(CONFIG_BCMDHD_VENDOR_EXT)
++extern int wl_cfgvendor_attach(struct wiphy *wiphy, struct dhd_pub *dhd);
++extern int wl_cfgvendor_detach(struct wiphy *wiphy);
++extern int wl_cfgvendor_send_async_event(struct wiphy *wiphy,
++                  struct net_device *dev, int event_id, const void  *data, int len);
++extern int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
++                struct net_device *dev, void  *data, int len, wl_vendor_event_t event);
++#else
++static INLINE int cfgvendor_attach(struct wiphy *wiphy, dhd_pub_t *dhd) { return 0; }
++static INLINE int cfgvendor_detach(struct wiphy *wiphy) { return 0; }
++static INLINE int wl_cfgvendor_send_async_event(struct wiphy *wiphy,
++	struct net_device *dev, int event_id, const void  *data, int len) { return 0; }
++#endif /* defined(WL_VENDOR_EXT_SUPPORT) ||  defined(CONFIG_BCMDHD_VENDOR_EXT) */
++
++#endif /* _wl_cfgvendor_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_dbg.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_dbg.h
+new file mode 100644
+index 000000000..3a9e2be66
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_dbg.h
+@@ -0,0 +1,211 @@
++/*
++ * Minimal debug/trace/assert driver definitions for
++ * Broadcom 802.11 Networking Adapter.
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_dbg.h 519338 2014-12-05 21:23:30Z $
++ */
++
++
++#ifndef _wl_dbg_h_
++#define _wl_dbg_h_
++
++/* wl_msg_level is a bit vector with defs in wlioctl.h */
++extern uint32 wl_msg_level;
++extern uint32 wl_msg_level2;
++
++#define WL_TIMESTAMP()
++
++#define WL_PRINT(args)		do { WL_TIMESTAMP(); printf args; } while (0)
++
++#if defined(EVENT_LOG_COMPILE) && defined(WLMSG_SRSCAN)
++#define _WL_SRSCAN(fmt, ...)	EVENT_LOG(EVENT_LOG_TAG_SRSCAN, fmt, ##__VA_ARGS__)
++#define WL_SRSCAN(args)		_WL_SRSCAN args
++#else
++#define WL_SRSCAN(args)
++#endif
++
++#if defined(BCMCONDITIONAL_LOGGING)
++
++/* Ideally this should be some include file that vendors can include to conditionalize logging */
++
++/* DBGONLY() macro to reduce ifdefs in code for statements that are only needed when
++ * BCMDBG is defined.
++ */
++#define DBGONLY(x)
++
++/* To disable a message completely ... until you need it again */
++#define WL_NONE(args)
++#define WL_ERROR(args)		do {if (wl_msg_level & WL_ERROR_VAL) WL_PRINT(args);} while (0)
++#define WL_TRACE(args)
++#define WL_PRHDRS_MSG(args)
++#define WL_PRHDRS(i, p, f, t, r, l)
++#define WL_PRPKT(m, b, n)
++#define WL_INFORM(args)
++#define WL_TMP(args)
++#define WL_OID(args)
++#define WL_RATE(args)		do {if (wl_msg_level & WL_RATE_VAL) WL_PRINT(args);} while (0)
++#define WL_ASSOC(args)		do {if (wl_msg_level & WL_ASSOC_VAL) WL_PRINT(args);} while (0)
++#define WL_PRUSR(m, b, n)
++#define WL_PS(args)		do {if (wl_msg_level & WL_PS_VAL) WL_PRINT(args);} while (0)
++
++#define WL_PORT(args)
++#define WL_DUAL(args)
++#define WL_REGULATORY(args)	do {if (wl_msg_level & WL_REGULATORY_VAL) WL_PRINT(args);} while (0)
++
++#define WL_MPC(args)
++#define WL_APSTA(args)
++#define WL_APSTA_BCN(args)
++#define WL_APSTA_TX(args)
++#define WL_APSTA_TSF(args)
++#define WL_APSTA_BSSID(args)
++#define WL_BA(args)
++#define WL_MBSS(args)
++#define WL_PROTO(args)
++
++#define	WL_CAC(args)		do {if (wl_msg_level & WL_CAC_VAL) WL_PRINT(args);} while (0)
++#define WL_AMSDU(args)
++#define WL_AMPDU(args)
++#define WL_FFPLD(args)
++#define WL_MCHAN(args)
++
++#define WL_DFS(args)
++#define WL_WOWL(args)
++#define WL_DPT(args)
++#define WL_ASSOC_OR_DPT(args)
++#define WL_SCAN(args)		do {if (wl_msg_level2 & WL_SCAN_VAL) WL_PRINT(args);} while (0)
++#define WL_COEX(args)
++#define WL_RTDC(w, s, i, j)
++#define WL_RTDC2(w, s, i, j)
++#define WL_CHANINT(args)
++#define WL_BTA(args)
++#define WL_P2P(args)
++#define WL_ITFR(args)
++#define WL_TDLS(args)
++#define WL_MCNX(args)
++#define WL_PROT(args)
++#define WL_PSTA(args)
++#define WL_WFDS(m, b, n)
++#define WL_TRF_MGMT(args)
++#define WL_L2FILTER(args)
++#define WL_MQ(args)
++#define WL_TXBF(args)
++#define WL_P2PO(args)
++#define WL_ROAM(args)
++#define WL_WNM(args)
++
++
++#define WL_AMPDU_UPDN(args)
++#define WL_AMPDU_RX(args)
++#define WL_AMPDU_ERR(args)
++#define WL_AMPDU_TX(args)
++#define WL_AMPDU_CTL(args)
++#define WL_AMPDU_HW(args)
++#define WL_AMPDU_HWTXS(args)
++#define WL_AMPDU_HWDBG(args)
++#define WL_AMPDU_STAT(args)
++#define WL_AMPDU_ERR_ON()       0
++#define WL_AMPDU_HW_ON()        0
++#define WL_AMPDU_HWTXS_ON()     0
++
++#define WL_APSTA_UPDN(args)
++#define WL_APSTA_RX(args)
++#define WL_WSEC(args)
++#define WL_WSEC_DUMP(args)
++#define WL_PCIE(args)
++#define WL_TSLOG(w, s, i, j)
++#define WL_FBT(args)
++
++#define WL_ERROR_ON()		(wl_msg_level & WL_ERROR_VAL)
++#define WL_TRACE_ON()		0
++#define WL_PRHDRS_ON()		0
++#define WL_PRPKT_ON()		0
++#define WL_INFORM_ON()		0
++#define WL_TMP_ON()		0
++#define WL_OID_ON()		0
++#define WL_RATE_ON()		(wl_msg_level & WL_RATE_VAL)
++#define WL_ASSOC_ON()		(wl_msg_level & WL_ASSOC_VAL)
++#define WL_PRUSR_ON()		0
++#define WL_PS_ON()		(wl_msg_level & WL_PS_VAL)
++#define WL_PORT_ON()		0
++#define WL_WSEC_ON()		0
++#define WL_WSEC_DUMP_ON()	0
++#define WL_MPC_ON()		0
++#define WL_REGULATORY_ON()	(wl_msg_level & WL_REGULATORY_VAL)
++#define WL_APSTA_ON()		0
++#define WL_DFS_ON()		0
++#define WL_MBSS_ON()		0
++#define WL_CAC_ON()		(wl_msg_level & WL_CAC_VAL)
++#define WL_AMPDU_ON()		0
++#define WL_DPT_ON()		0
++#define WL_WOWL_ON()		0
++#define WL_SCAN_ON()		(wl_msg_level2 & WL_SCAN_VAL)
++#define WL_BTA_ON()		0
++#define WL_P2P_ON()		0
++#define WL_ITFR_ON()		0
++#define WL_MCHAN_ON()		0
++#define WL_TDLS_ON()		0
++#define WL_MCNX_ON()		0
++#define WL_PROT_ON()		0
++#define WL_PSTA_ON()		0
++#define WL_TRF_MGMT_ON()	0
++#define WL_LPC_ON()		0
++#define WL_L2FILTER_ON()	0
++#define WL_TXBF_ON()		0
++#define WL_P2PO_ON()		0
++#define WL_TSLOG_ON()		0
++#define WL_WNM_ON()		0
++#define WL_PCIE_ON()		0
++
++#else /* !BCMDBG */
++
++/* DBGONLY() macro to reduce ifdefs in code for statements that are only needed when
++ * BCMDBG is defined.
++ */
++#define DBGONLY(x)
++
++/* To disable a message completely ... until you need it again */
++#define WL_NONE(args)
++
++#define	WL_ERROR(args)
++#define	WL_TRACE(args)
++#define WL_APSTA_UPDN(args)
++#define WL_APSTA_RX(args)
++#ifdef WLMSG_WSEC
++#define WL_WSEC(args)		WL_PRINT(args)
++#define WL_WSEC_DUMP(args)	WL_PRINT(args)
++#else
++#define WL_WSEC(args)
++#define WL_WSEC_DUMP(args)
++#endif
++#define WL_PCIE(args)		do {if (wl_msg_level2 & WL_PCIE_VAL) WL_PRINT(args);} while (0)
++#define WL_PCIE_ON()		(wl_msg_level2 & WL_PCIE_VAL)
++#define WL_PFN(args)      do {if (wl_msg_level & WL_PFN_VAL) WL_PRINT(args);} while (0)
++#define WL_PFN_ON()		(wl_msg_level & WL_PFN_VAL)
++#endif 
++
++extern uint32 wl_msg_level;
++extern uint32 wl_msg_level2;
++#endif /* _wl_dbg_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_iw.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_iw.c
+new file mode 100644
+index 000000000..55cda4a0a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_iw.c
+@@ -0,0 +1,3801 @@
++/*
++ * Linux Wireless Extensions support
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_iw.c 709309 2019-01-17 09:04:00Z $
++ */
++
++#if defined(USE_IW)
++#define LINUX_PORT
++
++#include <typedefs.h>
++#include <linuxver.h>
++#include <osl.h>
++
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <proto/ethernet.h>
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)
++#include <linux/sched/signal.h>
++#endif
++
++#include <linux/if_arp.h>
++#include <asm/uaccess.h>
++
++#include <wlioctl.h>
++#include <wlioctl_utils.h>
++
++typedef const struct si_pub	si_t;
++
++#include <wl_dbg.h>
++#include <wl_iw.h>
++
++
++/* Broadcom extensions to WEXT, linux upstream has obsoleted WEXT */
++#ifndef IW_AUTH_KEY_MGMT_FT_802_1X
++#define IW_AUTH_KEY_MGMT_FT_802_1X 0x04
++#endif
++
++#ifndef IW_AUTH_KEY_MGMT_FT_PSK
++#define IW_AUTH_KEY_MGMT_FT_PSK 0x08
++#endif
++
++#ifndef IW_ENC_CAPA_FW_ROAM_ENABLE
++#define IW_ENC_CAPA_FW_ROAM_ENABLE	0x00000020
++#endif
++
++
++/* FC9: wireless.h 2.6.25-14.fc9.i686 is missing these, even though WIRELESS_EXT is set to latest
++ * version 22.
++ */
++#ifndef IW_ENCODE_ALG_PMK
++#define IW_ENCODE_ALG_PMK 4
++#endif
++#ifndef IW_ENC_CAPA_4WAY_HANDSHAKE
++#define IW_ENC_CAPA_4WAY_HANDSHAKE 0x00000010
++#endif
++/* End FC9. */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++#include <linux/rtnetlink.h>
++#endif
++#if defined(SOFTAP)
++struct net_device *ap_net_dev = NULL;
++tsk_ctl_t ap_eth_ctl;  /* apsta AP netdev waiter thread */
++#endif /* SOFTAP */
++
++extern bool wl_iw_conn_status_str(uint32 event_type, uint32 status,
++	uint32 reason, char* stringBuf, uint buflen);
++
++uint wl_msg_level = WL_ERROR_VAL;
++
++#define MAX_WLIW_IOCTL_LEN 1024
++
++/* IOCTL swapping mode for Big Endian host with Little Endian dongle.  Default to off */
++#define htod32(i) (i)
++#define htod16(i) (i)
++#define dtoh32(i) (i)
++#define dtoh16(i) (i)
++#define htodchanspec(i) (i)
++#define dtohchanspec(i) (i)
++
++extern struct iw_statistics *dhd_get_wireless_stats(struct net_device *dev);
++extern int dhd_wait_pend8021x(struct net_device *dev);
++
++#if WIRELESS_EXT < 19
++#define IW_IOCTL_IDX(cmd)	((cmd) - SIOCIWFIRST)
++#define IW_EVENT_IDX(cmd)	((cmd) - IWEVFIRST)
++#endif /* WIRELESS_EXT < 19 */
++
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++#define DAEMONIZE(a)	do { \
++		allow_signal(SIGKILL);	\
++		allow_signal(SIGTERM);	\
++	} while (0)
++#elif ((LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) && \
++	(LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)))
++#define DAEMONIZE(a) daemonize(a); \
++	allow_signal(SIGKILL); \
++	allow_signal(SIGTERM);
++#else /* Linux 2.4 (w/o preemption patch) */
++#define RAISE_RX_SOFTIRQ() \
++	cpu_raise_softirq(smp_processor_id(), NET_RX_SOFTIRQ)
++#define DAEMONIZE(a) daemonize(); \
++	do { if (a) \
++		strncpy(current->comm, a, MIN(sizeof(current->comm), (strlen(a) + 1))); \
++	} while (0);
++#endif /* LINUX_VERSION_CODE  */
++
++#define ISCAN_STATE_IDLE   0
++#define ISCAN_STATE_SCANING 1
++
++/* the buf lengh can be WLC_IOCTL_MAXLEN (8K) to reduce iteration */
++#define WLC_IW_ISCAN_MAXLEN   2048
++typedef struct iscan_buf {
++	struct iscan_buf * next;
++	char   iscan_buf[WLC_IW_ISCAN_MAXLEN];
++} iscan_buf_t;
++
++typedef struct iscan_info {
++	struct net_device *dev;
++	struct timer_list timer;
++	uint32 timer_ms;
++	uint32 timer_on;
++	int    iscan_state;
++	iscan_buf_t * list_hdr;
++	iscan_buf_t * list_cur;
++
++	/* Thread to work on iscan */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
++	struct task_struct *kthread;
++#endif
++	long sysioc_pid;
++	struct semaphore sysioc_sem;
++	struct completion sysioc_exited;
++
++
++	char ioctlbuf[WLC_IOCTL_SMLEN];
++} iscan_info_t;
++iscan_info_t *g_iscan = NULL;
++static void wl_iw_timerfunc(ulong data);
++static void wl_iw_set_event_mask(struct net_device *dev);
++static int wl_iw_iscan(iscan_info_t *iscan, wlc_ssid_t *ssid, uint16 action);
++
++/* priv_link becomes netdev->priv and is the link between netdev and wlif struct */
++typedef struct priv_link {
++	wl_iw_t *wliw;
++} priv_link_t;
++
++/* dev to priv_link */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
++#define WL_DEV_LINK(dev)       (priv_link_t*)(dev->priv)
++#else
++#define WL_DEV_LINK(dev)       (priv_link_t*)netdev_priv(dev)
++#endif
++
++/* dev to wl_iw_t */
++#define IW_DEV_IF(dev)          ((wl_iw_t*)(WL_DEV_LINK(dev))->wliw)
++
++static void swap_key_from_BE(
++	        wl_wsec_key_t *key
++)
++{
++	key->index = htod32(key->index);
++	key->len = htod32(key->len);
++	key->algo = htod32(key->algo);
++	key->flags = htod32(key->flags);
++	key->rxiv.hi = htod32(key->rxiv.hi);
++	key->rxiv.lo = htod16(key->rxiv.lo);
++	key->iv_initialized = htod32(key->iv_initialized);
++}
++
++static void swap_key_to_BE(
++	        wl_wsec_key_t *key
++)
++{
++	key->index = dtoh32(key->index);
++	key->len = dtoh32(key->len);
++	key->algo = dtoh32(key->algo);
++	key->flags = dtoh32(key->flags);
++	key->rxiv.hi = dtoh32(key->rxiv.hi);
++	key->rxiv.lo = dtoh16(key->rxiv.lo);
++	key->iv_initialized = dtoh32(key->iv_initialized);
++}
++
++static int
++dev_wlc_ioctl(
++	struct net_device *dev,
++	int cmd,
++	void *arg,
++	int len
++)
++{
++	struct ifreq ifr;
++	wl_ioctl_t ioc;
++	mm_segment_t fs;
++	int ret;
++
++	memset(&ioc, 0, sizeof(ioc));
++	ioc.cmd = cmd;
++	ioc.buf = arg;
++	ioc.len = len;
++
++	strncpy(ifr.ifr_name, dev->name, sizeof(ifr.ifr_name));
++	ifr.ifr_name[sizeof(ifr.ifr_name) - 1] = '\0';
++	ifr.ifr_data = (caddr_t) &ioc;
++
++	fs = get_fs();
++	set_fs(get_ds());
++#if defined(WL_USE_NETDEV_OPS)
++	ret = dev->netdev_ops->ndo_do_ioctl(dev, &ifr, SIOCDEVPRIVATE);
++#else
++	ret = dev->do_ioctl(dev, &ifr, SIOCDEVPRIVATE);
++#endif
++	set_fs(fs);
++
++	return ret;
++}
++
++/*
++set named driver variable to int value and return error indication
++calling example: dev_wlc_intvar_set(dev, "arate", rate)
++*/
++
++static int
++dev_wlc_intvar_set(
++	struct net_device *dev,
++	char *name,
++	int val)
++{
++	char buf[WLC_IOCTL_SMLEN];
++	uint len;
++
++	val = htod32(val);
++	len = bcm_mkiovar(name, (char *)(&val), sizeof(val), buf, sizeof(buf));
++	ASSERT(len);
++
++	return (dev_wlc_ioctl(dev, WLC_SET_VAR, buf, len));
++}
++
++static int
++dev_iw_iovar_setbuf(
++	struct net_device *dev,
++	char *iovar,
++	void *param,
++	int paramlen,
++	void *bufptr,
++	int buflen)
++{
++	int iolen;
++
++	iolen = bcm_mkiovar(iovar, param, paramlen, bufptr, buflen);
++	ASSERT(iolen);
++	BCM_REFERENCE(iolen);
++
++	return (dev_wlc_ioctl(dev, WLC_SET_VAR, bufptr, iolen));
++}
++
++static int
++dev_iw_iovar_getbuf(
++	struct net_device *dev,
++	char *iovar,
++	void *param,
++	int paramlen,
++	void *bufptr,
++	int buflen)
++{
++	int iolen;
++
++	iolen = bcm_mkiovar(iovar, param, paramlen, bufptr, buflen);
++	ASSERT(iolen);
++	BCM_REFERENCE(iolen);
++
++	return (dev_wlc_ioctl(dev, WLC_GET_VAR, bufptr, buflen));
++}
++
++#if WIRELESS_EXT > 17
++static int
++dev_wlc_bufvar_set(
++	struct net_device *dev,
++	char *name,
++	char *buf, int len)
++{
++	char *ioctlbuf;
++	uint buflen;
++	int error;
++
++	ioctlbuf = kmalloc(MAX_WLIW_IOCTL_LEN, GFP_KERNEL);
++	if (!ioctlbuf)
++		return -ENOMEM;
++
++	buflen = bcm_mkiovar(name, buf, len, ioctlbuf, MAX_WLIW_IOCTL_LEN);
++	ASSERT(buflen);
++	error = dev_wlc_ioctl(dev, WLC_SET_VAR, ioctlbuf, buflen);
++
++	kfree(ioctlbuf);
++	return error;
++}
++#endif /* WIRELESS_EXT > 17 */
++
++/*
++get named driver variable to int value and return error indication
++calling example: dev_wlc_bufvar_get(dev, "arate", &rate)
++*/
++
++static int
++dev_wlc_bufvar_get(
++	struct net_device *dev,
++	char *name,
++	char *buf, int buflen)
++{
++	char *ioctlbuf;
++	int error;
++
++	uint len;
++
++	ioctlbuf = kmalloc(MAX_WLIW_IOCTL_LEN, GFP_KERNEL);
++	if (!ioctlbuf)
++		return -ENOMEM;
++	len = bcm_mkiovar(name, NULL, 0, ioctlbuf, MAX_WLIW_IOCTL_LEN);
++	ASSERT(len);
++	BCM_REFERENCE(len);
++	error = dev_wlc_ioctl(dev, WLC_GET_VAR, (void *)ioctlbuf, MAX_WLIW_IOCTL_LEN);
++	if (!error)
++		bcopy(ioctlbuf, buf, buflen);
++
++	kfree(ioctlbuf);
++	return (error);
++}
++
++/*
++get named driver variable to int value and return error indication
++calling example: dev_wlc_intvar_get(dev, "arate", &rate)
++*/
++
++static int
++dev_wlc_intvar_get(
++	struct net_device *dev,
++	char *name,
++	int *retval)
++{
++	union {
++		char buf[WLC_IOCTL_SMLEN];
++		int val;
++	} var;
++	int error;
++
++	uint len;
++	uint data_null;
++
++	len = bcm_mkiovar(name, (char *)(&data_null), 0, (char *)(&var), sizeof(var.buf));
++	ASSERT(len);
++	error = dev_wlc_ioctl(dev, WLC_GET_VAR, (void *)&var, len);
++
++	*retval = dtoh32(var.val);
++
++	return (error);
++}
++
++/* Maintain backward compatibility */
++#if WIRELESS_EXT < 13
++struct iw_request_info
++{
++	__u16		cmd;		/* Wireless Extension command */
++	__u16		flags;		/* More to come ;-) */
++};
++
++typedef int (*iw_handler)(struct net_device *dev, struct iw_request_info *info,
++	void *wrqu, char *extra);
++#endif /* WIRELESS_EXT < 13 */
++
++#if WIRELESS_EXT > 12
++static int
++wl_iw_set_leddc(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	union iwreq_data *wrqu,
++	char *extra
++)
++{
++	int dc = *(int *)extra;
++	int error;
++
++	error = dev_wlc_intvar_set(dev, "leddc", dc);
++	return error;
++}
++
++static int
++wl_iw_set_vlanmode(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	union iwreq_data *wrqu,
++	char *extra
++)
++{
++	int mode = *(int *)extra;
++	int error;
++
++	mode = htod32(mode);
++	error = dev_wlc_intvar_set(dev, "vlan_mode", mode);
++	return error;
++}
++
++static int
++wl_iw_set_pm(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	union iwreq_data *wrqu,
++	char *extra
++)
++{
++	int pm = *(int *)extra;
++	int error;
++
++	pm = htod32(pm);
++	error = dev_wlc_ioctl(dev, WLC_SET_PM, &pm, sizeof(pm));
++	return error;
++}
++
++#if WIRELESS_EXT > 17
++#endif /* WIRELESS_EXT > 17 */
++#endif /* WIRELESS_EXT > 12 */
++
++int
++wl_iw_send_priv_event(
++	struct net_device *dev,
++	char *flag
++)
++{
++	union iwreq_data wrqu;
++	char extra[IW_CUSTOM_MAX + 1];
++	int cmd;
++
++	cmd = IWEVCUSTOM;
++	memset(&wrqu, 0, sizeof(wrqu));
++	if (strlen(flag) > sizeof(extra))
++		return -1;
++
++	strncpy(extra, flag, sizeof(extra));
++	extra[sizeof(extra) - 1] = '\0';
++	wrqu.data.length = strlen(extra);
++	wireless_send_event(dev, cmd, &wrqu, extra);
++	WL_TRACE(("Send IWEVCUSTOM Event as %s\n", extra));
++
++	return 0;
++}
++
++static int
++wl_iw_config_commit(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	void *zwrq,
++	char *extra
++)
++{
++	wlc_ssid_t ssid;
++	int error;
++	struct sockaddr bssid;
++
++	WL_TRACE(("%s: SIOCSIWCOMMIT\n", dev->name));
++
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_SSID, &ssid, sizeof(ssid))))
++		return error;
++
++	ssid.SSID_len = dtoh32(ssid.SSID_len);
++
++	if (!ssid.SSID_len)
++		return 0;
++
++	bzero(&bssid, sizeof(struct sockaddr));
++	if ((error = dev_wlc_ioctl(dev, WLC_REASSOC, &bssid, ETHER_ADDR_LEN))) {
++		WL_ERROR(("%s: WLC_REASSOC failed (%d)\n", __FUNCTION__, error));
++		return error;
++	}
++
++	return 0;
++}
++
++static int
++wl_iw_get_name(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	union iwreq_data *cwrq,
++	char *extra
++)
++{
++	int phytype, err;
++	uint band[3];
++	char cap[5];
++
++	WL_TRACE(("%s: SIOCGIWNAME\n", dev->name));
++
++	cap[0] = 0;
++	if ((err = dev_wlc_ioctl(dev, WLC_GET_PHYTYPE, &phytype, sizeof(phytype))) < 0)
++		goto done;
++	if ((err = dev_wlc_ioctl(dev, WLC_GET_BANDLIST, band, sizeof(band))) < 0)
++		goto done;
++
++	band[0] = dtoh32(band[0]);
++	switch (phytype) {
++		case WLC_PHY_TYPE_A:
++			strncpy(cap, "a", sizeof(cap));
++			break;
++		case WLC_PHY_TYPE_B:
++			strncpy(cap, "b", sizeof(cap));
++			break;
++		case WLC_PHY_TYPE_G:
++			if (band[0] >= 2)
++				strncpy(cap, "abg", sizeof(cap));
++			else
++				strncpy(cap, "bg", sizeof(cap));
++			break;
++		case WLC_PHY_TYPE_N:
++			if (band[0] >= 2)
++				strncpy(cap, "abgn", sizeof(cap));
++			else
++				strncpy(cap, "bgn", sizeof(cap));
++			break;
++	}
++done:
++	(void)snprintf(cwrq->name, IFNAMSIZ, "IEEE 802.11%s", cap);
++
++	return 0;
++}
++
++static int
++wl_iw_set_freq(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_freq *fwrq,
++	char *extra
++)
++{
++	int error, chan;
++	uint sf = 0;
++
++	WL_TRACE(("%s: SIOCSIWFREQ\n", dev->name));
++
++	/* Setting by channel number */
++	if (fwrq->e == 0 && fwrq->m < MAXCHANNEL) {
++		chan = fwrq->m;
++	}
++
++	/* Setting by frequency */
++	else {
++		/* Convert to MHz as best we can */
++		if (fwrq->e >= 6) {
++			fwrq->e -= 6;
++			while (fwrq->e--)
++				fwrq->m *= 10;
++		} else if (fwrq->e < 6) {
++			while (fwrq->e++ < 6)
++				fwrq->m /= 10;
++		}
++	/* handle 4.9GHz frequencies as Japan 4 GHz based channelization */
++		if (fwrq->m > 4000 && fwrq->m < 5000)
++			sf = WF_CHAN_FACTOR_4_G; /* start factor for 4 GHz */
++
++		chan = wf_mhz2channel(fwrq->m, sf);
++	}
++	chan = htod32(chan);
++	if ((error = dev_wlc_ioctl(dev, WLC_SET_CHANNEL, &chan, sizeof(chan))))
++		return error;
++
++	/* -EINPROGRESS: Call commit handler */
++	return -EINPROGRESS;
++}
++
++static int
++wl_iw_get_freq(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_freq *fwrq,
++	char *extra
++)
++{
++	channel_info_t ci;
++	int error;
++
++	WL_TRACE(("%s: SIOCGIWFREQ\n", dev->name));
++
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_CHANNEL, &ci, sizeof(ci))))
++		return error;
++
++	/* Return radio channel in channel form */
++	fwrq->m = dtoh32(ci.hw_channel);
++	fwrq->e = dtoh32(0);
++	return 0;
++}
++
++static int
++wl_iw_set_mode(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	__u32 *uwrq,
++	char *extra
++)
++{
++	int infra = 0, ap = 0, error = 0;
++
++	WL_TRACE(("%s: SIOCSIWMODE\n", dev->name));
++
++	switch (*uwrq) {
++	case IW_MODE_MASTER:
++		infra = ap = 1;
++		break;
++	case IW_MODE_ADHOC:
++	case IW_MODE_AUTO:
++		break;
++	case IW_MODE_INFRA:
++		infra = 1;
++		break;
++	default:
++		return -EINVAL;
++	}
++	infra = htod32(infra);
++	ap = htod32(ap);
++
++	if ((error = dev_wlc_ioctl(dev, WLC_SET_INFRA, &infra, sizeof(infra))) ||
++	    (error = dev_wlc_ioctl(dev, WLC_SET_AP, &ap, sizeof(ap))))
++		return error;
++
++	/* -EINPROGRESS: Call commit handler */
++	return -EINPROGRESS;
++}
++
++static int
++wl_iw_get_mode(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	__u32 *uwrq,
++	char *extra
++)
++{
++	int error, infra = 0, ap = 0;
++
++	WL_TRACE(("%s: SIOCGIWMODE\n", dev->name));
++
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_INFRA, &infra, sizeof(infra))) ||
++	    (error = dev_wlc_ioctl(dev, WLC_GET_AP, &ap, sizeof(ap))))
++		return error;
++
++	infra = dtoh32(infra);
++	ap = dtoh32(ap);
++	*uwrq = infra ? ap ? IW_MODE_MASTER : IW_MODE_INFRA : IW_MODE_ADHOC;
++
++	return 0;
++}
++
++static int
++wl_iw_get_range(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	struct iw_range *range = (struct iw_range *) extra;
++	static int channels[MAXCHANNEL+1];
++	wl_uint32_list_t *list = (wl_uint32_list_t *) channels;
++	wl_rateset_t rateset;
++	int error, i, k;
++	uint sf, ch;
++
++	int phytype;
++	int bw_cap = 0, sgi_tx = 0, nmode = 0;
++	channel_info_t ci;
++	uint8 nrate_list2copy = 0;
++	uint16 nrate_list[4][8] = { {13, 26, 39, 52, 78, 104, 117, 130},
++		{14, 29, 43, 58, 87, 116, 130, 144},
++		{27, 54, 81, 108, 162, 216, 243, 270},
++		{30, 60, 90, 120, 180, 240, 270, 300}};
++	int fbt_cap = 0;
++
++	WL_TRACE(("%s: SIOCGIWRANGE\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	dwrq->length = sizeof(struct iw_range);
++	memset(range, 0, sizeof(*range));
++
++	/* We don't use nwids */
++	range->min_nwid = range->max_nwid = 0;
++
++	/* Set available channels/frequencies */
++	list->count = htod32(MAXCHANNEL);
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_VALID_CHANNELS, channels, sizeof(channels))))
++		return error;
++	for (i = 0; i < dtoh32(list->count) && i < IW_MAX_FREQUENCIES; i++) {
++		range->freq[i].i = dtoh32(list->element[i]);
++
++		ch = dtoh32(list->element[i]);
++		if (ch <= CH_MAX_2G_CHANNEL)
++			sf = WF_CHAN_FACTOR_2_4_G;
++		else
++			sf = WF_CHAN_FACTOR_5_G;
++
++		range->freq[i].m = wf_channel2mhz(ch, sf);
++		range->freq[i].e = 6;
++	}
++	range->num_frequency = range->num_channels = i;
++
++	/* Link quality (use NDIS cutoffs) */
++	range->max_qual.qual = 5;
++	/* Signal level (use RSSI) */
++	range->max_qual.level = 0x100 - 200;	/* -200 dBm */
++	/* Noise level (use noise) */
++	range->max_qual.noise = 0x100 - 200;	/* -200 dBm */
++	/* Signal level threshold range (?) */
++	range->sensitivity = 65535;
++
++#if WIRELESS_EXT > 11
++	/* Link quality (use NDIS cutoffs) */
++	range->avg_qual.qual = 3;
++	/* Signal level (use RSSI) */
++	range->avg_qual.level = 0x100 + WL_IW_RSSI_GOOD;
++	/* Noise level (use noise) */
++	range->avg_qual.noise = 0x100 - 75;	/* -75 dBm */
++#endif /* WIRELESS_EXT > 11 */
++
++	/* Set available bitrates */
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_CURR_RATESET, &rateset, sizeof(rateset))))
++		return error;
++	rateset.count = dtoh32(rateset.count);
++	range->num_bitrates = rateset.count;
++	for (i = 0; i < rateset.count && i < IW_MAX_BITRATES; i++)
++		range->bitrate[i] = (rateset.rates[i] & 0x7f) * 500000; /* convert to bps */
++	if ((error = dev_wlc_intvar_get(dev, "nmode", &nmode)))
++		return error;
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_PHYTYPE, &phytype, sizeof(phytype))))
++		return error;
++	if (nmode == 1 && (((phytype == WLC_PHY_TYPE_LCN) ||
++	                    (phytype == WLC_PHY_TYPE_LCN40)))) {
++		if ((error = dev_wlc_intvar_get(dev, "mimo_bw_cap", &bw_cap)))
++			return error;
++		if ((error = dev_wlc_intvar_get(dev, "sgi_tx", &sgi_tx)))
++			return error;
++		if ((error = dev_wlc_ioctl(dev, WLC_GET_CHANNEL, &ci, sizeof(channel_info_t))))
++			return error;
++		ci.hw_channel = dtoh32(ci.hw_channel);
++
++		if (bw_cap == 0 ||
++			(bw_cap == 2 && ci.hw_channel <= 14)) {
++			if (sgi_tx == 0)
++				nrate_list2copy = 0;
++			else
++				nrate_list2copy = 1;
++		}
++		if (bw_cap == 1 ||
++			(bw_cap == 2 && ci.hw_channel >= 36)) {
++			if (sgi_tx == 0)
++				nrate_list2copy = 2;
++			else
++				nrate_list2copy = 3;
++		}
++		range->num_bitrates += 8;
++		ASSERT(range->num_bitrates < IW_MAX_BITRATES);
++		for (k = 0; i < range->num_bitrates; k++, i++) {
++			/* convert to bps */
++			range->bitrate[i] = (nrate_list[nrate_list2copy][k]) * 500000;
++		}
++	}
++
++	/* Set an indication of the max TCP throughput
++	 * in bit/s that we can expect using this interface.
++	 * May be use for QoS stuff... Jean II
++	 */
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_PHYTYPE, &i, sizeof(i))))
++		return error;
++	i = dtoh32(i);
++	if (i == WLC_PHY_TYPE_A)
++		range->throughput = 24000000;	/* 24 Mbits/s */
++	else
++		range->throughput = 1500000;	/* 1.5 Mbits/s */
++
++	/* RTS and fragmentation thresholds */
++	range->min_rts = 0;
++	range->max_rts = 2347;
++	range->min_frag = 256;
++	range->max_frag = 2346;
++
++	range->max_encoding_tokens = DOT11_MAX_DEFAULT_KEYS;
++	range->num_encoding_sizes = 4;
++	range->encoding_size[0] = WEP1_KEY_SIZE;
++	range->encoding_size[1] = WEP128_KEY_SIZE;
++#if WIRELESS_EXT > 17
++	range->encoding_size[2] = TKIP_KEY_SIZE;
++#else
++	range->encoding_size[2] = 0;
++#endif
++	range->encoding_size[3] = AES_KEY_SIZE;
++
++	/* Do not support power micro-management */
++	range->min_pmp = 0;
++	range->max_pmp = 0;
++	range->min_pmt = 0;
++	range->max_pmt = 0;
++	range->pmp_flags = 0;
++	range->pm_capa = 0;
++
++	/* Transmit Power - values are in mW */
++	range->num_txpower = 2;
++	range->txpower[0] = 1;
++	range->txpower[1] = 255;
++	range->txpower_capa = IW_TXPOW_MWATT;
++
++#if WIRELESS_EXT > 10
++	range->we_version_compiled = WIRELESS_EXT;
++	range->we_version_source = 19;
++
++	/* Only support retry limits */
++	range->retry_capa = IW_RETRY_LIMIT;
++	range->retry_flags = IW_RETRY_LIMIT;
++	range->r_time_flags = 0;
++	/* SRL and LRL limits */
++	range->min_retry = 1;
++	range->max_retry = 255;
++	/* Retry lifetime limits unsupported */
++	range->min_r_time = 0;
++	range->max_r_time = 0;
++#endif /* WIRELESS_EXT > 10 */
++
++#if WIRELESS_EXT > 17
++	range->enc_capa = IW_ENC_CAPA_WPA;
++	range->enc_capa |= IW_ENC_CAPA_CIPHER_TKIP;
++	range->enc_capa |= IW_ENC_CAPA_CIPHER_CCMP;
++	range->enc_capa |= IW_ENC_CAPA_WPA2;
++
++	/* Determine driver FBT capability. */
++	if (dev_wlc_intvar_get(dev, "fbt_cap", &fbt_cap) == 0) {
++		if (fbt_cap == WLC_FBT_CAP_DRV_4WAY_AND_REASSOC) {
++			/* Tell the host (e.g. wpa_supplicant) to let driver do the handshake */
++			range->enc_capa |= IW_ENC_CAPA_4WAY_HANDSHAKE;
++		}
++	}
++
++#ifdef BCMFW_ROAM_ENABLE_WEXT
++	/* Advertise firmware roam capability to the external supplicant */
++	range->enc_capa |= IW_ENC_CAPA_FW_ROAM_ENABLE;
++#endif /* BCMFW_ROAM_ENABLE_WEXT */
++
++	/* Event capability (kernel) */
++	IW_EVENT_CAPA_SET_KERNEL(range->event_capa);
++	/* Event capability (driver) */
++	IW_EVENT_CAPA_SET(range->event_capa, SIOCGIWAP);
++	IW_EVENT_CAPA_SET(range->event_capa, SIOCGIWSCAN);
++	IW_EVENT_CAPA_SET(range->event_capa, IWEVTXDROP);
++	IW_EVENT_CAPA_SET(range->event_capa, IWEVMICHAELMICFAILURE);
++	IW_EVENT_CAPA_SET(range->event_capa, IWEVASSOCREQIE);
++	IW_EVENT_CAPA_SET(range->event_capa, IWEVASSOCRESPIE);
++	IW_EVENT_CAPA_SET(range->event_capa, IWEVPMKIDCAND);
++
++#if WIRELESS_EXT >= 22 && defined(IW_SCAN_CAPA_ESSID)
++	/* FC7 wireless.h defines EXT 22 but doesn't define scan_capa bits */
++	range->scan_capa = IW_SCAN_CAPA_ESSID;
++#endif
++#endif /* WIRELESS_EXT > 17 */
++
++	return 0;
++}
++
++static int
++rssi_to_qual(int rssi)
++{
++	if (rssi <= WL_IW_RSSI_NO_SIGNAL)
++		return 0;
++	else if (rssi <= WL_IW_RSSI_VERY_LOW)
++		return 1;
++	else if (rssi <= WL_IW_RSSI_LOW)
++		return 2;
++	else if (rssi <= WL_IW_RSSI_GOOD)
++		return 3;
++	else if (rssi <= WL_IW_RSSI_VERY_GOOD)
++		return 4;
++	else
++		return 5;
++}
++
++static int
++wl_iw_set_spy(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_iw_t *iw = IW_DEV_IF(dev);
++	struct sockaddr *addr = (struct sockaddr *) extra;
++	int i;
++
++	WL_TRACE(("%s: SIOCSIWSPY\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	iw->spy_num = MIN(ARRAYSIZE(iw->spy_addr), dwrq->length);
++	for (i = 0; i < iw->spy_num; i++)
++		memcpy(&iw->spy_addr[i], addr[i].sa_data, ETHER_ADDR_LEN);
++	memset(iw->spy_qual, 0, sizeof(iw->spy_qual));
++
++	return 0;
++}
++
++static int
++wl_iw_get_spy(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_iw_t *iw = IW_DEV_IF(dev);
++	struct sockaddr *addr = (struct sockaddr *) extra;
++	struct iw_quality *qual = (struct iw_quality *) &addr[iw->spy_num];
++	int i;
++
++	WL_TRACE(("%s: SIOCGIWSPY\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	dwrq->length = iw->spy_num;
++	for (i = 0; i < iw->spy_num; i++) {
++		memcpy(addr[i].sa_data, &iw->spy_addr[i], ETHER_ADDR_LEN);
++		addr[i].sa_family = AF_UNIX;
++		memcpy(&qual[i], &iw->spy_qual[i], sizeof(struct iw_quality));
++		iw->spy_qual[i].updated = 0;
++	}
++
++	return 0;
++}
++
++static int
++wl_iw_set_wap(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct sockaddr *awrq,
++	char *extra
++)
++{
++	int error = -EINVAL;
++
++	WL_TRACE(("%s: SIOCSIWAP\n", dev->name));
++
++	if (awrq->sa_family != ARPHRD_ETHER) {
++		WL_ERROR(("%s: Invalid Header...sa_family\n", __FUNCTION__));
++		return -EINVAL;
++	}
++
++	/* Ignore "auto" or "off" */
++	if (ETHER_ISBCAST(awrq->sa_data) || ETHER_ISNULLADDR(awrq->sa_data)) {
++		scb_val_t scbval;
++		bzero(&scbval, sizeof(scb_val_t));
++		if ((error = dev_wlc_ioctl(dev, WLC_DISASSOC, &scbval, sizeof(scb_val_t)))) {
++			WL_ERROR(("%s: WLC_DISASSOC failed (%d).\n", __FUNCTION__, error));
++		}
++		return 0;
++	}
++	/* WL_ASSOC(("Assoc to %s\n", bcm_ether_ntoa((struct ether_addr *)&(awrq->sa_data),
++	 * eabuf)));
++	 */
++	/* Reassociate to the specified AP */
++	if ((error = dev_wlc_ioctl(dev, WLC_REASSOC, awrq->sa_data, ETHER_ADDR_LEN))) {
++		WL_ERROR(("%s: WLC_REASSOC failed (%d).\n", __FUNCTION__, error));
++		return error;
++	}
++
++	return 0;
++}
++
++static int
++wl_iw_get_wap(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct sockaddr *awrq,
++	char *extra
++)
++{
++	WL_TRACE(("%s: SIOCGIWAP\n", dev->name));
++
++	awrq->sa_family = ARPHRD_ETHER;
++	memset(awrq->sa_data, 0, ETHER_ADDR_LEN);
++
++	/* Ignore error (may be down or disassociated) */
++	(void) dev_wlc_ioctl(dev, WLC_GET_BSSID, awrq->sa_data, ETHER_ADDR_LEN);
++
++	return 0;
++}
++
++#if WIRELESS_EXT > 17
++static int
++wl_iw_mlme(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct sockaddr *awrq,
++	char *extra
++)
++{
++	struct iw_mlme *mlme;
++	scb_val_t scbval;
++	int error  = -EINVAL;
++
++	WL_TRACE(("%s: SIOCSIWMLME\n", dev->name));
++
++	mlme = (struct iw_mlme *)extra;
++	if (mlme == NULL) {
++		WL_ERROR(("Invalid ioctl data.\n"));
++		return error;
++	}
++
++	scbval.val = mlme->reason_code;
++	bcopy(&mlme->addr.sa_data, &scbval.ea, ETHER_ADDR_LEN);
++
++	if (mlme->cmd == IW_MLME_DISASSOC) {
++		scbval.val = htod32(scbval.val);
++		error = dev_wlc_ioctl(dev, WLC_DISASSOC, &scbval, sizeof(scb_val_t));
++	}
++	else if (mlme->cmd == IW_MLME_DEAUTH) {
++		scbval.val = htod32(scbval.val);
++		error = dev_wlc_ioctl(dev, WLC_SCB_DEAUTHENTICATE_FOR_REASON, &scbval,
++			sizeof(scb_val_t));
++	}
++	else {
++		WL_ERROR(("%s: Invalid ioctl data.\n", __FUNCTION__));
++		return error;
++	}
++
++	return error;
++}
++#endif /* WIRELESS_EXT > 17 */
++
++static int
++wl_iw_get_aplist(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_scan_results_t *list;
++	struct sockaddr *addr = (struct sockaddr *) extra;
++	struct iw_quality qual[IW_MAX_AP];
++	wl_bss_info_t *bi = NULL;
++	int error, i;
++	uint buflen = dwrq->length;
++
++	WL_TRACE(("%s: SIOCGIWAPLIST\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	/* Get scan results (too large to put on the stack) */
++	list = kmalloc(buflen, GFP_KERNEL);
++	if (!list)
++		return -ENOMEM;
++	memset(list, 0, buflen);
++	list->buflen = htod32(buflen);
++	if ((error = dev_wlc_ioctl(dev, WLC_SCAN_RESULTS, list, buflen))) {
++		WL_ERROR(("%d: Scan results error %d\n", __LINE__, error));
++		kfree(list);
++		return error;
++	}
++	list->buflen = dtoh32(list->buflen);
++	list->version = dtoh32(list->version);
++	list->count = dtoh32(list->count);
++	ASSERT(list->version == WL_BSS_INFO_VERSION);
++
++	for (i = 0, dwrq->length = 0; i < list->count && dwrq->length < IW_MAX_AP; i++) {
++		bi = bi ? (wl_bss_info_t *)((uintptr)bi + dtoh32(bi->length)) : list->bss_info;
++		ASSERT(((uintptr)bi + dtoh32(bi->length)) <= ((uintptr)list +
++			buflen));
++
++		/* Infrastructure only */
++		if (!(dtoh16(bi->capability) & DOT11_CAP_ESS))
++			continue;
++
++		/* BSSID */
++		memcpy(addr[dwrq->length].sa_data, &bi->BSSID, ETHER_ADDR_LEN);
++		addr[dwrq->length].sa_family = ARPHRD_ETHER;
++		qual[dwrq->length].qual = rssi_to_qual(dtoh16(bi->RSSI));
++		qual[dwrq->length].level = 0x100 + dtoh16(bi->RSSI);
++		qual[dwrq->length].noise = 0x100 + bi->phy_noise;
++
++		/* Updated qual, level, and noise */
++#if WIRELESS_EXT > 18
++		qual[dwrq->length].updated = IW_QUAL_ALL_UPDATED | IW_QUAL_DBM;
++#else
++		qual[dwrq->length].updated = 7;
++#endif /* WIRELESS_EXT > 18 */
++
++		dwrq->length++;
++	}
++
++	kfree(list);
++
++	if (dwrq->length) {
++		memcpy(&addr[dwrq->length], qual, sizeof(struct iw_quality) * dwrq->length);
++		/* Provided qual */
++		dwrq->flags = 1;
++	}
++
++	return 0;
++}
++
++static int
++wl_iw_iscan_get_aplist(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_scan_results_t *list;
++	iscan_buf_t * buf;
++	iscan_info_t *iscan = g_iscan;
++
++	struct sockaddr *addr = (struct sockaddr *) extra;
++	struct iw_quality qual[IW_MAX_AP];
++	wl_bss_info_t *bi = NULL;
++	int i;
++
++	WL_TRACE(("%s: SIOCGIWAPLIST\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	if ((!iscan) || (iscan->sysioc_pid < 0)) {
++		return wl_iw_get_aplist(dev, info, dwrq, extra);
++	}
++
++	buf = iscan->list_hdr;
++	/* Get scan results (too large to put on the stack) */
++	while (buf) {
++	    list = &((wl_iscan_results_t*)buf->iscan_buf)->results;
++	    ASSERT(list->version == WL_BSS_INFO_VERSION);
++
++	    bi = NULL;
++	for (i = 0, dwrq->length = 0; i < list->count && dwrq->length < IW_MAX_AP; i++) {
++		bi = bi ? (wl_bss_info_t *)((uintptr)bi + dtoh32(bi->length)) : list->bss_info;
++		ASSERT(((uintptr)bi + dtoh32(bi->length)) <= ((uintptr)list +
++			WLC_IW_ISCAN_MAXLEN));
++
++		/* Infrastructure only */
++		if (!(dtoh16(bi->capability) & DOT11_CAP_ESS))
++			continue;
++
++		/* BSSID */
++		memcpy(addr[dwrq->length].sa_data, &bi->BSSID, ETHER_ADDR_LEN);
++		addr[dwrq->length].sa_family = ARPHRD_ETHER;
++		qual[dwrq->length].qual = rssi_to_qual(dtoh16(bi->RSSI));
++		qual[dwrq->length].level = 0x100 + dtoh16(bi->RSSI);
++		qual[dwrq->length].noise = 0x100 + bi->phy_noise;
++
++		/* Updated qual, level, and noise */
++#if WIRELESS_EXT > 18
++		qual[dwrq->length].updated = IW_QUAL_ALL_UPDATED | IW_QUAL_DBM;
++#else
++		qual[dwrq->length].updated = 7;
++#endif /* WIRELESS_EXT > 18 */
++
++		dwrq->length++;
++	    }
++	    buf = buf->next;
++	}
++	if (dwrq->length) {
++		memcpy(&addr[dwrq->length], qual, sizeof(struct iw_quality) * dwrq->length);
++		/* Provided qual */
++		dwrq->flags = 1;
++	}
++
++	return 0;
++}
++
++#if WIRELESS_EXT > 13
++static int
++wl_iw_set_scan(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	union iwreq_data *wrqu,
++	char *extra
++)
++{
++	wlc_ssid_t ssid;
++
++	WL_TRACE(("%s: SIOCSIWSCAN\n", dev->name));
++
++	/* default Broadcast scan */
++	memset(&ssid, 0, sizeof(ssid));
++
++#if WIRELESS_EXT > 17
++	/* check for given essid */
++	if (wrqu->data.length == sizeof(struct iw_scan_req)) {
++		if (wrqu->data.flags & IW_SCAN_THIS_ESSID) {
++			struct iw_scan_req *req = (struct iw_scan_req *)extra;
++			ssid.SSID_len = MIN(sizeof(ssid.SSID), req->essid_len);
++			memcpy(ssid.SSID, req->essid, ssid.SSID_len);
++			ssid.SSID_len = htod32(ssid.SSID_len);
++		}
++	}
++#endif
++	/* Ignore error (most likely scan in progress) */
++	(void) dev_wlc_ioctl(dev, WLC_SCAN, &ssid, sizeof(ssid));
++
++	return 0;
++}
++
++static int
++wl_iw_iscan_set_scan(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	union iwreq_data *wrqu,
++	char *extra
++)
++{
++	wlc_ssid_t ssid;
++	iscan_info_t *iscan = g_iscan;
++
++	WL_TRACE(("%s: SIOCSIWSCAN\n", dev->name));
++
++	/* use backup if our thread is not successful */
++	if ((!iscan) || (iscan->sysioc_pid < 0)) {
++		return wl_iw_set_scan(dev, info, wrqu, extra);
++	}
++	if (iscan->iscan_state == ISCAN_STATE_SCANING) {
++		return 0;
++	}
++
++	/* default Broadcast scan */
++	memset(&ssid, 0, sizeof(ssid));
++
++#if WIRELESS_EXT > 17
++	/* check for given essid */
++	if (wrqu->data.length == sizeof(struct iw_scan_req)) {
++		if (wrqu->data.flags & IW_SCAN_THIS_ESSID) {
++			struct iw_scan_req *req = (struct iw_scan_req *)extra;
++			ssid.SSID_len = MIN(sizeof(ssid.SSID), req->essid_len);
++			memcpy(ssid.SSID, req->essid, ssid.SSID_len);
++			ssid.SSID_len = htod32(ssid.SSID_len);
++		}
++	}
++#endif
++
++	iscan->list_cur = iscan->list_hdr;
++	iscan->iscan_state = ISCAN_STATE_SCANING;
++
++
++	wl_iw_set_event_mask(dev);
++	wl_iw_iscan(iscan, &ssid, WL_SCAN_ACTION_START);
++
++	iscan->timer.expires = jiffies + msecs_to_jiffies(iscan->timer_ms);
++	add_timer(&iscan->timer);
++	iscan->timer_on = 1;
++
++	return 0;
++}
++
++#if WIRELESS_EXT > 17
++static bool
++ie_is_wpa_ie(uint8 **wpaie, uint8 **tlvs, int *tlvs_len)
++{
++/* Is this body of this tlvs entry a WPA entry? If */
++/* not update the tlvs buffer pointer/length */
++	uint8 *ie = *wpaie;
++
++	/* If the contents match the WPA_OUI and type=1 */
++	if ((ie[1] >= 6) &&
++		!bcmp((const void *)&ie[2], (const void *)(WPA_OUI "\x01"), 4)) {
++		return TRUE;
++	}
++
++	/* point to the next ie */
++	ie += ie[1] + 2;
++	/* calculate the length of the rest of the buffer */
++	*tlvs_len -= (int)(ie - *tlvs);
++	/* update the pointer to the start of the buffer */
++	*tlvs = ie;
++	return FALSE;
++}
++
++static bool
++ie_is_wps_ie(uint8 **wpsie, uint8 **tlvs, int *tlvs_len)
++{
++/* Is this body of this tlvs entry a WPS entry? If */
++/* not update the tlvs buffer pointer/length */
++	uint8 *ie = *wpsie;
++
++	/* If the contents match the WPA_OUI and type=4 */
++	if ((ie[1] >= 4) &&
++		!bcmp((const void *)&ie[2], (const void *)(WPA_OUI "\x04"), 4)) {
++		return TRUE;
++	}
++
++	/* point to the next ie */
++	ie += ie[1] + 2;
++	/* calculate the length of the rest of the buffer */
++	*tlvs_len -= (int)(ie - *tlvs);
++	/* update the pointer to the start of the buffer */
++	*tlvs = ie;
++	return FALSE;
++}
++#endif /* WIRELESS_EXT > 17 */
++
++
++static int
++wl_iw_handle_scanresults_ies(char **event_p, char *end,
++	struct iw_request_info *info, wl_bss_info_t *bi)
++{
++#if WIRELESS_EXT > 17
++	struct iw_event	iwe;
++	char *event;
++
++	event = *event_p;
++	if (bi->ie_length) {
++		/* look for wpa/rsn ies in the ie list... */
++		bcm_tlv_t *ie;
++		uint8 *ptr = ((uint8 *)bi) + bi->ie_offset;
++		int ptr_len = bi->ie_length;
++
++		/* OSEN IE */
++		if ((ie = bcm_parse_tlvs(ptr, ptr_len, DOT11_MNG_VS_ID)) &&
++			ie->len > WFA_OUI_LEN + 1 &&
++			!bcmp((const void *)&ie->data[0], (const void *)WFA_OUI, WFA_OUI_LEN) &&
++			ie->data[WFA_OUI_LEN] == WFA_OUI_TYPE_OSEN) {
++			iwe.cmd = IWEVGENIE;
++			iwe.u.data.length = ie->len + 2;
++			event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, (char *)ie);
++		}
++		ptr = ((uint8 *)bi) + bi->ie_offset;
++
++		if ((ie = bcm_parse_tlvs(ptr, ptr_len, DOT11_MNG_RSN_ID))) {
++			iwe.cmd = IWEVGENIE;
++			iwe.u.data.length = ie->len + 2;
++			event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, (char *)ie);
++		}
++		ptr = ((uint8 *)bi) + bi->ie_offset;
++
++		if ((ie = bcm_parse_tlvs(ptr, ptr_len, DOT11_MNG_MDIE_ID))) {
++			iwe.cmd = IWEVGENIE;
++			iwe.u.data.length = ie->len + 2;
++			event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, (char *)ie);
++		}
++		ptr = ((uint8 *)bi) + bi->ie_offset;
++
++		while ((ie = bcm_parse_tlvs(ptr, ptr_len, DOT11_MNG_WPA_ID))) {
++			/* look for WPS IE */
++			if (ie_is_wps_ie(((uint8 **)&ie), &ptr, &ptr_len)) {
++				iwe.cmd = IWEVGENIE;
++				iwe.u.data.length = ie->len + 2;
++				event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, (char *)ie);
++				break;
++			}
++		}
++
++		ptr = ((uint8 *)bi) + bi->ie_offset;
++		ptr_len = bi->ie_length;
++		while ((ie = bcm_parse_tlvs(ptr, ptr_len, DOT11_MNG_WPA_ID))) {
++			if (ie_is_wpa_ie(((uint8 **)&ie), &ptr, &ptr_len)) {
++				iwe.cmd = IWEVGENIE;
++				iwe.u.data.length = ie->len + 2;
++				event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, (char *)ie);
++				break;
++			}
++		}
++
++	*event_p = event;
++	}
++
++#endif /* WIRELESS_EXT > 17 */
++	return 0;
++}
++static int
++wl_iw_get_scan(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	channel_info_t ci;
++	wl_scan_results_t *list;
++	struct iw_event	iwe;
++	wl_bss_info_t *bi = NULL;
++	int error, i, j;
++	char *event = extra, *end = extra + dwrq->length, *value;
++	uint buflen = dwrq->length;
++
++	WL_TRACE(("%s: SIOCGIWSCAN\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	/* Check for scan in progress */
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_CHANNEL, &ci, sizeof(ci))))
++		return error;
++	ci.scan_channel = dtoh32(ci.scan_channel);
++	if (ci.scan_channel)
++		return -EAGAIN;
++
++	/* Get scan results (too large to put on the stack) */
++	list = kmalloc(buflen, GFP_KERNEL);
++	if (!list)
++		return -ENOMEM;
++	memset(list, 0, buflen);
++	list->buflen = htod32(buflen);
++	if ((error = dev_wlc_ioctl(dev, WLC_SCAN_RESULTS, list, buflen))) {
++		kfree(list);
++		return error;
++	}
++	list->buflen = dtoh32(list->buflen);
++	list->version = dtoh32(list->version);
++	list->count = dtoh32(list->count);
++
++	ASSERT(list->version == WL_BSS_INFO_VERSION);
++
++	for (i = 0; i < list->count && i < IW_MAX_AP; i++) {
++		bi = bi ? (wl_bss_info_t *)((uintptr)bi + dtoh32(bi->length)) : list->bss_info;
++		ASSERT(((uintptr)bi + dtoh32(bi->length)) <= ((uintptr)list +
++			buflen));
++
++		/* First entry must be the BSSID */
++		iwe.cmd = SIOCGIWAP;
++		iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
++		memcpy(iwe.u.ap_addr.sa_data, &bi->BSSID, ETHER_ADDR_LEN);
++		event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_ADDR_LEN);
++
++		/* SSID */
++		iwe.u.data.length = dtoh32(bi->SSID_len);
++		iwe.cmd = SIOCGIWESSID;
++		iwe.u.data.flags = 1;
++		event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, bi->SSID);
++
++		/* Mode */
++		if (dtoh16(bi->capability) & (DOT11_CAP_ESS | DOT11_CAP_IBSS)) {
++			iwe.cmd = SIOCGIWMODE;
++			if (dtoh16(bi->capability) & DOT11_CAP_ESS)
++				iwe.u.mode = IW_MODE_INFRA;
++			else
++				iwe.u.mode = IW_MODE_ADHOC;
++			event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_UINT_LEN);
++		}
++
++		/* Channel */
++		iwe.cmd = SIOCGIWFREQ;
++
++		iwe.u.freq.m = wf_channel2mhz(CHSPEC_CHANNEL(bi->chanspec),
++			(CHSPEC_IS2G(bi->chanspec)) ?
++			WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G);
++		iwe.u.freq.e = 6;
++		event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_FREQ_LEN);
++
++		/* Channel quality */
++		iwe.cmd = IWEVQUAL;
++		iwe.u.qual.qual = rssi_to_qual(dtoh16(bi->RSSI));
++		iwe.u.qual.level = 0x100 + dtoh16(bi->RSSI);
++		iwe.u.qual.noise = 0x100 + bi->phy_noise;
++		event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_QUAL_LEN);
++
++		/* WPA, WPA2, WPS, WAPI IEs */
++		 wl_iw_handle_scanresults_ies(&event, end, info, bi);
++
++		/* Encryption */
++		iwe.cmd = SIOCGIWENCODE;
++		if (dtoh16(bi->capability) & DOT11_CAP_PRIVACY)
++			iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
++		else
++			iwe.u.data.flags = IW_ENCODE_DISABLED;
++		iwe.u.data.length = 0;
++		event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, (char *)event);
++
++		/* Rates */
++		if (bi->rateset.count) {
++			value = event + IW_EV_LCP_LEN;
++			iwe.cmd = SIOCGIWRATE;
++			/* Those two flags are ignored... */
++			iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0;
++			for (j = 0; j < bi->rateset.count && j < IW_MAX_BITRATES; j++) {
++				iwe.u.bitrate.value = (bi->rateset.rates[j] & 0x7f) * 500000;
++				value = IWE_STREAM_ADD_VALUE(info, event, value, end, &iwe,
++					IW_EV_PARAM_LEN);
++			}
++			event = value;
++		}
++	}
++
++	kfree(list);
++
++	dwrq->length = event - extra;
++	dwrq->flags = 0;	/* todo */
++
++	return 0;
++}
++
++static int
++wl_iw_iscan_get_scan(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_scan_results_t *list;
++	struct iw_event	iwe;
++	wl_bss_info_t *bi = NULL;
++	int ii, j;
++	int apcnt;
++	char *event = extra, *end = extra + dwrq->length, *value;
++	iscan_info_t *iscan = g_iscan;
++	iscan_buf_t * p_buf;
++
++	WL_TRACE(("%s: SIOCGIWSCAN\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	/* use backup if our thread is not successful */
++	if ((!iscan) || (iscan->sysioc_pid < 0)) {
++		return wl_iw_get_scan(dev, info, dwrq, extra);
++	}
++
++	/* Check for scan in progress */
++	if (iscan->iscan_state == ISCAN_STATE_SCANING)
++		return -EAGAIN;
++
++	apcnt = 0;
++	p_buf = iscan->list_hdr;
++	/* Get scan results */
++	while (p_buf != iscan->list_cur) {
++	    list = &((wl_iscan_results_t*)p_buf->iscan_buf)->results;
++
++	    if (list->version != WL_BSS_INFO_VERSION) {
++		WL_ERROR(("list->version %d != WL_BSS_INFO_VERSION\n", list->version));
++	    }
++
++	    bi = NULL;
++	    for (ii = 0; ii < list->count && apcnt < IW_MAX_AP; apcnt++, ii++) {
++		bi = bi ? (wl_bss_info_t *)((uintptr)bi + dtoh32(bi->length)) : list->bss_info;
++		ASSERT(((uintptr)bi + dtoh32(bi->length)) <= ((uintptr)list +
++			WLC_IW_ISCAN_MAXLEN));
++
++		/* overflow check cover fields before wpa IEs */
++		if (event + ETHER_ADDR_LEN + bi->SSID_len + IW_EV_UINT_LEN + IW_EV_FREQ_LEN +
++			IW_EV_QUAL_LEN >= end)
++			return -E2BIG;
++		/* First entry must be the BSSID */
++		iwe.cmd = SIOCGIWAP;
++		iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
++		memcpy(iwe.u.ap_addr.sa_data, &bi->BSSID, ETHER_ADDR_LEN);
++		event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_ADDR_LEN);
++
++		/* SSID */
++		iwe.u.data.length = dtoh32(bi->SSID_len);
++		iwe.cmd = SIOCGIWESSID;
++		iwe.u.data.flags = 1;
++		event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, bi->SSID);
++
++		/* Mode */
++		if (dtoh16(bi->capability) & (DOT11_CAP_ESS | DOT11_CAP_IBSS)) {
++			iwe.cmd = SIOCGIWMODE;
++			if (dtoh16(bi->capability) & DOT11_CAP_ESS)
++				iwe.u.mode = IW_MODE_INFRA;
++			else
++				iwe.u.mode = IW_MODE_ADHOC;
++			event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_UINT_LEN);
++		}
++
++		/* Channel */
++		iwe.cmd = SIOCGIWFREQ;
++
++		iwe.u.freq.m = wf_channel2mhz(CHSPEC_CHANNEL(bi->chanspec),
++			(CHSPEC_IS2G(bi->chanspec)) ?
++			WF_CHAN_FACTOR_2_4_G : WF_CHAN_FACTOR_5_G);
++		iwe.u.freq.e = 6;
++		event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_FREQ_LEN);
++
++		/* Channel quality */
++		iwe.cmd = IWEVQUAL;
++		iwe.u.qual.qual = rssi_to_qual(dtoh16(bi->RSSI));
++		iwe.u.qual.level = 0x100 + dtoh16(bi->RSSI);
++		iwe.u.qual.noise = 0x100 + bi->phy_noise;
++		event = IWE_STREAM_ADD_EVENT(info, event, end, &iwe, IW_EV_QUAL_LEN);
++
++		/* WPA, WPA2, WPS, WAPI IEs */
++		wl_iw_handle_scanresults_ies(&event, end, info, bi);
++
++		/* Encryption */
++		iwe.cmd = SIOCGIWENCODE;
++		if (dtoh16(bi->capability) & DOT11_CAP_PRIVACY)
++			iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
++		else
++			iwe.u.data.flags = IW_ENCODE_DISABLED;
++		iwe.u.data.length = 0;
++		event = IWE_STREAM_ADD_POINT(info, event, end, &iwe, (char *)event);
++
++		/* Rates */
++		if (bi->rateset.count <= sizeof(bi->rateset.rates)) {
++			if (event + IW_MAX_BITRATES*IW_EV_PARAM_LEN >= end)
++				return -E2BIG;
++
++			value = event + IW_EV_LCP_LEN;
++			iwe.cmd = SIOCGIWRATE;
++			/* Those two flags are ignored... */
++			iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0;
++			for (j = 0; j < bi->rateset.count && j < IW_MAX_BITRATES; j++) {
++				iwe.u.bitrate.value = (bi->rateset.rates[j] & 0x7f) * 500000;
++				value = IWE_STREAM_ADD_VALUE(info, event, value, end, &iwe,
++					IW_EV_PARAM_LEN);
++			}
++			event = value;
++		}
++	    }
++	    p_buf = p_buf->next;
++	} /* while (p_buf) */
++
++	dwrq->length = event - extra;
++	dwrq->flags = 0;	/* todo */
++
++	return 0;
++}
++
++#endif /* WIRELESS_EXT > 13 */
++
++
++static int
++wl_iw_set_essid(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wlc_ssid_t ssid;
++	int error;
++
++	WL_TRACE(("%s: SIOCSIWESSID\n", dev->name));
++
++	/* default Broadcast SSID */
++	memset(&ssid, 0, sizeof(ssid));
++	if (dwrq->length && extra) {
++#if WIRELESS_EXT > 20
++		ssid.SSID_len = MIN(sizeof(ssid.SSID), dwrq->length);
++#else
++		ssid.SSID_len = MIN(sizeof(ssid.SSID), dwrq->length-1);
++#endif
++		memcpy(ssid.SSID, extra, ssid.SSID_len);
++		ssid.SSID_len = htod32(ssid.SSID_len);
++
++		if ((error = dev_wlc_ioctl(dev, WLC_SET_SSID, &ssid, sizeof(ssid))))
++			return error;
++	}
++	/* If essid null then it is "iwconfig <interface> essid off" command */
++	else {
++		scb_val_t scbval;
++		bzero(&scbval, sizeof(scb_val_t));
++		if ((error = dev_wlc_ioctl(dev, WLC_DISASSOC, &scbval, sizeof(scb_val_t))))
++			return error;
++	}
++	return 0;
++}
++
++static int
++wl_iw_get_essid(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wlc_ssid_t ssid;
++	int error;
++
++	WL_TRACE(("%s: SIOCGIWESSID\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_SSID, &ssid, sizeof(ssid)))) {
++		WL_ERROR(("Error getting the SSID\n"));
++		return error;
++	}
++
++	ssid.SSID_len = dtoh32(ssid.SSID_len);
++
++	/* Get the current SSID */
++	memcpy(extra, ssid.SSID, ssid.SSID_len);
++
++	dwrq->length = ssid.SSID_len;
++
++	dwrq->flags = 1; /* active */
++
++	return 0;
++}
++
++static int
++wl_iw_set_nick(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_iw_t *iw = IW_DEV_IF(dev);
++	WL_TRACE(("%s: SIOCSIWNICKN\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	/* Check the size of the string */
++	if (dwrq->length > sizeof(iw->nickname))
++		return -E2BIG;
++
++	memcpy(iw->nickname, extra, dwrq->length);
++	iw->nickname[dwrq->length - 1] = '\0';
++
++	return 0;
++}
++
++static int
++wl_iw_get_nick(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_iw_t *iw = IW_DEV_IF(dev);
++	WL_TRACE(("%s: SIOCGIWNICKN\n", dev->name));
++
++	if (!extra)
++		return -EINVAL;
++
++	strcpy(extra, iw->nickname);
++	dwrq->length = strlen(extra) + 1;
++
++	return 0;
++}
++
++static int wl_iw_set_rate(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	wl_rateset_t rateset;
++	int error, rate, i, error_bg, error_a;
++
++	WL_TRACE(("%s: SIOCSIWRATE\n", dev->name));
++
++	/* Get current rateset */
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_CURR_RATESET, &rateset, sizeof(rateset))))
++		return error;
++
++	rateset.count = dtoh32(rateset.count);
++
++	if (vwrq->value < 0) {
++		/* Select maximum rate */
++		rate = rateset.rates[rateset.count - 1] & 0x7f;
++	} else if (vwrq->value < rateset.count) {
++		/* Select rate by rateset index */
++		rate = rateset.rates[vwrq->value] & 0x7f;
++	} else {
++		/* Specified rate in bps */
++		rate = vwrq->value / 500000;
++	}
++
++	if (vwrq->fixed) {
++		/*
++			Set rate override,
++			Since the is a/b/g-blind, both a/bg_rate are enforced.
++		*/
++		error_bg = dev_wlc_intvar_set(dev, "bg_rate", rate);
++		error_a = dev_wlc_intvar_set(dev, "a_rate", rate);
++
++		if (error_bg && error_a)
++			return (error_bg | error_a);
++	} else {
++		/*
++			clear rate override
++			Since the is a/b/g-blind, both a/bg_rate are enforced.
++		*/
++		/* 0 is for clearing rate override */
++		error_bg = dev_wlc_intvar_set(dev, "bg_rate", 0);
++		/* 0 is for clearing rate override */
++		error_a = dev_wlc_intvar_set(dev, "a_rate", 0);
++
++		if (error_bg && error_a)
++			return (error_bg | error_a);
++
++		/* Remove rates above selected rate */
++		for (i = 0; i < rateset.count; i++)
++			if ((rateset.rates[i] & 0x7f) > rate)
++				break;
++		rateset.count = htod32(i);
++
++		/* Set current rateset */
++		if ((error = dev_wlc_ioctl(dev, WLC_SET_RATESET, &rateset, sizeof(rateset))))
++			return error;
++	}
++
++	return 0;
++}
++
++static int wl_iw_get_rate(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, rate;
++
++	WL_TRACE(("%s: SIOCGIWRATE\n", dev->name));
++
++	/* Report the current tx rate */
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_RATE, &rate, sizeof(rate))))
++		return error;
++	rate = dtoh32(rate);
++	vwrq->value = rate * 500000;
++
++	return 0;
++}
++
++static int
++wl_iw_set_rts(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, rts;
++
++	WL_TRACE(("%s: SIOCSIWRTS\n", dev->name));
++
++	if (vwrq->disabled)
++		rts = DOT11_DEFAULT_RTS_LEN;
++	else if (vwrq->value < 0 || vwrq->value > DOT11_DEFAULT_RTS_LEN)
++		return -EINVAL;
++	else
++		rts = vwrq->value;
++
++	if ((error = dev_wlc_intvar_set(dev, "rtsthresh", rts)))
++		return error;
++
++	return 0;
++}
++
++static int
++wl_iw_get_rts(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, rts;
++
++	WL_TRACE(("%s: SIOCGIWRTS\n", dev->name));
++
++	if ((error = dev_wlc_intvar_get(dev, "rtsthresh", &rts)))
++		return error;
++
++	vwrq->value = rts;
++	vwrq->disabled = (rts >= DOT11_DEFAULT_RTS_LEN);
++	vwrq->fixed = 1;
++
++	return 0;
++}
++
++static int
++wl_iw_set_frag(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, frag;
++
++	WL_TRACE(("%s: SIOCSIWFRAG\n", dev->name));
++
++	if (vwrq->disabled)
++		frag = DOT11_DEFAULT_FRAG_LEN;
++	else if (vwrq->value < 0 || vwrq->value > DOT11_DEFAULT_FRAG_LEN)
++		return -EINVAL;
++	else
++		frag = vwrq->value;
++
++	if ((error = dev_wlc_intvar_set(dev, "fragthresh", frag)))
++		return error;
++
++	return 0;
++}
++
++static int
++wl_iw_get_frag(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, fragthreshold;
++
++	WL_TRACE(("%s: SIOCGIWFRAG\n", dev->name));
++
++	if ((error = dev_wlc_intvar_get(dev, "fragthresh", &fragthreshold)))
++		return error;
++
++	vwrq->value = fragthreshold;
++	vwrq->disabled = (fragthreshold >= DOT11_DEFAULT_FRAG_LEN);
++	vwrq->fixed = 1;
++
++	return 0;
++}
++
++static int
++wl_iw_set_txpow(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, disable;
++	uint16 txpwrmw;
++	WL_TRACE(("%s: SIOCSIWTXPOW\n", dev->name));
++
++	/* Make sure radio is off or on as far as software is concerned */
++	disable = vwrq->disabled ? WL_RADIO_SW_DISABLE : 0;
++	disable += WL_RADIO_SW_DISABLE << 16;
++
++	disable = htod32(disable);
++	if ((error = dev_wlc_ioctl(dev, WLC_SET_RADIO, &disable, sizeof(disable))))
++		return error;
++
++	/* If Radio is off, nothing more to do */
++	if (disable & WL_RADIO_SW_DISABLE)
++		return 0;
++
++	/* Only handle mW */
++	if (!(vwrq->flags & IW_TXPOW_MWATT))
++		return -EINVAL;
++
++	/* Value < 0 means just "on" or "off" */
++	if (vwrq->value < 0)
++		return 0;
++
++	if (vwrq->value > 0xffff) txpwrmw = 0xffff;
++	else txpwrmw = (uint16)vwrq->value;
++
++
++	error = dev_wlc_intvar_set(dev, "qtxpower", (int)(bcm_mw_to_qdbm(txpwrmw)));
++	return error;
++}
++
++static int
++wl_iw_get_txpow(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, disable, txpwrdbm;
++	uint8 result;
++
++	WL_TRACE(("%s: SIOCGIWTXPOW\n", dev->name));
++
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_RADIO, &disable, sizeof(disable))) ||
++	    (error = dev_wlc_intvar_get(dev, "qtxpower", &txpwrdbm)))
++		return error;
++
++	disable = dtoh32(disable);
++	result = (uint8)(txpwrdbm & ~WL_TXPWR_OVERRIDE);
++	vwrq->value = (int32)bcm_qdbm_to_mw(result);
++	vwrq->fixed = 0;
++	vwrq->disabled = (disable & (WL_RADIO_SW_DISABLE | WL_RADIO_HW_DISABLE)) ? 1 : 0;
++	vwrq->flags = IW_TXPOW_MWATT;
++
++	return 0;
++}
++
++#if WIRELESS_EXT > 10
++static int
++wl_iw_set_retry(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, lrl, srl;
++
++	WL_TRACE(("%s: SIOCSIWRETRY\n", dev->name));
++
++	/* Do not handle "off" or "lifetime" */
++	if (vwrq->disabled || (vwrq->flags & IW_RETRY_LIFETIME))
++		return -EINVAL;
++
++	/* Handle "[min|max] limit" */
++	if (vwrq->flags & IW_RETRY_LIMIT) {
++		/* "max limit" or just "limit" */
++#if WIRELESS_EXT > 20
++		if ((vwrq->flags & IW_RETRY_LONG) ||(vwrq->flags & IW_RETRY_MAX) ||
++			!((vwrq->flags & IW_RETRY_SHORT) || (vwrq->flags & IW_RETRY_MIN))) {
++#else
++		if ((vwrq->flags & IW_RETRY_MAX) || !(vwrq->flags & IW_RETRY_MIN)) {
++#endif /* WIRELESS_EXT > 20 */
++
++			lrl = htod32(vwrq->value);
++			if ((error = dev_wlc_ioctl(dev, WLC_SET_LRL, &lrl, sizeof(lrl))))
++				return error;
++		}
++		/* "min limit" or just "limit" */
++#if WIRELESS_EXT > 20
++		if ((vwrq->flags & IW_RETRY_SHORT) ||(vwrq->flags & IW_RETRY_MIN) ||
++			!((vwrq->flags & IW_RETRY_LONG) || (vwrq->flags & IW_RETRY_MAX))) {
++#else
++		if ((vwrq->flags & IW_RETRY_MIN) || !(vwrq->flags & IW_RETRY_MAX)) {
++#endif /* WIRELESS_EXT > 20 */
++
++			srl = htod32(vwrq->value);
++			if ((error = dev_wlc_ioctl(dev, WLC_SET_SRL, &srl, sizeof(srl))))
++				return error;
++		}
++	}
++
++	return 0;
++}
++
++static int
++wl_iw_get_retry(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, lrl, srl;
++
++	WL_TRACE(("%s: SIOCGIWRETRY\n", dev->name));
++
++	vwrq->disabled = 0;      /* Can't be disabled */
++
++	/* Do not handle lifetime queries */
++	if ((vwrq->flags & IW_RETRY_TYPE) == IW_RETRY_LIFETIME)
++		return -EINVAL;
++
++	/* Get retry limits */
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_LRL, &lrl, sizeof(lrl))) ||
++	    (error = dev_wlc_ioctl(dev, WLC_GET_SRL, &srl, sizeof(srl))))
++		return error;
++
++	lrl = dtoh32(lrl);
++	srl = dtoh32(srl);
++
++	/* Note : by default, display the min retry number */
++	if (vwrq->flags & IW_RETRY_MAX) {
++		vwrq->flags = IW_RETRY_LIMIT | IW_RETRY_MAX;
++		vwrq->value = lrl;
++	} else {
++		vwrq->flags = IW_RETRY_LIMIT;
++		vwrq->value = srl;
++		if (srl != lrl)
++			vwrq->flags |= IW_RETRY_MIN;
++	}
++
++	return 0;
++}
++#endif /* WIRELESS_EXT > 10 */
++
++static int
++wl_iw_set_encode(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_wsec_key_t key;
++	int error, val, wsec;
++
++	WL_TRACE(("%s: SIOCSIWENCODE\n", dev->name));
++
++	memset(&key, 0, sizeof(key));
++
++	if ((dwrq->flags & IW_ENCODE_INDEX) == 0) {
++		/* Find the current key */
++		for (key.index = 0; key.index < DOT11_MAX_DEFAULT_KEYS; key.index++) {
++			val = htod32(key.index);
++			if ((error = dev_wlc_ioctl(dev, WLC_GET_KEY_PRIMARY, &val, sizeof(val))))
++				return error;
++			val = dtoh32(val);
++			if (val)
++				break;
++		}
++		/* Default to 0 */
++		if (key.index == DOT11_MAX_DEFAULT_KEYS)
++			key.index = 0;
++	} else {
++		key.index = (dwrq->flags & IW_ENCODE_INDEX) - 1;
++		if (key.index >= DOT11_MAX_DEFAULT_KEYS)
++			return -EINVAL;
++	}
++
++	/* Interpret "off" to mean no encryption */
++	wsec = (dwrq->flags & IW_ENCODE_DISABLED) ? 0 : WEP_ENABLED;
++
++	if ((error = dev_wlc_intvar_set(dev, "wsec", wsec)))
++		return error;
++
++	/* Old API used to pass a NULL pointer instead of IW_ENCODE_NOKEY */
++	if (!extra || !dwrq->length || (dwrq->flags & IW_ENCODE_NOKEY)) {
++		/* Just select a new current key */
++		val = htod32(key.index);
++		if ((error = dev_wlc_ioctl(dev, WLC_SET_KEY_PRIMARY, &val, sizeof(val))))
++			return error;
++	} else {
++		key.len = dwrq->length;
++
++		if (dwrq->length > sizeof(key.data))
++			return -EINVAL;
++
++		memcpy(key.data, extra, dwrq->length);
++
++		key.flags = WL_PRIMARY_KEY;
++		switch (key.len) {
++		case WEP1_KEY_SIZE:
++			key.algo = CRYPTO_ALGO_WEP1;
++			break;
++		case WEP128_KEY_SIZE:
++			key.algo = CRYPTO_ALGO_WEP128;
++			break;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 14)
++		case TKIP_KEY_SIZE:
++			key.algo = CRYPTO_ALGO_TKIP;
++			break;
++#endif
++		case AES_KEY_SIZE:
++			key.algo = CRYPTO_ALGO_AES_CCM;
++			break;
++		default:
++			return -EINVAL;
++		}
++
++		/* Set the new key/index */
++		swap_key_from_BE(&key);
++		if ((error = dev_wlc_ioctl(dev, WLC_SET_KEY, &key, sizeof(key))))
++			return error;
++	}
++
++	/* Interpret "restricted" to mean shared key authentication */
++	val = (dwrq->flags & IW_ENCODE_RESTRICTED) ? 1 : 0;
++	val = htod32(val);
++	if ((error = dev_wlc_ioctl(dev, WLC_SET_AUTH, &val, sizeof(val))))
++		return error;
++
++	return 0;
++}
++
++static int
++wl_iw_get_encode(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_wsec_key_t key;
++	int error, val, wsec, auth;
++
++	WL_TRACE(("%s: SIOCGIWENCODE\n", dev->name));
++
++	/* assure default values of zero for things we don't touch */
++	bzero(&key, sizeof(wl_wsec_key_t));
++
++	if ((dwrq->flags & IW_ENCODE_INDEX) == 0) {
++		/* Find the current key */
++		for (key.index = 0; key.index < DOT11_MAX_DEFAULT_KEYS; key.index++) {
++			val = key.index;
++			if ((error = dev_wlc_ioctl(dev, WLC_GET_KEY_PRIMARY, &val, sizeof(val))))
++				return error;
++			val = dtoh32(val);
++			if (val)
++				break;
++		}
++	} else
++		key.index = (dwrq->flags & IW_ENCODE_INDEX) - 1;
++
++	if (key.index >= DOT11_MAX_DEFAULT_KEYS)
++		key.index = 0;
++
++	/* Get info */
++
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_WSEC, &wsec, sizeof(wsec))) ||
++	    (error = dev_wlc_ioctl(dev, WLC_GET_AUTH, &auth, sizeof(auth))))
++		return error;
++
++	swap_key_to_BE(&key);
++
++	wsec = dtoh32(wsec);
++	auth = dtoh32(auth);
++	/* Get key length */
++	dwrq->length = MIN(IW_ENCODING_TOKEN_MAX, key.len);
++
++	/* Get flags */
++	dwrq->flags = key.index + 1;
++	if (!(wsec & (WEP_ENABLED | TKIP_ENABLED | AES_ENABLED))) {
++		/* Interpret "off" to mean no encryption */
++		dwrq->flags |= IW_ENCODE_DISABLED;
++	}
++	if (auth) {
++		/* Interpret "restricted" to mean shared key authentication */
++		dwrq->flags |= IW_ENCODE_RESTRICTED;
++	}
++
++	/* Get key */
++	if (dwrq->length && extra)
++		memcpy(extra, key.data, dwrq->length);
++
++	return 0;
++}
++
++static int
++wl_iw_set_power(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, pm;
++
++	WL_TRACE(("%s: SIOCSIWPOWER\n", dev->name));
++
++	pm = vwrq->disabled ? PM_OFF : PM_MAX;
++
++	pm = htod32(pm);
++	if ((error = dev_wlc_ioctl(dev, WLC_SET_PM, &pm, sizeof(pm))))
++		return error;
++
++	return 0;
++}
++
++static int
++wl_iw_get_power(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error, pm;
++
++	WL_TRACE(("%s: SIOCGIWPOWER\n", dev->name));
++
++	if ((error = dev_wlc_ioctl(dev, WLC_GET_PM, &pm, sizeof(pm))))
++		return error;
++
++	pm = dtoh32(pm);
++	vwrq->disabled = pm ? 0 : 1;
++	vwrq->flags = IW_POWER_ALL_R;
++
++	return 0;
++}
++
++#if WIRELESS_EXT > 17
++static int
++wl_iw_set_wpaie(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *iwp,
++	char *extra
++)
++{
++		dev_wlc_bufvar_set(dev, "wpaie", extra, iwp->length);
++
++	return 0;
++}
++
++static int
++wl_iw_get_wpaie(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *iwp,
++	char *extra
++)
++{
++	WL_TRACE(("%s: SIOCGIWGENIE\n", dev->name));
++	iwp->length = 64;
++	dev_wlc_bufvar_get(dev, "wpaie", extra, iwp->length);
++	return 0;
++}
++
++static int
++wl_iw_set_encodeext(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_point *dwrq,
++	char *extra
++)
++{
++	wl_wsec_key_t key;
++	int error;
++	struct iw_encode_ext *iwe;
++
++	WL_TRACE(("%s: SIOCSIWENCODEEXT\n", dev->name));
++
++	memset(&key, 0, sizeof(key));
++	iwe = (struct iw_encode_ext *)extra;
++
++	/* disable encryption completely  */
++	if (dwrq->flags & IW_ENCODE_DISABLED) {
++
++	}
++
++	/* get the key index */
++	key.index = 0;
++	if (dwrq->flags & IW_ENCODE_INDEX)
++		key.index = (dwrq->flags & IW_ENCODE_INDEX) - 1;
++
++	key.len = iwe->key_len;
++
++	/* Instead of bcast for ea address for default wep keys, driver needs it to be Null */
++	if (!ETHER_ISMULTI(iwe->addr.sa_data))
++		bcopy((void *)&iwe->addr.sa_data, (char *)&key.ea, ETHER_ADDR_LEN);
++
++	/* check for key index change */
++	if (key.len == 0) {
++		if (iwe->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) {
++			WL_WSEC(("Changing the the primary Key to %d\n", key.index));
++			/* change the key index .... */
++			key.index = htod32(key.index);
++			error = dev_wlc_ioctl(dev, WLC_SET_KEY_PRIMARY,
++				&key.index, sizeof(key.index));
++			if (error)
++				return error;
++		}
++		/* key delete */
++		else {
++			swap_key_from_BE(&key);
++			error = dev_wlc_ioctl(dev, WLC_SET_KEY, &key, sizeof(key));
++			if (error)
++				return error;
++		}
++	}
++	/* This case is used to allow an external 802.1x supplicant
++	 * to pass the PMK to the in-driver supplicant for use in
++	 * the 4-way handshake.
++	 */
++	else if (iwe->alg == IW_ENCODE_ALG_PMK) {
++		int j;
++		wsec_pmk_t pmk;
++		char keystring[WSEC_MAX_PSK_LEN + 1];
++		char* charptr = keystring;
++		uint len;
++
++		/* copy the raw hex key to the appropriate format */
++		for (j = 0; j < (WSEC_MAX_PSK_LEN / 2); j++) {
++			(void)snprintf(charptr, 3, "%02x", iwe->key[j]);
++			charptr += 2;
++		}
++		len = strlen(keystring);
++		pmk.key_len = htod16(len);
++		bcopy(keystring, pmk.key, len);
++		pmk.flags = htod16(WSEC_PASSPHRASE);
++
++		error = dev_wlc_ioctl(dev, WLC_SET_WSEC_PMK, &pmk, sizeof(pmk));
++		if (error)
++			return error;
++	}
++
++	else {
++		if (iwe->key_len > sizeof(key.data))
++			return -EINVAL;
++
++		WL_WSEC(("Setting the key index %d\n", key.index));
++		if (iwe->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) {
++			WL_WSEC(("key is a Primary Key\n"));
++			key.flags = WL_PRIMARY_KEY;
++		}
++
++		bcopy((void *)iwe->key, key.data, iwe->key_len);
++
++		if (iwe->alg == IW_ENCODE_ALG_TKIP) {
++			uint8 keybuf[8];
++			bcopy(&key.data[24], keybuf, sizeof(keybuf));
++			bcopy(&key.data[16], &key.data[24], sizeof(keybuf));
++			bcopy(keybuf, &key.data[16], sizeof(keybuf));
++		}
++
++		/* rx iv */
++		if (iwe->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) {
++			uchar *ivptr;
++			ivptr = (uchar *)iwe->rx_seq;
++			key.rxiv.hi = (ivptr[5] << 24) | (ivptr[4] << 16) |
++				(ivptr[3] << 8) | ivptr[2];
++			key.rxiv.lo = (ivptr[1] << 8) | ivptr[0];
++			key.iv_initialized = TRUE;
++		}
++
++		switch (iwe->alg) {
++			case IW_ENCODE_ALG_NONE:
++				key.algo = CRYPTO_ALGO_OFF;
++				break;
++			case IW_ENCODE_ALG_WEP:
++				if (iwe->key_len == WEP1_KEY_SIZE)
++					key.algo = CRYPTO_ALGO_WEP1;
++				else
++					key.algo = CRYPTO_ALGO_WEP128;
++				break;
++			case IW_ENCODE_ALG_TKIP:
++				key.algo = CRYPTO_ALGO_TKIP;
++				break;
++			case IW_ENCODE_ALG_CCMP:
++				key.algo = CRYPTO_ALGO_AES_CCM;
++				break;
++			default:
++				break;
++		}
++		swap_key_from_BE(&key);
++
++		dhd_wait_pend8021x(dev);
++
++		error = dev_wlc_ioctl(dev, WLC_SET_KEY, &key, sizeof(key));
++		if (error)
++			return error;
++	}
++	return 0;
++}
++
++
++#if WIRELESS_EXT > 17
++struct {
++	pmkid_list_t pmkids;
++	pmkid_t foo[MAXPMKID-1];
++} pmkid_list;
++static int
++wl_iw_set_pmksa(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	struct iw_pmksa *iwpmksa;
++	uint i;
++	char eabuf[ETHER_ADDR_STR_LEN];
++	pmkid_t * pmkid_array = pmkid_list.pmkids.pmkid;
++
++	WL_TRACE(("%s: SIOCSIWPMKSA\n", dev->name));
++	iwpmksa = (struct iw_pmksa *)extra;
++	bzero((char *)eabuf, ETHER_ADDR_STR_LEN);
++	if (iwpmksa->cmd == IW_PMKSA_FLUSH) {
++		WL_TRACE(("wl_iw_set_pmksa - IW_PMKSA_FLUSH\n"));
++		bzero((char *)&pmkid_list, sizeof(pmkid_list));
++	}
++	if (iwpmksa->cmd == IW_PMKSA_REMOVE) {
++		pmkid_list_t pmkid, *pmkidptr;
++		pmkidptr = &pmkid;
++		bcopy(&iwpmksa->bssid.sa_data[0], &pmkidptr->pmkid[0].BSSID, ETHER_ADDR_LEN);
++		bcopy(&iwpmksa->pmkid[0], &pmkidptr->pmkid[0].PMKID, WPA2_PMKID_LEN);
++		{
++			uint j;
++			WL_TRACE(("wl_iw_set_pmksa,IW_PMKSA_REMOVE - PMKID: %s = ",
++				bcm_ether_ntoa(&pmkidptr->pmkid[0].BSSID,
++				eabuf)));
++			for (j = 0; j < WPA2_PMKID_LEN; j++)
++				WL_TRACE(("%02x ", pmkidptr->pmkid[0].PMKID[j]));
++			WL_TRACE(("\n"));
++		}
++		for (i = 0; i < pmkid_list.pmkids.npmkid; i++)
++			if (!bcmp(&iwpmksa->bssid.sa_data[0], &pmkid_array[i].BSSID,
++				ETHER_ADDR_LEN))
++				break;
++		for (; i < pmkid_list.pmkids.npmkid; i++) {
++			bcopy(&pmkid_array[i+1].BSSID,
++				&pmkid_array[i].BSSID,
++				ETHER_ADDR_LEN);
++			bcopy(&pmkid_array[i+1].PMKID,
++				&pmkid_array[i].PMKID,
++				WPA2_PMKID_LEN);
++		}
++		pmkid_list.pmkids.npmkid--;
++	}
++	if (iwpmksa->cmd == IW_PMKSA_ADD) {
++		bcopy(&iwpmksa->bssid.sa_data[0],
++			&pmkid_array[pmkid_list.pmkids.npmkid].BSSID,
++			ETHER_ADDR_LEN);
++		bcopy(&iwpmksa->pmkid[0], &pmkid_array[pmkid_list.pmkids.npmkid].PMKID,
++			WPA2_PMKID_LEN);
++		{
++			uint j;
++			uint k;
++			k = pmkid_list.pmkids.npmkid;
++			BCM_REFERENCE(k);
++			WL_TRACE(("wl_iw_set_pmksa,IW_PMKSA_ADD - PMKID: %s = ",
++				bcm_ether_ntoa(&pmkid_array[k].BSSID,
++				eabuf)));
++			for (j = 0; j < WPA2_PMKID_LEN; j++)
++				WL_TRACE(("%02x ", pmkid_array[k].PMKID[j]));
++			WL_TRACE(("\n"));
++		}
++		pmkid_list.pmkids.npmkid++;
++	}
++	WL_TRACE(("PRINTING pmkid LIST - No of elements %d\n", pmkid_list.pmkids.npmkid));
++	for (i = 0; i < pmkid_list.pmkids.npmkid; i++) {
++		uint j;
++		WL_TRACE(("PMKID[%d]: %s = ", i,
++			bcm_ether_ntoa(&pmkid_array[i].BSSID,
++			eabuf)));
++		for (j = 0; j < WPA2_PMKID_LEN; j++)
++			WL_TRACE(("%02x ", pmkid_array[i].PMKID[j]));
++		printf("\n");
++	}
++	WL_TRACE(("\n"));
++	dev_wlc_bufvar_set(dev, "pmkid_info", (char *)&pmkid_list, sizeof(pmkid_list));
++	return 0;
++}
++#endif /* WIRELESS_EXT > 17 */
++
++static int
++wl_iw_get_encodeext(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	WL_TRACE(("%s: SIOCGIWENCODEEXT\n", dev->name));
++	return 0;
++}
++
++static int
++wl_iw_set_wpaauth(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error = 0;
++	int paramid;
++	int paramval;
++	uint32 cipher_combined;
++	int val = 0;
++	wl_iw_t *iw = IW_DEV_IF(dev);
++
++	WL_TRACE(("%s: SIOCSIWAUTH\n", dev->name));
++
++	paramid = vwrq->flags & IW_AUTH_INDEX;
++	paramval = vwrq->value;
++
++	WL_TRACE(("%s: SIOCSIWAUTH, paramid = 0x%0x, paramval = 0x%0x\n",
++		dev->name, paramid, paramval));
++
++	switch (paramid) {
++
++	case IW_AUTH_WPA_VERSION:
++		/* supported wpa version disabled or wpa or wpa2 */
++		if (paramval & IW_AUTH_WPA_VERSION_DISABLED)
++			val = WPA_AUTH_DISABLED;
++		else if (paramval & (IW_AUTH_WPA_VERSION_WPA))
++			val = WPA_AUTH_PSK | WPA_AUTH_UNSPECIFIED;
++		else if (paramval & IW_AUTH_WPA_VERSION_WPA2)
++			val = WPA2_AUTH_PSK | WPA2_AUTH_UNSPECIFIED;
++		WL_TRACE(("%s: %d: setting wpa_auth to 0x%0x\n", __FUNCTION__, __LINE__, val));
++		if ((error = dev_wlc_intvar_set(dev, "wpa_auth", val)))
++			return error;
++		break;
++
++	case IW_AUTH_CIPHER_PAIRWISE:
++	case IW_AUTH_CIPHER_GROUP: {
++		int fbt_cap = 0;
++
++		if (paramid == IW_AUTH_CIPHER_PAIRWISE) {
++			iw->pwsec = paramval;
++		}
++		else {
++			iw->gwsec = paramval;
++		}
++
++		if ((error = dev_wlc_intvar_get(dev, "wsec", &val)))
++			return error;
++
++		cipher_combined = iw->gwsec | iw->pwsec;
++		val &= ~(WEP_ENABLED | TKIP_ENABLED | AES_ENABLED);
++		if (cipher_combined & (IW_AUTH_CIPHER_WEP40 | IW_AUTH_CIPHER_WEP104))
++			val |= WEP_ENABLED;
++		if (cipher_combined & IW_AUTH_CIPHER_TKIP)
++			val |= TKIP_ENABLED;
++		if (cipher_combined & IW_AUTH_CIPHER_CCMP)
++			val |= AES_ENABLED;
++
++		if (iw->privacy_invoked && !val) {
++			WL_WSEC(("%s: %s: 'Privacy invoked' TRUE but clearing wsec, assuming "
++			         "we're a WPS enrollee\n", dev->name, __FUNCTION__));
++			if ((error = dev_wlc_intvar_set(dev, "is_WPS_enrollee", TRUE))) {
++				WL_WSEC(("Failed to set iovar is_WPS_enrollee\n"));
++				return error;
++			}
++		} else if (val) {
++			if ((error = dev_wlc_intvar_set(dev, "is_WPS_enrollee", FALSE))) {
++				WL_WSEC(("Failed to clear iovar is_WPS_enrollee\n"));
++				return error;
++			}
++		}
++
++		if ((error = dev_wlc_intvar_set(dev, "wsec", val)))
++			return error;
++
++		/* Ensure in-dongle supplicant is turned on when FBT wants to do the 4-way
++		 * handshake.
++		 */
++		if (dev_wlc_intvar_get(dev, "fbt_cap", &fbt_cap) == 0) {
++			if (fbt_cap == WLC_FBT_CAP_DRV_4WAY_AND_REASSOC) {
++				if ((paramid == IW_AUTH_CIPHER_PAIRWISE) && (val & AES_ENABLED)) {
++					if ((error = dev_wlc_intvar_set(dev, "sup_wpa", 1)))
++						return error;
++				}
++				else if (val == 0) {
++					if ((error = dev_wlc_intvar_set(dev, "sup_wpa", 0)))
++						return error;
++				}
++			}
++		}
++		break;
++	}
++
++	case IW_AUTH_KEY_MGMT:
++		if ((error = dev_wlc_intvar_get(dev, "wpa_auth", &val)))
++			return error;
++
++		if (val & (WPA_AUTH_PSK | WPA_AUTH_UNSPECIFIED)) {
++			if (paramval & (IW_AUTH_KEY_MGMT_FT_PSK | IW_AUTH_KEY_MGMT_PSK))
++				val = WPA_AUTH_PSK;
++			else
++				val = WPA_AUTH_UNSPECIFIED;
++			if (paramval & (IW_AUTH_KEY_MGMT_FT_802_1X | IW_AUTH_KEY_MGMT_FT_PSK))
++				val |= WPA2_AUTH_FT;
++		}
++		else if (val & (WPA2_AUTH_PSK | WPA2_AUTH_UNSPECIFIED)) {
++			if (paramval & (IW_AUTH_KEY_MGMT_FT_PSK | IW_AUTH_KEY_MGMT_PSK))
++				val = WPA2_AUTH_PSK;
++			else
++				val = WPA2_AUTH_UNSPECIFIED;
++			if (paramval & (IW_AUTH_KEY_MGMT_FT_802_1X | IW_AUTH_KEY_MGMT_FT_PSK))
++				val |= WPA2_AUTH_FT;
++		}
++		WL_TRACE(("%s: %d: setting wpa_auth to %d\n", __FUNCTION__, __LINE__, val));
++		if ((error = dev_wlc_intvar_set(dev, "wpa_auth", val)))
++			return error;
++		break;
++
++	case IW_AUTH_TKIP_COUNTERMEASURES:
++		dev_wlc_bufvar_set(dev, "tkip_countermeasures", (char *)&paramval, 1);
++		break;
++
++	case IW_AUTH_80211_AUTH_ALG:
++		/* open shared */
++		WL_ERROR(("Setting the D11auth %d\n", paramval));
++		if (paramval & IW_AUTH_ALG_OPEN_SYSTEM)
++			val = 0;
++		else if (paramval & IW_AUTH_ALG_SHARED_KEY)
++			val = 1;
++		else
++			error = 1;
++		if (!error && (error = dev_wlc_intvar_set(dev, "auth", val)))
++			return error;
++		break;
++
++	case IW_AUTH_WPA_ENABLED:
++		if (paramval == 0) {
++			val = 0;
++			WL_TRACE(("%s: %d: setting wpa_auth to %d\n", __FUNCTION__, __LINE__, val));
++			error = dev_wlc_intvar_set(dev, "wpa_auth", val);
++			return error;
++		}
++		else {
++			/* If WPA is enabled, wpa_auth is set elsewhere */
++		}
++		break;
++
++	case IW_AUTH_DROP_UNENCRYPTED:
++		dev_wlc_bufvar_set(dev, "wsec_restrict", (char *)&paramval, 1);
++		break;
++
++	case IW_AUTH_RX_UNENCRYPTED_EAPOL:
++		dev_wlc_bufvar_set(dev, "rx_unencrypted_eapol", (char *)&paramval, 1);
++		break;
++
++#if WIRELESS_EXT > 17
++
++	case IW_AUTH_ROAMING_CONTROL:
++		WL_TRACE(("%s: IW_AUTH_ROAMING_CONTROL\n", __FUNCTION__));
++		/* driver control or user space app control */
++		break;
++
++	case IW_AUTH_PRIVACY_INVOKED: {
++		int wsec;
++
++		if (paramval == 0) {
++			iw->privacy_invoked = FALSE;
++			if ((error = dev_wlc_intvar_set(dev, "is_WPS_enrollee", FALSE))) {
++				WL_WSEC(("Failed to clear iovar is_WPS_enrollee\n"));
++				return error;
++			}
++		} else {
++			iw->privacy_invoked = TRUE;
++			if ((error = dev_wlc_intvar_get(dev, "wsec", &wsec)))
++				return error;
++
++			if (!WSEC_ENABLED(wsec)) {
++				/* if privacy is true, but wsec is false, we are a WPS enrollee */
++				if ((error = dev_wlc_intvar_set(dev, "is_WPS_enrollee", TRUE))) {
++					WL_WSEC(("Failed to set iovar is_WPS_enrollee\n"));
++					return error;
++				}
++			} else {
++				if ((error = dev_wlc_intvar_set(dev, "is_WPS_enrollee", FALSE))) {
++					WL_WSEC(("Failed to clear iovar is_WPS_enrollee\n"));
++					return error;
++				}
++			}
++		}
++		break;
++	}
++
++
++#endif /* WIRELESS_EXT > 17 */
++
++
++	default:
++		break;
++	}
++	return 0;
++}
++#define VAL_PSK(_val) (((_val) & WPA_AUTH_PSK) || ((_val) & WPA2_AUTH_PSK))
++
++static int
++wl_iw_get_wpaauth(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	struct iw_param *vwrq,
++	char *extra
++)
++{
++	int error;
++	int paramid;
++	int paramval = 0;
++	int val;
++	wl_iw_t *iw = IW_DEV_IF(dev);
++
++	WL_TRACE(("%s: SIOCGIWAUTH\n", dev->name));
++
++	paramid = vwrq->flags & IW_AUTH_INDEX;
++
++	switch (paramid) {
++	case IW_AUTH_WPA_VERSION:
++		/* supported wpa version disabled or wpa or wpa2 */
++		if ((error = dev_wlc_intvar_get(dev, "wpa_auth", &val)))
++			return error;
++		if (val & (WPA_AUTH_NONE | WPA_AUTH_DISABLED))
++			paramval = IW_AUTH_WPA_VERSION_DISABLED;
++		else if (val & (WPA_AUTH_PSK | WPA_AUTH_UNSPECIFIED))
++			paramval = IW_AUTH_WPA_VERSION_WPA;
++		else if (val & (WPA2_AUTH_PSK | WPA2_AUTH_UNSPECIFIED))
++			paramval = IW_AUTH_WPA_VERSION_WPA2;
++		break;
++
++	case IW_AUTH_CIPHER_PAIRWISE:
++		paramval = iw->pwsec;
++		break;
++
++	case IW_AUTH_CIPHER_GROUP:
++		paramval = iw->gwsec;
++		break;
++
++	case IW_AUTH_KEY_MGMT:
++		/* psk, 1x */
++		if ((error = dev_wlc_intvar_get(dev, "wpa_auth", &val)))
++			return error;
++		if (VAL_PSK(val))
++			paramval = IW_AUTH_KEY_MGMT_PSK;
++		else
++			paramval = IW_AUTH_KEY_MGMT_802_1X;
++
++		break;
++	case IW_AUTH_TKIP_COUNTERMEASURES:
++		dev_wlc_bufvar_get(dev, "tkip_countermeasures", (char *)&paramval, 1);
++		break;
++
++	case IW_AUTH_DROP_UNENCRYPTED:
++		dev_wlc_bufvar_get(dev, "wsec_restrict", (char *)&paramval, 1);
++		break;
++
++	case IW_AUTH_RX_UNENCRYPTED_EAPOL:
++		dev_wlc_bufvar_get(dev, "rx_unencrypted_eapol", (char *)&paramval, 1);
++		break;
++
++	case IW_AUTH_80211_AUTH_ALG:
++		/* open, shared, leap */
++		if ((error = dev_wlc_intvar_get(dev, "auth", &val)))
++			return error;
++		if (!val)
++			paramval = IW_AUTH_ALG_OPEN_SYSTEM;
++		else
++			paramval = IW_AUTH_ALG_SHARED_KEY;
++		break;
++	case IW_AUTH_WPA_ENABLED:
++		if ((error = dev_wlc_intvar_get(dev, "wpa_auth", &val)))
++			return error;
++		if (val)
++			paramval = TRUE;
++		else
++			paramval = FALSE;
++		break;
++
++#if WIRELESS_EXT > 17
++
++	case IW_AUTH_ROAMING_CONTROL:
++		WL_ERROR(("%s: IW_AUTH_ROAMING_CONTROL\n", __FUNCTION__));
++		/* driver control or user space app control */
++		break;
++
++	case IW_AUTH_PRIVACY_INVOKED:
++		paramval = iw->privacy_invoked;
++		break;
++
++#endif /* WIRELESS_EXT > 17 */
++	}
++	vwrq->value = paramval;
++	return 0;
++}
++#endif /* WIRELESS_EXT > 17 */
++
++static const iw_handler wl_iw_handler[] =
++{
++	(iw_handler) wl_iw_config_commit,	/* SIOCSIWCOMMIT */
++	(iw_handler) wl_iw_get_name,		/* SIOCGIWNAME */
++	(iw_handler) NULL,			/* SIOCSIWNWID */
++	(iw_handler) NULL,			/* SIOCGIWNWID */
++	(iw_handler) wl_iw_set_freq,		/* SIOCSIWFREQ */
++	(iw_handler) wl_iw_get_freq,		/* SIOCGIWFREQ */
++	(iw_handler) wl_iw_set_mode,		/* SIOCSIWMODE */
++	(iw_handler) wl_iw_get_mode,		/* SIOCGIWMODE */
++	(iw_handler) NULL,			/* SIOCSIWSENS */
++	(iw_handler) NULL,			/* SIOCGIWSENS */
++	(iw_handler) NULL,			/* SIOCSIWRANGE */
++	(iw_handler) wl_iw_get_range,		/* SIOCGIWRANGE */
++	(iw_handler) NULL,			/* SIOCSIWPRIV */
++	(iw_handler) NULL,			/* SIOCGIWPRIV */
++	(iw_handler) NULL,			/* SIOCSIWSTATS */
++	(iw_handler) NULL,			/* SIOCGIWSTATS */
++	(iw_handler) wl_iw_set_spy,		/* SIOCSIWSPY */
++	(iw_handler) wl_iw_get_spy,		/* SIOCGIWSPY */
++	(iw_handler) NULL,			/* -- hole -- */
++	(iw_handler) NULL,			/* -- hole -- */
++	(iw_handler) wl_iw_set_wap,		/* SIOCSIWAP */
++	(iw_handler) wl_iw_get_wap,		/* SIOCGIWAP */
++#if WIRELESS_EXT > 17
++	(iw_handler) wl_iw_mlme,		/* SIOCSIWMLME */
++#else
++	(iw_handler) NULL,			/* -- hole -- */
++#endif
++	(iw_handler) wl_iw_iscan_get_aplist,	/* SIOCGIWAPLIST */
++#if WIRELESS_EXT > 13
++	(iw_handler) wl_iw_iscan_set_scan,	/* SIOCSIWSCAN */
++	(iw_handler) wl_iw_iscan_get_scan,	/* SIOCGIWSCAN */
++#else	/* WIRELESS_EXT > 13 */
++	(iw_handler) NULL,			/* SIOCSIWSCAN */
++	(iw_handler) NULL,			/* SIOCGIWSCAN */
++#endif	/* WIRELESS_EXT > 13 */
++	(iw_handler) wl_iw_set_essid,		/* SIOCSIWESSID */
++	(iw_handler) wl_iw_get_essid,		/* SIOCGIWESSID */
++	(iw_handler) wl_iw_set_nick,		/* SIOCSIWNICKN */
++	(iw_handler) wl_iw_get_nick,		/* SIOCGIWNICKN */
++	(iw_handler) NULL,			/* -- hole -- */
++	(iw_handler) NULL,			/* -- hole -- */
++	(iw_handler) wl_iw_set_rate,		/* SIOCSIWRATE */
++	(iw_handler) wl_iw_get_rate,		/* SIOCGIWRATE */
++	(iw_handler) wl_iw_set_rts,		/* SIOCSIWRTS */
++	(iw_handler) wl_iw_get_rts,		/* SIOCGIWRTS */
++	(iw_handler) wl_iw_set_frag,		/* SIOCSIWFRAG */
++	(iw_handler) wl_iw_get_frag,		/* SIOCGIWFRAG */
++	(iw_handler) wl_iw_set_txpow,		/* SIOCSIWTXPOW */
++	(iw_handler) wl_iw_get_txpow,		/* SIOCGIWTXPOW */
++#if WIRELESS_EXT > 10
++	(iw_handler) wl_iw_set_retry,		/* SIOCSIWRETRY */
++	(iw_handler) wl_iw_get_retry,		/* SIOCGIWRETRY */
++#endif /* WIRELESS_EXT > 10 */
++	(iw_handler) wl_iw_set_encode,		/* SIOCSIWENCODE */
++	(iw_handler) wl_iw_get_encode,		/* SIOCGIWENCODE */
++	(iw_handler) wl_iw_set_power,		/* SIOCSIWPOWER */
++	(iw_handler) wl_iw_get_power,		/* SIOCGIWPOWER */
++#if WIRELESS_EXT > 17
++	(iw_handler) NULL,			/* -- hole -- */
++	(iw_handler) NULL,			/* -- hole -- */
++	(iw_handler) wl_iw_set_wpaie,		/* SIOCSIWGENIE */
++	(iw_handler) wl_iw_get_wpaie,		/* SIOCGIWGENIE */
++	(iw_handler) wl_iw_set_wpaauth,		/* SIOCSIWAUTH */
++	(iw_handler) wl_iw_get_wpaauth,		/* SIOCGIWAUTH */
++	(iw_handler) wl_iw_set_encodeext,	/* SIOCSIWENCODEEXT */
++	(iw_handler) wl_iw_get_encodeext,	/* SIOCGIWENCODEEXT */
++	(iw_handler) wl_iw_set_pmksa,		/* SIOCSIWPMKSA */
++#endif /* WIRELESS_EXT > 17 */
++};
++
++#if WIRELESS_EXT > 12
++enum {
++	WL_IW_SET_LEDDC = SIOCIWFIRSTPRIV,
++	WL_IW_SET_VLANMODE,
++	WL_IW_SET_PM,
++#if WIRELESS_EXT > 17
++#endif /* WIRELESS_EXT > 17 */
++	WL_IW_SET_LAST
++};
++
++static iw_handler wl_iw_priv_handler[] = {
++	wl_iw_set_leddc,
++	wl_iw_set_vlanmode,
++	wl_iw_set_pm,
++#if WIRELESS_EXT > 17
++#endif /* WIRELESS_EXT > 17 */
++	NULL
++};
++
++static struct iw_priv_args wl_iw_priv_args[] = {
++	{
++		WL_IW_SET_LEDDC,
++		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++		0,
++		"set_leddc"
++	},
++	{
++		WL_IW_SET_VLANMODE,
++		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++		0,
++		"set_vlanmode"
++	},
++	{
++		WL_IW_SET_PM,
++		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++		0,
++		"set_pm"
++	},
++#if WIRELESS_EXT > 17
++#endif /* WIRELESS_EXT > 17 */
++	{ 0, 0, 0, { 0 } }
++};
++
++const struct iw_handler_def wl_iw_handler_def =
++{
++	.num_standard = ARRAYSIZE(wl_iw_handler),
++	.num_private = ARRAY_SIZE(wl_iw_priv_handler),
++	.num_private_args = ARRAY_SIZE(wl_iw_priv_args),
++	.standard = (const iw_handler *) wl_iw_handler,
++	.private = wl_iw_priv_handler,
++	.private_args = wl_iw_priv_args,
++#if WIRELESS_EXT >= 19
++	get_wireless_stats: dhd_get_wireless_stats,
++#endif /* WIRELESS_EXT >= 19 */
++	};
++#endif /* WIRELESS_EXT > 12 */
++
++int
++wl_iw_ioctl(
++	struct net_device *dev,
++	struct ifreq *rq,
++	int cmd
++)
++{
++	struct iwreq *wrq = (struct iwreq *) rq;
++	struct iw_request_info info;
++	iw_handler handler;
++	char *extra = NULL;
++	size_t token_size = 1;
++	int max_tokens = 0, ret = 0;
++
++	if (cmd < SIOCIWFIRST ||
++		IW_IOCTL_IDX(cmd) >= ARRAYSIZE(wl_iw_handler) ||
++		!(handler = wl_iw_handler[IW_IOCTL_IDX(cmd)]))
++		return -EOPNOTSUPP;
++
++	switch (cmd) {
++
++	case SIOCSIWESSID:
++	case SIOCGIWESSID:
++	case SIOCSIWNICKN:
++	case SIOCGIWNICKN:
++		max_tokens = IW_ESSID_MAX_SIZE + 1;
++		break;
++
++	case SIOCSIWENCODE:
++	case SIOCGIWENCODE:
++#if WIRELESS_EXT > 17
++	case SIOCSIWENCODEEXT:
++	case SIOCGIWENCODEEXT:
++#endif
++		max_tokens = IW_ENCODING_TOKEN_MAX;
++		break;
++
++	case SIOCGIWRANGE:
++		max_tokens = sizeof(struct iw_range);
++		break;
++
++	case SIOCGIWAPLIST:
++		token_size = sizeof(struct sockaddr) + sizeof(struct iw_quality);
++		max_tokens = IW_MAX_AP;
++		break;
++
++#if WIRELESS_EXT > 13
++	case SIOCGIWSCAN:
++		if (g_iscan)
++			max_tokens = wrq->u.data.length;
++		else
++		max_tokens = IW_SCAN_MAX_DATA;
++		break;
++#endif /* WIRELESS_EXT > 13 */
++
++	case SIOCSIWSPY:
++		token_size = sizeof(struct sockaddr);
++		max_tokens = IW_MAX_SPY;
++		break;
++
++	case SIOCGIWSPY:
++		token_size = sizeof(struct sockaddr) + sizeof(struct iw_quality);
++		max_tokens = IW_MAX_SPY;
++		break;
++	default:
++		break;
++	}
++
++	if (max_tokens && wrq->u.data.pointer) {
++		if (wrq->u.data.length > max_tokens)
++			return -E2BIG;
++
++		if (!(extra = kmalloc(max_tokens * token_size, GFP_KERNEL)))
++			return -ENOMEM;
++
++		if (copy_from_user(extra, wrq->u.data.pointer, wrq->u.data.length * token_size)) {
++			kfree(extra);
++			return -EFAULT;
++		}
++	}
++
++	info.cmd = cmd;
++	info.flags = 0;
++
++	ret = handler(dev, &info, &wrq->u, extra);
++
++	if (extra) {
++		if (copy_to_user(wrq->u.data.pointer, extra, wrq->u.data.length * token_size)) {
++			kfree(extra);
++			return -EFAULT;
++		}
++
++		kfree(extra);
++	}
++
++	return ret;
++}
++
++/* Convert a connection status event into a connection status string.
++ * Returns TRUE if a matching connection status string was found.
++ */
++bool
++wl_iw_conn_status_str(uint32 event_type, uint32 status, uint32 reason,
++	char* stringBuf, uint buflen)
++{
++	typedef struct conn_fail_event_map_t {
++		uint32 inEvent;			/* input: event type to match */
++		uint32 inStatus;		/* input: event status code to match */
++		uint32 inReason;		/* input: event reason code to match */
++		const char* outName;	/* output: failure type */
++		const char* outCause;	/* output: failure cause */
++	} conn_fail_event_map_t;
++
++	/* Map of WLC_E events to connection failure strings */
++#	define WL_IW_DONT_CARE	9999
++	const conn_fail_event_map_t event_map [] = {
++		/* inEvent           inStatus                inReason         */
++		/* outName outCause                                           */
++		{WLC_E_SET_SSID,     WLC_E_STATUS_SUCCESS,   WL_IW_DONT_CARE,
++		"Conn", "Success"},
++		{WLC_E_SET_SSID,     WLC_E_STATUS_NO_NETWORKS, WL_IW_DONT_CARE,
++		"Conn", "NoNetworks"},
++		{WLC_E_SET_SSID,     WLC_E_STATUS_FAIL,      WL_IW_DONT_CARE,
++		"Conn", "ConfigMismatch"},
++		{WLC_E_PRUNE,        WL_IW_DONT_CARE,        WLC_E_PRUNE_ENCR_MISMATCH,
++		"Conn", "EncrypMismatch"},
++		{WLC_E_PRUNE,        WL_IW_DONT_CARE,        WLC_E_RSN_MISMATCH,
++		"Conn", "RsnMismatch"},
++		{WLC_E_AUTH,         WLC_E_STATUS_TIMEOUT,   WL_IW_DONT_CARE,
++		"Conn", "AuthTimeout"},
++		{WLC_E_AUTH,         WLC_E_STATUS_FAIL,      WL_IW_DONT_CARE,
++		"Conn", "AuthFail"},
++		{WLC_E_AUTH,         WLC_E_STATUS_NO_ACK,    WL_IW_DONT_CARE,
++		"Conn", "AuthNoAck"},
++		{WLC_E_REASSOC,      WLC_E_STATUS_FAIL,      WL_IW_DONT_CARE,
++		"Conn", "ReassocFail"},
++		{WLC_E_REASSOC,      WLC_E_STATUS_TIMEOUT,   WL_IW_DONT_CARE,
++		"Conn", "ReassocTimeout"},
++		{WLC_E_REASSOC,      WLC_E_STATUS_ABORT,     WL_IW_DONT_CARE,
++		"Conn", "ReassocAbort"},
++		{WLC_E_PSK_SUP,      WLC_SUP_KEYED,          WL_IW_DONT_CARE,
++		"Sup", "ConnSuccess"},
++		{WLC_E_PSK_SUP,      WL_IW_DONT_CARE,        WL_IW_DONT_CARE,
++		"Sup", "WpaHandshakeFail"},
++		{WLC_E_DEAUTH_IND,   WL_IW_DONT_CARE,        WL_IW_DONT_CARE,
++		"Conn", "Deauth"},
++		{WLC_E_DISASSOC_IND, WL_IW_DONT_CARE,        WL_IW_DONT_CARE,
++		"Conn", "DisassocInd"},
++		{WLC_E_DISASSOC,     WL_IW_DONT_CARE,        WL_IW_DONT_CARE,
++		"Conn", "Disassoc"}
++	};
++
++	const char* name = "";
++	const char* cause = NULL;
++	int i;
++
++	/* Search the event map table for a matching event */
++	for (i = 0;  i < sizeof(event_map)/sizeof(event_map[0]);  i++) {
++		const conn_fail_event_map_t* row = &event_map[i];
++		if (row->inEvent == event_type &&
++		    (row->inStatus == status || row->inStatus == WL_IW_DONT_CARE) &&
++		    (row->inReason == reason || row->inReason == WL_IW_DONT_CARE)) {
++			name = row->outName;
++			cause = row->outCause;
++			break;
++		}
++	}
++
++	/* If found, generate a connection failure string and return TRUE */
++	if (cause) {
++		memset(stringBuf, 0, buflen);
++		(void)snprintf(stringBuf, buflen, "%s %s %02d %02d", name, cause, status, reason);
++		WL_TRACE(("Connection status: %s\n", stringBuf));
++		return TRUE;
++	} else {
++		return FALSE;
++	}
++}
++
++#if (WIRELESS_EXT > 14)
++/* Check if we have received an event that indicates connection failure
++ * If so, generate a connection failure report string.
++ * The caller supplies a buffer to hold the generated string.
++ */
++static bool
++wl_iw_check_conn_fail(wl_event_msg_t *e, char* stringBuf, uint buflen)
++{
++	uint32 event = ntoh32(e->event_type);
++	uint32 status =  ntoh32(e->status);
++	uint32 reason =  ntoh32(e->reason);
++
++	if (wl_iw_conn_status_str(event, status, reason, stringBuf, buflen)) {
++		return TRUE;
++	} else
++	{
++		return FALSE;
++	}
++}
++#endif /* WIRELESS_EXT > 14 */
++
++#ifndef IW_CUSTOM_MAX
++#define IW_CUSTOM_MAX 256 /* size of extra buffer used for translation of events */
++#endif /* IW_CUSTOM_MAX */
++
++void
++wl_iw_event(struct net_device *dev, wl_event_msg_t *e, void* data)
++{
++#if WIRELESS_EXT > 13
++	union iwreq_data wrqu;
++	char extra[IW_CUSTOM_MAX + 1];
++	int cmd = 0;
++	uint32 event_type = ntoh32(e->event_type);
++	uint16 flags =  ntoh16(e->flags);
++	uint32 datalen = ntoh32(e->datalen);
++	uint32 status =  ntoh32(e->status);
++
++	memset(&wrqu, 0, sizeof(wrqu));
++	memset(extra, 0, sizeof(extra));
++
++	memcpy(wrqu.addr.sa_data, &e->addr, ETHER_ADDR_LEN);
++	wrqu.addr.sa_family = ARPHRD_ETHER;
++
++	switch (event_type) {
++	case WLC_E_TXFAIL:
++		cmd = IWEVTXDROP;
++		break;
++#if WIRELESS_EXT > 14
++	case WLC_E_JOIN:
++	case WLC_E_ASSOC_IND:
++	case WLC_E_REASSOC_IND:
++		cmd = IWEVREGISTERED;
++		break;
++	case WLC_E_DEAUTH_IND:
++	case WLC_E_DISASSOC_IND:
++		cmd = SIOCGIWAP;
++		wrqu.data.length = strlen(extra);
++		bzero(wrqu.addr.sa_data, ETHER_ADDR_LEN);
++		bzero(&extra, ETHER_ADDR_LEN);
++		break;
++
++	case WLC_E_LINK:
++		cmd = SIOCGIWAP;
++		wrqu.data.length = strlen(extra);
++		if (!(flags & WLC_EVENT_MSG_LINK)) {
++			bzero(wrqu.addr.sa_data, ETHER_ADDR_LEN);
++			bzero(&extra, ETHER_ADDR_LEN);
++		}
++		break;
++	case WLC_E_ACTION_FRAME:
++		cmd = IWEVCUSTOM;
++		if (datalen + 1 <= sizeof(extra)) {
++			wrqu.data.length = datalen + 1;
++			extra[0] = WLC_E_ACTION_FRAME;
++			memcpy(&extra[1], data, datalen);
++			WL_TRACE(("WLC_E_ACTION_FRAME len %d \n", wrqu.data.length));
++		}
++		break;
++
++	case WLC_E_ACTION_FRAME_COMPLETE:
++		cmd = IWEVCUSTOM;
++		if (sizeof(status) + 1 <= sizeof(extra)) {
++			wrqu.data.length = sizeof(status) + 1;
++			extra[0] = WLC_E_ACTION_FRAME_COMPLETE;
++			memcpy(&extra[1], &status, sizeof(status));
++			WL_TRACE(("wl_iw_event status %d  \n", status));
++		}
++		break;
++#endif /* WIRELESS_EXT > 14 */
++#if WIRELESS_EXT > 17
++	case WLC_E_MIC_ERROR: {
++		struct	iw_michaelmicfailure  *micerrevt = (struct  iw_michaelmicfailure  *)&extra;
++		cmd = IWEVMICHAELMICFAILURE;
++		wrqu.data.length = sizeof(struct iw_michaelmicfailure);
++		if (flags & WLC_EVENT_MSG_GROUP)
++			micerrevt->flags |= IW_MICFAILURE_GROUP;
++		else
++			micerrevt->flags |= IW_MICFAILURE_PAIRWISE;
++		memcpy(micerrevt->src_addr.sa_data, &e->addr, ETHER_ADDR_LEN);
++		micerrevt->src_addr.sa_family = ARPHRD_ETHER;
++
++		break;
++	}
++
++	case WLC_E_ASSOC_REQ_IE:
++		cmd = IWEVASSOCREQIE;
++		wrqu.data.length = datalen;
++		if (datalen < sizeof(extra))
++			memcpy(extra, data, datalen);
++		break;
++
++	case WLC_E_ASSOC_RESP_IE:
++		cmd = IWEVASSOCRESPIE;
++		wrqu.data.length = datalen;
++		if (datalen < sizeof(extra))
++			memcpy(extra, data, datalen);
++		break;
++
++	case WLC_E_PMKID_CACHE: {
++		struct iw_pmkid_cand *iwpmkidcand = (struct iw_pmkid_cand *)&extra;
++		pmkid_cand_list_t *pmkcandlist;
++		pmkid_cand_t	*pmkidcand;
++		int count;
++
++		if (data == NULL)
++			break;
++
++		cmd = IWEVPMKIDCAND;
++		pmkcandlist = data;
++		count = ntoh32_ua((uint8 *)&pmkcandlist->npmkid_cand);
++		wrqu.data.length = sizeof(struct iw_pmkid_cand);
++		pmkidcand = pmkcandlist->pmkid_cand;
++		while (count) {
++			bzero(iwpmkidcand, sizeof(struct iw_pmkid_cand));
++			if (pmkidcand->preauth)
++				iwpmkidcand->flags |= IW_PMKID_CAND_PREAUTH;
++			bcopy(&pmkidcand->BSSID, &iwpmkidcand->bssid.sa_data,
++			      ETHER_ADDR_LEN);
++			wireless_send_event(dev, cmd, &wrqu, extra);
++			pmkidcand++;
++			count--;
++		}
++		break;
++	}
++#endif /* WIRELESS_EXT > 17 */
++
++	case WLC_E_SCAN_COMPLETE:
++#if WIRELESS_EXT > 14
++		cmd = SIOCGIWSCAN;
++#endif
++		WL_TRACE(("event WLC_E_SCAN_COMPLETE\n"));
++		if ((g_iscan) && (g_iscan->sysioc_pid >= 0) &&
++			(g_iscan->iscan_state != ISCAN_STATE_IDLE))
++			up(&g_iscan->sysioc_sem);
++		break;
++
++	default:
++		/* Cannot translate event */
++		break;
++	}
++
++	if (cmd) {
++		if (cmd == SIOCGIWSCAN)
++			wireless_send_event(dev, cmd, &wrqu, NULL);
++		else
++			wireless_send_event(dev, cmd, &wrqu, extra);
++	}
++
++#if WIRELESS_EXT > 14
++	/* Look for WLC events that indicate a connection failure.
++	 * If found, generate an IWEVCUSTOM event.
++	 */
++	memset(extra, 0, sizeof(extra));
++	if (wl_iw_check_conn_fail(e, extra, sizeof(extra))) {
++		cmd = IWEVCUSTOM;
++		wrqu.data.length = strlen(extra);
++		wireless_send_event(dev, cmd, &wrqu, extra);
++	}
++#endif /* WIRELESS_EXT > 14 */
++
++#endif /* WIRELESS_EXT > 13 */
++}
++
++static int wl_iw_get_wireless_stats_cbfn(void *ctx, uint8 *data, uint16 type, uint16 len)
++{
++	struct iw_statistics *wstats = ctx;
++	int res = BCME_OK;
++
++	switch (type) {
++		case WL_CNT_XTLV_WLC: {
++			wl_cnt_wlc_t *cnt = (wl_cnt_wlc_t *)data;
++			if (len > sizeof(wl_cnt_wlc_t)) {
++				printf("counter structure length invalid! %d > %d\n",
++					len, (int)sizeof(wl_cnt_wlc_t));
++			}
++			wstats->discard.nwid = 0;
++			wstats->discard.code = dtoh32(cnt->rxundec);
++			wstats->discard.fragment = dtoh32(cnt->rxfragerr);
++			wstats->discard.retries = dtoh32(cnt->txfail);
++			wstats->discard.misc = dtoh32(cnt->rxrunt) + dtoh32(cnt->rxgiant);
++			wstats->miss.beacon = 0;
++			WL_TRACE(("wl_iw_get_wireless_stats counters txframe=%d txbyte=%d\n",
++				dtoh32(cnt->txframe), dtoh32(cnt->txbyte)));
++			WL_TRACE(("wl_iw_get_wireless_stats counters rxundec=%d\n",
++				dtoh32(cnt->rxundec)));
++			WL_TRACE(("wl_iw_get_wireless_stats counters txfail=%d\n",
++				dtoh32(cnt->txfail)));
++			WL_TRACE(("wl_iw_get_wireless_stats counters rxfragerr=%d\n",
++				dtoh32(cnt->rxfragerr)));
++			WL_TRACE(("wl_iw_get_wireless_stats counters rxrunt=%d\n",
++				dtoh32(cnt->rxrunt)));
++			WL_TRACE(("wl_iw_get_wireless_stats counters rxgiant=%d\n",
++				dtoh32(cnt->rxgiant)));
++			break;
++		}
++		case WL_CNT_XTLV_CNTV_LE10_UCODE:
++		case WL_CNT_XTLV_LT40_UCODE_V1:
++		case WL_CNT_XTLV_GE40_UCODE_V1:
++		{
++			/* Offsets of rxfrmtoolong and rxbadplcp are the same in
++			 * wl_cnt_v_le10_mcst_t, wl_cnt_lt40mcst_v1_t, and wl_cnt_ge40mcst_v1_t.
++			 * So we can just cast to wl_cnt_v_le10_mcst_t here.
++			 */
++			wl_cnt_v_le10_mcst_t *cnt = (wl_cnt_v_le10_mcst_t *)data;
++			if (len != WL_CNT_MCST_STRUCT_SZ) {
++				printf("counter structure length mismatch! %d != %d\n",
++					len, WL_CNT_MCST_STRUCT_SZ);
++			}
++			WL_TRACE(("wl_iw_get_wireless_stats counters rxfrmtoolong=%d\n",
++				dtoh32(cnt->rxfrmtoolong)));
++			WL_TRACE(("wl_iw_get_wireless_stats counters rxbadplcp=%d\n",
++				dtoh32(cnt->rxbadplcp)));
++			BCM_REFERENCE(cnt);
++			break;
++		}
++		default:
++			WL_ERROR(("%s %d: Unsupported type %d\n", __FUNCTION__, __LINE__, type));
++			break;
++	}
++	return res;
++}
++
++int wl_iw_get_wireless_stats(struct net_device *dev, struct iw_statistics *wstats)
++{
++	int res = 0;
++	int phy_noise;
++	int rssi;
++	scb_val_t scb_val;
++#if WIRELESS_EXT > 11
++	char *cntbuf = NULL;
++	wl_cnt_info_t *cntinfo;
++	uint16 ver;
++	uint32 corerev = 0;
++#endif /* WIRELESS_EXT > 11 */
++
++	phy_noise = 0;
++	if ((res = dev_wlc_ioctl(dev, WLC_GET_PHY_NOISE, &phy_noise, sizeof(phy_noise))))
++		goto done;
++
++	phy_noise = dtoh32(phy_noise);
++	WL_TRACE(("wl_iw_get_wireless_stats phy noise=%d\n *****", phy_noise));
++
++	scb_val.val = 0;
++	if ((res = dev_wlc_ioctl(dev, WLC_GET_RSSI, &scb_val, sizeof(scb_val_t))))
++		goto done;
++
++	rssi = dtoh32(scb_val.val);
++	WL_TRACE(("wl_iw_get_wireless_stats rssi=%d ****** \n", rssi));
++	if (rssi <= WL_IW_RSSI_NO_SIGNAL)
++		wstats->qual.qual = 0;
++	else if (rssi <= WL_IW_RSSI_VERY_LOW)
++		wstats->qual.qual = 1;
++	else if (rssi <= WL_IW_RSSI_LOW)
++		wstats->qual.qual = 2;
++	else if (rssi <= WL_IW_RSSI_GOOD)
++		wstats->qual.qual = 3;
++	else if (rssi <= WL_IW_RSSI_VERY_GOOD)
++		wstats->qual.qual = 4;
++	else
++		wstats->qual.qual = 5;
++
++	/* Wraps to 0 if RSSI is 0 */
++	wstats->qual.level = 0x100 + rssi;
++	wstats->qual.noise = 0x100 + phy_noise;
++#if WIRELESS_EXT > 18
++	wstats->qual.updated |= (IW_QUAL_ALL_UPDATED | IW_QUAL_DBM);
++#else
++	wstats->qual.updated |= 7;
++#endif /* WIRELESS_EXT > 18 */
++
++#if WIRELESS_EXT > 11
++	WL_TRACE(("wl_iw_get_wireless_stats counters=%d\n *****", WL_CNTBUF_MAX_SIZE));
++
++	if (WL_CNTBUF_MAX_SIZE > MAX_WLIW_IOCTL_LEN)
++	{
++		WL_ERROR(("wl_iw_get_wireless_stats buffer too short %d < %d\n",
++			WL_CNTBUF_MAX_SIZE, MAX_WLIW_IOCTL_LEN));
++		res = BCME_BUFTOOSHORT;
++		goto done;
++	}
++
++	cntbuf = kmalloc(WL_CNTBUF_MAX_SIZE, GFP_KERNEL);
++	if (!cntbuf) {
++		res = BCME_NOMEM;
++		goto done;
++	}
++
++	memset(cntbuf, 0, WL_CNTBUF_MAX_SIZE);
++	res = dev_wlc_bufvar_get(dev, "counters", cntbuf, WL_CNTBUF_MAX_SIZE);
++	if (res)
++	{
++		WL_ERROR(("wl_iw_get_wireless_stats counters failed error=%d ****** \n", res));
++		goto done;
++	}
++
++	cntinfo = (wl_cnt_info_t *)cntbuf;
++	cntinfo->version = dtoh16(cntinfo->version);
++	cntinfo->datalen = dtoh16(cntinfo->datalen);
++	ver = cntinfo->version;
++	if (ver > WL_CNT_T_VERSION) {
++		WL_TRACE(("\tIncorrect version of counters struct: expected %d; got %d\n",
++			WL_CNT_T_VERSION, ver));
++		res = BCME_VERSION;
++		goto done;
++	}
++
++	if (ver == WL_CNT_VERSION_11) {
++		wlc_rev_info_t revinfo;
++		memset(&revinfo, 0, sizeof(revinfo));
++		res = dev_wlc_ioctl(dev, WLC_GET_REVINFO, &revinfo, sizeof(revinfo));
++		if (res) {
++			WL_ERROR(("%s: WLC_GET_REVINFO failed %d\n", __FUNCTION__, res));
++			goto done;
++		}
++		corerev = dtoh32(revinfo.corerev);
++	}
++
++	res = wl_cntbuf_to_xtlv_format(NULL, cntinfo, WL_CNTBUF_MAX_SIZE, corerev);
++	if (res) {
++		WL_ERROR(("%s: wl_cntbuf_to_xtlv_format failed %d\n", __FUNCTION__, res));
++		goto done;
++	}
++
++	if ((res = bcm_unpack_xtlv_buf(wstats, cntinfo->data, cntinfo->datalen,
++		BCM_XTLV_OPTION_ALIGN32, wl_iw_get_wireless_stats_cbfn))) {
++		goto done;
++	}
++#endif /* WIRELESS_EXT > 11 */
++
++done:
++#if WIRELESS_EXT > 11
++	if (cntbuf) {
++		kfree(cntbuf);
++	}
++#endif /* WIRELESS_EXT > 11 */
++	return res;
++}
++
++static void
++wl_iw_timerfunc(ulong data)
++{
++	iscan_info_t *iscan = (iscan_info_t *)data;
++	iscan->timer_on = 0;
++	if (iscan->iscan_state != ISCAN_STATE_IDLE) {
++		WL_TRACE(("timer trigger\n"));
++		up(&iscan->sysioc_sem);
++	}
++}
++
++static void
++wl_iw_set_event_mask(struct net_device *dev)
++{
++	char eventmask[WL_EVENTING_MASK_LEN];
++	char iovbuf[WL_EVENTING_MASK_LEN + 12];	/* Room for "event_msgs" + '\0' + bitvec */
++
++	dev_iw_iovar_getbuf(dev, "event_msgs", "", 0, iovbuf, sizeof(iovbuf));
++	bcopy(iovbuf, eventmask, WL_EVENTING_MASK_LEN);
++	setbit(eventmask, WLC_E_SCAN_COMPLETE);
++	dev_iw_iovar_setbuf(dev, "event_msgs", eventmask, WL_EVENTING_MASK_LEN,
++		iovbuf, sizeof(iovbuf));
++
++}
++
++static int
++wl_iw_iscan_prep(wl_scan_params_t *params, wlc_ssid_t *ssid)
++{
++	int err = 0;
++
++	memcpy(&params->bssid, &ether_bcast, ETHER_ADDR_LEN);
++	params->bss_type = DOT11_BSSTYPE_ANY;
++	params->scan_type = 0;
++	params->nprobes = -1;
++	params->active_time = -1;
++	params->passive_time = -1;
++	params->home_time = -1;
++	params->channel_num = 0;
++
++	params->nprobes = htod32(params->nprobes);
++	params->active_time = htod32(params->active_time);
++	params->passive_time = htod32(params->passive_time);
++	params->home_time = htod32(params->home_time);
++	if (ssid && ssid->SSID_len)
++		memcpy(&params->ssid, ssid, sizeof(wlc_ssid_t));
++
++	return err;
++}
++
++static int
++wl_iw_iscan(iscan_info_t *iscan, wlc_ssid_t *ssid, uint16 action)
++{
++	int params_size = (WL_SCAN_PARAMS_FIXED_SIZE + OFFSETOF(wl_iscan_params_t, params));
++	wl_iscan_params_t *params;
++	int err = 0;
++
++	if (ssid && ssid->SSID_len) {
++		params_size += sizeof(wlc_ssid_t);
++	}
++	params = (wl_iscan_params_t*)kmalloc(params_size, GFP_KERNEL);
++	if (params == NULL) {
++		return -ENOMEM;
++	}
++	memset(params, 0, params_size);
++	ASSERT(params_size < WLC_IOCTL_SMLEN);
++
++	err = wl_iw_iscan_prep(&params->params, ssid);
++
++	if (!err) {
++		params->version = htod32(ISCAN_REQ_VERSION);
++		params->action = htod16(action);
++		params->scan_duration = htod16(0);
++
++		/* params_size += OFFSETOF(wl_iscan_params_t, params); */
++		(void) dev_iw_iovar_setbuf(iscan->dev, "iscan", params, params_size,
++			iscan->ioctlbuf, WLC_IOCTL_SMLEN);
++	}
++
++	kfree(params);
++	return err;
++}
++
++static uint32
++wl_iw_iscan_get(iscan_info_t *iscan)
++{
++	iscan_buf_t * buf;
++	iscan_buf_t * ptr;
++	wl_iscan_results_t * list_buf;
++	wl_iscan_results_t list;
++	wl_scan_results_t *results;
++	uint32 status;
++
++	/* buffers are allocated on demand */
++	if (iscan->list_cur) {
++		buf = iscan->list_cur;
++		iscan->list_cur = buf->next;
++	}
++	else {
++		buf = kmalloc(sizeof(iscan_buf_t), GFP_KERNEL);
++		if (!buf)
++			return WL_SCAN_RESULTS_ABORTED;
++		buf->next = NULL;
++		if (!iscan->list_hdr)
++			iscan->list_hdr = buf;
++		else {
++			ptr = iscan->list_hdr;
++			while (ptr->next) {
++				ptr = ptr->next;
++			}
++			ptr->next = buf;
++		}
++	}
++	memset(buf->iscan_buf, 0, WLC_IW_ISCAN_MAXLEN);
++	list_buf = (wl_iscan_results_t*)buf->iscan_buf;
++	results = &list_buf->results;
++	results->buflen = WL_ISCAN_RESULTS_FIXED_SIZE;
++	results->version = 0;
++	results->count = 0;
++
++	memset(&list, 0, sizeof(list));
++	list.results.buflen = htod32(WLC_IW_ISCAN_MAXLEN);
++	(void) dev_iw_iovar_getbuf(
++		iscan->dev,
++		"iscanresults",
++		&list,
++		WL_ISCAN_RESULTS_FIXED_SIZE,
++		buf->iscan_buf,
++		WLC_IW_ISCAN_MAXLEN);
++	results->buflen = dtoh32(results->buflen);
++	results->version = dtoh32(results->version);
++	results->count = dtoh32(results->count);
++	WL_TRACE(("results->count = %d\n", results->count));
++
++	WL_TRACE(("results->buflen = %d\n", results->buflen));
++	status = dtoh32(list_buf->status);
++	return status;
++}
++
++static void wl_iw_send_scan_complete(iscan_info_t *iscan)
++{
++	union iwreq_data wrqu;
++
++	memset(&wrqu, 0, sizeof(wrqu));
++
++	/* wext expects to get no data for SIOCGIWSCAN Event  */
++	wireless_send_event(iscan->dev, SIOCGIWSCAN, &wrqu, NULL);
++}
++
++static int
++_iscan_sysioc_thread(void *data)
++{
++	uint32 status;
++	iscan_info_t *iscan = (iscan_info_t *)data;
++
++	DAEMONIZE("iscan_sysioc");
++
++	status = WL_SCAN_RESULTS_PARTIAL;
++	while (down_interruptible(&iscan->sysioc_sem) == 0) {
++		if (iscan->timer_on) {
++			del_timer(&iscan->timer);
++			iscan->timer_on = 0;
++		}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++		rtnl_lock();
++#endif
++		status = wl_iw_iscan_get(iscan);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++		rtnl_unlock();
++#endif
++
++		switch (status) {
++			case WL_SCAN_RESULTS_PARTIAL:
++				WL_TRACE(("iscanresults incomplete\n"));
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++				rtnl_lock();
++#endif
++				/* make sure our buffer size is enough before going next round */
++				wl_iw_iscan(iscan, NULL, WL_SCAN_ACTION_CONTINUE);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++				rtnl_unlock();
++#endif
++				/* Reschedule the timer */
++				iscan->timer.expires = jiffies + msecs_to_jiffies(iscan->timer_ms);
++				add_timer(&iscan->timer);
++				iscan->timer_on = 1;
++				break;
++			case WL_SCAN_RESULTS_SUCCESS:
++				WL_TRACE(("iscanresults complete\n"));
++				iscan->iscan_state = ISCAN_STATE_IDLE;
++				wl_iw_send_scan_complete(iscan);
++				break;
++			case WL_SCAN_RESULTS_PENDING:
++				WL_TRACE(("iscanresults pending\n"));
++				/* Reschedule the timer */
++				iscan->timer.expires = jiffies + msecs_to_jiffies(iscan->timer_ms);
++				add_timer(&iscan->timer);
++				iscan->timer_on = 1;
++				break;
++			case WL_SCAN_RESULTS_ABORTED:
++				WL_TRACE(("iscanresults aborted\n"));
++				iscan->iscan_state = ISCAN_STATE_IDLE;
++				wl_iw_send_scan_complete(iscan);
++				break;
++			default:
++				WL_TRACE(("iscanresults returned unknown status %d\n", status));
++				break;
++		 }
++	}
++	complete_and_exit(&iscan->sysioc_exited, 0);
++}
++
++int
++wl_iw_attach(struct net_device *dev, void * dhdp)
++{
++	iscan_info_t *iscan = NULL;
++
++	if (!dev)
++		return 0;
++
++	iscan = kmalloc(sizeof(iscan_info_t), GFP_KERNEL);
++	if (!iscan)
++		return -ENOMEM;
++	memset(iscan, 0, sizeof(iscan_info_t));
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
++	iscan->kthread = NULL;
++#endif
++	iscan->sysioc_pid = -1;
++	/* we only care about main interface so save a global here */
++	g_iscan = iscan;
++	iscan->dev = dev;
++	iscan->iscan_state = ISCAN_STATE_IDLE;
++
++
++	/* Set up the timer */
++	iscan->timer_ms    = 2000;
++	init_timer(&iscan->timer);
++	iscan->timer.data = (ulong)iscan;
++	iscan->timer.function = wl_iw_timerfunc;
++
++	sema_init(&iscan->sysioc_sem, 0);
++	init_completion(&iscan->sysioc_exited);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
++	iscan->kthread = kthread_run(_iscan_sysioc_thread, iscan, "iscan_sysioc");
++	iscan->sysioc_pid = iscan->kthread->pid;
++#else
++	iscan->sysioc_pid = kernel_thread(_iscan_sysioc_thread, iscan, 0);
++#endif
++	if (iscan->sysioc_pid < 0)
++		return -ENOMEM;
++	return 0;
++}
++
++void wl_iw_detach(void)
++{
++	iscan_buf_t  *buf;
++	iscan_info_t *iscan = g_iscan;
++	if (!iscan)
++		return;
++	if (iscan->sysioc_pid >= 0) {
++		KILL_PROC(iscan->sysioc_pid, SIGTERM);
++		wait_for_completion(&iscan->sysioc_exited);
++	}
++
++	while (iscan->list_hdr) {
++		buf = iscan->list_hdr->next;
++		kfree(iscan->list_hdr);
++		iscan->list_hdr = buf;
++	}
++	kfree(iscan);
++	g_iscan = NULL;
++}
++
++#endif /* USE_IW */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_iw.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_iw.h
+new file mode 100644
+index 000000000..1396d12cd
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_iw.h
+@@ -0,0 +1,164 @@
++/*
++ * Linux Wireless Extensions support
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_iw.h 514727 2014-11-12 03:02:48Z $
++ */
++
++#ifndef _wl_iw_h_
++#define _wl_iw_h_
++
++#include <linux/wireless.h>
++
++#include <typedefs.h>
++#include <proto/ethernet.h>
++#include <wlioctl.h>
++
++#define WL_SCAN_PARAMS_SSID_MAX 	10
++#define GET_SSID			"SSID="
++#define GET_CHANNEL			"CH="
++#define GET_NPROBE 			"NPROBE="
++#define GET_ACTIVE_ASSOC_DWELL  	"ACTIVE="
++#define GET_PASSIVE_ASSOC_DWELL  	"PASSIVE="
++#define GET_HOME_DWELL  		"HOME="
++#define GET_SCAN_TYPE			"TYPE="
++
++#define BAND_GET_CMD				"GETBAND"
++#define BAND_SET_CMD				"SETBAND"
++#define DTIM_SKIP_GET_CMD			"DTIMSKIPGET"
++#define DTIM_SKIP_SET_CMD			"DTIMSKIPSET"
++#define SETSUSPEND_CMD				"SETSUSPENDOPT"
++#define PNOSSIDCLR_SET_CMD			"PNOSSIDCLR"
++/* Lin - Is the extra space needed? */
++#define PNOSETUP_SET_CMD			"PNOSETUP " /* TLV command has extra end space */
++#define PNOENABLE_SET_CMD			"PNOFORCE"
++#define PNODEBUG_SET_CMD			"PNODEBUG"
++#define TXPOWER_SET_CMD			"TXPOWER"
++
++#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
++#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
++
++/* Structure to keep global parameters */
++typedef struct wl_iw_extra_params {
++	int 	target_channel; /* target channel */
++} wl_iw_extra_params_t;
++
++struct cntry_locales_custom {
++	char iso_abbrev[WLC_CNTRY_BUF_SZ];	/* ISO 3166-1 country abbreviation */
++	char custom_locale[WLC_CNTRY_BUF_SZ];	/* Custom firmware locale */
++	int32 custom_locale_rev;		/* Custom local revisin default -1 */
++};
++/* ============================================== */
++/* Defines from wlc_pub.h */
++#define	WL_IW_RSSI_MINVAL		-200	/* Low value, e.g. for forcing roam */
++#define	WL_IW_RSSI_NO_SIGNAL	-91	/* NDIS RSSI link quality cutoffs */
++#define	WL_IW_RSSI_VERY_LOW	-80	/* Very low quality cutoffs */
++#define	WL_IW_RSSI_LOW		-70	/* Low quality cutoffs */
++#define	WL_IW_RSSI_GOOD		-68	/* Good quality cutoffs */
++#define	WL_IW_RSSI_VERY_GOOD	-58	/* Very good quality cutoffs */
++#define	WL_IW_RSSI_EXCELLENT	-57	/* Excellent quality cutoffs */
++#define	WL_IW_RSSI_INVALID	 0	/* invalid RSSI value */
++#define MAX_WX_STRING 80
++#define SSID_FMT_BUF_LEN	((4 * 32) + 1)
++#define isprint(c) bcm_isprint(c)
++#define WL_IW_SET_ACTIVE_SCAN	(SIOCIWFIRSTPRIV+1)
++#define WL_IW_GET_RSSI			(SIOCIWFIRSTPRIV+3)
++#define WL_IW_SET_PASSIVE_SCAN	(SIOCIWFIRSTPRIV+5)
++#define WL_IW_GET_LINK_SPEED	(SIOCIWFIRSTPRIV+7)
++#define WL_IW_GET_CURR_MACADDR	(SIOCIWFIRSTPRIV+9)
++#define WL_IW_SET_STOP				(SIOCIWFIRSTPRIV+11)
++#define WL_IW_SET_START			(SIOCIWFIRSTPRIV+13)
++
++#define 		G_SCAN_RESULTS 8*1024
++#define 		WE_ADD_EVENT_FIX	0x80
++#define          G_WLAN_SET_ON	0
++#define          G_WLAN_SET_OFF	1
++
++
++typedef struct wl_iw {
++	char nickname[IW_ESSID_MAX_SIZE];
++
++	struct iw_statistics wstats;
++
++	int spy_num;
++	uint32 pwsec;			/* pairwise wsec setting */
++	uint32 gwsec;			/* group wsec setting  */
++	bool privacy_invoked; 		/* IW_AUTH_PRIVACY_INVOKED setting */
++	struct ether_addr spy_addr[IW_MAX_SPY];
++	struct iw_quality spy_qual[IW_MAX_SPY];
++	void  *wlinfo;
++} wl_iw_t;
++
++struct wl_ctrl {
++	struct timer_list *timer;
++	struct net_device *dev;
++	long sysioc_pid;
++	struct semaphore sysioc_sem;
++	struct completion sysioc_exited;
++};
++
++
++#if WIRELESS_EXT > 12
++#include <net/iw_handler.h>
++extern const struct iw_handler_def wl_iw_handler_def;
++#endif /* WIRELESS_EXT > 12 */
++
++extern int wl_iw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
++extern void wl_iw_event(struct net_device *dev, wl_event_msg_t *e, void* data);
++extern int wl_iw_get_wireless_stats(struct net_device *dev, struct iw_statistics *wstats);
++int wl_iw_attach(struct net_device *dev, void * dhdp);
++int wl_iw_send_priv_event(struct net_device *dev, char *flag);
++
++void wl_iw_detach(void);
++
++#define CSCAN_COMMAND				"CSCAN "
++#define CSCAN_TLV_PREFIX 			'S'
++#define CSCAN_TLV_VERSION			1
++#define CSCAN_TLV_SUBVERSION			0
++#define CSCAN_TLV_TYPE_SSID_IE          'S'
++#define CSCAN_TLV_TYPE_CHANNEL_IE   'C'
++#define CSCAN_TLV_TYPE_NPROBE_IE     'N'
++#define CSCAN_TLV_TYPE_ACTIVE_IE      'A'
++#define CSCAN_TLV_TYPE_PASSIVE_IE    'P'
++#define CSCAN_TLV_TYPE_HOME_IE         'H'
++#define CSCAN_TLV_TYPE_STYPE_IE        'T'
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++#define IWE_STREAM_ADD_EVENT(info, stream, ends, iwe, extra) \
++	iwe_stream_add_event(info, stream, ends, iwe, extra)
++#define IWE_STREAM_ADD_VALUE(info, event, value, ends, iwe, event_len) \
++	iwe_stream_add_value(info, event, value, ends, iwe, event_len)
++#define IWE_STREAM_ADD_POINT(info, stream, ends, iwe, extra) \
++	iwe_stream_add_point(info, stream, ends, iwe, extra)
++#else
++#define IWE_STREAM_ADD_EVENT(info, stream, ends, iwe, extra) \
++	iwe_stream_add_event(stream, ends, iwe, extra)
++#define IWE_STREAM_ADD_VALUE(info, event, value, ends, iwe, event_len) \
++	iwe_stream_add_value(event, value, ends, iwe, event_len)
++#define IWE_STREAM_ADD_POINT(info, stream, ends, iwe, extra) \
++	iwe_stream_add_point(stream, ends, iwe, extra)
++#endif
++
++#endif /* _wl_iw_h_ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_linux_mon.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_linux_mon.c
+new file mode 100644
+index 000000000..9bd762581
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_linux_mon.c
+@@ -0,0 +1,406 @@
++/*
++ * Broadcom Dongle Host Driver (DHD), Linux monitor network interface
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_linux_mon.c 514727 2014-11-12 03:02:48Z $
++ */
++
++#include <osl.h>
++#include <linux/string.h>
++#include <linux/module.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/if_arp.h>
++#include <linux/ieee80211.h>
++#include <linux/rtnetlink.h>
++#include <net/ieee80211_radiotap.h>
++
++#include <wlioctl.h>
++#include <bcmutils.h>
++#include <dhd_dbg.h>
++#include <dngl_stats.h>
++#include <dhd.h>
++
++typedef enum monitor_states
++{
++	MONITOR_STATE_DEINIT = 0x0,
++	MONITOR_STATE_INIT = 0x1,
++	MONITOR_STATE_INTERFACE_ADDED = 0x2,
++	MONITOR_STATE_INTERFACE_DELETED = 0x4
++} monitor_states_t;
++int dhd_add_monitor(char *name, struct net_device **new_ndev);
++extern int dhd_start_xmit(struct sk_buff *skb, struct net_device *net);
++int dhd_del_monitor(struct net_device *ndev);
++int dhd_monitor_init(void *dhd_pub);
++int dhd_monitor_uninit(void);
++
++/**
++ * Local declarations and defintions (not exposed)
++ */
++#ifndef DHD_MAX_IFS
++#define DHD_MAX_IFS 16
++#endif
++#define MON_PRINT(format, ...) printk("DHD-MON: %s " format, __func__, ##__VA_ARGS__)
++#define MON_TRACE MON_PRINT
++
++typedef struct monitor_interface {
++	int radiotap_enabled;
++	struct net_device* real_ndev;	/* The real interface that the monitor is on */
++	struct net_device* mon_ndev;
++} monitor_interface;
++
++typedef struct dhd_linux_monitor {
++	void *dhd_pub;
++	monitor_states_t monitor_state;
++	monitor_interface mon_if[DHD_MAX_IFS];
++	struct mutex lock;		/* lock to protect mon_if */
++} dhd_linux_monitor_t;
++
++static dhd_linux_monitor_t g_monitor;
++
++static struct net_device* lookup_real_netdev(char *name);
++static monitor_interface* ndev_to_monif(struct net_device *ndev);
++static int dhd_mon_if_open(struct net_device *ndev);
++static int dhd_mon_if_stop(struct net_device *ndev);
++static int dhd_mon_if_subif_start_xmit(struct sk_buff *skb, struct net_device *ndev);
++static void dhd_mon_if_set_multicast_list(struct net_device *ndev);
++static int dhd_mon_if_change_mac(struct net_device *ndev, void *addr);
++
++static const struct net_device_ops dhd_mon_if_ops = {
++	.ndo_open		= dhd_mon_if_open,
++	.ndo_stop		= dhd_mon_if_stop,
++	.ndo_start_xmit		= dhd_mon_if_subif_start_xmit,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	.ndo_set_rx_mode = dhd_mon_if_set_multicast_list,
++#else
++	.ndo_set_multicast_list = dhd_mon_if_set_multicast_list,
++#endif
++	.ndo_set_mac_address 	= dhd_mon_if_change_mac,
++};
++
++/**
++ * Local static function defintions
++ */
++
++/* Look up dhd's net device table to find a match (e.g. interface "eth0" is a match for "mon.eth0"
++ * "p2p-eth0-0" is a match for "mon.p2p-eth0-0")
++ */
++static struct net_device* lookup_real_netdev(char *name)
++{
++	struct net_device *ndev_found = NULL;
++
++	int i;
++	int len = 0;
++	int last_name_len = 0;
++	struct net_device *ndev;
++
++	/* We need to find interface "p2p-p2p-0" corresponding to monitor interface "mon-p2p-0",
++	 * Once mon iface name reaches IFNAMSIZ, it is reset to p2p0-0 and corresponding mon
++	 * iface would be mon-p2p0-0.
++	 */
++	for (i = 0; i < DHD_MAX_IFS; i++) {
++		ndev = dhd_idx2net(g_monitor.dhd_pub, i);
++
++		/* Skip "p2p" and look for "-p2p0-x" in monitor interface name. If it
++		 * it matches, then this netdev is the corresponding real_netdev.
++		 */
++		if (ndev && strstr(ndev->name, "p2p-p2p0")) {
++			len = strlen("p2p");
++		} else {
++		/* if p2p- is not present, then the IFNAMSIZ have reached and name
++		 * would have got reset. In this casse,look for p2p0-x in mon-p2p0-x
++		 */
++			len = 0;
++		}
++		if (ndev && strstr(name, (ndev->name + len))) {
++			if (strlen(ndev->name) > last_name_len) {
++				ndev_found = ndev;
++				last_name_len = strlen(ndev->name);
++			}
++		}
++	}
++
++	return ndev_found;
++}
++
++static monitor_interface* ndev_to_monif(struct net_device *ndev)
++{
++	int i;
++
++	for (i = 0; i < DHD_MAX_IFS; i++) {
++		if (g_monitor.mon_if[i].mon_ndev == ndev)
++			return &g_monitor.mon_if[i];
++	}
++
++	return NULL;
++}
++
++static int dhd_mon_if_open(struct net_device *ndev)
++{
++	int ret = 0;
++
++	MON_PRINT("enter\n");
++	return ret;
++}
++
++static int dhd_mon_if_stop(struct net_device *ndev)
++{
++	int ret = 0;
++
++	MON_PRINT("enter\n");
++	return ret;
++}
++
++static int dhd_mon_if_subif_start_xmit(struct sk_buff *skb, struct net_device *ndev)
++{
++	int ret = 0;
++	int rtap_len;
++	int qos_len = 0;
++	int dot11_hdr_len = 24;
++	int snap_len = 6;
++	unsigned char *pdata;
++	unsigned short frame_ctl;
++	unsigned char src_mac_addr[6];
++	unsigned char dst_mac_addr[6];
++	struct ieee80211_hdr *dot11_hdr;
++	struct ieee80211_radiotap_header *rtap_hdr;
++	monitor_interface* mon_if;
++
++	MON_PRINT("enter\n");
++
++	mon_if = ndev_to_monif(ndev);
++	if (mon_if == NULL || mon_if->real_ndev == NULL) {
++		MON_PRINT(" cannot find matched net dev, skip the packet\n");
++		goto fail;
++	}
++
++	if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header)))
++		goto fail;
++
++	rtap_hdr = (struct ieee80211_radiotap_header *)skb->data;
++	if (unlikely(rtap_hdr->it_version))
++		goto fail;
++
++	rtap_len = ieee80211_get_radiotap_len(skb->data);
++	if (unlikely(skb->len < rtap_len))
++		goto fail;
++
++	MON_PRINT("radiotap len (should be 14): %d\n", rtap_len);
++
++	/* Skip the ratio tap header */
++	skb_pull(skb, rtap_len);
++
++	dot11_hdr = (struct ieee80211_hdr *)skb->data;
++	frame_ctl = le16_to_cpu(dot11_hdr->frame_control);
++	/* Check if the QoS bit is set */
++	if ((frame_ctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) {
++		/* Check if this ia a Wireless Distribution System (WDS) frame
++		 * which has 4 MAC addresses
++		 */
++		if (dot11_hdr->frame_control & 0x0080)
++			qos_len = 2;
++		if ((dot11_hdr->frame_control & 0x0300) == 0x0300)
++			dot11_hdr_len += 6;
++
++		memcpy(dst_mac_addr, dot11_hdr->addr1, sizeof(dst_mac_addr));
++		memcpy(src_mac_addr, dot11_hdr->addr2, sizeof(src_mac_addr));
++
++		/* Skip the 802.11 header, QoS (if any) and SNAP, but leave spaces for
++		 * for two MAC addresses
++		 */
++		skb_pull(skb, dot11_hdr_len + qos_len + snap_len - sizeof(src_mac_addr) * 2);
++		pdata = (unsigned char*)skb->data;
++		memcpy(pdata, dst_mac_addr, sizeof(dst_mac_addr));
++		memcpy(pdata + sizeof(dst_mac_addr), src_mac_addr, sizeof(src_mac_addr));
++		PKTSETPRIO(skb, 0);
++
++		MON_PRINT("if name: %s, matched if name %s\n", ndev->name, mon_if->real_ndev->name);
++
++		/* Use the real net device to transmit the packet */
++		ret = dhd_start_xmit(skb, mon_if->real_ndev);
++
++		return ret;
++	}
++fail:
++	dev_kfree_skb(skb);
++	return 0;
++}
++
++static void dhd_mon_if_set_multicast_list(struct net_device *ndev)
++{
++	monitor_interface* mon_if;
++
++	mon_if = ndev_to_monif(ndev);
++	if (mon_if == NULL || mon_if->real_ndev == NULL) {
++		MON_PRINT(" cannot find matched net dev, skip the packet\n");
++	} else {
++		MON_PRINT("enter, if name: %s, matched if name %s\n",
++		ndev->name, mon_if->real_ndev->name);
++	}
++}
++
++static int dhd_mon_if_change_mac(struct net_device *ndev, void *addr)
++{
++	int ret = 0;
++	monitor_interface* mon_if;
++
++	mon_if = ndev_to_monif(ndev);
++	if (mon_if == NULL || mon_if->real_ndev == NULL) {
++		MON_PRINT(" cannot find matched net dev, skip the packet\n");
++	} else {
++		MON_PRINT("enter, if name: %s, matched if name %s\n",
++		ndev->name, mon_if->real_ndev->name);
++	}
++	return ret;
++}
++
++/**
++ * Global function definitions (declared in dhd_linux_mon.h)
++ */
++
++int dhd_add_monitor(char *name, struct net_device **new_ndev)
++{
++	int i;
++	int idx = -1;
++	int ret = 0;
++	struct net_device* ndev = NULL;
++	dhd_linux_monitor_t **dhd_mon;
++
++	mutex_lock(&g_monitor.lock);
++
++	MON_TRACE("enter, if name: %s\n", name);
++	if (!name || !new_ndev) {
++		MON_PRINT("invalid parameters\n");
++		ret = -EINVAL;
++		goto out;
++	}
++
++	/*
++	 * Find a vacancy
++	 */
++	for (i = 0; i < DHD_MAX_IFS; i++)
++		if (g_monitor.mon_if[i].mon_ndev == NULL) {
++			idx = i;
++			break;
++		}
++	if (idx == -1) {
++		MON_PRINT("exceeds maximum interfaces\n");
++		ret = -EFAULT;
++		goto out;
++	}
++
++	ndev = alloc_etherdev(sizeof(dhd_linux_monitor_t*));
++	if (!ndev) {
++		MON_PRINT("failed to allocate memory\n");
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	ndev->type = ARPHRD_IEEE80211_RADIOTAP;
++	strncpy(ndev->name, name, IFNAMSIZ);
++	ndev->name[IFNAMSIZ - 1] = 0;
++	ndev->netdev_ops = &dhd_mon_if_ops;
++
++	ret = register_netdevice(ndev);
++	if (ret) {
++		MON_PRINT(" register_netdevice failed (%d)\n", ret);
++		goto out;
++	}
++
++	*new_ndev = ndev;
++	g_monitor.mon_if[idx].radiotap_enabled = TRUE;
++	g_monitor.mon_if[idx].mon_ndev = ndev;
++	g_monitor.mon_if[idx].real_ndev = lookup_real_netdev(name);
++	dhd_mon = (dhd_linux_monitor_t **)netdev_priv(ndev);
++	*dhd_mon = &g_monitor;
++	g_monitor.monitor_state = MONITOR_STATE_INTERFACE_ADDED;
++	MON_PRINT("net device returned: 0x%p\n", ndev);
++	MON_PRINT("found a matched net device, name %s\n", g_monitor.mon_if[idx].real_ndev->name);
++
++out:
++	if (ret && ndev)
++		free_netdev(ndev);
++
++	mutex_unlock(&g_monitor.lock);
++	return ret;
++
++}
++
++int dhd_del_monitor(struct net_device *ndev)
++{
++	int i;
++	if (!ndev)
++		return -EINVAL;
++	mutex_lock(&g_monitor.lock);
++	for (i = 0; i < DHD_MAX_IFS; i++) {
++		if (g_monitor.mon_if[i].mon_ndev == ndev ||
++			g_monitor.mon_if[i].real_ndev == ndev) {
++
++			g_monitor.mon_if[i].real_ndev = NULL;
++			unregister_netdevice(g_monitor.mon_if[i].mon_ndev);
++			free_netdev(g_monitor.mon_if[i].mon_ndev);
++			g_monitor.mon_if[i].mon_ndev = NULL;
++			g_monitor.monitor_state = MONITOR_STATE_INTERFACE_DELETED;
++			break;
++		}
++	}
++
++	if (g_monitor.monitor_state != MONITOR_STATE_INTERFACE_DELETED)
++		MON_PRINT("IF not found in monitor array, is this a monitor IF? 0x%p\n", ndev);
++	mutex_unlock(&g_monitor.lock);
++
++	return 0;
++}
++
++int dhd_monitor_init(void *dhd_pub)
++{
++	if (g_monitor.monitor_state == MONITOR_STATE_DEINIT) {
++		g_monitor.dhd_pub = dhd_pub;
++		mutex_init(&g_monitor.lock);
++		g_monitor.monitor_state = MONITOR_STATE_INIT;
++	}
++	return 0;
++}
++
++int dhd_monitor_uninit(void)
++{
++	int i;
++	struct net_device *ndev;
++	mutex_lock(&g_monitor.lock);
++	if (g_monitor.monitor_state != MONITOR_STATE_DEINIT) {
++		for (i = 0; i < DHD_MAX_IFS; i++) {
++			ndev = g_monitor.mon_if[i].mon_ndev;
++			if (ndev) {
++				unregister_netdevice(ndev);
++				free_netdev(ndev);
++				g_monitor.mon_if[i].real_ndev = NULL;
++				g_monitor.mon_if[i].mon_ndev = NULL;
++			}
++		}
++		g_monitor.monitor_state = MONITOR_STATE_DEINIT;
++	}
++	mutex_unlock(&g_monitor.lock);
++	return 0;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_roam.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_roam.c
+new file mode 100644
+index 000000000..876b129a5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wl_roam.c
+@@ -0,0 +1,28 @@
++/*
++ * Linux roam cache
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wl_roam.c 589977 2015-10-01 07:03:40Z $
++ */
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wldev_common.c b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wldev_common.c
+new file mode 100644
+index 000000000..1b5b4c03f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wldev_common.c
+@@ -0,0 +1,465 @@
++/*
++ * Common function shared by Linux WEXT, cfg80211 and p2p drivers
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wldev_common.c 674374 2017-10-20 07:38:00Z $
++ */
++
++#include <osl.h>
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/netdevice.h>
++
++#include <wldev_common.h>
++#include <bcmutils.h>
++
++#define htod32(i) (i)
++#define htod16(i) (i)
++#define dtoh32(i) (i)
++#define dtoh16(i) (i)
++#define htodchanspec(i) (i)
++#define dtohchanspec(i) (i)
++
++#define	WLDEV_ERROR(args)						\
++	do {										\
++		printk(KERN_ERR "WLDEV-ERROR) %s : ", __func__);	\
++		printk args;							\
++	} while (0)
++
++extern int dhd_ioctl_entry_local(struct net_device *net, wl_ioctl_t *ioc, int cmd);
++
++s32 wldev_ioctl(
++	struct net_device *dev, u32 cmd, void *arg, u32 len, u32 set)
++{
++	s32 ret = 0;
++	struct wl_ioctl ioc;
++
++
++	memset(&ioc, 0, sizeof(ioc));
++	ioc.cmd = cmd;
++	ioc.buf = arg;
++	ioc.len = len;
++	ioc.set = set;
++
++	ret = dhd_ioctl_entry_local(dev, &ioc, cmd);
++
++	return ret;
++}
++
++/* Format a iovar buffer, not bsscfg indexed. The bsscfg index will be
++ * taken care of in dhd_ioctl_entry. Internal use only, not exposed to
++ * wl_iw, wl_cfg80211 and wl_cfgp2p
++ */
++static s32 wldev_mkiovar(
++	const s8 *iovar_name, s8 *param, s32 paramlen,
++	s8 *iovar_buf, u32 buflen)
++{
++	s32 iolen = 0;
++
++	iolen = bcm_mkiovar(iovar_name, param, paramlen, iovar_buf, buflen);
++	return iolen;
++}
++
++s32 wldev_iovar_getbuf(
++	struct net_device *dev, s8 *iovar_name,
++	void *param, s32 paramlen, void *buf, s32 buflen, struct mutex* buf_sync)
++{
++	s32 ret = 0;
++	if (buf_sync) {
++		mutex_lock(buf_sync);
++	}
++	wldev_mkiovar(iovar_name, param, paramlen, buf, buflen);
++	ret = wldev_ioctl(dev, WLC_GET_VAR, buf, buflen, FALSE);
++	if (buf_sync)
++		mutex_unlock(buf_sync);
++	return ret;
++}
++
++
++s32 wldev_iovar_setbuf(
++	struct net_device *dev, s8 *iovar_name,
++	void *param, s32 paramlen, void *buf, s32 buflen, struct mutex* buf_sync)
++{
++	s32 ret = 0;
++	s32 iovar_len;
++	if (buf_sync) {
++		mutex_lock(buf_sync);
++	}
++	iovar_len = wldev_mkiovar(iovar_name, param, paramlen, buf, buflen);
++	if (iovar_len > 0)
++		ret = wldev_ioctl(dev, WLC_SET_VAR, buf, iovar_len, TRUE);
++	else
++		ret = BCME_BUFTOOSHORT;
++
++	if (buf_sync)
++		mutex_unlock(buf_sync);
++	return ret;
++}
++
++s32 wldev_iovar_setint(
++	struct net_device *dev, s8 *iovar, s32 val)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++
++	val = htod32(val);
++	memset(iovar_buf, 0, sizeof(iovar_buf));
++	return wldev_iovar_setbuf(dev, iovar, &val, sizeof(val), iovar_buf,
++		sizeof(iovar_buf), NULL);
++}
++
++
++s32 wldev_iovar_getint(
++	struct net_device *dev, s8 *iovar, s32 *pval)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	s32 err;
++
++	memset(iovar_buf, 0, sizeof(iovar_buf));
++	err = wldev_iovar_getbuf(dev, iovar, pval, sizeof(*pval), iovar_buf,
++		sizeof(iovar_buf), NULL);
++	if (err == 0)
++	{
++		memcpy(pval, iovar_buf, sizeof(*pval));
++		*pval = dtoh32(*pval);
++	}
++	return err;
++}
++
++/** Format a bsscfg indexed iovar buffer. The bsscfg index will be
++ *  taken care of in dhd_ioctl_entry. Internal use only, not exposed to
++ *  wl_iw, wl_cfg80211 and wl_cfgp2p
++ */
++s32 wldev_mkiovar_bsscfg(
++	const s8 *iovar_name, s8 *param, s32 paramlen,
++	s8 *iovar_buf, s32 buflen, s32 bssidx)
++{
++	const s8 *prefix = "bsscfg:";
++	s8 *p;
++	u32 prefixlen;
++	u32 namelen;
++	u32 iolen;
++
++	/* initialize buffer */
++	if (!iovar_buf || buflen == 0)
++		return BCME_BADARG;
++	memset(iovar_buf, 0, buflen);
++
++	if (bssidx == 0) {
++		return wldev_mkiovar(iovar_name, param, paramlen,
++			iovar_buf, buflen);
++	}
++
++	prefixlen = (u32) strlen(prefix); /* lengh of bsscfg prefix */
++	namelen = (u32) strlen(iovar_name) + 1; /* lengh of iovar  name + null */
++	iolen = prefixlen + namelen + sizeof(u32) + paramlen;
++
++	if (buflen < 0 || iolen > (u32)buflen)
++	{
++		WLDEV_ERROR(("%s: buffer is too short\n", __FUNCTION__));
++		return BCME_BUFTOOSHORT;
++	}
++
++	p = (s8 *)iovar_buf;
++
++	/* copy prefix, no null */
++	memcpy(p, prefix, prefixlen);
++	p += prefixlen;
++
++	/* copy iovar name including null */
++	memcpy(p, iovar_name, namelen);
++	p += namelen;
++
++	/* bss config index as first param */
++	bssidx = htod32(bssidx);
++	memcpy(p, &bssidx, sizeof(u32));
++	p += sizeof(u32);
++
++	/* parameter buffer follows */
++	if (paramlen)
++		memcpy(p, param, paramlen);
++
++	return iolen;
++
++}
++
++s32 wldev_iovar_getbuf_bsscfg(
++	struct net_device *dev, s8 *iovar_name,
++	void *param, s32 paramlen, void *buf, s32 buflen, s32 bsscfg_idx, struct mutex* buf_sync)
++{
++	s32 ret = 0;
++	if (buf_sync) {
++		mutex_lock(buf_sync);
++	}
++
++	wldev_mkiovar_bsscfg(iovar_name, param, paramlen, buf, buflen, bsscfg_idx);
++	ret = wldev_ioctl(dev, WLC_GET_VAR, buf, buflen, FALSE);
++	if (buf_sync) {
++		mutex_unlock(buf_sync);
++	}
++	return ret;
++
++}
++
++s32 wldev_iovar_setbuf_bsscfg(
++	struct net_device *dev, s8 *iovar_name,
++	void *param, s32 paramlen, void *buf, s32 buflen, s32 bsscfg_idx, struct mutex* buf_sync)
++{
++	s32 ret = 0;
++	s32 iovar_len;
++	if (buf_sync) {
++		mutex_lock(buf_sync);
++	}
++	iovar_len = wldev_mkiovar_bsscfg(iovar_name, param, paramlen, buf, buflen, bsscfg_idx);
++	if (iovar_len > 0)
++		ret = wldev_ioctl(dev, WLC_SET_VAR, buf, iovar_len, TRUE);
++	else {
++		ret = BCME_BUFTOOSHORT;
++	}
++
++	if (buf_sync) {
++		mutex_unlock(buf_sync);
++	}
++	return ret;
++}
++
++s32 wldev_iovar_setint_bsscfg(
++	struct net_device *dev, s8 *iovar, s32 val, s32 bssidx)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++
++	val = htod32(val);
++	memset(iovar_buf, 0, sizeof(iovar_buf));
++	return wldev_iovar_setbuf_bsscfg(dev, iovar, &val, sizeof(val), iovar_buf,
++		sizeof(iovar_buf), bssidx, NULL);
++}
++
++
++s32 wldev_iovar_getint_bsscfg(
++	struct net_device *dev, s8 *iovar, s32 *pval, s32 bssidx)
++{
++	s8 iovar_buf[WLC_IOCTL_SMLEN];
++	s32 err;
++
++	memset(iovar_buf, 0, sizeof(iovar_buf));
++	err = wldev_iovar_getbuf_bsscfg(dev, iovar, pval, sizeof(*pval), iovar_buf,
++		sizeof(iovar_buf), bssidx, NULL);
++	if (err == 0)
++	{
++		memcpy(pval, iovar_buf, sizeof(*pval));
++		*pval = dtoh32(*pval);
++	}
++	return err;
++}
++
++int wldev_get_link_speed(
++	struct net_device *dev, int *plink_speed)
++{
++	int error;
++
++	if (!plink_speed)
++		return -ENOMEM;
++	plink_speed = 0;
++	error = wldev_ioctl(dev, WLC_GET_RATE, plink_speed, sizeof(int), 0);
++	if (unlikely(error))
++		return error;
++
++	/* Convert internal 500Kbps to Kbps */
++	*plink_speed *= 500;
++	return error;
++}
++
++int wldev_get_rssi(
++	struct net_device *dev, scb_val_t *scb_val)
++{
++	int error;
++
++	if (!scb_val)
++		return -ENOMEM;
++
++	memset(scb_val, 0, sizeof(scb_val_t));
++	error = wldev_ioctl(dev, WLC_GET_RSSI, scb_val, sizeof(scb_val_t), 0);
++	if (unlikely(error))
++		return error;
++
++	return error;
++}
++
++int wldev_get_ssid(
++	struct net_device *dev, wlc_ssid_t *pssid)
++{
++	int error;
++
++	if (!pssid)
++		return -ENOMEM;
++
++	memset(pssid, 0, sizeof(wlc_ssid_t));
++	error = wldev_ioctl(dev, WLC_GET_SSID, pssid, sizeof(wlc_ssid_t), 0);
++	if (unlikely(error))
++		return error;
++	pssid->SSID_len = dtoh32(pssid->SSID_len);
++	return error;
++}
++
++int wldev_get_band(
++	struct net_device *dev, uint *pband)
++{
++	int error;
++
++	error = wldev_ioctl(dev, WLC_GET_BAND, pband, sizeof(uint), 0);
++	return error;
++}
++
++int wldev_set_band(
++	struct net_device *dev, uint band)
++{
++	int error = -1;
++
++	if ((band == WLC_BAND_AUTO) || (band == WLC_BAND_5G) || (band == WLC_BAND_2G)) {
++		error = wldev_ioctl(dev, WLC_SET_BAND, &band, sizeof(band), true);
++		if (!error)
++			dhd_bus_band_set(dev, band);
++	}
++	return error;
++}
++int wldev_get_datarate(struct net_device *dev, int *datarate)
++{
++	int error = 0;
++
++	error = wldev_ioctl(dev, WLC_GET_RATE, datarate, sizeof(int), false);
++	if (error) {
++		return -1;
++	} else {
++		*datarate = dtoh32(*datarate);
++	}
++
++	return error;
++}
++
++extern chanspec_t
++wl_chspec_driver_to_host(chanspec_t chanspec);
++#define WL_EXTRA_BUF_MAX 2048
++int wldev_get_mode(
++	struct net_device *dev, uint8 *cap)
++{
++	int error = 0;
++	int chanspec = 0;
++	uint16 band = 0;
++	uint16 bandwidth = 0;
++	wl_bss_info_t *bss = NULL;
++	char* buf = kzalloc(WL_EXTRA_BUF_MAX, GFP_KERNEL);
++	if (!buf) {
++		WLDEV_ERROR(("%s:NOMEM\n", __FUNCTION__));
++		return -ENOMEM;
++	}
++	*(u32*) buf = htod32(WL_EXTRA_BUF_MAX);
++	error = wldev_ioctl(dev, WLC_GET_BSS_INFO, (void*)buf, WL_EXTRA_BUF_MAX, false);
++	if (error) {
++		WLDEV_ERROR(("%s:failed:%d\n", __FUNCTION__, error));
++		kfree(buf);
++		buf = NULL;
++		return error;
++	}
++	bss = (struct  wl_bss_info *)(buf + 4);
++	chanspec = wl_chspec_driver_to_host(bss->chanspec);
++
++	band = chanspec & WL_CHANSPEC_BAND_MASK;
++	bandwidth = chanspec & WL_CHANSPEC_BW_MASK;
++
++	if (band == WL_CHANSPEC_BAND_2G) {
++		if (bss->n_cap)
++			strcpy(cap, "n");
++		else
++			strcpy(cap, "bg");
++	} else if (band == WL_CHANSPEC_BAND_5G) {
++		if (bandwidth == WL_CHANSPEC_BW_80)
++			strcpy(cap, "ac");
++		else if ((bandwidth == WL_CHANSPEC_BW_40) || (bandwidth == WL_CHANSPEC_BW_20)) {
++			if ((bss->nbss_cap & 0xf00) && (bss->n_cap))
++				strcpy(cap, "n|ac");
++			else if (bss->n_cap)
++				strcpy(cap, "n");
++			else if (bss->vht_cap)
++				strcpy(cap, "ac");
++			else
++				strcpy(cap, "a");
++		} else {
++			WLDEV_ERROR(("%s:Mode get failed\n", __FUNCTION__));
++			error = BCME_ERROR;
++		}
++
++	}
++	kfree(buf);
++	buf = NULL;
++	return error;
++}
++int wldev_set_country(
++	struct net_device *dev, char *country_code, bool notify, bool user_enforced, int revinfo)
++{
++	int error = -1;
++	wl_country_t cspec = {{0}, 0, {0}};
++	scb_val_t scbval;
++	char smbuf[WLC_IOCTL_SMLEN];
++
++	if (!country_code)
++		return error;
++
++	bzero(&scbval, sizeof(scb_val_t));
++	error = wldev_iovar_getbuf(dev, "country", NULL, 0, &cspec, sizeof(cspec), NULL);
++	if (error < 0) {
++		WLDEV_ERROR(("%s: get country failed = %d\n", __FUNCTION__, error));
++		return error;
++	}
++
++	if ((error < 0) ||
++			dhd_force_country_change(dev) ||
++	    (strncmp(country_code, cspec.country_abbrev, WLC_CNTRY_BUF_SZ) != 0)) {
++
++		if (user_enforced) {
++			bzero(&scbval, sizeof(scb_val_t));
++			error = wldev_ioctl(dev, WLC_DISASSOC, &scbval, sizeof(scb_val_t), true);
++			if (error < 0) {
++				WLDEV_ERROR(("%s: set country failed due to Disassoc error %d\n",
++					__FUNCTION__, error));
++				return error;
++			}
++		}
++
++		cspec.rev = revinfo;
++		memcpy(cspec.country_abbrev, country_code, WLC_CNTRY_BUF_SZ);
++		memcpy(cspec.ccode, country_code, WLC_CNTRY_BUF_SZ);
++		dhd_get_customized_country_code(dev, (char *)&cspec.country_abbrev, &cspec);
++		error = wldev_iovar_setbuf(dev, "country", &cspec, sizeof(cspec),
++			smbuf, sizeof(smbuf), NULL);
++		if (error < 0) {
++			WLDEV_ERROR(("%s: set country for %s as %s rev %d failed\n",
++				__FUNCTION__, country_code, cspec.ccode, cspec.rev));
++			return error;
++		}
++		dhd_bus_country_set(dev, &cspec, notify);
++		WLDEV_ERROR(("%s: set country for %s as %s rev %d\n",
++			__FUNCTION__, country_code, cspec.ccode, cspec.rev));
++	}
++	return 0;
++}
+diff --git a/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wldev_common.h b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wldev_common.h
+new file mode 100644
+index 000000000..4f0d70cbc
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/bcmdhd_1_363_125_17/wldev_common.h
+@@ -0,0 +1,123 @@
++/*
++ * Common function shared by Linux WEXT, cfg80211 and p2p drivers
++ *
++ * Copyright (C) 1999-2019, Broadcom Corporation
++ * 
++ *      Unless you and Broadcom execute a separate written software license
++ * agreement governing use of this software, this software is licensed to you
++ * under the terms of the GNU General Public License version 2 (the "GPL"),
++ * available at http://www.broadcom.com/licenses/GPLv2.php, with the
++ * following added to such license:
++ * 
++ *      As a special exception, the copyright holders of this software give you
++ * permission to link this software with independent modules, and to copy and
++ * distribute the resulting executable under terms of your choice, provided that
++ * you also meet, for each linked independent module, the terms and conditions of
++ * the license of that module.  An independent module is a module which is not
++ * derived from this software.  The special exception does not apply to any
++ * modifications of the software.
++ * 
++ *      Notwithstanding the above, under no circumstances may you combine this
++ * software in any way with any other Broadcom software provided under a license
++ * other than the GPL, without Broadcom's express prior written consent.
++ *
++ *
++ * <<Broadcom-WL-IPTag/Open:>>
++ *
++ * $Id: wldev_common.h 556083 2015-05-12 14:03:00Z $
++ */
++#ifndef __WLDEV_COMMON_H__
++#define __WLDEV_COMMON_H__
++
++#include <wlioctl.h>
++
++/* wl_dev_ioctl - get/set IOCTLs, will call net_device's do_ioctl (or
++ *  netdev_ops->ndo_do_ioctl in new kernels)
++ *  @dev: the net_device handle
++ */
++s32 wldev_ioctl(
++	struct net_device *dev, u32 cmd, void *arg, u32 len, u32 set);
++
++/** Retrieve named IOVARs, this function calls wl_dev_ioctl with
++ *  WLC_GET_VAR IOCTL code
++ */
++s32 wldev_iovar_getbuf(
++	struct net_device *dev, s8 *iovar_name,
++	void *param, s32 paramlen, void *buf, s32 buflen, struct mutex* buf_sync);
++
++/** Set named IOVARs, this function calls wl_dev_ioctl with
++ *  WLC_SET_VAR IOCTL code
++ */
++s32 wldev_iovar_setbuf(
++	struct net_device *dev, s8 *iovar_name,
++	void *param, s32 paramlen, void *buf, s32 buflen, struct mutex* buf_sync);
++
++s32 wldev_iovar_setint(
++	struct net_device *dev, s8 *iovar, s32 val);
++
++s32 wldev_iovar_getint(
++	struct net_device *dev, s8 *iovar, s32 *pval);
++
++/** The following function can be implemented if there is a need for bsscfg
++ *  indexed IOVARs
++ */
++
++s32 wldev_mkiovar_bsscfg(
++	const s8 *iovar_name, s8 *param, s32 paramlen,
++	s8 *iovar_buf, s32 buflen, s32 bssidx);
++
++/** Retrieve named and bsscfg indexed IOVARs, this function calls wl_dev_ioctl with
++ *  WLC_GET_VAR IOCTL code
++ */
++s32 wldev_iovar_getbuf_bsscfg(
++	struct net_device *dev, s8 *iovar_name, void *param, s32 paramlen,
++	void *buf, s32 buflen, s32 bsscfg_idx, struct mutex* buf_sync);
++
++/** Set named and bsscfg indexed IOVARs, this function calls wl_dev_ioctl with
++ *  WLC_SET_VAR IOCTL code
++ */
++s32 wldev_iovar_setbuf_bsscfg(
++	struct net_device *dev, s8 *iovar_name, void *param, s32 paramlen,
++	void *buf, s32 buflen, s32 bsscfg_idx, struct mutex* buf_sync);
++
++s32 wldev_iovar_getint_bsscfg(
++	struct net_device *dev, s8 *iovar, s32 *pval, s32 bssidx);
++
++s32 wldev_iovar_setint_bsscfg(
++	struct net_device *dev, s8 *iovar, s32 val, s32 bssidx);
++
++extern int dhd_net_set_fw_path(struct net_device *dev, char *fw);
++extern int dhd_net_bus_suspend(struct net_device *dev);
++extern int dhd_net_bus_resume(struct net_device *dev, uint8 stage);
++extern int dhd_net_wifi_platform_set_power(struct net_device *dev, bool on,
++	unsigned long delay_msec);
++extern void dhd_get_customized_country_code(struct net_device *dev, char *country_iso_code,
++	wl_country_t *cspec);
++extern void dhd_bus_country_set(struct net_device *dev, wl_country_t *cspec, bool notify);
++extern bool dhd_force_country_change(struct net_device *dev);
++extern void dhd_bus_band_set(struct net_device *dev, uint band);
++extern int wldev_set_country(struct net_device *dev, char *country_code, bool notify,
++	bool user_enforced, int revinfo);
++extern int net_os_wake_lock(struct net_device *dev);
++extern int net_os_wake_unlock(struct net_device *dev);
++extern int net_os_wake_lock_timeout(struct net_device *dev);
++extern int net_os_wake_lock_timeout_enable(struct net_device *dev, int val);
++extern int net_os_set_dtim_skip(struct net_device *dev, int val);
++extern int net_os_set_suspend_disable(struct net_device *dev, int val);
++extern int net_os_set_suspend(struct net_device *dev, int val, int force);
++extern int wl_iw_parse_ssid_list_tlv(char** list_str, wlc_ssid_ext_t* ssid,
++	int max, int *bytes_left);
++
++/* Get the link speed from dongle, speed is in kpbs */
++int wldev_get_link_speed(struct net_device *dev, int *plink_speed);
++
++int wldev_get_rssi(struct net_device *dev, scb_val_t *prssi);
++
++int wldev_get_ssid(struct net_device *dev, wlc_ssid_t *pssid);
++
++int wldev_get_band(struct net_device *dev, uint *pband);
++int wldev_get_mode(struct net_device *dev, uint8 *pband);
++int wldev_get_datarate(struct net_device *dev, int *datarate);
++int wldev_set_band(struct net_device *dev, uint band);
++
++#endif /* __WLDEV_COMMON_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/Makefile b/module_drivers/drivers/net/wireless/realtek/Makefile
+new file mode 100644
+index 000000000..c6e6e288b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/Makefile
+@@ -0,0 +1,4 @@
++#
++# Makefile for the Linux Wireless network device drivers for Realtek units
++#
++obj-$(CONFIG_RTL8723DS) += rtl8723ds/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/Kconfig b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/Kconfig
+new file mode 100644
+index 000000000..6ff2d6c2e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/Kconfig
+@@ -0,0 +1,4 @@
++config RTL8723DS
++	tristate "Realtek 8723D SDIO or SPI WiFi"
++	help
++	  Help message of RTL8723DS
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/Makefile b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/Makefile
+new file mode 100644
+index 000000000..d1a9de4e0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/Makefile
+@@ -0,0 +1,2439 @@
++EXTRA_CFLAGS += $(USER_EXTRA_CFLAGS)
++EXTRA_CFLAGS += -O1
++#EXTRA_CFLAGS += -O3
++#EXTRA_CFLAGS += -Wall
++#EXTRA_CFLAGS += -Wextra
++#EXTRA_CFLAGS += -Werror
++#EXTRA_CFLAGS += -pedantic
++#EXTRA_CFLAGS += -Wshadow -Wpointer-arith -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes
++
++EXTRA_CFLAGS += -Wno-unused-variable
++#EXTRA_CFLAGS += -Wno-unused-value
++#EXTRA_CFLAGS += -Wno-unused-label
++#EXTRA_CFLAGS += -Wno-unused-parameter
++#EXTRA_CFLAGS += -Wno-unused-function
++#EXTRA_CFLAGS += -Wno-unused
++#EXTRA_CFLAGS += -Wno-uninitialized
++
++GCC_VER_49 := $(shell echo `$(CC) -dumpversion | cut -f1-2 -d.` \>= 4.9 | bc )
++ifeq ($(GCC_VER_49),1)
++EXTRA_CFLAGS += -Wno-date-time	# Fix compile error && warning on gcc 4.9 and later
++endif
++
++EXTRA_CFLAGS += -I$(src)/include
++
++EXTRA_LDFLAGS += --strip-debug
++
++CONFIG_AUTOCFG_CP = n
++
++########################## WIFI IC ############################
++CONFIG_MULTIDRV = n
++CONFIG_RTL8188E = n
++CONFIG_RTL8812A = n
++CONFIG_RTL8821A = n
++CONFIG_RTL8192E = n
++CONFIG_RTL8723B = n
++CONFIG_RTL8814A = n
++CONFIG_RTL8723C = n
++CONFIG_RTL8188F = n
++CONFIG_RTL8188GTV = n
++CONFIG_RTL8822B = n
++CONFIG_RTL8723D = y
++CONFIG_RTL8821C = n
++CONFIG_RTL8710B = n
++CONFIG_RTL8192F = n
++CONFIG_RTL8822C = n
++CONFIG_RTL8814B = n
++######################### Interface ###########################
++CONFIG_USB_HCI = n
++CONFIG_PCI_HCI = n
++CONFIG_SDIO_HCI = y
++CONFIG_GSPI_HCI = n
++########################## Features ###########################
++CONFIG_MP_INCLUDED = y
++CONFIG_POWER_SAVING = n
++CONFIG_IPS_MODE = default
++CONFIG_LPS_MODE = default
++CONFIG_USB_AUTOSUSPEND = n
++CONFIG_HW_PWRP_DETECTION = n
++CONFIG_BT_COEXIST = y
++CONFIG_WAPI_SUPPORT = n
++CONFIG_EFUSE_CONFIG_FILE = y
++CONFIG_EXT_CLK = n
++CONFIG_TRAFFIC_PROTECT = n
++CONFIG_LOAD_PHY_PARA_FROM_FILE = y
++CONFIG_TXPWR_BY_RATE = y
++CONFIG_TXPWR_BY_RATE_EN = y
++CONFIG_TXPWR_LIMIT = y
++CONFIG_TXPWR_LIMIT_EN = n
++CONFIG_RTW_CHPLAN = 0xFF
++CONFIG_RTW_ADAPTIVITY_EN = disable
++CONFIG_RTW_ADAPTIVITY_MODE = normal
++CONFIG_SIGNAL_SCALE_MAPPING = n
++CONFIG_80211W = y
++CONFIG_REDUCE_TX_CPU_LOADING = n
++CONFIG_BR_EXT = y
++CONFIG_TDLS = n
++CONFIG_WIFI_MONITOR = n
++CONFIG_MCC_MODE = n
++CONFIG_APPEND_VENDOR_IE_ENABLE = y
++CONFIG_RTW_NAPI = y
++CONFIG_RTW_GRO = y
++CONFIG_RTW_NETIF_SG = y
++CONFIG_RTW_IPCAM_APPLICATION = n
++CONFIG_RTW_REPEATER_SON = n
++CONFIG_ICMP_VOQ = n
++CONFIG_IP_R_MONITOR = n #arp VOQ and high rate
++# user priority mapping rule : tos, dscp
++CONFIG_RTW_UP_MAPPING_RULE = tos
++CONFIG_RTW_MBO = n
++
++########################## Android ###########################
++# CONFIG_RTW_ANDROID - 0: no Android, 4/5/6/7/8/9/10 : Android version
++CONFIG_RTW_ANDROID = 0
++
++ifeq ($(shell test $(CONFIG_RTW_ANDROID) -gt 0; echo $$?), 0)
++EXTRA_CFLAGS += -DCONFIG_RTW_ANDROID=$(CONFIG_RTW_ANDROID)
++endif
++
++########################## Debug ###########################
++CONFIG_RTW_DEBUG = y
++# default log level is _DRV_INFO_ = 4,
++# please refer to "How_to_set_driver_debug_log_level.doc" to set the available level.
++CONFIG_RTW_LOG_LEVEL = 4
++
++# enable /proc/net/rtlxxxx/ debug interfaces
++CONFIG_PROC_DEBUG = y
++
++######################## Wake On Lan ##########################
++CONFIG_WOWLAN = n
++#bit2: deauth, bit1: unicast, bit0: magic pkt.
++CONFIG_WAKEUP_TYPE = 0x7
++CONFIG_WOW_LPS_MODE = default
++#bit0: disBBRF off, #bit1: Wireless remote controller (WRC)
++CONFIG_SUSPEND_TYPE = 0
++CONFIG_WOW_STA_MIX = n
++CONFIG_GPIO_WAKEUP = n
++# Please contact with RTK support team first. After getting the agreement from RTK support team, 
++# you are just able to modify the CONFIG_WAKEUP_GPIO_IDX with customized requirement.
++CONFIG_WAKEUP_GPIO_IDX = default
++CONFIG_HIGH_ACTIVE_DEV2HST = n
++######### only for USB #########
++CONFIG_ONE_PIN_GPIO = n
++CONFIG_HIGH_ACTIVE_HST2DEV = n
++CONFIG_PNO_SUPPORT = n
++CONFIG_PNO_SET_DEBUG = n
++CONFIG_AP_WOWLAN = n
++######### Notify SDIO Host Keep Power During Syspend ##########
++CONFIG_RTW_SDIO_PM_KEEP_POWER = y
++###################### MP HW TX MODE FOR VHT #######################
++CONFIG_MP_VHT_HW_TX_MODE = n
++###################### Platform Related #######################
++CONFIG_PLATFORM_I386_PC = n
++CONFIG_PLATFORM_ANDROID_X86 = n
++CONFIG_PLATFORM_ANDROID_INTEL_X86 = n
++CONFIG_PLATFORM_JB_X86 = n
++CONFIG_PLATFORM_ARM_S3C2K4 = n
++CONFIG_PLATFORM_ARM_PXA2XX = n
++CONFIG_PLATFORM_ARM_S3C6K4 = n
++CONFIG_PLATFORM_MIPS_RMI = n
++CONFIG_PLATFORM_RTD2880B = n
++CONFIG_PLATFORM_MIPS_AR9132 = n
++CONFIG_PLATFORM_RTK_DMP = n
++CONFIG_PLATFORM_MIPS_PLM = n
++CONFIG_PLATFORM_MSTAR389 = n
++CONFIG_PLATFORM_MT53XX = n
++CONFIG_PLATFORM_ARM_MX51_241H = n
++CONFIG_PLATFORM_FS_MX61 = n
++CONFIG_PLATFORM_ACTIONS_ATJ227X = n
++CONFIG_PLATFORM_TEGRA3_CARDHU = n
++CONFIG_PLATFORM_TEGRA4_DALMORE = n
++CONFIG_PLATFORM_ARM_TCC8900 = n
++CONFIG_PLATFORM_ARM_TCC8920 = n
++CONFIG_PLATFORM_ARM_TCC8920_JB42 = n
++CONFIG_PLATFORM_ARM_TCC8930_JB42 = n
++CONFIG_PLATFORM_ARM_RK2818 = n
++CONFIG_PLATFORM_ARM_RK3066 = n
++CONFIG_PLATFORM_ARM_RK3188 = n
++CONFIG_PLATFORM_ARM_URBETTER = n
++CONFIG_PLATFORM_ARM_TI_PANDA = n
++CONFIG_PLATFORM_MIPS_JZ4760 = n
++CONFIG_PLATFORM_MIPS_X2000 = y
++CONFIG_PLATFORM_DMP_PHILIPS = n
++CONFIG_PLATFORM_MSTAR_TITANIA12 = n
++CONFIG_PLATFORM_MSTAR = n
++CONFIG_PLATFORM_SZEBOOK = n
++CONFIG_PLATFORM_ARM_SUNxI = n
++CONFIG_PLATFORM_ARM_SUN6I = n
++CONFIG_PLATFORM_ARM_SUN7I = n
++CONFIG_PLATFORM_ARM_SUN8I_W3P1 = n
++CONFIG_PLATFORM_ARM_SUN8I_W5P1 = n
++CONFIG_PLATFORM_ACTIONS_ATM702X = n
++CONFIG_PLATFORM_ACTIONS_ATV5201 = n
++CONFIG_PLATFORM_ACTIONS_ATM705X = n
++CONFIG_PLATFORM_ARM_SUN50IW1P1 = n
++CONFIG_PLATFORM_ARM_RTD299X = n
++CONFIG_PLATFORM_ARM_LGE = n
++CONFIG_PLATFORM_ARM_SPREADTRUM_6820 = n
++CONFIG_PLATFORM_ARM_SPREADTRUM_8810 = n
++CONFIG_PLATFORM_ARM_WMT = n
++CONFIG_PLATFORM_TI_DM365 = n
++CONFIG_PLATFORM_MOZART = n
++CONFIG_PLATFORM_RTK119X = n
++CONFIG_PLATFORM_RTK119X_AM = n
++CONFIG_PLATFORM_RTK129X = n
++CONFIG_PLATFORM_RTK390X = n
++CONFIG_PLATFORM_NOVATEK_NT72668 = n
++CONFIG_PLATFORM_HISILICON = n
++CONFIG_PLATFORM_HISILICON_HI3798 = n
++CONFIG_PLATFORM_NV_TK1 = n
++CONFIG_PLATFORM_NV_TK1_UBUNTU = n
++CONFIG_PLATFORM_RTL8197D = n
++CONFIG_PLATFORM_AML_S905 = n
++CONFIG_PLATFORM_ZTE_ZX296716 = n
++########### CUSTOMER ################################
++CONFIG_CUSTOMER_HUAWEI_GENERAL = n
++
++CONFIG_DRVEXT_MODULE = n
++
++export TopDIR ?= $(shell pwd)
++
++########### COMMON  #################################
++ifeq ($(CONFIG_GSPI_HCI), y)
++HCI_NAME = gspi
++endif
++
++ifeq ($(CONFIG_SDIO_HCI), y)
++HCI_NAME = sdio
++endif
++
++ifeq ($(CONFIG_USB_HCI), y)
++HCI_NAME = usb
++endif
++
++ifeq ($(CONFIG_PCI_HCI), y)
++HCI_NAME = pci
++endif
++
++
++_OS_INTFS_FILES :=	os_dep/osdep_service.o \
++			os_dep/linux/os_intfs.o \
++			os_dep/linux/$(HCI_NAME)_intf.o \
++			os_dep/linux/$(HCI_NAME)_ops_linux.o \
++			os_dep/linux/ioctl_linux.o \
++			os_dep/linux/xmit_linux.o \
++			os_dep/linux/mlme_linux.o \
++			os_dep/linux/recv_linux.o \
++			os_dep/linux/ioctl_cfg80211.o \
++			os_dep/linux/rtw_cfgvendor.o \
++			os_dep/linux/wifi_regd.o \
++			os_dep/linux/rtw_android.o \
++			os_dep/linux/rtw_proc.o \
++			os_dep/linux/rtw_rhashtable.o
++
++ifeq ($(CONFIG_MP_INCLUDED), y)
++_OS_INTFS_FILES += os_dep/linux/ioctl_mp.o
++endif
++
++ifeq ($(CONFIG_SDIO_HCI), y)
++_OS_INTFS_FILES += os_dep/linux/custom_gpio_linux.o
++_OS_INTFS_FILES += os_dep/linux/$(HCI_NAME)_ops_linux.o
++endif
++
++ifeq ($(CONFIG_GSPI_HCI), y)
++_OS_INTFS_FILES += os_dep/linux/custom_gpio_linux.o
++_OS_INTFS_FILES += os_dep/linux/$(HCI_NAME)_ops_linux.o
++endif
++
++
++_HAL_INTFS_FILES :=	hal/hal_intf.o \
++			hal/hal_com.o \
++			hal/hal_com_phycfg.o \
++			hal/hal_phy.o \
++			hal/hal_dm.o \
++			hal/hal_dm_acs.o \
++			hal/hal_btcoex_wifionly.o \
++			hal/hal_btcoex.o \
++			hal/hal_mp.o \
++			hal/hal_mcc.o \
++			hal/hal_hci/hal_$(HCI_NAME).o \
++			hal/led/hal_led.o \
++			hal/led/hal_$(HCI_NAME)_led.o
++
++
++EXTRA_CFLAGS += -I$(src)/platform
++_PLATFORM_FILES := platform/platform_ops.o
++
++EXTRA_CFLAGS += -I$(src)/hal/btc
++
++########### HAL_RTL8188E #################################
++ifeq ($(CONFIG_RTL8188E), y)
++
++RTL871X = rtl8188e
++ifeq ($(CONFIG_SDIO_HCI), y)
++MODULE_NAME = 8189es
++endif
++
++ifeq ($(CONFIG_GSPI_HCI), y)
++MODULE_NAME = 8189es
++endif
++
++ifeq ($(CONFIG_USB_HCI), y)
++MODULE_NAME = 8188eu
++endif
++
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME = 8188ee
++endif
++EXTRA_CFLAGS += -DCONFIG_RTL8188E
++
++_HAL_INTFS_FILES +=	hal/HalPwrSeqCmd.o \
++					hal/$(RTL871X)/Hal8188EPwrSeq.o\
++ 					hal/$(RTL871X)/$(RTL871X)_xmit.o\
++					hal/$(RTL871X)/$(RTL871X)_sreset.o
++
++_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
++			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
++			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
++			hal/$(RTL871X)/$(RTL871X)_dm.o \
++			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
++			hal/$(RTL871X)/$(RTL871X)_cmd.o \
++			hal/$(RTL871X)/hal8188e_s_fw.o \
++			hal/$(RTL871X)/hal8188e_t_fw.o \
++			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
++
++ifeq ($(CONFIG_SDIO_HCI), y)
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
++else
++ifeq ($(CONFIG_GSPI_HCI), y)
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
++else
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
++endif
++endif
++
++ifeq ($(CONFIG_USB_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_USB.o
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_PCIE.o
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_SDIO.o
++endif
++
++endif
++
++########### HAL_RTL8192E #################################
++ifeq ($(CONFIG_RTL8192E), y)
++
++RTL871X = rtl8192e
++ifeq ($(CONFIG_SDIO_HCI), y)
++MODULE_NAME = 8192es
++endif
++
++ifeq ($(CONFIG_USB_HCI), y)
++MODULE_NAME = 8192eu
++endif
++
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME = 8192ee
++endif
++EXTRA_CFLAGS += -DCONFIG_RTL8192E
++_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
++					hal/$(RTL871X)/Hal8192EPwrSeq.o\
++					hal/$(RTL871X)/$(RTL871X)_xmit.o\
++					hal/$(RTL871X)/$(RTL871X)_sreset.o
++
++_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
++			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
++			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
++			hal/$(RTL871X)/$(RTL871X)_dm.o \
++			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
++			hal/$(RTL871X)/$(RTL871X)_cmd.o \
++			hal/$(RTL871X)/hal8192e_fw.o \
++			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
++
++ifeq ($(CONFIG_SDIO_HCI), y)
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
++else
++ifeq ($(CONFIG_GSPI_HCI), y)
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
++else
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
++endif
++endif
++
++ifeq ($(CONFIG_USB_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_USB.o
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_PCIE.o
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_SDIO.o
++endif
++
++ifeq ($(CONFIG_BT_COEXIST), y)
++_BTC_FILES += hal/btc/halbtc8192e1ant.o \
++				hal/btc/halbtc8192e2ant.o
++endif
++
++endif
++
++########### HAL_RTL8812A_RTL8821A #################################
++
++ifneq ($(CONFIG_RTL8812A)_$(CONFIG_RTL8821A), n_n)
++
++RTL871X = rtl8812a
++ifeq ($(CONFIG_USB_HCI), y)
++MODULE_NAME = 8812au
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME = 8812ae
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++MODULE_NAME = 8812as
++endif
++
++_HAL_INTFS_FILES +=  hal/HalPwrSeqCmd.o \
++					hal/$(RTL871X)/Hal8812PwrSeq.o \
++					hal/$(RTL871X)/Hal8821APwrSeq.o\
++					hal/$(RTL871X)/$(RTL871X)_xmit.o\
++					hal/$(RTL871X)/$(RTL871X)_sreset.o
++
++_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
++			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
++			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
++			hal/$(RTL871X)/$(RTL871X)_dm.o \
++			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
++			hal/$(RTL871X)/$(RTL871X)_cmd.o \
++			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
++
++ifeq ($(CONFIG_SDIO_HCI), y)
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
++else
++ifeq ($(CONFIG_GSPI_HCI), y)
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
++else
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
++endif
++endif
++
++ifeq ($(CONFIG_RTL8812A), y)
++ifeq ($(CONFIG_USB_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8812A_USB.o
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8812A_PCIE.o
++endif
++endif
++ifeq ($(CONFIG_RTL8821A), y)
++ifeq ($(CONFIG_USB_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_USB.o
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_PCIE.o
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_SDIO.o
++endif
++endif
++
++ifeq ($(CONFIG_RTL8812A), y)
++EXTRA_CFLAGS += -DCONFIG_RTL8812A
++_HAL_INTFS_FILES +=	hal/rtl8812a/hal8812a_fw.o
++endif
++
++ifeq ($(CONFIG_RTL8821A), y)
++
++ifeq ($(CONFIG_RTL8812A), n)
++
++RTL871X = rtl8821a
++ifeq ($(CONFIG_USB_HCI), y)
++ifeq ($(CONFIG_BT_COEXIST), y)
++MODULE_NAME := 8821au
++else
++MODULE_NAME := 8811au
++endif
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME := 8821ae
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++MODULE_NAME := 8821as
++endif
++
++endif
++
++EXTRA_CFLAGS += -DCONFIG_RTL8821A
++
++_HAL_INTFS_FILES +=	hal/rtl8812a/hal8821a_fw.o
++		
++endif
++
++ifeq ($(CONFIG_BT_COEXIST), y)
++ifeq ($(CONFIG_RTL8812A), y)
++_BTC_FILES += hal/btc/halbtc8812a1ant.o \
++				hal/btc/halbtc8812a2ant.o
++endif
++ifeq ($(CONFIG_RTL8821A), y)
++_BTC_FILES += hal/btc/halbtc8821a1ant.o \
++				hal/btc/halbtc8821a2ant.o
++endif
++endif
++
++endif
++
++########### HAL_RTL8723B #################################
++ifeq ($(CONFIG_RTL8723B), y)
++
++RTL871X = rtl8723b
++ifeq ($(CONFIG_USB_HCI), y)
++MODULE_NAME = 8723bu
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME = 8723be
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++MODULE_NAME = 8723bs
++endif
++
++EXTRA_CFLAGS += -DCONFIG_RTL8723B
++
++_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
++					hal/$(RTL871X)/Hal8723BPwrSeq.o\
++					hal/$(RTL871X)/$(RTL871X)_sreset.o
++
++_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
++			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
++			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
++			hal/$(RTL871X)/$(RTL871X)_dm.o \
++			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
++			hal/$(RTL871X)/$(RTL871X)_cmd.o \
++			hal/$(RTL871X)/hal8723b_fw.o
++
++_HAL_INTFS_FILES +=	\
++			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
++
++ifeq ($(CONFIG_PCI_HCI), y)
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
++else
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
++endif
++
++ifeq ($(CONFIG_USB_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_USB.o
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_PCIE.o
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_SDIO.o
++endif
++
++_BTC_FILES += hal/btc/halbtc8723bwifionly.o
++ifeq ($(CONFIG_BT_COEXIST), y)
++_BTC_FILES += hal/btc/halbtc8723b1ant.o \
++				hal/btc/halbtc8723b2ant.o
++endif
++
++endif
++
++########### HAL_RTL8814A #################################
++ifeq ($(CONFIG_RTL8814A), y)
++## ADD NEW VHT MP HW TX MODE ##
++#EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE
++#CONFIG_MP_VHT_HW_TX_MODE = y
++##########################################
++RTL871X = rtl8814a
++ifeq ($(CONFIG_USB_HCI), y)
++MODULE_NAME = 8814au
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME = 8814ae
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++MODULE_NAME = 8814as
++endif
++
++EXTRA_CFLAGS += -DCONFIG_RTL8814A
++
++_HAL_INTFS_FILES +=  hal/HalPwrSeqCmd.o \
++					hal/$(RTL871X)/Hal8814PwrSeq.o \
++					hal/$(RTL871X)/$(RTL871X)_xmit.o\
++					hal/$(RTL871X)/$(RTL871X)_sreset.o
++
++_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
++			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
++			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
++			hal/$(RTL871X)/$(RTL871X)_dm.o \
++			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
++			hal/$(RTL871X)/$(RTL871X)_cmd.o \
++			hal/$(RTL871X)/hal8814a_fw.o
++
++
++_HAL_INTFS_FILES +=	\
++			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
++
++ifeq ($(CONFIG_SDIO_HCI), y)
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
++else
++ifeq ($(CONFIG_GSPI_HCI), y)
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
++else
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
++endif
++endif
++
++ifeq ($(CONFIG_USB_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8814A_USB.o
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8814A_PCIE.o
++endif
++
++ifeq ($(CONFIG_BT_COEXIST), y)
++_BTC_FILES += hal/btc/halbtc8814a2ant.o
++endif
++endif
++
++########### HAL_RTL8723C #################################
++ifeq ($(CONFIG_RTL8723C), y)
++
++RTL871X = rtl8703b
++ifeq ($(CONFIG_USB_HCI), y)
++MODULE_NAME = 8723cu
++MODULE_SUB_NAME = 8703bu
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME = 8723ce
++MODULE_SUB_NAME = 8703be
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++MODULE_NAME = 8723cs
++MODULE_SUB_NAME = 8703bs
++endif
++
++EXTRA_CFLAGS += -DCONFIG_RTL8703B
++
++_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
++					hal/$(RTL871X)/Hal8703BPwrSeq.o\
++					hal/$(RTL871X)/$(RTL871X)_sreset.o
++
++_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
++			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
++			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
++			hal/$(RTL871X)/$(RTL871X)_dm.o \
++			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
++			hal/$(RTL871X)/$(RTL871X)_cmd.o \
++			hal/$(RTL871X)/hal8703b_fw.o
++
++_HAL_INTFS_FILES +=	\
++			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o
++
++ifeq ($(CONFIG_PCI_HCI), y)
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
++else
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
++endif
++
++ifeq ($(CONFIG_USB_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8703B_USB.o
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8703B_PCIE.o
++endif
++
++ifeq ($(CONFIG_BT_COEXIST), y)
++_BTC_FILES += hal/btc/halbtc8703b1ant.o
++endif
++
++endif
++
++########### HAL_RTL8723D #################################
++ifeq ($(CONFIG_RTL8723D), y)
++
++RTL871X = rtl8723d
++ifeq ($(CONFIG_USB_HCI), y)
++MODULE_NAME = 8723du
++MODULE_SUB_NAME = 8723du
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME = 8723de
++MODULE_SUB_NAME = 8723de
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++MODULE_NAME = 8723ds
++MODULE_SUB_NAME = 8723ds
++endif
++
++EXTRA_CFLAGS += -DCONFIG_RTL8723D
++
++_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
++					hal/$(RTL871X)/Hal8723DPwrSeq.o\
++					hal/$(RTL871X)/$(RTL871X)_sreset.o
++
++_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
++			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
++			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
++			hal/$(RTL871X)/$(RTL871X)_dm.o \
++			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
++			hal/$(RTL871X)/$(RTL871X)_cmd.o \
++			hal/$(RTL871X)/hal8723d_fw.o \
++			hal/$(RTL871X)/$(RTL871X)_lps_poff.o
++
++
++_HAL_INTFS_FILES +=	\
++			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o
++
++ifeq ($(CONFIG_PCI_HCI), y)
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
++else
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
++endif
++
++ifeq ($(CONFIG_USB_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723D_USB.o
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723D_PCIE.o
++endif
++
++ifeq ($(CONFIG_BT_COEXIST), y)
++_BTC_FILES += hal/btc/halbtc8723d1ant.o \
++				hal/btc/halbtc8723d2ant.o
++endif
++
++endif
++
++########### HAL_RTL8188F #################################
++ifeq ($(CONFIG_RTL8188F), y)
++
++RTL871X = rtl8188f
++ifeq ($(CONFIG_USB_HCI), y)
++MODULE_NAME = 8188fu
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME = 8188fe
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++MODULE_NAME = 8189fs
++endif
++
++EXTRA_CFLAGS += -DCONFIG_RTL8188F
++
++_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
++					hal/$(RTL871X)/Hal8188FPwrSeq.o\
++					hal/$(RTL871X)/$(RTL871X)_sreset.o
++
++_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
++			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
++			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
++			hal/$(RTL871X)/$(RTL871X)_dm.o \
++			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
++			hal/$(RTL871X)/$(RTL871X)_cmd.o \
++			hal/$(RTL871X)/hal8188f_fw.o
++
++_HAL_INTFS_FILES +=	\
++			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
++
++ifeq ($(CONFIG_PCI_HCI), y)
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
++else
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
++endif
++
++ifeq ($(CONFIG_USB_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188F_USB.o
++endif
++
++ifeq ($(CONFIG_SDIO_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188F_SDIO.o
++endif
++
++endif
++
++########### HAL_RTL8188GTV #################################
++ifeq ($(CONFIG_RTL8188GTV), y)
++
++RTL871X = rtl8188gtv
++ifeq ($(CONFIG_USB_HCI), y)
++MODULE_NAME = 8188gtvu
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++MODULE_NAME = 8189gtvs
++endif
++
++EXTRA_CFLAGS += -DCONFIG_RTL8188GTV
++
++_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
++					hal/$(RTL871X)/Hal8188GTVPwrSeq.o\
++					hal/$(RTL871X)/$(RTL871X)_sreset.o
++
++_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
++			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
++			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
++			hal/$(RTL871X)/$(RTL871X)_dm.o \
++			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
++			hal/$(RTL871X)/$(RTL871X)_cmd.o \
++			hal/$(RTL871X)/hal8188gtv_fw.o
++
++_HAL_INTFS_FILES +=	\
++			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
++
++ifeq ($(CONFIG_PCI_HCI), y)
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
++else
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
++endif
++
++ifeq ($(CONFIG_USB_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188GTV_USB.o
++endif
++
++ifeq ($(CONFIG_SDIO_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188GTV_SDIO.o
++endif
++
++endif
++
++########### HAL_RTL8822B #################################
++ifeq ($(CONFIG_RTL8822B), y)
++RTL871X := rtl8822b
++ifeq ($(CONFIG_USB_HCI), y)
++ifeq ($(CONFIG_BT_COEXIST), n)
++MODULE_NAME = 8812bu
++else
++MODULE_NAME = 88x2bu
++endif
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME = 88x2be
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++MODULE_NAME = 88x2bs
++endif
++
++endif
++########### HAL_RTL8821C #################################
++ifeq ($(CONFIG_RTL8821C), y)
++RTL871X := rtl8821c
++ifeq ($(CONFIG_USB_HCI), y)
++MODULE_NAME = 8821cu
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME = 8821ce
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++MODULE_NAME = 8821cs
++endif
++
++endif
++
++########### HAL_RTL8710B #################################
++ifeq ($(CONFIG_RTL8710B), y)
++
++RTL871X = rtl8710b
++ifeq ($(CONFIG_USB_HCI), y)
++MODULE_NAME = 8710bu
++MODULE_SUB_NAME = 8710bu
++endif
++
++EXTRA_CFLAGS += -DCONFIG_RTL8710B
++
++_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
++					hal/$(RTL871X)/Hal8710BPwrSeq.o\
++					hal/$(RTL871X)/$(RTL871X)_sreset.o
++
++_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
++			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
++			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
++			hal/$(RTL871X)/$(RTL871X)_dm.o \
++			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
++			hal/$(RTL871X)/$(RTL871X)_cmd.o \
++			hal/$(RTL871X)/hal8710b_fw.o \
++			hal/$(RTL871X)/$(RTL871X)_lps_poff.o
++
++
++_HAL_INTFS_FILES +=	\
++			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o
++
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
++
++ifeq ($(CONFIG_USB_HCI), y)
++_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8710B_USB.o
++endif
++
++endif
++
++########### HAL_RTL8192F #################################
++ifeq ($(CONFIG_RTL8192F), y)
++
++RTL871X = rtl8192f
++ifeq ($(CONFIG_USB_HCI), y)
++MODULE_NAME = 8192fu
++MODULE_SUB_NAME = 8192fu
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME = 8192fe
++MODULE_SUB_NAME = 8192fe
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++MODULE_NAME = 8192fs
++MODULE_SUB_NAME = 8192fs
++endif
++
++EXTRA_CFLAGS += -DCONFIG_RTL8192F
++
++_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
++					hal/$(RTL871X)/Hal8192FPwrSeq.o\
++					hal/$(RTL871X)/$(RTL871X)_sreset.o
++
++_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
++			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
++			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
++			hal/$(RTL871X)/$(RTL871X)_dm.o \
++			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
++			hal/$(RTL871X)/$(RTL871X)_cmd.o \
++			hal/$(RTL871X)/hal8192f_fw.o \
++			hal/$(RTL871X)/$(RTL871X)_lps_poff.o
++
++
++_HAL_INTFS_FILES +=	\
++			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \
++			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o
++			
++ifeq ($(CONFIG_PCI_HCI), y)
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
++else
++_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
++endif
++
++ifeq ($(CONFIG_SDIO_HCI), y)
++_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_SDIO.o
++endif
++
++ifeq ($(CONFIG_USB_HCI), y)
++_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_USB.o
++endif
++
++ifeq ($(CONFIG_PCI_HCI), y)
++_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_PCIE.o
++endif
++
++ifeq ($(CONFIG_BT_COEXIST), y)
++_BTC_FILES += hal/btc/halbtccommon.o \
++				hal/btc/halbtc8192f.o
++endif
++
++endif
++
++########### HAL_RTL8822C #################################
++ifeq ($(CONFIG_RTL8822C), y)
++RTL871X := rtl8822c
++ifeq ($(CONFIG_USB_HCI), y)
++ifeq ($(CONFIG_BT_COEXIST), n)
++MODULE_NAME = 8812cu
++else
++MODULE_NAME = 88x2cu
++endif
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME = 88x2ce
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++MODULE_NAME = 88x2cs
++endif
++
++endif
++
++########### HAL_RTL8814B #################################
++ifeq ($(CONFIG_RTL8814B), y)
++RTL871X := rtl8814b
++ifeq ($(CONFIG_USB_HCI), y)
++MODULE_NAME = 8814bu
++endif
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME = 8814be
++endif
++
++endif
++
++########### AUTO_CFG  #################################
++
++ifeq ($(CONFIG_AUTOCFG_CP), y)
++
++ifeq ($(CONFIG_MULTIDRV), y)
++$(shell cp $(TopDIR)/autoconf_multidrv_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
++else
++ifeq ($(CONFIG_RTL8188E)$(CONFIG_SDIO_HCI),yy)
++$(shell cp $(TopDIR)/autoconf_rtl8189e_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
++else ifeq ($(CONFIG_RTL8188F)$(CONFIG_SDIO_HCI),yy)
++$(shell cp $(TopDIR)/autoconf_rtl8189f_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
++else ifeq ($(CONFIG_RTL8723C),y)
++$(shell cp $(TopDIR)/autoconf_rtl8723c_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
++else
++$(shell cp $(TopDIR)/autoconf_$(RTL871X)_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
++endif
++endif
++
++endif
++
++########### END OF PATH  #################################
++
++ifeq ($(CONFIG_USB_HCI), y)
++ifeq ($(CONFIG_USB_AUTOSUSPEND), y)
++EXTRA_CFLAGS += -DCONFIG_USB_AUTOSUSPEND
++endif
++endif
++
++ifeq ($(CONFIG_MP_INCLUDED), y)
++#MODULE_NAME := $(MODULE_NAME)_mp
++EXTRA_CFLAGS += -DCONFIG_MP_INCLUDED
++endif
++
++ifeq ($(CONFIG_POWER_SAVING), y)
++ifneq ($(CONFIG_IPS_MODE), default)
++EXTRA_CFLAGS += -DRTW_IPS_MODE=$(CONFIG_IPS_MODE)
++endif
++ifneq ($(CONFIG_LPS_MODE), default)
++EXTRA_CFLAGS += -DRTW_LPS_MODE=$(CONFIG_LPS_MODE)
++endif
++ifneq ($(CONFIG_WOW_LPS_MODE), default)
++EXTRA_CFLAGS += -DRTW_WOW_LPS_MODE=$(CONFIG_WOW_LPS_MODE)
++endif
++EXTRA_CFLAGS += -DCONFIG_POWER_SAVING
++endif
++
++ifeq ($(CONFIG_HW_PWRP_DETECTION), y)
++EXTRA_CFLAGS += -DCONFIG_HW_PWRP_DETECTION
++endif
++
++ifeq ($(CONFIG_BT_COEXIST), y)
++EXTRA_CFLAGS += -DCONFIG_BT_COEXIST
++endif
++
++ifeq ($(CONFIG_WAPI_SUPPORT), y)
++EXTRA_CFLAGS += -DCONFIG_WAPI_SUPPORT
++endif
++
++
++ifeq ($(CONFIG_EFUSE_CONFIG_FILE), y)
++EXTRA_CFLAGS += -DCONFIG_EFUSE_CONFIG_FILE
++
++#EFUSE_MAP_PATH
++USER_EFUSE_MAP_PATH ?=
++ifneq ($(USER_EFUSE_MAP_PATH),)
++EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"$(USER_EFUSE_MAP_PATH)\"
++else ifeq ($(MODULE_NAME), 8189es)
++EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"/system/etc/wifi/wifi_efuse_8189e.map\"
++else ifeq ($(MODULE_NAME), 8723bs)
++EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"/system/etc/wifi/wifi_efuse_8723bs.map\"
++else
++EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"/system/etc/wifi/wifi_efuse_$(MODULE_NAME).map\"
++endif
++
++#WIFIMAC_PATH
++USER_WIFIMAC_PATH ?=
++ifneq ($(USER_WIFIMAC_PATH),)
++EXTRA_CFLAGS += -DWIFIMAC_PATH=\"$(USER_WIFIMAC_PATH)\"
++else
++EXTRA_CFLAGS += -DWIFIMAC_PATH=\"/data/wifimac.txt\"
++endif
++
++endif
++
++ifeq ($(CONFIG_EXT_CLK), y)
++EXTRA_CFLAGS += -DCONFIG_EXT_CLK
++endif
++
++ifeq ($(CONFIG_TRAFFIC_PROTECT), y)
++EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
++endif
++
++ifeq ($(CONFIG_LOAD_PHY_PARA_FROM_FILE), y)
++EXTRA_CFLAGS += -DCONFIG_LOAD_PHY_PARA_FROM_FILE
++#EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER
++EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"/lib/firmware/\"
++endif
++
++ifeq ($(CONFIG_TXPWR_BY_RATE), n)
++EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE=0
++else ifeq ($(CONFIG_TXPWR_BY_RATE), y)
++EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE=1
++endif
++ifeq ($(CONFIG_TXPWR_BY_RATE_EN), n)
++EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=0
++else ifeq ($(CONFIG_TXPWR_BY_RATE_EN), y)
++EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=1
++else ifeq ($(CONFIG_TXPWR_BY_RATE_EN), auto)
++EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=2
++endif
++
++ifeq ($(CONFIG_TXPWR_LIMIT), n)
++EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT=0
++else ifeq ($(CONFIG_TXPWR_LIMIT), y)
++EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT=1
++endif
++ifeq ($(CONFIG_TXPWR_LIMIT_EN), n)
++EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=0
++else ifeq ($(CONFIG_TXPWR_LIMIT_EN), y)
++EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=1
++else ifeq ($(CONFIG_TXPWR_LIMIT_EN), auto)
++EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=2
++endif
++
++ifneq ($(CONFIG_RTW_CHPLAN), 0xFF)
++EXTRA_CFLAGS += -DCONFIG_RTW_CHPLAN=$(CONFIG_RTW_CHPLAN)
++endif
++
++ifeq ($(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY), y)
++EXTRA_CFLAGS += -DCONFIG_CALIBRATE_TX_POWER_BY_REGULATORY
++endif
++
++ifeq ($(CONFIG_CALIBRATE_TX_POWER_TO_MAX), y)
++EXTRA_CFLAGS += -DCONFIG_CALIBRATE_TX_POWER_TO_MAX
++endif
++
++ifeq ($(CONFIG_RTW_ADAPTIVITY_EN), disable)
++EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_EN=0
++else ifeq ($(CONFIG_RTW_ADAPTIVITY_EN), enable)
++EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_EN=1
++endif
++
++ifeq ($(CONFIG_RTW_ADAPTIVITY_MODE), normal)
++EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_MODE=0
++else ifeq ($(CONFIG_RTW_ADAPTIVITY_MODE), carrier_sense)
++EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_MODE=1
++endif
++
++ifeq ($(CONFIG_SIGNAL_SCALE_MAPPING), y)
++EXTRA_CFLAGS += -DCONFIG_SIGNAL_SCALE_MAPPING
++endif
++
++ifeq ($(CONFIG_80211W), y)
++EXTRA_CFLAGS += -DCONFIG_IEEE80211W
++endif
++
++ifeq ($(CONFIG_WOWLAN), y)
++EXTRA_CFLAGS += -DCONFIG_WOWLAN -DRTW_WAKEUP_EVENT=$(CONFIG_WAKEUP_TYPE)
++EXTRA_CFLAGS += -DRTW_SUSPEND_TYPE=$(CONFIG_SUSPEND_TYPE)
++ifeq ($(CONFIG_WOW_STA_MIX), y)
++EXTRA_CFLAGS += -DRTW_WOW_STA_MIX
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER
++endif
++endif
++
++ifeq ($(CONFIG_AP_WOWLAN), y)
++EXTRA_CFLAGS += -DCONFIG_AP_WOWLAN
++ifeq ($(CONFIG_SDIO_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER
++endif
++endif
++
++ifeq ($(CONFIG_PNO_SUPPORT), y)
++EXTRA_CFLAGS += -DCONFIG_PNO_SUPPORT
++ifeq ($(CONFIG_PNO_SET_DEBUG), y)
++EXTRA_CFLAGS += -DCONFIG_PNO_SET_DEBUG
++endif
++endif
++
++ifeq ($(CONFIG_GPIO_WAKEUP), y)
++EXTRA_CFLAGS += -DCONFIG_GPIO_WAKEUP
++ifeq ($(CONFIG_ONE_PIN_GPIO), y)
++EXTRA_CFLAGS += -DCONFIG_RTW_ONE_PIN_GPIO
++endif
++ifeq ($(CONFIG_HIGH_ACTIVE_DEV2HST), y)
++EXTRA_CFLAGS += -DHIGH_ACTIVE_DEV2HST=1
++else
++EXTRA_CFLAGS += -DHIGH_ACTIVE_DEV2HST=0
++endif
++endif
++
++ifeq ($(CONFIG_HIGH_ACTIVE_HST2DEV), y)
++EXTRA_CFLAGS += -DHIGH_ACTIVE_HST2DEV=1
++else
++EXTRA_CFLAGS += -DHIGH_ACTIVE_HST2DEV=0
++endif
++
++ifneq ($(CONFIG_WAKEUP_GPIO_IDX), default)
++EXTRA_CFLAGS += -DWAKEUP_GPIO_IDX=$(CONFIG_WAKEUP_GPIO_IDX)
++endif
++
++ifeq ($(CONFIG_RTW_SDIO_PM_KEEP_POWER), y)
++ifeq ($(CONFIG_SDIO_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER
++endif
++endif
++
++ifeq ($(CONFIG_REDUCE_TX_CPU_LOADING), y)
++EXTRA_CFLAGS += -DCONFIG_REDUCE_TX_CPU_LOADING
++endif
++
++ifeq ($(CONFIG_BR_EXT), y)
++BR_NAME = br0
++EXTRA_CFLAGS += -DCONFIG_BR_EXT
++EXTRA_CFLAGS += '-DCONFIG_BR_EXT_BRNAME="'$(BR_NAME)'"'
++endif
++
++
++ifeq ($(CONFIG_TDLS), y)
++EXTRA_CFLAGS += -DCONFIG_TDLS
++endif
++
++ifeq ($(CONFIG_WIFI_MONITOR), y)
++EXTRA_CFLAGS += -DCONFIG_WIFI_MONITOR
++endif
++
++ifeq ($(CONFIG_MCC_MODE), y)
++EXTRA_CFLAGS += -DCONFIG_MCC_MODE
++endif
++
++ifeq ($(CONFIG_RTW_NAPI), y)
++EXTRA_CFLAGS += -DCONFIG_RTW_NAPI
++endif
++
++ifeq ($(CONFIG_RTW_GRO), y)
++EXTRA_CFLAGS += -DCONFIG_RTW_GRO
++endif
++
++ifeq ($(CONFIG_RTW_REPEATER_SON), y)
++EXTRA_CFLAGS += -DCONFIG_RTW_REPEATER_SON
++endif
++
++ifeq ($(CONFIG_RTW_IPCAM_APPLICATION), y)
++EXTRA_CFLAGS += -DCONFIG_RTW_IPCAM_APPLICATION
++ifeq ($(CONFIG_WIFI_MONITOR), n)
++EXTRA_CFLAGS += -DCONFIG_WIFI_MONITOR
++endif
++endif
++
++ifeq ($(CONFIG_RTW_NETIF_SG), y)
++EXTRA_CFLAGS += -DCONFIG_RTW_NETIF_SG
++endif
++
++ifeq ($(CONFIG_ICMP_VOQ), y)
++EXTRA_CFLAGS += -DCONFIG_ICMP_VOQ
++endif
++
++ifeq ($(CONFIG_IP_R_MONITOR), y)
++EXTRA_CFLAGS += -DCONFIG_IP_R_MONITOR
++endif
++
++ifeq ($(CONFIG_MP_VHT_HW_TX_MODE), y)
++EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE
++ifeq ($(CONFIG_PLATFORM_I386_PC), y)
++## For I386 X86 ToolChain use Hardware FLOATING
++EXTRA_CFLAGS += -mhard-float
++else
++## For ARM ToolChain use Hardware FLOATING
++EXTRA_CFLAGS += -mfloat-abi=hard
++endif
++endif
++
++ifeq ($(CONFIG_APPEND_VENDOR_IE_ENABLE), y)
++EXTRA_CFLAGS += -DCONFIG_APPEND_VENDOR_IE_ENABLE
++endif
++
++ifeq ($(CONFIG_RTW_DEBUG), y)
++EXTRA_CFLAGS += -DCONFIG_RTW_DEBUG
++EXTRA_CFLAGS += -DRTW_LOG_LEVEL=$(CONFIG_RTW_LOG_LEVEL)
++endif
++
++ifeq ($(CONFIG_PROC_DEBUG), y)
++EXTRA_CFLAGS += -DCONFIG_PROC_DEBUG
++endif
++
++ifeq ($(CONFIG_RTW_UP_MAPPING_RULE), dscp)
++EXTRA_CFLAGS += -DCONFIG_RTW_UP_MAPPING_RULE=1
++else
++EXTRA_CFLAGS += -DCONFIG_RTW_UP_MAPPING_RULE=0
++endif
++
++EXTRA_CFLAGS += -DDM_ODM_SUPPORT_TYPE=0x04
++
++ifeq ($(CONFIG_RTW_MBO), y)
++EXTRA_CFLAGS += -DCONFIG_RTW_MBO -DCONFIG_RTW_80211K -DCONFIG_RTW_WNM -DCONFIG_RTW_BTM_ROAM
++EXTRA_CFLAGS += -DCONFIG_RTW_80211R
++endif
++
++ifeq ($(CONFIG_PLATFORM_I386_PC), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++
++SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
++ARCH ?= $(SUBARCH)
++CROSS_COMPILE ?=
++KVER  := $(shell uname -r)
++KSRC := /lib/modules/$(KVER)/build
++MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
++INSTALL_PREFIX :=
++STAGINGMODDIR := /lib/modules/$(KVER)/kernel/drivers/staging
++endif
++
++ifeq ($(CONFIG_PLATFORM_NV_TK1), y)
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_NV_TK1
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++# default setting for Android 4.1, 4.2
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_PLATFORM_ANDROID
++# Enable this for Android 5.0
++EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
++EXTRA_CFLAGS += -DRTW_VENDOR_EXT_SUPPORT
++EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
++ARCH ?= arm
++
++CROSS_COMPILE := /mnt/newdisk/android_sdk/nvidia_tk1/android_L/prebuilts/gcc/linux-x86/arm/arm-eabi-4.8/bin/arm-eabi-
++KSRC :=/mnt/newdisk/android_sdk/nvidia_tk1/android_L/out/target/product/shieldtablet/obj/KERNEL/
++MODULE_NAME = wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_NV_TK1_UBUNTU), y)
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_NV_TK1
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++
++ARCH ?= arm
++
++CROSS_COMPILE ?=
++KVER := $(shell uname -r)
++KSRC := /lib/modules/$(KVER)/build
++MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
++INSTALL_PREFIX :=
++endif
++
++ifeq ($(CONFIG_PLATFORM_ACTIONS_ATM702X), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ACTIONS_ATM702X
++#ARCH := arm
++ARCH := $(R_ARCH)
++#CROSS_COMPILE := arm-none-linux-gnueabi-
++CROSS_COMPILE := $(R_CROSS_COMPILE)
++KVER:= 3.4.0
++#KSRC := ../../../../build/out/kernel
++KSRC := $(KERNEL_BUILD_PATH)
++MODULE_NAME :=wlan
++endif
++
++
++ifeq ($(CONFIG_PLATFORM_ACTIONS_ATM705X), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++#EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
++# default setting for Android 4.1, 4.2, 4.3, 4.4
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_ACTIONS_ATM705X
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++
++# Enable this for Android 5.0
++EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
++
++ifeq ($(CONFIG_SDIO_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
++_PLATFORM_FILES += platform/platform_arm_act_sdio.o
++endif
++
++ARCH := arm
++CROSS_COMPILE := /opt/arm-2011.09/bin/arm-none-linux-gnueabi-
++KSRC := /home/android_sdk/Action-semi/705a_android_L/android/kernel
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_SUN50IW1P1), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN50IW1P1
++EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
++# default setting for Android 4.1, 4.2
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++EXTRA_CFLAGS += -DCONFIG_RESUME_IN_WORKQUEUE
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
++
++# Enable this for Android 5.0
++EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
++
++ifeq ($(CONFIG_USB_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
++_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++_PLATFORM_FILES += platform/platform_ARM_SUN50IW1P1_sdio.o
++endif
++
++ARCH := arm64
++# ===Cross compile setting for Android 5.1(64) SDK ===
++CROSS_COMPILE := /home/android_sdk/Allwinner/a64/android-51/lichee/out/sun50iw1p1/android/common/buildroot/external-toolchain/bin/aarch64-linux-gnu-
++KSRC :=/home/android_sdk/Allwinner/a64/android-51/lichee/linux-3.10/
++endif
++
++ifeq ($(CONFIG_PLATFORM_TI_AM3517), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_SHUTTLE
++CROSS_COMPILE := arm-eabi-
++KSRC := $(shell pwd)/../../../Android/kernel
++ARCH := arm
++endif
++
++ifeq ($(CONFIG_PLATFORM_MSTAR_TITANIA12), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR -DCONFIG_PLATFORM_MSTAR_TITANIA12
++ARCH:=mips
++CROSS_COMPILE:= /usr/src/Mstar_kernel/mips-4.3/bin/mips-linux-gnu-
++KVER:= 2.6.28.9
++KSRC:= /usr/src/Mstar_kernel/2.6.28.9/
++endif
++
++ifeq ($(CONFIG_PLATFORM_MSTAR), y)
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_MSTAR
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_MSTAR_HIGH
++ifeq ($(CONFIG_USB_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX -DCONFIG_FIX_NR_BULKIN_BUFFER
++endif
++ARCH:=arm
++CROSS_COMPILE:= /usr/src/bin/arm-none-linux-gnueabi-
++KVER:= 3.1.10
++KSRC:= /usr/src/Mstar_kernel/3.1.10/
++endif
++
++ifeq ($(CONFIG_PLATFORM_ANDROID_X86), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
++ARCH := $(SUBARCH)
++CROSS_COMPILE := /media/DATA-2/android-x86/ics-x86_20120130/prebuilt/linux-x86/toolchain/i686-unknown-linux-gnu-4.2.1/bin/i686-unknown-linux-gnu-
++KSRC := /media/DATA-2/android-x86/ics-x86_20120130/out/target/product/generic_x86/obj/kernel
++MODULE_NAME :=wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ANDROID_INTEL_X86), y)
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_ANDROID_INTEL_X86
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_INTEL_BYT
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++EXTRA_CFLAGS += -DCONFIG_SKIP_SIGNAL_SCALE_MAPPING
++ifeq ($(CONFIG_SDIO_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_RESUME_IN_WORKQUEUE
++endif
++endif
++
++ifeq ($(CONFIG_PLATFORM_JB_X86), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
++ARCH := $(SUBARCH)
++CROSS_COMPILE := /home/android_sdk/android-x86_JB/prebuilts/gcc/linux-x86/x86/i686-linux-android-4.7/bin/i686-linux-android-
++KSRC := /home/android_sdk/android-x86_JB/out/target/product/x86/obj/kernel/
++MODULE_NAME :=wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_PXA2XX), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++ARCH := arm
++CROSS_COMPILE := arm-none-linux-gnueabi-
++KVER  := 2.6.34.1
++KSRC ?= /usr/src/linux-2.6.34.1
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_S3C2K4), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++ARCH := arm
++CROSS_COMPILE := arm-linux-
++KVER  := 2.6.24.7_$(ARCH)
++KSRC := /usr/src/kernels/linux-$(KVER)
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_S3C6K4), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++ARCH := arm
++CROSS_COMPILE := arm-none-linux-gnueabi-
++KVER  := 2.6.34.1
++KSRC ?= /usr/src/linux-2.6.34.1
++endif
++
++ifeq ($(CONFIG_PLATFORM_RTD2880B), y)
++EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTD2880B
++ARCH:=
++CROSS_COMPILE:=
++KVER:=
++KSRC:=
++endif
++
++ifeq ($(CONFIG_PLATFORM_MIPS_RMI), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++ARCH:=mips
++CROSS_COMPILE:=mipsisa32r2-uclibc-
++KVER:=
++KSRC:= /root/work/kernel_realtek
++endif
++
++ifeq ($(CONFIG_PLATFORM_MIPS_PLM), y)
++EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
++ARCH:=mips
++CROSS_COMPILE:=mipsisa32r2-uclibc-
++KVER:=
++KSRC:= /root/work/kernel_realtek
++endif
++
++ifeq ($(CONFIG_PLATFORM_MSTAR389), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR389
++ARCH:=mips
++CROSS_COMPILE:= mips-linux-gnu-
++KVER:= 2.6.28.10
++KSRC:= /home/mstar/mstar_linux/2.6.28.9/
++endif
++
++ifeq ($(CONFIG_PLATFORM_MIPS_AR9132), y)
++EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
++ARCH := mips
++CROSS_COMPILE := mips-openwrt-linux-
++KSRC := /home/alex/test_openwrt/tmp/linux-2.6.30.9
++endif
++
++ifeq ($(CONFIG_PLATFORM_DMP_PHILIPS), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM
++ARCH := mips
++#CROSS_COMPILE:=/usr/local/msdk-4.3.6-mips-EL-2.6.12.6-0.9.30.3/bin/mipsel-linux-
++CROSS_COMPILE:=/usr/local/toolchain_mipsel/bin/mipsel-linux-
++KSRC ?=/usr/local/Jupiter/linux-2.6.12
++endif
++
++ifeq ($(CONFIG_PLATFORM_RTK_DMP), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM  -DCONFIG_WIRELESS_EXT
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
++ifeq ($(CONFIG_USB_HCI), y)
++_PLATFORM_FILES += platform/platform_RTK_DMP_usb.o
++endif
++ARCH:=mips
++CROSS_COMPILE:=mipsel-linux-
++KVER:=
++KSRC ?= /usr/src/DMP_Kernel/jupiter/linux-2.6.12
++endif
++
++ifeq ($(CONFIG_PLATFORM_MT53XX), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MT53XX
++ARCH:= arm
++CROSS_COMPILE:= arm11_mtk_le-
++KVER:= 2.6.27
++KSRC?= /proj/mtk00802/BD_Compare/BDP/Dev/BDP_V301/BDP_Linux/linux-2.6.27
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_MX51_241H), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_WISTRON_PLATFORM
++ARCH := arm
++CROSS_COMPILE := /opt/freescale/usr/local/gcc-4.1.2-glibc-2.5-nptl-3/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-
++KVER  := 2.6.31
++KSRC ?= /lib/modules/2.6.31-770-g0e46b52/source
++endif
++
++ifeq ($(CONFIG_PLATFORM_FS_MX61), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++ARCH := arm
++CROSS_COMPILE := /home/share/CusEnv/FreeScale/arm-eabi-4.4.3/bin/arm-eabi-
++KSRC ?= /home/share/CusEnv/FreeScale/FS_kernel_env
++endif
++
++
++
++ifeq ($(CONFIG_PLATFORM_ACTIONS_ATJ227X), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATJ227X
++ARCH := mips
++CROSS_COMPILE := /home/cnsd4/project/actions/tools-2.6.27/bin/mipsel-linux-gnu-
++KVER  := 2.6.27
++KSRC := /home/cnsd4/project/actions/linux-2.6.27.28
++endif
++
++ifeq ($(CONFIG_PLATFORM_TI_DM365), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_TI_DM365
++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_RX
++EXTRA_CFLAGS += -DCONFIG_SINGLE_XMIT_BUF -DCONFIG_SINGLE_RECV_BUF
++ARCH := arm
++#CROSS_COMPILE := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/arm/v5t_le/bin/arm_v5t_le-
++#KSRC := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/lsp/ti-davinci/linux-dm365
++CROSS_COMPILE := /opt/montavista/pro5.0/devkit/arm/v5t_le/bin/arm-linux-
++KSRC:= /home/vivotek/lsp/DM365/kernel_platform/kernel/linux-2.6.18
++KERNELOUTPUT := ${PRODUCTDIR}/tmp
++KVER  := 2.6.18
++endif
++
++ifeq ($(CONFIG_PLATFORM_MOZART), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MOZART
++ARCH := arm
++CROSS_COMPILE := /home/vivotek/lsp/mozart3v2/Mozart3e_Toolchain/build_arm_nofpu/usr/bin/arm-linux-
++KVER  := $(shell uname -r)
++KSRC:= /opt/Vivotek/lsp/mozart3v2/kernel_platform/kernel/mozart_kernel-1.17
++KERNELOUTPUT := /home/pink/sample/ODM/IP8136W-VINT/tmp/kernel
++endif
++
++ifeq ($(CONFIG_PLATFORM_TEGRA3_CARDHU), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++# default setting for Android 4.1, 4.2
++EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++ARCH := arm
++CROSS_COMPILE := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
++KSRC := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/out/target/product/cardhu/obj/KERNEL
++MODULE_NAME := wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_TEGRA4_DALMORE), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++# default setting for Android 4.1, 4.2
++EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++ARCH := arm
++CROSS_COMPILE := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
++KSRC := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/out/target/product/dalmore/obj/KERNEL
++MODULE_NAME := wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_TCC8900), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++ARCH := arm
++CROSS_COMPILE := /home/android_sdk/Telechips/SDK_2304_20110613/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
++KSRC := /home/android_sdk/Telechips/SDK_2304_20110613/kernel
++MODULE_NAME := wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_TCC8920), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++ARCH := arm
++CROSS_COMPILE := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
++KSRC := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/kernel
++MODULE_NAME := wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_TCC8920_JB42), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++# default setting for Android 4.1, 4.2
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++ARCH := arm
++CROSS_COMPILE := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
++KSRC := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/kernel
++MODULE_NAME := wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_RK2818), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS
++ARCH := arm
++CROSS_COMPILE := /usr/src/release_fae_version/toolchain/arm-eabi-4.4.0/bin/arm-eabi-
++KSRC := /usr/src/release_fae_version/kernel25_A7_281x
++MODULE_NAME := wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_RK3188), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS
++# default setting for Android 4.1, 4.2, 4.3, 4.4
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++# default setting for Power control
++EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
++ifeq ($(CONFIG_SDIO_HCI), y)
++EXTRA_CFLAGS += -DRTW_SUPPORT_PLATFORM_SHUTDOWN
++endif
++# default setting for Special function
++ARCH := arm
++CROSS_COMPILE := /home/android_sdk/Rockchip/Rk3188/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
++KSRC := /home/android_sdk/Rockchip/Rk3188/kernel
++MODULE_NAME := wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_RK3066), y)
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_RK3066
++EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
++ifeq ($(CONFIG_SDIO_HCI), y)
++EXTRA_CFLAGS += -DRTW_SUPPORT_PLATFORM_SHUTDOWN
++endif
++EXTRA_CFLAGS += -fno-pic
++ARCH := arm
++CROSS_COMPILE := /home/android_sdk/Rockchip/rk3066_20130607/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/bin/arm-linux-androideabi-
++#CROSS_COMPILE := /home/android_sdk/Rockchip/Rk3066sdk/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/bin/arm-linux-androideabi-
++KSRC := /home/android_sdk/Rockchip/Rk3066sdk/kernel
++MODULE_NAME :=wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_URBETTER), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE
++ARCH := arm
++CROSS_COMPILE := /media/DATA-1/urbetter/arm-2009q3/bin/arm-none-linux-gnueabi-
++KSRC := /media/DATA-1/urbetter/ics-urbetter/kernel
++MODULE_NAME := wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_TI_PANDA), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE
++ARCH := arm
++#CROSS_COMPILE := /media/DATA-1/aosp/ics-aosp_20111227/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
++#KSRC := /media/DATA-1/aosp/android-omap-panda-3.0_20120104
++CROSS_COMPILE := /media/DATA-1/android-4.0/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
++KSRC := /media/DATA-1/android-4.0/panda_kernel/omap
++MODULE_NAME := wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_MIPS_JZ4760), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_MINIMAL_MEMORY_USAGE
++ARCH ?= mips
++CROSS_COMPILE ?= /mnt/sdb5/Ingenic/Umido/mips-4.3/bin/mips-linux-gnu-
++KSRC ?= /mnt/sdb5/Ingenic/Umido/kernel
++endif
++
++ifeq ($(CONFIG_PLATFORM_MIPS_X2000), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_SDIO_HOOK_DEV_SHUTDOWN
++ARCH ?= mips
++CROSS_COMPILE ?= /mnt/sdb5/Ingenic/Umido/mips-4.3/bin/mips-linux-gnu-
++KSRC ?= /mnt/sdb5/Ingenic/Umido/kernel
++endif
++
++ifeq ($(CONFIG_PLATFORM_SZEBOOK), y)
++EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
++ARCH:=arm
++CROSS_COMPILE:=/opt/crosstool2/bin/armeb-unknown-linux-gnueabi-
++KVER:= 2.6.31.6
++KSRC:= ../code/linux-2.6.31.6-2020/
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_SUNxI), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUNxI
++# default setting for Android 4.1, 4.2
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
++ifeq ($(CONFIG_USB_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
++_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++# default setting for A10-EVB mmc0
++#EXTRA_CFLAGS += -DCONFIG_WITS_EVB_V13
++_PLATFORM_FILES += platform/platform_ARM_SUNxI_sdio.o
++endif
++
++ARCH := arm
++#CROSS_COMPILE := arm-none-linux-gnueabi-
++CROSS_COMPILE=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/buildroot/output/external-toolchain/bin/arm-none-linux-gnueabi-
++KVER  := 3.0.8
++#KSRC:= ../lichee/linux-3.0/
++KSRC=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/linux-3.0
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_SUN6I), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN6I
++EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
++# default setting for Android 4.1, 4.2, 4.3, 4.4
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++EXTRA_CFLAGS +=  -DCONFIG_QOS_OPTIMIZATION
++
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
++ifeq ($(CONFIG_USB_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
++_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++# default setting for A31-EVB mmc0
++EXTRA_CFLAGS += -DCONFIG_A31_EVB
++_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
++endif
++
++ARCH := arm
++#Android-JB42
++#CROSS_COMPILE := /home/android_sdk/Allwinner/a31/android-jb42/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi-
++#KSRC :=/home/android_sdk/Allwinner/a31/android-jb42/lichee/linux-3.3
++#ifeq ($(CONFIG_USB_HCI), y)
++#MODULE_NAME := 8188eu_sw
++#endif
++# ==== Cross compile setting for kitkat-a3x_v4.5 =====
++CROSS_COMPILE := /home/android_sdk/Allwinner/a31/kitkat-a3x_v4.5/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi-
++KSRC :=/home/android_sdk/Allwinner/a31/kitkat-a3x_v4.5/lichee/linux-3.3
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_SUN7I), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN7I
++EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
++# default setting for Android 4.1, 4.2, 4.3, 4.4
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++EXTRA_CFLAGS +=  -DCONFIG_QOS_OPTIMIZATION
++
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
++ifeq ($(CONFIG_USB_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
++_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
++endif
++
++ARCH := arm
++# ===Cross compile setting for Android 4.2 SDK ===
++#CROSS_COMPILE := /home/android_sdk/Allwinner/a20_evb/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
++#KSRC := /home/android_sdk/Allwinner/a20_evb/lichee/linux-3.3
++# ==== Cross compile setting for Android 4.3 SDK =====
++#CROSS_COMPILE := /home/android_sdk/Allwinner/a20/android-jb43/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
++#KSRC := /home/android_sdk/Allwinner/a20/android-jb43/lichee/linux-3.4
++# ==== Cross compile setting for kitkat-a20_v4.4 =====
++CROSS_COMPILE := /home/android_sdk/Allwinner/a20/kitkat-a20_v4.4/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
++KSRC := /home/android_sdk/Allwinner/a20/kitkat-a20_v4.4/lichee/linux-3.4
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_SUN8I_W3P1), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I_W3P1
++EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
++# default setting for Android 4.1, 4.2
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
++ifeq ($(CONFIG_USB_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
++_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
++endif
++
++ARCH := arm
++# ===Cross compile setting for Android 4.2 SDK ===
++#CROSS_COMPILE := /home/android_sdk/Allwinner/a23/android-jb42/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
++#KSRC :=/home/android_sdk/Allwinner/a23/android-jb42/lichee/linux-3.4
++# ===Cross compile setting for Android 4.4 SDK ===
++CROSS_COMPILE := /home/android_sdk/Allwinner/a23/android-kk44/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
++KSRC :=/home/android_sdk/Allwinner/a23/android-kk44/lichee/linux-3.4
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_SUN8I_W5P1), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I_W5P1
++EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
++# default setting for Android 4.1, 4.2
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++
++# Enable this for Android 5.0
++EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
++
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
++ifeq ($(CONFIG_USB_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
++_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
++endif
++
++ARCH := arm
++# ===Cross compile setting for Android L SDK ===
++CROSS_COMPILE := /home/android_sdk/Allwinner/a33/android-L/lichee/out/sun8iw5p1/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
++KSRC :=/home/android_sdk/Allwinner/a33/android-L/lichee/linux-3.4
++endif
++
++ifeq ($(CONFIG_PLATFORM_ACTIONS_ATV5201), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATV5201
++EXTRA_CFLAGS += -DCONFIG_SDIO_DISABLE_RXFIFO_POLLING_LOOP
++ARCH := mips
++CROSS_COMPILE := mipsel-linux-gnu-
++KVER  := $(KERNEL_VER)
++KSRC:= $(CFGDIR)/../../kernel/linux-$(KERNEL_VER)
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_RTD299X), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++ifeq ($(CONFIG_ANDROID), y)
++# Enable this for Android 5.0
++EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
++endif
++#ARCH, CROSS_COMPILE, KSRC,and  MODDESTDIR are provided by external makefile
++INSTALL_PREFIX :=
++MODULE_NAME := wlan
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_RTD299X_LG), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DRTW_P2P_GROUP_INTERFACE=1
++EXTRA_CFLAGS += -DCONFIG_IFACE_NUMBER=3
++#EXTRA_CFLAGS += -DCONFIG_FIX_HWPORT
++EXTRA_CFLAGS += -DLGE_PRIVATE
++EXTRA_CFLAGS += -DPURE_SUPPLICANT
++EXTRA_CFLAGS += -DCONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP -DCONFIG_RTW_IOCTL_SET_COUNTRY
++EXTRA_CFLAGS += -DDBG_RX_DFRAME_RAW_DATA
++EXTRA_CFLAGS += -DRTW_REDUCE_SCAN_SWITCH_CH_TIME
++ARCH ?= arm
++KVER ?=
++
++ifneq ($(PLATFORM), WEBOS)
++$(info PLATFORM is empty)
++CROSS_COMPILE ?= /mnt/newdisk/LGE/arm-lg115x-linux-gnueabi-4.8-2016.03-x86_64/bin/arm-lg115x-linux-gnueabi-
++KSRC ?= /mnt/newdisk/LGE/linux-rockhopper_k3lp_drd4tv_423
++endif
++
++CROSS_COMPILE ?=
++KSRC ?= $(LINUX_SRC)
++INSTALL_PREFIX ?=
++endif
++
++ifeq ($(CONFIG_PLATFORM_HISILICON), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_HISILICON
++ifeq ($(SUPPORT_CONCURRENT),y)
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++endif
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++ARCH := arm
++ifeq ($(CROSS_COMPILE),)
++       CROSS_COMPILE = arm-hisiv200-linux-
++endif
++MODULE_NAME := rtl8192eu
++ifeq ($(KSRC),)
++       KSRC := ../../../../../../kernel/linux-3.4.y
++endif
++endif
++
++ifeq ($(CONFIG_PLATFORM_HISILICON_HI3798), y)
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON_HI3798
++#EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON_HI3798_MV200_HDMI_DONGLE
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++# default setting for Android
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
++EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT
++# default setting for Android 5.x and later
++#EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
++
++# If system could power on and recognize Wi-Fi SDIO automatically,
++# platfrom operations are not necessary.
++#ifeq ($(CONFIG_SDIO_HCI), y)
++#EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
++#_PLATFORM_FILES += platform/platform_hisilicon_hi3798_sdio.o
++#EXTRA_CFLAGS += -DCONFIG_HISI_SDIO_ID=1
++#endif
++
++ARCH ?= arm
++CROSS_COMPILE ?= /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/tools/linux/toolchains/arm-histbv310-linux/bin/arm-histbv310-linux-
++ifndef KSRC
++KSRC := /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/source/kernel/linux-3.18.y
++KSRC += O=/HiSTBAndroidV600R003C00SPC021_git_0512/out/target/product/Hi3798MV200/obj/KERNEL_OBJ
++endif
++
++ifeq ($(CONFIG_RTL8822B), y)
++ifeq ($(CONFIG_SDIO_HCI), y)
++CONFIG_RTL8822BS ?= m
++USER_MODULE_NAME := rtl8822bs
++endif
++endif
++
++endif
++
++# Platform setting
++ifeq ($(CONFIG_PLATFORM_ARM_SPREADTRUM_6820), y)
++ifeq ($(CONFIG_ANDROID_2X), y)
++EXTRA_CFLAGS += -DANDROID_2X
++endif
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_SPRD
++EXTRA_CFLAGS += -DPLATFORM_SPREADTRUM_6820
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++ifeq ($(RTL871X), rtl8188e)
++EXTRA_CFLAGS += -DSOFTAP_PS_DURATION=50
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
++_PLATFORM_FILES += platform/platform_sprd_sdio.o
++endif
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_SPREADTRUM_8810), y)
++ifeq ($(CONFIG_ANDROID_2X), y)
++EXTRA_CFLAGS += -DANDROID_2X
++endif
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_SPRD
++EXTRA_CFLAGS += -DPLATFORM_SPREADTRUM_8810
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++ifeq ($(RTL871X), rtl8188e)
++EXTRA_CFLAGS += -DSOFTAP_PS_DURATION=50
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
++_PLATFORM_FILES += platform/platform_sprd_sdio.o
++endif
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_WMT), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
++ifeq ($(CONFIG_SDIO_HCI), y)
++_PLATFORM_FILES += platform/platform_ARM_WMT_sdio.o
++endif
++ARCH := arm
++CROSS_COMPILE := /home/android_sdk/WonderMedia/wm8880-android4.4/toolchain/arm_201103_gcc4.5.2/mybin/arm_1103_le-
++KSRC := /home/android_sdk/WonderMedia/wm8880-android4.4/kernel4.4/
++MODULE_NAME :=8189es_kk
++endif
++
++ifeq ($(CONFIG_PLATFORM_RTK119X), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++#EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN7I
++EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
++# default setting for Android 4.1, 4.2
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++#EXTRA_CFLAGS +=  -DCONFIG_QOS_OPTIMIZATION
++EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION
++
++#EXTRA_CFLAGS += -DCONFIG_#PLATFORM_OPS
++ifeq ($(CONFIG_USB_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
++#_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
++endif
++ifeq ($(CONFIG_SDIO_HCI), y)
++_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
++endif
++
++ARCH := arm
++
++# ==== Cross compile setting for Android 4.4 SDK =====
++#CROSS_COMPILE := arm-linux-gnueabihf-
++KVER  := 3.10.24
++#KSRC :=/home/android_sdk/Allwinner/a20/android-kitkat44/lichee/linux-3.4
++CROSS_COMPILE := /home/realtek/software_phoenix/phoenix/toolchain/usr/local/arm-2013.11/bin/arm-linux-gnueabihf-
++KSRC := /home/realtek/software_phoenix/linux-kernel
++MODULE_NAME := 8192eu
++
++endif
++
++ifeq ($(CONFIG_PLATFORM_RTK119X_AM), y)
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_RTK119X_AM
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE -DCONFIG_FULL_CH_IN_P2P_HANDSHAKE
++EXTRA_CFLAGS += -DCONFIG_IFACE_NUMBER=3
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++
++ifeq ($(CONFIG_USB_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
++endif
++
++ARCH := arm
++
++#CROSS_COMPILE := arm-linux-gnueabihf-
++KVER  := 3.10.24
++#KSRC :=
++CROSS_COMPILE :=
++endif
++
++ifeq ($(CONFIG_PLATFORM_RTK129X), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DRTK_129X_PLATFORM
++EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
++# default setting for Android 4.1, 4.2
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++#EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_QOS_OPTIMIZATION
++EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION
++# Enable this for Android 5.0
++EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
++ifeq ($(CONFIG_RTL8821C)$(CONFIG_SDIO_HCI),yy)
++EXTRA_CFLAGS += -DCONFIG_WAKEUP_GPIO_INPUT_MODE
++EXTRA_CFLAGS += -DCONFIG_BT_WAKE_HST_OPEN_DRAIN
++endif
++EXTRA_CFLAGS += -Wno-error=date-time
++# default setting for Android 7.0
++ifeq ($(RTK_ANDROID_VERSION), nougat)
++EXTRA_CFLAGS += -DRTW_P2P_GROUP_INTERFACE=1
++endif
++#EXTRA_CFLAGS += -DCONFIG_#PLATFORM_OPS
++ifeq ($(CONFIG_USB_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
++endif
++
++ARCH := arm64
++
++# ==== Cross compile setting for Android 4.4 SDK =====
++#CROSS_COMPILE := arm-linux-gnueabihf-
++#KVER  := 4.1.10
++#CROSS_COMPILE := $(CROSS)
++#KSRC := $(LINUX_KERNEL_PATH)
++CROSS_COMPILE := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/phoenix/toolchain/asdk64-4.9.4-a53-EL-3.10-g2.19-a64nt-160307/bin/asdk64-linux-
++KSRC := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/linux-kernel
++endif
++
++ifeq ($(CONFIG_PLATFORM_RTK390X), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_RTK390X
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++EXTRA_CFLAGS += -DCONFIG_RTW_NETIF_SG
++ifeq ($(CONFIG_USB_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
++endif
++
++ARCH:=rlx
++
++CROSS_COMPILE:=mips-linux-
++KSRC:= /home/realtek/share/Develop/IPCAM_SDK/RealSil/rts3901_sdk_v1.2_vanilla/linux-3.10
++
++endif
++
++ifeq ($(CONFIG_PLATFORM_NOVATEK_NT72668), y)
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_NOVATEK_NT72668
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_RX
++EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
++ARCH ?= arm
++CROSS_COMPILE := arm-linux-gnueabihf-
++KVER := 3.8.0
++KSRC := /Custom/Novatek/TCL/linux-3.8_header
++#KSRC := $(KERNELDIR)
++endif
++
++ifeq ($(CONFIG_PLATFORM_ARM_TCC8930_JB42), y)
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++# default setting for Android 4.1, 4.2
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
++ARCH := arm
++CROSS_COMPILE := /home/android_sdk/Telechips/v13.05_r1-tcc-android-4.2.2_tcc893x-evm_build/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
++KSRC := /home/android_sdk/Telechips/v13.05_r1-tcc-android-4.2.2_tcc893x-evm_build/kernel
++MODULE_NAME := wlan
++endif 
++
++ifeq ($(CONFIG_PLATFORM_RTL8197D), y)
++EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTL8197D
++export DIR_LINUX=$(shell pwd)/../SDK/rlxlinux-sdk321-v50/linux-2.6.30
++ARCH ?= rlx
++CROSS_COMPILE:= $(DIR_LINUX)/../toolchain/rsdk-1.5.5-5281-EB-2.6.30-0.9.30.3-110714/bin/rsdk-linux-
++KSRC := $(DIR_LINUX)
++endif
++
++ifeq ($(CONFIG_PLATFORM_AML_S905), y)
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_AML_S905
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -fno-pic
++# default setting for Android
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
++EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT
++# default setting for Android 5.x and later
++EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
++
++ifeq ($(CONFIG_SDIO_HCI), y)
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
++_PLATFORM_FILES += platform/platform_aml_s905_sdio.o
++endif
++
++ARCH ?= arm64
++CROSS_COMPILE ?= /4.4_S905L_8822bs_compile/gcc-linaro-aarch64-linux-gnu-4.9-2014.09_linux/bin/aarch64-linux-gnu-
++ifndef KSRC
++KSRC := /4.4_S905L_8822bs_compile/common
++# To locate output files in a separate directory.
++KSRC += O=/4.4_S905L_8822bs_compile/KERNEL_OBJ
++endif
++
++ifeq ($(CONFIG_RTL8822B), y)
++ifeq ($(CONFIG_SDIO_HCI), y)
++CONFIG_RTL8822BS ?= m
++USER_MODULE_NAME := 8822bs
++endif
++endif
++
++endif
++
++ifeq ($(CONFIG_PLATFORM_ZTE_ZX296716), y)
++EXTRA_CFLAGS += -Wno-error=date-time
++EXTRA_CFLAGS += -DCONFIG_PLATFORM_ZTE_ZX296716
++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
++# default setting for Android
++EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
++EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
++EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT
++# default setting for Android 5.x and later
++#EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
++
++ifeq ($(CONFIG_SDIO_HCI), y)
++# mark this temporarily
++#EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
++#_PLATFORM_FILES += platform/platform_zte_zx296716_sdio.o
++endif
++
++ARCH ?= arm64
++CROSS_COMPILE ?=
++KSRC ?=
++
++ifeq ($(CONFIG_RTL8822B), y)
++ifeq ($(CONFIG_SDIO_HCI), y)
++CONFIG_RTL8822BS ?= m
++USER_MODULE_NAME := 8822bs
++endif
++endif
++
++endif
++
++########### CUSTOMER ################################
++ifeq ($(CONFIG_CUSTOMER_HUAWEI_GENERAL), y)
++CONFIG_CUSTOMER_HUAWEI = y
++endif
++
++ifeq ($(CONFIG_CUSTOMER_HUAWEI), y)
++EXTRA_CFLAGS += -DCONFIG_HUAWEI_PROC
++endif
++
++ifeq ($(CONFIG_MULTIDRV), y)
++
++ifeq ($(CONFIG_SDIO_HCI), y)
++MODULE_NAME := rtw_sdio
++endif
++
++ifeq ($(CONFIG_USB_HCI), y)
++MODULE_NAME := rtw_usb
++endif
++
++ifeq ($(CONFIG_PCI_HCI), y)
++MODULE_NAME := rtw_pci
++endif
++
++
++endif
++
++USER_MODULE_NAME ?=
++ifneq ($(USER_MODULE_NAME),)
++MODULE_NAME := $(USER_MODULE_NAME)
++endif
++
++ifneq ($(KERNELRELEASE),)
++
++########### this part for *.mk ############################
++include $(src)/hal/phydm/phydm.mk
++
++########### HAL_RTL8822B #################################
++ifeq ($(CONFIG_RTL8822B), y)
++include $(src)/rtl8822b.mk
++endif
++
++########### HAL_RTL8821C #################################
++ifeq ($(CONFIG_RTL8821C), y)
++include $(src)/rtl8821c.mk
++endif
++
++########### HAL_RTL8822C #################################
++ifeq ($(CONFIG_RTL8822C), y)
++include $(src)/rtl8822c.mk
++endif
++
++########### HAL_RTL8814B #################################
++ifeq ($(CONFIG_RTL8814B), y)
++include $(src)/rtl8814b.mk
++endif
++
++rtk_core :=	core/rtw_cmd.o \
++		core/rtw_security.o \
++		core/rtw_debug.o \
++		core/rtw_io.o \
++		core/rtw_ioctl_query.o \
++		core/rtw_ioctl_set.o \
++		core/rtw_ieee80211.o \
++		core/rtw_mlme.o \
++		core/rtw_mlme_ext.o \
++		core/rtw_mi.o \
++		core/rtw_wlan_util.o \
++		core/rtw_vht.o \
++		core/rtw_pwrctrl.o \
++		core/rtw_rf.o \
++		core/rtw_chplan.o \
++		core/monitor/rtw_radiotap.o \
++		core/rtw_recv.o \
++		core/rtw_sta_mgt.o \
++		core/rtw_ap.o \
++		core/wds/rtw_wds.o \
++		core/mesh/rtw_mesh.o \
++		core/mesh/rtw_mesh_pathtbl.o \
++		core/mesh/rtw_mesh_hwmp.o \
++		core/rtw_xmit.o	\
++		core/rtw_p2p.o \
++		core/rtw_rson.o \
++		core/rtw_tdls.o \
++		core/rtw_br_ext.o \
++		core/rtw_iol.o \
++		core/rtw_sreset.o \
++		core/rtw_btcoex_wifionly.o \
++		core/rtw_btcoex.o \
++		core/rtw_beamforming.o \
++		core/rtw_odm.o \
++		core/rtw_rm.o \
++		core/rtw_rm_fsm.o \
++		core/rtw_ft.o \
++		core/rtw_wnm.o \
++		core/rtw_mbo.o \
++		core/rtw_rm_util.o \
++		core/efuse/rtw_efuse.o 
++
++ifeq ($(CONFIG_SDIO_HCI), y)
++rtk_core += core/rtw_sdio.o
++endif
++
++EXTRA_CFLAGS += -I$(src)/core/crypto
++rtk_core += \
++		core/crypto/aes-internal.o \
++		core/crypto/aes-internal-enc.o \
++		core/crypto/aes-gcm.o \
++		core/crypto/aes-ccm.o \
++		core/crypto/aes-omac1.o \
++		core/crypto/ccmp.o \
++		core/crypto/gcmp.o \
++		core/crypto/aes-siv.o \
++		core/crypto/aes-ctr.o \
++		core/crypto/sha256-internal.o \
++		core/crypto/sha256.o \
++		core/crypto/sha256-prf.o \
++		core/crypto/rtw_crypto_wrap.o \
++		core/rtw_swcrypto.o
++
++$(MODULE_NAME)-y += $(rtk_core)
++
++$(MODULE_NAME)-$(CONFIG_WAPI_SUPPORT) += core/rtw_wapi.o	\
++					core/rtw_wapi_sms4.o
++
++$(MODULE_NAME)-y += $(_OS_INTFS_FILES)
++$(MODULE_NAME)-y += $(_HAL_INTFS_FILES)
++$(MODULE_NAME)-y += $(_PHYDM_FILES)
++$(MODULE_NAME)-y += $(_BTC_FILES)
++$(MODULE_NAME)-y += $(_PLATFORM_FILES)
++
++$(MODULE_NAME)-$(CONFIG_MP_INCLUDED) += core/rtw_mp.o
++
++ifeq ($(CONFIG_RTL8723B), y)
++$(MODULE_NAME)-$(CONFIG_MP_INCLUDED)+= core/rtw_bt_mp.o
++endif
++
++obj-$(CONFIG_RTL8723DS) := $(MODULE_NAME).o
++
++else
++
++export CONFIG_RTL8723DS = m
++
++all: modules
++
++modules:
++	$(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd)  modules
++
++strip:
++	$(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded
++
++install:
++	install -p -m 644 $(MODULE_NAME).ko  $(MODDESTDIR)
++	/sbin/depmod -a ${KVER}
++
++uninstall:
++	rm -f $(MODDESTDIR)/$(MODULE_NAME).ko
++	/sbin/depmod -a ${KVER}
++
++backup_rtlwifi:
++	@echo "Making backup rtlwifi drivers"
++ifneq (,$(wildcard $(STAGINGMODDIR)/rtl*))
++	@tar cPf $(wildcard $(STAGINGMODDIR))/backup_rtlwifi_driver.tar $(wildcard $(STAGINGMODDIR)/rtl*)
++	@rm -rf $(wildcard $(STAGINGMODDIR)/rtl*)
++endif
++ifneq (,$(wildcard $(MODDESTDIR)realtek))
++	@tar cPf $(MODDESTDIR)backup_rtlwifi_driver.tar $(MODDESTDIR)realtek
++	@rm -fr $(MODDESTDIR)realtek
++endif
++ifneq (,$(wildcard $(MODDESTDIR)rtl*))
++	@tar cPf $(MODDESTDIR)../backup_rtlwifi_driver.tar $(wildcard $(MODDESTDIR)rtl*)
++	@rm -fr $(wildcard $(MODDESTDIR)rtl*)
++endif
++	@/sbin/depmod -a ${KVER}
++	@echo "Please reboot your system"
++
++restore_rtlwifi:
++	@echo "Restoring backups"
++ifneq (,$(wildcard $(STAGINGMODDIR)/backup_rtlwifi_driver.tar))
++	@tar xPf $(STAGINGMODDIR)/backup_rtlwifi_driver.tar
++	@rm $(STAGINGMODDIR)/backup_rtlwifi_driver.tar
++endif
++ifneq (,$(wildcard $(MODDESTDIR)backup_rtlwifi_driver.tar))
++	@tar xPf $(MODDESTDIR)backup_rtlwifi_driver.tar
++	@rm $(MODDESTDIR)backup_rtlwifi_driver.tar
++endif
++ifneq (,$(wildcard $(MODDESTDIR)../backup_rtlwifi_driver.tar))
++	@tar xPf $(MODDESTDIR)../backup_rtlwifi_driver.tar
++	@rm $(MODDESTDIR)../backup_rtlwifi_driver.tar
++endif
++	@/sbin/depmod -a ${KVER}
++	@echo "Please reboot your system"
++
++config_r:
++	@echo "make config"
++	/bin/bash script/Configure script/config.in
++
++
++.PHONY: modules clean
++
++clean:
++	#$(MAKE) -C $(KSRC) M=$(shell pwd) clean
++	cd hal ; rm -fr */*/*/*.mod.c */*/*/*.mod */*/*/*.o */*/*/.*.cmd */*/*/*.ko
++	cd hal ; rm -fr */*/*.mod.c */*/*.mod */*/*.o */*/.*.cmd */*/*.ko
++	cd hal ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko
++	cd hal ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
++	cd core ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko
++	cd core ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
++	cd os_dep/linux ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
++	cd os_dep ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
++	cd platform ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
++	rm -fr Module.symvers ; rm -fr Module.markers ; rm -fr modules.order
++	rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~
++	rm -fr .tmp_versions
++endif
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/clean b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/clean
+new file mode 100644
+index 000000000..87664218b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/clean
+@@ -0,0 +1,5 @@
++#!/bin/bash
++rmmod 8192cu
++rmmod 8192ce
++rmmod 8192du
++rmmod 8192de
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-ccm.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-ccm.c
+new file mode 100644
+index 000000000..dceec778a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-ccm.c
+@@ -0,0 +1,211 @@
++/*
++ * Counter with CBC-MAC (CCM) with AES
++ *
++ * Copyright (c) 2010-2012, Jouni Malinen <j@w1.fi>
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#include "rtw_crypto_wrap.h"
++
++#include "aes.h"
++#include "aes_wrap.h"
++
++
++static void xor_aes_block(u8 *dst, const u8 *src)
++{
++	u32 *d = (u32 *) dst;
++	u32 *s = (u32 *) src;
++	*d++ ^= *s++;
++	*d++ ^= *s++;
++	*d++ ^= *s++;
++	*d++ ^= *s++;
++}
++
++
++static void aes_ccm_auth_start(void *aes, size_t M, size_t L, const u8 *nonce,
++			       const u8 *aad, size_t aad_len, size_t plain_len,
++			       u8 *x)
++{
++	u8 aad_buf[2 * AES_BLOCK_SIZE];
++	u8 b[AES_BLOCK_SIZE];
++
++	/* Authentication */
++	/* B_0: Flags | Nonce N | l(m) */
++	b[0] = aad_len ? 0x40 : 0 /* Adata */;
++	b[0] |= (((M - 2) / 2) /* M' */ << 3);
++	b[0] |= (L - 1) /* L' */;
++	os_memcpy(&b[1], nonce, 15 - L);
++	WPA_PUT_BE16(&b[AES_BLOCK_SIZE - L], plain_len);
++
++	wpa_hexdump_key(_MSG_EXCESSIVE_, "CCM B_0", b, AES_BLOCK_SIZE);
++	aes_encrypt(aes, b, x); /* X_1 = E(K, B_0) */
++
++	if (!aad_len)
++		return;
++
++	WPA_PUT_BE16(aad_buf, aad_len);
++	os_memcpy(aad_buf + 2, aad, aad_len);
++	os_memset(aad_buf + 2 + aad_len, 0, sizeof(aad_buf) - 2 - aad_len);
++
++	xor_aes_block(aad_buf, x);
++	aes_encrypt(aes, aad_buf, x); /* X_2 = E(K, X_1 XOR B_1) */
++
++	if (aad_len > AES_BLOCK_SIZE - 2) {
++		xor_aes_block(&aad_buf[AES_BLOCK_SIZE], x);
++		/* X_3 = E(K, X_2 XOR B_2) */
++		aes_encrypt(aes, &aad_buf[AES_BLOCK_SIZE], x);
++	}
++}
++
++
++static void aes_ccm_auth(void *aes, const u8 *data, size_t len, u8 *x)
++{
++	size_t last = len % AES_BLOCK_SIZE;
++	size_t i;
++
++	for (i = 0; i < len / AES_BLOCK_SIZE; i++) {
++		/* X_i+1 = E(K, X_i XOR B_i) */
++		xor_aes_block(x, data);
++		data += AES_BLOCK_SIZE;
++		aes_encrypt(aes, x, x);
++	}
++	if (last) {
++		/* XOR zero-padded last block */
++		for (i = 0; i < last; i++)
++			x[i] ^= *data++;
++		aes_encrypt(aes, x, x);
++	}
++}
++
++
++static void aes_ccm_encr_start(size_t L, const u8 *nonce, u8 *a)
++{
++	/* A_i = Flags | Nonce N | Counter i */
++	a[0] = L - 1; /* Flags = L' */
++	os_memcpy(&a[1], nonce, 15 - L);
++}
++
++
++static void aes_ccm_encr(void *aes, size_t L, const u8 *in, size_t len, u8 *out,
++			 u8 *a)
++{
++	size_t last = len % AES_BLOCK_SIZE;
++	size_t i;
++
++	/* crypt = msg XOR (S_1 | S_2 | ... | S_n) */
++	for (i = 1; i <= len / AES_BLOCK_SIZE; i++) {
++		WPA_PUT_BE16(&a[AES_BLOCK_SIZE - 2], i);
++		/* S_i = E(K, A_i) */
++		aes_encrypt(aes, a, out);
++		xor_aes_block(out, in);
++		out += AES_BLOCK_SIZE;
++		in += AES_BLOCK_SIZE;
++	}
++	if (last) {
++		WPA_PUT_BE16(&a[AES_BLOCK_SIZE - 2], i);
++		aes_encrypt(aes, a, out);
++		/* XOR zero-padded last block */
++		for (i = 0; i < last; i++)
++			*out++ ^= *in++;
++	}
++}
++
++
++static void aes_ccm_encr_auth(void *aes, size_t M, u8 *x, u8 *a, u8 *auth)
++{
++	size_t i;
++	u8 tmp[AES_BLOCK_SIZE];
++
++	wpa_hexdump_key(_MSG_EXCESSIVE_, "CCM T", x, M);
++	/* U = T XOR S_0; S_0 = E(K, A_0) */
++	WPA_PUT_BE16(&a[AES_BLOCK_SIZE - 2], 0);
++	aes_encrypt(aes, a, tmp);
++	for (i = 0; i < M; i++)
++		auth[i] = x[i] ^ tmp[i];
++	wpa_hexdump_key(_MSG_EXCESSIVE_, "CCM U", auth, M);
++}
++
++
++static void aes_ccm_decr_auth(void *aes, size_t M, u8 *a, const u8 *auth, u8 *t)
++{
++	size_t i;
++	u8 tmp[AES_BLOCK_SIZE];
++
++	wpa_hexdump_key(_MSG_EXCESSIVE_, "CCM U", auth, M);
++	/* U = T XOR S_0; S_0 = E(K, A_0) */
++	WPA_PUT_BE16(&a[AES_BLOCK_SIZE - 2], 0);
++	aes_encrypt(aes, a, tmp);
++	for (i = 0; i < M; i++)
++		t[i] = auth[i] ^ tmp[i];
++	wpa_hexdump_key(_MSG_EXCESSIVE_, "CCM T", t, M);
++}
++
++
++/* AES-CCM with fixed L=2 and aad_len <= 30 assumption */
++int aes_ccm_ae(const u8 *key, size_t key_len, const u8 *nonce,
++	       size_t M, const u8 *plain, size_t plain_len,
++	       const u8 *aad, size_t aad_len, u8 *crypt, u8 *auth)
++{
++	const size_t L = 2;
++	void *aes;
++	u8 x[AES_BLOCK_SIZE], a[AES_BLOCK_SIZE];
++
++	if (aad_len > 30 || M > AES_BLOCK_SIZE)
++		return -1;
++
++	aes = aes_encrypt_init(key, key_len);
++	if (aes == NULL)
++		return -1;
++
++	aes_ccm_auth_start(aes, M, L, nonce, aad, aad_len, plain_len, x);
++	aes_ccm_auth(aes, plain, plain_len, x);
++
++	/* Encryption */
++	aes_ccm_encr_start(L, nonce, a);
++	aes_ccm_encr(aes, L, plain, plain_len, crypt, a);
++	aes_ccm_encr_auth(aes, M, x, a, auth);
++
++	aes_encrypt_deinit(aes);
++
++	return 0;
++}
++
++
++/* AES-CCM with fixed L=2 and aad_len <= 30 assumption */
++int aes_ccm_ad(const u8 *key, size_t key_len, const u8 *nonce,
++	       size_t M, const u8 *crypt, size_t crypt_len,
++	       const u8 *aad, size_t aad_len, const u8 *auth, u8 *plain)
++{
++	const size_t L = 2;
++	void *aes;
++	u8 x[AES_BLOCK_SIZE], a[AES_BLOCK_SIZE];
++	u8 t[AES_BLOCK_SIZE];
++
++	if (aad_len > 30 || M > AES_BLOCK_SIZE)
++		return -1;
++
++	aes = aes_encrypt_init(key, key_len);
++	if (aes == NULL)
++		return -1;
++
++	/* Decryption */
++	aes_ccm_encr_start(L, nonce, a);
++	aes_ccm_decr_auth(aes, M, a, auth, t);
++
++	/* plaintext = msg XOR (S_1 | S_2 | ... | S_n) */
++	aes_ccm_encr(aes, L, crypt, crypt_len, plain, a);
++
++	aes_ccm_auth_start(aes, M, L, nonce, aad, aad_len, crypt_len, x);
++	aes_ccm_auth(aes, plain, crypt_len, x);
++
++	aes_encrypt_deinit(aes);
++
++	if (os_memcmp_const(x, t, M) != 0) {
++		wpa_printf(_MSG_EXCESSIVE_, "CCM: Auth mismatch");
++		return -1;
++	}
++
++	return 0;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-ctr.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-ctr.c
+new file mode 100644
+index 000000000..6c06851dd
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-ctr.c
+@@ -0,0 +1,70 @@
++/*
++ * AES-128/192/256 CTR
++ *
++ * Copyright (c) 2003-2007, Jouni Malinen <j@w1.fi>
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#include "rtw_crypto_wrap.h"
++
++#include "aes.h"
++#include "aes_wrap.h"
++
++/**
++ * aes_ctr_encrypt - AES-128/192/256 CTR mode encryption
++ * @key: Key for encryption (key_len bytes)
++ * @key_len: Length of the key (16, 24, or 32 bytes)
++ * @nonce: Nonce for counter mode (16 bytes)
++ * @data: Data to encrypt in-place
++ * @data_len: Length of data in bytes
++ * Returns: 0 on success, -1 on failure
++ */
++int aes_ctr_encrypt(const u8 *key, size_t key_len, const u8 *nonce,
++		    u8 *data, size_t data_len)
++{
++	void *ctx;
++	size_t j, len, left = data_len;
++	int i;
++	u8 *pos = data;
++	u8 counter[AES_BLOCK_SIZE], buf[AES_BLOCK_SIZE];
++
++	ctx = aes_encrypt_init(key, key_len);
++	if (ctx == NULL)
++		return -1;
++	os_memcpy(counter, nonce, AES_BLOCK_SIZE);
++
++	while (left > 0) {
++		aes_encrypt(ctx, counter, buf);
++
++		len = (left < AES_BLOCK_SIZE) ? left : AES_BLOCK_SIZE;
++		for (j = 0; j < len; j++)
++			pos[j] ^= buf[j];
++		pos += len;
++		left -= len;
++
++		for (i = AES_BLOCK_SIZE - 1; i >= 0; i--) {
++			counter[i]++;
++			if (counter[i])
++				break;
++		}
++	}
++	aes_encrypt_deinit(ctx);
++	return 0;
++}
++
++
++/**
++ * aes_128_ctr_encrypt - AES-128 CTR mode encryption
++ * @key: Key for encryption (key_len bytes)
++ * @nonce: Nonce for counter mode (16 bytes)
++ * @data: Data to encrypt in-place
++ * @data_len: Length of data in bytes
++ * Returns: 0 on success, -1 on failure
++ */
++int aes_128_ctr_encrypt(const u8 *key, const u8 *nonce,
++			u8 *data, size_t data_len)
++{
++	return aes_ctr_encrypt(key, 16, nonce, data, data_len);
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-gcm.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-gcm.c
+new file mode 100644
+index 000000000..47088102b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-gcm.c
+@@ -0,0 +1,326 @@
++/*
++ * Galois/Counter Mode (GCM) and GMAC with AES
++ *
++ * Copyright (c) 2012, Jouni Malinen <j@w1.fi>
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#include "rtw_crypto_wrap.h"
++
++#include "aes.h"
++#include "aes_wrap.h"
++
++static void inc32(u8 *block)
++{
++	u32 val;
++	val = WPA_GET_BE32(block + AES_BLOCK_SIZE - 4);
++	val++;
++	WPA_PUT_BE32(block + AES_BLOCK_SIZE - 4, val);
++}
++
++
++static void xor_block(u8 *dst, const u8 *src)
++{
++	u32 *d = (u32 *) dst;
++	u32 *s = (u32 *) src;
++	*d++ ^= *s++;
++	*d++ ^= *s++;
++	*d++ ^= *s++;
++	*d++ ^= *s++;
++}
++
++
++static void shift_right_block(u8 *v)
++{
++	u32 val;
++
++	val = WPA_GET_BE32(v + 12);
++	val >>= 1;
++	if (v[11] & 0x01)
++		val |= 0x80000000;
++	WPA_PUT_BE32(v + 12, val);
++
++	val = WPA_GET_BE32(v + 8);
++	val >>= 1;
++	if (v[7] & 0x01)
++		val |= 0x80000000;
++	WPA_PUT_BE32(v + 8, val);
++
++	val = WPA_GET_BE32(v + 4);
++	val >>= 1;
++	if (v[3] & 0x01)
++		val |= 0x80000000;
++	WPA_PUT_BE32(v + 4, val);
++
++	val = WPA_GET_BE32(v);
++	val >>= 1;
++	WPA_PUT_BE32(v, val);
++}
++
++
++/* Multiplication in GF(2^128) */
++static void gf_mult(const u8 *x, const u8 *y, u8 *z)
++{
++	u8 v[16];
++	int i, j;
++
++	os_memset(z, 0, 16); /* Z_0 = 0^128 */
++	os_memcpy(v, y, 16); /* V_0 = Y */
++
++	for (i = 0; i < 16; i++) {
++		for (j = 0; j < 8; j++) {
++			if (x[i] & BIT(7 - j)) {
++				/* Z_(i + 1) = Z_i XOR V_i */
++				xor_block(z, v);
++			} else {
++				/* Z_(i + 1) = Z_i */
++			}
++
++			if (v[15] & 0x01) {
++				/* V_(i + 1) = (V_i >> 1) XOR R */
++				shift_right_block(v);
++				/* R = 11100001 || 0^120 */
++				v[0] ^= 0xe1;
++			} else {
++				/* V_(i + 1) = V_i >> 1 */
++				shift_right_block(v);
++			}
++		}
++	}
++}
++
++
++static void ghash_start(u8 *y)
++{
++	/* Y_0 = 0^128 */
++	os_memset(y, 0, 16);
++}
++
++
++static void ghash(const u8 *h, const u8 *x, size_t xlen, u8 *y)
++{
++	size_t m, i;
++	const u8 *xpos = x;
++	u8 tmp[16];
++
++	m = xlen / 16;
++
++	for (i = 0; i < m; i++) {
++		/* Y_i = (Y^(i-1) XOR X_i) dot H */
++		xor_block(y, xpos);
++		xpos += 16;
++
++		/* dot operation:
++		 * multiplication operation for binary Galois (finite) field of
++		 * 2^128 elements */
++		gf_mult(y, h, tmp);
++		os_memcpy(y, tmp, 16);
++	}
++
++	if (x + xlen > xpos) {
++		/* Add zero padded last block */
++		size_t last = x + xlen - xpos;
++		os_memcpy(tmp, xpos, last);
++		os_memset(tmp + last, 0, sizeof(tmp) - last);
++
++		/* Y_i = (Y^(i-1) XOR X_i) dot H */
++		xor_block(y, tmp);
++
++		/* dot operation:
++		 * multiplication operation for binary Galois (finite) field of
++		 * 2^128 elements */
++		gf_mult(y, h, tmp);
++		os_memcpy(y, tmp, 16);
++	}
++
++	/* Return Y_m */
++}
++
++
++static void aes_gctr(void *aes, const u8 *icb, const u8 *x, size_t xlen, u8 *y)
++{
++	size_t i, n, last;
++	u8 cb[AES_BLOCK_SIZE], tmp[AES_BLOCK_SIZE];
++	const u8 *xpos = x;
++	u8 *ypos = y;
++
++	if (xlen == 0)
++		return;
++
++	n = xlen / 16;
++
++	os_memcpy(cb, icb, AES_BLOCK_SIZE);
++	/* Full blocks */
++	for (i = 0; i < n; i++) {
++		aes_encrypt(aes, cb, ypos);
++		xor_block(ypos, xpos);
++		xpos += AES_BLOCK_SIZE;
++		ypos += AES_BLOCK_SIZE;
++		inc32(cb);
++	}
++
++	last = x + xlen - xpos;
++	if (last) {
++		/* Last, partial block */
++		aes_encrypt(aes, cb, tmp);
++		for (i = 0; i < last; i++)
++			*ypos++ = *xpos++ ^ tmp[i];
++	}
++}
++
++
++static void * aes_gcm_init_hash_subkey(const u8 *key, size_t key_len, u8 *H)
++{
++	void *aes;
++
++	aes = aes_encrypt_init(key, key_len);
++	if (aes == NULL)
++		return NULL;
++
++	/* Generate hash subkey H = AES_K(0^128) */
++	os_memset(H, 0, AES_BLOCK_SIZE);
++	aes_encrypt(aes, H, H);
++	wpa_hexdump_key(_MSG_EXCESSIVE_, "Hash subkey H for GHASH",
++			H, AES_BLOCK_SIZE);
++	return aes;
++}
++
++
++static void aes_gcm_prepare_j0(const u8 *iv, size_t iv_len, const u8 *H, u8 *J0)
++{
++	u8 len_buf[16];
++
++	if (iv_len == 12) {
++		/* Prepare block J_0 = IV || 0^31 || 1 [len(IV) = 96] */
++		os_memcpy(J0, iv, iv_len);
++		os_memset(J0 + iv_len, 0, AES_BLOCK_SIZE - iv_len);
++		J0[AES_BLOCK_SIZE - 1] = 0x01;
++	} else {
++		/*
++		 * s = 128 * ceil(len(IV)/128) - len(IV)
++		 * J_0 = GHASH_H(IV || 0^(s+64) || [len(IV)]_64)
++		 */
++		ghash_start(J0);
++		ghash(H, iv, iv_len, J0);
++		WPA_PUT_BE64(len_buf, 0);
++		WPA_PUT_BE64(len_buf + 8, iv_len * 8);
++		ghash(H, len_buf, sizeof(len_buf), J0);
++	}
++}
++
++
++static void aes_gcm_gctr(void *aes, const u8 *J0, const u8 *in, size_t len,
++			 u8 *out)
++{
++	u8 J0inc[AES_BLOCK_SIZE];
++
++	if (len == 0)
++		return;
++
++	os_memcpy(J0inc, J0, AES_BLOCK_SIZE);
++	inc32(J0inc);
++	aes_gctr(aes, J0inc, in, len, out);
++}
++
++
++static void aes_gcm_ghash(const u8 *H, const u8 *aad, size_t aad_len,
++			  const u8 *crypt, size_t crypt_len, u8 *S)
++{
++	u8 len_buf[16];
++
++	/*
++	 * u = 128 * ceil[len(C)/128] - len(C)
++	 * v = 128 * ceil[len(A)/128] - len(A)
++	 * S = GHASH_H(A || 0^v || C || 0^u || [len(A)]64 || [len(C)]64)
++	 * (i.e., zero padded to block size A || C and lengths of each in bits)
++	 */
++	ghash_start(S);
++	ghash(H, aad, aad_len, S);
++	ghash(H, crypt, crypt_len, S);
++	WPA_PUT_BE64(len_buf, aad_len * 8);
++	WPA_PUT_BE64(len_buf + 8, crypt_len * 8);
++	ghash(H, len_buf, sizeof(len_buf), S);
++
++	wpa_hexdump_key(_MSG_EXCESSIVE_, "S = GHASH_H(...)", S, 16);
++}
++
++
++/**
++ * aes_gcm_ae - GCM-AE_K(IV, P, A)
++ */
++int aes_gcm_ae(const u8 *key, size_t key_len, const u8 *iv, size_t iv_len,
++	       const u8 *plain, size_t plain_len,
++	       const u8 *aad, size_t aad_len, u8 *crypt, u8 *tag)
++{
++	u8 H[AES_BLOCK_SIZE];
++	u8 J0[AES_BLOCK_SIZE];
++	u8 S[16];
++	void *aes;
++
++	aes = aes_gcm_init_hash_subkey(key, key_len, H);
++	if (aes == NULL)
++		return -1;
++
++	aes_gcm_prepare_j0(iv, iv_len, H, J0);
++
++	/* C = GCTR_K(inc_32(J_0), P) */
++	aes_gcm_gctr(aes, J0, plain, plain_len, crypt);
++
++	aes_gcm_ghash(H, aad, aad_len, crypt, plain_len, S);
++
++	/* T = MSB_t(GCTR_K(J_0, S)) */
++	aes_gctr(aes, J0, S, sizeof(S), tag);
++
++	/* Return (C, T) */
++
++	aes_encrypt_deinit(aes);
++
++	return 0;
++}
++
++
++/**
++ * aes_gcm_ad - GCM-AD_K(IV, C, A, T)
++ */
++int aes_gcm_ad(const u8 *key, size_t key_len, const u8 *iv, size_t iv_len,
++	       const u8 *crypt, size_t crypt_len,
++	       const u8 *aad, size_t aad_len, const u8 *tag, u8 *plain)
++{
++	u8 H[AES_BLOCK_SIZE];
++	u8 J0[AES_BLOCK_SIZE];
++	u8 S[16], T[16];
++	void *aes;
++
++	aes = aes_gcm_init_hash_subkey(key, key_len, H);
++	if (aes == NULL)
++		return -1;
++
++	aes_gcm_prepare_j0(iv, iv_len, H, J0);
++
++	/* P = GCTR_K(inc_32(J_0), C) */
++	aes_gcm_gctr(aes, J0, crypt, crypt_len, plain);
++
++	aes_gcm_ghash(H, aad, aad_len, crypt, crypt_len, S);
++
++	/* T' = MSB_t(GCTR_K(J_0, S)) */
++	aes_gctr(aes, J0, S, sizeof(S), T);
++
++	aes_encrypt_deinit(aes);
++
++	if (os_memcmp_const(tag, T, 16) != 0) {
++		wpa_printf(_MSG_EXCESSIVE_, "GCM: Tag mismatch");
++		return -1;
++	}
++
++	return 0;
++}
++
++
++int aes_gmac(const u8 *key, size_t key_len, const u8 *iv, size_t iv_len,
++	     const u8 *aad, size_t aad_len, u8 *tag)
++{
++	return aes_gcm_ae(key, key_len, iv, iv_len, NULL, 0, aad, aad_len, NULL,
++			  tag);
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-internal-enc.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-internal-enc.c
+new file mode 100644
+index 000000000..69e256be9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-internal-enc.c
+@@ -0,0 +1,129 @@
++/*
++ * AES (Rijndael) cipher - encrypt
++ *
++ * Modifications to public domain implementation:
++ * - cleanup
++ * - use C pre-processor to make it easier to change S table access
++ * - added option (AES_SMALL_TABLES) for reducing code size by about 8 kB at
++ *   cost of reduced throughput (quite small difference on Pentium 4,
++ *   10-25% when using -O1 or -O2 optimization)
++ *
++ * Copyright (c) 2003-2012, Jouni Malinen <j@w1.fi>
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#include "rtw_crypto_wrap.h"
++
++#include "aes_i.h"
++
++static void rijndaelEncrypt(const u32 rk[], int Nr, const u8 pt[16], u8 ct[16])
++{
++	u32 s0, s1, s2, s3, t0, t1, t2, t3;
++#ifndef FULL_UNROLL
++	int r;
++#endif /* ?FULL_UNROLL */
++
++	/*
++	 * map byte array block to cipher state
++	 * and add initial round key:
++	 */
++	s0 = GETU32(pt     ) ^ rk[0];
++	s1 = GETU32(pt +  4) ^ rk[1];
++	s2 = GETU32(pt +  8) ^ rk[2];
++	s3 = GETU32(pt + 12) ^ rk[3];
++
++#define ROUND(i,d,s) \
++d##0 = TE0(s##0) ^ TE1(s##1) ^ TE2(s##2) ^ TE3(s##3) ^ rk[4 * i]; \
++d##1 = TE0(s##1) ^ TE1(s##2) ^ TE2(s##3) ^ TE3(s##0) ^ rk[4 * i + 1]; \
++d##2 = TE0(s##2) ^ TE1(s##3) ^ TE2(s##0) ^ TE3(s##1) ^ rk[4 * i + 2]; \
++d##3 = TE0(s##3) ^ TE1(s##0) ^ TE2(s##1) ^ TE3(s##2) ^ rk[4 * i + 3]
++
++#ifdef FULL_UNROLL
++
++	ROUND(1,t,s);
++	ROUND(2,s,t);
++	ROUND(3,t,s);
++	ROUND(4,s,t);
++	ROUND(5,t,s);
++	ROUND(6,s,t);
++	ROUND(7,t,s);
++	ROUND(8,s,t);
++	ROUND(9,t,s);
++	if (Nr > 10) {
++		ROUND(10,s,t);
++		ROUND(11,t,s);
++		if (Nr > 12) {
++			ROUND(12,s,t);
++			ROUND(13,t,s);
++		}
++	}
++
++	rk += Nr << 2;
++
++#else  /* !FULL_UNROLL */
++
++	/* Nr - 1 full rounds: */
++	r = Nr >> 1;
++	for (;;) {
++		ROUND(1,t,s);
++		rk += 8;
++		if (--r == 0)
++			break;
++		ROUND(0,s,t);
++	}
++
++#endif /* ?FULL_UNROLL */
++
++#undef ROUND
++
++	/*
++	 * apply last round and
++	 * map cipher state to byte array block:
++	 */
++	s0 = TE41(t0) ^ TE42(t1) ^ TE43(t2) ^ TE44(t3) ^ rk[0];
++	PUTU32(ct     , s0);
++	s1 = TE41(t1) ^ TE42(t2) ^ TE43(t3) ^ TE44(t0) ^ rk[1];
++	PUTU32(ct +  4, s1);
++	s2 = TE41(t2) ^ TE42(t3) ^ TE43(t0) ^ TE44(t1) ^ rk[2];
++	PUTU32(ct +  8, s2);
++	s3 = TE41(t3) ^ TE42(t0) ^ TE43(t1) ^ TE44(t2) ^ rk[3];
++	PUTU32(ct + 12, s3);
++}
++
++
++void * aes_encrypt_init(const u8 *key, size_t len)
++{
++	u32 *rk;
++	int res;
++
++	if (TEST_FAIL())
++		return NULL;
++
++	rk = os_malloc(AES_PRIV_SIZE);
++	if (rk == NULL)
++		return NULL;
++	res = rijndaelKeySetupEnc(rk, key, len * 8);
++	if (res < 0) {
++		rtw_mfree(rk, AES_PRIV_SIZE);
++		return NULL;
++	}
++	rk[AES_PRIV_NR_POS] = res;
++	return rk;
++}
++
++
++int aes_encrypt(void *ctx, const u8 *plain, u8 *crypt)
++{
++	u32 *rk = ctx;
++	rijndaelEncrypt(ctx, rk[AES_PRIV_NR_POS], plain, crypt);
++	return 0;
++}
++
++
++void aes_encrypt_deinit(void *ctx)
++{
++	os_memset(ctx, 0, AES_PRIV_SIZE);
++	rtw_mfree(ctx, AES_PRIV_SIZE);
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-internal.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-internal.c
+new file mode 100644
+index 000000000..57d653949
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-internal.c
+@@ -0,0 +1,843 @@
++/*
++ * AES (Rijndael) cipher
++ *
++ * Modifications to public domain implementation:
++ * - cleanup
++ * - use C pre-processor to make it easier to change S table access
++ * - added option (AES_SMALL_TABLES) for reducing code size by about 8 kB at
++ *   cost of reduced throughput (quite small difference on Pentium 4,
++ *   10-25% when using -O1 or -O2 optimization)
++ *
++ * Copyright (c) 2003-2012, Jouni Malinen <j@w1.fi>
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#include "rtw_crypto_wrap.h"
++
++#include "aes_i.h"
++
++/*
++ * rijndael-alg-fst.c
++ *
++ * @version 3.0 (December 2000)
++ *
++ * Optimised ANSI C code for the Rijndael cipher (now AES)
++ *
++ * @author Vincent Rijmen <vincent.rijmen@esat.kuleuven.ac.be>
++ * @author Antoon Bosselaers <antoon.bosselaers@esat.kuleuven.ac.be>
++ * @author Paulo Barreto <paulo.barreto@terra.com.br>
++ *
++ * This code is hereby placed in the public domain.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ''AS IS'' AND ANY EXPRESS
++ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
++ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
++ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
++ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++
++/*
++Te0[x] = S [x].[02, 01, 01, 03];
++Te1[x] = S [x].[03, 02, 01, 01];
++Te2[x] = S [x].[01, 03, 02, 01];
++Te3[x] = S [x].[01, 01, 03, 02];
++Te4[x] = S [x].[01, 01, 01, 01];
++
++Td0[x] = Si[x].[0e, 09, 0d, 0b];
++Td1[x] = Si[x].[0b, 0e, 09, 0d];
++Td2[x] = Si[x].[0d, 0b, 0e, 09];
++Td3[x] = Si[x].[09, 0d, 0b, 0e];
++Td4[x] = Si[x].[01, 01, 01, 01];
++*/
++
++const u32 Te0[256] = {
++    0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU,
++    0xfff2f20dU, 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U,
++    0x60303050U, 0x02010103U, 0xce6767a9U, 0x562b2b7dU,
++    0xe7fefe19U, 0xb5d7d762U, 0x4dababe6U, 0xec76769aU,
++    0x8fcaca45U, 0x1f82829dU, 0x89c9c940U, 0xfa7d7d87U,
++    0xeffafa15U, 0xb25959ebU, 0x8e4747c9U, 0xfbf0f00bU,
++    0x41adadecU, 0xb3d4d467U, 0x5fa2a2fdU, 0x45afafeaU,
++    0x239c9cbfU, 0x53a4a4f7U, 0xe4727296U, 0x9bc0c05bU,
++    0x75b7b7c2U, 0xe1fdfd1cU, 0x3d9393aeU, 0x4c26266aU,
++    0x6c36365aU, 0x7e3f3f41U, 0xf5f7f702U, 0x83cccc4fU,
++    0x6834345cU, 0x51a5a5f4U, 0xd1e5e534U, 0xf9f1f108U,
++    0xe2717193U, 0xabd8d873U, 0x62313153U, 0x2a15153fU,
++    0x0804040cU, 0x95c7c752U, 0x46232365U, 0x9dc3c35eU,
++    0x30181828U, 0x379696a1U, 0x0a05050fU, 0x2f9a9ab5U,
++    0x0e070709U, 0x24121236U, 0x1b80809bU, 0xdfe2e23dU,
++    0xcdebeb26U, 0x4e272769U, 0x7fb2b2cdU, 0xea75759fU,
++    0x1209091bU, 0x1d83839eU, 0x582c2c74U, 0x341a1a2eU,
++    0x361b1b2dU, 0xdc6e6eb2U, 0xb45a5aeeU, 0x5ba0a0fbU,
++    0xa45252f6U, 0x763b3b4dU, 0xb7d6d661U, 0x7db3b3ceU,
++    0x5229297bU, 0xdde3e33eU, 0x5e2f2f71U, 0x13848497U,
++    0xa65353f5U, 0xb9d1d168U, 0x00000000U, 0xc1eded2cU,
++    0x40202060U, 0xe3fcfc1fU, 0x79b1b1c8U, 0xb65b5bedU,
++    0xd46a6abeU, 0x8dcbcb46U, 0x67bebed9U, 0x7239394bU,
++    0x944a4adeU, 0x984c4cd4U, 0xb05858e8U, 0x85cfcf4aU,
++    0xbbd0d06bU, 0xc5efef2aU, 0x4faaaae5U, 0xedfbfb16U,
++    0x864343c5U, 0x9a4d4dd7U, 0x66333355U, 0x11858594U,
++    0x8a4545cfU, 0xe9f9f910U, 0x04020206U, 0xfe7f7f81U,
++    0xa05050f0U, 0x783c3c44U, 0x259f9fbaU, 0x4ba8a8e3U,
++    0xa25151f3U, 0x5da3a3feU, 0x804040c0U, 0x058f8f8aU,
++    0x3f9292adU, 0x219d9dbcU, 0x70383848U, 0xf1f5f504U,
++    0x63bcbcdfU, 0x77b6b6c1U, 0xafdada75U, 0x42212163U,
++    0x20101030U, 0xe5ffff1aU, 0xfdf3f30eU, 0xbfd2d26dU,
++    0x81cdcd4cU, 0x180c0c14U, 0x26131335U, 0xc3ecec2fU,
++    0xbe5f5fe1U, 0x359797a2U, 0x884444ccU, 0x2e171739U,
++    0x93c4c457U, 0x55a7a7f2U, 0xfc7e7e82U, 0x7a3d3d47U,
++    0xc86464acU, 0xba5d5de7U, 0x3219192bU, 0xe6737395U,
++    0xc06060a0U, 0x19818198U, 0x9e4f4fd1U, 0xa3dcdc7fU,
++    0x44222266U, 0x542a2a7eU, 0x3b9090abU, 0x0b888883U,
++    0x8c4646caU, 0xc7eeee29U, 0x6bb8b8d3U, 0x2814143cU,
++    0xa7dede79U, 0xbc5e5ee2U, 0x160b0b1dU, 0xaddbdb76U,
++    0xdbe0e03bU, 0x64323256U, 0x743a3a4eU, 0x140a0a1eU,
++    0x924949dbU, 0x0c06060aU, 0x4824246cU, 0xb85c5ce4U,
++    0x9fc2c25dU, 0xbdd3d36eU, 0x43acacefU, 0xc46262a6U,
++    0x399191a8U, 0x319595a4U, 0xd3e4e437U, 0xf279798bU,
++    0xd5e7e732U, 0x8bc8c843U, 0x6e373759U, 0xda6d6db7U,
++    0x018d8d8cU, 0xb1d5d564U, 0x9c4e4ed2U, 0x49a9a9e0U,
++    0xd86c6cb4U, 0xac5656faU, 0xf3f4f407U, 0xcfeaea25U,
++    0xca6565afU, 0xf47a7a8eU, 0x47aeaee9U, 0x10080818U,
++    0x6fbabad5U, 0xf0787888U, 0x4a25256fU, 0x5c2e2e72U,
++    0x381c1c24U, 0x57a6a6f1U, 0x73b4b4c7U, 0x97c6c651U,
++    0xcbe8e823U, 0xa1dddd7cU, 0xe874749cU, 0x3e1f1f21U,
++    0x964b4bddU, 0x61bdbddcU, 0x0d8b8b86U, 0x0f8a8a85U,
++    0xe0707090U, 0x7c3e3e42U, 0x71b5b5c4U, 0xcc6666aaU,
++    0x904848d8U, 0x06030305U, 0xf7f6f601U, 0x1c0e0e12U,
++    0xc26161a3U, 0x6a35355fU, 0xae5757f9U, 0x69b9b9d0U,
++    0x17868691U, 0x99c1c158U, 0x3a1d1d27U, 0x279e9eb9U,
++    0xd9e1e138U, 0xebf8f813U, 0x2b9898b3U, 0x22111133U,
++    0xd26969bbU, 0xa9d9d970U, 0x078e8e89U, 0x339494a7U,
++    0x2d9b9bb6U, 0x3c1e1e22U, 0x15878792U, 0xc9e9e920U,
++    0x87cece49U, 0xaa5555ffU, 0x50282878U, 0xa5dfdf7aU,
++    0x038c8c8fU, 0x59a1a1f8U, 0x09898980U, 0x1a0d0d17U,
++    0x65bfbfdaU, 0xd7e6e631U, 0x844242c6U, 0xd06868b8U,
++    0x824141c3U, 0x299999b0U, 0x5a2d2d77U, 0x1e0f0f11U,
++    0x7bb0b0cbU, 0xa85454fcU, 0x6dbbbbd6U, 0x2c16163aU,
++};
++#ifndef AES_SMALL_TABLES
++const u32 Te1[256] = {
++    0xa5c66363U, 0x84f87c7cU, 0x99ee7777U, 0x8df67b7bU,
++    0x0dfff2f2U, 0xbdd66b6bU, 0xb1de6f6fU, 0x5491c5c5U,
++    0x50603030U, 0x03020101U, 0xa9ce6767U, 0x7d562b2bU,
++    0x19e7fefeU, 0x62b5d7d7U, 0xe64dababU, 0x9aec7676U,
++    0x458fcacaU, 0x9d1f8282U, 0x4089c9c9U, 0x87fa7d7dU,
++    0x15effafaU, 0xebb25959U, 0xc98e4747U, 0x0bfbf0f0U,
++    0xec41adadU, 0x67b3d4d4U, 0xfd5fa2a2U, 0xea45afafU,
++    0xbf239c9cU, 0xf753a4a4U, 0x96e47272U, 0x5b9bc0c0U,
++    0xc275b7b7U, 0x1ce1fdfdU, 0xae3d9393U, 0x6a4c2626U,
++    0x5a6c3636U, 0x417e3f3fU, 0x02f5f7f7U, 0x4f83ccccU,
++    0x5c683434U, 0xf451a5a5U, 0x34d1e5e5U, 0x08f9f1f1U,
++    0x93e27171U, 0x73abd8d8U, 0x53623131U, 0x3f2a1515U,
++    0x0c080404U, 0x5295c7c7U, 0x65462323U, 0x5e9dc3c3U,
++    0x28301818U, 0xa1379696U, 0x0f0a0505U, 0xb52f9a9aU,
++    0x090e0707U, 0x36241212U, 0x9b1b8080U, 0x3ddfe2e2U,
++    0x26cdebebU, 0x694e2727U, 0xcd7fb2b2U, 0x9fea7575U,
++    0x1b120909U, 0x9e1d8383U, 0x74582c2cU, 0x2e341a1aU,
++    0x2d361b1bU, 0xb2dc6e6eU, 0xeeb45a5aU, 0xfb5ba0a0U,
++    0xf6a45252U, 0x4d763b3bU, 0x61b7d6d6U, 0xce7db3b3U,
++    0x7b522929U, 0x3edde3e3U, 0x715e2f2fU, 0x97138484U,
++    0xf5a65353U, 0x68b9d1d1U, 0x00000000U, 0x2cc1ededU,
++    0x60402020U, 0x1fe3fcfcU, 0xc879b1b1U, 0xedb65b5bU,
++    0xbed46a6aU, 0x468dcbcbU, 0xd967bebeU, 0x4b723939U,
++    0xde944a4aU, 0xd4984c4cU, 0xe8b05858U, 0x4a85cfcfU,
++    0x6bbbd0d0U, 0x2ac5efefU, 0xe54faaaaU, 0x16edfbfbU,
++    0xc5864343U, 0xd79a4d4dU, 0x55663333U, 0x94118585U,
++    0xcf8a4545U, 0x10e9f9f9U, 0x06040202U, 0x81fe7f7fU,
++    0xf0a05050U, 0x44783c3cU, 0xba259f9fU, 0xe34ba8a8U,
++    0xf3a25151U, 0xfe5da3a3U, 0xc0804040U, 0x8a058f8fU,
++    0xad3f9292U, 0xbc219d9dU, 0x48703838U, 0x04f1f5f5U,
++    0xdf63bcbcU, 0xc177b6b6U, 0x75afdadaU, 0x63422121U,
++    0x30201010U, 0x1ae5ffffU, 0x0efdf3f3U, 0x6dbfd2d2U,
++    0x4c81cdcdU, 0x14180c0cU, 0x35261313U, 0x2fc3ececU,
++    0xe1be5f5fU, 0xa2359797U, 0xcc884444U, 0x392e1717U,
++    0x5793c4c4U, 0xf255a7a7U, 0x82fc7e7eU, 0x477a3d3dU,
++    0xacc86464U, 0xe7ba5d5dU, 0x2b321919U, 0x95e67373U,
++    0xa0c06060U, 0x98198181U, 0xd19e4f4fU, 0x7fa3dcdcU,
++    0x66442222U, 0x7e542a2aU, 0xab3b9090U, 0x830b8888U,
++    0xca8c4646U, 0x29c7eeeeU, 0xd36bb8b8U, 0x3c281414U,
++    0x79a7dedeU, 0xe2bc5e5eU, 0x1d160b0bU, 0x76addbdbU,
++    0x3bdbe0e0U, 0x56643232U, 0x4e743a3aU, 0x1e140a0aU,
++    0xdb924949U, 0x0a0c0606U, 0x6c482424U, 0xe4b85c5cU,
++    0x5d9fc2c2U, 0x6ebdd3d3U, 0xef43acacU, 0xa6c46262U,
++    0xa8399191U, 0xa4319595U, 0x37d3e4e4U, 0x8bf27979U,
++    0x32d5e7e7U, 0x438bc8c8U, 0x596e3737U, 0xb7da6d6dU,
++    0x8c018d8dU, 0x64b1d5d5U, 0xd29c4e4eU, 0xe049a9a9U,
++    0xb4d86c6cU, 0xfaac5656U, 0x07f3f4f4U, 0x25cfeaeaU,
++    0xafca6565U, 0x8ef47a7aU, 0xe947aeaeU, 0x18100808U,
++    0xd56fbabaU, 0x88f07878U, 0x6f4a2525U, 0x725c2e2eU,
++    0x24381c1cU, 0xf157a6a6U, 0xc773b4b4U, 0x5197c6c6U,
++    0x23cbe8e8U, 0x7ca1ddddU, 0x9ce87474U, 0x213e1f1fU,
++    0xdd964b4bU, 0xdc61bdbdU, 0x860d8b8bU, 0x850f8a8aU,
++    0x90e07070U, 0x427c3e3eU, 0xc471b5b5U, 0xaacc6666U,
++    0xd8904848U, 0x05060303U, 0x01f7f6f6U, 0x121c0e0eU,
++    0xa3c26161U, 0x5f6a3535U, 0xf9ae5757U, 0xd069b9b9U,
++    0x91178686U, 0x5899c1c1U, 0x273a1d1dU, 0xb9279e9eU,
++    0x38d9e1e1U, 0x13ebf8f8U, 0xb32b9898U, 0x33221111U,
++    0xbbd26969U, 0x70a9d9d9U, 0x89078e8eU, 0xa7339494U,
++    0xb62d9b9bU, 0x223c1e1eU, 0x92158787U, 0x20c9e9e9U,
++    0x4987ceceU, 0xffaa5555U, 0x78502828U, 0x7aa5dfdfU,
++    0x8f038c8cU, 0xf859a1a1U, 0x80098989U, 0x171a0d0dU,
++    0xda65bfbfU, 0x31d7e6e6U, 0xc6844242U, 0xb8d06868U,
++    0xc3824141U, 0xb0299999U, 0x775a2d2dU, 0x111e0f0fU,
++    0xcb7bb0b0U, 0xfca85454U, 0xd66dbbbbU, 0x3a2c1616U,
++};
++const u32 Te2[256] = {
++    0x63a5c663U, 0x7c84f87cU, 0x7799ee77U, 0x7b8df67bU,
++    0xf20dfff2U, 0x6bbdd66bU, 0x6fb1de6fU, 0xc55491c5U,
++    0x30506030U, 0x01030201U, 0x67a9ce67U, 0x2b7d562bU,
++    0xfe19e7feU, 0xd762b5d7U, 0xabe64dabU, 0x769aec76U,
++    0xca458fcaU, 0x829d1f82U, 0xc94089c9U, 0x7d87fa7dU,
++    0xfa15effaU, 0x59ebb259U, 0x47c98e47U, 0xf00bfbf0U,
++    0xadec41adU, 0xd467b3d4U, 0xa2fd5fa2U, 0xafea45afU,
++    0x9cbf239cU, 0xa4f753a4U, 0x7296e472U, 0xc05b9bc0U,
++    0xb7c275b7U, 0xfd1ce1fdU, 0x93ae3d93U, 0x266a4c26U,
++    0x365a6c36U, 0x3f417e3fU, 0xf702f5f7U, 0xcc4f83ccU,
++    0x345c6834U, 0xa5f451a5U, 0xe534d1e5U, 0xf108f9f1U,
++    0x7193e271U, 0xd873abd8U, 0x31536231U, 0x153f2a15U,
++    0x040c0804U, 0xc75295c7U, 0x23654623U, 0xc35e9dc3U,
++    0x18283018U, 0x96a13796U, 0x050f0a05U, 0x9ab52f9aU,
++    0x07090e07U, 0x12362412U, 0x809b1b80U, 0xe23ddfe2U,
++    0xeb26cdebU, 0x27694e27U, 0xb2cd7fb2U, 0x759fea75U,
++    0x091b1209U, 0x839e1d83U, 0x2c74582cU, 0x1a2e341aU,
++    0x1b2d361bU, 0x6eb2dc6eU, 0x5aeeb45aU, 0xa0fb5ba0U,
++    0x52f6a452U, 0x3b4d763bU, 0xd661b7d6U, 0xb3ce7db3U,
++    0x297b5229U, 0xe33edde3U, 0x2f715e2fU, 0x84971384U,
++    0x53f5a653U, 0xd168b9d1U, 0x00000000U, 0xed2cc1edU,
++    0x20604020U, 0xfc1fe3fcU, 0xb1c879b1U, 0x5bedb65bU,
++    0x6abed46aU, 0xcb468dcbU, 0xbed967beU, 0x394b7239U,
++    0x4ade944aU, 0x4cd4984cU, 0x58e8b058U, 0xcf4a85cfU,
++    0xd06bbbd0U, 0xef2ac5efU, 0xaae54faaU, 0xfb16edfbU,
++    0x43c58643U, 0x4dd79a4dU, 0x33556633U, 0x85941185U,
++    0x45cf8a45U, 0xf910e9f9U, 0x02060402U, 0x7f81fe7fU,
++    0x50f0a050U, 0x3c44783cU, 0x9fba259fU, 0xa8e34ba8U,
++    0x51f3a251U, 0xa3fe5da3U, 0x40c08040U, 0x8f8a058fU,
++    0x92ad3f92U, 0x9dbc219dU, 0x38487038U, 0xf504f1f5U,
++    0xbcdf63bcU, 0xb6c177b6U, 0xda75afdaU, 0x21634221U,
++    0x10302010U, 0xff1ae5ffU, 0xf30efdf3U, 0xd26dbfd2U,
++    0xcd4c81cdU, 0x0c14180cU, 0x13352613U, 0xec2fc3ecU,
++    0x5fe1be5fU, 0x97a23597U, 0x44cc8844U, 0x17392e17U,
++    0xc45793c4U, 0xa7f255a7U, 0x7e82fc7eU, 0x3d477a3dU,
++    0x64acc864U, 0x5de7ba5dU, 0x192b3219U, 0x7395e673U,
++    0x60a0c060U, 0x81981981U, 0x4fd19e4fU, 0xdc7fa3dcU,
++    0x22664422U, 0x2a7e542aU, 0x90ab3b90U, 0x88830b88U,
++    0x46ca8c46U, 0xee29c7eeU, 0xb8d36bb8U, 0x143c2814U,
++    0xde79a7deU, 0x5ee2bc5eU, 0x0b1d160bU, 0xdb76addbU,
++    0xe03bdbe0U, 0x32566432U, 0x3a4e743aU, 0x0a1e140aU,
++    0x49db9249U, 0x060a0c06U, 0x246c4824U, 0x5ce4b85cU,
++    0xc25d9fc2U, 0xd36ebdd3U, 0xacef43acU, 0x62a6c462U,
++    0x91a83991U, 0x95a43195U, 0xe437d3e4U, 0x798bf279U,
++    0xe732d5e7U, 0xc8438bc8U, 0x37596e37U, 0x6db7da6dU,
++    0x8d8c018dU, 0xd564b1d5U, 0x4ed29c4eU, 0xa9e049a9U,
++    0x6cb4d86cU, 0x56faac56U, 0xf407f3f4U, 0xea25cfeaU,
++    0x65afca65U, 0x7a8ef47aU, 0xaee947aeU, 0x08181008U,
++    0xbad56fbaU, 0x7888f078U, 0x256f4a25U, 0x2e725c2eU,
++    0x1c24381cU, 0xa6f157a6U, 0xb4c773b4U, 0xc65197c6U,
++    0xe823cbe8U, 0xdd7ca1ddU, 0x749ce874U, 0x1f213e1fU,
++    0x4bdd964bU, 0xbddc61bdU, 0x8b860d8bU, 0x8a850f8aU,
++    0x7090e070U, 0x3e427c3eU, 0xb5c471b5U, 0x66aacc66U,
++    0x48d89048U, 0x03050603U, 0xf601f7f6U, 0x0e121c0eU,
++    0x61a3c261U, 0x355f6a35U, 0x57f9ae57U, 0xb9d069b9U,
++    0x86911786U, 0xc15899c1U, 0x1d273a1dU, 0x9eb9279eU,
++    0xe138d9e1U, 0xf813ebf8U, 0x98b32b98U, 0x11332211U,
++    0x69bbd269U, 0xd970a9d9U, 0x8e89078eU, 0x94a73394U,
++    0x9bb62d9bU, 0x1e223c1eU, 0x87921587U, 0xe920c9e9U,
++    0xce4987ceU, 0x55ffaa55U, 0x28785028U, 0xdf7aa5dfU,
++    0x8c8f038cU, 0xa1f859a1U, 0x89800989U, 0x0d171a0dU,
++    0xbfda65bfU, 0xe631d7e6U, 0x42c68442U, 0x68b8d068U,
++    0x41c38241U, 0x99b02999U, 0x2d775a2dU, 0x0f111e0fU,
++    0xb0cb7bb0U, 0x54fca854U, 0xbbd66dbbU, 0x163a2c16U,
++};
++const u32 Te3[256] = {
++
++    0x6363a5c6U, 0x7c7c84f8U, 0x777799eeU, 0x7b7b8df6U,
++    0xf2f20dffU, 0x6b6bbdd6U, 0x6f6fb1deU, 0xc5c55491U,
++    0x30305060U, 0x01010302U, 0x6767a9ceU, 0x2b2b7d56U,
++    0xfefe19e7U, 0xd7d762b5U, 0xababe64dU, 0x76769aecU,
++    0xcaca458fU, 0x82829d1fU, 0xc9c94089U, 0x7d7d87faU,
++    0xfafa15efU, 0x5959ebb2U, 0x4747c98eU, 0xf0f00bfbU,
++    0xadadec41U, 0xd4d467b3U, 0xa2a2fd5fU, 0xafafea45U,
++    0x9c9cbf23U, 0xa4a4f753U, 0x727296e4U, 0xc0c05b9bU,
++    0xb7b7c275U, 0xfdfd1ce1U, 0x9393ae3dU, 0x26266a4cU,
++    0x36365a6cU, 0x3f3f417eU, 0xf7f702f5U, 0xcccc4f83U,
++    0x34345c68U, 0xa5a5f451U, 0xe5e534d1U, 0xf1f108f9U,
++    0x717193e2U, 0xd8d873abU, 0x31315362U, 0x15153f2aU,
++    0x04040c08U, 0xc7c75295U, 0x23236546U, 0xc3c35e9dU,
++    0x18182830U, 0x9696a137U, 0x05050f0aU, 0x9a9ab52fU,
++    0x0707090eU, 0x12123624U, 0x80809b1bU, 0xe2e23ddfU,
++    0xebeb26cdU, 0x2727694eU, 0xb2b2cd7fU, 0x75759feaU,
++    0x09091b12U, 0x83839e1dU, 0x2c2c7458U, 0x1a1a2e34U,
++    0x1b1b2d36U, 0x6e6eb2dcU, 0x5a5aeeb4U, 0xa0a0fb5bU,
++    0x5252f6a4U, 0x3b3b4d76U, 0xd6d661b7U, 0xb3b3ce7dU,
++    0x29297b52U, 0xe3e33eddU, 0x2f2f715eU, 0x84849713U,
++    0x5353f5a6U, 0xd1d168b9U, 0x00000000U, 0xeded2cc1U,
++    0x20206040U, 0xfcfc1fe3U, 0xb1b1c879U, 0x5b5bedb6U,
++    0x6a6abed4U, 0xcbcb468dU, 0xbebed967U, 0x39394b72U,
++    0x4a4ade94U, 0x4c4cd498U, 0x5858e8b0U, 0xcfcf4a85U,
++    0xd0d06bbbU, 0xefef2ac5U, 0xaaaae54fU, 0xfbfb16edU,
++    0x4343c586U, 0x4d4dd79aU, 0x33335566U, 0x85859411U,
++    0x4545cf8aU, 0xf9f910e9U, 0x02020604U, 0x7f7f81feU,
++    0x5050f0a0U, 0x3c3c4478U, 0x9f9fba25U, 0xa8a8e34bU,
++    0x5151f3a2U, 0xa3a3fe5dU, 0x4040c080U, 0x8f8f8a05U,
++    0x9292ad3fU, 0x9d9dbc21U, 0x38384870U, 0xf5f504f1U,
++    0xbcbcdf63U, 0xb6b6c177U, 0xdada75afU, 0x21216342U,
++    0x10103020U, 0xffff1ae5U, 0xf3f30efdU, 0xd2d26dbfU,
++    0xcdcd4c81U, 0x0c0c1418U, 0x13133526U, 0xecec2fc3U,
++    0x5f5fe1beU, 0x9797a235U, 0x4444cc88U, 0x1717392eU,
++    0xc4c45793U, 0xa7a7f255U, 0x7e7e82fcU, 0x3d3d477aU,
++    0x6464acc8U, 0x5d5de7baU, 0x19192b32U, 0x737395e6U,
++    0x6060a0c0U, 0x81819819U, 0x4f4fd19eU, 0xdcdc7fa3U,
++    0x22226644U, 0x2a2a7e54U, 0x9090ab3bU, 0x8888830bU,
++    0x4646ca8cU, 0xeeee29c7U, 0xb8b8d36bU, 0x14143c28U,
++    0xdede79a7U, 0x5e5ee2bcU, 0x0b0b1d16U, 0xdbdb76adU,
++    0xe0e03bdbU, 0x32325664U, 0x3a3a4e74U, 0x0a0a1e14U,
++    0x4949db92U, 0x06060a0cU, 0x24246c48U, 0x5c5ce4b8U,
++    0xc2c25d9fU, 0xd3d36ebdU, 0xacacef43U, 0x6262a6c4U,
++    0x9191a839U, 0x9595a431U, 0xe4e437d3U, 0x79798bf2U,
++    0xe7e732d5U, 0xc8c8438bU, 0x3737596eU, 0x6d6db7daU,
++    0x8d8d8c01U, 0xd5d564b1U, 0x4e4ed29cU, 0xa9a9e049U,
++    0x6c6cb4d8U, 0x5656faacU, 0xf4f407f3U, 0xeaea25cfU,
++    0x6565afcaU, 0x7a7a8ef4U, 0xaeaee947U, 0x08081810U,
++    0xbabad56fU, 0x787888f0U, 0x25256f4aU, 0x2e2e725cU,
++    0x1c1c2438U, 0xa6a6f157U, 0xb4b4c773U, 0xc6c65197U,
++    0xe8e823cbU, 0xdddd7ca1U, 0x74749ce8U, 0x1f1f213eU,
++    0x4b4bdd96U, 0xbdbddc61U, 0x8b8b860dU, 0x8a8a850fU,
++    0x707090e0U, 0x3e3e427cU, 0xb5b5c471U, 0x6666aaccU,
++    0x4848d890U, 0x03030506U, 0xf6f601f7U, 0x0e0e121cU,
++    0x6161a3c2U, 0x35355f6aU, 0x5757f9aeU, 0xb9b9d069U,
++    0x86869117U, 0xc1c15899U, 0x1d1d273aU, 0x9e9eb927U,
++    0xe1e138d9U, 0xf8f813ebU, 0x9898b32bU, 0x11113322U,
++    0x6969bbd2U, 0xd9d970a9U, 0x8e8e8907U, 0x9494a733U,
++    0x9b9bb62dU, 0x1e1e223cU, 0x87879215U, 0xe9e920c9U,
++    0xcece4987U, 0x5555ffaaU, 0x28287850U, 0xdfdf7aa5U,
++    0x8c8c8f03U, 0xa1a1f859U, 0x89898009U, 0x0d0d171aU,
++    0xbfbfda65U, 0xe6e631d7U, 0x4242c684U, 0x6868b8d0U,
++    0x4141c382U, 0x9999b029U, 0x2d2d775aU, 0x0f0f111eU,
++    0xb0b0cb7bU, 0x5454fca8U, 0xbbbbd66dU, 0x16163a2cU,
++};
++const u32 Te4[256] = {
++    0x63636363U, 0x7c7c7c7cU, 0x77777777U, 0x7b7b7b7bU,
++    0xf2f2f2f2U, 0x6b6b6b6bU, 0x6f6f6f6fU, 0xc5c5c5c5U,
++    0x30303030U, 0x01010101U, 0x67676767U, 0x2b2b2b2bU,
++    0xfefefefeU, 0xd7d7d7d7U, 0xababababU, 0x76767676U,
++    0xcacacacaU, 0x82828282U, 0xc9c9c9c9U, 0x7d7d7d7dU,
++    0xfafafafaU, 0x59595959U, 0x47474747U, 0xf0f0f0f0U,
++    0xadadadadU, 0xd4d4d4d4U, 0xa2a2a2a2U, 0xafafafafU,
++    0x9c9c9c9cU, 0xa4a4a4a4U, 0x72727272U, 0xc0c0c0c0U,
++    0xb7b7b7b7U, 0xfdfdfdfdU, 0x93939393U, 0x26262626U,
++    0x36363636U, 0x3f3f3f3fU, 0xf7f7f7f7U, 0xccccccccU,
++    0x34343434U, 0xa5a5a5a5U, 0xe5e5e5e5U, 0xf1f1f1f1U,
++    0x71717171U, 0xd8d8d8d8U, 0x31313131U, 0x15151515U,
++    0x04040404U, 0xc7c7c7c7U, 0x23232323U, 0xc3c3c3c3U,
++    0x18181818U, 0x96969696U, 0x05050505U, 0x9a9a9a9aU,
++    0x07070707U, 0x12121212U, 0x80808080U, 0xe2e2e2e2U,
++    0xebebebebU, 0x27272727U, 0xb2b2b2b2U, 0x75757575U,
++    0x09090909U, 0x83838383U, 0x2c2c2c2cU, 0x1a1a1a1aU,
++    0x1b1b1b1bU, 0x6e6e6e6eU, 0x5a5a5a5aU, 0xa0a0a0a0U,
++    0x52525252U, 0x3b3b3b3bU, 0xd6d6d6d6U, 0xb3b3b3b3U,
++    0x29292929U, 0xe3e3e3e3U, 0x2f2f2f2fU, 0x84848484U,
++    0x53535353U, 0xd1d1d1d1U, 0x00000000U, 0xededededU,
++    0x20202020U, 0xfcfcfcfcU, 0xb1b1b1b1U, 0x5b5b5b5bU,
++    0x6a6a6a6aU, 0xcbcbcbcbU, 0xbebebebeU, 0x39393939U,
++    0x4a4a4a4aU, 0x4c4c4c4cU, 0x58585858U, 0xcfcfcfcfU,
++    0xd0d0d0d0U, 0xefefefefU, 0xaaaaaaaaU, 0xfbfbfbfbU,
++    0x43434343U, 0x4d4d4d4dU, 0x33333333U, 0x85858585U,
++    0x45454545U, 0xf9f9f9f9U, 0x02020202U, 0x7f7f7f7fU,
++    0x50505050U, 0x3c3c3c3cU, 0x9f9f9f9fU, 0xa8a8a8a8U,
++    0x51515151U, 0xa3a3a3a3U, 0x40404040U, 0x8f8f8f8fU,
++    0x92929292U, 0x9d9d9d9dU, 0x38383838U, 0xf5f5f5f5U,
++    0xbcbcbcbcU, 0xb6b6b6b6U, 0xdadadadaU, 0x21212121U,
++    0x10101010U, 0xffffffffU, 0xf3f3f3f3U, 0xd2d2d2d2U,
++    0xcdcdcdcdU, 0x0c0c0c0cU, 0x13131313U, 0xececececU,
++    0x5f5f5f5fU, 0x97979797U, 0x44444444U, 0x17171717U,
++    0xc4c4c4c4U, 0xa7a7a7a7U, 0x7e7e7e7eU, 0x3d3d3d3dU,
++    0x64646464U, 0x5d5d5d5dU, 0x19191919U, 0x73737373U,
++    0x60606060U, 0x81818181U, 0x4f4f4f4fU, 0xdcdcdcdcU,
++    0x22222222U, 0x2a2a2a2aU, 0x90909090U, 0x88888888U,
++    0x46464646U, 0xeeeeeeeeU, 0xb8b8b8b8U, 0x14141414U,
++    0xdedededeU, 0x5e5e5e5eU, 0x0b0b0b0bU, 0xdbdbdbdbU,
++    0xe0e0e0e0U, 0x32323232U, 0x3a3a3a3aU, 0x0a0a0a0aU,
++    0x49494949U, 0x06060606U, 0x24242424U, 0x5c5c5c5cU,
++    0xc2c2c2c2U, 0xd3d3d3d3U, 0xacacacacU, 0x62626262U,
++    0x91919191U, 0x95959595U, 0xe4e4e4e4U, 0x79797979U,
++    0xe7e7e7e7U, 0xc8c8c8c8U, 0x37373737U, 0x6d6d6d6dU,
++    0x8d8d8d8dU, 0xd5d5d5d5U, 0x4e4e4e4eU, 0xa9a9a9a9U,
++    0x6c6c6c6cU, 0x56565656U, 0xf4f4f4f4U, 0xeaeaeaeaU,
++    0x65656565U, 0x7a7a7a7aU, 0xaeaeaeaeU, 0x08080808U,
++    0xbabababaU, 0x78787878U, 0x25252525U, 0x2e2e2e2eU,
++    0x1c1c1c1cU, 0xa6a6a6a6U, 0xb4b4b4b4U, 0xc6c6c6c6U,
++    0xe8e8e8e8U, 0xddddddddU, 0x74747474U, 0x1f1f1f1fU,
++    0x4b4b4b4bU, 0xbdbdbdbdU, 0x8b8b8b8bU, 0x8a8a8a8aU,
++    0x70707070U, 0x3e3e3e3eU, 0xb5b5b5b5U, 0x66666666U,
++    0x48484848U, 0x03030303U, 0xf6f6f6f6U, 0x0e0e0e0eU,
++    0x61616161U, 0x35353535U, 0x57575757U, 0xb9b9b9b9U,
++    0x86868686U, 0xc1c1c1c1U, 0x1d1d1d1dU, 0x9e9e9e9eU,
++    0xe1e1e1e1U, 0xf8f8f8f8U, 0x98989898U, 0x11111111U,
++    0x69696969U, 0xd9d9d9d9U, 0x8e8e8e8eU, 0x94949494U,
++    0x9b9b9b9bU, 0x1e1e1e1eU, 0x87878787U, 0xe9e9e9e9U,
++    0xcecececeU, 0x55555555U, 0x28282828U, 0xdfdfdfdfU,
++    0x8c8c8c8cU, 0xa1a1a1a1U, 0x89898989U, 0x0d0d0d0dU,
++    0xbfbfbfbfU, 0xe6e6e6e6U, 0x42424242U, 0x68686868U,
++    0x41414141U, 0x99999999U, 0x2d2d2d2dU, 0x0f0f0f0fU,
++    0xb0b0b0b0U, 0x54545454U, 0xbbbbbbbbU, 0x16161616U,
++};
++#endif /* AES_SMALL_TABLES */
++const u32 Td0[256] = {
++    0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U,
++    0x3bab6bcbU, 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U,
++    0x2030fa55U, 0xad766df6U, 0x88cc7691U, 0xf5024c25U,
++    0x4fe5d7fcU, 0xc52acbd7U, 0x26354480U, 0xb562a38fU,
++    0xdeb15a49U, 0x25ba1b67U, 0x45ea0e98U, 0x5dfec0e1U,
++    0xc32f7502U, 0x814cf012U, 0x8d4697a3U, 0x6bd3f9c6U,
++    0x038f5fe7U, 0x15929c95U, 0xbf6d7aebU, 0x955259daU,
++    0xd4be832dU, 0x587421d3U, 0x49e06929U, 0x8ec9c844U,
++    0x75c2896aU, 0xf48e7978U, 0x99583e6bU, 0x27b971ddU,
++    0xbee14fb6U, 0xf088ad17U, 0xc920ac66U, 0x7dce3ab4U,
++    0x63df4a18U, 0xe51a3182U, 0x97513360U, 0x62537f45U,
++    0xb16477e0U, 0xbb6bae84U, 0xfe81a01cU, 0xf9082b94U,
++    0x70486858U, 0x8f45fd19U, 0x94de6c87U, 0x527bf8b7U,
++    0xab73d323U, 0x724b02e2U, 0xe31f8f57U, 0x6655ab2aU,
++    0xb2eb2807U, 0x2fb5c203U, 0x86c57b9aU, 0xd33708a5U,
++    0x302887f2U, 0x23bfa5b2U, 0x02036abaU, 0xed16825cU,
++    0x8acf1c2bU, 0xa779b492U, 0xf307f2f0U, 0x4e69e2a1U,
++    0x65daf4cdU, 0x0605bed5U, 0xd134621fU, 0xc4a6fe8aU,
++    0x342e539dU, 0xa2f355a0U, 0x058ae132U, 0xa4f6eb75U,
++    0x0b83ec39U, 0x4060efaaU, 0x5e719f06U, 0xbd6e1051U,
++    0x3e218af9U, 0x96dd063dU, 0xdd3e05aeU, 0x4de6bd46U,
++    0x91548db5U, 0x71c45d05U, 0x0406d46fU, 0x605015ffU,
++    0x1998fb24U, 0xd6bde997U, 0x894043ccU, 0x67d99e77U,
++    0xb0e842bdU, 0x07898b88U, 0xe7195b38U, 0x79c8eedbU,
++    0xa17c0a47U, 0x7c420fe9U, 0xf8841ec9U, 0x00000000U,
++    0x09808683U, 0x322bed48U, 0x1e1170acU, 0x6c5a724eU,
++    0xfd0efffbU, 0x0f853856U, 0x3daed51eU, 0x362d3927U,
++    0x0a0fd964U, 0x685ca621U, 0x9b5b54d1U, 0x24362e3aU,
++    0x0c0a67b1U, 0x9357e70fU, 0xb4ee96d2U, 0x1b9b919eU,
++    0x80c0c54fU, 0x61dc20a2U, 0x5a774b69U, 0x1c121a16U,
++    0xe293ba0aU, 0xc0a02ae5U, 0x3c22e043U, 0x121b171dU,
++    0x0e090d0bU, 0xf28bc7adU, 0x2db6a8b9U, 0x141ea9c8U,
++    0x57f11985U, 0xaf75074cU, 0xee99ddbbU, 0xa37f60fdU,
++    0xf701269fU, 0x5c72f5bcU, 0x44663bc5U, 0x5bfb7e34U,
++    0x8b432976U, 0xcb23c6dcU, 0xb6edfc68U, 0xb8e4f163U,
++    0xd731dccaU, 0x42638510U, 0x13972240U, 0x84c61120U,
++    0x854a247dU, 0xd2bb3df8U, 0xaef93211U, 0xc729a16dU,
++    0x1d9e2f4bU, 0xdcb230f3U, 0x0d8652ecU, 0x77c1e3d0U,
++    0x2bb3166cU, 0xa970b999U, 0x119448faU, 0x47e96422U,
++    0xa8fc8cc4U, 0xa0f03f1aU, 0x567d2cd8U, 0x223390efU,
++    0x87494ec7U, 0xd938d1c1U, 0x8ccaa2feU, 0x98d40b36U,
++    0xa6f581cfU, 0xa57ade28U, 0xdab78e26U, 0x3fadbfa4U,
++    0x2c3a9de4U, 0x5078920dU, 0x6a5fcc9bU, 0x547e4662U,
++    0xf68d13c2U, 0x90d8b8e8U, 0x2e39f75eU, 0x82c3aff5U,
++    0x9f5d80beU, 0x69d0937cU, 0x6fd52da9U, 0xcf2512b3U,
++    0xc8ac993bU, 0x10187da7U, 0xe89c636eU, 0xdb3bbb7bU,
++    0xcd267809U, 0x6e5918f4U, 0xec9ab701U, 0x834f9aa8U,
++    0xe6956e65U, 0xaaffe67eU, 0x21bccf08U, 0xef15e8e6U,
++    0xbae79bd9U, 0x4a6f36ceU, 0xea9f09d4U, 0x29b07cd6U,
++    0x31a4b2afU, 0x2a3f2331U, 0xc6a59430U, 0x35a266c0U,
++    0x744ebc37U, 0xfc82caa6U, 0xe090d0b0U, 0x33a7d815U,
++    0xf104984aU, 0x41ecdaf7U, 0x7fcd500eU, 0x1791f62fU,
++    0x764dd68dU, 0x43efb04dU, 0xccaa4d54U, 0xe49604dfU,
++    0x9ed1b5e3U, 0x4c6a881bU, 0xc12c1fb8U, 0x4665517fU,
++    0x9d5eea04U, 0x018c355dU, 0xfa877473U, 0xfb0b412eU,
++    0xb3671d5aU, 0x92dbd252U, 0xe9105633U, 0x6dd64713U,
++    0x9ad7618cU, 0x37a10c7aU, 0x59f8148eU, 0xeb133c89U,
++    0xcea927eeU, 0xb761c935U, 0xe11ce5edU, 0x7a47b13cU,
++    0x9cd2df59U, 0x55f2733fU, 0x1814ce79U, 0x73c737bfU,
++    0x53f7cdeaU, 0x5ffdaa5bU, 0xdf3d6f14U, 0x7844db86U,
++    0xcaaff381U, 0xb968c43eU, 0x3824342cU, 0xc2a3405fU,
++    0x161dc372U, 0xbce2250cU, 0x283c498bU, 0xff0d9541U,
++    0x39a80171U, 0x080cb3deU, 0xd8b4e49cU, 0x6456c190U,
++    0x7bcb8461U, 0xd532b670U, 0x486c5c74U, 0xd0b85742U,
++};
++#ifndef AES_SMALL_TABLES
++const u32 Td1[256] = {
++    0x5051f4a7U, 0x537e4165U, 0xc31a17a4U, 0x963a275eU,
++    0xcb3bab6bU, 0xf11f9d45U, 0xabacfa58U, 0x934be303U,
++    0x552030faU, 0xf6ad766dU, 0x9188cc76U, 0x25f5024cU,
++    0xfc4fe5d7U, 0xd7c52acbU, 0x80263544U, 0x8fb562a3U,
++    0x49deb15aU, 0x6725ba1bU, 0x9845ea0eU, 0xe15dfec0U,
++    0x02c32f75U, 0x12814cf0U, 0xa38d4697U, 0xc66bd3f9U,
++    0xe7038f5fU, 0x9515929cU, 0xebbf6d7aU, 0xda955259U,
++    0x2dd4be83U, 0xd3587421U, 0x2949e069U, 0x448ec9c8U,
++    0x6a75c289U, 0x78f48e79U, 0x6b99583eU, 0xdd27b971U,
++    0xb6bee14fU, 0x17f088adU, 0x66c920acU, 0xb47dce3aU,
++    0x1863df4aU, 0x82e51a31U, 0x60975133U, 0x4562537fU,
++    0xe0b16477U, 0x84bb6baeU, 0x1cfe81a0U, 0x94f9082bU,
++    0x58704868U, 0x198f45fdU, 0x8794de6cU, 0xb7527bf8U,
++    0x23ab73d3U, 0xe2724b02U, 0x57e31f8fU, 0x2a6655abU,
++    0x07b2eb28U, 0x032fb5c2U, 0x9a86c57bU, 0xa5d33708U,
++    0xf2302887U, 0xb223bfa5U, 0xba02036aU, 0x5ced1682U,
++    0x2b8acf1cU, 0x92a779b4U, 0xf0f307f2U, 0xa14e69e2U,
++    0xcd65daf4U, 0xd50605beU, 0x1fd13462U, 0x8ac4a6feU,
++    0x9d342e53U, 0xa0a2f355U, 0x32058ae1U, 0x75a4f6ebU,
++    0x390b83ecU, 0xaa4060efU, 0x065e719fU, 0x51bd6e10U,
++    0xf93e218aU, 0x3d96dd06U, 0xaedd3e05U, 0x464de6bdU,
++    0xb591548dU, 0x0571c45dU, 0x6f0406d4U, 0xff605015U,
++    0x241998fbU, 0x97d6bde9U, 0xcc894043U, 0x7767d99eU,
++    0xbdb0e842U, 0x8807898bU, 0x38e7195bU, 0xdb79c8eeU,
++    0x47a17c0aU, 0xe97c420fU, 0xc9f8841eU, 0x00000000U,
++    0x83098086U, 0x48322bedU, 0xac1e1170U, 0x4e6c5a72U,
++    0xfbfd0effU, 0x560f8538U, 0x1e3daed5U, 0x27362d39U,
++    0x640a0fd9U, 0x21685ca6U, 0xd19b5b54U, 0x3a24362eU,
++    0xb10c0a67U, 0x0f9357e7U, 0xd2b4ee96U, 0x9e1b9b91U,
++    0x4f80c0c5U, 0xa261dc20U, 0x695a774bU, 0x161c121aU,
++    0x0ae293baU, 0xe5c0a02aU, 0x433c22e0U, 0x1d121b17U,
++    0x0b0e090dU, 0xadf28bc7U, 0xb92db6a8U, 0xc8141ea9U,
++    0x8557f119U, 0x4caf7507U, 0xbbee99ddU, 0xfda37f60U,
++    0x9ff70126U, 0xbc5c72f5U, 0xc544663bU, 0x345bfb7eU,
++    0x768b4329U, 0xdccb23c6U, 0x68b6edfcU, 0x63b8e4f1U,
++    0xcad731dcU, 0x10426385U, 0x40139722U, 0x2084c611U,
++    0x7d854a24U, 0xf8d2bb3dU, 0x11aef932U, 0x6dc729a1U,
++    0x4b1d9e2fU, 0xf3dcb230U, 0xec0d8652U, 0xd077c1e3U,
++    0x6c2bb316U, 0x99a970b9U, 0xfa119448U, 0x2247e964U,
++    0xc4a8fc8cU, 0x1aa0f03fU, 0xd8567d2cU, 0xef223390U,
++    0xc787494eU, 0xc1d938d1U, 0xfe8ccaa2U, 0x3698d40bU,
++    0xcfa6f581U, 0x28a57adeU, 0x26dab78eU, 0xa43fadbfU,
++    0xe42c3a9dU, 0x0d507892U, 0x9b6a5fccU, 0x62547e46U,
++    0xc2f68d13U, 0xe890d8b8U, 0x5e2e39f7U, 0xf582c3afU,
++    0xbe9f5d80U, 0x7c69d093U, 0xa96fd52dU, 0xb3cf2512U,
++    0x3bc8ac99U, 0xa710187dU, 0x6ee89c63U, 0x7bdb3bbbU,
++    0x09cd2678U, 0xf46e5918U, 0x01ec9ab7U, 0xa8834f9aU,
++    0x65e6956eU, 0x7eaaffe6U, 0x0821bccfU, 0xe6ef15e8U,
++    0xd9bae79bU, 0xce4a6f36U, 0xd4ea9f09U, 0xd629b07cU,
++    0xaf31a4b2U, 0x312a3f23U, 0x30c6a594U, 0xc035a266U,
++    0x37744ebcU, 0xa6fc82caU, 0xb0e090d0U, 0x1533a7d8U,
++    0x4af10498U, 0xf741ecdaU, 0x0e7fcd50U, 0x2f1791f6U,
++    0x8d764dd6U, 0x4d43efb0U, 0x54ccaa4dU, 0xdfe49604U,
++    0xe39ed1b5U, 0x1b4c6a88U, 0xb8c12c1fU, 0x7f466551U,
++    0x049d5eeaU, 0x5d018c35U, 0x73fa8774U, 0x2efb0b41U,
++    0x5ab3671dU, 0x5292dbd2U, 0x33e91056U, 0x136dd647U,
++    0x8c9ad761U, 0x7a37a10cU, 0x8e59f814U, 0x89eb133cU,
++    0xeecea927U, 0x35b761c9U, 0xede11ce5U, 0x3c7a47b1U,
++    0x599cd2dfU, 0x3f55f273U, 0x791814ceU, 0xbf73c737U,
++    0xea53f7cdU, 0x5b5ffdaaU, 0x14df3d6fU, 0x867844dbU,
++    0x81caaff3U, 0x3eb968c4U, 0x2c382434U, 0x5fc2a340U,
++    0x72161dc3U, 0x0cbce225U, 0x8b283c49U, 0x41ff0d95U,
++    0x7139a801U, 0xde080cb3U, 0x9cd8b4e4U, 0x906456c1U,
++    0x617bcb84U, 0x70d532b6U, 0x74486c5cU, 0x42d0b857U,
++};
++const u32 Td2[256] = {
++    0xa75051f4U, 0x65537e41U, 0xa4c31a17U, 0x5e963a27U,
++    0x6bcb3babU, 0x45f11f9dU, 0x58abacfaU, 0x03934be3U,
++    0xfa552030U, 0x6df6ad76U, 0x769188ccU, 0x4c25f502U,
++    0xd7fc4fe5U, 0xcbd7c52aU, 0x44802635U, 0xa38fb562U,
++    0x5a49deb1U, 0x1b6725baU, 0x0e9845eaU, 0xc0e15dfeU,
++    0x7502c32fU, 0xf012814cU, 0x97a38d46U, 0xf9c66bd3U,
++    0x5fe7038fU, 0x9c951592U, 0x7aebbf6dU, 0x59da9552U,
++    0x832dd4beU, 0x21d35874U, 0x692949e0U, 0xc8448ec9U,
++    0x896a75c2U, 0x7978f48eU, 0x3e6b9958U, 0x71dd27b9U,
++    0x4fb6bee1U, 0xad17f088U, 0xac66c920U, 0x3ab47dceU,
++    0x4a1863dfU, 0x3182e51aU, 0x33609751U, 0x7f456253U,
++    0x77e0b164U, 0xae84bb6bU, 0xa01cfe81U, 0x2b94f908U,
++    0x68587048U, 0xfd198f45U, 0x6c8794deU, 0xf8b7527bU,
++    0xd323ab73U, 0x02e2724bU, 0x8f57e31fU, 0xab2a6655U,
++    0x2807b2ebU, 0xc2032fb5U, 0x7b9a86c5U, 0x08a5d337U,
++    0x87f23028U, 0xa5b223bfU, 0x6aba0203U, 0x825ced16U,
++    0x1c2b8acfU, 0xb492a779U, 0xf2f0f307U, 0xe2a14e69U,
++    0xf4cd65daU, 0xbed50605U, 0x621fd134U, 0xfe8ac4a6U,
++    0x539d342eU, 0x55a0a2f3U, 0xe132058aU, 0xeb75a4f6U,
++    0xec390b83U, 0xefaa4060U, 0x9f065e71U, 0x1051bd6eU,
++
++    0x8af93e21U, 0x063d96ddU, 0x05aedd3eU, 0xbd464de6U,
++    0x8db59154U, 0x5d0571c4U, 0xd46f0406U, 0x15ff6050U,
++    0xfb241998U, 0xe997d6bdU, 0x43cc8940U, 0x9e7767d9U,
++    0x42bdb0e8U, 0x8b880789U, 0x5b38e719U, 0xeedb79c8U,
++    0x0a47a17cU, 0x0fe97c42U, 0x1ec9f884U, 0x00000000U,
++    0x86830980U, 0xed48322bU, 0x70ac1e11U, 0x724e6c5aU,
++    0xfffbfd0eU, 0x38560f85U, 0xd51e3daeU, 0x3927362dU,
++    0xd9640a0fU, 0xa621685cU, 0x54d19b5bU, 0x2e3a2436U,
++    0x67b10c0aU, 0xe70f9357U, 0x96d2b4eeU, 0x919e1b9bU,
++    0xc54f80c0U, 0x20a261dcU, 0x4b695a77U, 0x1a161c12U,
++    0xba0ae293U, 0x2ae5c0a0U, 0xe0433c22U, 0x171d121bU,
++    0x0d0b0e09U, 0xc7adf28bU, 0xa8b92db6U, 0xa9c8141eU,
++    0x198557f1U, 0x074caf75U, 0xddbbee99U, 0x60fda37fU,
++    0x269ff701U, 0xf5bc5c72U, 0x3bc54466U, 0x7e345bfbU,
++    0x29768b43U, 0xc6dccb23U, 0xfc68b6edU, 0xf163b8e4U,
++    0xdccad731U, 0x85104263U, 0x22401397U, 0x112084c6U,
++    0x247d854aU, 0x3df8d2bbU, 0x3211aef9U, 0xa16dc729U,
++    0x2f4b1d9eU, 0x30f3dcb2U, 0x52ec0d86U, 0xe3d077c1U,
++    0x166c2bb3U, 0xb999a970U, 0x48fa1194U, 0x642247e9U,
++    0x8cc4a8fcU, 0x3f1aa0f0U, 0x2cd8567dU, 0x90ef2233U,
++    0x4ec78749U, 0xd1c1d938U, 0xa2fe8ccaU, 0x0b3698d4U,
++    0x81cfa6f5U, 0xde28a57aU, 0x8e26dab7U, 0xbfa43fadU,
++    0x9de42c3aU, 0x920d5078U, 0xcc9b6a5fU, 0x4662547eU,
++    0x13c2f68dU, 0xb8e890d8U, 0xf75e2e39U, 0xaff582c3U,
++    0x80be9f5dU, 0x937c69d0U, 0x2da96fd5U, 0x12b3cf25U,
++    0x993bc8acU, 0x7da71018U, 0x636ee89cU, 0xbb7bdb3bU,
++    0x7809cd26U, 0x18f46e59U, 0xb701ec9aU, 0x9aa8834fU,
++    0x6e65e695U, 0xe67eaaffU, 0xcf0821bcU, 0xe8e6ef15U,
++    0x9bd9bae7U, 0x36ce4a6fU, 0x09d4ea9fU, 0x7cd629b0U,
++    0xb2af31a4U, 0x23312a3fU, 0x9430c6a5U, 0x66c035a2U,
++    0xbc37744eU, 0xcaa6fc82U, 0xd0b0e090U, 0xd81533a7U,
++    0x984af104U, 0xdaf741ecU, 0x500e7fcdU, 0xf62f1791U,
++    0xd68d764dU, 0xb04d43efU, 0x4d54ccaaU, 0x04dfe496U,
++    0xb5e39ed1U, 0x881b4c6aU, 0x1fb8c12cU, 0x517f4665U,
++    0xea049d5eU, 0x355d018cU, 0x7473fa87U, 0x412efb0bU,
++    0x1d5ab367U, 0xd25292dbU, 0x5633e910U, 0x47136dd6U,
++    0x618c9ad7U, 0x0c7a37a1U, 0x148e59f8U, 0x3c89eb13U,
++    0x27eecea9U, 0xc935b761U, 0xe5ede11cU, 0xb13c7a47U,
++    0xdf599cd2U, 0x733f55f2U, 0xce791814U, 0x37bf73c7U,
++    0xcdea53f7U, 0xaa5b5ffdU, 0x6f14df3dU, 0xdb867844U,
++    0xf381caafU, 0xc43eb968U, 0x342c3824U, 0x405fc2a3U,
++    0xc372161dU, 0x250cbce2U, 0x498b283cU, 0x9541ff0dU,
++    0x017139a8U, 0xb3de080cU, 0xe49cd8b4U, 0xc1906456U,
++    0x84617bcbU, 0xb670d532U, 0x5c74486cU, 0x5742d0b8U,
++};
++const u32 Td3[256] = {
++    0xf4a75051U, 0x4165537eU, 0x17a4c31aU, 0x275e963aU,
++    0xab6bcb3bU, 0x9d45f11fU, 0xfa58abacU, 0xe303934bU,
++    0x30fa5520U, 0x766df6adU, 0xcc769188U, 0x024c25f5U,
++    0xe5d7fc4fU, 0x2acbd7c5U, 0x35448026U, 0x62a38fb5U,
++    0xb15a49deU, 0xba1b6725U, 0xea0e9845U, 0xfec0e15dU,
++    0x2f7502c3U, 0x4cf01281U, 0x4697a38dU, 0xd3f9c66bU,
++    0x8f5fe703U, 0x929c9515U, 0x6d7aebbfU, 0x5259da95U,
++    0xbe832dd4U, 0x7421d358U, 0xe0692949U, 0xc9c8448eU,
++    0xc2896a75U, 0x8e7978f4U, 0x583e6b99U, 0xb971dd27U,
++    0xe14fb6beU, 0x88ad17f0U, 0x20ac66c9U, 0xce3ab47dU,
++    0xdf4a1863U, 0x1a3182e5U, 0x51336097U, 0x537f4562U,
++    0x6477e0b1U, 0x6bae84bbU, 0x81a01cfeU, 0x082b94f9U,
++    0x48685870U, 0x45fd198fU, 0xde6c8794U, 0x7bf8b752U,
++    0x73d323abU, 0x4b02e272U, 0x1f8f57e3U, 0x55ab2a66U,
++    0xeb2807b2U, 0xb5c2032fU, 0xc57b9a86U, 0x3708a5d3U,
++    0x2887f230U, 0xbfa5b223U, 0x036aba02U, 0x16825cedU,
++    0xcf1c2b8aU, 0x79b492a7U, 0x07f2f0f3U, 0x69e2a14eU,
++    0xdaf4cd65U, 0x05bed506U, 0x34621fd1U, 0xa6fe8ac4U,
++    0x2e539d34U, 0xf355a0a2U, 0x8ae13205U, 0xf6eb75a4U,
++    0x83ec390bU, 0x60efaa40U, 0x719f065eU, 0x6e1051bdU,
++    0x218af93eU, 0xdd063d96U, 0x3e05aeddU, 0xe6bd464dU,
++    0x548db591U, 0xc45d0571U, 0x06d46f04U, 0x5015ff60U,
++    0x98fb2419U, 0xbde997d6U, 0x4043cc89U, 0xd99e7767U,
++    0xe842bdb0U, 0x898b8807U, 0x195b38e7U, 0xc8eedb79U,
++    0x7c0a47a1U, 0x420fe97cU, 0x841ec9f8U, 0x00000000U,
++    0x80868309U, 0x2bed4832U, 0x1170ac1eU, 0x5a724e6cU,
++    0x0efffbfdU, 0x8538560fU, 0xaed51e3dU, 0x2d392736U,
++    0x0fd9640aU, 0x5ca62168U, 0x5b54d19bU, 0x362e3a24U,
++    0x0a67b10cU, 0x57e70f93U, 0xee96d2b4U, 0x9b919e1bU,
++    0xc0c54f80U, 0xdc20a261U, 0x774b695aU, 0x121a161cU,
++    0x93ba0ae2U, 0xa02ae5c0U, 0x22e0433cU, 0x1b171d12U,
++    0x090d0b0eU, 0x8bc7adf2U, 0xb6a8b92dU, 0x1ea9c814U,
++    0xf1198557U, 0x75074cafU, 0x99ddbbeeU, 0x7f60fda3U,
++    0x01269ff7U, 0x72f5bc5cU, 0x663bc544U, 0xfb7e345bU,
++    0x4329768bU, 0x23c6dccbU, 0xedfc68b6U, 0xe4f163b8U,
++    0x31dccad7U, 0x63851042U, 0x97224013U, 0xc6112084U,
++    0x4a247d85U, 0xbb3df8d2U, 0xf93211aeU, 0x29a16dc7U,
++    0x9e2f4b1dU, 0xb230f3dcU, 0x8652ec0dU, 0xc1e3d077U,
++    0xb3166c2bU, 0x70b999a9U, 0x9448fa11U, 0xe9642247U,
++    0xfc8cc4a8U, 0xf03f1aa0U, 0x7d2cd856U, 0x3390ef22U,
++    0x494ec787U, 0x38d1c1d9U, 0xcaa2fe8cU, 0xd40b3698U,
++    0xf581cfa6U, 0x7ade28a5U, 0xb78e26daU, 0xadbfa43fU,
++    0x3a9de42cU, 0x78920d50U, 0x5fcc9b6aU, 0x7e466254U,
++    0x8d13c2f6U, 0xd8b8e890U, 0x39f75e2eU, 0xc3aff582U,
++    0x5d80be9fU, 0xd0937c69U, 0xd52da96fU, 0x2512b3cfU,
++    0xac993bc8U, 0x187da710U, 0x9c636ee8U, 0x3bbb7bdbU,
++    0x267809cdU, 0x5918f46eU, 0x9ab701ecU, 0x4f9aa883U,
++    0x956e65e6U, 0xffe67eaaU, 0xbccf0821U, 0x15e8e6efU,
++    0xe79bd9baU, 0x6f36ce4aU, 0x9f09d4eaU, 0xb07cd629U,
++    0xa4b2af31U, 0x3f23312aU, 0xa59430c6U, 0xa266c035U,
++    0x4ebc3774U, 0x82caa6fcU, 0x90d0b0e0U, 0xa7d81533U,
++    0x04984af1U, 0xecdaf741U, 0xcd500e7fU, 0x91f62f17U,
++    0x4dd68d76U, 0xefb04d43U, 0xaa4d54ccU, 0x9604dfe4U,
++    0xd1b5e39eU, 0x6a881b4cU, 0x2c1fb8c1U, 0x65517f46U,
++    0x5eea049dU, 0x8c355d01U, 0x877473faU, 0x0b412efbU,
++    0x671d5ab3U, 0xdbd25292U, 0x105633e9U, 0xd647136dU,
++    0xd7618c9aU, 0xa10c7a37U, 0xf8148e59U, 0x133c89ebU,
++    0xa927eeceU, 0x61c935b7U, 0x1ce5ede1U, 0x47b13c7aU,
++    0xd2df599cU, 0xf2733f55U, 0x14ce7918U, 0xc737bf73U,
++    0xf7cdea53U, 0xfdaa5b5fU, 0x3d6f14dfU, 0x44db8678U,
++    0xaff381caU, 0x68c43eb9U, 0x24342c38U, 0xa3405fc2U,
++    0x1dc37216U, 0xe2250cbcU, 0x3c498b28U, 0x0d9541ffU,
++    0xa8017139U, 0x0cb3de08U, 0xb4e49cd8U, 0x56c19064U,
++    0xcb84617bU, 0x32b670d5U, 0x6c5c7448U, 0xb85742d0U,
++};
++const u32 Td4[256] = {
++    0x52525252U, 0x09090909U, 0x6a6a6a6aU, 0xd5d5d5d5U,
++    0x30303030U, 0x36363636U, 0xa5a5a5a5U, 0x38383838U,
++    0xbfbfbfbfU, 0x40404040U, 0xa3a3a3a3U, 0x9e9e9e9eU,
++    0x81818181U, 0xf3f3f3f3U, 0xd7d7d7d7U, 0xfbfbfbfbU,
++    0x7c7c7c7cU, 0xe3e3e3e3U, 0x39393939U, 0x82828282U,
++    0x9b9b9b9bU, 0x2f2f2f2fU, 0xffffffffU, 0x87878787U,
++    0x34343434U, 0x8e8e8e8eU, 0x43434343U, 0x44444444U,
++    0xc4c4c4c4U, 0xdedededeU, 0xe9e9e9e9U, 0xcbcbcbcbU,
++    0x54545454U, 0x7b7b7b7bU, 0x94949494U, 0x32323232U,
++    0xa6a6a6a6U, 0xc2c2c2c2U, 0x23232323U, 0x3d3d3d3dU,
++    0xeeeeeeeeU, 0x4c4c4c4cU, 0x95959595U, 0x0b0b0b0bU,
++    0x42424242U, 0xfafafafaU, 0xc3c3c3c3U, 0x4e4e4e4eU,
++    0x08080808U, 0x2e2e2e2eU, 0xa1a1a1a1U, 0x66666666U,
++    0x28282828U, 0xd9d9d9d9U, 0x24242424U, 0xb2b2b2b2U,
++    0x76767676U, 0x5b5b5b5bU, 0xa2a2a2a2U, 0x49494949U,
++    0x6d6d6d6dU, 0x8b8b8b8bU, 0xd1d1d1d1U, 0x25252525U,
++    0x72727272U, 0xf8f8f8f8U, 0xf6f6f6f6U, 0x64646464U,
++    0x86868686U, 0x68686868U, 0x98989898U, 0x16161616U,
++    0xd4d4d4d4U, 0xa4a4a4a4U, 0x5c5c5c5cU, 0xccccccccU,
++    0x5d5d5d5dU, 0x65656565U, 0xb6b6b6b6U, 0x92929292U,
++    0x6c6c6c6cU, 0x70707070U, 0x48484848U, 0x50505050U,
++    0xfdfdfdfdU, 0xededededU, 0xb9b9b9b9U, 0xdadadadaU,
++    0x5e5e5e5eU, 0x15151515U, 0x46464646U, 0x57575757U,
++    0xa7a7a7a7U, 0x8d8d8d8dU, 0x9d9d9d9dU, 0x84848484U,
++    0x90909090U, 0xd8d8d8d8U, 0xababababU, 0x00000000U,
++    0x8c8c8c8cU, 0xbcbcbcbcU, 0xd3d3d3d3U, 0x0a0a0a0aU,
++    0xf7f7f7f7U, 0xe4e4e4e4U, 0x58585858U, 0x05050505U,
++    0xb8b8b8b8U, 0xb3b3b3b3U, 0x45454545U, 0x06060606U,
++    0xd0d0d0d0U, 0x2c2c2c2cU, 0x1e1e1e1eU, 0x8f8f8f8fU,
++    0xcacacacaU, 0x3f3f3f3fU, 0x0f0f0f0fU, 0x02020202U,
++    0xc1c1c1c1U, 0xafafafafU, 0xbdbdbdbdU, 0x03030303U,
++    0x01010101U, 0x13131313U, 0x8a8a8a8aU, 0x6b6b6b6bU,
++    0x3a3a3a3aU, 0x91919191U, 0x11111111U, 0x41414141U,
++    0x4f4f4f4fU, 0x67676767U, 0xdcdcdcdcU, 0xeaeaeaeaU,
++    0x97979797U, 0xf2f2f2f2U, 0xcfcfcfcfU, 0xcecececeU,
++    0xf0f0f0f0U, 0xb4b4b4b4U, 0xe6e6e6e6U, 0x73737373U,
++    0x96969696U, 0xacacacacU, 0x74747474U, 0x22222222U,
++    0xe7e7e7e7U, 0xadadadadU, 0x35353535U, 0x85858585U,
++    0xe2e2e2e2U, 0xf9f9f9f9U, 0x37373737U, 0xe8e8e8e8U,
++    0x1c1c1c1cU, 0x75757575U, 0xdfdfdfdfU, 0x6e6e6e6eU,
++    0x47474747U, 0xf1f1f1f1U, 0x1a1a1a1aU, 0x71717171U,
++    0x1d1d1d1dU, 0x29292929U, 0xc5c5c5c5U, 0x89898989U,
++    0x6f6f6f6fU, 0xb7b7b7b7U, 0x62626262U, 0x0e0e0e0eU,
++    0xaaaaaaaaU, 0x18181818U, 0xbebebebeU, 0x1b1b1b1bU,
++    0xfcfcfcfcU, 0x56565656U, 0x3e3e3e3eU, 0x4b4b4b4bU,
++    0xc6c6c6c6U, 0xd2d2d2d2U, 0x79797979U, 0x20202020U,
++    0x9a9a9a9aU, 0xdbdbdbdbU, 0xc0c0c0c0U, 0xfefefefeU,
++    0x78787878U, 0xcdcdcdcdU, 0x5a5a5a5aU, 0xf4f4f4f4U,
++    0x1f1f1f1fU, 0xddddddddU, 0xa8a8a8a8U, 0x33333333U,
++    0x88888888U, 0x07070707U, 0xc7c7c7c7U, 0x31313131U,
++    0xb1b1b1b1U, 0x12121212U, 0x10101010U, 0x59595959U,
++    0x27272727U, 0x80808080U, 0xececececU, 0x5f5f5f5fU,
++    0x60606060U, 0x51515151U, 0x7f7f7f7fU, 0xa9a9a9a9U,
++    0x19191919U, 0xb5b5b5b5U, 0x4a4a4a4aU, 0x0d0d0d0dU,
++    0x2d2d2d2dU, 0xe5e5e5e5U, 0x7a7a7a7aU, 0x9f9f9f9fU,
++    0x93939393U, 0xc9c9c9c9U, 0x9c9c9c9cU, 0xefefefefU,
++    0xa0a0a0a0U, 0xe0e0e0e0U, 0x3b3b3b3bU, 0x4d4d4d4dU,
++    0xaeaeaeaeU, 0x2a2a2a2aU, 0xf5f5f5f5U, 0xb0b0b0b0U,
++    0xc8c8c8c8U, 0xebebebebU, 0xbbbbbbbbU, 0x3c3c3c3cU,
++    0x83838383U, 0x53535353U, 0x99999999U, 0x61616161U,
++    0x17171717U, 0x2b2b2b2bU, 0x04040404U, 0x7e7e7e7eU,
++    0xbabababaU, 0x77777777U, 0xd6d6d6d6U, 0x26262626U,
++    0xe1e1e1e1U, 0x69696969U, 0x14141414U, 0x63636363U,
++    0x55555555U, 0x21212121U, 0x0c0c0c0cU, 0x7d7d7d7dU,
++};
++const u32 rcon[] = {
++	0x01000000, 0x02000000, 0x04000000, 0x08000000,
++	0x10000000, 0x20000000, 0x40000000, 0x80000000,
++	0x1B000000, 0x36000000, /* for 128-bit blocks, Rijndael never uses more than 10 rcon values */
++};
++#else /* AES_SMALL_TABLES */
++const u8 Td4s[256] = {
++    0x52U, 0x09U, 0x6aU, 0xd5U, 0x30U, 0x36U, 0xa5U, 0x38U,
++    0xbfU, 0x40U, 0xa3U, 0x9eU, 0x81U, 0xf3U, 0xd7U, 0xfbU,
++    0x7cU, 0xe3U, 0x39U, 0x82U, 0x9bU, 0x2fU, 0xffU, 0x87U,
++    0x34U, 0x8eU, 0x43U, 0x44U, 0xc4U, 0xdeU, 0xe9U, 0xcbU,
++    0x54U, 0x7bU, 0x94U, 0x32U, 0xa6U, 0xc2U, 0x23U, 0x3dU,
++    0xeeU, 0x4cU, 0x95U, 0x0bU, 0x42U, 0xfaU, 0xc3U, 0x4eU,
++    0x08U, 0x2eU, 0xa1U, 0x66U, 0x28U, 0xd9U, 0x24U, 0xb2U,
++    0x76U, 0x5bU, 0xa2U, 0x49U, 0x6dU, 0x8bU, 0xd1U, 0x25U,
++    0x72U, 0xf8U, 0xf6U, 0x64U, 0x86U, 0x68U, 0x98U, 0x16U,
++    0xd4U, 0xa4U, 0x5cU, 0xccU, 0x5dU, 0x65U, 0xb6U, 0x92U,
++    0x6cU, 0x70U, 0x48U, 0x50U, 0xfdU, 0xedU, 0xb9U, 0xdaU,
++    0x5eU, 0x15U, 0x46U, 0x57U, 0xa7U, 0x8dU, 0x9dU, 0x84U,
++    0x90U, 0xd8U, 0xabU, 0x00U, 0x8cU, 0xbcU, 0xd3U, 0x0aU,
++    0xf7U, 0xe4U, 0x58U, 0x05U, 0xb8U, 0xb3U, 0x45U, 0x06U,
++    0xd0U, 0x2cU, 0x1eU, 0x8fU, 0xcaU, 0x3fU, 0x0fU, 0x02U,
++    0xc1U, 0xafU, 0xbdU, 0x03U, 0x01U, 0x13U, 0x8aU, 0x6bU,
++    0x3aU, 0x91U, 0x11U, 0x41U, 0x4fU, 0x67U, 0xdcU, 0xeaU,
++    0x97U, 0xf2U, 0xcfU, 0xceU, 0xf0U, 0xb4U, 0xe6U, 0x73U,
++    0x96U, 0xacU, 0x74U, 0x22U, 0xe7U, 0xadU, 0x35U, 0x85U,
++    0xe2U, 0xf9U, 0x37U, 0xe8U, 0x1cU, 0x75U, 0xdfU, 0x6eU,
++    0x47U, 0xf1U, 0x1aU, 0x71U, 0x1dU, 0x29U, 0xc5U, 0x89U,
++    0x6fU, 0xb7U, 0x62U, 0x0eU, 0xaaU, 0x18U, 0xbeU, 0x1bU,
++    0xfcU, 0x56U, 0x3eU, 0x4bU, 0xc6U, 0xd2U, 0x79U, 0x20U,
++    0x9aU, 0xdbU, 0xc0U, 0xfeU, 0x78U, 0xcdU, 0x5aU, 0xf4U,
++    0x1fU, 0xddU, 0xa8U, 0x33U, 0x88U, 0x07U, 0xc7U, 0x31U,
++    0xb1U, 0x12U, 0x10U, 0x59U, 0x27U, 0x80U, 0xecU, 0x5fU,
++    0x60U, 0x51U, 0x7fU, 0xa9U, 0x19U, 0xb5U, 0x4aU, 0x0dU,
++    0x2dU, 0xe5U, 0x7aU, 0x9fU, 0x93U, 0xc9U, 0x9cU, 0xefU,
++    0xa0U, 0xe0U, 0x3bU, 0x4dU, 0xaeU, 0x2aU, 0xf5U, 0xb0U,
++    0xc8U, 0xebU, 0xbbU, 0x3cU, 0x83U, 0x53U, 0x99U, 0x61U,
++    0x17U, 0x2bU, 0x04U, 0x7eU, 0xbaU, 0x77U, 0xd6U, 0x26U,
++    0xe1U, 0x69U, 0x14U, 0x63U, 0x55U, 0x21U, 0x0cU, 0x7dU,
++};
++const u8 rcons[] = {
++	0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1B, 0x36
++	/* for 128-bit blocks, Rijndael never uses more than 10 rcon values */
++};
++#endif /* AES_SMALL_TABLES */
++/**
++ * Expand the cipher key into the encryption key schedule.
++ *
++ * @return	the number of rounds for the given cipher key size.
++ */
++int rijndaelKeySetupEnc(u32 rk[], const u8 cipherKey[], int keyBits)
++{
++	int i;
++	u32 temp;
++
++	rk[0] = GETU32(cipherKey     );
++	rk[1] = GETU32(cipherKey +  4);
++	rk[2] = GETU32(cipherKey +  8);
++	rk[3] = GETU32(cipherKey + 12);
++
++	if (keyBits == 128) {
++		for (i = 0; i < 10; i++) {
++			temp  = rk[3];
++			rk[4] = rk[0] ^ TE421(temp) ^ TE432(temp) ^
++				TE443(temp) ^ TE414(temp) ^ RCON(i);
++			rk[5] = rk[1] ^ rk[4];
++			rk[6] = rk[2] ^ rk[5];
++			rk[7] = rk[3] ^ rk[6];
++			rk += 4;
++		}
++		return 10;
++	}
++
++	rk[4] = GETU32(cipherKey + 16);
++	rk[5] = GETU32(cipherKey + 20);
++
++	if (keyBits == 192) {
++		for (i = 0; i < 8; i++) {
++			temp  = rk[5];
++			rk[6] = rk[0] ^ TE421(temp) ^ TE432(temp) ^
++				TE443(temp) ^ TE414(temp) ^ RCON(i);
++			rk[7] = rk[1] ^ rk[6];
++			rk[8] = rk[2] ^ rk[7];
++			rk[9] = rk[3] ^ rk[8];
++			if (i == 7)
++				return 12;
++			rk[10] = rk[4] ^ rk[9];
++			rk[11] = rk[5] ^ rk[10];
++			rk += 6;
++		}
++	}
++
++	rk[6] = GETU32(cipherKey + 24);
++	rk[7] = GETU32(cipherKey + 28);
++
++	if (keyBits == 256) {
++		for (i = 0; i < 7; i++) {
++			temp  = rk[7];
++			rk[8] = rk[0] ^ TE421(temp) ^ TE432(temp) ^
++				TE443(temp) ^ TE414(temp) ^ RCON(i);
++			rk[9] = rk[1] ^ rk[8];
++			rk[10] = rk[2] ^ rk[9];
++			rk[11] = rk[3] ^ rk[10];
++			if (i == 6)
++				return 14;
++			temp  = rk[11];
++			rk[12] = rk[4] ^ TE411(temp) ^ TE422(temp) ^
++				TE433(temp) ^ TE444(temp);
++			rk[13] = rk[5] ^ rk[12];
++			rk[14] = rk[6] ^ rk[13];
++			rk[15] = rk[7] ^ rk[14];
++			rk += 8;
++		}
++	}
++
++	return -1;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-omac1.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-omac1.c
+new file mode 100644
+index 000000000..30b52629f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-omac1.c
+@@ -0,0 +1,172 @@
++/*
++ * One-key CBC MAC (OMAC1) hash with AES
++ *
++ * Copyright (c) 2003-2007, Jouni Malinen <j@w1.fi>
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#include "rtw_crypto_wrap.h"
++
++#include "aes.h"
++#include "aes_wrap.h"
++
++static void gf_mulx(u8 *pad)
++{
++	int i, carry;
++
++	carry = pad[0] & 0x80;
++	for (i = 0; i < AES_BLOCK_SIZE - 1; i++)
++		pad[i] = (pad[i] << 1) | (pad[i + 1] >> 7);
++	pad[AES_BLOCK_SIZE - 1] <<= 1;
++	if (carry)
++		pad[AES_BLOCK_SIZE - 1] ^= 0x87;
++}
++
++
++/**
++ * omac1_aes_vector - One-Key CBC MAC (OMAC1) hash with AES
++ * @key: Key for the hash operation
++ * @key_len: Key length in octets
++ * @num_elem: Number of elements in the data vector
++ * @addr: Pointers to the data areas
++ * @len: Lengths of the data blocks
++ * @mac: Buffer for MAC (128 bits, i.e., 16 bytes)
++ * Returns: 0 on success, -1 on failure
++ *
++ * This is a mode for using block cipher (AES in this case) for authentication.
++ * OMAC1 was standardized with the name CMAC by NIST in a Special Publication
++ * (SP) 800-38B.
++ */
++int omac1_aes_vector(const u8 *key, size_t key_len, size_t num_elem,
++		     const u8 *addr[], const size_t *len, u8 *mac)
++{
++	void *ctx;
++	u8 cbc[AES_BLOCK_SIZE], pad[AES_BLOCK_SIZE];
++	const u8 *pos, *end;
++	size_t i, e, left, total_len;
++
++	if (TEST_FAIL())
++		return -1;
++
++	ctx = aes_encrypt_init(key, key_len);
++	if (ctx == NULL)
++		return -1;
++	os_memset(cbc, 0, AES_BLOCK_SIZE);
++
++	total_len = 0;
++	for (e = 0; e < num_elem; e++)
++		total_len += len[e];
++	left = total_len;
++
++	e = 0;
++	pos = addr[0];
++	end = pos + len[0];
++
++	while (left >= AES_BLOCK_SIZE) {
++		for (i = 0; i < AES_BLOCK_SIZE; i++) {
++			cbc[i] ^= *pos++;
++			if (pos >= end) {
++				/*
++				 * Stop if there are no more bytes to process
++				 * since there are no more entries in the array.
++				 */
++				if (i + 1 == AES_BLOCK_SIZE &&
++				    left == AES_BLOCK_SIZE)
++					break;
++				e++;
++				pos = addr[e];
++				end = pos + len[e];
++			}
++		}
++		if (left > AES_BLOCK_SIZE)
++			aes_encrypt(ctx, cbc, cbc);
++		left -= AES_BLOCK_SIZE;
++	}
++
++	os_memset(pad, 0, AES_BLOCK_SIZE);
++	aes_encrypt(ctx, pad, pad);
++	gf_mulx(pad);
++
++	if (left || total_len == 0) {
++		for (i = 0; i < left; i++) {
++			cbc[i] ^= *pos++;
++			if (pos >= end) {
++				/*
++				 * Stop if there are no more bytes to process
++				 * since there are no more entries in the array.
++				 */
++				if (i + 1 == left)
++					break;
++				e++;
++				pos = addr[e];
++				end = pos + len[e];
++			}
++		}
++		cbc[left] ^= 0x80;
++		gf_mulx(pad);
++	}
++
++	for (i = 0; i < AES_BLOCK_SIZE; i++)
++		pad[i] ^= cbc[i];
++	aes_encrypt(ctx, pad, mac);
++	aes_encrypt_deinit(ctx);
++	return 0;
++}
++
++
++/**
++ * omac1_aes_128_vector - One-Key CBC MAC (OMAC1) hash with AES-128
++ * @key: 128-bit key for the hash operation
++ * @num_elem: Number of elements in the data vector
++ * @addr: Pointers to the data areas
++ * @len: Lengths of the data blocks
++ * @mac: Buffer for MAC (128 bits, i.e., 16 bytes)
++ * Returns: 0 on success, -1 on failure
++ *
++ * This is a mode for using block cipher (AES in this case) for authentication.
++ * OMAC1 was standardized with the name CMAC by NIST in a Special Publication
++ * (SP) 800-38B.
++ */
++int omac1_aes_128_vector(const u8 *key, size_t num_elem,
++			 const u8 *addr[], const size_t *len, u8 *mac)
++{
++	return omac1_aes_vector(key, 16, num_elem, addr, len, mac);
++}
++
++
++/**
++ * omac1_aes_128 - One-Key CBC MAC (OMAC1) hash with AES-128 (aka AES-CMAC)
++ * @key: 128-bit key for the hash operation
++ * @data: Data buffer for which a MAC is determined
++ * @data_len: Length of data buffer in bytes
++ * @mac: Buffer for MAC (128 bits, i.e., 16 bytes)
++ * Returns: 0 on success, -1 on failure
++ *
++ * This is a mode for using block cipher (AES in this case) for authentication.
++ * OMAC1 was standardized with the name CMAC by NIST in a Special Publication
++ * (SP) 800-38B.
++ */
++int omac1_aes_128(const u8 *key, const u8 *data, size_t data_len, u8 *mac)
++{
++	return omac1_aes_128_vector(key, 1, &data, &data_len, mac);
++}
++
++
++/**
++ * omac1_aes_256 - One-Key CBC MAC (OMAC1) hash with AES-256 (aka AES-CMAC)
++ * @key: 256-bit key for the hash operation
++ * @data: Data buffer for which a MAC is determined
++ * @data_len: Length of data buffer in bytes
++ * @mac: Buffer for MAC (128 bits, i.e., 16 bytes)
++ * Returns: 0 on success, -1 on failure
++ *
++ * This is a mode for using block cipher (AES in this case) for authentication.
++ * OMAC1 was standardized with the name CMAC by NIST in a Special Publication
++ * (SP) 800-38B.
++ */
++int omac1_aes_256(const u8 *key, const u8 *data, size_t data_len, u8 *mac)
++{
++	return omac1_aes_vector(key, 32, 1, &data, &data_len, mac);
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-siv.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-siv.c
+new file mode 100644
+index 000000000..58656f2b5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes-siv.c
+@@ -0,0 +1,207 @@
++/*
++ * AES SIV (RFC 5297)
++ * Copyright (c) 2013 Cozybit, Inc.
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#include "rtw_crypto_wrap.h"
++
++#include "aes.h"
++#include "aes_wrap.h"
++#include "aes_siv.h"
++
++
++static const u8 zero[AES_BLOCK_SIZE];
++
++
++static void dbl(u8 *pad)
++{
++	int i, carry;
++
++	carry = pad[0] & 0x80;
++	for (i = 0; i < AES_BLOCK_SIZE - 1; i++)
++		pad[i] = (pad[i] << 1) | (pad[i + 1] >> 7);
++	pad[AES_BLOCK_SIZE - 1] <<= 1;
++	if (carry)
++		pad[AES_BLOCK_SIZE - 1] ^= 0x87;
++}
++
++
++static void xor(u8 *a, const u8 *b)
++{
++	int i;
++
++	for (i = 0; i < AES_BLOCK_SIZE; i++)
++		*a++ ^= *b++;
++}
++
++
++static void xorend(u8 *a, int alen, const u8 *b, int blen)
++{
++	int i;
++
++	if (alen < blen)
++		return;
++
++	for (i = 0; i < blen; i++)
++		a[alen - blen + i] ^= b[i];
++}
++
++
++static void pad_block(u8 *pad, const u8 *addr, size_t len)
++{
++	os_memset(pad, 0, AES_BLOCK_SIZE);
++	os_memcpy(pad, addr, len);
++
++	if (len < AES_BLOCK_SIZE)
++		pad[len] = 0x80;
++}
++
++
++static int aes_s2v(const u8 *key, size_t key_len,
++		   size_t num_elem, const u8 *addr[], size_t *len, u8 *mac)
++{
++	u8 tmp[AES_BLOCK_SIZE], tmp2[AES_BLOCK_SIZE];
++	u8 *buf = NULL;
++	int ret;
++	size_t i;
++	const u8 *data[1];
++	size_t data_len[1];
++
++	if (!num_elem) {
++		os_memcpy(tmp, zero, sizeof(zero));
++		tmp[AES_BLOCK_SIZE - 1] = 1;
++		data[0] = tmp;
++		data_len[0] = sizeof(tmp);
++		return omac1_aes_vector(key, key_len, 1, data, data_len, mac);
++	}
++
++	data[0] = zero;
++	data_len[0] = sizeof(zero);
++	ret = omac1_aes_vector(key, key_len, 1, data, data_len, tmp);
++	if (ret)
++		return ret;
++
++	for (i = 0; i < num_elem - 1; i++) {
++		ret = omac1_aes_vector(key, key_len, 1, &addr[i], &len[i],
++				       tmp2);
++		if (ret)
++			return ret;
++
++		dbl(tmp);
++		xor(tmp, tmp2);
++	}
++	if (len[i] >= AES_BLOCK_SIZE) {
++		buf = os_memdup(addr[i], len[i]);
++		if (!buf)
++			return -ENOMEM;
++
++		xorend(buf, len[i], tmp, AES_BLOCK_SIZE);
++		data[0] = buf;
++		ret = omac1_aes_vector(key, key_len, 1, data, &len[i], mac);
++		bin_clear_free(buf, len[i]);
++		return ret;
++	}
++
++	dbl(tmp);
++	pad_block(tmp2, addr[i], len[i]);
++	xor(tmp, tmp2);
++
++	data[0] = tmp;
++	data_len[0] = sizeof(tmp);
++	return omac1_aes_vector(key, key_len, 1, data, data_len, mac);
++}
++
++
++int aes_siv_encrypt(const u8 *key, size_t key_len,
++		    const u8 *pw, size_t pwlen,
++		    size_t num_elem, const u8 *addr[], const size_t *len,
++		    u8 *out)
++{
++	const u8 *_addr[6];
++	size_t _len[6];
++	const u8 *k1, *k2;
++	u8 v[AES_BLOCK_SIZE];
++	size_t i;
++	u8 *iv, *crypt_pw;
++
++	if (num_elem > ARRAY_SIZE(_addr) - 1 ||
++	    (key_len != 32 && key_len != 48 && key_len != 64))
++		return -1;
++
++	key_len /= 2;
++	k1 = key;
++	k2 = key + key_len;
++
++	for (i = 0; i < num_elem; i++) {
++		_addr[i] = addr[i];
++		_len[i] = len[i];
++	}
++	_addr[num_elem] = pw;
++	_len[num_elem] = pwlen;
++
++	if (aes_s2v(k1, key_len, num_elem + 1, _addr, _len, v))
++		return -1;
++
++	iv = out;
++	crypt_pw = out + AES_BLOCK_SIZE;
++
++	os_memcpy(iv, v, AES_BLOCK_SIZE);
++	os_memcpy(crypt_pw, pw, pwlen);
++
++	/* zero out 63rd and 31st bits of ctr (from right) */
++	v[8] &= 0x7f;
++	v[12] &= 0x7f;
++	return aes_ctr_encrypt(k2, key_len, v, crypt_pw, pwlen);
++}
++
++
++int aes_siv_decrypt(const u8 *key, size_t key_len,
++		    const u8 *iv_crypt, size_t iv_c_len,
++		    size_t num_elem, const u8 *addr[], const size_t *len,
++		    u8 *out)
++{
++	const u8 *_addr[6];
++	size_t _len[6];
++	const u8 *k1, *k2;
++	size_t crypt_len;
++	size_t i;
++	int ret;
++	u8 iv[AES_BLOCK_SIZE];
++	u8 check[AES_BLOCK_SIZE];
++
++	if (iv_c_len < AES_BLOCK_SIZE || num_elem > ARRAY_SIZE(_addr) - 1 ||
++	    (key_len != 32 && key_len != 48 && key_len != 64))
++		return -1;
++	crypt_len = iv_c_len - AES_BLOCK_SIZE;
++	key_len /= 2;
++	k1 = key;
++	k2 = key + key_len;
++
++	for (i = 0; i < num_elem; i++) {
++		_addr[i] = addr[i];
++		_len[i] = len[i];
++	}
++	_addr[num_elem] = out;
++	_len[num_elem] = crypt_len;
++
++	os_memcpy(iv, iv_crypt, AES_BLOCK_SIZE);
++	os_memcpy(out, iv_crypt + AES_BLOCK_SIZE, crypt_len);
++
++	iv[8] &= 0x7f;
++	iv[12] &= 0x7f;
++
++	ret = aes_ctr_encrypt(k2, key_len, iv, out, crypt_len);
++	if (ret)
++		return ret;
++
++	ret = aes_s2v(k1, key_len, num_elem + 1, _addr, _len, check);
++	if (ret)
++		return ret;
++	if (os_memcmp(check, iv_crypt, AES_BLOCK_SIZE) == 0)
++		return 0;
++
++	return -1;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes.h
+new file mode 100644
+index 000000000..8ab3de2ee
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes.h
+@@ -0,0 +1,21 @@
++/*
++ * AES functions
++ * Copyright (c) 2003-2006, Jouni Malinen <j@w1.fi>
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#ifndef AES_H
++#define AES_H
++
++#define AES_BLOCK_SIZE 16
++
++void * aes_encrypt_init(const u8 *key, size_t len);
++int aes_encrypt(void *ctx, const u8 *plain, u8 *crypt);
++void aes_encrypt_deinit(void *ctx);
++void * aes_decrypt_init(const u8 *key, size_t len);
++int aes_decrypt(void *ctx, const u8 *crypt, u8 *plain);
++void aes_decrypt_deinit(void *ctx);
++
++#endif /* AES_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes_i.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes_i.h
+new file mode 100644
+index 000000000..54375cf35
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes_i.h
+@@ -0,0 +1,125 @@
++/*
++ * AES (Rijndael) cipher
++ * Copyright (c) 2003-2012, Jouni Malinen <j@w1.fi>
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#ifndef AES_I_H
++#define AES_I_H
++
++#include "aes.h"
++
++/* #define FULL_UNROLL */
++#define AES_SMALL_TABLES
++
++extern const u32 Te0[256];
++extern const u32 Te1[256];
++extern const u32 Te2[256];
++extern const u32 Te3[256];
++extern const u32 Te4[256];
++extern const u32 Td0[256];
++extern const u32 Td1[256];
++extern const u32 Td2[256];
++extern const u32 Td3[256];
++extern const u32 Td4[256];
++extern const u32 rcon[10];
++extern const u8 Td4s[256];
++extern const u8 rcons[10];
++
++#ifndef AES_SMALL_TABLES
++
++#define RCON(i) rcon[(i)]
++
++#define TE0(i) Te0[((i) >> 24) & 0xff]
++#define TE1(i) Te1[((i) >> 16) & 0xff]
++#define TE2(i) Te2[((i) >> 8) & 0xff]
++#define TE3(i) Te3[(i) & 0xff]
++#define TE41(i) (Te4[((i) >> 24) & 0xff] & 0xff000000)
++#define TE42(i) (Te4[((i) >> 16) & 0xff] & 0x00ff0000)
++#define TE43(i) (Te4[((i) >> 8) & 0xff] & 0x0000ff00)
++#define TE44(i) (Te4[(i) & 0xff] & 0x000000ff)
++#define TE421(i) (Te4[((i) >> 16) & 0xff] & 0xff000000)
++#define TE432(i) (Te4[((i) >> 8) & 0xff] & 0x00ff0000)
++#define TE443(i) (Te4[(i) & 0xff] & 0x0000ff00)
++#define TE414(i) (Te4[((i) >> 24) & 0xff] & 0x000000ff)
++#define TE411(i) (Te4[((i) >> 24) & 0xff] & 0xff000000)
++#define TE422(i) (Te4[((i) >> 16) & 0xff] & 0x00ff0000)
++#define TE433(i) (Te4[((i) >> 8) & 0xff] & 0x0000ff00)
++#define TE444(i) (Te4[(i) & 0xff] & 0x000000ff)
++#define TE4(i) (Te4[(i)] & 0x000000ff)
++
++#define TD0(i) Td0[((i) >> 24) & 0xff]
++#define TD1(i) Td1[((i) >> 16) & 0xff]
++#define TD2(i) Td2[((i) >> 8) & 0xff]
++#define TD3(i) Td3[(i) & 0xff]
++#define TD41(i) (Td4[((i) >> 24) & 0xff] & 0xff000000)
++#define TD42(i) (Td4[((i) >> 16) & 0xff] & 0x00ff0000)
++#define TD43(i) (Td4[((i) >> 8) & 0xff] & 0x0000ff00)
++#define TD44(i) (Td4[(i) & 0xff] & 0x000000ff)
++#define TD0_(i) Td0[(i) & 0xff]
++#define TD1_(i) Td1[(i) & 0xff]
++#define TD2_(i) Td2[(i) & 0xff]
++#define TD3_(i) Td3[(i) & 0xff]
++
++#else /* AES_SMALL_TABLES */
++
++#define RCON(i) (rcons[(i)] << 24)
++
++static inline u32 rotr(u32 val, int bits)
++{
++	return (val >> bits) | (val << (32 - bits));
++}
++
++#define TE0(i) Te0[((i) >> 24) & 0xff]
++#define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8)
++#define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16)
++#define TE3(i) rotr(Te0[(i) & 0xff], 24)
++#define TE41(i) ((Te0[((i) >> 24) & 0xff] << 8) & 0xff000000)
++#define TE42(i) (Te0[((i) >> 16) & 0xff] & 0x00ff0000)
++#define TE43(i) (Te0[((i) >> 8) & 0xff] & 0x0000ff00)
++#define TE44(i) ((Te0[(i) & 0xff] >> 8) & 0x000000ff)
++#define TE421(i) ((Te0[((i) >> 16) & 0xff] << 8) & 0xff000000)
++#define TE432(i) (Te0[((i) >> 8) & 0xff] & 0x00ff0000)
++#define TE443(i) (Te0[(i) & 0xff] & 0x0000ff00)
++#define TE414(i) ((Te0[((i) >> 24) & 0xff] >> 8) & 0x000000ff)
++#define TE411(i) ((Te0[((i) >> 24) & 0xff] << 8) & 0xff000000)
++#define TE422(i) (Te0[((i) >> 16) & 0xff] & 0x00ff0000)
++#define TE433(i) (Te0[((i) >> 8) & 0xff] & 0x0000ff00)
++#define TE444(i) ((Te0[(i) & 0xff] >> 8) & 0x000000ff)
++#define TE4(i) ((Te0[(i)] >> 8) & 0x000000ff)
++
++#define TD0(i) Td0[((i) >> 24) & 0xff]
++#define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8)
++#define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16)
++#define TD3(i) rotr(Td0[(i) & 0xff], 24)
++#define TD41(i) (Td4s[((i) >> 24) & 0xff] << 24)
++#define TD42(i) (Td4s[((i) >> 16) & 0xff] << 16)
++#define TD43(i) (Td4s[((i) >> 8) & 0xff] << 8)
++#define TD44(i) (Td4s[(i) & 0xff])
++#define TD0_(i) Td0[(i) & 0xff]
++#define TD1_(i) rotr(Td0[(i) & 0xff], 8)
++#define TD2_(i) rotr(Td0[(i) & 0xff], 16)
++#define TD3_(i) rotr(Td0[(i) & 0xff], 24)
++
++#endif /* AES_SMALL_TABLES */
++
++#ifdef _MSC_VER
++#define SWAP(x) (_lrotl(x, 8) & 0x00ff00ff | _lrotr(x, 8) & 0xff00ff00)
++#define GETU32(p) SWAP(*((u32 *)(p)))
++#define PUTU32(ct, st) { *((u32 *)(ct)) = SWAP((st)); }
++#else
++#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ \
++((u32)(pt)[2] <<  8) ^ ((u32)(pt)[3]))
++#define PUTU32(ct, st) { \
++(ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); \
++(ct)[2] = (u8)((st) >>  8); (ct)[3] = (u8)(st); }
++#endif
++
++#define AES_PRIV_SIZE (4 * 4 * 15 + 4)
++#define AES_PRIV_NR_POS (4 * 15)
++
++int rijndaelKeySetupEnc(u32 rk[], const u8 cipherKey[], int keyBits);
++
++#endif /* AES_I_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes_siv.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes_siv.h
+new file mode 100644
+index 000000000..fb05d80c1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes_siv.h
+@@ -0,0 +1,21 @@
++/*
++ * AES SIV (RFC 5297)
++ * Copyright (c) 2013 Cozybit, Inc.
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#ifndef AES_SIV_H
++#define AES_SIV_H
++
++int aes_siv_encrypt(const u8 *key, size_t key_len,
++		    const u8 *pw, size_t pwlen,
++		    size_t num_elem, const u8 *addr[], const size_t *len,
++		    u8 *out);
++int aes_siv_decrypt(const u8 *key, size_t key_len,
++		    const u8 *iv_crypt, size_t iv_c_len,
++		    size_t num_elem, const u8 *addr[], const size_t *len,
++		    u8 *out);
++
++#endif /* AES_SIV_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes_wrap.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes_wrap.h
+new file mode 100644
+index 000000000..b70b1d26e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/aes_wrap.h
+@@ -0,0 +1,73 @@
++/*
++ * AES-based functions
++ *
++ * - AES Key Wrap Algorithm (RFC3394)
++ * - One-Key CBC MAC (OMAC1) hash with AES-128 and AES-256
++ * - AES-128/192/256 CTR mode encryption
++ * - AES-128 EAX mode encryption/decryption
++ * - AES-128 CBC
++ * - AES-GCM
++ * - AES-CCM
++ *
++ * Copyright (c) 2003-2012, Jouni Malinen <j@w1.fi>
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#ifndef AES_WRAP_H
++#define AES_WRAP_H
++
++int __must_check aes_wrap(const u8 *kek, size_t kek_len, int n, const u8 *plain,
++			  u8 *cipher);
++int __must_check aes_unwrap(const u8 *kek, size_t kek_len, int n,
++			    const u8 *cipher, u8 *plain);
++int __must_check omac1_aes_vector(const u8 *key, size_t key_len,
++				  size_t num_elem, const u8 *addr[],
++				  const size_t *len, u8 *mac);
++int __must_check omac1_aes_128_vector(const u8 *key, size_t num_elem,
++				      const u8 *addr[], const size_t *len,
++				      u8 *mac);
++int __must_check omac1_aes_128(const u8 *key, const u8 *data, size_t data_len,
++			       u8 *mac);
++int __must_check omac1_aes_256(const u8 *key, const u8 *data, size_t data_len,
++			       u8 *mac);
++int __must_check aes_128_encrypt_block(const u8 *key, const u8 *in, u8 *out);
++int __must_check aes_ctr_encrypt(const u8 *key, size_t key_len, const u8 *nonce,
++				 u8 *data, size_t data_len);
++int __must_check aes_128_ctr_encrypt(const u8 *key, const u8 *nonce,
++				     u8 *data, size_t data_len);
++int __must_check aes_128_eax_encrypt(const u8 *key,
++				     const u8 *nonce, size_t nonce_len,
++				     const u8 *hdr, size_t hdr_len,
++				     u8 *data, size_t data_len, u8 *tag);
++int __must_check aes_128_eax_decrypt(const u8 *key,
++				     const u8 *nonce, size_t nonce_len,
++				     const u8 *hdr, size_t hdr_len,
++				     u8 *data, size_t data_len, const u8 *tag);
++int __must_check aes_128_cbc_encrypt(const u8 *key, const u8 *iv, u8 *data,
++				     size_t data_len);
++int __must_check aes_128_cbc_decrypt(const u8 *key, const u8 *iv, u8 *data,
++				     size_t data_len);
++int __must_check aes_gcm_ae(const u8 *key, size_t key_len,
++			    const u8 *iv, size_t iv_len,
++			    const u8 *plain, size_t plain_len,
++			    const u8 *aad, size_t aad_len,
++			    u8 *crypt, u8 *tag);
++int __must_check aes_gcm_ad(const u8 *key, size_t key_len,
++			    const u8 *iv, size_t iv_len,
++			    const u8 *crypt, size_t crypt_len,
++			    const u8 *aad, size_t aad_len, const u8 *tag,
++			    u8 *plain);
++int __must_check aes_gmac(const u8 *key, size_t key_len,
++			  const u8 *iv, size_t iv_len,
++			  const u8 *aad, size_t aad_len, u8 *tag);
++int __must_check aes_ccm_ae(const u8 *key, size_t key_len, const u8 *nonce,
++			    size_t M, const u8 *plain, size_t plain_len,
++			    const u8 *aad, size_t aad_len, u8 *crypt, u8 *auth);
++int __must_check aes_ccm_ad(const u8 *key, size_t key_len, const u8 *nonce,
++			    size_t M, const u8 *crypt, size_t crypt_len,
++			    const u8 *aad, size_t aad_len, const u8 *auth,
++			    u8 *plain);
++
++#endif /* AES_WRAP_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/ccmp.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/ccmp.c
+new file mode 100644
+index 000000000..f7742f83a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/ccmp.c
+@@ -0,0 +1,384 @@
++/*
++ * CTR with CBC-MAC Protocol (CCMP)
++ * Copyright (c) 2010-2012, Jouni Malinen <j@w1.fi>
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#include "rtw_crypto_wrap.h"
++
++#include "aes.h"
++#include "aes_wrap.h"
++#include "wlancrypto_wrap.h"
++
++
++
++static void ccmp_aad_nonce(const struct ieee80211_hdr *hdr, const u8 *data,
++			   u8 *aad, size_t *aad_len, u8 *nonce)
++{
++	u16 fc, stype, seq;
++	int qos = 0, addr4 = 0;
++	u8 *pos;
++
++	nonce[0] = 0;
++
++	fc = le_to_host16(hdr->frame_control);
++	stype = WLAN_FC_GET_STYPE(fc);
++	if ((fc & (WLAN_FC_TODS | WLAN_FC_FROMDS)) ==
++	    (WLAN_FC_TODS | WLAN_FC_FROMDS))
++		addr4 = 1;
++
++	if (WLAN_FC_GET_TYPE(fc) == WLAN_FC_TYPE_DATA) {
++		fc &= ~0x0070; /* Mask subtype bits */
++		if (stype & WLAN_FC_STYPE_QOS_DATA) {
++			const u8 *qc;
++			qos = 1;
++			fc &= ~WLAN_FC_ORDER;
++			qc = (const u8 *)hdr + 24;
++			if (addr4)
++				qc += ETH_ALEN;
++			nonce[0] = qc[0] & 0x0f;
++		}
++	} else if (WLAN_FC_GET_TYPE(fc) == WLAN_FC_TYPE_MGMT)
++		nonce[0] |= 0x10; /* Management */
++
++	fc &= ~(WLAN_FC_RETRY | WLAN_FC_PWRMGT | WLAN_FC_MOREDATA);
++	fc |= WLAN_FC_ISWEP;
++	WPA_PUT_LE16(aad, fc);
++	pos = aad + 2;
++	os_memcpy(pos, hdr->addr1, 3 * ETH_ALEN);
++	pos += 3 * ETH_ALEN;
++	seq = le_to_host16(hdr->seq_ctrl);
++	seq &= ~0xfff0; /* Mask Seq#; do not modify Frag# */
++	WPA_PUT_LE16(pos, seq);
++	pos += 2;
++
++	os_memcpy(pos, (u8 *)hdr + 24, addr4 * ETH_ALEN + qos * 2);
++	pos += addr4 * ETH_ALEN;
++	if (qos) {
++		pos[0] &= ~0x70;
++		if (1 /* FIX: either device has SPP A-MSDU Capab = 0 */)
++			pos[0] &= ~0x80;
++		pos++;
++		*pos++ = 0x00;
++	}
++
++	*aad_len = pos - aad;
++
++	os_memcpy(nonce + 1, hdr->addr2, ETH_ALEN);
++	nonce[7] = data[7]; /* PN5 */
++	nonce[8] = data[6]; /* PN4 */
++	nonce[9] = data[5]; /* PN3 */
++	nonce[10] = data[4]; /* PN2 */
++	nonce[11] = data[1]; /* PN1 */
++	nonce[12] = data[0]; /* PN0 */
++}
++
++
++static void ccmp_aad_nonce_pv1(const u8 *hdr, const u8 *a1, const u8 *a2,
++			       const u8 *a3, const u8 *pn,
++			       u8 *aad, size_t *aad_len, u8 *nonce)
++{
++	u16 fc, type;
++	u8 *pos;
++
++	nonce[0] = BIT(5); /* PV1 */
++	/* TODO: Priority for QMF; 0 is used for Data frames */
++
++	fc = WPA_GET_LE16(hdr);
++	type = (fc & (BIT(2) | BIT(3) | BIT(4))) >> 2;
++
++	if (type == 1)
++		nonce[0] |= 0x10; /* Management */
++
++	fc &= ~(BIT(10) | BIT(11) | BIT(13) | BIT(14) | BIT(15));
++	fc |= BIT(12);
++	WPA_PUT_LE16(aad, fc);
++	pos = aad + 2;
++	if (type == 0 || type == 3) {
++		const u8 *sc;
++
++		os_memcpy(pos, a1, ETH_ALEN);
++		pos += ETH_ALEN;
++		os_memcpy(pos, a2, ETH_ALEN);
++		pos += ETH_ALEN;
++
++		if (type == 0) {
++			/* Either A1 or A2 contains SID */
++			sc = hdr + 2 + 2 + ETH_ALEN;
++		} else {
++			/* Both A1 and A2 contain full addresses */
++			sc = hdr + 2 + 2 * ETH_ALEN;
++		}
++		/* SC with Sequence Number subfield (bits 4-15 of the Sequence
++		 * Control field) masked to 0. */
++		*pos++ = *sc & 0x0f;
++		*pos++ = 0;
++
++		if (a3) {
++			os_memcpy(pos, a3, ETH_ALEN);
++			pos += ETH_ALEN;
++		}
++	}
++
++	*aad_len = pos - aad;
++
++	os_memcpy(nonce + 1, a2, ETH_ALEN);
++	nonce[7] = pn[5]; /* PN5 */
++	nonce[8] = pn[4]; /* PN4 */
++	nonce[9] = pn[3]; /* PN3 */
++	nonce[10] = pn[2]; /* PN2 */
++	nonce[11] = pn[1]; /* PN1 */
++	nonce[12] = pn[0]; /* PN0 */
++}
++
++
++u8 * ccmp_decrypt(const u8 *tk, const struct ieee80211_hdr *hdr,
++		  const u8 *data, size_t data_len, size_t *decrypted_len)
++{
++	u8 aad[30], nonce[13];
++	size_t aad_len;
++	size_t mlen;
++	u8 *plain;
++
++	if (data_len < 8 + 8)
++		return NULL;
++
++	plain = os_malloc(data_len + AES_BLOCK_SIZE);
++	if (plain == NULL)
++		return NULL;
++
++	mlen = data_len - 8 - 8;
++
++	os_memset(aad, 0, sizeof(aad));
++	ccmp_aad_nonce(hdr, data, aad, &aad_len, nonce);
++	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP AAD", aad, aad_len);
++	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP nonce", nonce, 13);
++
++	if (aes_ccm_ad(tk, 16, nonce, 8, data + 8, mlen, aad, aad_len,
++		       data + 8 + mlen, plain) < 0) {
++		u16 seq_ctrl = le_to_host16(hdr->seq_ctrl);
++		wpa_printf(_MSG_INFO_, "Invalid CCMP MIC in frame: A1=" MACSTR
++			   " A2=" MACSTR " A3=" MACSTR " seq=%u frag=%u",
++			   MAC2STR(hdr->addr1), MAC2STR(hdr->addr2),
++			   MAC2STR(hdr->addr3),
++			   WLAN_GET_SEQ_SEQ(seq_ctrl),
++			   WLAN_GET_SEQ_FRAG(seq_ctrl));
++		rtw_mfree(plain, data_len + AES_BLOCK_SIZE);
++		return NULL;
++	}
++	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP decrypted", plain, mlen);
++
++	*decrypted_len = mlen;
++	return plain;
++}
++
++
++void ccmp_get_pn(u8 *pn, const u8 *data)
++{
++	pn[0] = data[7]; /* PN5 */
++	pn[1] = data[6]; /* PN4 */
++	pn[2] = data[5]; /* PN3 */
++	pn[3] = data[4]; /* PN2 */
++	pn[4] = data[1]; /* PN1 */
++	pn[5] = data[0]; /* PN0 */
++}
++
++
++u8 * ccmp_encrypt(const u8 *tk, u8 *frame, size_t len, size_t hdrlen, u8 *qos,
++		  u8 *pn, int keyid, size_t *encrypted_len)
++{
++	u8 aad[30], nonce[13];
++	size_t aad_len, plen;
++	u8 *crypt, *pos, *pdata;
++	struct ieee80211_hdr *hdr;
++
++	if (len < hdrlen || hdrlen < 24)
++		return NULL;
++	plen = len - hdrlen;
++
++	crypt = os_malloc(hdrlen + 8 + plen + 8 + AES_BLOCK_SIZE);
++	if (crypt == NULL)
++		return NULL;
++
++	if (pn == NULL) {
++		os_memcpy(crypt, frame, hdrlen + 8);
++		hdr = (struct ieee80211_hdr *) crypt;
++		hdr->frame_control |= host_to_le16(WLAN_FC_ISWEP);
++		pos = crypt + hdrlen + 8;
++		pdata = frame + hdrlen + 8;
++	} else {
++		os_memcpy(crypt, frame, hdrlen);
++		hdr = (struct ieee80211_hdr *) crypt;
++		hdr->frame_control |= host_to_le16(WLAN_FC_ISWEP);
++		pos = crypt + hdrlen;
++		*pos++ = pn[5]; /* PN0 */
++		*pos++ = pn[4]; /* PN1 */
++		*pos++ = 0x00; /* Rsvd */
++		*pos++ = 0x20 | (keyid << 6);
++		*pos++ = pn[3]; /* PN2 */
++		*pos++ = pn[2]; /* PN3 */
++		*pos++ = pn[1]; /* PN4 */
++		*pos++ = pn[0]; /* PN5 */
++		pdata = frame + hdrlen;
++	}
++
++	os_memset(aad, 0, sizeof(aad));
++	ccmp_aad_nonce(hdr, crypt + hdrlen, aad, &aad_len, nonce);
++	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP AAD", aad, aad_len);
++	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP nonce", nonce, 13);
++
++	if (aes_ccm_ae(tk, 16, nonce, 8, pdata, plen, aad, aad_len,
++		       pos, pos + plen) < 0) {
++		rtw_mfree(crypt, hdrlen + 8 + plen + 8 + AES_BLOCK_SIZE);
++		return NULL;
++	}
++
++	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP encrypted", crypt + hdrlen + 8, plen);
++
++	*encrypted_len = hdrlen + 8 + plen + 8;
++
++	return crypt;
++}
++
++
++u8 * ccmp_encrypt_pv1(const u8 *tk, const u8 *a1, const u8 *a2, const u8 *a3,
++		      const u8 *frame, size_t len,
++		      size_t hdrlen, const u8 *pn, int keyid,
++		      size_t *encrypted_len)
++{
++	u8 aad[24], nonce[13];
++	size_t aad_len, plen;
++	u8 *crypt, *pos;
++	struct ieee80211_hdr *hdr;
++
++	if (len < hdrlen || hdrlen < 12)
++		return NULL;
++	plen = len - hdrlen;
++
++	crypt = os_malloc(hdrlen + plen + 8 + AES_BLOCK_SIZE);
++	if (crypt == NULL)
++		return NULL;
++
++	os_memcpy(crypt, frame, hdrlen);
++	hdr = (struct ieee80211_hdr *) crypt;
++	hdr->frame_control |= host_to_le16(BIT(12)); /* Protected Frame */
++	pos = crypt + hdrlen;
++
++	os_memset(aad, 0, sizeof(aad));
++	ccmp_aad_nonce_pv1(crypt, a1, a2, a3, pn, aad, &aad_len, nonce);
++	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP AAD", aad, aad_len);
++	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP nonce", nonce, sizeof(nonce));
++
++	if (aes_ccm_ae(tk, 16, nonce, 8, frame + hdrlen, plen, aad, aad_len,
++		       pos, pos + plen) < 0) {
++		rtw_mfree(crypt, hdrlen + plen + 8 + AES_BLOCK_SIZE);
++		return NULL;
++	}
++
++	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP encrypted", crypt + hdrlen, plen);
++
++	*encrypted_len = hdrlen + plen + 8;
++
++	return crypt;
++}
++
++
++u8 * ccmp_256_decrypt(const u8 *tk, const struct ieee80211_hdr *hdr,
++		      const u8 *data, size_t data_len, size_t *decrypted_len)
++{
++	u8 aad[30], nonce[13];
++	size_t aad_len;
++	size_t mlen;
++	u8 *plain;
++
++	if (data_len < 8 + 16)
++		return NULL;
++
++	plain = os_malloc(data_len + AES_BLOCK_SIZE);
++	if (plain == NULL)
++		return NULL;
++
++	mlen = data_len - 8 - 16;
++
++	os_memset(aad, 0, sizeof(aad));
++	ccmp_aad_nonce(hdr, data, aad, &aad_len, nonce);
++	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP-256 AAD", aad, aad_len);
++	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP-256 nonce", nonce, 13);
++
++	if (aes_ccm_ad(tk, 32, nonce, 16, data + 8, mlen, aad, aad_len,
++		       data + 8 + mlen, plain) < 0) {
++		u16 seq_ctrl = le_to_host16(hdr->seq_ctrl);
++		wpa_printf(_MSG_INFO_, "Invalid CCMP-256 MIC in frame: A1=" MACSTR
++			   " A2=" MACSTR " A3=" MACSTR " seq=%u frag=%u",
++			   MAC2STR(hdr->addr1), MAC2STR(hdr->addr2),
++			   MAC2STR(hdr->addr3),
++			   WLAN_GET_SEQ_SEQ(seq_ctrl),
++			   WLAN_GET_SEQ_FRAG(seq_ctrl));
++		rtw_mfree(plain, data_len + AES_BLOCK_SIZE);
++		return NULL;
++	}
++	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP-256 decrypted", plain, mlen);
++
++	*decrypted_len = mlen;
++	return plain;
++}
++
++
++u8 * ccmp_256_encrypt(const u8 *tk, u8 *frame, size_t len, size_t hdrlen,
++		      u8 *qos, u8 *pn, int keyid, size_t *encrypted_len)
++{
++	u8 aad[30], nonce[13];
++	size_t aad_len, plen;
++	u8 *crypt, *pos, *pdata;
++	struct ieee80211_hdr *hdr;
++
++	if (len < hdrlen || hdrlen < 24)
++		return NULL;
++	plen = len - hdrlen;
++
++	crypt = os_malloc(hdrlen + 8 + plen + 16 + AES_BLOCK_SIZE);
++	if (crypt == NULL)
++		return NULL;
++
++	if (pn == NULL) {
++		os_memcpy(crypt, frame, hdrlen + 8);
++		hdr = (struct ieee80211_hdr *) crypt;
++		hdr->frame_control |= host_to_le16(WLAN_FC_ISWEP);
++		pos = crypt + hdrlen + 8;
++		pdata = frame + hdrlen + 8;
++	} else {
++		os_memcpy(crypt, frame, hdrlen);
++		hdr = (struct ieee80211_hdr *) crypt;
++		hdr->frame_control |= host_to_le16(WLAN_FC_ISWEP);
++		pos = crypt + hdrlen;
++		*pos++ = pn[5]; /* PN0 */
++		*pos++ = pn[4]; /* PN1 */
++		*pos++ = 0x00; /* Rsvd */
++		*pos++ = 0x20 | (keyid << 6);
++		*pos++ = pn[3]; /* PN2 */
++		*pos++ = pn[2]; /* PN3 */
++		*pos++ = pn[1]; /* PN4 */
++		*pos++ = pn[0]; /* PN5 */
++		pdata = frame + hdrlen;
++	}
++
++	os_memset(aad, 0, sizeof(aad));
++	ccmp_aad_nonce(hdr, crypt + hdrlen, aad, &aad_len, nonce);
++	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP-256 AAD", aad, aad_len);
++	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP-256 nonce", nonce, 13);
++
++	if (aes_ccm_ae(tk, 32, nonce, 16, pdata, plen, aad, aad_len,
++		       pos, pos + plen) < 0) {
++		rtw_mfree(crypt, hdrlen + 8 + plen + 16 + AES_BLOCK_SIZE);
++		return NULL;
++	}
++
++	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP-256 encrypted", crypt + hdrlen + 8,
++		    plen);
++
++	*encrypted_len = hdrlen + 8 + plen + 16;
++
++	return crypt;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/gcmp.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/gcmp.c
+new file mode 100644
+index 000000000..22e68d60e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/gcmp.c
+@@ -0,0 +1,193 @@
++/*
++ * GCM with GMAC Protocol (GCMP)
++ * Copyright (c) 2012, Jouni Malinen <j@w1.fi>
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#include "rtw_crypto_wrap.h"
++
++#include "aes.h"
++#include "aes_wrap.h"
++#include "wlancrypto_wrap.h"
++
++
++static void gcmp_aad_nonce(const struct ieee80211_hdr *hdr, const u8 *data,
++			   u8 *aad, size_t *aad_len, u8 *nonce)
++{
++	u16 fc, stype, seq;
++	int qos = 0, addr4 = 0;
++	u8 *pos;
++
++	fc = le_to_host16(hdr->frame_control);
++	stype = WLAN_FC_GET_STYPE(fc);
++	if ((fc & (WLAN_FC_TODS | WLAN_FC_FROMDS)) ==
++	    (WLAN_FC_TODS | WLAN_FC_FROMDS))
++		addr4 = 1;
++
++	if (WLAN_FC_GET_TYPE(fc) == WLAN_FC_TYPE_DATA) {
++		fc &= ~0x0070; /* Mask subtype bits */
++		if (stype & WLAN_FC_STYPE_QOS_DATA) {
++			const u8 *qc;
++			qos = 1;
++			fc &= ~WLAN_FC_ORDER;
++			qc = (const u8 *)hdr + 24;
++			if (addr4)
++				qc += ETH_ALEN;
++		}
++	}
++
++	fc &= ~(WLAN_FC_RETRY | WLAN_FC_PWRMGT | WLAN_FC_MOREDATA);
++	WPA_PUT_LE16(aad, fc);
++	pos = aad + 2;
++	os_memcpy(pos, hdr->addr1, 3 * ETH_ALEN);
++	pos += 3 * ETH_ALEN;
++	seq = le_to_host16(hdr->seq_ctrl);
++	seq &= ~0xfff0; /* Mask Seq#; do not modify Frag# */
++	WPA_PUT_LE16(pos, seq);
++	pos += 2;
++
++	wpa_printf(_MSG_INFO_, "pos - aad = %u, qos(%d)\n", (pos - aad), qos);
++
++	os_memcpy(pos, (u8 *)hdr + 24, addr4 * ETH_ALEN + qos * 2);
++	pos += addr4 * ETH_ALEN;
++	if (qos) {
++		pos[0] &= ~0x70;
++		if (1 /* FIX: either device has SPP A-MSDU Capab = 0 */)
++			pos[0] &= ~0x80;
++		pos++;
++		*pos++ = 0x00;
++	}
++
++	wpa_printf(_MSG_INFO_, "pos - aad = %u\n", (pos - aad));
++	*aad_len = pos - aad;
++
++	os_memcpy(nonce, hdr->addr2, ETH_ALEN);
++	nonce[6] = data[7]; /* PN5 */
++	nonce[7] = data[6]; /* PN4 */
++	nonce[8] = data[5]; /* PN3 */
++	nonce[9] = data[4]; /* PN2 */
++	nonce[10] = data[1]; /* PN1 */
++	nonce[11] = data[0]; /* PN0 */
++}
++
++/**
++ * gcmp_decrypt -
++ * @tk: the temporal key
++ * @tk_len: length of @tk
++ * @hdr: the mac header
++ * @data: payload after mac header (PN + enc_data + MIC)
++ * @data_len: length of @data (PN + enc_data + MIC)
++ * @decrypted_len: length of the data decrypted
++ */
++u8 * gcmp_decrypt(const u8 *tk, size_t tk_len, const struct ieee80211_hdr *hdr,
++		  const u8 *data, size_t data_len, size_t *decrypted_len)
++{
++	u8 aad[30], nonce[12], *plain;
++	size_t aad_len, mlen;
++	const u8 *m;
++
++	if (data_len < 8 + 16)
++		return NULL;
++
++	plain = os_malloc(data_len + AES_BLOCK_SIZE);
++	if (plain == NULL)
++		return NULL;
++
++	m = data + 8;
++	mlen = data_len - 8 - 16;
++
++	os_memset(aad, 0, sizeof(aad));
++	gcmp_aad_nonce(hdr, data, aad, &aad_len, nonce);
++	wpa_hexdump(_MSG_EXCESSIVE_, "GCMP AAD", aad, aad_len);
++	wpa_hexdump(_MSG_EXCESSIVE_, "GCMP nonce", nonce, sizeof(nonce));
++
++	if (aes_gcm_ad(tk, tk_len, nonce, sizeof(nonce), m, mlen, aad, aad_len,
++		       m + mlen, plain) < 0) {
++		u16 seq_ctrl = le_to_host16(hdr->seq_ctrl);
++		wpa_printf(_MSG_INFO_, "Invalid GCMP frame: A1=" MACSTR
++			   " A2=" MACSTR " A3=" MACSTR " seq=%u frag=%u",
++			   MAC2STR(hdr->addr1), MAC2STR(hdr->addr2),
++			   MAC2STR(hdr->addr3),
++			   WLAN_GET_SEQ_SEQ(seq_ctrl),
++			   WLAN_GET_SEQ_FRAG(seq_ctrl));
++		rtw_mfree(plain, data_len + AES_BLOCK_SIZE);
++		return NULL;
++	}
++
++	*decrypted_len = mlen;
++	return plain;
++}
++
++/**
++ * gcmp_encrypt - 
++ * @tk: the temporal key
++ * @tk_len: length of @tk
++ * @frame: the point to mac header, the frame including mac header and payload, 
++ *         if @pn is NULL, then the frame including pn
++ * @len: length of @frame 
++ *         length = mac header + payload
++ * @hdrlen: length of the mac header
++ * @qos: pointer to the QOS field of the frame
++ * @pn: packet number
++ * @keyid: key id
++ * @encrypted_len: length of the encrypted frame 
++ *                 including mac header, pn, payload and MIC
++ */
++u8 * gcmp_encrypt(const u8 *tk, size_t tk_len, const u8 *frame, size_t len,
++		  size_t hdrlen, const u8 *qos,
++		  const u8 *pn, int keyid, size_t *encrypted_len)
++{
++	u8 aad[30], nonce[12], *crypt, *pos;
++	const u8 *pdata;
++	size_t aad_len, plen;
++	struct ieee80211_hdr *hdr;
++
++	if (len < hdrlen || hdrlen < 24)
++		return NULL;
++	plen = len - hdrlen;
++
++	crypt = os_malloc(hdrlen + 8 + plen + 16 + AES_BLOCK_SIZE);
++	if (crypt == NULL)
++		return NULL;
++
++	if (pn == NULL) {
++		os_memcpy(crypt, frame, hdrlen + 8);
++		hdr = (struct ieee80211_hdr *)crypt;
++		pos = crypt + hdrlen + 8;
++		pdata = frame + hdrlen + 8;
++	} else {
++		os_memcpy(crypt, frame, hdrlen);
++		hdr = (struct ieee80211_hdr *)crypt;
++		pos = crypt + hdrlen;
++
++		*pos++ = pn[5]; /* PN0 */
++		*pos++ = pn[4]; /* PN1 */
++		*pos++ = 0x00; /* Rsvd */
++		*pos++ = 0x20 | (keyid << 6);
++		*pos++ = pn[3]; /* PN2 */
++		*pos++ = pn[2]; /* PN3 */
++		*pos++ = pn[1]; /* PN4 */
++		*pos++ = pn[0]; /* PN5 */
++		pdata = frame + hdrlen;
++	}
++
++	os_memset(aad, 0, sizeof(aad));
++	gcmp_aad_nonce(hdr, crypt + hdrlen, aad, &aad_len, nonce);
++	wpa_hexdump(_MSG_EXCESSIVE_, "GCMP AAD", aad, aad_len);
++	wpa_hexdump(_MSG_EXCESSIVE_, "GCMP nonce", nonce, sizeof(nonce));
++
++	if (aes_gcm_ae(tk, tk_len, nonce, sizeof(nonce), pdata, plen,
++			aad, aad_len, pos, pos + plen) < 0) {
++		rtw_mfree(crypt, hdrlen + 8 + plen + 16 + AES_BLOCK_SIZE);
++		return NULL;
++	}
++
++	wpa_hexdump(_MSG_EXCESSIVE_, "GCMP MIC", pos + plen, 16);
++	wpa_hexdump(_MSG_EXCESSIVE_, "GCMP encrypted", pos, plen);
++
++	*encrypted_len = hdrlen + 8 + plen + 16;
++
++	return crypt;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/rtw_crypto_wrap.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/rtw_crypto_wrap.c
+new file mode 100644
+index 000000000..ee02a803e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/rtw_crypto_wrap.c
+@@ -0,0 +1,90 @@
++#include "rtw_crypto_wrap.h"
++
++#ifndef DEBUG_CRYPTO
++#define DEBUG_CRYPTO 0
++#endif /* DEBUG_CRYTO */
++
++int os_memcmp(const void *s1, const void *s2, size_t n)
++{
++	return _rtw_memcmp2(s1, s2, n);
++}
++
++int os_memcmp_const(const void *a, const void *b, size_t len)
++{
++	const u8 *aa = a;
++	const u8 *bb = b;
++	size_t i;
++	u8 res;
++
++	for (res = 0, i = 0; i < len; i++)
++		res |= aa[i] ^ bb[i];
++
++	return res;
++}
++
++void* os_memdup(const void *src, u32 sz)
++{
++	void *r = rtw_malloc(sz);
++
++	if (r && src)
++		_rtw_memcpy(r, src, sz);
++	return r;
++}
++
++size_t os_strlen(const char *s)
++{
++	const char *p = s;
++	while (*p)
++		p++;
++	return p - s;
++}
++
++
++void forced_memzero(void *ptr, size_t len)
++{
++	_rtw_memset(ptr, 0, len);
++}
++
++void bin_clear_free(void *bin, size_t len)
++{
++	if (bin) {
++		forced_memzero(bin, len);
++		rtw_mfree(bin, len);
++	}
++}
++
++void wpa_printf(int level, const char *fmt, ...)
++{
++#if DEBUG_CRYPTO
++#define MSG_LEN 100
++	va_list args;
++	u8 buf[MSG_LEN] = { 0 };
++	int err;
++
++	va_start(args, fmt);
++	err = vsnprintf(buf, MSG_LEN, fmt, args);
++	va_end(args);
++
++	RTW_INFO("%s", buf);
++#undef MSG_LEN
++#endif /* DEBUG_CRYPTO */
++}
++
++void wpa_hexdump(int level, const char *title, const void *buf, size_t len)
++{
++#if DEBUG_CRYPTO
++	RTW_INFO_DUMP((u8 *)title, buf, len);
++#endif /* DEBUG_CRYPTO */
++}
++
++void wpa_hexdump_key(int level, const char *title, const void *buf, size_t len)
++{
++#if DEBUG_CRYPTO
++	RTW_INFO_DUMP((u8 *)title, buf, len);
++#endif /* DEBUG_CRYPTO */
++}
++
++u32 crc32(const u8 *frame, size_t frame_len)
++{
++	return rtw_calc_crc32((u8 *)frame, frame_len);
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/rtw_crypto_wrap.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/rtw_crypto_wrap.h
+new file mode 100644
+index 000000000..bdb4d8ad1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/rtw_crypto_wrap.h
+@@ -0,0 +1,65 @@
++#ifndef RTW_CRYTO_WRAP_H
++#define RTW_CRYTO_WRAP_H
++
++#include <drv_types.h>
++
++#define TEST_FAIL() 0
++
++#define os_memset _rtw_memset
++#define os_memcpy _rtw_memcpy
++#define os_malloc rtw_malloc
++
++#define le_to_host16 le16_to_cpu
++#define host_to_le16 cpu_to_le16
++
++#define WPA_PUT_LE16 RTW_PUT_LE16
++#define WPA_GET_LE16 RTW_GET_LE16
++#define WPA_PUT_LE32 RTW_PUT_LE32
++#define WPA_GET_LE32 RTW_GET_LE32
++#define WPA_PUT_LE64 RTW_PUT_LE64
++#define WPA_GET_LE64 RTW_GET_LE64
++#define WPA_PUT_BE16 RTW_PUT_BE16
++#define WPA_GET_BE16 RTW_GET_BE16
++#define WPA_PUT_BE32 RTW_PUT_BE32
++#define WPA_GET_BE32 RTW_GET_BE32
++#define WPA_PUT_BE64 RTW_PUT_BE64
++#define WPA_GET_BE64 RTW_GET_BE64
++
++#ifndef MAC2STR
++#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
++#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
++#endif
++
++#define WLAN_FC_PVER		0x0003
++#define WLAN_FC_TODS		0x0100
++#define WLAN_FC_FROMDS		0x0200
++#define WLAN_FC_MOREFRAG	0x0400
++#define WLAN_FC_RETRY		0x0800
++#define WLAN_FC_PWRMGT		0x1000
++#define WLAN_FC_MOREDATA	0x2000
++#define WLAN_FC_ISWEP		0x4000
++#define WLAN_FC_ORDER		0x8000
++
++#define WLAN_FC_TYPE_DATA RTW_IEEE80211_FTYPE_DATA
++#define WLAN_FC_TYPE_MGMT RTW_IEEE80211_FTYPE_MGMT
++
++#define WLAN_FC_STYPE_QOS_DATA RTW_IEEE80211_STYPE_QOS_DATA
++
++enum {
++	_MSG_EXCESSIVE_, _MSG_MSGDUMP_, _MSG_DEBUG_, _MSG_INFO_, _MSG_WARNING_, _MSG_ERROR_
++};
++
++int os_memcmp(const void *s1, const void *s2, size_t n);
++int os_memcmp_const(const void *a, const void *b, size_t len);
++void* os_memdup(const void *src, u32 sz);
++size_t os_strlen(const char *s);
++
++void forced_memzero(void *ptr, size_t len);
++void bin_clear_free(void *bin, size_t len);
++
++void wpa_printf(int level, const char *fmt, ...);
++void wpa_hexdump(int level, const char *title, const void *buf, size_t len);
++void wpa_hexdump_key(int level, const char *title, const void *buf, size_t len);
++
++u32 crc32(const u8 *frame, size_t frame_len);
++#endif /* RTW_CRYTO_WRAP_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/sha256-internal.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/sha256-internal.c
+new file mode 100644
+index 000000000..4d61cb173
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/sha256-internal.c
+@@ -0,0 +1,230 @@
++/*
++ * SHA-256 hash implementation and interface functions
++ * Copyright (c) 2003-2011, Jouni Malinen <j@w1.fi>
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#include "rtw_crypto_wrap.h"
++
++//#include "common.h"
++#include "sha256.h"
++#include "sha256_i.h"
++//#include "crypto.h"
++#include "wlancrypto_wrap.h"
++
++
++/**
++ * sha256_vector - SHA256 hash for data vector
++ * @num_elem: Number of elements in the data vector
++ * @addr: Pointers to the data areas
++ * @len: Lengths of the data blocks
++ * @mac: Buffer for the hash
++ * Returns: 0 on success, -1 of failure
++ */
++int sha256_vector(size_t num_elem, const u8 *addr[], const size_t *len,
++		  u8 *mac)
++{
++	struct sha256_state ctx;
++	size_t i;
++
++	if (TEST_FAIL())
++		return -1;
++
++	sha256_init(&ctx);
++	for (i = 0; i < num_elem; i++)
++		if (sha256_process(&ctx, addr[i], len[i]))
++			return -1;
++	if (sha256_done(&ctx, mac))
++		return -1;
++	return 0;
++}
++
++
++/* ===== start - public domain SHA256 implementation ===== */
++
++/* This is based on SHA256 implementation in LibTomCrypt that was released into
++ * public domain by Tom St Denis. */
++
++/* the K array */
++static const unsigned long K[64] = {
++	0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL,
++	0x59f111f1UL, 0x923f82a4UL, 0xab1c5ed5UL, 0xd807aa98UL, 0x12835b01UL,
++	0x243185beUL, 0x550c7dc3UL, 0x72be5d74UL, 0x80deb1feUL, 0x9bdc06a7UL,
++	0xc19bf174UL, 0xe49b69c1UL, 0xefbe4786UL, 0x0fc19dc6UL, 0x240ca1ccUL,
++	0x2de92c6fUL, 0x4a7484aaUL, 0x5cb0a9dcUL, 0x76f988daUL, 0x983e5152UL,
++	0xa831c66dUL, 0xb00327c8UL, 0xbf597fc7UL, 0xc6e00bf3UL, 0xd5a79147UL,
++	0x06ca6351UL, 0x14292967UL, 0x27b70a85UL, 0x2e1b2138UL, 0x4d2c6dfcUL,
++	0x53380d13UL, 0x650a7354UL, 0x766a0abbUL, 0x81c2c92eUL, 0x92722c85UL,
++	0xa2bfe8a1UL, 0xa81a664bUL, 0xc24b8b70UL, 0xc76c51a3UL, 0xd192e819UL,
++	0xd6990624UL, 0xf40e3585UL, 0x106aa070UL, 0x19a4c116UL, 0x1e376c08UL,
++	0x2748774cUL, 0x34b0bcb5UL, 0x391c0cb3UL, 0x4ed8aa4aUL, 0x5b9cca4fUL,
++	0x682e6ff3UL, 0x748f82eeUL, 0x78a5636fUL, 0x84c87814UL, 0x8cc70208UL,
++	0x90befffaUL, 0xa4506cebUL, 0xbef9a3f7UL, 0xc67178f2UL
++};
++
++
++/* Various logical functions */
++#define RORc(x, y) \
++( ((((unsigned long) (x) & 0xFFFFFFFFUL) >> (unsigned long) ((y) & 31)) | \
++   ((unsigned long) (x) << (unsigned long) (32 - ((y) & 31)))) & 0xFFFFFFFFUL)
++#define Ch(x,y,z)       (z ^ (x & (y ^ z)))
++#define Maj(x,y,z)      (((x | y) & z) | (x & y))
++#define S(x, n)         RORc((x), (n))
++#define R(x, n)         (((x)&0xFFFFFFFFUL)>>(n))
++#define Sigma0(x)       (S(x, 2) ^ S(x, 13) ^ S(x, 22))
++#define Sigma1(x)       (S(x, 6) ^ S(x, 11) ^ S(x, 25))
++#define Gamma0(x)       (S(x, 7) ^ S(x, 18) ^ R(x, 3))
++#define Gamma1(x)       (S(x, 17) ^ S(x, 19) ^ R(x, 10))
++#ifndef MIN
++#define MIN(x, y) (((x) < (y)) ? (x) : (y))
++#endif
++
++/* compress 512-bits */
++static int sha256_compress(struct sha256_state *md, unsigned char *buf)
++{
++	u32 S[8], W[64], t0, t1;
++	u32 t;
++	int i;
++
++	/* copy state into S */
++	for (i = 0; i < 8; i++) {
++		S[i] = md->state[i];
++	}
++
++	/* copy the state into 512-bits into W[0..15] */
++	for (i = 0; i < 16; i++)
++		W[i] = WPA_GET_BE32(buf + (4 * i));
++
++	/* fill W[16..63] */
++	for (i = 16; i < 64; i++) {
++		W[i] = Gamma1(W[i - 2]) + W[i - 7] + Gamma0(W[i - 15]) +
++			W[i - 16];
++	}
++
++	/* Compress */
++#define RND(a,b,c,d,e,f,g,h,i)                          \
++	t0 = h + Sigma1(e) + Ch(e, f, g) + K[i] + W[i];	\
++	t1 = Sigma0(a) + Maj(a, b, c);			\
++	d += t0;					\
++	h  = t0 + t1;
++
++	for (i = 0; i < 64; ++i) {
++		RND(S[0], S[1], S[2], S[3], S[4], S[5], S[6], S[7], i);
++		t = S[7]; S[7] = S[6]; S[6] = S[5]; S[5] = S[4];
++		S[4] = S[3]; S[3] = S[2]; S[2] = S[1]; S[1] = S[0]; S[0] = t;
++	}
++
++	/* feedback */
++	for (i = 0; i < 8; i++) {
++		md->state[i] = md->state[i] + S[i];
++	}
++	return 0;
++}
++
++
++/* Initialize the hash state */
++void sha256_init(struct sha256_state *md)
++{
++	md->curlen = 0;
++	md->length = 0;
++	md->state[0] = 0x6A09E667UL;
++	md->state[1] = 0xBB67AE85UL;
++	md->state[2] = 0x3C6EF372UL;
++	md->state[3] = 0xA54FF53AUL;
++	md->state[4] = 0x510E527FUL;
++	md->state[5] = 0x9B05688CUL;
++	md->state[6] = 0x1F83D9ABUL;
++	md->state[7] = 0x5BE0CD19UL;
++}
++
++/**
++   Process a block of memory though the hash
++   @param md     The hash state
++   @param in     The data to hash
++   @param inlen  The length of the data (octets)
++   @return CRYPT_OK if successful
++*/
++int sha256_process(struct sha256_state *md, const unsigned char *in,
++		   unsigned long inlen)
++{
++	unsigned long n;
++
++	if (md->curlen >= sizeof(md->buf))
++		return -1;
++
++	while (inlen > 0) {
++		if (md->curlen == 0 && inlen >= SHA256_BLOCK_SIZE) {
++			if (sha256_compress(md, (unsigned char *) in) < 0)
++				return -1;
++			md->length += SHA256_BLOCK_SIZE * 8;
++			in += SHA256_BLOCK_SIZE;
++			inlen -= SHA256_BLOCK_SIZE;
++		} else {
++			n = MIN(inlen, (SHA256_BLOCK_SIZE - md->curlen));
++			os_memcpy(md->buf + md->curlen, in, n);
++			md->curlen += n;
++			in += n;
++			inlen -= n;
++			if (md->curlen == SHA256_BLOCK_SIZE) {
++				if (sha256_compress(md, md->buf) < 0)
++					return -1;
++				md->length += 8 * SHA256_BLOCK_SIZE;
++				md->curlen = 0;
++			}
++		}
++	}
++
++	return 0;
++}
++
++
++/**
++   Terminate the hash to get the digest
++   @param md  The hash state
++   @param out [out] The destination of the hash (32 bytes)
++   @return CRYPT_OK if successful
++*/
++int sha256_done(struct sha256_state *md, unsigned char *out)
++{
++	int i;
++
++	if (md->curlen >= sizeof(md->buf))
++		return -1;
++
++	/* increase the length of the message */
++	md->length += md->curlen * 8;
++
++	/* append the '1' bit */
++	md->buf[md->curlen++] = (unsigned char) 0x80;
++
++	/* if the length is currently above 56 bytes we append zeros
++	 * then compress.  Then we can fall back to padding zeros and length
++	 * encoding like normal.
++	 */
++	if (md->curlen > 56) {
++		while (md->curlen < SHA256_BLOCK_SIZE) {
++			md->buf[md->curlen++] = (unsigned char) 0;
++		}
++		sha256_compress(md, md->buf);
++		md->curlen = 0;
++	}
++
++	/* pad up to 56 bytes of zeroes */
++	while (md->curlen < 56) {
++		md->buf[md->curlen++] = (unsigned char) 0;
++	}
++
++	/* store length */
++	WPA_PUT_BE64(md->buf + 56, md->length);
++	sha256_compress(md, md->buf);
++
++	/* copy output */
++	for (i = 0; i < 8; i++)
++		WPA_PUT_BE32(out + (4 * i), md->state[i]);
++
++	return 0;
++}
++
++/* ===== end - public domain SHA256 implementation ===== */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/sha256-prf.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/sha256-prf.c
+new file mode 100644
+index 000000000..642b38ff6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/sha256-prf.c
+@@ -0,0 +1,109 @@
++/*
++ * SHA256-based PRF (IEEE 802.11r)
++ * Copyright (c) 2003-2016, Jouni Malinen <j@w1.fi>
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#include "rtw_crypto_wrap.h"
++
++//#include "common.h"
++#include "sha256.h"
++//#include "crypto.h"
++#include "wlancrypto_wrap.h"
++
++
++/**
++ * sha256_prf - SHA256-based Pseudo-Random Function (IEEE 802.11r, 8.5.1.5.2)
++ * @key: Key for PRF
++ * @key_len: Length of the key in bytes
++ * @label: A unique label for each purpose of the PRF
++ * @data: Extra data to bind into the key
++ * @data_len: Length of the data
++ * @buf: Buffer for the generated pseudo-random key
++ * @buf_len: Number of bytes of key to generate
++ * Returns: 0 on success, -1 on failure
++ *
++ * This function is used to derive new, cryptographically separate keys from a
++ * given key.
++ */
++int sha256_prf(const u8 *key, size_t key_len, const char *label,
++		const u8 *data, size_t data_len, u8 *buf, size_t buf_len)
++{
++	return sha256_prf_bits(key, key_len, label, data, data_len, buf,
++			       buf_len * 8);
++}
++
++
++/**
++ * sha256_prf_bits - IEEE Std 802.11-2012, 11.6.1.7.2 Key derivation function
++ * @key: Key for KDF
++ * @key_len: Length of the key in bytes
++ * @label: A unique label for each purpose of the PRF
++ * @data: Extra data to bind into the key
++ * @data_len: Length of the data
++ * @buf: Buffer for the generated pseudo-random key
++ * @buf_len: Number of bits of key to generate
++ * Returns: 0 on success, -1 on failure
++ *
++ * This function is used to derive new, cryptographically separate keys from a
++ * given key. If the requested buf_len is not divisible by eight, the least
++ * significant 1-7 bits of the last octet in the output are not part of the
++ * requested output.
++ */
++int sha256_prf_bits(const u8 *key, size_t key_len, const char *label,
++		    const u8 *data, size_t data_len, u8 *buf,
++		    size_t buf_len_bits)
++{
++	u16 counter = 1;
++	size_t pos, plen;
++	u8 hash[SHA256_MAC_LEN];
++	const u8 *addr[4];
++	size_t len[4];
++	u8 counter_le[2], length_le[2];
++	size_t buf_len = (buf_len_bits + 7) / 8;
++
++	addr[0] = counter_le;
++	len[0] = 2;
++	addr[1] = (u8 *) label;
++	len[1] = os_strlen(label);
++	addr[2] = data;
++	len[2] = data_len;
++	addr[3] = length_le;
++	len[3] = sizeof(length_le);
++
++	WPA_PUT_LE16(length_le, buf_len_bits);
++	pos = 0;
++	while (pos < buf_len) {
++		plen = buf_len - pos;
++		WPA_PUT_LE16(counter_le, counter);
++		if (plen >= SHA256_MAC_LEN) {
++			if (hmac_sha256_vector(key, key_len, 4, addr, len,
++					       &buf[pos]) < 0)
++				return -1;
++			pos += SHA256_MAC_LEN;
++		} else {
++			if (hmac_sha256_vector(key, key_len, 4, addr, len,
++					       hash) < 0)
++				return -1;
++			os_memcpy(&buf[pos], hash, plen);
++			pos += plen;
++			break;
++		}
++		counter++;
++	}
++
++	/*
++	 * Mask out unused bits in the last octet if it does not use all the
++	 * bits.
++	 */
++	if (buf_len_bits % 8) {
++		u8 mask = 0xff << (8 - buf_len_bits % 8);
++		buf[pos - 1] &= mask;
++	}
++
++	forced_memzero(hash, sizeof(hash));
++
++	return 0;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/sha256.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/sha256.c
+new file mode 100644
+index 000000000..ea5d9e3f2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/sha256.c
+@@ -0,0 +1,104 @@
++/*
++ * SHA-256 hash implementation and interface functions
++ * Copyright (c) 2003-2012, Jouni Malinen <j@w1.fi>
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#include "rtw_crypto_wrap.h"
++
++#include "sha256.h"
++//#include "crypto.h"
++#include "wlancrypto_wrap.h"
++
++
++/**
++ * hmac_sha256_vector - HMAC-SHA256 over data vector (RFC 2104)
++ * @key: Key for HMAC operations
++ * @key_len: Length of the key in bytes
++ * @num_elem: Number of elements in the data vector
++ * @addr: Pointers to the data areas
++ * @len: Lengths of the data blocks
++ * @mac: Buffer for the hash (32 bytes)
++ * Returns: 0 on success, -1 on failure
++ */
++int hmac_sha256_vector(const u8 *key, size_t key_len, size_t num_elem,
++		       const u8 *addr[], const size_t *len, u8 *mac)
++{
++	unsigned char k_pad[64]; /* padding - key XORd with ipad/opad */
++	unsigned char tk[32];
++	const u8 *_addr[6];
++	size_t _len[6], i;
++
++	if (num_elem > 5) {
++		/*
++		 * Fixed limit on the number of fragments to avoid having to
++		 * allocate memory (which could fail).
++		 */
++		return -1;
++	}
++
++        /* if key is longer than 64 bytes reset it to key = SHA256(key) */
++        if (key_len > 64) {
++		if (sha256_vector(1, &key, &key_len, tk) < 0)
++			return -1;
++		key = tk;
++		key_len = 32;
++        }
++
++	/* the HMAC_SHA256 transform looks like:
++	 *
++	 * SHA256(K XOR opad, SHA256(K XOR ipad, text))
++	 *
++	 * where K is an n byte key
++	 * ipad is the byte 0x36 repeated 64 times
++	 * opad is the byte 0x5c repeated 64 times
++	 * and text is the data being protected */
++
++	/* start out by storing key in ipad */
++	os_memset(k_pad, 0, sizeof(k_pad));
++	os_memcpy(k_pad, key, key_len);
++	/* XOR key with ipad values */
++	for (i = 0; i < 64; i++)
++		k_pad[i] ^= 0x36;
++
++	/* perform inner SHA256 */
++	_addr[0] = k_pad;
++	_len[0] = 64;
++	for (i = 0; i < num_elem; i++) {
++		_addr[i + 1] = addr[i];
++		_len[i + 1] = len[i];
++	}
++	if (sha256_vector(1 + num_elem, _addr, _len, mac) < 0)
++		return -1;
++
++	os_memset(k_pad, 0, sizeof(k_pad));
++	os_memcpy(k_pad, key, key_len);
++	/* XOR key with opad values */
++	for (i = 0; i < 64; i++)
++		k_pad[i] ^= 0x5c;
++
++	/* perform outer SHA256 */
++	_addr[0] = k_pad;
++	_len[0] = 64;
++	_addr[1] = mac;
++	_len[1] = SHA256_MAC_LEN;
++	return sha256_vector(2, _addr, _len, mac);
++}
++
++
++/**
++ * hmac_sha256 - HMAC-SHA256 over data buffer (RFC 2104)
++ * @key: Key for HMAC operations
++ * @key_len: Length of the key in bytes
++ * @data: Pointers to the data area
++ * @data_len: Length of the data area
++ * @mac: Buffer for the hash (32 bytes)
++ * Returns: 0 on success, -1 on failure
++ */
++int hmac_sha256(const u8 *key, size_t key_len, const u8 *data,
++		size_t data_len, u8 *mac)
++{
++	return hmac_sha256_vector(key, key_len, 1, &data, &data_len, mac);
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/sha256.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/sha256.h
+new file mode 100644
+index 000000000..5219022ed
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/sha256.h
+@@ -0,0 +1,30 @@
++/*
++ * SHA256 hash implementation and interface functions
++ * Copyright (c) 2003-2016, Jouni Malinen <j@w1.fi>
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#ifndef SHA256_H
++#define SHA256_H
++
++#define SHA256_MAC_LEN 32
++
++int hmac_sha256_vector(const u8 *key, size_t key_len, size_t num_elem,
++		       const u8 *addr[], const size_t *len, u8 *mac);
++int hmac_sha256(const u8 *key, size_t key_len, const u8 *data,
++		size_t data_len, u8 *mac);
++int sha256_prf(const u8 *key, size_t key_len, const char *label,
++	       const u8 *data, size_t data_len, u8 *buf, size_t buf_len);
++int sha256_prf_bits(const u8 *key, size_t key_len, const char *label,
++		    const u8 *data, size_t data_len, u8 *buf,
++		    size_t buf_len_bits);
++void tls_prf_sha256(const u8 *secret, size_t secret_len,
++		    const char *label, const u8 *seed, size_t seed_len,
++		    u8 *out, size_t outlen);
++int hmac_sha256_kdf(const u8 *secret, size_t secret_len,
++		    const char *label, const u8 *seed, size_t seed_len,
++		    u8 *out, size_t outlen);
++
++#endif /* SHA256_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/sha256_i.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/sha256_i.h
+new file mode 100644
+index 000000000..a502d2ba5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/sha256_i.h
+@@ -0,0 +1,25 @@
++/*
++ * SHA-256 internal definitions
++ * Copyright (c) 2003-2011, Jouni Malinen <j@w1.fi>
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#ifndef SHA256_I_H
++#define SHA256_I_H
++
++#define SHA256_BLOCK_SIZE 64
++
++struct sha256_state {
++	u64 length;
++	u32 state[8], curlen;
++	u8 buf[SHA256_BLOCK_SIZE];
++};
++
++void sha256_init(struct sha256_state *md);
++int sha256_process(struct sha256_state *md, const unsigned char *in,
++		   unsigned long inlen);
++int sha256_done(struct sha256_state *md, unsigned char *out);
++
++#endif /* SHA256_I_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/wlancrypto_wrap.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/wlancrypto_wrap.h
+new file mode 100644
+index 000000000..e331d036b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/crypto/wlancrypto_wrap.h
+@@ -0,0 +1,34 @@
++/*
++ * wlantest - IEEE 802.11 protocol monitoring and testing tool
++ * Copyright (c) 2010-2013, Jouni Malinen <j@w1.fi>
++ *
++ * This software may be distributed under the terms of the BSD license.
++ * See README for more details.
++ */
++
++#ifndef WLANCRYPTO_WRAP_H
++#define WLANCRYPTO_WRAP_H
++
++int sha256_vector(size_t num_elem, const u8 *addr[], const size_t *len,
++	u8 *mac);
++
++u8* ccmp_decrypt(const u8 *tk, const struct ieee80211_hdr *hdr,
++	const u8 *data, size_t data_len, size_t *decrypted_len);
++u8* ccmp_encrypt(const u8 *tk, u8 *frame, size_t len, size_t hdrlen, u8 *qos,
++	u8 *pn, int keyid, size_t *encrypted_len);
++u8* ccmp_encrypt_pv1(const u8 *tk, const u8 *a1, const u8 *a2, const u8 *a3,
++	const u8 *frame, size_t len,
++	size_t hdrlen, const u8 *pn, int keyid,
++	size_t *encrypted_len);
++u8* ccmp_256_decrypt(const u8 *tk, const struct ieee80211_hdr *hdr,
++	const u8 *data, size_t data_len, size_t *decrypted_len);
++u8* ccmp_256_encrypt(const u8 *tk, u8 *frame, size_t len, size_t hdrlen,
++	u8 *qos, u8 *pn, int keyid, size_t *encrypted_len);
++
++u8* gcmp_decrypt(const u8 *tk, size_t tk_len, const struct ieee80211_hdr *hdr,
++	const u8 *data, size_t data_len, size_t *decrypted_len);
++u8* gcmp_encrypt(const u8 *tk, size_t tk_len, const u8 *frame, size_t len,
++	size_t hdrlen, const u8 *qos,
++	const u8 *pn, int keyid, size_t *encrypted_len);
++
++#endif /* WLANCRYPTO_WRAP_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/efuse/rtw_efuse.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/efuse/rtw_efuse.c
+new file mode 100644
+index 000000000..b67637fe6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/efuse/rtw_efuse.c
+@@ -0,0 +1,3538 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_EFUSE_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++#include "../hal/efuse/efuse_mask.h"
++
++/*------------------------Define local variable------------------------------*/
++u8	fakeEfuseBank = {0};
++u32	fakeEfuseUsedBytes = {0};
++u8	fakeEfuseContent[EFUSE_MAX_HW_SIZE] = {0};
++u8	fakeEfuseInitMap[EFUSE_MAX_MAP_LEN] = {0};
++u8	fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN] = {0};
++
++u32	BTEfuseUsedBytes = {0};
++u8	BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
++u8	BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN] = {0};
++u8	BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN] = {0};
++
++u32	fakeBTEfuseUsedBytes = {0};
++u8	fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
++u8	fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN] = {0};
++u8	fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN] = {0};
++
++u8	maskfileBuffer[64];
++u8	btmaskfileBuffer[64];
++
++/*------------------------Define local variable------------------------------*/
++BOOLEAN rtw_file_efuse_IsMasked(PADAPTER pAdapter, u16 Offset, u8 *maskbuf)
++{
++	int r = Offset / 16;
++	int c = (Offset % 16) / 2;
++	int result = 0;
++
++	if (pAdapter->registrypriv.boffefusemask)
++		return FALSE;
++
++	if (c < 4) /* Upper double word */
++		result = (maskbuf[r] & (0x10 << c));
++	else
++		result = (maskbuf[r] & (0x01 << (c - 4)));
++
++	return (result > 0) ? 0 : 1;
++}
++BOOLEAN efuse_IsBT_Masked(PADAPTER pAdapter, u16 Offset)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
++
++	if (pAdapter->registrypriv.boffefusemask)
++		return FALSE;
++
++#ifdef CONFIG_BT_EFUSE_MASK
++#ifdef CONFIG_USB_HCI
++	if (IS_HARDWARE_TYPE_8822C(pAdapter))
++		return (IS_BT_MASKED(8822C, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++#ifdef CONFIG_PCI_HCI
++	if (IS_HARDWARE_TYPE_8822C(pAdapter))
++		return (IS_BT_MASKED(8822C, _MPCIE, Offset)) ? TRUE : FALSE;
++#endif
++#ifdef CONFIG_SDIO_HCI
++	if (IS_HARDWARE_TYPE_8822C(pAdapter))
++		return (IS_BT_MASKED(8822C, _MSDIO, Offset)) ? TRUE : FALSE;
++#endif
++#endif /* CONFIG_BT_EFUSE_MASK */
++	return FALSE;
++}
++
++void rtw_bt_efuse_mask_array(PADAPTER pAdapter, u8 *pArray)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
++
++#ifdef CONFIG_BT_EFUSE_MASK
++#ifdef CONFIG_USB_HCI
++if (IS_HARDWARE_TYPE_8822CU(pAdapter))
++		GET_MASK_ARRAY(8822C, _MUSB, pArray);
++#endif
++#ifdef CONFIG_PCI_HCI
++	if (IS_HARDWARE_TYPE_8822CE(pAdapter))
++		GET_MASK_ARRAY(8822C, _MPCIE, pArray);
++#endif
++#ifdef CONFIG_SDIO_HCI
++	if (IS_HARDWARE_TYPE_8822CS(pAdapter))
++		GET_MASK_ARRAY(8822C, _MSDIO, pArray);
++#endif
++#endif /* CONFIG_BT_EFUSE_MASK */
++
++}
++
++u16 rtw_get_bt_efuse_mask_arraylen(PADAPTER pAdapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++
++#ifdef CONFIG_BT_EFUSE_MASK
++#ifdef CONFIG_USB_HCI
++	if (IS_HARDWARE_TYPE_8822CU(pAdapter))
++		return GET_BT_MASK_ARRAY_LEN(8822C, _MUSB);
++#endif
++#ifdef CONFIG_PCI_HCI
++	if (IS_HARDWARE_TYPE_8822CE(pAdapter))
++		return GET_BT_MASK_ARRAY_LEN(8822C, _MPCIE);
++#endif
++#ifdef CONFIG_SDIO_HCI
++	if (IS_HARDWARE_TYPE_8822CS(pAdapter))
++		return GET_BT_MASK_ARRAY_LEN(8822C, _MSDIO);
++#endif
++#endif /* CONFIG_BT_EFUSE_MASK */
++
++	return 0;
++}
++
++BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset)
++{
++
++	if (pAdapter->registrypriv.boffefusemask)
++		return FALSE;
++
++#ifdef CONFIG_USB_HCI
++#if defined(CONFIG_RTL8188E)
++	if (IS_HARDWARE_TYPE_8188E(pAdapter))
++		return (IS_MASKED(8188E, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8812A)
++	if (IS_HARDWARE_TYPE_8812(pAdapter))
++		return (IS_MASKED(8812A, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8821A)
++#if 0
++	if (IS_HARDWARE_TYPE_8811AU(pAdapter))
++		return (IS_MASKED(8811A, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++	if (IS_HARDWARE_TYPE_8821(pAdapter))
++		return (IS_MASKED(8821A, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8192E)
++	if (IS_HARDWARE_TYPE_8192E(pAdapter))
++		return (IS_MASKED(8192E, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8723B)
++	if (IS_HARDWARE_TYPE_8723B(pAdapter))
++		return (IS_MASKED(8723B, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8703B)
++	if (IS_HARDWARE_TYPE_8703B(pAdapter))
++		return (IS_MASKED(8703B, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8814A)
++	if (IS_HARDWARE_TYPE_8814A(pAdapter))
++		return (IS_MASKED(8814A, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8188F)
++	if (IS_HARDWARE_TYPE_8188F(pAdapter))
++		return (IS_MASKED(8188F, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8188GTV)
++	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
++		return (IS_MASKED(8188GTV, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8822B)
++	if (IS_HARDWARE_TYPE_8822B(pAdapter))
++		return (IS_MASKED(8822B, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8723D)
++	if (IS_HARDWARE_TYPE_8723D(pAdapter))
++		return (IS_MASKED(8723D, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8710B)
++	if (IS_HARDWARE_TYPE_8710B(pAdapter))
++		return (IS_MASKED(8710B, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8821C)
++	if (IS_HARDWARE_TYPE_8821CU(pAdapter))
++		return (IS_MASKED(8821C, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++
++#if defined(CONFIG_RTL8192F)
++	if (IS_HARDWARE_TYPE_8192FU(pAdapter))
++		return (IS_MASKED(8192F, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8822C)
++	if (IS_HARDWARE_TYPE_8822C(pAdapter))
++		return (IS_MASKED(8822C, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8814B)
++	if (IS_HARDWARE_TYPE_8814B(pAdapter))
++		return (IS_MASKED(8814B, _MUSB, Offset)) ? TRUE : FALSE;
++#endif
++#endif /*CONFIG_USB_HCI*/
++
++#ifdef CONFIG_PCI_HCI
++#if defined(CONFIG_RTL8188E)
++	if (IS_HARDWARE_TYPE_8188E(pAdapter))
++		return (IS_MASKED(8188E, _MPCIE, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8192E)
++	if (IS_HARDWARE_TYPE_8192E(pAdapter))
++		return (IS_MASKED(8192E, _MPCIE, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8812A)
++	if (IS_HARDWARE_TYPE_8812(pAdapter))
++		return (IS_MASKED(8812A, _MPCIE, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8821A)
++	if (IS_HARDWARE_TYPE_8821(pAdapter))
++		return (IS_MASKED(8821A, _MPCIE, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8723B)
++	if (IS_HARDWARE_TYPE_8723B(pAdapter))
++		return (IS_MASKED(8723B, _MPCIE, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8814A)
++	if (IS_HARDWARE_TYPE_8814A(pAdapter))
++		return (IS_MASKED(8814A, _MPCIE, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8822B)
++	if (IS_HARDWARE_TYPE_8822B(pAdapter))
++		return (IS_MASKED(8822B, _MPCIE, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8821C)
++	if (IS_HARDWARE_TYPE_8821CE(pAdapter))
++		return (IS_MASKED(8821C, _MPCIE, Offset)) ? TRUE : FALSE;
++#endif
++
++#if defined(CONFIG_RTL8192F)
++	if (IS_HARDWARE_TYPE_8192FE(pAdapter))
++		return (IS_MASKED(8192F, _MPCIE, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8822C)
++	if (IS_HARDWARE_TYPE_8822C(pAdapter))
++		return (IS_MASKED(8822C, _MPCIE, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8814B)
++	if (IS_HARDWARE_TYPE_8814B(pAdapter))
++		return (IS_MASKED(8814B, _MPCIE, Offset)) ? TRUE : FALSE;
++#endif
++#endif /*CONFIG_PCI_HCI*/
++
++#ifdef CONFIG_SDIO_HCI
++#ifdef CONFIG_RTL8188E_SDIO
++	if (IS_HARDWARE_TYPE_8188E(pAdapter))
++		return (IS_MASKED(8188E, _MSDIO, Offset)) ? TRUE : FALSE;
++#endif
++#ifdef CONFIG_RTL8723B
++	if (IS_HARDWARE_TYPE_8723BS(pAdapter))
++		return (IS_MASKED(8723B, _MSDIO, Offset)) ? TRUE : FALSE;
++#endif
++#ifdef CONFIG_RTL8188F
++	if (IS_HARDWARE_TYPE_8188F(pAdapter))
++		return (IS_MASKED(8188F, _MSDIO, Offset)) ? TRUE : FALSE;
++#endif
++#ifdef CONFIG_RTL8188GTV
++	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
++		return (IS_MASKED(8188GTV, _MSDIO, Offset)) ? TRUE : FALSE;
++#endif
++#ifdef CONFIG_RTL8192E
++	if (IS_HARDWARE_TYPE_8192ES(pAdapter))
++		return (IS_MASKED(8192E, _MSDIO, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8821A)
++	if (IS_HARDWARE_TYPE_8821S(pAdapter))
++		return (IS_MASKED(8821A, _MSDIO, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8821C)
++	if (IS_HARDWARE_TYPE_8821CS(pAdapter))
++		return (IS_MASKED(8821C, _MSDIO, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8822B)
++	if (IS_HARDWARE_TYPE_8822B(pAdapter))
++		return (IS_MASKED(8822B, _MSDIO, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8192F)
++	if (IS_HARDWARE_TYPE_8192FS(pAdapter))
++		return (IS_MASKED(8192F, _MSDIO, Offset)) ? TRUE : FALSE;
++#endif
++#if defined(CONFIG_RTL8822C)
++	if (IS_HARDWARE_TYPE_8822C(pAdapter))
++		return (IS_MASKED(8822C, _MSDIO, Offset)) ? TRUE : FALSE;
++#endif
++#endif /*CONFIG_SDIO_HCI*/
++
++	return FALSE;
++}
++
++void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray)
++{
++
++#ifdef CONFIG_USB_HCI
++#if defined(CONFIG_RTL8188E)
++	if (IS_HARDWARE_TYPE_8188E(pAdapter))
++		GET_MASK_ARRAY(8188E, _MUSB, pArray);
++#endif
++#if defined(CONFIG_RTL8812A)
++	if (IS_HARDWARE_TYPE_8812(pAdapter))
++		GET_MASK_ARRAY(8812A, _MUSB, pArray);
++#endif
++#if defined(CONFIG_RTL8821A)
++	if (IS_HARDWARE_TYPE_8821(pAdapter))
++		GET_MASK_ARRAY(8821A, _MUSB, pArray);
++#endif
++#if defined(CONFIG_RTL8192E)
++	if (IS_HARDWARE_TYPE_8192E(pAdapter))
++		GET_MASK_ARRAY(8192E, _MUSB, pArray);
++#endif
++#if defined(CONFIG_RTL8723B)
++	if (IS_HARDWARE_TYPE_8723B(pAdapter))
++		GET_MASK_ARRAY(8723B, _MUSB, pArray);
++#endif
++#if defined(CONFIG_RTL8703B)
++	if (IS_HARDWARE_TYPE_8703B(pAdapter))
++		GET_MASK_ARRAY(8703B, _MUSB, pArray);
++#endif
++#if defined(CONFIG_RTL8188F)
++	if (IS_HARDWARE_TYPE_8188F(pAdapter))
++		GET_MASK_ARRAY(8188F, _MUSB, pArray);
++#endif
++#if defined(CONFIG_RTL8188GTV)
++	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
++		GET_MASK_ARRAY(8188GTV, _MUSB, pArray);
++#endif
++#if defined(CONFIG_RTL8814A)
++	if (IS_HARDWARE_TYPE_8814A(pAdapter))
++		GET_MASK_ARRAY(8814A, _MUSB, pArray);
++#endif
++#if defined(CONFIG_RTL8822B)
++	if (IS_HARDWARE_TYPE_8822B(pAdapter))
++		GET_MASK_ARRAY(8822B, _MUSB, pArray);
++#endif
++#if defined(CONFIG_RTL8821C)
++	if (IS_HARDWARE_TYPE_8821CU(pAdapter))
++		GET_MASK_ARRAY(8821C, _MUSB, pArray);
++#endif
++#if defined(CONFIG_RTL8192F)
++	if (IS_HARDWARE_TYPE_8192FU(pAdapter))
++		GET_MASK_ARRAY(8192F, _MUSB, pArray);
++#endif
++#if defined(CONFIG_RTL8822C)
++	if (IS_HARDWARE_TYPE_8822C(pAdapter))
++		GET_MASK_ARRAY(8822C, _MUSB, pArray);
++#endif
++#if defined(CONFIG_RTL8814B)
++	if (IS_HARDWARE_TYPE_8814B(pAdapter))
++		GET_MASK_ARRAY(8814B, _MUSB, pArray);
++#endif
++#endif /*CONFIG_USB_HCI*/
++
++#ifdef CONFIG_PCI_HCI
++#if defined(CONFIG_RTL8188E)
++	if (IS_HARDWARE_TYPE_8188E(pAdapter))
++		GET_MASK_ARRAY(8188E, _MPCIE, pArray);
++#endif
++#if defined(CONFIG_RTL8192E)
++	if (IS_HARDWARE_TYPE_8192E(pAdapter))
++		GET_MASK_ARRAY(8192E, _MPCIE, pArray);
++#endif
++#if defined(CONFIG_RTL8812A)
++	if (IS_HARDWARE_TYPE_8812(pAdapter))
++		GET_MASK_ARRAY(8812A, _MPCIE, pArray);
++#endif
++#if defined(CONFIG_RTL8821A)
++	if (IS_HARDWARE_TYPE_8821(pAdapter))
++		GET_MASK_ARRAY(8821A, _MPCIE, pArray);
++#endif
++#if defined(CONFIG_RTL8723B)
++	if (IS_HARDWARE_TYPE_8723B(pAdapter))
++		GET_MASK_ARRAY(8723B, _MPCIE, pArray);
++#endif
++#if defined(CONFIG_RTL8814A)
++	if (IS_HARDWARE_TYPE_8814A(pAdapter))
++		GET_MASK_ARRAY(8814A, _MPCIE, pArray);
++#endif
++#if defined(CONFIG_RTL8822B)
++	if (IS_HARDWARE_TYPE_8822B(pAdapter))
++		GET_MASK_ARRAY(8822B, _MPCIE, pArray);
++#endif
++#if defined(CONFIG_RTL8821C)
++	if (IS_HARDWARE_TYPE_8821CE(pAdapter))
++		GET_MASK_ARRAY(8821C, _MPCIE, pArray);
++#endif
++#if defined(CONFIG_RTL8192F)
++	if (IS_HARDWARE_TYPE_8192FE(pAdapter))
++		GET_MASK_ARRAY(8192F, _MPCIE, pArray);
++#endif
++#if defined(CONFIG_RTL8822C)
++	if (IS_HARDWARE_TYPE_8822C(pAdapter))
++		GET_MASK_ARRAY(8822C, _MPCIE, pArray);
++#endif
++#if defined(CONFIG_RTL8814B)
++	if (IS_HARDWARE_TYPE_8814B(pAdapter))
++		GET_MASK_ARRAY(8814B, _MPCIE, pArray);
++#endif
++#endif /*CONFIG_PCI_HCI*/
++
++#ifdef CONFIG_SDIO_HCI
++#if defined(CONFIG_RTL8188E)
++	if (IS_HARDWARE_TYPE_8188E(pAdapter))
++		GET_MASK_ARRAY(8188E, _MSDIO, pArray);
++#endif
++#if defined(CONFIG_RTL8723B)
++	if (IS_HARDWARE_TYPE_8723BS(pAdapter))
++		GET_MASK_ARRAY(8723B, _MSDIO, pArray);
++#endif
++#if defined(CONFIG_RTL8188F)
++	if (IS_HARDWARE_TYPE_8188F(pAdapter))
++		GET_MASK_ARRAY(8188F, _MSDIO, pArray);
++#endif
++#if defined(CONFIG_RTL8188GTV)
++	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
++		GET_MASK_ARRAY(8188GTV, _MSDIO, pArray);
++#endif
++#if defined(CONFIG_RTL8192E)
++	if (IS_HARDWARE_TYPE_8192ES(pAdapter))
++		GET_MASK_ARRAY(8192E, _MSDIO, pArray);
++#endif
++#if defined(CONFIG_RTL8821A)
++	if (IS_HARDWARE_TYPE_8821S(pAdapter))
++		GET_MASK_ARRAY(8821A, _MSDIO, pArray);
++#endif
++#if defined(CONFIG_RTL8821C)
++	if (IS_HARDWARE_TYPE_8821CS(pAdapter))
++		GET_MASK_ARRAY(8821C , _MSDIO, pArray);
++#endif
++#if defined(CONFIG_RTL8822B)
++	if (IS_HARDWARE_TYPE_8822B(pAdapter))
++		GET_MASK_ARRAY(8822B , _MSDIO, pArray);
++#endif
++#if defined(CONFIG_RTL8192F)
++	if (IS_HARDWARE_TYPE_8192FS(pAdapter))
++		GET_MASK_ARRAY(8192F, _MSDIO, pArray);
++#endif
++#if defined(CONFIG_RTL8822C)
++	if (IS_HARDWARE_TYPE_8822C(pAdapter))
++		GET_MASK_ARRAY(8822C , _MSDIO, pArray);
++#endif
++#endif /*CONFIG_SDIO_HCI*/
++}
++
++u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter)
++{
++
++#ifdef CONFIG_USB_HCI
++#if defined(CONFIG_RTL8188E)
++	if (IS_HARDWARE_TYPE_8188E(pAdapter))
++		return GET_MASK_ARRAY_LEN(8188E, _MUSB);
++#endif
++#if defined(CONFIG_RTL8812A)
++	if (IS_HARDWARE_TYPE_8812(pAdapter))
++		return GET_MASK_ARRAY_LEN(8812A, _MUSB);
++#endif
++#if defined(CONFIG_RTL8821A)
++	if (IS_HARDWARE_TYPE_8821(pAdapter))
++		return GET_MASK_ARRAY_LEN(8821A, _MUSB);
++#endif
++#if defined(CONFIG_RTL8192E)
++	if (IS_HARDWARE_TYPE_8192E(pAdapter))
++		return GET_MASK_ARRAY_LEN(8192E, _MUSB);
++#endif
++#if defined(CONFIG_RTL8723B)
++	if (IS_HARDWARE_TYPE_8723B(pAdapter))
++		return GET_MASK_ARRAY_LEN(8723B, _MUSB);
++#endif
++#if defined(CONFIG_RTL8703B)
++	if (IS_HARDWARE_TYPE_8703B(pAdapter))
++		return GET_MASK_ARRAY_LEN(8703B, _MUSB);
++#endif
++#if defined(CONFIG_RTL8188F)
++	if (IS_HARDWARE_TYPE_8188F(pAdapter))
++		return GET_MASK_ARRAY_LEN(8188F, _MUSB);
++#endif
++#if defined(CONFIG_RTL8188GTV)
++	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
++		return GET_MASK_ARRAY_LEN(8188GTV, _MUSB);
++#endif
++#if defined(CONFIG_RTL8814A)
++	if (IS_HARDWARE_TYPE_8814A(pAdapter))
++		return GET_MASK_ARRAY_LEN(8814A, _MUSB);
++#endif
++#if defined(CONFIG_RTL8822B)
++	if (IS_HARDWARE_TYPE_8822B(pAdapter))
++		return GET_MASK_ARRAY_LEN(8822B, _MUSB);
++#endif
++#if defined(CONFIG_RTL8821C)
++	if (IS_HARDWARE_TYPE_8821CU(pAdapter))
++		return GET_MASK_ARRAY_LEN(8821C, _MUSB);
++#endif
++#if defined(CONFIG_RTL8192F)
++	if (IS_HARDWARE_TYPE_8192FU(pAdapter))
++		return GET_MASK_ARRAY_LEN(8192F, _MUSB);
++#endif
++#if defined(CONFIG_RTL8822C)
++	if (IS_HARDWARE_TYPE_8822C(pAdapter))
++		return GET_MASK_ARRAY_LEN(8822C, _MUSB);
++#endif
++#if defined(CONFIG_RTL8814B)
++	if (IS_HARDWARE_TYPE_8814B(pAdapter)) {
++		return GET_MASK_ARRAY_LEN(8814B, _MUSB);
++	}
++#endif
++#endif /*CONFIG_USB_HCI*/
++
++#ifdef CONFIG_PCI_HCI
++#if defined(CONFIG_RTL8188E)
++	if (IS_HARDWARE_TYPE_8188E(pAdapter))
++		return GET_MASK_ARRAY_LEN(8188E, _MPCIE);
++#endif
++#if defined(CONFIG_RTL8192E)
++	if (IS_HARDWARE_TYPE_8192E(pAdapter))
++		return GET_MASK_ARRAY_LEN(8192E, _MPCIE);
++#endif
++#if defined(CONFIG_RTL8812A)
++	if (IS_HARDWARE_TYPE_8812(pAdapter))
++		return GET_MASK_ARRAY_LEN(8812A, _MPCIE);
++#endif
++#if defined(CONFIG_RTL8821A)
++	if (IS_HARDWARE_TYPE_8821(pAdapter))
++		return GET_MASK_ARRAY_LEN(8821A, _MPCIE);
++#endif
++#if defined(CONFIG_RTL8723B)
++	if (IS_HARDWARE_TYPE_8723B(pAdapter))
++		return GET_MASK_ARRAY_LEN(8723B, _MPCIE);
++#endif
++#if defined(CONFIG_RTL8814A)
++	if (IS_HARDWARE_TYPE_8814A(pAdapter))
++		return GET_MASK_ARRAY_LEN(8814A, _MPCIE);
++#endif
++#if defined(CONFIG_RTL8822B)
++	if (IS_HARDWARE_TYPE_8822B(pAdapter))
++		return GET_MASK_ARRAY_LEN(8822B, _MPCIE);
++#endif
++#if defined(CONFIG_RTL8821C)
++	if (IS_HARDWARE_TYPE_8821CE(pAdapter))
++		return GET_MASK_ARRAY_LEN(8821C, _MPCIE);
++#endif
++#if defined(CONFIG_RTL8192F)
++	if (IS_HARDWARE_TYPE_8192FE(pAdapter))
++		return GET_MASK_ARRAY_LEN(8192F, _MPCIE);
++#endif
++#if defined(CONFIG_RTL8822C)
++	if (IS_HARDWARE_TYPE_8822C(pAdapter))
++		return GET_MASK_ARRAY_LEN(8822C, _MPCIE);
++#endif
++#if defined(CONFIG_RTL8814B)
++	if (IS_HARDWARE_TYPE_8814B(pAdapter))
++		return GET_MASK_ARRAY_LEN(8814B, _MPCIE);
++#endif
++#endif /*CONFIG_PCI_HCI*/
++
++#ifdef CONFIG_SDIO_HCI
++#if defined(CONFIG_RTL8188E)
++	if (IS_HARDWARE_TYPE_8188E(pAdapter))
++		return GET_MASK_ARRAY_LEN(8188E, _MSDIO);
++#endif
++#if defined(CONFIG_RTL8723B)
++	if (IS_HARDWARE_TYPE_8723BS(pAdapter))
++		return GET_MASK_ARRAY_LEN(8723B, _MSDIO);
++#endif
++#if defined(CONFIG_RTL8188F)
++	if (IS_HARDWARE_TYPE_8188F(pAdapter))
++		return GET_MASK_ARRAY_LEN(8188F, _MSDIO);
++#endif
++#if defined(CONFIG_RTL8188GTV)
++	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
++		return GET_MASK_ARRAY_LEN(8188GTV, _MSDIO);
++#endif
++#if defined(CONFIG_RTL8192E)
++	if (IS_HARDWARE_TYPE_8192ES(pAdapter))
++		return GET_MASK_ARRAY_LEN(8192E, _MSDIO);
++#endif
++#if defined(CONFIG_RTL8821A)
++	if (IS_HARDWARE_TYPE_8821S(pAdapter))
++		return GET_MASK_ARRAY_LEN(8821A, _MSDIO);
++#endif
++#if defined(CONFIG_RTL8821C)
++	if (IS_HARDWARE_TYPE_8821CS(pAdapter))
++		return GET_MASK_ARRAY_LEN(8821C, _MSDIO);
++#endif
++#if defined(CONFIG_RTL8822B)
++	if (IS_HARDWARE_TYPE_8822B(pAdapter))
++		return GET_MASK_ARRAY_LEN(8822B, _MSDIO);
++#endif
++#if defined(CONFIG_RTL8192F)
++	if (IS_HARDWARE_TYPE_8192FS(pAdapter))
++		return GET_MASK_ARRAY_LEN(8192F, _MSDIO);
++#endif
++#if defined(CONFIG_RTL8822C)
++	if (IS_HARDWARE_TYPE_8822C(pAdapter))
++		return GET_MASK_ARRAY_LEN(8822C, _MSDIO);
++#endif
++#endif/*CONFIG_SDIO_HCI*/
++	return 0;
++}
++
++static void rtw_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
++{
++	u16 i = 0;
++
++	if (padapter->registrypriv.boffefusemask == 0) {
++		for (i = 0; i < cnts; i++) {
++			if (padapter->registrypriv.bFileMaskEfuse == _TRUE) {
++					if (rtw_file_efuse_IsMasked(padapter, addr + i, maskfileBuffer)) /*use file efuse mask.*/
++						data[i] = 0xff;
++					else
++						RTW_DBG("data[%x] = %x\n", i, data[i]);
++			} else {
++					if (efuse_IsMasked(padapter, addr + i))
++						data[i] = 0xff;
++					else
++						RTW_DBG("data[%x] = %x\n", i, data[i]);
++			}
++		}
++	}
++}
++
++u8 rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
++{
++	u8	ret = _SUCCESS;
++	u16	mapLen = 0;
++
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);
++
++	ret = rtw_efuse_map_read(padapter, addr, cnts , data);
++
++	rtw_mask_map_read(padapter, addr, cnts , data);
++
++	return ret;
++
++}
++
++/* ***********************************************************
++ *				Efuse related code
++ * *********************************************************** */
++static u8 hal_EfuseSwitchToBank(
++	PADAPTER	padapter,
++	u8			bank,
++	u8			bPseudoTest)
++{
++	u8 bRet = _FALSE;
++	u32 value32 = 0;
++#ifdef HAL_EFUSE_MEMORY
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++	PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
++#endif
++
++
++	RTW_INFO("%s: Efuse switch bank to %d\n", __FUNCTION__, bank);
++	if (bPseudoTest) {
++#ifdef HAL_EFUSE_MEMORY
++		pEfuseHal->fakeEfuseBank = bank;
++#else
++		fakeEfuseBank = bank;
++#endif
++		bRet = _TRUE;
++	} else {
++		value32 = rtw_read32(padapter, 0x34);
++		bRet = _TRUE;
++		switch (bank) {
++		case 0:
++			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
++			break;
++		case 1:
++			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0);
++			break;
++		case 2:
++			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1);
++			break;
++		case 3:
++			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2);
++			break;
++		default:
++			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
++			bRet = _FALSE;
++			break;
++		}
++		rtw_write32(padapter, 0x34, value32);
++	}
++
++	return bRet;
++}
++
++void rtw_efuse_analyze(PADAPTER	padapter, u8 Type, u8 Fake)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	PEFUSE_HAL		pEfuseHal = &(pHalData->EfuseHal);
++	u16	eFuse_Addr = 0;
++	u8 offset, wden;
++	u16	 i, j;
++	u8	efuseHeader = 0, efuseExtHdr = 0, efuseData[EFUSE_MAX_WORD_UNIT*2] = {0}, dataCnt = 0;
++	u16	efuseHeader2Byte = 0;
++	u8	*eFuseWord = NULL;// [EFUSE_MAX_SECTION_NUM][EFUSE_MAX_WORD_UNIT];
++	u8	offset_2_0 = 0;
++	u8	pgSectionCnt = 0;
++	u8	wd_cnt = 0;
++	u8	max_section = 64;
++	u16	mapLen = 0, maprawlen = 0;
++	boolean	bExtHeader = _FALSE;
++	u8	efuseType = EFUSE_WIFI;
++	boolean	bPseudoTest = _FALSE;
++	u8	bank = 0, startBank = 0, endBank = 1-1;
++	boolean	bCheckNextBank = FALSE;
++	u8	protectBytesBank = 0;
++	u16	efuse_max = 0;
++	u8	ParseEfuseExtHdr, ParseEfuseHeader, ParseOffset, ParseWDEN, ParseOffset2_0;
++
++	eFuseWord = rtw_zmalloc(EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2));
++
++	if (eFuseWord == NULL) {
++		RTW_INFO("%s:rtw_zmalloc eFuseWord = NULL !!\n", __func__);
++		return;
++	}
++
++	RTW_INFO("\n");
++	if (Type == 0) {
++		if (Fake == 0) {
++			RTW_INFO("\n\tEFUSE_Analyze Wifi Content\n");
++			efuseType = EFUSE_WIFI;
++			bPseudoTest = FALSE;
++			startBank = 0;
++			endBank = 0;
++		} else {
++			RTW_INFO("\n\tEFUSE_Analyze Wifi Pseudo Content\n");
++			efuseType = EFUSE_WIFI;
++			bPseudoTest = TRUE;
++			startBank = 0;
++			endBank = 0;
++		}
++	} else {
++		if (Fake == 0) {
++			RTW_INFO("\n\tEFUSE_Analyze BT Content\n");
++			efuseType = EFUSE_BT;
++			bPseudoTest = FALSE;
++			startBank = 1;
++			endBank = EFUSE_MAX_BANK - 1;
++		} else {
++			RTW_INFO("\n\tEFUSE_Analyze BT Pseudo Content\n");
++			efuseType = EFUSE_BT;
++			bPseudoTest = TRUE;
++			startBank = 1;
++			endBank = EFUSE_MAX_BANK - 1;
++			if (IS_HARDWARE_TYPE_8821(padapter))
++				endBank = 3 - 1;/*EFUSE_MAX_BANK_8821A - 1;*/
++		}
++	}
++
++	RTW_INFO("\n\r 1Byte header, [7:4]=offset, [3:0]=word enable\n");
++	RTW_INFO("\n\r 2Byte header, header[7:5]=offset[2:0], header[4:0]=0x0F\n");
++	RTW_INFO("\n\r 2Byte header, extHeader[7:4]=offset[6:3], extHeader[3:0]=word enable\n");
++
++	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, bPseudoTest);
++	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_MAX_SECTION, (void *)&max_section, bPseudoTest);
++	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_PROTECT_BYTES_BANK, (void *)&protectBytesBank, bPseudoTest);
++	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_CONTENT_LEN_BANK, (void *)&efuse_max, bPseudoTest);
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (void *)&maprawlen, _FALSE);
++
++	_rtw_memset(eFuseWord, 0xff, EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2));
++	_rtw_memset(pEfuseHal->fakeEfuseInitMap, 0xff, EFUSE_MAX_MAP_LEN);
++
++	if (IS_HARDWARE_TYPE_8821(padapter))
++		endBank = 3 - 1;/*EFUSE_MAX_BANK_8821A - 1;*/
++
++	for (bank = startBank; bank <= endBank; bank++) {
++		if (!hal_EfuseSwitchToBank(padapter, bank, bPseudoTest)) {
++			RTW_INFO("EFUSE_SwitchToBank() Fail!!\n");
++			goto out_free_buffer;
++		}
++
++		eFuse_Addr = bank * EFUSE_MAX_BANK_SIZE;
++
++		efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
++
++		if (efuseHeader == 0xFF && bank == startBank && Fake != TRUE) {
++			RTW_INFO("Non-PGed Efuse\n");
++			goto out_free_buffer;
++		}
++		RTW_INFO("EFUSE_REAL_CONTENT_LEN = %d\n", maprawlen);
++
++		while ((efuseHeader != 0xFF) && ((efuseType == EFUSE_WIFI && (eFuse_Addr < maprawlen)) || (efuseType == EFUSE_BT && (eFuse_Addr < (endBank + 1) * EFUSE_MAX_BANK_SIZE)))) {
++
++			RTW_INFO("Analyzing: Offset: 0x%X\n", eFuse_Addr);
++
++			/* Check PG header for section num.*/
++			if (EXT_HEADER(efuseHeader)) {
++				bExtHeader = TRUE;
++				offset_2_0 = GET_HDR_OFFSET_2_0(efuseHeader);
++				efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
++
++				if (efuseExtHdr != 0xff) {
++					if (ALL_WORDS_DISABLED(efuseExtHdr)) {
++						/* Read next pg header*/
++						efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
++						continue;
++					} else {
++						offset = ((efuseExtHdr & 0xF0) >> 1) | offset_2_0;
++						wden = (efuseExtHdr & 0x0F);
++						efuseHeader2Byte = (efuseExtHdr<<8)|efuseHeader;
++						RTW_INFO("Find efuseHeader2Byte = 0x%04X, offset=%d, wden=0x%x\n",
++										efuseHeader2Byte, offset, wden);
++					}
++				} else {
++					RTW_INFO("Error, efuse[%d]=0xff, efuseExtHdr=0xff\n", eFuse_Addr-1);
++					break;
++				}
++			} else {
++				offset = ((efuseHeader >> 4) & 0x0f);
++				wden = (efuseHeader & 0x0f);
++			}
++
++			_rtw_memset(efuseData, '\0', EFUSE_MAX_WORD_UNIT * 2);
++			dataCnt = 0;
++
++			if (offset < max_section) {
++				for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
++					/* Check word enable condition in the section	*/
++					if (!(wden & (0x01<<i))) {
++						if (!((efuseType == EFUSE_WIFI && (eFuse_Addr + 2 < maprawlen)) ||
++								(efuseType == EFUSE_BT && (eFuse_Addr + 2 < (endBank + 1) * EFUSE_MAX_BANK_SIZE)))) {
++							RTW_INFO("eFuse_Addr exceeds, break\n");
++							break;
++						}
++						efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData[dataCnt++], bPseudoTest);
++						eFuseWord[(offset * 8) + (i * 2)] = (efuseData[dataCnt - 1]);
++						efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData[dataCnt++], bPseudoTest);
++						eFuseWord[(offset * 8) + (i * 2 + 1)] = (efuseData[dataCnt - 1]);
++					}
++				}
++			}
++
++			if (bExtHeader) {
++				RTW_INFO("Efuse PG Section (%d) = ", pgSectionCnt);
++				RTW_INFO("[ %04X ], [", efuseHeader2Byte);
++
++			} else {
++				RTW_INFO("Efuse PG Section (%d) = ", pgSectionCnt);
++				RTW_INFO("[ %02X ], [", efuseHeader);
++			}
++
++			for (j = 0; j < dataCnt; j++)
++				RTW_INFO(" %02X ", efuseData[j]);
++
++			RTW_INFO("]\n");
++
++
++			if (bExtHeader) {
++				ParseEfuseExtHdr = (efuseHeader2Byte & 0xff00) >> 8;
++				ParseEfuseHeader = (efuseHeader2Byte & 0xff);
++				ParseOffset2_0 = GET_HDR_OFFSET_2_0(ParseEfuseHeader);
++				ParseOffset = ((ParseEfuseExtHdr & 0xF0) >> 1) | ParseOffset2_0;
++				ParseWDEN = (ParseEfuseExtHdr & 0x0F);
++				RTW_INFO("Header=0x%x, ExtHeader=0x%x, ", ParseEfuseHeader, ParseEfuseExtHdr);
++			} else {
++				ParseEfuseHeader = efuseHeader;
++				ParseOffset = ((ParseEfuseHeader >> 4) & 0x0f);
++				ParseWDEN = (ParseEfuseHeader & 0x0f);
++				RTW_INFO("Header=0x%x, ", ParseEfuseHeader);
++			}
++			RTW_INFO("offset=0x%x(%d), word enable=0x%x\n", ParseOffset, ParseOffset, ParseWDEN);
++
++			wd_cnt = 0;
++			for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
++				if (!(wden & (0x01 << i))) {
++					RTW_INFO("Map[ %02X ] = %02X %02X\n", ((offset * EFUSE_MAX_WORD_UNIT * 2) + (i * 2)), efuseData[wd_cnt * 2 + 0], efuseData[wd_cnt * 2 + 1]);
++					wd_cnt++;
++				}
++			}
++
++			pgSectionCnt++;
++			bExtHeader = FALSE;
++			efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
++			if (efuseHeader == 0xFF) {
++				if ((eFuse_Addr + protectBytesBank) >= efuse_max)
++					bCheckNextBank = TRUE;
++				else
++					bCheckNextBank = FALSE;
++			}
++		}
++		if (!bCheckNextBank) {
++			RTW_INFO("Not need to check next bank, eFuse_Addr=%d, protectBytesBank=%d, efuse_max=%d\n",
++				eFuse_Addr, protectBytesBank, efuse_max);
++			break;
++		}
++	}
++	/* switch bank back to 0 for BT/wifi later use*/
++	hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
++
++	/* 3. Collect 16 sections and 4 word unit into Efuse map.*/
++	for (i = 0; i < max_section; i++) {
++		for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) {
++			pEfuseHal->fakeEfuseInitMap[(i*8)+(j*2)] = (eFuseWord[(i*8)+(j*2)]);
++			pEfuseHal->fakeEfuseInitMap[(i*8)+((j*2)+1)] =  (eFuseWord[(i*8)+((j*2)+1)]);
++		}
++	}
++
++	RTW_INFO("\n\tEFUSE Analyze Map\n");
++	i = 0;
++	j = 0;
++
++	for (i = 0; i < mapLen; i++) {
++		if (i % 16 == 0)
++			RTW_PRINT_SEL(RTW_DBGDUMP, "0x%03x: ", i);
++			_RTW_PRINT_SEL(RTW_DBGDUMP, "%02X%s"
++				, pEfuseHal->fakeEfuseInitMap[i]
++				, ((i + 1) % 16 == 0) ? "\n" : (((i + 1) % 8 == 0) ? "	  " : " ")
++			);
++		}
++	_RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
++
++out_free_buffer:
++	if (eFuseWord)
++		rtw_mfree((u8 *)eFuseWord, EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2));
++}
++
++void efuse_PreUpdateAction(
++	PADAPTER	pAdapter,
++	u32			*BackupRegs)
++{
++	if (IS_HARDWARE_TYPE_8812AU(pAdapter) || IS_HARDWARE_TYPE_8822BU(pAdapter)) {
++		/* <20131115, Kordan> Turn off Rx to prevent from being busy when writing the EFUSE. (Asked by Chunchu.)*/
++		BackupRegs[0] = phy_query_mac_reg(pAdapter, REG_RCR, bMaskDWord);
++		BackupRegs[1] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord);
++		BackupRegs[2] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord);
++#ifdef CONFIG_RTL8812A
++		BackupRegs[3] = phy_query_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord);
++#endif
++		PlatformEFIOWrite4Byte(pAdapter, REG_RCR, 0x1);
++		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0, 0);
++		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+1, 0);
++		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+2, 0);
++		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+3, 0);
++		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+4, 0);
++		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+5, 0);
++#ifdef CONFIG_RTL8812A
++		/* <20140410, Kordan> 0x11 = 0x4E, lower down LX_SPS0 voltage. (Asked by Chunchu)*/
++		phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskByte1, 0x4E);
++#endif
++		RTW_INFO(" %s , done\n", __func__);
++
++		}
++}
++
++
++void efuse_PostUpdateAction(
++	PADAPTER	pAdapter,
++	u32			*BackupRegs)
++{
++	if (IS_HARDWARE_TYPE_8812AU(pAdapter) || IS_HARDWARE_TYPE_8822BU(pAdapter)) {
++		/* <20131115, Kordan> Turn on Rx and restore the registers. (Asked by Chunchu.)*/
++		phy_set_mac_reg(pAdapter, REG_RCR, bMaskDWord, BackupRegs[0]);
++		phy_set_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord, BackupRegs[1]);
++		phy_set_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord, BackupRegs[2]);
++#ifdef CONFIG_RTL8812A
++		phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord, BackupRegs[3]);
++#endif
++	RTW_INFO(" %s , done\n", __func__);
++	}
++}
++
++
++#ifdef RTW_HALMAC
++#include "../../hal/hal_halmac.h"
++
++void Efuse_PowerSwitch(PADAPTER adapter, u8 write, u8 pwrstate)
++{
++}
++
++void BTEfuse_PowerSwitch(PADAPTER adapter, u8 write, u8 pwrstate)
++{
++}
++
++u8 efuse_GetCurrentSize(PADAPTER adapter, u16 *size)
++{
++	*size = 0;
++
++	return _FAIL;
++}
++
++u16 efuse_GetMaxSize(PADAPTER adapter)
++{
++	struct dvobj_priv *d;
++	u32 size = 0;
++	int err;
++
++	d = adapter_to_dvobj(adapter);
++	err = rtw_halmac_get_physical_efuse_size(d, &size);
++	if (err)
++		return 0;
++
++	return size;
++}
++
++u16 efuse_GetavailableSize(PADAPTER adapter)
++{
++	struct dvobj_priv *d;
++	u32 size = 0;
++	int err;
++
++	d = adapter_to_dvobj(adapter);
++	err = rtw_halmac_get_available_efuse_size(d, &size);
++	if (err)
++		return 0;
++
++	return size;
++}
++
++
++u8 efuse_bt_GetCurrentSize(PADAPTER adapter, u16 *usesize)
++{
++	u8 *efuse_map;
++
++	*usesize = 0;
++	efuse_map = rtw_malloc(EFUSE_BT_MAP_LEN);
++	if (efuse_map == NULL) {
++		RTW_DBG("%s: malloc FAIL\n", __FUNCTION__);
++		return _FAIL;
++	}
++
++	/* for get bt phy efuse last use byte */
++	hal_ReadEFuse_BT_logic_map(adapter, 0x00, EFUSE_BT_MAP_LEN, efuse_map);
++	*usesize = fakeBTEfuseUsedBytes;
++
++	if (efuse_map)
++		rtw_mfree(efuse_map, EFUSE_BT_MAP_LEN);
++
++	return _SUCCESS;
++}
++
++u16 efuse_bt_GetMaxSize(PADAPTER adapter)
++{
++	return EFUSE_BT_REAL_CONTENT_LEN;
++}
++
++void EFUSE_GetEfuseDefinition(PADAPTER adapter, u8 efusetype, u8 type, void *out, BOOLEAN test)
++{
++	struct dvobj_priv *d;
++	u32 v32 = 0;
++
++
++	d = adapter_to_dvobj(adapter);
++
++	if (adapter->hal_func.EFUSEGetEfuseDefinition) {
++		adapter->hal_func.EFUSEGetEfuseDefinition(adapter, efusetype, type, out, test);
++		return;
++	}
++
++	if (EFUSE_WIFI == efusetype) {
++		switch (type) {
++		case TYPE_EFUSE_MAP_LEN:
++			rtw_halmac_get_logical_efuse_size(d, &v32);
++			*(u16 *)out = (u16)v32;
++			return;
++
++		case TYPE_EFUSE_REAL_CONTENT_LEN:
++			rtw_halmac_get_physical_efuse_size(d, &v32);
++			*(u16 *)out = (u16)v32;
++			return;
++		}
++	} else if (EFUSE_BT == efusetype) {
++		switch (type) {
++		case TYPE_EFUSE_MAP_LEN:
++			*(u16 *)out = EFUSE_BT_MAP_LEN;
++			return;
++
++		case TYPE_EFUSE_REAL_CONTENT_LEN:
++			*(u16 *)out = EFUSE_BT_REAL_CONTENT_LEN;
++			return;
++		}
++	}
++}
++
++/*
++ * read/write raw efuse data
++ */
++u8 rtw_efuse_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data)
++{
++	struct dvobj_priv *d;
++	u8 *efuse = NULL;
++	u32 size;
++	int err;
++
++
++	d = adapter_to_dvobj(adapter);
++	err = rtw_halmac_get_physical_efuse_size(d, &size);
++	if (err){
++		size = EFUSE_MAX_SIZE;
++		RTW_INFO(" physical_efuse_size err size %d\n", size);
++	}
++
++	if ((addr + cnts) > size)
++		return _FAIL;
++
++	if (_TRUE == write) {
++		err = rtw_halmac_write_physical_efuse(d, addr, cnts, data);
++		if (err)
++			return _FAIL;
++	} else {
++		if (cnts > 16)
++			efuse = rtw_zmalloc(size);
++
++		if (efuse) {
++			err = rtw_halmac_read_physical_efuse_map(d, efuse, size);
++			if (err) {
++				rtw_mfree(efuse, size);
++				return _FAIL;
++			}
++
++			_rtw_memcpy(data, efuse + addr, cnts);
++			rtw_mfree(efuse, size);
++		} else {
++			err = rtw_halmac_read_physical_efuse(d, addr, cnts, data);
++			if (err)
++				return _FAIL;
++		}
++	}
++
++	return _SUCCESS;
++}
++
++static inline void dump_buf(u8 *buf, u32 len)
++{
++	u32 i;
++
++	RTW_INFO("-----------------Len %d----------------\n", len);
++	for (i = 0; i < len; i++)
++		printk("%2.2x-", *(buf + i));
++	printk("\n");
++}
++
++/*
++ * read/write raw efuse data
++ */
++u8 rtw_efuse_bt_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data)
++{
++	struct dvobj_priv *d;
++	u8 *efuse = NULL;
++	u32 size;
++	int err = _FAIL;
++
++
++	d = adapter_to_dvobj(adapter);
++
++	size = EFUSE_BT_REAL_CONTENT_LEN;
++
++	if ((addr + cnts) > size)
++		return _FAIL;
++
++	if (_TRUE == write) {
++		err = rtw_halmac_write_bt_physical_efuse(d, addr, cnts, data);
++		if (err == -1) {
++			RTW_ERR("%s: rtw_halmac_write_bt_physical_efuse fail!\n", __FUNCTION__);
++			return _FAIL;
++		}
++		RTW_INFO("%s: rtw_halmac_write_bt_physical_efuse OK! data 0x%x\n", __FUNCTION__, *data);
++	} else {
++		efuse = rtw_zmalloc(size);
++
++		if (efuse) {
++			err = rtw_halmac_read_bt_physical_efuse_map(d, efuse, size);
++
++			if (err == -1) {
++				RTW_ERR("%s: rtw_halmac_read_bt_physical_efuse_map fail!\n", __FUNCTION__);
++				rtw_mfree(efuse, size);
++				return _FAIL;
++			}
++			dump_buf(efuse + addr, cnts);
++
++			_rtw_memcpy(data, efuse + addr, cnts);
++
++			RTW_INFO("%s: rtw_halmac_read_bt_physical_efuse_map ok! data 0x%x\n", __FUNCTION__, *data);
++			rtw_mfree(efuse, size);
++		}
++	}
++
++	return _SUCCESS;
++}
++
++u8 rtw_efuse_map_read(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
++{
++	struct dvobj_priv *d;
++	u8 *efuse = NULL;
++	u32 size, i;
++	int err;
++	u32	backupRegs[4] = {0};
++	u8 status = _SUCCESS;
++
++	efuse_PreUpdateAction(adapter, backupRegs);
++
++	d = adapter_to_dvobj(adapter);
++	err = rtw_halmac_get_logical_efuse_size(d, &size);
++	if (err) {
++		status = _FAIL;
++		RTW_DBG("halmac_get_logical_efuse_size fail\n");
++		goto exit;
++	}
++	/* size error handle */
++	if ((addr + cnts) > size) {
++		if (addr < size)
++			cnts = size - addr;
++		else {
++			status = _FAIL;
++			RTW_DBG(" %s() ,addr + cnts) > size fail\n", __func__);
++			goto exit;
++		}
++	}
++
++	if (cnts > 16)
++		efuse = rtw_zmalloc(size);
++
++	if (efuse) {
++		err = rtw_halmac_read_logical_efuse_map(d, efuse, size, NULL, 0);
++		if (err) {
++			rtw_mfree(efuse, size);
++			status = _FAIL;
++			RTW_DBG(" %s() ,halmac_read_logical_efus map fail\n", __func__);
++			goto exit;
++		}
++
++		_rtw_memcpy(data, efuse + addr, cnts);
++		rtw_mfree(efuse, size);
++	} else {
++		err = rtw_halmac_read_logical_efuse(d, addr, cnts, data);
++		if (err) {
++			status = _FAIL;
++			RTW_DBG(" %s() ,halmac_read_logical_efus data fail\n", __func__);
++			goto exit;
++		}
++	}
++	status = _SUCCESS;
++exit:
++	efuse_PostUpdateAction(adapter, backupRegs);
++
++	return status;
++}
++
++
++u8 rtw_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
++{
++	struct dvobj_priv *d;
++	u8 *efuse = NULL;
++	u32 size;
++	int err;
++	u8 mask_buf[64] = "";
++	u16 mask_len = sizeof(u8) * rtw_get_efuse_mask_arraylen(adapter);
++	u32 backupRegs[4] = {0};
++	u8 status = _SUCCESS;;
++
++	efuse_PreUpdateAction(adapter, backupRegs);
++
++	d = adapter_to_dvobj(adapter);
++	err = rtw_halmac_get_logical_efuse_size(d, &size);
++	if (err) {
++		status = _FAIL;
++		goto exit;
++	}
++
++	if ((addr + cnts) > size) {
++		status = _FAIL;
++		goto exit;
++	}
++
++	efuse = rtw_zmalloc(size);
++	if (!efuse) {
++		status = _FAIL;
++		goto exit;
++	}
++
++	err = rtw_halmac_read_logical_efuse_map(d, efuse, size, NULL, 0);
++	if (err) {
++		rtw_mfree(efuse, size);
++		status = _FAIL;
++		goto exit;
++	}
++
++	_rtw_memcpy(efuse + addr, data, cnts);
++
++	if (adapter->registrypriv.boffefusemask == 0) {
++		RTW_INFO("Use mask Array Len: %d\n", mask_len);
++
++		if (mask_len != 0) {
++			if (adapter->registrypriv.bFileMaskEfuse == _TRUE)
++				_rtw_memcpy(mask_buf, maskfileBuffer, mask_len);
++			else
++				rtw_efuse_mask_array(adapter, mask_buf);
++
++			err = rtw_halmac_write_logical_efuse_map(d, efuse, size, mask_buf, mask_len);
++		} else
++			err = rtw_halmac_write_logical_efuse_map(d, efuse, size, NULL, 0);
++	} else {
++		_rtw_memset(mask_buf, 0xFF, sizeof(mask_buf));
++		RTW_INFO("Efuse mask off\n");
++		err = rtw_halmac_write_logical_efuse_map(d, efuse, size, mask_buf, size/16);
++	}
++
++	if (err) {
++		rtw_mfree(efuse, size);
++		status = _FAIL;
++		goto exit;
++	}
++
++	rtw_mfree(efuse, size);
++	status = _SUCCESS;
++exit :
++	efuse_PostUpdateAction(adapter, backupRegs);
++
++	return status;
++}
++
++int Efuse_PgPacketRead(PADAPTER adapter, u8 offset, u8 *data, BOOLEAN test)
++{
++	return _FALSE;
++}
++
++int Efuse_PgPacketWrite(PADAPTER adapter, u8 offset, u8 word_en, u8 *data, BOOLEAN test)
++{
++	return _FALSE;
++}
++
++static void rtw_bt_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
++{
++	u16 i = 0;
++
++	if (padapter->registrypriv.boffefusemask == 0) {
++			for (i = 0; i < cnts; i++) {
++				if (padapter->registrypriv.bBTFileMaskEfuse == _TRUE) {
++						if (rtw_file_efuse_IsMasked(padapter, addr + i, btmaskfileBuffer)) /*use BT file efuse mask.*/
++							data[i] = 0xff;
++						else
++							RTW_DBG("data[%x] = %x\n", i, data[i]);
++				} else {
++						if (efuse_IsBT_Masked(padapter, addr + i)) /*use drv internal efuse mask.*/
++							data[i] = 0xff;
++						else
++							RTW_DBG("data[%x] = %x\n", i, data[i]);
++					}
++			}
++	}
++
++}
++
++u8 rtw_BT_efuse_map_read(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
++{
++	hal_ReadEFuse_BT_logic_map(adapter, addr, cnts, data);
++
++	rtw_bt_mask_map_read(adapter, addr, cnts, data);
++
++	return _SUCCESS;
++}
++
++
++static u16
++hal_EfuseGetCurrentSize_BT(
++	PADAPTER	padapter,
++	u8			bPseudoTest)
++{
++#ifdef HAL_EFUSE_MEMORY
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++	PEFUSE_HAL		pEfuseHal = &pHalData->EfuseHal;
++#endif
++	u16 btusedbytes;
++	u16	efuse_addr;
++	u8	bank, startBank;
++	u8	hoffset = 0, hworden = 0;
++	u8	efuse_data, word_cnts = 0;
++	u16	retU2 = 0;
++
++
++	btusedbytes = fakeBTEfuseUsedBytes;
++
++	efuse_addr = (u16)((btusedbytes % EFUSE_BT_REAL_BANK_CONTENT_LEN));
++	startBank = (u8)(1 + (btusedbytes / EFUSE_BT_REAL_BANK_CONTENT_LEN));
++
++	RTW_INFO("%s: start from bank=%d addr=0x%X\n", __FUNCTION__, startBank, efuse_addr);
++	retU2 = EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK;
++
++	for (bank = startBank; bank < 3; bank++) {
++		if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == _FALSE) {
++			RTW_ERR("%s: switch bank(%d) Fail!!\n", __FUNCTION__, bank);
++			/* bank = EFUSE_MAX_BANK; */
++			break;
++		}
++
++		/* only when bank is switched we have to reset the efuse_addr. */
++		if (bank != startBank)
++			efuse_addr = 0;
++
++
++		while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
++			if (rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &efuse_data) == _FALSE) {
++				RTW_ERR("%s: efuse_OneByteRead Fail! addr=0x%X !!\n", __FUNCTION__, efuse_addr);
++				/* bank = EFUSE_MAX_BANK; */
++				break;
++			}
++			RTW_INFO("%s: efuse_OneByteRead ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank);
++
++			if (efuse_data == 0xFF)
++				break;
++
++			if (EXT_HEADER(efuse_data)) {
++				hoffset = GET_HDR_OFFSET_2_0(efuse_data);
++				efuse_addr++;
++				rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &efuse_data);
++				RTW_INFO("%s: efuse_OneByteRead EXT_HEADER ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank);
++
++				if (ALL_WORDS_DISABLED(efuse_data)) {
++					efuse_addr++;
++					continue;
++				}
++
++				/*				hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); */
++				hoffset |= ((efuse_data & 0xF0) >> 1);
++				hworden = efuse_data & 0x0F;
++			} else {
++				hoffset = (efuse_data >> 4) & 0x0F;
++				hworden =  efuse_data & 0x0F;
++			}
++
++			RTW_INFO(FUNC_ADPT_FMT": Offset=%d Worden=%#X\n",
++				 FUNC_ADPT_ARG(padapter), hoffset, hworden);
++
++			word_cnts = Efuse_CalculateWordCnts(hworden);
++			/* read next header */
++			efuse_addr += (word_cnts * 2) + 1;
++		}
++		/* Check if we need to check next bank efuse */
++		if (efuse_addr < retU2)
++			break;/* don't need to check next bank. */
++	}
++	retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;
++
++	fakeBTEfuseUsedBytes = retU2;
++	RTW_INFO("%s: CurrentSize=%d\n", __FUNCTION__, retU2);
++	return retU2;
++}
++
++#ifdef CONFIG_RTL8822C
++void rtw_pre_bt_efuse(PADAPTER padapter)
++{
++	char pgdata[4] = {0x72, 0x80, 0x14, 0x90}; /*BT 5M PLL*/
++	u8 status = 1;
++	u8 bkmask;
++	BOOLEAN bt_en;
++
++	bkmask = padapter->registrypriv.boffefusemask;
++	padapter->registrypriv.boffefusemask = 1;
++
++	bt_en = rtw_read8(padapter, 0x6A) & BIT2 ? _TRUE : _FALSE;
++	if (IS_HARDWARE_TYPE_8822C(padapter) && bt_en == _TRUE) {
++			status = rtw_BT_efuse_map_write(padapter, 0x1f8, 4, pgdata);
++			RTW_INFO("%s done!!!\n", __FUNCTION__);
++	}
++	if (status == _FAIL)
++		RTW_INFO("%s: fail\n", __FUNCTION__);
++	padapter->registrypriv.boffefusemask = bkmask;
++}
++#endif
++
++u8 rtw_BT_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
++{
++#define RT_ASSERT_RET(expr)									\
++	if (!(expr)) {										\
++		printk("Assertion failed! %s at ......\n", #expr);				\
++		printk("	  ......%s,%s, line=%d\n",__FILE__, __FUNCTION__, __LINE__);	\
++		return _FAIL;	\
++	}
++
++	u8	offset, word_en;
++	u8 *efuse = NULL;
++	u8	*map;
++	u8	newdata[PGPKT_DATA_SIZE];
++	s32 i = 0, j = 0, idx = 0, chk_total_byte = 0;
++	u8	ret = _SUCCESS;
++	u16 mapLen = 1024;
++	u16 startAddr = 0;
++
++	if ((addr + cnts) > mapLen)
++		return _FAIL;
++
++	RT_ASSERT_RET(PGPKT_DATA_SIZE == 8); /* have to be 8 byte alignment */
++	RT_ASSERT_RET((mapLen & 0x7) == 0); /* have to be PGPKT_DATA_SIZE alignment for memcpy */
++
++	efuse = rtw_zmalloc(mapLen);
++	if (!efuse)
++		return _FAIL;
++
++	map = rtw_zmalloc(mapLen);
++	if (map == NULL) {
++		rtw_mfree(efuse, mapLen);
++		return _FAIL;
++	}
++
++	_rtw_memset(map, 0xFF, mapLen);
++
++	ret = rtw_BT_efuse_map_read(adapter, 0, mapLen, map);
++	if (ret == _FAIL)
++		goto exit;
++
++	_rtw_memcpy(efuse , map, mapLen);
++	_rtw_memcpy(efuse + addr, data, cnts);
++
++	if (adapter->registrypriv.boffefusemask == 0) {
++		for (i = 0; i < cnts; i++) {
++			if (adapter->registrypriv.bFileMaskEfuse == _TRUE) {
++				if (rtw_file_efuse_IsMasked(adapter, addr + i, btmaskfileBuffer)) /*use file efuse mask. */
++					efuse[addr + i] = map[addr + i];
++			} else {
++				if (efuse_IsBT_Masked(adapter, addr + i))
++					efuse[addr + i] = map[addr + i];
++			}
++			RTW_INFO("%s , efuse[%x] = %x, map = %x\n", __func__, addr + i, efuse[ addr + i], map[addr + i]);
++		}
++	}
++	/* precheck pg efuse data byte*/
++	chk_total_byte = 0;
++	idx = 0;
++	offset = (addr >> 3);
++
++	while (idx < cnts) {
++		word_en = 0xF;
++		j = (addr + idx) & 0x7;
++		for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {
++			if (efuse[addr + idx] != map[addr + idx])
++				word_en &= ~BIT(i >> 1);
++		}
++
++		if (word_en != 0xF) {
++			chk_total_byte += Efuse_CalculateWordCnts(word_en) * 2;
++
++			if (offset >= EFUSE_MAX_SECTION_BASE) /* Over EFUSE_MAX_SECTION 16 for 2 ByteHeader */
++				chk_total_byte += 2;
++			else
++				chk_total_byte += 1;
++		}
++
++		offset++;
++	}
++
++	RTW_INFO("Total PG bytes Count = %d\n", chk_total_byte);
++	startAddr = hal_EfuseGetCurrentSize_BT(adapter, _FALSE);
++	RTW_INFO("%s: startAddr=%#X\n", __func__, startAddr);
++
++	if (!AVAILABLE_EFUSE_ADDR(startAddr + chk_total_byte)) {
++		RTW_INFO("%s: startAddr(0x%X) + PG data len %d >= efuse BT available offset (0x%X)\n",
++			 __func__, startAddr, chk_total_byte, EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK);
++		ret = _FAIL;
++		goto exit;
++	}
++
++	idx = 0;
++	offset = (addr >> 3);
++	while (idx < cnts) {
++		word_en = 0xF;
++		j = (addr + idx) & 0x7;
++		_rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE);
++		for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {
++			if (efuse[addr + idx] != map[addr + idx]) {
++				word_en &= ~BIT(i >> 1);
++				newdata[i] = efuse[addr + idx];
++			}
++		}
++
++		if (word_en != 0xF) {
++			ret = EfusePgPacketWrite_BT(adapter, offset, word_en, newdata, _FALSE);
++			RTW_INFO("offset=%x\n", offset);
++			RTW_INFO("word_en=%x\n", word_en);
++			RTW_INFO("%s: data=", __FUNCTION__);
++			for (i = 0; i < PGPKT_DATA_SIZE; i++)
++				RTW_INFO("0x%02X ", newdata[i]);
++			RTW_INFO("\n");
++			if (ret == _FAIL)
++				break;
++		}
++		offset++;
++	}
++exit:
++	rtw_mfree(map, mapLen);
++	return ret;
++}
++
++void hal_ReadEFuse_BT_logic_map(
++	PADAPTER	padapter,
++	u16			_offset,
++	u16			_size_byte,
++	u8			*pbuf
++)
++{
++
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++
++	u8	*efuseTbl, *phyefuse;
++	u8	bank;
++	u16	eFuse_Addr = 0;
++	u8	efuseHeader, efuseExtHdr, efuseData;
++	u8	offset, wden;
++	u16	i, total, used;
++	u8	efuse_usage;
++
++
++	/* */
++	/* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
++	/* */
++	if ((_offset + _size_byte) > EFUSE_BT_MAP_LEN) {
++		RTW_INFO("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __FUNCTION__, _offset, _size_byte);
++		return;
++	}
++
++	efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN);
++	phyefuse = rtw_malloc(EFUSE_BT_REAL_CONTENT_LEN);
++	if (efuseTbl == NULL || phyefuse == NULL) {
++		RTW_INFO("%s: efuseTbl or phyefuse malloc fail!\n", __FUNCTION__);
++		goto exit;
++	}
++
++	/* 0xff will be efuse default value instead of 0x00. */
++	_rtw_memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);
++	_rtw_memset(phyefuse, 0xFF, EFUSE_BT_REAL_CONTENT_LEN);
++
++	if (rtw_efuse_bt_access(padapter, _FALSE, 0, EFUSE_BT_REAL_CONTENT_LEN, phyefuse))
++		dump_buf(phyefuse, EFUSE_BT_REAL_BANK_CONTENT_LEN);
++
++	total = BANK_NUM;
++	for (bank = 1; bank <= total; bank++) { /* 8723d Max bake 0~2 */
++		eFuse_Addr = 0;
++
++		while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
++			/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); */
++			efuseHeader = phyefuse[eFuse_Addr++];
++
++			if (efuseHeader == 0xFF)
++				break;
++			RTW_INFO("%s: efuse[%#X]=0x%02x (header)\n", __FUNCTION__, (((bank - 1) * EFUSE_BT_REAL_CONTENT_LEN) + eFuse_Addr - 1), efuseHeader);
++
++			/* Check PG header for section num. */
++			if (EXT_HEADER(efuseHeader)) {	/* extended header */
++				offset = GET_HDR_OFFSET_2_0(efuseHeader);
++				RTW_INFO("%s: extended header offset_2_0=0x%X\n", __FUNCTION__, offset);
++
++				/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); */
++				efuseExtHdr = phyefuse[eFuse_Addr++];
++
++				RTW_INFO("%s: efuse[%#X]=0x%02x (ext header)\n", __FUNCTION__, (((bank - 1) * EFUSE_BT_REAL_CONTENT_LEN) + eFuse_Addr - 1), efuseExtHdr);
++				if (ALL_WORDS_DISABLED(efuseExtHdr))
++					continue;
++
++				offset |= ((efuseExtHdr & 0xF0) >> 1);
++				wden = (efuseExtHdr & 0x0F);
++			} else {
++				offset = ((efuseHeader >> 4) & 0x0f);
++				wden = (efuseHeader & 0x0f);
++			}
++
++			if (offset < EFUSE_BT_MAX_SECTION) {
++				u16 addr;
++
++				/* Get word enable value from PG header */
++				RTW_INFO("%s: Offset=%d Worden=%#X\n", __FUNCTION__, offset, wden);
++
++				addr = offset * PGPKT_DATA_SIZE;
++				for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
++					/* Check word enable condition in the section */
++					if (!(wden & (0x01 << i))) {
++						efuseData = 0;
++						/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
++						efuseData = phyefuse[eFuse_Addr++];
++
++						RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr - 1, efuseData);
++						efuseTbl[addr] = efuseData;
++
++						efuseData = 0;
++						/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
++						efuseData = phyefuse[eFuse_Addr++];
++
++						RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr - 1, efuseData);
++						efuseTbl[addr + 1] = efuseData;
++					}
++					addr += 2;
++				}
++			} else {
++				RTW_INFO("%s: offset(%d) is illegal!!\n", __FUNCTION__, offset);
++				eFuse_Addr += Efuse_CalculateWordCnts(wden) * 2;
++			}
++		}
++
++		if ((eFuse_Addr - 1) < total) {
++			RTW_INFO("%s: bank(%d) data end at %#x\n", __FUNCTION__, bank, eFuse_Addr - 1);
++			break;
++		}
++	}
++
++	/* switch bank back to bank 0 for later BT and wifi use. */
++	//hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
++
++	/* Copy from Efuse map to output pointer memory!!! */
++	for (i = 0; i < _size_byte; i++)
++		pbuf[i] = efuseTbl[_offset + i];
++	/* Calculate Efuse utilization */
++	total = EFUSE_BT_REAL_BANK_CONTENT_LEN;
++
++	used = eFuse_Addr - 1;
++
++	if (total)
++		efuse_usage = (u8)((used * 100) / total);
++	else
++		efuse_usage = 100;
++
++	fakeBTEfuseUsedBytes = used;
++	RTW_INFO("%s: BTEfuseUsed last Bytes = %#x\n", __FUNCTION__, fakeBTEfuseUsedBytes);
++
++exit:
++	if (efuseTbl)
++		rtw_mfree(efuseTbl, EFUSE_BT_MAP_LEN);
++	if (phyefuse)
++		rtw_mfree(phyefuse, EFUSE_BT_REAL_BANK_CONTENT_LEN);
++}
++
++
++static u8 hal_EfusePartialWriteCheck(
++	PADAPTER		padapter,
++	u8				efuseType,
++	u16				*pAddr,
++	PPGPKT_STRUCT	pTargetPkt,
++	u8				bPseudoTest)
++{
++	u8	bRet = _FALSE;
++	u16	startAddr = 0, efuse_max_available_len = EFUSE_BT_REAL_BANK_CONTENT_LEN, efuse_max = EFUSE_BT_REAL_BANK_CONTENT_LEN;
++	u8	efuse_data = 0;
++
++	startAddr = (u16)fakeBTEfuseUsedBytes;
++
++	startAddr %= efuse_max;
++	RTW_INFO("%s: startAddr=%#X\n", __FUNCTION__, startAddr);
++
++	while (1) {
++		if (startAddr >= efuse_max_available_len) {
++			bRet = _FALSE;
++			RTW_INFO("%s: startAddr(%d) >= efuse_max_available_len(%d)\n",
++				__FUNCTION__, startAddr, efuse_max_available_len);
++			break;
++		}
++		if (rtw_efuse_bt_access(padapter, _FALSE, startAddr, 1, &efuse_data)&& (efuse_data != 0xFF)) {
++			bRet = _FALSE;
++			RTW_INFO("%s: Something Wrong! last bytes(%#X=0x%02X) is not 0xFF\n",
++				 __FUNCTION__, startAddr, efuse_data);
++			break;
++		} else {
++			/* not used header, 0xff */
++			*pAddr = startAddr;
++			/*			RTW_INFO("%s: Started from unused header offset=%d\n", __FUNCTION__, startAddr)); */
++			bRet = _TRUE;
++			break;
++		}
++	}
++
++	return bRet;
++}
++
++
++static u8 hal_EfusePgPacketWrite2ByteHeader(
++	PADAPTER		padapter,
++	u8				efuseType,
++	u16				*pAddr,
++	PPGPKT_STRUCT	pTargetPkt,
++	u8				bPseudoTest)
++{
++	u16	efuse_addr, efuse_max_available_len = EFUSE_BT_REAL_BANK_CONTENT_LEN;
++	u8	pg_header = 0, tmp_header = 0;
++	u8	repeatcnt = 0;
++
++	/*	RTW_INFO("%s\n", __FUNCTION__); */
++
++	efuse_addr = *pAddr;
++	if (efuse_addr >= efuse_max_available_len) {
++		RTW_INFO("%s: addr(%d) over avaliable(%d)!!\n", __FUNCTION__, efuse_addr, efuse_max_available_len);
++		return _FALSE;
++	}
++
++	pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F;
++	/*	RTW_INFO("%s: pg_header=0x%x\n", __FUNCTION__, pg_header); */
++
++	do {
++
++		rtw_efuse_bt_access(padapter, _TRUE, efuse_addr, 1, &pg_header);
++		rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &tmp_header);
++
++		if (tmp_header != 0xFF)
++			break;
++		if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
++			RTW_INFO("%s: Repeat over limit for pg_header!!\n", __FUNCTION__);
++			return _FALSE;
++		}
++	} while (1);
++
++	if (tmp_header != pg_header) {
++		RTW_ERR("%s: PG Header Fail!!(pg=0x%02X read=0x%02X)\n", __FUNCTION__, pg_header, tmp_header);
++		return _FALSE;
++	}
++
++	/* to write ext_header */
++	efuse_addr++;
++	pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en;
++
++	do {
++		rtw_efuse_bt_access(padapter, _TRUE, efuse_addr, 1, &pg_header);
++		rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &tmp_header);
++
++		if (tmp_header != 0xFF)
++			break;
++		if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
++			RTW_INFO("%s: Repeat over limit for ext_header!!\n", __FUNCTION__);
++			return _FALSE;
++		}
++	} while (1);
++
++	if (tmp_header != pg_header) {	/* offset PG fail */
++		RTW_ERR("%s: PG EXT Header Fail!!(pg=0x%02X read=0x%02X)\n", __FUNCTION__, pg_header, tmp_header);
++		return _FALSE;
++	}
++
++	*pAddr = efuse_addr;
++
++	return _TRUE;
++}
++
++
++static u8 hal_EfusePgPacketWrite1ByteHeader(
++	PADAPTER		pAdapter,
++	u8				efuseType,
++	u16				*pAddr,
++	PPGPKT_STRUCT	pTargetPkt,
++	u8				bPseudoTest)
++{
++	u8	pg_header = 0, tmp_header = 0;
++	u16	efuse_addr = *pAddr;
++	u8	repeatcnt = 0;
++
++
++	/*	RTW_INFO("%s\n", __FUNCTION__); */
++	pg_header = ((pTargetPkt->offset << 4) & 0xf0) | pTargetPkt->word_en;
++
++	do {
++		rtw_efuse_bt_access(pAdapter, _TRUE, efuse_addr, 1, &pg_header);
++		rtw_efuse_bt_access(pAdapter, _FALSE, efuse_addr, 1, &tmp_header);
++
++		if (tmp_header != 0xFF)
++			break;
++		if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
++			RTW_INFO("%s: Repeat over limit for pg_header!!\n", __FUNCTION__);
++			return _FALSE;
++		}
++	} while (1);
++
++	if (tmp_header != pg_header) {
++		RTW_ERR("%s: PG Header Fail!!(pg=0x%02X read=0x%02X)\n", __FUNCTION__, pg_header, tmp_header);
++		return _FALSE;
++	}
++
++	*pAddr = efuse_addr;
++
++	return _TRUE;
++}
++
++static u8 hal_EfusePgPacketWriteHeader(
++	PADAPTER		padapter,
++	u8				efuseType,
++	u16				*pAddr,
++	PPGPKT_STRUCT	pTargetPkt,
++	u8				bPseudoTest)
++{
++	u8 bRet = _FALSE;
++
++	if (pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE)
++		bRet = hal_EfusePgPacketWrite2ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
++	else
++		bRet = hal_EfusePgPacketWrite1ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
++
++	return bRet;
++}
++
++
++static u8
++Hal_EfuseWordEnableDataWrite(
++	PADAPTER	padapter,
++	u16			efuse_addr,
++	u8			word_en,
++	u8			*data,
++	u8			bPseudoTest)
++{
++	u16	tmpaddr = 0;
++	u16	start_addr = efuse_addr;
++	u8	badworden = 0x0F;
++	u8	tmpdata[PGPKT_DATA_SIZE];
++
++
++	/*	RTW_INFO("%s: efuse_addr=%#x word_en=%#x\n", __FUNCTION__, efuse_addr, word_en); */
++	_rtw_memset(tmpdata, 0xFF, PGPKT_DATA_SIZE);
++
++	if (!(word_en & BIT(0))) {
++		tmpaddr = start_addr;
++		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[0]);
++		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[1]);
++		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[0]);
++		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[1]);
++		if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1]))
++			badworden &= (~BIT(0));
++	}
++	if (!(word_en & BIT(1))) {
++		tmpaddr = start_addr;
++		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[2]);
++		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[3]);
++		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[2]);
++		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[3]);
++		if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3]))
++			badworden &= (~BIT(1));
++	}
++	if (!(word_en & BIT(2))) {
++		tmpaddr = start_addr;
++		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[4]);
++		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[5]);
++		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[4]);
++		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[5]);
++		if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5]))
++			badworden &= (~BIT(2));
++	}
++	if (!(word_en & BIT(3))) {
++		tmpaddr = start_addr;
++		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[6]);
++		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[7]);
++		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[6]);
++		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[7]);
++
++		if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7]))
++			badworden &= (~BIT(3));
++	}
++
++	return badworden;
++}
++
++static void
++hal_EfuseConstructPGPkt(
++	u8				offset,
++	u8				word_en,
++	u8				*pData,
++	PPGPKT_STRUCT	pTargetPkt)
++{
++	_rtw_memset(pTargetPkt->data, 0xFF, PGPKT_DATA_SIZE);
++	pTargetPkt->offset = offset;
++	pTargetPkt->word_en = word_en;
++	efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data);
++	pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
++}
++
++static u8
++hal_EfusePgPacketWriteData(
++	PADAPTER		pAdapter,
++	u8				efuseType,
++	u16				*pAddr,
++	PPGPKT_STRUCT	pTargetPkt,
++	u8				bPseudoTest)
++{
++	u16	efuse_addr;
++	u8	badworden;
++
++	efuse_addr = *pAddr;
++	badworden = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr + 1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest);
++	if (badworden != 0x0F) {
++		RTW_INFO("%s: Fail!!\n", __FUNCTION__);
++		return _FALSE;
++	} else
++		RTW_INFO("%s: OK!!\n", __FUNCTION__);
++
++	return _TRUE;
++}
++
++u8 efuse_OneByteRead(struct _ADAPTER *a, u16 addr, u8 *data, u8 bPseudoTest)
++{
++		struct dvobj_priv *d;
++		int err;
++		u8 ret = _TRUE;
++
++		d = adapter_to_dvobj(a);
++		err = rtw_halmac_read_physical_efuse(d, addr, 1, data);
++		if (err) {
++			RTW_ERR("%s: addr=0x%x FAIL!!!\n", __FUNCTION__, addr);
++			ret = _FALSE;
++		}
++
++		return ret;
++
++}
++
++
++static u8
++hal_BT_EfusePgCheckAvailableAddr(
++	PADAPTER	pAdapter,
++	u8		bPseudoTest)
++{
++	u16	max_available = EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK;
++	u16	current_size = 0;
++
++	 RTW_INFO("%s: max_available=%d\n", __FUNCTION__, max_available);
++	current_size = hal_EfuseGetCurrentSize_BT(pAdapter, bPseudoTest);
++	if (current_size >= max_available) {
++		RTW_INFO("%s: Error!! current_size(%d)>max_available(%d)\n", __FUNCTION__, current_size, max_available);
++		return _FALSE;
++	}
++	return _TRUE;
++}
++
++u8 EfusePgPacketWrite_BT(
++	PADAPTER	pAdapter,
++	u8			offset,
++	u8			word_en,
++	u8			*pData,
++	u8			bPseudoTest)
++{
++	PGPKT_STRUCT targetPkt;
++	u16 startAddr = 0;
++	u8 efuseType = EFUSE_BT;
++
++	if (!hal_BT_EfusePgCheckAvailableAddr(pAdapter, bPseudoTest))
++		return _FALSE;
++
++	hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
++
++	if (!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
++		return _FALSE;
++
++	if (!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
++		return _FALSE;
++
++	if (!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
++		return _FALSE;
++
++	return _TRUE;
++}
++
++
++#else /* !RTW_HALMAC */
++/* ------------------------------------------------------------------------------ */
++#define REG_EFUSE_CTRL		0x0030
++#define EFUSE_CTRL			REG_EFUSE_CTRL		/* E-Fuse Control. */
++/* ------------------------------------------------------------------------------ */
++
++
++BOOLEAN
++Efuse_Read1ByteFromFakeContent(
++		PADAPTER	pAdapter,
++		u16		Offset,
++		u8		*Value);
++BOOLEAN
++Efuse_Read1ByteFromFakeContent(
++		PADAPTER	pAdapter,
++		u16		Offset,
++		u8		*Value)
++{
++	if (Offset >= EFUSE_MAX_HW_SIZE)
++		return _FALSE;
++	/* DbgPrint("Read fake content, offset = %d\n", Offset); */
++	if (fakeEfuseBank == 0)
++		*Value = fakeEfuseContent[Offset];
++	else
++		*Value = fakeBTEfuseContent[fakeEfuseBank - 1][Offset];
++	return _TRUE;
++}
++
++BOOLEAN
++Efuse_Write1ByteToFakeContent(
++			PADAPTER	pAdapter,
++			u16		Offset,
++			u8		Value);
++BOOLEAN
++Efuse_Write1ByteToFakeContent(
++			PADAPTER	pAdapter,
++			u16		Offset,
++			u8		Value)
++{
++	if (Offset >= EFUSE_MAX_HW_SIZE)
++		return _FALSE;
++	if (fakeEfuseBank == 0)
++		fakeEfuseContent[Offset] = Value;
++	else
++		fakeBTEfuseContent[fakeEfuseBank - 1][Offset] = Value;
++	return _TRUE;
++}
++
++/*-----------------------------------------------------------------------------
++ * Function:	Efuse_PowerSwitch
++ *
++ * Overview:	When we want to enable write operation, we should change to
++ *				pwr on state. When we stop write, we should switch to 500k mode
++ *				and disable LDO 2.5V.
++ *
++ * Input:       NONE
++ *
++ * Output:      NONE
++ *
++ * Return:      NONE
++ *
++ * Revised History:
++ * When			Who		Remark
++ * 11/17/2008	MHC		Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++void
++Efuse_PowerSwitch(
++		PADAPTER	pAdapter,
++		u8		bWrite,
++		u8		PwrState)
++{
++	pAdapter->hal_func.EfusePowerSwitch(pAdapter, bWrite, PwrState);
++}
++
++void
++BTEfuse_PowerSwitch(
++		PADAPTER	pAdapter,
++		u8		bWrite,
++		u8		PwrState)
++{
++	if (pAdapter->hal_func.BTEfusePowerSwitch)
++		pAdapter->hal_func.BTEfusePowerSwitch(pAdapter, bWrite, PwrState);
++}
++
++/*-----------------------------------------------------------------------------
++ * Function:	efuse_GetCurrentSize
++ *
++ * Overview:	Get current efuse size!!!
++ *
++ * Input:       NONE
++ *
++ * Output:      NONE
++ *
++ * Return:      NONE
++ *
++ * Revised History:
++ * When			Who		Remark
++ * 11/16/2008	MHC		Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++u16
++Efuse_GetCurrentSize(
++	PADAPTER		pAdapter,
++	u8			efuseType,
++	BOOLEAN		bPseudoTest)
++{
++	u16 ret = 0;
++
++	ret = pAdapter->hal_func.EfuseGetCurrentSize(pAdapter, efuseType, bPseudoTest);
++
++	return ret;
++}
++
++/*
++ *	Description:
++ *		Execute E-Fuse read byte operation.
++ *		Refered from SD1 Richard.
++ *
++ *	Assumption:
++ *		1. Boot from E-Fuse and successfully auto-load.
++ *		2. PASSIVE_LEVEL (USB interface)
++ *
++ *	Created by Roger, 2008.10.21.
++ *   */
++void
++ReadEFuseByte(
++	PADAPTER	Adapter,
++	u16			_offset,
++	u8			*pbuf,
++	BOOLEAN	bPseudoTest)
++{
++	u32	value32;
++	u8	readbyte;
++	u16	retry;
++	/* systime start=rtw_get_current_time(); */
++
++	if (bPseudoTest) {
++		Efuse_Read1ByteFromFakeContent(Adapter, _offset, pbuf);
++		return;
++	}
++	if (IS_HARDWARE_TYPE_8723B(Adapter)) {
++		/* <20130121, Kordan> For SMIC S55 EFUSE specificatoin. */
++		/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
++		phy_set_mac_reg(Adapter, EFUSE_TEST, BIT11, 0);
++	}
++	/* Write Address */
++	rtw_write8(Adapter, EFUSE_CTRL + 1, (_offset & 0xff));
++	readbyte = rtw_read8(Adapter, EFUSE_CTRL + 2);
++	rtw_write8(Adapter, EFUSE_CTRL + 2, ((_offset >> 8) & 0x03) | (readbyte & 0xfc));
++
++	/* Write bit 32 0 */
++	readbyte = rtw_read8(Adapter, EFUSE_CTRL + 3);
++	rtw_write8(Adapter, EFUSE_CTRL + 3, (readbyte & 0x7f));
++
++	/* Check bit 32 read-ready */
++	retry = 0;
++	value32 = rtw_read32(Adapter, EFUSE_CTRL);
++	/* while(!(((value32 >> 24) & 0xff) & 0x80)  && (retry<10)) */
++	while (!(((value32 >> 24) & 0xff) & 0x80)  && (retry < 10000)) {
++		value32 = rtw_read32(Adapter, EFUSE_CTRL);
++		retry++;
++	}
++
++	/* 20100205 Joseph: Add delay suggested by SD1 Victor. */
++	/* This fix the problem that Efuse read error in high temperature condition. */
++	/* Designer says that there shall be some delay after ready bit is set, or the */
++	/* result will always stay on last data we read. */
++	rtw_udelay_os(50);
++	value32 = rtw_read32(Adapter, EFUSE_CTRL);
++
++	*pbuf = (u8)(value32 & 0xff);
++	/* RTW_INFO("ReadEFuseByte _offset:%08u, in %d ms\n",_offset ,rtw_get_passing_time_ms(start)); */
++
++}
++
++/*
++ *	Description:
++ *		1. Execute E-Fuse read byte operation according as map offset and
++ *		    save to E-Fuse table.
++ *		2. Refered from SD1 Richard.
++ *
++ *	Assumption:
++ *		1. Boot from E-Fuse and successfully auto-load.
++ *		2. PASSIVE_LEVEL (USB interface)
++ *
++ *	Created by Roger, 2008.10.21.
++ *
++ *	2008/12/12 MH	1. Reorganize code flow and reserve bytes. and add description.
++ *					2. Add efuse utilization collect.
++ *	2008/12/22 MH	Read Efuse must check if we write section 1 data again!!! Sec1
++ *					write addr must be after sec5.
++ *   */
++
++void
++efuse_ReadEFuse(
++	PADAPTER	Adapter,
++	u8		efuseType,
++	u16		_offset,
++	u16		_size_byte,
++	u8	*pbuf,
++	BOOLEAN	bPseudoTest
++);
++void
++efuse_ReadEFuse(
++	PADAPTER	Adapter,
++	u8		efuseType,
++	u16		_offset,
++	u16		_size_byte,
++	u8	*pbuf,
++	BOOLEAN	bPseudoTest
++)
++{
++	Adapter->hal_func.ReadEFuse(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);
++}
++
++void
++EFUSE_GetEfuseDefinition(
++			PADAPTER	pAdapter,
++			u8		efuseType,
++			u8		type,
++			void		*pOut,
++			BOOLEAN		bPseudoTest
++)
++{
++	pAdapter->hal_func.EFUSEGetEfuseDefinition(pAdapter, efuseType, type, pOut, bPseudoTest);
++}
++
++
++/*  11/16/2008 MH Read one byte from real Efuse. */
++u8
++efuse_OneByteRead(
++		PADAPTER	pAdapter,
++		u16			addr,
++		u8			*data,
++		BOOLEAN		bPseudoTest)
++{
++	u32	tmpidx = 0;
++	u8	bResult;
++	u8	readbyte;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++
++	/* RTW_INFO("===> EFUSE_OneByteRead(), addr = %x\n", addr); */
++	/* RTW_INFO("===> EFUSE_OneByteRead() start, 0x34 = 0x%X\n", rtw_read32(pAdapter, EFUSE_TEST)); */
++
++	if (bPseudoTest) {
++		bResult = Efuse_Read1ByteFromFakeContent(pAdapter, addr, data);
++		return bResult;
++	}
++
++#ifdef CONFIG_RTL8710B
++	/* <20171208, Peter>, Dont do the following write16(0x34) */
++	if (IS_HARDWARE_TYPE_8710B(pAdapter)) {
++		bResult = pAdapter->hal_func.efuse_indirect_read4(pAdapter, addr, data);
++		return bResult;
++	}
++#endif
++
++	if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
++	    (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
++	    (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
++	   ) {
++		/* <20130121, Kordan> For SMIC EFUSE specificatoin. */
++		/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8])	 */
++		/* phy_set_mac_reg(pAdapter, 0x34, BIT11, 0); */
++		rtw_write16(pAdapter, 0x34, rtw_read16(pAdapter, 0x34) & (~BIT11));
++	}
++
++	/* -----------------e-fuse reg ctrl --------------------------------- */
++	/* address			 */
++	rtw_write8(pAdapter, EFUSE_CTRL + 1, (u8)(addr & 0xff));
++	rtw_write8(pAdapter, EFUSE_CTRL + 2, ((u8)((addr >> 8) & 0x03)) |
++		   (rtw_read8(pAdapter, EFUSE_CTRL + 2) & 0xFC));
++
++	/* rtw_write8(pAdapter, EFUSE_CTRL+3,  0x72); */ /* read cmd	 */
++	/* Write bit 32 0 */
++	readbyte = rtw_read8(pAdapter, EFUSE_CTRL + 3);
++	rtw_write8(pAdapter, EFUSE_CTRL + 3, (readbyte & 0x7f));
++
++	while (!(0x80 & rtw_read8(pAdapter, EFUSE_CTRL + 3)) && (tmpidx < 1000)) {
++		rtw_mdelay_os(1);
++		tmpidx++;
++	}
++	if (tmpidx < 100) {
++		*data = rtw_read8(pAdapter, EFUSE_CTRL);
++		bResult = _TRUE;
++	} else {
++		*data = 0xff;
++		bResult = _FALSE;
++		RTW_INFO("%s: [ERROR] addr=0x%x bResult=%d time out 1s !!!\n", __FUNCTION__, addr, bResult);
++		RTW_INFO("%s: [ERROR] EFUSE_CTRL =0x%08x !!!\n", __FUNCTION__, rtw_read32(pAdapter, EFUSE_CTRL));
++	}
++
++	return bResult;
++}
++
++/*  11/16/2008 MH Write one byte to reald Efuse. */
++u8
++efuse_OneByteWrite(
++		PADAPTER	pAdapter,
++		u16			addr,
++		u8			data,
++		BOOLEAN		bPseudoTest)
++{
++	u8	tmpidx = 0;
++	u8	bResult = _FALSE;
++	u32 efuseValue = 0;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++
++	/* RTW_INFO("===> EFUSE_OneByteWrite(), addr = %x data=%x\n", addr, data); */
++	/* RTW_INFO("===> EFUSE_OneByteWrite() start, 0x34 = 0x%X\n", rtw_read32(pAdapter, EFUSE_TEST)); */
++
++	if (bPseudoTest) {
++		bResult = Efuse_Write1ByteToFakeContent(pAdapter, addr, data);
++		return bResult;
++	}
++
++	Efuse_PowerSwitch(pAdapter, _TRUE, _TRUE);
++
++	/* -----------------e-fuse reg ctrl ---------------------------------	 */
++	/* address			 */
++
++
++	efuseValue = rtw_read32(pAdapter, EFUSE_CTRL);
++	efuseValue |= (BIT21 | BIT31);
++	efuseValue &= ~(0x3FFFF);
++	efuseValue |= ((addr << 8 | data) & 0x3FFFF);
++
++	/* <20130227, Kordan> 8192E MP chip A-cut had better not set 0x34[11] until B-Cut. */
++	if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
++	    (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
++	    (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
++	   ) {
++		/* <20130121, Kordan> For SMIC EFUSE specificatoin. */
++		/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
++		/* phy_set_mac_reg(pAdapter, 0x34, BIT11, 1); */
++		rtw_write16(pAdapter, 0x34, rtw_read16(pAdapter, 0x34) | (BIT11));
++		rtw_write32(pAdapter, EFUSE_CTRL, 0x90600000 | ((addr << 8 | data)));
++	} else
++		rtw_write32(pAdapter, EFUSE_CTRL, efuseValue);
++
++	rtw_mdelay_os(1);
++
++	while ((0x80 &  rtw_read8(pAdapter, EFUSE_CTRL + 3)) && (tmpidx < 100)) {
++		rtw_mdelay_os(1);
++		tmpidx++;
++	}
++
++	if (tmpidx < 100)
++		bResult = _TRUE;
++	else {
++		bResult = _FALSE;
++		RTW_INFO("%s: [ERROR] addr=0x%x ,efuseValue=0x%x ,bResult=%d time out 1s !!!\n",
++			 __FUNCTION__, addr, efuseValue, bResult);
++		RTW_INFO("%s: [ERROR] EFUSE_CTRL =0x%08x !!!\n", __FUNCTION__, rtw_read32(pAdapter, EFUSE_CTRL));
++	}
++
++	/* disable Efuse program enable */
++	if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
++	    (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
++	    (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
++	   )
++		phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT(11), 0);
++
++	Efuse_PowerSwitch(pAdapter, _TRUE, _FALSE);
++
++	return bResult;
++}
++
++int
++Efuse_PgPacketRead(PADAPTER	pAdapter,
++			u8			offset,
++			u8			*data,
++			BOOLEAN		bPseudoTest)
++{
++	int	ret = 0;
++
++	ret =  pAdapter->hal_func.Efuse_PgPacketRead(pAdapter, offset, data, bPseudoTest);
++
++	return ret;
++}
++
++int
++Efuse_PgPacketWrite(PADAPTER	pAdapter,
++			u8			offset,
++			u8			word_en,
++			u8			*data,
++			BOOLEAN		bPseudoTest)
++{
++	int ret;
++
++	ret =  pAdapter->hal_func.Efuse_PgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest);
++
++	return ret;
++}
++
++
++int
++Efuse_PgPacketWrite_BT(PADAPTER	pAdapter,
++			u8			offset,
++			u8			word_en,
++			u8			*data,
++			BOOLEAN		bPseudoTest)
++{
++	int ret;
++
++	ret =  pAdapter->hal_func.Efuse_PgPacketWrite_BT(pAdapter, offset, word_en, data, bPseudoTest);
++
++	return ret;
++}
++
++
++u8
++Efuse_WordEnableDataWrite(PADAPTER	pAdapter,
++				u16		efuse_addr,
++				u8		word_en,
++				u8		*data,
++				BOOLEAN		bPseudoTest)
++{
++	u8	ret = 0;
++
++	ret =  pAdapter->hal_func.Efuse_WordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest);
++
++	return ret;
++}
++
++static u8 efuse_read8(PADAPTER padapter, u16 address, u8 *value)
++{
++	return efuse_OneByteRead(padapter, address, value, _FALSE);
++}
++
++static u8 efuse_write8(PADAPTER padapter, u16 address, u8 *value)
++{
++	return efuse_OneByteWrite(padapter, address, *value, _FALSE);
++}
++
++/*
++ * read/wirte raw efuse data
++ */
++u8 rtw_efuse_access(PADAPTER padapter, u8 bWrite, u16 start_addr, u16 cnts, u8 *data)
++{
++	int i = 0;
++	u16	real_content_len = 0, max_available_size = 0;
++	u8 res = _FAIL ;
++	u8(*rw8)(PADAPTER, u16, u8 *);
++	u32	backupRegs[4] = {0};
++
++
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (void *)&real_content_len, _FALSE);
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (void *)&max_available_size, _FALSE);
++
++	if (start_addr > real_content_len)
++		return _FAIL;
++
++	if (_TRUE == bWrite) {
++		if ((start_addr + cnts) > max_available_size)
++			return _FAIL;
++		rw8 = &efuse_write8;
++	} else
++		rw8 = &efuse_read8;
++
++	efuse_PreUpdateAction(padapter, backupRegs);
++
++	Efuse_PowerSwitch(padapter, bWrite, _TRUE);
++
++	/* e-fuse one byte read / write */
++	for (i = 0; i < cnts; i++) {
++		if (start_addr >= real_content_len) {
++			res = _FAIL;
++			break;
++		}
++
++		res = rw8(padapter, start_addr++, data++);
++		if (_FAIL == res)
++			break;
++	}
++
++	Efuse_PowerSwitch(padapter, bWrite, _FALSE);
++
++	efuse_PostUpdateAction(padapter, backupRegs);
++
++	return res;
++}
++/* ------------------------------------------------------------------------------ */
++u16 efuse_GetMaxSize(PADAPTER padapter)
++{
++	u16	max_size;
++
++	max_size = 0;
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI , TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (void *)&max_size, _FALSE);
++	return max_size;
++}
++/* ------------------------------------------------------------------------------ */
++u8 efuse_GetCurrentSize(PADAPTER padapter, u16 *size)
++{
++	Efuse_PowerSwitch(padapter, _FALSE, _TRUE);
++	*size = Efuse_GetCurrentSize(padapter, EFUSE_WIFI, _FALSE);
++	Efuse_PowerSwitch(padapter, _FALSE, _FALSE);
++
++	return _SUCCESS;
++}
++/* ------------------------------------------------------------------------------ */
++u16 efuse_bt_GetMaxSize(PADAPTER padapter)
++{
++	u16	max_size;
++
++	max_size = 0;
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_BT , TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (void *)&max_size, _FALSE);
++	return max_size;
++}
++
++u8 efuse_bt_GetCurrentSize(PADAPTER padapter, u16 *size)
++{
++	Efuse_PowerSwitch(padapter, _FALSE, _TRUE);
++	*size = Efuse_GetCurrentSize(padapter, EFUSE_BT, _FALSE);
++	Efuse_PowerSwitch(padapter, _FALSE, _FALSE);
++
++	return _SUCCESS;
++}
++
++u8 rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
++{
++	u16	mapLen = 0;
++
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);
++
++	if ((addr + cnts) > mapLen)
++		return _FAIL;
++
++	Efuse_PowerSwitch(padapter, _FALSE, _TRUE);
++
++	efuse_ReadEFuse(padapter, EFUSE_WIFI, addr, cnts, data, _FALSE);
++
++	Efuse_PowerSwitch(padapter, _FALSE, _FALSE);
++
++	return _SUCCESS;
++}
++
++u8 rtw_BT_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
++{
++	u16	mapLen = 0;
++
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);
++
++	if ((addr + cnts) > mapLen)
++		return _FAIL;
++
++	Efuse_PowerSwitch(padapter, _FALSE, _TRUE);
++
++	efuse_ReadEFuse(padapter, EFUSE_BT, addr, cnts, data, _FALSE);
++
++	Efuse_PowerSwitch(padapter, _FALSE, _FALSE);
++
++	return _SUCCESS;
++}
++
++/* ------------------------------------------------------------------------------ */
++u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
++{
++#define RT_ASSERT_RET(expr)												\
++	if (!(expr)) {															\
++		printk("Assertion failed! %s at ......\n", #expr);							\
++		printk("      ......%s,%s, line=%d\n",__FILE__, __FUNCTION__, __LINE__);	\
++		return _FAIL;	\
++	}
++
++	u8 *efuse = NULL;
++	u8	offset, word_en;
++	u8	*map = NULL;
++	u8	newdata[PGPKT_DATA_SIZE];
++	s32	i, j, idx, chk_total_byte;
++	u8	ret = _SUCCESS;
++	u16	mapLen = 0, startAddr = 0, efuse_max_available_len = 0;
++	u32	backupRegs[4] = {0};
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	PEFUSE_HAL	pEfuseHal = &pHalData->EfuseHal;
++
++
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_max_available_len, _FALSE);
++
++	if ((addr + cnts) > mapLen)
++		return _FAIL;
++
++	RT_ASSERT_RET(PGPKT_DATA_SIZE == 8); /* have to be 8 byte alignment */
++	RT_ASSERT_RET((mapLen & 0x7) == 0); /* have to be PGPKT_DATA_SIZE alignment for memcpy */
++
++	efuse = rtw_zmalloc(mapLen);
++	if (!efuse)
++		return _FAIL;
++
++	map = rtw_zmalloc(mapLen);
++	if (map == NULL) {
++		rtw_mfree(efuse, mapLen);
++		return _FAIL;
++	}
++
++	_rtw_memset(map, 0xFF, mapLen);
++
++	ret = rtw_efuse_map_read(padapter, 0, mapLen, map);
++	if (ret == _FAIL)
++		goto exit;
++
++	_rtw_memcpy(efuse , map, mapLen);
++	_rtw_memcpy(efuse + addr, data, cnts);
++
++	if (padapter->registrypriv.boffefusemask == 0) {
++		for (i = 0; i < cnts; i++) {
++			if (padapter->registrypriv.bFileMaskEfuse == _TRUE) {
++				if (rtw_file_efuse_IsMasked(padapter, addr + i, maskfileBuffer)) /*use file efuse mask. */
++					efuse[addr + i] = map[addr + i];
++			} else {
++				if (efuse_IsMasked(padapter, addr + i))
++					efuse[addr + i] = map[addr + i];
++			}
++			RTW_INFO("%s , data[%d] = %x, map[addr+i]= %x\n", __func__, addr + i, efuse[ addr + i], map[addr + i]);
++		}
++	}
++	/*Efuse_PowerSwitch(padapter, _TRUE, _TRUE);*/
++
++	chk_total_byte = 0;
++	idx = 0;
++	offset = (addr >> 3);
++
++	while (idx < cnts) {
++		word_en = 0xF;
++		j = (addr + idx) & 0x7;
++		for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {
++			if (efuse[addr + idx] != map[addr + idx])
++				word_en &= ~BIT(i >> 1);
++		}
++
++		if (word_en != 0xF) {
++			chk_total_byte += Efuse_CalculateWordCnts(word_en) * 2;
++
++			if (offset >= EFUSE_MAX_SECTION_BASE) /* Over EFUSE_MAX_SECTION 16 for 2 ByteHeader */
++				chk_total_byte += 2;
++			else
++				chk_total_byte += 1;
++		}
++
++		offset++;
++	}
++
++	RTW_INFO("Total PG bytes Count = %d\n", chk_total_byte);
++	rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr);
++
++	if (startAddr == 0) {
++		startAddr = Efuse_GetCurrentSize(padapter, EFUSE_WIFI, _FALSE);
++		RTW_INFO("%s: Efuse_GetCurrentSize startAddr=%#X\n", __func__, startAddr);
++	}
++	RTW_DBG("%s: startAddr=%#X\n", __func__, startAddr);
++
++	if ((startAddr + chk_total_byte) >= efuse_max_available_len) {
++		RTW_INFO("%s: startAddr(0x%X) + PG data len %d >= efuse_max_available_len(0x%X)\n",
++			 __func__, startAddr, chk_total_byte, efuse_max_available_len);
++		ret = _FAIL;
++		goto exit;
++	}
++
++	efuse_PreUpdateAction(padapter, backupRegs);
++
++	idx = 0;
++	offset = (addr >> 3);
++	while (idx < cnts) {
++		word_en = 0xF;
++		j = (addr + idx) & 0x7;
++		_rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE);
++		for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {
++			if (efuse[addr + idx] != map[addr + idx]) {
++				word_en &= ~BIT(i >> 1);
++				newdata[i] = efuse[addr + idx];
++#ifdef CONFIG_RTL8723B
++				if (addr + idx == 0x8) {
++					if (IS_C_CUT(pHalData->version_id) || IS_B_CUT(pHalData->version_id)) {
++						if (pHalData->adjuseVoltageVal == 6) {
++							newdata[i] = map[addr + idx];
++							RTW_INFO(" %s ,\n adjuseVoltageVal = %d ,newdata[%d] = %x\n", __func__, pHalData->adjuseVoltageVal, i, newdata[i]);
++						}
++					}
++				}
++#endif
++			}
++		}
++
++		if (word_en != 0xF) {
++			ret = Efuse_PgPacketWrite(padapter, offset, word_en, newdata, _FALSE);
++			RTW_INFO("offset=%x\n", offset);
++			RTW_INFO("word_en=%x\n", word_en);
++
++			for (i = 0; i < PGPKT_DATA_SIZE; i++)
++				RTW_INFO("data=%x \t", newdata[i]);
++			if (ret == _FAIL)
++				break;
++		}
++
++		offset++;
++	}
++
++	/*Efuse_PowerSwitch(padapter, _TRUE, _FALSE);*/
++
++	efuse_PostUpdateAction(padapter, backupRegs);
++
++exit:
++
++	rtw_mfree(map, mapLen);
++	rtw_mfree(efuse, mapLen);
++
++	return ret;
++}
++
++
++u8 rtw_BT_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
++{
++#define RT_ASSERT_RET(expr)												\
++	if (!(expr)) {															\
++		printk("Assertion failed! %s at ......\n", #expr);							\
++		printk("      ......%s,%s, line=%d\n",__FILE__, __FUNCTION__, __LINE__);	\
++		return _FAIL;	\
++	}
++
++	u8	offset, word_en;
++	u8	*map;
++	u8	newdata[PGPKT_DATA_SIZE];
++	s32	i = 0, j = 0, idx;
++	u8	ret = _SUCCESS;
++	u16	mapLen = 0;
++
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);
++
++	if ((addr + cnts) > mapLen)
++		return _FAIL;
++
++	RT_ASSERT_RET(PGPKT_DATA_SIZE == 8); /* have to be 8 byte alignment */
++	RT_ASSERT_RET((mapLen & 0x7) == 0); /* have to be PGPKT_DATA_SIZE alignment for memcpy */
++
++	map = rtw_zmalloc(mapLen);
++	if (map == NULL)
++		return _FAIL;
++
++	ret = rtw_BT_efuse_map_read(padapter, 0, mapLen, map);
++	if (ret == _FAIL)
++		goto exit;
++	RTW_INFO("OFFSET\tVALUE(hex)\n");
++	for (i = 0; i < 1024; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */
++		RTW_INFO("0x%03x\t", i);
++		for (j = 0; j < 8; j++)
++			RTW_INFO("%02X ", map[i + j]);
++		RTW_INFO("\t");
++		for (; j < 16; j++)
++			RTW_INFO("%02X ", map[i + j]);
++		RTW_INFO("\n");
++	}
++	RTW_INFO("\n");
++	Efuse_PowerSwitch(padapter, _TRUE, _TRUE);
++
++	idx = 0;
++	offset = (addr >> 3);
++	while (idx < cnts) {
++		word_en = 0xF;
++		j = (addr + idx) & 0x7;
++		_rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE);
++		for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {
++			if (data[idx] != map[addr + idx]) {
++				word_en &= ~BIT(i >> 1);
++				newdata[i] = data[idx];
++			}
++		}
++
++		if (word_en != 0xF) {
++			RTW_INFO("offset=%x\n", offset);
++			RTW_INFO("word_en=%x\n", word_en);
++			RTW_INFO("%s: data=", __FUNCTION__);
++			for (i = 0; i < PGPKT_DATA_SIZE; i++)
++				RTW_INFO("0x%02X ", newdata[i]);
++			RTW_INFO("\n");
++			ret = Efuse_PgPacketWrite_BT(padapter, offset, word_en, newdata, _FALSE);
++			if (ret == _FAIL)
++				break;
++		}
++
++		offset++;
++	}
++
++	Efuse_PowerSwitch(padapter, _TRUE, _FALSE);
++
++exit:
++
++	rtw_mfree(map, mapLen);
++
++	return ret;
++}
++
++/*-----------------------------------------------------------------------------
++ * Function:	Efuse_ReadAllMap
++ *
++ * Overview:	Read All Efuse content
++ *
++ * Input:       NONE
++ *
++ * Output:      NONE
++ *
++ * Return:      NONE
++ *
++ * Revised History:
++ * When			Who		Remark
++ * 11/11/2008	MHC		Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++void
++Efuse_ReadAllMap(
++			PADAPTER	pAdapter,
++			u8		efuseType,
++			u8		*Efuse,
++			BOOLEAN		bPseudoTest);
++void
++Efuse_ReadAllMap(
++			PADAPTER	pAdapter,
++			u8		efuseType,
++			u8		*Efuse,
++			BOOLEAN		bPseudoTest)
++{
++	u16	mapLen = 0;
++
++	Efuse_PowerSwitch(pAdapter, _FALSE, _TRUE);
++
++	EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, bPseudoTest);
++
++	efuse_ReadEFuse(pAdapter, efuseType, 0, mapLen, Efuse, bPseudoTest);
++
++	Efuse_PowerSwitch(pAdapter, _FALSE, _FALSE);
++}
++
++/*-----------------------------------------------------------------------------
++ * Function:	efuse_ShadowWrite1Byte
++ *			efuse_ShadowWrite2Byte
++ *			efuse_ShadowWrite4Byte
++ *
++ * Overview:	Write efuse modify map by one/two/four byte.
++ *
++ * Input:       NONE
++ *
++ * Output:      NONE
++ *
++ * Return:      NONE
++ *
++ * Revised History:
++ * When			Who		Remark
++ * 11/12/2008	MHC		Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++#ifdef PLATFORM
++static void
++efuse_ShadowWrite1Byte(
++		PADAPTER	pAdapter,
++		u16		Offset,
++		u8		Value);
++#endif /* PLATFORM */
++static void
++efuse_ShadowWrite1Byte(
++		PADAPTER	pAdapter,
++		u16		Offset,
++		u8		Value)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
++
++	pHalData->efuse_eeprom_data[Offset] = Value;
++
++}	/* efuse_ShadowWrite1Byte */
++
++/* ---------------Write Two Bytes */
++static void
++efuse_ShadowWrite2Byte(
++		PADAPTER	pAdapter,
++		u16		Offset,
++		u16		Value)
++{
++
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
++
++
++	pHalData->efuse_eeprom_data[Offset] = Value & 0x00FF;
++	pHalData->efuse_eeprom_data[Offset + 1] = Value >> 8;
++
++}	/* efuse_ShadowWrite1Byte */
++
++/* ---------------Write Four Bytes */
++static void
++efuse_ShadowWrite4Byte(
++		PADAPTER	pAdapter,
++		u16		Offset,
++		u32		Value)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
++
++	pHalData->efuse_eeprom_data[Offset] = (u8)(Value & 0x000000FF);
++	pHalData->efuse_eeprom_data[Offset + 1] = (u8)((Value >> 8) & 0x0000FF);
++	pHalData->efuse_eeprom_data[Offset + 2] = (u8)((Value >> 16) & 0x00FF);
++	pHalData->efuse_eeprom_data[Offset + 3] = (u8)((Value >> 24) & 0xFF);
++
++}	/* efuse_ShadowWrite1Byte */
++
++
++/*-----------------------------------------------------------------------------
++ * Function:	EFUSE_ShadowWrite
++ *
++ * Overview:	Write efuse modify map for later update operation to use!!!!!
++ *
++ * Input:       NONE
++ *
++ * Output:      NONE
++ *
++ * Return:      NONE
++ *
++ * Revised History:
++ * When			Who		Remark
++ * 11/12/2008	MHC		Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++void
++EFUSE_ShadowWrite(
++		PADAPTER	pAdapter,
++		u8		Type,
++		u16		Offset,
++		u32		Value);
++void
++EFUSE_ShadowWrite(
++		PADAPTER	pAdapter,
++		u8		Type,
++		u16		Offset,
++		u32		Value)
++{
++#if (MP_DRIVER == 0)
++	return;
++#endif
++	if (pAdapter->registrypriv.mp_mode == 0)
++		return;
++
++
++	if (Type == 1)
++		efuse_ShadowWrite1Byte(pAdapter, Offset, (u8)Value);
++	else if (Type == 2)
++		efuse_ShadowWrite2Byte(pAdapter, Offset, (u16)Value);
++	else if (Type == 4)
++		efuse_ShadowWrite4Byte(pAdapter, Offset, (u32)Value);
++
++}	/* EFUSE_ShadowWrite */
++
++#endif /* !RTW_HALMAC */
++/*-----------------------------------------------------------------------------
++ * Function:	efuse_ShadowRead1Byte
++ *			efuse_ShadowRead2Byte
++ *			efuse_ShadowRead4Byte
++ *
++ * Overview:	Read from efuse init map by one/two/four bytes !!!!!
++ *
++ * Input:       NONE
++ *
++ * Output:      NONE
++ *
++ * Return:      NONE
++ *
++ * Revised History:
++ * When			Who		Remark
++ * 11/12/2008	MHC		Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++static void
++efuse_ShadowRead1Byte(
++		PADAPTER	pAdapter,
++		u16		Offset,
++		u8		*Value)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
++
++	*Value = pHalData->efuse_eeprom_data[Offset];
++
++}	/* EFUSE_ShadowRead1Byte */
++
++/* ---------------Read Two Bytes */
++static void
++efuse_ShadowRead2Byte(
++		PADAPTER	pAdapter,
++		u16		Offset,
++		u16		*Value)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
++
++	*Value = pHalData->efuse_eeprom_data[Offset];
++	*Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8;
++
++}	/* EFUSE_ShadowRead2Byte */
++
++/* ---------------Read Four Bytes */
++static void
++efuse_ShadowRead4Byte(
++		PADAPTER	pAdapter,
++		u16		Offset,
++		u32		*Value)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
++
++	*Value = pHalData->efuse_eeprom_data[Offset];
++	*Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8;
++	*Value |= pHalData->efuse_eeprom_data[Offset + 2] << 16;
++	*Value |= pHalData->efuse_eeprom_data[Offset + 3] << 24;
++
++}	/* efuse_ShadowRead4Byte */
++
++/*-----------------------------------------------------------------------------
++ * Function:	EFUSE_ShadowRead
++ *
++ * Overview:	Read from pHalData->efuse_eeprom_data
++ *---------------------------------------------------------------------------*/
++void
++EFUSE_ShadowRead(
++			PADAPTER	pAdapter,
++			u8		Type,
++			u16		Offset,
++			u32		*Value)
++{
++	if (Type == 1)
++		efuse_ShadowRead1Byte(pAdapter, Offset, (u8 *)Value);
++	else if (Type == 2)
++		efuse_ShadowRead2Byte(pAdapter, Offset, (u16 *)Value);
++	else if (Type == 4)
++		efuse_ShadowRead4Byte(pAdapter, Offset, (u32 *)Value);
++
++}	/* EFUSE_ShadowRead */
++
++/*  11/16/2008 MH Add description. Get current efuse area enabled word!!. */
++u8
++Efuse_CalculateWordCnts(u8	word_en)
++{
++	u8 word_cnts = 0;
++	if (!(word_en & BIT(0)))
++		word_cnts++; /* 0 : write enable */
++	if (!(word_en & BIT(1)))
++		word_cnts++;
++	if (!(word_en & BIT(2)))
++		word_cnts++;
++	if (!(word_en & BIT(3)))
++		word_cnts++;
++	return word_cnts;
++}
++
++/*-----------------------------------------------------------------------------
++ * Function:	efuse_WordEnableDataRead
++ *
++ * Overview:	Read allowed word in current efuse section data.
++ *
++ * Input:       NONE
++ *
++ * Output:      NONE
++ *
++ * Return:      NONE
++ *
++ * Revised History:
++ * When			Who		Remark
++ * 11/16/2008	MHC		Create Version 0.
++ * 11/21/2008	MHC		Fix Write bug when we only enable late word.
++ *
++ *---------------------------------------------------------------------------*/
++void
++efuse_WordEnableDataRead(u8	word_en,
++				u8	*sourdata,
++				u8	*targetdata)
++{
++	if (!(word_en & BIT(0))) {
++		targetdata[0] = sourdata[0];
++		targetdata[1] = sourdata[1];
++	}
++	if (!(word_en & BIT(1))) {
++		targetdata[2] = sourdata[2];
++		targetdata[3] = sourdata[3];
++	}
++	if (!(word_en & BIT(2))) {
++		targetdata[4] = sourdata[4];
++		targetdata[5] = sourdata[5];
++	}
++	if (!(word_en & BIT(3))) {
++		targetdata[6] = sourdata[6];
++		targetdata[7] = sourdata[7];
++	}
++}
++
++/*-----------------------------------------------------------------------------
++ * Function:	EFUSE_ShadowMapUpdate
++ *
++ * Overview:	Transfer current EFUSE content to shadow init and modify map.
++ *
++ * Input:       NONE
++ *
++ * Output:      NONE
++ *
++ * Return:      NONE
++ *
++ * Revised History:
++ * When			Who		Remark
++ * 11/13/2008	MHC		Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++void EFUSE_ShadowMapUpdate(
++	PADAPTER	pAdapter,
++	u8		efuseType,
++	BOOLEAN	bPseudoTest)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
++	u16	mapLen = 0;
++#ifdef RTW_HALMAC
++	u8 *efuse_map = NULL;
++	int err;
++
++
++	mapLen = EEPROM_MAX_SIZE;
++	efuse_map = pHalData->efuse_eeprom_data;
++	/* efuse default content is 0xFF */
++	_rtw_memset(efuse_map, 0xFF, EEPROM_MAX_SIZE);
++
++	EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, bPseudoTest);
++	if (!mapLen) {
++		RTW_WARN("%s: <ERROR> fail to get efuse size!\n", __FUNCTION__);
++		mapLen = EEPROM_MAX_SIZE;
++	}
++	if (mapLen > EEPROM_MAX_SIZE) {
++		RTW_WARN("%s: <ERROR> size of efuse data(%d) is large than expected(%d)!\n",
++			 __FUNCTION__, mapLen, EEPROM_MAX_SIZE);
++		mapLen = EEPROM_MAX_SIZE;
++	}
++
++	if (pHalData->bautoload_fail_flag == _FALSE) {
++		err = rtw_halmac_read_logical_efuse_map(adapter_to_dvobj(pAdapter), efuse_map, mapLen, NULL, 0);
++		if (err)
++			RTW_ERR("%s: <ERROR> fail to get efuse map!\n", __FUNCTION__);
++	}
++#else /* !RTW_HALMAC */
++	EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, bPseudoTest);
++
++	if (pHalData->bautoload_fail_flag == _TRUE)
++		_rtw_memset(pHalData->efuse_eeprom_data, 0xFF, mapLen);
++	else {
++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
++		if (_SUCCESS != retriveAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pHalData->efuse_eeprom_data)) {
++#endif
++
++			Efuse_ReadAllMap(pAdapter, efuseType, pHalData->efuse_eeprom_data, bPseudoTest);
++
++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
++			storeAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pHalData->efuse_eeprom_data);
++		}
++#endif
++	}
++
++	/* PlatformMoveMemory((void *)&pHalData->EfuseMap[EFUSE_MODIFY_MAP][0], */
++	/* (void *)&pHalData->EfuseMap[EFUSE_INIT_MAP][0], mapLen); */
++#endif /* !RTW_HALMAC */
++
++	rtw_mask_map_read(pAdapter, 0x00, mapLen, pHalData->efuse_eeprom_data);
++
++	rtw_dump_cur_efuse(pAdapter);
++} /* EFUSE_ShadowMapUpdate */
++
++const u8 _mac_hidden_max_bw_to_hal_bw_cap[MAC_HIDDEN_MAX_BW_NUM] = {
++	0,
++	0,
++	(BW_CAP_160M | BW_CAP_80M | BW_CAP_40M | BW_CAP_20M | BW_CAP_10M | BW_CAP_5M),
++	(BW_CAP_5M),
++	(BW_CAP_10M | BW_CAP_5M),
++	(BW_CAP_20M | BW_CAP_10M | BW_CAP_5M),
++	(BW_CAP_40M | BW_CAP_20M | BW_CAP_10M | BW_CAP_5M),
++	(BW_CAP_80M | BW_CAP_40M | BW_CAP_20M | BW_CAP_10M | BW_CAP_5M),
++};
++
++const u8 _mac_hidden_proto_to_hal_proto_cap[MAC_HIDDEN_PROTOCOL_NUM] = {
++	0,
++	0,
++	(PROTO_CAP_11N | PROTO_CAP_11G | PROTO_CAP_11B),
++	(PROTO_CAP_11AC | PROTO_CAP_11N | PROTO_CAP_11G | PROTO_CAP_11B),
++};
++
++u8 mac_hidden_wl_func_to_hal_wl_func(u8 func)
++{
++	u8 wl_func = 0;
++
++	if (func & BIT0)
++		wl_func |= WL_FUNC_MIRACAST;
++	if (func & BIT1)
++		wl_func |= WL_FUNC_P2P;
++	if (func & BIT2)
++		wl_func |= WL_FUNC_TDLS;
++	if (func & BIT3)
++		wl_func |= WL_FUNC_FTM;
++
++	return wl_func;
++}
++
++#ifdef PLATFORM_LINUX
++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
++/* #include <rtw_eeprom.h> */
++
++int isAdaptorInfoFileValid(void)
++{
++	return _TRUE;
++}
++
++int storeAdaptorInfoFile(char *path, u8 *efuse_data)
++{
++	int ret = _SUCCESS;
++
++	if (path && efuse_data) {
++		ret = rtw_store_to_file(path, efuse_data, EEPROM_MAX_SIZE_512);
++		if (ret == EEPROM_MAX_SIZE)
++			ret = _SUCCESS;
++		else
++			ret = _FAIL;
++	} else {
++		RTW_INFO("%s NULL pointer\n", __FUNCTION__);
++		ret =  _FAIL;
++	}
++	return ret;
++}
++
++int retriveAdaptorInfoFile(char *path, u8 *efuse_data)
++{
++	int ret = _SUCCESS;
++	mm_segment_t oldfs;
++	struct file *fp;
++
++	if (path && efuse_data) {
++
++		ret = rtw_retrieve_from_file(path, efuse_data, EEPROM_MAX_SIZE);
++
++		if (ret == EEPROM_MAX_SIZE)
++			ret = _SUCCESS;
++		else
++			ret = _FAIL;
++
++#if 0
++		if (isAdaptorInfoFileValid())
++			return 0;
++		else
++			return _FAIL;
++#endif
++
++	} else {
++		RTW_INFO("%s NULL pointer\n", __FUNCTION__);
++		ret = _FAIL;
++	}
++	return ret;
++}
++#endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */
++
++u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepath, u8 *buf, u32 len)
++{
++	char *ptmpbuf = NULL, *ptr;
++	u8 val8;
++	u32 count, i, j;
++	int err;
++	u32 bufsize = 4096;
++
++	ptmpbuf = rtw_zmalloc(bufsize);
++	if (ptmpbuf == NULL)
++		return _FALSE;
++
++	count = rtw_retrieve_from_file(filepath, ptmpbuf, bufsize);
++	if (count <= 90) {
++		rtw_mfree(ptmpbuf, bufsize);
++		RTW_ERR("%s, filepatch %s, size=%d, FAIL!!\n", __FUNCTION__, filepath, count);
++		return _FALSE;
++	}
++	i = 0;
++	j = 0;
++	ptr = ptmpbuf;
++	while ((j < len) && (i < count)) {
++		if (ptmpbuf[i] == '\0')
++			break;
++		ptr = strpbrk(&ptmpbuf[i], " \t\n\r");
++		if (ptr) {
++			if (ptr == &ptmpbuf[i]) {
++				i++;
++				continue;
++			}
++			/* Add string terminating null */
++			*ptr = 0;
++		} else {
++			ptr = &ptmpbuf[count-1];
++		}
++
++		err = sscanf(&ptmpbuf[i], "%hhx", &val8);
++		if (err != 1) {
++			RTW_WARN("Something wrong to parse efuse file, string=%s\n", &ptmpbuf[i]);
++		} else {
++			buf[j] = val8;
++			RTW_DBG("i=%d, j=%d, 0x%02x\n", i, j, buf[j]);
++			j++;
++		}
++		i = ptr - ptmpbuf + 1;
++	}
++	rtw_mfree(ptmpbuf, bufsize);
++	RTW_INFO("%s, filepatch %s, size=%d, done\n", __FUNCTION__, filepath, count);
++	return _TRUE;
++}
++
++
++u8 rtw_efuse_file_store(PADAPTER padapter, u8 *filepath, u8 *buf, u32 len)
++{
++	int err = 0, i = 0, j = 0, mapLen = 0 ;
++	char *cbuf, *pchr;
++
++	cbuf = rtw_zmalloc(len * 3);
++	pchr = cbuf;
++
++	if (filepath && buf) {
++		if (cbuf == NULL) {
++			RTW_INFO("%s, malloc cbuf _FAIL\n", __FUNCTION__);
++			err = _FAIL;
++		} else {
++			for (i = 0; i <= len; i += 16) {
++				for (j = 0; j < 16; j++)
++					pchr += sprintf(pchr, "%02X ", buf[i + j]);
++				pchr += sprintf(pchr, "\n");
++			}
++
++			err = rtw_store_to_file(filepath, cbuf, strlen(cbuf));
++			RTW_INFO("%s, rtw_store_to_file len=%d,err =%d, len(cbuf)=%zd\n", __FUNCTION__, len, err, strlen(cbuf));
++			if (err == strlen(cbuf)) {
++				err = _SUCCESS;
++				RTW_INFO("%s, filepatch %s, len=%d, done\n", __FUNCTION__, filepath, len);
++			} else {
++				err = _FAIL;
++				RTW_INFO("%s, filepatch %s, len=%d,err =%d, _FAIL\n", __FUNCTION__, filepath, len, err);
++			}
++		}
++	}
++	if (cbuf)
++		rtw_mfree(cbuf, len * 3);
++
++	return err;
++}
++
++#ifdef CONFIG_EFUSE_CONFIG_FILE
++u32 rtw_read_efuse_from_file(const char *path, u8 *buf, int map_size)
++{
++	u32 i;
++	u8 c;
++	u8 temp[3];
++	u8 temp_i;
++	u8 end = _FALSE;
++	u32 ret = _FAIL;
++
++	u8 *file_data = NULL;
++	u32 file_size, read_size, pos = 0;
++	u8 *map = NULL;
++
++	if (rtw_is_file_readable_with_size(path, &file_size) != _TRUE) {
++		RTW_PRINT("%s %s is not readable\n", __func__, path);
++		goto exit;
++	}
++
++	file_data = rtw_vmalloc(file_size);
++	if (!file_data) {
++		RTW_ERR("%s rtw_vmalloc(%d) fail\n", __func__, file_size);
++		goto exit;
++	}
++
++	read_size = rtw_retrieve_from_file(path, file_data, file_size);
++	if (read_size == 0) {
++		RTW_ERR("%s read from %s fail\n", __func__, path);
++		goto exit;
++	}
++
++	map = rtw_vmalloc(map_size);
++	if (!map) {
++		RTW_ERR("%s rtw_vmalloc(%d) fail\n", __func__, map_size);
++		goto exit;
++	}
++	_rtw_memset(map, 0xff, map_size);
++
++	temp[2] = 0; /* end of string '\0' */
++
++	for (i = 0 ; i < map_size ; i++) {
++		temp_i = 0;
++
++		while (1) {
++			if (pos >= read_size) {
++				end = _TRUE;
++				break;
++			}
++			c = file_data[pos++];
++
++			/* bypass spece or eol or null before first hex digit */
++			if (temp_i == 0 && (is_eol(c) == _TRUE || is_space(c) == _TRUE || is_null(c) == _TRUE))
++				continue;
++
++			if (IsHexDigit(c) == _FALSE) {
++				RTW_ERR("%s invalid 8-bit hex format for offset:0x%03x\n", __func__, i);
++				goto exit;
++			}
++
++			temp[temp_i++] = c;
++
++			if (temp_i == 2) {
++				/* parse value */
++				if (sscanf(temp, "%hhx", &map[i]) != 1) {
++					RTW_ERR("%s sscanf fail for offset:0x%03x\n", __func__, i);
++					goto exit;
++				}
++				break;
++			}
++		}
++
++		if (end == _TRUE) {
++			if (temp_i != 0) {
++				RTW_ERR("%s incomplete 8-bit hex format for offset:0x%03x\n", __func__, i);
++				goto exit;
++			}
++			break;
++		}
++	}
++
++	RTW_PRINT("efuse file:%s, 0x%03x byte content read\n", path, i);
++
++	_rtw_memcpy(buf, map, map_size);
++
++	ret = _SUCCESS;
++
++exit:
++	if (file_data)
++		rtw_vmfree(file_data, file_size);
++	if (map)
++		rtw_vmfree(map, map_size);
++
++	return ret;
++}
++
++u32 rtw_read_macaddr_from_file(const char *path, u8 *buf)
++{
++	u32 i;
++	u8 temp[3];
++	u32 ret = _FAIL;
++
++	u8 file_data[17];
++	u32 read_size;
++	u8 addr[ETH_ALEN];
++
++	if (rtw_is_file_readable(path) != _TRUE) {
++		RTW_PRINT("%s %s is not readable\n", __func__, path);
++		goto exit;
++	}
++
++	read_size = rtw_retrieve_from_file(path, file_data, 17);
++	if (read_size != 17) {
++		RTW_ERR("%s read from %s fail\n", __func__, path);
++		goto exit;
++	}
++
++	temp[2] = 0; /* end of string '\0' */
++
++	for (i = 0 ; i < ETH_ALEN ; i++) {
++		if (IsHexDigit(file_data[i * 3]) == _FALSE || IsHexDigit(file_data[i * 3 + 1]) == _FALSE) {
++			RTW_ERR("%s invalid 8-bit hex format for address offset:%u\n", __func__, i);
++			goto exit;
++		}
++
++		if (i < ETH_ALEN - 1 && file_data[i * 3 + 2] != ':') {
++			RTW_ERR("%s invalid separator after address offset:%u\n", __func__, i);
++			goto exit;
++		}
++
++		temp[0] = file_data[i * 3];
++		temp[1] = file_data[i * 3 + 1];
++		if (sscanf(temp, "%hhx", &addr[i]) != 1) {
++			RTW_ERR("%s sscanf fail for address offset:0x%03x\n", __func__, i);
++			goto exit;
++		}
++	}
++
++	_rtw_memcpy(buf, addr, ETH_ALEN);
++
++	RTW_PRINT("wifi_mac file: %s\n", path);
++#ifdef CONFIG_RTW_DEBUG
++	RTW_INFO(MAC_FMT"\n", MAC_ARG(buf));
++#endif
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++#endif /* CONFIG_EFUSE_CONFIG_FILE */
++
++#endif /* PLATFORM_LINUX */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh.c
+new file mode 100644
+index 000000000..a7f553119
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh.c
+@@ -0,0 +1,4392 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_MESH_C_
++
++#ifdef CONFIG_RTW_MESH
++#include <drv_types.h>
++
++const char *_rtw_mesh_plink_str[] = {
++	"UNKNOWN",
++	"LISTEN",
++	"OPN_SNT",
++	"OPN_RCVD",
++	"CNF_RCVD",
++	"ESTAB",
++	"HOLDING",
++	"BLOCKED",
++};
++
++const char *_rtw_mesh_ps_str[] = {
++	"UNKNOWN",
++	"ACTIVE",
++	"LSLEEP",
++	"DSLEEP",
++};
++
++const char *_action_self_protected_str[] = {
++	"ACT_SELF_PROTECTED_RSVD",
++	"MESH_OPEN",
++	"MESH_CONF",
++	"MESH_CLOSE",
++	"MESH_GK_INFORM",
++	"MESH_GK_ACK",
++};
++
++inline u8 *rtw_set_ie_mesh_id(u8 *buf, u32 *buf_len, const char *mesh_id, u8 id_len)
++{
++	return rtw_set_ie(buf, WLAN_EID_MESH_ID, id_len, mesh_id, buf_len);
++}
++
++inline u8 *rtw_set_ie_mesh_config(u8 *buf, u32 *buf_len
++	, u8 path_sel_proto, u8 path_sel_metric, u8 congest_ctl_mode, u8 sync_method, u8 auth_proto
++	, u8 num_of_peerings, bool cto_mgate, bool cto_as
++	, bool accept_peerings, bool mcca_sup, bool mcca_en, bool forwarding
++	, bool mbca_en, bool tbtt_adj, bool ps_level)
++{
++
++	u8 conf[7] = {0};
++
++	SET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(conf, path_sel_proto);
++	SET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(conf, path_sel_metric);
++	SET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(conf, congest_ctl_mode);
++	SET_MESH_CONF_ELE_SYNC_METHOD_ID(conf, sync_method);
++	SET_MESH_CONF_ELE_AUTH_PROTO_ID(conf, auth_proto);
++
++	SET_MESH_CONF_ELE_CTO_MGATE(conf, cto_mgate);
++	SET_MESH_CONF_ELE_NUM_OF_PEERINGS(conf, num_of_peerings);
++	SET_MESH_CONF_ELE_CTO_AS(conf, cto_as);
++
++	SET_MESH_CONF_ELE_ACCEPT_PEERINGS(conf, accept_peerings);
++	SET_MESH_CONF_ELE_MCCA_SUP(conf, mcca_sup);
++	SET_MESH_CONF_ELE_MCCA_EN(conf, mcca_en);
++	SET_MESH_CONF_ELE_FORWARDING(conf, forwarding);
++	SET_MESH_CONF_ELE_MBCA_EN(conf, mbca_en);
++	SET_MESH_CONF_ELE_TBTT_ADJ(conf, tbtt_adj);
++	SET_MESH_CONF_ELE_PS_LEVEL(conf, ps_level);
++
++	return rtw_set_ie(buf, WLAN_EID_MESH_CONFIG, 7, conf, buf_len);
++}
++
++inline u8 *rtw_set_ie_mpm(u8 *buf, u32 *buf_len
++	, u8 proto_id, u16 llid, u16 *plid, u16 *reason, u8 *chosen_pmk)
++{
++	u8 data[24] = {0};
++	u8 *pos = data;
++
++	RTW_PUT_LE16(pos, proto_id);
++	pos += 2;
++
++	RTW_PUT_LE16(pos, llid);
++	pos += 2;
++
++	if (plid) {
++		RTW_PUT_LE16(pos, *plid);
++		pos += 2;
++	}
++
++	if (reason) {
++		RTW_PUT_LE16(pos, *reason);
++		pos += 2;
++	}
++
++	if (chosen_pmk) {
++		_rtw_memcpy(pos, chosen_pmk, 16);
++		pos += 16;
++	}
++
++	return rtw_set_ie(buf, WLAN_EID_MPM, pos - data, data, buf_len);
++}
++
++bool rtw_bss_is_forwarding(WLAN_BSSID_EX *bss)
++{
++	u8 *ie;
++	int ie_len;
++	bool ret = 0;
++
++	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
++			BSS_EX_TLV_IES_LEN(bss));
++	if (!ie || ie_len != 7)
++		goto exit;
++
++	ret = GET_MESH_CONF_ELE_FORWARDING(ie + 2);
++
++exit:
++	return ret;
++}
++
++bool rtw_bss_is_cto_mgate(WLAN_BSSID_EX *bss)
++{
++	u8 *ie;
++	int ie_len;
++	bool ret = 0;
++
++	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
++			BSS_EX_TLV_IES_LEN(bss));
++	if (!ie || ie_len != 7)
++		goto exit;
++
++	ret = GET_MESH_CONF_ELE_CTO_MGATE(ie + 2);
++
++exit:
++	return ret;
++}
++
++int _rtw_bss_is_same_mbss(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b, u8 **a_mconf_ie_r, u8 **b_mconf_ie_r)
++{
++	int ret = 0;
++	u8 *a_mconf_ie, *b_mconf_ie;
++	sint a_mconf_ie_len, b_mconf_ie_len;
++
++	if (a->InfrastructureMode != Ndis802_11_mesh)
++		goto exit;
++	a_mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(a), WLAN_EID_MESH_CONFIG, &a_mconf_ie_len, BSS_EX_TLV_IES_LEN(a));
++	if (!a_mconf_ie || a_mconf_ie_len != 7)
++		goto exit;
++	if (a_mconf_ie_r)
++		*a_mconf_ie_r = a_mconf_ie;
++
++	if (b->InfrastructureMode != Ndis802_11_mesh)
++		goto exit;
++	b_mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(b), WLAN_EID_MESH_CONFIG, &b_mconf_ie_len, BSS_EX_TLV_IES_LEN(b));
++	if (!b_mconf_ie || b_mconf_ie_len != 7)
++		goto exit;
++	if (b_mconf_ie_r)
++		*b_mconf_ie_r = b_mconf_ie;
++
++	if (a->mesh_id.SsidLength != b->mesh_id.SsidLength
++		|| _rtw_memcmp(a->mesh_id.Ssid, b->mesh_id.Ssid, a->mesh_id.SsidLength) == _FALSE)
++		goto exit;
++
++	if (_rtw_memcmp(a_mconf_ie + 2, b_mconf_ie + 2, 5) == _FALSE)
++		goto exit;
++
++	ret = 1;
++
++exit:
++	return ret;
++}
++
++int rtw_bss_is_same_mbss(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b)
++{
++	return _rtw_bss_is_same_mbss(a, b, NULL, NULL);
++}
++
++int rtw_bss_is_candidate_mesh_peer(_adapter *adapter, WLAN_BSSID_EX *target, u8 ch, u8 add_peer)
++{
++	int ret = 0;
++	WLAN_BSSID_EX *self = &adapter->mlmepriv.cur_network.network;
++	u8 *s_mconf_ie, *t_mconf_ie;
++	u8 auth_pid;
++	int i, j;
++
++	if (ch && self->Configuration.DSConfig != target->Configuration.DSConfig)
++		goto exit;
++
++	if (!_rtw_bss_is_same_mbss(self, target, &s_mconf_ie, &t_mconf_ie))
++		goto exit;
++
++	if (add_peer) {
++		/* Accept additional mesh peerings */
++		if (GET_MESH_CONF_ELE_ACCEPT_PEERINGS(t_mconf_ie + 2) == 0)
++			goto exit;
++	}
++
++	/* BSSBasicRateSet */
++	for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
++		if (target->SupportedRates[i] == 0)
++			break;	
++		if (target->SupportedRates[i] & 0x80) {
++			u8 match = 0;
++
++			if (!ch) {
++				/* off-channel, check target with our hardcode capability */
++				if (target->Configuration.DSConfig > 14)
++					match = rtw_is_basic_rate_ofdm(target->SupportedRates[i]);
++				else
++					match = rtw_is_basic_rate_mix(target->SupportedRates[i]);
++			} else { 
++				for (j = 0; j < NDIS_802_11_LENGTH_RATES_EX; j++) {
++					if (self->SupportedRates[j] == 0)
++						break;
++					if (self->SupportedRates[j] == target->SupportedRates[i]) {
++						match = 1;
++						break;
++					}
++				}
++			}
++			if (!match)
++				goto exit;
++		}
++	}
++
++	/* BSSBasicMCSSet */
++
++
++	auth_pid = GET_MESH_CONF_ELE_AUTH_PROTO_ID(s_mconf_ie + 2);
++	if (auth_pid && auth_pid <= 2) {
++		struct security_priv *sec = &adapter->securitypriv;
++		u8 *rsn_ie;
++		int rsn_ie_len;
++		int group_cipher = 0, pairwise_cipher = 0, gmcs = 0;
++		u8 mfp_opt = MFP_NO;
++
++		/* 802.1X connected to AS ? */
++
++		/* RSN */
++		rsn_ie = rtw_get_wpa2_ie(BSS_EX_TLV_IES(target), &rsn_ie_len, BSS_EX_TLV_IES_LEN(target));
++		if (!rsn_ie || rsn_ie_len == 0)
++			goto exit;
++		if (rtw_parse_wpa2_ie(rsn_ie, rsn_ie_len + 2, &group_cipher, &pairwise_cipher, &gmcs, NULL, &mfp_opt) != _SUCCESS)
++			goto exit;
++		if ((sec->mfp_opt == MFP_REQUIRED && mfp_opt < MFP_OPTIONAL)
++			|| (mfp_opt == MFP_REQUIRED && sec->mfp_opt < MFP_OPTIONAL))
++			goto exit;
++		if (!(sec->wpa2_group_cipher & group_cipher))
++			goto exit;
++		if (!(sec->wpa2_pairwise_cipher & pairwise_cipher))
++			goto exit;
++		#ifdef CONFIG_IEEE80211W
++		if ((sec->mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL)
++			&& security_type_bip_to_gmcs(sec->dot11wCipher) != gmcs)
++			goto exit;
++		#endif
++	}
++
++	ret = 1;
++
++exit:
++	return ret;
++}
++
++void rtw_mesh_bss_peering_status(WLAN_BSSID_EX *bss, u8 *nop, u8 *accept)
++{
++	u8 *ie;
++	int ie_len;
++
++	if (nop)
++		*nop = 0;
++	if (accept)
++		*accept = 0;
++
++	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
++			BSS_EX_TLV_IES_LEN(bss));
++	if (!ie || ie_len != 7)
++		goto exit;
++
++	if (nop)
++		*nop = GET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2);
++	if (accept)
++		*accept = GET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2);
++
++exit:
++	return;
++}
++
++#if CONFIG_RTW_MESH_ACNODE_PREVENT
++void rtw_mesh_update_scanned_acnode_status(_adapter *adapter, struct wlan_network *scanned)
++{
++	bool acnode;
++	u8 nop, accept;
++
++	rtw_mesh_bss_peering_status(&scanned->network, &nop, &accept);
++
++	acnode = !nop && accept;
++
++	if (acnode && scanned->acnode_stime == 0) {
++		scanned->acnode_stime = rtw_get_current_time();
++		if (scanned->acnode_stime == 0)
++			scanned->acnode_stime++;
++	} else if (!acnode) {
++		scanned->acnode_stime = 0;
++		scanned->acnode_notify_etime = 0;
++	}
++}
++
++bool rtw_mesh_scanned_is_acnode_confirmed(_adapter *adapter, struct wlan_network *scanned)
++{
++	return scanned->acnode_stime
++			&& rtw_get_passing_time_ms(scanned->acnode_stime)
++				> adapter->mesh_cfg.peer_sel_policy.acnode_conf_timeout_ms;
++}
++
++static bool rtw_mesh_scanned_is_acnode_allow_notify(_adapter *adapter, struct wlan_network *scanned)
++{
++	return scanned->acnode_notify_etime
++			&& rtw_time_after(scanned->acnode_notify_etime, rtw_get_current_time());
++}
++
++bool rtw_mesh_acnode_prevent_allow_sacrifice(_adapter *adapter)
++{
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	struct sta_priv *stapriv = &adapter->stapriv;
++	bool allow = 0;
++
++	if (!mcfg->peer_sel_policy.acnode_prevent
++		|| mcfg->max_peer_links <= 1
++		|| stapriv->asoc_list_cnt < mcfg->max_peer_links)
++		goto exit;
++
++#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++	if (rtw_mesh_cto_mgate_required(adapter))
++		goto exit;
++#endif
++
++	allow = 1;
++
++exit:
++	return allow;
++}
++
++static bool rtw_mesh_acnode_candidate_exist(_adapter *adapter)
++{
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++	_queue *queue = &(mlme->scanned_queue);
++	_list *head, *list;
++	_irqL irqL;
++	struct wlan_network *scanned = NULL;
++	struct sta_info *sta = NULL;
++	bool need = 0;
++
++	_enter_critical_bh(&(mlme->scanned_queue.lock), &irqL);
++
++	head = get_list_head(queue);
++	list = get_next(head);
++	while (!rtw_end_of_queue_search(head, list)) {
++		scanned = LIST_CONTAINOR(list, struct wlan_network, list);
++		list = get_next(list);
++
++		if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms
++			&& rtw_mesh_scanned_is_acnode_confirmed(adapter, scanned)
++			&& (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi)
++			#if CONFIG_RTW_MACADDR_ACL
++			&& rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE
++			#endif
++			&& rtw_bss_is_candidate_mesh_peer(adapter, &scanned->network, 1, 1)
++			#if CONFIG_RTW_MESH_PEER_BLACKLIST
++			&& !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)
++			#endif
++			#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++			&& rtw_mesh_cto_mgate_network_filter(adapter, scanned)
++			#endif
++		) {
++			need = 1;
++			break;
++		}
++	}
++
++	_exit_critical_bh(&(mlme->scanned_queue.lock), &irqL);
++
++	return need;
++}
++
++static int rtw_mesh_acnode_prevent_sacrifice_chk(_adapter *adapter, struct sta_info **sac, struct sta_info *com)
++{
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	int updated = 0;
++
++	/*
++	* TODO: compare next_hop reference cnt of forwarding info
++	* don't sacrifice working next_hop or choose sta with least cnt
++	*/
++
++	if (*sac == NULL) {
++		updated = 1;
++		goto exit;
++	}
++
++#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++	if (mcfg->peer_sel_policy.cto_mgate_require
++		&& !mcfg->dot11MeshGateAnnouncementProtocol
++	) {
++		if (IS_CTO_MGATE_CONF_TIMEOUT(com->plink)) {
++			if (!IS_CTO_MGATE_CONF_TIMEOUT((*sac)->plink)) {
++				/* blacklist > not blacklist */
++				updated = 1;
++				goto exit;
++			}
++		} else if (!IS_CTO_MGATE_CONF_DISABLED(com->plink)) {
++			if (IS_CTO_MGATE_CONF_DISABLED((*sac)->plink)) {
++				/* confirming > disabled */
++				updated = 1;
++				goto exit;
++			}
++		}
++	}
++#endif
++
++exit:
++	if (updated)
++		*sac = com;
++
++	return updated;
++}
++
++struct sta_info *_rtw_mesh_acnode_prevent_pick_sacrifice(_adapter *adapter)
++{
++	struct sta_priv *stapriv = &adapter->stapriv;
++	_list *head, *list;
++	struct sta_info *sta, *sacrifice = NULL;
++	u8 nop;
++
++	head = &stapriv->asoc_list;
++	list = get_next(head);
++	while (rtw_end_of_queue_search(head, list) == _FALSE) {
++		sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
++		list = get_next(list);
++
++		if (!sta->plink || !sta->plink->scanned) {
++			rtw_warn_on(1);
++			continue;
++		}
++
++		rtw_mesh_bss_peering_status(&sta->plink->scanned->network, &nop, NULL);
++		if (nop < 2)
++			continue;
++
++		rtw_mesh_acnode_prevent_sacrifice_chk(adapter, &sacrifice, sta);
++	}
++
++	return sacrifice;
++}
++
++struct sta_info *rtw_mesh_acnode_prevent_pick_sacrifice(_adapter *adapter)
++{
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct sta_info *sacrifice = NULL;
++
++	enter_critical_bh(&stapriv->asoc_list_lock);
++
++	sacrifice = _rtw_mesh_acnode_prevent_pick_sacrifice(adapter);
++
++	exit_critical_bh(&stapriv->asoc_list_lock);
++
++	return sacrifice;
++}
++
++static void rtw_mesh_acnode_rsvd_chk(_adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	u8 acnode_rsvd = 0;
++
++	if (rtw_mesh_acnode_prevent_allow_sacrifice(adapter)
++		&& rtw_mesh_acnode_prevent_pick_sacrifice(adapter)
++		&& rtw_mesh_acnode_candidate_exist(adapter))
++		acnode_rsvd = 1;
++
++	if (plink_ctl->acnode_rsvd != acnode_rsvd) {
++		plink_ctl->acnode_rsvd = acnode_rsvd;
++		RTW_INFO(FUNC_ADPT_FMT" acnode_rsvd = %d\n", FUNC_ADPT_ARG(adapter), plink_ctl->acnode_rsvd);
++		update_beacon(adapter, WLAN_EID_MESH_CONFIG, NULL, 1, 0);
++	}
++}
++
++static void rtw_mesh_acnode_set_notify_etime(_adapter *adapter, u8 *rframe_whdr)
++{
++	if (adapter->mesh_info.plink_ctl.acnode_rsvd) {
++		struct wlan_network *scanned = rtw_find_network(&adapter->mlmepriv.scanned_queue, get_addr2_ptr(rframe_whdr));
++
++		if (rtw_mesh_scanned_is_acnode_confirmed(adapter, scanned)) {
++			scanned->acnode_notify_etime = rtw_get_current_time()
++				+ rtw_ms_to_systime(adapter->mesh_cfg.peer_sel_policy.acnode_notify_timeout_ms);
++			if (scanned->acnode_notify_etime == 0)
++				scanned->acnode_notify_etime++;
++		}
++	}
++}
++
++void dump_mesh_acnode_prevent_settings(void *sel, _adapter *adapter)
++{
++	struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
++
++	RTW_PRINT_SEL(sel, "%-6s %-12s %-14s\n"
++		, "enable", "conf_timeout", "nofity_timeout");
++	RTW_PRINT_SEL(sel, "%6u %12u %14u\n"
++		, peer_sel_policy->acnode_prevent
++		, peer_sel_policy->acnode_conf_timeout_ms
++		, peer_sel_policy->acnode_notify_timeout_ms);
++}
++#endif /* CONFIG_RTW_MESH_ACNODE_PREVENT */
++
++#if CONFIG_RTW_MESH_PEER_BLACKLIST
++int rtw_mesh_peer_blacklist_add(_adapter *adapter, const u8 *addr)
++{
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++
++	return rtw_blacklist_add(&plink_ctl->peer_blacklist, addr
++		, mcfg->peer_sel_policy.peer_blacklist_timeout_ms);
++}
++
++int rtw_mesh_peer_blacklist_del(_adapter *adapter, const u8 *addr)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++
++	return rtw_blacklist_del(&plink_ctl->peer_blacklist, addr);
++}
++
++int rtw_mesh_peer_blacklist_search(_adapter *adapter, const u8 *addr)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++
++	return rtw_blacklist_search(&plink_ctl->peer_blacklist, addr);
++}
++
++void rtw_mesh_peer_blacklist_flush(_adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++
++	rtw_blacklist_flush(&plink_ctl->peer_blacklist);
++}
++
++void dump_mesh_peer_blacklist(void *sel, _adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++
++	dump_blacklist(sel, &plink_ctl->peer_blacklist, "blacklist");
++}
++
++void dump_mesh_peer_blacklist_settings(void *sel, _adapter *adapter)
++{
++	struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
++
++	RTW_PRINT_SEL(sel, "%-12s %-17s\n"
++		, "conf_timeout", "blacklist_timeout");
++	RTW_PRINT_SEL(sel, "%12u %17u\n"
++		, peer_sel_policy->peer_conf_timeout_ms
++		, peer_sel_policy->peer_blacklist_timeout_ms);
++}
++#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */
++
++#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++u8 rtw_mesh_cto_mgate_required(_adapter *adapter)
++{
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++
++	return mcfg->peer_sel_policy.cto_mgate_require
++		&& !rtw_bss_is_cto_mgate(&(mlmeext->mlmext_info.network));
++}
++
++u8 rtw_mesh_cto_mgate_network_filter(_adapter *adapter, struct wlan_network *scanned)
++{
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++
++	return !rtw_mesh_cto_mgate_required(adapter)
++			|| (rtw_bss_is_cto_mgate(&scanned->network)
++				&& !rtw_mesh_cto_mgate_blacklist_search(adapter, scanned->network.MacAddress));
++}
++
++int rtw_mesh_cto_mgate_blacklist_add(_adapter *adapter, const u8 *addr)
++{
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++
++	return rtw_blacklist_add(&plink_ctl->cto_mgate_blacklist, addr
++		, mcfg->peer_sel_policy.cto_mgate_blacklist_timeout_ms);
++}
++
++int rtw_mesh_cto_mgate_blacklist_del(_adapter *adapter, const u8 *addr)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++
++	return rtw_blacklist_del(&plink_ctl->cto_mgate_blacklist, addr);
++}
++
++int rtw_mesh_cto_mgate_blacklist_search(_adapter *adapter, const u8 *addr)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++
++	return rtw_blacklist_search(&plink_ctl->cto_mgate_blacklist, addr);
++}
++
++void rtw_mesh_cto_mgate_blacklist_flush(_adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++
++	rtw_blacklist_flush(&plink_ctl->cto_mgate_blacklist);
++}
++
++void dump_mesh_cto_mgate_blacklist(void *sel, _adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++
++	dump_blacklist(sel, &plink_ctl->cto_mgate_blacklist, "blacklist");
++}
++
++void dump_mesh_cto_mgate_blacklist_settings(void *sel, _adapter *adapter)
++{
++	struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
++
++	RTW_PRINT_SEL(sel, "%-12s %-17s\n"
++		, "conf_timeout", "blacklist_timeout");
++	RTW_PRINT_SEL(sel, "%12u %17u\n"
++		, peer_sel_policy->cto_mgate_conf_timeout_ms
++		, peer_sel_policy->cto_mgate_blacklist_timeout_ms);
++}
++
++static void rtw_mesh_cto_mgate_blacklist_chk(_adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	_queue *blist = &plink_ctl->cto_mgate_blacklist;
++	_list *list, *head;
++	struct blacklist_ent *ent = NULL;
++	struct wlan_network *scanned = NULL;
++
++	enter_critical_bh(&blist->lock);
++	head = &blist->queue;
++	list = get_next(head);
++	while (rtw_end_of_queue_search(head, list) == _FALSE) {
++		ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
++		list = get_next(list);
++
++		if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
++			rtw_list_delete(&ent->list);
++			rtw_mfree(ent, sizeof(struct blacklist_ent));
++			continue;
++		}
++
++		scanned = rtw_find_network(&adapter->mlmepriv.scanned_queue, ent->addr);
++		if (!scanned)
++			continue;
++
++		if (rtw_bss_is_forwarding(&scanned->network)) {
++			rtw_list_delete(&ent->list);
++			rtw_mfree(ent, sizeof(struct blacklist_ent));
++		}
++	}
++
++	exit_critical_bh(&blist->lock);
++}
++#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
++
++void rtw_chk_candidate_peer_notify(_adapter *adapter, struct wlan_network *scanned)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	bool acnode = 0;
++
++	if (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl))
++		goto exit;
++
++	if (plink_ctl->num >= RTW_MESH_MAX_PEER_CANDIDATES)
++		goto exit;
++
++#if CONFIG_RTW_MESH_ACNODE_PREVENT
++	if (plink_ctl->acnode_rsvd) {
++		acnode = rtw_mesh_scanned_is_acnode_confirmed(adapter, scanned);
++		if (acnode && !rtw_mesh_scanned_is_acnode_allow_notify(adapter, scanned))
++			goto exit;
++	}
++#endif
++
++	/* wpa_supplicant's auto peer will initiate peering when candidate peer is reported without max_peer_links consideration */
++	if (plink_ctl->num >= mcfg->max_peer_links + acnode ? 1 : 0)
++		goto exit;
++
++	if (rtw_get_passing_time_ms(scanned->last_scanned) >= mcfg->peer_sel_policy.scanr_exp_ms
++		|| (mcfg->rssi_threshold && mcfg->rssi_threshold > scanned->network.Rssi)
++		|| !rtw_bss_is_candidate_mesh_peer(adapter, &scanned->network, 1, 1)
++		#if CONFIG_RTW_MACADDR_ACL
++		|| rtw_access_ctrl(adapter, scanned->network.MacAddress) == _FALSE
++		#endif
++		|| rtw_mesh_plink_get(adapter, scanned->network.MacAddress)
++		#if CONFIG_RTW_MESH_PEER_BLACKLIST
++		|| rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)
++		#endif
++		#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++		|| !rtw_mesh_cto_mgate_network_filter(adapter, scanned)
++		#endif
++	)
++		goto exit;
++
++#if CONFIG_RTW_MESH_ACNODE_PREVENT
++	if (acnode) {
++		scanned->acnode_notify_etime = 0;
++		RTW_INFO(FUNC_ADPT_FMT" acnode "MAC_FMT"\n"
++			, FUNC_ADPT_ARG(adapter), MAC_ARG(scanned->network.MacAddress));
++	}
++#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++	rtw_cfg80211_notify_new_peer_candidate(adapter->rtw_wdev
++		, scanned->network.MacAddress
++		, BSS_EX_TLV_IES(&scanned->network)
++		, BSS_EX_TLV_IES_LEN(&scanned->network)
++		, scanned->network.Rssi
++		, GFP_ATOMIC
++	);
++#endif
++
++exit:
++	return;
++}
++
++void rtw_mesh_peer_status_chk(_adapter *adapter)
++{
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	struct mesh_plink_ent *plink;
++	_list *head, *list;
++	struct sta_info *sta = NULL;
++	struct sta_priv *stapriv = &adapter->stapriv;
++	int stainfo_offset;
++#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++	u8 cto_mgate, forwarding, mgate;
++#endif
++	u8 flush;
++	s8 flush_list[NUM_STA];
++	u8 flush_num = 0;
++	int i;
++
++#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++	if (rtw_mesh_cto_mgate_required(adapter)) {
++		/* active scan on operating channel */
++		issue_probereq_ex(adapter, &adapter->mlmepriv.cur_network.network.mesh_id, NULL, 0, 0, 0, 0);
++	}
++#endif
++
++	enter_critical_bh(&(plink_ctl->lock));
++
++	/* check established peers */
++	enter_critical_bh(&stapriv->asoc_list_lock);
++
++	head = &stapriv->asoc_list;
++	list = get_next(head);
++	while (rtw_end_of_queue_search(head, list) == _FALSE) {
++		sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
++		list = get_next(list);
++
++		if (!sta->plink || !sta->plink->scanned) {
++			rtw_warn_on(1);
++			continue;
++		}
++		plink = sta->plink;
++		flush = 0;
++
++		/* remove unsuitable peer */
++		if (!rtw_bss_is_candidate_mesh_peer(adapter, &plink->scanned->network, 1, 0)
++			#if CONFIG_RTW_MACADDR_ACL
++			|| rtw_access_ctrl(adapter, plink->addr) == _FALSE
++			#endif
++		) {
++			flush = 1;
++			goto flush_add;
++		}
++
++		#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++		cto_mgate = rtw_bss_is_cto_mgate(&(plink->scanned->network));
++		forwarding = rtw_bss_is_forwarding(&(plink->scanned->network));
++		mgate = rtw_mesh_gate_search(minfo->mesh_paths, sta->cmn.mac_addr);
++
++		/* CTO_MGATE required, remove peer without CTO_MGATE */
++		if (rtw_mesh_cto_mgate_required(adapter) && !cto_mgate) {
++			flush = 1;
++			goto flush_add;
++		}
++
++		/* cto_mgate_conf status update */
++		if (IS_CTO_MGATE_CONF_DISABLED(plink)) {
++			if (cto_mgate && !forwarding && !mgate)
++				SET_CTO_MGATE_CONF_END_TIME(plink, mcfg->peer_sel_policy.cto_mgate_conf_timeout_ms);
++			else
++				rtw_mesh_cto_mgate_blacklist_del(adapter, sta->cmn.mac_addr);
++		} else {
++			/* cto_mgate_conf ongoing */
++			if (cto_mgate && !forwarding && !mgate) {
++				if (IS_CTO_MGATE_CONF_TIMEOUT(plink)) {
++					rtw_mesh_cto_mgate_blacklist_add(adapter, sta->cmn.mac_addr);
++
++					/* CTO_MGATE required, remove peering can't achieve CTO_MGATE */
++					if (rtw_mesh_cto_mgate_required(adapter)) {
++						flush = 1;
++						goto flush_add;
++					}	
++				}
++			} else {
++				SET_CTO_MGATE_CONF_DISABLED(plink);
++				rtw_mesh_cto_mgate_blacklist_del(adapter, sta->cmn.mac_addr);
++			}
++		}
++		#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
++
++flush_add:
++		if (flush) {
++			rtw_list_delete(&sta->asoc_list);
++			stapriv->asoc_list_cnt--;
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++			if (sta->tbtx_enable)
++				stapriv->tbtx_asoc_list_cnt--;
++#endif
++			STA_SET_MESH_PLINK(sta, NULL);
++
++			stainfo_offset = rtw_stainfo_offset(stapriv, sta);
++			if (stainfo_offset_valid(stainfo_offset))
++				flush_list[flush_num++] = stainfo_offset;
++			else
++				rtw_warn_on(1);
++		}
++	}
++
++	exit_critical_bh(&stapriv->asoc_list_lock);
++
++	/* check non-established peers */
++	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
++		plink = &plink_ctl->ent[i];
++		if (plink->valid != _TRUE || plink->plink_state == RTW_MESH_PLINK_ESTAB)
++			continue;
++
++		/* remove unsuitable peer */
++		if (!rtw_bss_is_candidate_mesh_peer(adapter, &plink->scanned->network, 1, 1)
++			#if CONFIG_RTW_MACADDR_ACL
++			|| rtw_access_ctrl(adapter, plink->addr) == _FALSE
++			#endif
++		) {
++			_rtw_mesh_expire_peer_ent(adapter, plink);
++			continue;
++		}
++
++		#if CONFIG_RTW_MESH_PEER_BLACKLIST
++		/* peer confirm check timeout, add to black list */
++		if (IS_PEER_CONF_TIMEOUT(plink)) {
++			rtw_mesh_peer_blacklist_add(adapter, plink->addr);
++			_rtw_mesh_expire_peer_ent(adapter, plink);
++		}
++		#endif
++	}
++
++	exit_critical_bh(&(plink_ctl->lock));
++
++	if (flush_num) {
++		u8 sta_addr[ETH_ALEN];
++		u8 updated = _FALSE;
++
++		for (i = 0; i < flush_num; i++) {
++			sta = rtw_get_stainfo_by_offset(stapriv, flush_list[i]);
++			_rtw_memcpy(sta_addr, sta->cmn.mac_addr, ETH_ALEN);
++
++			updated |= ap_free_sta(adapter, sta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _FALSE);
++			rtw_mesh_expire_peer(adapter, sta_addr);
++		}
++
++		associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL);
++	}
++
++#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++	/* loop cto_mgate_blacklist to remove ent according to scan_r */
++	rtw_mesh_cto_mgate_blacklist_chk(adapter);
++#endif
++
++#if CONFIG_RTW_MESH_ACNODE_PREVENT
++	rtw_mesh_acnode_rsvd_chk(adapter);
++#endif
++
++	return;
++}
++
++#if CONFIG_RTW_MESH_OFFCH_CAND
++static u8 rtw_mesh_offch_cto_mgate_required(_adapter *adapter)
++{
++#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++	_queue *queue = &(mlme->scanned_queue);
++	_list *head, *pos;
++	struct wlan_network *scanned = NULL;
++	u8 ret = 0;
++
++	if (!rtw_mesh_cto_mgate_required(adapter))
++		goto exit;
++
++	enter_critical_bh(&(mlme->scanned_queue.lock));
++
++	head = get_list_head(queue);
++	pos = get_next(head);
++	while (!rtw_end_of_queue_search(head, pos)) {
++		scanned = LIST_CONTAINOR(pos, struct wlan_network, list);
++
++		if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms
++			&& (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi)
++			#if CONFIG_RTW_MACADDR_ACL
++			&& rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE
++			#endif
++			&& rtw_bss_is_candidate_mesh_peer(adapter, &scanned->network, 1, 1)
++			&& rtw_bss_is_cto_mgate(&scanned->network)
++			#if CONFIG_RTW_MESH_PEER_BLACKLIST
++			&& !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)
++			#endif
++			&& !rtw_mesh_cto_mgate_blacklist_search(adapter, scanned->network.MacAddress)
++		)
++			break;
++
++		pos = get_next(pos);
++	}
++
++	if (rtw_end_of_queue_search(head, pos))
++		ret = 1;
++
++	exit_critical_bh(&(mlme->scanned_queue.lock));
++
++exit:
++	return ret;
++#else
++	return 0;
++#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
++}
++
++u8 rtw_mesh_offch_candidate_accepted(_adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	u8 ret = 0;
++
++	if (!adapter->mesh_cfg.peer_sel_policy.offch_cand)
++		goto exit;
++
++	ret = MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)
++		&& (!plink_ctl->num || rtw_mesh_offch_cto_mgate_required(adapter))
++		;
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (ret) {
++		struct mi_state mstate_no_self;
++
++		rtw_mi_status_no_self(adapter, &mstate_no_self);
++		if (MSTATE_STA_LD_NUM(&mstate_no_self))
++			ret = 0;
++	}
++#endif
++
++exit:
++	return ret;
++}
++
++/*
++ * this function is called under off channel candidate is required 
++ * the channel with maximum candidate count is selected
++*/
++u8 rtw_mesh_select_operating_ch(_adapter *adapter)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++	_queue *queue = &(mlme->scanned_queue);
++	_list *head, *pos;
++	_irqL irqL;
++	struct wlan_network *scanned = NULL;
++	int i;
++	/* statistics for candidate accept peering */
++	u8 cand_ap_cnt[MAX_CHANNEL_NUM] = {0};
++	u8 max_cand_ap_ch = 0;
++	u8 max_cand_ap_cnt = 0;
++	/* statistics for candidate including not accept peering */
++	u8 cand_cnt[MAX_CHANNEL_NUM] = {0};
++	u8 max_cand_ch = 0;
++	u8 max_cand_cnt = 0;
++
++	_enter_critical_bh(&(mlme->scanned_queue.lock), &irqL);
++
++	head = get_list_head(queue);
++	pos = get_next(head);
++	while (!rtw_end_of_queue_search(head, pos)) {
++		scanned = LIST_CONTAINOR(pos, struct wlan_network, list);
++		pos = get_next(pos);
++
++		if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms
++			&& (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi)
++			#if CONFIG_RTW_MACADDR_ACL
++			&& rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE
++			#endif
++			&& rtw_bss_is_candidate_mesh_peer(adapter, &scanned->network, 0, 0)
++			#if CONFIG_RTW_MESH_PEER_BLACKLIST
++			&& !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)
++			#endif
++			#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++			&& rtw_mesh_cto_mgate_network_filter(adapter, scanned)
++			#endif
++		) {
++			int ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, scanned->network.Configuration.DSConfig);
++
++			if (ch_set_idx >= 0
++				&& rfctl->channel_set[ch_set_idx].ScanType != SCAN_PASSIVE
++				&& !CH_IS_NON_OCP(&rfctl->channel_set[ch_set_idx])
++			) {
++				u8 nop, accept;
++
++				rtw_mesh_bss_peering_status(&scanned->network, &nop, &accept);
++				cand_cnt[ch_set_idx]++;
++				if (max_cand_cnt < cand_cnt[ch_set_idx]) {
++					max_cand_cnt = cand_cnt[ch_set_idx];
++					max_cand_ch = rfctl->channel_set[ch_set_idx].ChannelNum;
++				}
++				if (accept) {
++					cand_ap_cnt[ch_set_idx]++;
++					if (max_cand_ap_cnt < cand_ap_cnt[ch_set_idx]) {
++						max_cand_ap_cnt = cand_ap_cnt[ch_set_idx];
++						max_cand_ap_ch = rfctl->channel_set[ch_set_idx].ChannelNum;
++					}
++				}
++			}
++		}
++	}
++
++	_exit_critical_bh(&(mlme->scanned_queue.lock), &irqL);
++
++	return max_cand_ap_ch ? max_cand_ap_ch : max_cand_ch;
++}
++
++void dump_mesh_offch_cand_settings(void *sel, _adapter *adapter)
++{
++	struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
++
++	RTW_PRINT_SEL(sel, "%-6s %-11s\n"
++		, "enable", "find_int_ms");
++	RTW_PRINT_SEL(sel, "%6u %11u\n"
++		, peer_sel_policy->offch_cand, peer_sel_policy->offch_find_int_ms);
++}
++#endif /* CONFIG_RTW_MESH_OFFCH_CAND */
++
++void dump_mesh_peer_sel_policy(void *sel, _adapter *adapter)
++{
++	struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
++
++	RTW_PRINT_SEL(sel, "%-12s\n", "scanr_exp_ms");
++	RTW_PRINT_SEL(sel, "%12u\n", peer_sel_policy->scanr_exp_ms);
++}
++
++void dump_mesh_networks(void *sel, _adapter *adapter)
++{
++#if CONFIG_RTW_MESH_ACNODE_PREVENT
++#define NSTATE_TITLE_FMT_ACN " %-5s"
++#define NSTATE_VALUE_FMT_ACN " %5d"
++#define NSTATE_TITLE_ARG_ACN , "acn"
++#define NSTATE_VALUE_ARG_ACN , (acn_ms < 99999 ? acn_ms : 99999)
++#else
++#define NSTATE_TITLE_FMT_ACN ""
++#define NSTATE_VALUE_FMT_ACN ""
++#define NSTATE_TITLE_ARG_ACN
++#define NSTATE_VALUE_ARG_ACN
++#endif
++
++	struct mlme_priv *mlme = &(adapter->mlmepriv);
++	_queue *queue = &(mlme->scanned_queue);
++	struct wlan_network	*network;
++	_list *list, *head;
++	u8 same_mbss;
++	u8 candidate;
++	struct mesh_plink_ent *plink;
++	u8 blocked;
++	u8 established;
++	s32 age_ms;
++#if CONFIG_RTW_MESH_ACNODE_PREVENT
++	s32 acn_ms;
++#endif
++	u8 *mesh_conf_ie;
++	sint mesh_conf_ie_len;
++	u8 auth_pid;
++	u8 *rsn_ie;
++	int rsn_ie_len;
++	int gcs, pcs, gmcs;
++	u8 mfp_opt;
++	struct wlan_network **mesh_networks;
++	u8 mesh_network_cnt = 0;
++	int i;
++
++	mesh_networks = rtw_zvmalloc(mlme->max_bss_cnt * sizeof(struct wlan_network *));
++	if (!mesh_networks)
++		return;
++
++	enter_critical_bh(&queue->lock);
++	head = get_list_head(queue);
++	list = get_next(head);
++
++	while (rtw_end_of_queue_search(head, list) == _FALSE) {
++		network = LIST_CONTAINOR(list, struct wlan_network, list);
++		list = get_next(list);
++
++		if (network->network.InfrastructureMode != Ndis802_11_mesh)
++			continue;
++
++		mesh_conf_ie = rtw_get_ie(BSS_EX_TLV_IES(&network->network), WLAN_EID_MESH_CONFIG
++			, &mesh_conf_ie_len, BSS_EX_TLV_IES_LEN(&network->network));
++		if (!mesh_conf_ie || mesh_conf_ie_len != 7)
++			continue;
++
++		mesh_networks[mesh_network_cnt++] = network;
++	}
++
++	exit_critical_bh(&queue->lock);
++
++	RTW_PRINT_SEL(sel, "  %-17s %-3s %-4s %-5s %-32s %-10s"
++		" %-3s %-3s %-4s"
++		" %-3s %-3s %-3s"
++		NSTATE_TITLE_FMT_ACN
++		"\n"
++		, "bssid", "ch", "rssi", "age", "mesh_id", "P M C S A "
++		, "pcs", "gcs", "gmcs"
++		, "nop", "fwd", "cto"
++		NSTATE_TITLE_ARG_ACN
++	);
++
++	if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)) {
++		network = &mlme->cur_network;
++		mesh_conf_ie = rtw_get_ie(BSS_EX_TLV_IES(&network->network), WLAN_EID_MESH_CONFIG
++			, &mesh_conf_ie_len, BSS_EX_TLV_IES_LEN(&network->network));
++		if (mesh_conf_ie && mesh_conf_ie_len == 7) {
++			gcs = pcs = gmcs = 0;
++			mfp_opt = MFP_NO;
++			auth_pid = GET_MESH_CONF_ELE_AUTH_PROTO_ID(mesh_conf_ie + 2);
++			if (auth_pid && auth_pid <= 2) {
++				rsn_ie = rtw_get_wpa2_ie(BSS_EX_TLV_IES(&network->network)
++							, &rsn_ie_len, BSS_EX_TLV_IES_LEN(&network->network));
++				if (rsn_ie && rsn_ie_len)
++					rtw_parse_wpa2_ie(rsn_ie, rsn_ie_len + 2, &gcs, &pcs, &gmcs, NULL, &mfp_opt);
++			}
++			RTW_PRINT_SEL(sel, "* "MAC_FMT" %3d            %-32s %2x%2x%2x%2x%2x"
++				" %03x %03x %c%03x"
++				" %c%2u %3u %c%c "
++				"\n"
++				, MAC_ARG(network->network.MacAddress)
++				, network->network.Configuration.DSConfig
++				, network->network.mesh_id.Ssid
++				, GET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(mesh_conf_ie + 2)
++				, GET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(mesh_conf_ie + 2)
++				, GET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(mesh_conf_ie + 2)
++				, GET_MESH_CONF_ELE_SYNC_METHOD_ID(mesh_conf_ie + 2)
++				, auth_pid
++				, pcs, gcs, mfp_opt == MFP_REQUIRED ? 'R' : (mfp_opt == MFP_OPTIONAL ? 'C' : ' ')
++				, mfp_opt >= MFP_OPTIONAL ? gmcs : 0
++				, GET_MESH_CONF_ELE_ACCEPT_PEERINGS(mesh_conf_ie + 2) ? '+' : ' '
++				, GET_MESH_CONF_ELE_NUM_OF_PEERINGS(mesh_conf_ie + 2)
++				, GET_MESH_CONF_ELE_FORWARDING(mesh_conf_ie + 2)
++				, GET_MESH_CONF_ELE_CTO_MGATE(mesh_conf_ie + 2) ? 'G' : ' '
++				, GET_MESH_CONF_ELE_CTO_AS(mesh_conf_ie + 2) ? 'A' : ' '
++			);
++		}
++	}
++
++	for (i = 0; i < mesh_network_cnt; i++) {
++		network = mesh_networks[i];
++
++		if (network->network.InfrastructureMode != Ndis802_11_mesh)
++			continue;
++
++		mesh_conf_ie = rtw_get_ie(BSS_EX_TLV_IES(&network->network), WLAN_EID_MESH_CONFIG
++			, &mesh_conf_ie_len, BSS_EX_TLV_IES_LEN(&network->network));
++		if (!mesh_conf_ie || mesh_conf_ie_len != 7)
++			continue;
++
++		gcs = pcs = gmcs = 0;
++		mfp_opt = MFP_NO;
++		auth_pid = GET_MESH_CONF_ELE_AUTH_PROTO_ID(mesh_conf_ie + 2);
++		if (auth_pid && auth_pid <= 2) {
++			rsn_ie = rtw_get_wpa2_ie(BSS_EX_TLV_IES(&network->network), &rsn_ie_len, BSS_EX_TLV_IES_LEN(&network->network));
++			if (rsn_ie && rsn_ie_len)
++				rtw_parse_wpa2_ie(rsn_ie, rsn_ie_len + 2, &gcs, &pcs, &gmcs, NULL, &mfp_opt);
++		}
++		age_ms = rtw_get_passing_time_ms(network->last_scanned);
++		#if CONFIG_RTW_MESH_ACNODE_PREVENT
++		if (network->acnode_stime == 0)
++			acn_ms = 0;
++		else
++			acn_ms = rtw_get_passing_time_ms(network->acnode_stime);
++		#endif
++		same_mbss = 0;
++		candidate = 0;
++		plink = NULL;
++		blocked = 0;
++		established = 0;
++
++		if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)) {
++			plink = rtw_mesh_plink_get(adapter, network->network.MacAddress);
++			if (plink && plink->plink_state == RTW_MESH_PLINK_ESTAB)
++				established = 1;
++			else if (plink && plink->plink_state == RTW_MESH_PLINK_BLOCKED)
++				blocked = 1;
++			else if (plink)
++				;
++			else if (rtw_bss_is_candidate_mesh_peer(adapter, &network->network, 0, 1))
++				candidate = 1;
++			else if (rtw_bss_is_same_mbss(&mlme->cur_network.network, &network->network))
++				same_mbss = 1;
++		}
++
++		RTW_PRINT_SEL(sel, "%c "MAC_FMT" %3d %4ld %5d %-32s %2x%2x%2x%2x%2x"
++			" %03x %03x %c%03x"
++			" %c%2u %3u %c%c "
++			NSTATE_VALUE_FMT_ACN
++			"\n"
++			, established ? 'E' : (blocked ? 'B' : (plink ? 'N' : (candidate ? 'C' : (same_mbss ? 'S' : ' '))))
++			, MAC_ARG(network->network.MacAddress)
++			, network->network.Configuration.DSConfig
++			, network->network.Rssi
++			, age_ms < 99999 ? age_ms : 99999
++			, network->network.mesh_id.Ssid
++			, GET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(mesh_conf_ie + 2)
++			, GET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(mesh_conf_ie + 2)
++			, GET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(mesh_conf_ie + 2)
++			, GET_MESH_CONF_ELE_SYNC_METHOD_ID(mesh_conf_ie + 2)
++			, auth_pid
++			, pcs, gcs, mfp_opt == MFP_REQUIRED ? 'R' : (mfp_opt == MFP_OPTIONAL ? 'C' : ' ')
++			, mfp_opt >= MFP_OPTIONAL ? gmcs : 0
++			, GET_MESH_CONF_ELE_ACCEPT_PEERINGS(mesh_conf_ie + 2) ? '+' : ' '
++			, GET_MESH_CONF_ELE_NUM_OF_PEERINGS(mesh_conf_ie + 2)
++			, GET_MESH_CONF_ELE_FORWARDING(mesh_conf_ie + 2)
++			, GET_MESH_CONF_ELE_CTO_MGATE(mesh_conf_ie + 2) ? 'G' : ' '
++			, GET_MESH_CONF_ELE_CTO_AS(mesh_conf_ie + 2) ? 'A' : ' '
++			NSTATE_VALUE_ARG_ACN
++		);
++	}
++
++	rtw_vmfree(mesh_networks, mlme->max_bss_cnt * sizeof(struct wlan_network *));
++}
++
++void rtw_mesh_adjust_chbw(u8 req_ch, u8 *req_bw, u8 *req_offset)
++{
++	if (req_ch >= 5 && req_ch <= 9) {
++		/* prevent secondary channel offset mismatch */
++		if (*req_bw > CHANNEL_WIDTH_20) {
++			*req_bw = CHANNEL_WIDTH_20;
++			*req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		}
++	}
++}
++
++void rtw_mesh_sae_check_frames(_adapter *adapter, const u8 *buf, u32 len, u8 tx, u16 alg, u16 seq, u16 status)
++{
++#if CONFIG_RTW_MESH_PEER_BLACKLIST
++	if (tx && seq == 1)
++		rtw_mesh_plink_set_peer_conf_timeout(adapter, GetAddr1Ptr(buf));
++#endif
++}
++
++#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS
++#ifdef CONFIG_RTW_MESH_AEK
++static int rtw_mpm_ampe_dec(_adapter *adapter, struct mesh_plink_ent *plink
++	, u8 *fhead, size_t flen, u8* fbody, u8 *mic_ie, u8 *ampe_buf)
++{	
++	int ret = _FAIL, verify_ret;
++	const u8 *aad[] = {adapter_mac_addr(adapter), plink->addr, fbody};
++	const size_t aad_len[] = {ETH_ALEN, ETH_ALEN, mic_ie - fbody};
++	u8 *iv_crypt;
++	size_t iv_crypt_len = flen - (mic_ie + 2 - fhead);
++
++	iv_crypt = rtw_malloc(iv_crypt_len);
++	if (!iv_crypt)
++		goto exit;
++
++	_rtw_memcpy(iv_crypt, mic_ie + 2, iv_crypt_len);
++
++	verify_ret = rtw_aes_siv_decrypt(plink->aek, 32, iv_crypt, iv_crypt_len
++		, 3, aad, aad_len, ampe_buf);
++
++	rtw_mfree(iv_crypt, iv_crypt_len);
++
++	if (verify_ret) {
++		RTW_WARN("verify error, aek_valid=%u\n", plink->aek_valid);
++		goto exit;
++	} else if (*ampe_buf != WLAN_EID_AMPE) {
++		RTW_WARN("plaintext is not AMPE IE\n");
++		goto exit;
++	} else if ( 16 /* AES_BLOCK_SIZE*/ + 2 + *(ampe_buf + 1) > iv_crypt_len) {
++		RTW_WARN("plaintext AMPE IE length is not valid\n");
++		goto exit;
++	}
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++
++static int rtw_mpm_ampe_enc(_adapter *adapter, struct mesh_plink_ent *plink
++	, u8* fbody, u8 *mic_ie, u8 *ampe_buf, bool inverse)
++{
++	int ret = _FAIL, protect_ret;
++	const u8 *aad[3];
++	const size_t aad_len[3] = {ETH_ALEN, ETH_ALEN, mic_ie - fbody};
++	u8 *ampe_ie;
++	size_t ampe_ie_len = *(ampe_buf + 1) + 2; /* including id & len */
++
++	if (inverse) {
++		aad[0] = plink->addr;
++		aad[1] = adapter_mac_addr(adapter);
++	} else {
++		aad[0] = adapter_mac_addr(adapter);
++		aad[1] = plink->addr;
++	}
++	aad[2] = fbody;
++
++	ampe_ie = rtw_malloc(ampe_ie_len);
++	if (!ampe_ie)
++		goto exit;
++
++	_rtw_memcpy(ampe_ie, ampe_buf, ampe_ie_len);
++
++	protect_ret = rtw_aes_siv_encrypt(plink->aek, 32, ampe_ie, ampe_ie_len
++		, 3, aad, aad_len, mic_ie + 2);
++
++	rtw_mfree(ampe_ie, ampe_ie_len);
++
++	if (protect_ret) {
++		RTW_WARN("protect error, aek_valid=%u\n", plink->aek_valid);
++		goto exit;
++	}
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++#endif /* CONFIG_RTW_MESH_AEK */
++
++static int rtw_mpm_tx_ies_sync_bss(_adapter *adapter, struct mesh_plink_ent *plink
++	, u8 *fhead, size_t flen, u8* fbody, u8 tlv_ies_offset, u8 *mpm_ie, u8 *mic_ie
++	, u8 **nbuf, size_t *nlen)
++{
++	int ret = _FAIL;
++	struct mlme_priv *mlme = &(adapter->mlmepriv);
++	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++	struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info);
++	WLAN_BSSID_EX *network = &(mlmeinfo->network);
++	uint left;
++	u8 *pos;
++
++	uint mpm_ielen = *(mpm_ie + 1);
++	u8 *fpos;
++	u8 *new_buf = NULL;
++	size_t new_len = 0;
++
++	u8 *new_fhead;
++	size_t new_flen;
++	u8 *new_fbody;
++	u8 *new_mic_ie;
++
++#ifdef CONFIG_RTW_MESH_AEK
++	u8 *ampe_buf = NULL;
++	size_t ampe_buf_len = 0;
++
++	/* decode */
++	if (mic_ie) {
++		ampe_buf_len = flen - (mic_ie + 2 + 16 /* AES_BLOCK_SIZE */ - fhead);
++		ampe_buf = rtw_malloc(ampe_buf_len);
++		if (!ampe_buf)
++			goto exit;
++
++		if (rtw_mpm_ampe_dec(adapter, plink, fhead, flen, fbody, mic_ie, ampe_buf) != _SUCCESS)
++			goto exit;
++
++		if (*(ampe_buf + 1) >= 68) {
++			_rtw_memcpy(plink->sel_pcs, ampe_buf + 2, 4);
++			_rtw_memcpy(plink->l_nonce, ampe_buf + 6, 32);
++			_rtw_memcpy(plink->p_nonce, ampe_buf + 38, 32);
++		}
++	}
++#endif
++
++	/* count for new frame length  */
++	new_len = sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset;
++	left = BSS_EX_TLV_IES_LEN(network);
++	pos = BSS_EX_TLV_IES(network);
++	while (left >= 2) {
++		u8 id, elen;
++	
++		id = *pos++;
++		elen = *pos++;
++		left -= 2;
++
++		if (elen > left)
++			break;
++
++		switch (id) {
++		case WLAN_EID_SSID:
++		case WLAN_EID_DS_PARAMS:
++		case WLAN_EID_TIM:
++			break;
++		default:
++			new_len += 2 + elen;
++		}
++
++		left -= elen;
++		pos += elen;
++	}
++	new_len += mpm_ielen + 2;
++	if (mic_ie)
++		new_len += 16 /* AES_BLOCK_SIZE*/ + 2 + ampe_buf_len;
++
++	/* alloc new frame */
++	new_buf = rtw_malloc(new_len);
++	if (!new_buf) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	/* build new frame  */
++	_rtw_memcpy(new_buf, fhead, sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset);
++	new_fhead = new_buf;
++	new_flen = new_len;
++	new_fbody = new_fhead + sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	fpos = new_fbody + tlv_ies_offset;
++	left = BSS_EX_TLV_IES_LEN(network);
++	pos = BSS_EX_TLV_IES(network);
++	while (left >= 2) {
++		u8 id, elen;
++	
++		id = *pos++;
++		elen = *pos++;
++		left -= 2;
++
++		if (elen > left)
++			break;
++
++		switch (id) {
++		case WLAN_EID_SSID:
++		case WLAN_EID_DS_PARAMS:
++		case WLAN_EID_TIM:
++			break;
++		default:
++			fpos = rtw_set_ie(fpos, id, elen, pos, NULL);
++			if (id == WLAN_EID_MESH_CONFIG)
++				fpos = rtw_set_ie(fpos, WLAN_EID_MPM, mpm_ielen, mpm_ie + 2, NULL);
++		}
++
++		left -= elen;
++		pos += elen;
++	}
++	if (mic_ie) {
++		new_mic_ie = fpos;
++		*fpos++ = WLAN_EID_MIC;
++		*fpos++ = 16 /* AES_BLOCK_SIZE */;
++	}
++
++#ifdef CONFIG_RTW_MESH_AEK
++	/* encode */
++	if (mic_ie) {
++		int enc_ret = rtw_mpm_ampe_enc(adapter, plink, new_fbody, new_mic_ie, ampe_buf, 0);
++		if (enc_ret != _SUCCESS)
++			goto exit;
++	}
++#endif
++
++	*nlen = new_len;
++	*nbuf = new_buf;
++
++	ret = _SUCCESS;
++
++exit:
++	if (ret != _SUCCESS && new_buf)
++		rtw_mfree(new_buf, new_len);
++
++#ifdef CONFIG_RTW_MESH_AEK
++	if (ampe_buf)
++		rtw_mfree(ampe_buf, ampe_buf_len);
++#endif
++
++	return ret;
++}
++#endif /* CONFIG_RTW_MPM_TX_IES_SYNC_BSS */
++
++struct mpm_frame_info {
++	u8 *aid;
++	u16 aid_v;
++	u8 *pid;
++	u16 pid_v;
++	u8 *llid;
++	u16 llid_v;
++	u8 *plid;
++	u16 plid_v;
++	u8 *reason;
++	u16 reason_v;
++	u8 *chosen_pmk;
++};
++
++/*
++* pid:00000 llid:00000 chosen_pmk:0x00000000000000000000000000000000
++* aid:00000 pid:00000 llid:00000 plid:00000 chosen_pmk:0x00000000000000000000000000000000
++* pid:00000 llid:00000 plid:00000 reason:00000 chosen_pmk:0x00000000000000000000000000000000
++*/
++#define MPM_LOG_BUF_LEN 92 /* this length is limited for legal combination */
++static void rtw_mpm_info_msg(struct mpm_frame_info *mpm_info, u8 *mpm_log_buf)
++{
++	int cnt = 0;
++
++	if (mpm_info->aid) {
++		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "aid:%u ", mpm_info->aid_v);
++		if (cnt >= MPM_LOG_BUF_LEN - 1)
++			goto exit;
++	}
++	if (mpm_info->pid) {
++		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "pid:%u ", mpm_info->pid_v);
++		if (cnt >= MPM_LOG_BUF_LEN - 1)
++			goto exit;
++	}
++	if (mpm_info->llid) {
++		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "llid:%u ", mpm_info->llid_v);
++		if (cnt >= MPM_LOG_BUF_LEN - 1)
++			goto exit;
++	}
++	if (mpm_info->plid) {
++		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "plid:%u ", mpm_info->plid_v);
++		if (cnt >= MPM_LOG_BUF_LEN - 1)
++			goto exit;
++	}
++	if (mpm_info->reason) {
++		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "reason:%u ", mpm_info->reason_v);
++		if (cnt >= MPM_LOG_BUF_LEN - 1)
++			goto exit;
++	}
++	if (mpm_info->chosen_pmk) {
++		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "chosen_pmk:0x"KEY_FMT, KEY_ARG(mpm_info->chosen_pmk));
++		if (cnt >= MPM_LOG_BUF_LEN - 1)
++			goto exit;
++	}
++
++exit:
++	return;
++}
++
++static int rtw_mpm_check_frames(_adapter *adapter, u8 action, const u8 **buf, size_t *len, u8 tx)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	struct mesh_plink_ent *plink = NULL;
++	u8 *nbuf = NULL;
++	size_t nlen = 0;
++	u8 *fhead = (u8 *)*buf;
++	size_t flen = *len;
++	u8 *peer_addr = tx ? GetAddr1Ptr(fhead) : get_addr2_ptr(fhead);
++	u8 *frame_body = fhead + sizeof(struct rtw_ieee80211_hdr_3addr);
++	struct mpm_frame_info mpm_info;
++	u8 tlv_ies_offset;
++	u8 *mpm_ie = NULL;
++	uint mpm_ielen = 0;
++	u8 *mic_ie = NULL;
++	uint mic_ielen = 0;
++	int ret = 0;
++	u8 mpm_log_buf[MPM_LOG_BUF_LEN] = {0};
++
++	if (action == RTW_ACT_SELF_PROTECTED_MESH_OPEN)
++		tlv_ies_offset = 4;
++	else if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF)
++		tlv_ies_offset = 6;
++	else if (action == RTW_ACT_SELF_PROTECTED_MESH_CLOSE)
++		tlv_ies_offset = 2;
++	else {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	plink = rtw_mesh_plink_get(adapter, peer_addr);
++	if (!plink && (tx == _TRUE || action == RTW_ACT_SELF_PROTECTED_MESH_CONF)) {
++		/* warning message if no plink when: 1.TX all MPM or 2.RX CONF */
++		RTW_WARN("RTW_%s:%s without plink of "MAC_FMT"\n"
++			, (tx == _TRUE) ? "Tx" : "Rx", action_self_protected_str(action), MAC_ARG(peer_addr));
++		goto exit;
++	}
++
++	_rtw_memset(&mpm_info, 0, sizeof(struct mpm_frame_info));
++
++	if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF) {
++		mpm_info.aid = (u8 *)frame_body + 4;
++		mpm_info.aid_v = RTW_GET_LE16(mpm_info.aid);
++	}
++
++	mpm_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
++		, WLAN_EID_MPM, &mpm_ielen
++		, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
++	if (!mpm_ie || mpm_ielen < 2 + 2)
++		goto exit;
++
++	mpm_info.pid = mpm_ie + 2;
++	mpm_info.pid_v = RTW_GET_LE16(mpm_info.pid);
++	mpm_info.llid = mpm_info.pid + 2;
++	mpm_info.llid_v = RTW_GET_LE16(mpm_info.llid);
++
++	switch (action) {
++	case RTW_ACT_SELF_PROTECTED_MESH_OPEN:
++		/* pid:2, llid:2, (chosen_pmk:16) */
++		if (mpm_info.pid_v == 0 && mpm_ielen == 4)
++			;
++		else if (mpm_info.pid_v == 1 && mpm_ielen == 20)
++			mpm_info.chosen_pmk = mpm_info.llid + 2;
++		else
++			goto exit;
++		break;
++	case RTW_ACT_SELF_PROTECTED_MESH_CONF:
++		/* pid:2, llid:2, plid:2, (chosen_pmk:16) */
++		mpm_info.plid = mpm_info.llid + 2;
++		mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid);
++		if (mpm_info.pid_v == 0 && mpm_ielen == 6)
++			;
++		else if (mpm_info.pid_v == 1 && mpm_ielen == 22)
++			mpm_info.chosen_pmk = mpm_info.plid + 2;
++		else
++			goto exit;
++		break;
++	case RTW_ACT_SELF_PROTECTED_MESH_CLOSE:
++		/* pid:2, llid:2, (plid:2), reason:2, (chosen_pmk:16) */
++		if (mpm_info.pid_v == 0 && mpm_ielen == 6) {
++			/* MPM, without plid */
++			mpm_info.reason = mpm_info.llid + 2;
++			mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);
++		} else if (mpm_info.pid_v == 0 && mpm_ielen == 8) {
++			/* MPM, with plid */
++			mpm_info.plid = mpm_info.llid + 2;
++			mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid);
++			mpm_info.reason = mpm_info.plid + 2;
++			mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);
++		} else if (mpm_info.pid_v == 1 && mpm_ielen == 22) {
++			/* AMPE, without plid */
++			mpm_info.reason = mpm_info.llid + 2;
++			mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);
++			mpm_info.chosen_pmk = mpm_info.reason + 2;
++		} else if (mpm_info.pid_v == 1 && mpm_ielen == 24) {
++			/* AMPE, with plid */
++			mpm_info.plid = mpm_info.llid + 2;
++			mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid);
++			mpm_info.reason = mpm_info.plid + 2;
++			mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);
++			mpm_info.chosen_pmk = mpm_info.reason + 2;
++		} else
++			goto exit;
++		break;
++	};
++
++	if (mpm_info.pid_v == 1) {
++		mic_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
++			, WLAN_EID_MIC, &mic_ielen
++			, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
++		if (!mic_ie || mic_ielen != 16 /* AES_BLOCK_SIZE */)
++			goto exit;
++	}
++
++#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS
++	if ((action == RTW_ACT_SELF_PROTECTED_MESH_OPEN || action == RTW_ACT_SELF_PROTECTED_MESH_CONF)
++		&& tx == _TRUE
++	) {
++#define DBG_RTW_MPM_TX_IES_SYNC_BSS 0
++
++		if (mpm_info.pid_v == 1 && (!plink || !MESH_PLINK_AEK_VALID(plink))) {
++			RTW_WARN("AEK not ready, IEs can't sync with BSS\n");
++			goto bypass_sync_bss;
++		}
++
++		if (DBG_RTW_MPM_TX_IES_SYNC_BSS) {
++			RTW_INFO(FUNC_ADPT_FMT" before:\n", FUNC_ADPT_ARG(adapter));
++			dump_ies(RTW_DBGDUMP
++				, fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
++				, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
++		}
++
++		rtw_mpm_tx_ies_sync_bss(adapter, plink
++			, fhead, flen, frame_body, tlv_ies_offset, mpm_ie, mic_ie
++			, &nbuf, &nlen);
++		if (!nbuf)
++			goto exit;
++
++		/* update pointer & len for new frame */
++		fhead = nbuf;
++		flen = nlen;
++		frame_body = fhead + sizeof(struct rtw_ieee80211_hdr_3addr);
++		if (mpm_info.pid_v == 1) {
++			mic_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
++				, WLAN_EID_MIC, &mic_ielen
++				, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
++		}
++
++		if (DBG_RTW_MPM_TX_IES_SYNC_BSS) {
++			RTW_INFO(FUNC_ADPT_FMT" after:\n", FUNC_ADPT_ARG(adapter));
++			dump_ies(RTW_DBGDUMP
++				, fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
++				, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
++		}
++	}
++bypass_sync_bss:
++#endif /* CONFIG_RTW_MPM_TX_IES_SYNC_BSS */
++
++	if (!plink)
++		goto mpm_log;
++
++#if CONFIG_RTW_MESH_PEER_BLACKLIST
++	if (action == RTW_ACT_SELF_PROTECTED_MESH_OPEN) {
++		if (tx)
++			rtw_mesh_plink_set_peer_conf_timeout(adapter, peer_addr);
++
++	} else
++#endif
++#if CONFIG_RTW_MESH_ACNODE_PREVENT
++	if (action == RTW_ACT_SELF_PROTECTED_MESH_CLOSE) {
++		if (tx && mpm_info.reason && mpm_info.reason_v == WLAN_REASON_MESH_MAX_PEERS) {
++			if (rtw_mesh_scanned_is_acnode_confirmed(adapter, plink->scanned)
++				&& rtw_mesh_acnode_prevent_allow_sacrifice(adapter)
++			) {
++				struct sta_info *sac = rtw_mesh_acnode_prevent_pick_sacrifice(adapter);
++
++				if (sac) {
++					struct sta_priv *stapriv = &adapter->stapriv;
++					_irqL irqL;
++					u8 sta_addr[ETH_ALEN];
++					u8 updated = _FALSE;
++
++					_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
++					if (!rtw_is_list_empty(&sac->asoc_list)) {
++						rtw_list_delete(&sac->asoc_list);
++						stapriv->asoc_list_cnt--;
++						#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++						if (sac->tbtx_enable)
++							stapriv->tbtx_asoc_list_cnt--;
++						#endif			
++						STA_SET_MESH_PLINK(sac, NULL);
++					}
++					_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
++					RTW_INFO(FUNC_ADPT_FMT" sacrifice "MAC_FMT" for acnode\n"
++						, FUNC_ADPT_ARG(adapter), MAC_ARG(sac->cmn.mac_addr));
++
++					_rtw_memcpy(sta_addr, sac->cmn.mac_addr, ETH_ALEN);
++					updated = ap_free_sta(adapter, sac, 0, 0, 1);
++					rtw_mesh_expire_peer(stapriv->padapter, sta_addr);
++
++					associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL);
++				}
++			}
++		}
++	} else
++#endif
++	if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF) {
++		_irqL irqL;
++		u8 *ies = NULL;
++		u16 ies_len = 0;
++
++		_enter_critical_bh(&(plink_ctl->lock), &irqL);
++
++		plink = _rtw_mesh_plink_get(adapter, peer_addr);
++		if (!plink)
++			goto release_plink_ctl;
++
++		if (tx == _FALSE) {
++			ies = plink->rx_conf_ies;
++			ies_len = plink->rx_conf_ies_len;
++			plink->rx_conf_ies = NULL;
++			plink->rx_conf_ies_len = 0;
++
++			plink->llid = mpm_info.plid_v;
++			plink->plid = mpm_info.llid_v;
++			plink->peer_aid = mpm_info.aid_v;
++			if (mpm_info.pid_v == 1)
++				_rtw_memcpy(plink->chosen_pmk, mpm_info.chosen_pmk, 16);
++		}
++		#ifdef CONFIG_RTW_MESH_DRIVER_AID
++		else {
++			ies = plink->tx_conf_ies;
++			ies_len = plink->tx_conf_ies_len;
++			plink->tx_conf_ies = NULL;
++			plink->tx_conf_ies_len = 0;
++		}
++		#endif
++
++		if (ies && ies_len)
++			rtw_mfree(ies, ies_len);
++
++		#ifndef CONFIG_RTW_MESH_DRIVER_AID
++		if (tx == _TRUE)
++			goto release_plink_ctl; /* no need to copy tx conf ies */
++		#endif
++
++		/* copy mesh confirm IEs */
++		if (mpm_info.pid_v == 1) /* not include MIC & encrypted AMPE */
++			ies_len = (mic_ie - fhead) - sizeof(struct rtw_ieee80211_hdr_3addr) - 2;
++		else
++			ies_len = flen - sizeof(struct rtw_ieee80211_hdr_3addr) - 2;
++
++		ies = rtw_zmalloc(ies_len);
++		if (ies) {
++			_rtw_memcpy(ies, fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + 2, ies_len);
++			if (tx == _FALSE) {
++				plink->rx_conf_ies = ies;
++				plink->rx_conf_ies_len = ies_len;
++			}
++			#ifdef CONFIG_RTW_MESH_DRIVER_AID	
++			else {
++				plink->tx_conf_ies = ies;
++				plink->tx_conf_ies_len = ies_len;
++			}
++			#endif
++		}
++
++release_plink_ctl:
++		_exit_critical_bh(&(plink_ctl->lock), &irqL);
++	}
++
++mpm_log:
++	rtw_mpm_info_msg(&mpm_info, mpm_log_buf);
++	RTW_INFO("RTW_%s:%s %s\n"
++		, (tx == _TRUE) ? "Tx" : "Rx"
++		, action_self_protected_str(action)
++		, mpm_log_buf
++	);
++
++	ret = 1;
++
++exit:
++	if (nbuf) {
++		if (ret == 1) {
++			*buf = nbuf;
++			*len = nlen;
++		} else
++			rtw_mfree(nbuf, nlen);
++	}
++
++	return ret;
++}
++
++static int rtw_mesh_check_frames(_adapter *adapter, const u8 **buf, size_t *len, u8 tx)
++{
++	int is_mesh_frame = -1;
++	const u8 *frame_body;
++	u8 category, action;
++
++	frame_body = *buf + sizeof(struct rtw_ieee80211_hdr_3addr);
++	category = frame_body[0];
++
++	if (category == RTW_WLAN_CATEGORY_SELF_PROTECTED) {
++		action = frame_body[1];
++		switch (action) {
++		case RTW_ACT_SELF_PROTECTED_MESH_OPEN:
++		case RTW_ACT_SELF_PROTECTED_MESH_CONF:
++		case RTW_ACT_SELF_PROTECTED_MESH_CLOSE:
++			rtw_mpm_check_frames(adapter, action, buf, len, tx);
++			is_mesh_frame = action;
++			break;
++		case RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM:
++		case RTW_ACT_SELF_PROTECTED_MESH_GK_ACK:
++			RTW_INFO("RTW_%s:%s\n", (tx == _TRUE) ? "Tx" : "Rx", action_self_protected_str(action));
++			is_mesh_frame = action;
++			break;
++		default:
++			break;
++		};
++	}
++
++	return is_mesh_frame;
++}
++
++int rtw_mesh_check_frames_tx(_adapter *adapter, const u8 **buf, size_t *len)
++{
++	return rtw_mesh_check_frames(adapter, buf, len, _TRUE);
++}
++
++int rtw_mesh_check_frames_rx(_adapter *adapter, const u8 *buf, size_t len)
++{
++	return rtw_mesh_check_frames(adapter, &buf, &len, _FALSE);
++}
++
++int rtw_mesh_on_auth(_adapter *adapter, union recv_frame *rframe)
++{
++	u8 *whdr = rframe->u.hdr.rx_data;
++
++#if CONFIG_RTW_MACADDR_ACL
++	if (rtw_access_ctrl(adapter, get_addr2_ptr(whdr)) == _FALSE)
++		return _SUCCESS;
++#endif
++
++	if (!rtw_mesh_plink_get(adapter, get_addr2_ptr(whdr))) {
++		#if CONFIG_RTW_MESH_ACNODE_PREVENT
++		rtw_mesh_acnode_set_notify_etime(adapter, whdr);
++		#endif
++
++		if (adapter_to_rfctl(adapter)->offch_state == OFFCHS_NONE)
++			issue_probereq(adapter, &adapter->mlmepriv.cur_network.network.mesh_id, get_addr2_ptr(whdr));
++
++		/* only peer being added (checked by notify conditions) is allowed */
++		return _SUCCESS;
++	}
++
++	rtw_cfg80211_rx_mframe(adapter, rframe, NULL);
++	return _SUCCESS;
++}
++
++unsigned int on_action_self_protected(_adapter *adapter, union recv_frame *rframe)
++{
++	unsigned int ret = _FAIL;
++	struct sta_info *sta = NULL;
++	u8 *pframe = rframe->u.hdr.rx_data;
++	uint frame_len = rframe->u.hdr.len;
++	u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++	u8 category;
++	u8 action;
++
++	/* check RA matches or not */
++	if (!_rtw_memcmp(adapter_mac_addr(adapter), GetAddr1Ptr(pframe), ETH_ALEN))
++		goto exit;
++
++	category = frame_body[0];
++	if (category != RTW_WLAN_CATEGORY_SELF_PROTECTED)
++		goto exit;
++
++	action = frame_body[1];
++	switch (action) {
++	case RTW_ACT_SELF_PROTECTED_MESH_OPEN:
++	case RTW_ACT_SELF_PROTECTED_MESH_CONF:
++	case RTW_ACT_SELF_PROTECTED_MESH_CLOSE:
++	case RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM:
++	case RTW_ACT_SELF_PROTECTED_MESH_GK_ACK:
++		if (!(MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)))
++			goto exit;
++#ifdef CONFIG_IOCTL_CFG80211
++		#if CONFIG_RTW_MACADDR_ACL
++		if (rtw_access_ctrl(adapter, get_addr2_ptr(pframe)) == _FALSE)
++			goto exit;
++		#endif
++		#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++		if (rtw_mesh_cto_mgate_required(adapter)
++			/* only peer being added (checked by notify conditions) is allowed */
++			&& !rtw_mesh_plink_get(adapter, get_addr2_ptr(pframe)))
++			goto exit;
++		#endif
++		rtw_cfg80211_rx_action(adapter, rframe, NULL);
++		ret = _SUCCESS;
++#endif /* CONFIG_IOCTL_CFG80211 */
++		break;
++	default:
++		break;
++	}
++
++exit:
++	return ret;
++}
++
++const u8 ae_to_mesh_ctrl_len[] = {
++	6,
++	12, /* MESH_FLAGS_AE_A4 */
++	18, /* MESH_FLAGS_AE_A5_A6 */
++	0,
++};
++
++unsigned int on_action_mesh(_adapter *adapter, union recv_frame *rframe)
++{
++	unsigned int ret = _FAIL;
++	struct sta_info *sta = NULL;
++	struct sta_priv *stapriv = &adapter->stapriv;
++	u8 *pframe = rframe->u.hdr.rx_data;
++	uint frame_len = rframe->u.hdr.len;
++	u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++	u8 category;
++	u8 action;
++
++	if (!MLME_IS_MESH(adapter))
++		goto exit;
++
++	/* check stainfo exist? */
++
++	category = frame_body[0];
++	if (category != RTW_WLAN_CATEGORY_MESH)
++		goto exit;
++
++	action = frame_body[1];
++	switch (action) {
++	case RTW_ACT_MESH_HWMP_PATH_SELECTION:
++		rtw_mesh_rx_path_sel_frame(adapter, rframe);
++		ret = _SUCCESS;
++		break;
++	default:
++		break;
++	}
++
++exit:
++	return ret;
++}
++
++bool rtw_mesh_update_bss_peering_status(_adapter *adapter, WLAN_BSSID_EX *bss)
++{
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	u8 num_of_peerings = stapriv->asoc_list_cnt;
++	bool accept_peerings = stapriv->asoc_list_cnt < mcfg->max_peer_links;
++	u8 *ie;
++	int ie_len;
++	bool updated = 0;
++
++#if CONFIG_RTW_MESH_ACNODE_PREVENT
++	accept_peerings |= plink_ctl->acnode_rsvd;
++#endif
++
++	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len, BSS_EX_TLV_IES_LEN(bss));
++	if (!ie || ie_len != 7) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (GET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2) != num_of_peerings) {
++		SET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2, num_of_peerings);
++		updated = 1;
++	}
++
++	if (GET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2) != accept_peerings) {
++		SET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2, accept_peerings);
++		updated = 1;
++	}
++
++exit:
++	return updated;
++}
++
++bool rtw_mesh_update_bss_formation_info(_adapter *adapter, WLAN_BSSID_EX *bss)
++{
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	u8 cto_mgate = (minfo->num_gates || mcfg->dot11MeshGateAnnouncementProtocol);
++	u8 cto_as = 0;
++	u8 *ie;
++	int ie_len;
++	bool updated = 0;
++
++	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
++			BSS_EX_TLV_IES_LEN(bss));
++	if (!ie || ie_len != 7) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (GET_MESH_CONF_ELE_CTO_MGATE(ie + 2) != cto_mgate) {
++		SET_MESH_CONF_ELE_CTO_MGATE(ie + 2, cto_mgate);
++		updated = 1;
++	}
++
++	if (GET_MESH_CONF_ELE_CTO_AS(ie + 2) != cto_as) {
++		SET_MESH_CONF_ELE_CTO_AS(ie + 2, cto_as);
++		updated = 1;
++	}
++
++exit:
++	return updated;
++}
++
++bool rtw_mesh_update_bss_forwarding_state(_adapter *adapter, WLAN_BSSID_EX *bss)
++{
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	u8 forward = mcfg->dot11MeshForwarding;
++	u8 *ie;
++	int ie_len;
++	bool updated = 0;
++
++	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
++			BSS_EX_TLV_IES_LEN(bss));
++	if (!ie || ie_len != 7) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (GET_MESH_CONF_ELE_FORWARDING(ie + 2) != forward) {
++		SET_MESH_CONF_ELE_FORWARDING(ie + 2, forward);
++		updated = 1;
++	}
++
++exit:
++	return updated;
++}
++
++struct mesh_plink_ent *_rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	struct mesh_plink_ent *ent = NULL;
++	int i;
++
++	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
++		if (plink_ctl->ent[i].valid == _TRUE
++			&& _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE
++		) {
++			ent = &plink_ctl->ent[i];
++			break;
++		}
++	}
++
++	return ent;
++}
++
++struct mesh_plink_ent *rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	struct mesh_plink_ent *ent = NULL;
++	_irqL irqL;
++
++	_enter_critical_bh(&(plink_ctl->lock), &irqL);
++	ent = _rtw_mesh_plink_get(adapter, hwaddr);
++	_exit_critical_bh(&(plink_ctl->lock), &irqL);
++
++	return ent;
++}
++
++struct mesh_plink_ent *rtw_mesh_plink_get_no_estab_by_idx(_adapter *adapter, u8 idx)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	struct mesh_plink_ent *ent = NULL;
++	int i, j = 0;
++	_irqL irqL;
++
++	_enter_critical_bh(&(plink_ctl->lock), &irqL);
++	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
++		if (plink_ctl->ent[i].valid == _TRUE
++			&& plink_ctl->ent[i].plink_state != RTW_MESH_PLINK_ESTAB
++		) {
++			if (j == idx) {
++				ent = &plink_ctl->ent[i];
++				break;
++			}
++			j++;
++		}
++	}
++	_exit_critical_bh(&(plink_ctl->lock), &irqL);
++
++	return ent;
++}
++
++int _rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	struct mesh_plink_ent *ent = NULL;
++	u8 exist = _FALSE;
++	int i;
++
++	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
++		if (plink_ctl->ent[i].valid == _TRUE
++			&& _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE
++		) {
++			ent = &plink_ctl->ent[i];
++			exist = _TRUE;
++			break;
++		}
++
++		if (ent == NULL && plink_ctl->ent[i].valid == _FALSE)
++			ent = &plink_ctl->ent[i];
++	}
++
++	if (exist == _FALSE && ent) {
++		_rtw_memcpy(ent->addr, hwaddr, ETH_ALEN);
++		ent->valid = _TRUE;
++		#ifdef CONFIG_RTW_MESH_AEK
++		ent->aek_valid = 0;
++		#endif
++		ent->llid = 0;
++		ent->plid = 0;
++		_rtw_memset(ent->chosen_pmk, 0, 16);
++		#ifdef CONFIG_RTW_MESH_AEK
++		_rtw_memset(ent->sel_pcs, 0, 4);
++		_rtw_memset(ent->l_nonce, 0, 32);
++		_rtw_memset(ent->p_nonce, 0, 32);
++		#endif
++		ent->plink_state = RTW_MESH_PLINK_LISTEN;
++		#ifndef CONFIG_RTW_MESH_DRIVER_AID
++		ent->aid = 0;
++		#endif
++		ent->peer_aid = 0;
++		SET_PEER_CONF_DISABLED(ent);
++		SET_CTO_MGATE_CONF_DISABLED(ent);
++		plink_ctl->num++;
++	}
++
++	return exist == _TRUE ? RTW_ALREADY : (ent ? _SUCCESS : _FAIL);
++}
++
++int rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	_irqL irqL;
++	int ret;
++
++	_enter_critical_bh(&(plink_ctl->lock), &irqL);
++	ret = _rtw_mesh_plink_add(adapter, hwaddr);
++	_exit_critical_bh(&(plink_ctl->lock), &irqL);
++
++	return ret;
++}
++
++int rtw_mesh_plink_set_state(_adapter *adapter, const u8 *hwaddr, u8 state)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	struct mesh_plink_ent *ent = NULL;
++	_irqL irqL;
++
++	_enter_critical_bh(&(plink_ctl->lock), &irqL);
++	ent = _rtw_mesh_plink_get(adapter, hwaddr);
++	if (ent)
++		ent->plink_state = state;
++	_exit_critical_bh(&(plink_ctl->lock), &irqL);
++
++	return ent ? _SUCCESS : _FAIL;
++}
++
++#ifdef CONFIG_RTW_MESH_AEK
++int rtw_mesh_plink_set_aek(_adapter *adapter, const u8 *hwaddr, const u8 *aek)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	struct mesh_plink_ent *ent = NULL;
++	_irqL irqL;
++
++	_enter_critical_bh(&(plink_ctl->lock), &irqL);
++	ent = _rtw_mesh_plink_get(adapter, hwaddr);
++	if (ent) {
++		_rtw_memcpy(ent->aek, aek, 32);
++		ent->aek_valid = 1;
++	}
++	_exit_critical_bh(&(plink_ctl->lock), &irqL);
++
++	return ent ? _SUCCESS : _FAIL;
++}
++#endif
++
++#if CONFIG_RTW_MESH_PEER_BLACKLIST
++int rtw_mesh_plink_set_peer_conf_timeout(_adapter *adapter, const u8 *hwaddr)
++{
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	struct mesh_plink_ent *ent = NULL;
++	_irqL irqL;
++
++	_enter_critical_bh(&(plink_ctl->lock), &irqL);
++	ent = _rtw_mesh_plink_get(adapter, hwaddr);
++	if (ent) {
++		if (IS_PEER_CONF_DISABLED(ent))
++			SET_PEER_CONF_END_TIME(ent, mcfg->peer_sel_policy.peer_conf_timeout_ms);
++	}
++	_exit_critical_bh(&(plink_ctl->lock), &irqL);
++
++	return ent ? _SUCCESS : _FAIL;
++}
++#endif
++
++void _rtw_mesh_plink_del_ent(_adapter *adapter, struct mesh_plink_ent *ent)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++
++	ent->valid = _FALSE;
++	#ifdef CONFIG_RTW_MESH_DRIVER_AID
++	if (ent->tx_conf_ies && ent->tx_conf_ies_len)
++		rtw_mfree(ent->tx_conf_ies, ent->tx_conf_ies_len);
++	ent->tx_conf_ies = NULL;
++	ent->tx_conf_ies_len = 0;
++	#endif
++	if (ent->rx_conf_ies && ent->rx_conf_ies_len)
++		rtw_mfree(ent->rx_conf_ies, ent->rx_conf_ies_len);
++	ent->rx_conf_ies = NULL;
++	ent->rx_conf_ies_len = 0;
++	if (ent->scanned)
++		ent->scanned = NULL;
++	plink_ctl->num--;
++}
++
++int rtw_mesh_plink_del(_adapter *adapter, const u8 *hwaddr)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	struct mesh_plink_ent *ent = NULL;
++	u8 exist = _FALSE;
++	int i;
++	_irqL irqL;
++
++	_enter_critical_bh(&(plink_ctl->lock), &irqL);
++	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
++		if (plink_ctl->ent[i].valid == _TRUE
++			&& _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE
++		) {
++			ent = &plink_ctl->ent[i];
++			exist = _TRUE;
++			break;
++		}
++	}
++
++	if (exist == _TRUE)
++		_rtw_mesh_plink_del_ent(adapter, ent);
++
++	_exit_critical_bh(&(plink_ctl->lock), &irqL);
++
++	return exist == _TRUE ? _SUCCESS : RTW_ALREADY;
++}
++
++void rtw_mesh_plink_ctl_init(_adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	int i;
++
++	_rtw_spinlock_init(&plink_ctl->lock);
++	plink_ctl->num = 0;
++	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++)
++		plink_ctl->ent[i].valid = _FALSE;
++
++#if CONFIG_RTW_MESH_PEER_BLACKLIST
++	_rtw_init_queue(&plink_ctl->peer_blacklist);
++#endif
++#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++	_rtw_init_queue(&plink_ctl->cto_mgate_blacklist);
++#endif
++}
++
++void rtw_mesh_plink_ctl_deinit(_adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	struct mesh_plink_ent *ent;
++	int i;
++	_irqL irqL;
++
++	_enter_critical_bh(&(plink_ctl->lock), &irqL);
++	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
++		ent = &plink_ctl->ent[i];
++		#ifdef CONFIG_RTW_MESH_DRIVER_AID
++		if (ent->tx_conf_ies && ent->tx_conf_ies_len)
++			rtw_mfree(ent->tx_conf_ies, ent->tx_conf_ies_len);
++		#endif
++		if (ent->rx_conf_ies && ent->rx_conf_ies_len)
++			rtw_mfree(ent->rx_conf_ies, ent->rx_conf_ies_len);
++	}
++	_exit_critical_bh(&(plink_ctl->lock), &irqL);
++
++	_rtw_spinlock_free(&plink_ctl->lock);
++
++#if CONFIG_RTW_MESH_PEER_BLACKLIST
++	rtw_mesh_peer_blacklist_flush(adapter);
++	_rtw_deinit_queue(&plink_ctl->peer_blacklist);
++#endif
++#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++	rtw_mesh_cto_mgate_blacklist_flush(adapter);
++	_rtw_deinit_queue(&plink_ctl->cto_mgate_blacklist);
++#endif
++}
++
++void dump_mesh_plink_ctl(void *sel, _adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	struct mesh_plink_ent *ent;
++	int i;
++
++	RTW_PRINT_SEL(sel, "num:%u\n", plink_ctl->num);
++	#if CONFIG_RTW_MESH_ACNODE_PREVENT
++	RTW_PRINT_SEL(sel, "acnode_rsvd:%u\n", plink_ctl->acnode_rsvd);
++	#endif
++
++	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++)  {
++		ent = &plink_ctl->ent[i];
++		if (!ent->valid)
++			continue;
++
++		RTW_PRINT_SEL(sel, "\n");
++		RTW_PRINT_SEL(sel, "peer:"MAC_FMT"\n", MAC_ARG(ent->addr));
++		RTW_PRINT_SEL(sel, "plink_state:%s\n", rtw_mesh_plink_str(ent->plink_state));
++
++		#ifdef CONFIG_RTW_MESH_AEK
++		if (ent->aek_valid)
++			RTW_PRINT_SEL(sel, "aek:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->aek), KEY_ARG(ent->aek + 16));
++		#endif
++
++		RTW_PRINT_SEL(sel, "llid:%u, plid:%u\n", ent->llid, ent->plid);
++		#ifndef CONFIG_RTW_MESH_DRIVER_AID
++		RTW_PRINT_SEL(sel, "aid:%u\n", ent->aid);
++		#endif
++		RTW_PRINT_SEL(sel, "peer_aid:%u\n", ent->peer_aid);
++
++		RTW_PRINT_SEL(sel, "chosen_pmk:"KEY_FMT"\n", KEY_ARG(ent->chosen_pmk));
++
++		#ifdef CONFIG_RTW_MESH_AEK
++		RTW_PRINT_SEL(sel, "sel_pcs:%02x%02x%02x%02x\n"
++			, ent->sel_pcs[0], ent->sel_pcs[1], ent->sel_pcs[2], ent->sel_pcs[3]);
++		RTW_PRINT_SEL(sel, "l_nonce:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->l_nonce), KEY_ARG(ent->l_nonce + 16));
++		RTW_PRINT_SEL(sel, "p_nonce:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->p_nonce), KEY_ARG(ent->p_nonce + 16));
++		#endif
++
++		#ifdef CONFIG_RTW_MESH_DRIVER_AID
++		RTW_PRINT_SEL(sel, "tx_conf_ies:%p, len:%u\n", ent->tx_conf_ies, ent->tx_conf_ies_len);
++		#endif
++		RTW_PRINT_SEL(sel, "rx_conf_ies:%p, len:%u\n", ent->rx_conf_ies, ent->rx_conf_ies_len);
++		RTW_PRINT_SEL(sel, "scanned:%p\n", ent->scanned);
++
++		#if CONFIG_RTW_MESH_PEER_BLACKLIST
++		if (!IS_PEER_CONF_DISABLED(ent)) {
++			if (!IS_PEER_CONF_TIMEOUT(ent))
++				RTW_PRINT_SEL(sel, "peer_conf:%d\n", rtw_systime_to_ms(ent->peer_conf_end_time - rtw_get_current_time()));
++			else
++				RTW_PRINT_SEL(sel, "peer_conf:TIMEOUT\n");
++		}
++		#endif
++
++		#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++		if (!IS_CTO_MGATE_CONF_DISABLED(ent)) {
++			if (!IS_CTO_MGATE_CONF_TIMEOUT(ent))
++				RTW_PRINT_SEL(sel, "cto_mgate_conf:%d\n", rtw_systime_to_ms(ent->cto_mgate_conf_end_time - rtw_get_current_time()));
++			else
++				RTW_PRINT_SEL(sel, "cto_mgate_conf:TIMEOUT\n");
++		}
++		#endif
++	}
++}
++
++/* this function is called with plink_ctl being locked */
++static int rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *plink, struct sta_info *sta)
++{
++#ifndef DBG_RTW_MESH_PEER_ESTABLISH
++#define DBG_RTW_MESH_PEER_ESTABLISH 0
++#endif
++
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	u8 *tlv_ies;
++	u16 tlv_ieslen;
++	struct rtw_ieee802_11_elems elems;
++	_irqL irqL;
++	int i;
++	u16 status = 0;
++	int ret = _FAIL;
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	u8 sta_tbtx_enable = _FALSE;
++#endif
++
++	if (!plink->rx_conf_ies || !plink->rx_conf_ies_len) {
++		RTW_INFO(FUNC_ADPT_FMT" no rx confirm from sta "MAC_FMT"\n"
++			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
++		goto exit;
++	}
++
++	if (plink->rx_conf_ies_len < 4) {
++		RTW_INFO(FUNC_ADPT_FMT" confirm from sta "MAC_FMT" too short\n"
++			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
++		goto exit;
++	}
++
++#ifdef CONFIG_RTW_MESH_DRIVER_AID
++	if (!plink->tx_conf_ies || !plink->tx_conf_ies_len) {
++		RTW_INFO(FUNC_ADPT_FMT" no tx confirm to sta "MAC_FMT"\n"
++			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
++		goto exit;
++	}
++
++	if (plink->tx_conf_ies_len < 4) {
++		RTW_INFO(FUNC_ADPT_FMT" confirm to sta "MAC_FMT" too short\n"
++			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
++		goto exit;
++	}
++#endif
++
++	tlv_ies = plink->rx_conf_ies + 4;
++	tlv_ieslen = plink->rx_conf_ies_len - 4;
++
++	if (DBG_RTW_MESH_PEER_ESTABLISH)
++		dump_ies(RTW_DBGDUMP, tlv_ies, tlv_ieslen);
++
++	if (rtw_ieee802_11_parse_elems(tlv_ies, tlv_ieslen, &elems, 1) == ParseFailed) {
++		RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" sent invalid confirm\n"
++			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
++		goto exit;
++	}
++
++	SET_PEER_CONF_DISABLED(plink);
++	if (rtw_bss_is_cto_mgate(&plink->scanned->network)
++		&& !rtw_bss_is_forwarding(&plink->scanned->network))
++		SET_CTO_MGATE_CONF_END_TIME(plink, mcfg->peer_sel_policy.cto_mgate_conf_timeout_ms);
++	else
++		SET_CTO_MGATE_CONF_DISABLED(plink);
++
++	sta->state &= (~WIFI_FW_AUTH_SUCCESS);
++	sta->state |= WIFI_FW_ASSOC_STATE;
++
++	rtw_ap_parse_sta_capability(adapter, sta, plink->rx_conf_ies);
++
++	status = rtw_ap_parse_sta_supported_rates(adapter, sta, tlv_ies, tlv_ieslen);
++	if (status != _STATS_SUCCESSFUL_)
++		goto exit;
++
++	status = rtw_ap_parse_sta_security_ie(adapter, sta, &elems);
++	if (status != _STATS_SUCCESSFUL_) {
++		RTW_INFO(FUNC_ADPT_FMT" security check fail, status=%u\n", FUNC_ADPT_ARG(adapter), status);
++		goto exit;
++	}
++
++	rtw_ap_parse_sta_wmm_ie(adapter, sta, tlv_ies, tlv_ieslen);
++#ifdef CONFIG_RTS_FULL_BW
++	/*check vendor IE*/
++	rtw_parse_sta_vendor_ie_8812(adapter, sta, tlv_ies, tlv_ieslen);
++#endif/*CONFIG_RTS_FULL_BW*/
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	if (elems.tbtx_cap && elems.tbtx_cap_len != 0) {
++		if(rtw_is_tbtx_capabilty(elems.tbtx_cap, elems.tbtx_cap_len)) {
++			sta_tbtx_enable = _TRUE;
++		}
++	}
++#endif
++
++	rtw_ap_parse_sta_ht_ie(adapter, sta, &elems);
++	rtw_ap_parse_sta_vht_ie(adapter, sta, &elems);
++
++	/* AID */
++#ifdef CONFIG_RTW_MESH_DRIVER_AID
++	sta->cmn.aid = RTW_GET_LE16(plink->tx_conf_ies + 2);
++#else
++	sta->cmn.aid = plink->aid;
++#endif
++	stapriv->sta_aid[sta->cmn.aid - 1] = sta;
++	RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" aid:%u\n"
++		, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr), sta->cmn.aid);
++
++	sta->state &= (~WIFI_FW_ASSOC_STATE);
++	sta->state |= WIFI_FW_ASSOC_SUCCESS;
++
++	sta->local_mps = RTW_MESH_PS_ACTIVE;
++
++	rtw_ewma_err_rate_init(&sta->metrics.err_rate);
++	rtw_ewma_err_rate_add(&sta->metrics.err_rate, 1);
++	/* init data_rate to 1M */
++	sta->metrics.data_rate = 10;
++	sta->alive = _TRUE;
++
++	_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
++	if (rtw_is_list_empty(&sta->asoc_list)) {
++		STA_SET_MESH_PLINK(sta, plink);
++		/* TBD: up layer timeout mechanism */
++		/* sta->expire_to = mcfg->plink_timeout / 2; */
++		rtw_list_insert_tail(&sta->asoc_list, &stapriv->asoc_list);
++		stapriv->asoc_list_cnt++;
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++		if (sta_tbtx_enable) {
++			sta->tbtx_enable = _TRUE;
++			stapriv->tbtx_asoc_list_cnt++;
++		}
++#endif
++	}
++	_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
++
++	bss_cap_update_on_sta_join(adapter, sta);
++	sta_info_update(adapter, sta);
++	report_add_sta_event(adapter, sta->cmn.mac_addr);
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++
++int rtw_mesh_set_plink_state(_adapter *adapter, const u8 *mac, u8 plink_state)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	struct mesh_plink_ent *plink = NULL;
++	_irqL irqL2;
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct sta_info *sta = NULL;
++	_irqL irqL;
++	struct sta_info *del_sta = NULL;
++	int ret = _SUCCESS;
++
++	_enter_critical_bh(&(plink_ctl->lock), &irqL2);
++
++	plink = _rtw_mesh_plink_get(adapter, mac);
++	if (!plink) {
++		ret = _FAIL;
++		goto release_plink_ctl;
++	}
++
++	plink->plink_state = plink_state;
++
++	#if CONFIG_RTW_MESH_ACNODE_PREVENT
++	if (plink_state == RTW_MESH_PLINK_OPN_SNT) {
++		if (rtw_mesh_scanned_is_acnode_confirmed(adapter, plink->scanned)
++			&& rtw_mesh_acnode_prevent_allow_sacrifice(adapter)
++		) {
++			struct sta_info *sac = rtw_mesh_acnode_prevent_pick_sacrifice(adapter);
++
++			if (sac) {
++				del_sta = sac;
++				_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
++				if (!rtw_is_list_empty(&del_sta->asoc_list)) {
++					rtw_list_delete(&del_sta->asoc_list);
++					stapriv->asoc_list_cnt--;
++					#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++					if (del_sta->tbtx_enable)
++						stapriv->tbtx_asoc_list_cnt--;
++					#endif
++					STA_SET_MESH_PLINK(del_sta, NULL);
++				}
++				_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
++				RTW_INFO(FUNC_ADPT_FMT" sacrifice "MAC_FMT" for acnode\n"
++					, FUNC_ADPT_ARG(adapter), MAC_ARG(del_sta->cmn.mac_addr));
++			}
++		}
++	} else
++	#endif
++	if (plink_state == RTW_MESH_PLINK_OPN_RCVD
++		|| plink_state == RTW_MESH_PLINK_CNF_RCVD
++		|| plink_state == RTW_MESH_PLINK_ESTAB
++	) {
++		sta = rtw_get_stainfo(stapriv, mac);
++		if (!sta) {
++			sta = rtw_alloc_stainfo(stapriv, mac);
++			if (!sta)
++				goto release_plink_ctl;
++		}
++
++		if (plink_state == RTW_MESH_PLINK_ESTAB) {
++			if (rtw_mesh_peer_establish(adapter, plink, sta) != _SUCCESS) {
++				del_sta = sta;
++				ret = _FAIL;
++				goto release_plink_ctl;
++			}
++		}
++	}
++	else if (plink_state == RTW_MESH_PLINK_HOLDING) {
++		del_sta = rtw_get_stainfo(stapriv, mac);
++		if (!del_sta)
++			goto release_plink_ctl;
++
++		_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
++		if (!rtw_is_list_empty(&del_sta->asoc_list)) {
++			rtw_list_delete(&del_sta->asoc_list);
++			stapriv->asoc_list_cnt--;
++			#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++			if (del_sta->tbtx_enable)
++				stapriv->tbtx_asoc_list_cnt--;
++			#endif
++			STA_SET_MESH_PLINK(del_sta, NULL);
++		}
++		_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
++	}
++
++release_plink_ctl:
++	_exit_critical_bh(&(plink_ctl->lock), &irqL2);
++
++	if (del_sta) {
++		u8 sta_addr[ETH_ALEN];
++		u8 updated = _FALSE;
++
++		_rtw_memcpy(sta_addr, del_sta->cmn.mac_addr, ETH_ALEN);
++		updated = ap_free_sta(adapter, del_sta, 0, 0, 1);
++		rtw_mesh_expire_peer(stapriv->padapter, sta_addr);
++
++		associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL);
++	}
++
++	return ret;
++}
++
++struct mesh_set_plink_cmd_parm {
++	const u8 *mac;
++	u8 plink_state;
++};
++
++u8 rtw_mesh_set_plink_state_cmd_hdl(_adapter *adapter, u8 *parmbuf)
++{
++	struct mesh_set_plink_cmd_parm *parm = (struct mesh_set_plink_cmd_parm *)parmbuf;
++
++	if (rtw_mesh_set_plink_state(adapter, parm->mac, parm->plink_state) == _SUCCESS)
++		return	H2C_SUCCESS;
++
++	return H2C_CMD_FAIL;
++}
++
++u8 rtw_mesh_set_plink_state_cmd(_adapter *adapter, const u8 *mac, u8 plink_state)
++{
++	struct cmd_obj *cmdobj;
++	struct mesh_set_plink_cmd_parm *parm;
++	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
++	struct submit_ctx sctx;
++	u8 res = _SUCCESS;
++
++	/* prepare cmd parameter */
++	parm = rtw_zmalloc(sizeof(*parm));
++	if (parm == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++	parm->mac = mac;
++	parm->plink_state = plink_state;
++
++	/* need enqueue, prepare cmd_obj and enqueue */
++	cmdobj = rtw_zmalloc(sizeof(*cmdobj));
++	if (cmdobj == NULL) {
++		res = _FAIL;
++		rtw_mfree(parm, sizeof(*parm));
++		goto exit;
++	}
++
++	init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_MESH_PLINK_STATE);
++	cmdobj->sctx = &sctx;
++	rtw_sctx_init(&sctx, 2000);
++
++	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
++	if (res == _SUCCESS) {
++		rtw_sctx_wait(&sctx, __func__);
++		_enter_critical_mutex(&cmdpriv->sctx_mutex, NULL);
++		if (sctx.status == RTW_SCTX_SUBMITTED)
++			cmdobj->sctx = NULL;
++		_exit_critical_mutex(&cmdpriv->sctx_mutex, NULL);
++		if (sctx.status != RTW_SCTX_DONE_SUCCESS)
++			res = _FAIL;
++	}
++
++exit:
++	return res;
++}
++
++void rtw_mesh_expire_peer_notify(_adapter *adapter, const u8 *peer_addr)
++{
++	u8 null_ssid[2] = {0, 0};
++
++#ifdef CONFIG_IOCTL_CFG80211
++	rtw_cfg80211_notify_new_peer_candidate(adapter->rtw_wdev
++		, peer_addr
++		, null_ssid
++		, 2
++		, 0
++		, GFP_ATOMIC
++	);
++#endif
++
++	return;
++}
++
++static u8 *rtw_mesh_construct_peer_mesh_close(_adapter *adapter, struct mesh_plink_ent *plink, u16 reason, u32 *len)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	u8 *frame = NULL, *pos;
++	u32 flen;
++	struct rtw_ieee80211_hdr *whdr;
++
++	if (minfo->mesh_auth_id && !MESH_PLINK_AEK_VALID(plink))
++		goto exit;
++
++	flen = sizeof(struct rtw_ieee80211_hdr_3addr)
++		+ 2 /* category, action */
++		+ 2 + minfo->mesh_id_len /* mesh id */
++		+ 2 + 8 + (minfo->mesh_auth_id ? 16 : 0) /* mpm */
++		+ (minfo->mesh_auth_id ? 2 + 16 /* AES_BLOCK_SIZE */ : 0) /* mic */
++		+ (minfo->mesh_auth_id ? 70 : 0) /* ampe */
++		;
++
++	pos = frame = rtw_zmalloc(flen);
++	if (!frame)
++		goto exit;
++
++	whdr = (struct rtw_ieee80211_hdr *)frame;
++	_rtw_memcpy(whdr->addr1, adapter_mac_addr(adapter), ETH_ALEN);
++	_rtw_memcpy(whdr->addr2, plink->addr, ETH_ALEN);
++	_rtw_memcpy(whdr->addr3, adapter_mac_addr(adapter), ETH_ALEN);
++
++	set_frame_sub_type(frame, WIFI_ACTION);
++
++	pos += sizeof(struct rtw_ieee80211_hdr_3addr);
++	*(pos++) = RTW_WLAN_CATEGORY_SELF_PROTECTED;
++	*(pos++) = RTW_ACT_SELF_PROTECTED_MESH_CLOSE;
++
++	pos = rtw_set_ie_mesh_id(pos, NULL, minfo->mesh_id, minfo->mesh_id_len);
++
++	pos = rtw_set_ie_mpm(pos, NULL
++		, minfo->mesh_auth_id ? 1 : 0
++		, plink->plid
++		, &plink->llid
++		, &reason
++		, minfo->mesh_auth_id ? plink->chosen_pmk : NULL);
++
++#ifdef CONFIG_RTW_MESH_AEK
++	if (minfo->mesh_auth_id) {
++		u8 ampe_buf[70];
++		int enc_ret;
++
++		*pos = WLAN_EID_MIC;
++		*(pos + 1) = 16 /* AES_BLOCK_SIZE */;
++
++		ampe_buf[0] = WLAN_EID_AMPE;
++		ampe_buf[1] = 68;
++		_rtw_memcpy(ampe_buf + 2, plink->sel_pcs, 4);
++		_rtw_memcpy(ampe_buf + 6, plink->p_nonce, 32);
++		_rtw_memcpy(ampe_buf + 38, plink->l_nonce, 32);
++
++		enc_ret = rtw_mpm_ampe_enc(adapter, plink
++			, frame + sizeof(struct rtw_ieee80211_hdr_3addr)
++			, pos, ampe_buf, 1);
++		if (enc_ret != _SUCCESS) {
++			rtw_mfree(frame, flen);
++			frame = NULL;
++			goto exit;
++		}
++	}
++#endif
++
++	*len = flen;
++
++exit:
++	return frame;
++}
++
++void _rtw_mesh_expire_peer_ent(_adapter *adapter, struct mesh_plink_ent *plink)
++{
++#if defined(CONFIG_RTW_MESH_STA_DEL_DISASOC)
++	_rtw_mesh_plink_del_ent(adapter, plink);
++	rtw_cfg80211_indicate_sta_disassoc(adapter, plink->addr, 0);
++#else
++	u8 *frame = NULL;
++	u32 flen;
++
++	if (plink->plink_state == RTW_MESH_PLINK_ESTAB)
++		frame = rtw_mesh_construct_peer_mesh_close(adapter, plink, WLAN_REASON_MESH_CLOSE, &flen);
++
++	if (frame) {
++		struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++		struct wireless_dev *wdev = adapter->rtw_wdev;
++		s32 freq = rtw_ch2freq(mlmeext->cur_channel);
++
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++		rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, flen, GFP_ATOMIC);
++		#else
++		cfg80211_rx_action(adapter->pnetdev, freq, frame, flen, GFP_ATOMIC);
++		#endif
++
++		rtw_mfree(frame, flen);
++	} else {
++		rtw_mesh_expire_peer_notify(adapter, plink->addr);
++		RTW_INFO(FUNC_ADPT_FMT" set "MAC_FMT" plink unknown\n"
++			, FUNC_ADPT_ARG(adapter), MAC_ARG(plink->addr));
++		plink->plink_state = RTW_MESH_PLINK_UNKNOWN;
++	}
++#endif
++}
++
++void rtw_mesh_expire_peer(_adapter *adapter, const u8 *peer_addr)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++	struct mesh_plink_ent *plink;
++	_irqL irqL;
++
++	_enter_critical_bh(&(plink_ctl->lock), &irqL);
++
++	plink = _rtw_mesh_plink_get(adapter, peer_addr);
++	if (!plink)
++		goto exit;
++
++	_rtw_mesh_expire_peer_ent(adapter, plink);
++
++exit:
++	_exit_critical_bh(&(plink_ctl->lock), &irqL);
++}
++
++u8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps)
++{
++	_irqL irqL;
++	_list *head, *list;
++	struct sta_info *sta;
++	struct sta_priv *stapriv = &adapter->stapriv;
++	u8 sta_alive_num = 0, i;
++	char sta_alive_list[NUM_STA];
++	u8 annc_cnt = 0;
++
++	if (rtw_linked_check(adapter) == _FALSE)
++		goto exit;
++
++	_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
++
++	head = &stapriv->asoc_list;
++	list = get_next(head);
++	while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
++		int stainfo_offset;
++
++		sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
++		list = get_next(list);
++
++		stainfo_offset = rtw_stainfo_offset(stapriv, sta);
++		if (stainfo_offset_valid(stainfo_offset))
++			sta_alive_list[sta_alive_num++] = stainfo_offset;
++	}
++	_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
++
++	for (i = 0; i < sta_alive_num; i++) {
++		sta = rtw_get_stainfo_by_offset(stapriv, sta_alive_list[i]);
++		if (!sta)
++			continue;
++
++		issue_qos_nulldata(adapter, sta->cmn.mac_addr, 7, ps, 3, 500);
++		annc_cnt++;
++	}
++
++exit:
++	return annc_cnt;
++}
++
++static void mpath_tx_tasklet_hdl(void *priv)
++{
++	_adapter *adapter = (_adapter *)priv;
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct xmit_frame *xframe;
++	_list *list, *head;
++	_list tmp;
++	u32 tmp_len;
++	s32 res;
++
++	_rtw_init_listhead(&tmp);
++
++	while (1) {
++		tmp_len = 0;
++		enter_critical_bh(&minfo->mpath_tx_queue.lock);
++		if (minfo->mpath_tx_queue_len) {
++			rtw_list_splice_init(&minfo->mpath_tx_queue.queue, &tmp);
++			tmp_len = minfo->mpath_tx_queue_len;
++			minfo->mpath_tx_queue_len = 0;
++		}
++		exit_critical_bh(&minfo->mpath_tx_queue.lock);
++
++		if (!tmp_len)
++			break;
++
++		head = &tmp;
++		list = get_next(head);
++		while (rtw_end_of_queue_search(head, list) == _FALSE) {
++			xframe = LIST_CONTAINOR(list, struct xmit_frame, list);
++			list = get_next(list);
++			rtw_list_delete(&xframe->list);
++			res = rtw_xmit_posthandle(adapter, xframe, xframe->pkt);
++			if (res < 0) {
++				#ifdef DBG_TX_DROP_FRAME
++				RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__);
++				#endif
++				adapter->xmitpriv.tx_drop++;
++			}
++		}
++	}
++}
++
++static void rtw_mpath_tx_queue_flush(_adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct xmit_frame *xframe;
++	_list *list, *head;
++	_list tmp;
++
++	_rtw_init_listhead(&tmp);
++
++	enter_critical_bh(&minfo->mpath_tx_queue.lock);
++	rtw_list_splice_init(&minfo->mpath_tx_queue.queue, &tmp);
++	minfo->mpath_tx_queue_len = 0;
++	exit_critical_bh(&minfo->mpath_tx_queue.lock);
++
++	head = &tmp;
++	list = get_next(head);
++	while (rtw_end_of_queue_search(head, list) == _FALSE) {
++		xframe = LIST_CONTAINOR(list, struct xmit_frame, list);
++		list = get_next(list);
++		rtw_list_delete(&xframe->list);
++		rtw_free_xmitframe(&adapter->xmitpriv, xframe);
++	}
++}
++
++#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
++#if defined(CONFIG_SLUB)
++#include <linux/slub_def.h>
++#elif defined(CONFIG_SLAB)
++#include <linux/slab_def.h>
++#endif
++typedef struct kmem_cache rtw_mcache;
++#endif
++
++rtw_mcache *rtw_mcache_create(const char *name, size_t size)
++{
++#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
++	return kmem_cache_create(name, size, 0, 0, NULL);
++#else
++	#error "TBD\n";
++#endif
++}
++
++void rtw_mcache_destroy(rtw_mcache *s)
++{
++#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
++	kmem_cache_destroy(s);
++#else
++	#error "TBD\n";
++#endif
++}
++
++void *_rtw_mcache_alloc(rtw_mcache *cachep)
++{
++#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
++	return kmem_cache_alloc(cachep, GFP_ATOMIC);
++#else
++	#error "TBD\n";
++#endif
++}
++
++void _rtw_mcache_free(rtw_mcache *cachep, void *objp)
++{
++#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
++	kmem_cache_free(cachep, objp);
++#else
++	#error "TBD\n";
++#endif
++}
++
++#ifdef DBG_MEM_ALLOC
++inline void *dbg_rtw_mcache_alloc(rtw_mcache *cachep, const enum mstat_f flags, const char *func, const int line)
++{
++	void *p;
++	u32 sz = cachep->size;
++
++	if (match_mstat_sniff_rules(flags, sz))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u)\n", func, line, __func__, sz);
++
++	p = _rtw_mcache_alloc(cachep);
++
++	rtw_mstat_update(
++		flags
++		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++		, sz
++	);
++
++	return p;
++}
++
++inline void dbg_rtw_mcache_free(rtw_mcache *cachep, void *pbuf, const enum mstat_f flags, const char *func, const int line)
++{
++	u32 sz = cachep->size;
++
++	if (match_mstat_sniff_rules(flags, sz))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u)\n", func, line, __func__, sz);
++
++	_rtw_mcache_free(cachep, pbuf);
++
++	rtw_mstat_update(
++		flags
++		, MSTAT_FREE
++		, sz
++	);
++}
++
++#define rtw_mcache_alloc(cachep) dbg_rtw_mcache_alloc(cachep, MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_mcache_free(cachep, objp) dbg_rtw_mcache_free(cachep, objp, MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#else
++#define rtw_mcache_alloc(cachep) _rtw_mcache_alloc(cachep)
++#define rtw_mcache_free(cachep, objp) _rtw_mcache_free(cachep, objp)
++#endif /* DBG_MEM_ALLOC */
++
++/* Mesh Received Cache */
++#define RTW_MRC_BUCKETS			256 /* must be a power of 2 */
++#define RTW_MRC_QUEUE_MAX_LEN	4
++#define RTW_MRC_TIMEOUT_MS		(3 * 1000)
++
++/**
++ * struct rtw_mrc_entry - entry in the Mesh Received Cache
++ *
++ * @seqnum: mesh sequence number of the frame
++ * @exp_time: expiration time of the entry
++ * @msa: mesh source address of the frame
++ * @list: hashtable list pointer
++ *
++ * The Mesh Received Cache keeps track of the latest received frames that
++ * have been received by a mesh interface and discards received frames
++ * that are found in the cache.
++ */
++struct rtw_mrc_entry {
++	rtw_hlist_node list;
++	systime exp_time;
++	u32 seqnum;
++	u8 msa[ETH_ALEN];
++};
++
++struct rtw_mrc {
++	rtw_hlist_head bucket[RTW_MRC_BUCKETS];
++	u32 idx_mask;
++	rtw_mcache *cache;
++};
++
++static int rtw_mrc_init(_adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	char cache_name[IFNAMSIZ + 8 + 1];
++	int i;
++
++	minfo->mrc = rtw_malloc(sizeof(struct rtw_mrc));
++	if (!minfo->mrc)
++		return -ENOMEM;
++	minfo->mrc->idx_mask = RTW_MRC_BUCKETS - 1;
++	for (i = 0; i < RTW_MRC_BUCKETS; i++)
++		rtw_hlist_head_init(&minfo->mrc->bucket[i]);
++
++	sprintf(cache_name, "rtw_mrc_%s", ADPT_ARG(adapter));
++	minfo->mrc->cache = rtw_mcache_create(cache_name, sizeof(struct rtw_mrc_entry));
++
++	return 0;
++}
++
++static void rtw_mrc_free(_adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct rtw_mrc *mrc = minfo->mrc;
++	struct rtw_mrc_entry *p;
++	rtw_hlist_node *np, *n;
++	int i;
++
++	if (!mrc)
++		return;
++
++	for (i = 0; i < RTW_MRC_BUCKETS; i++) {
++		rtw_hlist_for_each_entry_safe(p, np, n, &mrc->bucket[i], list) {
++			rtw_hlist_del(&p->list);
++			rtw_mcache_free(mrc->cache, p);
++		}
++	}
++
++	rtw_mcache_destroy(mrc->cache);
++
++	rtw_mfree(mrc, sizeof(struct rtw_mrc));
++	minfo->mrc = NULL;
++}
++
++/**
++ * rtw_mrc_check - Check frame in mesh received cache and add if absent.
++ *
++ * @adapter:	interface
++ * @msa:		mesh source address
++ * @seq:		mesh seq number
++ *
++ * Returns: 0 if the frame is not in the cache, nonzero otherwise.
++ *
++ * Checks using the mesh source address and the mesh sequence number if we have
++ * received this frame lately. If the frame is not in the cache, it is added to
++ * it.
++ */
++static int rtw_mrc_check(_adapter *adapter, const u8 *msa, u32 seq)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct rtw_mrc *mrc = minfo->mrc;
++	int entries = 0;
++	u8 idx;
++	struct rtw_mrc_entry *p;
++	rtw_hlist_node *np, *n;
++	u8 timeout;
++
++	if (!mrc)
++		return -1;
++
++	idx = seq & mrc->idx_mask;
++	rtw_hlist_for_each_entry_safe(p, np, n, &mrc->bucket[idx], list) {
++		++entries;
++		timeout = rtw_time_after(rtw_get_current_time(), p->exp_time);
++		if (timeout || entries == RTW_MRC_QUEUE_MAX_LEN) {
++			if (!timeout)
++				minfo->mshstats.mrc_del_qlen++;
++
++			rtw_hlist_del(&p->list);
++			rtw_mcache_free(mrc->cache, p);
++			--entries;
++		} else if ((seq == p->seqnum) && _rtw_memcmp(msa, p->msa, ETH_ALEN) == _TRUE)
++			return -1;
++	}
++
++	p = rtw_mcache_alloc(mrc->cache);
++	if (!p)
++		return 0;
++
++	p->seqnum = seq;
++	p->exp_time = rtw_get_current_time() + rtw_ms_to_systime(RTW_MRC_TIMEOUT_MS);
++	_rtw_memcpy(p->msa, msa, ETH_ALEN);
++	rtw_hlist_add_head(&p->list, &mrc->bucket[idx]);
++	return 0;
++}
++
++static int rtw_mesh_decache(_adapter *adapter, const u8 *msa, u32 seq)
++{
++	return rtw_mrc_check(adapter, msa, seq);
++}
++
++#ifndef RTW_MESH_SCAN_RESULT_EXP_MS
++#define RTW_MESH_SCAN_RESULT_EXP_MS (10 * 1000)
++#endif
++
++#ifndef RTW_MESH_ACNODE_PREVENT
++#define RTW_MESH_ACNODE_PREVENT 0
++#endif
++#ifndef RTW_MESH_ACNODE_CONF_TIMEOUT_MS
++#define RTW_MESH_ACNODE_CONF_TIMEOUT_MS (20 * 1000)
++#endif
++#ifndef RTW_MESH_ACNODE_NOTIFY_TIMEOUT_MS
++#define RTW_MESH_ACNODE_NOTIFY_TIMEOUT_MS (2 * 1000)
++#endif
++
++#ifndef RTW_MESH_OFFCH_CAND
++#define RTW_MESH_OFFCH_CAND 1
++#endif
++#ifndef RTW_MESH_OFFCH_CAND_FIND_INT_MS
++#define RTW_MESH_OFFCH_CAND_FIND_INT_MS (10 * 1000)
++#endif
++
++#ifndef RTW_MESH_PEER_CONF_TIMEOUT_MS
++#define RTW_MESH_PEER_CONF_TIMEOUT_MS (20 * 1000)
++#endif
++#ifndef RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS
++#define RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS (20 * 1000)
++#endif
++
++#ifndef RTW_MESH_CTO_MGATE_REQUIRE
++#define RTW_MESH_CTO_MGATE_REQUIRE 0
++#endif
++#ifndef RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS
++#define RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS (20 * 1000)
++#endif
++#ifndef RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS
++#define RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS (20 * 1000)
++#endif
++
++void rtw_mesh_cfg_init_peer_sel_policy(struct rtw_mesh_cfg *mcfg)
++{
++	struct mesh_peer_sel_policy *sel_policy = &mcfg->peer_sel_policy;
++
++	sel_policy->scanr_exp_ms = RTW_MESH_SCAN_RESULT_EXP_MS;
++
++#if CONFIG_RTW_MESH_ACNODE_PREVENT
++	sel_policy->acnode_prevent = RTW_MESH_ACNODE_PREVENT;
++	sel_policy->acnode_conf_timeout_ms = RTW_MESH_ACNODE_CONF_TIMEOUT_MS;
++	sel_policy->acnode_notify_timeout_ms = RTW_MESH_ACNODE_NOTIFY_TIMEOUT_MS;
++#endif
++
++#if CONFIG_RTW_MESH_OFFCH_CAND
++	sel_policy->offch_cand = RTW_MESH_OFFCH_CAND;
++	sel_policy->offch_find_int_ms = RTW_MESH_OFFCH_CAND_FIND_INT_MS;
++#endif
++
++#if CONFIG_RTW_MESH_PEER_BLACKLIST
++	sel_policy->peer_conf_timeout_ms = RTW_MESH_PEER_CONF_TIMEOUT_MS;
++	sel_policy->peer_blacklist_timeout_ms = RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS;
++#endif
++
++#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++	sel_policy->cto_mgate_require = RTW_MESH_CTO_MGATE_REQUIRE;
++	sel_policy->cto_mgate_conf_timeout_ms = RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS;
++	sel_policy->cto_mgate_blacklist_timeout_ms = RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS;
++#endif
++}
++
++void rtw_mesh_cfg_init(_adapter *adapter)
++{
++	struct registry_priv *regsty = adapter_to_regsty(adapter);
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++
++	mcfg->max_peer_links = RTW_MESH_MAX_PEER_LINKS;
++	mcfg->plink_timeout = RTW_MESH_PEER_LINK_TIMEOUT;
++
++	mcfg->dot11MeshTTL = RTW_MESH_TTL;
++	mcfg->element_ttl = RTW_MESH_DEFAULT_ELEMENT_TTL;
++	mcfg->dot11MeshHWMPmaxPREQretries = RTW_MESH_MAX_PREQ_RETRIES;
++	mcfg->path_refresh_time = RTW_MESH_PATH_REFRESH_TIME;
++	mcfg->min_discovery_timeout = RTW_MESH_MIN_DISCOVERY_TIMEOUT;
++	mcfg->dot11MeshHWMPactivePathTimeout = RTW_MESH_PATH_TIMEOUT;
++	mcfg->dot11MeshHWMPpreqMinInterval = RTW_MESH_PREQ_MIN_INT;
++	mcfg->dot11MeshHWMPperrMinInterval = RTW_MESH_PERR_MIN_INT;
++	mcfg->dot11MeshHWMPnetDiameterTraversalTime = RTW_MESH_DIAM_TRAVERSAL_TIME;
++	mcfg->dot11MeshHWMPRootMode = RTW_IEEE80211_ROOTMODE_NO_ROOT;
++	mcfg->dot11MeshHWMPRannInterval = RTW_MESH_RANN_INTERVAL;
++	mcfg->dot11MeshGateAnnouncementProtocol = _FALSE;
++	mcfg->dot11MeshForwarding = _TRUE;
++	mcfg->rssi_threshold = 0;
++	mcfg->dot11MeshHWMPactivePathToRootTimeout = RTW_MESH_PATH_TO_ROOT_TIMEOUT;
++	mcfg->dot11MeshHWMProotInterval = RTW_MESH_ROOT_INTERVAL;
++	mcfg->dot11MeshHWMPconfirmationInterval = RTW_MESH_ROOT_CONFIRMATION_INTERVAL;
++	mcfg->path_gate_timeout_factor = 3;
++	rtw_mesh_cfg_init_peer_sel_policy(mcfg);
++#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
++	mcfg->sane_metric_delta = RTW_MESH_SANE_METRIC_DELTA;
++	mcfg->max_root_add_chk_cnt = RTW_MESH_MAX_ROOT_ADD_CHK_CNT;
++#endif
++
++#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++	mcfg->b2u_flags_msrc = regsty->msrc_b2u_flags;
++	mcfg->b2u_flags_mfwd = regsty->mfwd_b2u_flags;
++#endif
++}
++
++void rtw_mesh_cfg_init_max_peer_links(_adapter *adapter, u8 stack_conf)
++{
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++
++	mcfg->max_peer_links = RTW_MESH_MAX_PEER_LINKS;
++
++	if (mcfg->max_peer_links > stack_conf)
++		mcfg->max_peer_links = stack_conf;
++}
++
++void rtw_mesh_cfg_init_plink_timeout(_adapter *adapter, u32 stack_conf)
++{
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++
++	mcfg->plink_timeout = stack_conf;
++}
++
++void rtw_mesh_init_mesh_info(_adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++
++	_rtw_memset(minfo, 0, sizeof(struct rtw_mesh_info));
++
++	rtw_mesh_plink_ctl_init(adapter);
++	
++	minfo->last_preq = rtw_get_current_time();
++	/* minfo->last_sn_update = rtw_get_current_time(); */
++	minfo->next_perr = rtw_get_current_time();
++	
++	ATOMIC_SET(&minfo->mpaths, 0);
++	rtw_mesh_pathtbl_init(adapter);
++
++	_rtw_init_queue(&minfo->mpath_tx_queue);
++	tasklet_init(&minfo->mpath_tx_tasklet
++		, (void(*)(unsigned long))mpath_tx_tasklet_hdl
++		, (unsigned long)adapter);
++
++	rtw_mrc_init(adapter);
++
++	_rtw_init_listhead(&minfo->preq_queue.list);
++	_rtw_spinlock_init(&minfo->mesh_preq_queue_lock);
++	
++	rtw_init_timer(&adapter->mesh_path_timer, adapter, rtw_ieee80211_mesh_path_timer, adapter);
++	rtw_init_timer(&adapter->mesh_path_root_timer, adapter, rtw_ieee80211_mesh_path_root_timer, adapter);
++	rtw_init_timer(&adapter->mesh_atlm_param_req_timer, adapter, rtw_mesh_atlm_param_req_timer, adapter);
++	_init_workitem(&adapter->mesh_work, rtw_mesh_work_hdl, NULL);
++}
++
++void rtw_mesh_deinit_mesh_info(_adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++
++	tasklet_kill(&minfo->mpath_tx_tasklet);
++	rtw_mpath_tx_queue_flush(adapter);
++	_rtw_deinit_queue(&adapter->mesh_info.mpath_tx_queue);
++
++	rtw_mrc_free(adapter);
++
++	rtw_mesh_pathtbl_unregister(adapter);
++
++	rtw_mesh_plink_ctl_deinit(adapter);
++
++	_cancel_workitem_sync(&adapter->mesh_work);
++	_cancel_timer_ex(&adapter->mesh_path_timer);
++	_cancel_timer_ex(&adapter->mesh_path_root_timer);
++	_cancel_timer_ex(&adapter->mesh_atlm_param_req_timer);
++}
++
++/**
++ * rtw_mesh_nexthop_resolve - lookup next hop; conditionally start path discovery
++ *
++ * @skb: 802.11 frame to be sent
++ * @sdata: network subif the frame will be sent through
++ *
++ * Lookup next hop for given skb and start path discovery if no
++ * forwarding information is found.
++ *
++ * Returns: 0 if the next hop was found and -ENOENT if the frame was queued.
++ * skb is freeed here if no mpath could be allocated.
++ */
++int rtw_mesh_nexthop_resolve(_adapter *adapter,
++			struct xmit_frame *xframe)
++{
++	struct pkt_attrib *attrib = &xframe->attrib;
++	struct rtw_mesh_path *mpath;
++	struct xmit_frame *xframe_to_free = NULL;
++	u8 *target_addr = attrib->mda;
++	int err = 0;
++	int ret = _SUCCESS;
++
++	rtw_rcu_read_lock();
++	err = rtw_mesh_nexthop_lookup(adapter, target_addr, attrib->msa, attrib->ra);
++	if (!err)
++		goto endlookup;
++
++	/* no nexthop found, start resolving */
++	mpath = rtw_mesh_path_lookup(adapter, target_addr);
++	if (!mpath) {
++		mpath = rtw_mesh_path_add(adapter, target_addr);
++		if (IS_ERR(mpath)) {
++			xframe->pkt = NULL; /* free pkt outside */
++			rtw_mesh_path_discard_frame(adapter, xframe);
++			err = PTR_ERR(mpath);
++			ret = _FAIL;
++			goto endlookup;
++		}
++	}
++
++	if (!(mpath->flags & RTW_MESH_PATH_RESOLVING))
++		rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START);
++
++	enter_critical_bh(&mpath->frame_queue.lock);
++
++	if (mpath->frame_queue_len >= RTW_MESH_FRAME_QUEUE_LEN) {
++		xframe_to_free = LIST_CONTAINOR(get_next(get_list_head(&mpath->frame_queue)), struct xmit_frame, list);
++		rtw_list_delete(&(xframe_to_free->list));
++		mpath->frame_queue_len--;
++	}
++
++	rtw_list_insert_tail(&xframe->list, get_list_head(&mpath->frame_queue));
++	mpath->frame_queue_len++;
++
++	exit_critical_bh(&mpath->frame_queue.lock);
++
++	ret = RTW_RA_RESOLVING;
++	if (xframe_to_free)
++		rtw_mesh_path_discard_frame(adapter, xframe_to_free);
++
++endlookup:
++	rtw_rcu_read_unlock();
++	return ret;
++}
++
++/**
++ * rtw_mesh_nexthop_lookup - put the appropriate next hop on a mesh frame. Calling
++ * this function is considered "using" the associated mpath, so preempt a path
++ * refresh if this mpath expires soon.
++ *
++ * @skb: 802.11 frame to be sent
++ * @sdata: network subif the frame will be sent through
++ *
++ * Returns: 0 if the next hop was found. Nonzero otherwise.
++ */
++int rtw_mesh_nexthop_lookup(_adapter *adapter,
++	const u8 *mda, const u8 *msa, u8 *ra)
++{
++	struct rtw_mesh_path *mpath;
++	struct sta_info *next_hop;
++	const u8 *target_addr = mda;
++	int err = -ENOENT;
++	struct registry_priv  *registry_par = &adapter->registrypriv;
++	u8 peer_alive_based_preq = registry_par->peer_alive_based_preq;
++	BOOLEAN nexthop_alive = _TRUE;
++
++	rtw_rcu_read_lock();
++	mpath = rtw_mesh_path_lookup(adapter, target_addr);
++
++	if (!mpath || !(mpath->flags & RTW_MESH_PATH_ACTIVE))
++		goto endlookup;
++
++	next_hop = rtw_rcu_dereference(mpath->next_hop);
++	if (next_hop) {
++		_rtw_memcpy(ra, next_hop->cmn.mac_addr, ETH_ALEN);
++		err = 0;
++	}
++
++	if (peer_alive_based_preq && next_hop)
++		nexthop_alive = next_hop->alive;
++
++	if (_rtw_memcmp(adapter_mac_addr(adapter), msa, ETH_ALEN) == _TRUE &&
++	    !(mpath->flags & RTW_MESH_PATH_RESOLVING) &&
++	    !(mpath->flags & RTW_MESH_PATH_FIXED)) {
++		u8 flags = RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH;
++
++		if (peer_alive_based_preq && nexthop_alive == _FALSE) {
++			flags |= RTW_PREQ_Q_F_BCAST_PREQ;
++			rtw_mesh_queue_preq(mpath, flags);
++		} else if (rtw_time_after(rtw_get_current_time(),
++			mpath->exp_time -
++			rtw_ms_to_systime(adapter->mesh_cfg.path_refresh_time))) {
++			rtw_mesh_queue_preq(mpath, flags);
++		}
++	/* Avoid keeping trying unicast PREQ toward root,
++	   when next_hop leaves */
++	} else if (peer_alive_based_preq &&
++		   _rtw_memcmp(adapter_mac_addr(adapter), msa, ETH_ALEN) == _TRUE &&
++		   (mpath->flags & RTW_MESH_PATH_RESOLVING) &&
++		   !(mpath->flags & RTW_MESH_PATH_FIXED) &&
++		   !(mpath->flags & RTW_MESH_PATH_BCAST_PREQ) &&
++		   mpath->is_root && nexthop_alive == _FALSE) {
++		enter_critical_bh(&mpath->state_lock);
++		mpath->flags |= RTW_MESH_PATH_BCAST_PREQ;
++		exit_critical_bh(&mpath->state_lock);
++	}
++
++endlookup:
++	rtw_rcu_read_unlock();
++	return err;
++}
++
++#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++static bool rtw_mesh_data_bmc_to_uc(_adapter *adapter
++	, const u8 *da, const u8 *sa, const u8 *mda, const u8 *msa
++	, u8 ae_need, const u8 *ori_ta, u8 mfwd_ttl
++	, u16 os_qid, _list *b2u_list, u8 *b2u_num, u32 *b2u_mseq)
++{
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct xmit_priv *xmitpriv = &adapter->xmitpriv;
++	_irqL irqL;
++	_list *head, *list;
++	struct sta_info *sta;
++	char b2u_sta_id[NUM_STA];
++	u8 b2u_sta_num = 0;
++	bool bmc_need = _FALSE;
++	int i;
++
++	_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
++	head = &stapriv->asoc_list;
++	list = get_next(head);
++
++	while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
++		int stainfo_offset;
++
++		sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
++		list = get_next(list);
++	
++		stainfo_offset = rtw_stainfo_offset(stapriv, sta);
++		if (stainfo_offset_valid(stainfo_offset))
++			b2u_sta_id[b2u_sta_num++] = stainfo_offset;
++	}
++	_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
++
++	if (!b2u_sta_num)
++		goto exit;
++
++	for (i = 0; i < b2u_sta_num; i++) {
++		struct xmit_frame *b2uframe;
++		struct pkt_attrib *attrib;
++
++		sta = rtw_get_stainfo_by_offset(stapriv, b2u_sta_id[i]);
++		if (!(sta->state & WIFI_ASOC_STATE)
++			|| _rtw_memcmp(sta->cmn.mac_addr, msa, ETH_ALEN) == _TRUE
++			|| (ori_ta && _rtw_memcmp(sta->cmn.mac_addr, ori_ta, ETH_ALEN) == _TRUE)
++			|| is_broadcast_mac_addr(sta->cmn.mac_addr)
++			|| is_zero_mac_addr(sta->cmn.mac_addr))
++			continue;
++
++		b2uframe = rtw_alloc_xmitframe(xmitpriv, os_qid);
++		if (!b2uframe) {
++			bmc_need = _TRUE;
++			break;
++		}
++
++		if ((*b2u_num)++ == 0 && !ori_ta) {
++			*b2u_mseq = (cpu_to_le32(adapter->mesh_info.mesh_seqnum));
++			adapter->mesh_info.mesh_seqnum++;
++		}
++
++		attrib = &b2uframe->attrib;
++
++		attrib->mb2u = 1;
++		attrib->mseq = *b2u_mseq;
++		attrib->mfwd_ttl = ori_ta ? mfwd_ttl : 0;
++		_rtw_memcpy(attrib->ra, sta->cmn.mac_addr, ETH_ALEN);
++		_rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
++		_rtw_memcpy(attrib->mda, mda, ETH_ALEN);
++		_rtw_memcpy(attrib->msa, msa, ETH_ALEN);
++		_rtw_memcpy(attrib->dst, da, ETH_ALEN);
++		_rtw_memcpy(attrib->src, sa, ETH_ALEN);
++		attrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA;
++
++		rtw_list_insert_tail(&b2uframe->list, b2u_list);
++	}
++
++exit:
++	return bmc_need;
++}
++
++void dump_mesh_b2u_flags(void *sel, _adapter *adapter)
++{
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++
++	RTW_PRINT_SEL(sel, "%4s %4s\n", "msrc", "mfwd");
++	RTW_PRINT_SEL(sel, "0x%02x 0x%02x\n", mcfg->b2u_flags_msrc, mcfg->b2u_flags_mfwd);
++}
++#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */
++
++int rtw_mesh_addr_resolve(_adapter *adapter, u16 os_qid, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list)
++{
++	struct pkt_file pktfile;
++	struct ethhdr etherhdr;
++	struct pkt_attrib *attrib;
++	struct rtw_mesh_path *mpath = NULL, *mppath = NULL;
++	u8 is_da_mcast;
++	u8 ae_need;
++#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++	bool bmc_need = _TRUE;
++	u8 b2u_num = 0;
++	u32 b2u_mseq = 0;
++#endif
++	int res = _SUCCESS;
++
++	_rtw_open_pktfile(pkt, &pktfile);
++	if (_rtw_pktfile_read(&pktfile, (u8 *)&etherhdr, ETH_HLEN) != ETH_HLEN) {
++		res = _FAIL;
++		goto exit;
++	}
++	
++	xframe->pkt = pkt;
++#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++	_rtw_init_listhead(b2u_list);
++#endif
++
++	is_da_mcast = IS_MCAST(etherhdr.h_dest);
++	if (!is_da_mcast) {
++		struct sta_info *next_hop; 
++		bool mpp_lookup = 1;
++	
++		mpath = rtw_mesh_path_lookup(adapter, etherhdr.h_dest);
++		if (mpath) {
++			mpp_lookup = 0;
++			next_hop = rtw_rcu_dereference(mpath->next_hop);
++			if (!next_hop
++				|| !(mpath->flags & (RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVING))
++			) {
++				/* mpath is not valid, search mppath */
++				mpp_lookup = 1;
++			}
++		}
++
++		if (mpp_lookup) {
++			mppath = rtw_mpp_path_lookup(adapter, etherhdr.h_dest);
++			if (mppath)
++				mppath->exp_time = rtw_get_current_time();
++		}
++
++		if (mppath && mpath)
++			rtw_mesh_path_del(adapter, mpath->dst);
++
++		ae_need = _rtw_memcmp(adapter_mac_addr(adapter), etherhdr.h_source, ETH_ALEN) == _FALSE
++			|| (mppath && _rtw_memcmp(mppath->mpp, etherhdr.h_dest, ETH_ALEN) == _FALSE);
++	} else {
++		ae_need = _rtw_memcmp(adapter_mac_addr(adapter), etherhdr.h_source, ETH_ALEN) == _FALSE;
++
++		#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++		if (rtw_msrc_b2u_policy_chk(adapter->mesh_cfg.b2u_flags_msrc, etherhdr.h_dest)) {
++			bmc_need = rtw_mesh_data_bmc_to_uc(adapter
++				, etherhdr.h_dest, etherhdr.h_source
++				, etherhdr.h_dest, adapter_mac_addr(adapter), ae_need, NULL, 0
++				, os_qid, b2u_list, &b2u_num, &b2u_mseq);
++			if (bmc_need == _FALSE) {
++				res = RTW_BMC_NO_NEED;
++				goto exit;
++			}
++		}
++		#endif
++	}
++
++	attrib = &xframe->attrib;
++
++#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++	if (b2u_num) {
++		attrib->mb2u = 1;
++		attrib->mseq = b2u_mseq;
++	} else
++		attrib->mb2u = 0;
++#endif
++
++	attrib->mfwd_ttl = 0;
++	_rtw_memcpy(attrib->dst, etherhdr.h_dest, ETH_ALEN);
++	_rtw_memcpy(attrib->src, etherhdr.h_source, ETH_ALEN);
++	_rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
++
++	if (is_da_mcast) {
++		attrib->mesh_frame_mode = ae_need ? MESH_BMCAST_PX_DATA : MESH_BMCAST_DATA;
++		_rtw_memcpy(attrib->ra, attrib->dst, ETH_ALEN);
++		_rtw_memcpy(attrib->msa, adapter_mac_addr(adapter), ETH_ALEN);
++	} else {
++		attrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA;
++		_rtw_memcpy(attrib->mda, (mppath && ae_need) ? mppath->mpp : attrib->dst, ETH_ALEN);
++		_rtw_memcpy(attrib->msa, adapter_mac_addr(adapter), ETH_ALEN);
++		/* RA needs to be resolved */
++		res = rtw_mesh_nexthop_resolve(adapter, xframe);
++	}
++
++exit:
++	return res;
++}
++
++s8 rtw_mesh_tx_set_whdr_mctrl_len(u8 mesh_frame_mode, struct pkt_attrib *attrib)
++{
++	u8 ret = 0;
++	switch (mesh_frame_mode) {
++	case MESH_UCAST_DATA:
++		attrib->hdrlen = WLAN_HDR_A4_QOS_LEN;
++		/* mesh flag + mesh TTL + Mesh SN. no ext addr. */
++		attrib->meshctrl_len = 6;
++		break;
++	case MESH_BMCAST_DATA:
++		attrib->hdrlen = WLAN_HDR_A3_QOS_LEN;
++		/* mesh flag + mesh TTL + Mesh SN. no ext addr. */
++		attrib->meshctrl_len = 6;
++		break;
++	case MESH_UCAST_PX_DATA:
++		attrib->hdrlen = WLAN_HDR_A4_QOS_LEN;
++		/* mesh flag + mesh TTL + Mesh SN + extaddr1 + extaddr2. */
++		attrib->meshctrl_len = 18;
++		break;
++	case MESH_BMCAST_PX_DATA:
++		attrib->hdrlen = WLAN_HDR_A3_QOS_LEN;
++		/* mesh flag + mesh TTL + Mesh SN + extaddr1 */
++		attrib->meshctrl_len = 12;
++		break;
++	default:
++		RTW_WARN("Invalid mesh frame mode:%u\n", mesh_frame_mode);
++		ret = -1;
++		break;
++	}				
++
++	return ret;
++}
++
++void rtw_mesh_tx_build_mctrl(_adapter *adapter, struct pkt_attrib *attrib, u8 *buf)
++{
++	struct rtw_ieee80211s_hdr *mctrl = (struct rtw_ieee80211s_hdr *)buf;
++
++	_rtw_memset(mctrl, 0, XATTRIB_GET_MCTRL_LEN(attrib));
++
++	if (attrib->mfwd_ttl
++		#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++		|| attrib->mb2u
++		#endif
++	) {
++		#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++		if (!attrib->mfwd_ttl)
++			mctrl->ttl = adapter->mesh_cfg.dot11MeshTTL;
++		else
++		#endif
++			mctrl->ttl = attrib->mfwd_ttl;
++
++		mctrl->seqnum = (cpu_to_le32(attrib->mseq));
++	} else {
++		mctrl->ttl = adapter->mesh_cfg.dot11MeshTTL;
++		mctrl->seqnum = (cpu_to_le32(adapter->mesh_info.mesh_seqnum));
++		adapter->mesh_info.mesh_seqnum++;
++	}
++
++	switch (attrib->mesh_frame_mode){
++	case MESH_UCAST_DATA:
++	case MESH_BMCAST_DATA:
++		break;
++	case MESH_UCAST_PX_DATA:
++		mctrl->flags |= MESH_FLAGS_AE_A5_A6;
++		_rtw_memcpy(mctrl->eaddr1, attrib->dst, ETH_ALEN);
++		_rtw_memcpy(mctrl->eaddr2, attrib->src, ETH_ALEN);
++		break;
++	case MESH_BMCAST_PX_DATA:
++		mctrl->flags |= MESH_FLAGS_AE_A4;
++		_rtw_memcpy(mctrl->eaddr1, attrib->src, ETH_ALEN);
++		break;
++	case MESH_MHOP_UCAST_ACT:
++		/* TBD */
++		break;
++	case MESH_MHOP_BMCAST_ACT:
++		/* TBD */
++		break;
++	default:
++		break;
++	}
++}
++
++u8 rtw_mesh_tx_build_whdr(_adapter *adapter, struct pkt_attrib *attrib
++	, u16 *fctrl, struct rtw_ieee80211_hdr *whdr)
++{
++	switch (attrib->mesh_frame_mode) {
++	case MESH_UCAST_DATA:		/* 1, 1, RA, TA, mDA(=DA),	mSA(=SA) */
++	case MESH_UCAST_PX_DATA:	/* 1, 1, RA, TA, mDA,		mSA,		[DA, SA] */
++		SetToDs(fctrl);
++		SetFrDs(fctrl);
++		_rtw_memcpy(whdr->addr1, attrib->ra, ETH_ALEN);
++		_rtw_memcpy(whdr->addr2, attrib->ta, ETH_ALEN);
++		_rtw_memcpy(whdr->addr3, attrib->mda, ETH_ALEN);
++		_rtw_memcpy(whdr->addr4, attrib->msa, ETH_ALEN);
++		break;
++	case MESH_BMCAST_DATA:		/* 0, 1, RA(DA), TA, mSA(SA) */
++	case MESH_BMCAST_PX_DATA:	/* 0, 1, RA(DA), TA, mSA,		[SA] */
++		SetFrDs(fctrl);
++		_rtw_memcpy(whdr->addr1, attrib->ra, ETH_ALEN);
++		_rtw_memcpy(whdr->addr2, attrib->ta, ETH_ALEN);
++		_rtw_memcpy(whdr->addr3, attrib->msa, ETH_ALEN);
++		break;
++	case MESH_MHOP_UCAST_ACT:
++		/* TBD */
++		RTW_INFO("MESH_MHOP_UCAST_ACT\n");
++		break;
++	case MESH_MHOP_BMCAST_ACT:
++		/* TBD */
++		RTW_INFO("MESH_MHOP_BMCAST_ACT\n");
++		break;
++	default:
++		RTW_WARN("Invalid mesh frame mode\n");
++		break;
++	}
++	
++	return 0;
++}
++
++int rtw_mesh_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta)
++{
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
++	u8 *whdr = get_recvframe_data(rframe);
++	u8 is_ra_bmc = 0;
++	u8 a4_shift = 0;
++	u8 ps;
++	u8 *qc;
++	u8 mps_mode = RTW_MESH_PS_UNKNOWN;
++	sint ret = _FAIL;
++
++	if (!(MLME_STATE(adapter) & WIFI_ASOC_STATE))
++		goto exit;
++
++	if (!rattrib->qos)
++		goto exit;
++
++	switch (rattrib->to_fr_ds) {
++	case 1:
++		if (!IS_MCAST(GetAddr1Ptr(whdr)))
++			goto exit;
++		*sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr));
++		if (*sta == NULL) {
++			ret = _SUCCESS; /* return _SUCCESS to drop at sta checking */
++			goto exit;
++		}
++		_rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);
++		_rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);
++		_rtw_memcpy(rattrib->mda, GetAddr1Ptr(whdr), ETH_ALEN);
++		_rtw_memcpy(rattrib->msa, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
++		_rtw_memcpy(rattrib->dst, GetAddr1Ptr(whdr), ETH_ALEN);
++		_rtw_memcpy(rattrib->src, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */
++		_rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN);
++		is_ra_bmc = 1;
++		break;
++	case 3:
++		if (IS_MCAST(GetAddr1Ptr(whdr)))
++			goto exit;
++		*sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr));
++		if (*sta == NULL) {
++			ret = _SUCCESS; /* return _SUCCESS to drop at sta checking */
++			goto exit;
++		}
++		_rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);
++		_rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);
++		_rtw_memcpy(rattrib->mda, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
++		_rtw_memcpy(rattrib->msa, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
++		_rtw_memcpy(rattrib->dst, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */
++		_rtw_memcpy(rattrib->src, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */
++		_rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN);
++		a4_shift = ETH_ALEN;
++		break;
++	default:
++		goto exit;
++	}
++
++	qc = whdr + WLAN_HDR_A3_LEN + a4_shift;
++	ps = GetPwrMgt(whdr);
++	mps_mode = ps ? (is_ra_bmc || (get_mps_lv(qc)) ? RTW_MESH_PS_DSLEEP : RTW_MESH_PS_LSLEEP) : RTW_MESH_PS_ACTIVE;
++
++	if (ps) {
++		if (!((*sta)->state & WIFI_SLEEP_STATE))
++			stop_sta_xmit(adapter, *sta);
++	} else {
++		if ((*sta)->state & WIFI_SLEEP_STATE)
++			wakeup_sta_to_xmit(adapter, *sta);
++	}
++
++	if (is_ra_bmc)
++		(*sta)->nonpeer_mps = mps_mode;
++	else {
++		(*sta)->peer_mps = mps_mode;
++		if (mps_mode != RTW_MESH_PS_ACTIVE && (*sta)->nonpeer_mps == RTW_MESH_PS_ACTIVE)
++			(*sta)->nonpeer_mps = RTW_MESH_PS_DSLEEP;
++	}
++
++	if (get_frame_sub_type(whdr) & BIT(6)) {
++		/* No data, will not indicate to upper layer, temporily count it here */
++		count_rx_stats(adapter, rframe, *sta);
++		ret = RTW_RX_HANDLED;
++		goto exit;
++	}
++
++	rattrib->mesh_ctrl_present = get_mctrl_present(qc) ? 1 : 0;
++	if (!rattrib->mesh_ctrl_present)
++		goto exit;
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++
++int rtw_mesh_rx_data_validate_mctrl(_adapter *adapter, union recv_frame *rframe
++	, const struct rtw_ieee80211s_hdr *mctrl, const u8 *mda, const u8 *msa
++	, u8 *mctrl_len
++	, const u8 **da, const u8 **sa)
++{
++	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
++	u8 mlen;
++	u8 ae;
++	int ret = _SUCCESS;
++
++	ae = mctrl->flags & MESH_FLAGS_AE;
++	mlen = ae_to_mesh_ctrl_len[ae];
++	switch (rattrib->to_fr_ds) {
++	case 1:
++		*da = mda;
++		if (ae == MESH_FLAGS_AE_A4)
++			*sa = mctrl->eaddr1;
++		else if (ae == 0)
++			*sa = msa;
++		else
++			ret = _FAIL;
++		break;
++	case 3:
++		if (ae == MESH_FLAGS_AE_A5_A6) {
++			*da = mctrl->eaddr1;
++			*sa = mctrl->eaddr2;
++		} else if (ae == 0) {
++			*da = mda;
++			*sa = msa;
++		} else
++			ret = _FAIL;
++		break;
++	default:
++		ret = _FAIL;
++	}
++
++	if (ret == _FAIL) {
++		#ifdef DBG_RX_DROP_FRAME
++		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" invalid tfDS:%u AE:%u combination ra="MAC_FMT" ta="MAC_FMT"\n"
++			, FUNC_ADPT_ARG(adapter), rattrib->to_fr_ds, ae, MAC_ARG(rattrib->ra), MAC_ARG(rattrib->ta));
++		#endif
++		*mctrl_len = 0;
++	} else
++		*mctrl_len = mlen;
++
++	return ret;	
++}
++
++inline int rtw_mesh_rx_validate_mctrl_non_amsdu(_adapter *adapter, union recv_frame *rframe)
++{
++	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
++	const u8 *da, *sa;
++	int ret;
++
++	ret = rtw_mesh_rx_data_validate_mctrl(adapter, rframe
++			, (struct rtw_ieee80211s_hdr *)(get_recvframe_data(rframe) + rattrib->hdrlen + rattrib->iv_len)
++			, rattrib->mda, rattrib->msa
++			, &rattrib->mesh_ctrl_len
++			, &da, &sa);
++
++	if (ret == _SUCCESS) {
++		_rtw_memcpy(rattrib->dst, da, ETH_ALEN);
++		_rtw_memcpy(rattrib->src, sa, ETH_ALEN);
++	}
++
++	return ret;
++}
++
++/**
++ * rtw_mesh_rx_nexthop_resolve - lookup next hop; conditionally start path discovery
++ *
++ * @skb: 802.11 frame to be sent
++ * @sdata: network subif the frame will be sent through
++ *
++ * Lookup next hop for given skb and start path discovery if no
++ * forwarding information is found.
++ *
++ * Returns: 0 if the next hop was found and -ENOENT if the frame was queued.
++ * skb is freeed here if no mpath could be allocated.
++ */
++static int rtw_mesh_rx_nexthop_resolve(_adapter *adapter,
++	const u8 *mda, const u8 *msa, u8 *ra)
++{
++	struct rtw_mesh_path *mpath;
++	struct xmit_frame *xframe_to_free = NULL;
++	int err = 0;
++	int ret = _SUCCESS;
++
++	rtw_rcu_read_lock();
++	err = rtw_mesh_nexthop_lookup(adapter, mda, msa, ra);
++	if (!err)
++		goto endlookup;
++
++	/* no nexthop found, start resolving */
++	mpath = rtw_mesh_path_lookup(adapter, mda);
++	if (!mpath) {
++		mpath = rtw_mesh_path_add(adapter, mda);
++		if (IS_ERR(mpath)) {
++			err = PTR_ERR(mpath);
++			ret = _FAIL;
++			goto endlookup;
++		}
++	}
++
++	if (!(mpath->flags & RTW_MESH_PATH_RESOLVING))
++		rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START);
++
++	ret = _FAIL;
++
++endlookup:
++	rtw_rcu_read_unlock();
++	return ret;
++}
++
++#define RTW_MESH_DECACHE_BMC 1
++#define RTW_MESH_DECACHE_UC 0
++
++#define RTW_MESH_FORWARD_MDA_SELF_COND 0
++#define DBG_RTW_MESH_FORWARD_MDA_SELF_COND 0
++int rtw_mesh_rx_msdu_act_check(union recv_frame *rframe
++	, const u8 *mda, const u8 *msa
++	, const u8 *da, const u8 *sa
++	, struct rtw_ieee80211s_hdr *mctrl
++	, u8 *msdu, enum rtw_rx_llc_hdl llc_hdl
++	, struct xmit_frame **fwd_frame, _list *b2u_list)
++{
++	_adapter *adapter = rframe->u.hdr.adapter;
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
++	struct rtw_mesh_path *mppath;
++	u8 is_mda_bmc = IS_MCAST(mda); 
++	u8 is_mda_self = !is_mda_bmc && _rtw_memcmp(mda, adapter_mac_addr(adapter), ETH_ALEN);
++	u16 os_qid;
++	struct xmit_frame *xframe;
++	struct pkt_attrib *xattrib;
++	u8 fwd_ra[ETH_ALEN] = {0};
++	u8 fwd_mpp[ETH_ALEN] = {0}; /* forward to other gate */
++	u32 fwd_mseq;
++	int act = 0;
++	u8 ae_need;
++#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++	bool bmc_need = _TRUE;
++	u8 b2u_num = 0;
++#endif
++
++	/* fwd info lifetime update */
++	#if 0
++	if (!is_mda_self)
++		mDA(A3) fwinfo.lifetime
++	mSA(A4) fwinfo.lifetime
++	Precursor-to-mDA(A2) fwinfo.lifetime
++	#endif
++
++	/* update/create pxoxy info for SA, mSA */
++	if ((mctrl->flags & MESH_FLAGS_AE)
++		&& sa != msa && _rtw_memcmp(sa, msa, ETH_ALEN) == _FALSE
++	) {
++		const u8 *proxied_addr = sa;
++		const u8 *mpp_addr = msa;
++
++		rtw_rcu_read_lock();
++		mppath = rtw_mpp_path_lookup(adapter, proxied_addr);
++		if (!mppath)
++			rtw_mpp_path_add(adapter, proxied_addr, mpp_addr);
++		else {
++			enter_critical_bh(&mppath->state_lock);
++			if (_rtw_memcmp(mppath->mpp, mpp_addr, ETH_ALEN) == _FALSE)
++				_rtw_memcpy(mppath->mpp, mpp_addr, ETH_ALEN);
++			mppath->exp_time = rtw_get_current_time();
++			exit_critical_bh(&mppath->state_lock);
++		}
++		rtw_rcu_read_unlock();
++	}
++
++	/* mSA is self, need no further process */
++	if (_rtw_memcmp(msa, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)
++		goto exit;
++
++	fwd_mseq = le32_to_cpu(mctrl->seqnum);
++
++	/* check duplicate MSDU from mSA */
++	if (((RTW_MESH_DECACHE_BMC && is_mda_bmc)
++			|| (RTW_MESH_DECACHE_UC && !is_mda_bmc))
++		&& rtw_mesh_decache(adapter, msa, fwd_mseq)
++	) {
++		minfo->mshstats.dropped_frames_duplicate++;
++		goto exit;
++	}
++
++	if (is_mda_bmc) {
++		/* mDA is bmc addr */
++		act |= RTW_RX_MSDU_ACT_INDICATE;
++		if (!mcfg->dot11MeshForwarding)
++			goto exit;
++		goto fwd_chk;
++
++	} else if (!is_mda_self) {
++		/* mDA is unicast but not self */
++		if (!mcfg->dot11MeshForwarding) {
++			rtw_mesh_path_error_tx(adapter
++				, adapter->mesh_cfg.element_ttl
++				, mda, 0
++				, WLAN_REASON_MESH_PATH_NOFORWARD
++				, rattrib->ta
++			);
++			#ifdef DBG_RX_DROP_FRAME
++			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" mDA("MAC_FMT") not self, !dot11MeshForwarding\n"
++				, FUNC_ADPT_ARG(adapter), MAC_ARG(mda));
++			#endif
++			goto exit;
++		}
++
++		if (rtw_mesh_rx_nexthop_resolve(adapter, mda, msa, fwd_ra) != _SUCCESS) {
++			/* mDA is unknown */
++			rtw_mesh_path_error_tx(adapter
++				, adapter->mesh_cfg.element_ttl
++				, mda, 0
++				, WLAN_REASON_MESH_PATH_NOFORWARD
++				, rattrib->ta
++			);
++			#ifdef DBG_RX_DROP_FRAME
++			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" mDA("MAC_FMT") unknown\n"
++				, FUNC_ADPT_ARG(adapter), MAC_ARG(mda));
++			#endif
++			minfo->mshstats.dropped_frames_no_route++;
++			goto exit;
++
++		} else {
++			/* mDA is known in fwd info */
++			#if 0
++			if	(TA is not in precursors)
++				goto exit;
++			#endif
++			goto fwd_chk;
++		}
++
++	} else {
++		/* mDA is self */
++		#if RTW_MESH_FORWARD_MDA_SELF_COND
++		if (da == mda
++			|| _rtw_memcmp(da, adapter_mac_addr(adapter), ETH_ALEN)
++		) {
++			/* DA is self, indicate */
++			act |= RTW_RX_MSDU_ACT_INDICATE;
++			goto exit;
++		}
++
++		if (rtw_get_iface_by_macddr(adapter, da)) {
++			/* DA is buddy, indicate */
++			act |= RTW_RX_MSDU_ACT_INDICATE;
++			#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND
++			RTW_INFO(FUNC_ADPT_FMT" DA("MAC_FMT") is buddy("ADPT_FMT")\n"
++				, FUNC_ADPT_ARG(adapter), MAC_ARG(da), ADPT_ARG(rtw_get_iface_by_macddr(adapter, da)));
++			#endif
++			goto exit;
++		}
++
++		/* DA is not self or buddy */
++		if (rtw_mesh_nexthop_lookup(adapter, da, msa, fwd_ra) == 0) {
++			/* DA is known in fwd info */
++			if (!mcfg->dot11MeshForwarding) {
++				/* path error to? */
++				#if defined(DBG_RX_DROP_FRAME) || DBG_RTW_MESH_FORWARD_MDA_SELF_COND
++				RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") not self, !dot11MeshForwarding\n"
++					, FUNC_ADPT_ARG(adapter), MAC_ARG(da));
++				#endif
++				goto exit;
++			}
++			mda = da;
++			#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND
++			RTW_INFO(FUNC_ADPT_FMT" fwd to DA("MAC_FMT"), fwd_RA("MAC_FMT")\n"
++				, FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(fwd_ra));
++			#endif
++			goto fwd_chk;
++		}
++
++		rtw_rcu_read_lock();
++		mppath = rtw_mpp_path_lookup(adapter, da);
++		if (mppath) {
++			if (_rtw_memcmp(mppath->mpp, adapter_mac_addr(adapter), ETH_ALEN) == _FALSE) {
++				/* DA is proxied by others */
++				if (!mcfg->dot11MeshForwarding) {
++					/* path error to? */
++					#if defined(DBG_RX_DROP_FRAME) || DBG_RTW_MESH_FORWARD_MDA_SELF_COND
++					RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") is proxied by ("MAC_FMT"), !dot11MeshForwarding\n"
++						, FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(mppath->mpp));
++					#endif
++					rtw_rcu_read_unlock();
++					goto exit;
++				}
++				_rtw_memcpy(fwd_mpp, mppath->mpp, ETH_ALEN);
++				mda = fwd_mpp;
++				msa = adapter_mac_addr(adapter);
++				rtw_rcu_read_unlock();
++
++				/* resolve RA */
++				if (rtw_mesh_nexthop_lookup(adapter, mda, msa, fwd_ra) != 0) {
++					minfo->mshstats.dropped_frames_no_route++;
++					#if defined(DBG_RX_DROP_FRAME) || DBG_RTW_MESH_FORWARD_MDA_SELF_COND
++					RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") is proxied by ("MAC_FMT"), RA resolve fail\n"
++						, FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(mppath->mpp));
++					#endif
++					goto exit;
++				}
++				#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND
++				RTW_INFO(FUNC_ADPT_FMT" DA("MAC_FMT") is proxied by ("MAC_FMT"), fwd_RA("MAC_FMT")\n"
++					, FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(mppath->mpp), MAC_ARG(fwd_ra));
++				#endif
++				goto fwd_chk; /*  forward to other gate */
++			} else {
++				#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND
++				RTW_INFO(FUNC_ADPT_FMT" DA("MAC_FMT") is proxied by self\n"
++					, FUNC_ADPT_ARG(adapter), MAC_ARG(da));
++				#endif
++			}
++		}
++		rtw_rcu_read_unlock();
++
++		if (!mppath) {
++			#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND
++			RTW_INFO(FUNC_ADPT_FMT" DA("MAC_FMT") unknown\n"
++				, FUNC_ADPT_ARG(adapter), MAC_ARG(da));
++			#endif
++			/* DA is unknown */
++			#if 0 /* TODO: flags with AE bit */
++			rtw_mesh_path_error_tx(adapter
++				, adapter->mesh_cfg.element_ttl
++				, mda, adapter->mesh_info.last_sn_update
++				, WLAN_REASON_MESH_PATH_NOPROXY
++				, msa
++			);
++			#endif
++		}
++
++		/*
++		* indicate to DS for both cases:
++		* 1.) DA is proxied by self
++		* 2.) DA is unknown
++		*/
++		#endif /* RTW_MESH_FORWARD_MDA_SELF_COND */
++		act |= RTW_RX_MSDU_ACT_INDICATE;
++		goto exit;
++	}
++
++fwd_chk:
++
++	if (adapter->stapriv.asoc_list_cnt <= 1)
++		goto exit;
++
++	if (mctrl->ttl == 1) {
++		minfo->mshstats.dropped_frames_ttl++;
++		if (!act) {
++			#ifdef DBG_RX_DROP_FRAME
++			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" ttl reaches 0, not forwarding\n"
++				, FUNC_ADPT_ARG(adapter));
++			#endif
++		}
++		goto exit;
++	}
++
++	os_qid = rtw_os_recv_select_queue(msdu, llc_hdl);
++
++#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++	_rtw_init_listhead(b2u_list);
++#endif
++
++	ae_need = _rtw_memcmp(da , mda, ETH_ALEN) == _FALSE
++		|| _rtw_memcmp(sa , msa, ETH_ALEN) == _FALSE;
++
++#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++	if (is_mda_bmc
++		&& rtw_mfwd_b2u_policy_chk(mcfg->b2u_flags_mfwd, mda, rattrib->to_fr_ds == 3)
++	) {
++		bmc_need = rtw_mesh_data_bmc_to_uc(adapter
++			, da, sa, mda, msa, ae_need, rframe->u.hdr.psta->cmn.mac_addr, mctrl->ttl - 1
++			, os_qid, b2u_list, &b2u_num, &fwd_mseq);
++	}
++
++	if (bmc_need == _TRUE)
++#endif
++	{
++		xframe = rtw_alloc_xmitframe(&adapter->xmitpriv, os_qid);
++		if (!xframe) {
++			#ifdef DBG_TX_DROP_FRAME
++			RTW_INFO("DBG_TX_DROP_FRAME "FUNC_ADPT_FMT" rtw_alloc_xmitframe fail\n"
++				, FUNC_ADPT_ARG(adapter));
++			#endif
++			goto exit;
++		}
++
++		xattrib = &xframe->attrib;
++
++#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++		if (b2u_num)
++			xattrib->mb2u = 1;
++		else
++			xattrib->mb2u = 0;
++#endif
++		xattrib->mfwd_ttl = mctrl->ttl - 1;
++		xattrib->mseq = fwd_mseq;
++		_rtw_memcpy(xattrib->dst, da, ETH_ALEN);
++		_rtw_memcpy(xattrib->src, sa, ETH_ALEN);
++		_rtw_memcpy(xattrib->mda, mda, ETH_ALEN);
++		_rtw_memcpy(xattrib->msa, msa, ETH_ALEN);
++		_rtw_memcpy(xattrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
++
++		if (is_mda_bmc) {
++			xattrib->mesh_frame_mode = ae_need ? MESH_BMCAST_PX_DATA : MESH_BMCAST_DATA;
++			_rtw_memcpy(xattrib->ra, mda, ETH_ALEN);
++		} else {
++			xattrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA;
++			_rtw_memcpy(xattrib->ra, fwd_ra, ETH_ALEN);
++		}
++
++		*fwd_frame = xframe;
++	}
++
++	act |= RTW_RX_MSDU_ACT_FORWARD;
++	if (is_mda_bmc)
++		minfo->mshstats.fwded_mcast++;
++	else
++		minfo->mshstats.fwded_unicast++;
++	minfo->mshstats.fwded_frames++;
++
++exit:
++	return act;
++}
++
++void dump_mesh_stats(void *sel, _adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct rtw_mesh_stats *stats = &minfo->mshstats;
++
++	RTW_PRINT_SEL(sel, "fwd_bmc:%u\n", stats->fwded_mcast);
++	RTW_PRINT_SEL(sel, "fwd_uc:%u\n", stats->fwded_unicast);
++
++	RTW_PRINT_SEL(sel, "drop_ttl:%u\n", stats->dropped_frames_ttl);
++	RTW_PRINT_SEL(sel, "drop_no_route:%u\n", stats->dropped_frames_no_route);
++	RTW_PRINT_SEL(sel, "drop_congestion:%u\n", stats->dropped_frames_congestion);
++	RTW_PRINT_SEL(sel, "drop_dup:%u\n", stats->dropped_frames_duplicate);
++
++	RTW_PRINT_SEL(sel, "mrc_del_qlen:%u\n", stats->mrc_del_qlen);
++}
++#endif /* CONFIG_RTW_MESH */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh.h
+new file mode 100644
+index 000000000..5410ba404
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh.h
+@@ -0,0 +1,537 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_MESH_H_
++#define __RTW_MESH_H_
++
++#ifndef CONFIG_AP_MODE
++	#error "CONFIG_RTW_MESH can't be enabled when CONFIG_AP_MODE is not defined\n"
++#endif
++
++#define RTW_MESH_TTL				31
++#define RTW_MESH_PERR_MIN_INT			100
++#define RTW_MESH_DEFAULT_ELEMENT_TTL		31
++#define RTW_MESH_RANN_INTERVAL			5000
++#define RTW_MESH_PATH_TO_ROOT_TIMEOUT		6000
++#define RTW_MESH_DIAM_TRAVERSAL_TIME		50
++#define RTW_MESH_PATH_TIMEOUT			5000
++#define RTW_MESH_PREQ_MIN_INT			10
++#define RTW_MESH_MAX_PREQ_RETRIES		4
++#define RTW_MESH_MIN_DISCOVERY_TIMEOUT 		(2 * RTW_MESH_DIAM_TRAVERSAL_TIME)
++#define RTW_MESH_ROOT_CONFIRMATION_INTERVAL	2000
++#define RTW_MESH_PATH_REFRESH_TIME		1000
++#define RTW_MESH_ROOT_INTERVAL			5000
++
++#define RTW_MESH_SANE_METRIC_DELTA		100
++#define RTW_MESH_MAX_ROOT_ADD_CHK_CNT		2
++
++#define RTW_MESH_PLINK_UNKNOWN	0
++#define RTW_MESH_PLINK_LISTEN	1
++#define RTW_MESH_PLINK_OPN_SNT	2
++#define RTW_MESH_PLINK_OPN_RCVD 3
++#define RTW_MESH_PLINK_CNF_RCVD 4
++#define RTW_MESH_PLINK_ESTAB	5
++#define RTW_MESH_PLINK_HOLDING	6
++#define RTW_MESH_PLINK_BLOCKED	7
++
++extern const char *_rtw_mesh_plink_str[];
++#define rtw_mesh_plink_str(s) ((s <= RTW_MESH_PLINK_BLOCKED) ? _rtw_mesh_plink_str[s] : _rtw_mesh_plink_str[RTW_MESH_PLINK_UNKNOWN])
++
++#define RTW_MESH_PS_UNKNOWN 0
++#define RTW_MESH_PS_ACTIVE 1
++#define RTW_MESH_PS_LSLEEP 2
++#define RTW_MESH_PS_DSLEEP 3
++
++extern const char *_rtw_mesh_ps_str[];
++#define rtw_mesh_ps_str(mps) ((mps <= RTW_MESH_PS_DSLEEP) ? _rtw_mesh_ps_str[mps] : _rtw_mesh_ps_str[RTW_MESH_PS_UNKNOWN])
++
++#define GET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(_iec)		LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 0, 0, 8)
++#define GET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(_iec)		LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 1, 0, 8)
++#define GET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(_iec)	LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 2, 0, 8)
++#define GET_MESH_CONF_ELE_SYNC_METHOD_ID(_iec)			LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 3, 0, 8)
++#define GET_MESH_CONF_ELE_AUTH_PROTO_ID(_iec)			LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 4, 0, 8)
++
++#define GET_MESH_CONF_ELE_MESH_FORMATION(_iec)			LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 0, 8)
++#define GET_MESH_CONF_ELE_CTO_MGATE(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 0, 1)
++#define GET_MESH_CONF_ELE_NUM_OF_PEERINGS(_iec)			LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 1, 6)
++#define GET_MESH_CONF_ELE_CTO_AS(_iec)					LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 7, 1)
++
++#define GET_MESH_CONF_ELE_MESH_CAP(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 0, 8)
++#define GET_MESH_CONF_ELE_ACCEPT_PEERINGS(_iec)			LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 0, 1)
++#define GET_MESH_CONF_ELE_MCCA_SUP(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 1, 1)
++#define GET_MESH_CONF_ELE_MCCA_EN(_iec)					LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 2, 1)
++#define GET_MESH_CONF_ELE_FORWARDING(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 3, 1)
++#define GET_MESH_CONF_ELE_MBCA_EN(_iec)					LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 4, 1)
++#define GET_MESH_CONF_ELE_TBTT_ADJ(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 5, 1)
++#define GET_MESH_CONF_ELE_PS_LEVEL(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 6, 1)
++
++#define SET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(_iec, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 0, 0, 8, _val)
++#define SET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(_iec, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 1, 0, 8, _val)
++#define SET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(_iec, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 2, 0, 8, _val)
++#define SET_MESH_CONF_ELE_SYNC_METHOD_ID(_iec, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 3, 0, 8, _val)
++#define SET_MESH_CONF_ELE_AUTH_PROTO_ID(_iec, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 4, 0, 8, _val)
++
++#define SET_MESH_CONF_ELE_CTO_MGATE(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 0, 1, _val)
++#define SET_MESH_CONF_ELE_NUM_OF_PEERINGS(_iec, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 1, 6, _val)
++#define SET_MESH_CONF_ELE_CTO_AS(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 7, 1, _val)
++
++#define SET_MESH_CONF_ELE_ACCEPT_PEERINGS(_iec, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 0, 1, _val)
++#define SET_MESH_CONF_ELE_MCCA_SUP(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 1, 1, _val)
++#define SET_MESH_CONF_ELE_MCCA_EN(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 2, 1, _val)
++#define SET_MESH_CONF_ELE_FORWARDING(_iec, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 3, 1, _val)
++#define SET_MESH_CONF_ELE_MBCA_EN(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 4, 1, _val)
++#define SET_MESH_CONF_ELE_TBTT_ADJ(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 5, 1, _val)
++#define SET_MESH_CONF_ELE_PS_LEVEL(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 6, 1, _val)
++
++/* Mesh flags */
++#define MESH_FLAGS_AE		0x3 /* mask */
++#define MESH_FLAGS_AE_A4 	0x1
++#define MESH_FLAGS_AE_A5_A6	0x2
++
++/* Max number of paths */
++#define RTW_MESH_MAX_PATHS 1024
++
++#define RTW_PREQ_Q_F_START	0x1
++#define RTW_PREQ_Q_F_REFRESH	0x2
++#define RTW_PREQ_Q_F_CHK	0x4
++#define RTW_PREQ_Q_F_PEER_AKA	0x8
++#define RTW_PREQ_Q_F_BCAST_PREQ	0x10 /* force path_dicover using broadcast */
++struct rtw_mesh_preq_queue {
++	_list list;
++	u8 dst[ETH_ALEN];
++	u8 flags;
++};
++
++extern const u8 ae_to_mesh_ctrl_len[];
++
++enum mesh_frame_type {
++	MESH_UCAST_DATA		= 0x0,
++	MESH_BMCAST_DATA	= 0x1,
++	MESH_UCAST_PX_DATA	= 0x2,
++	MESH_BMCAST_PX_DATA	= 0x3,
++	MESH_MHOP_UCAST_ACT	= 0x4,
++	MESH_MHOP_BMCAST_ACT	= 0x5,
++};
++
++enum mpath_sel_frame_type {
++	MPATH_PREQ = 0,
++	MPATH_PREP,
++	MPATH_PERR,
++	MPATH_RANN
++};
++
++/**
++ * enum rtw_mesh_deferred_task_flags - mesh deferred tasks
++ *
++ *
++ *
++ * @RTW_MESH_WORK_HOUSEKEEPING: run the periodic mesh housekeeping tasks
++ * @RTW_MESH_WORK_ROOT: the mesh root station needs to send a frame
++ * @RTW_MESH_WORK_DRIFT_ADJUST: time to compensate for clock drift relative to other
++ * mesh nodes
++ * @RTW_MESH_WORK_MBSS_CHANGED: rebuild beacon and notify driver of BSS changes
++ */
++enum rtw_mesh_deferred_task_flags {
++	RTW_MESH_WORK_HOUSEKEEPING,
++	RTW_MESH_WORK_ROOT,
++	RTW_MESH_WORK_DRIFT_ADJUST,
++	RTW_MESH_WORK_MBSS_CHANGED,
++};
++
++#define RTW_MESH_MAX_PEER_CANDIDATES 15 /* aid consideration */
++#define RTW_MESH_MAX_PEER_LINKS 8
++#define RTW_MESH_PEER_LINK_TIMEOUT 20
++
++#define RTW_MESH_PEER_CONF_DISABLED 0 /* special time value means no confirmation ongoing */
++#if CONFIG_RTW_MESH_PEER_BLACKLIST
++#define IS_PEER_CONF_DISABLED(plink) ((plink)->peer_conf_end_time == RTW_MESH_PEER_CONF_DISABLED)
++#define IS_PEER_CONF_TIMEOUT(plink)(!IS_PEER_CONF_DISABLED(plink) && rtw_time_after(rtw_get_current_time(), (plink)->peer_conf_end_time))
++#define SET_PEER_CONF_DISABLED(plink) (plink)->peer_conf_end_time = RTW_MESH_PEER_CONF_DISABLED
++#define SET_PEER_CONF_END_TIME(plink, timeout_ms) \
++	do { \
++		(plink)->peer_conf_end_time = rtw_get_current_time() + rtw_ms_to_systime(timeout_ms); \
++		if ((plink)->peer_conf_end_time == RTW_MESH_PEER_CONF_DISABLED) \
++			(plink)->peer_conf_end_time++; \
++	} while (0)
++#else
++#define IS_PEER_CONF_DISABLED(plink) 1
++#define IS_PEER_CONF_TIMEOUT(plink) 0
++#define SET_PEER_CONF_DISABLED(plink) do {} while (0)
++#define SET_PEER_CONF_END_TIME(plink, timeout_ms) do {} while (0)
++#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */
++
++#define RTW_MESH_CTO_MGATE_CONF_DISABLED 0 /* special time value means no confirmation ongoing */
++#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++#define IS_CTO_MGATE_CONF_DISABLED(plink) ((plink)->cto_mgate_conf_end_time == RTW_MESH_CTO_MGATE_CONF_DISABLED)
++#define IS_CTO_MGATE_CONF_TIMEOUT(plink)(!IS_CTO_MGATE_CONF_DISABLED(plink) && rtw_time_after(rtw_get_current_time(), (plink)->cto_mgate_conf_end_time))
++#define SET_CTO_MGATE_CONF_DISABLED(plink) (plink)->cto_mgate_conf_end_time = RTW_MESH_CTO_MGATE_CONF_DISABLED
++#define SET_CTO_MGATE_CONF_END_TIME(plink, timeout_ms) \
++	do { \
++		(plink)->cto_mgate_conf_end_time = rtw_get_current_time() + rtw_ms_to_systime(timeout_ms); \
++		if ((plink)->cto_mgate_conf_end_time == RTW_MESH_CTO_MGATE_CONF_DISABLED) \
++			(plink)->cto_mgate_conf_end_time++; \
++	} while (0)
++#else
++#define IS_CTO_MGATE_CONF_DISABLED(plink) 1
++#define IS_CTO_MGATE_CONF_TIMEOUT(plink) 0
++#define SET_CTO_MGATE_CONF_DISABLED(plink) do {} while (0)
++#define SET_CTO_MGATE_CONF_END_TIME(plink, timeout_ms) do {} while (0)
++#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
++
++struct mesh_plink_ent {
++	u8 valid;
++	u8 addr[ETH_ALEN];
++	u8 plink_state;
++
++#ifdef CONFIG_RTW_MESH_AEK
++	u8 aek_valid;
++	u8 aek[32];
++#endif
++
++	u16 llid;
++	u16 plid;
++#ifndef CONFIG_RTW_MESH_DRIVER_AID
++	u16 aid; /* aid assigned from upper layer */
++#endif
++	u16 peer_aid; /* aid assigned from peer */
++
++	u8 chosen_pmk[16];
++
++#ifdef CONFIG_RTW_MESH_AEK
++	u8 sel_pcs[4];
++	u8 l_nonce[32];
++	u8 p_nonce[32];
++#endif
++
++#ifdef CONFIG_RTW_MESH_DRIVER_AID
++	u8 *tx_conf_ies;
++	u16 tx_conf_ies_len;
++#endif
++	u8 *rx_conf_ies;
++	u16 rx_conf_ies_len;
++
++	struct wlan_network *scanned;
++
++#if CONFIG_RTW_MESH_PEER_BLACKLIST
++	systime peer_conf_end_time;
++#endif
++#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++	systime cto_mgate_conf_end_time;
++#endif
++};
++
++#ifdef CONFIG_RTW_MESH_AEK
++#define MESH_PLINK_AEK_VALID(ent) ent->aek_valid
++#else
++#define MESH_PLINK_AEK_VALID(ent) 0
++#endif
++
++struct mesh_plink_pool {
++	_lock lock;
++	u8 num; /* current ent being used */
++	struct mesh_plink_ent ent[RTW_MESH_MAX_PEER_CANDIDATES];
++
++#if CONFIG_RTW_MESH_ACNODE_PREVENT
++	u8 acnode_rsvd;
++#endif
++
++#if CONFIG_RTW_MESH_PEER_BLACKLIST
++	_queue peer_blacklist;
++#endif
++#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++	_queue cto_mgate_blacklist;
++#endif
++};
++
++struct mesh_peer_sel_policy {
++	u32 scanr_exp_ms;
++
++#if CONFIG_RTW_MESH_ACNODE_PREVENT
++	u8 acnode_prevent;
++	u32 acnode_conf_timeout_ms;
++	u32 acnode_notify_timeout_ms;
++#endif
++
++#if CONFIG_RTW_MESH_OFFCH_CAND
++	u8 offch_cand;
++	u32 offch_find_int_ms; /* 0 means no offch find triggerred by driver self*/
++#endif
++
++#if CONFIG_RTW_MESH_PEER_BLACKLIST
++	u32 peer_conf_timeout_ms;
++	u32 peer_blacklist_timeout_ms;
++#endif
++
++#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++	u8 cto_mgate_require;
++	u32 cto_mgate_conf_timeout_ms;
++	u32 cto_mgate_blacklist_timeout_ms;
++#endif
++};
++
++/* b2u flags */
++#define RTW_MESH_B2U_ALL		BIT0
++#define RTW_MESH_B2U_GA_UCAST	BIT1 /* Group addressed unicast frame, forward only */
++#define RTW_MESH_B2U_BCAST		BIT2
++#define RTW_MESH_B2U_IP_MCAST	BIT3
++
++#define rtw_msrc_b2u_policy_chk(flags, mda) ( \
++	(flags & RTW_MESH_B2U_ALL) \
++	|| ((flags & RTW_MESH_B2U_BCAST) && is_broadcast_mac_addr(mda)) \
++	|| ((flags & RTW_MESH_B2U_IP_MCAST) && (IP_MCAST_MAC(mda) || ICMPV6_MCAST_MAC(mda))) \
++	)
++
++#define rtw_mfwd_b2u_policy_chk(flags, mda, ucst) ( \
++	(flags & RTW_MESH_B2U_ALL) \
++	|| ((flags & RTW_MESH_B2U_GA_UCAST) && ucst) \
++	|| ((flags & RTW_MESH_B2U_BCAST) && is_broadcast_mac_addr(mda)) \
++	|| ((flags & RTW_MESH_B2U_IP_MCAST) && (IP_MCAST_MAC(mda) || ICMPV6_MCAST_MAC(mda))) \
++	)
++
++/**
++ * @sane_metric_delta: Controlling if trigger additional path check mechanism
++ * @max_root_add_chk_cnt: The retry cnt to send additional root confirmation
++ *	PREQ through old(last) path
++ */
++struct rtw_mesh_cfg {
++	u8 max_peer_links; /* peering limit */
++	u32 plink_timeout; /* seconds */
++
++	u8 dot11MeshTTL;
++	u8 element_ttl;
++	u32 path_refresh_time;
++	u16 dot11MeshHWMPpreqMinInterval;
++	u16 dot11MeshHWMPnetDiameterTraversalTime;
++	u32 dot11MeshHWMPactivePathTimeout;
++	u8 dot11MeshHWMPmaxPREQretries;
++	u16 min_discovery_timeout;
++	u16 dot11MeshHWMPconfirmationInterval;
++	u16 dot11MeshHWMPperrMinInterval;
++	u8 dot11MeshHWMPRootMode;
++	BOOLEAN dot11MeshForwarding;
++	s32 rssi_threshold; /* in dBm, 0: no specified */
++	u16 dot11MeshHWMPRannInterval;
++	BOOLEAN dot11MeshGateAnnouncementProtocol;
++	u32 dot11MeshHWMPactivePathToRootTimeout;
++	u16 dot11MeshHWMProotInterval;
++	u8 path_gate_timeout_factor;
++#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
++	u16 sane_metric_delta;
++	u8 max_root_add_chk_cnt;
++#endif
++
++	struct mesh_peer_sel_policy peer_sel_policy;
++
++#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++	u8 b2u_flags_msrc;
++	u8 b2u_flags_mfwd;
++#endif
++};
++
++struct rtw_mesh_stats {
++	u32 fwded_mcast;		/* Mesh forwarded multicast frames */
++	u32 fwded_unicast;		/* Mesh forwarded unicast frames */
++	u32 fwded_frames;		/* Mesh total forwarded frames */
++	u32 dropped_frames_ttl;	/* Not transmitted since mesh_ttl == 0*/
++	u32 dropped_frames_no_route;	/* Not transmitted, no route found */
++	u32 dropped_frames_congestion;/* Not forwarded due to congestion */
++	u32 dropped_frames_duplicate;
++
++	u32 mrc_del_qlen; /* MRC entry deleted cause by queue length limit */
++};
++
++struct rtw_mrc;
++
++struct rtw_mesh_info {
++	u8 mesh_id[NDIS_802_11_LENGTH_SSID];
++	size_t mesh_id_len;
++	/* Active Path Selection Protocol Identifier */
++	u8 mesh_pp_id;
++	/* Active Path Selection Metric Identifier */
++	u8 mesh_pm_id;
++	/* Congestion Control Mode Identifier */
++	u8 mesh_cc_id;
++	/* Synchronization Protocol Identifier */
++	u8 mesh_sp_id;
++	/* Authentication Protocol Identifier */
++	u8 mesh_auth_id;
++
++	struct mesh_plink_pool plink_ctl;
++
++	u32 mesh_seqnum;
++	/* MSTA's own hwmp sequence number */
++	u32 sn;
++	systime last_preq;
++	systime last_sn_update;
++	systime next_perr;
++	/* Last used Path Discovery ID */
++	u32 preq_id;
++	
++	ATOMIC_T mpaths;
++	struct rtw_mesh_table *mesh_paths;
++	struct rtw_mesh_table *mpp_paths;
++	int mesh_paths_generation;
++	int mpp_paths_generation;
++
++	int num_gates;
++	struct rtw_mesh_path *max_addr_gate;
++	bool max_addr_gate_is_larger_than_self;
++
++	struct rtw_mesh_stats mshstats;
++
++	_queue mpath_tx_queue;
++	u32 mpath_tx_queue_len;
++	_tasklet mpath_tx_tasklet;
++
++	struct rtw_mrc *mrc;
++
++	_lock mesh_preq_queue_lock;
++	struct rtw_mesh_preq_queue preq_queue;
++	int preq_queue_len;
++};
++
++extern const char *_action_self_protected_str[];
++#define action_self_protected_str(action) ((action < RTW_ACT_SELF_PROTECTED_NUM) ? _action_self_protected_str[action] : _action_self_protected_str[0])
++
++u8 *rtw_set_ie_mesh_id(u8 *buf, u32 *buf_len, const char *mesh_id, u8 id_len);
++u8 *rtw_set_ie_mesh_config(u8 *buf, u32 *buf_len
++	, u8 path_sel_proto, u8 path_sel_metric, u8 congest_ctl_mode, u8 sync_method, u8 auth_proto
++	, u8 num_of_peerings, bool cto_mgate, bool cto_as
++	, bool accept_peerings, bool mcca_sup, bool mcca_en, bool forwarding
++	, bool mbca_en, bool tbtt_adj, bool ps_level);
++
++int rtw_bss_is_same_mbss(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b);
++int rtw_bss_is_candidate_mesh_peer(_adapter *adapter, WLAN_BSSID_EX *target, u8 ch, u8 add_peer);
++
++void rtw_chk_candidate_peer_notify(_adapter *adapter, struct wlan_network *scanned);
++
++void rtw_mesh_peer_status_chk(_adapter *adapter);
++
++#if CONFIG_RTW_MESH_ACNODE_PREVENT
++void rtw_mesh_update_scanned_acnode_status(_adapter *adapter, struct wlan_network *scanned);
++bool rtw_mesh_scanned_is_acnode_confirmed(_adapter *adapter, struct wlan_network *scanned);
++bool rtw_mesh_acnode_prevent_allow_sacrifice(_adapter *adapter);
++struct sta_info *rtw_mesh_acnode_prevent_pick_sacrifice(_adapter *adapter);
++void dump_mesh_acnode_prevent_settings(void *sel, _adapter *adapter);
++#endif
++
++#if CONFIG_RTW_MESH_OFFCH_CAND
++u8 rtw_mesh_offch_candidate_accepted(_adapter *adapter);
++u8 rtw_mesh_select_operating_ch(_adapter *adapter);
++void dump_mesh_offch_cand_settings(void *sel, _adapter *adapter);
++#endif
++
++#if CONFIG_RTW_MESH_PEER_BLACKLIST
++int rtw_mesh_peer_blacklist_add(_adapter *adapter, const u8 *addr);
++int rtw_mesh_peer_blacklist_del(_adapter *adapter, const u8 *addr);
++int rtw_mesh_peer_blacklist_search(_adapter *adapter, const u8 *addr);
++void rtw_mesh_peer_blacklist_flush(_adapter *adapter);
++void dump_mesh_peer_blacklist(void *sel, _adapter *adapter);
++void dump_mesh_peer_blacklist_settings(void *sel, _adapter *adapter);
++#endif
++#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++u8 rtw_mesh_cto_mgate_required(_adapter *adapter);
++u8 rtw_mesh_cto_mgate_network_filter(_adapter *adapter, struct wlan_network *scanned);
++int rtw_mesh_cto_mgate_blacklist_add(_adapter *adapter, const u8 *addr);
++int rtw_mesh_cto_mgate_blacklist_del(_adapter *adapter, const u8 *addr);
++int rtw_mesh_cto_mgate_blacklist_search(_adapter *adapter, const u8 *addr);
++void rtw_mesh_cto_mgate_blacklist_flush(_adapter *adapter);
++void dump_mesh_cto_mgate_blacklist(void *sel, _adapter *adapter);
++void dump_mesh_cto_mgate_blacklist_settings(void *sel, _adapter *adapter);
++#endif
++void dump_mesh_peer_sel_policy(void *sel, _adapter *adapter);
++void dump_mesh_networks(void *sel, _adapter *adapter);
++
++void rtw_mesh_adjust_chbw(u8 req_ch, u8 *req_bw, u8 *req_offset);
++
++void rtw_mesh_sae_check_frames(_adapter *adapter, const u8 *buf, u32 len, u8 tx, u16 alg, u16 seq, u16 status);
++int rtw_mesh_check_frames_tx(_adapter *adapter, const u8 **buf, size_t *len);
++int rtw_mesh_check_frames_rx(_adapter *adapter, const u8 *buf, size_t len);
++
++int rtw_mesh_on_auth(_adapter *adapter, union recv_frame *rframe);
++unsigned int on_action_self_protected(_adapter *adapter, union recv_frame *rframe);
++
++bool rtw_mesh_update_bss_peering_status(_adapter *adapter, WLAN_BSSID_EX *bss);
++bool rtw_mesh_update_bss_formation_info(_adapter *adapter, WLAN_BSSID_EX *bss);
++bool rtw_mesh_update_bss_forwarding_state(_adapter *adapter, WLAN_BSSID_EX *bss);
++
++struct mesh_plink_ent *_rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr);
++struct mesh_plink_ent *rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr);
++struct mesh_plink_ent *rtw_mesh_plink_get_no_estab_by_idx(_adapter *adapter, u8 idx);
++int _rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr);
++int rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr);
++int rtw_mesh_plink_set_state(_adapter *adapter, const u8 *hwaddr, u8 state);
++#ifdef CONFIG_RTW_MESH_AEK
++int rtw_mesh_plink_set_aek(_adapter *adapter, const u8 *hwaddr, const u8 *aek);
++#endif
++#if CONFIG_RTW_MESH_PEER_BLACKLIST
++int rtw_mesh_plink_set_peer_conf_timeout(_adapter *adapter, const u8 *hwaddr);
++#endif
++void _rtw_mesh_plink_del_ent(_adapter *adapter, struct mesh_plink_ent *ent);
++int rtw_mesh_plink_del(_adapter *adapter, const u8 *hwaddr);
++void rtw_mesh_plink_ctl_init(_adapter *adapter);
++void rtw_mesh_plink_ctl_deinit(_adapter *adapter);
++void dump_mesh_plink_ctl(void *sel, _adapter *adapter);
++
++u8 rtw_mesh_set_plink_state_cmd(_adapter *adapter, const u8 *mac, u8 plink_state);
++
++void _rtw_mesh_expire_peer_ent(_adapter *adapter, struct mesh_plink_ent *plink);
++void rtw_mesh_expire_peer(_adapter *adapter, const u8 *peer_addr);
++u8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps);
++
++unsigned int on_action_mesh(_adapter *adapter, union recv_frame *rframe);
++
++void rtw_mesh_cfg_init(_adapter *adapter);
++void rtw_mesh_cfg_init_max_peer_links(_adapter *adapter, u8 stack_conf);
++void rtw_mesh_cfg_init_plink_timeout(_adapter *adapter, u32 stack_conf);
++void rtw_mesh_init_mesh_info(_adapter *adapter);
++void rtw_mesh_deinit_mesh_info(_adapter *adapter);
++
++#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++void dump_mesh_b2u_flags(void *sel, _adapter *adapter);
++#endif
++
++int rtw_mesh_addr_resolve(_adapter *adapter, u16 os_qid, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list);
++
++s8 rtw_mesh_tx_set_whdr_mctrl_len(u8 mesh_frame_mode, struct pkt_attrib *attrib);
++void rtw_mesh_tx_build_mctrl(_adapter *adapter, struct pkt_attrib *attrib, u8 *buf);
++u8 rtw_mesh_tx_build_whdr(_adapter *adapter, struct pkt_attrib *attrib
++	, u16 *fctrl, struct rtw_ieee80211_hdr *whdr);
++
++int rtw_mesh_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta);
++int rtw_mesh_rx_data_validate_mctrl(_adapter *adapter, union recv_frame *rframe
++	, const struct rtw_ieee80211s_hdr *mctrl, const u8 *mda, const u8 *msa
++	, u8 *mctrl_len, const u8 **da, const u8 **sa);
++int rtw_mesh_rx_validate_mctrl_non_amsdu(_adapter *adapter, union recv_frame *rframe);
++
++int rtw_mesh_rx_msdu_act_check(union recv_frame *rframe
++	, const u8 *mda, const u8 *msa
++	, const u8 *da, const u8 *sa
++	, struct rtw_ieee80211s_hdr *mctrl
++	, u8 *msdu, enum rtw_rx_llc_hdl llc_hdl
++	, struct xmit_frame **fwd_frame, _list *b2u_list);
++
++void dump_mesh_stats(void *sel, _adapter *adapter);
++
++#if defined(PLATFORM_LINUX) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32))
++#define rtw_lockdep_assert_held(l) lockdep_assert_held(l)
++#define rtw_lockdep_is_held(l) lockdep_is_held(l)
++#else
++#error "TBD\n"
++#endif
++
++#include "rtw_mesh_pathtbl.h"
++#include "rtw_mesh_hwmp.h"
++#endif /* __RTW_MESH_H_ */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh_hwmp.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh_hwmp.c
+new file mode 100644
+index 000000000..449e838af
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh_hwmp.c
+@@ -0,0 +1,1674 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_HWMP_C_
++
++#ifdef CONFIG_RTW_MESH
++#include <drv_types.h>
++#include <hal_data.h>
++
++#define RTW_TEST_FRAME_LEN	8192
++#define RTW_MAX_METRIC	0xffffffff
++#define RTW_ARITH_SHIFT	8
++#define RTW_LINK_FAIL_THRESH 95
++#define RTW_MAX_PREQ_QUEUE_LEN	64
++#define RTW_ATLM_REQ_CYCLE 1000
++
++#define rtw_ilog2(n)			\
++(					\
++	(n) < 2 ? 0 :			\
++	(n) & (1ULL << 63) ? 63 :	\
++	(n) & (1ULL << 62) ? 62 :	\
++	(n) & (1ULL << 61) ? 61 :	\
++	(n) & (1ULL << 60) ? 60 :	\
++	(n) & (1ULL << 59) ? 59 :	\
++	(n) & (1ULL << 58) ? 58 :	\
++	(n) & (1ULL << 57) ? 57 :	\
++	(n) & (1ULL << 56) ? 56 :	\
++	(n) & (1ULL << 55) ? 55 :	\
++	(n) & (1ULL << 54) ? 54 :	\
++	(n) & (1ULL << 53) ? 53 :	\
++	(n) & (1ULL << 52) ? 52 :	\
++	(n) & (1ULL << 51) ? 51 :	\
++	(n) & (1ULL << 50) ? 50 :	\
++	(n) & (1ULL << 49) ? 49 :	\
++	(n) & (1ULL << 48) ? 48 :	\
++	(n) & (1ULL << 47) ? 47 :	\
++	(n) & (1ULL << 46) ? 46 :	\
++	(n) & (1ULL << 45) ? 45 :	\
++	(n) & (1ULL << 44) ? 44 :	\
++	(n) & (1ULL << 43) ? 43 :	\
++	(n) & (1ULL << 42) ? 42 :	\
++	(n) & (1ULL << 41) ? 41 :	\
++	(n) & (1ULL << 40) ? 40 :	\
++	(n) & (1ULL << 39) ? 39 :	\
++	(n) & (1ULL << 38) ? 38 :	\
++	(n) & (1ULL << 37) ? 37 :	\
++	(n) & (1ULL << 36) ? 36 :	\
++	(n) & (1ULL << 35) ? 35 :	\
++	(n) & (1ULL << 34) ? 34 :	\
++	(n) & (1ULL << 33) ? 33 :	\
++	(n) & (1ULL << 32) ? 32 :	\
++	(n) & (1ULL << 31) ? 31 :	\
++	(n) & (1ULL << 30) ? 30 :	\
++	(n) & (1ULL << 29) ? 29 :	\
++	(n) & (1ULL << 28) ? 28 :	\
++	(n) & (1ULL << 27) ? 27 :	\
++	(n) & (1ULL << 26) ? 26 :	\
++	(n) & (1ULL << 25) ? 25 :	\
++	(n) & (1ULL << 24) ? 24 :	\
++	(n) & (1ULL << 23) ? 23 :	\
++	(n) & (1ULL << 22) ? 22 :	\
++	(n) & (1ULL << 21) ? 21 :	\
++	(n) & (1ULL << 20) ? 20 :	\
++	(n) & (1ULL << 19) ? 19 :	\
++	(n) & (1ULL << 18) ? 18 :	\
++	(n) & (1ULL << 17) ? 17 :	\
++	(n) & (1ULL << 16) ? 16 :	\
++	(n) & (1ULL << 15) ? 15 :	\
++	(n) & (1ULL << 14) ? 14 :	\
++	(n) & (1ULL << 13) ? 13 :	\
++	(n) & (1ULL << 12) ? 12 :	\
++	(n) & (1ULL << 11) ? 11 :	\
++	(n) & (1ULL << 10) ? 10 :	\
++	(n) & (1ULL <<  9) ?  9 :	\
++	(n) & (1ULL <<  8) ?  8 :	\
++	(n) & (1ULL <<  7) ?  7 :	\
++	(n) & (1ULL <<  6) ?  6 :	\
++	(n) & (1ULL <<  5) ?  5 :	\
++	(n) & (1ULL <<  4) ?  4 :	\
++	(n) & (1ULL <<  3) ?  3 :	\
++	(n) & (1ULL <<  2) ?  2 :	\
++	1				\
++)
++
++enum rtw_mpath_frame_type {
++	RTW_MPATH_PREQ = 0,
++	RTW_MPATH_PREP,
++	RTW_MPATH_PERR,
++	RTW_MPATH_RANN
++};
++
++static inline u32 rtw_u32_field_get(const u8 *preq_elem, int shift, BOOLEAN ae)
++{
++	if (ae)
++		shift += 6;
++	return LE_BITS_TO_4BYTE(preq_elem + shift, 0, 32);
++}
++
++static inline u16 rtw_u16_field_get(const u8 *preq_elem, int shift, BOOLEAN ae)
++{
++	if (ae)
++		shift += 6;
++	return LE_BITS_TO_2BYTE(preq_elem + shift, 0, 16);
++}
++
++/* HWMP IE processing macros */
++#define RTW_AE_F			(1<<6)
++#define RTW_AE_F_SET(x)			(*x & RTW_AE_F)
++#define RTW_PREQ_IE_FLAGS(x)		(*(x))
++#define RTW_PREQ_IE_HOPCOUNT(x)		(*(x + 1))
++#define RTW_PREQ_IE_TTL(x)		(*(x + 2))
++#define RTW_PREQ_IE_PREQ_ID(x)		rtw_u32_field_get(x, 3, 0)
++#define RTW_PREQ_IE_ORIG_ADDR(x)	(x + 7)
++#define RTW_PREQ_IE_ORIG_SN(x)		rtw_u32_field_get(x, 13, 0)
++#define RTW_PREQ_IE_LIFETIME(x)		rtw_u32_field_get(x, 17, RTW_AE_F_SET(x))
++#define RTW_PREQ_IE_METRIC(x) 		rtw_u32_field_get(x, 21, RTW_AE_F_SET(x))
++#define RTW_PREQ_IE_TARGET_F(x)		(*(RTW_AE_F_SET(x) ? x + 32 : x + 26))
++#define RTW_PREQ_IE_TARGET_ADDR(x) 	(RTW_AE_F_SET(x) ? x + 33 : x + 27)
++#define RTW_PREQ_IE_TARGET_SN(x) 	rtw_u32_field_get(x, 33, RTW_AE_F_SET(x))
++
++#define RTW_PREP_IE_FLAGS(x)		RTW_PREQ_IE_FLAGS(x)
++#define RTW_PREP_IE_HOPCOUNT(x)		RTW_PREQ_IE_HOPCOUNT(x)
++#define RTW_PREP_IE_TTL(x)		RTW_PREQ_IE_TTL(x)
++#define RTW_PREP_IE_ORIG_ADDR(x)	(RTW_AE_F_SET(x) ? x + 27 : x + 21)
++#define RTW_PREP_IE_ORIG_SN(x)		rtw_u32_field_get(x, 27, RTW_AE_F_SET(x))
++#define RTW_PREP_IE_LIFETIME(x)		rtw_u32_field_get(x, 13, RTW_AE_F_SET(x))
++#define RTW_PREP_IE_METRIC(x)		rtw_u32_field_get(x, 17, RTW_AE_F_SET(x))
++#define RTW_PREP_IE_TARGET_ADDR(x)	(x + 3)
++#define RTW_PREP_IE_TARGET_SN(x)	rtw_u32_field_get(x, 9, 0)
++
++#define RTW_PERR_IE_TTL(x)		(*(x))
++#define RTW_PERR_IE_TARGET_FLAGS(x)	(*(x + 2))
++#define RTW_PERR_IE_TARGET_ADDR(x)	(x + 3)
++#define RTW_PERR_IE_TARGET_SN(x)	rtw_u32_field_get(x, 9, 0)
++#define RTW_PERR_IE_TARGET_RCODE(x)	rtw_u16_field_get(x, 13, 0)
++
++#define RTW_TU_TO_SYSTIME(x)	(rtw_us_to_systime((x) * 1024))
++#define RTW_TU_TO_EXP_TIME(x)	(rtw_get_current_time() + RTW_TU_TO_SYSTIME(x))
++#define RTW_MSEC_TO_TU(x) (x*1000/1024)
++#define RTW_SN_GT(x, y) ((s32)(y - x) < 0)
++#define RTW_SN_LT(x, y) ((s32)(x - y) < 0)
++#define RTW_MAX_SANE_SN_DELTA 32
++
++static inline u32 RTW_SN_DELTA(u32 x, u32 y)
++{
++	return x >= y ? x - y : y - x;
++}
++
++#define rtw_net_traversal_jiffies(adapter) \
++	rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPnetDiameterTraversalTime)
++#define rtw_default_lifetime(adapter) \
++	RTW_MSEC_TO_TU(adapter->mesh_cfg.dot11MeshHWMPactivePathTimeout)
++#define rtw_min_preq_int_jiff(adapter) \
++	(rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPpreqMinInterval))
++#define rtw_max_preq_retries(adapter) (adapter->mesh_cfg.dot11MeshHWMPmaxPREQretries)
++#define rtw_disc_timeout_jiff(adapter) \
++	rtw_ms_to_systime(adapter->mesh_cfg.min_discovery_timeout)
++#define rtw_root_path_confirmation_jiffies(adapter) \
++	rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPconfirmationInterval)
++
++static inline BOOLEAN rtw_ether_addr_equal(const u8 *addr1, const u8 *addr2)
++{
++	return _rtw_memcmp(addr1, addr2, ETH_ALEN);
++}
++
++#ifdef PLATFORM_LINUX
++#define rtw_print_ratelimit()	printk_ratelimit()
++#define rtw_mod_timer(ptimer, expires) mod_timer(&(ptimer)->timer, expires)
++#else
++
++#endif
++
++#define RTW_MESH_EWMA_PRECISION 20
++#define RTW_MESH_EWMA_WEIGHT_RCP 8
++#define RTW_TOTAL_PKT_MIN_THRESHOLD 1
++inline void rtw_ewma_err_rate_init(struct rtw_ewma_err_rate *e)
++{
++	e->internal = 0;
++}
++inline unsigned long rtw_ewma_err_rate_read(struct rtw_ewma_err_rate *e)
++{
++	return e->internal >> (RTW_MESH_EWMA_PRECISION);
++}
++inline void rtw_ewma_err_rate_add(struct rtw_ewma_err_rate *e,
++				  unsigned long val)
++{
++	unsigned long internal = e->internal;
++	unsigned long weight_rcp = rtw_ilog2(RTW_MESH_EWMA_WEIGHT_RCP);
++	unsigned long precision = RTW_MESH_EWMA_PRECISION;
++
++	(e->internal) = internal ? (((internal << weight_rcp) - internal) +
++			(val << precision)) >> weight_rcp :
++			(val << precision);
++}
++
++static const u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++
++static int rtw_mesh_path_sel_frame_tx(enum rtw_mpath_frame_type mpath_action, u8 flags,
++				      const u8 *originator_addr, u32 originator_sn,
++				      u8 target_flags, const u8 *target,
++				      u32 target_sn, const u8 *da, u8 hopcount, u8 ttl,
++				      u32 lifetime, u32 metric, u32 preq_id, 
++				      _adapter *adapter)
++{
++	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++	struct xmit_frame *pmgntframe = NULL;
++	struct rtw_ieee80211_hdr *pwlanhdr = NULL;
++	struct pkt_attrib *pattrib = NULL;
++	u8 category = RTW_WLAN_CATEGORY_MESH;
++	u8 action = RTW_ACT_MESH_HWMP_PATH_SELECTION;
++	u16 *fctrl = NULL;
++	u8 *pos, ie_len;
++
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return -1;
++
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(adapter, pattrib);
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pos = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pos;
++
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pos, WIFI_ACTION);
++
++	pos += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pos = rtw_set_fixed_ie(pos, 1, &(category), &(pattrib->pktlen));
++	pos = rtw_set_fixed_ie(pos, 1, &(action), &(pattrib->pktlen));
++
++	switch (mpath_action) {
++	case RTW_MPATH_PREQ:
++		RTW_HWMP_DBG("sending PREQ to "MAC_FMT"\n", MAC_ARG(target));
++		ie_len = 37;
++		pattrib->pktlen += (ie_len + 2);
++		*pos++ = WLAN_EID_PREQ;
++		break;
++	case RTW_MPATH_PREP:
++		RTW_HWMP_DBG("sending PREP to "MAC_FMT"\n", MAC_ARG(originator_addr));
++		ie_len = 31;
++		pattrib->pktlen += (ie_len + 2);
++		*pos++ = WLAN_EID_PREP;
++		break;
++	case RTW_MPATH_RANN:
++		RTW_HWMP_DBG("sending RANN from "MAC_FMT"\n", MAC_ARG(originator_addr));
++		ie_len = sizeof(struct rtw_ieee80211_rann_ie);
++		pattrib->pktlen += (ie_len + 2);
++		*pos++ = WLAN_EID_RANN;
++		break;
++	default:
++		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++		rtw_free_xmitframe(pxmitpriv, pmgntframe);
++		return _FAIL;
++	}
++	*pos++ = ie_len;
++	*pos++ = flags;
++	*pos++ = hopcount;
++	*pos++ = ttl;
++	if (mpath_action == RTW_MPATH_PREP) {
++		_rtw_memcpy(pos, target, ETH_ALEN);
++		pos += ETH_ALEN;
++		*(u32 *)pos = cpu_to_le32(target_sn);
++		pos += 4;
++	} else {
++		if (mpath_action == RTW_MPATH_PREQ) {
++			*(u32 *)pos = cpu_to_le32(preq_id);
++			pos += 4;
++		}
++		_rtw_memcpy(pos, originator_addr, ETH_ALEN);
++		pos += ETH_ALEN;
++		*(u32 *)pos = cpu_to_le32(originator_sn);
++		pos += 4;
++	}
++	*(u32 *)pos = cpu_to_le32(lifetime);
++	pos += 4;
++	*(u32 *)pos = cpu_to_le32(metric);
++	pos += 4;
++	if (mpath_action == RTW_MPATH_PREQ) {
++		*pos++ = 1; /* support only 1 destination now */
++		*pos++ = target_flags;
++		_rtw_memcpy(pos, target, ETH_ALEN);
++		pos += ETH_ALEN;
++		*(u32 *)pos = cpu_to_le32(target_sn);
++		pos += 4;
++	} else if (mpath_action == RTW_MPATH_PREP) {
++		_rtw_memcpy(pos, originator_addr, ETH_ALEN);
++		pos += ETH_ALEN;
++		*(u32 *)pos = cpu_to_le32(originator_sn);
++		pos += 4;
++	}
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++	dump_mgntframe(adapter, pmgntframe);
++	return 0;
++}
++
++int rtw_mesh_path_error_tx(_adapter *adapter,
++			   u8 ttl, const u8 *target, u32 target_sn,
++			   u16 perr_reason_code, const u8 *ra)
++{
++
++	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++	struct xmit_frame *pmgntframe = NULL;
++	struct rtw_ieee80211_hdr *pwlanhdr = NULL;
++	struct pkt_attrib *pattrib = NULL;
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	u8 category = RTW_WLAN_CATEGORY_MESH;
++	u8 action = RTW_ACT_MESH_HWMP_PATH_SELECTION;
++	u8 *pos, ie_len;
++	u16 *fctrl = NULL;
++
++	if (rtw_time_before(rtw_get_current_time(), minfo->next_perr))
++		return -1;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return -1;
++
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(adapter, pattrib);
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pos = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pos;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pos, WIFI_ACTION);
++
++	pos += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pos = rtw_set_fixed_ie(pos, 1, &(category), &(pattrib->pktlen));
++	pos = rtw_set_fixed_ie(pos, 1, &(action), &(pattrib->pktlen));
++
++	ie_len = 15;
++	pattrib->pktlen += (2 + ie_len);
++	*pos++ = WLAN_EID_PERR;
++	*pos++ = ie_len;
++	/* ttl */
++	*pos++ = ttl;
++	/* The Number of Destinations N */
++	*pos++ = 1;
++	/* Flags format | B7 | B6 | B5:B0 | = | rsvd | AE | rsvd | */
++	*pos = 0;
++	pos++;
++	_rtw_memcpy(pos, target, ETH_ALEN);
++	pos += ETH_ALEN;
++	*(u32 *)pos = cpu_to_le32(target_sn);
++	pos += 4;
++	*(u16 *)pos = cpu_to_le16(perr_reason_code);
++
++	adapter->mesh_info.next_perr = RTW_TU_TO_EXP_TIME(
++				adapter->mesh_cfg.dot11MeshHWMPperrMinInterval);
++	pattrib->last_txcmdsz = pattrib->pktlen;
++	/* Send directly. Rewrite it if deferred tx is needed */
++	dump_mgntframe(adapter, pmgntframe);
++
++	RTW_HWMP_DBG("TX PERR toward "MAC_FMT", ra = "MAC_FMT"\n", MAC_ARG(target), MAC_ARG(ra));
++	
++	return 0;
++}
++
++static u32 rtw_get_vht_bitrate(u8 mcs, u8 bw, u8 nss, u8 sgi)
++{
++	static const u32 base[4][10] = {
++		{   6500000,
++		   13000000,
++		   19500000,
++		   26000000,
++		   39000000,
++		   52000000,
++		   58500000,
++		   65000000,
++		   78000000,
++		/* not in the spec, but some devices use this: */
++		   86500000,
++		},
++		{  13500000,
++		   27000000,
++		   40500000,
++		   54000000,
++		   81000000,
++		  108000000,
++		  121500000,
++		  135000000,
++		  162000000,
++		  180000000,
++		},
++		{  29300000,
++		   58500000,
++		   87800000,
++		  117000000,
++		  175500000,
++		  234000000,
++		  263300000,
++		  292500000,
++		  351000000,
++		  390000000,
++		},
++		{  58500000,
++		  117000000,
++		  175500000,
++		  234000000,
++		  351000000,
++		  468000000,
++		  526500000,
++		  585000000,
++		  702000000,
++		  780000000,
++		},
++	};
++	u32 bitrate;
++	int bw_idx;
++
++	if (mcs > 9) {
++		RTW_HWMP_INFO("Invalid mcs = %d\n", mcs);
++		return 0;
++	}
++
++	if (nss > 4 || nss < 1) {
++		RTW_HWMP_INFO("Now only support nss = 1, 2, 3, 4\n");
++	}
++
++	switch (bw) {
++	case CHANNEL_WIDTH_160:
++		bw_idx = 3;
++		break;
++	case CHANNEL_WIDTH_80:
++		bw_idx = 2;
++		break;
++	case CHANNEL_WIDTH_40:
++		bw_idx = 1;
++		break;
++	case CHANNEL_WIDTH_20:
++		bw_idx = 0;
++		break;
++	default:
++		RTW_HWMP_INFO("bw = %d currently not supported\n", bw);
++		return 0;
++	}
++
++	bitrate = base[bw_idx][mcs];
++	bitrate *= nss;
++
++	if (sgi)
++		bitrate = (bitrate / 9) * 10;
++
++	/* do NOT round down here */
++	return (bitrate + 50000) / 100000;
++}
++
++static u32 rtw_get_ht_bitrate(u8 mcs, u8 bw, u8 sgi)
++{
++	int modulation, streams, bitrate;
++
++	/* the formula below does only work for MCS values smaller than 32 */
++	if (mcs >= 32) {
++		RTW_HWMP_INFO("Invalid mcs = %d\n", mcs);
++		return 0;
++	}
++
++	if (bw > 1) {
++		RTW_HWMP_INFO("Now HT only support bw = 0(20Mhz), 1(40Mhz)\n");
++		return 0;
++	}
++
++	modulation = mcs & 7;
++	streams = (mcs >> 3) + 1;
++
++	bitrate = (bw == 1) ? 13500000 : 6500000;
++
++	if (modulation < 4)
++		bitrate *= (modulation + 1);
++	else if (modulation == 4)
++		bitrate *= (modulation + 2);
++	else
++		bitrate *= (modulation + 3);
++
++	bitrate *= streams;
++
++	if (sgi)
++		bitrate = (bitrate / 9) * 10;
++
++	/* do NOT round down here */
++	return (bitrate + 50000) / 100000;
++}
++
++/**
++ * @bw: 0(20Mhz), 1(40Mhz), 2(80Mhz), 3(160Mhz)
++ * @rate_idx: DESC_RATEXXXX & 0x7f
++ * @sgi: DESC_RATEXXXX >> 7
++ * Returns: bitrate in 100kbps
++ */
++static u32 rtw_desc_rate_to_bitrate(u8 bw, u8 rate_idx, u8 sgi)
++{
++	u32 bitrate;
++
++	if (rate_idx <= DESC_RATE54M){
++		u16 ofdm_rate[12] = {10, 20, 55, 110,
++			60, 90, 120, 180, 240, 360, 480, 540};
++		bitrate = ofdm_rate[rate_idx];
++	} else if ((DESC_RATEMCS0 <= rate_idx) &&
++		   (rate_idx <= DESC_RATEMCS31)) {
++		u8 mcs = rate_idx - DESC_RATEMCS0;
++		bitrate = rtw_get_ht_bitrate(mcs, bw, sgi);
++	} else if ((DESC_RATEVHTSS1MCS0 <= rate_idx) &&
++		   (rate_idx <= DESC_RATEVHTSS4MCS9)) {
++		u8 mcs = (rate_idx - DESC_RATEVHTSS1MCS0) % 10;
++		u8 nss = ((rate_idx - DESC_RATEVHTSS1MCS0) / 10) + 1;
++		bitrate = rtw_get_vht_bitrate(mcs, bw, nss, sgi);
++	} else {
++		/* 60Ghz ??? */
++		bitrate = 1;
++	}
++
++	return bitrate;
++}
++
++static u32 rtw_airtime_link_metric_get(_adapter *adapter, struct sta_info *sta)
++{
++	struct dm_struct *dm = adapter_to_phydm(adapter);
++	int device_constant = phydm_get_plcp(dm, sta->cmn.mac_id) << RTW_ARITH_SHIFT;
++	u32 test_frame_len = RTW_TEST_FRAME_LEN << RTW_ARITH_SHIFT;
++	u32 s_unit = 1 << RTW_ARITH_SHIFT;
++	u32 err;
++	u16 rate;
++	u32 tx_time, estimated_retx;
++	u64 result;
++	/* The fail_avg should <= 100 here */
++	u32 fail_avg = (u32)rtw_ewma_err_rate_read(&sta->metrics.err_rate);
++
++	if (fail_avg > RTW_LINK_FAIL_THRESH)
++		return RTW_MAX_METRIC;
++
++	rate = sta->metrics.data_rate;
++	/* rate unit is 100Kbps, min rate = 10 */
++	if (rate < 10) {
++		RTW_HWMP_INFO("rate = %d\n", rate);
++		return RTW_MAX_METRIC;
++	}
++
++	err = (fail_avg << RTW_ARITH_SHIFT) / 100;
++
++	/* test_frame_len*10 to adjust the unit of rate(100kbps/unit) */
++	tx_time = (device_constant + 10 * test_frame_len / rate);
++	estimated_retx = ((1 << (2 * RTW_ARITH_SHIFT)) / (s_unit - err));
++	result = (tx_time * estimated_retx) >> (2 * RTW_ARITH_SHIFT);
++	/* Convert us to 0.01 TU(10.24us). x/10.24 = x*100/1024 */
++	result = (result * 100) >> 10;
++
++	return (u32)result;
++}
++
++void rtw_ieee80211s_update_metric(_adapter *adapter, u8 mac_id,
++				  u8 per, u8 rate,
++				  u8 bw, u8 total_pkt)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++	struct sta_info *sta;
++	u8 rate_idx;
++	u8 sgi;
++
++	sta = macid_ctl->sta[mac_id];
++	if (!sta)
++		return;
++
++	/* if RA, use reported rate */
++	if (adapter->fix_rate == 0xff) {
++		rate_idx = rate & 0x7f;
++		sgi = rate >> 7;
++	} else {
++		rate_idx = adapter->fix_rate & 0x7f;
++		sgi = adapter->fix_rate >> 7;
++	}
++	sta->metrics.data_rate = rtw_desc_rate_to_bitrate(bw, rate_idx, sgi);
++
++	if (total_pkt < RTW_TOTAL_PKT_MIN_THRESHOLD)
++		return;
++
++	/* TBD: sta->metrics.overhead = phydm_get_plcp(void *dm_void, u16 macid); */
++	sta->metrics.total_pkt = total_pkt;
++
++	rtw_ewma_err_rate_add(&sta->metrics.err_rate, per);
++	if (rtw_ewma_err_rate_read(&sta->metrics.err_rate) > 
++			RTW_LINK_FAIL_THRESH)
++		rtw_mesh_plink_broken(sta);
++}
++
++static void rtw_hwmp_preq_frame_process(_adapter *adapter,
++					struct rtw_ieee80211_hdr_3addr *mgmt,
++					const u8 *preq_elem, u32 originator_metric)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
++	struct rtw_mesh_path *path = NULL;
++	const u8 *target_addr, *originator_addr;
++	const u8 *da;
++	u8 target_flags, ttl, flags, to_gate_ask = 0;
++	u32 originator_sn, target_sn, lifetime, target_metric = 0;
++	BOOLEAN reply = _FALSE;
++	BOOLEAN forward = _TRUE;
++	BOOLEAN preq_is_gate;
++
++	/* Update target SN, if present */
++	target_addr = RTW_PREQ_IE_TARGET_ADDR(preq_elem);
++	originator_addr = RTW_PREQ_IE_ORIG_ADDR(preq_elem);
++	target_sn = RTW_PREQ_IE_TARGET_SN(preq_elem);
++	originator_sn = RTW_PREQ_IE_ORIG_SN(preq_elem);
++	target_flags = RTW_PREQ_IE_TARGET_F(preq_elem);
++	/* PREQ gate announcements */
++	flags = RTW_PREQ_IE_FLAGS(preq_elem);
++	preq_is_gate = !!(flags & RTW_IEEE80211_PREQ_IS_GATE_FLAG);
++
++	RTW_HWMP_DBG("received PREQ from "MAC_FMT"\n", MAC_ARG(originator_addr));
++
++	if (rtw_ether_addr_equal(target_addr, adapter_mac_addr(adapter))) {
++		RTW_HWMP_DBG("PREQ is for us\n");
++#ifdef CONFIG_RTW_MESH_ON_DMD_GANN
++		rtw_rcu_read_lock();
++		path = rtw_mesh_path_lookup(adapter, originator_addr);
++		if (path) {
++			if (preq_is_gate)
++				rtw_mesh_path_add_gate(path);
++			else if (path->is_gate) {
++				enter_critical_bh(&path->state_lock);
++				rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
++				exit_critical_bh(&path->state_lock);
++			}
++		}
++		path = NULL;
++		rtw_rcu_read_unlock();
++#endif
++		forward = _FALSE;
++		reply = _TRUE;
++		to_gate_ask = 1;
++		target_metric = 0;
++		if (rtw_time_after(rtw_get_current_time(), minfo->last_sn_update +
++					rtw_net_traversal_jiffies(adapter)) ||
++		    rtw_time_before(rtw_get_current_time(), minfo->last_sn_update)) {
++			++minfo->sn;
++			minfo->last_sn_update = rtw_get_current_time();
++		}
++		target_sn = minfo->sn;
++	} else if (is_broadcast_mac_addr(target_addr) &&
++		   (target_flags & RTW_IEEE80211_PREQ_TO_FLAG)) {
++		rtw_rcu_read_lock();
++		path = rtw_mesh_path_lookup(adapter, originator_addr);
++		if (path) {
++			if (flags & RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG) {
++				reply = _TRUE;
++				target_addr = adapter_mac_addr(adapter);
++				target_sn = ++minfo->sn;
++				target_metric = 0;
++				minfo->last_sn_update = rtw_get_current_time();
++			}
++
++			if (preq_is_gate) {
++				lifetime = RTW_PREQ_IE_LIFETIME(preq_elem);
++				path->gate_ann_int = lifetime;
++				path->gate_asked = false;
++				rtw_mesh_path_add_gate(path);
++			} else if (path->is_gate) {
++				enter_critical_bh(&path->state_lock);
++				rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
++				exit_critical_bh(&path->state_lock);
++			}
++		}
++		rtw_rcu_read_unlock();
++	} else {
++		rtw_rcu_read_lock();
++#ifdef CONFIG_RTW_MESH_ON_DMD_GANN
++		path = rtw_mesh_path_lookup(adapter, originator_addr);
++		if (path) {
++			if (preq_is_gate)
++				rtw_mesh_path_add_gate(path);
++			else if (path->is_gate) {
++				enter_critical_bh(&path->state_lock);
++				rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
++				exit_critical_bh(&path->state_lock);
++			}
++		}
++		path = NULL;
++#endif
++		path = rtw_mesh_path_lookup(adapter, target_addr);
++		if (path) {
++			if ((!(path->flags & RTW_MESH_PATH_SN_VALID)) ||
++					RTW_SN_LT(path->sn, target_sn)) {
++				path->sn = target_sn;
++				path->flags |= RTW_MESH_PATH_SN_VALID;
++			} else if ((!(target_flags & RTW_IEEE80211_PREQ_TO_FLAG)) &&
++					(path->flags & RTW_MESH_PATH_ACTIVE)) {
++				reply = _TRUE;
++				target_metric = path->metric;
++				target_sn = path->sn;
++				/* Case E2 of sec 13.10.9.3 IEEE 802.11-2012*/
++				target_flags |= RTW_IEEE80211_PREQ_TO_FLAG;
++			}
++		}
++		rtw_rcu_read_unlock();
++	}
++
++	if (reply) {
++		lifetime = RTW_PREQ_IE_LIFETIME(preq_elem);
++		ttl = mshcfg->element_ttl;
++		if (ttl != 0 && !to_gate_ask) {
++			RTW_HWMP_DBG("replying to the PREQ\n");
++			rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, 0, originator_addr,
++						   originator_sn, 0, target_addr,
++						   target_sn, mgmt->addr2, 0, ttl,
++						   lifetime, target_metric, 0,
++						   adapter);
++		} else if (ttl != 0 && to_gate_ask) {
++			RTW_HWMP_DBG("replying to the PREQ (PREQ for us)\n");
++			if (mshcfg->dot11MeshGateAnnouncementProtocol) {
++				/* BIT 7 is used to identify the prep is from mesh gate */
++				to_gate_ask = RTW_IEEE80211_PREQ_IS_GATE_FLAG | BIT(7);
++			} else {
++				to_gate_ask = 0;
++			}
++
++			rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, to_gate_ask, originator_addr,
++						   originator_sn, 0, target_addr,
++						   target_sn, mgmt->addr2, 0, ttl,
++						   lifetime, target_metric, 0,
++						   adapter);
++		} else {
++			minfo->mshstats.dropped_frames_ttl++;
++		}
++	}
++
++	if (forward && mshcfg->dot11MeshForwarding) {
++		u32 preq_id;
++		u8 hopcount;
++
++		ttl = RTW_PREQ_IE_TTL(preq_elem);
++		lifetime = RTW_PREQ_IE_LIFETIME(preq_elem);
++		if (ttl <= 1) {
++			minfo->mshstats.dropped_frames_ttl++;
++			return;
++		}
++		RTW_HWMP_DBG("forwarding the PREQ from "MAC_FMT"\n", MAC_ARG(originator_addr));
++		--ttl;
++		preq_id = RTW_PREQ_IE_PREQ_ID(preq_elem);
++		hopcount = RTW_PREQ_IE_HOPCOUNT(preq_elem) + 1;
++		da = (path && path->is_root) ?
++			path->rann_snd_addr : bcast_addr;
++
++		if (flags & RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG) {
++			target_addr = RTW_PREQ_IE_TARGET_ADDR(preq_elem);
++			target_sn = RTW_PREQ_IE_TARGET_SN(preq_elem);
++		}
++
++		rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, originator_addr,
++					   originator_sn, target_flags, target_addr,
++					   target_sn, da, hopcount, ttl, lifetime,
++					   originator_metric, preq_id, adapter);
++		if (!is_multicast_mac_addr(da))
++			minfo->mshstats.fwded_unicast++;
++		else
++			minfo->mshstats.fwded_mcast++;
++		minfo->mshstats.fwded_frames++;
++	}
++}
++
++static inline struct sta_info *
++rtw_next_hop_deref_protected(struct rtw_mesh_path *path)
++{
++	return rtw_rcu_dereference_protected(path->next_hop,
++					 rtw_lockdep_is_held(&path->state_lock));
++}
++
++static void rtw_hwmp_prep_frame_process(_adapter *adapter,
++					struct rtw_ieee80211_hdr_3addr *mgmt,
++					const u8 *prep_elem, u32 metric)
++{
++	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
++	struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats;
++	struct rtw_mesh_path *path;
++	const u8 *target_addr, *originator_addr;
++	u8 ttl, hopcount, flags;
++	u8 next_hop[ETH_ALEN];
++	u32 target_sn, originator_sn, lifetime;
++
++	RTW_HWMP_DBG("received PREP from "MAC_FMT"\n",
++		  MAC_ARG(RTW_PREP_IE_TARGET_ADDR(prep_elem)));
++
++	originator_addr = RTW_PREP_IE_ORIG_ADDR(prep_elem);
++	if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter))) {
++		/* destination, no forwarding required */
++		rtw_rcu_read_lock();
++		target_addr = RTW_PREP_IE_TARGET_ADDR(prep_elem);
++		path = rtw_mesh_path_lookup(adapter, target_addr);
++		if (path && path->gate_asked) {
++			flags = RTW_PREP_IE_FLAGS(prep_elem);
++			if (flags & BIT(7)) {
++				enter_critical_bh(&path->state_lock);
++				path->gate_asked = false;
++				exit_critical_bh(&path->state_lock);
++				if (!(flags & RTW_IEEE80211_PREQ_IS_GATE_FLAG)) {
++					enter_critical_bh(&path->state_lock);
++					rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
++					exit_critical_bh(&path->state_lock);
++				}
++			}
++		}
++
++		rtw_rcu_read_unlock();
++		return;
++	}
++
++	if (!mshcfg->dot11MeshForwarding)
++		return;
++
++	ttl = RTW_PREP_IE_TTL(prep_elem);
++	if (ttl <= 1) {
++		mshstats->dropped_frames_ttl++;
++		return;
++	}
++
++	rtw_rcu_read_lock();
++	path = rtw_mesh_path_lookup(adapter, originator_addr);
++	if (path)
++		enter_critical_bh(&path->state_lock);
++	else
++		goto fail;
++	if (!(path->flags & RTW_MESH_PATH_ACTIVE)) {
++		exit_critical_bh(&path->state_lock);
++		goto fail;
++	}
++	_rtw_memcpy(next_hop, rtw_next_hop_deref_protected(path)->cmn.mac_addr, ETH_ALEN);
++	exit_critical_bh(&path->state_lock);
++	--ttl;
++	flags = RTW_PREP_IE_FLAGS(prep_elem);
++	lifetime = RTW_PREP_IE_LIFETIME(prep_elem);
++	hopcount = RTW_PREP_IE_HOPCOUNT(prep_elem) + 1;
++	target_addr = RTW_PREP_IE_TARGET_ADDR(prep_elem);
++	target_sn = RTW_PREP_IE_TARGET_SN(prep_elem);
++	originator_sn = RTW_PREP_IE_ORIG_SN(prep_elem);
++
++	rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, flags, originator_addr, originator_sn, 0,
++				   target_addr, target_sn, next_hop, hopcount,
++				   ttl, lifetime, metric, 0, adapter);
++	rtw_rcu_read_unlock();
++
++	mshstats->fwded_unicast++;
++	mshstats->fwded_frames++;
++	return;
++
++fail:
++	rtw_rcu_read_unlock();
++	mshstats->dropped_frames_no_route++;
++}
++
++static void rtw_hwmp_perr_frame_process(_adapter *adapter,
++					struct rtw_ieee80211_hdr_3addr *mgmt,
++					const u8 *perr_elem)
++{
++	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
++	struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats;
++	struct rtw_mesh_path *path;
++	u8 ttl;
++	const u8 *ta, *target_addr;
++	u32 target_sn;
++	u16 perr_reason_code;
++
++	ta = mgmt->addr2;
++	ttl = RTW_PERR_IE_TTL(perr_elem);
++	if (ttl <= 1) {
++		mshstats->dropped_frames_ttl++;
++		return;
++	}
++	ttl--;
++	target_addr = RTW_PERR_IE_TARGET_ADDR(perr_elem);
++	target_sn = RTW_PERR_IE_TARGET_SN(perr_elem);
++	perr_reason_code = RTW_PERR_IE_TARGET_RCODE(perr_elem);
++
++	RTW_HWMP_DBG("received PERR toward target "MAC_FMT"\n", MAC_ARG(target_addr));
++
++	rtw_rcu_read_lock();
++	path = rtw_mesh_path_lookup(adapter, target_addr);
++	if (path) {
++		struct sta_info *sta;
++
++		enter_critical_bh(&path->state_lock);
++		sta = rtw_next_hop_deref_protected(path);
++		if (path->flags & RTW_MESH_PATH_ACTIVE &&
++		    rtw_ether_addr_equal(ta, sta->cmn.mac_addr) &&
++		    !(path->flags & RTW_MESH_PATH_FIXED) &&
++		    (!(path->flags & RTW_MESH_PATH_SN_VALID) ||
++		    RTW_SN_GT(target_sn, path->sn)  || target_sn == 0)) {
++			path->flags &= ~RTW_MESH_PATH_ACTIVE;
++			if (target_sn != 0)
++				path->sn = target_sn;
++			else
++				path->sn += 1;
++			exit_critical_bh(&path->state_lock);
++			if (!mshcfg->dot11MeshForwarding)
++				goto endperr;
++			rtw_mesh_path_error_tx(adapter, ttl, target_addr,
++					       target_sn, perr_reason_code,
++					       bcast_addr);
++		} else
++			exit_critical_bh(&path->state_lock);
++	}
++endperr:
++	rtw_rcu_read_unlock();
++}
++
++static void rtw_hwmp_rann_frame_process(_adapter *adapter,
++					struct rtw_ieee80211_hdr_3addr *mgmt,
++					const struct rtw_ieee80211_rann_ie *rann)
++{
++	struct sta_info *sta;
++	struct sta_priv *pstapriv = &adapter->stapriv;
++	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
++	struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats;
++	struct rtw_mesh_path *path;
++	u8 ttl, flags, hopcount;
++	const u8 *originator_addr;
++	u32 originator_sn, metric, metric_txsta, interval;
++	BOOLEAN root_is_gate;
++
++	ttl = rann->rann_ttl;
++	flags = rann->rann_flags;
++	root_is_gate = !!(flags & RTW_RANN_FLAG_IS_GATE);
++	originator_addr = rann->rann_addr;
++	originator_sn = le32_to_cpu(rann->rann_seq);
++	interval = le32_to_cpu(rann->rann_interval);
++	hopcount = rann->rann_hopcount;
++	hopcount++;
++	metric = le32_to_cpu(rann->rann_metric);
++
++	/*  Ignore our own RANNs */
++	if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter)))
++		return;
++
++	RTW_HWMP_DBG("received RANN from "MAC_FMT" via neighbour "MAC_FMT" (is_gate=%d)\n",
++		  MAC_ARG(originator_addr), MAC_ARG(mgmt->addr2), root_is_gate);
++
++	rtw_rcu_read_lock();
++	sta = rtw_get_stainfo(pstapriv, mgmt->addr2);
++	if (!sta) {
++		rtw_rcu_read_unlock();
++		return;
++	}
++
++	metric_txsta = rtw_airtime_link_metric_get(adapter, sta);
++
++	path = rtw_mesh_path_lookup(adapter, originator_addr);
++	if (!path) {
++		path = rtw_mesh_path_add(adapter, originator_addr);
++		if (IS_ERR(path)) {
++			rtw_rcu_read_unlock();
++			mshstats->dropped_frames_no_route++;
++			return;
++		}
++	}
++
++	if (!(RTW_SN_LT(path->sn, originator_sn)) &&
++	    !(path->sn == originator_sn && metric < path->rann_metric)) {
++		rtw_rcu_read_unlock();
++		return;
++	}
++
++	if ((!(path->flags & (RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVING)) ||
++	     (rtw_time_after(rtw_get_current_time(), path->last_preq_to_root +
++				  rtw_root_path_confirmation_jiffies(adapter)) ||
++	     rtw_time_before(rtw_get_current_time(), path->last_preq_to_root))) &&
++	     !(path->flags & RTW_MESH_PATH_FIXED) && (ttl != 0)) {
++		u8 preq_node_flag = RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH;
++
++		RTW_HWMP_DBG("time to refresh root path "MAC_FMT"\n",
++			  MAC_ARG(originator_addr));
++#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
++		if (RTW_SN_LT(path->sn, originator_sn) &&
++		    (path->rann_metric + mshcfg->sane_metric_delta < metric) &&
++		    _rtw_memcmp(bcast_addr, path->rann_snd_addr, ETH_ALEN) == _FALSE) {
++			RTW_HWMP_DBG("Trigger additional check for root "
++				     "confirm PREQ. rann_snd_addr = "MAC_FMT
++				     "add_chk_rann_snd_addr= "MAC_FMT"\n",
++					MAC_ARG(mgmt->addr2),
++					MAC_ARG(path->rann_snd_addr));
++			_rtw_memcpy(path->add_chk_rann_snd_addr,
++				    path->rann_snd_addr, ETH_ALEN);
++			preq_node_flag |= RTW_PREQ_Q_F_CHK;
++			
++		}
++#endif
++		rtw_mesh_queue_preq(path, preq_node_flag);
++		path->last_preq_to_root = rtw_get_current_time();
++	}
++
++	path->sn = originator_sn;
++	path->rann_metric = metric + metric_txsta;
++	path->is_root = _TRUE;
++	/* Recording RANNs sender address to send individually
++	 * addressed PREQs destined for root mesh STA */
++	_rtw_memcpy(path->rann_snd_addr, mgmt->addr2, ETH_ALEN);
++
++	if (root_is_gate) {
++		path->gate_ann_int = interval;
++		path->gate_asked = false;
++		rtw_mesh_path_add_gate(path);
++	} else if (path->is_gate) {
++		enter_critical_bh(&path->state_lock);
++		rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
++		exit_critical_bh(&path->state_lock);
++	}
++
++	if (ttl <= 1) {
++		mshstats->dropped_frames_ttl++;
++		rtw_rcu_read_unlock();
++		return;
++	}
++	ttl--;
++
++	if (mshcfg->dot11MeshForwarding) {
++		rtw_mesh_path_sel_frame_tx(RTW_MPATH_RANN, flags, originator_addr,
++					   originator_sn, 0, NULL, 0, bcast_addr,
++					   hopcount, ttl, interval,
++					   metric + metric_txsta, 0, adapter);
++	}
++
++	rtw_rcu_read_unlock();
++}
++
++static u32 rtw_hwmp_route_info_get(_adapter *adapter,
++				   struct rtw_ieee80211_hdr_3addr *mgmt,
++				   const u8 *hwmp_ie, enum rtw_mpath_frame_type action)
++{
++	struct rtw_mesh_path *path;
++	struct sta_priv *pstapriv = &adapter->stapriv;
++	struct sta_info *sta;
++	BOOLEAN fresh_info;
++	const u8 *originator_addr, *ta;
++	u32 originator_sn, originator_metric;
++	unsigned long originator_lifetime, exp_time;
++	u32 last_hop_metric, new_metric;
++	BOOLEAN process = _TRUE;
++
++	rtw_rcu_read_lock();
++	sta = rtw_get_stainfo(pstapriv, mgmt->addr2);
++	if (!sta) {
++		rtw_rcu_read_unlock();
++		return 0;
++	}
++
++	last_hop_metric = rtw_airtime_link_metric_get(adapter, sta);
++	/* Update and check originator routing info */
++	fresh_info = _TRUE;
++
++	switch (action) {
++	case RTW_MPATH_PREQ:
++		originator_addr = RTW_PREQ_IE_ORIG_ADDR(hwmp_ie);
++		originator_sn = RTW_PREQ_IE_ORIG_SN(hwmp_ie);
++		originator_lifetime = RTW_PREQ_IE_LIFETIME(hwmp_ie);
++		originator_metric = RTW_PREQ_IE_METRIC(hwmp_ie);
++		break;
++	case RTW_MPATH_PREP:
++		/* Note: For coding, the naming is not consist with spec */
++		originator_addr = RTW_PREP_IE_TARGET_ADDR(hwmp_ie);
++		originator_sn = RTW_PREP_IE_TARGET_SN(hwmp_ie);
++		originator_lifetime = RTW_PREP_IE_LIFETIME(hwmp_ie);
++		originator_metric = RTW_PREP_IE_METRIC(hwmp_ie);
++		break;
++	default:
++		rtw_rcu_read_unlock();
++		return 0;
++	}
++	new_metric = originator_metric + last_hop_metric;
++	if (new_metric < originator_metric)
++		new_metric = RTW_MAX_METRIC;
++	exp_time = RTW_TU_TO_EXP_TIME(originator_lifetime);
++
++	if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter))) {
++		process = _FALSE;
++		fresh_info = _FALSE;
++	} else {
++		path = rtw_mesh_path_lookup(adapter, originator_addr);
++		if (path) {
++			enter_critical_bh(&path->state_lock);
++			if (path->flags & RTW_MESH_PATH_FIXED)
++				fresh_info = _FALSE;
++			else if ((path->flags & RTW_MESH_PATH_ACTIVE) &&
++			    (path->flags & RTW_MESH_PATH_SN_VALID)) {
++				if (RTW_SN_GT(path->sn, originator_sn) ||
++				    (path->sn == originator_sn &&
++				     new_metric >= path->metric)) {
++					process = _FALSE;
++					fresh_info = _FALSE;
++				}
++			} else if (!(path->flags & RTW_MESH_PATH_ACTIVE)) {
++				BOOLEAN have_sn, newer_sn, bounced;
++
++				have_sn = path->flags & RTW_MESH_PATH_SN_VALID;
++				newer_sn = have_sn && RTW_SN_GT(originator_sn, path->sn);
++				bounced = have_sn &&
++					  (RTW_SN_DELTA(originator_sn, path->sn) >
++							RTW_MAX_SANE_SN_DELTA);
++
++				if (!have_sn || newer_sn) {
++				} else if (bounced) {
++				} else {
++					process = _FALSE;
++					fresh_info = _FALSE;
++				}
++			}
++		} else {
++			path = rtw_mesh_path_add(adapter, originator_addr);
++			if (IS_ERR(path)) {
++				rtw_rcu_read_unlock();
++				return 0;
++			}
++			enter_critical_bh(&path->state_lock);
++		}
++
++		if (fresh_info) {
++			rtw_mesh_path_assign_nexthop(path, sta);
++			path->flags |= RTW_MESH_PATH_SN_VALID;
++			path->metric = new_metric;
++			path->sn = originator_sn;
++			path->exp_time = rtw_time_after(path->exp_time, exp_time)
++					  ?  path->exp_time : exp_time;
++			rtw_mesh_path_activate(path);
++#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
++			if (path->is_root && (action == RTW_MPATH_PREP)) {
++				_rtw_memcpy(path->rann_snd_addr, 
++				mgmt->addr2, ETH_ALEN);
++				path->rann_metric = new_metric;
++			}
++#endif
++			exit_critical_bh(&path->state_lock);
++			rtw_mesh_path_tx_pending(path);
++		} else
++			exit_critical_bh(&path->state_lock);
++	}
++
++	/* Update and check transmitter routing info */
++	ta = mgmt->addr2;
++	if (rtw_ether_addr_equal(originator_addr, ta))
++		fresh_info = _FALSE;
++	else {
++		fresh_info = _TRUE;
++
++		path = rtw_mesh_path_lookup(adapter, ta);
++		if (path) {
++			enter_critical_bh(&path->state_lock);
++			if ((path->flags & RTW_MESH_PATH_FIXED) ||
++				((path->flags & RTW_MESH_PATH_ACTIVE) &&
++					(last_hop_metric > path->metric)))
++				fresh_info = _FALSE;
++		} else {
++			path = rtw_mesh_path_add(adapter, ta);
++			if (IS_ERR(path)) {
++				rtw_rcu_read_unlock();
++				return 0;
++			}
++			enter_critical_bh(&path->state_lock);
++		}
++
++		if (fresh_info) {
++			rtw_mesh_path_assign_nexthop(path, sta);
++			path->metric = last_hop_metric;
++			path->exp_time = rtw_time_after(path->exp_time, exp_time)
++					  ?  path->exp_time : exp_time;
++			rtw_mesh_path_activate(path);
++			exit_critical_bh(&path->state_lock);
++			rtw_mesh_path_tx_pending(path);
++		} else
++			exit_critical_bh(&path->state_lock);
++	}
++
++	rtw_rcu_read_unlock();
++
++	return process ? new_metric : 0;
++}
++
++static void rtw_mesh_rx_hwmp_frame_cnts(_adapter *adapter, u8 *addr)
++{
++	struct sta_info *sta;
++
++	sta = rtw_get_stainfo(&adapter->stapriv, addr);
++	if (sta)
++		sta->sta_stats.rx_hwmp_pkts++;
++}
++
++void rtw_mesh_rx_path_sel_frame(_adapter *adapter, union recv_frame *rframe)
++{
++	struct mesh_plink_ent *plink = NULL;
++	struct rtw_ieee802_11_elems elems;
++	u32 path_metric;
++	struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib;
++	u8 *pframe = rframe->u.hdr.rx_data, *start;
++	uint frame_len = rframe->u.hdr.len, left;
++	struct rtw_ieee80211_hdr_3addr *frame_hdr = (struct rtw_ieee80211_hdr_3addr *)pframe;
++	u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++	ParseRes parse_res;
++
++	plink = rtw_mesh_plink_get(adapter, get_addr2_ptr(pframe));
++	if (!plink || plink->plink_state != RTW_MESH_PLINK_ESTAB)
++		return;
++
++	rtw_mesh_rx_hwmp_frame_cnts(adapter, get_addr2_ptr(pframe));
++
++	/* Mesh action frame IE offset = 2 */
++	attrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++	left = frame_len - attrib->hdrlen - attrib->iv_len - attrib->icv_len - 2;
++	start = pframe + attrib->hdrlen + 2;
++
++	parse_res = rtw_ieee802_11_parse_elems(start, left, &elems, 1);
++	if (parse_res == ParseFailed)
++		RTW_HWMP_INFO(FUNC_ADPT_FMT" Path Select Frame ParseFailed\n"
++			, FUNC_ADPT_ARG(adapter));
++	else if (parse_res == ParseUnknown)
++		RTW_HWMP_INFO(FUNC_ADPT_FMT" Path Select Frame ParseUnknown\n"
++			, FUNC_ADPT_ARG(adapter));
++
++	if (elems.preq) {
++		if (elems.preq_len != 37)
++			/* Right now we support just 1 destination and no AE */
++			return;
++		path_metric = rtw_hwmp_route_info_get(adapter, frame_hdr, elems.preq,
++						  MPATH_PREQ);
++		if (path_metric)
++			rtw_hwmp_preq_frame_process(adapter, frame_hdr, elems.preq,
++						path_metric);
++	}
++	if (elems.prep) {
++		if (elems.prep_len != 31)
++			/* Right now we support no AE */
++			return;
++		path_metric = rtw_hwmp_route_info_get(adapter, frame_hdr, elems.prep,
++						  MPATH_PREP);
++		if (path_metric)
++			rtw_hwmp_prep_frame_process(adapter, frame_hdr, elems.prep,
++						path_metric);
++	}
++	if (elems.perr) {
++		if (elems.perr_len != 15)
++			/* Right now we support only one destination per PERR */
++			return;
++		rtw_hwmp_perr_frame_process(adapter, frame_hdr, elems.perr);
++	}
++	if (elems.rann)
++		rtw_hwmp_rann_frame_process(adapter, frame_hdr, (struct rtw_ieee80211_rann_ie *)elems.rann);
++}
++
++void rtw_mesh_queue_preq(struct rtw_mesh_path *path, u8 flags)
++{
++	_adapter *adapter = path->adapter;
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct rtw_mesh_preq_queue *preq_node;
++
++	preq_node = rtw_malloc(sizeof(struct rtw_mesh_preq_queue));
++	if (!preq_node) {
++		RTW_HWMP_INFO("could not allocate PREQ node\n");
++		return;
++	}
++
++	enter_critical_bh(&minfo->mesh_preq_queue_lock);
++	if (minfo->preq_queue_len == RTW_MAX_PREQ_QUEUE_LEN) {
++		exit_critical_bh(&minfo->mesh_preq_queue_lock);
++		rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue));
++		if (rtw_print_ratelimit())
++			RTW_HWMP_INFO("PREQ node queue full\n");
++		return;
++	}
++
++	_rtw_spinlock(&path->state_lock);
++	if (path->flags & RTW_MESH_PATH_REQ_QUEUED) {
++		_rtw_spinunlock(&path->state_lock);
++		exit_critical_bh(&minfo->mesh_preq_queue_lock);
++		rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue));
++		return;
++	}
++
++	_rtw_memcpy(preq_node->dst, path->dst, ETH_ALEN);
++	preq_node->flags = flags;
++
++	path->flags |= RTW_MESH_PATH_REQ_QUEUED;
++#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
++	if (flags & RTW_PREQ_Q_F_CHK)
++		path->flags |= RTW_MESH_PATH_ROOT_ADD_CHK;
++#endif
++	if (flags & RTW_PREQ_Q_F_PEER_AKA)
++		path->flags |= RTW_MESH_PATH_PEER_AKA;
++	if (flags & RTW_PREQ_Q_F_BCAST_PREQ)
++		path->flags |= RTW_MESH_PATH_BCAST_PREQ;
++	_rtw_spinunlock(&path->state_lock);
++
++	rtw_list_insert_tail(&preq_node->list, &minfo->preq_queue.list);
++	++minfo->preq_queue_len;
++	exit_critical_bh(&minfo->mesh_preq_queue_lock);
++
++	if (rtw_time_after(rtw_get_current_time(), minfo->last_preq + rtw_min_preq_int_jiff(adapter)))
++		rtw_mesh_work(&adapter->mesh_work);
++
++	else if (rtw_time_before(rtw_get_current_time(), minfo->last_preq)) {
++		/* systime wrapped around issue */
++		minfo->last_preq = rtw_get_current_time() - rtw_min_preq_int_jiff(adapter) - 1;
++		rtw_mesh_work(&adapter->mesh_work);
++	} else
++		rtw_mod_timer(&adapter->mesh_path_timer, minfo->last_preq +
++					rtw_min_preq_int_jiff(adapter) + 1);
++}
++
++static const u8 *rtw_hwmp_preq_da(struct rtw_mesh_path *path,
++			    BOOLEAN is_root_add_chk, BOOLEAN da_is_peer,
++			    BOOLEAN force_preq_bcast)
++{
++	const u8 *da;
++
++	if (da_is_peer)
++		da = path->dst;
++	else if (force_preq_bcast)
++		da = bcast_addr;
++	else if (path->is_root)
++#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
++		da = is_root_add_chk ? path->add_chk_rann_snd_addr:
++				       path->rann_snd_addr;
++#else
++		da = path->rann_snd_addr;
++#endif
++	else
++		da = bcast_addr;
++
++	return da;
++}
++
++void rtw_mesh_path_start_discovery(_adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
++	struct rtw_mesh_preq_queue *preq_node;
++	struct rtw_mesh_path *path;
++	u8 ttl, target_flags = 0;
++	const u8 *da;
++	u32 lifetime;
++	u8 flags = 0;
++	BOOLEAN is_root_add_chk = _FALSE;
++	BOOLEAN da_is_peer, force_preq_bcast;
++
++	enter_critical_bh(&minfo->mesh_preq_queue_lock);
++	if (!minfo->preq_queue_len ||
++		rtw_time_before(rtw_get_current_time(), minfo->last_preq +
++				rtw_min_preq_int_jiff(adapter))) {
++		exit_critical_bh(&minfo->mesh_preq_queue_lock);
++		return;
++	}
++
++	preq_node = rtw_list_first_entry(&minfo->preq_queue.list,
++			struct rtw_mesh_preq_queue, list);
++	rtw_list_delete(&preq_node->list); /* list_del_init(&preq_node->list); */
++	--minfo->preq_queue_len;
++	exit_critical_bh(&minfo->mesh_preq_queue_lock);
++
++	rtw_rcu_read_lock();
++	path = rtw_mesh_path_lookup(adapter, preq_node->dst);
++	if (!path)
++		goto enddiscovery;
++
++	enter_critical_bh(&path->state_lock);
++	if (path->flags & (RTW_MESH_PATH_DELETED | RTW_MESH_PATH_FIXED)) {
++		exit_critical_bh(&path->state_lock);
++		goto enddiscovery;
++	}
++	path->flags &= ~RTW_MESH_PATH_REQ_QUEUED;
++	if (preq_node->flags & RTW_PREQ_Q_F_START) {
++		if (path->flags & RTW_MESH_PATH_RESOLVING) {
++			exit_critical_bh(&path->state_lock);
++			goto enddiscovery;
++		} else {
++			path->flags &= ~RTW_MESH_PATH_RESOLVED;
++			path->flags |= RTW_MESH_PATH_RESOLVING;
++			path->discovery_retries = 0;
++			path->discovery_timeout = rtw_disc_timeout_jiff(adapter);
++		}
++	} else if (!(path->flags & RTW_MESH_PATH_RESOLVING) ||
++			path->flags & RTW_MESH_PATH_RESOLVED) {
++		path->flags &= ~RTW_MESH_PATH_RESOLVING;
++		exit_critical_bh(&path->state_lock);
++		goto enddiscovery;
++	}
++
++	minfo->last_preq = rtw_get_current_time();
++
++	if (rtw_time_after(rtw_get_current_time(), minfo->last_sn_update +
++				rtw_net_traversal_jiffies(adapter)) ||
++	    rtw_time_before(rtw_get_current_time(), minfo->last_sn_update)) {
++		++minfo->sn;
++		minfo->last_sn_update = rtw_get_current_time();
++	}
++	lifetime = rtw_default_lifetime(adapter);
++	ttl = mshcfg->element_ttl;
++	if (ttl == 0) {
++		minfo->mshstats.dropped_frames_ttl++;
++		exit_critical_bh(&path->state_lock);
++		goto enddiscovery;
++	}
++
++	if (preq_node->flags & RTW_PREQ_Q_F_REFRESH)
++		target_flags |= RTW_IEEE80211_PREQ_TO_FLAG;
++	else
++		target_flags &= ~RTW_IEEE80211_PREQ_TO_FLAG;
++
++#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
++	is_root_add_chk = !!(path->flags & RTW_MESH_PATH_ROOT_ADD_CHK);
++#endif
++	da_is_peer = !!(path->flags & RTW_MESH_PATH_PEER_AKA);
++	force_preq_bcast = !!(path->flags & RTW_MESH_PATH_BCAST_PREQ);
++	exit_critical_bh(&path->state_lock);
++
++	da = rtw_hwmp_preq_da(path, is_root_add_chk,
++			      da_is_peer, force_preq_bcast);
++
++#ifdef CONFIG_RTW_MESH_ON_DMD_GANN
++	flags = (mshcfg->dot11MeshGateAnnouncementProtocol)
++		? RTW_IEEE80211_PREQ_IS_GATE_FLAG : 0;
++#endif
++	rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, adapter_mac_addr(adapter), minfo->sn,
++				   target_flags, path->dst, path->sn, da, 0,
++				   ttl, lifetime, 0, minfo->preq_id++, adapter);
++	rtw_mod_timer(&path->timer, rtw_get_current_time() + path->discovery_timeout);
++
++enddiscovery:
++	rtw_rcu_read_unlock();
++	rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue));
++}
++
++void rtw_mesh_path_timer(void *ctx)
++{
++	struct rtw_mesh_path *path = (void *) ctx;
++	_adapter *adapter = path->adapter;
++	int ret;
++	u8 retry = 0;
++#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
++	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
++#endif
++	/* TBD: Proctect for suspend */
++#if 0
++	if (suspending)
++		return;
++#endif
++	enter_critical_bh(&path->state_lock);
++	if (path->flags & RTW_MESH_PATH_RESOLVED ||
++			(!(path->flags & RTW_MESH_PATH_RESOLVING))) {
++		path->flags &= ~(RTW_MESH_PATH_RESOLVING |
++				 RTW_MESH_PATH_RESOLVED |
++				 RTW_MESH_PATH_ROOT_ADD_CHK |
++				 RTW_MESH_PATH_PEER_AKA |
++				 RTW_MESH_PATH_BCAST_PREQ);
++		exit_critical_bh(&path->state_lock);
++	} else if (path->discovery_retries < rtw_max_preq_retries(adapter)) {
++		++path->discovery_retries;
++		path->discovery_timeout *= 2;
++		path->flags &= ~RTW_MESH_PATH_REQ_QUEUED;
++#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
++		if (path->discovery_retries > mshcfg->max_root_add_chk_cnt)
++			path->flags &= ~RTW_MESH_PATH_ROOT_ADD_CHK;
++#endif
++		if (path->gate_asked)
++			retry |= RTW_PREQ_Q_F_REFRESH;
++
++		exit_critical_bh(&path->state_lock);
++		rtw_mesh_queue_preq(path, retry);
++	} else {
++		path->flags &= ~(RTW_MESH_PATH_RESOLVING |
++				  RTW_MESH_PATH_RESOLVED |
++				  RTW_MESH_PATH_REQ_QUEUED |
++				  RTW_MESH_PATH_ROOT_ADD_CHK |
++				  RTW_MESH_PATH_PEER_AKA |
++				  RTW_MESH_PATH_BCAST_PREQ);
++		path->exp_time = rtw_get_current_time();
++		exit_critical_bh(&path->state_lock);
++		if (!path->is_gate && rtw_mesh_gate_num(adapter) > 0) {
++			ret = rtw_mesh_path_send_to_gates(path);
++			if (ret)
++				RTW_HWMP_DBG("no gate was reachable\n");
++		} else
++			rtw_mesh_path_flush_pending(path);
++	}
++}
++
++
++void rtw_mesh_path_tx_root_frame(_adapter *adapter)
++{
++	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	u32 interval = mshcfg->dot11MeshHWMPRannInterval;
++	u8 flags, target_flags = 0;
++
++	flags = (mshcfg->dot11MeshGateAnnouncementProtocol)
++			? RTW_RANN_FLAG_IS_GATE : 0;
++
++	switch (mshcfg->dot11MeshHWMPRootMode) {
++	case RTW_IEEE80211_PROACTIVE_RANN:
++		rtw_mesh_path_sel_frame_tx(RTW_MPATH_RANN, flags, adapter_mac_addr(adapter),
++					   ++minfo->sn, 0, NULL, 0, bcast_addr,
++					   0, mshcfg->element_ttl,
++					   interval, 0, 0, adapter);
++		break;
++	case RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP:
++		flags |= RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG;
++	case RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP:
++		interval = mshcfg->dot11MeshHWMPactivePathToRootTimeout;
++		target_flags |= RTW_IEEE80211_PREQ_TO_FLAG |
++				RTW_IEEE80211_PREQ_USN_FLAG;
++		rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, adapter_mac_addr(adapter),
++					   ++minfo->sn, target_flags,
++					   (u8 *) bcast_addr, 0, bcast_addr,
++					   0, mshcfg->element_ttl, interval,
++					   0, minfo->preq_id++, adapter);
++		break;
++	default:
++		RTW_HWMP_INFO("Proactive mechanism not supported\n");
++		return;
++	}
++}
++
++void rtw_mesh_work(_workitem *work)
++{
++	/* use kernel global workqueue */
++	_set_workitem(work);
++}
++
++void rtw_ieee80211_mesh_path_timer(void *ctx)
++{
++	_adapter *adapter = (_adapter *)ctx;
++	rtw_mesh_work(&adapter->mesh_work);
++}
++
++void rtw_ieee80211_mesh_path_root_timer(void *ctx)
++{
++	_adapter *adapter = (_adapter *)ctx;
++
++	rtw_set_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags);
++
++	rtw_mesh_work(&adapter->mesh_work);
++}
++
++static void rtw_ieee80211_mesh_rootpath(_adapter *adapter)
++{
++	u32 interval;
++
++	rtw_mesh_path_tx_root_frame(adapter);
++
++	if (adapter->mesh_cfg.dot11MeshHWMPRootMode == RTW_IEEE80211_PROACTIVE_RANN)
++		interval = adapter->mesh_cfg.dot11MeshHWMPRannInterval;
++	else
++		interval = adapter->mesh_cfg.dot11MeshHWMProotInterval;
++
++	rtw_mod_timer(&adapter->mesh_path_root_timer,
++		  RTW_TU_TO_EXP_TIME(interval));
++}
++
++BOOLEAN rtw_ieee80211_mesh_root_setup(_adapter *adapter)
++{
++	BOOLEAN root_enabled = _FALSE;
++
++	if (adapter->mesh_cfg.dot11MeshHWMPRootMode > RTW_IEEE80211_ROOTMODE_ROOT) {
++		rtw_set_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags);
++		root_enabled = _TRUE;
++	}
++	else {
++		rtw_clear_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags);
++		/* stop running timer */
++		_cancel_timer_ex(&adapter->mesh_path_root_timer);
++		root_enabled = _FALSE;
++	}
++
++	return root_enabled;
++}
++
++void rtw_mesh_work_hdl(_workitem *work)
++{
++	_adapter *adapter = container_of(work, _adapter, mesh_work);
++
++	while(adapter->mesh_info.preq_queue_len) {
++		if (rtw_time_after(rtw_get_current_time(),
++		       adapter->mesh_info.last_preq + rtw_min_preq_int_jiff(adapter)))
++		       /* It will consume preq_queue_len */
++		       rtw_mesh_path_start_discovery(adapter);
++		else {
++			struct rtw_mesh_info *minfo = &adapter->mesh_info;
++
++			rtw_mod_timer(&adapter->mesh_path_timer,
++				minfo->last_preq + rtw_min_preq_int_jiff(adapter) + 1);
++			break;
++		}
++	}
++
++	if (rtw_test_and_clear_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags))
++		rtw_ieee80211_mesh_rootpath(adapter);
++}
++
++#ifndef RTW_PER_CMD_SUPPORT_FW
++static void rtw_update_metric_directly(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++	u8 i;
++
++	for (i = 0; i < macid_ctl->num; i++) {
++		u8 role;
++		role = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]);
++		if (role == H2C_MSR_ROLE_MESH) {
++			struct sta_info *sta = macid_ctl->sta[i];
++			u8 rate_idx, sgi, bw;
++			u32 rate;
++
++			if (!sta)
++				continue;
++			rate_idx = rtw_get_current_tx_rate(adapter, sta);
++			sgi = rtw_get_current_tx_sgi(adapter, sta);
++			bw = sta->cmn.bw_mode;
++			rate = rtw_desc_rate_to_bitrate(bw, rate_idx, sgi);
++			sta->metrics.data_rate = rate;
++		}
++	}
++}
++#endif
++
++void rtw_mesh_atlm_param_req_timer(void *ctx)
++{
++	_adapter *adapter = (_adapter *)ctx;
++	u8 ret = _FAIL;
++
++#ifdef RTW_PER_CMD_SUPPORT_FW
++	ret = rtw_req_per_cmd(adapter);
++	if (ret == _FAIL)
++		RTW_HWMP_INFO("rtw_req_per_cmd fail\n");
++#else
++	rtw_update_metric_directly(adapter);
++#endif
++	_set_timer(&adapter->mesh_atlm_param_req_timer, RTW_ATLM_REQ_CYCLE);
++}
++
++#endif /* CONFIG_RTW_MESH */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh_hwmp.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh_hwmp.h
+new file mode 100644
+index 000000000..943341781
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh_hwmp.h
+@@ -0,0 +1,60 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_MESH_HWMP_H_
++#define __RTW_MESH_HWMP_H_
++
++#ifndef DBG_RTW_HWMP
++#define DBG_RTW_HWMP 0
++#endif
++#if DBG_RTW_HWMP
++#define RTW_HWMP_DBG(fmt, arg...) RTW_PRINT(fmt, ##arg)
++#else
++#define RTW_HWMP_DBG(fmt, arg...) RTW_DBG(fmt, ##arg)
++#endif
++
++#ifndef INFO_RTW_HWMP
++#define INFO_RTW_HWMP 0
++#endif
++#if INFO_RTW_HWMP
++#define RTW_HWMP_INFO(fmt, arg...) RTW_PRINT(fmt, ##arg)
++#else
++#define RTW_HWMP_INFO(fmt, arg...) RTW_INFO(fmt, ##arg)
++#endif
++
++
++void rtw_ewma_err_rate_init(struct rtw_ewma_err_rate *e);
++unsigned long rtw_ewma_err_rate_read(struct rtw_ewma_err_rate *e);
++void rtw_ewma_err_rate_add(struct rtw_ewma_err_rate *e, unsigned long val);
++int rtw_mesh_path_error_tx(_adapter *adapter,
++			   u8 ttl, const u8 *target, u32 target_sn,
++			   u16 target_rcode, const u8 *ra);
++void rtw_ieee80211s_update_metric(_adapter *adapter, u8 mac_id,
++				  u8 per, u8 rate,
++				  u8 bw, u8 total_pkt);
++void rtw_mesh_rx_path_sel_frame(_adapter *adapter, union recv_frame *rframe);
++void rtw_mesh_queue_preq(struct rtw_mesh_path *mpath, u8 flags);
++void rtw_mesh_path_start_discovery(_adapter *adapter);
++void rtw_mesh_path_timer(void *ctx);
++void rtw_mesh_path_tx_root_frame(_adapter *adapter);
++void rtw_mesh_work_hdl(_workitem *work);
++void rtw_ieee80211_mesh_path_timer(void *ctx);
++void rtw_ieee80211_mesh_path_root_timer(void *ctx);
++BOOLEAN rtw_ieee80211_mesh_root_setup(_adapter *adapter);
++void rtw_mesh_work(_workitem *work);
++void rtw_mesh_atlm_param_req_timer(void *ctx);
++
++#endif /* __RTW_MESH_HWMP_H_ */
++
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh_pathtbl.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh_pathtbl.c
+new file mode 100644
+index 000000000..b74b56792
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh_pathtbl.c
+@@ -0,0 +1,1242 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_MESH_PATHTBL_C_
++
++#ifdef CONFIG_RTW_MESH
++#include <drv_types.h>
++#include <linux/jhash.h>
++
++#ifdef PLATFORM_LINUX
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++static void rtw_mpath_free_rcu(struct rtw_mesh_path *mpath)
++{
++	kfree_rcu(mpath, rcu);
++	rtw_mstat_update(MSTAT_TYPE_PHY, MSTAT_FREE, sizeof(struct rtw_mesh_path));
++}
++#else
++static void rtw_mpath_free_rcu_callback(rtw_rcu_head *head)
++{
++	struct rtw_mesh_path *mpath;
++
++	mpath = container_of(head, struct rtw_mesh_path, rcu);
++	rtw_mfree(mpath, sizeof(struct rtw_mesh_path));
++}
++
++static void rtw_mpath_free_rcu(struct rtw_mesh_path *mpath)
++{
++	call_rcu(&mpath->rcu, rtw_mpath_free_rcu_callback);
++}
++#endif
++#endif /* PLATFORM_LINUX */
++
++static void rtw_mesh_path_free_rcu(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath);
++
++static u32 rtw_mesh_table_hash(const void *addr, u32 len, u32 seed)
++{
++	/* Use last four bytes of hw addr as hash index */
++	return jhash_1word(*(u32 *)(addr+2), seed);
++}
++
++static const rtw_rhashtable_params rtw_mesh_rht_params = {
++	.nelem_hint = 2,
++	.automatic_shrinking = true,
++	.key_len = ETH_ALEN,
++	.key_offset = offsetof(struct rtw_mesh_path, dst),
++	.head_offset = offsetof(struct rtw_mesh_path, rhash),
++	.hashfn = rtw_mesh_table_hash,
++};
++
++static inline bool rtw_mpath_expired(struct rtw_mesh_path *mpath)
++{
++	return (mpath->flags & RTW_MESH_PATH_ACTIVE) &&
++	       rtw_time_after(rtw_get_current_time(), mpath->exp_time) &&
++	       !(mpath->flags & RTW_MESH_PATH_FIXED);
++}
++
++static void rtw_mesh_path_rht_free(void *ptr, void *tblptr)
++{
++	struct rtw_mesh_path *mpath = ptr;
++	struct rtw_mesh_table *tbl = tblptr;
++
++	rtw_mesh_path_free_rcu(tbl, mpath);
++}
++
++static struct rtw_mesh_table *rtw_mesh_table_alloc(void)
++{
++	struct rtw_mesh_table *newtbl;
++
++	newtbl = rtw_malloc(sizeof(struct rtw_mesh_table));
++	if (!newtbl)
++		return NULL;
++
++	rtw_hlist_head_init(&newtbl->known_gates);
++	ATOMIC_SET(&newtbl->entries,  0);
++	_rtw_spinlock_init(&newtbl->gates_lock);
++
++	return newtbl;
++}
++
++static void rtw_mesh_table_free(struct rtw_mesh_table *tbl)
++{
++	rtw_rhashtable_free_and_destroy(&tbl->rhead,
++				    rtw_mesh_path_rht_free, tbl);
++	rtw_mfree(tbl, sizeof(struct rtw_mesh_table));
++}
++
++/**
++ *
++ * rtw_mesh_path_assign_nexthop - update mesh path next hop
++ *
++ * @mpath: mesh path to update
++ * @sta: next hop to assign
++ *
++ * Locking: mpath->state_lock must be held when calling this function
++ */
++void rtw_mesh_path_assign_nexthop(struct rtw_mesh_path *mpath, struct sta_info *sta)
++{
++	struct xmit_frame *xframe;
++	_list *list, *head;
++
++	rtw_rcu_assign_pointer(mpath->next_hop, sta);
++
++	enter_critical_bh(&mpath->frame_queue.lock);
++	head = &mpath->frame_queue.queue;
++	list = get_next(head);
++	while (rtw_end_of_queue_search(head, list) == _FALSE) {
++		xframe = LIST_CONTAINOR(list, struct xmit_frame, list);
++		list = get_next(list);
++		_rtw_memcpy(xframe->attrib.ra, sta->cmn.mac_addr, ETH_ALEN);
++	}
++
++	exit_critical_bh(&mpath->frame_queue.lock);
++}
++
++static void rtw_prepare_for_gate(struct xmit_frame *xframe, char *dst_addr,
++			     struct rtw_mesh_path *gate_mpath)
++{
++	struct pkt_attrib *attrib = &xframe->attrib;
++	char *next_hop;
++
++	if (attrib->mesh_frame_mode == MESH_UCAST_DATA)
++		attrib->mesh_frame_mode = MESH_UCAST_PX_DATA;
++
++	/* update next hop */
++	rtw_rcu_read_lock();
++	next_hop = rtw_rcu_dereference(gate_mpath->next_hop)->cmn.mac_addr;
++	_rtw_memcpy(attrib->ra, next_hop, ETH_ALEN);
++	rtw_rcu_read_unlock();
++	_rtw_memcpy(attrib->mda, dst_addr, ETH_ALEN);
++}
++
++/**
++ *
++ * rtw_mesh_path_move_to_queue - Move or copy frames from one mpath queue to another
++ *
++ * This function is used to transfer or copy frames from an unresolved mpath to
++ * a gate mpath.  The function also adds the Address Extension field and
++ * updates the next hop.
++ *
++ * If a frame already has an Address Extension field, only the next hop and
++ * destination addresses are updated.
++ *
++ * The gate mpath must be an active mpath with a valid mpath->next_hop.
++ *
++ * @mpath: An active mpath the frames will be sent to (i.e. the gate)
++ * @from_mpath: The failed mpath
++ * @copy: When true, copy all the frames to the new mpath queue.  When false,
++ * move them.
++ */
++static void rtw_mesh_path_move_to_queue(struct rtw_mesh_path *gate_mpath,
++				    struct rtw_mesh_path *from_mpath,
++				    bool copy)
++{
++	struct xmit_frame *fskb;
++	_list *list, *head;
++	_list failq;
++	u32 failq_len;
++	_irqL flags;
++
++	if (rtw_warn_on(gate_mpath == from_mpath))
++		return;
++	if (rtw_warn_on(!gate_mpath->next_hop))
++		return;
++
++	_rtw_init_listhead(&failq);
++
++	_enter_critical_bh(&from_mpath->frame_queue.lock, &flags);
++	rtw_list_splice_init(&from_mpath->frame_queue.queue, &failq);
++	failq_len = from_mpath->frame_queue_len;
++	from_mpath->frame_queue_len = 0;
++	_exit_critical_bh(&from_mpath->frame_queue.lock, &flags);
++
++	head = &failq;
++	list = get_next(head);
++	while (rtw_end_of_queue_search(head, list) == _FALSE) {
++		if (gate_mpath->frame_queue_len >= RTW_MESH_FRAME_QUEUE_LEN) {
++			RTW_MPATH_DBG(FUNC_ADPT_FMT" mpath queue for gate %pM is full!\n"
++				, FUNC_ADPT_ARG(gate_mpath->adapter), gate_mpath->dst);
++			break;
++		}
++
++		fskb = LIST_CONTAINOR(list, struct xmit_frame, list);
++		list = get_next(list);
++
++		rtw_list_delete(&fskb->list);
++		failq_len--;
++		rtw_prepare_for_gate(fskb, gate_mpath->dst, gate_mpath);
++		_enter_critical_bh(&gate_mpath->frame_queue.lock, &flags);
++		rtw_list_insert_tail(&fskb->list, get_list_head(&gate_mpath->frame_queue));
++		gate_mpath->frame_queue_len++;
++		_exit_critical_bh(&gate_mpath->frame_queue.lock, &flags);
++
++		#if 0 /* TODO: copy */
++		skb = rtw_skb_copy(fskb);
++		if (rtw_warn_on(!skb))
++			break;
++
++		rtw_prepare_for_gate(skb, gate_mpath->dst, gate_mpath);
++		skb_queue_tail(&gate_mpath->frame_queue, skb);
++
++		if (copy)
++			continue;
++
++		__skb_unlink(fskb, &failq);
++		rtw_skb_free(fskb);
++		#endif
++	}
++
++	RTW_MPATH_DBG(FUNC_ADPT_FMT" mpath queue for gate %pM has %d frames\n"
++		, FUNC_ADPT_ARG(gate_mpath->adapter), gate_mpath->dst, gate_mpath->frame_queue_len);
++
++	if (!copy)
++		return;
++
++	_enter_critical_bh(&from_mpath->frame_queue.lock, &flags);
++	rtw_list_splice(&failq, &from_mpath->frame_queue.queue);
++	from_mpath->frame_queue_len += failq_len;
++	_exit_critical_bh(&from_mpath->frame_queue.lock, &flags);
++}
++
++
++static struct rtw_mesh_path *rtw_mpath_lookup(struct rtw_mesh_table *tbl, const u8 *dst)
++{
++	struct rtw_mesh_path *mpath;
++
++	if (!tbl)
++		return NULL;
++
++	mpath = rtw_rhashtable_lookup_fast(&tbl->rhead, dst, rtw_mesh_rht_params);
++
++	if (mpath && rtw_mpath_expired(mpath)) {
++		enter_critical_bh(&mpath->state_lock);
++		mpath->flags &= ~RTW_MESH_PATH_ACTIVE;
++		exit_critical_bh(&mpath->state_lock);
++	}
++	return mpath;
++}
++
++/**
++ * rtw_mesh_path_lookup - look up a path in the mesh path table
++ * @sdata: local subif
++ * @dst: hardware address (ETH_ALEN length) of destination
++ *
++ * Returns: pointer to the mesh path structure, or NULL if not found
++ *
++ * Locking: must be called within a read rcu section.
++ */
++struct rtw_mesh_path *
++rtw_mesh_path_lookup(_adapter *adapter, const u8 *dst)
++{
++	return rtw_mpath_lookup(adapter->mesh_info.mesh_paths, dst);
++}
++
++struct rtw_mesh_path *
++rtw_mpp_path_lookup(_adapter *adapter, const u8 *dst)
++{
++	return rtw_mpath_lookup(adapter->mesh_info.mpp_paths, dst);
++}
++
++static struct rtw_mesh_path *
++__rtw_mesh_path_lookup_by_idx(struct rtw_mesh_table *tbl, int idx)
++{
++	int i = 0, ret;
++	struct rtw_mesh_path *mpath = NULL;
++	rtw_rhashtable_iter iter;
++
++	if (!tbl)
++		return NULL;
++
++	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
++	if (ret)
++		return NULL;
++
++	ret = rtw_rhashtable_walk_start(&iter);
++	if (ret && ret != -EAGAIN)
++		goto err;
++
++	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
++		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
++			continue;
++		if (IS_ERR(mpath))
++			break;
++		if (i++ == idx)
++			break;
++	}
++err:
++	rtw_rhashtable_walk_stop(&iter);
++	rtw_rhashtable_walk_exit(&iter);
++
++	if (IS_ERR(mpath) || !mpath)
++		return NULL;
++
++	if (rtw_mpath_expired(mpath)) {
++		enter_critical_bh(&mpath->state_lock);
++		mpath->flags &= ~RTW_MESH_PATH_ACTIVE;
++		exit_critical_bh(&mpath->state_lock);
++	}
++	return mpath;
++}
++
++/**
++ * rtw_mesh_path_lookup_by_idx - look up a path in the mesh path table by its index
++ * @idx: index
++ * @sdata: local subif, or NULL for all entries
++ *
++ * Returns: pointer to the mesh path structure, or NULL if not found.
++ *
++ * Locking: must be called within a read rcu section.
++ */
++struct rtw_mesh_path *
++rtw_mesh_path_lookup_by_idx(_adapter *adapter, int idx)
++{
++	return __rtw_mesh_path_lookup_by_idx(adapter->mesh_info.mesh_paths, idx);
++}
++
++void dump_mpath(void *sel, _adapter *adapter)
++{
++	struct rtw_mesh_path *mpath;
++	int idx = 0;
++	char dst[ETH_ALEN];
++	char next_hop[ETH_ALEN];
++	u32 sn, metric, qlen;
++	u32 exp_ms = 0, dto_ms;
++	u8 drty;
++	enum rtw_mesh_path_flags flags;
++
++	RTW_PRINT_SEL(sel, "%-17s %-17s %-10s %-10s %-4s %-6s %-6s %-4s flags\n"
++		, "dst", "next_hop", "sn", "metric", "qlen", "exp_ms", "dto_ms", "drty"
++	);
++
++	do {
++		rtw_rcu_read_lock();
++
++		mpath = rtw_mesh_path_lookup_by_idx(adapter, idx);
++		if (mpath) {
++			_rtw_memcpy(dst, mpath->dst, ETH_ALEN);
++			_rtw_memcpy(next_hop, mpath->next_hop->cmn.mac_addr, ETH_ALEN);
++			sn = mpath->sn;
++			metric = mpath->metric;
++			qlen = mpath->frame_queue_len;
++			if (rtw_time_after(mpath->exp_time, rtw_get_current_time()))
++				exp_ms = rtw_get_remaining_time_ms(mpath->exp_time);
++			dto_ms = rtw_systime_to_ms(mpath->discovery_timeout);
++			drty = mpath->discovery_retries;
++			flags = mpath->flags;
++		}
++
++		rtw_rcu_read_unlock();
++
++		if (mpath) {
++			RTW_PRINT_SEL(sel, MAC_FMT" "MAC_FMT" %10u %10u %4u %6u %6u %4u%s%s%s%s%s%s%s%s%s%s\n"
++				, MAC_ARG(dst), MAC_ARG(next_hop), sn, metric, qlen
++				, exp_ms < 999999 ? exp_ms : 999999
++				, dto_ms < 999999 ? dto_ms : 999999
++				, drty
++				, (flags & RTW_MESH_PATH_ACTIVE) ? " ACT" : ""
++				, (flags & RTW_MESH_PATH_RESOLVING) ? " RSVING" : ""
++				, (flags & RTW_MESH_PATH_SN_VALID) ? " SN_VALID" : ""
++				, (flags & RTW_MESH_PATH_FIXED) ?  " FIXED" : ""
++				, (flags & RTW_MESH_PATH_RESOLVED) ? " RSVED" : ""
++				, (flags & RTW_MESH_PATH_REQ_QUEUED) ? " REQ_IN_Q" : ""
++				, (flags & RTW_MESH_PATH_DELETED) ? " DELETED" : ""
++				, (flags & RTW_MESH_PATH_ROOT_ADD_CHK) ? " R_ADD_CHK" : ""
++				, (flags & RTW_MESH_PATH_PEER_AKA) ? " PEER_AKA" : ""
++				, (flags & RTW_MESH_PATH_BCAST_PREQ) ? " BC_PREQ" : ""
++			);
++		}
++
++		idx++;
++	} while (mpath);
++}
++
++/**
++ * rtw_mpp_path_lookup_by_idx - look up a path in the proxy path table by its index
++ * @idx: index
++ * @sdata: local subif, or NULL for all entries
++ *
++ * Returns: pointer to the proxy path structure, or NULL if not found.
++ *
++ * Locking: must be called within a read rcu section.
++ */
++struct rtw_mesh_path *
++rtw_mpp_path_lookup_by_idx(_adapter *adapter, int idx)
++{
++	return __rtw_mesh_path_lookup_by_idx(adapter->mesh_info.mpp_paths, idx);
++}
++
++/**
++ * rtw_mesh_path_add_gate - add the given mpath to a mesh gate to our path table
++ * @mpath: gate path to add to table
++ */
++int rtw_mesh_path_add_gate(struct rtw_mesh_path *mpath)
++{
++	struct rtw_mesh_cfg *mcfg;
++	struct rtw_mesh_info *minfo;
++	struct rtw_mesh_table *tbl;
++	int err, ori_num_gates;
++
++	rtw_rcu_read_lock();
++	tbl = mpath->adapter->mesh_info.mesh_paths;
++	if (!tbl) {
++		err = -ENOENT;
++		goto err_rcu;
++	}
++
++	enter_critical_bh(&mpath->state_lock);
++	mcfg = &mpath->adapter->mesh_cfg;
++	mpath->gate_timeout = rtw_get_current_time() +
++			      rtw_ms_to_systime(mcfg->path_gate_timeout_factor *
++					        mpath->gate_ann_int);
++	if (mpath->is_gate) {
++		err = -EEXIST;
++		exit_critical_bh(&mpath->state_lock);
++		goto err_rcu;
++	}
++
++	minfo = &mpath->adapter->mesh_info;
++	mpath->is_gate = true;
++	_rtw_spinlock(&tbl->gates_lock);
++	ori_num_gates = minfo->num_gates;
++	minfo->num_gates++;
++	rtw_hlist_add_head_rcu(&mpath->gate_list, &tbl->known_gates);
++
++	if (ori_num_gates == 0
++		|| rtw_macaddr_is_larger(mpath->dst, minfo->max_addr_gate->dst)
++	) {
++		minfo->max_addr_gate = mpath;
++		minfo->max_addr_gate_is_larger_than_self =
++			rtw_macaddr_is_larger(mpath->dst, adapter_mac_addr(mpath->adapter));
++	}
++
++	_rtw_spinunlock(&tbl->gates_lock);
++
++	exit_critical_bh(&mpath->state_lock);
++
++	if (ori_num_gates == 0) {
++		update_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE, 0);
++		#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER
++		if (!rtw_mesh_cto_mgate_required(mpath->adapter))
++			rtw_netif_carrier_on(mpath->adapter->pnetdev);
++		#endif
++	}
++
++	RTW_MPATH_DBG(
++		  FUNC_ADPT_FMT" Mesh path: Recorded new gate: %pM. %d known gates\n",
++		  FUNC_ADPT_ARG(mpath->adapter),
++		  mpath->dst, mpath->adapter->mesh_info.num_gates);
++	err = 0;
++err_rcu:
++	rtw_rcu_read_unlock();
++	return err;
++}
++
++/**
++ * rtw_mesh_gate_del - remove a mesh gate from the list of known gates
++ * @tbl: table which holds our list of known gates
++ * @mpath: gate mpath
++ */
++void rtw_mesh_gate_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath)
++{
++	struct rtw_mesh_cfg *mcfg;
++	struct rtw_mesh_info *minfo;
++	int ori_num_gates;
++
++	rtw_lockdep_assert_held(&mpath->state_lock);
++	if (!mpath->is_gate)
++		return;
++
++	mcfg = &mpath->adapter->mesh_cfg;
++	minfo = &mpath->adapter->mesh_info;
++
++	mpath->is_gate = false;
++	enter_critical_bh(&tbl->gates_lock);
++	rtw_hlist_del_rcu(&mpath->gate_list);
++	ori_num_gates = minfo->num_gates;
++	minfo->num_gates--;
++
++	if (ori_num_gates == 1) {
++		minfo->max_addr_gate = NULL;
++		minfo->max_addr_gate_is_larger_than_self = 0;
++	} else if (minfo->max_addr_gate == mpath) {
++		struct rtw_mesh_path *gate, *max_addr_gate = NULL;
++		rtw_hlist_node *node;
++
++		rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
++			if (!max_addr_gate || rtw_macaddr_is_larger(gate->dst, max_addr_gate->dst))
++				max_addr_gate = gate;
++		}
++		minfo->max_addr_gate = max_addr_gate;
++		minfo->max_addr_gate_is_larger_than_self =
++			rtw_macaddr_is_larger(max_addr_gate->dst, adapter_mac_addr(mpath->adapter));
++	}
++
++	exit_critical_bh(&tbl->gates_lock);
++
++	if (ori_num_gates == 1) {
++		update_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE, 0);
++		#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER
++		if (rtw_mesh_cto_mgate_required(mpath->adapter))
++			rtw_netif_carrier_off(mpath->adapter->pnetdev);
++		#endif
++	}
++
++	RTW_MPATH_DBG(
++		  FUNC_ADPT_FMT" Mesh path: Deleted gate: %pM. %d known gates\n",
++		  FUNC_ADPT_ARG(mpath->adapter),
++		  mpath->dst, mpath->adapter->mesh_info.num_gates);
++}
++
++/**
++ * rtw_mesh_gate_search - search a mesh gate from the list of known gates
++ * @tbl: table which holds our list of known gates
++ * @addr: address of gate
++ */
++bool rtw_mesh_gate_search(struct rtw_mesh_table *tbl, const u8 *addr)
++{
++	struct rtw_mesh_path *gate;
++	rtw_hlist_node *node;
++	bool exist = 0;
++
++	rtw_rcu_read_lock();
++	rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
++		if (_rtw_memcmp(gate->dst, addr, ETH_ALEN) == _TRUE) {
++			exist = 1;
++			break;
++		}
++	}
++
++	rtw_rcu_read_unlock();
++
++	return exist;
++}
++
++/**
++ * rtw_mesh_gate_num - number of gates known to this interface
++ * @sdata: subif data
++ */
++int rtw_mesh_gate_num(_adapter *adapter)
++{
++	return adapter->mesh_info.num_gates;
++}
++
++bool rtw_mesh_is_primary_gate(_adapter *adapter)
++{
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++
++	return mcfg->dot11MeshGateAnnouncementProtocol
++		&& !minfo->max_addr_gate_is_larger_than_self;
++}
++
++void dump_known_gates(void *sel, _adapter *adapter)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct rtw_mesh_table *tbl;
++	struct rtw_mesh_path *gate;
++	rtw_hlist_node *node;
++
++	if (!rtw_mesh_gate_num(adapter))
++		goto exit;
++
++	rtw_rcu_read_lock();
++
++	tbl = minfo->mesh_paths;
++	if (!tbl)
++		goto unlock;
++
++	RTW_PRINT_SEL(sel, "num:%d\n", rtw_mesh_gate_num(adapter));
++
++	rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
++		RTW_PRINT_SEL(sel, "%c"MAC_FMT"\n"
++			, gate == minfo->max_addr_gate ? '*' : ' '
++			, MAC_ARG(gate->dst));
++	}
++
++unlock:
++	rtw_rcu_read_unlock();
++exit:
++	return;
++}
++
++static
++struct rtw_mesh_path *rtw_mesh_path_new(_adapter *adapter,
++				const u8 *dst)
++{
++	struct rtw_mesh_path *new_mpath;
++
++	new_mpath = rtw_zmalloc(sizeof(struct rtw_mesh_path));
++	if (!new_mpath)
++		return NULL;
++
++	_rtw_memcpy(new_mpath->dst, dst, ETH_ALEN);
++	_rtw_memset(new_mpath->rann_snd_addr, 0xFF, ETH_ALEN);
++	new_mpath->is_root = false;
++	new_mpath->adapter = adapter;
++	new_mpath->flags = 0;
++	new_mpath->gate_asked = false;
++	_rtw_init_queue(&new_mpath->frame_queue);
++	new_mpath->frame_queue_len = 0;
++	new_mpath->exp_time = rtw_get_current_time();
++	_rtw_spinlock_init(&new_mpath->state_lock);
++	rtw_init_timer(&new_mpath->timer, adapter, rtw_mesh_path_timer, new_mpath);
++
++	return new_mpath;
++}
++
++/**
++ * rtw_mesh_path_add - allocate and add a new path to the mesh path table
++ * @dst: destination address of the path (ETH_ALEN length)
++ * @sdata: local subif
++ *
++ * Returns: 0 on success
++ *
++ * State: the initial state of the new path is set to 0
++ */
++struct rtw_mesh_path *rtw_mesh_path_add(_adapter *adapter,
++				const u8 *dst)
++{
++	struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths;
++	struct rtw_mesh_path *mpath, *new_mpath;
++	int ret;
++
++	if (!tbl)
++		return ERR_PTR(-ENOTSUPP);
++
++	if (_rtw_memcmp(dst, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)
++		/* never add ourselves as neighbours */
++		return ERR_PTR(-ENOTSUPP);
++
++	if (is_multicast_mac_addr(dst))
++		return ERR_PTR(-ENOTSUPP);
++
++	if (ATOMIC_INC_UNLESS(&adapter->mesh_info.mpaths, RTW_MESH_MAX_MPATHS) == 0)
++		return ERR_PTR(-ENOSPC);
++
++	new_mpath = rtw_mesh_path_new(adapter, dst);
++	if (!new_mpath)
++		return ERR_PTR(-ENOMEM);
++
++	do {
++		ret = rtw_rhashtable_lookup_insert_fast(&tbl->rhead,
++						    &new_mpath->rhash,
++						    rtw_mesh_rht_params);
++
++		if (ret == -EEXIST)
++			mpath = rtw_rhashtable_lookup_fast(&tbl->rhead,
++						       dst,
++						       rtw_mesh_rht_params);
++
++	} while (unlikely(ret == -EEXIST && !mpath));
++
++	if (ret && ret != -EEXIST)
++		return ERR_PTR(ret);
++
++	/* At this point either new_mpath was added, or we found a
++	 * matching entry already in the table; in the latter case
++	 * free the unnecessary new entry.
++	 */
++	if (ret == -EEXIST) {
++		rtw_mfree(new_mpath, sizeof(struct rtw_mesh_path));
++		new_mpath = mpath;
++	}
++	adapter->mesh_info.mesh_paths_generation++;
++	return new_mpath;
++}
++
++int rtw_mpp_path_add(_adapter *adapter,
++		 const u8 *dst, const u8 *mpp)
++{
++	struct rtw_mesh_table *tbl = adapter->mesh_info.mpp_paths;
++	struct rtw_mesh_path *new_mpath;
++	int ret;
++
++	if (!tbl)
++		return -ENOTSUPP;
++
++	if (_rtw_memcmp(dst, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)
++		/* never add ourselves as neighbours */
++		return -ENOTSUPP;
++
++	if (is_multicast_mac_addr(dst))
++		return -ENOTSUPP;
++
++	new_mpath = rtw_mesh_path_new(adapter, dst);
++
++	if (!new_mpath)
++		return -ENOMEM;
++
++	_rtw_memcpy(new_mpath->mpp, mpp, ETH_ALEN);
++	ret = rtw_rhashtable_lookup_insert_fast(&tbl->rhead,
++					    &new_mpath->rhash,
++					    rtw_mesh_rht_params);
++
++	adapter->mesh_info.mpp_paths_generation++;
++	return ret;
++}
++
++void dump_mpp(void *sel, _adapter *adapter)
++{
++	struct rtw_mesh_path *mpath;
++	int idx = 0;
++	char dst[ETH_ALEN];
++	char mpp[ETH_ALEN];
++
++	RTW_PRINT_SEL(sel, "%-17s %-17s\n", "dst", "mpp");
++
++	do {
++		rtw_rcu_read_lock();
++
++		mpath = rtw_mpp_path_lookup_by_idx(adapter, idx);
++		if (mpath) {
++			_rtw_memcpy(dst, mpath->dst, ETH_ALEN);
++			_rtw_memcpy(mpp, mpath->mpp, ETH_ALEN);
++		}
++
++		rtw_rcu_read_unlock();
++
++		if (mpath) {
++			RTW_PRINT_SEL(sel, MAC_FMT" "MAC_FMT"\n"
++				, MAC_ARG(dst), MAC_ARG(mpp));
++		}
++
++		idx++;
++	} while (mpath);
++}
++
++/**
++ * rtw_mesh_plink_broken - deactivates paths and sends perr when a link breaks
++ *
++ * @sta: broken peer link
++ *
++ * This function must be called from the rate control algorithm if enough
++ * delivery errors suggest that a peer link is no longer usable.
++ */
++void rtw_mesh_plink_broken(struct sta_info *sta)
++{
++	_adapter *adapter = sta->padapter;
++	struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths;
++	static const u8 bcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	struct rtw_mesh_path *mpath;
++	rtw_rhashtable_iter iter;
++	int ret;
++
++	if (!tbl)
++		return;
++
++	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
++	if (ret)
++		return;
++
++	ret = rtw_rhashtable_walk_start(&iter);
++	if (ret && ret != -EAGAIN)
++		goto out;
++
++	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
++		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
++			continue;
++		if (IS_ERR(mpath))
++			break;
++		if (rtw_rcu_access_pointer(mpath->next_hop) == sta &&
++		    mpath->flags & RTW_MESH_PATH_ACTIVE &&
++		    !(mpath->flags & RTW_MESH_PATH_FIXED)) {
++			enter_critical_bh(&mpath->state_lock);
++			mpath->flags &= ~RTW_MESH_PATH_ACTIVE;
++			++mpath->sn;
++			exit_critical_bh(&mpath->state_lock);
++			rtw_mesh_path_error_tx(adapter,
++				adapter->mesh_cfg.element_ttl,
++				mpath->dst, mpath->sn,
++				WLAN_REASON_MESH_PATH_DEST_UNREACHABLE, bcast);
++		}
++	}
++out:
++	rtw_rhashtable_walk_stop(&iter);
++	rtw_rhashtable_walk_exit(&iter);
++}
++
++static void rtw_mesh_path_free_rcu(struct rtw_mesh_table *tbl,
++			       struct rtw_mesh_path *mpath)
++{
++	_adapter *adapter = mpath->adapter;
++
++	enter_critical_bh(&mpath->state_lock);
++	mpath->flags |= RTW_MESH_PATH_RESOLVING | RTW_MESH_PATH_DELETED;
++	rtw_mesh_gate_del(tbl, mpath);
++	exit_critical_bh(&mpath->state_lock);
++	_cancel_timer_ex(&mpath->timer);
++	ATOMIC_DEC(&adapter->mesh_info.mpaths);
++	ATOMIC_DEC(&tbl->entries);
++	_rtw_spinlock_free(&mpath->state_lock);
++
++	rtw_mesh_path_flush_pending(mpath);
++
++	rtw_mpath_free_rcu(mpath);
++}
++
++static void __rtw_mesh_path_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath)
++{
++	rtw_rhashtable_remove_fast(&tbl->rhead, &mpath->rhash, rtw_mesh_rht_params);
++	rtw_mesh_path_free_rcu(tbl, mpath);
++}
++
++/**
++ * rtw_mesh_path_flush_by_nexthop - Deletes mesh paths if their next hop matches
++ *
++ * @sta: mesh peer to match
++ *
++ * RCU notes: this function is called when a mesh plink transitions from
++ * PLINK_ESTAB to any other state, since PLINK_ESTAB state is the only one that
++ * allows path creation. This will happen before the sta can be freed (because
++ * sta_info_destroy() calls this) so any reader in a rcu read block will be
++ * protected against the plink disappearing.
++ */
++void rtw_mesh_path_flush_by_nexthop(struct sta_info *sta)
++{
++	_adapter *adapter = sta->padapter;
++	struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths;
++	struct rtw_mesh_path *mpath;
++	rtw_rhashtable_iter iter;
++	int ret;
++
++	if (!tbl)
++		return;
++
++	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
++	if (ret)
++		return;
++
++	ret = rtw_rhashtable_walk_start(&iter);
++	if (ret && ret != -EAGAIN)
++		goto out;
++
++	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
++		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
++			continue;
++		if (IS_ERR(mpath))
++			break;
++
++		if (rtw_rcu_access_pointer(mpath->next_hop) == sta)
++			__rtw_mesh_path_del(tbl, mpath);
++	}
++out:
++	rtw_rhashtable_walk_stop(&iter);
++	rtw_rhashtable_walk_exit(&iter);
++}
++
++static void rtw_mpp_flush_by_proxy(_adapter *adapter,
++			       const u8 *proxy)
++{
++	struct rtw_mesh_table *tbl = adapter->mesh_info.mpp_paths;
++	struct rtw_mesh_path *mpath;
++	rtw_rhashtable_iter iter;
++	int ret;
++
++	if (!tbl)
++		return;
++
++	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
++	if (ret)
++		return;
++
++	ret = rtw_rhashtable_walk_start(&iter);
++	if (ret && ret != -EAGAIN)
++		goto out;
++
++	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
++		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
++			continue;
++		if (IS_ERR(mpath))
++			break;
++
++		if (_rtw_memcmp(mpath->mpp, proxy, ETH_ALEN) == _TRUE)
++			__rtw_mesh_path_del(tbl, mpath);
++	}
++out:
++	rtw_rhashtable_walk_stop(&iter);
++	rtw_rhashtable_walk_exit(&iter);
++}
++
++static void rtw_table_flush_by_iface(struct rtw_mesh_table *tbl)
++{
++	struct rtw_mesh_path *mpath;
++	rtw_rhashtable_iter iter;
++	int ret;
++
++	if (!tbl)
++		return;
++	
++	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
++	if (ret)
++		return;
++
++	ret = rtw_rhashtable_walk_start(&iter);
++	if (ret && ret != -EAGAIN)
++		goto out;
++
++	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
++		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
++			continue;
++		if (IS_ERR(mpath))
++			break;
++		__rtw_mesh_path_del(tbl, mpath);
++	}
++out:
++	rtw_rhashtable_walk_stop(&iter);
++	rtw_rhashtable_walk_exit(&iter);
++}
++
++/**
++ * rtw_mesh_path_flush_by_iface - Deletes all mesh paths associated with a given iface
++ *
++ * This function deletes both mesh paths as well as mesh portal paths.
++ *
++ * @sdata: interface data to match
++ *
++ */
++void rtw_mesh_path_flush_by_iface(_adapter *adapter)
++{
++	rtw_table_flush_by_iface(adapter->mesh_info.mesh_paths);
++	rtw_table_flush_by_iface(adapter->mesh_info.mpp_paths);
++}
++
++/**
++ * rtw_table_path_del - delete a path from the mesh or mpp table
++ *
++ * @tbl: mesh or mpp path table
++ * @sdata: local subif
++ * @addr: dst address (ETH_ALEN length)
++ *
++ * Returns: 0 if successful
++ */
++static int rtw_table_path_del(struct rtw_mesh_table *tbl,
++			  const u8 *addr)
++{
++	struct rtw_mesh_path *mpath;
++
++	if (!tbl)
++		return -ENXIO;
++
++	rtw_rcu_read_lock();
++	mpath = rtw_rhashtable_lookup_fast(&tbl->rhead, addr, rtw_mesh_rht_params);
++	if (!mpath) {
++		rtw_rcu_read_unlock();
++		return -ENXIO;
++	}
++
++	__rtw_mesh_path_del(tbl, mpath);
++	rtw_rcu_read_unlock();
++	return 0;
++}
++
++
++/**
++ * rtw_mesh_path_del - delete a mesh path from the table
++ *
++ * @addr: dst address (ETH_ALEN length)
++ * @sdata: local subif
++ *
++ * Returns: 0 if successful
++ */
++int rtw_mesh_path_del(_adapter *adapter, const u8 *addr)
++{
++	int err;
++
++	/* flush relevant mpp entries first */
++	rtw_mpp_flush_by_proxy(adapter, addr);
++
++	err = rtw_table_path_del(adapter->mesh_info.mesh_paths, addr);
++	adapter->mesh_info.mesh_paths_generation++;
++	return err;
++}
++
++/**
++ * rtw_mesh_path_tx_pending - sends pending frames in a mesh path queue
++ *
++ * @mpath: mesh path to activate
++ *
++ * Locking: the state_lock of the mpath structure must NOT be held when calling
++ * this function.
++ */
++void rtw_mesh_path_tx_pending(struct rtw_mesh_path *mpath)
++{
++	if (mpath->flags & RTW_MESH_PATH_ACTIVE) {
++		struct rtw_mesh_info *minfo = &mpath->adapter->mesh_info;
++		_list q;
++		u32 q_len = 0;
++
++		_rtw_init_listhead(&q);
++
++		/* move to local queue */
++		enter_critical_bh(&mpath->frame_queue.lock);
++		if (mpath->frame_queue_len) {
++			rtw_list_splice_init(&mpath->frame_queue.queue, &q);
++			q_len = mpath->frame_queue_len;
++			mpath->frame_queue_len = 0;
++		}
++		exit_critical_bh(&mpath->frame_queue.lock);
++
++		if (q_len) {
++			/* move to mpath_tx_queue */
++			enter_critical_bh(&minfo->mpath_tx_queue.lock);
++			rtw_list_splice_tail(&q, &minfo->mpath_tx_queue.queue);
++			minfo->mpath_tx_queue_len += q_len;
++			exit_critical_bh(&minfo->mpath_tx_queue.lock);
++
++			/* schedule mpath_tx_tasklet */
++			tasklet_hi_schedule(&minfo->mpath_tx_tasklet);
++		}
++	}
++}
++
++/**
++ * rtw_mesh_path_send_to_gates - sends pending frames to all known mesh gates
++ *
++ * @mpath: mesh path whose queue will be emptied
++ *
++ * If there is only one gate, the frames are transferred from the failed mpath
++ * queue to that gate's queue.  If there are more than one gates, the frames
++ * are copied from each gate to the next.  After frames are copied, the
++ * mpath queues are emptied onto the transmission queue.
++ */
++int rtw_mesh_path_send_to_gates(struct rtw_mesh_path *mpath)
++{
++	_adapter *adapter = mpath->adapter;
++	struct rtw_mesh_table *tbl;
++	struct rtw_mesh_path *from_mpath = mpath;
++	struct rtw_mesh_path *gate;
++	bool copy = false;
++	rtw_hlist_node *node;
++
++	tbl = adapter->mesh_info.mesh_paths;
++	if (!tbl)
++		return 0;
++
++	rtw_rcu_read_lock();
++	rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
++		if (gate->flags & RTW_MESH_PATH_ACTIVE) {
++			RTW_MPATH_DBG(FUNC_ADPT_FMT" Forwarding to %pM\n",
++				FUNC_ADPT_ARG(adapter), gate->dst);
++			rtw_mesh_path_move_to_queue(gate, from_mpath, copy);
++			from_mpath = gate;
++			copy = true;
++		} else {
++			RTW_MPATH_DBG(
++				  FUNC_ADPT_FMT" Not forwarding to %pM (flags %#x)\n",
++				  FUNC_ADPT_ARG(adapter), gate->dst, gate->flags);
++		}
++	}
++
++	rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
++		RTW_MPATH_DBG(FUNC_ADPT_FMT" Sending to %pM\n",
++			FUNC_ADPT_ARG(adapter), gate->dst);
++		rtw_mesh_path_tx_pending(gate);
++	}
++	rtw_rcu_read_unlock();
++
++	return (from_mpath == mpath) ? -EHOSTUNREACH : 0;
++}
++
++/**
++ * rtw_mesh_path_discard_frame - discard a frame whose path could not be resolved
++ *
++ * @skb: frame to discard
++ * @sdata: network subif the frame was to be sent through
++ *
++ * Locking: the function must me called within a rcu_read_lock region
++ */
++void rtw_mesh_path_discard_frame(_adapter *adapter,
++			     struct xmit_frame *xframe)
++{
++	rtw_free_xmitframe(&adapter->xmitpriv, xframe);
++	adapter->mesh_info.mshstats.dropped_frames_no_route++;
++}
++
++/**
++ * rtw_mesh_path_flush_pending - free the pending queue of a mesh path
++ *
++ * @mpath: mesh path whose queue has to be freed
++ *
++ * Locking: the function must me called within a rcu_read_lock region
++ */
++void rtw_mesh_path_flush_pending(struct rtw_mesh_path *mpath)
++{
++	struct xmit_frame *xframe;
++	_list *list, *head;
++	_list tmp;
++
++	_rtw_init_listhead(&tmp);
++
++	enter_critical_bh(&mpath->frame_queue.lock);
++	rtw_list_splice_init(&mpath->frame_queue.queue, &tmp);
++	mpath->frame_queue_len = 0;
++	exit_critical_bh(&mpath->frame_queue.lock);
++
++	head = &tmp;
++	list = get_next(head);
++	while (rtw_end_of_queue_search(head, list) == _FALSE) {
++		xframe = LIST_CONTAINOR(list, struct xmit_frame, list);
++		list = get_next(list);
++		rtw_list_delete(&xframe->list);
++		rtw_mesh_path_discard_frame(mpath->adapter, xframe);
++	}
++}
++
++/**
++ * rtw_mesh_path_fix_nexthop - force a specific next hop for a mesh path
++ *
++ * @mpath: the mesh path to modify
++ * @next_hop: the next hop to force
++ *
++ * Locking: this function must be called holding mpath->state_lock
++ */
++void rtw_mesh_path_fix_nexthop(struct rtw_mesh_path *mpath, struct sta_info *next_hop)
++{
++	enter_critical_bh(&mpath->state_lock);
++	rtw_mesh_path_assign_nexthop(mpath, next_hop);
++	mpath->sn = 0xffff;
++	mpath->metric = 0;
++	mpath->hop_count = 0;
++	mpath->exp_time = 0;
++	mpath->flags = RTW_MESH_PATH_FIXED | RTW_MESH_PATH_SN_VALID;
++	rtw_mesh_path_activate(mpath);
++	exit_critical_bh(&mpath->state_lock);
++	rtw_ewma_err_rate_init(&next_hop->metrics.err_rate);
++	/* init it at a low value - 0 start is tricky */
++	rtw_ewma_err_rate_add(&next_hop->metrics.err_rate, 1);
++	rtw_mesh_path_tx_pending(mpath);
++}
++
++int rtw_mesh_pathtbl_init(_adapter *adapter)
++{
++	struct rtw_mesh_table *tbl_path, *tbl_mpp;
++	int ret;
++
++	tbl_path = rtw_mesh_table_alloc();
++	if (!tbl_path)
++		return -ENOMEM;
++
++	tbl_mpp = rtw_mesh_table_alloc();
++	if (!tbl_mpp) {
++		ret = -ENOMEM;
++		goto free_path;
++	}
++
++	rtw_rhashtable_init(&tbl_path->rhead, &rtw_mesh_rht_params);
++	rtw_rhashtable_init(&tbl_mpp->rhead, &rtw_mesh_rht_params);
++
++	adapter->mesh_info.mesh_paths = tbl_path;
++	adapter->mesh_info.mpp_paths = tbl_mpp;
++
++	return 0;
++
++free_path:
++	rtw_mesh_table_free(tbl_path);
++	return ret;
++}
++
++static
++void rtw_mesh_path_tbl_expire(_adapter *adapter,
++			  struct rtw_mesh_table *tbl)
++{
++	struct rtw_mesh_path *mpath;
++	rtw_rhashtable_iter iter;
++	int ret;
++
++	if (!tbl)
++		return;
++
++	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
++	if (ret)
++		return;
++
++	ret = rtw_rhashtable_walk_start(&iter);
++	if (ret && ret != -EAGAIN)
++		goto out;
++
++	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
++		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
++			continue;
++		if (IS_ERR(mpath))
++			break;
++		if ((!(mpath->flags & RTW_MESH_PATH_RESOLVING)) &&
++		    (!(mpath->flags & RTW_MESH_PATH_FIXED)) &&
++		     rtw_time_after(rtw_get_current_time(), mpath->exp_time + RTW_MESH_PATH_EXPIRE))
++			__rtw_mesh_path_del(tbl, mpath);
++
++		if (mpath->is_gate &&  /* need not to deal with non-gate case */
++		    rtw_time_after(rtw_get_current_time(), mpath->gate_timeout)) {
++			RTW_MPATH_DBG(FUNC_ADPT_FMT"mpath [%pM] expired systime is %lu systime is %lu\n",
++				      FUNC_ADPT_ARG(adapter), mpath->dst,
++				      mpath->gate_timeout, rtw_get_current_time());
++			enter_critical_bh(&mpath->state_lock);
++			if (mpath->gate_asked) { /* asked gate before */
++				rtw_mesh_gate_del(tbl, mpath);
++				exit_critical_bh(&mpath->state_lock);
++			} else {
++				mpath->gate_asked = true;
++				mpath->gate_timeout = rtw_get_current_time() + rtw_ms_to_systime(mpath->gate_ann_int);
++				exit_critical_bh(&mpath->state_lock);
++				rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH);
++				RTW_MPATH_DBG(FUNC_ADPT_FMT"mpath [%pM] ask mesh gate existence (is_root=%d)\n",
++				      FUNC_ADPT_ARG(adapter), mpath->dst, mpath->is_root);
++			}
++		}
++	}
++
++out:
++	rtw_rhashtable_walk_stop(&iter);
++	rtw_rhashtable_walk_exit(&iter);
++}
++
++void rtw_mesh_path_expire(_adapter *adapter)
++{
++	rtw_mesh_path_tbl_expire(adapter, adapter->mesh_info.mesh_paths);
++	rtw_mesh_path_tbl_expire(adapter, adapter->mesh_info.mpp_paths);
++}
++
++void rtw_mesh_pathtbl_unregister(_adapter *adapter)
++{
++	if (adapter->mesh_info.mesh_paths) {
++		rtw_mesh_table_free(adapter->mesh_info.mesh_paths);
++		adapter->mesh_info.mesh_paths = NULL;
++	}
++
++	if (adapter->mesh_info.mpp_paths) {
++		rtw_mesh_table_free(adapter->mesh_info.mpp_paths);
++		adapter->mesh_info.mpp_paths = NULL;
++	}
++}
++#endif /* CONFIG_RTW_MESH */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh_pathtbl.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh_pathtbl.h
+new file mode 100644
+index 000000000..be0c40980
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/mesh/rtw_mesh_pathtbl.h
+@@ -0,0 +1,211 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_MESH_PATHTBL_H_
++#define __RTW_MESH_PATHTBL_H_
++
++#ifndef DBG_RTW_MPATH
++#define DBG_RTW_MPATH 1
++#endif
++#if DBG_RTW_MPATH
++#define RTW_MPATH_DBG(fmt, arg...) RTW_PRINT(fmt, ##arg)
++#else
++#define RTW_MPATH_DBG(fmt, arg...) do {} while (0)
++#endif
++
++/**
++ * enum rtw_mesh_path_flags - mesh path flags
++ *
++ * @RTW_MESH_PATH_ACTIVE: the mesh path can be used for forwarding
++ * @RTW_MESH_PATH_RESOLVING: the discovery process is running for this mesh path
++ * @RTW_MESH_PATH_SN_VALID: the mesh path contains a valid destination sequence
++ *	number
++ * @RTW_MESH_PATH_FIXED: the mesh path has been manually set and should not be
++ *	modified
++ * @RTW_MESH_PATH_RESOLVED: the mesh path can has been resolved
++ * @RTW_MESH_PATH_REQ_QUEUED: there is an unsent path request for this destination
++ *	already queued up, waiting for the discovery process to start.
++ * @RTW_MESH_PATH_DELETED: the mesh path has been deleted and should no longer
++ *	be used
++ * @RTW_MESH_PATH_ROOT_ADD_CHK: root additional check in root mode.
++ *	With this flag, It will try the last used rann_snd_addr
++ * @RTW_MESH_PATH_PEER_AKA: only used toward a peer, only used in active keep
++ *	alive mechanism. PREQ's da = path dst
++ * @RTW_MESH_PATH_BCAST_PREQ: for re-checking next hop resolve toward root.
++ *	Use it to force path_discover sending broadcast PREQ for root.
++ * 
++ * RTW_MESH_PATH_RESOLVED is used by the mesh path timer to
++ * decide when to stop or cancel the mesh path discovery.
++ */
++enum rtw_mesh_path_flags {
++	RTW_MESH_PATH_ACTIVE =		BIT(0),
++	RTW_MESH_PATH_RESOLVING =	BIT(1),
++	RTW_MESH_PATH_SN_VALID =	BIT(2),
++	RTW_MESH_PATH_FIXED	=	BIT(3),
++	RTW_MESH_PATH_RESOLVED =	BIT(4),
++	RTW_MESH_PATH_REQ_QUEUED =	BIT(5),
++	RTW_MESH_PATH_DELETED =		BIT(6),
++	RTW_MESH_PATH_ROOT_ADD_CHK =	BIT(7),
++	RTW_MESH_PATH_PEER_AKA =	BIT(8),
++	RTW_MESH_PATH_BCAST_PREQ =	BIT(9),	
++};
++
++/**
++ * struct rtw_mesh_path - mesh path structure
++ *
++ * @dst: mesh path destination mac address
++ * @mpp: mesh proxy mac address
++ * @rhash: rhashtable list pointer
++ * @gate_list: list pointer for known gates list
++ * @sdata: mesh subif
++ * @next_hop: mesh neighbor to which frames for this destination will be
++ *	forwarded
++ * @timer: mesh path discovery timer
++ * @frame_queue: pending queue for frames sent to this destination while the
++ *	path is unresolved
++ * @rcu: rcu head for freeing mesh path
++ * @sn: target sequence number
++ * @metric: current metric to this destination
++ * @hop_count: hops to destination
++ * @exp_time: in jiffies, when the path will expire or when it expired
++ * @discovery_timeout: timeout (lapse in jiffies) used for the last discovery
++ *	retry
++ * @discovery_retries: number of discovery retries
++ * @flags: mesh path flags, as specified on &enum rtw_mesh_path_flags
++ * @state_lock: mesh path state lock used to protect changes to the
++ * mpath itself.  No need to take this lock when adding or removing
++ * an mpath to a hash bucket on a path table.
++ * @rann_snd_addr: the RANN sender address
++ * @rann_metric: the aggregated path metric towards the root node
++ * @last_preq_to_root: Timestamp of last PREQ sent to root
++ * @is_root: the destination station of this path is a root node
++ * @is_gate: the destination station of this path is a mesh gate
++ *
++ *
++ * The dst address is unique in the mesh path table. Since the mesh_path is
++ * protected by RCU, deleting the next_hop STA must remove / substitute the
++ * mesh_path structure and wait until that is no longer reachable before
++ * destroying the STA completely.
++ */
++struct rtw_mesh_path {
++	u8 dst[ETH_ALEN];
++	u8 mpp[ETH_ALEN];	/* used for MPP or MAP */
++	rtw_rhash_head rhash;
++	rtw_hlist_node gate_list;
++	_adapter *adapter;
++	struct sta_info __rcu *next_hop;
++	_timer timer;
++	_queue frame_queue;
++	u32 frame_queue_len;
++	rtw_rcu_head rcu;
++	u32 sn;
++	u32 metric;
++	u8 hop_count;
++	systime exp_time;
++	systime discovery_timeout;
++	systime gate_timeout;
++	u32 gate_ann_int;    /* gate announce interval */
++	u8 discovery_retries;
++	enum rtw_mesh_path_flags flags;
++	_lock state_lock;
++	u8 rann_snd_addr[ETH_ALEN];
++#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
++	u8 add_chk_rann_snd_addr[ETH_ALEN];
++#endif
++	u32 rann_metric;
++	unsigned long last_preq_to_root;
++	bool is_root;
++	bool is_gate;
++	bool gate_asked;
++};
++
++/**
++ * struct rtw_mesh_table
++ *
++ * @known_gates: list of known mesh gates and their mpaths by the station. The
++ * gate's mpath may or may not be resolved and active.
++ * @gates_lock: protects updates to known_gates
++ * @rhead: the rhashtable containing struct mesh_paths, keyed by dest addr
++ * @entries: number of entries in the table
++ */
++struct rtw_mesh_table {
++	rtw_hlist_head known_gates;
++	_lock gates_lock;
++	rtw_rhashtable rhead;
++	ATOMIC_T entries;
++};
++
++#define RTW_MESH_PATH_EXPIRE (600 * HZ)
++
++/* Maximum number of paths per interface */
++#define RTW_MESH_MAX_MPATHS		1024
++
++/* Number of frames buffered per destination for unresolved destinations */
++#define RTW_MESH_FRAME_QUEUE_LEN	10
++
++int rtw_mesh_nexthop_lookup(_adapter *adapter,
++	const u8 *mda, const u8 *msa, u8 *ra);
++int rtw_mesh_nexthop_resolve(_adapter *adapter,
++			 struct xmit_frame *xframe);
++
++struct rtw_mesh_path *rtw_mesh_path_lookup(_adapter *adapter,
++				   const u8 *dst);
++struct rtw_mesh_path *rtw_mpp_path_lookup(_adapter *adapter,
++				  const u8 *dst);
++int rtw_mpp_path_add(_adapter *adapter,
++		 const u8 *dst, const u8 *mpp);
++void dump_mpp(void *sel, _adapter *adapter);
++
++struct rtw_mesh_path *
++rtw_mesh_path_lookup_by_idx(_adapter *adapter, int idx);
++void dump_mpath(void *sel, _adapter *adapter);
++
++struct rtw_mesh_path *
++rtw_mpp_path_lookup_by_idx(_adapter *adapter, int idx);
++void rtw_mesh_path_fix_nexthop(struct rtw_mesh_path *mpath, struct sta_info *next_hop);
++void rtw_mesh_path_expire(_adapter *adapter);
++
++struct rtw_mesh_path *
++rtw_mesh_path_add(_adapter *adapter, const u8 *dst);
++
++int rtw_mesh_path_add_gate(struct rtw_mesh_path *mpath);
++void rtw_mesh_gate_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath);
++bool rtw_mesh_gate_search(struct rtw_mesh_table *tbl, const u8 *addr);
++int rtw_mesh_path_send_to_gates(struct rtw_mesh_path *mpath);
++int rtw_mesh_gate_num(_adapter *adapter);
++bool rtw_mesh_is_primary_gate(_adapter *adapter);
++void dump_known_gates(void *sel, _adapter *adapter);
++
++void rtw_mesh_plink_broken(struct sta_info *sta);
++
++void rtw_mesh_path_assign_nexthop(struct rtw_mesh_path *mpath, struct sta_info *sta);
++void rtw_mesh_path_flush_pending(struct rtw_mesh_path *mpath);
++void rtw_mesh_path_tx_pending(struct rtw_mesh_path *mpath);
++int rtw_mesh_pathtbl_init(_adapter *adapter);
++void rtw_mesh_pathtbl_unregister(_adapter *adapter);
++int rtw_mesh_path_del(_adapter *adapter, const u8 *addr);
++
++void rtw_mesh_path_flush_by_nexthop(struct sta_info *sta);
++void rtw_mesh_path_discard_frame(_adapter *adapter,
++			     struct xmit_frame *xframe);
++
++static inline void rtw_mesh_path_activate(struct rtw_mesh_path *mpath)
++{
++	mpath->flags |= RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVED;
++}
++
++void rtw_mesh_path_flush_by_iface(_adapter *adapter);
++
++#endif /* __RTW_MESH_PATHTBL_H_ */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/monitor/rtw_radiotap.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/monitor/rtw_radiotap.c
+new file mode 100644
+index 000000000..e9ebc7d7a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/monitor/rtw_radiotap.c
+@@ -0,0 +1,615 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_RADIOTAP_C_
++
++#ifdef CONFIG_WIFI_MONITOR
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++#define CHAN2FREQ(a) ((a < 14) ? (2407+5*a) : (5000+5*a))
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0))
++#define IEEE80211_RADIOTAP_ZERO_LEN_PSDU 26
++#define IEEE80211_RADIOTAP_LSIG 27
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0))
++#define IEEE80211_RADIOTAP_TIMESTAMP 22
++/* For IEEE80211_RADIOTAP_TIMESTAMP */
++#define IEEE80211_RADIOTAP_TIMESTAMP_UNIT_MASK			0x000F
++#define IEEE80211_RADIOTAP_TIMESTAMP_UNIT_MS			0x0000
++#define IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US			0x0001
++#define IEEE80211_RADIOTAP_TIMESTAMP_UNIT_NS			0x0003
++#define IEEE80211_RADIOTAP_TIMESTAMP_SPOS_MASK			0x00F0
++#define IEEE80211_RADIOTAP_TIMESTAMP_SPOS_BEGIN_MDPU		0x0000
++#define IEEE80211_RADIOTAP_TIMESTAMP_SPOS_EO_MPDU		0x0010
++#define IEEE80211_RADIOTAP_TIMESTAMP_SPOS_EO_PPDU		0x0020
++#define IEEE80211_RADIOTAP_TIMESTAMP_SPOS_PLCP_SIG_ACQ		0x0030
++#define IEEE80211_RADIOTAP_TIMESTAMP_SPOS_UNKNOWN		0x00F0
++
++#define IEEE80211_RADIOTAP_TIMESTAMP_FLAG_64BIT			0x00
++#define IEEE80211_RADIOTAP_TIMESTAMP_FLAG_32BIT			0x01
++#define IEEE80211_RADIOTAP_TIMESTAMP_FLAG_ACCURACY		0x02
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 12, 0))
++/* for IEEE80211_RADIOTAP_CHANNEL */
++#define	IEEE80211_CHAN_GSM	0x1000	/* GSM (900 MHz) */
++#define	IEEE80211_CHAN_STURBO	0x2000	/* Static Turbo */
++#define	IEEE80211_CHAN_HALF	0x4000	/* Half channel (10 MHz wide) */
++#define	IEEE80211_CHAN_QUARTER	0x8000	/* Quarter channel (5 MHz wide) */
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
++#define IEEE80211_RADIOTAP_VHT 21
++/* For IEEE80211_RADIOTAP_VHT */
++#define IEEE80211_RADIOTAP_VHT_KNOWN_STBC			0x0001
++#define IEEE80211_RADIOTAP_VHT_KNOWN_TXOP_PS_NA			0x0002
++#define IEEE80211_RADIOTAP_VHT_KNOWN_GI				0x0004
++#define IEEE80211_RADIOTAP_VHT_KNOWN_SGI_NSYM_DIS		0x0008
++#define IEEE80211_RADIOTAP_VHT_KNOWN_LDPC_EXTRA_OFDM_SYM	0x0010
++#define IEEE80211_RADIOTAP_VHT_KNOWN_BEAMFORMED			0x0020
++#define IEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH			0x0040
++#define IEEE80211_RADIOTAP_VHT_KNOWN_GROUP_ID			0x0080
++#define IEEE80211_RADIOTAP_VHT_KNOWN_PARTIAL_AID		0x0100
++
++#define IEEE80211_RADIOTAP_VHT_FLAG_STBC			0x01
++#define IEEE80211_RADIOTAP_VHT_FLAG_TXOP_PS_NA			0x02
++#define IEEE80211_RADIOTAP_VHT_FLAG_SGI				0x04
++#define IEEE80211_RADIOTAP_VHT_FLAG_SGI_NSYM_M10_9		0x08
++#define IEEE80211_RADIOTAP_VHT_FLAG_LDPC_EXTRA_OFDM_SYM		0x10
++#define IEEE80211_RADIOTAP_VHT_FLAG_BEAMFORMED			0x20
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0))
++#define IEEE80211_RADIOTAP_CODING_LDPC_USER0			0x01
++#define IEEE80211_RADIOTAP_CODING_LDPC_USER1			0x02
++#define IEEE80211_RADIOTAP_CODING_LDPC_USER2			0x04
++#define IEEE80211_RADIOTAP_CODING_LDPC_USER3			0x08
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0))
++#define IEEE80211_RADIOTAP_AMPDU_STATUS 20
++/* For IEEE80211_RADIOTAP_AMPDU_STATUS */
++#define IEEE80211_RADIOTAP_AMPDU_REPORT_ZEROLEN		0x0001
++#define IEEE80211_RADIOTAP_AMPDU_IS_ZEROLEN		0x0002
++#define IEEE80211_RADIOTAP_AMPDU_LAST_KNOWN		0x0004
++#define IEEE80211_RADIOTAP_AMPDU_IS_LAST		0x0008
++#define IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_ERR		0x0010
++#define IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_KNOWN	0x0020
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0))
++#define IEEE80211_RADIOTAP_AMPDU_EOF			0x0040
++#define IEEE80211_RADIOTAP_AMPDU_EOF_KNOWN		0x0080
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39))
++#define IEEE80211_RADIOTAP_MCS 19
++/* For IEEE80211_RADIOTAP_MCS */
++#define IEEE80211_RADIOTAP_MCS_HAVE_BW		0x01
++#define IEEE80211_RADIOTAP_MCS_HAVE_MCS		0x02
++#define IEEE80211_RADIOTAP_MCS_HAVE_GI		0x04
++#define IEEE80211_RADIOTAP_MCS_HAVE_FMT		0x08
++#define IEEE80211_RADIOTAP_MCS_HAVE_FEC		0x10
++
++#define IEEE80211_RADIOTAP_MCS_BW_MASK		0x03
++#define		IEEE80211_RADIOTAP_MCS_BW_20		0
++#define		IEEE80211_RADIOTAP_MCS_BW_40		1
++#define		IEEE80211_RADIOTAP_MCS_BW_20L		2
++#define		IEEE80211_RADIOTAP_MCS_BW_20U		3
++#define IEEE80211_RADIOTAP_MCS_SGI		0x04
++#define IEEE80211_RADIOTAP_MCS_FMT_GF		0x08
++#define IEEE80211_RADIOTAP_MCS_FEC_LDPC		0x10
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0))
++#define IEEE80211_RADIOTAP_MCS_HAVE_STBC	0x20
++
++#define IEEE80211_RADIOTAP_MCS_STBC_MASK	0x60
++#define		IEEE80211_RADIOTAP_MCS_STBC_1	1
++#define		IEEE80211_RADIOTAP_MCS_STBC_2	2
++#define		IEEE80211_RADIOTAP_MCS_STBC_3	3
++#define IEEE80211_RADIOTAP_MCS_STBC_SHIFT	5
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 34))
++#define IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE 29
++#define IEEE80211_RADIOTAP_VENDOR_NAMESPACE 30
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 30))
++#define IEEE80211_RADIOTAP_F_BADFCS 0x40
++#endif
++
++static inline void _rtw_radiotap_fill_flags(struct rx_pkt_attrib *a, u8 *flags)
++{
++	struct moinfo *moif = (struct moinfo *)&a->moif;
++
++	if (0)
++		*flags |= IEEE80211_RADIOTAP_F_CFP;
++
++	if (0)
++		*flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
++
++	if ((a->encrypt == 1) || (a->encrypt == 5))
++		*flags |= IEEE80211_RADIOTAP_F_WEP;
++
++	if (a->mfrag)
++		*flags |= IEEE80211_RADIOTAP_F_FRAG;
++
++	if (1)
++		*flags |= IEEE80211_RADIOTAP_F_FCS;
++
++	if (0)
++		*flags |= IEEE80211_RADIOTAP_F_DATAPAD;
++
++	if (a->crc_err)
++		*flags |= IEEE80211_RADIOTAP_F_BADFCS;
++
++	/* Currently unspecified but used
++	   for short guard interval (HT) */
++	if (moif->u.snif_info.sgi || a->sgi)
++		*flags |= 0x80;
++
++}
++
++sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf)
++{
++#define RTAP_HDR_MAX 64
++
++	sint ret = _SUCCESS;
++	struct moinfo *moif = (struct moinfo *)&a->moif;
++
++	u8 rx_cnt = 0;
++
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++	int i = 0;
++	u8 tmp_8bit = 0;
++	u16 tmp_16bit = 0;
++	u32 tmp_32bit = 0;
++	u64 tmp_64bit = 0;
++
++	_pkt *pskb = NULL;
++
++	struct ieee80211_radiotap_header *rtap_hdr = NULL;
++	u8 *ptr = NULL;
++
++	/* 
++	  radiotap length (include header 8)
++	  11G length: 36 (0x0040002f)
++	  11N length:
++	  11AC length: 60 (0x0070002b)
++	 */
++	u8 hdr_buf[RTAP_HDR_MAX] = { 0 };
++	u16 rt_len = 8;
++
++	/* create header */
++	rtap_hdr = (struct ieee80211_radiotap_header *)&hdr_buf[0];
++	rtap_hdr->it_version = PKTHDR_RADIOTAP_VERSION;
++
++	/* each antenna information */
++	rx_cnt = rf_type_to_rf_rx_cnt(pHalData->rf_type);
++#if 0
++	if (rx_cnt > 1) {
++		rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE) |
++		BIT(IEEE80211_RADIOTAP_EXT);
++
++		for (i = 1; i < rx_cnt; i++) {
++			tmp_32bit = (BIT(IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
++				     BIT(IEEE80211_RADIOTAP_LOCK_QUALITY) |
++				     BIT(IEEE80211_RADIOTAP_ANTENNA) |
++				     BIT(IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE) |
++				     BIT(IEEE80211_RADIOTAP_EXT));
++			_rtw_memcpy(&hdr_buf[rt_len], &tmp_32bit, 4);
++			rt_len += 4;
++		}
++
++		tmp_32bit = (BIT(IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
++			     BIT(IEEE80211_RADIOTAP_LOCK_QUALITY) |
++			     BIT(IEEE80211_RADIOTAP_ANTENNA));
++		_rtw_memcpy(&hdr_buf[rt_len], &tmp_32bit, 4);
++		rt_len += 4;
++	}
++#endif
++
++	/* tsft, Required Alignment: 8 bytes */
++	if (0) { //(a->free_cnt) {
++		/* TSFT + free_cnt */
++		rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_TSFT);
++		if (!IS_ALIGNED(rt_len, 8))
++			rt_len = ((rt_len + 7) & 0xFFF8); /* Alignment */
++
++		tmp_64bit = cpu_to_le64(a->free_cnt);
++		_rtw_memcpy(&hdr_buf[rt_len], &tmp_64bit, 8);
++		rt_len += 8;
++	}
++
++	/* flags */
++	rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_FLAGS);
++	_rtw_radiotap_fill_flags(a, &hdr_buf[rt_len]);
++	rt_len += 1;
++
++	/* rate */
++	if (a->data_rate <= DESC_RATE54M) {
++		rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_RATE);
++		hdr_buf[rt_len] = hw_rate_to_m_rate(a->data_rate);
++		rt_len += 1;
++	}
++
++	/* channel & flags, Required Alignment: 2 bytes */
++	if (1) {
++		rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_CHANNEL);
++		rt_len += (rt_len % 2); /* Alignment */
++
++		tmp_16bit = CHAN2FREQ(rtw_get_oper_ch(padapter));
++		_rtw_memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
++		rt_len += 2;
++
++		/* channel flags */
++		tmp_16bit = 0;
++		if (pHalData->current_band_type == 0)
++			tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_2GHZ);
++		else
++			tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_5GHZ);
++
++		if (a->data_rate <= DESC_RATE11M) {
++			/* CCK */
++			tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_CCK);
++		} else {
++			/* OFDM */
++			tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_OFDM);
++		}
++
++		if (rtw_get_oper_bw(padapter) == CHANNEL_WIDTH_10) {
++			/* 10Mhz Channel Width */
++			tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_HALF);
++		}
++
++		if (rtw_get_oper_bw(padapter) == CHANNEL_WIDTH_5) {
++			/* 5Mhz Channel Width */
++			tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_QUARTER);
++		}
++		_rtw_memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
++		rt_len += 2;
++	}
++
++	/* dBm Antenna Signal */
++	rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_DBM_ANTSIGNAL);
++	hdr_buf[rt_len] = a->phy_info.recv_signal_power;
++	rt_len += 1;
++
++#if 0
++	/* dBm Antenna Noise */
++	rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_DBM_ANTNOISE);
++	hdr_buf[rt_len] = 0;
++	rt_len += 1;
++#endif
++#if 0
++	/* Signal Quality, Required Alignment: 2 bytes */
++	rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_LOCK_QUALITY);
++	if (!IS_ALIGNED(rt_len, 2))
++	rt_len++;
++	hdr_buf[rt_len] = a->phy_info.signal_quality;
++	rt_len += 2;
++
++#endif
++
++#if 0
++	/* Antenna */
++	rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_ANTENNA);
++	hdr_buf[rt_len] = 0; /* pHalData->rf_type; */
++	rt_len += 1;
++#endif
++#if 0
++	/* RX flags, Required Alignment: 2 bytes */
++	rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_RX_FLAGS);
++	tmp_16bit = 0;
++	_rtw_memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
++	rt_len += 2;
++#endif
++
++	/* MCS information, Required Alignment: 1 bytes */
++	if (a->data_rate >= DESC_RATEMCS0 && a->data_rate <= DESC_RATEMCS31) {
++		rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_MCS);
++		/* Structure u8 known, u8 flags, u8 mcs */
++
++		/* known.bandwidth */
++		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_MCS_HAVE_BW;
++		if (moif->u.snif_info.ofdm_bw)
++			hdr_buf[rt_len + 1] |= IEEE80211_RADIOTAP_MCS_BW_40;
++		if (a->bw == CHANNEL_WIDTH_40)
++			hdr_buf[rt_len + 1] |= IEEE80211_RADIOTAP_MCS_BW_40;
++		else
++			hdr_buf[rt_len + 1] |= IEEE80211_RADIOTAP_MCS_BW_20;
++
++
++		/* known.guard interval */
++		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_MCS_HAVE_GI;
++		if (moif->u.snif_info.sgi) {
++			hdr_buf[rt_len + 1] |= IEEE80211_RADIOTAP_MCS_SGI;
++		} else {
++			hdr_buf[rt_len + 1] |= ((a->sgi & 0x01) << 2);
++		}
++
++		/* FEC Type */
++		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_MCS_HAVE_FEC;
++		if (moif->u.snif_info.ldpc) {
++			hdr_buf[rt_len + 1] |= ((moif->u.snif_info.ldpc & 0x01) << 4);
++		} else {
++			hdr_buf[rt_len + 1] |= ((a->ldpc & 0x01) << 4);
++		}
++
++		/* STBC */
++		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_MCS_HAVE_STBC;
++		if (moif->u.snif_info.stbc) {
++			hdr_buf[rt_len + 1] |= ((moif->u.snif_info.stbc & 0x03) << 5);
++		} else {
++			hdr_buf[rt_len + 1] |= ((a->stbc & 0x03) << 5);
++		}
++
++		/* known.MCS index */
++		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_MCS_HAVE_MCS;
++
++		/* u8 mcs */
++		hdr_buf[rt_len + 2] = a->data_rate - DESC_RATEMCS0;
++
++		rt_len += 3;
++	}
++
++	/* AMPDU, Required Alignment: 4 bytes */
++	if (a->ampdu) {
++		static u32 ref_num = 0x10000000;
++		static u8 ppdu_cnt = 0;
++
++		/* Structure u32 reference number, u16 flags, u8 delimiter CRC value, u8 reserved */
++		rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_AMPDU_STATUS);
++		if (!IS_ALIGNED(rt_len, 4))
++			rt_len = ((rt_len + 3) & 0xFFFC); /* Alignment */
++
++		/* u32 reference number */
++		if (a->ppdu_cnt != ppdu_cnt) {
++			ppdu_cnt = a->ppdu_cnt;
++			ref_num += 1;
++		}
++		tmp_32bit = cpu_to_le32(ref_num);
++		_rtw_memcpy(&hdr_buf[rt_len], &tmp_32bit, 4);
++		rt_len += 4;
++
++		/* u16 flags */
++		tmp_16bit = 0;
++		if (0) {
++			tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_REPORT_ZEROLEN);
++			tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_IS_ZEROLEN);
++		}
++
++		if (0) {
++			tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_IS_LAST);
++			tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_LAST_KNOWN);
++		}
++
++		if (0) {
++			tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_ERR);
++			tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_KNOWN);
++		}
++
++		if (a->ampdu_eof) {
++			tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_EOF_KNOWN);
++			tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_EOF);
++		}
++
++		_rtw_memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
++		rt_len += 2;
++
++		/* u8 delimiter CRC value, u8 reserved */
++		rt_len += 2;
++	}
++
++	/* VHT, Required Alignment: 2 bytes */
++	if (a->data_rate >= DESC_RATEVHTSS1MCS0 && a->data_rate <= DESC_RATEVHTSS4MCS9) {
++		rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_VHT);
++
++		rt_len += (rt_len % 2); /* Alignment */
++
++		/* Structure
++		   u16 known, u8 flags, u8 bandwidth, u8 mcs_nss[4],
++		   u8 coding, u8 group_id, u16 partial_aid */
++
++		tmp_16bit = 0;
++
++		/* STBC */
++		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_STBC);
++		if (moif->u.snif_info.stbc) {
++			hdr_buf[rt_len + 2] |= IEEE80211_RADIOTAP_VHT_FLAG_STBC;
++		} else {
++			hdr_buf[rt_len + 2] |= (a->stbc & 0x01);
++		}
++
++		/* TXOP_PS_NOT_ALLOWED */
++		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_TXOP_PS_NA);
++		if (moif->u.snif_info.vht_txop_not_allow) {
++			hdr_buf[rt_len + 2] |= IEEE80211_RADIOTAP_VHT_FLAG_TXOP_PS_NA;
++		}
++
++
++		/* Guard interval */
++		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_GI);
++		if (moif->u.snif_info.sgi) {
++			hdr_buf[rt_len + 2] |= IEEE80211_RADIOTAP_VHT_FLAG_SGI;
++		} else {
++			hdr_buf[rt_len + 2] |= ((a->sgi & 0x01) << 2);
++		}
++
++		/* Short GI NSYM */
++		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_SGI_NSYM_DIS);
++		if (moif->u.snif_info.vht_nsym_dis) {
++			hdr_buf[rt_len + 2] |= IEEE80211_RADIOTAP_VHT_FLAG_SGI_NSYM_M10_9;
++		}
++
++		/* LDPC extra OFDM symbol */
++		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_LDPC_EXTRA_OFDM_SYM);
++		if (moif->u.snif_info.vht_ldpc_extra) {
++			hdr_buf[rt_len + 2] |= IEEE80211_RADIOTAP_VHT_FLAG_LDPC_EXTRA_OFDM_SYM;
++		} else {
++			hdr_buf[rt_len + 2] |= ((a->ldpc & 0x01) << 4);
++		}
++
++		/* Short GI NSYM */
++		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_BEAMFORMED);
++		if (moif->u.snif_info.vht_beamformed) {
++			hdr_buf[rt_len + 2] |= IEEE80211_RADIOTAP_VHT_FLAG_BEAMFORMED;
++		}
++
++		/* know.Bandwidth */
++		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH);
++
++		/* Group ID */
++		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_GROUP_ID);
++
++		/* Partial AID */
++		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_PARTIAL_AID);
++
++		_rtw_memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
++		rt_len += 3;
++
++		/* u8 bandwidth */
++		if (moif->u.snif_info.ofdm_bw)
++			tmp_8bit = moif->u.snif_info.ofdm_bw;
++		else
++			tmp_8bit = a->bw;
++
++		switch (tmp_8bit) {
++		case CHANNEL_WIDTH_20:
++			hdr_buf[rt_len] |= 0;
++			break;
++		case CHANNEL_WIDTH_40:
++			hdr_buf[rt_len] |= 1;
++			break;
++		case CHANNEL_WIDTH_80:
++			hdr_buf[rt_len] |= 4;
++			break;
++		case CHANNEL_WIDTH_160:
++			hdr_buf[rt_len] |= 11;
++			break;
++		default:
++			hdr_buf[rt_len] |= 0;
++		}
++		rt_len += 1;
++
++		/* u8 mcs_nss[4] */
++		if ((DESC_RATEVHTSS1MCS0 <= a->data_rate) &&
++			(a->data_rate <= DESC_RATEVHTSS4MCS9)) {
++			/* User 0 */
++			/* MCS */
++			hdr_buf[rt_len] = ((a->data_rate - DESC_RATEVHTSS1MCS0) % 10) << 4;
++			/* NSS */
++			hdr_buf[rt_len] |= (((a->data_rate - DESC_RATEVHTSS1MCS0) / 10) + 1);
++		}
++		rt_len += 4;
++
++		/* u8 coding, phystat? */
++		hdr_buf[rt_len] = 0;
++		rt_len += 1;
++
++		/* u8 group_id */
++		hdr_buf[rt_len] = moif->u.snif_info.vht_group_id;
++		rt_len += 1;
++
++		/* u16 partial_aid */
++		tmp_16bit = cpu_to_le16(moif->u.snif_info.vht_nsts_aid);
++		_rtw_memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
++		rt_len += 2;
++	}
++
++	/* frame timestamp, Required Alignment: 8 bytes */
++	if (0) { //(a->free_cnt) {
++		rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_TIMESTAMP);
++		if (!IS_ALIGNED(rt_len, 8))
++			rt_len = ((rt_len + 7) & 0xFFF8); /* Alignment */
++
++		/* u64 timestamp */
++		tmp_64bit = cpu_to_le64(a->free_cnt);
++		_rtw_memcpy(&hdr_buf[rt_len], &tmp_64bit, 8);
++		rt_len += 8;
++
++		/* u16 accuracy */
++		tmp_16bit = cpu_to_le16(22);
++		_rtw_memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
++		rt_len += 2;
++
++		/* u8 unit/position */
++		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US;
++		rt_len += 1;
++
++		/* u8 flags */
++		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_TIMESTAMP_FLAG_32BIT;
++		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_TIMESTAMP_FLAG_ACCURACY;
++		rt_len += 1;
++	}
++
++	/* each antenna information */
++#if 0
++	if (rx_cnt > 1) {
++		for (i = 0; i <= rx_cnt; i++) {
++			/* dBm Antenna Signal */
++			hdr_buf[rt_len] = a->phy_info.rx_mimo_signal_strength[i];
++			rt_len += 1;
++
++			/* Signal Quality */
++			if (!IS_ALIGNED(rt_len, 2))
++				rt_len++;
++			hdr_buf[rt_len] = cpu_to_le16(a->phy_info.rx_mimo_signal_quality[i]);
++			rt_len += 2;
++
++			/* Antenna */
++			hdr_buf[rt_len] = i; /* pHalData->rf_type; */
++			rt_len += 1;
++		}
++	}
++#endif
++
++	/* push to skb */
++	pskb = (_pkt *)buf;
++	if (skb_headroom(pskb) < rt_len) {
++		RTW_INFO("%s:%d %s headroom is too small.\n", __FILE__, __LINE__, __func__);
++		ret = _FAIL;
++		return ret;
++	}
++
++	ptr = skb_push(pskb, rt_len);
++	if (ptr) {
++		rtap_hdr->it_len = cpu_to_le16(rt_len);
++		rtap_hdr->it_present = cpu_to_le32(rtap_hdr->it_present);
++		memcpy(ptr, rtap_hdr, rt_len);
++	} else
++		ret = _FAIL;
++
++	return ret;
++
++}
++
++void rx_query_moinfo(struct rx_pkt_attrib *a, u8 *desc)
++{
++	switch (a->drvinfo_sz) {
++	case 40:
++		_rtw_memcpy(a->moif, &desc[32], 8);
++		break;
++	case 48:
++		_rtw_memcpy(a->moif, &desc[32], 12);
++		break;
++	case 32:
++		/* passthrough */
++	default:
++		break;
++	}
++}
++
++#endif /* CONFIG_WIFI_MONITOR */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/monitor/rtw_radiotap.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/monitor/rtw_radiotap.h
+new file mode 100644
+index 000000000..affacd185
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/monitor/rtw_radiotap.h
+@@ -0,0 +1,63 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_RADIOTAP_H_
++#define __RTW_RADIOTAP_H_
++
++struct mon_reg_backup {
++	/* flags */
++	u8	known_rcr:1;
++	u8	known_drvinfo:1;
++	u8	known_rxfilter:1;
++	u8	known_misc0:1;
++	/* data */
++	u8	drvinfo;
++	u16	rxfilter0;
++	u16	rxfilter1;
++	u16	rxfilter2;
++	u32	rcr;
++	u32	misc0;
++};
++
++struct moinfo {
++	union {
++		struct  {
++			u32	sgi:1;
++			u32	ldpc:1;
++			u32	stbc:2;
++			u32	not_sounding:1;
++			u32	ofdm_bw:2;
++			u32	vht_group_id:2;
++			u32	vht_nsts_aid:12;
++			u32	vht_txop_not_allow:1;
++			u32	vht_nsym_dis:1;
++			u32	vht_ldpc_extra:1;
++			u32	vht_su_mcs:12;
++			u32	vht_beamformed:1;
++		}snif_info;
++
++		struct  {
++			u32	A;
++			u32	B;
++			u32	C;
++		}plcp_info;
++	}u;
++};
++
++sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf);
++
++void rx_query_moinfo(struct rx_pkt_attrib *a, u8 *desc);
++
++#endif /* __RTW_RADIOTAP_H_ */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_ap.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_ap.c
+new file mode 100755
+index 000000000..411e94042
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_ap.c
+@@ -0,0 +1,5941 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_AP_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++#ifdef CONFIG_AP_MODE
++
++extern unsigned char	RTW_WPA_OUI[];
++extern unsigned char	WMM_OUI[];
++extern unsigned char	WPS_OUI[];
++extern unsigned char	P2P_OUI[];
++extern unsigned char	WFD_OUI[];
++
++void init_mlme_ap_info(_adapter *padapter)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++	_rtw_spinlock_init(&pmlmepriv->bcn_update_lock);
++	/* pmlmeext->bstart_bss = _FALSE; */
++}
++
++void free_mlme_ap_info(_adapter *padapter)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++	stop_ap_mode(padapter);
++	_rtw_spinlock_free(&pmlmepriv->bcn_update_lock);
++
++}
++
++/*
++* Set TIM IE
++* return length of total TIM IE
++*/
++u8 rtw_set_tim_ie(u8 dtim_cnt, u8 dtim_period
++	, const u8 *tim_bmp, u8 tim_bmp_len, u8 *tim_ie)
++{
++	u8 *p = tim_ie;
++	u8 i, n1, n2;
++	u8 bmp_len;
++
++	if (rtw_bmp_not_empty(tim_bmp, tim_bmp_len)) {
++		/* find the first nonzero octet in tim_bitmap */
++		for (i = 0; i < tim_bmp_len; i++)
++			if (tim_bmp[i])
++				break;
++		n1 = i & 0xFE;
++	
++		/* find the last nonzero octet in tim_bitmap, except octet 0 */
++		for (i = tim_bmp_len - 1; i > 0; i--)
++			if (tim_bmp[i])
++				break;
++		n2 = i;
++		bmp_len = n2 - n1 + 1;
++	} else {
++		n1 = n2 = 0;
++		bmp_len = 1;
++	}
++
++	*p++ = WLAN_EID_TIM;
++	*p++ = 2 + 1 + bmp_len;
++	*p++ = dtim_cnt;
++	*p++ = dtim_period;
++	*p++ = (rtw_bmp_is_set(tim_bmp, tim_bmp_len, 0) ? BIT0 : 0) | n1;
++	_rtw_memcpy(p, tim_bmp + n1, bmp_len);
++
++#if 0
++	RTW_INFO("n1:%u, n2:%u, bmp_offset:%u, bmp_len:%u\n", n1, n2, n1 / 2, bmp_len);
++	RTW_INFO_DUMP("tim_ie: ", tim_ie + 2, 2 + 1 + bmp_len);
++#endif
++	return 2 + 2 + 1 + bmp_len;
++}
++
++static void update_BCNTIM(_adapter *padapter)
++{
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network);
++	unsigned char *pie = pnetwork_mlmeext->IEs;
++
++#if 0
++
++
++	/* update TIM IE */
++	/* if(rtw_tim_map_anyone_be_set(padapter, pstapriv->tim_bitmap)) */
++#endif
++	if (_TRUE) {
++		u8 *p, *dst_ie, *premainder_ie = NULL, *pbackup_remainder_ie = NULL;
++		uint offset, tmp_len, tim_ielen, tim_ie_offset, remainder_ielen;
++
++		p = rtw_get_ie(pie + _FIXED_IE_LENGTH_, _TIM_IE_, &tim_ielen, pnetwork_mlmeext->IELength - _FIXED_IE_LENGTH_);
++		if (p != NULL && tim_ielen > 0) {
++			tim_ielen += 2;
++
++			premainder_ie = p + tim_ielen;
++
++			tim_ie_offset = (sint)(p - pie);
++
++			remainder_ielen = pnetwork_mlmeext->IELength - tim_ie_offset - tim_ielen;
++
++			/*append TIM IE from dst_ie offset*/
++			dst_ie = p;
++		} else {
++			tim_ielen = 0;
++
++			/*calculate head_len*/
++			offset = _FIXED_IE_LENGTH_;
++
++			/* get ssid_ie len */
++			p = rtw_get_ie(pie + _BEACON_IE_OFFSET_, _SSID_IE_, &tmp_len, (pnetwork_mlmeext->IELength - _BEACON_IE_OFFSET_));
++			if (p != NULL)
++				offset += tmp_len + 2;
++
++			/*get supported rates len*/
++			p = rtw_get_ie(pie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &tmp_len, (pnetwork_mlmeext->IELength - _BEACON_IE_OFFSET_));
++			if (p !=  NULL)
++				offset += tmp_len + 2;
++
++			/*DS Parameter Set IE, len=3*/
++			offset += 3;
++
++			premainder_ie = pie + offset;
++
++			remainder_ielen = pnetwork_mlmeext->IELength - offset - tim_ielen;
++
++			/*append TIM IE from offset*/
++			dst_ie = pie + offset;
++
++		}
++
++		if (remainder_ielen > 0) {
++			pbackup_remainder_ie = rtw_malloc(remainder_ielen);
++			if (pbackup_remainder_ie && premainder_ie)
++				_rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);
++		}
++
++		/* append TIM IE */
++		dst_ie += rtw_set_tim_ie(0, 1, pstapriv->tim_bitmap, pstapriv->aid_bmp_len, dst_ie);
++
++		/*copy remainder IE*/
++		if (pbackup_remainder_ie) {
++			_rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen);
++
++			rtw_mfree(pbackup_remainder_ie, remainder_ielen);
++		}
++
++		offset = (uint)(dst_ie - pie);
++		pnetwork_mlmeext->IELength = offset + remainder_ielen;
++
++	}
++}
++
++void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len)
++{
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++	u8	bmatch = _FALSE;
++	u8	*pie = pnetwork->IEs;
++	u8	*p = NULL, *dst_ie = NULL, *premainder_ie = NULL, *pbackup_remainder_ie = NULL;
++	u32	i, offset, ielen, ie_offset, remainder_ielen = 0;
++
++	for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pnetwork->IELength;) {
++		pIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i);
++
++		if (pIE->ElementID > index)
++			break;
++		else if (pIE->ElementID == index) { /* already exist the same IE */
++			p = (u8 *)pIE;
++			ielen = pIE->Length;
++			bmatch = _TRUE;
++			break;
++		}
++
++		p = (u8 *)pIE;
++		ielen = pIE->Length;
++		i += (pIE->Length + 2);
++	}
++
++	if (p != NULL && ielen > 0) {
++		ielen += 2;
++
++		premainder_ie = p + ielen;
++
++		ie_offset = (sint)(p - pie);
++
++		remainder_ielen = pnetwork->IELength - ie_offset - ielen;
++
++		if (bmatch)
++			dst_ie = p;
++		else
++			dst_ie = (p + ielen);
++	}
++
++	if (dst_ie == NULL)
++		return;
++
++	if (remainder_ielen > 0) {
++		pbackup_remainder_ie = rtw_malloc(remainder_ielen);
++		if (pbackup_remainder_ie && premainder_ie)
++			_rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);
++	}
++
++	*dst_ie++ = index;
++	*dst_ie++ = len;
++
++	_rtw_memcpy(dst_ie, data, len);
++	dst_ie += len;
++
++	/* copy remainder IE */
++	if (pbackup_remainder_ie) {
++		_rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen);
++
++		rtw_mfree(pbackup_remainder_ie, remainder_ielen);
++	}
++
++	offset = (uint)(dst_ie - pie);
++	pnetwork->IELength = offset + remainder_ielen;
++}
++
++void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index)
++{
++	u8 *p, *dst_ie = NULL, *premainder_ie = NULL, *pbackup_remainder_ie = NULL;
++	uint offset, ielen, ie_offset, remainder_ielen = 0;
++	u8	*pie = pnetwork->IEs;
++
++	p = rtw_get_ie(pie + _FIXED_IE_LENGTH_, index, &ielen, pnetwork->IELength - _FIXED_IE_LENGTH_);
++	if (p != NULL && ielen > 0) {
++		ielen += 2;
++
++		premainder_ie = p + ielen;
++
++		ie_offset = (sint)(p - pie);
++
++		remainder_ielen = pnetwork->IELength - ie_offset - ielen;
++
++		dst_ie = p;
++	} else
++		return;
++
++	if (remainder_ielen > 0) {
++		pbackup_remainder_ie = rtw_malloc(remainder_ielen);
++		if (pbackup_remainder_ie && premainder_ie)
++			_rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);
++	}
++
++	/* copy remainder IE */
++	if (pbackup_remainder_ie) {
++		_rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen);
++
++		rtw_mfree(pbackup_remainder_ie, remainder_ielen);
++	}
++
++	offset = (uint)(dst_ie - pie);
++	pnetwork->IELength = offset + remainder_ielen;
++}
++
++
++u8 chk_sta_is_alive(struct sta_info *psta);
++u8 chk_sta_is_alive(struct sta_info *psta)
++{
++	u8 ret = _FALSE;
++#ifdef DBG_EXPIRATION_CHK
++	RTW_INFO("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", expire_to:%u, %s%ssq_len:%u\n"
++		 , MAC_ARG(psta->cmn.mac_addr)
++		 , psta->cmn.rssi_stat.rssi
++		 /* , STA_RX_PKTS_ARG(psta) */
++		 , STA_RX_PKTS_DIFF_ARG(psta)
++		 , psta->expire_to
++		 , psta->state & WIFI_SLEEP_STATE ? "PS, " : ""
++		 , psta->state & WIFI_STA_ALIVE_CHK_STATE ? "SAC, " : ""
++		 , psta->sleepq_len
++		);
++#endif
++
++	/* if(sta_last_rx_pkts(psta) == sta_rx_pkts(psta)) */
++	if ((psta->sta_stats.last_rx_data_pkts + psta->sta_stats.last_rx_ctrl_pkts) == (psta->sta_stats.rx_data_pkts + psta->sta_stats.rx_ctrl_pkts)) {
++#if 0
++		if (psta->state & WIFI_SLEEP_STATE)
++			ret = _TRUE;
++#endif
++	} else
++		ret = _TRUE;
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(psta->padapter)) {
++		u8 bcn_alive, hwmp_alive;
++
++		hwmp_alive = (psta->sta_stats.rx_hwmp_pkts !=
++			      psta->sta_stats.last_rx_hwmp_pkts);
++		bcn_alive = (psta->sta_stats.rx_beacon_pkts != 
++			     psta->sta_stats.last_rx_beacon_pkts);
++		/* The reference for nexthop_lookup */
++		psta->alive = ret || hwmp_alive || bcn_alive;
++		/* The reference for expire_timeout_chk */
++		/* Exclude bcn_alive to avoid a misjudge condition
++		   that a peer unexpectedly leave and restart quickly*/
++		ret = ret || hwmp_alive;
++	}
++#endif
++
++	sta_update_last_rx_pkts(psta);
++
++	return ret;
++}
++
++/**
++ * issue_aka_chk_frame - issue active keep alive check frame
++ *	aka = active keep alive
++ */
++#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++static int issue_aka_chk_frame(_adapter *adapter, struct sta_info *psta)
++{
++	int ret = _FAIL;
++	u8 *target_addr = psta->cmn.mac_addr;
++
++	if (MLME_IS_AP(adapter)) {
++		/* issue null data to check sta alive */
++		if (psta->state & WIFI_SLEEP_STATE)
++			ret = issue_nulldata(adapter, target_addr, 0, 1, 50);
++		else
++			ret = issue_nulldata(adapter, target_addr, 0, 3, 50);
++	}
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(adapter)) {
++		struct rtw_mesh_path *mpath;
++
++		rtw_rcu_read_lock();
++		mpath = rtw_mesh_path_lookup(adapter, target_addr);
++		if (!mpath) {
++			mpath = rtw_mesh_path_add(adapter, target_addr);
++			if (IS_ERR(mpath)) {
++				rtw_rcu_read_unlock();
++				RTW_ERR(FUNC_ADPT_FMT" rtw_mesh_path_add for "MAC_FMT" fail.\n",
++					FUNC_ADPT_ARG(adapter), MAC_ARG(target_addr));
++				return _FAIL;
++			}
++		}
++		if (mpath->flags & RTW_MESH_PATH_ACTIVE)
++			ret = _SUCCESS;
++		else {
++			u8 flags = RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_PEER_AKA;
++			/* issue PREQ to check peer alive */
++			rtw_mesh_queue_preq(mpath, flags);
++			ret = _FALSE;
++		}
++		rtw_rcu_read_unlock();
++	}
++#endif
++	return ret;
++}
++#endif
++
++#ifdef RTW_CONFIG_RFREG18_WA
++static void rtw_check_restore_rf18(_adapter *padapter)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++	u32 reg;
++	u8 union_ch = 0, union_bw = 0, union_offset = 0, setchbw = _FALSE;
++		
++	reg = rtw_hal_read_rfreg(padapter, 0, 0x18, 0x3FF);
++	if ((reg & 0xFF) == 0)
++			setchbw = _TRUE;
++	reg = rtw_hal_read_rfreg(padapter, 1, 0x18, 0x3FF);
++	if ((reg & 0xFF) == 0)
++			setchbw = _TRUE;
++
++	if (setchbw) {
++		if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset)) {
++			RTW_INFO("Hit RF(0x18)=0!! restore original channel setting.\n");
++			union_ch =  pmlmeext->cur_channel;
++			union_offset = pmlmeext->cur_ch_offset ;
++			union_bw = pmlmeext->cur_bwmode;
++		} else {
++			RTW_INFO("Hit RF(0x18)=0!! set ch(%x) offset(%x) bwmode(%x)\n", union_ch, union_offset, union_bw);
++		}
++		/*	Initial the channel_bw setting procedure.	*/
++		pHalData->current_channel = 0;
++		set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
++	}
++}
++#endif
++
++void	expire_timeout_chk(_adapter *padapter)
++{
++	_irqL irqL;
++	_list	*phead, *plist;
++	u8 updated = _FALSE;
++	struct sta_info *psta = NULL;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	u8 chk_alive_num = 0;
++	char chk_alive_list[NUM_STA];
++	int i;
++	int stainfo_offset;
++	u8 flush_num = 0;
++	char flush_list[NUM_STA]={0};
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(padapter)
++		&& check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)
++	) {
++		struct rtw_mesh_cfg *mcfg = &padapter->mesh_cfg;
++
++		rtw_mesh_path_expire(padapter);
++
++		/* TBD: up layer timeout mechanism */
++		/* if (!mcfg->plink_timeout)
++			return; */
++#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++		return;
++#endif
++	}
++#endif
++
++#ifdef CONFIG_RTW_WDS
++	rtw_wds_path_expire(padapter);
++#endif
++
++#ifdef CONFIG_MCC_MODE
++	/*	then driver may check fail due to not recv client's frame under sitesurvey,
++	 *	don't expire timeout chk under MCC under sitesurvey */
++
++	if (rtw_hal_mcc_link_status_chk(padapter, __func__) == _FALSE)
++		return;
++#endif
++
++	_enter_critical_bh(&pstapriv->auth_list_lock, &irqL);
++
++	phead = &pstapriv->auth_list;
++	plist = get_next(phead);
++
++	/* check auth_queue */
++#ifdef DBG_EXPIRATION_CHK
++	if (rtw_end_of_queue_search(phead, plist) == _FALSE) {
++		RTW_INFO(FUNC_ADPT_FMT" auth_list, cnt:%u\n"
++			, FUNC_ADPT_ARG(padapter), pstapriv->auth_list_cnt);
++	}
++#endif
++	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++		psta = LIST_CONTAINOR(plist, struct sta_info, auth_list);
++
++		plist = get_next(plist);
++
++
++#ifdef CONFIG_ATMEL_RC_PATCH
++		if (_rtw_memcmp((void *)(pstapriv->atmel_rc_pattern), (void *)(psta->cmn.mac_addr), ETH_ALEN) == _TRUE)
++			continue;
++		if (psta->flag_atmel_rc)
++			continue;
++#endif
++		if (psta->expire_to > 0) {
++			psta->expire_to--;
++			if (psta->expire_to == 0) {
++				stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
++				if (stainfo_offset_valid(stainfo_offset))
++					flush_list[flush_num++] = stainfo_offset;
++				else
++					rtw_warn_on(1);
++			}
++		}
++
++	}
++
++	_exit_critical_bh(&pstapriv->auth_list_lock, &irqL);
++	for (i = 0; i < flush_num; i++) {
++		psta = rtw_get_stainfo_by_offset(pstapriv, flush_list[i]);
++		RTW_INFO(FUNC_ADPT_FMT" auth expire "MAC_FMT"\n"
++			, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
++		rtw_free_stainfo(padapter, psta);
++		psta = NULL;
++	}
++
++	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++	phead = &pstapriv->asoc_list;
++	plist = get_next(phead);
++
++	/* check asoc_queue */
++#ifdef DBG_EXPIRATION_CHK
++	if (rtw_end_of_queue_search(phead, plist) == _FALSE) {
++		RTW_INFO(FUNC_ADPT_FMT" asoc_list, cnt:%u\n"
++			, FUNC_ADPT_ARG(padapter), pstapriv->asoc_list_cnt);
++	}
++#endif
++	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++		plist = get_next(plist);
++#ifdef CONFIG_ATMEL_RC_PATCH
++		RTW_INFO("%s:%d  psta=%p, %02x,%02x||%02x,%02x  \n\n", __func__,  __LINE__,
++			psta, pstapriv->atmel_rc_pattern[0], pstapriv->atmel_rc_pattern[5], psta->cmn.mac_addr[0], psta->cmn.mac_addr[5]);
++		if (_rtw_memcmp((void *)pstapriv->atmel_rc_pattern, (void *)(psta->cmn.mac_addr), ETH_ALEN) == _TRUE)
++			continue;
++		if (psta->flag_atmel_rc)
++			continue;
++		RTW_INFO("%s: debug line:%d\n", __func__, __LINE__);
++#endif
++#ifdef CONFIG_AUTO_AP_MODE
++		if (psta->isrc)
++			continue;
++#endif
++		if (chk_sta_is_alive(psta) || !psta->expire_to) {
++			psta->expire_to = pstapriv->expire_to;
++			psta->keep_alive_trycnt = 0;
++			#if !defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && defined(CONFIG_80211N_HT)
++			psta->under_exist_checking = 0;
++			#endif
++		} else
++			psta->expire_to--;
++
++#if !defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && defined(CONFIG_80211N_HT)
++		if ((psta->flags & WLAN_STA_HT) && (psta->htpriv.agg_enable_bitmap || psta->under_exist_checking)) {
++			/* check sta by delba(addba) for 11n STA */
++			/* ToDo: use CCX report to check for all STAs */
++			/* RTW_INFO("asoc check by DELBA/ADDBA! (pstapriv->expire_to=%d s)(psta->expire_to=%d s), [%02x, %d]\n", pstapriv->expire_to*2, psta->expire_to*2, psta->htpriv.agg_enable_bitmap, psta->under_exist_checking); */
++			if (psta->expire_to <= (pstapriv->expire_to - 50)) {
++				RTW_INFO("asoc expire by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to - psta->expire_to) * 2);
++				psta->under_exist_checking = 0;
++				psta->expire_to = 0;
++			} else if (psta->expire_to <= (pstapriv->expire_to - 3) && (psta->under_exist_checking == 0)) {
++				RTW_INFO("asoc check by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to - psta->expire_to) * 2);
++				psta->under_exist_checking = 1;
++				/* tear down TX AMPDU */
++				send_delba(padapter, 1, psta->cmn.mac_addr);/*  */ /* originator */
++				psta->htpriv.agg_enable_bitmap = 0x0;/* reset */
++				psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */
++			}
++		}
++#endif /* !defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && defined(CONFIG_80211N_HT) */
++
++		if (psta->expire_to <= 0) {
++			struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++			if (padapter->registrypriv.wifi_spec == 1) {
++				psta->expire_to = pstapriv->expire_to;
++				continue;
++			}
++
++#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++#ifdef CONFIG_80211N_HT
++
++#define KEEP_ALIVE_TRYCNT (3)
++
++			if (psta->keep_alive_trycnt > 0 && psta->keep_alive_trycnt <= KEEP_ALIVE_TRYCNT) {
++				if (psta->state & WIFI_STA_ALIVE_CHK_STATE)
++					psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
++				else
++					psta->keep_alive_trycnt = 0;
++
++			} else if ((psta->keep_alive_trycnt > KEEP_ALIVE_TRYCNT) && !(psta->state & WIFI_STA_ALIVE_CHK_STATE))
++				psta->keep_alive_trycnt = 0;
++			if ((psta->htpriv.ht_option == _TRUE) && (psta->htpriv.ampdu_enable == _TRUE)) {
++				uint priority = 1; /* test using BK */
++				u8 issued = 0;
++
++				/* issued = (psta->htpriv.agg_enable_bitmap>>priority)&0x1; */
++				issued |= (psta->htpriv.candidate_tid_bitmap >> priority) & 0x1;
++
++				if (0 == issued) {
++					if (!(psta->state & WIFI_STA_ALIVE_CHK_STATE)) {
++						psta->htpriv.candidate_tid_bitmap |= BIT((u8)priority);
++
++						if (psta->state & WIFI_SLEEP_STATE)
++							psta->expire_to = 2; /* 2x2=4 sec */
++						else
++							psta->expire_to = 1; /* 2 sec */
++
++						psta->state |= WIFI_STA_ALIVE_CHK_STATE;
++
++						/* add_ba_hdl(padapter, (u8*)paddbareq_parm); */
++
++						RTW_INFO("issue addba_req to check if sta alive, keep_alive_trycnt=%d\n", psta->keep_alive_trycnt);
++
++						issue_addba_req(padapter, psta->cmn.mac_addr, (u8)priority);
++
++						_set_timer(&psta->addba_retry_timer, ADDBA_TO);
++
++						psta->keep_alive_trycnt++;
++
++						continue;
++					}
++				}
++			}
++			if (psta->keep_alive_trycnt > 0 && psta->state & WIFI_STA_ALIVE_CHK_STATE) {
++				psta->keep_alive_trycnt = 0;
++				psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
++				RTW_INFO("change to another methods to check alive if staion is at ps mode\n");
++			}
++
++#endif /* CONFIG_80211N_HT */
++#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK	 */
++			if (psta->state & WIFI_SLEEP_STATE) {
++				if (!(psta->state & WIFI_STA_ALIVE_CHK_STATE)) {
++					/* to check if alive by another methods if staion is at ps mode.					 */
++					psta->expire_to = pstapriv->expire_to;
++					psta->state |= WIFI_STA_ALIVE_CHK_STATE;
++
++					/* RTW_INFO("alive chk, sta:" MAC_FMT " is at ps mode!\n", MAC_ARG(psta->cmn.mac_addr)); */
++
++					/* to update bcn with tim_bitmap for this station */
++					rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
++					update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0);
++
++					if (!pmlmeext->active_keep_alive_check)
++						continue;
++				}
++			}
++
++			{
++				int stainfo_offset;
++
++				stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
++				if (stainfo_offset_valid(stainfo_offset))
++					chk_alive_list[chk_alive_num++] = stainfo_offset;
++				continue;
++			}
++		} else {
++			/* TODO: Aging mechanism to digest frames in sleep_q to avoid running out of xmitframe */
++			if (psta->sleepq_len > (NR_XMITFRAME / pstapriv->asoc_list_cnt)
++			    && padapter->xmitpriv.free_xmitframe_cnt < ((NR_XMITFRAME / pstapriv->asoc_list_cnt) / 2)
++			   ) {
++				RTW_INFO(FUNC_ADPT_FMT" sta:"MAC_FMT", sleepq_len:%u, free_xmitframe_cnt:%u, asoc_list_cnt:%u, clear sleep_q\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++					, psta->sleepq_len, padapter->xmitpriv.free_xmitframe_cnt, pstapriv->asoc_list_cnt);
++				wakeup_sta_to_xmit(padapter, psta);
++			}
++		}
++	}
++
++	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++	if (chk_alive_num) {
++#if defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK)
++		u8 backup_ch = 0, backup_bw = 0, backup_offset = 0;
++		u8 union_ch = 0, union_bw = 0, union_offset = 0;
++		u8 switch_channel_by_drv = _TRUE;
++		struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++#endif
++		char del_asoc_list[NUM_STA];
++
++		_rtw_memset(del_asoc_list, NUM_STA, NUM_STA);
++
++		#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++		if (pmlmeext->active_keep_alive_check) {
++			#ifdef CONFIG_MCC_MODE
++			if (MCC_EN(padapter)) {
++				/* driver doesn't switch channel under MCC */
++				if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
++					switch_channel_by_drv = _FALSE;
++			}
++			#endif
++
++			if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset)
++				|| pmlmeext->cur_channel != union_ch)
++				switch_channel_by_drv = _FALSE;
++
++			/* switch to correct channel of current network  before issue keep-alive frames */
++			if (switch_channel_by_drv == _TRUE && rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) {
++				backup_ch = rtw_get_oper_ch(padapter);
++				backup_bw = rtw_get_oper_bw(padapter);
++				backup_offset = rtw_get_oper_choffset(padapter);
++				set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
++			}
++		}
++		#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
++
++		/* check loop */
++		for (i = 0; i < chk_alive_num; i++) {
++			#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++			int ret = _FAIL;
++			#endif
++
++			psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]);
++
++			#ifdef CONFIG_ATMEL_RC_PATCH
++			if (_rtw_memcmp(pstapriv->atmel_rc_pattern, psta->cmn.mac_addr, ETH_ALEN) == _TRUE)
++				continue;
++			if (psta->flag_atmel_rc)
++				continue;
++			#endif
++
++			if (!(psta->state & WIFI_ASOC_STATE))
++				continue;
++
++			#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++			if (pmlmeext->active_keep_alive_check) {
++				/* issue active keep alive frame to check */
++				ret = issue_aka_chk_frame(padapter, psta);
++
++				psta->keep_alive_trycnt++;
++				if (ret == _SUCCESS) {
++					RTW_INFO(FUNC_ADPT_FMT" asoc check, "MAC_FMT" is alive\n"
++						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
++					psta->expire_to = pstapriv->expire_to;
++					psta->keep_alive_trycnt = 0;
++					continue;
++				} else if (psta->keep_alive_trycnt <= 3) {
++					RTW_INFO(FUNC_ADPT_FMT" asoc check, "MAC_FMT" keep_alive_trycnt=%d\n"
++						, FUNC_ADPT_ARG(padapter) , MAC_ARG(psta->cmn.mac_addr), psta->keep_alive_trycnt);
++					psta->expire_to = 1;
++					continue;
++				}
++			}
++			#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
++
++			psta->keep_alive_trycnt = 0;
++			del_asoc_list[i] = chk_alive_list[i];
++			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++			if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
++				rtw_list_delete(&psta->asoc_list);
++				pstapriv->asoc_list_cnt--;
++				#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++				if (psta->tbtx_enable)
++					pstapriv->tbtx_asoc_list_cnt--;
++				#endif				
++				STA_SET_MESH_PLINK(psta, NULL);
++			}
++			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++		}
++
++		/* delete loop */
++		for (i = 0; i < chk_alive_num; i++) {
++			u8 sta_addr[ETH_ALEN];
++
++			if (del_asoc_list[i] >= NUM_STA)
++				continue;
++
++			psta = rtw_get_stainfo_by_offset(pstapriv, del_asoc_list[i]);
++			_rtw_memcpy(sta_addr, psta->cmn.mac_addr, ETH_ALEN);
++
++			RTW_INFO(FUNC_ADPT_FMT" asoc expire "MAC_FMT", state=0x%x\n"
++				, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr), psta->state);
++			updated |= ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _FALSE);
++			#ifdef CONFIG_RTW_MESH
++			if (MLME_IS_MESH(padapter))
++				rtw_mesh_expire_peer(padapter, sta_addr);
++			#endif
++		}
++
++		#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++		if (pmlmeext->active_keep_alive_check) {
++			/* back to the original operation channel */
++			if (switch_channel_by_drv == _TRUE && backup_ch > 0)
++				set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw);
++		}
++		#endif
++	}
++
++#ifdef RTW_CONFIG_RFREG18_WA
++	rtw_check_restore_rf18(padapter);
++#endif
++	associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
++}
++
++void rtw_ap_update_sta_ra_info(_adapter *padapter, struct sta_info *psta)
++{
++	unsigned char sta_band = 0;
++	u64 tx_ra_bitmap = 0;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
++
++	if (!psta)
++		return;
++
++	if (!(psta->state & WIFI_ASOC_STATE))
++		return;
++
++	rtw_hal_update_sta_ra_info(padapter, psta);
++	tx_ra_bitmap = psta->cmn.ra_info.ramask;
++
++	if (pcur_network->Configuration.DSConfig > 14) {
++
++		if (tx_ra_bitmap & 0xffff000)
++			sta_band |= WIRELESS_11_5N;
++
++		if (tx_ra_bitmap & 0xff0)
++			sta_band |= WIRELESS_11A;
++
++		/* 5G band */
++#ifdef CONFIG_80211AC_VHT
++		if (psta->vhtpriv.vht_option)
++			sta_band = WIRELESS_11_5AC;
++#endif
++	} else {
++		if (tx_ra_bitmap & 0xffff000)
++			sta_band |= WIRELESS_11_24N;
++
++		if (tx_ra_bitmap & 0xff0)
++			sta_band |= WIRELESS_11G;
++
++		if (tx_ra_bitmap & 0x0f)
++			sta_band |= WIRELESS_11B;
++	}
++
++	psta->wireless_mode = sta_band;
++	rtw_hal_update_sta_wset(padapter, psta);
++	RTW_INFO("%s=> mac_id:%d , tx_ra_bitmap:0x%016llx, networkType:0x%02x\n",
++			__FUNCTION__, psta->cmn.mac_id, tx_ra_bitmap, psta->wireless_mode);
++}
++
++#ifdef CONFIG_BMC_TX_RATE_SELECT
++u8 rtw_ap_find_mini_tx_rate(_adapter *adapter)
++{
++	_irqL irqL;
++	_list	*phead, *plist;
++	u8 miini_tx_rate = ODM_RATEVHTSS4MCS9, sta_tx_rate;
++	struct sta_info *psta = NULL;
++	struct sta_priv *pstapriv = &adapter->stapriv;
++
++	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++	phead = &pstapriv->asoc_list;
++	plist = get_next(phead);
++	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++		plist = get_next(plist);
++
++		sta_tx_rate = psta->cmn.ra_info.curr_tx_rate & 0x7F;
++		if (sta_tx_rate < miini_tx_rate)
++			miini_tx_rate = sta_tx_rate;
++	}
++	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++	return miini_tx_rate;
++}
++
++u8 rtw_ap_find_bmc_rate(_adapter *adapter, u8 tx_rate)
++{
++	PHAL_DATA_TYPE	hal_data = GET_HAL_DATA(adapter);
++	u8 tx_ini_rate = ODM_RATE6M;
++
++	switch (tx_rate) {
++	case ODM_RATEVHTSS3MCS9:
++	case ODM_RATEVHTSS3MCS8:
++	case ODM_RATEVHTSS3MCS7:
++	case ODM_RATEVHTSS3MCS6:
++	case ODM_RATEVHTSS3MCS5:
++	case ODM_RATEVHTSS3MCS4:
++	case ODM_RATEVHTSS3MCS3:
++	case ODM_RATEVHTSS2MCS9:
++	case ODM_RATEVHTSS2MCS8:
++	case ODM_RATEVHTSS2MCS7:
++	case ODM_RATEVHTSS2MCS6:
++	case ODM_RATEVHTSS2MCS5:
++	case ODM_RATEVHTSS2MCS4:
++	case ODM_RATEVHTSS2MCS3:
++	case ODM_RATEVHTSS1MCS9:
++	case ODM_RATEVHTSS1MCS8:
++	case ODM_RATEVHTSS1MCS7:
++	case ODM_RATEVHTSS1MCS6:
++	case ODM_RATEVHTSS1MCS5:
++	case ODM_RATEVHTSS1MCS4:
++	case ODM_RATEVHTSS1MCS3:
++	case ODM_RATEMCS15:
++	case ODM_RATEMCS14:
++	case ODM_RATEMCS13:
++	case ODM_RATEMCS12:
++	case ODM_RATEMCS11:
++	case ODM_RATEMCS7:
++	case ODM_RATEMCS6:
++	case ODM_RATEMCS5:
++	case ODM_RATEMCS4:
++	case ODM_RATEMCS3:
++	case ODM_RATE54M:
++	case ODM_RATE48M:
++	case ODM_RATE36M:
++	case ODM_RATE24M:
++		tx_ini_rate = ODM_RATE24M;
++		break;
++	case ODM_RATEVHTSS3MCS2:
++	case ODM_RATEVHTSS3MCS1:
++	case ODM_RATEVHTSS2MCS2:
++	case ODM_RATEVHTSS2MCS1:
++	case ODM_RATEVHTSS1MCS2:
++	case ODM_RATEVHTSS1MCS1:
++	case ODM_RATEMCS10:
++	case ODM_RATEMCS9:
++	case ODM_RATEMCS2:
++	case ODM_RATEMCS1:
++	case ODM_RATE18M:
++	case ODM_RATE12M:
++		tx_ini_rate = ODM_RATE12M;
++		break;
++	case ODM_RATEVHTSS3MCS0:
++	case ODM_RATEVHTSS2MCS0:
++	case ODM_RATEVHTSS1MCS0:
++	case ODM_RATEMCS8:
++	case ODM_RATEMCS0:
++	case ODM_RATE9M:
++	case ODM_RATE6M:
++		tx_ini_rate = ODM_RATE6M;
++		break;
++	case ODM_RATE11M:
++	case ODM_RATE5_5M:
++	case ODM_RATE2M:
++	case ODM_RATE1M:
++		tx_ini_rate = ODM_RATE1M;
++		break;
++	default:
++		tx_ini_rate = ODM_RATE6M;
++		break;
++	}
++
++	if (hal_data->current_band_type == BAND_ON_5G)
++		if (tx_ini_rate < ODM_RATE6M)
++			tx_ini_rate = ODM_RATE6M;
++
++	return tx_ini_rate;
++}
++
++void rtw_update_bmc_sta_tx_rate(_adapter *adapter)
++{
++	struct sta_info *psta = NULL;
++	u8 tx_rate;
++
++	psta = rtw_get_bcmc_stainfo(adapter);
++	if (psta == NULL) {
++		RTW_ERR(ADPT_FMT "could not get bmc_sta !!\n", ADPT_ARG(adapter));
++		return;
++	}
++
++	if (adapter->bmc_tx_rate != MGN_UNKNOWN) {
++		psta->init_rate = adapter->bmc_tx_rate;
++		goto _exit;
++	}
++
++	if (adapter->stapriv.asoc_sta_count <= 2)
++		goto _exit;
++
++	tx_rate = rtw_ap_find_mini_tx_rate(adapter);
++	#ifdef CONFIG_BMC_TX_LOW_RATE
++	tx_rate = rtw_ap_find_bmc_rate(adapter, tx_rate);
++	#endif
++
++	psta->init_rate = hw_rate_to_m_rate(tx_rate);
++
++_exit:
++	RTW_INFO(ADPT_FMT" BMC Tx rate - %s\n", ADPT_ARG(adapter), MGN_RATE_STR(psta->init_rate));
++}
++#endif
++
++void rtw_init_bmc_sta_tx_rate(_adapter *padapter, struct sta_info *psta)
++{
++#ifdef CONFIG_BMC_TX_LOW_RATE
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++#endif
++	u8 rate_idx = 0;
++	u8 brate_table[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M,
++		MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M};
++
++	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
++		return;
++
++	if (padapter->bmc_tx_rate != MGN_UNKNOWN)
++		psta->init_rate = padapter->bmc_tx_rate;
++	else {
++		#ifdef CONFIG_BMC_TX_LOW_RATE
++		if (IsEnableHWOFDM(pmlmeext->cur_wireless_mode) && (psta->cmn.ra_info.ramask && 0xFF0))
++			rate_idx = get_lowest_rate_idx_ex(psta->cmn.ra_info.ramask, 4); /*from basic rate*/
++		else
++			rate_idx = get_lowest_rate_idx(psta->cmn.ra_info.ramask); /*from basic rate*/
++		#else
++		rate_idx = get_highest_rate_idx(psta->cmn.ra_info.ramask); /*from basic rate*/
++		#endif
++		if (rate_idx < 12)
++			psta->init_rate = brate_table[rate_idx];
++		else
++			psta->init_rate = MGN_1M;
++	}
++
++	RTW_INFO(ADPT_FMT" BMC Init Tx rate - %s\n", ADPT_ARG(padapter), MGN_RATE_STR(psta->init_rate));
++}
++
++void update_bmc_sta(_adapter *padapter)
++{
++	_irqL	irqL;
++	unsigned char	network_type;
++	int supportRateNum = 0;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
++	struct sta_info *psta = rtw_get_bcmc_stainfo(padapter);
++
++	if (psta) {
++		psta->cmn.aid = 0;/* default set to 0 */
++#ifdef CONFIG_RTW_MESH
++		if (MLME_IS_MESH(padapter))
++			psta->qos_option = 1;
++		else
++#endif
++			psta->qos_option = 0;
++#ifdef CONFIG_80211N_HT
++		psta->htpriv.ht_option = _FALSE;
++#endif /* CONFIG_80211N_HT */
++
++		psta->ieee8021x_blocked = 0;
++
++		_rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats));
++
++		/* psta->dot118021XPrivacy = _NO_PRIVACY_; */ /* !!! remove it, because it has been set before this. */
++
++		supportRateNum = rtw_get_rateset_len((u8 *)&pcur_network->SupportedRates);
++		network_type = rtw_check_network_type((u8 *)&pcur_network->SupportedRates, supportRateNum, pcur_network->Configuration.DSConfig);
++		if (IsSupportedTxCCK(network_type))
++			network_type = WIRELESS_11B;
++		else if (network_type == WIRELESS_INVALID) { /* error handling */
++			if (pcur_network->Configuration.DSConfig > 14)
++				network_type = WIRELESS_11A;
++			else
++				network_type = WIRELESS_11B;
++		}
++		update_sta_basic_rate(psta, network_type);
++		psta->wireless_mode = network_type;
++
++		rtw_hal_update_sta_ra_info(padapter, psta);
++
++		_enter_critical_bh(&psta->lock, &irqL);
++		psta->state = WIFI_ASOC_STATE;
++		_exit_critical_bh(&psta->lock, &irqL);
++
++		rtw_sta_media_status_rpt(padapter, psta, 1);
++		rtw_init_bmc_sta_tx_rate(padapter, psta);
++
++	} else
++		RTW_INFO("add_RATid_bmc_sta error!\n");
++
++}
++
++#if defined(CONFIG_80211N_HT) && defined(CONFIG_BEAMFORMING)
++void update_sta_info_apmode_ht_bf_cap(_adapter *padapter, struct sta_info *psta)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct ht_priv	*phtpriv_ap = &pmlmepriv->htpriv;
++	struct ht_priv	*phtpriv_sta = &psta->htpriv;
++
++	u8 cur_beamform_cap = 0;
++
++	/*Config Tx beamforming setting*/
++	if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
++		GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP((u8 *)(&phtpriv_sta->ht_cap))) {
++		SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
++		/*Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/
++		SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 6);
++	}
++
++	if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
++		GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP((u8 *)(&phtpriv_sta->ht_cap))) {
++		SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
++		/*Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/
++		SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 4);
++	}
++	if (cur_beamform_cap)
++		RTW_INFO("Client STA(%d) HT Beamforming Cap = 0x%02X\n", psta->cmn.aid, cur_beamform_cap);
++
++	phtpriv_sta->beamform_cap = cur_beamform_cap;
++	psta->cmn.bf_info.ht_beamform_cap = cur_beamform_cap;
++
++}
++#endif /*CONFIG_80211N_HT && CONFIG_BEAMFORMING*/
++
++/* notes:
++ * AID: 1~MAX for sta and 0 for bc/mc in ap/adhoc mode  */
++void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta)
++{
++	_irqL	irqL;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++#ifdef CONFIG_80211N_HT
++	struct ht_priv	*phtpriv_ap = &pmlmepriv->htpriv;
++	struct ht_priv	*phtpriv_sta = &psta->htpriv;
++#endif /* CONFIG_80211N_HT */
++	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0;
++	/* set intf_tag to if1 */
++	/* psta->intf_tag = 0; */
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	/*alloc macid when call rtw_alloc_stainfo(),release macid when call rtw_free_stainfo()*/
++
++	if (!MLME_IS_MESH(padapter) && psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
++		psta->ieee8021x_blocked = _TRUE;
++	else
++		psta->ieee8021x_blocked = _FALSE;
++
++
++	/* update sta's cap */
++
++	/* ERP */
++	VCS_update(padapter, psta);
++#ifdef CONFIG_80211N_HT
++	/* HT related cap */
++	if (phtpriv_sta->ht_option) {
++		/* check if sta supports rx ampdu */
++		phtpriv_sta->ampdu_enable = phtpriv_ap->ampdu_enable;
++
++		phtpriv_sta->rx_ampdu_min_spacing = (phtpriv_sta->ht_cap.ampdu_params_info & IEEE80211_HT_CAP_AMPDU_DENSITY) >> 2;
++
++		/* bwmode */
++		if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH))
++			psta->cmn.bw_mode = CHANNEL_WIDTH_40;
++		else
++			psta->cmn.bw_mode = CHANNEL_WIDTH_20;
++
++		if (phtpriv_sta->op_present
++			&& !GET_HT_OP_ELE_STA_CHL_WIDTH(phtpriv_sta->ht_op))
++			psta->cmn.bw_mode = CHANNEL_WIDTH_20;
++
++		if (psta->ht_40mhz_intolerant)
++			psta->cmn.bw_mode = CHANNEL_WIDTH_20;
++
++		if (pmlmeext->cur_bwmode < psta->cmn.bw_mode)
++			psta->cmn.bw_mode = pmlmeext->cur_bwmode;
++
++		phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset;
++
++
++		/* check if sta support s Short GI 20M */
++		if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_20))
++			phtpriv_sta->sgi_20m = _TRUE;
++
++		/* check if sta support s Short GI 40M */
++		if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)) {
++			if (psta->cmn.bw_mode == CHANNEL_WIDTH_40) /* according to psta->bw_mode */
++				phtpriv_sta->sgi_40m = _TRUE;
++			else
++				phtpriv_sta->sgi_40m = _FALSE;
++		}
++
++		psta->qos_option = _TRUE;
++
++		/* B0 Config LDPC Coding Capability */
++		if (TEST_FLAG(phtpriv_ap->ldpc_cap, LDPC_HT_ENABLE_TX) &&
++		    GET_HT_CAP_ELE_LDPC_CAP((u8 *)(&phtpriv_sta->ht_cap))) {
++			SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX));
++			RTW_INFO("Enable HT Tx LDPC for STA(%d)\n", psta->cmn.aid);
++		}
++
++		/* B7 B8 B9 Config STBC setting */
++		if (TEST_FLAG(phtpriv_ap->stbc_cap, STBC_HT_ENABLE_TX) &&
++		    GET_HT_CAP_ELE_RX_STBC((u8 *)(&phtpriv_sta->ht_cap))) {
++			SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX));
++			RTW_INFO("Enable HT Tx STBC for STA(%d)\n", psta->cmn.aid);
++		}
++
++		#ifdef CONFIG_BEAMFORMING
++		update_sta_info_apmode_ht_bf_cap(padapter, psta);
++		#endif
++	} else {
++		phtpriv_sta->ampdu_enable = _FALSE;
++
++		phtpriv_sta->sgi_20m = _FALSE;
++		phtpriv_sta->sgi_40m = _FALSE;
++		psta->cmn.bw_mode = CHANNEL_WIDTH_20;
++		phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++	}
++
++	phtpriv_sta->ldpc_cap = cur_ldpc_cap;
++	phtpriv_sta->stbc_cap = cur_stbc_cap;
++
++	/* Rx AMPDU */
++	send_delba(padapter, 0, psta->cmn.mac_addr);/* recipient */
++
++	/* TX AMPDU */
++	send_delba(padapter, 1, psta->cmn.mac_addr);/*  */ /* originator */
++	phtpriv_sta->agg_enable_bitmap = 0x0;/* reset */
++	phtpriv_sta->candidate_tid_bitmap = 0x0;/* reset */
++#endif /* CONFIG_80211N_HT */
++
++#ifdef CONFIG_80211AC_VHT
++	update_sta_vht_info_apmode(padapter, psta);
++#endif
++	psta->cmn.ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta));
++	update_ldpc_stbc_cap(psta);
++
++	/* todo: init other variables */
++
++	_rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats));
++
++
++	/* add ratid */
++	/* add_RATid(padapter, psta); */ /* move to ap_sta_info_defer_update() */
++
++	/* ap mode */
++	rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);
++
++	_enter_critical_bh(&psta->lock, &irqL);
++
++	/* Check encryption */
++	if (!MLME_IS_MESH(padapter) && psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
++		psta->state |= WIFI_UNDER_KEY_HANDSHAKE;
++
++	psta->state |= WIFI_ASOC_STATE;
++
++	_exit_critical_bh(&psta->lock, &irqL);
++}
++
++static void update_ap_info(_adapter *padapter, struct sta_info *psta)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++#ifdef CONFIG_80211N_HT
++	struct ht_priv	*phtpriv_ap = &pmlmepriv->htpriv;
++#endif /* CONFIG_80211N_HT */
++
++	psta->wireless_mode = pmlmeext->cur_wireless_mode;
++
++	psta->bssratelen = rtw_get_rateset_len(pnetwork->SupportedRates);
++	_rtw_memcpy(psta->bssrateset, pnetwork->SupportedRates, psta->bssratelen);
++
++#ifdef CONFIG_80211N_HT
++	/* HT related cap */
++	if (phtpriv_ap->ht_option) {
++		/* check if sta supports rx ampdu */
++		/* phtpriv_ap->ampdu_enable = phtpriv_ap->ampdu_enable; */
++
++		/* check if sta support s Short GI 20M */
++		if ((phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_20))
++			phtpriv_ap->sgi_20m = _TRUE;
++		/* check if sta support s Short GI 40M */
++		if ((phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_40))
++			phtpriv_ap->sgi_40m = _TRUE;
++
++		psta->qos_option = _TRUE;
++	} else {
++		phtpriv_ap->ampdu_enable = _FALSE;
++
++		phtpriv_ap->sgi_20m = _FALSE;
++		phtpriv_ap->sgi_40m = _FALSE;
++	}
++
++	psta->cmn.bw_mode = pmlmeext->cur_bwmode;
++	phtpriv_ap->ch_offset = pmlmeext->cur_ch_offset;
++
++	phtpriv_ap->agg_enable_bitmap = 0x0;/* reset */
++	phtpriv_ap->candidate_tid_bitmap = 0x0;/* reset */
++
++	_rtw_memcpy(&psta->htpriv, &pmlmepriv->htpriv, sizeof(struct ht_priv));
++
++#ifdef CONFIG_80211AC_VHT
++	_rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv));
++#endif /* CONFIG_80211AC_VHT */
++
++#endif /* CONFIG_80211N_HT */
++
++	psta->state |= WIFI_AP_STATE; /* Aries, add,fix bug of flush_cam_entry at STOP AP mode , 0724 */
++}
++
++static void rtw_set_hw_wmm_param(_adapter *padapter)
++{
++	u8	AIFS, ECWMin, ECWMax, aSifsTime;
++	u8	acm_mask;
++	u16	TXOP;
++	u32	acParm, i;
++	u32	edca[4], inx[4];
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct xmit_priv		*pxmitpriv = &padapter->xmitpriv;
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++
++	acm_mask = 0;
++#ifdef CONFIG_80211N_HT
++	if (pregpriv->ht_enable &&
++		(is_supported_5g(pmlmeext->cur_wireless_mode) ||
++	    (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)))
++		aSifsTime = 16;
++	else
++#endif /* CONFIG_80211N_HT */
++		aSifsTime = 10;
++
++	if (pmlmeinfo->WMM_enable == 0) {
++		padapter->mlmepriv.acm_mask = 0;
++
++		AIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
++
++		if (pmlmeext->cur_wireless_mode & (WIRELESS_11G | WIRELESS_11A)) {
++			ECWMin = 4;
++			ECWMax = 10;
++		} else if (pmlmeext->cur_wireless_mode & WIRELESS_11B) {
++			ECWMin = 5;
++			ECWMax = 10;
++		} else {
++			ECWMin = 4;
++			ECWMax = 10;
++		}
++
++		TXOP = 0;
++		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));
++
++		ECWMin = 2;
++		ECWMax = 3;
++		TXOP = 0x2f;
++		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));
++
++	} else {
++		edca[0] = edca[1] = edca[2] = edca[3] = 0;
++
++		/*TODO:*/
++		acm_mask = 0;
++		padapter->mlmepriv.acm_mask = acm_mask;
++
++#if 0
++		/* BK */
++		/* AIFS = AIFSN * slot time + SIFS - r2t phy delay */
++#endif
++		AIFS = (7 * pmlmeinfo->slotTime) + aSifsTime;
++		ECWMin = 4;
++		ECWMax = 10;
++		TXOP = 0;
++		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));
++		edca[XMIT_BK_QUEUE] = acParm;
++		RTW_INFO("WMM(BK): %x\n", acParm);
++
++		/* BE */
++		AIFS = (3 * pmlmeinfo->slotTime) + aSifsTime;
++		ECWMin = 4;
++		ECWMax = 6;
++		TXOP = 0;
++		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));
++		edca[XMIT_BE_QUEUE] = acParm;
++		RTW_INFO("WMM(BE): %x\n", acParm);
++
++		/* VI */
++		AIFS = (1 * pmlmeinfo->slotTime) + aSifsTime;
++		ECWMin = 3;
++		ECWMax = 4;
++		TXOP = 94;
++		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));
++		edca[XMIT_VI_QUEUE] = acParm;
++		RTW_INFO("WMM(VI): %x\n", acParm);
++
++		/* VO */
++		AIFS = (1 * pmlmeinfo->slotTime) + aSifsTime;
++		ECWMin = 2;
++		ECWMax = 3;
++		TXOP = 47;
++		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));
++		edca[XMIT_VO_QUEUE] = acParm;
++		RTW_INFO("WMM(VO): %x\n", acParm);
++
++
++		if (padapter->registrypriv.acm_method == 1)
++			rtw_hal_set_hwreg(padapter, HW_VAR_ACM_CTRL, (u8 *)(&acm_mask));
++		else
++			padapter->mlmepriv.acm_mask = acm_mask;
++
++		inx[0] = 0;
++		inx[1] = 1;
++		inx[2] = 2;
++		inx[3] = 3;
++
++		if (pregpriv->wifi_spec == 1) {
++			u32	j, tmp, change_inx = _FALSE;
++
++			/* entry indx: 0->vo, 1->vi, 2->be, 3->bk. */
++			for (i = 0 ; i < 4 ; i++) {
++				for (j = i + 1 ; j < 4 ; j++) {
++					/* compare CW and AIFS */
++					if ((edca[j] & 0xFFFF) < (edca[i] & 0xFFFF))
++						change_inx = _TRUE;
++					else if ((edca[j] & 0xFFFF) == (edca[i] & 0xFFFF)) {
++						/* compare TXOP */
++						if ((edca[j] >> 16) > (edca[i] >> 16))
++							change_inx = _TRUE;
++					}
++
++					if (change_inx) {
++						tmp = edca[i];
++						edca[i] = edca[j];
++						edca[j] = tmp;
++
++						tmp = inx[i];
++						inx[i] = inx[j];
++						inx[j] = tmp;
++
++						change_inx = _FALSE;
++					}
++				}
++			}
++		}
++
++		for (i = 0 ; i < 4 ; i++) {
++			pxmitpriv->wmm_para_seq[i] = inx[i];
++			RTW_INFO("wmm_para_seq(%d): %d\n", i, pxmitpriv->wmm_para_seq[i]);
++		}
++
++	}
++
++}
++#ifdef CONFIG_80211N_HT
++static void update_hw_ht_param(_adapter *padapter)
++{
++	unsigned char		max_AMPDU_len;
++	unsigned char		min_MPDU_spacing;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++
++	/* handle A-MPDU parameter field */
++	/*
++		AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k
++		AMPDU_para [4:2]:Min MPDU Start Spacing
++	*/
++	max_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
++
++	min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2;
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing));
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len));
++
++	/*  */
++	/* Config SM Power Save setting */
++	/*  */
++	pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2;
++	if (pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) {
++#if 0
++		u8 i;
++		/* update the MCS rates */
++		for (i = 0; i < 16; i++)
++			pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
++#endif
++		RTW_INFO("%s(): WLAN_HT_CAP_SM_PS_STATIC\n", __FUNCTION__);
++	}
++
++	/*  */
++	/* Config current HT Protection mode. */
++	/*  */
++	/* pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; */
++
++}
++#endif /* CONFIG_80211N_HT */
++static void rtw_ap_check_scan(_adapter *padapter)
++{
++	_irqL	irqL;
++	_list		*plist, *phead;
++	u32	delta_time, lifetime;
++	struct	wlan_network	*pnetwork = NULL;
++	WLAN_BSSID_EX *pbss = NULL;
++	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	_queue	*queue	= &(pmlmepriv->scanned_queue);
++	u8 do_scan = _FALSE;
++	u8 reason = RTW_AUTO_SCAN_REASON_UNSPECIFIED;
++
++	lifetime = SCANQUEUE_LIFETIME; /* 20 sec */
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++	phead = get_list_head(queue);
++	if (rtw_end_of_queue_search(phead, get_next(phead)) == _TRUE)
++		if (padapter->registrypriv.wifi_spec) {
++			do_scan = _TRUE;
++			reason |= RTW_AUTO_SCAN_REASON_2040_BSS;
++		}
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++#ifdef CONFIG_RTW_ACS
++	if (padapter->registrypriv.acs_auto_scan) {
++		do_scan = _TRUE;
++		reason |= RTW_AUTO_SCAN_REASON_ACS;
++		rtw_acs_start(padapter);
++	}
++#endif/*CONFIG_RTW_ACS*/
++
++	if (_TRUE == do_scan) {
++		RTW_INFO("%s : drv scans by itself and wait_completed\n", __func__);
++		rtw_drv_scan_by_self(padapter, reason);
++		rtw_scan_wait_completed(padapter);
++	}
++
++#ifdef CONFIG_RTW_ACS
++	if (padapter->registrypriv.acs_auto_scan)
++		rtw_acs_stop(padapter);
++#endif
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++
++	while (1) {
++
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++		if (rtw_chset_search_ch(adapter_to_chset(padapter), pnetwork->network.Configuration.DSConfig) >= 0
++		    && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE
++		    && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))) {
++			delta_time = (u32) rtw_get_passing_time_ms(pnetwork->last_scanned);
++
++			if (delta_time < lifetime) {
++
++				uint ie_len = 0;
++				u8 *pbuf = NULL;
++				u8 *ie = NULL;
++
++				pbss = &pnetwork->network;
++				ie = pbss->IEs;
++
++				/*check if HT CAP INFO IE exists or not*/
++				pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pbss->IELength - _BEACON_IE_OFFSET_));
++				if (pbuf == NULL) {
++					/* HT CAP INFO IE don't exist, it is b/g mode bss.*/
++
++					if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc))
++						ATOMIC_SET(&pmlmepriv->olbc, _TRUE);
++
++					if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc_ht))
++						ATOMIC_SET(&pmlmepriv->olbc_ht, _TRUE);
++					
++					if (padapter->registrypriv.wifi_spec)
++						RTW_INFO("%s: %s is a/b/g ap\n", __func__, pnetwork->network.Ssid.Ssid);
++				}
++			}
++		}
++
++		plist = get_next(plist);
++
++	}
++
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++#ifdef CONFIG_80211N_HT
++	pmlmepriv->num_sta_no_ht = 0; /* reset to 0 after ap do scanning*/
++#endif
++}
++
++void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter)
++{
++	WLAN_BSSID_EX *pnetwork = &(adapter->mlmepriv.cur_network.network);
++	struct sta_info *sta = NULL;
++
++	/* update cur_wireless_mode */
++	update_wireless_mode(adapter);
++
++	/* update RRSR and RTS_INIT_RATE register after set channel and bandwidth */
++	UpdateBrateTbl(adapter, pnetwork->SupportedRates);
++	rtw_hal_set_hwreg(adapter, HW_VAR_BASIC_RATE, pnetwork->SupportedRates);
++
++	/* update capability after cur_wireless_mode updated */
++	update_capinfo(adapter, rtw_get_capability(pnetwork));
++
++	/* update bc/mc sta_info */
++	update_bmc_sta(adapter);
++
++	/* update AP's sta info */
++	sta = rtw_get_stainfo(&adapter->stapriv, pnetwork->MacAddress);
++	if (!sta) {
++		RTW_INFO(FUNC_ADPT_FMT" !sta for macaddr="MAC_FMT"\n", FUNC_ADPT_ARG(adapter), MAC_ARG(pnetwork->MacAddress));
++		rtw_warn_on(1);
++		return;
++	}
++
++	update_ap_info(adapter, sta);
++}
++
++#ifdef CONFIG_FW_HANDLE_TXBCN
++bool rtw_ap_nums_check(_adapter *adapter)
++{
++	if (rtw_ap_get_nums(adapter) < CONFIG_LIMITED_AP_NUM)
++		return _TRUE;
++	return _FALSE;
++}
++u8 rtw_ap_allocate_vapid(struct dvobj_priv *dvobj)
++{
++	u8 vap_id;
++
++	for (vap_id = 0; vap_id < CONFIG_LIMITED_AP_NUM; vap_id++) {
++		if (!(dvobj->vap_map & BIT(vap_id)))
++			break;
++	}
++
++	if (vap_id < CONFIG_LIMITED_AP_NUM)
++		dvobj->vap_map |= BIT(vap_id);
++
++	return vap_id;
++}
++u8 rtw_ap_release_vapid(struct dvobj_priv *dvobj, u8 vap_id)
++{
++	if (vap_id >= CONFIG_LIMITED_AP_NUM) {
++		RTW_ERR("%s - vapid(%d) failed\n", __func__, vap_id);
++		rtw_warn_on(1);
++		return _FAIL;
++	}
++	dvobj->vap_map &= ~ BIT(vap_id);
++	return _SUCCESS;
++}
++#endif
++static void _rtw_iface_undersurvey_chk(const char *func, _adapter *adapter)
++{
++	int i;
++	_adapter *iface;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mlme_priv *pmlmepriv;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if ((iface) && rtw_is_adapter_up(iface)) {
++			pmlmepriv = &iface->mlmepriv;
++			if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY))
++				RTW_ERR("%s ("ADPT_FMT") under survey\n", func, ADPT_ARG(iface));
++		}
++	}
++}
++void start_bss_network(_adapter *padapter, struct createbss_parm *parm)
++{
++#define DUMP_ADAPTERS_STATUS 0
++	u8 mlme_act = MLME_ACTION_UNKNOWN;
++	u8 val8;
++	u16 bcn_interval;
++	u32	acparm;
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct security_priv *psecuritypriv = &(padapter->securitypriv);
++	WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; /* used as input */
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network);
++	struct dvobj_priv *pdvobj = padapter->dvobj;
++	s16 req_ch = REQ_CH_NONE, req_bw = REQ_BW_NONE, req_offset = REQ_OFFSET_NONE;
++	u8 ch_to_set = 0, bw_to_set, offset_to_set;
++	u8 doiqk = _FALSE;
++	/* use for check ch bw offset can be allowed or not */
++	u8 chbw_allow = _TRUE;
++	int i;
++	u8 ifbmp_ch_changed = 0;
++
++	if (parm->req_ch != 0) {
++		/* bypass other setting, go checking ch, bw, offset */
++		mlme_act = MLME_OPCH_SWITCH;
++		req_ch = parm->req_ch;
++		req_bw = parm->req_bw;
++		req_offset = parm->req_offset;
++		goto chbw_decision;
++	} else {
++		/* request comes from upper layer */
++		if (MLME_IS_AP(padapter))
++			mlme_act = MLME_AP_STARTED;
++		else if (MLME_IS_MESH(padapter))
++			mlme_act = MLME_MESH_STARTED;
++		else
++			rtw_warn_on(1);
++		req_ch = 0;
++		_rtw_memcpy(pnetwork_mlmeext, pnetwork, pnetwork->Length);
++	}
++
++	bcn_interval = (u16)pnetwork->Configuration.BeaconPeriod;
++
++	/* check if there is wps ie, */
++	/* if there is wpsie in beacon, the hostapd will update beacon twice when stating hostapd, */
++	/* and at first time the security ie ( RSN/WPA IE) will not include in beacon. */
++	if (NULL == rtw_get_wps_ie(pnetwork->IEs + _FIXED_IE_LENGTH_, pnetwork->IELength - _FIXED_IE_LENGTH_, NULL, NULL))
++		pmlmeext->bstart_bss = _TRUE;
++
++	/* todo: update wmm, ht cap */
++	/* pmlmeinfo->WMM_enable; */
++	/* pmlmeinfo->HT_enable; */
++	if (pmlmepriv->qospriv.qos_option)
++		pmlmeinfo->WMM_enable = _TRUE;
++#ifdef CONFIG_80211N_HT
++	if (pmlmepriv->htpriv.ht_option) {
++		pmlmeinfo->WMM_enable = _TRUE;
++		pmlmeinfo->HT_enable = _TRUE;
++		/* pmlmeinfo->HT_info_enable = _TRUE; */
++		/* pmlmeinfo->HT_caps_enable = _TRUE; */
++
++		update_hw_ht_param(padapter);
++	}
++#endif /* #CONFIG_80211N_HT */
++
++#ifdef CONFIG_80211AC_VHT
++	if (pmlmepriv->vhtpriv.vht_option) {
++		pmlmeinfo->VHT_enable = _TRUE;
++		update_hw_vht_param(padapter);
++	}
++#endif /* CONFIG_80211AC_VHT */
++
++	if (pmlmepriv->cur_network.join_res != _TRUE) { /* setting only at  first time */
++		/* WEP Key will be set before this function, do not clear CAM. */
++		if ((psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) && (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_)
++			&& !MLME_IS_MESH(padapter) /* mesh group key is set before this function */
++		)
++			flush_all_cam_entry(padapter);	/* clear CAM */
++	}
++
++	/* set MSR to AP_Mode		 */
++	Set_MSR(padapter, _HW_STATE_AP_);
++
++	/* Set BSSID REG */
++	rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pnetwork->MacAddress);
++
++	/* Set Security */
++	val8 = (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) ? 0xcc : 0xcf;
++	rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
++
++	/* Beacon Control related register */
++	rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&bcn_interval));
++
++	rtw_hal_rcr_set_chk_bssid(padapter, mlme_act);
++
++chbw_decision:
++	ifbmp_ch_changed = rtw_ap_chbw_decision(padapter, parm->ifbmp, parm->excl_ifbmp
++						, req_ch, req_bw, req_offset
++						, &ch_to_set, &bw_to_set, &offset_to_set, &chbw_allow);
++
++	for (i = 0; i < pdvobj->iface_nums; i++) {
++		if (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i])
++			continue;
++
++		/* let pnetwork_mlme == pnetwork_mlmeext */
++		_rtw_memcpy(&(pdvobj->padapters[i]->mlmepriv.cur_network.network)
++			, &(pdvobj->padapters[i]->mlmeextpriv.mlmext_info.network)
++			, pdvobj->padapters[i]->mlmeextpriv.mlmext_info.network.Length);
++
++		rtw_start_bss_hdl_after_chbw_decided(pdvobj->padapters[i]);
++
++		/* Set EDCA param reg after update cur_wireless_mode & update_capinfo */
++		if (pregpriv->wifi_spec == 1)
++			rtw_set_hw_wmm_param(pdvobj->padapters[i]);
++	}
++
++#if defined(CONFIG_DFS_MASTER)
++	rtw_dfs_rd_en_decision(padapter, mlme_act, parm->excl_ifbmp);
++#endif
++
++#ifdef CONFIG_MCC_MODE
++	if (MCC_EN(padapter)) {
++		/* 
++		* due to check under rtw_ap_chbw_decision
++		* if under MCC mode, means req channel setting is the same as current channel setting
++		* if not under MCC mode, mean req channel setting is not the same as current channel setting
++		*/
++		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
++				RTW_INFO(FUNC_ADPT_FMT": req channel setting is the same as current channel setting, go to update BCN\n"
++				, FUNC_ADPT_ARG(padapter));
++
++				goto update_beacon;
++
++		}
++	}
++
++	/* issue null data to AP for all interface connecting to AP before switch channel setting for softap */
++	rtw_hal_mcc_issue_null_data(padapter, chbw_allow, 1);
++#endif /* CONFIG_MCC_MODE */
++
++	if (!IS_CH_WAITING(adapter_to_rfctl(padapter))) {
++		doiqk = _TRUE;
++		rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
++	}
++
++	if (ch_to_set != 0) {
++		set_channel_bwmode(padapter, ch_to_set, offset_to_set, bw_to_set);
++		rtw_mi_update_union_chan_inf(padapter, ch_to_set, offset_to_set, bw_to_set);
++	}
++
++	doiqk = _FALSE;
++	rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
++
++#ifdef CONFIG_MCC_MODE
++	/* after set_channel_bwmode for backup IQK */
++	rtw_hal_set_mcc_setting_start_bss_network(padapter, chbw_allow);
++#endif
++
++#if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++	for (i = 0; i < pdvobj->iface_nums; i++) {
++		if (!(ifbmp_ch_changed & BIT(i)) || !pdvobj->padapters[i])
++			continue;
++
++		{
++			u8 ht_option = 0;
++
++			#ifdef CONFIG_80211N_HT
++			ht_option = pdvobj->padapters[i]->mlmepriv.htpriv.ht_option;
++			#endif
++
++			rtw_cfg80211_ch_switch_notify(pdvobj->padapters[i]
++				, pdvobj->padapters[i]->mlmeextpriv.cur_channel
++				, pdvobj->padapters[i]->mlmeextpriv.cur_bwmode
++				, pdvobj->padapters[i]->mlmeextpriv.cur_ch_offset
++				, ht_option, 0);
++		}
++	}
++#endif /* defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) */
++
++	if (DUMP_ADAPTERS_STATUS) {
++		RTW_INFO(FUNC_ADPT_FMT" done\n", FUNC_ADPT_ARG(padapter));
++		dump_adapters_status(RTW_DBGDUMP , adapter_to_dvobj(padapter));
++	}
++
++#ifdef CONFIG_MCC_MODE
++update_beacon:
++#endif
++
++	for (i = 0; i < pdvobj->iface_nums; i++) {
++		struct mlme_priv *mlme;
++
++		if (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i])
++			continue;
++
++		/* update beacon content only if bstart_bss is _TRUE */
++		if (pdvobj->padapters[i]->mlmeextpriv.bstart_bss != _TRUE)
++			continue;
++
++		mlme = &(pdvobj->padapters[i]->mlmepriv);
++
++		#ifdef CONFIG_80211N_HT
++		if ((ATOMIC_READ(&mlme->olbc) == _TRUE) || (ATOMIC_READ(&mlme->olbc_ht) == _TRUE)) {
++			/* AP is not starting a 40 MHz BSS in presence of an 802.11g BSS. */
++			mlme->ht_op_mode &= (~HT_INFO_OPERATION_MODE_OP_MODE_MASK);
++			mlme->ht_op_mode |= OP_MODE_MAY_BE_LEGACY_STAS;
++			update_beacon(pdvobj->padapters[i], _HT_ADD_INFO_IE_, NULL, _FALSE, 0);
++		}
++		#endif
++
++		update_beacon(pdvobj->padapters[i], _TIM_IE_, NULL, _FALSE, 0);
++	}
++
++	if (mlme_act != MLME_OPCH_SWITCH
++		&& pmlmeext->bstart_bss == _TRUE
++	) {
++#ifdef CONFIG_SUPPORT_MULTI_BCN
++		_irqL irqL;
++
++		_enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
++		if (rtw_is_list_empty(&padapter->list)) {
++			#ifdef CONFIG_FW_HANDLE_TXBCN
++			padapter->vap_id = rtw_ap_allocate_vapid(pdvobj);
++			#endif
++			rtw_list_insert_tail(&padapter->list, get_list_head(&pdvobj->ap_if_q));
++			pdvobj->nr_ap_if++;
++			pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL / pdvobj->nr_ap_if;
++		}
++		_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
++
++		#ifdef CONFIG_SWTIMER_BASED_TXBCN
++		rtw_ap_set_mbid_num(padapter, pdvobj->nr_ap_if);
++		rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pdvobj->inter_bcn_space));
++		#endif /*CONFIG_SWTIMER_BASED_TXBCN*/
++
++#endif /*CONFIG_SUPPORT_MULTI_BCN*/
++
++		#ifdef CONFIG_HW_P0_TSF_SYNC
++		correct_TSF(padapter, mlme_act);
++		#endif
++	}
++
++	rtw_scan_wait_completed(padapter);
++
++	_rtw_iface_undersurvey_chk(__func__, padapter);
++	/* send beacon */
++	ResumeTxBeacon(padapter);
++	{
++#if !defined(CONFIG_INTERRUPT_BASED_TXBCN)
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_PCI_BCN_POLLING)
++#ifdef CONFIG_SWTIMER_BASED_TXBCN
++		if (pdvobj->nr_ap_if == 1
++			&& mlme_act != MLME_OPCH_SWITCH
++		) {
++			RTW_INFO("start SW BCN TIMER!\n");
++			_set_timer(&pdvobj->txbcn_timer, bcn_interval);
++		}
++#else
++		for (i = 0; i < pdvobj->iface_nums; i++) {
++			if (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i])
++				continue;
++
++			if (send_beacon(pdvobj->padapters[i]) == _FAIL)
++				RTW_INFO(ADPT_FMT" issue_beacon, fail!\n", ADPT_ARG(pdvobj->padapters[i]));
++		}
++#endif
++#endif
++#endif /* !defined(CONFIG_INTERRUPT_BASED_TXBCN) */
++
++#ifdef CONFIG_FW_HANDLE_TXBCN
++		if (mlme_act != MLME_OPCH_SWITCH)
++			rtw_ap_mbid_bcn_en(padapter, padapter->vap_id);
++#endif
++	}
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	if (MLME_IS_AP(padapter) && padapter->tbtx_capability == _TRUE) {
++		_set_timer(&pmlmeext->tbtx_token_dispatch_timer, 1);
++		RTW_INFO("Start token dispatch\n");
++	}
++#endif
++}
++
++int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf,  int len)
++{
++	int ret = _SUCCESS;
++	u8 *p;
++	u8 *pHT_caps_ie = NULL;
++	u8 *pHT_info_ie = NULL;
++	u16 cap, ht_cap = _FALSE;
++	uint ie_len = 0;
++	int group_cipher, pairwise_cipher, gmcs;
++	u32 akm;
++	u8 mfp_opt = MFP_NO;
++	u8	channel, network_type;
++	u8 OUI1[] = {0x00, 0x50, 0xf2, 0x01};
++	u8 WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01};
++	HT_CAP_AMPDU_DENSITY best_ampdu_density;
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	WLAN_BSSID_EX *pbss_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
++	u8 *ie = pbss_network->IEs;
++	u8 vht_cap = _FALSE;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	u8 rf_num = 0;
++	int ret_rm;
++	/* SSID */
++	/* Supported rates */
++	/* DS Params */
++	/* WLAN_EID_COUNTRY */
++	/* ERP Information element */
++	/* Extended supported rates */
++	/* WPA/WPA2 */
++	/* Wi-Fi Wireless Multimedia Extensions */
++	/* ht_capab, ht_oper */
++	/* WPS IE */
++
++	RTW_INFO("%s, len=%d\n", __FUNCTION__, len);
++
++	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
++		return _FAIL;
++
++
++	if (len > MAX_IE_SZ)
++		return _FAIL;
++
++	pbss_network->IELength = len;
++
++	_rtw_memset(ie, 0, MAX_IE_SZ);
++
++	_rtw_memcpy(ie, pbuf, pbss_network->IELength);
++
++
++	if (pbss_network->InfrastructureMode != Ndis802_11APMode
++		&& pbss_network->InfrastructureMode != Ndis802_11_mesh
++	) {
++		rtw_warn_on(1);
++		return _FAIL;
++	}
++
++
++	rtw_ap_check_scan(padapter);
++
++
++	pbss_network->Rssi = 0;
++
++	_rtw_memcpy(pbss_network->MacAddress, adapter_mac_addr(padapter), ETH_ALEN);
++
++	/* beacon interval */
++	p = rtw_get_beacon_interval_from_ie(ie);/* ie + 8;	 */ /* 8: TimeStamp, 2: Beacon Interval 2:Capability */
++	/* pbss_network->Configuration.BeaconPeriod = le16_to_cpu(*(unsigned short*)p); */
++	pbss_network->Configuration.BeaconPeriod = RTW_GET_LE16(p);
++
++	/* capability */
++	/* cap = *(unsigned short *)rtw_get_capability_from_ie(ie); */
++	/* cap = le16_to_cpu(cap); */
++	cap = RTW_GET_LE16(ie);
++
++	/* SSID */
++	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SSID_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
++	if (p && ie_len > 0) {
++		_rtw_memset(&pbss_network->Ssid, 0, sizeof(NDIS_802_11_SSID));
++		_rtw_memcpy(pbss_network->Ssid.Ssid, (p + 2), ie_len);
++		pbss_network->Ssid.SsidLength = ie_len;
++#ifdef CONFIG_P2P
++		_rtw_memcpy(padapter->wdinfo.p2p_group_ssid, pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength);
++		padapter->wdinfo.p2p_group_ssid_len = pbss_network->Ssid.SsidLength;
++#endif
++	}
++
++#ifdef CONFIG_RTW_MESH
++	/* Mesh ID */
++	if (MLME_IS_MESH(padapter)) {
++		p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, WLAN_EID_MESH_ID, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
++		if (p && ie_len > 0) {
++			_rtw_memset(&pbss_network->mesh_id, 0, sizeof(NDIS_802_11_SSID));
++			_rtw_memcpy(pbss_network->mesh_id.Ssid, (p + 2), ie_len);
++			pbss_network->mesh_id.SsidLength = ie_len;
++		}
++	}
++#endif
++
++	/* chnnel */
++	channel = 0;
++	pbss_network->Configuration.Length = 0;
++	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _DSSET_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
++	if (p && ie_len > 0)
++		channel = *(p + 2);
++
++	pbss_network->Configuration.DSConfig = channel;
++
++	/*	support rate ie & ext support ie & IElen & SupportedRates	*/
++	network_type = rtw_update_rate_bymode(pbss_network, pregistrypriv->wireless_mode);
++
++	/* parsing ERP_IE */
++	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
++	if (p && ie_len > 0)  {
++		if(padapter->registrypriv.wireless_mode == WIRELESS_11B ) {
++
++			pbss_network->IELength = pbss_network->IELength - *(p+1) - 2;
++			ret_rm = rtw_ies_remove_ie(ie , &len, _BEACON_IE_OFFSET_, _ERPINFO_IE_,NULL,0);
++			RTW_DBG("%s, remove_ie of ERP_IE=%d\n", __FUNCTION__, ret_rm);
++		} else 
++			ERP_IE_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)p);
++
++	}
++
++	/* update privacy/security */
++	if (cap & BIT(4))
++		pbss_network->Privacy = 1;
++	else
++		pbss_network->Privacy = 0;
++
++	psecuritypriv->wpa_psk = 0;
++
++	/* wpa2 */
++	akm = 0;
++	gmcs = 0;
++	group_cipher = 0;
++	pairwise_cipher = 0;
++	psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_;
++	psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_;
++	psecuritypriv->akmp = 0;
++	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
++	if (p && ie_len > 0) {
++		if (rtw_parse_wpa2_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, &gmcs, &akm, &mfp_opt) == _SUCCESS) {
++			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
++			psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK;
++			psecuritypriv->dot8021xalg = 1;/* psk,  todo:802.1x */
++			psecuritypriv->wpa_psk |= BIT(1);
++
++			psecuritypriv->wpa2_group_cipher = group_cipher;
++			psecuritypriv->wpa2_pairwise_cipher = pairwise_cipher;
++			psecuritypriv->akmp = akm;
++
++#ifdef CONFIG_IOCTL_CFG80211
++			/**
++			 * Kernel < v5.x, the auth_type set as
++			 * NL80211_AUTHTYPE_AUTOMATIC in
++			 * cfg80211_rtw_start_ap(). if the AKM SAE in the RSN
++			 * IE, we have to update the auth_type for SAE in
++			 * rtw_check_beacon_data()
++			 */
++			if (CHECK_BIT(WLAN_AKM_TYPE_SAE, akm)) {
++				RTW_INFO("%s: Auth type as SAE\n", __func__);
++				psecuritypriv->auth_type = MLME_AUTHTYPE_SAE;
++				psecuritypriv->auth_alg = WLAN_AUTH_SAE;
++			}
++#endif /* CONFIG_IOCTL_CFG80211 */
++#if 0
++			switch (group_cipher) {
++			case WPA_CIPHER_NONE:
++				psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_;
++				break;
++			case WPA_CIPHER_WEP40:
++				psecuritypriv->wpa2_group_cipher = _WEP40_;
++				break;
++			case WPA_CIPHER_TKIP:
++				psecuritypriv->wpa2_group_cipher = _TKIP_;
++				break;
++			case WPA_CIPHER_CCMP:
++				psecuritypriv->wpa2_group_cipher = _AES_;
++				break;
++			case WPA_CIPHER_WEP104:
++				psecuritypriv->wpa2_group_cipher = _WEP104_;
++				break;
++			}
++
++			switch (pairwise_cipher) {
++			case WPA_CIPHER_NONE:
++				psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_;
++				break;
++			case WPA_CIPHER_WEP40:
++				psecuritypriv->wpa2_pairwise_cipher = _WEP40_;
++				break;
++			case WPA_CIPHER_TKIP:
++				psecuritypriv->wpa2_pairwise_cipher = _TKIP_;
++				break;
++			case WPA_CIPHER_CCMP:
++				psecuritypriv->wpa2_pairwise_cipher = _AES_;
++				break;
++			case WPA_CIPHER_WEP104:
++				psecuritypriv->wpa2_pairwise_cipher = _WEP104_;
++				break;
++			}
++#endif
++		}
++
++	}
++
++	/* wpa */
++	ie_len = 0;
++	group_cipher = 0;
++	pairwise_cipher = 0;
++	psecuritypriv->wpa_group_cipher = _NO_PRIVACY_;
++	psecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_;
++	for (p = ie + _BEACON_IE_OFFSET_; ; p += (ie_len + 2)) {
++		p = rtw_get_ie(p, _SSN_IE_1_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2)));
++		if ((p) && (_rtw_memcmp(p + 2, OUI1, 4))) {
++			if (rtw_parse_wpa_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {
++				psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
++				psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPAPSK;
++				psecuritypriv->dot8021xalg = 1;/* psk,  todo:802.1x */
++
++				psecuritypriv->wpa_psk |= BIT(0);
++
++				psecuritypriv->wpa_group_cipher = group_cipher;
++				psecuritypriv->wpa_pairwise_cipher = pairwise_cipher;
++
++#if 0
++				switch (group_cipher) {
++				case WPA_CIPHER_NONE:
++					psecuritypriv->wpa_group_cipher = _NO_PRIVACY_;
++					break;
++				case WPA_CIPHER_WEP40:
++					psecuritypriv->wpa_group_cipher = _WEP40_;
++					break;
++				case WPA_CIPHER_TKIP:
++					psecuritypriv->wpa_group_cipher = _TKIP_;
++					break;
++				case WPA_CIPHER_CCMP:
++					psecuritypriv->wpa_group_cipher = _AES_;
++					break;
++				case WPA_CIPHER_WEP104:
++					psecuritypriv->wpa_group_cipher = _WEP104_;
++					break;
++				}
++
++				switch (pairwise_cipher) {
++				case WPA_CIPHER_NONE:
++					psecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_;
++					break;
++				case WPA_CIPHER_WEP40:
++					psecuritypriv->wpa_pairwise_cipher = _WEP40_;
++					break;
++				case WPA_CIPHER_TKIP:
++					psecuritypriv->wpa_pairwise_cipher = _TKIP_;
++					break;
++				case WPA_CIPHER_CCMP:
++					psecuritypriv->wpa_pairwise_cipher = _AES_;
++					break;
++				case WPA_CIPHER_WEP104:
++					psecuritypriv->wpa_pairwise_cipher = _WEP104_;
++					break;
++				}
++#endif
++			}
++
++			break;
++
++		}
++
++		if ((p == NULL) || (ie_len == 0))
++			break;
++
++	}
++
++	if (mfp_opt == MFP_INVALID) {
++		RTW_INFO(FUNC_ADPT_FMT" invalid MFP setting\n", FUNC_ADPT_ARG(padapter));
++		return _FAIL;
++	}
++	psecuritypriv->mfp_opt = mfp_opt;
++
++	/* wmm */
++	ie_len = 0;
++	pmlmepriv->qospriv.qos_option = 0;
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(padapter))
++		pmlmepriv->qospriv.qos_option = 1;
++#endif
++	if (pregistrypriv->wmm_enable) {
++		for (p = ie + _BEACON_IE_OFFSET_; ; p += (ie_len + 2)) {
++			p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2)));
++			if ((p) && _rtw_memcmp(p + 2, WMM_PARA_IE, 6)) {
++				pmlmepriv->qospriv.qos_option = 1;
++
++				*(p + 8) |= BIT(7); /* QoS Info, support U-APSD */
++
++				/* disable all ACM bits since the WMM admission control is not supported */
++				*(p + 10) &= ~BIT(4); /* BE */
++				*(p + 14) &= ~BIT(4); /* BK */
++				*(p + 18) &= ~BIT(4); /* VI */
++				*(p + 22) &= ~BIT(4); /* VO */
++
++				WMM_param_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)p);
++
++				break;
++			}
++
++			if ((p == NULL) || (ie_len == 0))
++				break;
++		}
++	}
++#ifdef CONFIG_80211N_HT
++	if(padapter->registrypriv.ht_enable &&
++		is_supported_ht(padapter->registrypriv.wireless_mode)) {
++		/* parsing HT_CAP_IE */
++		p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
++		if (p && ie_len > 0) {
++			HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor = MAX_AMPDU_FACTOR_64K;
++			struct rtw_ieee80211_ht_cap *pht_cap = (struct rtw_ieee80211_ht_cap *)(p + 2);
++
++			if (0) {
++				RTW_INFO(FUNC_ADPT_FMT" HT_CAP_IE from upper layer:\n", FUNC_ADPT_ARG(padapter));
++				dump_ht_cap_ie_content(RTW_DBGDUMP, p + 2, ie_len);
++			}
++
++			pHT_caps_ie = p;
++
++			ht_cap = _TRUE;
++			network_type |= WIRELESS_11_24N;
++
++			rtw_ht_use_default_setting(padapter);
++
++			/* Update HT Capabilities Info field */
++			if (pmlmepriv->htpriv.sgi_20m == _FALSE)
++				pht_cap->cap_info &= ~(IEEE80211_HT_CAP_SGI_20);
++
++			if (pmlmepriv->htpriv.sgi_40m == _FALSE)
++				pht_cap->cap_info &= ~(IEEE80211_HT_CAP_SGI_40);
++
++			if (!TEST_FLAG(pmlmepriv->htpriv.ldpc_cap, LDPC_HT_ENABLE_RX))
++				pht_cap->cap_info &= ~(IEEE80211_HT_CAP_LDPC_CODING);
++
++			if (!TEST_FLAG(pmlmepriv->htpriv.stbc_cap, STBC_HT_ENABLE_TX))
++				pht_cap->cap_info &= ~(IEEE80211_HT_CAP_TX_STBC);
++
++			if (!TEST_FLAG(pmlmepriv->htpriv.stbc_cap, STBC_HT_ENABLE_RX))
++				pht_cap->cap_info &= ~(IEEE80211_HT_CAP_RX_STBC_3R);
++
++			/* Update A-MPDU Parameters field */
++			pht_cap->ampdu_params_info &= ~(IEEE80211_HT_CAP_AMPDU_FACTOR | IEEE80211_HT_CAP_AMPDU_DENSITY);
++
++			if ((psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_CCMP) ||
++				(psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_CCMP)) {
++				rtw_hal_get_def_var(padapter, HW_VAR_BEST_AMPDU_DENSITY, &best_ampdu_density);
++				pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & (best_ampdu_density << 2));
++			} else
++				pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & 0x00);
++
++			rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor);
++			pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_FACTOR & max_rx_ampdu_factor); /* set  Max Rx AMPDU size  to 64K */
++
++			_rtw_memcpy(&(pmlmeinfo->HT_caps), pht_cap, sizeof(struct HT_caps_element));
++
++			/* Update Supported MCS Set field */
++			{
++				u8 rx_nss = 0;
++				int i;
++
++				rx_nss = GET_HAL_RX_NSS(padapter);
++
++				/* RX MCS Bitmask */
++				switch (rx_nss) {
++				case 1:
++					set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_1R);
++					break;
++				case 2:
++					set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_2R);
++					break;
++				case 3:
++					set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_3R);
++					break;
++				case 4:
++					set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_4R);
++					break;
++				default:
++					RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", GET_HAL_RFPATH(padapter), rx_nss);
++				}
++				for (i = 0; i < 10; i++)
++					*(HT_CAP_ELE_RX_MCS_MAP(pht_cap) + i) &= padapter->mlmeextpriv.default_supported_mcs_set[i];
++			}
++
++#ifdef CONFIG_BEAMFORMING
++			/* Use registry value to enable HT Beamforming. */
++			/* ToDo: use configure file to set these capability. */
++			pht_cap->tx_BF_cap_info = 0;
++
++			/* HT Beamformer */
++			if (TEST_FLAG(pmlmepriv->htpriv.beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {
++				/* Transmit NDP Capable */
++				SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(pht_cap, 1);
++				/* Explicit Compressed Steering Capable */
++				SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pht_cap, 1);
++				/* Compressed Steering Number Antennas */
++				SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pht_cap, 1);
++				rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num);
++				SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pht_cap, rf_num);
++			}
++
++			/* HT Beamformee */
++			if (TEST_FLAG(pmlmepriv->htpriv.beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) {
++				/* Receive NDP Capable */
++				SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(pht_cap, 1);
++				/* Explicit Compressed Beamforming Feedback Capable */
++				SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pht_cap, 2);
++				rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);
++				SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pht_cap, rf_num);
++			}
++#endif /* CONFIG_BEAMFORMING */
++
++			_rtw_memcpy(&pmlmepriv->htpriv.ht_cap, p + 2, ie_len);
++
++			if (0) {
++				RTW_INFO(FUNC_ADPT_FMT" HT_CAP_IE driver masked:\n", FUNC_ADPT_ARG(padapter));
++				dump_ht_cap_ie_content(RTW_DBGDUMP, p + 2, ie_len);
++			}
++		}
++
++		/* parsing HT_INFO_IE */
++		p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
++		if (p && ie_len > 0) {
++			pHT_info_ie = p;
++			if (channel == 0)
++				pbss_network->Configuration.DSConfig = GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2);
++			else if (channel != GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2)) {
++				RTW_INFO(FUNC_ADPT_FMT" ch inconsistent, DSSS:%u, HT primary:%u\n"
++					, FUNC_ADPT_ARG(padapter), channel, GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2));
++			}
++		}
++	}
++#endif /* CONFIG_80211N_HT */
++	pmlmepriv->cur_network.network_type = network_type;
++
++#ifdef CONFIG_80211N_HT
++	pmlmepriv->htpriv.ht_option = _FALSE;
++
++	if ((psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_TKIP) ||
++	    (psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_TKIP)) {
++		/* todo: */
++		/* ht_cap = _FALSE; */
++	}
++
++	/* ht_cap	 */
++	if (padapter->registrypriv.ht_enable &&
++		is_supported_ht(padapter->registrypriv.wireless_mode) && ht_cap == _TRUE) {
++
++		pmlmepriv->htpriv.ht_option = _TRUE;
++		pmlmepriv->qospriv.qos_option = 1;
++
++		pmlmepriv->htpriv.ampdu_enable = pregistrypriv->ampdu_enable ? _TRUE : _FALSE;
++
++		HT_caps_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_caps_ie);
++
++		HT_info_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_info_ie);
++	}
++#endif
++
++#ifdef CONFIG_80211AC_VHT
++	pmlmepriv->ori_vht_en = 0;
++	pmlmepriv->vhtpriv.vht_option = _FALSE;
++
++	if (pmlmepriv->htpriv.ht_option == _TRUE
++		&& pbss_network->Configuration.DSConfig > 14
++		&& REGSTY_IS_11AC_ENABLE(pregistrypriv)
++		&& is_supported_vht(pregistrypriv->wireless_mode)
++		&& (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
++	) {
++		/* Parsing VHT CAP IE */
++		p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
++		if (p && ie_len > 0)
++			vht_cap = _TRUE;
++
++		/* Parsing VHT OPERATION IE */
++
++		if (vht_cap == _TRUE
++			&& MLME_IS_MESH(padapter) /* allow only mesh temporarily before VHT IE checking is ready */
++		) {
++			rtw_check_for_vht20(padapter, ie + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_);
++			pmlmepriv->ori_vht_en = 1;
++			pmlmepriv->vhtpriv.vht_option = _TRUE;
++		} else if (REGSTY_IS_11AC_AUTO(pregistrypriv)) {
++			rtw_vht_ies_detach(padapter, pbss_network);
++			rtw_vht_ies_attach(padapter, pbss_network);
++		}
++	}
++
++	if (pmlmepriv->vhtpriv.vht_option == _FALSE)
++		rtw_vht_ies_detach(padapter, pbss_network);
++#endif /* CONFIG_80211AC_VHT */
++
++#ifdef CONFIG_80211N_HT
++	if(padapter->registrypriv.ht_enable &&
++					is_supported_ht(padapter->registrypriv.wireless_mode) &&
++		pbss_network->Configuration.DSConfig <= 14 && padapter->registrypriv.wifi_spec == 1 &&
++		pbss_network->IELength + 10 <= MAX_IE_SZ) {
++		uint len = 0;
++
++		SET_EXT_CAPABILITY_ELE_BSS_COEXIST(pmlmepriv->ext_capab_ie_data, 1);
++		pmlmepriv->ext_capab_ie_len = 10;
++		rtw_set_ie(pbss_network->IEs + pbss_network->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len);
++		pbss_network->IELength += pmlmepriv->ext_capab_ie_len;
++	}
++#endif /* CONFIG_80211N_HT */
++
++	pbss_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pbss_network);
++
++	rtw_ies_get_chbw(pbss_network->IEs + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_
++		, &pmlmepriv->ori_ch, &pmlmepriv->ori_bw, &pmlmepriv->ori_offset, 1, 1);
++	rtw_warn_on(pmlmepriv->ori_ch == 0);
++
++	{
++		/* alloc sta_info for ap itself */
++
++		struct sta_info *sta;
++
++		sta = rtw_get_stainfo(&padapter->stapriv, pbss_network->MacAddress);
++		if (!sta) {
++			sta = rtw_alloc_stainfo(&padapter->stapriv, pbss_network->MacAddress);
++			if (sta == NULL)
++				return _FAIL;
++		}
++	}
++
++	rtw_startbss_cmd(padapter, RTW_CMDF_WAIT_ACK);
++	{
++		int sk_band = RTW_GET_SCAN_BAND_SKIP(padapter);
++
++		if (sk_band)
++			RTW_CLR_SCAN_BAND_SKIP(padapter, sk_band);
++	}
++
++	rtw_indicate_connect(padapter);
++
++	pmlmepriv->cur_network.join_res = _TRUE;/* for check if already set beacon */
++
++	/* update bc/mc sta_info */
++	/* update_bmc_sta(padapter); */
++
++	return ret;
++
++}
++
++#if CONFIG_RTW_MACADDR_ACL
++void rtw_macaddr_acl_init(_adapter *adapter, u8 period)
++{
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct wlan_acl_pool *acl;
++	_queue *acl_node_q;
++	int i;
++	_irqL irqL;
++
++	if (period >= RTW_ACL_PERIOD_NUM) {
++		rtw_warn_on(1);
++		return;
++	}
++
++	acl = &stapriv->acl_list[period];
++	acl_node_q = &acl->acl_node_q;
++
++	_rtw_spinlock_init(&(acl_node_q->lock));
++
++	_enter_critical_bh(&(acl_node_q->lock), &irqL);
++	_rtw_init_listhead(&(acl_node_q->queue));
++	acl->num = 0;
++	acl->mode = RTW_ACL_MODE_DISABLED;
++	for (i = 0; i < NUM_ACL; i++) {
++		_rtw_init_listhead(&acl->aclnode[i].list);
++		acl->aclnode[i].valid = _FALSE;
++	}
++	_exit_critical_bh(&(acl_node_q->lock), &irqL);
++}
++
++static void _rtw_macaddr_acl_deinit(_adapter *adapter, u8 period, bool clear_only)
++{
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct wlan_acl_pool *acl;
++	_queue *acl_node_q;
++	_irqL irqL;
++	_list *head, *list;
++	struct rtw_wlan_acl_node *acl_node;
++
++	if (period >= RTW_ACL_PERIOD_NUM) {
++		rtw_warn_on(1);
++		return;
++	}
++
++	acl = &stapriv->acl_list[period];
++	acl_node_q = &acl->acl_node_q;
++
++	_enter_critical_bh(&(acl_node_q->lock), &irqL);
++	head = get_list_head(acl_node_q);
++	list = get_next(head);
++	while (rtw_end_of_queue_search(head, list) == _FALSE) {
++		acl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list);
++		list = get_next(list);
++
++		if (acl_node->valid == _TRUE) {
++			acl_node->valid = _FALSE;
++			rtw_list_delete(&acl_node->list);
++			acl->num--;
++		}
++	}
++	_exit_critical_bh(&(acl_node_q->lock), &irqL);
++
++	if (!clear_only)
++		_rtw_spinlock_free(&(acl_node_q->lock));
++
++	rtw_warn_on(acl->num);
++	acl->mode = RTW_ACL_MODE_DISABLED;
++}
++
++void rtw_macaddr_acl_deinit(_adapter *adapter, u8 period)
++{
++	_rtw_macaddr_acl_deinit(adapter, period, 0);
++}
++
++void rtw_macaddr_acl_clear(_adapter *adapter, u8 period)
++{
++	_rtw_macaddr_acl_deinit(adapter, period, 1);
++}
++
++void rtw_set_macaddr_acl(_adapter *adapter, u8 period, int mode)
++{
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct wlan_acl_pool *acl;
++
++	if (period >= RTW_ACL_PERIOD_NUM) {
++		rtw_warn_on(1);
++		return;
++	}
++
++	acl = &stapriv->acl_list[period];
++
++	RTW_INFO(FUNC_ADPT_FMT" p=%u, mode=%d\n"
++		, FUNC_ADPT_ARG(adapter), period, mode);
++
++	acl->mode = mode;
++}
++
++int rtw_acl_add_sta(_adapter *adapter, u8 period, const u8 *addr)
++{
++	_irqL irqL;
++	_list *list, *head;
++	u8 existed = 0;
++	int i = -1, ret = 0;
++	struct rtw_wlan_acl_node *acl_node;
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct wlan_acl_pool *acl;
++	_queue *acl_node_q;
++
++	if (period >= RTW_ACL_PERIOD_NUM) {
++		rtw_warn_on(1);
++		ret = -1;
++		goto exit;
++	}
++
++	acl = &stapriv->acl_list[period];
++	acl_node_q = &acl->acl_node_q;
++
++	_enter_critical_bh(&(acl_node_q->lock), &irqL);
++
++	head = get_list_head(acl_node_q);
++	list = get_next(head);
++
++	/* search for existed entry */
++	while (rtw_end_of_queue_search(head, list) == _FALSE) {
++		acl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list);
++		list = get_next(list);
++
++		if (_rtw_memcmp(acl_node->addr, addr, ETH_ALEN)) {
++			if (acl_node->valid == _TRUE) {
++				existed = 1;
++				break;
++			}
++		}
++	}
++	if (existed)
++		goto release_lock;
++
++	if (acl->num >= NUM_ACL)
++		goto release_lock;
++
++	/* find empty one and use */
++	for (i = 0; i < NUM_ACL; i++) {
++
++		acl_node = &acl->aclnode[i];
++		if (acl_node->valid == _FALSE) {
++
++			_rtw_init_listhead(&acl_node->list);
++			_rtw_memcpy(acl_node->addr, addr, ETH_ALEN);
++			acl_node->valid = _TRUE;
++
++			rtw_list_insert_tail(&acl_node->list, get_list_head(acl_node_q));
++			acl->num++;
++			break;
++		}
++	}
++
++release_lock:
++	_exit_critical_bh(&(acl_node_q->lock), &irqL);
++
++	if (!existed && (i < 0 || i >= NUM_ACL))
++		ret = -1;
++
++	RTW_INFO(FUNC_ADPT_FMT" p=%u "MAC_FMT" %s (acl_num=%d)\n"
++		 , FUNC_ADPT_ARG(adapter), period, MAC_ARG(addr)
++		, (existed ? "existed" : ((i < 0 || i >= NUM_ACL) ? "no room" : "added"))
++		 , acl->num);
++exit:
++	return ret;
++}
++
++int rtw_acl_remove_sta(_adapter *adapter, u8 period, const u8 *addr)
++{
++	_irqL irqL;
++	_list *list, *head;
++	int ret = 0;
++	struct rtw_wlan_acl_node *acl_node;
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct wlan_acl_pool *acl;
++	_queue	*acl_node_q;
++	u8 is_baddr = is_broadcast_mac_addr(addr);
++	u8 match = 0;
++
++	if (period >= RTW_ACL_PERIOD_NUM) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	acl = &stapriv->acl_list[period];
++	acl_node_q = &acl->acl_node_q;
++
++	_enter_critical_bh(&(acl_node_q->lock), &irqL);
++
++	head = get_list_head(acl_node_q);
++	list = get_next(head);
++
++	while (rtw_end_of_queue_search(head, list) == _FALSE) {
++		acl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list);
++		list = get_next(list);
++
++		if (is_baddr || _rtw_memcmp(acl_node->addr, addr, ETH_ALEN)) {
++			if (acl_node->valid == _TRUE) {
++				acl_node->valid = _FALSE;
++				rtw_list_delete(&acl_node->list);
++				acl->num--;
++				match = 1;
++			}
++		}
++	}
++
++	_exit_critical_bh(&(acl_node_q->lock), &irqL);
++
++	RTW_INFO(FUNC_ADPT_FMT" p=%u "MAC_FMT" %s (acl_num=%d)\n"
++		 , FUNC_ADPT_ARG(adapter), period, MAC_ARG(addr)
++		 , is_baddr ? "clear all" : (match ? "match" : "no found")
++		 , acl->num);
++
++exit:
++	return ret;
++}
++#endif /* CONFIG_RTW_MACADDR_ACL */
++
++u8 rtw_ap_set_sta_key(_adapter *adapter, const u8 *addr, u8 alg, const u8 *key, u8 keyid, u8 gk)
++{
++	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
++	struct cmd_obj *cmd;
++	struct set_stakey_parm *param;
++	u8	res = _SUCCESS;
++
++	cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (cmd == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	param = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm));
++	if (param == NULL) {
++		rtw_mfree((u8 *) cmd, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	init_h2fwcmd_w_parm_no_rsp(cmd, param, CMD_SET_STAKEY);
++
++	_rtw_memcpy(param->addr, addr, ETH_ALEN);
++	param->algorithm = alg;
++	param->keyid = keyid;
++	if (!!(alg & _SEC_TYPE_256_))
++		_rtw_memcpy(param->key, key, 32);
++	else
++		_rtw_memcpy(param->key, key, 16);
++	param->gk = gk;
++
++	res = rtw_enqueue_cmd(cmdpriv, cmd);
++
++exit:
++	return res;
++}
++
++u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta)
++{
++	return rtw_ap_set_sta_key(padapter
++		, psta->cmn.mac_addr
++		, psta->dot118021XPrivacy
++		, psta->dot118021x_UncstKey.skey
++		, 0
++		, 0
++	);
++}
++
++static int rtw_ap_set_key(_adapter *padapter, u8 *key, u8 alg, int keyid, u8 set_tx)
++{
++	u8 keylen;
++	struct cmd_obj *pcmd;
++	struct setkey_parm *psetkeyparm;
++	struct cmd_priv	*pcmdpriv = &(padapter->cmdpriv);
++	int res = _SUCCESS;
++
++	/* RTW_INFO("%s\n", __FUNCTION__); */
++
++	pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (pcmd == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++	psetkeyparm = (struct setkey_parm *)rtw_zmalloc(sizeof(struct setkey_parm));
++	if (psetkeyparm == NULL) {
++		rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	_rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm));
++
++	psetkeyparm->keyid = (u8)keyid;
++	if (is_wep_enc(alg))
++		padapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid);
++
++	psetkeyparm->algorithm = alg;
++
++	psetkeyparm->set_tx = set_tx;
++
++	switch (alg) {
++	case _WEP40_:
++		keylen = 5;
++		break;
++	case _WEP104_:
++		keylen = 13;
++		break;
++	case _GCMP_256_:
++	case _CCMP_256_:
++		keylen = 32;
++		break;
++	case _TKIP_:
++	case _TKIP_WTMIC_:
++	case _AES_:
++	case _GCMP_:
++	default:
++		keylen = 16;
++	}
++
++	_rtw_memcpy(&(psetkeyparm->key[0]), key, keylen);
++
++	pcmd->cmdcode = CMD_SET_KEY; /*_SetKey_CMD_;*/
++	pcmd->parmbuf = (u8 *)psetkeyparm;
++	pcmd->cmdsz = (sizeof(struct setkey_parm));
++	pcmd->rsp = NULL;
++	pcmd->rspsz = 0;
++
++
++	_rtw_init_listhead(&pcmd->list);
++
++	res = rtw_enqueue_cmd(pcmdpriv, pcmd);
++
++exit:
++
++	return res;
++}
++
++int rtw_ap_set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid)
++{
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	return rtw_ap_set_key(padapter, key, alg, keyid, 1);
++}
++
++int rtw_ap_set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid, u8 set_tx)
++{
++	u8 alg;
++
++	switch (keylen) {
++	case 5:
++		alg = _WEP40_;
++		break;
++	case 13:
++		alg = _WEP104_;
++		break;
++	default:
++		alg = _NO_PRIVACY_;
++	}
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	return rtw_ap_set_key(padapter, key, alg, keyid, set_tx);
++}
++
++u8 rtw_ap_bmc_frames_hdl(_adapter *padapter)
++{
++#define HIQ_XMIT_COUNTS (6)
++	_irqL irqL;
++	struct sta_info *psta_bmc;
++	_list	*xmitframe_plist, *xmitframe_phead;
++	struct xmit_frame *pxmitframe = NULL;
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	struct sta_priv  *pstapriv = &padapter->stapriv;
++	bool update_tim = _FALSE;
++
++
++	if (padapter->registrypriv.wifi_spec != 1)
++		return H2C_SUCCESS;
++
++
++	psta_bmc = rtw_get_bcmc_stainfo(padapter);
++	if (!psta_bmc)
++		return H2C_SUCCESS;
++
++
++	_enter_critical_bh(&pxmitpriv->lock, &irqL);
++
++	if ((rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) && (psta_bmc->sleepq_len > 0)) {
++		int tx_counts = 0;
++
++		_update_beacon(padapter, _TIM_IE_, NULL, _FALSE, 0, "update TIM with TIB=1");
++
++		RTW_INFO("sleepq_len of bmc_sta = %d\n", psta_bmc->sleepq_len);
++
++		xmitframe_phead = get_list_head(&psta_bmc->sleep_q);
++		xmitframe_plist = get_next(xmitframe_phead);
++
++		while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
++			pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
++
++			xmitframe_plist = get_next(xmitframe_plist);
++
++			rtw_list_delete(&pxmitframe->list);
++
++			psta_bmc->sleepq_len--;
++			tx_counts++;
++
++			if (psta_bmc->sleepq_len > 0)
++				pxmitframe->attrib.mdata = 1;
++			else
++				pxmitframe->attrib.mdata = 0;
++
++			if (tx_counts == HIQ_XMIT_COUNTS)
++				pxmitframe->attrib.mdata = 0;
++
++			pxmitframe->attrib.triggered = 1;
++
++			if (xmitframe_hiq_filter(pxmitframe) == _TRUE)
++				pxmitframe->attrib.qsel = QSLT_HIGH;/*HIQ*/
++
++			rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
++
++			if (tx_counts == HIQ_XMIT_COUNTS)
++				break;
++
++		}
++
++	} else {
++		if (psta_bmc->sleepq_len == 0) {
++
++			/*RTW_INFO("sleepq_len of bmc_sta = %d\n", psta_bmc->sleepq_len);*/
++
++			if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0))
++				update_tim = _TRUE;
++
++			rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0);
++			rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0);
++
++			if (update_tim == _TRUE) {
++				RTW_INFO("clear TIB\n");
++				_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, "bmc sleepq and HIQ empty");
++			}
++		}
++	}
++
++	_exit_critical_bh(&pxmitpriv->lock, &irqL);
++
++#if 0
++	/* HIQ Check */
++	rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty);
++
++	while (_FALSE == empty && rtw_get_passing_time_ms(start) < 3000) {
++		rtw_msleep_os(100);
++		rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty);
++	}
++
++
++	printk("check if hiq empty=%d\n", empty);
++#endif
++
++	return H2C_SUCCESS;
++}
++
++#ifdef CONFIG_NATIVEAP_MLME
++
++static void associated_stainfo_update(_adapter *padapter, struct sta_info *psta, u32 sta_info_type)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++	RTW_INFO("%s: "MAC_FMT", updated_type=0x%x\n", __func__, MAC_ARG(psta->cmn.mac_addr), sta_info_type);
++#ifdef CONFIG_80211N_HT
++	if (sta_info_type & STA_INFO_UPDATE_BW) {
++
++		if ((psta->flags & WLAN_STA_HT) && !psta->ht_20mhz_set) {
++			if (pmlmepriv->sw_to_20mhz) {
++				psta->cmn.bw_mode = CHANNEL_WIDTH_20;
++				/*psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;*/
++				psta->htpriv.sgi_40m = _FALSE;
++			} else {
++				/*TODO: Switch back to 40MHZ?80MHZ*/
++			}
++		}
++	}
++#endif /* CONFIG_80211N_HT */
++	/*
++		if (sta_info_type & STA_INFO_UPDATE_RATE) {
++
++		}
++	*/
++
++	if (sta_info_type & STA_INFO_UPDATE_PROTECTION_MODE)
++		VCS_update(padapter, psta);
++
++	/*
++		if (sta_info_type & STA_INFO_UPDATE_CAP) {
++
++		}
++
++		if (sta_info_type & STA_INFO_UPDATE_HT_CAP) {
++
++		}
++
++		if (sta_info_type & STA_INFO_UPDATE_VHT_CAP) {
++
++		}
++	*/
++
++}
++
++static void update_bcn_ext_capab_ie(_adapter *padapter)
++{
++	sint ie_len = 0;
++	unsigned char	*pbuf;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
++	u8 *ie = pnetwork->IEs;
++	u8 null_extcap_data[8] = {0};
++
++	pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_CAP_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
++	if (pbuf && ie_len > 0)
++		rtw_remove_bcn_ie(padapter, pnetwork, _EXT_CAP_IE_);
++
++	if ((pmlmepriv->ext_capab_ie_len > 0) &&
++	    (_rtw_memcmp(pmlmepriv->ext_capab_ie_data, null_extcap_data, sizeof(null_extcap_data)) == _FALSE))
++		rtw_add_bcn_ie(padapter, pnetwork, _EXT_CAP_IE_, pmlmepriv->ext_capab_ie_data, pmlmepriv->ext_capab_ie_len);
++
++}
++
++static void update_bcn_erpinfo_ie(_adapter *padapter)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
++	unsigned char *p, *ie = pnetwork->IEs;
++	u32 len = 0;
++
++	RTW_INFO("%s, ERP_enable=%d\n", __FUNCTION__, pmlmeinfo->ERP_enable);
++
++	if (!pmlmeinfo->ERP_enable)
++		return;
++
++	/* parsing ERP_IE */
++	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
++	if (p && len > 0) {
++		PNDIS_802_11_VARIABLE_IEs pIE = (PNDIS_802_11_VARIABLE_IEs)p;
++
++		if (pmlmepriv->num_sta_non_erp == 1)
++			pIE->data[0] |= RTW_ERP_INFO_NON_ERP_PRESENT | RTW_ERP_INFO_USE_PROTECTION;
++		else
++			pIE->data[0] &= ~(RTW_ERP_INFO_NON_ERP_PRESENT | RTW_ERP_INFO_USE_PROTECTION);
++
++		if (pmlmepriv->num_sta_no_short_preamble > 0)
++			pIE->data[0] |= RTW_ERP_INFO_BARKER_PREAMBLE_MODE;
++		else
++			pIE->data[0] &= ~(RTW_ERP_INFO_BARKER_PREAMBLE_MODE);
++
++		ERP_IE_handler(padapter, pIE);
++	}
++
++}
++
++static void update_bcn_htcap_ie(_adapter *padapter)
++{
++	RTW_INFO("%s\n", __FUNCTION__);
++
++}
++
++static void update_bcn_htinfo_ie(_adapter *padapter)
++{
++#ifdef CONFIG_80211N_HT
++	/*
++	u8 beacon_updated = _FALSE;
++	u32 sta_info_update_type = STA_INFO_UPDATE_NONE;
++	*/
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
++	unsigned char *p, *ie = pnetwork->IEs;
++	u32 len = 0;
++
++	if (pmlmepriv->htpriv.ht_option == _FALSE)
++		return;
++
++	if (pmlmeinfo->HT_info_enable != 1)
++		return;
++
++
++	RTW_INFO("%s current operation mode=0x%X\n",
++		 __FUNCTION__, pmlmepriv->ht_op_mode);
++
++	RTW_INFO("num_sta_40mhz_intolerant(%d), 20mhz_width_req(%d), intolerant_ch_rpt(%d), olbc(%d)\n",
++		pmlmepriv->num_sta_40mhz_intolerant, pmlmepriv->ht_20mhz_width_req, pmlmepriv->ht_intolerant_ch_reported, ATOMIC_READ(&pmlmepriv->olbc));
++
++	/*parsing HT_INFO_IE, currently only update ht_op_mode - pht_info->infos[1] & pht_info->infos[2] for wifi logo test*/
++	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
++	if (p && len > 0) {
++		struct HT_info_element *pht_info = NULL;
++
++		pht_info = (struct HT_info_element *)(p + 2);
++
++		/* for STA Channel Width/Secondary Channel Offset*/
++		if ((pmlmepriv->sw_to_20mhz == 0) && (pmlmeext->cur_channel <= 14)) {
++			if ((pmlmepriv->num_sta_40mhz_intolerant > 0) || (pmlmepriv->ht_20mhz_width_req == _TRUE)
++			    || (pmlmepriv->ht_intolerant_ch_reported == _TRUE) || (ATOMIC_READ(&pmlmepriv->olbc) == _TRUE)) {
++				SET_HT_OP_ELE_2ND_CHL_OFFSET(pht_info, 0);
++				SET_HT_OP_ELE_STA_CHL_WIDTH(pht_info, 0);
++
++				pmlmepriv->sw_to_20mhz = 1;
++				/*
++				sta_info_update_type |= STA_INFO_UPDATE_BW;
++				beacon_updated = _TRUE;
++				*/
++
++				RTW_INFO("%s:switching to 20Mhz\n", __FUNCTION__);
++
++				/*TODO : cur_bwmode/cur_ch_offset switches to 20Mhz*/
++			}
++		} else {
++
++			if ((pmlmepriv->num_sta_40mhz_intolerant == 0) && (pmlmepriv->ht_20mhz_width_req == _FALSE)
++			    && (pmlmepriv->ht_intolerant_ch_reported == _FALSE) && (ATOMIC_READ(&pmlmepriv->olbc) == _FALSE)) {
++
++				if (pmlmeext->cur_bwmode >= CHANNEL_WIDTH_40) {
++
++					SET_HT_OP_ELE_STA_CHL_WIDTH(pht_info, 1);
++
++					SET_HT_OP_ELE_2ND_CHL_OFFSET(pht_info,
++						(pmlmeext->cur_ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) ?
++						HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE : HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW);
++
++					pmlmepriv->sw_to_20mhz = 0;
++					/*
++					sta_info_update_type |= STA_INFO_UPDATE_BW;
++					beacon_updated = _TRUE;
++					*/
++
++					RTW_INFO("%s:switching back to 40Mhz\n", __FUNCTION__);
++				}
++			}
++		}
++
++		/* to update  ht_op_mode*/
++		*(u16 *)(pht_info->infos + 1) = cpu_to_le16(pmlmepriv->ht_op_mode);
++
++	}
++
++	/*associated_clients_update(padapter, beacon_updated, sta_info_update_type);*/
++#endif /* CONFIG_80211N_HT */
++}
++
++static void update_bcn_rsn_ie(_adapter *padapter)
++{
++	RTW_INFO("%s\n", __FUNCTION__);
++
++}
++
++static void update_bcn_wpa_ie(_adapter *padapter)
++{
++	RTW_INFO("%s\n", __FUNCTION__);
++
++}
++
++static void update_bcn_wmm_ie(_adapter *padapter)
++{
++	RTW_INFO("%s\n", __FUNCTION__);
++
++}
++
++static void update_bcn_wps_ie(_adapter *padapter)
++{
++	u8 *pwps_ie = NULL, *pwps_ie_src, *premainder_ie, *pbackup_remainder_ie = NULL;
++	uint wps_ielen = 0, wps_offset, remainder_ielen;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
++	unsigned char *ie = pnetwork->IEs;
++	u32 ielen = pnetwork->IELength;
++
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	pwps_ie = rtw_get_wps_ie(ie + _FIXED_IE_LENGTH_, ielen - _FIXED_IE_LENGTH_, NULL, &wps_ielen);
++
++	if (pwps_ie == NULL || wps_ielen == 0)
++		return;
++
++	pwps_ie_src = pmlmepriv->wps_beacon_ie;
++	if (pwps_ie_src == NULL)
++		return;
++
++	wps_offset = (uint)(pwps_ie - ie);
++
++	premainder_ie = pwps_ie + wps_ielen;
++
++	remainder_ielen = ielen - wps_offset - wps_ielen;
++
++	if (remainder_ielen > 0) {
++		pbackup_remainder_ie = rtw_malloc(remainder_ielen);
++		if (pbackup_remainder_ie)
++			_rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);
++	}
++
++	wps_ielen = (uint)pwps_ie_src[1];/* to get ie data len */
++	if ((wps_offset + wps_ielen + 2 + remainder_ielen) <= MAX_IE_SZ) {
++		_rtw_memcpy(pwps_ie, pwps_ie_src, wps_ielen + 2);
++		pwps_ie += (wps_ielen + 2);
++
++		if (pbackup_remainder_ie)
++			_rtw_memcpy(pwps_ie, pbackup_remainder_ie, remainder_ielen);
++
++		/* update IELength */
++		pnetwork->IELength = wps_offset + (wps_ielen + 2) + remainder_ielen;
++	}
++
++	if (pbackup_remainder_ie)
++		rtw_mfree(pbackup_remainder_ie, remainder_ielen);
++
++	/* deal with the case without set_tx_beacon_cmd() in update_beacon() */
++#if defined(CONFIG_INTERRUPT_BASED_TXBCN) || defined(CONFIG_PCI_HCI)
++	if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
++		u8 sr = 0;
++		rtw_get_wps_attr_content(pwps_ie_src,  wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);
++
++		if (sr) {
++			set_fwstate(pmlmepriv, WIFI_UNDER_WPS);
++			RTW_INFO("%s, set WIFI_UNDER_WPS\n", __func__);
++		} else {
++			clr_fwstate(pmlmepriv, WIFI_UNDER_WPS);
++			RTW_INFO("%s, clr WIFI_UNDER_WPS\n", __func__);
++		}
++	}
++#endif
++}
++
++static void update_bcn_p2p_ie(_adapter *padapter)
++{
++
++}
++
++static void update_bcn_vendor_spec_ie(_adapter *padapter, u8 *oui)
++{
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	if (_rtw_memcmp(RTW_WPA_OUI, oui, 4))
++		update_bcn_wpa_ie(padapter);
++	else if (_rtw_memcmp(WMM_OUI, oui, 4))
++		update_bcn_wmm_ie(padapter);
++	else if (_rtw_memcmp(WPS_OUI, oui, 4))
++		update_bcn_wps_ie(padapter);
++	else if (_rtw_memcmp(P2P_OUI, oui, 4))
++		update_bcn_p2p_ie(padapter);
++	else
++		RTW_INFO("unknown OUI type!\n");
++
++
++}
++
++void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, u8 flags, const char *tag)
++{
++	_irqL irqL;
++	struct mlme_priv *pmlmepriv;
++	struct mlme_ext_priv *pmlmeext;
++	bool updated = 1; /* treat as upadated by default */
++
++	if (!padapter)
++		return;
++
++	pmlmepriv = &(padapter->mlmepriv);
++	pmlmeext = &(padapter->mlmeextpriv);
++
++	if (pmlmeext->bstart_bss == _FALSE)
++		return;
++
++	_enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
++
++	switch (ie_id) {
++	case _TIM_IE_:
++		update_BCNTIM(padapter);
++		break;
++
++	case _ERPINFO_IE_:
++		update_bcn_erpinfo_ie(padapter);
++		break;
++
++	case _HT_CAPABILITY_IE_:
++		update_bcn_htcap_ie(padapter);
++		break;
++
++	case _RSN_IE_2_:
++		update_bcn_rsn_ie(padapter);
++		break;
++
++	case _HT_ADD_INFO_IE_:
++		update_bcn_htinfo_ie(padapter);
++		break;
++
++	case _EXT_CAP_IE_:
++		update_bcn_ext_capab_ie(padapter);
++		break;
++
++#ifdef CONFIG_RTW_MESH
++	case WLAN_EID_MESH_CONFIG:
++		updated = rtw_mesh_update_bss_peering_status(padapter, &(pmlmeext->mlmext_info.network));
++		updated |= rtw_mesh_update_bss_formation_info(padapter, &(pmlmeext->mlmext_info.network));
++		updated |= rtw_mesh_update_bss_forwarding_state(padapter, &(pmlmeext->mlmext_info.network));
++		break;
++#endif
++
++	case _VENDOR_SPECIFIC_IE_:
++		update_bcn_vendor_spec_ie(padapter, oui);
++		break;
++
++	case 0xFF:
++	default:
++		break;
++	}
++
++	if (updated)
++		pmlmepriv->update_bcn = _TRUE;
++
++	_exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
++
++#ifndef CONFIG_INTERRUPT_BASED_TXBCN
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_PCI_BCN_POLLING)
++	if (tx && updated) {
++		/* send_beacon(padapter); */ /* send_beacon must execute on TSR level */
++		if (0)
++			RTW_INFO(FUNC_ADPT_FMT" ie_id:%u - %s\n", FUNC_ADPT_ARG(padapter), ie_id, tag);
++		if(flags == RTW_CMDF_WAIT_ACK)
++			set_tx_beacon_cmd(padapter, RTW_CMDF_WAIT_ACK);
++		else
++			set_tx_beacon_cmd(padapter, 0);
++	}
++#else
++	{
++		/* PCI will issue beacon when BCN interrupt occurs.		 */
++	}
++#endif
++#endif /* !CONFIG_INTERRUPT_BASED_TXBCN */
++}
++
++#ifdef CONFIG_80211N_HT
++
++void rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_len)
++{
++	struct sta_info *psta;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	u8 beacon_updated = _FALSE;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
++	uint frame_body_len = frame_len - sizeof(struct rtw_ieee80211_hdr_3addr);
++	u8 category, action;
++
++	psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
++	if (psta == NULL)
++		return;
++
++
++	category = frame_body[0];
++	action = frame_body[1];
++
++	if (frame_body_len > 0) {
++		if ((frame_body[2] == EID_BSSCoexistence) && (frame_body[3] > 0)) {
++			u8 ie_data = frame_body[4];
++
++			if (ie_data & RTW_WLAN_20_40_BSS_COEX_40MHZ_INTOL) {
++				if (psta->ht_40mhz_intolerant == 0) {
++					psta->ht_40mhz_intolerant = 1;
++					pmlmepriv->num_sta_40mhz_intolerant++;
++					beacon_updated = _TRUE;
++				}
++			} else if (ie_data & RTW_WLAN_20_40_BSS_COEX_20MHZ_WIDTH_REQ)	{
++				if (pmlmepriv->ht_20mhz_width_req == _FALSE) {
++					pmlmepriv->ht_20mhz_width_req = _TRUE;
++					beacon_updated = _TRUE;
++				}
++			} else
++				beacon_updated = _FALSE;
++		}
++	}
++
++	if (frame_body_len > 8) {
++		/* if EID_BSSIntolerantChlReport ie exists */
++		if ((frame_body[5] == EID_BSSIntolerantChlReport) && (frame_body[6] > 0)) {
++			/*todo:*/
++			if (pmlmepriv->ht_intolerant_ch_reported == _FALSE) {
++				pmlmepriv->ht_intolerant_ch_reported = _TRUE;
++				beacon_updated = _TRUE;
++			}
++		}
++	}
++
++	if (beacon_updated) {
++
++		update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE, 0);
++
++		associated_stainfo_update(padapter, psta, STA_INFO_UPDATE_BW);
++	}
++
++
++
++}
++
++void rtw_process_ht_action_smps(_adapter *padapter, u8 *ta, u8 ctrl_field)
++{
++	u8 e_field, m_field;
++	struct sta_info *psta;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++
++	psta = rtw_get_stainfo(pstapriv, ta);
++	if (psta == NULL)
++		return;
++
++	e_field = (ctrl_field & BIT(0)) ? 1 : 0; /*SM Power Save Enabled*/
++	m_field = (ctrl_field & BIT(1)) ? 1 : 0; /*SM Mode, 0:static SMPS, 1:dynamic SMPS*/
++
++	if (e_field) {
++		if (m_field) { /*mode*/
++			psta->htpriv.smps_cap = WLAN_HT_CAP_SM_PS_DYNAMIC;
++			RTW_ERR("Don't support dynamic SMPS\n");
++		}
++		else
++			psta->htpriv.smps_cap = WLAN_HT_CAP_SM_PS_STATIC;
++	} else {
++		/*disable*/
++		psta->htpriv.smps_cap = WLAN_HT_CAP_SM_PS_DISABLED;
++	}
++
++	if (psta->htpriv.smps_cap != WLAN_HT_CAP_SM_PS_DYNAMIC)
++		rtw_ssmps_wk_cmd(padapter, psta, e_field, 1);
++}
++
++/*
++op_mode
++Set to 0 (HT pure) under the followign conditions
++	- all STAs in the BSS are 20/40 MHz HT in 20/40 MHz BSS or
++	- all STAs in the BSS are 20 MHz HT in 20 MHz BSS
++Set to 1 (HT non-member protection) if there may be non-HT STAs
++	in both the primary and the secondary channel
++Set to 2 if only HT STAs are associated in BSS,
++	however and at least one 20 MHz HT STA is associated
++Set to 3 (HT mixed mode) when one or more non-HT STAs are associated
++	(currently non-GF HT station is considered as non-HT STA also)
++*/
++int rtw_ht_operation_update(_adapter *padapter)
++{
++	u16 cur_op_mode, new_op_mode;
++	int op_mode_changes = 0;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct ht_priv	*phtpriv_ap = &pmlmepriv->htpriv;
++
++	if (pmlmepriv->htpriv.ht_option == _FALSE)
++		return 0;
++
++	/*if (!iface->conf->ieee80211n || iface->conf->ht_op_mode_fixed)
++		return 0;*/
++
++	RTW_INFO("%s current operation mode=0x%X\n",
++		 __FUNCTION__, pmlmepriv->ht_op_mode);
++
++	if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)
++	    && pmlmepriv->num_sta_ht_no_gf) {
++		pmlmepriv->ht_op_mode |=
++			HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT;
++		op_mode_changes++;
++	} else if ((pmlmepriv->ht_op_mode &
++		    HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT) &&
++		   pmlmepriv->num_sta_ht_no_gf == 0) {
++		pmlmepriv->ht_op_mode &=
++			~HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT;
++		op_mode_changes++;
++	}
++
++	if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) &&
++	    (pmlmepriv->num_sta_no_ht || ATOMIC_READ(&pmlmepriv->olbc_ht))) {
++		pmlmepriv->ht_op_mode |= HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT;
++		op_mode_changes++;
++	} else if ((pmlmepriv->ht_op_mode &
++		    HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) &&
++		   (pmlmepriv->num_sta_no_ht == 0 && !ATOMIC_READ(&pmlmepriv->olbc_ht))) {
++		pmlmepriv->ht_op_mode &=
++			~HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT;
++		op_mode_changes++;
++	}
++
++	/* Note: currently we switch to the MIXED op mode if HT non-greenfield
++	 * station is associated. Probably it's a theoretical case, since
++	 * it looks like all known HT STAs support greenfield.
++	 */
++	new_op_mode = 0;
++	if (pmlmepriv->num_sta_no_ht /*||
++	    (pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/)
++		new_op_mode = OP_MODE_MIXED;
++	else if ((phtpriv_ap->ht_cap.cap_info & IEEE80211_HT_CAP_SUP_WIDTH)
++		 && pmlmepriv->num_sta_ht_20mhz)
++		new_op_mode = OP_MODE_20MHZ_HT_STA_ASSOCED;
++	else if (ATOMIC_READ(&pmlmepriv->olbc_ht))
++		new_op_mode = OP_MODE_MAY_BE_LEGACY_STAS;
++	else
++		new_op_mode = OP_MODE_PURE;
++
++	cur_op_mode = pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_OP_MODE_MASK;
++	if (cur_op_mode != new_op_mode) {
++		pmlmepriv->ht_op_mode &= ~HT_INFO_OPERATION_MODE_OP_MODE_MASK;
++		pmlmepriv->ht_op_mode |= new_op_mode;
++		op_mode_changes++;
++	}
++
++	RTW_INFO("%s new operation mode=0x%X changes=%d\n",
++		 __FUNCTION__, pmlmepriv->ht_op_mode, op_mode_changes);
++
++	return op_mode_changes;
++
++}
++
++#endif /* CONFIG_80211N_HT */
++
++void associated_clients_update(_adapter *padapter, u8 updated, u32 sta_info_type)
++{
++	/* update associcated stations cap. */
++	if (updated == _TRUE) {
++		_irqL irqL;
++		_list	*phead, *plist;
++		struct sta_info *psta = NULL;
++		struct sta_priv *pstapriv = &padapter->stapriv;
++
++		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++		phead = &pstapriv->asoc_list;
++		plist = get_next(phead);
++
++		/* check asoc_queue */
++		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++			psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++
++			plist = get_next(plist);
++
++			associated_stainfo_update(padapter, psta, sta_info_type);
++		}
++
++		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++	}
++
++}
++
++/* called > TSR LEVEL for USB or SDIO Interface*/
++void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
++{
++	u8 beacon_updated = _FALSE;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++
++
++#if 0
++	if (!(psta->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) &&
++	    !psta->no_short_preamble_set) {
++		psta->no_short_preamble_set = 1;
++		pmlmepriv->num_sta_no_short_preamble++;
++		if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
++		    (pmlmepriv->num_sta_no_short_preamble == 1))
++			ieee802_11_set_beacons(hapd->iface);
++	}
++#endif
++
++
++	if (!(psta->flags & WLAN_STA_SHORT_PREAMBLE)) {
++		if (!psta->no_short_preamble_set) {
++			psta->no_short_preamble_set = 1;
++
++			pmlmepriv->num_sta_no_short_preamble++;
++
++			if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
++			    (pmlmepriv->num_sta_no_short_preamble == 1))
++				beacon_updated = _TRUE;
++		}
++	} else {
++		if (psta->no_short_preamble_set) {
++			psta->no_short_preamble_set = 0;
++
++			pmlmepriv->num_sta_no_short_preamble--;
++
++			if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
++			    (pmlmepriv->num_sta_no_short_preamble == 0))
++				beacon_updated = _TRUE;
++		}
++	}
++
++#if 0
++	if (psta->flags & WLAN_STA_NONERP && !psta->nonerp_set) {
++		psta->nonerp_set = 1;
++		pmlmepriv->num_sta_non_erp++;
++		if (pmlmepriv->num_sta_non_erp == 1)
++			ieee802_11_set_beacons(hapd->iface);
++	}
++#endif
++
++	if (psta->flags & WLAN_STA_NONERP) {
++		if (!psta->nonerp_set) {
++			psta->nonerp_set = 1;
++
++			pmlmepriv->num_sta_non_erp++;
++
++			if (pmlmepriv->num_sta_non_erp == 1) {
++				beacon_updated = _TRUE;
++				update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE, 0);
++			}
++		}
++
++	} else {
++		if (psta->nonerp_set) {
++			psta->nonerp_set = 0;
++
++			pmlmepriv->num_sta_non_erp--;
++
++			if (pmlmepriv->num_sta_non_erp == 0) {
++				beacon_updated = _TRUE;
++				update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE, 0);
++			}
++		}
++
++	}
++
++
++#if 0
++	if (!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT) &&
++	    !psta->no_short_slot_time_set) {
++		psta->no_short_slot_time_set = 1;
++		pmlmepriv->num_sta_no_short_slot_time++;
++		if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
++		    (pmlmepriv->num_sta_no_short_slot_time == 1))
++			ieee802_11_set_beacons(hapd->iface);
++	}
++#endif
++
++	if (!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT)) {
++		if (!psta->no_short_slot_time_set) {
++			psta->no_short_slot_time_set = 1;
++
++			pmlmepriv->num_sta_no_short_slot_time++;
++
++			if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
++			    (pmlmepriv->num_sta_no_short_slot_time == 1))
++				beacon_updated = _TRUE;
++		}
++	} else {
++		if (psta->no_short_slot_time_set) {
++			psta->no_short_slot_time_set = 0;
++
++			pmlmepriv->num_sta_no_short_slot_time--;
++
++			if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
++			    (pmlmepriv->num_sta_no_short_slot_time == 0))
++				beacon_updated = _TRUE;
++		}
++	}
++
++#ifdef CONFIG_80211N_HT
++	if(padapter->registrypriv.ht_enable &&
++		is_supported_ht(padapter->registrypriv.wireless_mode)) {
++		if (psta->flags & WLAN_STA_HT) {
++			u16 ht_capab = le16_to_cpu(psta->htpriv.ht_cap.cap_info);
++
++			RTW_INFO("HT: STA " MAC_FMT " HT Capabilities Info: 0x%04x\n",
++				MAC_ARG(psta->cmn.mac_addr), ht_capab);
++
++			if (psta->no_ht_set) {
++				psta->no_ht_set = 0;
++				pmlmepriv->num_sta_no_ht--;
++			}
++
++			if ((ht_capab & IEEE80211_HT_CAP_GRN_FLD) == 0) {
++				if (!psta->no_ht_gf_set) {
++					psta->no_ht_gf_set = 1;
++					pmlmepriv->num_sta_ht_no_gf++;
++				}
++				RTW_INFO("%s STA " MAC_FMT " - no "
++					 "greenfield, num of non-gf stations %d\n",
++					 __FUNCTION__, MAC_ARG(psta->cmn.mac_addr),
++					 pmlmepriv->num_sta_ht_no_gf);
++			}
++
++			if ((ht_capab & IEEE80211_HT_CAP_SUP_WIDTH) == 0) {
++				if (!psta->ht_20mhz_set) {
++					psta->ht_20mhz_set = 1;
++					pmlmepriv->num_sta_ht_20mhz++;
++				}
++				RTW_INFO("%s STA " MAC_FMT " - 20 MHz HT, "
++					 "num of 20MHz HT STAs %d\n",
++					 __FUNCTION__, MAC_ARG(psta->cmn.mac_addr),
++					 pmlmepriv->num_sta_ht_20mhz);
++			}
++
++			if (((ht_capab & RTW_IEEE80211_HT_CAP_40MHZ_INTOLERANT) != 0) &&
++				(psta->ht_40mhz_intolerant == 0)) {
++				psta->ht_40mhz_intolerant = 1;
++				pmlmepriv->num_sta_40mhz_intolerant++;
++				RTW_INFO("%s STA " MAC_FMT " - 40MHZ_INTOLERANT, ",
++					   __FUNCTION__, MAC_ARG(psta->cmn.mac_addr));
++			}
++
++		} else {
++			if (!psta->no_ht_set) {
++				psta->no_ht_set = 1;
++				pmlmepriv->num_sta_no_ht++;
++			}
++			if (pmlmepriv->htpriv.ht_option == _TRUE) {
++				RTW_INFO("%s STA " MAC_FMT
++					 " - no HT, num of non-HT stations %d\n",
++					 __FUNCTION__, MAC_ARG(psta->cmn.mac_addr),
++					 pmlmepriv->num_sta_no_ht);
++			}
++		}
++
++		if (rtw_ht_operation_update(padapter) > 0) {
++			update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0);
++			update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE, 0);
++			beacon_updated = _TRUE;
++		}
++	}
++#endif /* CONFIG_80211N_HT */
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(padapter)) {
++		struct sta_priv *pstapriv = &padapter->stapriv;
++
++		update_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE, 0);
++		if (pstapriv->asoc_list_cnt == 1)
++			_set_timer(&padapter->mesh_atlm_param_req_timer, 0);
++		beacon_updated = _TRUE;
++	}
++#endif
++
++	if (beacon_updated)
++		update_beacon(padapter, 0xFF, NULL, _TRUE, 0);
++
++	/* update associcated stations cap. */
++	associated_clients_update(padapter,  beacon_updated, STA_INFO_UPDATE_ALL);
++
++	RTW_INFO("%s, updated=%d\n", __func__, beacon_updated);
++
++}
++
++u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta)
++{
++	u8 beacon_updated = _FALSE;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++
++	if (!psta)
++		return beacon_updated;
++
++	if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) {
++		rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
++		beacon_updated = _TRUE;
++		update_beacon(padapter, _TIM_IE_, NULL, _FALSE, 0);
++	}
++
++	if (psta->no_short_preamble_set) {
++		psta->no_short_preamble_set = 0;
++		pmlmepriv->num_sta_no_short_preamble--;
++		if (pmlmeext->cur_wireless_mode > WIRELESS_11B
++		    && pmlmepriv->num_sta_no_short_preamble == 0)
++			beacon_updated = _TRUE;
++	}
++
++	if (psta->nonerp_set) {
++		psta->nonerp_set = 0;
++		pmlmepriv->num_sta_non_erp--;
++		if (pmlmepriv->num_sta_non_erp == 0) {
++			beacon_updated = _TRUE;
++			update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE, 0);
++		}
++	}
++
++	if (psta->no_short_slot_time_set) {
++		psta->no_short_slot_time_set = 0;
++		pmlmepriv->num_sta_no_short_slot_time--;
++		if (pmlmeext->cur_wireless_mode > WIRELESS_11B
++		    && pmlmepriv->num_sta_no_short_slot_time == 0)
++			beacon_updated = _TRUE;
++	}
++
++#ifdef CONFIG_80211N_HT
++	if (psta->no_ht_gf_set) {
++		psta->no_ht_gf_set = 0;
++		pmlmepriv->num_sta_ht_no_gf--;
++	}
++
++	if (psta->no_ht_set) {
++		psta->no_ht_set = 0;
++		pmlmepriv->num_sta_no_ht--;
++	}
++
++	if (psta->ht_20mhz_set) {
++		psta->ht_20mhz_set = 0;
++		pmlmepriv->num_sta_ht_20mhz--;
++	}
++
++	if (psta->ht_40mhz_intolerant) {
++		psta->ht_40mhz_intolerant = 0;
++		if (pmlmepriv->num_sta_40mhz_intolerant > 0)
++			pmlmepriv->num_sta_40mhz_intolerant--;
++		else
++			rtw_warn_on(1);
++	}
++
++	if (rtw_ht_operation_update(padapter) > 0) {
++		update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0);
++		update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE, 0);
++	}
++#endif /* CONFIG_80211N_HT */
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(padapter)) {
++		update_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE, 0);
++		if (pstapriv->asoc_list_cnt == 0)
++			_cancel_timer_ex(&padapter->mesh_atlm_param_req_timer);
++		beacon_updated = _TRUE;
++	}
++#endif
++
++	if (beacon_updated == _TRUE)
++		update_beacon(padapter, 0xFF, NULL, _TRUE, 0);
++
++#if 0
++	/* update associated stations cap. */
++	associated_clients_update(padapter,  beacon_updated, STA_INFO_UPDATE_ALL); /* move it to avoid deadlock */
++#endif
++
++	RTW_INFO("%s, updated=%d\n", __func__, beacon_updated);
++
++	return beacon_updated;
++
++}
++
++u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue)
++{
++	_irqL irqL;
++	u8 beacon_updated = _FALSE;
++
++	if (!psta)
++		return beacon_updated;
++
++	if (active == _TRUE) {
++#ifdef CONFIG_80211N_HT
++		/* tear down Rx AMPDU */
++		send_delba(padapter, 0, psta->cmn.mac_addr);/* recipient */
++
++		/* tear down TX AMPDU */
++		send_delba(padapter, 1, psta->cmn.mac_addr);/*  */ /* originator */
++
++#endif /* CONFIG_80211N_HT */
++
++		if (!MLME_IS_MESH(padapter))
++			issue_deauth(padapter, psta->cmn.mac_addr, reason);
++	}
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(padapter))
++		rtw_mesh_path_flush_by_nexthop(psta);
++#endif
++
++#ifdef CONFIG_BEAMFORMING
++	beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, psta->cmn.mac_addr, ETH_ALEN, 1);
++#endif
++
++#ifdef CONFIG_80211N_HT
++	psta->htpriv.agg_enable_bitmap = 0x0;/* reset */
++	psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */
++#endif
++
++
++
++	_enter_critical_bh(&psta->lock, &irqL);
++	psta->state &= ~(WIFI_ASOC_STATE | WIFI_UNDER_KEY_HANDSHAKE);
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if ((psta->auth_len != 0) && (psta->pauth_frame != NULL)) {
++		rtw_mfree(psta->pauth_frame, psta->auth_len);
++		psta->pauth_frame = NULL;
++		psta->auth_len = 0;
++	}
++	if (psta->passoc_req && psta->assoc_req_len > 0) {
++		rtw_mfree(psta->passoc_req , psta->assoc_req_len);
++		psta->passoc_req = NULL;
++		psta->assoc_req_len = 0;
++	}
++#endif /* CONFIG_IOCTL_CFG80211 */
++	_exit_critical_bh(&psta->lock, &irqL);
++
++	if (!MLME_IS_MESH(padapter)) {
++		#ifdef CONFIG_RTW_WDS
++		rtw_wds_path_flush_by_nexthop(psta);
++		#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++		#ifdef COMPAT_KERNEL_RELEASE
++		rtw_cfg80211_indicate_sta_disassoc(padapter, psta->cmn.mac_addr, reason);
++		#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
++		rtw_cfg80211_indicate_sta_disassoc(padapter, psta->cmn.mac_addr, reason);
++		#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */
++		/* will call rtw_cfg80211_indicate_sta_disassoc() in cmd_thread for old API context */
++		#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */
++#else
++		rtw_indicate_sta_disassoc_event(padapter, psta);
++#endif
++	}
++
++	beacon_updated = bss_cap_update_on_sta_leave(padapter, psta);
++
++	report_del_sta_event(padapter, psta->cmn.mac_addr, reason, enqueue, _FALSE);
++	/* clear cam entry / key */
++	rtw_clearstakey_cmd(padapter, psta, enqueue);
++
++	return beacon_updated;
++
++}
++
++int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset)
++{
++	_irqL irqL;
++	_list	*phead, *plist;
++	int ret = 0;
++	struct sta_info *psta = NULL;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++
++	if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
++		return ret;
++
++	RTW_INFO(FUNC_NDEV_FMT" with ch:%u, offset:%u\n",
++		 FUNC_NDEV_ARG(padapter->pnetdev), new_ch, ch_offset);
++
++	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++	phead = &pstapriv->asoc_list;
++	plist = get_next(phead);
++
++	/* for each sta in asoc_queue */
++	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++		plist = get_next(plist);
++
++		issue_action_spct_ch_switch(padapter, psta->cmn.mac_addr, new_ch, ch_offset);
++		psta->expire_to = ((pstapriv->expire_to * 2) > 5) ? 5 : (pstapriv->expire_to * 2);
++	}
++	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++	issue_action_spct_ch_switch(padapter, bc_addr, new_ch, ch_offset);
++
++	return ret;
++}
++
++int rtw_sta_flush(_adapter *padapter, bool enqueue)
++{
++	_irqL irqL;
++	_list	*phead, *plist;
++	int ret = 0;
++	struct sta_info *psta = NULL;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	u8 flush_num = 0;
++	char flush_list[NUM_STA];
++	int i;
++
++	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
++		return ret;
++
++	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev));
++
++	/* pick sta from sta asoc_queue */
++	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++	phead = &pstapriv->asoc_list;
++	plist = get_next(phead);
++	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++		int stainfo_offset;
++
++		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++		plist = get_next(plist);
++
++		rtw_list_delete(&psta->asoc_list);
++		pstapriv->asoc_list_cnt--;
++		#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++		if (psta->tbtx_enable)
++			pstapriv->tbtx_asoc_list_cnt--;
++		#endif
++		STA_SET_MESH_PLINK(psta, NULL);
++
++		stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
++		if (stainfo_offset_valid(stainfo_offset))
++			flush_list[flush_num++] = stainfo_offset;
++		else
++			rtw_warn_on(1);
++	}
++	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++	/* call ap_free_sta() for each sta picked */
++	for (i = 0; i < flush_num; i++) {
++		u8 sta_addr[ETH_ALEN];
++
++		psta = rtw_get_stainfo_by_offset(pstapriv, flush_list[i]);
++		_rtw_memcpy(sta_addr, psta->cmn.mac_addr, ETH_ALEN);
++
++		ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, enqueue);
++		#ifdef CONFIG_RTW_MESH
++		if (MLME_IS_MESH(padapter))
++			rtw_mesh_expire_peer(padapter, sta_addr);
++		#endif
++	}
++
++	if (!MLME_IS_MESH(padapter))
++		issue_deauth(padapter, bc_addr, WLAN_REASON_DEAUTH_LEAVING);
++
++	associated_clients_update(padapter, _TRUE, STA_INFO_UPDATE_ALL);
++
++	return ret;
++}
++
++/* called > TSR LEVEL for USB or SDIO Interface*/
++void sta_info_update(_adapter *padapter, struct sta_info *psta)
++{
++	int flags = psta->flags;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++
++	/* update wmm cap. */
++	if (WLAN_STA_WME & flags)
++		psta->qos_option = 1;
++	else
++		psta->qos_option = 0;
++
++	if (pmlmepriv->qospriv.qos_option == 0)
++		psta->qos_option = 0;
++
++
++#ifdef CONFIG_80211N_HT
++	/* update 802.11n ht cap. */
++	if (WLAN_STA_HT & flags) {
++		psta->htpriv.ht_option = _TRUE;
++		psta->qos_option = 1;
++
++		psta->htpriv.smps_cap = (psta->htpriv.ht_cap.cap_info & IEEE80211_HT_CAP_SM_PS) >> 2;
++	} else
++		psta->htpriv.ht_option = _FALSE;
++
++	if (pmlmepriv->htpriv.ht_option == _FALSE)
++		psta->htpriv.ht_option = _FALSE;
++#endif
++
++#ifdef CONFIG_80211AC_VHT
++	/* update 802.11AC vht cap. */
++	if (WLAN_STA_VHT & flags)
++		psta->vhtpriv.vht_option = _TRUE;
++	else
++		psta->vhtpriv.vht_option = _FALSE;
++
++	if (pmlmepriv->vhtpriv.vht_option == _FALSE)
++		psta->vhtpriv.vht_option = _FALSE;
++#endif
++
++	update_sta_info_apmode(padapter, psta);
++}
++
++/* called >= TSR LEVEL for USB or SDIO Interface*/
++void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta)
++{
++	if (psta->state & WIFI_ASOC_STATE)
++		rtw_hal_update_ra_mask(psta); /* DM_RATR_STA_INIT */
++}
++/* restore hw setting from sw data structures */
++void rtw_ap_restore_network(_adapter *padapter)
++{
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct sta_info *psta;
++	struct security_priv *psecuritypriv = &(padapter->securitypriv);
++	_irqL irqL;
++	_list	*phead, *plist;
++	u8 chk_alive_num = 0;
++	char chk_alive_list[NUM_STA];
++	int i;
++
++	rtw_setopmode_cmd(padapter
++		, MLME_IS_AP(padapter) ? Ndis802_11APMode : Ndis802_11_mesh
++		, RTW_CMDF_DIRECTLY
++	);
++
++	set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++
++	rtw_startbss_cmd(padapter, RTW_CMDF_DIRECTLY);
++
++	if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
++	    (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) {
++		/* restore group key, WEP keys is restored in ips_leave() */
++		rtw_set_key(padapter, psecuritypriv, psecuritypriv->dot118021XGrpKeyid, 0, _FALSE);
++	}
++
++	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++	phead = &pstapriv->asoc_list;
++	plist = get_next(phead);
++
++	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++		int stainfo_offset;
++
++		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++		plist = get_next(plist);
++
++		stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
++		if (stainfo_offset_valid(stainfo_offset))
++			chk_alive_list[chk_alive_num++] = stainfo_offset;
++	}
++
++	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++	for (i = 0; i < chk_alive_num; i++) {
++		psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]);
++
++		if (psta == NULL)
++			RTW_INFO(FUNC_ADPT_FMT" sta_info is null\n", FUNC_ADPT_ARG(padapter));
++		else if (psta->state & WIFI_ASOC_STATE) {
++			rtw_sta_media_status_rpt(padapter, psta, 1);
++			Update_RA_Entry(padapter, psta);
++			/* pairwise key */
++			/* per sta pairwise key and settings */
++			if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
++			    (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_))
++				rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _FALSE);
++		}
++	}
++
++}
++
++void start_ap_mode(_adapter *padapter)
++{
++	int i;
++	struct sta_info *psta = NULL;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++
++	pmlmepriv->update_bcn = _FALSE;
++
++	/*init_mlme_ap_info(padapter);*/
++
++	pmlmeext->bstart_bss = _FALSE;
++
++	pmlmepriv->num_sta_non_erp = 0;
++
++	pmlmepriv->num_sta_no_short_slot_time = 0;
++
++	pmlmepriv->num_sta_no_short_preamble = 0;
++
++	pmlmepriv->num_sta_ht_no_gf = 0;
++#ifdef CONFIG_80211N_HT
++	pmlmepriv->num_sta_no_ht = 0;
++#endif /* CONFIG_80211N_HT */
++	pmlmeinfo->HT_info_enable = 0;
++	pmlmeinfo->HT_caps_enable = 0;
++	pmlmeinfo->HT_enable = 0;
++
++	pmlmepriv->num_sta_ht_20mhz = 0;
++	pmlmepriv->num_sta_40mhz_intolerant = 0;
++	ATOMIC_SET(&pmlmepriv->olbc, _FALSE);
++	ATOMIC_SET(&pmlmepriv->olbc_ht, _FALSE);
++
++#ifdef CONFIG_80211N_HT
++	pmlmepriv->ht_20mhz_width_req = _FALSE;
++	pmlmepriv->ht_intolerant_ch_reported = _FALSE;
++	pmlmepriv->ht_op_mode = 0;
++	pmlmepriv->sw_to_20mhz = 0;
++#endif
++
++	_rtw_memset(pmlmepriv->ext_capab_ie_data, 0, sizeof(pmlmepriv->ext_capab_ie_data));
++	pmlmepriv->ext_capab_ie_len = 0;
++
++	psecuritypriv->dot118021x_bmc_cam_id = INVALID_SEC_MAC_CAM_ID;
++
++	for (i = 0 ;  i < pstapriv->max_aid; i++)
++		pstapriv->sta_aid[i] = NULL;
++
++#ifdef CONFIG_RTW_WDS
++	if (MLME_IS_AP(padapter))
++		rtw_wds_pathtbl_init(padapter);
++#endif
++
++	psta = rtw_get_bcmc_stainfo(padapter);
++	/*_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/
++	if (psta)
++		rtw_free_stainfo(padapter, psta);
++	/*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/
++
++	rtw_init_bcmc_stainfo(padapter);
++
++	if (rtw_mi_get_ap_num(padapter))
++		RTW_SET_SCAN_BAND_SKIP(padapter, BAND_5G);
++
++}
++
++void stop_ap_mode(_adapter *padapter)
++{
++	u8 self_action = MLME_ACTION_UNKNOWN;
++	struct sta_info *psta = NULL;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++#ifdef CONFIG_SUPPORT_MULTI_BCN
++	struct dvobj_priv *pdvobj = padapter->dvobj;
++	_irqL irqL;
++#endif
++
++	RTW_INFO("%s -"ADPT_FMT"\n", __func__, ADPT_ARG(padapter));
++
++	if (MLME_IS_AP(padapter))
++		self_action = MLME_AP_STOPPED;
++	else if (MLME_IS_MESH(padapter))
++		self_action = MLME_MESH_STOPPED;
++	else
++		rtw_warn_on(1);
++
++	pmlmepriv->update_bcn = _FALSE;
++	/*pmlmeext->bstart_bss = _FALSE;*/
++	padapter->netif_up = _FALSE;
++	/* _rtw_spinlock_free(&pmlmepriv->bcn_update_lock); */
++
++	/* reset and init security priv , this can refine with rtw_reset_securitypriv */
++	_rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof(struct security_priv));
++	padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;
++	padapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled;
++
++#ifdef CONFIG_DFS_MASTER
++	rtw_dfs_rd_en_decision(padapter, self_action, 0);
++#endif
++
++	/* free scan queue */
++	rtw_free_network_queue(padapter, _TRUE);
++
++#if CONFIG_RTW_MACADDR_ACL
++	rtw_macaddr_acl_clear(padapter, RTW_ACL_PERIOD_BSS);
++#endif
++
++	rtw_sta_flush(padapter, _TRUE);
++
++	/* free_assoc_sta_resources	 */
++	rtw_free_all_stainfo(padapter);
++
++	psta = rtw_get_bcmc_stainfo(padapter);
++	if (psta) {
++		rtw_sta_mstatus_disc_rpt(padapter, psta->cmn.mac_id);
++		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
++		rtw_free_stainfo(padapter, psta);
++		/*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/
++	}
++
++	pmlmepriv->ap_isolate = 0;
++#ifdef CONFIG_RTW_WDS
++	adapter_set_use_wds(padapter, 0);
++#endif
++#ifdef CONFIG_RTW_MULTI_AP
++	padapter->multi_ap = 0;
++#endif
++	rtw_free_mlme_priv_ie_data(pmlmepriv);
++
++#ifdef CONFIG_SUPPORT_MULTI_BCN
++	if (pmlmeext->bstart_bss == _TRUE) {
++		#ifdef CONFIG_FW_HANDLE_TXBCN
++		u8 free_apid = CONFIG_LIMITED_AP_NUM;
++		#endif
++
++		_enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
++		pdvobj->nr_ap_if--;
++		if (pdvobj->nr_ap_if > 0)
++			pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL / pdvobj->nr_ap_if;
++		else
++			pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL;
++		#ifdef CONFIG_FW_HANDLE_TXBCN
++		rtw_ap_release_vapid(pdvobj, padapter->vap_id);
++		free_apid = padapter->vap_id;
++		padapter->vap_id = CONFIG_LIMITED_AP_NUM;
++		#endif
++		rtw_list_delete(&padapter->list);
++		_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
++		#ifdef CONFIG_FW_HANDLE_TXBCN
++		rtw_ap_mbid_bcn_dis(padapter, free_apid);
++		#endif
++
++		#ifdef CONFIG_SWTIMER_BASED_TXBCN
++		rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pdvobj->inter_bcn_space));
++
++		if (pdvobj->nr_ap_if == 0)
++			_cancel_timer_ex(&pdvobj->txbcn_timer);
++		#endif
++	}
++#endif
++
++	pmlmeext->bstart_bss = _FALSE;
++
++	rtw_hal_rcr_set_chk_bssid(padapter, self_action);
++
++#ifdef CONFIG_HW_P0_TSF_SYNC
++	correct_TSF(padapter, self_action);
++#endif
++
++#ifdef CONFIG_BT_COEXIST
++	rtw_btcoex_MediaStatusNotify(padapter, 0); /* disconnect */
++#endif
++
++#ifdef CONFIG_RTW_WDS
++	if (MLME_IS_AP(padapter))
++		rtw_wds_pathtbl_unregister(padapter);
++#endif
++}
++
++#endif /* CONFIG_NATIVEAP_MLME */
++
++void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset)
++{
++#define UPDATE_VHT_CAP 1
++#define UPDATE_HT_CAP 1
++#ifdef CONFIG_80211AC_VHT
++	struct vht_priv *vhtpriv = &adapter->mlmepriv.vhtpriv;
++#endif
++	{
++		u8 *p;
++		int ie_len;
++		u8 old_ch = bss->Configuration.DSConfig;
++		bool change_band = _FALSE;
++
++		if ((ch <= 14 && old_ch >= 36) || (ch >= 36 && old_ch <= 14))
++			change_band = _TRUE;
++
++		/* update channel in IE */
++		p = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
++		if (p && ie_len > 0)
++			*(p + 2) = ch;
++
++		bss->Configuration.DSConfig = ch;
++
++		/* band is changed, update ERP, support rate, ext support rate IE */
++		if (change_band == _TRUE)
++			change_band_update_ie(adapter, bss, ch);
++	}
++
++#ifdef CONFIG_80211AC_VHT
++	if (vhtpriv->vht_option == _TRUE) {
++		u8 *vht_cap_ie, *vht_op_ie;
++		int vht_cap_ielen, vht_op_ielen;
++		u8	center_freq;
++
++		vht_cap_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_VHTCapability, &vht_cap_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
++		vht_op_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_VHTOperation, &vht_op_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
++		center_freq = rtw_get_center_ch(ch, bw, offset);
++
++		/* update vht cap ie */
++		if (vht_cap_ie && vht_cap_ielen) {
++			#if UPDATE_VHT_CAP
++			/* if ((bw == CHANNEL_WIDTH_160 || bw == CHANNEL_WIDTH_80_80) && pvhtpriv->sgi_160m)
++				SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvht_cap_ie + 2, 1);
++			else */
++				SET_VHT_CAPABILITY_ELE_SHORT_GI160M(vht_cap_ie + 2, 0);
++
++			if (bw >= CHANNEL_WIDTH_80 && vhtpriv->sgi_80m)
++				SET_VHT_CAPABILITY_ELE_SHORT_GI80M(vht_cap_ie + 2, 1);
++			else
++				SET_VHT_CAPABILITY_ELE_SHORT_GI80M(vht_cap_ie + 2, 0);
++			#endif
++		}
++
++		/* update vht op ie */
++		if (vht_op_ie && vht_op_ielen) {
++			if (bw < CHANNEL_WIDTH_80) {
++				SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0);
++				SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0);
++				SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0);
++			} else if (bw == CHANNEL_WIDTH_80) {
++				SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 1);
++				SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, center_freq);
++				SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0);
++			} else {
++				RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(adapter), bw);
++				rtw_warn_on(1);
++			}
++		}
++	}
++#endif /* CONFIG_80211AC_VHT */
++#ifdef CONFIG_80211N_HT
++	{
++		struct ht_priv	*htpriv = &adapter->mlmepriv.htpriv;
++		u8 *ht_cap_ie, *ht_op_ie;
++		int ht_cap_ielen, ht_op_ielen;
++
++		ht_cap_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_HTCapability, &ht_cap_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
++		ht_op_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_HTInfo, &ht_op_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
++
++		/* update ht cap ie */
++		if (ht_cap_ie && ht_cap_ielen) {
++			#if UPDATE_HT_CAP
++			if (bw >= CHANNEL_WIDTH_40)
++				SET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2, 1);
++			else
++				SET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2, 0);
++
++			if (bw >= CHANNEL_WIDTH_40 && htpriv->sgi_40m)
++				SET_HT_CAP_ELE_SHORT_GI40M(ht_cap_ie + 2, 1);
++			else
++				SET_HT_CAP_ELE_SHORT_GI40M(ht_cap_ie + 2, 0);
++
++			if (htpriv->sgi_20m)
++				SET_HT_CAP_ELE_SHORT_GI20M(ht_cap_ie + 2, 1);
++			else
++				SET_HT_CAP_ELE_SHORT_GI20M(ht_cap_ie + 2, 0);
++			#endif
++		}
++
++		/* update ht op ie */
++		if (ht_op_ie && ht_op_ielen) {
++			SET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2, ch);
++			switch (offset) {
++			case HAL_PRIME_CHNL_OFFSET_LOWER:
++				SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCA);
++				break;
++			case HAL_PRIME_CHNL_OFFSET_UPPER:
++				SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCB);
++				break;
++			case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
++			default:
++				SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCN);
++				break;
++			}
++
++			if (bw >= CHANNEL_WIDTH_40)
++				SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2, 1);
++			else
++				SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2, 0);
++		}
++	}
++#endif /* CONFIG_80211N_HT */
++}
++
++static u8 rtw_ap_update_chbw_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp
++	, u8 cur_ie_ch[], u8 cur_ie_bw[], u8 cur_ie_offset[]
++	, u8 dec_ch[], u8 dec_bw[], u8 dec_offset[]
++	, const char *caller)
++{
++	_adapter *iface;
++	struct mlme_ext_priv *mlmeext;
++	WLAN_BSSID_EX *network;
++	u8 ifbmp_ch_changed = 0;
++	int i;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		if (!(ifbmp & BIT(i)) || !dvobj->padapters)
++			continue;
++
++		iface = dvobj->padapters[i];
++		mlmeext = &(iface->mlmeextpriv);
++
++		if (MLME_IS_ASOC(iface)) {
++			RTW_INFO(FUNC_ADPT_FMT" %u,%u,%u => %u,%u,%u%s\n", caller, ADPT_ARG(iface)
++				, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset
++				, dec_ch[i], dec_bw[i], dec_offset[i]
++				, MLME_IS_OPCH_SW(iface) ? " OPCH_SW" : "");
++		} else {
++			RTW_INFO(FUNC_ADPT_FMT" %u,%u,%u => %u,%u,%u%s\n", caller, ADPT_ARG(iface)
++				, cur_ie_ch[i], cur_ie_bw[i], cur_ie_offset[i]
++				, dec_ch[i], dec_bw[i], dec_offset[i]
++				, MLME_IS_OPCH_SW(iface) ? " OPCH_SW" : "");
++		}
++	}
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		if (!(ifbmp & BIT(i)) || !dvobj->padapters)
++			continue;
++
++		iface = dvobj->padapters[i];
++		mlmeext = &(iface->mlmeextpriv);
++		network = &(mlmeext->mlmext_info.network);
++
++		/* ch setting differs from mlmeext.network IE */
++		if (cur_ie_ch[i] != dec_ch[i]
++			|| cur_ie_bw[i] != dec_bw[i]
++			|| cur_ie_offset[i] != dec_offset[i])
++			ifbmp_ch_changed |= BIT(i);
++
++		/* ch setting differs from existing one */
++		if (MLME_IS_ASOC(iface)
++			&& (mlmeext->cur_channel != dec_ch[i]
++				|| mlmeext->cur_bwmode != dec_bw[i]
++				|| mlmeext->cur_ch_offset != dec_offset[i])
++		) {
++			if (rtw_linked_check(iface) == _TRUE) {
++				#ifdef CONFIG_SPCT_CH_SWITCH
++				if (1)
++					rtw_ap_inform_ch_switch(iface, dec_ch[i], dec_offset[i]);
++				else
++				#endif
++					rtw_sta_flush(iface, _FALSE);
++			}
++		}
++
++		mlmeext->cur_channel = dec_ch[i];
++		mlmeext->cur_bwmode = dec_bw[i];
++		mlmeext->cur_ch_offset = dec_offset[i];
++
++		rtw_ap_update_bss_chbw(iface, network, dec_ch[i], dec_bw[i], dec_offset[i]);
++	}
++
++	return ifbmp_ch_changed;
++}
++
++static u8 rtw_ap_ch_specific_chk(_adapter *adapter, u8 ch, u8 *bw, u8 *offset, const char *caller)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	RT_CHANNEL_INFO *chset = rfctl->channel_set;
++	int ch_idx;
++	u8 ret = _SUCCESS;
++
++	ch_idx = rtw_chset_search_ch(chset, ch);
++	if (ch_idx < 0) {
++		RTW_WARN("%s ch:%u doesn't fit in chplan\n", caller, ch);
++		ret = _FAIL;
++		goto exit;
++	}
++	if (chset[ch_idx].ScanType == SCAN_PASSIVE) {
++		RTW_WARN("%s ch:%u is passive\n", caller, ch);
++		ret = _FAIL;
++		goto exit;
++	}
++
++	rtw_adjust_chbw(adapter, ch, bw, offset);
++
++	if (!rtw_get_offset_by_chbw(ch, *bw, offset)) {
++		RTW_WARN("%s %u,%u has no valid offset\n", caller, ch, *bw);
++		ret = _FAIL;
++		goto exit;
++	}
++
++	while (!rtw_chset_is_chbw_valid(chset, ch, *bw, *offset, 0, 0)
++		|| (rtw_rfctl_dfs_domain_unknown(rfctl) && rtw_chset_is_dfs_chbw(chset, ch, *bw, *offset))
++	) {
++		if (*bw > CHANNEL_WIDTH_20)
++			(*bw)--;
++		if (*bw == CHANNEL_WIDTH_20) {
++			*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++			break;
++		}
++	}
++
++	if (rtw_rfctl_dfs_domain_unknown(rfctl) && rtw_chset_is_dfs_chbw(chset, ch, *bw, *offset)) {
++		RTW_WARN("%s DFS channel %u can't be used\n", caller, ch);
++		ret = _FAIL;
++		goto exit;
++	}
++
++exit:
++	return ret;
++}
++
++static bool rtw_ap_choose_chbw(_adapter *adapter, u8 sel_ch, u8 max_bw, u8 cur_ch
++	, u8 *ch, u8 *bw, u8 *offset, bool by_int_info, u8 mesh_only, const char *caller)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	bool ch_avail = _FALSE;
++
++#if defined(CONFIG_DFS_MASTER)
++	if (!rtw_rfctl_dfs_domain_unknown(rfctl)) {
++		if (rfctl->radar_detected
++			&& rfctl->dbg_dfs_choose_dfs_ch_first
++		) {
++			ch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw
++						, ch, bw, offset
++						, RTW_CHF_2G | RTW_CHF_NON_DFS
++						, cur_ch, by_int_info, mesh_only);
++			if (ch_avail == _TRUE) {
++				RTW_INFO("%s choose 5G DFS channel for debug\n", caller);
++				goto exit;
++			}
++		}
++
++		if (rfctl->radar_detected
++			&& rfctl->dfs_ch_sel_d_flags
++		) {
++			ch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw
++						, ch, bw, offset
++						, rfctl->dfs_ch_sel_d_flags
++						, cur_ch, by_int_info, mesh_only);
++			if (ch_avail == _TRUE) {
++				RTW_INFO("%s choose with dfs_ch_sel_d_flags:0x%02x for debug\n"
++					, caller, rfctl->dfs_ch_sel_d_flags);
++				goto exit;
++			}
++		}
++
++		ch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw
++					, ch, bw, offset
++					, 0
++					, cur_ch, by_int_info, mesh_only);
++	} else
++#endif /* defined(CONFIG_DFS_MASTER) */
++	{
++		ch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw
++					, ch, bw, offset
++					, RTW_CHF_DFS
++					, cur_ch, by_int_info, mesh_only);
++	}
++#if defined(CONFIG_DFS_MASTER)
++exit:
++#endif
++	if (ch_avail == _FALSE)
++		RTW_WARN("%s no available channel\n", caller);
++
++	return ch_avail;
++}
++
++u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp
++	, s16 req_ch, s8 req_bw, s8 req_offset
++	, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	RT_CHANNEL_INFO *chset = adapter_to_chset(adapter);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	bool ch_avail = _FALSE;
++	u8 cur_ie_ch[CONFIG_IFACE_NUMBER] = {0};
++	u8 cur_ie_bw[CONFIG_IFACE_NUMBER] = {0};
++	u8 cur_ie_offset[CONFIG_IFACE_NUMBER] = {0};
++	u8 dec_ch[CONFIG_IFACE_NUMBER] = {0};
++	u8 dec_bw[CONFIG_IFACE_NUMBER] = {0};
++	u8 dec_offset[CONFIG_IFACE_NUMBER] = {0};
++	u8 u_ch = 0, u_bw = 0, u_offset = 0;
++	struct mlme_ext_priv *mlmeext;
++	WLAN_BSSID_EX *network;
++	struct mi_state mstate;
++	struct mi_state mstate_others;
++	bool set_u_ch = _FALSE;
++	u8 ifbmp_others = 0xFF & ~ifbmp & ~excl_ifbmp;
++	u8 ifbmp_ch_changed = 0;
++	bool ifbmp_all_mesh = 0;
++	_adapter *iface;
++	int i;
++
++#ifdef CONFIG_RTW_MESH
++	for (i = 0; i < dvobj->iface_nums; i++)
++		if ((ifbmp & BIT(i)) && dvobj->padapters)
++			if (!MLME_IS_MESH(dvobj->padapters[i]))
++				break;
++	ifbmp_all_mesh = i >= dvobj->iface_nums ? 1 : 0;
++#endif
++
++	RTW_INFO("%s ifbmp:0x%02x excl_ifbmp:0x%02x req:%d,%d,%d\n", __func__
++		, ifbmp, excl_ifbmp, req_ch, req_bw, req_offset);
++	rtw_mi_status_by_ifbmp(dvobj, ifbmp, &mstate);
++	rtw_mi_status_by_ifbmp(dvobj, ifbmp_others, &mstate_others);
++	RTW_INFO("%s others ld_sta_num:%u, lg_sta_num:%u, ap_num:%u, mesh_num:%u\n"
++		, __func__, MSTATE_STA_LD_NUM(&mstate_others), MSTATE_STA_LG_NUM(&mstate_others)
++		, MSTATE_AP_NUM(&mstate_others), MSTATE_MESH_NUM(&mstate_others));
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
++			continue;
++		iface = dvobj->padapters[i];
++		mlmeext = &(iface->mlmeextpriv);
++		network = &(mlmeext->mlmext_info.network);
++
++		/* get current IE channel settings */
++		rtw_ies_get_chbw(BSS_EX_TLV_IES(network), BSS_EX_TLV_IES_LEN(network)
++			, &cur_ie_ch[i], &cur_ie_bw[i], &cur_ie_offset[i], 1, 1);
++
++		/* prepare temporary channel setting decision */
++		if (req_ch == 0) {
++			/* request comes from upper layer, use cur_ie values */
++			dec_ch[i] = cur_ie_ch[i];
++			dec_bw[i] = cur_ie_bw[i];
++			dec_offset[i] = cur_ie_offset[i];
++		} else {
++			/* use chbw of cur_ie updated with specifying req as temporary decision */
++			dec_ch[i] = (req_ch <= REQ_CH_NONE) ? cur_ie_ch[i] : req_ch;
++			if (req_bw <= REQ_BW_NONE) {
++				if (req_bw == REQ_BW_ORI)
++					dec_bw[i] = iface->mlmepriv.ori_bw;
++				else
++					dec_bw[i] = cur_ie_bw[i];
++			} else
++				dec_bw[i] = req_bw;
++			dec_offset[i] = (req_offset <= REQ_OFFSET_NONE) ? cur_ie_offset[i] : req_offset;
++		}
++	}
++
++	if (MSTATE_STA_LD_NUM(&mstate_others) || MSTATE_STA_LG_NUM(&mstate_others)
++		|| MSTATE_AP_NUM(&mstate_others) || MSTATE_MESH_NUM(&mstate_others)
++	) {
++		/* has linked/linking STA or has AP/Mesh mode */
++		rtw_warn_on(!rtw_mi_get_ch_setting_union_by_ifbmp(dvobj, ifbmp_others, &u_ch, &u_bw, &u_offset));
++		RTW_INFO("%s others union:%u,%u,%u\n", __func__, u_ch, u_bw, u_offset);
++	}
++
++#ifdef CONFIG_MCC_MODE
++	if (MCC_EN(adapter) && req_ch == 0) {
++		if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
++			u8 if_id = adapter->iface_id;
++
++			mlmeext = &(adapter->mlmeextpriv);
++
++			/* check channel settings are the same */
++			if (cur_ie_ch[if_id] == mlmeext->cur_channel
++				&& cur_ie_bw[if_id] == mlmeext->cur_bwmode
++				&& cur_ie_offset[if_id] == mlmeext->cur_ch_offset) {
++
++				RTW_INFO(FUNC_ADPT_FMT"req ch settings are the same as current ch setting, go to exit\n"
++					, FUNC_ADPT_ARG(adapter));
++
++				*chbw_allow = _FALSE;
++				goto exit;
++			} else {
++				RTW_INFO(FUNC_ADPT_FMT"request channel settings are not the same as current channel setting(%d,%d,%d,%d,%d,%d), restart MCC\n"
++					, FUNC_ADPT_ARG(adapter)
++					, cur_ie_ch[if_id], cur_ie_bw[if_id], cur_ie_offset[if_id]
++					, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
++
++				rtw_hal_set_mcc_setting_disconnect(adapter);
++			}
++		}	
++	}
++#endif /* CONFIG_MCC_MODE */
++
++	if (MSTATE_STA_LG_NUM(&mstate_others) && !MSTATE_STA_LD_NUM(&mstate_others)) {
++		/* has linking STA but no linked STA */
++
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
++				continue;
++			iface = dvobj->padapters[i];
++
++			rtw_adjust_chbw(iface, dec_ch[i], &dec_bw[i], &dec_offset[i]);
++			#ifdef CONFIG_RTW_MESH
++			if (MLME_IS_MESH(iface))
++				rtw_mesh_adjust_chbw(dec_ch[i], &dec_bw[i], &dec_offset[i]);
++			#endif
++
++			if (rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch[i], dec_bw[i], dec_offset[i])) {
++				rtw_chset_sync_chbw(chset
++					, &dec_ch[i], &dec_bw[i], &dec_offset[i]
++					, &u_ch, &u_bw, &u_offset, 1, 0);
++				set_u_ch = _TRUE;
++
++				/* channel bw offset can be allowed, not need MCC */
++				*chbw_allow = _TRUE;
++			} else {
++				#ifdef CONFIG_MCC_MODE
++				if (MCC_EN(iface)) {
++					mlmeext = &(iface->mlmeextpriv);
++					mlmeext->cur_channel = *ch = dec_ch[i];
++					mlmeext->cur_bwmode = *bw = dec_bw[i];
++					mlmeext->cur_ch_offset = *offset = dec_offset[i];
++
++					/* channel bw offset can not be allowed, need MCC */
++					*chbw_allow = _FALSE;
++					RTW_INFO(FUNC_ADPT_FMT" enable mcc: %u,%u,%u\n", FUNC_ADPT_ARG(iface)
++						 , *ch, *bw, *offset);
++					goto exit;
++				}
++				#endif /* CONFIG_MCC_MODE */
++
++				/* set this for possible ch change when join down*/
++				set_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING);
++			}
++		}
++
++	} else if (MSTATE_STA_LD_NUM(&mstate_others)
++		|| MSTATE_AP_NUM(&mstate_others) || MSTATE_MESH_NUM(&mstate_others)
++	) {
++		/* has linked STA mode or AP/Mesh mode */
++
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
++				continue;
++			iface = dvobj->padapters[i];
++
++			rtw_adjust_chbw(iface, u_ch, &dec_bw[i], &dec_offset[i]);
++			#ifdef CONFIG_RTW_MESH
++			if (MLME_IS_MESH(iface))
++				rtw_mesh_adjust_chbw(u_ch, &dec_bw[i], &dec_offset[i]);
++			#endif
++
++			#ifdef CONFIG_MCC_MODE
++			if (MCC_EN(iface)) {
++				if (!rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch[i], dec_bw[i], dec_offset[i])) {
++					mlmeext = &(iface->mlmeextpriv);
++					mlmeext->cur_channel = *ch = dec_ch[i] = cur_ie_ch[i];
++					mlmeext->cur_bwmode = *bw = dec_bw[i] = cur_ie_bw[i];
++					mlmeext->cur_ch_offset = *offset = dec_offset[i] = cur_ie_offset[i];
++					/* channel bw offset can not be allowed, need MCC */
++					*chbw_allow = _FALSE;
++					RTW_INFO(FUNC_ADPT_FMT" enable mcc: %u,%u,%u\n", FUNC_ADPT_ARG(iface)
++						 , *ch, *bw, *offset);
++					goto exit;
++				} else
++					/* channel bw offset can be allowed, not need MCC */
++					*chbw_allow = _TRUE;
++			}
++			#endif /* CONFIG_MCC_MODE */
++
++			if (req_ch == 0 && dec_bw[i] > u_bw
++				&& rtw_chset_is_dfs_chbw(chset, u_ch, u_bw, u_offset)
++			) {
++				/* request comes from upper layer, prevent from additional channel waiting */
++				dec_bw[i] = u_bw;
++				if (dec_bw[i] == CHANNEL_WIDTH_20)
++					dec_offset[i] = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++			}
++
++			/* follow */
++			rtw_chset_sync_chbw(chset
++				, &dec_ch[i], &dec_bw[i], &dec_offset[i]
++				, &u_ch, &u_bw, &u_offset, 1, 0);
++		}
++
++		set_u_ch = _TRUE;
++
++	} else {
++		/* autonomous decision */
++		u8 ori_ch = 0;
++		u8 max_bw;
++		bool by_int_info;
++
++		/* autonomous decision, not need MCC */
++		*chbw_allow = _TRUE;
++
++		if (req_ch <= REQ_CH_NONE) /* channel is not specified */
++			goto choose_chbw;
++
++		/* get tmp dec union of ifbmp */
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
++				continue;
++			if (u_ch == 0) {
++				u_ch = dec_ch[i];
++				u_bw = dec_bw[i];
++				u_offset = dec_offset[i];
++				rtw_adjust_chbw(adapter, u_ch, &u_bw, &u_offset);
++				rtw_get_offset_by_chbw(u_ch, u_bw, &u_offset);
++			} else {
++				u8 tmp_ch = dec_ch[i];
++				u8 tmp_bw = dec_bw[i];
++				u8 tmp_offset = dec_offset[i];
++				
++				rtw_adjust_chbw(adapter, tmp_ch, &tmp_bw, &tmp_offset);
++				rtw_get_offset_by_chbw(tmp_ch, tmp_bw, &tmp_offset);
++
++				rtw_warn_on(!rtw_is_chbw_grouped(u_ch, u_bw, u_offset, tmp_ch, tmp_bw, tmp_offset));
++				rtw_sync_chbw(&tmp_ch, &tmp_bw, &tmp_offset, &u_ch, &u_bw, &u_offset);
++			}
++		}
++
++		#ifdef CONFIG_RTW_MESH
++		/* if ifbmp are all mesh, apply bw restriction */
++		if (ifbmp_all_mesh)
++			rtw_mesh_adjust_chbw(u_ch, &u_bw, &u_offset);
++		#endif
++
++		RTW_INFO("%s ifbmp:0x%02x tmp union:%u,%u,%u\n", __func__, ifbmp, u_ch, u_bw, u_offset);
++
++		/* check if tmp dec union is usable */
++		if (rtw_ap_ch_specific_chk(adapter, u_ch, &u_bw, &u_offset, __func__) == _FAIL) {
++			/* channel can't be used */
++			if (req_ch > 0) {
++				/* specific channel and not from IE => don't change channel setting */
++				goto exit;
++			}
++			goto choose_chbw;
++		} else if (rtw_chset_is_chbw_non_ocp(chset, u_ch, u_bw, u_offset)) {
++			RTW_WARN("%s DFS channel %u,%u under non ocp\n", __func__, u_ch, u_bw);
++			if (req_ch > 0 && req_bw > REQ_BW_NONE) {
++				/* change_chbw with specific channel and specific bw, goto update_bss_chbw directly */
++				goto update_bss_chbw;
++			}
++		} else
++			goto update_bss_chbw;
++
++choose_chbw:
++		by_int_info = req_ch == REQ_CH_INT_INFO ? 1 : 0;
++		req_ch = req_ch > 0 ? req_ch : 0;
++		max_bw = req_bw > REQ_BW_NONE ? req_bw : CHANNEL_WIDTH_20;
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
++				continue;
++			iface = dvobj->padapters[i];
++			mlmeext = &(iface->mlmeextpriv);
++
++			if (req_bw <= REQ_BW_NONE) {
++				if (req_bw == REQ_BW_ORI) {
++					if (max_bw < iface->mlmepriv.ori_bw)
++						max_bw = iface->mlmepriv.ori_bw;
++				} else {
++					if (max_bw < cur_ie_bw[i])
++						max_bw = cur_ie_bw[i];
++				}
++			}
++
++			if (MSTATE_AP_NUM(&mstate) || MSTATE_MESH_NUM(&mstate)) {
++				if (ori_ch == 0)
++					ori_ch = mlmeext->cur_channel;
++				else if (ori_ch != mlmeext->cur_channel)
++					rtw_warn_on(1);
++			} else {
++				if (ori_ch == 0)
++					ori_ch = cur_ie_ch[i];
++				else if (ori_ch != cur_ie_ch[i])
++					rtw_warn_on(1);
++			}
++		}
++
++		ch_avail = rtw_ap_choose_chbw(adapter, req_ch, max_bw
++			, ori_ch, &u_ch, &u_bw, &u_offset, by_int_info, ifbmp_all_mesh, __func__);
++		if (ch_avail == _FALSE)
++			goto exit;
++
++update_bss_chbw:
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
++				continue;
++			iface = dvobj->padapters[i];
++
++			dec_ch[i] = u_ch;
++			if (dec_bw[i] > u_bw)
++				dec_bw[i] = u_bw;
++			if (dec_bw[i] == CHANNEL_WIDTH_20)
++				dec_offset[i] = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++			else
++				dec_offset[i] = u_offset;
++
++			#ifdef CONFIG_RTW_MESH
++			if (MLME_IS_MESH(iface))
++				rtw_mesh_adjust_chbw(dec_ch[i], &dec_bw[i], &dec_offset[i]);
++			#endif
++		}
++
++		set_u_ch = _TRUE;
++	}
++
++	ifbmp_ch_changed = rtw_ap_update_chbw_by_ifbmp(dvobj, ifbmp
++							, cur_ie_ch, cur_ie_bw, cur_ie_offset
++							, dec_ch, dec_bw, dec_offset
++							, __func__);
++
++	if (u_ch != 0)
++		RTW_INFO("%s union:%u,%u,%u\n", __func__, u_ch, u_bw, u_offset);
++
++	if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_SURVEY)) {
++		/* scanning, leave ch setting to scan state machine */
++		set_u_ch = _FALSE;
++	}
++
++	if (set_u_ch == _TRUE) {
++		*ch = u_ch;
++		*bw = u_bw;
++		*offset = u_offset;
++	}
++exit:
++	return ifbmp_ch_changed;
++}
++
++u8 rtw_ap_sta_states_check(_adapter *adapter)
++{
++	struct sta_info *psta;
++	struct sta_priv *pstapriv = &adapter->stapriv;
++	_list *plist, *phead;
++	_irqL irqL;
++	u8 rst = _FALSE;
++
++	if (!MLME_IS_AP(adapter) && !MLME_IS_MESH(adapter))
++		return _FALSE;
++
++	if (pstapriv->auth_list_cnt !=0)
++		return _TRUE;
++
++	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++	phead = &pstapriv->asoc_list;
++	plist = get_next(phead);
++	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++
++		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++		plist = get_next(plist);
++
++		if (!(psta->state & WIFI_ASOC_STATE)) {
++			RTW_INFO(ADPT_FMT"- SoftAP/Mesh - sta under linking, its state = 0x%x\n", ADPT_ARG(adapter), psta->state);
++			rst = _TRUE;
++			break;
++		} else if (psta->state & WIFI_UNDER_KEY_HANDSHAKE) {
++			RTW_INFO(ADPT_FMT"- SoftAP/Mesh - sta under key handshaking, its state = 0x%x\n", ADPT_ARG(adapter), psta->state);
++			rst = _TRUE;
++			break;
++		}
++	}
++	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++	return rst;
++}
++
++/*#define DBG_SWTIMER_BASED_TXBCN*/
++#ifdef CONFIG_SWTIMER_BASED_TXBCN
++void tx_beacon_handlder(struct dvobj_priv *pdvobj)
++{
++#define BEACON_EARLY_TIME		20	/* unit:TU*/
++	_irqL irqL;
++	_list	*plist, *phead;
++	u32 timestamp[2];
++	u32 bcn_interval_us; /* unit : usec */
++	u64 time;
++	u32 cur_tick, time_offset; /* unit : usec */
++	u32 inter_bcn_space_us; /* unit : usec */
++	u32 txbcn_timer_ms; /* unit : ms */
++	int nr_vap, idx, bcn_idx;
++	int i;
++	u8 val8, late = 0;
++	_adapter *padapter = NULL;
++
++	i = 0;
++
++	/* get first ap mode interface */
++	_enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
++	if (rtw_is_list_empty(&pdvobj->ap_if_q.queue) || (pdvobj->nr_ap_if == 0)) {
++		RTW_INFO("[%s] ERROR: ap_if_q is empty!or nr_ap = %d\n", __func__, pdvobj->nr_ap_if);
++		_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
++		return;
++	} else
++		padapter = LIST_CONTAINOR(get_next(&(pdvobj->ap_if_q.queue)), struct _ADAPTER, list);
++	_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
++
++	if (NULL == padapter) {
++		RTW_INFO("[%s] ERROR: no any ap interface!\n", __func__);
++		return;
++	}
++
++
++	bcn_interval_us = DEFAULT_BCN_INTERVAL * NET80211_TU_TO_US;
++	if (0 == bcn_interval_us) {
++		RTW_INFO("[%s] ERROR: beacon interval = 0\n", __func__);
++		return;
++	}
++
++	/* read TSF */
++	timestamp[1] = rtw_read32(padapter, 0x560 + 4);
++	timestamp[0] = rtw_read32(padapter, 0x560);
++	while (timestamp[1]) {
++		time = (0xFFFFFFFF % bcn_interval_us + 1) * timestamp[1] + timestamp[0];
++		timestamp[0] = (u32)time;
++		timestamp[1] = (u32)(time >> 32);
++	}
++	cur_tick = timestamp[0] % bcn_interval_us;
++
++
++	_enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
++
++	nr_vap = (pdvobj->nr_ap_if - 1);
++	if (nr_vap > 0) {
++		inter_bcn_space_us = pdvobj->inter_bcn_space * NET80211_TU_TO_US; /* beacon_interval / (nr_vap+1); */
++		idx = cur_tick / inter_bcn_space_us;
++		if (idx < nr_vap)	/* if (idx < (nr_vap+1))*/
++			bcn_idx = idx + 1;	/* bcn_idx = (idx + 1) % (nr_vap+1);*/
++		else
++			bcn_idx = 0;
++
++		/* to get padapter based on bcn_idx */
++		padapter = NULL;
++		phead = get_list_head(&pdvobj->ap_if_q);
++		plist = get_next(phead);
++		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++			padapter = LIST_CONTAINOR(plist, struct _ADAPTER, list);
++
++			plist = get_next(plist);
++
++			if (i == bcn_idx)
++				break;
++
++			i++;
++		}
++		if ((NULL == padapter) || (i > pdvobj->nr_ap_if)) {
++			RTW_INFO("[%s] ERROR: nr_ap_if = %d, padapter=%p, bcn_idx=%d, index=%d\n",
++				__func__, pdvobj->nr_ap_if, padapter, bcn_idx, i);
++			_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
++			return;
++		}
++#ifdef DBG_SWTIMER_BASED_TXBCN
++		RTW_INFO("BCN_IDX=%d, cur_tick=%d, padapter=%p\n", bcn_idx, cur_tick, padapter);
++#endif
++		if (((idx + 2 == nr_vap + 1) && (idx < nr_vap + 1)) || (0 == bcn_idx)) {
++			time_offset = bcn_interval_us - cur_tick - BEACON_EARLY_TIME * NET80211_TU_TO_US;
++			if ((s32)time_offset < 0)
++				time_offset += inter_bcn_space_us;
++
++		} else {
++			time_offset = (idx + 2) * inter_bcn_space_us - cur_tick - BEACON_EARLY_TIME * NET80211_TU_TO_US;
++			if (time_offset > (inter_bcn_space_us + (inter_bcn_space_us >> 1))) {
++				time_offset -= inter_bcn_space_us;
++				late = 1;
++			}
++		}
++	} else
++		/*#endif*/ { /* MBSSID */
++		time_offset = 2 * bcn_interval_us - cur_tick - BEACON_EARLY_TIME * NET80211_TU_TO_US;
++		if (time_offset > (bcn_interval_us + (bcn_interval_us >> 1))) {
++			time_offset -= bcn_interval_us;
++			late = 1;
++		}
++	}
++	_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
++
++#ifdef DBG_SWTIMER_BASED_TXBCN
++	RTW_INFO("set sw bcn timer %d us\n", time_offset);
++#endif
++	txbcn_timer_ms = time_offset / NET80211_TU_TO_US;
++	_set_timer(&pdvobj->txbcn_timer, txbcn_timer_ms);
++
++	if (padapter) {
++#ifdef CONFIG_BCN_RECOVERY
++		rtw_ap_bcn_recovery(padapter);
++#endif /*CONFIG_BCN_RECOVERY*/
++
++#ifdef CONFIG_BCN_XMIT_PROTECT
++		rtw_ap_bcn_queue_empty_check(padapter, txbcn_timer_ms);
++#endif /*CONFIG_BCN_XMIT_PROTECT*/
++
++#ifdef DBG_SWTIMER_BASED_TXBCN
++		RTW_INFO("padapter=%p, PORT=%d\n", padapter, padapter->hw_port);
++#endif
++		/* bypass TX BCN queue if op ch is switching/waiting */
++		if (!check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING)
++			&& !IS_CH_WAITING(adapter_to_rfctl(padapter))
++		) {
++			/*update_beacon(padapter, _TIM_IE_, NULL, _FALSE, 0);*/
++			/*issue_beacon(padapter, 0);*/
++			send_beacon(padapter);
++		}
++	}
++
++#if 0
++	/* handle any buffered BC/MC frames*/
++	/* Don't dynamically change DIS_ATIM due to HW will auto send ACQ after HIQ empty.*/
++	val8 = *((unsigned char *)priv->beaconbuf + priv->timoffset + 4);
++	if (val8 & 0x01) {
++		process_mcast_dzqueue(priv);
++		priv->pkt_in_dtimQ = 0;
++	}
++#endif
++
++}
++
++void tx_beacon_timer_handlder(void *ctx)
++{
++	struct dvobj_priv *pdvobj = (struct dvobj_priv *)ctx;
++	_adapter *padapter = pdvobj->padapters[0];
++
++	if (padapter)
++		set_tx_beacon_cmd(padapter, 0);
++}
++#endif
++
++void rtw_ap_parse_sta_capability(_adapter *adapter, struct sta_info *sta, u8 *cap)
++{
++	sta->capability = RTW_GET_LE16(cap);
++	if (sta->capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
++		sta->flags |= WLAN_STA_SHORT_PREAMBLE;
++	else
++		sta->flags &= ~WLAN_STA_SHORT_PREAMBLE;
++}
++
++u16 rtw_ap_parse_sta_supported_rates(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len)
++{
++	u8 rate_set[12];
++	u8 rate_num;
++	int i;
++	u16 status = _STATS_SUCCESSFUL_;
++
++	rtw_ies_get_supported_rate(tlv_ies, tlv_ies_len, rate_set, &rate_num);
++	if (rate_num == 0) {
++		RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" with no supported rate\n"
++			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
++		status = _STATS_FAILURE_;
++		goto exit;
++	}
++
++	_rtw_memcpy(sta->bssrateset, rate_set, rate_num);
++	sta->bssratelen = rate_num;
++
++	if (MLME_IS_AP(adapter)) {
++		/* this function force only CCK rates to be bassic rate... */
++		UpdateBrateTblForSoftAP(sta->bssrateset, sta->bssratelen);
++	}
++
++	/* if (hapd->iface->current_mode->mode == HOSTAPD_MODE_IEEE80211G) */ /* ? */
++	sta->flags |= WLAN_STA_NONERP;
++	for (i = 0; i < sta->bssratelen; i++) {
++		if ((sta->bssrateset[i] & 0x7f) > 22) {
++			sta->flags &= ~WLAN_STA_NONERP;
++			break;
++		}
++	}
++
++exit:
++	return status;
++}
++
++u16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems)
++{
++	struct security_priv *sec = &adapter->securitypriv;
++	u8 *wpa_ie;
++	int wpa_ie_len;
++	int group_cipher = 0, pairwise_cipher = 0, gmcs = 0;
++	u32 akm = 0;
++	u8 mfp_opt = MFP_NO;
++	u16 status = _STATS_SUCCESSFUL_;
++
++	sta->dot8021xalg = 0;
++	sta->wpa_psk = 0;
++	sta->wpa_group_cipher = 0;
++	sta->wpa2_group_cipher = 0;
++	sta->wpa_pairwise_cipher = 0;
++	sta->wpa2_pairwise_cipher = 0;
++	_rtw_memset(sta->wpa_ie, 0, sizeof(sta->wpa_ie));
++
++	if ((sec->wpa_psk & BIT(1)) && elems->rsn_ie) {
++		wpa_ie = elems->rsn_ie;
++		wpa_ie_len = elems->rsn_ie_len;
++
++		if (rtw_parse_wpa2_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, &gmcs, &akm, &mfp_opt) == _SUCCESS) {
++			sta->dot8021xalg = 1;/* psk, todo:802.1x */
++			sta->wpa_psk |= BIT(1);
++
++			sta->wpa2_group_cipher = group_cipher & sec->wpa2_group_cipher;
++			sta->wpa2_pairwise_cipher = pairwise_cipher & sec->wpa2_pairwise_cipher;
++
++			sta->akm_suite_type = akm;
++			if (MLME_IS_AP(adapter) && (CHECK_BIT(WLAN_AKM_TYPE_SAE, akm)) && (MFP_NO == mfp_opt)) {
++				status = WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION;
++				goto exit;
++			}
++
++			if (MLME_IS_AP(adapter) && (!CHECK_BIT(sec->akmp, akm))) {
++				status = WLAN_STATUS_AKMP_NOT_VALID;
++				goto exit;
++			}
++
++			if (!sta->wpa2_group_cipher) {
++				status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID;
++				goto exit;
++			}
++
++			if (!sta->wpa2_pairwise_cipher) {
++				status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID;
++				goto exit;
++			}
++
++		} else {
++			status = WLAN_STATUS_INVALID_IE;
++			goto exit;
++		}
++
++	}
++	else if ((sec->wpa_psk & BIT(0)) && elems->wpa_ie) {
++		wpa_ie = elems->wpa_ie;
++		wpa_ie_len = elems->wpa_ie_len;
++
++		if (rtw_parse_wpa_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {
++			sta->dot8021xalg = 1;/* psk, todo:802.1x */
++			sta->wpa_psk |= BIT(0);
++
++			sta->wpa_group_cipher = group_cipher & sec->wpa_group_cipher;
++			sta->wpa_pairwise_cipher = pairwise_cipher & sec->wpa_pairwise_cipher;
++
++			if (!sta->wpa_group_cipher) {
++				status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID;
++				goto exit;
++			}
++
++			if (!sta->wpa_pairwise_cipher) {
++				status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID;
++				goto exit;
++			}
++		} else {
++			status = WLAN_STATUS_INVALID_IE;
++			goto exit;
++		}
++
++	} else {
++		wpa_ie = NULL;
++		wpa_ie_len = 0;
++	}
++
++	if ((sec->mfp_opt == MFP_REQUIRED && mfp_opt < MFP_OPTIONAL)
++		|| (mfp_opt == MFP_REQUIRED && sec->mfp_opt < MFP_OPTIONAL)
++	) {
++		status = WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION;
++		goto exit;
++	}
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(adapter)) {
++		/* MFP is mandatory for secure mesh */
++		if (adapter->mesh_info.mesh_auth_id)
++			sta->flags |= WLAN_STA_MFP;
++	} else
++#endif
++	if (sec->mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL)
++		sta->flags |= WLAN_STA_MFP;
++
++#ifdef CONFIG_IEEE80211W
++	if ((sta->flags & WLAN_STA_MFP)
++		&& (sec->mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL)
++		&& security_type_bip_to_gmcs(sec->dot11wCipher) != gmcs
++	) {
++		status = WLAN_STATUS_CIPHER_REJECTED_PER_POLICY;
++		goto exit;
++	}
++#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (MLME_IS_AP(adapter) &&
++		(sec->auth_type == MLME_AUTHTYPE_SAE) &&
++		(CHECK_BIT(WLAN_AKM_TYPE_SAE, sta->akm_suite_type)) &&
++		(WLAN_AUTH_OPEN == sta->authalg)) {
++		/* WPA3-SAE, PMK caching */
++		if (rtw_cached_pmkid(adapter, sta->cmn.mac_addr) == -1) {
++			RTW_INFO("SAE: No PMKSA cache entry found\n");
++			status = WLAN_STATUS_INVALID_PMKID;
++			goto exit;
++		} else {
++			RTW_INFO("SAE: PMKSA cache entry found\n");
++		}
++	}
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++	if (!MLME_IS_AP(adapter))
++		goto exit;
++
++	sta->flags &= ~(WLAN_STA_WPS | WLAN_STA_MAYBE_WPS);
++	/* if (hapd->conf->wps_state && wpa_ie == NULL) { */ /* todo: to check ap if supporting WPS */
++	if (wpa_ie == NULL) {
++		if (elems->wps_ie) {
++			RTW_INFO("STA included WPS IE in "
++				 "(Re)Association Request - assume WPS is "
++				 "used\n");
++			sta->flags |= WLAN_STA_WPS;
++			/* wpabuf_free(sta->wps_ie); */
++			/* sta->wps_ie = wpabuf_alloc_copy(elems.wps_ie + 4, */
++			/*				elems.wps_ie_len - 4); */
++		} else {
++			RTW_INFO("STA did not include WPA/RSN IE "
++				 "in (Re)Association Request - possible WPS "
++				 "use\n");
++			sta->flags |= WLAN_STA_MAYBE_WPS;
++		}
++
++		/* AP support WPA/RSN, and sta is going to do WPS, but AP is not ready */
++		/* that the selected registrar of AP is _FLASE */
++		if ((sec->wpa_psk > 0)
++			&& (sta->flags & (WLAN_STA_WPS | WLAN_STA_MAYBE_WPS))
++		) {
++			struct mlme_priv *mlme = &adapter->mlmepriv;
++
++			if (mlme->wps_beacon_ie) {
++				u8 selected_registrar = 0;
++
++				rtw_get_wps_attr_content(mlme->wps_beacon_ie, mlme->wps_beacon_ie_len, WPS_ATTR_SELECTED_REGISTRAR, &selected_registrar, NULL);
++
++				if (!selected_registrar) {
++					RTW_INFO("selected_registrar is _FALSE , or AP is not ready to do WPS\n");
++					status = _STATS_UNABLE_HANDLE_STA_;
++					goto exit;
++				}
++			}
++		}
++
++	} else {
++		int copy_len;
++
++		if (sec->wpa_psk == 0) {
++			RTW_INFO("STA " MAC_FMT
++				": WPA/RSN IE in association request, but AP don't support WPA/RSN\n",
++				MAC_ARG(sta->cmn.mac_addr));
++			status = WLAN_STATUS_INVALID_IE;
++			goto exit;
++		}
++
++		if (elems->wps_ie) {
++			RTW_INFO("STA included WPS IE in "
++				 "(Re)Association Request - WPS is "
++				 "used\n");
++			sta->flags |= WLAN_STA_WPS;
++			copy_len = 0;
++		} else
++			copy_len = ((wpa_ie_len + 2) > sizeof(sta->wpa_ie)) ? (sizeof(sta->wpa_ie)) : (wpa_ie_len + 2);
++
++		if (copy_len > 0)
++			_rtw_memcpy(sta->wpa_ie, wpa_ie - 2, copy_len);
++	}
++
++exit:
++	return status;
++}
++
++void rtw_ap_parse_sta_wmm_ie(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len)
++{
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++	unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01};
++	u8 *p;
++
++	sta->flags &= ~WLAN_STA_WME;
++	sta->qos_option = 0;
++	sta->qos_info = 0;
++	sta->has_legacy_ac = _TRUE;
++	sta->uapsd_vo = 0;
++	sta->uapsd_vi = 0;
++	sta->uapsd_be = 0;
++	sta->uapsd_bk = 0;
++
++	if (!mlme->qospriv.qos_option)
++		goto exit;
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(adapter)) {
++		/* QoS is mandatory in mesh */
++		sta->flags |= WLAN_STA_WME;
++	}
++#endif
++
++	p = rtw_get_ie_ex(tlv_ies, tlv_ies_len, WLAN_EID_VENDOR_SPECIFIC, WMM_IE, 6, NULL, NULL);
++	if (!p)
++		goto exit;
++
++	sta->flags |= WLAN_STA_WME;
++	sta->qos_option = 1;
++	sta->qos_info = *(p + 8);
++	sta->max_sp_len = (sta->qos_info >> 5) & 0x3;
++
++	if ((sta->qos_info & 0xf) != 0xf)
++		sta->has_legacy_ac = _TRUE;
++	else
++		sta->has_legacy_ac = _FALSE;
++
++	if (sta->qos_info & 0xf) {
++		if (sta->qos_info & BIT(0))
++			sta->uapsd_vo = BIT(0) | BIT(1);
++		else
++			sta->uapsd_vo = 0;
++
++		if (sta->qos_info & BIT(1))
++			sta->uapsd_vi = BIT(0) | BIT(1);
++		else
++			sta->uapsd_vi = 0;
++
++		if (sta->qos_info & BIT(2))
++			sta->uapsd_bk = BIT(0) | BIT(1);
++		else
++			sta->uapsd_bk = 0;
++
++		if (sta->qos_info & BIT(3))
++			sta->uapsd_be = BIT(0) | BIT(1);
++		else
++			sta->uapsd_be = 0;
++	}
++
++exit:
++	return;
++}
++
++void rtw_ap_parse_sta_ht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems)
++{
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++
++	sta->flags &= ~WLAN_STA_HT;
++
++#ifdef CONFIG_80211N_HT
++	if (mlme->htpriv.ht_option == _FALSE)
++		goto exit;
++
++	/* save HT capabilities in the sta object */
++	_rtw_memset(&sta->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap));
++	if (elems->ht_capabilities && elems->ht_capabilities_len >= sizeof(struct rtw_ieee80211_ht_cap)) {
++		sta->flags |= WLAN_STA_HT;
++		sta->flags |= WLAN_STA_WME;
++		_rtw_memcpy(&sta->htpriv.ht_cap, elems->ht_capabilities, sizeof(struct rtw_ieee80211_ht_cap));
++
++		if (elems->ht_operation && elems->ht_operation_len == HT_OP_IE_LEN) {
++			_rtw_memcpy(sta->htpriv.ht_op, elems->ht_operation, HT_OP_IE_LEN);
++			sta->htpriv.op_present = 1;
++		}
++	}
++exit:
++#endif
++
++	return;
++}
++
++void rtw_ap_parse_sta_vht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems)
++{
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++
++	sta->flags &= ~WLAN_STA_VHT;
++
++#ifdef CONFIG_80211AC_VHT
++	if (mlme->vhtpriv.vht_option == _FALSE)
++		goto exit;
++
++	_rtw_memset(&sta->vhtpriv, 0, sizeof(struct vht_priv));
++	if (elems->vht_capabilities && elems->vht_capabilities_len == VHT_CAP_IE_LEN) {
++		sta->flags |= WLAN_STA_VHT;
++		_rtw_memcpy(sta->vhtpriv.vht_cap, elems->vht_capabilities, VHT_CAP_IE_LEN);
++
++		if (elems->vht_operation && elems->vht_operation_len== VHT_OP_IE_LEN) {
++			_rtw_memcpy(sta->vhtpriv.vht_op, elems->vht_operation, VHT_OP_IE_LEN);
++			sta->vhtpriv.op_present = 1;
++		}
++
++		if (elems->vht_op_mode_notify && elems->vht_op_mode_notify_len == 1) {
++			_rtw_memcpy(&sta->vhtpriv.vht_op_mode_notify, elems->vht_op_mode_notify, 1);
++			sta->vhtpriv.notify_present = 1;
++		}
++	}
++exit:
++#endif
++
++	return;
++}
++
++void rtw_ap_parse_sta_multi_ap_ie(_adapter *adapter, struct sta_info *sta, u8 *ies, int ies_len)
++{
++	sta->flags &= ~WLAN_STA_MULTI_AP;
++
++#ifdef CONFIG_RTW_MULTI_AP
++	if (adapter->multi_ap
++		&& (rtw_get_multi_ap_ie_ext(ies, ies_len) & MULTI_AP_BACKHAUL_STA)
++	) {
++		if (adapter->multi_ap & MULTI_AP_BACKHAUL_BSS) /* with backhaul bss, enable WDS */
++			sta->flags |= WLAN_STA_MULTI_AP | WLAN_STA_WDS;
++		else if (adapter->multi_ap & MULTI_AP_FRONTHAUL_BSS) /* fronthaul bss only */
++			sta->flags |= WLAN_STA_MULTI_AP;
++	}
++#endif
++}
++
++#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++static bool rtw_ap_data_bmc_to_uc(_adapter *adapter
++	, const u8 *da, const u8 *sa, const u8 *ori_ta
++	, u16 os_qid, _list *b2u_list)
++{
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct xmit_priv *xmitpriv = &adapter->xmitpriv;
++	_irqL irqL;
++	_list *head, *list;
++	struct sta_info *sta;
++	char b2u_sta_id[NUM_STA];
++	u8 b2u_sta_num = 0;
++	bool bmc_need = _FALSE;
++	int i;
++
++	_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
++	head = &stapriv->asoc_list;
++	list = get_next(head);
++
++	while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
++		int stainfo_offset;
++
++		sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
++		list = get_next(list);
++	
++		stainfo_offset = rtw_stainfo_offset(stapriv, sta);
++		if (stainfo_offset_valid(stainfo_offset))
++			b2u_sta_id[b2u_sta_num++] = stainfo_offset;
++	}
++	_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
++
++	if (!b2u_sta_num)
++		goto exit;
++
++	for (i = 0; i < b2u_sta_num; i++) {
++		struct xmit_frame *b2uframe;
++		struct pkt_attrib *attrib;
++
++		sta = rtw_get_stainfo_by_offset(stapriv, b2u_sta_id[i]);
++		if (!(sta->state & WIFI_ASOC_STATE)
++			|| _rtw_memcmp(sta->cmn.mac_addr, sa, ETH_ALEN) == _TRUE
++			|| (ori_ta && _rtw_memcmp(sta->cmn.mac_addr, ori_ta, ETH_ALEN) == _TRUE)
++			|| is_broadcast_mac_addr(sta->cmn.mac_addr)
++			|| is_zero_mac_addr(sta->cmn.mac_addr))
++			continue;
++
++		b2uframe = rtw_alloc_xmitframe(xmitpriv, os_qid);
++		if (!b2uframe) {
++			bmc_need = _TRUE;
++			break;
++		}
++
++		attrib = &b2uframe->attrib;
++
++		_rtw_memcpy(attrib->ra, sta->cmn.mac_addr, ETH_ALEN);
++		_rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
++		#ifdef CONFIG_RTW_WDS
++		if (adapter_use_wds(adapter) && (sta->flags & WLAN_STA_WDS)) {
++			_rtw_memcpy(attrib->dst, da, ETH_ALEN);
++			attrib->wds = 1;
++		} else
++		#endif
++			_rtw_memcpy(attrib->dst, attrib->ra, ETH_ALEN);
++		_rtw_memcpy(attrib->src, sa, ETH_ALEN);
++
++		rtw_list_insert_tail(&b2uframe->list, b2u_list);
++	}
++
++exit:
++	return bmc_need;
++}
++
++void dump_ap_b2u_flags(void *sel, _adapter *adapter)
++{
++	RTW_PRINT_SEL(sel, "%4s %4s\n", "src", "fwd");
++	RTW_PRINT_SEL(sel, "0x%02x 0x%02x\n", adapter->b2u_flags_ap_src, adapter->b2u_flags_ap_fwd);
++}
++#endif /* CONFIG_RTW_AP_DATA_BMC_TO_UC */
++
++static int rtw_ap_nexthop_resolve(_adapter *adapter, struct xmit_frame *xframe)
++{
++	struct pkt_attrib *attrib = &xframe->attrib;
++	int ret = _SUCCESS;
++
++#ifdef CONFIG_RTW_WDS
++	if (adapter_use_wds(adapter)
++		&& rtw_wds_nexthop_lookup(adapter, attrib->dst, attrib->ra) == 0
++	) {
++		if (_rtw_memcmp(attrib->dst, attrib->ra, ETH_ALEN) == _FALSE)
++			attrib->wds = 1;
++	} else
++#endif
++		_rtw_memcpy(attrib->ra, attrib->dst, ETH_ALEN);
++
++	return ret;
++}
++
++int rtw_ap_addr_resolve(_adapter *adapter, u16 os_qid, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list)
++{
++	struct pkt_file pktfile;
++	struct ethhdr etherhdr;
++	struct pkt_attrib *attrib;
++	struct rtw_mesh_path *mpath = NULL, *mppath = NULL;
++	u8 is_da_mcast;
++	u8 addr4_need;
++#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++	bool bmc_need = _TRUE;
++#endif
++	int res = _SUCCESS;
++
++	_rtw_open_pktfile(pkt, &pktfile);
++	if (_rtw_pktfile_read(&pktfile, (u8 *)&etherhdr, ETH_HLEN) != ETH_HLEN) {
++		res = _FAIL;
++		goto exit;
++	}
++	
++	xframe->pkt = pkt;
++#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++	_rtw_init_listhead(b2u_list);
++#endif
++
++	is_da_mcast = IS_MCAST(etherhdr.h_dest);
++	if (is_da_mcast) {
++		#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++		if (rtw_ap_src_b2u_policy_chk(adapter->b2u_flags_ap_src, etherhdr.h_dest)
++			&& adapter->registrypriv.wifi_spec == 0
++			&& adapter->xmitpriv.free_xmitframe_cnt > (NR_XMITFRAME / 4)
++		) {
++			bmc_need = rtw_ap_data_bmc_to_uc(adapter
++				, etherhdr.h_dest, etherhdr.h_source, NULL, os_qid, b2u_list);
++			if (bmc_need == _FALSE) {
++				res = RTW_BMC_NO_NEED;
++				goto exit;
++			}
++		}
++		#endif
++	}
++
++	attrib = &xframe->attrib;
++
++	_rtw_memcpy(attrib->dst, etherhdr.h_dest, ETH_ALEN);
++	_rtw_memcpy(attrib->src, etherhdr.h_source, ETH_ALEN);
++	_rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
++
++	if (is_da_mcast)
++		_rtw_memcpy(attrib->ra, attrib->dst, ETH_ALEN);
++	else
++		res = rtw_ap_nexthop_resolve(adapter, xframe);
++
++exit:
++	return res;
++}
++
++int rtw_ap_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta)
++{
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
++	u8 *whdr = get_recvframe_data(rframe);
++	u8 is_ra_bmc = 0;
++	sint ret = _FAIL;
++
++	if (!(MLME_STATE(adapter) & WIFI_ASOC_STATE))
++		goto exit;
++
++	switch (rattrib->to_fr_ds) {
++	case 2:
++		if (IS_MCAST(GetAddr1Ptr(whdr)))
++			goto exit;
++		_rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);
++		_rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);
++		_rtw_memcpy(rattrib->dst, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
++		_rtw_memcpy(rattrib->src, get_addr2_ptr(whdr), ETH_ALEN);
++		_rtw_memcpy(rattrib->bssid, GetAddr1Ptr(whdr), ETH_ALEN);
++		break;
++	case 3:
++		is_ra_bmc = IS_MCAST(GetAddr1Ptr(whdr)) ? 1 : 0;
++		_rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);
++		_rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);
++		_rtw_memcpy(rattrib->dst, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
++		_rtw_memcpy(rattrib->src, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
++		if (!is_ra_bmc)
++			_rtw_memcpy(rattrib->bssid, GetAddr1Ptr(whdr), ETH_ALEN);
++		break;
++	default:
++		ret = RTW_RX_HANDLED; /* don't count for drop */
++		goto exit;
++	}
++
++	*sta = rtw_get_stainfo(stapriv, rattrib->ta);
++	if (*sta == NULL) {
++		if (!is_ra_bmc && !IS_RADAR_DETECTED(adapter_to_rfctl(adapter))) {
++			#ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL
++			RTW_INFO(FUNC_ADPT_FMT" issue_deauth to "MAC_FMT" with reason(7), unknown TA\n"
++				, FUNC_ADPT_ARG(adapter), MAC_ARG(rattrib->ta));
++			issue_deauth(adapter, rattrib->ta, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
++			#endif
++		}
++		ret = RTW_RX_HANDLED;
++		goto exit;
++	}
++
++#ifdef CONFIG_RTW_WDS_AUTO_EN
++	if (rattrib->to_fr_ds == 3 && !(sta->flags & WLAN_STA_WDS))
++		sta->flags |= WLAN_STA_WDS;
++#endif
++
++	process_pwrbit_data(adapter, rframe, *sta);
++	
++	if ((get_frame_sub_type(whdr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE)
++		process_wmmps_data(adapter, rframe, *sta);
++	
++	if (get_frame_sub_type(whdr) & BIT(6)) {
++		/* No data, will not indicate to upper layer, temporily count it here */
++		count_rx_stats(adapter, rframe, *sta);
++		ret = RTW_RX_HANDLED;
++		goto exit;
++	}
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++
++int rtw_ap_rx_msdu_act_check(union recv_frame *rframe
++	, const u8 *da, const u8 *sa
++	, u8 *msdu, enum rtw_rx_llc_hdl llc_hdl
++	, struct xmit_frame **fwd_frame, _list *b2u_list)
++{
++	_adapter *adapter = rframe->u.hdr.adapter;
++	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
++	struct rtw_wds_path *wpath;
++	u8 is_da_bmc = IS_MCAST(da); 
++	u8 is_da_self = !is_da_bmc && _rtw_memcmp(da, adapter_mac_addr(adapter), ETH_ALEN);
++	u8 is_da_peer;
++	int in_wds_tbl = 0;
++	u16 os_qid;
++	struct xmit_frame *xframe;
++	struct pkt_attrib *xattrib;
++	u8 fwd_ra[ETH_ALEN] = {0};
++	int act = 0;
++#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++	bool bmc_need = _TRUE;
++#endif
++
++#ifdef CONFIG_RTW_WDS
++	/* update/create wds info for SA, RA */
++	if (adapter_use_wds(adapter)
++		&& (rframe->u.hdr.psta->state & WIFI_ASOC_STATE)
++		&& _rtw_memcmp(sa, rframe->u.hdr.psta->cmn.mac_addr, ETH_ALEN) == _FALSE
++	) {
++		rtw_rcu_read_lock();
++		wpath = rtw_wds_path_lookup(adapter, sa);
++		if (!wpath)
++			rtw_wds_path_add(adapter, sa, rframe->u.hdr.psta);
++		else {
++			rtw_wds_path_assign_nexthop(wpath, rframe->u.hdr.psta);
++			wpath->last_update = rtw_get_current_time();
++		}
++		rtw_rcu_read_unlock();
++	}
++#endif
++
++	/* SA is self, need no further process */
++	if (_rtw_memcmp(sa, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)
++		goto exit;
++
++	if (is_da_bmc) {
++		/* DA is bmc addr */
++		act |= RTW_RX_MSDU_ACT_INDICATE;
++		if (adapter->mlmepriv.ap_isolate)
++			goto exit;
++		goto fwd_chk;
++
++	}
++	
++	if (is_da_self) {
++		/* DA is self, indicate */
++		act |= RTW_RX_MSDU_ACT_INDICATE;
++		goto exit;
++	}
++
++	/* DA is not self */
++#ifdef CONFIG_RTW_WDS
++	if (adapter_use_wds(adapter))
++		in_wds_tbl = rtw_wds_nexthop_lookup(adapter, da, fwd_ra) == 0;
++#endif
++	if (!in_wds_tbl)
++		is_da_peer = rtw_get_stainfo(&adapter->stapriv, da) ? 1 : 0;
++
++	if (in_wds_tbl || is_da_peer) {
++		/* DA is known (peer or can be forwarded by peer) */
++		if (adapter->mlmepriv.ap_isolate) {
++			#if defined(DBG_RX_DROP_FRAME)
++			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") through peer, ap_isolate\n"
++				, FUNC_ADPT_ARG(adapter), MAC_ARG(da));
++			#endif
++			goto exit;
++		}
++		goto fwd_chk;
++	}
++
++	/* DA is unknown*/
++	act |= RTW_RX_MSDU_ACT_INDICATE;
++	goto exit;
++
++fwd_chk:
++
++	if (adapter->stapriv.asoc_list_cnt <= 1)
++		goto exit;
++
++	os_qid = rtw_os_recv_select_queue(msdu, llc_hdl);
++
++#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++	_rtw_init_listhead(b2u_list);
++
++	if (is_da_bmc
++		&& rtw_ap_fwd_b2u_policy_chk(adapter->b2u_flags_ap_fwd, da, rattrib->to_fr_ds == 3 && !IS_MCAST(rattrib->ra))
++		&& adapter->registrypriv.wifi_spec == 0
++		&& adapter->xmitpriv.free_xmitframe_cnt > (NR_XMITFRAME / 4)
++	) {
++		bmc_need = rtw_ap_data_bmc_to_uc(adapter
++			, da, sa, rframe->u.hdr.psta->cmn.mac_addr
++			, os_qid, b2u_list);
++	}
++
++	if (bmc_need == _TRUE)
++#endif
++	{
++		xframe = rtw_alloc_xmitframe(&adapter->xmitpriv, os_qid);
++		if (!xframe) {
++			#ifdef DBG_TX_DROP_FRAME
++			RTW_INFO("DBG_TX_DROP_FRAME "FUNC_ADPT_FMT" rtw_alloc_xmitframe fail\n"
++				, FUNC_ADPT_ARG(adapter));
++			#endif
++			goto exit;
++		}
++
++		xattrib = &xframe->attrib;
++
++		_rtw_memcpy(xattrib->dst, da, ETH_ALEN);
++		_rtw_memcpy(xattrib->src, sa, ETH_ALEN);
++		_rtw_memcpy(xattrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
++
++		#ifdef CONFIG_RTW_WDS
++		if (in_wds_tbl && _rtw_memcmp(da, fwd_ra, ETH_ALEN) == _FALSE) {
++			_rtw_memcpy(xattrib->ra, fwd_ra, ETH_ALEN);
++			xattrib->wds = 1;			
++		} else
++		#endif
++			_rtw_memcpy(xattrib->ra, da, ETH_ALEN);
++
++		*fwd_frame = xframe;
++	}
++
++	act |= RTW_RX_MSDU_ACT_FORWARD;
++
++exit:
++	return act;
++}
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++void rtw_issue_action_token_req(_adapter *padapter, struct sta_info *pstat)
++{
++	/* Token Request Format
++	 	Category code :		1 Byte
++		Action code : 		1 Byte
++		Element field: 		4 Bytes, the duration of data transmission requested for the station.
++	*/
++
++	u8 val = 0x0;
++	u8 category = RTW_WLAN_CATEGORY_TBTX;
++	u32 tbtx_duration = TBTX_TX_DURATION*1000;
++	u8 *pframe;
++	unsigned short *fctrl;
++	struct xmit_frame		*pmgntframe;
++	struct pkt_attrib		*pattrib;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
++
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		return;
++
++	RTW_DBG("%s: %6ph\n", __FUNCTION__, pstat->cmn.mac_addr);
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++	pattrib->rate = MGN_24M; /* issue action request using OFDM rate? 20190716 Bruce add */ 
++	
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->cmn.mac_addr, ETH_ALEN);
++	_rtw_memcpy((void *)get_addr2_ptr(pwlanhdr), adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++	
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(val), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *)&(tbtx_duration), &(pattrib->pktlen));
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++	padapter->stapriv.last_token_holder = pstat;
++	dump_mgntframe(padapter, pmgntframe);
++
++}
++#endif	/* CONFIG_RTW_TOKEN_BASED_XMIT */
++#endif	/* CONFIG_AP_MODE */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_beamforming.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_beamforming.c
+new file mode 100644
+index 000000000..6e613ec05
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_beamforming.c
+@@ -0,0 +1,2121 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_BEAMFORMING_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++#ifdef CONFIG_BEAMFORMING
++
++#ifdef RTW_BEAMFORMING_VERSION_2
++
++struct ndpa_sta_info {
++	u16 aid:12;
++	u16 feedback_type:1;
++	u16 nc_index:3;
++};
++
++static void _get_txvector_parameter(PADAPTER adapter, struct sta_info *sta, u8 *g_id, u16 *p_aid)
++{
++	struct mlme_priv *mlme;
++	u16 aid;
++	u8 *bssid;
++	u16 val16;
++	u8 i;
++
++
++	mlme = &adapter->mlmepriv;
++
++	if (check_fwstate(mlme, WIFI_AP_STATE)) {
++		/*
++		 * Sent by an AP and addressed to a STA associated with that AP
++		 * or sent by a DLS or TDLS STA in a direct path to
++		 * a DLS or TDLS peer STA
++		 */
++
++		aid = sta->cmn.aid;
++		bssid = adapter_mac_addr(adapter);
++		RTW_INFO("%s: AID=0x%x BSSID=" MAC_FMT "\n",
++			 __FUNCTION__, sta->cmn.aid, MAC_ARG(bssid));
++
++		/* AID[0:8] */
++		aid &= 0x1FF;
++		/* BSSID[44:47] xor BSSID[40:43] */
++		val16 = ((bssid[5] & 0xF0) >> 4) ^ (bssid[5] & 0xF);
++		/* (dec(AID[0:8]) + dec(BSSID)*2^5) mod 2^9 */
++		*p_aid = (aid + (val16 << 5)) & 0x1FF;
++		*g_id = 63;
++	} else if ((check_fwstate(mlme, WIFI_ADHOC_STATE) == _TRUE)
++		   || (check_fwstate(mlme, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
++		/*
++		 * Otherwise, includes
++		 * 1. Sent to an IBSS STA
++		 * 2. Sent by an AP to a non associated STA
++		 * 3. Sent to a STA for which it is not known
++		 *    which condition is applicable
++		 */
++		*p_aid = 0;
++		*g_id = 63;
++	} else {
++		/* Addressed to AP */
++		bssid = sta->cmn.mac_addr;
++		RTW_INFO("%s: BSSID=" MAC_FMT "\n", __FUNCTION__, MAC_ARG(bssid));
++
++		/* BSSID[39:47] */
++		*p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
++		*g_id = 0;
++	}
++
++	RTW_INFO("%s: GROUP_ID=0x%02x PARTIAL_AID=0x%04x\n",
++		 __FUNCTION__, *g_id, *p_aid);
++}
++
++/*
++ * Parameters
++ *	adapter		struct _adapter*
++ *	sta		struct sta_info*
++ *	sta_bf_cap	beamforming capabe of sta
++ *	sounding_dim	Number of Sounding Dimensions
++ *	comp_steering	Compressed Steering Number of Beamformer Antennas Supported
++ */
++static void _get_sta_beamform_cap(PADAPTER adapter, struct sta_info *sta,
++	u8 *sta_bf_cap, u8 *sounding_dim, u8 *comp_steering)
++{
++	struct beamforming_info *info;
++	struct ht_priv *ht;
++#ifdef CONFIG_80211AC_VHT
++	struct vht_priv *vht;
++#endif /* CONFIG_80211AC_VHT */
++	u16 bf_cap;
++
++
++	*sta_bf_cap = 0;
++	*sounding_dim = 0;
++	*comp_steering = 0;
++
++	info = GET_BEAMFORM_INFO(adapter);
++	ht = &adapter->mlmepriv.htpriv;
++#ifdef CONFIG_80211AC_VHT
++	vht = &adapter->mlmepriv.vhtpriv;
++#endif /* CONFIG_80211AC_VHT */
++
++	if (is_supported_ht(sta->wireless_mode) == _TRUE) {
++		/* HT */
++		bf_cap = ht->beamform_cap;
++
++		if (TEST_FLAG(bf_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) {
++			info->beamforming_cap |= BEAMFORMEE_CAP_HT_EXPLICIT;
++			*sta_bf_cap |= BEAMFORMER_CAP_HT_EXPLICIT;
++			*sounding_dim = (bf_cap & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6;
++		}
++		if (TEST_FLAG(bf_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {
++			info->beamforming_cap |= BEAMFORMER_CAP_HT_EXPLICIT;
++			*sta_bf_cap |= BEAMFORMEE_CAP_HT_EXPLICIT;
++			*comp_steering = (bf_cap & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4;
++		}
++	}
++
++#ifdef CONFIG_80211AC_VHT
++	if (is_supported_vht(sta->wireless_mode) == _TRUE) {
++		/* VHT */
++		bf_cap = vht->beamform_cap;
++
++		/* We are SU Beamformee because the STA is SU Beamformer */
++		if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {
++			info->beamforming_cap |= BEAMFORMEE_CAP_VHT_SU;
++			*sta_bf_cap |= BEAMFORMER_CAP_VHT_SU;
++
++			/* We are MU Beamformee because the STA is MU Beamformer */
++			if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) {
++				info->beamforming_cap |= BEAMFORMEE_CAP_VHT_MU;
++				*sta_bf_cap |= BEAMFORMER_CAP_VHT_MU;
++			}
++
++			*sounding_dim = (bf_cap & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12;
++		}
++		/* We are SU Beamformer because the STA is SU Beamformee */
++		if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
++			info->beamforming_cap |= BEAMFORMER_CAP_VHT_SU;
++			*sta_bf_cap |= BEAMFORMEE_CAP_VHT_SU;
++
++			/* We are MU Beamformer because the STA is MU Beamformee */
++			if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) {
++				info->beamforming_cap |= BEAMFORMER_CAP_VHT_MU;
++				*sta_bf_cap |= BEAMFORMEE_CAP_VHT_MU;
++			}
++
++			*comp_steering = (bf_cap & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8;
++		}
++	}
++#endif /* CONFIG_80211AC_VHT */
++}
++
++static u8 _send_ht_ndpa_packet(PADAPTER adapter, u8 *ra, enum channel_width bw)
++{
++	/* General */
++	struct xmit_priv		*pxmitpriv;
++	struct mlme_ext_priv		*pmlmeext;
++	struct mlme_ext_info		*pmlmeinfo;
++	struct xmit_frame		*pmgntframe;
++	/* Beamforming */
++	struct beamforming_info		*info;
++	struct beamformee_entry		*bfee;
++	struct ndpa_sta_info		sta_info;
++	u8 ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xE0, 0x4C};
++	/* MISC */
++	struct pkt_attrib		*attrib;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	enum MGN_RATE txrate;
++	u8 *pframe;
++	u16 duration = 0;
++	u8 aSifsTime = 0;
++
++
++	RTW_INFO("+%s: Send to " MAC_FMT "\n", __FUNCTION__, MAC_ARG(ra));
++
++	pxmitpriv = &adapter->xmitpriv;
++	pmlmeext = &adapter->mlmeextpriv;
++	pmlmeinfo = &pmlmeext->mlmext_info;
++	bfee = rtw_bf_bfee_get_entry_by_addr(adapter, ra);
++	if (!bfee) {
++		RTW_ERR("%s: Cann't find beamformee entry!\n", __FUNCTION__);
++		return _FALSE;
++	}
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (!pmgntframe) {
++		RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__);
++		return _FALSE;
++	}
++
++	txrate = beamforming_get_htndp_tx_rate(GET_PDM_ODM(adapter), bfee->comp_steering_num_of_bfer);
++
++	/* update attribute */
++	attrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(adapter, attrib);
++	/*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */
++	attrib->subtype = WIFI_ACTION_NOACK;
++	attrib->bwmode = bw;
++	/*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */
++	attrib->order = 1;
++	attrib->rate = (u8)txrate;
++	attrib->bf_pkt_type = 0;
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	/* Frame control */
++	pwlanhdr->frame_ctl = 0;
++	set_frame_sub_type(pframe, attrib->subtype);
++	set_order_bit(pframe);
++
++	/* Duration */
++	if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
++		aSifsTime = 10;
++	else
++		aSifsTime = 16;
++	duration = 2 * aSifsTime + 40;
++	if (bw == CHANNEL_WIDTH_40)
++		duration += 87;
++	else
++		duration += 180;
++	set_duration(pframe, duration);
++
++	/* DA */
++	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
++	/* SA */
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
++	/* BSSID */
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
++
++	/* HT control field */
++	SET_HT_CTRL_CSI_STEERING(pframe + 24, 3);
++	SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1);
++
++	/*
++	 * Frame Body
++	 * Category field: vender-specific value, 0x7F
++	 * OUI: 0x00E04C
++	 */
++	_rtw_memcpy(pframe + 28, ActionHdr, 4);
++
++	attrib->pktlen = 32;
++	attrib->last_txcmdsz = attrib->pktlen;
++
++	dump_mgntframe(adapter, pmgntframe);
++
++	return _TRUE;
++}
++
++static u8 _send_vht_ndpa_packet(PADAPTER adapter, u8 *ra, u16 aid, enum channel_width bw)
++{
++	/* General */
++	struct xmit_priv		*pxmitpriv;
++	struct mlme_ext_priv		*pmlmeext;
++	struct xmit_frame		*pmgntframe;
++	/* Beamforming */
++	struct beamforming_info		*info;
++	struct beamformee_entry		*bfee;
++	struct ndpa_sta_info		sta_info;
++	/* MISC */
++	struct pkt_attrib		*attrib;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	u8 *pframe;
++	enum MGN_RATE txrate;
++	u16 duration = 0;
++	u8 sequence = 0, aSifsTime = 0;
++
++
++	RTW_INFO("+%s: Send to " MAC_FMT "\n", __FUNCTION__, MAC_ARG(ra));
++
++	pxmitpriv = &adapter->xmitpriv;
++	pmlmeext = &adapter->mlmeextpriv;
++	info = GET_BEAMFORM_INFO(adapter);
++	bfee = rtw_bf_bfee_get_entry_by_addr(adapter, ra);
++	if (!bfee) {
++		RTW_ERR("%s: Cann't find beamformee entry!\n", __FUNCTION__);
++		return _FALSE;
++	}
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (!pmgntframe) {
++		RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__);
++		return _FALSE;
++	}
++
++	txrate = beamforming_get_vht_ndp_tx_rate(GET_PDM_ODM(adapter), bfee->comp_steering_num_of_bfer);
++
++	/* update attribute */
++	attrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(adapter, attrib);
++	/*pattrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */
++	attrib->subtype = WIFI_NDPA;
++	attrib->bwmode = bw;
++	/*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */
++	attrib->rate = (u8)txrate;
++	attrib->bf_pkt_type = 0;
++
++	_rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET);
++	pframe = pmgntframe->buf_addr + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	/* Frame control */
++	pwlanhdr->frame_ctl = 0;
++	set_frame_sub_type(pframe, attrib->subtype);
++
++	/* Duration */
++	if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
++		aSifsTime = 16;
++	else
++		aSifsTime = 10;
++	duration = 2 * aSifsTime + 44;
++	if (bw == CHANNEL_WIDTH_80)
++		duration += 40;
++	else if (bw == CHANNEL_WIDTH_40)
++		duration += 87;
++	else
++		duration += 180;
++	set_duration(pframe, duration);
++
++	/* RA */
++	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
++
++	/* TA */
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
++
++	/* Sounding Sequence, bit0~1 is reserved */
++	sequence = info->sounding_sequence << 2;
++	if (info->sounding_sequence >= 0x3f)
++		info->sounding_sequence = 0;
++	else
++		info->sounding_sequence++;
++	_rtw_memcpy(pframe + 16, &sequence, 1);
++
++	/* STA Info */
++	/*
++	 * "AID12" Equal to 0 if the STA is an AP, mesh STA or
++	 * STA that is a member of an IBSS
++	 */
++	if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _FALSE)
++		aid = 0;
++	sta_info.aid = aid;
++	/* "Feedback Type" set to 0 for SU */
++	sta_info.feedback_type = 0;
++	/* "Nc Index" reserved if the Feedback Type field indicates SU */
++	sta_info.nc_index = 0;
++	_rtw_memcpy(pframe + 17, (u8 *)&sta_info, 2);
++
++	attrib->pktlen = 19;
++	attrib->last_txcmdsz = attrib->pktlen;
++
++	dump_mgntframe(adapter, pmgntframe);
++
++	return _TRUE;
++}
++
++static u8 _send_vht_mu_ndpa_packet(PADAPTER adapter, enum channel_width bw)
++{
++	/* General */
++	struct xmit_priv		*pxmitpriv;
++	struct mlme_ext_priv		*pmlmeext;
++	struct xmit_frame		*pmgntframe;
++	/* Beamforming */
++	struct beamforming_info		*info;
++	struct sounding_info		*sounding;
++	struct beamformee_entry		*bfee;
++	struct ndpa_sta_info		sta_info;
++	/* MISC */
++	struct pkt_attrib		*attrib;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	enum MGN_RATE txrate;
++	u8 *pframe;
++	u8 *ra = NULL;
++	u16 duration = 0;
++	u8 sequence = 0, aSifsTime = 0;
++	u8 i;
++
++
++	RTW_INFO("+%s\n", __FUNCTION__);
++
++	pxmitpriv = &adapter->xmitpriv;
++	pmlmeext = &adapter->mlmeextpriv;
++	info = GET_BEAMFORM_INFO(adapter);
++	sounding = &info->sounding_info;
++
++	txrate = MGN_VHT2SS_MCS0;
++
++	/*
++	 * Fill the first MU BFee entry (STA1) MAC addr to destination address then
++	 * HW will change A1 to broadcast addr.
++	 * 2015.05.28. Suggested by SD1 Chunchu.
++	 */
++	bfee = &info->bfee_entry[sounding->mu_sounding_list[0]];
++	ra = bfee->mac_addr;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (!pmgntframe) {
++		RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__);
++		return _FALSE;
++	}
++
++	/* update attribute */
++	attrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(adapter, attrib);
++	/*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */
++	attrib->subtype = WIFI_NDPA;
++	attrib->bwmode = bw;
++	/*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */
++	attrib->rate = (u8)txrate;
++	/* Set TxBFPktType of Tx desc to unicast type if there is only one MU STA for HW design */
++	if (info->sounding_info.candidate_mu_bfee_cnt > 1)
++		attrib->bf_pkt_type = 1;
++	else
++		attrib->bf_pkt_type = 0;
++
++	_rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET);
++	pframe = pmgntframe->buf_addr + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	/* Frame control */
++	pwlanhdr->frame_ctl = 0;
++	set_frame_sub_type(pframe, attrib->subtype);
++
++	/* Duration */
++	if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
++		aSifsTime = 16;
++	else
++		aSifsTime = 10;
++	duration = 2 * aSifsTime + 44;
++	if (bw == CHANNEL_WIDTH_80)
++		duration += 40;
++	else if (bw == CHANNEL_WIDTH_40)
++		duration += 87;
++	else
++		duration += 180;
++	set_duration(pframe, duration);
++
++	/* RA */
++	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
++
++	/* TA */
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
++
++	/* Sounding Sequence, bit0~1 is reserved */
++	sequence = info->sounding_sequence << 2;
++	if (info->sounding_sequence >= 0x3f)
++		info->sounding_sequence = 0;
++	else
++		info->sounding_sequence++;
++	_rtw_memcpy(pframe + 16, &sequence, 1);
++
++	attrib->pktlen = 17;
++
++	/*
++	 * Construct STA info. for multiple STAs
++	 * STA Info1, ..., STA Info n
++	 */
++	for (i = 0; i < sounding->candidate_mu_bfee_cnt; i++) {
++		bfee = &info->bfee_entry[sounding->mu_sounding_list[i]];
++		sta_info.aid = bfee->aid;
++		sta_info.feedback_type = 1; /* 1'b1: MU */
++		sta_info.nc_index = 0;
++		_rtw_memcpy(pframe + attrib->pktlen, (u8 *)&sta_info, 2);
++		attrib->pktlen += 2;
++	}
++
++	attrib->last_txcmdsz = attrib->pktlen;
++
++	dump_mgntframe(adapter, pmgntframe);
++
++	return _TRUE;
++}
++
++static u8 _send_bf_report_poll(PADAPTER adapter, u8 *ra, u8 bFinalPoll)
++{
++	/* General */
++	struct xmit_priv *pxmitpriv;
++	struct xmit_frame *pmgntframe;
++	/* MISC */
++	struct pkt_attrib *attrib;
++	struct rtw_ieee80211_hdr *pwlanhdr;
++	u8 *pframe;
++
++
++	RTW_INFO("+%s: Send to " MAC_FMT "\n", __FUNCTION__, MAC_ARG(ra));
++
++	pxmitpriv = &adapter->xmitpriv;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (!pmgntframe) {
++		RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__);
++		return _FALSE;
++	}
++
++	/* update attribute */
++	attrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(adapter, attrib);
++	/*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */
++	attrib->subtype = WIFI_BF_REPORT_POLL;
++	attrib->bwmode = CHANNEL_WIDTH_20;
++	/*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */
++	attrib->rate = MGN_6M;
++	if (bFinalPoll)
++		attrib->bf_pkt_type = 3;
++	else
++		attrib->bf_pkt_type = 2;
++
++	_rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET);
++	pframe = pmgntframe->buf_addr + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	/* Frame control */
++	pwlanhdr->frame_ctl = 0;
++	set_frame_sub_type(pframe, attrib->subtype);
++
++	/* Duration */
++	set_duration(pframe, 100);
++
++	/* RA */
++	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
++
++	/* TA */
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
++
++	/* Feedback Segment Retransmission Bitmap */
++	pframe[16] = 0xFF;
++
++	attrib->pktlen = 17;
++	attrib->last_txcmdsz = attrib->pktlen;
++
++	dump_mgntframe(adapter, pmgntframe);
++
++	return _TRUE;
++}
++
++static void _sounding_update_min_period(PADAPTER adapter, u16 period, u8 leave)
++{
++	struct beamforming_info *info;
++	struct beamformee_entry *bfee;
++	u8 i = 0;
++	u16 min_val = 0xFFFF;
++
++
++	info = GET_BEAMFORM_INFO(adapter);
++
++	if (_TRUE == leave) {
++		/*
++		 * When a BFee left,
++		 * we need to find the latest min sounding period
++		 * from the remaining BFees
++		 */
++		for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
++			bfee = &info->bfee_entry[i];
++			if ((bfee->used == _TRUE)
++			    && (bfee->sound_period < min_val))
++				min_val = bfee->sound_period;
++		}
++
++		if (min_val == 0xFFFF)
++			info->sounding_info.min_sounding_period = 0;
++		else
++			info->sounding_info.min_sounding_period = min_val;
++	} else {
++		if ((info->sounding_info.min_sounding_period == 0)
++		    || (period < info->sounding_info.min_sounding_period))
++			info->sounding_info.min_sounding_period = period;
++	}
++}
++
++static void _sounding_init(struct sounding_info *sounding)
++{
++	_rtw_memset(sounding->su_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_SU);
++	_rtw_memset(sounding->mu_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_MU);
++	sounding->state = SOUNDING_STATE_NONE;
++	sounding->su_bfee_curidx = 0xFF;
++	sounding->candidate_mu_bfee_cnt = 0;
++	sounding->min_sounding_period = 0;
++	sounding->sound_remain_cnt_per_period = 0;
++}
++
++static void _sounding_reset_vars(PADAPTER adapter)
++{
++	struct beamforming_info	*info;
++	struct sounding_info *sounding;
++	u8 idx;
++
++
++	info = GET_BEAMFORM_INFO(adapter);
++	sounding = &info->sounding_info;
++
++	_rtw_memset(sounding->su_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_SU);
++	_rtw_memset(sounding->mu_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_MU);
++	sounding->su_bfee_curidx = 0xFF;
++	sounding->candidate_mu_bfee_cnt = 0;
++
++	/* Clear bSound flag for the new period */
++	for (idx = 0; idx < MAX_BEAMFORMEE_ENTRY_NUM; idx++) {
++		if ((info->bfee_entry[idx].used == _TRUE)
++		    && (info->bfee_entry[idx].sounding == _TRUE)) {
++			info->bfee_entry[idx].sounding = _FALSE;
++			info->bfee_entry[idx].bCandidateSoundingPeer = _FALSE;
++		}
++	}
++}
++
++/*
++ * Return
++ *	0	Prepare sounding list OK
++ *	-1	Fail to prepare sounding list, because no beamformee need to souding
++ *	-2	Fail to prepare sounding list, because beamformee state not ready
++ *
++ */
++static int _sounding_get_list(PADAPTER adapter)
++{
++	struct beamforming_info	*info;
++	struct sounding_info *sounding;
++	struct beamformee_entry *bfee;
++	u8 i, mu_idx = 0, su_idx = 0, not_ready = 0;
++	int ret = 0;
++
++
++	info = GET_BEAMFORM_INFO(adapter);
++	sounding = &info->sounding_info;
++
++	/* Add MU BFee list first because MU priority is higher than SU */
++	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
++		bfee = &info->bfee_entry[i];
++		if (bfee->used == _FALSE)
++			continue;
++
++		if (bfee->state != BEAMFORM_ENTRY_HW_STATE_ADDED) {
++			RTW_ERR("%s: Invalid BFee idx(%d) Hw state=%d\n", __FUNCTION__, i, bfee->state);
++			not_ready++;
++			continue;
++		}
++
++		/*
++		 * Decrease BFee's SoundCnt per period
++		 * If the remain count is 0,
++		 * then it can be sounded at this time
++		 */
++		if (bfee->SoundCnt) {
++			bfee->SoundCnt--;
++			if (bfee->SoundCnt)
++				continue;
++		}
++
++		/*
++		 * <tynli_Note>
++		 *	If the STA supports MU BFee capability then we add it to MUSoundingList directly
++		 *	because we can only sound one STA by unicast NDPA with MU cap enabled to get correct channel info.
++		 *	Suggested by BB team Luke Lee. 2015.11.25.
++		 */
++		if (bfee->cap & BEAMFORMEE_CAP_VHT_MU) {
++			/* MU BFee */
++			if (mu_idx >= MAX_NUM_BEAMFORMEE_MU) {
++				RTW_ERR("%s: Too much MU bfee entry(Limit:%d)\n", __FUNCTION__, MAX_NUM_BEAMFORMEE_MU);
++				continue;
++			}
++
++			if (bfee->bApplySounding == _TRUE) {
++				bfee->bCandidateSoundingPeer = _TRUE;
++				bfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, sounding->min_sounding_period);
++				sounding->mu_sounding_list[mu_idx] = i;
++				mu_idx++;
++			}
++		} else if (bfee->cap & (BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) {
++			/* SU BFee (HT/VHT) */
++			if (su_idx >= MAX_NUM_BEAMFORMEE_SU) {
++				RTW_ERR("%s: Too much SU bfee entry(Limit:%d)\n", __FUNCTION__, MAX_NUM_BEAMFORMEE_SU);
++				continue;
++			}
++
++			if (bfee->bDeleteSounding == _TRUE) {
++				sounding->su_sounding_list[su_idx] = i;
++				su_idx++;
++			} else if ((bfee->bApplySounding == _TRUE)
++			    && (bfee->bSuspendSUCap == _FALSE)) {
++				bfee->bCandidateSoundingPeer = _TRUE;
++				bfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, sounding->min_sounding_period);
++				sounding->su_sounding_list[su_idx] = i;
++				su_idx++;
++			}
++		}
++	}
++
++	sounding->candidate_mu_bfee_cnt = mu_idx;
++
++	if (su_idx + mu_idx == 0) {
++		ret = -1;
++		if (not_ready)
++			ret = -2;
++	}
++
++	RTW_INFO("-%s: There are %d SU and %d MU BFees in this sounding period\n", __FUNCTION__, su_idx, mu_idx);
++
++	return ret;
++}
++
++static void _sounding_handler(PADAPTER adapter)
++{
++	struct beamforming_info	*info;
++	struct sounding_info *sounding;
++	struct beamformee_entry *bfee;
++	u8 su_idx, i;
++	u32 timeout_period = 0;
++	u8 set_timer = _FALSE;
++	int ret = 0;
++	static u16 wait_cnt = 0;
++
++
++	info = GET_BEAMFORM_INFO(adapter);
++	sounding = &info->sounding_info;
++
++	RTW_DBG("+%s: state=%d\n", __FUNCTION__, sounding->state);
++	if ((sounding->state != SOUNDING_STATE_INIT)
++	    && (sounding->state != SOUNDING_STATE_SU_SOUNDDOWN)
++	    && (sounding->state != SOUNDING_STATE_MU_SOUNDDOWN)
++	    && (sounding->state != SOUNDING_STATE_SOUNDING_TIMEOUT)) {
++		RTW_WARN("%s: Invalid State(%d) and return!\n", __FUNCTION__, sounding->state);
++		return;
++	}
++
++	if (sounding->state == SOUNDING_STATE_INIT) {
++		RTW_INFO("%s: Sounding start\n", __FUNCTION__);
++
++		/* Init Var */
++		_sounding_reset_vars(adapter);
++
++		/* Get the sounding list of this sounding period */
++		ret = _sounding_get_list(adapter);
++		if (ret == -1) {
++			wait_cnt = 0;
++			sounding->state = SOUNDING_STATE_NONE;
++			RTW_ERR("%s: No BFees found, set to SOUNDING_STATE_NONE\n", __FUNCTION__);
++			info->sounding_running--;
++			return;
++		}
++		if (ret == -2) {
++			RTW_WARN("%s: Temporarily cann't find BFee to sounding\n", __FUNCTION__);
++			if (wait_cnt < 5) {
++				wait_cnt++;
++			} else {
++				wait_cnt = 0;
++				sounding->state = SOUNDING_STATE_NONE;
++				RTW_ERR("%s: Wait changing state timeout!! Set to SOUNDING_STATE_NONE\n", __FUNCTION__);
++			}
++			info->sounding_running--;
++			return;
++		}
++		if (ret != 0) {
++			wait_cnt = 0;
++			RTW_ERR("%s: Unkown state(%d)!\n", __FUNCTION__, ret);
++			info->sounding_running--;
++			return;
++
++		}
++
++		wait_cnt = 0;
++
++		if (check_fwstate(&adapter->mlmepriv, WIFI_UNDER_SURVEY) == _TRUE) {
++			RTW_INFO("%s: Sounding abort! scanning APs...\n", __FUNCTION__);
++			info->sounding_running--;
++			return;
++		}
++
++		rtw_ps_deny(adapter, PS_DENY_BEAMFORMING);
++		LeaveAllPowerSaveModeDirect(adapter);
++	}
++
++	/* Get non-sound SU BFee index */
++	for (i = 0; i < MAX_NUM_BEAMFORMEE_SU; i++) {
++		su_idx = sounding->su_sounding_list[i];
++		if (su_idx >= MAX_BEAMFORMEE_ENTRY_NUM)
++			continue;
++		bfee = &info->bfee_entry[su_idx];
++		if (_FALSE == bfee->sounding)
++			break;
++	}
++	if (i < MAX_NUM_BEAMFORMEE_SU) {
++		sounding->su_bfee_curidx = su_idx;
++		/* Set to sounding start state */
++		sounding->state = SOUNDING_STATE_SU_START;
++		RTW_DBG("%s: Set to SOUNDING_STATE_SU_START\n", __FUNCTION__);
++
++		bfee->sounding = _TRUE;
++		/* Reset sounding timeout flag for the new sounding */
++		bfee->bSoundingTimeout = _FALSE;
++
++		if (_TRUE == bfee->bDeleteSounding) {
++			u8 res = _FALSE;
++			rtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 0);
++			return;
++		}
++
++		/* Start SU sounding */
++		if (bfee->cap & BEAMFORMEE_CAP_VHT_SU)
++			_send_vht_ndpa_packet(adapter, bfee->mac_addr, bfee->aid, bfee->sound_bw);
++		else if (bfee->cap & BEAMFORMEE_CAP_HT_EXPLICIT)
++			_send_ht_ndpa_packet(adapter, bfee->mac_addr, bfee->sound_bw);
++
++		/* Set sounding timeout timer */
++		_set_timer(&info->sounding_timeout_timer, SU_SOUNDING_TIMEOUT);
++		return;
++	}
++
++	if (sounding->candidate_mu_bfee_cnt > 0) {
++		/*
++		 * If there is no SU BFee then find MU BFee and perform MU sounding
++		 *
++		 * <tynli_note> Need to check the MU starting condition. 2015.12.15.
++		 */
++		sounding->state = SOUNDING_STATE_MU_START;
++		RTW_DBG("%s: Set to SOUNDING_STATE_MU_START\n", __FUNCTION__);
++
++		/* Update MU BFee info */
++		for (i = 0; i < sounding->candidate_mu_bfee_cnt; i++) {
++			bfee = &info->bfee_entry[sounding->mu_sounding_list[i]];
++			bfee->sounding = _TRUE;
++		}
++
++		/* Send MU NDPA */
++		bfee = &info->bfee_entry[sounding->mu_sounding_list[0]];
++		_send_vht_mu_ndpa_packet(adapter, bfee->sound_bw);
++
++		/* Send BF report poll if more than 1 MU STA */
++		for (i = 1; i < sounding->candidate_mu_bfee_cnt; i++) {
++			bfee = &info->bfee_entry[sounding->mu_sounding_list[i]];
++
++			if (i == (sounding->candidate_mu_bfee_cnt - 1))/* The last STA*/
++				_send_bf_report_poll(adapter, bfee->mac_addr, _TRUE);
++			else
++				_send_bf_report_poll(adapter, bfee->mac_addr, _FALSE);
++		}
++
++		sounding->candidate_mu_bfee_cnt = 0;
++
++		/* Set sounding timeout timer */
++		_set_timer(&info->sounding_timeout_timer, MU_SOUNDING_TIMEOUT);
++		return;
++	}
++
++	info->sounding_running--;
++	sounding->state = SOUNDING_STATE_INIT;
++	RTW_INFO("%s: Sounding finished!\n", __FUNCTION__);
++	rtw_ps_deny_cancel(adapter, PS_DENY_BEAMFORMING);
++}
++
++static void _sounding_force_stop(PADAPTER adapter)
++{
++	struct beamforming_info	*info;
++	struct sounding_info *sounding;
++
++	info = GET_BEAMFORM_INFO(adapter);
++	sounding = &info->sounding_info;
++
++	if ((sounding->state == SOUNDING_STATE_SU_START)
++	    || (sounding->state == SOUNDING_STATE_MU_START)) {
++		u8 res = _FALSE;
++		_cancel_timer_ex(&info->sounding_timeout_timer);
++		rtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 1);
++		return;
++	}
++
++	info->sounding_running--;
++	sounding->state = SOUNDING_STATE_INIT;
++	RTW_INFO("%s: Sounding finished!\n", __FUNCTION__);
++	rtw_ps_deny_cancel(adapter, PS_DENY_BEAMFORMING);
++}
++
++static void _sounding_timer_handler(void *FunctionContext)
++{
++	PADAPTER adapter;
++	struct beamforming_info	*info;
++	struct sounding_info *sounding;
++	static u8 delay = 0;
++
++
++	RTW_DBG("+%s\n", __FUNCTION__);
++
++	adapter = (PADAPTER)FunctionContext;
++	info = GET_BEAMFORM_INFO(adapter);
++	sounding = &info->sounding_info;
++
++	if (SOUNDING_STATE_NONE == sounding->state) {
++		RTW_INFO("%s: Stop!\n", __FUNCTION__);
++		if (info->sounding_running)
++			RTW_WARN("%s: souding_running=%d when thread stop!\n",
++				 __FUNCTION__, info->sounding_running);
++		return;
++	}
++
++	_set_timer(&info->sounding_timer, sounding->min_sounding_period);
++
++	if (!info->sounding_running) {
++		if (SOUNDING_STATE_INIT != sounding->state) {
++			RTW_WARN("%s: state(%d) != SOUNDING_STATE_INIT!!\n", __FUNCTION__, sounding->state);
++			sounding->state = SOUNDING_STATE_INIT;
++		}
++		delay = 0;
++		info->sounding_running++;
++		rtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 1);
++	} else {
++		if (delay != 0xFF)
++			delay++;
++		RTW_WARN("%s: souding is still processing...(state:%d, running:%d, delay:%d)\n",
++			 __FUNCTION__, sounding->state, info->sounding_running, delay);
++		if (delay > 3) {
++			RTW_WARN("%s: Stop sounding!!\n", __FUNCTION__);
++			_sounding_force_stop(adapter);
++		}
++	}
++}
++
++static void _sounding_timeout_timer_handler(void *FunctionContext)
++{
++	PADAPTER adapter;
++	struct beamforming_info	*info;
++	struct sounding_info *sounding;
++	struct beamformee_entry *bfee;
++
++
++	RTW_WARN("+%s\n", __FUNCTION__);
++
++	adapter = (PADAPTER)FunctionContext;
++	info = GET_BEAMFORM_INFO(adapter);
++	sounding = &info->sounding_info;
++
++	if (SOUNDING_STATE_SU_START == sounding->state) {
++		sounding->state = SOUNDING_STATE_SOUNDING_TIMEOUT;
++		RTW_ERR("%s: Set to SU SOUNDING_STATE_SOUNDING_TIMEOUT\n", __FUNCTION__);
++		/* SU BFee */
++		bfee = &info->bfee_entry[sounding->su_bfee_curidx];
++		bfee->bSoundingTimeout = _TRUE;
++		RTW_WARN("%s: The BFee entry[%d] is Sounding Timeout!\n", __FUNCTION__, sounding->su_bfee_curidx);
++	} else if (SOUNDING_STATE_MU_START == sounding->state) {
++		sounding->state = SOUNDING_STATE_SOUNDING_TIMEOUT;
++		RTW_ERR("%s: Set to MU SOUNDING_STATE_SOUNDING_TIMEOUT\n", __FUNCTION__);
++	} else {
++		RTW_WARN("%s: unexpected sounding state:0x%02x\n", __FUNCTION__, sounding->state);
++		return;
++	}
++
++	rtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 1);
++}
++
++static struct beamformer_entry *_bfer_get_free_entry(PADAPTER adapter)
++{
++	u8 i = 0;
++	struct beamforming_info *info;
++	struct beamformer_entry *bfer;
++
++
++	info = GET_BEAMFORM_INFO(adapter);
++
++	for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) {
++		bfer = &info->bfer_entry[i];
++		if (bfer->used == _FALSE)
++			return bfer;
++	}
++
++	return NULL;
++}
++
++static struct beamformer_entry *_bfer_get_entry_by_addr(PADAPTER adapter, u8 *ra)
++{
++	u8 i = 0;
++	struct beamforming_info *info;
++	struct beamformer_entry *bfer;
++
++
++	info = GET_BEAMFORM_INFO(adapter);
++
++	for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) {
++		bfer = &info->bfer_entry[i];
++		if (bfer->used == _FALSE)
++			continue;
++		if (_rtw_memcmp(ra, bfer->mac_addr, ETH_ALEN) == _TRUE)
++			return bfer;
++	}
++
++	return NULL;
++}
++
++static struct beamformer_entry *_bfer_add_entry(PADAPTER adapter,
++	struct sta_info *sta, u8 bf_cap, u8 sounding_dim, u8 comp_steering)
++{
++	struct mlme_priv *mlme;
++	struct beamforming_info *info;
++	struct beamformer_entry *bfer;
++	u8 *bssid;
++	u16 val16;
++	u8 i;
++
++
++	mlme = &adapter->mlmepriv;
++	info = GET_BEAMFORM_INFO(adapter);
++
++	bfer = _bfer_get_entry_by_addr(adapter, sta->cmn.mac_addr);
++	if (!bfer) {
++		bfer = _bfer_get_free_entry(adapter);
++		if (!bfer)
++			return NULL;
++	}
++
++	bfer->used = _TRUE;
++	_get_txvector_parameter(adapter, sta, &bfer->g_id, &bfer->p_aid);
++	_rtw_memcpy(bfer->mac_addr, sta->cmn.mac_addr, ETH_ALEN);
++	bfer->cap = bf_cap;
++	bfer->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT;
++	bfer->NumofSoundingDim = sounding_dim;
++
++	if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_MU)) {
++		info->beamformer_mu_cnt += 1;
++		bfer->aid = sta->cmn.aid;
++	} else if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) {
++		info->beamformer_su_cnt += 1;
++
++		/* Record HW idx info */
++		for (i = 0; i < MAX_NUM_BEAMFORMER_SU; i++) {
++			if ((info->beamformer_su_reg_maping & BIT(i)) == 0) {
++				info->beamformer_su_reg_maping |= BIT(i);
++				bfer->su_reg_index = i;
++				break;
++			}
++		}
++		RTW_INFO("%s: Add BFer entry beamformer_su_reg_maping=%#x, su_reg_index=%d\n",
++			 __FUNCTION__, info->beamformer_su_reg_maping, bfer->su_reg_index);
++	}
++
++	return bfer;
++}
++
++static void _bfer_remove_entry(PADAPTER adapter, struct beamformer_entry *entry)
++{
++	struct beamforming_info *info;
++
++
++	info = GET_BEAMFORM_INFO(adapter);
++
++	entry->state = BEAMFORM_ENTRY_HW_STATE_DELETE_INIT;
++
++	if (TEST_FLAG(entry->cap, BEAMFORMER_CAP_VHT_MU)) {
++		info->beamformer_mu_cnt -= 1;
++		_rtw_memset(entry->gid_valid, 0, 8);
++		_rtw_memset(entry->user_position, 0, 16);
++	} else if (TEST_FLAG(entry->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) {
++		info->beamformer_su_cnt -= 1;
++	}
++
++	if (info->beamformer_mu_cnt == 0)
++		info->beamforming_cap &= ~BEAMFORMEE_CAP_VHT_MU;
++	if (info->beamformer_su_cnt == 0)
++		info->beamforming_cap &= ~(BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT);
++}
++
++static u8 _bfer_set_entry_gid(PADAPTER adapter, u8 *addr, u8 *gid, u8 *position)
++{
++	struct beamformer_entry bfer;
++
++	memset(&bfer, 0, sizeof(bfer));
++	memcpy(bfer.mac_addr, addr, ETH_ALEN);
++
++	/* Parsing Membership Status Array */
++	memcpy(bfer.gid_valid, gid, 8);
++
++	/* Parsing User Position Array */
++	memcpy(bfer.user_position, position, 16);
++
++	/* Config HW GID table */
++	rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_GID_TABLE, (u8 *) &bfer,
++			sizeof(bfer), 1);
++
++	return _SUCCESS;
++}
++
++static struct beamformee_entry *_bfee_get_free_entry(PADAPTER adapter)
++{
++	u8 i = 0;
++	struct beamforming_info *info;
++	struct beamformee_entry *bfee;
++
++
++	info = GET_BEAMFORM_INFO(adapter);
++
++	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
++		bfee = &info->bfee_entry[i];
++		if (bfee->used == _FALSE)
++			return bfee;
++	}
++
++	return NULL;
++}
++
++static struct beamformee_entry *_bfee_get_entry_by_addr(PADAPTER adapter, u8 *ra)
++{
++	u8 i = 0;
++	struct beamforming_info *info;
++	struct beamformee_entry *bfee;
++
++
++	info = GET_BEAMFORM_INFO(adapter);
++
++	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
++		bfee = &info->bfee_entry[i];
++		if (bfee->used == _FALSE)
++			continue;
++		if (_rtw_memcmp(ra, bfee->mac_addr, ETH_ALEN) == _TRUE)
++			return bfee;
++	}
++
++	return NULL;
++}
++
++static u8 _bfee_get_first_su_entry_idx(PADAPTER adapter, struct beamformee_entry *ignore)
++{
++	struct beamforming_info *info;
++	struct beamformee_entry *bfee;
++	u8 i;
++
++
++	info = GET_BEAMFORM_INFO(adapter);
++
++	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
++		bfee = &info->bfee_entry[i];
++		if (ignore && (bfee == ignore))
++			continue;
++		if (bfee->used == _FALSE)
++			continue;
++		if ((!TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU))
++		    && TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT))
++			return i;
++	}
++
++	return 0xFF;
++}
++
++/*
++ * Description:
++ *	Get the first entry index of MU Beamformee.
++ *
++ * Return Value:
++ *	Index of the first MU sta, or 0xFF for invalid index.
++ *
++ * 2015.05.25. Created by tynli.
++ *
++ */
++static u8 _bfee_get_first_mu_entry_idx(PADAPTER adapter, struct beamformee_entry *ignore)
++{
++	struct beamforming_info *info;
++	struct beamformee_entry *bfee;
++	u8 i;
++
++
++	info = GET_BEAMFORM_INFO(adapter);
++
++	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
++		bfee = &info->bfee_entry[i];
++		if (ignore && (bfee == ignore))
++			continue;
++		if (bfee->used == _FALSE)
++			continue;
++		if (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU))
++			return i;
++	}
++
++	return 0xFF;
++}
++
++static struct beamformee_entry *_bfee_add_entry(PADAPTER adapter,
++	struct sta_info *sta, u8 bf_cap, u8 sounding_dim, u8 comp_steering)
++{
++	struct mlme_priv *mlme;
++	struct beamforming_info *info;
++	struct beamformee_entry *bfee;
++	u8 *bssid;
++	u16 val16;
++	u8 i;
++
++
++	mlme = &adapter->mlmepriv;
++	info = GET_BEAMFORM_INFO(adapter);
++
++	bfee = _bfee_get_entry_by_addr(adapter, sta->cmn.mac_addr);
++	if (!bfee) {
++		bfee = _bfee_get_free_entry(adapter);
++		if (!bfee)
++			return NULL;
++	}
++
++	bfee->used = _TRUE;
++	bfee->aid = sta->cmn.aid;
++	bfee->mac_id = sta->cmn.mac_id;
++	bfee->sound_bw = sta->cmn.bw_mode;
++
++	_get_txvector_parameter(adapter, sta, &bfee->g_id, &bfee->p_aid);
++	sta->cmn.bf_info.g_id = bfee->g_id;
++	sta->cmn.bf_info.p_aid = bfee->p_aid;
++
++	_rtw_memcpy(bfee->mac_addr, sta->cmn.mac_addr, ETH_ALEN);
++	bfee->txbf = _FALSE;
++	bfee->sounding = _FALSE;
++	bfee->sound_period = 40;
++	_sounding_update_min_period(adapter, bfee->sound_period, _FALSE);
++	bfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, info->sounding_info.min_sounding_period);
++	bfee->cap = bf_cap;
++	bfee->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT;
++
++	bfee->bCandidateSoundingPeer = _FALSE;
++	bfee->bSoundingTimeout = _FALSE;
++	bfee->bDeleteSounding = _FALSE;
++	bfee->bApplySounding = _TRUE;
++
++	bfee->tx_timestamp = 0;
++	bfee->tx_bytes = 0;
++
++	bfee->LogStatusFailCnt = 0;
++	bfee->NumofSoundingDim = sounding_dim;
++	bfee->comp_steering_num_of_bfer = comp_steering;
++	bfee->bSuspendSUCap = _FALSE;
++
++	if (TEST_FLAG(bf_cap, BEAMFORMEE_CAP_VHT_MU)) {
++		info->beamformee_mu_cnt += 1;
++		info->first_mu_bfee_index = _bfee_get_first_mu_entry_idx(adapter, NULL);
++
++		if (_TRUE == info->bEnableSUTxBFWorkAround) {
++			/* When the first MU BFee added, discard SU BFee bfee's capability */
++			if ((info->beamformee_mu_cnt == 1) && (info->beamformee_su_cnt > 0)) {
++				if (info->TargetSUBFee) {
++					info->TargetSUBFee->bSuspendSUCap = _TRUE;
++					info->TargetSUBFee->bDeleteSounding = _TRUE;
++				} else {
++					RTW_ERR("%s: UNEXPECTED!! info->TargetSUBFee is NULL!", __FUNCTION__);
++				}
++				info->TargetSUBFee = NULL;
++				_rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));
++				rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 0);
++			}
++		}
++
++		/* Record HW idx info */
++		for (i = 0; i < MAX_NUM_BEAMFORMEE_MU; i++) {
++			if ((info->beamformee_mu_reg_maping & BIT(i)) == 0) {
++				info->beamformee_mu_reg_maping |= BIT(i);
++				bfee->mu_reg_index = i;
++				break;
++			}
++		}
++		RTW_INFO("%s: Add BFee entry beamformee_mu_reg_maping=%#x, mu_reg_index=%d\n",
++			 __FUNCTION__, info->beamformee_mu_reg_maping, bfee->mu_reg_index);
++
++	} else if (TEST_FLAG(bf_cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) {
++		info->beamformee_su_cnt += 1;
++
++		if (_TRUE == info->bEnableSUTxBFWorkAround) {
++			/* Record the first SU BFee index. We only allow the first SU BFee to be sound */
++			if ((info->beamformee_su_cnt == 1) && (info->beamformee_mu_cnt == 0)) {
++				info->TargetSUBFee = bfee;
++				_rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));
++				bfee->bSuspendSUCap = _FALSE;
++			} else {
++				bfee->bSuspendSUCap = _TRUE;
++			}
++		}
++
++		/* Record HW idx info */
++		for (i = 0; i < MAX_NUM_BEAMFORMEE_SU; i++) {
++			if ((info->beamformee_su_reg_maping & BIT(i)) == 0) {
++				info->beamformee_su_reg_maping |= BIT(i);
++				bfee->su_reg_index = i;
++				break;
++			}
++		}
++		RTW_INFO("%s: Add BFee entry beamformee_su_reg_maping=%#x, su_reg_index=%d\n",
++			 __FUNCTION__, info->beamformee_su_reg_maping, bfee->su_reg_index);
++	}
++
++	return bfee;
++}
++
++static void _bfee_remove_entry(PADAPTER adapter, struct beamformee_entry *entry)
++{
++	struct beamforming_info *info;
++	u8 idx;
++
++
++	info = GET_BEAMFORM_INFO(adapter);
++
++	entry->state = BEAMFORM_ENTRY_HW_STATE_DELETE_INIT;
++
++	if (TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_MU)) {
++		info->beamformee_mu_cnt -= 1;
++		info->first_mu_bfee_index = _bfee_get_first_mu_entry_idx(adapter, entry);
++
++		if (_TRUE == info->bEnableSUTxBFWorkAround) {
++			if ((info->beamformee_mu_cnt == 0) && (info->beamformee_su_cnt > 0)) {
++				idx = _bfee_get_first_su_entry_idx(adapter, NULL);
++				info->TargetSUBFee = &info->bfee_entry[idx];
++				_rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));
++				info->TargetSUBFee->bSuspendSUCap = _FALSE;
++			}
++		}
++	} else if (TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) {
++		info->beamformee_su_cnt -= 1;
++
++		/* When the target SU BFee leaves, disable workaround */
++		if ((_TRUE == info->bEnableSUTxBFWorkAround)
++		    && (entry == info->TargetSUBFee)) {
++			entry->bSuspendSUCap = _TRUE;
++			info->TargetSUBFee = NULL;
++			_rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));
++			rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 0);
++		}
++	}
++
++	if (info->beamformee_mu_cnt == 0)
++		info->beamforming_cap &= ~BEAMFORMER_CAP_VHT_MU;
++	if (info->beamformee_su_cnt == 0)
++		info->beamforming_cap &= ~(BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT);
++
++	_sounding_update_min_period(adapter, 0, _TRUE);
++}
++
++static enum beamforming_cap _bfee_get_entry_cap_by_macid(PADAPTER adapter, u8 macid)
++{
++	struct beamforming_info *info;
++	struct beamformee_entry *bfee;
++	u8 i;
++
++
++	info = GET_BEAMFORM_INFO(adapter);
++
++	for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) {
++		bfee = &info->bfee_entry[i];
++		if (bfee->used == _FALSE)
++			continue;
++		if (bfee->mac_id == macid)
++			return bfee->cap;
++	}
++
++	return BEAMFORMING_CAP_NONE;
++}
++
++static void _beamforming_enter(PADAPTER adapter, void *p)
++{
++	struct mlme_priv *mlme;
++	struct ht_priv *htpriv;
++#ifdef CONFIG_80211AC_VHT
++	struct vht_priv *vhtpriv;
++#endif
++	struct mlme_ext_priv *mlme_ext;
++	struct sta_info *sta, *sta_copy;
++	struct beamforming_info *info;
++	struct beamformer_entry *bfer = NULL;
++	struct beamformee_entry *bfee = NULL;
++	u8 wireless_mode;
++	u8 sta_bf_cap;
++	u8 sounding_dim = 0; /* number of sounding dimensions */
++	u8 comp_steering_num = 0; /* compressed steering number */
++
++
++	mlme = &adapter->mlmepriv;
++	htpriv = &mlme->htpriv;
++#ifdef CONFIG_80211AC_VHT
++	vhtpriv = &mlme->vhtpriv;
++#endif
++	mlme_ext = &adapter->mlmeextpriv;
++	info = GET_BEAMFORM_INFO(adapter);
++
++	sta_copy = (struct sta_info *)p;
++	sta = rtw_get_stainfo(&adapter->stapriv, sta_copy->cmn.mac_addr);
++	if (!sta) {
++		RTW_ERR("%s: Cann't find STA info for " MAC_FMT "\n",
++			__FUNCTION__, MAC_ARG(sta_copy->cmn.mac_addr));
++		return;
++	}
++	if (sta != sta_copy) {
++		RTW_WARN("%s: Origin sta(fake)=%p realsta=%p for " MAC_FMT "\n",
++		__FUNCTION__, sta_copy, sta, MAC_ARG(sta_copy->cmn.mac_addr));
++	}
++
++	/* The current setting does not support Beaforming */
++	wireless_mode = sta->wireless_mode;
++	if ((is_supported_ht(wireless_mode) == _FALSE)
++	    && (is_supported_vht(wireless_mode) == _FALSE)) {
++		RTW_WARN("%s: Not support HT or VHT mode\n", __FUNCTION__);
++		return;
++	}
++
++	if ((0 == htpriv->beamform_cap)
++#ifdef CONFIG_80211AC_VHT
++	    && (0 == vhtpriv->beamform_cap)
++#endif
++	   ) {
++		RTW_INFO("The configuration disabled Beamforming! Skip...\n");
++		return;
++	}
++
++	_get_sta_beamform_cap(adapter, sta,
++			      &sta_bf_cap, &sounding_dim, &comp_steering_num);
++	RTW_INFO("STA Beamforming Capability=0x%02X\n", sta_bf_cap);
++	if (sta_bf_cap == BEAMFORMING_CAP_NONE)
++		return;
++	if ((sta_bf_cap & BEAMFORMEE_CAP_HT_EXPLICIT)
++	    || (sta_bf_cap & BEAMFORMEE_CAP_VHT_SU)
++	    || (sta_bf_cap & BEAMFORMEE_CAP_VHT_MU))
++		sta_bf_cap |= BEAMFORMEE_CAP;
++	if ((sta_bf_cap & BEAMFORMER_CAP_HT_EXPLICIT)
++	    || (sta_bf_cap & BEAMFORMER_CAP_VHT_SU)
++	    || (sta_bf_cap & BEAMFORMER_CAP_VHT_MU))
++		sta_bf_cap |= BEAMFORMER_CAP;
++
++	if (sta_bf_cap & BEAMFORMER_CAP) {
++		/* The other side is beamformer */
++		bfer = _bfer_add_entry(adapter, sta, sta_bf_cap, sounding_dim, comp_steering_num);
++		if (!bfer)
++			RTW_ERR("%s: Fail to allocate bfer entry!\n", __FUNCTION__);
++	}
++	if (sta_bf_cap & BEAMFORMEE_CAP) {
++		/* The other side is beamformee */
++		bfee = _bfee_add_entry(adapter, sta, sta_bf_cap, sounding_dim, comp_steering_num);
++		if (!bfee)
++			RTW_ERR("%s: Fail to allocate bfee entry!\n", __FUNCTION__);
++	}
++	if (!bfer && !bfee)
++		return;
++
++	rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_ENTER, (u8*)sta);
++
++	/* Perform sounding if there is BFee */
++	if ((info->beamformee_su_cnt != 0)
++	    || (info->beamformee_mu_cnt != 0)) {
++		if (SOUNDING_STATE_NONE == info->sounding_info.state) {
++			info->sounding_info.state = SOUNDING_STATE_INIT;
++			/* Start sounding after 2 sec */
++			_set_timer(&info->sounding_timer, 2000);
++		}
++	}
++}
++
++static void _beamforming_reset(PADAPTER adapter)
++{
++	RTW_ERR("%s: Not ready!!\n", __FUNCTION__);
++}
++
++static void _beamforming_leave(PADAPTER adapter, u8 *ra)
++{
++	struct beamforming_info *info;
++	struct beamformer_entry *bfer = NULL;
++	struct beamformee_entry *bfee = NULL;
++	u8 bHwStateAddInit = _FALSE;
++
++
++	RTW_INFO("+%s\n", __FUNCTION__);
++
++	info = GET_BEAMFORM_INFO(adapter);
++	bfer = _bfer_get_entry_by_addr(adapter, ra);
++	bfee = _bfee_get_entry_by_addr(adapter, ra);
++
++	if (!bfer && !bfee) {
++		RTW_WARN("%s: " MAC_FMT " is neither beamforming ee or er!!\n",
++			__FUNCTION__, MAC_ARG(ra));
++		return;
++	}
++
++	if (bfer)
++		_bfer_remove_entry(adapter, bfer);
++
++	if (bfee)
++		_bfee_remove_entry(adapter, bfee);
++
++	rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_LEAVE, ra);
++
++	/* Stop sounding if there is no any BFee */
++	if ((info->beamformee_su_cnt == 0)
++	    && (info->beamformee_mu_cnt == 0)) {
++		_cancel_timer_ex(&info->sounding_timer);
++		_sounding_init(&info->sounding_info);
++	}
++
++	RTW_INFO("-%s\n", __FUNCTION__);
++}
++
++static void _beamforming_sounding_down(PADAPTER adapter, u8 status)
++{
++	struct beamforming_info	*info;
++	struct sounding_info *sounding;
++	struct beamformee_entry *bfee;
++
++
++	info = GET_BEAMFORM_INFO(adapter);
++	sounding = &info->sounding_info;
++
++	RTW_INFO("+%s: sounding=%d, status=0x%02x\n", __FUNCTION__, sounding->state, status);
++
++	if (sounding->state == SOUNDING_STATE_MU_START) {
++		RTW_INFO("%s: MU sounding done\n", __FUNCTION__);
++		sounding->state = SOUNDING_STATE_MU_SOUNDDOWN;
++		RTW_INFO("%s: Set to SOUNDING_STATE_MU_SOUNDDOWN\n", __FUNCTION__);
++		info->SetHalSoundownOnDemandCnt++;
++		rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status);
++	} else if (sounding->state == SOUNDING_STATE_SU_START) {
++		RTW_INFO("%s: SU entry[%d] sounding down\n", __FUNCTION__, sounding->su_bfee_curidx);
++		bfee = &info->bfee_entry[sounding->su_bfee_curidx];
++		sounding->state = SOUNDING_STATE_SU_SOUNDDOWN;
++		RTW_INFO("%s: Set to SOUNDING_STATE_SU_SOUNDDOWN\n", __FUNCTION__);
++
++		/*
++		 * <tynli_note>
++		 *	bfee->bSoundingTimeout this flag still cannot avoid
++		 *	old sound down event happens in the new sounding period.
++		 *	2015.12.10
++		 */
++		if (_TRUE == bfee->bSoundingTimeout) {
++			RTW_WARN("%s: The entry[%d] is bSoundingTimeout!\n", __FUNCTION__, sounding->su_bfee_curidx);
++			bfee->bSoundingTimeout = _FALSE;
++			return;
++		}
++
++		if (_TRUE == status) {
++			/* success */
++			bfee->LogStatusFailCnt = 0;
++			info->SetHalSoundownOnDemandCnt++;
++			rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status);
++		} else if (_TRUE == bfee->bDeleteSounding) {
++			RTW_WARN("%s: Delete entry[%d] sounding info!\n", __FUNCTION__, sounding->su_bfee_curidx);
++			rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status);
++			bfee->bDeleteSounding = _FALSE;
++		} else {
++			bfee->LogStatusFailCnt++;
++			RTW_WARN("%s: LogStatusFailCnt=%d\n", __FUNCTION__, bfee->LogStatusFailCnt);
++			if (bfee->LogStatusFailCnt > 30) {
++				RTW_ERR("%s: LogStatusFailCnt > 30, Stop SOUNDING!!\n", __FUNCTION__);
++				rtw_bf_cmd(adapter, BEAMFORMING_CTRL_LEAVE, bfee->mac_addr, ETH_ALEN, 1);
++			}
++		}
++	} else {
++		RTW_WARN("%s: unexpected sounding state:0x%02x\n", __FUNCTION__, sounding->state);
++		return;
++	}
++
++	rtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 0);
++}
++
++static void _c2h_snd_txbf(PADAPTER adapter, u8 *buf, u8 buf_len)
++{
++	struct beamforming_info	*info;
++	u8 res;
++
++	info = GET_BEAMFORM_INFO(adapter);
++
++	_cancel_timer_ex(&info->sounding_timeout_timer);
++
++	res = C2H_SND_TXBF_GET_SND_RESULT(buf) ? _TRUE : _FALSE;
++	RTW_INFO("+%s: %s\n", __FUNCTION__, res==_TRUE?"Success":"Fail!");
++
++	rtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 1);
++}
++
++/*
++ * Description:
++ *	This function is for phydm only
++ */
++enum beamforming_cap rtw_bf_bfee_get_entry_cap_by_macid(void *mlme, u8 macid)
++{
++	PADAPTER adapter;
++	enum beamforming_cap cap = BEAMFORMING_CAP_NONE;
++
++
++	adapter = mlme_to_adapter((struct mlme_priv *)mlme);
++	cap = _bfee_get_entry_cap_by_macid(adapter, macid);
++
++	return cap;
++}
++
++struct beamformer_entry *rtw_bf_bfer_get_entry_by_addr(PADAPTER adapter, u8 *ra)
++{
++	return _bfer_get_entry_by_addr(adapter, ra);
++}
++
++struct beamformee_entry *rtw_bf_bfee_get_entry_by_addr(PADAPTER adapter, u8 *ra)
++{
++	return _bfee_get_entry_by_addr(adapter, ra);
++}
++
++void rtw_bf_get_ndpa_packet(PADAPTER adapter, union recv_frame *precv_frame)
++{
++	RTW_DBG("+%s\n", __FUNCTION__);
++}
++
++u32 rtw_bf_get_report_packet(PADAPTER adapter, union recv_frame *precv_frame)
++{
++	u32 ret = _SUCCESS;
++	struct beamforming_info *info;
++	struct beamformee_entry *bfee = NULL;
++	u8 *pframe;
++	u32 frame_len;
++	u8 *ta;
++	u8 *frame_body;
++	u8 category, action;
++	u8 *pMIMOCtrlField, *pCSIMatrix;
++	u8 Nc = 0, Nr = 0, CH_W = 0, Ng = 0, CodeBook = 0;
++	u16 CSIMatrixLen = 0;
++
++
++	RTW_INFO("+%s\n", __FUNCTION__);
++
++	info = GET_BEAMFORM_INFO(adapter);
++	pframe = precv_frame->u.hdr.rx_data;
++	frame_len = precv_frame->u.hdr.len;
++
++	/* Memory comparison to see if CSI report is the same with previous one */
++	ta = get_addr2_ptr(pframe);
++	bfee = _bfee_get_entry_by_addr(adapter, ta);
++	if (!bfee)
++		return _FAIL;
++
++	frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
++	category = frame_body[0];
++	action = frame_body[1];
++
++	if ((category == RTW_WLAN_CATEGORY_VHT)
++	    && (action == RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING)) {
++		pMIMOCtrlField = pframe + 26;
++		Nc = (*pMIMOCtrlField) & 0x7;
++		Nr = ((*pMIMOCtrlField) & 0x38) >> 3;
++		CH_W =  (((*pMIMOCtrlField) & 0xC0) >> 6);
++		Ng = (*(pMIMOCtrlField+1)) & 0x3;
++		CodeBook = ((*(pMIMOCtrlField+1)) & 0x4) >> 2;
++		/*
++		 * 24+(1+1+3)+2
++		 * ==> MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)
++		 */
++		pCSIMatrix = pMIMOCtrlField + 3 + Nc;
++		CSIMatrixLen = frame_len - 26 - 3 - Nc;
++		info->TargetCSIInfo.bVHT = _TRUE;
++	} else if ((category == RTW_WLAN_CATEGORY_HT)
++		   && (action == RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING)) {
++		pMIMOCtrlField = pframe + 26;
++		Nc = (*pMIMOCtrlField) & 0x3;
++		Nr = ((*pMIMOCtrlField) & 0xC) >> 2;
++		CH_W = ((*pMIMOCtrlField) & 0x10) >> 4;
++		Ng = ((*pMIMOCtrlField) & 0x60) >> 5;
++		CodeBook = ((*(pMIMOCtrlField+1)) & 0x6) >> 1;
++		/*
++		 * 24+(1+1+6)+2
++		 * ==> MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)
++		 */
++		pCSIMatrix = pMIMOCtrlField + 6 + Nr;
++		CSIMatrixLen = frame_len  - 26 - 6 - Nr;
++		info->TargetCSIInfo.bVHT = _FALSE;
++	}
++
++	/* Update current CSI report info */
++	if ((_TRUE == info->bEnableSUTxBFWorkAround)
++	    && (info->TargetSUBFee == bfee)) {
++		if ((info->TargetCSIInfo.Nc != Nc) || (info->TargetCSIInfo.Nr != Nr) ||
++			(info->TargetCSIInfo.ChnlWidth != CH_W) || (info->TargetCSIInfo.Ng != Ng) ||
++			(info->TargetCSIInfo.CodeBook != CodeBook)) {
++			info->TargetCSIInfo.Nc = Nc;
++			info->TargetCSIInfo.Nr = Nr;
++			info->TargetCSIInfo.ChnlWidth = CH_W;
++			info->TargetCSIInfo.Ng = Ng;
++			info->TargetCSIInfo.CodeBook = CodeBook;
++
++			rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 1);
++		}
++	}
++
++	RTW_INFO("%s: pkt type=%d-%d, Nc=%d, Nr=%d, CH_W=%d, Ng=%d, CodeBook=%d\n",
++		 __FUNCTION__, category, action, Nc, Nr, CH_W, Ng, CodeBook);
++
++	return ret;
++}
++
++u8 rtw_bf_send_vht_gid_mgnt_packet(PADAPTER adapter, u8 *ra, u8 *gid, u8 *position)
++{
++	/* General */
++	struct xmit_priv *xmitpriv;
++	struct mlme_priv *mlmepriv;
++	struct xmit_frame *pmgntframe;
++	/* MISC */
++	struct pkt_attrib *attrib;
++	struct rtw_ieee80211_hdr *wlanhdr;
++	u8 *pframe, *ptr;
++
++
++	xmitpriv = &adapter->xmitpriv;
++	mlmepriv = &adapter->mlmepriv;
++
++	pmgntframe = alloc_mgtxmitframe(xmitpriv);
++	if (!pmgntframe)
++		return _FALSE;
++
++	/* update attribute */
++	attrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(adapter, attrib);
++	attrib->rate = MGN_6M;
++	attrib->bwmode = CHANNEL_WIDTH_20;
++	attrib->subtype = WIFI_ACTION;
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)pmgntframe->buf_addr + TXDESC_OFFSET;
++	wlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	wlanhdr->frame_ctl = 0;
++	set_frame_sub_type(pframe, attrib->subtype);
++	set_duration(pframe, 0);
++	SetFragNum(pframe, 0);
++	SetSeqNum(pframe, 0);
++
++	_rtw_memcpy(wlanhdr->addr1, ra, ETH_ALEN);
++	_rtw_memcpy(wlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
++	_rtw_memcpy(wlanhdr->addr3, get_bssid(mlmepriv), ETH_ALEN);
++
++	pframe[24] = RTW_WLAN_CATEGORY_VHT;
++	pframe[25] = RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT;
++	/* Set Membership Status Array */
++	ptr = pframe + 26;
++	_rtw_memcpy(ptr, gid, 8);
++	/* Set User Position Array */
++	ptr = pframe + 34;
++	_rtw_memcpy(ptr, position, 16);
++
++	attrib->pktlen = 54;
++	attrib->last_txcmdsz = attrib->pktlen;
++
++	dump_mgntframe(adapter, pmgntframe);
++
++	return _TRUE;
++}
++
++/*
++ * Description:
++ *	On VHT GID management frame by an MU beamformee.
++ */
++void rtw_bf_get_vht_gid_mgnt_packet(PADAPTER adapter, union recv_frame *precv_frame)
++{
++	u8 *pframe;
++	u8 *ta, *gid, *position;
++
++
++	RTW_DBG("+%s\n", __FUNCTION__);
++
++	pframe = precv_frame->u.hdr.rx_data;
++
++	/* Get address by Addr2 */
++	ta = get_addr2_ptr(pframe);
++	/* Remove signaling TA */
++	ta[0] &= 0xFE;
++
++	/* Membership Status Array */
++	gid = pframe + 26;
++	/* User Position Array */
++	position= pframe + 34;
++
++	_bfer_set_entry_gid(adapter, ta, gid, position);
++}
++
++void rtw_bf_init(PADAPTER adapter)
++{
++	struct beamforming_info	*info;
++
++
++	info = GET_BEAMFORM_INFO(adapter);
++	info->beamforming_cap = BEAMFORMING_CAP_NONE;
++	info->beamforming_state = BEAMFORMING_STATE_IDLE;
++/*
++	info->bfee_entry[MAX_BEAMFORMEE_ENTRY_NUM];
++	info->bfer_entry[MAX_BEAMFORMER_ENTRY_NUM];
++*/
++	info->sounding_sequence = 0;
++	info->beamformee_su_cnt = 0;
++	info->beamformer_su_cnt = 0;
++	info->beamformee_su_reg_maping = 0;
++	info->beamformer_su_reg_maping = 0;
++	info->beamformee_mu_cnt = 0;
++	info->beamformer_mu_cnt = 0;
++	info->beamformee_mu_reg_maping = 0;
++	info->first_mu_bfee_index = 0xFF;
++	info->mu_bfer_curidx = 0xFF;
++	info->cur_csi_rpt_rate = HALMAC_OFDM24;
++
++	_sounding_init(&info->sounding_info);
++	rtw_init_timer(&info->sounding_timer, adapter, _sounding_timer_handler, adapter);
++	rtw_init_timer(&info->sounding_timeout_timer, adapter, _sounding_timeout_timer_handler, adapter);
++
++	info->SetHalBFEnterOnDemandCnt = 0;
++	info->SetHalBFLeaveOnDemandCnt = 0;
++	info->SetHalSoundownOnDemandCnt = 0;
++
++	info->bEnableSUTxBFWorkAround = _TRUE;
++	info->TargetSUBFee = NULL;
++
++	info->sounding_running = 0;
++}
++
++void rtw_bf_cmd_hdl(PADAPTER adapter, u8 type, u8 *pbuf)
++{
++	switch (type) {
++	case BEAMFORMING_CTRL_ENTER:
++		_beamforming_enter(adapter, pbuf);
++		break;
++
++	case BEAMFORMING_CTRL_LEAVE:
++		if (pbuf == NULL)
++			_beamforming_reset(adapter);
++		else
++			_beamforming_leave(adapter, pbuf);
++		break;
++
++	case BEAMFORMING_CTRL_START_PERIOD:
++		_sounding_handler(adapter);
++		break;
++
++	case BEAMFORMING_CTRL_END_PERIOD:
++		_beamforming_sounding_down(adapter, *pbuf);
++		break;
++
++	case BEAMFORMING_CTRL_SET_GID_TABLE:
++		rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_SET_GID_TABLE, pbuf);
++		break;
++
++	case BEAMFORMING_CTRL_SET_CSI_REPORT:
++		rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_CSI_REPORT, pbuf);
++		break;
++
++	default:
++		break;
++	}
++}
++
++u8 rtw_bf_cmd(PADAPTER adapter, s32 type, u8 *pbuf, s32 size, u8 enqueue)
++{
++	struct cmd_obj *ph2c;
++	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++	struct cmd_priv	*pcmdpriv = &adapter->cmdpriv;
++	u8 *wk_buf;
++	u8 res = _SUCCESS;
++
++
++	if (!enqueue) {
++		rtw_bf_cmd_hdl(adapter, type, pbuf);
++		goto exit;
++	}
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	if (pbuf != NULL) {
++		wk_buf = rtw_zmalloc(size);
++		if (wk_buf == NULL) {
++			rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
++			rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
++			res = _FAIL;
++			goto exit;
++		}
++
++		_rtw_memcpy(wk_buf, pbuf, size);
++	} else {
++		wk_buf = NULL;
++		size = 0;
++	}
++
++	pdrvextra_cmd_parm->ec_id = BEAMFORMING_WK_CID;
++	pdrvextra_cmd_parm->type = type;
++	pdrvextra_cmd_parm->size = size;
++	pdrvextra_cmd_parm->pbuf = wk_buf;
++
++	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++	return res;
++}
++
++void rtw_bf_update_attrib(PADAPTER adapter, struct pkt_attrib *attrib, struct sta_info *sta)
++{
++	if (sta) {
++		attrib->txbf_g_id = sta->cmn.bf_info.g_id;
++		attrib->txbf_p_aid = sta->cmn.bf_info.p_aid;
++	}
++}
++
++void rtw_bf_c2h_handler(PADAPTER adapter, u8 id, u8 *buf, u8 buf_len)
++{
++	switch (id) {
++	case CMD_ID_C2H_SND_TXBF:
++		_c2h_snd_txbf(adapter, buf, buf_len);
++		break;
++	}
++}
++
++#define toMbps(bytes, secs)	(rtw_division64(bytes >> 17, secs))
++void rtw_bf_update_traffic(PADAPTER adapter)
++{
++	struct beamforming_info	*info;
++	struct sounding_info *sounding;
++	struct beamformee_entry *bfee;
++	struct sta_info *sta;
++	u8 bfee_cnt, sounding_idx, i;
++	u16 tp[MAX_BEAMFORMEE_ENTRY_NUM] = {0};
++	u8 tx_rate[MAX_BEAMFORMEE_ENTRY_NUM] = {0};
++	u64 tx_bytes, last_bytes;
++	u32 time;
++	systime last_timestamp;
++	u8 set_timer = _FALSE;
++
++
++	info = GET_BEAMFORM_INFO(adapter);
++	sounding = &info->sounding_info;
++
++	/* Check any bfee exist? */
++	bfee_cnt = info->beamformee_su_cnt + info->beamformee_mu_cnt;
++	if (bfee_cnt == 0)
++		return;
++
++	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
++		bfee = &info->bfee_entry[i];
++		if (_FALSE == bfee->used)
++			continue;
++
++		sta = rtw_get_stainfo(&adapter->stapriv, bfee->mac_addr);
++		if (!sta) {
++			RTW_ERR("%s: Cann't find sta_info for " MAC_FMT "!\n", __FUNCTION__, MAC_ARG(bfee->mac_addr));
++			continue;
++		}
++
++		last_timestamp = bfee->tx_timestamp;
++		last_bytes = bfee->tx_bytes;
++		bfee->tx_timestamp = rtw_get_current_time();
++		bfee->tx_bytes = sta->sta_stats.tx_bytes;
++		if (last_timestamp) {
++			if (bfee->tx_bytes >= last_bytes)
++				tx_bytes = bfee->tx_bytes - last_bytes;
++			else
++				tx_bytes = bfee->tx_bytes + (~last_bytes);
++			time = rtw_get_time_interval_ms(last_timestamp, bfee->tx_timestamp);
++			time = (time > 1000) ? time/1000 : 1;
++			tp[i] = toMbps(tx_bytes, time);
++			tx_rate[i] = rtw_get_current_tx_rate(adapter, sta);
++			RTW_INFO("%s: BFee idx(%d), MadId(%d), TxTP=%lld bytes (%d Mbps), txrate=%d\n",
++				 __FUNCTION__, i, bfee->mac_id, tx_bytes, tp[i], tx_rate[i]);
++		}
++	}
++
++	sounding_idx = phydm_get_beamforming_sounding_info(GET_PDM_ODM(adapter), tp, MAX_BEAMFORMEE_ENTRY_NUM, tx_rate);
++
++	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
++		bfee = &info->bfee_entry[i];
++		if (_FALSE == bfee->used) {
++			if (sounding_idx & BIT(i))
++				RTW_WARN("%s: bfee(%d) not in used but need sounding?!\n", __FUNCTION__, i);
++			continue;
++		}
++
++		if (sounding_idx & BIT(i)) {
++			if (_FALSE == bfee->bApplySounding) {
++				bfee->bApplySounding = _TRUE;
++				bfee->SoundCnt = 0;
++				set_timer = _TRUE;
++			}
++		} else {
++			if (_TRUE == bfee->bApplySounding) {
++				bfee->bApplySounding = _FALSE;
++				bfee->bDeleteSounding = _TRUE;
++				bfee->SoundCnt = 0;
++				set_timer = _TRUE;
++			}
++		}
++	}
++
++	if (_TRUE == set_timer) {
++		if (SOUNDING_STATE_NONE == info->sounding_info.state) {
++			info->sounding_info.state = SOUNDING_STATE_INIT;
++			_set_timer(&info->sounding_timer, 0);
++		}
++	}
++}
++
++#else /* !RTW_BEAMFORMING_VERSION_2 */
++
++/*PHYDM_BF - (BEAMFORMING_SUPPORT == 1)*/
++u32	rtw_beamforming_get_report_frame(PADAPTER	 Adapter, union recv_frame *precv_frame)
++{
++	u32	ret = _SUCCESS;
++
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
++	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
++
++	ret = beamforming_get_report_frame(pDM_Odm, precv_frame);
++	return ret;
++}
++
++void	rtw_beamforming_get_ndpa_frame(PADAPTER	 Adapter, union recv_frame *precv_frame)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
++	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
++
++	beamforming_get_ndpa_frame(pDM_Odm, precv_frame);
++}
++
++void	beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
++
++	/*(BEAMFORMING_SUPPORT == 1)- for PHYDM beamfoming*/
++	switch (type) {
++	case BEAMFORMING_CTRL_ENTER: {
++		struct sta_info	*psta = (void *)pbuf;
++		u16			staIdx = psta->cmn.mac_id;
++
++		beamforming_enter(pDM_Odm, staIdx, adapter_mac_addr(psta->padapter));
++		break;
++	}
++	case BEAMFORMING_CTRL_LEAVE:
++		beamforming_leave(pDM_Odm, pbuf);
++		break;
++	default:
++		break;
++
++	}
++}
++
++u8	beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enqueue)
++{
++	struct cmd_obj	*ph2c;
++	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
++	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8	res = _SUCCESS;
++
++	/*20170214 ad_hoc mode and mp_mode not support BF*/
++	if ((padapter->registrypriv.mp_mode == 1)
++		|| (pmlmeinfo->state == WIFI_FW_ADHOC_STATE))
++		return res;
++
++	if (enqueue) {
++		u8	*wk_buf;
++
++		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++		if (ph2c == NULL) {
++			res = _FAIL;
++			goto exit;
++		}
++
++		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++		if (pdrvextra_cmd_parm == NULL) {
++			rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++			res = _FAIL;
++			goto exit;
++		}
++
++		if (pbuf != NULL) {
++			wk_buf = rtw_zmalloc(size);
++			if (wk_buf == NULL) {
++				rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
++				rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
++				res = _FAIL;
++				goto exit;
++			}
++
++			_rtw_memcpy(wk_buf, pbuf, size);
++		} else {
++			wk_buf = NULL;
++			size = 0;
++		}
++
++		pdrvextra_cmd_parm->ec_id = BEAMFORMING_WK_CID;
++		pdrvextra_cmd_parm->type = type;
++		pdrvextra_cmd_parm->size = size;
++		pdrvextra_cmd_parm->pbuf = wk_buf;
++
++		init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++	} else
++		beamforming_wk_hdl(padapter, type, pbuf);
++
++exit:
++
++
++	return res;
++}
++
++void update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta)
++{
++	if (psta) {
++		pattrib->txbf_g_id = psta->cmn.bf_info.g_id;
++		pattrib->txbf_p_aid = psta->cmn.bf_info.p_aid;
++	}
++}
++#endif /* !RTW_BEAMFORMING_VERSION_2 */
++
++#endif /* CONFIG_BEAMFORMING */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_br_ext.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_br_ext.c
+new file mode 100644
+index 000000000..9a0effd8b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_br_ext.c
+@@ -0,0 +1,1581 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_BR_EXT_C_
++
++#ifdef __KERNEL__
++	#include <linux/if_arp.h>
++	#include <net/ip.h>
++	#include <net/ipx.h>
++	#include <linux/atalk.h>
++	#include <linux/udp.h>
++	#include <linux/if_pppox.h>
++#endif
++
++#if 1	/* rtw_wifi_driver */
++	#include <drv_types.h>
++#else	/* rtw_wifi_driver */
++	#include "./8192cd_cfg.h"
++
++	#ifndef __KERNEL__
++		#include "./sys-support.h"
++	#endif
++
++	#include "./8192cd.h"
++	#include "./8192cd_headers.h"
++	#include "./8192cd_br_ext.h"
++	#include "./8192cd_debug.h"
++#endif /* rtw_wifi_driver */
++
++#ifdef CL_IPV6_PASS
++	#ifdef __KERNEL__
++		#include <linux/ipv6.h>
++		#include <linux/icmpv6.h>
++		#include <net/ndisc.h>
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
++			#include <net/ip6_checksum.h>
++		#else
++			#include <net/checksum.h>
++		#endif
++	#endif
++#endif
++
++#ifdef CONFIG_BR_EXT
++
++/* #define BR_EXT_DEBUG */
++
++#define NAT25_IPV4		01
++#define NAT25_IPV6		02
++#define NAT25_IPX		03
++#define NAT25_APPLE		04
++#define NAT25_PPPOE		05
++
++#define RTL_RELAY_TAG_LEN (ETH_ALEN)
++#define TAG_HDR_LEN		4
++
++#define MAGIC_CODE		0x8186
++#define MAGIC_CODE_LEN	2
++#define WAIT_TIME_PPPOE	5	/* waiting time for pppoe server in sec */
++
++/*-----------------------------------------------------------------
++  How database records network address:
++           0    1    2    3    4    5    6    7    8    9   10
++        |----|----|----|----|----|----|----|----|----|----|----|
++  IPv4  |type|                             |      IP addr      |
++  IPX   |type|      Net addr     |          Node addr          |
++  IPX   |type|      Net addr     |Sckt addr|
++  Apple |type| Network |node|
++  PPPoE |type|   SID   |           AC MAC            |
++-----------------------------------------------------------------*/
++
++
++/* Find a tag in pppoe frame and return the pointer */
++static __inline__ unsigned char *__nat25_find_pppoe_tag(struct pppoe_hdr *ph, unsigned short type)
++{
++	unsigned char *cur_ptr, *start_ptr;
++	unsigned short tagLen, tagType;
++
++	start_ptr = cur_ptr = (unsigned char *)ph->tag;
++	while ((cur_ptr - start_ptr) < ntohs(ph->length)) {
++		/* prevent un-alignment access */
++		tagType = (unsigned short)((cur_ptr[0] << 8) + cur_ptr[1]);
++		tagLen  = (unsigned short)((cur_ptr[2] << 8) + cur_ptr[3]);
++		if (tagType == type)
++			return cur_ptr;
++		cur_ptr = cur_ptr + TAG_HDR_LEN + tagLen;
++	}
++	return 0;
++}
++
++
++static __inline__ int __nat25_add_pppoe_tag(struct sk_buff *skb, struct pppoe_tag *tag)
++{
++	struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN);
++	int data_len;
++
++	data_len = tag->tag_len + TAG_HDR_LEN;
++	if (skb_tailroom(skb) < data_len) {
++		_DEBUG_ERR("skb_tailroom() failed in add SID tag!\n");
++		return -1;
++	}
++
++	skb_put(skb, data_len);
++	/* have a room for new tag */
++	memmove(((unsigned char *)ph->tag + data_len), (unsigned char *)ph->tag, ntohs(ph->length));
++	ph->length = htons(ntohs(ph->length) + data_len);
++	memcpy((unsigned char *)ph->tag, tag, data_len);
++	return data_len;
++}
++
++static int skb_pull_and_merge(struct sk_buff *skb, unsigned char *src, int len)
++{
++	int tail_len;
++	unsigned long end, tail;
++
++	if ((src + len) > skb_tail_pointer(skb) || skb->len < len)
++		return -1;
++
++	tail = (unsigned long)skb_tail_pointer(skb);
++	end = (unsigned long)src + len;
++	if (tail < end)
++		return -1;
++
++	tail_len = (int)(tail - end);
++	if (tail_len > 0)
++		memmove(src, src + len, tail_len);
++
++	skb_trim(skb, skb->len - len);
++	return 0;
++}
++
++static __inline__ unsigned long __nat25_timeout(_adapter *priv)
++{
++	unsigned long timeout;
++
++	timeout = jiffies - NAT25_AGEING_TIME * HZ;
++
++	return timeout;
++}
++
++
++static __inline__ int  __nat25_has_expired(_adapter *priv,
++		struct nat25_network_db_entry *fdb)
++{
++	if (time_before_eq(fdb->ageing_timer, __nat25_timeout(priv)))
++		return 1;
++
++	return 0;
++}
++
++
++static __inline__ void __nat25_generate_ipv4_network_addr(unsigned char *networkAddr,
++		unsigned int *ipAddr)
++{
++	memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
++
++	networkAddr[0] = NAT25_IPV4;
++	memcpy(networkAddr + 7, (unsigned char *)ipAddr, 4);
++}
++
++
++static __inline__ void __nat25_generate_ipx_network_addr_with_node(unsigned char *networkAddr,
++		unsigned int *ipxNetAddr, unsigned char *ipxNodeAddr)
++{
++	memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
++
++	networkAddr[0] = NAT25_IPX;
++	memcpy(networkAddr + 1, (unsigned char *)ipxNetAddr, 4);
++	memcpy(networkAddr + 5, ipxNodeAddr, 6);
++}
++
++
++static __inline__ void __nat25_generate_ipx_network_addr_with_socket(unsigned char *networkAddr,
++		unsigned int *ipxNetAddr, unsigned short *ipxSocketAddr)
++{
++	memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
++
++	networkAddr[0] = NAT25_IPX;
++	memcpy(networkAddr + 1, (unsigned char *)ipxNetAddr, 4);
++	memcpy(networkAddr + 5, (unsigned char *)ipxSocketAddr, 2);
++}
++
++
++static __inline__ void __nat25_generate_apple_network_addr(unsigned char *networkAddr,
++		unsigned short *network, unsigned char *node)
++{
++	memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
++
++	networkAddr[0] = NAT25_APPLE;
++	memcpy(networkAddr + 1, (unsigned char *)network, 2);
++	networkAddr[3] = *node;
++}
++
++
++static __inline__ void __nat25_generate_pppoe_network_addr(unsigned char *networkAddr,
++		unsigned char *ac_mac, unsigned short *sid)
++{
++	memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
++
++	networkAddr[0] = NAT25_PPPOE;
++	memcpy(networkAddr + 1, (unsigned char *)sid, 2);
++	memcpy(networkAddr + 3, (unsigned char *)ac_mac, 6);
++}
++
++
++#ifdef CL_IPV6_PASS
++static  void __nat25_generate_ipv6_network_addr(unsigned char *networkAddr,
++		unsigned int *ipAddr)
++{
++	memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
++
++	networkAddr[0] = NAT25_IPV6;
++	memcpy(networkAddr + 1, (unsigned char *)ipAddr, 16);
++}
++
++
++static unsigned char *scan_tlv(unsigned char *data, int len, unsigned char tag, unsigned char len8b)
++{
++	while (len > 0) {
++		if (*data == tag && *(data + 1) == len8b && len >= len8b * 8)
++			return data + 2;
++
++		len -= (*(data + 1)) * 8;
++		data += (*(data + 1)) * 8;
++	}
++	return NULL;
++}
++
++
++static int update_nd_link_layer_addr(unsigned char *data, int len, unsigned char *replace_mac)
++{
++	struct icmp6hdr *icmphdr = (struct icmp6hdr *)data;
++	unsigned char *mac;
++
++	if (icmphdr->icmp6_type == NDISC_ROUTER_SOLICITATION) {
++		if (len >= 8) {
++			mac = scan_tlv(&data[8], len - 8, 1, 1);
++			if (mac) {
++				RTW_INFO("Router Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
++					mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
++					replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);
++				memcpy(mac, replace_mac, 6);
++				return 1;
++			}
++		}
++	} else if (icmphdr->icmp6_type == NDISC_ROUTER_ADVERTISEMENT) {
++		if (len >= 16) {
++			mac = scan_tlv(&data[16], len - 16, 1, 1);
++			if (mac) {
++				RTW_INFO("Router Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
++					mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
++					replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);
++				memcpy(mac, replace_mac, 6);
++				return 1;
++			}
++		}
++	} else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_SOLICITATION) {
++		if (len >= 24) {
++			mac = scan_tlv(&data[24], len - 24, 1, 1);
++			if (mac) {
++				RTW_INFO("Neighbor Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
++					mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
++					replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);
++				memcpy(mac, replace_mac, 6);
++				return 1;
++			}
++		}
++	} else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_ADVERTISEMENT) {
++		if (len >= 24) {
++			mac = scan_tlv(&data[24], len - 24, 2, 1);
++			if (mac) {
++				RTW_INFO("Neighbor Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
++					mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
++					replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);
++				memcpy(mac, replace_mac, 6);
++				return 1;
++			}
++		}
++	} else if (icmphdr->icmp6_type == NDISC_REDIRECT) {
++		if (len >= 40) {
++			mac = scan_tlv(&data[40], len - 40, 2, 1);
++			if (mac) {
++				RTW_INFO("Redirect,  replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
++					mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
++					replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);
++				memcpy(mac, replace_mac, 6);
++				return 1;
++			}
++		}
++	}
++	return 0;
++}
++
++#ifdef SUPPORT_RX_UNI2MCAST
++static void convert_ipv6_mac_to_mc(struct sk_buff *skb)
++{
++	struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN);
++	unsigned char *dst_mac = skb->data;
++
++	/* dst_mac[0] = 0xff; */
++	/* dst_mac[1] = 0xff; */
++	/*modified by qinjunjie,ipv6 multicast address ix 0x33-33-xx-xx-xx-xx*/
++	dst_mac[0] = 0x33;
++	dst_mac[1] = 0x33;
++	memcpy(&dst_mac[2], &iph->daddr.s6_addr32[3], 4);
++#if defined(__LINUX_2_6__)
++	/*modified by qinjunjie,warning:should not remove next line*/
++	skb->pkt_type = PACKET_MULTICAST;
++#endif
++}
++#endif /* CL_IPV6_PASS */
++#endif /* SUPPORT_RX_UNI2MCAST */
++
++
++static __inline__ int __nat25_network_hash(unsigned char *networkAddr)
++{
++	if (networkAddr[0] == NAT25_IPV4) {
++		unsigned long x;
++
++		x = networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10];
++
++		return x & (NAT25_HASH_SIZE - 1);
++	} else if (networkAddr[0] == NAT25_IPX) {
++		unsigned long x;
++
++		x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^
++		    networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10];
++
++		return x & (NAT25_HASH_SIZE - 1);
++	} else if (networkAddr[0] == NAT25_APPLE) {
++		unsigned long x;
++
++		x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3];
++
++		return x & (NAT25_HASH_SIZE - 1);
++	} else if (networkAddr[0] == NAT25_PPPOE) {
++		unsigned long x;
++
++		x = networkAddr[0] ^ networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ networkAddr[6] ^ networkAddr[7] ^ networkAddr[8];
++
++		return x & (NAT25_HASH_SIZE - 1);
++	}
++#ifdef CL_IPV6_PASS
++	else if (networkAddr[0] == NAT25_IPV6) {
++		unsigned long x;
++
++		x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^
++		    networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10] ^
++		    networkAddr[11] ^ networkAddr[12] ^ networkAddr[13] ^ networkAddr[14] ^ networkAddr[15] ^
++		    networkAddr[16];
++
++		return x & (NAT25_HASH_SIZE - 1);
++	}
++#endif
++	else {
++		unsigned long x = 0;
++		int i;
++
++		for (i = 0; i < MAX_NETWORK_ADDR_LEN; i++)
++			x ^= networkAddr[i];
++
++		return x & (NAT25_HASH_SIZE - 1);
++	}
++}
++
++
++static __inline__ void __network_hash_link(_adapter *priv,
++		struct nat25_network_db_entry *ent, int hash)
++{
++	/* Caller must _enter_critical_bh already! */
++	/* _irqL irqL; */
++	/* _enter_critical_bh(&priv->br_ext_lock, &irqL); */
++
++	ent->next_hash = priv->nethash[hash];
++	if (ent->next_hash != NULL)
++		ent->next_hash->pprev_hash = &ent->next_hash;
++	priv->nethash[hash] = ent;
++	ent->pprev_hash = &priv->nethash[hash];
++
++	/* _exit_critical_bh(&priv->br_ext_lock, &irqL); */
++}
++
++
++static __inline__ void __network_hash_unlink(struct nat25_network_db_entry *ent)
++{
++	/* Caller must _enter_critical_bh already! */
++	/* _irqL irqL; */
++	/* _enter_critical_bh(&priv->br_ext_lock, &irqL); */
++
++	*(ent->pprev_hash) = ent->next_hash;
++	if (ent->next_hash != NULL)
++		ent->next_hash->pprev_hash = ent->pprev_hash;
++	ent->next_hash = NULL;
++	ent->pprev_hash = NULL;
++
++	/* _exit_critical_bh(&priv->br_ext_lock, &irqL); */
++}
++
++
++static int __nat25_db_network_lookup_and_replace(_adapter *priv,
++		struct sk_buff *skb, unsigned char *networkAddr)
++{
++	struct nat25_network_db_entry *db;
++	_irqL irqL;
++	_enter_critical_bh(&priv->br_ext_lock, &irqL);
++
++	db = priv->nethash[__nat25_network_hash(networkAddr)];
++	while (db != NULL) {
++		if (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) {
++			if (!__nat25_has_expired(priv, db)) {
++				/* replace the destination mac address */
++				memcpy(skb->data, db->macAddr, ETH_ALEN);
++				atomic_inc(&db->use_count);
++
++#ifdef CL_IPV6_PASS
++				RTW_INFO("NAT25: Lookup M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
++					 "%02x%02x%02x%02x%02x%02x\n",
++					 db->macAddr[0],
++					 db->macAddr[1],
++					 db->macAddr[2],
++					 db->macAddr[3],
++					 db->macAddr[4],
++					 db->macAddr[5],
++					 db->networkAddr[0],
++					 db->networkAddr[1],
++					 db->networkAddr[2],
++					 db->networkAddr[3],
++					 db->networkAddr[4],
++					 db->networkAddr[5],
++					 db->networkAddr[6],
++					 db->networkAddr[7],
++					 db->networkAddr[8],
++					 db->networkAddr[9],
++					 db->networkAddr[10],
++					 db->networkAddr[11],
++					 db->networkAddr[12],
++					 db->networkAddr[13],
++					 db->networkAddr[14],
++					 db->networkAddr[15],
++					 db->networkAddr[16]);
++#else
++				RTW_INFO("NAT25: Lookup M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
++					 db->macAddr[0],
++					 db->macAddr[1],
++					 db->macAddr[2],
++					 db->macAddr[3],
++					 db->macAddr[4],
++					 db->macAddr[5],
++					 db->networkAddr[0],
++					 db->networkAddr[1],
++					 db->networkAddr[2],
++					 db->networkAddr[3],
++					 db->networkAddr[4],
++					 db->networkAddr[5],
++					 db->networkAddr[6],
++					 db->networkAddr[7],
++					 db->networkAddr[8],
++					 db->networkAddr[9],
++					 db->networkAddr[10]);
++#endif
++			}
++			_exit_critical_bh(&priv->br_ext_lock, &irqL);
++			return 1;
++		}
++
++		db = db->next_hash;
++	}
++
++	_exit_critical_bh(&priv->br_ext_lock, &irqL);
++	return 0;
++}
++
++
++static void __nat25_db_network_insert(_adapter *priv,
++		      unsigned char *macAddr, unsigned char *networkAddr)
++{
++	struct nat25_network_db_entry *db;
++	int hash;
++	_irqL irqL;
++	_enter_critical_bh(&priv->br_ext_lock, &irqL);
++
++	hash = __nat25_network_hash(networkAddr);
++	db = priv->nethash[hash];
++	while (db != NULL) {
++		if (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) {
++			memcpy(db->macAddr, macAddr, ETH_ALEN);
++			db->ageing_timer = jiffies;
++			_exit_critical_bh(&priv->br_ext_lock, &irqL);
++			return;
++		}
++
++		db = db->next_hash;
++	}
++
++	db = (struct nat25_network_db_entry *) rtw_malloc(sizeof(*db));
++	if (db == NULL) {
++		_exit_critical_bh(&priv->br_ext_lock, &irqL);
++		return;
++	}
++
++	memcpy(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN);
++	memcpy(db->macAddr, macAddr, ETH_ALEN);
++	atomic_set(&db->use_count, 1);
++	db->ageing_timer = jiffies;
++
++	__network_hash_link(priv, db, hash);
++
++	_exit_critical_bh(&priv->br_ext_lock, &irqL);
++}
++
++
++static void __nat25_db_print(_adapter *priv)
++{
++	_irqL irqL;
++	_enter_critical_bh(&priv->br_ext_lock, &irqL);
++
++#ifdef BR_EXT_DEBUG
++	static int counter = 0;
++	int i, j;
++	struct nat25_network_db_entry *db;
++
++	counter++;
++	if ((counter % 16) != 0)
++		return;
++
++	for (i = 0, j = 0; i < NAT25_HASH_SIZE; i++) {
++		db = priv->nethash[i];
++
++		while (db != NULL) {
++#ifdef CL_IPV6_PASS
++			panic_printk("NAT25: DB(%d) H(%02d) C(%d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
++				     "%02x%02x%02x%02x%02x%02x\n",
++				     j,
++				     i,
++				     atomic_read(&db->use_count),
++				     db->macAddr[0],
++				     db->macAddr[1],
++				     db->macAddr[2],
++				     db->macAddr[3],
++				     db->macAddr[4],
++				     db->macAddr[5],
++				     db->networkAddr[0],
++				     db->networkAddr[1],
++				     db->networkAddr[2],
++				     db->networkAddr[3],
++				     db->networkAddr[4],
++				     db->networkAddr[5],
++				     db->networkAddr[6],
++				     db->networkAddr[7],
++				     db->networkAddr[8],
++				     db->networkAddr[9],
++				     db->networkAddr[10],
++				     db->networkAddr[11],
++				     db->networkAddr[12],
++				     db->networkAddr[13],
++				     db->networkAddr[14],
++				     db->networkAddr[15],
++				     db->networkAddr[16]);
++#else
++			panic_printk("NAT25: DB(%d) H(%02d) C(%d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
++				     j,
++				     i,
++				     atomic_read(&db->use_count),
++				     db->macAddr[0],
++				     db->macAddr[1],
++				     db->macAddr[2],
++				     db->macAddr[3],
++				     db->macAddr[4],
++				     db->macAddr[5],
++				     db->networkAddr[0],
++				     db->networkAddr[1],
++				     db->networkAddr[2],
++				     db->networkAddr[3],
++				     db->networkAddr[4],
++				     db->networkAddr[5],
++				     db->networkAddr[6],
++				     db->networkAddr[7],
++				     db->networkAddr[8],
++				     db->networkAddr[9],
++				     db->networkAddr[10]);
++#endif
++			j++;
++
++			db = db->next_hash;
++		}
++	}
++#endif
++
++	_exit_critical_bh(&priv->br_ext_lock, &irqL);
++}
++
++
++
++
++/*
++ *	NAT2.5 interface
++ */
++
++void nat25_db_cleanup(_adapter *priv)
++{
++	int i;
++	_irqL irqL;
++	_enter_critical_bh(&priv->br_ext_lock, &irqL);
++
++	for (i = 0; i < NAT25_HASH_SIZE; i++) {
++		struct nat25_network_db_entry *f;
++		f = priv->nethash[i];
++		while (f != NULL) {
++			struct nat25_network_db_entry *g;
++
++			g = f->next_hash;
++			if (priv->scdb_entry == f) {
++				memset(priv->scdb_mac, 0, ETH_ALEN);
++				memset(priv->scdb_ip, 0, 4);
++				priv->scdb_entry = NULL;
++			}
++			__network_hash_unlink(f);
++			rtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry));
++
++			f = g;
++		}
++	}
++
++	_exit_critical_bh(&priv->br_ext_lock, &irqL);
++}
++
++
++void nat25_db_expire(_adapter *priv)
++{
++	int i;
++	_irqL irqL;
++	_enter_critical_bh(&priv->br_ext_lock, &irqL);
++
++	/* if(!priv->ethBrExtInfo.nat25_disable) */
++	{
++		for (i = 0; i < NAT25_HASH_SIZE; i++) {
++			struct nat25_network_db_entry *f;
++			f = priv->nethash[i];
++
++			while (f != NULL) {
++				struct nat25_network_db_entry *g;
++				g = f->next_hash;
++
++				if (__nat25_has_expired(priv, f)) {
++					if (atomic_dec_and_test(&f->use_count)) {
++#ifdef BR_EXT_DEBUG
++#ifdef CL_IPV6_PASS
++						panic_printk("NAT25 Expire H(%02d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
++							"%02x%02x%02x%02x%02x%02x\n",
++							     i,
++							     f->macAddr[0],
++							     f->macAddr[1],
++							     f->macAddr[2],
++							     f->macAddr[3],
++							     f->macAddr[4],
++							     f->macAddr[5],
++							     f->networkAddr[0],
++							     f->networkAddr[1],
++							     f->networkAddr[2],
++							     f->networkAddr[3],
++							     f->networkAddr[4],
++							     f->networkAddr[5],
++							     f->networkAddr[6],
++							     f->networkAddr[7],
++							     f->networkAddr[8],
++							     f->networkAddr[9],
++							     f->networkAddr[10],
++							     f->networkAddr[11],
++							     f->networkAddr[12],
++							     f->networkAddr[13],
++							     f->networkAddr[14],
++							     f->networkAddr[15],
++							f->networkAddr[16]);
++#else
++
++						panic_printk("NAT25 Expire H(%02d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
++							     i,
++							     f->macAddr[0],
++							     f->macAddr[1],
++							     f->macAddr[2],
++							     f->macAddr[3],
++							     f->macAddr[4],
++							     f->macAddr[5],
++							     f->networkAddr[0],
++							     f->networkAddr[1],
++							     f->networkAddr[2],
++							     f->networkAddr[3],
++							     f->networkAddr[4],
++							     f->networkAddr[5],
++							     f->networkAddr[6],
++							     f->networkAddr[7],
++							     f->networkAddr[8],
++							     f->networkAddr[9],
++							f->networkAddr[10]);
++#endif
++#endif
++						if (priv->scdb_entry == f) {
++							memset(priv->scdb_mac, 0, ETH_ALEN);
++							memset(priv->scdb_ip, 0, 4);
++							priv->scdb_entry = NULL;
++						}
++						__network_hash_unlink(f);
++						rtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry));
++					}
++				}
++
++				f = g;
++			}
++		}
++	}
++
++	_exit_critical_bh(&priv->br_ext_lock, &irqL);
++}
++
++
++#ifdef SUPPORT_TX_MCAST2UNI
++static int checkIPMcAndReplace(_adapter *priv, struct sk_buff *skb, unsigned int *dst_ip)
++{
++	struct stat_info	*pstat;
++	struct list_head	*phead, *plist;
++	int i;
++
++	phead = &priv->asoc_list;
++	plist = phead->next;
++
++	while (plist != phead) {
++		pstat = list_entry(plist, struct stat_info, asoc_list);
++		plist = plist->next;
++
++		if (pstat->ipmc_num == 0)
++			continue;
++
++		for (i = 0; i < MAX_IP_MC_ENTRY; i++) {
++			if (pstat->ipmc[i].used && !memcmp(&pstat->ipmc[i].mcmac[3], ((unsigned char *)dst_ip) + 1, 3)) {
++				memcpy(skb->data, pstat->ipmc[i].mcmac, ETH_ALEN);
++				return 1;
++			}
++		}
++	}
++	return 0;
++}
++#endif
++
++int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method)
++{
++	unsigned short protocol;
++	unsigned char networkAddr[MAX_NETWORK_ADDR_LEN];
++
++	if (skb == NULL)
++		return -1;
++
++	if ((method <= NAT25_MIN) || (method >= NAT25_MAX))
++		return -1;
++
++	protocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN));
++
++	/*---------------------------------------------------*/
++	/*                 Handle IP frame                  */
++	/*---------------------------------------------------*/
++	if (protocol == __constant_htons(ETH_P_IP)) {
++		struct iphdr *iph = (struct iphdr *)(skb->data + ETH_HLEN);
++
++		if (((unsigned char *)(iph) + (iph->ihl << 2)) >= (skb->data + ETH_HLEN + skb->len)) {
++			DEBUG_WARN("NAT25: malformed IP packet !\n");
++			return -1;
++		}
++
++		switch (method) {
++		case NAT25_CHECK:
++			return -1;
++
++		case NAT25_INSERT: {
++			/* some muticast with source IP is all zero, maybe other case is illegal */
++			/* in class A, B, C, host address is all zero or all one is illegal */
++			if (iph->saddr == 0)
++				return 0;
++			RTW_INFO("NAT25: Insert IP, SA=%08x, DA=%08x\n", iph->saddr, iph->daddr);
++			__nat25_generate_ipv4_network_addr(networkAddr, &iph->saddr);
++			/* record source IP address and , source mac address into db */
++			__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
++
++			__nat25_db_print(priv);
++		}
++		return 0;
++
++		case NAT25_LOOKUP: {
++			RTW_INFO("NAT25: Lookup IP, SA=%08x, DA=%08x\n", iph->saddr, iph->daddr);
++#ifdef SUPPORT_TX_MCAST2UNI
++			if (priv->pshare->rf_ft_var.mc2u_disable ||
++			    ((((OPMODE & (WIFI_STATION_STATE | WIFI_ASOC_STATE))
++			       == (WIFI_STATION_STATE | WIFI_ASOC_STATE)) &&
++			      !checkIPMcAndReplace(priv, skb, &iph->daddr)) ||
++			     (OPMODE & WIFI_ADHOC_STATE)))
++#endif
++			{
++				__nat25_generate_ipv4_network_addr(networkAddr, &iph->daddr);
++
++				if (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) {
++					if (*((unsigned char *)&iph->daddr + 3) == 0xff) {
++						/* L2 is unicast but L3 is broadcast, make L2 bacome broadcast */
++						RTW_INFO("NAT25: Set DA as boardcast\n");
++						memset(skb->data, 0xff, ETH_ALEN);
++					} else {
++						/* forward unknow IP packet to upper TCP/IP */
++						RTW_INFO("NAT25: Replace DA with BR's MAC\n");
++						if ((*(u32 *)priv->br_mac) == 0 && (*(u16 *)(priv->br_mac + 4)) == 0) {
++							void netdev_br_init(struct net_device *netdev);
++							printk("Re-init netdev_br_init() due to br_mac==0!\n");
++							netdev_br_init(priv->pnetdev);
++						}
++						memcpy(skb->data, priv->br_mac, ETH_ALEN);
++					}
++				}
++			}
++		}
++		return 0;
++
++		default:
++			return -1;
++		}
++	}
++
++	/*---------------------------------------------------*/
++	/*                 Handle ARP frame                 */
++	/*---------------------------------------------------*/
++	else if (protocol == __constant_htons(ETH_P_ARP)) {
++		struct arphdr *arp = (struct arphdr *)(skb->data + ETH_HLEN);
++		unsigned char *arp_ptr = (unsigned char *)(arp + 1);
++		unsigned int *sender, *target;
++
++		if (arp->ar_pro != __constant_htons(ETH_P_IP)) {
++			DEBUG_WARN("NAT25: arp protocol unknown (%4x)!\n", htons(arp->ar_pro));
++			return -1;
++		}
++
++		switch (method) {
++		case NAT25_CHECK:
++			return 0;	/* skb_copy for all ARP frame */
++
++		case NAT25_INSERT: {
++			RTW_INFO("NAT25: Insert ARP, MAC=%02x%02x%02x%02x%02x%02x\n", arp_ptr[0],
++				arp_ptr[1], arp_ptr[2], arp_ptr[3], arp_ptr[4], arp_ptr[5]);
++
++			/* change to ARP sender mac address to wlan STA address */
++			memcpy(arp_ptr, GET_MY_HWADDR(priv), ETH_ALEN);
++
++			arp_ptr += arp->ar_hln;
++			sender = (unsigned int *)arp_ptr;
++
++			__nat25_generate_ipv4_network_addr(networkAddr, sender);
++
++			__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
++
++			__nat25_db_print(priv);
++		}
++		return 0;
++
++		case NAT25_LOOKUP: {
++			RTW_INFO("NAT25: Lookup ARP\n");
++
++			arp_ptr += arp->ar_hln;
++			sender = (unsigned int *)arp_ptr;
++			arp_ptr += (arp->ar_hln + arp->ar_pln);
++			target = (unsigned int *)arp_ptr;
++
++			__nat25_generate_ipv4_network_addr(networkAddr, target);
++
++			__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
++
++			/* change to ARP target mac address to Lookup result */
++			arp_ptr = (unsigned char *)(arp + 1);
++			arp_ptr += (arp->ar_hln + arp->ar_pln);
++			memcpy(arp_ptr, skb->data, ETH_ALEN);
++		}
++		return 0;
++
++		default:
++			return -1;
++		}
++	}
++
++	/*---------------------------------------------------*/
++	/*         Handle IPX and Apple Talk frame          */
++	/*---------------------------------------------------*/
++	else if ((protocol == __constant_htons(ETH_P_IPX)) ||
++		 (protocol == __constant_htons(ETH_P_ATALK)) ||
++		 (protocol == __constant_htons(ETH_P_AARP))) {
++		unsigned char ipx_header[2] = {0xFF, 0xFF};
++		struct ipxhdr	*ipx = NULL;
++		struct elapaarp	*ea = NULL;
++		struct ddpehdr	*ddp = NULL;
++		unsigned char *framePtr = skb->data + ETH_HLEN;
++
++		if (protocol == __constant_htons(ETH_P_IPX)) {
++			RTW_INFO("NAT25: Protocol=IPX (Ethernet II)\n");
++			ipx = (struct ipxhdr *)framePtr;
++		} else { /* if(protocol <= __constant_htons(ETH_FRAME_LEN)) */
++			if (!memcmp(ipx_header, framePtr, 2)) {
++				RTW_INFO("NAT25: Protocol=IPX (Ethernet 802.3)\n");
++				ipx = (struct ipxhdr *)framePtr;
++			} else {
++				unsigned char ipx_8022_type =  0xE0;
++				unsigned char snap_8022_type = 0xAA;
++
++				if (*framePtr == snap_8022_type) {
++					unsigned char ipx_snap_id[5] = {0x0, 0x0, 0x0, 0x81, 0x37};		/* IPX SNAP ID */
++					unsigned char aarp_snap_id[5] = {0x00, 0x00, 0x00, 0x80, 0xF3};	/* Apple Talk AARP SNAP ID */
++					unsigned char ddp_snap_id[5] = {0x08, 0x00, 0x07, 0x80, 0x9B};	/* Apple Talk DDP SNAP ID */
++
++					framePtr += 3;	/* eliminate the 802.2 header */
++
++					if (!memcmp(ipx_snap_id, framePtr, 5)) {
++						framePtr += 5;	/* eliminate the SNAP header */
++
++						RTW_INFO("NAT25: Protocol=IPX (Ethernet SNAP)\n");
++						ipx = (struct ipxhdr *)framePtr;
++					} else if (!memcmp(aarp_snap_id, framePtr, 5)) {
++						framePtr += 5;	/* eliminate the SNAP header */
++
++						ea = (struct elapaarp *)framePtr;
++					} else if (!memcmp(ddp_snap_id, framePtr, 5)) {
++						framePtr += 5;	/* eliminate the SNAP header */
++
++						ddp = (struct ddpehdr *)framePtr;
++					} else {
++						DEBUG_WARN("NAT25: Protocol=Ethernet SNAP %02x%02x%02x%02x%02x\n", framePtr[0],
++							framePtr[1], framePtr[2], framePtr[3], framePtr[4]);
++						return -1;
++					}
++				} else if (*framePtr == ipx_8022_type) {
++					framePtr += 3;	/* eliminate the 802.2 header */
++
++					if (!memcmp(ipx_header, framePtr, 2)) {
++						RTW_INFO("NAT25: Protocol=IPX (Ethernet 802.2)\n");
++						ipx = (struct ipxhdr *)framePtr;
++					} else
++						return -1;
++				}
++			}
++		}
++
++		/*   IPX  */
++		if (ipx != NULL) {
++			switch (method) {
++			case NAT25_CHECK:
++				if (!memcmp(skb->data + ETH_ALEN, ipx->ipx_source.node, ETH_ALEN)) {
++					RTW_INFO("NAT25: Check IPX skb_copy\n");
++					return 0;
++				}
++				return -1;
++
++			case NAT25_INSERT: {
++				RTW_INFO("NAT25: Insert IPX, Dest=%08x,%02x%02x%02x%02x%02x%02x,%04x Source=%08x,%02x%02x%02x%02x%02x%02x,%04x\n",
++					 ipx->ipx_dest.net,
++					 ipx->ipx_dest.node[0],
++					 ipx->ipx_dest.node[1],
++					 ipx->ipx_dest.node[2],
++					 ipx->ipx_dest.node[3],
++					 ipx->ipx_dest.node[4],
++					 ipx->ipx_dest.node[5],
++					 ipx->ipx_dest.sock,
++					 ipx->ipx_source.net,
++					 ipx->ipx_source.node[0],
++					 ipx->ipx_source.node[1],
++					 ipx->ipx_source.node[2],
++					 ipx->ipx_source.node[3],
++					 ipx->ipx_source.node[4],
++					 ipx->ipx_source.node[5],
++					 ipx->ipx_source.sock);
++
++				if (!memcmp(skb->data + ETH_ALEN, ipx->ipx_source.node, ETH_ALEN)) {
++					RTW_INFO("NAT25: Use IPX Net, and Socket as network addr\n");
++
++					__nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_source.net, &ipx->ipx_source.sock);
++
++					/* change IPX source node addr to wlan STA address */
++					memcpy(ipx->ipx_source.node, GET_MY_HWADDR(priv), ETH_ALEN);
++				} else
++					__nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_source.net, ipx->ipx_source.node);
++
++				__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
++
++				__nat25_db_print(priv);
++			}
++			return 0;
++
++			case NAT25_LOOKUP: {
++				if (!memcmp(GET_MY_HWADDR(priv), ipx->ipx_dest.node, ETH_ALEN)) {
++					RTW_INFO("NAT25: Lookup IPX, Modify Destination IPX Node addr\n");
++
++					__nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_dest.net, &ipx->ipx_dest.sock);
++
++					__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
++
++					/* replace IPX destination node addr with Lookup destination MAC addr */
++					memcpy(ipx->ipx_dest.node, skb->data, ETH_ALEN);
++				} else {
++					__nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_dest.net, ipx->ipx_dest.node);
++
++					__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
++				}
++			}
++			return 0;
++
++			default:
++				return -1;
++			}
++		}
++
++		/*   AARP  */
++		else if (ea != NULL) {
++			/* Sanity check fields. */
++			if (ea->hw_len != ETH_ALEN || ea->pa_len != AARP_PA_ALEN) {
++				DEBUG_WARN("NAT25: Appletalk AARP Sanity check fail!\n");
++				return -1;
++			}
++
++			switch (method) {
++			case NAT25_CHECK:
++				return 0;
++
++			case NAT25_INSERT: {
++				/* change to AARP source mac address to wlan STA address */
++				memcpy(ea->hw_src, GET_MY_HWADDR(priv), ETH_ALEN);
++
++				RTW_INFO("NAT25: Insert AARP, Source=%d,%d Destination=%d,%d\n",
++					 ea->pa_src_net,
++					 ea->pa_src_node,
++					 ea->pa_dst_net,
++					 ea->pa_dst_node);
++
++				__nat25_generate_apple_network_addr(networkAddr, &ea->pa_src_net, &ea->pa_src_node);
++
++				__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
++
++				__nat25_db_print(priv);
++			}
++			return 0;
++
++			case NAT25_LOOKUP: {
++				RTW_INFO("NAT25: Lookup AARP, Source=%d,%d Destination=%d,%d\n",
++					 ea->pa_src_net,
++					 ea->pa_src_node,
++					 ea->pa_dst_net,
++					 ea->pa_dst_node);
++
++				__nat25_generate_apple_network_addr(networkAddr, &ea->pa_dst_net, &ea->pa_dst_node);
++
++				__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
++
++				/* change to AARP destination mac address to Lookup result */
++				memcpy(ea->hw_dst, skb->data, ETH_ALEN);
++			}
++			return 0;
++
++			default:
++				return -1;
++			}
++		}
++
++		/*   DDP  */
++		else if (ddp != NULL) {
++			switch (method) {
++			case NAT25_CHECK:
++				return -1;
++
++			case NAT25_INSERT: {
++				RTW_INFO("NAT25: Insert DDP, Source=%d,%d Destination=%d,%d\n",
++					 ddp->deh_snet,
++					 ddp->deh_snode,
++					 ddp->deh_dnet,
++					 ddp->deh_dnode);
++
++				__nat25_generate_apple_network_addr(networkAddr, &ddp->deh_snet, &ddp->deh_snode);
++
++				__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
++
++				__nat25_db_print(priv);
++			}
++			return 0;
++
++			case NAT25_LOOKUP: {
++				RTW_INFO("NAT25: Lookup DDP, Source=%d,%d Destination=%d,%d\n",
++					 ddp->deh_snet,
++					 ddp->deh_snode,
++					 ddp->deh_dnet,
++					 ddp->deh_dnode);
++
++				__nat25_generate_apple_network_addr(networkAddr, &ddp->deh_dnet, &ddp->deh_dnode);
++
++				__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
++			}
++			return 0;
++
++			default:
++				return -1;
++			}
++		}
++
++		return -1;
++	}
++
++	/*---------------------------------------------------*/
++	/*                Handle PPPoE frame                */
++	/*---------------------------------------------------*/
++	else if ((protocol == __constant_htons(ETH_P_PPP_DISC)) ||
++		 (protocol == __constant_htons(ETH_P_PPP_SES))) {
++		struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN);
++		unsigned short *pMagic;
++
++		switch (method) {
++		case NAT25_CHECK:
++			if (ph->sid == 0)
++				return 0;
++			return 1;
++
++		case NAT25_INSERT:
++			if (ph->sid == 0) {	/* Discovery phase according to tag */
++				if (ph->code == PADI_CODE || ph->code == PADR_CODE) {
++					if (priv->ethBrExtInfo.addPPPoETag) {
++						struct pppoe_tag *tag, *pOldTag;
++						unsigned char tag_buf[40];
++						int old_tag_len = 0;
++
++						tag = (struct pppoe_tag *)tag_buf;
++						pOldTag = (struct pppoe_tag *)__nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID));
++						if (pOldTag) { /* if SID existed, copy old value and delete it */
++							old_tag_len = ntohs(pOldTag->tag_len);
++							if (old_tag_len + TAG_HDR_LEN + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN > sizeof(tag_buf)) {
++								DEBUG_ERR("SID tag length too long!\n");
++								return -1;
++							}
++
++							memcpy(tag->tag_data + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN,
++							       pOldTag->tag_data, old_tag_len);
++
++							if (skb_pull_and_merge(skb, (unsigned char *)pOldTag, TAG_HDR_LEN + old_tag_len) < 0) {
++								DEBUG_ERR("call skb_pull_and_merge() failed in PADI/R packet!\n");
++								return -1;
++							}
++							ph->length = htons(ntohs(ph->length) - TAG_HDR_LEN - old_tag_len);
++						}
++
++						tag->tag_type = PTT_RELAY_SID;
++						tag->tag_len = htons(MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN + old_tag_len);
++
++						/* insert the magic_code+client mac in relay tag */
++						pMagic = (unsigned short *)tag->tag_data;
++						*pMagic = htons(MAGIC_CODE);
++						memcpy(tag->tag_data + MAGIC_CODE_LEN, skb->data + ETH_ALEN, ETH_ALEN);
++
++						/* Add relay tag */
++						if (__nat25_add_pppoe_tag(skb, tag) < 0)
++							return -1;
++
++						RTW_INFO("NAT25: Insert PPPoE, forward %s packet\n",
++							(ph->code == PADI_CODE ? "PADI" : "PADR"));
++					} else { /* not add relay tag */
++						if (priv->pppoe_connection_in_progress &&
++						    memcmp(skb->data + ETH_ALEN, priv->pppoe_addr, ETH_ALEN))	 {
++							DEBUG_ERR("Discard PPPoE packet due to another PPPoE connection is in progress!\n");
++							return -2;
++						}
++
++						if (priv->pppoe_connection_in_progress == 0)
++							memcpy(priv->pppoe_addr, skb->data + ETH_ALEN, ETH_ALEN);
++
++						priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE;
++					}
++				} else
++					return -1;
++			} else {	/* session phase */
++				RTW_INFO("NAT25: Insert PPPoE, insert session packet to %s\n", skb->dev->name);
++
++				__nat25_generate_pppoe_network_addr(networkAddr, skb->data, &(ph->sid));
++
++				__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
++
++				__nat25_db_print(priv);
++
++				if (!priv->ethBrExtInfo.addPPPoETag &&
++				    priv->pppoe_connection_in_progress &&
++				    !memcmp(skb->data + ETH_ALEN, priv->pppoe_addr, ETH_ALEN))
++					priv->pppoe_connection_in_progress = 0;
++			}
++			return 0;
++
++		case NAT25_LOOKUP:
++			if (ph->code == PADO_CODE || ph->code == PADS_CODE) {
++				if (priv->ethBrExtInfo.addPPPoETag) {
++					struct pppoe_tag *tag;
++					unsigned char *ptr;
++					unsigned short tagType, tagLen;
++					int offset = 0;
++
++					ptr = __nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID));
++					if (ptr == 0) {
++						DEBUG_ERR("Fail to find PTT_RELAY_SID in FADO!\n");
++						return -1;
++					}
++
++					tag = (struct pppoe_tag *)ptr;
++					tagType = (unsigned short)((ptr[0] << 8) + ptr[1]);
++					tagLen = (unsigned short)((ptr[2] << 8) + ptr[3]);
++
++					if ((tagType != ntohs(PTT_RELAY_SID)) || (tagLen < (MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN))) {
++						DEBUG_ERR("Invalid PTT_RELAY_SID tag length [%d]!\n", tagLen);
++						return -1;
++					}
++
++					pMagic = (unsigned short *)tag->tag_data;
++					if (ntohs(*pMagic) != MAGIC_CODE) {
++						DEBUG_ERR("Can't find MAGIC_CODE in %s packet!\n",
++							(ph->code == PADO_CODE ? "PADO" : "PADS"));
++						return -1;
++					}
++
++					memcpy(skb->data, tag->tag_data + MAGIC_CODE_LEN, ETH_ALEN);
++
++					if (tagLen > MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN)
++						offset = TAG_HDR_LEN;
++
++					if (skb_pull_and_merge(skb, ptr + offset, TAG_HDR_LEN + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN - offset) < 0) {
++						DEBUG_ERR("call skb_pull_and_merge() failed in PADO packet!\n");
++						return -1;
++					}
++					ph->length = htons(ntohs(ph->length) - (TAG_HDR_LEN + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN - offset));
++					if (offset > 0)
++						tag->tag_len = htons(tagLen - MAGIC_CODE_LEN - RTL_RELAY_TAG_LEN);
++
++					RTW_INFO("NAT25: Lookup PPPoE, forward %s Packet from %s\n",
++						(ph->code == PADO_CODE ? "PADO" : "PADS"),	skb->dev->name);
++				} else { /* not add relay tag */
++					if (!priv->pppoe_connection_in_progress) {
++						DEBUG_ERR("Discard PPPoE packet due to no connection in progresss!\n");
++						return -1;
++					}
++					memcpy(skb->data, priv->pppoe_addr, ETH_ALEN);
++					priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE;
++				}
++			} else {
++				if (ph->sid != 0) {
++					RTW_INFO("NAT25: Lookup PPPoE, lookup session packet from %s\n", skb->dev->name);
++					__nat25_generate_pppoe_network_addr(networkAddr, skb->data + ETH_ALEN, &(ph->sid));
++
++					__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
++
++					__nat25_db_print(priv);
++				} else
++					return -1;
++
++			}
++			return 0;
++
++		default:
++			return -1;
++		}
++	}
++
++	/*---------------------------------------------------*/
++	/*                 Handle EAP frame                 */
++	/*---------------------------------------------------*/
++	else if (protocol == __constant_htons(0x888e)) {
++		switch (method) {
++		case NAT25_CHECK:
++			return -1;
++
++		case NAT25_INSERT:
++			return 0;
++
++		case NAT25_LOOKUP:
++			return 0;
++
++		default:
++			return -1;
++		}
++	}
++
++	/*---------------------------------------------------*/
++	/*         Handle C-Media proprietary frame         */
++	/*---------------------------------------------------*/
++	else if ((protocol == __constant_htons(0xe2ae)) ||
++		 (protocol == __constant_htons(0xe2af))) {
++		switch (method) {
++		case NAT25_CHECK:
++			return -1;
++
++		case NAT25_INSERT:
++			return 0;
++
++		case NAT25_LOOKUP:
++			return 0;
++
++		default:
++			return -1;
++		}
++	}
++
++	/*---------------------------------------------------*/
++	/*         Handle IPV6 frame      							 */
++	/*---------------------------------------------------*/
++#ifdef CL_IPV6_PASS
++	else if (protocol == __constant_htons(ETH_P_IPV6)) {
++		struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN);
++
++		if (sizeof(*iph) >= (skb->len - ETH_HLEN)) {
++			DEBUG_WARN("NAT25: malformed IPv6 packet !\n");
++			return -1;
++		}
++
++		switch (method) {
++		case NAT25_CHECK:
++			if (skb->data[0] & 1)
++				return 0;
++			return -1;
++
++		case NAT25_INSERT: {
++			RTW_INFO("NAT25: Insert IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x,"
++				" DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\n",
++				iph->saddr.s6_addr16[0], iph->saddr.s6_addr16[1], iph->saddr.s6_addr16[2], iph->saddr.s6_addr16[3],
++				iph->saddr.s6_addr16[4], iph->saddr.s6_addr16[5], iph->saddr.s6_addr16[6], iph->saddr.s6_addr16[7],
++				iph->daddr.s6_addr16[0], iph->daddr.s6_addr16[1], iph->daddr.s6_addr16[2], iph->daddr.s6_addr16[3],
++				iph->daddr.s6_addr16[4], iph->daddr.s6_addr16[5], iph->daddr.s6_addr16[6], iph->daddr.s6_addr16[7]);
++
++			if (memcmp(&iph->saddr, "\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0", 16)) {
++				__nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->saddr);
++				__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
++				__nat25_db_print(priv);
++
++				if (iph->nexthdr == IPPROTO_ICMPV6 &&
++				    skb->len > (ETH_HLEN +  sizeof(*iph) + 4)) {
++					if (update_nd_link_layer_addr(skb->data + ETH_HLEN + sizeof(*iph),
++						skb->len - ETH_HLEN - sizeof(*iph), GET_MY_HWADDR(priv))) {
++						struct icmp6hdr  *hdr = (struct icmp6hdr *)(skb->data + ETH_HLEN + sizeof(*iph));
++						hdr->icmp6_cksum = 0;
++						hdr->icmp6_cksum = csum_ipv6_magic(&iph->saddr, &iph->daddr,
++							iph->payload_len,
++							IPPROTO_ICMPV6,
++							csum_partial((__u8 *)hdr, iph->payload_len, 0));
++					}
++				}
++			}
++		}
++		return 0;
++
++		case NAT25_LOOKUP:
++			RTW_INFO("NAT25: Lookup IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x,"
++				 " DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\n",
++				iph->saddr.s6_addr16[0], iph->saddr.s6_addr16[1], iph->saddr.s6_addr16[2], iph->saddr.s6_addr16[3],
++				iph->saddr.s6_addr16[4], iph->saddr.s6_addr16[5], iph->saddr.s6_addr16[6], iph->saddr.s6_addr16[7],
++				iph->daddr.s6_addr16[0], iph->daddr.s6_addr16[1], iph->daddr.s6_addr16[2], iph->daddr.s6_addr16[3],
++				iph->daddr.s6_addr16[4], iph->daddr.s6_addr16[5], iph->daddr.s6_addr16[6], iph->daddr.s6_addr16[7]);
++
++
++			__nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->daddr);
++			if (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) {
++#ifdef SUPPORT_RX_UNI2MCAST
++				if (iph->daddr.s6_addr[0] == 0xff)
++					convert_ipv6_mac_to_mc(skb);
++#endif
++			}
++			return 0;
++
++		default:
++			return -1;
++		}
++	}
++#endif /* CL_IPV6_PASS */
++
++	return -1;
++}
++
++
++int nat25_handle_frame(_adapter *priv, struct sk_buff *skb)
++{
++#ifdef BR_EXT_DEBUG
++	if ((!priv->ethBrExtInfo.nat25_disable) && (!(skb->data[0] & 1))) {
++		panic_printk("NAT25: Input Frame: DA=%02x%02x%02x%02x%02x%02x SA=%02x%02x%02x%02x%02x%02x\n",
++			     skb->data[0],
++			     skb->data[1],
++			     skb->data[2],
++			     skb->data[3],
++			     skb->data[4],
++			     skb->data[5],
++			     skb->data[6],
++			     skb->data[7],
++			     skb->data[8],
++			     skb->data[9],
++			     skb->data[10],
++			     skb->data[11]);
++	}
++#endif
++
++	if (!(skb->data[0] & 1)) {
++		int is_vlan_tag = 0, i, retval = 0;
++		unsigned short vlan_hdr = 0;
++
++		if (*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_8021Q)) {
++			is_vlan_tag = 1;
++			vlan_hdr = *((unsigned short *)(skb->data + ETH_ALEN * 2 + 2));
++			for (i = 0; i < 6; i++)
++				*((unsigned short *)(skb->data + ETH_ALEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + ETH_ALEN * 2 - 2 - i * 2));
++			skb_pull(skb, 4);
++		}
++
++		if (!priv->ethBrExtInfo.nat25_disable) {
++			_irqL irqL;
++			_enter_critical_bh(&priv->br_ext_lock, &irqL);
++			/*
++			 *	This function look up the destination network address from
++			 *	the NAT2.5 database. Return value = -1 means that the
++			 *	corresponding network protocol is NOT support.
++			 */
++			if (!priv->ethBrExtInfo.nat25sc_disable &&
++			    (*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_IP)) &&
++			    !memcmp(priv->scdb_ip, skb->data + ETH_HLEN + 16, 4)) {
++				memcpy(skb->data, priv->scdb_mac, ETH_ALEN);
++
++				_exit_critical_bh(&priv->br_ext_lock, &irqL);
++			} else {
++				_exit_critical_bh(&priv->br_ext_lock, &irqL);
++
++				retval = nat25_db_handle(priv, skb, NAT25_LOOKUP);
++			}
++		} else {
++			if (((*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_IP)) &&
++			     !memcmp(priv->br_ip, skb->data + ETH_HLEN + 16, 4)) ||
++			    ((*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_ARP)) &&
++			     !memcmp(priv->br_ip, skb->data + ETH_HLEN + 24, 4))) {
++				/* for traffic to upper TCP/IP */
++				retval = nat25_db_handle(priv, skb, NAT25_LOOKUP);
++			}
++		}
++
++		if (is_vlan_tag) {
++			skb_push(skb, 4);
++			for (i = 0; i < 6; i++)
++				*((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2));
++			*((unsigned short *)(skb->data + ETH_ALEN * 2)) = __constant_htons(ETH_P_8021Q);
++			*((unsigned short *)(skb->data + ETH_ALEN * 2 + 2)) = vlan_hdr;
++		}
++
++		if (retval == -1) {
++			/* DEBUG_ERR("NAT25: Lookup fail!\n"); */
++			return -1;
++		}
++	}
++
++	return 0;
++}
++
++#if 0
++void mac_clone(_adapter *priv, unsigned char *addr)
++{
++	struct sockaddr sa;
++
++	memcpy(sa.sa_data, addr, ETH_ALEN);
++	RTW_INFO("MAC Clone: Addr=%02x%02x%02x%02x%02x%02x\n",
++		 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
++	rtl8192cd_set_hwaddr(priv->dev, &sa);
++}
++
++
++int mac_clone_handle_frame(_adapter *priv, struct sk_buff *skb)
++{
++	if (priv->ethBrExtInfo.macclone_enable && !priv->macclone_completed) {
++		if (!(skb->data[ETH_ALEN] & 1)) {	/* check any other particular MAC add */
++			if (memcmp(skb->data + ETH_ALEN, GET_MY_HWADDR(priv), ETH_ALEN) &&
++			    ((priv->dev->br_port) &&
++			     memcmp(skb->data + ETH_ALEN, priv->br_mac, ETH_ALEN))) {
++				mac_clone(priv, skb->data + ETH_ALEN);
++				priv->macclone_completed = 1;
++			}
++		}
++	}
++
++	return 0;
++}
++#endif /* 0 */
++
++#define SERVER_PORT			67
++#define CLIENT_PORT			68
++#define DHCP_MAGIC			0x63825363
++#define BROADCAST_FLAG		0x8000
++
++struct dhcpMessage {
++	u_int8_t op;
++	u_int8_t htype;
++	u_int8_t hlen;
++	u_int8_t hops;
++	u_int32_t xid;
++	u_int16_t secs;
++	u_int16_t flags;
++	u_int32_t ciaddr;
++	u_int32_t yiaddr;
++	u_int32_t siaddr;
++	u_int32_t giaddr;
++	u_int8_t chaddr[16];
++	u_int8_t sname[64];
++	u_int8_t file[128];
++	u_int32_t cookie;
++	u_int8_t options[308]; /* 312 - cookie */
++};
++
++void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb)
++{
++	if (skb == NULL)
++		return;
++
++	if (!priv->ethBrExtInfo.dhcp_bcst_disable) {
++		unsigned short protocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN));
++
++		if (protocol == __constant_htons(ETH_P_IP)) { /* IP */
++			struct iphdr *iph = (struct iphdr *)(skb->data + ETH_HLEN);
++
++			if (iph->protocol == IPPROTO_UDP) { /* UDP */
++				struct udphdr *udph = (struct udphdr *)((SIZE_PTR)iph + (iph->ihl << 2));
++
++				if ((udph->source == __constant_htons(CLIENT_PORT))
++				    && (udph->dest == __constant_htons(SERVER_PORT))) { /* DHCP request */
++					struct dhcpMessage *dhcph =
++						(struct dhcpMessage *)((SIZE_PTR)udph + sizeof(struct udphdr));
++
++					if (dhcph->cookie == __constant_htonl(DHCP_MAGIC)) { /* match magic word */
++						if (!(dhcph->flags & htons(BROADCAST_FLAG))) { /* if not broadcast */
++							register int sum = 0;
++
++							RTW_INFO("DHCP: change flag of DHCP request to broadcast.\n");
++							/* or BROADCAST flag */
++							dhcph->flags |= htons(BROADCAST_FLAG);
++							/* recalculate checksum */
++							sum = ~(udph->check) & 0xffff;
++							sum += dhcph->flags;
++							while (sum >> 16)
++								sum = (sum & 0xffff) + (sum >> 16);
++							udph->check = ~sum;
++						}
++					}
++				}
++			}
++		}
++	}
++}
++
++
++void *scdb_findEntry(_adapter *priv, unsigned char *macAddr,
++		     unsigned char *ipAddr)
++{
++	unsigned char networkAddr[MAX_NETWORK_ADDR_LEN];
++	struct nat25_network_db_entry *db;
++	int hash;
++	/* _irqL irqL; */
++	/* _enter_critical_bh(&priv->br_ext_lock, &irqL); */
++
++	__nat25_generate_ipv4_network_addr(networkAddr, (unsigned int *)ipAddr);
++	hash = __nat25_network_hash(networkAddr);
++	db = priv->nethash[hash];
++	while (db != NULL) {
++		if (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) {
++			/* _exit_critical_bh(&priv->br_ext_lock, &irqL); */
++			return (void *)db;
++		}
++
++		db = db->next_hash;
++	}
++
++	/* _exit_critical_bh(&priv->br_ext_lock, &irqL); */
++	return NULL;
++}
++
++#endif /* CONFIG_BR_EXT */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_bt_mp.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_bt_mp.c
+new file mode 100644
+index 000000000..ce7aa29f7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_bt_mp.c
+@@ -0,0 +1,1575 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++
++#include <drv_types.h>
++#include <rtw_bt_mp.h>
++
++#if defined(CONFIG_RTL8723B)
++	#include <rtl8723b_hal.h>
++#endif
++
++#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A)
++void MPh2c_timeout_handle(void *FunctionContext)
++{
++	PADAPTER pAdapter;
++	PMPT_CONTEXT pMptCtx;
++
++
++	RTW_INFO("[MPT], MPh2c_timeout_handle\n");
++
++	pAdapter = (PADAPTER)FunctionContext;
++	pMptCtx = &pAdapter->mppriv.mpt_ctx;
++
++	pMptCtx->bMPh2c_timeout = _TRUE;
++
++	if ((_FALSE == pMptCtx->MptH2cRspEvent)
++	    || ((_TRUE == pMptCtx->MptH2cRspEvent)
++		&& (_FALSE == pMptCtx->MptBtC2hEvent)))
++		_rtw_up_sema(&pMptCtx->MPh2c_Sema);
++}
++
++u32 WaitC2Hevent(PADAPTER pAdapter, u8 *C2H_event, u32 delay_time)
++{
++	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
++	pMptCtx->bMPh2c_timeout = _FALSE;
++
++	if (pAdapter->registrypriv.mp_mode == 0) {
++		RTW_INFO("[MPT], Error!! WaitC2Hevent mp_mode == 0!!\n");
++		return _FALSE;
++	}
++
++	_set_timer(&pMptCtx->MPh2c_timeout_timer, delay_time);
++
++	_rtw_down_sema(&pMptCtx->MPh2c_Sema);
++
++	if (pMptCtx->bMPh2c_timeout == _TRUE) {
++		*C2H_event = _FALSE;
++
++		return _FALSE;
++	}
++
++	/* for safty, cancel timer here again */
++	_cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);
++
++	return _TRUE;
++}
++
++BT_CTRL_STATUS
++mptbt_CheckC2hFrame(
++	PADAPTER		Adapter,
++	PBT_H2C			pH2c,
++	PBT_EXT_C2H		pExtC2h
++)
++{
++	BT_CTRL_STATUS	c2hStatus = BT_STATUS_C2H_SUCCESS;
++
++	/* RTW_INFO("[MPT], MPT rsp C2H hex: %x %x %x  %x %x %x\n"), pExtC2h , pExtC2h+1 ,pExtC2h+2 ,pExtC2h+3 ,pExtC2h+4 ,pExtC2h+5); */
++
++	RTW_INFO("[MPT], statusCode = 0x%x\n", pExtC2h->statusCode);
++	RTW_INFO("[MPT], retLen = %d\n", pExtC2h->retLen);
++	RTW_INFO("[MPT], opCodeVer : req/rsp=%d/%d\n", pH2c->opCodeVer, pExtC2h->opCodeVer);
++	RTW_INFO("[MPT], reqNum : req/rsp=%d/%d\n", pH2c->reqNum, pExtC2h->reqNum);
++	if (pExtC2h->reqNum != pH2c->reqNum) {
++		c2hStatus = BT_STATUS_C2H_REQNUM_MISMATCH;
++		RTW_INFO("[MPT], Error!! C2H reqNum Mismatch!!\n");
++	} else if (pExtC2h->opCodeVer != pH2c->opCodeVer) {
++		c2hStatus = BT_STATUS_OPCODE_L_VERSION_MISMATCH;
++		RTW_INFO("[MPT], Error!! OPCode version L mismatch!!\n");
++	}
++
++	return c2hStatus;
++}
++
++BT_CTRL_STATUS
++mptbt_SendH2c(
++	PADAPTER	Adapter,
++	PBT_H2C	pH2c,
++	u16		h2cCmdLen
++)
++{
++	/* KIRQL				OldIrql = KeGetCurrentIrql(); */
++	BT_CTRL_STATUS	h2cStatus = BT_STATUS_H2C_SUCCESS;
++	PMPT_CONTEXT		pMptCtx = &(Adapter->mppriv.mpt_ctx);
++	u8				i;
++
++	RTW_INFO("[MPT], mptbt_SendH2c()=========>\n");
++
++	/* PlatformResetEvent(&pMptCtx->MptH2cRspEvent); */
++	/* PlatformResetEvent(&pMptCtx->MptBtC2hEvent); */
++
++	/*	if(OldIrql == PASSIVE_LEVEL)
++	 *	{ */
++	/* RTPRINT_DATA(FMPBT, FMPBT_H2C_CONTENT, ("[MPT], MPT H2C hex:\n"), pH2c, h2cCmdLen); */
++
++	for (i = 0; i < BT_H2C_MAX_RETRY; i++) {
++		RTW_INFO("[MPT], Send H2C command to wifi!!!\n");
++
++		pMptCtx->MptH2cRspEvent = _FALSE;
++		pMptCtx->MptBtC2hEvent = _FALSE;
++
++#if defined(CONFIG_RTL8723B)
++		rtl8723b_set_FwBtMpOper_cmd(Adapter, pH2c->opCode, pH2c->opCodeVer, pH2c->reqNum, pH2c->buf);
++#endif
++		pMptCtx->h2cReqNum++;
++		pMptCtx->h2cReqNum %= 16;
++
++		if (WaitC2Hevent(Adapter, &pMptCtx->MptH2cRspEvent, 100)) {
++			RTW_INFO("[MPT], Received WiFi MptH2cRspEvent!!!\n");
++			if (WaitC2Hevent(Adapter, &pMptCtx->MptBtC2hEvent, 400)) {
++				RTW_INFO("[MPT], Received MptBtC2hEvent!!!\n");
++				break;
++			} else {
++				RTW_INFO("[MPT], Error!!BT MptBtC2hEvent timeout!!\n");
++				h2cStatus = BT_STATUS_H2C_BT_NO_RSP;
++			}
++		} else {
++			RTW_INFO("[MPT], Error!!WiFi  MptH2cRspEvent timeout!!\n");
++			h2cStatus = BT_STATUS_H2C_TIMTOUT;
++		}
++	}
++	/*	}
++	 *	else
++	 *	{
++	 * 		RT_ASSERT(FALSE, ("[MPT],  mptbt_SendH2c() can only run under PASSIVE_LEVEL!!\n"));
++	 *		h2cStatus = BT_STATUS_WRONG_LEVEL;
++	 *	} */
++
++	RTW_INFO("[MPT], mptbt_SendH2c()<=========\n");
++	return h2cStatus;
++}
++
++
++
++BT_CTRL_STATUS
++mptbt_CheckBtRspStatus(
++	PADAPTER			Adapter,
++	PBT_EXT_C2H			pExtC2h
++)
++{
++	BT_CTRL_STATUS	retStatus = BT_OP_STATUS_SUCCESS;
++
++	switch (pExtC2h->statusCode) {
++	case BT_OP_STATUS_SUCCESS:
++		retStatus = BT_STATUS_BT_OP_SUCCESS;
++		RTW_INFO("[MPT], BT status : BT_STATUS_SUCCESS\n");
++		break;
++	case BT_OP_STATUS_VERSION_MISMATCH:
++		retStatus = BT_STATUS_OPCODE_L_VERSION_MISMATCH;
++		RTW_INFO("[MPT], BT status : BT_STATUS_OPCODE_L_VERSION_MISMATCH\n");
++		break;
++	case BT_OP_STATUS_UNKNOWN_OPCODE:
++		retStatus = BT_STATUS_UNKNOWN_OPCODE_L;
++		RTW_INFO("[MPT], BT status : BT_STATUS_UNKNOWN_OPCODE_L\n");
++		break;
++	case BT_OP_STATUS_ERROR_PARAMETER:
++		retStatus = BT_STATUS_PARAMETER_FORMAT_ERROR_L;
++		RTW_INFO("[MPT], BT status : BT_STATUS_PARAMETER_FORMAT_ERROR_L\n");
++		break;
++	default:
++		retStatus = BT_STATUS_UNKNOWN_STATUS_L;
++		RTW_INFO("[MPT], BT status : BT_STATUS_UNKNOWN_STATUS_L\n");
++		break;
++	}
++
++	return retStatus;
++}
++
++
++
++BT_CTRL_STATUS
++mptbt_BtFwOpCodeProcess(
++	PADAPTER		Adapter,
++	u8			btFwOpCode,
++	u8			opCodeVer,
++	u8			*pH2cPar,
++	u8			h2cParaLen
++)
++{
++	u8				H2C_Parameter[6] = {0};
++	PBT_H2C				pH2c = (PBT_H2C)&H2C_Parameter[0];
++	PMPT_CONTEXT		pMptCtx = &(Adapter->mppriv.mpt_ctx);
++	PBT_EXT_C2H			pExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0];
++	u16				paraLen = 0, i;
++	BT_CTRL_STATUS	h2cStatus = BT_STATUS_H2C_SUCCESS, c2hStatus = BT_STATUS_C2H_SUCCESS;
++	BT_CTRL_STATUS	retStatus = BT_STATUS_H2C_BT_NO_RSP;
++
++	if (Adapter->registrypriv.mp_mode == 0) {
++		RTW_INFO("[MPT], Error!! mptbt_BtFwOpCodeProces mp_mode == 0!!\n");
++		return _FALSE;
++	}
++
++	pH2c->opCode = btFwOpCode;
++	pH2c->opCodeVer = opCodeVer;
++	pH2c->reqNum = pMptCtx->h2cReqNum;
++	/* PlatformMoveMemory(&pH2c->buf[0], pH2cPar, h2cParaLen); */
++	/* _rtw_memcpy(&pH2c->buf[0], pH2cPar, h2cParaLen); */
++	_rtw_memcpy(pH2c->buf, pH2cPar, h2cParaLen);
++
++	RTW_INFO("[MPT], pH2c->opCode=%d\n", pH2c->opCode);
++	RTW_INFO("[MPT], pH2c->opCodeVer=%d\n", pH2c->opCodeVer);
++	RTW_INFO("[MPT], pH2c->reqNum=%d\n", pH2c->reqNum);
++	RTW_INFO("[MPT], h2c parameter length=%d\n", h2cParaLen);
++	for (i = 0; i < h2cParaLen; i++)
++		RTW_INFO("[MPT], parameter[%d]=0x%02x\n", i, pH2c->buf[i]);
++
++	h2cStatus = mptbt_SendH2c(Adapter, pH2c, h2cParaLen + 2);
++	if (BT_STATUS_H2C_SUCCESS == h2cStatus) {
++		/* if reach here, it means H2C get the correct c2h response, */
++		c2hStatus = mptbt_CheckC2hFrame(Adapter, pH2c, pExtC2h);
++		if (BT_STATUS_C2H_SUCCESS == c2hStatus)
++			retStatus = mptbt_CheckBtRspStatus(Adapter, pExtC2h);
++		else {
++			RTW_INFO("[MPT], Error!! C2H failed for pH2c->opCode=%d\n", pH2c->opCode);
++			/* check c2h status error, return error status code to upper layer. */
++			retStatus = c2hStatus;
++		}
++	} else {
++		RTW_INFO("[MPT], Error!! H2C failed for pH2c->opCode=%d\n", pH2c->opCode);
++		/* check h2c status error, return error status code to upper layer. */
++		retStatus = h2cStatus;
++	}
++
++	return retStatus;
++}
++
++
++
++
++u16
++mptbt_BtReady(
++	PADAPTER		Adapter,
++	PBT_REQ_CMD	pBtReq,
++	PBT_RSP_CMD	pBtRsp
++)
++{
++	u8				h2cParaBuf[6] = {0};
++	u8				h2cParaLen = 0;
++	u16				paraLen = 0;
++	u8				retStatus = BT_STATUS_BT_OP_SUCCESS;
++	u8				btOpcode;
++	u8				btOpcodeVer = 0;
++	PMPT_CONTEXT		pMptCtx = &(Adapter->mppriv.mpt_ctx);
++	PBT_EXT_C2H			pExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0];
++	u8				i;
++	u8				btFwVer = 0, bdAddr[6] = {0};
++	u16				btRealFwVer = 0;
++	u16				*pu2Tmp = NULL;
++
++	/*  */
++	/* check upper layer parameters */
++	/*  */
++
++	/* 1. check upper layer opcode version */
++	if (pBtReq->opCodeVer != 1) {
++		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
++		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
++		return paraLen;
++	}
++
++	pBtRsp->pParamStart[0] = MP_BT_NOT_READY;
++	paraLen = 10;
++	/*  */
++	/* execute lower layer opcodes */
++	/*  */
++
++	/* Get BT FW version */
++	/* fill h2c parameters */
++	btOpcode = BT_LO_OP_GET_BT_VERSION;
++	/* execute h2c and check respond c2h from bt fw is correct or not */
++	retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++	/* ckeck bt return status. */
++	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++		pBtRsp->status = ((btOpcode << 8) | retStatus);
++		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++		return paraLen;
++	} else {
++		pu2Tmp = (u16 *)&pExtC2h->buf[0];
++		btRealFwVer = *pu2Tmp;
++		btFwVer = pExtC2h->buf[1];
++		RTW_INFO("[MPT], btRealFwVer=0x%x, btFwVer=0x%x\n", btRealFwVer, btFwVer);
++	}
++
++	/* Get BD Address */
++	/* fill h2c parameters */
++	btOpcode = BT_LO_OP_GET_BD_ADDR_L;
++	/* execute h2c and check respond c2h from bt fw is correct or not */
++	retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++	/* ckeck bt return status. */
++	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++		pBtRsp->status = ((btOpcode << 8) | retStatus);
++		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++		return paraLen;
++	} else {
++		bdAddr[5] = pExtC2h->buf[0];
++		bdAddr[4] = pExtC2h->buf[1];
++		bdAddr[3] = pExtC2h->buf[2];
++	}
++
++	/* fill h2c parameters */
++	btOpcode = BT_LO_OP_GET_BD_ADDR_H;
++	/* execute h2c and check respond c2h from bt fw is correct or not */
++	retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++	/* ckeck bt return status. */
++	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++		pBtRsp->status = ((btOpcode << 8) | retStatus);
++		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++		return paraLen;
++	} else {
++		bdAddr[2] = pExtC2h->buf[0];
++		bdAddr[1] = pExtC2h->buf[1];
++		bdAddr[0] = pExtC2h->buf[2];
++	}
++	RTW_INFO("[MPT], Local BDAddr:");
++	for (i = 0; i < 6; i++)
++		RTW_INFO(" 0x%x ", bdAddr[i]);
++	pBtRsp->status = BT_STATUS_SUCCESS;
++	pBtRsp->pParamStart[0] = MP_BT_READY;
++	pu2Tmp = (u16 *)&pBtRsp->pParamStart[1];
++	*pu2Tmp = btRealFwVer;
++	pBtRsp->pParamStart[3] = btFwVer;
++	for (i = 0; i < 6; i++)
++		pBtRsp->pParamStart[4 + i] = bdAddr[5 - i];
++
++	return paraLen;
++}
++
++void mptbt_close_WiFiRF(PADAPTER Adapter)
++{
++	phy_set_bb_reg(Adapter, 0x824, 0xF, 0x0);
++	phy_set_bb_reg(Adapter, 0x824, 0x700000, 0x0);
++	phy_set_rf_reg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x0);
++}
++
++void mptbt_open_WiFiRF(PADAPTER	Adapter)
++{
++	phy_set_bb_reg(Adapter, 0x824, 0x700000, 0x3);
++	phy_set_bb_reg(Adapter, 0x824, 0xF, 0x2);
++	phy_set_rf_reg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x3);
++}
++
++u32 mptbt_switch_RF(PADAPTER	Adapter, u8	Enter)
++{
++	u16	tmp_2byte = 0;
++
++	/* Enter test mode */
++	if (Enter) {
++		/* 1>. close WiFi RF */
++		mptbt_close_WiFiRF(Adapter);
++
++		/* 2>. change ant switch to BT */
++		tmp_2byte = rtw_read16(Adapter, 0x860);
++		tmp_2byte = tmp_2byte | BIT(9);
++		tmp_2byte = tmp_2byte & (~BIT(8));
++		rtw_write16(Adapter, 0x860, tmp_2byte);
++		rtw_write16(Adapter, 0x870, 0x300);
++	} else {
++		/* 1>. Open WiFi RF */
++		mptbt_open_WiFiRF(Adapter);
++
++		/* 2>. change ant switch back */
++		tmp_2byte = rtw_read16(Adapter, 0x860);
++		tmp_2byte = tmp_2byte | BIT(8);
++		tmp_2byte = tmp_2byte & (~BIT(9));
++		rtw_write16(Adapter, 0x860, tmp_2byte);
++		rtw_write16(Adapter, 0x870, 0x300);
++	}
++
++	return 0;
++}
++
++u16
++mptbt_BtSetMode(
++	PADAPTER		Adapter,
++	PBT_REQ_CMD	pBtReq,
++	PBT_RSP_CMD	pBtRsp
++)
++{
++	u8				h2cParaBuf[6] = {0};
++	u8				h2cParaLen = 0;
++	u16				paraLen = 0;
++	u8				retStatus = BT_STATUS_BT_OP_SUCCESS;
++	u8				btOpcode;
++	u8				btOpcodeVer = 0;
++	u8				btModeToSet = 0;
++
++	/*  */
++	/* check upper layer parameters */
++	/*  */
++	/* 1. check upper layer opcode version */
++	if (pBtReq->opCodeVer != 1) {
++		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
++		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
++		return paraLen;
++	}
++	/* 2. check upper layer parameter length */
++	if (1 == pBtReq->paraLength) {
++		btModeToSet = pBtReq->pParamStart[0];
++		RTW_INFO("[MPT], BtTestMode=%d\n", btModeToSet);
++	} else {
++		RTW_INFO("[MPT], Error!! wrong parameter length=%d (should be 1)\n", pBtReq->paraLength);
++		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
++		return paraLen;
++	}
++
++	/*  */
++	/* execute lower layer opcodes */
++	/*  */
++
++	/* 1. fill h2c parameters	 */
++	/* check bt mode */
++	btOpcode = BT_LO_OP_SET_BT_MODE;
++	if (btModeToSet >= MP_BT_MODE_MAX) {
++		pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++		return paraLen;
++	} else {
++		mptbt_switch_RF(Adapter, 1);
++
++		h2cParaBuf[0] = btModeToSet;
++		h2cParaLen = 1;
++		/* 2. execute h2c and check respond c2h from bt fw is correct or not */
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++	}
++
++	/* 3. construct respond status code and data. */
++	if (BT_STATUS_BT_OP_SUCCESS == retStatus)
++		pBtRsp->status = BT_STATUS_SUCCESS;
++	else {
++		pBtRsp->status = ((btOpcode << 8) | retStatus);
++		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++	}
++
++	return paraLen;
++}
++
++
++void
++MPTBT_FwC2hBtMpCtrl(
++	PADAPTER	Adapter,
++	u8		*tmpBuf,
++	u8		length
++)
++{
++	u32 i;
++	PMPT_CONTEXT	pMptCtx = &(Adapter->mppriv.mpt_ctx);
++	PBT_EXT_C2H pExtC2h = (PBT_EXT_C2H)tmpBuf;
++
++	if (GET_HAL_DATA(Adapter)->bBTFWReady == _FALSE || Adapter->registrypriv.mp_mode == 0) {
++		/* RTW_INFO("Ignore C2H BT MP Info since not in MP mode\n"); */
++		return;
++	}
++	if (length > 32 || length < 3) {
++		RTW_INFO("\n [MPT], pExtC2h->buf hex: length=%d > 32 || < 3\n", length);
++		return;
++	}
++
++	/* cancel_timeout for h2c handle */
++	_cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);
++
++	for (i = 0; i < length; i++)
++		RTW_INFO("[MPT], %s, buf[%d]=0x%02x ", __FUNCTION__, i, tmpBuf[i]);
++	RTW_INFO("[MPT], pExtC2h->extendId=0x%x\n", pExtC2h->extendId);
++
++	switch (pExtC2h->extendId) {
++	case EXT_C2H_WIFI_FW_ACTIVE_RSP:
++		RTW_INFO("[MPT], EXT_C2H_WIFI_FW_ACTIVE_RSP\n");
++#if 0
++		RTW_INFO("[MPT], pExtC2h->buf hex:\n");
++		for (i = 0; i < (length - 3); i++)
++			RTW_INFO(" 0x%x ", pExtC2h->buf[i]);
++#endif
++		if ((_FALSE == pMptCtx->bMPh2c_timeout)
++		    && (_FALSE == pMptCtx->MptH2cRspEvent)) {
++			pMptCtx->MptH2cRspEvent = _TRUE;
++			_rtw_up_sema(&pMptCtx->MPh2c_Sema);
++		}
++		break;
++
++	case EXT_C2H_TRIG_BY_BT_FW:
++		RTW_INFO("[MPT], EXT_C2H_TRIG_BY_BT_FW\n");
++		_rtw_memcpy(&pMptCtx->c2hBuf[0], tmpBuf, length);
++		RTW_INFO("[MPT], pExtC2h->statusCode=0x%x\n", pExtC2h->statusCode);
++		RTW_INFO("[MPT], pExtC2h->retLen=0x%x\n", pExtC2h->retLen);
++		RTW_INFO("[MPT], pExtC2h->opCodeVer=0x%x\n", pExtC2h->opCodeVer);
++		RTW_INFO("[MPT], pExtC2h->reqNum=0x%x\n", pExtC2h->reqNum);
++		for (i = 0; i < (length - 3); i++)
++			RTW_INFO("[MPT], pExtC2h->buf[%d]=0x%02x\n", i, pExtC2h->buf[i]);
++
++		if ((_FALSE == pMptCtx->bMPh2c_timeout)
++		    && (_TRUE == pMptCtx->MptH2cRspEvent)
++		    && (_FALSE == pMptCtx->MptBtC2hEvent)) {
++			pMptCtx->MptBtC2hEvent = _TRUE;
++			_rtw_up_sema(&pMptCtx->MPh2c_Sema);
++		}
++		break;
++
++	default:
++		RTW_INFO("[MPT], EXT_C2H Target not found,pExtC2h->extendId =%d ,pExtC2h->reqNum=%d\n", pExtC2h->extendId, pExtC2h->reqNum);
++		break;
++	}
++
++
++
++}
++
++
++u16
++mptbt_BtGetGeneral(
++		PADAPTER		Adapter,
++		PBT_REQ_CMD	pBtReq,
++		PBT_RSP_CMD	pBtRsp
++)
++{
++	PMPT_CONTEXT		pMptCtx = &(Adapter->mppriv.mpt_ctx);
++	PBT_EXT_C2H		pExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0];
++	u8				h2cParaBuf[6] = {0};
++	u8				h2cParaLen = 0;
++	u16				paraLen = 0;
++	u8				retStatus = BT_STATUS_BT_OP_SUCCESS;
++	u8				btOpcode, bdAddr[6] = {0};
++	u8				btOpcodeVer = 0;
++	u8				getType = 0, i;
++	u16				getParaLen = 0, validParaLen = 0;
++	u8				regType = 0, reportType = 0;
++	u32				regAddr = 0, regValue = 0;
++	u32 				*pu4Tmp;
++	u16 				*pu2Tmp;
++	u8 				*pu1Tmp;
++
++	/*  */
++	/* check upper layer parameters */
++	/*  */
++
++	/* check upper layer opcode version */
++	if (pBtReq->opCodeVer != 1) {
++		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
++		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
++		return paraLen;
++	}
++	/* check upper layer parameter length */
++	if (pBtReq->paraLength < 1) {
++		RTW_INFO("[MPT], Error!! wrong parameter length=%d (should larger than 1)\n", pBtReq->paraLength);
++		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
++		return paraLen;
++	}
++	getParaLen = pBtReq->paraLength - 1;
++	getType = pBtReq->pParamStart[0];
++
++	RTW_INFO("[MPT], getType=%d, getParaLen=%d\n", getType, getParaLen);
++
++	/* check parameter first */
++	switch (getType) {
++	case BT_GGET_REG:
++		RTW_INFO("[MPT], [BT_GGET_REG]\n");
++		validParaLen = 5;
++		if (getParaLen == validParaLen) {
++			btOpcode = BT_LO_OP_READ_REG;
++			regType = pBtReq->pParamStart[1];
++			pu4Tmp = (u32 *)&pBtReq->pParamStart[2];
++			regAddr = *pu4Tmp;
++			RTW_INFO("[MPT], BT_GGET_REG regType=0x%02x, regAddr=0x%08x!!\n",
++				 regType, regAddr);
++			if (regType >= BT_REG_MAX) {
++				pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++				return paraLen;
++			} else {
++				if (((BT_REG_RF == regType) && (regAddr > 0x7f)) ||
++				    ((BT_REG_MODEM == regType) && (regAddr > 0x1ff)) ||
++				    ((BT_REG_BLUEWIZE == regType) && (regAddr > 0xfff)) ||
++				    ((BT_REG_VENDOR == regType) && (regAddr > 0xfff)) ||
++				    ((BT_REG_LE == regType) && (regAddr > 0xfff))) {
++					pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++					return paraLen;
++				}
++			}
++		}
++		break;
++	case BT_GGET_STATUS:
++		RTW_INFO("[MPT], [BT_GGET_STATUS]\n");
++		validParaLen = 0;
++		break;
++	case BT_GGET_REPORT:
++		RTW_INFO("[MPT], [BT_GGET_REPORT]\n");
++		validParaLen = 1;
++		if (getParaLen == validParaLen) {
++			reportType = pBtReq->pParamStart[1];
++			RTW_INFO("[MPT], BT_GGET_REPORT reportType=0x%x!!\n", reportType);
++			if (reportType >= BT_REPORT_MAX) {
++				pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++				return paraLen;
++			}
++		}
++		break;
++	default: {
++		RTW_INFO("[MPT], Error!! getType=%d, out of range\n", getType);
++		pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++		return paraLen;
++	}
++	break;
++	}
++	if (getParaLen != validParaLen) {
++		RTW_INFO("[MPT], Error!! wrong parameter length=%d for BT_GET_GEN_CMD cmd id=0x%x, paraLen should=0x%x\n",
++			 getParaLen, getType, validParaLen);
++		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
++		return paraLen;
++	}
++
++	/*  */
++	/* execute lower layer opcodes */
++	/*  */
++	if (BT_GGET_REG == getType) {
++		/* fill h2c parameters */
++		/* here we should write reg value first then write the address, adviced by Austin */
++		btOpcode = BT_LO_OP_READ_REG;
++		h2cParaBuf[0] = regType;
++		h2cParaBuf[1] = pBtReq->pParamStart[2];
++		h2cParaBuf[2] = pBtReq->pParamStart[3];
++		h2cParaLen = 3;
++		/* execute h2c and check respond c2h from bt fw is correct or not */
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++		/* construct respond status code and data. */
++		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++			pBtRsp->status = ((btOpcode << 8) | retStatus);
++			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++			return paraLen;
++		}
++
++		pu2Tmp = (u16 *)&pExtC2h->buf[0];
++		regValue = *pu2Tmp;
++		RTW_INFO("[MPT], read reg regType=0x%02x, regAddr=0x%08x, regValue=0x%04x\n",
++			 regType, regAddr, regValue);
++
++		pu4Tmp = (u32 *)&pBtRsp->pParamStart[0];
++		*pu4Tmp = regValue;
++		paraLen = 4;
++	} else if (BT_GGET_STATUS == getType) {
++		btOpcode = BT_LO_OP_GET_BT_STATUS;
++		h2cParaLen = 0;
++		/* execute h2c and check respond c2h from bt fw is correct or not */
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++		/* construct respond status code and data. */
++		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++			pBtRsp->status = ((btOpcode << 8) | retStatus);
++			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++			return paraLen;
++		}
++
++		pBtRsp->pParamStart[0] = pExtC2h->buf[0];
++		pBtRsp->pParamStart[1] = pExtC2h->buf[1];
++		RTW_INFO("[MPT], read bt status, testMode=0x%x, testStatus=0x%x\n",
++			 pBtRsp->pParamStart[0], pBtRsp->pParamStart[1]);
++		paraLen = 2;
++	} else if (BT_GGET_REPORT == getType) {
++		switch (reportType) {
++		case BT_REPORT_RX_PACKET_CNT: {
++			RTW_INFO("[MPT], [Rx Packet Counts]\n");
++			btOpcode = BT_LO_OP_GET_RX_PKT_CNT_L;
++			h2cParaLen = 0;
++			/* execute h2c and check respond c2h from bt fw is correct or not */
++			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++			/* construct respond status code and data. */
++			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++				pBtRsp->status = ((btOpcode << 8) | retStatus);
++				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++				return paraLen;
++			}
++			pBtRsp->pParamStart[0] = pExtC2h->buf[0];
++			pBtRsp->pParamStart[1] = pExtC2h->buf[1];
++
++			btOpcode = BT_LO_OP_GET_RX_PKT_CNT_H;
++			h2cParaLen = 0;
++			/* execute h2c and check respond c2h from bt fw is correct or not */
++			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++			/* construct respond status code and data. */
++			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++				pBtRsp->status = ((btOpcode << 8) | retStatus);
++				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++				return paraLen;
++			}
++			pBtRsp->pParamStart[2] = pExtC2h->buf[0];
++			pBtRsp->pParamStart[3] = pExtC2h->buf[1];
++			paraLen = 4;
++		}
++		break;
++		case BT_REPORT_RX_ERROR_BITS: {
++			RTW_INFO("[MPT], [Rx Error Bits]\n");
++			btOpcode = BT_LO_OP_GET_RX_ERROR_BITS_L;
++			h2cParaLen = 0;
++			/* execute h2c and check respond c2h from bt fw is correct or not */
++			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++			/* construct respond status code and data. */
++			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++				pBtRsp->status = ((btOpcode << 8) | retStatus);
++				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++				return paraLen;
++			}
++			pBtRsp->pParamStart[0] = pExtC2h->buf[0];
++			pBtRsp->pParamStart[1] = pExtC2h->buf[1];
++
++			btOpcode = BT_LO_OP_GET_RX_ERROR_BITS_H;
++			h2cParaLen = 0;
++			/* execute h2c and check respond c2h from bt fw is correct or not */
++			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++			/* construct respond status code and data. */
++			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++				pBtRsp->status = ((btOpcode << 8) | retStatus);
++				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++				return paraLen;
++			}
++			pBtRsp->pParamStart[2] = pExtC2h->buf[0];
++			pBtRsp->pParamStart[3] = pExtC2h->buf[1];
++			paraLen = 4;
++		}
++		break;
++		case BT_REPORT_RSSI: {
++			RTW_INFO("[MPT], [RSSI]\n");
++			btOpcode = BT_LO_OP_GET_RSSI;
++			h2cParaLen = 0;
++			/* execute h2c and check respond c2h from bt fw is correct or not */
++			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++			/* construct respond status code and data. */
++			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++				pBtRsp->status = ((btOpcode << 8) | retStatus);
++				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++				return paraLen;
++			}
++			pBtRsp->pParamStart[0] = pExtC2h->buf[0];
++			pBtRsp->pParamStart[1] = pExtC2h->buf[1];
++			paraLen = 2;
++		}
++		break;
++		case BT_REPORT_CFO_HDR_QUALITY: {
++			RTW_INFO("[MPT], [CFO & Header Quality]\n");
++			btOpcode = BT_LO_OP_GET_CFO_HDR_QUALITY_L;
++			h2cParaLen = 0;
++			/* execute h2c and check respond c2h from bt fw is correct or not */
++			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++			/* construct respond status code and data. */
++			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++				pBtRsp->status = ((btOpcode << 8) | retStatus);
++				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++				return paraLen;
++			}
++			pBtRsp->pParamStart[0] = pExtC2h->buf[0];
++			pBtRsp->pParamStart[1] = pExtC2h->buf[1];
++
++			btOpcode = BT_LO_OP_GET_CFO_HDR_QUALITY_H;
++			h2cParaLen = 0;
++			/* execute h2c and check respond c2h from bt fw is correct or not */
++			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++			/* construct respond status code and data. */
++			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++				pBtRsp->status = ((btOpcode << 8) | retStatus);
++				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++				return paraLen;
++			}
++			pBtRsp->pParamStart[2] = pExtC2h->buf[0];
++			pBtRsp->pParamStart[3] = pExtC2h->buf[1];
++			paraLen = 4;
++		}
++		break;
++		case BT_REPORT_CONNECT_TARGET_BD_ADDR: {
++			RTW_INFO("[MPT], [Connected Target BD ADDR]\n");
++			btOpcode = BT_LO_OP_GET_TARGET_BD_ADDR_L;
++			h2cParaLen = 0;
++			/* execute h2c and check respond c2h from bt fw is correct or not */
++			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++			/* construct respond status code and data. */
++			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++				pBtRsp->status = ((btOpcode << 8) | retStatus);
++				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++				return paraLen;
++			}
++			bdAddr[5] = pExtC2h->buf[0];
++			bdAddr[4] = pExtC2h->buf[1];
++			bdAddr[3] = pExtC2h->buf[2];
++
++			btOpcode = BT_LO_OP_GET_TARGET_BD_ADDR_H;
++			h2cParaLen = 0;
++			/* execute h2c and check respond c2h from bt fw is correct or not */
++			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++			/* construct respond status code and data. */
++			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++				pBtRsp->status = ((btOpcode << 8) | retStatus);
++				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++				return paraLen;
++			}
++			bdAddr[2] = pExtC2h->buf[0];
++			bdAddr[1] = pExtC2h->buf[1];
++			bdAddr[0] = pExtC2h->buf[2];
++
++			RTW_INFO("[MPT], Connected Target BDAddr:%s", bdAddr);
++			for (i = 0; i < 6; i++)
++				pBtRsp->pParamStart[i] = bdAddr[5 - i];
++			paraLen = 6;
++		}
++		break;
++		default:
++			pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++			return paraLen;
++			break;
++		}
++	}
++
++	pBtRsp->status = BT_STATUS_SUCCESS;
++	return paraLen;
++}
++
++
++
++u16
++mptbt_BtSetGeneral(
++		PADAPTER		Adapter,
++		PBT_REQ_CMD	pBtReq,
++		PBT_RSP_CMD	pBtRsp
++)
++{
++	u8				h2cParaBuf[6] = {0};
++	u8				h2cParaLen = 0;
++	u16				paraLen = 0;
++	u8				retStatus = BT_STATUS_BT_OP_SUCCESS;
++	u8				btOpcode;
++	u8				btOpcodeVer = 0;
++	u8				setType = 0;
++	u16				setParaLen = 0, validParaLen = 0;
++	u8				regType = 0, bdAddr[6] = {0}, calVal = 0;
++	u32				regAddr = 0, regValue = 0;
++	u32 				*pu4Tmp;
++	u16 				*pu2Tmp;
++	u8 				*pu1Tmp;
++
++	/*  */
++	/* check upper layer parameters */
++	/*  */
++
++	/* check upper layer opcode version */
++	if (pBtReq->opCodeVer != 1) {
++		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
++		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
++		return paraLen;
++	}
++	/* check upper layer parameter length */
++	if (pBtReq->paraLength < 1) {
++		RTW_INFO("[MPT], Error!! wrong parameter length=%d (should larger than 1)\n", pBtReq->paraLength);
++		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
++		return paraLen;
++	}
++	setParaLen = pBtReq->paraLength - 1;
++	setType = pBtReq->pParamStart[0];
++
++	RTW_INFO("[MPT], setType=%d, setParaLen=%d\n", setType, setParaLen);
++
++	/* check parameter first */
++	switch (setType) {
++	case BT_GSET_REG:
++		RTW_INFO("[MPT], [BT_GSET_REG]\n");
++		validParaLen = 9;
++		if (setParaLen == validParaLen) {
++			btOpcode = BT_LO_OP_WRITE_REG_VALUE;
++			regType = pBtReq->pParamStart[1];
++			pu4Tmp = (u32 *)&pBtReq->pParamStart[2];
++			regAddr = *pu4Tmp;
++			pu4Tmp = (u32 *)&pBtReq->pParamStart[6];
++			regValue = *pu4Tmp;
++			RTW_INFO("[MPT], BT_GSET_REG regType=0x%x, regAddr=0x%x, regValue=0x%x!!\n",
++				 regType, regAddr, regValue);
++			if (regType >= BT_REG_MAX) {
++				pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++				return paraLen;
++			} else {
++				if (((BT_REG_RF == regType) && (regAddr > 0x7f)) ||
++				    ((BT_REG_MODEM == regType) && (regAddr > 0x1ff)) ||
++				    ((BT_REG_BLUEWIZE == regType) && (regAddr > 0xfff)) ||
++				    ((BT_REG_VENDOR == regType) && (regAddr > 0xfff)) ||
++				    ((BT_REG_LE == regType) && (regAddr > 0xfff))) {
++					pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++					return paraLen;
++				}
++			}
++		}
++		break;
++	case BT_GSET_RESET:
++		RTW_INFO("[MPT], [BT_GSET_RESET]\n");
++		validParaLen = 0;
++		break;
++	case BT_GSET_TARGET_BD_ADDR:
++		RTW_INFO("[MPT], [BT_GSET_TARGET_BD_ADDR]\n");
++		validParaLen = 6;
++		if (setParaLen == validParaLen) {
++			btOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_H;
++			if ((pBtReq->pParamStart[1] == 0) &&
++			    (pBtReq->pParamStart[2] == 0) &&
++			    (pBtReq->pParamStart[3] == 0) &&
++			    (pBtReq->pParamStart[4] == 0) &&
++			    (pBtReq->pParamStart[5] == 0) &&
++			    (pBtReq->pParamStart[6] == 0)) {
++				RTW_INFO("[MPT], Error!! targetBDAddr=all zero\n");
++				pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++				return paraLen;
++			}
++			if ((pBtReq->pParamStart[1] == 0xff) &&
++			    (pBtReq->pParamStart[2] == 0xff) &&
++			    (pBtReq->pParamStart[3] == 0xff) &&
++			    (pBtReq->pParamStart[4] == 0xff) &&
++			    (pBtReq->pParamStart[5] == 0xff) &&
++			    (pBtReq->pParamStart[6] == 0xff)) {
++				RTW_INFO("[MPT], Error!! targetBDAddr=all 0xf\n");
++				pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++				return paraLen;
++			}
++			bdAddr[0] = pBtReq->pParamStart[6];
++			bdAddr[1] = pBtReq->pParamStart[5];
++			bdAddr[2] = pBtReq->pParamStart[4];
++			bdAddr[3] = pBtReq->pParamStart[3];
++			bdAddr[4] = pBtReq->pParamStart[2];
++			bdAddr[5] = pBtReq->pParamStart[1];
++			RTW_INFO("[MPT], target BDAddr:%x,%x,%x,%x,%x,%x\n",
++				bdAddr[0], bdAddr[1], bdAddr[2], bdAddr[3], bdAddr[4], bdAddr[5]);
++		}
++		break;
++	case BT_GSET_TX_PWR_FINETUNE:
++		RTW_INFO("[MPT], [BT_GSET_TX_PWR_FINETUNE]\n");
++		validParaLen = 1;
++		if (setParaLen == validParaLen) {
++			btOpcode = BT_LO_OP_SET_TX_POWER_CALIBRATION;
++			calVal = pBtReq->pParamStart[1];
++			if ((calVal < 1) || (calVal > 9)) {
++				pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++				return paraLen;
++			}
++			RTW_INFO("[MPT], calVal=%d\n", calVal);
++		}
++		break;
++	case BT_SET_TRACKING_INTERVAL:
++		RTW_INFO("[MPT], [BT_SET_TRACKING_INTERVAL] setParaLen =%d\n", setParaLen);
++
++		validParaLen = 1;
++		if (setParaLen == validParaLen)
++			calVal = pBtReq->pParamStart[1];
++		break;
++	case BT_SET_THERMAL_METER:
++		RTW_INFO("[MPT], [BT_SET_THERMAL_METER] setParaLen =%d\n", setParaLen);
++		validParaLen = 1;
++		if (setParaLen == validParaLen)
++			calVal = pBtReq->pParamStart[1];
++		break;
++	case BT_ENABLE_CFO_TRACKING:
++		RTW_INFO("[MPT], [BT_ENABLE_CFO_TRACKING] setParaLen =%d\n", setParaLen);
++		validParaLen = 1;
++		if (setParaLen == validParaLen)
++			calVal = pBtReq->pParamStart[1];
++		break;
++	case BT_GSET_UPDATE_BT_PATCH:
++
++		break;
++	default: {
++		RTW_INFO("[MPT], Error!! setType=%d, out of range\n", setType);
++		pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++		return paraLen;
++	}
++	break;
++	}
++	if (setParaLen != validParaLen) {
++		RTW_INFO("[MPT], Error!! wrong parameter length=%d for BT_SET_GEN_CMD cmd id=0x%x, paraLen should=0x%x\n",
++			 setParaLen, setType, validParaLen);
++		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
++		return paraLen;
++	}
++
++	/*  */
++	/* execute lower layer opcodes */
++	/*  */
++	if (BT_GSET_REG == setType) {
++		/* fill h2c parameters */
++		/* here we should write reg value first then write the address, adviced by Austin */
++		btOpcode = BT_LO_OP_WRITE_REG_VALUE;
++		h2cParaBuf[0] = pBtReq->pParamStart[6];
++		h2cParaBuf[1] = pBtReq->pParamStart[7];
++		h2cParaBuf[2] = pBtReq->pParamStart[8];
++		h2cParaLen = 3;
++		/* execute h2c and check respond c2h from bt fw is correct or not */
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++		/* construct respond status code and data. */
++		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++			pBtRsp->status = ((btOpcode << 8) | retStatus);
++			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++			return paraLen;
++		}
++
++		/* write reg address */
++		btOpcode = BT_LO_OP_WRITE_REG_ADDR;
++		h2cParaBuf[0] = regType;
++		h2cParaBuf[1] = pBtReq->pParamStart[2];
++		h2cParaBuf[2] = pBtReq->pParamStart[3];
++		h2cParaLen = 3;
++		/* execute h2c and check respond c2h from bt fw is correct or not */
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++		/* construct respond status code and data. */
++		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++			pBtRsp->status = ((btOpcode << 8) | retStatus);
++			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++			return paraLen;
++		}
++	} else if (BT_GSET_RESET == setType) {
++		btOpcode = BT_LO_OP_RESET;
++		h2cParaLen = 0;
++		/* execute h2c and check respond c2h from bt fw is correct or not */
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++		/* construct respond status code and data. */
++		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++			pBtRsp->status = ((btOpcode << 8) | retStatus);
++			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++			return paraLen;
++		}
++	} else if (BT_GSET_TARGET_BD_ADDR == setType) {
++		/* fill h2c parameters */
++		btOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_L;
++		h2cParaBuf[0] = pBtReq->pParamStart[1];
++		h2cParaBuf[1] = pBtReq->pParamStart[2];
++		h2cParaBuf[2] = pBtReq->pParamStart[3];
++		h2cParaLen = 3;
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++		/* ckeck bt return status. */
++		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++			pBtRsp->status = ((btOpcode << 8) | retStatus);
++			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++			return paraLen;
++		}
++
++		btOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_H;
++		h2cParaBuf[0] = pBtReq->pParamStart[4];
++		h2cParaBuf[1] = pBtReq->pParamStart[5];
++		h2cParaBuf[2] = pBtReq->pParamStart[6];
++		h2cParaLen = 3;
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++		/* ckeck bt return status. */
++		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++			pBtRsp->status = ((btOpcode << 8) | retStatus);
++			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++			return paraLen;
++		}
++	} else if (BT_GSET_TX_PWR_FINETUNE == setType) {
++		/* fill h2c parameters */
++		btOpcode = BT_LO_OP_SET_TX_POWER_CALIBRATION;
++		h2cParaBuf[0] = calVal;
++		h2cParaLen = 1;
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++		/* ckeck bt return status. */
++		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++			pBtRsp->status = ((btOpcode << 8) | retStatus);
++			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++			return paraLen;
++		}
++	} else if (BT_SET_TRACKING_INTERVAL == setType) {
++		/*	BT_LO_OP_SET_TRACKING_INTERVAL								= 0x22, */
++		/*	BT_LO_OP_SET_THERMAL_METER									= 0x23, */
++		/*	BT_LO_OP_ENABLE_CFO_TRACKING									= 0x24, */
++		btOpcode = BT_LO_OP_SET_TRACKING_INTERVAL;
++		h2cParaBuf[0] = calVal;
++		h2cParaLen = 1;
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++		/* ckeck bt return status. */
++		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++			pBtRsp->status = ((btOpcode << 8) | retStatus);
++			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++			return paraLen;
++		}
++	} else if (BT_SET_THERMAL_METER == setType) {
++		btOpcode = BT_LO_OP_SET_THERMAL_METER;
++		h2cParaBuf[0] = calVal;
++		h2cParaLen = 1;
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++		/* ckeck bt return status. */
++		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++			pBtRsp->status = ((btOpcode << 8) | retStatus);
++			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++			return paraLen;
++		}
++	} else if (BT_ENABLE_CFO_TRACKING == setType) {
++		btOpcode = BT_LO_OP_ENABLE_CFO_TRACKING;
++		h2cParaBuf[0] = calVal;
++		h2cParaLen = 1;
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++		/* ckeck bt return status. */
++		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++			pBtRsp->status = ((btOpcode << 8) | retStatus);
++			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++			return paraLen;
++		}
++	}
++
++	pBtRsp->status = BT_STATUS_SUCCESS;
++	return paraLen;
++}
++
++
++
++u16
++mptbt_BtSetTxRxPars(
++		PADAPTER		Adapter,
++		PBT_REQ_CMD	pBtReq,
++		PBT_RSP_CMD	pBtRsp
++)
++{
++	u8				h2cParaBuf[6] = {0};
++	u8				h2cParaLen = 0;
++	u16				paraLen = 0;
++	u8				retStatus = BT_STATUS_BT_OP_SUCCESS;
++	u8				btOpcode;
++	u8				btOpcodeVer = 0;
++	PBT_TXRX_PARAMETERS pTxRxPars = (PBT_TXRX_PARAMETERS)&pBtReq->pParamStart[0];
++	u16				lenTxRx = sizeof(BT_TXRX_PARAMETERS);
++	u8				i;
++	u8				bdAddr[6] = {0};
++
++	/*  */
++	/* check upper layer parameters */
++	/*  */
++
++	/* 1. check upper layer opcode version */
++	if (pBtReq->opCodeVer != 1) {
++		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
++		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
++		return paraLen;
++	}
++	/* 2. check upper layer parameter length */
++	if (pBtReq->paraLength == sizeof(BT_TXRX_PARAMETERS)) {
++		RTW_INFO("[MPT], pTxRxPars->txrxChannel=0x%x\n", pTxRxPars->txrxChannel);
++		RTW_INFO("[MPT], pTxRxPars->txrxTxPktCnt=0x%8x\n", pTxRxPars->txrxTxPktCnt);
++		RTW_INFO("[MPT], pTxRxPars->txrxTxPktInterval=0x%x\n", pTxRxPars->txrxTxPktInterval);
++		RTW_INFO("[MPT], pTxRxPars->txrxPayloadType=0x%x\n", pTxRxPars->txrxPayloadType);
++		RTW_INFO("[MPT], pTxRxPars->txrxPktType=0x%x\n", pTxRxPars->txrxPktType);
++		RTW_INFO("[MPT], pTxRxPars->txrxPayloadLen=0x%x\n", pTxRxPars->txrxPayloadLen);
++		RTW_INFO("[MPT], pTxRxPars->txrxPktHeader=0x%x\n", pTxRxPars->txrxPktHeader);
++		RTW_INFO("[MPT], pTxRxPars->txrxWhitenCoeff=0x%x\n", pTxRxPars->txrxWhitenCoeff);
++		bdAddr[0] = pTxRxPars->txrxBdaddr[5];
++		bdAddr[1] = pTxRxPars->txrxBdaddr[4];
++		bdAddr[2] = pTxRxPars->txrxBdaddr[3];
++		bdAddr[3] = pTxRxPars->txrxBdaddr[2];
++		bdAddr[4] = pTxRxPars->txrxBdaddr[1];
++		bdAddr[5] = pTxRxPars->txrxBdaddr[0];
++		RTW_INFO("[MPT], pTxRxPars->txrxBdaddr: %s", &bdAddr[0]);
++		RTW_INFO("[MPT], pTxRxPars->txrxTxGainIndex=0x%x\n", pTxRxPars->txrxTxGainIndex);
++	} else {
++		RTW_INFO("[MPT], Error!! pBtReq->paraLength=%d, correct Len=%d\n", pBtReq->paraLength, lenTxRx);
++		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
++		return paraLen;
++	}
++
++	/*  */
++	/* execute lower layer opcodes */
++	/*  */
++
++	/* fill h2c parameters */
++	btOpcode = BT_LO_OP_SET_PKT_HEADER;
++	if (pTxRxPars->txrxPktHeader > 0x3ffff) {
++		RTW_INFO("[MPT], Error!! pTxRxPars->txrxPktHeader=0x%x is out of range, (should be between 0x0~0x3ffff)\n", pTxRxPars->txrxPktHeader);
++		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++		return paraLen;
++	} else {
++		h2cParaBuf[0] = (u8)(pTxRxPars->txrxPktHeader & 0xff);
++		h2cParaBuf[1] = (u8)((pTxRxPars->txrxPktHeader & 0xff00) >> 8);
++		h2cParaBuf[2] = (u8)((pTxRxPars->txrxPktHeader & 0xff0000) >> 16);
++		h2cParaLen = 3;
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++	}
++
++	/* ckeck bt return status. */
++	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++		pBtRsp->status = ((btOpcode << 8) | retStatus);
++		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++		return paraLen;
++	}
++
++	/* fill h2c parameters */
++	btOpcode = BT_LO_OP_SET_PKT_TYPE_LEN;
++	{
++		u16	payloadLenLimit = 0;
++		switch (pTxRxPars->txrxPktType) {
++		case MP_BT_PKT_DH1:
++			payloadLenLimit = 27 * 8;
++			break;
++		case MP_BT_PKT_DH3:
++			payloadLenLimit = 183 * 8;
++			break;
++		case MP_BT_PKT_DH5:
++			payloadLenLimit = 339 * 8;
++			break;
++		case MP_BT_PKT_2DH1:
++			payloadLenLimit = 54 * 8;
++			break;
++		case MP_BT_PKT_2DH3:
++			payloadLenLimit = 367 * 8;
++			break;
++		case MP_BT_PKT_2DH5:
++			payloadLenLimit = 679 * 8;
++			break;
++		case MP_BT_PKT_3DH1:
++			payloadLenLimit = 83 * 8;
++			break;
++		case MP_BT_PKT_3DH3:
++			payloadLenLimit = 552 * 8;
++			break;
++		case MP_BT_PKT_3DH5:
++			payloadLenLimit = 1021 * 8;
++			break;
++		case MP_BT_PKT_LE:
++			payloadLenLimit = 39 * 8;
++			break;
++		default: {
++			RTW_INFO("[MPT], Error!! Unknown pTxRxPars->txrxPktType=0x%x\n", pTxRxPars->txrxPktType);
++			pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++			return paraLen;
++		}
++		break;
++		}
++
++		if (pTxRxPars->txrxPayloadLen > payloadLenLimit) {
++			RTW_INFO("[MPT], Error!! pTxRxPars->txrxPayloadLen=0x%x, (should smaller than %d)\n",
++				 pTxRxPars->txrxPayloadLen, payloadLenLimit);
++			pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++			return paraLen;
++		}
++
++		h2cParaBuf[0] = pTxRxPars->txrxPktType;
++		h2cParaBuf[1] = (u8)((pTxRxPars->txrxPayloadLen & 0xff));
++		h2cParaBuf[2] = (u8)((pTxRxPars->txrxPayloadLen & 0xff00) >> 8);
++		h2cParaLen = 3;
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++	}
++
++	/* ckeck bt return status. */
++	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++		pBtRsp->status = ((btOpcode << 8) | retStatus);
++		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++		return paraLen;
++	}
++
++	/* fill h2c parameters */
++	btOpcode = BT_LO_OP_SET_PKT_CNT_L_PL_TYPE;
++	if (pTxRxPars->txrxPayloadType > MP_BT_PAYLOAD_MAX) {
++		RTW_INFO("[MPT], Error!! pTxRxPars->txrxPayloadType=0x%x, (should be between 0~4)\n", pTxRxPars->txrxPayloadType);
++		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++		return paraLen;
++	} else {
++		h2cParaBuf[0] = (u8)((pTxRxPars->txrxTxPktCnt & 0xff));
++		h2cParaBuf[1] = (u8)((pTxRxPars->txrxTxPktCnt & 0xff00) >> 8);
++		h2cParaBuf[2] = pTxRxPars->txrxPayloadType;
++		h2cParaLen = 3;
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++	}
++
++	/* ckeck bt return status. */
++	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++		pBtRsp->status = ((btOpcode << 8) | retStatus);
++		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++		return paraLen;
++	}
++
++	/* fill h2c parameters */
++	btOpcode = BT_LO_OP_SET_PKT_CNT_H_PKT_INTV;
++	if (pTxRxPars->txrxTxPktInterval > 15) {
++		RTW_INFO("[MPT], Error!! pTxRxPars->txrxTxPktInterval=0x%x, (should be between 0~15)\n", pTxRxPars->txrxTxPktInterval);
++		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++		return paraLen;
++	} else {
++		h2cParaBuf[0] = (u8)((pTxRxPars->txrxTxPktCnt & 0xff0000) >> 16);
++		h2cParaBuf[1] = (u8)((pTxRxPars->txrxTxPktCnt & 0xff000000) >> 24);
++		h2cParaBuf[2] = pTxRxPars->txrxTxPktInterval;
++		h2cParaLen = 3;
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++	}
++
++	/* ckeck bt return status. */
++	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++		pBtRsp->status = ((btOpcode << 8) | retStatus);
++		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++		return paraLen;
++	}
++
++	/* fill h2c parameters */
++	btOpcode = BT_LO_OP_SET_WHITENCOEFF;
++	{
++		h2cParaBuf[0] = pTxRxPars->txrxWhitenCoeff;
++		h2cParaLen = 1;
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++	}
++
++	/* ckeck bt return status. */
++	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++		pBtRsp->status = ((btOpcode << 8) | retStatus);
++		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++		return paraLen;
++	}
++
++
++	/* fill h2c parameters */
++	btOpcode = BT_LO_OP_SET_CHNL_TX_GAIN;
++	if ((pTxRxPars->txrxChannel > 78) ||
++	    (pTxRxPars->txrxTxGainIndex > 7)) {
++		RTW_INFO("[MPT], Error!! pTxRxPars->txrxChannel=0x%x, (should be between 0~78)\n", pTxRxPars->txrxChannel);
++		RTW_INFO("[MPT], Error!! pTxRxPars->txrxTxGainIndex=0x%x, (should be between 0~7)\n", pTxRxPars->txrxTxGainIndex);
++		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++		return paraLen;
++	} else {
++		h2cParaBuf[0] = pTxRxPars->txrxChannel;
++		h2cParaBuf[1] = pTxRxPars->txrxTxGainIndex;
++		h2cParaLen = 2;
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++	}
++
++	/* ckeck bt return status. */
++	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++		pBtRsp->status = ((btOpcode << 8) | retStatus);
++		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++		return paraLen;
++	}
++
++	/* fill h2c parameters */
++	btOpcode = BT_LO_OP_SET_BD_ADDR_L;
++	if ((pTxRxPars->txrxBdaddr[0] == 0) &&
++	    (pTxRxPars->txrxBdaddr[1] == 0) &&
++	    (pTxRxPars->txrxBdaddr[2] == 0) &&
++	    (pTxRxPars->txrxBdaddr[3] == 0) &&
++	    (pTxRxPars->txrxBdaddr[4] == 0) &&
++	    (pTxRxPars->txrxBdaddr[5] == 0)) {
++		RTW_INFO("[MPT], Error!! pTxRxPars->txrxBdaddr=all zero\n");
++		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++		return paraLen;
++	}
++	if ((pTxRxPars->txrxBdaddr[0] == 0xff) &&
++	    (pTxRxPars->txrxBdaddr[1] == 0xff) &&
++	    (pTxRxPars->txrxBdaddr[2] == 0xff) &&
++	    (pTxRxPars->txrxBdaddr[3] == 0xff) &&
++	    (pTxRxPars->txrxBdaddr[4] == 0xff) &&
++	    (pTxRxPars->txrxBdaddr[5] == 0xff)) {
++		RTW_INFO("[MPT], Error!! pTxRxPars->txrxBdaddr=all 0xf\n");
++		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++		return paraLen;
++	}
++
++	{
++		h2cParaBuf[0] = pTxRxPars->txrxBdaddr[0];
++		h2cParaBuf[1] = pTxRxPars->txrxBdaddr[1];
++		h2cParaBuf[2] = pTxRxPars->txrxBdaddr[2];
++		h2cParaLen = 3;
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++	}
++	/* ckeck bt return status. */
++	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++		pBtRsp->status = ((btOpcode << 8) | retStatus);
++		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++		return paraLen;
++	}
++
++	btOpcode = BT_LO_OP_SET_BD_ADDR_H;
++	{
++		h2cParaBuf[0] = pTxRxPars->txrxBdaddr[3];
++		h2cParaBuf[1] = pTxRxPars->txrxBdaddr[4];
++		h2cParaBuf[2] = pTxRxPars->txrxBdaddr[5];
++		h2cParaLen = 3;
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++	}
++	/* ckeck bt return status. */
++	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++		pBtRsp->status = ((btOpcode << 8) | retStatus);
++		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++		return paraLen;
++	}
++
++	pBtRsp->status = BT_STATUS_SUCCESS;
++	return paraLen;
++}
++
++
++
++u16
++mptbt_BtTestCtrl(
++		PADAPTER		Adapter,
++		PBT_REQ_CMD	pBtReq,
++		PBT_RSP_CMD	pBtRsp
++)
++{
++	u8				h2cParaBuf[6] = {0};
++	u8				h2cParaLen = 0;
++	u16				paraLen = 0;
++	u8				retStatus = BT_STATUS_BT_OP_SUCCESS;
++	u8				btOpcode;
++	u8				btOpcodeVer = 0;
++	u8				testCtrl = 0;
++
++	/*  */
++	/* check upper layer parameters */
++	/*  */
++
++	/* 1. check upper layer opcode version */
++	if (pBtReq->opCodeVer != 1) {
++		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
++		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
++		return paraLen;
++	}
++	/* 2. check upper layer parameter length */
++	if (1 == pBtReq->paraLength) {
++		testCtrl = pBtReq->pParamStart[0];
++		RTW_INFO("[MPT], testCtrl=%d\n", testCtrl);
++	} else {
++		RTW_INFO("[MPT], Error!! wrong parameter length=%d (should be 1)\n", pBtReq->paraLength);
++		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
++		return paraLen;
++	}
++
++	/*  */
++	/* execute lower layer opcodes */
++	/*  */
++
++	/* 1. fill h2c parameters	 */
++	/* check bt mode */
++	btOpcode = BT_LO_OP_TEST_CTRL;
++	if (testCtrl >= MP_BT_TEST_MAX) {
++		RTW_INFO("[MPT], Error!! testCtrl=0x%x, (should be between smaller or equal to 0x%x)\n",
++			 testCtrl, MP_BT_TEST_MAX - 1);
++		pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
++		return paraLen;
++	} else {
++		h2cParaBuf[0] = testCtrl;
++		h2cParaLen = 1;
++		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
++	}
++
++	/* 3. construct respond status code and data. */
++	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++		pBtRsp->status = ((btOpcode << 8) | retStatus);
++		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++		return paraLen;
++	}
++
++	pBtRsp->status = BT_STATUS_SUCCESS;
++	return paraLen;
++}
++
++
++u16
++mptbt_TestBT(
++		PADAPTER		Adapter,
++		PBT_REQ_CMD	pBtReq,
++		PBT_RSP_CMD	pBtRsp
++)
++{
++
++	u8				h2cParaBuf[6] = {0};
++	u8				h2cParaLen = 0;
++	u16				paraLen = 0;
++	u8				retStatus = BT_STATUS_BT_OP_SUCCESS;
++	u8				btOpcode;
++	u8				btOpcodeVer = 0;
++	u8				testCtrl = 0;
++
++	/* 1. fill h2c parameters	 */
++	btOpcode =  0x11;
++	h2cParaBuf[0] = 0x11;
++	h2cParaBuf[1] = 0x0;
++	h2cParaBuf[2] = 0x0;
++	h2cParaBuf[3] = 0x0;
++	h2cParaBuf[4] = 0x0;
++	h2cParaLen = 1;
++	/*	retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); */
++	retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, h2cParaBuf, h2cParaLen);
++
++
++	/* 3. construct respond status code and data. */
++	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
++		pBtRsp->status = ((btOpcode << 8) | retStatus);
++		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
++		return paraLen;
++	}
++
++	pBtRsp->status = BT_STATUS_SUCCESS;
++	return paraLen;
++}
++
++void
++mptbt_BtControlProcess(
++	PADAPTER	Adapter,
++	void			*pInBuf
++)
++{
++	u8			H2C_Parameter[6] = {0};
++	PBT_H2C		pH2c = (PBT_H2C)&H2C_Parameter[0];
++	PMPT_CONTEXT	pMptCtx = &(Adapter->mppriv.mpt_ctx);
++	PBT_REQ_CMD	pBtReq = (PBT_REQ_CMD)pInBuf;
++	PBT_RSP_CMD	pBtRsp;
++	u8			i;
++
++
++	RTW_INFO("[MPT], mptbt_BtControlProcess()=========>\n");
++
++	RTW_INFO("[MPT], input opCodeVer=%d\n", pBtReq->opCodeVer);
++	RTW_INFO("[MPT], input OpCode=%d\n", pBtReq->OpCode);
++	RTW_INFO("[MPT], paraLength=%d\n", pBtReq->paraLength);
++	if (pBtReq->paraLength) {
++		/* RTW_INFO("[MPT], parameters(hex):0x%x %d\n",&pBtReq->pParamStart[0], pBtReq->paraLength); */
++	}
++
++	_rtw_memset((void *)pMptCtx->mptOutBuf, 0, 100);
++	pMptCtx->mptOutLen = 4; /* length of (BT_RSP_CMD.status+BT_RSP_CMD.paraLength) */
++
++	pBtRsp = (PBT_RSP_CMD)pMptCtx->mptOutBuf;
++	pBtRsp->status = BT_STATUS_SUCCESS;
++	pBtRsp->paraLength = 0x0;
++
++	/* The following we should maintain the User OP codes sent by upper layer */
++	switch (pBtReq->OpCode) {
++	case BT_UP_OP_BT_READY:
++		RTW_INFO("[MPT], OPcode : [BT_READY]\n");
++		pBtRsp->paraLength = mptbt_BtReady(Adapter, pBtReq, pBtRsp);
++		break;
++	case BT_UP_OP_BT_SET_MODE:
++		RTW_INFO("[MPT], OPcode : [BT_SET_MODE]\n");
++		pBtRsp->paraLength = mptbt_BtSetMode(Adapter, pBtReq, pBtRsp);
++		break;
++	case BT_UP_OP_BT_SET_TX_RX_PARAMETER:
++		RTW_INFO("[MPT], OPcode : [BT_SET_TXRX_PARAMETER]\n");
++		pBtRsp->paraLength = mptbt_BtSetTxRxPars(Adapter, pBtReq, pBtRsp);
++		break;
++	case BT_UP_OP_BT_SET_GENERAL:
++		RTW_INFO("[MPT], OPcode : [BT_SET_GENERAL]\n");
++		pBtRsp->paraLength = mptbt_BtSetGeneral(Adapter, pBtReq, pBtRsp);
++		break;
++	case BT_UP_OP_BT_GET_GENERAL:
++		RTW_INFO("[MPT], OPcode : [BT_GET_GENERAL]\n");
++		pBtRsp->paraLength = mptbt_BtGetGeneral(Adapter, pBtReq, pBtRsp);
++		break;
++	case BT_UP_OP_BT_TEST_CTRL:
++		RTW_INFO("[MPT], OPcode : [BT_TEST_CTRL]\n");
++		pBtRsp->paraLength = mptbt_BtTestCtrl(Adapter, pBtReq, pBtRsp);
++		break;
++	case BT_UP_OP_TEST_BT:
++		RTW_INFO("[MPT], OPcode : [TEST_BT]\n");
++		pBtRsp->paraLength = mptbt_TestBT(Adapter, pBtReq, pBtRsp);
++		break;
++	default:
++		RTW_INFO("[MPT], Error!! OPcode : UNDEFINED!!!!\n");
++		pBtRsp->status = BT_STATUS_UNKNOWN_OPCODE_U;
++		pBtRsp->paraLength = 0x0;
++		break;
++	}
++
++	pMptCtx->mptOutLen += pBtRsp->paraLength;
++
++	RTW_INFO("[MPT], pMptCtx->mptOutLen=%d, pBtRsp->paraLength=%d\n", pMptCtx->mptOutLen, pBtRsp->paraLength);
++	RTW_INFO("[MPT], mptbt_BtControlProcess()<=========\n");
++}
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_btcoex.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_btcoex.c
+new file mode 100644
+index 000000000..a3c8ee316
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_btcoex.c
+@@ -0,0 +1,1801 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#include <drv_types.h>
++#include <hal_data.h>
++#ifdef CONFIG_BT_COEXIST
++#include <hal_btcoex.h>
++
++void rtw_btcoex_Initialize(PADAPTER padapter)
++{
++	hal_btcoex_Initialize(padapter);
++}
++
++void rtw_btcoex_PowerOnSetting(PADAPTER padapter)
++{
++	hal_btcoex_PowerOnSetting(padapter);
++}
++
++void rtw_btcoex_AntInfoSetting(PADAPTER padapter)
++{
++	hal_btcoex_AntInfoSetting(padapter);
++}
++
++void rtw_btcoex_PowerOffSetting(PADAPTER padapter)
++{
++	hal_btcoex_PowerOffSetting(padapter);
++}
++
++void rtw_btcoex_PreLoadFirmware(PADAPTER padapter)
++{
++	hal_btcoex_PreLoadFirmware(padapter);
++}
++
++void rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly)
++{
++	hal_btcoex_InitHwConfig(padapter, bWifiOnly);
++}
++
++void rtw_btcoex_IpsNotify(PADAPTER padapter, u8 type)
++{
++	PHAL_DATA_TYPE	pHalData;
++
++	pHalData = GET_HAL_DATA(padapter);
++	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++		return;
++
++	hal_btcoex_IpsNotify(padapter, type);
++}
++
++void rtw_btcoex_LpsNotify(PADAPTER padapter, u8 type)
++{
++	PHAL_DATA_TYPE	pHalData;
++
++	pHalData = GET_HAL_DATA(padapter);
++	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++		return;
++
++	hal_btcoex_LpsNotify(padapter, type);
++}
++
++void rtw_btcoex_ScanNotify(PADAPTER padapter, u8 type)
++{
++	PHAL_DATA_TYPE	pHalData;
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++	struct bt_coex_info *pcoex_info = &padapter->coex_info;
++	PBT_MGNT	pBtMgnt = &pcoex_info->BtMgnt;
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++
++	pHalData = GET_HAL_DATA(padapter);
++	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++		return;
++
++	if (_FALSE == type) {
++		#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_SURVEY))
++			return;
++		#endif
++
++		if (DEV_MGMT_TX_NUM(adapter_to_dvobj(padapter))
++			|| DEV_ROCH_NUM(adapter_to_dvobj(padapter)))
++			return;
++	}
++
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++	if (pBtMgnt->ExtConfig.bEnableWifiScanNotify)
++		rtw_btcoex_SendScanNotify(padapter, type);
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX	 */
++
++	hal_btcoex_ScanNotify(padapter, type);
++}
++
++static void _rtw_btcoex_connect_notify(PADAPTER padapter, u8 action)
++{
++	PHAL_DATA_TYPE	pHalData;
++
++	pHalData = GET_HAL_DATA(padapter);
++	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++		return;
++
++#ifdef DBG_CONFIG_ERROR_RESET
++	if (_TRUE == rtw_hal_sreset_inprogress(padapter)) {
++		RTW_INFO(FUNC_ADPT_FMT ": [BTCoex] under reset, skip notify!\n",
++			 FUNC_ADPT_ARG(padapter));
++		return;
++	}
++#endif /* DBG_CONFIG_ERROR_RESET */
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (_FALSE == action) {
++		if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING))
++			return;
++	}
++#endif
++
++	hal_btcoex_ConnectNotify(padapter, action);
++}
++
++void rtw_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus)
++{
++	PHAL_DATA_TYPE	pHalData;
++
++	pHalData = GET_HAL_DATA(padapter);
++	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++		return;
++
++#ifdef DBG_CONFIG_ERROR_RESET
++	if (_TRUE == rtw_hal_sreset_inprogress(padapter)) {
++		RTW_INFO(FUNC_ADPT_FMT ": [BTCoex] under reset, skip notify!\n",
++			 FUNC_ADPT_ARG(padapter));
++		return;
++	}
++#endif /* DBG_CONFIG_ERROR_RESET */
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (RT_MEDIA_DISCONNECT == mediaStatus) {
++		if (rtw_mi_buddy_check_fwstate(padapter, WIFI_ASOC_STATE))
++			return;
++	}
++#endif /* CONFIG_CONCURRENT_MODE */
++
++	if ((RT_MEDIA_CONNECT == mediaStatus)
++	    && (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE))
++		rtw_hal_set_hwreg(padapter, HW_VAR_DL_RSVD_PAGE, NULL);
++
++	hal_btcoex_MediaStatusNotify(padapter, mediaStatus);
++}
++
++void rtw_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType)
++{
++	PHAL_DATA_TYPE	pHalData;
++
++	pHalData = GET_HAL_DATA(padapter);
++	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++		return;
++
++	hal_btcoex_SpecialPacketNotify(padapter, pktType);
++}
++
++void rtw_btcoex_IQKNotify(PADAPTER padapter, u8 state)
++{
++	PHAL_DATA_TYPE	pHalData;
++
++	pHalData = GET_HAL_DATA(padapter);
++	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++		return;
++
++	hal_btcoex_IQKNotify(padapter, state);
++}
++
++void rtw_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
++{
++	PHAL_DATA_TYPE	pHalData;
++
++	pHalData = GET_HAL_DATA(padapter);
++	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++		return;
++
++	hal_btcoex_BtInfoNotify(padapter, length, tmpBuf);
++}
++
++void rtw_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
++{
++	PHAL_DATA_TYPE	pHalData;
++
++	pHalData = GET_HAL_DATA(padapter);
++	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++		return;
++
++	if (padapter->registrypriv.mp_mode == 1)
++		return;
++
++	hal_btcoex_BtMpRptNotify(padapter, length, tmpBuf);
++}
++
++void rtw_btcoex_SuspendNotify(PADAPTER padapter, u8 state)
++{
++	PHAL_DATA_TYPE	pHalData;
++
++	pHalData = GET_HAL_DATA(padapter);
++	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++		return;
++
++	hal_btcoex_SuspendNotify(padapter, state);
++}
++
++void rtw_btcoex_HaltNotify(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE	pHalData;
++	u8 do_halt = 1;
++
++	pHalData = GET_HAL_DATA(padapter);
++	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++		do_halt = 0;
++
++	if (_FALSE == padapter->bup) {
++		RTW_INFO(FUNC_ADPT_FMT ": bup=%d Skip!\n",
++			 FUNC_ADPT_ARG(padapter), padapter->bup);
++		do_halt = 0;
++	}
++
++	if (rtw_is_surprise_removed(padapter)) {
++		RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=%s Skip!\n",
++			FUNC_ADPT_ARG(padapter), rtw_is_surprise_removed(padapter) ? "True" : "False");
++		do_halt = 0;
++	}
++
++	hal_btcoex_HaltNotify(padapter, do_halt);
++}
++
++void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type)
++{
++	hal_btcoex_switchband_notify(under_scan, band_type);
++}
++
++void rtw_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length)
++{
++	hal_btcoex_WlFwDbgInfoNotify(padapter, tmpBuf, length);
++}
++
++void rtw_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id)
++{
++	hal_btcoex_rx_rate_change_notify(padapter, is_data_frame, rate_id);
++}
++
++void rtw_btcoex_SwitchBtTRxMask(PADAPTER padapter)
++{
++	hal_btcoex_SwitchBtTRxMask(padapter);
++}
++
++void rtw_btcoex_Switch(PADAPTER padapter, u8 enable)
++{
++	hal_btcoex_SetBTCoexist(padapter, enable);
++}
++
++u8 rtw_btcoex_IsBtDisabled(PADAPTER padapter)
++{
++	return hal_btcoex_IsBtDisabled(padapter);
++}
++
++void rtw_btcoex_Handler(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE	pHalData;
++
++	pHalData = GET_HAL_DATA(padapter);
++
++	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++		return;
++
++	hal_btcoex_Hanlder(padapter);
++}
++
++s32 rtw_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter)
++{
++	s32 coexctrl;
++
++	coexctrl = hal_btcoex_IsBTCoexRejectAMPDU(padapter);
++
++	return coexctrl;
++}
++
++s32 rtw_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter)
++{
++	s32 coexctrl;
++
++	coexctrl = hal_btcoex_IsBTCoexCtrlAMPDUSize(padapter);
++
++	return coexctrl;
++}
++
++u32 rtw_btcoex_GetAMPDUSize(PADAPTER padapter)
++{
++	u32 size;
++
++	size = hal_btcoex_GetAMPDUSize(padapter);
++
++	return size;
++}
++
++void rtw_btcoex_SetManualControl(PADAPTER padapter, u8 manual)
++{
++	if (_TRUE == manual)
++		hal_btcoex_SetManualControl(padapter, _TRUE);
++	else
++		hal_btcoex_SetManualControl(padapter, _FALSE);
++}
++
++u8 rtw_btcoex_1Ant(PADAPTER padapter)
++{
++	return hal_btcoex_1Ant(padapter);
++}
++
++u8 rtw_btcoex_IsBtControlLps(PADAPTER padapter)
++{
++	return hal_btcoex_IsBtControlLps(padapter);
++}
++
++u8 rtw_btcoex_IsLpsOn(PADAPTER padapter)
++{
++	return hal_btcoex_IsLpsOn(padapter);
++}
++
++u8 rtw_btcoex_RpwmVal(PADAPTER padapter)
++{
++	return hal_btcoex_RpwmVal(padapter);
++}
++
++u8 rtw_btcoex_LpsVal(PADAPTER padapter)
++{
++	return hal_btcoex_LpsVal(padapter);
++}
++
++u32 rtw_btcoex_GetRaMask(PADAPTER padapter)
++{
++	return hal_btcoex_GetRaMask(padapter);
++}
++
++u8 rtw_btcoex_query_reduced_wl_pwr_lvl(PADAPTER padapter)
++{
++	return hal_btcoex_query_reduced_wl_pwr_lvl(padapter);
++}
++
++void rtw_btcoex_set_reduced_wl_pwr_lvl(PADAPTER padapter, u8 val)
++{
++	hal_btcoex_set_reduced_wl_pwr_lvl(padapter, val);
++}
++
++void rtw_btcoex_do_reduce_wl_pwr_lvl(PADAPTER padapter)
++{
++	hal_btcoex_do_reduce_wl_pwr_lvl(padapter);
++}
++
++void rtw_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen)
++{
++	hal_btcoex_RecordPwrMode(padapter, pCmdBuf, cmdLen);
++}
++
++void rtw_btcoex_DisplayBtCoexInfo(PADAPTER padapter, u8 *pbuf, u32 bufsize)
++{
++	hal_btcoex_DisplayBtCoexInfo(padapter, pbuf, bufsize);
++}
++
++void rtw_btcoex_SetDBG(PADAPTER padapter, u32 *pDbgModule)
++{
++	hal_btcoex_SetDBG(padapter, pDbgModule);
++}
++
++u32 rtw_btcoex_GetDBG(PADAPTER padapter, u8 *pStrBuf, u32 bufSize)
++{
++	return hal_btcoex_GetDBG(padapter, pStrBuf, bufSize);
++}
++
++u8 rtw_btcoex_IncreaseScanDeviceNum(PADAPTER padapter)
++{
++	return hal_btcoex_IncreaseScanDeviceNum(padapter);
++}
++
++u8 rtw_btcoex_IsBtLinkExist(PADAPTER padapter)
++{
++	return hal_btcoex_IsBtLinkExist(padapter);
++}
++
++void rtw_btcoex_SetBtPatchVersion(PADAPTER padapter, u16 btHciVer, u16 btPatchVer)
++{
++	hal_btcoex_SetBtPatchVersion(padapter, btHciVer, btPatchVer);
++}
++
++void rtw_btcoex_SetHciVersion(PADAPTER  padapter, u16 hciVersion)
++{
++	hal_btcoex_SetHciVersion(padapter, hciVersion);
++}
++
++void rtw_btcoex_StackUpdateProfileInfo(void)
++{
++	hal_btcoex_StackUpdateProfileInfo();
++}
++
++void rtw_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON)
++{
++	hal_btcoex_pta_off_on_notify(padapter, bBTON);
++}
++
++#ifdef CONFIG_RF4CE_COEXIST
++void rtw_btcoex_SetRf4ceLinkState(PADAPTER padapter, u8 state)
++{
++	hal_btcoex_set_rf4ce_link_state(state);
++}
++
++u8 rtw_btcoex_GetRf4ceLinkState(PADAPTER padapter)
++{
++	return hal_btcoex_get_rf4ce_link_state();
++}
++#endif
++
++/* ==================================================
++ * Below Functions are called by BT-Coex
++ * ================================================== */
++void rtw_btcoex_rx_ampdu_apply(PADAPTER padapter)
++{
++	rtw_rx_ampdu_apply(padapter);
++}
++
++void rtw_btcoex_LPS_Enter(PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrpriv;
++	u8 lpsVal;
++
++
++	pwrpriv = adapter_to_pwrctl(padapter);
++
++	pwrpriv->bpower_saving = _TRUE;
++	lpsVal = rtw_btcoex_LpsVal(padapter);
++	rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, lpsVal, "BTCOEX");
++}
++
++u8 rtw_btcoex_LPS_Leave(PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrpriv;
++
++
++	pwrpriv = adapter_to_pwrctl(padapter);
++
++	if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
++		rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "BTCOEX");
++		pwrpriv->bpower_saving = _FALSE;
++	}
++
++	return _TRUE;
++}
++
++u16 rtw_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data)
++{
++	return hal_btcoex_btreg_read(padapter, type, addr, data);
++}
++
++u16 rtw_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val)
++{
++	return hal_btcoex_btreg_write(padapter, type, addr, val);
++}
++
++u16 rtw_btcoex_btset_testmode(PADAPTER padapter, u8 type)
++{
++	return hal_btcoex_btset_testode(padapter, type);
++}
++
++u8 rtw_btcoex_get_reduce_wl_txpwr(PADAPTER padapter)
++{
++	return rtw_btcoex_query_reduced_wl_pwr_lvl(padapter);
++}
++
++u8 rtw_btcoex_get_bt_coexist(PADAPTER padapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	return pHalData->EEPROMBluetoothCoexist;
++}
++
++u8 rtw_btcoex_get_chip_type(PADAPTER padapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	return pHalData->EEPROMBluetoothType;
++}
++
++u8 rtw_btcoex_get_pg_ant_num(PADAPTER padapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	return pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1;
++}
++
++u8 rtw_btcoex_get_pg_single_ant_path(PADAPTER padapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	return pHalData->ant_path;
++}
++
++u8 rtw_btcoex_get_pg_rfe_type(PADAPTER padapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	return pHalData->rfe_type;
++}
++
++u8 rtw_btcoex_is_tfbga_package_type(PADAPTER padapter)
++{
++#ifdef CONFIG_RTL8723B
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA80)
++	    || (pHalData->PackageType == PACKAGE_TFBGA90))
++		return _TRUE;
++#endif
++
++	return _FALSE;
++}
++
++u8 rtw_btcoex_get_ant_div_cfg(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE pHalData;
++
++	pHalData = GET_HAL_DATA(padapter);
++	
++	return (pHalData->AntDivCfg == 0) ? _FALSE : _TRUE;
++}
++
++/* ==================================================
++ * Below Functions are BT-Coex socket related function
++ * ================================================== */
++
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++_adapter *pbtcoexadapter; /* = NULL; */ /* do not initialise globals to 0 or NULL */
++u8 rtw_btcoex_btinfo_cmd(_adapter *adapter, u8 *buf, u16 len)
++{
++	struct cmd_obj *ph2c;
++	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++	u8 *btinfo;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++	u8	res = _SUCCESS;
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	btinfo = rtw_zmalloc(len);
++	if (btinfo == NULL) {
++		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
++		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm->ec_id = BTINFO_WK_CID;
++	pdrvextra_cmd_parm->type = 0;
++	pdrvextra_cmd_parm->size = len;
++	pdrvextra_cmd_parm->pbuf = btinfo;
++
++	_rtw_memcpy(btinfo, buf, len);
++
++	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++	return res;
++}
++
++u8 rtw_btcoex_send_event_to_BT(_adapter *padapter, u8 status,  u8 event_code, u8 opcode_low, u8 opcode_high, u8 *dbg_msg)
++{
++	u8 localBuf[6] = "";
++	u8 *pRetPar;
++	u8	len = 0, tx_event_length = 0;
++	rtw_HCI_event *pEvent;
++
++	pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++	pEvent->EventCode = event_code;
++	pEvent->Data[0] = 0x1;	/* packet # */
++	pEvent->Data[1] = opcode_low;
++	pEvent->Data[2] = opcode_high;
++	len = len + 3;
++
++	/* Return parameters starts from here */
++	pRetPar = &pEvent->Data[len];
++	pRetPar[0] = status;		/* status */
++
++	len++;
++	pEvent->Length = len;
++
++	/* total tx event length + EventCode length + sizeof(length) */
++	tx_event_length = pEvent->Length + 2;
++#if 0
++	rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, dbg_msg);
++#endif
++	status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++
++	return status;
++}
++
++/*
++Ref:
++Realtek Wi-Fi Driver
++Host Controller Interface for
++Bluetooth 3.0 + HS V1.4 2013/02/07
++
++Window team code & BT team code
++ */
++
++
++u8 rtw_btcoex_parse_BT_info_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++#define BT_INFO_LENGTH 8
++
++	u8 curPollEnable = pcmd[0];
++	u8 curPollTime = pcmd[1];
++	u8 btInfoReason = pcmd[2];
++	u8 btInfoLen = pcmd[3];
++	u8 btinfo[BT_INFO_LENGTH];
++
++	u8 localBuf[6] = "";
++	u8 *pRetPar;
++	u8	len = 0, tx_event_length = 0;
++	RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
++	rtw_HCI_event *pEvent;
++
++	/* RTW_INFO("%s\n",__func__);
++	RTW_INFO("current Poll Enable: %d, currrent Poll Time: %d\n",curPollEnable,curPollTime);
++	RTW_INFO("BT Info reason: %d, BT Info length: %d\n",btInfoReason,btInfoLen);
++	RTW_INFO("%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n"
++		,pcmd[4],pcmd[5],pcmd[6],pcmd[7],pcmd[8],pcmd[9],pcmd[10],pcmd[11]);*/
++
++	_rtw_memset(btinfo, 0, BT_INFO_LENGTH);
++
++#if 1
++	if (BT_INFO_LENGTH != btInfoLen) {
++		status = HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE;
++		RTW_INFO("Error BT Info Length: %d\n", btInfoLen);
++		/* return _FAIL; */
++	} else
++#endif
++	{
++		if (0x1 == btInfoReason || 0x2 == btInfoReason) {
++			_rtw_memcpy(btinfo, &pcmd[4], btInfoLen);
++			btinfo[0] = btInfoReason;
++			rtw_btcoex_btinfo_cmd(padapter, btinfo, btInfoLen);
++		} else
++			RTW_INFO("Other BT info reason\n");
++	}
++
++	/* send complete event to BT */
++	{
++
++		pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++		pEvent->Data[0] = 0x1;	/* packet # */
++		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_INFO_NOTIFY, OGF_EXTENSION);
++		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_INFO_NOTIFY, OGF_EXTENSION);
++		len = len + 3;
++
++		/* Return parameters starts from here */
++		pRetPar = &pEvent->Data[len];
++		pRetPar[0] = status;		/* status */
++
++		len++;
++		pEvent->Length = len;
++
++		/* total tx event length + EventCode length + sizeof(length) */
++		tx_event_length = pEvent->Length + 2;
++#if 0
++		rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT_info_event");
++#endif
++		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++
++		return status;
++		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++	}
++}
++
++u8 rtw_btcoex_parse_BT_patch_ver_info_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++	RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
++	u16		btPatchVer = 0x0, btHciVer = 0x0;
++	/* u16		*pU2tmp; */
++
++	u8 localBuf[6] = "";
++	u8 *pRetPar;
++	u8	len = 0, tx_event_length = 0;
++	rtw_HCI_event *pEvent;
++
++	btHciVer = pcmd[0] | pcmd[1] << 8;
++	btPatchVer = pcmd[2] | pcmd[3] << 8;
++
++
++	RTW_INFO("%s, cmd:%02x %02x %02x %02x\n", __func__, pcmd[0] , pcmd[1] , pcmd[2] , pcmd[3]);
++	RTW_INFO("%s, HCI Ver:%d, Patch Ver:%d\n", __func__, btHciVer, btPatchVer);
++
++	rtw_btcoex_SetBtPatchVersion(padapter, btHciVer, btPatchVer);
++
++
++	/* send complete event to BT */
++	{
++		pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++		pEvent->Data[0] = 0x1;	/* packet # */
++		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_PATCH_VERSION_NOTIFY, OGF_EXTENSION);
++		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_PATCH_VERSION_NOTIFY, OGF_EXTENSION);
++		len = len + 3;
++
++		/* Return parameters starts from here */
++		pRetPar = &pEvent->Data[len];
++		pRetPar[0] = status;		/* status */
++
++		len++;
++		pEvent->Length = len;
++
++		/* total tx event length + EventCode length + sizeof(length) */
++		tx_event_length = pEvent->Length + 2;
++#if 0
++		rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT_patch_event");
++#endif
++		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++		return status;
++		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++	}
++}
++
++u8 rtw_btcoex_parse_HCI_Ver_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++	RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
++	u16 hciver = pcmd[0] | pcmd[1] << 8;
++
++	u8 localBuf[6] = "";
++	u8 *pRetPar;
++	u8	len = 0, tx_event_length = 0;
++	rtw_HCI_event *pEvent;
++
++	struct bt_coex_info *pcoex_info = &padapter->coex_info;
++	PBT_MGNT	pBtMgnt = &pcoex_info->BtMgnt;
++	pBtMgnt->ExtConfig.HCIExtensionVer = hciver;
++	RTW_INFO("%s, HCI Version: %d\n", __func__, pBtMgnt->ExtConfig.HCIExtensionVer);
++	if (pBtMgnt->ExtConfig.HCIExtensionVer  < 4) {
++		status = HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE;
++		RTW_INFO("%s, Version = %d, HCI Version < 4\n", __func__, pBtMgnt->ExtConfig.HCIExtensionVer);
++	} else
++		rtw_btcoex_SetHciVersion(padapter, hciver);
++	/* send complete event to BT */
++	{
++		pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++		pEvent->Data[0] = 0x1;	/* packet # */
++		pEvent->Data[1] = HCIOPCODELOW(HCI_EXTENSION_VERSION_NOTIFY, OGF_EXTENSION);
++		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_EXTENSION_VERSION_NOTIFY, OGF_EXTENSION);
++		len = len + 3;
++
++		/* Return parameters starts from here */
++		pRetPar = &pEvent->Data[len];
++		pRetPar[0] = status;		/* status */
++
++		len++;
++		pEvent->Length = len;
++
++		/* total tx event length + EventCode length + sizeof(length) */
++		tx_event_length = pEvent->Length + 2;
++
++		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++		return status;
++		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++	}
++
++}
++
++u8 rtw_btcoex_parse_WIFI_scan_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++	RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
++
++	u8 localBuf[6] = "";
++	u8 *pRetPar;
++	u8	len = 0, tx_event_length = 0;
++	rtw_HCI_event *pEvent;
++
++	struct bt_coex_info *pcoex_info = &padapter->coex_info;
++	PBT_MGNT	pBtMgnt = &pcoex_info->BtMgnt;
++	pBtMgnt->ExtConfig.bEnableWifiScanNotify = pcmd[0];
++	RTW_INFO("%s, bEnableWifiScanNotify: %d\n", __func__, pBtMgnt->ExtConfig.bEnableWifiScanNotify);
++
++	/* send complete event to BT */
++	{
++		pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++		pEvent->Data[0] = 0x1;	/* packet # */
++		pEvent->Data[1] = HCIOPCODELOW(HCI_ENABLE_WIFI_SCAN_NOTIFY, OGF_EXTENSION);
++		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_ENABLE_WIFI_SCAN_NOTIFY, OGF_EXTENSION);
++		len = len + 3;
++
++		/* Return parameters starts from here */
++		pRetPar = &pEvent->Data[len];
++		pRetPar[0] = status;		/* status */
++
++		len++;
++		pEvent->Length = len;
++
++		/* total tx event length + EventCode length + sizeof(length) */
++		tx_event_length = pEvent->Length + 2;
++
++		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++		return status;
++		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++	}
++}
++
++u8 rtw_btcoex_parse_HCI_link_status_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
++	struct bt_coex_info	*pcoex_info = &padapter->coex_info;
++	PBT_MGNT	pBtMgnt = &pcoex_info->BtMgnt;
++	/* PBT_DBG		pBtDbg=&padapter->MgntInfo.BtInfo.BtDbg; */
++	u8		i, numOfHandle = 0, numOfAcl = 0;
++	u16		conHandle;
++	u8		btProfile, btCoreSpec, linkRole;
++	u8		*pTriple;
++
++	u8 localBuf[6] = "";
++	u8 *pRetPar;
++	u8	len = 0, tx_event_length = 0;
++	rtw_HCI_event *pEvent;
++
++	/* pBtDbg->dbgHciInfo.hciCmdCntLinkStatusNotify++; */
++	/* RT_DISP_DATA(FIOCTL, IOCTL_BT_HCICMD_EXT, "LinkStatusNotify, Hex Data :\n",  */
++	/*		&pHciCmd->Data[0], pHciCmd->Length); */
++
++	RTW_INFO("BTLinkStatusNotify\n");
++
++	/* Current only RTL8723 support this command. */
++	/* pBtMgnt->bSupportProfile = TRUE; */
++	pBtMgnt->bSupportProfile = _FALSE;
++
++	pBtMgnt->ExtConfig.NumberOfACL = 0;
++	pBtMgnt->ExtConfig.NumberOfSCO = 0;
++
++	numOfHandle = pcmd[0];
++	/* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, ("numOfHandle = 0x%x\n", numOfHandle)); */
++	/* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, ("HCIExtensionVer = %d\n", pBtMgnt->ExtConfig.HCIExtensionVer)); */
++	RTW_INFO("numOfHandle = 0x%x\n", numOfHandle);
++	RTW_INFO("HCIExtensionVer = %d\n", pBtMgnt->ExtConfig.HCIExtensionVer);
++
++	pTriple = &pcmd[1];
++	for (i = 0; i < numOfHandle; i++) {
++		if (pBtMgnt->ExtConfig.HCIExtensionVer < 1) {
++			conHandle = *((u8 *)&pTriple[0]);
++			btProfile = pTriple[2];
++			btCoreSpec = pTriple[3];
++			if (BT_PROFILE_SCO == btProfile)
++				pBtMgnt->ExtConfig.NumberOfSCO++;
++			else {
++				pBtMgnt->ExtConfig.NumberOfACL++;
++				pBtMgnt->ExtConfig.aclLink[i].ConnectHandle = conHandle;
++				pBtMgnt->ExtConfig.aclLink[i].BTProfile = btProfile;
++				pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec = btCoreSpec;
++			}
++			/* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, */
++			/*	("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d\n", */
++			/*		conHandle, btProfile, btCoreSpec)); */
++			RTW_INFO("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d\n", conHandle, btProfile, btCoreSpec);
++			pTriple += 4;
++		} else if (pBtMgnt->ExtConfig.HCIExtensionVer >= 1) {
++			conHandle = *((u16 *)&pTriple[0]);
++			btProfile = pTriple[2];
++			btCoreSpec = pTriple[3];
++			linkRole = pTriple[4];
++			if (BT_PROFILE_SCO == btProfile)
++				pBtMgnt->ExtConfig.NumberOfSCO++;
++			else {
++				pBtMgnt->ExtConfig.NumberOfACL++;
++				pBtMgnt->ExtConfig.aclLink[i].ConnectHandle = conHandle;
++				pBtMgnt->ExtConfig.aclLink[i].BTProfile = btProfile;
++				pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec = btCoreSpec;
++				pBtMgnt->ExtConfig.aclLink[i].linkRole = linkRole;
++			}
++			/* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, */
++			RTW_INFO("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d, LinkRole=%d\n",
++				 conHandle, btProfile, btCoreSpec, linkRole);
++			pTriple += 5;
++		}
++	}
++	rtw_btcoex_StackUpdateProfileInfo();
++
++	/* send complete event to BT */
++	{
++		pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++		pEvent->Data[0] = 0x1;	/* packet # */
++		pEvent->Data[1] = HCIOPCODELOW(HCI_LINK_STATUS_NOTIFY, OGF_EXTENSION);
++		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_LINK_STATUS_NOTIFY, OGF_EXTENSION);
++		len = len + 3;
++
++		/* Return parameters starts from here */
++		pRetPar = &pEvent->Data[len];
++		pRetPar[0] = status;		/* status */
++
++		len++;
++		pEvent->Length = len;
++
++		/* total tx event length + EventCode length + sizeof(length) */
++		tx_event_length = pEvent->Length + 2;
++
++		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++		return status;
++		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++	}
++
++
++}
++
++u8 rtw_btcoex_parse_HCI_BT_coex_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++	u8 localBuf[6] = "";
++	u8 *pRetPar;
++	u8	len = 0, tx_event_length = 0;
++	rtw_HCI_event *pEvent;
++	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
++
++	{
++		pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++		pEvent->Data[0] = 0x1;	/* packet # */
++		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_COEX_NOTIFY, OGF_EXTENSION);
++		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_COEX_NOTIFY, OGF_EXTENSION);
++		len = len + 3;
++
++		/* Return parameters starts from here */
++		pRetPar = &pEvent->Data[len];
++		pRetPar[0] = status;		/* status */
++
++		len++;
++		pEvent->Length = len;
++
++		/* total tx event length + EventCode length + sizeof(length) */
++		tx_event_length = pEvent->Length + 2;
++
++		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++		return status;
++		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++	}
++}
++
++u8 rtw_btcoex_parse_HCI_BT_operation_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++	u8 localBuf[6] = "";
++	u8 *pRetPar;
++	u8	len = 0, tx_event_length = 0;
++	rtw_HCI_event *pEvent;
++	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
++
++	RTW_INFO("%s, OP code: %d\n", __func__, pcmd[0]);
++
++	switch (pcmd[0]) {
++	case HCI_BT_OP_NONE:
++		RTW_INFO("[bt operation] : Operation None!!\n");
++		break;
++	case HCI_BT_OP_INQUIRY_START:
++		RTW_INFO("[bt operation] : Inquiry start!!\n");
++		break;
++	case HCI_BT_OP_INQUIRY_FINISH:
++		RTW_INFO("[bt operation] : Inquiry finished!!\n");
++		break;
++	case HCI_BT_OP_PAGING_START:
++		RTW_INFO("[bt operation] : Paging is started!!\n");
++		break;
++	case HCI_BT_OP_PAGING_SUCCESS:
++		RTW_INFO("[bt operation] : Paging complete successfully!!\n");
++		break;
++	case HCI_BT_OP_PAGING_UNSUCCESS:
++		RTW_INFO("[bt operation] : Paging complete unsuccessfully!!\n");
++		break;
++	case HCI_BT_OP_PAIRING_START:
++		RTW_INFO("[bt operation] : Pairing start!!\n");
++		break;
++	case HCI_BT_OP_PAIRING_FINISH:
++		RTW_INFO("[bt operation] : Pairing finished!!\n");
++		break;
++	case HCI_BT_OP_BT_DEV_ENABLE:
++		RTW_INFO("[bt operation] : BT Device is enabled!!\n");
++		break;
++	case HCI_BT_OP_BT_DEV_DISABLE:
++		RTW_INFO("[bt operation] : BT Device is disabled!!\n");
++		break;
++	default:
++		RTW_INFO("[bt operation] : Unknown, error!!\n");
++		break;
++	}
++
++	/* send complete event to BT */
++	{
++		pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++		pEvent->Data[0] = 0x1;	/* packet # */
++		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_OPERATION_NOTIFY, OGF_EXTENSION);
++		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_OPERATION_NOTIFY, OGF_EXTENSION);
++		len = len + 3;
++
++		/* Return parameters starts from here */
++		pRetPar = &pEvent->Data[len];
++		pRetPar[0] = status;		/* status */
++
++		len++;
++		pEvent->Length = len;
++
++		/* total tx event length + EventCode length + sizeof(length) */
++		tx_event_length = pEvent->Length + 2;
++
++		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++		return status;
++		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++	}
++}
++
++u8 rtw_btcoex_parse_BT_AFH_MAP_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++	u8 localBuf[6] = "";
++	u8 *pRetPar;
++	u8	len = 0, tx_event_length = 0;
++	rtw_HCI_event *pEvent;
++	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
++
++	{
++		pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++		pEvent->Data[0] = 0x1;	/* packet # */
++		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_AFH_MAP_NOTIFY, OGF_EXTENSION);
++		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_AFH_MAP_NOTIFY, OGF_EXTENSION);
++		len = len + 3;
++
++		/* Return parameters starts from here */
++		pRetPar = &pEvent->Data[len];
++		pRetPar[0] = status;		/* status */
++
++		len++;
++		pEvent->Length = len;
++
++		/* total tx event length + EventCode length + sizeof(length) */
++		tx_event_length = pEvent->Length + 2;
++
++		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++		return status;
++		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++	}
++}
++
++u8 rtw_btcoex_parse_BT_register_val_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++
++	u8 localBuf[6] = "";
++	u8 *pRetPar;
++	u8	len = 0, tx_event_length = 0;
++	rtw_HCI_event *pEvent;
++	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
++
++	{
++		pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++		pEvent->Data[0] = 0x1;	/* packet # */
++		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_REGISTER_VALUE_NOTIFY, OGF_EXTENSION);
++		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_REGISTER_VALUE_NOTIFY, OGF_EXTENSION);
++		len = len + 3;
++
++		/* Return parameters starts from here */
++		pRetPar = &pEvent->Data[len];
++		pRetPar[0] = status;		/* status */
++
++		len++;
++		pEvent->Length = len;
++
++		/* total tx event length + EventCode length + sizeof(length) */
++		tx_event_length = pEvent->Length + 2;
++
++		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++		return status;
++		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++	}
++}
++
++u8 rtw_btcoex_parse_HCI_BT_abnormal_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++	u8 localBuf[6] = "";
++	u8 *pRetPar;
++	u8	len = 0, tx_event_length = 0;
++	rtw_HCI_event *pEvent;
++	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
++
++	{
++		pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++		pEvent->Data[0] = 0x1;	/* packet # */
++		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_ABNORMAL_NOTIFY, OGF_EXTENSION);
++		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_ABNORMAL_NOTIFY, OGF_EXTENSION);
++		len = len + 3;
++
++		/* Return parameters starts from here */
++		pRetPar = &pEvent->Data[len];
++		pRetPar[0] = status;		/* status */
++
++		len++;
++		pEvent->Length = len;
++
++		/* total tx event length + EventCode length + sizeof(length) */
++		tx_event_length = pEvent->Length + 2;
++
++		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++		return status;
++		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++	}
++}
++
++u8 rtw_btcoex_parse_HCI_query_RF_status_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++	u8 localBuf[6] = "";
++	u8 *pRetPar;
++	u8	len = 0, tx_event_length = 0;
++	rtw_HCI_event *pEvent;
++	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
++
++	{
++		pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++		pEvent->Data[0] = 0x1;	/* packet # */
++		pEvent->Data[1] = HCIOPCODELOW(HCI_QUERY_RF_STATUS, OGF_EXTENSION);
++		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_QUERY_RF_STATUS, OGF_EXTENSION);
++		len = len + 3;
++
++		/* Return parameters starts from here */
++		pRetPar = &pEvent->Data[len];
++		pRetPar[0] = status;		/* status */
++
++		len++;
++		pEvent->Length = len;
++
++		/* total tx event length + EventCode length + sizeof(length) */
++		tx_event_length = pEvent->Length + 2;
++
++		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++		return status;
++		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++	}
++}
++
++/*****************************************
++* HCI cmd format :
++*| 15 - 0						|
++*| OPcode (OCF|OGF<<10)		|
++*| 15 - 8		|7 - 0			|
++*|Cmd para	|Cmd para Length	|
++*|Cmd para......				|
++******************************************/
++
++/* bit 0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
++ *	 |	OCF			             |	   OGF       | */
++void rtw_btcoex_parse_hci_extend_cmd(_adapter *padapter, u8 *pcmd, u16 len, const u16 hci_OCF)
++{
++
++	RTW_INFO("%s: OCF: %x\n", __func__, hci_OCF);
++	switch (hci_OCF) {
++	case HCI_EXTENSION_VERSION_NOTIFY:
++		RTW_INFO("HCI_EXTENSION_VERSION_NOTIFY\n");
++		rtw_btcoex_parse_HCI_Ver_notify_cmd(padapter, pcmd, len);
++		break;
++	case HCI_LINK_STATUS_NOTIFY:
++		RTW_INFO("HCI_LINK_STATUS_NOTIFY\n");
++		rtw_btcoex_parse_HCI_link_status_notify_cmd(padapter, pcmd, len);
++		break;
++	case HCI_BT_OPERATION_NOTIFY:
++		/* only for 8723a 2ant */
++		RTW_INFO("HCI_BT_OPERATION_NOTIFY\n");
++		rtw_btcoex_parse_HCI_BT_operation_notify_cmd(padapter, pcmd, len);
++		/*  */
++		break;
++	case HCI_ENABLE_WIFI_SCAN_NOTIFY:
++		RTW_INFO("HCI_ENABLE_WIFI_SCAN_NOTIFY\n");
++		rtw_btcoex_parse_WIFI_scan_notify_cmd(padapter, pcmd, len);
++		break;
++	case HCI_QUERY_RF_STATUS:
++		/* only for 8723b 2ant */
++		RTW_INFO("HCI_QUERY_RF_STATUS\n");
++		rtw_btcoex_parse_HCI_query_RF_status_cmd(padapter, pcmd, len);
++		break;
++	case HCI_BT_ABNORMAL_NOTIFY:
++		RTW_INFO("HCI_BT_ABNORMAL_NOTIFY\n");
++		rtw_btcoex_parse_HCI_BT_abnormal_notify_cmd(padapter, pcmd, len);
++		break;
++	case HCI_BT_INFO_NOTIFY:
++		RTW_INFO("HCI_BT_INFO_NOTIFY\n");
++		rtw_btcoex_parse_BT_info_notify_cmd(padapter, pcmd, len);
++		break;
++	case HCI_BT_COEX_NOTIFY:
++		RTW_INFO("HCI_BT_COEX_NOTIFY\n");
++		rtw_btcoex_parse_HCI_BT_coex_notify_cmd(padapter, pcmd, len);
++		break;
++	case HCI_BT_PATCH_VERSION_NOTIFY:
++		RTW_INFO("HCI_BT_PATCH_VERSION_NOTIFY\n");
++		rtw_btcoex_parse_BT_patch_ver_info_cmd(padapter, pcmd, len);
++		break;
++	case HCI_BT_AFH_MAP_NOTIFY:
++		RTW_INFO("HCI_BT_AFH_MAP_NOTIFY\n");
++		rtw_btcoex_parse_BT_AFH_MAP_notify_cmd(padapter, pcmd, len);
++		break;
++	case HCI_BT_REGISTER_VALUE_NOTIFY:
++		RTW_INFO("HCI_BT_REGISTER_VALUE_NOTIFY\n");
++		rtw_btcoex_parse_BT_register_val_notify_cmd(padapter, pcmd, len);
++		break;
++	default:
++		RTW_INFO("ERROR!!! Unknown OCF: %x\n", hci_OCF);
++		break;
++
++	}
++}
++
++void rtw_btcoex_parse_hci_cmd(_adapter *padapter, u8 *pcmd, u16 len)
++{
++	u16 opcode = pcmd[0] | pcmd[1] << 8;
++	u16 hci_OGF = HCI_OGF(opcode);
++	u16 hci_OCF = HCI_OCF(opcode);
++	u8 cmdlen = len - 3;
++	u8 pare_len = pcmd[2];
++
++	RTW_INFO("%s OGF: %x,OCF: %x\n", __func__, hci_OGF, hci_OCF);
++	switch (hci_OGF) {
++	case OGF_EXTENSION:
++		RTW_INFO("HCI_EXTENSION_CMD_OGF\n");
++		rtw_btcoex_parse_hci_extend_cmd(padapter, &pcmd[3], cmdlen, hci_OCF);
++		break;
++	default:
++		RTW_INFO("Other OGF: %x\n", hci_OGF);
++		break;
++	}
++}
++
++u16 rtw_btcoex_parse_recv_data(u8 *msg, u8 msg_size)
++{
++	u8 cmp_msg1[32] = attend_ack;
++	u8 cmp_msg2[32] = leave_ack;
++	u8 cmp_msg3[32] = bt_leave;
++	u8 cmp_msg4[32] = invite_req;
++	u8 cmp_msg5[32] = attend_req;
++	u8 cmp_msg6[32] = invite_rsp;
++	u8 res = OTHER;
++
++	if (_rtw_memcmp(cmp_msg1, msg, msg_size) == _TRUE) {
++		/*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
++		res = RX_ATTEND_ACK;
++	} else if (_rtw_memcmp(cmp_msg2, msg, msg_size) == _TRUE) {
++		/*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
++		res = RX_LEAVE_ACK;
++	} else if (_rtw_memcmp(cmp_msg3, msg, msg_size) == _TRUE) {
++		/*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
++		res = RX_BT_LEAVE;
++	} else if (_rtw_memcmp(cmp_msg4, msg, msg_size) == _TRUE) {
++		/*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
++		res = RX_INVITE_REQ;
++	} else if (_rtw_memcmp(cmp_msg5, msg, msg_size) == _TRUE)
++		res = RX_ATTEND_REQ;
++	else if (_rtw_memcmp(cmp_msg6, msg, msg_size) == _TRUE)
++		res = RX_INVITE_RSP;
++	else {
++		/*RTW_INFO("%s, %s\n", __func__, msg);*/
++		res = OTHER;
++	}
++
++	/*RTW_INFO("%s, res:%d\n", __func__, res);*/
++
++	return res;
++}
++
++void rtw_btcoex_recvmsgbysocket(void *data)
++{
++	u8 recv_data[255];
++	u8 tx_msg[255] = leave_ack;
++	u32 len = 0;
++	u16 recv_length = 0;
++	u16 parse_res = 0;
++#if 0
++	u8 para_len = 0, polling_enable = 0, poling_interval = 0, reason = 0, btinfo_len = 0;
++	u8 btinfo[BT_INFO_LEN] = {0};
++#endif
++
++	struct bt_coex_info *pcoex_info = NULL;
++	struct sock *sk = NULL;
++	struct sk_buff *skb = NULL;
++
++	/*RTW_INFO("%s\n",__func__);*/
++
++	if (pbtcoexadapter == NULL) {
++		RTW_INFO("%s: btcoexadapter NULL!\n", __func__);
++		return;
++	}
++
++	pcoex_info = &pbtcoexadapter->coex_info;
++	sk = pcoex_info->sk_store;
++
++	if (sk == NULL) {
++		RTW_INFO("%s: critical error when receive socket data!\n", __func__);
++		return;
++	}
++
++	len = skb_queue_len(&sk->sk_receive_queue);
++	while (len > 0) {
++		skb = skb_dequeue(&sk->sk_receive_queue);
++
++		/*important: cut the udp header from skb->data! header length is 8 byte*/
++		recv_length = skb->len - 8;
++		_rtw_memset(recv_data, 0, sizeof(recv_data));
++		_rtw_memcpy(recv_data, skb->data + 8, recv_length);
++
++		parse_res = rtw_btcoex_parse_recv_data(recv_data, recv_length);
++#if 0
++		if (RX_ATTEND_ACK == parse_res) {
++			/* attend ack */
++			pcoex_info->BT_attend = _TRUE;
++			RTW_INFO("RX_ATTEND_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++		} else if (RX_ATTEND_REQ == parse_res) {
++			/* attend req from BT */
++			pcoex_info->BT_attend = _TRUE;
++			RTW_INFO("RX_BT_ATTEND_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, attend_ack, sizeof(attend_ack), _FALSE);
++		} else if (RX_INVITE_REQ == parse_res) {
++			/* invite req from BT */
++			pcoex_info->BT_attend = _TRUE;
++			RTW_INFO("RX_INVITE_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, invite_rsp, sizeof(invite_rsp), _FALSE);
++		} else if (RX_INVITE_RSP == parse_res) {
++			/* invite rsp */
++			pcoex_info->BT_attend = _TRUE;
++			RTW_INFO("RX_INVITE_RSP!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++		} else if (RX_LEAVE_ACK == parse_res) {
++			/* mean BT know wifi  will leave */
++			pcoex_info->BT_attend = _FALSE;
++			RTW_INFO("RX_LEAVE_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++		} else if (RX_BT_LEAVE == parse_res) {
++			/* BT leave */
++			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, leave_ack, sizeof(leave_ack), _FALSE); /*  no ack */
++			pcoex_info->BT_attend = _FALSE;
++			RTW_INFO("RX_BT_LEAVE!sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++		} else {
++			/* todo: check if recv data are really hci cmds */
++			if (_TRUE == pcoex_info->BT_attend)
++				rtw_btcoex_parse_hci_cmd(pbtcoexadapter, recv_data, recv_length);
++		}
++#endif
++		switch (parse_res) {
++		case RX_ATTEND_ACK:
++			/* attend ack */
++			pcoex_info->BT_attend = _TRUE;
++			RTW_INFO("RX_ATTEND_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
++			break;
++
++		case RX_ATTEND_REQ:
++			pcoex_info->BT_attend = _TRUE;
++			RTW_INFO("RX_BT_ATTEND_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, attend_ack, sizeof(attend_ack), _FALSE);
++			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
++			break;
++
++		case RX_INVITE_REQ:
++			/* invite req from BT */
++			pcoex_info->BT_attend = _TRUE;
++			RTW_INFO("RX_INVITE_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, invite_rsp, sizeof(invite_rsp), _FALSE);
++			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
++			break;
++
++		case RX_INVITE_RSP:
++			/*invite rsp*/
++			pcoex_info->BT_attend = _TRUE;
++			RTW_INFO("RX_INVITE_RSP!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
++			break;
++
++		case RX_LEAVE_ACK:
++			/* mean BT know wifi  will leave */
++			pcoex_info->BT_attend = _FALSE;
++			RTW_INFO("RX_LEAVE_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
++			break;
++
++		case RX_BT_LEAVE:
++			/* BT leave */
++			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, leave_ack, sizeof(leave_ack), _FALSE); /* no ack */
++			pcoex_info->BT_attend = _FALSE;
++			RTW_INFO("RX_BT_LEAVE!sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
++			break;
++
++		default:
++			if (_TRUE == pcoex_info->BT_attend)
++				rtw_btcoex_parse_hci_cmd(pbtcoexadapter, recv_data, recv_length);
++			else
++				RTW_INFO("ERROR!! BT is UP\n");
++			break;
++
++		}
++
++		len--;
++		kfree_skb(skb);
++	}
++}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0))
++	void rtw_btcoex_recvmsg_init(struct sock *sk_in, s32 bytes)
++#else
++	void rtw_btcoex_recvmsg_init(struct sock *sk_in)
++#endif
++{
++	struct bt_coex_info *pcoex_info = NULL;
++
++	if (pbtcoexadapter == NULL) {
++		RTW_INFO("%s: btcoexadapter NULL\n", __func__);
++		return;
++	}
++	pcoex_info = &pbtcoexadapter->coex_info;
++	pcoex_info->sk_store = sk_in;
++	if (pcoex_info->btcoex_wq != NULL)
++		queue_delayed_work(pcoex_info->btcoex_wq, &pcoex_info->recvmsg_work, 0);
++	else
++		RTW_INFO("%s: BTCOEX workqueue NULL\n", __func__);
++}
++
++u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool force)
++{
++	u8 error;
++	struct msghdr	udpmsg;
++	mm_segment_t	oldfs;
++	struct iovec	iov;
++	struct bt_coex_info *pcoex_info = &padapter->coex_info;
++
++	/* RTW_INFO("%s: msg:%s, force:%s\n", __func__, msg, force == _TRUE?"TRUE":"FALSE"); */
++	if (_FALSE == force) {
++		if (_FALSE == pcoex_info->BT_attend) {
++			RTW_INFO("TX Blocked: WiFi-BT disconnected\n");
++			return _FAIL;
++		}
++	}
++
++	iov.iov_base	 = (void *)msg;
++	iov.iov_len	 = msg_size;
++	udpmsg.msg_name	 = &pcoex_info->bt_sockaddr;
++	udpmsg.msg_namelen	= sizeof(struct sockaddr_in);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++	/* referece:sock_xmit in kernel code
++	 * WRITE for sock_sendmsg, READ for sock_recvmsg
++	 * third parameter for msg_iovlen
++	 * last parameter for iov_len
++	 */
++	iov_iter_init(&udpmsg.msg_iter, WRITE, &iov, 1, msg_size);
++#else
++	udpmsg.msg_iov	 = &iov;
++	udpmsg.msg_iovlen	= 1;
++#endif
++	udpmsg.msg_control	= NULL;
++	udpmsg.msg_controllen = 0;
++	udpmsg.msg_flags	= MSG_DONTWAIT | MSG_NOSIGNAL;
++	oldfs = get_fs();
++	set_fs(KERNEL_DS);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
++	error = sock_sendmsg(pcoex_info->udpsock, &udpmsg);
++#else
++	error = sock_sendmsg(pcoex_info->udpsock, &udpmsg, msg_size);
++#endif
++	set_fs(oldfs);
++	if (error < 0) {
++		RTW_INFO("Error when sendimg msg, error:%d\n", error);
++		return _FAIL;
++	} else
++		return _SUCCESS;
++}
++
++u8 rtw_btcoex_create_kernel_socket(_adapter *padapter)
++{
++	s8 kernel_socket_err;
++	u8 tx_msg[255] = attend_req;
++	struct bt_coex_info *pcoex_info = &padapter->coex_info;
++	s32 sock_reuse = 1;
++	u8 status = _FAIL;
++
++	RTW_INFO("%s CONNECT_PORT %d\n", __func__, CONNECT_PORT);
++
++	if (NULL == pcoex_info) {
++		RTW_INFO("coex_info: NULL\n");
++		status =  _FAIL;
++	}
++
++	kernel_socket_err = sock_create(PF_INET, SOCK_DGRAM, 0, &pcoex_info->udpsock);
++
++	if (kernel_socket_err < 0) {
++		RTW_INFO("Error during creation of socket error:%d\n", kernel_socket_err);
++		status = _FAIL;
++	} else {
++		_rtw_memset(&(pcoex_info->wifi_sockaddr), 0, sizeof(pcoex_info->wifi_sockaddr));
++		pcoex_info->wifi_sockaddr.sin_family = AF_INET;
++		pcoex_info->wifi_sockaddr.sin_port = htons(CONNECT_PORT);
++		pcoex_info->wifi_sockaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);
++
++		_rtw_memset(&(pcoex_info->bt_sockaddr), 0, sizeof(pcoex_info->bt_sockaddr));
++		pcoex_info->bt_sockaddr.sin_family = AF_INET;
++		pcoex_info->bt_sockaddr.sin_port = htons(CONNECT_PORT_BT);
++		pcoex_info->bt_sockaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);
++
++		pcoex_info->sk_store = NULL;
++		kernel_socket_err = pcoex_info->udpsock->ops->bind(pcoex_info->udpsock, (struct sockaddr *)&pcoex_info->wifi_sockaddr,
++				    sizeof(pcoex_info->wifi_sockaddr));
++		if (kernel_socket_err == 0) {
++			RTW_INFO("binding socket success\n");
++			pcoex_info->udpsock->sk->sk_data_ready = rtw_btcoex_recvmsg_init;
++			pcoex_info->sock_open |=  KERNEL_SOCKET_OK;
++			pcoex_info->BT_attend = _FALSE;
++			RTW_INFO("WIFI sending attend_req\n");
++			rtw_btcoex_sendmsgbysocket(padapter, attend_req, sizeof(attend_req), _TRUE);
++			status = _SUCCESS;
++		} else {
++			pcoex_info->BT_attend = _FALSE;
++			sock_release(pcoex_info->udpsock); /* bind fail release socket */
++			RTW_INFO("Error binding socket: %d\n", kernel_socket_err);
++			status = _FAIL;
++		}
++
++	}
++
++	return status;
++}
++
++void rtw_btcoex_close_kernel_socket(_adapter *padapter)
++{
++	struct bt_coex_info *pcoex_info = &padapter->coex_info;
++	if (pcoex_info->sock_open & KERNEL_SOCKET_OK) {
++		RTW_INFO("release kernel socket\n");
++		sock_release(pcoex_info->udpsock);
++		pcoex_info->sock_open &= ~(KERNEL_SOCKET_OK);
++		if (_TRUE == pcoex_info->BT_attend)
++			pcoex_info->BT_attend = _FALSE;
++
++		RTW_INFO("sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++	}
++}
++
++void rtw_btcoex_init_socket(_adapter *padapter)
++{
++
++	u8 is_invite = _FALSE;
++	struct bt_coex_info *pcoex_info = &padapter->coex_info;
++	RTW_INFO("%s\n", __func__);
++	if (_FALSE == pcoex_info->is_exist) {
++		_rtw_memset(pcoex_info, 0, sizeof(struct bt_coex_info));
++		pcoex_info->btcoex_wq = create_workqueue("BTCOEX");
++		INIT_DELAYED_WORK(&pcoex_info->recvmsg_work,
++				  (void *)rtw_btcoex_recvmsgbysocket);
++		pbtcoexadapter = padapter;
++		/* We expect BT is off if BT don't send ack to wifi */
++		RTW_INFO("We expect BT is off if BT send ack to wifi\n");
++		rtw_btcoex_pta_off_on_notify(pbtcoexadapter, _FALSE);
++		if (rtw_btcoex_create_kernel_socket(padapter) == _SUCCESS)
++			pcoex_info->is_exist = _TRUE;
++		else {
++			pcoex_info->is_exist = _FALSE;
++			pbtcoexadapter = NULL;
++		}
++
++		RTW_INFO("%s: pbtcoexadapter:%p, coex_info->is_exist: %s\n"
++			, __func__, pbtcoexadapter, pcoex_info->is_exist == _TRUE ? "TRUE" : "FALSE");
++	}
++}
++
++void rtw_btcoex_close_socket(_adapter *padapter)
++{
++	struct bt_coex_info *pcoex_info = &padapter->coex_info;
++
++	RTW_INFO("%s--coex_info->is_exist: %s, pcoex_info->BT_attend:%s\n"
++		, __func__, pcoex_info->is_exist == _TRUE ? "TRUE" : "FALSE", pcoex_info->BT_attend == _TRUE ? "TRUE" : "FALSE");
++
++	if (_TRUE == pcoex_info->is_exist) {
++		if (_TRUE == pcoex_info->BT_attend) {
++			/*inform BT wifi leave*/
++			rtw_btcoex_sendmsgbysocket(padapter, wifi_leave, sizeof(wifi_leave), _FALSE);
++			msleep(50);
++		}
++
++		if (pcoex_info->btcoex_wq != NULL) {
++			flush_workqueue(pcoex_info->btcoex_wq);
++			destroy_workqueue(pcoex_info->btcoex_wq);
++		}
++
++		rtw_btcoex_close_kernel_socket(padapter);
++		pbtcoexadapter = NULL;
++		pcoex_info->is_exist = _FALSE;
++	}
++}
++
++void rtw_btcoex_dump_tx_msg(u8 *tx_msg, u8 len, u8 *msg_name)
++{
++	u8	i = 0;
++	RTW_INFO("======> Msg name: %s\n", msg_name);
++	for (i = 0; i < len; i++)
++		printk("%02x ", tx_msg[i]);
++	printk("\n");
++	RTW_INFO("Msg name: %s <======\n", msg_name);
++}
++
++/* Porting from Windows team */
++void rtw_btcoex_SendEventExtBtCoexControl(PADAPTER padapter, u8 bNeedDbgRsp, u8 dataLen, void *pData)
++{
++	u8			len = 0, tx_event_length = 0;
++	u8 			localBuf[32] = "";
++	u8			*pRetPar;
++	u8			opCode = 0;
++	u8			*pInBuf = (u8 *)pData;
++	u8			*pOpCodeContent;
++	rtw_HCI_event *pEvent;
++
++	opCode = pInBuf[0];
++
++	RTW_INFO("%s, OPCode:%02x\n", __func__, opCode);
++
++	pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++	/* len += bthci_ExtensionEventHeaderRtk(&localBuf[0], */
++	/*	HCI_EVENT_EXT_BT_COEX_CONTROL); */
++	pEvent->EventCode = HCI_EVENT_EXTENSION_RTK;
++	pEvent->Data[0] = HCI_EVENT_EXT_BT_COEX_CONTROL;	/* extension event code */
++	len++;
++
++	/* Return parameters starts from here */
++	pRetPar = &pEvent->Data[len];
++	_rtw_memcpy(&pRetPar[0], pData, dataLen);
++
++	len += dataLen;
++
++	pEvent->Length = len;
++
++	/* total tx event length + EventCode length + sizeof(length) */
++	tx_event_length = pEvent->Length + 2;
++#if 0
++	rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT COEX CONTROL", _FALSE);
++#endif
++	rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++
++}
++
++/* Porting from Windows team */
++void rtw_btcoex_SendEventExtBtInfoControl(PADAPTER padapter, u8 dataLen, void *pData)
++{
++	rtw_HCI_event *pEvent;
++	u8			*pRetPar;
++	u8			len = 0, tx_event_length = 0;
++	u8 			localBuf[32] = "";
++
++	struct bt_coex_info *pcoex_info = &padapter->coex_info;
++	PBT_MGNT		pBtMgnt = &pcoex_info->BtMgnt;
++
++	/* RTW_INFO("%s\n",__func__);*/
++	if (pBtMgnt->ExtConfig.HCIExtensionVer < 4) { /* not support */
++		RTW_INFO("ERROR: HCIExtensionVer = %d, HCIExtensionVer<4 !!!!\n", pBtMgnt->ExtConfig.HCIExtensionVer);
++		return;
++	}
++
++	pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++	/* len += bthci_ExtensionEventHeaderRtk(&localBuf[0], */
++	/*		HCI_EVENT_EXT_BT_INFO_CONTROL); */
++	pEvent->EventCode = HCI_EVENT_EXTENSION_RTK;
++	pEvent->Data[0] = HCI_EVENT_EXT_BT_INFO_CONTROL;		/* extension event code */
++	len++;
++
++	/* Return parameters starts from here */
++	pRetPar = &pEvent->Data[len];
++	_rtw_memcpy(&pRetPar[0], pData, dataLen);
++
++	len += dataLen;
++
++	pEvent->Length = len;
++
++	/* total tx event length + EventCode length + sizeof(length) */
++	tx_event_length = pEvent->Length + 2;
++#if 0
++	rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT INFO CONTROL");
++#endif
++	rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++
++}
++
++void rtw_btcoex_SendScanNotify(PADAPTER padapter, u8 scanType)
++{
++	u8	len = 0, tx_event_length = 0;
++	u8 	localBuf[7] = "";
++	u8	*pRetPar;
++	u8	*pu1Temp;
++	rtw_HCI_event *pEvent;
++	struct bt_coex_info *pcoex_info = &padapter->coex_info;
++	PBT_MGNT		pBtMgnt = &pcoex_info->BtMgnt;
++
++	/*	if(!pBtMgnt->BtOperationOn)
++	 *		return; */
++
++	pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++	/*	len += bthci_ExtensionEventHeaderRtk(&localBuf[0],
++	 *			HCI_EVENT_EXT_WIFI_SCAN_NOTIFY); */
++
++	pEvent->EventCode = HCI_EVENT_EXTENSION_RTK;
++	pEvent->Data[0] = HCI_EVENT_EXT_WIFI_SCAN_NOTIFY;		/* extension event code */
++	len++;
++
++	/* Return parameters starts from here */
++	/* pRetPar = &PPacketIrpEvent->Data[len]; */
++	/* pu1Temp = (u8 *)&pRetPar[0]; */
++	/* *pu1Temp = scanType; */
++	pEvent->Data[len] = scanType;
++	len += 1;
++
++	pEvent->Length = len;
++
++	/* total tx event length + EventCode length + sizeof(length) */
++	tx_event_length = pEvent->Length + 2;
++#if 0
++	rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "WIFI SCAN OPERATION");
++#endif
++	rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++}
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++#endif /* CONFIG_BT_COEXIST */
++
++void rtw_btcoex_set_ant_info(PADAPTER padapter)
++{
++#ifdef CONFIG_BT_COEXIST
++	PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
++
++	if (hal->EEPROMBluetoothCoexist == _TRUE) {
++		u8 bMacPwrCtrlOn = _FALSE;
++
++		rtw_btcoex_AntInfoSetting(padapter);
++		rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++		if (bMacPwrCtrlOn == _TRUE)
++			rtw_btcoex_PowerOnSetting(padapter);
++	}
++	else
++#endif
++		rtw_btcoex_wifionly_AntInfoSetting(padapter);
++}
++
++void rtw_btcoex_connect_notify(PADAPTER padapter, u8 join_type)
++{
++#ifdef CONFIG_BT_COEXIST
++	PHAL_DATA_TYPE	pHalData;
++
++	pHalData = GET_HAL_DATA(padapter);
++
++	if (pHalData->EEPROMBluetoothCoexist == _TRUE)
++		_rtw_btcoex_connect_notify(padapter, join_type ? _FALSE : _TRUE);
++	else
++#endif /* CONFIG_BT_COEXIST */
++	rtw_btcoex_wifionly_connect_notify(padapter);
++}
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_btcoex_wifionly.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_btcoex_wifionly.c
+new file mode 100644
+index 000000000..d9872b022
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_btcoex_wifionly.c
+@@ -0,0 +1,47 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#include <drv_types.h>
++#include <hal_btcoex_wifionly.h>
++#include <hal_data.h>
++
++void rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter)
++{
++	hal_btcoex_wifionly_switchband_notify(padapter);
++}
++
++void rtw_btcoex_wifionly_scan_notify(PADAPTER padapter)
++{
++	hal_btcoex_wifionly_scan_notify(padapter);
++}
++
++void rtw_btcoex_wifionly_connect_notify(PADAPTER padapter)
++{
++	hal_btcoex_wifionly_connect_notify(padapter);
++}
++
++void rtw_btcoex_wifionly_hw_config(PADAPTER padapter)
++{
++	hal_btcoex_wifionly_hw_config(padapter);
++}
++
++void rtw_btcoex_wifionly_initialize(PADAPTER padapter)
++{
++	hal_btcoex_wifionly_initlizevariables(padapter);
++}
++
++void rtw_btcoex_wifionly_AntInfoSetting(PADAPTER padapter)
++{
++	hal_btcoex_wifionly_AntInfoSetting(padapter);
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_chplan.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_chplan.c
+new file mode 100644
+index 000000000..86169568e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_chplan.c
+@@ -0,0 +1,1241 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2018 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_CHPLAN_C_
++
++#include <drv_types.h>
++
++#define RTW_DOMAIN_MAP_VER		"46"
++#define RTW_DOMAIN_MAP_M_VER	"f"
++#define RTW_COUNTRY_MAP_VER		"25"
++
++enum rtw_rd_2g {
++	RTW_RD_2G_WORLD = 0,	/* Worldwide 13 */
++	RTW_RD_2G_ETSI1 = 1,	/* Europe */
++	RTW_RD_2G_FCC1 = 2,		/* US */
++	RTW_RD_2G_MKK1 = 3,		/* Japan */
++	RTW_RD_2G_ETSI2 = 4,	/* France */
++	RTW_RD_2G_GLOBAL = 5,	/* 2G Global (include Ch14) */
++	RTW_RD_2G_MKK2 = 6,		/* Japan */
++	RTW_RD_2G_FCC2 = 7,		/* US */
++	RTW_RD_2G_NULL = 8,
++	RTW_RD_2G_IC1 = 9,		/* Canada */
++	RTW_RD_2G_WORLD1 = 10,	/* Worldwide 11 */
++	RTW_RD_2G_KCC1 = 11,	/* Korea */
++	RTW_RD_2G_IC2 = 12,		/* Canada */
++
++	RTW_RD_2G_MAX,
++};
++
++enum rtw_rd_5g {
++	RTW_RD_5G_NULL = 0,		/*	*/
++	RTW_RD_5G_ETSI1 = 1,	/* Europe */
++	RTW_RD_5G_ETSI2 = 2,	/* Australia, New Zealand */
++	RTW_RD_5G_ETSI3 = 3,	/* Russia */
++	RTW_RD_5G_FCC1 = 4,		/* US */
++	RTW_RD_5G_FCC2 = 5,		/* FCC w/o DFS Channels */
++	RTW_RD_5G_FCC3 = 6,		/* Bolivia, Chile, El Salvador, Venezuela */
++	RTW_RD_5G_FCC4 = 7,		/* Venezuela */
++	RTW_RD_5G_FCC5 = 8,		/* China */
++	RTW_RD_5G_FCC6 = 9,		/*	*/
++	RTW_RD_5G_FCC7 = 10,	/* US(w/o Weather radar) */
++	RTW_RD_5G_IC1 = 11,		/* Canada(w/o Weather radar) */
++	RTW_RD_5G_KCC1 = 12,	/* Korea */
++	RTW_RD_5G_MKK1 = 13,	/* Japan */
++	RTW_RD_5G_MKK2 = 14,	/* Japan (W52, W53) */
++	RTW_RD_5G_MKK3 = 15,	/* Japan (W56) */
++	RTW_RD_5G_NCC1 = 16,	/* Taiwan, (w/o Weather radar) */
++	RTW_RD_5G_NCC2 = 17,	/* Taiwan, Band2, Band4 */
++	RTW_RD_5G_NCC3 = 18,	/* Taiwan w/o DFS, Band4 only */
++	RTW_RD_5G_ETSI4 = 19,	/* Europe w/o DFS, Band1 only */
++	RTW_RD_5G_ETSI5 = 20,	/* Australia, New Zealand(w/o Weather radar) */
++	RTW_RD_5G_FCC8 = 21,	/* Latin America */
++	RTW_RD_5G_ETSI6 = 22,	/* Israel, Bahrain, Egypt, India, China, Malaysia */
++	RTW_RD_5G_ETSI7 = 23,	/* China */
++	RTW_RD_5G_ETSI8 = 24,	/* Jordan */
++	RTW_RD_5G_ETSI9 = 25,	/* Lebanon */
++	RTW_RD_5G_ETSI10 = 26,	/* Qatar */
++	RTW_RD_5G_ETSI11 = 27,	/* Russia */
++	RTW_RD_5G_NCC4 = 28,	/* Taiwan, (w/o Weather radar) */
++	RTW_RD_5G_ETSI12 = 29,	/* Indonesia */
++	RTW_RD_5G_FCC9 = 30,	/* (w/o Weather radar) */
++	RTW_RD_5G_ETSI13 = 31,	/* (w/o Weather radar) */
++	RTW_RD_5G_FCC10 = 32,	/* Argentina(w/o Weather radar) */
++	RTW_RD_5G_MKK4 = 33,	/* Japan (W52) */
++	RTW_RD_5G_ETSI14 = 34,	/* Russia */
++	RTW_RD_5G_FCC11 = 35,	/* US(include CH144) */
++	RTW_RD_5G_ETSI15 = 36,	/* Malaysia */
++	RTW_RD_5G_MKK5 = 37,	/* Japan */
++	RTW_RD_5G_ETSI16 = 38,	/* Europe */
++	RTW_RD_5G_ETSI17 = 39,	/* Europe */
++	RTW_RD_5G_FCC12 = 40,	/* FCC */
++	RTW_RD_5G_FCC13 = 41,	/* FCC */
++	RTW_RD_5G_FCC14 = 42,	/* FCC w/o Weather radar(w/o 5600~5650MHz) */
++	RTW_RD_5G_FCC15 = 43,	/* FCC w/o Band3 */
++	RTW_RD_5G_FCC16 = 44,	/* FCC w/o Band3 */
++	RTW_RD_5G_ETSI18 = 45,	/* ETSI w/o DFS Band2&3 */
++	RTW_RD_5G_ETSI19 = 46,	/* Europe */
++	RTW_RD_5G_FCC17 = 47,	/* FCC w/o Weather radar(w/o 5600~5650MHz) */
++	RTW_RD_5G_ETSI20 = 48,	/* Europe */
++	RTW_RD_5G_IC2 = 49,		/* Canada(w/o Weather radar), include ch144 */
++	RTW_RD_5G_ETSI21 = 50,	/* Australia, New Zealand(w/o Weather radar) */
++	RTW_RD_5G_FCC18 = 51,	/*  */
++	RTW_RD_5G_WORLD = 52,	/* Worldwide */
++	RTW_RD_5G_CHILE1 = 53,	/* Chile */
++	RTW_RD_5G_ACMA1 = 54,	/* Australia, New Zealand (w/o Weather radar) (w/o Ch120~Ch128) */
++	RTW_RD_5G_WORLD1 = 55,	/* 5G Worldwide Band1&2 */
++	RTW_RD_5G_CHILE2 = 56,	/* Chile (Band2,Band3) */
++	RTW_RD_5G_KCC2 = 57,	/* Korea (New standard) */
++	RTW_RD_5G_KCC3 = 58,	/* Korea (2018 Dec 05 New standard, include ch144) */
++	RTW_RD_5G_MKK6 = 59,	/* Japan */
++	RTW_RD_5G_MKK7 = 60,	/* Japan */
++	RTW_RD_5G_MKK8 = 61,	/* Japan */
++	RTW_RD_5G_MEX1 = 62,	/* Mexico */
++	RTW_RD_5G_ETSI22 = 63,	/* Europe */
++	RTW_RD_5G_MKK9 = 64,	/* Japan */
++	RTW_RD_5G_FCC19 = 65,	/* FCC */
++	RTW_RD_5G_FCC20 = 66,	/* FCC w/o Band3 */
++	RTW_RD_5G_FCC21 = 67,	/* FCC */
++	RTW_RD_5G_ETSI23 = 68,	/* Indonesia */
++	RTW_RD_5G_ETSI24 = 69,	/* Indonesia */
++	RTW_RD_5G_ETSI25 = 70,	/* China */
++	RTW_RD_5G_MKK10 = 71,	/* Japan */
++	RTW_RD_5G_ETSI26 = 72,	/* Singapore */
++
++	RTW_RD_5G_MAX,
++};
++
++struct ch_list_t {
++	u8 *len_ch_attr;
++};
++
++#define CLA_2G_12_14_PASSIVE	BIT0
++
++#define CLA_5G_B1_PASSIVE		BIT0
++#define CLA_5G_B2_PASSIVE		BIT1
++#define CLA_5G_B3_PASSIVE		BIT2
++#define CLA_5G_B4_PASSIVE		BIT3
++#define CLA_5G_B2_DFS			BIT4
++#define CLA_5G_B3_DFS			BIT5
++#define CLA_5G_B4_DFS			BIT6
++
++#define CH_LIST_ENT(_len, arg...) \
++	{.len_ch_attr = (u8[_len + 2]) {_len, ##arg}, }
++
++#define CH_LIST_LEN(_ch_list) (_ch_list.len_ch_attr[0])
++#define CH_LIST_CH(_ch_list, _i) (_ch_list.len_ch_attr[_i + 1])
++#define CH_LIST_ATTRIB(_ch_list) (_ch_list.len_ch_attr[CH_LIST_LEN(_ch_list) + 1])
++
++struct chplan_ent_t {
++	u8 rd_2g;
++#if CONFIG_IEEE80211_BAND_5GHZ
++	u8 rd_5g;
++#endif
++	u8 regd; /* value of REGULATION_TXPWR_LMT */
++};
++
++#if CONFIG_IEEE80211_BAND_5GHZ
++#define CHPLAN_ENT(i2g, i5g, regd) {i2g, i5g, regd}
++#else
++#define CHPLAN_ENT(i2g, i5g, regd) {i2g, regd}
++#endif
++
++#define CHPLAN_ENT_NOT_DEFINED CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW)
++
++static const struct ch_list_t RTW_ChannelPlan2G[] = {
++	/* 0, RTW_RD_2G_WORLD */	CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, CLA_2G_12_14_PASSIVE),
++	/* 1, RTW_RD_2G_ETSI1 */		CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0),
++	/* 2, RTW_RD_2G_FCC1 */		CH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 0),
++	/* 3, RTW_RD_2G_MKK1 */		CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0),
++	/* 4, RTW_RD_2G_ETSI2 */		CH_LIST_ENT(4, 10, 11, 12, 13, 0),
++	/* 5, RTW_RD_2G_GLOBAL */	CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, CLA_2G_12_14_PASSIVE),
++	/* 6, RTW_RD_2G_MKK2 */		CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0),
++	/* 7, RTW_RD_2G_FCC2 */		CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0),
++	/* 8, RTW_RD_2G_NULL */		CH_LIST_ENT(0, 0),
++	/* 9, RTW_RD_2G_IC1 */		CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0),
++	/* 10, RTW_RD_2G_WORLD1 */	CH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 0),
++	/* 11, RTW_RD_2G_KCC1 */	CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0),
++	/* 12, RTW_RD_2G_IC2 */		CH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 0),
++};
++
++#if CONFIG_IEEE80211_BAND_5GHZ
++static const struct ch_list_t RTW_ChannelPlan5G[] = {
++	/* 0, RTW_RD_5G_NULL */		CH_LIST_ENT(0, 0),
++	/* 1, RTW_RD_5G_ETSI1 */		CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 2, RTW_RD_5G_ETSI2 */		CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 3, RTW_RD_5G_ETSI3 */		CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 4, RTW_RD_5G_FCC1 */		CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 5, RTW_RD_5G_FCC2 */		CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165, 0),
++	/* 6, RTW_RD_5G_FCC3 */		CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_DFS),
++	/* 7, RTW_RD_5G_FCC4 */		CH_LIST_ENT(12, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, CLA_5G_B2_DFS),
++	/* 8, RTW_RD_5G_FCC5 */		CH_LIST_ENT(5, 149, 153, 157, 161, 165, 0),
++	/* 9, RTW_RD_5G_FCC6 */		CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64, CLA_5G_B2_DFS),
++	/* 10, RTW_RD_5G_FCC7 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 11, RTW_RD_5G_IC1 */		CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 12, RTW_RD_5G_KCC1 */	CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 13, RTW_RD_5G_MKK1 */	CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 14, RTW_RD_5G_MKK2 */	CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64, CLA_5G_B2_DFS),
++	/* 15, RTW_RD_5G_MKK3 */	CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, CLA_5G_B3_DFS),
++	/* 16, RTW_RD_5G_NCC1 */	CH_LIST_ENT(16, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 17, RTW_RD_5G_NCC2 */	CH_LIST_ENT(8, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_DFS),
++	/* 18, RTW_RD_5G_NCC3 */	CH_LIST_ENT(5, 149, 153, 157, 161, 165, 0),
++	/* 19, RTW_RD_5G_ETSI4 */	CH_LIST_ENT(4, 36, 40, 44, 48, 0),
++	/* 20, RTW_RD_5G_ETSI5 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 21, RTW_RD_5G_FCC8 */	CH_LIST_ENT(4, 149, 153, 157, 161, 0),
++	/* 22, RTW_RD_5G_ETSI6 */	CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64, CLA_5G_B2_DFS),
++	/* 23, RTW_RD_5G_ETSI7 */	CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_DFS),
++	/* 24, RTW_RD_5G_ETSI8 */	CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165, 0),
++	/* 25, RTW_RD_5G_ETSI9 */	CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 0),
++	/* 26, RTW_RD_5G_ETSI10 */	CH_LIST_ENT(5, 149, 153, 157, 161, 165, 0),
++	/* 27, RTW_RD_5G_ETSI11 */	CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 28, RTW_RD_5G_NCC4 */	CH_LIST_ENT(17, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 29, RTW_RD_5G_ETSI12 */	CH_LIST_ENT(4, 149, 153, 157, 161, 0),
++	/* 30, RTW_RD_5G_FCC9 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 31, RTW_RD_5G_ETSI13 */	CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 32, RTW_RD_5G_FCC10 */	CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 33, RTW_RD_5G_MKK4 */	CH_LIST_ENT(4, 36, 40, 44, 48, 0),
++	/* 34, RTW_RD_5G_ETSI14 */	CH_LIST_ENT(11, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 35, RTW_RD_5G_FCC11 */	CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 36, RTW_RD_5G_ETSI15 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 37, RTW_RD_5G_MKK5 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE),
++	/* 38, RTW_RD_5G_ETSI16 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE),
++	/* 39, RTW_RD_5G_ETSI17 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE),
++	/* 40, RTW_RD_5G_FCC12 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE),
++	/* 41, RTW_RD_5G_FCC13 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE),
++	/* 42, RTW_RD_5G_FCC14 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE),
++	/* 43, RTW_RD_5G_FCC15 */	CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE),
++	/* 44, RTW_RD_5G_FCC16 */	CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE),
++	/* 45, RTW_RD_5G_ETSI18 */	CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B4_PASSIVE),
++	/* 46, RTW_RD_5G_ETSI19 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE),
++	/* 47, RTW_RD_5G_FCC17 */	CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 48, RTW_RD_5G_ETSI20 */	CH_LIST_ENT(9, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_DFS),
++	/* 49, RTW_RD_5G_IC2 */		CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 144, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 50, RTW_RD_5G_ETSI21 */	CH_LIST_ENT(13, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B3_DFS),
++	/* 51, RTW_RD_5G_FCC18 */	CH_LIST_ENT(8, 100, 104, 108, 112, 116, 132, 136, 140, CLA_5G_B3_DFS),
++	/* 52, RTW_RD_5G_WORLD */	CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE),
++	/* 53, RTW_RD_5G_CHILE1 */	CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 54, RTW_RD_5G_ACMA1 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 55, RTW_RD_5G_WORLD1 */	CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE),
++	/* 56, RTW_RD_5G_CHILE2 */	CH_LIST_ENT(16, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 57, RTW_RD_5G_KCC2 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 58, RTW_RD_5G_KCC3 */	CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 59, RTW_RD_5G_MKK6 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_DFS | CLA_5G_B3_DFS | CLA_5G_B4_DFS),
++	/* 60, RTW_RD_5G_MKK7 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 61, RTW_RD_5G_MKK8 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 62, RTW_RD_5G_MEX1 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
++	/* 63, RTW_RD_5G_ETSI22 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_DFS | CLA_5G_B3_DFS | CLA_5G_B4_PASSIVE),
++	/* 64, RTW_RD_5G_MKK9 */	CH_LIST_ENT(23, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE),
++	/* 65, RTW_RD_5G_FCC19 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE),
++	/* 66, RTW_RD_5G_FCC20 */	CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B4_PASSIVE),
++	/* 67, RTW_RD_5G_FCC21 */	CH_LIST_ENT(23, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE),
++	/* 68, RTW_RD_5G_ETSI23 */	CH_LIST_ENT(12, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, CLA_5G_B2_DFS),
++	/* 69, RTW_RD_5G_ETSI24 */	CH_LIST_ENT(12, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, CLA_5G_B2_PASSIVE),
++	/* 70, RTW_RD_5G_ETSI25 */	CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE),
++	/* 71, RTW_RD_5G_MKK10 */	CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE),
++	/* 72, RTW_RD_5G_ETSI26 */	CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE),
++};
++#endif /* CONFIG_IEEE80211_BAND_5GHZ */
++
++static const struct chplan_ent_t RTW_ChannelPlanMap[] = {
++	/* 0x00 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x01 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x02 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x03 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x04 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x05 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x06 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x07 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x08 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x09 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x0A */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x0B */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x0C */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x0D */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x0E */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x0F */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x10 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x11 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x12 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x13 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x14 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x15 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x16 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x17 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x18 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x19 */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x1A */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x1B */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x1C */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x1D */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x1E */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x1F */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x20 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),
++	/* 0x21 */	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_NULL,		TXPWR_LMT_ETSI),
++	/* 0x22 */	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_NULL,		TXPWR_LMT_FCC),
++	/* 0x23 */	CHPLAN_ENT(RTW_RD_2G_MKK1,		RTW_RD_5G_NULL,		TXPWR_LMT_MKK),
++	/* 0x24 */	CHPLAN_ENT(RTW_RD_2G_ETSI2,		RTW_RD_5G_NULL,		TXPWR_LMT_ETSI),
++	/* 0x25 */	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC1,		TXPWR_LMT_FCC),
++	/* 0x26 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI1,	TXPWR_LMT_ETSI),
++	/* 0x27 */	CHPLAN_ENT(RTW_RD_2G_MKK1,		RTW_RD_5G_MKK1,		TXPWR_LMT_MKK),
++	/* 0x28 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_KCC1,		TXPWR_LMT_KCC),
++	/* 0x29 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC2,		TXPWR_LMT_FCC),
++	/* 0x2A */	CHPLAN_ENT(RTW_RD_2G_FCC2,		RTW_RD_5G_NULL,		TXPWR_LMT_FCC),
++	/* 0x2B */	CHPLAN_ENT(RTW_RD_2G_IC1,		RTW_RD_5G_IC2,		TXPWR_LMT_IC),
++	/* 0x2C */	CHPLAN_ENT(RTW_RD_2G_MKK2,		RTW_RD_5G_NULL,		TXPWR_LMT_MKK),
++	/* 0x2D */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_CHILE1,	TXPWR_LMT_CHILE),
++	/* 0x2E */	CHPLAN_ENT(RTW_RD_2G_WORLD1,	RTW_RD_5G_WORLD1,	TXPWR_LMT_WW),
++	/* 0x2F */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_CHILE2,	TXPWR_LMT_CHILE),
++	/* 0x30 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC3,		TXPWR_LMT_FCC),
++	/* 0x31 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC4,		TXPWR_LMT_FCC),
++	/* 0x32 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC5,		TXPWR_LMT_FCC),
++	/* 0x33 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC6,		TXPWR_LMT_FCC),
++	/* 0x34 */	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC7,		TXPWR_LMT_FCC),
++	/* 0x35 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI2,	TXPWR_LMT_ETSI),
++	/* 0x36 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI3,	TXPWR_LMT_ETSI),
++	/* 0x37 */	CHPLAN_ENT(RTW_RD_2G_MKK1,		RTW_RD_5G_MKK2,		TXPWR_LMT_MKK),
++	/* 0x38 */	CHPLAN_ENT(RTW_RD_2G_MKK1,		RTW_RD_5G_MKK3,		TXPWR_LMT_MKK),
++	/* 0x39 */	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_NCC1,		TXPWR_LMT_FCC),
++	/* 0x3A */	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI1,	TXPWR_LMT_ETSI),
++	/* 0x3B */	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ACMA1,	TXPWR_LMT_ACMA),
++	/* 0x3C */	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI6,	TXPWR_LMT_ETSI),
++	/* 0x3D */	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI12,	TXPWR_LMT_ETSI),
++	/* 0x3E */	CHPLAN_ENT(RTW_RD_2G_KCC1,		RTW_RD_5G_KCC2,		TXPWR_LMT_KCC),
++	/* 0x3F */	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC11,	TXPWR_LMT_FCC),
++	/* 0x40 */	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_NCC2,		TXPWR_LMT_FCC),
++	/* 0x41 */	CHPLAN_ENT(RTW_RD_2G_GLOBAL,	RTW_RD_5G_NULL,		TXPWR_LMT_WW),
++	/* 0x42 */	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI4,	TXPWR_LMT_ETSI),
++	/* 0x43 */	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC2,		TXPWR_LMT_FCC),
++	/* 0x44 */	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_NCC3,		TXPWR_LMT_FCC),
++	/* 0x45 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ACMA1,	TXPWR_LMT_ACMA),
++	/* 0x46 */	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC8,		TXPWR_LMT_FCC),
++	/* 0x47 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI6,	TXPWR_LMT_ETSI),
++	/* 0x48 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI7,	TXPWR_LMT_ETSI),
++	/* 0x49 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI8,	TXPWR_LMT_ETSI),
++	/* 0x4A */	CHPLAN_ENT(RTW_RD_2G_IC2,		RTW_RD_5G_IC2,		TXPWR_LMT_IC),
++	/* 0x4B */	CHPLAN_ENT(RTW_RD_2G_KCC1,		RTW_RD_5G_KCC3,		TXPWR_LMT_KCC),
++	/* 0x4C */	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC15,	TXPWR_LMT_FCC),
++	/* 0x4D */	CHPLAN_ENT(RTW_RD_2G_FCC2,		RTW_RD_5G_MEX1,		TXPWR_LMT_MEXICO),
++	/* 0x4E */	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI22,	TXPWR_LMT_ETSI),
++	/* 0x4F */	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_MKK9,		TXPWR_LMT_MKK),
++	/* 0x50 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI9,	TXPWR_LMT_ETSI),
++	/* 0x51 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI10,	TXPWR_LMT_ETSI),
++	/* 0x52 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI11,	TXPWR_LMT_ETSI),
++	/* 0x53 */	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_NCC4,		TXPWR_LMT_FCC),
++	/* 0x54 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI12,	TXPWR_LMT_ETSI),
++	/* 0x55 */	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC9,		TXPWR_LMT_FCC),
++	/* 0x56 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI13,	TXPWR_LMT_ETSI),
++	/* 0x57 */	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC10,	TXPWR_LMT_FCC),
++	/* 0x58 */	CHPLAN_ENT(RTW_RD_2G_MKK2,		RTW_RD_5G_MKK4,		TXPWR_LMT_MKK),
++	/* 0x59 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI14,	TXPWR_LMT_ETSI),
++	/* 0x5A */	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_FCC19,	TXPWR_LMT_FCC),
++	/* 0x5B */	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_FCC20,	TXPWR_LMT_FCC),
++	/* 0x5C */	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_FCC21,	TXPWR_LMT_FCC),
++	/* 0x5D */	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI23,	TXPWR_LMT_ETSI),
++	/* 0x5E */	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI2,	TXPWR_LMT_ETSI),
++	/* 0x5F */	CHPLAN_ENT(RTW_RD_2G_MKK2,		RTW_RD_5G_MKK10,	TXPWR_LMT_MKK),
++	/* 0x60 */	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC5,		TXPWR_LMT_FCC),
++	/* 0x61 */	CHPLAN_ENT(RTW_RD_2G_FCC2,		RTW_RD_5G_FCC7,		TXPWR_LMT_FCC),
++	/* 0x62 */	CHPLAN_ENT(RTW_RD_2G_FCC2,		RTW_RD_5G_FCC1,		TXPWR_LMT_FCC),
++	/* 0x63 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI15,	TXPWR_LMT_ETSI),
++	/* 0x64 */	CHPLAN_ENT(RTW_RD_2G_MKK2,		RTW_RD_5G_MKK5,		TXPWR_LMT_MKK),
++	/* 0x65 */	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI16,	TXPWR_LMT_ETSI),
++	/* 0x66 */	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC14,	TXPWR_LMT_FCC),
++	/* 0x67 */	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC12,	TXPWR_LMT_FCC),
++	/* 0x68 */	CHPLAN_ENT(RTW_RD_2G_FCC2,		RTW_RD_5G_FCC14,	TXPWR_LMT_FCC),
++	/* 0x69 */	CHPLAN_ENT(RTW_RD_2G_FCC2,		RTW_RD_5G_FCC12,	TXPWR_LMT_FCC),
++	/* 0x6A */	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI17,	TXPWR_LMT_ETSI),
++	/* 0x6B */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC16,	TXPWR_LMT_FCC),
++	/* 0x6C */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC13,	TXPWR_LMT_FCC),
++	/* 0x6D */	CHPLAN_ENT(RTW_RD_2G_FCC2,		RTW_RD_5G_FCC15,	TXPWR_LMT_FCC),
++	/* 0x6E */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC12,	TXPWR_LMT_FCC),
++	/* 0x6F */	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_ETSI8,	TXPWR_LMT_ETSI),
++	/* 0x70 */	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_ETSI18,	TXPWR_LMT_ETSI),
++	/* 0x71 */	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_ETSI17,	TXPWR_LMT_ETSI),
++	/* 0x72 */	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_ETSI19,	TXPWR_LMT_ETSI),
++	/* 0x73 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC7,		TXPWR_LMT_FCC),
++	/* 0x74 */	CHPLAN_ENT(RTW_RD_2G_FCC2,		RTW_RD_5G_FCC17,	TXPWR_LMT_FCC),
++	/* 0x75 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI20,	TXPWR_LMT_ETSI),
++	/* 0x76 */	CHPLAN_ENT(RTW_RD_2G_FCC2,		RTW_RD_5G_FCC11,	TXPWR_LMT_FCC),
++	/* 0x77 */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI21,	TXPWR_LMT_ETSI),
++	/* 0x78 */	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC18,	TXPWR_LMT_FCC),
++	/* 0x79 */	CHPLAN_ENT(RTW_RD_2G_MKK2,		RTW_RD_5G_MKK1,		TXPWR_LMT_MKK),
++	/* 0x7A */	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI25, 	TXPWR_LMT_ETSI),
++	/* 0x7B */	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI24,	TXPWR_LMT_ETSI),
++	/* 0x7C */	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI26,	TXPWR_LMT_ETSI),
++	/* 0x7D */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x7E */	CHPLAN_ENT_NOT_DEFINED,
++	/* 0x7F */	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC1,		TXPWR_LMT_FCC),		/* Realtek Define */
++};
++
++const int RTW_ChannelPlanMap_size = sizeof(RTW_ChannelPlanMap) / sizeof(RTW_ChannelPlanMap[0]);
++
++u8 rtw_chplan_get_default_regd(u8 id)
++{
++	return RTW_ChannelPlanMap[id].regd;
++}
++
++bool rtw_chplan_is_empty(u8 id)
++{
++	const struct chplan_ent_t *chplan_map = &RTW_ChannelPlanMap[id];
++
++	if (chplan_map->rd_2g == RTW_RD_2G_NULL
++		#if CONFIG_IEEE80211_BAND_5GHZ
++		&& chplan_map->rd_5g == RTW_RD_5G_NULL
++		#endif
++	)
++		return _TRUE;
++
++	return _FALSE;
++}
++
++bool rtw_is_channel_plan_valid(u8 id)
++{
++	return id < RTW_ChannelPlanMap_size && !rtw_chplan_is_empty(id);
++}
++
++bool rtw_regsty_is_excl_chs(struct registry_priv *regsty, u8 ch)
++{
++	int i;
++
++	for (i = 0; i < MAX_CHANNEL_NUM; i++) {
++		if (regsty->excl_chs[i] == 0)
++			break;
++		if (regsty->excl_chs[i] == ch)
++			return _TRUE;
++	}
++	return _FALSE;
++}
++
++u8 init_channel_set(_adapter *padapter, u8 ChannelPlan, RT_CHANNEL_INFO *channel_set)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	struct registry_priv *regsty = adapter_to_regsty(padapter);
++	u8 index, chanset_size = 0;
++	u8 b5GBand = _FALSE, b2_4GBand = _FALSE;
++	u8 rd_2g = 0, rd_5g = 0;
++	u8 ch, attrib;
++#ifdef CONFIG_DFS_MASTER
++	int i;
++#endif
++
++	if (!rtw_is_channel_plan_valid(ChannelPlan)) {
++		RTW_ERR("ChannelPlan ID 0x%02X error !!!!!\n", ChannelPlan);
++		return chanset_size;
++	}
++
++	_rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
++
++	if (IsSupported24G(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_2G))
++		b2_4GBand = _TRUE;
++
++	if (is_supported_5g(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_5G))
++		b5GBand = _TRUE;
++
++	if (b2_4GBand == _FALSE && b5GBand == _FALSE) {
++		RTW_WARN("HW band_cap has no intersection with SW wireless_mode setting\n");
++		return chanset_size;
++	}
++
++	if (b2_4GBand) {
++		rd_2g = RTW_ChannelPlanMap[ChannelPlan].rd_2g;
++		attrib = CH_LIST_ATTRIB(RTW_ChannelPlan2G[rd_2g]);
++
++		for (index = 0; index < CH_LIST_LEN(RTW_ChannelPlan2G[rd_2g]); index++) {
++			ch = CH_LIST_CH(RTW_ChannelPlan2G[rd_2g], index);
++			if (rtw_regsty_is_excl_chs(regsty, ch) == _TRUE)
++				continue;
++
++			if (chanset_size >= MAX_CHANNEL_NUM) {
++				RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM);
++				break;
++			}
++
++			channel_set[chanset_size].ChannelNum = ch;
++
++			if (ch >= 12 && ch <= 14 && (attrib & CLA_2G_12_14_PASSIVE))
++				channel_set[chanset_size].ScanType = SCAN_PASSIVE;
++			else
++				channel_set[chanset_size].ScanType = SCAN_ACTIVE;
++
++			if (channel_set[chanset_size].ScanType == SCAN_PASSIVE) {
++				if (rfctl->country_ent || ch <= 11)
++					RTW_INFO("ch%u is PASSIVE\n", ch);
++			}
++
++			chanset_size++;
++		}
++	}
++
++#if CONFIG_IEEE80211_BAND_5GHZ
++	if (b5GBand) {
++		bool dfs;
++
++		rd_5g = RTW_ChannelPlanMap[ChannelPlan].rd_5g;
++		attrib = CH_LIST_ATTRIB(RTW_ChannelPlan5G[rd_5g]);
++
++		for (index = 0; index < CH_LIST_LEN(RTW_ChannelPlan5G[rd_5g]); index++) {
++			ch = CH_LIST_CH(RTW_ChannelPlan5G[rd_5g], index);
++			if (rtw_regsty_is_excl_chs(regsty, ch) == _TRUE)
++				continue;
++			dfs = (rtw_is_5g_band2(ch) && (attrib & CLA_5G_B2_DFS))
++				|| (rtw_is_5g_band3(ch) && (attrib & CLA_5G_B3_DFS))
++				|| (rtw_is_5g_band4(ch) && (attrib & CLA_5G_B4_DFS));
++			#if !CONFIG_DFS
++			if (dfs)
++				continue;
++			#endif
++
++			if (chanset_size >= MAX_CHANNEL_NUM) {
++				RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM);
++				break;
++			}
++
++			channel_set[chanset_size].ChannelNum = ch;
++
++			if ((rtw_is_5g_band1(ch) && (attrib & CLA_5G_B1_PASSIVE)) /* band1 passive */
++				|| (rtw_is_5g_band2(ch) && (attrib & CLA_5G_B2_PASSIVE)) /* band2 passive */
++				|| (rtw_is_5g_band3(ch) && (attrib & CLA_5G_B3_PASSIVE)) /* band3 passive */
++				|| (rtw_is_5g_band4(ch) && (attrib & CLA_5G_B4_PASSIVE)) /* band4 passive */
++			)
++				channel_set[chanset_size].ScanType = SCAN_PASSIVE;
++			else
++				channel_set[chanset_size].ScanType = SCAN_ACTIVE;
++
++			channel_set[chanset_size].dfs = dfs;
++
++			if (channel_set[chanset_size].ScanType == SCAN_PASSIVE) {
++				if (rfctl->country_ent || channel_set[chanset_size].dfs)
++					RTW_INFO("ch%u is PASSIVE%s\n", ch, dfs ? " DFS" : "");
++			}
++
++			chanset_size++;
++		}
++	}
++
++	#ifdef CONFIG_DFS_MASTER
++	for (i = 0; i < chanset_size; i++)
++		channel_set[i].non_ocp_end_time = rtw_get_current_time();
++	#endif
++#endif /* CONFIG_IEEE80211_BAND_5GHZ */
++
++	if (chanset_size)
++		RTW_INFO(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, ch num:%d\n"
++			, FUNC_ADPT_ARG(padapter), ChannelPlan, chanset_size);
++	else
++		RTW_WARN(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, final chset has no channel\n"
++			, FUNC_ADPT_ARG(padapter), ChannelPlan);
++
++	return chanset_size;
++}
++
++bool rtw_chset_is_dfs_range(struct _RT_CHANNEL_INFO *chset, u32 hi, u32 lo)
++{
++	u8 hi_ch = rtw_freq2ch(hi);
++	u8 lo_ch = rtw_freq2ch(lo);
++	int i;
++
++	for (i = 0; i < MAX_CHANNEL_NUM && chset[i].ChannelNum != 0; i++){
++		if (!chset[i].dfs)
++			continue;
++		if (hi_ch > chset[i].ChannelNum && lo_ch < chset[i].ChannelNum)
++			return 1;
++	}
++
++	return 0;
++}
++
++bool rtw_chset_is_dfs_ch(struct _RT_CHANNEL_INFO *chset, u8 ch)
++{
++	int i;
++
++	for (i = 0; i < MAX_CHANNEL_NUM && chset[i].ChannelNum != 0; i++){
++		if (chset[i].ChannelNum == ch)
++			return chset[i].dfs;
++	}
++
++	return 0;
++}
++
++bool rtw_chset_is_dfs_chbw(struct _RT_CHANNEL_INFO *chset, u8 ch, u8 bw, u8 offset)
++{
++	u32 hi, lo;
++
++	if (!rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo))
++		return 0;
++
++	return rtw_chset_is_dfs_range(chset, hi, lo);
++}
++
++void rtw_process_beacon_hint(_adapter *adapter, WLAN_BSSID_EX *bss)
++{
++#ifndef RTW_CHPLAN_BEACON_HINT_NON_WORLD_WIDE
++#define RTW_CHPLAN_BEACON_HINT_NON_WORLD_WIDE 0
++#endif
++
++#ifndef RTW_CHPLAN_BEACON_HINT_ON_2G_CH_1_11
++#define RTW_CHPLAN_BEACON_HINT_ON_2G_CH_1_11 0
++#endif
++
++#ifndef RTW_CHPLAN_BEACON_HINT_ON_DFS_CH
++#define RTW_CHPLAN_BEACON_HINT_ON_DFS_CH 0
++#endif
++
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	RT_CHANNEL_INFO *chset = rfctl->channel_set;
++	u8 ch = bss->Configuration.DSConfig;
++	int chset_idx = rtw_chset_search_ch(chset, ch);
++
++	if (chset_idx < 0)
++		return;
++
++	if (chset[chset_idx].ScanType == SCAN_PASSIVE
++		&& (RTW_CHPLAN_BEACON_HINT_NON_WORLD_WIDE || !rfctl->country_ent)
++		&& (RTW_CHPLAN_BEACON_HINT_ON_2G_CH_1_11 || !(ch <= 11))
++		&& (RTW_CHPLAN_BEACON_HINT_ON_DFS_CH || !chset[chset_idx].dfs)
++	) {
++		RTW_INFO("%s: change ch:%d to active\n", __func__, ch);
++		chset[chset_idx].ScanType = SCAN_ACTIVE;
++		init_op_class_ch_bmp(adapter, chset, rfctl->cur_spt_op_class_ch_bmp);
++	}
++}
++
++#ifdef CONFIG_80211AC_VHT
++#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val) , .en_11ac = (_val)
++#else
++#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val)
++#endif
++
++#if RTW_DEF_MODULE_REGULATORY_CERT
++#define COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_val) , .def_module_flags = (_val)
++#else
++#define COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_val)
++#endif
++
++/* has def_module_flags specified, used by common map and HAL dfference map */
++#define COUNTRY_CHPLAN_ENT(_alpha2, _chplan, _en_11ac, _def_module_flags) \
++	{.alpha2 = (_alpha2), .chplan = (_chplan) \
++		COUNTRY_CHPLAN_ASSIGN_EN_11AC(_en_11ac) \
++		COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_def_module_flags) \
++	}
++
++#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP
++
++#include "../platform/custom_country_chplan.h"
++
++#elif RTW_DEF_MODULE_REGULATORY_CERT
++
++/* leave def_module_flags empty, def_module_flags check is done on country_chplan_map */
++#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AE_HMC_M2) /* 2013 certify */
++static const struct country_chplan RTL8821AE_HMC_M2_country_chplan_exc_map[] = {
++	COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0), /* Canada */
++	COUNTRY_CHPLAN_ENT("CL", 0x30, 1, 0), /* Chile */
++	COUNTRY_CHPLAN_ENT("CN", 0x51, 1, 0), /* China */
++	COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0), /* Colombia */
++	COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0), /* Costa Rica */
++	COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0), /* Dominican Republic */
++	COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0), /* Ecuador */
++	COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0), /* Guatemala */
++	COUNTRY_CHPLAN_ENT("ID", 0x3D, 0, 0), /* Indonesia */
++	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
++	COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
++	COUNTRY_CHPLAN_ENT("MY", 0x47, 1, 0), /* Malaysia */
++	COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0), /* Nicaragua */
++	COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0), /* Panama */
++	COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0), /* Peru */
++	COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0), /* Puerto Rico */
++	COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0), /* Paraguay */
++	COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
++	COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0), /* Ukraine */
++	COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
++};
++#endif
++
++#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AU) /* 2014 certify */
++static const struct country_chplan RTL8821AU_country_chplan_exc_map[] = {
++	COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0), /* Canada */
++	COUNTRY_CHPLAN_ENT("ID", 0x3D, 0, 0), /* Indonesia */
++	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
++	COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0), /* Russia(fac/gost), Kaliningrad */
++	COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
++	COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0), /* Ukraine */
++	COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
++};
++#endif
++
++#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AENF_NGFF) /* 2014 certify */
++static const struct country_chplan RTL8812AENF_NGFF_country_chplan_exc_map[] = {
++	COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
++	COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
++};
++#endif
++
++#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AEBT_HMC) /* 2013 certify */
++static const struct country_chplan RTL8812AEBT_HMC_country_chplan_exc_map[] = {
++	COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0), /* Canada */
++	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
++	COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0), /* Russia(fac/gost), Kaliningrad */
++	COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
++	COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0), /* Ukraine */
++	COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
++};
++#endif
++
++#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8188EE_HMC_M2) /* 2012 certify */
++static const struct country_chplan RTL8188EE_HMC_M2_country_chplan_exc_map[] = {
++	COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0), /* Aruba */
++	COUNTRY_CHPLAN_ENT("BB", 0x34, 1, 0), /* Barbados */
++	COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */
++	COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0), /* Colombia */
++	COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0), /* Costa Rica */
++	COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0), /* Dominican Republic */
++	COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0), /* Ecuador */
++	COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0), /* Guatemala */
++	COUNTRY_CHPLAN_ENT("HT", 0x34, 1, 0), /* Haiti */
++	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
++	COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
++	COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0), /* Nicaragua */
++	COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0), /* Panama */
++	COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0), /* Peru */
++	COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0), /* Puerto Rico */
++	COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0), /* Paraguay */
++	COUNTRY_CHPLAN_ENT("SC", 0x34, 1, 0), /* Seychelles */
++	COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
++	COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
++	COUNTRY_CHPLAN_ENT("VC", 0x34, 1, 0), /* Saint Vincent and the Grenadines */
++};
++#endif
++
++#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BE_HMC_M2) /* 2013 certify */
++static const struct country_chplan RTL8723BE_HMC_M2_country_chplan_exc_map[] = {
++	COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0), /* Aruba */
++	COUNTRY_CHPLAN_ENT("BS", 0x34, 1, 0), /* Bahamas */
++	COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */
++	COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0), /* Colombia */
++	COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0), /* Costa Rica */
++	COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0), /* Dominican Republic */
++	COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0), /* Ecuador */
++	COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0), /* Guatemala */
++	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
++	COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
++	COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0), /* Nicaragua */
++	COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0), /* Panama */
++	COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0), /* Peru */
++	COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0), /* Puerto Rico */
++	COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0), /* Paraguay */
++	COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
++	COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
++};
++#endif
++
++#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BS_NGFF1216) /* 2014 certify */
++static const struct country_chplan RTL8723BS_NGFF1216_country_chplan_exc_map[] = {
++	COUNTRY_CHPLAN_ENT("BB", 0x34, 1, 0), /* Barbados */
++	COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */
++	COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0), /* Colombia */
++	COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0), /* Costa Rica */
++	COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0), /* Dominican Republic */
++	COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0), /* Ecuador */
++	COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0), /* Guatemala */
++	COUNTRY_CHPLAN_ENT("HT", 0x34, 1, 0), /* Haiti */
++	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
++	COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
++	COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0), /* Nicaragua */
++	COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0), /* Panama */
++	COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0), /* Peru */
++	COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0), /* Puerto Rico */
++	COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0), /* Paraguay */
++	COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
++	COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
++};
++#endif
++
++#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8192EEBT_HMC_M2) /* 2013 certify */
++static const struct country_chplan RTL8192EEBT_HMC_M2_country_chplan_exc_map[] = {
++	COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0), /* Aruba */
++	COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */
++	COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0), /* Colombia */
++	COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0), /* Costa Rica */
++	COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0), /* Dominican Republic */
++	COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0), /* Ecuador */
++	COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0), /* Guatemala */
++	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
++	COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
++	COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0), /* Nicaragua */
++	COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0), /* Panama */
++	COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0), /* Peru */
++	COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0), /* Puerto Rico */
++	COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0), /* Paraguay */
++	COUNTRY_CHPLAN_ENT("SC", 0x34, 1, 0), /* Seychelles */
++	COUNTRY_CHPLAN_ENT("ST", 0x34, 1, 0), /* Sao Tome and Principe */
++	COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
++	COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
++};
++#endif
++
++#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723DE_NGFF1630) /* 2016 certify */
++static const struct country_chplan RTL8723DE_NGFF1630_country_chplan_exc_map[] = {
++	COUNTRY_CHPLAN_ENT("CA", 0x2A, 1, 0), /* Canada */
++	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
++	COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
++};
++#endif
++
++#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8822BE) /* 2016 certify */
++static const struct country_chplan RTL8822BE_country_chplan_exc_map[] = {
++	COUNTRY_CHPLAN_ENT("ID", 0x3D, 0, 0), /* Indonesia */
++	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
++};
++#endif
++
++#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821CE) /* 2016 certify */
++static const struct country_chplan RTL8821CE_country_chplan_exc_map[] = {
++	COUNTRY_CHPLAN_ENT("ID", 0x3D, 0, 0), /* Indonesia */
++	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
++};
++#endif
++
++#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8822CE) /* 2018 certify */
++static const struct country_chplan RTL8822CE_country_chplan_exc_map[] = {
++};
++#endif
++
++/**
++ * rtw_def_module_get_chplan_from_country -
++ * @country_code: string of country code
++ * @return:
++ * Return NULL for case referring to common map
++ */
++static const struct country_chplan *rtw_def_module_get_chplan_from_country(const char *country_code)
++{
++	const struct country_chplan *ent = NULL;
++	const struct country_chplan *hal_map = NULL;
++	u16 hal_map_sz = 0;
++	int i;
++
++	/* TODO: runtime selection for multi driver */
++#if (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AE_HMC_M2)
++	hal_map = RTL8821AE_HMC_M2_country_chplan_exc_map;
++	hal_map_sz = sizeof(RTL8821AE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan);
++#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AU)
++	hal_map = RTL8821AU_country_chplan_exc_map;
++	hal_map_sz = sizeof(RTL8821AU_country_chplan_exc_map) / sizeof(struct country_chplan);
++#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AENF_NGFF)
++	hal_map = RTL8812AENF_NGFF_country_chplan_exc_map;
++	hal_map_sz = sizeof(RTL8812AENF_NGFF_country_chplan_exc_map) / sizeof(struct country_chplan);
++#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AEBT_HMC)
++	hal_map = RTL8812AEBT_HMC_country_chplan_exc_map;
++	hal_map_sz = sizeof(RTL8812AEBT_HMC_country_chplan_exc_map) / sizeof(struct country_chplan);
++#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8188EE_HMC_M2)
++	hal_map = RTL8188EE_HMC_M2_country_chplan_exc_map;
++	hal_map_sz = sizeof(RTL8188EE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan);
++#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BE_HMC_M2)
++	hal_map = RTL8723BE_HMC_M2_country_chplan_exc_map;
++	hal_map_sz = sizeof(RTL8723BE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan);
++#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BS_NGFF1216)
++	hal_map = RTL8723BS_NGFF1216_country_chplan_exc_map;
++	hal_map_sz = sizeof(RTL8723BS_NGFF1216_country_chplan_exc_map) / sizeof(struct country_chplan);
++#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8192EEBT_HMC_M2)
++	hal_map = RTL8192EEBT_HMC_M2_country_chplan_exc_map;
++	hal_map_sz = sizeof(RTL8192EEBT_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan);
++#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723DE_NGFF1630)
++	hal_map = RTL8723DE_NGFF1630_country_chplan_exc_map;
++	hal_map_sz = sizeof(RTL8723DE_NGFF1630_country_chplan_exc_map) / sizeof(struct country_chplan);
++#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8822BE)
++	hal_map = RTL8822BE_country_chplan_exc_map;
++	hal_map_sz = sizeof(RTL8822BE_country_chplan_exc_map) / sizeof(struct country_chplan);
++#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821CE)
++	hal_map = RTL8821CE_country_chplan_exc_map;
++	hal_map_sz = sizeof(RTL8821CE_country_chplan_exc_map) / sizeof(struct country_chplan);
++#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8822CE)
++	hal_map = RTL8822CE_country_chplan_exc_map;
++	hal_map_sz = sizeof(RTL8822CE_country_chplan_exc_map) / sizeof(struct country_chplan);
++#endif
++
++	if (hal_map == NULL || hal_map_sz == 0)
++		goto exit;
++
++	for (i = 0; i < hal_map_sz; i++) {
++		if (strncmp(country_code, hal_map[i].alpha2, 2) == 0) {
++			ent = &hal_map[i];
++			break;
++		}
++	}
++
++exit:
++	return ent;
++}
++#endif /* CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP or RTW_DEF_MODULE_REGULATORY_CERT */
++
++static const struct country_chplan country_chplan_map[] = {
++	COUNTRY_CHPLAN_ENT("AD", 0x26, 1, 0x000), /* Andorra */
++	COUNTRY_CHPLAN_ENT("AE", 0x35, 1, 0xFFB), /* United Arab Emirates */
++	COUNTRY_CHPLAN_ENT("AF", 0x42, 1, 0x000), /* Afghanistan */
++	COUNTRY_CHPLAN_ENT("AG", 0x76, 1, 0x000), /* Antigua & Barbuda */
++	COUNTRY_CHPLAN_ENT("AI", 0x26, 1, 0x000), /* Anguilla(UK) */
++	COUNTRY_CHPLAN_ENT("AL", 0x26, 1, 0xFF1), /* Albania */
++	COUNTRY_CHPLAN_ENT("AM", 0x26, 1, 0xEB0), /* Armenia */
++	COUNTRY_CHPLAN_ENT("AN", 0x76, 1, 0xFF1), /* Netherlands Antilles */
++	COUNTRY_CHPLAN_ENT("AO", 0x47, 1, 0xEE0), /* Angola */
++	COUNTRY_CHPLAN_ENT("AQ", 0x26, 1, 0x000), /* Antarctica */
++	COUNTRY_CHPLAN_ENT("AR", 0x61, 1, 0xFF3), /* Argentina */
++	COUNTRY_CHPLAN_ENT("AS", 0x76, 1, 0x000), /* American Samoa */
++	COUNTRY_CHPLAN_ENT("AT", 0x26, 1, 0xFFB), /* Austria */
++	COUNTRY_CHPLAN_ENT("AU", 0x45, 1, 0xFFB), /* Australia */
++	COUNTRY_CHPLAN_ENT("AW", 0x76, 1, 0x8B0), /* Aruba */
++	COUNTRY_CHPLAN_ENT("AZ", 0x26, 1, 0xFF1), /* Azerbaijan */
++	COUNTRY_CHPLAN_ENT("BA", 0x26, 1, 0xFF1), /* Bosnia & Herzegovina */
++	COUNTRY_CHPLAN_ENT("BB", 0x76, 1, 0xE50), /* Barbados */
++	COUNTRY_CHPLAN_ENT("BD", 0x26, 1, 0xFF1), /* Bangladesh */
++	COUNTRY_CHPLAN_ENT("BE", 0x26, 1, 0xFFB), /* Belgium */
++	COUNTRY_CHPLAN_ENT("BF", 0x26, 1, 0xEB0), /* Burkina Faso */
++	COUNTRY_CHPLAN_ENT("BG", 0x26, 1, 0xFF1), /* Bulgaria */
++	COUNTRY_CHPLAN_ENT("BH", 0x48, 1, 0xFF1), /* Bahrain */
++	COUNTRY_CHPLAN_ENT("BI", 0x26, 1, 0xEB0), /* Burundi */
++	COUNTRY_CHPLAN_ENT("BJ", 0x26, 1, 0xEB0), /* Benin */
++	COUNTRY_CHPLAN_ENT("BM", 0x76, 1, 0xE00), /* Bermuda (UK) */
++	COUNTRY_CHPLAN_ENT("BN", 0x47, 1, 0xE10), /* Brunei */
++	COUNTRY_CHPLAN_ENT("BO", 0x73, 1, 0xFF1), /* Bolivia */
++	COUNTRY_CHPLAN_ENT("BR", 0x62, 1, 0xFF1), /* Brazil */
++	COUNTRY_CHPLAN_ENT("BS", 0x76, 1, 0xE20), /* Bahamas */
++	COUNTRY_CHPLAN_ENT("BT", 0x26, 1, 0x000), /* Bhutan */
++	COUNTRY_CHPLAN_ENT("BV", 0x26, 1, 0x000), /* Bouvet Island (Norway) */
++	COUNTRY_CHPLAN_ENT("BW", 0x35, 1, 0xEF1), /* Botswana */
++	COUNTRY_CHPLAN_ENT("BY", 0x26, 1, 0xFF1), /* Belarus */
++	COUNTRY_CHPLAN_ENT("BZ", 0x76, 1, 0x000), /* Belize */
++	COUNTRY_CHPLAN_ENT("CA", 0x2B, 1, 0xFFB), /* Canada */
++	COUNTRY_CHPLAN_ENT("CC", 0x26, 1, 0x000), /* Cocos (Keeling) Islands (Australia) */
++	COUNTRY_CHPLAN_ENT("CD", 0x26, 1, 0xEB0), /* Congo, Republic of the */
++	COUNTRY_CHPLAN_ENT("CF", 0x26, 1, 0xEB0), /* Central African Republic */
++	COUNTRY_CHPLAN_ENT("CG", 0x26, 1, 0xEB0), /* Congo, Democratic Republic of the. Zaire */
++	COUNTRY_CHPLAN_ENT("CH", 0x26, 1, 0xFFB), /* Switzerland */
++	COUNTRY_CHPLAN_ENT("CI", 0x42, 1, 0xFF1), /* Cote d'Ivoire */
++	COUNTRY_CHPLAN_ENT("CK", 0x26, 1, 0x000), /* Cook Islands */
++	COUNTRY_CHPLAN_ENT("CL", 0x2D, 1, 0xFF1), /* Chile */
++	COUNTRY_CHPLAN_ENT("CM", 0x26, 1, 0xEB0), /* Cameroon */
++	COUNTRY_CHPLAN_ENT("CN", 0x48, 1, 0xFFB), /* China */
++	COUNTRY_CHPLAN_ENT("CO", 0x76, 1, 0xFF1), /* Colombia */
++	COUNTRY_CHPLAN_ENT("CR", 0x76, 1, 0xFF1), /* Costa Rica */
++	COUNTRY_CHPLAN_ENT("CV", 0x26, 1, 0xEB0), /* Cape Verde */
++	COUNTRY_CHPLAN_ENT("CX", 0x45, 1, 0x000), /* Christmas Island (Australia) */
++	COUNTRY_CHPLAN_ENT("CY", 0x26, 1, 0xFFB), /* Cyprus */
++	COUNTRY_CHPLAN_ENT("CZ", 0x26, 1, 0xFFB), /* Czech Republic */
++	COUNTRY_CHPLAN_ENT("DE", 0x26, 1, 0xFFB), /* Germany */
++	COUNTRY_CHPLAN_ENT("DJ", 0x26, 1, 0xE80), /* Djibouti */
++	COUNTRY_CHPLAN_ENT("DK", 0x26, 1, 0xFFB), /* Denmark */
++	COUNTRY_CHPLAN_ENT("DM", 0x76, 1, 0x000), /* Dominica */
++	COUNTRY_CHPLAN_ENT("DO", 0x76, 1, 0xFF1), /* Dominican Republic */
++	COUNTRY_CHPLAN_ENT("DZ", 0x26, 1, 0xFF1), /* Algeria */
++	COUNTRY_CHPLAN_ENT("EC", 0x76, 1, 0xFF1), /* Ecuador */
++	COUNTRY_CHPLAN_ENT("EE", 0x26, 1, 0xFFB), /* Estonia */
++	COUNTRY_CHPLAN_ENT("EG", 0x47, 1, 0xFF1), /* Egypt */
++	COUNTRY_CHPLAN_ENT("EH", 0x47, 1, 0xE80), /* Western Sahara */
++	COUNTRY_CHPLAN_ENT("ER", 0x26, 1, 0x000), /* Eritrea */
++	COUNTRY_CHPLAN_ENT("ES", 0x26, 1, 0xFFB), /* Spain, Canary Islands, Ceuta, Melilla */
++	COUNTRY_CHPLAN_ENT("ET", 0x26, 1, 0xCB0), /* Ethiopia */
++	COUNTRY_CHPLAN_ENT("FI", 0x26, 1, 0xFFB), /* Finland */
++	COUNTRY_CHPLAN_ENT("FJ", 0x76, 1, 0xE00), /* Fiji */
++	COUNTRY_CHPLAN_ENT("FK", 0x26, 1, 0x000), /* Falkland Islands (Islas Malvinas) (UK) */
++	COUNTRY_CHPLAN_ENT("FM", 0x76, 1, 0x000), /* Micronesia, Federated States of (USA) */
++	COUNTRY_CHPLAN_ENT("FO", 0x26, 1, 0x000), /* Faroe Islands (Denmark) */
++	COUNTRY_CHPLAN_ENT("FR", 0x26, 1, 0xFFB), /* France */
++	COUNTRY_CHPLAN_ENT("GA", 0x26, 1, 0xEB0), /* Gabon */
++	COUNTRY_CHPLAN_ENT("GB", 0x26, 1, 0xFFB), /* Great Britain (United Kingdom; England) */
++	COUNTRY_CHPLAN_ENT("GD", 0x76, 1, 0x0B0), /* Grenada */
++	COUNTRY_CHPLAN_ENT("GE", 0x26, 1, 0xE00), /* Georgia */
++	COUNTRY_CHPLAN_ENT("GF", 0x26, 1, 0x080), /* French Guiana */
++	COUNTRY_CHPLAN_ENT("GG", 0x26, 1, 0x000), /* Guernsey (UK) */
++	COUNTRY_CHPLAN_ENT("GH", 0x26, 1, 0xFF1), /* Ghana */
++	COUNTRY_CHPLAN_ENT("GI", 0x26, 1, 0xE00), /* Gibraltar (UK) */
++	COUNTRY_CHPLAN_ENT("GL", 0x26, 1, 0xE00), /* Greenland (Denmark) */
++	COUNTRY_CHPLAN_ENT("GM", 0x26, 1, 0xEB0), /* Gambia */
++	COUNTRY_CHPLAN_ENT("GN", 0x26, 1, 0xE10), /* Guinea */
++	COUNTRY_CHPLAN_ENT("GP", 0x26, 1, 0xE00), /* Guadeloupe (France) */
++	COUNTRY_CHPLAN_ENT("GQ", 0x26, 1, 0xEB0), /* Equatorial Guinea */
++	COUNTRY_CHPLAN_ENT("GR", 0x26, 1, 0xFFB), /* Greece */
++	COUNTRY_CHPLAN_ENT("GS", 0x26, 1, 0x000), /* South Georgia and the Sandwich Islands (UK) */
++	COUNTRY_CHPLAN_ENT("GT", 0x61, 1, 0xFF1), /* Guatemala */
++	COUNTRY_CHPLAN_ENT("GU", 0x76, 1, 0xE00), /* Guam (USA) */
++	COUNTRY_CHPLAN_ENT("GW", 0x26, 1, 0xEB0), /* Guinea-Bissau */
++	COUNTRY_CHPLAN_ENT("GY", 0x44, 1, 0x000), /* Guyana */
++	COUNTRY_CHPLAN_ENT("HK", 0x35, 1, 0xFFB), /* Hong Kong */
++	COUNTRY_CHPLAN_ENT("HM", 0x45, 1, 0x000), /* Heard and McDonald Islands (Australia) */
++	COUNTRY_CHPLAN_ENT("HN", 0x32, 1, 0xFF1), /* Honduras */
++	COUNTRY_CHPLAN_ENT("HR", 0x26, 1, 0xFF9), /* Croatia */
++	COUNTRY_CHPLAN_ENT("HT", 0x76, 1, 0xE50), /* Haiti */
++	COUNTRY_CHPLAN_ENT("HU", 0x26, 1, 0xFFB), /* Hungary */
++	COUNTRY_CHPLAN_ENT("ID", 0x5D, 1, 0x7F3), /* Indonesia */
++	COUNTRY_CHPLAN_ENT("IE", 0x26, 1, 0xFFB), /* Ireland */
++	COUNTRY_CHPLAN_ENT("IL", 0x47, 1, 0xFF1), /* Israel */
++	COUNTRY_CHPLAN_ENT("IM", 0x26, 1, 0x000), /* Isle of Man (UK) */
++	COUNTRY_CHPLAN_ENT("IN", 0x48, 1, 0xFF1), /* India */
++	COUNTRY_CHPLAN_ENT("IO", 0x26, 1, 0x000), /* British Indian Ocean Territory (UK) */
++	COUNTRY_CHPLAN_ENT("IQ", 0x26, 1, 0x000), /* Iraq */
++	COUNTRY_CHPLAN_ENT("IR", 0x26, 0, 0x000), /* Iran */
++	COUNTRY_CHPLAN_ENT("IS", 0x26, 1, 0xFFB), /* Iceland */
++	COUNTRY_CHPLAN_ENT("IT", 0x26, 1, 0xFFB), /* Italy */
++	COUNTRY_CHPLAN_ENT("JE", 0x26, 1, 0x000), /* Jersey (UK) */
++	COUNTRY_CHPLAN_ENT("JM", 0x32, 1, 0xFF1), /* Jamaica */
++	COUNTRY_CHPLAN_ENT("JO", 0x49, 1, 0xFFB), /* Jordan */
++	COUNTRY_CHPLAN_ENT("JP", 0x27, 1, 0xFFF), /* Japan- Telec */
++	COUNTRY_CHPLAN_ENT("KE", 0x47, 1, 0xFF9), /* Kenya */
++	COUNTRY_CHPLAN_ENT("KG", 0x26, 1, 0xFF1), /* Kyrgyzstan */
++	COUNTRY_CHPLAN_ENT("KH", 0x26, 1, 0xFF1), /* Cambodia */
++	COUNTRY_CHPLAN_ENT("KI", 0x26, 1, 0x000), /* Kiribati */
++	COUNTRY_CHPLAN_ENT("KM", 0x26, 1, 0x800), /* Comoros */
++	COUNTRY_CHPLAN_ENT("KN", 0x76, 1, 0x000), /* Saint Kitts and Nevis */
++	COUNTRY_CHPLAN_ENT("KR", 0x4B, 1, 0xFFB), /* South Korea */
++	COUNTRY_CHPLAN_ENT("KW", 0x47, 1, 0xFFB), /* Kuwait */
++	COUNTRY_CHPLAN_ENT("KY", 0x76, 1, 0x000), /* Cayman Islands (UK) */
++	COUNTRY_CHPLAN_ENT("KZ", 0x26, 1, 0xF00), /* Kazakhstan */
++	COUNTRY_CHPLAN_ENT("LA", 0x26, 1, 0x000), /* Laos */
++	COUNTRY_CHPLAN_ENT("LB", 0x26, 1, 0xFF1), /* Lebanon */
++	COUNTRY_CHPLAN_ENT("LC", 0x76, 1, 0x000), /* Saint Lucia */
++	COUNTRY_CHPLAN_ENT("LI", 0x26, 1, 0xFFB), /* Liechtenstein */
++	COUNTRY_CHPLAN_ENT("LK", 0x26, 1, 0xFF1), /* Sri Lanka */
++	COUNTRY_CHPLAN_ENT("LR", 0x26, 1, 0xEB0), /* Liberia */
++	COUNTRY_CHPLAN_ENT("LS", 0x26, 1, 0xFF1), /* Lesotho */
++	COUNTRY_CHPLAN_ENT("LT", 0x26, 1, 0xFFB), /* Lithuania */
++	COUNTRY_CHPLAN_ENT("LU", 0x26, 1, 0xFFB), /* Luxembourg */
++	COUNTRY_CHPLAN_ENT("LV", 0x26, 1, 0xFFB), /* Latvia */
++	COUNTRY_CHPLAN_ENT("LY", 0x26, 1, 0x000), /* Libya */
++	COUNTRY_CHPLAN_ENT("MA", 0x47, 1, 0xFF1), /* Morocco */
++	COUNTRY_CHPLAN_ENT("MC", 0x26, 1, 0xFFB), /* Monaco */
++	COUNTRY_CHPLAN_ENT("MD", 0x26, 1, 0xFF1), /* Moldova */
++	COUNTRY_CHPLAN_ENT("ME", 0x26, 1, 0xFF1), /* Montenegro */
++	COUNTRY_CHPLAN_ENT("MF", 0x76, 1, 0x000), /* Saint Martin */
++	COUNTRY_CHPLAN_ENT("MG", 0x26, 1, 0xE20), /* Madagascar */
++	COUNTRY_CHPLAN_ENT("MH", 0x76, 1, 0x000), /* Marshall Islands (USA) */
++	COUNTRY_CHPLAN_ENT("MK", 0x26, 1, 0xFF1), /* Republic of Macedonia (FYROM) */
++	COUNTRY_CHPLAN_ENT("ML", 0x26, 1, 0xEB0), /* Mali */
++	COUNTRY_CHPLAN_ENT("MM", 0x26, 1, 0x000), /* Burma (Myanmar) */
++	COUNTRY_CHPLAN_ENT("MN", 0x26, 1, 0x000), /* Mongolia */
++	COUNTRY_CHPLAN_ENT("MO", 0x35, 1, 0xE00), /* Macau */
++	COUNTRY_CHPLAN_ENT("MP", 0x76, 1, 0x000), /* Northern Mariana Islands (USA) */
++	COUNTRY_CHPLAN_ENT("MQ", 0x26, 1, 0xE40), /* Martinique (France) */
++	COUNTRY_CHPLAN_ENT("MR", 0x26, 1, 0xEA0), /* Mauritania */
++	COUNTRY_CHPLAN_ENT("MS", 0x26, 1, 0x000), /* Montserrat (UK) */
++	COUNTRY_CHPLAN_ENT("MT", 0x26, 1, 0xFFB), /* Malta */
++	COUNTRY_CHPLAN_ENT("MU", 0x26, 1, 0xEB0), /* Mauritius */
++	COUNTRY_CHPLAN_ENT("MV", 0x47, 1, 0x000), /* Maldives */
++	COUNTRY_CHPLAN_ENT("MW", 0x26, 1, 0xEB0), /* Malawi */
++	COUNTRY_CHPLAN_ENT("MX", 0x4D, 1, 0xFF1), /* Mexico */
++	COUNTRY_CHPLAN_ENT("MY", 0x63, 1, 0xFF1), /* Malaysia */
++	COUNTRY_CHPLAN_ENT("MZ", 0x26, 1, 0xFF1), /* Mozambique */
++	COUNTRY_CHPLAN_ENT("NA", 0x26, 1, 0xF00), /* Namibia */
++	COUNTRY_CHPLAN_ENT("NC", 0x26, 1, 0x000), /* New Caledonia */
++	COUNTRY_CHPLAN_ENT("NE", 0x26, 1, 0xEB0), /* Niger */
++	COUNTRY_CHPLAN_ENT("NF", 0x45, 1, 0x000), /* Norfolk Island (Australia) */
++	COUNTRY_CHPLAN_ENT("NG", 0x75, 1, 0xFF9), /* Nigeria */
++	COUNTRY_CHPLAN_ENT("NI", 0x76, 1, 0xFF1), /* Nicaragua */
++	COUNTRY_CHPLAN_ENT("NL", 0x26, 1, 0xFFB), /* Netherlands */
++	COUNTRY_CHPLAN_ENT("NO", 0x26, 1, 0xFFB), /* Norway */
++	COUNTRY_CHPLAN_ENT("NP", 0x48, 1, 0xEF0), /* Nepal */
++	COUNTRY_CHPLAN_ENT("NR", 0x26, 1, 0x000), /* Nauru */
++	COUNTRY_CHPLAN_ENT("NU", 0x45, 1, 0x000), /* Niue */
++	COUNTRY_CHPLAN_ENT("NZ", 0x45, 1, 0xFFB), /* New Zealand */
++	COUNTRY_CHPLAN_ENT("OM", 0x26, 1, 0xFF9), /* Oman */
++	COUNTRY_CHPLAN_ENT("PA", 0x76, 1, 0xFF1), /* Panama */
++	COUNTRY_CHPLAN_ENT("PE", 0x76, 1, 0xFF1), /* Peru */
++	COUNTRY_CHPLAN_ENT("PF", 0x26, 1, 0x000), /* French Polynesia (France) */
++	COUNTRY_CHPLAN_ENT("PG", 0x35, 1, 0xFF1), /* Papua New Guinea */
++	COUNTRY_CHPLAN_ENT("PH", 0x35, 1, 0xFF1), /* Philippines */
++	COUNTRY_CHPLAN_ENT("PK", 0x51, 1, 0xFF1), /* Pakistan */
++	COUNTRY_CHPLAN_ENT("PL", 0x26, 1, 0xFFB), /* Poland */
++	COUNTRY_CHPLAN_ENT("PM", 0x26, 1, 0x000), /* Saint Pierre and Miquelon (France) */
++	COUNTRY_CHPLAN_ENT("PR", 0x76, 1, 0xFF1), /* Puerto Rico */
++	COUNTRY_CHPLAN_ENT("PT", 0x26, 1, 0xFFB), /* Portugal */
++	COUNTRY_CHPLAN_ENT("PW", 0x76, 1, 0x000), /* Palau */
++	COUNTRY_CHPLAN_ENT("PY", 0x76, 1, 0xFF1), /* Paraguay */
++	COUNTRY_CHPLAN_ENT("QA", 0x35, 1, 0xFF9), /* Qatar */
++	COUNTRY_CHPLAN_ENT("RE", 0x26, 1, 0x000), /* Reunion (France) */
++	COUNTRY_CHPLAN_ENT("RO", 0x26, 1, 0xFF1), /* Romania */
++	COUNTRY_CHPLAN_ENT("RS", 0x26, 1, 0xFF1), /* Serbia, Kosovo */
++	COUNTRY_CHPLAN_ENT("RU", 0x59, 1, 0xFFB), /* Russia(fac/gost), Kaliningrad */
++	COUNTRY_CHPLAN_ENT("RW", 0x26, 1, 0x0B0), /* Rwanda */
++	COUNTRY_CHPLAN_ENT("SA", 0x35, 1, 0xFFB), /* Saudi Arabia */
++	COUNTRY_CHPLAN_ENT("SB", 0x26, 1, 0x000), /* Solomon Islands */
++	COUNTRY_CHPLAN_ENT("SC", 0x76, 1, 0xE90), /* Seychelles */
++	COUNTRY_CHPLAN_ENT("SE", 0x26, 1, 0xFFB), /* Sweden */
++	COUNTRY_CHPLAN_ENT("SG", 0x35, 1, 0xFFB), /* Singapore */
++	COUNTRY_CHPLAN_ENT("SH", 0x26, 1, 0x000), /* Saint Helena (UK) */
++	COUNTRY_CHPLAN_ENT("SI", 0x26, 1, 0xFFB), /* Slovenia */
++	COUNTRY_CHPLAN_ENT("SJ", 0x26, 1, 0x000), /* Svalbard (Norway) */
++	COUNTRY_CHPLAN_ENT("SK", 0x26, 1, 0xFFB), /* Slovakia */
++	COUNTRY_CHPLAN_ENT("SL", 0x26, 1, 0xEB0), /* Sierra Leone */
++	COUNTRY_CHPLAN_ENT("SM", 0x26, 1, 0x000), /* San Marino */
++	COUNTRY_CHPLAN_ENT("SN", 0x26, 1, 0xFF1), /* Senegal */
++	COUNTRY_CHPLAN_ENT("SO", 0x26, 1, 0x000), /* Somalia */
++	COUNTRY_CHPLAN_ENT("SR", 0x74, 1, 0x000), /* Suriname */
++	COUNTRY_CHPLAN_ENT("ST", 0x76, 1, 0xE80), /* Sao Tome and Principe */
++	COUNTRY_CHPLAN_ENT("SV", 0x30, 1, 0xFF1), /* El Salvador */
++	COUNTRY_CHPLAN_ENT("SX", 0x76, 1, 0x000), /* Sint Marteen */
++	COUNTRY_CHPLAN_ENT("SZ", 0x26, 1, 0x820), /* Swaziland */
++	COUNTRY_CHPLAN_ENT("TC", 0x26, 1, 0x000), /* Turks and Caicos Islands (UK) */
++	COUNTRY_CHPLAN_ENT("TD", 0x26, 1, 0xEB0), /* Chad */
++	COUNTRY_CHPLAN_ENT("TF", 0x26, 1, 0xE80), /* French Southern and Antarctic Lands (FR Southern Territories) */
++	COUNTRY_CHPLAN_ENT("TG", 0x26, 1, 0xEB0), /* Togo */
++	COUNTRY_CHPLAN_ENT("TH", 0x35, 1, 0xFF1), /* Thailand */
++	COUNTRY_CHPLAN_ENT("TJ", 0x26, 1, 0xE40), /* Tajikistan */
++	COUNTRY_CHPLAN_ENT("TK", 0x45, 1, 0x000), /* Tokelau */
++	COUNTRY_CHPLAN_ENT("TM", 0x26, 1, 0x000), /* Turkmenistan */
++	COUNTRY_CHPLAN_ENT("TN", 0x47, 1, 0xFF1), /* Tunisia */
++	COUNTRY_CHPLAN_ENT("TO", 0x26, 1, 0x000), /* Tonga */
++	COUNTRY_CHPLAN_ENT("TR", 0x26, 1, 0xFF1), /* Turkey, Northern Cyprus */
++	COUNTRY_CHPLAN_ENT("TT", 0x76, 1, 0x3F1), /* Trinidad & Tobago */
++	COUNTRY_CHPLAN_ENT("TV", 0x21, 0, 0x000), /* Tuvalu */
++	COUNTRY_CHPLAN_ENT("TW", 0x76, 1, 0xFFF), /* Taiwan */
++	COUNTRY_CHPLAN_ENT("TZ", 0x26, 1, 0xEF0), /* Tanzania */
++	COUNTRY_CHPLAN_ENT("UA", 0x36, 1, 0xFFB), /* Ukraine */
++	COUNTRY_CHPLAN_ENT("UG", 0x26, 1, 0xEF1), /* Uganda */
++	COUNTRY_CHPLAN_ENT("US", 0x76, 1, 0xFFF), /* United States of America (USA) */
++	COUNTRY_CHPLAN_ENT("UY", 0x30, 1, 0xFF1), /* Uruguay */
++	COUNTRY_CHPLAN_ENT("UZ", 0x47, 1, 0xEF0), /* Uzbekistan */
++	COUNTRY_CHPLAN_ENT("VA", 0x26, 1, 0x000), /* Holy See (Vatican City) */
++	COUNTRY_CHPLAN_ENT("VC", 0x76, 1, 0x010), /* Saint Vincent and the Grenadines */
++	COUNTRY_CHPLAN_ENT("VE", 0x30, 1, 0xFF1), /* Venezuela */
++	COUNTRY_CHPLAN_ENT("VG", 0x76, 1, 0x000), /* British Virgin Islands (UK) */
++	COUNTRY_CHPLAN_ENT("VI", 0x76, 1, 0x000), /* United States Virgin Islands (USA) */
++	COUNTRY_CHPLAN_ENT("VN", 0x35, 1, 0xFF1), /* Vietnam */
++	COUNTRY_CHPLAN_ENT("VU", 0x26, 1, 0x000), /* Vanuatu */
++	COUNTRY_CHPLAN_ENT("WF", 0x26, 1, 0x000), /* Wallis and Futuna (France) */
++	COUNTRY_CHPLAN_ENT("WS", 0x76, 1, 0x000), /* Samoa */
++	COUNTRY_CHPLAN_ENT("YE", 0x26, 1, 0x040), /* Yemen */
++	COUNTRY_CHPLAN_ENT("YT", 0x26, 1, 0xE80), /* Mayotte (France) */
++	COUNTRY_CHPLAN_ENT("ZA", 0x35, 1, 0xFF1), /* South Africa */
++	COUNTRY_CHPLAN_ENT("ZM", 0x26, 1, 0xEB0), /* Zambia */
++	COUNTRY_CHPLAN_ENT("ZW", 0x26, 1, 0xFF1), /* Zimbabwe */
++};
++
++/*
++* rtw_get_chplan_from_country -
++* @country_code: string of country code
++*
++* Return pointer of struct country_chplan entry or NULL when unsupported country_code is given
++*/
++const struct country_chplan *rtw_get_chplan_from_country(const char *country_code)
++{
++#if RTW_DEF_MODULE_REGULATORY_CERT
++	const struct country_chplan *exc_ent = NULL;
++#endif
++	const struct country_chplan *ent = NULL;
++	const struct country_chplan *map = NULL;
++	u16 map_sz = 0;
++	char code[2];
++	int i;
++
++	code[0] = alpha_to_upper(country_code[0]);
++	code[1] = alpha_to_upper(country_code[1]);
++
++#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP
++	map = CUSTOMIZED_country_chplan_map;
++	map_sz = sizeof(CUSTOMIZED_country_chplan_map) / sizeof(struct country_chplan);
++#else
++	#if RTW_DEF_MODULE_REGULATORY_CERT
++	exc_ent = rtw_def_module_get_chplan_from_country(code);
++	#endif
++	map = country_chplan_map;
++	map_sz = sizeof(country_chplan_map) / sizeof(struct country_chplan);
++#endif
++
++	for (i = 0; i < map_sz; i++) {
++		if (strncmp(code, map[i].alpha2, 2) == 0) {
++			ent = &map[i];
++			break;
++		}
++	}
++
++	#if RTW_DEF_MODULE_REGULATORY_CERT
++	if (!ent || !(COUNTRY_CHPLAN_DEF_MODULE_FALGS(ent) & RTW_DEF_MODULE_REGULATORY_CERT))
++		exc_ent = ent = NULL;
++	if (exc_ent)
++		ent = exc_ent;
++	#endif
++
++	return ent;
++}
++
++void dump_country_chplan(void *sel, const struct country_chplan *ent)
++{
++	RTW_PRINT_SEL(sel, "\"%c%c\", 0x%02X%s\n"
++		, ent->alpha2[0], ent->alpha2[1], ent->chplan
++		, COUNTRY_CHPLAN_EN_11AC(ent) ? " ac" : ""
++	);
++}
++
++void dump_country_chplan_map(void *sel)
++{
++	const struct country_chplan *ent;
++	u8 code[2];
++
++#if RTW_DEF_MODULE_REGULATORY_CERT
++	RTW_PRINT_SEL(sel, "RTW_DEF_MODULE_REGULATORY_CERT:0x%x\n", RTW_DEF_MODULE_REGULATORY_CERT);
++#endif
++#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP
++	RTW_PRINT_SEL(sel, "CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP\n");
++#endif
++
++	for (code[0] = 'A'; code[0] <= 'Z'; code[0]++) {
++		for (code[1] = 'A'; code[1] <= 'Z'; code[1]++) {
++			ent = rtw_get_chplan_from_country(code);
++			if (!ent)
++				continue;
++
++			dump_country_chplan(sel, ent);
++		}
++	}
++}
++
++void dump_chplan_id_list(void *sel)
++{
++	u8 first = 1;
++	int i;
++
++	for (i = 0; i < RTW_ChannelPlanMap_size; i++) {
++		if (!rtw_is_channel_plan_valid(i))
++			continue;
++
++		if (first) {
++			RTW_PRINT_SEL(sel, "0x%02X ", i);
++			first = 0;
++		} else
++			_RTW_PRINT_SEL(sel, "0x%02X ", i);
++	}
++}
++
++void dump_chplan_test(void *sel)
++{
++	int i, j;
++
++	/* check invalid channel */
++	for (i = 0; i < RTW_RD_2G_MAX; i++) {
++		for (j = 0; j < CH_LIST_LEN(RTW_ChannelPlan2G[i]); j++) {
++			if (rtw_ch2freq(CH_LIST_CH(RTW_ChannelPlan2G[i], j)) == 0)
++				RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", CH_LIST_CH(RTW_ChannelPlan2G[i], j), i, j);
++		}
++	}
++
++#if CONFIG_IEEE80211_BAND_5GHZ
++	for (i = 0; i < RTW_RD_5G_MAX; i++) {
++		for (j = 0; j < CH_LIST_LEN(RTW_ChannelPlan5G[i]); j++) {
++			if (rtw_ch2freq(CH_LIST_CH(RTW_ChannelPlan5G[i], j)) == 0)
++				RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", CH_LIST_CH(RTW_ChannelPlan5G[i], j), i, j);
++		}
++	}
++#endif
++}
++
++void dump_chplan_ver(void *sel)
++{
++	RTW_PRINT_SEL(sel, "%s%s-%s\n", RTW_DOMAIN_MAP_VER, RTW_DOMAIN_MAP_M_VER, RTW_COUNTRY_MAP_VER);
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_chplan.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_chplan.h
+new file mode 100644
+index 000000000..1e022d40b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_chplan.h
+@@ -0,0 +1,77 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2018 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_CHPLAN_H__
++#define __RTW_CHPLAN_H__
++
++#define RTW_CHPLAN_UNSPECIFIED 0xFF
++
++u8 rtw_chplan_get_default_regd(u8 id);
++bool rtw_chplan_is_empty(u8 id);
++bool rtw_is_channel_plan_valid(u8 id);
++
++struct _RT_CHANNEL_INFO;
++u8 init_channel_set(_adapter *padapter, u8 ChannelPlan, struct _RT_CHANNEL_INFO *channel_set);
++bool rtw_chset_is_dfs_range(struct _RT_CHANNEL_INFO *chset, u32 hi, u32 lo);
++bool rtw_chset_is_dfs_ch(struct _RT_CHANNEL_INFO *chset, u8 ch);
++bool rtw_chset_is_dfs_chbw(struct _RT_CHANNEL_INFO *chset, u8 ch, u8 bw, u8 offset);
++void rtw_process_beacon_hint(_adapter *adapter, WLAN_BSSID_EX *bss);
++
++#define IS_ALPHA2_NO_SPECIFIED(_alpha2) ((*((u16 *)(_alpha2))) == 0xFFFF)
++
++#define RTW_MODULE_RTL8821AE_HMC_M2		BIT0	/* RTL8821AE(HMC + M.2) */
++#define RTW_MODULE_RTL8821AU			BIT1	/* RTL8821AU */
++#define RTW_MODULE_RTL8812AENF_NGFF		BIT2	/* RTL8812AENF(8812AE+8761)_NGFF */
++#define RTW_MODULE_RTL8812AEBT_HMC		BIT3	/* RTL8812AEBT(8812AE+8761)_HMC */
++#define RTW_MODULE_RTL8188EE_HMC_M2		BIT4	/* RTL8188EE(HMC + M.2) */
++#define RTW_MODULE_RTL8723BE_HMC_M2		BIT5	/* RTL8723BE(HMC + M.2) */
++#define RTW_MODULE_RTL8723BS_NGFF1216	BIT6	/* RTL8723BS(NGFF1216) */
++#define RTW_MODULE_RTL8192EEBT_HMC_M2	BIT7	/* RTL8192EEBT(8192EE+8761AU)_(HMC + M.2) */
++#define RTW_MODULE_RTL8723DE_NGFF1630	BIT8	/* RTL8723DE(NGFF1630) */
++#define RTW_MODULE_RTL8822BE			BIT9	/* RTL8822BE */
++#define RTW_MODULE_RTL8821CE			BIT10	/* RTL8821CE */
++#define RTW_MODULE_RTL8822CE			BIT11	/* RTL8822CE */
++
++struct country_chplan {
++	char alpha2[2];
++	u8 chplan;
++#ifdef CONFIG_80211AC_VHT
++	u8 en_11ac;
++#endif
++#if RTW_DEF_MODULE_REGULATORY_CERT
++	u16 def_module_flags; /* RTW_MODULE_RTLXXX */
++#endif
++};
++
++#ifdef CONFIG_80211AC_VHT
++#define COUNTRY_CHPLAN_EN_11AC(_ent) ((_ent)->en_11ac)
++#else
++#define COUNTRY_CHPLAN_EN_11AC(_ent) 0
++#endif
++
++#if RTW_DEF_MODULE_REGULATORY_CERT
++#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) ((_ent)->def_module_flags)
++#else
++#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) 0
++#endif
++
++const struct country_chplan *rtw_get_chplan_from_country(const char *country_code);
++
++void dump_country_chplan(void *sel, const struct country_chplan *ent);
++void dump_country_chplan_map(void *sel);
++void dump_chplan_id_list(void *sel);
++void dump_chplan_test(void *sel);
++void dump_chplan_ver(void *sel);
++
++#endif /* __RTW_CHPLAN_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_cmd.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_cmd.c
+new file mode 100755
+index 000000000..735aa1d41
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_cmd.c
+@@ -0,0 +1,5511 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_CMD_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++#ifndef DBG_CMD_EXECUTE
++	#define DBG_CMD_EXECUTE 0
++#endif
++
++/*
++Caller and the rtw_cmd_thread can protect cmd_q by spin_lock.
++No irqsave is necessary.
++*/
++
++sint	_rtw_init_cmd_priv(struct	cmd_priv *pcmdpriv)
++{
++	sint res = _SUCCESS;
++
++
++	_rtw_init_sema(&(pcmdpriv->cmd_queue_sema), 0);
++	/* _rtw_init_sema(&(pcmdpriv->cmd_done_sema), 0); */
++	_rtw_init_sema(&(pcmdpriv->start_cmdthread_sema), 0);
++
++	_rtw_init_queue(&(pcmdpriv->cmd_queue));
++
++	/* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */
++
++	pcmdpriv->cmd_seq = 1;
++
++	pcmdpriv->cmd_allocated_buf = rtw_zmalloc(MAX_CMDSZ + CMDBUFF_ALIGN_SZ);
++
++	if (pcmdpriv->cmd_allocated_buf == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pcmdpriv->cmd_buf = pcmdpriv->cmd_allocated_buf  +  CMDBUFF_ALIGN_SZ - ((SIZE_PTR)(pcmdpriv->cmd_allocated_buf) & (CMDBUFF_ALIGN_SZ - 1));
++
++	pcmdpriv->rsp_allocated_buf = rtw_zmalloc(MAX_RSPSZ + 4);
++
++	if (pcmdpriv->rsp_allocated_buf == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pcmdpriv->rsp_buf = pcmdpriv->rsp_allocated_buf  +  4 - ((SIZE_PTR)(pcmdpriv->rsp_allocated_buf) & 3);
++
++	pcmdpriv->cmd_issued_cnt = pcmdpriv->cmd_done_cnt = pcmdpriv->rsp_cnt = 0;
++
++	_rtw_mutex_init(&pcmdpriv->sctx_mutex);
++exit:
++
++
++	return res;
++
++}
++
++#ifdef CONFIG_C2H_WK
++static void c2h_wk_callback(_workitem *work)
++{
++	struct evt_priv *evtpriv = container_of(work, struct evt_priv, c2h_wk);
++	_adapter *adapter = container_of(evtpriv, _adapter, evtpriv);
++	u8 *c2h_evt;
++	c2h_id_filter direct_hdl_filter = rtw_hal_c2h_id_handle_directly;
++	u8 id, seq, plen;
++	u8 *payload;
++
++	evtpriv->c2h_wk_alive = _TRUE;
++
++	while (!rtw_cbuf_empty(evtpriv->c2h_queue)) {
++		c2h_evt = (u8 *)rtw_cbuf_pop(evtpriv->c2h_queue);
++		if (c2h_evt != NULL) {
++			/* This C2H event is read, clear it */
++			c2h_evt_clear(adapter);
++		} else {
++			c2h_evt = (u8 *)rtw_malloc(C2H_REG_LEN);
++			if (c2h_evt == NULL) {
++				rtw_warn_on(1);
++				continue;
++			}
++
++			/* This C2H event is not read, read & clear now */
++			if (rtw_hal_c2h_evt_read(adapter, c2h_evt) != _SUCCESS) {
++				rtw_mfree(c2h_evt, C2H_REG_LEN);
++				continue;
++			}
++		}
++
++		/* Special pointer to trigger c2h_evt_clear only */
++		if ((void *)c2h_evt == (void *)evtpriv)
++			continue;
++
++		if (!rtw_hal_c2h_valid(adapter, c2h_evt)
++			|| rtw_hal_c2h_reg_hdr_parse(adapter, c2h_evt, &id, &seq, &plen, &payload) != _SUCCESS
++		) {
++			rtw_mfree(c2h_evt, C2H_REG_LEN);
++			continue;
++		}
++
++		if (direct_hdl_filter(adapter, id, seq, plen, payload) == _TRUE) {
++			/* Handle directly */
++			rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
++			rtw_mfree(c2h_evt, C2H_REG_LEN);
++		} else {
++			/* Enqueue into cmd_thread for others */
++			rtw_c2h_reg_wk_cmd(adapter, c2h_evt);
++			rtw_mfree(c2h_evt, C2H_REG_LEN);
++		}
++	}
++
++	evtpriv->c2h_wk_alive = _FALSE;
++}
++#endif /* CONFIG_C2H_WK */
++
++sint _rtw_init_evt_priv(struct evt_priv *pevtpriv)
++{
++	sint res = _SUCCESS;
++
++
++#ifdef CONFIG_H2CLBK
++	_rtw_init_sema(&(pevtpriv->lbkevt_done), 0);
++	pevtpriv->lbkevt_limit = 0;
++	pevtpriv->lbkevt_num = 0;
++	pevtpriv->cmdevt_parm = NULL;
++#endif
++
++	/* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */
++	ATOMIC_SET(&pevtpriv->event_seq, 0);
++	pevtpriv->evt_done_cnt = 0;
++
++#ifdef CONFIG_EVENT_THREAD_MODE
++
++	_rtw_init_sema(&(pevtpriv->evt_notify), 0);
++
++	pevtpriv->evt_allocated_buf = rtw_zmalloc(MAX_EVTSZ + 4);
++	if (pevtpriv->evt_allocated_buf == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++	pevtpriv->evt_buf = pevtpriv->evt_allocated_buf  +  4 - ((unsigned int)(pevtpriv->evt_allocated_buf) & 3);
++
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	pevtpriv->allocated_c2h_mem = rtw_zmalloc(C2H_MEM_SZ + 4);
++
++	if (pevtpriv->allocated_c2h_mem == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pevtpriv->c2h_mem = pevtpriv->allocated_c2h_mem +  4\
++			    - ((u32)(pevtpriv->allocated_c2h_mem) & 3);
++#endif /* end of CONFIG_SDIO_HCI */
++
++	_rtw_init_queue(&(pevtpriv->evt_queue));
++
++exit:
++
++#endif /* end of CONFIG_EVENT_THREAD_MODE */
++
++#ifdef CONFIG_C2H_WK
++	_init_workitem(&pevtpriv->c2h_wk, c2h_wk_callback, NULL);
++	pevtpriv->c2h_wk_alive = _FALSE;
++	pevtpriv->c2h_queue = rtw_cbuf_alloc(C2H_QUEUE_MAX_LEN + 1);
++#endif
++
++
++	return res;
++}
++
++void _rtw_free_evt_priv(struct	evt_priv *pevtpriv)
++{
++
++
++#ifdef CONFIG_EVENT_THREAD_MODE
++	_rtw_free_sema(&(pevtpriv->evt_notify));
++
++	if (pevtpriv->evt_allocated_buf)
++		rtw_mfree(pevtpriv->evt_allocated_buf, MAX_EVTSZ + 4);
++#endif
++
++#ifdef CONFIG_C2H_WK
++	_cancel_workitem_sync(&pevtpriv->c2h_wk);
++	while (pevtpriv->c2h_wk_alive)
++		rtw_msleep_os(10);
++
++	while (!rtw_cbuf_empty(pevtpriv->c2h_queue)) {
++		void *c2h;
++		c2h = rtw_cbuf_pop(pevtpriv->c2h_queue);
++		if (c2h != NULL && c2h != (void *)pevtpriv)
++			rtw_mfree(c2h, 16);
++	}
++	rtw_cbuf_free(pevtpriv->c2h_queue);
++#endif
++
++
++
++}
++
++void _rtw_free_cmd_priv(struct	cmd_priv *pcmdpriv)
++{
++
++	if (pcmdpriv) {
++		_rtw_spinlock_free(&(pcmdpriv->cmd_queue.lock));
++		_rtw_free_sema(&(pcmdpriv->cmd_queue_sema));
++		/* _rtw_free_sema(&(pcmdpriv->cmd_done_sema)); */
++		_rtw_free_sema(&(pcmdpriv->start_cmdthread_sema));
++
++		if (pcmdpriv->cmd_allocated_buf)
++			rtw_mfree(pcmdpriv->cmd_allocated_buf, MAX_CMDSZ + CMDBUFF_ALIGN_SZ);
++
++		if (pcmdpriv->rsp_allocated_buf)
++			rtw_mfree(pcmdpriv->rsp_allocated_buf, MAX_RSPSZ + 4);
++
++		_rtw_mutex_free(&pcmdpriv->sctx_mutex);
++	}
++}
++
++/*
++Calling Context:
++
++rtw_enqueue_cmd can only be called between kernel thread,
++since only spin_lock is used.
++
++ISR/Call-Back functions can't call this sub-function.
++
++*/
++#ifdef DBG_CMD_QUEUE
++extern u8 dump_cmd_id;
++#endif
++
++sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head)
++{
++	_irqL irqL;
++
++
++	if (obj == NULL)
++		goto exit;
++
++	/* _enter_critical_bh(&queue->lock, &irqL); */
++	_enter_critical(&queue->lock, &irqL);
++
++	if (to_head)
++		rtw_list_insert_head(&obj->list, &queue->queue);
++	else
++		rtw_list_insert_tail(&obj->list, &queue->queue);
++
++#ifdef DBG_CMD_QUEUE
++	if (dump_cmd_id) {
++		RTW_INFO("%s===> cmdcode:0x%02x\n", __FUNCTION__, obj->cmdcode);
++		if (obj->cmdcode == CMD_SET_MLME_EVT) {
++			if (obj->parmbuf) {
++				struct rtw_evt_header *evt_hdr = (struct rtw_evt_header *)(obj->parmbuf);
++				RTW_INFO("evt_hdr->id:%d\n", evt_hdr->id);
++			}
++		}
++		if (obj->cmdcode == CMD_SET_DRV_EXTRA) {
++			if (obj->parmbuf) {
++				struct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)(obj->parmbuf);
++				RTW_INFO("pdrvextra_cmd_parm->ec_id:0x%02x\n", pdrvextra_cmd_parm->ec_id);
++			}
++		}
++	}
++
++	if (queue->queue.prev->next != &queue->queue) {
++		RTW_INFO("[%d] head %p, tail %p, tail->prev->next %p[tail], tail->next %p[head]\n", __LINE__,
++			&queue->queue, queue->queue.prev, queue->queue.prev->prev->next, queue->queue.prev->next);
++
++		RTW_INFO("==========%s============\n", __FUNCTION__);
++		RTW_INFO("head:%p,obj_addr:%p\n", &queue->queue, obj);
++		RTW_INFO("padapter: %p\n", obj->padapter);
++		RTW_INFO("cmdcode: 0x%02x\n", obj->cmdcode);
++		RTW_INFO("res: %d\n", obj->res);
++		RTW_INFO("parmbuf: %p\n", obj->parmbuf);
++		RTW_INFO("cmdsz: %d\n", obj->cmdsz);
++		RTW_INFO("rsp: %p\n", obj->rsp);
++		RTW_INFO("rspsz: %d\n", obj->rspsz);
++		RTW_INFO("sctx: %p\n", obj->sctx);
++		RTW_INFO("list->next: %p\n", obj->list.next);
++		RTW_INFO("list->prev: %p\n", obj->list.prev);
++	}
++#endif /* DBG_CMD_QUEUE */
++
++	/* _exit_critical_bh(&queue->lock, &irqL);	 */
++	_exit_critical(&queue->lock, &irqL);
++
++exit:
++
++
++	return _SUCCESS;
++}
++
++struct	cmd_obj	*_rtw_dequeue_cmd(_queue *queue)
++{
++	_irqL irqL;
++	struct cmd_obj *obj;
++
++
++	/* _enter_critical_bh(&(queue->lock), &irqL); */
++	_enter_critical(&queue->lock, &irqL);
++
++#ifdef DBG_CMD_QUEUE
++	if (queue->queue.prev->next != &queue->queue) {
++		RTW_INFO("[%d] head %p, tail %p, tail->prev->next %p[tail], tail->next %p[head]\n", __LINE__,
++			&queue->queue, queue->queue.prev, queue->queue.prev->prev->next, queue->queue.prev->next);
++	}
++#endif /* DBG_CMD_QUEUE */
++
++
++	if (rtw_is_list_empty(&(queue->queue)))
++		obj = NULL;
++	else {
++		obj = LIST_CONTAINOR(get_next(&(queue->queue)), struct cmd_obj, list);
++
++#ifdef DBG_CMD_QUEUE
++		if (queue->queue.prev->next != &queue->queue) {
++			RTW_INFO("==========%s============\n", __FUNCTION__);
++			RTW_INFO("head:%p,obj_addr:%p\n", &queue->queue, obj);
++			RTW_INFO("padapter: %p\n", obj->padapter);
++			RTW_INFO("cmdcode: 0x%02x\n", obj->cmdcode);
++			RTW_INFO("res: %d\n", obj->res);
++			RTW_INFO("parmbuf: %p\n", obj->parmbuf);
++			RTW_INFO("cmdsz: %d\n", obj->cmdsz);
++			RTW_INFO("rsp: %p\n", obj->rsp);
++			RTW_INFO("rspsz: %d\n", obj->rspsz);
++			RTW_INFO("sctx: %p\n", obj->sctx);
++			RTW_INFO("list->next: %p\n", obj->list.next);
++			RTW_INFO("list->prev: %p\n", obj->list.prev);
++		}
++
++		if (dump_cmd_id) {
++			RTW_INFO("%s===> cmdcode:0x%02x\n", __FUNCTION__, obj->cmdcode);
++			if (obj->cmdcode == CMD_SET_DRV_EXTRA) {
++				if (obj->parmbuf) {
++					struct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)(obj->parmbuf);
++					printk("pdrvextra_cmd_parm->ec_id:0x%02x\n", pdrvextra_cmd_parm->ec_id);
++				}
++			}
++
++		}
++#endif /* DBG_CMD_QUEUE */
++
++		rtw_list_delete(&obj->list);
++	}
++
++	/* _exit_critical_bh(&(queue->lock), &irqL); */
++	_exit_critical(&queue->lock, &irqL);
++
++
++	return obj;
++}
++
++u32	rtw_init_cmd_priv(struct cmd_priv *pcmdpriv)
++{
++	u32	res;
++	res = _rtw_init_cmd_priv(pcmdpriv);
++	return res;
++}
++
++u32	rtw_init_evt_priv(struct	evt_priv *pevtpriv)
++{
++	int	res;
++	res = _rtw_init_evt_priv(pevtpriv);
++	return res;
++}
++
++void rtw_free_evt_priv(struct	evt_priv *pevtpriv)
++{
++	_rtw_free_evt_priv(pevtpriv);
++}
++
++void rtw_free_cmd_priv(struct	cmd_priv *pcmdpriv)
++{
++	_rtw_free_cmd_priv(pcmdpriv);
++}
++
++int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj);
++int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj)
++{
++	u8 bAllow = _FALSE; /* set to _TRUE to allow enqueuing cmd when hw_init_completed is _FALSE */
++
++#ifdef SUPPORT_HW_RFOFF_DETECTED
++	/* To decide allow or not */
++	if ((adapter_to_pwrctl(pcmdpriv->padapter)->bHWPwrPindetect)
++	    && (!pcmdpriv->padapter->registrypriv.usbss_enable)
++	   ) {
++		if (cmd_obj->cmdcode == CMD_SET_DRV_EXTRA) {
++			struct drvextra_cmd_parm	*pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf;
++			if (pdrvextra_cmd_parm->ec_id == POWER_SAVING_CTRL_WK_CID) {
++				/* RTW_INFO("==>enqueue POWER_SAVING_CTRL_WK_CID\n"); */
++				bAllow = _TRUE;
++			}
++		}
++	}
++#endif
++
++	if (cmd_obj->cmdcode == CMD_SET_CHANPLAN)
++		bAllow = _TRUE;
++
++	if (cmd_obj->no_io)
++		bAllow = _TRUE;
++
++	if ((!rtw_is_hw_init_completed(pcmdpriv->padapter) && (bAllow == _FALSE))
++	    || ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _FALSE	/* com_thread not running */
++	   ) {
++		if (DBG_CMD_EXECUTE)
++			RTW_INFO(ADPT_FMT" drop "CMD_FMT" hw_init_completed:%u, cmdthd_running:%u\n", ADPT_ARG(cmd_obj->padapter)
++				, CMD_ARG(cmd_obj), rtw_get_hw_init_completed(cmd_obj->padapter), ATOMIC_READ(&pcmdpriv->cmdthd_running));
++		if (0)
++			rtw_warn_on(1);
++
++		return _FAIL;
++	}
++	return _SUCCESS;
++}
++
++
++
++u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj)
++{
++	int res = _FAIL;
++	PADAPTER padapter = pcmdpriv->padapter;
++
++
++	if (cmd_obj == NULL)
++		goto exit;
++
++	cmd_obj->padapter = padapter;
++
++#ifdef CONFIG_CONCURRENT_MODE
++	/* change pcmdpriv to primary's pcmdpriv */
++	if (!is_primary_adapter(padapter))
++		pcmdpriv = &(GET_PRIMARY_ADAPTER(padapter)->cmdpriv);
++#endif
++
++	res = rtw_cmd_filter(pcmdpriv, cmd_obj);
++	if ((_FAIL == res) || (cmd_obj->cmdsz > MAX_CMDSZ)) {
++		if (cmd_obj->cmdsz > MAX_CMDSZ) {
++			RTW_INFO("%s failed due to obj->cmdsz(%d) > MAX_CMDSZ(%d)\n", __func__, cmd_obj->cmdsz, MAX_CMDSZ);
++			rtw_warn_on(1);
++		}
++
++		if (cmd_obj->cmdcode == CMD_SET_DRV_EXTRA) {
++			struct drvextra_cmd_parm *extra_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf;
++
++			if (extra_parm->pbuf && extra_parm->size > 0)
++				rtw_mfree(extra_parm->pbuf, extra_parm->size);
++		}
++		rtw_free_cmd_obj(cmd_obj);
++		goto exit;
++	}
++
++	res = _rtw_enqueue_cmd(&pcmdpriv->cmd_queue, cmd_obj, 0);
++
++	if (res == _SUCCESS)
++		_rtw_up_sema(&pcmdpriv->cmd_queue_sema);
++
++exit:
++
++
++	return res;
++}
++
++struct	cmd_obj	*rtw_dequeue_cmd(struct cmd_priv *pcmdpriv)
++{
++	struct cmd_obj *cmd_obj;
++
++
++	cmd_obj = _rtw_dequeue_cmd(&pcmdpriv->cmd_queue);
++
++	return cmd_obj;
++}
++
++void rtw_cmd_clr_isr(struct	cmd_priv *pcmdpriv)
++{
++	pcmdpriv->cmd_done_cnt++;
++	/* _rtw_up_sema(&(pcmdpriv->cmd_done_sema)); */
++}
++
++void rtw_free_cmd_obj(struct cmd_obj *pcmd)
++{
++	if (pcmd->parmbuf != NULL) {
++		/* free parmbuf in cmd_obj */
++		rtw_mfree((unsigned char *)pcmd->parmbuf, pcmd->cmdsz);
++	}
++	if (pcmd->rsp != NULL) {
++		if (pcmd->rspsz != 0) {
++			/* free rsp in cmd_obj */
++			rtw_mfree((unsigned char *)pcmd->rsp, pcmd->rspsz);
++		}
++	}
++
++	/* free cmd_obj */
++	rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj));
++}
++
++
++void rtw_stop_cmd_thread(_adapter *adapter)
++{
++	if (adapter->cmdThread) {
++		_rtw_up_sema(&adapter->cmdpriv.cmd_queue_sema);
++		rtw_thread_stop(adapter->cmdThread);
++		adapter->cmdThread = NULL;
++	}
++}
++
++thread_return rtw_cmd_thread(thread_context context)
++{
++	u8 ret;
++	struct cmd_obj *pcmd;
++	u8 *pcmdbuf, *prspbuf;
++	systime cmd_start_time;
++	u32 cmd_process_time;
++	u8(*cmd_hdl)(_adapter *padapter, u8 *pbuf);
++	void (*pcmd_callback)(_adapter *dev, struct cmd_obj *pcmd);
++	PADAPTER padapter = (PADAPTER)context;
++	struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
++	struct drvextra_cmd_parm *extra_parm = NULL;
++	_irqL irqL;
++
++	thread_enter("RTW_CMD_THREAD");
++
++	pcmdbuf = pcmdpriv->cmd_buf;
++	prspbuf = pcmdpriv->rsp_buf;
++	ATOMIC_SET(&(pcmdpriv->cmdthd_running), _TRUE);
++	_rtw_up_sema(&pcmdpriv->start_cmdthread_sema);
++
++
++	while (1) {
++		if (_rtw_down_sema(&pcmdpriv->cmd_queue_sema) == _FAIL) {
++			RTW_PRINT(FUNC_ADPT_FMT" _rtw_down_sema(&pcmdpriv->cmd_queue_sema) return _FAIL, break\n", FUNC_ADPT_ARG(padapter));
++			break;
++		}
++
++		if (RTW_CANNOT_RUN(padapter)) {
++			RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n",
++				FUNC_ADPT_ARG(padapter),
++				rtw_is_drv_stopped(padapter) ? "True" : "False",
++				rtw_is_surprise_removed(padapter) ? "True" : "False");
++			break;
++		}
++
++		_enter_critical(&pcmdpriv->cmd_queue.lock, &irqL);
++		if (rtw_is_list_empty(&(pcmdpriv->cmd_queue.queue))) {
++			/* RTW_INFO("%s: cmd queue is empty!\n", __func__); */
++			_exit_critical(&pcmdpriv->cmd_queue.lock, &irqL);
++			continue;
++		}
++		_exit_critical(&pcmdpriv->cmd_queue.lock, &irqL);
++
++_next:
++		if (RTW_CANNOT_RUN(padapter)) {
++			RTW_PRINT("%s: DriverStopped(%s) SurpriseRemoved(%s) break at line %d\n",
++				  __func__
++				, rtw_is_drv_stopped(padapter) ? "True" : "False"
++				, rtw_is_surprise_removed(padapter) ? "True" : "False"
++				  , __LINE__);
++			break;
++		}
++
++		pcmd = rtw_dequeue_cmd(pcmdpriv);
++		if (!pcmd) {
++#ifdef CONFIG_LPS_LCLK
++			rtw_unregister_cmd_alive(padapter);
++#endif
++			continue;
++		}
++
++		cmd_start_time = rtw_get_current_time();
++		pcmdpriv->cmd_issued_cnt++;
++
++		if (pcmd->cmdsz > MAX_CMDSZ) {
++			RTW_ERR("%s cmdsz:%d > MAX_CMDSZ:%d\n", __func__, pcmd->cmdsz, MAX_CMDSZ);
++			pcmd->res = H2C_PARAMETERS_ERROR;
++			goto post_process;
++		}
++
++		if (pcmd->cmdcode >= (sizeof(wlancmds) / sizeof(struct rtw_cmd))) {
++			RTW_ERR("%s undefined cmdcode:%d\n", __func__, pcmd->cmdcode);
++			pcmd->res = H2C_PARAMETERS_ERROR;
++			goto post_process;
++		}
++
++		cmd_hdl = wlancmds[pcmd->cmdcode].cmd_hdl;
++		if (!cmd_hdl) {
++			RTW_ERR("%s no cmd_hdl for cmdcode:%d\n", __func__, pcmd->cmdcode);
++			pcmd->res = H2C_PARAMETERS_ERROR;
++			goto post_process;
++		}
++
++		if (_FAIL == rtw_cmd_filter(pcmdpriv, pcmd)) {
++			pcmd->res = H2C_DROPPED;
++			if (pcmd->cmdcode == CMD_SET_DRV_EXTRA) {
++				extra_parm = (struct drvextra_cmd_parm *)pcmd->parmbuf;
++				if (extra_parm && extra_parm->pbuf && extra_parm->size > 0)
++					rtw_mfree(extra_parm->pbuf, extra_parm->size);
++			}
++			#if CONFIG_DFS
++			else if (pcmd->cmdcode == CMD_SET_CHANSWITCH)
++				adapter_to_rfctl(padapter)->csa_ch = 0;
++			#endif
++			goto post_process;
++		}
++
++#ifdef CONFIG_LPS_LCLK
++		if (pcmd->no_io)
++			rtw_unregister_cmd_alive(padapter);
++		else {
++			if (rtw_register_cmd_alive(padapter) != _SUCCESS) {
++				if (DBG_CMD_EXECUTE)
++					RTW_PRINT("%s: wait to leave LPS_LCLK\n", __func__);
++
++				pcmd->res = H2C_ENQ_HEAD;
++				ret = _rtw_enqueue_cmd(&pcmdpriv->cmd_queue, pcmd, 1);
++				if (ret == _SUCCESS) {
++					if (DBG_CMD_EXECUTE)
++						RTW_INFO(ADPT_FMT" "CMD_FMT" ENQ_HEAD\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd));
++					continue;
++				}
++
++				RTW_INFO(ADPT_FMT" "CMD_FMT" ENQ_HEAD_FAIL\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd));
++				pcmd->res = H2C_ENQ_HEAD_FAIL;
++				rtw_warn_on(1);
++			}
++		}
++#endif /* CONFIG_LPS_LCLK */
++
++		if (DBG_CMD_EXECUTE)
++			RTW_INFO(ADPT_FMT" "CMD_FMT" %sexecute\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd)
++				, pcmd->res == H2C_ENQ_HEAD ? "ENQ_HEAD " : (pcmd->res == H2C_ENQ_HEAD_FAIL ? "ENQ_HEAD_FAIL " : ""));
++
++		_rtw_memcpy(pcmdbuf, pcmd->parmbuf, pcmd->cmdsz);
++		ret = cmd_hdl(pcmd->padapter, pcmdbuf);
++		pcmd->res = ret;
++
++		pcmdpriv->cmd_seq++;
++
++post_process:
++
++		_enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);
++		if (pcmd->sctx) {
++			if (0)
++				RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n", FUNC_ADPT_ARG(pcmd->padapter));
++			if (pcmd->res == H2C_SUCCESS)
++				rtw_sctx_done(&pcmd->sctx);
++			else
++				rtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_ERROR);
++		}
++		_exit_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);
++
++		cmd_process_time = rtw_get_passing_time_ms(cmd_start_time);
++		if (cmd_process_time > 1000) {
++			RTW_INFO(ADPT_FMT" "CMD_FMT" process_time=%d\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd), cmd_process_time);
++			if (0)
++				rtw_warn_on(1);
++		}
++
++		/* call callback function for post-processed */
++		if (pcmd->cmdcode < (sizeof(wlancmds) / sizeof(struct rtw_cmd)))
++			pcmd_callback = wlancmds[pcmd->cmdcode].callback;
++		else
++			pcmd_callback = NULL;
++
++		if (pcmd_callback == NULL) {
++			rtw_free_cmd_obj(pcmd);
++		} else {
++			/* todo: !!! fill rsp_buf to pcmd->rsp if (pcmd->rsp!=NULL) */
++			pcmd_callback(pcmd->padapter, pcmd);/* need conider that free cmd_obj in rtw_cmd_callback */
++		}
++
++		flush_signals_thread();
++
++		goto _next;
++
++	}
++
++#ifdef CONFIG_LPS_LCLK
++	rtw_unregister_cmd_alive(padapter);
++#endif
++
++	/* to avoid enqueue cmd after free all cmd_obj */
++	ATOMIC_SET(&(pcmdpriv->cmdthd_running), _FALSE);
++
++	/* free all cmd_obj resources */
++	do {
++		pcmd = rtw_dequeue_cmd(pcmdpriv);
++		if (pcmd == NULL)
++			break;
++
++		if (0)
++			RTW_INFO("%s: leaving... drop "CMD_FMT"\n", __func__, CMD_ARG(pcmd));
++
++		if (pcmd->cmdcode == CMD_SET_DRV_EXTRA) {
++			extra_parm = (struct drvextra_cmd_parm *)pcmd->parmbuf;
++			if (extra_parm->pbuf && extra_parm->size > 0)
++				rtw_mfree(extra_parm->pbuf, extra_parm->size);
++		}
++		#if CONFIG_DFS
++		else if (pcmd->cmdcode == CMD_SET_CHANSWITCH)
++			adapter_to_rfctl(padapter)->csa_ch = 0;
++		#endif
++
++		_enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);
++		if (pcmd->sctx) {
++			if (0)
++				RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n", FUNC_ADPT_ARG(pcmd->padapter));
++			rtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_DROP);
++		}
++		_exit_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);
++
++		rtw_free_cmd_obj(pcmd);
++	} while (1);
++
++	RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(padapter));
++
++	rtw_thread_wait_stop();
++
++	return 0;
++}
++
++
++#ifdef CONFIG_EVENT_THREAD_MODE
++u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj)
++{
++	_irqL irqL;
++	int	res;
++	_queue *queue = &pevtpriv->evt_queue;
++
++
++	res = _SUCCESS;
++
++	if (obj == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	_enter_critical_bh(&queue->lock, &irqL);
++
++	rtw_list_insert_tail(&obj->list, &queue->queue);
++
++	_exit_critical_bh(&queue->lock, &irqL);
++
++	/* rtw_evt_notify_isr(pevtpriv); */
++
++exit:
++
++
++	return res;
++}
++
++struct evt_obj *rtw_dequeue_evt(_queue *queue)
++{
++	_irqL irqL;
++	struct	evt_obj	*pevtobj;
++
++
++	_enter_critical_bh(&queue->lock, &irqL);
++
++	if (rtw_is_list_empty(&(queue->queue)))
++		pevtobj = NULL;
++	else {
++		pevtobj = LIST_CONTAINOR(get_next(&(queue->queue)), struct evt_obj, list);
++		rtw_list_delete(&pevtobj->list);
++	}
++
++	_exit_critical_bh(&queue->lock, &irqL);
++
++
++	return pevtobj;
++}
++
++void rtw_free_evt_obj(struct evt_obj *pevtobj)
++{
++
++	if (pevtobj->parmbuf)
++		rtw_mfree((unsigned char *)pevtobj->parmbuf, pevtobj->evtsz);
++
++	rtw_mfree((unsigned char *)pevtobj, sizeof(struct evt_obj));
++
++}
++
++void rtw_evt_notify_isr(struct evt_priv *pevtpriv)
++{
++	pevtpriv->evt_done_cnt++;
++	_rtw_up_sema(&(pevtpriv->evt_notify));
++}
++#endif
++
++void rtw_init_sitesurvey_parm(_adapter *padapter, struct sitesurvey_parm *pparm)
++{
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++
++	_rtw_memset(pparm, 0, sizeof(struct sitesurvey_parm));
++	pparm->scan_mode = pmlmepriv->scan_mode;
++}
++
++/*
++rtw_sitesurvey_cmd(~)
++	### NOTE:#### (!!!!)
++	MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock
++*/
++u8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm)
++{
++	u8 res = _FAIL;
++	struct cmd_obj		*ph2c;
++	struct sitesurvey_parm	*psurveyPara;
++	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++
++#ifdef CONFIG_LPS
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++		rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SCAN, 0);
++#endif
++
++#ifdef CONFIG_P2P_PS
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++		p2p_ps_wk_cmd(padapter, P2P_PS_SCAN, 1);
++#endif /* CONFIG_P2P_PS */
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL)
++		return _FAIL;
++
++	psurveyPara = (struct sitesurvey_parm *)rtw_zmalloc(sizeof(struct sitesurvey_parm));
++	if (psurveyPara == NULL) {
++		rtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj));
++		return _FAIL;
++	}
++
++	if (pparm)
++		_rtw_memcpy(psurveyPara, pparm, sizeof(struct sitesurvey_parm));
++	else
++		psurveyPara->scan_mode = pmlmepriv->scan_mode;
++
++	rtw_free_network_queue(padapter, _FALSE);
++
++	init_h2fwcmd_w_parm_no_rsp(ph2c, psurveyPara, CMD_SITE_SURVEY);
++
++	set_fwstate(pmlmepriv, WIFI_UNDER_SURVEY);
++
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++	if (res == _SUCCESS) {
++		u32 scan_timeout_ms;
++
++		pmlmepriv->scan_start_time = rtw_get_current_time();
++		scan_timeout_ms = rtw_scan_timeout_decision(padapter);
++		mlme_set_scan_to_timer(pmlmepriv,scan_timeout_ms);
++
++		rtw_led_control(padapter, LED_CTL_SITE_SURVEY);
++	} else
++		_clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY);
++
++
++	return res;
++}
++
++void rtw_readtssi_cmdrsp_callback(_adapter	*padapter,  struct cmd_obj *pcmd)
++{
++
++	rtw_mfree((unsigned char *) pcmd->parmbuf, pcmd->cmdsz);
++	rtw_mfree((unsigned char *) pcmd, sizeof(struct cmd_obj));
++
++#ifdef CONFIG_MP_INCLUDED
++	if (padapter->registrypriv.mp_mode == 1)
++		padapter->mppriv.workparam.bcompleted = _TRUE;
++#endif
++
++}
++
++static u8 rtw_createbss_cmd(_adapter  *adapter, int flags, bool adhoc
++	, u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset)
++{
++	struct cmd_obj *cmdobj;
++	struct createbss_parm *parm;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++	struct submit_ctx sctx;
++	u8 res = _SUCCESS;
++
++	if (req_ch > 0 && req_bw >= 0 && req_offset >= 0) {
++		if (!rtw_chset_is_chbw_valid(adapter_to_chset(adapter), req_ch, req_bw, req_offset, 0, 0)) {
++			res = _FAIL;
++			goto exit;
++		}
++	}
++
++	/* prepare cmd parameter */
++	parm = (struct createbss_parm *)rtw_zmalloc(sizeof(*parm));
++	if (parm == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	if (adhoc) {
++		/* for now, adhoc doesn't support ch,bw,offset request */
++		parm->adhoc = 1;
++	} else {
++		parm->adhoc = 0;
++		parm->ifbmp = ifbmp;
++		parm->excl_ifbmp = excl_ifbmp;
++		parm->req_ch = req_ch;
++		parm->req_bw = req_bw;
++		parm->req_offset = req_offset;
++	}
++
++	if (flags & RTW_CMDF_DIRECTLY) {
++		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
++		if (H2C_SUCCESS != createbss_hdl(adapter, (u8 *)parm))
++			res = _FAIL;
++		rtw_mfree((u8 *)parm, sizeof(*parm));
++	} else {
++		/* need enqueue, prepare cmd_obj and enqueue */
++		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
++		if (cmdobj == NULL) {
++			res = _FAIL;
++			rtw_mfree((u8 *)parm, sizeof(*parm));
++			goto exit;
++		}
++
++		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_CREATE_BSS);
++
++		if (flags & RTW_CMDF_WAIT_ACK) {
++			cmdobj->sctx = &sctx;
++			rtw_sctx_init(&sctx, 2000);
++		}
++
++		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
++
++		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
++			rtw_sctx_wait(&sctx, __func__);
++			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status == RTW_SCTX_SUBMITTED)
++				cmdobj->sctx = NULL;
++			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++		}
++	}
++
++exit:
++	return res;
++}
++
++inline u8 rtw_create_ibss_cmd(_adapter *adapter, int flags)
++{
++	return rtw_createbss_cmd(adapter, flags
++		, 1
++		, 0, 0
++		, 0, REQ_BW_NONE, REQ_OFFSET_NONE /* for now, adhoc doesn't support ch,bw,offset request */
++	);
++}
++
++inline u8 rtw_startbss_cmd(_adapter *adapter, int flags)
++{
++	return rtw_createbss_cmd(adapter, flags
++		, 0
++		, BIT(adapter->iface_id), 0
++		, 0, REQ_BW_NONE, REQ_OFFSET_NONE /* excute entire AP setup cmd */
++	);
++}
++
++inline u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags
++	, u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset)
++{
++	return rtw_createbss_cmd(adapter, flags
++		, 0
++		, ifbmp, excl_ifbmp
++		, req_ch, req_bw, req_offset
++	);
++}
++
++u8 rtw_joinbss_cmd(_adapter  *padapter, struct wlan_network *pnetwork)
++{
++	u8	*auth, res = _SUCCESS;
++	uint	t_len = 0;
++	WLAN_BSSID_EX		*psecnetwork;
++	struct cmd_obj		*pcmd;
++	struct cmd_priv		*pcmdpriv = &padapter->cmdpriv;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
++	struct security_priv	*psecuritypriv = &padapter->securitypriv;
++	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
++#ifdef CONFIG_80211N_HT
++	struct ht_priv			*phtpriv = &pmlmepriv->htpriv;
++#endif /* CONFIG_80211N_HT */
++#ifdef CONFIG_80211AC_VHT
++	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
++#endif /* CONFIG_80211AC_VHT */
++	NDIS_802_11_NETWORK_INFRASTRUCTURE ndis_network_mode = pnetwork->network.InfrastructureMode;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	u32 tmp_len;
++	u8 *ptmp = NULL;
++
++	rtw_led_control(padapter, LED_CTL_START_TO_LINK);
++
++	pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (pcmd == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++#if 0
++	/*  for IEs is pointer */
++	t_len = sizeof(u32) + sizeof(NDIS_802_11_MAC_ADDRESS) + 2 +
++		sizeof(NDIS_802_11_SSID) + sizeof(u32) +
++		sizeof(NDIS_802_11_RSSI) + sizeof(NDIS_802_11_NETWORK_TYPE) +
++		sizeof(NDIS_802_11_CONFIGURATION) +
++		sizeof(NDIS_802_11_NETWORK_INFRASTRUCTURE) +
++		sizeof(NDIS_802_11_RATES_EX) + sizeof(WLAN_PHY_INFO) + sizeof(u32) + MAX_IE_SZ;
++#endif
++	/* for IEs is fix buf size */
++	t_len = sizeof(WLAN_BSSID_EX);
++
++
++	/* for hidden ap to set fw_state here */
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) != _TRUE) {
++		switch (ndis_network_mode) {
++		case Ndis802_11IBSS:
++			set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
++			break;
++
++		case Ndis802_11Infrastructure:
++			set_fwstate(pmlmepriv, WIFI_STATION_STATE);
++			break;
++
++		default:
++			rtw_warn_on(1);
++			break;
++		}
++	}
++
++	pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->network.IEs, pnetwork->network.IELength);
++
++#ifdef CONFIG_80211AC_VHT
++	/* save AP beamform_cap info for BCM IOT issue */
++	if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM)
++		get_vht_bf_cap(pnetwork->network.IEs,
++			pnetwork->network.IELength,
++			&pvhtpriv->ap_bf_cap);
++#endif
++	/*
++		Modified by Arvin 2015/05/13
++		Solution for allocating a new WLAN_BSSID_EX to avoid race condition issue between disconnect and joinbss
++	*/
++	psecnetwork = (WLAN_BSSID_EX *)rtw_zmalloc(sizeof(WLAN_BSSID_EX));
++	if (psecnetwork == NULL) {
++		if (pcmd != NULL)
++			rtw_mfree((unsigned char *)pcmd, sizeof(struct	cmd_obj));
++
++		res = _FAIL;
++
++
++		goto exit;
++	}
++
++	_rtw_memset(psecnetwork, 0, t_len);
++
++	_rtw_memcpy(psecnetwork, &pnetwork->network, get_WLAN_BSSID_EX_sz(&pnetwork->network));
++
++	auth = &psecuritypriv->authenticator_ie[0];
++	psecuritypriv->authenticator_ie[0] = (unsigned char)psecnetwork->IELength;
++
++	if ((psecnetwork->IELength - 12) < (256 - 1))
++		_rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], psecnetwork->IELength - 12);
++	else
++		_rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], (256 - 1));
++
++	psecnetwork->IELength = 0;
++	/* Added by Albert 2009/02/18 */
++	/* If the the driver wants to use the bssid to create the connection. */
++	/* If not,  we have to copy the connecting AP's MAC address to it so that */
++	/* the driver just has the bssid information for PMKIDList searching. */
++
++	if (pmlmepriv->assoc_by_bssid == _FALSE)
++		_rtw_memcpy(&pmlmepriv->assoc_bssid[0], &pnetwork->network.MacAddress[0], ETH_ALEN);
++
++	/* copy fixed ie */
++	_rtw_memcpy(psecnetwork->IEs, pnetwork->network.IEs, 12);
++	psecnetwork->IELength = 12;
++
++	psecnetwork->IELength += rtw_restruct_sec_ie(padapter, psecnetwork->IEs + psecnetwork->IELength);
++
++
++	pqospriv->qos_option = 0;
++
++	if (pregistrypriv->wmm_enable) {
++#ifdef CONFIG_WMMPS_STA	
++		rtw_uapsd_use_default_setting(padapter);
++#endif /* CONFIG_WMMPS_STA */		
++		tmp_len = rtw_restruct_wmm_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength, psecnetwork->IELength);
++
++		if (psecnetwork->IELength != tmp_len) {
++			psecnetwork->IELength = tmp_len;
++			pqospriv->qos_option = 1; /* There is WMM IE in this corresp. beacon */
++		} else {
++			pqospriv->qos_option = 0;/* There is no WMM IE in this corresp. beacon */
++		}
++	}
++
++#ifdef CONFIG_80211N_HT
++	phtpriv->ht_option = _FALSE;
++	if (pregistrypriv->ht_enable && is_supported_ht(pregistrypriv->wireless_mode)) {
++		ptmp = rtw_get_ie(&pnetwork->network.IEs[12], _HT_CAPABILITY_IE_, &tmp_len, pnetwork->network.IELength - 12);
++		if (ptmp && tmp_len > 0) {
++			/*	Added by Albert 2010/06/23 */
++			/*	For the WEP mode, we will use the bg mode to do the connection to avoid some IOT issue. */
++			/*	Especially for Realtek 8192u SoftAP. */
++			if ((padapter->securitypriv.dot11PrivacyAlgrthm != _WEP40_) &&
++			    (padapter->securitypriv.dot11PrivacyAlgrthm != _WEP104_) &&
++			    (padapter->securitypriv.dot11PrivacyAlgrthm != _TKIP_)) {
++				rtw_ht_use_default_setting(padapter);
++
++				/* rtw_restructure_ht_ie */
++				rtw_restructure_ht_ie(padapter, &pnetwork->network.IEs[12], &psecnetwork->IEs[0],
++					pnetwork->network.IELength - 12, &psecnetwork->IELength,
++					pnetwork->network.Configuration.DSConfig);
++			}
++		}
++	}
++
++#ifdef CONFIG_80211AC_VHT
++	pvhtpriv->vht_option = _FALSE;
++	if (phtpriv->ht_option
++		&& REGSTY_IS_11AC_ENABLE(pregistrypriv)
++		&& is_supported_vht(pregistrypriv->wireless_mode)
++		&& (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
++		&& ((padapter->registrypriv.wifi_spec == 0) || (pnetwork->network.Configuration.DSConfig > 14))
++	) {
++		rtw_restructure_vht_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0],
++			pnetwork->network.IELength, &psecnetwork->IELength);
++	}
++#endif
++#endif /* CONFIG_80211N_HT */
++
++	rtw_append_exented_cap(padapter, &psecnetwork->IEs[0], &psecnetwork->IELength);
++
++#ifdef CONFIG_RTW_80211R
++	rtw_ft_validate_akm_type(padapter, pnetwork);
++#endif
++
++#if 0
++	psecuritypriv->supplicant_ie[0] = (u8)psecnetwork->IELength;
++
++	if (psecnetwork->IELength < (256 - 1))
++		_rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], psecnetwork->IELength);
++	else
++		_rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], (256 - 1));
++#endif
++
++	pcmd->cmdsz = sizeof(WLAN_BSSID_EX);
++
++	_rtw_init_listhead(&pcmd->list);
++	pcmd->cmdcode = CMD_JOINBSS;/* _JoinBss_CMD_ */
++	pcmd->parmbuf = (unsigned char *)psecnetwork;
++	pcmd->rsp = NULL;
++	pcmd->rspsz = 0;
++
++	res = rtw_enqueue_cmd(pcmdpriv, pcmd);
++
++exit:
++
++
++	return res;
++}
++
++u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags) /* for sta_mode */
++{
++	struct cmd_obj *cmdobj = NULL;
++	struct disconnect_parm *param = NULL;
++	struct cmd_priv *cmdpriv = &padapter->cmdpriv;
++	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++	struct submit_ctx sctx;
++	u8 res = _SUCCESS;
++
++	/* prepare cmd parameter */
++	param = (struct disconnect_parm *)rtw_zmalloc(sizeof(*param));
++	if (param == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++	param->deauth_timeout_ms = deauth_timeout_ms;
++
++	if (flags & RTW_CMDF_DIRECTLY) {
++		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
++		if (disconnect_hdl(padapter, (u8 *)param) != H2C_SUCCESS)
++			res = _FAIL;
++		rtw_mfree((u8 *)param, sizeof(*param));
++
++	} else {
++		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
++		if (cmdobj == NULL) {
++			res = _FAIL;
++			rtw_mfree((u8 *)param, sizeof(*param));
++			goto exit;
++		}
++		init_h2fwcmd_w_parm_no_rsp(cmdobj, param, CMD_DISCONNECT);
++		if (flags & RTW_CMDF_WAIT_ACK) {
++			cmdobj->sctx = &sctx;
++			rtw_sctx_init(&sctx, 2000);
++		}
++		res = rtw_enqueue_cmd(cmdpriv, cmdobj);
++		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
++			rtw_sctx_wait(&sctx, __func__);
++			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status == RTW_SCTX_SUBMITTED)
++				cmdobj->sctx = NULL;
++			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++		}
++	}
++
++exit:
++
++
++	return res;
++}
++
++
++u8 rtw_stop_ap_cmd(_adapter  *adapter, u8 flags)
++{
++#ifdef CONFIG_AP_MODE
++	struct cmd_obj *cmdobj;
++	struct drvextra_cmd_parm *parm;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++	struct submit_ctx sctx;
++	u8 res = _SUCCESS;
++
++	if (flags & RTW_CMDF_DIRECTLY) {
++		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
++		if (H2C_SUCCESS != stop_ap_hdl(adapter))
++			res = _FAIL;
++	} else {
++		parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++		if (parm == NULL) {
++			res = _FAIL;
++			goto exit;
++		}
++
++		parm->ec_id = STOP_AP_WK_CID;
++		parm->type = 0;
++		parm->size = 0;
++		parm->pbuf = NULL;
++		
++		/* need enqueue, prepare cmd_obj and enqueue */
++		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
++		if (cmdobj == NULL) {
++			res = _FAIL;
++			goto exit;
++		}
++
++		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
++
++		if (flags & RTW_CMDF_WAIT_ACK) {
++			cmdobj->sctx = &sctx;
++			rtw_sctx_init(&sctx, 2000);
++		}
++
++		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
++
++		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
++			rtw_sctx_wait(&sctx, __func__);
++			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status == RTW_SCTX_SUBMITTED)
++				cmdobj->sctx = NULL;
++			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++		}
++	}
++
++exit:
++	return res;
++#endif
++}
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++u8 rtw_tx_control_cmd(_adapter *adapter)
++{
++	struct cmd_obj		*ph2c;
++	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++
++	u8 res = _SUCCESS;
++	
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL){
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm->ec_id = TBTX_CONTROL_TX_WK_CID;
++	pdrvextra_cmd_parm->type = 0;
++	pdrvextra_cmd_parm->size = 0;
++	pdrvextra_cmd_parm->pbuf = NULL;
++	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++	return res;	
++}
++#endif
++
++u8 rtw_setopmode_cmd(_adapter  *adapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags)
++{
++	struct cmd_obj *cmdobj;
++	struct setopmode_parm *parm;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++	struct submit_ctx sctx;
++	u8 res = _SUCCESS;
++
++	/* prepare cmd parameter */
++	parm = (struct setopmode_parm *)rtw_zmalloc(sizeof(*parm));
++	if (parm == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++	parm->mode = (u8)networktype;
++
++	if (flags & RTW_CMDF_DIRECTLY) {
++		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
++		if (H2C_SUCCESS != setopmode_hdl(adapter, (u8 *)parm))
++			res = _FAIL;
++		rtw_mfree((u8 *)parm, sizeof(*parm));
++	} else {
++		/* need enqueue, prepare cmd_obj and enqueue */
++		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
++		if (cmdobj == NULL) {
++			res = _FAIL;
++			rtw_mfree((u8 *)parm, sizeof(*parm));
++			goto exit;
++		}
++
++		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_OPMODE);
++
++		if (flags & RTW_CMDF_WAIT_ACK) {
++			cmdobj->sctx = &sctx;
++			rtw_sctx_init(&sctx, 2000);
++		}
++
++		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
++
++		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
++			rtw_sctx_wait(&sctx, __func__);
++			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status == RTW_SCTX_SUBMITTED)
++				cmdobj->sctx = NULL;
++			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++		}
++	}
++
++exit:
++	return res;
++}
++
++u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool enqueue)
++{
++	struct cmd_obj			*ph2c;
++	struct set_stakey_parm	*psetstakey_para;
++	struct cmd_priv			*pcmdpriv = &padapter->cmdpriv;
++	struct set_stakey_rsp		*psetstakey_rsp = NULL;
++
++	struct mlme_priv			*pmlmepriv = &padapter->mlmepriv;
++	struct security_priv		*psecuritypriv = &padapter->securitypriv;
++	u8 key_len =16;
++	u8	res = _SUCCESS;
++
++
++	psetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm));
++	if (psetstakey_para == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	_rtw_memcpy(psetstakey_para->addr, sta->cmn.mac_addr, ETH_ALEN);
++
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
++		psetstakey_para->algorithm = (unsigned char) psecuritypriv->dot11PrivacyAlgrthm;
++	else
++		GET_ENCRY_ALGO(psecuritypriv, sta, psetstakey_para->algorithm, _FALSE);
++
++	if ((psetstakey_para->algorithm == _GCMP_256_) || (psetstakey_para->algorithm == _CCMP_256_)) 
++		key_len = 32;
++
++	if (key_type == GROUP_KEY) {
++		_rtw_memcpy(&psetstakey_para->key, &psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, key_len);
++		psetstakey_para->gk = 1;
++	} else if (key_type == UNICAST_KEY)
++		_rtw_memcpy(&psetstakey_para->key, &sta->dot118021x_UncstKey, key_len);
++#ifdef CONFIG_TDLS
++	else if (key_type == TDLS_KEY) {
++		_rtw_memcpy(&psetstakey_para->key, sta->tpk.tk, key_len);
++		psetstakey_para->algorithm = (u8)sta->dot118021XPrivacy;
++	}
++#endif /* CONFIG_TDLS */
++
++	/* jeff: set this becasue at least sw key is ready */
++	padapter->securitypriv.busetkipkey = _TRUE;
++
++	if (enqueue) {
++		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++		if (ph2c == NULL) {
++			rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));
++			res = _FAIL;
++			goto exit;
++		}
++
++		psetstakey_rsp = (struct set_stakey_rsp *)rtw_zmalloc(sizeof(struct set_stakey_rsp));
++		if (psetstakey_rsp == NULL) {
++			rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
++			rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));
++			res = _FAIL;
++			goto exit;
++		}
++
++		init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, CMD_SET_STAKEY);
++		ph2c->rsp = (u8 *) psetstakey_rsp;
++		ph2c->rspsz = sizeof(struct set_stakey_rsp);
++		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++	} else {
++		set_stakey_hdl(padapter, (u8 *)psetstakey_para);
++		rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));
++	}
++exit:
++
++
++	return res;
++}
++
++u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue)
++{
++	struct cmd_obj			*ph2c;
++	struct set_stakey_parm	*psetstakey_para;
++	struct cmd_priv			*pcmdpriv = &padapter->cmdpriv;
++	struct set_stakey_rsp		*psetstakey_rsp = NULL;
++	s16 cam_id = 0;
++	u8	res = _SUCCESS;
++
++	if (!sta) {
++		RTW_ERR("%s sta == NULL\n", __func__);
++		goto exit;
++	}
++
++	if (!enqueue) {
++		while ((cam_id = rtw_camid_search(padapter, sta->cmn.mac_addr, -1, -1)) >= 0) {
++			RTW_PRINT("clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(sta->cmn.mac_addr), cam_id);
++			clear_cam_entry(padapter, cam_id);
++			rtw_camid_free(padapter, cam_id);
++		}
++	} else {
++		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++		if (ph2c == NULL) {
++			res = _FAIL;
++			goto exit;
++		}
++
++		psetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm));
++		if (psetstakey_para == NULL) {
++			rtw_mfree((u8 *) ph2c, sizeof(struct	cmd_obj));
++			res = _FAIL;
++			goto exit;
++		}
++
++		psetstakey_rsp = (struct set_stakey_rsp *)rtw_zmalloc(sizeof(struct set_stakey_rsp));
++		if (psetstakey_rsp == NULL) {
++			rtw_mfree((u8 *) ph2c, sizeof(struct	cmd_obj));
++			rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));
++			res = _FAIL;
++			goto exit;
++		}
++
++		init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, CMD_SET_STAKEY);
++		ph2c->rsp = (u8 *) psetstakey_rsp;
++		ph2c->rspsz = sizeof(struct set_stakey_rsp);
++
++		_rtw_memcpy(psetstakey_para->addr, sta->cmn.mac_addr, ETH_ALEN);
++
++		psetstakey_para->algorithm = _NO_PRIVACY_;
++
++		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++	}
++
++exit:
++
++
++	return res;
++}
++
++u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr)
++{
++	struct cmd_priv		*pcmdpriv = &padapter->cmdpriv;
++	struct cmd_obj		*ph2c;
++	struct addBaReq_parm	*paddbareq_parm;
++
++	u8	res = _SUCCESS;
++
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	paddbareq_parm = (struct addBaReq_parm *)rtw_zmalloc(sizeof(struct addBaReq_parm));
++	if (paddbareq_parm == NULL) {
++		rtw_mfree((unsigned char *)ph2c, sizeof(struct	cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	paddbareq_parm->tid = tid;
++	_rtw_memcpy(paddbareq_parm->addr, addr, ETH_ALEN);
++
++	init_h2fwcmd_w_parm_no_rsp(ph2c, paddbareq_parm, CMD_ADD_BAREQ);
++
++	/* RTW_INFO("rtw_addbareq_cmd, tid=%d\n", tid); */
++
++	/* rtw_enqueue_cmd(pcmdpriv, ph2c);	 */
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++
++	return res;
++}
++
++u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u16 start_seq)
++{
++	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++	struct cmd_obj *ph2c;
++	struct addBaRsp_parm *paddBaRsp_parm;
++	u8 res = _SUCCESS;
++
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	paddBaRsp_parm = (struct addBaRsp_parm *)rtw_zmalloc(sizeof(struct addBaRsp_parm));
++
++	if (paddBaRsp_parm == NULL) {
++		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	_rtw_memcpy(paddBaRsp_parm->addr, addr, ETH_ALEN);
++	paddBaRsp_parm->tid = tid;
++	paddBaRsp_parm->status = status;
++	paddBaRsp_parm->size = size;
++	paddBaRsp_parm->start_seq = start_seq;
++
++	init_h2fwcmd_w_parm_no_rsp(ph2c, paddBaRsp_parm, CMD_ADD_BARSP);
++
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++
++	return res;
++}
++/* add for CONFIG_IEEE80211W, none 11w can use it */
++u8 rtw_reset_securitypriv_cmd(_adapter *padapter)
++{
++	struct cmd_obj		*ph2c;
++	struct drvextra_cmd_parm  *pdrvextra_cmd_parm;
++	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
++	u8	res = _SUCCESS;
++
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm->ec_id = RESET_SECURITYPRIV;
++	pdrvextra_cmd_parm->type = 0;
++	pdrvextra_cmd_parm->size = 0;
++	pdrvextra_cmd_parm->pbuf = NULL;
++
++	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++
++	/* rtw_enqueue_cmd(pcmdpriv, ph2c);	 */
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++
++	return res;
++
++}
++
++void free_assoc_resources_hdl(_adapter *padapter, u8 lock_scanned_queue)
++{
++	rtw_free_assoc_resources(padapter, lock_scanned_queue);
++}
++
++u8 rtw_free_assoc_resources_cmd(_adapter *padapter, u8 lock_scanned_queue, int flags)
++{
++	struct cmd_obj *cmd;
++	struct drvextra_cmd_parm  *pdrvextra_cmd_parm;
++	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
++	struct submit_ctx sctx;
++	u8	res = _SUCCESS;
++
++	if (flags & RTW_CMDF_DIRECTLY) {
++		free_assoc_resources_hdl(padapter, lock_scanned_queue);
++	}
++	else {
++		cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++		if (cmd == NULL) {
++			res = _FAIL;
++			goto exit;
++		}
++
++		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++		if (pdrvextra_cmd_parm == NULL) {
++			rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj));
++			res = _FAIL;
++			goto exit;
++		}
++
++		pdrvextra_cmd_parm->ec_id = FREE_ASSOC_RESOURCES;
++		pdrvextra_cmd_parm->type = lock_scanned_queue;
++		pdrvextra_cmd_parm->size = 0;
++		pdrvextra_cmd_parm->pbuf = NULL;
++
++		init_h2fwcmd_w_parm_no_rsp(cmd, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++		if (flags & RTW_CMDF_WAIT_ACK) {
++			cmd->sctx = &sctx;
++			rtw_sctx_init(&sctx, 2000);
++		}
++
++		res = rtw_enqueue_cmd(pcmdpriv, cmd);
++
++		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
++			rtw_sctx_wait(&sctx, __func__);
++			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status == RTW_SCTX_SUBMITTED)
++				cmd->sctx = NULL;
++			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++		}
++	}
++exit:
++	return res;
++
++}
++
++u8 rtw_dynamic_chk_wk_cmd(_adapter *padapter)
++{
++	struct cmd_obj		*ph2c;
++	struct drvextra_cmd_parm  *pdrvextra_cmd_parm;
++	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
++	u8	res = _SUCCESS;
++
++
++	/* only  primary padapter does this cmd */
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm->ec_id = DYNAMIC_CHK_WK_CID;
++	pdrvextra_cmd_parm->type = 0;
++	pdrvextra_cmd_parm->size = 0;
++	pdrvextra_cmd_parm->pbuf = NULL;
++	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++
++	/* rtw_enqueue_cmd(pcmdpriv, ph2c);	 */
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++
++	return res;
++
++}
++
++u8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags)
++{
++	struct cmd_obj *pcmdobj;
++	struct set_ch_parm *set_ch_parm;
++	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++	struct submit_ctx sctx;
++	u8 res = _SUCCESS;
++
++
++	RTW_INFO(FUNC_NDEV_FMT" ch:%u, bw:%u, ch_offset:%u\n",
++		 FUNC_NDEV_ARG(padapter->pnetdev), ch, bw, ch_offset);
++
++	/* check input parameter */
++
++	/* prepare cmd parameter */
++	set_ch_parm = (struct set_ch_parm *)rtw_zmalloc(sizeof(*set_ch_parm));
++	if (set_ch_parm == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++	set_ch_parm->ch = ch;
++	set_ch_parm->bw = bw;
++	set_ch_parm->ch_offset = ch_offset;
++
++	if (flags & RTW_CMDF_DIRECTLY) {
++		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
++		if (H2C_SUCCESS != rtw_set_chbw_hdl(padapter, (u8 *)set_ch_parm))
++			res = _FAIL;
++
++		rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm));
++	} else {
++		/* need enqueue, prepare cmd_obj and enqueue */
++		pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct	cmd_obj));
++		if (pcmdobj == NULL) {
++			rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm));
++			res = _FAIL;
++			goto exit;
++		}
++
++		init_h2fwcmd_w_parm_no_rsp(pcmdobj, set_ch_parm, CMD_SET_CHANNEL);
++
++		if (flags & RTW_CMDF_WAIT_ACK) {
++			pcmdobj->sctx = &sctx;
++			rtw_sctx_init(&sctx, 10 * 1000);
++		}
++
++		res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
++
++		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
++			rtw_sctx_wait(&sctx, __func__);
++			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status == RTW_SCTX_SUBMITTED)
++				pcmdobj->sctx = NULL;
++			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++		}
++	}
++
++	/* do something based on res... */
++
++exit:
++
++	RTW_INFO(FUNC_NDEV_FMT" res:%u\n", FUNC_NDEV_ARG(padapter->pnetdev), res);
++
++
++	return res;
++}
++
++u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const struct country_chplan *country_ent, u8 swconfig)
++{
++	struct cmd_obj *cmdobj;
++	struct	SetChannelPlan_param *parm;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++	struct submit_ctx sctx;
++	u8 res = _SUCCESS;
++
++
++	/* check if allow software config */
++	if (swconfig && rtw_hal_is_disable_sw_channel_plan(adapter) == _TRUE) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	/* if country_entry is provided, replace chplan */
++	if (country_ent)
++		chplan = country_ent->chplan;
++
++	/* check input parameter */
++	if (!rtw_is_channel_plan_valid(chplan)) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	/* prepare cmd parameter */
++	parm = (struct SetChannelPlan_param *)rtw_zmalloc(sizeof(*parm));
++	if (parm == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++	parm->country_ent = country_ent;
++	parm->channel_plan = chplan;
++
++	if (flags & RTW_CMDF_DIRECTLY) {
++		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
++		if (H2C_SUCCESS != set_chplan_hdl(adapter, (u8 *)parm))
++			res = _FAIL;
++		rtw_mfree((u8 *)parm, sizeof(*parm));
++	} else {
++		/* need enqueue, prepare cmd_obj and enqueue */
++		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
++		if (cmdobj == NULL) {
++			res = _FAIL;
++			rtw_mfree((u8 *)parm, sizeof(*parm));
++			goto exit;
++		}
++
++		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_CHANPLAN);
++
++		if (flags & RTW_CMDF_WAIT_ACK) {
++			cmdobj->sctx = &sctx;
++			rtw_sctx_init(&sctx, 2000);
++		}
++
++		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
++
++		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
++			rtw_sctx_wait(&sctx, __func__);
++			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status == RTW_SCTX_SUBMITTED)
++				cmdobj->sctx = NULL;
++			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status != RTW_SCTX_DONE_SUCCESS)
++				res = _FAIL;
++		}
++
++		/* allow set channel plan when cmd_thread is not running */
++		if (res != _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
++			parm = (struct SetChannelPlan_param *)rtw_zmalloc(sizeof(*parm));
++			if (parm == NULL) {
++				res = _FAIL;
++				goto exit;
++			}
++			parm->country_ent = country_ent;
++			parm->channel_plan = chplan;
++
++			if (H2C_SUCCESS != set_chplan_hdl(adapter, (u8 *)parm))
++				res = _FAIL;
++			else
++				res = _SUCCESS;
++			rtw_mfree((u8 *)parm, sizeof(*parm));
++		}
++	}
++
++exit:
++	return res;
++}
++
++inline u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 swconfig)
++{
++	return _rtw_set_chplan_cmd(adapter, flags, chplan, NULL, swconfig);
++}
++
++inline u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, u8 swconfig)
++{
++	const struct country_chplan *ent;
++
++	if (is_alpha(country_code[0]) == _FALSE
++	    || is_alpha(country_code[1]) == _FALSE
++	   ) {
++		RTW_PRINT("%s input country_code is not alpha2\n", __func__);
++		return _FAIL;
++	}
++
++	ent = rtw_get_chplan_from_country(country_code);
++
++	if (ent == NULL) {
++		RTW_PRINT("%s unsupported country_code:\"%c%c\"\n", __func__, country_code[0], country_code[1]);
++		return _FAIL;
++	}
++
++	RTW_PRINT("%s country_code:\"%c%c\" mapping to chplan:0x%02x\n", __func__, country_code[0], country_code[1], ent->chplan);
++
++	return _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_UNSPECIFIED, ent, swconfig);
++}
++
++u8 rtw_led_blink_cmd(_adapter *padapter, void *pLed)
++{
++	struct	cmd_obj	*pcmdobj;
++	struct	LedBlink_param *ledBlink_param;
++	struct	cmd_priv   *pcmdpriv = &padapter->cmdpriv;
++
++	u8	res = _SUCCESS;
++
++
++
++	pcmdobj = (struct	cmd_obj *)rtw_zmalloc(sizeof(struct	cmd_obj));
++	if (pcmdobj == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	ledBlink_param = (struct	LedBlink_param *)rtw_zmalloc(sizeof(struct	LedBlink_param));
++	if (ledBlink_param == NULL) {
++		rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	ledBlink_param->pLed = pLed;
++
++	init_h2fwcmd_w_parm_no_rsp(pcmdobj, ledBlink_param, CMD_LEDBLINK);
++	res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
++
++exit:
++
++
++	return res;
++}
++
++u8 rtw_set_csa_cmd(_adapter *adapter)
++{
++	struct cmd_obj *cmdobj;
++	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
++	u8	res = _SUCCESS;
++
++	cmdobj = rtw_zmalloc(sizeof(struct cmd_obj));
++	if (cmdobj == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	init_h2fwcmd_w_parm_no_parm_rsp(cmdobj, CMD_SET_CHANSWITCH);
++	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
++
++exit:
++	return res;
++}
++
++u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option)
++{
++	u8 res = _SUCCESS;
++#ifdef CONFIG_TDLS
++	struct	cmd_obj	*pcmdobj;
++	struct	TDLSoption_param	*TDLSoption;
++	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct	cmd_priv   *pcmdpriv = &padapter->cmdpriv;
++
++	pcmdobj = (struct	cmd_obj *)rtw_zmalloc(sizeof(struct	cmd_obj));
++	if (pcmdobj == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	TDLSoption = (struct TDLSoption_param *)rtw_zmalloc(sizeof(struct TDLSoption_param));
++	if (TDLSoption == NULL) {
++		rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	_rtw_spinlock(&(padapter->tdlsinfo.cmd_lock));
++	if (addr != NULL)
++		_rtw_memcpy(TDLSoption->addr, addr, 6);
++	TDLSoption->option = option;
++	_rtw_spinunlock(&(padapter->tdlsinfo.cmd_lock));
++	init_h2fwcmd_w_parm_no_rsp(pcmdobj, TDLSoption, CMD_TDLS);
++	res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
++
++exit:
++#endif /* CONFIG_TDLS */
++
++	return res;
++}
++
++u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter)
++{
++	struct cmd_obj *ph2c;
++	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
++	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++	u8	res = _SUCCESS;
++
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm->ec_id = EN_HW_UPDATE_TSF_WK_CID;
++	pdrvextra_cmd_parm->type = 0;
++	pdrvextra_cmd_parm->size = 0;
++	pdrvextra_cmd_parm->pbuf = NULL;
++
++	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++	return res;
++}
++
++u8 rtw_periodic_tsf_update_end_cmd(_adapter *adapter)
++{
++	struct cmd_obj *cmdobj;
++	struct drvextra_cmd_parm *parm;
++	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
++	u8 res = _SUCCESS;
++
++	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (cmdobj == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (parm == NULL) {
++		rtw_mfree((unsigned char *)cmdobj, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	parm->ec_id = PERIOD_TSF_UPDATE_END_WK_CID;
++	parm->type = 0;
++	parm->size = 0;
++	parm->pbuf = NULL;
++
++	init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
++
++	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
++
++exit:
++	return res;
++}
++u8 rtw_ssmps_wk_hdl(_adapter *adapter, struct ssmps_cmd_parm *ssmp_param)
++{
++	u8 res = _SUCCESS;
++	struct sta_info *sta = ssmp_param->sta;
++	u8 smps = ssmp_param->smps;
++
++	if (sta == NULL)
++		return _FALSE;
++
++	if (smps)
++		rtw_ssmps_enter(adapter, sta);
++	else
++		rtw_ssmps_leave(adapter, sta);
++	return res;
++}
++
++u8 rtw_ssmps_wk_cmd(_adapter *adapter, struct sta_info *sta, u8 smps, u8 enqueue)
++{
++	struct cmd_obj *cmdobj;
++	struct drvextra_cmd_parm *cmd_parm;
++	struct ssmps_cmd_parm *ssmp_param;
++	struct cmd_priv	*pcmdpriv = &adapter->cmdpriv;
++	u8	res = _SUCCESS;
++
++	if (enqueue) {
++		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++		if (cmdobj == NULL) {
++			res = _FAIL;
++			goto exit;
++		}
++
++		cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++		if (cmd_parm == NULL) {
++			rtw_mfree((unsigned char *)cmdobj, sizeof(struct cmd_obj));
++			res = _FAIL;
++			goto exit;
++		}
++
++		ssmp_param = (struct ssmps_cmd_parm *)rtw_zmalloc(sizeof(struct ssmps_cmd_parm));
++		if (ssmp_param == NULL) {
++			rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
++			rtw_mfree((u8 *)cmd_parm, sizeof(struct drvextra_cmd_parm));
++			res = _FAIL;
++			goto exit;
++		}
++
++		ssmp_param->smps = smps;
++		ssmp_param->sta = sta;
++
++		cmd_parm->ec_id = SSMPS_WK_CID;
++		cmd_parm->type = 0;
++		cmd_parm->size = sizeof(struct ssmps_cmd_parm);
++		cmd_parm->pbuf = (u8 *)ssmp_param;
++
++		init_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, CMD_SET_DRV_EXTRA);
++
++		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
++	} else {
++		struct ssmps_cmd_parm tmp_ssmp_param;
++
++		tmp_ssmp_param.smps = smps;
++		tmp_ssmp_param.sta = sta;
++		rtw_ssmps_wk_hdl(adapter, &tmp_ssmp_param);
++	}
++
++exit:
++	return res;
++}
++
++#ifdef CONFIG_SUPPORT_STATIC_SMPS
++u8 _ssmps_chk_by_tp(_adapter *adapter, u8 from_timer)
++{
++	u8 enter_smps = _FALSE;
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++	struct sta_priv *pstapriv = &adapter->stapriv;
++	struct sta_info *psta;
++	u32 tx_tp_mbits, rx_tp_mbits;
++
++	if (!MLME_IS_STA(adapter) ||
++		!hal_is_mimo_support(adapter) ||
++		!pmlmeext->ssmps_en ||
++		(pmlmeext->cur_channel > 14)
++	)
++		return enter_smps;
++
++	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
++	if (psta == NULL) {
++		RTW_ERR(ADPT_FMT" sta == NULL\n", ADPT_ARG(adapter));
++		rtw_warn_on(1);
++		return enter_smps;
++	}
++
++	if (psta->cmn.mimo_type == RF_1T1R)
++		return enter_smps;
++
++	tx_tp_mbits = psta->sta_stats.tx_tp_kbits >> 10;
++	rx_tp_mbits = psta->sta_stats.rx_tp_kbits >> 10;
++
++	#ifdef DBG_STATIC_SMPS
++	if (pmlmeext->ssmps_test) {
++		enter_smps = (pmlmeext->ssmps_test_en == 1) ? _TRUE : _FALSE;
++	}
++	else
++	#endif
++	{
++		if ((tx_tp_mbits <= pmlmeext->ssmps_tx_tp_th) &&
++			(rx_tp_mbits <= pmlmeext->ssmps_rx_tp_th))
++			enter_smps = _TRUE;
++		else
++			enter_smps = _FALSE;
++	}
++
++	if (1) {
++		RTW_INFO(FUNC_ADPT_FMT" tx_tp:%d [%d], rx_tp:%d [%d] , SSMPS enter :%s\n",
++			FUNC_ADPT_ARG(adapter),
++			tx_tp_mbits, pmlmeext->ssmps_tx_tp_th,
++			rx_tp_mbits, pmlmeext->ssmps_rx_tp_th,
++			(enter_smps == _TRUE) ? "True" : "False");
++		#ifdef DBG_STATIC_SMPS
++		RTW_INFO(FUNC_ADPT_FMT" test:%d test_en:%d\n",
++			FUNC_ADPT_ARG(adapter),
++			pmlmeext->ssmps_test,
++			pmlmeext->ssmps_test_en);
++		#endif
++	}
++
++	if (enter_smps) {
++		if (!from_timer && psta->cmn.sm_ps != SM_PS_STATIC)
++			rtw_ssmps_enter(adapter, psta);
++	} else {
++		if (!from_timer && psta->cmn.sm_ps != SM_PS_DISABLE)
++			rtw_ssmps_leave(adapter, psta);
++		else {
++			u8 ps_change = _FALSE;
++
++			if (enter_smps && psta->cmn.sm_ps != SM_PS_STATIC)
++				ps_change = _TRUE;
++			else if (!enter_smps && psta->cmn.sm_ps != SM_PS_DISABLE)
++				ps_change = _TRUE;
++
++			if (ps_change)
++				rtw_ssmps_wk_cmd(adapter, psta, enter_smps, 1);
++		}
++	}
++
++	return enter_smps;
++}
++#endif /*CONFIG_SUPPORT_STATIC_SMPS*/
++
++#ifdef CONFIG_CTRL_TXSS_BY_TP
++void rtw_ctrl_txss_update_mimo_type(_adapter *adapter, struct sta_info *sta)
++{
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++
++	pmlmeext->txss_momi_type_bk = sta->cmn.mimo_type;
++}
++
++u8 rtw_ctrl_txss(_adapter *adapter, struct sta_info *sta, bool tx_1ss)
++{
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	u8 lps_changed = _FALSE;
++	u8 rst = _SUCCESS;
++
++	if (pmlmeext->txss_1ss == tx_1ss)
++		return _FALSE;
++
++	if (pwrpriv->bLeisurePs && pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
++		lps_changed = _TRUE;
++		LPS_Leave(adapter, "LPS_CTRL_TXSS");
++	}
++
++	RTW_INFO(ADPT_FMT" STA [" MAC_FMT "] set tx to %d ss\n",
++		ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr),
++		(tx_1ss) ? 1 : rtw_get_sta_tx_nss(adapter, sta));
++
++	/*ra re-registed*/
++	sta->cmn.mimo_type = (tx_1ss) ? RF_1T1R : pmlmeext->txss_momi_type_bk;
++	rtw_phydm_ra_registed(adapter, sta);
++
++	/*configure trx mode*/
++	rtw_phydm_trx_cfg(adapter, tx_1ss);
++	pmlmeext->txss_1ss = tx_1ss;
++
++	if (lps_changed)
++		LPS_Enter(adapter, "LPS_CTRL_TXSS");
++
++	return rst;
++}
++
++u8 rtw_ctrl_txss_wk_hdl(_adapter *adapter, struct txss_cmd_parm *txss_param)
++{
++	if (!txss_param->sta)
++		return _FALSE;
++
++	return rtw_ctrl_txss(adapter, txss_param->sta, txss_param->tx_1ss);
++}
++
++u8 rtw_ctrl_txss_wk_cmd(_adapter *adapter, struct sta_info *sta, bool tx_1ss, u8 flag)
++{
++	struct cmd_obj *cmdobj;
++	struct drvextra_cmd_parm *cmd_parm;
++	struct txss_cmd_parm *txss_param;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++	struct submit_ctx sctx;
++	u8	res = _SUCCESS;
++
++	txss_param = (struct txss_cmd_parm *)rtw_zmalloc(sizeof(struct txss_cmd_parm));
++	if (txss_param == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	txss_param->tx_1ss = tx_1ss;
++	txss_param->sta = sta;
++
++	if (flag & RTW_CMDF_DIRECTLY) {
++		res = rtw_ctrl_txss_wk_hdl(adapter, txss_param);
++		rtw_mfree((u8 *)txss_param, sizeof(*txss_param));
++	} else {
++		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++		if (cmdobj == NULL) {
++			res = _FAIL;
++			goto exit;
++		}
++
++		cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++		if (cmd_parm == NULL) {
++			rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
++			res = _FAIL;
++			goto exit;
++		}
++
++		cmd_parm->ec_id = TXSS_WK_CID;
++		cmd_parm->type = 0;
++		cmd_parm->size = sizeof(struct txss_cmd_parm);
++		cmd_parm->pbuf = (u8 *)txss_param;
++
++		init_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, CMD_SET_DRV_EXTRA);
++
++		if (flag & RTW_CMDF_WAIT_ACK) {
++			cmdobj->sctx = &sctx;
++			rtw_sctx_init(&sctx, 10 * 1000);
++		}
++
++		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
++		if (res == _SUCCESS && (flag & RTW_CMDF_WAIT_ACK)) {
++			rtw_sctx_wait(&sctx, __func__);
++			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status == RTW_SCTX_SUBMITTED)
++				cmdobj->sctx = NULL;
++			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status != RTW_SCTX_DONE_SUCCESS)
++				res = _FAIL;
++		}
++	}
++
++exit:
++	return res;
++}
++
++void rtw_ctrl_tx_ss_by_tp(_adapter *adapter, u8 from_timer)
++{
++	bool tx_1ss  = _FALSE; /*change tx from 2ss to 1ss*/
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++	struct sta_priv *pstapriv = &adapter->stapriv;
++	struct sta_info *psta;
++	u32 tx_tp_mbits;
++
++	if (!MLME_IS_STA(adapter) ||
++		!hal_is_mimo_support(adapter) ||
++		!pmlmeext->txss_ctrl_en
++	)
++		return;
++
++	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
++	if (psta == NULL) {
++		RTW_ERR(ADPT_FMT" sta == NULL\n", ADPT_ARG(adapter));
++		rtw_warn_on(1);
++		return;
++	}
++
++	tx_tp_mbits = psta->sta_stats.tx_tp_kbits >> 10;
++	if (tx_tp_mbits >= pmlmeext->txss_tp_th) {
++		tx_1ss = _FALSE;
++	} else {
++		if (pmlmeext->txss_tp_chk_cnt && --pmlmeext->txss_tp_chk_cnt)
++			tx_1ss = _FALSE;
++		else
++			tx_1ss = _TRUE;
++	}
++
++	if (1) {
++		RTW_INFO(FUNC_ADPT_FMT" tx_tp:%d [%d] tx_1ss(%d):%s\n",
++			FUNC_ADPT_ARG(adapter),
++			tx_tp_mbits, pmlmeext->txss_tp_th,
++			pmlmeext->txss_tp_chk_cnt,
++			(tx_1ss == _TRUE) ? "True" : "False");
++	}
++
++	if (pmlmeext->txss_1ss != tx_1ss) {
++		if (from_timer)
++			rtw_ctrl_txss_wk_cmd(adapter, psta, tx_1ss, 0);
++		else
++			rtw_ctrl_txss(adapter, psta, tx_1ss);
++	}
++}
++#ifdef DBG_CTRL_TXSS
++void dbg_ctrl_txss(_adapter *adapter, bool tx_1ss)
++{
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++	struct sta_priv *pstapriv = &adapter->stapriv;
++	struct sta_info *psta;
++
++	if (!MLME_IS_STA(adapter) ||
++		!hal_is_mimo_support(adapter)
++	)
++		return;
++
++	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
++	if (psta == NULL) {
++		RTW_ERR(ADPT_FMT" sta == NULL\n", ADPT_ARG(adapter));
++		rtw_warn_on(1);
++		return;
++	}
++
++	rtw_ctrl_txss(adapter, psta, tx_1ss);
++}
++#endif
++#endif /*CONFIG_CTRL_TXSS_BY_TP*/
++
++#ifdef CONFIG_LPS
++#ifdef CONFIG_LPS_CHK_BY_TP
++#ifdef LPS_BCN_CNT_MONITOR
++static u8 _bcn_cnt_expected(struct sta_info *psta)
++{
++	_adapter *adapter = psta->padapter;
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8 dtim = rtw_get_bcn_dtim_period(adapter);
++	u8 bcn_cnt = 0;
++
++	if ((pmlmeinfo->bcn_interval !=0) && (dtim != 0))
++		bcn_cnt = 2000 / pmlmeinfo->bcn_interval / dtim * 4 / 5; /*2s*/
++	if (0)
++		RTW_INFO("%s bcn_cnt:%d\n", __func__, bcn_cnt);
++
++	if (bcn_cnt == 0) {
++		RTW_ERR(FUNC_ADPT_FMT" bcn_cnt == 0\n", FUNC_ADPT_ARG(adapter));
++		rtw_warn_on(1);
++	}
++
++	return bcn_cnt;
++}
++#endif
++u8 _lps_chk_by_tp(_adapter *adapter, u8 from_timer)
++{
++	u8 enter_ps = _FALSE;
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	struct sta_priv *pstapriv = &adapter->stapriv;
++	struct sta_info *psta;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	u32 tx_tp_mbits, rx_tp_mbits, bi_tp_mbits;
++	u8 rx_bcn_cnt;
++
++	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
++	if (psta == NULL) {
++		RTW_ERR(ADPT_FMT" sta == NULL\n", ADPT_ARG(adapter));
++		rtw_warn_on(1);
++		return enter_ps;
++	}
++
++	rx_bcn_cnt = rtw_get_bcn_cnt(psta->padapter);
++	psta->sta_stats.acc_tx_bytes = psta->sta_stats.tx_bytes;
++	psta->sta_stats.acc_rx_bytes = psta->sta_stats.rx_bytes;
++
++#if 1
++	tx_tp_mbits = psta->sta_stats.tx_tp_kbits >> 10;
++	rx_tp_mbits = psta->sta_stats.rx_tp_kbits >> 10;
++	bi_tp_mbits = tx_tp_mbits + rx_tp_mbits;
++#else
++	tx_tp_mbits = psta->sta_stats.smooth_tx_tp_kbits >> 10;
++	rx_tp_mbits = psta->sta_stats.smooth_rx_tp_kbits >> 10;
++	bi_tp_mbits = tx_tp_mbits + rx_tp_mbits;
++#endif
++
++	if ((bi_tp_mbits >= pwrpriv->lps_bi_tp_th) ||
++		(tx_tp_mbits >= pwrpriv->lps_tx_tp_th) ||
++		(rx_tp_mbits >= pwrpriv->lps_rx_tp_th)) {
++		enter_ps = _FALSE;
++		pwrpriv->lps_chk_cnt = pwrpriv->lps_chk_cnt_th;
++	}
++	else {
++#ifdef LPS_BCN_CNT_MONITOR
++		u8 bcn_cnt = _bcn_cnt_expected(psta);
++
++		if (bcn_cnt && (rx_bcn_cnt < bcn_cnt)) {
++			pwrpriv->lps_chk_cnt = 2;
++			RTW_ERR(FUNC_ADPT_FMT" BCN_CNT:%d(%d) invalid\n",
++				FUNC_ADPT_ARG(adapter), rx_bcn_cnt, bcn_cnt);
++		}
++#endif
++
++		if (pwrpriv->lps_chk_cnt && --pwrpriv->lps_chk_cnt)
++			enter_ps = _FALSE;
++		else
++			enter_ps = _TRUE;
++	}
++
++	if (1) {
++		RTW_INFO(FUNC_ADPT_FMT" tx_tp:%d [%d], rx_tp:%d [%d], bi_tp:%d [%d], enter_ps(%d):%s\n",
++			FUNC_ADPT_ARG(adapter),
++			tx_tp_mbits, pwrpriv->lps_tx_tp_th,
++			rx_tp_mbits, pwrpriv->lps_rx_tp_th,
++			bi_tp_mbits, pwrpriv->lps_bi_tp_th,
++			pwrpriv->lps_chk_cnt,
++			(enter_ps == _TRUE) ? "True" : "False");
++		RTW_INFO(FUNC_ADPT_FMT" tx_pkt_cnt :%d [%d], rx_pkt_cnt :%d [%d]\n",
++			FUNC_ADPT_ARG(adapter),
++			pmlmepriv->LinkDetectInfo.NumTxOkInPeriod,
++			pwrpriv->lps_tx_pkts,
++			pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod,
++			pwrpriv->lps_rx_pkts);
++		if (!adapter->bsta_tp_dump)
++			RTW_INFO(FUNC_ADPT_FMT" bcn_cnt:%d (per-%d second)\n",
++			FUNC_ADPT_ARG(adapter),
++			rx_bcn_cnt,
++			2);
++	}
++
++	if (enter_ps) {
++		if (!from_timer)
++			LPS_Enter(adapter, "TRAFFIC_IDLE");
++	} else {
++		if (!from_timer)
++			LPS_Leave(adapter, "TRAFFIC_BUSY");
++		else {
++			#ifdef CONFIG_CONCURRENT_MODE
++			#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
++			if (adapter->hw_port == HW_PORT0)
++			#endif
++			#endif
++				rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_TRAFFIC_BUSY, 0);
++		}
++	}
++
++	return enter_ps;
++}
++#endif
++
++static u8 _lps_chk_by_pkt_cnts(_adapter *padapter, u8 from_timer, u8 bBusyTraffic)
++{		
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	u8	bEnterPS = _FALSE;
++
++	/* check traffic for  powersaving. */
++	if (((pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod) > 8) ||
++		#ifdef CONFIG_LPS_SLOW_TRANSITION
++		(pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 2)
++		#else /* CONFIG_LPS_SLOW_TRANSITION */
++		(pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 4)
++		#endif /* CONFIG_LPS_SLOW_TRANSITION */
++	) {
++		#ifdef DBG_RX_COUNTER_DUMP
++		if (padapter->dump_rx_cnt_mode & DUMP_DRV_TRX_COUNTER_DATA)
++			RTW_INFO("(-)Tx = %d, Rx = %d\n", pmlmepriv->LinkDetectInfo.NumTxOkInPeriod, pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod);
++		#endif
++
++		bEnterPS = _FALSE;
++		#ifdef CONFIG_LPS_SLOW_TRANSITION
++		if (bBusyTraffic == _TRUE) {
++			if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount <= 4)
++				pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 4;
++
++			pmlmepriv->LinkDetectInfo.TrafficTransitionCount++;
++
++			/* RTW_INFO("Set TrafficTransitionCount to %d\n", pmlmepriv->LinkDetectInfo.TrafficTransitionCount); */
++
++			if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount > 30/*TrafficTransitionLevel*/)
++				pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 30;
++		}
++		#endif /* CONFIG_LPS_SLOW_TRANSITION */
++	} else {
++		#ifdef DBG_RX_COUNTER_DUMP
++		if (padapter->dump_rx_cnt_mode & DUMP_DRV_TRX_COUNTER_DATA)
++			RTW_INFO("(+)Tx = %d, Rx = %d\n", pmlmepriv->LinkDetectInfo.NumTxOkInPeriod, pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod);
++		#endif
++
++		#ifdef CONFIG_LPS_SLOW_TRANSITION
++		if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount >= 2)
++			pmlmepriv->LinkDetectInfo.TrafficTransitionCount -= 2;
++		else
++			pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0;
++
++		if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount == 0)
++			bEnterPS = _TRUE;
++		#else /* CONFIG_LPS_SLOW_TRANSITION */
++			bEnterPS = _TRUE;
++		#endif /* CONFIG_LPS_SLOW_TRANSITION */
++	}
++
++	#ifdef CONFIG_DYNAMIC_DTIM
++	if (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount == 8)
++		bEnterPS = _FALSE;
++
++	RTW_INFO("LowPowerTransitionCount=%d\n", pmlmepriv->LinkDetectInfo.LowPowerTransitionCount);
++	#endif /* CONFIG_DYNAMIC_DTIM */
++
++	/* LeisurePS only work in infra mode. */
++	if (bEnterPS) {
++		if (!from_timer) {
++			#ifdef CONFIG_DYNAMIC_DTIM
++			if (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount < 8)
++				adapter_to_pwrctl(padapter)->dtim = 1;
++			else
++				adapter_to_pwrctl(padapter)->dtim = 3;
++			#endif /* CONFIG_DYNAMIC_DTIM */
++			LPS_Enter(padapter, "TRAFFIC_IDLE");
++		} else {
++			/* do this at caller */
++			/* rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_ENTER, 0); */
++			/* rtw_hal_dm_watchdog_in_lps(padapter); */
++		}
++
++		#ifdef CONFIG_DYNAMIC_DTIM
++		if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE)
++			pmlmepriv->LinkDetectInfo.LowPowerTransitionCount++;
++		#endif /* CONFIG_DYNAMIC_DTIM */
++	} else {
++		#ifdef CONFIG_DYNAMIC_DTIM
++		if (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount != 8)
++			pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0;
++		else
++			pmlmepriv->LinkDetectInfo.LowPowerTransitionCount++;
++		#endif /* CONFIG_DYNAMIC_DTIM */
++
++		if (!from_timer)
++			LPS_Leave(padapter, "TRAFFIC_BUSY");
++		else {
++			#ifdef CONFIG_CONCURRENT_MODE
++			#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
++			if (padapter->hw_port == HW_PORT0)
++			#endif
++			#endif
++				rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_TRAFFIC_BUSY, 0);
++		}
++	}
++
++	return bEnterPS;
++}
++#endif /* CONFIG_LPS */
++
++/* from_timer == 1 means driver is in LPS */
++u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer)
++{
++	u8	bEnterPS = _FALSE;
++	u16 BusyThresholdHigh;
++	u16	BusyThresholdLow;
++	u16	BusyThreshold;
++	u8	bBusyTraffic = _FALSE, bTxBusyTraffic = _FALSE, bRxBusyTraffic = _FALSE;
++	u8	bHigherBusyTraffic = _FALSE, bHigherBusyRxTraffic = _FALSE, bHigherBusyTxTraffic = _FALSE;
++
++	struct mlme_priv		*pmlmepriv = &(padapter->mlmepriv);
++#ifdef CONFIG_TDLS
++	struct tdls_info *ptdlsinfo = &(padapter->tdlsinfo);
++	struct tdls_txmgmt txmgmt;
++	u8 baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
++#endif /* CONFIG_TDLS */
++#ifdef CONFIG_TRAFFIC_PROTECT
++	RT_LINK_DETECT_T *link_detect = &pmlmepriv->LinkDetectInfo;
++#endif
++
++#ifdef CONFIG_BT_COEXIST
++	if (padapter->registrypriv.wifi_spec != 1) {
++		BusyThresholdHigh = 25;
++		BusyThresholdLow = 10;
++	} else
++#endif /* CONFIG_BT_COEXIST */
++	{
++		BusyThresholdHigh = 100;
++		BusyThresholdLow = 75;
++	}
++	BusyThreshold = BusyThresholdHigh;
++
++
++	/*  */
++	/* Determine if our traffic is busy now */
++	/*  */
++	if ((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++	    /*&& !MgntInitAdapterInProgress(pMgntInfo)*/) {
++		/* if we raise bBusyTraffic in last watchdog, using lower threshold. */
++		if (pmlmepriv->LinkDetectInfo.bBusyTraffic)
++			BusyThreshold = BusyThresholdLow;
++
++		if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > BusyThreshold ||
++		    pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > BusyThreshold) {
++			bBusyTraffic = _TRUE;
++
++			if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > pmlmepriv->LinkDetectInfo.NumTxOkInPeriod)
++				bRxBusyTraffic = _TRUE;
++			else
++				bTxBusyTraffic = _TRUE;
++		}
++
++		/* Higher Tx/Rx data. */
++		if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > 4000 ||
++		    pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > 4000) {
++			bHigherBusyTraffic = _TRUE;
++
++			if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > pmlmepriv->LinkDetectInfo.NumTxOkInPeriod)
++				bHigherBusyRxTraffic = _TRUE;
++			else
++				bHigherBusyTxTraffic = _TRUE;
++		}
++
++#ifdef CONFIG_TRAFFIC_PROTECT
++#define TX_ACTIVE_TH 10
++#define RX_ACTIVE_TH 20
++#define TRAFFIC_PROTECT_PERIOD_MS 4500
++
++		if (link_detect->NumTxOkInPeriod > TX_ACTIVE_TH
++		    || link_detect->NumRxUnicastOkInPeriod > RX_ACTIVE_TH) {
++
++			RTW_INFO(FUNC_ADPT_FMT" acqiure wake_lock for %u ms(tx:%d,rx_unicast:%d)\n",
++				 FUNC_ADPT_ARG(padapter),
++				 TRAFFIC_PROTECT_PERIOD_MS,
++				 link_detect->NumTxOkInPeriod,
++				 link_detect->NumRxUnicastOkInPeriod);
++
++			rtw_lock_traffic_suspend_timeout(TRAFFIC_PROTECT_PERIOD_MS);
++		}
++#endif
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_TDLS_AUTOSETUP
++		/* TDLS_WATCHDOG_PERIOD * 2sec, periodically send */
++		if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _TRUE) {
++			if ((ptdlsinfo->watchdog_count % TDLS_WATCHDOG_PERIOD) == 0) {
++				_rtw_memcpy(txmgmt.peer, baddr, ETH_ALEN);
++				issue_tdls_dis_req(padapter, &txmgmt);
++			}
++			ptdlsinfo->watchdog_count++;
++		}
++#endif /* CONFIG_TDLS_AUTOSETUP */
++#endif /* CONFIG_TDLS */
++
++#ifdef CONFIG_SUPPORT_STATIC_SMPS
++		_ssmps_chk_by_tp(padapter, from_timer);
++#endif
++#ifdef CONFIG_CTRL_TXSS_BY_TP
++		rtw_ctrl_tx_ss_by_tp(padapter, from_timer);
++#endif
++
++#ifdef CONFIG_LPS
++		if (adapter_to_pwrctl(padapter)->bLeisurePs && MLME_IS_STA(padapter)) {
++			#ifdef CONFIG_LPS_CHK_BY_TP
++			if (adapter_to_pwrctl(padapter)->lps_chk_by_tp)
++				bEnterPS = _lps_chk_by_tp(padapter, from_timer);
++			else
++			#endif /*CONFIG_LPS_CHK_BY_TP*/
++				bEnterPS = _lps_chk_by_pkt_cnts(padapter, from_timer, bBusyTraffic);
++		}
++#endif /* CONFIG_LPS */
++
++	} else {
++#ifdef CONFIG_LPS
++		if (!from_timer && rtw_mi_get_assoc_if_num(padapter) == 0)
++			LPS_Leave(padapter, "NON_LINKED");
++#endif
++	}
++
++	session_tracker_chk_cmd(padapter, NULL);
++
++#ifdef CONFIG_BEAMFORMING
++#ifdef RTW_BEAMFORMING_VERSION_2
++	rtw_bf_update_traffic(padapter);
++#endif /* RTW_BEAMFORMING_VERSION_2 */
++#endif /* CONFIG_BEAMFORMING */
++
++	pmlmepriv->LinkDetectInfo.NumRxOkInPeriod = 0;
++	pmlmepriv->LinkDetectInfo.NumTxOkInPeriod = 0;
++	pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod = 0;
++	pmlmepriv->LinkDetectInfo.bBusyTraffic = bBusyTraffic;
++	pmlmepriv->LinkDetectInfo.bTxBusyTraffic = bTxBusyTraffic;
++	pmlmepriv->LinkDetectInfo.bRxBusyTraffic = bRxBusyTraffic;
++	pmlmepriv->LinkDetectInfo.bHigherBusyTraffic = bHigherBusyTraffic;
++	pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic = bHigherBusyRxTraffic;
++	pmlmepriv->LinkDetectInfo.bHigherBusyTxTraffic = bHigherBusyTxTraffic;
++
++	return bEnterPS;
++
++}
++
++
++/* for 11n Logo 4.2.31/4.2.32 */
++static void dynamic_update_bcn_check(_adapter *padapter)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++	if (!padapter->registrypriv.wifi_spec)
++		return;
++
++	if (!padapter->registrypriv.ht_enable || !is_supported_ht(padapter->registrypriv.wireless_mode))
++		return;
++
++	if (!MLME_IS_AP(padapter))
++		return;
++
++	if (pmlmeext->bstart_bss) {
++		/* In 10 * 2 = 20s, there are no legacy AP, update HT info  */
++		static u8 count = 1;
++
++		if (count % 10 == 0) {
++			count = 1;
++#ifdef CONFIG_80211N_HT
++			if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc)
++				&& _FALSE == ATOMIC_READ(&pmlmepriv->olbc_ht)) {
++
++				if (rtw_ht_operation_update(padapter) > 0) {
++					update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0);
++					update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE, 0);
++				}
++			}
++#endif /* CONFIG_80211N_HT */
++		}
++
++#ifdef CONFIG_80211N_HT
++		/* In 2s, there are any legacy AP, update HT info, and then reset count  */
++
++		if (_FALSE != ATOMIC_READ(&pmlmepriv->olbc)
++			&& _FALSE != ATOMIC_READ(&pmlmepriv->olbc_ht)) {
++					
++			if (rtw_ht_operation_update(padapter) > 0) {
++				update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0);
++				update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE, 0);
++
++			}
++			ATOMIC_SET(&pmlmepriv->olbc, _FALSE);
++			ATOMIC_SET(&pmlmepriv->olbc_ht, _FALSE);
++			count = 0;
++		}
++#endif /* CONFIG_80211N_HT */
++		count ++;
++	}
++}
++void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter)
++{
++	#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++	#ifdef CONFIG_AP_MODE
++	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
++		expire_timeout_chk(padapter);
++		#ifdef CONFIG_RTW_MESH
++		if (MLME_IS_MESH(padapter) && MLME_IS_ASOC(padapter))
++			rtw_mesh_peer_status_chk(padapter);
++		#endif
++	}
++	#endif
++	#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
++	dynamic_update_bcn_check(padapter);
++
++	linked_status_chk(padapter, 0);
++	traffic_status_watchdog(padapter, 0);
++
++	/* for debug purpose */
++	_linked_info_dump(padapter);
++
++#ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
++        rtw_cfgvendor_rssi_monitor_evt(padapter);
++#endif
++
++
++}
++void rtw_dynamic_chk_wk_hdl(_adapter *padapter)
++{
++	rtw_mi_dynamic_chk_wk_hdl(padapter);
++#ifdef CONFIG_MP_INCLUDED
++	if (rtw_mp_mode_check(padapter) == _FALSE)
++#endif
++	{
++#ifdef DBG_CONFIG_ERROR_DETECT
++		rtw_hal_sreset_xmit_status_check(padapter);
++		rtw_hal_sreset_linked_status_check(padapter);
++#endif
++	}
++
++	/* if(check_fwstate(pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_SURVEY)==_FALSE) */
++	{
++#ifdef DBG_RX_COUNTER_DUMP
++		rtw_dump_rx_counters(padapter);
++#endif
++		dm_DynamicUsbTxAgg(padapter, 0);
++	}
++	rtw_hal_dm_watchdog(padapter);
++
++	/* check_hw_pbc(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type); */
++
++#ifdef CONFIG_BT_COEXIST
++	/* BT-Coexist */
++	rtw_btcoex_Handler(padapter);
++#endif
++
++#ifdef CONFIG_IPS_CHECK_IN_WD
++	/* always call rtw_ps_processor() at last one. */
++	rtw_ps_processor(padapter);
++#endif
++
++#ifdef CONFIG_MCC_MODE
++	rtw_hal_mcc_sw_status_check(padapter);
++#endif /* CONFIG_MCC_MODE */
++
++	rtw_hal_periodic_tsf_update_chk(padapter);
++}
++
++#ifdef CONFIG_LPS
++struct lps_ctrl_wk_parm {
++	s8 lps_level;
++	#ifdef CONFIG_LPS_1T1R
++	s8 lps_1t1r;
++	#endif
++};
++
++void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type, u8 *buf)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct lps_ctrl_wk_parm *parm = (struct lps_ctrl_wk_parm *)buf;
++	u8	mstatus;
++
++	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)
++	    || (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
++		return;
++
++	switch (lps_ctrl_type) {
++	case LPS_CTRL_SCAN:
++		/* RTW_INFO("LPS_CTRL_SCAN\n"); */
++#ifdef CONFIG_BT_COEXIST
++		rtw_btcoex_ScanNotify(padapter, _TRUE);
++#endif /* CONFIG_BT_COEXIST */
++		if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++			/* connect */
++			LPS_Leave(padapter, "LPS_CTRL_SCAN");
++		}
++		break;
++	case LPS_CTRL_JOINBSS:
++		/* RTW_INFO("LPS_CTRL_JOINBSS\n"); */
++		LPS_Leave(padapter, "LPS_CTRL_JOINBSS");
++		break;
++	case LPS_CTRL_CONNECT:
++		/* RTW_INFO("LPS_CTRL_CONNECT\n"); */
++		mstatus = 1;/* connect */
++		/* Reset LPS Setting */
++		pwrpriv->LpsIdleCount = 0;
++		rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus));
++#ifdef CONFIG_BT_COEXIST
++		rtw_btcoex_MediaStatusNotify(padapter, mstatus);
++#endif /* CONFIG_BT_COEXIST */
++		break;
++	case LPS_CTRL_DISCONNECT:
++		/* RTW_INFO("LPS_CTRL_DISCONNECT\n"); */
++		mstatus = 0;/* disconnect */
++#ifdef CONFIG_BT_COEXIST
++		rtw_btcoex_MediaStatusNotify(padapter, mstatus);
++#endif /* CONFIG_BT_COEXIST */
++		LPS_Leave(padapter, "LPS_CTRL_DISCONNECT");
++		rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus));
++		break;
++	case LPS_CTRL_SPECIAL_PACKET:
++		/* RTW_INFO("LPS_CTRL_SPECIAL_PACKET\n"); */
++		rtw_set_lps_deny(padapter, LPS_DELAY_MS);
++#ifdef CONFIG_BT_COEXIST
++		rtw_btcoex_SpecialPacketNotify(padapter, PACKET_DHCP);
++#endif /* CONFIG_BT_COEXIST */
++		LPS_Leave(padapter, "LPS_CTRL_SPECIAL_PACKET");
++		break;
++	case LPS_CTRL_LEAVE:
++		LPS_Leave(padapter, "LPS_CTRL_LEAVE");
++		break;
++	case LPS_CTRL_LEAVE_SET_OPTION:
++		LPS_Leave(padapter, "LPS_CTRL_LEAVE_SET_OPTION");
++		if (parm) {
++			if (parm->lps_level >= 0)
++				pwrpriv->lps_level = parm->lps_level;
++			#ifdef CONFIG_LPS_1T1R
++			if (parm->lps_1t1r >= 0)
++				pwrpriv->lps_1t1r = parm->lps_1t1r;
++			#endif
++		}
++		break;
++	case LPS_CTRL_LEAVE_CFG80211_PWRMGMT:
++		LPS_Leave(padapter, "CFG80211_PWRMGMT");
++		break;
++	case LPS_CTRL_TRAFFIC_BUSY:
++		LPS_Leave(padapter, "LPS_CTRL_TRAFFIC_BUSY");
++		break;
++	case LPS_CTRL_TX_TRAFFIC_LEAVE:
++		LPS_Leave(padapter, "LPS_CTRL_TX_TRAFFIC_LEAVE");
++		break;
++	case LPS_CTRL_RX_TRAFFIC_LEAVE:
++		LPS_Leave(padapter, "LPS_CTRL_RX_TRAFFIC_LEAVE");
++		break;
++	case LPS_CTRL_ENTER:
++		LPS_Enter(padapter, "TRAFFIC_IDLE_1");
++		break;
++	default:
++		break;
++	}
++
++}
++
++static u8 _rtw_lps_ctrl_wk_cmd(_adapter *adapter, u8 lps_ctrl_type, s8 lps_level, s8 lps_1t1r, u8 flags)
++{
++	struct cmd_obj *cmdobj;
++	struct drvextra_cmd_parm *parm;
++	struct lps_ctrl_wk_parm *wk_parm = NULL;
++	struct cmd_priv	*pcmdpriv = &adapter->cmdpriv;
++	struct submit_ctx sctx;
++	u8	res = _SUCCESS;
++
++	if (lps_ctrl_type == LPS_CTRL_LEAVE_SET_OPTION) {
++		wk_parm = rtw_zmalloc(sizeof(*wk_parm));
++		if (wk_parm == NULL) {
++			res = _FAIL;
++			goto exit;
++		}
++		wk_parm->lps_level = lps_level;
++		#ifdef CONFIG_LPS_1T1R
++		wk_parm->lps_1t1r = lps_1t1r;
++		#endif
++	}
++
++	if (flags & RTW_CMDF_DIRECTLY) {
++		/* no need to enqueue, do the cmd hdl directly */
++		lps_ctrl_wk_hdl(adapter, lps_ctrl_type, (u8 *)wk_parm);
++		if (wk_parm)
++			rtw_mfree(wk_parm, sizeof(*wk_parm));
++	} else {
++		/* need enqueue, prepare cmd_obj and enqueue */
++		parm = rtw_zmalloc(sizeof(*parm));
++		if (parm == NULL) {
++			if (wk_parm)
++				rtw_mfree(wk_parm, sizeof(*wk_parm));
++			res = _FAIL;
++			goto exit;
++		}
++
++		parm->ec_id = LPS_CTRL_WK_CID;
++		parm->type = lps_ctrl_type;
++		parm->size = wk_parm ? sizeof(*wk_parm) : 0;
++		parm->pbuf = (u8 *)wk_parm;
++
++		cmdobj = rtw_zmalloc(sizeof(*cmdobj));
++		if (cmdobj == NULL) {
++			rtw_mfree(parm, sizeof(*parm));
++			if (wk_parm)
++				rtw_mfree(wk_parm, sizeof(*wk_parm));
++			res = _FAIL;
++			goto exit;
++		}
++
++		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
++
++		if (flags & RTW_CMDF_WAIT_ACK) {
++			cmdobj->sctx = &sctx;
++			rtw_sctx_init(&sctx, 2000);
++		}
++
++		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
++
++		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
++			rtw_sctx_wait(&sctx, __func__);
++			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status == RTW_SCTX_SUBMITTED)
++				cmdobj->sctx = NULL;
++			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status != RTW_SCTX_DONE_SUCCESS)
++				res = _FAIL;
++		}
++	}
++
++exit:
++	return res;
++}
++
++u8 rtw_lps_ctrl_wk_cmd(_adapter *adapter, u8 lps_ctrl_type, u8 flags)
++{
++	return _rtw_lps_ctrl_wk_cmd(adapter, lps_ctrl_type, -1, -1, flags);
++}
++
++u8 rtw_lps_ctrl_leave_set_level_cmd(_adapter *adapter, u8 lps_level, u8 flags)
++{
++	return _rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_LEAVE_SET_OPTION, lps_level, -1, flags);
++}
++
++#ifdef CONFIG_LPS_1T1R
++u8 rtw_lps_ctrl_leave_set_1t1r_cmd(_adapter *adapter, u8 lps_1t1r, u8 flags)
++{
++	return _rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_LEAVE_SET_OPTION, -1, lps_1t1r, flags);
++}
++#endif
++
++void rtw_dm_in_lps_hdl(_adapter *padapter)
++{
++	rtw_hal_set_hwreg(padapter, HW_VAR_DM_IN_LPS_LCLK, NULL);
++}
++
++u8 rtw_dm_in_lps_wk_cmd(_adapter *padapter)
++{
++	struct cmd_obj	*ph2c;
++	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
++	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
++	u8	res = _SUCCESS;
++
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm->ec_id = DM_IN_LPS_WK_CID;
++	pdrvextra_cmd_parm->type = 0;
++	pdrvextra_cmd_parm->size = 0;
++	pdrvextra_cmd_parm->pbuf = NULL;
++
++	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++	return res;
++
++}
++
++void rtw_lps_change_dtim_hdl(_adapter *padapter, u8 dtim)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++
++	if (dtim <= 0 || dtim > 16)
++		return;
++
++#ifdef CONFIG_BT_COEXIST
++	if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
++		return;
++#endif
++
++#ifdef CONFIG_LPS_LCLK
++	_enter_pwrlock(&pwrpriv->lock);
++#endif
++
++	if (pwrpriv->dtim != dtim) {
++		RTW_INFO("change DTIM from %d to %d, bFwCurrentInPSMode=%d, ps_mode=%d\n", pwrpriv->dtim, dtim,
++			 pwrpriv->bFwCurrentInPSMode, pwrpriv->pwr_mode);
++
++		pwrpriv->dtim = dtim;
++	}
++
++	if ((pwrpriv->bFwCurrentInPSMode == _TRUE) && (pwrpriv->pwr_mode > PS_MODE_ACTIVE)) {
++		u8 ps_mode = pwrpriv->pwr_mode;
++
++		/* RTW_INFO("change DTIM from %d to %d, ps_mode=%d\n", pwrpriv->dtim, dtim, ps_mode); */
++
++		rtw_exec_lps(padapter, ps_mode);
++	}
++
++#ifdef CONFIG_LPS_LCLK
++	_exit_pwrlock(&pwrpriv->lock);
++#endif
++
++}
++
++#endif
++
++u8 rtw_lps_change_dtim_cmd(_adapter *padapter, u8 dtim)
++{
++	struct cmd_obj	*ph2c;
++	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
++	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
++	u8	res = _SUCCESS;
++	/*
++	#ifdef CONFIG_CONCURRENT_MODE
++		if (padapter->hw_port != HW_PORT0)
++			return res;
++	#endif
++	*/
++	{
++		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++		if (ph2c == NULL) {
++			res = _FAIL;
++			goto exit;
++		}
++
++		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++		if (pdrvextra_cmd_parm == NULL) {
++			rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++			res = _FAIL;
++			goto exit;
++		}
++
++		pdrvextra_cmd_parm->ec_id = LPS_CHANGE_DTIM_CID;
++		pdrvextra_cmd_parm->type = dtim;
++		pdrvextra_cmd_parm->size = 0;
++		pdrvextra_cmd_parm->pbuf = NULL;
++
++		init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++	}
++
++exit:
++
++	return res;
++
++}
++
++#if (RATE_ADAPTIVE_SUPPORT == 1)
++void rpt_timer_setting_wk_hdl(_adapter *padapter, u16 minRptTime)
++{
++	rtw_hal_set_hwreg(padapter, HW_VAR_RPT_TIMER_SETTING, (u8 *)(&minRptTime));
++}
++
++u8 rtw_rpt_timer_cfg_cmd(_adapter *padapter, u16 minRptTime)
++{
++	struct cmd_obj		*ph2c;
++	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
++	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
++
++	u8	res = _SUCCESS;
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm->ec_id = RTP_TIMER_CFG_WK_CID;
++	pdrvextra_cmd_parm->type = minRptTime;
++	pdrvextra_cmd_parm->size = 0;
++	pdrvextra_cmd_parm->pbuf = NULL;
++	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++exit:
++
++
++	return res;
++
++}
++
++#endif
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++void antenna_select_wk_hdl(_adapter *padapter, u8 antenna)
++{
++	rtw_hal_set_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &antenna, _TRUE);
++}
++
++u8 rtw_antenna_select_cmd(_adapter *padapter, u8 antenna, u8 enqueue)
++{
++	struct cmd_obj		*ph2c;
++	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
++	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	u8	bSupportAntDiv = _FALSE;
++	u8	res = _SUCCESS;
++	int	i;
++
++	rtw_hal_get_def_var(padapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv));
++	if (_FALSE == bSupportAntDiv)
++		return _FAIL;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		if (rtw_linked_check(dvobj->padapters[i]))
++			return _FAIL;
++	}
++
++	if (_TRUE == enqueue) {
++		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++		if (ph2c == NULL) {
++			res = _FAIL;
++			goto exit;
++		}
++
++		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++		if (pdrvextra_cmd_parm == NULL) {
++			rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++			res = _FAIL;
++			goto exit;
++		}
++
++		pdrvextra_cmd_parm->ec_id = ANT_SELECT_WK_CID;
++		pdrvextra_cmd_parm->type = antenna;
++		pdrvextra_cmd_parm->size = 0;
++		pdrvextra_cmd_parm->pbuf = NULL;
++		init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++	} else
++		antenna_select_wk_hdl(padapter, antenna);
++exit:
++
++
++	return res;
++
++}
++#endif
++
++void rtw_dm_ra_mask_hdl(_adapter *padapter, struct sta_info *psta)
++{
++	if (psta)
++		set_sta_rate(padapter, psta);
++}
++
++u8 rtw_dm_ra_mask_wk_cmd(_adapter *padapter, u8 *psta)
++{
++	struct cmd_obj	*ph2c;
++	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
++	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
++	u8	res = _SUCCESS;
++
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm->ec_id = DM_RA_MSK_WK_CID;
++	pdrvextra_cmd_parm->type = 0;
++	pdrvextra_cmd_parm->size = 0;
++	pdrvextra_cmd_parm->pbuf = psta;
++
++	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++	return res;
++
++}
++
++void power_saving_wk_hdl(_adapter *padapter)
++{
++	rtw_ps_processor(padapter);
++}
++
++/* add for CONFIG_IEEE80211W, none 11w can use it */
++void reset_securitypriv_hdl(_adapter *padapter)
++{
++	rtw_reset_securitypriv(padapter);
++}
++
++#ifdef CONFIG_P2P
++u8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType)
++{
++	struct cmd_obj	*ph2c;
++	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
++	u8	res = _SUCCESS;
++
++
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++		return res;
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm->ec_id = P2P_PROTO_WK_CID;
++	pdrvextra_cmd_parm->type = intCmdType;	/*	As the command tppe. */
++	pdrvextra_cmd_parm->size = 0;
++	pdrvextra_cmd_parm->pbuf = NULL;		/*	Must be NULL here */
++
++	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++
++	return res;
++
++}
++
++#ifdef CONFIG_IOCTL_CFG80211
++static u8 _p2p_roch_cmd(_adapter *adapter
++	, u64 cookie, struct wireless_dev *wdev
++	, struct ieee80211_channel *ch, enum nl80211_channel_type ch_type
++	, unsigned int duration
++	, u8 flags
++)
++{
++	struct cmd_obj *cmdobj;
++	struct drvextra_cmd_parm *parm;
++	struct p2p_roch_parm *roch_parm;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++	struct submit_ctx sctx;
++	u8 cancel = duration ? 0 : 1;
++	u8	res = _SUCCESS;
++
++	roch_parm = (struct p2p_roch_parm *)rtw_zmalloc(sizeof(struct p2p_roch_parm));
++	if (roch_parm == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	roch_parm->cookie = cookie;
++	roch_parm->wdev = wdev;
++	if (!cancel) {
++		_rtw_memcpy(&roch_parm->ch, ch, sizeof(struct ieee80211_channel));
++		roch_parm->ch_type = ch_type;
++		roch_parm->duration = duration;
++	}
++
++	if (flags & RTW_CMDF_DIRECTLY) {
++		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
++		if (H2C_SUCCESS != p2p_protocol_wk_hdl(adapter, cancel ? P2P_CANCEL_RO_CH_WK : P2P_RO_CH_WK, (u8 *)roch_parm))
++			res = _FAIL;
++		rtw_mfree((u8 *)roch_parm, sizeof(*roch_parm));
++	} else {
++		/* need enqueue, prepare cmd_obj and enqueue */
++		parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++		if (parm == NULL) {
++			rtw_mfree((u8 *)roch_parm, sizeof(*roch_parm));
++			res = _FAIL;
++			goto exit;
++		}
++
++		parm->ec_id = P2P_PROTO_WK_CID;
++		parm->type = cancel ? P2P_CANCEL_RO_CH_WK : P2P_RO_CH_WK;
++		parm->size = sizeof(*roch_parm);
++		parm->pbuf = (u8 *)roch_parm;
++
++		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
++		if (cmdobj == NULL) {
++			res = _FAIL;
++			rtw_mfree((u8 *)roch_parm, sizeof(*roch_parm));
++			rtw_mfree((u8 *)parm, sizeof(*parm));
++			goto exit;
++		}
++
++		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
++
++		if (flags & RTW_CMDF_WAIT_ACK) {
++			cmdobj->sctx = &sctx;
++			rtw_sctx_init(&sctx, 10 * 1000);
++		}
++
++		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
++
++		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
++			rtw_sctx_wait(&sctx, __func__);
++			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status == RTW_SCTX_SUBMITTED)
++				cmdobj->sctx = NULL;
++			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status != RTW_SCTX_DONE_SUCCESS)
++				res = _FAIL;
++		}
++	}
++
++exit:
++	return res;
++}
++
++inline u8 p2p_roch_cmd(_adapter *adapter
++	, u64 cookie, struct wireless_dev *wdev
++	, struct ieee80211_channel *ch, enum nl80211_channel_type ch_type
++	, unsigned int duration
++	, u8 flags
++)
++{
++	return _p2p_roch_cmd(adapter, cookie, wdev, ch, ch_type, duration, flags);
++}
++
++inline u8 p2p_cancel_roch_cmd(_adapter *adapter, u64 cookie, struct wireless_dev *wdev, u8 flags)
++{
++	return _p2p_roch_cmd(adapter, cookie, wdev, NULL, 0, 0, flags);
++}
++
++#endif /* CONFIG_IOCTL_CFG80211 */
++#endif /* CONFIG_P2P */
++
++#ifdef CONFIG_IOCTL_CFG80211 
++inline u8 rtw_mgnt_tx_cmd(_adapter *adapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack, u8 flags)
++{
++	struct cmd_obj *cmdobj;
++	struct drvextra_cmd_parm *parm;
++	struct mgnt_tx_parm *mgnt_parm;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++	struct submit_ctx sctx;
++	u8	res = _SUCCESS;
++
++	mgnt_parm = (struct mgnt_tx_parm *)rtw_zmalloc(sizeof(struct mgnt_tx_parm));
++	if (mgnt_parm == NULL) {
++		res = _FAIL;
++			goto exit;
++	}
++
++	mgnt_parm->tx_ch = tx_ch;
++	mgnt_parm->no_cck = no_cck;
++	mgnt_parm->buf = buf;
++	mgnt_parm->len = len;
++	mgnt_parm->wait_ack = wait_ack;
++
++	if (flags & RTW_CMDF_DIRECTLY) {
++		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
++		if (H2C_SUCCESS != rtw_mgnt_tx_handler(adapter, (u8 *)mgnt_parm))
++			res = _FAIL;
++		rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm));
++	} else {
++		/* need enqueue, prepare cmd_obj and enqueue */
++		parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++		if (parm == NULL) {
++			rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm));
++			res = _FAIL;
++			goto exit;
++		}
++
++		parm->ec_id = MGNT_TX_WK_CID;
++		parm->type = 0;
++		parm->size = sizeof(*mgnt_parm);
++		parm->pbuf = (u8 *)mgnt_parm;
++
++		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
++		if (cmdobj == NULL) {
++			res = _FAIL;
++			rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm));
++			rtw_mfree((u8 *)parm, sizeof(*parm));
++			goto exit;
++		}
++
++		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
++
++		if (flags & RTW_CMDF_WAIT_ACK) {
++			cmdobj->sctx = &sctx;
++			rtw_sctx_init(&sctx, 10 * 1000);
++		}
++
++		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
++
++		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
++			rtw_sctx_wait(&sctx, __func__);
++			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status == RTW_SCTX_SUBMITTED)
++				cmdobj->sctx = NULL;
++			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status != RTW_SCTX_DONE_SUCCESS)
++				res = _FAIL;
++		}
++	}
++
++exit:
++	return res;
++}
++#endif
++
++u8 rtw_ps_cmd(_adapter *padapter)
++{
++	struct cmd_obj		*ppscmd;
++	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
++	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
++
++	u8	res = _SUCCESS;
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (!is_primary_adapter(padapter))
++		goto exit;
++#endif
++
++	ppscmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ppscmd == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((unsigned char *)ppscmd, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm->ec_id = POWER_SAVING_CTRL_WK_CID;
++	pdrvextra_cmd_parm->type = 0;
++	pdrvextra_cmd_parm->size = 0;
++	pdrvextra_cmd_parm->pbuf = NULL;
++	init_h2fwcmd_w_parm_no_rsp(ppscmd, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++	res = rtw_enqueue_cmd(pcmdpriv, ppscmd);
++
++exit:
++
++
++	return res;
++
++}
++
++#if CONFIG_DFS
++void rtw_dfs_ch_switch_hdl(struct dvobj_priv *dvobj)
++{
++	struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
++	_adapter *pri_adapter = dvobj_get_primary_adapter(dvobj);
++	u8 ifbmp_m = rtw_mi_get_ap_mesh_ifbmp(pri_adapter);
++	u8 ifbmp_s = rtw_mi_get_ld_sta_ifbmp(pri_adapter);
++	s16 req_ch;
++
++	rtw_hal_macid_sleep_all_used(pri_adapter);
++
++	if (rtw_chset_search_ch(rfctl->channel_set, rfctl->csa_ch) >= 0
++		&& !rtw_chset_is_ch_non_ocp(rfctl->channel_set, rfctl->csa_ch)
++	) {
++		/* CSA channel available and valid */
++		req_ch = rfctl->csa_ch;
++		RTW_INFO("%s valid CSA ch%u\n", __func__, rfctl->csa_ch);
++	} else if (ifbmp_m) {
++		/* no available or valid CSA channel, having AP/MESH ifaces */
++		req_ch = REQ_CH_NONE;
++		RTW_INFO("%s ch sel by AP/MESH ifaces\n", __func__);
++	} else {
++		/* no available or valid CSA channel and no AP/MESH ifaces */
++		if (!IsSupported24G(dvobj_to_regsty(dvobj)->wireless_mode)
++			#ifdef CONFIG_DFS_MASTER
++			|| rfctl->radar_detected
++			#endif
++		)
++			req_ch = 36;
++		else
++			req_ch = 1;
++		RTW_INFO("%s switch to ch%d\n", __func__, req_ch);
++	}
++
++	/*  issue deauth for all asoc STA ifaces */
++	if (ifbmp_s) {
++		_adapter *iface;
++		int i;
++
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			iface = dvobj->padapters[i];
++			if (!iface || !(ifbmp_s & BIT(iface->iface_id)))
++				continue;
++			set_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING);
++
++			/* TODO: true op ch switching */
++			issue_deauth(iface, get_bssid(&iface->mlmepriv), WLAN_REASON_DEAUTH_LEAVING);
++		}
++	}
++
++#ifdef CONFIG_AP_MODE
++	if (ifbmp_m) {
++		/* trigger channel selection without consideraton of asoc STA ifaces */
++		rtw_change_bss_chbw_cmd(dvobj_get_primary_adapter(dvobj), RTW_CMDF_DIRECTLY
++			, ifbmp_m, ifbmp_s, req_ch, REQ_BW_ORI, REQ_OFFSET_NONE);
++	} else
++#endif
++	{
++		/* no AP/MESH iface, switch DFS status and channel directly */
++		rtw_warn_on(req_ch <= 0);
++		#ifdef CONFIG_DFS_MASTER
++		rtw_dfs_rd_en_decision(pri_adapter, MLME_OPCH_SWITCH, ifbmp_s);
++		#endif
++		set_channel_bwmode(pri_adapter, req_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++	}
++
++	/* make asoc STA ifaces disconnect */
++	/* TODO: true op ch switching */
++	if (ifbmp_s) {
++		_adapter *iface;
++		int i;
++	
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			iface = dvobj->padapters[i];
++			if (!iface || !(ifbmp_s & BIT(iface->iface_id)))
++				continue;
++			rtw_disassoc_cmd(iface, 0, RTW_CMDF_DIRECTLY);
++			rtw_indicate_disconnect(iface, 0, _FALSE);
++			rtw_free_assoc_resources(iface, _TRUE);
++			rtw_free_network_queue(iface, _TRUE);
++		}
++	}
++
++	rfctl->csa_ch = 0;
++
++	rtw_hal_macid_wakeup_all_used(pri_adapter);
++	rtw_mi_os_xmit_schedule(pri_adapter);
++}
++#endif /* CONFIG_DFS */
++
++#ifdef CONFIG_AP_MODE
++
++static void rtw_chk_hi_queue_hdl(_adapter *padapter)
++{
++	struct sta_info *psta_bmc;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	systime start = rtw_get_current_time();
++	u8 empty = _FALSE;
++
++	psta_bmc = rtw_get_bcmc_stainfo(padapter);
++	if (!psta_bmc)
++		return;
++
++	rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty);
++
++	while (_FALSE == empty && rtw_get_passing_time_ms(start) < rtw_get_wait_hiq_empty_ms()) {
++		rtw_msleep_os(100);
++		rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty);
++	}
++
++	if (psta_bmc->sleepq_len == 0) {
++		if (empty == _SUCCESS) {
++			bool update_tim = _FALSE;
++
++			if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0))
++				update_tim = _TRUE;
++
++			rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0);
++			rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0);
++
++			if (update_tim == _TRUE)
++				_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0,"bmc sleepq and HIQ empty");
++		} else /* re check again */
++			rtw_chk_hi_queue_cmd(padapter);
++
++	}
++
++}
++
++u8 rtw_chk_hi_queue_cmd(_adapter *padapter)
++{
++	struct cmd_obj	*ph2c;
++	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
++	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
++	u8	res = _SUCCESS;
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm->ec_id = CHECK_HIQ_WK_CID;
++	pdrvextra_cmd_parm->type = 0;
++	pdrvextra_cmd_parm->size = 0;
++	pdrvextra_cmd_parm->pbuf = NULL;
++
++	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++	return res;
++
++}
++
++#ifdef CONFIG_DFS_MASTER
++u8 rtw_dfs_rd_hdl(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++
++	if (!rfctl->radar_detect_enabled)
++		goto exit;
++
++	if (dvobj->oper_channel != rfctl->radar_detect_ch
++		|| rtw_get_passing_time_ms(rtw_get_on_oper_ch_time(adapter)) < 300
++	) {
++		/* offchannel, bypass radar detect */
++		goto cac_status_chk;
++	}
++
++	if (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl)) {
++		/* non_ocp, bypass radar detect */
++		goto cac_status_chk;
++	}
++
++	if (!rfctl->dbg_dfs_fake_radar_detect_cnt
++		&& rtw_odm_radar_detect(adapter) != _TRUE)
++		goto cac_status_chk;
++
++	if (!rfctl->dbg_dfs_fake_radar_detect_cnt
++		&& rfctl->dbg_dfs_radar_detect_trigger_non
++	) {
++		/* radar detect debug mode, trigger no mlme flow */
++		RTW_INFO("%s radar detected on test mode, trigger no mlme flow\n", __func__);
++		goto cac_status_chk;
++	}
++
++	if (rfctl->dbg_dfs_fake_radar_detect_cnt != 0) {
++		RTW_INFO("%s fake radar detected, cnt:%d\n", __func__
++			, rfctl->dbg_dfs_fake_radar_detect_cnt);
++		rfctl->dbg_dfs_fake_radar_detect_cnt--;
++	} else
++		RTW_INFO("%s radar detected\n", __func__);
++
++	rfctl->radar_detected = 1;
++
++	rtw_chset_update_non_ocp(rfctl->channel_set
++		, rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset);
++
++	rtw_dfs_ch_switch_hdl(dvobj);
++
++	if (rfctl->radar_detect_enabled)
++		goto set_timer;
++	goto exit;
++
++cac_status_chk:
++
++	if (!IS_CAC_STOPPED(rfctl)
++		&& ((IS_UNDER_CAC(rfctl) && rfctl->cac_force_stop)
++			|| !IS_CH_WAITING(rfctl)
++			)
++	) {
++		u8 pause = 0x00;
++
++		rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause);
++		rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;
++
++		if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_LINKING|WIFI_UNDER_SURVEY) == _FALSE) {
++			u8 doiqk = _TRUE;
++			u8 u_ch, u_bw, u_offset;
++
++			rtw_hal_set_hwreg(adapter , HW_VAR_DO_IQK , &doiqk);
++
++			if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset))
++				set_channel_bwmode(adapter, u_ch, u_offset, u_bw);
++			else
++				rtw_warn_on(1);
++
++			doiqk = _FALSE;
++			rtw_hal_set_hwreg(adapter , HW_VAR_DO_IQK , &doiqk);
++
++			ResumeTxBeacon(adapter);
++			rtw_mi_tx_beacon_hdl(adapter);
++		}
++	}
++
++set_timer:
++	_set_timer(&rfctl->radar_detect_timer
++		, rtw_odm_radar_detect_polling_int_ms(dvobj));
++
++exit:
++	return H2C_SUCCESS;
++}
++
++u8 rtw_dfs_rd_cmd(_adapter *adapter, bool enqueue)
++{
++	struct cmd_obj *cmdobj;
++	struct drvextra_cmd_parm *parm;
++	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
++	u8 res = _FAIL;
++
++	if (enqueue) {
++		cmdobj = rtw_zmalloc(sizeof(struct cmd_obj));
++		if (cmdobj == NULL)
++			goto exit;
++
++		parm = rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++		if (parm == NULL) {
++			rtw_mfree(cmdobj, sizeof(struct cmd_obj));
++			goto exit;
++		}
++
++		parm->ec_id = DFS_RADAR_DETECT_WK_CID;
++		parm->type = 0;
++		parm->size = 0;
++		parm->pbuf = NULL;
++
++		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
++		res = rtw_enqueue_cmd(cmdpriv, cmdobj);
++	} else {
++		rtw_dfs_rd_hdl(adapter);
++		res = _SUCCESS;
++	}
++
++exit:
++	return res;
++}
++
++void rtw_dfs_rd_timer_hdl(void *ctx)
++{
++	struct rf_ctl_t *rfctl = (struct rf_ctl_t *)ctx;
++	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
++
++	rtw_dfs_rd_cmd(dvobj_get_primary_adapter(dvobj), _TRUE);
++}
++
++static void rtw_dfs_rd_enable(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool bypass_cac)
++{
++	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
++	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
++
++	RTW_INFO("%s on %u,%u,%u\n", __func__, ch, bw, offset);
++
++	if (bypass_cac)
++		rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;
++	else if (rtw_is_cac_reset_needed(rfctl, ch, bw, offset) == _TRUE)
++		rtw_reset_cac(rfctl, ch, bw, offset);
++
++	rfctl->radar_detect_by_others = _FALSE;
++	rfctl->radar_detect_ch = ch;
++	rfctl->radar_detect_bw = bw;
++	rfctl->radar_detect_offset = offset;
++
++	rfctl->radar_detected = 0;
++
++	if (IS_CH_WAITING(rfctl))
++		StopTxBeacon(adapter);
++
++	if (!rfctl->radar_detect_enabled) {
++		RTW_INFO("%s set radar_detect_enabled\n", __func__);
++		rfctl->radar_detect_enabled = 1;
++		#ifdef CONFIG_LPS
++		LPS_Leave(adapter, "RADAR_DETECT_EN");
++		#endif
++		_set_timer(&rfctl->radar_detect_timer
++			, rtw_odm_radar_detect_polling_int_ms(dvobj));
++
++		if (rtw_rfctl_overlap_radar_detect_ch(rfctl)) {
++			if (IS_CH_WAITING(rfctl)) {
++				u8 pause = 0xFF;
++
++				rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause);
++			}
++			rtw_odm_radar_detect_enable(adapter);
++		}
++	}
++}
++
++static void rtw_dfs_rd_disable(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool by_others)
++{
++	_adapter *adapter = dvobj_get_primary_adapter(rfctl_to_dvobj(rfctl));
++
++	rfctl->radar_detect_by_others = by_others;
++
++	if (rfctl->radar_detect_enabled) {
++		bool overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl);
++
++		RTW_INFO("%s clear radar_detect_enabled\n", __func__);
++
++		rfctl->radar_detect_enabled = 0;
++		rfctl->radar_detected = 0;
++		rfctl->radar_detect_ch = 0;
++		rfctl->radar_detect_bw = 0;
++		rfctl->radar_detect_offset = 0;
++		rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;
++		_cancel_timer_ex(&rfctl->radar_detect_timer);
++
++		if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_LINKING|WIFI_UNDER_SURVEY) == _FALSE) {
++			ResumeTxBeacon(adapter);
++			rtw_mi_tx_beacon_hdl(adapter);
++		}
++
++		if (overlap_radar_detect_ch) {
++			u8 pause = 0x00;
++
++			rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause);
++			rtw_odm_radar_detect_disable(adapter);
++		}
++	}
++
++	if (by_others) {
++		rfctl->radar_detect_ch = ch;
++		rfctl->radar_detect_bw = bw;
++		rfctl->radar_detect_offset = offset;
++	}
++}
++
++void rtw_dfs_rd_en_decision(_adapter *adapter, u8 mlme_act, u8 excl_ifbmp)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++	struct mi_state mstate;
++	u8 ifbmp;
++	u8 u_ch, u_bw, u_offset;
++	bool ld_sta_in_dfs = _FALSE;
++	bool sync_ch = _FALSE; /* _FALSE: asign channel directly */
++	bool needed = _FALSE;
++
++	if (mlme_act == MLME_OPCH_SWITCH
++		|| mlme_act == MLME_ACTION_NONE
++	) {
++		ifbmp = ~excl_ifbmp;
++		rtw_mi_status_by_ifbmp(dvobj, ifbmp, &mstate);
++		rtw_mi_get_ch_setting_union_by_ifbmp(dvobj, ifbmp, &u_ch, &u_bw, &u_offset);
++	} else {
++		ifbmp = ~excl_ifbmp & ~BIT(adapter->iface_id);
++		rtw_mi_status_by_ifbmp(dvobj, ifbmp, &mstate);
++		rtw_mi_get_ch_setting_union_by_ifbmp(dvobj, ifbmp, &u_ch, &u_bw, &u_offset);
++		if (u_ch != 0)
++			sync_ch = _TRUE;
++
++		switch (mlme_act) {
++		case MLME_STA_CONNECTING:
++			MSTATE_STA_LG_NUM(&mstate)++;
++			break;
++		case MLME_STA_CONNECTED:
++			MSTATE_STA_LD_NUM(&mstate)++;
++			break;
++		case MLME_STA_DISCONNECTED:
++			break;
++#ifdef CONFIG_AP_MODE
++		case MLME_AP_STARTED:
++			MSTATE_AP_NUM(&mstate)++;
++			break;
++		case MLME_AP_STOPPED:
++			break;
++#endif
++#ifdef CONFIG_RTW_MESH
++		case MLME_MESH_STARTED:
++			MSTATE_MESH_NUM(&mstate)++;
++			break;
++		case MLME_MESH_STOPPED:
++			break;
++#endif
++		default:
++			rtw_warn_on(1);
++			break;
++		}
++
++		if (sync_ch == _TRUE) {
++			if (!MLME_IS_OPCH_SW(adapter)) {
++				if (!rtw_is_chbw_grouped(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset, u_ch, u_bw, u_offset)) {
++					RTW_INFO(FUNC_ADPT_FMT" can't sync %u,%u,%u with %u,%u,%u\n", FUNC_ADPT_ARG(adapter)
++						, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset, u_ch, u_bw, u_offset);
++					goto apply;
++				}
++
++				rtw_sync_chbw(&mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset
++					, &u_ch, &u_bw, &u_offset);
++			}
++		} else {
++			u_ch = mlmeext->cur_channel;
++			u_bw = mlmeext->cur_bwmode;
++			u_offset = mlmeext->cur_ch_offset;
++		}
++	}
++
++	if (MSTATE_STA_LG_NUM(&mstate) > 0) {
++		/* STA mode is linking */
++		goto apply;
++	}
++
++	if (MSTATE_STA_LD_NUM(&mstate) > 0) {
++		if (rtw_chset_is_dfs_chbw(rfctl->channel_set, u_ch, u_bw, u_offset)) {
++			/*
++			* if operate as slave w/o radar detect,
++			* rely on AP on which STA mode connects
++			*/
++			if (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_rfctl_dfs_domain_unknown(rfctl))
++				needed = _TRUE;
++			ld_sta_in_dfs = _TRUE;
++		}
++		goto apply;
++	}
++
++	if (!MSTATE_AP_NUM(&mstate) && !MSTATE_MESH_NUM(&mstate)) {
++		/* No working AP/Mesh mode */
++		goto apply;
++	}
++
++	if (rtw_chset_is_dfs_chbw(rfctl->channel_set, u_ch, u_bw, u_offset))
++		needed = _TRUE;
++
++apply:
++
++	RTW_INFO(FUNC_ADPT_FMT" needed:%d, mlme_act:%u, excl_ifbmp:0x%02x\n"
++		, FUNC_ADPT_ARG(adapter), needed, mlme_act, excl_ifbmp);
++	RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num:%u, ap_num:%u, mesh_num:%u, %u,%u,%u\n"
++		, FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_STA_LG_NUM(&mstate)
++		, MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate)
++		, u_ch, u_bw, u_offset);
++
++	if (needed == _TRUE)
++		rtw_dfs_rd_enable(rfctl, u_ch, u_bw, u_offset, ld_sta_in_dfs);
++	else
++		rtw_dfs_rd_disable(rfctl, u_ch, u_bw, u_offset, ld_sta_in_dfs);
++}
++
++u8 rtw_dfs_rd_en_decision_cmd(_adapter *adapter)
++{
++	struct cmd_obj *cmdobj;
++	struct drvextra_cmd_parm *parm;
++	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
++	u8 res = _FAIL;
++
++	cmdobj = rtw_zmalloc(sizeof(struct cmd_obj));
++	if (cmdobj == NULL)
++		goto exit;
++
++	parm = rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (parm == NULL) {
++		rtw_mfree(cmdobj, sizeof(struct cmd_obj));
++		goto exit;
++	}
++
++	parm->ec_id = DFS_RADAR_DETECT_EN_DEC_WK_CID;
++	parm->type = 0;
++	parm->size = 0;
++	parm->pbuf = NULL;
++
++	init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
++	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
++
++exit:
++	return res;
++}
++#endif /* CONFIG_DFS_MASTER */
++
++#endif /* CONFIG_AP_MODE */
++
++#ifdef CONFIG_BT_COEXIST
++struct btinfo {
++	u8 cid;
++	u8 len;
++
++	u8 bConnection:1;
++	u8 bSCOeSCO:1;
++	u8 bInQPage:1;
++	u8 bACLBusy:1;
++	u8 bSCOBusy:1;
++	u8 bHID:1;
++	u8 bA2DP:1;
++	u8 bFTP:1;
++
++	u8 retry_cnt:4;
++	u8 rsvd_34:1;
++	u8 rsvd_35:1;
++	u8 rsvd_36:1;
++	u8 rsvd_37:1;
++
++	u8 rssi;
++
++	u8 rsvd_50:1;
++	u8 rsvd_51:1;
++	u8 rsvd_52:1;
++	u8 rsvd_53:1;
++	u8 rsvd_54:1;
++	u8 rsvd_55:1;
++	u8 eSCO_SCO:1;
++	u8 Master_Slave:1;
++
++	u8 rsvd_6;
++	u8 rsvd_7;
++};
++
++void btinfo_evt_dump(void *sel, void *buf)
++{
++	struct btinfo *info = (struct btinfo *)buf;
++
++	RTW_PRINT_SEL(sel, "cid:0x%02x, len:%u\n", info->cid, info->len);
++
++	if (info->len > 2)
++		RTW_PRINT_SEL(sel, "byte2:%s%s%s%s%s%s%s%s\n"
++			      , info->bConnection ? "bConnection " : ""
++			      , info->bSCOeSCO ? "bSCOeSCO " : ""
++			      , info->bInQPage ? "bInQPage " : ""
++			      , info->bACLBusy ? "bACLBusy " : ""
++			      , info->bSCOBusy ? "bSCOBusy " : ""
++			      , info->bHID ? "bHID " : ""
++			      , info->bA2DP ? "bA2DP " : ""
++			      , info->bFTP ? "bFTP" : ""
++			     );
++
++	if (info->len > 3)
++		RTW_PRINT_SEL(sel, "retry_cnt:%u\n", info->retry_cnt);
++
++	if (info->len > 4)
++		RTW_PRINT_SEL(sel, "rssi:%u\n", info->rssi);
++
++	if (info->len > 5)
++		RTW_PRINT_SEL(sel, "byte5:%s%s\n"
++			      , info->eSCO_SCO ? "eSCO_SCO " : ""
++			      , info->Master_Slave ? "Master_Slave " : ""
++			     );
++}
++
++static void rtw_btinfo_hdl(_adapter *adapter, u8 *buf, u16 buf_len)
++{
++#define BTINFO_WIFI_FETCH 0x23
++#define BTINFO_BT_AUTO_RPT 0x27
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++	struct btinfo_8761ATV *info = (struct btinfo_8761ATV *)buf;
++#else /* !CONFIG_BT_COEXIST_SOCKET_TRX */
++	struct btinfo *info = (struct btinfo *)buf;
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++	u8 cmd_idx;
++	u8 len;
++
++	cmd_idx = info->cid;
++
++	if (info->len > buf_len - 2) {
++		rtw_warn_on(1);
++		len = buf_len - 2;
++	} else
++		len = info->len;
++
++	/* #define DBG_PROC_SET_BTINFO_EVT */
++#ifdef DBG_PROC_SET_BTINFO_EVT
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++	RTW_INFO("%s: btinfo[0]=%x,btinfo[1]=%x,btinfo[2]=%x,btinfo[3]=%x btinfo[4]=%x,btinfo[5]=%x,btinfo[6]=%x,btinfo[7]=%x\n"
++		, __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
++#else/* !CONFIG_BT_COEXIST_SOCKET_TRX */
++	btinfo_evt_dump(RTW_DBGDUMP, info);
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++#endif /* DBG_PROC_SET_BTINFO_EVT */
++
++	/* transform BT-FW btinfo to WiFI-FW C2H format and notify */
++	if (cmd_idx == BTINFO_WIFI_FETCH)
++		buf[1] = 0;
++	else if (cmd_idx == BTINFO_BT_AUTO_RPT)
++		buf[1] = 2;
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++	else if (0x01 == cmd_idx || 0x02 == cmd_idx)
++		buf[1] = buf[0];
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++	rtw_btcoex_BtInfoNotify(adapter , len + 1, &buf[1]);
++}
++
++u8 rtw_btinfo_cmd(_adapter *adapter, u8 *buf, u16 len)
++{
++	struct cmd_obj *ph2c;
++	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++	u8 *btinfo;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++	u8	res = _SUCCESS;
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	btinfo = rtw_zmalloc(len);
++	if (btinfo == NULL) {
++		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
++		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm->ec_id = BTINFO_WK_CID;
++	pdrvextra_cmd_parm->type = 0;
++	pdrvextra_cmd_parm->size = len;
++	pdrvextra_cmd_parm->pbuf = btinfo;
++
++	_rtw_memcpy(btinfo, buf, len);
++
++	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++	return res;
++}
++
++static void rtw_btc_reduce_wl_txpwr_hdl(_adapter *adapter, u32 pwr_lvl)
++{
++	rtw_btcoex_set_reduced_wl_pwr_lvl(adapter, pwr_lvl);
++	rtw_btcoex_do_reduce_wl_pwr_lvl(adapter);
++
++	RTW_INFO(FUNC_ADPT_FMT ": BTC reduce WL TxPwr %d dB!\n",
++		 FUNC_ADPT_ARG(adapter), pwr_lvl);
++}
++
++u8 rtw_btc_reduce_wl_txpwr_cmd(_adapter *adapter, u32 val)
++{
++	struct cmd_obj *pcmdobj;
++	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++	u8	res = _SUCCESS;
++
++	pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (pcmdobj == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm->ec_id = BTC_REDUCE_WL_TXPWR_CID;
++	pdrvextra_cmd_parm->type = val;
++	pdrvextra_cmd_parm->size = 0;
++	pdrvextra_cmd_parm->pbuf = NULL;
++
++	init_h2fwcmd_w_parm_no_rsp(pcmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++	res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
++
++exit:
++	return res;
++}
++#endif /* CONFIG_BT_COEXIST */
++
++u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len)
++{
++	struct cmd_obj *pcmdobj;
++	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++	u8 *ph2c_content;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++	u8	res = _SUCCESS;
++
++	pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (pcmdobj == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	ph2c_content = rtw_zmalloc(len);
++	if (ph2c_content == NULL) {
++		rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));
++		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm->ec_id = TEST_H2C_CID;
++	pdrvextra_cmd_parm->type = 0;
++	pdrvextra_cmd_parm->size = len;
++	pdrvextra_cmd_parm->pbuf = ph2c_content;
++
++	_rtw_memcpy(ph2c_content, buf, len);
++
++	init_h2fwcmd_w_parm_no_rsp(pcmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++	res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
++
++exit:
++	return res;
++}
++
++#ifdef CONFIG_MP_INCLUDED
++static s32 rtw_mp_cmd_hdl(_adapter *padapter, u8 mp_cmd_id)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	int ret = H2C_SUCCESS;
++	uint status = _SUCCESS;
++
++	if (mp_cmd_id == MP_START) {
++		if (padapter->registrypriv.mp_mode == 0) {
++			rtw_intf_stop(padapter);
++			rtw_hal_deinit(padapter);
++			padapter->registrypriv.mp_mode = 1;
++#ifdef CONFIG_BT_COEXIST
++		padapter->mppriv.CureFuseBTCoex = pHalData->EEPROMBluetoothCoexist;
++		pHalData->EEPROMBluetoothCoexist = _FALSE;
++#endif
++#ifdef CONFIG_RF_POWER_TRIM
++			if (!IS_HARDWARE_TYPE_8814A(padapter) && !IS_HARDWARE_TYPE_8822B(padapter) && !IS_HARDWARE_TYPE_8822C(padapter)) {
++				padapter->registrypriv.RegPwrTrimEnable = 1;
++				rtw_hal_read_chip_info(padapter);
++			}
++#endif /*CONFIG_RF_POWER_TRIM*/
++			rtw_reset_drv_sw(padapter);
++#ifdef CONFIG_NEW_NETDEV_HDL
++			if (!rtw_is_hw_init_completed(padapter)) {
++				status = rtw_hal_init(padapter);
++				if (status == _FAIL) {
++					ret = H2C_REJECTED;
++					goto exit;
++				}
++				rtw_hal_iface_init(padapter);
++			}
++#else
++			status = rtw_hal_init(padapter);
++			if (status == _FAIL) {
++				ret = H2C_REJECTED;
++				goto exit;
++			}
++#endif /*CONFIG_NEW_NETDEV_HDL*/
++#ifndef RTW_HALMAC
++			rtw_intf_start(padapter);
++#endif /* !RTW_HALMAC */
++#ifdef RTW_HALMAC /*for New IC*/
++			MPT_InitializeAdapter(padapter, 1);
++#endif /* CONFIG_MP_INCLUDED */
++		}
++
++		if (padapter->registrypriv.mp_mode == 0) {
++			ret = H2C_REJECTED;
++			goto exit;
++		}
++
++		if (padapter->mppriv.mode == MP_OFF) {
++			if (mp_start_test(padapter) == _FAIL) {
++				ret = H2C_REJECTED;
++				goto exit;
++			}
++			padapter->mppriv.mode = MP_ON;
++			MPT_PwrCtlDM(padapter, 0);
++		}
++		padapter->mppriv.bmac_filter = _FALSE;
++#ifdef CONFIG_RTL8723B
++#ifdef CONFIG_USB_HCI
++		rtw_write32(padapter, 0x765, 0x0000);
++		rtw_write32(padapter, 0x948, 0x0280);
++#else
++		rtw_write32(padapter, 0x765, 0x0000);
++		rtw_write32(padapter, 0x948, 0x0000);
++#endif
++#ifdef CONFIG_FOR_RTL8723BS_VQ0
++		rtw_write32(padapter, 0x765, 0x0000);
++		rtw_write32(padapter, 0x948, 0x0280);
++#endif
++		rtw_write8(padapter, 0x66, 0x27); /*Open BT uart Log*/
++		rtw_write8(padapter, 0xc50, 0x20); /*for RX init Gain*/
++#endif
++		odm_write_dig(&pHalData->odmpriv, 0x20);
++
++	} else if (mp_cmd_id == MP_STOP) {
++		if (padapter->registrypriv.mp_mode == 1) {
++			MPT_DeInitAdapter(padapter);
++			rtw_intf_stop(padapter);
++			rtw_hal_deinit(padapter);
++			padapter->registrypriv.mp_mode = 0;
++#ifdef CONFIG_BT_COEXIST
++			pHalData->EEPROMBluetoothCoexist = padapter->mppriv.CureFuseBTCoex;
++#endif
++			rtw_reset_drv_sw(padapter);
++#ifdef CONFIG_NEW_NETDEV_HDL
++			if (!rtw_is_hw_init_completed(padapter)) {
++				status = rtw_hal_init(padapter);
++				if (status == _FAIL) {
++					ret = H2C_REJECTED;
++					goto exit;
++				}
++				rtw_hal_iface_init(padapter);
++			}
++#else
++			status = rtw_hal_init(padapter);
++			if (status == _FAIL) {
++				ret = H2C_REJECTED;
++				goto exit;
++			}
++#endif /*CONFIG_NEW_NETDEV_HDL*/
++#ifndef RTW_HALMAC
++			rtw_intf_start(padapter);
++#endif /* !RTW_HALMAC */
++		}
++
++		if (padapter->mppriv.mode != MP_OFF) {
++			mp_stop_test(padapter);
++			padapter->mppriv.mode = MP_OFF;
++		}
++
++	} else {
++		RTW_INFO(FUNC_ADPT_FMT"invalid id:%d\n", FUNC_ADPT_ARG(padapter), mp_cmd_id);
++		ret = H2C_PARAMETERS_ERROR;
++		rtw_warn_on(1);
++	}
++
++exit:
++	return ret;
++}
++
++u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags)
++{
++	struct cmd_obj *cmdobj;
++	struct drvextra_cmd_parm *parm;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++	struct submit_ctx sctx;
++	u8	res = _SUCCESS;
++
++	parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (parm == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	parm->ec_id = MP_CMD_WK_CID;
++	parm->type = mp_cmd_id;
++	parm->size = 0;
++	parm->pbuf = NULL;
++
++	if (flags & RTW_CMDF_DIRECTLY) {
++		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
++		if (H2C_SUCCESS != rtw_mp_cmd_hdl(adapter, mp_cmd_id))
++			res = _FAIL;
++		rtw_mfree((u8 *)parm, sizeof(*parm));
++	} else {
++		/* need enqueue, prepare cmd_obj and enqueue */
++		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
++		if (cmdobj == NULL) {
++			res = _FAIL;
++			rtw_mfree((u8 *)parm, sizeof(*parm));
++			goto exit;
++		}
++
++		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
++
++		if (flags & RTW_CMDF_WAIT_ACK) {
++			cmdobj->sctx = &sctx;
++			rtw_sctx_init(&sctx, 10 * 1000);
++		}
++
++		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
++
++		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
++			rtw_sctx_wait(&sctx, __func__);
++			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status == RTW_SCTX_SUBMITTED)
++				cmdobj->sctx = NULL;
++			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++			if (sctx.status != RTW_SCTX_DONE_SUCCESS)
++				res = _FAIL;
++		}
++	}
++
++exit:
++	return res;
++}
++#endif	/*CONFIG_MP_INCLUDED*/
++
++#ifdef CONFIG_RTW_CUSTOMER_STR
++static s32 rtw_customer_str_cmd_hdl(_adapter *adapter, u8 write, const u8 *cstr)
++{
++	int ret = H2C_SUCCESS;
++
++	if (write)
++		ret = rtw_hal_h2c_customer_str_write(adapter, cstr);
++	else
++		ret = rtw_hal_h2c_customer_str_req(adapter);
++
++	return ret == _SUCCESS ? H2C_SUCCESS : H2C_REJECTED;
++}
++
++static u8 rtw_customer_str_cmd(_adapter *adapter, u8 write, const u8 *cstr)
++{
++	struct cmd_obj *cmdobj;
++	struct drvextra_cmd_parm *parm;
++	u8 *str = NULL;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++	struct submit_ctx sctx;
++	u8 res = _SUCCESS;
++
++	parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (parm == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	if (write) {
++		str = rtw_zmalloc(RTW_CUSTOMER_STR_LEN);
++		if (str == NULL) {
++			rtw_mfree((u8 *)parm, sizeof(struct drvextra_cmd_parm));
++			res = _FAIL;
++			goto exit;
++		}
++	}
++
++	parm->ec_id = CUSTOMER_STR_WK_CID;
++	parm->type = write;
++	parm->size = write ? RTW_CUSTOMER_STR_LEN : 0;
++	parm->pbuf = write ? str : NULL;
++
++	if (write)
++		_rtw_memcpy(str, cstr, RTW_CUSTOMER_STR_LEN);
++
++	/* need enqueue, prepare cmd_obj and enqueue */
++	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
++	if (cmdobj == NULL) {
++		res = _FAIL;
++		rtw_mfree((u8 *)parm, sizeof(*parm));
++		if (write)
++			rtw_mfree(str, RTW_CUSTOMER_STR_LEN);
++		goto exit;
++	}
++
++	init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
++
++	cmdobj->sctx = &sctx;
++	rtw_sctx_init(&sctx, 2 * 1000);
++
++	res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
++
++	if (res == _SUCCESS) {
++		rtw_sctx_wait(&sctx, __func__);
++		_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++		if (sctx.status == RTW_SCTX_SUBMITTED)
++			cmdobj->sctx = NULL;
++		_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++		if (sctx.status != RTW_SCTX_DONE_SUCCESS)
++			res = _FAIL;
++	}
++
++exit:
++	return res;
++}
++
++inline u8 rtw_customer_str_req_cmd(_adapter *adapter)
++{
++	return rtw_customer_str_cmd(adapter, 0, NULL);
++}
++
++inline u8 rtw_customer_str_write_cmd(_adapter *adapter, const u8 *cstr)
++{
++	return rtw_customer_str_cmd(adapter, 1, cstr);
++}
++#endif /* CONFIG_RTW_CUSTOMER_STR */
++
++u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *pbuf, u16 length, u8 type)
++{
++	struct cmd_obj *ph2c;
++	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++	u8 *extra_cmd_buf;
++	u8 res = _SUCCESS;
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	extra_cmd_buf = rtw_zmalloc(length);
++	if (extra_cmd_buf == NULL) {
++		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
++		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
++		res = _FAIL;
++		goto exit;
++	}
++
++	_rtw_memcpy(extra_cmd_buf, pbuf, length);
++	pdrvextra_cmd_parm->ec_id = C2H_WK_CID;
++	pdrvextra_cmd_parm->type = type;
++	pdrvextra_cmd_parm->size = length;
++	pdrvextra_cmd_parm->pbuf = extra_cmd_buf;
++
++	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++	return res;
++}
++
++#ifdef CONFIG_FW_C2H_REG
++inline u8 rtw_c2h_reg_wk_cmd(_adapter *adapter, u8 *c2h_evt)
++{
++	return rtw_c2h_wk_cmd(adapter, c2h_evt, c2h_evt ? C2H_REG_LEN : 0, C2H_TYPE_REG);
++}
++#endif
++
++#ifdef CONFIG_FW_C2H_PKT
++inline u8 rtw_c2h_packet_wk_cmd(_adapter *adapter, u8 *c2h_evt, u16 length)
++{
++	return rtw_c2h_wk_cmd(adapter, c2h_evt, length, C2H_TYPE_PKT);
++}
++#endif
++
++static u8 _rtw_run_in_thread_cmd(_adapter *adapter, void (*func)(void *), void *context, s32 timeout_ms)
++{
++	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
++	struct cmd_obj *cmdobj;
++	struct RunInThread_param *parm;
++	struct submit_ctx sctx;
++	s32 res = _SUCCESS;
++
++	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (NULL == cmdobj) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	parm = (struct RunInThread_param *)rtw_zmalloc(sizeof(struct RunInThread_param));
++	if (NULL == parm) {
++		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	parm->func = func;
++	parm->context = context;
++	init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_RUN_INTHREAD);
++
++	if (timeout_ms >= 0) {
++		cmdobj->sctx = &sctx;
++		rtw_sctx_init(&sctx, timeout_ms);
++	}
++
++	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
++
++	if (res == _SUCCESS && timeout_ms >= 0) {
++		rtw_sctx_wait(&sctx, __func__);
++		_enter_critical_mutex(&cmdpriv->sctx_mutex, NULL);
++		if (sctx.status == RTW_SCTX_SUBMITTED)
++			cmdobj->sctx = NULL;
++		_exit_critical_mutex(&cmdpriv->sctx_mutex, NULL);
++		if (sctx.status != RTW_SCTX_DONE_SUCCESS)
++			res = _FAIL;
++	}
++
++exit:
++	return res;
++}
++
++u8 rtw_run_in_thread_cmd(_adapter *adapter, void (*func)(void *), void *context)
++{
++	return _rtw_run_in_thread_cmd(adapter, func, context, -1);
++}
++
++u8 rtw_run_in_thread_cmd_wait(_adapter *adapter, void (*func)(void *), void *context, s32 timeout_ms)
++{
++	return _rtw_run_in_thread_cmd(adapter, func, context, timeout_ms);
++}
++
++#ifdef CONFIG_FW_C2H_REG
++s32 c2h_evt_hdl(_adapter *adapter, u8 *c2h_evt, c2h_id_filter filter)
++{
++	s32 ret = _FAIL;
++	u8 buf[C2H_REG_LEN] = {0};
++	u8 id, seq, plen;
++	u8 *payload;
++
++	if (!c2h_evt) {
++		/* No c2h event in cmd_obj, read c2h event before handling*/
++		if (rtw_hal_c2h_evt_read(adapter, buf) != _SUCCESS)
++			goto exit;
++		c2h_evt = buf;
++	}
++
++	rtw_hal_c2h_reg_hdr_parse(adapter, c2h_evt, &id, &seq, &plen, &payload);
++
++	if (filter && filter(adapter, id, seq, plen, payload) == _FALSE)
++		goto exit;
++
++	ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
++
++exit:
++	return ret;
++}
++#endif /* CONFIG_FW_C2H_REG */
++
++u8 session_tracker_cmd(_adapter *adapter, u8 cmd, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
++{
++	struct cmd_priv	*cmdpriv = &adapter->cmdpriv;
++	struct cmd_obj *cmdobj;
++	struct drvextra_cmd_parm *cmd_parm;
++	struct st_cmd_parm *st_parm;
++	u8	res = _SUCCESS;
++
++	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (cmdobj == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (cmd_parm == NULL) {
++		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	st_parm = (struct st_cmd_parm *)rtw_zmalloc(sizeof(struct st_cmd_parm));
++	if (st_parm == NULL) {
++		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
++		rtw_mfree((u8 *)cmd_parm, sizeof(struct drvextra_cmd_parm));
++		res = _FAIL;
++		goto exit;
++	}
++
++	st_parm->cmd = cmd;
++	st_parm->sta = sta;
++	if (cmd != ST_CMD_CHK) {
++		_rtw_memcpy(&st_parm->local_naddr, local_naddr, 4);
++		_rtw_memcpy(&st_parm->local_port, local_port, 2);
++		_rtw_memcpy(&st_parm->remote_naddr, remote_naddr, 4);
++		_rtw_memcpy(&st_parm->remote_port, remote_port, 2);
++	}
++
++	cmd_parm->ec_id = SESSION_TRACKER_WK_CID;
++	cmd_parm->type = 0;
++	cmd_parm->size = sizeof(struct st_cmd_parm);
++	cmd_parm->pbuf = (u8 *)st_parm;
++	init_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, CMD_SET_DRV_EXTRA);
++	cmdobj->no_io = 1;
++
++	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
++
++exit:
++	return res;
++}
++
++inline u8 session_tracker_chk_cmd(_adapter *adapter, struct sta_info *sta)
++{
++	return session_tracker_cmd(adapter, ST_CMD_CHK, sta, NULL, NULL, NULL, NULL);
++}
++
++inline u8 session_tracker_add_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
++{
++	return session_tracker_cmd(adapter, ST_CMD_ADD, sta, local_naddr, local_port, remote_naddr, remote_port);
++}
++
++inline u8 session_tracker_del_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
++{
++	return session_tracker_cmd(adapter, ST_CMD_DEL, sta, local_naddr, local_port, remote_naddr, remote_port);
++}
++
++void session_tracker_chk_for_sta(_adapter *adapter, struct sta_info *sta)
++{
++	struct st_ctl_t *st_ctl = &sta->st_ctl;
++	int i;
++	_irqL irqL;
++	_list *plist, *phead, *pnext;
++	_list dlist;
++	struct session_tracker *st = NULL;
++	u8 op_wfd_mode = MIRACAST_DISABLED;
++
++	if (DBG_SESSION_TRACKER)
++		RTW_INFO(FUNC_ADPT_FMT" sta:%p\n", FUNC_ADPT_ARG(adapter), sta);
++
++	if (!(sta->state & WIFI_ASOC_STATE))
++		goto exit;
++
++	for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) {
++		if (st_ctl->reg[i].s_proto != 0)
++			break;
++	}
++	if (i >= SESSION_TRACKER_REG_ID_NUM)
++		goto chk_sta;
++
++	_rtw_init_listhead(&dlist);
++
++	_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);
++
++	phead = &st_ctl->tracker_q.queue;
++	plist = get_next(phead);
++	pnext = get_next(plist);
++	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
++		st = LIST_CONTAINOR(plist, struct session_tracker, list);
++		plist = pnext;
++		pnext = get_next(pnext);
++
++		if (st->status != ST_STATUS_ESTABLISH
++			&& rtw_get_passing_time_ms(st->set_time) > ST_EXPIRE_MS
++		) {
++			rtw_list_delete(&st->list);
++			rtw_list_insert_tail(&st->list, &dlist);
++		}
++
++		/* TODO: check OS for status update */
++		if (st->status == ST_STATUS_CHECK)
++			st->status = ST_STATUS_ESTABLISH;
++
++		if (st->status != ST_STATUS_ESTABLISH)
++			continue;
++
++		#ifdef CONFIG_WFD
++		if (0)
++			RTW_INFO(FUNC_ADPT_FMT" local:%u, remote:%u, rtsp:%u, %u, %u\n", FUNC_ADPT_ARG(adapter)
++				, ntohs(st->local_port), ntohs(st->remote_port), adapter->wfd_info.rtsp_ctrlport, adapter->wfd_info.tdls_rtsp_ctrlport
++				, adapter->wfd_info.peer_rtsp_ctrlport);
++		if (ntohs(st->local_port) == adapter->wfd_info.rtsp_ctrlport)
++			op_wfd_mode |= MIRACAST_SINK;
++		if (ntohs(st->local_port) == adapter->wfd_info.tdls_rtsp_ctrlport)
++			op_wfd_mode |= MIRACAST_SINK;
++		if (ntohs(st->remote_port) == adapter->wfd_info.peer_rtsp_ctrlport)
++			op_wfd_mode |= MIRACAST_SOURCE;
++		#endif
++	}
++
++	_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
++
++	plist = get_next(&dlist);
++	while (rtw_end_of_queue_search(&dlist, plist) == _FALSE) {
++		st = LIST_CONTAINOR(plist, struct session_tracker, list);
++		plist = get_next(plist);
++		rtw_mfree((u8 *)st, sizeof(struct session_tracker));
++	}
++
++chk_sta:
++	if (STA_OP_WFD_MODE(sta) != op_wfd_mode) {
++		STA_SET_OP_WFD_MODE(sta, op_wfd_mode);
++		rtw_sta_media_status_rpt_cmd(adapter, sta, 1);
++	}
++
++exit:
++	return;
++}
++
++void session_tracker_chk_for_adapter(_adapter *adapter)
++{
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct sta_info *sta;
++	int i;
++	_irqL irqL;
++	_list *plist, *phead;
++	u8 op_wfd_mode = MIRACAST_DISABLED;
++
++	_enter_critical_bh(&stapriv->sta_hash_lock, &irqL);
++
++	for (i = 0; i < NUM_STA; i++) {
++		phead = &(stapriv->sta_hash[i]);
++		plist = get_next(phead);
++
++		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++			sta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++			plist = get_next(plist);
++
++			session_tracker_chk_for_sta(adapter, sta);
++
++			op_wfd_mode |= STA_OP_WFD_MODE(sta);
++		}
++	}
++
++	_exit_critical_bh(&stapriv->sta_hash_lock, &irqL);
++
++#ifdef CONFIG_WFD
++	adapter->wfd_info.op_wfd_mode = MIRACAST_MODE_REVERSE(op_wfd_mode);
++#endif
++}
++
++void session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm)
++{
++	u8 cmd = parm->cmd;
++	struct sta_info *sta = parm->sta;
++
++	if (cmd == ST_CMD_CHK) {
++		if (sta)
++			session_tracker_chk_for_sta(adapter, sta);
++		else
++			session_tracker_chk_for_adapter(adapter);
++
++		goto exit;
++
++	} else if (cmd == ST_CMD_ADD || cmd == ST_CMD_DEL) {
++		struct st_ctl_t *st_ctl;
++		u32 local_naddr = parm->local_naddr;
++		u16 local_port = parm->local_port;
++		u32 remote_naddr = parm->remote_naddr;
++		u16 remote_port = parm->remote_port;
++		struct session_tracker *st = NULL;
++		_irqL irqL;
++		_list *plist, *phead;
++		u8 free_st = 0;
++		u8 alloc_st = 0;
++
++		if (DBG_SESSION_TRACKER)
++			RTW_INFO(FUNC_ADPT_FMT" cmd:%u, sta:%p, local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT"\n"
++				, FUNC_ADPT_ARG(adapter), cmd, sta
++				, IP_ARG(&local_naddr), PORT_ARG(&local_port)
++				, IP_ARG(&remote_naddr), PORT_ARG(&remote_port)
++			);
++
++		if (!(sta->state & WIFI_ASOC_STATE))
++			goto exit;
++
++		st_ctl = &sta->st_ctl;
++
++		_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);
++
++		phead = &st_ctl->tracker_q.queue;
++		plist = get_next(phead);
++		while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
++			st = LIST_CONTAINOR(plist, struct session_tracker, list);
++
++			if (st->local_naddr == local_naddr
++				&& st->local_port == local_port
++				&& st->remote_naddr == remote_naddr
++				&& st->remote_port == remote_port)
++				break;
++
++			plist = get_next(plist);
++		}
++
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			st = NULL;
++
++		switch (cmd) {
++		case ST_CMD_DEL:
++			if (st) {
++				rtw_list_delete(plist);
++				free_st = 1;
++			}
++			goto unlock;
++		case ST_CMD_ADD:
++			if (!st)
++				alloc_st = 1;
++		}
++
++unlock:
++		_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
++
++		if (free_st) {
++			rtw_mfree((u8 *)st, sizeof(struct session_tracker));
++			goto exit;
++		}
++
++		if (alloc_st) {
++			st = (struct session_tracker *)rtw_zmalloc(sizeof(struct session_tracker));
++			if (!st)
++				goto exit;
++
++			st->local_naddr = local_naddr;
++			st->local_port = local_port;
++			st->remote_naddr = remote_naddr;
++			st->remote_port = remote_port;
++			st->set_time = rtw_get_current_time();
++			st->status = ST_STATUS_CHECK;
++
++			_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);
++			rtw_list_insert_tail(&st->list, phead);
++			_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
++		}
++	}
++
++exit:
++	return;
++}
++
++#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW)
++static s32 rtw_req_per_cmd_hdl(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++	struct macid_bmp req_macid_bmp, *macid_bmp;
++	u8 i, ret = _FAIL;
++
++	macid_bmp = &macid_ctl->if_g[adapter->iface_id];
++	_rtw_memcpy(&req_macid_bmp, macid_bmp, sizeof(struct macid_bmp));
++
++	/* Clear none mesh's macid */
++	for (i = 0; i < macid_ctl->num; i++) {
++		u8 role;
++		role = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]);
++		if (role != H2C_MSR_ROLE_MESH)
++			rtw_macid_map_clr(&req_macid_bmp, i);
++	}
++
++	/* group_macid: always be 0 in NIC, so only pass macid_bitmap.m0
++	 * rpt_type: 0 includes all info in 1, use 0 for now 
++	 * macid_bitmap: pass m0 only for NIC
++	 */
++	ret = rtw_hal_set_req_per_rpt_cmd(adapter, 0, 0, req_macid_bmp.m0);
++
++	return ret;
++}
++
++u8 rtw_req_per_cmd(_adapter *adapter)
++{
++	struct cmd_obj *cmdobj;
++	struct drvextra_cmd_parm *parm;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++	struct submit_ctx sctx;
++	u8 res = _SUCCESS;
++
++	parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (parm == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	parm->ec_id = REQ_PER_CMD_WK_CID;
++	parm->type = 0;
++	parm->size = 0;
++	parm->pbuf = NULL;
++
++	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
++	if (cmdobj == NULL) {
++		res = _FAIL;
++		rtw_mfree((u8 *)parm, sizeof(*parm));
++		goto exit;
++	}
++
++	init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
++
++	res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
++
++exit:
++	return res;
++}
++#endif
++
++
++void rtw_ac_parm_cmd_hdl(_adapter *padapter, u8 *_ac_parm_buf, int ac_type)
++{
++
++	u32 ac_parm_buf;
++
++	_rtw_memcpy(&ac_parm_buf, _ac_parm_buf, sizeof(ac_parm_buf));
++	switch (ac_type) {
++	case XMIT_VO_QUEUE:
++		RTW_INFO(FUNC_NDEV_FMT" AC_VO = 0x%08x\n", FUNC_ADPT_ARG(padapter), (unsigned int) ac_parm_buf);
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&ac_parm_buf));
++		break;
++
++	case XMIT_VI_QUEUE:
++		RTW_INFO(FUNC_NDEV_FMT" AC_VI = 0x%08x\n", FUNC_ADPT_ARG(padapter), (unsigned int) ac_parm_buf);
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&ac_parm_buf));
++		break;
++
++	case XMIT_BE_QUEUE:
++		RTW_INFO(FUNC_NDEV_FMT" AC_BE = 0x%08x\n", FUNC_ADPT_ARG(padapter), (unsigned int) ac_parm_buf);
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&ac_parm_buf));
++		break;
++
++	case XMIT_BK_QUEUE:
++		RTW_INFO(FUNC_NDEV_FMT" AC_BK = 0x%08x\n", FUNC_ADPT_ARG(padapter), (unsigned int) ac_parm_buf);
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&ac_parm_buf));
++		break;
++
++	default:
++		break;
++	}
++
++}
++
++
++u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++	int ret = H2C_SUCCESS;
++	struct drvextra_cmd_parm *pdrvextra_cmd;
++
++	if (!pbuf)
++		return H2C_PARAMETERS_ERROR;
++
++	pdrvextra_cmd = (struct drvextra_cmd_parm *)pbuf;
++
++	switch (pdrvextra_cmd->ec_id) {
++	case STA_MSTATUS_RPT_WK_CID:
++		rtw_sta_media_status_rpt_cmd_hdl(padapter, (struct sta_media_status_rpt_cmd_parm *)pdrvextra_cmd->pbuf);
++		break;
++
++	case DYNAMIC_CHK_WK_CID:/*only  primary padapter go to this cmd, but execute dynamic_chk_wk_hdl() for two interfaces */
++		rtw_dynamic_chk_wk_hdl(padapter);
++		break;
++	case POWER_SAVING_CTRL_WK_CID:
++		power_saving_wk_hdl(padapter);
++		break;
++#ifdef CONFIG_LPS
++	case LPS_CTRL_WK_CID:
++		lps_ctrl_wk_hdl(padapter, (u8)pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
++		break;
++	case DM_IN_LPS_WK_CID:
++		rtw_dm_in_lps_hdl(padapter);
++		break;
++	case LPS_CHANGE_DTIM_CID:
++		rtw_lps_change_dtim_hdl(padapter, (u8)pdrvextra_cmd->type);
++		break;
++#endif
++#if (RATE_ADAPTIVE_SUPPORT == 1)
++	case RTP_TIMER_CFG_WK_CID:
++		rpt_timer_setting_wk_hdl(padapter, pdrvextra_cmd->type);
++		break;
++#endif
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	case ANT_SELECT_WK_CID:
++		antenna_select_wk_hdl(padapter, pdrvextra_cmd->type);
++		break;
++#endif
++#ifdef CONFIG_P2P_PS
++	case P2P_PS_WK_CID:
++		p2p_ps_wk_hdl(padapter, pdrvextra_cmd->type);
++		break;
++#endif
++#ifdef CONFIG_P2P
++	case P2P_PROTO_WK_CID:
++		/*
++		* Commented by Albert 2011/07/01
++		* I used the type_size as the type command
++		*/
++		ret = p2p_protocol_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
++		break;
++#endif
++#ifdef CONFIG_AP_MODE
++	case CHECK_HIQ_WK_CID:
++		rtw_chk_hi_queue_hdl(padapter);
++		break;
++#endif
++	/* add for CONFIG_IEEE80211W, none 11w can use it */
++	case RESET_SECURITYPRIV:
++		reset_securitypriv_hdl(padapter);
++		break;
++	case FREE_ASSOC_RESOURCES:
++		free_assoc_resources_hdl(padapter, (u8)pdrvextra_cmd->type);
++		break;
++	case C2H_WK_CID:
++		switch (pdrvextra_cmd->type) {
++		#ifdef CONFIG_FW_C2H_REG
++		case C2H_TYPE_REG:
++			c2h_evt_hdl(padapter, pdrvextra_cmd->pbuf, NULL);
++			break;
++		#endif
++		#ifdef CONFIG_FW_C2H_PKT
++		case C2H_TYPE_PKT:
++			rtw_hal_c2h_pkt_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->size);
++			break;
++		#endif
++		default:
++			RTW_ERR("unknown C2H type:%d\n", pdrvextra_cmd->type);
++			rtw_warn_on(1);
++			break;
++		}
++		break;
++#ifdef CONFIG_BEAMFORMING
++	case BEAMFORMING_WK_CID:
++		beamforming_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
++		break;
++#endif
++	case DM_RA_MSK_WK_CID:
++		rtw_dm_ra_mask_hdl(padapter, (struct sta_info *)pdrvextra_cmd->pbuf);
++		break;
++#ifdef CONFIG_BT_COEXIST
++	case BTINFO_WK_CID:
++		rtw_btinfo_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->size);
++		break;
++	case BTC_REDUCE_WL_TXPWR_CID:
++		rtw_btc_reduce_wl_txpwr_hdl(padapter, pdrvextra_cmd->type);
++		break;
++#endif
++#ifdef CONFIG_DFS_MASTER
++	case DFS_RADAR_DETECT_WK_CID:
++		rtw_dfs_rd_hdl(padapter);
++		break;
++	case DFS_RADAR_DETECT_EN_DEC_WK_CID:
++		rtw_dfs_rd_en_decision(padapter, MLME_ACTION_NONE, 0);
++		break;
++#endif
++	case SESSION_TRACKER_WK_CID:
++		session_tracker_cmd_hdl(padapter, (struct st_cmd_parm *)pdrvextra_cmd->pbuf);
++		break;
++	case EN_HW_UPDATE_TSF_WK_CID:
++		rtw_hal_set_hwreg(padapter, HW_VAR_EN_HW_UPDATE_TSF, NULL);
++		break;
++	case PERIOD_TSF_UPDATE_END_WK_CID:
++		rtw_hal_periodic_tsf_update_chk(padapter);
++		break;
++	case TEST_H2C_CID:
++		rtw_hal_fill_h2c_cmd(padapter, pdrvextra_cmd->pbuf[0], pdrvextra_cmd->size - 1, &pdrvextra_cmd->pbuf[1]);
++		break;
++	case MP_CMD_WK_CID:
++#ifdef CONFIG_MP_INCLUDED
++		ret = rtw_mp_cmd_hdl(padapter, pdrvextra_cmd->type);
++#endif
++		break;
++#ifdef CONFIG_RTW_CUSTOMER_STR
++	case CUSTOMER_STR_WK_CID:
++		ret = rtw_customer_str_cmd_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
++		break;
++#endif
++
++#ifdef CONFIG_RTW_REPEATER_SON
++	case RSON_SCAN_WK_CID:
++		rtw_rson_scan_cmd_hdl(padapter, pdrvextra_cmd->type);
++		break;
++#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++	case MGNT_TX_WK_CID:
++		ret = rtw_mgnt_tx_handler(padapter, pdrvextra_cmd->pbuf);
++		break;
++#endif /* CONFIG_IOCTL_CFG80211 */
++#ifdef CONFIG_MCC_MODE
++	case MCC_CMD_WK_CID:
++		ret = rtw_mcc_cmd_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
++		break;
++#endif /* CONFIG_MCC_MODE */
++#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW)
++	case REQ_PER_CMD_WK_CID:
++		ret = rtw_req_per_cmd_hdl(padapter);
++		break;
++#endif
++#ifdef CONFIG_SUPPORT_STATIC_SMPS
++	case SSMPS_WK_CID :
++		rtw_ssmps_wk_hdl(padapter, (struct ssmps_cmd_parm *)pdrvextra_cmd->pbuf);
++		break;
++#endif
++#ifdef CONFIG_CTRL_TXSS_BY_TP
++	case TXSS_WK_CID :
++		rtw_ctrl_txss_wk_hdl(padapter, (struct txss_cmd_parm *)pdrvextra_cmd->pbuf);
++		break;
++#endif
++	case AC_PARM_CMD_WK_CID:
++		rtw_ac_parm_cmd_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type);
++		break;
++#ifdef CONFIG_AP_MODE
++	case STOP_AP_WK_CID:
++		stop_ap_hdl(padapter);
++		break;
++#endif
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	case TBTX_CONTROL_TX_WK_CID:
++		tx_control_hdl(padapter);
++		break;
++#endif
++	default:
++		break;
++	}
++
++	if (pdrvextra_cmd->pbuf && pdrvextra_cmd->size > 0)
++		rtw_mfree(pdrvextra_cmd->pbuf, pdrvextra_cmd->size);
++
++	return ret;
++}
++
++void rtw_survey_cmd_callback(_adapter	*padapter ,  struct cmd_obj *pcmd)
++{
++	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++
++	if (pcmd->res == H2C_DROPPED) {
++		/* TODO: cancel timer and do timeout handler directly... */
++		/* need to make timeout handlerOS independent */
++		mlme_set_scan_to_timer(pmlmepriv, 1);
++	} else if (pcmd->res != H2C_SUCCESS) {
++		mlme_set_scan_to_timer(pmlmepriv, 1);
++	}
++
++	/* free cmd */
++	rtw_free_cmd_obj(pcmd);
++
++}
++void rtw_disassoc_cmd_callback(_adapter	*padapter,  struct cmd_obj *pcmd)
++{
++	_irqL	irqL;
++	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++
++	if (pcmd->res != H2C_SUCCESS) {
++		_enter_critical_bh(&pmlmepriv->lock, &irqL);
++		set_fwstate(pmlmepriv, WIFI_ASOC_STATE);
++		_exit_critical_bh(&pmlmepriv->lock, &irqL);
++		goto exit;
++	}
++#ifdef CONFIG_BR_EXT
++	else /* clear bridge database */
++		nat25_db_cleanup(padapter);
++#endif /* CONFIG_BR_EXT */
++
++	/* free cmd */
++	rtw_free_cmd_obj(pcmd);
++
++exit:
++	return;
++}
++
++void rtw_joinbss_cmd_callback(_adapter	*padapter,  struct cmd_obj *pcmd)
++{
++	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++
++	if (pcmd->res == H2C_DROPPED) {
++		/* TODO: cancel timer and do timeout handler directly... */
++		/* need to make timeout handlerOS independent */
++		_set_timer(&pmlmepriv->assoc_timer, 1);
++	} else if (pcmd->res != H2C_SUCCESS)
++		_set_timer(&pmlmepriv->assoc_timer, 1);
++
++	rtw_free_cmd_obj(pcmd);
++
++}
++
++void rtw_create_ibss_post_hdl(_adapter *padapter, int status)
++{
++	_irqL irqL;
++	struct wlan_network *pwlan = NULL;
++	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	WLAN_BSSID_EX *pdev_network = &padapter->registrypriv.dev_network;
++	struct wlan_network *mlme_cur_network = &(pmlmepriv->cur_network);
++
++	if (status != H2C_SUCCESS)
++		_set_timer(&pmlmepriv->assoc_timer, 1);
++
++	_cancel_timer_ex(&pmlmepriv->assoc_timer);
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++	{
++		_irqL irqL;
++
++		pwlan = _rtw_alloc_network(pmlmepriv);
++		_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++		if (pwlan == NULL) {
++			pwlan = rtw_get_oldest_wlan_network(&pmlmepriv->scanned_queue);
++			if (pwlan == NULL) {
++				_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++				goto createbss_cmd_fail;
++			}
++			pwlan->last_scanned = rtw_get_current_time();
++		} else
++			rtw_list_insert_tail(&(pwlan->list), &pmlmepriv->scanned_queue.queue);
++
++		pdev_network->Length = get_WLAN_BSSID_EX_sz(pdev_network);
++		_rtw_memcpy(&(pwlan->network), pdev_network, pdev_network->Length);
++		/* pwlan->fixed = _TRUE; */
++
++		/* copy pdev_network information to pmlmepriv->cur_network */
++		_rtw_memcpy(&mlme_cur_network->network, pdev_network, (get_WLAN_BSSID_EX_sz(pdev_network)));
++
++#if 0
++		/* reset DSConfig */
++		mlme_cur_network->network.Configuration.DSConfig = (u32)rtw_ch2freq(pdev_network->Configuration.DSConfig);
++#endif
++
++		_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
++		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++		/* we will set WIFI_ASOC_STATE when there is one more sat to join us (rtw_stassoc_event_callback) */
++	}
++
++createbss_cmd_fail:
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++	return;
++}
++
++
++
++void rtw_setstaKey_cmdrsp_callback(_adapter	*padapter ,  struct cmd_obj *pcmd)
++{
++
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct set_stakey_rsp *psetstakey_rsp = (struct set_stakey_rsp *)(pcmd->rsp);
++	struct sta_info	*psta = rtw_get_stainfo(pstapriv, psetstakey_rsp->addr);
++
++
++	if (psta == NULL) {
++		goto exit;
++	}
++
++	/* psta->cmn.aid = psta->cmn.mac_id = psetstakey_rsp->keyid; */ /* CAM_ID(CAM_ENTRY) */
++
++exit:
++
++	rtw_free_cmd_obj(pcmd);
++
++
++}
++
++void rtw_getrttbl_cmd_cmdrsp_callback(_adapter	*padapter,  struct cmd_obj *pcmd)
++{
++
++	rtw_free_cmd_obj(pcmd);
++#ifdef CONFIG_MP_INCLUDED
++	if (padapter->registrypriv.mp_mode == 1)
++		padapter->mppriv.workparam.bcompleted = _TRUE;
++#endif
++
++
++}
++
++u8 set_txq_params_cmd(_adapter *adapter, u32 ac_parm, u8 ac_type)
++{
++	struct cmd_obj *cmdobj;
++	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++	u8 *ac_parm_buf = NULL;
++	u8 sz;
++	u8 res = _SUCCESS;
++
++
++	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (cmdobj == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	sz = sizeof(ac_parm);
++	ac_parm_buf = rtw_zmalloc(sz);
++	if (ac_parm_buf == NULL) {
++		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
++		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm->ec_id = AC_PARM_CMD_WK_CID;
++	pdrvextra_cmd_parm->type = ac_type;
++	pdrvextra_cmd_parm->size = sz;
++	pdrvextra_cmd_parm->pbuf = ac_parm_buf;
++
++	_rtw_memcpy(ac_parm_buf, &ac_parm, sz);
++
++	init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++	res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
++
++exit:
++	return res;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_debug.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_debug.c
+new file mode 100755
+index 000000000..58008fe18
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_debug.c
+@@ -0,0 +1,7601 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_DEBUG_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++#ifdef CONFIG_RTW_DEBUG
++const char *rtw_log_level_str[] = {
++	"_DRV_NONE_ = 0",
++	"_DRV_ALWAYS_ = 1",
++	"_DRV_ERR_ = 2",
++	"_DRV_WARNING_ = 3",
++	"_DRV_INFO_ = 4",
++	"_DRV_DEBUG_ = 5",
++	"_DRV_MAX_ = 6",
++};
++#endif
++
++#ifdef CONFIG_DEBUG_RTL871X
++	u64 GlobalDebugComponents = 0;
++#endif /* CONFIG_DEBUG_RTL871X */
++
++#include <rtw_version.h>
++
++#ifdef CONFIG_TDLS
++	#define TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE	41
++#endif
++
++void dump_drv_version(void *sel)
++{
++	RTW_PRINT_SEL(sel, "%s %s\n", DRV_NAME, DRIVERVERSION);
++	RTW_PRINT_SEL(sel, "build time: %s %s\n", __DATE__, __TIME__);
++}
++
++void dump_drv_cfg(void *sel)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
++	char *kernel_version = utsname()->release;
++
++	RTW_PRINT_SEL(sel, "\nKernel Version: %s\n", kernel_version);
++#endif
++
++	RTW_PRINT_SEL(sel, "Driver Version: %s\n", DRIVERVERSION);
++	RTW_PRINT_SEL(sel, "------------------------------------------------\n");
++#ifdef CONFIG_IOCTL_CFG80211
++	RTW_PRINT_SEL(sel, "CFG80211\n");
++#ifdef RTW_USE_CFG80211_STA_EVENT
++	RTW_PRINT_SEL(sel, "RTW_USE_CFG80211_STA_EVENT\n");
++#endif
++	#ifdef CONFIG_RADIO_WORK
++	RTW_PRINT_SEL(sel, "CONFIG_RADIO_WORK\n");
++	#endif
++#else
++	RTW_PRINT_SEL(sel, "WEXT\n");
++#endif
++
++	RTW_PRINT_SEL(sel, "DBG:%d\n", DBG);
++#ifdef CONFIG_RTW_DEBUG
++	RTW_PRINT_SEL(sel, "CONFIG_RTW_DEBUG\n");
++#endif
++
++#ifdef CONFIG_CONCURRENT_MODE
++	RTW_PRINT_SEL(sel, "CONFIG_CONCURRENT_MODE\n");
++#endif
++
++#ifdef CONFIG_POWER_SAVING
++	RTW_PRINT_SEL(sel, "CONFIG_POWER_SAVING\n");
++	#ifdef CONFIG_IPS
++	RTW_PRINT_SEL(sel, "CONFIG_IPS\n");
++	#endif
++	#ifdef CONFIG_LPS
++		RTW_PRINT_SEL(sel, "CONFIG_LPS\n");
++		#ifdef CONFIG_LPS_LCLK
++		RTW_PRINT_SEL(sel, "CONFIG_LPS_LCLK\n");
++		#ifdef CONFIG_DETECT_CPWM_BY_POLLING
++		RTW_PRINT_SEL(sel, "CONFIG_DETECT_CPWM_BY_POLLING\n");
++		#endif
++		#endif /*CONFIG_LPS_LCLK*/
++		#ifdef CONFIG_LPS_CHK_BY_TP
++		RTW_PRINT_SEL(sel, "CONFIG_LPS_CHK_BY_TP\n");
++		#endif
++		#ifdef CONFIG_LPS_ACK
++		RTW_PRINT_SEL(sel, "CONFIG_LPS_ACK\n");
++		#endif
++	#endif/*CONFIG_LPS*/
++#endif
++
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++	RTW_PRINT_SEL(sel, "LOAD_PHY_PARA_FROM_FILE - REALTEK_CONFIG_PATH=%s\n", REALTEK_CONFIG_PATH);
++	#if defined(CONFIG_MULTIDRV) || defined(REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER)
++	RTW_PRINT_SEL(sel, "LOAD_PHY_PARA_FROM_FILE - REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER\n");
++	#endif
++
++/* configurations about TX power */
++#ifdef CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY
++	RTW_PRINT_SEL(sel, "CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY\n");
++#endif
++#ifdef CONFIG_CALIBRATE_TX_POWER_TO_MAX
++	RTW_PRINT_SEL(sel, "CONFIG_CALIBRATE_TX_POWER_TO_MAX\n");
++#endif
++#endif
++	RTW_PRINT_SEL(sel, "RTW_DEF_MODULE_REGULATORY_CERT=0x%02x\n", RTW_DEF_MODULE_REGULATORY_CERT);
++
++	RTW_PRINT_SEL(sel, "CONFIG_TXPWR_BY_RATE=%d\n", CONFIG_TXPWR_BY_RATE);
++	RTW_PRINT_SEL(sel, "CONFIG_TXPWR_BY_RATE_EN=%d\n", CONFIG_TXPWR_BY_RATE_EN);
++	RTW_PRINT_SEL(sel, "CONFIG_TXPWR_LIMIT=%d\n", CONFIG_TXPWR_LIMIT);
++	RTW_PRINT_SEL(sel, "CONFIG_TXPWR_LIMIT_EN=%d\n", CONFIG_TXPWR_LIMIT_EN);
++
++
++#ifdef CONFIG_DISABLE_ODM
++	RTW_PRINT_SEL(sel, "CONFIG_DISABLE_ODM\n");
++#endif
++
++#ifdef CONFIG_MINIMAL_MEMORY_USAGE
++	RTW_PRINT_SEL(sel, "CONFIG_MINIMAL_MEMORY_USAGE\n");
++#endif
++
++	RTW_PRINT_SEL(sel, "CONFIG_RTW_ADAPTIVITY_EN = %d\n", CONFIG_RTW_ADAPTIVITY_EN);
++#if (CONFIG_RTW_ADAPTIVITY_EN)
++	RTW_PRINT_SEL(sel, "ADAPTIVITY_MODE = %s\n", (CONFIG_RTW_ADAPTIVITY_MODE) ? "carrier_sense" : "normal");
++#endif
++
++#ifdef CONFIG_WOWLAN
++	RTW_PRINT_SEL(sel, "CONFIG_WOWLAN - ");
++
++#ifdef CONFIG_GPIO_WAKEUP
++	RTW_PRINT_SEL(sel, "CONFIG_GPIO_WAKEUP - WAKEUP_GPIO_IDX:%d\n", WAKEUP_GPIO_IDX);
++#endif
++#endif
++
++#ifdef CONFIG_TDLS
++	RTW_PRINT_SEL(sel, "CONFIG_TDLS\n");
++#endif
++
++#ifdef CONFIG_RTW_80211R
++	RTW_PRINT_SEL(sel, "CONFIG_RTW_80211R\n");
++#endif
++
++#ifdef CONFIG_RTW_NETIF_SG
++	RTW_PRINT_SEL(sel, "CONFIG_RTW_NETIF_SG\n");
++#endif
++
++#ifdef CONFIG_RTW_WIFI_HAL
++	RTW_PRINT_SEL(sel, "CONFIG_RTW_WIFI_HAL\n");
++#endif
++
++#ifdef RTW_BUSY_DENY_SCAN
++	RTW_PRINT_SEL(sel, "RTW_BUSY_DENY_SCAN\n");
++	RTW_PRINT_SEL(sel, "BUSY_TRAFFIC_SCAN_DENY_PERIOD = %u ms\n", \
++		      BUSY_TRAFFIC_SCAN_DENY_PERIOD);
++#endif
++
++#ifdef CONFIG_RTW_TPT_MODE
++	RTW_PRINT_SEL(sel, "CONFIG_RTW_TPT_MODE\n");
++#endif 
++
++#ifdef CONFIG_USB_HCI
++#ifdef CONFIG_SUPPORT_USB_INT
++	RTW_PRINT_SEL(sel, "CONFIG_SUPPORT_USB_INT\n");
++#endif
++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
++	RTW_PRINT_SEL(sel, "CONFIG_USB_INTERRUPT_IN_PIPE\n");
++#endif
++#ifdef CONFIG_USB_TX_AGGREGATION
++	RTW_PRINT_SEL(sel, "CONFIG_USB_TX_AGGREGATION\n");
++#endif
++#ifdef CONFIG_USB_RX_AGGREGATION
++	RTW_PRINT_SEL(sel, "CONFIG_USB_RX_AGGREGATION\n");
++#endif
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX
++	RTW_PRINT_SEL(sel, "CONFIG_USE_USB_BUFFER_ALLOC_TX\n");
++#endif
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
++	RTW_PRINT_SEL(sel, "CONFIG_USE_USB_BUFFER_ALLOC_RX\n");
++#endif
++#ifdef CONFIG_PREALLOC_RECV_SKB
++	RTW_PRINT_SEL(sel, "CONFIG_PREALLOC_RECV_SKB\n");
++#endif
++#ifdef CONFIG_FIX_NR_BULKIN_BUFFER
++	RTW_PRINT_SEL(sel, "CONFIG_FIX_NR_BULKIN_BUFFER\n");
++#endif
++#endif /*CONFIG_USB_HCI*/
++
++#ifdef CONFIG_SDIO_HCI
++#ifdef CONFIG_TX_AGGREGATION
++	RTW_PRINT_SEL(sel, "CONFIG_TX_AGGREGATION\n");
++#endif
++#ifdef CONFIG_RX_AGGREGATION
++	RTW_PRINT_SEL(sel, "CONFIG_RX_AGGREGATION\n");
++#endif
++#ifdef RTW_XMIT_THREAD_HIGH_PRIORITY
++	RTW_PRINT_SEL(sel, "RTW_XMIT_THREAD_HIGH_PRIORITY\n");
++#endif
++#ifdef RTW_XMIT_THREAD_HIGH_PRIORITY_AGG
++	RTW_PRINT_SEL(sel, "RTW_XMIT_THREAD_HIGH_PRIORITY_AGG\n");
++#endif
++
++#ifdef DBG_SDIO
++	RTW_PRINT_SEL(sel, "DBG_SDIO = %d\n", DBG_SDIO);
++#endif
++#endif /*CONFIG_SDIO_HCI*/
++
++#ifdef CONFIG_PCI_HCI
++#endif
++
++	RTW_PRINT_SEL(sel, "CONFIG_IFACE_NUMBER = %d\n", CONFIG_IFACE_NUMBER);
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++	RTW_PRINT_SEL(sel, "CONFIG_MI_WITH_MBSSID_CAM\n");
++#endif
++#ifdef CONFIG_SWTIMER_BASED_TXBCN
++	RTW_PRINT_SEL(sel, "CONFIG_SWTIMER_BASED_TXBCN\n");
++#endif
++#ifdef CONFIG_FW_HANDLE_TXBCN
++	RTW_PRINT_SEL(sel, "CONFIG_FW_HANDLE_TXBCN\n");
++	RTW_PRINT_SEL(sel, "CONFIG_LIMITED_AP_NUM = %d\n", CONFIG_LIMITED_AP_NUM);
++#endif
++#ifdef CONFIG_CLIENT_PORT_CFG
++	RTW_PRINT_SEL(sel, "CONFIG_CLIENT_PORT_CFG\n");
++#endif
++#ifdef CONFIG_PCI_TX_POLLING
++	RTW_PRINT_SEL(sel, "CONFIG_PCI_TX_POLLING\n");
++#endif
++	RTW_PRINT_SEL(sel, "CONFIG_RTW_UP_MAPPING_RULE = %s\n", (CONFIG_RTW_UP_MAPPING_RULE == 1) ? "dscp" : "tos");
++
++	RTW_PRINT_SEL(sel, "\n=== XMIT-INFO ===\n");
++	RTW_PRINT_SEL(sel, "NR_XMITFRAME = %d\n", NR_XMITFRAME);
++	RTW_PRINT_SEL(sel, "NR_XMITBUFF = %d\n", NR_XMITBUFF);
++	RTW_PRINT_SEL(sel, "MAX_XMITBUF_SZ = %d\n", MAX_XMITBUF_SZ);
++	RTW_PRINT_SEL(sel, "NR_XMIT_EXTBUFF = %d\n", NR_XMIT_EXTBUFF);
++	RTW_PRINT_SEL(sel, "MAX_XMIT_EXTBUF_SZ = %d\n", MAX_XMIT_EXTBUF_SZ);
++	RTW_PRINT_SEL(sel, "MAX_CMDBUF_SZ = %d\n", MAX_CMDBUF_SZ);
++
++	RTW_PRINT_SEL(sel, "\n=== RECV-INFO ===\n");
++	RTW_PRINT_SEL(sel, "NR_RECVFRAME = %d\n", NR_RECVFRAME);
++	RTW_PRINT_SEL(sel, "NR_RECVBUFF = %d\n", NR_RECVBUFF);
++	RTW_PRINT_SEL(sel, "MAX_RECVBUF_SZ = %d\n", MAX_RECVBUF_SZ);
++
++}
++
++void dump_log_level(void *sel)
++{
++#ifdef CONFIG_RTW_DEBUG
++	int i;
++
++	RTW_PRINT_SEL(sel, "drv_log_level:%d\n", rtw_drv_log_level);
++	for (i = 0; i <= _DRV_MAX_; i++) {
++		if (rtw_log_level_str[i])
++			RTW_PRINT_SEL(sel, "%c %s = %d\n",
++				(rtw_drv_log_level == i) ? '+' : ' ', rtw_log_level_str[i], i);
++	}
++#else
++	RTW_PRINT_SEL(sel, "CONFIG_RTW_DEBUG is disabled\n");
++#endif
++}
++
++#ifdef CONFIG_SDIO_HCI
++void sd_f0_reg_dump(void *sel, _adapter *adapter)
++{
++	int i;
++
++	for (i = 0x0; i <= 0xff; i++) {
++		if (i % 16 == 0)
++			RTW_PRINT_SEL(sel, "0x%02x ", i);
++
++		_RTW_PRINT_SEL(sel, "%02x ", rtw_sd_f0_read8(adapter, i));
++
++		if (i % 16 == 15)
++			_RTW_PRINT_SEL(sel, "\n");
++		else if (i % 8 == 7)
++			_RTW_PRINT_SEL(sel, "\t");
++	}
++}
++
++void sdio_local_reg_dump(void *sel, _adapter *adapter)
++{
++	int i, j = 1;
++
++	for (i = 0x0; i < 0x100; i += 4) {
++		if (j % 4 == 1)
++			RTW_PRINT_SEL(sel, "0x%02x", i);
++		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, (0x1025 << 16) | i));
++		if ((j++) % 4 == 0)
++			_RTW_PRINT_SEL(sel, "\n");
++	}
++}
++#endif /* CONFIG_SDIO_HCI */
++
++void mac_reg_dump(void *sel, _adapter *adapter)
++{
++	int i, j = 1;
++
++	RTW_PRINT_SEL(sel, "======= MAC REG =======\n");
++
++	for (i = 0x0; i < 0x800; i += 4) {
++		if (j % 4 == 1)
++			RTW_PRINT_SEL(sel, "0x%04x", i);
++		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
++		if ((j++) % 4 == 0)
++			_RTW_PRINT_SEL(sel, "\n");
++	}
++
++#ifdef CONFIG_RTL8814A
++	{
++		for (i = 0x1000; i < 0x1650; i += 4) {
++			if (j % 4 == 1)
++				RTW_PRINT_SEL(sel, "0x%04x", i);
++			_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
++			if ((j++) % 4 == 0)
++				_RTW_PRINT_SEL(sel, "\n");
++		}
++	}
++#endif /* CONFIG_RTL8814A */
++
++#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
++	for (i = 0x1000; i < 0x1800; i += 4) {
++		if (j % 4 == 1)
++			RTW_PRINT_SEL(sel, "0x%04x", i);
++		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
++		if ((j++) % 4 == 0)
++			_RTW_PRINT_SEL(sel, "\n");
++	}
++#endif /* CONFIG_RTL8822B  or 8821c*/
++
++#if defined(CONFIG_RTL8192F)
++	for (i = 0x1000; i < 0x1100; i += 4) {
++		if (j % 4 == 1)
++			RTW_PRINT_SEL(sel, "0x%04x", i);
++		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
++		if ((j++) % 4 == 0)
++			_RTW_PRINT_SEL(sel, "\n");
++	}
++	for (i = 0x1300; i < 0x1360; i += 4) {
++		if (j % 4 == 1)
++			RTW_PRINT_SEL(sel, "0x%04x", i);
++		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
++		if ((j++) % 4 == 0)
++			_RTW_PRINT_SEL(sel, "\n");
++	}
++#endif
++
++#if defined(CONFIG_RTL8814B)
++	for (i = 0x2000; i < 0x2800; i += 4) {
++		if (j % 4 == 1)
++			RTW_PRINT_SEL(sel, "0x%04x", i);
++		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
++		if ((j++) % 4 == 0)
++			_RTW_PRINT_SEL(sel, "\n");
++	}
++
++	for (i = 0x3000; i < 0x3800; i += 4) {
++		if (j % 4 == 1)
++			RTW_PRINT_SEL(sel, "0x%04x", i);
++		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
++		if ((j++) % 4 == 0)
++			_RTW_PRINT_SEL(sel, "\n");
++	}
++#endif
++
++}
++
++void bb_reg_dump(void *sel, _adapter *adapter)
++{
++	int i, j = 1;
++
++	RTW_PRINT_SEL(sel, "======= BB REG =======\n");
++	for (i = 0x800; i < 0x1000; i += 4) {
++		if (j % 4 == 1)
++			RTW_PRINT_SEL(sel, "0x%04x", i);
++		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
++		if ((j++) % 4 == 0)
++			_RTW_PRINT_SEL(sel, "\n");
++	}
++
++#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
++	for (i = 0x1800; i < 0x2000; i += 4) {
++		if (j % 4 == 1)
++			RTW_PRINT_SEL(sel, "0x%04x", i);
++		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
++		if ((j++) % 4 == 0)
++			_RTW_PRINT_SEL(sel, "\n");
++	}
++#endif /* CONFIG_RTL8822B */
++
++#if defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
++	for (i = 0x2c00; i < 0x2c60; i += 4) {
++		if (j % 4 == 1)
++			RTW_PRINT_SEL(sel, "0x%04x", i);
++		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
++		if ((j++) % 4 == 0)
++			_RTW_PRINT_SEL(sel, "\n");
++	}
++
++	for (i = 0x2d00; i < 0x2df0; i += 4) {
++		if (j % 4 == 1)
++			RTW_PRINT_SEL(sel, "0x%04x", i);
++		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
++		if ((j++) % 4 == 0)
++			_RTW_PRINT_SEL(sel, "\n");
++	}	
++
++	for (i = 0x4000; i < 0x4060; i += 4) {
++		if (j % 4 == 1)
++			RTW_PRINT_SEL(sel, "0x%04x", i);
++		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
++		if ((j++) % 4 == 0)
++			_RTW_PRINT_SEL(sel, "\n");
++	}	
++
++	for (i = 0x4100; i < 0x4200; i += 4) {
++		if (j % 4 == 1)
++			RTW_PRINT_SEL(sel, "0x%04x", i);
++		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
++		if ((j++) % 4 == 0)
++			_RTW_PRINT_SEL(sel, "\n");
++	}	
++
++#endif /* CONFIG_RTL8822C || CONFIG_RTL8814B */
++
++#if defined(CONFIG_RTL8814B)
++	for (i = 0x5200; i < 0x5400; i += 4) {
++		if (j % 4 == 1)
++			RTW_PRINT_SEL(sel, "0x%04x", i);
++		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
++		if ((j++) % 4 == 0)
++			_RTW_PRINT_SEL(sel, "\n");
++	}
++#endif /* CONFIG_RTL8814B */
++}
++
++void bb_reg_dump_ex(void *sel, _adapter *adapter)
++{
++	int i;
++
++	RTW_PRINT_SEL(sel, "======= BB REG =======\n");
++	for (i = 0x800; i < 0x1000; i += 4) {
++		RTW_PRINT_SEL(sel, "0x%04x", i);
++		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++
++#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
++	for (i = 0x1800; i < 0x2000; i += 4) {
++		RTW_PRINT_SEL(sel, "0x%04x", i);
++		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++#endif /* CONFIG_RTL8822B */
++}
++
++void rf_reg_dump(void *sel, _adapter *adapter)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	int i, j = 1, path;
++	u32 value;
++	u8 path_nums = hal_spec->rf_reg_path_num;
++
++	RTW_PRINT_SEL(sel, "======= RF REG =======\n");
++
++	for (path = 0; path < path_nums; path++) {
++		RTW_PRINT_SEL(sel, "RF_Path(%x)\n", path);
++		for (i = 0; i < 0x100; i++) {
++			value = rtw_hal_read_rfreg(adapter, path, i, 0xffffffff);
++			if (j % 4 == 1)
++				RTW_PRINT_SEL(sel, "0x%02x ", i);
++			_RTW_PRINT_SEL(sel, " 0x%08x ", value);
++			if ((j++) % 4 == 0)
++				_RTW_PRINT_SEL(sel, "\n");
++		}
++	}
++}
++
++void rtw_sink_rtp_seq_dbg(_adapter *adapter, u8 *ehdr_pos)
++{
++	struct recv_priv *precvpriv = &(adapter->recvpriv);
++	if (precvpriv->sink_udpport > 0) {
++		if (*((u16 *)(ehdr_pos + 0x24)) == cpu_to_be16(precvpriv->sink_udpport)) {
++			precvpriv->pre_rtp_rxseq = precvpriv->cur_rtp_rxseq;
++			precvpriv->cur_rtp_rxseq = be16_to_cpu(*((u16 *)(ehdr_pos + 0x2C)));
++			if (precvpriv->pre_rtp_rxseq + 1 != precvpriv->cur_rtp_rxseq) {
++				if(precvpriv->pre_rtp_rxseq == 65535 ) {
++					if( precvpriv->cur_rtp_rxseq != 0) {
++						RTW_INFO("%s : RTP Seq num from %d to %d\n", __FUNCTION__, precvpriv->pre_rtp_rxseq, precvpriv->cur_rtp_rxseq);
++					}
++				} else {
++					RTW_INFO("%s : RTP Seq num from %d to %d\n", __FUNCTION__, precvpriv->pre_rtp_rxseq, precvpriv->cur_rtp_rxseq);
++				}
++			}	
++		}
++	}
++}
++
++void sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta)
++{
++	struct recv_reorder_ctrl *reorder_ctl;
++	int i;
++
++	for (i = 0; i < 16; i++) {
++		reorder_ctl = &sta->recvreorder_ctrl[i];
++		if (reorder_ctl->ampdu_size != RX_AMPDU_SIZE_INVALID || reorder_ctl->indicate_seq != 0xFFFF) {
++			RTW_PRINT_SEL(sel, "tid=%d, enable=%d, ampdu_size=%u, indicate_seq=%u\n"
++				, i, reorder_ctl->enable, reorder_ctl->ampdu_size, reorder_ctl->indicate_seq
++				     );
++		}
++	}
++}
++
++void dump_tx_rate_bmp(void *sel, struct dvobj_priv *dvobj)
++{
++	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
++	struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
++	u8 bw;
++
++	RTW_PRINT_SEL(sel, "%-6s", "bw");
++	if (hal_chk_proto_cap(adapter, PROTO_CAP_11AC))
++		_RTW_PRINT_SEL(sel, " %-15s", "vht");
++
++	_RTW_PRINT_SEL(sel, " %-11s %-4s %-3s\n", "ht", "ofdm", "cck");
++
++	for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) {
++		if (!hal_is_bw_support(adapter, bw))
++			continue;
++
++		RTW_PRINT_SEL(sel, "%6s", ch_width_str(bw));
++		if (hal_chk_proto_cap(adapter, PROTO_CAP_11AC)) {
++			_RTW_PRINT_SEL(sel, " %03x %03x %03x %03x"
++				, RATE_BMP_GET_VHT_4SS(rfctl->rate_bmp_vht_by_bw[bw])
++				, RATE_BMP_GET_VHT_3SS(rfctl->rate_bmp_vht_by_bw[bw])
++				, RATE_BMP_GET_VHT_2SS(rfctl->rate_bmp_vht_by_bw[bw])
++				, RATE_BMP_GET_VHT_1SS(rfctl->rate_bmp_vht_by_bw[bw])
++			);
++		}
++
++		_RTW_PRINT_SEL(sel, " %02x %02x %02x %02x"
++			, bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_4SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0
++			, bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_3SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0
++			, bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_2SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0
++			, bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_1SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0
++		);
++
++		_RTW_PRINT_SEL(sel, "  %03x   %01x\n"
++			, bw <= CHANNEL_WIDTH_20 ? RATE_BMP_GET_OFDM(rfctl->rate_bmp_cck_ofdm) : 0
++			, bw <= CHANNEL_WIDTH_20 ? RATE_BMP_GET_CCK(rfctl->rate_bmp_cck_ofdm) : 0
++		);
++	}
++}
++
++void dump_adapters_status(void *sel, struct dvobj_priv *dvobj)
++{
++	struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
++	int i;
++	_adapter *iface;
++	u8 u_ch, u_bw, u_offset;
++#if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG)
++	char str_val[64] = {'\0'};
++#endif
++	dump_mi_status(sel, dvobj);
++
++#if defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)
++	RTW_PRINT_SEL(sel, "[AP] LIMITED_AP_NUM:%d\n", CONFIG_LIMITED_AP_NUM);
++	RTW_PRINT_SEL(sel, "[AP] vap_map:0x%02x\n", dvobj->vap_map);
++#endif
++#ifdef CONFIG_HW_P0_TSF_SYNC
++	RTW_PRINT_SEL(sel, "[AP] p0 tsf sync port = %d\n", dvobj->p0_tsf.sync_port);
++	RTW_PRINT_SEL(sel, "[AP] p0 tsf timer offset = %d\n", dvobj->p0_tsf.offset);
++#endif
++#ifdef CONFIG_CLIENT_PORT_CFG
++	RTW_PRINT_SEL(sel, "[CLT] clt_num = %d\n", dvobj->clt_port.num);
++	RTW_PRINT_SEL(sel, "[CLT] clt_map = 0x%02x\n", dvobj->clt_port.bmp);
++#endif
++#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++	RTW_PRINT_SEL(sel, "[MI] default port id:%d\n\n", dvobj->dft.port_id);
++#endif /* CONFIG_FW_MULTI_PORT_SUPPORT */
++
++	RTW_PRINT_SEL(sel, "dev status:%s%s\n\n"
++		, dev_is_surprise_removed(dvobj) ? " SR" : ""
++		, dev_is_drv_stopped(dvobj) ? " DS" : ""
++	);
++
++#ifdef CONFIG_P2P
++#define P2P_INFO_TITLE_FMT	" %-3s %-4s"
++#define P2P_INFO_TITLE_ARG	, "lch", "p2ps"
++#ifdef CONFIG_IOCTL_CFG80211
++#define P2P_INFO_VALUE_FMT	" %3u %c%3u"
++#define P2P_INFO_VALUE_ARG	, iface->wdinfo.listen_channel, iface->wdev_data.p2p_enabled ? 'e' : ' ', rtw_p2p_state(&iface->wdinfo)
++#else
++#define P2P_INFO_VALUE_FMT	" %3u %4u"
++#define P2P_INFO_VALUE_ARG	, iface->wdinfo.listen_channel, rtw_p2p_state(&iface->wdinfo)
++#endif
++#define P2P_INFO_DASH		"---------"
++#else
++#define P2P_INFO_TITLE_FMT	""
++#define P2P_INFO_TITLE_ARG
++#define P2P_INFO_VALUE_FMT	""
++#define P2P_INFO_VALUE_ARG
++#define P2P_INFO_DASH
++#endif
++
++#ifdef DBG_TSF_UPDATE
++#define TSF_PAUSE_TIME_TITLE_FMT " %-5s"
++#define TSF_PAUSE_TIME_TITLE_ARG , "tsfup"
++#define TSF_PAUSE_TIME_VALUE_FMT " %5d"
++#define TSF_PAUSE_TIME_VALUE_ARG , ((iface->mlmeextpriv.tsf_update_required && iface->mlmeextpriv.tsf_update_pause_stime) ? (rtw_get_passing_time_ms(iface->mlmeextpriv.tsf_update_pause_stime) > 99999 ? 99999 : rtw_get_passing_time_ms(iface->mlmeextpriv.tsf_update_pause_stime)) : 0)
++#else
++#define TSF_PAUSE_TIME_TITLE_FMT ""
++#define TSF_PAUSE_TIME_TITLE_ARG
++#define TSF_PAUSE_TIME_VALUE_FMT ""
++#define TSF_PAUSE_TIME_VALUE_ARG
++#endif
++
++#if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG)
++#define INFO_FMT	" %-4s"
++#define INFO_ARG	, "info"
++#define INFO_CNT_FMT	" %-20s"
++#define INFO_CNT_ARG	, str_val
++#else
++#define INFO_FMT	""
++#define INFO_ARG
++#define INFO_CNT_FMT	""
++#define INFO_CNT_ARG
++#endif
++
++	RTW_PRINT_SEL(sel, "%-2s %-15s %c %-3s %-3s %-3s %-17s %-4s %-7s %-5s"
++		P2P_INFO_TITLE_FMT
++		TSF_PAUSE_TIME_TITLE_FMT
++		" %s"INFO_FMT"\n"
++		, "id", "ifname", ' ', "bup", "nup", "ncd", "macaddr", "port", "ch", "class"
++		P2P_INFO_TITLE_ARG
++		TSF_PAUSE_TIME_TITLE_ARG
++		, "status"INFO_ARG);
++
++	RTW_PRINT_SEL(sel, "---------------------------------------------------------------"
++		P2P_INFO_DASH
++		"-------\n");
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (iface) {
++			#if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG)
++			_rtw_memset(&str_val, '\0', sizeof(str_val));
++			#endif
++			#if defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)
++			if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) {
++				u8 len;
++				char *p = str_val;
++				char tmp_str[10] = {'\0'};
++
++				len = snprintf(tmp_str, sizeof(tmp_str), "%s", "ap_id:");
++				strncpy(p, tmp_str, len);
++				p += len;
++				_rtw_memset(&tmp_str, '\0', sizeof(tmp_str));
++				#ifdef DBG_HW_PORT
++				len = snprintf(tmp_str, sizeof(tmp_str), "%d (%d,%d)", iface->vap_id, iface->hw_port, iface->client_port);
++				#else
++				len = snprintf(tmp_str, sizeof(tmp_str), "%d", iface->vap_id);
++				#endif
++				strncpy(p, tmp_str, len);
++			}
++			#endif
++			#ifdef CONFIG_CLIENT_PORT_CFG
++			if (MLME_IS_STA(iface)) {
++				u8 len;
++				char *p = str_val;
++				char tmp_str[10] = {'\0'};
++
++				len = snprintf(tmp_str, sizeof(tmp_str), "%s", "c_pid:");
++				strncpy(p, tmp_str, len);
++				p += len;
++				_rtw_memset(&tmp_str, '\0', sizeof(tmp_str));
++				#ifdef DBG_HW_PORT
++				len = snprintf(tmp_str, sizeof(tmp_str), "%d (%d,%d)", iface->client_port, iface->hw_port, iface->client_port);
++				#else
++				len = snprintf(tmp_str, sizeof(tmp_str), "%d", iface->client_port);
++				#endif
++				strncpy(p, tmp_str, len);
++			}
++			#endif
++
++			RTW_PRINT_SEL(sel, "%2d %-15s %c %3u %3u %3u "MAC_FMT" %4hhu %3u,%u,%u %5u"
++				P2P_INFO_VALUE_FMT
++				TSF_PAUSE_TIME_VALUE_FMT
++				" "MLME_STATE_FMT" " INFO_CNT_FMT"\n"
++				, i, iface->registered ? ADPT_ARG(iface) : NULL
++				, iface->registered ? 'R' : ' '
++				, iface->bup
++				, iface->netif_up
++				, iface->net_closed
++				, MAC_ARG(adapter_mac_addr(iface))
++				, rtw_hal_get_port(iface)
++				, iface->mlmeextpriv.cur_channel
++				, iface->mlmeextpriv.cur_bwmode
++				, iface->mlmeextpriv.cur_ch_offset
++				, rtw_get_op_class_by_chbw(iface->mlmeextpriv.cur_channel
++					, iface->mlmeextpriv.cur_bwmode
++					, iface->mlmeextpriv.cur_ch_offset)
++				P2P_INFO_VALUE_ARG
++				TSF_PAUSE_TIME_VALUE_ARG
++				, MLME_STATE_ARG(iface)
++				INFO_CNT_ARG
++			);
++		}
++	}
++
++	RTW_PRINT_SEL(sel, "---------------------------------------------------------------"
++		P2P_INFO_DASH
++		"-------\n");
++
++	if (rtw_mi_get_ch_setting_union(dvobj_get_primary_adapter(dvobj), &u_ch, &u_bw, &u_offset))
++		RTW_PRINT_SEL(sel, "%55s %3u,%u,%u\n"
++			, "union:"
++			, u_ch, u_bw, u_offset);
++
++	RTW_PRINT_SEL(sel, "%55s %3u,%u,%u offch_state:%d\n"
++		, "oper:"
++		, dvobj->oper_channel
++		, dvobj->oper_bwmode
++		, dvobj->oper_ch_offset
++		, rfctl->offch_state
++	);
++
++#ifdef CONFIG_DFS_MASTER
++	if (rfctl->radar_detect_ch != 0) {
++		RTW_PRINT_SEL(sel, "%55s %3u,%u,%u"
++			, "radar_detect:"
++			, rfctl->radar_detect_ch
++			, rfctl->radar_detect_bw
++			, rfctl->radar_detect_offset
++		);
++
++		if (rfctl->radar_detect_by_others)
++			_RTW_PRINT_SEL(sel, ", by AP of STA link");
++		else {
++			u32 non_ocp_ms;
++			u32 cac_ms;
++			u8 dfs_domain = rtw_rfctl_get_dfs_domain(rfctl);
++
++			_RTW_PRINT_SEL(sel, ", domain:%u", dfs_domain);
++
++			rtw_get_ch_waiting_ms(rfctl
++				, rfctl->radar_detect_ch
++				, rfctl->radar_detect_bw
++				, rfctl->radar_detect_offset
++				, &non_ocp_ms
++				, &cac_ms
++			);
++
++			if (non_ocp_ms)
++				_RTW_PRINT_SEL(sel, ", non_ocp:%d", non_ocp_ms);
++			if (cac_ms)
++				_RTW_PRINT_SEL(sel, ", cac:%d", cac_ms);
++		}
++
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++#endif /* CONFIG_DFS_MASTER */
++}
++
++#define SEC_CAM_ENT_ID_TITLE_FMT "%-2s"
++#define SEC_CAM_ENT_ID_TITLE_ARG "id"
++#define SEC_CAM_ENT_ID_VALUE_FMT "%2u"
++#define SEC_CAM_ENT_ID_VALUE_ARG(id) (id)
++
++#define SEC_CAM_ENT_TITLE_FMT "%-6s %-17s %-32s %-3s %-8s %-2s %-2s %-5s"
++#define SEC_CAM_ENT_TITLE_ARG "ctrl", "addr", "key", "kid", "type", "MK", "GK", "valid"
++#define SEC_CAM_ENT_VALUE_FMT "0x%04x "MAC_FMT" "KEY_FMT" %3u %-8s %2u %2u %5u"
++#define SEC_CAM_ENT_VALUE_ARG(ent) \
++	(ent)->ctrl \
++	, MAC_ARG((ent)->mac) \
++	, KEY_ARG((ent)->key) \
++	, ((ent)->ctrl) & 0x03 \
++	, (((ent)->ctrl) & 0x200) ? \
++	security_type_str((((ent)->ctrl) >> 2 & 0x7) | _SEC_TYPE_256_) : \
++	security_type_str(((ent)->ctrl) >> 2 & 0x7) \
++	, (((ent)->ctrl) >> 5) & 0x01 \
++	, (((ent)->ctrl) >> 6) & 0x01 \
++	, (((ent)->ctrl) >> 15) & 0x01
++
++void dump_sec_cam_ent(void *sel, struct sec_cam_ent *ent, int id)
++{
++	if (id >= 0) {
++		RTW_PRINT_SEL(sel, SEC_CAM_ENT_ID_VALUE_FMT " " SEC_CAM_ENT_VALUE_FMT"\n"
++			, SEC_CAM_ENT_ID_VALUE_ARG(id), SEC_CAM_ENT_VALUE_ARG(ent));
++	} else
++		RTW_PRINT_SEL(sel, SEC_CAM_ENT_VALUE_FMT"\n", SEC_CAM_ENT_VALUE_ARG(ent));
++}
++
++void dump_sec_cam_ent_title(void *sel, u8 has_id)
++{
++	if (has_id) {
++		RTW_PRINT_SEL(sel, SEC_CAM_ENT_ID_TITLE_FMT " " SEC_CAM_ENT_TITLE_FMT"\n"
++			, SEC_CAM_ENT_ID_TITLE_ARG, SEC_CAM_ENT_TITLE_ARG);
++	} else
++		RTW_PRINT_SEL(sel, SEC_CAM_ENT_TITLE_FMT"\n", SEC_CAM_ENT_TITLE_ARG);
++}
++
++void dump_sec_cam(void *sel, _adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	struct sec_cam_ent ent;
++	int i;
++
++	RTW_PRINT_SEL(sel, "HW sec cam:\n");
++	dump_sec_cam_ent_title(sel, 1);
++	for (i = 0; i < cam_ctl->num; i++) {
++		rtw_sec_read_cam_ent(adapter, i, (u8 *)(&ent.ctrl), ent.mac, ent.key);
++		dump_sec_cam_ent(sel , &ent, i);
++	}
++}
++
++void dump_sec_cam_cache(void *sel, _adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	int i;
++
++	RTW_PRINT_SEL(sel, "SW sec cam cache:\n");
++	dump_sec_cam_ent_title(sel, 1);
++	for (i = 0; i < cam_ctl->num; i++) {
++		if (dvobj->cam_cache[i].ctrl != 0)
++			dump_sec_cam_ent(sel, &dvobj->cam_cache[i], i);
++	}
++
++}
++
++static u8 fwdl_test_chksum_fail = 0;
++static u8 fwdl_test_wintint_rdy_fail = 0;
++
++bool rtw_fwdl_test_trigger_chksum_fail(void)
++{
++	if (fwdl_test_chksum_fail) {
++		RTW_PRINT("fwdl test case: trigger chksum_fail\n");
++		fwdl_test_chksum_fail--;
++		return _TRUE;
++	}
++	return _FALSE;
++}
++
++bool rtw_fwdl_test_trigger_wintint_rdy_fail(void)
++{
++	if (fwdl_test_wintint_rdy_fail) {
++		RTW_PRINT("fwdl test case: trigger wintint_rdy_fail\n");
++		fwdl_test_wintint_rdy_fail--;
++		return _TRUE;
++	}
++	return _FALSE;
++}
++
++static u8 del_rx_ampdu_test_no_tx_fail = 0;
++
++bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void)
++{
++	if (del_rx_ampdu_test_no_tx_fail) {
++		RTW_PRINT("del_rx_ampdu test case: trigger no_tx_fail\n");
++		del_rx_ampdu_test_no_tx_fail--;
++		return _TRUE;
++	}
++	return _FALSE;
++}
++
++static u32 g_wait_hiq_empty_ms = 0;
++
++u32 rtw_get_wait_hiq_empty_ms(void)
++{
++	return g_wait_hiq_empty_ms;
++}
++
++static systime sta_linking_test_start_time = 0;
++static u32 sta_linking_test_wait_ms = 0;
++static u8 sta_linking_test_force_fail = 0;
++
++void rtw_sta_linking_test_set_start(void)
++{
++	sta_linking_test_start_time = rtw_get_current_time();
++}
++
++bool rtw_sta_linking_test_wait_done(void)
++{
++	return rtw_get_passing_time_ms(sta_linking_test_start_time) >= sta_linking_test_wait_ms;
++}
++
++bool rtw_sta_linking_test_force_fail(void)
++{
++	return sta_linking_test_force_fail;
++}
++
++#ifdef CONFIG_AP_MODE
++static u16 ap_linking_test_force_auth_fail = 0;
++static u16 ap_linking_test_force_asoc_fail = 0;
++
++u16 rtw_ap_linking_test_force_auth_fail(void)
++{
++	return ap_linking_test_force_auth_fail;
++}
++
++u16 rtw_ap_linking_test_force_asoc_fail(void)
++{
++	return ap_linking_test_force_asoc_fail;
++}
++#endif
++
++int proc_get_defs_param(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++
++	RTW_PRINT_SEL(m, "%s %15s\n", "lmt_sta", "lmt_time");
++	RTW_PRINT_SEL(m, "%-15u %-15u\n"
++		, mlme->defs_lmt_sta
++		, mlme->defs_lmt_time
++	);
++
++	return 0;
++}
++
++ssize_t proc_set_defs_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++
++	char tmp[32];
++	u32 defs_lmt_sta;
++	u32 defs_lmt_time;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%u %u", &defs_lmt_sta, &defs_lmt_time);
++
++		if (num >= 1)
++			mlme->defs_lmt_sta = defs_lmt_sta;
++		if (num >= 2)
++			mlme->defs_lmt_time = defs_lmt_time;
++	}
++
++	return count;
++
++}
++
++#ifdef CONFIG_PROC_DEBUG
++ssize_t proc_set_write_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u32 addr, val, len;
++
++	if (count < 3) {
++		RTW_INFO("argument size is less than 3\n");
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%x %x %x", &addr, &val, &len);
++
++		if (num !=  3) {
++			RTW_INFO("invalid write_reg parameter!\n");
++			return count;
++		}
++
++		switch (len) {
++		case 1:
++			rtw_write8(padapter, addr, (u8)val);
++			break;
++		case 2:
++			rtw_write16(padapter, addr, (u16)val);
++			break;
++		case 4:
++			rtw_write32(padapter, addr, val);
++			break;
++		default:
++			RTW_INFO("error write length=%d", len);
++			break;
++		}
++
++	}
++
++	return count;
++
++}
++
++static u32 proc_get_read_addr = 0xeeeeeeee;
++static u32 proc_get_read_len = 0x4;
++
++int proc_get_read_reg(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (proc_get_read_addr == 0xeeeeeeee) {
++		RTW_PRINT_SEL(m, "address not initialized\n");
++		return 0;
++	}
++
++	switch (proc_get_read_len) {
++	case 1:
++		RTW_PRINT_SEL(m, "rtw_read8(0x%x)=0x%x\n", proc_get_read_addr, rtw_read8(padapter, proc_get_read_addr));
++		break;
++	case 2:
++		RTW_PRINT_SEL(m, "rtw_read16(0x%x)=0x%x\n", proc_get_read_addr, rtw_read16(padapter, proc_get_read_addr));
++		break;
++	case 4:
++		RTW_PRINT_SEL(m, "rtw_read32(0x%x)=0x%x\n", proc_get_read_addr, rtw_read32(padapter, proc_get_read_addr));
++		break;
++	default:
++		RTW_PRINT_SEL(m, "error read length=%d\n", proc_get_read_len);
++		break;
++	}
++
++	return 0;
++}
++
++ssize_t proc_set_read_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	char tmp[16];
++	u32 addr, len;
++
++	if (count < 2) {
++		RTW_INFO("argument size is less than 2\n");
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%x %x", &addr, &len);
++
++		if (num !=  2) {
++			RTW_INFO("invalid read_reg parameter!\n");
++			return count;
++		}
++
++		proc_get_read_addr = addr;
++
++		proc_get_read_len = len;
++	}
++
++	return count;
++
++}
++
++int proc_get_rx_stat(struct seq_file *m, void *v)
++{
++	_irqL	 irqL;
++	_list	*plist, *phead;
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct sta_info *psta = NULL;
++	struct stainfo_stats	*pstats = NULL;
++	struct sta_priv		*pstapriv = &(adapter->stapriv);
++	u32 i, j;
++	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
++
++	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++	for (i = 0; i < NUM_STA; i++) {
++		phead = &(pstapriv->sta_hash[i]);
++		plist = get_next(phead);
++		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++			plist = get_next(plist);
++			pstats = &psta->sta_stats;
++
++			if (pstats == NULL)
++				continue;
++			if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) !=  _TRUE)
++				&& (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE)
++				&& (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) {
++				RTW_PRINT_SEL(m, "MAC :\t\t"MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
++				RTW_PRINT_SEL(m, "data_rx_cnt :\t%llu\n", sta_rx_data_uc_pkts(psta) - pstats->last_rx_data_uc_pkts);
++				pstats->last_rx_data_uc_pkts = sta_rx_data_uc_pkts(psta);
++				RTW_PRINT_SEL(m, "duplicate_cnt :\t%u\n", pstats->duplicate_cnt);
++				pstats->duplicate_cnt = 0;
++				RTW_PRINT_SEL(m, "rx_per_rate_cnt :\n");
++
++				for (j = 0; j < 0x60; j++) {
++					RTW_PRINT_SEL(m, "%08u  ", pstats->rxratecnt[j]);
++					pstats->rxratecnt[j] = 0;
++					if ((j%8) == 7)
++						RTW_PRINT_SEL(m, "\n");
++				}
++				RTW_PRINT_SEL(m, "\n");
++			}
++		}
++	}
++	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++	return 0;
++}
++
++int proc_get_tx_stat(struct seq_file *m, void *v)
++{
++	_irqL	irqL;
++	_list	*plist, *phead;
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct sta_info *psta = NULL;
++	u8 sta_mac[NUM_STA][ETH_ALEN] = {{0}};
++	uint mac_id[NUM_STA];
++	struct stainfo_stats	*pstats = NULL;
++	struct sta_priv	*pstapriv = &(adapter->stapriv);
++	struct sta_priv	*pstapriv_primary = &(GET_PRIMARY_ADAPTER(adapter))->stapriv;
++	u32 i, macid_rec_idx = 0;
++	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
++	struct submit_ctx gotc2h;
++
++	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++	for (i = 0; i < NUM_STA; i++) {
++		phead = &(pstapriv->sta_hash[i]);
++		plist = get_next(phead);
++		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++			plist = get_next(plist);
++			if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) !=  _TRUE)
++				&& (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE)
++				&& (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) {
++				_rtw_memcpy(&sta_mac[macid_rec_idx][0], psta->cmn.mac_addr, ETH_ALEN);
++				mac_id[macid_rec_idx] = psta->cmn.mac_id;
++				macid_rec_idx++;
++			}
++		}
++	}
++	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++	for (i = 0; i < macid_rec_idx; i++) {
++		_rtw_memcpy(pstapriv_primary->c2h_sta_mac, &sta_mac[i][0], ETH_ALEN);
++		pstapriv_primary->c2h_adapter_id = adapter->iface_id;
++		rtw_sctx_init(&gotc2h, 60);
++		pstapriv_primary->gotc2h = &gotc2h;
++		rtw_hal_reqtxrpt(adapter, mac_id[i]);
++		if (rtw_sctx_wait(&gotc2h, __func__)) {
++			psta = rtw_get_stainfo(pstapriv, &sta_mac[i][0]);
++			if(psta) {
++				pstats = &psta->sta_stats;
++#ifndef ROKU_PRIVATE
++				RTW_PRINT_SEL(m, "data_sent_cnt :\t%u\n", pstats->tx_ok_cnt + pstats->tx_fail_cnt);
++				RTW_PRINT_SEL(m, "success_cnt :\t%u\n", pstats->tx_ok_cnt);
++				RTW_PRINT_SEL(m, "failure_cnt :\t%u\n", pstats->tx_fail_cnt);
++				RTW_PRINT_SEL(m, "retry_cnt :\t%u\n\n", pstats->tx_retry_cnt);
++#else
++				RTW_PRINT_SEL(m, "MAC: " MAC_FMT " sent: %u fail: %u retry: %u\n",
++				MAC_ARG(&sta_mac[i][0]), pstats->tx_ok_cnt, pstats->tx_fail_cnt, pstats->tx_retry_cnt);
++#endif /* ROKU_PRIVATE */
++
++			} else
++				RTW_PRINT_SEL(m, "STA is gone\n");
++		} else {
++			//to avoid c2h modify counters
++			pstapriv_primary->gotc2h = NULL;
++			_rtw_memset(pstapriv_primary->c2h_sta_mac, 0, ETH_ALEN);
++			pstapriv_primary->c2h_adapter_id = CONFIG_IFACE_NUMBER;
++			RTW_PRINT_SEL(m, "Warming : Query timeout, operation abort!!\n");
++			break;
++		}
++		pstapriv_primary->gotc2h = NULL;
++		_rtw_memset(pstapriv_primary->c2h_sta_mac, 0, ETH_ALEN);
++		pstapriv_primary->c2h_adapter_id = CONFIG_IFACE_NUMBER;
++	}
++	return 0;
++}
++
++int proc_get_fwstate(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++	RTW_PRINT_SEL(m, "fwstate=0x%x\n", get_fwstate(pmlmepriv));
++
++	return 0;
++}
++
++int proc_get_sec_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct security_priv *sec = &padapter->securitypriv;
++
++	RTW_PRINT_SEL(m, "auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n",
++		sec->dot11AuthAlgrthm, sec->dot11PrivacyAlgrthm,
++		sec->ndisauthtype, sec->ndisencryptstatus);
++
++	RTW_PRINT_SEL(m, "hw_decrypted=%d\n", sec->hw_decrypted);
++
++#ifdef DBG_SW_SEC_CNT
++	RTW_PRINT_SEL(m, "wep_sw_enc_cnt=%llu, %llu, %llu\n"
++		, sec->wep_sw_enc_cnt_bc , sec->wep_sw_enc_cnt_mc, sec->wep_sw_enc_cnt_uc);
++	RTW_PRINT_SEL(m, "wep_sw_dec_cnt=%llu, %llu, %llu\n"
++		, sec->wep_sw_dec_cnt_bc , sec->wep_sw_dec_cnt_mc, sec->wep_sw_dec_cnt_uc);
++
++	RTW_PRINT_SEL(m, "tkip_sw_enc_cnt=%llu, %llu, %llu\n"
++		, sec->tkip_sw_enc_cnt_bc , sec->tkip_sw_enc_cnt_mc, sec->tkip_sw_enc_cnt_uc);
++	RTW_PRINT_SEL(m, "tkip_sw_dec_cnt=%llu, %llu, %llu\n"
++		, sec->tkip_sw_dec_cnt_bc , sec->tkip_sw_dec_cnt_mc, sec->tkip_sw_dec_cnt_uc);
++
++	RTW_PRINT_SEL(m, "aes_sw_enc_cnt=%llu, %llu, %llu\n"
++		, sec->aes_sw_enc_cnt_bc , sec->aes_sw_enc_cnt_mc, sec->aes_sw_enc_cnt_uc);
++	RTW_PRINT_SEL(m, "aes_sw_dec_cnt=%llu, %llu, %llu\n"
++		, sec->aes_sw_dec_cnt_bc , sec->aes_sw_dec_cnt_mc, sec->aes_sw_dec_cnt_uc);
++
++	RTW_PRINT_SEL(m, "gcmp_sw_enc_cnt=%llu, %llu, %llu\n"
++		, sec->gcmp_sw_enc_cnt_bc , sec->gcmp_sw_enc_cnt_mc, sec->gcmp_sw_enc_cnt_uc);
++	RTW_PRINT_SEL(m, "gcmp_sw_dec_cnt=%llu, %llu, %llu\n"
++		, sec->gcmp_sw_dec_cnt_bc , sec->gcmp_sw_dec_cnt_mc, sec->gcmp_sw_dec_cnt_uc);
++#endif /* DBG_SW_SEC_CNT */
++
++	return 0;
++}
++
++int proc_get_mlmext_state(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	RTW_PRINT_SEL(m, "pmlmeinfo->state=0x%x\n", pmlmeinfo->state);
++
++	return 0;
++}
++
++#ifdef CONFIG_LAYER2_ROAMING
++int proc_get_roam_flags(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_PRINT_SEL(m, "0x%02x\n", rtw_roam_flags(adapter));
++
++	return 0;
++}
++
++ssize_t proc_set_roam_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	char tmp[32];
++	u8 flags;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhx", &flags);
++
++		if (num == 1)
++			rtw_assign_roam_flags(adapter, flags);
++	}
++
++	return count;
++
++}
++
++int proc_get_roam_param(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++
++	RTW_PRINT_SEL(m, "%12s %15s %26s %16s\n", "rssi_diff_th", "scanr_exp_ms", "scan_interval(unit:2 sec)", "rssi_threshold");
++	RTW_PRINT_SEL(m, "%-15u %-13u %-27u %-11u\n"
++		, mlme->roam_rssi_diff_th
++		, mlme->roam_scanr_exp_ms
++		, mlme->roam_scan_int
++		, mlme->roam_rssi_threshold
++	);
++
++	return 0;
++}
++
++ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++
++	char tmp[32];
++	u8 rssi_diff_th;
++	u32 scanr_exp_ms;
++	u32 scan_int;
++	u8 rssi_threshold;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhu %u %u %hhu", &rssi_diff_th, &scanr_exp_ms, &scan_int, &rssi_threshold);
++
++		if (num >= 1)
++			mlme->roam_rssi_diff_th = rssi_diff_th;
++		if (num >= 2)
++			mlme->roam_scanr_exp_ms = scanr_exp_ms;
++		if (num >= 3)
++			mlme->roam_scan_int = scan_int;
++		if (num >= 4)
++			mlme->roam_rssi_threshold = rssi_threshold;
++	}
++
++	return count;
++
++}
++
++ssize_t proc_set_roam_tgt_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	char tmp[32];
++	u8 addr[ETH_ALEN];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", addr, addr + 1, addr + 2, addr + 3, addr + 4, addr + 5);
++		if (num == 6)
++			_rtw_memcpy(adapter->mlmepriv.roam_tgt_addr, addr, ETH_ALEN);
++
++		RTW_INFO("set roam_tgt_addr to "MAC_FMT"\n", MAC_ARG(adapter->mlmepriv.roam_tgt_addr));
++	}
++
++	return count;
++}
++#endif /* CONFIG_LAYER2_ROAMING */
++
++int proc_get_qos_option(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++	RTW_PRINT_SEL(m, "qos_option=%d\n", pmlmepriv->qospriv.qos_option);
++
++	return 0;
++}
++
++int proc_get_ht_option(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++#ifdef CONFIG_80211N_HT
++	RTW_PRINT_SEL(m, "ht_option=%d\n", pmlmepriv->htpriv.ht_option);
++#endif /* CONFIG_80211N_HT */
++
++	return 0;
++}
++
++int proc_get_rf_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++
++	RTW_PRINT_SEL(m, "cur_ch=%d, cur_bw=%d, cur_ch_offet=%d\n",
++		pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
++
++	RTW_PRINT_SEL(m, "oper_ch=%d, oper_bw=%d, oper_ch_offet=%d\n",
++		rtw_get_oper_ch(padapter), rtw_get_oper_bw(padapter),  rtw_get_oper_choffset(padapter));
++
++	return 0;
++}
++
++int proc_get_scan_param(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++	struct ss_res *ss = &mlmeext->sitesurvey_res;
++
++#define SCAN_PARAM_TITLE_FMT "%10s"
++#define SCAN_PARAM_VALUE_FMT "%-10u"
++#define SCAN_PARAM_TITLE_ARG , "scan_ch_ms"
++#define SCAN_PARAM_VALUE_ARG , ss->scan_ch_ms
++#ifdef CONFIG_80211N_HT
++#define SCAN_PARAM_TITLE_FMT_HT " %15s %13s"
++#define SCAN_PARAM_VALUE_FMT_HT " %-15u %-13u"
++#define SCAN_PARAM_TITLE_ARG_HT , "rx_ampdu_accept", "rx_ampdu_size"
++#define SCAN_PARAM_VALUE_ARG_HT , ss->rx_ampdu_accept, ss->rx_ampdu_size
++#else
++#define SCAN_PARAM_TITLE_FMT_HT ""
++#define SCAN_PARAM_VALUE_FMT_HT ""
++#define SCAN_PARAM_TITLE_ARG_HT
++#define SCAN_PARAM_VALUE_ARG_HT
++#endif
++#ifdef CONFIG_SCAN_BACKOP
++#define SCAN_PARAM_TITLE_FMT_BACKOP " %9s %12s"
++#define SCAN_PARAM_VALUE_FMT_BACKOP " %-9u %-12u"
++#define SCAN_PARAM_TITLE_ARG_BACKOP , "backop_ms", "scan_cnt_max"
++#define SCAN_PARAM_VALUE_ARG_BACKOP , ss->backop_ms, ss->scan_cnt_max
++#else
++#define SCAN_PARAM_TITLE_FMT_BACKOP ""
++#define SCAN_PARAM_VALUE_FMT_BACKOP ""
++#define SCAN_PARAM_TITLE_ARG_BACKOP
++#define SCAN_PARAM_VALUE_ARG_BACKOP
++#endif
++
++	RTW_PRINT_SEL(m,
++		SCAN_PARAM_TITLE_FMT
++		SCAN_PARAM_TITLE_FMT_HT
++		SCAN_PARAM_TITLE_FMT_BACKOP
++		"\n"
++		SCAN_PARAM_TITLE_ARG
++		SCAN_PARAM_TITLE_ARG_HT
++		SCAN_PARAM_TITLE_ARG_BACKOP
++	);
++
++	RTW_PRINT_SEL(m,
++		SCAN_PARAM_VALUE_FMT
++		SCAN_PARAM_VALUE_FMT_HT
++		SCAN_PARAM_VALUE_FMT_BACKOP
++		"\n"
++		SCAN_PARAM_VALUE_ARG
++		SCAN_PARAM_VALUE_ARG_HT
++		SCAN_PARAM_VALUE_ARG_BACKOP
++	);
++
++	return 0;
++}
++
++ssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++	struct ss_res *ss = &mlmeext->sitesurvey_res;
++
++	char tmp[32] = {0};
++
++	u16 scan_ch_ms;
++#define SCAN_PARAM_INPUT_FMT "%hu"
++#define SCAN_PARAM_INPUT_ARG , &scan_ch_ms
++#ifdef CONFIG_80211N_HT
++	u8 rx_ampdu_accept;
++	u8 rx_ampdu_size;
++#define SCAN_PARAM_INPUT_FMT_HT " %hhu %hhu"
++#define SCAN_PARAM_INPUT_ARG_HT , &rx_ampdu_accept, &rx_ampdu_size
++#else
++#define SCAN_PARAM_INPUT_FMT_HT ""
++#define SCAN_PARAM_INPUT_ARG_HT
++#endif
++#ifdef CONFIG_SCAN_BACKOP
++	u16 backop_ms;
++	u8 scan_cnt_max;
++#define SCAN_PARAM_INPUT_FMT_BACKOP " %hu %hhu"
++#define SCAN_PARAM_INPUT_ARG_BACKOP , &backop_ms, &scan_cnt_max
++#else
++#define SCAN_PARAM_INPUT_FMT_BACKOP ""
++#define SCAN_PARAM_INPUT_ARG_BACKOP
++#endif
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp,
++			SCAN_PARAM_INPUT_FMT
++			SCAN_PARAM_INPUT_FMT_HT
++			SCAN_PARAM_INPUT_FMT_BACKOP
++			SCAN_PARAM_INPUT_ARG
++			SCAN_PARAM_INPUT_ARG_HT
++			SCAN_PARAM_INPUT_ARG_BACKOP
++		);
++
++		if (num-- > 0)
++			ss->scan_ch_ms = scan_ch_ms;
++#ifdef CONFIG_80211N_HT
++		if (num-- > 0)
++			ss->rx_ampdu_accept = rx_ampdu_accept;
++		if (num-- > 0)
++			ss->rx_ampdu_size = rx_ampdu_size;
++#endif
++#ifdef CONFIG_SCAN_BACKOP
++		if (num-- > 0)
++			ss->backop_ms = backop_ms;
++		if (num-- > 0)
++			ss->scan_cnt_max = scan_cnt_max;
++#endif
++	}
++
++	return count;
++}
++
++int proc_get_scan_abort(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	u32 pass_ms;
++
++	pass_ms = rtw_scan_abort_timeout(adapter, 10000);
++
++	RTW_PRINT_SEL(m, "%u\n", pass_ms);
++
++	return 0;
++}
++
++#ifdef CONFIG_RTW_REPEATER_SON
++int proc_get_rson_data(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char rson_data_str[256];
++
++	rtw_rson_get_property_str(padapter, rson_data_str);
++	RTW_PRINT_SEL(m, "%s\n", rson_data_str);
++	return 0;
++}
++
++ssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
++	char tmp[64] = {0};
++	int num;
++	u8 field[10], value[64];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		num = sscanf(tmp, "%s %s", field, value);
++		if (num != 2) {
++			RTW_INFO("Invalid format : echo <field> <value> > son_data\n");
++			return count;
++		}
++		RTW_INFO("field=%s  value=%s\n", field, value);
++		num = rtw_rson_set_property(padapter, field, value);
++		if (num != 1) {
++			RTW_INFO("Invalid field(%s) or value(%s)\n", field, value);
++			return count;
++		}
++	}
++	return count;
++}
++#endif /*CONFIG_RTW_REPEATER_SON*/
++
++int proc_get_survey_info(struct seq_file *m, void *v)
++{
++	_irqL irqL;
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	_queue	*queue	= &(pmlmepriv->scanned_queue);
++	struct wlan_network	*pnetwork = NULL;
++	_list	*plist, *phead;
++	s32 notify_signal;
++	s16 notify_noise = 0;
++	u16  index = 0, ie_cap = 0;
++	unsigned char *ie_wpa = NULL, *ie_wpa2 = NULL, *ie_wps = NULL;
++	unsigned char *ie_p2p = NULL, *ssid = NULL;
++	char flag_str[64];
++	int ielen = 0;
++	u32 wpsielen = 0;
++#ifdef CONFIG_RTW_MESH
++	const char *ssid_title_str = "ssid/mesh_id";
++#else
++	const char *ssid_title_str = "ssid";
++#endif
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++	phead = get_list_head(queue);
++	if (!phead)
++		goto _exit;
++	plist = get_next(phead);
++	if (!plist)
++		goto _exit;
++
++#ifdef CONFIG_RTW_REPEATER_SON
++	rtw_rson_show_survey_info(m, plist, phead);
++#else
++
++	RTW_PRINT_SEL(m, "%5s  %-17s  %3s  %-3s  %-4s  %-4s  %5s  %32s  %32s\n", "index", "bssid", "ch", "RSSI", "SdBm", "Noise", "age", "flag", ssid_title_str);
++	while (1) {
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++		if (!pnetwork)
++			break;
++
++		if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE &&
++		    is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) {
++			notify_signal = translate_percentage_to_dbm(padapter->recvpriv.signal_strength);/* dbm */
++		} else {
++			notify_signal = translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength);/* dbm */
++		}
++
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++		if (IS_NM_ENABLE(padapter))
++			notify_noise = rtw_noise_query_by_chan_num(padapter, pnetwork->network.Configuration.DSConfig);
++#endif
++
++		ie_wpa = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &ielen, pnetwork->network.IELength - 12);
++		ie_wpa2 = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &ielen, pnetwork->network.IELength - 12);
++		ie_cap = rtw_get_capability(&pnetwork->network);
++		ie_wps = rtw_get_wps_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &wpsielen);
++		ie_p2p = rtw_get_p2p_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &ielen);
++		ssid = pnetwork->network.Ssid.Ssid;
++		sprintf(flag_str, "%s%s%s%s%s%s%s",
++			(ie_wpa) ? "[WPA]" : "",
++			(ie_wpa2) ? "[WPA2]" : "",
++			(!ie_wpa && !ie_wpa && ie_cap & BIT(4)) ? "[WEP]" : "",
++			(ie_wps) ? "[WPS]" : "",
++			(pnetwork->network.InfrastructureMode == Ndis802_11IBSS) ? "[IBSS]" :
++				(pnetwork->network.InfrastructureMode == Ndis802_11_mesh) ? "[MESH]" : "",
++			(ie_cap & BIT(0)) ? "[ESS]" : "",
++			(ie_p2p) ? "[P2P]" : "");
++		RTW_PRINT_SEL(m, "%5d  "MAC_FMT"  %3d  %3d  %4d  %4d    %5d  %32s  %32s\n",
++			++index,
++			MAC_ARG(pnetwork->network.MacAddress),
++			pnetwork->network.Configuration.DSConfig,
++			(int)pnetwork->network.Rssi,
++			notify_signal,
++			notify_noise,
++			rtw_get_passing_time_ms(pnetwork->last_scanned),
++			flag_str,
++			pnetwork->network.InfrastructureMode == Ndis802_11_mesh ? pnetwork->network.mesh_id.Ssid : pnetwork->network.Ssid.Ssid
++		);
++		plist = get_next(plist);
++	}
++#endif
++_exit:
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	return 0;
++}
++
++ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u8 _status = _FALSE;
++	u8 ssc_chk;
++	char tmp[32] = {0};
++	char cmd[8] = {0};
++	bool acs = 0;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%s", cmd);
++
++		if (num < 1)
++			return count;
++
++		if (strcmp("acs", cmd) == 0)
++			acs = 1;
++	}
++
++#if 1
++	ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
++	if (ssc_chk != SS_ALLOW)
++		goto exit;
++
++	rtw_ps_deny(padapter, PS_DENY_SCAN);
++	if (_FAIL == rtw_pwr_wakeup(padapter))
++		goto cancel_ps_deny;
++	if (!rtw_is_adapter_up(padapter)) {
++		RTW_INFO("scan abort!! adapter cannot use\n");
++		goto cancel_ps_deny;
++	}
++#else
++#ifdef CONFIG_MP_INCLUDED
++	if (rtw_mp_mode_check(padapter)) {
++		RTW_INFO("MP mode block Scan request\n");
++		goto exit;
++	}
++#endif
++	if (rtw_is_scan_deny(padapter)) {
++		RTW_INFO(FUNC_ADPT_FMT  ": scan deny\n", FUNC_ADPT_ARG(padapter));
++		goto exit;
++	}
++
++	rtw_ps_deny(padapter, PS_DENY_SCAN);
++	if (_FAIL == rtw_pwr_wakeup(padapter))
++		goto cancel_ps_deny;
++
++	if (!rtw_is_adapter_up(padapter)) {
++		RTW_INFO("scan abort!! adapter cannot use\n");
++		goto cancel_ps_deny;
++	}
++
++	if (rtw_mi_busy_traffic_check(padapter)) {
++		RTW_INFO("scan abort!! BusyTraffic == _TRUE\n");
++		goto cancel_ps_deny;
++	}
++
++	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
++		RTW_INFO("scan abort!! AP mode process WPS\n");
++		goto cancel_ps_deny;
++	}
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING) == _TRUE) {
++		RTW_INFO("scan abort!! fwstate=0x%x\n", pmlmepriv->fw_state);
++		goto cancel_ps_deny;
++	}
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_buddy_check_fwstate(padapter,
++		       WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING | WIFI_UNDER_WPS)) {
++		RTW_INFO("scan abort!! buddy_fwstate check failed\n");
++		goto cancel_ps_deny;
++	}
++#endif
++#endif
++
++	if (acs) {
++		#ifdef CONFIG_RTW_ACS
++		_status = rtw_set_acs_sitesurvey(padapter);
++		#endif
++	} else
++		_status = rtw_set_802_11_bssid_list_scan(padapter, NULL);
++
++cancel_ps_deny:
++	rtw_ps_deny_cancel(padapter, PS_DENY_SCAN);
++exit:
++	return count;
++}
++#ifdef ROKU_PRIVATE
++int proc_get_infra_ap(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	struct sta_info *psta;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct ht_priv_infra_ap *phtpriv = &pmlmepriv->htpriv_infra_ap;
++#ifdef CONFIG_80211AC_VHT
++	struct vht_priv_infra_ap *pvhtpriv = &pmlmepriv->vhtpriv_infra_ap;
++#endif
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
++		psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
++		if (psta) {
++			unsigned int i, j;
++			unsigned int Rx_ss = 0, Tx_ss = 0;
++			struct recv_reorder_ctrl *preorder_ctrl;
++
++			RTW_PRINT_SEL(m, "SSID=%s\n", pmlmeinfo->network.Ssid.Ssid);
++			RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
++			RTW_PRINT_SEL(m, "Supported rate=");
++			for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
++				if (pmlmeinfo->SupportedRates_infra_ap[i] == 0)
++					break;
++				RTW_PRINT_SEL(m, " 0x%x", pmlmeinfo->SupportedRates_infra_ap[i]);
++			}
++			RTW_PRINT_SEL(m, "\n");
++#ifdef CONFIG_80211N_HT
++			if (pmlmeinfo->ht_vht_received & BIT(0)) {
++				RTW_PRINT_SEL(m, "Supported MCS set=");
++				for (i = 0; i < 16 ; i++)
++					RTW_PRINT_SEL(m, " 0x%02x",  phtpriv->MCS_set_infra_ap[i]);
++				RTW_PRINT_SEL(m, "\n");
++				RTW_PRINT_SEL(m, "highest supported data rate=0x%x\n", phtpriv->rx_highest_data_rate_infra_ap);
++				RTW_PRINT_SEL(m, "HT_supported_channel_width_set=0x%x\n", phtpriv->channel_width_infra_ap);
++				RTW_PRINT_SEL(m, "sgi_20m=%d, sgi_40m=%d\n", phtpriv->sgi_20m_infra_ap, phtpriv->sgi_40m_infra_ap);
++				RTW_PRINT_SEL(m, "ldpc_cap=0x%x, stbc_cap=0x%x\n", phtpriv->ldpc_cap_infra_ap, phtpriv->stbc_cap_infra_ap);
++				RTW_PRINT_SEL(m, "HT_number_of_stream=%d\n", phtpriv->Rx_ss_infra_ap);
++			}
++#endif
++
++#ifdef CONFIG_80211AC_VHT
++			if (pmlmeinfo->ht_vht_received & BIT(1)) {
++				RTW_PRINT_SEL(m, "VHT_supported_channel_width_set=0x%x\n", pvhtpriv->channel_width_infra_ap);
++				RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", pvhtpriv->ldpc_cap_infra_ap, pvhtpriv->stbc_cap_infra_ap, pvhtpriv->beamform_cap_infra_ap);
++				RTW_PRINT_SEL(m, "Rx_vht_mcs_map=0x%x, Tx_vht_mcs_map=0x%x\n", *(u16 *)pvhtpriv->vht_mcs_map_infra_ap, *(u16 *)pvhtpriv->vht_mcs_map_tx_infra_ap);
++				RTW_PRINT_SEL(m, "VHT_number_of_stream=%d\n", pvhtpriv->number_of_streams_infra_ap);
++			}
++#endif
++		} else
++			RTW_PRINT_SEL(m, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress));
++	} else
++		RTW_PRINT_SEL(m, "this only applies to STA mode\n");
++	return 0;
++}
++
++#endif /* ROKU_PRIVATE */
++
++static int wireless_mode_to_str(u32 mode, char *str)
++{
++	str[0]='\0';
++	if (mode&WIRELESS_11A)
++		sprintf(str+strlen(str),"%s","A/");
++	if (mode&WIRELESS_11B)
++		sprintf(str+strlen(str),"%s","B/");
++	if (mode&WIRELESS_11G)
++		sprintf(str+strlen(str),"%s","G/");
++	if (mode&(WIRELESS_11_24N|WIRELESS_11_5N))
++		sprintf(str+strlen(str),"%s","N/");
++	if (mode&WIRELESS_11AC)
++		sprintf(str+strlen(str),"%s","AC/");
++
++	if (strlen(str)>1)
++		str[strlen(str)-1]='\0';
++
++	return strlen(str);
++}
++
++int proc_get_ap_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	struct sta_info *psta;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	char wl_mode[16];
++
++	/* ap vendor */
++	char vendor[VENDOR_NAME_LEN] = {0};
++	get_assoc_AP_Vendor(vendor,pmlmeinfo->assoc_AP_vendor);
++	RTW_PRINT_SEL(m,"AP Vendor %s\n", vendor);
++
++	psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
++	if (psta) {
++		wireless_mode_to_str(psta->wireless_mode, wl_mode);
++		RTW_PRINT_SEL(m, "SSID=%s\n", cur_network->network.Ssid.Ssid);
++		RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
++		RTW_PRINT_SEL(m, "cur_channel=%d, cur_bwmode=%d(%s), cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, ch_width_str(pmlmeext->cur_bwmode), pmlmeext->cur_ch_offset);
++		RTW_PRINT_SEL(m, "wireless_mode=0x%x(%s), rtsen=%d, cts2slef=%d\n", psta->wireless_mode, wl_mode, psta->rtsen, psta->cts2self);
++		RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n",
++			psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);
++#ifdef CONFIG_80211N_HT
++		RTW_PRINT_SEL(m, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
++		RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n"
++			, psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m);
++		RTW_PRINT_SEL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
++		RTW_PRINT_SEL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
++		RTW_PRINT_SEL(m, "ldpc_cap=0x%x, stbc_cap=0x%x, beamform_cap=0x%x\n", psta->htpriv.ldpc_cap, psta->htpriv.stbc_cap, psta->htpriv.beamform_cap);
++#endif /* CONFIG_80211N_HT */
++#ifdef CONFIG_80211AC_VHT
++		RTW_PRINT_SEL(m, "vht_en=%d, vht_sgi_80m=%d\n", psta->vhtpriv.vht_option, psta->vhtpriv.sgi_80m);
++		RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap);
++		RTW_PRINT_SEL(m, "vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\n", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len);
++#endif
++		sta_rx_reorder_ctl_dump(m, psta);
++	} else
++		RTW_PRINT_SEL(m, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress));
++
++	return 0;
++}
++
++ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct recv_priv  *precvpriv = &padapter->recvpriv;
++	char cmd[32] = {0};
++	u8 cnt = 0;
++
++	if (count > sizeof(cmd)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(cmd, buffer, count)) {
++		int num = sscanf(cmd, "%hhx", &cnt);
++
++		if (num == 1 && cnt == 0) {
++			precvpriv->dbg_rx_ampdu_drop_count = 0;
++			precvpriv->dbg_rx_ampdu_forced_indicate_count = 0;
++			precvpriv->dbg_rx_ampdu_loss_count = 0;
++			precvpriv->dbg_rx_dup_mgt_frame_drop_count = 0;
++			precvpriv->dbg_rx_ampdu_window_shift_cnt = 0;
++			precvpriv->dbg_rx_conflic_mac_addr_cnt = 0;
++			precvpriv->dbg_rx_drop_count = 0;
++		}
++	}
++
++	return count;
++}
++
++int proc_get_trx_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	int i;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	struct recv_priv  *precvpriv = &padapter->recvpriv;
++	struct hw_xmit *phwxmit;
++	u16 vo_params[4], vi_params[4], be_params[4], bk_params[4];
++
++	padapter->hal_func.read_wmmedca_reg(padapter, vo_params, vi_params, be_params, bk_params);
++
++	RTW_PRINT_SEL(m, "wmm_edca_vo, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", vo_params[0], vo_params[1], vo_params[2], vo_params[3]);
++	RTW_PRINT_SEL(m, "wmm_edca_vi, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", vi_params[0], vi_params[1], vi_params[2], vi_params[3]);
++	RTW_PRINT_SEL(m, "wmm_edca_be, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", be_params[0], be_params[1], be_params[2], be_params[3]);
++	RTW_PRINT_SEL(m, "wmm_edca_bk, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", bk_params[0], bk_params[1], bk_params[2], bk_params[3]);
++
++	dump_os_queue(m, padapter);
++
++	RTW_PRINT_SEL(m, "free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d\n"
++		, pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt);
++	RTW_PRINT_SEL(m, "free_ext_xmitbuf_cnt=%d, free_xframe_ext_cnt=%d\n"
++		, pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt);
++	RTW_PRINT_SEL(m, "free_recvframe_cnt=%d\n"
++		      , precvpriv->free_recvframe_cnt);
++
++	for (i = 0; i < 4; i++) {
++		phwxmit = pxmitpriv->hwxmits + i;
++		RTW_PRINT_SEL(m, "%d, hwq.accnt=%d\n", i, phwxmit->accnt);
++	}
++
++	rtw_hal_get_hwreg(padapter, HW_VAR_DUMP_MAC_TXFIFO, (u8 *)m);
++
++#ifdef CONFIG_USB_HCI
++	RTW_PRINT_SEL(m, "rx_urb_pending_cn=%d\n", ATOMIC_READ(&(precvpriv->rx_pending_cnt)));
++#endif
++
++	dump_rx_bh_tk(m, &GET_PRIMARY_ADAPTER(padapter)->recvpriv);
++
++	/* Folowing are RX info */
++	RTW_PRINT_SEL(m, "RX: Count of Packets dropped by Driver: %llu\n", (unsigned long long)precvpriv->dbg_rx_drop_count);
++	/* Counts of packets whose seq_num is less than preorder_ctrl->indicate_seq, Ex delay, retransmission, redundant packets and so on */
++	RTW_PRINT_SEL(m, "Rx: Counts of Packets Whose Seq_Num Less Than Reorder Control Seq_Num: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_drop_count);
++	/* How many times the Rx Reorder Timer is triggered. */
++	RTW_PRINT_SEL(m, "Rx: Reorder Time-out Trigger Counts: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_forced_indicate_count);
++	/* Total counts of packets loss */
++	RTW_PRINT_SEL(m, "Rx: Packet Loss Counts: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_loss_count);
++	RTW_PRINT_SEL(m, "Rx: Duplicate Management Frame Drop Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_dup_mgt_frame_drop_count);
++	RTW_PRINT_SEL(m, "Rx: AMPDU BA window shift Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_window_shift_cnt);
++	/*The same mac addr counts*/
++	RTW_PRINT_SEL(m, "Rx: Conflict MAC Address Frames Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_conflic_mac_addr_cnt);
++	return 0;
++}
++
++int proc_get_rate_ctl(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	u8 data_rate = 0, sgi = 0, data_fb = 0;
++
++	if (adapter->fix_rate != 0xff) {
++		data_rate = adapter->fix_rate & 0x7F;
++		sgi = adapter->fix_rate >> 7;
++		data_fb = adapter->data_fb ? 1 : 0;
++		RTW_PRINT_SEL(m, "FIXED %s%s%s\n"
++			, HDATA_RATE(data_rate)
++			, data_rate > DESC_RATE54M ? (sgi ? " SGI" : " LGI") : ""
++			, data_fb ? " FB" : ""
++		);
++		RTW_PRINT_SEL(m, "0x%02x %u\n", adapter->fix_rate, adapter->data_fb);
++	} else
++		RTW_PRINT_SEL(m, "RA\n");
++
++	return 0;
++}
++
++#ifdef 	CONFIG_PHDYM_FW_FIXRATE
++void phydm_fw_fix_rate(void *dm_void, u8 en, u8	macid, u8 bw, u8 rate);
++#endif
++ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	char tmp[32];
++	u8 fix_rate = 0xFF;
++#ifdef 	CONFIG_PHDYM_FW_FIXRATE
++	u8 bw = 0;
++#else
++	u8 data_fb = 0;
++#endif
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++#ifdef 	CONFIG_PHDYM_FW_FIXRATE
++		struct dm_struct *dm = adapter_to_phydm(adapter);
++		u8 en = 1, macid = 255;
++		_irqL	irqL;
++		_list	*plist, *phead;
++		struct sta_info *psta = NULL;
++		struct sta_priv	*pstapriv = &(adapter->stapriv);
++		u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++		u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
++		uint mac_id[NUM_STA];
++		int i, macid_rec_idx = 0;
++		int num = sscanf(tmp, "%hhx %hhu %hhu", &fix_rate, &bw, &macid);
++
++		if (num < 1) {
++			RTW_INFO("Invalid input!! \"ex: echo <rate> <bw> <macid> > /proc/.../rate_ctl\"\n");
++			return count;
++		}
++
++		if ((fix_rate == 0) || (fix_rate == 0xFF))
++			en = 0;
++			
++		if (macid != 255) {
++			RTW_INFO("Call phydm_fw_fix_rate()--en[%d] mac_id[%d] bw[%d] fix_rate[%d]\n", en, macid, bw, fix_rate);
++			phydm_fw_fix_rate(dm, en, macid, bw, fix_rate);
++			return count;
++		}
++
++		/*	no specific macid, apply to all macids except bc/mc macid */
++		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++		for (i = 0; i < NUM_STA; i++) {
++			phead = &(pstapriv->sta_hash[i]);
++			plist = get_next(phead);
++			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++				plist = get_next(plist);
++				if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) !=  _TRUE)
++					&& (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE)
++					&& (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) {
++						mac_id[macid_rec_idx] = psta->cmn.mac_id;
++						macid_rec_idx++;
++				}
++			}
++		}
++		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++		for (i = 0; i < macid_rec_idx; i++) {
++			RTW_INFO("Call phydm_fw_fix_rate()--en[%d] mac_id[%d] bw[%d] fix_rate[%d]\n", en, mac_id[i], bw, fix_rate);
++			phydm_fw_fix_rate(dm, en, mac_id[i], bw, fix_rate);
++		}
++#else
++		int num = sscanf(tmp, "%hhx %hhu", &fix_rate, &data_fb);
++
++		if (num >= 1) {
++			u8 fix_rate_ori = adapter->fix_rate;
++
++			adapter->fix_rate = fix_rate;
++			if (fix_rate == 0xFF)
++				hal_data->ForcedDataRate = 0;
++			else
++				hal_data->ForcedDataRate = hw_rate_to_m_rate(fix_rate & 0x7F);
++
++			if (adapter->fix_bw != 0xFF && fix_rate_ori != fix_rate)
++				rtw_run_in_thread_cmd(adapter, ((void *)(rtw_update_tx_rate_bmp)), adapter_to_dvobj(adapter));
++		}
++		if (num >= 2)
++			adapter->data_fb = data_fb ? 1 : 0;
++#endif
++	}
++
++	return count;
++}
++
++#ifdef CONFIG_AP_MODE
++int proc_get_bmc_tx_rate(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (!MLME_IS_AP(adapter) && !MLME_IS_MESH(adapter)) {
++		RTW_PRINT_SEL(m, "[ERROR] Not in SoftAP/Mesh mode !!\n");
++		return 0;
++	}
++
++	RTW_PRINT_SEL(m, " BMC Tx rate - %s\n", MGN_RATE_STR(adapter->bmc_tx_rate));
++	return 0;
++}
++
++ssize_t proc_set_bmc_tx_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u8 bmc_tx_rate;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhx", &bmc_tx_rate);
++
++		if (num >= 1)
++			/*adapter->bmc_tx_rate = hw_rate_to_m_rate(bmc_tx_rate);*/
++			adapter->bmc_tx_rate = bmc_tx_rate;
++	}
++
++	return count;
++}
++#endif /*CONFIG_AP_MODE*/
++
++
++int proc_get_tx_power_offset(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_PRINT_SEL(m, "Tx power offset - %u\n", adapter->power_offset);
++	return 0;
++}
++
++ssize_t proc_set_tx_power_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u8 power_offset = 0;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhu", &power_offset);
++
++		if (num >= 1) {
++			if (power_offset > 5)
++				power_offset = 0;
++
++			adapter->power_offset = power_offset;
++		}
++	}
++
++	return count;
++}
++
++int proc_get_bw_ctl(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	u8 data_bw = 0;
++
++	if (adapter->fix_bw != 0xff) {
++		data_bw = adapter->fix_bw;
++		RTW_PRINT_SEL(m, "FIXED %s\n", ch_width_str(data_bw));
++	} else
++		RTW_PRINT_SEL(m, "Auto\n");
++
++	return 0;
++}
++
++ssize_t proc_set_bw_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u8 fix_bw;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%hhu", &fix_bw);
++
++		if (num >= 1) {
++			u8 fix_bw_ori = adapter->fix_bw;
++
++			adapter->fix_bw = fix_bw;
++
++			if (adapter->fix_rate != 0xFF && fix_bw_ori != fix_bw)
++				rtw_run_in_thread_cmd(adapter, ((void *)(rtw_update_tx_rate_bmp)), adapter_to_dvobj(adapter));
++		}
++	}
++
++	return count;
++}
++
++#ifdef DBG_RX_COUNTER_DUMP
++int proc_get_rx_cnt_dump(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	int i;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_PRINT_SEL(m, "BIT0- Dump RX counters of DRV\n");
++	RTW_PRINT_SEL(m, "BIT1- Dump RX counters of MAC\n");
++	RTW_PRINT_SEL(m, "BIT2- Dump RX counters of PHY\n");
++	RTW_PRINT_SEL(m, "BIT3- Dump TRX data frame of DRV\n");
++	RTW_PRINT_SEL(m, "dump_rx_cnt_mode = 0x%02x\n", adapter->dump_rx_cnt_mode);
++
++	return 0;
++}
++ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u8 dump_rx_cnt_mode;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhx", &dump_rx_cnt_mode);
++
++		if (num == 1) {
++			rtw_dump_phy_rxcnts_preprocess(adapter, dump_rx_cnt_mode);
++			adapter->dump_rx_cnt_mode = dump_rx_cnt_mode;
++		}
++	}
++
++	return count;
++}
++#endif
++
++ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	char tmp[32];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count))
++		sscanf(tmp, "%hhu %hhu", &fwdl_test_chksum_fail, &fwdl_test_wintint_rdy_fail);
++
++	return count;
++}
++
++ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	char tmp[32];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count))
++		sscanf(tmp, "%hhu", &del_rx_ampdu_test_no_tx_fail);
++
++	return count;
++}
++
++ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	char tmp[32];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count))
++		sscanf(tmp, "%u", &g_wait_hiq_empty_ms);
++
++	return count;
++}
++
++ssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	char tmp[32];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		u32 wait_ms = 0;
++		u8 force_fail = 0;
++		int num = sscanf(tmp, "%u %hhu", &wait_ms, &force_fail);
++
++		if (num >= 1)
++			sta_linking_test_wait_ms = wait_ms;
++		if (num >= 2)
++			sta_linking_test_force_fail = force_fail;
++	}
++
++	return count;
++}
++
++#ifdef CONFIG_AP_MODE
++ssize_t proc_set_ap_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	char tmp[32];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		u16 force_auth_fail = 0;
++		u16 force_asoc_fail = 0;
++		int num = sscanf(tmp, "%hu %hu", &force_auth_fail, &force_asoc_fail);
++
++		if (num >= 1)
++			ap_linking_test_force_auth_fail = force_auth_fail;
++		if (num >= 2)
++			ap_linking_test_force_asoc_fail = force_asoc_fail;
++	}
++
++	return count;
++}
++#endif /* CONFIG_AP_MODE */
++
++int proc_get_ps_dbg_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
++
++	RTW_PRINT_SEL(m, "dbg_sdio_alloc_irq_cnt=%d\n", pdbgpriv->dbg_sdio_alloc_irq_cnt);
++	RTW_PRINT_SEL(m, "dbg_sdio_free_irq_cnt=%d\n", pdbgpriv->dbg_sdio_free_irq_cnt);
++	RTW_PRINT_SEL(m, "dbg_sdio_alloc_irq_error_cnt=%d\n", pdbgpriv->dbg_sdio_alloc_irq_error_cnt);
++	RTW_PRINT_SEL(m, "dbg_sdio_free_irq_error_cnt=%d\n", pdbgpriv->dbg_sdio_free_irq_error_cnt);
++	RTW_PRINT_SEL(m, "dbg_sdio_init_error_cnt=%d\n", pdbgpriv->dbg_sdio_init_error_cnt);
++	RTW_PRINT_SEL(m, "dbg_sdio_deinit_error_cnt=%d\n", pdbgpriv->dbg_sdio_deinit_error_cnt);
++	RTW_PRINT_SEL(m, "dbg_suspend_error_cnt=%d\n", pdbgpriv->dbg_suspend_error_cnt);
++	RTW_PRINT_SEL(m, "dbg_suspend_cnt=%d\n", pdbgpriv->dbg_suspend_cnt);
++	RTW_PRINT_SEL(m, "dbg_resume_cnt=%d\n", pdbgpriv->dbg_resume_cnt);
++	RTW_PRINT_SEL(m, "dbg_resume_error_cnt=%d\n", pdbgpriv->dbg_resume_error_cnt);
++	RTW_PRINT_SEL(m, "dbg_deinit_fail_cnt=%d\n", pdbgpriv->dbg_deinit_fail_cnt);
++	RTW_PRINT_SEL(m, "dbg_carddisable_cnt=%d\n", pdbgpriv->dbg_carddisable_cnt);
++	RTW_PRINT_SEL(m, "dbg_ps_insuspend_cnt=%d\n", pdbgpriv->dbg_ps_insuspend_cnt);
++	RTW_PRINT_SEL(m, "dbg_dev_unload_inIPS_cnt=%d\n", pdbgpriv->dbg_dev_unload_inIPS_cnt);
++	RTW_PRINT_SEL(m, "dbg_scan_pwr_state_cnt=%d\n", pdbgpriv->dbg_scan_pwr_state_cnt);
++	RTW_PRINT_SEL(m, "dbg_downloadfw_pwr_state_cnt=%d\n", pdbgpriv->dbg_downloadfw_pwr_state_cnt);
++	RTW_PRINT_SEL(m, "dbg_carddisable_error_cnt=%d\n", pdbgpriv->dbg_carddisable_error_cnt);
++	RTW_PRINT_SEL(m, "dbg_fw_read_ps_state_fail_cnt=%d\n", pdbgpriv->dbg_fw_read_ps_state_fail_cnt);
++	RTW_PRINT_SEL(m, "dbg_leave_ips_fail_cnt=%d\n", pdbgpriv->dbg_leave_ips_fail_cnt);
++	RTW_PRINT_SEL(m, "dbg_leave_lps_fail_cnt=%d\n", pdbgpriv->dbg_leave_lps_fail_cnt);
++	RTW_PRINT_SEL(m, "dbg_h2c_leave32k_fail_cnt=%d\n", pdbgpriv->dbg_h2c_leave32k_fail_cnt);
++	RTW_PRINT_SEL(m, "dbg_diswow_dload_fw_fail_cnt=%d\n", pdbgpriv->dbg_diswow_dload_fw_fail_cnt);
++	RTW_PRINT_SEL(m, "dbg_enwow_dload_fw_fail_cnt=%d\n", pdbgpriv->dbg_enwow_dload_fw_fail_cnt);
++	RTW_PRINT_SEL(m, "dbg_ips_drvopen_fail_cnt=%d\n", pdbgpriv->dbg_ips_drvopen_fail_cnt);
++	RTW_PRINT_SEL(m, "dbg_poll_fail_cnt=%d\n", pdbgpriv->dbg_poll_fail_cnt);
++	RTW_PRINT_SEL(m, "dbg_rpwm_toogle_cnt=%d\n", pdbgpriv->dbg_rpwm_toogle_cnt);
++	RTW_PRINT_SEL(m, "dbg_rpwm_timeout_fail_cnt=%d\n", pdbgpriv->dbg_rpwm_timeout_fail_cnt);
++	RTW_PRINT_SEL(m, "dbg_sreset_cnt=%d\n", pdbgpriv->dbg_sreset_cnt);
++	RTW_PRINT_SEL(m, "dbg_fw_mem_dl_error_cnt=%d\n", pdbgpriv->dbg_fw_mem_dl_error_cnt);
++
++	return 0;
++}
++ssize_t proc_set_ps_dbg_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = adapter->dvobj;
++	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
++	char tmp[32];
++	u8 ps_dbg_cmd_id;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhx", &ps_dbg_cmd_id);
++
++		if (num == 1 && ps_dbg_cmd_id == 1) /*Clean all*/
++			_rtw_memset(pdbgpriv, 0, sizeof(struct debug_priv));
++
++	}
++
++	return count;
++}
++
++
++#ifdef CONFIG_DBG_COUNTER
++
++int proc_get_rx_logs(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rx_logs *rx_logs = &padapter->rx_logs;
++
++	RTW_PRINT_SEL(m,
++		      "intf_rx=%d\n"
++		      "intf_rx_err_recvframe=%d\n"
++		      "intf_rx_err_skb=%d\n"
++		      "intf_rx_report=%d\n"
++		      "core_rx=%d\n"
++		      "core_rx_pre=%d\n"
++		      "core_rx_pre_ver_err=%d\n"
++		      "core_rx_pre_mgmt=%d\n"
++		      "core_rx_pre_mgmt_err_80211w=%d\n"
++		      "core_rx_pre_mgmt_err=%d\n"
++		      "core_rx_pre_ctrl=%d\n"
++		      "core_rx_pre_ctrl_err=%d\n"
++		      "core_rx_pre_data=%d\n"
++		      "core_rx_pre_data_wapi_seq_err=%d\n"
++		      "core_rx_pre_data_wapi_key_err=%d\n"
++		      "core_rx_pre_data_handled=%d\n"
++		      "core_rx_pre_data_err=%d\n"
++		      "core_rx_pre_data_unknown=%d\n"
++		      "core_rx_pre_unknown=%d\n"
++		      "core_rx_enqueue=%d\n"
++		      "core_rx_dequeue=%d\n"
++		      "core_rx_post=%d\n"
++		      "core_rx_post_decrypt=%d\n"
++		      "core_rx_post_decrypt_wep=%d\n"
++		      "core_rx_post_decrypt_tkip=%d\n"
++		      "core_rx_post_decrypt_aes=%d\n"
++		      "core_rx_post_decrypt_wapi=%d\n"
++		      "core_rx_post_decrypt_hw=%d\n"
++		      "core_rx_post_decrypt_unknown=%d\n"
++		      "core_rx_post_decrypt_err=%d\n"
++		      "core_rx_post_defrag_err=%d\n"
++		      "core_rx_post_portctrl_err=%d\n"
++		      "core_rx_post_indicate=%d\n"
++		      "core_rx_post_indicate_in_oder=%d\n"
++		      "core_rx_post_indicate_reoder=%d\n"
++		      "core_rx_post_indicate_err=%d\n"
++		      "os_indicate=%d\n"
++		      "os_indicate_ap_mcast=%d\n"
++		      "os_indicate_ap_forward=%d\n"
++		      "os_indicate_ap_self=%d\n"
++		      "os_indicate_err=%d\n"
++		      "os_netif_ok=%d\n"
++		      "os_netif_err=%d\n",
++		      rx_logs->intf_rx,
++		      rx_logs->intf_rx_err_recvframe,
++		      rx_logs->intf_rx_err_skb,
++		      rx_logs->intf_rx_report,
++		      rx_logs->core_rx,
++		      rx_logs->core_rx_pre,
++		      rx_logs->core_rx_pre_ver_err,
++		      rx_logs->core_rx_pre_mgmt,
++		      rx_logs->core_rx_pre_mgmt_err_80211w,
++		      rx_logs->core_rx_pre_mgmt_err,
++		      rx_logs->core_rx_pre_ctrl,
++		      rx_logs->core_rx_pre_ctrl_err,
++		      rx_logs->core_rx_pre_data,
++		      rx_logs->core_rx_pre_data_wapi_seq_err,
++		      rx_logs->core_rx_pre_data_wapi_key_err,
++		      rx_logs->core_rx_pre_data_handled,
++		      rx_logs->core_rx_pre_data_err,
++		      rx_logs->core_rx_pre_data_unknown,
++		      rx_logs->core_rx_pre_unknown,
++		      rx_logs->core_rx_enqueue,
++		      rx_logs->core_rx_dequeue,
++		      rx_logs->core_rx_post,
++		      rx_logs->core_rx_post_decrypt,
++		      rx_logs->core_rx_post_decrypt_wep,
++		      rx_logs->core_rx_post_decrypt_tkip,
++		      rx_logs->core_rx_post_decrypt_aes,
++		      rx_logs->core_rx_post_decrypt_wapi,
++		      rx_logs->core_rx_post_decrypt_hw,
++		      rx_logs->core_rx_post_decrypt_unknown,
++		      rx_logs->core_rx_post_decrypt_err,
++		      rx_logs->core_rx_post_defrag_err,
++		      rx_logs->core_rx_post_portctrl_err,
++		      rx_logs->core_rx_post_indicate,
++		      rx_logs->core_rx_post_indicate_in_oder,
++		      rx_logs->core_rx_post_indicate_reoder,
++		      rx_logs->core_rx_post_indicate_err,
++		      rx_logs->os_indicate,
++		      rx_logs->os_indicate_ap_mcast,
++		      rx_logs->os_indicate_ap_forward,
++		      rx_logs->os_indicate_ap_self,
++		      rx_logs->os_indicate_err,
++		      rx_logs->os_netif_ok,
++		      rx_logs->os_netif_err
++		     );
++
++	return 0;
++}
++
++int proc_get_tx_logs(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct tx_logs *tx_logs = &padapter->tx_logs;
++
++	RTW_PRINT_SEL(m,
++		      "os_tx=%d\n"
++		      "os_tx_err_up=%d\n"
++		      "os_tx_err_xmit=%d\n"
++		      "os_tx_m2u=%d\n"
++		      "os_tx_m2u_ignore_fw_linked=%d\n"
++		      "os_tx_m2u_ignore_self=%d\n"
++		      "os_tx_m2u_entry=%d\n"
++		      "os_tx_m2u_entry_err_xmit=%d\n"
++		      "os_tx_m2u_entry_err_skb=%d\n"
++		      "os_tx_m2u_stop=%d\n"
++		      "core_tx=%d\n"
++		      "core_tx_err_pxmitframe=%d\n"
++		      "core_tx_err_brtx=%d\n"
++		      "core_tx_upd_attrib=%d\n"
++		      "core_tx_upd_attrib_adhoc=%d\n"
++		      "core_tx_upd_attrib_sta=%d\n"
++		      "core_tx_upd_attrib_ap=%d\n"
++		      "core_tx_upd_attrib_unknown=%d\n"
++		      "core_tx_upd_attrib_dhcp=%d\n"
++		      "core_tx_upd_attrib_icmp=%d\n"
++		      "core_tx_upd_attrib_active=%d\n"
++		      "core_tx_upd_attrib_err_ucast_sta=%d\n"
++		      "core_tx_upd_attrib_err_ucast_ap_link=%d\n"
++		      "core_tx_upd_attrib_err_sta=%d\n"
++		      "core_tx_upd_attrib_err_link=%d\n"
++		      "core_tx_upd_attrib_err_sec=%d\n"
++		      "core_tx_ap_enqueue_warn_fwstate=%d\n"
++		      "core_tx_ap_enqueue_warn_sta=%d\n"
++		      "core_tx_ap_enqueue_warn_nosta=%d\n"
++		      "core_tx_ap_enqueue_warn_link=%d\n"
++		      "core_tx_ap_enqueue_warn_trigger=%d\n"
++		      "core_tx_ap_enqueue_mcast=%d\n"
++		      "core_tx_ap_enqueue_ucast=%d\n"
++		      "core_tx_ap_enqueue=%d\n"
++		      "intf_tx=%d\n"
++		      "intf_tx_pending_ac=%d\n"
++		      "intf_tx_pending_fw_under_survey=%d\n"
++		      "intf_tx_pending_fw_under_linking=%d\n"
++		      "intf_tx_pending_xmitbuf=%d\n"
++		      "intf_tx_enqueue=%d\n"
++		      "core_tx_enqueue=%d\n"
++		      "core_tx_enqueue_class=%d\n"
++		      "core_tx_enqueue_class_err_sta=%d\n"
++		      "core_tx_enqueue_class_err_nosta=%d\n"
++		      "core_tx_enqueue_class_err_fwlink=%d\n"
++		      "intf_tx_direct=%d\n"
++		      "intf_tx_direct_err_coalesce=%d\n"
++		      "intf_tx_dequeue=%d\n"
++		      "intf_tx_dequeue_err_coalesce=%d\n"
++		      "intf_tx_dump_xframe=%d\n"
++		      "intf_tx_dump_xframe_err_txdesc=%d\n"
++		      "intf_tx_dump_xframe_err_port=%d\n",
++		      tx_logs->os_tx,
++		      tx_logs->os_tx_err_up,
++		      tx_logs->os_tx_err_xmit,
++		      tx_logs->os_tx_m2u,
++		      tx_logs->os_tx_m2u_ignore_fw_linked,
++		      tx_logs->os_tx_m2u_ignore_self,
++		      tx_logs->os_tx_m2u_entry,
++		      tx_logs->os_tx_m2u_entry_err_xmit,
++		      tx_logs->os_tx_m2u_entry_err_skb,
++		      tx_logs->os_tx_m2u_stop,
++		      tx_logs->core_tx,
++		      tx_logs->core_tx_err_pxmitframe,
++		      tx_logs->core_tx_err_brtx,
++		      tx_logs->core_tx_upd_attrib,
++		      tx_logs->core_tx_upd_attrib_adhoc,
++		      tx_logs->core_tx_upd_attrib_sta,
++		      tx_logs->core_tx_upd_attrib_ap,
++		      tx_logs->core_tx_upd_attrib_unknown,
++		      tx_logs->core_tx_upd_attrib_dhcp,
++		      tx_logs->core_tx_upd_attrib_icmp,
++		      tx_logs->core_tx_upd_attrib_active,
++		      tx_logs->core_tx_upd_attrib_err_ucast_sta,
++		      tx_logs->core_tx_upd_attrib_err_ucast_ap_link,
++		      tx_logs->core_tx_upd_attrib_err_sta,
++		      tx_logs->core_tx_upd_attrib_err_link,
++		      tx_logs->core_tx_upd_attrib_err_sec,
++		      tx_logs->core_tx_ap_enqueue_warn_fwstate,
++		      tx_logs->core_tx_ap_enqueue_warn_sta,
++		      tx_logs->core_tx_ap_enqueue_warn_nosta,
++		      tx_logs->core_tx_ap_enqueue_warn_link,
++		      tx_logs->core_tx_ap_enqueue_warn_trigger,
++		      tx_logs->core_tx_ap_enqueue_mcast,
++		      tx_logs->core_tx_ap_enqueue_ucast,
++		      tx_logs->core_tx_ap_enqueue,
++		      tx_logs->intf_tx,
++		      tx_logs->intf_tx_pending_ac,
++		      tx_logs->intf_tx_pending_fw_under_survey,
++		      tx_logs->intf_tx_pending_fw_under_linking,
++		      tx_logs->intf_tx_pending_xmitbuf,
++		      tx_logs->intf_tx_enqueue,
++		      tx_logs->core_tx_enqueue,
++		      tx_logs->core_tx_enqueue_class,
++		      tx_logs->core_tx_enqueue_class_err_sta,
++		      tx_logs->core_tx_enqueue_class_err_nosta,
++		      tx_logs->core_tx_enqueue_class_err_fwlink,
++		      tx_logs->intf_tx_direct,
++		      tx_logs->intf_tx_direct_err_coalesce,
++		      tx_logs->intf_tx_dequeue,
++		      tx_logs->intf_tx_dequeue_err_coalesce,
++		      tx_logs->intf_tx_dump_xframe,
++		      tx_logs->intf_tx_dump_xframe_err_txdesc,
++		      tx_logs->intf_tx_dump_xframe_err_port
++		     );
++
++	return 0;
++}
++
++int proc_get_int_logs(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_PRINT_SEL(m,
++		      "all=%d\n"
++		      "err=%d\n"
++		      "tbdok=%d\n"
++		      "tbder=%d\n"
++		      "bcnderr=%d\n"
++		      "bcndma=%d\n"
++		      "bcndma_e=%d\n"
++		      "rx=%d\n"
++		      "rx_rdu=%d\n"
++		      "rx_fovw=%d\n"
++		      "txfovw=%d\n"
++		      "mgntok=%d\n"
++		      "highdok=%d\n"
++		      "bkdok=%d\n"
++		      "bedok=%d\n"
++		      "vidok=%d\n"
++		      "vodok=%d\n",
++		      padapter->int_logs.all,
++		      padapter->int_logs.err,
++		      padapter->int_logs.tbdok,
++		      padapter->int_logs.tbder,
++		      padapter->int_logs.bcnderr,
++		      padapter->int_logs.bcndma,
++		      padapter->int_logs.bcndma_e,
++		      padapter->int_logs.rx,
++		      padapter->int_logs.rx_rdu,
++		      padapter->int_logs.rx_fovw,
++		      padapter->int_logs.txfovw,
++		      padapter->int_logs.mgntok,
++		      padapter->int_logs.highdok,
++		      padapter->int_logs.bkdok,
++		      padapter->int_logs.bedok,
++		      padapter->int_logs.vidok,
++		      padapter->int_logs.vodok
++		     );
++
++	return 0;
++}
++
++#endif /* CONFIG_DBG_COUNTER */
++
++int proc_get_hw_status(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
++	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
++
++	if (regsty->check_hw_status == 0)
++		RTW_PRINT_SEL(m, "RX FIFO full count: not check in watch dog\n");
++	else if (pdbgpriv->dbg_rx_fifo_last_overflow == 1
++	    && pdbgpriv->dbg_rx_fifo_curr_overflow == 1
++	    && pdbgpriv->dbg_rx_fifo_diff_overflow == 1
++	   )
++		RTW_PRINT_SEL(m, "RX FIFO full count: no implementation\n");
++	else {
++		RTW_PRINT_SEL(m, "RX FIFO full count: last_time=%llu, current_time=%llu, differential=%llu\n"
++			, pdbgpriv->dbg_rx_fifo_last_overflow, pdbgpriv->dbg_rx_fifo_curr_overflow, pdbgpriv->dbg_rx_fifo_diff_overflow);
++	}
++
++	return 0;
++}
++
++ssize_t proc_set_hw_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = padapter->dvobj;
++	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
++	char tmp[32];
++	u32 enable;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d ", &enable);
++
++		if (num == 1 && regsty && enable <= 1) {
++			regsty->check_hw_status = enable;
++			RTW_INFO("check_hw_status=%d\n", regsty->check_hw_status);
++		}
++	}
++
++	return count;
++}
++
++#ifdef CONFIG_HUAWEI_PROC
++int proc_get_huawei_trx_info(struct seq_file *sel, void *v)
++{
++	struct net_device *dev = sel->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dm_struct *dm = adapter_to_phydm(padapter);
++	struct sta_info *psta;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++	struct ra_sta_info *ra_info;
++	u8 curr_tx_sgi = _FALSE;
++	u8 curr_tx_rate = 0;
++	u8 mac_id;
++#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
++	u8 isCCKrate, rf_path;
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++	struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
++#endif
++
++	if (!dm->is_linked) {
++		RTW_PRINT_SEL(sel, "NO link\n\n");
++		return 0;
++	}
++
++	/*============  tx info ============	*/
++	for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) {
++		if (rtw_macid_is_used(macid_ctl, mac_id) && !rtw_macid_is_bmc(macid_ctl, mac_id)) {
++			psta = macid_ctl->sta[mac_id];
++			if (!psta)
++				continue;
++
++			RTW_PRINT_SEL(sel, "STA [" MAC_FMT "]\n", MAC_ARG(psta->cmn.mac_addr));
++
++			ra_info = &psta->cmn.ra_info;
++			curr_tx_sgi = rtw_get_current_tx_sgi(padapter, psta);
++			curr_tx_rate = rtw_get_current_tx_rate(padapter, psta);
++			RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n",
++					HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L");
++			RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw));
++		}
++	}
++
++	/*============  rx info ============	*/
++	RTW_PRINT_SEL(sel, "rx_rate : %s\n", HDATA_RATE(dm->rx_rate));
++#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
++	isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? TRUE : FALSE;
++
++	for (rf_path = 0; rf_path < hal_spec->rf_reg_path_num; rf_path++) {
++		if (!(GET_HAL_RX_PATH_BMP(padapter) & BIT(rf_path)))
++			continue;
++		if (!isCCKrate)
++			_RTW_PRINT_SEL(sel , "RF_PATH_%d : rx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\n",
++				rf_path, psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);
++	}
++#endif
++	RTW_PRINT_SEL(sel, "\n");
++	return 0;
++}
++#endif /* CONFIG_HUAWEI_PROC */
++
++int proc_get_trx_info_debug(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	/*============  tx info ============	*/
++	rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, m);
++
++	/*============  rx info ============	*/
++	rtw_hal_set_odm_var(padapter, HAL_ODM_RX_INFO_DUMP, m, _FALSE);
++
++	return 0;
++}
++
++int proc_get_rx_signal(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_PRINT_SEL(m, "rssi:%d\n", padapter->recvpriv.rssi);
++#ifdef CONFIG_MP_INCLUDED
++	if (padapter->registrypriv.mp_mode == 1) {
++		struct dm_struct *odm = adapter_to_phydm(padapter);
++		if (padapter->mppriv.antenna_rx == ANTENNA_A)
++			RTW_PRINT_SEL(m, "Antenna: A\n");
++		else if (padapter->mppriv.antenna_rx == ANTENNA_B)
++			RTW_PRINT_SEL(m, "Antenna: B\n");
++		else if (padapter->mppriv.antenna_rx == ANTENNA_C)
++			RTW_PRINT_SEL(m, "Antenna: C\n");
++		else if (padapter->mppriv.antenna_rx == ANTENNA_D)
++			RTW_PRINT_SEL(m, "Antenna: D\n");
++		else if (padapter->mppriv.antenna_rx == ANTENNA_AB)
++			RTW_PRINT_SEL(m, "Antenna: AB\n");
++		else if (padapter->mppriv.antenna_rx == ANTENNA_BC)
++			RTW_PRINT_SEL(m, "Antenna: BC\n");
++		else if (padapter->mppriv.antenna_rx == ANTENNA_CD)
++			RTW_PRINT_SEL(m, "Antenna: CD\n");
++		else
++			RTW_PRINT_SEL(m, "Antenna: __\n");
++
++		RTW_PRINT_SEL(m, "rx_rate = %s\n", HDATA_RATE(odm->rx_rate));
++		return 0;
++	} else 
++#endif
++	{
++		/* RTW_PRINT_SEL(m, "rxpwdb:%d\n", padapter->recvpriv.rxpwdb); */
++		RTW_PRINT_SEL(m, "signal_strength:%u\n", padapter->recvpriv.signal_strength);
++		RTW_PRINT_SEL(m, "signal_qual:%u\n", padapter->recvpriv.signal_qual);
++	}
++#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
++	rtw_odm_get_perpkt_rssi(m, padapter);
++	rtw_get_raw_rssi_info(m, padapter);
++#endif
++	return 0;
++}
++
++ssize_t proc_set_rx_signal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u32 is_signal_dbg, signal_strength;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%u %u", &is_signal_dbg, &signal_strength);
++
++		if (num < 1)
++			return count;
++
++		is_signal_dbg = is_signal_dbg == 0 ? 0 : 1;
++
++		if (is_signal_dbg && num < 2)
++			return count;
++
++		signal_strength = signal_strength > 100 ? 100 : signal_strength;
++
++		padapter->recvpriv.is_signal_dbg = is_signal_dbg;
++		padapter->recvpriv.signal_strength_dbg = signal_strength;
++
++		if (is_signal_dbg)
++			RTW_INFO("set %s %u\n", "DBG_SIGNAL_STRENGTH", signal_strength);
++		else
++			RTW_INFO("set %s\n", "HW_SIGNAL_STRENGTH");
++
++	}
++
++	return count;
++
++}
++
++int proc_get_mac_rptbuf(struct seq_file *m, void *v)
++{
++#ifdef CONFIG_RTL8814A
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u16 i;
++	u16 mac_id;
++	u32 shcut_addr = 0;
++	u32 read_addr = 0;
++
++	RTW_PRINT_SEL(m, "TX ShortCut:\n");
++	for (mac_id = 0; mac_id < 64; mac_id++) {
++		rtw_write16(padapter, 0x140, 0x662 | ((mac_id & BIT5) >> 5));
++		shcut_addr = 0x8000;
++		shcut_addr = shcut_addr | ((mac_id & 0x1f) << 7);
++		RTW_PRINT_SEL(m, "mac_id=%d, 0x140=%x =>\n", mac_id, 0x662 | ((mac_id & BIT5) >> 5));
++		for (i = 0; i < 30; i++) {
++			read_addr = 0;
++			read_addr = shcut_addr | (i << 2);
++			RTW_PRINT_SEL(m, "i=%02d: MAC_%04x= %08x ", i, read_addr, rtw_read32(padapter, read_addr));
++			if (!((i + 1) % 4))
++				RTW_PRINT_SEL(m, "\n");
++			if (i == 29)
++				RTW_PRINT_SEL(m, "\n");
++		}
++	}
++#endif /* CONFIG_RTL8814A */
++	return 0;
++}
++
++#ifdef CONFIG_80211N_HT
++
++int proc_get_ht_enable(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++
++	if (pregpriv)
++		RTW_PRINT_SEL(m, "%d\n", pregpriv->ht_enable);
++
++	return 0;
++}
++
++ssize_t proc_set_ht_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++	char tmp[32];
++	u32 mode;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d ", &mode);
++
++		if ( num == 1 && pregpriv && mode < 2) {
++			pregpriv->ht_enable = mode;
++			RTW_INFO("ht_enable=%d\n", pregpriv->ht_enable);
++		}
++	}
++
++	return count;
++
++}
++
++int proc_get_bw_mode(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++
++	if (pregpriv)
++		RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->bw_mode);
++
++	return 0;
++}
++
++ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++	char tmp[32];
++	u32 mode;
++	u8 bw_2g;
++	u8 bw_5g;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%x ", &mode);
++		bw_5g = mode >> 4;
++		bw_2g = mode & 0x0f;
++
++		if (num == 1 && pregpriv && bw_2g <= 4 && bw_5g <= 4) {
++			pregpriv->bw_mode = mode;
++			printk("bw_mode=0x%x\n", mode);
++		}
++	}
++
++	return count;
++
++}
++
++int proc_get_ampdu_enable(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++
++	if (pregpriv)
++		RTW_PRINT_SEL(m, "%d\n", pregpriv->ampdu_enable);
++
++	return 0;
++}
++
++ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++	char tmp[32];
++	u32 mode;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d ", &mode);
++
++		if (num == 1 && pregpriv && mode < 2) {
++			pregpriv->ampdu_enable = mode;
++			printk("ampdu_enable=%d\n", mode);
++		}
++
++	}
++
++	return count;
++
++}
++
++
++void dump_regsty_rx_ampdu_size_limit(void *sel, _adapter *adapter)
++{
++	struct registry_priv *regsty = adapter_to_regsty(adapter);
++	int i;
++
++	RTW_PRINT_SEL(sel, "%-3s %-3s %-3s %-3s %-4s\n"
++		, "", "20M", "40M", "80M", "160M");
++	for (i = 0; i < 4; i++)
++		RTW_PRINT_SEL(sel, "%dSS %3u %3u %3u %4u\n", i + 1
++			, regsty->rx_ampdu_sz_limit_by_nss_bw[i][0]
++			, regsty->rx_ampdu_sz_limit_by_nss_bw[i][1]
++			, regsty->rx_ampdu_sz_limit_by_nss_bw[i][2]
++			, regsty->rx_ampdu_sz_limit_by_nss_bw[i][3]);
++}
++
++int proc_get_rx_ampdu(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	_RTW_PRINT_SEL(m, "accept: ");
++	if (padapter->fix_rx_ampdu_accept == RX_AMPDU_ACCEPT_INVALID)
++		RTW_PRINT_SEL(m, "%u%s\n", rtw_rx_ampdu_is_accept(padapter), "(auto)");
++	else
++		RTW_PRINT_SEL(m, "%u%s\n", padapter->fix_rx_ampdu_accept, "(fixed)");
++
++	_RTW_PRINT_SEL(m, "size: ");
++	if (padapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID) {
++		RTW_PRINT_SEL(m, "%u%s\n", rtw_rx_ampdu_size(padapter), "(auto) with conditional limit:");
++		dump_regsty_rx_ampdu_size_limit(m, padapter);
++	} else
++		RTW_PRINT_SEL(m, "%u%s\n", padapter->fix_rx_ampdu_size, "(fixed)");
++	RTW_PRINT_SEL(m, "\n");
++
++	RTW_PRINT_SEL(m, "%19s %17s\n", "fix_rx_ampdu_accept", "fix_rx_ampdu_size");
++
++	_RTW_PRINT_SEL(m, "%-19d %-17u\n"
++		, padapter->fix_rx_ampdu_accept
++		, padapter->fix_rx_ampdu_size);
++
++	return 0;
++}
++
++ssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u8 accept;
++	u8 size;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhu %hhu", &accept, &size);
++
++		if (num >= 1)
++			rtw_rx_ampdu_set_accept(padapter, accept, RX_AMPDU_DRV_FIXED);
++		if (num >= 2)
++			rtw_rx_ampdu_set_size(padapter, size, RX_AMPDU_DRV_FIXED);
++
++		rtw_rx_ampdu_apply(padapter);
++	}
++
++	return count;
++}
++#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
++int proc_get_tx_aval_th(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++	if (padapter) {
++
++		switch(dvobj->tx_aval_int_thr_mode) {
++			case 0:
++				RTW_PRINT_SEL(m, "tx_aval_int_thr_mode = %u (auto) \n", dvobj->tx_aval_int_thr_mode);
++				break;
++			case 1:
++				RTW_PRINT_SEL(m, "tx_aval_int_thr_mode = %u (fixed)\n", dvobj->tx_aval_int_thr_mode);
++				RTW_PRINT_SEL(m, "tx_aval_threshold = 0x%x\n", dvobj->tx_aval_int_thr_value);
++				break;
++			case 2:
++				RTW_PRINT_SEL(m, "tx_aval_int_thr_mode = %u(by sdio_tx_max_len)\n", dvobj->tx_aval_int_thr_mode);
++			   	break;
++			default:
++				break;
++		}
++	}
++	return 0;
++}
++
++ssize_t proc_set_tx_aval_th(struct file *file, const char __user *buffer
++				 , size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	char tmp[32];
++	u32 mode;
++	u32 threshold;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d %d ",&mode, &threshold);
++
++		if(num >= 1)
++			dvobj->tx_aval_int_thr_mode = mode;
++		if(num >= 2)
++			dvobj->tx_aval_int_thr_value = threshold;
++		RTW_INFO("dvobj->tx_aval_int_thr_mode= 0x%x\n", mode);
++		RTW_INFO("dvobj->tx_aval_int_thr_value= 0x%x(range need 1~255)\n", threshold);
++	}
++
++	return count;
++}
++#endif /*CONFIG_SDIO_TX_ENABLE_AVAL_INT*/
++
++int proc_get_rx_ampdu_factor(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++
++	if (padapter)
++		RTW_PRINT_SEL(m, "rx ampdu factor = %x\n", padapter->driver_rx_ampdu_factor);
++
++	return 0;
++}
++
++ssize_t proc_set_rx_ampdu_factor(struct file *file, const char __user *buffer
++				 , size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u32 factor;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d ", &factor);
++
++		if (padapter && (num == 1)) {
++			RTW_INFO("padapter->driver_rx_ampdu_factor = %x\n", factor);
++
++			if (factor  > 0x03)
++				padapter->driver_rx_ampdu_factor = 0xFF;
++			else
++				padapter->driver_rx_ampdu_factor = factor;
++		}
++	}
++
++	return count;
++}
++
++int proc_get_tx_max_agg_num(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++
++	if (padapter)
++		RTW_PRINT_SEL(m, "tx max AMPDU num = 0x%02x\n", padapter->driver_tx_max_agg_num);
++
++	return 0;
++}
++
++ssize_t proc_set_tx_max_agg_num(struct file *file, const char __user *buffer
++				 , size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u8 agg_num;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhx ", &agg_num);
++
++		if (padapter && (num == 1)) {
++			RTW_INFO("padapter->driver_tx_max_agg_num = 0x%02x\n", agg_num);
++
++			padapter->driver_tx_max_agg_num = agg_num;
++		}
++	}
++
++	return count;
++}
++
++int proc_get_rx_ampdu_density(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++
++	if (padapter)
++		RTW_PRINT_SEL(m, "rx ampdu densityg = %x\n", padapter->driver_rx_ampdu_spacing);
++
++	return 0;
++}
++
++ssize_t proc_set_rx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u32 density;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d ", &density);
++
++		if (padapter && (num == 1)) {
++			RTW_INFO("padapter->driver_rx_ampdu_spacing = %x\n", density);
++
++			if (density > 0x07)
++				padapter->driver_rx_ampdu_spacing = 0xFF;
++			else
++				padapter->driver_rx_ampdu_spacing = density;
++		}
++	}
++
++	return count;
++}
++
++int proc_get_tx_ampdu_density(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++
++	if (padapter)
++		RTW_PRINT_SEL(m, "tx ampdu density = %x\n", padapter->driver_ampdu_spacing);
++
++	return 0;
++}
++
++ssize_t proc_set_tx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u32 density;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d ", &density);
++
++		if (padapter && (num == 1)) {
++			RTW_INFO("padapter->driver_ampdu_spacing = %x\n", density);
++
++			if (density > 0x07)
++				padapter->driver_ampdu_spacing = 0xFF;
++			else
++				padapter->driver_ampdu_spacing = density;
++		}
++	}
++
++	return count;
++}
++
++int proc_get_tx_quick_addba_req(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++
++	if (padapter)
++		RTW_PRINT_SEL(m, "tx_quick_addba_req = %x\n", pregpriv->tx_quick_addba_req);
++
++	return 0;
++}
++
++ssize_t proc_set_tx_quick_addba_req(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++	char tmp[32];
++	u32 enable;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d ", &enable);
++
++		if (padapter && (num == 1)) {
++			pregpriv->tx_quick_addba_req = enable;
++			RTW_INFO("tx_quick_addba_req = %d\n", pregpriv->tx_quick_addba_req);
++		}
++	}
++
++	return count;
++}
++#ifdef CONFIG_TX_AMSDU
++int proc_get_tx_amsdu(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++	if (padapter)
++	{
++		RTW_PRINT_SEL(m, "tx amsdu = %d\n", padapter->tx_amsdu);
++		RTW_PRINT_SEL(m, "amsdu set timer conut = %u\n", pxmitpriv->amsdu_debug_set_timer);
++		RTW_PRINT_SEL(m, "amsdu  time out count = %u\n", pxmitpriv->amsdu_debug_timeout);
++		RTW_PRINT_SEL(m, "amsdu coalesce one count = %u\n", pxmitpriv->amsdu_debug_coalesce_one);
++		RTW_PRINT_SEL(m, "amsdu coalesce two count = %u\n", pxmitpriv->amsdu_debug_coalesce_two);
++	}
++
++	return 0;
++}
++
++ssize_t proc_set_tx_amsdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	char tmp[32];
++	u32 amsdu;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d ", &amsdu);
++
++		if (padapter && (num == 1)) {
++			RTW_INFO("padapter->tx_amsdu = %x\n", amsdu);
++
++			if (amsdu > 3)
++				padapter->tx_amsdu = 0;
++			else if(amsdu == 3)
++			{
++				pxmitpriv->amsdu_debug_set_timer = 0;
++				pxmitpriv->amsdu_debug_timeout = 0;
++				pxmitpriv->amsdu_debug_coalesce_one = 0;
++				pxmitpriv->amsdu_debug_coalesce_two = 0;
++			}
++			else
++				padapter->tx_amsdu = amsdu;
++		}
++	}
++
++	return count;
++}
++
++int proc_get_tx_amsdu_rate(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (padapter)
++		RTW_PRINT_SEL(m, "tx amsdu rate = %d Mbps\n", padapter->tx_amsdu_rate);
++
++	return 0;
++}
++
++ssize_t proc_set_tx_amsdu_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u32 amsdu_rate;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d ", &amsdu_rate);
++
++		if (padapter && (num == 1)) {
++			RTW_INFO("padapter->tx_amsdu_rate = %x\n", amsdu_rate);
++			padapter->tx_amsdu_rate = amsdu_rate;
++		}
++	}
++
++	return count;
++}
++#endif /* CONFIG_TX_AMSDU */
++#endif /* CONFIG_80211N_HT */
++ssize_t proc_set_dyn_rrsr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv *pregpriv = &padapter->registrypriv;
++
++	char tmp[32] = {0};
++	u32 num = 0, enable = 0, rrsr_val = 0; /* gpio_mode:0 input  1:output; */
++
++	if (count < 2)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		num	= sscanf(tmp, "%d 0x%x", &enable, &rrsr_val);
++		RTW_INFO("num=%u enable=%d rrsr_val=0x%x\n", num, enable, rrsr_val);
++		pregpriv->en_dyn_rrsr = enable;
++		pregpriv->set_rrsr_value = rrsr_val;
++		rtw_phydm_dyn_rrsr_en(padapter, enable);
++		rtw_phydm_set_rrsr(padapter, rrsr_val, TRUE);
++
++	}
++	return count;
++
++}
++int proc_get_dyn_rrsr(struct seq_file *m, void *v) {
++
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv *pregpriv = &padapter->registrypriv;
++	u32 init_rrsr =0xFFFFFFFF;
++
++	if (padapter) 
++		RTW_PRINT_SEL(m, "en_dyn_rrsr = %d fixed_rrsr_value =0x%x %s\n"
++			, pregpriv->en_dyn_rrsr
++			, pregpriv->set_rrsr_value 
++			, (pregpriv->set_rrsr_value == init_rrsr)?"(default)":"(fixed)"
++		);
++
++	return 0;
++}
++int proc_get_en_fwps(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++
++	if (pregpriv)
++		RTW_PRINT_SEL(m, "check_fw_ps = %d , 1:enable get FW PS state , 0: disable get FW PS state\n"
++			      , pregpriv->check_fw_ps);
++
++	return 0;
++}
++
++ssize_t proc_set_en_fwps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++	char tmp[32];
++	u32 mode;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d ", &mode);
++
++		if (num == 1 && pregpriv &&  mode < 2) {
++			pregpriv->check_fw_ps = mode;
++			RTW_INFO("pregpriv->check_fw_ps=%d\n", pregpriv->check_fw_ps);
++		}
++
++	}
++
++	return count;
++}
++
++/*
++int proc_get_two_path_rssi(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if(padapter)
++		RTW_PRINT_SEL(m, "%d %d\n",
++			padapter->recvpriv.RxRssi[0], padapter->recvpriv.RxRssi[1]);
++
++	return 0;
++}
++*/
++#ifdef CONFIG_80211N_HT
++void rtw_dump_dft_phy_cap(void *sel, _adapter *adapter)
++{
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	struct ht_priv	*phtpriv = &pmlmepriv->htpriv;
++	#ifdef CONFIG_80211AC_VHT
++	struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
++	#endif
++
++	#ifdef CONFIG_80211AC_VHT
++	RTW_PRINT_SEL(sel, "[DFT CAP] VHT STBC Tx : %s\n", (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) ? "V" : "X");
++	RTW_PRINT_SEL(sel, "[DFT CAP] VHT STBC Rx : %s\n", (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) ? "V" : "X");
++	#endif
++	RTW_PRINT_SEL(sel, "[DFT CAP] HT STBC Tx : %s\n", (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX)) ? "V" : "X");
++	RTW_PRINT_SEL(sel, "[DFT CAP] HT STBC Rx : %s\n\n", (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) ? "V" : "X");
++
++	#ifdef CONFIG_80211AC_VHT
++	RTW_PRINT_SEL(sel, "[DFT CAP] VHT LDPC Tx : %s\n", (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX)) ? "V" : "X");
++	RTW_PRINT_SEL(sel, "[DFT CAP] VHT LDPC Rx : %s\n", (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) ? "V" : "X");
++	#endif
++	RTW_PRINT_SEL(sel, "[DFT CAP] HT LDPC Tx : %s\n", (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX)) ? "V" : "X");
++	RTW_PRINT_SEL(sel, "[DFT CAP] HT LDPC Rx : %s\n\n", (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX)) ? "V" : "X");
++
++	#ifdef CONFIG_BEAMFORMING
++	#ifdef CONFIG_80211AC_VHT
++	RTW_PRINT_SEL(sel, "[DFT CAP] VHT MU Bfer : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) ? "V" : "X");
++	RTW_PRINT_SEL(sel, "[DFT CAP] VHT MU Bfee : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) ? "V" : "X");
++	RTW_PRINT_SEL(sel, "[DFT CAP] VHT SU Bfer : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) ? "V" : "X");
++	RTW_PRINT_SEL(sel, "[DFT CAP] VHT SU Bfee : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) ? "V" : "X");
++	#endif
++	RTW_PRINT_SEL(sel, "[DFT CAP] HT Bfer : %s\n", (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE))  ? "V" : "X");
++	RTW_PRINT_SEL(sel, "[DFT CAP] HT Bfee : %s\n", (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) ? "V" : "X");
++	#endif
++}
++
++void rtw_get_dft_phy_cap(void *sel, _adapter *adapter)
++{
++	RTW_PRINT_SEL(sel, "\n ======== PHY CAP protocol ========\n");
++	rtw_ht_use_default_setting(adapter);
++	#ifdef CONFIG_80211AC_VHT
++	rtw_vht_use_default_setting(adapter);
++	#endif
++	#ifdef CONFIG_80211N_HT
++	rtw_dump_dft_phy_cap(sel, adapter);
++	#endif
++}
++
++void rtw_dump_drv_phy_cap(void *sel, _adapter *adapter)
++{
++	struct registry_priv	*pregistry_priv = &adapter->registrypriv;
++
++	RTW_PRINT_SEL(sel, "\n ======== DRV's configuration ========\n");
++	#if 0
++	RTW_PRINT_SEL(sel, "[DRV CAP] TRx Capability : 0x%08x\n", phy_spec->trx_cap);
++	RTW_PRINT_SEL(sel, "[DRV CAP] Tx Stream Num Index : %d\n", (phy_spec->trx_cap >> 24) & 0xFF); /*Tx Stream Num Index [31:24]*/
++	RTW_PRINT_SEL(sel, "[DRV CAP] Rx Stream Num Index : %d\n", (phy_spec->trx_cap >> 16) & 0xFF); /*Rx Stream Num Index [23:16]*/
++	RTW_PRINT_SEL(sel, "[DRV CAP] Tx Path Num Index : %d\n", (phy_spec->trx_cap >> 8) & 0xFF);/*Tx Path Num Index	[15:8]*/
++	RTW_PRINT_SEL(sel, "[DRV CAP] Rx Path Num Index : %d\n", (phy_spec->trx_cap & 0xFF));/*Rx Path Num Index	[7:0]*/
++	#endif
++	#ifdef CONFIG_80211N_HT
++	RTW_PRINT_SEL(sel, "[DRV CAP] STBC Capability : 0x%02x\n", pregistry_priv->stbc_cap);
++	RTW_PRINT_SEL(sel, "[DRV CAP] VHT STBC Tx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT1)) ? "V" : "X"); /*BIT1: Enable VHT STBC Tx*/
++	RTW_PRINT_SEL(sel, "[DRV CAP] VHT STBC Rx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT0)) ? "V" : "X"); /*BIT0: Enable VHT STBC Rx*/
++	RTW_PRINT_SEL(sel, "[DRV CAP] HT STBC Tx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT5)) ? "V" : "X"); /*BIT5: Enable HT STBC Tx*/
++	RTW_PRINT_SEL(sel, "[DRV CAP] HT STBC Rx : %s\n\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT4)) ? "V" : "X"); /*BIT4: Enable HT STBC Rx*/
++
++	RTW_PRINT_SEL(sel, "[DRV CAP] LDPC Capability : 0x%02x\n", pregistry_priv->ldpc_cap);
++	RTW_PRINT_SEL(sel, "[DRV CAP] VHT LDPC Tx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT1)) ? "V" : "X"); /*BIT1: Enable VHT LDPC Tx*/
++	RTW_PRINT_SEL(sel, "[DRV CAP] VHT LDPC Rx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT0)) ? "V" : "X"); /*BIT0: Enable VHT LDPC Rx*/
++	RTW_PRINT_SEL(sel, "[DRV CAP] HT LDPC Tx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT5)) ? "V" : "X"); /*BIT5: Enable HT LDPC Tx*/
++	RTW_PRINT_SEL(sel, "[DRV CAP] HT LDPC Rx : %s\n\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT4)) ? "V" : "X"); /*BIT4: Enable HT LDPC Rx*/
++	#endif /* CONFIG_80211N_HT */
++	#ifdef CONFIG_BEAMFORMING
++	#if 0
++	RTW_PRINT_SEL(sel, "[DRV CAP] TxBF parameter : 0x%08x\n", phy_spec->txbf_param);
++	RTW_PRINT_SEL(sel, "[DRV CAP] VHT Sounding Dim : %d\n", (phy_spec->txbf_param >> 24) & 0xFF); /*VHT Sounding Dim [31:24]*/
++	RTW_PRINT_SEL(sel, "[DRV CAP] VHT Steering Ant : %d\n", (phy_spec->txbf_param >> 16) & 0xFF); /*VHT Steering Ant [23:16]*/
++	RTW_PRINT_SEL(sel, "[DRV CAP] HT Sounding Dim : %d\n", (phy_spec->txbf_param >> 8) & 0xFF); /*HT Sounding Dim [15:8]*/
++	RTW_PRINT_SEL(sel, "[DRV CAP] HT Steering Ant : %d\n", phy_spec->txbf_param & 0xFF); /*HT Steering Ant [7:0]*/
++	#endif
++
++	/*
++	 * BIT0: Enable VHT SU Beamformer
++	 * BIT1: Enable VHT SU Beamformee
++	 * BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer
++	 * BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee
++	 * BIT4: Enable HT Beamformer
++	 * BIT5: Enable HT Beamformee
++	 */
++	RTW_PRINT_SEL(sel, "[DRV CAP] TxBF Capability : 0x%02x\n", pregistry_priv->beamform_cap);
++	RTW_PRINT_SEL(sel, "[DRV CAP] VHT MU Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT2)) ? "V" : "X");
++	RTW_PRINT_SEL(sel, "[DRV CAP] VHT MU Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT3)) ? "V" : "X");
++	RTW_PRINT_SEL(sel, "[DRV CAP] VHT SU Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT0)) ? "V" : "X");
++	RTW_PRINT_SEL(sel, "[DRV CAP] VHT SU Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT1)) ? "V" : "X");
++	RTW_PRINT_SEL(sel, "[DRV CAP] HT Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT4))  ? "V" : "X");
++	RTW_PRINT_SEL(sel, "[DRV CAP] HT Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT5)) ? "V" : "X");
++
++	RTW_PRINT_SEL(sel, "[DRV CAP] Tx Bfer rf_num : %d\n", pregistry_priv->beamformer_rf_num);
++	RTW_PRINT_SEL(sel, "[DRV CAP] Tx Bfee rf_num : %d\n", pregistry_priv->beamformee_rf_num);
++	#endif
++}
++
++int proc_get_stbc_cap(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++
++	if (pregpriv)
++		RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->stbc_cap);
++
++	return 0;
++}
++
++ssize_t proc_set_stbc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++	char tmp[32];
++	u32 mode;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d ", &mode);
++
++		if (num == 1 && pregpriv) {
++			pregpriv->stbc_cap = mode;
++			RTW_INFO("stbc_cap = 0x%02x\n", mode);
++		}
++	}
++
++	return count;
++}
++int proc_get_rx_stbc(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++
++	if (pregpriv)
++		RTW_PRINT_SEL(m, "%d\n", pregpriv->rx_stbc);
++
++	return 0;
++}
++
++ssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++	char tmp[32];
++	u32 mode;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d ", &mode);
++
++		if (num == 1 && pregpriv && (mode == 0 || mode == 1 || mode == 2 || mode == 3)) {
++			pregpriv->rx_stbc = mode;
++			printk("rx_stbc=%d\n", mode);
++		}
++	}
++
++	return count;
++
++}
++int proc_get_ldpc_cap(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++
++	if (pregpriv)
++		RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->ldpc_cap);
++
++	return 0;
++}
++
++ssize_t proc_set_ldpc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++	char tmp[32];
++	u32 mode;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d ", &mode);
++
++		if (num == 1 && pregpriv) {
++			pregpriv->ldpc_cap = mode;
++			RTW_INFO("ldpc_cap = 0x%02x\n", mode);
++		}
++	}
++
++	return count;
++}
++#ifdef CONFIG_BEAMFORMING
++int proc_get_txbf_cap(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++
++	if (pregpriv)
++		RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->beamform_cap);
++
++	return 0;
++}
++
++ssize_t proc_set_txbf_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++	char tmp[32];
++	u32 mode;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d ", &mode);
++
++		if (num == 1 && pregpriv) {
++			pregpriv->beamform_cap = mode;
++			RTW_INFO("beamform_cap = 0x%02x\n", mode);
++		}
++	}
++
++	return count;
++}
++#endif
++#endif /* CONFIG_80211N_HT */
++
++/*int proc_get_rssi_disp(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	return 0;
++}
++*/
++
++/*ssize_t proc_set_rssi_disp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u32 enable=0;
++
++	if (count < 1)
++	{
++		RTW_INFO("argument size is less than 1\n");
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%x", &enable);
++
++		if (num !=  1) {
++			RTW_INFO("invalid set_rssi_disp parameter!\n");
++			return count;
++		}
++
++		if(enable)
++		{
++			RTW_INFO("Linked info Function Enable\n");
++			padapter->bLinkInfoDump = enable ;
++		}
++		else
++		{
++			RTW_INFO("Linked info Function Disable\n");
++			padapter->bLinkInfoDump = 0 ;
++		}
++
++	}
++
++	return count;
++
++}
++
++*/
++#ifdef CONFIG_AP_MODE
++
++int proc_get_all_sta_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_irqL irqL;
++	struct sta_info *psta;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	int i;
++	_list	*plist, *phead;
++
++	RTW_MAP_DUMP_SEL(m, "sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);
++	RTW_MAP_DUMP_SEL(m, "tim_bitmap=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len);
++
++	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++	for (i = 0; i < NUM_STA; i++) {
++		phead = &(pstapriv->sta_hash[i]);
++		plist = get_next(phead);
++
++		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++
++			plist = get_next(plist);
++
++			/* if(extra_arg == psta->cmn.aid) */
++			{
++				RTW_PRINT_SEL(m, "==============================\n");
++				RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
++				RTW_PRINT_SEL(m, "rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self);
++				RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n",
++					psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);
++#ifdef CONFIG_RTS_FULL_BW
++				if(psta->vendor_8812)
++					RTW_PRINT_SEL(m,"Vendor Realtek 8812\n");
++#endif/*CONFIG_RTS_FULL_BW*/
++#ifdef CONFIG_80211N_HT
++				RTW_PRINT_SEL(m, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
++				RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n"
++					, psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m);
++				RTW_PRINT_SEL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
++				RTW_PRINT_SEL(m, "tx_amsdu_enable = %d\n", psta->htpriv.tx_amsdu_enable);
++				RTW_PRINT_SEL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
++#endif /* CONFIG_80211N_HT */
++#ifdef CONFIG_80211AC_VHT
++				RTW_PRINT_SEL(m, "vht_en=%d, vht_sgi_80m=%d\n", psta->vhtpriv.vht_option, psta->vhtpriv.sgi_80m);
++				RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap);
++				RTW_PRINT_SEL(m, "vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\n", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len);
++#endif
++				RTW_PRINT_SEL(m, "sleepq_len=%d\n", psta->sleepq_len);
++				RTW_PRINT_SEL(m, "sta_xmitpriv.vo_q_qcnt=%d\n", psta->sta_xmitpriv.vo_q.qcnt);
++				RTW_PRINT_SEL(m, "sta_xmitpriv.vi_q_qcnt=%d\n", psta->sta_xmitpriv.vi_q.qcnt);
++				RTW_PRINT_SEL(m, "sta_xmitpriv.be_q_qcnt=%d\n", psta->sta_xmitpriv.be_q.qcnt);
++				RTW_PRINT_SEL(m, "sta_xmitpriv.bk_q_qcnt=%d\n", psta->sta_xmitpriv.bk_q.qcnt);
++
++				RTW_PRINT_SEL(m, "capability=0x%x\n", psta->capability);
++				RTW_PRINT_SEL(m, "flags=0x%x\n", psta->flags);
++				RTW_PRINT_SEL(m, "wpa_psk=0x%x\n", psta->wpa_psk);
++				RTW_PRINT_SEL(m, "wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher);
++				RTW_PRINT_SEL(m, "wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher);
++				RTW_PRINT_SEL(m, "qos_info=0x%x\n", psta->qos_info);
++				RTW_PRINT_SEL(m, "dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy);
++
++				sta_rx_reorder_ctl_dump(m, psta);
++
++#ifdef CONFIG_TDLS
++				RTW_PRINT_SEL(m, "tdls_sta_state=0x%08x\n", psta->tdls_sta_state);
++				RTW_PRINT_SEL(m, "PeerKey_Lifetime=%d\n", psta->TDLS_PeerKey_Lifetime);
++#endif /* CONFIG_TDLS */
++				RTW_PRINT_SEL(m, "rx_data_uc_pkts=%llu\n", sta_rx_data_uc_pkts(psta));
++				RTW_PRINT_SEL(m, "rx_data_mc_pkts=%llu\n", psta->sta_stats.rx_data_mc_pkts);
++				RTW_PRINT_SEL(m, "rx_data_bc_pkts=%llu\n", psta->sta_stats.rx_data_bc_pkts);
++				RTW_PRINT_SEL(m, "rx_uc_bytes=%llu\n", sta_rx_uc_bytes(psta));
++				RTW_PRINT_SEL(m, "rx_mc_bytes=%llu\n", psta->sta_stats.rx_mc_bytes);
++				RTW_PRINT_SEL(m, "rx_bc_bytes=%llu\n", psta->sta_stats.rx_bc_bytes);
++				if (psta->sta_stats.rx_tp_kbits >> 10)
++					RTW_PRINT_SEL(m, "rx_tp =%d (Mbps)\n", psta->sta_stats.rx_tp_kbits >> 10);
++				else
++					RTW_PRINT_SEL(m, "rx_tp =%d (Kbps)\n", psta->sta_stats.rx_tp_kbits);
++
++				RTW_PRINT_SEL(m, "tx_data_pkts=%llu\n", psta->sta_stats.tx_pkts);
++				RTW_PRINT_SEL(m, "tx_bytes=%llu\n", psta->sta_stats.tx_bytes);
++				if (psta->sta_stats.tx_tp_kbits >> 10)
++					RTW_PRINT_SEL(m, "tx_tp =%d (Mbps)\n", psta->sta_stats.tx_tp_kbits >> 10);
++				else
++					RTW_PRINT_SEL(m, "tx_tp =%d (Kbps)\n", psta->sta_stats.tx_tp_kbits);
++#ifdef CONFIG_RTW_80211K
++				RTW_PRINT_SEL(m, "rm_en_cap="RM_CAP_FMT"\n", RM_CAP_ARG(psta->rm_en_cap));
++#endif
++				dump_st_ctl(m, &psta->st_ctl);
++
++				if (STA_OP_WFD_MODE(psta))
++					RTW_PRINT_SEL(m, "op_wfd_mode:0x%02x\n", STA_OP_WFD_MODE(psta));
++
++				RTW_PRINT_SEL(m, "==============================\n");
++			}
++
++		}
++
++	}
++
++	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++	return 0;
++}
++
++#endif
++
++#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
++int proc_get_rtkm_info(struct seq_file *m, void *v)
++{
++#ifdef CONFIG_USB_HCI
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct recv_priv	*precvpriv = &padapter->recvpriv;
++	struct recv_buf *precvbuf;
++
++	precvbuf = (struct recv_buf *)precvpriv->precv_buf;
++#endif /* CONFIG_USB_HCI */
++
++	RTW_PRINT_SEL(m, "============[RTKM Info]============\n");
++	RTW_PRINT_SEL(m, "MAX_RTKM_NR_PREALLOC_RECV_SKB: %d\n", rtw_rtkm_get_nr_recv_skb());
++	RTW_PRINT_SEL(m, "MAX_RTKM_RECVBUF_SZ: %d\n", rtw_rtkm_get_buff_size());
++
++	RTW_PRINT_SEL(m, "============[Driver Info]============\n");
++	RTW_PRINT_SEL(m, "NR_PREALLOC_RECV_SKB: %d\n", NR_PREALLOC_RECV_SKB);
++#ifdef CONFIG_USB_HCI
++	RTW_PRINT_SEL(m, "MAX_RECVBUF_SZ: %d\n", precvbuf->alloc_sz);
++#else /* !CONFIG_USB_HCI */
++	RTW_PRINT_SEL(m, "MAX_RECVBUF_SZ: %d\n", MAX_RECVBUF_SZ);
++#endif /* !CONFIG_USB_HCI */
++
++	return 0;
++}
++#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
++
++#ifdef DBG_MEMORY_LEAK
++#include <asm/atomic.h>
++extern atomic_t _malloc_cnt;;
++extern atomic_t _malloc_size;;
++
++int proc_get_malloc_cnt(struct seq_file *m, void *v)
++{
++	RTW_PRINT_SEL(m, "_malloc_cnt=%d\n", atomic_read(&_malloc_cnt));
++	RTW_PRINT_SEL(m, "_malloc_size=%d\n", atomic_read(&_malloc_size));
++
++	return 0;
++}
++#endif /* DBG_MEMORY_LEAK */
++
++#ifdef CONFIG_FIND_BEST_CHANNEL
++int proc_get_best_channel(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0;
++
++	for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {
++		if (rfctl->channel_set[i].ChannelNum == 1)
++			index_24G = i;
++		if (rfctl->channel_set[i].ChannelNum == 36)
++			index_5G = i;
++	}
++
++	for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {
++		/* 2.4G */
++		if (rfctl->channel_set[i].ChannelNum == 6) {
++			if (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_24G].rx_count) {
++				index_24G = i;
++				best_channel_24G = rfctl->channel_set[i].ChannelNum;
++			}
++		}
++
++		/* 5G */
++		if (rfctl->channel_set[i].ChannelNum >= 36
++		    && rfctl->channel_set[i].ChannelNum < 140) {
++			/* Find primary channel */
++			if (((rfctl->channel_set[i].ChannelNum - 36) % 8 == 0)
++			    && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {
++				index_5G = i;
++				best_channel_5G = rfctl->channel_set[i].ChannelNum;
++			}
++		}
++
++		if (rfctl->channel_set[i].ChannelNum >= 149
++		    && rfctl->channel_set[i].ChannelNum < 165) {
++			/* find primary channel */
++			if (((rfctl->channel_set[i].ChannelNum - 149) % 8 == 0)
++			    && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {
++				index_5G = i;
++				best_channel_5G = rfctl->channel_set[i].ChannelNum;
++			}
++		}
++#if 1 /* debug */
++		RTW_PRINT_SEL(m, "The rx cnt of channel %3d = %d\n",
++			rfctl->channel_set[i].ChannelNum, rfctl->channel_set[i].rx_count);
++#endif
++	}
++
++	RTW_PRINT_SEL(m, "best_channel_5G = %d\n", best_channel_5G);
++	RTW_PRINT_SEL(m, "best_channel_24G = %d\n", best_channel_24G);
++
++	return 0;
++}
++
++ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	char tmp[32];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int i;
++		for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++)
++			rfctl->channel_set[i].rx_count = 0;
++
++		RTW_INFO("set %s\n", "Clean Best Channel Count");
++	}
++
++	return count;
++}
++#endif /* CONFIG_FIND_BEST_CHANNEL */
++
++#ifdef CONFIG_BT_COEXIST
++int proc_get_btcoex_dbg(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	PADAPTER padapter;
++	char buf[512] = {0};
++	padapter = (PADAPTER)rtw_netdev_priv(dev);
++
++	rtw_btcoex_GetDBG(padapter, buf, 512);
++
++	_RTW_PRINT_SEL(m, "%s", buf);
++
++	return 0;
++}
++
++ssize_t proc_set_btcoex_dbg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	PADAPTER padapter;
++	u8 tmp[80] = {0};
++	u32 module[2] = {0};
++	u32 num;
++
++	padapter = (PADAPTER)rtw_netdev_priv(dev);
++
++	/*	RTW_INFO("+" FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(padapter)); */
++
++	if (NULL == buffer) {
++		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n",
++			 FUNC_ADPT_ARG(padapter));
++
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n",
++			 FUNC_ADPT_ARG(padapter));
++
++		return -EFAULT;
++	}
++
++	num = count;
++	if (num > (sizeof(tmp) - 1))
++		num = (sizeof(tmp) - 1);
++
++	if (copy_from_user(tmp, buffer, num)) {
++		RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n",
++			 FUNC_ADPT_ARG(padapter));
++
++		return -EFAULT;
++	}
++
++	num = sscanf(tmp, "%x %x", module, module + 1);
++	if (1 == num) {
++		if (0 == module[0])
++			_rtw_memset(module, 0, sizeof(module));
++		else
++			_rtw_memset(module, 0xFF, sizeof(module));
++	} else if (2 != num) {
++		RTW_INFO(FUNC_ADPT_FMT ": input(\"%s\") format incorrect!\n",
++			 FUNC_ADPT_ARG(padapter), tmp);
++
++		if (0 == num)
++			return -EFAULT;
++	}
++
++	RTW_INFO(FUNC_ADPT_FMT ": input 0x%08X 0x%08X\n",
++		 FUNC_ADPT_ARG(padapter), module[0], module[1]);
++	rtw_btcoex_SetDBG(padapter, module);
++
++	return count;
++}
++
++int proc_get_btcoex_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	PADAPTER padapter;
++	const u32 bufsize = 40 * 100;
++	u8 *pbuf = NULL;
++
++	padapter = (PADAPTER)rtw_netdev_priv(dev);
++
++	pbuf = rtw_zmalloc(bufsize);
++	if (NULL == pbuf)
++		return -ENOMEM;
++
++	rtw_btcoex_DisplayBtCoexInfo(padapter, pbuf, bufsize);
++
++	_RTW_PRINT_SEL(m, "%s\n", pbuf);
++
++	rtw_mfree(pbuf, bufsize);
++
++	return 0;
++}
++
++#ifdef CONFIG_RF4CE_COEXIST
++int proc_get_rf4ce_state(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	u8 state = 0, voice = 0;
++
++	state = rtw_btcoex_GetRf4ceLinkState(adapter);
++
++	RTW_PRINT_SEL(m, "RF4CE %s\n", state?"Connected":"Disconnect");
++
++	return 0;
++}
++
++/* This interface is designed for user space application to inform RF4CE state
++ * Initial define for DHC 1295 E387 project
++ *
++ * echo state voice > rf4ce_state
++ * state
++ *	0: RF4CE disconnected
++ *	1: RF4CE connected
++ */
++ssize_t proc_set_rf4ce_state(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u8 state;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhx", &state);
++
++		if (num >= 1)
++			rtw_btcoex_SetRf4ceLinkState(adapter, state);
++	}
++
++	return count;
++}
++#endif /* CONFIG_RF4CE_COEXIST */
++#endif /* CONFIG_BT_COEXIST */
++
++#if defined(DBG_CONFIG_ERROR_DETECT)
++int proc_get_sreset(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *psdpriv = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++
++	if (psrtpriv->dbg_sreset_ctrl == _TRUE) {
++		RTW_PRINT_SEL(m, "self_dect_tx_cnt:%llu\n", psrtpriv->self_dect_tx_cnt);
++		RTW_PRINT_SEL(m, "self_dect_rx_cnt:%llu\n", psrtpriv->self_dect_rx_cnt);
++		RTW_PRINT_SEL(m, "self_dect_fw_cnt:%llu\n", psrtpriv->self_dect_fw_cnt);
++		RTW_PRINT_SEL(m, "tx_dma_status_cnt:%llu\n", psrtpriv->tx_dma_status_cnt);
++		RTW_PRINT_SEL(m, "rx_dma_status_cnt:%llu\n", psrtpriv->rx_dma_status_cnt);
++		RTW_PRINT_SEL(m, "self_dect_case:%d\n", psrtpriv->self_dect_case);
++		RTW_PRINT_SEL(m, "dbg_sreset_cnt:%d\n", pdbgpriv->dbg_sreset_cnt);
++	}
++	return 0;
++}
++
++ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++	char tmp[32];
++	s32 trigger_point;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d", &trigger_point);
++
++		if (num < 1)
++			return count;
++
++		if (trigger_point == SRESET_TGP_NULL)
++			rtw_hal_sreset_reset(padapter);
++		else if (trigger_point == SRESET_TGP_INFO)
++			psrtpriv->dbg_sreset_ctrl = _TRUE;
++		else
++			sreset_set_trigger_point(padapter, trigger_point);
++	}
++
++	return count;
++
++}
++#endif /* DBG_CONFIG_ERROR_DETECT */
++
++#ifdef CONFIG_PCI_HCI
++
++ssize_t proc_set_pci_bridge_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
++	struct pci_dev  *pdev = pdvobjpriv->ppcidev;
++	struct pci_dev  *bridge_pdev = pdev->bus->self;
++
++	char tmp[32] = { 0 };
++	int num;
++
++	u32 reg = 0, value = 0;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		num = sscanf(tmp, "%x %x", &reg, &value);
++		if (num != 2) {
++			RTW_INFO("invalid parameter!\n");
++			return count;
++		}
++
++		if (reg >= 0x1000) {
++			RTW_INFO("invalid register!\n");
++			return count;
++		}
++
++		if (value > 0xFF) {
++			RTW_INFO("invalid value! Only one byte\n");
++			return count;
++		}
++
++		RTW_INFO(FUNC_ADPT_FMT ": register 0x%x value 0x%x\n",
++			FUNC_ADPT_ARG(padapter), reg, value);
++
++		pci_write_config_byte(bridge_pdev, reg, value);
++	}
++	return count;
++}
++
++
++int proc_get_pci_bridge_conf_space(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
++	struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
++	struct pci_dev  *pdev = pdvobjpriv->ppcidev;
++	struct pci_dev  *bridge_pdev = pdev->bus->self;
++
++	u32 tmp[4] = { 0 };
++	u32 i, j;
++
++	RTW_PRINT_SEL(m, "\n*****  PCI Host Device Configuration Space*****\n\n");
++
++	for (i = 0; i < 0x1000; i += 0x10) {
++		for (j = 0 ; j < 4 ; j++)
++			pci_read_config_dword(bridge_pdev, i + j * 4, tmp+j);
++
++		RTW_PRINT_SEL(m, "%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
++			i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,
++			tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,
++			tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,
++			tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);
++	}
++	return 0;
++}
++
++
++ssize_t proc_set_pci_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
++	struct pci_dev  *pdev = pdvobjpriv->ppcidev;
++
++	char tmp[32] = { 0 };
++	int num;
++
++	u32 reg = 0, value = 0;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		num = sscanf(tmp, "%x %x", &reg, &value);
++
++		if (num != 2) {
++			RTW_INFO("invalid parameter!\n");
++			return count;
++		}
++
++
++		if (reg >= 0x1000) {
++			RTW_INFO("invalid register!\n");
++			return count;
++		}
++
++		if (value > 0xFF) {
++			RTW_INFO("invalid value! Only one byte\n");
++			return count;
++		}
++
++		RTW_INFO(FUNC_ADPT_FMT ": register 0x%x value 0x%x\n",
++			FUNC_ADPT_ARG(padapter), reg, value);
++
++		pci_write_config_byte(pdev, reg, value);
++
++
++	}
++	return count;
++}
++
++
++int proc_get_pci_conf_space(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
++	struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
++	struct pci_dev  *pdev = pdvobjpriv->ppcidev;
++	struct pci_dev  *bridge_pdev = pdev->bus->self;
++
++	u32 tmp[4] = { 0 };
++	u32 i, j;
++
++	RTW_PRINT_SEL(m, "\n*****  PCI Device Configuration Space *****\n\n");
++
++	for (i = 0; i < 0x1000; i += 0x10) {
++		for (j = 0 ; j < 4 ; j++)
++			pci_read_config_dword(pdev, i + j * 4, tmp+j);
++
++		RTW_PRINT_SEL(m, "%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
++			i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,
++			tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,
++			tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,
++			tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);
++	}
++
++	return 0;
++}
++
++
++int proc_get_pci_aspm(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
++	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct pci_priv	*pcipriv = &(pdvobjpriv->pcipriv);
++	u8 tmp8 = 0;
++	u16 tmp16 = 0;
++	u32 tmp32 = 0;
++	u8 l1_idle = 0;
++
++
++	RTW_PRINT_SEL(m, "***** ASPM Capability *****\n");
++
++	pci_read_config_dword(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCAP, &tmp32);
++
++	RTW_PRINT_SEL(m, "CLK REQ:	%s\n", (tmp32&PCI_EXP_LNKCAP_CLKPM) ? "Enable" : "Disable");
++	RTW_PRINT_SEL(m, "ASPM L0s:	%s\n", (tmp32&BIT10) ? "Enable" : "Disable");
++	RTW_PRINT_SEL(m, "ASPM L1:	%s\n", (tmp32&BIT11) ? "Enable" : "Disable");
++
++	tmp8 = rtw_hal_pci_l1off_capability(padapter);
++	RTW_PRINT_SEL(m, "ASPM L1OFF:	%s\n", tmp8 ? "Enable" : "Disable");
++
++	RTW_PRINT_SEL(m, "***** ASPM CTRL Reg *****\n");
++
++	pci_read_config_word(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCTL, &tmp16);
++
++	RTW_PRINT_SEL(m, "CLK REQ:	%s\n", (tmp16&PCI_EXP_LNKCTL_CLKREQ_EN) ? "Enable" : "Disable");
++	RTW_PRINT_SEL(m, "ASPM L0s:	%s\n", (tmp16&BIT0) ? "Enable" : "Disable");
++	RTW_PRINT_SEL(m, "ASPM L1:	%s\n", (tmp16&BIT1) ? "Enable" : "Disable");
++
++	tmp8 = rtw_hal_pci_l1off_nic_support(padapter);
++	RTW_PRINT_SEL(m, "ASPM L1OFF:	%s\n", tmp8 ? "Enable" : "Disable");
++
++	RTW_PRINT_SEL(m, "***** ASPM Backdoor *****\n");
++
++	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719);
++	RTW_PRINT_SEL(m, "CLK REQ:	%s\n", (tmp8 & BIT4) ? "Enable" : "Disable");
++
++	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f);
++	l1_idle = tmp8 & 0x38;
++	RTW_PRINT_SEL(m, "ASPM L0s:	%s\n", (tmp8&BIT7) ? "Enable" : "Disable");
++
++	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719);
++	RTW_PRINT_SEL(m, "ASPM L1:	%s\n", (tmp8 & BIT3) ? "Enable" : "Disable");
++
++	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x718);
++	RTW_PRINT_SEL(m, "ASPM L1OFF:	%s\n", (tmp8 & BIT5) ? "Enable" : "Disable");
++
++	RTW_PRINT_SEL(m, "********* MISC **********\n");
++	RTW_PRINT_SEL(m, "ASPM L1 Idel Time: 0x%x\n", l1_idle>>3);
++	RTW_PRINT_SEL(m, "*************************\n");
++
++#ifdef CONFIG_PCI_DYNAMIC_ASPM
++	RTW_PRINT_SEL(m, "Dynamic ASPM mode: %d (%s)\n", pcipriv->aspm_mode,
++		      pcipriv->aspm_mode == ASPM_MODE_PERF ? "Perf" :
++		      pcipriv->aspm_mode == ASPM_MODE_PS ? "PS" : "Und");
++#endif
++
++	return 0;
++}
++
++int proc_get_rx_ring(struct seq_file *m, void *v)
++{
++	_irqL irqL;
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
++	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++	struct recv_priv *precvpriv = &padapter->recvpriv;
++	struct rtw_rx_ring *rx_ring = &precvpriv->rx_ring[RX_MPDU_QUEUE];
++	int i, j;
++
++	RTW_PRINT_SEL(m, "rx ring (%p)\n", rx_ring);
++	RTW_PRINT_SEL(m, "  dma: 0x%08x\n", (int) rx_ring->dma);
++	RTW_PRINT_SEL(m, "  idx: %d\n", rx_ring->idx);
++
++	_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
++	for (i = 0; i < precvpriv->rxringcount; i++) {
++#ifdef CONFIG_TRX_BD_ARCH
++		struct rx_buf_desc *entry = &rx_ring->buf_desc[i];
++#else
++		struct recv_stat *entry = &rx_ring->desc[i];
++#endif
++		struct sk_buff *skb = rx_ring->rx_buf[i];
++
++		RTW_PRINT_SEL(m, "  desc[%03d]: %p, rx_buf[%03d]: 0x%08x\n",
++			i, entry, i, cpu_to_le32(*((dma_addr_t *)skb->cb)));
++
++		for (j = 0; j < sizeof(*entry) / 4; j++) {
++			if ((j % 4) == 0)
++				RTW_PRINT_SEL(m, "  0x%03x", j);
++
++			RTW_PRINT_SEL(m, " 0x%08x ", ((int *) entry)[j]);
++
++			if ((j % 4) == 3)
++				RTW_PRINT_SEL(m, "\n");
++		}
++	}
++	_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
++
++	return 0;
++}
++
++int proc_get_tx_ring(struct seq_file *m, void *v)
++{
++	_irqL irqL;
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
++	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	int i, j, k;
++
++	_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
++	for (i = 0; i < PCI_MAX_TX_QUEUE_COUNT; i++) {
++		struct rtw_tx_ring *tx_ring = &pxmitpriv->tx_ring[i];
++
++		RTW_PRINT_SEL(m, "tx ring[%d] (%p)\n", i, tx_ring);
++		RTW_PRINT_SEL(m, "  dma: 0x%08x\n", (int) tx_ring->dma);
++		RTW_PRINT_SEL(m, "  idx: %d\n", tx_ring->idx);
++		RTW_PRINT_SEL(m, "  entries: %d\n", tx_ring->entries);
++		/*		RTW_PRINT_SEL(m, "  queue: %d\n", tx_ring->queue); */
++		RTW_PRINT_SEL(m, "  qlen: %d\n", tx_ring->qlen);
++
++		for (j = 0; j < pxmitpriv->txringcount[i]; j++) {
++#ifdef CONFIG_TRX_BD_ARCH
++			struct tx_buf_desc *entry = &tx_ring->buf_desc[j];
++			RTW_PRINT_SEL(m, "  buf_desc[%03d]: %p\n", j, entry);
++#else
++			struct tx_desc *entry = &tx_ring->desc[j];
++			RTW_PRINT_SEL(m, "  desc[%03d]: %p\n", j, entry);
++#endif
++
++			for (k = 0; k < sizeof(*entry) / 4; k++) {
++				if ((k % 4) == 0)
++					RTW_PRINT_SEL(m, "  0x%03x", k);
++
++				RTW_PRINT_SEL(m, " 0x%08x ", ((int *) entry)[k]);
++
++				if ((k % 4) == 3)
++					RTW_PRINT_SEL(m, "\n");
++			}
++		}
++	}
++	_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
++
++	return 0;
++}
++
++#ifdef DBG_TXBD_DESC_DUMP
++int proc_get_tx_ring_ext(struct seq_file *m, void *v)
++{
++	_irqL irqL;
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
++	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	struct rtw_tx_desc_backup *pbuf;
++	int i, j, k, idx;
++
++	RTW_PRINT_SEL(m, "<<<< tx ring ext dump settings >>>>\n");
++	RTW_PRINT_SEL(m, " - backup frame num: %d\n", TX_BAK_FRMAE_CNT);
++	RTW_PRINT_SEL(m, " - backup max. desc size: %d bytes\n", TX_BAK_DESC_LEN);
++	RTW_PRINT_SEL(m, " - backup data size: %d bytes\n\n", TX_BAK_DATA_LEN);
++
++	if (!pxmitpriv->dump_txbd_desc) {
++		RTW_PRINT_SEL(m, "Dump function is disabled.\n");
++		return 0;
++	}
++
++	_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
++	for (i = 0; i < HW_QUEUE_ENTRY; i++) {
++		struct rtw_tx_ring *tx_ring = &pxmitpriv->tx_ring[i];
++
++		idx = rtw_get_tx_desc_backup(padapter, i, &pbuf);
++
++		RTW_PRINT_SEL(m, "Tx ring[%d]", i);
++		switch (i) {
++		case 0:
++			RTW_PRINT_SEL(m, " (VO)\n");
++			break;
++		case 1:
++			RTW_PRINT_SEL(m, " (VI)\n");
++			break;
++		case 2:
++			RTW_PRINT_SEL(m, " (BE)\n");
++			break;
++		case 3:
++			RTW_PRINT_SEL(m, " (BK)\n");
++			break;
++		case 4:
++			RTW_PRINT_SEL(m, " (BCN)\n");
++			break;
++		case 5:
++			RTW_PRINT_SEL(m, " (MGT)\n");
++			break;
++		case 6:
++			RTW_PRINT_SEL(m, " (HIGH)\n");
++			break;
++		case 7:
++			RTW_PRINT_SEL(m, " (TXCMD)\n");
++			break;
++		default:
++			RTW_PRINT_SEL(m, " (?)\n");
++			break;
++		}
++
++		RTW_PRINT_SEL(m, "  Entries: %d\n", TX_BAK_FRMAE_CNT);
++		RTW_PRINT_SEL(m, "  Last idx: %d\n", idx);
++
++		for (j = 0; j < TX_BAK_FRMAE_CNT; j++) {
++			RTW_PRINT_SEL(m, "  desc[%03d]:\n", j);
++
++			for (k = 0; k < (pbuf->tx_desc_size) / 4; k++) {
++				if ((k % 4) == 0)
++					RTW_PRINT_SEL(m, "  0x%03x", k);
++
++				RTW_PRINT_SEL(m, " 0x%08x ", ((int *)pbuf->tx_bak_desc)[k]);
++
++				if ((k % 4) == 3)
++					RTW_PRINT_SEL(m, "\n");
++			}
++
++#if 1 /* data dump */
++			if (pbuf->tx_desc_size) {
++				RTW_PRINT_SEL(m, "  data[%03d]:\n", j);
++
++				for (k = 0; k < (TX_BAK_DATA_LEN) / 4; k++) {
++					if ((k % 4) == 0)
++						RTW_PRINT_SEL(m, "  0x%03x", k);
++
++					RTW_PRINT_SEL(m, " 0x%08x ", ((int *)pbuf->tx_bak_data_hdr)[k]);
++
++					if ((k % 4) == 3)
++						RTW_PRINT_SEL(m, "\n");
++				}
++				RTW_PRINT_SEL(m, "\n");
++			}
++#endif
++
++			RTW_PRINT_SEL(m, "  R/W pointer: %d/%d\n", pbuf->tx_bak_rp, pbuf->tx_bak_wp);
++
++			pbuf = pbuf + 1;
++		}
++		RTW_PRINT_SEL(m, "\n");
++	}
++	_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
++
++	return 0;
++}
++
++ssize_t proc_set_tx_ring_ext(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	_irqL irqL;
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++	char tmp[32];
++	u32 reset = 0;
++	u32 dump = 0;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%u %u", &dump, &reset);
++
++		if (num != 2) {
++			RTW_INFO("invalid parameter!\n");
++			return count;
++		}
++
++		_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
++		pxmitpriv->dump_txbd_desc = (BOOLEAN) dump;
++
++		if (reset == 1)
++			rtw_tx_desc_backup_reset();
++
++		_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
++
++	}
++
++	return count;
++}
++
++#endif
++
++#endif
++
++#ifdef CONFIG_WOWLAN
++int proc_get_wow_enable(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv *registry_pair = &padapter->registrypriv;
++
++	RTW_PRINT_SEL(m, "wow - %s\n", (registry_pair->wowlan_enable)? "enable" : "disable");
++	return 0;
++}
++
++ssize_t proc_set_wow_enable(struct file *file, const char __user *buffer,
++			    size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv *registry_pair = &padapter->registrypriv;
++	char tmp[8];
++	int num = 0;
++	int mode = 0;
++
++	if (count < 1) 
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) 
++		num = sscanf(tmp, "%d", &mode);
++	else 
++		return -EFAULT;
++
++	if (num != 1) {
++		RTW_ERR("%s: %s - invalid parameter!\n", __func__, tmp);
++		return -EINVAL;
++	}
++
++	if (mode == 1) {
++		RTW_PRINT("%s: wowlan - enable\n", __func__);
++	} else if (mode == 0) {
++		RTW_PRINT("%s: wowlan - disable\n", __func__);
++	} else {
++		RTW_ERR("%s: %s - invalid parameter!, mode=%d\n",
++			__func__, tmp, mode);
++		return -EINVAL;
++	}
++
++	registry_pair->wowlan_enable = mode;
++
++	return count;
++}
++
++int proc_get_pattern_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	u8 val8;
++	char str_1[128];
++	char *p_str;
++	int i = 0 , j = 0, k = 0;
++	int len = 0, max_len = 0, total = 0;
++
++	p_str = str_1;
++	max_len = sizeof(str_1);
++
++	total = pwrpriv->wowlan_pattern_idx;
++
++	rtw_set_default_pattern(padapter);
++
++	/*show pattern*/
++	RTW_PRINT_SEL(m, "\n======[Pattern Info.]======\n");
++	RTW_PRINT_SEL(m, "pattern number: %d\n", total);
++	RTW_PRINT_SEL(m, "support default patterns: %c\n",
++		      (pwrpriv->default_patterns_en) ? 'Y' : 'N');
++
++	for (k = 0; k < total ; k++) {
++		RTW_PRINT_SEL(m, "\npattern idx: %d\n", k);
++		RTW_PRINT_SEL(m, "pattern content:\n");
++
++		p_str = str_1;
++		max_len = sizeof(str_1);
++		for (i = 0 ; i < MAX_WKFM_PATTERN_SIZE / 8 ; i++) {
++			_rtw_memset(p_str, 0, max_len);
++			len = 0;
++			for (j = 0 ; j < 8 ; j++) {
++				val8 = pwrpriv->patterns[k].content[i * 8 + j];
++				len += snprintf(p_str + len, max_len - len,
++						"%02x ", val8);
++			}
++			RTW_PRINT_SEL(m, "%s\n", p_str);
++		}
++		RTW_PRINT_SEL(m, "\npattern mask:\n");
++		for (i = 0 ; i < MAX_WKFM_SIZE / 8 ; i++) {
++			_rtw_memset(p_str, 0, max_len);
++			len = 0;
++			for (j = 0 ; j < 8 ; j++) {
++				val8 = pwrpriv->patterns[k].mask[i * 8 + j];
++				len += snprintf(p_str + len, max_len - len,
++						"%02x ", val8);
++			}
++			RTW_PRINT_SEL(m, "%s\n", p_str);
++		}
++
++		RTW_PRINT_SEL(m, "\npriv_pattern_len:\n");
++		RTW_PRINT_SEL(m, "pattern_len: %d\n", pwrpriv->patterns[k].len);
++		RTW_PRINT_SEL(m, "*****************\n");
++	}
++
++	return 0;
++}
++
++ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer,
++			      size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct wowlan_ioctl_param poidparam;
++	u8 tmp[MAX_WKFM_PATTERN_STR_LEN + 1] = {0};
++	int ret = 0;
++	u8 index = 0;
++
++	poidparam.subcode = 0;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count >= sizeof(tmp)) {
++		RTW_ERR("%s: pattern string is too long, count=%zu\n",
++			__func__, count);
++		return -EFAULT;
++	}
++
++	if (pwrpriv->wowlan_pattern_idx >= MAX_WKFM_CAM_NUM) {
++		RTW_ERR("priv-pattern is full(idx: %d)\n",
++			 pwrpriv->wowlan_pattern_idx);
++		RTW_ERR("please clean priv-pattern first\n");
++		return -ENOMEM;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		if (strncmp(tmp, "clean", 5) == 0) {
++			poidparam.subcode = WOWLAN_PATTERN_CLEAN;
++			rtw_hal_set_hwreg(padapter,
++					  HW_VAR_WOWLAN, (u8 *)&poidparam);
++		} else {
++			index = pwrpriv->wowlan_pattern_idx;
++			ret = rtw_wowlan_parser_pattern_cmd(tmp,
++					    pwrpriv->patterns[index].content,
++					    &pwrpriv->patterns[index].len,
++					    pwrpriv->patterns[index].mask);
++			if (ret == _TRUE)
++				pwrpriv->wowlan_pattern_idx++;
++		}
++	} else {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	return count;
++}
++
++int proc_get_wakeup_event(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv  *registry_par = &padapter->registrypriv;
++
++	RTW_PRINT_SEL(m, "wakeup event: %#02x\n", registry_par->wakeup_event);
++	return 0;
++}
++
++ssize_t proc_set_wakeup_event(struct file *file, const char __user *buffer,
++			      size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++	struct registry_priv  *registry_par = &padapter->registrypriv;
++	u32 wakeup_event = 0;
++
++	u8 tmp[8] = {0};
++	int num = 0;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count))
++		num = sscanf(tmp, "%u", &wakeup_event);
++	else
++		return -EFAULT;
++
++	if (num == 1 && wakeup_event <= 0x07) {
++		registry_par->wakeup_event = wakeup_event;
++
++		if (wakeup_event & BIT(1))
++			pwrctrlpriv->default_patterns_en = _TRUE;
++		else
++			pwrctrlpriv->default_patterns_en = _FALSE;
++
++		rtw_wow_pattern_sw_reset(padapter);
++
++		RTW_INFO("%s: wakeup_event: %#2x, default pattern: %d\n",
++			 __func__, registry_par->wakeup_event,
++			 pwrctrlpriv->default_patterns_en);
++	} else {
++		return -EINVAL;
++	}
++
++	return count;
++}
++
++int proc_get_wakeup_reason(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	u8 val = pwrpriv->wowlan_last_wake_reason;
++
++	RTW_PRINT_SEL(m, "last wake reason: %#02x\n", val);
++	return 0;
++}
++#endif /*CONFIG_WOWLAN*/
++
++#ifdef CONFIG_GPIO_WAKEUP
++int proc_get_wowlan_gpio_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	u8 gpio_index = pwrpriv->wowlan_gpio_index;
++	u8 gpio_output_state = pwrpriv->wowlan_gpio_output_state;
++	u8 val = pwrpriv->is_high_active;
++
++	RTW_PRINT_SEL(m, "wakeup_gpio_idx: %d\n", gpio_index);
++#if (!defined(CONFIG_WAKEUP_GPIO_INPUT_MODE) && !defined(CONFIG_RTW_ONE_PIN_GPIO))
++	RTW_PRINT_SEL(m, "current_gpio_output_state: %d\n", gpio_output_state);
++#endif
++	RTW_PRINT_SEL(m, "high_active: %d\n", val);
++
++	return 0;
++}
++
++ssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer,
++				  size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	char tmp[32] = {0};
++	int num = 0;
++	u32 is_high_active = 0;
++	u8 val8 = 0;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		num = sscanf(tmp, "%u", &is_high_active);
++
++		if (num != 1) {
++			RTW_INFO("Invalid format\n");
++			return count;
++		}
++
++		is_high_active = is_high_active == 0 ? 0 : 1;
++
++		pwrpriv->is_high_active = is_high_active;
++
++		rtw_ps_deny(padapter, PS_DENY_IOCTL);
++		LeaveAllPowerSaveModeDirect(padapter);
++
++#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
++		if (pwrpriv->is_high_active == 0)
++			rtw_hal_set_input_gpio(padapter, pwrpriv->wowlan_gpio_index);
++		else
++			rtw_hal_set_output_gpio(padapter, pwrpriv->wowlan_gpio_index,
++				GPIO_OUTPUT_LOW);
++#else
++		val8 = (pwrpriv->is_high_active == 0) ? 1 : 0;
++		rtw_hal_switch_gpio_wl_ctrl(padapter, pwrpriv->wowlan_gpio_index, _TRUE);
++		rtw_hal_set_output_gpio(padapter, pwrpriv->wowlan_gpio_index, val8);
++#endif
++		rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
++
++		RTW_INFO("%s set GPIO_%d to %s_ACTIVE\n", __func__,
++			pwrpriv->wowlan_gpio_index,
++			pwrpriv->is_high_active ? "HIGH" : "LOW");
++	}
++
++	return count;
++}
++#endif /* CONFIG_GPIO_WAKEUP */
++
++#ifdef CONFIG_P2P_WOWLAN
++int proc_get_p2p_wowlan_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++	struct p2p_wowlan_info	 peerinfo = pwdinfo->p2p_wow_info;
++	if (_TRUE == peerinfo.is_trigger) {
++		RTW_PRINT_SEL(m, "is_trigger: TRUE\n");
++		switch (peerinfo.wowlan_recv_frame_type) {
++		case P2P_WOWLAN_RECV_NEGO_REQ:
++			RTW_PRINT_SEL(m, "Frame Type: Nego Request\n");
++			break;
++		case P2P_WOWLAN_RECV_INVITE_REQ:
++			RTW_PRINT_SEL(m, "Frame Type: Invitation Request\n");
++			break;
++		case P2P_WOWLAN_RECV_PROVISION_REQ:
++			RTW_PRINT_SEL(m, "Frame Type: Provision Request\n");
++			break;
++		default:
++			break;
++		}
++		RTW_PRINT_SEL(m, "Peer Addr: "MAC_FMT"\n", MAC_ARG(peerinfo.wowlan_peer_addr));
++		RTW_PRINT_SEL(m, "Peer WPS Config: %x\n", peerinfo.wowlan_peer_wpsconfig);
++		RTW_PRINT_SEL(m, "Persistent Group: %d\n", peerinfo.wowlan_peer_is_persistent);
++		RTW_PRINT_SEL(m, "Intivation Type: %d\n", peerinfo.wowlan_peer_invitation_type);
++	} else
++		RTW_PRINT_SEL(m, "is_trigger: False\n");
++	return 0;
++}
++#endif /* CONFIG_P2P_WOWLAN */
++#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
++int proc_get_new_bcn_max(struct seq_file *m, void *v)
++{
++	extern int new_bcn_max;
++
++	RTW_PRINT_SEL(m, "%d", new_bcn_max);
++	return 0;
++}
++
++ssize_t proc_set_new_bcn_max(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	char tmp[32];
++	extern int new_bcn_max;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count))
++		sscanf(tmp, "%d ", &new_bcn_max);
++
++	return count;
++}
++#endif
++#ifdef CONFIG_POWER_SAVING
++int proc_get_ps_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	u8 ips_mode = pwrpriv->ips_mode_req;
++	u8 lps_mode = pwrpriv->power_mgnt;
++	u8 lps_level = pwrpriv->lps_level;
++#ifdef CONFIG_LPS_1T1R
++	u8 lps_1t1r = pwrpriv->lps_1t1r;
++#endif
++#ifdef CONFIG_WOWLAN
++	u8 wow_lps_mode = pwrpriv->wowlan_power_mgmt;
++	u8 wow_lps_level = pwrpriv->wowlan_lps_level;
++	#ifdef CONFIG_LPS_1T1R
++	u8 wow_lps_1t1r = pwrpriv->wowlan_lps_1t1r;
++	#endif
++#endif /* CONFIG_WOWLAN */
++	char *str = "";
++
++	RTW_PRINT_SEL(m, "======Power Saving Info:======\n");
++	RTW_PRINT_SEL(m, "*IPS:\n");
++
++	if (ips_mode == IPS_NORMAL) {
++#ifdef CONFIG_FWLPS_IN_IPS
++		str = "FW_LPS_IN_IPS";
++#else
++		str = "Card Disable";
++#endif
++	} else if (ips_mode == IPS_NONE)
++		str = "NO IPS";
++	else if (ips_mode == IPS_LEVEL_2)
++		str = "IPS_LEVEL_2";
++	else
++		str = "invalid ips_mode";
++
++	RTW_PRINT_SEL(m, " IPS mode: %s\n", str);
++	RTW_PRINT_SEL(m, " IPS enter count:%d, IPS leave count:%d\n",
++		      pwrpriv->ips_enter_cnts, pwrpriv->ips_leave_cnts);
++	RTW_PRINT_SEL(m, "------------------------------\n");
++	RTW_PRINT_SEL(m, "*LPS:\n");
++
++	if (lps_mode == PS_MODE_ACTIVE)
++		str = "NO LPS";
++	else if (lps_mode == PS_MODE_MIN)
++		str = "MIN";
++	else if (lps_mode == PS_MODE_MAX)
++		str = "MAX";
++	else if (lps_mode == PS_MODE_DTIM)
++		str = "DTIM";
++	else
++		sprintf(str, "%d", lps_mode);
++
++	RTW_PRINT_SEL(m, " LPS mode: %s\n", str);
++
++	if (pwrpriv->dtim != 0)
++		RTW_PRINT_SEL(m, " DTIM: %d\n", pwrpriv->dtim);
++	RTW_PRINT_SEL(m, " LPS enter count:%d, LPS leave count:%d\n",
++		      pwrpriv->lps_enter_cnts, pwrpriv->lps_leave_cnts);
++
++	if (lps_level == LPS_LCLK)
++		str = "LPS_LCLK";
++	else if  (lps_level == LPS_PG)
++		str = "LPS_PG";
++	else
++		str = "LPS_NORMAL";
++	RTW_PRINT_SEL(m, " LPS level: %s\n", str);
++
++#ifdef CONFIG_LPS_1T1R
++	RTW_PRINT_SEL(m, " LPS 1T1R: %d\n", lps_1t1r);
++#endif
++
++#ifdef CONFIG_WOWLAN
++	RTW_PRINT_SEL(m, "------------------------------\n");
++	RTW_PRINT_SEL(m, "*WOW LPS:\n");
++
++	if (wow_lps_mode == PS_MODE_ACTIVE)
++		str = "NO LPS";
++	else if (wow_lps_mode == PS_MODE_MIN)
++		str = "MIN";
++	else if (wow_lps_mode == PS_MODE_MAX)
++		str = "MAX";
++	else if (wow_lps_mode == PS_MODE_DTIM)
++		str = "DTIM";
++	else
++		sprintf(str, "%d", wow_lps_mode);
++
++	RTW_PRINT_SEL(m, " WOW LPS mode: %s\n", str);
++
++	if (wow_lps_level == LPS_LCLK)
++		str = "LPS_LCLK";
++	else if  (wow_lps_level == LPS_PG)
++		str = "LPS_PG";
++	else
++		str = "LPS_NORMAL";
++	RTW_PRINT_SEL(m, " WOW LPS level: %s\n", str);
++
++	#ifdef CONFIG_LPS_1T1R
++	RTW_PRINT_SEL(m, " WOW LPS 1T1R: %d\n", wow_lps_1t1r);
++	#endif
++#endif /* CONFIG_WOWLAN */
++
++	RTW_PRINT_SEL(m, "=============================\n");
++	return 0;
++}
++
++ssize_t proc_set_ps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	struct _ADAPTER *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[8];
++	int num = 0;
++	int mode = 0;
++	int en = 0;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (!buffer || copy_from_user(tmp, buffer, count))
++		goto exit;
++
++	num = sscanf(tmp, "%d %d", &mode, &en);
++	if (num >  2) {
++		RTW_ERR("%s: invalid parameter!\n", __FUNCTION__);
++		goto exit;
++	}
++
++	if (num == 1 && mode == 0) {
++		/* back to original LPS/IPS Mode */
++		RTW_INFO("%s: back to original LPS/IPS Mode\n", __FUNCTION__);
++
++		rtw_pm_set_lps(adapter, adapter->registrypriv.power_mgnt);
++		
++		rtw_pm_set_ips(adapter, adapter->registrypriv.ips_mode);
++
++#ifdef CONFIG_WOWLAN
++		RTW_INFO("%s: back to original WOW LPS Mode\n", __FUNCTION__);
++
++		rtw_pm_set_wow_lps(adapter, adapter->registrypriv.wow_power_mgnt);
++#endif /* CONFIG_WOWLAN */
++
++		goto exit;
++	}
++	
++	if (mode == 1) { 
++		/* LPS */
++		RTW_INFO("%s: LPS: %s, en=%d\n", __FUNCTION__, (en == 0) ? "disable":"enable", en);	
++		if (rtw_pm_set_lps(adapter, en) != 0 )
++			RTW_ERR("%s: invalid parameter, mode=%d, level=%d\n", __FUNCTION__, mode, en);
++		
++	} else if (mode == 2) {
++		/* IPS */
++		RTW_INFO("%s: IPS: %s, en=%d\n", __FUNCTION__, (en == 0) ? "disable":"enable", en);	
++		if (rtw_pm_set_ips(adapter, en) != 0 )
++			RTW_ERR("%s: invalid parameter, mode=%d, level=%d\n", __FUNCTION__, mode, en);
++	}
++#ifdef CONFIG_WOWLAN
++	else if (mode == 3) {
++		/* WOW LPS */
++		RTW_INFO("%s: WOW LPS: %s, en=%d\n", __FUNCTION__, (en == 0) ? "disable":"enable", en);
++		if (rtw_pm_set_wow_lps(adapter, en) != 0 )
++			RTW_ERR("%s: invalid parameter, mode=%d, level=%d\n", __FUNCTION__, mode, en);
++	}
++#endif /* CONFIG_WOWLAN */
++	else
++		RTW_ERR("%s: invalid parameter, mode = %d!\n", __FUNCTION__, mode);
++
++exit:
++	return count;
++}
++
++#ifdef CONFIG_WMMPS_STA
++int proc_get_wmmps_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++	char *uapsd_max_sp_str="";
++
++	if (pregpriv){
++		switch(pregpriv->uapsd_max_sp_len) {
++			case 0:
++				uapsd_max_sp_str = "NO_LIMIT";
++				break;
++			case 1:
++				uapsd_max_sp_str = "TWO_MSDU";
++				break;
++			case 2:
++				uapsd_max_sp_str = "FOUR_MSDU";
++				break;
++			case 3:
++				uapsd_max_sp_str = "SIX_MSDU";
++				break;
++			default:
++				uapsd_max_sp_str = "UNSPECIFIED";
++				break;
++		}
++
++		RTW_PRINT_SEL(m, "====== WMMPS_STA Info:======\n");
++		RTW_PRINT_SEL(m, "uapsd_max_sp_len=0x%02x (%s)\n", pregpriv->uapsd_max_sp_len, uapsd_max_sp_str);
++		RTW_PRINT_SEL(m, "uapsd_ac_enable=0x%02x\n", pregpriv->uapsd_ac_enable);
++		RTW_PRINT_SEL(m, "BIT0 - AC_VO UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VO) ? "Enabled" : "Disabled");
++		RTW_PRINT_SEL(m, "BIT1 - AC_VI UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VI) ? "Enabled" : "Disabled");
++		RTW_PRINT_SEL(m, "BIT2 - AC_BK UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BK) ? "Enabled" : "Disabled");
++		RTW_PRINT_SEL(m, "BIT3 - AC_BE UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BE) ? "Enabled" : "Disabled");
++		RTW_PRINT_SEL(m, "============================\n");
++	}
++
++	return 0;
++}
++
++ssize_t proc_set_wmmps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++	char tmp[32];
++	u8 uapsd_ac_setting;
++	u8 uapsd_max_sp_len_setting;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhu %hhx", &uapsd_max_sp_len_setting, &uapsd_ac_setting);
++
++		if (pregpriv) {
++			if (num >= 1) {
++				pregpriv->uapsd_max_sp_len = uapsd_max_sp_len_setting;
++				RTW_INFO("uapsd_max_sp_len = %d\n", pregpriv->uapsd_max_sp_len);
++			}
++
++			if (num >= 2) {
++				pregpriv->uapsd_ac_enable = uapsd_ac_setting;
++				RTW_INFO("uapsd_ac_enable = 0x%02x\n", pregpriv->uapsd_ac_enable);
++			}
++		}
++	}
++
++	return count;
++}
++#endif /* CONFIG_WMMPS_STA */
++#endif /* CONFIG_POWER_SAVING */
++
++#ifdef CONFIG_TDLS
++int proc_get_tdls_enable(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv *pregpriv = &padapter->registrypriv;
++
++	if (pregpriv)
++		RTW_PRINT_SEL(m, "TDLS is %s !\n", (rtw_is_tdls_enabled(padapter) == _TRUE) ? "enabled" : "disabled");
++
++	return 0;
++}
++
++ssize_t proc_set_tdls_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++	char tmp[32];
++	u32 en_tdls = 0;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d ", &en_tdls);
++
++		if (num == 1 && pregpriv) {
++			if (en_tdls > 0)
++				rtw_enable_tdls_func(padapter);
++			else
++				rtw_disable_tdls_func(padapter, _TRUE);
++		}
++	}
++
++	return count;
++}
++
++static int proc_tdls_display_tdls_function_info(struct seq_file *m)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++	u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE;
++	u8 SpaceBtwnItemAndValueTmp = 0;
++	BOOLEAN FirstMatchFound = _FALSE;
++	int j = 0;
++
++	RTW_PRINT_SEL(m, "============[TDLS Function Info]============\n");
++	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Enable", (rtw_is_tdls_enabled(padapter) == _TRUE) ? "_TRUE" : "_FALSE");
++	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Driver Setup", (ptdlsinfo->driver_setup == _TRUE) ? "_TRUE" : "_FALSE");
++	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Prohibited", (ptdlsinfo->ap_prohibited == _TRUE) ? "_TRUE" : "_FALSE");
++	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Channel Switch Prohibited", (ptdlsinfo->ch_switch_prohibited == _TRUE) ? "_TRUE" : "_FALSE");
++	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Link Established", (ptdlsinfo->link_established == _TRUE) ? "_TRUE" : "_FALSE");
++	RTW_PRINT_SEL(m, "%-*s = %d/%d\n", SpaceBtwnItemAndValue, "TDLS STA Num (Linked/Allowed)", ptdlsinfo->sta_cnt, MAX_ALLOWED_TDLS_STA_NUM);
++	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Allowed STA Num Reached", (ptdlsinfo->sta_maximum == _TRUE) ? "_TRUE" : "_FALSE");
++
++#ifdef CONFIG_TDLS_CH_SW
++	RTW_PRINT_SEL(m, "%-*s =", SpaceBtwnItemAndValue, "TDLS CH SW State");
++	if (ptdlsinfo->chsw_info.ch_sw_state == TDLS_STATE_NONE)
++		RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_STATE_NONE");
++	else {
++		for (j = 0; j < 32; j++) {
++			if (ptdlsinfo->chsw_info.ch_sw_state & BIT(j)) {
++				if (FirstMatchFound ==  _FALSE) {
++					SpaceBtwnItemAndValueTmp = 1;
++					FirstMatchFound = _TRUE;
++				} else
++					SpaceBtwnItemAndValueTmp = SpaceBtwnItemAndValue + 3;
++				switch (BIT(j)) {
++				case TDLS_INITIATOR_STATE:
++					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_INITIATOR_STATE");
++					break;
++				case TDLS_RESPONDER_STATE:
++					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_RESPONDER_STATE");
++					break;
++				case TDLS_LINKED_STATE:
++					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_LINKED_STATE");
++					break;
++				case TDLS_WAIT_PTR_STATE:
++					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_WAIT_PTR_STATE");
++					break;
++				case TDLS_ALIVE_STATE:
++					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_ALIVE_STATE");
++					break;
++				case TDLS_CH_SWITCH_ON_STATE:
++					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SWITCH_ON_STATE");
++					break;
++				case TDLS_PEER_AT_OFF_STATE:
++					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_PEER_AT_OFF_STATE");
++					break;
++				case TDLS_CH_SW_INITIATOR_STATE:
++					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SW_INITIATOR_STATE");
++					break;
++				case TDLS_WAIT_CH_RSP_STATE:
++					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValue, " ", "TDLS_WAIT_CH_RSP_STATE");
++					break;
++				default:
++					RTW_PRINT_SEL(m, "%-*sBIT(%d)\n", SpaceBtwnItemAndValueTmp, " ", j);
++					break;
++				}
++			}
++		}
++	}
++
++	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS CH SW On", (ATOMIC_READ(&ptdlsinfo->chsw_info.chsw_on) == _TRUE) ? "_TRUE" : "_FALSE");
++	RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Off-Channel Num", ptdlsinfo->chsw_info.off_ch_num);
++	RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Channel Offset", ptdlsinfo->chsw_info.ch_offset);
++	RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Current Time", ptdlsinfo->chsw_info.cur_time);
++	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS CH SW Delay Switch Back", (ptdlsinfo->chsw_info.delay_switch_back == _TRUE) ? "_TRUE" : "_FALSE");
++	RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Dump Back", ptdlsinfo->chsw_info.dump_stack);
++#endif
++
++	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Device Discovered", (ptdlsinfo->dev_discovered == _TRUE) ? "_TRUE" : "_FALSE");
++
++	return 0;
++}
++
++static int proc_tdls_display_network_info(struct seq_file *m)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
++	int i = 0;
++	u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE;
++
++	/* Display the linked AP/GO info */
++	RTW_PRINT_SEL(m, "============[Associated AP/GO Info]============\n");
++
++	if ((pmlmepriv->fw_state & WIFI_STATION_STATE) && (pmlmepriv->fw_state & WIFI_ASOC_STATE)) {
++		RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "BSSID", cur_network->network.Ssid.Ssid);
++		RTW_PRINT_SEL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(cur_network->network.MacAddress));
++
++		RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Wireless Mode");
++		for (i = 0; i < 8; i++) {
++			if (pmlmeext->cur_wireless_mode & BIT(i)) {
++				switch (BIT(i)) {
++				case WIRELESS_11B:
++					RTW_PRINT_SEL(m, "%4s", "11B ");
++					break;
++				case WIRELESS_11G:
++					RTW_PRINT_SEL(m, "%4s", "11G ");
++					break;
++				case WIRELESS_11A:
++					RTW_PRINT_SEL(m, "%4s", "11A ");
++					break;
++				case WIRELESS_11_24N:
++					RTW_PRINT_SEL(m, "%7s", "11_24N ");
++					break;
++				case WIRELESS_11_5N:
++					RTW_PRINT_SEL(m, "%6s", "11_5N ");
++					break;
++				case WIRELESS_AUTO:
++					RTW_PRINT_SEL(m, "%5s", "AUTO ");
++					break;
++				case WIRELESS_11AC:
++					RTW_PRINT_SEL(m, "%5s", "11AC ");
++					break;
++				}
++			}
++		}
++		RTW_PRINT_SEL(m, "\n");
++
++		RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Privacy");
++		switch (padapter->securitypriv.dot11PrivacyAlgrthm) {
++		case _NO_PRIVACY_:
++			RTW_PRINT_SEL(m, "%s\n", "NO PRIVACY");
++			break;
++		case _WEP40_:
++			RTW_PRINT_SEL(m, "%s\n", "WEP 40");
++			break;
++		case _TKIP_:
++			RTW_PRINT_SEL(m, "%s\n", "TKIP");
++			break;
++		case _TKIP_WTMIC_:
++			RTW_PRINT_SEL(m, "%s\n", "TKIP WTMIC");
++			break;
++		case _AES_:
++			RTW_PRINT_SEL(m, "%s\n", "AES");
++			break;
++		case _WEP104_:
++			RTW_PRINT_SEL(m, "%s\n", "WEP 104");
++			break;
++#if 0 /* no this setting */
++		case _WEP_WPA_MIXED_:
++			RTW_PRINT_SEL(m, "%s\n", "WEP/WPA Mixed");
++			break;
++#endif
++		case _SMS4_:
++			RTW_PRINT_SEL(m, "%s\n", "SMS4");
++			break;
++#ifdef CONFIG_IEEE80211W
++		case _BIP_CMAC_128_:
++			RTW_PRINT_SEL(m, "%s\n", "BIP");
++			break;
++#endif /* CONFIG_IEEE80211W */
++		}
++
++		RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "Channel", pmlmeext->cur_channel);
++		RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Channel Offset");
++		switch (pmlmeext->cur_ch_offset) {
++		case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
++			RTW_PRINT_SEL(m, "%s\n", "N/A");
++			break;
++		case HAL_PRIME_CHNL_OFFSET_LOWER:
++			RTW_PRINT_SEL(m, "%s\n", "Lower");
++			break;
++		case HAL_PRIME_CHNL_OFFSET_UPPER:
++			RTW_PRINT_SEL(m, "%s\n", "Upper");
++			break;
++		}
++
++		RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Bandwidth Mode");
++		switch (pmlmeext->cur_bwmode) {
++		case CHANNEL_WIDTH_20:
++			RTW_PRINT_SEL(m, "%s\n", "20MHz");
++			break;
++		case CHANNEL_WIDTH_40:
++			RTW_PRINT_SEL(m, "%s\n", "40MHz");
++			break;
++		case CHANNEL_WIDTH_80:
++			RTW_PRINT_SEL(m, "%s\n", "80MHz");
++			break;
++		case CHANNEL_WIDTH_160:
++			RTW_PRINT_SEL(m, "%s\n", "160MHz");
++			break;
++		case CHANNEL_WIDTH_80_80:
++			RTW_PRINT_SEL(m, "%s\n", "80MHz + 80MHz");
++			break;
++		}
++	} else
++		RTW_PRINT_SEL(m, "No association with AP/GO exists!\n");
++
++	return 0;
++}
++
++static int proc_tdls_display_tdls_sta_info(struct seq_file *m)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++	struct sta_info *psta;
++	int i = 0, j = 0;
++	_irqL irqL;
++	_list	*plist, *phead;
++	u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE;
++	u8 SpaceBtwnItemAndValueTmp = 0;
++	u8 NumOfTdlsStaToShow = 0;
++	BOOLEAN FirstMatchFound = _FALSE;
++
++	/* Search for TDLS sta info to display */
++	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++	for (i = 0; i < NUM_STA; i++) {
++		phead = &(pstapriv->sta_hash[i]);
++		plist = get_next(phead);
++		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++			plist = get_next(plist);
++			if (psta->tdls_sta_state != TDLS_STATE_NONE) {
++				/* We got one TDLS sta info to show */
++				RTW_PRINT_SEL(m, "============[TDLS Peer STA Info: STA %d]============\n", ++NumOfTdlsStaToShow);
++				RTW_PRINT_SEL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(psta->cmn.mac_addr));
++				RTW_PRINT_SEL(m, "%-*s =", SpaceBtwnItemAndValue, "TDLS STA State");
++				SpaceBtwnItemAndValueTmp = 0;
++				FirstMatchFound = _FALSE;
++				for (j = 0; j < 32; j++) {
++					if (psta->tdls_sta_state & BIT(j)) {
++						if (FirstMatchFound ==  _FALSE) {
++							SpaceBtwnItemAndValueTmp = 1;
++							FirstMatchFound = _TRUE;
++						} else
++							SpaceBtwnItemAndValueTmp = SpaceBtwnItemAndValue + 3;
++						switch (BIT(j)) {
++						case TDLS_INITIATOR_STATE:
++							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_INITIATOR_STATE");
++							break;
++						case TDLS_RESPONDER_STATE:
++							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_RESPONDER_STATE");
++							break;
++						case TDLS_LINKED_STATE:
++							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_LINKED_STATE");
++							break;
++						case TDLS_WAIT_PTR_STATE:
++							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_WAIT_PTR_STATE");
++							break;
++						case TDLS_ALIVE_STATE:
++							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_ALIVE_STATE");
++							break;
++						case TDLS_CH_SWITCH_ON_STATE:
++							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SWITCH_ON_STATE");
++							break;
++						case TDLS_PEER_AT_OFF_STATE:
++							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_PEER_AT_OFF_STATE");
++							break;
++						case TDLS_CH_SW_INITIATOR_STATE:
++							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SW_INITIATOR_STATE");
++							break;
++						case TDLS_WAIT_CH_RSP_STATE:
++							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValue, " ", "TDLS_WAIT_CH_RSP_STATE");
++							break;
++						default:
++							RTW_PRINT_SEL(m, "%-*sBIT(%d)\n", SpaceBtwnItemAndValueTmp, " ", j);
++							break;
++						}
++					}
++				}
++
++				RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Wireless Mode");
++				for (j = 0; j < 8; j++) {
++					if (psta->wireless_mode & BIT(j)) {
++						switch (BIT(j)) {
++						case WIRELESS_11B:
++							RTW_PRINT_SEL(m, "%4s", "11B ");
++							break;
++						case WIRELESS_11G:
++							RTW_PRINT_SEL(m, "%4s", "11G ");
++							break;
++						case WIRELESS_11A:
++							RTW_PRINT_SEL(m, "%4s", "11A ");
++							break;
++						case WIRELESS_11_24N:
++							RTW_PRINT_SEL(m, "%7s", "11_24N ");
++							break;
++						case WIRELESS_11_5N:
++							RTW_PRINT_SEL(m, "%6s", "11_5N ");
++							break;
++						case WIRELESS_AUTO:
++							RTW_PRINT_SEL(m, "%5s", "AUTO ");
++							break;
++						case WIRELESS_11AC:
++							RTW_PRINT_SEL(m, "%5s", "11AC ");
++							break;
++						}
++					}
++				}
++				RTW_PRINT_SEL(m, "\n");
++
++				RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Bandwidth Mode");
++				switch (psta->cmn.bw_mode) {
++				case CHANNEL_WIDTH_20:
++					RTW_PRINT_SEL(m, "%s\n", "20MHz");
++					break;
++				case CHANNEL_WIDTH_40:
++					RTW_PRINT_SEL(m, "%s\n", "40MHz");
++					break;
++				case CHANNEL_WIDTH_80:
++					RTW_PRINT_SEL(m, "%s\n", "80MHz");
++					break;
++				case CHANNEL_WIDTH_160:
++					RTW_PRINT_SEL(m, "%s\n", "160MHz");
++					break;
++				case CHANNEL_WIDTH_80_80:
++					RTW_PRINT_SEL(m, "%s\n", "80MHz + 80MHz");
++					break;
++				case CHANNEL_WIDTH_5:
++					RTW_PRINT_SEL(m, "%s\n", "5MHz");
++					break;
++				case CHANNEL_WIDTH_10:
++					RTW_PRINT_SEL(m, "%s\n", "10MHz");
++					break;
++				default:
++					RTW_PRINT_SEL(m, "(%d)%s\n", psta->cmn.bw_mode, "invalid");
++					break;
++				}
++
++				RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Privacy");
++				switch (psta->dot118021XPrivacy) {
++				case _NO_PRIVACY_:
++					RTW_PRINT_SEL(m, "%s\n", "NO PRIVACY");
++					break;
++				case _WEP40_:
++					RTW_PRINT_SEL(m, "%s\n", "WEP 40");
++					break;
++				case _TKIP_:
++					RTW_PRINT_SEL(m, "%s\n", "TKIP");
++					break;
++				case _TKIP_WTMIC_:
++					RTW_PRINT_SEL(m, "%s\n", "TKIP WTMIC");
++					break;
++				case _AES_:
++					RTW_PRINT_SEL(m, "%s\n", "AES");
++					break;
++				case _WEP104_:
++					RTW_PRINT_SEL(m, "%s\n", "WEP 104");
++					break;
++#if 0 /* no this setting */
++				case _WEP_WPA_MIXED_:
++					RTW_PRINT_SEL(m, "%s\n", "WEP/WPA Mixed");
++					break;
++#endif
++				case _SMS4_:
++					RTW_PRINT_SEL(m, "%s\n", "SMS4");
++					break;
++#ifdef CONFIG_IEEE80211W
++				case _BIP_CMAC_128_:
++					RTW_PRINT_SEL(m, "%s\n", "BIP");
++					break;
++#endif /* CONFIG_IEEE80211W */
++				}
++
++				RTW_PRINT_SEL(m, "%-*s = %d sec/%d sec\n", SpaceBtwnItemAndValue, "TPK Lifetime (Current/Expire)", psta->TPK_count, psta->TDLS_PeerKey_Lifetime);
++				RTW_PRINT_SEL(m, "%-*s = %llu\n", SpaceBtwnItemAndValue, "Tx Packets Over Direct Link", psta->sta_stats.tx_pkts);
++				RTW_PRINT_SEL(m, "%-*s = %llu\n", SpaceBtwnItemAndValue, "Rx Packets Over Direct Link", psta->sta_stats.rx_data_pkts);
++			}
++		}
++	}
++	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++	if (NumOfTdlsStaToShow == 0) {
++		RTW_PRINT_SEL(m, "============[TDLS Peer STA Info]============\n");
++		RTW_PRINT_SEL(m, "No TDLS direct link exists!\n");
++	}
++
++	return 0;
++}
++
++int proc_get_tdls_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++	struct sta_info *psta;
++	int i = 0, j = 0;
++	_irqL irqL;
++	_list	*plist, *phead;
++	u8 SpaceBtwnItemAndValue = 41;
++	u8 SpaceBtwnItemAndValueTmp = 0;
++	u8 NumOfTdlsStaToShow = 0;
++	BOOLEAN FirstMatchFound = _FALSE;
++
++	if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) {
++		RTW_PRINT_SEL(m, "No tdls info can be shown since hal doesn't support tdls\n");
++		return 0;
++	}
++
++	proc_tdls_display_tdls_function_info(m);
++	proc_tdls_display_network_info(m);
++	proc_tdls_display_tdls_sta_info(m);
++
++	return 0;
++}
++#endif
++
++int proc_get_monitor(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++	if (MLME_IS_MONITOR(padapter)) {
++		RTW_PRINT_SEL(m, "Monitor mode : Enable\n");
++		RTW_PRINT_SEL(m, "Device type  : %u\n", dev->type);
++
++		RTW_PRINT_SEL(m, "ch=%d, ch_offset=%d, bw=%d\n",
++			rtw_get_oper_ch(padapter),
++			rtw_get_oper_choffset(padapter),
++			rtw_get_oper_bw(padapter));
++	} else
++		RTW_PRINT_SEL(m, "Monitor mode : Disable\n");
++
++	return 0;
++}
++
++ssize_t proc_set_monitor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	char tmp[32];
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u16 target_type;
++	u8 target_ch, target_offset, target_bw;
++
++	if (count < 3) {
++		RTW_INFO("argument size is less than 3\n");
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = 0;
++
++		num = sscanf(tmp, "type %hu", &target_type);
++		if ((num == 1) &&
++			((target_type != ARPHRD_IEEE80211) &&
++			(target_type != ARPHRD_IEEE80211_RADIOTAP))) {
++			dev->type = ARPHRD_IEEE80211_RADIOTAP;
++			return count;
++		}
++
++		num = sscanf(tmp, "%hhu %hhu %hhu", &target_ch, &target_offset, &target_bw);
++		if (num != 3) {
++			RTW_INFO("invalid write_reg parameter!\n");
++			return count;
++		}
++
++		padapter->mlmeextpriv.cur_channel = target_ch;
++		set_channel_bwmode(padapter, target_ch, target_offset, target_bw);
++	}
++
++	return count;
++}
++
++#ifdef RTW_SIMPLE_CONFIG
++/* For RtwSimleConfig */
++int proc_get_simple_config(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_PRINT_SEL(m, "RTW Simple Config : %s\n", padapter->rtw_simple_config ? "Enable" : "Disable");
++
++	return 0;
++}
++
++ssize_t proc_set_simple_config(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	char tmp[32];
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u8 ret;
++
++	if (count < 1) {
++		RTW_INFO("argument size is less than 1\n");
++		return -EFAULT;
++	}
++	
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%hhd", &ret);
++
++		padapter->rtw_simple_config = ret ? _TRUE : _FALSE;
++	}
++
++	return count;
++}
++#endif
++
++#ifdef DBG_XMIT_BLOCK
++int proc_get_xmit_block(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_xmit_block(m, padapter);
++
++	return 0;
++}
++
++ssize_t proc_set_xmit_block(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u8 xb_mode, xb_reason;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhx %hhx", &xb_mode, &xb_reason);
++
++		if (num != 2) {
++			RTW_INFO("invalid parameter!\n");
++			return count;
++		}
++
++		if (xb_mode == 0)/*set*/
++			rtw_set_xmit_block(padapter, xb_reason);
++		else if (xb_mode == 1)/*clear*/
++			rtw_clr_xmit_block(padapter, xb_reason);
++		else
++			RTW_INFO("invalid parameter!\n");
++	}
++
++	return count;
++}
++#endif
++
++#include <hal_data.h>
++int proc_get_efuse_map(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++	struct pwrctrl_priv *pwrctrlpriv  = adapter_to_pwrctl(padapter);
++	PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
++	int i, j;
++	u8 ips_mode = IPS_NUM;
++	u16 mapLen;
++
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);
++	if (mapLen > EFUSE_MAX_MAP_LEN)
++		mapLen = EFUSE_MAX_MAP_LEN;
++
++	ips_mode = pwrctrlpriv->ips_mode;
++	rtw_pm_set_ips(padapter, IPS_NONE);
++
++	if (pHalData->efuse_file_status == EFUSE_FILE_LOADED) {
++		RTW_PRINT_SEL(m, "File eFuse Map loaded! file path:%s\nDriver eFuse Map From File\n", EFUSE_MAP_PATH);
++		if (pHalData->bautoload_fail_flag)
++			RTW_PRINT_SEL(m, "File Autoload fail!!!\n");
++	} else if (pHalData->efuse_file_status ==  EFUSE_FILE_FAILED) {
++		RTW_PRINT_SEL(m, "Open File eFuse Map Fail ! file path:%s\nDriver eFuse Map From Default\n", EFUSE_MAP_PATH);
++		if (pHalData->bautoload_fail_flag)
++			RTW_PRINT_SEL(m, "HW Autoload fail!!!\n");
++	} else {
++		RTW_PRINT_SEL(m, "Driver eFuse Map From HW\n");
++		if (pHalData->bautoload_fail_flag)
++			RTW_PRINT_SEL(m, "HW Autoload fail!!!\n");
++	}
++	for (i = 0; i < mapLen; i += 16) {
++		RTW_PRINT_SEL(m, "0x%02x\t", i);
++		for (j = 0; j < 8; j++)
++			RTW_PRINT_SEL(m, "%02X ", pHalData->efuse_eeprom_data[i + j]);
++		RTW_PRINT_SEL(m, "\t");
++		for (; j < 16; j++)
++			RTW_PRINT_SEL(m, "%02X ", pHalData->efuse_eeprom_data[i + j]);
++		RTW_PRINT_SEL(m, "\n");
++	}
++
++	if (rtw_efuse_map_read(padapter, 0, mapLen, pEfuseHal->fakeEfuseInitMap) == _FAIL) {
++		RTW_PRINT_SEL(m, "WARN - Read Realmap Failed\n");
++		return 0;
++	}
++
++	RTW_PRINT_SEL(m, "\n");
++	RTW_PRINT_SEL(m, "HW eFuse Map\n");
++	for (i = 0; i < mapLen; i += 16) {
++		RTW_PRINT_SEL(m, "0x%02x\t", i);
++		for (j = 0; j < 8; j++)
++			RTW_PRINT_SEL(m, "%02X ", pEfuseHal->fakeEfuseInitMap[i + j]);
++		RTW_PRINT_SEL(m, "\t");
++		for (; j < 16; j++)
++			RTW_PRINT_SEL(m, "%02X ", pEfuseHal->fakeEfuseInitMap[i + j]);
++		RTW_PRINT_SEL(m, "\n");
++	}
++
++	rtw_pm_set_ips(padapter, ips_mode);
++
++	return 0;
++}
++
++ssize_t proc_set_efuse_map(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++#if 0
++	char tmp[256] = {0};
++	u32 addr, cnts;
++	u8 efuse_data;
++
++	int jj, kk;
++
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct pwrctrl_priv *pwrctrlpriv  = adapter_to_pwrctl(padapter);
++	u8 ips_mode = IPS_NUM;
++
++	if (count < 3) {
++		RTW_INFO("argument size is less than 3\n");
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%x %d %x", &addr, &cnts, &efuse_data);
++
++		if (num != 3) {
++			RTW_INFO("invalid write_reg parameter!\n");
++			return count;
++		}
++	}
++	ips_mode = pwrctrlpriv->ips_mode;
++	rtw_pm_set_ips(padapter, IPS_NONE);
++	if (rtw_efuse_map_write(padapter, addr, cnts, &efuse_data) == _FAIL)
++		RTW_INFO("WARN - rtw_efuse_map_write error!!\n");
++	rtw_pm_set_ips(padapter, ips_mode);
++#endif
++	return count;
++}
++
++#ifdef CONFIG_IEEE80211W
++ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct	sta_priv *pstapriv = &padapter->stapriv;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++	struct sta_info *psta;
++	_list	*plist, *phead;
++	_irqL	 irqL;
++	char tmp[16];
++	u8	mac_addr[NUM_STA][ETH_ALEN];
++	u32 key_type;
++	u8 index;
++
++	if (count > 2) {
++		RTW_INFO("argument size is more than 2\n");
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
++
++		int num = sscanf(tmp, "%x", &key_type);
++
++		if (num !=  1) {
++			RTW_INFO("invalid read_reg parameter!\n");
++			return count;
++		}
++		RTW_INFO("0: set sa query request , key_type=%d\n", key_type);
++	}
++
++	if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
++	    && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) {
++		RTW_INFO("STA:"MAC_FMT"\n", MAC_ARG(get_my_bssid(&(pmlmeinfo->network))));
++		/* TX unicast sa_query to AP */
++		issue_action_SA_Query(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, 0, (u8)key_type);
++	} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) {
++		/* TX unicast sa_query to every client STA */
++		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++		for (index = 0; index < NUM_STA; index++) {
++			psta = NULL;
++
++			phead = &(pstapriv->sta_hash[index]);
++			plist = get_next(phead);
++
++			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++				plist = get_next(plist);
++				_rtw_memcpy(&mac_addr[psta->cmn.mac_id][0], psta->cmn.mac_addr, ETH_ALEN);
++			}
++		}
++		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++		for (index = 0; index < macid_ctl->num && index < NUM_STA; index++) {
++			if (rtw_macid_is_used(macid_ctl, index) && !rtw_macid_is_bmc(macid_ctl, index)) {
++				if (!_rtw_memcmp(get_my_bssid(&(pmlmeinfo->network)), &mac_addr[index][0], ETH_ALEN)
++				    && !IS_MCAST(&mac_addr[index][0])) {
++					issue_action_SA_Query(padapter, &mac_addr[index][0], 0, 0, (u8)key_type);
++					RTW_INFO("STA[%u]:"MAC_FMT"\n", index , MAC_ARG(&mac_addr[index][0]));
++				}
++			}
++		}
++	}
++
++	return count;
++}
++
++int proc_get_tx_sa_query(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_PRINT_SEL(m, "%s\n", __func__);
++	return 0;
++}
++
++ssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct	sta_priv *pstapriv = &padapter->stapriv;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++	struct sta_info *psta;
++	_list	*plist, *phead;
++	_irqL	 irqL;
++	char tmp[16];
++	u8	mac_addr[NUM_STA][ETH_ALEN];
++	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	u32 key_type;
++	u8 index;
++
++
++	if (count > 2) {
++		RTW_INFO("argument size is more than 2\n");
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
++
++		int num = sscanf(tmp, "%x", &key_type);
++
++		if (num !=  1) {
++			RTW_INFO("invalid read_reg parameter!\n");
++			return count;
++		}
++		RTW_INFO("key_type=%d\n", key_type);
++	}
++	if (key_type < 0 || key_type > 4)
++		return count;
++
++	if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
++	    && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) {
++		if (key_type == 3) /* key_type 3 only for AP mode */
++			return count;
++		/* TX unicast deauth to AP */
++		issue_deauth_11w(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, (u8)key_type);
++	} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
++		u8 updated = _FALSE;
++
++		if (key_type == 3)
++			issue_deauth_11w(padapter, bc_addr, 0, IEEE80211W_RIGHT_KEY);
++
++		/* TX unicast deauth to every client STA */
++		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++		for (index = 0; index < NUM_STA; index++) {
++			psta = NULL;
++
++			phead = &(pstapriv->sta_hash[index]);
++			plist = get_next(phead);
++
++			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++				plist = get_next(plist);
++				_rtw_memcpy(&mac_addr[psta->cmn.mac_id][0], psta->cmn.mac_addr, ETH_ALEN);
++			}
++		}
++		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++		for (index = 0; index < macid_ctl->num && index < NUM_STA; index++) {
++			if (rtw_macid_is_used(macid_ctl, index) && !rtw_macid_is_bmc(macid_ctl, index)) {
++				if (!_rtw_memcmp(get_my_bssid(&(pmlmeinfo->network)), &mac_addr[index][0], ETH_ALEN)) {
++					if (key_type != 3)
++						issue_deauth_11w(padapter, &mac_addr[index][0], 0, (u8)key_type);
++
++					psta = rtw_get_stainfo(pstapriv, &mac_addr[index][0]);
++					if (psta && key_type != IEEE80211W_WRONG_KEY && key_type != IEEE80211W_NO_KEY) {
++						_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++						if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
++							rtw_list_delete(&psta->asoc_list);
++							pstapriv->asoc_list_cnt--;
++							#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++							if (psta->tbtx_enable)
++								pstapriv->tbtx_asoc_list_cnt--;
++							#endif
++							updated |= ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE);
++
++						}
++						_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++					}
++
++					RTW_INFO("STA[%u]:"MAC_FMT"\n", index , MAC_ARG(&mac_addr[index][0]));
++				}
++			}
++		}
++
++		associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
++	}
++
++	return count;
++}
++
++int proc_get_tx_deauth(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_PRINT_SEL(m, "%s\n", __func__);
++	return 0;
++}
++
++ssize_t proc_set_tx_auth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct	sta_priv *pstapriv = &padapter->stapriv;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++	struct sta_info *psta;
++	_list	*plist, *phead;
++	_irqL	 irqL;
++	char tmp[16];
++	u8	mac_addr[NUM_STA][ETH_ALEN];
++	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	u32 tx_auth;
++	u8 index;
++
++
++	if (count > 2) {
++		RTW_INFO("argument size is more than 2\n");
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
++
++		int num = sscanf(tmp, "%x", &tx_auth);
++
++		if (num !=  1) {
++			RTW_INFO("invalid read_reg parameter!\n");
++			return count;
++		}
++		RTW_INFO("1: setnd auth, 2: send assoc request. tx_auth=%d\n", tx_auth);
++	}
++
++	if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
++	    && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) {
++		if (tx_auth == 1) {
++			/* TX unicast auth to AP */
++			issue_auth(padapter, NULL, 0);
++		} else if (tx_auth == 2) {
++			/* TX unicast auth to AP */
++			issue_assocreq(padapter);
++		}
++	}
++
++	return count;
++}
++
++int proc_get_tx_auth(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_PRINT_SEL(m, "%s\n", __func__);
++	return 0;
++}
++#endif /* CONFIG_IEEE80211W */
++
++#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
++static u32 phase_idx;
++int proc_get_pathb_phase(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_PRINT_SEL(m, "PathB phase index =%d\n", phase_idx);
++	return 0;
++}
++
++ssize_t proc_set_pathb_phase(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[255];
++	int num;
++	u32 tmp_idx;
++
++	if (NULL == buffer) {
++		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		num = sscanf(tmp, "%u", &tmp_idx);
++		if ((tmp_idx < 0) || (tmp_idx > 11)) {
++			RTW_INFO(FUNC_ADPT_FMT "Invalid input value\n", FUNC_ADPT_ARG(padapter));
++			return count;
++		}
++		phase_idx = tmp_idx;
++		rtw_hal_set_pathb_phase(padapter, phase_idx);
++	}
++	return count;
++}
++#endif
++
++#ifdef CONFIG_MCC_MODE
++int proc_get_mcc_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_adapters_status(m, adapter_to_dvobj(adapter));
++	rtw_hal_dump_mcc_info(m, adapter_to_dvobj(adapter));
++	return 0;
++}
++
++int proc_get_mcc_policy_table(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	rtw_hal_dump_mcc_policy_table(m);
++	return 0;
++}
++
++ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[255];
++	u32 en_mcc = 0;
++
++	if (NULL == buffer) {
++		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++		_adapter *iface = NULL;
++		u8 i = 0;
++		int num = sscanf(tmp, "%u", &en_mcc);
++
++		if (num < 1) {
++			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
++			return -EINVAL;
++		}
++
++		RTW_INFO("%s: en_mcc = %d\n", __func__, en_mcc);
++
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			iface = dvobj->padapters[i];
++			if (!iface)
++				continue;
++			iface->registrypriv.en_mcc = en_mcc;
++		}
++	}
++
++	return count;
++}
++
++ssize_t proc_set_mcc_duration(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[255];
++	u32 enable_runtime_duration = 0, mcc_duration = 0, type = 0;
++
++	if (NULL == buffer) {
++		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%u %u %u", &enable_runtime_duration, &type, &mcc_duration);
++
++		if (num < 1) {
++			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
++			return -EINVAL;
++		}
++
++		if (num > 3) {
++			RTW_INFO(FUNC_ADPT_FMT ": input parameters > 2\n", FUNC_ADPT_ARG(padapter));
++			return -EINVAL;
++		}
++
++		if (num == 2) {
++			RTW_INFO(FUNC_ADPT_FMT ": input parameters > 2\n", FUNC_ADPT_ARG(padapter));
++			return -EINVAL;
++		}
++
++		if (num >= 1) {
++			SET_MCC_RUNTIME_DURATION(padapter, enable_runtime_duration);
++			RTW_INFO("runtime duration:%s\n", enable_runtime_duration ? "enable":"disable");
++		}
++
++		if (num == 3) {
++			RTW_INFO("type:%d, mcc duration:%d\n", type, mcc_duration);
++			rtw_set_mcc_duration_cmd(padapter, type, mcc_duration);
++		}
++	}
++
++	return count;
++}
++
++#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++ssize_t proc_set_mcc_phydm_offload_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[255];
++	u32 mcc_phydm_enable = 0;
++
++	if (NULL == buffer) {
++		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++		u8 i = 0;
++		int num = sscanf(tmp, "%u", &mcc_phydm_enable);
++
++		if (num < 1) {
++			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
++			return -EINVAL;
++		}
++
++		RTW_INFO("%s: mcc phydm enable = %d\n", __func__, mcc_phydm_enable);
++		rtw_set_mcc_phydm_offload_enable_cmd(padapter, mcc_phydm_enable, _TRUE);
++	}
++
++	return count;
++}
++#endif
++
++ssize_t proc_set_mcc_single_tx_criteria(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[255];
++	u32 mcc_single_tx_criteria = 0;
++
++	if (NULL == buffer) {
++		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++		_adapter *iface = NULL;
++		u8 i = 0;
++		int num = sscanf(tmp, "%u", &mcc_single_tx_criteria);
++
++		if (num < 1) {
++			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
++			return -EINVAL;
++		}
++
++		RTW_INFO("%s: mcc_single_tx_criteria = %d\n", __func__, mcc_single_tx_criteria);
++
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			iface = dvobj->padapters[i];
++			if (!iface)
++				continue;
++			iface->registrypriv.rtw_mcc_single_tx_cri = mcc_single_tx_criteria;
++		}
++
++
++	}
++
++	return count;
++}
++
++
++ssize_t proc_set_mcc_ap_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[255];
++	u32 mcc_ap_bw20_target_tp = 0;
++
++	if (NULL == buffer) {
++		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%u", &mcc_ap_bw20_target_tp);
++
++		if (num < 1) {
++			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
++			return -EINVAL;
++		}
++
++		RTW_INFO("%s: mcc_ap_bw20_target_tp = %d\n", __func__, mcc_ap_bw20_target_tp);
++
++		padapter->registrypriv.rtw_mcc_ap_bw20_target_tx_tp = mcc_ap_bw20_target_tp;
++
++
++	}
++
++	return count;
++}
++
++ssize_t proc_set_mcc_ap_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[255];
++	u32 mcc_ap_bw40_target_tp = 0;
++
++	if (NULL == buffer) {
++		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%u", &mcc_ap_bw40_target_tp);
++
++		if (num < 1) {
++			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
++			return -EINVAL;
++		}
++
++		RTW_INFO("%s: mcc_ap_bw40_target_tp = %d\n", __func__, mcc_ap_bw40_target_tp);
++
++		padapter->registrypriv.rtw_mcc_ap_bw40_target_tx_tp = mcc_ap_bw40_target_tp;
++
++
++	}
++
++	return count;
++}
++
++ssize_t proc_set_mcc_ap_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[255];
++	u32 mcc_ap_bw80_target_tp = 0;
++
++	if (NULL == buffer) {
++		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%u", &mcc_ap_bw80_target_tp);
++
++		if (num < 1) {
++			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
++			return -EINVAL;
++		}
++
++		RTW_INFO("%s: mcc_ap_bw80_target_tp = %d\n", __func__, mcc_ap_bw80_target_tp);
++
++		padapter->registrypriv.rtw_mcc_ap_bw80_target_tx_tp = mcc_ap_bw80_target_tp;
++
++
++	}
++
++	return count;
++}
++
++ssize_t proc_set_mcc_sta_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[255];
++	u32 mcc_sta_bw20_target_tp = 0;
++
++	if (NULL == buffer) {
++		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%u", &mcc_sta_bw20_target_tp);
++
++		if (num < 1) {
++			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
++			return -EINVAL;
++		}
++
++		RTW_INFO("%s: mcc_sta_bw20_target_tp = %d\n", __func__, mcc_sta_bw20_target_tp);
++
++		padapter->registrypriv.rtw_mcc_sta_bw20_target_tx_tp = mcc_sta_bw20_target_tp;
++
++
++	}
++
++	return count;
++}
++
++ssize_t proc_set_mcc_sta_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[255];
++	u32 mcc_sta_bw40_target_tp = 0;
++
++	if (NULL == buffer) {
++		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%u", &mcc_sta_bw40_target_tp);
++
++		if (num < 1) {
++			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
++			return -EINVAL;
++		}
++
++		RTW_INFO("%s: mcc_sta_bw40_target_tp = %d\n", __func__, mcc_sta_bw40_target_tp);
++
++		padapter->registrypriv.rtw_mcc_sta_bw40_target_tx_tp = mcc_sta_bw40_target_tp;
++
++
++	}
++
++	return count;
++}
++
++ssize_t proc_set_mcc_sta_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[255];
++	u32 mcc_sta_bw80_target_tp = 0;
++
++	if (NULL == buffer) {
++		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%u", &mcc_sta_bw80_target_tp);
++
++		if (num < 1) {
++			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
++			return -EINVAL;
++		}
++
++		RTW_INFO("%s: mcc_sta_bw80_target_tp = %d\n", __func__, mcc_sta_bw80_target_tp);
++
++		padapter->registrypriv.rtw_mcc_sta_bw80_target_tx_tp = mcc_sta_bw80_target_tp;
++
++
++	}
++
++	return count;
++}
++#endif /* CONFIG_MCC_MODE */
++
++int proc_get_ack_timeout(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u8 ack_timeout_val;
++#ifdef CONFIG_RTL8821C
++	u8 ack_timeout_val_cck;
++#endif
++
++	ack_timeout_val = rtw_read8(padapter, REG_ACKTO);
++
++#ifdef CONFIG_RTL8821C
++	ack_timeout_val_cck = rtw_read8(padapter, REG_ACKTO_CCK_8821C);
++	RTW_PRINT_SEL(m, "Current CCK packet ACK Timeout = %d us (0x%x).\n", ack_timeout_val_cck, ack_timeout_val_cck);
++	RTW_PRINT_SEL(m, "Current non-CCK packet ACK Timeout = %d us (0x%x).\n", ack_timeout_val, ack_timeout_val);
++#else
++	RTW_PRINT_SEL(m, "Current ACK Timeout = %d us (0x%x).\n", ack_timeout_val, ack_timeout_val);
++#endif
++
++	return 0;
++}
++
++ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u32 ack_timeout_ms, ack_timeout_ms_cck;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%u %u", &ack_timeout_ms, &ack_timeout_ms_cck);
++
++#ifdef CONFIG_RTL8821C
++		if (num < 2) {
++			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 2\n", FUNC_ADPT_ARG(padapter));
++			return -EINVAL;
++		}
++#else
++		if (num < 1) {
++			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
++			return -EINVAL;
++		}
++#endif
++		/* This register sets the Ack time out value after Tx unicast packet. It is in units of us. */
++		rtw_write8(padapter, REG_ACKTO, (u8)ack_timeout_ms);
++
++#ifdef CONFIG_RTL8821C
++		/* This register sets the Ack time out value after Tx unicast CCK packet. It is in units of us. */
++		rtw_write8(padapter, REG_ACKTO_CCK_8821C, (u8)ack_timeout_ms_cck);
++		RTW_INFO("Set CCK packet ACK Timeout to %d us.\n", ack_timeout_ms_cck);
++		RTW_INFO("Set non-CCK packet ACK Timeout to %d us.\n", ack_timeout_ms);
++#else
++		RTW_INFO("Set ACK Timeout to %d us.\n", ack_timeout_ms);
++#endif
++	}
++
++	return count;
++}
++
++ssize_t proc_set_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	_adapter *pri_adapter = GET_PRIMARY_ADAPTER(adapter);
++	HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
++	char tmp[32];
++	u32 iqk_offload_enable = 0, ch_switch_offload_enable = 0;
++
++	if (buffer == NULL) {
++		RTW_INFO("input buffer is NULL!\n");
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO("input length is 0!\n");
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		RTW_INFO("input length is too large\n");
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%d %d", &iqk_offload_enable, &ch_switch_offload_enable);
++
++		if (num < 2) {
++			RTW_INFO("input parameters < 1\n");
++			return -EINVAL;
++		}
++
++		if (hal->RegIQKFWOffload != iqk_offload_enable) {
++			hal->RegIQKFWOffload = iqk_offload_enable;
++			rtw_run_in_thread_cmd(pri_adapter, ((void *)(rtw_hal_update_iqk_fw_offload_cap)), pri_adapter);
++		}
++
++		if (hal->ch_switch_offload != ch_switch_offload_enable)
++			hal->ch_switch_offload = ch_switch_offload_enable;
++	}
++
++	return count;
++}
++
++int proc_get_fw_offload(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
++
++
++	RTW_PRINT_SEL(m, "IQK FW offload:%s\n", hal->RegIQKFWOffload?"enable":"disable");
++	RTW_PRINT_SEL(m, "Channel switch FW offload:%s\n", hal->ch_switch_offload?"enable":"disable");
++	return 0;
++}
++#ifdef CONFIG_FW_HANDLE_TXBCN
++extern void rtw_hal_set_fw_ap_bcn_offload_cmd(_adapter *adapter, bool fw_bcn_en, u8 tbtt_rpt_map);
++ssize_t proc_set_fw_tbtt_rpt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u32 fw_tbtt_rpt, fw_bcn_offload;
++
++
++	if (buffer == NULL) {
++		RTW_INFO("input buffer is NULL!\n");
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO("input length is 0!\n");
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		RTW_INFO("input length is too large\n");
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%d %x",&fw_bcn_offload, &fw_tbtt_rpt);
++
++		if (num < 2) {
++			RTW_INFO("input parameters < 2\n");
++			return -EINVAL;
++		}
++		rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, fw_bcn_offload, fw_tbtt_rpt);
++	}
++
++	return count;
++}
++
++int proc_get_fw_tbtt_rpt(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++	RTW_PRINT_SEL(m, "FW BCN offload:%s\n", dvobj->fw_bcn_offload ? "enable" : "disable");
++	RTW_PRINT_SEL(m, "FW TBTT RPT:%x\n", dvobj->vap_tbtt_rpt_map);
++	return 0;
++}
++
++#endif
++
++#ifdef CONFIG_CTRL_TXSS_BY_TP
++ssize_t proc_set_txss_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++
++	char tmp[32];
++	u32 enable = 0;
++	u32 txss_tx_tp = 0;
++	int txss_chk_cnt = 0;
++
++	if (buffer == NULL) {
++		RTW_INFO("input buffer is NULL!\n");
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO("input length is 0!\n");
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		RTW_INFO("input length is too large\n");
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%u %u %d",
++			&enable, &txss_tx_tp, &txss_chk_cnt);
++
++		if (num < 1) {
++			RTW_INFO("input parameters < 1\n");
++			return -EINVAL;
++		}
++		pmlmeext->txss_ctrl_en = enable;
++
++		if (txss_tx_tp)
++			pmlmeext->txss_tp_th = txss_tx_tp;
++		if (txss_chk_cnt)
++			pmlmeext->txss_tp_chk_cnt = txss_chk_cnt;
++
++		RTW_INFO("%s txss_ctl_en :%s , txss_tp_th:%d, tp_chk_cnt:%d\n",
++			__func__, pmlmeext->txss_tp_th ? "Y" : "N",
++			pmlmeext->txss_tp_th, pmlmeext->txss_tp_chk_cnt);
++
++	}
++
++	return count;
++}
++
++int proc_get_txss_tp(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++
++	RTW_PRINT_SEL(m, "TXSS  Control - %s\n", pmlmeext->txss_ctrl_en ? "enable" : "disable");
++	RTW_PRINT_SEL(m, "TXSS  Tx TP TH - %d\n", pmlmeext->txss_tp_th);
++	RTW_PRINT_SEL(m, "TXSS  check cnt - %d\n", pmlmeext->txss_tp_chk_cnt);
++
++	return 0;
++}
++#ifdef DBG_CTRL_TXSS
++ssize_t proc_set_txss_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++
++	char tmp[32];
++	u32 tx_1ss = 0;
++
++	if (buffer == NULL) {
++		RTW_INFO("input buffer is NULL!\n");
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO("input length is 0!\n");
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		RTW_INFO("input length is too large\n");
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%u",	&tx_1ss);
++
++		if (num < 1) {
++			RTW_INFO("input parameters < 1\n");
++			return -EINVAL;
++		}
++
++		pmlmeext->txss_ctrl_en = _FALSE;
++
++		dbg_ctrl_txss(adapter, tx_1ss);
++
++		RTW_INFO("%s set tx to  1ss :%s\n", __func__, tx_1ss ? "Y" : "N");
++	}
++
++	return count;
++}
++
++int proc_get_txss_ctrl(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++
++	RTW_PRINT_SEL(m, "TXSS  1ss - %s\n", pmlmeext->txss_1ss ? "Y" : "N");
++
++	return 0;
++}
++#endif
++#endif
++
++#ifdef CONFIG_DBG_RF_CAL
++int proc_get_iqk_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	return 0;
++}
++
++ssize_t proc_set_iqk(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u32 recovery, clear, segment;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d %d %d", &recovery, &clear, &segment);
++
++		if (num != 3) {
++			RTW_INFO("Invalid format\n");
++			return count;
++		}
++
++		rtw_hal_iqk_test(padapter, recovery, clear, segment);
++	}
++
++	return count;
++
++}
++
++int proc_get_lck_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	return 0;
++}
++
++ssize_t proc_set_lck(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u32 trigger;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d", &trigger);
++
++		if (num != 1) {
++			RTW_INFO("Invalid format\n");
++			return count;
++		}
++
++		rtw_hal_lck_test(padapter);
++	}
++
++	return count;
++}
++#endif /* CONFIG_DBG_RF_CAL */
++
++#ifdef CONFIG_LPS_CHK_BY_TP
++ssize_t proc_set_lps_chk_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	char tmp[32];
++	u32 enable = 0;
++	u32 lps_tx_tp = 0, lps_rx_tp = 0, lps_bi_tp = 0;
++	int lps_chk_cnt_th = 0;
++	u32 lps_tx_pkts = 0, lps_rx_pkts = 0;
++
++	if (buffer == NULL) {
++		RTW_INFO("input buffer is NULL!\n");
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO("input length is 0!\n");
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		RTW_INFO("input length is too large\n");
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%u %u %u %u %d %u %u",
++			&enable, &lps_tx_tp, &lps_rx_tp, &lps_bi_tp,
++			&lps_chk_cnt_th, &lps_tx_pkts, &lps_rx_pkts);
++
++		if (num < 1) {
++			RTW_INFO("input parameters < 1\n");
++			return -EINVAL;
++		}
++		pwrpriv->lps_chk_by_tp = enable;
++
++		if (lps_tx_tp) {
++			pwrpriv->lps_tx_tp_th = lps_tx_tp;
++			pwrpriv->lps_rx_tp_th = lps_tx_tp;
++			pwrpriv->lps_bi_tp_th = lps_tx_tp;
++		}
++		if (lps_rx_tp)
++			pwrpriv->lps_rx_tp_th = lps_rx_tp;
++		if (lps_bi_tp)
++			pwrpriv->lps_bi_tp_th = lps_bi_tp;
++
++		if (lps_chk_cnt_th)
++			pwrpriv->lps_chk_cnt_th = lps_chk_cnt_th;
++
++		if (lps_tx_pkts)
++			pwrpriv->lps_tx_pkts = lps_tx_pkts;
++
++		if (lps_rx_pkts)
++			pwrpriv->lps_rx_pkts = lps_rx_pkts;
++
++		RTW_INFO("%s lps_chk_by_tp:%s , lps_tx_tp_th:%d, lps_tx_tp_th:%d, lps_bi_tp:%d\n",
++			__func__, pwrpriv->lps_chk_by_tp ? "Y" : "N",
++			pwrpriv->lps_tx_tp_th, pwrpriv->lps_tx_tp_th, pwrpriv->lps_bi_tp_th);
++		RTW_INFO("%s lps_chk_cnt_th:%d , lps_tx_pkts:%d, lps_rx_pkts:%d\n",
++			__func__, pwrpriv->lps_chk_cnt_th, pwrpriv->lps_tx_pkts, pwrpriv->lps_rx_pkts);
++	}
++
++	return count;
++}
++
++int proc_get_lps_chk_tp(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++
++	RTW_PRINT_SEL(m, "LPS chk by tp - %s\n", pwrpriv->lps_chk_by_tp ? "enable" : "disable");
++	RTW_PRINT_SEL(m, "LPS Tx TP TH - %d(Mbps)\n", pwrpriv->lps_tx_tp_th);
++	RTW_PRINT_SEL(m, "LPS Rx TP TH - %d(Mbps)\n", pwrpriv->lps_rx_tp_th);
++	RTW_PRINT_SEL(m, "LPS BI TP TH - %d(Mbps)\n", pwrpriv->lps_bi_tp_th);
++
++	RTW_PRINT_SEL(m, "LPS CHK CNT - %d\n", pwrpriv->lps_chk_cnt_th);
++	RTW_PRINT_SEL(m, "LPS Tx PKTs - %d\n", pwrpriv->lps_tx_pkts);
++	RTW_PRINT_SEL(m, "LPS Rx PKTs - %d\n", pwrpriv->lps_rx_pkts);
++	return 0;
++}
++#endif /*CONFIG_LPS_CHK_BY_TP*/
++#ifdef CONFIG_SUPPORT_STATIC_SMPS
++ssize_t proc_set_smps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++	char tmp[32];
++	u32 enable = 0;
++	u32 smps_en, smps_tx_tp = 0, smps_rx_tp = 0;
++	u32 smps_test = 0, smps_test_en = 0;
++
++	if (buffer == NULL) {
++		RTW_INFO("input buffer is NULL!\n");
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO("input length is 0!\n");
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		RTW_INFO("input length is too large\n");
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%u %u %u %u %u", &smps_en, &smps_tx_tp, &smps_rx_tp,
++			&smps_test, &smps_test_en);
++
++		if (num < 1) {
++			RTW_INFO("input parameters < 1\n");
++			return -EINVAL;
++		}
++
++		pmlmeext->ssmps_en = smps_en;
++		if (smps_tx_tp) {
++			pmlmeext->ssmps_tx_tp_th= smps_tx_tp;
++			pmlmeext->ssmps_rx_tp_th= smps_tx_tp;
++		}
++		if (smps_rx_tp)
++			pmlmeext->ssmps_rx_tp_th = smps_rx_tp;
++
++		#ifdef DBG_STATIC_SMPS
++		if (num > 3) {
++			pmlmeext->ssmps_test = smps_test;
++			pmlmeext->ssmps_test_en = smps_test_en;
++		}
++		#endif
++		RTW_INFO("SM PS : %s tx_tp_th:%d, rx_tp_th:%d\n",
++			(smps_en) ? "Enable" : "Disable",
++			pmlmeext->ssmps_tx_tp_th,
++			pmlmeext->ssmps_rx_tp_th);
++		#ifdef DBG_STATIC_SMPS
++		RTW_INFO("SM PS : %s ssmps_test_en:%d\n",
++			(smps_test) ? "Enable" : "Disable",
++			pmlmeext->ssmps_test_en);
++		#endif
++	}
++
++	return count;
++}
++
++int proc_get_smps(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++
++	RTW_PRINT_SEL(m, "Static SMPS %s\n", pmlmeext->ssmps_en ? "enable" : "disable");
++	RTW_PRINT_SEL(m, "Tx TP TH %d\n", pmlmeext->ssmps_tx_tp_th);
++	RTW_PRINT_SEL(m, "Rx TP TH %d\n", pmlmeext->ssmps_rx_tp_th);
++	#ifdef DBG_STATIC_SMPS
++	RTW_PRINT_SEL(m, "test %d, test_en:%d\n", pmlmeext->ssmps_test, pmlmeext->ssmps_test_en);
++	#endif
++	return 0;
++}
++#endif /*CONFIG_SUPPORT_STATIC_SMPS*/
++
++#endif /* CONFIG_PROC_DEBUG */
++#define RTW_BUFDUMP_BSIZE		16
++#if 1
++inline void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring,
++					bool _idx_show, const u8 *_hexdata, int _hexdatalen)
++{
++#ifdef CONFIG_RTW_DEBUG
++	int __i;
++	u8 *ptr = (u8 *)_hexdata;
++
++	if (_loglevel <= rtw_drv_log_level) {
++		if (_titlestring) {
++			if (sel == RTW_DBGDUMP)
++				RTW_PRINT("");
++			_RTW_PRINT_SEL(sel, "%s", _titlestring);
++			if (_hexdatalen >= RTW_BUFDUMP_BSIZE)
++				_RTW_PRINT_SEL(sel, "\n");
++		}
++
++		for (__i = 0; __i < _hexdatalen; __i++) {
++			if (((__i % RTW_BUFDUMP_BSIZE) == 0) && (_hexdatalen >= RTW_BUFDUMP_BSIZE)) {
++				if (sel == RTW_DBGDUMP)
++					RTW_PRINT("");
++				if (_idx_show)
++					_RTW_PRINT_SEL(sel, "0x%03X: ", __i);
++			}
++			_RTW_PRINT_SEL(sel, "%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? "  " : " ");
++			if ((__i + 1 < _hexdatalen) && ((__i + 1) % RTW_BUFDUMP_BSIZE) == 0)
++				_RTW_PRINT_SEL(sel, "\n");
++		}
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++#endif
++}
++#else
++inline void _RTW_STR_DUMP_SEL(void *sel, char *str_out)
++{
++	if (sel == RTW_DBGDUMP)
++		_dbgdump("%s\n", str_out);
++	#if defined(_seqdump)
++	else
++		_seqdump(sel, "%s\n", str_out);
++	#endif /*_seqdump*/
++}
++inline void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring,
++					bool _idx_show, u8 *_hexdata, int _hexdatalen)
++{
++	int __i, len;
++	int __j, idx;
++	int block_num, remain_byte;
++	char str_out[128] = {'\0'};
++	char str_val[32] = {'\0'};
++	char *p = NULL;
++	u8 *ptr = (u8 *)_hexdata;
++
++	if (_loglevel <= rtw_drv_log_level) {
++		/*dump title*/
++		p = &str_out[0];
++		if (_titlestring) {
++			if (sel == RTW_DBGDUMP) {
++				len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX);
++				strncpy(p, str_val, len);
++				p += len;
++			}
++			len = snprintf(str_val, sizeof(str_val), "%s", _titlestring);
++			strncpy(p, str_val, len);
++			p += len;
++		}
++		if (p != &str_out[0]) {
++			_RTW_STR_DUMP_SEL(sel, str_out);
++			_rtw_memset(&str_out, '\0', sizeof(str_out));
++		}
++
++		/*dump buffer*/
++		block_num = _hexdatalen / RTW_BUFDUMP_BSIZE;
++		remain_byte = _hexdatalen % RTW_BUFDUMP_BSIZE;
++		for (__i = 0; __i < block_num; __i++) {
++			p = &str_out[0];
++			if (sel == RTW_DBGDUMP) {
++				len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX);
++				strncpy(p, str_val, len);
++				p += len;
++			}
++			if (_idx_show) {
++				len = snprintf(str_val, sizeof(str_val), "0x%03X: ", __i * RTW_BUFDUMP_BSIZE);
++				strncpy(p, str_val, len);
++				p += len;
++			}
++			for (__j =0; __j < RTW_BUFDUMP_BSIZE; __j++) {
++				idx = __i * RTW_BUFDUMP_BSIZE + __j;
++				len = snprintf(str_val, sizeof(str_val), "%02X%s", ptr[idx], (((__j + 1) % 4) == 0) ? "  " : " ");
++				strncpy(p, str_val, len);
++				p += len;
++			}
++			_RTW_STR_DUMP_SEL(sel, str_out);
++			_rtw_memset(&str_out, '\0', sizeof(str_out));
++		}
++
++		p = &str_out[0];
++		if ((sel == RTW_DBGDUMP) && remain_byte) {
++			len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX);
++			strncpy(p, str_val, len);
++			p += len;
++		}
++		if (_idx_show && remain_byte) {
++			len = snprintf(str_val, sizeof(str_val), "0x%03X: ", block_num * RTW_BUFDUMP_BSIZE);
++			strncpy(p, str_val, len);
++			p += len;
++		}
++		for (__i = 0; __i < remain_byte; __i++) {
++			idx = block_num * RTW_BUFDUMP_BSIZE + __i;
++			len = snprintf(str_val, sizeof(str_val), "%02X%s", ptr[idx], (((__i + 1) % 4) == 0) ? "  " : " ");
++			strncpy(p, str_val, len);
++			p += len;
++		}
++		_RTW_STR_DUMP_SEL(sel, str_out);
++	}
++}
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_eeprom.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_eeprom.c
+new file mode 100644
+index 000000000..62c0be06c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_eeprom.c
+@@ -0,0 +1,329 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_EEPROM_C_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++void up_clk(_adapter	*padapter,	 u16 *x)
++{
++	*x = *x | _EESK;
++	rtw_write8(padapter, EE_9346CR, (u8)*x);
++	rtw_udelay_os(CLOCK_RATE);
++
++
++}
++
++void down_clk(_adapter	*padapter, u16 *x)
++{
++	*x = *x & ~_EESK;
++	rtw_write8(padapter, EE_9346CR, (u8)*x);
++	rtw_udelay_os(CLOCK_RATE);
++}
++
++void shift_out_bits(_adapter *padapter, u16 data, u16 count)
++{
++	u16 x, mask;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		goto out;
++	}
++	mask = 0x01 << (count - 1);
++	x = rtw_read8(padapter, EE_9346CR);
++
++	x &= ~(_EEDO | _EEDI);
++
++	do {
++		x &= ~_EEDI;
++		if (data & mask)
++			x |= _EEDI;
++		if (rtw_is_surprise_removed(padapter)) {
++			goto out;
++		}
++		rtw_write8(padapter, EE_9346CR, (u8)x);
++		rtw_udelay_os(CLOCK_RATE);
++		up_clk(padapter, &x);
++		down_clk(padapter, &x);
++		mask = mask >> 1;
++	} while (mask);
++	if (rtw_is_surprise_removed(padapter)) {
++		goto out;
++	}
++	x &= ~_EEDI;
++	rtw_write8(padapter, EE_9346CR, (u8)x);
++out:
++	return;
++}
++
++u16 shift_in_bits(_adapter *padapter)
++{
++	u16 x, d = 0, i;
++	if (rtw_is_surprise_removed(padapter)) {
++		goto out;
++	}
++	x = rtw_read8(padapter, EE_9346CR);
++
++	x &= ~(_EEDO | _EEDI);
++	d = 0;
++
++	for (i = 0; i < 16; i++) {
++		d = d << 1;
++		up_clk(padapter, &x);
++		if (rtw_is_surprise_removed(padapter)) {
++			goto out;
++		}
++		x = rtw_read8(padapter, EE_9346CR);
++
++		x &= ~(_EEDI);
++		if (x & _EEDO)
++			d |= 1;
++
++		down_clk(padapter, &x);
++	}
++out:
++
++	return d;
++}
++
++void standby(_adapter	*padapter)
++{
++	u8   x;
++	x = rtw_read8(padapter, EE_9346CR);
++
++	x &= ~(_EECS | _EESK);
++	rtw_write8(padapter, EE_9346CR, x);
++
++	rtw_udelay_os(CLOCK_RATE);
++	x |= _EECS;
++	rtw_write8(padapter, EE_9346CR, x);
++	rtw_udelay_os(CLOCK_RATE);
++}
++
++u16 wait_eeprom_cmd_done(_adapter *padapter)
++{
++	u8	x;
++	u16	i, res = _FALSE;
++	standby(padapter);
++	for (i = 0; i < 200; i++) {
++		x = rtw_read8(padapter, EE_9346CR);
++		if (x & _EEDO) {
++			res = _TRUE;
++			goto exit;
++		}
++		rtw_udelay_os(CLOCK_RATE);
++	}
++exit:
++	return res;
++}
++
++void eeprom_clean(_adapter *padapter)
++{
++	u16 x;
++	if (rtw_is_surprise_removed(padapter)) {
++		goto out;
++	}
++	x = rtw_read8(padapter, EE_9346CR);
++	if (rtw_is_surprise_removed(padapter)) {
++		goto out;
++	}
++	x &= ~(_EECS | _EEDI);
++	rtw_write8(padapter, EE_9346CR, (u8)x);
++	if (rtw_is_surprise_removed(padapter)) {
++		goto out;
++	}
++	up_clk(padapter, &x);
++	if (rtw_is_surprise_removed(padapter)) {
++		goto out;
++	}
++	down_clk(padapter, &x);
++out:
++	return;
++}
++
++void eeprom_write16(_adapter *padapter, u16 reg, u16 data)
++{
++	u8 x;
++	x = rtw_read8(padapter, EE_9346CR);
++
++	x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
++	x |= _EEM1 | _EECS;
++	rtw_write8(padapter, EE_9346CR, x);
++
++	shift_out_bits(padapter, EEPROM_EWEN_OPCODE, 5);
++
++	if (padapter->EepromAddressSize == 8)	/* CF+ and SDIO */
++		shift_out_bits(padapter, 0, 6);
++	else									/* USB */
++		shift_out_bits(padapter, 0, 4);
++
++	standby(padapter);
++
++	/* Commented out by rcnjko, 2004.0
++	 * 	  Erase this particular word.  Write the erase opcode and register
++	 *    number in that order. The opcode is 3bits in length; reg is 6 bits long. */
++/*	shift_out_bits(Adapter, EEPROM_ERASE_OPCODE, 3);
++ *	shift_out_bits(Adapter, reg, Adapter->EepromAddressSize);
++ *
++ *	if (wait_eeprom_cmd_done(Adapter ) == FALSE)
++ *	{
++ *		return;
++ *	} */
++
++
++	standby(padapter);
++
++	/* write the new word to the EEPROM */
++
++	/* send the write opcode the EEPORM */
++	shift_out_bits(padapter, EEPROM_WRITE_OPCODE, 3);
++
++	/* select which word in the EEPROM that we are writing to. */
++	shift_out_bits(padapter, reg, padapter->EepromAddressSize);
++
++	/* write the data to the selected EEPROM word. */
++	shift_out_bits(padapter, data, 16);
++
++	if (wait_eeprom_cmd_done(padapter) == _FALSE)
++
++		goto exit;
++
++	standby(padapter);
++
++	shift_out_bits(padapter, EEPROM_EWDS_OPCODE, 5);
++	shift_out_bits(padapter, reg, 4);
++
++	eeprom_clean(padapter);
++exit:
++	return;
++}
++
++u16 eeprom_read16(_adapter *padapter, u16 reg)  /* ReadEEprom */
++{
++
++	u16 x;
++	u16 data = 0;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		goto out;
++	}
++	/* select EEPROM, reset bits, set _EECS */
++	x = rtw_read8(padapter, EE_9346CR);
++
++	if (rtw_is_surprise_removed(padapter)) {
++		goto out;
++	}
++
++	x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
++	x |= _EEM1 | _EECS;
++	rtw_write8(padapter, EE_9346CR, (unsigned char)x);
++
++	/* write the read opcode and register number in that order */
++	/* The opcode is 3bits in length, reg is 6 bits long */
++	shift_out_bits(padapter, EEPROM_READ_OPCODE, 3);
++	shift_out_bits(padapter, reg, padapter->EepromAddressSize);
++
++	/* Now read the data (16 bits) in from the selected EEPROM word */
++	data = shift_in_bits(padapter);
++
++	eeprom_clean(padapter);
++out:
++
++	return data;
++
++
++}
++
++
++
++
++/* From even offset */
++void eeprom_read_sz(_adapter *padapter, u16 reg, u8 *data, u32 sz)
++{
++
++	u16 x, data16;
++	u32 i;
++	if (rtw_is_surprise_removed(padapter)) {
++		goto out;
++	}
++	/* select EEPROM, reset bits, set _EECS */
++	x = rtw_read8(padapter, EE_9346CR);
++
++	if (rtw_is_surprise_removed(padapter)) {
++		goto out;
++	}
++
++	x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
++	x |= _EEM1 | _EECS;
++	rtw_write8(padapter, EE_9346CR, (unsigned char)x);
++
++	/* write the read opcode and register number in that order */
++	/* The opcode is 3bits in length, reg is 6 bits long */
++	shift_out_bits(padapter, EEPROM_READ_OPCODE, 3);
++	shift_out_bits(padapter, reg, padapter->EepromAddressSize);
++
++
++	for (i = 0; i < sz; i += 2) {
++		data16 = shift_in_bits(padapter);
++		data[i] = data16 & 0xff;
++		data[i + 1] = data16 >> 8;
++	}
++
++	eeprom_clean(padapter);
++out:
++	return;
++}
++
++
++/* addr_off : address offset of the entry in eeprom (not the tuple number of eeprom (reg); that is addr_off !=reg) */
++u8 eeprom_read(_adapter *padapter, u32 addr_off, u8 sz, u8 *rbuf)
++{
++	u8 quotient, remainder, addr_2align_odd;
++	u16 reg, stmp , i = 0, idx = 0;
++	reg = (u16)(addr_off >> 1);
++	addr_2align_odd = (u8)(addr_off & 0x1);
++
++	if (addr_2align_odd) { /* read that start at high part: e.g  1,3,5,7,9,... */
++		stmp = eeprom_read16(padapter, reg);
++		rbuf[idx++] = (u8)((stmp >> 8) & 0xff); /* return hogh-part of the short */
++		reg++;
++		sz--;
++	}
++
++	quotient = sz >> 1;
++	remainder = sz & 0x1;
++
++	for (i = 0 ; i < quotient; i++) {
++		stmp = eeprom_read16(padapter, reg + i);
++		rbuf[idx++] = (u8)(stmp & 0xff);
++		rbuf[idx++] = (u8)((stmp >> 8) & 0xff);
++	}
++
++	reg = reg + i;
++	if (remainder) { /* end of read at lower part of short : 0,2,4,6,... */
++		stmp = eeprom_read16(padapter, reg);
++		rbuf[idx] = (u8)(stmp & 0xff);
++	}
++	return _TRUE;
++}
++
++
++
++void read_eeprom_content(_adapter	*padapter)
++{
++
++
++
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_ft.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_ft.c
+new file mode 100755
+index 000000000..1ba55ce74
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_ft.c
+@@ -0,0 +1,668 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++#ifdef CONFIG_RTW_80211R
++
++#ifndef RTW_FT_DBG
++	#define RTW_FT_DBG	0
++#endif
++#if RTW_FT_DBG
++	#define RTW_FT_INFO(fmt, arg...)	\
++		RTW_INFO(fmt, arg)
++	#define RTW_FT_DUMP(str, data, len)	\
++		RTW_INFO_DUMP(str, data, len)
++#else
++	#define RTW_FT_INFO(fmt, arg...) do {} while (0)
++	#define RTW_FT_DUMP(str, data, len) do {} while (0)
++#endif
++
++void rtw_ft_info_init(struct ft_roam_info *pft)
++{
++	_rtw_memset(pft, 0, sizeof(struct ft_roam_info));
++	pft->ft_flags = 0
++		| RTW_FT_EN
++	/*	| RTW_FT_OTD_EN */
++#ifdef CONFIG_RTW_BTM_ROAM
++		| RTW_FT_BTM_ROAM
++#endif
++		;
++	pft->ft_updated_bcn = _FALSE;
++	RTW_FT_INFO("%s : ft_flags=0x%02x\n", __func__, pft->ft_flags);
++}
++
++ssize_t rtw_ft_proc_flags_set(struct file *file,
++	const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	char tmp[32];
++	u8 flags;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%hhx", &flags);
++		if (num == 1)
++			adapter->mlmepriv.ft_roam.ft_flags = flags;
++	}
++
++	return count;
++
++}
++
++int rtw_ft_proc_flags_get(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_PRINT_SEL(m, "0x%02x\n", adapter->mlmepriv.ft_roam.ft_flags);
++
++	return 0;
++}
++
++u8 rtw_ft_chk_roaming_candidate(
++	_adapter *padapter, struct wlan_network *competitor)
++{
++	u8 *pmdie;
++	u32 mdie_len = 0;
++	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
++
++	if (!(pmdie = rtw_get_ie(&competitor->network.IEs[12],
++			_MDIE_, &mdie_len, competitor->network.IELength-12))) {
++		RTW_INFO("FT : MDIE not foud in competitor!\n");
++		return _FALSE;
++	}	
++
++	if (!_rtw_memcmp(&pft_roam->mdid, (pmdie+2), 2)) {
++		RTW_INFO("FT : unmatched MDIE!\n");
++		return _FALSE;
++	}
++
++	/*The candidate don't support over-the-DS*/
++	if (rtw_ft_valid_otd_candidate(padapter, pmdie)) {
++		RTW_INFO("FT: ignore the candidate("
++			MAC_FMT ") for over-the-DS\n", 
++			MAC_ARG(competitor->network.MacAddress));
++		/*	rtw_ft_clr_flags(padapter, RTW_FT_PEER_OTD_EN); */
++		return _FALSE;	
++	}
++
++	if (rtw_ft_chk_flags(padapter, RTW_FT_TEST_RSSI_ROAM)) {
++		if (!_rtw_memcmp(padapter->mlmepriv.cur_network.network.MacAddress, 
++			competitor->network.MacAddress, ETH_ALEN) ) {
++			competitor->network.Rssi +=20;
++			RTW_FT_INFO("%s : update "MAC_FMT" RSSI to %d for RTW_FT_TEST_RSSI_ROAM\n",
++				__func__, MAC_ARG(competitor->network.MacAddress),
++				(int)competitor->network.Rssi);
++			rtw_ft_clr_flags(padapter, RTW_FT_TEST_RSSI_ROAM);
++		}
++	}	
++
++	return _TRUE;
++}
++
++void rtw_ft_update_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork)
++{
++	struct sta_priv		*pstapriv = &padapter->stapriv;
++	struct sta_info		*psta = NULL;
++
++	psta = rtw_get_stainfo(pstapriv, pnetwork->MacAddress);
++	if (psta == NULL)
++		psta = rtw_alloc_stainfo(pstapriv, pnetwork->MacAddress);
++
++	if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) {
++
++		padapter->securitypriv.binstallGrpkey = _FALSE;
++		padapter->securitypriv.busetkipkey = _FALSE;
++		padapter->securitypriv.bgrpkey_handshake = _FALSE;
++
++		psta->ieee8021x_blocked = _TRUE;
++		psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
++
++		_rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof(union Keytype));
++		_rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof(union Keytype));
++		_rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof(union Keytype));
++	}
++
++}
++
++void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct stassoc_event *pstassoc = (struct stassoc_event *)pbuf;
++	struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&(pmlmeinfo->network);
++	struct cfg80211_ft_event_params ft_evt_parms;
++	_irqL irqL;
++
++	_rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms));
++	rtw_ft_update_stainfo(padapter, pnetwork);
++	ft_evt_parms.ies_len = pft_roam->ft_event.ies_len;
++	ft_evt_parms.ies =  rtw_zmalloc(ft_evt_parms.ies_len);
++	if (ft_evt_parms.ies)
++		_rtw_memcpy((void *)ft_evt_parms.ies, pft_roam->ft_event.ies, ft_evt_parms.ies_len);
++	 else
++		goto err_2;
++
++	ft_evt_parms.target_ap = rtw_zmalloc(ETH_ALEN);
++	if (ft_evt_parms.target_ap)
++		_rtw_memcpy((void *)ft_evt_parms.target_ap, pstassoc->macaddr, ETH_ALEN);
++	else
++		goto err_1;
++
++	ft_evt_parms.ric_ies = pft_roam->ft_event.ric_ies;
++	ft_evt_parms.ric_ies_len = pft_roam->ft_event.ric_ies_len;
++
++	/* It's a KERNEL issue between v4.11 ~ v4.16, 
++	* <= v4.10, NLMSG_DEFAULT_SIZE is used for nlmsg_new().
++	* v4.11 ~ v4.16, only used "100 + >ric_ies_len" for nlmsg_new() 
++	*	even then DRIVER don't support RIC.
++	* >= v4.17, issue should correct as "100 + ies_len + ric_ies_len".
++	*/	
++	#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)) && \
++	(LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0)))
++		if (!ft_evt_parms.ric_ies_len)
++			ft_evt_parms.ric_ies_len = ft_evt_parms.ies_len;
++		else 
++			ft_evt_parms.ric_ies_len += ft_evt_parms.ies_len;	
++	#endif	
++	
++	rtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA, &irqL);
++	rtw_cfg80211_ft_event(padapter, &ft_evt_parms);
++	RTW_INFO("%s: to "MAC_FMT"\n", __func__, MAC_ARG(ft_evt_parms.target_ap));
++
++	rtw_mfree((u8 *)pft_roam->ft_event.target_ap, ETH_ALEN);
++err_1:
++	rtw_mfree((u8 *)ft_evt_parms.ies, ft_evt_parms.ies_len);
++err_2:
++	return;
++}
++
++void rtw_ft_validate_akm_type(_adapter  *padapter,
++	struct wlan_network *pnetwork)
++{
++	struct security_priv *psecuritypriv = &(padapter->securitypriv);
++	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
++	u32 tmp_len;
++	u8 *ptmp;
++
++	/*IEEE802.11-2012 Std. Table 8-101-AKM suite selectors*/
++	if (rtw_ft_valid_akm(padapter, psecuritypriv->rsn_akm_suite_type)) {
++		ptmp = rtw_get_ie(&pnetwork->network.IEs[12], 
++				_MDIE_, &tmp_len, (pnetwork->network.IELength-12));
++		if (ptmp) {
++			pft_roam->mdid = *(u16 *)(ptmp+2);
++			pft_roam->ft_cap = *(ptmp+4);
++
++			RTW_INFO("FT: target " MAC_FMT " mdid=(0x%2x), capacity=(0x%2x)\n", 
++				MAC_ARG(pnetwork->network.MacAddress), pft_roam->mdid, pft_roam->ft_cap);
++			rtw_ft_set_flags(padapter, RTW_FT_PEER_EN);
++			RTW_FT_INFO("%s : peer support FTOTA(0x%02x)\n", __func__, pft_roam->ft_flags);
++
++			if (rtw_ft_otd_roam_en(padapter)) {
++				rtw_ft_set_flags(padapter, RTW_FT_PEER_OTD_EN);
++				RTW_FT_INFO("%s : peer support FTOTD(0x%02x)\n", __func__, pft_roam->ft_flags);
++			}
++		} else {
++			/* Don't use FT roaming if target AP cannot support FT */
++			rtw_ft_clr_flags(padapter, (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN));
++			rtw_ft_reset_status(padapter);
++		}
++	} else {
++		/* It could be a non-FT connection */
++		rtw_ft_clr_flags(padapter, (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN));
++		rtw_ft_reset_status(padapter);
++	}	
++
++	RTW_FT_INFO("%s : ft_flags=0x%02x\n", __func__, pft_roam->ft_flags);
++}
++
++void rtw_ft_update_bcn(_adapter *padapter, union recv_frame *precv_frame)
++{
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	uint len = precv_frame->u.hdr.len;
++	WLAN_BSSID_EX *pbss;
++
++	if (rtw_ft_chk_status(padapter,RTW_FT_ASSOCIATED_STA) 
++		&& (pmlmepriv->ft_roam.ft_updated_bcn == _FALSE)) {
++		pbss = (WLAN_BSSID_EX*)rtw_malloc(sizeof(WLAN_BSSID_EX));
++		if (pbss) {
++			if (collect_bss_info(padapter, precv_frame, pbss) == _SUCCESS) {
++				struct beacon_keys recv_beacon;
++
++				update_network(&(pmlmepriv->cur_network.network), pbss, padapter, _TRUE);
++				/* Move into rtw_get_bcn_keys */
++				/* rtw_get_bcn_info(&(pmlmepriv->cur_network)); */
++				
++				/* update bcn keys */
++				if (rtw_get_bcn_keys(padapter, pframe, len, &recv_beacon) == _TRUE) {
++					RTW_FT_INFO("%s: beacon keys ready\n", __func__);
++					_rtw_memcpy(&pmlmepriv->cur_beacon_keys,
++						&recv_beacon, sizeof(recv_beacon));
++					if (is_hidden_ssid(recv_beacon.ssid, recv_beacon.ssid_len)) {
++						_rtw_memcpy(pmlmepriv->cur_beacon_keys.ssid, pmlmeinfo->network.Ssid.Ssid, IW_ESSID_MAX_SIZE);
++						pmlmepriv->cur_beacon_keys.ssid_len = pmlmeinfo->network.Ssid.SsidLength;
++					}
++				} else {
++					RTW_ERR("%s: get beacon keys failed\n", __func__);
++					_rtw_memset(&pmlmepriv->cur_beacon_keys, 0, sizeof(recv_beacon));
++				}
++				#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
++				pmlmepriv->new_beacon_cnts = 0;
++				#endif
++			}
++			rtw_mfree((u8*)pbss, sizeof(WLAN_BSSID_EX));
++		}
++
++		/* check the vendor of the assoc AP */
++		pmlmeinfo->assoc_AP_vendor = 	
++			check_assoc_AP(pframe+sizeof(struct rtw_ieee80211_hdr_3addr),
++				(len - sizeof(struct rtw_ieee80211_hdr_3addr)));
++
++		/* update TSF Value */
++		update_TSF(pmlmeext, pframe, len);
++		pmlmeext->bcn_cnt = 0;
++		pmlmeext->last_bcn_cnt = 0;
++		pmlmepriv->ft_roam.ft_updated_bcn = _TRUE;
++	}
++}
++
++void rtw_ft_start_clnt_join(_adapter *padapter)
++{
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct	mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
++
++	if (rtw_ft_otd_roam(padapter)) {
++		pmlmeinfo->state = WIFI_FW_AUTH_SUCCESS | WIFI_FW_STATION_STATE;
++		pft_roam->ft_event.ies =
++			(pft_roam->ft_action + sizeof(struct rtw_ieee80211_hdr_3addr) + 16);
++		pft_roam->ft_event.ies_len =
++			(pft_roam->ft_action_len - sizeof(struct rtw_ieee80211_hdr_3addr));
++
++		/*Not support RIC*/
++		pft_roam->ft_event.ric_ies =  NULL;
++		pft_roam->ft_event.ric_ies_len = 0;
++		rtw_ft_report_evt(padapter);
++		return;
++	}
++
++	pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE;
++	start_clnt_auth(padapter);
++}
++
++u8 rtw_ft_update_rsnie(
++	_adapter *padapter, u8 bwrite, 
++	struct pkt_attrib *pattrib, u8 **pframe)
++{
++	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
++	u8 *pie;
++	u32 len;
++
++	pie = rtw_get_ie(pft_roam->updated_ft_ies, EID_WPA2, &len, 
++			pft_roam->updated_ft_ies_len);
++
++	if (!bwrite)
++		return (pie)?_SUCCESS:_FAIL;
++	
++	if (pie) {
++		*pframe = rtw_set_ie(((u8 *)*pframe), EID_WPA2, len, 
++						pie+2, &(pattrib->pktlen));
++	} else
++		return _FAIL;
++
++	return _SUCCESS;	
++}
++
++static u8 rtw_ft_update_mdie(
++	_adapter *padapter, struct pkt_attrib *pattrib, u8 **pframe)
++{
++	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
++	u8 *pie, mdie[3];
++	u32 len = 3;
++
++	if (rtw_ft_roam(padapter)) {
++		if ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _MDIE_, 
++				&len, pft_roam->updated_ft_ies_len))) {
++			pie = (pie + 2); /* ignore md-id & length */
++		} else 
++			return _FAIL;
++	} else {
++		*((u16 *)&mdie[0]) = pft_roam->mdid;
++		mdie[2] = pft_roam->ft_cap;
++		pie = &mdie[0];
++	}
++
++	*pframe = rtw_set_ie(((u8 *)*pframe), _MDIE_, len , pie, &(pattrib->pktlen));
++	return _SUCCESS;	
++}
++
++static u8 rtw_ft_update_ftie(
++	_adapter *padapter, struct pkt_attrib *pattrib, u8 **pframe)
++{
++	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
++	u8 *pie;
++	u32 len;
++
++	if ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _FTIE_, &len, 
++				pft_roam->updated_ft_ies_len)) != NULL) {
++		*pframe = rtw_set_ie(*pframe, _FTIE_, len , 
++					(pie+2), &(pattrib->pktlen));
++	} else
++		return _FAIL;
++
++	return _SUCCESS;	
++}
++
++void rtw_ft_build_auth_req_ies(_adapter *padapter, 
++	struct pkt_attrib *pattrib, u8 **pframe)
++{
++	u8 ftie_append = _TRUE;
++
++	if (!pattrib || !(*pframe))
++		return;
++
++	if (!rtw_ft_roam(padapter))
++		return;
++
++	ftie_append = rtw_ft_update_rsnie(padapter, _TRUE, pattrib, pframe);
++	rtw_ft_update_mdie(padapter, pattrib, pframe);
++	if (ftie_append)
++		rtw_ft_update_ftie(padapter, pattrib, pframe);
++}
++
++void rtw_ft_build_assoc_req_ies(_adapter *padapter, 
++	u8 is_reassoc, struct pkt_attrib *pattrib, u8 **pframe)
++{
++	if (!pattrib || !(*pframe))
++		return;
++
++	if (rtw_ft_chk_flags(padapter, RTW_FT_PEER_EN))
++		rtw_ft_update_mdie(padapter, pattrib, pframe);
++
++	if ((!is_reassoc) || (!rtw_ft_roam(padapter)))
++		return;
++
++	if (rtw_ft_update_rsnie(padapter, _FALSE, pattrib, pframe))
++		rtw_ft_update_ftie(padapter, pattrib, pframe);	
++}
++
++u8 rtw_ft_update_auth_rsp_ies(_adapter *padapter, u8 *pframe, u32 len)
++{
++	u8 ret = _SUCCESS;
++	u8 target_ap_addr[ETH_ALEN] = {0};
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
++
++	if (!rtw_ft_roam(padapter))
++		return _FAIL;
++
++	/*rtw_ft_report_reassoc_evt already,
++	 * and waiting for cfg80211_rtw_update_ft_ies */
++	if (rtw_ft_authed_sta(padapter))
++		return ret;
++
++	if (!pframe || !len)
++		return _FAIL;
++	
++	rtw_buf_update(&pmlmepriv->auth_rsp, 
++		&pmlmepriv->auth_rsp_len, pframe, len);
++	pft_roam->ft_event.ies =
++		(pmlmepriv->auth_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6);
++	pft_roam->ft_event.ies_len =
++		(pmlmepriv->auth_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6);
++
++	/*Not support RIC*/
++	pft_roam->ft_event.ric_ies =  NULL;
++	pft_roam->ft_event.ric_ies_len =  0;
++	_rtw_memcpy(target_ap_addr, pmlmepriv->assoc_bssid, ETH_ALEN);
++	rtw_ft_report_reassoc_evt(padapter, target_ap_addr);
++
++	return ret;	
++}
++
++static void rtw_ft_start_clnt_action(_adapter *padapter, u8 *pTargetAddr)
++{
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++	rtw_ft_set_status(padapter, RTW_FT_REQUESTING_STA);
++	rtw_ft_issue_action_req(padapter, pTargetAddr);
++	_set_timer(&pmlmeext->ft_link_timer, REASSOC_TO);
++}
++
++void rtw_ft_start_roam(_adapter *padapter, u8 *pTargetAddr)
++{
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++	if (rtw_ft_otd_roam(padapter)) {
++		RTW_FT_INFO("%s : try OTD roaming\n", __func__);
++		rtw_ft_start_clnt_action(padapter, pTargetAddr);
++	} else {
++		/*wait a little time to retrieve packets buffered in the current ap while scan*/
++		RTW_FT_INFO("%s : start roaming timer\n", __func__);
++		_set_timer(&pmlmeext->ft_roam_timer, 30);
++	}
++}
++
++void rtw_ft_issue_action_req(_adapter *padapter, u8 *pTargetAddr)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct xmit_frame *pmgntframe;
++	struct rtw_ieee80211_hdr *pwlanhdr;
++	struct pkt_attrib *pattrib;
++	u8 *pframe;
++	u8 category = RTW_WLAN_CATEGORY_FT;
++	u8 action = RTW_WLAN_ACTION_FT_REQ;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++	pwlanhdr->frame_ctl = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++
++	_rtw_memcpy(pframe, adapter_mac_addr(padapter), ETH_ALEN);
++	pframe += ETH_ALEN;
++	pattrib->pktlen += ETH_ALEN;
++
++	_rtw_memcpy(pframe, pTargetAddr, ETH_ALEN);
++	pframe += ETH_ALEN;
++	pattrib->pktlen += ETH_ALEN;
++
++	rtw_ft_update_mdie(padapter, pattrib, &pframe);
++	if (rtw_ft_update_rsnie(padapter, _TRUE, pattrib, &pframe))
++		rtw_ft_update_ftie(padapter, pattrib, &pframe);
++
++	RTW_INFO("FT : issue RTW_WLAN_ACTION_FT_REQ\n");
++	pattrib->last_txcmdsz = pattrib->pktlen;
++	dump_mgntframe(padapter, pmgntframe);
++}
++
++void rtw_ft_report_evt(_adapter *padapter)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&(pmlmeinfo->network);
++	struct cfg80211_ft_event_params ft_evt_parms;
++	_irqL irqL;
++
++	_rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms));
++	rtw_ft_update_stainfo(padapter, pnetwork);
++
++	if (!pnetwork)
++		goto err_2;
++
++	ft_evt_parms.ies_len = pft_roam->ft_event.ies_len;
++	ft_evt_parms.ies =  rtw_zmalloc(ft_evt_parms.ies_len);
++	if (ft_evt_parms.ies)
++		_rtw_memcpy((void *)ft_evt_parms.ies, pft_roam->ft_event.ies, ft_evt_parms.ies_len);
++	 else
++		goto err_2;
++
++	ft_evt_parms.target_ap = rtw_zmalloc(ETH_ALEN);
++	if (ft_evt_parms.target_ap)
++		_rtw_memcpy((void *)ft_evt_parms.target_ap, pnetwork->MacAddress, ETH_ALEN);
++	else
++		goto err_1;
++
++	ft_evt_parms.ric_ies = pft_roam->ft_event.ric_ies;
++	ft_evt_parms.ric_ies_len = pft_roam->ft_event.ric_ies_len;
++
++	/* It's a KERNEL issue between v4.11 ~ v4.16, 
++	* <= v4.10, NLMSG_DEFAULT_SIZE is used for nlmsg_new().
++	* v4.11 ~ v4.16, only used "100 + >ric_ies_len" for nlmsg_new() 
++	*	even then DRIVER don't support RIC.
++	* >= v4.17, issue should correct as "100 + ies_len + ric_ies_len".
++	*/	
++	#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)) && \
++	(LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0)))
++		ft_evt_parms.ric_ies_len = (ft_evt_parms.ies_len <= 100 )?
++			(0):(ft_evt_parms.ies_len - 100);
++	#endif
++	
++	rtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA, &irqL);
++	rtw_cfg80211_ft_event(padapter, &ft_evt_parms);
++	RTW_INFO("FT: rtw_ft_report_evt\n");
++	rtw_mfree((u8 *)pft_roam->ft_event.target_ap, ETH_ALEN);
++err_1:
++	rtw_mfree((u8 *)ft_evt_parms.ies, ft_evt_parms.ies_len);
++err_2:
++	return;
++}
++
++void rtw_ft_report_reassoc_evt(_adapter *padapter, u8 *pMacAddr)
++{
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++	struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
++	struct cmd_obj *pcmd_obj = NULL;
++	struct stassoc_event *passoc_sta_evt = NULL;
++	struct rtw_evt_header *evt_hdr = NULL;
++	u8 *pevtcmd = NULL;
++	u32 cmdsz = 0;
++
++	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (pcmd_obj == NULL)
++		return;
++
++	cmdsz = (sizeof(struct stassoc_event) + sizeof(struct rtw_evt_header));
++	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
++	if (pevtcmd == NULL) {
++		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
++		return;
++	}
++
++	_rtw_init_listhead(&pcmd_obj->list);
++	pcmd_obj->cmdcode = CMD_SET_MLME_EVT;
++	pcmd_obj->cmdsz = cmdsz;
++	pcmd_obj->parmbuf = pevtcmd;
++	pcmd_obj->rsp = NULL;
++	pcmd_obj->rspsz  = 0;
++
++	evt_hdr = (struct rtw_evt_header *)(pevtcmd);
++	evt_hdr->len = sizeof(struct stassoc_event);
++	evt_hdr->id = EVT_FT_REASSOC;
++	evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
++
++	passoc_sta_evt = (struct stassoc_event *)(pevtcmd + sizeof(struct rtw_evt_header));
++	_rtw_memcpy((unsigned char *)(&(passoc_sta_evt->macaddr)), pMacAddr, ETH_ALEN);
++	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
++}
++
++void rtw_ft_link_timer_hdl(void *ctx)
++{
++	_adapter *padapter = (_adapter *)ctx;
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
++
++	if (rtw_ft_chk_status(padapter, RTW_FT_REQUESTING_STA)) {
++		if (pft_roam->ft_req_retry_cnt < RTW_FT_ACTION_REQ_LMT) {
++			pft_roam->ft_req_retry_cnt++;
++			rtw_ft_issue_action_req(padapter, (u8 *)pmlmepriv->roam_network->network.MacAddress);
++			_set_timer(&pmlmeext->ft_link_timer, REASSOC_TO);
++		} else {
++			pft_roam->ft_req_retry_cnt = 0;	
++			if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
++				rtw_ft_set_status(padapter, RTW_FT_ASSOCIATED_STA);
++			else
++				rtw_ft_reset_status(padapter);
++		}
++	}
++}
++
++void rtw_ft_roam_timer_hdl(void *ctx)
++{
++	_adapter *padapter = (_adapter *)ctx;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++	RTW_FT_INFO("%s : try roaming\n", __func__);
++	receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress
++				, WLAN_REASON_ACTIVE_ROAM, _FALSE);
++}
++
++void rtw_ft_roam_status_reset(_adapter *padapter)
++{
++	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
++
++	if ((rtw_to_roam(padapter) > 0) && 
++		(!rtw_ft_chk_status(padapter, RTW_FT_REQUESTED_STA))) {
++		rtw_ft_reset_status(padapter);
++	}	
++	
++	padapter->mlmepriv.ft_roam.ft_updated_bcn = _FALSE;
++}
++
++#endif /* CONFIG_RTW_80211R */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_ieee80211.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_ieee80211.c
+new file mode 100644
+index 000000000..9d1033bb4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_ieee80211.c
+@@ -0,0 +1,3090 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _IEEE80211_C
++
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++	#include <linux/fs.h>
++#endif
++#include <drv_types.h>
++
++
++u8 RTW_WPA_OUI_TYPE[] = { 0x00, 0x50, 0xf2, 1 };
++u16 RTW_WPA_VERSION = 1;
++u8 WPA_AUTH_KEY_MGMT_NONE[] = { 0x00, 0x50, 0xf2, 0 };
++u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[] = { 0x00, 0x50, 0xf2, 1 };
++u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[] = { 0x00, 0x50, 0xf2, 2 };
++u8 WPA_CIPHER_SUITE_NONE[] = { 0x00, 0x50, 0xf2, 0 };
++u8 WPA_CIPHER_SUITE_WEP40[] = { 0x00, 0x50, 0xf2, 1 };
++u8 WPA_CIPHER_SUITE_TKIP[] = { 0x00, 0x50, 0xf2, 2 };
++u8 WPA_CIPHER_SUITE_WRAP[] = { 0x00, 0x50, 0xf2, 3 };
++u8 WPA_CIPHER_SUITE_CCMP[] = { 0x00, 0x50, 0xf2, 4 };
++u8 WPA_CIPHER_SUITE_WEP104[] = { 0x00, 0x50, 0xf2, 5 };
++
++u16 RSN_VERSION_BSD = 1;
++u8 RSN_CIPHER_SUITE_NONE[] = { 0x00, 0x0f, 0xac, 0 };
++u8 RSN_CIPHER_SUITE_WEP40[] = { 0x00, 0x0f, 0xac, 1 };
++u8 RSN_CIPHER_SUITE_TKIP[] = { 0x00, 0x0f, 0xac, 2 };
++u8 RSN_CIPHER_SUITE_WRAP[] = { 0x00, 0x0f, 0xac, 3 };
++u8 RSN_CIPHER_SUITE_CCMP[] = { 0x00, 0x0f, 0xac, 4 };
++u8 RSN_CIPHER_SUITE_AES_128_CMAC[] = { 0x00, 0x0f, 0xac, 6 };
++u8 RSN_CIPHER_SUITE_GCMP[] = { 0x00, 0x0f, 0xac, 8 };
++u8 RSN_CIPHER_SUITE_GCMP_256[] = { 0x00, 0x0f, 0xac, 9 };
++u8 RSN_CIPHER_SUITE_CCMP_256[] = { 0x00, 0x0f, 0xac, 10 };
++u8 RSN_CIPHER_SUITE_BIP_GMAC_128[] = { 0x00, 0x0f, 0xac, 11 };
++u8 RSN_CIPHER_SUITE_BIP_GMAC_256[] = { 0x00, 0x0f, 0xac, 12 };
++u8 RSN_CIPHER_SUITE_BIP_CMAC_256[] = { 0x00, 0x0f, 0xac, 13 };
++u8 RSN_CIPHER_SUITE_WEP104[] = { 0x00, 0x0f, 0xac, 5 };
++
++u8 WLAN_AKM_8021X[] = {0x00, 0x0f, 0xac, 1};
++u8 WLAN_AKM_PSK[] = {0x00, 0x0f, 0xac, 2};
++u8 WLAN_AKM_FT_8021X[] = {0x00, 0x0f, 0xac, 3};
++u8 WLAN_AKM_FT_PSK[] = {0x00, 0x0f, 0xac, 4};
++u8 WLAN_AKM_8021X_SHA256[] = {0x00, 0x0f, 0xac, 5};
++u8 WLAN_AKM_PSK_SHA256[] = {0x00, 0x0f, 0xac, 6};
++u8 WLAN_AKM_TDLS[] = {0x00, 0x0f, 0xac, 7};
++u8 WLAN_AKM_SAE[] = {0x00, 0x0f, 0xac, 8};
++u8 WLAN_AKM_FT_OVER_SAE[] = {0x00, 0x0f, 0xac, 9};
++u8 WLAN_AKM_8021X_SUITE_B[] = {0x00, 0x0f, 0xac, 11};
++u8 WLAN_AKM_8021X_SUITE_B_192[] = {0x00, 0x0f, 0xac, 12};
++u8 WLAN_AKM_FILS_SHA256[] = {0x00, 0x0f, 0xac, 14};
++u8 WLAN_AKM_FILS_SHA384[] = {0x00, 0x0f, 0xac, 15};
++u8 WLAN_AKM_FT_FILS_SHA256[] = {0x00, 0x0f, 0xac, 16};
++u8 WLAN_AKM_FT_FILS_SHA384[] = {0x00, 0x0f, 0xac, 17};
++/* -----------------------------------------------------------
++ * for adhoc-master to generate ie and provide supported-rate to fw
++ * ----------------------------------------------------------- */
++
++u8	WIFI_CCKRATES[] = {
++	(IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK),
++	(IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK),
++	(IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK),
++	(IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK)
++};
++
++u8	WIFI_OFDMRATES[] = {
++	(IEEE80211_OFDM_RATE_6MB),
++	(IEEE80211_OFDM_RATE_9MB),
++	(IEEE80211_OFDM_RATE_12MB),
++	(IEEE80211_OFDM_RATE_18MB),
++	(IEEE80211_OFDM_RATE_24MB),
++	IEEE80211_OFDM_RATE_36MB,
++	IEEE80211_OFDM_RATE_48MB,
++	IEEE80211_OFDM_RATE_54MB
++};
++
++u8 mgn_rates_cck[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
++u8 mgn_rates_ofdm[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M};
++u8 mgn_rates_mcs0_7[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7};
++u8 mgn_rates_mcs8_15[8] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15};
++u8 mgn_rates_mcs16_23[8] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23};
++u8 mgn_rates_mcs24_31[8] = {MGN_MCS24, MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29, MGN_MCS30, MGN_MCS31};
++u8 mgn_rates_vht1ss[10] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4
++	, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9
++			  };
++u8 mgn_rates_vht2ss[10] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4
++	, MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9
++			  };
++u8 mgn_rates_vht3ss[10] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4
++	, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9
++			  };
++u8 mgn_rates_vht4ss[10] = {MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4
++	, MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9
++			  };
++
++RATE_SECTION mgn_rate_to_rs(enum MGN_RATE rate)
++{
++	RATE_SECTION rs = RATE_SECTION_NUM;
++
++	if (IS_CCK_RATE(rate))
++		rs = CCK;
++	else if (IS_OFDM_RATE(rate))
++		rs = OFDM;
++	else if (IS_HT1SS_RATE(rate))
++		rs = HT_1SS;
++	else if (IS_HT2SS_RATE(rate))
++		rs = HT_2SS;
++	else if (IS_HT3SS_RATE(rate))
++		rs = HT_3SS;
++	else if (IS_HT4SS_RATE(rate))
++		rs = HT_4SS;
++	else if (IS_VHT1SS_RATE(rate))
++		rs = VHT_1SS;
++	else if (IS_VHT2SS_RATE(rate))
++		rs = VHT_2SS;
++	else if (IS_VHT3SS_RATE(rate))
++		rs = VHT_3SS;
++	else if (IS_VHT4SS_RATE(rate))
++		rs = VHT_4SS;
++
++	return rs;
++}
++
++static const char *const _rate_section_str[] = {
++	"CCK",
++	"OFDM",
++	"HT_1SS",
++	"HT_2SS",
++	"HT_3SS",
++	"HT_4SS",
++	"VHT_1SS",
++	"VHT_2SS",
++	"VHT_3SS",
++	"VHT_4SS",
++	"RATE_SECTION_UNKNOWN",
++};
++
++const char *rate_section_str(u8 section)
++{
++	section = (section >= RATE_SECTION_NUM) ? RATE_SECTION_NUM : section;
++	return _rate_section_str[section];
++}
++
++struct rate_section_ent rates_by_sections[RATE_SECTION_NUM] = {
++	{RF_1TX, 4, mgn_rates_cck},
++	{RF_1TX, 8, mgn_rates_ofdm},
++	{RF_1TX, 8, mgn_rates_mcs0_7},
++	{RF_2TX, 8, mgn_rates_mcs8_15},
++	{RF_3TX, 8, mgn_rates_mcs16_23},
++	{RF_4TX, 8, mgn_rates_mcs24_31},
++	{RF_1TX, 10, mgn_rates_vht1ss},
++	{RF_2TX, 10, mgn_rates_vht2ss},
++	{RF_3TX, 10, mgn_rates_vht3ss},
++	{RF_4TX, 10, mgn_rates_vht4ss},
++};
++
++int rtw_get_bit_value_from_ieee_value(u8 val)
++{
++	unsigned char dot11_rate_table[] = {2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108, 0}; /* last element must be zero!! */
++
++	int i = 0;
++	while (dot11_rate_table[i] != 0) {
++		if (dot11_rate_table[i] == val)
++			return BIT(i);
++		i++;
++	}
++	return 0;
++}
++uint rtw_get_cckrate_size(u8 *rate, u32 rate_length)
++{
++	int i = 0;
++	while(i < rate_length){
++		RTW_DBG("%s, rate[%d]=%u\n", __FUNCTION__, i, rate[i]);
++		if (((rate[i] & 0x7f) == 2) || ((rate[i] & 0x7f) == 4) ||
++			((rate[i] & 0x7f) == 11)  || ((rate[i] & 0x7f) == 22))
++			i++;
++		else
++			break;
++	}
++	return i;
++}
++
++uint	rtw_is_cckrates_included(u8 *rate)
++{
++	u32	i = 0;
++
++	while (rate[i] != 0) {
++		if ((((rate[i]) & 0x7f) == 2)	|| (((rate[i]) & 0x7f) == 4) ||
++		    (((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) == 22))
++			return _TRUE;
++		i++;
++	}
++
++	return _FALSE;
++}
++
++uint	rtw_is_cckratesonly_included(u8 *rate)
++{
++	u32 i = 0;
++
++
++	while (rate[i] != 0) {
++		if ((((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) &&
++		    (((rate[i]) & 0x7f) != 11)  && (((rate[i]) & 0x7f) != 22))
++			return _FALSE;
++
++		i++;
++	}
++
++	return _TRUE;
++
++}
++
++int rtw_check_network_type(unsigned char *rate, int ratelen, int channel)
++{
++	if (channel > 14) {
++		if ((rtw_is_cckrates_included(rate)) == _TRUE)
++			return WIRELESS_INVALID;
++		else
++			return WIRELESS_11A;
++	} else { /* could be pure B, pure G, or B/G */
++		if ((rtw_is_cckratesonly_included(rate)) == _TRUE)
++			return WIRELESS_11B;
++		else if ((rtw_is_cckrates_included(rate)) == _TRUE)
++			return	WIRELESS_11BG;
++		else
++			return WIRELESS_11G;
++	}
++
++}
++
++u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source,
++		     unsigned int *frlen)
++{
++	_rtw_memcpy((void *)pbuf, (void *)source, len);
++	*frlen = *frlen + len;
++	return pbuf + len;
++}
++
++/* rtw_set_ie will update frame length */
++u8 *rtw_set_ie
++(
++	u8 *pbuf,
++	sint index,
++	uint len,
++	const u8 *source,
++	uint *frlen /* frame length */
++)
++{
++	*pbuf = (u8)index;
++
++	*(pbuf + 1) = (u8)len;
++
++	if (len > 0)
++		_rtw_memcpy((void *)(pbuf + 2), (void *)source, len);
++
++	if (frlen)
++		*frlen = *frlen + (len + 2);
++
++	return pbuf + len + 2;
++}
++
++inline u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode,
++				u8 new_ch, u8 ch_switch_cnt)
++{
++	u8 ie_data[3];
++
++	ie_data[0] = ch_switch_mode;
++	ie_data[1] = new_ch;
++	ie_data[2] = ch_switch_cnt;
++	return rtw_set_ie(buf, WLAN_EID_CHANNEL_SWITCH,  3, ie_data, buf_len);
++}
++
++inline u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset)
++{
++	if (ch_offset == SCN)
++		return HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++	else if (ch_offset == SCA)
++		return HAL_PRIME_CHNL_OFFSET_LOWER;
++	else if (ch_offset == SCB)
++		return HAL_PRIME_CHNL_OFFSET_UPPER;
++
++	return HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++}
++
++inline u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset)
++{
++	if (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
++		return SCN;
++	else if (ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
++		return SCA;
++	else if (ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
++		return SCB;
++
++	return SCN;
++}
++
++inline u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset)
++{
++	return rtw_set_ie(buf, WLAN_EID_SECONDARY_CHANNEL_OFFSET,  1, &secondary_ch_offset, buf_len);
++}
++
++inline u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl,
++		u8 flags, u16 reason, u16 precedence)
++{
++	u8 ie_data[6];
++
++	ie_data[0] = ttl;
++	ie_data[1] = flags;
++	RTW_PUT_LE16((u8 *)&ie_data[2], reason);
++	RTW_PUT_LE16((u8 *)&ie_data[4], precedence);
++
++	return rtw_set_ie(buf, 0x118,  6, ie_data, buf_len);
++}
++
++/*----------------------------------------------------------------------------
++index: the information element id index, limit is the limit for search
++-----------------------------------------------------------------------------*/
++u8 *rtw_get_ie(const u8 *pbuf, sint index, sint *len, sint limit)
++{
++	sint tmp, i;
++	const u8 *p;
++	if (limit < 1) {
++		return NULL;
++	}
++
++	p = pbuf;
++	i = 0;
++	*len = 0;
++	while (1) {
++		if (*p == index) {
++			*len = *(p + 1);
++			return (u8 *)p;
++		} else {
++			tmp = *(p + 1);
++			p += (tmp + 2);
++			i += (tmp + 2);
++		}
++		if (i >= limit)
++			break;
++	}
++	return NULL;
++}
++
++/**
++ * rtw_get_ie_ex - Search specific IE from a series of IEs
++ * @in_ie: Address of IEs to search
++ * @in_len: Length limit from in_ie
++ * @eid: Element ID to match
++ * @oui: OUI to match
++ * @oui_len: OUI length
++ * @ie: If not NULL and the specific IE is found, the IE will be copied to the buf starting from the specific IE
++ * @ielen: If not NULL and the specific IE is found, will set to the length of the entire IE
++ *
++ * Returns: The address of the specific IE found, or NULL
++ */
++u8 *rtw_get_ie_ex(const u8 *in_ie, uint in_len, u8 eid, const u8 *oui, u8 oui_len, u8 *ie, uint *ielen)
++{
++	uint cnt;
++	const u8 *target_ie = NULL;
++
++
++	if (ielen)
++		*ielen = 0;
++
++	if (!in_ie || in_len <= 0)
++		return (u8 *)target_ie;
++
++	cnt = 0;
++
++	while (cnt < in_len) {
++		if (eid == in_ie[cnt]
++		    && (!oui || _rtw_memcmp(&in_ie[cnt + 2], oui, oui_len) == _TRUE)) {
++			target_ie = &in_ie[cnt];
++
++			if (ie)
++				_rtw_memcpy(ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
++
++			if (ielen)
++				*ielen = in_ie[cnt + 1] + 2;
++
++			break;
++		} else {
++			cnt += in_ie[cnt + 1] + 2; /* goto next	 */
++		}
++
++	}
++
++	return (u8 *)target_ie;
++}
++
++/**
++ * rtw_ies_remove_ie - Find matching IEs and remove
++ * @ies: Address of IEs to search
++ * @ies_len: Pointer of length of ies, will update to new length
++ * @offset: The offset to start scarch
++ * @eid: Element ID to match
++ * @oui: OUI to match
++ * @oui_len: OUI length
++ *
++ * Returns: _SUCCESS: ies is updated, _FAIL: not updated
++ */
++int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len)
++{
++	int ret = _FAIL;
++	u8 *target_ie;
++	u32 target_ielen;
++	u8 *start;
++	uint search_len;
++
++	if (!ies || !ies_len || *ies_len <= offset)
++		goto exit;
++
++	start = ies + offset;
++	search_len = *ies_len - offset;
++
++	while (1) {
++		target_ie = rtw_get_ie_ex(start, search_len, eid, oui, oui_len, NULL, &target_ielen);
++		if (target_ie && target_ielen) {
++			u8 *remain_ies = target_ie + target_ielen;
++			uint remain_len = search_len - (remain_ies - start);
++
++			_rtw_memmove(target_ie, remain_ies, remain_len);
++			*ies_len = *ies_len - target_ielen;
++			ret = _SUCCESS;
++
++			start = target_ie;
++			search_len = remain_len;
++		} else
++			break;
++	}
++exit:
++	return ret;
++}
++
++void rtw_set_supported_rate(u8 *SupportedRates, uint mode)
++{
++
++	_rtw_memset(SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX);
++
++	switch (mode) {
++	case WIRELESS_11B:
++		_rtw_memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN);
++		break;
++
++	case WIRELESS_11G:
++	case WIRELESS_11A:
++	case WIRELESS_11_5N:
++	case WIRELESS_11A_5N: /* Todo: no basic rate for ofdm ? */
++	case WIRELESS_11_5AC:
++		_rtw_memcpy(SupportedRates, WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN);
++		break;
++
++	case WIRELESS_11BG:
++	case WIRELESS_11G_24N:
++	case WIRELESS_11_24N:
++	case WIRELESS_11BG_24N:
++		_rtw_memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN);
++		_rtw_memcpy(SupportedRates + IEEE80211_CCK_RATE_LEN, WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN);
++		break;
++
++	}
++}
++
++void rtw_filter_suppport_rateie(WLAN_BSSID_EX *pbss_network, u8 keep)
++{
++	u8 i, idx = 0, new_rate[NDIS_802_11_LENGTH_RATES_EX], *p;
++	uint iscck, isofdm, ie_orilen = 0, remain_len;
++	u8 *remain_ies;
++
++	p = rtw_get_ie(pbss_network->IEs + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &ie_orilen, (pbss_network->IELength - _BEACON_IE_OFFSET_));
++	if (!p)
++		return;
++
++	_rtw_memset(new_rate, 0, NDIS_802_11_LENGTH_RATES_EX);
++	for (i=0; i < ie_orilen; i++) {
++		iscck = rtw_is_cck_rate(p[i+2]);
++		isofdm= rtw_is_ofdm_rate(p[i+2]);
++		if (((keep == CCK) && iscck)
++			|| ((keep == OFDM) && isofdm))
++			new_rate[idx++]= rtw_is_basic_rate_ofdm(p[i+2]) ? p[i+2]|IEEE80211_BASIC_RATE_MASK : p[i+2];
++	}
++	/*	update rate ie	*/
++	p[1] = idx;
++	_rtw_memcpy(p+2, new_rate, idx);
++	/*	update remain ie & IELength*/
++	remain_ies = p + 2 + ie_orilen;
++	remain_len = pbss_network->IELength - (remain_ies - pbss_network->IEs);
++	_rtw_memmove(p+2+idx, remain_ies, remain_len);
++	pbss_network->IELength -= (ie_orilen - idx);
++}
++ 
++
++/*
++	Adjust those items by given wireless_mode
++		1. pbss_network->IELength
++		2. pbss_network->IE (SUPPORTRATE & EXT_SUPPORTRATE)
++		3. pbss_network->SupportedRates
++*/
++
++u8 rtw_update_rate_bymode(WLAN_BSSID_EX *pbss_network, u32 mode)
++{
++	u8 network_type, *p, *ie = pbss_network->IEs;
++	sint ie_len;
++	uint network_ielen = pbss_network->IELength;
++
++	if (mode == WIRELESS_11B) {
++		/*only keep CCK in support_rate IE and remove whole ext_support_rate IE*/
++		rtw_filter_suppport_rateie(pbss_network, CCK);
++		p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ie_len, pbss_network->IELength - _BEACON_IE_OFFSET_);
++		if (p) {
++			rtw_ies_remove_ie(ie , &network_ielen, _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, NULL, 0);
++			pbss_network->IELength -= ie_len;
++		}
++		network_type = WIRELESS_11B;
++	} else if ((mode & WIRELESS_11B) == 0) {
++		/* Remove CCK in support_rate IE */
++		rtw_filter_suppport_rateie(pbss_network, OFDM);
++		if (pbss_network->Configuration.DSConfig > 14)
++			network_type = WIRELESS_11A;
++		else
++			network_type = WIRELESS_11G;
++	} else
++		network_type = WIRELESS_11BG;		/*	do nothing	*/
++
++	rtw_set_supported_rate(pbss_network->SupportedRates, network_type);
++	return network_type;
++}
++
++uint	rtw_get_rateset_len(u8	*rateset)
++{
++	uint i = 0;
++	while (1) {
++		if ((rateset[i]) == 0)
++			break;
++
++		if (i > 12)
++			break;
++
++		i++;
++	}
++	return i;
++}
++
++int rtw_generate_ie(struct registry_priv *pregistrypriv)
++{
++	u8	wireless_mode;
++	int	sz = 0, rateLen;
++	WLAN_BSSID_EX	*pdev_network = &pregistrypriv->dev_network;
++	u8	*ie = pdev_network->IEs;
++
++
++	/* timestamp will be inserted by hardware */
++	sz += 8;
++	ie += sz;
++
++	/* beacon interval : 2bytes */
++	*(u16 *)ie = cpu_to_le16((u16)pdev_network->Configuration.BeaconPeriod); /* BCN_INTERVAL; */
++	sz += 2;
++	ie += 2;
++
++	/* capability info */
++	*(u16 *)ie = 0;
++
++	*(u16 *)ie |= cpu_to_le16(cap_IBSS);
++
++	if (pregistrypriv->preamble == PREAMBLE_SHORT)
++		*(u16 *)ie |= cpu_to_le16(cap_ShortPremble);
++
++	if (pdev_network->Privacy)
++		*(u16 *)ie |= cpu_to_le16(cap_Privacy);
++
++	sz += 2;
++	ie += 2;
++
++	/* SSID */
++	ie = rtw_set_ie(ie, _SSID_IE_, pdev_network->Ssid.SsidLength, pdev_network->Ssid.Ssid, &sz);
++
++	/* supported rates */
++	if (pregistrypriv->wireless_mode == WIRELESS_11ABGN) {
++		if (pdev_network->Configuration.DSConfig > 14)
++			wireless_mode = WIRELESS_11A_5N;
++		else
++			wireless_mode = WIRELESS_11BG_24N;
++	} else if (pregistrypriv->wireless_mode == WIRELESS_MODE_MAX) { /* WIRELESS_11ABGN | WIRELESS_11AC */
++		if (pdev_network->Configuration.DSConfig > 14)
++			wireless_mode = WIRELESS_11_5AC;
++		else
++			wireless_mode = WIRELESS_11BG_24N;
++	} else
++		wireless_mode = pregistrypriv->wireless_mode;
++
++	rtw_set_supported_rate(pdev_network->SupportedRates, wireless_mode) ;
++
++	rateLen = rtw_get_rateset_len(pdev_network->SupportedRates);
++
++	if (rateLen > 8) {
++		ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, 8, pdev_network->SupportedRates, &sz);
++		/* ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz); */
++	} else
++		ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, rateLen, pdev_network->SupportedRates, &sz);
++
++	/* DS parameter set */
++	ie = rtw_set_ie(ie, _DSSET_IE_, 1, (u8 *)&(pdev_network->Configuration.DSConfig), &sz);
++
++
++	/* IBSS Parameter Set */
++
++	ie = rtw_set_ie(ie, _IBSS_PARA_IE_, 2, (u8 *)&(pdev_network->Configuration.ATIMWindow), &sz);
++
++	if (rateLen > 8)
++		ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz);
++
++#ifdef CONFIG_80211N_HT
++	/* HT Cap. */
++	if (is_supported_ht(pregistrypriv->wireless_mode)
++	    && (pregistrypriv->ht_enable == _TRUE)) {
++		/* todo: */
++	}
++#endif /* CONFIG_80211N_HT */
++
++	/* pdev_network->IELength =  sz; */ /* update IELength */
++
++
++	/* return _SUCCESS; */
++
++	return sz;
++
++}
++
++unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit)
++{
++	int len;
++	u16 val16;
++	unsigned char wpa_oui_type[] = {0x00, 0x50, 0xf2, 0x01};
++	u8 *pbuf = pie;
++	int limit_new = limit;
++
++	while (1) {
++		pbuf = rtw_get_ie(pbuf, _WPA_IE_ID_, &len, limit_new);
++
++		if (pbuf) {
++
++			/* check if oui matches... */
++			if (_rtw_memcmp((pbuf + 2), wpa_oui_type, sizeof(wpa_oui_type)) == _FALSE)
++
++				goto check_next_ie;
++
++			/* check version... */
++			_rtw_memcpy((u8 *)&val16, (pbuf + 6), sizeof(val16));
++
++			val16 = le16_to_cpu(val16);
++			if (val16 != 0x0001)
++				goto check_next_ie;
++
++			*wpa_ie_len = *(pbuf + 1);
++
++			return pbuf;
++
++		} else {
++
++			*wpa_ie_len = 0;
++			return NULL;
++		}
++
++check_next_ie:
++
++		limit_new = limit - (pbuf - pie) - 2 - len;
++
++		if (limit_new <= 0)
++			break;
++
++		pbuf += (2 + len);
++
++	}
++
++	*wpa_ie_len = 0;
++
++	return NULL;
++
++}
++
++unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit)
++{
++
++	return rtw_get_ie(pie, _WPA2_IE_ID_, rsn_ie_len, limit);
++
++}
++
++int rtw_get_wpa_cipher_suite(u8 *s)
++{
++	if (_rtw_memcmp(s, WPA_CIPHER_SUITE_NONE, WPA_SELECTOR_LEN) == _TRUE)
++		return WPA_CIPHER_NONE;
++	if (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP40, WPA_SELECTOR_LEN) == _TRUE)
++		return WPA_CIPHER_WEP40;
++	if (_rtw_memcmp(s, WPA_CIPHER_SUITE_TKIP, WPA_SELECTOR_LEN) == _TRUE)
++		return WPA_CIPHER_TKIP;
++	if (_rtw_memcmp(s, WPA_CIPHER_SUITE_CCMP, WPA_SELECTOR_LEN) == _TRUE)
++		return WPA_CIPHER_CCMP;
++	if (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP104, WPA_SELECTOR_LEN) == _TRUE)
++		return WPA_CIPHER_WEP104;
++
++	return 0;
++}
++
++int rtw_get_rsn_cipher_suite(u8 *s)
++{
++	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_NONE, RSN_SELECTOR_LEN) == _TRUE)
++		return WPA_CIPHER_NONE;
++	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP40, RSN_SELECTOR_LEN) == _TRUE)
++		return WPA_CIPHER_WEP40;
++	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_TKIP, RSN_SELECTOR_LEN) == _TRUE)
++		return WPA_CIPHER_TKIP;
++	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_CCMP, RSN_SELECTOR_LEN) == _TRUE)
++		return WPA_CIPHER_CCMP;
++	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_GCMP, RSN_SELECTOR_LEN) == _TRUE)
++		return WPA_CIPHER_GCMP;
++	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_GCMP_256, RSN_SELECTOR_LEN) == _TRUE)
++		return WPA_CIPHER_GCMP_256;
++	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_CCMP_256, RSN_SELECTOR_LEN) == _TRUE)
++		return WPA_CIPHER_CCMP_256;
++	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP104, RSN_SELECTOR_LEN) == _TRUE)
++		return WPA_CIPHER_WEP104;
++	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_AES_128_CMAC, RSN_SELECTOR_LEN) == _TRUE)
++		return WPA_CIPHER_BIP_CMAC_128;
++	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_BIP_GMAC_128, RSN_SELECTOR_LEN) == _TRUE)
++		return WPA_CIPHER_BIP_GMAC_128;
++	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_BIP_GMAC_256, RSN_SELECTOR_LEN) == _TRUE)
++		return WPA_CIPHER_BIP_GMAC_256;
++	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_BIP_CMAC_256, RSN_SELECTOR_LEN) == _TRUE)
++		return WPA_CIPHER_BIP_CMAC_256;
++	return 0;
++}
++
++u32 rtw_get_akm_suite_bitmap(u8 *s)
++{
++	if (_rtw_memcmp(s, WLAN_AKM_8021X, RSN_SELECTOR_LEN) == _TRUE)
++		return WLAN_AKM_TYPE_8021X;
++	if (_rtw_memcmp(s, WLAN_AKM_PSK, RSN_SELECTOR_LEN) == _TRUE)
++		return WLAN_AKM_TYPE_PSK;
++	if (_rtw_memcmp(s, WLAN_AKM_FT_8021X, RSN_SELECTOR_LEN) == _TRUE)
++		return WLAN_AKM_TYPE_FT_8021X;
++	if (_rtw_memcmp(s, WLAN_AKM_FT_PSK, RSN_SELECTOR_LEN) == _TRUE)
++		return WLAN_AKM_TYPE_FT_PSK;
++	if (_rtw_memcmp(s, WLAN_AKM_8021X_SHA256, RSN_SELECTOR_LEN) == _TRUE)
++		return WLAN_AKM_TYPE_8021X_SHA256;
++	if (_rtw_memcmp(s, WLAN_AKM_PSK_SHA256, RSN_SELECTOR_LEN) == _TRUE)
++		return WLAN_AKM_TYPE_PSK_SHA256;
++	if (_rtw_memcmp(s, WLAN_AKM_TDLS, RSN_SELECTOR_LEN) == _TRUE)
++		return WLAN_AKM_TYPE_TDLS;
++	if (_rtw_memcmp(s, WLAN_AKM_SAE, RSN_SELECTOR_LEN) == _TRUE)
++		return WLAN_AKM_TYPE_SAE;
++	if (_rtw_memcmp(s, WLAN_AKM_FT_OVER_SAE, RSN_SELECTOR_LEN) == _TRUE)
++		return WLAN_AKM_TYPE_FT_OVER_SAE;
++	if (_rtw_memcmp(s, WLAN_AKM_8021X_SUITE_B, RSN_SELECTOR_LEN) == _TRUE)
++		return WLAN_AKM_TYPE_8021X_SUITE_B;
++	if (_rtw_memcmp(s, WLAN_AKM_8021X_SUITE_B_192, RSN_SELECTOR_LEN) == _TRUE)
++		return WLAN_AKM_TYPE_8021X_SUITE_B_192;
++	if (_rtw_memcmp(s, WLAN_AKM_FILS_SHA256, RSN_SELECTOR_LEN) == _TRUE)
++		return WLAN_AKM_TYPE_FILS_SHA256;
++	if (_rtw_memcmp(s, WLAN_AKM_FILS_SHA384, RSN_SELECTOR_LEN) == _TRUE)
++		return WLAN_AKM_TYPE_FILS_SHA384;
++	if (_rtw_memcmp(s, WLAN_AKM_FT_FILS_SHA256, RSN_SELECTOR_LEN) == _TRUE)
++		return WLAN_AKM_TYPE_FT_FILS_SHA256;
++	if (_rtw_memcmp(s, WLAN_AKM_FT_FILS_SHA384, RSN_SELECTOR_LEN) == _TRUE)
++		return WLAN_AKM_TYPE_FT_FILS_SHA384;
++
++	return 0;
++}
++
++int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher,
++	int *pairwise_cipher, u32 *akm)
++{
++	int i, ret = _SUCCESS;
++	int left, count;
++	u8 *pos;
++	u8 SUITE_1X[4] = {0x00, 0x50, 0xf2, 1};
++
++	if (wpa_ie_len <= 0) {
++		/* No WPA IE - fail silently */
++		return _FAIL;
++	}
++
++
++	if ((*wpa_ie != _WPA_IE_ID_) || (*(wpa_ie + 1) != (u8)(wpa_ie_len - 2)) ||
++	    (_rtw_memcmp(wpa_ie + 2, RTW_WPA_OUI_TYPE, WPA_SELECTOR_LEN) != _TRUE))
++		return _FAIL;
++
++	pos = wpa_ie;
++
++	pos += 8;
++	left = wpa_ie_len - 8;
++
++
++	/* group_cipher */
++	if (left >= WPA_SELECTOR_LEN) {
++
++		*group_cipher = rtw_get_wpa_cipher_suite(pos);
++
++		pos += WPA_SELECTOR_LEN;
++		left -= WPA_SELECTOR_LEN;
++
++	} else if (left > 0) {
++
++		return _FAIL;
++	}
++
++
++	/* pairwise_cipher */
++	if (left >= 2) {
++		/* count = le16_to_cpu(*(u16*)pos);	 */
++		count = RTW_GET_LE16(pos);
++		pos += 2;
++		left -= 2;
++
++		if (count == 0 || left < count * WPA_SELECTOR_LEN) {
++			return _FAIL;
++		}
++
++		for (i = 0; i < count; i++) {
++			*pairwise_cipher |= rtw_get_wpa_cipher_suite(pos);
++
++			pos += WPA_SELECTOR_LEN;
++			left -= WPA_SELECTOR_LEN;
++		}
++
++	} else if (left == 1) {
++		return _FAIL;
++	}
++
++	if (akm) {
++		if (left >= 6) {
++			pos += 2;
++			if (_rtw_memcmp(pos, SUITE_1X, 4) == 1) {
++				*akm = WLAN_AKM_TYPE_8021X;
++			}
++		}
++	}
++
++	return ret;
++
++}
++
++int rtw_rsne_info_parse(const u8 *ie, uint ie_len, struct rsne_info *info)
++{
++	const u8 *pos = ie;
++	u16 cnt;
++
++	_rtw_memset(info, 0, sizeof(struct rsne_info));
++
++	if (ie + ie_len < pos + 4)
++		goto err;
++
++	if (*ie != WLAN_EID_RSN || *(ie + 1) != ie_len - 2)
++		goto err;
++	pos += 2 + 2;
++
++	/* Group CS */
++	if (ie + ie_len < pos + 4) {
++		if (ie + ie_len != pos)
++			goto err;
++		goto exit;
++	}
++	info->gcs = (u8 *)pos;
++	pos += 4;
++
++	/* Pairwise CS */
++	if (ie + ie_len < pos + 2) {
++		if (ie + ie_len != pos)
++			goto err;
++		goto exit;
++	}
++	cnt = RTW_GET_LE16(pos);
++	pos += 2;
++	if (ie + ie_len < pos + 4 * cnt) {
++		if (ie + ie_len != pos)
++			goto err;
++		goto exit;
++	}
++	info->pcs_cnt = cnt;
++	info->pcs_list = (u8 *)pos;
++	pos += 4 * cnt;
++
++	/* AKM */
++	if (ie + ie_len < pos + 2) {
++		if (ie + ie_len != pos)
++			goto err;
++		goto exit;
++	}
++	cnt = RTW_GET_LE16(pos);
++	pos += 2;
++	if (ie + ie_len < pos + 4 * cnt) {
++		if (ie + ie_len != pos)
++			goto err;
++		goto exit;
++	}
++	info->akm_cnt = cnt;
++	info->akm_list = (u8 *)pos;
++	pos += 4 * cnt;
++
++	/* RSN cap */
++	if (ie + ie_len < pos + 2) {
++		if (ie + ie_len != pos)
++			goto err;
++		goto exit;
++	}
++	info->cap = (u8 *)pos;
++	pos += 2;
++
++	/* PMKID */
++	if (ie + ie_len < pos + 2) {
++		if (ie + ie_len != pos)
++			goto err;
++		goto exit;
++	}
++	cnt = RTW_GET_LE16(pos);
++	pos += 2;
++	if (ie + ie_len < pos + 16 * cnt) {
++		if (ie + ie_len != pos)
++			goto err;
++		goto exit;
++	}
++	info->pmkid_cnt = cnt;
++	info->pmkid_list = (u8 *)pos;
++	pos += 16 * cnt;
++
++	/* Group Mgmt CS */
++	if (ie + ie_len < pos + 4) {
++		if (ie + ie_len != pos)
++			goto err;
++		goto exit;
++	}
++	info->gmcs = (u8 *)pos;
++
++exit:
++	return _SUCCESS;
++
++err:
++	info->err = 1;
++	return _FAIL;
++}
++
++int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher,
++	int *pairwise_cipher, int *gmcs, u32 *akm, u8 *mfp_opt)
++{
++	struct rsne_info info;
++	int i, ret = _SUCCESS;
++
++	ret = rtw_rsne_info_parse(rsn_ie, rsn_ie_len, &info);
++	if (ret != _SUCCESS)
++		goto exit;
++
++	if (group_cipher) {
++		if (info.gcs)
++			*group_cipher = rtw_get_rsn_cipher_suite(info.gcs);
++		else
++			*group_cipher = 0;
++	}
++
++	if (pairwise_cipher) {
++		*pairwise_cipher = 0;
++		for (i = 0; i < info.pcs_cnt; i++)
++			*pairwise_cipher |= rtw_get_rsn_cipher_suite(info.pcs_list + 4 * i);
++	}
++
++	if (gmcs) {
++		if (info.gmcs)
++			*gmcs = rtw_get_rsn_cipher_suite(info.gmcs);
++		else
++			*gmcs = WPA_CIPHER_BIP_CMAC_128; /* default value when absent */
++	}
++
++	if (akm) {
++		*akm = 0;
++		for (i = 0; i < info.akm_cnt; i++)
++			*akm |= rtw_get_akm_suite_bitmap(info.akm_list + 4 * i);
++	}
++
++	if (mfp_opt) {
++		*mfp_opt = MFP_NO;
++		if (info.cap)
++			*mfp_opt = GET_RSN_CAP_MFP_OPTION(info.cap);
++	}
++
++exit:
++	return ret;
++}
++
++/* #ifdef CONFIG_WAPI_SUPPORT */
++int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len)
++{
++	int len = 0;
++	u8 authmode;
++	uint	cnt;
++	u8 wapi_oui1[4] = {0x0, 0x14, 0x72, 0x01};
++	u8 wapi_oui2[4] = {0x0, 0x14, 0x72, 0x02};
++
++
++	if (wapi_len)
++		*wapi_len = 0;
++
++	if (!in_ie || in_len <= 0)
++		return len;
++
++	cnt = (_TIMESTAMP_ + _BEACON_ITERVAL_ + _CAPABILITY_);
++
++	while (cnt < in_len) {
++		authmode = in_ie[cnt];
++
++		/* if(authmode==_WAPI_IE_) */
++		if (authmode == _WAPI_IE_ && (_rtw_memcmp(&in_ie[cnt + 6], wapi_oui1, 4) == _TRUE ||
++			_rtw_memcmp(&in_ie[cnt + 6], wapi_oui2, 4) == _TRUE)) {
++			if (wapi_ie)
++				_rtw_memcpy(wapi_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
++
++			if (wapi_len)
++				*wapi_len = in_ie[cnt + 1] + 2;
++
++			cnt += in_ie[cnt + 1] + 2; /* get next */
++		} else {
++			cnt += in_ie[cnt + 1] + 2; /* get next */
++		}
++	}
++
++	if (wapi_len)
++		len = *wapi_len;
++
++
++	return len;
++
++}
++/* #endif */
++
++int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie, u16 *wpa_len)
++{
++	u8 authmode, sec_idx;
++	u8 wpa_oui[4] = {0x0, 0x50, 0xf2, 0x01};
++	uint	cnt;
++
++
++	/* Search required WPA or WPA2 IE and copy to sec_ie[ ] */
++
++	cnt = (_TIMESTAMP_ + _BEACON_ITERVAL_ + _CAPABILITY_);
++
++	sec_idx = 0;
++
++	while (cnt < in_len) {
++		authmode = in_ie[cnt];
++
++		if ((authmode == _WPA_IE_ID_) && (_rtw_memcmp(&in_ie[cnt + 2], &wpa_oui[0], 4) == _TRUE)) {
++
++			if (wpa_ie)
++				_rtw_memcpy(wpa_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
++
++			*wpa_len = in_ie[cnt + 1] + 2;
++			cnt += in_ie[cnt + 1] + 2; /* get next */
++		} else {
++			if (authmode == _WPA2_IE_ID_) {
++
++				if (rsn_ie)
++					_rtw_memcpy(rsn_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
++
++				*rsn_len = in_ie[cnt + 1] + 2;
++				cnt += in_ie[cnt + 1] + 2; /* get next */
++			} else {
++				cnt += in_ie[cnt + 1] + 2; /* get next */
++			}
++		}
++
++	}
++
++
++	return *rsn_len + *wpa_len;
++
++}
++
++u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen)
++{
++	u8 match = _FALSE;
++	u8 eid, wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};
++
++	if (ie_ptr == NULL)
++		return match;
++
++	eid = ie_ptr[0];
++
++	if ((eid == _WPA_IE_ID_) && (_rtw_memcmp(&ie_ptr[2], wps_oui, 4) == _TRUE)) {
++		/* RTW_INFO("==> found WPS_IE.....\n"); */
++		*wps_ielen = ie_ptr[1] + 2;
++		match = _TRUE;
++	}
++	return match;
++}
++
++u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, enum bss_type frame_type)
++{
++	u8	*wps = NULL;
++
++	RTW_INFO("[%s] frame_type = %d\n", __FUNCTION__, frame_type);
++	switch (frame_type) {
++	case BSS_TYPE_BCN:
++	case BSS_TYPE_PROB_RSP: {
++		/*	Beacon or Probe Response */
++		wps = rtw_get_wps_ie(in_ie + _PROBERSP_IE_OFFSET_, in_len - _PROBERSP_IE_OFFSET_, wps_ie, wps_ielen);
++		break;
++	}
++	case BSS_TYPE_PROB_REQ: {
++		/*	Probe Request */
++		wps = rtw_get_wps_ie(in_ie + _PROBEREQ_IE_OFFSET_ , in_len - _PROBEREQ_IE_OFFSET_ , wps_ie, wps_ielen);
++		break;
++	}
++	default:
++	case BSS_TYPE_UNDEF:
++		break;
++	}
++	return wps;
++}
++
++/**
++ * rtw_get_wps_ie - Search WPS IE from a series of IEs
++ * @in_ie: Address of IEs to search
++ * @in_len: Length limit from in_ie
++ * @wps_ie: If not NULL and WPS IE is found, WPS IE will be copied to the buf starting from wps_ie
++ * @wps_ielen: If not NULL and WPS IE is found, will set to the length of the entire WPS IE
++ *
++ * Returns: The address of the WPS IE found, or NULL
++ */
++u8 *rtw_get_wps_ie(const u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen)
++{
++	uint cnt;
++	const u8 *wpsie_ptr = NULL;
++	u8 eid, wps_oui[4] = {0x00, 0x50, 0xf2, 0x04};
++
++	if (wps_ielen)
++		*wps_ielen = 0;
++
++	if (!in_ie) {
++		rtw_warn_on(1);
++		return (u8 *)wpsie_ptr;
++	}
++
++	if (in_len <= 0)
++		return (u8 *)wpsie_ptr;
++
++	cnt = 0;
++
++	while (cnt + 1 + 4 < in_len) {
++		eid = in_ie[cnt];
++
++		if (cnt + 1 + 4 >= MAX_IE_SZ) {
++			rtw_warn_on(1);
++			return NULL;
++		}
++
++		if (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], wps_oui, 4) == _TRUE) {
++			wpsie_ptr = in_ie + cnt;
++
++			if (wps_ie)
++				_rtw_memcpy(wps_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
++
++			if (wps_ielen)
++				*wps_ielen = in_ie[cnt + 1] + 2;
++
++			break;
++		} else
++			cnt += in_ie[cnt + 1] + 2;
++
++	}
++
++	return (u8 *)wpsie_ptr;
++}
++
++/**
++ * rtw_get_wps_attr - Search a specific WPS attribute from a given WPS IE
++ * @wps_ie: Address of WPS IE to search
++ * @wps_ielen: Length limit from wps_ie
++ * @target_attr_id: The attribute ID of WPS attribute to search
++ * @buf_attr: If not NULL and the WPS attribute is found, WPS attribute will be copied to the buf starting from buf_attr
++ * @len_attr: If not NULL and the WPS attribute is found, will set to the length of the entire WPS attribute
++ *
++ * Returns: the address of the specific WPS attribute found, or NULL
++ */
++u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_attr, u32 *len_attr)
++{
++	u8 *attr_ptr = NULL;
++	u8 *target_attr_ptr = NULL;
++	u8 wps_oui[4] = {0x00, 0x50, 0xF2, 0x04};
++
++	if (len_attr)
++		*len_attr = 0;
++
++	if ((wps_ie[0] != _VENDOR_SPECIFIC_IE_) ||
++	    (_rtw_memcmp(wps_ie + 2, wps_oui , 4) != _TRUE))
++		return attr_ptr;
++
++	/* 6 = 1(Element ID) + 1(Length) + 4(WPS OUI) */
++	attr_ptr = wps_ie + 6; /* goto first attr */
++
++	while (attr_ptr - wps_ie < wps_ielen) {
++		/* 4 = 2(Attribute ID) + 2(Length) */
++		u16 attr_id = RTW_GET_BE16(attr_ptr);
++		u16 attr_data_len = RTW_GET_BE16(attr_ptr + 2);
++		u16 attr_len = attr_data_len + 4;
++
++		/* RTW_INFO("%s attr_ptr:%p, id:%u, length:%u\n", __FUNCTION__, attr_ptr, attr_id, attr_data_len); */
++		if (attr_id == target_attr_id) {
++			target_attr_ptr = attr_ptr;
++
++			if (buf_attr)
++				_rtw_memcpy(buf_attr, attr_ptr, attr_len);
++
++			if (len_attr)
++				*len_attr = attr_len;
++
++			break;
++		} else {
++			attr_ptr += attr_len; /* goto next */
++		}
++
++	}
++
++	return target_attr_ptr;
++}
++
++/**
++ * rtw_get_wps_attr_content - Search a specific WPS attribute content from a given WPS IE
++ * @wps_ie: Address of WPS IE to search
++ * @wps_ielen: Length limit from wps_ie
++ * @target_attr_id: The attribute ID of WPS attribute to search
++ * @buf_content: If not NULL and the WPS attribute is found, WPS attribute content will be copied to the buf starting from buf_content
++ * @len_content: If not NULL and the WPS attribute is found, will set to the length of the WPS attribute content
++ *
++ * Returns: the address of the specific WPS attribute content found, or NULL
++ */
++u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_content, uint *len_content)
++{
++	u8 *attr_ptr;
++	u32 attr_len;
++
++	if (len_content)
++		*len_content = 0;
++
++	attr_ptr = rtw_get_wps_attr(wps_ie, wps_ielen, target_attr_id, NULL, &attr_len);
++
++	if (attr_ptr && attr_len) {
++		if (buf_content)
++			_rtw_memcpy(buf_content, attr_ptr + 4, attr_len - 4);
++
++		if (len_content)
++			*len_content = attr_len - 4;
++
++		return attr_ptr + 4;
++	}
++
++	return NULL;
++}
++
++/* OWE */
++
++/**
++ * rtw_get_OWE_ie - Search OWE IE from a series of IEs
++ * @in_ie: Address of IEs to search
++ * @in_len: Length limit from in_ie
++ * @wps_ie: If not NULL and OWE IE is found, OWE IE will be copied to the buf starting from owe_ie
++ * @wps_ielen: If not NULL and OWE IE is found, will set to the length of the entire OWE IE
++ *
++ * Returns: The address of the OWE IE found, or NULL
++ */
++u8 *rtw_get_owe_ie(const u8 *in_ie, uint in_len, u8 *owe_ie, uint *owe_ielen)
++{
++	uint cnt;
++	const u8 *oweie_ptr = NULL;
++	u8 eid;
++
++	if (owe_ielen)
++		*owe_ielen = 0;
++
++	if (!in_ie) {
++		rtw_warn_on(1);
++		return (u8 *)oweie_ptr;
++	}
++
++	if (in_len <= 0)
++		return (u8 *)oweie_ptr;
++
++	cnt = 0;
++
++	while (cnt + 1 + 4 < in_len) {
++		eid = in_ie[cnt];
++
++		if (cnt + 1 + 4 >= MAX_IE_SZ) {
++			rtw_warn_on(1);
++			return NULL;
++		}
++
++		if ((eid == WLAN_EID_EXTENSION) && (in_ie[cnt + 2] == WLAN_EID_EXT_OWE_DH_PARAM)) {
++			oweie_ptr = in_ie + cnt;
++
++			if (owe_ie)
++				_rtw_memcpy(owe_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
++
++			if (owe_ielen)
++				*owe_ielen = in_ie[cnt + 1] + 2;
++
++			break;
++		} else
++			cnt += in_ie[cnt + 1] + 2;
++
++	}
++
++	return (u8 *)oweie_ptr;
++}
++
++static int rtw_ieee802_11_parse_vendor_specific(u8 *pos, uint elen,
++		struct rtw_ieee802_11_elems *elems,
++		int show_errors)
++{
++	unsigned int oui;
++
++	/* first 3 bytes in vendor specific information element are the IEEE
++	 * OUI of the vendor. The following byte is used a vendor specific
++	 * sub-type. */
++	if (elen < 4) {
++		if (show_errors) {
++			RTW_INFO("short vendor specific "
++				 "information element ignored (len=%lu)\n",
++				 (unsigned long) elen);
++		}
++		return -1;
++	}
++
++	oui = RTW_GET_BE24(pos);
++	switch (oui) {
++	case OUI_MICROSOFT:
++		/* Microsoft/Wi-Fi information elements are further typed and
++		 * subtyped */
++		switch (pos[3]) {
++		case 1:
++			/* Microsoft OUI (00:50:F2) with OUI Type 1:
++			 * real WPA information element */
++			elems->wpa_ie = pos;
++			elems->wpa_ie_len = elen;
++			break;
++		case WME_OUI_TYPE: /* this is a Wi-Fi WME info. element */
++			if (elen < 5) {
++				RTW_DBG("short WME "
++					"information element ignored "
++					"(len=%lu)\n",
++					(unsigned long) elen);
++				return -1;
++			}
++			switch (pos[4]) {
++			case WME_OUI_SUBTYPE_INFORMATION_ELEMENT:
++			case WME_OUI_SUBTYPE_PARAMETER_ELEMENT:
++				elems->wme = pos;
++				elems->wme_len = elen;
++				break;
++			case WME_OUI_SUBTYPE_TSPEC_ELEMENT:
++				elems->wme_tspec = pos;
++				elems->wme_tspec_len = elen;
++				break;
++			default:
++				RTW_DBG("unknown WME "
++					"information element ignored "
++					"(subtype=%d len=%lu)\n",
++					pos[4], (unsigned long) elen);
++				return -1;
++			}
++			break;
++		case 4:
++			/* Wi-Fi Protected Setup (WPS) IE */
++			elems->wps_ie = pos;
++			elems->wps_ie_len = elen;
++			break;
++		default:
++			RTW_DBG("Unknown Microsoft "
++				"information element ignored "
++				"(type=%d len=%lu)\n",
++				pos[3], (unsigned long) elen);
++			return -1;
++		}
++		break;
++
++	case OUI_BROADCOM:
++		switch (pos[3]) {
++		case VENDOR_HT_CAPAB_OUI_TYPE:
++			elems->vendor_ht_cap = pos;
++			elems->vendor_ht_cap_len = elen;
++			break;
++		default:
++			RTW_DBG("Unknown Broadcom "
++				"information element ignored "
++				"(type=%d len=%lu)\n",
++				pos[3], (unsigned long) elen);
++			return -1;
++		}
++		break;
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	case OUI_REALTEK:
++		if (elen == 8) {  // TBTX capable IE length is 8
++			elems->tbtx_cap = pos;
++			elems->tbtx_cap_len = elen;
++		}
++		break;
++#endif
++	default:
++		RTW_DBG("unknown vendor specific information "
++			"element ignored (vendor OUI %02x:%02x:%02x "
++			"len=%lu)\n",
++			pos[0], pos[1], pos[2], (unsigned long) elen);
++		return -1;
++	}
++
++	return 0;
++
++}
++
++/**
++ * ieee802_11_parse_elems - Parse information elements in management frames
++ * @start: Pointer to the start of IEs
++ * @len: Length of IE buffer in octets
++ * @elems: Data structure for parsed elements
++ * @show_errors: Whether to show parsing errors in debug log
++ * Returns: Parsing result
++ */
++ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len,
++				    struct rtw_ieee802_11_elems *elems,
++				    int show_errors)
++{
++	uint left = len;
++	u8 *pos = start;
++	int unknown = 0;
++
++	_rtw_memset(elems, 0, sizeof(*elems));
++
++	while (left >= 2) {
++		u8 id, elen;
++
++		id = *pos++;
++		elen = *pos++;
++		left -= 2;
++
++		if (elen > left) {
++			if (show_errors) {
++				RTW_INFO("IEEE 802.11 element "
++					 "parse failed (id=%d elen=%d "
++					 "left=%lu)\n",
++					 id, elen, (unsigned long) left);
++			}
++			return ParseFailed;
++		}
++
++		switch (id) {
++		case WLAN_EID_SSID:
++			elems->ssid = pos;
++			elems->ssid_len = elen;
++			break;
++		case WLAN_EID_SUPP_RATES:
++			elems->supp_rates = pos;
++			elems->supp_rates_len = elen;
++			break;
++		case WLAN_EID_FH_PARAMS:
++			elems->fh_params = pos;
++			elems->fh_params_len = elen;
++			break;
++		case WLAN_EID_DS_PARAMS:
++			elems->ds_params = pos;
++			elems->ds_params_len = elen;
++			break;
++		case WLAN_EID_CF_PARAMS:
++			elems->cf_params = pos;
++			elems->cf_params_len = elen;
++			break;
++		case WLAN_EID_TIM:
++			elems->tim = pos;
++			elems->tim_len = elen;
++			break;
++		case WLAN_EID_IBSS_PARAMS:
++			elems->ibss_params = pos;
++			elems->ibss_params_len = elen;
++			break;
++		case WLAN_EID_CHALLENGE:
++			elems->challenge = pos;
++			elems->challenge_len = elen;
++			break;
++		case WLAN_EID_ERP_INFO:
++			elems->erp_info = pos;
++			elems->erp_info_len = elen;
++			break;
++		case WLAN_EID_EXT_SUPP_RATES:
++			elems->ext_supp_rates = pos;
++			elems->ext_supp_rates_len = elen;
++			break;
++		case WLAN_EID_VENDOR_SPECIFIC:
++			if (rtw_ieee802_11_parse_vendor_specific(pos, elen,
++					elems,
++					show_errors))
++				unknown++;
++			break;
++		case WLAN_EID_RSN:
++			elems->rsn_ie = pos;
++			elems->rsn_ie_len = elen;
++			break;
++		case WLAN_EID_PWR_CAPABILITY:
++			elems->power_cap = pos;
++			elems->power_cap_len = elen;
++			break;
++		case WLAN_EID_SUPPORTED_CHANNELS:
++			elems->supp_channels = pos;
++			elems->supp_channels_len = elen;
++			break;
++		case WLAN_EID_MOBILITY_DOMAIN:
++			elems->mdie = pos;
++			elems->mdie_len = elen;
++			break;
++		case WLAN_EID_FAST_BSS_TRANSITION:
++			elems->ftie = pos;
++			elems->ftie_len = elen;
++			break;
++		case WLAN_EID_TIMEOUT_INTERVAL:
++			elems->timeout_int = pos;
++			elems->timeout_int_len = elen;
++			break;
++		case WLAN_EID_HT_CAP:
++			elems->ht_capabilities = pos;
++			elems->ht_capabilities_len = elen;
++			break;
++		case WLAN_EID_HT_OPERATION:
++			elems->ht_operation = pos;
++			elems->ht_operation_len = elen;
++			break;
++		case WLAN_EID_VHT_CAPABILITY:
++			elems->vht_capabilities = pos;
++			elems->vht_capabilities_len = elen;
++			break;
++		case WLAN_EID_VHT_OPERATION:
++			elems->vht_operation = pos;
++			elems->vht_operation_len = elen;
++			break;
++		case WLAN_EID_VHT_OP_MODE_NOTIFY:
++			elems->vht_op_mode_notify = pos;
++			elems->vht_op_mode_notify_len = elen;
++			break;
++		case _EID_RRM_EN_CAP_IE_:
++			elems->rm_en_cap = pos;
++			elems->rm_en_cap_len = elen;
++			break;
++#ifdef CONFIG_RTW_MESH
++		case WLAN_EID_PREQ:
++			elems->preq = pos;
++			elems->preq_len = elen;
++			break;
++		case WLAN_EID_PREP:
++			elems->prep = pos;
++			elems->prep_len = elen;
++			break;
++		case WLAN_EID_PERR:
++			elems->perr = pos;
++			elems->perr_len = elen;
++			break;
++		case WLAN_EID_RANN:
++			elems->rann = pos;
++			elems->rann_len = elen;
++			break;
++#endif
++		default:
++			unknown++;
++			if (!show_errors)
++				break;
++			RTW_DBG("IEEE 802.11 element parse "
++				"ignored unknown element (id=%d elen=%d)\n",
++				id, elen);
++			break;
++		}
++
++		left -= elen;
++		pos += elen;
++	}
++
++	if (left)
++		return ParseFailed;
++
++	return unknown ? ParseUnknown : ParseOK;
++
++}
++
++static u8 key_char2num(u8 ch);
++static u8 key_char2num(u8 ch)
++{
++	if ((ch >= '0') && (ch <= '9'))
++		return ch - '0';
++	else if ((ch >= 'a') && (ch <= 'f'))
++		return ch - 'a' + 10;
++	else if ((ch >= 'A') && (ch <= 'F'))
++		return ch - 'A' + 10;
++	else
++		return 0xff;
++}
++
++u8 str_2char2num(u8 hch, u8 lch);
++u8 str_2char2num(u8 hch, u8 lch)
++{
++	return (key_char2num(hch) * 10) + key_char2num(lch);
++}
++
++u8 key_2char2num(u8 hch, u8 lch);
++u8 key_2char2num(u8 hch, u8 lch)
++{
++	return (key_char2num(hch) << 4) | key_char2num(lch);
++}
++
++void macstr2num(u8 *dst, u8 *src);
++void macstr2num(u8 *dst, u8 *src)
++{
++	int	jj, kk;
++	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
++		dst[jj] = key_2char2num(src[kk], src[kk + 1]);
++}
++
++u8 convert_ip_addr(u8 hch, u8 mch, u8 lch)
++{
++	return (key_char2num(hch) * 100) + (key_char2num(mch) * 10) + key_char2num(lch);
++}
++
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++#define MAC_ADDRESS_LEN 12
++
++int rtw_get_mac_addr_intel(unsigned char *buf)
++{
++	int ret = 0;
++	int i;
++	struct file *fp = NULL;
++	mm_segment_t oldfs;
++	unsigned char c_mac[MAC_ADDRESS_LEN];
++	char fname[] = "/config/wifi/mac.txt";
++	int jj, kk;
++
++	RTW_INFO("%s Enter\n", __FUNCTION__);
++
++	ret = rtw_retrieve_from_file(fname, c_mac, MAC_ADDRESS_LEN);
++	if (ret < MAC_ADDRESS_LEN)
++		return -1;
++
++	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 2)
++		buf[jj] = key_2char2num(c_mac[kk], c_mac[kk + 1]);
++
++	RTW_INFO("%s: read from file mac address: "MAC_FMT"\n",
++		 __FUNCTION__, MAC_ARG(buf));
++
++	return 0;
++}
++#endif /* CONFIG_PLATFORM_INTEL_BYT */
++
++/*
++ * Description:
++ * rtw_check_invalid_mac_address:
++ * This is only used for checking mac address valid or not.
++ *
++ * Input:
++ * adapter: mac_address pointer.
++ * check_local_bit: check locally bit or not.
++ *
++ * Output:
++ * _TRUE: The mac address is invalid.
++ * _FALSE: The mac address is valid.
++ *
++ * Auther: Isaac.Li
++ */
++u8 rtw_check_invalid_mac_address(u8 *mac_addr, u8 check_local_bit)
++{
++	u8 null_mac_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
++	u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	u8 res = _FALSE;
++
++	if (_rtw_memcmp(mac_addr, null_mac_addr, ETH_ALEN)) {
++		res = _TRUE;
++		goto func_exit;
++	}
++
++	if (_rtw_memcmp(mac_addr, multi_mac_addr, ETH_ALEN)) {
++		res = _TRUE;
++		goto func_exit;
++	}
++
++	if (mac_addr[0] & BIT0) {
++		res = _TRUE;
++		goto func_exit;
++	}
++
++	if (check_local_bit == _TRUE) {
++		if (mac_addr[0] & BIT1) {
++			res = _TRUE;
++			goto func_exit;
++		}
++	}
++
++func_exit:
++	return res;
++}
++
++extern char *rtw_initmac;
++/**
++ * rtw_macaddr_cfg - Decide the mac address used
++ * @out: buf to store mac address decided
++ * @hw_mac_addr: mac address from efuse/epprom
++ */
++void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr)
++{
++#define DEFAULT_RANDOM_MACADDR 1
++	u8 mac[ETH_ALEN];
++
++	if (out == NULL) {
++		rtw_warn_on(1);
++		return;
++	}
++
++	/* Users specify the mac address */
++	if (rtw_initmac) {
++		int jj, kk;
++
++		for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
++			mac[jj] = key_2char2num(rtw_initmac[kk], rtw_initmac[kk + 1]);
++
++		goto err_chk;
++	}
++
++	/* platform specified */
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++	if (rtw_get_mac_addr_intel(mac) == 0)
++		goto err_chk;
++#endif
++
++	/* Use the mac address stored in the Efuse */
++	if (hw_mac_addr) {
++		_rtw_memcpy(mac, hw_mac_addr, ETH_ALEN);
++		goto err_chk;
++	}
++
++err_chk:
++	if (rtw_check_invalid_mac_address(mac, _TRUE) == _TRUE) {
++#if DEFAULT_RANDOM_MACADDR
++		RTW_ERR("invalid mac addr:"MAC_FMT", assign random MAC\n", MAC_ARG(mac));
++		*((u32 *)(&mac[2])) = rtw_random32();
++		mac[0] = 0x00;
++		mac[1] = 0xe0;
++		mac[2] = 0x4c;
++#else
++		RTW_ERR("invalid mac addr:"MAC_FMT", assign default one\n", MAC_ARG(mac));
++		mac[0] = 0x00;
++		mac[1] = 0xe0;
++		mac[2] = 0x4c;
++		mac[3] = 0x87;
++		mac[4] = 0x00;
++		mac[5] = 0x00;
++#endif
++	}
++
++	_rtw_memcpy(out, mac, ETH_ALEN);
++	RTW_INFO("%s mac addr:"MAC_FMT"\n", __func__, MAC_ARG(out));
++}
++
++#ifdef CONFIG_80211N_HT
++void dump_ht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len)
++{
++	if (buf_len != HT_CAP_IE_LEN) {
++		RTW_PRINT_SEL(sel, "Invalid HT capability IE len:%d != %d\n", buf_len, HT_CAP_IE_LEN);
++		return;
++	}
++
++	RTW_PRINT_SEL(sel, "cap_info:%02x%02x:%s\n", *(buf), *(buf + 1)
++		, GET_HT_CAP_ELE_CHL_WIDTH(buf) ? " 40MHz" : " 20MHz");
++	RTW_PRINT_SEL(sel, "A-MPDU Parameters:"HT_AMPDU_PARA_FMT"\n"
++		      , HT_AMPDU_PARA_ARG(HT_CAP_ELE_AMPDU_PARA(buf)));
++	RTW_PRINT_SEL(sel, "Supported MCS Set:"HT_SUP_MCS_SET_FMT"\n"
++		      , HT_SUP_MCS_SET_ARG(HT_CAP_ELE_SUP_MCS_SET(buf)));
++}
++
++void dump_ht_cap_ie(void *sel, const u8 *ie, u32 ie_len)
++{
++	const u8 *ht_cap_ie;
++	sint ht_cap_ielen;
++
++	ht_cap_ie = rtw_get_ie(ie, WLAN_EID_HT_CAP, &ht_cap_ielen, ie_len);
++	if (!ie || ht_cap_ie != ie)
++		return;
++
++	dump_ht_cap_ie_content(sel, ht_cap_ie + 2, ht_cap_ielen);
++}
++
++const char *const _ht_sc_offset_str[] = {
++	"SCN",
++	"SCA",
++	"SC-RSVD",
++	"SCB",
++};
++
++void dump_ht_op_ie_content(void *sel, const u8 *buf, u32 buf_len)
++{
++	if (buf_len != HT_OP_IE_LEN) {
++		RTW_PRINT_SEL(sel, "Invalid HT operation IE len:%d != %d\n", buf_len, HT_OP_IE_LEN);
++		return;
++	}
++
++	RTW_PRINT_SEL(sel, "ch:%u%s %s\n"
++		, GET_HT_OP_ELE_PRI_CHL(buf)
++		, GET_HT_OP_ELE_STA_CHL_WIDTH(buf) ? "" : " 20MHz only"
++		, ht_sc_offset_str(GET_HT_OP_ELE_2ND_CHL_OFFSET(buf))
++	);
++}
++
++void dump_ht_op_ie(void *sel, const u8 *ie, u32 ie_len)
++{
++	const u8 *ht_op_ie;
++	sint ht_op_ielen;
++
++	ht_op_ie = rtw_get_ie(ie, WLAN_EID_HT_OPERATION, &ht_op_ielen, ie_len);
++	if (!ie || ht_op_ie != ie)
++		return;
++
++	dump_ht_op_ie_content(sel, ht_op_ie + 2, ht_op_ielen);
++}
++#endif /* CONFIG_80211N_HT */
++
++void dump_ies(void *sel, const u8 *buf, u32 buf_len)
++{
++	const u8 *pos = buf;
++	u8 id, len;
++
++	while (pos - buf + 1 < buf_len) {
++		id = *pos;
++		len = *(pos + 1);
++
++		RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u\n", __FUNCTION__, id, len);
++#ifdef CONFIG_80211N_HT
++		dump_ht_cap_ie(sel, pos, len + 2);
++		dump_ht_op_ie(sel, pos, len + 2);
++#endif
++#ifdef CONFIG_80211AC_VHT
++		dump_vht_cap_ie(sel, pos, len + 2);
++		dump_vht_op_ie(sel, pos, len + 2);
++#endif
++		dump_wps_ie(sel, pos, len + 2);
++#ifdef CONFIG_P2P
++		dump_p2p_ie(sel, pos, len + 2);
++#ifdef CONFIG_WFD
++		dump_wfd_ie(sel, pos, len + 2);
++#endif
++#endif
++#ifdef CONFIG_RTW_MULTI_AP
++		dump_multi_ap_ie(sel, pos, len + 2);
++#endif
++
++		pos += (2 + len);
++	}
++}
++
++void dump_wps_ie(void *sel, const u8 *ie, u32 ie_len)
++{
++	const u8 *pos = ie;
++	u16 id;
++	u16 len;
++
++	const u8 *wps_ie;
++	uint wps_ielen;
++
++	wps_ie = rtw_get_wps_ie(ie, ie_len, NULL, &wps_ielen);
++	if (wps_ie != ie || wps_ielen == 0)
++		return;
++
++	pos += 6;
++	while (pos - ie + 4 <= ie_len) {
++		id = RTW_GET_BE16(pos);
++		len = RTW_GET_BE16(pos + 2);
++
++		RTW_PRINT_SEL(sel, "%s ID:0x%04x, LEN:%u%s\n", __func__, id, len
++			, ((pos - ie + 4 + len) <= ie_len) ? "" : "(exceed ie_len)");
++
++		pos += (4 + len);
++	}
++}
++
++/**
++ * rtw_ies_get_chbw - get operation ch, bw, offset from IEs of BSS.
++ * @ies: pointer of the first tlv IE
++ * @ies_len: length of @ies
++ * @ch: pointer of ch, used as output
++ * @bw: pointer of bw, used as output
++ * @offset: pointer of offset, used as output
++ * @ht: check HT IEs
++ * @vht: check VHT IEs, if true imply ht is true
++ */
++void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht)
++{
++	u8 *p;
++	int	ie_len;
++
++	*ch = 0;
++	*bw = CHANNEL_WIDTH_20;
++	*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++	p = rtw_get_ie(ies, _DSSET_IE_, &ie_len, ies_len);
++	if (p && ie_len > 0)
++		*ch = *(p + 2);
++
++#ifdef CONFIG_80211N_HT
++	if (ht || vht) {
++		u8 *ht_cap_ie, *ht_op_ie;
++		int ht_cap_ielen, ht_op_ielen;
++
++		ht_cap_ie = rtw_get_ie(ies, EID_HTCapability, &ht_cap_ielen, ies_len);
++		if (ht_cap_ie && ht_cap_ielen) {
++			if (GET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2))
++				*bw = CHANNEL_WIDTH_40;
++		}
++
++		ht_op_ie = rtw_get_ie(ies, EID_HTInfo, &ht_op_ielen, ies_len);
++		if (ht_op_ie && ht_op_ielen) {
++			if (*ch == 0)
++				*ch = GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2);
++			else if (*ch != 0 && *ch != GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2)) {
++				RTW_INFO("%s ch inconsistent, DSSS:%u, HT primary:%u\n"
++					, __func__, *ch, GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2));
++			}
++
++			if (!GET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2))
++				*bw = CHANNEL_WIDTH_20;
++
++			if (*bw == CHANNEL_WIDTH_40) {
++				switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2)) {
++				case SCA:
++					*offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++					break;
++				case SCB:
++					*offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++					break;
++				}
++			}
++		}
++
++#ifdef CONFIG_80211AC_VHT
++		if (vht) {
++			u8 *vht_op_ie;
++			int vht_op_ielen;
++
++			vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len);
++			if (vht_op_ie && vht_op_ielen) {
++				if (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2) >= 1)
++					*bw = CHANNEL_WIDTH_80;
++			}
++		}
++#endif /* CONFIG_80211AC_VHT */
++
++	}
++#endif /* CONFIG_80211N_HT */
++}
++
++void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht)
++{
++	rtw_ies_get_chbw(bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)
++		, bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)
++		, ch, bw, offset, ht, vht);
++
++	if (*ch == 0)
++		*ch = bss->Configuration.DSConfig;
++	else if (*ch != bss->Configuration.DSConfig) {
++		RTW_INFO("inconsistent ch - ies:%u bss->Configuration.DSConfig:%u\n"
++			 , *ch, bss->Configuration.DSConfig);
++		*ch = bss->Configuration.DSConfig;
++		rtw_warn_on(1);
++	}
++}
++
++/**
++ * rtw_is_chbw_grouped - test if the two ch settings can be grouped together
++ * @ch_a: ch of set a
++ * @bw_a: bw of set a
++ * @offset_a: offset of set a
++ * @ch_b: ch of set b
++ * @bw_b: bw of set b
++ * @offset_b: offset of set b
++ */
++bool rtw_is_chbw_grouped(u8 ch_a, u8 bw_a, u8 offset_a
++			 , u8 ch_b, u8 bw_b, u8 offset_b)
++{
++	bool is_grouped = _FALSE;
++
++	if (ch_a != ch_b) {
++		/* ch is different */
++		goto exit;
++	} else if ((bw_a == CHANNEL_WIDTH_40 || bw_a == CHANNEL_WIDTH_80)
++		   && (bw_b == CHANNEL_WIDTH_40 || bw_b == CHANNEL_WIDTH_80)
++		  ) {
++		if (offset_a != offset_b)
++			goto exit;
++	}
++
++	is_grouped = _TRUE;
++
++exit:
++	return is_grouped;
++}
++
++/**
++ * rtw_sync_chbw - obey g_ch, adjust g_bw, g_offset, bw, offset
++ * @req_ch: pointer of the request ch, may be modified further
++ * @req_bw: pointer of the request bw, may be modified further
++ * @req_offset: pointer of the request offset, may be modified further
++ * @g_ch: pointer of the ongoing group ch
++ * @g_bw: pointer of the ongoing group bw, may be modified further
++ * @g_offset: pointer of the ongoing group offset, may be modified further
++ */
++void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset
++		   , u8 *g_ch, u8 *g_bw, u8 *g_offset)
++{
++
++	*req_ch = *g_ch;
++
++	if (*req_bw == CHANNEL_WIDTH_80 && *g_ch <= 14) {
++		/*2.4G ch, downgrade to 40Mhz */
++		*req_bw = CHANNEL_WIDTH_40;
++	}
++
++	switch (*req_bw) {
++	case CHANNEL_WIDTH_80:
++		if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80)
++			*req_offset = *g_offset;
++		else if (*g_bw == CHANNEL_WIDTH_20)
++			rtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset);
++
++		if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) {
++			RTW_ERR("%s req 80MHz BW without offset, down to 20MHz\n", __func__);
++			rtw_warn_on(1);
++			*req_bw = CHANNEL_WIDTH_20;
++		}
++		break;
++	case CHANNEL_WIDTH_40:
++		if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80)
++			*req_offset = *g_offset;
++		else if (*g_bw == CHANNEL_WIDTH_20)
++			rtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset);
++
++		if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) {
++			RTW_ERR("%s req 40MHz BW without offset, down to 20MHz\n", __func__);
++			rtw_warn_on(1);
++			*req_bw = CHANNEL_WIDTH_20;
++		}
++		break;
++	case CHANNEL_WIDTH_20:
++		*req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		break;
++	default:
++		RTW_ERR("%s req unsupported BW:%u\n", __func__, *req_bw);
++		rtw_warn_on(1);
++	}
++
++	if (*req_bw > *g_bw) {
++		*g_bw = *req_bw;
++		*g_offset = *req_offset;
++	}
++}
++
++/**
++ * rtw_get_p2p_merged_len - Get merged ie length from muitiple p2p ies.
++ * @in_ie: Pointer of the first p2p ie
++ * @in_len: Total len of muiltiple p2p ies
++ * Returns: Length of merged p2p ie length
++ */
++u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len)
++{
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++	u8 OUI[4] = { 0x50, 0x6f, 0x9a, 0x09 };
++	int i = 0;
++	int len = 0;
++
++	while (i < in_len) {
++		pIE = (PNDIS_802_11_VARIABLE_IEs)(in_ie + i);
++
++		if (pIE->ElementID == _VENDOR_SPECIFIC_IE_ && _rtw_memcmp(pIE->data, OUI, 4)) {
++			len += pIE->Length - 4; /* 4 is P2P OUI length, don't count it in this loop */
++		}
++
++		i += (pIE->Length + 2);
++	}
++
++	return len + 4;	/* Append P2P OUI length at last. */
++}
++
++/**
++ * rtw_p2p_merge_ies - Merge muitiple p2p ies into one
++ * @in_ie: Pointer of the first p2p ie
++ * @in_len: Total len of muiltiple p2p ies
++ * @merge_ie: Pointer of merged ie
++ * Returns: Length of merged p2p ie
++ */
++int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie)
++{
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++	u8 len = 0;
++	u8 OUI[4] = { 0x50, 0x6f, 0x9a, 0x09 };
++	u8 ELOUI[6] = { 0xDD, 0x00, 0x50, 0x6f, 0x9a, 0x09 };	/* EID;Len;OUI, Len would copy at the end of function */
++	int i = 0;
++
++	if (merge_ie != NULL) {
++		/* Set first P2P OUI */
++		_rtw_memcpy(merge_ie, ELOUI, 6);
++		merge_ie += 6;
++
++		while (i < in_len) {
++			pIE = (PNDIS_802_11_VARIABLE_IEs)(in_ie + i);
++
++			/* Take out the rest of P2P OUIs */
++			if (pIE->ElementID == _VENDOR_SPECIFIC_IE_ && _rtw_memcmp(pIE->data, OUI, 4)) {
++				_rtw_memcpy(merge_ie, pIE->data + 4, pIE->Length - 4);
++				len += pIE->Length - 4;
++				merge_ie += pIE->Length - 4;
++			}
++
++			i += (pIE->Length + 2);
++		}
++
++		return len + 4;	/* 4 is for P2P OUI */
++
++	}
++
++	return 0;
++}
++
++void dump_p2p_ie(void *sel, const u8 *ie, u32 ie_len)
++{
++	const u8 *pos = ie;
++	u8 id;
++	u16 len;
++
++	const u8 *p2p_ie;
++	uint p2p_ielen;
++
++	p2p_ie = rtw_get_p2p_ie(ie, ie_len, NULL, &p2p_ielen);
++	if (p2p_ie != ie || p2p_ielen == 0)
++		return;
++
++	pos += 6;
++	while (pos - ie + 3 <= ie_len) {
++		id = *pos;
++		len = RTW_GET_LE16(pos + 1);
++
++		RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u%s\n", __func__, id, len
++			, ((pos - ie + 3 + len) <= ie_len) ? "" : "(exceed ie_len)");
++
++		pos += (3 + len);
++	}
++}
++
++/**
++ * rtw_get_p2p_ie - Search P2P IE from a series of IEs
++ * @in_ie: Address of IEs to search
++ * @in_len: Length limit from in_ie
++ * @p2p_ie: If not NULL and P2P IE is found, P2P IE will be copied to the buf starting from p2p_ie
++ * @p2p_ielen: If not NULL and P2P IE is found, will set to the length of the entire P2P IE
++ *
++ * Returns: The address of the P2P IE found, or NULL
++ */
++u8 *rtw_get_p2p_ie(const u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen)
++{
++	uint cnt;
++	const u8 *p2p_ie_ptr = NULL;
++	u8 eid, p2p_oui[4] = {0x50, 0x6F, 0x9A, 0x09};
++
++	if (p2p_ielen)
++		*p2p_ielen = 0;
++
++	if (!in_ie || in_len < 0) {
++		rtw_warn_on(1);
++		return (u8 *)p2p_ie_ptr;
++	}
++
++	if (in_len <= 0)
++		return (u8 *)p2p_ie_ptr;
++
++	cnt = 0;
++
++	while (cnt + 1 + 4 < in_len) {
++		eid = in_ie[cnt];
++
++		if (cnt + 1 + 4 >= MAX_IE_SZ) {
++			rtw_warn_on(1);
++			return NULL;
++		}
++
++		if (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], p2p_oui, 4) == _TRUE) {
++			p2p_ie_ptr = in_ie + cnt;
++
++			if (p2p_ie)
++				_rtw_memcpy(p2p_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
++
++			if (p2p_ielen)
++				*p2p_ielen = in_ie[cnt + 1] + 2;
++
++			break;
++		} else
++			cnt += in_ie[cnt + 1] + 2;
++
++	}
++
++	return (u8 *)p2p_ie_ptr;
++}
++
++/**
++ * rtw_get_p2p_attr - Search a specific P2P attribute from a given P2P IE
++ * @p2p_ie: Address of P2P IE to search
++ * @p2p_ielen: Length limit from p2p_ie
++ * @target_attr_id: The attribute ID of P2P attribute to search
++ * @buf_attr: If not NULL and the P2P attribute is found, P2P attribute will be copied to the buf starting from buf_attr
++ * @len_attr: If not NULL and the P2P attribute is found, will set to the length of the entire P2P attribute
++ *
++ * Returns: the address of the specific WPS attribute found, or NULL
++ */
++u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id , u8 *buf_attr, u32 *len_attr)
++{
++	u8 *attr_ptr = NULL;
++	u8 *target_attr_ptr = NULL;
++	u8 p2p_oui[4] = {0x50, 0x6F, 0x9A, 0x09};
++
++	if (len_attr)
++		*len_attr = 0;
++
++	if (!p2p_ie
++	    || p2p_ielen <= 6
++	    || (p2p_ie[0] != WLAN_EID_VENDOR_SPECIFIC)
++	    || (_rtw_memcmp(p2p_ie + 2, p2p_oui, 4) != _TRUE))
++		return attr_ptr;
++
++	/* 6 = 1(Element ID) + 1(Length) + 3 (OUI) + 1(OUI Type) */
++	attr_ptr = p2p_ie + 6; /* goto first attr */
++
++	while ((attr_ptr - p2p_ie + 3) <= p2p_ielen) {
++		/* 3 = 1(Attribute ID) + 2(Length) */
++		u8 attr_id = *attr_ptr;
++		u16 attr_data_len = RTW_GET_LE16(attr_ptr + 1);
++		u16 attr_len = attr_data_len + 3;
++
++		if (0)
++			RTW_INFO("%s attr_ptr:%p, id:%u, length:%u\n", __func__, attr_ptr, attr_id, attr_data_len);
++
++		if ((attr_ptr - p2p_ie + attr_len) > p2p_ielen)
++			break;
++
++		if (attr_id == target_attr_id) {
++			target_attr_ptr = attr_ptr;
++
++			if (buf_attr)
++				_rtw_memcpy(buf_attr, attr_ptr, attr_len);
++
++			if (len_attr)
++				*len_attr = attr_len;
++
++			break;
++		} else
++			attr_ptr += attr_len;
++	}
++
++	return target_attr_ptr;
++}
++
++/**
++ * rtw_get_p2p_attr_content - Search a specific P2P attribute content from a given P2P IE
++ * @p2p_ie: Address of P2P IE to search
++ * @p2p_ielen: Length limit from p2p_ie
++ * @target_attr_id: The attribute ID of P2P attribute to search
++ * @buf_content: If not NULL and the P2P attribute is found, P2P attribute content will be copied to the buf starting from buf_content
++ * @len_content: If not NULL and the P2P attribute is found, will set to the length of the P2P attribute content
++ *
++ * Returns: the address of the specific P2P attribute content found, or NULL
++ */
++u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id , u8 *buf_content, uint *len_content)
++{
++	u8 *attr_ptr;
++	u32 attr_len;
++
++	if (len_content)
++		*len_content = 0;
++
++	attr_ptr = rtw_get_p2p_attr(p2p_ie, p2p_ielen, target_attr_id, NULL, &attr_len);
++
++	if (attr_ptr && attr_len) {
++		if (buf_content)
++			_rtw_memcpy(buf_content, attr_ptr + 3, attr_len - 3);
++
++		if (len_content)
++			*len_content = attr_len - 3;
++
++		return attr_ptr + 3;
++	}
++
++	return NULL;
++}
++
++u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr)
++{
++	u32 a_len;
++
++	*pbuf = attr_id;
++
++	/* *(u16*)(pbuf + 1) = cpu_to_le16(attr_len); */
++	RTW_PUT_LE16(pbuf + 1, attr_len);
++
++	if (pdata_attr)
++		_rtw_memcpy(pbuf + 3, pdata_attr, attr_len);
++
++	a_len = attr_len + 3;
++
++	return a_len;
++}
++
++uint rtw_del_p2p_ie(u8 *ies, uint ies_len_ori, const char *msg)
++{
++#define DBG_DEL_P2P_IE 0
++
++	u8 *target_ie;
++	u32 target_ie_len;
++	uint ies_len = ies_len_ori;
++	int index = 0;
++
++	while (1) {
++		target_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &target_ie_len);
++		if (target_ie && target_ie_len) {
++			u8 *next_ie = target_ie + target_ie_len;
++			uint remain_len = ies_len - (next_ie - ies);
++
++			if (DBG_DEL_P2P_IE && msg) {
++				RTW_INFO("%s %d before\n", __func__, index);
++				dump_ies(RTW_DBGDUMP, ies, ies_len);
++
++				RTW_INFO("ies:%p, ies_len:%u\n", ies, ies_len);
++				RTW_INFO("target_ie:%p, target_ie_len:%u\n", target_ie, target_ie_len);
++				RTW_INFO("next_ie:%p, remain_len:%u\n", next_ie, remain_len);
++			}
++
++			_rtw_memmove(target_ie, next_ie, remain_len);
++			_rtw_memset(target_ie + remain_len, 0, target_ie_len);
++			ies_len -= target_ie_len;
++
++			if (DBG_DEL_P2P_IE && msg) {
++				RTW_INFO("%s %d after\n", __func__, index);
++				dump_ies(RTW_DBGDUMP, ies, ies_len);
++			}
++
++			index++;
++		} else
++			break;
++	}
++
++	return ies_len;
++}
++
++uint rtw_del_p2p_attr(u8 *ie, uint ielen_ori, u8 attr_id)
++{
++#define DBG_DEL_P2P_ATTR 0
++
++	u8 *target_attr;
++	u32 target_attr_len;
++	uint ielen = ielen_ori;
++	int index = 0;
++
++	while (1) {
++		target_attr = rtw_get_p2p_attr(ie, ielen, attr_id, NULL, &target_attr_len);
++		if (target_attr && target_attr_len) {
++			u8 *next_attr = target_attr + target_attr_len;
++			uint remain_len = ielen - (next_attr - ie);
++
++			if (DBG_DEL_P2P_ATTR) {
++				RTW_INFO("%s %d before\n", __func__, index);
++				dump_ies(RTW_DBGDUMP, ie, ielen);
++
++				RTW_INFO("ie:%p, ielen:%u\n", ie, ielen);
++				RTW_INFO("target_attr:%p, target_attr_len:%u\n", target_attr, target_attr_len);
++				RTW_INFO("next_attr:%p, remain_len:%u\n", next_attr, remain_len);
++			}
++
++			_rtw_memmove(target_attr, next_attr, remain_len);
++			_rtw_memset(target_attr + remain_len, 0, target_attr_len);
++			*(ie + 1) -= target_attr_len;
++			ielen -= target_attr_len;
++
++			if (DBG_DEL_P2P_ATTR) {
++				RTW_INFO("%s %d after\n", __func__, index);
++				dump_ies(RTW_DBGDUMP, ie, ielen);
++			}
++
++			index++;
++		} else
++			break;
++	}
++
++	return ielen;
++}
++
++inline u8 *rtw_bss_ex_get_p2p_ie(WLAN_BSSID_EX *bss_ex, u8 *p2p_ie, uint *p2p_ielen)
++{
++	return rtw_get_p2p_ie(BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex), p2p_ie, p2p_ielen);
++}
++
++void rtw_bss_ex_del_p2p_ie(WLAN_BSSID_EX *bss_ex)
++{
++#define DBG_BSS_EX_DEL_P2P_IE 0
++
++	u8 *ies = BSS_EX_TLV_IES(bss_ex);
++	uint ies_len_ori = BSS_EX_TLV_IES_LEN(bss_ex);
++	uint ies_len;
++
++	ies_len = rtw_del_p2p_ie(ies, ies_len_ori, DBG_BSS_EX_DEL_P2P_IE ? __func__ : NULL);
++	bss_ex->IELength -= ies_len_ori - ies_len;
++}
++
++void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id)
++{
++#define DBG_BSS_EX_DEL_P2P_ATTR 0
++
++	u8 *ies = BSS_EX_TLV_IES(bss_ex);
++	uint ies_len = BSS_EX_TLV_IES_LEN(bss_ex);
++
++	u8 *ie;
++	uint ie_len, ie_len_ori;
++
++	int index = 0;
++
++	while (1) {
++		ie = rtw_get_p2p_ie(ies, ies_len, NULL, &ie_len_ori);
++		if (ie) {
++			u8 *next_ie_ori = ie + ie_len_ori;
++			uint remain_len = bss_ex->IELength - (next_ie_ori - bss_ex->IEs);
++			u8 has_target_attr = 0;
++
++			if (DBG_BSS_EX_DEL_P2P_ATTR) {
++				if (rtw_get_p2p_attr(ie, ie_len_ori, attr_id, NULL, NULL)) {
++					RTW_INFO("%s %d before\n", __func__, index);
++					dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex));
++
++					RTW_INFO("ies:%p, ies_len:%u\n", ies, ies_len);
++					RTW_INFO("ie:%p, ie_len_ori:%u\n", ie, ie_len_ori);
++					RTW_INFO("next_ie_ori:%p, remain_len:%u\n", next_ie_ori, remain_len);
++					has_target_attr = 1;
++				}
++			}
++
++			ie_len = rtw_del_p2p_attr(ie, ie_len_ori, attr_id);
++			if (ie_len != ie_len_ori) {
++				u8 *next_ie = ie + ie_len;
++
++				_rtw_memmove(next_ie, next_ie_ori, remain_len);
++				_rtw_memset(next_ie + remain_len, 0, ie_len_ori - ie_len);
++				bss_ex->IELength -= ie_len_ori - ie_len;
++
++				ies = next_ie;
++			} else
++				ies = next_ie_ori;
++
++			if (DBG_BSS_EX_DEL_P2P_ATTR) {
++				if (has_target_attr) {
++					RTW_INFO("%s %d after\n", __func__, index);
++					dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex));
++				}
++			}
++
++			ies_len = remain_len;
++
++			index++;
++		} else
++			break;
++	}
++}
++
++void dump_wfd_ie(void *sel, const u8 *ie, u32 ie_len)
++{
++	const u8 *pos = ie;
++	u8 id;
++	u16 len;
++
++	const u8 *wfd_ie;
++	uint wfd_ielen;
++
++	wfd_ie = rtw_get_wfd_ie(ie, ie_len, NULL, &wfd_ielen);
++	if (wfd_ie != ie || wfd_ielen == 0)
++		return;
++
++	pos += 6;
++	while (pos - ie + 3 <= ie_len) {
++		id = *pos;
++		len = RTW_GET_BE16(pos + 1);
++
++		RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u%s\n", __func__, id, len
++			, ((pos - ie + 3 + len) <= ie_len) ? "" : "(exceed ie_len)");
++
++		pos += (3 + len);
++	}
++}
++
++/**
++ * rtw_get_wfd_ie - Search WFD IE from a series of IEs
++ * @in_ie: Address of IEs to search
++ * @in_len: Length limit from in_ie
++ * @wfd_ie: If not NULL and WFD IE is found, WFD IE will be copied to the buf starting from wfd_ie
++ * @wfd_ielen: If not NULL and WFD IE is found, will set to the length of the entire WFD IE
++ *
++ * Returns: The address of the P2P IE found, or NULL
++ */
++u8 *rtw_get_wfd_ie(const u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen)
++{
++	uint cnt;
++	const u8 *wfd_ie_ptr = NULL;
++	u8 eid, wfd_oui[4] = {0x50, 0x6F, 0x9A, 0x0A};
++
++	if (wfd_ielen)
++		*wfd_ielen = 0;
++
++	if (!in_ie || in_len < 0) {
++		rtw_warn_on(1);
++		return (u8 *)wfd_ie_ptr;
++	}
++
++	if (in_len <= 0)
++		return (u8 *)wfd_ie_ptr;
++
++	cnt = 0;
++
++	while (cnt + 1 + 4 < in_len) {
++		eid = in_ie[cnt];
++
++		if (cnt + 1 + 4 >= MAX_IE_SZ) {
++			rtw_warn_on(1);
++			return NULL;
++		}
++
++		if (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], wfd_oui, 4) == _TRUE) {
++			wfd_ie_ptr = in_ie + cnt;
++
++			if (wfd_ie)
++				_rtw_memcpy(wfd_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
++
++			if (wfd_ielen)
++				*wfd_ielen = in_ie[cnt + 1] + 2;
++
++			break;
++		} else
++			cnt += in_ie[cnt + 1] + 2;
++
++	}
++
++	return (u8 *)wfd_ie_ptr;
++}
++
++/**
++ * rtw_get_wfd_attr - Search a specific WFD attribute from a given WFD IE
++ * @wfd_ie: Address of WFD IE to search
++ * @wfd_ielen: Length limit from wfd_ie
++ * @target_attr_id: The attribute ID of WFD attribute to search
++ * @buf_attr: If not NULL and the WFD attribute is found, WFD attribute will be copied to the buf starting from buf_attr
++ * @len_attr: If not NULL and the WFD attribute is found, will set to the length of the entire WFD attribute
++ *
++ * Returns: the address of the specific WPS attribute found, or NULL
++ */
++u8 *rtw_get_wfd_attr(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr)
++{
++	u8 *attr_ptr = NULL;
++	u8 *target_attr_ptr = NULL;
++	u8 wfd_oui[4] = {0x50, 0x6F, 0x9A, 0x0A};
++
++	if (len_attr)
++		*len_attr = 0;
++
++	if (!wfd_ie
++	    || wfd_ielen <= 6
++	    || (wfd_ie[0] != WLAN_EID_VENDOR_SPECIFIC)
++	    || (_rtw_memcmp(wfd_ie + 2, wfd_oui, 4) != _TRUE))
++		return attr_ptr;
++
++	/* 6 = 1(Element ID) + 1(Length) + 3 (OUI) + 1(OUI Type) */
++	attr_ptr = wfd_ie + 6; /* goto first attr */
++
++	while ((attr_ptr - wfd_ie + 3) <= wfd_ielen) {
++		/* 3 = 1(Attribute ID) + 2(Length) */
++		u8 attr_id = *attr_ptr;
++		u16 attr_data_len = RTW_GET_BE16(attr_ptr + 1);
++		u16 attr_len = attr_data_len + 3;
++
++		if (0)
++			RTW_INFO("%s attr_ptr:%p, id:%u, length:%u\n", __func__, attr_ptr, attr_id, attr_data_len);
++
++		if ((attr_ptr - wfd_ie + attr_len) > wfd_ielen)
++			break;
++
++		if (attr_id == target_attr_id) {
++			target_attr_ptr = attr_ptr;
++
++			if (buf_attr)
++				_rtw_memcpy(buf_attr, attr_ptr, attr_len);
++
++			if (len_attr)
++				*len_attr = attr_len;
++
++			break;
++		} else
++			attr_ptr += attr_len;
++	}
++
++	return target_attr_ptr;
++}
++
++/**
++ * rtw_get_wfd_attr_content - Search a specific WFD attribute content from a given WFD IE
++ * @wfd_ie: Address of WFD IE to search
++ * @wfd_ielen: Length limit from wfd_ie
++ * @target_attr_id: The attribute ID of WFD attribute to search
++ * @buf_content: If not NULL and the WFD attribute is found, WFD attribute content will be copied to the buf starting from buf_content
++ * @len_content: If not NULL and the WFD attribute is found, will set to the length of the WFD attribute content
++ *
++ * Returns: the address of the specific WFD attribute content found, or NULL
++ */
++u8 *rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content)
++{
++	u8 *attr_ptr;
++	u32 attr_len;
++
++	if (len_content)
++		*len_content = 0;
++
++	attr_ptr = rtw_get_wfd_attr(wfd_ie, wfd_ielen, target_attr_id, NULL, &attr_len);
++
++	if (attr_ptr && attr_len) {
++		if (buf_content)
++			_rtw_memcpy(buf_content, attr_ptr + 3, attr_len - 3);
++
++		if (len_content)
++			*len_content = attr_len - 3;
++
++		return attr_ptr + 3;
++	}
++
++	return NULL;
++}
++
++uint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg)
++{
++#define DBG_DEL_WFD_IE 0
++
++	u8 *target_ie;
++	u32 target_ie_len;
++	uint ies_len = ies_len_ori;
++	int index = 0;
++
++	while (1) {
++		target_ie = rtw_get_wfd_ie(ies, ies_len, NULL, &target_ie_len);
++		if (target_ie && target_ie_len) {
++			u8 *next_ie = target_ie + target_ie_len;
++			uint remain_len = ies_len - (next_ie - ies);
++
++			if (DBG_DEL_WFD_IE && msg) {
++				RTW_INFO("%s %d before\n", __func__, index);
++				dump_ies(RTW_DBGDUMP, ies, ies_len);
++
++				RTW_INFO("ies:%p, ies_len:%u\n", ies, ies_len);
++				RTW_INFO("target_ie:%p, target_ie_len:%u\n", target_ie, target_ie_len);
++				RTW_INFO("next_ie:%p, remain_len:%u\n", next_ie, remain_len);
++			}
++
++			_rtw_memmove(target_ie, next_ie, remain_len);
++			_rtw_memset(target_ie + remain_len, 0, target_ie_len);
++			ies_len -= target_ie_len;
++
++			if (DBG_DEL_WFD_IE && msg) {
++				RTW_INFO("%s %d after\n", __func__, index);
++				dump_ies(RTW_DBGDUMP, ies, ies_len);
++			}
++
++			index++;
++		} else
++			break;
++	}
++
++	return ies_len;
++}
++
++uint rtw_del_wfd_attr(u8 *ie, uint ielen_ori, u8 attr_id)
++{
++#define DBG_DEL_WFD_ATTR 0
++
++	u8 *target_attr;
++	u32 target_attr_len;
++	uint ielen = ielen_ori;
++	int index = 0;
++
++	while (1) {
++		target_attr = rtw_get_wfd_attr(ie, ielen, attr_id, NULL, &target_attr_len);
++		if (target_attr && target_attr_len) {
++			u8 *next_attr = target_attr + target_attr_len;
++			uint remain_len = ielen - (next_attr - ie);
++
++			if (DBG_DEL_WFD_ATTR) {
++				RTW_INFO("%s %d before\n", __func__, index);
++				dump_ies(RTW_DBGDUMP, ie, ielen);
++
++				RTW_INFO("ie:%p, ielen:%u\n", ie, ielen);
++				RTW_INFO("target_attr:%p, target_attr_len:%u\n", target_attr, target_attr_len);
++				RTW_INFO("next_attr:%p, remain_len:%u\n", next_attr, remain_len);
++			}
++
++			_rtw_memmove(target_attr, next_attr, remain_len);
++			_rtw_memset(target_attr + remain_len, 0, target_attr_len);
++			*(ie + 1) -= target_attr_len;
++			ielen -= target_attr_len;
++
++			if (DBG_DEL_WFD_ATTR) {
++				RTW_INFO("%s %d after\n", __func__, index);
++				dump_ies(RTW_DBGDUMP, ie, ielen);
++			}
++
++			index++;
++		} else
++			break;
++	}
++
++	return ielen;
++}
++
++inline u8 *rtw_bss_ex_get_wfd_ie(WLAN_BSSID_EX *bss_ex, u8 *wfd_ie, uint *wfd_ielen)
++{
++	return rtw_get_wfd_ie(BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex), wfd_ie, wfd_ielen);
++}
++
++void rtw_bss_ex_del_wfd_ie(WLAN_BSSID_EX *bss_ex)
++{
++#define DBG_BSS_EX_DEL_WFD_IE 0
++	u8 *ies = BSS_EX_TLV_IES(bss_ex);
++	uint ies_len_ori = BSS_EX_TLV_IES_LEN(bss_ex);
++	uint ies_len;
++
++	ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_BSS_EX_DEL_WFD_IE ? __func__ : NULL);
++	bss_ex->IELength -= ies_len_ori - ies_len;
++}
++
++void rtw_bss_ex_del_wfd_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id)
++{
++#define DBG_BSS_EX_DEL_WFD_ATTR 0
++
++	u8 *ies = BSS_EX_TLV_IES(bss_ex);
++	uint ies_len = BSS_EX_TLV_IES_LEN(bss_ex);
++
++	u8 *ie;
++	uint ie_len, ie_len_ori;
++
++	int index = 0;
++
++	while (1) {
++		ie = rtw_get_wfd_ie(ies, ies_len, NULL, &ie_len_ori);
++		if (ie) {
++			u8 *next_ie_ori = ie + ie_len_ori;
++			uint remain_len = bss_ex->IELength - (next_ie_ori - bss_ex->IEs);
++			u8 has_target_attr = 0;
++
++			if (DBG_BSS_EX_DEL_WFD_ATTR) {
++				if (rtw_get_wfd_attr(ie, ie_len_ori, attr_id, NULL, NULL)) {
++					RTW_INFO("%s %d before\n", __func__, index);
++					dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex));
++
++					RTW_INFO("ies:%p, ies_len:%u\n", ies, ies_len);
++					RTW_INFO("ie:%p, ie_len_ori:%u\n", ie, ie_len_ori);
++					RTW_INFO("next_ie_ori:%p, remain_len:%u\n", next_ie_ori, remain_len);
++					has_target_attr = 1;
++				}
++			}
++
++			ie_len = rtw_del_wfd_attr(ie, ie_len_ori, attr_id);
++			if (ie_len != ie_len_ori) {
++				u8 *next_ie = ie + ie_len;
++
++				_rtw_memmove(next_ie, next_ie_ori, remain_len);
++				_rtw_memset(next_ie + remain_len, 0, ie_len_ori - ie_len);
++				bss_ex->IELength -= ie_len_ori - ie_len;
++
++				ies = next_ie;
++			} else
++				ies = next_ie_ori;
++
++			if (DBG_BSS_EX_DEL_WFD_ATTR) {
++				if (has_target_attr) {
++					RTW_INFO("%s %d after\n", __func__, index);
++					dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex));
++				}
++			}
++
++			ies_len = remain_len;
++
++			index++;
++		} else
++			break;
++	}
++}
++
++#ifdef CONFIG_RTW_MULTI_AP
++void dump_multi_ap_ie(void *sel, const u8 *ie, u32 ie_len)
++{
++	const u8 *pos = ie;
++	u8 id;
++	u8 len;
++
++	const u8 *multi_ap_ie;
++	uint multi_ap_ielen;
++
++	multi_ap_ie = rtw_get_ie_ex(ie, ie_len, WLAN_EID_VENDOR_SPECIFIC, MULTI_AP_OUI, 4, NULL, &multi_ap_ielen);
++	if (multi_ap_ie != ie || multi_ap_ielen == 0)
++		return;
++
++	pos += 6;
++	while (pos - ie + 2 <= ie_len) {
++		id = *pos;
++		len = *(pos + 1);
++
++		RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u%s\n", __func__, id, len
++			, ((pos - ie + 2 + len) <= ie_len) ? "" : "(exceed ie_len)");
++		RTW_DUMP_SEL(sel, pos + 2, len);
++
++		pos += (2 + len);
++	}
++}
++
++/**
++ * rtw_get_multi_ap_ext - Search Multi-AP IE from a series of IEs and return extension subelement value
++ * @ies: Address of IEs to search
++ * @ies_len: Length limit from in_ie
++ *
++ * Returns: The address of the target IE found, or NULL
++ */
++u8 rtw_get_multi_ap_ie_ext(const u8 *ies, int ies_len)
++{
++	u8 *ie;
++	uint ielen;
++	u8 val = 0;
++
++	ie = rtw_get_ie_ex(ies, ies_len, WLAN_EID_VENDOR_SPECIFIC, MULTI_AP_OUI, 4, NULL, &ielen);
++	if (ielen < 9)
++		goto exit;
++
++	if (ie[6] != MULTI_AP_SUB_ELEM_TYPE)
++		goto exit;
++
++	val = ie[8];
++
++exit:
++	return val;
++}
++
++u8 *rtw_set_multi_ap_ie_ext(u8 *pbuf, uint *frlen, u8 val)
++{
++	u8 cont_len = 7;
++
++	*pbuf++ = WLAN_EID_VENDOR_SPECIFIC;
++	*pbuf++ = cont_len;
++	_rtw_memcpy(pbuf, MULTI_AP_OUI, 4);
++	pbuf += 4;
++	*pbuf++ = MULTI_AP_SUB_ELEM_TYPE;
++	*pbuf++ = 1; /* len */
++	*pbuf++ = val;
++
++	if (frlen)
++		*frlen = *frlen + (cont_len + 2);
++
++	return pbuf;
++}
++#endif /* CONFIG_RTW_MULTI_AP */
++
++/* Baron adds to avoid FreeBSD warning */
++int ieee80211_is_empty_essid(const char *essid, int essid_len)
++{
++	/* Single white space is for Linksys APs */
++	if (essid_len == 1 && essid[0] == ' ')
++		return 1;
++
++	/* Otherwise, if the entire essid is 0, we assume it is hidden */
++	while (essid_len) {
++		essid_len--;
++		if (essid[essid_len] != '\0')
++			return 0;
++	}
++
++	return 1;
++}
++
++int ieee80211_get_hdrlen(u16 fc)
++{
++	int hdrlen = 24;
++
++	switch (WLAN_FC_GET_TYPE(fc)) {
++	case RTW_IEEE80211_FTYPE_DATA:
++		if (fc & RTW_IEEE80211_STYPE_QOS_DATA)
++			hdrlen += 2;
++		if ((fc & RTW_IEEE80211_FCTL_FROMDS) && (fc & RTW_IEEE80211_FCTL_TODS))
++			hdrlen += 6; /* Addr4 */
++		break;
++	case RTW_IEEE80211_FTYPE_CTL:
++		switch (WLAN_FC_GET_STYPE(fc)) {
++		case RTW_IEEE80211_STYPE_CTS:
++		case RTW_IEEE80211_STYPE_ACK:
++			hdrlen = 10;
++			break;
++		default:
++			hdrlen = 16;
++			break;
++		}
++		break;
++	}
++
++	return hdrlen;
++}
++
++u8	rtw_ht_mcsset_to_nss(u8 *supp_mcs_set)
++{
++	u8 nss = 1;
++
++	if (supp_mcs_set[3])
++		nss = 4;
++	else if (supp_mcs_set[2])
++		nss = 3;
++	else if (supp_mcs_set[1])
++		nss = 2;
++	else if (supp_mcs_set[0])
++		nss = 1;
++	else
++		RTW_INFO("%s,%d, warning! supp_mcs_set is zero\n", __func__, __LINE__);
++	/* RTW_INFO("%s HT: %dSS\n", __FUNCTION__, nss); */
++	return nss;
++}
++
++u32	rtw_ht_mcs_set_to_bitmap(u8 *mcs_set, u8 nss)
++{
++	u8 i;
++	u32 bitmap = 0;
++
++	for (i = 0; i < nss; i++)
++		bitmap |= mcs_set[i] << (i * 8);
++
++	RTW_INFO("ht_mcs_set=%02x %02x %02x %02x, nss=%u, bitmap=%08x\n"
++		, mcs_set[0], mcs_set[1], mcs_set[2], mcs_set[3], nss, bitmap);
++
++	return bitmap;
++}
++
++/* show MCS rate, unit: 100Kbps */
++u16 rtw_ht_mcs_rate(u8 bw_40MHz, u8 short_GI, unsigned char *MCS_rate)
++{
++	u16 max_rate = 0;
++
++	if (MCS_rate[3]) {
++		if (MCS_rate[3] & BIT(7))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 6000 : 5400) : ((short_GI) ? 2889 : 2600);
++		else if (MCS_rate[3] & BIT(6))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 5400 : 4860) : ((short_GI) ? 2600 : 2340);
++		else if (MCS_rate[3] & BIT(5))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 4800 : 4320) : ((short_GI) ? 2311 : 2080);
++		else if (MCS_rate[3] & BIT(4))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 3600 : 3240) : ((short_GI) ? 1733 : 1560);
++		else if (MCS_rate[3] & BIT(3))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 2400 : 2160) : ((short_GI) ? 1156 : 1040);
++		else if (MCS_rate[3] & BIT(2))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 1800 : 1620) : ((short_GI) ? 867 : 780);
++		else if (MCS_rate[3] & BIT(1))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 1200 : 1080) : ((short_GI) ? 578 : 520);
++		else if (MCS_rate[3] & BIT(0))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 600 : 540) : ((short_GI) ? 289 : 260);
++	} else if (MCS_rate[2]) {
++		if (MCS_rate[2] & BIT(7))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 4500 : 4050) : ((short_GI) ? 2167 : 1950);
++		else if (MCS_rate[2] & BIT(6))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 4050 : 3645) : ((short_GI) ? 1950 : 1750);
++		else if (MCS_rate[2] & BIT(5))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 3600 : 3240) : ((short_GI) ? 1733 : 1560);
++		else if (MCS_rate[2] & BIT(4))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 2700 : 2430) : ((short_GI) ? 1300 : 1170);
++		else if (MCS_rate[2] & BIT(3))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 1800 : 1620) : ((short_GI) ? 867 : 780);
++		else if (MCS_rate[2] & BIT(2))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 1350 : 1215) : ((short_GI) ? 650 : 585);
++		else if (MCS_rate[2] & BIT(1))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 900 : 810) : ((short_GI) ? 433 : 390);
++		else if (MCS_rate[2] & BIT(0))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 450 : 405) : ((short_GI) ? 217 : 195);
++	} else if (MCS_rate[1]) {
++		if (MCS_rate[1] & BIT(7))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 3000 : 2700) : ((short_GI) ? 1444 : 1300);
++		else if (MCS_rate[1] & BIT(6))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 2700 : 2430) : ((short_GI) ? 1300 : 1170);
++		else if (MCS_rate[1] & BIT(5))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 2400 : 2160) : ((short_GI) ? 1156 : 1040);
++		else if (MCS_rate[1] & BIT(4))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 1800 : 1620) : ((short_GI) ? 867 : 780);
++		else if (MCS_rate[1] & BIT(3))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 1200 : 1080) : ((short_GI) ? 578 : 520);
++		else if (MCS_rate[1] & BIT(2))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 900 : 810) : ((short_GI) ? 433 : 390);
++		else if (MCS_rate[1] & BIT(1))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 600 : 540) : ((short_GI) ? 289 : 260);
++		else if (MCS_rate[1] & BIT(0))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 300 : 270) : ((short_GI) ? 144 : 130);
++	} else {
++		if (MCS_rate[0] & BIT(7))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 1500 : 1350) : ((short_GI) ? 722 : 650);
++		else if (MCS_rate[0] & BIT(6))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 1350 : 1215) : ((short_GI) ? 650 : 585);
++		else if (MCS_rate[0] & BIT(5))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 1200 : 1080) : ((short_GI) ? 578 : 520);
++		else if (MCS_rate[0] & BIT(4))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 900 : 810) : ((short_GI) ? 433 : 390);
++		else if (MCS_rate[0] & BIT(3))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 600 : 540) : ((short_GI) ? 289 : 260);
++		else if (MCS_rate[0] & BIT(2))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 450 : 405) : ((short_GI) ? 217 : 195);
++		else if (MCS_rate[0] & BIT(1))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 300 : 270) : ((short_GI) ? 144 : 130);
++		else if (MCS_rate[0] & BIT(0))
++			max_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65);
++	}
++
++	return max_rate;
++}
++
++int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8 *category, u8 *action)
++{
++	const u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr);
++	u16 fc;
++	u8 c;
++	u8 a = ACT_PUBLIC_MAX;
++
++	fc = le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)frame)->frame_ctl);
++
++	if ((fc & (RTW_IEEE80211_FCTL_FTYPE | RTW_IEEE80211_FCTL_STYPE))
++	    != (RTW_IEEE80211_FTYPE_MGMT | RTW_IEEE80211_STYPE_ACTION)
++	   )
++		return _FALSE;
++
++	c = frame_body[0];
++
++	switch (c) {
++	case RTW_WLAN_CATEGORY_P2P: /* vendor-specific */
++		break;
++	default:
++		a = frame_body[1];
++	}
++
++	if (category)
++		*category = c;
++	if (action)
++		*action = a;
++
++	return _TRUE;
++}
++
++static const char *_action_public_str[] = {
++	"ACT_PUB_BSSCOEXIST",
++	"ACT_PUB_DSE_ENABLE",
++	"ACT_PUB_DSE_DEENABLE",
++	"ACT_PUB_DSE_REG_LOCATION",
++	"ACT_PUB_EXT_CHL_SWITCH",
++	"ACT_PUB_DSE_MSR_REQ",
++	"ACT_PUB_DSE_MSR_RPRT",
++	"ACT_PUB_MP",
++	"ACT_PUB_DSE_PWR_CONSTRAINT",
++	"ACT_PUB_VENDOR",
++	"ACT_PUB_GAS_INITIAL_REQ",
++	"ACT_PUB_GAS_INITIAL_RSP",
++	"ACT_PUB_GAS_COMEBACK_REQ",
++	"ACT_PUB_GAS_COMEBACK_RSP",
++	"ACT_PUB_TDLS_DISCOVERY_RSP",
++	"ACT_PUB_LOCATION_TRACK",
++	"ACT_PUB_RSVD",
++};
++
++const char *action_public_str(u8 action)
++{
++	action = (action >= ACT_PUBLIC_MAX) ? ACT_PUBLIC_MAX : action;
++	return _action_public_str[action];
++}
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_io.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_io.c
+new file mode 100644
+index 000000000..734d3e591
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_io.c
+@@ -0,0 +1,952 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*
++
++The purpose of rtw_io.c
++
++a. provides the API
++
++b. provides the protocol engine
++
++c. provides the software interface between caller and the hardware interface
++
++
++Compiler Flag Option:
++
++1. CONFIG_SDIO_HCI:
++    a. USE_SYNC_IRP:  Only sync operations are provided.
++    b. USE_ASYNC_IRP:Both sync/async operations are provided.
++
++2. CONFIG_USB_HCI:
++   a. USE_ASYNC_IRP: Both sync/async operations are provided.
++
++3. CONFIG_CFIO_HCI:
++   b. USE_SYNC_IRP: Only sync operations are provided.
++
++
++Only sync read/rtw_write_mem operations are provided.
++
++jackson@realtek.com.tw
++
++*/
++
++#define _RTW_IO_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_PLATFORM_RTL8197D)
++	#define rtw_le16_to_cpu(val)		val
++	#define rtw_le32_to_cpu(val)		val
++	#define rtw_cpu_to_le16(val)		val
++	#define rtw_cpu_to_le32(val)		val
++#else
++	#define rtw_le16_to_cpu(val)		le16_to_cpu(val)
++	#define rtw_le32_to_cpu(val)		le32_to_cpu(val)
++	#define rtw_cpu_to_le16(val)		cpu_to_le16(val)
++	#define rtw_cpu_to_le32(val)		cpu_to_le32(val)
++#endif
++
++
++u8 _rtw_read8(_adapter *adapter, u32 addr)
++{
++	u8 r_val;
++	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
++	u8(*_read8)(struct intf_hdl *pintfhdl, u32 addr);
++	_read8 = pintfhdl->io_ops._read8;
++
++	r_val = _read8(pintfhdl, addr);
++	return r_val;
++}
++
++u16 _rtw_read16(_adapter *adapter, u32 addr)
++{
++	u16 r_val;
++	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
++	u16(*_read16)(struct intf_hdl *pintfhdl, u32 addr);
++	_read16 = pintfhdl->io_ops._read16;
++
++	r_val = _read16(pintfhdl, addr);
++	return rtw_le16_to_cpu(r_val);
++}
++
++u32 _rtw_read32(_adapter *adapter, u32 addr)
++{
++	u32 r_val;
++	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
++	u32(*_read32)(struct intf_hdl *pintfhdl, u32 addr);
++	_read32 = pintfhdl->io_ops._read32;
++
++	r_val = _read32(pintfhdl, addr);
++	return rtw_le32_to_cpu(r_val);
++
++}
++
++int _rtw_write8(_adapter *adapter, u32 addr, u8 val)
++{
++	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
++	int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
++	int ret;
++	_write8 = pintfhdl->io_ops._write8;
++
++	ret = _write8(pintfhdl, addr, val);
++
++	return RTW_STATUS_CODE(ret);
++}
++int _rtw_write16(_adapter *adapter, u32 addr, u16 val)
++{
++	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
++	int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
++	int ret;
++	_write16 = pintfhdl->io_ops._write16;
++
++	val = rtw_cpu_to_le16(val);
++	ret = _write16(pintfhdl, addr, val);
++
++	return RTW_STATUS_CODE(ret);
++}
++int _rtw_write32(_adapter *adapter, u32 addr, u32 val)
++{
++	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
++	int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
++	int ret;
++	_write32 = pintfhdl->io_ops._write32;
++
++	val = rtw_cpu_to_le32(val);
++	ret = _write32(pintfhdl, addr, val);
++
++	return RTW_STATUS_CODE(ret);
++}
++
++int _rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *pdata)
++{
++	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct	intf_hdl	*pintfhdl = (struct intf_hdl *)(&(pio_priv->intf));
++	int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);
++	int ret;
++	_writeN = pintfhdl->io_ops._writeN;
++
++	ret = _writeN(pintfhdl, addr, length, pdata);
++
++	return RTW_STATUS_CODE(ret);
++}
++
++#ifdef CONFIG_SDIO_HCI
++u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr)
++{
++	u8 r_val = 0x00;
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct intf_hdl *pintfhdl = &(pio_priv->intf);
++	u8(*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr);
++
++	_sd_f0_read8 = pintfhdl->io_ops._sd_f0_read8;
++
++	if (_sd_f0_read8)
++		r_val = _sd_f0_read8(pintfhdl, addr);
++	else
++		RTW_WARN(FUNC_ADPT_FMT" _sd_f0_read8 callback is NULL\n", FUNC_ADPT_ARG(adapter));
++
++	return r_val;
++}
++
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++u8 _rtw_sd_iread8(_adapter *adapter, u32 addr)
++{
++	u8 r_val = 0x00;
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct intf_hdl *pintfhdl = &(pio_priv->intf);
++	u8(*_sd_iread8)(struct intf_hdl *pintfhdl, u32 addr);
++
++	_sd_iread8 = pintfhdl->io_ops._sd_iread8;
++
++	if (_sd_iread8)
++		r_val = _sd_iread8(pintfhdl, addr);
++	else
++		RTW_ERR(FUNC_ADPT_FMT" _sd_iread8 callback is NULL\n", FUNC_ADPT_ARG(adapter));
++
++	return r_val;
++}
++
++u16 _rtw_sd_iread16(_adapter *adapter, u32 addr)
++{
++	u16 r_val = 0x00;
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct intf_hdl *pintfhdl = &(pio_priv->intf);
++	u16(*_sd_iread16)(struct intf_hdl *pintfhdl, u32 addr);
++
++	_sd_iread16 = pintfhdl->io_ops._sd_iread16;
++
++	if (_sd_iread16)
++		r_val = _sd_iread16(pintfhdl, addr);
++	else
++		RTW_ERR(FUNC_ADPT_FMT" _sd_iread16 callback is NULL\n", FUNC_ADPT_ARG(adapter));
++
++	return r_val;
++}
++
++u32 _rtw_sd_iread32(_adapter *adapter, u32 addr)
++{
++	u32 r_val = 0x00;
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct intf_hdl *pintfhdl = &(pio_priv->intf);
++	u32(*_sd_iread32)(struct intf_hdl *pintfhdl, u32 addr);
++
++	_sd_iread32 = pintfhdl->io_ops._sd_iread32;
++
++	if (_sd_iread32)
++		r_val = _sd_iread32(pintfhdl, addr);
++	else
++		RTW_ERR(FUNC_ADPT_FMT" _sd_iread32 callback is NULL\n", FUNC_ADPT_ARG(adapter));
++
++	return r_val;
++}
++
++int _rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val)
++{
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct intf_hdl *pintfhdl = &(pio_priv->intf);
++	int (*_sd_iwrite8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
++	int ret = -1;
++
++	_sd_iwrite8 = pintfhdl->io_ops._sd_iwrite8;
++
++	if (_sd_iwrite8)
++		ret = _sd_iwrite8(pintfhdl, addr, val);
++	else
++		RTW_ERR(FUNC_ADPT_FMT" _sd_iwrite8 callback is NULL\n", FUNC_ADPT_ARG(adapter));
++
++	return RTW_STATUS_CODE(ret);
++}
++
++int _rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val)
++{
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct intf_hdl *pintfhdl = &(pio_priv->intf);
++	int (*_sd_iwrite16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
++	int ret = -1;
++
++	_sd_iwrite16 = pintfhdl->io_ops._sd_iwrite16;
++
++	if (_sd_iwrite16)
++		ret = _sd_iwrite16(pintfhdl, addr, val);
++	else
++		RTW_ERR(FUNC_ADPT_FMT" _sd_iwrite16 callback is NULL\n", FUNC_ADPT_ARG(adapter));
++
++	return RTW_STATUS_CODE(ret);
++}
++int _rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val)
++{
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct intf_hdl *pintfhdl = &(pio_priv->intf);
++	int (*_sd_iwrite32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
++	int ret = -1;
++
++	_sd_iwrite32 = pintfhdl->io_ops._sd_iwrite32;
++
++	if (_sd_iwrite32)
++		ret = _sd_iwrite32(pintfhdl, addr, val);
++	else
++		RTW_ERR(FUNC_ADPT_FMT" _sd_iwrite32 callback is NULL\n", FUNC_ADPT_ARG(adapter));
++
++	return RTW_STATUS_CODE(ret);
++}
++
++#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
++
++#endif /* CONFIG_SDIO_HCI */
++
++int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val)
++{
++	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
++	int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
++	int ret;
++	_write8_async = pintfhdl->io_ops._write8_async;
++
++	ret = _write8_async(pintfhdl, addr, val);
++
++	return RTW_STATUS_CODE(ret);
++}
++int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val)
++{
++	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
++	int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
++	int ret;
++	_write16_async = pintfhdl->io_ops._write16_async;
++	val = rtw_cpu_to_le16(val);
++	ret = _write16_async(pintfhdl, addr, val);
++
++	return RTW_STATUS_CODE(ret);
++}
++int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val)
++{
++	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
++	int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
++	int ret;
++	_write32_async = pintfhdl->io_ops._write32_async;
++	val = rtw_cpu_to_le32(val);
++	ret = _write32_async(pintfhdl, addr, val);
++
++	return RTW_STATUS_CODE(ret);
++}
++
++void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
++{
++	void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
++
++
++	if (RTW_CANNOT_RUN(adapter)) {
++		return;
++	}
++
++	_read_mem = pintfhdl->io_ops._read_mem;
++
++	_read_mem(pintfhdl, addr, cnt, pmem);
++
++
++}
++
++void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
++{
++	void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
++
++
++	_write_mem = pintfhdl->io_ops._write_mem;
++
++	_write_mem(pintfhdl, addr, cnt, pmem);
++
++
++}
++
++void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
++{
++	u32(*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
++
++
++	if (RTW_CANNOT_RUN(adapter)) {
++		return;
++	}
++
++	_read_port = pintfhdl->io_ops._read_port;
++
++	_read_port(pintfhdl, addr, cnt, pmem);
++
++
++}
++
++void _rtw_read_port_cancel(_adapter *adapter)
++{
++	void (*_read_port_cancel)(struct intf_hdl *pintfhdl);
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct intf_hdl *pintfhdl = &(pio_priv->intf);
++
++	_read_port_cancel = pintfhdl->io_ops._read_port_cancel;
++
++	RTW_DISABLE_FUNC(adapter, DF_RX_BIT);
++
++	if (_read_port_cancel)
++		_read_port_cancel(pintfhdl);
++}
++
++u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
++{
++	u32(*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
++	u32 ret = _SUCCESS;
++
++
++	_write_port = pintfhdl->io_ops._write_port;
++
++	ret = _write_port(pintfhdl, addr, cnt, pmem);
++
++
++	return ret;
++}
++
++u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms)
++{
++	int ret = _SUCCESS;
++	struct xmit_buf *pxmitbuf = (struct xmit_buf *)pmem;
++	struct submit_ctx sctx;
++
++	rtw_sctx_init(&sctx, timeout_ms);
++	pxmitbuf->sctx = &sctx;
++
++	ret = _rtw_write_port(adapter, addr, cnt, pmem);
++
++	if (ret == _SUCCESS) {
++		ret = rtw_sctx_wait(&sctx, __func__);
++
++		if (ret != _SUCCESS)
++			pxmitbuf->sctx = NULL;
++	}
++
++	return ret;
++}
++
++void _rtw_write_port_cancel(_adapter *adapter)
++{
++	void (*_write_port_cancel)(struct intf_hdl *pintfhdl);
++	struct io_priv *pio_priv = &adapter->iopriv;
++	struct intf_hdl *pintfhdl = &(pio_priv->intf);
++
++	_write_port_cancel = pintfhdl->io_ops._write_port_cancel;
++
++	RTW_DISABLE_FUNC(adapter, DF_TX_BIT);
++
++	if (_write_port_cancel)
++		_write_port_cancel(pintfhdl);
++}
++int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter, struct _io_ops *pops))
++{
++	struct io_priv	*piopriv = &padapter->iopriv;
++	struct intf_hdl *pintf = &piopriv->intf;
++
++	if (set_intf_ops == NULL)
++		return _FAIL;
++
++	piopriv->padapter = padapter;
++	pintf->padapter = padapter;
++	pintf->pintf_dev = adapter_to_dvobj(padapter);
++
++	set_intf_ops(padapter, &pintf->io_ops);
++
++	return _SUCCESS;
++}
++
++/*
++* Increase and check if the continual_io_error of this @param dvobjprive is larger than MAX_CONTINUAL_IO_ERR
++* @return _TRUE:
++* @return _FALSE:
++*/
++int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj)
++{
++	int ret = _FALSE;
++	int value;
++
++	value = ATOMIC_INC_RETURN(&dvobj->continual_io_error);
++	if (value > MAX_CONTINUAL_IO_ERR) {
++		RTW_INFO("[dvobj:%p][ERROR] continual_io_error:%d > %d\n", dvobj, value, MAX_CONTINUAL_IO_ERR);
++		ret = _TRUE;
++	} else {
++		/* RTW_INFO("[dvobj:%p] continual_io_error:%d\n", dvobj, value); */
++	}
++	return ret;
++}
++
++/*
++* Set the continual_io_error of this @param dvobjprive to 0
++*/
++void rtw_reset_continual_io_error(struct dvobj_priv *dvobj)
++{
++	ATOMIC_SET(&dvobj->continual_io_error, 0);
++}
++
++#ifdef DBG_IO
++#define RTW_IO_SNIFF_TYPE_RANGE	0 /* specific address range is accessed */
++#define RTW_IO_SNIFF_TYPE_VALUE	1 /* value match for sniffed range */
++
++struct rtw_io_sniff_ent {
++	u8 chip;
++	u8 hci;
++	u32 addr;
++	u8 type;
++	union {
++		u32 end_addr;
++		struct {
++			u32 mask;
++			u32 val;
++			bool equal;
++		} vm; /* value match */
++	} u;
++	bool trace;
++	char *tag;
++	bool (*assert_protsel)(_adapter *adapter, u32 addr, u8 len);
++};
++
++#define RTW_IO_SNIFF_RANGE_ENT(_chip, _hci, _addr, _end_addr, _trace, _tag) \
++	{.chip = _chip, .hci = _hci, .addr = _addr, .u.end_addr = _end_addr, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_RANGE,}
++
++#define RTW_IO_SNIFF_RANGE_PROT_ENT(_chip, _hci, _addr, _end_addr, _assert_protsel, _tag) \
++	{.chip = _chip, .hci = _hci, .addr = _addr, .u.end_addr = _end_addr, .trace = 1, .assert_protsel = _assert_protsel, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_RANGE,}
++
++#define RTW_IO_SNIFF_VALUE_ENT(_chip, _hci, _addr, _mask, _val, _equal, _trace, _tag) \
++	{.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = _val, .u.vm.equal = _equal, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,}
++
++/* part or all sniffed range is enabled (not all 0) */
++#define RTW_IO_SNIFF_EN_ENT(_chip, _hci, _addr, _mask, _trace, _tag) \
++	{.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = 0, .u.vm.equal = 0, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,}
++
++/* part or all sniffed range is disabled (not all 1) */
++#define RTW_IO_SNIFF_DIS_ENT(_chip, _hci, _addr, _mask, _trace, _tag) \
++	{.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = 0xFFFFFFFF, .u.vm.equal = 0, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,}
++
++const struct rtw_io_sniff_ent read_sniff[] = {
++#ifdef DBG_IO_HCI_EN_CHK
++	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_SDIO, 0x02, 0x1FC, 1, "SDIO 0x02[8:2] not all 0"),
++	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_USB, 0x02, 0x1E0, 1, "USB 0x02[8:5] not all 0"),
++	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_PCIE, 0x02, 0x01C, 1, "PCI 0x02[4:2] not all 0"),
++#endif
++#ifdef DBG_IO_SNIFF_EXAMPLE
++	RTW_IO_SNIFF_RANGE_ENT(MAX_CHIP_TYPE, 0, 0x522, 0x522, 0, "read TXPAUSE"),
++	RTW_IO_SNIFF_DIS_ENT(MAX_CHIP_TYPE, 0, 0x02, 0x3, 0, "0x02[1:0] not all 1"),
++#endif
++#ifdef DBG_IO_PROT_SEL
++	RTW_IO_SNIFF_RANGE_PROT_ENT(MAX_CHIP_TYPE, 0, 0x1501, 0x1513, rtw_assert_protsel_port, "protsel port"),
++	RTW_IO_SNIFF_RANGE_PROT_ENT(MAX_CHIP_TYPE, 0, 0x153a, 0x153b, rtw_assert_protsel_atimdtim, "protsel atimdtim"),
++#endif
++};
++
++const int read_sniff_num = sizeof(read_sniff) / sizeof(struct rtw_io_sniff_ent);
++
++const struct rtw_io_sniff_ent write_sniff[] = {
++#ifdef DBG_IO_HCI_EN_CHK
++	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_SDIO, 0x02, 0x1FC, 1, "SDIO 0x02[8:2] not all 0"),
++	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_USB, 0x02, 0x1E0, 1, "USB 0x02[8:5] not all 0"),
++	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_PCIE, 0x02, 0x01C, 1, "PCI 0x02[4:2] not all 0"),
++#endif
++#ifdef DBG_IO_8822C_1TX_PATH_EN
++	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x1a04, 0xc0000000, 0x02, 1, 0, "write tx_path_en_cck A enabled"),
++	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x1a04, 0xc0000000, 0x01, 1, 0, "write tx_path_en_cck B enabled"),
++	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x1a04, 0xc0000000, 0x03, 1, 1, "write tx_path_en_cck AB enabled"),
++	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x03, 0x01, 1, 0, "write tx_path_en_ofdm_1sts A enabled"),
++	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x03, 0x02, 1, 0, "write tx_path_en_ofdm_1sts B enabled"),
++	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x03, 0x03, 1, 1, "write tx_path_en_ofdm_1sts AB enabled"),
++	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x30, 0x01, 1, 0, "write tx_path_en_ofdm_2sts A enabled"),
++	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x30, 0x02, 1, 0, "write tx_path_en_ofdm_2sts B enabled"),
++	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x30, 0x03, 1, 1, "write tx_path_en_ofdm_2sts AB enabled"),
++#endif
++#ifdef DBG_IO_SNIFF_EXAMPLE
++	RTW_IO_SNIFF_RANGE_ENT(MAX_CHIP_TYPE, 0, 0x522, 0x522, 0, "write TXPAUSE"),
++	RTW_IO_SNIFF_DIS_ENT(MAX_CHIP_TYPE, 0, 0x02, 0x3, 0, "0x02[1:0] not all 1"),
++#endif
++};
++
++const int write_sniff_num = sizeof(write_sniff) / sizeof(struct rtw_io_sniff_ent);
++
++static bool match_io_sniff_ranges(_adapter *adapter
++	, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u16 len)
++{
++
++	/* check if IO range after sniff end address */
++	if (addr > sniff->u.end_addr)
++		return 0;
++
++	if (sniff->assert_protsel &&
++	    sniff->assert_protsel(adapter, addr, len))
++		return 0;
++
++	return 1;
++}
++
++static bool match_io_sniff_value(_adapter *adapter
++	, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val)
++{
++	u8 sniff_len;
++	s8 mask_shift;
++	u32 mask;
++	s8 value_shift;
++	u32 value;
++	bool ret = 0;
++
++	/* check if IO range after sniff end address */
++	sniff_len = 4;
++	while (!(sniff->u.vm.mask & (0xFF << ((sniff_len - 1) * 8)))) {
++		sniff_len--;
++		if (sniff_len == 0)
++			goto exit;
++	}
++	if (sniff->addr + sniff_len <= addr)
++		goto exit;
++
++	/* align to IO addr */
++	mask_shift = (sniff->addr - addr) * 8;
++	value_shift = mask_shift + bitshift(sniff->u.vm.mask);
++	if (mask_shift > 0)
++		mask = sniff->u.vm.mask << mask_shift;
++	else if (mask_shift < 0)
++		mask = sniff->u.vm.mask >> -mask_shift;
++	else
++		mask = sniff->u.vm.mask;
++
++	if (value_shift > 0)
++		value = sniff->u.vm.val << value_shift;
++	else if (mask_shift < 0)
++		value = sniff->u.vm.val >> -value_shift;
++	else
++		value = sniff->u.vm.val;
++
++	if ((sniff->u.vm.equal && (mask & val) == (mask & value))
++		|| (!sniff->u.vm.equal && (mask & val) != (mask & value))
++	) {
++		ret = 1;
++		if (0)
++			RTW_INFO(FUNC_ADPT_FMT" addr:0x%x len:%u val:0x%x (i:%d sniff_len:%u m_shift:%d mask:0x%x v_shifd:%d value:0x%x equal:%d)\n"
++				, FUNC_ADPT_ARG(adapter), addr, len, val, i, sniff_len, mask_shift, mask, value_shift, value, sniff->u.vm.equal);
++	}
++
++exit:
++	return ret;
++}
++
++static bool match_io_sniff(_adapter *adapter
++	, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val)
++{
++	bool ret = 0;
++
++	if (sniff->chip != MAX_CHIP_TYPE
++		&& sniff->chip != rtw_get_chip_type(adapter))
++		goto exit;
++	if (sniff->hci
++		&& !(sniff->hci & rtw_get_intf_type(adapter)))
++		goto exit;
++	if (sniff->addr >= addr + len) /* IO range below sniff start address */
++		goto exit;
++
++	switch (sniff->type) {
++	case RTW_IO_SNIFF_TYPE_RANGE:
++		ret = match_io_sniff_ranges(adapter, sniff, i, addr, len);
++		break;
++	case RTW_IO_SNIFF_TYPE_VALUE:
++		if (len == 1 || len == 2 || len == 4)
++			ret = match_io_sniff_value(adapter, sniff, i, addr, len, val);
++		break;
++	default:
++		rtw_warn_on(1);
++		break;
++	}
++
++exit:
++	return ret;
++}
++
++u32 match_read_sniff(_adapter *adapter, u32 addr, u16 len, u32 val)
++{
++	int i;
++	bool trace = 0;
++	u32 match = 0;
++
++	for (i = 0; i < read_sniff_num; i++) {
++		if (match_io_sniff(adapter, &read_sniff[i], i, addr, len, val)) {
++			match++;
++			trace |= read_sniff[i].trace;
++			if (read_sniff[i].tag)
++				RTW_INFO("DBG_IO TAG %s\n", read_sniff[i].tag);
++		}
++	}
++
++	rtw_warn_on(trace);
++
++	return match;
++}
++
++u32 match_write_sniff(_adapter *adapter, u32 addr, u16 len, u32 val)
++{
++	int i;
++	bool trace = 0;
++	u32 match = 0;
++
++	for (i = 0; i < write_sniff_num; i++) {
++		if (match_io_sniff(adapter, &write_sniff[i], i, addr, len, val)) {
++			match++;
++			trace |= write_sniff[i].trace;
++			if (write_sniff[i].tag)
++				RTW_INFO("DBG_IO TAG %s\n", write_sniff[i].tag);
++		}
++	}
++
++	rtw_warn_on(trace);
++
++	return match;
++}
++
++struct rf_sniff_ent {
++	u8 path;
++	u16 reg;
++	u32 mask;
++};
++
++struct rf_sniff_ent rf_read_sniff_ranges[] = {
++	/* example for all path addr 0x55 with all RF Reg mask */
++	/* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */
++};
++
++struct rf_sniff_ent rf_write_sniff_ranges[] = {
++	/* example for all path addr 0x55 with all RF Reg mask */
++	/* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */
++};
++
++int rf_read_sniff_num = sizeof(rf_read_sniff_ranges) / sizeof(struct rf_sniff_ent);
++int rf_write_sniff_num = sizeof(rf_write_sniff_ranges) / sizeof(struct rf_sniff_ent);
++
++bool match_rf_read_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask)
++{
++	int i;
++
++	for (i = 0; i < rf_read_sniff_num; i++) {
++		if (rf_read_sniff_ranges[i].path == MAX_RF_PATH || rf_read_sniff_ranges[i].path == path)
++			if (addr == rf_read_sniff_ranges[i].reg && (mask & rf_read_sniff_ranges[i].mask))
++				return _TRUE;
++	}
++
++	return _FALSE;
++}
++
++bool match_rf_write_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask)
++{
++	int i;
++
++	for (i = 0; i < rf_write_sniff_num; i++) {
++		if (rf_write_sniff_ranges[i].path == MAX_RF_PATH || rf_write_sniff_ranges[i].path == path)
++			if (addr == rf_write_sniff_ranges[i].reg && (mask & rf_write_sniff_ranges[i].mask))
++				return _TRUE;
++	}
++
++	return _FALSE;
++}
++
++void dbg_rtw_reg_read_monitor(_adapter *adapter, u32 addr, u32 len, u32 val, const char *caller, const int line)
++{
++	if (match_read_sniff(adapter, addr, len, val)) {
++		switch (len) {
++		case 1:
++			RTW_INFO("DBG_IO %s:%d read8(0x%04x) return 0x%02x\n"
++				, caller, line, addr, val);
++			break;
++		case 2:
++			RTW_INFO("DBG_IO %s:%d read16(0x%04x) return 0x%04x\n"
++				, caller, line, addr, val);
++			break;
++		case 4:
++			RTW_INFO("DBG_IO %s:%d read32(0x%04x) return 0x%08x\n"
++				, caller, line, addr, val);
++			break;
++		default:
++			RTW_INFO("DBG_IO %s:%d readN(0x%04x, %u)\n"
++				, caller, line, addr, len);
++		}
++	}
++}
++
++void dbg_rtw_reg_write_monitor(_adapter *adapter, u32 addr, u32 len, u32 val, const char *caller, const int line)
++{
++	if (match_write_sniff(adapter, addr, len, val)) {
++		switch (len) {
++		case 1:
++			RTW_INFO("DBG_IO %s:%d write8(0x%04x, 0x%02x)\n"
++				, caller, line, addr, val);
++			break;
++		case 2:
++			RTW_INFO("DBG_IO %s:%d write16(0x%04x, 0x%04x)\n"
++				, caller, line, addr, val);
++			break;
++		case 4:
++			RTW_INFO("DBG_IO %s:%d write32(0x%04x, 0x%08x)\n"
++				, caller, line, addr, val);
++			break;
++		default:
++			RTW_INFO("DBG_IO %s:%d rtw_writeN(0x%04x, %u)\n"
++				, caller, line, addr, len);
++		}
++	}
++}
++
++u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line)
++{
++	u8 val = _rtw_read8(adapter, addr);
++
++	if (match_read_sniff(adapter, addr, 1, val)) {
++		RTW_INFO("DBG_IO %s:%d rtw_read8(0x%04x) return 0x%02x\n"
++			, caller, line, addr, val);
++	}
++
++	return val;
++}
++
++u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line)
++{
++	u16 val = _rtw_read16(adapter, addr);
++
++	if (match_read_sniff(adapter, addr, 2, val)) {
++		RTW_INFO("DBG_IO %s:%d rtw_read16(0x%04x) return 0x%04x\n"
++			, caller, line, addr, val);
++	}
++
++	return val;
++}
++
++u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line)
++{
++	u32 val = _rtw_read32(adapter, addr);
++
++	if (match_read_sniff(adapter, addr, 4, val)) {
++		RTW_INFO("DBG_IO %s:%d rtw_read32(0x%04x) return 0x%08x\n"
++			, caller, line, addr, val);
++	}
++
++	return val;
++}
++
++int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line)
++{
++	if (match_write_sniff(adapter, addr, 1, val)) {
++		RTW_INFO("DBG_IO %s:%d rtw_write8(0x%04x, 0x%02x)\n"
++			, caller, line, addr, val);
++	}
++
++	return _rtw_write8(adapter, addr, val);
++}
++int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line)
++{
++	if (match_write_sniff(adapter, addr, 2, val)) {
++		RTW_INFO("DBG_IO %s:%d rtw_write16(0x%04x, 0x%04x)\n"
++			, caller, line, addr, val);
++	}
++
++	return _rtw_write16(adapter, addr, val);
++}
++int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line)
++{
++	if (match_write_sniff(adapter, addr, 4, val)) {
++		RTW_INFO("DBG_IO %s:%d rtw_write32(0x%04x, 0x%08x)\n"
++			, caller, line, addr, val);
++	}
++
++	return _rtw_write32(adapter, addr, val);
++}
++int dbg_rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *data, const char *caller, const int line)
++{
++	if (match_write_sniff(adapter, addr, length, 0)) {
++		RTW_INFO("DBG_IO %s:%d rtw_writeN(0x%04x, %u)\n"
++			, caller, line, addr, length);
++	}
++
++	return _rtw_writeN(adapter, addr, length, data);
++}
++
++#ifdef CONFIG_SDIO_HCI
++u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line)
++{
++	u8 val = _rtw_sd_f0_read8(adapter, addr);
++
++#if 0
++	if (match_read_sniff(adapter, addr, 1, val)) {
++		RTW_INFO("DBG_IO %s:%d rtw_sd_f0_read8(0x%04x) return 0x%02x\n"
++			, caller, line, addr, val);
++	}
++#endif
++
++	return val;
++}
++
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++u8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line)
++{
++	u8 val = rtw_sd_iread8(adapter, addr);
++
++	if (match_read_sniff(adapter, addr, 1, val)) {
++		RTW_INFO("DBG_IO %s:%d rtw_sd_iread8(0x%04x) return 0x%02x\n"
++			, caller, line, addr, val);
++	}
++
++	return val;
++}
++
++u16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line)
++{
++	u16 val = _rtw_sd_iread16(adapter, addr);
++
++	if (match_read_sniff(adapter, addr, 2, val)) {
++		RTW_INFO("DBG_IO %s:%d rtw_sd_iread16(0x%04x) return 0x%04x\n"
++			, caller, line, addr, val);
++	}
++
++	return val;
++}
++
++u32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line)
++{
++	u32 val = _rtw_sd_iread32(adapter, addr);
++
++	if (match_read_sniff(adapter, addr, 4, val)) {
++		RTW_INFO("DBG_IO %s:%d rtw_sd_iread32(0x%04x) return 0x%08x\n"
++			, caller, line, addr, val);
++	}
++
++	return val;
++}
++
++int dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line)
++{
++	if (match_write_sniff(adapter, addr, 1, val)) {
++		RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite8(0x%04x, 0x%02x)\n"
++			, caller, line, addr, val);
++	}
++
++	return _rtw_sd_iwrite8(adapter, addr, val);
++}
++int dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line)
++{
++	if (match_write_sniff(adapter, addr, 2, val)) {
++		RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite16(0x%04x, 0x%04x)\n"
++			, caller, line, addr, val);
++	}
++
++	return _rtw_sd_iwrite16(adapter, addr, val);
++}
++int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line)
++{
++	if (match_write_sniff(adapter, addr, 4, val)) {
++		RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite32(0x%04x, 0x%08x)\n"
++			, caller, line, addr, val);
++	}
++
++	return _rtw_sd_iwrite32(adapter, addr, val);
++}
++
++#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
++
++#endif /* CONFIG_SDIO_HCI */
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_ioctl_query.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_ioctl_query.c
+new file mode 100644
+index 000000000..939213843
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_ioctl_query.c
+@@ -0,0 +1,19 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_IOCTL_QUERY_C_
++
++#include <drv_types.h>
++
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_ioctl_set.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_ioctl_set.c
+new file mode 100644
+index 000000000..f06321bb3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_ioctl_set.c
+@@ -0,0 +1,923 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_IOCTL_SET_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++
++extern void indicate_wx_scan_complete_event(_adapter *padapter);
++
++#define IS_MAC_ADDRESS_BROADCAST(addr) \
++	(\
++	 ((addr[0] == 0xff) && (addr[1] == 0xff) && \
++	  (addr[2] == 0xff) && (addr[3] == 0xff) && \
++	  (addr[4] == 0xff) && (addr[5] == 0xff)) ? _TRUE : _FALSE \
++	)
++
++u8 rtw_validate_bssid(u8 *bssid)
++{
++	u8 ret = _TRUE;
++
++	if (is_zero_mac_addr(bssid)
++	    || is_broadcast_mac_addr(bssid)
++	    || is_multicast_mac_addr(bssid)
++	   )
++		ret = _FALSE;
++
++	return ret;
++}
++
++u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid)
++{
++#ifdef CONFIG_VALIDATE_SSID
++	u8	 i;
++#endif
++	u8	ret = _TRUE;
++
++
++	if (ssid->SsidLength > 32) {
++		ret = _FALSE;
++		goto exit;
++	}
++
++#ifdef CONFIG_VALIDATE_SSID
++	for (i = 0; i < ssid->SsidLength; i++) {
++		/* wifi, printable ascii code must be supported */
++		if (!((ssid->Ssid[i] >= 0x20) && (ssid->Ssid[i] <= 0x7e))) {
++			ret = _FALSE;
++			break;
++		}
++	}
++#endif /* CONFIG_VALIDATE_SSID */
++
++exit:
++
++
++	return ret;
++}
++
++u8 rtw_do_join(_adapter *padapter);
++u8 rtw_do_join(_adapter *padapter)
++{
++	_irqL	irqL;
++	_list	*plist, *phead;
++	u8 *pibss = NULL;
++	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	struct sitesurvey_parm parm;
++	_queue	*queue	= &(pmlmepriv->scanned_queue);
++	u8 ret = _SUCCESS;
++
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++
++
++	pmlmepriv->cur_network.join_res = -2;
++
++	set_fwstate(pmlmepriv, WIFI_UNDER_LINKING);
++
++	pmlmepriv->pscanned = plist;
++
++	pmlmepriv->to_join = _TRUE;
++
++	rtw_init_sitesurvey_parm(padapter, &parm);
++	_rtw_memcpy(&parm.ssid[0], &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
++	parm.ssid_num = 1;
++
++	if (pmlmepriv->assoc_ch) {
++		parm.ch_num = 1;
++		parm.ch[0].hw_value = pmlmepriv->assoc_ch;
++		parm.ch[0].flags = 0;
++	}
++
++	if (_rtw_queue_empty(queue) == _TRUE) {
++		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++		_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
++
++		/* when set_ssid/set_bssid for rtw_do_join(), but scanning queue is empty */
++		/* we try to issue sitesurvey firstly	 */
++
++		if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE
++		    || rtw_to_roam(padapter) > 0
++		   ) {
++			u8 ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
++
++			if ((ssc_chk == SS_ALLOW) || (ssc_chk == SS_DENY_BUSY_TRAFFIC) ){
++				/* submit site_survey_cmd */
++				ret = rtw_sitesurvey_cmd(padapter, &parm);
++				if (_SUCCESS != ret)
++					pmlmepriv->to_join = _FALSE;
++			} else {
++				/*if (ssc_chk == SS_DENY_BUDDY_UNDER_SURVEY)*/
++				pmlmepriv->to_join = _FALSE;
++				ret = _FAIL;
++			}
++		} else {
++			pmlmepriv->to_join = _FALSE;
++			ret = _FAIL;
++		}
++
++		goto exit;
++	} else {
++		int select_ret;
++		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++		select_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv);
++		if (select_ret == _SUCCESS) {
++			pmlmepriv->to_join = _FALSE;
++			_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
++		} else {
++			if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {
++				/* submit createbss_cmd to change to a ADHOC_MASTER */
++
++				/* pmlmepriv->lock has been acquired by caller... */
++				WLAN_BSSID_EX    *pdev_network = &(padapter->registrypriv.dev_network);
++
++				/*pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;*/
++				init_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
++
++				pibss = padapter->registrypriv.dev_network.MacAddress;
++
++				_rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID));
++				_rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
++
++				rtw_update_registrypriv_dev_network(padapter);
++
++				rtw_generate_random_ibss(pibss);
++
++				if (rtw_create_ibss_cmd(padapter, 0) != _SUCCESS) {
++					ret =  _FALSE;
++					goto exit;
++				}
++
++				pmlmepriv->to_join = _FALSE;
++
++
++			} else {
++				/* can't associate ; reset under-linking			 */
++				_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
++
++				/* when set_ssid/set_bssid for rtw_do_join(), but there are no desired bss in scanning queue */
++				/* we try to issue sitesurvey firstly			 */
++				if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE
++				    || rtw_to_roam(padapter) > 0
++				   ) {
++					u8 ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
++
++					if ((ssc_chk == SS_ALLOW) || (ssc_chk == SS_DENY_BUSY_TRAFFIC)){
++						/* RTW_INFO(("rtw_do_join() when   no desired bss in scanning queue\n"); */
++						ret = rtw_sitesurvey_cmd(padapter, &parm);
++						if (_SUCCESS != ret)
++							pmlmepriv->to_join = _FALSE;
++					} else {
++						/*if (ssc_chk == SS_DENY_BUDDY_UNDER_SURVEY) {
++						} else {*/
++						ret = _FAIL;
++						pmlmepriv->to_join = _FALSE;
++					}
++				} else {
++					ret = _FAIL;
++					pmlmepriv->to_join = _FALSE;
++				}
++			}
++
++		}
++
++	}
++
++exit:
++
++	return ret;
++}
++
++u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid)
++{
++	_irqL irqL;
++	u8 status = _SUCCESS;
++
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++
++	RTW_PRINT("set bssid:%pM\n", bssid);
++
++	if ((bssid[0] == 0x00 && bssid[1] == 0x00 && bssid[2] == 0x00 && bssid[3] == 0x00 && bssid[4] == 0x00 && bssid[5] == 0x00) ||
++	    (bssid[0] == 0xFF && bssid[1] == 0xFF && bssid[2] == 0xFF && bssid[3] == 0xFF && bssid[4] == 0xFF && bssid[5] == 0xFF)) {
++		status = _FAIL;
++		goto exit;
++	}
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++
++	RTW_INFO("Set BSSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv));
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE)
++		goto handle_tkip_countermeasure;
++	else if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE)
++		goto release_mlme_lock;
++
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE) {
++
++		if (_rtw_memcmp(&pmlmepriv->cur_network.network.MacAddress, bssid, ETH_ALEN) == _TRUE) {
++			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE)
++				goto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */
++		} else {
++
++			rtw_disassoc_cmd(padapter, 0, 0);
++
++			if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++				rtw_indicate_disconnect(padapter, 0, _FALSE);
++
++			rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
++
++			if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
++				_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
++				set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
++			}
++		}
++	}
++
++handle_tkip_countermeasure:
++	if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {
++		status = _FAIL;
++		goto release_mlme_lock;
++	}
++
++	_rtw_memset(&pmlmepriv->assoc_ssid, 0, sizeof(NDIS_802_11_SSID));
++	_rtw_memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN);
++	pmlmepriv->assoc_ch = 0;
++	pmlmepriv->assoc_by_bssid = _TRUE;
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE)
++		pmlmepriv->to_join = _TRUE;
++	else
++		status = rtw_do_join(padapter);
++
++release_mlme_lock:
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++exit:
++
++
++	return status;
++}
++
++u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid)
++{
++	_irqL irqL;
++	u8 status = _SUCCESS;
++
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct wlan_network *pnetwork = &pmlmepriv->cur_network;
++
++
++	RTW_PRINT("set ssid [%s] fw_state=0x%08x\n",
++		  ssid->Ssid, get_fwstate(pmlmepriv));
++
++	if (!rtw_is_hw_init_completed(padapter)) {
++		status = _FAIL;
++		goto exit;
++	}
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++	RTW_INFO("Set SSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv));
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE)
++		goto handle_tkip_countermeasure;
++	else if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE)
++		goto release_mlme_lock;
++
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE) {
++
++		if ((pmlmepriv->assoc_ssid.SsidLength == ssid->SsidLength) &&
++		    (_rtw_memcmp(&pmlmepriv->assoc_ssid.Ssid, ssid->Ssid, ssid->SsidLength) == _TRUE)) {
++			if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE)) {
++
++				if (rtw_is_same_ibss(padapter, pnetwork) == _FALSE) {
++					/* if in WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE, create bss or rejoin again */
++					rtw_disassoc_cmd(padapter, 0, 0);
++
++					if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++						rtw_indicate_disconnect(padapter, 0, _FALSE);
++
++					rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
++
++					if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) {
++						_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
++						set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
++					}
++				} else {
++					goto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */
++				}
++			}
++#ifdef CONFIG_LPS
++			else
++				rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_JOINBSS, 0);
++#endif
++		} else {
++
++			rtw_disassoc_cmd(padapter, 0, 0);
++
++			if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++				rtw_indicate_disconnect(padapter, 0, _FALSE);
++
++			rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
++
++			if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) {
++				_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
++				set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
++			}
++		}
++	}
++
++handle_tkip_countermeasure:
++	if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {
++		status = _FAIL;
++		goto release_mlme_lock;
++	}
++
++	if (rtw_validate_ssid(ssid) == _FALSE) {
++		status = _FAIL;
++		goto release_mlme_lock;
++	}
++
++	_rtw_memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(NDIS_802_11_SSID));
++	pmlmepriv->assoc_ch = 0;
++	pmlmepriv->assoc_by_bssid = _FALSE;
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE)
++		pmlmepriv->to_join = _TRUE;
++	else
++		status = rtw_do_join(padapter);
++
++release_mlme_lock:
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++exit:
++
++
++	return status;
++
++}
++
++u8 rtw_set_802_11_connect(_adapter *padapter,
++			  u8 *bssid, NDIS_802_11_SSID *ssid, u16 ch)
++{
++	_irqL irqL;
++	u8 status = _SUCCESS;
++	bool bssid_valid = _TRUE;
++	bool ssid_valid = _TRUE;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++
++	if (!ssid || rtw_validate_ssid(ssid) == _FALSE)
++		ssid_valid = _FALSE;
++
++	if (!bssid || rtw_validate_bssid(bssid) == _FALSE)
++		bssid_valid = _FALSE;
++
++	if (ssid_valid == _FALSE && bssid_valid == _FALSE) {
++		RTW_INFO(FUNC_ADPT_FMT" ssid:%p, ssid_valid:%d, bssid:%p, bssid_valid:%d\n",
++			FUNC_ADPT_ARG(padapter), ssid, ssid_valid, bssid, bssid_valid);
++		status = _FAIL;
++		goto exit;
++	}
++
++	if (!rtw_is_hw_init_completed(padapter)) {
++		status = _FAIL;
++		goto exit;
++	}
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++	RTW_PRINT(FUNC_ADPT_FMT"  fw_state=0x%08x\n",
++		  FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv));
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE)
++		goto handle_tkip_countermeasure;
++	else if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE)
++		goto release_mlme_lock;
++
++handle_tkip_countermeasure:
++	if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {
++		status = _FAIL;
++		goto release_mlme_lock;
++	}
++
++	if (ssid && ssid_valid)
++		_rtw_memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(NDIS_802_11_SSID));
++	else
++		_rtw_memset(&pmlmepriv->assoc_ssid, 0, sizeof(NDIS_802_11_SSID));
++
++	if (bssid && bssid_valid) {
++		_rtw_memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN);
++		pmlmepriv->assoc_by_bssid = _TRUE;
++	} else
++		pmlmepriv->assoc_by_bssid = _FALSE;
++
++	pmlmepriv->assoc_ch = ch;
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE)
++		pmlmepriv->to_join = _TRUE;
++	else
++		status = rtw_do_join(padapter);
++
++release_mlme_lock:
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++exit:
++	return status;
++}
++
++u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter,
++			      NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags)
++{
++	_irqL irqL;
++	struct	mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct	wlan_network	*cur_network = &pmlmepriv->cur_network;
++	NDIS_802_11_NETWORK_INFRASTRUCTURE *pold_state = &(cur_network->network.InfrastructureMode);
++	u8 ap2sta_mode = _FALSE;
++	u8 ret = _TRUE;
++	u8 is_linked = _FALSE, is_adhoc_master = _FALSE;
++
++	if (*pold_state != networktype) {
++		/* RTW_INFO("change mode, old_mode=%d, new_mode=%d, fw_state=0x%x\n", *pold_state, networktype, get_fwstate(pmlmepriv)); */
++
++		if (*pold_state == Ndis802_11APMode
++			|| *pold_state == Ndis802_11_mesh
++		) {
++			/* change to other mode from Ndis802_11APMode/Ndis802_11_mesh */
++			cur_network->join_res = -1;
++			ap2sta_mode = _TRUE;
++#ifdef CONFIG_NATIVEAP_MLME
++			stop_ap_mode(padapter);
++#endif
++		}
++
++		_enter_critical_bh(&pmlmepriv->lock, &irqL);
++		is_linked = check_fwstate(pmlmepriv, WIFI_ASOC_STATE);
++		is_adhoc_master = check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
++
++		/* flags = 0, means enqueue cmd and no wait */
++		if (flags != 0)
++			_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++		if ((is_linked == _TRUE) || (*pold_state == Ndis802_11IBSS))
++			rtw_disassoc_cmd(padapter, 0, flags);
++
++		if ((is_linked == _TRUE) ||
++		    (is_adhoc_master == _TRUE))
++			rtw_free_assoc_resources_cmd(padapter, _TRUE, flags);
++
++		if ((*pold_state == Ndis802_11Infrastructure) || (*pold_state == Ndis802_11IBSS)) {
++			if (is_linked == _TRUE) {
++				rtw_indicate_disconnect(padapter, 0, _FALSE); /*will clr Linked_state; before this function, we must have checked whether issue dis-assoc_cmd or not*/
++			}
++		}
++
++		/* flags = 0, means enqueue cmd and no wait */
++		if (flags != 0)
++			_enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++		*pold_state = networktype;
++
++		_clr_fwstate_(pmlmepriv, ~WIFI_NULL_STATE);
++
++		switch (networktype) {
++		case Ndis802_11IBSS:
++			set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
++			break;
++
++		case Ndis802_11Infrastructure:
++			set_fwstate(pmlmepriv, WIFI_STATION_STATE);
++
++			if (ap2sta_mode)
++				rtw_init_bcmc_stainfo(padapter);
++			break;
++
++		case Ndis802_11APMode:
++			set_fwstate(pmlmepriv, WIFI_AP_STATE);
++#ifdef CONFIG_NATIVEAP_MLME
++			start_ap_mode(padapter);
++			/* rtw_indicate_connect(padapter); */
++#endif
++
++			break;
++
++#ifdef CONFIG_RTW_MESH
++		case Ndis802_11_mesh:
++			set_fwstate(pmlmepriv, WIFI_MESH_STATE);
++			start_ap_mode(padapter);
++			break;
++#endif
++
++		case Ndis802_11AutoUnknown:
++		case Ndis802_11InfrastructureMax:
++			break;
++#ifdef CONFIG_WIFI_MONITOR
++		case Ndis802_11Monitor:
++			set_fwstate(pmlmepriv, WIFI_MONITOR_STATE);
++			break;
++#endif /* CONFIG_WIFI_MONITOR */
++		default:
++			ret = _FALSE;
++			rtw_warn_on(1);
++		}
++
++		/* SecClearAllKeys(adapter); */
++
++
++		_exit_critical_bh(&pmlmepriv->lock, &irqL);
++	}
++
++	return ret;
++}
++
++
++u8 rtw_set_802_11_disassociate(_adapter *padapter)
++{
++	_irqL irqL;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++
++		rtw_disassoc_cmd(padapter, 0, 0);
++		rtw_indicate_disconnect(padapter, 0, _FALSE);
++		/* modify for CONFIG_IEEE80211W, none 11w can use it */
++		rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
++		if (_FAIL == rtw_pwr_wakeup(padapter))
++			RTW_INFO("%s(): rtw_pwr_wakeup fail !!!\n", __FUNCTION__);
++	}
++
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++
++	return _TRUE;
++}
++
++#if 1
++u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm)
++{
++	_irqL	irqL;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	u8	res = _TRUE;
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++	res = rtw_sitesurvey_cmd(padapter, pparm);
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++	return res;
++}
++
++#else
++u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm)
++{
++	_irqL	irqL;
++	struct	mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	u8	res = _TRUE;
++
++
++
++	if (padapter == NULL) {
++		res = _FALSE;
++		goto exit;
++	}
++	if (!rtw_is_hw_init_completed(padapter)) {
++		res = _FALSE;
++		goto exit;
++	}
++
++	if ((check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING) == _TRUE) ||
++	    (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)) {
++		/* Scan or linking is in progress, do nothing. */
++		res = _TRUE;
++
++
++	} else {
++		if (rtw_is_scan_deny(padapter)) {
++			RTW_INFO(FUNC_ADPT_FMT": scan deny\n", FUNC_ADPT_ARG(padapter));
++			indicate_wx_scan_complete_event(padapter);
++			return _SUCCESS;
++		}
++
++		_enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++		res = rtw_sitesurvey_cmd(padapter, pparm);
++
++		_exit_critical_bh(&pmlmepriv->lock, &irqL);
++	}
++exit:
++
++
++	return res;
++}
++#endif
++
++#ifdef CONFIG_RTW_ACS
++u8 rtw_set_acs_sitesurvey(_adapter *adapter)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	struct sitesurvey_parm parm;
++	u8 uch;
++	u8 ch_num = 0;
++	int i;
++	BAND_TYPE band;
++	u8 (*center_chs_num)(u8) = NULL;
++	u8 (*center_chs)(u8, u8) = NULL;
++	u8 ret = _FAIL;
++
++	if (!rtw_mi_get_ch_setting_union(adapter, &uch, NULL, NULL))
++		goto exit;
++
++	_rtw_memset(&parm, 0, sizeof(struct sitesurvey_parm));
++	parm.scan_mode = SCAN_PASSIVE;
++	parm.bw = CHANNEL_WIDTH_20;
++	parm.acs = 1;
++
++	for (band = BAND_ON_2_4G; band < BAND_MAX; band++) {
++		if (band == BAND_ON_2_4G) {
++			center_chs_num = center_chs_2g_num;
++			center_chs = center_chs_2g;
++		} else
++		#ifdef CONFIG_IEEE80211_BAND_5GHZ
++		if (band == BAND_ON_5G) {
++			center_chs_num = center_chs_5g_num;
++			center_chs = center_chs_5g;
++		} else
++		#endif
++		{
++			center_chs_num = NULL;
++			center_chs = NULL;
++		}
++
++		if (!center_chs_num || !center_chs)
++			continue;
++
++		if (rfctl->ch_sel_within_same_band) {
++			if (rtw_is_2g_ch(uch) && band != BAND_ON_2_4G)
++				continue;
++			#ifdef CONFIG_IEEE80211_BAND_5GHZ
++			if (rtw_is_5g_ch(uch) && band != BAND_ON_5G)
++				continue;
++			#endif
++		}
++
++		ch_num = center_chs_num(CHANNEL_WIDTH_20);	
++		for (i = 0; i < ch_num && parm.ch_num < RTW_CHANNEL_SCAN_AMOUNT; i++) {
++			parm.ch[parm.ch_num].hw_value = center_chs(CHANNEL_WIDTH_20, i);
++			parm.ch[parm.ch_num].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN;
++			parm.ch_num++;
++		}
++	}
++
++	ret = rtw_set_802_11_bssid_list_scan(adapter, &parm);
++
++exit:
++	return ret;
++}
++#endif /* CONFIG_RTW_ACS */
++
++u8 rtw_set_802_11_authentication_mode(_adapter *padapter, NDIS_802_11_AUTHENTICATION_MODE authmode)
++{
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	int res;
++	u8 ret;
++
++
++
++	psecuritypriv->ndisauthtype = authmode;
++
++
++	if (psecuritypriv->ndisauthtype > 3)
++		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
++
++#ifdef CONFIG_WAPI_SUPPORT
++	if (psecuritypriv->ndisauthtype == 6)
++		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;
++#endif
++
++	res = rtw_set_auth(padapter, psecuritypriv);
++
++	if (res == _SUCCESS)
++		ret = _TRUE;
++	else
++		ret = _FALSE;
++
++
++	return ret;
++}
++
++u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep)
++{
++
++	u8		bdefaultkey;
++	u8		btransmitkey;
++	sint		keyid, res;
++	struct security_priv *psecuritypriv = &(padapter->securitypriv);
++	u8		ret = _SUCCESS;
++
++
++	bdefaultkey = (wep->KeyIndex & 0x40000000) > 0 ? _FALSE : _TRUE; /* for ??? */
++	btransmitkey = (wep->KeyIndex & 0x80000000) > 0 ? _TRUE  : _FALSE;	/* for ??? */
++	keyid = wep->KeyIndex & 0x3fffffff;
++
++	if (keyid >= 4) {
++		ret = _FALSE;
++		goto exit;
++	}
++
++	switch (wep->KeyLength) {
++	case 5:
++		psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
++		break;
++	case 13:
++		psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
++		break;
++	default:
++		psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
++		break;
++	}
++
++
++	_rtw_memcpy(&(psecuritypriv->dot11DefKey[keyid].skey[0]), &(wep->KeyMaterial), wep->KeyLength);
++
++	psecuritypriv->dot11DefKeylen[keyid] = wep->KeyLength;
++
++	psecuritypriv->dot11PrivacyKeyIndex = keyid;
++
++
++	res = rtw_set_key(padapter, psecuritypriv, keyid, 1, _TRUE);
++
++	if (res == _FAIL)
++		ret = _FALSE;
++exit:
++
++
++	return ret;
++
++}
++
++/*
++* rtw_get_cur_max_rate -
++* @adapter: pointer to _adapter structure
++*
++* Return 0 or 100Kbps
++*/
++u16 rtw_get_cur_max_rate(_adapter *adapter)
++{
++	int j;
++	int	i = 0;
++	u16	rate = 0, max_rate = 0;
++	struct mlme_priv	*pmlmepriv = &adapter->mlmepriv;
++	WLAN_BSSID_EX	*pcur_bss = &pmlmepriv->cur_network.network;
++	int	sta_bssrate_len = 0;
++	unsigned char	sta_bssrate[NumRates];
++	struct sta_info *psta = NULL;
++	u8	short_GI = 0;
++
++#ifdef CONFIG_MP_INCLUDED
++	if (adapter->registrypriv.mp_mode == 1) {
++		if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
++			return 0;
++	}
++#endif
++
++	if ((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) != _TRUE)
++	    && (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE))
++		return 0;
++
++	psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
++	if (psta == NULL)
++		return 0;
++
++	short_GI = query_ra_short_GI(psta, rtw_get_tx_bw_mode(adapter, psta));
++
++#ifdef CONFIG_80211N_HT
++	if (is_supported_ht(psta->wireless_mode)) {
++		max_rate = rtw_ht_mcs_rate((psta->cmn.bw_mode == CHANNEL_WIDTH_40) ? 1 : 0
++			, short_GI
++			, psta->htpriv.ht_cap.supp_mcs_set
++		);
++	}
++#ifdef CONFIG_80211AC_VHT
++	else if (is_supported_vht(psta->wireless_mode))
++		max_rate = ((rtw_vht_mcs_to_data_rate(psta->cmn.bw_mode, short_GI, pmlmepriv->vhtpriv.vht_highest_rate) + 1) >> 1) * 10;
++#endif /* CONFIG_80211AC_VHT */
++	else
++#endif /* CONFIG_80211N_HT */
++	{
++		/*station mode show :station && ap support rate; softap :show ap support rate*/	
++		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
++			get_rate_set(adapter, sta_bssrate, &sta_bssrate_len);/*get sta rate and length*/
++
++
++		while ((pcur_bss->SupportedRates[i] != 0) && (pcur_bss->SupportedRates[i] != 0xFF)) {
++			rate = pcur_bss->SupportedRates[i] & 0x7F;/*AP support rates*/
++			/*RTW_INFO("%s rate=%02X \n", __func__, rate);*/
++
++			/*check STA  support rate or not */
++			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
++				for (j = 0; j < sta_bssrate_len; j++) {
++					/* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */
++					if ((rate | IEEE80211_BASIC_RATE_MASK)
++					    == (sta_bssrate[j] | IEEE80211_BASIC_RATE_MASK)) {
++						if (rate > max_rate) {
++							max_rate = rate;
++						}
++						break;
++					}
++				}
++			} else {
++			
++				if (rate > max_rate)
++					max_rate = rate;
++
++			}
++			i++;
++		}
++
++		max_rate = max_rate * 10 / 2;
++	}
++	return max_rate;
++}
++
++/*
++* rtw_set_scan_mode -
++* @adapter: pointer to _adapter structure
++* @scan_mode:
++*
++* Return _SUCCESS or _FAIL
++*/
++int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode)
++{
++	if (scan_mode != SCAN_ACTIVE && scan_mode != SCAN_PASSIVE)
++		return _FAIL;
++
++	adapter->mlmepriv.scan_mode = scan_mode;
++
++	return _SUCCESS;
++}
++
++/*
++* rtw_set_channel_plan -
++* @adapter: pointer to _adapter structure
++* @channel_plan:
++*
++* Return _SUCCESS or _FAIL
++*/
++int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan)
++{
++	/* handle by cmd_thread to sync with scan operation */
++	return rtw_set_chplan_cmd(adapter, RTW_CMDF_WAIT_ACK, channel_plan, 1);
++}
++
++/*
++* rtw_set_country -
++* @adapter: pointer to _adapter structure
++* @country_code: string of country code
++*
++* Return _SUCCESS or _FAIL
++*/
++int rtw_set_country(_adapter *adapter, const char *country_code)
++{
++#ifdef CONFIG_RTW_IOCTL_SET_COUNTRY
++	return rtw_set_country_cmd(adapter, RTW_CMDF_WAIT_ACK, country_code, 1);
++#else
++	RTW_INFO("%s(): not applied\n", __func__);
++	return _SUCCESS;
++#endif
++}
++
++/*
++* rtw_set_band -
++* @adapter: pointer to _adapter structure
++* @band: band to set
++*
++* Return _SUCCESS or _FAIL
++*/
++int rtw_set_band(_adapter *adapter, u8 band)
++{
++	if (rtw_band_valid(band)) {
++		RTW_INFO(FUNC_ADPT_FMT" band:%d\n", FUNC_ADPT_ARG(adapter), band);
++		adapter->setband = band;
++		return _SUCCESS;
++	}
++
++	RTW_PRINT(FUNC_ADPT_FMT" band:%d fail\n", FUNC_ADPT_ARG(adapter), band);
++	return _FAIL;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_iol.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_iol.c
+new file mode 100644
+index 000000000..714a3f44e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_iol.c
+@@ -0,0 +1,388 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <drv_types.h>
++
++#ifdef CONFIG_IOL
++struct xmit_frame	*rtw_IOL_accquire_xmit_frame(ADAPTER *adapter)
++{
++	struct xmit_frame	*xmit_frame;
++	struct xmit_buf	*xmitbuf;
++	struct pkt_attrib	*pattrib;
++	struct xmit_priv	*pxmitpriv = &(adapter->xmitpriv);
++
++#if 1
++	xmit_frame = rtw_alloc_xmitframe(pxmitpriv, 0);
++	if (xmit_frame == NULL) {
++		RTW_INFO("%s rtw_alloc_xmitframe return null\n", __FUNCTION__);
++		goto exit;
++	}
++
++	xmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
++	if (xmitbuf == NULL) {
++		RTW_INFO("%s rtw_alloc_xmitbuf return null\n", __FUNCTION__);
++		rtw_free_xmitframe(pxmitpriv, xmit_frame);
++		xmit_frame = NULL;
++		goto exit;
++	}
++
++	xmit_frame->frame_tag = MGNT_FRAMETAG;
++	xmit_frame->pxmitbuf = xmitbuf;
++	xmit_frame->buf_addr = xmitbuf->pbuf;
++	xmitbuf->priv_data = xmit_frame;
++
++	pattrib = &xmit_frame->attrib;
++	update_mgntframe_attrib(adapter, pattrib);
++	pattrib->qsel = QSLT_BEACON;/* Beacon	 */
++	pattrib->subtype = WIFI_BEACON;
++	pattrib->pktlen = pattrib->last_txcmdsz = 0;
++
++#else
++	xmit_frame = alloc_mgtxmitframe(pxmitpriv);
++	if (xmit_frame == NULL)
++		RTW_INFO("%s alloc_mgtxmitframe return null\n", __FUNCTION__);
++	else {
++		pattrib = &xmit_frame->attrib;
++		update_mgntframe_attrib(adapter, pattrib);
++		pattrib->qsel = QSLT_BEACON;
++		pattrib->pktlen = pattrib->last_txcmdsz = 0;
++	}
++#endif
++
++exit:
++	return xmit_frame;
++}
++
++
++int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len)
++{
++	struct pkt_attrib	*pattrib = &xmit_frame->attrib;
++	u16 buf_offset;
++	u32 ori_len;
++
++	buf_offset = TXDESC_OFFSET;
++	ori_len = buf_offset + pattrib->pktlen;
++
++	/* check if the io_buf can accommodate new cmds */
++	if (ori_len + cmd_len + 8 > MAX_XMITBUF_SZ) {
++		RTW_INFO("%s %u is large than MAX_XMITBUF_SZ:%u, can't accommodate new cmds\n", __FUNCTION__
++			 , ori_len + cmd_len + 8, MAX_XMITBUF_SZ);
++		return _FAIL;
++	}
++
++	_rtw_memcpy(xmit_frame->buf_addr + buf_offset + pattrib->pktlen, IOL_cmds, cmd_len);
++	pattrib->pktlen += cmd_len;
++	pattrib->last_txcmdsz += cmd_len;
++
++	/* RTW_INFO("%s ori:%u + cmd_len:%u = %u\n", __FUNCTION__, ori_len, cmd_len, buf_offset+pattrib->pktlen); */
++
++	return _SUCCESS;
++}
++
++bool rtw_IOL_applied(ADAPTER *adapter)
++{
++	if (1 == adapter->registrypriv.fw_iol)
++		return _TRUE;
++
++#ifdef CONFIG_USB_HCI
++	if ((2 == adapter->registrypriv.fw_iol) && (IS_FULL_SPEED_USB(adapter)))
++		return _TRUE;
++#endif
++
++	return _FALSE;
++}
++
++int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)
++{
++	return rtw_hal_iol_cmd(adapter, xmit_frame, max_wating_ms, bndy_cnt);
++}
++
++#ifdef CONFIG_IOL_NEW_GENERATION
++int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary)
++{
++	return _SUCCESS;
++}
++int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask)
++{
++	struct ioreg_cfg cmd = {8, IOREG_CMD_WB_REG, 0x0, 0x0, 0x0};
++
++	/* RTW_PUT_LE16((u8*)&cmd.address, addr);	 */
++	/* RTW_PUT_LE32((u8*)&cmd.value, (u32)value);	 */
++	cmd.address = cpu_to_le16(addr);
++	cmd.data = cpu_to_le32(value);
++
++	if (mask != 0xFF) {
++		cmd.length = 12;
++		/* RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);	 */
++		cmd.mask = cpu_to_le32(mask);
++	}
++
++	/* RTW_INFO("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FUNCTION__, addr,value,mask); */
++
++	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
++
++}
++int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask)
++{
++	struct ioreg_cfg cmd = {8, IOREG_CMD_WW_REG, 0x0, 0x0, 0x0};
++
++	/* RTW_PUT_LE16((u8*)&cmd.address, addr);	 */
++	/* RTW_PUT_LE32((u8*)&cmd.value, (u32)value);	 */
++	cmd.address = cpu_to_le16(addr);
++	cmd.data = cpu_to_le32(value);
++
++	if (mask != 0xFFFF) {
++		cmd.length = 12;
++		/* RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);	 */
++		cmd.mask =  cpu_to_le32(mask);
++	}
++
++	/* RTW_INFO("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FUNCTION__, addr,value,mask); */
++
++	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
++
++}
++int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask)
++{
++	struct ioreg_cfg cmd = {8, IOREG_CMD_WD_REG, 0x0, 0x0, 0x0};
++
++	/* RTW_PUT_LE16((u8*)&cmd.address, addr);	 */
++	/* RTW_PUT_LE32((u8*)&cmd.value, (u32)value);	 */
++	cmd.address = cpu_to_le16(addr);
++	cmd.data = cpu_to_le32(value);
++
++	if (mask != 0xFFFFFFFF) {
++		cmd.length = 12;
++		/* RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);	 */
++		cmd.mask =  cpu_to_le32(mask);
++	}
++
++	/* RTW_INFO("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FU2NCTION__, addr,value,mask); */
++
++	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
++
++}
++
++int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask)
++{
++	struct ioreg_cfg cmd = {8, IOREG_CMD_W_RF, 0x0, 0x0, 0x0};
++
++	/* RTW_PUT_LE16((u8*)&cmd.address, addr);	 */
++	/* RTW_PUT_LE32((u8*)&cmd.value, (u32)value);	 */
++	cmd.address = (rf_path << 8) | ((addr) & 0xFF);
++	cmd.data = cpu_to_le32(value);
++
++	if (mask != 0x000FFFFF) {
++		cmd.length = 12;
++		/* RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);	 */
++		cmd.mask =  cpu_to_le32(mask);
++	}
++
++	/* RTW_INFO("%s rf_path:0x%02x addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FU2NCTION__,rf_path, addr,value,mask); */
++
++	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
++
++}
++
++
++
++int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)
++{
++	struct ioreg_cfg cmd = {4, IOREG_CMD_DELAY_US, 0x0, 0x0, 0x0};
++	/* RTW_PUT_LE16((u8*)&cmd.address, us);	 */
++	cmd.address = cpu_to_le16(us);
++
++	/* RTW_INFO("%s %u\n", __FUNCTION__, us); */
++	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);
++}
++
++int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)
++{
++	struct ioreg_cfg cmd = {4, IOREG_CMD_DELAY_US, 0x0, 0x0, 0x0};
++
++	/* RTW_PUT_LE16((u8*)&cmd.address, ms);	 */
++	cmd.address = cpu_to_le16(ms);
++
++	/* RTW_INFO("%s %u\n", __FUNCTION__, ms); */
++	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);
++}
++int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame)
++{
++	struct ioreg_cfg cmd = {4, IOREG_CMD_END, 0xFFFF, 0xFF, 0x0};
++	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);
++
++}
++
++u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame)
++{
++	u8 is_cmd_bndy = _FALSE;
++	if (((pxmit_frame->attrib.pktlen + 32) % 256) + 8 >= 256) {
++		rtw_IOL_append_END_cmd(pxmit_frame);
++		pxmit_frame->attrib.pktlen = ((((pxmit_frame->attrib.pktlen + 32) / 256) + 1) * 256);
++
++		/* printk("==> %s, pktlen(%d)\n",__FUNCTION__,pxmit_frame->attrib.pktlen); */
++		pxmit_frame->attrib.last_txcmdsz = pxmit_frame->attrib.pktlen;
++		is_cmd_bndy = _TRUE;
++	}
++	return is_cmd_bndy;
++}
++
++void rtw_IOL_cmd_buf_dump(ADAPTER *Adapter, int buf_len, u8 *pbuf)
++{
++	int i;
++	int j = 1;
++
++	printk("###### %s ######\n", __FUNCTION__);
++	for (i = 0; i < buf_len; i++) {
++		printk("%02x-", *(pbuf + i));
++
++		if (j % 32 == 0)
++			printk("\n");
++		j++;
++	}
++	printk("\n");
++	printk("============= ioreg_cmd len = %d ===============\n", buf_len);
++}
++
++
++#else /* CONFIG_IOL_NEW_GENERATION */
++int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary)
++{
++	IOL_CMD cmd = {0x0, IOL_CMD_LLT, 0x0, 0x0};
++
++	RTW_PUT_BE32((u8 *)&cmd.value, (u32)page_boundary);
++
++	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
++}
++
++int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value)
++{
++	IOL_CMD cmd = {0x0, IOL_CMD_WB_REG, 0x0, 0x0};
++
++	RTW_PUT_BE16((u8 *)&cmd.address, (u16)addr);
++	RTW_PUT_BE32((u8 *)&cmd.value, (u32)value);
++
++	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
++}
++
++int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value)
++{
++	IOL_CMD cmd = {0x0, IOL_CMD_WW_REG, 0x0, 0x0};
++
++	RTW_PUT_BE16((u8 *)&cmd.address, (u16)addr);
++	RTW_PUT_BE32((u8 *)&cmd.value, (u32)value);
++
++	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
++}
++
++int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value)
++{
++	IOL_CMD cmd = {0x0, IOL_CMD_WD_REG, 0x0, 0x0};
++	u8 *pos = (u8 *)&cmd;
++
++	RTW_PUT_BE16((u8 *)&cmd.address, (u16)addr);
++	RTW_PUT_BE32((u8 *)&cmd.value, (u32)value);
++
++	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
++}
++
++#ifdef DBG_IO
++int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line)
++{
++	if (match_write_sniff(xmit_frame->padapter, addr, 1, value)) {
++		RTW_INFO("DBG_IO %s:%d IOL_WB(0x%04x, 0x%02x)\n"
++			, caller, line, addr, value);
++	}
++
++	return _rtw_IOL_append_WB_cmd(xmit_frame, addr, value);
++}
++
++int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line)
++{
++	if (match_write_sniff(xmit_frame->padapter, addr, 2, value)) {
++		RTW_INFO("DBG_IO %s:%d IOL_WW(0x%04x, 0x%04x)\n"
++			, caller, line, addr, value);
++	}
++
++	return _rtw_IOL_append_WW_cmd(xmit_frame, addr, value);
++}
++
++int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line)
++{
++	if (match_write_sniff(xmit_frame->padapter, addr, 4, value)) {
++		RTW_INFO("DBG_IO %s:%d IOL_WD(0x%04x, 0x%08x)\n"
++			, caller, line, addr, value);
++	}
++
++	return _rtw_IOL_append_WD_cmd(xmit_frame, addr, value);
++}
++#endif
++
++int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)
++{
++	IOL_CMD cmd = {0x0, IOL_CMD_DELAY_US, 0x0, 0x0};
++
++	RTW_PUT_BE32((u8 *)&cmd.value, (u32)us);
++
++	/* RTW_INFO("%s %u\n", __FUNCTION__, us); */
++
++	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
++}
++
++int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)
++{
++	IOL_CMD cmd = {0x0, IOL_CMD_DELAY_MS, 0x0, 0x0};
++
++	RTW_PUT_BE32((u8 *)&cmd.value, (u32)ms);
++
++	/* RTW_INFO("%s %u\n", __FUNCTION__, ms); */
++
++	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
++}
++
++int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame)
++{
++	IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0};
++
++
++	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&end_cmd, 8);
++
++}
++
++int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms)
++{
++	struct xmit_frame	*xmit_frame;
++
++	xmit_frame = rtw_IOL_accquire_xmit_frame(adapter);
++	if (xmit_frame == NULL)
++		return _FAIL;
++
++	if (rtw_IOL_append_cmds(xmit_frame, IOL_cmds, cmd_num << 3) == _FAIL)
++		return _FAIL;
++
++	return rtw_IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms, 0);
++}
++
++int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms)
++{
++	IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0};
++	return rtw_IOL_exec_cmd_array_sync(adapter, (u8 *)&end_cmd, 1, max_wating_ms);
++}
++#endif /* CONFIG_IOL_NEW_GENERATION */
++
++
++
++
++#endif /* CONFIG_IOL */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mbo.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mbo.c
+new file mode 100755
+index 000000000..44f93ad6c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mbo.c
+@@ -0,0 +1,803 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++#ifdef CONFIG_RTW_MBO
++
++#ifndef RTW_MBO_DBG
++#define RTW_MBO_DBG	0
++#endif
++#if RTW_MBO_DBG
++	#define RTW_MBO_INFO(fmt, arg...)	\
++		RTW_INFO(fmt, arg)
++	#define RTW_MBO_DUMP(str, data, len)	\
++		RTW_INFO_DUMP(str, data, len)	
++#else
++	#define RTW_MBO_INFO(fmt, arg...) do {} while (0)
++	#define RTW_MBO_DUMP(str, data, len) do {} while (0)
++#endif
++
++/* Cellular Data Connectivity field
++ * 1 : Cellular data connection available
++ * 2 : Cellular data connection not available
++ * 3 : Not Cellular data capable
++ * otherwise : Reserved
++*/
++int rtw_mbo_cell_data_conn = 2;
++module_param(rtw_mbo_cell_data_conn, int, 0644);
++
++static u8 wfa_mbo_oui[] = {0x50, 0x6F, 0x9A, 0x16};
++
++#define rtw_mbo_get_oui(p) ((u8 *)(p) + 2) 
++
++#define rtw_mbo_get_attr_id(p) ((u8 *)(p)) 
++
++#define rtw_mbo_get_disallow_res(p) ((u8 *)(p) + 3) 
++
++#define rtw_mbo_set_1byte_ie(p, v, l)	\
++	rtw_set_fixed_ie((p), 1, (v), (l))
++
++#define rtw_mbo_set_4byte_ie(p, v, l)	\
++	rtw_set_fixed_ie((p), 4, (v), (l))
++
++#define rtw_mbo_set_nbyte_ie(p, sz, v, l)	\
++	rtw_set_fixed_ie((p), (sz), (v), (l))
++
++#define rtw_mbo_subfield_set(p, offset, val) (*(p + offset) = val)
++
++#define rtw_mbo_subfields_set(p, offset, buf, len)	\
++	do {	\
++		u32 _offset = 0;	\
++		u8 *_p = p + offset;	\
++		while(_offset < len) {	\
++			*(_p + _offset) = *(buf + _offset);	\
++			_offset++;	\
++		}	\
++	} while(0)
++	
++static u8 *rtw_mbo_ie_get(u8 *pie, u32 *plen, u32 limit)
++{
++	const u8 *p = pie;
++	u32 tmp, i;
++	
++	if (limit <= 1)
++		return NULL;
++
++	i = 0;
++	*plen = 0;
++	while (1) {
++		if ((*p == _VENDOR_SPECIFIC_IE_) && 
++			(_rtw_memcmp(rtw_mbo_get_oui(p), wfa_mbo_oui, 4))) {
++			*plen = *(p + 1);
++			RTW_MBO_DUMP("VENDOR_SPECIFIC_IE MBO: ", p, *(p + 1));
++			return (u8 *)p;
++		} else {
++			tmp = *(p + 1);
++			p += (tmp + 2);
++			i += (tmp + 2);
++		}
++		
++		if (i >= limit)
++			break;
++	}
++	
++	return NULL;	
++}
++
++static u8 *rtw_mbo_attrs_get(u8 *pie, u32 limit, u8 attr_id, u32 *attr_len)
++{
++	u8 *p = NULL;
++	u32 offset, plen = 0;
++
++	if ((pie == NULL) || (limit <= 1))
++		goto exit;
++	
++	if ((p = rtw_mbo_ie_get(pie, &plen, limit)) == NULL)
++		goto exit;
++
++	/* shift 2 + OUI size and move to attributes content */
++	p = p + 2 + sizeof(wfa_mbo_oui);
++	plen = plen - 4;
++	RTW_MBO_DUMP("Attributes contents: ", p, plen);
++
++	if ((p = rtw_get_ie(p, attr_id, attr_len, plen)) == NULL)
++		goto exit;
++
++	RTW_MBO_INFO("%s : id=%u(len=%u)\n", __func__, attr_id, *attr_len);
++	RTW_MBO_DUMP("contents : ", p, *attr_len);
++
++exit:
++	return p;	
++
++}
++
++static u32 rtw_mbo_attr_sz_get(
++	_adapter *padapter, u8 id)
++{
++	u32 len = 0;
++
++	switch (id) {
++		case RTW_MBO_ATTR_NPREF_CH_RPT_ID:
++			{
++				struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
++				struct npref_ch_rtp *prpt = &(prfctl->ch_rtp);
++				struct npref_ch* pch;
++				u32 i, attr_len, offset;
++
++				for (i=0; i < prpt->nm_of_rpt; i++) {
++					pch = &prpt->ch_rpt[i];
++					/*attr_len = ch list + op class + preference + reason */
++					attr_len = pch->nm_of_ch + 3;
++					/* offset = id + len field + attr_len */
++					offset = attr_len + 2;
++					len += offset;
++				}							
++			}
++			break;
++		case RTW_MBO_ATTR_CELL_DATA_CAP_ID:
++		case RTW_MBO_ATTR_TRANS_REJ_ID:
++			len = 3;
++			break;
++		default:
++			break;
++	}
++
++	return len;
++}
++
++static void rtw_mbo_build_mbo_ie_hdr(
++	u8 **pframe, struct pkt_attrib *pattrib, u8 payload_len)
++{
++	u8 eid = RTW_MBO_EID;
++	u8 len = payload_len + 4; 
++
++	*pframe = rtw_mbo_set_1byte_ie(*pframe, &eid, &(pattrib->pktlen));
++	*pframe = rtw_mbo_set_1byte_ie(*pframe, &len, &(pattrib->pktlen));
++	*pframe = rtw_mbo_set_4byte_ie(*pframe, wfa_mbo_oui, &(pattrib->pktlen));
++}
++
++void rtw_mbo_build_cell_data_cap_attr(
++	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	u8 attr_id = RTW_MBO_ATTR_CELL_DATA_CAP_ID;
++	u8 attr_len = 1;
++	u8 cell_data_con = rtw_mbo_cell_data_conn;
++
++	/* used Cellular Data Capabilities from supplicant */
++	if (!rtw_mbo_wifi_logo_test(padapter) &&
++		pmlmepriv->pcell_data_cap_ie && pmlmepriv->cell_data_cap_len == 1) {
++		cell_data_con = *pmlmepriv->pcell_data_cap_ie;
++		RTW_MBO_INFO("%s : used Cellular Data Capabilities(%u) from supplicant!\n",
++			__func__, *pmlmepriv->pcell_data_cap_ie);
++	}
++		
++	*pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_id, &(pattrib->pktlen));
++	*pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_len, &(pattrib->pktlen));	
++	*pframe = rtw_mbo_set_1byte_ie(*pframe, &cell_data_con, &(pattrib->pktlen));
++}
++
++static void rtw_mbo_update_cell_data_cap(
++	_adapter *padapter, u8 *pie, u32 ie_len)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	u8 *mbo_attr;	
++	u32	mbo_attrlen;
++
++	if ((pie == NULL) || (ie_len == 0))
++		return;
++
++	mbo_attr = rtw_mbo_attrs_get(pie, ie_len, 
++		RTW_MBO_ATTR_CELL_DATA_CAP_ID, &mbo_attrlen);
++
++	if ((mbo_attr == NULL) || (mbo_attrlen == 0) ) {
++		RTW_INFO("MBO : Cellular Data Capabilities not found!\n");
++		return;
++	}
++
++	rtw_buf_update(&pmlmepriv->pcell_data_cap_ie, 
++		&pmlmepriv->cell_data_cap_len, (mbo_attr + 2), mbo_attrlen);
++	RTW_MBO_DUMP("rtw_mbo_update_cell_data_cap : ", 
++		pmlmepriv->pcell_data_cap_ie, pmlmepriv->cell_data_cap_len);
++}
++
++void rtw_mbo_update_ie_data(
++	_adapter *padapter, u8 *pie, u32 ie_len)
++{
++	rtw_mbo_update_cell_data_cap(padapter, pie, ie_len);
++}
++
++static u8 rtw_mbo_current_op_class_get(_adapter *padapter)
++{
++	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
++	struct p2p_channels *pch_list =  &(prfctl->channel_list);	
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++	struct p2p_reg_class *preg_class;
++	int class_idx, ch_idx;
++	u8 cur_op_class = 0;
++
++	for(class_idx =0; class_idx < pch_list->reg_classes; class_idx++) {
++		preg_class =  &pch_list->reg_class[class_idx];
++		for (ch_idx = 0; ch_idx <= preg_class->channels; ch_idx++) {
++			if (pmlmeext->cur_channel ==  preg_class->channel[ch_idx]) {
++				cur_op_class = preg_class->reg_class;
++				RTW_MBO_INFO("%s : current ch : %d, op class : %d\n",
++					__func__, pmlmeext->cur_channel, cur_op_class);		
++				break;
++			}
++		}
++	}
++	
++	return cur_op_class;
++}
++
++static void rtw_mbo_supp_op_classes_get(_adapter *padapter, u8 *pclasses)
++{
++	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
++	struct p2p_channels *pch_list =  &(prfctl->channel_list);	
++	int class_idx;
++
++	if (pclasses == NULL)
++		return;
++
++	RTW_MBO_INFO("%s : support op class \n", __func__);
++	for(class_idx = 0; class_idx < pch_list->reg_classes; class_idx++) {
++		*(pclasses + class_idx) = pch_list->reg_class[class_idx].reg_class;
++		RTW_MBO_INFO("%u ,", *(pclasses + class_idx));		
++	}
++
++	RTW_MBO_INFO("%s : \n", __func__);	
++}
++
++void rtw_mbo_build_supp_op_class_elem(
++	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib)
++{
++	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
++	u8 payload[32] = {0};
++	u8 delimiter_130 = 130;	/*0x82*/
++	u8 reg_class_nm, len;
++
++	if ((reg_class_nm = prfctl->channel_list.reg_classes) == 0)
++		return;
++
++	payload[0] = rtw_mbo_current_op_class_get(padapter);
++	rtw_mbo_supp_op_classes_get(padapter, &payload[1]);
++
++	/* IEEE 802.11 Std Current Operating Class Extension Sequence */
++	payload[reg_class_nm + 1] = delimiter_130;
++	payload[reg_class_nm + 2] = 0x00;
++
++	RTW_MBO_DUMP("op class :", payload, reg_class_nm);
++
++	/* Current Operating Class field + Operating Class field 
++		+ OneHundredAndThirty Delimiter field */
++	len = reg_class_nm + 3;	
++	*pframe = rtw_set_ie(*pframe, EID_SupRegulatory, len , 
++					payload, &(pattrib->pktlen));	
++}
++
++static u8 rtw_mbo_construct_npref_ch_rpt_attr(
++	_adapter *padapter, u8 *pbuf, u32 buf_len, u32 *plen)
++{
++	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
++	struct npref_ch_rtp *prpt = &(prfctl->ch_rtp);
++	struct npref_ch* pch;
++	u32 attr_len, offset;
++	int i;
++	u8 *p = pbuf;
++
++	if (prpt->nm_of_rpt == 0) {
++		*plen = 0;
++		return _FALSE;
++	}	
++
++	for (i=0; i < prpt->nm_of_rpt; i++) {
++		pch = &prpt->ch_rpt[i];
++		/* attr_len = ch list + op class + preference + reason */
++		attr_len = pch->nm_of_ch + 3;
++		/* offset = id + len field + attr_len */
++		offset = attr_len + 2;
++		rtw_mbo_subfield_set(p, 0, RTW_MBO_ATTR_NPREF_CH_RPT_ID);
++		rtw_mbo_subfield_set(p, 1, attr_len);
++		rtw_mbo_subfield_set(p, 2, pch->op_class);
++		rtw_mbo_subfields_set(p, 3, pch->chs, pch->nm_of_ch);
++		rtw_mbo_subfield_set(p, (offset - 2), pch->preference);
++		rtw_mbo_subfield_set(p, (offset - 1), pch->reason);
++		p +=  offset;
++		*plen += offset;
++
++		if (*plen >=  buf_len) {
++			RTW_ERR("MBO : construct non-preferred channel report fail!\n");
++			return _FALSE;
++		}
++	}
++
++	return _TRUE;
++}
++
++void rtw_mbo_build_npref_ch_rpt_attr(
++	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib)
++{
++	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
++	struct npref_ch_rtp *prpt = &(prfctl->ch_rtp);
++	u32 tmp_sz = 0, body_len = 0;
++	u8 *ptmp;
++
++	tmp_sz = prpt->nm_of_rpt * sizeof(struct npref_ch);
++	ptmp = rtw_zmalloc(tmp_sz);
++	if (ptmp == NULL)
++		return;
++
++	if (rtw_mbo_construct_npref_ch_rpt_attr(padapter, ptmp, tmp_sz, &body_len) == _FALSE) {
++		rtw_mfree(ptmp, tmp_sz);
++		return;
++	}	
++
++	RTW_MBO_DUMP("Non-preferred Channel Report :", ptmp, body_len);
++	*pframe = rtw_mbo_set_nbyte_ie(*pframe, body_len, ptmp, &(pattrib->pktlen));
++
++	rtw_mfree(ptmp, tmp_sz);
++}
++
++void rtw_mbo_build_trans_reject_reason_attr(
++	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib, u8 *pres)
++{
++	u8 attr_id = RTW_MBO_ATTR_TRANS_REJ_ID;
++	u8 attr_len = 1;
++	u32 len = 0;
++
++	len = rtw_mbo_attr_sz_get(padapter, RTW_MBO_ATTR_TRANS_REJ_ID);
++	if ((len == 0) || (len > 3)) {
++		RTW_ERR("MBO : build Transition Rejection Reason  attribute fail(len=%u)\n", len);
++		return;
++	}
++			
++	rtw_mbo_build_mbo_ie_hdr(pframe, pattrib, len);
++	*pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_id, &(pattrib->pktlen));
++	*pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_len, &(pattrib->pktlen));	
++	*pframe = rtw_mbo_set_1byte_ie(*pframe, pres, &(pattrib->pktlen));
++}
++
++u8 rtw_mbo_disallowed_network(struct wlan_network *pnetwork)
++{
++	u8 *p, *attr_id, *res;
++	u32 attr_len = 0;
++	u8 disallow = _FALSE;
++
++	if (pnetwork == NULL)
++		goto exit;
++
++	p = rtw_mbo_attrs_get(pnetwork->network.IEs, 
++		pnetwork->network.IELength, 
++		RTW_MBO_ATTR_ASSOC_DISABLED_ID, 
++		&attr_len);
++
++	if (p == NULL) {
++		RTW_MBO_INFO("%s :Assoc Disallowed attribute not found!\n",__func__);
++		goto exit;
++	}
++		
++	RTW_MBO_DUMP("Association Disallowed attribute :",p , attr_len + 2);
++	RTW_INFO("MBO : block "MAC_FMT" assoc disallowed reason %d\n",
++		MAC_ARG(pnetwork->network.MacAddress), *(rtw_mbo_get_disallow_res(p)));
++
++	disallow = _TRUE;
++exit:
++	return disallow;
++}
++
++void rtw_mbo_build_exented_cap(
++	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib)
++{
++	u8 content[8] = { 0 };
++
++	rtw_wnm_set_ext_cap_btm(content, 1);
++	rtw_mbo_set_ext_cap_internw(content, 1);
++	*pframe = rtw_set_ie(*pframe, 
++				EID_EXTCapability, 
++				8, 
++				content, 
++				&(pattrib->pktlen));
++}
++
++static void rtw_mbo_non_pref_chans_dump(struct npref_ch* pch)
++{
++	int i;
++	u8 buf[128] = {0};
++
++	for (i=0; i < pch->nm_of_ch; i++)
++		rtw_sprintf(buf, 128, "%s,%d", buf, pch->chs[i]);
++
++	RTW_MBO_INFO("%s : op_class=%01x, ch=%s, preference=%d, reason=%d\n", 
++		__func__, pch->op_class, buf, pch->preference, pch->reason);		
++}
++
++static u8 rtw_mbo_non_pref_chan_exist(struct npref_ch* pch, u8 ch)
++{
++	u32 i;
++	u8 found = _FALSE;
++
++	for (i=0; i < pch->nm_of_ch; i++) {
++		if (pch->chs[i] == ch) {
++			found = _TRUE;
++			break;
++		}
++	}
++	
++	return found;
++}
++
++static struct npref_ch* rtw_mbo_non_pref_chan_get(
++	_adapter *padapter, u8 op_class, u8  prefe, u8  res)
++{
++	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
++	struct npref_ch_rtp *prpt = &(prfctl->ch_rtp);
++	struct npref_ch* pch = NULL;
++	int i;
++
++	if (prpt->nm_of_rpt == 0)
++		return pch;
++
++	for (i=0; i < prpt->nm_of_rpt; i++) {
++		if ((prpt->ch_rpt[i].op_class == op_class) &&
++			(prpt->ch_rpt[i].preference == prefe) && 
++			(prpt->ch_rpt[i].reason == res)) {
++			pch = &prpt->ch_rpt[i];
++			break;
++		}
++	}
++
++	return pch;
++}
++
++static void rtw_mbo_non_pref_chan_set(
++	struct npref_ch* pch, u8 op_class, u8 ch, u8  prefe, u8  res, u8 update)
++{
++	u32 offset = pch->nm_of_ch;
++
++	if (update) {
++		if (rtw_mbo_non_pref_chan_exist(pch, ch) == _FALSE) {
++			pch->chs[offset] = ch;
++			pch->nm_of_ch++;
++		}
++	} else {
++		pch->op_class = op_class;
++		pch->chs[0] = ch;
++		pch->preference = prefe;
++		pch->reason = res;
++		pch->nm_of_ch = 1;
++	}
++}
++
++static void  rtw_mbo_non_pref_chans_update(
++	_adapter *padapter, u8 op_class, u8 ch, u8  prefe, u8  res)
++{
++	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
++	struct npref_ch_rtp *pch_rpt = &(prfctl->ch_rtp);
++	struct npref_ch* pch;
++
++	if (pch_rpt->nm_of_rpt >= RTW_MBO_MAX_CH_RPT_NUM) {
++		RTW_ERR("MBO : %d non_pref_chan entries supported!", 
++			RTW_MBO_MAX_CH_RPT_NUM);
++		return;
++	}
++
++	if (pch_rpt->nm_of_rpt == 0) {
++		pch = &pch_rpt->ch_rpt[0];
++		rtw_mbo_non_pref_chan_set(pch, op_class, ch, prefe, res, _FALSE);
++		pch_rpt->nm_of_rpt = 1;
++		return;
++	}
++
++	pch = rtw_mbo_non_pref_chan_get(padapter, op_class, prefe, res);
++	if (pch == NULL) {
++		pch = &pch_rpt->ch_rpt[pch_rpt->nm_of_rpt];
++		rtw_mbo_non_pref_chan_set(pch, op_class, ch, prefe, res, _FALSE);
++		pch_rpt->nm_of_rpt++;
++	} else
++		rtw_mbo_non_pref_chan_set(pch, op_class, ch, prefe, res, _TRUE);
++
++	rtw_mbo_non_pref_chans_dump(pch);
++}
++
++static void  rtw_mbo_non_pref_chans_set(
++	_adapter *padapter, char *param, ssize_t sz)
++{
++	char *pnext;
++	u32 op_class, ch, prefe, res;
++	int i = 0;
++	
++	do {
++		pnext = strsep(&param, " ");
++		if (pnext == NULL)
++			break;
++
++		sscanf(pnext, "%d:%d:%d:%d", &op_class, &ch, &prefe, &res);
++		rtw_mbo_non_pref_chans_update(padapter, op_class, ch, prefe, res);
++	
++		if ((i++) > 10) {
++			RTW_ERR("MBO : overflow %d \n", i);
++			break;
++		}
++		
++	} while(param != '\0');
++	
++}
++
++static void  rtw_mbo_non_pref_chans_del(
++	_adapter *padapter, char *param, ssize_t sz)
++{
++	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
++	struct npref_ch_rtp *prpt = &(prfctl->ch_rtp);
++	
++	RTW_INFO("%s : delete non_pref_chan %s\n", __func__, param);
++	_rtw_memset(prpt, 0, sizeof(struct npref_ch_rtp));
++}
++
++ssize_t rtw_mbo_proc_non_pref_chans_set(
++	struct file *pfile, const char __user *buffer, 
++	size_t count, loff_t *pos, void *pdata)
++{
++	struct net_device *dev = pdata;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	u8 tmp[128] = {0};
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		if (strncmp(tmp, "add", 3) == 0)
++			rtw_mbo_non_pref_chans_set(padapter, &tmp[4], (count - 4));
++		else if (strncmp(tmp, "delete", 6) == 0)
++			rtw_mbo_non_pref_chans_del(padapter, &tmp[7], (count - 7));
++		else {
++			RTW_ERR("MBO : Invalid format : echo [add|delete] <oper_class>:<chan>:<preference>:<reason>\n");
++			return -EFAULT;
++		}
++	}	
++
++#ifdef CONFIG_RTW_WNM
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) &&
++		check_fwstate(pmlmepriv, WIFI_STATION_STATE)) 
++		rtw_wnm_issue_action(padapter, RTW_WLAN_ACTION_WNM_NOTIF_REQ, 0, 0);
++#endif
++	
++	return count;
++}
++
++int rtw_mbo_proc_non_pref_chans_get(
++	struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
++	struct npref_ch_rtp *prpt = &(prfctl->ch_rtp);
++	struct npref_ch* pch;
++	int i,j;
++	u8 buf[32] = {0};
++
++	RTW_PRINT_SEL(m, "op_class                     ch    preference    reason \n");
++	RTW_PRINT_SEL(m, "=======================================================\n");
++
++		
++	if (prpt->nm_of_rpt == 0) {
++		RTW_PRINT_SEL(m, " empty table \n");
++		return 0;
++	}
++
++	for (i=0; i < prpt->nm_of_rpt; i++) {
++		pch = &prpt->ch_rpt[i];	
++		buf[0]='\0';
++		for (j=0; j < pch->nm_of_ch; j++) {
++			if (j == 0)
++				rtw_sprintf(buf, 32, "%02u", pch->chs[j]);
++			else				
++				rtw_sprintf(buf, 32, "%s,%02u", buf, pch->chs[j]);
++		}
++
++		RTW_PRINT_SEL(m, "    %04u    %20s           %02u        %02u\n",
++			pch->op_class, buf, pch->preference, pch->reason);		
++	}
++	
++	return 0;
++}
++
++ssize_t rtw_mbo_proc_cell_data_set(
++	struct file *pfile, const char __user *buffer,
++	size_t count, loff_t *pos, void *pdata)
++{
++	struct net_device *dev = pdata;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	int mbo_cell_data = 0;
++	u8 tmp[8] = {0};
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp))
++		return -EFAULT;
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%d", &mbo_cell_data);
++		if (num == 1) {
++			rtw_mbo_cell_data_conn = mbo_cell_data;
++		#ifdef CONFIG_RTW_WNM
++			if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) &&
++				check_fwstate(pmlmepriv, WIFI_STATION_STATE)) 
++				rtw_wnm_issue_action(padapter, RTW_WLAN_ACTION_WNM_NOTIF_REQ, 0, 0);
++		#endif
++		}
++	}
++
++
++	return count;
++}
++
++int rtw_mbo_proc_cell_data_get(
++	struct seq_file *m, void *v)
++{
++#if 0
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++#endif
++
++	RTW_PRINT_SEL(m, "Cellular Data Connectivity : %d\n", rtw_mbo_cell_data_conn);
++	return 0;
++}
++
++static void rtw_mbo_non_pref_chan_subelem_parsing(
++	_adapter *padapter, u8 *subelem, size_t subelem_len)
++{
++	u8 *pnon_pref_chans;
++	u32 non_pref_chan_offset, op_subelem_len; 
++	u32 oui_offset = 3;
++	/* wpa_supplicant don't apped OUI Type */
++	u32 oui_type_offset = 0;
++
++	RTW_MBO_DUMP("Non-preferred Channel subelem : ", subelem , subelem_len);
++
++	/* Subelem : 
++		Vendor Specific | Length | WFA OUI | OUI Type | MBO Attributes */
++	non_pref_chan_offset = 2 + oui_offset + oui_type_offset;
++	pnon_pref_chans = subelem + non_pref_chan_offset;
++	op_subelem_len = subelem_len - non_pref_chan_offset;
++
++	/* wpa_supplicant don't indicate non_pref_chan length,
++		so we cannot get how many non_pref_chan in a wnm notification */
++	RTW_MBO_DUMP("Non-preferred Channel : ", pnon_pref_chans, op_subelem_len);
++}
++
++void rtw_mbo_wnm_notification_parsing(
++	_adapter *padapter, const u8 *pdata, size_t data_len)
++{
++	u8 *paction;
++	u8 category, action, dialog, type;
++	u32 len;
++
++	if ((pdata == NULL) || (data_len == 0))
++		return;
++
++	RTW_MBO_DUMP("WNM notification data : ", pdata, data_len);	
++	paction = (u8 *)pdata + sizeof(struct rtw_ieee80211_hdr_3addr);
++	category = paction[0];
++	action = paction[1];
++	dialog = paction[2];
++	type = paction[3];
++
++	if ((action == RTW_WLAN_ACTION_WNM_NOTIF_REQ) && 
++		(type == WLAN_EID_VENDOR_SPECIFIC)) {
++		rtw_mbo_non_pref_chan_subelem_parsing(padapter, &paction[4], 
++			(data_len - sizeof(struct rtw_ieee80211_hdr_3addr)));
++	}
++	
++}
++
++void rtw_mbo_build_wnm_notification(
++	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib)
++{
++	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
++	struct npref_ch_rtp *prpt = &(prfctl->ch_rtp);
++	struct npref_ch* pch;
++	u8 subelem_id = WLAN_EID_VENDOR_SPECIFIC;
++	u8 non_pref_ch_oui[] = {0x50, 0x6F, 0x9A, 0x2};
++	u8 cell_data_cap_oui[] = {0x50, 0x6F, 0x9A, 0x3};
++	u8 cell_data_con = rtw_mbo_cell_data_conn;
++	u8 len, cell_data_con_len = 0, *pcont = *pframe;
++	int i;
++
++	if (rtw_mbo_cell_data_conn > 0) {
++		len = 0x5;
++		*pframe = rtw_mbo_set_1byte_ie(*pframe, &subelem_id, &(pattrib->pktlen));
++		*pframe = rtw_mbo_set_1byte_ie(*pframe, &len, &(pattrib->pktlen));
++		*pframe = rtw_mbo_set_4byte_ie(*pframe, cell_data_cap_oui, &(pattrib->pktlen));	
++		*pframe = rtw_mbo_set_1byte_ie(*pframe, &cell_data_con, &(pattrib->pktlen));
++		RTW_MBO_INFO("%s : Cellular Data Capabilities subelemen\n", __func__);
++		RTW_MBO_DUMP(":", pcont, len + 2);
++		pcont += len + 2 ;
++	}
++
++	if (prpt->nm_of_rpt == 0) {
++		len = 0x4;
++		*pframe = rtw_mbo_set_1byte_ie(*pframe, &subelem_id, &(pattrib->pktlen));
++		*pframe = rtw_mbo_set_1byte_ie(*pframe, &len, &(pattrib->pktlen));
++		*pframe = rtw_mbo_set_4byte_ie(*pframe, non_pref_ch_oui, &(pattrib->pktlen));
++		RTW_MBO_INFO("%s :Non-preferred Channel Report subelement without data\n", __func__);
++		return;	
++	}
++
++	for (i=0; i < prpt->nm_of_rpt; i++) {
++		pch = &prpt->ch_rpt[i];	
++		/* OUI(3B)  + OUT-type(1B) + op-class(1B) + ch list(nB) 
++			+ Preference(1B) + reason(1B) */
++		len = pch->nm_of_ch + 7;
++		*pframe = rtw_mbo_set_1byte_ie(*pframe, &subelem_id, &(pattrib->pktlen));
++		*pframe = rtw_mbo_set_1byte_ie(*pframe, &len, &(pattrib->pktlen));
++		*pframe = rtw_mbo_set_4byte_ie(*pframe, non_pref_ch_oui, &(pattrib->pktlen));	
++		*pframe = rtw_mbo_set_1byte_ie(*pframe, &pch->op_class, &(pattrib->pktlen));
++		*pframe = rtw_mbo_set_nbyte_ie(*pframe, pch->nm_of_ch, pch->chs, &(pattrib->pktlen));
++		*pframe = rtw_mbo_set_1byte_ie(*pframe, &pch->preference, &(pattrib->pktlen));
++		*pframe = rtw_mbo_set_1byte_ie(*pframe, &pch->reason, &(pattrib->pktlen));
++		RTW_MBO_INFO("%s :Non-preferred Channel Report subelement\n", __func__);
++		RTW_MBO_DUMP(":", pcont, len);
++		pcont = *pframe;
++	}
++}
++
++void rtw_mbo_build_probe_req_ies(
++	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib)
++{
++	u32 len =0;
++	
++	rtw_mbo_build_exented_cap(padapter, pframe, pattrib);
++
++	len = rtw_mbo_attr_sz_get(padapter, RTW_MBO_ATTR_CELL_DATA_CAP_ID);
++	if ((len == 0) || (len > 3)) {
++		RTW_ERR("MBO : build Cellular Data Capabilities attribute fail(len=%u)\n", len);
++		return;
++	}
++	
++	rtw_mbo_build_mbo_ie_hdr(pframe, pattrib, len);
++	rtw_mbo_build_cell_data_cap_attr(padapter, pframe, pattrib);
++}
++
++void rtw_mbo_build_assoc_req_ies(
++	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib)
++{
++	u32 len = 0;
++	
++	rtw_mbo_build_supp_op_class_elem(padapter, pframe, pattrib);
++
++	len += rtw_mbo_attr_sz_get(padapter, RTW_MBO_ATTR_CELL_DATA_CAP_ID);
++	len += rtw_mbo_attr_sz_get(padapter, RTW_MBO_ATTR_NPREF_CH_RPT_ID);
++	if ((len == 0)|| (len < 3)) {
++		RTW_ERR("MBO : build assoc MBO IE fail(len=%u)\n", len);
++		return;
++	}
++	
++	rtw_mbo_build_mbo_ie_hdr(pframe, pattrib, len);
++	rtw_mbo_build_cell_data_cap_attr(padapter, pframe, pattrib);
++	rtw_mbo_build_npref_ch_rpt_attr(padapter, pframe, pattrib);
++}
++
++#endif /* CONFIG_RTW_MBO */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mem.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mem.c
+new file mode 100644
+index 000000000..d9f5652f9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mem.c
+@@ -0,0 +1,128 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <drv_types.h>
++#include <rtw_mem.h>
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Realtek Wireless Lan Driver");
++MODULE_AUTHOR("Realtek Semiconductor Corp.");
++MODULE_VERSION("DRIVERVERSION");
++
++struct sk_buff_head rtk_skb_mem_q;
++struct u8 *rtk_buf_mem[NR_RECVBUFF];
++
++struct u8	*rtw_get_buf_premem(int index)
++{
++	printk("%s, rtk_buf_mem index : %d\n", __func__, index);
++	return rtk_buf_mem[index];
++}
++
++u16 rtw_rtkm_get_buff_size(void)
++{
++	return MAX_RTKM_RECVBUF_SZ;
++}
++EXPORT_SYMBOL(rtw_rtkm_get_buff_size);
++
++u8 rtw_rtkm_get_nr_recv_skb(void)
++{
++	return MAX_RTKM_NR_PREALLOC_RECV_SKB;
++}
++EXPORT_SYMBOL(rtw_rtkm_get_nr_recv_skb);
++
++struct sk_buff *rtw_alloc_skb_premem(u16 in_size)
++{
++	struct sk_buff *skb = NULL;
++
++	if (in_size > MAX_RTKM_RECVBUF_SZ) {
++		pr_info("warning %s: driver buffer size(%d) > rtkm buffer size(%d)\n", __func__, in_size, MAX_RTKM_RECVBUF_SZ);
++		WARN_ON(1);
++		return skb;
++	}
++
++	skb = skb_dequeue(&rtk_skb_mem_q);
++
++	printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
++
++	return skb;
++}
++EXPORT_SYMBOL(rtw_alloc_skb_premem);
++
++int rtw_free_skb_premem(struct sk_buff *pskb)
++{
++	if (!pskb)
++		return -1;
++
++	if (skb_queue_len(&rtk_skb_mem_q) >= MAX_RTKM_NR_PREALLOC_RECV_SKB)
++		return -1;
++
++	skb_queue_tail(&rtk_skb_mem_q, pskb);
++
++	printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
++
++	return 0;
++}
++EXPORT_SYMBOL(rtw_free_skb_premem);
++
++static int __init rtw_mem_init(void)
++{
++	int i;
++	SIZE_PTR tmpaddr = 0;
++	SIZE_PTR alignment = 0;
++	struct sk_buff *pskb = NULL;
++
++	printk("%s\n", __func__);
++	pr_info("MAX_RTKM_NR_PREALLOC_RECV_SKB: %d\n", MAX_RTKM_NR_PREALLOC_RECV_SKB);
++	pr_info("MAX_RTKM_RECVBUF_SZ: %d\n", MAX_RTKM_RECVBUF_SZ);
++
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
++	for (i = 0; i < NR_RECVBUFF; i++)
++		rtk_buf_mem[i] = usb_buffer_alloc(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma);
++#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
++
++	skb_queue_head_init(&rtk_skb_mem_q);
++
++	for (i = 0; i < MAX_RTKM_NR_PREALLOC_RECV_SKB; i++) {
++		pskb = __dev_alloc_skb(MAX_RTKM_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
++		if (pskb) {
++			tmpaddr = (SIZE_PTR)pskb->data;
++			alignment = tmpaddr & (RECVBUFF_ALIGN_SZ - 1);
++			skb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignment));
++
++			skb_queue_tail(&rtk_skb_mem_q, pskb);
++		} else
++			printk("%s, alloc skb memory fail!\n", __func__);
++
++		pskb = NULL;
++	}
++
++	printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
++
++	return 0;
++
++}
++
++static void __exit rtw_mem_exit(void)
++{
++	if (skb_queue_len(&rtk_skb_mem_q))
++		printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
++
++	skb_queue_purge(&rtk_skb_mem_q);
++
++	printk("%s\n", __func__);
++}
++
++module_init(rtw_mem_init);
++module_exit(rtw_mem_exit);
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mi.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mi.c
+new file mode 100644
+index 000000000..e803d7fed
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mi.c
+@@ -0,0 +1,1550 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_MI_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++void rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mi_state *iface_state = &dvobj->iface_state;
++
++	iface_state->union_ch = ch;
++	iface_state->union_bw = bw;
++	iface_state->union_offset = offset;
++}
++
++#ifdef DBG_IFACE_STATUS
++#ifdef CONFIG_P2P
++static u8 _rtw_mi_p2p_listen_scan_chk(_adapter *adapter)
++{
++	int i;
++	_adapter *iface;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	u8 p2p_listen_scan_state = _FALSE;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_LISTEN) ||
++			rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_SCAN)) {
++			p2p_listen_scan_state = _TRUE;
++			break;
++		}
++	}
++	return p2p_listen_scan_state;
++}
++#endif
++#endif
++
++u8 rtw_mi_stayin_union_ch_chk(_adapter *adapter)
++{
++	u8 rst = _TRUE;
++	u8 u_ch, u_bw, u_offset;
++	u8 o_ch, o_bw, o_offset;
++
++	u_ch = rtw_mi_get_union_chan(adapter);
++	u_bw = rtw_mi_get_union_bw(adapter);
++	u_offset = rtw_mi_get_union_offset(adapter);
++
++	o_ch = rtw_get_oper_ch(adapter);
++	o_bw = rtw_get_oper_bw(adapter);
++	o_offset = rtw_get_oper_choffset(adapter);
++
++	if ((u_ch != o_ch) || (u_bw != o_bw) || (u_offset != o_offset))
++		rst = _FALSE;
++
++	#ifdef DBG_IFACE_STATUS
++	if (rst == _FALSE) {
++		RTW_ERR("%s Not stay in union channel\n", __func__);
++		if (GET_HAL_DATA(adapter)->bScanInProcess == _TRUE)
++			RTW_ERR("ScanInProcess\n");
++		#ifdef CONFIG_P2P
++		if (_rtw_mi_p2p_listen_scan_chk(adapter))
++			RTW_ERR("P2P in listen or scan state\n");
++		#endif
++		RTW_ERR("union ch, bw, offset: %u,%u,%u\n", u_ch, u_bw, u_offset);
++		RTW_ERR("oper ch, bw, offset: %u,%u,%u\n", o_ch, o_bw, o_offset);
++		RTW_ERR("=========================\n");
++	}
++	#endif
++	return rst;
++}
++
++u8 rtw_mi_stayin_union_band_chk(_adapter *adapter)
++{
++	u8 rst = _TRUE;
++	u8 u_ch, o_ch;
++	u8 u_band, o_band;
++
++	u_ch = rtw_mi_get_union_chan(adapter);
++	o_ch = rtw_get_oper_ch(adapter);
++	u_band = (u_ch > 14) ? BAND_ON_5G : BAND_ON_2_4G;
++	o_band = (o_ch > 14) ? BAND_ON_5G : BAND_ON_2_4G;
++
++	if (u_ch != o_ch)
++		if(u_band != o_band)
++			rst = _FALSE;
++
++	#ifdef DBG_IFACE_STATUS
++	if (rst == _FALSE)
++		RTW_ERR("%s Not stay in union band\n", __func__);
++	#endif
++
++	return rst;
++}
++
++/* Find union about ch, bw, ch_offset of all linked/linking interfaces */
++int rtw_mi_get_ch_setting_union_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, u8 *ch, u8 *bw, u8 *offset)
++{
++	_adapter *iface;
++	struct mlme_ext_priv *mlmeext;
++	int i;
++	u8 ch_ret = 0;
++	u8 bw_ret = CHANNEL_WIDTH_20;
++	u8 offset_ret = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++	int num = 0;
++
++	if (ch)
++		*ch = 0;
++	if (bw)
++		*bw = CHANNEL_WIDTH_20;
++	if (offset)
++		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (!iface || !(ifbmp & BIT(iface->iface_id)))
++			continue;
++
++		mlmeext = &iface->mlmeextpriv;
++
++		if (!check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE | WIFI_UNDER_LINKING))
++			continue;
++
++		if (check_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING))
++			continue;
++
++		if (num == 0) {
++			ch_ret = mlmeext->cur_channel;
++			bw_ret = mlmeext->cur_bwmode;
++			offset_ret = mlmeext->cur_ch_offset;
++			num++;
++			continue;
++		}
++
++		if (ch_ret != mlmeext->cur_channel) {
++			num = 0;
++			break;
++		}
++
++		if (bw_ret < mlmeext->cur_bwmode) {
++			bw_ret = mlmeext->cur_bwmode;
++			offset_ret = mlmeext->cur_ch_offset;
++		} else if (bw_ret == mlmeext->cur_bwmode && offset_ret != mlmeext->cur_ch_offset) {
++			num = 0;
++			break;
++		}
++
++		num++;
++	}
++
++	if (num) {
++		if (ch)
++			*ch = ch_ret;
++		if (bw)
++			*bw = bw_ret;
++		if (offset)
++			*offset = offset_ret;
++	}
++
++	return num;
++}
++
++inline int rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset)
++{
++	return rtw_mi_get_ch_setting_union_by_ifbmp(adapter_to_dvobj(adapter), 0xFF, ch, bw, offset);
++}
++
++inline int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset)
++{
++	return rtw_mi_get_ch_setting_union_by_ifbmp(adapter_to_dvobj(adapter), 0xFF & ~BIT(adapter->iface_id), ch, bw, offset);
++}
++
++/* For now, not return union_ch/bw/offset */
++void rtw_mi_status_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, struct mi_state *mstate)
++{
++	_adapter *iface;
++	int i;
++
++	_rtw_memset(mstate, 0, sizeof(struct mi_state));
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (!iface || !(ifbmp & BIT(iface->iface_id)))
++			continue;
++
++		if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) {
++			MSTATE_STA_NUM(mstate)++;
++			if (check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++				MSTATE_STA_LD_NUM(mstate)++;
++
++				#ifdef CONFIG_TDLS
++				if (iface->tdlsinfo.link_established == _TRUE)
++					MSTATE_TDLS_LD_NUM(mstate)++;
++				#endif
++				#ifdef CONFIG_P2P
++				if (MLME_IS_GC(iface))
++					MSTATE_P2P_GC_NUM(mstate)++;
++				#endif
++			}
++			if (check_fwstate(&iface->mlmepriv, WIFI_UNDER_LINKING) == _TRUE)
++				MSTATE_STA_LG_NUM(mstate)++;
++
++#ifdef CONFIG_AP_MODE
++		} else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE ) {
++			if (check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++				MSTATE_AP_NUM(mstate)++;
++				if (iface->stapriv.asoc_sta_count > 2)
++					MSTATE_AP_LD_NUM(mstate)++;
++				#ifdef CONFIG_P2P
++				if (MLME_IS_GO(iface))
++					MSTATE_P2P_GO_NUM(mstate)++;
++				#endif
++			} else
++				MSTATE_AP_STARTING_NUM(mstate)++;
++#endif
++
++		} else if (check_fwstate(&iface->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE
++			&& check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE
++		) {
++			MSTATE_ADHOC_NUM(mstate)++;
++			if (iface->stapriv.asoc_sta_count > 2)
++				MSTATE_ADHOC_LD_NUM(mstate)++;
++
++#ifdef CONFIG_RTW_MESH
++		} else if (check_fwstate(&iface->mlmepriv, WIFI_MESH_STATE) == _TRUE
++			&& check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE
++		) {
++			MSTATE_MESH_NUM(mstate)++;
++			if (iface->stapriv.asoc_sta_count > 2)
++				MSTATE_MESH_LD_NUM(mstate)++;
++#endif
++
++		}
++
++		if (check_fwstate(&iface->mlmepriv, WIFI_UNDER_WPS) == _TRUE)
++			MSTATE_WPS_NUM(mstate)++;
++
++		if (check_fwstate(&iface->mlmepriv, WIFI_UNDER_SURVEY) == _TRUE) {
++			MSTATE_SCAN_NUM(mstate)++;
++
++			if (mlmeext_scan_state(&iface->mlmeextpriv) != SCAN_DISABLE
++				&& mlmeext_scan_state(&iface->mlmeextpriv) != SCAN_BACK_OP)
++				MSTATE_SCAN_ENTER_NUM(mstate)++;
++		}
++
++#ifdef CONFIG_IOCTL_CFG80211
++		if (rtw_cfg80211_get_is_mgmt_tx(iface))
++			MSTATE_MGMT_TX_NUM(mstate)++;
++		#ifdef CONFIG_P2P
++		if (rtw_cfg80211_get_is_roch(iface) == _TRUE)
++			MSTATE_ROCH_NUM(mstate)++;
++		#endif
++#endif /* CONFIG_IOCTL_CFG80211 */
++#ifdef CONFIG_P2P
++		if (MLME_IS_PD(iface))
++			MSTATE_P2P_DV_NUM(mstate)++;
++#endif
++	}
++}
++
++inline void rtw_mi_status(_adapter *adapter, struct mi_state *mstate)
++{
++	return rtw_mi_status_by_ifbmp(adapter_to_dvobj(adapter), 0xFF, mstate);
++}
++
++inline void rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate)
++{
++	return rtw_mi_status_by_ifbmp(adapter_to_dvobj(adapter), 0xFF & ~BIT(adapter->iface_id), mstate);
++}
++
++inline void rtw_mi_status_no_others(_adapter *adapter, struct mi_state *mstate)
++{
++	return rtw_mi_status_by_ifbmp(adapter_to_dvobj(adapter), BIT(adapter->iface_id), mstate);
++}
++
++/* For now, not handle union_ch/bw/offset */
++inline void rtw_mi_status_merge(struct mi_state *d, struct mi_state *a)
++{
++	d->sta_num += a->sta_num;
++	d->ld_sta_num += a->ld_sta_num;
++	d->lg_sta_num += a->lg_sta_num;
++#ifdef CONFIG_TDLS
++	d->ld_tdls_num += a->ld_tdls_num;
++#endif
++#ifdef CONFIG_AP_MODE
++	d->ap_num += a->ap_num;
++	d->ld_ap_num += a->ld_ap_num;
++#endif
++	d->adhoc_num += a->adhoc_num;
++	d->ld_adhoc_num += a->ld_adhoc_num;
++#ifdef CONFIG_RTW_MESH
++	d->mesh_num += a->mesh_num;
++	d->ld_mesh_num += a->ld_mesh_num;
++#endif
++	d->scan_num += a->scan_num;
++	d->scan_enter_num += a->scan_enter_num;
++	d->uwps_num += a->uwps_num;
++#ifdef CONFIG_IOCTL_CFG80211
++	#ifdef CONFIG_P2P
++	d->roch_num += a->roch_num;
++	#endif
++	d->mgmt_tx_num += a->mgmt_tx_num;
++#endif
++}
++
++void dump_mi_status(void *sel, struct dvobj_priv *dvobj)
++{
++	RTW_PRINT_SEL(sel, "== dvobj-iface_state ==\n");
++	RTW_PRINT_SEL(sel, "sta_num:%d\n", DEV_STA_NUM(dvobj));
++	RTW_PRINT_SEL(sel, "linking_sta_num:%d\n", DEV_STA_LG_NUM(dvobj));
++	RTW_PRINT_SEL(sel, "linked_sta_num:%d\n", DEV_STA_LD_NUM(dvobj));
++#ifdef CONFIG_TDLS
++	RTW_PRINT_SEL(sel, "linked_tdls_num:%d\n", DEV_TDLS_LD_NUM(dvobj));
++#endif
++#ifdef CONFIG_AP_MODE
++	RTW_PRINT_SEL(sel, "ap_num:%d\n", DEV_AP_NUM(dvobj));
++	RTW_PRINT_SEL(sel, "starting_ap_num:%d\n", DEV_AP_STARTING_NUM(dvobj));
++	RTW_PRINT_SEL(sel, "linked_ap_num:%d\n", DEV_AP_LD_NUM(dvobj));
++#endif
++	RTW_PRINT_SEL(sel, "adhoc_num:%d\n", DEV_ADHOC_NUM(dvobj));
++	RTW_PRINT_SEL(sel, "linked_adhoc_num:%d\n", DEV_ADHOC_LD_NUM(dvobj));
++#ifdef CONFIG_RTW_MESH
++	RTW_PRINT_SEL(sel, "mesh_num:%d\n", DEV_MESH_NUM(dvobj));
++	RTW_PRINT_SEL(sel, "linked_mesh_num:%d\n", DEV_MESH_LD_NUM(dvobj));
++#endif
++#ifdef CONFIG_P2P
++	RTW_PRINT_SEL(sel, "p2p_device_num:%d\n", DEV_P2P_DV_NUM(dvobj));
++	RTW_PRINT_SEL(sel, "p2p_gc_num:%d\n", DEV_P2P_GC_NUM(dvobj));
++	RTW_PRINT_SEL(sel, "p2p_go_num:%d\n", DEV_P2P_GO_NUM(dvobj));
++#endif
++	RTW_PRINT_SEL(sel, "scan_num:%d\n", DEV_SCAN_NUM(dvobj));
++	RTW_PRINT_SEL(sel, "under_wps_num:%d\n", DEV_WPS_NUM(dvobj));
++#if defined(CONFIG_IOCTL_CFG80211)
++	#if defined(CONFIG_P2P)
++	RTW_PRINT_SEL(sel, "roch_num:%d\n", DEV_ROCH_NUM(dvobj));
++	#endif
++	RTW_PRINT_SEL(sel, "mgmt_tx_num:%d\n", DEV_MGMT_TX_NUM(dvobj));
++#endif
++	RTW_PRINT_SEL(sel, "union_ch:%d\n", DEV_U_CH(dvobj));
++	RTW_PRINT_SEL(sel, "union_bw:%d\n", DEV_U_BW(dvobj));
++	RTW_PRINT_SEL(sel, "union_offset:%d\n", DEV_U_OFFSET(dvobj));
++	RTW_PRINT_SEL(sel, "================\n\n");
++}
++
++void dump_dvobj_mi_status(void *sel, const char *fun_name, _adapter *adapter)
++{
++	RTW_INFO("\n[ %s ] call %s\n", fun_name, __func__);
++	dump_mi_status(sel, adapter_to_dvobj(adapter));
++}
++
++inline void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state)
++{
++	_adapter *adapter = container_of(pmlmepriv, _adapter, mlmepriv);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mi_state *iface_state = &dvobj->iface_state;
++	struct mi_state tmp_mstate;
++	u8 u_ch, u_offset, u_bw;
++
++	if (state == WIFI_MONITOR_STATE
++		|| state == 0xFFFFFFFF
++	)
++		return;
++
++	if (0)
++		RTW_INFO("%s => will change or clean state to 0x%08x\n", __func__, state);
++
++	rtw_mi_status(adapter, &tmp_mstate);
++	_rtw_memcpy(iface_state, &tmp_mstate, sizeof(struct mi_state));
++
++	if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset))
++		rtw_mi_update_union_chan_inf(adapter , u_ch, u_offset , u_bw);
++	else {
++		if (0) {
++			dump_adapters_status(RTW_DBGDUMP , dvobj);
++			RTW_INFO("%s-[ERROR] cannot get union channel\n", __func__);
++			rtw_warn_on(1);
++		}
++	}
++
++#ifdef DBG_IFACE_STATUS
++	DBG_IFACE_STATUS_DUMP(adapter);
++#endif
++}
++u8 rtw_mi_check_status(_adapter *adapter, u8 type)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mi_state *iface_state = &dvobj->iface_state;
++	u8 ret = _FALSE;
++
++#ifdef DBG_IFACE_STATUS
++	DBG_IFACE_STATUS_DUMP(adapter);
++	RTW_INFO("%s-"ADPT_FMT" check type:%d\n", __func__, ADPT_ARG(adapter), type);
++#endif
++
++	switch (type) {
++	case MI_LINKED:
++		if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_NUM(iface_state) || MSTATE_ADHOC_NUM(iface_state) || MSTATE_MESH_NUM(iface_state)) /*check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE)*/
++			ret = _TRUE;
++		break;
++	case MI_ASSOC:
++		if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_LD_NUM(iface_state) || MSTATE_ADHOC_LD_NUM(iface_state) || MSTATE_MESH_LD_NUM(iface_state))
++			ret = _TRUE;
++		break;
++	case MI_UNDER_WPS:
++		if (MSTATE_WPS_NUM(iface_state))
++			ret = _TRUE;
++		break;
++
++	case MI_AP_MODE:
++		if (MSTATE_AP_NUM(iface_state))
++			ret = _TRUE;
++		break;
++	case MI_AP_ASSOC:
++		if (MSTATE_AP_LD_NUM(iface_state))
++			ret = _TRUE;
++		break;
++
++	case MI_ADHOC:
++		if (MSTATE_ADHOC_NUM(iface_state))
++			ret = _TRUE;
++		break;
++	case MI_ADHOC_ASSOC:
++		if (MSTATE_ADHOC_LD_NUM(iface_state))
++			ret = _TRUE;
++		break;
++
++#ifdef CONFIG_RTW_MESH
++	case MI_MESH:
++		if (MSTATE_MESH_NUM(iface_state))
++			ret = _TRUE;
++		break;
++	case MI_MESH_ASSOC:
++		if (MSTATE_MESH_LD_NUM(iface_state))
++			ret = _TRUE;
++		break;
++#endif
++
++	case MI_STA_NOLINK: /* this is misleading, but not used now */
++		if (MSTATE_STA_NUM(iface_state) && (!(MSTATE_STA_LD_NUM(iface_state) || MSTATE_STA_LG_NUM(iface_state))))
++			ret = _TRUE;
++		break;
++	case MI_STA_LINKED:
++		if (MSTATE_STA_LD_NUM(iface_state))
++			ret = _TRUE;
++		break;
++	case MI_STA_LINKING:
++		if (MSTATE_STA_LG_NUM(iface_state))
++			ret = _TRUE;
++		break;
++
++	default:
++		break;
++	}
++	return ret;
++}
++
++/*
++* return value : 0 is failed or have not interface meet condition
++* return value : !0 is success or interface numbers which meet condition
++* return value of ops_func must be _TRUE or _FALSE
++*/
++static u8 _rtw_mi_process(_adapter *padapter, bool exclude_self,
++		  void *data, u8(*ops_func)(_adapter *padapter, void *data))
++{
++	int i;
++	_adapter *iface;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++	u8 ret = 0;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if ((iface) && rtw_is_adapter_up(iface)) {
++
++			if ((exclude_self) && (iface == padapter))
++				continue;
++
++			if (ops_func)
++				if (_TRUE == ops_func(iface, data))
++					ret++;
++		}
++	}
++	return ret;
++}
++static u8 _rtw_mi_process_without_schk(_adapter *padapter, bool exclude_self,
++		  void *data, u8(*ops_func)(_adapter *padapter, void *data))
++{
++	int i;
++	_adapter *iface;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++	u8 ret = 0;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (iface) {
++			if ((exclude_self) && (iface == padapter))
++				continue;
++
++			if (ops_func)
++				if (ops_func(iface, data) == _TRUE)
++					ret++;
++		}
++	}
++	return ret;
++}
++
++static u8 _rtw_mi_netif_caroff_qstop(_adapter *padapter, void *data)
++{
++	struct net_device *pnetdev = padapter->pnetdev;
++
++	rtw_netif_carrier_off(pnetdev);
++	rtw_netif_stop_queue(pnetdev);
++	return _TRUE;
++}
++u8 rtw_mi_netif_caroff_qstop(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_caroff_qstop);
++}
++u8 rtw_mi_buddy_netif_caroff_qstop(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_caroff_qstop);
++}
++
++static u8 _rtw_mi_netif_caron_qstart(_adapter *padapter, void *data)
++{
++	struct net_device *pnetdev = padapter->pnetdev;
++
++	rtw_netif_carrier_on(pnetdev);
++	rtw_netif_start_queue(pnetdev);
++	return _TRUE;
++}
++u8 rtw_mi_netif_caron_qstart(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_caron_qstart);
++}
++u8 rtw_mi_buddy_netif_caron_qstart(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_caron_qstart);
++}
++
++static u8 _rtw_mi_netif_stop_queue(_adapter *padapter, void *data)
++{
++	struct net_device *pnetdev = padapter->pnetdev;
++
++	rtw_netif_stop_queue(pnetdev);
++	return _TRUE;
++}
++u8 rtw_mi_netif_stop_queue(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_stop_queue);
++}
++u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_stop_queue);
++}
++
++static u8 _rtw_mi_netif_wake_queue(_adapter *padapter, void *data)
++{
++	struct net_device *pnetdev = padapter->pnetdev;
++
++	if (pnetdev)
++		rtw_netif_wake_queue(pnetdev);
++	return _TRUE;
++}
++u8 rtw_mi_netif_wake_queue(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_wake_queue);
++}
++u8 rtw_mi_buddy_netif_wake_queue(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_wake_queue);
++}
++
++static u8 _rtw_mi_netif_carrier_on(_adapter *padapter, void *data)
++{
++	struct net_device *pnetdev = padapter->pnetdev;
++
++	if (pnetdev)
++		rtw_netif_carrier_on(pnetdev);
++	return _TRUE;
++}
++u8 rtw_mi_netif_carrier_on(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_carrier_on);
++}
++u8 rtw_mi_buddy_netif_carrier_on(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_carrier_on);
++}
++
++static u8 _rtw_mi_netif_carrier_off(_adapter *padapter, void *data)
++{
++	struct net_device *pnetdev = padapter->pnetdev;
++
++	if (pnetdev)
++		rtw_netif_carrier_off(pnetdev);
++	return _TRUE;
++}
++u8 rtw_mi_netif_carrier_off(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_carrier_off);
++}
++u8 rtw_mi_buddy_netif_carrier_off(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_carrier_off);
++}
++
++static u8 _rtw_mi_scan_abort(_adapter *adapter, void *data)
++{
++	bool bwait = *(bool *)data;
++
++	if (bwait)
++		rtw_scan_abort(adapter);
++	else
++		rtw_scan_abort_no_wait(adapter);
++
++	return _TRUE;
++}
++void rtw_mi_scan_abort(_adapter *adapter, bool bwait)
++{
++	bool in_data = bwait;
++
++	_rtw_mi_process(adapter, _FALSE, &in_data, _rtw_mi_scan_abort);
++
++}
++void rtw_mi_buddy_scan_abort(_adapter *adapter, bool bwait)
++{
++	bool in_data = bwait;
++
++	_rtw_mi_process(adapter, _TRUE, &in_data, _rtw_mi_scan_abort);
++}
++
++static u32 _rtw_mi_start_drv_threads(_adapter *adapter, bool exclude_self)
++{
++	int i;
++	_adapter *iface = NULL;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	u32 _status = _SUCCESS;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (iface) {
++			if ((exclude_self) && (iface == adapter))
++				continue;
++			if (rtw_start_drv_threads(iface) == _FAIL) {
++				_status = _FAIL;
++				break;
++			}
++		}
++	}
++	return _status;
++}
++u32 rtw_mi_start_drv_threads(_adapter *adapter)
++{
++	return _rtw_mi_start_drv_threads(adapter, _FALSE);
++}
++u32 rtw_mi_buddy_start_drv_threads(_adapter *adapter)
++{
++	return _rtw_mi_start_drv_threads(adapter, _TRUE);
++}
++
++static void _rtw_mi_stop_drv_threads(_adapter *adapter, bool exclude_self)
++{
++	int i;
++	_adapter *iface = NULL;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (iface) {
++			if ((exclude_self) && (iface == adapter))
++				continue;
++			rtw_stop_drv_threads(iface);
++		}
++	}
++}
++void rtw_mi_stop_drv_threads(_adapter *adapter)
++{
++	_rtw_mi_stop_drv_threads(adapter, _FALSE);
++}
++void rtw_mi_buddy_stop_drv_threads(_adapter *adapter)
++{
++	_rtw_mi_stop_drv_threads(adapter, _TRUE);
++}
++
++static u8 _rtw_mi_cancel_all_timer(_adapter *adapter, void *data)
++{
++	rtw_cancel_all_timer(adapter);
++	return _TRUE;
++}
++void rtw_mi_cancel_all_timer(_adapter *adapter)
++{
++	_rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_cancel_all_timer);
++}
++void rtw_mi_buddy_cancel_all_timer(_adapter *adapter)
++{
++	_rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_cancel_all_timer);
++}
++
++static u8 _rtw_mi_reset_drv_sw(_adapter *adapter, void *data)
++{
++	rtw_reset_drv_sw(adapter);
++	return _TRUE;
++}
++void rtw_mi_reset_drv_sw(_adapter *adapter)
++{
++	_rtw_mi_process_without_schk(adapter, _FALSE, NULL, _rtw_mi_reset_drv_sw);
++}
++void rtw_mi_buddy_reset_drv_sw(_adapter *adapter)
++{
++	_rtw_mi_process_without_schk(adapter, _TRUE, NULL, _rtw_mi_reset_drv_sw);
++}
++
++static u8 _rtw_mi_intf_start(_adapter *adapter, void *data)
++{
++	rtw_intf_start(adapter);
++	return _TRUE;
++}
++void rtw_mi_intf_start(_adapter *adapter)
++{
++	_rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_intf_start);
++}
++void rtw_mi_buddy_intf_start(_adapter *adapter)
++{
++	_rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_intf_start);
++}
++
++static u8 _rtw_mi_intf_stop(_adapter *adapter, void *data)
++{
++	rtw_intf_stop(adapter);
++	return _TRUE;
++}
++void rtw_mi_intf_stop(_adapter *adapter)
++{
++	_rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_intf_stop);
++}
++void rtw_mi_buddy_intf_stop(_adapter *adapter)
++{
++	_rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_intf_stop);
++}
++
++#ifdef CONFIG_NEW_NETDEV_HDL
++u8 rtw_mi_hal_iface_init(_adapter *padapter)
++{
++	int i;
++	_adapter *iface;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++	u8 ret = _TRUE;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (iface && iface->netif_up)
++			rtw_hal_iface_init(padapter);
++	}
++	return ret;
++}
++#endif
++
++static u8 _rtw_mi_suspend_free_assoc_resource(_adapter *padapter, void *data)
++{
++	return rtw_suspend_free_assoc_resource(padapter);
++}
++void rtw_mi_suspend_free_assoc_resource(_adapter *adapter)
++{
++	_rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_suspend_free_assoc_resource);
++}
++void rtw_mi_buddy_suspend_free_assoc_resource(_adapter *adapter)
++{
++	_rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_suspend_free_assoc_resource);
++}
++
++static u8 _rtw_mi_is_scan_deny(_adapter *adapter, void *data)
++{
++	return rtw_is_scan_deny(adapter);
++}
++
++u8 rtw_mi_is_scan_deny(_adapter *adapter)
++{
++	return _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_is_scan_deny);
++
++}
++u8 rtw_mi_buddy_is_scan_deny(_adapter *adapter)
++{
++	return _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_is_scan_deny);
++}
++
++#ifdef CONFIG_SET_SCAN_DENY_TIMER
++static u8 _rtw_mi_set_scan_deny(_adapter *adapter, void *data)
++{
++	u32 ms = *(u32 *)data;
++
++	rtw_set_scan_deny(adapter, ms);
++	return _TRUE;
++}
++void rtw_mi_set_scan_deny(_adapter *adapter, u32 ms)
++{
++	u32 in_data = ms;
++
++	_rtw_mi_process(adapter, _FALSE, &in_data, _rtw_mi_set_scan_deny);
++}
++void rtw_mi_buddy_set_scan_deny(_adapter *adapter, u32 ms)
++{
++	u32 in_data = ms;
++
++	_rtw_mi_process(adapter, _TRUE, &in_data, _rtw_mi_set_scan_deny);
++}
++#endif /*CONFIG_SET_SCAN_DENY_TIMER*/
++
++static u8 _rtw_mi_beacon_update(_adapter *padapter, void *data)
++{
++	if (!MLME_IS_STA(padapter)
++	    && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++		RTW_INFO(ADPT_FMT" - update_beacon\n", ADPT_ARG(padapter));
++		update_beacon(padapter, 0xFF, NULL, _TRUE, 0);
++	}
++	return _TRUE;
++}
++
++void rtw_mi_beacon_update(_adapter *padapter)
++{
++	_rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_beacon_update);
++}
++
++void rtw_mi_buddy_beacon_update(_adapter *padapter)
++{
++	_rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_beacon_update);
++}
++
++#ifndef CONFIG_MI_WITH_MBSSID_CAM
++static u8 _rtw_mi_hal_dump_macaddr(_adapter *padapter, void *sel)
++{
++	u8 mac_addr[ETH_ALEN] = {0};
++
++	rtw_hal_get_hwreg(padapter, HW_VAR_MAC_ADDR, mac_addr);
++	RTW_PRINT_SEL(sel, ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n",
++					ADPT_ARG(padapter), padapter->hw_port, MAC_ARG(mac_addr));
++
++	return _TRUE;
++}
++void rtw_mi_hal_dump_macaddr(void *sel, _adapter *padapter)
++{
++	_rtw_mi_process(padapter, _FALSE, sel, _rtw_mi_hal_dump_macaddr);
++}
++void rtw_mi_buddy_hal_dump_macaddr(void *sel, _adapter *padapter)
++{
++	_rtw_mi_process(padapter, _TRUE, sel, _rtw_mi_hal_dump_macaddr);
++}
++#endif
++
++#ifdef CONFIG_PCI_HCI
++static u8 _rtw_mi_xmit_tasklet_schedule(_adapter *padapter, void *data)
++{
++	if (rtw_txframes_pending(padapter)) {
++		/* try to deal with the pending packets */
++		tasklet_hi_schedule(&(padapter->xmitpriv.xmit_tasklet));
++	}
++	return _TRUE;
++}
++void rtw_mi_xmit_tasklet_schedule(_adapter *padapter)
++{
++	_rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_xmit_tasklet_schedule);
++}
++void rtw_mi_buddy_xmit_tasklet_schedule(_adapter *padapter)
++{
++	_rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_xmit_tasklet_schedule);
++}
++#endif
++
++u8 _rtw_mi_busy_traffic_check(_adapter *padapter, void *data)
++{
++	return padapter->mlmepriv.LinkDetectInfo.bBusyTraffic;
++}
++
++u8 rtw_mi_busy_traffic_check(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_busy_traffic_check);
++}
++u8 rtw_mi_buddy_busy_traffic_check(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_busy_traffic_check);
++}
++static u8 _rtw_mi_check_mlmeinfo_state(_adapter *padapter, void *data)
++{
++	u32 state = *(u32 *)data;
++	struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv;
++
++	/*if (mlmeext_msr(mlmeext) == state)*/
++	if (check_mlmeinfo_state(mlmeext, state))
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++u8 rtw_mi_check_mlmeinfo_state(_adapter *padapter, u32 state)
++{
++	u32 in_data = state;
++
++	return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_check_mlmeinfo_state);
++}
++
++u8 rtw_mi_buddy_check_mlmeinfo_state(_adapter *padapter, u32 state)
++{
++	u32 in_data = state;
++
++	return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_check_mlmeinfo_state);
++}
++
++/*#define DBG_DUMP_FW_STATE*/
++#ifdef DBG_DUMP_FW_STATE
++static void rtw_dbg_dump_fwstate(_adapter *padapter, sint state)
++{
++	u8 buf[32] = {0};
++
++	if (state & WIFI_FW_NULL_STATE) {
++		_rtw_memset(buf, 0, 32);
++		sprintf(buf, "WIFI_FW_NULL_STATE");
++		RTW_INFO(FUNC_ADPT_FMT"fwstate-%s\n", FUNC_ADPT_ARG(padapter), buf);
++	}
++
++	if (state & WIFI_ASOC_STATE) {
++		_rtw_memset(buf, 0, 32);
++		sprintf(buf, "WIFI_ASOC_STATE");
++		RTW_INFO(FUNC_ADPT_FMT"fwstate-%s\n", FUNC_ADPT_ARG(padapter), buf);
++	}
++
++	if (state & WIFI_UNDER_LINKING) {
++		_rtw_memset(buf, 0, 32);
++		sprintf(buf, "WIFI_UNDER_LINKING");
++		RTW_INFO(FUNC_ADPT_FMT"fwstate-%s\n", FUNC_ADPT_ARG(padapter), buf);
++	}
++
++	if (state & WIFI_UNDER_SURVEY) {
++		_rtw_memset(buf, 0, 32);
++		sprintf(buf, "WIFI_UNDER_SURVEY");
++		RTW_INFO(FUNC_ADPT_FMT"fwstate-%s\n", FUNC_ADPT_ARG(padapter), buf);
++	}
++}
++#endif
++
++static u8 _rtw_mi_check_fwstate(_adapter *padapter, void *data)
++{
++	u8 ret = _FALSE;
++
++	sint state = *(sint *)data;
++
++	if ((state == WIFI_FW_NULL_STATE) &&
++	    (padapter->mlmepriv.fw_state == WIFI_FW_NULL_STATE))
++		ret = _TRUE;
++	else if (_TRUE == check_fwstate(&padapter->mlmepriv, state))
++		ret = _TRUE;
++#ifdef DBG_DUMP_FW_STATE
++	if (ret)
++		rtw_dbg_dump_fwstate(padapter, state);
++#endif
++	return ret;
++}
++u8 rtw_mi_check_fwstate(_adapter *padapter, sint state)
++{
++	sint in_data = state;
++
++	return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_check_fwstate);
++}
++u8 rtw_mi_buddy_check_fwstate(_adapter *padapter, sint state)
++{
++	sint in_data = state;
++
++	return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_check_fwstate);
++}
++
++static u8 _rtw_mi_traffic_statistics(_adapter *padapter , void *data)
++{
++	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
++
++	/* Tx */
++	pdvobjpriv->traffic_stat.tx_bytes += padapter->xmitpriv.tx_bytes;
++	pdvobjpriv->traffic_stat.tx_pkts += padapter->xmitpriv.tx_pkts;
++	pdvobjpriv->traffic_stat.tx_drop += padapter->xmitpriv.tx_drop;
++
++	/* Rx */
++	pdvobjpriv->traffic_stat.rx_bytes += padapter->recvpriv.rx_bytes;
++	pdvobjpriv->traffic_stat.rx_pkts += padapter->recvpriv.rx_pkts;
++	pdvobjpriv->traffic_stat.rx_drop += padapter->recvpriv.rx_drop;
++	return _TRUE;
++}
++u8 rtw_mi_traffic_statistics(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_traffic_statistics);
++}
++
++static u8 _rtw_mi_check_miracast_enabled(_adapter *padapter , void *data)
++{
++	return is_miracast_enabled(padapter);
++}
++u8 rtw_mi_check_miracast_enabled(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_check_miracast_enabled);
++}
++
++#ifdef CONFIG_XMIT_THREAD_MODE
++static u8 _rtw_mi_check_pending_xmitbuf(_adapter *padapter , void *data)
++{
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++	return check_pending_xmitbuf(pxmitpriv);
++}
++u8 rtw_mi_check_pending_xmitbuf(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_check_pending_xmitbuf);
++}
++u8 rtw_mi_buddy_check_pending_xmitbuf(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_check_pending_xmitbuf);
++}
++#endif
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++static u8 _rtw_mi_dequeue_writeport(_adapter *padapter , bool exclude_self)
++{
++	int i;
++	u8	queue_empty = _TRUE;
++	_adapter *iface;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if ((iface) && rtw_is_adapter_up(iface)) {
++
++			if ((exclude_self) && (iface == padapter))
++				continue;
++
++			queue_empty &= _dequeue_writeport(iface);
++		}
++	}
++	return queue_empty;
++}
++u8 rtw_mi_dequeue_writeport(_adapter *padapter)
++{
++	return _rtw_mi_dequeue_writeport(padapter, _FALSE);
++}
++u8 rtw_mi_buddy_dequeue_writeport(_adapter *padapter)
++{
++	return _rtw_mi_dequeue_writeport(padapter, _TRUE);
++}
++#endif
++static void _rtw_mi_adapter_reset(_adapter *padapter , u8 exclude_self)
++{
++	int i;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		if (dvobj->padapters[i]) {
++			if ((exclude_self) && (dvobj->padapters[i] == padapter))
++				continue;
++			dvobj->padapters[i] = NULL;
++		}
++	}
++}
++
++void rtw_mi_adapter_reset(_adapter *padapter)
++{
++	_rtw_mi_adapter_reset(padapter, _FALSE);
++}
++
++void rtw_mi_buddy_adapter_reset(_adapter *padapter)
++{
++	_rtw_mi_adapter_reset(padapter, _TRUE);
++}
++
++static u8 _rtw_mi_dynamic_check_timer_handlder(_adapter *adapter, void *data)
++{
++	rtw_iface_dynamic_check_timer_handlder(adapter);
++	return _TRUE;
++}
++u8 rtw_mi_dynamic_check_timer_handlder(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_dynamic_check_timer_handlder);
++}
++u8 rtw_mi_buddy_dynamic_check_timer_handlder(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_dynamic_check_timer_handlder);
++}
++
++static u8 _rtw_mi_dynamic_chk_wk_hdl(_adapter *adapter, void *data)
++{
++	rtw_iface_dynamic_chk_wk_hdl(adapter);
++	return _TRUE;
++}
++u8 rtw_mi_dynamic_chk_wk_hdl(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_dynamic_chk_wk_hdl);
++}
++u8 rtw_mi_buddy_dynamic_chk_wk_hdl(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_dynamic_chk_wk_hdl);
++}
++
++static u8 _rtw_mi_os_xmit_schedule(_adapter *adapter, void *data)
++{
++	rtw_os_xmit_schedule(adapter);
++	return _TRUE;
++}
++u8 rtw_mi_os_xmit_schedule(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_os_xmit_schedule);
++}
++u8 rtw_mi_buddy_os_xmit_schedule(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_os_xmit_schedule);
++}
++
++static u8 _rtw_mi_report_survey_event(_adapter *adapter, void *data)
++{
++	union recv_frame *precv_frame = (union recv_frame *)data;
++
++	report_survey_event(adapter, precv_frame);
++	return _TRUE;
++}
++u8 rtw_mi_report_survey_event(_adapter *padapter, union recv_frame *precv_frame)
++{
++	return _rtw_mi_process(padapter, _FALSE, precv_frame, _rtw_mi_report_survey_event);
++}
++u8 rtw_mi_buddy_report_survey_event(_adapter *padapter, union recv_frame *precv_frame)
++{
++	return _rtw_mi_process(padapter, _TRUE, precv_frame, _rtw_mi_report_survey_event);
++}
++
++static u8 _rtw_mi_sreset_adapter_hdl(_adapter *adapter, void *data)
++{
++	u8 bstart = *(u8 *)data;
++
++	if (bstart)
++		sreset_start_adapter(adapter);
++	else
++		sreset_stop_adapter(adapter);
++	return _TRUE;
++}
++u8 rtw_mi_sreset_adapter_hdl(_adapter *padapter, u8 bstart)
++{
++	u8 in_data = bstart;
++
++	return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_sreset_adapter_hdl);
++}
++
++#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE)
++void rtw_mi_ap_info_restore(_adapter *adapter)
++{
++	int i;
++	_adapter *iface;
++	struct mlme_priv *pmlmepriv;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (iface) {
++			pmlmepriv = &iface->mlmepriv;
++
++			if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) {
++				RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(iface), MLME_IS_AP(iface) ? "AP" : "MESH");
++				rtw_iface_bcmc_sec_cam_map_restore(iface);
++			}
++		}
++	}
++}
++#endif /*#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE)*/
++
++u8 rtw_mi_buddy_sreset_adapter_hdl(_adapter *padapter, u8 bstart)
++{
++	u8 in_data = bstart;
++
++	return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_sreset_adapter_hdl);
++}
++static u8 _rtw_mi_tx_beacon_hdl(_adapter *adapter, void *data)
++{
++	if ((MLME_IS_AP(adapter) || MLME_IS_MESH(adapter))
++		&& check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE
++	) {
++		adapter->mlmepriv.update_bcn = _TRUE;
++#ifndef CONFIG_INTERRUPT_BASED_TXBCN
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_PCI_BCN_POLLING)
++		tx_beacon_hdl(adapter, NULL);
++#endif
++#endif
++	}
++	return _TRUE;
++}
++u8 rtw_mi_tx_beacon_hdl(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_tx_beacon_hdl);
++}
++u8 rtw_mi_buddy_tx_beacon_hdl(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_sreset_adapter_hdl);
++}
++
++static u8 _rtw_mi_set_tx_beacon_cmd(_adapter *adapter, void *data)
++{
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++
++	if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
++		if (pmlmepriv->update_bcn == _TRUE)
++			set_tx_beacon_cmd(adapter, 0);
++	}
++	return _TRUE;
++}
++u8 rtw_mi_set_tx_beacon_cmd(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_set_tx_beacon_cmd);
++}
++u8 rtw_mi_buddy_set_tx_beacon_cmd(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_set_tx_beacon_cmd);
++}
++
++#ifdef CONFIG_P2P
++static u8 _rtw_mi_p2p_chk_state(_adapter *adapter, void *data)
++{
++	struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
++	enum P2P_STATE state = *(enum P2P_STATE *)data;
++
++	return rtw_p2p_chk_state(pwdinfo, state);
++}
++u8 rtw_mi_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state)
++{
++	u8 in_data = p2p_state;
++
++	return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_p2p_chk_state);
++}
++u8 rtw_mi_buddy_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state)
++{
++	u8 in_data  = p2p_state;
++
++	return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_p2p_chk_state);
++}
++static u8 _rtw_mi_stay_in_p2p_mode(_adapter *adapter, void *data)
++{
++	struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
++
++	if (rtw_p2p_role(pwdinfo) != P2P_ROLE_DISABLE)
++		return _TRUE;
++	return _FALSE;
++}
++u8 rtw_mi_stay_in_p2p_mode(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_stay_in_p2p_mode);
++}
++u8 rtw_mi_buddy_stay_in_p2p_mode(_adapter *padapter)
++{
++	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_stay_in_p2p_mode);
++}
++#endif /*CONFIG_P2P*/
++
++_adapter *rtw_get_iface_by_id(_adapter *padapter, u8 iface_id)
++{
++	_adapter *iface = NULL;
++	struct dvobj_priv *dvobj;
++
++	if ((padapter == NULL) || (iface_id >= CONFIG_IFACE_NUMBER)) {
++		rtw_warn_on(1);
++		return iface;
++	}
++
++	dvobj = adapter_to_dvobj(padapter);
++	return dvobj->padapters[iface_id];
++}
++
++_adapter *rtw_get_iface_by_macddr(_adapter *padapter, const u8 *mac_addr)
++{
++	int i;
++	_adapter *iface = NULL;
++	u8 bmatch = _FALSE;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if ((iface) && (_rtw_memcmp(mac_addr, adapter_mac_addr(iface), ETH_ALEN))) {
++			bmatch = _TRUE;
++			break;
++		}
++	}
++	if (bmatch)
++		return iface;
++	else
++		return NULL;
++}
++
++_adapter *rtw_get_iface_by_hwport(_adapter *padapter, u8 hw_port)
++{
++	int i;
++	_adapter *iface = NULL;
++	u8 bmatch = _FALSE;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if ((iface) && (hw_port == iface->hw_port)) {
++			bmatch = _TRUE;
++			break;
++		}
++	}
++	if (bmatch)
++		return iface;
++	else
++		return NULL;
++}
++
++/*#define CONFIG_SKB_ALLOCATED*/
++#define DBG_SKB_PROCESS
++#ifdef DBG_SKB_PROCESS
++void rtw_dbg_skb_process(_adapter *padapter, union recv_frame *precvframe, union recv_frame *pcloneframe)
++{
++	_pkt *pkt_copy, *pkt_org;
++
++	pkt_org = precvframe->u.hdr.pkt;
++	pkt_copy = pcloneframe->u.hdr.pkt;
++	/*
++		RTW_INFO("%s ===== ORG SKB =====\n", __func__);
++		RTW_INFO(" SKB head(%p)\n", pkt_org->head);
++		RTW_INFO(" SKB data(%p)\n", pkt_org->data);
++		RTW_INFO(" SKB tail(%p)\n", pkt_org->tail);
++		RTW_INFO(" SKB end(%p)\n", pkt_org->end);
++
++		RTW_INFO(" recv frame head(%p)\n", precvframe->u.hdr.rx_head);
++		RTW_INFO(" recv frame data(%p)\n", precvframe->u.hdr.rx_data);
++		RTW_INFO(" recv frame tail(%p)\n", precvframe->u.hdr.rx_tail);
++		RTW_INFO(" recv frame end(%p)\n", precvframe->u.hdr.rx_end);
++
++		RTW_INFO("%s ===== COPY SKB =====\n", __func__);
++		RTW_INFO(" SKB head(%p)\n", pkt_copy->head);
++		RTW_INFO(" SKB data(%p)\n", pkt_copy->data);
++		RTW_INFO(" SKB tail(%p)\n", pkt_copy->tail);
++		RTW_INFO(" SKB end(%p)\n", pkt_copy->end);
++
++		RTW_INFO(" recv frame head(%p)\n", pcloneframe->u.hdr.rx_head);
++		RTW_INFO(" recv frame data(%p)\n", pcloneframe->u.hdr.rx_data);
++		RTW_INFO(" recv frame tail(%p)\n", pcloneframe->u.hdr.rx_tail);
++		RTW_INFO(" recv frame end(%p)\n", pcloneframe->u.hdr.rx_end);
++	*/
++	/*
++		RTW_INFO("%s => recv_frame adapter(%p,%p)\n", __func__, precvframe->u.hdr.adapter, pcloneframe->u.hdr.adapter);
++		RTW_INFO("%s => recv_frame dev(%p,%p)\n", __func__, pkt_org->dev , pkt_copy->dev);
++		RTW_INFO("%s => recv_frame len(%d,%d)\n", __func__, precvframe->u.hdr.len, pcloneframe->u.hdr.len);
++	*/
++	if (precvframe->u.hdr.len != pcloneframe->u.hdr.len)
++		RTW_INFO("%s [WARN]  recv_frame length(%d:%d) compare failed\n", __func__, precvframe->u.hdr.len, pcloneframe->u.hdr.len);
++
++	if (_rtw_memcmp(&precvframe->u.hdr.attrib, &pcloneframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib)) == _FALSE)
++		RTW_INFO("%s [WARN]  recv_frame attrib compare failed\n", __func__);
++
++	if (_rtw_memcmp(precvframe->u.hdr.rx_data, pcloneframe->u.hdr.rx_data, precvframe->u.hdr.len) == _FALSE)
++		RTW_INFO("%s [WARN]  recv_frame rx_data compare failed\n", __func__);
++
++}
++#endif
++
++static s32 _rtw_mi_buddy_clone_bcmc_packet(_adapter *adapter, union recv_frame *precvframe, u8 *pphy_status, union recv_frame *pcloneframe)
++{
++	s32 ret = _SUCCESS;
++#ifdef CONFIG_SKB_ALLOCATED
++	u8 *pbuf = precvframe->u.hdr.rx_data;
++#endif
++	struct rx_pkt_attrib *pattrib = NULL;
++
++	if (pcloneframe) {
++		pcloneframe->u.hdr.adapter = adapter;
++
++		_rtw_init_listhead(&pcloneframe->u.hdr.list);
++		pcloneframe->u.hdr.precvbuf = NULL;	/*can't access the precvbuf for new arch.*/
++		pcloneframe->u.hdr.len = 0;
++
++		_rtw_memcpy(&pcloneframe->u.hdr.attrib, &precvframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib));
++
++		pattrib = &pcloneframe->u.hdr.attrib;
++#ifdef CONFIG_SKB_ALLOCATED
++		if (rtw_os_alloc_recvframe(adapter, pcloneframe, pbuf, NULL) == _SUCCESS)
++#else
++		if (rtw_os_recvframe_duplicate_skb(adapter, pcloneframe, precvframe->u.hdr.pkt) == _SUCCESS)
++#endif
++		{
++#ifdef CONFIG_SKB_ALLOCATED
++			recvframe_put(pcloneframe, pattrib->pkt_len);
++#endif
++
++#ifdef DBG_SKB_PROCESS
++			rtw_dbg_skb_process(adapter, precvframe, pcloneframe);
++#endif
++
++			if (pphy_status)
++				rx_query_phy_status(pcloneframe, pphy_status);
++
++			ret = rtw_recv_entry(pcloneframe);
++		} else {
++			ret = -1;
++			RTW_INFO("%s()-%d: rtw_os_alloc_recvframe() failed!\n", __func__, __LINE__);
++		}
++
++	}
++	return ret;
++}
++
++void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvframe, u8 *pphy_status)
++{
++	int i;
++	s32 ret = _SUCCESS;
++	_adapter *iface = NULL;
++	union recv_frame *pcloneframe = NULL;
++	struct recv_priv *precvpriv = &padapter->recvpriv;/*primary_padapter*/
++	_queue *pfree_recv_queue = &precvpriv->free_recv_queue;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	u8 *fhead = get_recvframe_data(precvframe);
++	u8 type = GetFrameType(fhead);
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (!iface || iface == padapter)
++			continue;
++		if (rtw_is_adapter_up(iface) == _FALSE || iface->registered == 0)
++			continue;
++		if (type == WIFI_DATA_TYPE && !adapter_allow_bmc_data_rx(iface))
++			continue;
++
++		pcloneframe = rtw_alloc_recvframe(pfree_recv_queue);
++		if (pcloneframe) {
++			ret = _rtw_mi_buddy_clone_bcmc_packet(iface, precvframe, pphy_status, pcloneframe);
++			if (_SUCCESS != ret) {
++				if (ret == -1)
++					rtw_free_recvframe(pcloneframe, pfree_recv_queue);
++				/*RTW_INFO(ADPT_FMT"-clone BC/MC frame failed\n", ADPT_ARG(iface));*/
++			}
++		}
++	}
++
++}
++
++#ifdef CONFIG_PCI_HCI
++/*API be created temporary for MI, caller is interrupt-handler, PCIE's interrupt handler cannot apply to multi-AP*/
++_adapter *rtw_mi_get_ap_adapter(_adapter *padapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	int i;
++	_adapter *iface = NULL;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (!iface)
++			continue;
++
++		if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE
++		    && check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE)
++			break;
++
++	}
++	return iface;
++}
++#endif
++
++u8 rtw_mi_get_ld_sta_ifbmp(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	int i;
++	_adapter *iface = NULL;
++	u8 ifbmp = 0;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (!iface)
++			continue;
++
++		if (MLME_IS_STA(iface) && MLME_IS_ASOC(iface))
++			ifbmp |= BIT(i);
++	}
++
++	return ifbmp;
++}
++
++u8 rtw_mi_get_ap_mesh_ifbmp(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	int i;
++	_adapter *iface = NULL;
++	u8 ifbmp = 0;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (!iface)
++			continue;
++
++		if (CHK_MLME_STATE(iface, WIFI_AP_STATE | WIFI_MESH_STATE)
++			&& MLME_IS_ASOC(iface))
++			ifbmp |= BIT(i);
++	}
++
++	return ifbmp;
++}
++
++void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b)
++{
++#ifdef CONFIG_CONCURRENT_MODE
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++
++	int i;
++	_adapter *iface = NULL;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (!iface)
++			continue;
++
++		if (macid_ctl->iface_bmc[iface->iface_id] != INVALID_SEC_MAC_CAM_ID) {
++			if (macid_ctl->iface_bmc[iface->iface_id] == camid_a)
++				macid_ctl->iface_bmc[iface->iface_id] = camid_b;
++			else if (macid_ctl->iface_bmc[iface->iface_id] == camid_b)
++				macid_ctl->iface_bmc[iface->iface_id] = camid_a;
++			iface->securitypriv.dot118021x_bmc_cam_id  = macid_ctl->iface_bmc[iface->iface_id];
++		}
++	}
++#endif
++}
++
++u8 rtw_mi_get_assoc_if_num(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	u8 n_assoc_iface = 0;
++#if 1
++	u8 i;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		if (check_fwstate(&(dvobj->padapters[i]->mlmepriv), WIFI_ASOC_STATE))
++			n_assoc_iface++;
++	}
++#else
++	n_assoc_iface = DEV_STA_LD_NUM(dvobj) + DEV_AP_NUM(dvobj) + DEV_ADHOC_NUM(dvobj) + DEV_MESH_NUM(dvobj);
++#endif
++	return n_assoc_iface;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mlme.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mlme.c
+new file mode 100755
+index 000000000..8d4f98091
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mlme.c
+@@ -0,0 +1,5440 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_MLME_C_
++
++#include <hal_data.h>
++
++extern void indicate_wx_scan_complete_event(_adapter *padapter);
++extern u8 rtw_do_join(_adapter *padapter);
++
++
++void rtw_init_mlme_timer(_adapter *padapter)
++{
++	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++	rtw_init_timer(&(pmlmepriv->assoc_timer), padapter, rtw_join_timeout_handler, padapter);
++	rtw_init_timer(&(pmlmepriv->scan_to_timer), padapter, rtw_scan_timeout_handler, padapter);
++
++#ifdef CONFIG_SET_SCAN_DENY_TIMER
++	rtw_init_timer(&(pmlmepriv->set_scan_deny_timer), padapter, rtw_set_scan_deny_timer_hdl, padapter);
++#endif
++
++#ifdef RTK_DMP_PLATFORM
++	_init_workitem(&(pmlmepriv->Linkup_workitem), Linkup_workitem_callback, padapter);
++	_init_workitem(&(pmlmepriv->Linkdown_workitem), Linkdown_workitem_callback, padapter);
++#endif
++}
++
++sint	_rtw_init_mlme_priv(_adapter *padapter)
++{
++	sint	i;
++	u8	*pbuf;
++	struct wlan_network	*pnetwork;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	sint	res = _SUCCESS;
++
++
++	/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
++	/* _rtw_memset((u8 *)pmlmepriv, 0, sizeof(struct mlme_priv)); */
++
++
++	/*qos_priv*/
++	/*pmlmepriv->qospriv.qos_option = pregistrypriv->wmm_enable;*/
++
++	/*ht_priv*/
++#ifdef CONFIG_80211N_HT
++	pmlmepriv->htpriv.ampdu_enable = _FALSE;/*set to disabled*/
++#endif
++
++	pmlmepriv->nic_hdl = (u8 *)padapter;
++
++	pmlmepriv->pscanned = NULL;
++	init_fwstate(pmlmepriv, WIFI_STATION_STATE);
++	pmlmepriv->cur_network.network.InfrastructureMode = Ndis802_11AutoUnknown;
++	pmlmepriv->scan_mode = SCAN_ACTIVE; /* 1: active, 0: pasive. Maybe someday we should rename this varable to "active_mode" (Jeff) */
++
++	_rtw_spinlock_init(&(pmlmepriv->lock));
++	_rtw_init_queue(&(pmlmepriv->free_bss_pool));
++	_rtw_init_queue(&(pmlmepriv->scanned_queue));
++
++	set_scanned_network_val(pmlmepriv, 0);
++
++	_rtw_memset(&pmlmepriv->assoc_ssid, 0, sizeof(NDIS_802_11_SSID));
++
++	if (padapter->registrypriv.max_bss_cnt != 0)
++		pmlmepriv->max_bss_cnt = padapter->registrypriv.max_bss_cnt;
++	else if (rfctl->max_chan_nums <= MAX_CHANNEL_NUM_2G)
++		pmlmepriv->max_bss_cnt = MAX_BSS_CNT;
++	else
++		pmlmepriv->max_bss_cnt = MAX_BSS_CNT + MAX_BSS_CNT;
++
++
++	pbuf = rtw_zvmalloc(pmlmepriv->max_bss_cnt * (sizeof(struct wlan_network)));
++
++	if (pbuf == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++	pmlmepriv->free_bss_buf = pbuf;
++
++	pnetwork = (struct wlan_network *)pbuf;
++
++	for (i = 0; i < pmlmepriv->max_bss_cnt; i++) {
++		_rtw_init_listhead(&(pnetwork->list));
++
++		rtw_list_insert_tail(&(pnetwork->list), &(pmlmepriv->free_bss_pool.queue));
++
++		pnetwork++;
++	}
++
++	/* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */
++
++	rtw_clear_scan_deny(padapter);
++#ifdef CONFIG_ARP_KEEP_ALIVE
++	pmlmepriv->bGetGateway = 0;
++	pmlmepriv->GetGatewayTryCnt = 0;
++#endif
++
++#ifdef CONFIG_LAYER2_ROAMING
++#define RTW_ROAM_SCAN_RESULT_EXP_MS (5*1000)
++#define RTW_ROAM_RSSI_DIFF_TH 10
++#define RTW_ROAM_SCAN_INTERVAL (5)    /* 5*(2 second)*/
++#define RTW_ROAM_RSSI_THRESHOLD 70
++
++	pmlmepriv->roam_flags = 0
++				| RTW_ROAM_ON_EXPIRED
++#ifdef CONFIG_LAYER2_ROAMING_RESUME
++				| RTW_ROAM_ON_RESUME
++#endif
++#ifdef CONFIG_LAYER2_ROAMING_ACTIVE
++				| RTW_ROAM_ACTIVE
++#endif
++				;
++
++	pmlmepriv->roam_scanr_exp_ms = RTW_ROAM_SCAN_RESULT_EXP_MS;
++	pmlmepriv->roam_rssi_diff_th = RTW_ROAM_RSSI_DIFF_TH;
++	pmlmepriv->roam_scan_int 	 = RTW_ROAM_SCAN_INTERVAL;
++	pmlmepriv->roam_rssi_threshold = RTW_ROAM_RSSI_THRESHOLD;
++	pmlmepriv->need_to_roam = _FALSE;
++	pmlmepriv->last_roaming = rtw_get_current_time();
++#endif /* CONFIG_LAYER2_ROAMING */
++
++#ifdef CONFIG_RTW_80211R
++	rtw_ft_info_init(&pmlmepriv->ft_roam);
++#endif
++#ifdef CONFIG_LAYER2_ROAMING
++#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
++	rtw_roam_nb_info_init(padapter);
++	pmlmepriv->ch_cnt = 0;
++#endif	
++#endif
++
++	pmlmepriv->defs_lmt_sta = 2;
++	pmlmepriv->defs_lmt_time = 5;
++
++	rtw_init_mlme_timer(padapter);
++
++exit:
++
++
++	return res;
++}
++
++void rtw_mfree_mlme_priv_lock(struct mlme_priv *pmlmepriv);
++void rtw_mfree_mlme_priv_lock(struct mlme_priv *pmlmepriv)
++{
++	_rtw_spinlock_free(&pmlmepriv->lock);
++	_rtw_spinlock_free(&(pmlmepriv->free_bss_pool.lock));
++	_rtw_spinlock_free(&(pmlmepriv->scanned_queue.lock));
++}
++
++static void rtw_free_mlme_ie_data(u8 **ppie, u32 *plen)
++{
++	if (*ppie) {
++		rtw_mfree(*ppie, *plen);
++		*plen = 0;
++		*ppie = NULL;
++	}
++}
++
++void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv)
++{
++#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++	rtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len);
++	rtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len);
++	rtw_free_mlme_ie_data(&pmlmepriv->wps_beacon_ie, &pmlmepriv->wps_beacon_ie_len);
++	rtw_free_mlme_ie_data(&pmlmepriv->wps_probe_req_ie, &pmlmepriv->wps_probe_req_ie_len);
++	rtw_free_mlme_ie_data(&pmlmepriv->wps_probe_resp_ie, &pmlmepriv->wps_probe_resp_ie_len);
++	rtw_free_mlme_ie_data(&pmlmepriv->wps_assoc_resp_ie, &pmlmepriv->wps_assoc_resp_ie_len);
++
++	rtw_free_mlme_ie_data(&pmlmepriv->p2p_beacon_ie, &pmlmepriv->p2p_beacon_ie_len);
++	rtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_req_ie, &pmlmepriv->p2p_probe_req_ie_len);
++	rtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_resp_ie, &pmlmepriv->p2p_probe_resp_ie_len);
++	rtw_free_mlme_ie_data(&pmlmepriv->p2p_go_probe_resp_ie, &pmlmepriv->p2p_go_probe_resp_ie_len);
++	rtw_free_mlme_ie_data(&pmlmepriv->p2p_assoc_req_ie, &pmlmepriv->p2p_assoc_req_ie_len);
++	rtw_free_mlme_ie_data(&pmlmepriv->p2p_assoc_resp_ie, &pmlmepriv->p2p_assoc_resp_ie_len);
++#endif
++
++#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)
++	rtw_free_mlme_ie_data(&pmlmepriv->wfd_beacon_ie, &pmlmepriv->wfd_beacon_ie_len);
++	rtw_free_mlme_ie_data(&pmlmepriv->wfd_probe_req_ie, &pmlmepriv->wfd_probe_req_ie_len);
++	rtw_free_mlme_ie_data(&pmlmepriv->wfd_probe_resp_ie, &pmlmepriv->wfd_probe_resp_ie_len);
++	rtw_free_mlme_ie_data(&pmlmepriv->wfd_go_probe_resp_ie, &pmlmepriv->wfd_go_probe_resp_ie_len);
++	rtw_free_mlme_ie_data(&pmlmepriv->wfd_assoc_req_ie, &pmlmepriv->wfd_assoc_req_ie_len);
++	rtw_free_mlme_ie_data(&pmlmepriv->wfd_assoc_resp_ie, &pmlmepriv->wfd_assoc_resp_ie_len);
++#endif
++
++#ifdef CONFIG_RTW_80211R
++	rtw_free_mlme_ie_data(&pmlmepriv->auth_rsp, &pmlmepriv->auth_rsp_len);
++#endif
++#ifdef CONFIG_RTW_MBO
++	rtw_free_mlme_ie_data(&pmlmepriv->pcell_data_cap_ie, &pmlmepriv->cell_data_cap_len);
++#endif
++}
++
++#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)
++int rtw_mlme_update_wfd_ie_data(struct mlme_priv *mlme, u8 type, u8 *ie, u32 ie_len)
++{
++	_adapter *adapter = mlme_to_adapter(mlme);
++	struct wifi_display_info *wfd_info = &adapter->wfd_info;
++	u8 clear = 0;
++	u8 **t_ie = NULL;
++	u32 *t_ie_len = NULL;
++	int ret = _FAIL;
++
++	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
++		goto success;
++
++	if (wfd_info->wfd_enable == _TRUE)
++		goto success; /* WFD IE is build by self */
++
++	if (!ie && !ie_len)
++		clear = 1;
++	else if (!ie || !ie_len) {
++		RTW_PRINT(FUNC_ADPT_FMT" type:%u, ie:%p, ie_len:%u"
++			  , FUNC_ADPT_ARG(adapter), type, ie, ie_len);
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	switch (type) {
++	case MLME_BEACON_IE:
++		t_ie = &mlme->wfd_beacon_ie;
++		t_ie_len = &mlme->wfd_beacon_ie_len;
++		break;
++	case MLME_PROBE_REQ_IE:
++		t_ie = &mlme->wfd_probe_req_ie;
++		t_ie_len = &mlme->wfd_probe_req_ie_len;
++		break;
++	case MLME_PROBE_RESP_IE:
++		t_ie = &mlme->wfd_probe_resp_ie;
++		t_ie_len = &mlme->wfd_probe_resp_ie_len;
++		break;
++	case MLME_GO_PROBE_RESP_IE:
++		t_ie = &mlme->wfd_go_probe_resp_ie;
++		t_ie_len = &mlme->wfd_go_probe_resp_ie_len;
++		break;
++	case MLME_ASSOC_REQ_IE:
++		t_ie = &mlme->wfd_assoc_req_ie;
++		t_ie_len = &mlme->wfd_assoc_req_ie_len;
++		break;
++	case MLME_ASSOC_RESP_IE:
++		t_ie = &mlme->wfd_assoc_resp_ie;
++		t_ie_len = &mlme->wfd_assoc_resp_ie_len;
++		break;
++	default:
++		RTW_PRINT(FUNC_ADPT_FMT" unsupported type:%u"
++			  , FUNC_ADPT_ARG(adapter), type);
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (*t_ie) {
++		u32 free_len = *t_ie_len;
++		*t_ie_len = 0;
++		rtw_mfree(*t_ie, free_len);
++		*t_ie = NULL;
++	}
++
++	if (!clear) {
++		*t_ie = rtw_malloc(ie_len);
++		if (*t_ie == NULL) {
++			RTW_ERR(FUNC_ADPT_FMT" type:%u, rtw_malloc() fail\n"
++				, FUNC_ADPT_ARG(adapter), type);
++			goto exit;
++		}
++		_rtw_memcpy(*t_ie, ie, ie_len);
++		*t_ie_len = ie_len;
++	}
++
++	if (*t_ie && *t_ie_len) {
++		u8 *attr_content;
++		u32 attr_contentlen = 0;
++
++		attr_content = rtw_get_wfd_attr_content(*t_ie, *t_ie_len, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen);
++		if (attr_content && attr_contentlen) {
++			if (RTW_GET_BE16(attr_content + 2) != wfd_info->rtsp_ctrlport) {
++				wfd_info->rtsp_ctrlport = RTW_GET_BE16(attr_content + 2);
++				RTW_INFO(FUNC_ADPT_FMT" type:%u, RTSP CTRL port = %u\n"
++					, FUNC_ADPT_ARG(adapter), type, wfd_info->rtsp_ctrlport);
++			}
++		}
++	}
++
++success:
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++#endif /* defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) */
++
++void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv)
++{
++	_adapter *adapter = mlme_to_adapter(pmlmepriv);
++	if (NULL == pmlmepriv) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++	rtw_free_mlme_priv_ie_data(pmlmepriv);
++
++	if (pmlmepriv) {
++		rtw_mfree_mlme_priv_lock(pmlmepriv);
++
++		if (pmlmepriv->free_bss_buf)
++			rtw_vmfree(pmlmepriv->free_bss_buf, pmlmepriv->max_bss_cnt * sizeof(struct wlan_network));
++	}
++exit:
++	return;
++}
++
++sint	_rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork)
++{
++	_irqL irqL;
++
++
++	if (pnetwork == NULL)
++		goto exit;
++
++	_enter_critical_bh(&queue->lock, &irqL);
++
++	rtw_list_insert_tail(&pnetwork->list, &queue->queue);
++
++	_exit_critical_bh(&queue->lock, &irqL);
++
++exit:
++
++
++	return _SUCCESS;
++}
++
++/*
++struct	wlan_network *_rtw_dequeue_network(_queue *queue)
++{
++	_irqL irqL;
++
++	struct wlan_network *pnetwork;
++
++
++	_enter_critical_bh(&queue->lock, &irqL);
++
++	if (_rtw_queue_empty(queue) == _TRUE)
++
++		pnetwork = NULL;
++
++	else
++	{
++		pnetwork = LIST_CONTAINOR(get_next(&queue->queue), struct wlan_network, list);
++
++		rtw_list_delete(&(pnetwork->list));
++	}
++
++	_exit_critical_bh(&queue->lock, &irqL);
++
++
++	return pnetwork;
++}
++*/
++
++struct	wlan_network *_rtw_alloc_network(struct	mlme_priv *pmlmepriv) /* (_queue *free_queue) */
++{
++	_irqL	irqL;
++	struct	wlan_network	*pnetwork;
++	_queue *free_queue = &pmlmepriv->free_bss_pool;
++	_list *plist = NULL;
++
++
++	_enter_critical_bh(&free_queue->lock, &irqL);
++
++	if (_rtw_queue_empty(free_queue) == _TRUE) {
++		pnetwork = NULL;
++		goto exit;
++	}
++	plist = get_next(&(free_queue->queue));
++
++	pnetwork = LIST_CONTAINOR(plist , struct wlan_network, list);
++
++	rtw_list_delete(&pnetwork->list);
++
++	pnetwork->network_type = 0;
++	pnetwork->fixed = _FALSE;
++	pnetwork->last_scanned = rtw_get_current_time();
++	pnetwork->last_non_hidden_ssid_ap = pnetwork->last_scanned;
++#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT
++	pnetwork->acnode_stime = 0;
++	pnetwork->acnode_notify_etime = 0;
++#endif
++
++	pnetwork->aid = 0;
++	pnetwork->join_res = 0;
++
++	pmlmepriv->num_of_scanned++;
++
++exit:
++	_exit_critical_bh(&free_queue->lock, &irqL);
++
++
++	return pnetwork;
++}
++
++void _rtw_free_network(struct	mlme_priv *pmlmepriv , struct wlan_network *pnetwork, u8 isfreeall)
++{
++	u32 delta_time;
++	u32 lifetime = SCANQUEUE_LIFETIME;
++	_irqL irqL;
++	_queue *free_queue = &(pmlmepriv->free_bss_pool);
++
++
++	if (pnetwork == NULL)
++		goto exit;
++
++	if (pnetwork->fixed == _TRUE)
++		goto exit;
++
++	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
++	    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
++		lifetime = 1;
++
++	if (!isfreeall) {
++		delta_time = (u32) rtw_get_passing_time_ms(pnetwork->last_scanned);
++		if (delta_time < lifetime) /* unit:msec */
++			goto exit;
++	}
++
++	_enter_critical_bh(&free_queue->lock, &irqL);
++
++	rtw_list_delete(&(pnetwork->list));
++
++	rtw_list_insert_tail(&(pnetwork->list), &(free_queue->queue));
++
++	pmlmepriv->num_of_scanned--;
++
++
++	/* RTW_INFO("_rtw_free_network:SSID=%s\n", pnetwork->network.Ssid.Ssid); */
++
++	_exit_critical_bh(&free_queue->lock, &irqL);
++
++exit:
++	return;
++}
++
++void _rtw_free_network_nolock(struct	mlme_priv *pmlmepriv, struct wlan_network *pnetwork)
++{
++
++	_queue *free_queue = &(pmlmepriv->free_bss_pool);
++
++
++	if (pnetwork == NULL)
++		goto exit;
++
++	if (pnetwork->fixed == _TRUE)
++		goto exit;
++
++	/* _enter_critical(&free_queue->lock, &irqL); */
++
++	rtw_list_delete(&(pnetwork->list));
++
++	rtw_list_insert_tail(&(pnetwork->list), get_list_head(free_queue));
++
++	pmlmepriv->num_of_scanned--;
++
++	/* _exit_critical(&free_queue->lock, &irqL); */
++
++exit:
++	return;
++}
++
++void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall)
++{
++	_irqL irqL;
++	_list *phead, *plist;
++	struct wlan_network *pnetwork;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	_queue *scanned_queue = &pmlmepriv->scanned_queue;
++
++
++
++	_enter_critical_bh(&scanned_queue->lock, &irqL);
++
++	phead = get_list_head(scanned_queue);
++	plist = get_next(phead);
++
++	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++		plist = get_next(plist);
++
++		_rtw_free_network(pmlmepriv, pnetwork, isfreeall);
++
++	}
++
++	_exit_critical_bh(&scanned_queue->lock, &irqL);
++
++
++}
++
++
++
++
++sint rtw_if_up(_adapter *padapter)
++{
++
++	sint res;
++
++	if (RTW_CANNOT_RUN(padapter) ||
++	    (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _FALSE)) {
++		res = _FALSE;
++	} else
++		res =  _TRUE;
++
++	return res;
++}
++
++
++void rtw_generate_random_ibss(u8 *pibss)
++{
++	*((u32 *)(&pibss[2])) = rtw_random32();
++	pibss[0] = 0x02; /* in ad-hoc mode local bit must set to 1 */
++	pibss[1] = 0x11;
++	pibss[2] = 0x87;
++}
++
++u8 *rtw_get_capability_from_ie(u8 *ie)
++{
++	return ie + 8 + 2;
++}
++
++
++u16 rtw_get_capability(WLAN_BSSID_EX *bss)
++{
++	u16	val;
++
++	_rtw_memcpy((u8 *)&val, rtw_get_capability_from_ie(bss->IEs), 2);
++
++	return le16_to_cpu(val);
++}
++
++u8 *rtw_get_timestampe_from_ie(u8 *ie)
++{
++	return ie + 0;
++}
++
++u8 *rtw_get_beacon_interval_from_ie(u8 *ie)
++{
++	return ie + 8;
++}
++
++
++int	rtw_init_mlme_priv(_adapter *padapter) /* (struct	mlme_priv *pmlmepriv) */
++{
++	int	res;
++	res = _rtw_init_mlme_priv(padapter);/* (pmlmepriv); */
++	return res;
++}
++
++void rtw_free_mlme_priv(struct mlme_priv *pmlmepriv)
++{
++	_rtw_free_mlme_priv(pmlmepriv);
++}
++
++int	rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork);
++int	rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork)
++{
++	int	res;
++	res = _rtw_enqueue_network(queue, pnetwork);
++	return res;
++}
++
++/*
++static struct	wlan_network *rtw_dequeue_network(_queue *queue)
++{
++	struct wlan_network *pnetwork;
++	pnetwork = _rtw_dequeue_network(queue);
++	return pnetwork;
++}
++*/
++
++struct	wlan_network *rtw_alloc_network(struct	mlme_priv *pmlmepriv);
++struct	wlan_network *rtw_alloc_network(struct	mlme_priv *pmlmepriv) /* (_queue	*free_queue) */
++{
++	struct	wlan_network	*pnetwork;
++	pnetwork = _rtw_alloc_network(pmlmepriv);
++	return pnetwork;
++}
++
++void rtw_free_network(struct mlme_priv *pmlmepriv, struct	wlan_network *pnetwork, u8 is_freeall);
++void rtw_free_network(struct mlme_priv *pmlmepriv, struct	wlan_network *pnetwork, u8 is_freeall)/* (struct	wlan_network *pnetwork, _queue	*free_queue) */
++{
++	_rtw_free_network(pmlmepriv, pnetwork, is_freeall);
++}
++
++void rtw_free_network_nolock(_adapter *padapter, struct wlan_network *pnetwork);
++void rtw_free_network_nolock(_adapter *padapter, struct wlan_network *pnetwork)
++{
++	_rtw_free_network_nolock(&(padapter->mlmepriv), pnetwork);
++#ifdef CONFIG_IOCTL_CFG80211
++	rtw_cfg80211_unlink_bss(padapter, pnetwork);
++#endif /* CONFIG_IOCTL_CFG80211 */
++}
++
++
++void rtw_free_network_queue(_adapter *dev, u8 isfreeall)
++{
++	_rtw_free_network_queue(dev, isfreeall);
++}
++
++struct wlan_network *_rtw_find_network(_queue *scanned_queue, const u8 *addr)
++{
++	_list	*phead, *plist;
++	struct	wlan_network *pnetwork = NULL;
++	u8 zero_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
++
++	if (_rtw_memcmp(zero_addr, addr, ETH_ALEN)) {
++		pnetwork = NULL;
++		goto exit;
++	}
++
++	phead = get_list_head(scanned_queue);
++	plist = get_next(phead);
++
++	while (plist != phead) {
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network , list);
++
++		if (_rtw_memcmp(addr, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE)
++			break;
++
++		plist = get_next(plist);
++	}
++
++	if (plist == phead)
++		pnetwork = NULL;
++
++exit:
++	return pnetwork;
++}
++
++struct wlan_network *rtw_find_network(_queue *scanned_queue, const u8 *addr)
++{
++	struct	wlan_network *pnetwork;
++	_irqL irqL;
++
++	 _enter_critical_bh(&scanned_queue->lock, &irqL);
++	pnetwork = _rtw_find_network(scanned_queue, addr);
++	_exit_critical_bh(&scanned_queue->lock, &irqL);
++
++	return pnetwork;
++}
++
++int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork)
++{
++	int ret = _TRUE;
++	struct security_priv *psecuritypriv = &adapter->securitypriv;
++
++	if ((psecuritypriv->dot11PrivacyAlgrthm != _NO_PRIVACY_) &&
++	    (pnetwork->network.Privacy == 0))
++		ret = _FALSE;
++	else if ((psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_) &&
++		 (pnetwork->network.Privacy == 1))
++		ret = _FALSE;
++	else
++		ret = _TRUE;
++
++	return ret;
++
++}
++
++inline int is_same_ess(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b)
++{
++	return (a->Ssid.SsidLength == b->Ssid.SsidLength)
++	       &&  _rtw_memcmp(a->Ssid.Ssid, b->Ssid.Ssid, a->Ssid.SsidLength) == _TRUE;
++}
++
++int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature)
++{
++	u16 s_cap, d_cap;
++
++
++	if (rtw_bug_check(dst, src, &s_cap, &d_cap) == _FALSE)
++		return _FALSE;
++
++	_rtw_memcpy((u8 *)&s_cap, rtw_get_capability_from_ie(src->IEs), 2);
++	_rtw_memcpy((u8 *)&d_cap, rtw_get_capability_from_ie(dst->IEs), 2);
++
++
++	s_cap = le16_to_cpu(s_cap);
++	d_cap = le16_to_cpu(d_cap);
++
++
++#ifdef CONFIG_P2P
++	if ((feature == 1) && /* 1: P2P supported */
++	    (_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN) == _TRUE)
++	   )
++		return _TRUE;
++#endif
++
++	/* Wi-Fi driver doesn't consider the situation of BCN and ProbRsp sent from the same hidden AP, 
++	  * it considers these two packets are sent from different AP. 
++	  * Therefore, the scan queue may store two scan results of the same hidden AP, likes below.
++	  *
++	  *  index            bssid              ch    RSSI   SdBm  Noise   age          flag             ssid
++	  *    1    00:e0:4c:55:50:01    153   -73     -73        0     7044   [WPS][ESS]     RTK5G
++	  *    3    00:e0:4c:55:50:01    153   -73     -73        0     7044   [WPS][ESS]
++	  *
++	  * Original rules will compare Ssid, SsidLength, MacAddress, s_cap, d_cap at the same time.
++	  * Wi-Fi driver will assume that the BCN and ProbRsp sent from the same hidden AP are the same network
++	  * after we add an additional rule to compare SsidLength and Ssid.
++	  * It means the scan queue will not store two scan results of the same hidden AP, it only store ProbRsp.
++	  * For customer request.
++	  */
++	  
++	if (((_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN)) == _TRUE) &&
++		((s_cap & WLAN_CAPABILITY_IBSS) == (d_cap & WLAN_CAPABILITY_IBSS)) &&
++		((s_cap & WLAN_CAPABILITY_BSS) == (d_cap & WLAN_CAPABILITY_BSS))) {
++		if ((src->Ssid.SsidLength == dst->Ssid.SsidLength) && 
++			(((_rtw_memcmp(src->Ssid.Ssid, dst->Ssid.Ssid, src->Ssid.SsidLength)) == _TRUE) || //Case of normal AP
++			(is_all_null(src->Ssid.Ssid, src->Ssid.SsidLength) == _TRUE || is_all_null(dst->Ssid.Ssid, dst->Ssid.SsidLength) == _TRUE))) //Case of hidden AP
++			return _TRUE;
++		else if ((src->Ssid.SsidLength == 0 || dst->Ssid.SsidLength == 0)) //Case of hidden AP
++			return _TRUE;
++		else
++			return _FALSE;
++	} else {
++		return _FALSE;
++	}
++}
++
++struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network)
++{
++	_list *phead, *plist;
++	struct wlan_network *found = NULL;
++
++	phead = get_list_head(scanned_queue);
++	plist = get_next(phead);
++
++	while (plist != phead) {
++		found = LIST_CONTAINOR(plist, struct wlan_network , list);
++
++		if (is_same_network(&network->network, &found->network, 0))
++			break;
++
++		plist = get_next(plist);
++	}
++
++	if (plist == phead)
++		found = NULL;
++
++	return found;
++}
++
++struct wlan_network *rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network)
++{
++	_irqL irqL;
++	struct wlan_network *found = NULL;
++
++	if (scanned_queue == NULL || network == NULL)
++		goto exit;
++
++	_enter_critical_bh(&scanned_queue->lock, &irqL);
++	found = _rtw_find_same_network(scanned_queue, network);
++	_exit_critical_bh(&scanned_queue->lock, &irqL);
++
++exit:
++	return found;
++}
++
++struct	wlan_network	*rtw_get_oldest_wlan_network(_queue *scanned_queue)
++{
++	_list	*plist, *phead;
++
++
++	struct	wlan_network	*pwlan = NULL;
++	struct	wlan_network	*oldest = NULL;
++	phead = get_list_head(scanned_queue);
++
++	plist = get_next(phead);
++
++	while (1) {
++
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		pwlan = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++		if (pwlan->fixed != _TRUE) {
++			if (oldest == NULL || rtw_time_after(oldest->last_scanned, pwlan->last_scanned))
++				oldest = pwlan;
++		}
++
++		plist = get_next(plist);
++	}
++	return oldest;
++
++}
++
++void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src,
++		    _adapter *padapter, bool update_ie)
++{
++#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1
++	u8 ss_ori = dst->PhyInfo.SignalStrength;
++	u8 sq_ori = dst->PhyInfo.SignalQuality;
++	u8 ss_smp = src->PhyInfo.SignalStrength;
++	long rssi_smp = src->Rssi;
++#endif
++	long rssi_ori = dst->Rssi;
++
++	u8 sq_smp = src->PhyInfo.SignalQuality;
++	u8 ss_final;
++	u8 sq_final;
++	long rssi_final;
++
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	rtw_hal_antdiv_rssi_compared(padapter, dst, src); /* this will update src.Rssi, need consider again */
++#endif
++
++#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1
++	if (strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) {
++		RTW_INFO(FUNC_ADPT_FMT" %s("MAC_FMT", ch%u) ss_ori:%3u, sq_ori:%3u, rssi_ori:%3ld, ss_smp:%3u, sq_smp:%3u, rssi_smp:%3ld\n"
++			 , FUNC_ADPT_ARG(padapter)
++			, src->Ssid.Ssid, MAC_ARG(src->MacAddress), src->Configuration.DSConfig
++			 , ss_ori, sq_ori, rssi_ori
++			 , ss_smp, sq_smp, rssi_smp
++			);
++	}
++#endif
++
++	/* The rule below is 1/5 for sample value, 4/5 for history value */
++	if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) && is_same_network(&(padapter->mlmepriv.cur_network.network), src, 0)) {
++		/* Take the recvpriv's value for the connected AP*/
++		ss_final = padapter->recvpriv.signal_strength;
++		sq_final = padapter->recvpriv.signal_qual;
++		/* the rssi value here is undecorated, and will be used for antenna diversity */
++		if (sq_smp != 101) /* from the right channel */
++			rssi_final = (src->Rssi + dst->Rssi * 4) / 5;
++		else
++			rssi_final = rssi_ori;
++	} else {
++		if (sq_smp != 101) { /* from the right channel */
++			ss_final = ((u32)(src->PhyInfo.SignalStrength) + (u32)(dst->PhyInfo.SignalStrength) * 4) / 5;
++			sq_final = ((u32)(src->PhyInfo.SignalQuality) + (u32)(dst->PhyInfo.SignalQuality) * 4) / 5;
++			rssi_final = (src->Rssi + dst->Rssi * 4) / 5;
++		} else {
++			/* bss info not receving from the right channel, use the original RX signal infos */
++			ss_final = dst->PhyInfo.SignalStrength;
++			sq_final = dst->PhyInfo.SignalQuality;
++			rssi_final = dst->Rssi;
++		}
++
++	}
++
++	if (update_ie) {
++		dst->Reserved[0] = src->Reserved[0];
++		dst->Reserved[1] = src->Reserved[1];
++		_rtw_memcpy((u8 *)dst, (u8 *)src, get_WLAN_BSSID_EX_sz(src));
++	}
++
++	dst->PhyInfo.SignalStrength = ss_final;
++	dst->PhyInfo.SignalQuality = sq_final;
++	dst->Rssi = rssi_final;
++
++#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1
++	if (strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) {
++		RTW_INFO(FUNC_ADPT_FMT" %s("MAC_FMT"), SignalStrength:%u, SignalQuality:%u, RawRSSI:%ld\n"
++			 , FUNC_ADPT_ARG(padapter)
++			, dst->Ssid.Ssid, MAC_ARG(dst->MacAddress), dst->PhyInfo.SignalStrength, dst->PhyInfo.SignalQuality, dst->Rssi);
++	}
++#endif
++
++#if 0 /* old codes, may be useful one day...
++ * 	RTW_INFO("update_network: rssi=0x%lx dst->Rssi=%d ,dst->Rssi=0x%lx , src->Rssi=0x%lx",(dst->Rssi+src->Rssi)/2,dst->Rssi,dst->Rssi,src->Rssi); */
++	if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) && is_same_network(&(padapter->mlmepriv.cur_network.network), src)) {
++
++		/* RTW_INFO("b:ssid=%s update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Ssid.Ssid,src->Rssi,padapter->recvpriv.signal); */
++		if (padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) {
++			padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX;
++			last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index];
++			padapter->recvpriv.signal_qual_data.total_val -= last_evm;
++		}
++		padapter->recvpriv.signal_qual_data.total_val += query_rx_pwr_percentage(src->Rssi);
++
++		padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = query_rx_pwr_percentage(src->Rssi);
++		if (padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX)
++			padapter->recvpriv.signal_qual_data.index = 0;
++
++		/* RTW_INFO("Total SQ=%d  pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, src->Rssi); */
++
++		/* <1> Showed on UI for user,in percentage. */
++		tmpVal = padapter->recvpriv.signal_qual_data.total_val / padapter->recvpriv.signal_qual_data.total_num;
++		padapter->recvpriv.signal = (u8)tmpVal; /* Link quality */
++
++		src->Rssi = translate_percentage_to_dbm(padapter->recvpriv.signal) ;
++	} else {
++		/*	RTW_INFO("ELSE:ssid=%s update_network: src->rssi=0x%d dst->rssi=%d\n",src->Ssid.Ssid,src->Rssi,dst->Rssi); */
++		src->Rssi = (src->Rssi + dst->Rssi) / 2; /* dBM */
++	}
++
++	/*	RTW_INFO("a:update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Rssi,padapter->recvpriv.signal); */
++
++#endif
++
++}
++
++static void update_current_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork)
++{
++	struct	mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
++
++
++	rtw_bug_check(&(pmlmepriv->cur_network.network),
++		      &(pmlmepriv->cur_network.network),
++		      &(pmlmepriv->cur_network.network),
++		      &(pmlmepriv->cur_network.network));
++
++	if ((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) && (is_same_network(&(pmlmepriv->cur_network.network), pnetwork, 0))) {
++
++		/* if(pmlmepriv->cur_network.network.IELength<= pnetwork->IELength) */
++		{
++			update_network(&(pmlmepriv->cur_network.network), pnetwork, adapter, _TRUE);
++			rtw_update_protection(adapter, (pmlmepriv->cur_network.network.IEs) + sizeof(NDIS_802_11_FIXED_IEs),
++				      pmlmepriv->cur_network.network.IELength);
++		}
++	}
++
++
++}
++
++
++/*
++
++Caller must hold pmlmepriv->lock first.
++
++
++*/
++bool rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target)
++{
++	_irqL irqL;
++	_list	*plist, *phead;
++	u32	bssid_ex_sz;
++	struct mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
++#ifdef CONFIG_P2P
++	struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
++#endif /* CONFIG_P2P */
++	_queue	*queue	= &(pmlmepriv->scanned_queue);
++	struct wlan_network	*pnetwork = NULL;
++	struct wlan_network	*choice = NULL;
++	int target_find = 0;
++	u8 feature = 0;
++	bool update_ie = _FALSE;
++
++	_enter_critical_bh(&queue->lock, &irqL);
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++
++#if 0
++	RTW_INFO("%s => ssid:%s , rssi:%ld , ss:%d\n",
++		__func__, target->Ssid.Ssid, target->Rssi, target->PhyInfo.SignalStrength);
++#endif
++
++#ifdef CONFIG_P2P
++	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++		feature = 1; /* p2p enable */
++#endif
++
++	while (1) {
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++		rtw_bug_check(pnetwork, pnetwork, pnetwork, pnetwork);
++
++#ifdef CONFIG_P2P
++		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) &&
++		    (_rtw_memcmp(pnetwork->network.MacAddress, target->MacAddress, ETH_ALEN) == _TRUE)) {
++			target_find = 1;
++			break;
++		}
++#endif
++
++		if (is_same_network(&(pnetwork->network), target, feature)) {
++			target_find = 1;
++			break;
++		}
++
++		if (rtw_roam_flags(adapter)) {
++			/* TODO: don't  select netowrk in the same ess as choice if it's new enough*/
++		}
++		if (pnetwork->fixed) {
++			plist = get_next(plist);
++			continue;
++		}
++			
++#ifdef CONFIG_RSSI_PRIORITY
++		if ((choice == NULL) || (pnetwork->network.PhyInfo.SignalStrength < choice->network.PhyInfo.SignalStrength))
++			#ifdef CONFIG_RTW_MESH
++			if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter)
++				|| !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network))
++			#endif
++				choice = pnetwork;
++#else
++		if (choice == NULL || rtw_time_after(choice->last_scanned, pnetwork->last_scanned))
++			#ifdef CONFIG_RTW_MESH
++			if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter)
++				|| !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network))
++			#endif
++				choice = pnetwork;
++#endif
++		plist = get_next(plist);
++
++	}
++
++
++	/* If we didn't find a match, then get a new network slot to initialize
++	 * with this beacon's information */
++	/* if (rtw_end_of_queue_search(phead,plist)== _TRUE) { */
++	if (!target_find) {
++		if (_rtw_queue_empty(&(pmlmepriv->free_bss_pool)) == _TRUE) {
++			/* If there are no more slots, expire the choice */
++			/* list_del_init(&choice->list); */
++			pnetwork = choice;
++			if (pnetwork == NULL)
++				goto unlock_scan_queue;
++
++#ifdef CONFIG_RSSI_PRIORITY
++		RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT"  will be deleted from scanned_queue (rssi:%ld , ss:%d)\n",
++			__func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Rssi, pnetwork->network.PhyInfo.SignalStrength);
++#else
++		RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT" will be deleted from scanned_queue\n",
++			__func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress));
++#endif
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++			rtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(target->PhyInfo.Optimum_antenna), NULL);
++#endif
++			_rtw_memcpy(&(pnetwork->network), target,  get_WLAN_BSSID_EX_sz(target));
++			pnetwork->bcn_keys_valid = 0;
++			if (target->Reserved[0] == BSS_TYPE_BCN || target->Reserved[0] == BSS_TYPE_PROB_RSP)
++				rtw_update_bcn_keys_of_network(pnetwork);
++			/* variable initialize */
++			pnetwork->fixed = _FALSE;
++			pnetwork->last_scanned = rtw_get_current_time();
++			pnetwork->last_non_hidden_ssid_ap = pnetwork->last_scanned;
++			#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT
++			pnetwork->acnode_stime = 0;
++			pnetwork->acnode_notify_etime = 0;
++			#endif
++
++			pnetwork->network_type = 0;
++			pnetwork->aid = 0;
++			pnetwork->join_res = 0;
++
++			/* bss info not receving from the right channel */
++			if (pnetwork->network.PhyInfo.SignalQuality == 101)
++				pnetwork->network.PhyInfo.SignalQuality = 0;
++		} else {
++			/* Otherwise just pull from the free list */
++
++			pnetwork = rtw_alloc_network(pmlmepriv); /* will update scan_time */
++			if (pnetwork == NULL)
++				goto unlock_scan_queue;
++
++			bssid_ex_sz = get_WLAN_BSSID_EX_sz(target);
++			target->Length = bssid_ex_sz;
++#ifdef CONFIG_ANTENNA_DIVERSITY
++			rtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(target->PhyInfo.Optimum_antenna), NULL);
++#endif
++			_rtw_memcpy(&(pnetwork->network), target, bssid_ex_sz);
++			pnetwork->bcn_keys_valid = 0;
++			if (target->Reserved[0] == BSS_TYPE_BCN || target->Reserved[0] == BSS_TYPE_PROB_RSP)
++				rtw_update_bcn_keys_of_network(pnetwork);
++
++			/* bss info not receving from the right channel */
++			if (pnetwork->network.PhyInfo.SignalQuality == 101)
++				pnetwork->network.PhyInfo.SignalQuality = 0;
++
++			rtw_list_insert_tail(&(pnetwork->list), &(queue->queue));
++
++		}
++	} else {
++		/* we have an entry and we are going to update it. But this entry may
++		 * be already expired. In this case we do the same as we found a new
++		 * net and call the new_net handler
++		 */
++		#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT
++		systime last_scanned = pnetwork->last_scanned;
++		#endif
++		struct beacon_keys bcn_keys;
++		bool bcn_keys_valid = 0;
++		bool is_hidden_ssid_ap = 0;
++
++		pnetwork->last_scanned = rtw_get_current_time();
++
++		if (target->Reserved[0] == BSS_TYPE_BCN || target->Reserved[0] == BSS_TYPE_PROB_RSP) {
++			if (target->InfrastructureMode == Ndis802_11Infrastructure) {
++				is_hidden_ssid_ap = hidden_ssid_ap(target);
++				if (!is_hidden_ssid_ap) /* update last time it's non hidden ssid AP */
++					pnetwork->last_non_hidden_ssid_ap = rtw_get_current_time();
++			}
++			bcn_keys_valid = rtw_get_bcn_keys_from_bss(target, &bcn_keys);
++		}
++
++		if (target->InfrastructureMode == Ndis802_11_mesh
++			|| target->Reserved[0] >= pnetwork->network.Reserved[0])
++			update_ie = _TRUE;
++		else if (target->InfrastructureMode == Ndis802_11Infrastructure && !pnetwork->fixed
++			&& rtw_get_passing_time_ms(pnetwork->last_non_hidden_ssid_ap) > SCANQUEUE_LIFETIME)
++			update_ie = _TRUE;
++		else if (bcn_keys_valid) {
++			if (is_hidden_ssid(bcn_keys.ssid, bcn_keys.ssid_len)) {
++				/* hidden ssid, replace with current beacon ssid directly */
++				_rtw_memcpy(bcn_keys.ssid, pnetwork->bcn_keys.ssid, pnetwork->bcn_keys.ssid_len);
++				bcn_keys.ssid_len = pnetwork->bcn_keys.ssid_len;
++			}
++			if (rtw_bcn_key_compare(&pnetwork->bcn_keys, &bcn_keys) == _FALSE)
++				update_ie = _TRUE;
++		}
++
++		#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT
++		if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter)
++			|| pnetwork->network.Configuration.DSConfig != target->Configuration.DSConfig
++			|| rtw_get_passing_time_ms(last_scanned) > adapter->mesh_cfg.peer_sel_policy.scanr_exp_ms
++			|| !rtw_bss_is_same_mbss(&pnetwork->network, target)
++		) {
++			pnetwork->acnode_stime = 0;
++			pnetwork->acnode_notify_etime = 0;
++		}
++		#endif
++
++		if (bcn_keys_valid) {
++			_rtw_memcpy(&pnetwork->bcn_keys, &bcn_keys, sizeof(bcn_keys));
++			pnetwork->bcn_keys_valid = 1;
++		} else if (update_ie)
++			pnetwork->bcn_keys_valid = 0;
++
++		update_network(&(pnetwork->network), target, adapter, update_ie);
++	}
++
++	#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT
++	if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter))
++		rtw_mesh_update_scanned_acnode_status(adapter, pnetwork);
++	#endif
++
++unlock_scan_queue:
++	_exit_critical_bh(&queue->lock, &irqL);
++
++#ifdef CONFIG_RTW_MESH
++	if (pnetwork && MLME_IS_MESH(adapter)
++		&& check_fwstate(pmlmepriv, WIFI_ASOC_STATE)
++		&& !check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)
++	)
++		rtw_chk_candidate_peer_notify(adapter, pnetwork);
++#endif
++
++	return update_ie;
++}
++
++void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork);
++void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork)
++{
++	bool update_ie;
++	/* _queue	*queue	= &(pmlmepriv->scanned_queue); */
++
++	/* _enter_critical_bh(&queue->lock, &irqL); */
++
++#if defined(CONFIG_P2P) && defined(CONFIG_P2P_REMOVE_GROUP_INFO)
++	if (adapter->registrypriv.wifi_spec == 0)
++		rtw_bss_ex_del_p2p_attr(pnetwork, P2P_ATTR_GROUP_INFO);
++#endif
++
++	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
++		rtw_bss_ex_del_wfd_ie(pnetwork);
++
++	/* Wi-Fi driver will update the current network if the scan result of the connected AP be updated by scan. */
++	update_ie = rtw_update_scanned_network(adapter, pnetwork);
++
++	if (update_ie)
++		update_current_network(adapter, pnetwork);
++
++	/* _exit_critical_bh(&queue->lock, &irqL); */
++
++}
++
++/* select the desired network based on the capability of the (i)bss.
++ * check items: (1) security
++ *			   (2) network_type
++ *			   (3) WMM
++ *			   (4) HT
++ * (5) others */
++int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork);
++int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork)
++{
++	struct security_priv *psecuritypriv = &adapter->securitypriv;
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	u32 desired_encmode;
++	u32 privacy;
++
++	/* u8 wps_ie[512]; */
++	uint wps_ielen;
++
++	int bselected = _TRUE;
++
++	desired_encmode = psecuritypriv->ndisencryptstatus;
++	privacy = pnetwork->network.Privacy;
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
++		if (rtw_get_wps_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_, pnetwork->network.IELength - _FIXED_IE_LENGTH_, NULL, &wps_ielen) != NULL)
++			return _TRUE;
++		else
++			return _FALSE;
++	}
++	if (adapter->registrypriv.wifi_spec == 1) { /* for  correct flow of 8021X  to do.... */
++		u8 *p = NULL;
++		uint ie_len = 0;
++
++		if ((desired_encmode == Ndis802_11EncryptionDisabled) && (privacy != 0))
++			bselected = _FALSE;
++
++		if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) {
++			p = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_));
++			if (p && ie_len > 0)
++				bselected = _TRUE;
++			else
++				bselected = _FALSE;
++		}
++	}
++
++
++	if ((desired_encmode != Ndis802_11EncryptionDisabled) && (privacy == 0)) {
++		RTW_INFO("desired_encmode: %d, privacy: %d\n", desired_encmode, privacy);
++		bselected = _FALSE;
++	}
++
++	if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {
++		if (pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode)
++			bselected = _FALSE;
++	}
++
++#ifdef CONFIG_RTW_MBO
++	if (rtw_mbo_disallowed_network(pnetwork) == _TRUE)
++		bselected = _FALSE;
++#endif
++
++	return bselected;
++}
++
++#ifdef CONFIG_80211D
++static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	struct registry_priv *pregistrypriv;
++	struct mlme_ext_priv *pmlmeext;
++	RT_CHANNEL_INFO *chplan_new;
++	u8 channel;
++	u8 i;
++
++
++	pregistrypriv = &padapter->registrypriv;
++	pmlmeext = &padapter->mlmeextpriv;
++
++	/* Adjust channel plan by AP Country IE */
++	if (pregistrypriv->enable80211d
++	    && (!pmlmeext->update_channel_plan_by_ap_done)) {
++		u8 *ie, *p;
++		u32 len;
++		RT_CHANNEL_PLAN chplan_ap;
++		RT_CHANNEL_INFO *chplan_sta = NULL;
++		u8 country[4];
++		u8 fcn; /* first channel number */
++		u8 noc; /* number of channel */
++		u8 j, k;
++
++		ie = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _COUNTRY_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_);
++		if (!ie)
++			return;
++		if (len < 6)
++			return;
++
++		ie += 2;
++		p = ie;
++		ie += len;
++
++		_rtw_memset(country, 0, 4);
++		_rtw_memcpy(country, p, 3);
++		p += 3;
++		RTW_INFO("%s: 802.11d country=%s\n", __FUNCTION__, country);
++
++		i = 0;
++		while ((ie - p) >= 3) {
++			fcn = *(p++);
++			noc = *(p++);
++			p++;
++
++			for (j = 0; j < noc; j++) {
++				if (fcn <= 14)
++					channel = fcn + j; /* 2.4 GHz */
++				else
++					channel = fcn + j * 4; /* 5 GHz */
++
++				chplan_ap.Channel[i++] = channel;
++			}
++		}
++		chplan_ap.Len = i;
++
++#ifdef CONFIG_RTW_DEBUG
++		i = 0;
++		RTW_INFO("%s: AP[%s] channel plan {", __FUNCTION__, bssid->Ssid.Ssid);
++		while ((i < chplan_ap.Len) && (chplan_ap.Channel[i] != 0)) {
++			_RTW_INFO("%02d,", chplan_ap.Channel[i]);
++			i++;
++		}
++		_RTW_INFO("}\n");
++#endif
++
++		chplan_sta = rtw_malloc(sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
++		if (!chplan_sta)
++			goto done_update_chplan_from_ap;
++
++		_rtw_memcpy(chplan_sta, rfctl->channel_set, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
++#ifdef CONFIG_RTW_DEBUG
++		i = 0;
++		RTW_INFO("%s: STA channel plan {", __FUNCTION__);
++		while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) {
++			_RTW_INFO("%02d(%c),", chplan_sta[i].ChannelNum, chplan_sta[i].ScanType == SCAN_PASSIVE ? 'p' : 'a');
++			i++;
++		}
++		_RTW_INFO("}\n");
++#endif
++
++		_rtw_memset(rfctl->channel_set, 0, sizeof(rfctl->channel_set));
++		chplan_new = rfctl->channel_set;
++
++		i = j = k = 0;
++		if (pregistrypriv->wireless_mode & WIRELESS_11G) {
++			do {
++				if ((i == MAX_CHANNEL_NUM)
++				    || (chplan_sta[i].ChannelNum == 0)
++				    || (chplan_sta[i].ChannelNum > 14))
++					break;
++
++				if ((j == chplan_ap.Len) || (chplan_ap.Channel[j] > 14))
++					break;
++
++				if (chplan_sta[i].ChannelNum == chplan_ap.Channel[j]) {
++					chplan_new[k].ChannelNum = chplan_ap.Channel[j];
++					chplan_new[k].ScanType = SCAN_ACTIVE;
++					i++;
++					j++;
++					k++;
++				} else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j]) {
++					chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
++#if 0
++					chplan_new[k].ScanType = chplan_sta[i].ScanType;
++#else
++					chplan_new[k].ScanType = SCAN_PASSIVE;
++#endif
++					i++;
++					k++;
++				} else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j]) {
++					chplan_new[k].ChannelNum = chplan_ap.Channel[j];
++					chplan_new[k].ScanType = SCAN_ACTIVE;
++					j++;
++					k++;
++				}
++			} while (1);
++
++			/* change AP not support channel to Passive scan */
++			while ((i < MAX_CHANNEL_NUM)
++			       && (chplan_sta[i].ChannelNum != 0)
++			       && (chplan_sta[i].ChannelNum <= 14)) {
++				chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
++#if 0
++				chplan_new[k].ScanType = chplan_sta[i].ScanType;
++#else
++				chplan_new[k].ScanType = SCAN_PASSIVE;
++#endif
++				i++;
++				k++;
++			}
++
++			/* add channel AP supported */
++			while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14)) {
++				chplan_new[k].ChannelNum = chplan_ap.Channel[j];
++				chplan_new[k].ScanType = SCAN_ACTIVE;
++				j++;
++				k++;
++			}
++		} else {
++			/* keep original STA 2.4G channel plan */
++			while ((i < MAX_CHANNEL_NUM)
++			       && (chplan_sta[i].ChannelNum != 0)
++			       && (chplan_sta[i].ChannelNum <= 14)) {
++				chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
++				chplan_new[k].ScanType = chplan_sta[i].ScanType;
++				i++;
++				k++;
++			}
++
++			/* skip AP 2.4G channel plan */
++			while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14))
++				j++;
++		}
++
++		if (pregistrypriv->wireless_mode & WIRELESS_11A) {
++			do {
++				if ((i >= MAX_CHANNEL_NUM)
++				    || (chplan_sta[i].ChannelNum == 0))
++					break;
++
++				if ((j == chplan_ap.Len) || (chplan_ap.Channel[j] == 0))
++					break;
++
++				if (chplan_sta[i].ChannelNum == chplan_ap.Channel[j]) {
++					chplan_new[k].ChannelNum = chplan_ap.Channel[j];
++					chplan_new[k].ScanType = SCAN_ACTIVE;
++					i++;
++					j++;
++					k++;
++				} else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j]) {
++					chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
++#if 0
++					chplan_new[k].ScanType = chplan_sta[i].ScanType;
++#else
++					chplan_new[k].ScanType = SCAN_PASSIVE;
++#endif
++					i++;
++					k++;
++				} else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j]) {
++					chplan_new[k].ChannelNum = chplan_ap.Channel[j];
++					chplan_new[k].ScanType = SCAN_ACTIVE;
++					j++;
++					k++;
++				}
++			} while (1);
++
++			/* change AP not support channel to Passive scan */
++			while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) {
++				chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
++#if 0
++				chplan_new[k].ScanType = chplan_sta[i].ScanType;
++#else
++				chplan_new[k].ScanType = SCAN_PASSIVE;
++#endif
++				i++;
++				k++;
++			}
++
++			/* add channel AP supported */
++			while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] != 0)) {
++				chplan_new[k].ChannelNum = chplan_ap.Channel[j];
++				chplan_new[k].ScanType = SCAN_ACTIVE;
++				j++;
++				k++;
++			}
++		} else {
++			/* keep original STA 5G channel plan */
++			while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) {
++				chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
++				chplan_new[k].ScanType = chplan_sta[i].ScanType;
++				i++;
++				k++;
++			}
++		}
++
++		pmlmeext->update_channel_plan_by_ap_done = 1;
++
++#ifdef CONFIG_RTW_DEBUG
++		k = 0;
++		RTW_INFO("%s: new STA channel plan {", __FUNCTION__);
++		while ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0)) {
++			_RTW_INFO("%02d(%c),", chplan_new[k].ChannelNum, chplan_new[k].ScanType == SCAN_PASSIVE ? 'p' : 'c');
++			k++;
++		}
++		_RTW_INFO("}\n");
++#endif
++
++#if 0
++		/* recover the right channel index */
++		channel = chplan_sta[pmlmeext->sitesurvey_res.channel_idx].ChannelNum;
++		k = 0;
++		while ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0)) {
++			if (chplan_new[k].ChannelNum == channel) {
++				RTW_INFO("%s: change mlme_ext sitesurvey channel index from %d to %d\n",
++					__FUNCTION__, pmlmeext->sitesurvey_res.channel_idx, k);
++				pmlmeext->sitesurvey_res.channel_idx = k;
++				break;
++			}
++			k++;
++		}
++#endif
++
++done_update_chplan_from_ap:
++		if (chplan_sta)
++			rtw_mfree(chplan_sta, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
++	}
++}
++#endif
++
++void rtw_survey_event_callback(_adapter	*adapter, u8 *pbuf)
++{
++	_irqL  irqL;
++	u32 len;
++	u8 val8;
++	WLAN_BSSID_EX *pnetwork;
++	struct	mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
++
++	pnetwork = (WLAN_BSSID_EX *)pbuf;
++
++	len = get_WLAN_BSSID_EX_sz(pnetwork);
++	if (len > (sizeof(WLAN_BSSID_EX))) {
++		return;
++	}
++
++#ifdef CONFIG_RTW_80211K
++    	val8 = 0;
++	rtw_hal_get_hwreg(adapter, HW_VAR_FREECNT, &val8);
++
++	/* use TSF if no free run counter */
++	if (val8==0)
++		pnetwork->PhyInfo.free_cnt = (u32)rtw_hal_get_tsftr_by_port(
++			adapter, rtw_hal_get_port(adapter));
++#endif
++
++	if (pnetwork->InfrastructureMode == Ndis802_11Infrastructure) {
++		#ifdef CONFIG_80211D
++		process_80211d(adapter, pnetwork);
++		#endif
++		rtw_process_beacon_hint(adapter, pnetwork);
++	}
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++	/* update IBSS_network 's timestamp */
++	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) {
++		if (_rtw_memcmp(&(pmlmepriv->cur_network.network.MacAddress), pnetwork->MacAddress, ETH_ALEN)) {
++			struct wlan_network *ibss_wlan = NULL;
++			_irqL	irqL;
++
++			_rtw_memcpy(pmlmepriv->cur_network.network.IEs, pnetwork->IEs, 8);
++			_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++			ibss_wlan = _rtw_find_network(&pmlmepriv->scanned_queue,  pnetwork->MacAddress);
++			if (ibss_wlan) {
++				_rtw_memcpy(ibss_wlan->network.IEs , pnetwork->IEs, 8);
++				_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++				goto exit;
++			}
++			_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++		}
++	}
++
++	/* lock pmlmepriv->lock when you accessing network_q */
++	if ((check_fwstate(pmlmepriv, WIFI_UNDER_LINKING)) == _FALSE) {
++		if (pnetwork->Ssid.Ssid[0] == 0)
++			pnetwork->Ssid.SsidLength = 0;
++		rtw_add_network(adapter, pnetwork);
++	}
++
++exit:
++
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++
++	return;
++}
++
++void rtw_surveydone_event_callback(_adapter	*adapter, u8 *pbuf)
++{
++	_irqL  irqL;
++	struct surveydone_event *parm = (struct surveydone_event *)pbuf;
++	struct	mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
++#ifdef CONFIG_RTW_80211R
++	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
++#endif
++
++#ifdef CONFIG_MLME_EXT
++	mlmeext_surveydone_event_callback(adapter);
++#endif
++
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++	if (pmlmepriv->wps_probe_req_ie) {
++		u32 free_len = pmlmepriv->wps_probe_req_ie_len;
++		pmlmepriv->wps_probe_req_ie_len = 0;
++		rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len);
++		pmlmepriv->wps_probe_req_ie = NULL;
++	}
++
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _FALSE) {
++		RTW_INFO(FUNC_ADPT_FMT" fw_state:0x%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv));
++		/* rtw_warn_on(1); */
++	}
++
++	_clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY);
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++	_cancel_timer_ex(&pmlmepriv->scan_to_timer);
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++	rtw_set_signal_stat_timer(&adapter->recvpriv);
++#endif
++
++	if (pmlmepriv->to_join == _TRUE) {
++		if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) {
++			if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) {
++				set_fwstate(pmlmepriv, WIFI_UNDER_LINKING);
++
++				if (rtw_select_and_join_from_scanned_queue(pmlmepriv) == _SUCCESS)
++					_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
++				else {
++					WLAN_BSSID_EX    *pdev_network = &(adapter->registrypriv.dev_network);
++					u8 *pibss = adapter->registrypriv.dev_network.MacAddress;
++
++					/* pmlmepriv->fw_state ^= WIFI_UNDER_SURVEY; */ /* because don't set assoc_timer */
++					_clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY);
++
++
++					_rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID));
++					_rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
++
++					rtw_update_registrypriv_dev_network(adapter);
++					rtw_generate_random_ibss(pibss);
++
++					/*pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;*/
++					init_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
++
++					if (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS)
++						RTW_ERR("rtw_create_ibss_cmd FAIL\n");
++
++					pmlmepriv->to_join = _FALSE;
++				}
++			}
++		} else {
++			int s_ret;
++			set_fwstate(pmlmepriv, WIFI_UNDER_LINKING);
++			pmlmepriv->to_join = _FALSE;
++			s_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv);
++			if (_SUCCESS == s_ret)
++				_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
++			else if (s_ret == 2) { /* there is no need to wait for join */
++				_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
++				rtw_indicate_connect(adapter);
++			} else {
++				RTW_INFO("try_to_join, but select scanning queue fail, to_roam:%d\n", rtw_to_roam(adapter));
++
++				if (rtw_to_roam(adapter) != 0) {
++					struct sitesurvey_parm scan_parm;
++					u8 ssc_chk = rtw_sitesurvey_condition_check(adapter, _FALSE);
++
++					rtw_init_sitesurvey_parm(adapter, &scan_parm);
++					_rtw_memcpy(&scan_parm.ssid[0], &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
++					scan_parm.ssid_num = 1;
++
++					if (rtw_dec_to_roam(adapter) == 0
++						|| (ssc_chk != SS_ALLOW && ssc_chk != SS_DENY_BUSY_TRAFFIC)
++						|| _SUCCESS != rtw_sitesurvey_cmd(adapter, &scan_parm)
++					   ) {
++						rtw_set_to_roam(adapter, 0);
++						rtw_free_assoc_resources(adapter, _TRUE);
++						rtw_indicate_disconnect(adapter, 0, _FALSE);
++					} else
++						pmlmepriv->to_join = _TRUE;
++				} else
++					rtw_indicate_disconnect(adapter, 0, _FALSE);
++				_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
++			}
++		}
++	} else {
++		if (rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)
++		#if (defined(CONFIG_RTW_WNM) && defined(CONFIG_RTW_80211R))
++			|| rtw_wnm_btm_roam_triggered(adapter)
++		#endif
++		) {
++			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
++			    && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
++				if (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) {
++			#ifdef CONFIG_RTW_80211R
++					rtw_ft_start_roam(adapter,
++						(u8 *)pmlmepriv->roam_network->network.MacAddress);
++			#else
++					receive_disconnect(adapter, pmlmepriv->cur_network.network.MacAddress
++						, WLAN_REASON_ACTIVE_ROAM, _FALSE);
++			#endif
++				}
++			}
++		}
++	}
++
++	/* RTW_INFO("scan complete in %dms\n",rtw_get_passing_time_ms(pmlmepriv->scan_start_time)); */
++
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++#ifdef CONFIG_P2P_PS
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++		p2p_ps_wk_cmd(adapter, P2P_PS_SCAN_DONE, 0);
++#endif /* CONFIG_P2P_PS */
++
++	rtw_mi_os_xmit_schedule(adapter);
++
++#ifdef CONFIG_DRVEXT_MODULE_WSC
++	drvext_surveydone_callback(&adapter->drvextpriv);
++#endif
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++	{
++		struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++		if (pmlmeext->sitesurvey_res.bss_cnt == 0) {
++			/* rtw_hal_sreset_reset(adapter); */
++		}
++	}
++#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++	rtw_cfg80211_surveydone_event_callback(adapter);
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++	rtw_indicate_scan_done(adapter, _FALSE);
++
++#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_IOCTL_CFG80211)
++	rtw_cfg80211_indicate_scan_done_for_buddy(adapter, _FALSE);
++#endif
++
++#ifdef CONFIG_RTW_MESH
++	#if CONFIG_RTW_MESH_OFFCH_CAND
++	if (rtw_mesh_offch_candidate_accepted(adapter)) {
++		u8 ch;
++
++		ch = rtw_mesh_select_operating_ch(adapter);
++		if (ch && pmlmepriv->cur_network.network.Configuration.DSConfig != ch) {
++			u8 ifbmp = rtw_mi_get_ap_mesh_ifbmp(adapter);
++
++			if (ifbmp) {
++				/* switch to selected channel */
++				rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_DIRECTLY, ifbmp, 0, ch, REQ_BW_ORI, REQ_OFFSET_NONE);
++				issue_probereq_ex(adapter, &pmlmepriv->cur_network.network.mesh_id, NULL, 0, 0, 0, 0);
++			} else
++				rtw_warn_on(1);
++		}
++	}
++	#endif
++#endif /* CONFIG_RTW_MESH */
++
++#ifdef CONFIG_RTW_ACS
++	if (parm->acs) {
++		u8 ifbmp = rtw_mi_get_ap_mesh_ifbmp(adapter);
++
++		if (ifbmp)
++			rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_DIRECTLY, ifbmp, 0, REQ_CH_INT_INFO, REQ_BW_ORI, REQ_OFFSET_NONE);
++	}
++#endif
++}
++
++u8 _rtw_sitesurvey_condition_check(const char *caller, _adapter *adapter, bool check_sc_interval)
++{
++	u8 ss_condition = SS_ALLOW;
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	struct registry_priv *registry_par = &adapter->registrypriv;
++
++
++#ifdef CONFIG_MP_INCLUDED
++	if (rtw_mp_mode_check(adapter)) {
++		RTW_INFO("%s ("ADPT_FMT") MP mode block Scan request\n", caller, ADPT_ARG(adapter));
++		ss_condition = SS_DENY_MP_MODE;
++		goto _exit;
++	}
++#endif
++
++#ifdef DBG_LA_MODE
++	if(registry_par->la_mode_en == 1 && MLME_IS_ASOC(adapter)) {
++		RTW_INFO("%s ("ADPT_FMT") LA debug mode block Scan request\n", caller, ADPT_ARG(adapter));
++		ss_condition = SS_DENY_LA_MODE;
++		goto _exit;
++	}
++#endif
++
++#ifdef CONFIG_RTW_REPEATER_SON
++	if (adapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) {
++		RTW_INFO("%s ("ADPT_FMT") blocking scan for under rson scanning process\n", caller, ADPT_ARG(adapter));
++		ss_condition = SS_DENY_RSON_SCANING;
++		goto _exit;
++	}
++#endif
++#ifdef CONFIG_IOCTL_CFG80211
++	if (adapter_wdev_data(adapter)->block_scan == _TRUE) {
++		RTW_INFO("%s ("ADPT_FMT") wdev_priv.block_scan is set\n", caller, ADPT_ARG(adapter));
++		ss_condition = SS_DENY_BLOCK_SCAN;
++		goto _exit;
++	}
++#endif
++
++	if (adapter_to_dvobj(adapter)->scan_deny == _TRUE) {
++		RTW_INFO("%s ("ADPT_FMT") tpt mode, scan deny!\n", caller, ADPT_ARG(adapter));
++		ss_condition = SS_DENY_BLOCK_SCAN;
++		goto _exit;
++	}
++
++	if (rtw_is_scan_deny(adapter)) {
++		RTW_INFO("%s ("ADPT_FMT") : scan deny\n", caller, ADPT_ARG(adapter));
++		ss_condition = SS_DENY_BY_DRV;
++		goto _exit;
++	}
++
++#ifdef CONFIG_ADAPTIVITY_DENY_SCAN
++	if (registry_par->adaptivity_en
++	    && rtw_phydm_get_edcca_flag(adapter)
++	    && rtw_is_2g_ch(GET_HAL_DATA(adapter)->current_channel)) {
++		RTW_WARN(FUNC_ADPT_FMT": Adaptivity block scan! (ch=%u)\n",
++			 FUNC_ADPT_ARG(adapter),
++			 GET_HAL_DATA(adapter)->current_channel);
++		ss_condition = SS_DENY_ADAPTIVITY;
++		goto _exit;
++	}
++#endif /* CONFIG_ADAPTIVITY_DENY_SCAN */
++
++	if (check_fwstate(pmlmepriv, WIFI_AP_STATE)){
++		if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
++			RTW_INFO("%s ("ADPT_FMT") : scan abort!! AP mode process WPS\n", caller, ADPT_ARG(adapter));
++			ss_condition = SS_DENY_SELF_AP_UNDER_WPS;
++			goto _exit;
++		} else if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) {
++			RTW_INFO("%s ("ADPT_FMT") : scan abort!!AP mode under linking (fwstate=0x%x)\n",
++				caller, ADPT_ARG(adapter), pmlmepriv->fw_state);
++			ss_condition = SS_DENY_SELF_AP_UNDER_LINKING;
++			goto _exit;
++		} else if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE) {
++			RTW_INFO("%s ("ADPT_FMT") : scan abort!!AP mode under survey (fwstate=0x%x)\n",
++				caller, ADPT_ARG(adapter), pmlmepriv->fw_state);
++			ss_condition = SS_DENY_SELF_AP_UNDER_SURVEY;
++			goto _exit;
++		}
++	} else {
++		if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) {
++			RTW_INFO("%s ("ADPT_FMT") : scan abort!!STA mode under linking (fwstate=0x%x)\n",
++				caller, ADPT_ARG(adapter), pmlmepriv->fw_state);
++			ss_condition = SS_DENY_SELF_STA_UNDER_LINKING;
++			goto _exit;
++		} else if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE) {
++			RTW_INFO("%s ("ADPT_FMT") : scan abort!!STA mode under survey (fwstate=0x%x)\n",
++				caller, ADPT_ARG(adapter), pmlmepriv->fw_state);
++			ss_condition = SS_DENY_SELF_STA_UNDER_SURVEY;
++			goto _exit;
++		}
++	}
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_buddy_check_fwstate(adapter, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)) {
++		RTW_INFO("%s ("ADPT_FMT") : scan abort!! buddy_intf under linking or wps\n", caller, ADPT_ARG(adapter));
++		ss_condition = SS_DENY_BUDDY_UNDER_LINK_WPS;
++		goto _exit;
++
++	} else if (rtw_mi_buddy_check_fwstate(adapter, WIFI_UNDER_SURVEY)) {
++		RTW_INFO("%s ("ADPT_FMT") : scan abort!! buddy_intf under survey\n", caller, ADPT_ARG(adapter));
++		ss_condition = SS_DENY_BUDDY_UNDER_SURVEY;
++		goto _exit;
++	}
++#endif /* CONFIG_CONCURRENT_MODE */
++
++#ifdef RTW_BUSY_DENY_SCAN
++	/*
++	 * busy traffic check
++	 * Rules:
++	 * 1. If (scan interval <= BUSY_TRAFFIC_SCAN_DENY_PERIOD) always allow
++	 *    scan, otherwise goto rule 2.
++	 * 2. Deny scan if any interface is busy, otherwise allow scan.
++	 */
++	if (pmlmepriv->lastscantime
++	    && (rtw_get_passing_time_ms(pmlmepriv->lastscantime) >
++		registry_par->scan_interval_thr)
++	    && rtw_mi_busy_traffic_check(adapter)) {
++		RTW_WARN("%s ("ADPT_FMT") : scan abort!! BusyTraffic\n",
++			 caller, ADPT_ARG(adapter));
++		ss_condition = SS_DENY_BUSY_TRAFFIC;
++		goto _exit;
++	}
++#endif /* RTW_BUSY_DENY_SCAN */
++
++_exit:
++	return ss_condition;
++}
++
++static void free_scanqueue(struct	mlme_priv *pmlmepriv)
++{
++	_irqL irqL, irqL0;
++	_queue *free_queue = &pmlmepriv->free_bss_pool;
++	_queue *scan_queue = &pmlmepriv->scanned_queue;
++	_list	*plist, *phead, *ptemp;
++
++
++	_enter_critical_bh(&scan_queue->lock, &irqL0);
++	_enter_critical_bh(&free_queue->lock, &irqL);
++
++	phead = get_list_head(scan_queue);
++	plist = get_next(phead);
++
++	while (plist != phead) {
++		ptemp = get_next(plist);
++		rtw_list_delete(plist);
++		rtw_list_insert_tail(plist, &free_queue->queue);
++		plist = ptemp;
++		pmlmepriv->num_of_scanned--;
++	}
++
++	_exit_critical_bh(&free_queue->lock, &irqL);
++	_exit_critical_bh(&scan_queue->lock, &irqL0);
++
++}
++
++void rtw_reset_rx_info(_adapter *adapter)
++{
++	struct recv_priv  *precvpriv = &adapter->recvpriv;
++
++	precvpriv->dbg_rx_ampdu_drop_count = 0;
++	precvpriv->dbg_rx_ampdu_forced_indicate_count = 0;
++	precvpriv->dbg_rx_ampdu_loss_count = 0;
++	precvpriv->dbg_rx_dup_mgt_frame_drop_count = 0;
++	precvpriv->dbg_rx_ampdu_window_shift_cnt = 0;
++	precvpriv->dbg_rx_drop_count = 0;
++	precvpriv->dbg_rx_conflic_mac_addr_cnt = 0;
++}
++
++/*
++*rtw_free_assoc_resources: the caller has to lock pmlmepriv->lock
++*/
++void rtw_free_assoc_resources(_adapter *adapter, u8 lock_scanned_queue)
++{
++	_irqL irqL;
++	struct wlan_network *pwlan = NULL;
++	struct	mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	struct wlan_network *tgt_network = &pmlmepriv->cur_network;
++
++
++#ifdef CONFIG_TDLS
++	struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
++#endif /* CONFIG_TDLS */
++
++
++	RTW_INFO("%s-"ADPT_FMT" tgt_network MacAddress=" MAC_FMT" ssid=%s\n",
++		__func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress), tgt_network->network.Ssid.Ssid);
++
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
++		struct sta_info *psta;
++
++		psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress);
++
++#ifdef CONFIG_TDLS
++		rtw_free_all_tdls_sta(adapter, _TRUE);
++		rtw_reset_tdls_info(adapter);
++
++		if (ptdlsinfo->link_established == _TRUE)
++			rtw_tdls_cmd(adapter, NULL, TDLS_RS_RCR);
++#endif /* CONFIG_TDLS */
++
++		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
++		rtw_free_stainfo(adapter, psta);
++		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
++
++	}
++
++	if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
++		struct sta_info *psta;
++
++		rtw_free_all_stainfo(adapter);
++
++		psta = rtw_get_bcmc_stainfo(adapter);
++		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
++		rtw_free_stainfo(adapter, psta);
++		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
++
++		rtw_init_bcmc_stainfo(adapter);
++	}
++
++	if (lock_scanned_queue)
++		_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS) || (pmlmepriv->wpa_phase == _TRUE)){
++		RTW_INFO("Dont free disconnecting network of scanned_queue due to uner %s %s phase\n\n",
++			check_fwstate(pmlmepriv, WIFI_UNDER_WPS) ? "WPS" : "",
++			(pmlmepriv->wpa_phase == _TRUE) ? "WPA" : "");
++	} else {
++		pwlan = _rtw_find_same_network(&pmlmepriv->scanned_queue, tgt_network);
++		if (pwlan) {
++			pwlan->fixed = _FALSE;
++
++			RTW_INFO("Free disconnecting network of scanned_queue\n");
++			rtw_free_network_nolock(adapter, pwlan);
++#ifdef CONFIG_P2P
++			if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) {
++				rtw_set_scan_deny(adapter, 2000);
++				/* rtw_clear_scan_deny(adapter); */
++			}
++#endif /* CONFIG_P2P */
++		} else
++			RTW_ERR("Free disconnecting network of scanned_queue failed due to pwlan == NULL\n\n");
++	}
++
++	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) && (adapter->stapriv.asoc_sta_count == 1))
++	    /*||check_fwstate(pmlmepriv, WIFI_STATION_STATE)*/) {
++		if (pwlan)
++			rtw_free_network_nolock(adapter, pwlan);
++	}
++
++	if (lock_scanned_queue)
++		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	adapter->securitypriv.key_mask = 0;
++
++	rtw_reset_rx_info(adapter);
++
++
++}
++
++/*
++*rtw_indicate_connect: the caller has to lock pmlmepriv->lock
++*/
++void rtw_indicate_connect(_adapter *padapter)
++{
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++
++	pmlmepriv->to_join = _FALSE;
++
++	if (!check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) {
++
++		set_fwstate(pmlmepriv, WIFI_ASOC_STATE);
++
++		rtw_led_control(padapter, LED_CTL_LINK);
++
++		rtw_os_indicate_connect(padapter);
++	}
++
++	rtw_set_to_roam(padapter, 0);
++	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
++		rtw_mi_set_scan_deny(padapter, 3000);
++
++
++}
++
++
++/*
++*rtw_indicate_disconnect: the caller has to lock pmlmepriv->lock
++*/
++void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated)
++{
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX	*cur_network = &(pmlmeinfo->network);
++#ifdef CONFIG_WAPI_SUPPORT
++	struct sta_info *psta;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++#endif
++	u8 *wps_ie = NULL;
++	uint wpsie_len = 0;
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS))
++		pmlmepriv->wpa_phase = _TRUE;
++
++	_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS | WIFI_OP_CH_SWITCHING | WIFI_UNDER_KEY_HANDSHAKE);
++
++	/* force to clear cur_network_scanned's SELECTED REGISTRAR */
++	if (pmlmepriv->cur_network_scanned) {
++		WLAN_BSSID_EX	*current_joined_bss = &(pmlmepriv->cur_network_scanned->network);
++		if (current_joined_bss) {
++			wps_ie = rtw_get_wps_ie(current_joined_bss->IEs + _FIXED_IE_LENGTH_,
++				current_joined_bss->IELength - _FIXED_IE_LENGTH_, NULL, &wpsie_len);
++			if (wps_ie && wpsie_len > 0) {
++				u8 *attr = NULL;
++				u32 attr_len;
++				attr = rtw_get_wps_attr(wps_ie, wpsie_len, WPS_ATTR_SELECTED_REGISTRAR,
++							NULL, &attr_len);
++				if (attr)
++					*(attr + 4) = 0;
++			}
++		}
++	}
++	/* RTW_INFO("clear wps when %s\n", __func__); */
++
++	if (rtw_to_roam(padapter) > 0)
++		_clr_fwstate_(pmlmepriv, WIFI_ASOC_STATE);
++
++#ifdef CONFIG_WAPI_SUPPORT
++	psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
++		rtw_wapi_return_one_sta_info(padapter, psta->cmn.mac_addr);
++	else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) ||
++		 check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE))
++		rtw_wapi_return_all_sta_info(padapter);
++#endif
++
++	if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)
++	    || (rtw_to_roam(padapter) <= 0)
++	   ) {
++		#ifdef CONFIG_RTW_WDS
++		adapter_set_use_wds(padapter, 0);
++		#endif
++		#ifdef CONFIG_RTW_MULTI_AP
++		padapter->multi_ap = 0;
++		#endif
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++		if (ATOMIC_READ(&padapter->tbtx_tx_pause) == _TRUE) {
++			ATOMIC_SET(&padapter->tbtx_tx_pause, _FALSE);
++			rtw_tx_control_cmd(padapter);
++		}
++#endif
++
++		rtw_os_indicate_disconnect(padapter, reason, locally_generated);
++
++		/* set ips_deny_time to avoid enter IPS before LPS leave */
++		rtw_set_ips_deny(padapter, 3000);
++
++		_clr_fwstate_(pmlmepriv, WIFI_ASOC_STATE);
++
++		rtw_led_control(padapter, LED_CTL_NO_LINK);
++
++		rtw_clear_scan_deny(padapter);
++	}
++
++#ifdef CONFIG_P2P_PS
++	p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1);
++#endif /* CONFIG_P2P_PS */
++
++#ifdef CONFIG_LPS
++	rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_DISCONNECT, 0);
++#endif
++
++#ifdef CONFIG_BEAMFORMING
++	beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, cur_network->MacAddress, ETH_ALEN, 1);
++#endif /*CONFIG_BEAMFORMING*/
++
++}
++
++inline void rtw_indicate_scan_done(_adapter *padapter, bool aborted)
++{
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++	rtw_os_indicate_scan_done(padapter, aborted);
++
++#ifdef CONFIG_IPS
++	if (is_primary_adapter(padapter)
++	    && (_FALSE == adapter_to_pwrctl(padapter)->bInSuspend)
++	    && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE | WIFI_UNDER_LINKING) == _FALSE)) {
++		struct pwrctrl_priv *pwrpriv;
++
++		pwrpriv = adapter_to_pwrctl(padapter);
++		rtw_set_ips_deny(padapter, 0);
++#ifdef CONFIG_IPS_CHECK_IN_WD
++		_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 1);
++#else /* !CONFIG_IPS_CHECK_IN_WD */
++		_rtw_set_pwr_state_check_timer(pwrpriv, 1);
++#endif /* !CONFIG_IPS_CHECK_IN_WD */
++	}
++#endif /* CONFIG_IPS */
++}
++
++static u32 _rtw_wait_scan_done(_adapter *adapter, u8 abort, u32 timeout_ms)
++{
++	systime start;
++	u32 pass_ms;
++	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++
++	start = rtw_get_current_time();
++
++	pmlmeext->scan_abort = abort;
++
++	while (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)
++	       && rtw_get_passing_time_ms(start) <= timeout_ms) {
++
++		if (RTW_CANNOT_RUN(adapter))
++			break;
++
++		RTW_INFO(FUNC_NDEV_FMT"fw_state=WIFI_UNDER_SURVEY!\n", FUNC_NDEV_ARG(adapter->pnetdev));
++		rtw_msleep_os(20);
++	}
++
++	if (_TRUE == abort) {
++		if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)) {
++			if (!RTW_CANNOT_RUN(adapter))
++				RTW_INFO(FUNC_NDEV_FMT"waiting for scan_abort time out!\n", FUNC_NDEV_ARG(adapter->pnetdev));
++#ifdef CONFIG_PLATFORM_MSTAR
++			/*_clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY);*/
++			set_survey_timer(pmlmeext, 0);
++			mlme_set_scan_to_timer(pmlmepriv, 50);
++#endif
++			rtw_indicate_scan_done(adapter, _TRUE);
++		}
++	}
++
++	pmlmeext->scan_abort = _FALSE;
++	pass_ms = rtw_get_passing_time_ms(start);
++
++	return pass_ms;
++
++}
++
++void rtw_scan_wait_completed(_adapter *adapter)
++{
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++	struct ss_res *ss = &pmlmeext->sitesurvey_res;
++
++	_rtw_wait_scan_done(adapter, _FALSE, ss->scan_timeout_ms);
++}
++
++u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms)
++{
++	return _rtw_wait_scan_done(adapter, _TRUE, timeout_ms);
++}
++
++void rtw_scan_abort_no_wait(_adapter *adapter)
++{
++	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY))
++		pmlmeext->scan_abort = _TRUE;
++}
++
++void rtw_scan_abort(_adapter *adapter)
++{
++	rtw_scan_abort_timeout(adapter, 200);
++}
++
++static u32 _rtw_wait_join_done(_adapter *adapter, u8 abort, u32 timeout_ms)
++{
++	systime start;
++	u32 pass_ms;
++	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++
++	start = rtw_get_current_time();
++
++	pmlmeext->join_abort = abort;
++	if (abort)
++		set_link_timer(pmlmeext, 1);
++
++	while (rtw_get_passing_time_ms(start) <= timeout_ms
++		&& (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING)
++			#ifdef CONFIG_IOCTL_CFG80211
++			|| rtw_cfg80211_is_connect_requested(adapter)
++			#endif
++			)
++	) {
++		if (RTW_CANNOT_RUN(adapter))
++			break;
++
++		RTW_INFO(FUNC_ADPT_FMT" linking...\n", FUNC_ADPT_ARG(adapter));
++		rtw_msleep_os(20);
++	}
++
++	if (abort) {
++		if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING)
++			#ifdef CONFIG_IOCTL_CFG80211
++			|| rtw_cfg80211_is_connect_requested(adapter)
++			#endif
++		) {
++			if (!RTW_CANNOT_RUN(adapter))
++				RTW_INFO(FUNC_ADPT_FMT" waiting for join_abort time out!\n", FUNC_ADPT_ARG(adapter));
++		}
++	}
++
++	pmlmeext->join_abort = 0;
++	pass_ms = rtw_get_passing_time_ms(start);
++
++	return pass_ms;
++}
++
++u32 rtw_join_abort_timeout(_adapter *adapter, u32 timeout_ms)
++{
++	return _rtw_wait_join_done(adapter, _TRUE, timeout_ms);
++}
++
++static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wlan_network *pnetwork)
++{
++	int i;
++	struct sta_info *psta = NULL;
++	struct recv_reorder_ctrl *preorder_ctrl;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++#ifdef CONFIG_RTS_FULL_BW
++	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	struct wlan_network  *cur_network = &(pmlmepriv->cur_network);
++#endif/*CONFIG_RTS_FULL_BW*/
++
++	psta = rtw_get_stainfo(pstapriv, pnetwork->network.MacAddress);
++	if (psta == NULL)
++		psta = rtw_alloc_stainfo(pstapriv, pnetwork->network.MacAddress);
++
++	if (psta) { /* update ptarget_sta */
++		RTW_INFO("%s\n", __FUNCTION__);
++
++		psta->cmn.aid  = pnetwork->join_res;
++
++		update_sta_info(padapter, psta);
++
++		/* update station supportRate */
++		psta->bssratelen = rtw_get_rateset_len(pnetwork->network.SupportedRates);
++		_rtw_memcpy(psta->bssrateset, pnetwork->network.SupportedRates, psta->bssratelen);
++		rtw_hal_update_sta_ra_info(padapter, psta);
++
++		psta->wireless_mode = pmlmeext->cur_wireless_mode;
++		rtw_hal_update_sta_wset(padapter, psta);
++
++		/* sta mode */
++		rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);
++
++		/* security related */
++#ifdef CONFIG_RTW_80211R
++		if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
++			&& (psta->ft_pairwise_key_installed == _FALSE)) {
++#else
++		if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) {
++#endif
++			u8 *ie;
++			sint ie_len;
++			u8 mfp_opt = MFP_NO;
++
++			padapter->securitypriv.binstallGrpkey = _FALSE;
++			padapter->securitypriv.busetkipkey = _FALSE;
++			padapter->securitypriv.bgrpkey_handshake = _FALSE;
++
++			ie = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, WLAN_EID_RSN
++				, &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_));
++			if (ie && ie_len > 0
++				&& rtw_parse_wpa2_ie(ie, ie_len + 2, NULL, NULL, NULL, NULL, &mfp_opt) == _SUCCESS
++			) {
++				if (padapter->securitypriv.mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL)
++					psta->flags |= WLAN_STA_MFP;
++			}
++
++			psta->ieee8021x_blocked = _TRUE;
++			psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
++
++			_rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof(union Keytype));
++			_rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof(union Keytype));
++			_rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof(union Keytype));
++		}
++
++		/*	Commented by Albert 2012/07/21 */
++		/*	When doing the WPS, the wps_ie_len won't equal to 0 */
++		/*	And the Wi-Fi driver shouldn't allow the data packet to be tramsmitted. */
++		if (padapter->securitypriv.wps_ie_len != 0) {
++			psta->ieee8021x_blocked = _TRUE;
++			padapter->securitypriv.wps_ie_len = 0;
++		}
++
++
++		/* for A-MPDU Rx reordering buffer control for sta_info */
++		/* if A-MPDU Rx is enabled, reseting  rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff */
++		/* todo: check if AP can send A-MPDU packets */
++		for (i = 0; i < 16 ; i++) {
++			/* preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; */
++			preorder_ctrl = &psta->recvreorder_ctrl[i];
++			preorder_ctrl->enable = _FALSE;
++			preorder_ctrl->indicate_seq = 0xffff;
++			rtw_clear_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack);
++			#ifdef DBG_RX_SEQ
++			RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%u preorder_ctrl->rec_abba_rsp_ack:%lu\n"
++				, FUNC_ADPT_ARG(padapter)
++				, i
++				, preorder_ctrl->indicate_seq
++				,preorder_ctrl->rec_abba_rsp_ack
++				);
++			#endif
++			preorder_ctrl->wend_b = 0xffff;
++			preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */
++			preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID;
++		}
++	}
++
++#ifdef	CONFIG_RTW_80211K
++	_rtw_memcpy(&psta->rm_en_cap, pnetwork->network.PhyInfo.rm_en_cap, 5);
++#endif
++#ifdef CONFIG_RTW_MULTI_AP
++	if (padapter->multi_ap & MULTI_AP_BACKHAUL_STA) {
++		u8 multi_ap = rtw_get_multi_ap_ie_ext(pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6
++				, pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6);
++
++		if (multi_ap & MULTI_AP_BACKHAUL_BSS) /* backhaul bss, enable WDS */
++			psta->flags |= WLAN_STA_MULTI_AP | WLAN_STA_WDS;
++		else if (multi_ap & MULTI_AP_FRONTHAUL_BSS) /* fronthaul bss only */
++			psta->flags |= WLAN_STA_MULTI_AP;
++	}
++#endif
++#ifdef CONFIG_RTS_FULL_BW
++	rtw_parse_sta_vendor_ie_8812(padapter, psta, BSS_EX_TLV_IES(&cur_network->network), BSS_EX_TLV_IES_LEN(&cur_network->network));
++#endif
++	return psta;
++
++}
++
++/* pnetwork : returns from rtw_joinbss_event_callback
++ * ptarget_wlan: found from scanned_queue */
++static void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network *ptarget_wlan, struct wlan_network  *pnetwork)
++{
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	struct wlan_network  *cur_network = &(pmlmepriv->cur_network);
++	sint tmp_fw_state = 0x0;
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	/* why not use ptarget_wlan?? */
++	_rtw_memcpy(&cur_network->network, &pnetwork->network, pnetwork->network.Length);
++	/* some IEs in pnetwork is wrong, so we should use ptarget_wlan IEs */
++	cur_network->network.IELength = ptarget_wlan->network.IELength;
++	_rtw_memcpy(&cur_network->network.IEs[0], &ptarget_wlan->network.IEs[0], MAX_IE_SZ);
++
++	cur_network->aid = pnetwork->join_res;
++
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++	rtw_set_signal_stat_timer(&padapter->recvpriv);
++#endif
++	padapter->recvpriv.signal_strength = ptarget_wlan->network.PhyInfo.SignalStrength;
++	padapter->recvpriv.signal_qual = ptarget_wlan->network.PhyInfo.SignalQuality;
++	/* the ptarget_wlan->network.Rssi is raw data, we use ptarget_wlan->network.PhyInfo.SignalStrength instead (has scaled) */
++	padapter->recvpriv.rssi = translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength);
++#if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1
++	RTW_INFO(FUNC_ADPT_FMT" signal_strength:%3u, rssi:%3d, signal_qual:%3u"
++		 "\n"
++		 , FUNC_ADPT_ARG(padapter)
++		 , padapter->recvpriv.signal_strength
++		 , padapter->recvpriv.rssi
++		 , padapter->recvpriv.signal_qual
++		);
++#endif
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++	rtw_set_signal_stat_timer(&padapter->recvpriv);
++#endif
++
++	/* update fw_state */ /* will clr WIFI_UNDER_LINKING here indirectly */
++
++	switch (pnetwork->network.InfrastructureMode) {
++	case Ndis802_11Infrastructure:
++		/* Check encryption */
++		if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
++			tmp_fw_state = tmp_fw_state | WIFI_UNDER_KEY_HANDSHAKE;
++
++		if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS))
++			tmp_fw_state = tmp_fw_state | WIFI_UNDER_WPS;
++
++		init_fwstate(pmlmepriv, WIFI_STATION_STATE | tmp_fw_state);
++
++		break;
++	case Ndis802_11IBSS:
++		/*pmlmepriv->fw_state = WIFI_ADHOC_STATE;*/
++		init_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
++		break;
++	default:
++		/*pmlmepriv->fw_state = WIFI_NULL_STATE;*/
++		init_fwstate(pmlmepriv, WIFI_NULL_STATE);
++		break;
++	}
++
++	rtw_update_protection(padapter, (cur_network->network.IEs) + sizeof(NDIS_802_11_FIXED_IEs),
++			      (cur_network->network.IELength));
++
++#ifdef CONFIG_80211N_HT
++	rtw_update_ht_cap(padapter, cur_network->network.IEs, cur_network->network.IELength, (u8) cur_network->network.Configuration.DSConfig);
++#endif
++}
++
++/* Notes: the fucntion could be > passive_level (the same context as Rx tasklet)
++ * pnetwork : returns from rtw_joinbss_event_callback
++ * ptarget_wlan: found from scanned_queue
++ * if join_res > 0, for (fw_state==WIFI_STATION_STATE), we check if  "ptarget_sta" & "ptarget_wlan" exist.
++ * if join_res > 0, for (fw_state==WIFI_ADHOC_STATE), we only check if "ptarget_wlan" exist.
++ * if join_res > 0, update "cur_network->network" from "pnetwork->network" if (ptarget_wlan !=NULL).
++ */
++/* #define REJOIN */
++void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status)
++{
++	_irqL irqL;
++	static u8 retry = 0;
++	struct sta_info *ptarget_sta = NULL, *pcur_sta = NULL;
++	struct	sta_priv *pstapriv = &adapter->stapriv;
++	struct	mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
++	struct wlan_network	*pnetwork	= (struct wlan_network *)pbuf;
++	struct wlan_network	*cur_network = &(pmlmepriv->cur_network);
++	struct wlan_network	*pcur_wlan = NULL, *ptarget_wlan = NULL;
++	unsigned int		the_same_macaddr = _FALSE;
++
++	rtw_get_encrypt_decrypt_from_registrypriv(adapter);
++
++	the_same_macaddr = _rtw_memcmp(pnetwork->network.MacAddress, cur_network->network.MacAddress, ETH_ALEN);
++
++	pnetwork->network.Length = get_WLAN_BSSID_EX_sz(&pnetwork->network);
++	if (pnetwork->network.Length > sizeof(WLAN_BSSID_EX))
++		goto exit;
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++	pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0;
++	pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0;
++
++
++	if (pnetwork->join_res > 0) {
++		_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++		retry = 0;
++		if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING)) {
++			/* s1. find ptarget_wlan */
++			if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
++				if (the_same_macaddr == _TRUE)
++					ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
++				else {
++					pcur_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
++					if (pcur_wlan)
++						pcur_wlan->fixed = _FALSE;
++
++					pcur_sta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
++					if (pcur_sta) {
++						/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */
++						rtw_free_stainfo(adapter,  pcur_sta);
++						/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */
++					}
++
++					ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress);
++					if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
++						if (ptarget_wlan)
++							ptarget_wlan->fixed = _TRUE;
++					}
++				}
++
++			} else {
++				ptarget_wlan = _rtw_find_same_network(&pmlmepriv->scanned_queue, pnetwork);
++				if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
++					if (ptarget_wlan)
++						ptarget_wlan->fixed = _TRUE;
++				}
++			}
++
++			/* s2. update cur_network */
++			if (ptarget_wlan)
++				rtw_joinbss_update_network(adapter, ptarget_wlan, pnetwork);
++			else {
++				RTW_PRINT("Can't find ptarget_wlan when joinbss_event callback\n");
++				_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++				goto ignore_joinbss_callback;
++			}
++
++
++			/* s3. find ptarget_sta & update ptarget_sta after update cur_network only for station mode */
++			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
++				ptarget_sta = rtw_joinbss_update_stainfo(adapter, pnetwork);
++				if (ptarget_sta == NULL) {
++					RTW_ERR("Can't update stainfo when joinbss_event callback\n");
++					_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++					goto ignore_joinbss_callback;
++				}
++
++				/* Queue TX packets before FW/HW ready */
++				/* clear in mlmeext_joinbss_event_callback() */
++				rtw_xmit_queue_set(ptarget_sta);
++			}
++
++			/* s4. indicate connect			 */
++			if (MLME_IS_STA(adapter) || MLME_IS_ADHOC(adapter)) {
++				pmlmepriv->cur_network_scanned = ptarget_wlan;
++				rtw_indicate_connect(adapter);
++			}
++
++			/* s5. Cancle assoc_timer					 */
++			_cancel_timer_ex(&pmlmepriv->assoc_timer);
++
++
++		} else {
++			_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++			goto ignore_joinbss_callback;
++		}
++
++		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	} else if (pnetwork->join_res == -4) {
++		rtw_reset_securitypriv(adapter);
++		pmlmepriv->join_status = status;
++		_set_timer(&pmlmepriv->assoc_timer, 1);
++
++		/* rtw_free_assoc_resources(adapter, _TRUE); */
++
++		if ((check_fwstate(pmlmepriv, WIFI_UNDER_LINKING)) == _TRUE) {
++			_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
++		}
++
++	} else { /* if join_res < 0 (join fails), then try again */
++
++#ifdef REJOIN
++		res = _FAIL;
++		if (retry < 2) {
++			res = rtw_select_and_join_from_scanned_queue(pmlmepriv);
++		}
++
++		if (res == _SUCCESS) {
++			/* extend time of assoc_timer */
++			_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
++			retry++;
++		} else if (res == 2) { /* there is no need to wait for join */
++			_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
++			rtw_indicate_connect(adapter);
++		} else {
++#endif
++			pmlmepriv->join_status = status;
++			_set_timer(&pmlmepriv->assoc_timer, 1);
++			/* rtw_free_assoc_resources(adapter, _TRUE); */
++			_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
++
++#ifdef REJOIN
++			retry = 0;
++		}
++#endif
++	}
++
++ignore_joinbss_callback:
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++exit:
++	return;
++}
++
++void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf)
++{
++	struct wlan_network	*pnetwork	= (struct wlan_network *)pbuf;
++
++
++	mlmeext_joinbss_event_callback(adapter, pnetwork->join_res);
++
++	rtw_mi_os_xmit_schedule(adapter);
++
++}
++
++void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool connected)
++{
++	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
++	bool miracast_enabled = 0;
++	bool miracast_sink = 0;
++	u8 role = H2C_MSR_ROLE_RSVD;
++
++	if (sta == NULL) {
++		RTW_PRINT(FUNC_ADPT_FMT" sta is NULL\n"
++			  , FUNC_ADPT_ARG(adapter));
++		rtw_warn_on(1);
++		return;
++	}
++
++	if (sta->cmn.mac_id >= macid_ctl->num) {
++		RTW_PRINT(FUNC_ADPT_FMT" invalid macid:%u\n"
++			  , FUNC_ADPT_ARG(adapter), sta->cmn.mac_id);
++		rtw_warn_on(1);
++		return;
++	}
++
++	if (!rtw_macid_is_used(macid_ctl, sta->cmn.mac_id)) {
++		RTW_PRINT(FUNC_ADPT_FMT" macid:%u not is used, set connected to 0\n"
++			  , FUNC_ADPT_ARG(adapter), sta->cmn.mac_id);
++		connected = 0;
++		rtw_warn_on(1);
++	}
++
++	if (connected && !rtw_macid_is_bmc(macid_ctl, sta->cmn.mac_id)) {
++		miracast_enabled = STA_OP_WFD_MODE(sta) != 0 && is_miracast_enabled(adapter);
++		miracast_sink = miracast_enabled && (STA_OP_WFD_MODE(sta) & MIRACAST_SINK);
++
++#ifdef CONFIG_TDLS
++		if (sta->tdls_sta_state & TDLS_LINKED_STATE)
++			role = H2C_MSR_ROLE_TDLS;
++		else
++#endif
++		if (MLME_IS_STA(adapter)) {
++			if (MLME_IS_GC(adapter))
++				role = H2C_MSR_ROLE_GO;
++			else
++				role = H2C_MSR_ROLE_AP;
++		} else if (MLME_IS_AP(adapter)) {
++			if (MLME_IS_GO(adapter))
++				role = H2C_MSR_ROLE_GC;
++			else
++				role = H2C_MSR_ROLE_STA;
++		} else if (MLME_IS_ADHOC(adapter) || MLME_IS_ADHOC_MASTER(adapter))
++			role = H2C_MSR_ROLE_ADHOC;
++		else if (MLME_IS_MESH(adapter))
++			role = H2C_MSR_ROLE_MESH;
++
++#ifdef CONFIG_WFD
++		if (role == H2C_MSR_ROLE_GC
++			|| role == H2C_MSR_ROLE_GO
++			|| role == H2C_MSR_ROLE_TDLS
++		) {
++			if (adapter->wfd_info.rtsp_ctrlport
++				|| adapter->wfd_info.tdls_rtsp_ctrlport
++				|| adapter->wfd_info.peer_rtsp_ctrlport)
++				rtw_wfd_st_switch(sta, 1);
++		}
++#endif
++	}
++
++	rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter
++		, connected
++		, miracast_enabled
++		, miracast_sink
++		, role
++		, sta->cmn.mac_id
++	);
++}
++
++u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected)
++{
++	struct cmd_priv	*cmdpriv = &adapter->cmdpriv;
++	struct cmd_obj *cmdobj;
++	struct drvextra_cmd_parm *cmd_parm;
++	struct sta_media_status_rpt_cmd_parm *rpt_parm;
++	u8	res = _SUCCESS;
++
++	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (cmdobj == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (cmd_parm == NULL) {
++		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	rpt_parm = (struct sta_media_status_rpt_cmd_parm *)rtw_zmalloc(sizeof(struct sta_media_status_rpt_cmd_parm));
++	if (rpt_parm == NULL) {
++		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
++		rtw_mfree((u8 *)cmd_parm, sizeof(struct drvextra_cmd_parm));
++		res = _FAIL;
++		goto exit;
++	}
++
++	rpt_parm->sta = sta;
++	rpt_parm->connected = connected;
++
++	cmd_parm->ec_id = STA_MSTATUS_RPT_WK_CID;
++	cmd_parm->type = 0;
++	cmd_parm->size = sizeof(struct sta_media_status_rpt_cmd_parm);
++	cmd_parm->pbuf = (u8 *)rpt_parm;
++	init_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, CMD_SET_DRV_EXTRA);
++
++	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
++
++exit:
++	return res;
++}
++
++inline void rtw_sta_media_status_rpt_cmd_hdl(_adapter *adapter, struct sta_media_status_rpt_cmd_parm *parm)
++{
++	rtw_sta_media_status_rpt(adapter, parm->sta, parm->connected);
++}
++
++void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf)
++{
++	_irqL irqL;
++	struct sta_info *psta;
++	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++	struct stassoc_event	*pstassoc	= (struct stassoc_event *)pbuf;
++	struct wlan_network	*cur_network = &(pmlmepriv->cur_network);
++	struct wlan_network	*ptarget_wlan = NULL;
++
++
++#if CONFIG_RTW_MACADDR_ACL
++	if (rtw_access_ctrl(adapter, pstassoc->macaddr) == _FALSE)
++		return;
++#endif
++
++#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++	if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
++		psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr);
++		if (psta) {
++			u8 *passoc_req = NULL;
++			u32 assoc_req_len = 0;
++
++			rtw_sta_media_status_rpt(adapter, psta, 1);
++
++#ifdef CONFIG_MCC_MODE
++			rtw_hal_mcc_update_macid_bitmap(adapter, psta->cmn.mac_id, _TRUE);
++#endif /* CONFIG_MCC_MODE */
++
++#ifndef CONFIG_AUTO_AP_MODE
++			ap_sta_info_defer_update(adapter, psta);
++
++			if (!MLME_IS_MESH(adapter)) {
++				/* report to upper layer */
++				RTW_INFO("indicate_sta_assoc_event to upper layer - hostapd\n");
++				#ifdef CONFIG_IOCTL_CFG80211
++				_enter_critical_bh(&psta->lock, &irqL);
++				if (psta->passoc_req && psta->assoc_req_len > 0) {
++					passoc_req = rtw_zmalloc(psta->assoc_req_len);
++					if (passoc_req) {
++						assoc_req_len = psta->assoc_req_len;
++						_rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len);
++					}
++				}
++				_exit_critical_bh(&psta->lock, &irqL);
++
++				if (passoc_req && assoc_req_len > 0) {
++					rtw_cfg80211_indicate_sta_assoc(adapter, passoc_req, assoc_req_len);
++					rtw_mfree(passoc_req, assoc_req_len);
++				}
++				#else /* !CONFIG_IOCTL_CFG80211	 */
++				rtw_indicate_sta_assoc_event(adapter, psta);
++				#endif /* !CONFIG_IOCTL_CFG80211 */
++			}
++#endif /* !CONFIG_AUTO_AP_MODE */
++
++#ifdef CONFIG_BEAMFORMING
++			beamforming_wk_cmd(adapter, BEAMFORMING_CTRL_ENTER, (u8 *)psta, sizeof(struct sta_info), 0);
++#endif/*CONFIG_BEAMFORMING*/
++			if (is_wep_enc(adapter->securitypriv.dot11PrivacyAlgrthm))
++				rtw_ap_wep_pk_setting(adapter, psta);
++		}
++		goto exit;
++	}
++#endif /* defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
++
++	/* for AD-HOC mode */
++	psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr);
++	if (psta == NULL) {
++		RTW_ERR(FUNC_ADPT_FMT" get no sta_info with "MAC_FMT"\n"
++			, FUNC_ADPT_ARG(adapter), MAC_ARG(pstassoc->macaddr));
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	rtw_sta_media_status_rpt(adapter, psta, 1);
++
++	if (adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
++		psta->dot118021XPrivacy = adapter->securitypriv.dot11PrivacyAlgrthm;
++
++
++	psta->ieee8021x_blocked = _FALSE;
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
++	    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) {
++		if (adapter->stapriv.asoc_sta_count == 2) {
++			_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++			ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
++			pmlmepriv->cur_network_scanned = ptarget_wlan;
++			if (ptarget_wlan)
++				ptarget_wlan->fixed = _TRUE;
++			_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++			/* a sta + bc/mc_stainfo (not Ibss_stainfo) */
++			rtw_indicate_connect(adapter);
++		}
++	}
++
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++
++	mlmeext_sta_add_event_callback(adapter, psta);
++
++#ifdef CONFIG_RTL8711
++	/* submit SetStaKey_cmd to tell fw, fw will allocate an CAM entry for this sta	 */
++	rtw_setstakey_cmd(adapter, psta, GROUP_KEY, _TRUE);
++#endif
++
++exit:
++#ifdef CONFIG_RTS_FULL_BW
++	rtw_set_rts_bw(adapter);
++#endif/*CONFIG_RTS_FULL_BW*/
++	return;
++}
++
++#ifdef CONFIG_IEEE80211W
++void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf)
++{
++	_irqL irqL;
++	struct sta_info *psta;
++	struct stadel_event *pstadel = (struct stadel_event *)pbuf;
++	struct sta_priv *pstapriv = &adapter->stapriv;
++
++
++	psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr);
++
++	if (psta) {
++		u8 updated = _FALSE;
++
++		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++		if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
++			rtw_list_delete(&psta->asoc_list);
++			pstapriv->asoc_list_cnt--;
++			#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++			if (psta->tbtx_enable)
++				pstapriv->tbtx_asoc_list_cnt--;
++			#endif
++			updated = ap_free_sta(adapter, psta, _TRUE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE);
++		}
++		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++		associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL);
++	}
++
++
++
++}
++#endif /* CONFIG_IEEE80211W */
++
++void rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id)
++{
++	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
++
++	if (mac_id < macid_ctl->num) {
++		u8 id_is_shared = mac_id == RTW_DEFAULT_MGMT_MACID; /* TODO: real shared macid judgment */
++
++		RTW_INFO(FUNC_ADPT_FMT" - mac_id=%d%s\n", FUNC_ADPT_ARG(adapter)
++			, mac_id, id_is_shared ? " shared" : "");
++
++		if (!id_is_shared) {
++			rtw_hal_macid_drop(adapter, mac_id);
++			rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter, 0, 0, 0, 0, mac_id);
++			/*
++			 * For safety, prevent from keeping macid sleep.
++			 * If we can sure all power mode enter/leave are paired,
++			 * this check can be removed.
++			 * Lucas@20131113
++			 */
++			/* wakeup macid after disconnect. */
++			/*if (MLME_IS_STA(adapter))*/
++			rtw_hal_macid_wakeup(adapter, mac_id);
++		}
++	} else {
++		RTW_PRINT(FUNC_ADPT_FMT" invalid macid:%u\n"
++			  , FUNC_ADPT_ARG(adapter), mac_id);
++		rtw_warn_on(1);
++	}
++}
++void rtw_sta_mstatus_report(_adapter *adapter)
++{
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	struct wlan_network *tgt_network = &pmlmepriv->cur_network;
++	struct sta_info *psta = NULL;
++
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
++		psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress);
++		if (psta)
++			rtw_sta_mstatus_disc_rpt(adapter, psta->cmn.mac_id);
++		else {
++			RTW_INFO("%s "ADPT_FMT" - mac_addr: "MAC_FMT" psta == NULL\n", __func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress));
++			rtw_warn_on(1);
++		}
++	}
++}
++
++void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf)
++{
++	_irqL irqL, irqL2;
++
++	struct sta_info *psta;
++	struct wlan_network *pwlan = NULL;
++	WLAN_BSSID_EX    *pdev_network = NULL;
++	u8 *pibss = NULL;
++	struct	mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
++	struct	stadel_event *pstadel	= (struct stadel_event *)pbuf;
++	struct wlan_network *tgt_network = &(pmlmepriv->cur_network);
++
++	RTW_INFO("%s(mac_id=%d)=" MAC_FMT "\n", __func__, pstadel->mac_id, MAC_ARG(pstadel->macaddr));
++	rtw_sta_mstatus_disc_rpt(adapter, pstadel->mac_id);
++
++#ifdef CONFIG_MCC_MODE
++	rtw_hal_mcc_update_macid_bitmap(adapter, pstadel->mac_id, _FALSE);
++#endif /* CONFIG_MCC_MODE */
++
++	psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr);
++
++	if (psta == NULL) {
++		RTW_INFO("%s(mac_id=%d)=" MAC_FMT " psta == NULL\n", __func__, pstadel->mac_id, MAC_ARG(pstadel->macaddr));
++		/*rtw_warn_on(1);*/
++	}
++
++	if (psta)
++		rtw_wfd_st_switch(psta, 0);
++
++	if (MLME_IS_MESH(adapter)) {
++		rtw_free_stainfo(adapter, psta);
++		goto exit;
++	}
++
++	if (MLME_IS_AP(adapter)) {
++#ifdef CONFIG_IOCTL_CFG80211
++#ifdef COMPAT_KERNEL_RELEASE
++
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
++		rtw_cfg80211_indicate_sta_disassoc(adapter, pstadel->macaddr, *(u16 *)pstadel->rsvd);
++#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++		rtw_free_stainfo(adapter, psta);
++
++		goto exit;
++	}
++
++	mlmeext_sta_del_event_callback(adapter);
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL2);
++
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
++		u16 reason = *((unsigned short *)(pstadel->rsvd));
++		bool roam = _FALSE;
++		struct wlan_network *roam_target = NULL;
++
++#ifdef CONFIG_LAYER2_ROAMING
++#ifdef CONFIG_RTW_80211R
++		if (rtw_ft_roam_expired(adapter, reason))
++			pmlmepriv->ft_roam.ft_roam_on_expired = _TRUE;
++		else
++			pmlmepriv->ft_roam.ft_roam_on_expired = _FALSE;
++#endif
++		if (adapter->registrypriv.wifi_spec == 1)
++			roam = _FALSE;
++		else if (reason == WLAN_REASON_EXPIRATION_CHK && rtw_chk_roam_flags(adapter, RTW_ROAM_ON_EXPIRED))
++			roam = _TRUE;
++		else if (reason == WLAN_REASON_ACTIVE_ROAM && rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) {
++			roam = _TRUE;
++			roam_target = pmlmepriv->roam_network;
++		}
++
++#ifdef CONFIG_RTW_80211R
++		if (reason == WLAN_REASON_ACTIVE_ROAM && rtw_ft_chk_flags(adapter, RTW_FT_BTM_ROAM)) {
++			roam = _TRUE;
++			roam_target = pmlmepriv->roam_network;
++		}
++#endif
++
++		if (roam == _TRUE) {
++			if (rtw_to_roam(adapter) > 0)
++				rtw_dec_to_roam(adapter); /* this stadel_event is caused by roaming, decrease to_roam */
++			else if (rtw_to_roam(adapter) == 0)
++				rtw_set_to_roam(adapter, adapter->registrypriv.max_roaming_times);
++		} else
++			rtw_set_to_roam(adapter, 0);
++#endif /* CONFIG_LAYER2_ROAMING */
++
++		rtw_free_uc_swdec_pending_queue(adapter);
++
++		rtw_free_assoc_resources(adapter, _TRUE);
++		rtw_free_mlme_priv_ie_data(pmlmepriv);
++
++		rtw_indicate_disconnect(adapter, *(u16 *)pstadel->rsvd, pstadel->locally_generated);
++
++		_rtw_roaming(adapter, roam_target);
++	}
++
++	if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) ||
++	    check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) {
++
++		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
++		rtw_free_stainfo(adapter,  psta);
++		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
++
++		if (adapter->stapriv.asoc_sta_count == 1) { /* a sta + bc/mc_stainfo (not Ibss_stainfo) */
++			/* rtw_indicate_disconnect(adapter); */ /* removed@20091105 */
++			_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++			/* free old ibss network */
++			/* pwlan = _rtw_find_network(&pmlmepriv->scanned_queue, pstadel->macaddr); */
++			pwlan = _rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress);
++			if (pwlan) {
++				pwlan->fixed = _FALSE;
++				rtw_free_network_nolock(adapter, pwlan);
++			}
++			_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++			/* re-create ibss */
++			pdev_network = &(adapter->registrypriv.dev_network);
++			pibss = adapter->registrypriv.dev_network.MacAddress;
++
++			_rtw_memcpy(pdev_network, &tgt_network->network, get_WLAN_BSSID_EX_sz(&tgt_network->network));
++
++			_rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID));
++			_rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
++
++			rtw_update_registrypriv_dev_network(adapter);
++
++			rtw_generate_random_ibss(pibss);
++
++			if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) {
++				set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
++				_clr_fwstate_(pmlmepriv, WIFI_ADHOC_STATE);
++			}
++
++			if (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS)
++				RTW_ERR("rtw_create_ibss_cmd FAIL\n");
++
++		}
++
++	}
++
++	_exit_critical_bh(&pmlmepriv->lock, &irqL2);
++exit:
++	#ifdef CONFIG_RTS_FULL_BW
++	rtw_set_rts_bw(adapter);
++	#endif/*CONFIG_RTS_FULL_BW*/
++	return;
++}
++
++void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf)
++{
++
++	WMMOnAssocRsp(padapter);
++
++
++}
++
++/*
++* rtw_join_timeout_handler - Timeout/failure handler for CMD JoinBss
++*/
++void rtw_join_timeout_handler(void *ctx)
++{
++	_adapter *adapter = (_adapter *)ctx;
++	_irqL irqL;
++	struct	mlme_priv *pmlmepriv = &adapter->mlmepriv;
++
++#if 0
++	if (rtw_is_drv_stopped(adapter)) {
++		_rtw_up_sema(&pmlmepriv->assoc_terminate);
++		return;
++	}
++#endif
++
++
++
++	RTW_INFO("%s, fw_state=%x\n", __FUNCTION__, get_fwstate(pmlmepriv));
++
++	if (RTW_CANNOT_RUN(adapter))
++		return;
++
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++#ifdef CONFIG_LAYER2_ROAMING
++	if (rtw_to_roam(adapter) > 0) { /* join timeout caused by roaming */
++		while (1) {
++			rtw_dec_to_roam(adapter);
++			if (rtw_to_roam(adapter) != 0) { /* try another */
++				int do_join_r;
++				RTW_INFO("%s try another roaming\n", __FUNCTION__);
++				do_join_r = rtw_do_join(adapter);
++				if (_SUCCESS != do_join_r) {
++					RTW_INFO("%s roaming do_join return %d\n", __FUNCTION__ , do_join_r);
++					continue;
++				}
++				break;
++			} else {
++				RTW_INFO("%s We've try roaming but fail\n", __FUNCTION__);
++#ifdef CONFIG_RTW_80211R
++				rtw_ft_clr_flags(adapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN);
++				rtw_ft_reset_status(adapter);
++#endif
++				rtw_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE);
++				break;
++			}
++		}
++
++	} else
++#endif
++	{
++		rtw_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE);
++		free_scanqueue(pmlmepriv);/* ??? */
++
++#ifdef CONFIG_IOCTL_CFG80211
++		/* indicate disconnect for the case that join_timeout and check_fwstate != FW_LINKED */
++		rtw_cfg80211_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE);
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++	}
++
++	pmlmepriv->join_status = 0; /* reset */
++
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++
++#ifdef CONFIG_DRVEXT_MODULE_WSC
++	drvext_assoc_fail_indicate(&adapter->drvextpriv);
++#endif
++
++
++
++}
++
++/*
++* rtw_scan_timeout_handler - Timeout/Faliure handler for CMD SiteSurvey
++* @adapter: pointer to _adapter structure
++*/
++void rtw_scan_timeout_handler(void *ctx)
++{
++	_adapter *adapter = (_adapter *)ctx;
++	_irqL irqL;
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	RTW_INFO(FUNC_ADPT_FMT" fw_state=%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv));
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++	_clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY);
++
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++#ifdef CONFIG_IOCTL_CFG80211
++	rtw_cfg80211_surveydone_event_callback(adapter);
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++	rtw_indicate_scan_done(adapter, _TRUE);
++
++#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_IOCTL_CFG80211)
++	rtw_cfg80211_indicate_scan_done_for_buddy(adapter, _TRUE);
++#endif
++}
++
++void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason)
++{
++#if defined(CONFIG_RTW_MESH) && defined(CONFIG_DFS_MASTER)
++#if CONFIG_RTW_MESH_OFFCH_CAND 
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++#endif
++#endif
++	u8 u_ch;
++	u32 interval_ms = 0xffffffff; /* 0xffffffff: special value to make min() works well, also means no auto scan */
++
++	*reason = RTW_AUTO_SCAN_REASON_UNSPECIFIED;
++	rtw_mi_get_ch_setting_union(adapter, &u_ch, NULL, NULL);
++
++	if (hal_chk_bw_cap(adapter, BW_CAP_40M)
++		&& is_client_associated_to_ap(adapter) == _TRUE
++		&& u_ch >= 1 && u_ch <= 14
++		&& adapter->registrypriv.wifi_spec
++		/* TODO: AP Connected is 40MHz capability? */
++	) {
++		interval_ms = rtw_min(interval_ms, 60 * 1000);
++		*reason |= RTW_AUTO_SCAN_REASON_2040_BSS;
++	}
++
++#ifdef CONFIG_RTW_MESH
++	#if CONFIG_RTW_MESH_OFFCH_CAND
++	if (adapter->mesh_cfg.peer_sel_policy.offch_find_int_ms
++		&& rtw_mesh_offch_candidate_accepted(adapter)
++		#ifdef CONFIG_DFS_MASTER
++		&& (!rfctl->radar_detect_ch || (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl)))
++		#endif
++	) {
++		interval_ms = rtw_min(interval_ms, adapter->mesh_cfg.peer_sel_policy.offch_find_int_ms);
++		*reason |= RTW_AUTO_SCAN_REASON_MESH_OFFCH_CAND;
++	}
++	#endif
++#endif /* CONFIG_RTW_MESH */
++
++	if (interval_ms == 0xffffffff)
++		interval_ms = 0;
++
++	rtw_mlme_set_auto_scan_int(adapter, interval_ms);
++	return;
++}
++
++void rtw_drv_scan_by_self(_adapter *padapter, u8 reason)
++{
++	struct sitesurvey_parm parm;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	int i;
++#if 1
++	u8 ssc_chk;
++
++	ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
++	if( ssc_chk == SS_DENY_BUSY_TRAFFIC) {
++		#ifdef CONFIG_LAYER2_ROAMING
++		if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE) && pmlmepriv->need_to_roam == _TRUE)
++			RTW_INFO(FUNC_ADPT_FMT" need to roam, don't care BusyTraffic\n", FUNC_ADPT_ARG(padapter));
++		else
++		#endif
++			RTW_INFO(FUNC_ADPT_FMT" exit BusyTraffic\n", FUNC_ADPT_ARG(padapter));
++			goto exit;
++	}
++	else if (ssc_chk != SS_ALLOW)
++		goto exit;
++
++	if (!rtw_is_adapter_up(padapter))
++		goto exit;
++#else
++	if (rtw_is_scan_deny(padapter))
++		goto exit;
++
++	if (!rtw_is_adapter_up(padapter))
++		goto exit;
++
++	if (rtw_mi_busy_traffic_check(padapter)) {
++#ifdef CONFIG_LAYER2_ROAMING
++		if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE) && pmlmepriv->need_to_roam == _TRUE) {
++			RTW_INFO("need to roam, don't care BusyTraffic\n");
++		} else
++#endif
++		{
++			RTW_INFO(FUNC_ADPT_FMT" exit BusyTraffic\n", FUNC_ADPT_ARG(padapter));
++			goto exit;
++		}
++	}
++	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
++		RTW_INFO(FUNC_ADPT_FMT" WIFI_AP_STATE && WIFI_UNDER_WPS\n", FUNC_ADPT_ARG(padapter));
++		goto exit;
++	}
++	if (check_fwstate(pmlmepriv, (WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING)) == _TRUE) {
++		RTW_INFO(FUNC_ADPT_FMT" WIFI_UNDER_SURVEY|WIFI_UNDER_LINKING\n", FUNC_ADPT_ARG(padapter));
++		goto exit;
++	}
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_buddy_check_fwstate(padapter, (WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING | WIFI_UNDER_WPS))) {
++		RTW_INFO(FUNC_ADPT_FMT", but buddy_intf is under scanning or linking or wps_phase\n", FUNC_ADPT_ARG(padapter));
++		goto exit;
++	}
++#endif
++#endif
++
++	RTW_INFO(FUNC_ADPT_FMT" reason:0x%02x\n", FUNC_ADPT_ARG(padapter), reason);
++
++	/* only for 20/40 BSS */
++	if (reason == RTW_AUTO_SCAN_REASON_2040_BSS) {
++		rtw_init_sitesurvey_parm(padapter, &parm);
++		for (i=0;i<14;i++) {
++			parm.ch[i].hw_value = i + 1;
++			parm.ch[i].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN;
++		}
++		parm.ch_num = 14;
++		rtw_set_802_11_bssid_list_scan(padapter, &parm);
++		goto exit;
++	}
++
++#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
++	if ((reason == RTW_AUTO_SCAN_REASON_ROAM) 
++		&& (rtw_roam_nb_scan_list_set(padapter, &parm)))
++		goto exit;
++#endif
++
++	rtw_set_802_11_bssid_list_scan(padapter, NULL);
++exit:
++	return;
++}
++
++static void rtw_auto_scan_handler(_adapter *padapter)
++{
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	u8 reason = RTW_AUTO_SCAN_REASON_UNSPECIFIED;
++
++	rtw_mlme_reset_auto_scan_int(padapter, &reason);
++
++#ifdef CONFIG_P2P
++	if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE))
++		goto exit;
++#endif
++
++#ifdef CONFIG_TDLS
++	if (padapter->tdlsinfo.link_established == _TRUE)
++		goto exit;
++#endif
++
++	if (pmlmepriv->auto_scan_int_ms == 0
++	    || rtw_get_passing_time_ms(pmlmepriv->scan_start_time) < pmlmepriv->auto_scan_int_ms)
++		goto exit;
++
++	rtw_drv_scan_by_self(padapter, reason);
++
++exit:
++	return;
++}
++static u8 is_drv_in_lps(_adapter *adapter)
++{
++	u8 is_in_lps = _FALSE;
++
++	#ifdef CONFIG_LPS_LCLK_WD_TIMER /* to avoid leaving lps 32k frequently*/
++	if ((adapter_to_pwrctl(adapter)->bFwCurrentInPSMode == _TRUE)
++	#ifdef CONFIG_BT_COEXIST
++		&& (rtw_btcoex_IsBtControlLps(adapter) == _FALSE)
++	#endif
++		)
++		is_in_lps = _TRUE;
++	#endif /* CONFIG_LPS_LCLK_WD_TIMER*/
++	return is_in_lps;
++}
++void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter)
++{
++#ifdef CONFIG_AP_MODE
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++#endif /* CONFIG_AP_MODE */
++
++	if (adapter->net_closed == _TRUE)
++		return;
++	#ifdef CONFIG_LPS_LCLK_WD_TIMER /* to avoid leaving lps 32k frequently*/
++	if (is_drv_in_lps(adapter)) {
++		u8 bEnterPS;
++
++		linked_status_chk(adapter, 1);
++
++		bEnterPS = traffic_status_watchdog(adapter, 1);
++		if (bEnterPS) {
++			/* rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_ENTER, 0); */
++			rtw_hal_dm_watchdog_in_lps(adapter);
++		} else {
++			/* call rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0) in traffic_status_watchdog() */
++		}
++	}
++	#endif /* CONFIG_LPS_LCLK_WD_TIMER	*/
++
++	/* auto site survey */
++	rtw_auto_scan_handler(adapter);
++
++#ifdef CONFIG_AP_MODE
++	if (MLME_IS_AP(adapter)|| MLME_IS_MESH(adapter)) {
++		#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++		expire_timeout_chk(adapter);
++		#endif /* !CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
++
++		#ifdef CONFIG_BMC_TX_RATE_SELECT
++		rtw_update_bmc_sta_tx_rate(adapter);
++		#endif /*CONFIG_BMC_TX_RATE_SELECT*/
++	}
++#endif /*CONFIG_AP_MODE*/
++
++
++#ifdef CONFIG_BR_EXT
++if (!adapter_use_wds(adapter)) {
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
++	rcu_read_lock();
++#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) */
++
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++	if (adapter->pnetdev->br_port
++#else	/* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
++	if (rcu_dereference(adapter->pnetdev->rx_handler_data)
++#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
++		&& (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE)) {
++		/* expire NAT2.5 entry */
++		void nat25_db_expire(_adapter *priv);
++		nat25_db_expire(adapter);
++
++		if (adapter->pppoe_connection_in_progress > 0)
++			adapter->pppoe_connection_in_progress--;
++		/* due to rtw_dynamic_check_timer_handlder() is called every 2 seconds */
++		if (adapter->pppoe_connection_in_progress > 0)
++			adapter->pppoe_connection_in_progress--;
++	}
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
++	rcu_read_unlock();
++#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) */
++}
++#endif /* CONFIG_BR_EXT */
++
++}
++
++/*TP_avg(t) = (1/10) * TP_avg(t-1) + (9/10) * TP(t) MBps*/
++static void collect_sta_traffic_statistics(_adapter *adapter)
++{
++	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
++	struct sta_info *sta;
++	u64 curr_tx_bytes = 0, curr_rx_bytes = 0;
++	u32 curr_tx_mbytes = 0, curr_rx_mbytes = 0;
++	int i;
++
++	for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
++		sta = macid_ctl->sta[i];
++		if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr)) {
++			if (sta->sta_stats.last_tx_bytes > sta->sta_stats.tx_bytes)
++				sta->sta_stats.last_tx_bytes =  sta->sta_stats.tx_bytes;
++			if (sta->sta_stats.last_rx_bytes > sta->sta_stats.rx_bytes)
++				sta->sta_stats.last_rx_bytes = sta->sta_stats.rx_bytes;
++			if (sta->sta_stats.last_rx_bc_bytes > sta->sta_stats.rx_bc_bytes)
++				sta->sta_stats.last_rx_bc_bytes = sta->sta_stats.rx_bc_bytes;
++			if (sta->sta_stats.last_rx_mc_bytes > sta->sta_stats.rx_mc_bytes)
++				sta->sta_stats.last_rx_mc_bytes = sta->sta_stats.rx_mc_bytes;
++
++			curr_tx_bytes = sta->sta_stats.tx_bytes - sta->sta_stats.last_tx_bytes;
++			curr_rx_bytes = sta->sta_stats.rx_bytes - sta->sta_stats.last_rx_bytes;
++			sta->sta_stats.tx_tp_kbits = (curr_tx_bytes * 8 / 2) >> 10;/*Kbps*/
++			sta->sta_stats.rx_tp_kbits = (curr_rx_bytes * 8 / 2) >> 10;/*Kbps*/
++
++			sta->sta_stats.smooth_tx_tp_kbits = (sta->sta_stats.smooth_tx_tp_kbits * 6 / 10) + (sta->sta_stats.tx_tp_kbits * 4 / 10);/*Kbps*/
++			sta->sta_stats.smooth_rx_tp_kbits = (sta->sta_stats.smooth_rx_tp_kbits * 6 / 10) + (sta->sta_stats.rx_tp_kbits * 4 / 10);/*Kbps*/
++
++			curr_tx_mbytes = (curr_tx_bytes / 2) >> 20;/*MBps*/
++			curr_rx_mbytes = (curr_rx_bytes / 2) >> 20;/*MBps*/
++
++			sta->cmn.tx_moving_average_tp =
++				(sta->cmn.tx_moving_average_tp / 10) + (curr_tx_mbytes * 9 / 10); /*MBps*/
++
++			sta->cmn.rx_moving_average_tp =
++				(sta->cmn.rx_moving_average_tp / 10) + (curr_rx_mbytes * 9 /10); /*MBps*/
++
++			rtw_collect_bcn_info(sta->padapter);
++
++			if (adapter->bsta_tp_dump)
++				dump_sta_traffic(RTW_DBGDUMP, adapter, sta);
++
++			sta->sta_stats.last_tx_bytes = sta->sta_stats.tx_bytes;
++			sta->sta_stats.last_rx_bytes = sta->sta_stats.rx_bytes;
++			sta->sta_stats.last_rx_bc_bytes = sta->sta_stats.rx_bc_bytes;
++			sta->sta_stats.last_rx_mc_bytes = sta->sta_stats.rx_mc_bytes;
++		}
++	}
++}
++
++void rtw_sta_traffic_info(void *sel, _adapter *adapter)
++{
++	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
++	struct sta_info *sta;
++	int i;
++
++	for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
++		sta = macid_ctl->sta[i];
++		if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr))
++			dump_sta_traffic(sel, adapter, sta);
++	}
++}
++
++/*#define DBG_TRAFFIC_STATISTIC*/
++static void collect_traffic_statistics(_adapter *padapter)
++{
++	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
++
++	/*_rtw_memset(&pdvobjpriv->traffic_stat, 0, sizeof(struct rtw_traffic_statistics));*/
++
++	/* Tx bytes reset*/
++	pdvobjpriv->traffic_stat.tx_bytes = 0;
++	pdvobjpriv->traffic_stat.tx_pkts = 0;
++	pdvobjpriv->traffic_stat.tx_drop = 0;
++
++	/* Rx bytes reset*/
++	pdvobjpriv->traffic_stat.rx_bytes = 0;
++	pdvobjpriv->traffic_stat.rx_pkts = 0;
++	pdvobjpriv->traffic_stat.rx_drop = 0;
++
++	rtw_mi_traffic_statistics(padapter);
++
++	/* Calculate throughput in last interval */
++	pdvobjpriv->traffic_stat.cur_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes - pdvobjpriv->traffic_stat.last_tx_bytes;
++	pdvobjpriv->traffic_stat.cur_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes - pdvobjpriv->traffic_stat.last_rx_bytes;
++	pdvobjpriv->traffic_stat.last_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes;
++	pdvobjpriv->traffic_stat.last_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes;
++
++	pdvobjpriv->traffic_stat.cur_tx_tp = (u32)(pdvobjpriv->traffic_stat.cur_tx_bytes * 8 / 2 / 1024 / 1024);/*Mbps*/
++	pdvobjpriv->traffic_stat.cur_rx_tp = (u32)(pdvobjpriv->traffic_stat.cur_rx_bytes * 8 / 2 / 1024 / 1024);/*Mbps*/
++
++	#ifdef DBG_TRAFFIC_STATISTIC
++	RTW_INFO("\n========================\n");
++	RTW_INFO("cur_tx_bytes:%lld\n", pdvobjpriv->traffic_stat.cur_tx_bytes);
++	RTW_INFO("cur_rx_bytes:%lld\n", pdvobjpriv->traffic_stat.cur_rx_bytes);
++
++	RTW_INFO("last_tx_bytes:%lld\n", pdvobjpriv->traffic_stat.last_tx_bytes);
++	RTW_INFO("last_rx_bytes:%lld\n", pdvobjpriv->traffic_stat.last_rx_bytes);
++
++	RTW_INFO("cur_tx_tp:%d (Mbps)\n", pdvobjpriv->traffic_stat.cur_tx_tp);
++	RTW_INFO("cur_rx_tp:%d (Mbps)\n", pdvobjpriv->traffic_stat.cur_rx_tp);
++	#endif
++
++#ifdef CONFIG_RTW_NAPI
++#ifdef CONFIG_RTW_NAPI_DYNAMIC
++	dynamic_napi_th_chk (padapter);
++#endif /* CONFIG_RTW_NAPI_DYNAMIC */
++#endif
++	
++}
++
++void rtw_dynamic_check_timer_handlder(void *ctx)
++{
++	struct dvobj_priv *pdvobj = (struct dvobj_priv *)ctx;
++	_adapter *adapter = dvobj_get_primary_adapter(pdvobj);
++
++	if (!adapter)
++		goto exit;
++
++#if (MP_DRIVER == 1)
++	if (adapter->registrypriv.mp_mode == 1 && adapter->mppriv.mp_dm == 0) { /* for MP ODM dynamic Tx power tracking */
++		/* RTW_INFO("%s mp_dm =0 return\n", __func__); */
++		goto exit;
++	}
++#endif
++
++	if (!rtw_is_hw_init_completed(adapter))
++		goto exit;
++
++	if (RTW_CANNOT_RUN(adapter))
++		goto exit;
++
++	collect_traffic_statistics(adapter);
++	collect_sta_traffic_statistics(adapter);
++	rtw_mi_dynamic_check_timer_handlder(adapter);
++
++	if (!is_drv_in_lps(adapter))
++		rtw_dynamic_chk_wk_cmd(adapter);
++
++exit:
++	_set_timer(&pdvobj->dynamic_chk_timer, 2000);
++}
++
++
++#ifdef CONFIG_SET_SCAN_DENY_TIMER
++inline bool rtw_is_scan_deny(_adapter *adapter)
++{
++	struct mlme_priv *mlmepriv = &adapter->mlmepriv;
++	return (ATOMIC_READ(&mlmepriv->set_scan_deny) != 0) ? _TRUE : _FALSE;
++}
++
++inline void rtw_clear_scan_deny(_adapter *adapter)
++{
++	struct mlme_priv *mlmepriv = &adapter->mlmepriv;
++	ATOMIC_SET(&mlmepriv->set_scan_deny, 0);
++	if (0)
++		RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
++}
++
++void rtw_set_scan_deny_timer_hdl(void *ctx)
++{
++	_adapter *adapter = (_adapter *)ctx;
++
++	rtw_clear_scan_deny(adapter);
++}
++void rtw_set_scan_deny(_adapter *adapter, u32 ms)
++{
++	struct mlme_priv *mlmepriv = &adapter->mlmepriv;
++	if (0)
++		RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
++	ATOMIC_SET(&mlmepriv->set_scan_deny, 1);
++	_set_timer(&mlmepriv->set_scan_deny_timer, ms);
++}
++#endif
++
++#ifdef CONFIG_LAYER2_ROAMING
++/*
++* Select a new roaming candidate from the original @param candidate and @param competitor
++* @return _TRUE: candidate is updated
++* @return _FALSE: candidate is not updated
++*/
++static int rtw_check_roaming_candidate(struct mlme_priv *mlme
++	, struct wlan_network **candidate, struct wlan_network *competitor)
++{
++	int updated = _FALSE;
++	_adapter *adapter = container_of(mlme, _adapter, mlmepriv);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	RT_CHANNEL_INFO *chset = rfctl->channel_set;
++	u8 ch = competitor->network.Configuration.DSConfig;
++
++	if (rtw_chset_search_ch(chset, ch) < 0)
++		goto exit;
++	if (IS_DFS_SLAVE_WITH_RD(rfctl)
++		&& !rtw_rfctl_dfs_domain_unknown(rfctl)
++		&& rtw_chset_is_ch_non_ocp(chset, ch))
++		goto exit;
++
++#if defined(CONFIG_RTW_REPEATER_SON) &&  (!defined(CONFIG_RTW_REPEATER_SON_ROOT))
++	if (rtw_rson_isupdate_roamcan(mlme, candidate, competitor))
++		goto  update;
++	goto exit;
++#endif
++
++	if (is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE)
++		goto exit;
++
++	if (rtw_is_desired_network(adapter, competitor) == _FALSE)
++		goto exit;
++
++#ifdef CONFIG_LAYER2_ROAMING
++	if (mlme->need_to_roam == _FALSE)
++		goto exit;
++#endif
++
++	RTW_INFO("roam candidate:%s %s("MAC_FMT", ch%3u) rssi:%d, age:%5d\n",
++		 (competitor == mlme->cur_network_scanned) ? "*" : " " ,
++		 competitor->network.Ssid.Ssid,
++		 MAC_ARG(competitor->network.MacAddress),
++		 competitor->network.Configuration.DSConfig,
++		 (int)competitor->network.Rssi,
++		 rtw_get_passing_time_ms(competitor->last_scanned)
++		);
++
++	/* got specific addr to roam */
++	if (!is_zero_mac_addr(mlme->roam_tgt_addr)) {
++		if (_rtw_memcmp(mlme->roam_tgt_addr, competitor->network.MacAddress, ETH_ALEN) == _TRUE)
++			goto update;
++		else
++			goto exit;
++	}
++
++#ifdef CONFIG_RTW_80211R
++	if (rtw_ft_chk_flags(adapter, RTW_FT_PEER_EN)) {
++		if (rtw_ft_chk_roaming_candidate(adapter, competitor) == _FALSE)
++		goto exit;
++	}
++
++#ifdef CONFIG_RTW_WNM
++	if (rtw_wnm_btm_diff_bss(adapter) && 
++		rtw_wnm_btm_roam_candidate(adapter, competitor)) {
++		goto update;
++	}	
++#endif
++#endif
++
++#if 1
++	if (rtw_get_passing_time_ms(competitor->last_scanned) >= mlme->roam_scanr_exp_ms)
++		goto exit;
++
++	if (competitor->network.Rssi - mlme->cur_network_scanned->network.Rssi < mlme->roam_rssi_diff_th)
++		goto exit;
++
++	if (*candidate != NULL && (*candidate)->network.Rssi >= competitor->network.Rssi)
++		goto exit;
++#else
++	goto exit;
++#endif
++
++update:
++	*candidate = competitor;
++	updated = _TRUE;
++
++exit:
++	return updated;
++}
++
++int rtw_select_roaming_candidate(struct mlme_priv *mlme)
++{
++	_irqL	irqL;
++	int ret = _FAIL;
++	_list	*phead;
++	_adapter *adapter;
++	_queue	*queue	= &(mlme->scanned_queue);
++	struct	wlan_network	*pnetwork = NULL;
++	struct	wlan_network	*candidate = NULL;
++
++	if (mlme->cur_network_scanned == NULL) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	_enter_critical_bh(&(mlme->scanned_queue.lock), &irqL);
++	phead = get_list_head(queue);
++	adapter = (_adapter *)mlme->nic_hdl;
++
++	mlme->pscanned = get_next(phead);
++
++	while (!rtw_end_of_queue_search(phead, mlme->pscanned)) {
++
++		pnetwork = LIST_CONTAINOR(mlme->pscanned, struct wlan_network, list);
++		if (pnetwork == NULL) {
++			ret = _FAIL;
++			goto exit;
++		}
++
++		mlme->pscanned = get_next(mlme->pscanned);
++
++		if (0)
++			RTW_INFO("%s("MAC_FMT", ch%u) rssi:%d\n"
++				 , pnetwork->network.Ssid.Ssid
++				 , MAC_ARG(pnetwork->network.MacAddress)
++				 , pnetwork->network.Configuration.DSConfig
++				 , (int)pnetwork->network.Rssi);
++
++		rtw_check_roaming_candidate(mlme, &candidate, pnetwork);
++
++	}
++
++	if (candidate == NULL) {
++	/*	if parent note lost the path to root and there is no other cadidate, report disconnection	*/
++#if defined(CONFIG_RTW_REPEATER_SON) &&  (!defined(CONFIG_RTW_REPEATER_SON_ROOT))
++		struct rtw_rson_struct  rson_curr;
++		u8 rson_score;
++
++		rtw_get_rson_struct(&(mlme->cur_network_scanned->network), &rson_curr);
++		rson_score = rtw_cal_rson_score(&rson_curr, mlme->cur_network_scanned->network.Rssi);
++		if (check_fwstate(mlme, WIFI_ASOC_STATE)
++			&& ((rson_score == RTW_RSON_SCORE_NOTCNNT)
++			|| (rson_score == RTW_RSON_SCORE_NOTSUP)))
++			receive_disconnect(adapter, mlme->cur_network_scanned->network.MacAddress
++								, WLAN_REASON_EXPIRATION_CHK, _FALSE);
++#endif
++		RTW_INFO("%s: return _FAIL(candidate == NULL)\n", __FUNCTION__);
++		ret = _FAIL;
++		goto exit;
++	} else {
++#if defined(CONFIG_RTW_REPEATER_SON) &&  (!defined(CONFIG_RTW_REPEATER_SON_ROOT))
++		struct rtw_rson_struct  rson_curr;
++		u8 rson_score;
++
++		rtw_get_rson_struct(&(candidate->network), &rson_curr);
++		rson_score = rtw_cal_rson_score(&rson_curr, candidate->network.Rssi);
++		RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u) rson_score:%d\n", __FUNCTION__,
++			candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress),
++			 candidate->network.Configuration.DSConfig, rson_score);
++#else
++		RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u)\n", __FUNCTION__,
++			candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress),
++			 candidate->network.Configuration.DSConfig);
++#endif
++		mlme->roam_network = candidate;
++
++		if (_rtw_memcmp(candidate->network.MacAddress, mlme->roam_tgt_addr, ETH_ALEN) == _TRUE)
++			_rtw_memset(mlme->roam_tgt_addr, 0, ETH_ALEN);
++	}
++
++	ret = _SUCCESS;
++exit:
++	_exit_critical_bh(&(mlme->scanned_queue.lock), &irqL);
++
++	return ret;
++}
++#endif /* CONFIG_LAYER2_ROAMING */
++
++/*
++* Select a new join candidate from the original @param candidate and @param competitor
++* @return _TRUE: candidate is updated
++* @return _FALSE: candidate is not updated
++*/
++static int rtw_check_join_candidate(struct mlme_priv *mlme
++	    , struct wlan_network **candidate, struct wlan_network *competitor)
++{
++	int updated = _FALSE;
++	_adapter *adapter = container_of(mlme, _adapter, mlmepriv);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	RT_CHANNEL_INFO *chset = rfctl->channel_set;
++	u8 ch = competitor->network.Configuration.DSConfig;
++
++	if (rtw_chset_search_ch(chset, ch) < 0)
++		goto exit;
++	if (IS_DFS_SLAVE_WITH_RD(rfctl)
++		&& !rtw_rfctl_dfs_domain_unknown(rfctl)
++		&& rtw_chset_is_ch_non_ocp(chset, ch))
++		goto exit;
++
++#if defined(CONFIG_RTW_REPEATER_SON) &&  (!defined(CONFIG_RTW_REPEATER_SON_ROOT))
++	s16 rson_score;
++	struct rtw_rson_struct  rson_data;
++
++	if (rtw_rson_choose(candidate, competitor)) {
++		*candidate = competitor;
++		rtw_get_rson_struct(&((*candidate)->network), &rson_data);
++		rson_score = rtw_cal_rson_score(&rson_data, (*candidate)->network.Rssi);
++		RTW_INFO("[assoc_ssid:%s] new candidate: %s("MAC_FMT", ch%u) rson_score:%d\n",
++			 mlme->assoc_ssid.Ssid,
++			 (*candidate)->network.Ssid.Ssid,
++			 MAC_ARG((*candidate)->network.MacAddress),
++			 (*candidate)->network.Configuration.DSConfig,
++			 rson_score);
++		return _TRUE;
++	}
++	return _FALSE;
++#endif
++
++	/* check bssid, if needed */
++	if (mlme->assoc_by_bssid == _TRUE) {
++		if (_rtw_memcmp(competitor->network.MacAddress, mlme->assoc_bssid, ETH_ALEN) == _FALSE)
++			goto exit;
++	}
++
++	/* check ssid, if needed */
++	if (mlme->assoc_ssid.Ssid[0] && mlme->assoc_ssid.SsidLength) {
++		if (competitor->network.Ssid.SsidLength != mlme->assoc_ssid.SsidLength
++		    || _rtw_memcmp(competitor->network.Ssid.Ssid, mlme->assoc_ssid.Ssid, mlme->assoc_ssid.SsidLength) == _FALSE
++		   )
++			goto exit;
++	}
++
++	if (rtw_is_desired_network(adapter, competitor)  == _FALSE)
++		goto exit;
++
++#ifdef CONFIG_LAYER2_ROAMING
++	if (rtw_to_roam(adapter) > 0) {
++		if (rtw_get_passing_time_ms(competitor->last_scanned) >= mlme->roam_scanr_exp_ms
++		    || is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE
++		   )
++			goto exit;
++	}
++#endif
++
++	if (*candidate == NULL || (*candidate)->network.Rssi < competitor->network.Rssi) {
++		*candidate = competitor;
++		updated = _TRUE;
++	}
++
++	if (updated) {
++		RTW_INFO("[by_bssid:%u][assoc_ssid:%s][to_roam:%u] "
++			 "new candidate: %s("MAC_FMT", ch%u) rssi:%d\n",
++			 mlme->assoc_by_bssid,
++			 mlme->assoc_ssid.Ssid,
++			 rtw_to_roam(adapter),
++			 (*candidate)->network.Ssid.Ssid,
++			 MAC_ARG((*candidate)->network.MacAddress),
++			 (*candidate)->network.Configuration.DSConfig,
++			 (int)(*candidate)->network.Rssi
++			);
++	}
++
++exit:
++	return updated;
++}
++
++/*
++Calling context:
++The caller of the sub-routine will be in critical section...
++
++The caller must hold the following spinlock
++
++pmlmepriv->lock
++
++
++*/
++
++int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv)
++{
++	_irqL	irqL;
++	int ret;
++	_list	*phead;
++	_adapter *adapter;
++	_queue	*queue	= &(pmlmepriv->scanned_queue);
++	struct	wlan_network	*pnetwork = NULL;
++	struct	wlan_network	*candidate = NULL;
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	u8		bSupportAntDiv = _FALSE;
++#endif
++
++	adapter = (_adapter *)pmlmepriv->nic_hdl;
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++#ifdef CONFIG_LAYER2_ROAMING
++	if (pmlmepriv->roam_network) {
++		candidate = pmlmepriv->roam_network;
++		pmlmepriv->roam_network = NULL;
++		goto candidate_exist;
++	}
++#endif
++
++	phead = get_list_head(queue);
++	pmlmepriv->pscanned = get_next(phead);
++
++	while (!rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) {
++
++		pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);
++		if (pnetwork == NULL) {
++			ret = _FAIL;
++			goto exit;
++		}
++
++		pmlmepriv->pscanned = get_next(pmlmepriv->pscanned);
++
++		if (0)
++			RTW_INFO("%s("MAC_FMT", ch%u) rssi:%d\n"
++				 , pnetwork->network.Ssid.Ssid
++				 , MAC_ARG(pnetwork->network.MacAddress)
++				 , pnetwork->network.Configuration.DSConfig
++				 , (int)pnetwork->network.Rssi);
++
++		rtw_check_join_candidate(pmlmepriv, &candidate, pnetwork);
++
++	}
++
++	if (candidate == NULL) {
++		RTW_INFO("%s: return _FAIL(candidate == NULL)\n", __FUNCTION__);
++#ifdef CONFIG_WOWLAN
++		_clr_fwstate_(pmlmepriv, WIFI_ASOC_STATE | WIFI_UNDER_LINKING);
++#endif
++		ret = _FAIL;
++		goto exit;
++	} else {
++		RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u)\n", __FUNCTION__,
++			candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress),
++			 candidate->network.Configuration.DSConfig);
++		goto candidate_exist;
++	}
++
++candidate_exist:
++
++	/* check for situation of  WIFI_ASOC_STATE */
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++		RTW_INFO("%s: WIFI_ASOC_STATE while ask_for_joinbss!!!\n", __FUNCTION__);
++
++#if 0 /* for WPA/WPA2 authentication, wpa_supplicant will expect authentication from AP, it is needed to reconnect AP... */
++		if (is_same_network(&pmlmepriv->cur_network.network, &candidate->network)) {
++			RTW_INFO("%s: WIFI_ASOC_STATE and is same network, it needn't join again\n", __FUNCTION__);
++
++			rtw_indicate_connect(adapter);/* rtw_indicate_connect again */
++
++			ret = 2;
++			goto exit;
++		} else
++#endif
++		{
++			rtw_disassoc_cmd(adapter, 0, 0);
++			rtw_indicate_disconnect(adapter, 0, _FALSE);
++			rtw_free_assoc_resources_cmd(adapter, _TRUE, 0);
++		}
++	}
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	rtw_hal_get_def_var(adapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv));
++	if (_TRUE == bSupportAntDiv) {
++		u8 CurrentAntenna;
++		rtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(CurrentAntenna), NULL);
++		RTW_INFO("#### Opt_Ant_(%s) , cur_Ant(%s)\n",
++			(MAIN_ANT == candidate->network.PhyInfo.Optimum_antenna) ? "MAIN_ANT" : "AUX_ANT",
++			 (MAIN_ANT == CurrentAntenna) ? "MAIN_ANT" : "AUX_ANT"
++			);
++	}
++#endif
++	set_fwstate(pmlmepriv, WIFI_UNDER_LINKING);
++	ret = rtw_joinbss_cmd(adapter, candidate);
++
++exit:
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++
++	return ret;
++}
++
++sint rtw_set_auth(_adapter *adapter, struct security_priv *psecuritypriv)
++{
++	struct	cmd_obj *pcmd;
++	struct	setauth_parm *psetauthparm;
++	struct	cmd_priv	*pcmdpriv = &(adapter->cmdpriv);
++	sint		res = _SUCCESS;
++
++
++	pcmd = (struct	cmd_obj *)rtw_zmalloc(sizeof(struct	cmd_obj));
++	if (pcmd == NULL) {
++		res = _FAIL; /* try again */
++		goto exit;
++	}
++
++	psetauthparm = (struct setauth_parm *)rtw_zmalloc(sizeof(struct setauth_parm));
++	if (psetauthparm == NULL) {
++		rtw_mfree((unsigned char *)pcmd, sizeof(struct	cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	_rtw_memset(psetauthparm, 0, sizeof(struct setauth_parm));
++	psetauthparm->mode = (unsigned char)psecuritypriv->dot11AuthAlgrthm;
++
++	pcmd->cmdcode = CMD_SET_AUTH;
++	pcmd->parmbuf = (unsigned char *)psetauthparm;
++	pcmd->cmdsz = (sizeof(struct setauth_parm));
++	pcmd->rsp = NULL;
++	pcmd->rspsz = 0;
++
++
++	_rtw_init_listhead(&pcmd->list);
++
++
++	res = rtw_enqueue_cmd(pcmdpriv, pcmd);
++
++exit:
++
++
++	return res;
++
++}
++
++
++sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint keyid, u8 set_tx, bool enqueue)
++{
++	u8	keylen;
++	struct cmd_obj		*pcmd;
++	struct setkey_parm	*psetkeyparm;
++	struct cmd_priv		*pcmdpriv = &(adapter->cmdpriv);
++	sint	res = _SUCCESS;
++
++
++	psetkeyparm = (struct setkey_parm *)rtw_zmalloc(sizeof(struct setkey_parm));
++	if (psetkeyparm == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++	_rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm));
++
++	if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) {
++		psetkeyparm->algorithm = (unsigned char)psecuritypriv->dot118021XGrpPrivacy;
++	} else {
++		psetkeyparm->algorithm = (u8)psecuritypriv->dot11PrivacyAlgrthm;
++
++	}
++	psetkeyparm->keyid = (u8)keyid;/* 0~3 */
++	psetkeyparm->set_tx = set_tx;
++	if (is_wep_enc(psetkeyparm->algorithm))
++		adapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid);
++
++	RTW_INFO("==> rtw_set_key algorithm(%x),keyid(%x),key_mask(%x)\n", psetkeyparm->algorithm, psetkeyparm->keyid, adapter->securitypriv.key_mask);
++
++	switch (psetkeyparm->algorithm) {
++
++	case _WEP40_:
++		keylen = 5;
++		_rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen);
++		break;
++	case _WEP104_:
++		keylen = 13;
++		_rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen);
++		break;
++	case _TKIP_:
++		keylen = 16;
++		_rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen);
++		break;
++	case _AES_:
++	case _GCMP_:
++		keylen = 16;
++		_rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen);
++		break;
++	case _GCMP_256_:
++	case _CCMP_256_:
++		keylen = 32;
++		_rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen);
++		break;
++	default:
++		res = _FAIL;
++		rtw_mfree((unsigned char *)psetkeyparm, sizeof(struct setkey_parm));
++		goto exit;
++	}
++
++
++	if (enqueue) {
++		pcmd = (struct	cmd_obj *)rtw_zmalloc(sizeof(struct	cmd_obj));
++		if (pcmd == NULL) {
++			rtw_mfree((unsigned char *)psetkeyparm, sizeof(struct setkey_parm));
++			res = _FAIL; /* try again */
++			goto exit;
++		}
++
++		pcmd->cmdcode =CMD_SET_KEY;
++		pcmd->parmbuf = (u8 *)psetkeyparm;
++		pcmd->cmdsz = (sizeof(struct setkey_parm));
++		pcmd->rsp = NULL;
++		pcmd->rspsz = 0;
++
++		_rtw_init_listhead(&pcmd->list);
++
++		/* _rtw_init_sema(&(pcmd->cmd_sem), 0); */
++
++		res = rtw_enqueue_cmd(pcmdpriv, pcmd);
++	} else {
++		setkey_hdl(adapter, (u8 *)psetkeyparm);
++		rtw_mfree((u8 *) psetkeyparm, sizeof(struct setkey_parm));
++	}
++exit:
++	return res;
++
++}
++
++#ifdef CONFIG_WMMPS_STA
++/*
++ * rtw_uapsd_use_default_setting
++ * This function is used for setting default uapsd max sp length to uapsd_max_sp_len
++ * in qos_priv data structure from registry. In additional, it will also map default uapsd 
++ * ac to each uapsd TID, delivery-enabled and trigger-enabled of corresponding TID. 
++ * 
++ * Arguments:
++ * @padapter: _adapter pointer.
++ *
++ * Auther: Arvin Liu
++ * Date: 2017/05/03
++ */
++void	rtw_uapsd_use_default_setting(_adapter *padapter)
++{
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
++	struct registry_priv		*pregistrypriv = &padapter->registrypriv;
++
++	if (pregistrypriv->uapsd_ac_enable != 0) {
++		pqospriv->uapsd_max_sp_len = pregistrypriv->uapsd_max_sp_len;
++		
++		CLEAR_FLAGS(pqospriv->uapsd_tid);
++		CLEAR_FLAGS(pqospriv->uapsd_tid_delivery_enabled);
++		CLEAR_FLAGS(pqospriv->uapsd_tid_trigger_enabled);
++
++		/* check the uapsd setting of AC_VO from registry then map these setting to each TID if necessary  */
++		if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_VO)) {
++			SET_FLAG(pqospriv->uapsd_tid, WMM_TID7);
++			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID7);
++			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID7);
++			SET_FLAG(pqospriv->uapsd_tid, WMM_TID6);
++			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID6);
++			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID6);
++		}
++
++		/* check the uapsd setting of AC_VI from registry then map these setting to each TID if necessary  */
++		if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_VI)) {	
++			SET_FLAG(pqospriv->uapsd_tid, WMM_TID5);
++			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID5);
++			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID5);
++			SET_FLAG(pqospriv->uapsd_tid, WMM_TID4);
++			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID4);
++			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID4);
++		}
++
++		/* check the uapsd setting of AC_BK from registry then map these setting to each TID if necessary  */
++		if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_BK)) {
++			SET_FLAG(pqospriv->uapsd_tid, WMM_TID2);
++			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID2);
++			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID2);
++			SET_FLAG(pqospriv->uapsd_tid, WMM_TID1);
++			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID1);
++			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID1);
++		}
++
++		/* check the uapsd setting of AC_BE from registry then map these setting to each TID if necessary  */
++		if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_BE)) {
++			SET_FLAG(pqospriv->uapsd_tid, WMM_TID3);
++			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID3);
++			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID3);
++			SET_FLAG(pqospriv->uapsd_tid, WMM_TID0);
++			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID0);
++			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID0);
++		}
++
++		RTW_INFO("[WMMPS] UAPSD MAX SP Len = 0x%02x, UAPSD TID enabled = 0x%02x\n", 
++			pqospriv->uapsd_max_sp_len, (u8)pqospriv->uapsd_tid);
++	}
++
++}
++
++/*
++ * rtw_is_wmmps_mode
++ * This function is used for checking whether Driver and an AP support uapsd function or not.
++ * If both of them support uapsd function, it will return true. Otherwise returns false.
++ * 
++ * Arguments:
++ * @padapter: _adapter pointer.
++ *
++ * Auther: Arvin Liu
++ * Date: 2017/06/12
++ */
++bool rtw_is_wmmps_mode(_adapter *padapter) 
++{
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	struct qos_priv	*pqospriv = &pmlmepriv->qospriv;
++		
++	if ((pqospriv->uapsd_ap_supported) && ((pqospriv->uapsd_tid & BIT_MASK_TID_TC)  != 0))
++		return _TRUE;
++
++	return _FALSE;
++}
++#endif /* CONFIG_WMMPS_STA */
++
++/* adjust IEs for rtw_joinbss_cmd in WMM */
++int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len)
++{
++#ifdef CONFIG_WMMPS_STA
++	struct mlme_priv		*pmlmepriv = &adapter->mlmepriv;
++	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
++#endif /* CONFIG_WMMPS_STA */
++	unsigned	int ielength = 0;
++	unsigned int i, j;
++	u8 qos_info = 0;
++
++	i = 12; /* after the fixed IE */
++	while (i < in_len) {
++		ielength = initial_out_len;
++
++		if (in_ie[i] == 0xDD && in_ie[i + 2] == 0x00 && in_ie[i + 3] == 0x50  && in_ie[i + 4] == 0xF2 && in_ie[i + 5] == 0x02 && i + 5 < in_len) { /* WMM element ID and OUI */
++
++			/* Append WMM IE to the last index of out_ie */
++#if 0
++			for (j = i; j < i + (in_ie[i + 1] + 2); j++) {
++				out_ie[ielength] = in_ie[j];
++				ielength++;
++			}
++			out_ie[initial_out_len + 8] = 0x00; /* force the QoS Info Field to be zero */
++#endif
++
++			for (j = i; j < i + 9; j++) {
++				out_ie[ielength] = in_ie[j];
++				ielength++;
++			}
++			out_ie[initial_out_len + 1] = 0x07;
++			out_ie[initial_out_len + 6] = 0x00;
++
++#ifdef CONFIG_WMMPS_STA
++			switch(pqospriv->uapsd_max_sp_len) {
++				case NO_LIMIT: 
++					/* do nothing */
++					break;
++				case TWO_MSDU: 
++					SET_FLAG(qos_info, BIT5);
++					break;
++				case FOUR_MSDU: 
++					SET_FLAG(qos_info, BIT6);
++					break;	
++				case SIX_MSDU: 
++					SET_FLAG(qos_info, BIT5);
++					SET_FLAG(qos_info, BIT6);
++					break;
++				default:
++					/* do nothing */
++					break;
++			};
++
++			/* check TID7 and TID6 for AC_VO to set corresponding Qos_info bit in WMM IE  */
++			if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID7)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID6)))
++				SET_FLAG(qos_info, WMM_IE_UAPSD_VO);
++			/* check TID5 and TID4 for AC_VI to set corresponding Qos_info bit in WMM IE  */
++			if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID5)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID4)))
++				SET_FLAG(qos_info, WMM_IE_UAPSD_VI);
++			/* check TID2 and TID1 for AC_BK to set corresponding Qos_info bit in WMM IE  */
++			if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID2)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID1)))
++				SET_FLAG(qos_info, WMM_IE_UAPSD_BK);
++			/* check TID3 and TID0 for AC_BE to set corresponding Qos_info bit in WMM IE  */
++			if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID3)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID0)))
++				SET_FLAG(qos_info, WMM_IE_UAPSD_BE);
++#endif /* CONFIG_WMMPS_STA */
++			
++			out_ie[initial_out_len + 8] = qos_info;
++
++			break;
++		}
++
++		i += (in_ie[i + 1] + 2); /* to the next IE element */
++	}
++
++	return ielength;
++
++}
++
++
++/*
++ * Ported from 8185: IsInPreAuthKeyList(). (Renamed from SecIsInPreAuthKeyList(), 2006-10-13.)
++ * Added by Annie, 2006-05-07.
++ *
++ * Search by BSSID,
++ * Return Value:
++ *		-1		:if there is no pre-auth key in the  table
++ *		>=0		:if there is pre-auth key, and   return the entry id
++ *
++ *   */
++
++static int SecIsInPMKIDList(_adapter *Adapter, u8 *bssid)
++{
++	struct security_priv *psecuritypriv = &Adapter->securitypriv;
++	int i = 0;
++
++	do {
++		if ((psecuritypriv->PMKIDList[i].bUsed) &&
++		    (_rtw_memcmp(psecuritypriv->PMKIDList[i].Bssid, bssid, ETH_ALEN) == _TRUE))
++			break;
++		else {
++			i++;
++			/* continue; */
++		}
++
++	} while (i < NUM_PMKID_CACHE);
++
++	if (i == NUM_PMKID_CACHE) {
++		i = -1;/* Could not find. */
++	} else {
++		/* There is one Pre-Authentication Key for the specific BSSID. */
++	}
++
++	return i;
++
++}
++
++int rtw_cached_pmkid(_adapter *Adapter, u8 *bssid)
++{
++	return SecIsInPMKIDList(Adapter, bssid);
++}
++
++int rtw_rsn_sync_pmkid(_adapter *adapter, u8 *ie, uint ie_len, int i_ent)
++{
++	struct security_priv *sec = &adapter->securitypriv;
++	struct rsne_info info;
++	u8 gm_cs[4];
++	int i;
++
++	rtw_rsne_info_parse(ie, ie_len, &info);
++
++	if (info.err) {
++		RTW_WARN(FUNC_ADPT_FMT" rtw_rsne_info_parse error\n"
++			, FUNC_ADPT_ARG(adapter));
++		return 0;
++	}
++
++	if (i_ent < 0 && info.pmkid_cnt == 0)
++		goto exit;
++
++	if (i_ent >= 0 && info.pmkid_cnt == 1 && _rtw_memcmp(info.pmkid_list, sec->PMKIDList[i_ent].PMKID, 16)) {
++		RTW_INFO(FUNC_ADPT_FMT" has carried the same PMKID:"KEY_FMT"\n"
++			, FUNC_ADPT_ARG(adapter), KEY_ARG(&sec->PMKIDList[i_ent].PMKID));
++		goto exit;
++	}
++
++	/* bakcup group mgmt cs */
++	if (info.gmcs)
++		_rtw_memcpy(gm_cs, info.gmcs, 4);
++
++	if (info.pmkid_cnt) {
++		RTW_INFO(FUNC_ADPT_FMT" remove original PMKID, count:%u\n"
++			 , FUNC_ADPT_ARG(adapter), info.pmkid_cnt);
++		for (i = 0; i < info.pmkid_cnt; i++)
++			RTW_INFO("    "KEY_FMT"\n", KEY_ARG(info.pmkid_list + i * 16));
++	}
++
++	if (i_ent >= 0) {
++		RTW_INFO(FUNC_ADPT_FMT" append PMKID:"KEY_FMT"\n"
++			, FUNC_ADPT_ARG(adapter), KEY_ARG(sec->PMKIDList[i_ent].PMKID));
++
++		info.pmkid_cnt = 1; /* update new pmkid_cnt */
++		_rtw_memcpy(info.pmkid_list, sec->PMKIDList[i_ent].PMKID, 16);
++	} else
++		info.pmkid_cnt = 0; /* update new pmkid_cnt */
++
++	RTW_PUT_LE16(info.pmkid_list - 2, info.pmkid_cnt);
++	if (info.gmcs)
++		_rtw_memcpy(info.pmkid_list + 16 * info.pmkid_cnt, gm_cs, 4);
++
++	ie_len = 1 + 1 + 2 + 4
++		+ 2 + 4 * info.pcs_cnt
++		+ 2 + 4 * info.akm_cnt
++		+ 2
++		+ 2 + 16 * info.pmkid_cnt
++		+ (info.gmcs ? 4 : 0)
++		;
++	
++	ie[1] = (u8)(ie_len - 2);
++
++exit:
++	return ie_len;
++}
++
++sint rtw_restruct_sec_ie(_adapter *adapter, u8 *out_ie)
++{
++	u8 authmode = 0x0;
++	uint	ielength = 0;
++	int iEntry;
++
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	struct security_priv *psecuritypriv = &adapter->securitypriv;
++	uint	ndisauthmode = psecuritypriv->ndisauthtype;
++
++	if ((ndisauthmode == Ndis802_11AuthModeWPA) || (ndisauthmode == Ndis802_11AuthModeWPAPSK))
++		authmode = _WPA_IE_ID_;
++	if ((ndisauthmode == Ndis802_11AuthModeWPA2) || (ndisauthmode == Ndis802_11AuthModeWPA2PSK))
++		authmode = _WPA2_IE_ID_;
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
++		_rtw_memcpy(out_ie, psecuritypriv->wps_ie, psecuritypriv->wps_ie_len);
++		ielength = psecuritypriv->wps_ie_len;
++
++	} else if ((authmode == _WPA_IE_ID_) || (authmode == _WPA2_IE_ID_)) {
++		/* copy RSN or SSN		 */
++		_rtw_memcpy(out_ie, psecuritypriv->supplicant_ie, psecuritypriv->supplicant_ie[1] + 2);
++		/* debug for CONFIG_IEEE80211W
++		{
++			int jj;
++			printk("supplicant_ie_length=%d &&&&&&&&&&&&&&&&&&&\n", psecuritypriv->supplicant_ie[1]+2);
++			for(jj=0; jj < psecuritypriv->supplicant_ie[1]+2; jj++)
++				printk(" %02x ", psecuritypriv->supplicant_ie[jj]);
++			printk("\n");
++		}*/
++		ielength = psecuritypriv->supplicant_ie[1] + 2;
++		rtw_report_sec_ie(adapter, authmode, psecuritypriv->supplicant_ie);
++	}
++
++	if (authmode == WLAN_EID_RSN) {
++		iEntry = SecIsInPMKIDList(adapter, pmlmepriv->assoc_bssid);
++		ielength = rtw_rsn_sync_pmkid(adapter, out_ie, ielength, iEntry);
++	}
++
++	return ielength;
++}
++
++void rtw_init_registrypriv_dev_network(_adapter *adapter)
++{
++	struct registry_priv *pregistrypriv = &adapter->registrypriv;
++	WLAN_BSSID_EX    *pdev_network = &pregistrypriv->dev_network;
++	u8 *myhwaddr = adapter_mac_addr(adapter);
++
++
++	_rtw_memcpy(pdev_network->MacAddress, myhwaddr, ETH_ALEN);
++
++	_rtw_memcpy(&pdev_network->Ssid, &pregistrypriv->ssid, sizeof(NDIS_802_11_SSID));
++
++	pdev_network->Configuration.Length = sizeof(NDIS_802_11_CONFIGURATION);
++	pdev_network->Configuration.BeaconPeriod = 100;
++}
++
++void rtw_update_registrypriv_dev_network(_adapter *adapter)
++{
++	int sz = 0;
++	struct registry_priv *pregistrypriv = &adapter->registrypriv;
++	WLAN_BSSID_EX    *pdev_network = &pregistrypriv->dev_network;
++	struct	security_priv	*psecuritypriv = &adapter->securitypriv;
++	struct	wlan_network	*cur_network = &adapter->mlmepriv.cur_network;
++	/* struct	xmit_priv	*pxmitpriv = &adapter->xmitpriv; */
++	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
++
++
++#if 0
++	pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense;
++	pxmitpriv->vcs = pregistrypriv->vcs_type;
++	pxmitpriv->vcs_type = pregistrypriv->vcs_type;
++	/* pxmitpriv->rts_thresh = pregistrypriv->rts_thresh; */
++	pxmitpriv->frag_len = pregistrypriv->frag_thresh;
++
++	adapter->qospriv.qos_option = pregistrypriv->wmm_enable;
++#endif
++
++	pdev_network->Privacy = (psecuritypriv->dot11PrivacyAlgrthm > 0 ? 1 : 0) ; /* adhoc no 802.1x */
++
++	pdev_network->Rssi = 0;
++
++	pdev_network->Configuration.DSConfig = (pregistrypriv->channel);
++
++	if (cur_network->network.InfrastructureMode == Ndis802_11IBSS) {
++		pdev_network->Configuration.ATIMWindow = (0);
++
++		if (pmlmeext->cur_channel != 0)
++			pdev_network->Configuration.DSConfig = pmlmeext->cur_channel;
++		else
++			pdev_network->Configuration.DSConfig = 1;
++	}
++
++	pdev_network->InfrastructureMode = (cur_network->network.InfrastructureMode);
++
++	/* 1. Supported rates */
++	/* 2. IE */
++
++	/* rtw_set_supported_rate(pdev_network->SupportedRates, pregistrypriv->wireless_mode) ; */ /* will be called in rtw_generate_ie */
++	sz = rtw_generate_ie(pregistrypriv);
++
++	pdev_network->IELength = sz;
++
++	pdev_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pdev_network);
++
++	/* notes: translate IELength & Length after assign the Length to cmdsz in createbss_cmd(); */
++	/* pdev_network->IELength = cpu_to_le32(sz); */
++
++
++}
++
++void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter)
++{
++
++
++
++}
++
++/* the fucntion is at passive_level */
++void rtw_joinbss_reset(_adapter *padapter)
++{
++	u8	threshold;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	/* todo: if you want to do something io/reg/hw setting before join_bss, please add code here */
++
++#ifdef CONFIG_80211N_HT
++	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
++
++	pmlmepriv->num_FortyMHzIntolerant = 0;
++
++	pmlmepriv->num_sta_no_ht = 0;
++
++	phtpriv->ampdu_enable = _FALSE;/* reset to disabled */
++
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
++	/* TH=1 => means that invalidate usb rx aggregation */
++	/* TH=0 => means that validate usb rx aggregation, use init value. */
++	if (phtpriv->ht_option) {
++		if (padapter->registrypriv.wifi_spec == 1)
++			threshold = 1;
++		else
++			threshold = 0;
++		rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
++	} else {
++		threshold = 1;
++		rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
++	}
++#endif/* #if defined( CONFIG_USB_HCI) || defined (CONFIG_SDIO_HCI) */
++
++#endif/* #ifdef CONFIG_80211N_HT */
++
++}
++
++
++#ifdef CONFIG_80211N_HT
++void	rtw_ht_use_default_setting(_adapter *padapter)
++{
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
++	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
++	BOOLEAN		bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE;
++#ifdef CONFIG_BEAMFORMING
++	BOOLEAN		bHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE;
++#endif /* CONFIG_BEAMFORMING */
++
++	if (pregistrypriv->wifi_spec)
++		phtpriv->bss_coexist = 1;
++	else
++		phtpriv->bss_coexist = 0;
++
++	phtpriv->sgi_40m = TEST_FLAG(pregistrypriv->short_gi, BIT1) ? _TRUE : _FALSE;
++	phtpriv->sgi_20m = TEST_FLAG(pregistrypriv->short_gi, BIT0) ? _TRUE : _FALSE;
++
++	/* LDPC support */
++	rtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport);
++	CLEAR_FLAGS(phtpriv->ldpc_cap);
++	if (bHwLDPCSupport) {
++		if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT4))
++			SET_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX);
++	}
++	rtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport);
++	if (bHwLDPCSupport) {
++		if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT5))
++			SET_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX);
++	}
++	if (phtpriv->ldpc_cap)
++		RTW_INFO("[HT] HAL Support LDPC = 0x%02X\n", phtpriv->ldpc_cap);
++
++	/* STBC */
++	rtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport);
++	CLEAR_FLAGS(phtpriv->stbc_cap);
++	if (bHwSTBCSupport) {
++		if (TEST_FLAG(pregistrypriv->stbc_cap, BIT5))
++			SET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX);
++	}
++	rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport);
++	if (bHwSTBCSupport) {
++		if (TEST_FLAG(pregistrypriv->stbc_cap, BIT4))
++			SET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX);
++	}
++	if (phtpriv->stbc_cap)
++		RTW_INFO("[HT] HAL Support STBC = 0x%02X\n", phtpriv->stbc_cap);
++
++	/* Beamforming setting */
++	CLEAR_FLAGS(phtpriv->beamform_cap);
++#ifdef CONFIG_BEAMFORMING
++#ifdef RTW_BEAMFORMING_VERSION_2
++	/* only enable beamforming in STA client mode */
++	if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter)
++				  && !MLME_IS_ADHOC(padapter)
++				  && !MLME_IS_MESH(padapter))
++#endif
++	{
++		rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer);
++		rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee);
++		if (TEST_FLAG(pregistrypriv->beamform_cap, BIT4) && bHwSupportBeamformer) {
++			SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
++			RTW_INFO("[HT] HAL Support Beamformer\n");
++		}
++		if (TEST_FLAG(pregistrypriv->beamform_cap, BIT5) && bHwSupportBeamformee) {
++			SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
++			RTW_INFO("[HT] HAL Support Beamformee\n");
++		}
++	}
++#endif /* CONFIG_BEAMFORMING */
++}
++void rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len)
++{
++	unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00};
++	int out_len;
++	u8 *pframe;
++
++	if (padapter->mlmepriv.qospriv.qos_option == 0) {
++		out_len = *pout_len;
++		pframe = rtw_set_ie(out_ie + out_len, _VENDOR_SPECIFIC_IE_,
++				    _WMM_IE_Length_, WMM_IE, pout_len);
++
++		padapter->mlmepriv.qospriv.qos_option = 1;
++	}
++}
++#if defined(CONFIG_80211N_HT)
++/* the fucntion is >= passive_level */
++unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel)
++{
++	u32 ielen, out_len;
++	u32 rx_packet_offset, max_recvbuf_sz;
++	HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor;
++	HT_CAP_AMPDU_DENSITY best_ampdu_density;
++	unsigned char *p, *pframe;
++	struct rtw_ieee80211_ht_cap ht_capie;
++	u8	cbw40_enable = 0, rf_num = 0, rx_stbc_nss = 0, rx_nss = 0;
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++#ifdef CONFIG_80211AC_VHT
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct vht_priv	*pvhtpriv = &pmlmepriv->vhtpriv;
++#endif /* CONFIG_80211AC_VHT */
++
++	phtpriv->ht_option = _FALSE;
++
++	out_len = *pout_len;
++
++	_rtw_memset(&ht_capie, 0, sizeof(struct rtw_ieee80211_ht_cap));
++
++	ht_capie.cap_info = IEEE80211_HT_CAP_DSSSCCK40;
++
++	if (phtpriv->sgi_20m)
++		ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_20;
++
++	/* check if 40MHz is allowed according to hal cap and registry */
++	if (hal_chk_bw_cap(padapter, BW_CAP_40M)) {
++		if (channel > 14) {
++			if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
++				cbw40_enable = 1;
++		} else {
++			if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
++				cbw40_enable = 1;
++		}
++	}
++
++	if (cbw40_enable) {
++		struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++		RT_CHANNEL_INFO *chset = rfctl->channel_set;
++		u8 oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++		if (in_ie == NULL) {
++			/* TDLS: TODO 20/40 issue */
++			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
++				oper_bw = padapter->mlmeextpriv.cur_bwmode;
++				if (oper_bw > CHANNEL_WIDTH_40)
++					oper_bw = CHANNEL_WIDTH_40;
++			} else
++				/* TDLS: TODO 40? */
++				oper_bw = CHANNEL_WIDTH_40;
++		} else {
++			p = rtw_get_ie(in_ie, WLAN_EID_HT_OPERATION, &ielen, in_len);
++			if (p && ielen == HT_OP_IE_LEN) {
++				if (GET_HT_OP_ELE_STA_CHL_WIDTH(p + 2)) {
++					switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(p + 2)) {
++					case SCA:
++						oper_bw = CHANNEL_WIDTH_40;
++						oper_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++						break;
++					case SCB:
++						oper_bw = CHANNEL_WIDTH_40;
++						oper_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++						break;
++					}
++				}
++			}
++			// IOT issue : AP TP-Link WDR6500
++			if(oper_bw == CHANNEL_WIDTH_40){ 
++				p = rtw_get_ie(in_ie, WLAN_EID_HT_CAP, &ielen, in_len);
++				if (p && ielen == HT_CAP_IE_LEN) {
++					oper_bw = GET_HT_CAP_ELE_CHL_WIDTH(p + 2)  ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20;
++					if(oper_bw == CHANNEL_WIDTH_20)
++						oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++				}
++			}
++		}
++
++		/* adjust bw to fit in channel plan setting */
++		if (oper_bw == CHANNEL_WIDTH_40
++			&& oper_offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE /* check this because TDLS has no info to set offset */
++			&& (!rtw_chset_is_chbw_valid(chset, channel, oper_bw, oper_offset, 1, 1)
++				|| (IS_DFS_SLAVE_WITH_RD(rfctl)
++					&& !rtw_rfctl_dfs_domain_unknown(rfctl)
++					&& rtw_chset_is_chbw_non_ocp(chset, channel, oper_bw, oper_offset))
++				)
++		) {
++			oper_bw = CHANNEL_WIDTH_20;
++			oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++			rtw_warn_on(!rtw_chset_is_chbw_valid(chset, channel, oper_bw, oper_offset, 1, 1));
++			if (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_rfctl_dfs_domain_unknown(rfctl))
++				rtw_warn_on(rtw_chset_is_chbw_non_ocp(chset, channel, oper_bw, oper_offset));
++		}
++
++		if (oper_bw == CHANNEL_WIDTH_40) {
++			ht_capie.cap_info |= IEEE80211_HT_CAP_SUP_WIDTH;
++			if (phtpriv->sgi_40m)
++				ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_40;
++		}
++
++		cbw40_enable = oper_bw == CHANNEL_WIDTH_40 ? 1 : 0;
++	}
++
++	/* todo: disable SM power save mode */
++	ht_capie.cap_info |= IEEE80211_HT_CAP_SM_PS;
++
++	/* RX LDPC */
++	if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX)) {
++		ht_capie.cap_info |= IEEE80211_HT_CAP_LDPC_CODING;
++		RTW_INFO("[HT] Declare supporting RX LDPC\n");
++	}
++
++	/* TX STBC */
++	if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX)) {
++		ht_capie.cap_info |= IEEE80211_HT_CAP_TX_STBC;
++		RTW_INFO("[HT] Declare supporting TX STBC\n");
++	}
++
++	/* RX STBC */
++	if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) {
++		if ((pregistrypriv->rx_stbc == 0x3) ||							/* enable for 2.4/5 GHz */
++		    ((channel <= 14) && (pregistrypriv->rx_stbc == 0x1)) ||		/* enable for 2.4GHz */
++		    ((channel > 14) && (pregistrypriv->rx_stbc == 0x2)) ||		/* enable for 5GHz */
++		    (pregistrypriv->wifi_spec == 1)) {
++			/* HAL_DEF_RX_STBC means STBC RX spatial stream, todo: VHT 4 streams */
++			rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss));
++			SET_HT_CAP_ELE_RX_STBC(&ht_capie, rx_stbc_nss);
++			RTW_INFO("[HT] Declare supporting RX STBC = %d\n", rx_stbc_nss);
++		}
++	}
++
++	/* fill default supported_mcs_set */
++	_rtw_memcpy(ht_capie.supp_mcs_set, pmlmeext->default_supported_mcs_set, 16);
++
++	/* update default supported_mcs_set */
++	rx_nss = GET_HAL_RX_NSS(padapter);
++
++	switch (rx_nss) {
++	case 1:
++		set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_1R);
++		break;
++	case 2:
++		#ifdef CONFIG_DISABLE_MCS13TO15
++		if (cbw40_enable && pregistrypriv->wifi_spec != 1)
++			set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R_13TO15_OFF);
++		else
++		#endif
++			set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R);
++		break;
++	case 3:
++		set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_3R);
++		break;
++	case 4:
++		set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_4R);
++		break;
++	default:
++		RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", GET_HAL_RFPATH(padapter), rx_nss);
++	}
++
++	{
++		rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset);
++		rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz);
++		if (max_recvbuf_sz - rx_packet_offset >= (8191 - 256)) {
++			RTW_INFO("%s IEEE80211_HT_CAP_MAX_AMSDU is set\n", __FUNCTION__);
++			ht_capie.cap_info = ht_capie.cap_info | IEEE80211_HT_CAP_MAX_AMSDU;
++		}
++	}
++	/*
++	AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k
++	AMPDU_para [4:2]:Min MPDU Start Spacing
++	*/
++
++	/*
++	#if defined(CONFIG_RTL8188E) && defined(CONFIG_SDIO_HCI)
++	ht_capie.ampdu_params_info = 2;
++	#else
++	ht_capie.ampdu_params_info = (IEEE80211_HT_CAP_AMPDU_FACTOR&0x03);
++	#endif
++	*/
++
++	if (padapter->driver_rx_ampdu_factor != 0xFF)
++		max_rx_ampdu_factor = (HT_CAP_AMPDU_FACTOR)padapter->driver_rx_ampdu_factor;
++	else
++		rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor);
++
++	/* rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); */
++	ht_capie.ampdu_params_info = (max_rx_ampdu_factor & 0x03);
++
++	if (padapter->driver_rx_ampdu_spacing != 0xFF)
++		ht_capie.ampdu_params_info |= ((padapter->driver_rx_ampdu_spacing & 0x07) << 2);
++	else {
++		if (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_) {
++			/*
++			*	Todo : Each chip must to ask DD , this chip best ampdu_density setting
++			*	By yiwei.sun
++			*/
++			rtw_hal_get_def_var(padapter, HW_VAR_BEST_AMPDU_DENSITY, &best_ampdu_density);
++
++			ht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & (best_ampdu_density << 2));
++
++		} else
++			ht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & 0x00);
++	}
++#ifdef CONFIG_BEAMFORMING
++	ht_capie.tx_BF_cap_info = 0;
++
++	/* HT Beamformer*/
++	if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {
++		/* Transmit NDP Capable */
++		SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(&ht_capie, 1);
++		/* Explicit Compressed Steering Capable */
++		SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(&ht_capie, 1);
++		/* Compressed Steering Number Antennas */
++		SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(&ht_capie, 1);
++		rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num);
++		SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(&ht_capie, rf_num);
++	}
++
++	/* HT Beamformee */
++	if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) {
++		/* Receive NDP Capable */
++		SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(&ht_capie, 1);
++		/* Explicit Compressed Beamforming Feedback Capable */
++		SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(&ht_capie, 2);
++
++		rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);
++#ifdef CONFIG_80211AC_VHT
++		/* IOT action suggested by Yu Chen 2017/3/3 */
++		if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) &&
++			!pvhtpriv->ap_bf_cap.is_mu_bfer &&
++			pvhtpriv->ap_bf_cap.su_sound_dim == 2)
++			rf_num = (rf_num >= 2 ? 2 : rf_num);
++#endif
++		SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(&ht_capie, rf_num);
++	}
++#endif/*CONFIG_BEAMFORMING*/
++
++	pframe = rtw_set_ie(out_ie + out_len, _HT_CAPABILITY_IE_,
++		sizeof(struct rtw_ieee80211_ht_cap), (unsigned char *)&ht_capie, pout_len);
++
++	phtpriv->ht_option = _TRUE;
++
++	if (in_ie != NULL) {
++		p = rtw_get_ie(in_ie, _HT_ADD_INFO_IE_, &ielen, in_len);
++		if (p && (ielen == sizeof(struct ieee80211_ht_addt_info))) {
++			out_len = *pout_len;
++			pframe = rtw_set_ie(out_ie + out_len, _HT_ADD_INFO_IE_, ielen, p + 2 , pout_len);
++		}
++	}
++
++	return phtpriv->ht_option;
++
++}
++
++/* the fucntion is > passive_level (in critical_section) */
++void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel)
++{
++	u8 *p, max_ampdu_sz;
++	int len;
++	/* struct sta_info *bmc_sta, *psta; */
++	struct rtw_ieee80211_ht_cap *pht_capie;
++	struct ieee80211_ht_addt_info *pht_addtinfo;
++	/* struct recv_reorder_ctrl *preorder_ctrl; */
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
++	/* struct recv_priv *precvpriv = &padapter->recvpriv; */
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++	/* struct wlan_network *pcur_network = &(pmlmepriv->cur_network);; */
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8 cbw40_enable = 0;
++
++
++	if (!phtpriv->ht_option)
++		return;
++
++	if ((!pmlmeinfo->HT_info_enable) || (!pmlmeinfo->HT_caps_enable))
++		return;
++
++	RTW_INFO("+rtw_update_ht_cap()\n");
++
++	/* maybe needs check if ap supports rx ampdu. */
++	if ((phtpriv->ampdu_enable == _FALSE) && (pregistrypriv->ampdu_enable == 1)) {
++		if (pregistrypriv->wifi_spec == 1) {
++			/* remove this part because testbed AP should disable RX AMPDU */
++			/* phtpriv->ampdu_enable = _FALSE; */
++			phtpriv->ampdu_enable = _TRUE;
++		} else
++			phtpriv->ampdu_enable = _TRUE;
++	} 
++
++
++	/* check Max Rx A-MPDU Size */
++	len = 0;
++	p = rtw_get_ie(pie + sizeof(NDIS_802_11_FIXED_IEs), _HT_CAPABILITY_IE_, &len, ie_len - sizeof(NDIS_802_11_FIXED_IEs));
++	if (p && len > 0) {
++		pht_capie = (struct rtw_ieee80211_ht_cap *)(p + 2);
++		max_ampdu_sz = (pht_capie->ampdu_params_info & IEEE80211_HT_CAP_AMPDU_FACTOR);
++		max_ampdu_sz = 1 << (max_ampdu_sz + 3); /* max_ampdu_sz (kbytes); */
++
++		/* RTW_INFO("rtw_update_ht_cap(): max_ampdu_sz=%d\n", max_ampdu_sz); */
++		phtpriv->rx_ampdu_maxlen = max_ampdu_sz;
++
++	}
++
++
++	len = 0;
++	p = rtw_get_ie(pie + sizeof(NDIS_802_11_FIXED_IEs), _HT_ADD_INFO_IE_, &len, ie_len - sizeof(NDIS_802_11_FIXED_IEs));
++	if (p && len > 0) {
++		pht_addtinfo = (struct ieee80211_ht_addt_info *)(p + 2);
++		/* todo: */
++	}
++
++	if (hal_chk_bw_cap(padapter, BW_CAP_40M)) {
++		if (channel > 14) {
++			if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
++				cbw40_enable = 1;
++		} else {
++			if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
++				cbw40_enable = 1;
++		}
++	}
++
++	/* update cur_bwmode & cur_ch_offset */
++	if ((cbw40_enable) &&
++	    (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) &&
++	    (pmlmeinfo->HT_info.infos[0] & BIT(2))) {
++		int i;
++		u8 rx_nss = 0;
++
++		rx_nss = GET_HAL_RX_NSS(padapter);
++
++		/* update the MCS set */
++		for (i = 0; i < 16; i++)
++			pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i];
++
++		/* update the MCS rates */
++		switch (rx_nss) {
++		case 1:
++			set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R);
++			break;
++		case 2:
++			#ifdef CONFIG_DISABLE_MCS13TO15
++			if (pmlmeext->cur_bwmode == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1)
++				set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R_13TO15_OFF);
++			else
++			#endif
++				set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R);
++			break;
++		case 3:
++			set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R);
++			break;
++		case 4:
++			set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_4R);
++			break;
++		default:
++			RTW_WARN("rx_nss:%u is not expected\n", rx_nss);
++		}
++
++		/* switch to the 40M Hz mode accoring to the AP */
++		/* pmlmeext->cur_bwmode = CHANNEL_WIDTH_40; */
++		switch ((pmlmeinfo->HT_info.infos[0] & 0x3)) {
++		case EXTCHNL_OFFSET_UPPER:
++			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++			break;
++
++		case EXTCHNL_OFFSET_LOWER:
++			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++			break;
++
++		default:
++			pmlmeext->cur_bwmode = CHANNEL_WIDTH_20;
++			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++			RTW_INFO("%s : ch offset is not assigned for HT40 mod , update cur_bwmode=%u, cur_ch_offset=%u\n", 
++					__func__, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
++			break;
++		}
++	}
++
++	/*  */
++	/* Config SM Power Save setting */
++	/*  */
++	pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2;
++	if (pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) {
++#if 0
++		u8 i;
++		/* update the MCS rates */
++		for (i = 0; i < 16; i++)
++			pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
++#endif
++		RTW_INFO("%s(): WLAN_HT_CAP_SM_PS_STATIC\n", __FUNCTION__);
++	}
++
++	/*  */
++	/* Config current HT Protection mode. */
++	/*  */
++	pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3;
++}
++#endif
++
++#ifdef CONFIG_TDLS
++void rtw_issue_addbareq_cmd_tdls(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++	struct pkt_attrib *pattrib = &pxmitframe->attrib;
++	struct sta_info *ptdls_sta = NULL;
++	u8 issued;
++	int priority;
++	struct ht_priv	*phtpriv;
++
++	priority = pattrib->priority;
++
++	if (pattrib->direct_link == _TRUE) {
++		ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst);
++		if ((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) {
++			phtpriv = &ptdls_sta->htpriv;
++
++			if ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) {
++				issued = (phtpriv->agg_enable_bitmap >> priority) & 0x1;
++				issued |= (phtpriv->candidate_tid_bitmap >> priority) & 0x1;
++
++				if (0 == issued) {
++					RTW_INFO("[%s], p=%d\n", __FUNCTION__, priority);
++					ptdls_sta->htpriv.candidate_tid_bitmap |= BIT((u8)priority);
++					rtw_addbareq_cmd(padapter, (u8)priority, pattrib->dst);
++				}
++			}
++		}
++	}
++}
++#endif /* CONFIG_TDLS */
++
++#ifdef CONFIG_80211N_HT
++static u8 rtw_issue_addbareq_check(_adapter *padapter, struct xmit_frame *pxmitframe, u8 issue_when_busy)
++{
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct registry_priv *pregistry = &padapter->registrypriv;
++	struct pkt_attrib *pattrib = &pxmitframe->attrib;
++	s32 bmcst = IS_MCAST(pattrib->ra);
++
++	if (bmcst)
++		return _FALSE;
++
++	if (pregistry->tx_quick_addba_req == 0) {
++		if ((issue_when_busy == _TRUE) && (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE))
++			return _FALSE;
++
++		if (pmlmepriv->LinkDetectInfo.NumTxOkInPeriod < 100)
++			return _FALSE;
++	}
++
++	return _TRUE;
++}
++
++void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe, u8 issue_when_busy)
++{
++	u8 issued;
++	int priority;
++	struct sta_info *psta = NULL;
++	struct ht_priv	*phtpriv;
++	struct pkt_attrib *pattrib = &pxmitframe->attrib;
++
++	if (rtw_issue_addbareq_check(padapter,pxmitframe, issue_when_busy) == _FALSE)
++		return;
++
++	priority = pattrib->priority;
++
++#ifdef CONFIG_TDLS
++	rtw_issue_addbareq_cmd_tdls(padapter, pxmitframe);
++#endif /* CONFIG_TDLS */
++
++	psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
++	if (pattrib->psta != psta) {
++		RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
++		return;
++	}
++
++	if (psta == NULL) {
++		RTW_INFO("%s, psta==NUL\n", __func__);
++		return;
++	}
++
++	if (!(psta->state & WIFI_ASOC_STATE)) {
++		RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
++		return;
++	}
++
++
++	phtpriv = &psta->htpriv;
++
++	if ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) {
++		issued = (phtpriv->agg_enable_bitmap >> priority) & 0x1;
++		issued |= (phtpriv->candidate_tid_bitmap >> priority) & 0x1;
++
++		if (0 == issued) {
++			RTW_INFO("rtw_issue_addbareq_cmd, p=%d\n", priority);
++			psta->htpriv.candidate_tid_bitmap |= BIT((u8)priority);
++			rtw_addbareq_cmd(padapter, (u8) priority, pattrib->ra);
++		}
++	}
++
++}
++#endif /* CONFIG_80211N_HT */
++void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len)
++{
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
++#ifdef CONFIG_80211AC_VHT
++	struct vht_priv	*pvhtpriv = &pmlmepriv->vhtpriv;
++#endif /* CONFIG_80211AC_VHT */
++	u8	cap_content[8] = { 0 };
++	u8	*pframe;
++	u8   null_content[8] = {0};
++
++	if (phtpriv->bss_coexist)
++		SET_EXT_CAPABILITY_ELE_BSS_COEXIST(cap_content, 1);
++
++#ifdef CONFIG_80211AC_VHT
++	if (pvhtpriv->vht_option)
++		SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(cap_content, 1);
++#endif /* CONFIG_80211AC_VHT */
++#ifdef CONFIG_RTW_WNM
++	rtw_wnm_set_ext_cap_btm(cap_content, 1);
++#endif
++
++#ifdef CONFIG_RTW_MBO
++	rtw_mbo_set_ext_cap_internw(cap_content, 1);
++#endif
++	/*
++		From 802.11 specification,if a STA does not support any of capabilities defined
++		in the Extended Capabilities element, then the STA is not required to
++		transmit the Extended Capabilities element.
++	*/
++	if (_FALSE == _rtw_memcmp(cap_content, null_content, 8))
++		pframe = rtw_set_ie(out_ie + *pout_len, EID_EXTCapability, 8, cap_content , pout_len);
++}
++#endif
++
++#ifdef CONFIG_LAYER2_ROAMING
++inline void rtw_set_to_roam(_adapter *adapter, u8 to_roam)
++{
++	if (to_roam == 0)
++		adapter->mlmepriv.to_join = _FALSE;
++	adapter->mlmepriv.to_roam = to_roam;
++}
++
++inline u8 rtw_dec_to_roam(_adapter *adapter)
++{
++	adapter->mlmepriv.to_roam--;
++	return adapter->mlmepriv.to_roam;
++}
++
++inline u8 rtw_to_roam(_adapter *adapter)
++{
++	return adapter->mlmepriv.to_roam;
++}
++
++void rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network)
++{
++	_irqL irqL;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++	_rtw_roaming(padapter, tgt_network);
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++}
++void _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network)
++{
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct wlan_network *cur_network = &pmlmepriv->cur_network;
++	int do_join_r;
++
++	if (0 < rtw_to_roam(padapter)) {
++		RTW_INFO("roaming from %s("MAC_FMT"), length:%d\n",
++			cur_network->network.Ssid.Ssid, MAC_ARG(cur_network->network.MacAddress),
++			 cur_network->network.Ssid.SsidLength);
++		_rtw_memcpy(&pmlmepriv->assoc_ssid, &cur_network->network.Ssid, sizeof(NDIS_802_11_SSID));
++		pmlmepriv->assoc_ch = 0;
++		pmlmepriv->assoc_by_bssid = _FALSE;
++
++#ifdef CONFIG_WAPI_SUPPORT
++		rtw_wapi_return_all_sta_info(padapter);
++#endif
++
++		while (1) {
++			do_join_r = rtw_do_join(padapter);
++			if (_SUCCESS == do_join_r)
++				break;
++			else {
++				RTW_INFO("roaming do_join return %d\n", do_join_r);
++				rtw_dec_to_roam(padapter);
++
++				if (rtw_to_roam(padapter) > 0)
++					continue;
++				else {
++					RTW_INFO("%s(%d) -to roaming fail, indicate_disconnect\n", __FUNCTION__, __LINE__);
++#ifdef CONFIG_RTW_80211R
++					rtw_ft_clr_flags(padapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN);
++					rtw_ft_reset_status(padapter);
++#endif
++					rtw_indicate_disconnect(padapter, 0, _FALSE);
++					break;
++				}
++			}
++		}
++	}
++
++}
++#endif /* CONFIG_LAYER2_ROAMING */
++
++bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset)
++{
++	struct registry_priv *regsty = adapter_to_regsty(adapter);
++	u8 allowed_bw;
++
++	if (req_ch < 14)
++		allowed_bw = REGSTY_BW_2G(regsty);
++	else if (req_ch == 14)
++		allowed_bw = CHANNEL_WIDTH_20;
++	else
++		allowed_bw = REGSTY_BW_5G(regsty);
++
++	allowed_bw = hal_largest_bw(adapter, allowed_bw);
++
++	if (allowed_bw == CHANNEL_WIDTH_80 && *req_bw > CHANNEL_WIDTH_80)
++		*req_bw = CHANNEL_WIDTH_80;
++	else if (allowed_bw == CHANNEL_WIDTH_40 && *req_bw > CHANNEL_WIDTH_40)
++		*req_bw = CHANNEL_WIDTH_40;
++	else if (allowed_bw == CHANNEL_WIDTH_20 && *req_bw > CHANNEL_WIDTH_20) {
++		*req_bw = CHANNEL_WIDTH_20;
++		*req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++	} else
++		return _FALSE;
++
++	return _TRUE;
++}
++
++sint rtw_linked_check(_adapter *padapter)
++{
++	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)
++		|| MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter)
++	) {
++		if (padapter->stapriv.asoc_sta_count > 2)
++			return _TRUE;
++	} else {
++		/* Station mode */
++		if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE)
++			return _TRUE;
++	}
++	return _FALSE;
++}
++/*#define DBG_ADAPTER_STATE_CHK*/
++u8 rtw_is_adapter_up(_adapter *padapter)
++{
++	if (padapter == NULL)
++		return _FALSE;
++
++	if (RTW_CANNOT_RUN(padapter)) {
++		#ifdef DBG_ADAPTER_STATE_CHK
++		RTW_INFO(FUNC_ADPT_FMT " FALSE -bDriverStopped(%s) bSurpriseRemoved(%s)\n"
++			, FUNC_ADPT_ARG(padapter)
++			, rtw_is_drv_stopped(padapter) ? "True" : "False"
++			, rtw_is_surprise_removed(padapter) ? "True" : "False");
++		#endif
++		return _FALSE;
++	}
++
++	if (!rtw_is_hw_init_completed(padapter)) {
++		#ifdef DBG_ADAPTER_STATE_CHK
++		RTW_INFO(FUNC_ADPT_FMT " FALSE -(hw_init_completed == _FALSE)\n", FUNC_ADPT_ARG(padapter));
++		#endif
++		return _FALSE;
++	}
++
++	if (padapter->bup == _FALSE) {
++		#ifdef DBG_ADAPTER_STATE_CHK
++		RTW_INFO(FUNC_ADPT_FMT " FALSE -(bup == _FALSE)\n", FUNC_ADPT_ARG(padapter));
++		#endif
++		return _FALSE;
++	}
++
++	return _TRUE;
++}
++
++bool is_miracast_enabled(_adapter *adapter)
++{
++	bool enabled = 0;
++#ifdef CONFIG_WFD
++	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
++
++	enabled = (wfdinfo->stack_wfd_mode & (MIRACAST_SOURCE | MIRACAST_SINK))
++		  || (wfdinfo->op_wfd_mode & (MIRACAST_SOURCE | MIRACAST_SINK));
++#endif
++
++	return enabled;
++}
++
++bool rtw_chk_miracast_mode(_adapter *adapter, u8 mode)
++{
++	bool ret = 0;
++#ifdef CONFIG_WFD
++	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
++
++	ret = (wfdinfo->stack_wfd_mode & mode) || (wfdinfo->op_wfd_mode & mode);
++#endif
++
++	return ret;
++}
++
++const char *get_miracast_mode_str(int mode)
++{
++	if (mode == MIRACAST_SOURCE)
++		return "SOURCE";
++	else if (mode == MIRACAST_SINK)
++		return "SINK";
++	else if (mode == (MIRACAST_SOURCE | MIRACAST_SINK))
++		return "SOURCE&SINK";
++	else if (mode == MIRACAST_DISABLED)
++		return "DISABLED";
++	else
++		return "INVALID";
++}
++
++#ifdef CONFIG_WFD
++static bool wfd_st_match_rule(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
++{
++	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
++
++	if (ntohs(*((u16 *)local_port)) == wfdinfo->rtsp_ctrlport
++	    || ntohs(*((u16 *)local_port)) == wfdinfo->tdls_rtsp_ctrlport
++	    || ntohs(*((u16 *)remote_port)) == wfdinfo->peer_rtsp_ctrlport)
++		return _TRUE;
++	return _FALSE;
++}
++
++static struct st_register wfd_st_reg = {
++	.s_proto = 0x06,
++	.rule = wfd_st_match_rule,
++};
++#endif /* CONFIG_WFD */
++
++inline void rtw_wfd_st_switch(struct sta_info *sta, bool on)
++{
++#ifdef CONFIG_WFD
++	if (on)
++		rtw_st_ctl_register(&sta->st_ctl, SESSION_TRACKER_REG_ID_WFD, &wfd_st_reg);
++	else
++		rtw_st_ctl_unregister(&sta->st_ctl, SESSION_TRACKER_REG_ID_WFD);
++#endif
++}
++
++void dump_arp_pkt(void *sel, u8 *da, u8 *sa, u8 *arp, bool tx)
++{
++	RTW_PRINT_SEL(sel, "%s ARP da="MAC_FMT", sa="MAC_FMT"\n"
++		, tx ? "send" : "recv", MAC_ARG(da), MAC_ARG(sa));
++	RTW_PRINT_SEL(sel, "htype=%u, ptype=0x%04x, hlen=%u, plen=%u, oper=%u\n"
++		, GET_ARP_HTYPE(arp), GET_ARP_PTYPE(arp), GET_ARP_HLEN(arp)
++		, GET_ARP_PLEN(arp), GET_ARP_OPER(arp));
++	RTW_PRINT_SEL(sel, "sha="MAC_FMT", spa="IP_FMT"\n"
++		, MAC_ARG(ARP_SENDER_MAC_ADDR(arp)), IP_ARG(ARP_SENDER_IP_ADDR(arp)));
++	RTW_PRINT_SEL(sel, "tha="MAC_FMT", tpa="IP_FMT"\n"
++		, MAC_ARG(ARP_TARGET_MAC_ADDR(arp)), IP_ARG(ARP_TARGET_IP_ADDR(arp)));
++}
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mlme_ext.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mlme_ext.c
+new file mode 100755
+index 000000000..eb923cb62
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mlme_ext.c
+@@ -0,0 +1,16111 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_MLME_EXT_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++struct mlme_handler mlme_sta_tbl[] = {
++	{WIFI_ASSOCREQ,		"OnAssocReq",	&OnAssocReq},
++	{WIFI_ASSOCRSP,		"OnAssocRsp",	&OnAssocRsp},
++	{WIFI_REASSOCREQ,	"OnReAssocReq",	&OnAssocReq},
++	{WIFI_REASSOCRSP,	"OnReAssocRsp",	&OnAssocRsp},
++	{WIFI_PROBEREQ,		"OnProbeReq",	&OnProbeReq},
++	{WIFI_PROBERSP,		"OnProbeRsp",		&OnProbeRsp},
++
++	/*----------------------------------------------------------
++					below 2 are reserved
++	-----------------------------------------------------------*/
++	{0,					"DoReserved",		&DoReserved},
++	{0,					"DoReserved",		&DoReserved},
++	{WIFI_BEACON,		"OnBeacon",		&OnBeacon},
++	{WIFI_ATIM,			"OnATIM",		&OnAtim},
++	{WIFI_DISASSOC,		"OnDisassoc",		&OnDisassoc},
++	{WIFI_AUTH,			"OnAuth",		&OnAuthClient},
++	{WIFI_DEAUTH,		"OnDeAuth",		&OnDeAuth},
++	{WIFI_ACTION,		"OnAction",		&OnAction},
++	{WIFI_ACTION_NOACK, "OnActionNoAck",	&OnAction},
++};
++
++#ifdef _CONFIG_NATIVEAP_MLME_
++struct mlme_handler mlme_ap_tbl[] = {
++	{WIFI_ASSOCREQ,		"OnAssocReq",	&OnAssocReq},
++	{WIFI_ASSOCRSP,		"OnAssocRsp",	&OnAssocRsp},
++	{WIFI_REASSOCREQ,	"OnReAssocReq",	&OnAssocReq},
++	{WIFI_REASSOCRSP,	"OnReAssocRsp",	&OnAssocRsp},
++	{WIFI_PROBEREQ,		"OnProbeReq",	&OnProbeReq},
++	{WIFI_PROBERSP,		"OnProbeRsp",		&OnProbeRsp},
++
++	/*----------------------------------------------------------
++					below 2 are reserved
++	-----------------------------------------------------------*/
++	{0,					"DoReserved",		&DoReserved},
++	{0,					"DoReserved",		&DoReserved},
++	{WIFI_BEACON,		"OnBeacon",		&OnBeacon},
++	{WIFI_ATIM,			"OnATIM",		&OnAtim},
++	{WIFI_DISASSOC,		"OnDisassoc",		&OnDisassoc},
++	{WIFI_AUTH,			"OnAuth",		&OnAuth},
++	{WIFI_DEAUTH,		"OnDeAuth",		&OnDeAuth},
++	{WIFI_ACTION,		"OnAction",		&OnAction},
++	{WIFI_ACTION_NOACK, "OnActionNoAck",	&OnAction},
++};
++#endif
++
++struct action_handler OnAction_tbl[] = {
++	{RTW_WLAN_CATEGORY_SPECTRUM_MGMT,	 "ACTION_SPECTRUM_MGMT", on_action_spct},
++	{RTW_WLAN_CATEGORY_QOS, "ACTION_QOS", &OnAction_qos},
++	{RTW_WLAN_CATEGORY_DLS, "ACTION_DLS", &OnAction_dls},
++	{RTW_WLAN_CATEGORY_BACK, "ACTION_BACK", &OnAction_back},
++	{RTW_WLAN_CATEGORY_PUBLIC, "ACTION_PUBLIC", on_action_public},
++	{RTW_WLAN_CATEGORY_RADIO_MEAS, "ACTION_RADIO_MEAS", &on_action_rm},
++	{RTW_WLAN_CATEGORY_FT, "ACTION_FT",	&OnAction_ft},
++	{RTW_WLAN_CATEGORY_HT,	"ACTION_HT",	&OnAction_ht},
++#ifdef CONFIG_IEEE80211W
++	{RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &OnAction_sa_query},
++#else
++	{RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &DoReserved},
++#endif /* CONFIG_IEEE80211W */
++#ifdef CONFIG_RTW_WNM
++	{RTW_WLAN_CATEGORY_WNM, "ACTION_WNM", &on_action_wnm},
++#endif
++	{RTW_WLAN_CATEGORY_UNPROTECTED_WNM, "ACTION_UNPROTECTED_WNM", &DoReserved},
++#ifdef CONFIG_RTW_MESH
++	{RTW_WLAN_CATEGORY_MESH, "ACTION_MESH", &on_action_mesh},
++	{RTW_WLAN_CATEGORY_SELF_PROTECTED, "ACTION_SELF_PROTECTED", &on_action_self_protected},
++#endif
++	{RTW_WLAN_CATEGORY_WMM, "ACTION_WMM", &OnAction_wmm},
++	{RTW_WLAN_CATEGORY_VHT, "ACTION_VHT", &OnAction_vht},
++	{RTW_WLAN_CATEGORY_P2P, "ACTION_P2P", &OnAction_p2p},
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	{RTW_WLAN_CATEGORY_TBTX, "ACTION_TBTX_TOKEN", &OnAction_tbtx_token}
++#endif
++};
++
++
++u8	null_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
++
++/**************************************************
++OUI definitions for the vendor specific IE
++***************************************************/
++unsigned char	RTW_WPA_OUI[] = {0x00, 0x50, 0xf2, 0x01};
++unsigned char WMM_OUI[] = {0x00, 0x50, 0xf2, 0x02};
++unsigned char	WPS_OUI[] = {0x00, 0x50, 0xf2, 0x04};
++unsigned char	P2P_OUI[] = {0x50, 0x6F, 0x9A, 0x09};
++unsigned char	WFD_OUI[] = {0x50, 0x6F, 0x9A, 0x0A};
++unsigned char	DPP_OUI[] = {0x50, 0x6F, 0x9A, 0x1A};
++unsigned char	MULTI_AP_OUI[] = {0x50, 0x6F, 0x9A, 0x1B};
++
++unsigned char	WMM_INFO_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01};
++unsigned char	WMM_PARA_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01};
++
++unsigned char WPA_TKIP_CIPHER[4] = {0x00, 0x50, 0xf2, 0x02};
++unsigned char RSN_TKIP_CIPHER[4] = {0x00, 0x0f, 0xac, 0x02};
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++unsigned char REALTEK_TBTX_IE[] = {0x00, 0xe0, 0x4c, 0x01, 0x00, 0x00, 0x00, 0x00};
++#endif
++extern unsigned char REALTEK_96B_IE[];
++
++static void init_channel_list(_adapter *padapter, RT_CHANNEL_INFO *channel_set
++	, struct p2p_channels *channel_list)
++{
++	struct registry_priv *regsty = adapter_to_regsty(padapter);
++
++	struct p2p_oper_class_map op_class[] = {
++		{ IEEE80211G,  81,   1,  13,  1, BW20 },
++		{ IEEE80211G,  82,  14,  14,  1, BW20 },
++#if 0 /* Do not enable HT40 on 2 GHz */
++		{ IEEE80211G,  83,   1,   9,  1, BW40PLUS },
++		{ IEEE80211G,  84,   5,  13,  1, BW40MINUS },
++#endif
++		{ IEEE80211A, 115,  36,  48,  4, BW20 },
++		{ IEEE80211A, 116,  36,  44,  8, BW40PLUS },
++		{ IEEE80211A, 117,  40,  48,  8, BW40MINUS },
++		{ IEEE80211A, 124, 149, 161,  4, BW20 },
++		{ IEEE80211A, 125, 149, 169,  4, BW20 },
++		{ IEEE80211A, 126, 149, 157,  8, BW40PLUS },
++		{ IEEE80211A, 127, 153, 161,  8, BW40MINUS },
++		{ -1, 0, 0, 0, 0, BW20 }
++	};
++
++	int cla, op;
++
++	cla = 0;
++
++	for (op = 0; op_class[op].op_class; op++) {
++		u8 ch;
++		struct p2p_oper_class_map *o = &op_class[op];
++		struct p2p_reg_class *reg = NULL;
++
++		for (ch = o->min_chan; ch <= o->max_chan; ch += o->inc) {
++			if (rtw_chset_search_ch(channel_set, ch) == -1)
++				continue;
++#if defined(CONFIG_80211N_HT) || defined(CONFIG_80211AC_VHT)
++			if ((padapter->registrypriv.ht_enable == 0) && (o->inc == 8))
++				continue;
++
++			if ((REGSTY_IS_BW_5G_SUPPORT(regsty, CHANNEL_WIDTH_40)) &&
++			    ((o->bw == BW40MINUS) || (o->bw == BW40PLUS)))
++				continue;
++#endif
++			if (reg == NULL) {
++				reg = &channel_list->reg_class[cla];
++				cla++;
++				reg->reg_class = o->op_class;
++				reg->channels = 0;
++			}
++			reg->channel[reg->channels] = ch;
++			reg->channels++;
++		}
++	}
++	channel_list->reg_classes = cla;
++
++}
++
++#if CONFIG_TXPWR_LIMIT
++void rtw_txpwr_init_regd(struct rf_ctl_t *rfctl)
++{
++	u8 regd;
++	struct regd_exc_ent *exc;
++	struct txpwr_lmt_ent *ent;
++	_irqL irqL;
++
++	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++
++	rfctl->regd_name = NULL;
++
++	if (rfctl->txpwr_regd_num == 0) {
++		RTW_PRINT("there is no any txpwr_regd\n");
++		goto release_lock;
++	}
++
++	/* search from exception mapping */
++	exc = _rtw_regd_exc_search(rfctl
++		, rfctl->country_ent ? rfctl->country_ent->alpha2 : NULL
++		, rfctl->ChannelPlan);
++	if (exc) {
++		u8 has_country = (exc->country[0] == '\0' && exc->country[1] == '\0') ? 0 : 1;
++
++		if (strcmp(exc->regd_name, regd_str(TXPWR_LMT_NONE)) == 0)
++			rfctl->regd_name = regd_str(TXPWR_LMT_NONE);
++		else if (strcmp(exc->regd_name, regd_str(TXPWR_LMT_WW)) == 0)
++			rfctl->regd_name = regd_str(TXPWR_LMT_WW);
++		else {
++			ent = _rtw_txpwr_lmt_get_by_name(rfctl, exc->regd_name);
++			if (ent)
++				rfctl->regd_name = ent->regd_name;
++		}
++
++		RTW_PRINT("exception mapping country:%c%c domain:0x%02x to%s regd_name:%s\n"
++			, has_country ? exc->country[0] : '0'
++			, has_country ? exc->country[1] : '0'
++			, exc->domain
++			, rfctl->regd_name ? "" : " unknown"
++			, exc->regd_name
++		);
++		if (rfctl->regd_name)
++			goto release_lock;
++	}
++
++	/* follow default channel plan mapping */
++	regd = rtw_chplan_get_default_regd(rfctl->ChannelPlan);
++	if (regd == TXPWR_LMT_NONE)
++		rfctl->regd_name = regd_str(TXPWR_LMT_NONE);
++	else if (regd == TXPWR_LMT_WW)
++		rfctl->regd_name = regd_str(TXPWR_LMT_WW);
++	else {
++		ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_str(regd));
++		if (ent)
++			rfctl->regd_name = ent->regd_name;
++	}
++
++	RTW_PRINT("default mapping domain:0x%02x to%s regd_name:%s\n"
++		, rfctl->ChannelPlan
++		, rfctl->regd_name ? "" : " unknown"
++		, regd_str(regd)
++	);
++	if (rfctl->regd_name)
++		goto release_lock;
++
++	switch (regd) {
++	/*
++	* To support older chips without new predefined regd:
++	* - use FCC if IC or CHILE or MEXICO not found
++	* - use ETSI if KCC or ACMA not found
++	*/
++	case TXPWR_LMT_IC:
++	case TXPWR_LMT_KCC:
++	case TXPWR_LMT_ACMA:
++	case TXPWR_LMT_CHILE:
++	case TXPWR_LMT_MEXICO:
++		if (regd == TXPWR_LMT_IC || regd == TXPWR_LMT_CHILE || regd == TXPWR_LMT_MEXICO)
++			regd = TXPWR_LMT_FCC;
++		else if (regd == TXPWR_LMT_KCC || regd == TXPWR_LMT_ACMA)
++			regd = TXPWR_LMT_ETSI;
++		ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_str(regd));
++		if (ent)
++			rfctl->regd_name = ent->regd_name;
++		RTW_PRINT("alternate regd_name:%s %s\n"
++			, regd_str(regd)
++			, rfctl->regd_name ? "is used" : "not found"
++		);
++		if (rfctl->regd_name)
++			break;
++	default:
++		rfctl->regd_name = regd_str(TXPWR_LMT_WW);
++		RTW_PRINT("assign %s for default case\n", regd_str(TXPWR_LMT_WW));
++		break;
++	};
++
++release_lock:
++	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++}
++#endif /* CONFIG_TXPWR_LIMIT */
++
++void rtw_rfctl_init(_adapter *adapter)
++{
++	struct registry_priv *regsty = adapter_to_regsty(adapter);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++
++	_rtw_mutex_init(&rfctl->offch_mutex);
++
++#if CONFIG_TXPWR_LIMIT
++	_rtw_mutex_init(&rfctl->txpwr_lmt_mutex);
++	_rtw_init_listhead(&rfctl->reg_exc_list);
++	_rtw_init_listhead(&rfctl->txpwr_lmt_list);
++#endif
++
++	rfctl->ch_sel_within_same_band = 1;
++
++#ifdef CONFIG_DFS_MASTER
++	rfctl->dfs_region_domain = regsty->dfs_region_domain;
++	rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;
++	rtw_init_timer(&(rfctl->radar_detect_timer), adapter, rtw_dfs_rd_timer_hdl, rfctl);
++#endif
++#if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
++	rfctl->dfs_slave_with_rd = 1;
++#endif
++
++	rfctl->cap_spt_op_class_num = init_op_class_ch_bmp(adapter, NULL, rfctl->cap_spt_op_class_ch_bmp);
++	rfctl->max_chan_nums = init_channel_set(adapter, rfctl->ChannelPlan, rfctl->channel_set);
++	rfctl->cur_spt_op_class_num = init_op_class_ch_bmp(adapter, rfctl->channel_set, rfctl->cur_spt_op_class_ch_bmp);
++	init_channel_list(adapter, rfctl->channel_set, &rfctl->channel_list);
++}
++
++void rtw_rfctl_deinit(_adapter *adapter)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++
++	_rtw_mutex_free(&rfctl->offch_mutex);
++
++#if CONFIG_TXPWR_LIMIT
++	rtw_regd_exc_list_free(rfctl);
++	rtw_txpwr_lmt_list_free(rfctl);
++	_rtw_mutex_free(&rfctl->txpwr_lmt_mutex);
++#endif
++}
++
++inline u8 rtw_rfctl_get_dfs_domain(struct rf_ctl_t *rfctl)
++{
++#ifdef CONFIG_DFS_MASTER
++	return rfctl->dfs_region_domain;
++#else
++	return PHYDM_DFS_DOMAIN_UNKNOWN;
++#endif
++}
++
++inline u8 rtw_rfctl_dfs_domain_unknown(struct rf_ctl_t *rfctl)
++{
++#ifdef CONFIG_DFS_MASTER
++	return rtw_rfctl_get_dfs_domain(rfctl) == PHYDM_DFS_DOMAIN_UNKNOWN;
++#else
++	return 1;
++#endif
++}
++
++#ifdef CONFIG_DFS_MASTER
++/*
++* called in rtw_dfs_rd_enable()
++* assume the request channel coverage is DFS range
++* base on the current status and the request channel coverage to check if need to reset complete CAC time
++*/
++bool rtw_is_cac_reset_needed(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset)
++{
++	bool needed = _FALSE;
++	u32 cur_hi, cur_lo, hi, lo;
++
++	if (rfctl->radar_detected == 1) {
++		needed = _TRUE;
++		goto exit;
++	}
++
++	if (rfctl->radar_detect_ch == 0) {
++		needed = _TRUE;
++		goto exit;
++	}
++
++	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) {
++		RTW_ERR("request detection range ch:%u, bw:%u, offset:%u\n", ch, bw, offset);
++		rtw_warn_on(1);
++	}
++
++	if (rtw_chbw_to_freq_range(rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset, &cur_hi, &cur_lo) == _FALSE) {
++		RTW_ERR("cur detection range ch:%u, bw:%u, offset:%u\n", rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset);
++		rtw_warn_on(1);
++	}
++
++	if (hi <= lo || cur_hi <= cur_lo) {
++		RTW_ERR("hi:%u, lo:%u, cur_hi:%u, cur_lo:%u\n", hi, lo, cur_hi, cur_lo);
++		rtw_warn_on(1);
++	}
++
++	if (rtw_is_range_a_in_b(hi, lo, cur_hi, cur_lo)) {
++		/* request is in current detect range */
++		goto exit;
++	}
++
++	/* check if request channel coverage has new range and the new range is in DFS range */
++	if (!rtw_is_range_overlap(hi, lo, cur_hi, cur_lo)) {
++		/* request has no overlap with current */
++		needed = _TRUE;
++	} else if (rtw_is_range_a_in_b(cur_hi, cur_lo, hi, lo)) {
++		/* request is supper set of current */
++		if ((hi != cur_hi && rtw_chset_is_dfs_range(rfctl->channel_set, hi, cur_hi))
++			|| (lo != cur_lo && rtw_chset_is_dfs_range(rfctl->channel_set, cur_lo, lo)))
++			needed = _TRUE;
++	} else {
++		/* request is not supper set of current, but has overlap */
++		if ((lo < cur_lo && rtw_chset_is_dfs_range(rfctl->channel_set, cur_lo, lo))
++			|| (hi > cur_hi && rtw_chset_is_dfs_range(rfctl->channel_set, hi, cur_hi)))
++			needed = _TRUE;
++	}
++
++exit:
++	return needed;
++}
++
++bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset)
++{
++	bool ret = _FALSE;
++	u32 hi = 0, lo = 0;
++	u32 r_hi = 0, r_lo = 0;
++	int i;
++
++	if (rfctl->radar_detect_by_others)
++		goto exit;
++
++	if (rfctl->radar_detect_ch == 0)
++		goto exit;
++
++	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (rtw_chbw_to_freq_range(rfctl->radar_detect_ch
++			, rfctl->radar_detect_bw, rfctl->radar_detect_offset
++			, &r_hi, &r_lo) == _FALSE) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (rtw_is_range_overlap(hi, lo, r_hi, r_lo))
++		ret = _TRUE;
++
++exit:
++	return ret;
++}
++
++bool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl)
++{
++	return _rtw_rfctl_overlap_radar_detect_ch(rfctl
++				, rfctl_to_dvobj(rfctl)->oper_channel
++				, rfctl_to_dvobj(rfctl)->oper_bwmode
++				, rfctl_to_dvobj(rfctl)->oper_ch_offset);
++}
++
++bool rtw_rfctl_is_tx_blocked_by_ch_waiting(struct rf_ctl_t *rfctl)
++{
++	return rtw_rfctl_overlap_radar_detect_ch(rfctl) && IS_CH_WAITING(rfctl);
++}
++
++bool rtw_chset_is_chbw_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)
++{
++	bool ret = _FALSE;
++	u32 hi = 0, lo = 0;
++	int i;
++
++	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
++		goto exit;
++
++	for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
++		if (!rtw_ch2freq(ch_set[i].ChannelNum)) {
++			rtw_warn_on(1);
++			continue;
++		}
++
++		if (!CH_IS_NON_OCP(&ch_set[i]))
++			continue;
++
++		if (lo <= rtw_ch2freq(ch_set[i].ChannelNum)
++			&& rtw_ch2freq(ch_set[i].ChannelNum) <= hi
++		) {
++			ret = _TRUE;
++			break;
++		}
++	}
++
++exit:
++	return ret;
++}
++
++bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch)
++{
++	return rtw_chset_is_chbw_non_ocp(ch_set, ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
++}
++
++u32 rtw_chset_get_ch_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)
++{
++	int ms = 0;
++	systime current_time;
++	u32 hi = 0, lo = 0;
++	int i;
++
++	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
++		goto exit;
++
++	current_time = rtw_get_current_time();
++
++	for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
++		if (!rtw_ch2freq(ch_set[i].ChannelNum)) {
++			rtw_warn_on(1);
++			continue;
++		}
++
++		if (!CH_IS_NON_OCP(&ch_set[i]))
++			continue;
++
++		if (lo <= rtw_ch2freq(ch_set[i].ChannelNum)
++			&& rtw_ch2freq(ch_set[i].ChannelNum) <= hi
++		) {
++			if (rtw_systime_to_ms(ch_set[i].non_ocp_end_time - current_time) > ms)
++				ms = rtw_systime_to_ms(ch_set[i].non_ocp_end_time - current_time);
++		}
++	}
++
++exit:
++	return ms;
++}
++
++/**
++ * rtw_chset_update_non_ocp - update non_ocp_end_time according to the given @ch, @bw, @offset into @ch_set
++ * @ch_set: the given channel set
++ * @ch: channel number on which radar is detected
++ * @bw: bandwidth on which radar is detected
++ * @offset: bandwidth offset on which radar is detected
++ * @ms: ms to add from now to update non_ocp_end_time, ms < 0 means use NON_OCP_TIME_MS
++ */
++static void _rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms)
++{
++	u32 hi = 0, lo = 0;
++	int i;
++
++	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
++		goto exit;
++
++	for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
++		if (!rtw_ch2freq(ch_set[i].ChannelNum)) {
++			rtw_warn_on(1);
++			continue;
++		}
++
++		if (lo <= rtw_ch2freq(ch_set[i].ChannelNum)
++			&& rtw_ch2freq(ch_set[i].ChannelNum) <= hi
++		) {
++			if (ms >= 0)
++				ch_set[i].non_ocp_end_time = rtw_get_current_time() + rtw_ms_to_systime(ms);
++			else
++				ch_set[i].non_ocp_end_time = rtw_get_current_time() + rtw_ms_to_systime(NON_OCP_TIME_MS);
++		}
++	}
++
++exit:
++	return;
++}
++
++inline void rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)
++{
++	_rtw_chset_update_non_ocp(ch_set, ch, bw, offset, -1);
++}
++
++inline void rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms)
++{
++	_rtw_chset_update_non_ocp(ch_set, ch, bw, offset, ms);
++}
++
++u32 rtw_get_ch_waiting_ms(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms)
++{
++	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
++	u32 non_ocp_ms;
++	u32 cac_ms;
++	u8 in_rd_range = 0; /* if in current radar detection range*/
++
++	if (rtw_chset_is_chbw_non_ocp(rfctl->channel_set, ch, bw, offset))
++		non_ocp_ms = rtw_chset_get_ch_non_ocp_ms(rfctl->channel_set, ch, bw, offset);
++	else
++		non_ocp_ms = 0;
++
++	if (rfctl->radar_detect_enabled) {
++		u32 cur_hi, cur_lo, hi, lo;
++
++		if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) {
++			RTW_ERR("input range ch:%u, bw:%u, offset:%u\n", ch, bw, offset);
++			rtw_warn_on(1);
++		}
++
++		if (rtw_chbw_to_freq_range(rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset, &cur_hi, &cur_lo) == _FALSE) {
++			RTW_ERR("cur detection range ch:%u, bw:%u, offset:%u\n", rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset);
++			rtw_warn_on(1);
++		}
++
++		if (rtw_is_range_a_in_b(hi, lo, cur_hi, cur_lo))
++			in_rd_range = 1;
++	}
++
++	if (!rtw_chset_is_dfs_chbw(rfctl->channel_set, ch, bw, offset))
++		cac_ms = 0;
++	else if (in_rd_range && !non_ocp_ms) {
++		if (IS_CH_WAITING(rfctl))
++			cac_ms = rtw_systime_to_ms(rfctl->cac_end_time - rtw_get_current_time());
++		else
++			cac_ms = 0;
++	} else if (rtw_is_long_cac_ch(ch, bw, offset, rtw_rfctl_get_dfs_domain(rfctl)))
++		cac_ms = CAC_TIME_CE_MS;
++	else
++		cac_ms = CAC_TIME_MS;
++
++	if (r_non_ocp_ms)
++		*r_non_ocp_ms = non_ocp_ms;
++	if (r_cac_ms)
++		*r_cac_ms = cac_ms;
++
++	return non_ocp_ms + cac_ms;
++}
++
++void rtw_reset_cac(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset)
++{
++	u32 non_ocp_ms;
++	u32 cac_ms;
++
++	rtw_get_ch_waiting_ms(rfctl
++		, ch
++		, bw
++		, offset
++		, &non_ocp_ms
++		, &cac_ms
++	);
++
++	rfctl->cac_start_time = rtw_get_current_time() + rtw_ms_to_systime(non_ocp_ms);
++	rfctl->cac_end_time = rfctl->cac_start_time + rtw_ms_to_systime(cac_ms);
++
++	/* skip special value */
++	if (rfctl->cac_start_time == RTW_CAC_STOPPED) {
++		rfctl->cac_start_time++;
++		rfctl->cac_end_time++;
++	}
++	if (rfctl->cac_end_time == RTW_CAC_STOPPED)
++		rfctl->cac_end_time++;
++}
++
++u32 rtw_force_stop_cac(struct rf_ctl_t *rfctl, u32 timeout_ms)
++{
++	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
++	systime start;
++	u32 pass_ms;
++
++	start = rtw_get_current_time();
++
++	rfctl->cac_force_stop = 1;
++
++	while (rtw_get_passing_time_ms(start) <= timeout_ms
++		&& IS_UNDER_CAC(rfctl)
++	) {
++		if (dev_is_surprise_removed(dvobj) || dev_is_drv_stopped(dvobj))
++			break;
++		rtw_msleep_os(20);
++	}
++
++	if (IS_UNDER_CAC(rfctl)) {
++		if (!dev_is_surprise_removed(dvobj) && !dev_is_drv_stopped(dvobj))
++			RTW_INFO("%s waiting for cac stop timeout!\n", __func__);
++	}
++
++	rfctl->cac_force_stop = 0;
++
++	pass_ms = rtw_get_passing_time_ms(start);
++
++	return pass_ms;
++}
++#endif /* CONFIG_DFS_MASTER */
++
++/* choose channel with shortest waiting (non ocp + cac) time */
++bool rtw_choose_shortest_waiting_ch(struct rf_ctl_t *rfctl, u8 sel_ch, u8 max_bw
++	, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset
++	, u8 d_flags, u8 cur_ch, bool by_int_info, u8 mesh_only)
++{
++#ifndef DBG_CHOOSE_SHORTEST_WAITING_CH
++#define DBG_CHOOSE_SHORTEST_WAITING_CH 0
++#endif
++	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
++#ifdef CONFIG_RTW_ACS
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(dvobj_get_primary_adapter(dvobj));
++#endif
++	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
++	u8 ch, bw, offset;
++	u8 ch_c = 0, bw_c = 0, offset_c = 0;
++	int i;
++	u32 min_waiting_ms = 0;
++	u16 int_factor_c = 0;
++
++	if (!dec_ch || !dec_bw || !dec_offset) {
++		rtw_warn_on(1);
++		return _FALSE;
++	}
++
++	RTW_INFO("%s: sel_ch:%u max_bw:%u d_flags:0x%02x cur_ch:%u within_sb:%d%s%s\n"
++		, __func__, sel_ch, max_bw, d_flags, cur_ch, rfctl->ch_sel_within_same_band
++		, by_int_info ? " int" : "", mesh_only ? " mesh_only" : "");
++
++	/* full search and narrow bw judegement first to avoid potetial judegement timing issue */
++	for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) {
++		if (!hal_is_bw_support(dvobj_get_primary_adapter(dvobj), bw))
++			continue;
++
++		for (i = 0; i < rfctl->max_chan_nums; i++) {
++			u32 non_ocp_ms = 0;
++			u32 cac_ms = 0;
++			u32 waiting_ms = 0;
++			u16 int_factor = 0;
++			bool dfs_ch;
++
++			ch = rfctl->channel_set[i].ChannelNum;
++			if (sel_ch) {
++				if (ch != sel_ch)
++					continue;
++			} else if (rfctl->ch_sel_within_same_band && !rtw_is_same_band(cur_ch, ch))
++				continue;
++
++			if ((d_flags & RTW_CHF_2G) && ch <= 14)
++				continue;
++
++			if ((d_flags & RTW_CHF_5G) && ch > 14)
++				continue;
++
++			if (ch > 14) {
++				if (bw > REGSTY_BW_5G(regsty))
++					continue;
++			} else {
++				if (bw > REGSTY_BW_2G(regsty))
++					continue;
++			}
++
++			if (mesh_only && ch >= 5 && ch <= 9 && bw > CHANNEL_WIDTH_20)
++				continue;
++
++			if (!rtw_get_offset_by_chbw(ch, bw, &offset))
++				continue;
++
++			if (!rtw_chset_is_chbw_valid(rfctl->channel_set, ch, bw, offset, 0, 0))
++				continue;
++
++			if ((d_flags & RTW_CHF_NON_OCP) && rtw_chset_is_chbw_non_ocp(rfctl->channel_set, ch, bw, offset))
++				continue;
++
++			dfs_ch = rtw_chset_is_dfs_chbw(rfctl->channel_set, ch, bw, offset);
++			if ((d_flags & RTW_CHF_DFS) && dfs_ch)
++				continue;
++
++			if ((d_flags & RTW_CHF_LONG_CAC) && dfs_ch && rtw_is_long_cac_ch(ch, bw, offset, rtw_rfctl_get_dfs_domain(rfctl)))
++				continue;
++
++			if ((d_flags & RTW_CHF_NON_DFS) && !dfs_ch)
++				continue;
++
++			if ((d_flags & RTW_CHF_NON_LONG_CAC) && !(dfs_ch && rtw_is_long_cac_ch(ch, bw, offset, rtw_rfctl_get_dfs_domain(rfctl))))
++				continue;
++
++			#ifdef CONFIG_DFS_MASTER
++			waiting_ms = rtw_get_ch_waiting_ms(rfctl, ch, bw, offset, &non_ocp_ms, &cac_ms);
++			#endif
++
++			#ifdef CONFIG_RTW_ACS
++			if (by_int_info) {
++				/* for now, consider only primary channel */
++				int_factor = hal_data->acs.interference_time[i];
++			}
++			#endif
++
++			if (DBG_CHOOSE_SHORTEST_WAITING_CH)
++				RTW_INFO("%s:%u,%u,%u %u(non_ocp:%u, cac:%u), int:%u\n"
++					, __func__, ch, bw, offset, waiting_ms, non_ocp_ms, cac_ms, int_factor);
++
++			if (ch_c == 0
++				/* first: smaller wating time */
++				|| min_waiting_ms > waiting_ms
++				/* then: less interference */
++				|| (min_waiting_ms == waiting_ms && int_factor_c > int_factor)
++				/* then: wider bw */
++				|| (min_waiting_ms == waiting_ms && int_factor_c == int_factor && bw > bw_c)
++				/* if all condition equal, same channel -> same band prefer */
++				|| (min_waiting_ms == waiting_ms && int_factor_c == int_factor && bw == bw_c
++					&& ((cur_ch != ch_c && cur_ch == ch)
++						|| (!rtw_is_same_band(cur_ch, ch_c) && rtw_is_same_band(cur_ch, ch)))
++					)
++			) {
++				ch_c = ch;
++				bw_c = bw;
++				offset_c = offset;
++				min_waiting_ms = waiting_ms;
++				int_factor_c = int_factor;
++			}
++		}
++	}
++
++	if (ch_c != 0) {
++		RTW_INFO("%s: select %u,%u,%u waiting_ms:%u\n"
++			, __func__, ch_c, bw_c, offset_c, min_waiting_ms);
++		*dec_ch = ch_c;
++		*dec_bw = bw_c;
++		*dec_offset = offset_c;
++		return _TRUE;
++	} else {
++		RTW_INFO("%s: not found\n", __func__);
++		if (d_flags == 0)
++			rtw_warn_on(1);
++	}
++
++	return _FALSE;
++}
++
++void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set)
++{
++	u8	i;
++
++	for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
++		RTW_PRINT_SEL(sel, "ch:%3u, freq:%u, scan_type:%d"
++			, ch_set[i].ChannelNum, rtw_ch2freq(ch_set[i].ChannelNum), ch_set[i].ScanType);
++
++#ifdef CONFIG_FIND_BEST_CHANNEL
++		_RTW_PRINT_SEL(sel, ", rx_count:%u", ch_set[i].rx_count);
++#endif
++
++#ifdef CONFIG_DFS_MASTER
++		if (ch_set[i].dfs) {
++			if (CH_IS_NON_OCP(&ch_set[i]))
++				_RTW_PRINT_SEL(sel, ", non_ocp:%d"
++					, rtw_systime_to_ms(ch_set[i].non_ocp_end_time - rtw_get_current_time()));
++			else
++				_RTW_PRINT_SEL(sel, ", non_ocp:N/A");
++		}
++#endif
++
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++
++	RTW_PRINT_SEL(sel, "total ch number:%d\n", i);
++}
++
++void dump_cur_chset(void *sel, struct rf_ctl_t *rfctl)
++{
++	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
++	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
++	int i;
++
++	if (rfctl->country_ent)
++		dump_country_chplan(sel, rfctl->country_ent);
++	else
++		RTW_PRINT_SEL(sel, "chplan:0x%02X\n", rfctl->ChannelPlan);
++
++#if CONFIG_TXPWR_LIMIT
++	RTW_PRINT_SEL(sel, "PLS regd:%s\n", rfctl->regd_name);
++#endif
++
++#ifdef CONFIG_DFS_MASTER
++	RTW_PRINT_SEL(sel, "dfs_domain:%u\n", rtw_rfctl_get_dfs_domain(rfctl));
++#endif
++
++	for (i = 0; i < MAX_CHANNEL_NUM; i++)
++		if (regsty->excl_chs[i] != 0)
++			break;
++
++	if (i < MAX_CHANNEL_NUM) {
++		RTW_PRINT_SEL(sel, "excl_chs:");
++		for (i = 0; i < MAX_CHANNEL_NUM; i++) {
++			if (regsty->excl_chs[i] == 0)
++				break;
++			_RTW_PRINT_SEL(sel, "%u ", regsty->excl_chs[i]);
++		}
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++
++	dump_chset(sel, rfctl->channel_set);
++}
++
++/*
++ * Search the @param ch in given @param ch_set
++ * @ch_set: the given channel set
++ * @ch: the given channel number
++ *
++ * return the index of channel_num in channel_set, -1 if not found
++ */
++int rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch)
++{
++	int i;
++
++	if (ch == 0)
++		return -1;
++
++	for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
++		if (ch == ch_set[i].ChannelNum)
++			return i;
++	}
++
++	return -1;
++}
++
++/*
++ * Check if the @param ch, bw, offset is valid for the given @param ch_set
++ * @ch_set: the given channel set
++ * @ch: the given channel number
++ * @bw: the given bandwidth
++ * @offset: the given channel offset
++ *
++ * return valid (1) or not (0)
++ */
++u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset
++	, bool allow_primary_passive, bool allow_passive)
++{
++	u8 cch;
++	u8 *op_chs;
++	u8 op_ch_num;
++	u8 valid = 0;
++	int i;
++	int ch_idx;
++
++	cch = rtw_get_center_ch(ch, bw, offset);
++
++	if (!rtw_get_op_chs_by_cch_bw(cch, bw, &op_chs, &op_ch_num))
++		goto exit;
++
++	for (i = 0; i < op_ch_num; i++) {
++		if (0)
++			RTW_INFO("%u,%u,%u - cch:%u, bw:%u, op_ch:%u\n", ch, bw, offset, cch, bw, *(op_chs + i));
++		ch_idx = rtw_chset_search_ch(ch_set, *(op_chs + i));
++		if (ch_idx == -1)
++			break;
++		if (ch_set[ch_idx].ScanType == SCAN_PASSIVE) {
++			if ((!allow_primary_passive && ch_set[ch_idx].ChannelNum == ch)
++				|| (!allow_passive && ch_set[ch_idx].ChannelNum != ch))
++			break;
++		}
++	}
++
++	if (op_ch_num != 0 && i == op_ch_num)
++		valid = 1;
++
++exit:
++	return valid;
++}
++
++/**
++ * rtw_chset_sync_chbw - obey g_ch, adjust g_bw, g_offset, bw, offset to fit in channel plan
++ * @ch_set: channel plan to check
++ * @req_ch: pointer of the request ch, may be modified further
++ * @req_bw: pointer of the request bw, may be modified further
++ * @req_offset: pointer of the request offset, may be modified further
++ * @g_ch: pointer of the ongoing group ch
++ * @g_bw: pointer of the ongoing group bw, may be modified further
++ * @g_offset: pointer of the ongoing group offset, may be modified further
++ * @allow_primary_passive: if allow passive primary ch when deciding chbw
++ * @allow_passive: if allow passive ch (not primary) when deciding chbw
++ */
++void rtw_chset_sync_chbw(RT_CHANNEL_INFO *ch_set, u8 *req_ch, u8 *req_bw, u8 *req_offset
++	, u8 *g_ch, u8 *g_bw, u8 *g_offset, bool allow_primary_passive, bool allow_passive)
++{
++	u8 r_ch, r_bw, r_offset;
++	u8 u_ch, u_bw, u_offset;
++	u8 cur_bw = *req_bw;
++
++	while (1) {
++		r_ch = *req_ch;
++		r_bw = cur_bw;
++		r_offset = *req_offset;
++		u_ch = *g_ch;
++		u_bw = *g_bw;
++		u_offset = *g_offset;
++
++		rtw_sync_chbw(&r_ch, &r_bw, &r_offset, &u_ch, &u_bw, &u_offset);
++
++		if (rtw_chset_is_chbw_valid(ch_set, r_ch, r_bw, r_offset, allow_primary_passive, allow_passive))
++			break;
++		if (cur_bw == CHANNEL_WIDTH_20) {
++			rtw_warn_on(1);
++			break;
++		}
++		cur_bw--;
++	};
++
++	*req_ch = r_ch;
++	*req_bw = r_bw;
++	*req_offset = r_offset;
++	*g_ch = u_ch;
++	*g_bw = u_bw;
++	*g_offset = u_offset;
++}
++
++/*
++ * Check the @param ch is fit with setband setting of @param adapter
++ * @adapter: the given adapter
++ * @ch: the given channel number
++ *
++ * return _TRUE when check valid, _FALSE not valid
++ */
++bool rtw_mlme_band_check(_adapter *adapter, const u32 ch)
++{
++	if (adapter->setband == WIFI_FREQUENCY_BAND_AUTO /* 2.4G and 5G */
++		|| (adapter->setband == WIFI_FREQUENCY_BAND_2GHZ && ch < 35) /* 2.4G only */
++		|| (adapter->setband == WIFI_FREQUENCY_BAND_5GHZ && ch > 35) /* 5G only */
++	)
++		return _TRUE;
++	return _FALSE;
++}
++inline void RTW_SET_SCAN_BAND_SKIP(_adapter *padapter, int skip_band)
++{
++	int bs = ATOMIC_READ(&padapter->bandskip);
++
++	bs |= skip_band;
++	ATOMIC_SET(&padapter->bandskip, bs);
++}
++
++inline void RTW_CLR_SCAN_BAND_SKIP(_adapter *padapter, int skip_band)
++{
++	int bs = ATOMIC_READ(&padapter->bandskip);
++
++	bs &= ~(skip_band);
++	ATOMIC_SET(&padapter->bandskip, bs);
++}
++inline int RTW_GET_SCAN_BAND_SKIP(_adapter *padapter)
++{
++	return ATOMIC_READ(&padapter->bandskip);
++}
++
++#define RTW_IS_SCAN_BAND_SKIP(padapter, skip_band) (ATOMIC_READ(&padapter->bandskip) & (skip_band))
++
++bool rtw_mlme_ignore_chan(_adapter *adapter, const u32 ch)
++{
++	if (RTW_IS_SCAN_BAND_SKIP(adapter, BAND_24G) && ch < 35) /* SKIP 2.4G Band channel */
++		return _TRUE;
++	if (RTW_IS_SCAN_BAND_SKIP(adapter, BAND_5G)  && ch > 35) /* SKIP 5G Band channel */
++		return _TRUE;
++
++	return _FALSE;
++}
++
++
++/****************************************************************************
++
++Following are the initialization functions for WiFi MLME
++
++*****************************************************************************/
++
++int init_hw_mlme_ext(_adapter *padapter)
++{
++	struct	mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++	u8 rx_bar_enble = _TRUE;
++
++	/*
++	 * Sync driver status and hardware setting
++	 */
++
++	/* Modify to make sure first time change channel(band) would be done properly */
++	pHalData->current_channel = 0;
++	pHalData->current_channel_bw = CHANNEL_WIDTH_MAX;
++	#if CONFIG_IEEE80211_BAND_5GHZ
++	pHalData->current_band_type = BAND_MAX;
++	#else
++	pHalData->current_band_type = BAND_ON_2_4G;
++	#endif
++
++	/* set_opmode_cmd(padapter, infra_client_with_mlme); */ /* removed */
++	rtw_hal_set_hwreg(padapter, HW_VAR_ENABLE_RX_BAR, &rx_bar_enble);
++	set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++
++	return _SUCCESS;
++}
++
++void init_mlme_default_rate_set(_adapter *padapter)
++{
++	struct	mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	unsigned	char end_set[1] = {0xff};
++	u8	offset_datarate = 0;
++	u8	offset_basicrate = 0;
++#ifdef CONFIG_80211N_HT
++	unsigned char	supported_mcs_set[16] = {0xff, 0xff, 0xff, 0xff, 0x00, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
++#endif
++
++	if (IsSupportedTxCCK(padapter->registrypriv.wireless_mode)) {
++
++		unsigned char	datarate_b[B_MODE_RATE_NUM] ={_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_};
++		_rtw_memcpy(pmlmeext->datarate, datarate_b, B_MODE_RATE_NUM);
++		_rtw_memcpy(pmlmeext->basicrate, datarate_b, B_MODE_RATE_NUM);
++		offset_datarate += B_MODE_RATE_NUM;
++		offset_basicrate += B_MODE_RATE_NUM;
++		RTW_INFO("%s: support CCK\n", __func__);
++	}
++	if(IsSupportedTxOFDM(padapter->registrypriv.wireless_mode)) {
++		unsigned char	datarate_g[G_MODE_RATE_NUM] ={_6M_RATE_, _9M_RATE_, _12M_RATE_, _18M_RATE_,_24M_RATE_, _36M_RATE_, _48M_RATE_, _54M_RATE_};
++		unsigned char	basicrate_g[G_MODE_BASIC_RATE_NUM] = {_6M_RATE_, _12M_RATE_, _24M_RATE_};
++		_rtw_memcpy(pmlmeext->datarate + offset_datarate, datarate_g, G_MODE_RATE_NUM);
++		_rtw_memcpy(pmlmeext->basicrate + offset_basicrate,basicrate_g, G_MODE_BASIC_RATE_NUM);
++		offset_datarate += G_MODE_RATE_NUM;
++		offset_basicrate += G_MODE_BASIC_RATE_NUM;
++		RTW_INFO("%s: support OFDM\n", __func__);
++
++	}
++	_rtw_memcpy(pmlmeext->datarate + offset_datarate, end_set, 1);
++	_rtw_memcpy(pmlmeext->basicrate + offset_basicrate, end_set, 1);
++
++#ifdef CONFIG_80211N_HT
++	if( padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode))
++		_rtw_memcpy(pmlmeext->default_supported_mcs_set, supported_mcs_set, sizeof(pmlmeext->default_supported_mcs_set));
++#endif
++}
++
++static void init_mlme_ext_priv_value(_adapter *padapter)
++{
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	ATOMIC_SET(&pmlmeext->event_seq, 0);
++	pmlmeext->mgnt_seq = 0;/* reset to zero when disconnect at client mode */
++#ifdef CONFIG_IEEE80211W
++	pmlmeext->sa_query_seq = 0;
++#endif
++	pmlmeext->cur_channel = padapter->registrypriv.channel;
++	pmlmeext->cur_bwmode = CHANNEL_WIDTH_20;
++	pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++	pmlmeext->retry = 0;
++
++	pmlmeext->cur_wireless_mode = padapter->registrypriv.wireless_mode;
++	init_mlme_default_rate_set(padapter);
++
++	if ((pmlmeext->cur_channel > 14) || ((padapter->registrypriv.wireless_mode & WIRELESS_11B) == 0))
++		pmlmeext->tx_rate = IEEE80211_OFDM_RATE_6MB;
++	else
++		pmlmeext->tx_rate = IEEE80211_CCK_RATE_1MB;
++
++	mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE);
++	pmlmeext->sitesurvey_res.channel_idx = 0;
++	pmlmeext->sitesurvey_res.bss_cnt = 0;
++	pmlmeext->sitesurvey_res.scan_ch_ms = SURVEY_TO;
++	pmlmeext->sitesurvey_res.rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID;
++	pmlmeext->sitesurvey_res.rx_ampdu_size = RX_AMPDU_SIZE_INVALID;
++#ifdef CONFIG_SCAN_BACKOP
++	mlmeext_assign_scan_backop_flags_sta(pmlmeext, /*SS_BACKOP_EN|*/SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME);
++	#ifdef CONFIG_AP_MODE
++	mlmeext_assign_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN | SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME);
++	#endif
++	#ifdef CONFIG_RTW_MESH
++	mlmeext_assign_scan_backop_flags_mesh(pmlmeext, /*SS_BACKOP_EN | */SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME);
++	#endif
++	pmlmeext->sitesurvey_res.scan_cnt = 0;
++	pmlmeext->sitesurvey_res.scan_cnt_max = RTW_SCAN_NUM_OF_CH;
++	pmlmeext->sitesurvey_res.backop_ms = RTW_BACK_OP_CH_MS;
++#endif
++#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)
++	pmlmeext->sitesurvey_res.is_sw_antdiv_bl_scan = 0;
++#endif
++	pmlmeext->scan_abort = _FALSE;
++
++	pmlmeinfo->state = WIFI_FW_NULL_STATE;
++	pmlmeinfo->reauth_count = 0;
++	pmlmeinfo->reassoc_count = 0;
++	pmlmeinfo->link_count = 0;
++	pmlmeinfo->auth_seq = 0;
++	pmlmeinfo->auth_algo = dot11AuthAlgrthm_Open;
++	pmlmeinfo->key_index = 0;
++	pmlmeinfo->iv = 0;
++
++	pmlmeinfo->enc_algo = _NO_PRIVACY_;
++	pmlmeinfo->authModeToggle = 0;
++
++	_rtw_memset(pmlmeinfo->chg_txt, 0, 128);
++
++	pmlmeinfo->slotTime = SHORT_SLOT_TIME;
++	pmlmeinfo->preamble_mode = PREAMBLE_AUTO;
++
++	pmlmeinfo->dialogToken = 0;
++
++	pmlmeext->action_public_rxseq = 0xffff;
++	pmlmeext->action_public_dialog_token = 0xff;
++#ifdef ROKU_PRIVATE
++/*infra mode, used to store AP's info*/
++	_rtw_memset(pmlmeinfo->SupportedRates_infra_ap, 0, NDIS_802_11_LENGTH_RATES_EX);
++	pmlmeinfo->ht_vht_received = 0;
++#endif /* ROKU_PRIVATE */
++}
++
++void init_mlme_ext_timer(_adapter *padapter)
++{
++	struct	mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++	rtw_init_timer(&pmlmeext->survey_timer, padapter, survey_timer_hdl, padapter);
++	rtw_init_timer(&pmlmeext->link_timer, padapter, link_timer_hdl, padapter);
++#ifdef CONFIG_RTW_80211R
++	rtw_init_timer(&pmlmeext->ft_link_timer, padapter, rtw_ft_link_timer_hdl, padapter);
++	rtw_init_timer(&pmlmeext->ft_roam_timer, padapter, rtw_ft_roam_timer_hdl, padapter);
++#endif
++
++#ifdef CONFIG_RTW_REPEATER_SON
++	rtw_init_timer(&pmlmeext->rson_scan_timer, padapter, rson_timer_hdl, padapter);
++#endif
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	rtw_init_timer(&pmlmeext->tbtx_xmit_timer, padapter, rtw_tbtx_xmit_timer_hdl, padapter);
++	rtw_init_timer(&pmlmeext->tbtx_token_dispatch_timer, padapter, rtw_tbtx_token_dispatch_timer_hdl, padapter);
++#endif
++}
++
++int	init_mlme_ext_priv(_adapter *padapter)
++{
++	int	res = _SUCCESS;
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
++	/* _rtw_memset((u8 *)pmlmeext, 0, sizeof(struct mlme_ext_priv)); */
++
++	pmlmeext->padapter = padapter;
++
++	/* fill_fwpriv(padapter, &(pmlmeext->fwpriv)); */
++
++	init_mlme_ext_priv_value(padapter);
++	pmlmeinfo->bAcceptAddbaReq = pregistrypriv->bAcceptAddbaReq;
++
++	init_mlme_ext_timer(padapter);
++
++#ifdef CONFIG_AP_MODE
++	init_mlme_ap_info(padapter);
++#endif
++
++	pmlmeext->last_scan_time = 0;
++	pmlmeext->mlmeext_init = _TRUE;
++
++
++#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++	pmlmeext->active_keep_alive_check = _TRUE;
++#else
++	pmlmeext->active_keep_alive_check = _FALSE;
++#endif
++
++#ifdef DBG_FIXED_CHAN
++	pmlmeext->fixed_chan = 0xFF;
++#endif
++
++	pmlmeext->tsf_update_pause_factor = pregistrypriv->tsf_update_pause_factor;
++	pmlmeext->tsf_update_restore_factor = pregistrypriv->tsf_update_restore_factor;
++
++#ifdef CONFIG_SUPPORT_STATIC_SMPS
++	pmlmeext->ssmps_en = _FALSE;
++	pmlmeext->ssmps_tx_tp_th = SSMPS_TX_TP_TH;/*Mbps*/
++	pmlmeext->ssmps_rx_tp_th = SSMPS_RX_TP_TH;/*Mbps*/
++	#ifdef DBG_STATIC_SMPS
++	pmlmeext->ssmps_test = _FALSE;
++	#endif
++#endif
++
++#ifdef CONFIG_CTRL_TXSS_BY_TP
++	pmlmeext->txss_ctrl_en = _TRUE;
++	pmlmeext->txss_tp_th = TXSS_TP_TH;
++	pmlmeext->txss_tp_chk_cnt = TXSS_TP_CHK_CNT;
++#endif
++
++	return res;
++
++}
++
++void free_mlme_ext_priv(struct mlme_ext_priv *pmlmeext)
++{
++	_adapter *padapter = pmlmeext->padapter;
++
++	if (!padapter)
++		return;
++
++	if (rtw_is_drv_stopped(padapter)) {
++		_cancel_timer_ex(&pmlmeext->survey_timer);
++		_cancel_timer_ex(&pmlmeext->link_timer);
++	}
++}
++
++#ifdef CONFIG_PATCH_JOIN_WRONG_CHANNEL
++static u8 cmp_pkt_chnl_diff(_adapter *padapter, u8 *pframe, uint packet_len)
++{
++	/* if the channel is same, return 0. else return channel differential	 */
++	uint len;
++	u8 channel;
++	u8 *p;
++
++	p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_, _DSSET_IE_, &len, packet_len - _BEACON_IE_OFFSET_);
++	if (p) {
++		channel = *(p + 2);
++		if (padapter->mlmeextpriv.cur_channel >= channel)
++			return padapter->mlmeextpriv.cur_channel - channel;
++		else
++			return channel - padapter->mlmeextpriv.cur_channel;
++	} else
++		return 0;
++}
++#endif /* CONFIG_PATCH_JOIN_WRONG_CHANNEL */
++
++static void _mgt_dispatcher(_adapter *padapter, struct mlme_handler *ptable, union recv_frame *precv_frame)
++{
++	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++
++	if (ptable->func) {
++		/* receive the frames that ra(a1) is my address or ra(a1) is bc address. */
++		if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN) &&
++		    !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN))
++#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++		{
++			struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++
++			if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) != _TRUE)
++				return;
++
++		    if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE)
++				return;
++
++		    if ( pwdev_priv->pno_mac_addr[0] == 0xFF)
++				return;
++
++		    if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_pno_mac_addr(padapter), ETH_ALEN))
++				return;
++		}
++#else
++			return;
++#endif
++
++		ptable->func(padapter, precv_frame);
++	}
++
++}
++
++void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame)
++{
++	int index;
++	struct mlme_handler *ptable;
++	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(pframe));
++	struct recv_priv  *precvpriv = &padapter->recvpriv;
++
++
++#if 0
++	{
++		u8 *pbuf;
++		pbuf = GetAddr1Ptr(pframe);
++		RTW_INFO("A1-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5));
++		pbuf = get_addr2_ptr(pframe);
++		RTW_INFO("A2-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5));
++		pbuf = GetAddr3Ptr(pframe);
++		RTW_INFO("A3-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5));
++	}
++#endif
++
++	if (GetFrameType(pframe) != WIFI_MGT_TYPE) {
++		return;
++	}
++
++	/* receive the frames that ra(a1) is my address or ra(a1) is bc address. */
++	if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN) &&
++	    !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN))
++#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++		{
++			struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++
++			if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) != _TRUE)
++				return;
++
++			if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE)
++				return;
++
++			if ( pwdev_priv->pno_mac_addr[0] == 0xFF)
++				return;
++
++			if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_pno_mac_addr(padapter), ETH_ALEN))
++				return;
++		}
++#else
++		return;
++#endif
++
++	ptable = mlme_sta_tbl;
++
++	index = get_frame_sub_type(pframe) >> 4;
++
++#ifdef CONFIG_TDLS
++	if ((index << 4) == WIFI_ACTION) {
++		/* category==public (4), action==TDLS_DISCOVERY_RESPONSE */
++		if (*(pframe + 24) == RTW_WLAN_CATEGORY_PUBLIC && *(pframe + 25) == TDLS_DISCOVERY_RESPONSE) {
++			RTW_INFO("[TDLS] Recv %s from "MAC_FMT"\n", rtw_tdls_action_txt(TDLS_DISCOVERY_RESPONSE), MAC_ARG(get_addr2_ptr(pframe)));
++			On_TDLS_Dis_Rsp(padapter, precv_frame);
++		}
++	}
++#endif /* CONFIG_TDLS */
++
++	if (index >= (sizeof(mlme_sta_tbl) / sizeof(struct mlme_handler))) {
++		return;
++	}
++	ptable += index;
++
++#if 1
++	if (psta != NULL) {
++		if (GetRetry(pframe)) {
++			if (precv_frame->u.hdr.attrib.seq_num == psta->RxMgmtFrameSeqNum) {
++				/* drop the duplicate management frame */
++				precvpriv->dbg_rx_dup_mgt_frame_drop_count++;
++				RTW_INFO("Drop duplicate management frame with seq_num = %d.\n", precv_frame->u.hdr.attrib.seq_num);
++				return;
++			}
++		}
++		psta->RxMgmtFrameSeqNum = precv_frame->u.hdr.attrib.seq_num;
++	}
++#else
++
++	if (GetRetry(pframe)) {
++		/* return; */
++	}
++#endif
++
++#ifdef CONFIG_AP_MODE
++	switch (get_frame_sub_type(pframe)) {
++	case WIFI_AUTH:
++		if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter))
++			ptable->func = &OnAuth;
++		else
++			ptable->func = &OnAuthClient;
++	/* pass through */
++	case WIFI_ASSOCREQ:
++	case WIFI_REASSOCREQ:
++		_mgt_dispatcher(padapter, ptable, precv_frame);
++		#ifdef CONFIG_HOSTAPD_MLME
++		if (MLME_IS_AP(padapter))
++			rtw_hostapd_mlme_rx(padapter, precv_frame);
++		#endif
++		break;
++	case WIFI_PROBEREQ:
++		_mgt_dispatcher(padapter, ptable, precv_frame);
++		#ifdef CONFIG_HOSTAPD_MLME
++		if (MLME_IS_AP(padapter))
++			rtw_hostapd_mlme_rx(padapter, precv_frame);
++		#endif
++		break;
++	case WIFI_BEACON:
++		_mgt_dispatcher(padapter, ptable, precv_frame);
++		break;
++	case WIFI_ACTION:
++		_mgt_dispatcher(padapter, ptable, precv_frame);
++		break;
++	default:
++		_mgt_dispatcher(padapter, ptable, precv_frame);
++		#ifdef CONFIG_HOSTAPD_MLME
++		if (MLME_IS_AP(padapter))
++			rtw_hostapd_mlme_rx(padapter, precv_frame);
++		#endif
++		break;
++	}
++#else
++
++	_mgt_dispatcher(padapter, ptable, precv_frame);
++
++#endif
++
++}
++
++#ifdef CONFIG_P2P
++u32 p2p_listen_state_process(_adapter *padapter, unsigned char *da)
++{
++	bool response = _TRUE;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) {
++		if (rtw_cfg80211_get_is_roch(padapter) == _FALSE
++			|| rtw_get_oper_ch(padapter) != padapter->wdinfo.listen_channel
++			|| adapter_wdev_data(padapter)->p2p_enabled == _FALSE
++			|| padapter->mlmepriv.wps_probe_resp_ie == NULL
++			|| padapter->mlmepriv.p2p_probe_resp_ie == NULL
++		) {
++#ifdef CONFIG_DEBUG_CFG80211
++			RTW_INFO(ADPT_FMT" DON'T issue_probersp_p2p: p2p_enabled:%d, wps_probe_resp_ie:%p, p2p_probe_resp_ie:%p\n"
++				, ADPT_ARG(padapter)
++				, adapter_wdev_data(padapter)->p2p_enabled
++				, padapter->mlmepriv.wps_probe_resp_ie
++				, padapter->mlmepriv.p2p_probe_resp_ie);
++			RTW_INFO(ADPT_FMT" DON'T issue_probersp_p2p: is_ro_ch:%d, op_ch:%d, p2p_listen_channel:%d\n"
++				, ADPT_ARG(padapter)
++				, rtw_cfg80211_get_is_roch(padapter)
++				, rtw_get_oper_ch(padapter)
++				, padapter->wdinfo.listen_channel);
++#endif
++			response = _FALSE;
++		}
++	} else
++#endif /* CONFIG_IOCTL_CFG80211 */
++		if (padapter->wdinfo.driver_interface == DRIVER_WEXT) {
++			/*	do nothing if the device name is empty */
++			if (!padapter->wdinfo.device_name_len)
++				response	= _FALSE;
++		}
++
++	if (response == _TRUE)
++		issue_probersp_p2p(padapter, da);
++
++	return _SUCCESS;
++}
++#endif /* CONFIG_P2P */
++
++
++/****************************************************************************
++
++Following are the callback functions for each subtype of the management frames
++
++*****************************************************************************/
++
++unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame)
++{
++	unsigned int	ielen;
++	unsigned char	*p;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX	*cur = &(pmlmeinfo->network);
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	uint len = precv_frame->u.hdr.len;
++	u8 is_valid_p2p_probereq = _FALSE;
++
++#ifdef CONFIG_ATMEL_RC_PATCH
++	u8 *target_ie = NULL, *wps_ie = NULL;
++	u8 *start;
++	uint search_len = 0, wps_ielen = 0, target_ielen = 0;
++	struct sta_info	*psta;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++#endif
++
++
++#ifdef CONFIG_P2P
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++	struct rx_pkt_attrib	*pattrib = &precv_frame->u.hdr.attrib;
++	u8 wifi_test_chk_rate = 1;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if ((pwdinfo->driver_interface == DRIVER_CFG80211)
++	    && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
++	    && (GET_CFG80211_REPORT_MGMT(adapter_wdev_data(padapter), IEEE80211_STYPE_PROBE_REQ) == _TRUE)
++	) {
++		rtw_cfg80211_rx_probe_request(padapter, precv_frame);
++		return _SUCCESS;
++	}
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) &&
++	    !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) &&
++	    !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) &&
++	    !rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) &&
++	    !rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN)
++	   ) {
++		/*	Commented by Albert 2011/03/17 */
++		/*	mcs_rate = 0->CCK 1M rate */
++		/*	mcs_rate = 1->CCK 2M rate */
++		/*	mcs_rate = 2->CCK 5.5M rate */
++		/*	mcs_rate = 3->CCK 11M rate */
++		/*	In the P2P mode, the driver should not support the CCK rate */
++
++		/*	Commented by Kurt 2012/10/16 */
++		/*	IOT issue: Google Nexus7 use 1M rate to send p2p_probe_req after GO nego completed and Nexus7 is client */
++		if (padapter->registrypriv.wifi_spec == 1) {
++			if (pattrib->data_rate <= DESC_RATE11M)
++				wifi_test_chk_rate = 0;
++		}
++
++		if (wifi_test_chk_rate == 1) {
++			is_valid_p2p_probereq = process_probe_req_p2p_ie(pwdinfo, pframe, len);
++			if (is_valid_p2p_probereq == _TRUE) {
++				if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) {
++					/* FIXME */
++					if (padapter->wdinfo.driver_interface == DRIVER_WEXT)
++						report_survey_event(padapter, precv_frame);
++
++					p2p_listen_state_process(padapter,  get_sa(pframe));
++
++					return _SUCCESS;
++				}
++
++				if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++					goto _continue;
++			}
++		}
++	}
++
++_continue:
++#endif /* CONFIG_P2P */
++
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
++		return _SUCCESS;
++
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE &&
++	    check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE | WIFI_MESH_STATE) == _FALSE)
++		return _SUCCESS;
++
++
++	/* RTW_INFO("+OnProbeReq\n"); */
++
++
++#ifdef CONFIG_ATMEL_RC_PATCH
++	wps_ie = rtw_get_wps_ie(
++			      pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_,
++			      len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_,
++			      NULL, &wps_ielen);
++	if (wps_ie)
++		target_ie = rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_MANUFACTURER, NULL, &target_ielen);
++	if ((target_ie && (target_ielen == 4)) && (_TRUE == _rtw_memcmp((void *)target_ie, "Ozmo", 4))) {
++		/* psta->flag_atmel_rc = 1; */
++		unsigned char *sa_addr = get_sa(pframe);
++		printk("%s: Find Ozmo RC -- %02x:%02x:%02x:%02x:%02x:%02x  \n\n",
++		       __func__, *sa_addr, *(sa_addr + 1), *(sa_addr + 2), *(sa_addr + 3), *(sa_addr + 4), *(sa_addr + 5));
++		_rtw_memcpy(pstapriv->atmel_rc_pattern, get_sa(pframe), ETH_ALEN);
++	}
++#endif
++
++
++#ifdef CONFIG_AUTO_AP_MODE
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE &&
++	    pmlmepriv->cur_network.join_res == _TRUE) {
++		_irqL	irqL;
++		struct sta_info	*psta;
++		u8 *mac_addr, *peer_addr;
++		struct sta_priv *pstapriv = &padapter->stapriv;
++		u8 RC_OUI[4] = {0x00, 0xE0, 0x4C, 0x0A};
++		/* EID[1] + EID_LEN[1] + RC_OUI[4] + MAC[6] + PairingID[2] + ChannelNum[2] */
++
++		p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, (int *)&ielen,
++			       len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
++
++		if (!p || ielen != 14)
++			goto _non_rc_device;
++
++		if (!_rtw_memcmp(p + 2, RC_OUI, sizeof(RC_OUI)))
++			goto _non_rc_device;
++
++		if (!_rtw_memcmp(p + 6, get_sa(pframe), ETH_ALEN)) {
++			RTW_INFO("%s, do rc pairing ("MAC_FMT"), but mac addr mismatch!("MAC_FMT")\n", __FUNCTION__,
++				 MAC_ARG(get_sa(pframe)), MAC_ARG(p + 6));
++
++			goto _non_rc_device;
++		}
++
++		RTW_INFO("%s, got the pairing device("MAC_FMT")\n", __FUNCTION__,  MAC_ARG(get_sa(pframe)));
++
++		/* new a station */
++		psta = rtw_get_stainfo(pstapriv, get_sa(pframe));
++		if (psta == NULL) {
++			/* allocate a new one */
++			RTW_INFO("going to alloc stainfo for rc="MAC_FMT"\n",  MAC_ARG(get_sa(pframe)));
++			psta = rtw_alloc_stainfo(pstapriv, get_sa(pframe));
++			if (psta == NULL) {
++				/* TODO: */
++				RTW_INFO(" Exceed the upper limit of supported clients...\n");
++				return _SUCCESS;
++			}
++
++			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++			if (rtw_is_list_empty(&psta->asoc_list)) {
++				psta->expire_to = pstapriv->expire_to;
++				rtw_list_insert_tail(&psta->asoc_list, &pstapriv->asoc_list);
++				pstapriv->asoc_list_cnt++;
++				#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++				if (psta->tbtx_enable)
++					pstapriv->tbtx_asoc_list_cnt++;
++				#endif
++			}
++			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++			/* generate pairing ID */
++			mac_addr = adapter_mac_addr(padapter);
++			peer_addr = psta->cmn.mac_addr;
++			psta->pid = (u16)(((mac_addr[4] << 8) + mac_addr[5]) + ((peer_addr[4] << 8) + peer_addr[5]));
++
++			/* update peer stainfo */
++			psta->isrc = _TRUE;
++
++			/* AID assignment */
++			if (psta->cmn.aid > 0)
++				RTW_INFO(FUNC_ADPT_FMT" old AID=%d\n", FUNC_ADPT_ARG(padapter), psta->cmn.aid);
++			else {
++				if (!rtw_aid_alloc(padapter, psta)) {
++					RTW_INFO(FUNC_ADPT_FMT" no room for more AIDs\n", FUNC_ADPT_ARG(padapter));
++					return _SUCCESS;
++				}
++				RTW_INFO(FUNC_ADPT_FMT" allocate new AID=%d\n", FUNC_ADPT_ARG(padapter), psta->cmn.aid);
++			}
++
++			psta->qos_option = 1;
++			psta->cmn.bw_mode = CHANNEL_WIDTH_20;
++			psta->ieee8021x_blocked = _FALSE;
++#ifdef CONFIG_80211N_HT
++			if(padapter->registrypriv.ht_enable &&
++				is_supported_ht(padapter->registrypriv.wireless_mode)) {
++				psta->htpriv.ht_option = _TRUE;
++				psta->htpriv.ampdu_enable = _FALSE;
++				psta->htpriv.sgi_20m = _FALSE;
++				psta->htpriv.sgi_40m = _FALSE;
++				psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++				psta->htpriv.agg_enable_bitmap = 0x0;/* reset */
++				psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */
++			}
++#endif
++
++			rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);
++
++			_rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats));
++
++			_enter_critical_bh(&psta->lock, &irqL);
++			psta->state |= WIFI_ASOC_STATE;
++			_exit_critical_bh(&psta->lock, &irqL);
++
++			report_add_sta_event(padapter, psta->cmn.mac_addr);
++
++		}
++
++		issue_probersp(padapter, get_sa(pframe), _FALSE);
++
++		return _SUCCESS;
++
++	}
++
++_non_rc_device:
++
++	return _SUCCESS;
++
++#endif /* CONFIG_AUTO_AP_MODE */
++
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) &&
++	    rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING | WIFI_UNDER_SURVEY)) {
++		/* don't process probe req */
++		return _SUCCESS;
++	}
++#endif
++
++	p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ielen,
++		       len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
++
++
++	/* check (wildcard) SSID */
++	if (p != NULL) {
++		if (is_valid_p2p_probereq == _TRUE)
++			goto _issue_probersp;
++
++		if ((ielen != 0 && _FALSE == _rtw_memcmp((void *)(p + 2), (void *)cur->Ssid.Ssid, cur->Ssid.SsidLength))
++			|| (ielen == 0 && pmlmeinfo->hidden_ssid_mode))
++			goto exit;
++
++		#ifdef CONFIG_RTW_MESH
++		if (MLME_IS_MESH(padapter)) {
++			p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, WLAN_EID_MESH_ID, (int *)&ielen,
++					len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
++
++			if (!p)
++				goto exit;
++			if (ielen != 0 && _rtw_memcmp((void *)(p + 2), (void *)cur->mesh_id.Ssid, cur->mesh_id.SsidLength) == _FALSE)
++				goto exit;
++		}
++		#endif
++
++_issue_probersp:
++		if (((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE &&
++		      pmlmepriv->cur_network.join_res == _TRUE)) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) {
++			/* RTW_INFO("+issue_probersp during ap mode\n"); */
++			issue_probersp(padapter, get_sa(pframe), is_valid_p2p_probereq);
++		}
++
++	}
++
++exit:
++	return _SUCCESS;
++
++}
++
++unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame)
++{
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	u8	*pframe = precv_frame->u.hdr.rx_data;
++#ifdef CONFIG_P2P
++	struct wifidirect_info	*pwdinfo = &padapter->wdinfo;
++#endif
++
++
++#ifdef CONFIG_P2P
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) {
++		if (_TRUE == pwdinfo->tx_prov_disc_info.benable) {
++			if (_rtw_memcmp(pwdinfo->tx_prov_disc_info.peerIFAddr, get_addr2_ptr(pframe), ETH_ALEN)) {
++				if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
++					pwdinfo->tx_prov_disc_info.benable = _FALSE;
++					issue_p2p_provision_request(padapter,
++						pwdinfo->tx_prov_disc_info.ssid.Ssid,
++						pwdinfo->tx_prov_disc_info.ssid.SsidLength,
++						pwdinfo->tx_prov_disc_info.peerDevAddr);
++				} else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++					pwdinfo->tx_prov_disc_info.benable = _FALSE;
++					issue_p2p_provision_request(padapter,
++								    NULL,
++								    0,
++						pwdinfo->tx_prov_disc_info.peerDevAddr);
++				}
++			}
++		}
++		return _SUCCESS;
++	} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) {
++		if (_TRUE == pwdinfo->nego_req_info.benable) {
++			RTW_INFO("[%s] P2P State is GONEGO ING!\n", __FUNCTION__);
++			if (_rtw_memcmp(pwdinfo->nego_req_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN)) {
++				pwdinfo->nego_req_info.benable = _FALSE;
++				issue_p2p_GO_request(padapter, pwdinfo->nego_req_info.peerDevAddr);
++			}
++		}
++	} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ)) {
++		if (_TRUE == pwdinfo->invitereq_info.benable) {
++			RTW_INFO("[%s] P2P_STATE_TX_INVITE_REQ!\n", __FUNCTION__);
++			if (_rtw_memcmp(pwdinfo->invitereq_info.peer_macaddr, get_addr2_ptr(pframe), ETH_ALEN)) {
++				pwdinfo->invitereq_info.benable = _FALSE;
++				issue_p2p_invitation_request(padapter, pwdinfo->invitereq_info.peer_macaddr);
++			}
++		}
++	}
++#endif
++
++
++	if ((mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS))
++		|| (MLME_IS_MESH(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE))
++		#ifdef CONFIG_RTW_REPEATER_SON
++		|| (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS)
++		#endif
++	) {
++		struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++		if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)
++			&& (pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
++		) {
++			if (!rtw_check_bcn_info(padapter, pframe, precv_frame->u.hdr.len)) {
++				RTW_PRINT(FUNC_ADPT_FMT" ap has changed, disconnect now\n", FUNC_ADPT_ARG(padapter));
++				receive_disconnect(padapter, pmlmeinfo->network.MacAddress , 0, _FALSE);
++			}
++		}
++
++		rtw_mi_report_survey_event(padapter, precv_frame);
++		return _SUCCESS;
++	}
++
++#if 0 /* move to validate_recv_mgnt_frame */
++	if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) {
++		if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) {
++			psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
++			if (psta != NULL)
++				psta->sta_stats.rx_mgnt_pkts++;
++		}
++	}
++#endif
++
++	return _SUCCESS;
++
++}
++
++/* for 11n Logo 4.2.31/4.2.32 */
++static void rtw_check_legacy_ap(_adapter *padapter, u8 *pframe, u32 len)
++{
++
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++	if (!padapter->registrypriv.wifi_spec)
++		return;
++	
++	if(!MLME_IS_AP(padapter))
++		return;
++	
++
++	if (pmlmeext->bstart_bss == _TRUE) {
++		int left;
++		unsigned char *pos;
++		struct rtw_ieee802_11_elems elems;
++#ifdef CONFIG_80211N_HT
++		u16 cur_op_mode; 
++#endif
++		/* checking IEs */
++		left = len - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_;
++		pos = pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_;
++		if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) {
++			RTW_INFO("%s: parse fail for "MAC_FMT"\n", __func__, MAC_ARG(GetAddr3Ptr(pframe)));
++			return;
++		}
++#ifdef CONFIG_80211N_HT
++		cur_op_mode = pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_OP_MODE_MASK;
++#endif
++		/* for legacy ap */
++		if (elems.ht_capabilities == NULL && elems.ht_capabilities_len == 0) {
++
++			if (0)
++				RTW_INFO("%s: "MAC_FMT" is legacy ap\n", __func__, MAC_ARG(GetAddr3Ptr(pframe)));
++
++			ATOMIC_SET(&pmlmepriv->olbc, _TRUE);
++			ATOMIC_SET(&pmlmepriv->olbc_ht, _TRUE);
++		}
++			
++	}
++}
++
++unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)
++{
++	struct sta_info	*psta;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct sta_priv	*pstapriv = &padapter->stapriv;
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	uint len = precv_frame->u.hdr.len;
++	WLAN_BSSID_EX *pbss;
++	int ret = _SUCCESS;
++#ifdef CONFIG_TDLS
++	struct sta_info *ptdls_sta;
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++#ifdef CONFIG_TDLS_CH_SW
++	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
++#endif
++#endif /* CONFIG_TDLS */
++
++	if (validate_beacon_len(pframe, len) == _FALSE)
++		return _SUCCESS;
++
++	if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)
++		|| (MLME_IS_MESH(padapter) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
++	) {
++		if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)
++			&& (pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
++		) {
++			if (!rtw_check_bcn_info(padapter, pframe, len)) {
++				RTW_PRINT(FUNC_ADPT_FMT" ap has changed, disconnect now\n", FUNC_ADPT_ARG(padapter));
++				receive_disconnect(padapter, pmlmeinfo->network.MacAddress , 0, _FALSE);
++			}
++		}
++
++		rtw_mi_report_survey_event(padapter, precv_frame);
++		return _SUCCESS;
++	}
++#ifdef CONFIG_RTW_REPEATER_SON
++	if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS)
++		rtw_mi_report_survey_event(padapter, precv_frame);
++#endif
++
++	rtw_check_legacy_ap(padapter, pframe, len);
++
++	if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) {
++		if ((pmlmeinfo->state & WIFI_FW_AUTH_NULL)
++			&& (rtw_sta_linking_test_wait_done() || pmlmeext->join_abort)
++		) {
++			if (rtw_sta_linking_test_force_fail() || pmlmeext->join_abort) {
++				set_link_timer(pmlmeext, 1);
++				return _SUCCESS;
++			}
++
++			/* we should update current network before auth, or some IE is wrong */
++			pbss = (WLAN_BSSID_EX *)rtw_malloc(sizeof(WLAN_BSSID_EX));
++			if (pbss) {
++				if (collect_bss_info(padapter, precv_frame, pbss) == _SUCCESS) {
++					struct beacon_keys recv_beacon;
++
++					update_network(&(pmlmepriv->cur_network.network), pbss, padapter, _TRUE);
++
++					/* update bcn keys */
++					if (rtw_get_bcn_keys(padapter, pframe, len, &recv_beacon) == _TRUE) {
++						RTW_INFO("%s: beacon keys ready\n", __func__);
++						_rtw_memcpy(&pmlmepriv->cur_beacon_keys,
++							&recv_beacon, sizeof(recv_beacon));
++						if (is_hidden_ssid(recv_beacon.ssid, recv_beacon.ssid_len)) {
++							_rtw_memcpy(pmlmepriv->cur_beacon_keys.ssid, pmlmeinfo->network.Ssid.Ssid, IW_ESSID_MAX_SIZE);
++							pmlmepriv->cur_beacon_keys.ssid_len = pmlmeinfo->network.Ssid.SsidLength;
++						}
++					} else {
++						RTW_ERR("%s: get beacon keys failed\n", __func__);
++						_rtw_memset(&pmlmepriv->cur_beacon_keys, 0, sizeof(recv_beacon));
++					}
++					#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
++					pmlmepriv->new_beacon_cnts = 0;
++					#endif
++				}
++				rtw_mfree((u8 *)pbss, sizeof(WLAN_BSSID_EX));
++			}
++
++			/* check the vendor of the assoc AP */
++			pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pframe + sizeof(struct rtw_ieee80211_hdr_3addr), len - sizeof(struct rtw_ieee80211_hdr_3addr));
++
++			/* update TSF Value */
++			update_TSF(pmlmeext, pframe, len);
++			pmlmeext->bcn_cnt = 0;
++			pmlmeext->last_bcn_cnt = 0;
++
++#ifdef CONFIG_P2P_PS
++			/* Comment by YiWei , in wifi p2p spec the "3.3 P2P Power Management" , "These mechanisms are available in a P2P Group in which only P2P Devices are associated." */
++			/* process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)); */
++#endif /* CONFIG_P2P_PS */
++
++#if defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)
++			if (padapter->registrypriv.wifi_spec) {
++				if (process_p2p_cross_connect_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)) == _FALSE) {
++					if (rtw_mi_buddy_check_mlmeinfo_state(padapter, WIFI_FW_AP_STATE)) {
++						RTW_PRINT("no issue auth, P2P cross-connect does not permit\n ");
++						return _SUCCESS;
++					}
++				}
++			}
++#endif /* CONFIG_P2P CONFIG_P2P and CONFIG_CONCURRENT_MODE */
++
++			/* start auth */
++			start_clnt_auth(padapter);
++
++			return _SUCCESS;
++		}
++
++		if (((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) {
++			psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
++			if (psta != NULL) {
++#ifdef CONFIG_PATCH_JOIN_WRONG_CHANNEL
++				/* Merge from 8712 FW code */
++				if (cmp_pkt_chnl_diff(padapter, pframe, len) != 0) {
++					/* join wrong channel, deauth and reconnect           */
++					issue_deauth(padapter, (&(pmlmeinfo->network))->MacAddress, WLAN_REASON_DEAUTH_LEAVING);
++
++					report_del_sta_event(padapter, (&(pmlmeinfo->network))->MacAddress, WLAN_REASON_JOIN_WRONG_CHANNEL, _TRUE, _FALSE);
++					pmlmeinfo->state &= (~WIFI_FW_ASSOC_SUCCESS);
++					return _SUCCESS;
++				}
++#endif /* CONFIG_PATCH_JOIN_WRONG_CHANNEL */
++#ifdef CONFIG_RTW_80211R
++				rtw_ft_update_bcn(padapter, precv_frame);
++#endif
++				ret = rtw_check_bcn_info(padapter, pframe, len);
++				if (!ret) {
++					RTW_PRINT(FUNC_ADPT_FMT" ap has changed, disconnect now\n", FUNC_ADPT_ARG(padapter));
++					receive_disconnect(padapter, pmlmeinfo->network.MacAddress , 0, _FALSE);
++					return _SUCCESS;
++				}
++				/* update WMM, ERP in the beacon */
++				/* todo: the timer is used instead of the number of the beacon received */
++				if ((sta_rx_pkts(psta) & 0xf) == 0) {
++					/* RTW_INFO("update_bcn_info\n"); */
++					update_beacon_info(padapter, pframe, len, psta);
++				}
++
++				pmlmepriv->cur_network_scanned->network.Rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power;
++				pmlmeext->bcn_cnt++;
++#ifdef CONFIG_BCN_RECV_TIME
++				rtw_rx_bcn_time_update(padapter, len, precv_frame->u.hdr.attrib.data_rate);
++#endif
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_TDLS_CH_SW
++				if (rtw_tdls_is_chsw_allowed(padapter) == _TRUE) {
++					/* Send TDLS Channel Switch Request when receiving Beacon */
++					if ((padapter->tdlsinfo.chsw_info.ch_sw_state & TDLS_CH_SW_INITIATOR_STATE) && (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE)
++					    && (pmlmeext->cur_channel == rtw_get_oper_ch(padapter))) {
++						ptdls_sta = rtw_get_stainfo(&padapter->stapriv, padapter->tdlsinfo.chsw_info.addr);
++						if (ptdls_sta != NULL) {
++							if (ptdls_sta->tdls_sta_state | TDLS_LINKED_STATE)
++								_set_timer(&ptdls_sta->stay_on_base_chnl_timer, TDLS_CH_SW_STAY_ON_BASE_CHNL_TIMEOUT);
++						}
++					}
++				}
++#endif
++#endif /* CONFIG_TDLS */
++
++				#if CONFIG_DFS
++				process_csa_ie(padapter
++					, pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_
++					, len - (WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_));
++				#endif
++
++#ifdef CONFIG_P2P_PS
++				process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN));
++#endif /* CONFIG_P2P_PS */
++
++				if (pmlmeext->tsf_update_required && pmlmeext->en_hw_update_tsf)
++					rtw_enable_hw_update_tsf_cmd(padapter);
++
++#if 0 /* move to validate_recv_mgnt_frame */
++				psta->sta_stats.rx_mgnt_pkts++;
++#endif
++			}
++
++		} else if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
++			u8 rate_set[16];
++			u8 rate_num = 0;
++
++			psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
++			if (psta != NULL) {
++				/*
++				* update WMM, ERP in the beacon
++				* todo: the timer is used instead of the number of the beacon received
++				*/
++				if ((sta_rx_pkts(psta) & 0xf) == 0)
++					update_beacon_info(padapter, pframe, len, psta);
++
++				if (pmlmeext->tsf_update_required && pmlmeext->en_hw_update_tsf)
++					rtw_enable_hw_update_tsf_cmd(padapter);
++			} else {
++				rtw_ies_get_supported_rate(pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_, len - WLAN_HDR_A3_LEN - _BEACON_IE_OFFSET_, rate_set, &rate_num);
++				if (rate_num == 0) {
++					RTW_INFO(FUNC_ADPT_FMT" RX beacon with no supported rate\n", FUNC_ADPT_ARG(padapter));
++					goto _END_ONBEACON_;
++				}
++
++				psta = rtw_alloc_stainfo(pstapriv, get_addr2_ptr(pframe));
++				if (psta == NULL) {
++					RTW_INFO(FUNC_ADPT_FMT" Exceed the upper limit of supported clients\n", FUNC_ADPT_ARG(padapter));
++					goto _END_ONBEACON_;
++				}
++
++				psta->expire_to = pstapriv->adhoc_expire_to;
++
++				_rtw_memcpy(psta->bssrateset, rate_set, rate_num);
++				psta->bssratelen = rate_num;
++
++				/* update TSF Value */
++				update_TSF(pmlmeext, pframe, len);
++
++				/* report sta add event */
++				report_add_sta_event(padapter, get_addr2_ptr(pframe));
++			}
++		}
++	}
++
++_END_ONBEACON_:
++
++	return _SUCCESS;
++
++}
++
++static u32 rtw_get_sta_num_by_state(_adapter *padapter, u32 state)
++{
++	_irqL irqL;
++	_list	*plist, *phead;
++	u32	index, sta_num = 0;
++	struct sta_info *psta = NULL;
++	struct sta_priv *pstapriv = &(padapter->stapriv);
++
++	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);	
++	for (index = 0; index < NUM_STA; index++) {		
++		phead = &(pstapriv->sta_hash[index]);
++		plist = get_next(phead);
++		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++			psta = LIST_CONTAINOR(plist, struct sta_info , hash_list);
++			if ((psta->state & (state)))
++				sta_num++;
++			plist = get_next(plist);
++		}
++	}
++	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++	/* RTW_INFO("%s : waiting for %u sta under linking \n", __func__, sta_num); */
++	return sta_num;
++}
++
++static u8  rtw_defs_attack_chk(_adapter *padapter)
++{
++	struct mlme_priv *mlme = &(padapter->mlmepriv);
++	u8 is_reject = _FALSE;
++	u32 sta_limit = 0;
++	u32 stime = rtw_systime_to_ms(rtw_get_current_time());
++	static u32 ptime = 0;
++
++	/* RTW_INFO("%s : ptime=%u, stime=%u, diff=%u\n", __func__, ptime, stime, (stime - ptime)); */
++	if ((ptime > 0) && ((stime - ptime) < mlme->defs_lmt_time)) {
++		sta_limit = rtw_get_sta_num_by_state(padapter, WIFI_FW_LINKING_STATE);
++		if (sta_limit >= mlme->defs_lmt_sta)
++			is_reject = _TRUE;
++	}
++
++	ptime = stime;
++	/* RTW_INFO("%s : current linking num=%u\n", __func__, sta_limit); */
++	return is_reject;	
++}
++
++unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame)
++{
++#ifdef CONFIG_AP_MODE
++	_irqL irqL;
++	unsigned int	auth_mode, seq, ie_len;
++	unsigned char	*sa, *p;
++	u16	algorithm;
++	int	status;
++	static struct sta_info stat;
++	struct	sta_info	*pstat = NULL;
++	struct	sta_priv *pstapriv = &padapter->stapriv;
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	uint len = precv_frame->u.hdr.len;
++	u8	offset = 0;
++
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) &&
++	    rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING | WIFI_UNDER_SURVEY)) {
++		/* don't process auth request; */
++		return _SUCCESS;
++	}
++#endif /* CONFIG_CONCURRENT_MODE */
++
++	if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
++		return _FAIL;
++
++	if (!MLME_IS_ASOC(padapter))
++		return _SUCCESS;
++
++#if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_RTW_MESH)
++	if (MLME_IS_MESH(padapter))
++		return rtw_mesh_on_auth(padapter, precv_frame);
++#endif
++
++	RTW_INFO("+OnAuth\n");
++
++	sa = get_addr2_ptr(pframe);
++
++	auth_mode = psecuritypriv->dot11AuthAlgrthm;
++
++	if (GetPrivacy(pframe)) {
++		u8	*iv;
++		struct rx_pkt_attrib	*prxattrib = &(precv_frame->u.hdr.attrib);
++
++		prxattrib->hdrlen = WLAN_HDR_A3_LEN;
++		prxattrib->encrypt = _WEP40_;
++
++		iv = pframe + prxattrib->hdrlen;
++		prxattrib->key_index = ((iv[3] >> 6) & 0x3);
++
++		prxattrib->iv_len = 4;
++		prxattrib->icv_len = 4;
++
++		rtw_wep_decrypt(padapter, (u8 *)precv_frame);
++
++		offset = 4;
++	}
++
++	algorithm = le16_to_cpu(*(u16 *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset));
++	seq	= le16_to_cpu(*(u16 *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2));
++
++	RTW_INFO("auth alg=%x, seq=%X\n", algorithm, seq);
++
++	if (rtw_check_invalid_mac_address(sa, _FALSE)){
++		RTW_INFO("%s : reject invalid AUTH-req "MAC_FMT"\n", 
++			__func__, MAC_ARG(get_addr2_ptr(pframe)));
++		return _FAIL;
++	}
++
++	if(rtw_defs_attack_chk(padapter))  {
++		struct sta_info *_psta;
++		_psta = rtw_get_stainfo(pstapriv, sa);
++		if ((_psta == NULL) || !(_psta->state & WIFI_FW_ASSOC_SUCCESS)) {
++			status = _STATS_REFUSED_TEMPORARILY_;
++			RTW_ERR("%s : refused temporarily for sa "MAC_FMT" !\n", __func__, MAC_ARG(sa));
++			goto auth_fail;
++		}
++	}
++
++	if (rtw_ap_linking_test_force_auth_fail()) {
++		status = rtw_ap_linking_test_force_auth_fail();
++		RTW_INFO(FUNC_ADPT_FMT" force auth fail with status:%u\n"
++			, FUNC_ADPT_ARG(padapter), status);
++		goto auth_fail;
++	}
++
++	if ((auth_mode == 2) && (algorithm != WLAN_AUTH_SAE) &&
++	    (psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) &&
++	    (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_))
++		auth_mode = 0;
++
++	if ((algorithm > 0 && auth_mode == 0) ||	/* rx a shared-key auth but shared not enabled */
++	    (algorithm == 0 && auth_mode == 1)) {	/* rx a open-system auth but shared-key is enabled */
++		RTW_INFO("auth rejected due to bad alg [alg=%d, auth_mib=%d] %02X%02X%02X%02X%02X%02X\n",
++			algorithm, auth_mode, sa[0], sa[1], sa[2], sa[3], sa[4], sa[5]);
++
++		status = _STATS_NO_SUPP_ALG_;
++
++		goto auth_fail;
++	}
++
++#if CONFIG_RTW_MACADDR_ACL
++	if (rtw_access_ctrl(padapter, sa) == _FALSE) {
++		status = _STATS_UNABLE_HANDLE_STA_;
++		goto auth_fail;
++	}
++#endif
++
++	pstat = rtw_get_stainfo(pstapriv, sa);
++	if (pstat == NULL) {
++
++		/* allocate a new one */
++		RTW_INFO("going to alloc stainfo for sa="MAC_FMT"\n",  MAC_ARG(sa));
++		pstat = rtw_alloc_stainfo(pstapriv, sa);
++		if (pstat == NULL) {
++			RTW_INFO(" Exceed the upper limit of supported clients...\n");
++			status = _STATS_UNABLE_HANDLE_STA_;
++			goto auth_fail;
++		}
++
++		pstat->state = WIFI_FW_AUTH_NULL;
++		pstat->auth_seq = 0;
++
++		/* pstat->flags = 0; */
++		/* pstat->capability = 0; */
++	} else {
++#ifdef CONFIG_IEEE80211W
++		if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) 
++			|| !(pstat->flags & WLAN_STA_MFP))
++#endif /* CONFIG_IEEE80211W */
++		{
++
++			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++			if (rtw_is_list_empty(&pstat->asoc_list) == _FALSE) {
++				rtw_list_delete(&pstat->asoc_list);
++				pstapriv->asoc_list_cnt--;
++				#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++				if (pstat->tbtx_enable)
++					pstapriv->tbtx_asoc_list_cnt--;
++				#endif
++				if (pstat->expire_to > 0)
++					;/* TODO: STA re_auth within expire_to */
++			}
++			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++			if (seq == 1)
++				; /* TODO: STA re_auth and auth timeout */
++
++		}
++	}
++
++#ifdef CONFIG_IEEE80211W
++	if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) 
++		|| !(pstat->flags & WLAN_STA_MFP))
++#endif /* CONFIG_IEEE80211W */
++	{
++		_enter_critical_bh(&pstapriv->auth_list_lock, &irqL);
++		if (rtw_is_list_empty(&pstat->auth_list)) {
++
++			rtw_list_insert_tail(&pstat->auth_list, &pstapriv->auth_list);
++			pstapriv->auth_list_cnt++;
++		}
++		_exit_critical_bh(&pstapriv->auth_list_lock, &irqL);
++	}
++
++	if (pstat->auth_seq == 0)
++		pstat->expire_to = pstapriv->auth_to;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (GET_CFG80211_REPORT_MGMT(adapter_wdev_data(padapter), IEEE80211_STYPE_AUTH) == _TRUE) {
++		if ((algorithm == WLAN_AUTH_SAE) &&
++			(auth_mode == dot11AuthAlgrthm_8021X)) {
++			pstat->authalg = algorithm;
++
++			rtw_cfg80211_rx_mframe(padapter, precv_frame, NULL);
++			return _SUCCESS;
++		}
++	}
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++	if ((pstat->auth_seq + 1) != seq) {
++		RTW_INFO("(1)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n",
++			 seq, pstat->auth_seq + 1);
++		status = _STATS_OUT_OF_AUTH_SEQ_;
++		goto auth_fail;
++	}
++
++	if (algorithm == 0 && (auth_mode == 0 || auth_mode == 2 || auth_mode == 3)) {
++		if (seq == 1) {
++#ifdef CONFIG_IEEE80211W
++			if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) 
++				|| !(pstat->flags & WLAN_STA_MFP))
++#endif /* CONFIG_IEEE80211W */
++			{
++				pstat->state &= ~WIFI_FW_AUTH_NULL;
++				pstat->state |= WIFI_FW_AUTH_SUCCESS;
++				pstat->expire_to = pstapriv->assoc_to;
++			}
++			pstat->authalg = algorithm;
++		} else {
++			RTW_INFO("(2)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n",
++				 seq, pstat->auth_seq + 1);
++			status = _STATS_OUT_OF_AUTH_SEQ_;
++			goto auth_fail;
++		}
++	} else { /* shared system or auto authentication */
++		if (seq == 1) {
++			/* prepare for the challenging txt... */
++
++			/* get_random_bytes((void *)pstat->chg_txt, 128); */ /* TODO: */
++			_rtw_memset((void *)pstat->chg_txt, 78, 128);
++#ifdef CONFIG_IEEE80211W
++			if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) 
++				|| !(pstat->flags & WLAN_STA_MFP))
++#endif /* CONFIG_IEEE80211W */
++			{
++				pstat->state &= ~WIFI_FW_AUTH_NULL;
++				pstat->state |= WIFI_FW_AUTH_STATE;
++			}
++			pstat->authalg = algorithm;
++			pstat->auth_seq = 2;
++		} else if (seq == 3) {
++			/* checking for challenging txt... */
++			RTW_INFO("checking for challenging txt...\n");
++
++			p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + 4 + _AUTH_IE_OFFSET_ , _CHLGETXT_IE_, (int *)&ie_len,
++				len - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_ - 4);
++
++			if ((p == NULL) || (ie_len <= 0)) {
++				RTW_INFO("auth rejected because challenge failure!(1)\n");
++				status = _STATS_CHALLENGE_FAIL_;
++				goto auth_fail;
++			}
++
++			if (_rtw_memcmp((void *)(p + 2), pstat->chg_txt, 128)) {
++#ifdef CONFIG_IEEE80211W
++				if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) 
++					|| !(pstat->flags & WLAN_STA_MFP))
++#endif /* CONFIG_IEEE80211W */
++				{
++					pstat->state &= (~WIFI_FW_AUTH_STATE);
++					pstat->state |= WIFI_FW_AUTH_SUCCESS;
++					/* challenging txt is correct... */
++					pstat->expire_to =  pstapriv->assoc_to;
++				}
++			} else {
++				RTW_INFO("auth rejected because challenge failure!\n");
++				status = _STATS_CHALLENGE_FAIL_;
++				goto auth_fail;
++			}
++		} else {
++			RTW_INFO("(3)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n",
++				 seq, pstat->auth_seq + 1);
++			status = _STATS_OUT_OF_AUTH_SEQ_;
++			goto auth_fail;
++		}
++	}
++
++
++	/* Now, we are going to issue_auth... */
++	pstat->auth_seq = seq + 1;
++
++#ifdef CONFIG_NATIVEAP_MLME
++	issue_auth(padapter, pstat, (unsigned short)(_STATS_SUCCESSFUL_));
++#endif
++
++	if ((pstat->state & WIFI_FW_AUTH_SUCCESS) || (pstat->state & WIFI_FW_ASSOC_SUCCESS))
++		pstat->auth_seq = 0;
++
++
++	return _SUCCESS;
++
++auth_fail:
++
++	if (pstat)
++		rtw_free_stainfo(padapter , pstat);
++
++	pstat = &stat;
++	_rtw_memset((char *)pstat, '\0', sizeof(stat));
++	pstat->auth_seq = 2;
++	_rtw_memcpy(pstat->cmn.mac_addr, sa, ETH_ALEN);
++
++#ifdef CONFIG_NATIVEAP_MLME
++	issue_auth(padapter, pstat, (unsigned short)status);
++#endif
++
++#endif
++	return _FAIL;
++
++}
++
++unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame)
++{
++	unsigned int	seq, len, status, algthm, offset;
++	unsigned char	*p;
++	unsigned int	go2asoc = 0;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	uint pkt_len = precv_frame->u.hdr.len;
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (GET_CFG80211_REPORT_MGMT(adapter_wdev_data(padapter), IEEE80211_STYPE_AUTH) == _TRUE) {
++		if (rtw_sec_chk_auth_type(padapter, MLME_AUTHTYPE_SAE)) {
++			if (rtw_cached_pmkid(padapter, get_my_bssid(&pmlmeinfo->network)) != -1) {
++				RTW_INFO("SAE: PMKSA cache entry found\n");
++				goto normal;
++			}
++			rtw_cfg80211_rx_mframe(padapter, precv_frame, NULL);
++			return _SUCCESS;
++		}
++	}
++
++normal:
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++	/* check A1 matches or not */
++	if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN))
++		return _SUCCESS;
++
++	if (!(pmlmeinfo->state & WIFI_FW_AUTH_STATE) || pmlmeext->join_abort)
++		return _SUCCESS;
++
++	offset = (GetPrivacy(pframe)) ? 4 : 0;
++
++	algthm	= le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset));
++	seq	= le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2));
++	status	= le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 4));
++
++	if (status != 0) {
++		RTW_INFO("clnt auth fail, status: %d\n", status);
++		if (status == 13) { /* && pmlmeinfo->auth_algo == dot11AuthAlgrthm_Auto) */
++			if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared)
++				pmlmeinfo->auth_algo = dot11AuthAlgrthm_Open;
++			else
++				pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared;
++			/* pmlmeinfo->reauth_count = 0; */
++		}
++
++		pmlmeinfo->auth_status = status;
++		set_link_timer(pmlmeext, 1);
++		goto authclnt_fail;
++	}
++
++	if (seq == 2) {
++		if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) {
++			/* legendary shared system */
++			p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _AUTH_IE_OFFSET_, _CHLGETXT_IE_, (int *)&len,
++				pkt_len - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_);
++
++			if (p == NULL) {
++				/* RTW_INFO("marc: no challenge text?\n"); */
++				goto authclnt_fail;
++			}
++
++			_rtw_memcpy((void *)(pmlmeinfo->chg_txt), (void *)(p + 2), len);
++			pmlmeinfo->auth_seq = 3;
++			issue_auth(padapter, NULL, 0);
++			set_link_timer(pmlmeext, REAUTH_TO);
++
++			return _SUCCESS;
++		} else {
++			/* open, or 802.11r FTAA system */
++			go2asoc = 1;
++		}
++	} else if (seq == 4) {
++		if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared)
++			go2asoc = 1;
++		else
++			goto authclnt_fail;
++	} else {
++		/* this is also illegal */
++		/* RTW_INFO("marc: clnt auth failed due to illegal seq=%x\n", seq); */
++		goto authclnt_fail;
++	}
++
++	if (go2asoc) {
++#ifdef CONFIG_RTW_80211R
++		if (rtw_ft_update_auth_rsp_ies(padapter, pframe, pkt_len))
++			return _SUCCESS;
++#endif
++		RTW_PRINT("auth success, start assoc\n");
++		start_clnt_assoc(padapter);
++		return _SUCCESS;
++	}
++
++authclnt_fail:
++
++	/* pmlmeinfo->state &= ~(WIFI_FW_AUTH_STATE); */
++
++	return _FAIL;
++
++}
++
++unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
++{
++#ifdef CONFIG_AP_MODE
++	_irqL irqL;
++	u16 listen_interval;
++	struct rtw_ieee802_11_elems elems;
++	struct sta_info	*pstat;
++	unsigned char		reassoc, *pos;
++	int		left;
++	unsigned short		status = _STATS_SUCCESSFUL_;
++	unsigned short		frame_type, ie_offset = 0;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX	*cur = &(pmlmeinfo->network);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	uint pkt_len = precv_frame->u.hdr.len;
++#ifdef CONFIG_P2P
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++	u8 p2p_status_code = P2P_STATUS_SUCCESS;
++	u8 *p2pie;
++	u32 p2pielen = 0;
++#endif /* CONFIG_P2P */
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	u8 sta_tbtx_enable = _FALSE;
++#endif
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) &&
++	    rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING | WIFI_UNDER_SURVEY)) {
++		/* don't process assoc request; */
++		return _SUCCESS;
++	}
++#endif /* CONFIG_CONCURRENT_MODE */
++
++	if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
++		return _FAIL;
++
++	if (rtw_check_invalid_mac_address(get_addr2_ptr(pframe), _FALSE)) {
++		RTW_INFO("%s : reject invalid ASSOC-req "MAC_FMT"\n", 
++			__func__, MAC_ARG(get_addr2_ptr(pframe)));
++		return _FAIL;
++	}
++
++	frame_type = get_frame_sub_type(pframe);
++	if (frame_type == WIFI_ASSOCREQ) {
++		reassoc = 0;
++		ie_offset = _ASOCREQ_IE_OFFSET_;
++	} else { /* WIFI_REASSOCREQ */
++		reassoc = 1;
++		ie_offset = _REASOCREQ_IE_OFFSET_;
++	}
++
++
++	if (pkt_len < IEEE80211_3ADDR_LEN + ie_offset) {
++		RTW_INFO("handle_assoc(reassoc=%d) - too short payload (len=%lu)"
++			 "\n", reassoc, (unsigned long)pkt_len);
++		return _FAIL;
++	}
++
++	pstat = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
++	if (pstat == (struct sta_info *)NULL) {
++		status = _RSON_CLS2_;
++		goto asoc_class2_error;
++	}
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	if (pstat->authalg == WLAN_AUTH_SAE) {
++		/* WPA3-SAE */
++		if (((pstat->state) & WIFI_FW_AUTH_NULL)) {
++			/* TODO:
++			   Queue AssocReq and Proccess
++			   by external auth trigger. */
++			RTW_INFO("%s: wait external auth trigger\n", __func__);
++			return _SUCCESS;
++		}
++	}
++
++	/* check if this stat has been successfully authenticated/assocated */
++	if (!((pstat->state) & WIFI_FW_AUTH_SUCCESS)) {
++		if (!((pstat->state) & WIFI_FW_ASSOC_SUCCESS)) {
++			status = _RSON_CLS2_;
++			goto asoc_class2_error;
++		} else {
++			pstat->state &= (~WIFI_FW_ASSOC_SUCCESS);
++			pstat->state |= WIFI_FW_ASSOC_STATE;
++		}
++	} else {
++		pstat->state &= (~WIFI_FW_AUTH_SUCCESS);
++		pstat->state |= WIFI_FW_ASSOC_STATE;
++	}
++
++#if 0/* todo:tkip_countermeasures */
++	if (hapd->tkip_countermeasures) {
++		resp = WLAN_REASON_MICHAEL_MIC_FAILURE;
++		goto fail;
++	}
++#endif
++
++	if (rtw_ap_linking_test_force_asoc_fail()) {
++		status = rtw_ap_linking_test_force_asoc_fail();
++		RTW_INFO(FUNC_ADPT_FMT" force asoc fail with status:%u\n"
++			, FUNC_ADPT_ARG(padapter), status);
++		goto OnAssocReqFail;
++	}
++
++	/* now parse all ieee802_11 ie to point to elems */
++	left = pkt_len - (IEEE80211_3ADDR_LEN + ie_offset);
++	pos = pframe + (IEEE80211_3ADDR_LEN + ie_offset);
++	if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) {
++		RTW_INFO("STA " MAC_FMT " sent invalid association request\n",
++			 MAC_ARG(pstat->cmn.mac_addr));
++		status = _STATS_FAILURE_;
++		goto OnAssocReqFail;
++	}
++
++	rtw_ap_parse_sta_capability(padapter, pstat, pframe + WLAN_HDR_A3_LEN);
++
++	listen_interval = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN + 2);
++#if 0/* todo: */
++	/* check listen_interval */
++	if (listen_interval > hapd->conf->max_listen_interval) {
++		hostapd_logger(hapd, mgmt->sa, HOSTAPD_MODULE_IEEE80211,
++			       HOSTAPD_LEVEL_DEBUG,
++			       "Too large Listen Interval (%d)",
++			       listen_interval);
++		resp = WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE;
++		goto fail;
++	}
++
++	pstat->listen_interval = listen_interval;
++#endif
++
++	/* now we should check all the fields... */
++	/* checking SSID */
++	if (elems.ssid == NULL
++		|| elems.ssid_len == 0
++		|| elems.ssid_len != cur->Ssid.SsidLength
++		|| _rtw_memcmp(elems.ssid, cur->Ssid.Ssid, cur->Ssid.SsidLength) == _FALSE
++	) {
++		status = _STATS_FAILURE_;
++		goto OnAssocReqFail;
++	}
++
++	/* (Extended) Supported rates */
++	status = rtw_ap_parse_sta_supported_rates(padapter, pstat
++		, pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset);
++	if (status != _STATS_SUCCESSFUL_)
++		goto OnAssocReqFail;
++
++	/* check RSN/WPA/WPS */
++	status = rtw_ap_parse_sta_security_ie(padapter, pstat, &elems);
++	if (status != _STATS_SUCCESSFUL_)
++		goto OnAssocReqFail;
++
++	/* check if there is WMM IE & support WWM-PS */
++	rtw_ap_parse_sta_wmm_ie(padapter, pstat
++		, pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset);
++
++#ifdef CONFIG_RTS_FULL_BW
++	/*check vendor IE*/
++	rtw_parse_sta_vendor_ie_8812(padapter, pstat
++		, pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset);
++#endif/*CONFIG_RTS_FULL_BW*/
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	if (elems.tbtx_cap && elems.tbtx_cap_len != 0) {
++		if(rtw_is_tbtx_capabilty(elems.tbtx_cap, elems.tbtx_cap_len)) {
++			sta_tbtx_enable = _TRUE;
++		}
++	}
++
++#endif
++
++	rtw_ap_parse_sta_ht_ie(padapter, pstat, &elems);
++	rtw_ap_parse_sta_vht_ie(padapter, pstat, &elems);
++
++	if (((pstat->flags & WLAN_STA_HT) || (pstat->flags & WLAN_STA_VHT)) &&
++	    ((pstat->wpa2_pairwise_cipher & WPA_CIPHER_TKIP) ||
++	     (pstat->wpa_pairwise_cipher & WPA_CIPHER_TKIP))) {
++
++		RTW_INFO("(V)HT: " MAC_FMT " tried to use TKIP with (V)HT association\n", MAC_ARG(pstat->cmn.mac_addr));
++
++		pstat->flags &= ~WLAN_STA_HT;
++		pstat->flags &= ~WLAN_STA_VHT;
++		/*status = WLAN_STATUS_CIPHER_REJECTED_PER_POLICY;
++		  * goto OnAssocReqFail;
++		*/
++	}
++
++#ifdef CONFIG_P2P
++	pstat->is_p2p_device = _FALSE;
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++		p2pie = rtw_get_p2p_ie(pframe + WLAN_HDR_A3_LEN + ie_offset , pkt_len - WLAN_HDR_A3_LEN - ie_offset , NULL, &p2pielen);
++		if (p2pie) {
++			pstat->is_p2p_device = _TRUE;
++			p2p_status_code = (u8)process_assoc_req_p2p_ie(pwdinfo, pframe, pkt_len, pstat);
++			if (p2p_status_code > 0) {
++				pstat->p2p_status_code = p2p_status_code;
++				status = _STATS_CAP_FAIL_;
++				goto OnAssocReqFail;
++			}
++		}
++#ifdef CONFIG_WFD
++		rtw_process_wfd_ies(padapter, pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset, __func__);
++#endif
++	}
++	pstat->p2p_status_code = p2p_status_code;
++#endif /* CONFIG_P2P */
++
++	rtw_ap_parse_sta_multi_ap_ie(padapter, pstat, pos, left);
++
++#ifdef CONFIG_RTW_REPEATER_SON
++	if (rtw_rson_ap_check_sta(padapter, pframe, pkt_len, ie_offset))
++		goto OnAssocReqFail;
++#endif
++
++	/* TODO: identify_proprietary_vendor_ie(); */
++	/* Realtek proprietary IE */
++	/* identify if this is Broadcom sta */
++	/* identify if this is ralink sta */
++	/* Customer proprietary IE */
++
++#ifdef CONFIG_RTW_80211K
++	rtw_ap_parse_sta_rm_en_cap(padapter, pstat, &elems);
++#endif
++
++	/* AID assignment */
++	if (pstat->cmn.aid > 0)
++		RTW_INFO(FUNC_ADPT_FMT" old AID=%d\n", FUNC_ADPT_ARG(padapter), pstat->cmn.aid);
++	else {
++		if (!rtw_aid_alloc(padapter, pstat)) {
++			RTW_INFO(FUNC_ADPT_FMT" no room for more AIDs\n", FUNC_ADPT_ARG(padapter));
++			status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA;
++			goto OnAssocReqFail;
++		}
++		RTW_INFO(FUNC_ADPT_FMT" allocate new AID=%d\n", FUNC_ADPT_ARG(padapter), pstat->cmn.aid);
++	}
++
++	pstat->state &= (~WIFI_FW_ASSOC_STATE);
++	pstat->state |= WIFI_FW_ASSOC_SUCCESS;
++	/* RTW_INFO("==================%s, %d,  (%x), bpairwise_key_installed=%d, MAC:"MAC_FMT"\n"
++	, __func__, __LINE__, pstat->state, pstat->bpairwise_key_installed, MAC_ARG(pstat->cmn.mac_addr)); */
++#ifdef CONFIG_IEEE80211W
++	if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) 
++		|| !(pstat->flags & WLAN_STA_MFP))
++#endif /* CONFIG_IEEE80211W */
++	{
++		_enter_critical_bh(&pstapriv->auth_list_lock, &irqL);
++		if (!rtw_is_list_empty(&pstat->auth_list)) {
++			rtw_list_delete(&pstat->auth_list);
++			pstapriv->auth_list_cnt--;
++		}
++		_exit_critical_bh(&pstapriv->auth_list_lock, &irqL);
++
++		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++		if (rtw_is_list_empty(&pstat->asoc_list)) {
++			pstat->expire_to = pstapriv->expire_to;
++			rtw_list_insert_tail(&pstat->asoc_list, &pstapriv->asoc_list);
++			pstapriv->asoc_list_cnt++;
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++			if (sta_tbtx_enable) {
++				pstat->tbtx_enable = _TRUE;
++				pstapriv->tbtx_asoc_list_cnt++;
++			}
++#endif
++		}
++		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++	}
++
++	/* now the station is qualified to join our BSS...	 */
++	if (pstat && (pstat->state & WIFI_FW_ASSOC_SUCCESS) && (_STATS_SUCCESSFUL_ == status)) {
++#ifdef CONFIG_NATIVEAP_MLME
++#ifdef CONFIG_IEEE80211W
++		if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) 
++			|| !(pstat->flags & WLAN_STA_MFP))
++#endif /* CONFIG_IEEE80211W */
++		{
++			/* .1 bss_cap_update & sta_info_update */
++			bss_cap_update_on_sta_join(padapter, pstat);
++			sta_info_update(padapter, pstat);
++		}
++#ifdef CONFIG_IEEE80211W
++		if (pstat->bpairwise_key_installed == _TRUE && (pstat->flags & WLAN_STA_MFP))
++			status = _STATS_REFUSED_TEMPORARILY_;
++#endif /* CONFIG_IEEE80211W */
++		/* .2 issue assoc rsp before notify station join event. */
++		if (frame_type == WIFI_ASSOCREQ)
++			issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP);
++		else
++			issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP);
++
++#ifdef CONFIG_IOCTL_CFG80211
++		_enter_critical_bh(&pstat->lock, &irqL);
++		if (pstat->passoc_req) {
++			rtw_mfree(pstat->passoc_req, pstat->assoc_req_len);
++			pstat->passoc_req = NULL;
++			pstat->assoc_req_len = 0;
++		}
++
++		pstat->passoc_req =  rtw_zmalloc(pkt_len);
++		if (pstat->passoc_req) {
++			_rtw_memcpy(pstat->passoc_req, pframe, pkt_len);
++			pstat->assoc_req_len = pkt_len;
++		}
++		_exit_critical_bh(&pstat->lock, &irqL);
++#endif /* CONFIG_IOCTL_CFG80211 */
++#ifdef CONFIG_IEEE80211W
++		if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) 
++			|| !(pstat->flags & WLAN_STA_MFP))
++#endif /* CONFIG_IEEE80211W */
++		{
++			/* .3-(1) report sta add event */
++			report_add_sta_event(padapter, pstat->cmn.mac_addr);
++		}
++#ifdef CONFIG_IEEE80211W
++		if (pstat->bpairwise_key_installed == _TRUE && (pstat->flags & WLAN_STA_MFP)) {
++			RTW_INFO(MAC_FMT"\n", MAC_ARG(pstat->cmn.mac_addr));
++			issue_action_SA_Query(padapter, pstat->cmn.mac_addr, 0, 0, IEEE80211W_RIGHT_KEY);
++		}
++#endif /* CONFIG_IEEE80211W */
++#endif /* CONFIG_NATIVEAP_MLME */
++	}
++
++	return _SUCCESS;
++
++asoc_class2_error:
++
++#ifdef CONFIG_NATIVEAP_MLME
++	issue_deauth(padapter, (void *)get_addr2_ptr(pframe), status);
++#endif
++
++	return _FAIL;
++
++OnAssocReqFail:
++
++
++#ifdef CONFIG_NATIVEAP_MLME
++	/* pstat->cmn.aid = 0; */
++	if (frame_type == WIFI_ASSOCREQ)
++		issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP);
++	else
++		issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP);
++#endif
++
++
++#endif /* CONFIG_AP_MODE */
++
++	return _FAIL;
++
++}
++
++#if defined(CONFIG_LAYER2_ROAMING) && defined(CONFIG_RTW_80211K)
++void rtw_roam_nb_discover(_adapter *padapter, u8 bfroce)
++{
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);	
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct sta_info *psta;
++	u8 nb_req_issue = _FALSE;
++
++	if (!check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
++		return;
++
++	if (!rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE))
++		return;
++
++	psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
++	if (!psta)
++		return;
++	
++	if (bfroce || (!pmlmepriv->nb_info.nb_rpt_is_same))
++		nb_req_issue = _TRUE;
++	
++	if (nb_req_issue && (psta->rm_en_cap[0] & RTW_RRM_NB_RPT_EN)) 
++		rm_add_nb_req(padapter, psta);
++}
++#endif
++
++unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame)
++{
++	uint i;
++	int res;
++	unsigned short	status;
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	/* WLAN_BSSID_EX 		*cur_network = &(pmlmeinfo->network); */
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	uint pkt_len = precv_frame->u.hdr.len;
++#ifdef CONFIG_WAPI_SUPPORT
++	PNDIS_802_11_VARIABLE_IEs	pWapiIE = NULL;
++#endif
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	/* check A1 matches or not */
++	if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN))
++		return _SUCCESS;
++
++	if (!(pmlmeinfo->state & (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE)) || pmlmeext->join_abort)
++		return _SUCCESS;
++
++	if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
++		return _SUCCESS;
++
++	_cancel_timer_ex(&pmlmeext->link_timer);
++
++	/* status */
++	status = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 2));
++	if (status > 0) {
++		RTW_INFO("assoc reject, status code: %d\n", status);
++		pmlmeinfo->state = WIFI_FW_NULL_STATE;
++		res = -4;
++		goto report_assoc_result;
++	}
++
++	/* get capabilities */
++	pmlmeinfo->capability = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));
++
++	/* set slot time */
++	pmlmeinfo->slotTime = (pmlmeinfo->capability & BIT(10)) ? 9 : 20;
++
++	/* AID */
++	res = pmlmeinfo->aid = (int)(le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 4)) & 0x3fff);
++	
++	/* check aid value */
++	if (res < 1 || res > 2007) {
++		RTW_INFO("assoc reject, aid: %d\n", res);
++		pmlmeinfo->state = WIFI_FW_NULL_STATE;
++		res = -4;
++		goto report_assoc_result;
++	}
++
++	/* following are moved to join event callback function */
++	/* to handle HT, WMM, rate adaptive, update MAC reg */
++	/* for not to handle the synchronous IO in the tasklet */
++	for (i = (6 + WLAN_HDR_A3_LEN); i < pkt_len;) {
++		pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i);
++
++		switch (pIE->ElementID) {
++		case _VENDOR_SPECIFIC_IE_:
++			if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6))	/* WMM */
++				WMM_param_handler(padapter, pIE);
++#if defined(CONFIG_P2P) && defined(CONFIG_WFD)
++			else if (_rtw_memcmp(pIE->data, WFD_OUI, 4))		/* WFD */
++				rtw_process_wfd_ie(padapter, (u8 *)pIE, pIE->Length, __func__);
++#endif
++			break;
++
++#ifdef CONFIG_WAPI_SUPPORT
++		case _WAPI_IE_:
++			pWapiIE = pIE;
++			break;
++#endif
++
++		case _HT_CAPABILITY_IE_:	/* HT caps */
++			HT_caps_handler(padapter, pIE);
++#ifdef ROKU_PRIVATE
++			HT_caps_handler_infra_ap(padapter, pIE);
++#endif /* ROKU_PRIVATE */
++			break;
++
++		case _HT_EXTRA_INFO_IE_:	/* HT info */
++			HT_info_handler(padapter, pIE);
++			break;
++
++#ifdef CONFIG_80211AC_VHT
++		case EID_VHTCapability:
++			VHT_caps_handler(padapter, pIE);
++#ifdef ROKU_PRIVATE
++			VHT_caps_handler_infra_ap(padapter, pIE);
++#endif /* ROKU_PRIVATE */
++			break;
++
++		case EID_VHTOperation:
++			VHT_operation_handler(padapter, pIE);
++			break;
++#endif
++
++		case _ERPINFO_IE_:
++			ERP_IE_handler(padapter, pIE);
++			break;
++#ifdef CONFIG_TDLS
++		case _EXT_CAP_IE_:
++			if (check_ap_tdls_prohibited(pIE->data, pIE->Length) == _TRUE)
++				padapter->tdlsinfo.ap_prohibited = _TRUE;
++			if (check_ap_tdls_ch_switching_prohibited(pIE->data, pIE->Length) == _TRUE)
++				padapter->tdlsinfo.ch_switch_prohibited = _TRUE;
++			break;
++#endif /* CONFIG_TDLS */
++
++#ifdef CONFIG_RTW_80211K
++		case _EID_RRM_EN_CAP_IE_:
++			RM_IE_handler(padapter, pIE);
++			break;
++#endif
++
++#ifdef ROKU_PRIVATE
++		/* Infra mode, used to store AP's info , Parse the supported rates from AssocRsp */
++		case _SUPPORTEDRATES_IE_:
++			Supported_rate_infra_ap(padapter, pIE);
++			break;
++
++		case _EXT_SUPPORTEDRATES_IE_:
++			Extended_Supported_rate_infra_ap(padapter, pIE);
++			break;
++#endif /* ROKU_PRIVATE */
++		default:
++			break;
++		}
++
++		i += (pIE->Length + 2);
++	}
++
++#ifdef CONFIG_WAPI_SUPPORT
++	rtw_wapi_on_assoc_ok(padapter, pIE);
++#endif
++
++	pmlmeinfo->state &= (~WIFI_FW_ASSOC_STATE);
++	pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
++
++	/* Update Basic Rate Table for spec, 2010-12-28 , by thomas */
++	UpdateBrateTbl(padapter, pmlmeinfo->network.SupportedRates);
++
++report_assoc_result:
++	if (res > 0)
++		rtw_buf_update(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len, pframe, pkt_len);
++	else
++		rtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len);
++
++	report_join_res(padapter, res, status);
++
++#if defined(CONFIG_LAYER2_ROAMING) && defined(CONFIG_RTW_80211K)
++	rtw_roam_nb_discover(padapter, _TRUE);
++#endif
++	return _SUCCESS;
++}
++
++unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame)
++{
++	unsigned short	reason;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++#ifdef CONFIG_P2P
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++#endif /* CONFIG_P2P */
++
++	/* check A3 */
++	if (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)))
++		return _SUCCESS;
++
++	RTW_INFO(FUNC_ADPT_FMT" - Start to Disconnect\n", FUNC_ADPT_ARG(padapter));
++
++#ifdef CONFIG_P2P
++	if (pwdinfo->rx_invitereq_info.scan_op_ch_only) {
++		_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);
++		_set_timer(&pwdinfo->reset_ch_sitesurvey, 10);
++	}
++#endif /* CONFIG_P2P */
++
++	reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));
++
++#ifdef CONFIG_AP_MODE
++	if (MLME_IS_AP(padapter)) {
++		_irqL irqL;
++		struct sta_info *psta;
++		struct sta_priv *pstapriv = &padapter->stapriv;
++
++		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
++		/* rtw_free_stainfo(padapter, psta); */
++		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
++
++		RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n"
++			, FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe));
++
++		psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
++		if (psta) {
++			u8 updated = _FALSE;
++
++			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++			if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
++				rtw_list_delete(&psta->asoc_list);
++				pstapriv->asoc_list_cnt--;
++				#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++				if (psta->tbtx_enable)
++					pstapriv->tbtx_asoc_list_cnt--;
++				#endif
++				updated = ap_free_sta(padapter, psta, _FALSE, reason, _TRUE);
++
++			}
++			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++			associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
++		}
++
++
++		return _SUCCESS;
++	} else
++#endif
++	if (!MLME_IS_MESH(padapter)) {
++		int	ignore_received_deauth = 0;
++
++		/*	Commented by Albert 20130604 */
++		/*	Before sending the auth frame to start the STA/GC mode connection with AP/GO,  */
++		/*	we will send the deauth first. */
++		/*	However, the Win8.1 with BRCM Wi-Fi will send the deauth with reason code 6 to us after receieving our deauth. */
++		/*	Added the following code to avoid this case. */
++		if ((pmlmeinfo->state & WIFI_FW_AUTH_STATE) ||
++		    (pmlmeinfo->state & WIFI_FW_ASSOC_STATE)) {
++			if (reason == WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA)
++				ignore_received_deauth = 1;
++			else if (WLAN_REASON_PREV_AUTH_NOT_VALID == reason) {
++				/* TODO: 802.11r */
++				ignore_received_deauth = 1;
++			}
++		}
++
++		RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM, ignore=%d\n"
++			, FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe), ignore_received_deauth);
++
++		if (0 == ignore_received_deauth)
++			receive_disconnect(padapter, get_addr2_ptr(pframe), reason, _FALSE);
++	}
++	pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
++	return _SUCCESS;
++
++}
++
++unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame)
++{
++	unsigned short	reason;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++#ifdef CONFIG_P2P
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++#endif /* CONFIG_P2P */
++
++	/* check A3 */
++	if (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)))
++		return _SUCCESS;
++
++	RTW_INFO(FUNC_ADPT_FMT" - Start to Disconnect\n", FUNC_ADPT_ARG(padapter));
++
++#ifdef CONFIG_P2P
++	if (pwdinfo->rx_invitereq_info.scan_op_ch_only) {
++		_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);
++		_set_timer(&pwdinfo->reset_ch_sitesurvey, 10);
++	}
++#endif /* CONFIG_P2P */
++
++	reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));
++
++#ifdef CONFIG_AP_MODE
++	if (MLME_IS_AP(padapter)) {
++		_irqL irqL;
++		struct sta_info *psta;
++		struct sta_priv *pstapriv = &padapter->stapriv;
++
++		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);	 */
++		/* rtw_free_stainfo(padapter, psta); */
++		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
++
++		RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n"
++			, FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe));
++
++		psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
++		if (psta) {
++			u8 updated = _FALSE;
++
++			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++			if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
++				rtw_list_delete(&psta->asoc_list);
++				pstapriv->asoc_list_cnt--;
++				#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++				if (psta->tbtx_enable)
++					pstapriv->tbtx_asoc_list_cnt--;
++				#endif
++				updated = ap_free_sta(padapter, psta, _FALSE, reason, _TRUE);
++
++			}
++			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++			associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
++		}
++
++		return _SUCCESS;
++	} else
++#endif
++	if (!MLME_IS_MESH(padapter)) {
++		RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n"
++			, FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe));
++
++	#ifdef CONFIG_RTW_WNM
++		if (rtw_wnm_try_btm_roam_imnt(padapter) > 0)
++	#endif
++		receive_disconnect(padapter, get_addr2_ptr(pframe), reason, _FALSE);
++	}
++	pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
++	return _SUCCESS;
++
++}
++
++unsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame)
++{
++	RTW_INFO("%s\n", __FUNCTION__);
++	return _SUCCESS;
++}
++
++unsigned int on_action_spct_ch_switch(_adapter *padapter, struct sta_info *psta, u8 *ies, uint ies_len)
++{
++	unsigned int ret = _FAIL;
++	struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(mlmeext->mlmext_info);
++
++	if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) {
++		ret = _SUCCESS;
++		goto exit;
++	}
++
++	if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) {
++
++		int ch_switch_mode = -1, ch = -1, ch_switch_cnt = -1;
++		int ch_offset = -1;
++		u8 bwmode;
++		struct ieee80211_info_element *ie;
++
++		RTW_INFO(FUNC_NDEV_FMT" from "MAC_FMT"\n",
++			FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(psta->cmn.mac_addr));
++
++		for_each_ie(ie, ies, ies_len) {
++			if (ie->id == WLAN_EID_CHANNEL_SWITCH) {
++				ch_switch_mode = ie->data[0];
++				ch = ie->data[1];
++				ch_switch_cnt = ie->data[2];
++				RTW_INFO("ch_switch_mode:%d, ch:%d, ch_switch_cnt:%d\n",
++					 ch_switch_mode, ch, ch_switch_cnt);
++			} else if (ie->id == WLAN_EID_SECONDARY_CHANNEL_OFFSET) {
++				ch_offset = secondary_ch_offset_to_hal_ch_offset(ie->data[0]);
++				RTW_INFO("ch_offset:%d\n", ch_offset);
++			}
++		}
++
++		if (ch == -1)
++			return _SUCCESS;
++
++		if (ch_offset == -1)
++			bwmode = mlmeext->cur_bwmode;
++		else
++			bwmode = (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) ?
++				 CHANNEL_WIDTH_20 : CHANNEL_WIDTH_40;
++
++		ch_offset = (ch_offset == -1) ? mlmeext->cur_ch_offset : ch_offset;
++
++		/* todo:
++		 * 1. the decision of channel switching
++		 * 2. things after channel switching
++		 */
++
++		ret = rtw_set_chbw_cmd(padapter, ch, bwmode, ch_offset, 0);
++	}
++
++exit:
++	return ret;
++}
++
++unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame)
++{
++	unsigned int ret = _FAIL;
++	struct sta_info *psta = NULL;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	uint frame_len = precv_frame->u.hdr.len;
++	u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++	u8 category;
++	u8 action;
++
++	psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
++
++	if (!psta)
++		goto exit;
++
++	category = frame_body[0];
++	if (category != RTW_WLAN_CATEGORY_SPECTRUM_MGMT)
++		goto exit;
++
++	action = frame_body[1];
++
++	RTW_INFO(FUNC_ADPT_FMT" action:%u\n", FUNC_ADPT_ARG(padapter), action);
++
++	switch (action) {
++	case RTW_WLAN_ACTION_SPCT_MSR_REQ:
++	case RTW_WLAN_ACTION_SPCT_MSR_RPRT:
++	case RTW_WLAN_ACTION_SPCT_TPC_REQ:
++	case RTW_WLAN_ACTION_SPCT_TPC_RPRT:
++		break;
++	case RTW_WLAN_ACTION_SPCT_CHL_SWITCH:
++#ifdef CONFIG_SPCT_CH_SWITCH
++		ret = on_action_spct_ch_switch(padapter, psta
++				, frame_body + 2, frame_len - (frame_body - pframe) - 2);
++#elif CONFIG_DFS
++		if (MLME_IS_STA(padapter) && MLME_IS_ASOC(padapter)) {
++			process_csa_ie(padapter
++				, frame_body + 2, frame_len - (frame_body - pframe) - 2);
++		}
++#endif
++		break;
++	default:
++		break;
++	}
++
++exit:
++	return ret;
++}
++
++unsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame)
++{
++	return _SUCCESS;
++}
++
++unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame)
++{
++	return _SUCCESS;
++}
++
++#ifdef CONFIG_RTW_WNM
++unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe)
++{
++	unsigned int ret = _FAIL;
++	struct sta_info *sta = NULL;
++	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++	struct sta_priv *stapriv = &(adapter->stapriv);
++	u8 *frame = rframe->u.hdr.rx_data;
++	u32 frame_len = rframe->u.hdr.len;
++	u8 *frame_body = (u8 *)(frame + sizeof(struct rtw_ieee80211_hdr_3addr));
++	u32 frame_body_len = frame_len - sizeof(struct rtw_ieee80211_hdr_3addr);	
++	u8 category, action;
++	int cnt = 0;
++	char msg[16];
++
++	sta = rtw_get_stainfo(stapriv, get_addr2_ptr(frame));
++	if (!sta)
++		goto exit;
++
++	category = frame_body[0];
++	if (category != RTW_WLAN_CATEGORY_WNM)
++		goto exit;
++
++	action = frame_body[1];
++
++	switch (action) {
++#ifdef CONFIG_RTW_80211R
++	case RTW_WLAN_ACTION_WNM_BTM_REQ:
++		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
++			RTW_INFO("WNM: BSS Transition Management Request recv.\n");
++			rtw_wnm_process_btm_req(adapter, frame_body, frame_body_len);
++		}
++		ret = _SUCCESS;
++		break;
++#endif		
++	default:
++		#ifdef CONFIG_IOCTL_CFG80211
++		cnt += sprintf((msg + cnt), "ACT_WNM %u", action);
++		rtw_cfg80211_rx_action(adapter, rframe, msg);
++		#endif
++		ret = _SUCCESS;
++		break;
++	}
++
++exit:
++	return ret;
++}
++#endif /* CONFIG_RTW_WNM */
++
++/**
++ * rtw_rx_ampdu_size - Get the target RX AMPDU buffer size for the specific @adapter
++ * @adapter: the adapter to get target RX AMPDU buffer size
++ *
++ * Returns: the target RX AMPDU buffer size
++ */
++u8 rtw_rx_ampdu_size(_adapter *adapter)
++{
++	u8 size;
++	HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor;
++
++#ifdef CONFIG_BT_COEXIST
++	if (rtw_btcoex_IsBTCoexCtrlAMPDUSize(adapter) == _TRUE) {
++		size = rtw_btcoex_GetAMPDUSize(adapter);
++		goto exit;
++	}
++#endif
++
++	/* for scan */
++	if (!mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_DISABLE)
++	    && !mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_COMPLETE)
++	    && adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_size != RX_AMPDU_SIZE_INVALID
++	   ) {
++		size = adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_size;
++		goto exit;
++	}
++
++	/* default value based on max_rx_ampdu_factor */
++	if (adapter->driver_rx_ampdu_factor != 0xFF)
++		max_rx_ampdu_factor = (HT_CAP_AMPDU_FACTOR)adapter->driver_rx_ampdu_factor;
++	else
++		rtw_hal_get_def_var(adapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor);
++	
++	/* In Maximum A-MPDU Length Exponent subfield of A-MPDU Parameters field of HT Capabilities element,
++		the unit of max_rx_ampdu_factor are octets. 8K, 16K, 32K, 64K is right.
++		But the buffer size subfield of Block Ack Parameter Set field in ADDBA action frame indicates
++		the number of buffers available for this particular TID. Each buffer is equal to max. size of 
++		MSDU or AMSDU. 
++		The size variable means how many MSDUs or AMSDUs, it's not Kbytes.
++	*/
++	if (MAX_AMPDU_FACTOR_64K == max_rx_ampdu_factor)
++		size = 64;
++	else if (MAX_AMPDU_FACTOR_32K == max_rx_ampdu_factor)
++		size = 32;
++	else if (MAX_AMPDU_FACTOR_16K == max_rx_ampdu_factor)
++		size = 16;
++	else if (MAX_AMPDU_FACTOR_8K == max_rx_ampdu_factor)
++		size = 8;
++	else
++		size = 64;
++
++exit:
++
++	if (size > 127)
++		size = 127;
++
++	return size;
++}
++
++/**
++ * rtw_rx_ampdu_is_accept - Get the permission if RX AMPDU should be set up for the specific @adapter
++ * @adapter: the adapter to get the permission if RX AMPDU should be set up
++ *
++ * Returns: accept or not
++ */
++bool rtw_rx_ampdu_is_accept(_adapter *adapter)
++{
++	bool accept;
++
++	if (adapter->fix_rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID) {
++		accept = adapter->fix_rx_ampdu_accept;
++		goto exit;
++	}
++
++#ifdef CONFIG_BT_COEXIST
++	if (rtw_btcoex_IsBTCoexRejectAMPDU(adapter) == _TRUE) {
++		accept = _FALSE;
++		goto exit;
++	}
++#endif
++
++	/* for scan */
++	if (!mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_DISABLE)
++	    && !mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_COMPLETE)
++	    && adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID
++	   ) {
++		accept = adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept;
++		goto exit;
++	}
++
++	/* default value for other cases */
++	accept = adapter->mlmeextpriv.mlmext_info.bAcceptAddbaReq;
++
++exit:
++	return accept;
++}
++
++/**
++ * rtw_rx_ampdu_set_size - Set the target RX AMPDU buffer size for the specific @adapter and specific @reason
++ * @adapter: the adapter to set target RX AMPDU buffer size
++ * @size: the target RX AMPDU buffer size to set
++ * @reason: reason for the target RX AMPDU buffer size setting
++ *
++ * Returns: whether the target RX AMPDU buffer size is changed
++ */
++bool rtw_rx_ampdu_set_size(_adapter *adapter, u8 size, u8 reason)
++{
++	bool is_adj = _FALSE;
++	struct mlme_ext_priv *mlmeext;
++	struct mlme_ext_info *mlmeinfo;
++
++	mlmeext = &adapter->mlmeextpriv;
++	mlmeinfo = &mlmeext->mlmext_info;
++
++	if (reason == RX_AMPDU_DRV_FIXED) {
++		if (adapter->fix_rx_ampdu_size != size) {
++			adapter->fix_rx_ampdu_size = size;
++			is_adj = _TRUE;
++			RTW_INFO(FUNC_ADPT_FMT" fix_rx_ampdu_size:%u\n", FUNC_ADPT_ARG(adapter), size);
++		}
++	} else if (reason == RX_AMPDU_DRV_SCAN) {
++		struct ss_res *ss = &adapter->mlmeextpriv.sitesurvey_res;
++
++		if (ss->rx_ampdu_size != size) {
++			ss->rx_ampdu_size = size;
++			is_adj = _TRUE;
++			RTW_INFO(FUNC_ADPT_FMT" ss.rx_ampdu_size:%u\n", FUNC_ADPT_ARG(adapter), size);
++		}
++	}
++
++	return is_adj;
++}
++
++/**
++ * rtw_rx_ampdu_set_accept - Set the permission if RX AMPDU should be set up for the specific @adapter and specific @reason
++ * @adapter: the adapter to set if RX AMPDU should be set up
++ * @accept: if RX AMPDU should be set up
++ * @reason: reason for the permission if RX AMPDU should be set up
++ *
++ * Returns: whether the permission if RX AMPDU should be set up is changed
++ */
++bool rtw_rx_ampdu_set_accept(_adapter *adapter, u8 accept, u8 reason)
++{
++	bool is_adj = _FALSE;
++	struct mlme_ext_priv *mlmeext;
++	struct mlme_ext_info *mlmeinfo;
++
++	mlmeext = &adapter->mlmeextpriv;
++	mlmeinfo = &mlmeext->mlmext_info;
++
++	if (reason == RX_AMPDU_DRV_FIXED) {
++		if (adapter->fix_rx_ampdu_accept != accept) {
++			adapter->fix_rx_ampdu_accept = accept;
++			is_adj = _TRUE;
++			RTW_INFO(FUNC_ADPT_FMT" fix_rx_ampdu_accept:%u\n", FUNC_ADPT_ARG(adapter), accept);
++		}
++	} else if (reason == RX_AMPDU_DRV_SCAN) {
++		if (adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept != accept) {
++			adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept = accept;
++			is_adj = _TRUE;
++			RTW_INFO(FUNC_ADPT_FMT" ss.rx_ampdu_accept:%u\n", FUNC_ADPT_ARG(adapter), accept);
++		}
++	}
++
++	return is_adj;
++}
++
++/**
++ * rx_ampdu_apply_sta_tid - Apply RX AMPDU setting to the specific @sta and @tid
++ * @adapter: the adapter to which @sta belongs
++ * @sta: the sta to be checked
++ * @tid: the tid to be checked
++ * @accept: the target permission if RX AMPDU should be set up
++ * @size: the target RX AMPDU buffer size
++ *
++ * Returns:
++ * 0: no canceled
++ * 1: canceled by no permission
++ * 2: canceled by different buffer size
++ * 3: canceled by potential mismatched status
++ *
++ * Blocking function, may sleep
++ */
++u8 rx_ampdu_apply_sta_tid(_adapter *adapter, struct sta_info *sta, u8 tid, u8 accept, u8 size)
++{
++	u8 ret = 0;
++	struct recv_reorder_ctrl *reorder_ctl = &sta->recvreorder_ctrl[tid];
++
++	if (reorder_ctl->enable == _FALSE) {
++		if (reorder_ctl->ampdu_size != RX_AMPDU_SIZE_INVALID) {
++			send_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 1);
++			ret = 3;
++		}
++		goto exit;
++	}
++
++	if (accept == _FALSE) {
++		send_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 0);
++		ret = 1;
++	} else if (reorder_ctl->ampdu_size != size) {
++		send_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 0);
++		ret = 2;
++	}
++
++exit:
++	return ret;
++}
++
++u8 rx_ampdu_size_sta_limit(_adapter *adapter, struct sta_info *sta)
++{
++	u8 sz_limit = 0xFF;
++
++#ifdef CONFIG_80211N_HT
++	struct registry_priv *regsty = adapter_to_regsty(adapter);
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++	struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info;
++	s8 nss = -1;
++	u8 bw = rtw_min(sta->cmn.bw_mode, adapter->mlmeextpriv.cur_bwmode);
++
++	#ifdef CONFIG_80211AC_VHT
++	if (is_supported_vht(sta->wireless_mode)) {
++		nss = rtw_min(rtw_vht_mcsmap_to_nss(mlme->vhtpriv.vht_mcs_map)
++				, rtw_vht_mcsmap_to_nss(sta->vhtpriv.vht_mcs_map));
++	} else
++	#endif
++	if (is_supported_ht(sta->wireless_mode)) {
++		nss = rtw_min(rtw_ht_mcsset_to_nss(mlmeinfo->HT_caps.u.HT_cap_element.MCS_rate)
++				, rtw_ht_mcsset_to_nss(sta->htpriv.ht_cap.supp_mcs_set));
++	}
++
++	if (nss >= 1)
++		sz_limit = regsty->rx_ampdu_sz_limit_by_nss_bw[nss - 1][bw];
++#endif /* CONFIG_80211N_HT */
++
++	return sz_limit;
++}
++
++/**
++ * rx_ampdu_apply_sta - Apply RX AMPDU setting to the specific @sta
++ * @adapter: the adapter to which @sta belongs
++ * @sta: the sta to be checked
++ * @accept: the target permission if RX AMPDU should be set up
++ * @size: the target RX AMPDU buffer size
++ *
++ * Returns: number of the RX AMPDU assciation canceled for applying current target setting
++ *
++ * Blocking function, may sleep
++ */
++u8 rx_ampdu_apply_sta(_adapter *adapter, struct sta_info *sta, u8 accept, u8 size)
++{
++	u8 change_cnt = 0;
++	int i;
++
++	for (i = 0; i < TID_NUM; i++) {
++		if (rx_ampdu_apply_sta_tid(adapter, sta, i, accept, size) != 0)
++			change_cnt++;
++	}
++
++	return change_cnt;
++}
++
++/**
++ * rtw_rx_ampdu_apply - Apply the current target RX AMPDU setting for the specific @adapter
++ * @adapter: the adapter to be applied
++ *
++ * Returns: number of the RX AMPDU assciation canceled for applying current target setting
++ */
++u16 rtw_rx_ampdu_apply(_adapter *adapter)
++{
++	u16 adj_cnt = 0;
++	struct sta_info *sta;
++	u8 accept = rtw_rx_ampdu_is_accept(adapter);
++	u8 size;
++
++	if (adapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID)
++		size = adapter->fix_rx_ampdu_size;
++	else
++		size = rtw_rx_ampdu_size(adapter);
++
++	if (MLME_IS_STA(adapter)) {
++		sta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv));
++		if (sta) {
++			u8 sta_size = size;
++
++			if (adapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID)
++				sta_size = rtw_min(size, rx_ampdu_size_sta_limit(adapter, sta));
++			adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size);
++		}
++		/* TODO: TDLS peer */
++
++	} else if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
++		_irqL irqL;
++		_list *phead, *plist;
++		u8 peer_num = 0;
++		char peers[NUM_STA];
++		struct sta_priv *pstapriv = &adapter->stapriv;
++		int i;
++
++		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++		phead = &pstapriv->asoc_list;
++		plist = get_next(phead);
++
++		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++			int stainfo_offset;
++
++			sta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++			plist = get_next(plist);
++
++			stainfo_offset = rtw_stainfo_offset(pstapriv, sta);
++			if (stainfo_offset_valid(stainfo_offset))
++				peers[peer_num++] = stainfo_offset;
++		}
++
++		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++		for (i = 0; i < peer_num; i++) {
++			sta = rtw_get_stainfo_by_offset(pstapriv, peers[i]);
++			if (sta) {
++				u8 sta_size = size;
++
++				if (adapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID)
++					sta_size = rtw_min(size, rx_ampdu_size_sta_limit(adapter, sta));
++				adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size);
++			}
++		}
++	}
++
++	/* TODO: ADHOC */
++
++	return adj_cnt;
++}
++
++unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame)
++{
++	u8 *addr;
++	struct sta_info *psta = NULL;
++	struct recv_reorder_ctrl *preorder_ctrl;
++	unsigned char		*frame_body;
++	unsigned char		category, action;
++	unsigned short	tid, status, reason_code = 0;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct registry_priv *pregpriv = &padapter->registrypriv;
++
++#ifdef CONFIG_80211N_HT
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	/* check RA matches or not	 */
++	if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))
++		return _SUCCESS;
++
++#if 0
++	/* check A1 matches or not */
++	if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN))
++		return _SUCCESS;
++#endif
++
++	if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
++		if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS))
++			return _SUCCESS;
++
++	addr = get_addr2_ptr(pframe);
++	psta = rtw_get_stainfo(pstapriv, addr);
++
++	if (psta == NULL)
++		return _SUCCESS;
++
++	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++
++	category = frame_body[0];
++	if (category == RTW_WLAN_CATEGORY_BACK) { /* representing Block Ack */
++#ifdef CONFIG_TDLS
++		if ((psta->tdls_sta_state & TDLS_LINKED_STATE) &&
++		    (psta->htpriv.ht_option == _TRUE) &&
++		    (psta->htpriv.ampdu_enable == _TRUE))
++			RTW_INFO("Recv [%s] from direc link\n", __FUNCTION__);
++		else
++#endif /* CONFIG_TDLS */
++			if (!pmlmeinfo->HT_enable)
++				return _SUCCESS;
++
++		action = frame_body[1];
++		RTW_INFO("%s, action=%d\n", __FUNCTION__, action);
++		switch (action) {
++		case RTW_WLAN_ACTION_ADDBA_REQ: /* ADDBA request */
++
++			_rtw_memcpy(&(pmlmeinfo->ADDBA_req), &(frame_body[2]), sizeof(struct ADDBA_request));
++			/* process_addba_req(padapter, (u8*)&(pmlmeinfo->ADDBA_req), GetAddr3Ptr(pframe)); */
++			process_addba_req(padapter, (u8 *)&(pmlmeinfo->ADDBA_req), addr);
++
++			break;
++
++		case RTW_WLAN_ACTION_ADDBA_RESP: /* ADDBA response */
++
++			/* status = frame_body[3] | (frame_body[4] << 8); */ /* endian issue */
++			status = RTW_GET_LE16(&frame_body[3]);
++			tid = ((frame_body[5] >> 2) & 0x7);
++			if (status == 0) {
++				/* successful					 */
++				RTW_INFO("agg_enable for TID=%d\n", tid);
++				psta->htpriv.agg_enable_bitmap |= 1 << tid;
++				psta->htpriv.candidate_tid_bitmap &= ~BIT(tid);
++				/* amsdu in ampdu */
++				if (pregpriv->tx_ampdu_amsdu == 0)
++					psta->htpriv.tx_amsdu_enable = _FALSE;
++				else if (pregpriv->tx_ampdu_amsdu == 1)
++					psta->htpriv.tx_amsdu_enable = _TRUE;
++				else {
++					if (frame_body[5] & 1)
++						psta->htpriv.tx_amsdu_enable = _TRUE;
++				}
++			} else
++				psta->htpriv.agg_enable_bitmap &= ~BIT(tid);
++
++			if (psta->state & WIFI_STA_ALIVE_CHK_STATE) {
++				RTW_INFO("%s alive check - rx ADDBA response\n", __func__);
++				psta->htpriv.agg_enable_bitmap &= ~BIT(tid);
++				psta->expire_to = pstapriv->expire_to;
++				psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
++			}
++
++			/* RTW_INFO("marc: ADDBA RSP: %x\n", pmlmeinfo->agg_enable_bitmap); */
++			break;
++
++		case RTW_WLAN_ACTION_DELBA: /* DELBA */
++			if ((frame_body[3] & BIT(3)) == 0) {
++				psta->htpriv.agg_enable_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf));
++				psta->htpriv.candidate_tid_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf));
++
++				/* reason_code = frame_body[4] | (frame_body[5] << 8); */
++				reason_code = RTW_GET_LE16(&frame_body[4]);
++			} else if ((frame_body[3] & BIT(3)) == BIT(3)) {
++				tid = (frame_body[3] >> 4) & 0x0F;
++
++				preorder_ctrl = &psta->recvreorder_ctrl[tid];
++				preorder_ctrl->enable = _FALSE;
++				preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID;
++			}
++
++			RTW_INFO("%s(): DELBA: %x(%x)\n", __FUNCTION__, pmlmeinfo->agg_enable_bitmap, reason_code);
++			/* todo: how to notify the host while receiving DELETE BA */
++			break;
++
++		default:
++			break;
++		}
++	}
++#endif /* CONFIG_80211N_HT */
++	return _SUCCESS;
++}
++
++#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
++u32 rtw_build_vendor_ie(_adapter *padapter , unsigned char **pframe , u8 mgmt_frame_tyte)
++{
++	int vendor_ie_num = 0;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	u32 len = 0;
++
++	for (vendor_ie_num = 0 ; vendor_ie_num < WLAN_MAX_VENDOR_IE_NUM ; vendor_ie_num++) {
++		if (pmlmepriv->vendor_ielen[vendor_ie_num] > 0 && pmlmepriv->vendor_ie_mask[vendor_ie_num] & mgmt_frame_tyte) {
++			_rtw_memcpy(*pframe , pmlmepriv->vendor_ie[vendor_ie_num] , pmlmepriv->vendor_ielen[vendor_ie_num]);
++			*pframe +=  pmlmepriv->vendor_ielen[vendor_ie_num];
++			len += pmlmepriv->vendor_ielen[vendor_ie_num];
++		}
++	}
++
++	return len;
++}
++#endif
++
++#ifdef CONFIG_P2P
++int get_reg_classes_full_count(struct p2p_channels *channel_list)
++{
++	int cnt = 0;
++	int i;
++
++	for (i = 0; i < channel_list->reg_classes; i++)
++		cnt += channel_list->reg_class[i].channels;
++
++	return cnt;
++}
++
++void issue_p2p_GO_request(_adapter *padapter, u8 *raddr)
++{
++	struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
++	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++	u8			action = P2P_PUB_ACTION_ACTION;
++	u32			p2poui = cpu_to_be32(P2POUI);
++	u8			oui_subtype = P2P_GO_NEGO_REQ;
++	u8			wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };
++	u8			wpsielen = 0, p2pielen = 0;
++	u16			len_channellist_attr = 0;
++#ifdef CONFIG_WFD
++	u32					wfdielen = 0;
++#endif
++
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++	RTW_INFO("[%s] In\n", __FUNCTION__);
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++	pwdinfo->negotiation_dialog_token = 1;	/*	Initialize the dialog value */
++	pframe = rtw_set_fixed_ie(pframe, 1, &pwdinfo->negotiation_dialog_token, &(pattrib->pktlen));
++
++
++
++	/*	WPS Section */
++	wpsielen = 0;
++	/*	WPS OUI */
++	*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
++	wpsielen += 4;
++
++	/*	WPS version */
++	/*	Type: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
++	wpsielen += 2;
++
++	/*	Length: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
++	wpsielen += 2;
++
++	/*	Value: */
++	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
++
++	/*	Device Password ID */
++	/*	Type: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);
++	wpsielen += 2;
++
++	/*	Length: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
++	wpsielen += 2;
++
++	/*	Value: */
++
++	if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN)
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC);
++	else if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN)
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);
++	else if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC)
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC);
++
++	wpsielen += 2;
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
++
++
++	/*	P2P IE Section. */
++
++	/*	P2P OUI */
++	p2pielen = 0;
++	p2pie[p2pielen++] = 0x50;
++	p2pie[p2pielen++] = 0x6F;
++	p2pie[p2pielen++] = 0x9A;
++	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
++
++	/*	Commented by Albert 20110306 */
++	/*	According to the P2P Specification, the group negoitation request frame should contain 9 P2P attributes */
++	/*	1. P2P Capability */
++	/*	2. Group Owner Intent */
++	/*	3. Configuration Timeout */
++	/*	4. Listen Channel */
++	/*	5. Extended Listen Timing */
++	/*	6. Intended P2P Interface Address */
++	/*	7. Channel List */
++	/*	8. P2P Device Info */
++	/*	9. Operating Channel */
++
++
++	/*	P2P Capability */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Device Capability Bitmap, 1 byte */
++	p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
++
++	/*	Group Capability Bitmap, 1 byte */
++	if (pwdinfo->persistent_supported)
++		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;
++	else
++		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;
++
++
++	/*	Group Owner Intent */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_GO_INTENT;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Todo the tie breaker bit. */
++	p2pie[p2pielen++] = ((pwdinfo->intent << 1) &  0xFE);
++
++	/*	Configuration Timeout */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
++	p2pielen += 2;
++
++	/*	Value: */
++	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
++	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
++
++
++	/*	Listen Channel */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_LISTEN_CH;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Country String */
++	p2pie[p2pielen++] = 'X';
++	p2pie[p2pielen++] = 'X';
++
++	/*	The third byte should be set to 0x04. */
++	/*	Described in the "Operating Channel Attribute" section. */
++	p2pie[p2pielen++] = 0x04;
++
++	/*	Operating Class */
++	p2pie[p2pielen++] = 0x51;	/*	Copy from SD7 */
++
++	/*	Channel Number */
++	p2pie[p2pielen++] = pwdinfo->listen_channel;	/*	listening channel number */
++
++
++	/*	Extended Listen Timing ATTR */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Availability Period */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
++	p2pielen += 2;
++
++	/*	Availability Interval */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
++	p2pielen += 2;
++
++
++	/*	Intended P2P Interface Address */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
++	p2pielen += 2;
++
++	/*	Value: */
++	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
++	p2pielen += ETH_ALEN;
++
++
++	/*	Channel List */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
++
++	/* Length: */
++	/* Country String(3) */
++	/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
++	/* + number of channels in all classes */
++	len_channellist_attr = 3
++		       + (1 + 1) * (u16)(ch_list->reg_classes)
++		       + get_reg_classes_full_count(ch_list);
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
++	else
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
++#else
++
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
++
++#endif
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Country String */
++	p2pie[p2pielen++] = 'X';
++	p2pie[p2pielen++] = 'X';
++
++	/*	The third byte should be set to 0x04. */
++	/*	Described in the "Operating Channel Attribute" section. */
++	p2pie[p2pielen++] = 0x04;
++
++	/*	Channel Entry List */
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
++		u8 union_ch = rtw_mi_get_union_chan(padapter);
++
++		/*	Operating Class */
++		if (union_ch > 14) {
++			if (union_ch >= 149)
++				p2pie[p2pielen++] = 0x7c;
++			else
++				p2pie[p2pielen++] = 0x73;
++		} else
++			p2pie[p2pielen++] = 0x51;
++
++
++		/*	Number of Channels */
++		/*	Just support 1 channel and this channel is AP's channel */
++		p2pie[p2pielen++] = 1;
++
++		/*	Channel List */
++		p2pie[p2pielen++] = union_ch;
++	} else
++#endif /* CONFIG_CONCURRENT_MODE */
++	{
++		int i, j;
++		for (j = 0; j < ch_list->reg_classes; j++) {
++			/*	Operating Class */
++			p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
++
++			/*	Number of Channels */
++			p2pie[p2pielen++] = ch_list->reg_class[j].channels;
++
++			/*	Channel List */
++			for (i = 0; i < ch_list->reg_class[j].channels; i++)
++				p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
++		}
++	}
++
++	/*	Device Info */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
++	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	P2P Device Address */
++	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
++	p2pielen += ETH_ALEN;
++
++	/*	Config Method */
++	/*	This field should be big endian. Noted by P2P specification. */
++
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
++
++	p2pielen += 2;
++
++	/*	Primary Device Type */
++	/*	Category ID */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
++	p2pielen += 2;
++
++	/*	OUI */
++	*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);
++	p2pielen += 4;
++
++	/*	Sub Category ID */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
++	p2pielen += 2;
++
++	/*	Number of Secondary Device Types */
++	p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
++
++	/*	Device Name */
++	/*	Type: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
++	p2pielen += 2;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);
++	p2pielen += 2;
++
++	/*	Value: */
++	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len);
++	p2pielen += pwdinfo->device_name_len;
++
++
++	/*	Operating Channel */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Country String */
++	p2pie[p2pielen++] = 'X';
++	p2pie[p2pielen++] = 'X';
++
++	/*	The third byte should be set to 0x04. */
++	/*	Described in the "Operating Channel Attribute" section. */
++	p2pie[p2pielen++] = 0x04;
++
++	/*	Operating Class */
++	if (pwdinfo->operating_channel <= 14) {
++		/*	Operating Class */
++		p2pie[p2pielen++] = 0x51;
++	} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {
++		/*	Operating Class */
++		p2pie[p2pielen++] = 0x73;
++	} else {
++		/*	Operating Class */
++		p2pie[p2pielen++] = 0x7c;
++	}
++
++	/*	Channel Number */
++	p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
++
++#ifdef CONFIG_WFD
++	wfdielen = build_nego_req_wfd_ie(pwdinfo, pframe);
++	pframe += wfdielen;
++	pattrib->pktlen += wfdielen;
++#endif
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(padapter, pmgntframe);
++
++	return;
++
++}
++
++
++void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint len, u8 result)
++{
++	struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
++	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++	u8			action = P2P_PUB_ACTION_ACTION;
++	u32			p2poui = cpu_to_be32(P2POUI);
++	u8			oui_subtype = P2P_GO_NEGO_RESP;
++	u8			wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };
++	u8			p2pielen = 0;
++	uint			wpsielen = 0;
++	u16			wps_devicepassword_id = 0x0000;
++	uint			wps_devicepassword_id_len = 0;
++	u16			len_channellist_attr = 0;
++
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++#ifdef CONFIG_WFD
++	u32					wfdielen = 0;
++#endif
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++	RTW_INFO("[%s] In, result = %d\n", __FUNCTION__,  result);
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++	pwdinfo->negotiation_dialog_token = frame_body[7];	/*	The Dialog Token of provisioning discovery request frame. */
++	pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen));
++
++	/*	Commented by Albert 20110328 */
++	/*	Try to get the device password ID from the WPS IE of group negotiation request frame */
++	/*	WiFi Direct test plan 5.1.15 */
++	rtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen);
++	rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8 *) &wps_devicepassword_id, &wps_devicepassword_id_len);
++	wps_devicepassword_id = be16_to_cpu(wps_devicepassword_id);
++
++	_rtw_memset(wpsie, 0x00, 255);
++	wpsielen = 0;
++
++	/*	WPS Section */
++	wpsielen = 0;
++	/*	WPS OUI */
++	*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
++	wpsielen += 4;
++
++	/*	WPS version */
++	/*	Type: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
++	wpsielen += 2;
++
++	/*	Length: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
++	wpsielen += 2;
++
++	/*	Value: */
++	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
++
++	/*	Device Password ID */
++	/*	Type: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);
++	wpsielen += 2;
++
++	/*	Length: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
++	wpsielen += 2;
++
++	/*	Value: */
++	if (wps_devicepassword_id == WPS_DPID_USER_SPEC)
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);
++	else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC);
++	else
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC);
++	wpsielen += 2;
++
++	/*	Commented by Kurt 20120113 */
++	/*	If some device wants to do p2p handshake without sending prov_disc_req */
++	/*	We have to get peer_req_cm from here. */
++	if (_rtw_memcmp(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3)) {
++		if (wps_devicepassword_id == WPS_DPID_USER_SPEC)
++			_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3);
++		else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)
++			_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3);
++		else
++			_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3);
++	}
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
++
++
++	/*	P2P IE Section. */
++
++	/*	P2P OUI */
++	p2pielen = 0;
++	p2pie[p2pielen++] = 0x50;
++	p2pie[p2pielen++] = 0x6F;
++	p2pie[p2pielen++] = 0x9A;
++	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
++
++	/*	Commented by Albert 20100908 */
++	/*	According to the P2P Specification, the group negoitation response frame should contain 9 P2P attributes */
++	/*	1. Status */
++	/*	2. P2P Capability */
++	/*	3. Group Owner Intent */
++	/*	4. Configuration Timeout */
++	/*	5. Operating Channel */
++	/*	6. Intended P2P Interface Address */
++	/*	7. Channel List */
++	/*	8. Device Info */
++	/*	9. Group ID	( Only GO ) */
++
++
++	/*	ToDo: */
++
++	/*	P2P Status */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_STATUS;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
++	p2pielen += 2;
++
++	/*	Value: */
++	p2pie[p2pielen++] = result;
++
++	/*	P2P Capability */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Device Capability Bitmap, 1 byte */
++
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
++		/*	Commented by Albert 2011/03/08 */
++		/*	According to the P2P specification */
++		/*	if the sending device will be client, the P2P Capability should be reserved of group negotation response frame */
++		p2pie[p2pielen++] = 0;
++	} else {
++		/*	Be group owner or meet the error case */
++		p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
++	}
++
++	/*	Group Capability Bitmap, 1 byte */
++	if (pwdinfo->persistent_supported)
++		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;
++	else
++		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;
++
++	/*	Group Owner Intent */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_GO_INTENT;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
++	p2pielen += 2;
++
++	/*	Value: */
++	if (pwdinfo->peer_intent & 0x01) {
++		/*	Peer's tie breaker bit is 1, our tie breaker bit should be 0 */
++		p2pie[p2pielen++] = (pwdinfo->intent << 1);
++	} else {
++		/*	Peer's tie breaker bit is 0, our tie breaker bit should be 1 */
++		p2pie[p2pielen++] = ((pwdinfo->intent << 1) | BIT(0));
++	}
++
++
++	/*	Configuration Timeout */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
++	p2pielen += 2;
++
++	/*	Value: */
++	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
++	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
++
++	/*	Operating Channel */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Country String */
++	p2pie[p2pielen++] = 'X';
++	p2pie[p2pielen++] = 'X';
++
++	/*	The third byte should be set to 0x04. */
++	/*	Described in the "Operating Channel Attribute" section. */
++	p2pie[p2pielen++] = 0x04;
++
++	/*	Operating Class */
++	if (pwdinfo->operating_channel <= 14) {
++		/*	Operating Class */
++		p2pie[p2pielen++] = 0x51;
++	} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {
++		/*	Operating Class */
++		p2pie[p2pielen++] = 0x73;
++	} else {
++		/*	Operating Class */
++		p2pie[p2pielen++] = 0x7c;
++	}
++
++	/*	Channel Number */
++	p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
++
++	/*	Intended P2P Interface Address	 */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
++	p2pielen += 2;
++
++	/*	Value: */
++	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
++	p2pielen += ETH_ALEN;
++
++	/*	Channel List */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
++
++	/* Country String(3) */
++	/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
++	/* + number of channels in all classes */
++	len_channellist_attr = 3
++		       + (1 + 1) * (u16)ch_list->reg_classes
++		       + get_reg_classes_full_count(ch_list);
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
++	else
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
++#else
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
++
++#endif
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Country String */
++	p2pie[p2pielen++] = 'X';
++	p2pie[p2pielen++] = 'X';
++
++	/*	The third byte should be set to 0x04. */
++	/*	Described in the "Operating Channel Attribute" section. */
++	p2pie[p2pielen++] = 0x04;
++
++	/*	Channel Entry List */
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
++
++		u8 union_chan = rtw_mi_get_union_chan(padapter);
++
++		/*Operating Class*/
++		if (union_chan > 14) {
++			if (union_chan >= 149)
++				p2pie[p2pielen++] = 0x7c;
++			else
++				p2pie[p2pielen++] = 0x73;
++
++		} else
++			p2pie[p2pielen++] = 0x51;
++
++		/*	Number of Channels
++			Just support 1 channel and this channel is AP's channel*/
++		p2pie[p2pielen++] = 1;
++
++		/*Channel List*/
++		p2pie[p2pielen++] = union_chan;
++	} else
++#endif /* CONFIG_CONCURRENT_MODE */
++	{
++		int i, j;
++		for (j = 0; j < ch_list->reg_classes; j++) {
++			/*	Operating Class */
++			p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
++
++			/*	Number of Channels */
++			p2pie[p2pielen++] = ch_list->reg_class[j].channels;
++
++			/*	Channel List */
++			for (i = 0; i < ch_list->reg_class[j].channels; i++)
++				p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
++		}
++	}
++
++	/*	Device Info */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
++	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	P2P Device Address */
++	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
++	p2pielen += ETH_ALEN;
++
++	/*	Config Method */
++	/*	This field should be big endian. Noted by P2P specification. */
++
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
++
++	p2pielen += 2;
++
++	/*	Primary Device Type */
++	/*	Category ID */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
++	p2pielen += 2;
++
++	/*	OUI */
++	*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);
++	p2pielen += 4;
++
++	/*	Sub Category ID */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
++	p2pielen += 2;
++
++	/*	Number of Secondary Device Types */
++	p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
++
++	/*	Device Name */
++	/*	Type: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
++	p2pielen += 2;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);
++	p2pielen += 2;
++
++	/*	Value: */
++	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len);
++	p2pielen += pwdinfo->device_name_len;
++
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++		/*	Group ID Attribute */
++		/*	Type: */
++		p2pie[p2pielen++] = P2P_ATTR_GROUP_ID;
++
++		/*	Length: */
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen);
++		p2pielen += 2;
++
++		/*	Value: */
++		/*	p2P Device Address */
++		_rtw_memcpy(p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN);
++		p2pielen += ETH_ALEN;
++
++		/*	SSID */
++		_rtw_memcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);
++		p2pielen += pwdinfo->nego_ssidlen;
++
++	}
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
++
++#ifdef CONFIG_WFD
++	wfdielen = build_nego_resp_wfd_ie(pwdinfo, pframe);
++	pframe += wfdielen;
++	pattrib->pktlen += wfdielen;
++#endif
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(padapter, pmgntframe);
++
++	return;
++
++}
++
++void issue_p2p_GO_confirm(_adapter *padapter, u8 *raddr, u8 result)
++{
++
++	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++	u8			action = P2P_PUB_ACTION_ACTION;
++	u32			p2poui = cpu_to_be32(P2POUI);
++	u8			oui_subtype = P2P_GO_NEGO_CONF;
++	u8			p2pie[255] = { 0x00 };
++	u8			p2pielen = 0;
++
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++#ifdef CONFIG_WFD
++	u32					wfdielen = 0;
++#endif
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++	RTW_INFO("[%s] In\n", __FUNCTION__);
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen));
++
++
++
++	/*	P2P IE Section. */
++
++	/*	P2P OUI */
++	p2pielen = 0;
++	p2pie[p2pielen++] = 0x50;
++	p2pie[p2pielen++] = 0x6F;
++	p2pie[p2pielen++] = 0x9A;
++	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
++
++	/*	Commented by Albert 20110306 */
++	/*	According to the P2P Specification, the group negoitation request frame should contain 5 P2P attributes */
++	/*	1. Status */
++	/*	2. P2P Capability */
++	/*	3. Operating Channel */
++	/*	4. Channel List */
++	/*	5. Group ID	( if this WiFi is GO ) */
++
++	/*	P2P Status */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_STATUS;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
++	p2pielen += 2;
++
++	/*	Value: */
++	p2pie[p2pielen++] = result;
++
++	/*	P2P Capability */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Device Capability Bitmap, 1 byte */
++	p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
++
++	/*	Group Capability Bitmap, 1 byte */
++	if (pwdinfo->persistent_supported)
++		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;
++	else
++		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;
++
++
++	/*	Operating Channel */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Country String */
++	p2pie[p2pielen++] = 'X';
++	p2pie[p2pielen++] = 'X';
++
++	/*	The third byte should be set to 0x04. */
++	/*	Described in the "Operating Channel Attribute" section. */
++	p2pie[p2pielen++] = 0x04;
++
++
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
++		if (pwdinfo->peer_operating_ch <= 14) {
++			/*	Operating Class */
++			p2pie[p2pielen++] = 0x51;
++		} else if ((pwdinfo->peer_operating_ch >= 36) && (pwdinfo->peer_operating_ch <= 48)) {
++			/*	Operating Class */
++			p2pie[p2pielen++] = 0x73;
++		} else {
++			/*	Operating Class */
++			p2pie[p2pielen++] = 0x7c;
++		}
++
++		p2pie[p2pielen++] = pwdinfo->peer_operating_ch;
++	} else {
++		if (pwdinfo->operating_channel <= 14) {
++			/*	Operating Class */
++			p2pie[p2pielen++] = 0x51;
++		} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {
++			/*	Operating Class */
++			p2pie[p2pielen++] = 0x73;
++		} else {
++			/*	Operating Class */
++			p2pie[p2pielen++] = 0x7c;
++		}
++
++		/*	Channel Number */
++		p2pie[p2pielen++] = pwdinfo->operating_channel;		/*	Use the listen channel as the operating channel */
++	}
++
++
++	/*	Channel List */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
++
++	*(u16 *)(p2pie + p2pielen) = 6;
++	p2pielen += 2;
++
++	/*	Country String */
++	p2pie[p2pielen++] = 'X';
++	p2pie[p2pielen++] = 'X';
++
++	/*	The third byte should be set to 0x04. */
++	/*	Described in the "Operating Channel Attribute" section. */
++	p2pie[p2pielen++] = 0x04;
++
++	/*	Value: */
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
++		if (pwdinfo->peer_operating_ch <= 14) {
++			/*	Operating Class */
++			p2pie[p2pielen++] = 0x51;
++		} else if ((pwdinfo->peer_operating_ch >= 36) && (pwdinfo->peer_operating_ch <= 48)) {
++			/*	Operating Class */
++			p2pie[p2pielen++] = 0x73;
++		} else {
++			/*	Operating Class */
++			p2pie[p2pielen++] = 0x7c;
++		}
++		p2pie[p2pielen++] = 1;
++		p2pie[p2pielen++] = pwdinfo->peer_operating_ch;
++	} else {
++		if (pwdinfo->operating_channel <= 14) {
++			/*	Operating Class */
++			p2pie[p2pielen++] = 0x51;
++		} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {
++			/*	Operating Class */
++			p2pie[p2pielen++] = 0x73;
++		} else {
++			/*	Operating Class */
++			p2pie[p2pielen++] = 0x7c;
++		}
++
++		/*	Channel Number */
++		p2pie[p2pielen++] = 1;
++		p2pie[p2pielen++] = pwdinfo->operating_channel;		/*	Use the listen channel as the operating channel */
++	}
++
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++		/*	Group ID Attribute */
++		/*	Type: */
++		p2pie[p2pielen++] = P2P_ATTR_GROUP_ID;
++
++		/*	Length: */
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen);
++		p2pielen += 2;
++
++		/*	Value: */
++		/*	p2P Device Address */
++		_rtw_memcpy(p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN);
++		p2pielen += ETH_ALEN;
++
++		/*	SSID */
++		_rtw_memcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);
++		p2pielen += pwdinfo->nego_ssidlen;
++	}
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
++
++#ifdef CONFIG_WFD
++	wfdielen = build_nego_confirm_wfd_ie(pwdinfo, pframe);
++	pframe += wfdielen;
++	pattrib->pktlen += wfdielen;
++#endif
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(padapter, pmgntframe);
++
++	return;
++
++}
++
++void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr)
++{
++	struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
++	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++	u8			action = P2P_PUB_ACTION_ACTION;
++	u32			p2poui = cpu_to_be32(P2POUI);
++	u8			oui_subtype = P2P_INVIT_REQ;
++	u8			p2pie[255] = { 0x00 };
++	u8			p2pielen = 0;
++	u8			dialogToken = 3;
++	u16			len_channellist_attr = 0;
++#ifdef CONFIG_WFD
++	u32					wfdielen = 0;
++#endif
++
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, raddr,  ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
++
++	/*	P2P IE Section. */
++
++	/*	P2P OUI */
++	p2pielen = 0;
++	p2pie[p2pielen++] = 0x50;
++	p2pie[p2pielen++] = 0x6F;
++	p2pie[p2pielen++] = 0x9A;
++	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
++
++	/*	Commented by Albert 20101011 */
++	/*	According to the P2P Specification, the P2P Invitation request frame should contain 7 P2P attributes */
++	/*	1. Configuration Timeout */
++	/*	2. Invitation Flags */
++	/*	3. Operating Channel	( Only GO ) */
++	/*	4. P2P Group BSSID	( Should be included if I am the GO ) */
++	/*	5. Channel List */
++	/*	6. P2P Group ID */
++	/*	7. P2P Device Info */
++
++	/*	Configuration Timeout */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
++	p2pielen += 2;
++
++	/*	Value: */
++	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
++	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
++
++	/*	Invitation Flags */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_INVITATION_FLAGS;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
++	p2pielen += 2;
++
++	/*	Value: */
++	p2pie[p2pielen++] = P2P_INVITATION_FLAGS_PERSISTENT;
++
++
++	/*	Operating Channel */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Country String */
++	p2pie[p2pielen++] = 'X';
++	p2pie[p2pielen++] = 'X';
++
++	/*	The third byte should be set to 0x04. */
++	/*	Described in the "Operating Channel Attribute" section. */
++	p2pie[p2pielen++] = 0x04;
++
++	/*	Operating Class */
++	if (pwdinfo->invitereq_info.operating_ch <= 14)
++		p2pie[p2pielen++] = 0x51;
++	else if ((pwdinfo->invitereq_info.operating_ch >= 36) && (pwdinfo->invitereq_info.operating_ch <= 48))
++		p2pie[p2pielen++] = 0x73;
++	else
++		p2pie[p2pielen++] = 0x7c;
++
++	/*	Channel Number */
++	p2pie[p2pielen++] = pwdinfo->invitereq_info.operating_ch;	/*	operating channel number */
++
++	if (_rtw_memcmp(adapter_mac_addr(padapter), pwdinfo->invitereq_info.go_bssid, ETH_ALEN)) {
++		/*	P2P Group BSSID */
++		/*	Type: */
++		p2pie[p2pielen++] = P2P_ATTR_GROUP_BSSID;
++
++		/*	Length: */
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
++		p2pielen += 2;
++
++		/*	Value: */
++		/*	P2P Device Address for GO */
++		_rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN);
++		p2pielen += ETH_ALEN;
++	}
++
++	/*	Channel List */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
++
++
++	/*	Length: */
++	/* Country String(3) */
++	/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
++	/* + number of channels in all classes */
++	len_channellist_attr = 3
++		       + (1 + 1) * (u16)ch_list->reg_classes
++		       + get_reg_classes_full_count(ch_list);
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
++	else
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
++#else
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
++#endif
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Country String */
++	p2pie[p2pielen++] = 'X';
++	p2pie[p2pielen++] = 'X';
++
++	/*	The third byte should be set to 0x04. */
++	/*	Described in the "Operating Channel Attribute" section. */
++	p2pie[p2pielen++] = 0x04;
++
++	/*	Channel Entry List */
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
++		u8 union_ch =  rtw_mi_get_union_chan(padapter);
++
++		/*	Operating Class */
++		if (union_ch > 14) {
++			if (union_ch >= 149)
++				p2pie[p2pielen++] = 0x7c;
++			else
++				p2pie[p2pielen++] = 0x73;
++		} else
++			p2pie[p2pielen++] = 0x51;
++
++
++		/*	Number of Channels */
++		/*	Just support 1 channel and this channel is AP's channel */
++		p2pie[p2pielen++] = 1;
++
++		/*	Channel List */
++		p2pie[p2pielen++] = union_ch;
++	} else
++#endif /* CONFIG_CONCURRENT_MODE */
++	{
++		int i, j;
++		for (j = 0; j < ch_list->reg_classes; j++) {
++			/*	Operating Class */
++			p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
++
++			/*	Number of Channels */
++			p2pie[p2pielen++] = ch_list->reg_class[j].channels;
++
++			/*	Channel List */
++			for (i = 0; i < ch_list->reg_class[j].channels; i++)
++				p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
++		}
++	}
++
++
++	/*	P2P Group ID */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_GROUP_ID;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(6 + pwdinfo->invitereq_info.ssidlen);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	P2P Device Address for GO */
++	_rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN);
++	p2pielen += ETH_ALEN;
++
++	/*	SSID */
++	_rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_ssid, pwdinfo->invitereq_info.ssidlen);
++	p2pielen += pwdinfo->invitereq_info.ssidlen;
++
++
++	/*	Device Info */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
++	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	P2P Device Address */
++	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
++	p2pielen += ETH_ALEN;
++
++	/*	Config Method */
++	/*	This field should be big endian. Noted by P2P specification. */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_DISPLAY);
++	p2pielen += 2;
++
++	/*	Primary Device Type */
++	/*	Category ID */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
++	p2pielen += 2;
++
++	/*	OUI */
++	*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);
++	p2pielen += 4;
++
++	/*	Sub Category ID */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
++	p2pielen += 2;
++
++	/*	Number of Secondary Device Types */
++	p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
++
++	/*	Device Name */
++	/*	Type: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
++	p2pielen += 2;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);
++	p2pielen += 2;
++
++	/*	Value: */
++	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len);
++	p2pielen += pwdinfo->device_name_len;
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
++
++#ifdef CONFIG_WFD
++	wfdielen = build_invitation_req_wfd_ie(pwdinfo, pframe);
++	pframe += wfdielen;
++	pattrib->pktlen += wfdielen;
++#endif
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(padapter, pmgntframe);
++
++	return;
++
++}
++
++void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken, u8 status_code)
++{
++	struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
++	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++	u8			action = P2P_PUB_ACTION_ACTION;
++	u32			p2poui = cpu_to_be32(P2POUI);
++	u8			oui_subtype = P2P_INVIT_RESP;
++	u8			p2pie[255] = { 0x00 };
++	u8			p2pielen = 0;
++	u16			len_channellist_attr = 0;
++#ifdef CONFIG_WFD
++	u32					wfdielen = 0;
++#endif
++
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, raddr,  ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
++
++	/*	P2P IE Section. */
++
++	/*	P2P OUI */
++	p2pielen = 0;
++	p2pie[p2pielen++] = 0x50;
++	p2pie[p2pielen++] = 0x6F;
++	p2pie[p2pielen++] = 0x9A;
++	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
++
++	/*	Commented by Albert 20101005 */
++	/*	According to the P2P Specification, the P2P Invitation response frame should contain 5 P2P attributes */
++	/*	1. Status */
++	/*	2. Configuration Timeout */
++	/*	3. Operating Channel	( Only GO ) */
++	/*	4. P2P Group BSSID	( Only GO ) */
++	/*	5. Channel List */
++
++	/*	P2P Status */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_STATUS;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	When status code is P2P_STATUS_FAIL_INFO_UNAVAILABLE. */
++	/*	Sent the event receiving the P2P Invitation Req frame to DMP UI. */
++	/*	DMP had to compare the MAC address to find out the profile. */
++	/*	So, the WiFi driver will send the P2P_STATUS_FAIL_INFO_UNAVAILABLE to NB. */
++	/*	If the UI found the corresponding profile, the WiFi driver sends the P2P Invitation Req */
++	/*	to NB to rebuild the persistent group. */
++	p2pie[p2pielen++] = status_code;
++
++	/*	Configuration Timeout */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
++	p2pielen += 2;
++
++	/*	Value: */
++	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
++	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
++
++	if (status_code == P2P_STATUS_SUCCESS) {
++		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++			/*	The P2P Invitation request frame asks this Wi-Fi device to be the P2P GO */
++			/*	In this case, the P2P Invitation response frame should carry the two more P2P attributes. */
++			/*	First one is operating channel attribute. */
++			/*	Second one is P2P Group BSSID attribute. */
++
++			/*	Operating Channel */
++			/*	Type: */
++			p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
++
++			/*	Length: */
++			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
++			p2pielen += 2;
++
++			/*	Value: */
++			/*	Country String */
++			p2pie[p2pielen++] = 'X';
++			p2pie[p2pielen++] = 'X';
++
++			/*	The third byte should be set to 0x04. */
++			/*	Described in the "Operating Channel Attribute" section. */
++			p2pie[p2pielen++] = 0x04;
++
++			/*	Operating Class */
++			p2pie[p2pielen++] = 0x51;	/*	Copy from SD7 */
++
++			/*	Channel Number */
++			p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
++
++
++			/*	P2P Group BSSID */
++			/*	Type: */
++			p2pie[p2pielen++] = P2P_ATTR_GROUP_BSSID;
++
++			/*	Length: */
++			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
++			p2pielen += 2;
++
++			/*	Value: */
++			/*	P2P Device Address for GO */
++			_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
++			p2pielen += ETH_ALEN;
++
++		}
++
++		/*	Channel List */
++		/*	Type: */
++		p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
++
++		/*	Length: */
++		/* Country String(3) */
++		/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
++		/* + number of channels in all classes */
++		len_channellist_attr = 3
++			+ (1 + 1) * (u16)ch_list->reg_classes
++			+ get_reg_classes_full_count(ch_list);
++
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
++			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
++		else
++			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
++#else
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
++#endif
++		p2pielen += 2;
++
++		/*	Value: */
++		/*	Country String */
++		p2pie[p2pielen++] = 'X';
++		p2pie[p2pielen++] = 'X';
++
++		/*	The third byte should be set to 0x04. */
++		/*	Described in the "Operating Channel Attribute" section. */
++		p2pie[p2pielen++] = 0x04;
++
++		/*	Channel Entry List */
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
++			u8 union_ch = rtw_mi_get_union_chan(padapter);
++
++			/*	Operating Class */
++			if (union_ch > 14) {
++				if (union_ch >= 149)
++					p2pie[p2pielen++]  = 0x7c;
++				else
++					p2pie[p2pielen++] = 0x73;
++			} else
++				p2pie[p2pielen++] = 0x51;
++
++
++			/*	Number of Channels */
++			/*	Just support 1 channel and this channel is AP's channel */
++			p2pie[p2pielen++] = 1;
++
++			/*	Channel List */
++			p2pie[p2pielen++] = union_ch;
++		} else
++#endif /* CONFIG_CONCURRENT_MODE */
++		{
++			int i, j;
++			for (j = 0; j < ch_list->reg_classes; j++) {
++				/*	Operating Class */
++				p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
++
++				/*	Number of Channels */
++				p2pie[p2pielen++] = ch_list->reg_class[j].channels;
++
++				/*	Channel List */
++				for (i = 0; i < ch_list->reg_class[j].channels; i++)
++					p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
++			}
++		}
++	}
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
++
++#ifdef CONFIG_WFD
++	wfdielen = build_invitation_resp_wfd_ie(pwdinfo, pframe);
++	pframe += wfdielen;
++	pattrib->pktlen += wfdielen;
++#endif
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(padapter, pmgntframe);
++
++	return;
++
++}
++
++void issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8 *pdev_raddr)
++{
++	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++	u8			action = P2P_PUB_ACTION_ACTION;
++	u8			dialogToken = 1;
++	u32			p2poui = cpu_to_be32(P2POUI);
++	u8			oui_subtype = P2P_PROVISION_DISC_REQ;
++	u8			wpsie[100] = { 0x00 };
++	u8			wpsielen = 0;
++	u32			p2pielen = 0;
++#ifdef CONFIG_WFD
++	u32					wfdielen = 0;
++#endif
++
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++	RTW_INFO("[%s] In\n", __FUNCTION__);
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, pdev_raddr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, pdev_raddr, ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
++
++	p2pielen = build_prov_disc_request_p2p_ie(pwdinfo, pframe, pssid, ussidlen, pdev_raddr);
++
++	pframe += p2pielen;
++	pattrib->pktlen += p2pielen;
++
++	wpsielen = 0;
++	/*	WPS OUI */
++	*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
++	wpsielen += 4;
++
++	/*	WPS version */
++	/*	Type: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
++	wpsielen += 2;
++
++	/*	Length: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
++	wpsielen += 2;
++
++	/*	Value: */
++	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
++
++	/*	Config Method */
++	/*	Type: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);
++	wpsielen += 2;
++
++	/*	Length: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
++	wpsielen += 2;
++
++	/*	Value: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->tx_prov_disc_info.wps_config_method_request);
++	wpsielen += 2;
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
++
++
++#ifdef CONFIG_WFD
++	wfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe);
++	pframe += wfdielen;
++	pattrib->pktlen += wfdielen;
++#endif
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(padapter, pmgntframe);
++
++	return;
++
++}
++
++
++u8 is_matched_in_profilelist(u8 *peermacaddr, struct profile_info *profileinfo)
++{
++	u8 i, match_result = 0;
++
++	RTW_INFO("[%s] peermac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__,
++		peermacaddr[0], peermacaddr[1], peermacaddr[2], peermacaddr[3], peermacaddr[4], peermacaddr[5]);
++
++	for (i = 0; i < P2P_MAX_PERSISTENT_GROUP_NUM; i++, profileinfo++) {
++		RTW_INFO("[%s] profileinfo_mac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__,
++			profileinfo->peermac[0], profileinfo->peermac[1], profileinfo->peermac[2], profileinfo->peermac[3], profileinfo->peermac[4], profileinfo->peermac[5]);
++		if (_rtw_memcmp(peermacaddr, profileinfo->peermac, ETH_ALEN)) {
++			match_result = 1;
++			RTW_INFO("[%s] Match!\n", __FUNCTION__);
++			break;
++		}
++	}
++
++	return match_result ;
++}
++
++void issue_probersp_p2p(_adapter *padapter, unsigned char *da)
++{
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	unsigned char					*mac;
++	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	/* WLAN_BSSID_EX 		*cur_network = &(pmlmeinfo->network); */
++	u16					beacon_interval = 100;
++	u16					capInfo = 0;
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++	u8					wpsie[255] = { 0x00 };
++	u32					wpsielen = 0, p2pielen = 0;
++#ifdef CONFIG_WFD
++	u32					wfdielen = 0;
++#endif
++
++	/* RTW_INFO("%s\n", __FUNCTION__); */
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	if (IS_CCK_RATE(pattrib->rate)) {
++		/* force OFDM 6M rate */
++		pattrib->rate = MGN_6M;
++		pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G);
++	}
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	mac = adapter_mac_addr(padapter);
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
++
++	/*	Use the device address for BSSID field.	 */
++	_rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(fctrl, WIFI_PROBERSP);
++
++	pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = pattrib->hdrlen;
++	pframe += pattrib->hdrlen;
++
++	/* timestamp will be inserted by hardware */
++	pframe += 8;
++	pattrib->pktlen += 8;
++
++	/* beacon interval: 2 bytes */
++	_rtw_memcpy(pframe, (unsigned char *) &beacon_interval, 2);
++	pframe += 2;
++	pattrib->pktlen += 2;
++
++	/*	capability info: 2 bytes */
++	/*	ESS and IBSS bits must be 0 (defined in the 3.1.2.1.1 of WiFi Direct Spec) */
++	capInfo |= cap_ShortPremble;
++	capInfo |= cap_ShortSlot;
++
++	_rtw_memcpy(pframe, (unsigned char *) &capInfo, 2);
++	pframe += 2;
++	pattrib->pktlen += 2;
++
++
++	/* SSID */
++	pframe = rtw_set_ie(pframe, _SSID_IE_, 7, pwdinfo->p2p_wildcard_ssid, &pattrib->pktlen);
++
++	/* supported rates... */
++	/*	Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) */
++	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen);
++
++	/* DS parameter set */
++	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&pwdinfo->listen_channel, &pattrib->pktlen);
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
++		if (pmlmepriv->wps_probe_resp_ie != NULL && pmlmepriv->p2p_probe_resp_ie != NULL) {
++			/* WPS IE */
++			_rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len);
++			pattrib->pktlen += pmlmepriv->wps_probe_resp_ie_len;
++			pframe += pmlmepriv->wps_probe_resp_ie_len;
++
++			/* P2P IE */
++			_rtw_memcpy(pframe, pmlmepriv->p2p_probe_resp_ie, pmlmepriv->p2p_probe_resp_ie_len);
++			pattrib->pktlen += pmlmepriv->p2p_probe_resp_ie_len;
++			pframe += pmlmepriv->p2p_probe_resp_ie_len;
++		}
++	} else
++#endif /* CONFIG_IOCTL_CFG80211		 */
++	{
++
++		/*	Todo: WPS IE */
++		/*	Noted by Albert 20100907 */
++		/*	According to the WPS specification, all the WPS attribute is presented by Big Endian. */
++
++		wpsielen = 0;
++		/*	WPS OUI */
++		*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
++		wpsielen += 4;
++
++		/*	WPS version */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
++		wpsielen += 2;
++
++		/*	Value: */
++		wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
++
++		/*	WiFi Simple Config State */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SIMPLE_CONF_STATE);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
++		wpsielen += 2;
++
++		/*	Value: */
++		wpsie[wpsielen++] = WPS_WSC_STATE_NOT_CONFIG;	/*	Not Configured. */
++
++		/*	Response Type */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_RESP_TYPE);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
++		wpsielen += 2;
++
++		/*	Value: */
++		wpsie[wpsielen++] = WPS_RESPONSE_TYPE_8021X;
++
++		/*	UUID-E */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_UUID_E);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0010);
++		wpsielen += 2;
++
++		/*	Value: */
++		if (pwdinfo->external_uuid == 0) {
++			_rtw_memset(wpsie + wpsielen, 0x0, 16);
++			_rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN);
++		} else
++			_rtw_memcpy(wpsie + wpsielen, pwdinfo->uuid, 0x10);
++		wpsielen += 0x10;
++
++		/*	Manufacturer */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MANUFACTURER);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0007);
++		wpsielen += 2;
++
++		/*	Value: */
++		_rtw_memcpy(wpsie + wpsielen, "Realtek", 7);
++		wpsielen += 7;
++
++		/*	Model Name */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NAME);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0006);
++		wpsielen += 2;
++
++		/*	Value: */
++		_rtw_memcpy(wpsie + wpsielen, "8192CU", 6);
++		wpsielen += 6;
++
++		/*	Model Number */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NUMBER);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
++		wpsielen += 2;
++
++		/*	Value: */
++		wpsie[wpsielen++] = 0x31;		/*	character 1 */
++
++		/*	Serial Number */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SERIAL_NUMBER);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(ETH_ALEN);
++		wpsielen += 2;
++
++		/*	Value: */
++		_rtw_memcpy(wpsie + wpsielen, "123456" , ETH_ALEN);
++		wpsielen += ETH_ALEN;
++
++		/*	Primary Device Type */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008);
++		wpsielen += 2;
++
++		/*	Value: */
++		/*	Category ID */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
++		wpsielen += 2;
++
++		/*	OUI */
++		*(u32 *)(wpsie + wpsielen) = cpu_to_be32(WPSOUI);
++		wpsielen += 4;
++
++		/*	Sub Category ID */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
++		wpsielen += 2;
++
++		/*	Device Name */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->device_name_len);
++		wpsielen += 2;
++
++		/*	Value: */
++		_rtw_memcpy(wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len);
++		wpsielen += pwdinfo->device_name_len;
++
++		/*	Config Method */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
++		wpsielen += 2;
++
++		/*	Value: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
++		wpsielen += 2;
++
++
++		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
++
++
++		p2pielen = build_probe_resp_p2p_ie(pwdinfo, pframe);
++		pframe += p2pielen;
++		pattrib->pktlen += p2pielen;
++	}
++
++#ifdef CONFIG_WFD
++	wfdielen = rtw_append_probe_resp_wfd_ie(padapter, pframe);
++	pframe += wfdielen;
++	pattrib->pktlen += wfdielen;
++#endif
++
++/* Vendor Specific IE */
++#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
++	pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_P2P_PROBERESP_VENDOR_IE_BIT);
++#endif
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++
++	dump_mgntframe(padapter, pmgntframe);
++
++	return;
++
++}
++
++int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack)
++{
++	int ret = _FAIL;
++	struct xmit_frame		*pmgntframe;
++	struct pkt_attrib		*pattrib;
++	unsigned char			*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short		*fctrl;
++	unsigned char			*mac;
++	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++	u8					wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };
++	u16					wpsielen = 0, p2pielen = 0;
++#ifdef CONFIG_WFD
++	u32					wfdielen = 0;
++#endif
++
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	if (IS_CCK_RATE(pattrib->rate)) {
++		/* force OFDM 6M rate */
++		pattrib->rate = MGN_6M;
++		pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G);
++	}
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	mac = adapter_mac_addr(padapter);
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	if (da) {
++		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);
++	} else {
++		if ((pwdinfo->p2p_info.scan_op_ch_only) || (pwdinfo->rx_invitereq_info.scan_op_ch_only)) {
++			/*	This two flags will be set when this is only the P2P client mode. */
++			_rtw_memcpy(pwlanhdr->addr1, pwdinfo->p2p_peer_interface_addr, ETH_ALEN);
++			_rtw_memcpy(pwlanhdr->addr3, pwdinfo->p2p_peer_interface_addr, ETH_ALEN);
++		} else {
++			/*	broadcast probe request frame */
++			_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
++			_rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN);
++		}
++	}
++	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_PROBEREQ);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ))
++		pframe = rtw_set_ie(pframe, _SSID_IE_, pwdinfo->tx_prov_disc_info.ssid.SsidLength, pwdinfo->tx_prov_disc_info.ssid.Ssid, &(pattrib->pktlen));
++	else
++		pframe = rtw_set_ie(pframe, _SSID_IE_, P2P_WILDCARD_SSID_LEN, pwdinfo->p2p_wildcard_ssid, &(pattrib->pktlen));
++	/*	Use the OFDM rate in the P2P probe request frame. ( 6(B), 9(B), 12(B), 24(B), 36, 48, 54 ) */
++	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen);
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
++		if (pmlmepriv->wps_probe_req_ie != NULL && pmlmepriv->p2p_probe_req_ie != NULL) {
++			/* WPS IE */
++			_rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len);
++			pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len;
++			pframe += pmlmepriv->wps_probe_req_ie_len;
++
++			/* P2P IE */
++			_rtw_memcpy(pframe, pmlmepriv->p2p_probe_req_ie, pmlmepriv->p2p_probe_req_ie_len);
++			pattrib->pktlen += pmlmepriv->p2p_probe_req_ie_len;
++			pframe += pmlmepriv->p2p_probe_req_ie_len;
++		}
++	} else
++#endif /* CONFIG_IOCTL_CFG80211 */
++	{
++
++		/*	WPS IE */
++		/*	Noted by Albert 20110221 */
++		/*	According to the WPS specification, all the WPS attribute is presented by Big Endian. */
++
++		wpsielen = 0;
++		/*	WPS OUI */
++		*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
++		wpsielen += 4;
++
++		/*	WPS version */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
++		wpsielen += 2;
++
++		/*	Value: */
++		wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
++
++		if (pmlmepriv->wps_probe_req_ie == NULL) {
++			/*	UUID-E */
++			/*	Type: */
++			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_UUID_E);
++			wpsielen += 2;
++
++			/*	Length: */
++			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0010);
++			wpsielen += 2;
++
++			/*	Value: */
++			if (pwdinfo->external_uuid == 0) {
++				_rtw_memset(wpsie + wpsielen, 0x0, 16);
++				_rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN);
++			} else
++				_rtw_memcpy(wpsie + wpsielen, pwdinfo->uuid, 0x10);
++			wpsielen += 0x10;
++
++			/*	Config Method */
++			/*	Type: */
++			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);
++			wpsielen += 2;
++
++			/*	Length: */
++			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
++			wpsielen += 2;
++
++			/*	Value: */
++			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
++			wpsielen += 2;
++		}
++
++		/*	Device Name */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->device_name_len);
++		wpsielen += 2;
++
++		/*	Value: */
++		_rtw_memcpy(wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len);
++		wpsielen += pwdinfo->device_name_len;
++
++		/*	Primary Device Type */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008);
++		wpsielen += 2;
++
++		/*	Value: */
++		/*	Category ID */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_RTK_WIDI);
++		wpsielen += 2;
++
++		/*	OUI */
++		*(u32 *)(wpsie + wpsielen) = cpu_to_be32(WPSOUI);
++		wpsielen += 4;
++
++		/*	Sub Category ID */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_RTK_DMP);
++		wpsielen += 2;
++
++		/*	Device Password ID */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
++		wpsielen += 2;
++
++		/*	Value: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);	/*	Registrar-specified */
++		wpsielen += 2;
++
++		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
++
++		/*	P2P OUI */
++		p2pielen = 0;
++		p2pie[p2pielen++] = 0x50;
++		p2pie[p2pielen++] = 0x6F;
++		p2pie[p2pielen++] = 0x9A;
++		p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
++
++		/*	Commented by Albert 20110221 */
++		/*	According to the P2P Specification, the probe request frame should contain 5 P2P attributes */
++		/*	1. P2P Capability */
++		/*	2. P2P Device ID if this probe request wants to find the specific P2P device */
++		/*	3. Listen Channel */
++		/*	4. Extended Listen Timing */
++		/*	5. Operating Channel if this WiFi is working as the group owner now */
++
++		/*	P2P Capability */
++		/*	Type: */
++		p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
++
++		/*	Length: */
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
++		p2pielen += 2;
++
++		/*	Value: */
++		/*	Device Capability Bitmap, 1 byte */
++		p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
++
++		/*	Group Capability Bitmap, 1 byte */
++		if (pwdinfo->persistent_supported)
++			p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;
++		else
++			p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT;
++
++		/*	Listen Channel */
++		/*	Type: */
++		p2pie[p2pielen++] = P2P_ATTR_LISTEN_CH;
++
++		/*	Length: */
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
++		p2pielen += 2;
++
++		/*	Value: */
++		/*	Country String */
++		p2pie[p2pielen++] = 'X';
++		p2pie[p2pielen++] = 'X';
++
++		/*	The third byte should be set to 0x04. */
++		/*	Described in the "Operating Channel Attribute" section. */
++		p2pie[p2pielen++] = 0x04;
++
++		/*	Operating Class */
++		p2pie[p2pielen++] = 0x51;	/*	Copy from SD7 */
++
++		/*	Channel Number */
++		p2pie[p2pielen++] = pwdinfo->listen_channel;	/*	listen channel */
++
++
++		/*	Extended Listen Timing */
++		/*	Type: */
++		p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING;
++
++		/*	Length: */
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004);
++		p2pielen += 2;
++
++		/*	Value: */
++		/*	Availability Period */
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
++		p2pielen += 2;
++
++		/*	Availability Interval */
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
++		p2pielen += 2;
++
++		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++			/*	Operating Channel (if this WiFi is working as the group owner now) */
++			/*	Type: */
++			p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
++
++			/*	Length: */
++			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
++			p2pielen += 2;
++
++			/*	Value: */
++			/*	Country String */
++			p2pie[p2pielen++] = 'X';
++			p2pie[p2pielen++] = 'X';
++
++			/*	The third byte should be set to 0x04. */
++			/*	Described in the "Operating Channel Attribute" section. */
++			p2pie[p2pielen++] = 0x04;
++
++			/*	Operating Class */
++			p2pie[p2pielen++] = 0x51;	/*	Copy from SD7 */
++
++			/*	Channel Number */
++			p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
++
++		}
++
++		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
++
++	}
++
++#ifdef CONFIG_WFD
++	wfdielen = rtw_append_probe_req_wfd_ie(padapter, pframe);
++	pframe += wfdielen;
++	pattrib->pktlen += wfdielen;
++#endif
++
++/* Vendor Specific IE */
++#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
++	pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_P2P_PROBEREQ_VENDOR_IE_BIT);
++#endif
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++
++	if (wait_ack)
++		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
++	else {
++		dump_mgntframe(padapter, pmgntframe);
++		ret = _SUCCESS;
++	}
++
++exit:
++	return ret;
++}
++
++inline void issue_probereq_p2p(_adapter *adapter, u8 *da)
++{
++	_issue_probereq_p2p(adapter, da, _FALSE);
++}
++
++/*
++ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
++ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
++ * try_cnt means the maximal TX count to try
++ */
++int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms)
++{
++	int ret;
++	int i = 0;
++	systime start = rtw_get_current_time();
++
++	do {
++		ret = _issue_probereq_p2p(adapter, da, wait_ms > 0 ? _TRUE : _FALSE);
++
++		i++;
++
++		if (RTW_CANNOT_RUN(adapter))
++			break;
++
++		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
++			rtw_msleep_os(wait_ms);
++
++	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
++
++	if (ret != _FAIL) {
++		ret = _SUCCESS;
++#ifndef DBG_XMIT_ACK
++		goto exit;
++#endif
++	}
++
++	if (try_cnt && wait_ms) {
++		if (da)
++			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
++				FUNC_ADPT_ARG(adapter), MAC_ARG(da), rtw_get_oper_ch(adapter),
++				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
++		else
++			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
++				FUNC_ADPT_ARG(adapter), rtw_get_oper_ch(adapter),
++				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
++	}
++exit:
++	return ret;
++}
++
++#endif /* CONFIG_P2P */
++
++s32 rtw_action_public_decache(union recv_frame *rframe, u8 token_offset)
++{
++	_adapter *adapter = rframe->u.hdr.adapter;
++	struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv);
++	u8 *frame = rframe->u.hdr.rx_data;
++	u16 seq_ctrl = ((rframe->u.hdr.attrib.seq_num & 0xffff) << 4) | (rframe->u.hdr.attrib.frag_num & 0xf);
++	u8 token = *(rframe->u.hdr.rx_data + sizeof(struct rtw_ieee80211_hdr_3addr) + token_offset);
++
++	if (GetRetry(frame)) {
++		if ((seq_ctrl == mlmeext->action_public_rxseq)
++		    && (token == mlmeext->action_public_dialog_token)
++		   ) {
++			RTW_INFO(FUNC_ADPT_FMT" seq_ctrl=0x%x, rxseq=0x%x, token:%d\n",
++				FUNC_ADPT_ARG(adapter), seq_ctrl, mlmeext->action_public_rxseq, token);
++			return _FAIL;
++		}
++	}
++
++	/* TODO: per sta seq & token */
++	mlmeext->action_public_rxseq = seq_ctrl;
++	mlmeext->action_public_dialog_token = token;
++
++	return _SUCCESS;
++}
++
++unsigned int on_action_public_p2p(union recv_frame *precv_frame)
++{
++	_adapter *padapter = precv_frame->u.hdr.adapter;
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	uint len = precv_frame->u.hdr.len;
++	u8 *frame_body;
++#ifdef CONFIG_P2P
++	u8 *p2p_ie;
++	u32	p2p_ielen;
++	struct	wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++	u8	result = P2P_STATUS_SUCCESS;
++	u8	empty_addr[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
++	u8 *merged_p2pie = NULL;
++	u32 merged_p2p_ielen = 0;
++#endif /* CONFIG_P2P */
++
++	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++
++#ifdef CONFIG_P2P
++	_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);
++#ifdef CONFIG_IOCTL_CFG80211
++	if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211)
++		rtw_cfg80211_rx_p2p_action_public(padapter, precv_frame);
++	else
++#endif /* CONFIG_IOCTL_CFG80211 */
++	{
++		/*	Do nothing if the driver doesn't enable the P2P function. */
++		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE))
++			return _SUCCESS;
++
++		len -= sizeof(struct rtw_ieee80211_hdr_3addr);
++
++		switch (frame_body[6]) { /* OUI Subtype */
++		case P2P_GO_NEGO_REQ: {
++			RTW_INFO("[%s] Got GO Nego Req Frame\n", __FUNCTION__);
++			_rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info));
++
++			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ))
++				rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
++
++			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) {
++				/*	Commented by Albert 20110526 */
++				/*	In this case, this means the previous nego fail doesn't be reset yet. */
++				_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
++				/*	Restore the previous p2p state */
++				rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
++				RTW_INFO("[%s] Restore the previous p2p state to %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo));
++			}
++#ifdef CONFIG_CONCURRENT_MODE
++			if (rtw_mi_buddy_check_fwstate(padapter, WIFI_ASOC_STATE))
++				_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);
++#endif /* CONFIG_CONCURRENT_MODE */
++
++			/*	Commented by Kurt 20110902 */
++			/* Add if statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. */
++			if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING))
++				rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++
++			/*	Commented by Kurt 20120113 */
++			/*	Get peer_dev_addr here if peer doesn't issue prov_disc frame. */
++			if (_rtw_memcmp(pwdinfo->rx_prov_disc_info.peerDevAddr, empty_addr, ETH_ALEN))
++				_rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN);
++
++			result = process_p2p_group_negotation_req(pwdinfo, frame_body, len);
++			issue_p2p_GO_response(padapter, get_addr2_ptr(pframe), frame_body, len, result);
++
++			/*	Commented by Albert 20110718 */
++			/*	No matter negotiating or negotiation failure, the driver should set up the restore P2P state timer. */
++#ifdef CONFIG_CONCURRENT_MODE
++			/*	Commented by Albert 20120107 */
++			_set_timer(&pwdinfo->restore_p2p_state_timer, 3000);
++#else /* CONFIG_CONCURRENT_MODE */
++			_set_timer(&pwdinfo->restore_p2p_state_timer, 5000);
++#endif /* CONFIG_CONCURRENT_MODE */
++			break;
++		}
++		case P2P_GO_NEGO_RESP: {
++			RTW_INFO("[%s] Got GO Nego Resp Frame\n", __FUNCTION__);
++
++			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) {
++				/*	Commented by Albert 20110425 */
++				/*	The restore timer is enabled when issuing the nego request frame of rtw_p2p_connect function. */
++				_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
++				pwdinfo->nego_req_info.benable = _FALSE;
++				result = process_p2p_group_negotation_resp(pwdinfo, frame_body, len);
++				issue_p2p_GO_confirm(pwdinfo->padapter, get_addr2_ptr(pframe), result);
++				if (P2P_STATUS_SUCCESS == result) {
++					if (rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT) {
++						pwdinfo->p2p_info.operation_ch[0] = pwdinfo->peer_operating_ch;
++#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
++						pwdinfo->p2p_info.operation_ch[1] = 1;	/* Check whether GO is operating in channel 1; */
++						pwdinfo->p2p_info.operation_ch[2] = 6;	/* Check whether GO is operating in channel 6; */
++						pwdinfo->p2p_info.operation_ch[3] = 11;	/* Check whether GO is operating in channel 11; */
++#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
++						pwdinfo->p2p_info.scan_op_ch_only = 1;
++						_set_timer(&pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH);
++					}
++				}
++
++				/*	Reset the dialog token for group negotiation frames. */
++				pwdinfo->negotiation_dialog_token = 1;
++
++				if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL))
++					_set_timer(&pwdinfo->restore_p2p_state_timer, 5000);
++			} else
++				RTW_INFO("[%s] Skipped GO Nego Resp Frame (p2p_state != P2P_STATE_GONEGO_ING)\n", __FUNCTION__);
++
++			break;
++		}
++		case P2P_GO_NEGO_CONF: {
++			RTW_INFO("[%s] Got GO Nego Confirm Frame\n", __FUNCTION__);
++			result = process_p2p_group_negotation_confirm(pwdinfo, frame_body, len);
++			if (P2P_STATUS_SUCCESS == result) {
++				if (rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT) {
++					pwdinfo->p2p_info.operation_ch[0] = pwdinfo->peer_operating_ch;
++#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
++					pwdinfo->p2p_info.operation_ch[1] = 1;	/* Check whether GO is operating in channel 1; */
++					pwdinfo->p2p_info.operation_ch[2] = 6;	/* Check whether GO is operating in channel 6; */
++					pwdinfo->p2p_info.operation_ch[3] = 11;	/* Check whether GO is operating in channel 11; */
++#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
++					pwdinfo->p2p_info.scan_op_ch_only = 1;
++					_set_timer(&pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH);
++				}
++			}
++			break;
++		}
++		case P2P_INVIT_REQ: {
++			/*	Added by Albert 2010/10/05 */
++			/*	Received the P2P Invite Request frame. */
++
++			RTW_INFO("[%s] Got invite request frame!\n", __FUNCTION__);
++			p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen);
++			if (p2p_ie) {
++				/*	Parse the necessary information from the P2P Invitation Request frame. */
++				/*	For example: The MAC address of sending this P2P Invitation Request frame. */
++				u32	attr_contentlen = 0;
++				u8	status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
++				struct group_id_info group_id;
++				u8	invitation_flag = 0;
++
++				merged_p2p_ielen = rtw_get_p2p_merged_ies_len(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_);
++
++				merged_p2pie = rtw_zmalloc(merged_p2p_ielen + 2);	/* 2 is for EID and Length */
++				if (merged_p2pie == NULL) {
++					RTW_INFO("[%s] Malloc p2p ie fail\n", __FUNCTION__);
++					goto exit;
++				}
++				_rtw_memset(merged_p2pie, 0x00, merged_p2p_ielen);
++
++				merged_p2p_ielen = rtw_p2p_merge_ies(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, merged_p2pie);
++
++				rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_INVITATION_FLAGS, &invitation_flag, &attr_contentlen);
++				if (attr_contentlen) {
++
++					rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_BSSID, pwdinfo->p2p_peer_interface_addr, &attr_contentlen);
++					/*	Commented by Albert 20120510 */
++					/*	Copy to the pwdinfo->p2p_peer_interface_addr. */
++					/*	So that the WFD UI ( or Sigma ) can get the peer interface address by using the following command. */
++					/*	#> iwpriv wlan0 p2p_get peer_ifa */
++					/*	After having the peer interface address, the sigma can find the correct conf file for wpa_supplicant. */
++
++					if (attr_contentlen) {
++						RTW_INFO("[%s] GO's BSSID = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__,
++							pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1],
++							pwdinfo->p2p_peer_interface_addr[2], pwdinfo->p2p_peer_interface_addr[3],
++							pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);
++					}
++
++					if (invitation_flag & P2P_INVITATION_FLAGS_PERSISTENT) {
++						/*	Re-invoke the persistent group. */
++
++						_rtw_memset(&group_id, 0x00, sizeof(struct group_id_info));
++						rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, (u8 *) &group_id, &attr_contentlen);
++						if (attr_contentlen) {
++							if (_rtw_memcmp(group_id.go_device_addr, adapter_mac_addr(padapter), ETH_ALEN)) {
++								/*	The p2p device sending this p2p invitation request wants this Wi-Fi device to be the persistent GO. */
++								rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_GO);
++								rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++								status_code = P2P_STATUS_SUCCESS;
++							} else {
++								/*	The p2p device sending this p2p invitation request wants to be the persistent GO. */
++								if (is_matched_in_profilelist(pwdinfo->p2p_peer_interface_addr, &pwdinfo->profileinfo[0])) {
++									u8 operatingch_info[5] = { 0x00 };
++									if (rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info,
++										&attr_contentlen)) {
++										if (rtw_chset_search_ch(adapter_to_chset(padapter), (u32)operatingch_info[4]) >= 0) {
++											/*	The operating channel is acceptable for this device. */
++											pwdinfo->rx_invitereq_info.operation_ch[0] = operatingch_info[4];
++#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
++											pwdinfo->rx_invitereq_info.operation_ch[1] = 1;		/* Check whether GO is operating in channel 1; */
++											pwdinfo->rx_invitereq_info.operation_ch[2] = 6;		/* Check whether GO is operating in channel 6; */
++											pwdinfo->rx_invitereq_info.operation_ch[3] = 11;		/* Check whether GO is operating in channel 11; */
++#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
++											pwdinfo->rx_invitereq_info.scan_op_ch_only = 1;
++											_set_timer(&pwdinfo->reset_ch_sitesurvey, P2P_RESET_SCAN_CH);
++											rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH);
++											rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++											status_code = P2P_STATUS_SUCCESS;
++										} else {
++											/*	The operating channel isn't supported by this device. */
++											rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH);
++											rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++											status_code = P2P_STATUS_FAIL_NO_COMMON_CH;
++											_set_timer(&pwdinfo->restore_p2p_state_timer, 3000);
++										}
++									} else {
++										/*	Commented by Albert 20121130 */
++										/*	Intel will use the different P2P IE to store the operating channel information */
++										/*	Workaround for Intel WiDi 3.5 */
++										rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH);
++										rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++										status_code = P2P_STATUS_SUCCESS;
++									}
++								} else {
++									rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH);
++									status_code = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP;
++								}
++							}
++						} else {
++							RTW_INFO("[%s] P2P Group ID Attribute NOT FOUND!\n", __FUNCTION__);
++							status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
++						}
++					} else {
++						/*	Received the invitation to join a P2P group. */
++
++						_rtw_memset(&group_id, 0x00, sizeof(struct group_id_info));
++						rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, (u8 *) &group_id, &attr_contentlen);
++						if (attr_contentlen) {
++							if (_rtw_memcmp(group_id.go_device_addr, adapter_mac_addr(padapter), ETH_ALEN)) {
++								/*	In this case, the GO can't be myself. */
++								rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH);
++								status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
++							} else {
++								/*	The p2p device sending this p2p invitation request wants to join an existing P2P group */
++								/*	Commented by Albert 2012/06/28 */
++								/*	In this case, this Wi-Fi device should use the iwpriv command to get the peer device address. */
++								/*	The peer device address should be the destination address for the provisioning discovery request. */
++								/*	Then, this Wi-Fi device should use the iwpriv command to get the peer interface address. */
++								/*	The peer interface address should be the address for WPS mac address */
++								_rtw_memcpy(pwdinfo->p2p_peer_device_addr, group_id.go_device_addr , ETH_ALEN);
++								rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++								rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_JOIN);
++								status_code = P2P_STATUS_SUCCESS;
++							}
++						} else {
++							RTW_INFO("[%s] P2P Group ID Attribute NOT FOUND!\n", __FUNCTION__);
++							status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
++						}
++					}
++				} else {
++					RTW_INFO("[%s] P2P Invitation Flags Attribute NOT FOUND!\n", __FUNCTION__);
++					status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
++				}
++
++				RTW_INFO("[%s] status_code = %d\n", __FUNCTION__, status_code);
++
++				pwdinfo->inviteresp_info.token = frame_body[7];
++				issue_p2p_invitation_response(padapter, get_addr2_ptr(pframe), pwdinfo->inviteresp_info.token, status_code);
++				_set_timer(&pwdinfo->restore_p2p_state_timer, 3000);
++			}
++			break;
++		}
++		case P2P_INVIT_RESP: {
++			u8	attr_content = 0x00;
++			u32	attr_contentlen = 0;
++
++			RTW_INFO("[%s] Got invite response frame!\n", __FUNCTION__);
++			_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
++			p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen);
++			if (p2p_ie) {
++				rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen);
++
++				if (attr_contentlen == 1) {
++					RTW_INFO("[%s] Status = %d\n", __FUNCTION__, attr_content);
++					pwdinfo->invitereq_info.benable = _FALSE;
++
++					if (attr_content == P2P_STATUS_SUCCESS) {
++						if (_rtw_memcmp(pwdinfo->invitereq_info.go_bssid, adapter_mac_addr(padapter), ETH_ALEN))
++							rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++						else
++							rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++
++						rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_OK);
++					} else {
++						rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++						rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL);
++					}
++				} else {
++					rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++					rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL);
++				}
++			} else {
++				rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++				rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL);
++			}
++
++			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL))
++				_set_timer(&pwdinfo->restore_p2p_state_timer, 5000);
++			break;
++		}
++		case P2P_DEVDISC_REQ:
++
++			process_p2p_devdisc_req(pwdinfo, pframe, len);
++
++			break;
++
++		case P2P_DEVDISC_RESP:
++
++			process_p2p_devdisc_resp(pwdinfo, pframe, len);
++
++			break;
++
++		case P2P_PROVISION_DISC_REQ:
++			RTW_INFO("[%s] Got Provisioning Discovery Request Frame\n", __FUNCTION__);
++			process_p2p_provdisc_req(pwdinfo, pframe, len);
++			_rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN);
++
++			/* 20110902 Kurt */
++			/* Add the following statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. */
++			if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ))
++				rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++
++			rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ);
++			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT);
++			break;
++
++		case P2P_PROVISION_DISC_RESP:
++			/*	Commented by Albert 20110707 */
++			/*	Should we check the pwdinfo->tx_prov_disc_info.bsent flag here?? */
++			RTW_INFO("[%s] Got Provisioning Discovery Response Frame\n", __FUNCTION__);
++			/*	Commented by Albert 20110426 */
++			/*	The restore timer is enabled when issuing the provisioing request frame in rtw_p2p_prov_disc function. */
++			_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
++			rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP);
++			process_p2p_provdisc_resp(pwdinfo, pframe);
++			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT);
++			break;
++
++		}
++	}
++
++
++exit:
++
++	if (merged_p2pie)
++		rtw_mfree(merged_p2pie, merged_p2p_ielen + 2);
++#endif /* CONFIG_P2P */
++	return _SUCCESS;
++}
++
++unsigned int on_action_public_vendor(union recv_frame *precv_frame)
++{
++	unsigned int ret = _FAIL;
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
++	_adapter *adapter = precv_frame->u.hdr.adapter;
++	int cnt = 0;
++	char msg[64];
++
++	if (_rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE) {
++		if (rtw_action_public_decache(precv_frame, 7) == _FAIL)
++			goto exit;
++
++		if (!hal_chk_wl_func(precv_frame->u.hdr.adapter, WL_FUNC_MIRACAST))
++			rtw_rframe_del_wfd_ie(precv_frame, 8);
++
++		ret = on_action_public_p2p(precv_frame);
++	} else if (_rtw_memcmp(frame_body + 2, DPP_OUI, 4) == _TRUE) {
++		u8 dpp_type = frame_body[7];
++
++#ifdef CONFIG_IOCTL_CFG80211
++		cnt += sprintf((msg + cnt), "DPP(type:%u)", dpp_type);
++		rtw_cfg80211_rx_action(adapter, precv_frame, msg);
++#endif
++	}
++
++exit:
++	return ret;
++}
++
++unsigned int on_action_public_default(union recv_frame *precv_frame, u8 action)
++{
++	unsigned int ret = _FAIL;
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
++	u8 token;
++	_adapter *adapter = precv_frame->u.hdr.adapter;
++	int cnt = 0;
++	char msg[64];
++
++	token = frame_body[2];
++
++	if (rtw_action_public_decache(precv_frame, 2) == _FAIL)
++		goto exit;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	cnt += sprintf((msg + cnt), "%s(token:%u)", action_public_str(action), token);
++	rtw_cfg80211_rx_action(adapter, precv_frame, msg);
++#endif
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++
++unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame)
++{
++	unsigned int ret = _FAIL;
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	uint frame_len = precv_frame->u.hdr.len;
++	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
++	u8 category, action;
++
++	/* check RA matches or not */
++	if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))
++		goto exit;
++
++	category = frame_body[0];
++	if (category != RTW_WLAN_CATEGORY_PUBLIC)
++		goto exit;
++
++	action = frame_body[1];
++	switch (action) {
++	case ACT_PUBLIC_BSSCOEXIST:
++#ifdef CONFIG_80211N_HT
++#ifdef CONFIG_AP_MODE
++		/*20/40 BSS Coexistence Management frame is a Public Action frame*/
++		if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
++			rtw_process_public_act_bsscoex(padapter, pframe, frame_len);
++#endif /*CONFIG_AP_MODE*/
++#endif /*CONFIG_80211N_HT*/
++		break;
++	case ACT_PUBLIC_VENDOR:
++		ret = on_action_public_vendor(precv_frame);
++		break;
++	default:
++		ret = on_action_public_default(precv_frame, action);
++		break;
++	}
++
++exit:
++	return ret;
++}
++
++unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame)
++{
++#ifdef CONFIG_RTW_80211R
++	u32	ret = _FAIL;
++	u32	frame_len = 0;
++	u8	action_code = 0;
++	u8	category = 0;
++	u8	*pframe = NULL;
++	u8	*pframe_body = NULL;
++	u8 	tgt_addr[ETH_ALEN];
++	u8	*pie = NULL;
++	u32	ft_ie_len = 0;
++	u32 status_code = 0;
++	struct mlme_ext_priv *pmlmeext = NULL;
++	struct mlme_ext_info *pmlmeinfo = NULL;
++	struct mlme_priv *pmlmepriv = NULL;
++	struct wlan_network *proam_target = NULL;
++	struct ft_roam_info *pft_roam = NULL;
++	_irqL  irqL;
++
++	pmlmeext = &(padapter->mlmeextpriv);
++	pmlmeinfo = &(pmlmeext->mlmext_info);
++	pmlmepriv = &(padapter->mlmepriv);
++	pft_roam = &(pmlmepriv->ft_roam);
++	pframe = precv_frame->u.hdr.rx_data;
++	frame_len = precv_frame->u.hdr.len;
++	pframe_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
++	category = pframe_body[0];
++
++	if (category != RTW_WLAN_CATEGORY_FT)
++		goto exit;
++
++	action_code = pframe_body[1];
++	switch (action_code) {
++	case RTW_WLAN_ACTION_FT_RSP:
++		RTW_INFO("FT: RTW_WLAN_ACTION_FT_RSP recv.\n");
++		if (!_rtw_memcmp(adapter_mac_addr(padapter), &pframe_body[2], ETH_ALEN)) {
++			RTW_ERR("FT: Unmatched STA MAC Address "MAC_FMT"\n", MAC_ARG(&pframe_body[2]));
++			goto exit;
++		}
++
++		status_code = le16_to_cpu(*(u16 *)((SIZE_PTR)pframe +  sizeof(struct rtw_ieee80211_hdr_3addr) + 14));
++		if (status_code != 0) {
++			RTW_ERR("FT: WLAN ACTION FT RESPONSE fail, status: %d\n", status_code);
++			goto exit;
++		}
++
++		_rtw_memcpy(tgt_addr, &pframe_body[8], ETH_ALEN);
++		if (is_zero_mac_addr(tgt_addr) || is_broadcast_mac_addr(tgt_addr)) {
++			RTW_ERR("FT: Invalid Target MAC Address "MAC_FMT"\n", MAC_ARG(tgt_addr));
++			goto exit;
++		}
++
++		pie = rtw_get_ie(pframe_body, _MDIE_, &ft_ie_len, frame_len);
++		if (pie) {
++			if (!_rtw_memcmp(&pft_roam->mdid, pie+2, 2)) {
++				RTW_ERR("FT: Invalid MDID\n");
++				goto exit;
++			}
++		}
++
++		rtw_ft_set_status(padapter, RTW_FT_REQUESTED_STA);
++		_cancel_timer_ex(&pmlmeext->ft_link_timer);
++
++		/*Disconnect current AP*/
++		receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress, WLAN_REASON_ACTIVE_ROAM, _FALSE);
++
++		pft_roam->ft_action_len = frame_len;
++		_rtw_memcpy(pft_roam->ft_action, pframe, rtw_min(frame_len, RTW_FT_MAX_IE_SZ));
++		ret = _SUCCESS;
++		break;
++	case RTW_WLAN_ACTION_FT_REQ:
++	case RTW_WLAN_ACTION_FT_CONF:
++	case RTW_WLAN_ACTION_FT_ACK:
++	default:
++		RTW_ERR("FT: Unsupported FT Action!\n");
++		break;
++	}
++
++exit:
++	return ret;
++#else
++	return _SUCCESS;
++#endif
++}
++
++unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame)
++{
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
++	u8 category, action;
++
++	/* check RA matches or not */
++	if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))
++		goto exit;
++
++	category = frame_body[0];
++	if (category != RTW_WLAN_CATEGORY_HT)
++		goto exit;
++
++	action = frame_body[1];
++	switch (action) {
++	case RTW_WLAN_ACTION_HT_SM_PS:
++#ifdef CONFIG_80211N_HT
++#ifdef CONFIG_AP_MODE
++		if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
++			rtw_process_ht_action_smps(padapter, get_addr2_ptr(pframe), frame_body[2]);
++#endif /*CONFIG_AP_MODE*/
++#endif /*CONFIG_80211N_HT*/
++		break;
++	case RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING:
++#ifdef CONFIG_BEAMFORMING
++		/*RTW_INFO("RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING\n");*/
++		rtw_beamforming_get_report_frame(padapter, precv_frame);
++#endif /*CONFIG_BEAMFORMING*/
++		break;
++	default:
++		break;
++	}
++
++exit:
++
++	return _SUCCESS;
++}
++
++#ifdef CONFIG_IEEE80211W
++unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame)
++{
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct sta_info		*psta;
++	struct sta_priv		*pstapriv = &padapter->stapriv;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	u16 tid;
++	/* Baron */
++
++	RTW_INFO("OnAction_sa_query\n");
++
++	switch (pframe[WLAN_HDR_A3_LEN + 1]) {
++	case 0: /* SA Query req */
++		_rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN + 2], sizeof(u16));
++		RTW_INFO("OnAction_sa_query request,action=%d, tid=%04x, pframe=%02x-%02x\n"
++			, pframe[WLAN_HDR_A3_LEN + 1], tid, pframe[WLAN_HDR_A3_LEN + 2], pframe[WLAN_HDR_A3_LEN + 3]);
++		issue_action_SA_Query(padapter, get_addr2_ptr(pframe), 1, tid, IEEE80211W_RIGHT_KEY);
++		break;
++
++	case 1: /* SA Query rsp */
++		psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
++		if (psta != NULL)
++			_cancel_timer_ex(&psta->dot11w_expire_timer);
++
++		_rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN + 2], sizeof(u16));
++		RTW_INFO("OnAction_sa_query response,action=%d, tid=%04x, cancel timer\n", pframe[WLAN_HDR_A3_LEN + 1], tid);
++		break;
++	default:
++		break;
++	}
++	if (0) {
++		int pp;
++		printk("pattrib->pktlen = %d =>", pattrib->pkt_len);
++		for (pp = 0; pp < pattrib->pkt_len; pp++)
++			printk(" %02x ", pframe[pp]);
++		printk("\n");
++	}
++
++	return _SUCCESS;
++}
++#endif /* CONFIG_IEEE80211W */
++
++unsigned int on_action_rm(_adapter *padapter, union recv_frame *precv_frame)
++{
++#ifdef CONFIG_RTW_80211K
++	return rm_on_action(padapter, precv_frame);
++#else
++	return _SUCCESS;
++#endif  /* CONFIG_RTW_80211K */
++}
++
++unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame)
++{
++	return _SUCCESS;
++}
++
++unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame)
++{
++#ifdef CONFIG_80211AC_VHT
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	struct rtw_ieee80211_hdr_3addr *whdr = (struct rtw_ieee80211_hdr_3addr *)pframe;
++	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
++	u8 category, action;
++	struct sta_info *psta = NULL;
++
++	/* check RA matches or not */
++	if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))
++		goto exit;
++
++	category = frame_body[0];
++	if (category != RTW_WLAN_CATEGORY_VHT)
++		goto exit;
++
++	action = frame_body[1];
++	switch (action) {
++	case RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING:
++#ifdef CONFIG_BEAMFORMING
++		/*RTW_INFO("RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING\n");*/
++		rtw_beamforming_get_report_frame(padapter, precv_frame);
++#endif /*CONFIG_BEAMFORMING*/
++		break;
++	case RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION:
++		/* CategoryCode(1) + ActionCode(1) + OpModeNotification(1) */
++		/* RTW_INFO("RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION\n"); */
++		psta = rtw_get_stainfo(&padapter->stapriv, whdr->addr2);
++		if (psta)
++			rtw_process_vht_op_mode_notify(padapter, &frame_body[2], psta);
++		break;
++	case RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT:
++#ifdef CONFIG_BEAMFORMING
++#ifdef RTW_BEAMFORMING_VERSION_2
++		rtw_beamforming_get_vht_gid_mgnt_frame(padapter, precv_frame);
++#endif /* RTW_BEAMFORMING_VERSION_2 */
++#endif /* CONFIG_BEAMFORMING */
++		break;
++	default:
++		break;
++	}
++
++exit:
++#endif /* CONFIG_80211AC_VHT */
++
++	return _SUCCESS;
++}
++
++unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame)
++{
++#ifdef CONFIG_P2P
++	u8 *frame_body;
++	u8 category, OUI_Subtype, dialogToken = 0;
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	uint len = precv_frame->u.hdr.len;
++	struct	wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++	/* check RA matches or not */
++	if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))
++		return _SUCCESS;
++
++	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++
++	category = frame_body[0];
++	if (category != RTW_WLAN_CATEGORY_P2P)
++		return _SUCCESS;
++
++	if (cpu_to_be32(*((u32 *)(frame_body + 1))) != P2POUI)
++		return _SUCCESS;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (adapter_wdev_data(padapter)->p2p_enabled
++		&& pwdinfo->driver_interface == DRIVER_CFG80211
++	) {
++		rtw_cfg80211_rx_action_p2p(padapter, precv_frame);
++		return _SUCCESS;
++	} else
++#endif /* CONFIG_IOCTL_CFG80211 */
++	{
++		len -= sizeof(struct rtw_ieee80211_hdr_3addr);
++		OUI_Subtype = frame_body[5];
++		dialogToken = frame_body[6];
++
++		switch (OUI_Subtype) {
++		case P2P_NOTICE_OF_ABSENCE:
++
++			break;
++
++		case P2P_PRESENCE_REQUEST:
++
++			process_p2p_presence_req(pwdinfo, pframe, len);
++
++			break;
++
++		case P2P_PRESENCE_RESPONSE:
++
++			break;
++
++		case P2P_GO_DISC_REQUEST:
++
++			break;
++
++		default:
++			break;
++
++		}
++	}
++#endif /* CONFIG_P2P */
++
++	return _SUCCESS;
++
++}
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++unsigned int OnAction_tbtx_token(_adapter *padapter, union recv_frame *precv_frame)
++{
++#define TOKEN_REQ 0x00
++#define TOKEN_REL 0x01
++
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct sta_info *psta;
++	u32 xmit_time;
++	u8 *src=NULL, *pframe = precv_frame->u.hdr.rx_data;
++	u8 tbtx_action_code;
++	u8 i, nr_send;
++	uint tx_duration = 0;
++
++	if (padapter->tbtx_capability == _FALSE)
++		goto exit;
++
++	tbtx_action_code = *(pframe + WLAN_HDR_A3_LEN + 1);
++
++
++	switch (tbtx_action_code)
++	{
++		case TOKEN_REQ:
++			// parse duration
++			tx_duration = le32_to_cpu(*(uint *)(pframe + WLAN_HDR_A3_LEN + 2));
++			padapter->tbtx_duration = tx_duration/1000; // Mirocsecond to Millisecond
++			ATOMIC_SET(&padapter->tbtx_tx_pause, _FALSE);
++			rtw_tx_control_cmd(padapter);
++			_set_timer(&pmlmeext->tbtx_xmit_timer, padapter->tbtx_duration);
++			ATOMIC_SET(&padapter->tbtx_remove_tx_pause, _FALSE);
++#if defined(CONFIG_SDIO_HCI) && !defined(CONFIG_SDIO_TX_TASKLET)
++			_rtw_up_sema(&pxmitpriv->SdioXmitSema);
++#else
++			tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
++#endif
++			break;
++#ifdef CONFIG_AP_MODE
++		case TOKEN_REL:
++			src = get_addr2_ptr(pframe);
++			if (!src)
++				goto exit;
++			psta = rtw_get_stainfo(&padapter->stapriv, src);
++			if (!psta)
++				goto exit;
++
++			if (ATOMIC_READ(&pstapriv->nr_token_keeper) < 1)
++				goto exit;
++
++			for (i=0; i< NR_MAXSTA_INSLOT; i++) {
++				if (pstapriv->token_holder[i] == psta) {
++					pstapriv->token_holder[i] = NULL;
++					//RTW_INFO("macaddr1:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
++					ATOMIC_DEC(&pstapriv->nr_token_keeper);
++					break;
++				}
++			}
++
++			if (ATOMIC_READ(&pstapriv->nr_token_keeper) == 0)
++				_set_timer(&pmlmeext->tbtx_token_dispatch_timer, 1);
++
++			break;
++#endif
++		default:
++			RTW_INFO("Undefined Action Code\n");
++			goto exit;
++			break;
++	}
++
++exit:
++	return _SUCCESS;
++}
++
++void rtw_issue_action_token_rel(_adapter *padapter)
++{
++
++	// Todo: 
++	// gen token
++	/* Token Release Format
++		Category code : 	1 Byte
++		Action code : 		1 Byte */
++	int ret = _FAIL;
++	//u16	*fctrl;
++	u8	val = 0x01;
++	u8	category = RTW_WLAN_CATEGORY_TBTX;
++	u8	*pframe;
++	struct xmit_frame		*pmgntframe;
++	struct pkt_attrib		*pattrib;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	struct	mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	//struct sta_info			*psta;
++	//struct sta_priv			*pstapriv = &padapter->stapriv;
++	//struct registry_priv		*pregpriv = &padapter->registrypriv;
++	
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		return;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++	
++	/*update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++	pattrib->rate = MGN_24M; /* issue action release using OFDM rate? 20190716 Bruce add */ 
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++	
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	//fctrl = &(pwlanhdr->frame_ctl);
++	//*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++	// SetSeqNum??
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(val), &(pattrib->pktlen));
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(padapter, pmgntframe);
++
++	//RTW_INFO("%s\n", __func__);
++
++}
++#endif
++
++unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame)
++{
++	int i;
++	unsigned char	category;
++	struct action_handler *ptable;
++	unsigned char	*frame_body;
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++
++	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++
++	category = frame_body[0];
++
++	for (i = 0; i < sizeof(OnAction_tbl) / sizeof(struct action_handler); i++) {
++		ptable = &OnAction_tbl[i];
++
++		if (category == ptable->num)
++			ptable->func(padapter, precv_frame);
++
++	}
++
++	return _SUCCESS;
++
++}
++
++unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame)
++{
++
++	/* RTW_INFO("rcvd mgt frame(%x, %x)\n", (get_frame_sub_type(pframe) >> 4), *(unsigned int *)GetAddr1Ptr(pframe)); */
++	return _SUCCESS;
++}
++
++struct xmit_frame *_alloc_mgtxmitframe(struct xmit_priv *pxmitpriv, bool once)
++{
++	struct xmit_frame *pmgntframe;
++	struct xmit_buf *pxmitbuf;
++
++	if (once)
++		pmgntframe = rtw_alloc_xmitframe_once(pxmitpriv);
++	else
++		pmgntframe = rtw_alloc_xmitframe_ext(pxmitpriv);
++
++	if (pmgntframe == NULL) {
++		RTW_INFO(FUNC_ADPT_FMT" alloc xmitframe fail, once:%d\n", FUNC_ADPT_ARG(pxmitpriv->adapter), once);
++		goto exit;
++	}
++
++	pxmitbuf = rtw_alloc_xmitbuf_ext(pxmitpriv);
++	if (pxmitbuf == NULL) {
++		RTW_INFO(FUNC_ADPT_FMT" alloc xmitbuf fail\n", FUNC_ADPT_ARG(pxmitpriv->adapter));
++		rtw_free_xmitframe(pxmitpriv, pmgntframe);
++		pmgntframe = NULL;
++		goto exit;
++	}
++
++	pmgntframe->frame_tag = MGNT_FRAMETAG;
++	pmgntframe->pxmitbuf = pxmitbuf;
++	pmgntframe->buf_addr = pxmitbuf->pbuf;
++	pxmitbuf->priv_data = pmgntframe;
++
++exit:
++	return pmgntframe;
++
++}
++
++inline struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv)
++{
++	return _alloc_mgtxmitframe(pxmitpriv, _FALSE);
++}
++
++inline struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv)
++{
++	return _alloc_mgtxmitframe(pxmitpriv, _TRUE);
++}
++
++
++/****************************************************************************
++
++Following are some TX fuctions for WiFi MLME
++
++*****************************************************************************/
++
++void update_mgnt_tx_rate(_adapter *padapter, u8 rate)
++{
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++
++	pmlmeext->tx_rate = rate;
++	/* RTW_INFO("%s(): rate = %x\n",__FUNCTION__, rate); */
++}
++
++
++void update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	u8	wireless_mode;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct xmit_priv		*pxmitpriv = &padapter->xmitpriv;
++	struct sta_info		*psta = NULL;
++	struct sta_priv		*pstapriv = &padapter->stapriv;
++
++	psta = rtw_get_stainfo(pstapriv, pattrib->ra);
++
++	pattrib->hdrlen = 24;
++	pattrib->nr_frags = 1;
++	pattrib->priority = 7;
++	pattrib->mac_id = RTW_DEFAULT_MGMT_MACID;
++	pattrib->qsel = QSLT_MGNT;
++
++	pattrib->pktlen = 0;
++
++	if (pmlmeext->tx_rate == IEEE80211_CCK_RATE_1MB)
++		wireless_mode = WIRELESS_11B;
++	else
++		wireless_mode = WIRELESS_11G;
++
++	pattrib->raid = rtw_get_mgntframe_raid(padapter, wireless_mode);
++#ifdef CONFIG_80211AC_VHT
++	if (pHalData->rf_type == RF_1T1R)
++		pattrib->raid = RATEID_IDX_VHT_1SS;
++	else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
++		pattrib->raid = RATEID_IDX_VHT_2SS;
++	else if (pHalData->rf_type == RF_3T3R)
++		pattrib->raid = RATEID_IDX_VHT_3SS;
++	else
++		pattrib->raid = RATEID_IDX_BGN_40M_1SS;
++#endif
++
++#ifdef CONFIG_80211AC_VHT
++	pattrib->rate = MGN_VHT1SS_MCS9;
++#else
++	pattrib->rate = MGN_MCS7;
++#endif
++
++	pattrib->encrypt = _NO_PRIVACY_;
++	pattrib->bswenc = _FALSE;
++
++	pattrib->qos_en = _FALSE;
++	pattrib->ht_en = 1;
++	pattrib->bwmode = CHANNEL_WIDTH_20;
++	pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++	pattrib->sgi = _FALSE;
++
++	pattrib->seqnum = pmlmeext->mgnt_seq;
++
++	pattrib->retry_ctrl = _TRUE;
++
++	pattrib->mbssid = 0;
++	pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no;
++
++}
++
++
++void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
++{
++	u8	wireless_mode;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct xmit_priv		*pxmitpriv = &padapter->xmitpriv;
++
++#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++#endif /* CONFIG_P2P_PS_NOA_USE_MACID_SLEEP */
++
++	/* _rtw_memset((u8 *)(pattrib), 0, sizeof(struct pkt_attrib)); */
++
++	pattrib->hdrlen = 24;
++	pattrib->nr_frags = 1;
++	pattrib->priority = 7;
++	pattrib->mac_id = RTW_DEFAULT_MGMT_MACID;
++	pattrib->qsel = QSLT_MGNT;
++
++#ifdef CONFIG_MCC_MODE
++	update_mcc_mgntframe_attrib(padapter, pattrib);
++#endif
++
++
++#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_buddy_check_fwstate(padapter, WIFI_ASOC_STATE))
++#endif /* CONFIG_CONCURRENT_MODE */
++		if (MLME_IS_GC(padapter)) {
++			if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) {
++				struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++				struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++				WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
++				struct sta_priv *pstapriv = &padapter->stapriv;
++				struct sta_info *psta;
++
++				psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
++				if (psta) {
++					/* use macid sleep during NoA, mgmt frame use ac queue & ap macid */
++					pattrib->mac_id = psta->cmn.mac_id;
++					pattrib->qsel = QSLT_VO;
++				} else {
++					if (pwdinfo->p2p_ps_state != P2P_PS_DISABLE)
++						RTW_ERR("%s , psta was NULL\n", __func__);
++				}
++			}
++		}
++#endif /* CONFIG_P2P_PS_NOA_USE_MACID_SLEEP */
++
++
++	pattrib->pktlen = 0;
++
++	if (IS_CCK_RATE(pmlmeext->tx_rate))
++		wireless_mode = WIRELESS_11B;
++	else
++		wireless_mode = WIRELESS_11G;
++	pattrib->raid =  rtw_get_mgntframe_raid(padapter, wireless_mode);
++	pattrib->rate = pmlmeext->tx_rate;
++
++	pattrib->encrypt = _NO_PRIVACY_;
++	pattrib->bswenc = _FALSE;
++
++	pattrib->qos_en = _FALSE;
++	pattrib->ht_en = _FALSE;
++	pattrib->bwmode = CHANNEL_WIDTH_20;
++	pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++	pattrib->sgi = _FALSE;
++
++	pattrib->seqnum = pmlmeext->mgnt_seq;
++
++	pattrib->retry_ctrl = _TRUE;
++
++	pattrib->mbssid = 0;
++	pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no;
++}
++
++void update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntframe)
++{
++	u8	*pframe;
++	struct pkt_attrib	*pattrib = &pmgntframe->attrib;
++#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY)
++	struct sta_info		*sta = NULL;
++#endif
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++
++	_rtw_memcpy(pattrib->ra, GetAddr1Ptr(pframe), ETH_ALEN);
++	_rtw_memcpy(pattrib->ta, get_addr2_ptr(pframe), ETH_ALEN);
++
++#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY)
++	sta = pattrib->psta;
++	if (!sta) {
++		sta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
++		pattrib->psta = sta;
++	}
++	#ifdef CONFIG_BEAMFORMING
++	if (sta)
++		update_attrib_txbf_info(padapter, pattrib, sta);
++	#endif
++#endif /* defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) */
++}
++
++void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe)
++{
++	if (RTW_CANNOT_RUN(padapter)) {
++		rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf);
++		rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe);
++		return;
++	}
++
++	rtw_hal_mgnt_xmit(padapter, pmgntframe);
++}
++
++s32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms)
++{
++	s32 ret = _FAIL;
++	_irqL irqL;
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	struct xmit_buf *pxmitbuf = pmgntframe->pxmitbuf;
++	struct submit_ctx sctx;
++
++	if (RTW_CANNOT_RUN(padapter)) {
++		rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf);
++		rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe);
++		return ret;
++	}
++
++	rtw_sctx_init(&sctx, timeout_ms);
++	pxmitbuf->sctx = &sctx;
++
++	ret = rtw_hal_mgnt_xmit(padapter, pmgntframe);
++
++	if (ret == _SUCCESS)
++		ret = rtw_sctx_wait(&sctx, __func__);
++
++	_enter_critical(&pxmitpriv->lock_sctx, &irqL);
++	pxmitbuf->sctx = NULL;
++	_exit_critical(&pxmitpriv->lock_sctx, &irqL);
++
++	return ret;
++}
++
++s32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms)
++{
++#ifdef CONFIG_XMIT_ACK
++	static u8 seq_no = 0;
++	s32 ret = _FAIL;
++	struct xmit_priv	*pxmitpriv = &(GET_PRIMARY_ADAPTER(padapter))->xmitpriv;
++
++	if (RTW_CANNOT_RUN(padapter)) {
++		rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf);
++		rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe);
++		return -1;
++	}
++
++	_enter_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL);
++	pxmitpriv->ack_tx = _TRUE;
++	pxmitpriv->seq_no = seq_no++;
++	pmgntframe->ack_report = 1;
++	rtw_sctx_init(&(pxmitpriv->ack_tx_ops), timeout_ms);
++	if (rtw_hal_mgnt_xmit(padapter, pmgntframe) == _SUCCESS)
++		ret = rtw_sctx_wait(&(pxmitpriv->ack_tx_ops), __func__);
++
++	pxmitpriv->ack_tx = _FALSE;
++	_exit_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL);
++
++	return ret;
++#else /* !CONFIG_XMIT_ACK */
++	dump_mgntframe(padapter, pmgntframe);
++	rtw_msleep_os(50);
++	return _SUCCESS;
++#endif /* !CONFIG_XMIT_ACK */
++}
++
++s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntframe)
++{
++	/* In this case, use 500 ms as the default wait_ack timeout */
++	return dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, 500);
++}
++
++
++int update_hidden_ssid(u8 *ies, u32 ies_len, u8 hidden_ssid_mode)
++{
++	u8 *ssid_ie;
++	sint ssid_len_ori;
++	int len_diff = 0;
++
++	ssid_ie = rtw_get_ie(ies,  WLAN_EID_SSID, &ssid_len_ori, ies_len);
++
++	/* RTW_INFO("%s hidden_ssid_mode:%u, ssid_ie:%p, ssid_len_ori:%d\n", __FUNCTION__, hidden_ssid_mode, ssid_ie, ssid_len_ori); */
++
++	if (ssid_ie && ssid_len_ori > 0) {
++		switch (hidden_ssid_mode) {
++		case 1: {
++			u8 *next_ie = ssid_ie + 2 + ssid_len_ori;
++			u32 remain_len = 0;
++
++			remain_len = ies_len - (next_ie - ies);
++
++			ssid_ie[1] = 0;
++			_rtw_memcpy(ssid_ie + 2, next_ie, remain_len);
++			len_diff -= ssid_len_ori;
++
++			break;
++		}
++		case 2:
++			_rtw_memset(&ssid_ie[2], 0, ssid_len_ori);
++			break;
++		default:
++			break;
++		}
++	}
++
++	return len_diff;
++}
++
++void issue_beacon(_adapter *padapter, int timeout_ms)
++{
++	struct xmit_frame	*pmgntframe;
++	struct pkt_attrib	*pattrib;
++	unsigned char	*pframe;
++	struct rtw_ieee80211_hdr *pwlanhdr;
++	unsigned short *fctrl;
++	unsigned int	rate_len;
++	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
++#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++	_irqL irqL;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
++	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++#ifdef CONFIG_P2P
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++#endif /* CONFIG_P2P */
++
++
++	/* RTW_INFO("%s\n", __FUNCTION__); */
++
++#ifdef CONFIG_BCN_ICF
++	pmgntframe = rtw_alloc_bcnxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++#else
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++#endif
++	{
++		RTW_INFO("%s, alloc mgnt frame fail\n", __FUNCTION__);
++		return;
++	}
++#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++	_enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
++#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++	pattrib->qsel = QSLT_BEACON;
++
++#if defined(CONFIG_CONCURRENT_MODE) && (!defined(CONFIG_SWTIMER_BASED_TXBCN))
++	if (padapter->hw_port == HW_PORT1)
++		pattrib->mbssid = 1;
++#endif
++#ifdef CONFIG_FW_HANDLE_TXBCN
++	if (padapter->vap_id != CONFIG_LIMITED_AP_NUM)
++		pattrib->mbssid = padapter->vap_id;
++#endif
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
++	/* pmlmeext->mgnt_seq++; */
++	set_frame_sub_type(pframe, WIFI_BEACON);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
++		/* RTW_INFO("ie len=%d\n", cur_network->IELength); */
++#ifdef CONFIG_P2P
++		/* for P2P : Primary Device Type & Device Name */
++		u32 wpsielen = 0, insert_len = 0;
++		u8 *wpsie = NULL;
++		wpsie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen);
++
++		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && wpsie && wpsielen > 0) {
++			uint wps_offset, remainder_ielen;
++			u8 *premainder_ie, *pframe_wscie;
++
++			wps_offset = (uint)(wpsie - cur_network->IEs);
++
++			premainder_ie = wpsie + wpsielen;
++
++			remainder_ielen = cur_network->IELength - wps_offset - wpsielen;
++
++#ifdef CONFIG_IOCTL_CFG80211
++			if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
++				if (pmlmepriv->wps_beacon_ie && pmlmepriv->wps_beacon_ie_len > 0) {
++					_rtw_memcpy(pframe, cur_network->IEs, wps_offset);
++					pframe += wps_offset;
++					pattrib->pktlen += wps_offset;
++
++					_rtw_memcpy(pframe, pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len);
++					pframe += pmlmepriv->wps_beacon_ie_len;
++					pattrib->pktlen += pmlmepriv->wps_beacon_ie_len;
++
++					/* copy remainder_ie to pframe */
++					_rtw_memcpy(pframe, premainder_ie, remainder_ielen);
++					pframe += remainder_ielen;
++					pattrib->pktlen += remainder_ielen;
++				} else {
++					_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
++					pframe += cur_network->IELength;
++					pattrib->pktlen += cur_network->IELength;
++				}
++			} else
++#endif /* CONFIG_IOCTL_CFG80211 */
++			{
++				pframe_wscie = pframe + wps_offset;
++				_rtw_memcpy(pframe, cur_network->IEs, wps_offset + wpsielen);
++				pframe += (wps_offset + wpsielen);
++				pattrib->pktlen += (wps_offset + wpsielen);
++
++				/* now pframe is end of wsc ie, insert Primary Device Type & Device Name */
++				/*	Primary Device Type */
++				/*	Type: */
++				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);
++				insert_len += 2;
++
++				/*	Length: */
++				*(u16 *)(pframe + insert_len) = cpu_to_be16(0x0008);
++				insert_len += 2;
++
++				/*	Value: */
++				/*	Category ID */
++				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
++				insert_len += 2;
++
++				/*	OUI */
++				*(u32 *)(pframe + insert_len) = cpu_to_be32(WPSOUI);
++				insert_len += 4;
++
++				/*	Sub Category ID */
++				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
++				insert_len += 2;
++
++
++				/*	Device Name */
++				/*	Type: */
++				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
++				insert_len += 2;
++
++				/*	Length: */
++				*(u16 *)(pframe + insert_len) = cpu_to_be16(pwdinfo->device_name_len);
++				insert_len += 2;
++
++				/*	Value: */
++				_rtw_memcpy(pframe + insert_len, pwdinfo->device_name, pwdinfo->device_name_len);
++				insert_len += pwdinfo->device_name_len;
++
++
++				/* update wsc ie length */
++				*(pframe_wscie + 1) = (wpsielen - 2) + insert_len;
++
++				/* pframe move to end */
++				pframe += insert_len;
++				pattrib->pktlen += insert_len;
++
++				/* copy remainder_ie to pframe */
++				_rtw_memcpy(pframe, premainder_ie, remainder_ielen);
++				pframe += remainder_ielen;
++				pattrib->pktlen += remainder_ielen;
++			}
++		} else
++#endif /* CONFIG_P2P */
++		{
++			int len_diff;
++			_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
++			len_diff = update_hidden_ssid(
++					   pframe + _BEACON_IE_OFFSET_
++				   , cur_network->IELength - _BEACON_IE_OFFSET_
++					   , pmlmeinfo->hidden_ssid_mode
++				   );
++			pframe += (cur_network->IELength + len_diff);
++			pattrib->pktlen += (cur_network->IELength + len_diff);
++		}
++
++		{
++			u8 *wps_ie;
++			uint wps_ielen;
++			u8 sr = 0;
++			wps_ie = rtw_get_wps_ie(pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_,
++				pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_, NULL, &wps_ielen);
++			if (wps_ie && wps_ielen > 0)
++				rtw_get_wps_attr_content(wps_ie,  wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);
++			if (sr != 0)
++				set_fwstate(pmlmepriv, WIFI_UNDER_WPS);
++			else
++				_clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS);
++		}
++
++#ifdef CONFIG_RTW_80211K
++		pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_,
++			sizeof(padapter->rmpriv.rm_en_cap_def),
++			padapter->rmpriv.rm_en_cap_def, &pattrib->pktlen);
++#endif
++
++#ifdef CONFIG_P2P
++		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++			u32 len;
++#ifdef CONFIG_IOCTL_CFG80211
++			if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
++				len = pmlmepriv->p2p_beacon_ie_len;
++				if (pmlmepriv->p2p_beacon_ie && len > 0)
++					_rtw_memcpy(pframe, pmlmepriv->p2p_beacon_ie, len);
++			} else
++#endif /* CONFIG_IOCTL_CFG80211 */
++			{
++				len = build_beacon_p2p_ie(pwdinfo, pframe);
++			}
++
++			pframe += len;
++			pattrib->pktlen += len;
++
++#ifdef CONFIG_MCC_MODE
++			pframe = rtw_hal_mcc_append_go_p2p_ie(padapter, pframe, &pattrib->pktlen);
++#endif /* CONFIG_MCC_MODE*/
++
++#ifdef CONFIG_WFD
++			len = rtw_append_beacon_wfd_ie(padapter, pframe);
++			pframe += len;
++			pattrib->pktlen += len;
++#endif
++		}
++#endif /* CONFIG_P2P */
++#ifdef CONFIG_RTW_REPEATER_SON
++		rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen);
++#endif
++#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
++		pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_BEACON_VENDOR_IE_BIT);
++#endif
++
++#ifdef CONFIG_RTL8812A 
++		pframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen );
++#endif/*CONFIG_RTL8812A*/
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++		if (padapter->tbtx_capability == _TRUE)
++			pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 8, REALTEK_TBTX_IE, &pattrib->pktlen);
++#endif
++
++		goto _issue_bcn;
++
++	}
++
++	/* below for ad-hoc mode */
++
++	/* timestamp will be inserted by hardware */
++	pframe += 8;
++	pattrib->pktlen += 8;
++
++	/* beacon interval: 2 bytes */
++
++	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
++
++	pframe += 2;
++	pattrib->pktlen += 2;
++
++	/* capability info: 2 bytes */
++
++	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
++
++	pframe += 2;
++	pattrib->pktlen += 2;
++
++	/* SSID */
++	pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen);
++
++	/* supported rates... */
++	rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
++	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pattrib->pktlen);
++
++	/* DS parameter set */
++	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen);
++
++	/* if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) */
++	{
++		u8 erpinfo = 0;
++		u32 ATIMWindow;
++		/* IBSS Parameter Set... */
++		/* ATIMWindow = cur->Configuration.ATIMWindow; */
++		ATIMWindow = 0;
++		pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen);
++
++		/* ERP IE */
++		pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen);
++	}
++
++
++	/* EXTERNDED SUPPORTED RATE */
++	if (rate_len > 8)
++		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen);
++
++
++	/* todo:HT for adhoc */
++
++_issue_bcn:
++
++#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++	pmlmepriv->update_bcn = _FALSE;
++
++	_exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
++#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
++
++	if ((pattrib->pktlen + TXDESC_SIZE) > MAX_BEACON_LEN) {
++		RTW_ERR("beacon frame too large ,len(%d,%d)\n",
++			(pattrib->pktlen + TXDESC_SIZE), MAX_BEACON_LEN);
++		rtw_warn_on(1);
++		return;
++	}
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	/* RTW_INFO("issue bcn_sz=%d\n", pattrib->last_txcmdsz); */
++	if (timeout_ms > 0)
++		dump_mgntframe_and_wait(padapter, pmgntframe, timeout_ms);
++	else
++		dump_mgntframe(padapter, pmgntframe);
++
++}
++
++void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq)
++{
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	unsigned char					*mac, *bssid;
++	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
++#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++	u8 *pwps_ie;
++	uint wps_ielen;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
++	unsigned int	rate_len;
++#ifdef CONFIG_P2P
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++#endif /* CONFIG_P2P */
++
++	/* RTW_INFO("%s\n", __FUNCTION__); */
++
++	if (da == NULL)
++		return;
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		return;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL) {
++		RTW_INFO("%s, alloc mgnt frame fail\n", __FUNCTION__);
++		return;
++	}
++
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	mac = adapter_mac_addr(padapter);
++	bssid = cur_network->MacAddress;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(fctrl, WIFI_PROBERSP);
++
++	pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = pattrib->hdrlen;
++	pframe += pattrib->hdrlen;
++
++
++	if (cur_network->IELength > MAX_IE_SZ)
++		return;
++
++#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++	if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
++		pwps_ie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wps_ielen);
++
++		/* inerset & update wps_probe_resp_ie */
++		if ((pmlmepriv->wps_probe_resp_ie != NULL) && pwps_ie && (wps_ielen > 0)) {
++			uint wps_offset, remainder_ielen;
++			u8 *premainder_ie;
++
++			wps_offset = (uint)(pwps_ie - cur_network->IEs);
++
++			premainder_ie = pwps_ie + wps_ielen;
++
++			remainder_ielen = cur_network->IELength - wps_offset - wps_ielen;
++
++			_rtw_memcpy(pframe, cur_network->IEs, wps_offset);
++			pframe += wps_offset;
++			pattrib->pktlen += wps_offset;
++
++			wps_ielen = (uint)pmlmepriv->wps_probe_resp_ie[1];/* to get ie data len */
++			if ((wps_offset + wps_ielen + 2) <= MAX_IE_SZ) {
++				_rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, wps_ielen + 2);
++				pframe += wps_ielen + 2;
++				pattrib->pktlen += wps_ielen + 2;
++			}
++
++			if ((wps_offset + wps_ielen + 2 + remainder_ielen) <= MAX_IE_SZ) {
++				_rtw_memcpy(pframe, premainder_ie, remainder_ielen);
++				pframe += remainder_ielen;
++				pattrib->pktlen += remainder_ielen;
++			}
++		} else {
++			_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
++			pframe += cur_network->IELength;
++			pattrib->pktlen += cur_network->IELength;
++		}
++
++		/* retrieve SSID IE from cur_network->Ssid */
++		{
++			u8 *ssid_ie;
++			sint ssid_ielen;
++			sint ssid_ielen_diff;
++			u8 buf[MAX_IE_SZ];
++			u8 *ies = pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr);
++
++			ssid_ie = rtw_get_ie(ies + _FIXED_IE_LENGTH_, _SSID_IE_, &ssid_ielen,
++				     (pframe - ies) - _FIXED_IE_LENGTH_);
++
++			ssid_ielen_diff = cur_network->Ssid.SsidLength - ssid_ielen;
++
++			if (ssid_ie &&  cur_network->Ssid.SsidLength) {
++				uint remainder_ielen;
++				u8 *remainder_ie;
++				remainder_ie = ssid_ie + 2;
++				remainder_ielen = (pframe - remainder_ie);
++
++				if (remainder_ielen > MAX_IE_SZ) {
++					RTW_WARN(FUNC_ADPT_FMT" remainder_ielen > MAX_IE_SZ\n", FUNC_ADPT_ARG(padapter));
++					remainder_ielen = MAX_IE_SZ;
++				}
++
++				_rtw_memcpy(buf, remainder_ie, remainder_ielen);
++				_rtw_memcpy(remainder_ie + ssid_ielen_diff, buf, remainder_ielen);
++				*(ssid_ie + 1) = cur_network->Ssid.SsidLength;
++				_rtw_memcpy(ssid_ie + 2, cur_network->Ssid.Ssid, cur_network->Ssid.SsidLength);
++
++				pframe += ssid_ielen_diff;
++				pattrib->pktlen += ssid_ielen_diff;
++			}
++		}
++#ifdef CONFIG_RTW_REPEATER_SON
++		rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen);
++#endif
++#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
++		pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_PROBERESP_VENDOR_IE_BIT);
++#endif
++	} else
++#endif
++	{
++
++		/* timestamp will be inserted by hardware */
++		pframe += 8;
++		pattrib->pktlen += 8;
++
++		/* beacon interval: 2 bytes */
++
++		_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
++
++		pframe += 2;
++		pattrib->pktlen += 2;
++
++		/* capability info: 2 bytes */
++
++		_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
++
++		pframe += 2;
++		pattrib->pktlen += 2;
++
++		/* below for ad-hoc mode */
++
++		/* SSID */
++		pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen);
++
++		/* supported rates... */
++		rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
++		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pattrib->pktlen);
++
++		/* DS parameter set */
++		pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen);
++
++		if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
++			u8 erpinfo = 0;
++			u32 ATIMWindow;
++			/* IBSS Parameter Set... */
++			/* ATIMWindow = cur->Configuration.ATIMWindow; */
++			ATIMWindow = 0;
++			pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen);
++
++			/* ERP IE */
++			pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen);
++		}
++
++
++		/* EXTERNDED SUPPORTED RATE */
++		if (rate_len > 8)
++			pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen);
++
++
++		/* todo:HT for adhoc */
++
++	}
++
++#ifdef CONFIG_RTW_80211K
++	pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_,
++		sizeof(padapter->rmpriv.rm_en_cap_def),
++		padapter->rmpriv.rm_en_cap_def, &pattrib->pktlen);
++#endif
++
++#ifdef CONFIG_P2P
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)
++	    /* IOT issue, When wifi_spec is not set, send probe_resp with P2P IE even if probe_req has no P2P IE */
++	    && (is_valid_p2p_probereq || !padapter->registrypriv.wifi_spec)) {
++		u32 len;
++#ifdef CONFIG_IOCTL_CFG80211
++		if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
++			/* if pwdinfo->role == P2P_ROLE_DEVICE will call issue_probersp_p2p() */
++			len = pmlmepriv->p2p_go_probe_resp_ie_len;
++			if (pmlmepriv->p2p_go_probe_resp_ie && len > 0)
++				_rtw_memcpy(pframe, pmlmepriv->p2p_go_probe_resp_ie, len);
++		} else
++#endif /* CONFIG_IOCTL_CFG80211 */
++		{
++			len = build_probe_resp_p2p_ie(pwdinfo, pframe);
++		}
++
++		pframe += len;
++		pattrib->pktlen += len;
++
++#ifdef CONFIG_MCC_MODE
++		pframe = rtw_hal_mcc_append_go_p2p_ie(padapter, pframe, &pattrib->pktlen);
++#endif /* CONFIG_MCC_MODE*/
++
++#ifdef CONFIG_WFD
++		len = rtw_append_probe_resp_wfd_ie(padapter, pframe);
++		pframe += len;
++		pattrib->pktlen += len;
++#endif
++	}
++#endif /* CONFIG_P2P */
++
++
++#ifdef CONFIG_AUTO_AP_MODE
++	{
++		struct sta_info	*psta;
++		struct sta_priv *pstapriv = &padapter->stapriv;
++
++		RTW_INFO("(%s)\n", __FUNCTION__);
++
++		/* check rc station */
++		psta = rtw_get_stainfo(pstapriv, da);
++		if (psta && psta->isrc && psta->pid > 0) {
++			u8 RC_OUI[4] = {0x00, 0xE0, 0x4C, 0x0A};
++			u8 RC_INFO[14] = {0};
++			/* EID[1] + EID_LEN[1] + RC_OUI[4] + MAC[6] + PairingID[2] + ChannelNum[2] */
++			u16 cu_ch = (u16)cur_network->Configuration.DSConfig;
++
++			RTW_INFO("%s, reply rc(pid=0x%x) device "MAC_FMT" in ch=%d\n", __FUNCTION__,
++				 psta->pid, MAC_ARG(psta->cmn.mac_addr), cu_ch);
++
++			/* append vendor specific ie */
++			_rtw_memcpy(RC_INFO, RC_OUI, sizeof(RC_OUI));
++			_rtw_memcpy(&RC_INFO[4], mac, ETH_ALEN);
++			_rtw_memcpy(&RC_INFO[10], (u8 *)&psta->pid, 2);
++			_rtw_memcpy(&RC_INFO[12], (u8 *)&cu_ch, 2);
++
++			pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, sizeof(RC_INFO), RC_INFO, &pattrib->pktlen);
++		}
++	}
++#endif /* CONFIG_AUTO_AP_MODE */
++
++#ifdef CONFIG_RTL8812A 
++	pframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen);
++#endif/*CONFIG_RTL8812A*/
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++
++	dump_mgntframe(padapter, pmgntframe);
++
++	return;
++
++}
++
++int _issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int wait_ack)
++{
++	int ret = _FAIL;
++	struct xmit_frame		*pmgntframe;
++	struct pkt_attrib		*pattrib;
++	unsigned char			*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short		*fctrl;
++	unsigned char			*mac;
++	unsigned char			bssrate[NumRates];
++	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	int	bssrate_len = 0;
++	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++#endif
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		goto exit;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++	if ((pwdev_priv->pno_mac_addr[0] != 0xFF)
++	    && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE)
++	    && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _FALSE))
++		mac = pwdev_priv->pno_mac_addr;
++	else
++#endif
++	mac = adapter_mac_addr(padapter);
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	if (da) {
++		/*	unicast probe request frame */
++		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);
++	} else {
++		/*	broadcast probe request frame */
++		_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN);
++	}
++
++	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
++
++#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++	if ((pwdev_priv->pno_mac_addr[0] != 0xFF)
++	    && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE)
++	    && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _FALSE)) {
++#ifdef CONFIG_RTW_DEBUG
++		RTW_DBG("%s pno_scan_seq_num: %d\n", __func__,
++			 pwdev_priv->pno_scan_seq_num);
++#endif
++		SetSeqNum(pwlanhdr, pwdev_priv->pno_scan_seq_num);
++		pattrib->seqnum = pwdev_priv->pno_scan_seq_num;
++		pattrib->qos_en = 1;
++		pwdev_priv->pno_scan_seq_num++;
++	} else
++#endif
++	{
++		SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++		pmlmeext->mgnt_seq++;
++	}
++	set_frame_sub_type(pframe, WIFI_PROBEREQ);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	if (pssid && !MLME_IS_MESH(padapter))
++		pframe = rtw_set_ie(pframe, _SSID_IE_, pssid->SsidLength, pssid->Ssid, &(pattrib->pktlen));
++	else
++		pframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &(pattrib->pktlen));
++
++	get_rate_set(padapter, bssrate, &bssrate_len);
++
++	if (bssrate_len > 8) {
++		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen));
++		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen));
++	} else
++		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));
++
++	if (ch)
++		pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, &ch, &pattrib->pktlen);
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(padapter)) {
++		if (pssid)
++			pframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, pssid->Ssid, pssid->SsidLength);
++		else
++			pframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, NULL, 0);
++	}
++#endif
++
++	if (append_wps) {
++		/* add wps_ie for wps2.0 */
++		if (pmlmepriv->wps_probe_req_ie_len > 0 && pmlmepriv->wps_probe_req_ie) {
++			_rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len);
++			pframe += pmlmepriv->wps_probe_req_ie_len;
++			pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len;
++			/* pmlmepriv->wps_probe_req_ie_len = 0 ; */ /* reset to zero */
++		}
++	}
++#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
++	pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_PROBEREQ_VENDOR_IE_BIT);
++#endif
++
++#ifdef CONFIG_RTL8812A 
++	pframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen );
++#endif/*CONFIG_RTL8812A*/
++
++
++#ifdef CONFIG_RTW_MBO
++	rtw_mbo_build_probe_req_ies(	padapter, &pframe, pattrib);
++#endif
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++
++	if (wait_ack)
++		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
++	else {
++		dump_mgntframe(padapter, pmgntframe);
++		ret = _SUCCESS;
++	}
++
++exit:
++	return ret;
++}
++
++inline void issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da)
++{
++	_issue_probereq(padapter, pssid, da, 0, 1, _FALSE);
++}
++
++/*
++ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
++ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
++ * try_cnt means the maximal TX count to try
++ */
++int issue_probereq_ex(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps,
++		      int try_cnt, int wait_ms)
++{
++	int ret = _FAIL;
++	int i = 0;
++	systime start = rtw_get_current_time();
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		goto exit;
++
++	do {
++		ret = _issue_probereq(padapter, pssid, da, ch, append_wps, wait_ms > 0 ? _TRUE : _FALSE);
++
++		i++;
++
++		if (RTW_CANNOT_RUN(padapter))
++			break;
++
++		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
++			rtw_msleep_os(wait_ms);
++
++	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
++
++	if (ret != _FAIL) {
++		ret = _SUCCESS;
++#ifndef DBG_XMIT_ACK
++		goto exit;
++#endif
++	}
++
++	if (try_cnt && wait_ms) {
++		if (da)
++			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
++				FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
++				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
++		else
++			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
++				FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
++				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
++	}
++exit:
++	return ret;
++}
++
++/* if psta == NULL, indiate we are station(client) now... */
++void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status)
++{
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	unsigned int					val32;
++	unsigned short				val16;
++	int use_shared_key = 0;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		return;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_AUTH);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++
++	if (psta) { /* for AP mode */
++#ifdef CONFIG_NATIVEAP_MLME
++
++		_rtw_memcpy(pwlanhdr->addr1, psta->cmn.mac_addr, ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
++
++
++		/* setting auth algo number */
++		val16 = (u16)psta->authalg;
++
++		if (status != _STATS_SUCCESSFUL_)
++			val16 = 0;
++
++		if (val16)	{
++			val16 = cpu_to_le16(val16);
++			use_shared_key = 1;
++		}
++
++		pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));
++
++		/* setting auth seq number */
++		val16 = (u16)psta->auth_seq;
++		val16 = cpu_to_le16(val16);
++		pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));
++
++		/* setting status code... */
++		val16 = status;
++		val16 = cpu_to_le16(val16);
++		pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen));
++
++		/* added challenging text... */
++		if ((psta->auth_seq == 2) && (psta->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1))
++			pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, psta->chg_txt, &(pattrib->pktlen));
++#endif
++	} else {
++		_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
++
++#ifdef CONFIG_RTW_80211R
++		if (rtw_ft_roam(padapter)) {
++			/* 2: 802.11R FTAA */
++			val16 = cpu_to_le16(2);
++		} else
++#endif
++		{
++			/* setting auth algo number */
++			val16 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) ? 1 : 0;	/* 0:OPEN System, 1:Shared key */
++			if (val16) {
++				val16 = cpu_to_le16(val16);
++				use_shared_key = 1;
++			}
++		}
++
++		/* RTW_INFO("%s auth_algo= %s auth_seq=%d\n",__FUNCTION__,(pmlmeinfo->auth_algo==0)?"OPEN":"SHARED",pmlmeinfo->auth_seq); */
++
++		/* setting IV for auth seq #3 */
++		if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) {
++			/* RTW_INFO("==> iv(%d),key_index(%d)\n",pmlmeinfo->iv,pmlmeinfo->key_index); */
++			val32 = ((pmlmeinfo->iv++) | (pmlmeinfo->key_index << 30));
++			val32 = cpu_to_le32(val32);
++			pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *)&val32, &(pattrib->pktlen));
++
++			pattrib->iv_len = 4;
++		}
++
++		pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));
++
++		/* setting auth seq number */
++		val16 = pmlmeinfo->auth_seq;
++		val16 = cpu_to_le16(val16);
++		pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));
++
++
++		/* setting status code... */
++		val16 = status;
++		val16 = cpu_to_le16(val16);
++		pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen));
++
++#ifdef CONFIG_RTW_80211R
++		rtw_ft_build_auth_req_ies(padapter, pattrib, &pframe);
++#endif
++
++		/* then checking to see if sending challenging text... */
++		if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) {
++			pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, pmlmeinfo->chg_txt, &(pattrib->pktlen));
++
++			SetPrivacy(fctrl);
++
++			pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++			pattrib->encrypt = _WEP40_;
++
++			pattrib->icv_len = 4;
++
++			pattrib->pktlen += pattrib->icv_len;
++
++		}
++
++	}
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	rtw_wep_encrypt(padapter, (u8 *)pmgntframe);
++	RTW_INFO("%s\n", __FUNCTION__);
++	dump_mgntframe(padapter, pmgntframe);
++
++	return;
++}
++
++
++void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type)
++{
++#ifdef CONFIG_AP_MODE
++	struct xmit_frame	*pmgntframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	struct pkt_attrib *pattrib;
++	unsigned char	*pbuf, *pframe;
++	unsigned short val, ie_status;
++	unsigned short *fctrl;
++	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
++	u8 *ie = pnetwork->IEs;
++#ifdef CONFIG_P2P
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++#ifdef CONFIG_WFD
++	u32					wfdielen = 0;
++#endif
++
++#endif /* CONFIG_P2P */
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		return;
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->cmn.mac_addr, ETH_ALEN);
++	_rtw_memcpy((void *)get_addr2_ptr(pwlanhdr), adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	if ((pkt_type == WIFI_ASSOCRSP) || (pkt_type == WIFI_REASSOCRSP))
++		set_frame_sub_type(pwlanhdr, pkt_type);
++	else
++		return;
++
++	pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen += pattrib->hdrlen;
++	pframe += pattrib->hdrlen;
++
++	/* capability */
++	val = *(unsigned short *)rtw_get_capability_from_ie(ie);
++
++	pframe = rtw_set_fixed_ie(pframe, _CAPABILITY_ , (unsigned char *)&val, &(pattrib->pktlen));
++
++	ie_status = cpu_to_le16(status);
++	pframe = rtw_set_fixed_ie(pframe , _STATUS_CODE_ , (unsigned char *)&ie_status, &(pattrib->pktlen));
++
++	val = cpu_to_le16(pstat->cmn.aid | BIT(14) | BIT(15));
++	pframe = rtw_set_fixed_ie(pframe, _ASOC_ID_ , (unsigned char *)&val, &(pattrib->pktlen));
++
++	if (pstat->bssratelen <= 8)
++		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, pstat->bssratelen, pstat->bssrateset, &(pattrib->pktlen));
++	else {
++		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pstat->bssrateset, &(pattrib->pktlen));
++		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (pstat->bssratelen - 8), pstat->bssrateset + 8, &(pattrib->pktlen));
++	}
++
++#ifdef CONFIG_IEEE80211W
++	if (status == _STATS_REFUSED_TEMPORARILY_) {
++		u8 timeout_itvl[5];
++		u32 timeout_interval = 3000;
++		/* Association Comeback time */
++		timeout_itvl[0] = 0x03;
++		timeout_interval = cpu_to_le32(timeout_interval);
++		_rtw_memcpy(timeout_itvl + 1, &timeout_interval, 4);
++		pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen));
++	}
++#endif /* CONFIG_IEEE80211W */
++
++#ifdef CONFIG_80211N_HT
++	if ((pstat->flags & WLAN_STA_HT) && (pmlmepriv->htpriv.ht_option)) {
++		uint ie_len = 0;
++
++		/* FILL HT CAP INFO IE */
++		/* p = hostapd_eid_ht_capabilities_info(hapd, p); */
++		pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
++		if (pbuf && ie_len > 0) {
++			_rtw_memcpy(pframe, pbuf, ie_len + 2);
++			pframe += (ie_len + 2);
++			pattrib->pktlen += (ie_len + 2);
++		}
++
++		/* FILL HT ADD INFO IE */
++		/* p = hostapd_eid_ht_operation(hapd, p); */
++		pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
++		if (pbuf && ie_len > 0) {
++			_rtw_memcpy(pframe, pbuf, ie_len + 2);
++			pframe += (ie_len + 2);
++			pattrib->pktlen += (ie_len + 2);
++		}
++
++	}
++#endif
++
++	/*adding EXT_CAPAB_IE */
++	if (pmlmepriv->ext_capab_ie_len > 0) {
++		uint ie_len = 0;
++
++		pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_CAP_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
++		if (pbuf && ie_len > 0) {
++			_rtw_memcpy(pframe, pbuf, ie_len + 2);
++			pframe += (ie_len + 2);
++			pattrib->pktlen += (ie_len + 2);
++		}
++	}
++
++#ifdef CONFIG_80211AC_VHT
++	if ((pstat->flags & WLAN_STA_VHT) && (pmlmepriv->vhtpriv.vht_option)
++	    && (pstat->wpa_pairwise_cipher != WPA_CIPHER_TKIP)
++	    && (pstat->wpa2_pairwise_cipher != WPA_CIPHER_TKIP)) {
++		u32 ie_len = 0;
++
++		/* FILL VHT CAP IE */
++		pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
++		if (pbuf && ie_len > 0) {
++			_rtw_memcpy(pframe, pbuf, ie_len + 2);
++			pframe += (ie_len + 2);
++			pattrib->pktlen += (ie_len + 2);
++		}
++
++		/* FILL VHT OPERATION IE */
++		pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTOperation, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
++		if (pbuf && ie_len > 0) {
++			_rtw_memcpy(pframe, pbuf, ie_len + 2);
++			pframe += (ie_len + 2);
++			pattrib->pktlen += (ie_len + 2);
++		}
++	}
++#endif /* CONFIG_80211AC_VHT */
++
++	/* FILL WMM IE */
++	if ((pstat->flags & WLAN_STA_WME) && (pmlmepriv->qospriv.qos_option)) {
++		uint ie_len = 0;
++		unsigned char WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01};
++
++		for (pbuf = ie + _BEACON_IE_OFFSET_; ; pbuf += (ie_len + 2)) {
++			pbuf = rtw_get_ie(pbuf, _VENDOR_SPECIFIC_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2)));
++			if (pbuf && _rtw_memcmp(pbuf + 2, WMM_PARA_IE, 6)) {
++				_rtw_memcpy(pframe, pbuf, ie_len + 2);
++				pframe += (ie_len + 2);
++				pattrib->pktlen += (ie_len + 2);
++
++				break;
++			}
++
++			if ((pbuf == NULL) || (ie_len == 0))
++				break;
++		}
++
++	}
++
++
++	if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK)
++		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen));
++
++	/* add WPS IE ie for wps 2.0 */
++	if (pmlmepriv->wps_assoc_resp_ie && pmlmepriv->wps_assoc_resp_ie_len > 0) {
++		_rtw_memcpy(pframe, pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len);
++
++		pframe += pmlmepriv->wps_assoc_resp_ie_len;
++		pattrib->pktlen += pmlmepriv->wps_assoc_resp_ie_len;
++	}
++
++#ifdef CONFIG_P2P
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && (pstat->is_p2p_device == _TRUE)) {
++		u32 len;
++
++		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) {
++			len = 0;
++			if (pmlmepriv->p2p_assoc_resp_ie && pmlmepriv->p2p_assoc_resp_ie_len > 0) {
++				len = pmlmepriv->p2p_assoc_resp_ie_len;
++				_rtw_memcpy(pframe, pmlmepriv->p2p_assoc_resp_ie, len);
++			}
++		} else
++			len = build_assoc_resp_p2p_ie(pwdinfo, pframe, pstat->p2p_status_code);
++		pframe += len;
++		pattrib->pktlen += len;
++	}
++
++#ifdef CONFIG_WFD
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++		wfdielen = rtw_append_assoc_resp_wfd_ie(padapter, pframe);
++		pframe += wfdielen;
++		pattrib->pktlen += wfdielen;
++	}
++#endif
++
++#endif /* CONFIG_P2P */
++
++#ifdef CONFIG_RTW_MULTI_AP
++	if (padapter->multi_ap && (pstat->flags & WLAN_STA_MULTI_AP))
++		pframe = rtw_set_multi_ap_ie_ext(pframe, &pattrib->pktlen, padapter->multi_ap);
++#endif
++
++#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
++	pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_ASSOCRESP_VENDOR_IE_BIT);
++#endif
++
++#ifdef CONFIG_RTL8812A 
++	pframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen );
++#endif/*CONFIG_RTL8812A*/
++
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	if (padapter->tbtx_capability == _TRUE)
++		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 8, REALTEK_TBTX_IE, &pattrib->pktlen);
++#endif
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(padapter, pmgntframe);
++
++#endif
++}
++
++static u32 rtw_append_assoc_req_owe_ie(_adapter *adapter, u8 *pbuf)
++{
++	struct security_priv *sec = &adapter->securitypriv;
++	u32 len = 0;
++
++	if (sec == NULL)
++		goto exit;
++
++	if (sec->owe_ie && sec->owe_ie_len > 0) {
++		len = sec->owe_ie_len;
++		_rtw_memcpy(pbuf, sec->owe_ie, len);
++	}
++
++exit:
++	return len;
++}
++
++void _issue_assocreq(_adapter *padapter, u8 is_reassoc)
++{
++	int ret = _FAIL;
++	struct xmit_frame				*pmgntframe;
++	struct pkt_attrib				*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr			*pwlanhdr;
++	unsigned short				*fctrl;
++	unsigned short				val16;
++	unsigned int					i, j, index = 0;
++	unsigned char					bssrate[NumRates], sta_bssrate[NumRates];
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	int	bssrate_len = 0, sta_bssrate_len = 0;
++	u8	vs_ie_length = 0;
++#ifdef CONFIG_P2P
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++	u8					p2pie[255] = { 0x00 };
++	u16					p2pielen = 0;
++#ifdef CONFIG_WFD
++	u32					wfdielen = 0;
++#endif
++#endif /* CONFIG_P2P */
++
++#if CONFIG_DFS
++	u16	cap;
++#endif
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		goto exit;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	if (is_reassoc == _TRUE)
++		set_frame_sub_type(pframe, WIFI_REASSOCREQ);
++	else
++		set_frame_sub_type(pframe, WIFI_ASSOCREQ);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	/* caps */
++
++#if CONFIG_DFS
++	_rtw_memcpy(&cap, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2);
++	cap |= cap_SpecMgmt;
++	_rtw_memcpy(pframe, &cap, 2);
++#else
++	_rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2);
++#endif
++
++	pframe += 2;
++	pattrib->pktlen += 2;
++
++	/* listen interval */
++	/* todo: listen interval for power saving */
++	val16 = cpu_to_le16(3);
++	_rtw_memcpy(pframe , (unsigned char *)&val16, 2);
++	pframe += 2;
++	pattrib->pktlen += 2;
++
++	/*Construct Current AP Field for Reassoc-Req only*/
++	if (is_reassoc == _TRUE) {
++		_rtw_memcpy(pframe, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++		pframe += ETH_ALEN;
++		pattrib->pktlen += ETH_ALEN;
++	}
++
++	/* SSID */
++	pframe = rtw_set_ie(pframe, _SSID_IE_,  pmlmeinfo->network.Ssid.SsidLength, pmlmeinfo->network.Ssid.Ssid, &(pattrib->pktlen));
++
++#if CONFIG_IEEE80211_BAND_5GHZ && CONFIG_DFS
++	/* Dot H */
++	if (pmlmeext->cur_channel > 14) {
++		struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++		u8 pow_cap_ele[2] = { 0x00 };
++		u8 sup_ch[30 * 2] = {0x00 }, sup_ch_idx = 0, idx_5g = 2;	/* For supported channel */
++
++		pow_cap_ele[0] = 13;	/* Minimum transmit power capability */
++		pow_cap_ele[1] = 21;	/* Maximum transmit power capability */
++		pframe = rtw_set_ie(pframe, EID_PowerCap, 2, pow_cap_ele, &(pattrib->pktlen));
++
++		/* supported channels */
++		while (sup_ch_idx < rfctl->max_chan_nums && rfctl->channel_set[sup_ch_idx].ChannelNum != 0) {
++			if (rfctl->channel_set[sup_ch_idx].ChannelNum <= 14) {
++				/* TODO: fix 2.4G supported channel when channel doesn't start from 1 and continuous */
++				sup_ch[0] = 1;	/* First channel number */
++				sup_ch[1] = rfctl->channel_set[sup_ch_idx].ChannelNum;	/* Number of channel */
++			} else {
++				sup_ch[idx_5g++] = rfctl->channel_set[sup_ch_idx].ChannelNum;
++				sup_ch[idx_5g++] = 1;
++			}
++			sup_ch_idx++;
++		}
++		pframe = rtw_set_ie(pframe, EID_SupportedChannels, idx_5g, sup_ch, &(pattrib->pktlen));
++	}
++#endif /* CONFIG_IEEE80211_BAND_5GHZ && CONFIG_DFS */
++
++	/* supported rate & extended supported rate */
++
++#if 1	/* Check if the AP's supported rates are also supported by STA. */
++	get_rate_set(padapter, sta_bssrate, &sta_bssrate_len);
++	/* RTW_INFO("sta_bssrate_len=%d\n", sta_bssrate_len); */
++
++	if (pmlmeext->cur_channel == 14) /* for JAPAN, channel 14 can only uses B Mode(CCK) */
++		sta_bssrate_len = 4;
++
++
++	/* for (i = 0; i < sta_bssrate_len; i++) { */
++	/*	RTW_INFO("sta_bssrate[%d]=%02X\n", i, sta_bssrate[i]); */
++	/* } */
++
++	for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
++		if (pmlmeinfo->network.SupportedRates[i] == 0)
++			break;
++		RTW_INFO("network.SupportedRates[%d]=%02X\n", i, pmlmeinfo->network.SupportedRates[i]);
++	}
++
++
++	for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
++		if (pmlmeinfo->network.SupportedRates[i] == 0)
++			break;
++
++
++		/* Check if the AP's supported rates are also supported by STA. */
++		for (j = 0; j < sta_bssrate_len; j++) {
++			/* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */
++			if ((pmlmeinfo->network.SupportedRates[i] | IEEE80211_BASIC_RATE_MASK)
++			    == (sta_bssrate[j] | IEEE80211_BASIC_RATE_MASK)) {
++				/* RTW_INFO("match i = %d, j=%d\n", i, j); */
++				break;
++			} else {
++				/* RTW_INFO("not match: %02X != %02X\n", (pmlmeinfo->network.SupportedRates[i]|IEEE80211_BASIC_RATE_MASK), (sta_bssrate[j]|IEEE80211_BASIC_RATE_MASK)); */
++			}
++		}
++
++		if (j == sta_bssrate_len) {
++			/* the rate is not supported by STA */
++			RTW_INFO("%s(): the rate[%d]=%02X is not supported by STA!\n", __FUNCTION__, i, pmlmeinfo->network.SupportedRates[i]);
++		} else {
++			/* the rate is supported by STA */
++			bssrate[index++] = pmlmeinfo->network.SupportedRates[i];
++		}
++	}
++
++	bssrate_len = index;
++	RTW_INFO("bssrate_len = %d\n", bssrate_len);
++
++#else	/* Check if the AP's supported rates are also supported by STA. */
++#if 0
++	get_rate_set(padapter, bssrate, &bssrate_len);
++#else
++	for (bssrate_len = 0; bssrate_len < NumRates; bssrate_len++) {
++		if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0)
++			break;
++
++		if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0x2C) /* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */
++			break;
++
++		bssrate[bssrate_len] = pmlmeinfo->network.SupportedRates[bssrate_len];
++	}
++#endif
++#endif /* Check if the AP's supported rates are also supported by STA. */
++
++	if ((bssrate_len == 0) && (pmlmeinfo->network.SupportedRates[0] != 0)) {
++		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++		rtw_free_xmitframe(pxmitpriv, pmgntframe);
++		goto exit; /* don't connect to AP if no joint supported rate */
++	}
++
++
++	if (bssrate_len > 8) {
++		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen));
++		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen));
++	} else if (bssrate_len > 0)
++		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));
++	else
++		RTW_INFO("%s: Connect to AP without 11b and 11g data rate!\n", __FUNCTION__);
++
++#ifdef CONFIG_RTW_MBO
++	rtw_mbo_build_assoc_req_ies(padapter, &pframe, pattrib);
++#endif
++#ifdef CONFIG_RTW_80211R
++	rtw_ft_build_assoc_req_ies(padapter, is_reassoc, pattrib, &pframe);
++#endif
++#ifdef CONFIG_RTW_80211K
++	if (pmlmeinfo->network.PhyInfo.rm_en_cap[0] /* RM Enabled Capabilities */
++		| pmlmeinfo->network.PhyInfo.rm_en_cap[1]
++		| pmlmeinfo->network.PhyInfo.rm_en_cap[2]
++		| pmlmeinfo->network.PhyInfo.rm_en_cap[3]
++		| pmlmeinfo->network.PhyInfo.rm_en_cap[4])
++		pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_, 5,
++				(u8 *)padapter->rmpriv.rm_en_cap_def, &(pattrib->pktlen));
++#endif /* CONFIG_RTW_80211K */
++
++	/* vendor specific IE, such as WPA, WMM, WPS */
++	for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) {
++		pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i);
++
++		switch (pIE->ElementID) {
++		case _VENDOR_SPECIFIC_IE_:
++			if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) ||
++			    (_rtw_memcmp(pIE->data, WMM_OUI, 4)) ||
++			    (_rtw_memcmp(pIE->data, WPS_OUI, 4))) {
++				vs_ie_length = pIE->Length;
++				if ((!padapter->registrypriv.wifi_spec) && (_rtw_memcmp(pIE->data, WPS_OUI, 4))) {
++					/* Commented by Kurt 20110629 */
++					/* In some older APs, WPS handshake */
++					/* would be fail if we append vender extensions informations to AP */
++
++					vs_ie_length = 14;
++				}
++
++				pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, vs_ie_length, pIE->data, &(pattrib->pktlen));
++			}
++			break;
++
++		case EID_WPA2:
++#ifdef CONFIG_RTW_80211R
++			if ((is_reassoc) && (rtw_ft_roam(padapter))) {
++				rtw_ft_update_rsnie(padapter, _TRUE, pattrib, &pframe);
++			} else
++#endif
++			{
++#ifdef CONFIG_IOCTL_CFG80211
++				if (rtw_sec_chk_auth_alg(padapter, WLAN_AUTH_OPEN) &&
++					rtw_sec_chk_auth_type(padapter, MLME_AUTHTYPE_SAE)) {
++					s32 entry = rtw_cached_pmkid(padapter, pmlmepriv->assoc_bssid);
++
++					rtw_rsn_sync_pmkid(padapter, (u8 *)pIE, (pIE->Length + 2), entry);
++				}
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++				pframe = rtw_set_ie(pframe, EID_WPA2, pIE->Length, pIE->data, &(pattrib->pktlen));
++			}
++			break;
++#ifdef CONFIG_80211N_HT
++		case EID_HTCapability:
++			if (padapter->mlmepriv.htpriv.ht_option == _TRUE) {
++				if (!(is_ap_in_tkip(padapter))) {
++					_rtw_memcpy(&(pmlmeinfo->HT_caps), pIE->data, sizeof(struct HT_caps_element));
++
++					pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = cpu_to_le16(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info);
++
++					pframe = rtw_set_ie(pframe, EID_HTCapability, pIE->Length , (u8 *)(&(pmlmeinfo->HT_caps)), &(pattrib->pktlen));
++				}
++			}
++			break;
++
++		case EID_EXTCapability:
++			if (padapter->mlmepriv.htpriv.ht_option == _TRUE)
++				pframe = rtw_set_ie(pframe, EID_EXTCapability, pIE->Length, pIE->data, &(pattrib->pktlen));
++			break;
++#endif /* CONFIG_80211N_HT */
++#ifdef CONFIG_80211AC_VHT
++		case EID_VHTCapability:
++			if (padapter->mlmepriv.vhtpriv.vht_option == _TRUE)
++				pframe = rtw_set_ie(pframe, EID_VHTCapability, pIE->Length, pIE->data, &(pattrib->pktlen));
++			break;
++
++		case EID_OpModeNotification:
++			if (padapter->mlmepriv.vhtpriv.vht_option == _TRUE)
++				pframe = rtw_set_ie(pframe, EID_OpModeNotification, pIE->Length, pIE->data, &(pattrib->pktlen));
++			break;
++#endif /* CONFIG_80211AC_VHT */
++		default:
++			break;
++		}
++
++		i += (pIE->Length + 2);
++	}
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	if (padapter->tbtx_capability == _TRUE)
++		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 8 , REALTEK_TBTX_IE, &(pattrib->pktlen));
++#endif
++
++	if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK)
++		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen));
++
++
++#ifdef CONFIG_WAPI_SUPPORT
++	rtw_build_assoc_req_wapi_ie(padapter, pframe, pattrib);
++#endif
++
++
++#ifdef CONFIG_P2P
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
++		if (pmlmepriv->p2p_assoc_req_ie && pmlmepriv->p2p_assoc_req_ie_len > 0) {
++			_rtw_memcpy(pframe, pmlmepriv->p2p_assoc_req_ie, pmlmepriv->p2p_assoc_req_ie_len);
++			pframe += pmlmepriv->p2p_assoc_req_ie_len;
++			pattrib->pktlen += pmlmepriv->p2p_assoc_req_ie_len;
++		}
++	} else
++#endif /* CONFIG_IOCTL_CFG80211 */
++	{
++		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) {
++			/*	Should add the P2P IE in the association request frame.	 */
++			/*	P2P OUI */
++
++			p2pielen = 0;
++			p2pie[p2pielen++] = 0x50;
++			p2pie[p2pielen++] = 0x6F;
++			p2pie[p2pielen++] = 0x9A;
++			p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
++
++			/*	Commented by Albert 20101109 */
++			/*	According to the P2P Specification, the association request frame should contain 3 P2P attributes */
++			/*	1. P2P Capability */
++			/*	2. Extended Listen Timing */
++			/*	3. Device Info */
++			/*	Commented by Albert 20110516 */
++			/*	4. P2P Interface */
++
++			/*	P2P Capability */
++			/*	Type: */
++			p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
++
++			/*	Length: */
++			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
++			p2pielen += 2;
++
++			/*	Value: */
++			/*	Device Capability Bitmap, 1 byte */
++			p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
++
++			/*	Group Capability Bitmap, 1 byte */
++			if (pwdinfo->persistent_supported)
++				p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;
++			else
++				p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT;
++
++			/*	Extended Listen Timing */
++			/*	Type: */
++			p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING;
++
++			/*	Length: */
++			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004);
++			p2pielen += 2;
++
++			/*	Value: */
++			/*	Availability Period */
++			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
++			p2pielen += 2;
++
++			/*	Availability Interval */
++			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
++			p2pielen += 2;
++
++			/*	Device Info */
++			/*	Type: */
++			p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
++
++			/*	Length: */
++			/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
++			/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
++			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);
++			p2pielen += 2;
++
++			/*	Value: */
++			/*	P2P Device Address */
++			_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
++			p2pielen += ETH_ALEN;
++
++			/*	Config Method */
++			/*	This field should be big endian. Noted by P2P specification. */
++			if ((pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN) ||
++			    (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN))
++				*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_DISPLAY);
++			else
++				*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_PBC);
++
++			p2pielen += 2;
++
++			/*	Primary Device Type */
++			/*	Category ID */
++			*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
++			p2pielen += 2;
++
++			/*	OUI */
++			*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);
++			p2pielen += 4;
++
++			/*	Sub Category ID */
++			*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
++			p2pielen += 2;
++
++			/*	Number of Secondary Device Types */
++			p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
++
++			/*	Device Name */
++			/*	Type: */
++			*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
++			p2pielen += 2;
++
++			/*	Length: */
++			*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);
++			p2pielen += 2;
++
++			/*	Value: */
++			_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len);
++			p2pielen += pwdinfo->device_name_len;
++
++			/*	P2P Interface */
++			/*	Type: */
++			p2pie[p2pielen++] = P2P_ATTR_INTERFACE;
++
++			/*	Length: */
++			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x000D);
++			p2pielen += 2;
++
++			/*	Value: */
++			_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN);	/*	P2P Device Address */
++			p2pielen += ETH_ALEN;
++
++			p2pie[p2pielen++] = 1;	/*	P2P Interface Address Count */
++
++			_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN);	/*	P2P Interface Address List */
++			p2pielen += ETH_ALEN;
++
++			pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
++		}
++	}
++
++#ifdef CONFIG_WFD
++	wfdielen = rtw_append_assoc_req_wfd_ie(padapter, pframe);
++	pframe += wfdielen;
++	pattrib->pktlen += wfdielen;
++#endif
++#endif /* CONFIG_P2P */
++
++#ifdef CONFIG_RTW_MULTI_AP
++	if (padapter->multi_ap)
++		pframe = rtw_set_multi_ap_ie_ext(pframe, &pattrib->pktlen, padapter->multi_ap);
++#endif
++
++	/* OWE */
++	{
++	u32 owe_ie_len;
++	
++	owe_ie_len = rtw_append_assoc_req_owe_ie(padapter, pframe);
++	pframe += owe_ie_len;
++	pattrib->pktlen += owe_ie_len;
++	}
++
++#ifdef CONFIG_RTW_REPEATER_SON
++	rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen);
++#endif
++#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
++	pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_ASSOCREQ_VENDOR_IE_BIT);
++#endif
++
++#ifdef CONFIG_RTL8812A 
++	pframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen );
++#endif/*CONFIG_RTL8812A*/
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++	dump_mgntframe(padapter, pmgntframe);
++
++	ret = _SUCCESS;
++
++exit:
++	if (ret == _SUCCESS) {
++		rtw_buf_update(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len, (u8 *)pwlanhdr, pattrib->pktlen);
++	#ifdef CONFIG_RTW_WNM
++		if (is_reassoc == _TRUE)
++			rtw_wnm_update_reassoc_req_ie(padapter);
++	#endif
++	} else
++		rtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len);
++
++	return;
++}
++
++void issue_assocreq(_adapter *padapter)
++{
++	_issue_assocreq(padapter, _FALSE);
++}
++
++void issue_reassocreq(_adapter *padapter)
++{
++	_issue_assocreq(padapter, _TRUE);
++}
++
++/* when wait_ack is ture, this function shoule be called at process context */
++static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ack)
++{
++	int ret = _FAIL;
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	struct xmit_priv	*pxmitpriv;
++	struct mlme_ext_priv	*pmlmeext;
++	struct mlme_ext_info	*pmlmeinfo;
++	u8 a4_shift;
++
++	/* RTW_INFO("%s:%d\n", __FUNCTION__, power_mode); */
++
++	if (!padapter)
++		goto exit;
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		goto exit;
++
++	pxmitpriv = &(padapter->xmitpriv);
++	pmlmeext = &(padapter->mlmeextpriv);
++	pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++	pattrib->retry_ctrl = _FALSE;
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	if (MLME_IS_AP(padapter))
++		SetFrDs(fctrl);
++	else if (MLME_IS_STA(padapter))
++		SetToDs(fctrl);
++	else if (MLME_IS_MESH(padapter)) {
++		SetToDs(fctrl);
++		SetFrDs(fctrl);
++	}
++
++	if (power_mode)
++		SetPwrMgt(fctrl);
++
++	if (get_tofr_ds(fctrl) == 3) {
++		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN);
++		a4_shift = ETH_ALEN;
++		pattrib->hdrlen += ETH_ALEN;
++	} else {
++		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++		a4_shift = 0;
++	}
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_DATA_NULL);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift;
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift;
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	if (wait_ack)
++		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
++	else {
++		dump_mgntframe(padapter, pmgntframe);
++		ret = _SUCCESS;
++	}
++
++exit:
++	return ret;
++}
++
++/*
++ * When wait_ms > 0, this function should be called at process context
++ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
++ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
++ * try_cnt means the maximal TX count to try
++ * da == NULL for station mode
++ */
++int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms)
++{
++	int ret = _FAIL;
++	int i = 0;
++	systime start = rtw_get_current_time();
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		goto exit;
++
++	/* da == NULL, assum it's null data for sta to ap */
++	if (da == NULL)
++		da = get_my_bssid(&(pmlmeinfo->network));
++
++	do {
++		ret = _issue_nulldata(padapter, da, power_mode, wait_ms > 0 ? _TRUE : _FALSE);
++
++		i++;
++
++		if (RTW_CANNOT_RUN(padapter))
++			break;
++
++		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
++			rtw_msleep_os(wait_ms);
++
++	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
++
++	if (ret != _FAIL) {
++		ret = _SUCCESS;
++#ifndef DBG_XMIT_ACK
++		goto exit;
++#endif
++	}
++
++	if (try_cnt && wait_ms) {
++		if (da)
++			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
++				FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
++				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
++		else
++			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
++				FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
++				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
++	}
++exit:
++	return ret;
++}
++
++/* when wait_ack is ture, this function shoule be called at process context */
++static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int wait_ack)
++{
++	int ret = _FAIL;
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl, *qc;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8 a4_shift;
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		goto exit;
++
++	/* RTW_INFO("%s\n", __FUNCTION__); */
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	pattrib->hdrlen += 2;
++	pattrib->qos_en = _TRUE;
++	pattrib->eosp = 1;
++	pattrib->ack_policy = 0;
++	pattrib->mdata = 0;
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	if (MLME_IS_AP(padapter))
++		SetFrDs(fctrl);
++	else if (MLME_IS_STA(padapter))
++		SetToDs(fctrl);
++	else if (MLME_IS_MESH(padapter)) {
++		SetToDs(fctrl);
++		SetFrDs(fctrl);
++	}
++
++	if (ps)
++		SetPwrMgt(fctrl);
++
++	if (pattrib->mdata)
++		SetMData(fctrl);
++
++	if (get_tofr_ds(fctrl) == 3) {
++		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN);
++		a4_shift = ETH_ALEN;
++		pattrib->hdrlen += ETH_ALEN;
++	} else {
++		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++		a4_shift = 0;
++	}
++
++	qc = (unsigned short *)(pframe + pattrib->hdrlen - 2);
++
++	SetPriority(qc, tid);
++
++	SetEOSP(qc, pattrib->eosp);
++
++	SetAckpolicy(qc, pattrib->ack_policy);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift;
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift;
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	if (wait_ack)
++		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
++	else {
++		dump_mgntframe(padapter, pmgntframe);
++		ret = _SUCCESS;
++	}
++
++exit:
++	return ret;
++}
++
++/*
++ * when wait_ms >0 , this function should be called at process context
++ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
++ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
++ * try_cnt means the maximal TX count to try
++ * da == NULL for station mode
++ */
++int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int try_cnt, int wait_ms)
++{
++	int ret = _FAIL;
++	int i = 0;
++	systime start = rtw_get_current_time();
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		goto exit;
++
++	/* da == NULL, assum it's null data for sta to ap*/
++	if (da == NULL)
++		da = get_my_bssid(&(pmlmeinfo->network));
++
++	do {
++		ret = _issue_qos_nulldata(padapter, da, tid, ps, wait_ms > 0 ? _TRUE : _FALSE);
++
++		i++;
++
++		if (RTW_CANNOT_RUN(padapter))
++			break;
++
++		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
++			rtw_msleep_os(wait_ms);
++
++	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
++
++	if (ret != _FAIL) {
++		ret = _SUCCESS;
++#ifndef DBG_XMIT_ACK
++		goto exit;
++#endif
++	}
++
++	if (try_cnt && wait_ms) {
++		if (da)
++			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
++				FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
++				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
++		else
++			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
++				FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
++				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
++	}
++exit:
++	return ret;
++}
++
++static int _issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason, u8 wait_ack, u8 key_type)
++{
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	int ret = _FAIL;
++#ifdef CONFIG_P2P
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++#endif /* CONFIG_P2P	 */
++
++	/* RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(da)); */
++
++#ifdef CONFIG_P2P
++	if (!(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) && (pwdinfo->rx_invitereq_info.scan_op_ch_only)) {
++		_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);
++		_set_timer(&pwdinfo->reset_ch_sitesurvey, 10);
++	}
++#endif /* CONFIG_P2P */
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		goto exit;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++	pattrib->retry_ctrl = _FALSE;
++	pattrib->key_type = key_type;
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_DEAUTH);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	reason = cpu_to_le16(reason);
++	pframe = rtw_set_fixed_ie(pframe, _RSON_CODE_ , (unsigned char *)&reason, &(pattrib->pktlen));
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++
++	if (wait_ack)
++		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
++	else {
++		dump_mgntframe(padapter, pmgntframe);
++		ret = _SUCCESS;
++	}
++
++exit:
++	return ret;
++}
++
++int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason)
++{
++	RTW_INFO("%s reason(%u) to "MAC_FMT"\n", __func__, reason, MAC_ARG(da));
++	return _issue_deauth(padapter, da, reason, _FALSE, IEEE80211W_RIGHT_KEY);
++}
++
++#ifdef CONFIG_IEEE80211W
++int issue_deauth_11w(_adapter *padapter, unsigned char *da, unsigned short reason, u8 key_type)
++{
++	RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(da));
++	return _issue_deauth(padapter, da, reason, _FALSE, key_type);
++}
++#endif /* CONFIG_IEEE80211W */
++
++/*
++ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
++ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
++ * try_cnt means the maximal TX count to try
++ */
++int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt,
++		    int wait_ms)
++{
++	int ret = _FAIL;
++	int i = 0;
++	systime start = rtw_get_current_time();
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		goto exit;
++
++	do {
++		ret = _issue_deauth(padapter, da, reason, wait_ms > 0 ? _TRUE : _FALSE, IEEE80211W_RIGHT_KEY);
++
++		i++;
++
++		if (RTW_CANNOT_RUN(padapter))
++			break;
++
++		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
++			rtw_msleep_os(wait_ms);
++
++	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
++
++	if (ret != _FAIL) {
++		ret = _SUCCESS;
++#ifndef DBG_XMIT_ACK
++		goto exit;
++#endif
++	}
++
++	if (try_cnt && wait_ms) {
++		if (da)
++			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
++				FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
++				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
++		else
++			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
++				FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
++				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
++	}
++exit:
++	return ret;
++}
++
++void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset)
++{
++	struct xmit_frame *pmgntframe;
++	struct pkt_attrib *pattrib;
++	unsigned char				*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short			*fctrl;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		return;
++
++	RTW_INFO(FUNC_NDEV_FMT" ra="MAC_FMT", ch:%u, offset:%u\n",
++		FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(ra), new_ch, ch_offset);
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); /* RA */
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); /* TA */
++	_rtw_memcpy(pwlanhdr->addr3, ra, ETH_ALEN); /* DA = RA */
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	/* category, action */
++	{
++		u8 category, action;
++		category = RTW_WLAN_CATEGORY_SPECTRUM_MGMT;
++		action = RTW_WLAN_ACTION_SPCT_CHL_SWITCH;
++
++		pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++		pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++	}
++
++	pframe = rtw_set_ie_ch_switch(pframe, &(pattrib->pktlen), 0, new_ch, 0);
++	pframe = rtw_set_ie_secondary_ch_offset(pframe, &(pattrib->pktlen),
++			hal_ch_offset_to_secondary_ch_offset(ch_offset));
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(padapter, pmgntframe);
++
++}
++
++#ifdef CONFIG_IEEE80211W
++void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid, u8 key_type)
++{
++	u8	category = RTW_WLAN_CATEGORY_SA_QUERY;
++	u16	reason_code;
++	struct xmit_frame		*pmgntframe;
++	struct pkt_attrib		*pattrib;
++	u8					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	u16					*fctrl;
++	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct sta_info		*psta;
++	struct sta_priv		*pstapriv = &padapter->stapriv;
++	struct registry_priv		*pregpriv = &padapter->registrypriv;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		return;
++
++	RTW_INFO("%s, %04x\n", __FUNCTION__, tid);
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL) {
++		RTW_INFO("%s: alloc_mgtxmitframe fail\n", __FUNCTION__);
++		return;
++	}
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++	pattrib->key_type = key_type;
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	if (raddr)
++		_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
++	else
++		_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &category, &pattrib->pktlen);
++	pframe = rtw_set_fixed_ie(pframe, 1, &action, &pattrib->pktlen);
++
++	switch (action) {
++	case 0: /* SA Query req */
++		pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&pmlmeext->sa_query_seq, &pattrib->pktlen);
++		pmlmeext->sa_query_seq++;
++		/* send sa query request to AP, AP should reply sa query response in 1 second */
++		if (pattrib->key_type == IEEE80211W_RIGHT_KEY) {
++			psta = rtw_get_stainfo(pstapriv, pwlanhdr->addr1);
++			if (psta != NULL) {
++				/* RTW_INFO("%s, %d, set dot11w_expire_timer\n", __func__, __LINE__); */
++				_set_timer(&psta->dot11w_expire_timer, 1000);
++			}
++		}
++		break;
++
++	case 1: /* SA Query rsp */
++		tid = cpu_to_le16(tid);
++		/* RTW_INFO("rtw_set_fixed_ie, %04x\n", tid); */
++		pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&tid, &pattrib->pktlen);
++		break;
++	default:
++		break;
++	}
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(padapter, pmgntframe);
++}
++#endif /* CONFIG_IEEE80211W */
++
++/**
++ * issue_action_ba - internal function to TX Block Ack action frame
++ * @padapter: the adapter to TX
++ * @raddr: receiver address
++ * @action: Block Ack Action
++ * @tid: tid
++ * @size: the announced AMPDU buffer size. used by ADDBA_RESP
++ * @status: status/reason code. used by ADDBA_RESP, DELBA
++ * @initiator: if we are the initiator of AMPDU association. used by DELBA
++ * @wait_ack: used xmit ack
++ *
++ * Returns:
++ * _SUCCESS: No xmit ack is used or acked
++ * _FAIL: not acked when using xmit ack
++ */
++static int issue_action_ba(_adapter *padapter, unsigned char *raddr, unsigned char action
++		   , u8 tid, u8 size, u16 status, u8 initiator, int wait_ack)
++{
++	int ret = _FAIL;
++	u8	category = RTW_WLAN_CATEGORY_BACK;
++	u16	start_seq;
++	u16	BA_para_set;
++	u16	BA_timeout_value;
++	u16	BA_starting_seqctrl;
++	struct xmit_frame		*pmgntframe;
++	struct pkt_attrib		*pattrib;
++	u8					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	u16					*fctrl;
++	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct sta_info		*psta;
++	struct sta_priv		*pstapriv = &padapter->stapriv;
++	struct registry_priv		*pregpriv = &padapter->registrypriv;
++
++#ifdef CONFIG_80211N_HT
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		goto exit;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	/* _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); */
++	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++
++	if (category == 3) {
++		switch (action) {
++		case RTW_WLAN_ACTION_ADDBA_REQ:
++			do {
++				pmlmeinfo->dialogToken++;
++			} while (pmlmeinfo->dialogToken == 0);
++			pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->dialogToken), &(pattrib->pktlen));
++
++#if defined(CONFIG_RTL8188E) && defined(CONFIG_SDIO_HCI)
++			BA_para_set = (0x0802 | ((tid & 0xf) << 2)); /* immediate ack & 16 buffer size */
++#else
++			BA_para_set = (0x1002 | ((tid & 0xf) << 2)); /* immediate ack & 64 buffer size */
++#endif
++
++#ifdef CONFIG_TX_AMSDU
++			if (padapter->tx_amsdu >= 1) /* TX AMSDU  enabled */
++				BA_para_set |= BIT(0);
++			else /* TX AMSDU disabled */
++				BA_para_set &= ~BIT(0);
++#endif
++			BA_para_set = cpu_to_le16(BA_para_set);
++			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen));
++
++			/* BA_timeout_value = 0xffff; */ /* max: 65535 TUs(~ 65 ms) */
++			BA_timeout_value = 5000;/* ~ 5ms */
++			BA_timeout_value = cpu_to_le16(BA_timeout_value);
++			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_timeout_value)), &(pattrib->pktlen));
++
++			/* if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL) */
++			psta = rtw_get_stainfo(pstapriv, raddr);
++			if (psta != NULL) {
++				start_seq = (psta->sta_xmitpriv.txseq_tid[tid & 0x07] & 0xfff) + 1;
++
++				RTW_INFO("BA_starting_seqctrl = %d for TID=%d\n", start_seq, tid & 0x07);
++
++				psta->BA_starting_seqctrl[tid & 0x07] = start_seq;
++
++				BA_starting_seqctrl = start_seq << 4;
++			}
++
++			BA_starting_seqctrl = cpu_to_le16(BA_starting_seqctrl);
++			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_starting_seqctrl)), &(pattrib->pktlen));
++			break;
++
++		case RTW_WLAN_ACTION_ADDBA_RESP:
++			pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->ADDBA_req.dialog_token), &(pattrib->pktlen));
++			status = cpu_to_le16(status);
++			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&status), &(pattrib->pktlen));
++
++			BA_para_set = le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set);
++
++			BA_para_set &= ~IEEE80211_ADDBA_PARAM_TID_MASK;
++			BA_para_set |= (tid << 2) & IEEE80211_ADDBA_PARAM_TID_MASK;
++
++			BA_para_set &= ~RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK;
++			BA_para_set |= (size << 6) & RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK;
++
++			if (!padapter->registrypriv.wifi_spec) {
++				if (pregpriv->rx_ampdu_amsdu == 0) /* disabled */
++					BA_para_set &= ~BIT(0);
++				else if (pregpriv->rx_ampdu_amsdu == 1) /* enabled */
++					BA_para_set |= BIT(0);
++			}
++
++			BA_para_set = cpu_to_le16(BA_para_set);
++
++			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen));
++			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(pmlmeinfo->ADDBA_req.BA_timeout_value)), &(pattrib->pktlen));
++			break;
++
++		case RTW_WLAN_ACTION_DELBA:
++			BA_para_set = 0;
++			BA_para_set |= (tid << 12) & IEEE80211_DELBA_PARAM_TID_MASK;
++			BA_para_set |= (initiator << 11) & IEEE80211_DELBA_PARAM_INITIATOR_MASK;
++
++			BA_para_set = cpu_to_le16(BA_para_set);
++			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen));
++			status = cpu_to_le16(status);
++			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(status)), &(pattrib->pktlen));
++			break;
++		default:
++			break;
++		}
++	}
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	if (wait_ack)
++		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
++	else {
++		dump_mgntframe(padapter, pmgntframe);
++		ret = _SUCCESS;
++	}
++
++exit:
++#endif /* CONFIG_80211N_HT */
++	return ret;
++}
++
++/**
++ * issue_addba_req - TX ADDBA_REQ
++ * @adapter: the adapter to TX
++ * @ra: receiver address
++ * @tid: tid
++ */
++inline void issue_addba_req(_adapter *adapter, unsigned char *ra, u8 tid)
++{
++	issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_REQ
++			, tid
++			, 0 /* unused */
++			, 0 /* unused */
++			, 0 /* unused */
++			, _FALSE
++		       );
++	RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" tid=%u\n"
++		 , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), tid);
++
++}
++
++/**
++ * issue_addba_rsp - TX ADDBA_RESP
++ * @adapter: the adapter to TX
++ * @ra: receiver address
++ * @tid: tid
++ * @status: status code
++ * @size: the announced AMPDU buffer size
++ */
++inline void issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size)
++{
++	issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_RESP
++			, tid
++			, size
++			, status
++			, 0 /* unused */
++			, _FALSE
++		       );
++	RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" status=%u, tid=%u, size=%u\n"
++		 , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), status, tid, size);
++}
++
++/**
++ * issue_addba_rsp_wait_ack - TX ADDBA_RESP and wait ack
++ * @adapter: the adapter to TX
++ * @ra: receiver address
++ * @tid: tid
++ * @status: status code
++ * @size: the announced AMPDU buffer size
++ * @try_cnt: the maximal TX count to try
++ * @wait_ms: == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
++ *           > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
++ */
++inline u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size, int try_cnt, int wait_ms)
++{
++	int ret = _FAIL;
++	int i = 0;
++	systime start = rtw_get_current_time();
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter)))
++		goto exit;
++
++	do {
++		ret = issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_RESP
++				      , tid
++				      , size
++				      , status
++				      , 0 /* unused */
++				      , _TRUE
++				     );
++
++		i++;
++
++		if (RTW_CANNOT_RUN(adapter))
++			break;
++
++		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
++			rtw_msleep_os(wait_ms);
++
++	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
++
++	if (ret != _FAIL) {
++		ret = _SUCCESS;
++#ifndef DBG_XMIT_ACK
++		/* goto exit; */
++#endif
++	}
++
++	if (try_cnt && wait_ms) {
++		RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" status:=%u tid=%u size:%u%s, %d/%d in %u ms\n"
++			, FUNC_ADPT_ARG(adapter), MAC_ARG(ra), status, tid, size
++			, ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
++	}
++
++exit:
++	return ret;
++}
++
++/**
++ * issue_del_ba - TX DELBA
++ * @adapter: the adapter to TX
++ * @ra: receiver address
++ * @tid: tid
++ * @reason: reason code
++ * @initiator: if we are the initiator of AMPDU association. used by DELBA
++ */
++inline void issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator)
++{
++	issue_action_ba(adapter, ra, RTW_WLAN_ACTION_DELBA
++			, tid
++			, 0 /* unused */
++			, reason
++			, initiator
++			, _FALSE
++		       );
++	RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" reason=%u, tid=%u, initiator=%u\n"
++		 , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), reason, tid, initiator);
++}
++
++/**
++ * issue_del_ba_ex - TX DELBA with xmit ack options
++ * @adapter: the adapter to TX
++ * @ra: receiver address
++ * @tid: tid
++ * @reason: reason code
++ * @initiator: if we are the initiator of AMPDU association. used by DELBA
++ * @try_cnt: the maximal TX count to try
++ * @wait_ms: == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
++ *           > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
++ */
++int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator
++		    , int try_cnt, int wait_ms)
++{
++	int ret = _FAIL;
++	int i = 0;
++	systime start = rtw_get_current_time();
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter)))
++		goto exit;
++
++	do {
++		ret = issue_action_ba(adapter, ra, RTW_WLAN_ACTION_DELBA
++				      , tid
++				      , 0 /* unused */
++				      , reason
++				      , initiator
++				      , wait_ms > 0 ? _TRUE : _FALSE
++				     );
++
++		i++;
++
++		if (RTW_CANNOT_RUN(adapter))
++			break;
++
++		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
++			rtw_msleep_os(wait_ms);
++
++	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
++
++	if (ret != _FAIL) {
++		ret = _SUCCESS;
++#ifndef DBG_XMIT_ACK
++		/* goto exit; */
++#endif
++	}
++
++	if (try_cnt && wait_ms) {
++		RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" reason=%u, tid=%u, initiator=%u%s, %d/%d in %u ms\n"
++			, FUNC_ADPT_ARG(adapter), MAC_ARG(ra), reason, tid, initiator
++			, ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
++	}
++exit:
++	return ret;
++}
++
++void issue_action_BSSCoexistPacket(_adapter *padapter)
++{
++	_irqL	irqL;
++	_list		*plist, *phead;
++	unsigned char category, action;
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char				*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short			*fctrl;
++	struct	wlan_network	*pnetwork = NULL;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	_queue		*queue	= &(pmlmepriv->scanned_queue);
++	u8 InfoContent[16] = {0};
++	u8 ICS[8][15];
++#ifdef CONFIG_80211N_HT
++	if ((pmlmepriv->num_FortyMHzIntolerant == 0) && (pmlmepriv->num_sta_no_ht == 0))
++		return;
++
++	if (_TRUE == pmlmeinfo->bwmode_updated)
++		return;
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		return;
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++
++	category = RTW_WLAN_CATEGORY_PUBLIC;
++	action = ACT_PUBLIC_BSSCOEXIST;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++
++	/* TODO calculate 40Mhz intolerant via ch and ch offset */
++	/* if (pmlmepriv->num_FortyMHzIntolerant > 0) */
++	{
++		u8 iedata = 0;
++
++		iedata |= BIT(2);/* 20 MHz BSS Width Request */
++		pframe = rtw_set_ie(pframe, EID_BSSCoexistence,  1, &iedata, &(pattrib->pktlen));
++	}
++
++	/*  */
++	_rtw_memset(ICS, 0, sizeof(ICS));
++	if (pmlmepriv->num_sta_no_ht > 0) {
++		int i;
++
++		_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++		phead = get_list_head(queue);
++		plist = get_next(phead);
++
++		while (1) {
++			int len;
++			u8 *p;
++			WLAN_BSSID_EX *pbss_network;
++
++			if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++				break;
++
++			pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++			plist = get_next(plist);
++
++			pbss_network = (WLAN_BSSID_EX *)&pnetwork->network;
++
++			p = rtw_get_ie(pbss_network->IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, pbss_network->IELength - _FIXED_IE_LENGTH_);
++			if ((p == NULL) || (len == 0)) { /* non-HT */
++				if ((pbss_network->Configuration.DSConfig <= 0) || (pbss_network->Configuration.DSConfig > 14))
++					continue;
++
++				ICS[0][pbss_network->Configuration.DSConfig] = 1;
++
++				if (ICS[0][0] == 0)
++					ICS[0][0] = 1;
++			}
++
++		}
++
++		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++
++		for (i = 0; i < 8; i++) {
++			if (ICS[i][0] == 1) {
++				int j, k = 0;
++
++				InfoContent[k] = i;
++				/* SET_BSS_INTOLERANT_ELE_REG_CLASS(InfoContent,i); */
++				k++;
++
++				for (j = 1; j <= 14; j++) {
++					if (ICS[i][j] == 1) {
++						if (k < 16) {
++							InfoContent[k] = j; /* channel number */
++							/* SET_BSS_INTOLERANT_ELE_CHANNEL(InfoContent+k, j); */
++							k++;
++						}
++					}
++				}
++
++				pframe = rtw_set_ie(pframe, EID_BSSIntolerantChlReport, k, InfoContent, &(pattrib->pktlen));
++
++			}
++
++		}
++
++
++	}
++
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(padapter, pmgntframe);
++#endif /* CONFIG_80211N_HT */
++}
++
++/* Spatial Multiplexing Powersave (SMPS) action frame */
++int _issue_action_SM_PS(_adapter *padapter ,  unsigned char *raddr , u8 NewMimoPsMode ,  u8 wait_ack)
++{
++
++	int ret = _FAIL;
++	unsigned char category = RTW_WLAN_CATEGORY_HT;
++	u8 action = RTW_WLAN_ACTION_HT_SM_PS;
++	u8 sm_power_control = 0;
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++
++	if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_DISABLED) {
++		sm_power_control = sm_power_control  & ~(BIT(0)); /* SM Power Save Enable = 0 SM Power Save Disable */
++	} else if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_STATIC) {
++		sm_power_control = sm_power_control | BIT(0);    /* SM Power Save Enable = 1 SM Power Save Enable  */
++		sm_power_control = sm_power_control & ~(BIT(1)); /* SM Mode = 0 Static Mode */
++	} else if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_DYNAMIC) {
++		sm_power_control = sm_power_control | BIT(0); /* SM Power Save Enable = 1 SM Power Save Enable  */
++		sm_power_control = sm_power_control | BIT(1); /* SM Mode = 1 Dynamic Mode */
++	} else
++		return ret;
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		return ret;
++
++	RTW_INFO("%s, sm_power_control=%u, NewMimoPsMode=%u\n", __FUNCTION__ , sm_power_control , NewMimoPsMode);
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return ret;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); /* RA */
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); /* TA */
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); /* DA = RA */
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	/* category, action */
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &(sm_power_control), &(pattrib->pktlen));
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	if (wait_ack)
++		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
++	else {
++		dump_mgntframe(padapter, pmgntframe);
++		ret = _SUCCESS;
++	}
++
++	if (ret != _SUCCESS)
++		RTW_INFO("%s, ack to\n", __func__);
++
++	return ret;
++}
++
++/*
++ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
++ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
++ * try_cnt means the maximal TX count to try
++ */
++int issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 NewMimoPsMode, int try_cnt, int wait_ms)
++{
++	int ret = _FAIL;
++	int i = 0;
++	systime start = rtw_get_current_time();
++
++	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
++		goto exit;
++
++	do {
++		ret = _issue_action_SM_PS(padapter, raddr, NewMimoPsMode , wait_ms > 0 ? _TRUE : _FALSE);
++
++		i++;
++
++		if (RTW_CANNOT_RUN(padapter))
++			break;
++
++		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
++			rtw_msleep_os(wait_ms);
++
++	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
++
++	if (ret != _FAIL) {
++		ret = _SUCCESS;
++#ifndef DBG_XMIT_ACK
++		goto exit;
++#endif
++	}
++
++	if (try_cnt && wait_ms) {
++		if (raddr)
++			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", %s , %d/%d in %u ms\n",
++				 FUNC_ADPT_ARG(padapter), MAC_ARG(raddr),
++				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
++		else
++			RTW_INFO(FUNC_ADPT_FMT", %s , %d/%d in %u ms\n",
++				 FUNC_ADPT_ARG(padapter),
++				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
++	}
++exit:
++
++	return ret;
++}
++
++int issue_action_SM_PS(_adapter *padapter ,  unsigned char *raddr , u8 NewMimoPsMode)
++{
++	RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(raddr));
++	return _issue_action_SM_PS(padapter, raddr, NewMimoPsMode , _FALSE);
++}
++
++/**
++ * _send_delba_sta_tid - Cancel the AMPDU association for the specific @sta, @tid
++ * @adapter: the adapter to which @sta belongs
++ * @initiator: if we are the initiator of AMPDU association
++ * @sta: the sta to be checked
++ * @tid: the tid to be checked
++ * @force: cancel and send DELBA even when no AMPDU association is setup
++ * @wait_ack: send delba with xmit ack (valid when initiator == 0)
++ *
++ * Returns:
++ * _FAIL if sta is NULL
++ * when initiator is 1, always _SUCCESS
++ * when initiator is 0, _SUCCESS if DELBA is acked
++ */
++static unsigned int _send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid
++					, u8 force, int wait_ack)
++{
++	int ret = _SUCCESS;
++
++	if (sta == NULL) {
++		ret = _FAIL;
++		goto exit;
++	}
++
++	if (initiator == 0) {
++		/* recipient */
++		if (force || sta->recvreorder_ctrl[tid].enable == _TRUE) {
++			u8 ampdu_size_bak = sta->recvreorder_ctrl[tid].ampdu_size;
++
++			sta->recvreorder_ctrl[tid].enable = _FALSE;
++			sta->recvreorder_ctrl[tid].ampdu_size = RX_AMPDU_SIZE_INVALID;
++
++			if (rtw_del_rx_ampdu_test_trigger_no_tx_fail())
++				ret = _FAIL;
++			else if (wait_ack)
++				ret = issue_del_ba_ex(adapter, sta->cmn.mac_addr, tid, 37, initiator, 3, 1);
++			else
++				issue_del_ba(adapter, sta->cmn.mac_addr, tid, 37, initiator);
++
++			if (ret == _FAIL && sta->recvreorder_ctrl[tid].enable == _FALSE)
++				sta->recvreorder_ctrl[tid].ampdu_size = ampdu_size_bak;
++		}
++	} else if (initiator == 1) {
++		/* originator */
++#ifdef CONFIG_80211N_HT
++		if (force || sta->htpriv.agg_enable_bitmap & BIT(tid)) {
++			sta->htpriv.agg_enable_bitmap &= ~BIT(tid);
++			sta->htpriv.candidate_tid_bitmap &= ~BIT(tid);
++			issue_del_ba(adapter, sta->cmn.mac_addr, tid, 37, initiator);
++		}
++#endif
++	}
++
++exit:
++	return ret;
++}
++
++inline unsigned int send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid
++				       , u8 force)
++{
++	return _send_delba_sta_tid(adapter, initiator, sta, tid, force, 0);
++}
++
++inline unsigned int send_delba_sta_tid_wait_ack(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid
++		, u8 force)
++{
++	return _send_delba_sta_tid(adapter, initiator, sta, tid, force, 1);
++}
++
++unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr)
++{
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct sta_info *psta = NULL;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u16 tid;
++
++	if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
++		if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS))
++			return _SUCCESS;
++
++	psta = rtw_get_stainfo(pstapriv, addr);
++	if (psta == NULL)
++		return _SUCCESS;
++
++#if 0
++	RTW_INFO("%s:%s\n", __func__, (initiator == 0) ? "RX_DIR" : "TX_DIR");
++	if (initiator == 1) /* originator */
++		RTW_INFO("tx agg_enable_bitmap(0x%08x)\n", psta->htpriv.agg_enable_bitmap);
++#endif
++
++	for (tid = 0; tid < TID_NUM; tid++)
++		send_delba_sta_tid(padapter, initiator, psta, tid, 0);
++
++	return _SUCCESS;
++}
++
++unsigned int send_beacon(_adapter *padapter)
++{
++#if defined(CONFIG_PCI_HCI) && !defined(CONFIG_PCI_BCN_POLLING)
++	#ifdef CONFIG_FW_HANDLE_TXBCN
++	u8 vap_id = padapter->vap_id;
++
++	/* bypass TX BCN because vap_id is invalid*/
++	if (vap_id == CONFIG_LIMITED_AP_NUM)
++		return _SUCCESS;
++	#endif
++
++	/* bypass TX BCN queue because op ch is switching/waiting */
++	if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING)
++		|| IS_CH_WAITING(adapter_to_rfctl(padapter))
++	)
++		return _SUCCESS;
++
++	/* RTW_INFO("%s\n", __FUNCTION__); */
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
++
++	/* 8192EE Port select for Beacon DL */
++	rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
++	#ifdef CONFIG_FW_HANDLE_TXBCN
++	rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id);
++	#endif
++
++	issue_beacon(padapter, 0);
++
++	#ifdef CONFIG_FW_HANDLE_TXBCN
++	vap_id = 0xFF;
++	rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id);
++	#endif
++
++	#ifdef RTL8814AE_SW_BCN
++	if (GET_HAL_DATA(padapter)->bCorrectBCN != 0)
++		RTW_INFO("%s, line%d, Warnning, pHalData->bCorrectBCN != 0\n", __func__, __LINE__);
++	GET_HAL_DATA(padapter)->bCorrectBCN = 1;
++	#endif
++
++	return _SUCCESS;
++#endif
++
++/* CONFIG_PCI_BCN_POLLING is for pci interface beacon polling mode */
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)|| defined(CONFIG_PCI_BCN_POLLING) 
++	u8 bxmitok = _FALSE;
++	int issue = 0;
++	int poll = 0;
++	systime start = rtw_get_current_time();
++	#ifdef CONFIG_FW_HANDLE_TXBCN
++	u8 vap_id = padapter->vap_id;
++
++	/* bypass TX BCN because vap_id is invalid*/
++	if (vap_id == CONFIG_LIMITED_AP_NUM)
++		return _SUCCESS;
++	#endif
++
++	/* bypass TX BCN queue because op ch is switching/waiting */
++	if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING)
++		|| IS_CH_WAITING(adapter_to_rfctl(padapter))
++	)
++		return _SUCCESS;
++
++	#if defined(CONFIG_USB_HCI)
++	#if defined(CONFIG_RTL8812A)
++	if (IS_FULL_SPEED_USB(padapter)) {
++		issue_beacon(padapter, 300);
++		bxmitok = _TRUE;
++	} else
++	#endif
++	#endif
++	{
++		rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
++		rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
++		#ifdef CONFIG_FW_HANDLE_TXBCN
++		rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id);
++		#endif
++		do {
++			#if defined(CONFIG_PCI_BCN_POLLING) 
++			issue_beacon(padapter, 0);
++			#else
++			issue_beacon(padapter, 100);
++			#endif
++			issue++;
++			do {
++				#if defined(CONFIG_PCI_BCN_POLLING) 
++				rtw_msleep_os(1);
++				#else
++				rtw_yield_os();
++				#endif
++				rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8 *)(&bxmitok));
++				poll++;
++			} while ((poll % 10) != 0 && _FALSE == bxmitok && !RTW_CANNOT_RUN(padapter));
++			#if defined(CONFIG_PCI_BCN_POLLING) 
++			rtw_hal_unmap_beacon_icf(padapter);
++			#endif
++		} while (bxmitok == _FALSE && (issue < 100) && !RTW_CANNOT_RUN(padapter));
++		#ifdef CONFIG_FW_HANDLE_TXBCN
++		vap_id = 0xFF;
++		rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id);
++		#endif
++	}
++	if (RTW_CANNOT_RUN(padapter))
++		return _FAIL;
++
++
++	if (_FALSE == bxmitok) {
++		RTW_INFO("%s fail! %u ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
++		#ifdef CONFIG_BCN_RECOVERY
++		GET_HAL_DATA(padapter)->issue_bcn_fail++;
++		#endif  /*CONFIG_BCN_RECOVERY*/
++		return _FAIL;
++	} else {
++		u32 passing_time = rtw_get_passing_time_ms(start);
++
++		if (passing_time > 100 || issue > 3)
++			RTW_INFO("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start));
++		else if (0)
++			RTW_INFO("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start));
++
++		#ifdef CONFIG_FW_CORRECT_BCN
++		rtw_hal_fw_correct_bcn(padapter);
++		#endif
++		return _SUCCESS;
++	}
++
++#endif /*defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)*/
++
++}
++
++/****************************************************************************
++
++Following are some utitity fuctions for WiFi MLME
++
++*****************************************************************************/
++
++BOOLEAN IsLegal5GChannel(
++	PADAPTER			Adapter,
++	u8			channel)
++{
++
++	int i = 0;
++	u8 Channel_5G[45] = {36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
++		60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122,
++		124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159,
++			     161, 163, 165
++			    };
++	for (i = 0; i < sizeof(Channel_5G); i++)
++		if (channel == Channel_5G[i])
++			return _TRUE;
++	return _FALSE;
++}
++
++/* collect bss info from Beacon and Probe request/response frames. */
++u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid)
++{
++	int	i;
++	sint len;
++	u8	*p;
++	u8	rf_path;
++	u16	val16, subtype;
++	u8	*pframe = precv_frame->u.hdr.rx_data;
++	u32	packet_len = precv_frame->u.hdr.len;
++	u8 ie_offset;
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++
++	len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	if (len > MAX_IE_SZ) {
++		/* RTW_INFO("IE too long for survey event\n"); */
++		return _FAIL;
++	}
++
++	_rtw_memset(bssid, 0, sizeof(WLAN_BSSID_EX));
++
++	subtype = get_frame_sub_type(pframe);
++
++	if (subtype == WIFI_BEACON) {
++		bssid->Reserved[0] = BSS_TYPE_BCN;
++		ie_offset = _BEACON_IE_OFFSET_;
++	} else {
++		/* FIXME : more type */
++		if (subtype == WIFI_PROBERSP) {
++			ie_offset = _PROBERSP_IE_OFFSET_;
++			bssid->Reserved[0] = BSS_TYPE_PROB_RSP;
++		} else if (subtype == WIFI_PROBEREQ) {
++			ie_offset = _PROBEREQ_IE_OFFSET_;
++			bssid->Reserved[0] = BSS_TYPE_PROB_REQ;
++		} else {
++			bssid->Reserved[0] = BSS_TYPE_UNDEF;
++			ie_offset = _FIXED_IE_LENGTH_;
++		}
++	}
++
++	bssid->Length = sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + len;
++
++	/* below is to copy the information element */
++	bssid->IELength = len;
++	_rtw_memcpy(bssid->IEs, (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)), bssid->IELength);
++
++	/* get the signal strength */
++	/* bssid->Rssi = precv_frame->u.hdr.attrib.SignalStrength; */ /* 0-100 index. */
++	bssid->Rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power; /* in dBM.raw data */
++	bssid->PhyInfo.SignalQuality = precv_frame->u.hdr.attrib.phy_info.signal_quality;/* in percentage */
++	bssid->PhyInfo.SignalStrength = precv_frame->u.hdr.attrib.phy_info.signal_strength;/* in percentage */
++
++	/* get rx_snr */
++	if (precv_frame->u.hdr.attrib.data_rate >= DESC_RATE11M) {
++		bssid->PhyInfo.is_cck_rate = 0;
++		for (rf_path = 0; rf_path < hal_spec->rf_reg_path_num; rf_path++)
++			bssid->PhyInfo.rx_snr[rf_path] =
++				precv_frame->u.hdr.attrib.phy_info.rx_snr[rf_path];
++	} else
++		bssid->PhyInfo.is_cck_rate = 1;
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &(bssid->PhyInfo.Optimum_antenna), NULL);
++#endif
++
++	/* checking SSID */
++	p = rtw_get_ie(bssid->IEs + ie_offset, _SSID_IE_, &len, bssid->IELength - ie_offset);
++	if (p == NULL) {
++		RTW_INFO("marc: cannot find SSID for survey event\n");
++		return _FAIL;
++	}
++
++	if (*(p + 1)) {
++		if (len > NDIS_802_11_LENGTH_SSID) {
++			RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len);
++			return _FAIL;
++		}
++		_rtw_memcpy(bssid->Ssid.Ssid, (p + 2), *(p + 1));
++		bssid->Ssid.SsidLength = *(p + 1);
++	} else
++		bssid->Ssid.SsidLength = 0;
++
++	_rtw_memset(bssid->SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX);
++
++	/* checking rate info... */
++	i = 0;
++	p = rtw_get_ie(bssid->IEs + ie_offset, _SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset);
++	if (p != NULL) {
++		if (len > NDIS_802_11_LENGTH_RATES_EX) {
++			RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len);
++			return _FAIL;
++		}
++		if (rtw_validate_value(_SUPPORTEDRATES_IE_, p+2, len) == _FALSE) {
++			rtw_absorb_ssid_ifneed(padapter, bssid, pframe);
++			RTW_DBG_DUMP("Invalidated Support Rate IE --", p, len+2);
++			return _FAIL;
++		}
++		_rtw_memcpy(bssid->SupportedRates, (p + 2), len);
++		i = len;
++	}
++
++	p = rtw_get_ie(bssid->IEs + ie_offset, _EXT_SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset);
++	if (p != NULL) {
++		if (len > (NDIS_802_11_LENGTH_RATES_EX - i)) {
++			RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len);
++			return _FAIL;
++		}
++		if (rtw_validate_value(_EXT_SUPPORTEDRATES_IE_, p+2, len) == _FALSE) {
++			rtw_absorb_ssid_ifneed(padapter, bssid, pframe);
++			RTW_DBG_DUMP("Invalidated EXT Support Rate IE --", p, len+2);
++			return _FAIL;
++		}
++		_rtw_memcpy(bssid->SupportedRates + i, (p + 2), len);
++	}
++
++#ifdef CONFIG_P2P
++	if (subtype == WIFI_PROBEREQ) {
++		u8 *p2p_ie;
++		u32	p2p_ielen;
++		/* Set Listion Channel */
++		p2p_ie = rtw_get_p2p_ie(bssid->IEs, bssid->IELength, NULL, &p2p_ielen);
++		if (p2p_ie) {
++			u32	attr_contentlen = 0;
++			u8 listen_ch[5] = { 0x00 };
++
++			rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, listen_ch, &attr_contentlen);
++			bssid->Configuration.DSConfig = listen_ch[4];
++		} else {
++			/* use current channel */
++			bssid->Configuration.DSConfig = padapter->mlmeextpriv.cur_channel;
++			RTW_INFO("%s()-%d: Cannot get p2p_ie. set DSconfig to op_ch(%d)\n", __FUNCTION__, __LINE__, bssid->Configuration.DSConfig);
++		}
++
++		/* FIXME */
++		bssid->InfrastructureMode = Ndis802_11Infrastructure;
++		_rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN);
++		bssid->Privacy = 1;
++		return _SUCCESS;
++	}
++#endif /* CONFIG_P2P */
++
++	if (bssid->IELength < 12)
++		return _FAIL;
++
++	/* Checking for DSConfig */
++	p = rtw_get_ie(bssid->IEs + ie_offset, _DSSET_IE_, &len, bssid->IELength - ie_offset);
++
++	bssid->Configuration.DSConfig = 0;
++	bssid->Configuration.Length = 0;
++
++	if (p)
++		bssid->Configuration.DSConfig = *(p + 2);
++	else {
++		/* In 5G, some ap do not have DSSET IE */
++		/* checking HT info for channel */
++		p = rtw_get_ie(bssid->IEs + ie_offset, _HT_ADD_INFO_IE_, &len, bssid->IELength - ie_offset);
++		if (p) {
++			struct HT_info_element *HT_info = (struct HT_info_element *)(p + 2);
++			bssid->Configuration.DSConfig = HT_info->primary_channel;
++		} else {
++			/* use current channel */
++			bssid->Configuration.DSConfig = rtw_get_oper_ch(padapter);
++		}
++	}
++
++	_rtw_memcpy(&bssid->Configuration.BeaconPeriod, rtw_get_beacon_interval_from_ie(bssid->IEs), 2);
++	bssid->Configuration.BeaconPeriod = le32_to_cpu(bssid->Configuration.BeaconPeriod);
++
++	val16 = rtw_get_capability((WLAN_BSSID_EX *)bssid);
++
++	if ((val16 & 0x03) == cap_ESS) {
++		bssid->InfrastructureMode = Ndis802_11Infrastructure;
++		_rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN);
++	} else if ((val16 & 0x03) == cap_IBSS){
++		bssid->InfrastructureMode = Ndis802_11IBSS;
++		_rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN);
++	} else if ((val16 & 0x03) == 0x00){
++		u8 *mesh_id_ie, *mesh_conf_ie;
++		sint mesh_id_ie_len, mesh_conf_ie_len;
++
++		mesh_id_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_ID, &mesh_id_ie_len, bssid->IELength - ie_offset);
++		mesh_conf_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_CONFIG, &mesh_conf_ie_len, bssid->IELength - ie_offset);
++		if (mesh_id_ie || mesh_conf_ie) {
++			if (!mesh_id_ie) {
++				RTW_INFO("cannot find Mesh ID for survey event\n");
++				return _FAIL;
++			}
++			if (mesh_id_ie_len) {
++				if (mesh_id_ie_len > NDIS_802_11_LENGTH_SSID) {
++					RTW_INFO("Mesh ID too long (%d) for survey event\n", mesh_id_ie_len);
++					return _FAIL;
++				}
++				_rtw_memcpy(bssid->mesh_id.Ssid, (mesh_id_ie + 2), mesh_id_ie_len);
++				bssid->mesh_id.SsidLength = mesh_id_ie_len;
++			} else
++				bssid->mesh_id.SsidLength = 0;
++
++			if (!mesh_conf_ie) {
++				RTW_INFO("cannot find Mesh config for survey event\n");
++				return _FAIL;
++			}
++			if (mesh_conf_ie_len != 7) {
++				RTW_INFO("invalid Mesh conf IE len (%d) for survey event\n", mesh_conf_ie_len);
++				return _FAIL;
++			}
++
++			bssid->InfrastructureMode = Ndis802_11_mesh;
++			_rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN);
++		} else {
++			/* default cases */
++			bssid->InfrastructureMode = Ndis802_11IBSS;
++			_rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN);
++		}
++	}
++
++	if (val16 & BIT(4))
++		bssid->Privacy = 1;
++	else
++		bssid->Privacy = 0;
++
++	bssid->Configuration.ATIMWindow = 0;
++
++	/* 20/40 BSS Coexistence check */
++	if ((pregistrypriv->wifi_spec == 1) && (_FALSE == pmlmeinfo->bwmode_updated)) {
++		struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++#ifdef CONFIG_80211N_HT
++		p = rtw_get_ie(bssid->IEs + ie_offset, _HT_CAPABILITY_IE_, &len, bssid->IELength - ie_offset);
++		if (p && len > 0) {
++			struct HT_caps_element	*pHT_caps;
++			pHT_caps = (struct HT_caps_element *)(p + 2);
++
++			if (pHT_caps->u.HT_cap_element.HT_caps_info & BIT(14))
++				pmlmepriv->num_FortyMHzIntolerant++;
++		} else
++			pmlmepriv->num_sta_no_ht++;
++#endif /* CONFIG_80211N_HT */
++
++	}
++
++#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) & 1
++	if (strcmp(bssid->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) {
++		RTW_INFO("Receiving %s("MAC_FMT", DSConfig:%u) from ch%u with ss:%3u, sq:%3u, RawRSSI:%3ld\n"
++			, bssid->Ssid.Ssid, MAC_ARG(bssid->MacAddress), bssid->Configuration.DSConfig
++			 , rtw_get_oper_ch(padapter)
++			, bssid->PhyInfo.SignalStrength, bssid->PhyInfo.SignalQuality, bssid->Rssi
++			);
++	}
++#endif
++
++	/* mark bss info receving from nearby channel as SignalQuality 101 */
++	if (bssid->Configuration.DSConfig != rtw_get_oper_ch(padapter))
++		bssid->PhyInfo.SignalQuality = 101;
++
++#ifdef CONFIG_RTW_80211K
++	p = rtw_get_ie(bssid->IEs + ie_offset, _EID_RRM_EN_CAP_IE_, &len, bssid->IELength - ie_offset);
++	if (p)
++		_rtw_memcpy(bssid->PhyInfo.rm_en_cap, (p + 2), *(p + 1));
++
++	/* save freerun counter */
++	bssid->PhyInfo.free_cnt = precv_frame->u.hdr.attrib.free_cnt;
++#endif
++	return _SUCCESS;
++}
++
++void start_create_ibss(_adapter *padapter)
++{
++	unsigned short	caps;
++	u8	val8;
++	u8	join_type;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
++	u8 doiqk = _FALSE;
++	pmlmeext->cur_channel = (u8)pnetwork->Configuration.DSConfig;
++	pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork);
++
++	/* update wireless mode */
++	update_wireless_mode(padapter);
++
++	/* udpate capability */
++	caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork);
++	update_capinfo(padapter, caps);
++	if (caps & cap_IBSS) { /* adhoc master */
++		/* set_opmode_cmd(padapter, adhoc); */ /* removed */
++
++		val8 = 0xcf;
++		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
++
++		doiqk = _TRUE;
++		rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
++
++		/* switch channel */
++		set_channel_bwmode(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++
++		doiqk = _FALSE;
++		rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
++
++		beacon_timing_control(padapter);
++
++		/* set msr to WIFI_FW_ADHOC_STATE */
++		pmlmeinfo->state = WIFI_FW_ADHOC_STATE;
++		Set_MSR(padapter, (pmlmeinfo->state & 0x3));
++
++		/* issue beacon */
++		if (send_beacon(padapter) == _FAIL) {
++
++			report_join_res(padapter, -1, WLAN_STATUS_UNSPECIFIED_FAILURE);
++			pmlmeinfo->state = WIFI_FW_NULL_STATE;
++		} else {
++			rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress);
++			rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);
++			join_type = 0;
++			rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
++
++			rtw_btcoex_connect_notify(padapter, join_type);
++
++			report_join_res(padapter, 1, WLAN_STATUS_SUCCESS);
++			pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
++			rtw_indicate_connect(padapter);
++		}
++	} else {
++		RTW_INFO("start_create_ibss, invalid cap:%x\n", caps);
++		return;
++	}
++	/* update bc/mc sta_info */
++	update_bmc_sta(padapter);
++
++}
++
++void start_clnt_join(_adapter *padapter)
++{
++	unsigned short	caps;
++	u8	val8;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
++	int beacon_timeout;
++	u8 ASIX_ID[] = {0x00, 0x0E, 0xC6};
++
++	/* update wireless mode */
++	update_wireless_mode(padapter);
++
++	/* udpate capability */
++	caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork);
++	update_capinfo(padapter, caps);
++
++	/* check if sta is ASIX peer and fix IOT issue if it is. */
++	if (_rtw_memcmp(get_my_bssid(&pmlmeinfo->network) , ASIX_ID , 3)) {
++		u8 iot_flag = _TRUE;
++		rtw_hal_set_hwreg(padapter, HW_VAR_ASIX_IOT, (u8 *)(&iot_flag));
++	}
++
++	if (caps & cap_ESS) {
++		Set_MSR(padapter, WIFI_FW_STATION_STATE);
++
++		val8 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) ? 0xcc : 0xcf;
++
++#ifdef CONFIG_WAPI_SUPPORT
++		if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) {
++			/* Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey. */
++			val8 = 0x4c;
++		}
++#endif
++		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
++
++#ifdef CONFIG_DEAUTH_BEFORE_CONNECT
++		/* Because of AP's not receiving deauth before */
++		/* AP may: 1)not response auth or 2)deauth us after link is complete */
++		/* issue deauth before issuing auth to deal with the situation */
++
++		/*	Commented by Albert 2012/07/21 */
++		/*	For the Win8 P2P connection, it will be hard to have a successful connection if this Wi-Fi doesn't connect to it. */
++		{
++#ifdef CONFIG_P2P
++			_queue *queue = &(padapter->mlmepriv.scanned_queue);
++			_list	*head = get_list_head(queue);
++			_list *pos = get_next(head);
++			struct wlan_network *scanned = NULL;
++			u8 ie_offset = 0;
++			_irqL irqL;
++			bool has_p2p_ie = _FALSE;
++
++			_enter_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL);
++
++			for (pos = get_next(head); !rtw_end_of_queue_search(head, pos); pos = get_next(pos)) {
++
++				scanned = LIST_CONTAINOR(pos, struct wlan_network, list);
++
++				if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE
++				    && _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE
++				   ) {
++					ie_offset = (scanned->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12);
++					if (rtw_get_p2p_ie(scanned->network.IEs + ie_offset, scanned->network.IELength - ie_offset, NULL, NULL))
++						has_p2p_ie = _TRUE;
++					break;
++				}
++			}
++
++			_exit_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL);
++
++			if (scanned == NULL || rtw_end_of_queue_search(head, pos) || has_p2p_ie == _FALSE)
++#endif /* CONFIG_P2P */
++				/* To avoid connecting to AP fail during resume process, change retry count from 5 to 1 */
++				issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100);
++		}
++#endif /* CONFIG_DEAUTH_BEFORE_CONNECT */
++
++		/* here wait for receiving the beacon to start auth */
++		/* and enable a timer */
++		beacon_timeout = decide_wait_for_beacon_timeout(pmlmeinfo->bcn_interval);
++		set_link_timer(pmlmeext, beacon_timeout);
++		_set_timer(&padapter->mlmepriv.assoc_timer,
++			(REAUTH_TO * REAUTH_LIMIT) + (REASSOC_TO * REASSOC_LIMIT) + beacon_timeout);
++
++#ifdef CONFIG_RTW_80211R
++		if (rtw_ft_roam(padapter)) {
++			rtw_ft_start_clnt_join(padapter);
++		} else
++#endif
++		{
++			rtw_sta_linking_test_set_start();
++			pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE;
++		}
++	} else if (caps & cap_IBSS) { /* adhoc client */
++		Set_MSR(padapter, WIFI_FW_ADHOC_STATE);
++
++		val8 = 0xcf;
++		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
++
++		beacon_timing_control(padapter);
++
++		pmlmeinfo->state = WIFI_FW_ADHOC_STATE;
++
++		report_join_res(padapter, 1, WLAN_STATUS_SUCCESS);
++	} else {
++		/* RTW_INFO("marc: invalid cap:%x\n", caps); */
++		return;
++	}
++
++}
++
++void start_clnt_auth(_adapter *padapter)
++{
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	_cancel_timer_ex(&pmlmeext->link_timer);
++
++	pmlmeinfo->state &= (~WIFI_FW_AUTH_NULL);
++	pmlmeinfo->state |= WIFI_FW_AUTH_STATE;
++
++	pmlmeinfo->auth_seq = 1;
++	pmlmeinfo->reauth_count = 0;
++	pmlmeinfo->reassoc_count = 0;
++	pmlmeinfo->link_count = 0;
++	pmlmeext->retry = 0;
++
++#ifdef CONFIG_RTW_80211R
++	if (rtw_ft_roam(padapter)) {
++		rtw_ft_set_status(padapter, RTW_FT_AUTHENTICATING_STA);
++		RTW_PRINT("start ft auth\n");
++	} else
++#endif
++		RTW_PRINT("start auth\n");
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (rtw_sec_chk_auth_type(padapter, MLME_AUTHTYPE_SAE)) {
++		if (rtw_cached_pmkid(padapter, get_my_bssid(&pmlmeinfo->network)) != -1) {
++			RTW_INFO("SAE: PMKSA cache entry found\n");
++			padapter->securitypriv.auth_alg = WLAN_AUTH_OPEN;
++			goto no_external_auth;
++		}
++
++		RTW_PRINT("SAE: start external auth\n");
++		rtw_cfg80211_external_auth_request(padapter, NULL);
++		return;
++	}
++no_external_auth:
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++	issue_auth(padapter, NULL, 0);
++
++	set_link_timer(pmlmeext, REAUTH_TO);
++
++}
++
++
++void start_clnt_assoc(_adapter *padapter)
++{
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	_cancel_timer_ex(&pmlmeext->link_timer);
++
++	pmlmeinfo->state &= (~(WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE));
++	pmlmeinfo->state |= (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE);
++
++#ifdef CONFIG_RTW_80211R
++	if (rtw_ft_roam(padapter)
++	#ifdef CONFIG_RTW_WNM
++		|| rtw_wnm_btm_reassoc_req(padapter)
++	#endif
++	)
++		issue_reassocreq(padapter);
++	else
++#endif
++		issue_assocreq(padapter);
++
++	set_link_timer(pmlmeext, REASSOC_TO);
++}
++
++unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, u8 locally_generated)
++{
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	if (!(_rtw_memcmp(MacAddr, get_my_bssid(&pmlmeinfo->network), ETH_ALEN)))
++		return _SUCCESS;
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++#ifdef CONFIG_RTW_REPEATER_SON
++	rtw_rson_do_disconnect(padapter);
++#endif
++	if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) {
++		if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) {
++			if (report_del_sta_event(padapter, MacAddr, reason, _TRUE, locally_generated) != _FAIL)
++				pmlmeinfo->state = WIFI_FW_NULL_STATE;
++		} else if (pmlmeinfo->state & WIFI_FW_LINKING_STATE) {
++			if (report_join_res(padapter, -2, reason) != _FAIL)
++				pmlmeinfo->state = WIFI_FW_NULL_STATE;
++		} else
++			RTW_INFO(FUNC_ADPT_FMT" - End to Disconnect\n", FUNC_ADPT_ARG(padapter));
++#ifdef CONFIG_RTW_80211R
++		rtw_ft_roam_status_reset(padapter);
++#endif
++#ifdef CONFIG_RTW_WNM
++		rtw_wnm_reset_btm_state(padapter);
++#endif
++	}
++
++	return _SUCCESS;
++}
++
++static void rtw_hidden_ssid_bss_count(_adapter *adapter, WLAN_BSSID_EX *bss)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	RT_CHANNEL_INFO *chset = rfctl->channel_set;
++	int chset_idx;
++
++	if (bss->InfrastructureMode != Ndis802_11Infrastructure)
++		return;
++
++	if (!hidden_ssid_ap(bss))
++		return;
++
++	chset_idx = rtw_chset_search_ch(chset, bss->Configuration.DSConfig);
++	if (chset_idx < 0)
++		return;
++	
++	chset[chset_idx].hidden_bss_cnt++;
++}
++
++/****************************************************************************
++
++Following are the functions to report events
++
++*****************************************************************************/
++
++void report_survey_event(_adapter *padapter, union recv_frame *precv_frame)
++{
++	struct cmd_obj *pcmd_obj;
++	u8 *pevtcmd;
++	u32 cmdsz;
++	struct survey_event *psurvey_evt;
++	struct rtw_evt_header *evt_hdr;
++	struct mlme_ext_priv *pmlmeext;
++	struct cmd_priv *pcmdpriv;
++	/* u8 *pframe = precv_frame->u.hdr.rx_data; */
++	/* uint len = precv_frame->u.hdr.len; */
++
++	if (!padapter)
++		return;
++
++	pmlmeext = &padapter->mlmeextpriv;
++	pcmdpriv = &padapter->cmdpriv;
++
++	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (pcmd_obj == NULL)
++		return;
++
++	cmdsz = (sizeof(struct survey_event) + sizeof(struct rtw_evt_header));
++	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
++	if (pevtcmd == NULL) {
++		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
++		return;
++	}
++
++	_rtw_init_listhead(&pcmd_obj->list);
++
++	pcmd_obj->cmdcode = CMD_SET_MLME_EVT;
++	pcmd_obj->cmdsz = cmdsz;
++	pcmd_obj->parmbuf = pevtcmd;
++
++	pcmd_obj->rsp = NULL;
++	pcmd_obj->rspsz  = 0;
++
++	evt_hdr = (struct rtw_evt_header *)(pevtcmd);
++	evt_hdr->len = sizeof(struct survey_event);
++	evt_hdr->id = EVT_SURVEY;
++	evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
++
++	psurvey_evt = (struct survey_event *)(pevtcmd + sizeof(struct rtw_evt_header));
++
++	if (collect_bss_info(padapter, precv_frame, (WLAN_BSSID_EX *)&psurvey_evt->bss) == _FAIL) {
++		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
++		rtw_mfree((u8 *)pevtcmd, cmdsz);
++		return;
++	}
++
++	rtw_hidden_ssid_bss_count(padapter, &psurvey_evt->bss);
++
++	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
++
++	pmlmeext->sitesurvey_res.bss_cnt++;
++
++	return;
++
++}
++
++/*
++* @acs: aim to trigger channel selection
++*/
++void report_surveydone_event(_adapter *padapter, bool acs)
++{
++	struct cmd_obj *pcmd_obj;
++	u8	*pevtcmd;
++	u32 cmdsz;
++	struct surveydone_event *psurveydone_evt;
++	struct rtw_evt_header *evt_hdr;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++
++	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (pcmd_obj == NULL)
++		return;
++
++	cmdsz = (sizeof(struct surveydone_event) + sizeof(struct rtw_evt_header));
++	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
++	if (pevtcmd == NULL) {
++		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
++		return;
++	}
++
++	_rtw_init_listhead(&pcmd_obj->list);
++
++	pcmd_obj->cmdcode = CMD_SET_MLME_EVT;
++	pcmd_obj->cmdsz = cmdsz;
++	pcmd_obj->parmbuf = pevtcmd;
++
++	pcmd_obj->rsp = NULL;
++	pcmd_obj->rspsz  = 0;
++
++	evt_hdr = (struct rtw_evt_header *)(pevtcmd);
++	evt_hdr->len = sizeof(struct surveydone_event);
++	evt_hdr->id = EVT_SURVEY_DONE;
++	evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
++
++	psurveydone_evt = (struct surveydone_event *)(pevtcmd + sizeof(struct rtw_evt_header));
++	psurveydone_evt->bss_cnt = pmlmeext->sitesurvey_res.bss_cnt;
++	psurveydone_evt->acs = acs;
++
++	RTW_INFO("survey done event(%x) band:%d for "ADPT_FMT"\n", psurveydone_evt->bss_cnt, padapter->setband, ADPT_ARG(padapter));
++
++	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
++
++	return;
++
++}
++
++u32 report_join_res(_adapter *padapter, int aid_res, u16 status)
++{
++	struct cmd_obj *pcmd_obj;
++	u8	*pevtcmd;
++	u32 cmdsz;
++	struct joinbss_event *pjoinbss_evt;
++	struct rtw_evt_header *evt_hdr;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++	u32 ret = _FAIL;
++
++	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (pcmd_obj == NULL)
++		goto exit;
++
++	cmdsz = (sizeof(struct joinbss_event) + sizeof(struct rtw_evt_header));
++	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
++	if (pevtcmd == NULL) {
++		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
++		goto exit;
++	}
++
++	_rtw_init_listhead(&pcmd_obj->list);
++
++	pcmd_obj->cmdcode = CMD_SET_MLME_EVT;
++	pcmd_obj->cmdsz = cmdsz;
++	pcmd_obj->parmbuf = pevtcmd;
++
++	pcmd_obj->rsp = NULL;
++	pcmd_obj->rspsz  = 0;
++
++	evt_hdr = (struct rtw_evt_header *)(pevtcmd);
++	evt_hdr->len = sizeof(struct joinbss_event);
++	evt_hdr->id = EVT_JOINBSS;
++	evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
++
++	pjoinbss_evt = (struct joinbss_event *)(pevtcmd + sizeof(struct rtw_evt_header));
++	_rtw_memcpy((unsigned char *)(&(pjoinbss_evt->network.network)), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX));
++	pjoinbss_evt->network.join_res = pjoinbss_evt->network.aid = aid_res;
++
++	RTW_INFO("report_join_res(%d, %u)\n", aid_res, status);
++
++
++	rtw_joinbss_event_prehandle(padapter, (u8 *)&pjoinbss_evt->network, status);
++
++
++	ret = rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
++
++exit:
++	return ret;
++}
++
++void report_wmm_edca_update(_adapter *padapter)
++{
++	struct cmd_obj *pcmd_obj;
++	u8 *pevtcmd;
++	u32 cmdsz;
++	struct wmm_event *pwmm_event;
++	struct rtw_evt_header *evt_hdr;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++
++	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (pcmd_obj == NULL)
++		return;
++
++	cmdsz = (sizeof(struct wmm_event) + sizeof(struct rtw_evt_header));
++	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
++	if (pevtcmd == NULL) {
++		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
++		return;
++	}
++
++	_rtw_init_listhead(&pcmd_obj->list);
++
++	pcmd_obj->cmdcode = CMD_SET_MLME_EVT;
++	pcmd_obj->cmdsz = cmdsz;
++	pcmd_obj->parmbuf = pevtcmd;
++
++	pcmd_obj->rsp = NULL;
++	pcmd_obj->rspsz  = 0;
++
++	evt_hdr = (struct rtw_evt_header *)(pevtcmd);
++	evt_hdr->len = sizeof(struct wmm_event);
++	evt_hdr->id = EVT_WMM_UPDATE;
++	evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
++
++	pwmm_event = (struct wmm_event *)(pevtcmd + sizeof(struct rtw_evt_header));
++	pwmm_event->wmm = 0;
++
++	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
++
++	return;
++
++}
++
++u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, bool enqueue, u8 locally_generated)
++{
++	struct cmd_obj *pcmd_obj;
++	u8 *pevtcmd;
++	u32 cmdsz;
++	struct sta_info *psta;
++	int mac_id = -1;
++	struct stadel_event *pdel_sta_evt;
++	struct rtw_evt_header *evt_hdr;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++	u8 res = _SUCCESS;
++
++	/* prepare cmd parameter */
++	cmdsz = (sizeof(struct stadel_event) + sizeof(struct rtw_evt_header));
++	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
++	if (pevtcmd == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	evt_hdr = (struct rtw_evt_header *)(pevtcmd);
++	evt_hdr->len = sizeof(struct stadel_event);
++	evt_hdr->id = EVT_DEL_STA;
++	evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
++
++	pdel_sta_evt = (struct stadel_event *)(pevtcmd + sizeof(struct rtw_evt_header));
++	_rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN);
++	_rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd), (unsigned char *)(&reason), 2);
++	psta = rtw_get_stainfo(&padapter->stapriv, MacAddr);
++	if (psta)
++		mac_id = (int)psta->cmn.mac_id;
++	else
++		mac_id = (-1);
++	pdel_sta_evt->mac_id = mac_id;
++	pdel_sta_evt->locally_generated = locally_generated;
++
++	if (!enqueue) {
++		/* do directly */
++		rtw_stadel_event_callback(padapter, (u8 *)pdel_sta_evt);
++		rtw_mfree(pevtcmd, cmdsz);
++	} else {
++		pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++		if (pcmd_obj == NULL) {
++			rtw_mfree(pevtcmd, cmdsz);
++			res = _FAIL;
++			goto exit;
++		}
++
++		_rtw_init_listhead(&pcmd_obj->list);
++		pcmd_obj->cmdcode = CMD_SET_MLME_EVT;
++		pcmd_obj->cmdsz = cmdsz;
++		pcmd_obj->parmbuf = pevtcmd;
++
++		pcmd_obj->rsp = NULL;
++		pcmd_obj->rspsz  = 0;
++
++		res = rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
++	}
++
++exit:
++
++	RTW_INFO(FUNC_ADPT_FMT" "MAC_FMT" mac_id=%d, enqueue:%d, res:%u\n"
++		, FUNC_ADPT_ARG(padapter), MAC_ARG(MacAddr), mac_id, enqueue, res);
++
++	return res;
++}
++
++void report_add_sta_event(_adapter *padapter, unsigned char *MacAddr)
++{
++	struct cmd_obj *pcmd_obj;
++	u8 *pevtcmd;
++	u32 cmdsz;
++	struct stassoc_event *padd_sta_evt;
++	struct rtw_evt_header *evt_hdr;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++
++	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (pcmd_obj == NULL)
++		return;
++
++	cmdsz = (sizeof(struct stassoc_event) + sizeof(struct rtw_evt_header));
++	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
++	if (pevtcmd == NULL) {
++		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
++		return;
++	}
++
++	_rtw_init_listhead(&pcmd_obj->list);
++
++	pcmd_obj->cmdcode = CMD_SET_MLME_EVT;
++	pcmd_obj->cmdsz = cmdsz;
++	pcmd_obj->parmbuf = pevtcmd;
++
++	pcmd_obj->rsp = NULL;
++	pcmd_obj->rspsz  = 0;
++
++	evt_hdr = (struct rtw_evt_header *)(pevtcmd);
++	evt_hdr->len = sizeof(struct stassoc_event);
++	evt_hdr->id = EVT_ADD_STA;
++	evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
++
++	padd_sta_evt = (struct stassoc_event *)(pevtcmd + sizeof(struct rtw_evt_header));
++	_rtw_memcpy((unsigned char *)(&(padd_sta_evt->macaddr)), MacAddr, ETH_ALEN);
++
++	RTW_INFO("report_add_sta_event: add STA\n");
++
++	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
++
++	return;
++}
++
++
++bool rtw_port_switch_chk(_adapter *adapter)
++{
++	bool switch_needed = _FALSE;
++#ifdef CONFIG_CONCURRENT_MODE
++#ifdef CONFIG_RUNTIME_PORT_SWITCH
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct pwrctrl_priv *pwrctl = dvobj_to_pwrctl(dvobj);
++	_adapter *if_port0 = NULL;
++	_adapter *if_port1 = NULL;
++	struct mlme_ext_info *if_port0_mlmeinfo = NULL;
++	struct mlme_ext_info *if_port1_mlmeinfo = NULL;
++	int i;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		if (get_hw_port(dvobj->padapters[i]) == HW_PORT0) {
++			if_port0 = dvobj->padapters[i];
++			if_port0_mlmeinfo = &(if_port0->mlmeextpriv.mlmext_info);
++		} else if (get_hw_port(dvobj->padapters[i]) == HW_PORT1) {
++			if_port1 = dvobj->padapters[i];
++			if_port1_mlmeinfo = &(if_port1->mlmeextpriv.mlmext_info);
++		}
++	}
++
++	if (if_port0 == NULL) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (if_port1 == NULL) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++#ifdef DBG_RUNTIME_PORT_SWITCH
++	RTW_INFO(FUNC_ADPT_FMT" wowlan_mode:%u\n"
++		 ADPT_FMT", port0, mlmeinfo->state:0x%08x, p2p_state:%d, %d\n"
++		 ADPT_FMT", port1, mlmeinfo->state:0x%08x, p2p_state:%d, %d\n",
++		 FUNC_ADPT_ARG(adapter), pwrctl->wowlan_mode,
++		ADPT_ARG(if_port0), if_port0_mlmeinfo->state, rtw_p2p_state(&if_port0->wdinfo), rtw_p2p_chk_state(&if_port0->wdinfo, P2P_STATE_NONE),
++		ADPT_ARG(if_port1), if_port1_mlmeinfo->state, rtw_p2p_state(&if_port1->wdinfo), rtw_p2p_chk_state(&if_port1->wdinfo, P2P_STATE_NONE));
++#endif /* DBG_RUNTIME_PORT_SWITCH */
++
++#ifdef CONFIG_WOWLAN
++	/* WOWLAN interface(primary, for now) should be port0 */
++	if (pwrctl->wowlan_mode == _TRUE) {
++		if (!is_primary_adapter(if_port0)) {
++			RTW_INFO("%s "ADPT_FMT" enable WOWLAN\n", __func__, ADPT_ARG(if_port1));
++			switch_needed = _TRUE;
++		}
++		goto exit;
++	}
++#endif /* CONFIG_WOWLAN */
++
++	/* AP/Mesh should use port0 for ctl frame's ack */
++	if ((if_port1_mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
++		RTW_INFO("%s "ADPT_FMT" is AP/GO/Mesh\n", __func__, ADPT_ARG(if_port1));
++		switch_needed = _TRUE;
++		goto exit;
++	}
++
++	/* GC should use port0 for p2p ps */
++	if (((if_port1_mlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE)
++	    && (if_port1_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
++#ifdef CONFIG_P2P
++	    && !rtw_p2p_chk_state(&if_port1->wdinfo, P2P_STATE_NONE)
++#endif
++	    && !check_fwstate(&if_port1->mlmepriv, WIFI_UNDER_WPS)
++	   ) {
++		RTW_INFO("%s "ADPT_FMT" is GC\n", __func__, ADPT_ARG(if_port1));
++		switch_needed = _TRUE;
++		goto exit;
++	}
++
++	/* port1 linked, but port0 not linked */
++	if ((if_port1_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
++	    && !(if_port0_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
++	    && ((if_port0_mlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
++	   ) {
++		RTW_INFO("%s "ADPT_FMT" is SINGLE_LINK\n", __func__, ADPT_ARG(if_port1));
++		switch_needed = _TRUE;
++		goto exit;
++	}
++
++exit:
++#ifdef DBG_RUNTIME_PORT_SWITCH
++	RTW_INFO(FUNC_ADPT_FMT" ret:%d\n", FUNC_ADPT_ARG(adapter), switch_needed);
++#endif /* DBG_RUNTIME_PORT_SWITCH */
++#endif /* CONFIG_RUNTIME_PORT_SWITCH */
++#endif /* CONFIG_CONCURRENT_MODE */
++	return switch_needed;
++}
++
++/****************************************************************************
++
++Following are the event callback functions
++
++*****************************************************************************/
++
++/* for sta/adhoc mode */
++void update_sta_info(_adapter *padapter, struct sta_info *psta)
++{
++	_irqL	irqL;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	/* ERP */
++	VCS_update(padapter, psta);
++
++#ifdef CONFIG_80211N_HT
++	/* HT */
++	if (pmlmepriv->htpriv.ht_option) {
++		psta->htpriv.ht_option = _TRUE;
++
++		psta->htpriv.ampdu_enable = pmlmepriv->htpriv.ampdu_enable;
++
++		psta->htpriv.rx_ampdu_min_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & IEEE80211_HT_CAP_AMPDU_DENSITY) >> 2;
++
++		if (support_short_GI(padapter, &(pmlmeinfo->HT_caps), CHANNEL_WIDTH_20))
++			psta->htpriv.sgi_20m = _TRUE;
++
++		if (support_short_GI(padapter, &(pmlmeinfo->HT_caps), CHANNEL_WIDTH_40))
++			psta->htpriv.sgi_40m = _TRUE;
++
++		psta->qos_option = _TRUE;
++
++		psta->htpriv.ldpc_cap = pmlmepriv->htpriv.ldpc_cap;
++		psta->htpriv.stbc_cap = pmlmepriv->htpriv.stbc_cap;
++		psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap;
++
++		_rtw_memcpy(&psta->htpriv.ht_cap, &pmlmeinfo->HT_caps, sizeof(struct rtw_ieee80211_ht_cap));
++		#ifdef CONFIG_BEAMFORMING
++		psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap;
++		psta->cmn.bf_info.ht_beamform_cap = pmlmepriv->htpriv.beamform_cap;
++		#endif
++	} else
++#endif /* CONFIG_80211N_HT */
++	{
++#ifdef CONFIG_80211N_HT
++		psta->htpriv.ht_option = _FALSE;
++		psta->htpriv.ampdu_enable = _FALSE;
++		psta->htpriv.tx_amsdu_enable = _FALSE;
++		psta->htpriv.sgi_20m = _FALSE;
++		psta->htpriv.sgi_40m = _FALSE;
++#endif /* CONFIG_80211N_HT */
++		psta->qos_option = _FALSE;
++
++	}
++
++#ifdef CONFIG_80211N_HT
++	psta->htpriv.ch_offset = pmlmeext->cur_ch_offset;
++
++	psta->htpriv.agg_enable_bitmap = 0x0;/* reset */
++	psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */
++#endif /* CONFIG_80211N_HT */
++
++	psta->cmn.bw_mode = pmlmeext->cur_bwmode;
++
++	/* QoS */
++	if (pmlmepriv->qospriv.qos_option)
++		psta->qos_option = _TRUE;
++
++#ifdef CONFIG_80211AC_VHT
++	_rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv));
++	if (psta->vhtpriv.vht_option) {
++		psta->cmn.ra_info.is_vht_enable = _TRUE;
++		#ifdef CONFIG_BEAMFORMING
++		psta->vhtpriv.beamform_cap = pmlmepriv->vhtpriv.beamform_cap;
++		psta->cmn.bf_info.vht_beamform_cap = pmlmepriv->vhtpriv.beamform_cap;
++		#endif /*CONFIG_BEAMFORMING*/
++	}
++#endif /* CONFIG_80211AC_VHT */
++	psta->cmn.ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta));
++	update_ldpc_stbc_cap(psta);
++
++	_enter_critical_bh(&psta->lock, &irqL);
++	psta->state = WIFI_ASOC_STATE;
++	_exit_critical_bh(&psta->lock, &irqL);
++
++}
++
++static void rtw_mlmeext_disconnect(_adapter *padapter)
++{
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8 self_action = MLME_ACTION_UNKNOWN;
++	u8 state_backup = (pmlmeinfo->state & 0x03);
++	u8 ASIX_ID[] = {0x00, 0x0E, 0xC6};
++
++	if (MLME_IS_AP(padapter))
++		self_action = MLME_AP_STOPPED;
++	else if (MLME_IS_MESH(padapter))
++		self_action = MLME_MESH_STOPPED;
++	else if (MLME_IS_STA(padapter))
++		self_action = MLME_STA_DISCONNECTED;
++	else if (MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter))
++		self_action = MLME_ADHOC_STOPPED;
++	else {
++		RTW_INFO("state:0x%x\n", MLME_STATE(padapter));
++		rtw_warn_on(1);
++	}
++
++	/* set_opmode_cmd(padapter, infra_client_with_mlme); */
++#ifdef CONFIG_HW_P0_TSF_SYNC
++	if (self_action == MLME_STA_DISCONNECTED)
++		correct_TSF(padapter, self_action);
++#endif
++	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0);
++	rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr);
++	if (self_action == MLME_STA_DISCONNECTED)
++		rtw_hal_rcr_set_chk_bssid(padapter, self_action);
++
++	/* set MSR to no link state->infra. mode */
++	Set_MSR(padapter, _HW_STATE_STATION_);
++
++	/* check if sta is ASIX peer and fix IOT issue if it is. */
++	if (_rtw_memcmp(get_my_bssid(&pmlmeinfo->network) , ASIX_ID , 3)) {
++		u8 iot_flag = _FALSE;
++		rtw_hal_set_hwreg(padapter, HW_VAR_ASIX_IOT, (u8 *)(&iot_flag));
++	}
++	pmlmeinfo->state = WIFI_FW_NULL_STATE;
++
++#ifdef CONFIG_MCC_MODE
++	/* mcc disconnect setting before download LPS rsvd page */
++	rtw_hal_set_mcc_setting_disconnect(padapter);
++#endif /* CONFIG_MCC_MODE */
++
++	if (state_backup == WIFI_FW_STATION_STATE) {
++		if (rtw_port_switch_chk(padapter) == _TRUE) {
++			rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);
++#ifdef CONFIG_LPS
++			{
++				_adapter *port0_iface = dvobj_get_port0_adapter(adapter_to_dvobj(padapter));
++				if (port0_iface)
++					rtw_lps_ctrl_wk_cmd(port0_iface, LPS_CTRL_CONNECT, RTW_CMDF_DIRECTLY);
++			}
++#endif
++		}
++	}
++
++	/* switch to the 20M Hz mode after disconnect */
++	pmlmeext->cur_bwmode = CHANNEL_WIDTH_20;
++	pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++#ifdef CONFIG_CTRL_TXSS_BY_TP
++	pmlmeext->txss_1ss = _FALSE;
++#endif
++
++#ifdef CONFIG_FCS_MODE
++	if (EN_FCS(padapter))
++		rtw_hal_set_hwreg(padapter, HW_VAR_STOP_FCS_MODE, NULL);
++#endif
++
++	if (!(MLME_IS_STA(padapter) && MLME_IS_OPCH_SW(padapter))) {
++		/* DFS and channel status no need to check here for STA under OPCH_SW */
++		u8 ch, bw, offset;
++
++		#ifdef CONFIG_DFS_MASTER
++		rtw_dfs_rd_en_decision(padapter, self_action, 0);
++		#endif
++
++		if (rtw_mi_get_ch_setting_union_no_self(padapter, &ch, &bw, &offset) != 0) {
++			set_channel_bwmode(padapter, ch, offset, bw);
++			rtw_mi_update_union_chan_inf(padapter, ch, offset, bw);
++		}
++	}
++
++	flush_all_cam_entry(padapter);
++
++	_cancel_timer_ex(&pmlmeext->link_timer);
++
++	/* pmlmepriv->LinkDetectInfo.TrafficBusyState = _FALSE; */
++	pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0;
++	pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0;
++
++#ifdef CONFIG_TDLS
++	padapter->tdlsinfo.ap_prohibited = _FALSE;
++
++	/* For TDLS channel switch, currently we only allow it to work in wifi logo test mode */
++	if (padapter->registrypriv.wifi_spec == 1)
++		padapter->tdlsinfo.ch_switch_prohibited = _FALSE;
++#endif /* CONFIG_TDLS */
++
++#ifdef CONFIG_WMMPS_STA
++	 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
++		/* reset currently related uapsd setting when the connection has broken */
++		pmlmepriv->qospriv.uapsd_max_sp_len = 0;
++		pmlmepriv->qospriv.uapsd_tid = 0;
++		pmlmepriv->qospriv.uapsd_tid_delivery_enabled = 0;
++		pmlmepriv->qospriv.uapsd_tid_trigger_enabled = 0;
++		pmlmepriv->qospriv.uapsd_ap_supported = 0;
++	}
++#endif /* CONFIG_WMMPS_STA */
++#ifdef CONFIG_RTS_FULL_BW
++	rtw_set_rts_bw(padapter);
++#endif/*CONFIG_RTS_FULL_BW*/
++
++}
++
++void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res)
++{
++	struct sta_info		*psta;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
++	struct sta_priv		*pstapriv = &padapter->stapriv;
++	u8	join_type;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++
++#ifndef CONFIG_IOCTL_CFG80211
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++#endif
++
++	if (pmlmepriv->wpa_phase == _TRUE)
++		pmlmepriv->wpa_phase = _FALSE;
++
++	if (join_res < 0) {
++		join_type = 1;
++		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
++		rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr);
++		if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE)
++			rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_DISCONNECTED);
++
++		rtw_btcoex_connect_notify(padapter, join_type);
++
++		goto exit_mlmeext_joinbss_event_callback;
++	}
++
++#ifdef CONFIG_ARP_KEEP_ALIVE
++	pmlmepriv->bGetGateway = 1;
++	pmlmepriv->GetGatewayTryCnt = 0;
++#endif
++
++	if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
++		/* update bc/mc sta_info */
++		update_bmc_sta(padapter);
++	}
++
++
++	/* turn on dynamic functions */
++	/* Switch_DM_Func(padapter, DYNAMIC_ALL_FUNC_ENABLE, _TRUE); */
++
++	/* update IOT-releated issue */
++	update_IOT_info(padapter);
++
++	#ifdef CONFIG_RTS_FULL_BW
++	rtw_set_rts_bw(padapter);
++	#endif/*CONFIG_RTS_FULL_BW*/
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, cur_network->SupportedRates);
++
++	/* BCN interval */
++	rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pmlmeinfo->bcn_interval));
++
++	/* udpate capability */
++	update_capinfo(padapter, pmlmeinfo->capability);
++
++	/* WMM, Update EDCA param */
++	WMMOnAssocRsp(padapter);
++#ifdef CONFIG_80211N_HT
++	/* HT */
++	HTOnAssocRsp(padapter);
++#endif /* CONFIG_80211N_HT */
++#ifdef CONFIG_80211AC_VHT
++	/* VHT */
++	VHTOnAssocRsp(padapter);
++#endif
++
++	psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
++	if (psta) { /* only for infra. mode */
++		psta->wireless_mode = pmlmeext->cur_wireless_mode;
++
++		/* set per sta rate after updating HT cap. */
++		set_sta_rate(padapter, psta);
++
++		rtw_sta_media_status_rpt(padapter, psta, 1);
++
++		/* wakeup macid after join bss successfully to ensure
++			the subsequent data frames can be sent out normally */
++		rtw_hal_macid_wakeup(padapter, psta->cmn.mac_id);
++
++		rtw_xmit_queue_clear(psta);
++	}
++
++#ifndef CONFIG_IOCTL_CFG80211
++	if (is_wep_enc(psecuritypriv->dot11PrivacyAlgrthm))
++		rtw_sec_restore_wep_key(padapter);
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++	if (rtw_port_switch_chk(padapter) == _TRUE)
++		rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);
++
++	join_type = 2;
++	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
++
++	if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) {
++		rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTED);
++
++		/* correcting TSF */
++		correct_TSF(padapter, MLME_STA_CONNECTED);
++
++		/* set_link_timer(pmlmeext, DISCONNECT_TO); */
++	}
++
++#ifdef CONFIG_LPS
++	#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
++	if (get_hw_port(padapter) == HW_PORT0)
++	#endif
++		rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_CONNECT, RTW_CMDF_DIRECTLY);
++#endif
++
++	rtw_btcoex_connect_notify(padapter, join_type);
++
++#ifdef CONFIG_BEAMFORMING
++	if (psta)
++		beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_ENTER, (u8 *)psta, sizeof(struct sta_info), 0);
++#endif/*CONFIG_BEAMFORMING*/
++
++exit_mlmeext_joinbss_event_callback:
++
++	rtw_join_done_chk_ch(padapter, join_res);
++#ifdef CONFIG_RTW_REPEATER_SON
++	rtw_rson_join_done(padapter);
++#endif
++
++	RTW_INFO("=>%s - End to Connection without 4-way\n", __FUNCTION__);
++}
++
++/* currently only adhoc mode will go here */
++void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta)
++{
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8	join_type;
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
++		if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { /* adhoc master or sta_count>1 */
++			/* nothing to do */
++		} else { /* adhoc client */
++			/* update TSF Value */
++			/* update_TSF(pmlmeext, pframe, len);			 */
++
++			/* correcting TSF */
++			correct_TSF(padapter, MLME_ADHOC_STARTED);
++
++			/* start beacon */
++			if (send_beacon(padapter) == _FAIL)
++				rtw_warn_on(1);
++
++			pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
++		}
++
++		join_type = 2;
++		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
++
++		rtw_btcoex_connect_notify(padapter, join_type);
++	}
++
++	/* update adhoc sta_info */
++	update_sta_info(padapter, psta);
++
++	rtw_hal_update_sta_ra_info(padapter, psta);
++
++	/* ToDo: HT for Ad-hoc */
++	psta->wireless_mode = rtw_check_network_type(psta->bssrateset, psta->bssratelen, pmlmeext->cur_channel);
++	rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);
++
++	/* rate radaptive */
++	Update_RA_Entry(padapter, psta);
++}
++
++void mlmeext_sta_del_event_callback(_adapter *padapter)
++{
++	if (is_client_associated_to_ap(padapter) || is_IBSS_empty(padapter))
++		rtw_mlmeext_disconnect(padapter);
++}
++
++/****************************************************************************
++
++Following are the functions for the timer handlers
++
++*****************************************************************************/
++void _linked_info_dump(_adapter *padapter)
++{
++	if (padapter->bLinkInfoDump) {
++		rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, RTW_DBGDUMP);
++		rtw_hal_set_odm_var(padapter, HAL_ODM_RX_INFO_DUMP, RTW_DBGDUMP, _FALSE);
++	}
++}
++/********************************************************************
++
++When station does not receive any packet in MAX_CONTINUAL_NORXPACKET_COUNT*2 seconds,
++recipient station will teardown the block ack by issuing DELBA frame.
++
++*********************************************************************/
++void rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer)
++{
++	int	i = 0;
++	int ret = _SUCCESS;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	/*
++		IOT issue,occur Broadcom ap(Buffalo WZR-D1800H,Netgear R6300).
++		AP is originator.AP does not transmit unicast packets when STA response its BAR.
++		This case probably occur ap issue BAR after AP builds BA.
++
++		Follow 802.11 spec, STA shall maintain an inactivity timer for every negotiated Block Ack setup.
++		The inactivity timer is not reset when MPDUs corresponding to other TIDs are received.
++	*/
++	if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) {
++		for (i = 0; i < TID_NUM ; i++) {
++			if ((psta->recvreorder_ctrl[i].enable) && 
++                        (sta_rx_data_qos_pkts(psta, i) == sta_last_rx_data_qos_pkts(psta, i)) ) {			
++					if (_TRUE == rtw_inc_and_chk_continual_no_rx_packet(psta, i)) {					
++						/* send a DELBA frame to the peer STA with the Reason Code field set to TIMEOUT */
++						if (!from_timer)
++							ret = issue_del_ba_ex(padapter, psta->cmn.mac_addr, i, 39, 0, 3, 1);
++						else
++							issue_del_ba(padapter,  psta->cmn.mac_addr, i, 39, 0);
++						psta->recvreorder_ctrl[i].enable = _FALSE;
++						if (ret != _FAIL)
++							psta->recvreorder_ctrl[i].ampdu_size = RX_AMPDU_SIZE_INVALID;
++						rtw_reset_continual_no_rx_packet(psta, i);
++					}				
++			} else {
++				/* The inactivity timer is reset when MPDUs to the TID is received. */
++				rtw_reset_continual_no_rx_packet(psta, i);
++			}
++		}
++	}
++}
++
++u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta)
++{
++	u8 ret = _FALSE;
++#ifdef DBG_EXPIRATION_CHK
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	RTW_INFO(FUNC_ADPT_FMT" rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu"
++		/*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/
++		 ", retry:%u\n"
++		 , FUNC_ADPT_ARG(padapter)
++		 , STA_RX_PKTS_DIFF_ARG(psta)
++		, psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts
++		, psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts
++		/*, psta->sta_stats.rx_probersp_bm_pkts - psta->sta_stats.last_rx_probersp_bm_pkts
++		, psta->sta_stats.rx_probersp_uo_pkts - psta->sta_stats.last_rx_probersp_uo_pkts
++		, psta->sta_stats.rx_probereq_pkts - psta->sta_stats.last_rx_probereq_pkts
++		 , pmlmeinfo->bcn_interval*/
++		 , pmlmeext->retry
++		);
++
++	RTW_INFO(FUNC_ADPT_FMT" tx_pkts:%llu, link_count:%u\n", FUNC_ADPT_ARG(padapter)
++		 , sta_tx_pkts(psta)
++		 , pmlmeinfo->link_count
++		);
++#endif
++
++	if ((sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta))
++	    && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta)
++	    && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta)
++	   )
++		ret = _FALSE;
++	else
++		ret = _TRUE;
++
++	sta_update_last_rx_pkts(psta);
++
++	return ret;
++}
++
++u8 chk_adhoc_peer_is_alive(struct sta_info *psta)
++{
++	u8 ret = _TRUE;
++
++#ifdef DBG_EXPIRATION_CHK
++	RTW_INFO("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu"
++		/*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/
++		 ", expire_to:%u\n"
++		 , MAC_ARG(psta->cmn.mac_addr)
++		 , psta->cmn.rssi_stat.rssi
++		 , STA_RX_PKTS_DIFF_ARG(psta)
++		, psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts
++		, psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts
++		/*, psta->sta_stats.rx_probersp_bm_pkts - psta->sta_stats.last_rx_probersp_bm_pkts
++		, psta->sta_stats.rx_probersp_uo_pkts - psta->sta_stats.last_rx_probersp_uo_pkts
++		, psta->sta_stats.rx_probereq_pkts - psta->sta_stats.last_rx_probereq_pkts
++		 , pmlmeinfo->bcn_interval*/
++		 , psta->expire_to
++		);
++#endif
++
++	if (sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta)
++	    && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta)
++	    && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta))
++		ret = _FALSE;
++
++	sta_update_last_rx_pkts(psta);
++
++	return ret;
++}
++
++#ifdef CONFIG_TDLS
++u8 chk_tdls_peer_sta_is_alive(_adapter *padapter, struct sta_info *psta)
++{
++	if ((psta->sta_stats.rx_data_pkts == psta->sta_stats.last_rx_data_pkts)
++	    && (psta->sta_stats.rx_tdls_disc_rsp_pkts == psta->sta_stats.last_rx_tdls_disc_rsp_pkts))
++		return _FALSE;
++
++	return _TRUE;
++}
++
++void linked_status_chk_tdls(_adapter *padapter)
++{
++	struct candidate_pool {
++		struct sta_info *psta;
++		u8 addr[ETH_ALEN];
++	};
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	_irqL irqL;
++	u8 ack_chk;
++	struct sta_info *psta;
++	int i, num_teardown = 0, num_checkalive = 0;
++	_list	*plist, *phead;
++	struct tdls_txmgmt txmgmt;
++	struct candidate_pool checkalive[MAX_ALLOWED_TDLS_STA_NUM];
++	struct candidate_pool teardown[MAX_ALLOWED_TDLS_STA_NUM];
++	u8 tdls_sta_max = _FALSE;
++
++#define ALIVE_MIN 2
++#define ALIVE_MAX 5
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++	_rtw_memset(checkalive, 0x00, sizeof(checkalive));
++	_rtw_memset(teardown, 0x00, sizeof(teardown));
++
++	if ((padapter->tdlsinfo.link_established == _TRUE)) {
++		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++		for (i = 0; i < NUM_STA; i++) {
++			phead = &(pstapriv->sta_hash[i]);
++			plist = get_next(phead);
++
++			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++				plist = get_next(plist);
++
++				if (psta->tdls_sta_state & TDLS_LINKED_STATE) {
++					psta->alive_count++;
++					if (psta->alive_count >= ALIVE_MIN) {
++						if (chk_tdls_peer_sta_is_alive(padapter, psta) == _FALSE) {
++							if (psta->alive_count < ALIVE_MAX) {
++								_rtw_memcpy(checkalive[num_checkalive].addr, psta->cmn.mac_addr, ETH_ALEN);
++								checkalive[num_checkalive].psta = psta;
++								num_checkalive++;
++							} else {
++								_rtw_memcpy(teardown[num_teardown].addr, psta->cmn.mac_addr, ETH_ALEN);
++								teardown[num_teardown].psta = psta;
++								num_teardown++;
++							}
++						} else
++							psta->alive_count = 0;
++					}
++					psta->sta_stats.last_rx_data_pkts = psta->sta_stats.rx_data_pkts;
++					psta->sta_stats.last_rx_tdls_disc_rsp_pkts = psta->sta_stats.rx_tdls_disc_rsp_pkts;
++
++					if ((num_checkalive >= MAX_ALLOWED_TDLS_STA_NUM) || (num_teardown >= MAX_ALLOWED_TDLS_STA_NUM)) {
++						tdls_sta_max = _TRUE;
++						break;
++					}
++				}
++			}
++
++			if (tdls_sta_max == _TRUE)
++				break;
++		}
++		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++		if (num_checkalive > 0) {
++			for (i = 0; i < num_checkalive; i++) {
++				_rtw_memcpy(txmgmt.peer, checkalive[i].addr, ETH_ALEN);
++				issue_tdls_dis_req(padapter, &txmgmt);
++				issue_tdls_dis_req(padapter, &txmgmt);
++				issue_tdls_dis_req(padapter, &txmgmt);
++			}
++		}
++
++		if (num_teardown > 0) {
++			for (i = 0; i < num_teardown; i++) {
++				RTW_INFO("[%s %d] Send teardown to "MAC_FMT"\n", __FUNCTION__, __LINE__, MAC_ARG(teardown[i].addr));
++				txmgmt.status_code = _RSON_TDLS_TEAR_TOOFAR_;
++				_rtw_memcpy(txmgmt.peer, teardown[i].addr, ETH_ALEN);
++				issue_tdls_teardown(padapter, &txmgmt, _FALSE);
++			}
++		}
++	}
++
++}
++#endif /* CONFIG_TDLS */
++
++inline int rtw_get_rx_chk_limit(_adapter *adapter)
++{
++	return adapter->stapriv.rx_chk_limit;
++}
++
++inline void rtw_set_rx_chk_limit(_adapter *adapter, int limit)
++{
++	adapter->stapriv.rx_chk_limit = limit;
++}
++
++/* from_timer == 1 means driver is in LPS */
++void linked_status_chk(_adapter *padapter, u8 from_timer)
++{
++	u32	i;
++	struct sta_info		*psta;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct sta_priv		*pstapriv = &padapter->stapriv;
++#if defined(CONFIG_ARP_KEEP_ALIVE) || defined(CONFIG_LAYER2_ROAMING)
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++#endif
++#ifdef CONFIG_LAYER2_ROAMING
++	struct recv_priv	*precvpriv = &padapter->recvpriv;
++#endif
++
++	if (padapter->registrypriv.mp_mode == _TRUE)
++		return;
++
++	if (is_client_associated_to_ap(padapter)) {
++		/* linked infrastructure client mode */
++
++		int tx_chk = _SUCCESS, rx_chk = _SUCCESS;
++		int rx_chk_limit;
++		int link_count_limit;
++
++#if defined(CONFIG_RTW_REPEATER_SON)
++	rtw_rson_scan_wk_cmd(padapter, RSON_SCAN_PROCESS);
++#elif defined(CONFIG_LAYER2_ROAMING)
++		if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) {
++			RTW_INFO("signal_strength_data.avg_val = %d\n", precvpriv->signal_strength_data.avg_val);
++			if ((precvpriv->signal_strength_data.avg_val < pmlmepriv->roam_rssi_threshold)
++				&& (rtw_get_passing_time_ms(pmlmepriv->last_roaming) >= pmlmepriv->roam_scan_int*2000)) {
++#ifdef CONFIG_RTW_80211K
++				rtw_roam_nb_discover(padapter, _FALSE);
++#endif
++				pmlmepriv->need_to_roam = _TRUE;
++				rtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM);
++				pmlmepriv->last_roaming = rtw_get_current_time();
++			} else
++				pmlmepriv->need_to_roam = _FALSE;
++		}
++#endif
++#ifdef CONFIG_MCC_MODE
++		/*
++		 * due to tx ps null date to ao, so ap doest not tx pkt to driver
++		 * we may check chk_ap_is_alive fail, and may issue_probereq to wrong channel under sitesurvey
++		 * don't keep alive check under MCC
++		 */
++		if (rtw_hal_mcc_link_status_chk(padapter, __func__) == _FALSE)
++			return;
++#endif
++
++		rx_chk_limit = rtw_get_rx_chk_limit(padapter);
++
++#ifdef CONFIG_ARP_KEEP_ALIVE
++		if (!from_timer && pmlmepriv->bGetGateway == 1 && pmlmepriv->GetGatewayTryCnt < 3) {
++			RTW_INFO("do rtw_gw_addr_query() : %d\n", pmlmepriv->GetGatewayTryCnt);
++			pmlmepriv->GetGatewayTryCnt++;
++			if (rtw_gw_addr_query(padapter) == 0)
++				pmlmepriv->bGetGateway = 0;
++			else {
++				_rtw_memset(pmlmepriv->gw_ip, 0, 4);
++				_rtw_memset(pmlmepriv->gw_mac_addr, 0, ETH_ALEN);
++			}
++		}
++#endif
++#ifdef CONFIG_P2P
++		if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) {
++			if (!from_timer)
++				link_count_limit = 3; /* 8 sec */
++			else
++				link_count_limit = 15; /* 32 sec */
++		} else
++#endif /* CONFIG_P2P */
++		{
++			if (!from_timer)
++				link_count_limit = 7; /* 16 sec */
++			else
++				link_count_limit = 29; /* 60 sec */
++		}
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_TDLS_CH_SW
++		if (ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on) == _TRUE)
++			return;
++#endif /* CONFIG_TDLS_CH_SW */
++
++#ifdef CONFIG_TDLS_AUTOCHECKALIVE
++		linked_status_chk_tdls(padapter);
++#endif /* CONFIG_TDLS_AUTOCHECKALIVE */
++#endif /* CONFIG_TDLS */
++
++		psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
++		if (psta != NULL) {
++			bool is_p2p_enable = _FALSE;
++#ifdef CONFIG_P2P
++			is_p2p_enable = !rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE);
++#endif
++
++#ifdef CONFIG_ISSUE_DELBA_WHEN_NO_TRAFFIC 
++			/*issue delba when ap does not tx data packet that is Broadcom ap */
++			rtw_delba_check(padapter, psta, from_timer);
++#endif
++			if (chk_ap_is_alive(padapter, psta) == _FALSE)
++				rx_chk = _FAIL;
++
++			if (sta_last_tx_pkts(psta) == sta_tx_pkts(psta))
++				tx_chk = _FAIL;
++
++#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++			if (!from_timer && pmlmeext->active_keep_alive_check && (rx_chk == _FAIL || tx_chk == _FAIL)
++			) {
++				u8 backup_ch = 0, backup_bw = 0, backup_offset = 0;
++				u8 union_ch = 0, union_bw = 0, union_offset = 0;
++				u8 switch_channel_by_drv = _TRUE;
++
++				
++#ifdef CONFIG_MCC_MODE
++				if (MCC_EN(padapter)) {
++					/* driver doesn't switch channel under MCC */
++					if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
++						switch_channel_by_drv = _FALSE;
++				}
++#endif
++				if (switch_channel_by_drv) {
++					if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset)
++						|| pmlmeext->cur_channel != union_ch)
++							goto bypass_active_keep_alive;
++
++					/* switch to correct channel of current network  before issue keep-alive frames */
++					if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) {
++						backup_ch = rtw_get_oper_ch(padapter);
++						backup_bw = rtw_get_oper_bw(padapter);
++						backup_offset = rtw_get_oper_choffset(padapter);
++						set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
++					}
++				}
++
++				if (rx_chk != _SUCCESS)
++					issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, psta->cmn.mac_addr, 0, 0, 3, 1);
++
++				if ((tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit) || rx_chk != _SUCCESS) {
++					if (rtw_mi_check_fwstate(padapter, WIFI_UNDER_SURVEY))
++						tx_chk = issue_nulldata(padapter, psta->cmn.mac_addr, 1, 3, 1);
++					else
++						tx_chk = issue_nulldata(padapter, psta->cmn.mac_addr, 0, 3, 1);
++					/* if tx acked and p2p disabled, set rx_chk _SUCCESS to reset retry count */
++					if (tx_chk == _SUCCESS && !is_p2p_enable)
++						rx_chk = _SUCCESS;
++				}
++
++				/* back to the original operation channel */
++				if (backup_ch > 0 && switch_channel_by_drv)
++					set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw);
++
++bypass_active_keep_alive:
++				;
++			} else
++#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
++			{
++				if (rx_chk != _SUCCESS) {
++					if (pmlmeext->retry == 0) {
++#ifdef DBG_EXPIRATION_CHK
++						RTW_INFO("issue_probereq to trigger probersp, retry=%d\n", pmlmeext->retry);
++#endif
++						issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1));
++						issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1));
++						issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1));
++					}
++				}
++
++				if (tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit
++#ifdef CONFIG_MCC_MODE
++				    /* FW tx nulldata under MCC mode, we just check  ap is alive */
++				    && (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC))
++#endif /* CONFIG_MCC_MODE */
++				) {
++					#ifdef DBG_EXPIRATION_CHK
++					RTW_INFO("%s issue_nulldata(%d)\n", __FUNCTION__, from_timer ? 1 : 0);
++					#endif
++					if (from_timer || rtw_mi_check_fwstate(padapter, WIFI_UNDER_SURVEY))
++						tx_chk = issue_nulldata(padapter, NULL, 1, 0, 0);
++					else
++						tx_chk = issue_nulldata(padapter, NULL, 0, 1, 1);
++				}
++			}
++
++			if (rx_chk == _FAIL) {
++				pmlmeext->retry++;
++				if (pmlmeext->retry > rx_chk_limit) {
++					RTW_PRINT(FUNC_ADPT_FMT" disconnect or roaming\n",
++						  FUNC_ADPT_ARG(padapter));
++					receive_disconnect(padapter, pmlmeinfo->network.MacAddress
++						, WLAN_REASON_EXPIRATION_CHK, _FALSE);
++					return;
++				}
++			} else
++				pmlmeext->retry = 0;
++
++			if (tx_chk == _FAIL)
++				pmlmeinfo->link_count %= (link_count_limit + 1);
++			else {
++				psta->sta_stats.last_tx_pkts = psta->sta_stats.tx_pkts;
++				pmlmeinfo->link_count = 0;
++			}
++
++		} /* end of if ((psta = rtw_get_stainfo(pstapriv, passoc_res->network.MacAddress)) != NULL) */
++
++	} else if (is_client_associated_to_ibss(padapter)) {
++		_irqL irqL;
++		_list *phead, *plist, dlist;
++
++		_rtw_init_listhead(&dlist);
++
++		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++		for (i = 0; i < NUM_STA; i++) {
++
++			phead = &(pstapriv->sta_hash[i]);
++			plist = get_next(phead);
++			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++				plist = get_next(plist);
++
++				if (is_broadcast_mac_addr(psta->cmn.mac_addr))
++					continue;
++
++				if (chk_adhoc_peer_is_alive(psta) || !psta->expire_to)
++					psta->expire_to = pstapriv->adhoc_expire_to;
++				else
++					psta->expire_to--;
++
++				if (psta->expire_to <= 0) {
++					rtw_list_delete(&psta->list);
++					rtw_list_insert_tail(&psta->list, &dlist);
++				}
++			}
++		}
++
++		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++		plist = get_next(&dlist);
++		while (rtw_end_of_queue_search(&dlist, plist) == _FALSE) {
++			psta = LIST_CONTAINOR(plist, struct sta_info, list);
++			plist = get_next(plist);
++			rtw_list_delete(&psta->list);
++			RTW_INFO(FUNC_ADPT_FMT" ibss expire "MAC_FMT"\n"
++				, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
++			report_del_sta_event(padapter, psta->cmn.mac_addr, WLAN_REASON_EXPIRATION_CHK, from_timer ? _TRUE : _FALSE, _FALSE);
++		}
++	}
++
++}
++
++void survey_timer_hdl(void *ctx)
++{
++	_adapter *padapter = (_adapter *)ctx;
++	struct cmd_obj *cmd;
++	struct sitesurvey_parm *psurveyPara;
++	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++	if (mlmeext_scan_state(pmlmeext) > SCAN_DISABLE) {
++		cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++		if (cmd == NULL) {
++			rtw_warn_on(1);
++			goto exit;
++		}
++
++		psurveyPara = (struct sitesurvey_parm *)rtw_zmalloc(sizeof(struct sitesurvey_parm));
++		if (psurveyPara == NULL) {
++			rtw_warn_on(1);
++			rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj));
++			goto exit;
++		}
++
++		init_h2fwcmd_w_parm_no_rsp(cmd, psurveyPara, CMD_SITE_SURVEY);
++		rtw_enqueue_cmd(pcmdpriv, cmd);
++	}
++
++exit:
++	return;
++}
++
++#ifdef CONFIG_RTW_REPEATER_SON
++/*	 100ms pass, stop rson_scan	*/
++void rson_timer_hdl(void *ctx)
++{
++	_adapter *padapter = (_adapter *)ctx;
++
++	rtw_rson_scan_wk_cmd(padapter, RSON_SCAN_DISABLE);
++}
++
++#endif
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++void rtw_tbtx_xmit_timer_hdl(void *ctx)
++{
++	_adapter *padapter = (_adapter *)ctx;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++
++	if (ATOMIC_READ(&padapter->tbtx_remove_tx_pause) == _TRUE){
++		ATOMIC_SET(&padapter->tbtx_tx_pause, _FALSE);
++		rtw_tx_control_cmd(padapter);
++	}else {
++		rtw_issue_action_token_rel(padapter);
++		ATOMIC_SET(&padapter->tbtx_tx_pause, _TRUE);
++		rtw_tx_control_cmd(padapter);
++		_set_timer(&pmlmeext->tbtx_xmit_timer, MAX_TXPAUSE_DURATION);
++		ATOMIC_SET(&padapter->tbtx_remove_tx_pause, _TRUE);
++	}
++}
++
++#ifdef CONFIG_AP_MODE
++void rtw_tbtx_token_dispatch_timer_hdl(void *ctx)
++{
++	_adapter *padapter = (_adapter *)ctx;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	_irqL irqL;
++	struct sta_info *psta = NULL;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	_list *phead, *plist;
++	int i, found = _FALSE;
++	u8 nr_send, th_idx = 0;
++
++	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++	RTW_DBG("%s:asoc_cnt: %d\n",__func__, pstapriv->tbtx_asoc_list_cnt);
++
++	// check number of TBTX sta
++	if (padapter->stapriv.tbtx_asoc_list_cnt < 2)
++		goto exit;
++
++	// dispatch token
++	
++	nr_send = RTW_DIV_ROUND_UP(pstapriv->tbtx_asoc_list_cnt, NR_TBTX_SLOT);
++
++	phead = &pstapriv->asoc_list;
++	plist = get_next(phead);
++	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++		/* psta is supporting TBTX */
++		if ((!psta) || (!psta->tbtx_enable))
++			RTW_DBG("sta tbtx_enable is false\n");
++		else {
++			for (i = 0; i < nr_send; i++) {
++				if (pstapriv->last_token_holder == psta) {
++					found = _TRUE;
++					goto outof_loop;
++				}
++			}
++		}
++		plist = get_next(plist);
++	}
++outof_loop:
++	
++	RTW_DBG("rtw_tbtx_token_dispatch_timer_hdl()   th_idx=%d,  nr_send=%d, phead=%p, plist=%p, found=%d\n ", th_idx ,  nr_send, phead, plist, found);
++	if (!found) {
++		plist = get_next(phead);
++		while(rtw_end_of_queue_search(phead, plist) == _FALSE) {
++			psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++			if ((!psta) || (!psta->tbtx_enable))
++				RTW_DBG("sta tbtx_enable is false\n");
++			else {
++					pstapriv->token_holder[th_idx] = psta;
++					rtw_issue_action_token_req(padapter, pstapriv->token_holder[th_idx++]);
++					break;
++			}
++			plist = get_next(plist);
++		}
++	}
++
++	for (i=th_idx; i<nr_send;) {
++		plist = get_next(plist);
++		if (plist == phead)
++			plist = get_next(plist);
++		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++		if ((!psta) || (!psta->tbtx_enable))
++			RTW_DBG("sta tbtx_enable is false\n");		
++		else {
++			pstapriv->token_holder[th_idx] = psta;
++			rtw_issue_action_token_req(padapter, pstapriv->token_holder[th_idx++]);
++			i++;
++		}
++	}
++	ATOMIC_SET(&pstapriv->nr_token_keeper, nr_send);
++	
++
++exit:
++	// set_timer
++	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++	_set_timer(&pmlmeext->tbtx_token_dispatch_timer, TBTX_TX_DURATION); 
++}
++#endif /* CONFIG_AP_MODE */
++#endif /* CONFIG_RTW_TOKEN_BASED_XMIT */
++
++void link_timer_hdl(void *ctx)
++{
++	_adapter *padapter = (_adapter *)ctx;
++	/* static unsigned int		rx_pkt = 0; */
++	/* static u64				tx_cnt = 0; */
++	/* struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv); */
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	/* struct sta_priv		*pstapriv = &padapter->stapriv; */
++#ifdef CONFIG_RTW_80211R
++	struct	sta_priv		*pstapriv = &padapter->stapriv;
++	struct	sta_info		*psta = NULL;
++	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
++#endif
++
++	if (rtw_sta_linking_test_force_fail())
++		RTW_INFO("rtw_sta_linking_test_force_fail\n");
++
++	if (pmlmeext->join_abort && pmlmeinfo->state != WIFI_FW_NULL_STATE) {
++		RTW_INFO(FUNC_ADPT_FMT" join abort\n", FUNC_ADPT_ARG(padapter));
++		pmlmeinfo->state = WIFI_FW_NULL_STATE;
++		report_join_res(padapter, -4, WLAN_STATUS_UNSPECIFIED_FAILURE);
++		goto exit;
++	}
++
++	if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) {
++		RTW_INFO("link_timer_hdl:no beacon while connecting\n");
++		pmlmeinfo->state = WIFI_FW_NULL_STATE;
++		report_join_res(padapter, -3, WLAN_STATUS_UNSPECIFIED_FAILURE);
++	} else if (pmlmeinfo->state & WIFI_FW_AUTH_STATE) {
++
++#ifdef CONFIG_IOCTL_CFG80211
++		if (rtw_sec_chk_auth_type(padapter, MLME_AUTHTYPE_SAE))
++			return;
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++		/* re-auth timer */
++		if (++pmlmeinfo->reauth_count > REAUTH_LIMIT) {
++			/* if (pmlmeinfo->auth_algo != dot11AuthAlgrthm_Auto) */
++			/* { */
++			pmlmeinfo->state = 0;
++			if (pmlmeinfo->auth_status) {
++				report_join_res(padapter, -1, pmlmeinfo->auth_status);
++				pmlmeinfo->auth_status = 0; /* reset */
++			} else
++				report_join_res(padapter, -1, WLAN_STATUS_UNSPECIFIED_FAILURE);
++			return;
++			/* } */
++			/* else */
++			/* { */
++			/*	pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared; */
++			/*	pmlmeinfo->reauth_count = 0; */
++			/* } */
++		}
++
++		RTW_INFO("link_timer_hdl: auth timeout and try again\n");
++		pmlmeinfo->auth_seq = 1;
++		issue_auth(padapter, NULL, 0);
++		set_link_timer(pmlmeext, REAUTH_TO);
++	} else if (pmlmeinfo->state & WIFI_FW_ASSOC_STATE) {
++		/* re-assoc timer */
++		if (++pmlmeinfo->reassoc_count > REASSOC_LIMIT) {
++			pmlmeinfo->state = WIFI_FW_NULL_STATE;
++#ifdef CONFIG_RTW_80211R
++			if (rtw_ft_roam(padapter)) {
++				psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
++				if (psta)
++					rtw_free_stainfo(padapter,  psta);
++			}
++#endif
++			report_join_res(padapter, -2, WLAN_STATUS_UNSPECIFIED_FAILURE);
++			return;
++		}
++
++#ifdef CONFIG_RTW_80211R
++		if (rtw_ft_roam(padapter)) {
++			RTW_INFO("link_timer_hdl: reassoc timeout and try again\n");
++			issue_reassocreq(padapter);
++		} else
++#endif
++		{
++			RTW_INFO("link_timer_hdl: assoc timeout and try again\n");
++			issue_assocreq(padapter);
++		}
++
++		set_link_timer(pmlmeext, REASSOC_TO);
++	}
++
++exit:
++	return;
++}
++
++void addba_timer_hdl(void *ctx)
++{
++	struct sta_info *psta = (struct sta_info *)ctx;
++
++#ifdef CONFIG_80211N_HT
++	struct ht_priv	*phtpriv;
++
++	if (!psta)
++		return;
++
++	phtpriv = &psta->htpriv;
++
++	if ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) {
++		if (phtpriv->candidate_tid_bitmap)
++			phtpriv->candidate_tid_bitmap = 0x0;
++
++	}
++#endif /* CONFIG_80211N_HT */
++}
++
++#ifdef CONFIG_IEEE80211W
++void report_sta_timeout_event(_adapter *padapter, u8 *MacAddr, unsigned short reason)
++{
++	struct cmd_obj *pcmd_obj;
++	u8 *pevtcmd;
++	u32 cmdsz;
++	struct sta_info *psta;
++	int	mac_id;
++	struct stadel_event *pdel_sta_evt;
++	struct rtw_evt_header *evt_hdr;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++
++	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (pcmd_obj == NULL)
++		return;
++
++	cmdsz = (sizeof(struct stadel_event) + sizeof(struct rtw_evt_header));
++	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
++	if (pevtcmd == NULL) {
++		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
++		return;
++	}
++
++	_rtw_init_listhead(&pcmd_obj->list);
++
++	pcmd_obj->cmdcode = CMD_SET_MLME_EVT;
++	pcmd_obj->cmdsz = cmdsz;
++	pcmd_obj->parmbuf = pevtcmd;
++
++	pcmd_obj->rsp = NULL;
++	pcmd_obj->rspsz  = 0;
++
++	evt_hdr = (struct rtw_evt_header *)(pevtcmd);
++	evt_hdr->len = sizeof(struct stadel_event);
++	evt_hdr->id = EVT_TIMEOUT_STA;
++	evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
++
++	pdel_sta_evt = (struct stadel_event *)(pevtcmd + sizeof(struct rtw_evt_header));
++	_rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN);
++	_rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd), (unsigned char *)(&reason), 2);
++
++
++	psta = rtw_get_stainfo(&padapter->stapriv, MacAddr);
++	if (psta)
++		mac_id = (int)psta->cmn.mac_id;
++	else
++		mac_id = (-1);
++
++	pdel_sta_evt->mac_id = mac_id;
++
++	RTW_INFO("report_del_sta_event: delete STA, mac_id=%d\n", mac_id);
++
++	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
++
++	return;
++}
++
++void clnt_sa_query_timeout(_adapter *padapter)
++{
++	struct mlme_ext_priv *mlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info);
++
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++	receive_disconnect(padapter, get_my_bssid(&(mlmeinfo->network)), WLAN_REASON_SA_QUERY_TIMEOUT, _FALSE);
++}
++
++void sa_query_timer_hdl(void *ctx)
++{
++	struct sta_info *psta = (struct sta_info *)ctx;
++	_adapter *padapter = psta->padapter;
++	_irqL irqL;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE &&
++	    check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++		clnt_sa_query_timeout(padapter);
++	else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++		report_sta_timeout_event(padapter, psta->cmn.mac_addr, WLAN_REASON_PREV_AUTH_NOT_VALID);
++}
++
++#endif /* CONFIG_IEEE80211W */
++
++#ifdef CONFIG_AUTO_AP_MODE
++void rtw_auto_ap_rx_msg_dump(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_pos)
++{
++	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++	struct sta_info *psta = precv_frame->u.hdr.psta;
++	struct ethhdr *ehdr = (struct ethhdr *)ehdr_pos;
++
++	RTW_INFO("eth rx: got eth_type=0x%x\n", ntohs(ehdr->h_proto));
++
++	if (psta && psta->isrc && psta->pid > 0) {
++		u16 rx_pid;
++
++		rx_pid = *(u16 *)(ehdr_pos + ETH_HLEN);
++
++		RTW_INFO("eth rx(pid=0x%x): sta("MAC_FMT") pid=0x%x\n",
++			 rx_pid, MAC_ARG(psta->cmn.mac_addr), psta->pid);
++
++		if (rx_pid == psta->pid) {
++			int i;
++			u16 len = *(u16 *)(ehdr_pos + ETH_HLEN + 2);
++			/* u16 ctrl_type = *(u16 *)(ehdr_pos + ETH_HLEN + 4); */
++
++			/* RTW_INFO("eth, RC: len=0x%x, ctrl_type=0x%x\n", len, ctrl_type);  */
++			RTW_INFO("eth, RC: len=0x%x\n", len);
++
++			for (i = 0; i < len; i++)
++				RTW_INFO("0x%x\n", *(ehdr_pos + ETH_HLEN + 4 + i));
++			/* RTW_INFO("0x%x\n", *(ehdr_pos + ETH_HLEN + 6 + i)); */
++
++			RTW_INFO("eth, RC-end\n");
++		}
++	}
++
++}
++
++void rtw_start_auto_ap(_adapter *adapter)
++{
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11APMode, 0);
++
++	rtw_setopmode_cmd(adapter, Ndis802_11APMode, RTW_CMDF_WAIT_ACK);
++}
++
++static int rtw_auto_ap_start_beacon(_adapter *adapter)
++{
++	int ret = 0;
++	u8 *pbuf = NULL;
++	uint len;
++	u8	supportRate[16];
++	int	sz = 0, rateLen;
++	u8	*ie;
++	u8	wireless_mode, oper_channel;
++	u8 ssid[3] = {0}; /* hidden ssid */
++	u32 ssid_len = sizeof(ssid);
++	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++
++	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++		return -EINVAL;
++
++
++	len = 128;
++	pbuf = rtw_zmalloc(len);
++	if (!pbuf)
++		return -ENOMEM;
++
++
++	/* generate beacon */
++	ie = pbuf;
++
++	/* timestamp will be inserted by hardware */
++	sz += 8;
++	ie += sz;
++
++	/* beacon interval : 2bytes */
++	*(u16 *)ie = cpu_to_le16((u16)100); /* BCN_INTERVAL=100; */
++	sz += 2;
++	ie += 2;
++
++	/* capability info */
++	*(u16 *)ie = 0;
++	*(u16 *)ie |= cpu_to_le16(cap_ESS);
++	*(u16 *)ie |= cpu_to_le16(cap_ShortPremble);
++	/* *(u16*)ie |= cpu_to_le16(cap_Privacy); */
++	sz += 2;
++	ie += 2;
++
++	/* SSID */
++	ie = rtw_set_ie(ie, _SSID_IE_, ssid_len, ssid, &sz);
++
++	/* supported rates */
++	wireless_mode = (WIRELESS_11BG_24N & padapter->registrypriv.wireless_mode);
++	rtw_set_supported_rate(supportRate, wireless_mode);
++	rateLen = rtw_get_rateset_len(supportRate);
++	if (rateLen > 8)
++		ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, 8, supportRate, &sz);
++	else
++		ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, rateLen, supportRate, &sz);
++
++
++	/* DS parameter set */
++	if (rtw_mi_check_status(adapter, MI_LINKED))
++		oper_channel = rtw_mi_get_union_chan(adapter);
++	else
++		oper_channel = adapter_to_dvobj(adapter)->oper_channel;
++
++	ie = rtw_set_ie(ie, _DSSET_IE_, 1, &oper_channel, &sz);
++
++	/* ext supported rates */
++	if (rateLen > 8)
++		ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (supportRate + 8), &sz);
++
++	RTW_INFO("%s, start auto ap beacon sz=%d\n", __FUNCTION__, sz);
++
++	/* lunch ap mode & start to issue beacon */
++	if (rtw_check_beacon_data(adapter, pbuf,  sz) == _SUCCESS) {
++
++	} else
++		ret = -EINVAL;
++
++
++	rtw_mfree(pbuf, len);
++
++	return ret;
++
++}
++#endif/* CONFIG_AUTO_AP_MODE */
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++u8 tx_control_hdl(_adapter *adapter)
++{
++	u8 val;
++
++	if(ATOMIC_READ(&adapter->tbtx_tx_pause))
++		val = 0xff;
++	else
++		val = 0x00;
++
++	rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &val);
++
++	return H2C_SUCCESS;
++}
++#endif
++
++#ifdef CONFIG_AP_MODE
++u8 stop_ap_hdl(_adapter *adapter)
++{
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
++
++	rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11Infrastructure, RTW_CMDF_DIRECTLY);
++	rtw_setopmode_cmd(adapter, Ndis802_11Infrastructure, RTW_CMDF_DIRECTLY);
++
++	return H2C_SUCCESS;
++}
++#endif
++
++u8 setopmode_hdl(_adapter *padapter, u8 *pbuf)
++{
++	u8	type;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct setopmode_parm *psetop = (struct setopmode_parm *)pbuf;
++
++	if (psetop->mode == Ndis802_11APMode
++		|| psetop->mode == Ndis802_11_mesh
++	) {
++		pmlmeinfo->state = WIFI_FW_AP_STATE;
++		type = _HW_STATE_AP_;
++	} else if (psetop->mode == Ndis802_11Infrastructure) {
++		pmlmeinfo->state &= ~(BIT(0) | BIT(1)); /* clear state */
++		pmlmeinfo->state |= WIFI_FW_STATION_STATE;/* set to 	STATION_STATE */
++		type = _HW_STATE_STATION_;
++	} else if (psetop->mode == Ndis802_11IBSS)
++		type = _HW_STATE_ADHOC_;
++	else if (psetop->mode == Ndis802_11Monitor)
++		type = _HW_STATE_MONITOR_;
++	else
++		type = _HW_STATE_NOLINK_;
++
++#ifdef CONFIG_AP_PORT_SWAP
++	rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, (u8 *)(&type));
++#endif
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_SET_OPMODE, (u8 *)(&type));
++
++#ifdef CONFIG_AUTO_AP_MODE
++	if (psetop->mode == Ndis802_11APMode)
++		rtw_auto_ap_start_beacon(padapter);
++#endif
++
++	if (rtw_port_switch_chk(padapter) == _TRUE) {
++		rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);
++
++		if (psetop->mode == Ndis802_11APMode)
++			adapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff; /* ap mode won't dowload rsvd pages */
++		else if (psetop->mode == Ndis802_11Infrastructure) {
++#ifdef CONFIG_LPS
++			_adapter *port0_iface = dvobj_get_port0_adapter(adapter_to_dvobj(padapter));
++			if (port0_iface)
++				rtw_lps_ctrl_wk_cmd(port0_iface, LPS_CTRL_CONNECT, RTW_CMDF_DIRECTLY);
++#endif
++		}
++	}
++
++#ifdef CONFIG_BT_COEXIST
++	if (psetop->mode == Ndis802_11APMode
++		|| psetop->mode == Ndis802_11_mesh
++		|| psetop->mode == Ndis802_11Monitor
++	) {
++		/* Do this after port switch to */
++		/* prevent from downloading rsvd page to wrong port */
++		rtw_btcoex_MediaStatusNotify(padapter, 1); /* connect */
++	}
++#endif /* CONFIG_BT_COEXIST */
++
++	return H2C_SUCCESS;
++
++}
++
++u8 createbss_hdl(_adapter *padapter, u8 *pbuf)
++{
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX	*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
++	WLAN_BSSID_EX	*pdev_network = &padapter->registrypriv.dev_network;
++	struct createbss_parm *parm = (struct createbss_parm *)pbuf;
++	u8 ret = H2C_SUCCESS;
++	/* u8	initialgain; */
++
++#ifdef CONFIG_AP_MODE
++	if ((parm->req_ch == 0 && pmlmeinfo->state == WIFI_FW_AP_STATE)
++		|| parm->req_ch != 0
++	) {
++		start_bss_network(padapter, parm);
++		goto exit;
++	}
++#endif
++
++	/* below is for ad-hoc master */
++	if (parm->adhoc) {
++		rtw_warn_on(pdev_network->InfrastructureMode != Ndis802_11IBSS);
++		rtw_joinbss_reset(padapter);
++
++		pmlmeext->cur_bwmode = CHANNEL_WIDTH_20;
++		pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		pmlmeinfo->ERP_enable = 0;
++		pmlmeinfo->WMM_enable = 0;
++		pmlmeinfo->HT_enable = 0;
++		pmlmeinfo->HT_caps_enable = 0;
++		pmlmeinfo->HT_info_enable = 0;
++		pmlmeinfo->agg_enable_bitmap = 0;
++		pmlmeinfo->candidate_tid_bitmap = 0;
++
++		/* cancel link timer */
++		_cancel_timer_ex(&pmlmeext->link_timer);
++
++		/* clear CAM */
++		flush_all_cam_entry(padapter);
++
++		pdev_network->Length = get_WLAN_BSSID_EX_sz(pdev_network);
++		_rtw_memcpy(pnetwork, pdev_network, FIELD_OFFSET(WLAN_BSSID_EX, IELength));
++		pnetwork->IELength = pdev_network->IELength;
++
++		if (pnetwork->IELength > MAX_IE_SZ) {
++			ret = H2C_PARAMETERS_ERROR;
++			goto ibss_post_hdl;
++		}
++
++		_rtw_memcpy(pnetwork->IEs, pdev_network->IEs, pnetwork->IELength);
++		start_create_ibss(padapter);
++	} else {
++		rtw_warn_on(1);
++		ret = H2C_PARAMETERS_ERROR;
++	}
++
++ibss_post_hdl:
++	rtw_create_ibss_post_hdl(padapter, ret);
++
++exit:
++	return ret;
++}
++
++u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf)
++{
++	u8	join_type;
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	struct joinbss_parm	*pparm = (struct joinbss_parm *)pbuf;
++#endif /* CONFIG_ANTENNA_DIVERSITY */
++	u32 i;
++	/* u8	initialgain; */
++	/* u32	acparm; */
++	u8 u_ch, u_bw, u_offset;
++	u8 doiqk = _FALSE;
++
++	/* check already connecting to AP or not */
++	if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) {
++		if (pmlmeinfo->state & WIFI_FW_STATION_STATE)
++			issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100);
++		pmlmeinfo->state = WIFI_FW_NULL_STATE;
++
++		/* clear CAM */
++		flush_all_cam_entry(padapter);
++
++		_cancel_timer_ex(&pmlmeext->link_timer);
++
++		/* set MSR to nolink->infra. mode		 */
++		/* Set_MSR(padapter, _HW_STATE_NOLINK_); */
++		Set_MSR(padapter, _HW_STATE_STATION_);
++
++
++		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0);
++		if (pmlmeinfo->state & WIFI_FW_STATION_STATE)
++			rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_DISCONNECTED);
++	}
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	rtw_antenna_select_cmd(padapter, pparm->network.PhyInfo.Optimum_antenna, _FALSE);
++#endif
++
++#ifdef CONFIG_WAPI_SUPPORT
++	rtw_wapi_clear_all_cam_entry(padapter);
++#endif
++
++	rtw_joinbss_reset(padapter);
++
++	pmlmeinfo->ERP_enable = 0;
++	pmlmeinfo->WMM_enable = 0;
++	pmlmeinfo->HT_enable = 0;
++	pmlmeinfo->HT_caps_enable = 0;
++	pmlmeinfo->HT_info_enable = 0;
++	pmlmeinfo->agg_enable_bitmap = 0;
++	pmlmeinfo->candidate_tid_bitmap = 0;
++	pmlmeinfo->bwmode_updated = _FALSE;
++	/* pmlmeinfo->assoc_AP_vendor = HT_IOT_PEER_MAX; */
++	pmlmeinfo->VHT_enable = 0;
++#ifdef ROKU_PRIVATE
++	pmlmeinfo->ht_vht_received = 0;
++	_rtw_memset(pmlmeinfo->SupportedRates_infra_ap, 0, NDIS_802_11_LENGTH_RATES_EX);
++#endif /* ROKU_PRIVATE */
++	_rtw_memcpy(pnetwork, pbuf, FIELD_OFFSET(WLAN_BSSID_EX, IELength));
++	pnetwork->IELength = ((WLAN_BSSID_EX *)pbuf)->IELength;
++
++	if (pnetwork->IELength > MAX_IE_SZ) /* Check pbuf->IELength */
++		return H2C_PARAMETERS_ERROR;
++
++	if (pnetwork->IELength < 2) {
++		report_join_res(padapter, (-4), WLAN_STATUS_UNSPECIFIED_FAILURE);
++		return H2C_SUCCESS;
++	}
++	_rtw_memcpy(pnetwork->IEs, ((WLAN_BSSID_EX *)pbuf)->IEs, pnetwork->IELength);
++
++	pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork);
++
++	/* Check AP vendor to move rtw_joinbss_cmd() */
++	/* pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->IEs, pnetwork->IELength); */
++
++	/* sizeof(NDIS_802_11_FIXED_IEs)	 */
++	for (i = _FIXED_IE_LENGTH_ ; i < pnetwork->IELength - 2 ;) {
++		pIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i);
++
++		switch (pIE->ElementID) {
++		case _VENDOR_SPECIFIC_IE_: /* Get WMM IE. */
++			if (_rtw_memcmp(pIE->data, WMM_OUI, 4))
++				WMM_param_handler(padapter, pIE);
++			break;
++
++#ifdef CONFIG_80211N_HT
++		case _HT_CAPABILITY_IE_:	/* Get HT Cap IE. */
++			pmlmeinfo->HT_caps_enable = 1;
++			break;
++
++		case _HT_EXTRA_INFO_IE_:	/* Get HT Info IE. */
++			pmlmeinfo->HT_info_enable = 1;
++			break;
++#endif /* CONFIG_80211N_HT */
++
++#ifdef CONFIG_80211AC_VHT
++		case EID_VHTCapability: /* Get VHT Cap IE. */
++			pmlmeinfo->VHT_enable = 1;
++			break;
++
++		case EID_VHTOperation: /* Get VHT Operation IE. */
++			break;
++#endif /* CONFIG_80211AC_VHT */
++		default:
++			break;
++		}
++
++		i += (pIE->Length + 2);
++	}
++
++	rtw_bss_get_chbw(pnetwork
++		, &pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset, 1, 1);
++
++	rtw_adjust_chbw(padapter, pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset);
++
++#if 0
++	if (padapter->registrypriv.wifi_spec) {
++		/* for WiFi test, follow WMM test plan spec */
++		acparm = 0x002F431C; /* VO */
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm));
++		acparm = 0x005E541C; /* VI */
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm));
++		acparm = 0x0000A525; /* BE */
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));
++		acparm = 0x0000A549; /* BK */
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm));
++
++		/* for WiFi test, mixed mode with intel STA under bg mode throughput issue */
++		if (padapter->mlmepriv.htpriv.ht_option == _FALSE) {
++			acparm = 0x00004320;
++			rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));
++		}
++	} else {
++		acparm = 0x002F3217; /* VO */
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm));
++		acparm = 0x005E4317; /* VI */
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm));
++		acparm = 0x00105320; /* BE */
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));
++		acparm = 0x0000A444; /* BK */
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm));
++	}
++#endif
++
++	/* check channel, bandwidth, offset and switch */
++	if (rtw_chk_start_clnt_join(padapter, &u_ch, &u_bw, &u_offset) == _FAIL) {
++		report_join_res(padapter, (-4), WLAN_STATUS_UNSPECIFIED_FAILURE);
++		return H2C_SUCCESS;
++	}
++
++	/* disable dynamic functions, such as high power, DIG */
++	/*rtw_phydm_func_disable_all(padapter);*/
++
++	/* config the initial gain under linking, need to write the BB registers */
++	/* initialgain = 0x1E; */
++	/*rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);*/
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
++	if (MLME_IS_STA(padapter))
++		rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTING);
++	else
++		rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);
++
++	join_type = 0;
++	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
++
++	rtw_btcoex_connect_notify(padapter, join_type);
++
++	doiqk = _TRUE;
++	rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
++
++	set_channel_bwmode(padapter, u_ch, u_offset, u_bw);
++	rtw_mi_update_union_chan_inf(padapter, u_ch, u_offset, u_bw);
++
++	doiqk = _FALSE;
++	rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
++
++	/* cancel link timer */
++	_cancel_timer_ex(&pmlmeext->link_timer);
++
++	start_clnt_join(padapter);
++
++	return H2C_SUCCESS;
++
++}
++
++u8 disconnect_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++#if CONFIG_DFS
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++#endif
++	struct disconnect_parm *param = (struct disconnect_parm *)pbuf;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
++	u8 val8;
++
++	if (is_client_associated_to_ap(padapter)
++		#if CONFIG_DFS
++		&& !IS_RADAR_DETECTED(rfctl) && !rfctl->csa_ch
++		#endif
++	) {
++		#ifdef CONFIG_PLATFORM_ROCKCHIPS
++		/* To avoid connecting to AP fail during resume process, change retry count from 5 to 1 */
++		issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100);
++		#else
++		issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, param->deauth_timeout_ms / 100, 100);
++		#endif /* CONFIG_PLATFORM_ROCKCHIPS */
++	}
++
++#ifndef CONFIG_SUPPORT_MULTI_BCN
++	if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {
++		/* Stop BCN */
++		val8 = 0;
++		rtw_hal_set_hwreg(padapter, HW_VAR_BCN_FUNC, (u8 *)(&val8));
++	}
++#endif
++
++	rtw_sta_mstatus_report(padapter);
++
++	rtw_mlmeext_disconnect(padapter);
++
++	rtw_free_uc_swdec_pending_queue(padapter);
++
++	return	H2C_SUCCESS;
++}
++
++static const char *const _scan_state_str[] = {
++	"SCAN_DISABLE",
++	"SCAN_START",
++	"SCAN_PS_ANNC_WAIT",
++	"SCAN_ENTER",
++	"SCAN_PROCESS",
++	"SCAN_BACKING_OP",
++	"SCAN_BACK_OP",
++	"SCAN_LEAVING_OP",
++	"SCAN_LEAVE_OP",
++	"SCAN_SW_ANTDIV_BL",
++	"SCAN_TO_P2P_LISTEN",
++	"SCAN_P2P_LISTEN",
++	"SCAN_COMPLETE",
++	"SCAN_STATE_MAX",
++};
++
++const char *scan_state_str(u8 state)
++{
++	state = (state >= SCAN_STATE_MAX) ? SCAN_STATE_MAX : state;
++	return _scan_state_str[state];
++}
++
++static bool scan_abort_hdl(_adapter *adapter)
++{
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++	struct ss_res *ss = &pmlmeext->sitesurvey_res;
++#ifdef CONFIG_P2P
++	struct wifidirect_info *pwdinfo = &adapter->wdinfo;
++#endif
++	bool ret = _FALSE;
++
++	if (pmlmeext->scan_abort == _TRUE) {
++#ifdef CONFIG_P2P
++		if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) {
++			rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_MAX);
++			ss->channel_idx = 3;
++			RTW_INFO("%s idx:%d, cnt:%u\n", __FUNCTION__
++				 , ss->channel_idx
++				 , pwdinfo->find_phase_state_exchange_cnt
++				);
++		} else
++#endif
++		{
++			ss->channel_idx = ss->ch_num;
++			RTW_INFO("%s idx:%d\n", __FUNCTION__
++				 , ss->channel_idx
++				);
++		}
++		pmlmeext->scan_abort = _FALSE;
++		ret = _TRUE;
++	}
++
++	return ret;
++}
++
++u8 rtw_scan_sparse(_adapter *adapter, struct rtw_ieee80211_channel *ch, u8 ch_num)
++{
++	/* interval larger than this is treated as backgroud scan */
++#ifndef RTW_SCAN_SPARSE_BG_INTERVAL_MS
++#define RTW_SCAN_SPARSE_BG_INTERVAL_MS 12000
++#endif
++
++#ifndef RTW_SCAN_SPARSE_CH_NUM_MIRACAST
++#define RTW_SCAN_SPARSE_CH_NUM_MIRACAST 1
++#endif
++#ifndef RTW_SCAN_SPARSE_CH_NUM_BG
++#define RTW_SCAN_SPARSE_CH_NUM_BG 4
++#endif
++#ifdef CONFIG_LAYER2_ROAMING
++#ifndef RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE
++#define RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE 1
++#endif
++#endif
++
++#define SCAN_SPARSE_CH_NUM_INVALID 255
++
++	static u8 token = 255;
++	u32 interval;
++	bool busy_traffic = _FALSE;
++	bool miracast_enabled = _FALSE;
++	bool bg_scan = _FALSE;
++	u8 max_allow_ch = SCAN_SPARSE_CH_NUM_INVALID;
++	u8 scan_division_num;
++	u8 ret_num = ch_num;
++	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++
++	if (mlmeext->last_scan_time == 0)
++		mlmeext->last_scan_time = rtw_get_current_time();
++
++	interval = rtw_get_passing_time_ms(mlmeext->last_scan_time);
++
++
++	if (rtw_mi_busy_traffic_check(adapter))
++		busy_traffic = _TRUE;
++
++	if (rtw_mi_check_miracast_enabled(adapter))
++		miracast_enabled = _TRUE;
++
++	if (interval > RTW_SCAN_SPARSE_BG_INTERVAL_MS)
++		bg_scan = _TRUE;
++
++	/* max_allow_ch by conditions*/
++
++#if RTW_SCAN_SPARSE_MIRACAST
++	if (miracast_enabled == _TRUE && busy_traffic == _TRUE)
++		max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_MIRACAST);
++#endif
++
++#if RTW_SCAN_SPARSE_BG
++	if (bg_scan == _TRUE)
++		max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_BG);
++#endif
++
++#if  defined(CONFIG_LAYER2_ROAMING) && defined(RTW_SCAN_SPARSE_ROAMING_ACTIVE)
++	if (rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) {
++		if (busy_traffic == _TRUE && adapter->mlmepriv.need_to_roam == _TRUE)
++			max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE);
++	}
++#endif
++
++
++	if (max_allow_ch != SCAN_SPARSE_CH_NUM_INVALID) {
++		int i;
++		int k = 0;
++
++		scan_division_num = (ch_num / max_allow_ch) + ((ch_num % max_allow_ch) ? 1 : 0);
++		token = (token + 1) % scan_division_num;
++
++		if (0)
++			RTW_INFO("scan_division_num:%u, token:%u\n", scan_division_num, token);
++
++		for (i = 0; i < ch_num; i++) {
++			if (ch[i].hw_value && (i % scan_division_num) == token
++			   ) {
++				if (i != k)
++					_rtw_memcpy(&ch[k], &ch[i], sizeof(struct rtw_ieee80211_channel));
++				k++;
++			}
++		}
++
++		_rtw_memset(&ch[k], 0, sizeof(struct rtw_ieee80211_channel));
++
++		ret_num = k;
++		mlmeext->last_scan_time = rtw_get_current_time();
++	}
++
++	return ret_num;
++}
++
++#ifdef CONFIG_SCAN_BACKOP
++u8 rtw_scan_backop_decision(_adapter *adapter)
++{
++	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++	struct mi_state mstate;
++	u8 backop_flags = 0;
++
++	rtw_mi_status(adapter, &mstate);
++
++	if ((MSTATE_STA_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(mlmeext, SS_BACKOP_EN))
++		|| (MSTATE_STA_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(mlmeext, SS_BACKOP_EN_NL)))
++		backop_flags |= mlmeext_scan_backop_flags_sta(mlmeext);
++
++#ifdef CONFIG_AP_MODE
++	if ((MSTATE_AP_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(mlmeext, SS_BACKOP_EN))
++		|| (MSTATE_AP_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(mlmeext, SS_BACKOP_EN_NL)))
++		backop_flags |= mlmeext_scan_backop_flags_ap(mlmeext);
++#endif
++
++#ifdef CONFIG_RTW_MESH
++	if ((MSTATE_MESH_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_mesh(mlmeext, SS_BACKOP_EN))
++		|| (MSTATE_MESH_NUM(&mstate) && mlmeext_chk_scan_backop_flags_mesh(mlmeext, SS_BACKOP_EN_NL)))
++		backop_flags |= mlmeext_scan_backop_flags_mesh(mlmeext);
++#endif
++
++	return backop_flags;
++}
++#endif
++
++#define SCANNING_TIMEOUT_EX	2000
++u32 rtw_scan_timeout_decision(_adapter *padapter)
++{
++	u32 back_op_times= 0;
++	u8 max_chan_num;
++	u16 scan_ms;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct ss_res *ss = &pmlmeext->sitesurvey_res;
++
++	if (is_supported_5g(padapter->registrypriv.wireless_mode)
++		&& IsSupported24G(padapter->registrypriv.wireless_mode)) 
++		max_chan_num = MAX_CHANNEL_NUM;/* dual band */
++	else
++		max_chan_num = MAX_CHANNEL_NUM_2G;/*single band*/
++
++	#ifdef CONFIG_SCAN_BACKOP
++	if (rtw_scan_backop_decision(padapter))
++		back_op_times = (max_chan_num / ss->scan_cnt_max) * ss->backop_ms;
++	#endif
++
++	if (ss->duration)
++		scan_ms = ss->duration;
++	else
++	#if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)
++	if (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter))
++		scan_ms = rtw_acs_get_adv_st(padapter);
++	else
++	#endif /*CONFIG_RTW_ACS*/
++		scan_ms = ss->scan_ch_ms;
++
++	ss->scan_timeout_ms = (scan_ms * max_chan_num) + back_op_times + SCANNING_TIMEOUT_EX;
++	#ifdef DBG_SITESURVEY
++	RTW_INFO("%s , scan_timeout_ms = %d (ms)\n", __func__, ss->scan_timeout_ms);
++	#endif /*DBG_SITESURVEY*/
++	return ss->scan_timeout_ms;
++}
++
++static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel *out,
++		u32 out_num, struct rtw_ieee80211_channel *in, u32 in_num, bool no_sparse)
++{
++	int i, j;
++	int set_idx;
++	u8 chan;
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(padapter));
++
++	/* clear first */
++	_rtw_memset(out, 0, sizeof(struct rtw_ieee80211_channel) * out_num);
++
++	/* acquire channels from in */
++	j = 0;
++	for (i = 0; i < in_num; i++) {
++
++		if (0)
++			RTW_INFO(FUNC_ADPT_FMT" "CHAN_FMT"\n", FUNC_ADPT_ARG(padapter), CHAN_ARG(&in[i]));
++
++		if (!in[i].hw_value || (in[i].flags & RTW_IEEE80211_CHAN_DISABLED))
++			continue;
++		if (rtw_mlme_band_check(padapter, in[i].hw_value) == _FALSE)
++			continue;
++
++		set_idx = rtw_chset_search_ch(rfctl->channel_set, in[i].hw_value);
++		if (set_idx >= 0) {
++			if (j >= out_num) {
++				RTW_PRINT(FUNC_ADPT_FMT" out_num:%u not enough\n",
++					  FUNC_ADPT_ARG(padapter), out_num);
++				break;
++			}
++
++			_rtw_memcpy(&out[j], &in[i], sizeof(struct rtw_ieee80211_channel));
++
++			if (rfctl->channel_set[set_idx].ScanType == SCAN_PASSIVE
++				|| rfctl->channel_set[set_idx].dfs)
++				out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN;
++
++			j++;
++		}
++		if (j >= out_num)
++			break;
++	}
++
++	/* if out is empty, use channel_set as default */
++	if (j == 0) {
++		for (i = 0; i < rfctl->max_chan_nums; i++) {
++			chan = rfctl->channel_set[i].ChannelNum;
++			if (rtw_mlme_band_check(padapter, chan) == _TRUE) {
++				if (rtw_mlme_ignore_chan(padapter, chan) == _TRUE)
++					continue;
++
++				if (0)
++					RTW_INFO(FUNC_ADPT_FMT" ch:%u\n", FUNC_ADPT_ARG(padapter), chan);
++
++				if (j >= out_num) {
++					RTW_PRINT(FUNC_ADPT_FMT" out_num:%u not enough\n",
++						FUNC_ADPT_ARG(padapter), out_num);
++					break;
++				}
++
++				out[j].hw_value = chan;
++
++				if (rfctl->channel_set[i].ScanType == SCAN_PASSIVE
++					|| rfctl->channel_set[i].dfs)
++					out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN;
++
++				j++;
++			}
++		}
++	}
++
++	if (!no_sparse
++		&& !regsty->wifi_spec
++		&& j > 6 /* assume ch_num > 6 is normal scan */
++	) {
++		/* scan_sparse */
++		j = rtw_scan_sparse(padapter, out, j);
++	}
++
++	return j;
++}
++
++static void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm)
++{
++	struct ss_res *ss = &adapter->mlmeextpriv.sitesurvey_res;
++	RT_CHANNEL_INFO *chset = adapter_to_chset(adapter);
++	int i;
++
++	ss->bss_cnt = 0;
++	ss->channel_idx = 0;
++	ss->force_ssid_scan = 0;
++	ss->igi_scan = 0;
++	ss->igi_before_scan = 0;
++#ifdef CONFIG_SCAN_BACKOP
++	ss->scan_cnt = 0;
++#endif
++#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)
++	ss->is_sw_antdiv_bl_scan = 0;
++#endif
++	ss->ssid_num = 0;
++	for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) {
++		if (parm->ssid[i].SsidLength) {
++			_rtw_memcpy(ss->ssid[i].Ssid, parm->ssid[i].Ssid, IW_ESSID_MAX_SIZE);
++			ss->ssid[i].SsidLength = parm->ssid[i].SsidLength;
++			ss->ssid_num++;
++		} else
++			ss->ssid[i].SsidLength = 0;
++	}
++
++	ss->ch_num = rtw_scan_ch_decision(adapter
++					, ss->ch, RTW_CHANNEL_SCAN_AMOUNT
++					, parm->ch, parm->ch_num
++					, parm->acs
++				);
++
++	for (i = 0; i < MAX_CHANNEL_NUM; i++)
++		chset[i].hidden_bss_cnt = 0;
++
++	ss->bw = parm->bw;
++	ss->igi = parm->igi;
++	ss->token = parm->token;
++	ss->duration = parm->duration;
++	ss->scan_mode = parm->scan_mode;
++	ss->token = parm->token;
++	ss->acs = parm->acs;
++}
++
++static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE *type)
++{
++	u8 next_state;
++	u8 scan_ch = 0;
++	RT_SCAN_TYPE scan_type = SCAN_PASSIVE;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct ss_res *ss = &pmlmeext->sitesurvey_res;
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	int ch_set_idx;
++#ifdef CONFIG_P2P
++	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++#endif
++#ifdef CONFIG_SCAN_BACKOP
++	u8 backop_flags = 0;
++#endif
++
++	/* handle scan abort request */
++	scan_abort_hdl(padapter);
++
++#ifdef CONFIG_P2P
++	if (pwdinfo->rx_invitereq_info.scan_op_ch_only || pwdinfo->p2p_info.scan_op_ch_only) {
++		if (pwdinfo->rx_invitereq_info.scan_op_ch_only)
++			scan_ch = pwdinfo->rx_invitereq_info.operation_ch[ss->channel_idx];
++		else
++			scan_ch = pwdinfo->p2p_info.operation_ch[ss->channel_idx];
++		scan_type = SCAN_ACTIVE;
++	} else if (rtw_p2p_findphase_ex_is_social(pwdinfo)) {
++		/*
++		* Commented by Albert 2011/06/03
++		* The driver is in the find phase, it should go through the social channel.
++		*/
++		scan_ch = pwdinfo->social_chan[ss->channel_idx];
++		ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, scan_ch);
++		if (ch_set_idx >= 0)
++			scan_type = rfctl->channel_set[ch_set_idx].ScanType;
++		else
++			scan_type = SCAN_ACTIVE;
++	} else
++#endif /* CONFIG_P2P */
++	{
++		struct rtw_ieee80211_channel *ch;
++
++		#ifdef CONFIG_SCAN_BACKOP
++		backop_flags = rtw_scan_backop_decision(padapter);
++		#endif
++
++		#ifdef CONFIG_SCAN_BACKOP
++		if (!(backop_flags && ss->scan_cnt >= ss->scan_cnt_max))
++		#endif
++		{
++			#ifdef CONFIG_RTW_WIFI_HAL
++			if (adapter_to_dvobj(padapter)->nodfs) {
++				while (ss->channel_idx < ss->ch_num && rtw_chset_is_dfs_ch(rfctl->channel_set, ss->ch[ss->channel_idx].hw_value))
++					ss->channel_idx++;
++			} else
++			#endif
++			if (ss->channel_idx != 0 && ss->force_ssid_scan == 0
++				&& pmlmeext->sitesurvey_res.ssid_num
++				&& (ss->ch[ss->channel_idx - 1].flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN)
++			) {
++				ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, ss->ch[ss->channel_idx - 1].hw_value);
++				if (ch_set_idx != -1 && rfctl->channel_set[ch_set_idx].hidden_bss_cnt
++					&& (!IS_DFS_SLAVE_WITH_RD(rfctl)
++						|| rtw_rfctl_dfs_domain_unknown(rfctl)
++						|| !CH_IS_NON_OCP(&rfctl->channel_set[ch_set_idx]))
++				) {
++					ss->channel_idx--;
++					ss->force_ssid_scan = 1;
++				}
++			} else
++				ss->force_ssid_scan = 0;
++		}
++
++		if (ss->channel_idx < ss->ch_num) {
++			ch = &ss->ch[ss->channel_idx];
++			scan_ch = ch->hw_value;
++
++			#if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)
++			if (IS_ACS_ENABLE(padapter) && rtw_is_acs_passiv_scan(padapter))
++				scan_type = SCAN_PASSIVE;
++			else
++			#endif /*CONFIG_RTW_ACS*/
++				scan_type = (ch->flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) ? SCAN_PASSIVE : SCAN_ACTIVE;
++		}
++	}
++
++	if (scan_ch != 0) {
++		next_state = SCAN_PROCESS;
++
++		#ifdef CONFIG_SCAN_BACKOP
++		if (backop_flags) {
++			if (ss->scan_cnt < ss->scan_cnt_max)
++				ss->scan_cnt++;
++			else {
++				mlmeext_assign_scan_backop_flags(pmlmeext, backop_flags);
++				next_state = SCAN_BACKING_OP;
++			}
++		}
++		#endif
++
++	} else if (rtw_p2p_findphase_ex_is_needed(pwdinfo)) {
++		/* go p2p listen */
++		next_state = SCAN_TO_P2P_LISTEN;
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	} else if (rtw_hal_antdiv_before_linked(padapter)) {
++		/* go sw antdiv before link */
++		next_state = SCAN_SW_ANTDIV_BL;
++#endif
++	} else {
++		next_state = SCAN_COMPLETE;
++
++#if defined(DBG_SCAN_SW_ANTDIV_BL)
++		{
++			/* for SCAN_SW_ANTDIV_BL state testing */
++			struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++			int i;
++			bool is_linked = _FALSE;
++
++			for (i = 0; i < dvobj->iface_nums; i++) {
++				if (rtw_linked_check(dvobj->padapters[i]))
++					is_linked = _TRUE;
++			}
++
++			if (!is_linked) {
++				static bool fake_sw_antdiv_bl_state = 0;
++
++				if (fake_sw_antdiv_bl_state == 0) {
++					next_state = SCAN_SW_ANTDIV_BL;
++					fake_sw_antdiv_bl_state = 1;
++				} else
++					fake_sw_antdiv_bl_state = 0;
++			}
++		}
++#endif /* defined(DBG_SCAN_SW_ANTDIV_BL) */
++	}
++
++#ifdef CONFIG_SCAN_BACKOP
++	if (next_state != SCAN_PROCESS)
++		ss->scan_cnt = 0;
++#endif
++
++
++#ifdef DBG_FIXED_CHAN
++	if (pmlmeext->fixed_chan != 0xff && next_state == SCAN_PROCESS)
++		scan_ch = pmlmeext->fixed_chan;
++#endif
++
++	if (ch)
++		*ch = scan_ch;
++	if (type)
++		*type = scan_type;
++
++	return next_state;
++}
++
++void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType)
++{
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct ss_res *ss = &pmlmeext->sitesurvey_res;
++	u8 ssid_scan = 0;
++
++#ifdef CONFIG_P2P
++#ifndef CONFIG_IOCTL_CFG80211
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++#endif
++#endif
++
++	if (survey_channel != 0) {
++		set_channel_bwmode(padapter, survey_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++
++		if (ScanType == SCAN_PASSIVE && ss->force_ssid_scan)
++			ssid_scan = 1;
++		else if (ScanType == SCAN_ACTIVE) {
++#ifdef CONFIG_P2P
++			#ifdef CONFIG_IOCTL_CFG80211
++			if (rtw_cfg80211_is_p2p_scan(padapter))
++			#else
++			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN)
++				|| rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH))
++			#endif
++			{
++				issue_probereq_p2p(padapter, NULL);
++				issue_probereq_p2p(padapter, NULL);
++				issue_probereq_p2p(padapter, NULL);
++			} else
++#endif /* CONFIG_P2P */
++			{
++				if (pmlmeext->sitesurvey_res.scan_mode == SCAN_ACTIVE) {
++					/* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */
++					if (padapter->registrypriv.wifi_spec)
++						issue_probereq(padapter, NULL, NULL);
++					else
++						issue_probereq_ex(padapter, NULL, NULL, 0, 0, 0, 0);
++					issue_probereq(padapter, NULL, NULL);
++				}
++
++				ssid_scan = 1;
++			}
++		}
++
++		if (ssid_scan) {
++			int i;
++
++			for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) {
++				if (pmlmeext->sitesurvey_res.ssid[i].SsidLength) {
++					/* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */
++					if (padapter->registrypriv.wifi_spec)
++						issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL);
++					else
++						issue_probereq_ex(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL, 0, 0, 0, 0);
++					issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL);
++				}
++			}
++		}
++	} else {
++		/* channel number is 0 or this channel is not valid. */
++		rtw_warn_on(1);
++	}
++
++	return;
++}
++
++void survey_done_set_ch_bw(_adapter *padapter)
++{
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	u8 cur_channel = 0;
++	u8 cur_bwmode;
++	u8 cur_ch_offset;
++
++#ifdef CONFIG_MCC_MODE
++	if (!rtw_hal_mcc_change_scan_flag(padapter, &cur_channel, &cur_bwmode, &cur_ch_offset)) {
++		if (0)
++			RTW_INFO(FUNC_ADPT_FMT" back to AP channel - ch:%u, bw:%u, offset:%u\n",
++				FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset);
++		goto exit;
++	}
++#endif
++
++	if (rtw_mi_get_ch_setting_union(padapter, &cur_channel, &cur_bwmode, &cur_ch_offset) != 0) {
++		if (0)
++			RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n",
++				FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset);
++	} else {
++#ifdef CONFIG_P2P
++		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++		_adapter *iface;
++		int i;
++
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			iface = dvobj->padapters[i];
++			if (!iface)
++				continue;
++
++#ifdef CONFIG_IOCTL_CFG80211
++			if (iface->wdinfo.driver_interface == DRIVER_CFG80211 && !adapter_wdev_data(iface)->p2p_enabled)
++				continue;
++#endif
++
++			if (rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_LISTEN)) {
++				cur_channel = iface->wdinfo.listen_channel;
++				cur_bwmode = CHANNEL_WIDTH_20;
++				cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++				if (0)
++					RTW_INFO(FUNC_ADPT_FMT" back to "ADPT_FMT"'s listen ch - ch:%u, bw:%u, offset:%u\n",
++						FUNC_ADPT_ARG(padapter), ADPT_ARG(iface), cur_channel, cur_bwmode, cur_ch_offset);
++				break;
++			}
++		}
++#endif /* CONFIG_P2P */
++
++		if (cur_channel == 0) {
++			cur_channel = pmlmeext->cur_channel;
++			cur_bwmode = pmlmeext->cur_bwmode;
++			cur_ch_offset = pmlmeext->cur_ch_offset;
++			if (0)
++				RTW_INFO(FUNC_ADPT_FMT" back to ch:%u, bw:%u, offset:%u\n",
++					FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset);
++		}
++	}
++#ifdef CONFIG_MCC_MODE
++exit:
++#endif
++	set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode);
++}
++
++/**
++ * rtw_ps_annc - check and doing ps announcement for all the adapters
++ * @adapter: the requesting adapter
++ * @ps: power saving or not
++ *
++ * Returns: 0: no ps announcement is doing. 1: ps announcement is doing
++ */
++u8 rtw_ps_annc(_adapter *adapter, bool ps)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	_adapter *iface;
++	int i;
++	u8 ps_anc = 0;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (!iface)
++			continue;
++
++		if (MLME_IS_STA(iface)) {
++			if (is_client_associated_to_ap(iface) == _TRUE) {
++				/* TODO: TDLS peers */
++				#ifdef CONFIG_MCC_MODE
++				/* for two station case */
++				if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_NEED_MCC)) {
++					u8 ch = iface->mlmeextpriv.cur_channel;
++					u8 offset = iface->mlmeextpriv.cur_ch_offset;
++					u8 bw = iface->mlmeextpriv.cur_bwmode;
++
++					set_channel_bwmode(iface, ch, offset, bw);
++				}
++				#endif /* CONFIG_MCC_MODE */
++				issue_nulldata(iface, NULL, ps, 3, 500);
++				ps_anc = 1;
++			}
++		#ifdef CONFIG_RTW_MESH
++		} else if (MLME_IS_MESH(iface)) {
++			if (rtw_mesh_ps_annc(iface, ps))
++				ps_anc = 1;
++		#endif
++		}
++	}
++	return ps_anc;
++}
++
++void rtw_leave_opch(_adapter *adapter)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++
++#ifdef CONFIG_MCC_MODE
++	if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
++		return;
++#endif
++
++	_enter_critical_mutex(&rfctl->offch_mutex, NULL);
++
++	if (rfctl->offch_state == OFFCHS_NONE) {
++		/* prepare to leave operating channel */
++		rfctl->offch_state = OFFCHS_LEAVING_OP;
++
++		/* clear HW TX queue */
++		rtw_hal_set_hwreg(adapter, HW_VAR_CHECK_TXBUF, 0);
++
++		rtw_hal_macid_sleep_all_used(adapter);
++
++		rtw_ps_annc(adapter, 1);
++
++		rfctl->offch_state = OFFCHS_LEAVE_OP;
++	}
++
++	_exit_critical_mutex(&rfctl->offch_mutex, NULL);
++}
++
++void rtw_back_opch(_adapter *adapter)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++
++#ifdef CONFIG_MCC_MODE
++	if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
++		return;
++#endif
++
++	_enter_critical_mutex(&rfctl->offch_mutex, NULL);
++
++	if (rfctl->offch_state != OFFCHS_NONE) {
++		rfctl->offch_state = OFFCHS_BACKING_OP;
++		rtw_hal_macid_wakeup_all_used(adapter);
++		rtw_ps_annc(adapter, 0);
++
++		rfctl->offch_state = OFFCHS_NONE;
++		rtw_mi_os_xmit_schedule(adapter);
++	}
++
++	_exit_critical_mutex(&rfctl->offch_mutex, NULL);
++}
++
++void sitesurvey_set_igi(_adapter *adapter)
++{
++	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++	struct ss_res *ss = &mlmeext->sitesurvey_res;
++	u8 igi;
++#ifdef CONFIG_P2P
++	struct wifidirect_info *pwdinfo = &adapter->wdinfo;
++#endif
++
++	switch (mlmeext_scan_state(mlmeext)) {
++	case SCAN_ENTER:
++		#ifdef CONFIG_P2P
++		#ifdef CONFIG_IOCTL_CFG80211
++		if (pwdinfo->driver_interface == DRIVER_CFG80211 && rtw_cfg80211_is_p2p_scan(adapter))
++			igi = 0x30;
++		else
++		#endif /* CONFIG_IOCTL_CFG80211 */
++		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++			igi = 0x28;
++		else
++		#endif /* CONFIG_P2P */
++
++		if (ss->igi)
++			igi = ss->igi;
++		else
++		#if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)
++		if (IS_ACS_ENABLE(adapter) && rtw_is_acs_igi_valid(adapter))
++			igi = rtw_acs_get_adv_igi(adapter);
++		else
++		#endif /*CONFIG_RTW_ACS*/
++			igi = 0x1e;
++
++		/* record IGI status */
++		ss->igi_scan = igi;
++		rtw_hal_get_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &ss->igi_before_scan, NULL);
++
++		/* disable DIG and set IGI for scan */
++		rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE);
++		break;
++	case SCAN_COMPLETE:
++	case SCAN_TO_P2P_LISTEN:
++		/* enable DIG and restore IGI */
++		igi = 0xff;
++		rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE);
++		break;
++#ifdef CONFIG_SCAN_BACKOP
++	case SCAN_BACKING_OP:
++		/* write IGI for op channel when DIG is not enabled */
++		odm_write_dig(adapter_to_phydm(adapter), ss->igi_before_scan);
++		break;
++	case SCAN_LEAVE_OP:
++		/* write IGI for scan when DIG is not enabled */
++		odm_write_dig(adapter_to_phydm(adapter), ss->igi_scan);
++		break;
++#endif /* CONFIG_SCAN_BACKOP */
++	default:
++		rtw_warn_on(1);
++		break;
++	}
++}
++void sitesurvey_set_msr(_adapter *adapter, bool enter)
++{
++	u8 network_type;
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	if (enter) {
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++		rtw_hal_get_hwreg(adapter, HW_VAR_MEDIA_STATUS, (u8 *)(&pmlmeinfo->hw_media_state));
++#endif
++		/* set MSR to no link state */
++		network_type = _HW_STATE_NOLINK_;
++	} else {
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++		network_type = pmlmeinfo->hw_media_state;
++#else
++		network_type = pmlmeinfo->state & 0x3;
++#endif
++	}
++	Set_MSR(adapter, network_type);
++}
++
++void sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++
++	_enter_critical_mutex(&rfctl->offch_mutex, NULL);
++
++	switch (scan_state) {
++	case SCAN_DISABLE:
++	case SCAN_BACK_OP:
++		rfctl->offch_state = OFFCHS_NONE;
++		break;
++	case SCAN_START:
++	case SCAN_LEAVING_OP:
++		rfctl->offch_state = OFFCHS_LEAVING_OP;
++		break;
++	case SCAN_ENTER:
++	case SCAN_LEAVE_OP:
++		rfctl->offch_state = OFFCHS_LEAVE_OP;
++		break;
++	case SCAN_COMPLETE:
++	case SCAN_BACKING_OP:
++		rfctl->offch_state = OFFCHS_BACKING_OP;
++		break;
++	default:
++		break;
++	}
++
++	_exit_critical_mutex(&rfctl->offch_mutex, NULL);
++}
++
++u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
++{
++	struct sitesurvey_parm	*pparm = (struct sitesurvey_parm *)pbuf;
++#ifdef DBG_CHECK_FW_PS_STATE
++	struct dvobj_priv *dvobj = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
++#endif
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct ss_res *ss = &pmlmeext->sitesurvey_res;
++#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++		struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++#endif
++	u8 val8;
++
++#ifdef CONFIG_P2P
++	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++#endif
++
++#ifdef DBG_CHECK_FW_PS_STATE
++	if (rtw_fw_ps_state(padapter) == _FAIL) {
++		RTW_INFO("scan without leave 32k\n");
++		pdbgpriv->dbg_scan_pwr_state_cnt++;
++	}
++#endif /* DBG_CHECK_FW_PS_STATE */
++
++	/* increase channel idx */
++	if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS))
++		ss->channel_idx++;
++
++	/* update scan state to next state (assigned by previous cmd hdl) */
++	if (mlmeext_scan_state(pmlmeext) != mlmeext_scan_next_state(pmlmeext))
++		mlmeext_set_scan_state(pmlmeext, mlmeext_scan_next_state(pmlmeext));
++
++operation_by_state:
++	switch (mlmeext_scan_state(pmlmeext)) {
++
++	case SCAN_DISABLE:
++		/*
++		* SW parameter initialization
++		*/
++
++		sitesurvey_res_reset(padapter, pparm);
++		mlmeext_set_scan_state(pmlmeext, SCAN_START);
++		goto operation_by_state;
++
++	case SCAN_START:
++#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++		if ((pwdev_priv->pno_mac_addr[0] != 0xFF)
++			    && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE)
++	    	    && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _FALSE)) {
++			u16 seq_num;
++
++			rtw_hal_pno_random_gen_mac_addr(padapter);
++			rtw_hal_set_hw_mac_addr(padapter, pwdev_priv->pno_mac_addr);
++			get_random_bytes(&seq_num, 2);
++			pwdev_priv->pno_scan_seq_num = seq_num & 0xFFF;
++			RTW_INFO("%s pno_scan_seq_num %d\n", __func__,
++				 pwdev_priv->pno_scan_seq_num);
++		}
++#endif
++
++		/*
++		* prepare to leave operating channel
++		*/
++
++#ifdef CONFIG_MCC_MODE
++		rtw_hal_set_mcc_setting_scan_start(padapter);
++#endif /* CONFIG_MCC_MODE */
++
++		/* apply rx ampdu setting */
++		if (ss->rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID
++			|| ss->rx_ampdu_size != RX_AMPDU_SIZE_INVALID)
++			rtw_rx_ampdu_apply(padapter);
++
++		/* clear HW TX queue before scan */
++		rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);
++
++		rtw_hal_macid_sleep_all_used(padapter);
++
++		/* power save state announcement */
++		if (rtw_ps_annc(padapter, 1)) {
++			mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT);
++			mlmeext_set_scan_next_state(pmlmeext, SCAN_ENTER);
++			set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */
++		} else {
++			mlmeext_set_scan_state(pmlmeext, SCAN_ENTER);
++			goto operation_by_state;
++		}
++
++		break;
++
++	case SCAN_ENTER:
++		/*
++		* HW register and DM setting for enter scan
++		*/
++
++		rtw_phydm_ability_backup(padapter);
++
++		sitesurvey_set_igi(padapter);
++
++		/* config dynamic functions for off channel */
++		rtw_phydm_func_for_offchannel(padapter);
++		/* set MSR to no link state */
++		sitesurvey_set_msr(padapter, _TRUE);
++
++		val8 = 1; /* under site survey */
++		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++
++		mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS);
++		goto operation_by_state;
++
++	case SCAN_PROCESS: {
++		u8 scan_ch;
++		RT_SCAN_TYPE scan_type;
++		u8 next_state;
++		u32 scan_ms;
++
++#ifdef CONFIG_RTW_ACS
++		if (IS_ACS_ENABLE(padapter))
++			rtw_acs_get_rst(padapter);
++#endif
++
++		next_state = sitesurvey_pick_ch_behavior(padapter, &scan_ch, &scan_type);
++
++		if (next_state != SCAN_PROCESS) {
++			mlmeext_set_scan_state(pmlmeext, next_state);
++			goto operation_by_state;
++		}
++
++		/* still SCAN_PROCESS state */
++		#ifdef DBG_SITESURVEY
++			#ifdef CONFIG_P2P
++			RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (cnt:%u,idx:%d) at %dms, %c%c%c%c\n"
++				, FUNC_ADPT_ARG(padapter)
++				, mlmeext_scan_state_str(pmlmeext)
++				, scan_ch
++				, pwdinfo->find_phase_state_exchange_cnt, ss->channel_idx
++				, rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time)
++				, scan_type ? 'A' : 'P', ss->scan_mode ? 'A' : 'P'
++				, ss->ssid[0].SsidLength ? 'S' : ' '
++				, ss->force_ssid_scan ? 'F' : ' '
++			);
++			#else
++			RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (idx:%d) at %dms, %c%c%c%c\n"
++				, FUNC_ADPT_ARG(padapter)
++				, mlmeext_scan_state_str(pmlmeext)
++				, scan_ch
++				, ss->channel_idx
++				, rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time)
++				, scan_type ? 'A' : 'P', ss->scan_mode ? 'A' : 'P'
++				, ss->ssid[0].SsidLength ? 'S' : ' '
++				, ss->force_ssid_scan ? 'F' : ' '
++			);
++			#endif /* CONFIG_P2P */
++		#endif /*DBG_SITESURVEY*/
++#ifdef DBG_FIXED_CHAN
++		if (pmlmeext->fixed_chan != 0xff)
++			RTW_INFO(FUNC_ADPT_FMT" fixed_chan:%u\n", pmlmeext->fixed_chan);
++#endif
++
++		site_survey(padapter, scan_ch, scan_type);
++
++#if defined(CONFIG_ATMEL_RC_PATCH)
++		if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++			scan_ms = 20;
++		else
++			scan_ms = 40;
++#else
++		#if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)
++		if (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter))
++			scan_ms = rtw_acs_get_adv_st(padapter);
++		else
++		#endif /*CONFIG_RTW_ACS*/
++			scan_ms = ss->scan_ch_ms;
++#endif
++
++#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)
++		if (ss->is_sw_antdiv_bl_scan)
++			scan_ms = scan_ms / 2;
++#endif
++
++#ifdef CONFIG_RTW_ACS
++		if (IS_ACS_ENABLE(padapter)) {
++			if (pparm->token)
++				rtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_IEEE_11K_HIGH);
++			else
++				rtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_ACS);
++		}
++#endif
++
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++		if (IS_NM_ENABLE(padapter))
++			rtw_noise_measure(padapter, scan_ch, _FALSE, 0, scan_ms / 2);
++#endif
++		set_survey_timer(pmlmeext, scan_ms);
++		break;
++	}
++
++#ifdef CONFIG_SCAN_BACKOP
++	case SCAN_BACKING_OP: {
++		u8 back_ch, back_bw, back_ch_offset;
++		u8 need_ch_setting_union = _TRUE;
++
++#ifdef CONFIG_MCC_MODE
++		need_ch_setting_union = rtw_hal_mcc_change_scan_flag(padapter,
++				&back_ch, &back_bw, &back_ch_offset);
++#endif /* CONFIG_MCC_MODE */
++
++		if (need_ch_setting_union) {
++			if (rtw_mi_get_ch_setting_union(padapter, &back_ch, &back_bw, &back_ch_offset) == 0) {
++				rtw_warn_on(1);
++				back_ch = pmlmeext->cur_channel;
++				back_bw = pmlmeext->cur_bwmode;
++				back_ch_offset = pmlmeext->cur_ch_offset;
++			}
++		}
++
++		#ifdef DBG_SITESURVEY
++			RTW_INFO(FUNC_ADPT_FMT" %s ch:%u, bw:%u, offset:%u at %dms\n"
++				 , FUNC_ADPT_ARG(padapter)
++				 , mlmeext_scan_state_str(pmlmeext)
++				 , back_ch, back_bw, back_ch_offset
++				, rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time)
++				);
++		#endif /*DBG_SITESURVEY*/
++		set_channel_bwmode(padapter, back_ch, back_ch_offset, back_bw);
++
++		sitesurvey_set_msr(padapter, _FALSE);
++
++		val8 = 0; /* survey done */
++		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++
++		if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) {
++			sitesurvey_set_igi(padapter);
++			rtw_hal_macid_wakeup_all_used(padapter);
++			rtw_ps_annc(padapter, 0);
++		}
++
++		mlmeext_set_scan_state(pmlmeext, SCAN_BACK_OP);
++		ss->backop_time = rtw_get_current_time();
++
++		if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_TX_RESUME))
++			rtw_mi_os_xmit_schedule(padapter);
++
++
++		goto operation_by_state;
++	}
++
++	case SCAN_BACK_OP:
++		if (rtw_get_passing_time_ms(ss->backop_time) >= ss->backop_ms
++		    || pmlmeext->scan_abort
++		   ) {
++			mlmeext_set_scan_state(pmlmeext, SCAN_LEAVING_OP);
++			goto operation_by_state;
++		}
++		set_survey_timer(pmlmeext, 50);
++		break;
++
++	case SCAN_LEAVING_OP:
++		/*
++		 * prepare to leave operating channel
++		 */
++
++		/* clear HW TX queue before scan */
++		rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);
++
++		rtw_hal_macid_sleep_all_used(padapter);
++		if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)
++			&& rtw_ps_annc(padapter, 1)
++		) {
++			mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT);
++			mlmeext_set_scan_next_state(pmlmeext, SCAN_LEAVE_OP);
++			set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */
++		} else {
++			mlmeext_set_scan_state(pmlmeext, SCAN_LEAVE_OP);
++			goto operation_by_state;
++		}
++
++		break;
++
++	case SCAN_LEAVE_OP:
++		/*
++		* HW register and DM setting for enter scan
++		*/
++
++		if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC))
++			sitesurvey_set_igi(padapter);
++
++		sitesurvey_set_msr(padapter, _TRUE);
++
++		val8 = 1; /* under site survey */
++		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++
++		mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS);
++		goto operation_by_state;
++
++#endif /* CONFIG_SCAN_BACKOP */
++
++#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)
++	case SCAN_SW_ANTDIV_BL:
++		/*
++		* 20100721
++		* For SW antenna diversity before link, it needs to switch to another antenna and scan again.
++		* It compares the scan result and select better one to do connection.
++		*/
++		ss->bss_cnt = 0;
++		ss->channel_idx = 0;
++		ss->is_sw_antdiv_bl_scan = 1;
++
++		mlmeext_set_scan_next_state(pmlmeext, SCAN_PROCESS);
++		set_survey_timer(pmlmeext, ss->scan_ch_ms);
++		break;
++#endif
++
++#ifdef CONFIG_P2P
++	case SCAN_TO_P2P_LISTEN:
++		/*
++		* Set the P2P State to the listen state of find phase
++		* and set the current channel to the listen channel
++		*/
++		set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++		rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_LISTEN);
++
++		/* turn on phy-dynamic functions */
++		rtw_phydm_ability_restore(padapter);
++
++		sitesurvey_set_igi(padapter);
++
++		mlmeext_set_scan_state(pmlmeext, SCAN_P2P_LISTEN);
++		_set_timer(&pwdinfo->find_phase_timer, (u32)((u32)pwdinfo->listen_dwell * 100));
++		break;
++
++	case SCAN_P2P_LISTEN:
++		mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS);
++		ss->channel_idx = 0;
++		goto operation_by_state;
++#endif /* CONFIG_P2P */
++
++	case SCAN_COMPLETE:
++#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++		rtw_hal_set_hw_mac_addr(padapter, adapter_mac_addr(padapter));
++#endif
++#ifdef CONFIG_P2P
++		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN)
++		    || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH)
++		   ) {
++#ifdef CONFIG_CONCURRENT_MODE
++			if (pwdinfo->driver_interface == DRIVER_WEXT) {
++				if (rtw_mi_check_status(padapter, MI_LINKED))
++					_set_timer(&pwdinfo->ap_p2p_switch_timer, 500);
++			}
++#endif
++
++			rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
++		}
++		rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);
++#endif /* CONFIG_P2P */
++
++		/* switch channel */
++		survey_done_set_ch_bw(padapter);
++
++		sitesurvey_set_msr(padapter, _FALSE);
++
++		val8 = 0; /* survey done */
++		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++
++		/* turn on phy-dynamic functions */
++		rtw_phydm_ability_restore(padapter);
++
++		sitesurvey_set_igi(padapter);
++
++#ifdef CONFIG_MCC_MODE
++		/* start MCC fail, then tx null data */
++		if (!rtw_hal_set_mcc_setting_scan_complete(padapter))
++#endif
++		{
++			rtw_hal_macid_wakeup_all_used(padapter);
++			rtw_ps_annc(padapter, 0);
++		}
++
++		/* apply rx ampdu setting */
++		rtw_rx_ampdu_apply(padapter);
++
++		mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE);
++
++		report_surveydone_event(padapter, ss->acs);
++#ifdef CONFIG_RTW_ACS
++		if (IS_ACS_ENABLE(padapter))
++			rtw_acs_select_best_chan(padapter);
++#endif
++
++#if defined(CONFIG_BACKGROUND_NOISE_MONITOR) && defined(DBG_NOISE_MONITOR)
++		if (IS_NM_ENABLE(padapter))
++			rtw_noise_info_dump(RTW_DBGDUMP, padapter);
++#endif
++		issue_action_BSSCoexistPacket(padapter);
++		issue_action_BSSCoexistPacket(padapter);
++		issue_action_BSSCoexistPacket(padapter);
++
++#ifdef CONFIG_RTW_80211K
++		if (ss->token)
++			rm_post_event(padapter, ss->token, RM_EV_survey_done);
++#endif /* CONFIG_RTW_80211K */
++
++		break;
++	}
++
++	return H2C_SUCCESS;
++}
++
++u8 setauth_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++	struct setauth_parm		*pparm = (struct setauth_parm *)pbuf;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	if (pparm->mode < 4)
++		pmlmeinfo->auth_algo = pparm->mode;
++
++	return	H2C_SUCCESS;
++}
++
++/*
++SEC CAM Entry format (32 bytes)
++DW0 - MAC_ADDR[15:0] | Valid[15] | MFB[14:8] | RSVD[7]  | GK[6] | MIC_KEY[5] | SEC_TYPE[4:2] | KID[1:0]
++DW0 - MAC_ADDR[15:0] | Valid[15] |RSVD[14:9] | RPT_MODE[8] | SPP_MODE[7]  | GK[6] | MIC_KEY[5] | SEC_TYPE[4:2] | KID[1:0] (92E/8812A/8814A)
++DW1 - MAC_ADDR[47:16]
++DW2 - KEY[31:0]
++DW3 - KEY[63:32]
++DW4 - KEY[95:64]
++DW5 - KEY[127:96]
++DW6 - RSVD
++DW7 - RSVD
++*/
++
++/*Set WEP key or Group Key*/
++u8 setkey_hdl(_adapter *padapter, u8 *pbuf)
++{
++	u16	ctrl = 0;
++	s16 cam_id = 0;
++	struct setkey_parm		*pparm = (struct setkey_parm *)pbuf;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	unsigned char null_addr[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
++	u8 *addr;
++	bool used = _FALSE;
++
++	/* main tx key for wep. */
++	if (pparm->set_tx)
++		pmlmeinfo->key_index = pparm->keyid;
++
++#ifndef SEC_DEFAULT_KEY_SEARCH
++	if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE))
++		cam_id = rtw_iface_bcmc_id_get(padapter);
++	else
++#endif
++		cam_id = rtw_camid_alloc(padapter, NULL, pparm->keyid, 1,
++			!!(pparm->algorithm & _SEC_TYPE_256_), &used);
++
++	if (cam_id < 0)
++		goto enable_mc;
++
++#ifdef SEC_DEFAULT_KEY_SEARCH
++	if (cam_id >= 0 && cam_id <= 3) {
++		/* default key camid */
++		addr = null_addr;
++	} else
++#endif
++	{
++		/* not default key camid */
++		if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) {
++			/* group TX, force sec cam entry_id */
++			addr = adapter_mac_addr(padapter);
++		} else {
++			/* group RX, searched by A2 (TA) */
++			addr = get_bssid(&padapter->mlmepriv);
++		}
++	}
++
++#ifdef CONFIG_LPS_PG
++	if (adapter_to_pwrctl(padapter)->lps_level == LPS_PG)
++		LPS_Leave(padapter, "SET_KEY");
++#endif
++
++	/* cam entry searched is pairwise key */
++	if (used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _FALSE) {
++		s16 camid_clr;
++
++		RTW_PRINT(FUNC_ADPT_FMT" group key with "MAC_FMT" id:%u the same key id as pairwise key\n"
++			, FUNC_ADPT_ARG(padapter), MAC_ARG(addr), pparm->keyid);
++
++		/* HW has problem to distinguish this group key with existing pairwise key, stop HW enc and dec for BMC */
++		rtw_camctl_set_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH);
++		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL);
++
++		/* clear group key */
++		while ((camid_clr = rtw_camid_search(padapter, addr, -1, 1)) >= 0) {
++			RTW_PRINT("clear group key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(addr), camid_clr);
++			clear_cam_entry(padapter, camid_clr);
++			rtw_camid_free(padapter, camid_clr);
++		}
++
++		goto enable_mc;
++	}
++
++	ctrl = BIT(15) | BIT(6) | ((pparm->algorithm & 0x07) << 2) | pparm->keyid;
++
++	RTW_PRINT("set group key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n"
++		, cam_id, MAC_ARG(addr), pparm->keyid, security_type_str(pparm->algorithm));
++
++	if (pparm->algorithm & _SEC_TYPE_256_)  {
++		RTW_INFO_DUMP("GTK : ", pparm->key, sizeof(pparm->key));
++		ctrl |= BIT(9);
++	}	
++
++	write_cam(padapter, cam_id, ctrl, addr, pparm->key);
++
++	/* if ((cam_id > 3) && (((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)))*/
++#ifndef SEC_DEFAULT_KEY_SEARCH
++	if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) {
++		if (is_wep_enc(pparm->algorithm)) {
++			padapter->securitypriv.dot11Def_camid[pparm->keyid] = cam_id;
++			padapter->securitypriv.dot118021x_bmc_cam_id =
++				padapter->securitypriv.dot11Def_camid[padapter->securitypriv.dot11PrivacyKeyIndex];
++			RTW_PRINT("wep group key - force camid:%d\n", padapter->securitypriv.dot118021x_bmc_cam_id);
++		} else {
++			/*u8 org_cam_id = padapter->securitypriv.dot118021x_bmc_cam_id;*/
++
++			/*force GK's cam id*/
++			padapter->securitypriv.dot118021x_bmc_cam_id = cam_id;
++
++			/* for GTK rekey
++			if ((org_cam_id != INVALID_SEC_MAC_CAM_ID) &&
++				(org_cam_id != cam_id)) {
++				RTW_PRINT("clear group key for addr:"MAC_FMT", org_camid:%d new_camid:%d\n", MAC_ARG(addr), org_cam_id, cam_id);
++				clear_cam_entry(padapter, org_cam_id);
++				rtw_camid_free(padapter, org_cam_id);
++			}*/
++		}
++	}
++#else
++	if (cam_id >= 0 && cam_id <= 3)
++		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8 *)_TRUE);
++#endif
++
++	/* 8814au should set both broadcast and unicast CAM entry for WEP key in STA mode */
++	if (is_wep_enc(pparm->algorithm) && check_mlmeinfo_state(pmlmeext, WIFI_FW_STATION_STATE) &&
++	    _rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_BMC)) {
++		struct set_stakey_parm	sta_pparm;
++
++		_rtw_memset(&sta_pparm, 0, sizeof(struct set_stakey_parm));
++		sta_pparm.algorithm = pparm->algorithm;
++		sta_pparm.keyid = pparm->keyid;
++		_rtw_memcpy(sta_pparm.key, pparm->key, 16);
++		_rtw_memcpy(sta_pparm.addr, get_bssid(&padapter->mlmepriv), ETH_ALEN);
++		set_stakey_hdl(padapter, (u8 *)&sta_pparm);
++	}
++
++enable_mc:
++	/* allow multicast packets to driver */
++	rtw_hal_set_hwreg(padapter, HW_VAR_ON_RCR_AM, null_addr);
++
++	return H2C_SUCCESS;
++}
++
++void rtw_ap_wep_pk_setting(_adapter *adapter, struct sta_info *psta)
++{
++	struct security_priv *psecuritypriv = &(adapter->securitypriv);
++	struct set_stakey_parm	sta_pparm;
++	sint keyid;
++
++	if (!is_wep_enc(psecuritypriv->dot11PrivacyAlgrthm))
++		return;
++
++	for (keyid = 0; keyid < 4; keyid++) {
++		if ((psecuritypriv->key_mask & BIT(keyid)) && (keyid == psecuritypriv->dot11PrivacyKeyIndex)) {
++			sta_pparm.algorithm = psecuritypriv->dot11PrivacyAlgrthm;
++			sta_pparm.keyid = keyid;
++			sta_pparm.gk = 0;
++			_rtw_memcpy(sta_pparm.key, &(psecuritypriv->dot11DefKey[keyid].skey[0]), 16);
++			_rtw_memcpy(sta_pparm.addr, psta->cmn.mac_addr, ETH_ALEN);
++
++			RTW_PRINT(FUNC_ADPT_FMT"set WEP - PK with "MAC_FMT" keyid:%u\n"
++				, FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr), keyid);
++
++			set_stakey_hdl(adapter, (u8 *)&sta_pparm);
++		}
++	}
++}
++
++u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf)
++{
++	u16 ctrl = 0;
++	s16 cam_id = 0;
++	bool used;
++	u8 ret = H2C_SUCCESS;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct set_stakey_parm	*pparm = (struct set_stakey_parm *)pbuf;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct sta_info *psta;
++
++	if (pparm->algorithm == _NO_PRIVACY_)
++		goto write_to_cam;
++
++	psta = rtw_get_stainfo(pstapriv, pparm->addr);
++	if (!psta) {
++		RTW_PRINT("%s sta:"MAC_FMT" not found\n", __func__, MAC_ARG(pparm->addr));
++		ret = H2C_REJECTED;
++		goto exit;
++	}
++
++	pmlmeinfo->enc_algo = pparm->algorithm;
++
++	cam_id = rtw_camid_alloc(padapter, psta, pparm->keyid, pparm->gk,
++		!!(pparm->algorithm & _SEC_TYPE_256_), &used);
++	if (cam_id < 0)
++		goto exit;
++
++#ifdef CONFIG_LPS_PG
++	if (adapter_to_pwrctl(padapter)->lps_level == LPS_PG)
++		LPS_Leave(padapter, "SET_KEY");
++#endif
++
++	/* cam entry searched is group key when setting pariwise key */
++	if (!pparm->gk && used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _TRUE) {
++		s16 camid_clr;
++
++		RTW_PRINT(FUNC_ADPT_FMT" pairwise key with "MAC_FMT" id:%u the same key id as group key\n"
++			, FUNC_ADPT_ARG(padapter), MAC_ARG(pparm->addr), pparm->keyid);
++
++		/* HW has problem to distinguish this pairwise key with existing group key, stop HW enc and dec for BMC */
++		rtw_camctl_set_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH);
++		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL);
++
++		/* clear group key */
++		while ((camid_clr = rtw_camid_search(padapter, pparm->addr, -1, 1)) >= 0) {
++			RTW_PRINT("clear group key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(pparm->addr), camid_clr);
++			clear_cam_entry(padapter, camid_clr);
++			rtw_camid_free(padapter, camid_clr);
++		}
++	}
++
++write_to_cam:
++	if (pparm->algorithm == _NO_PRIVACY_) {
++		while ((cam_id = rtw_camid_search(padapter, pparm->addr, -1, -1)) >= 0) {
++			RTW_PRINT("clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(pparm->addr), cam_id);
++			clear_cam_entry(padapter, cam_id);
++			rtw_camid_free(padapter, cam_id);
++		}
++	} else {
++		RTW_PRINT("set %s key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n"
++			, pparm->gk ? "group" : "pairwise"
++			, cam_id, MAC_ARG(pparm->addr), pparm->keyid, security_type_str(pparm->algorithm));
++		ctrl = BIT(15) | ((pparm->algorithm & 0x07) << 2) | pparm->keyid;
++		if (pparm->gk)
++			ctrl |= BIT(6);
++		if (pparm->algorithm & _SEC_TYPE_256_) {
++			RTW_INFO_DUMP("PTK : ", pparm->key, sizeof(pparm->key));
++			ctrl |= BIT(9);
++		}
++
++		write_cam(padapter, cam_id, ctrl, pparm->addr, pparm->key);
++	}
++	ret = H2C_SUCCESS_RSP;
++
++exit:
++	return ret;
++}
++
++u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++	struct addBaReq_parm	*pparm = (struct addBaReq_parm *)pbuf;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, pparm->addr);
++
++	if (!psta)
++		return	H2C_SUCCESS;
++
++#ifdef CONFIG_80211N_HT
++	if (((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && (pmlmeinfo->HT_enable)) ||
++	    ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {
++		/* pmlmeinfo->ADDBA_retry_count = 0; */
++		/* pmlmeinfo->candidate_tid_bitmap |= (0x1 << pparm->tid);		 */
++		/* psta->htpriv.candidate_tid_bitmap |= BIT(pparm->tid); */
++		issue_addba_req(padapter, pparm->addr, (u8)pparm->tid);
++		_set_timer(&psta->addba_retry_timer, ADDBA_TO);
++	}
++#ifdef CONFIG_TDLS
++	else if ((psta->tdls_sta_state & TDLS_LINKED_STATE) &&
++		 (psta->htpriv.ht_option == _TRUE) &&
++		 (psta->htpriv.ampdu_enable == _TRUE)) {
++		issue_addba_req(padapter, pparm->addr, (u8)pparm->tid);
++		_set_timer(&psta->addba_retry_timer, ADDBA_TO);
++	}
++#endif /* CONFIG */
++	else
++		psta->htpriv.candidate_tid_bitmap &= ~BIT(pparm->tid);
++#endif /* CONFIG_80211N_HT */
++	return	H2C_SUCCESS;
++}
++
++
++u8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++	struct addBaRsp_parm *pparm = (struct addBaRsp_parm *)pbuf;
++	struct recv_reorder_ctrl *preorder_ctrl;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct sta_info *psta;
++	u8 ret = _TRUE;
++
++	psta = rtw_get_stainfo(pstapriv, pparm->addr);
++	if (!psta)
++		goto exit;
++
++	preorder_ctrl = &psta->recvreorder_ctrl[pparm->tid];
++	ret = issue_addba_rsp_wait_ack(padapter, pparm->addr, pparm->tid, pparm->status, pparm->size, 3, 50);
++
++#ifdef CONFIG_UPDATE_INDICATE_SEQ_WHILE_PROCESS_ADDBA_REQ
++	/* status = 0 means accept this addba req, so update indicate seq = start_seq under this compile flag */
++	if (pparm->status == 0) {
++		preorder_ctrl->indicate_seq = pparm->start_seq;
++		#ifdef DBG_RX_SEQ
++		RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_UPDATE indicate_seq:%d, start_seq:%d\n"
++			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pparm->start_seq);
++		#endif
++	}
++#else
++	rtw_set_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack);
++	#ifdef DBG_RX_SEQ
++	RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%d, start_seq:%d preorder_ctrl->rec_abba_rsp_ack =%lu \n"
++		, FUNC_ADPT_ARG(padapter)
++		, preorder_ctrl->tid
++		, preorder_ctrl->indicate_seq
++		, pparm->start_seq
++		,preorder_ctrl->rec_abba_rsp_ack
++		);
++	#endif
++#endif
++
++	/*
++	  * status = 0 means accept this addba req
++	  * status = 37 means reject this addba req
++	  */
++	if (pparm->status == 0) {
++		preorder_ctrl->enable = _TRUE;
++		preorder_ctrl->ampdu_size = pparm->size;
++	} else if (pparm->status == 37)
++		preorder_ctrl->enable = _FALSE;
++
++exit:
++	return H2C_SUCCESS;
++}
++
++u8 chk_bmc_sleepq_cmd(_adapter *padapter)
++{
++	struct cmd_obj *ph2c;
++	struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
++	u8 res = _SUCCESS;
++
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	init_h2fwcmd_w_parm_no_parm_rsp(ph2c, CMD_CHK_BMCSLEEPQ);
++
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++
++
++	return res;
++}
++
++u8 set_tx_beacon_cmd(_adapter *padapter, u8 flags)
++{
++	struct cmd_obj	*ph2c;
++	struct Tx_Beacon_param	*ptxBeacon_parm;
++	struct cmd_priv	*pcmdpriv = &(padapter->cmdpriv);
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct submit_ctx sctx;
++	u8	res = _SUCCESS;
++	int len_diff = 0;
++
++	/*prepare cmd parameter*/
++	ptxBeacon_parm = (struct Tx_Beacon_param *)rtw_zmalloc(sizeof(struct Tx_Beacon_param));
++	if (ptxBeacon_parm == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	_rtw_memcpy(&(ptxBeacon_parm->network), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX));
++
++	len_diff = update_hidden_ssid(
++			   ptxBeacon_parm->network.IEs + _BEACON_IE_OFFSET_
++		   , ptxBeacon_parm->network.IELength - _BEACON_IE_OFFSET_
++			   , pmlmeinfo->hidden_ssid_mode
++		   );
++	ptxBeacon_parm->network.IELength += len_diff;
++
++
++	/* need enqueue, prepare cmd_obj and enqueue */
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL) {
++		res = _FAIL;
++		rtw_mfree((u8 *)ptxBeacon_parm, sizeof(*ptxBeacon_parm));
++		goto exit;
++	}
++
++	init_h2fwcmd_w_parm_no_rsp(ph2c, ptxBeacon_parm, CMD_TX_BEACON);
++
++	if (flags & RTW_CMDF_WAIT_ACK) {
++		ph2c->sctx = &sctx;
++		rtw_sctx_init(&sctx, 10 * 1000);
++	}
++
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++	if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
++		rtw_sctx_wait(&sctx, __func__);
++		_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++		if (sctx.status == RTW_SCTX_SUBMITTED)
++			ph2c->sctx = NULL;
++		_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
++	}
++	
++
++exit:
++
++
++	return res;
++}
++
++
++u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++	struct rtw_evt_header *evt_hdr;
++	u8 *peventbuf;
++	void (*event_callback)(_adapter *dev, u8 *pbuf);
++	struct evt_priv *pevt_priv = &(padapter->evtpriv);
++
++	if (pbuf == NULL)
++		goto _abort_event_;
++
++	evt_hdr = (struct rtw_evt_header *)pbuf;
++	peventbuf = pbuf + sizeof(struct rtw_evt_header);
++
++#ifdef CHECK_EVENT_SEQ
++	/* checking event sequence...		 */
++	if (evt_hdr->seq != (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f)) {
++		pevt_priv->event_seq = (evt_hdr->seq + 1) & 0x7f;
++		goto _abort_event_;
++	}
++#endif
++
++	/* checking if event code is valid */
++	if (evt_hdr->id >= EVT_ID_MAX) {
++		goto _abort_event_;
++	}
++
++	/* checking if event size match the event parm size	 */
++	if ((wlanevents[evt_hdr->id].parmsize != 0) &&
++	    (wlanevents[evt_hdr->id].parmsize != evt_hdr->len)) {
++
++		goto _abort_event_;
++
++	}
++
++	ATOMIC_INC(&pevt_priv->event_seq);
++
++	if (peventbuf) {
++		event_callback = wlanevents[evt_hdr->id].event_callback;
++		event_callback(padapter, (u8 *)peventbuf);
++		pevt_priv->evt_done_cnt++;
++	}
++
++_abort_event_:
++	return H2C_SUCCESS;
++
++}
++
++u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++#ifdef CONFIG_AP_MODE
++	_irqL irqL;
++	struct sta_info *psta_bmc;
++	_list	*xmitframe_plist, *xmitframe_phead;
++	struct xmit_frame *pxmitframe = NULL;
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	struct sta_priv  *pstapriv = &padapter->stapriv;
++
++	/* for BC/MC Frames */
++	psta_bmc = rtw_get_bcmc_stainfo(padapter);
++	if (!psta_bmc)
++		return H2C_SUCCESS;
++
++	if ((rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) && (psta_bmc->sleepq_len > 0)) {
++#ifndef CONFIG_PCI_HCI
++		rtw_msleep_os(10);/* 10ms, ATIM(HIQ) Windows */
++#endif
++		/* _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); */
++		_enter_critical_bh(&pxmitpriv->lock, &irqL);
++
++		xmitframe_phead = get_list_head(&psta_bmc->sleep_q);
++		xmitframe_plist = get_next(xmitframe_phead);
++
++		while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
++			pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
++
++			xmitframe_plist = get_next(xmitframe_plist);
++
++			rtw_list_delete(&pxmitframe->list);
++
++			psta_bmc->sleepq_len--;
++			if (psta_bmc->sleepq_len > 0)
++				pxmitframe->attrib.mdata = 1;
++			else
++				pxmitframe->attrib.mdata = 0;
++
++			pxmitframe->attrib.triggered = 1;
++
++			if (xmitframe_hiq_filter(pxmitframe) == _TRUE)
++				pxmitframe->attrib.qsel = QSLT_HIGH;/* HIQ */
++
++#if 0
++			_exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
++			if (rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
++				rtw_os_xmit_complete(padapter, pxmitframe);
++			_enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
++#endif
++			rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
++		}
++
++		/* _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); */
++		_exit_critical_bh(&pxmitpriv->lock, &irqL);
++
++		if (rtw_get_intf_type(padapter) != RTW_PCIE) {
++			/* check hi queue and bmc_sleepq */
++			rtw_chk_hi_queue_cmd(padapter);
++		}
++	}
++#endif
++
++	return H2C_SUCCESS;
++}
++
++u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++	/*RTW_INFO(FUNC_ADPT_FMT, FUNC_ADPT_ARG(padapter));*/
++#ifdef CONFIG_SWTIMER_BASED_TXBCN
++
++	tx_beacon_handlder(padapter->dvobj);
++
++#else
++
++	if (send_beacon(padapter) == _FAIL) {
++		RTW_INFO("issue_beacon, fail!\n");
++		return H2C_PARAMETERS_ERROR;
++	}
++
++	/* tx bc/mc frames after update TIM */
++	chk_bmc_sleepq_hdl(padapter, NULL);
++#endif
++
++	return H2C_SUCCESS;
++}
++
++/*
++* according to channel
++* add/remove WLAN_BSSID_EX.IEs's ERP ie
++* set WLAN_BSSID_EX.SupportedRates
++* update WLAN_BSSID_EX.IEs's Supported Rate and Extended Supported Rate ie
++*/
++void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch)
++{
++	u8	network_type, rate_len, total_rate_len, remainder_rate_len;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	u8	erpinfo = 0x4;
++
++	if (ch >= 36) {
++		network_type = WIRELESS_11A;
++		total_rate_len = IEEE80211_NUM_OFDM_RATESLEN;
++		rtw_remove_bcn_ie(padapter, pnetwork, _ERPINFO_IE_);
++		#ifdef CONFIG_80211AC_VHT
++		/* if channel in 5G band, then add vht ie . */
++		if ((pmlmepriv->htpriv.ht_option == _TRUE)
++			&& REGSTY_IS_11AC_ENABLE(&padapter->registrypriv)
++			&& is_supported_vht(padapter->registrypriv.wireless_mode)
++			&& (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
++		) {
++			if (REGSTY_IS_11AC_AUTO(&padapter->registrypriv)
++				|| pmlmepriv->ori_vht_en)
++				rtw_vht_ies_attach(padapter, pnetwork);
++		}
++		#endif
++	} else {
++		network_type = 0;
++		total_rate_len = 0;
++		if (padapter->registrypriv.wireless_mode & WIRELESS_11B) {
++			network_type |= WIRELESS_11B;
++			total_rate_len += IEEE80211_CCK_RATE_LEN;
++		}
++		if (padapter->registrypriv.wireless_mode & WIRELESS_11G) {
++			network_type |= WIRELESS_11G;
++			total_rate_len += IEEE80211_NUM_OFDM_RATESLEN;
++		}
++		rtw_add_bcn_ie(padapter, pnetwork, _ERPINFO_IE_, &erpinfo, 1);
++		#ifdef CONFIG_80211AC_VHT
++		rtw_vht_ies_detach(padapter, pnetwork);
++		#endif
++	}
++
++	rtw_set_supported_rate(pnetwork->SupportedRates, network_type);
++
++	UpdateBrateTbl(padapter, pnetwork->SupportedRates);
++
++	if (total_rate_len > 8) {
++		rate_len = 8;
++		remainder_rate_len = total_rate_len - 8;
++	} else {
++		rate_len = total_rate_len;
++		remainder_rate_len = 0;
++	}
++
++	rtw_add_bcn_ie(padapter, pnetwork, _SUPPORTEDRATES_IE_, pnetwork->SupportedRates, rate_len);
++
++	if (remainder_rate_len)
++		rtw_add_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_, (pnetwork->SupportedRates + 8), remainder_rate_len);
++	else
++		rtw_remove_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_);
++
++	pnetwork->Length = get_WLAN_BSSID_EX_sz(pnetwork);
++}
++
++void rtw_join_done_chk_ch(_adapter *adapter, int join_res)
++{
++#define DUMP_ADAPTERS_STATUS 0
++
++	struct dvobj_priv *dvobj;
++	_adapter *iface;
++	struct mlme_priv *mlme;
++	struct mlme_ext_priv *mlmeext;
++	u8 u_ch, u_offset, u_bw;
++	int i, ret;
++
++	dvobj = adapter_to_dvobj(adapter);
++
++	if (DUMP_ADAPTERS_STATUS) {
++		RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(adapter));
++		dump_adapters_status(RTW_DBGDUMP , dvobj);
++	}
++
++	ret = rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset);
++	if (join_res >= 0 && ret <= 0) {
++		join_res = -1;
++		dump_adapters_status(RTW_DBGDUMP , dvobj);
++		rtw_warn_on(1);
++	}
++
++	if (join_res >= 0) {
++#ifdef CONFIG_MCC_MODE
++		/* MCC setting success, don't go to ch union process */
++		if (rtw_hal_set_mcc_setting_join_done_chk_ch(adapter))
++			return;
++#endif /* CONFIG_MCC_MODE */
++
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			iface = dvobj->padapters[i];
++			mlme = &iface->mlmepriv;
++			mlmeext = &iface->mlmeextpriv;
++
++			if (!iface || iface == adapter)
++				continue;
++
++			if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))
++				&& check_fwstate(mlme, WIFI_ASOC_STATE)
++			) {
++				u8 ori_ch, ori_bw, ori_offset;
++				bool is_grouped = rtw_is_chbw_grouped(u_ch, u_bw, u_offset
++					, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
++
++				if (is_grouped == _FALSE) {
++					/* handle AP which need to switch ch setting */
++
++					ori_ch = mlmeext->cur_channel;
++					ori_bw = mlmeext->cur_bwmode;
++					ori_offset = mlmeext->cur_ch_offset;
++
++					/* restore original bw, adjust bw by registry setting on target ch */
++					mlmeext->cur_bwmode = mlme->ori_bw;
++					mlmeext->cur_channel = u_ch;
++					rtw_adjust_chbw(iface, mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset);
++					#ifdef CONFIG_RTW_MESH
++					if (MLME_IS_MESH(iface))
++						rtw_mesh_adjust_chbw(mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset);
++					#endif
++
++					rtw_chset_sync_chbw(adapter_to_chset(adapter)
++						, &mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset
++						, &u_ch, &u_bw, &u_offset, 1, 0);
++
++					RTW_INFO(FUNC_ADPT_FMT" %u,%u,%u => %u,%u,%u\n", FUNC_ADPT_ARG(iface)
++						, ori_ch, ori_bw, ori_offset
++						, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
++
++					rtw_ap_update_bss_chbw(iface, &(mlmeext->mlmext_info.network)
++						, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
++
++					_rtw_memcpy(&(mlme->cur_network.network), &(mlmeext->mlmext_info.network), sizeof(WLAN_BSSID_EX));
++
++					rtw_start_bss_hdl_after_chbw_decided(iface);
++
++					{
++						#if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++						u8 ht_option = 0;
++
++						#ifdef CONFIG_80211N_HT
++						ht_option = mlme->htpriv.ht_option;
++						#endif
++
++						rtw_cfg80211_ch_switch_notify(iface
++							, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset
++							, ht_option, 0);
++						#endif
++					}
++				}
++
++				clr_fwstate(mlme, WIFI_OP_CH_SWITCHING);
++				update_beacon(iface, 0xFF, NULL, _TRUE, 0);
++			}
++		}
++
++#ifdef CONFIG_DFS_MASTER
++		rtw_dfs_rd_en_decision(adapter, MLME_STA_CONNECTED, 0);
++#endif
++	} else {
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			iface = dvobj->padapters[i];
++			mlme = &iface->mlmepriv;
++			mlmeext = &iface->mlmeextpriv;
++
++			if (!iface || iface == adapter)
++				continue;
++
++			if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))
++				&& check_fwstate(mlme, WIFI_ASOC_STATE)
++			) {
++				clr_fwstate(mlme, WIFI_OP_CH_SWITCHING);
++				update_beacon(iface, 0xFF, NULL, _TRUE, 0);
++			}
++		}
++#ifdef CONFIG_DFS_MASTER
++		rtw_dfs_rd_en_decision(adapter, MLME_STA_DISCONNECTED, 0);
++#endif
++	}
++
++	if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset)) {
++		RTW_INFO(FUNC_ADPT_FMT" union:%u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset);
++		set_channel_bwmode(adapter, u_ch, u_offset, u_bw);
++		rtw_mi_update_union_chan_inf(adapter, u_ch, u_offset, u_bw);
++	}
++
++	if (DUMP_ADAPTERS_STATUS) {
++		RTW_INFO(FUNC_ADPT_FMT" exit\n", FUNC_ADPT_ARG(adapter));
++		dump_adapters_status(RTW_DBGDUMP , dvobj);
++	}
++}
++
++int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset)
++{
++#ifdef CONFIG_CONCURRENT_MODE
++	bool chbw_allow = _TRUE;
++#endif
++	bool connect_allow = _TRUE;
++	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
++	u8 cur_ch, cur_bw, cur_ch_offset;
++	u8 u_ch, u_offset, u_bw;
++
++	u_ch = cur_ch = pmlmeext->cur_channel;
++	u_bw = cur_bw = pmlmeext->cur_bwmode;
++	u_offset = cur_ch_offset = pmlmeext->cur_ch_offset;
++
++	if (!ch || !bw || !offset) {
++		connect_allow = _FALSE;
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (cur_ch == 0) {
++		connect_allow = _FALSE;
++		RTW_ERR(FUNC_ADPT_FMT" cur_ch:%u\n"
++			, FUNC_ADPT_ARG(adapter), cur_ch);
++		rtw_warn_on(1);
++		goto exit;
++	}
++	RTW_INFO(FUNC_ADPT_FMT" req: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset);
++
++#ifdef CONFIG_CONCURRENT_MODE
++	{
++		struct dvobj_priv *dvobj;
++		_adapter *iface;
++		struct mlme_priv *mlme;
++		struct mlme_ext_priv *mlmeext;
++		struct mi_state mstate;
++		int i;
++
++		dvobj = adapter_to_dvobj(adapter);
++
++		rtw_mi_status_no_self(adapter, &mstate);
++		RTW_INFO(FUNC_ADPT_FMT" others ld_sta_num:%u, ap_num:%u, mesh_num:%u\n"
++			, FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate)
++			, MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate));
++
++		if (!MSTATE_STA_LD_NUM(&mstate) && !MSTATE_AP_NUM(&mstate) && !MSTATE_MESH_NUM(&mstate)) {
++			/* consider linking STA? */
++			goto connect_allow_hdl;
++		}
++
++		if (rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset) <= 0) {
++			dump_adapters_status(RTW_DBGDUMP , dvobj);
++			rtw_warn_on(1);
++		}
++		RTW_INFO(FUNC_ADPT_FMT" others union:%u,%u,%u\n"
++			 , FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset);
++
++		/* chbw_allow? */
++		chbw_allow = rtw_is_chbw_grouped(pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset
++						 , u_ch, u_bw, u_offset);
++
++		RTW_INFO(FUNC_ADPT_FMT" chbw_allow:%d\n"
++			 , FUNC_ADPT_ARG(adapter), chbw_allow);
++
++#ifdef CONFIG_MCC_MODE
++		/* check setting success, don't go to ch union process */
++		if (rtw_hal_set_mcc_setting_chk_start_clnt_join(adapter, &u_ch, &u_bw, &u_offset, chbw_allow))
++			goto exit;
++#endif
++
++		if (chbw_allow == _TRUE) {
++			rtw_sync_chbw(&cur_ch, &cur_bw, &cur_ch_offset, &u_ch, &u_bw, &u_offset);
++			rtw_warn_on(cur_ch != pmlmeext->cur_channel);
++			rtw_warn_on(cur_bw != pmlmeext->cur_bwmode);
++			rtw_warn_on(cur_ch_offset != pmlmeext->cur_ch_offset);
++			goto connect_allow_hdl;
++		}
++
++#ifdef CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT
++		/* chbw_allow is _FALSE, connect allow? */
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			iface = dvobj->padapters[i];
++			mlme = &iface->mlmepriv;
++			mlmeext = &iface->mlmeextpriv;
++
++			if (check_fwstate(mlme, WIFI_STATION_STATE)
++			    && check_fwstate(mlme, WIFI_ASOC_STATE)
++#if defined(CONFIG_P2P)
++			    && rtw_p2p_chk_state(&(iface->wdinfo), P2P_STATE_NONE)
++#endif
++			   ) {
++				connect_allow = _FALSE;
++				break;
++			}
++		}
++#endif /* CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT */
++
++		if (MSTATE_STA_LD_NUM(&mstate) + MSTATE_AP_LD_NUM(&mstate) + MSTATE_MESH_LD_NUM(&mstate) >= 4)
++			connect_allow = _FALSE;
++
++		RTW_INFO(FUNC_ADPT_FMT" connect_allow:%d\n"
++			 , FUNC_ADPT_ARG(adapter), connect_allow);
++
++		if (connect_allow == _FALSE)
++			goto exit;
++
++connect_allow_hdl:
++		/* connect_allow == _TRUE */
++
++		if (chbw_allow == _FALSE) {
++			u_ch = cur_ch;
++			u_bw = cur_bw;
++			u_offset = cur_ch_offset;
++
++			for (i = 0; i < dvobj->iface_nums; i++) {
++				iface = dvobj->padapters[i];
++				mlme = &iface->mlmepriv;
++				mlmeext = &iface->mlmeextpriv;
++
++				if (!iface || iface == adapter)
++					continue;
++
++				if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))
++					&& check_fwstate(mlme, WIFI_ASOC_STATE)
++				) {
++					#ifdef CONFIG_SPCT_CH_SWITCH
++					if (1)
++						rtw_ap_inform_ch_switch(iface, pmlmeext->cur_channel , pmlmeext->cur_ch_offset);
++					else
++					#endif
++						rtw_sta_flush(iface, _FALSE);
++
++					rtw_hal_set_hwreg(iface, HW_VAR_CHECK_TXBUF, 0);
++					set_fwstate(mlme, WIFI_OP_CH_SWITCHING);
++
++				} else if (check_fwstate(mlme, WIFI_STATION_STATE)
++					&& check_fwstate(mlme, WIFI_ASOC_STATE)
++				) {
++					rtw_disassoc_cmd(iface, 500, RTW_CMDF_DIRECTLY);
++					rtw_indicate_disconnect(iface, 0, _FALSE);
++					rtw_free_assoc_resources(iface, _TRUE);
++				}
++			}
++		}
++
++		#ifdef CONFIG_DFS_MASTER
++		rtw_dfs_rd_en_decision(adapter, MLME_STA_CONNECTING, 0);
++		#endif
++	}
++#endif /* CONFIG_CONCURRENT_MODE */
++
++exit:
++
++	if (connect_allow == _TRUE) {
++		RTW_INFO(FUNC_ADPT_FMT" union: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset);
++		*ch = u_ch;
++		*bw = u_bw;
++		*offset = u_offset;
++
++#if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++		{
++			u8 ht_option = 0;
++
++#ifdef CONFIG_80211N_HT
++			ht_option = adapter->mlmepriv.htpriv.ht_option;
++#endif /* CONFIG_80211N_HT */
++
++			/*
++				when supplicant send the mlme frame,
++				the bss freq is updated by channel switch event.
++			*/
++			rtw_cfg80211_ch_switch_notify(adapter,
++				cur_ch, cur_bw, cur_ch_offset, ht_option, 1);
++		}
++#endif
++	}
++
++	return connect_allow == _TRUE ? _SUCCESS : _FAIL;
++}
++
++void rtw_set_external_auth_status(_adapter *padapter,
++	const void *data, int len)
++{
++#ifdef CONFIG_IOCTL_CFG80211
++	struct net_device *dev = padapter->pnetdev;
++	struct wiphy *wiphy = adapter_to_wiphy(padapter);
++	struct rtw_external_auth_params params;
++
++	/* convert data to external_auth_params */
++	params.action = RTW_GET_BE32((u8 *)data);
++	_rtw_memcpy(&params.bssid, (u8 *)data + 4, ETH_ALEN);
++	_rtw_memcpy(&params.ssid.ssid, (u8 *)data + 10, WLAN_SSID_MAXLEN);
++	params.ssid.ssid_len = RTW_GET_BE64((u8 *)data + 42);
++	params.key_mgmt_suite = RTW_GET_BE32((u8 *)data + 58);
++	params.status = RTW_GET_BE16((u8 *)data + 62);
++	_rtw_memcpy(&params.pmkid, (u8 *)data + 64, PMKID_LEN);
++
++	rtw_cfg80211_external_auth_status(wiphy, dev, &params);
++#endif /* CONFIG_IOCTL_CFG80211 */
++}
++
++u8 rtw_set_chbw_hdl(_adapter *padapter, u8 *pbuf)
++{
++	struct set_ch_parm *set_ch_parm;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++
++	if (!pbuf)
++		return H2C_PARAMETERS_ERROR;
++
++	set_ch_parm = (struct set_ch_parm *)pbuf;
++
++	RTW_INFO(FUNC_NDEV_FMT" ch:%u, bw:%u, ch_offset:%u\n",
++		 FUNC_NDEV_ARG(padapter->pnetdev),
++		 set_ch_parm->ch, set_ch_parm->bw, set_ch_parm->ch_offset);
++
++	pmlmeext->cur_channel = set_ch_parm->ch;
++	pmlmeext->cur_ch_offset = set_ch_parm->ch_offset;
++	pmlmeext->cur_bwmode = set_ch_parm->bw;
++
++	set_channel_bwmode(padapter, set_ch_parm->ch, set_ch_parm->ch_offset, set_ch_parm->bw);
++
++	return	H2C_SUCCESS;
++}
++
++u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++	struct SetChannelPlan_param *setChannelPlan_param;
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++
++	if (!pbuf)
++		return H2C_PARAMETERS_ERROR;
++
++	setChannelPlan_param = (struct SetChannelPlan_param *)pbuf;
++
++	if (!rtw_is_channel_plan_valid(setChannelPlan_param->channel_plan))
++		return H2C_PARAMETERS_ERROR;
++
++	rfctl->country_ent = setChannelPlan_param->country_ent;
++	rfctl->ChannelPlan = setChannelPlan_param->channel_plan;
++
++	rfctl->max_chan_nums = init_channel_set(padapter, rfctl->ChannelPlan, rfctl->channel_set);
++	rfctl->cur_spt_op_class_num = init_op_class_ch_bmp(padapter, rfctl->channel_set, rfctl->cur_spt_op_class_ch_bmp);
++	init_channel_list(padapter, rfctl->channel_set, &rfctl->channel_list);
++#if CONFIG_TXPWR_LIMIT
++	rtw_txpwr_init_regd(rfctl);
++#endif
++
++	rtw_hal_set_odm_var(padapter, HAL_ODM_REGULATION, NULL, _TRUE);
++
++#ifdef CONFIG_IOCTL_CFG80211
++	rtw_regd_apply_flags(adapter_to_wiphy(padapter));
++#endif
++
++	return	H2C_SUCCESS;
++}
++
++u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++	struct LedBlink_param *ledBlink_param;
++
++	if (!pbuf)
++		return H2C_PARAMETERS_ERROR;
++
++	ledBlink_param = (struct LedBlink_param *)pbuf;
++
++#ifdef CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD
++	BlinkHandler((PLED_DATA)ledBlink_param->pLed);
++#endif
++
++	return	H2C_SUCCESS;
++}
++
++u8 set_csa_hdl(_adapter *adapter, unsigned char *pbuf)
++{
++#if CONFIG_DFS
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++
++	if (rfctl->csa_ch)
++		rtw_dfs_ch_switch_hdl(adapter_to_dvobj(adapter));
++#endif
++	return	H2C_SUCCESS;
++}
++
++u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf)
++{
++#ifdef CONFIG_TDLS
++	_irqL irqL;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++#ifdef CONFIG_TDLS_CH_SW
++	struct tdls_ch_switch *pchsw_info = &ptdlsinfo->chsw_info;
++#endif
++	struct TDLSoption_param *TDLSoption;
++	struct sta_info *ptdls_sta = NULL;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
++	struct sta_info *ap_sta = rtw_get_stainfo(&padapter->stapriv, get_my_bssid(&(pmlmeinfo->network)));
++	u8 survey_channel, i, min, option;
++	struct tdls_txmgmt txmgmt;
++	u32 setchtime, resp_sleep = 0, wait_time;
++	u8 zaddr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
++	u8 ret;
++	u8 doiqk;
++	u64 tx_ra_bitmap = 0;
++
++	if (!pbuf)
++		return H2C_PARAMETERS_ERROR;
++
++	TDLSoption = (struct TDLSoption_param *)pbuf;
++	option = TDLSoption->option;
++
++	if (!_rtw_memcmp(TDLSoption->addr, zaddr, ETH_ALEN)) {
++		ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), TDLSoption->addr);
++		if (ptdls_sta == NULL)
++			return H2C_REJECTED;
++	} else {
++		if (!(option == TDLS_RS_RCR))
++			return H2C_REJECTED;
++	}
++
++	/* _enter_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); */
++	/* RTW_INFO("[%s] option:%d\n", __FUNCTION__, option); */
++
++	switch (option) {
++	case TDLS_ESTABLISHED: {
++		/* As long as TDLS handshake success, we should set RCR_CBSSID_DATA bit to 0 */
++		/* So we can receive all kinds of data frames. */
++		u8 sta_band = 0;
++
++		/* leave ALL PS when TDLS is established */
++		rtw_pwr_wakeup(padapter);
++
++		rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_LINKED);
++		RTW_INFO("Created Direct Link with "MAC_FMT"\n", MAC_ARG(ptdls_sta->cmn.mac_addr));
++
++		/* Set TDLS sta rate. */
++		/* Update station supportRate */
++		rtw_hal_update_sta_ra_info(padapter, ptdls_sta);
++		tx_ra_bitmap = ptdls_sta->cmn.ra_info.ramask;
++
++		if (pmlmeext->cur_channel > 14) {
++			if (tx_ra_bitmap & 0xffff000)
++				sta_band |= WIRELESS_11_5N ;
++
++			if (tx_ra_bitmap & 0xff0)
++				sta_band |= WIRELESS_11A;
++
++			/* 5G band */
++#ifdef CONFIG_80211AC_VHT
++			if (ptdls_sta->vhtpriv.vht_option)
++				sta_band = WIRELESS_11_5AC;
++#endif
++
++		} else {
++			if (tx_ra_bitmap & 0xffff000)
++				sta_band |= WIRELESS_11_24N;
++
++			if (tx_ra_bitmap & 0xff0)
++				sta_band |= WIRELESS_11G;
++
++			if (tx_ra_bitmap & 0x0f)
++				sta_band |= WIRELESS_11B;
++		}
++		ptdls_sta->wireless_mode = sta_band;
++		rtw_hal_update_sta_wset(padapter, ptdls_sta);
++		/* Sta mode */
++		rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, ptdls_sta, _TRUE);
++
++		set_sta_rate(padapter, ptdls_sta);
++		rtw_sta_media_status_rpt(padapter, ptdls_sta, 1);
++		break;
++	}
++	case TDLS_ISSUE_PTI:
++		ptdls_sta->tdls_sta_state |= TDLS_WAIT_PTR_STATE;
++		issue_tdls_peer_traffic_indication(padapter, ptdls_sta);
++		_set_timer(&ptdls_sta->pti_timer, TDLS_PTI_TIME);
++		break;
++#ifdef CONFIG_TDLS_CH_SW
++	case TDLS_CH_SW_RESP:
++		_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++		txmgmt.status_code = 0;
++		_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
++
++		if (ap_sta)
++			rtw_hal_macid_sleep(padapter, ap_sta->cmn.mac_id);
++		issue_nulldata(padapter, NULL, 1, 3, 3);
++
++		RTW_INFO("[TDLS ] issue tdls channel switch response\n");
++		ret = issue_tdls_ch_switch_rsp(padapter, &txmgmt, _TRUE);
++
++		/* If we receive TDLS_CH_SW_REQ at off channel which it's target is AP's channel */
++		/* then we just switch to AP's channel*/
++		if (padapter->mlmeextpriv.cur_channel == pchsw_info->off_ch_num) {
++			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL);
++			break;
++		}
++
++		if (ret == _SUCCESS)
++			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_OFF_CHNL);
++		else
++			RTW_INFO("[TDLS] issue_tdls_ch_switch_rsp wait ack fail !!!!!!!!!!\n");
++
++		break;
++	case TDLS_CH_SW_PREPARE:
++		pchsw_info->ch_sw_state |= TDLS_CH_SWITCH_PREPARE_STATE;
++
++		/* to collect IQK info of off-chnl */
++		doiqk = _TRUE;
++		rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk);
++		set_channel_bwmode(padapter, pchsw_info->off_ch_num, pchsw_info->ch_offset, (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20);
++		doiqk = _FALSE;
++		rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk);
++
++		/* switch back to base-chnl */
++		set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++
++		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);
++
++		pchsw_info->ch_sw_state &= ~(TDLS_CH_SWITCH_PREPARE_STATE);
++
++		break;
++	case TDLS_CH_SW_START:
++		rtw_tdls_set_ch_sw_oper_control(padapter, _TRUE);
++		break;
++	case TDLS_CH_SW_TO_OFF_CHNL:
++		if (ap_sta)
++			rtw_hal_macid_sleep(padapter, ap_sta->cmn.mac_id);
++		issue_nulldata(padapter, NULL, 1, 3, 3);
++
++		if (padapter->registrypriv.wifi_spec == 0) {
++		if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
++			_set_timer(&ptdls_sta->ch_sw_timer, (u32)(ptdls_sta->ch_switch_timeout) / 1000);
++		}
++
++		if (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_OFF_CHNL, pchsw_info->off_ch_num,
++			pchsw_info->ch_offset, (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20, ptdls_sta->ch_switch_time) == _SUCCESS) {
++			pchsw_info->ch_sw_state &= ~(TDLS_PEER_AT_OFF_STATE);
++			if (pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE) {
++				if (issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta->cmn.mac_addr, 0, 1, 
++					(padapter->registrypriv.wifi_spec == 0) ? 3 : 0) == _FAIL)
++					rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL);
++			}
++		} else {
++			if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
++				_cancel_timer_ex(&ptdls_sta->ch_sw_timer);
++		}
++
++
++		break;
++	case TDLS_CH_SW_END:
++	case TDLS_CH_SW_END_TO_BASE_CHNL:
++		rtw_tdls_set_ch_sw_oper_control(padapter, _FALSE);
++		_cancel_timer_ex(&ptdls_sta->ch_sw_timer);
++		_cancel_timer_ex(&ptdls_sta->stay_on_base_chnl_timer);
++		_cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer);
++#if 0
++		_rtw_memset(pHalData->tdls_ch_sw_iqk_info_base_chnl, 0x00, sizeof(pHalData->tdls_ch_sw_iqk_info_base_chnl));
++		_rtw_memset(pHalData->tdls_ch_sw_iqk_info_off_chnl, 0x00, sizeof(pHalData->tdls_ch_sw_iqk_info_off_chnl));
++#endif
++
++		if (option == TDLS_CH_SW_END_TO_BASE_CHNL)
++			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL);
++
++		break;
++	case TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED:
++	case TDLS_CH_SW_TO_BASE_CHNL:
++		pchsw_info->ch_sw_state &= ~(TDLS_PEER_AT_OFF_STATE | TDLS_WAIT_CH_RSP_STATE);
++
++		if (option == TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED) {
++			if (ptdls_sta != NULL) {
++				/* Send unsolicited channel switch rsp. to peer */
++				_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++				txmgmt.status_code = 0;
++				_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
++				issue_tdls_ch_switch_rsp(padapter, &txmgmt, _FALSE);
++			}
++		}
++
++		if (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_BASE_CHNL, pmlmeext->cur_channel,
++			pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode, ptdls_sta->ch_switch_time) == _SUCCESS) {
++			if (ap_sta)
++				rtw_hal_macid_wakeup(padapter, ap_sta->cmn.mac_id);
++			issue_nulldata(padapter, NULL, 0, 3, 3);
++			/* set ch sw monitor timer for responder */
++			if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
++				_set_timer(&ptdls_sta->ch_sw_monitor_timer, TDLS_CH_SW_MONITOR_TIMEOUT);
++		}
++
++		break;
++#endif
++	case TDLS_RS_RCR:
++		rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_NOLINK);
++		break;
++	case TDLS_TEARDOWN_STA:
++	case TDLS_TEARDOWN_STA_NO_WAIT:
++		_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++		txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;
++		_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
++
++		issue_tdls_teardown(padapter, &txmgmt, (option == TDLS_TEARDOWN_STA) ? _TRUE : _FALSE);
++
++		break;
++	case TDLS_TEARDOWN_STA_LOCALLY:
++	case TDLS_TEARDOWN_STA_LOCALLY_POST:
++#ifdef CONFIG_TDLS_CH_SW
++		if (_rtw_memcmp(TDLSoption->addr, pchsw_info->addr, ETH_ALEN) == _TRUE) {
++			pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE |
++						     TDLS_CH_SWITCH_ON_STATE |
++						     TDLS_PEER_AT_OFF_STATE);
++			rtw_tdls_set_ch_sw_oper_control(padapter, _FALSE);
++			_rtw_memset(pchsw_info->addr, 0x00, ETH_ALEN);
++		}
++#endif
++
++		if (option == TDLS_TEARDOWN_STA_LOCALLY)
++			rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
++
++		rtw_tdls_teardown_post_hdl(padapter, ptdls_sta, _FALSE);
++
++		if (ptdlsinfo->tdls_sctx != NULL)
++			rtw_sctx_done(&(ptdlsinfo->tdls_sctx));
++
++		break;
++	}
++
++	/* _exit_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); */
++
++	return H2C_SUCCESS;
++#else
++	return H2C_REJECTED;
++#endif /* CONFIG_TDLS */
++
++}
++
++u8 run_in_thread_hdl(_adapter *padapter, u8 *pbuf)
++{
++	struct RunInThread_param *p;
++
++
++	if (NULL == pbuf)
++		return H2C_PARAMETERS_ERROR;
++	p = (struct RunInThread_param *)pbuf;
++
++	if (p->func)
++		p->func(p->context);
++
++	return H2C_SUCCESS;
++}
++
++int rtw_sae_preprocess(_adapter *adapter, const u8 *buf, u32 len, u8 tx)
++{
++#ifdef CONFIG_IOCTL_CFG80211
++	const u8 *frame_body = buf + sizeof(struct rtw_ieee80211_hdr_3addr);
++	u16 alg;
++	u16 seq;
++	u16 status;
++	int ret = _FAIL;
++
++	alg = RTW_GET_LE16(frame_body);
++	if (alg != WLAN_AUTH_SAE)
++		goto exit;
++
++	seq = RTW_GET_LE16(frame_body + 2);
++	status = RTW_GET_LE16(frame_body + 4);
++
++	RTW_INFO("RTW_%s:AUTH alg:0x%04x, seq:0x%04x, status:0x%04x, mesg:%s\n",
++		(tx == _TRUE) ? "Tx" : "Rx", alg, seq, status,
++		(seq == 1) ? "Commit" : "Confirm");
++
++	ret = _SUCCESS;
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(adapter)) {
++		rtw_mesh_sae_check_frames(adapter, buf, len, tx, alg, seq, status);
++		goto exit;
++	}
++#endif
++
++	if (tx && (seq == 2) && (status == 0)) {
++		/* quere commit frame until external auth statue update */
++		struct sta_priv *pstapriv = &adapter->stapriv;
++		struct sta_info	*psta = NULL;
++		_irqL irqL;
++
++		psta = rtw_get_stainfo(pstapriv, GetAddr1Ptr(buf));
++		if (psta) {
++			_enter_critical_bh(&psta->lock, &irqL);
++			if (psta->pauth_frame) {
++				rtw_mfree(psta->pauth_frame, psta->auth_len);
++				psta->pauth_frame = NULL;
++				psta->auth_len = 0;
++			}
++
++			psta->pauth_frame =  rtw_zmalloc(len);
++			if (psta->pauth_frame) {
++				_rtw_memcpy(psta->pauth_frame, buf, len);
++				psta->auth_len = len;
++			}
++			_exit_critical_bh(&psta->lock, &irqL);
++
++			ret = 2;
++		}
++	}
++exit:
++	return ret;
++#else
++	return _SUCCESS;
++#endif /* CONFIG_IOCTL_CFG80211 */
++}
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mp.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mp.c
+new file mode 100644
+index 000000000..c3be71fb4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_mp.c
+@@ -0,0 +1,3971 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_MP_C_
++#include <drv_types.h>
++#ifdef PLATFORM_FREEBSD
++	#include <sys/unistd.h>		/* for RFHIGHPID */
++#endif
++
++#include "../hal/phydm/phydm_precomp.h"
++#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A)
++	#include <rtw_bt_mp.h>
++#endif
++
++#ifdef CONFIG_MP_VHT_HW_TX_MODE
++#define CEILING_POS(X) ((X - (int)(X)) > 0 ? (int)(X + 1) : (int)(X))
++#define CEILING_NEG(X) ((X - (int)(X)) < 0 ? (int)(X - 1) : (int)(X))
++#define ceil(X) (((X) > 0) ? CEILING_POS(X) : CEILING_NEG(X))
++
++int rtfloor(float x)
++{
++	int i = x - 2;
++	while
++	(++i <= x - 1)
++		;
++	return i;
++}
++#endif
++
++#ifdef CONFIG_MP_INCLUDED
++u32 read_macreg(_adapter *padapter, u32 addr, u32 sz)
++{
++	u32 val = 0;
++
++	switch (sz) {
++	case 1:
++		val = rtw_read8(padapter, addr);
++		break;
++	case 2:
++		val = rtw_read16(padapter, addr);
++		break;
++	case 4:
++		val = rtw_read32(padapter, addr);
++		break;
++	default:
++		val = 0xffffffff;
++		break;
++	}
++
++	return val;
++
++}
++
++void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz)
++{
++	switch (sz) {
++	case 1:
++		rtw_write8(padapter, addr, (u8)val);
++		break;
++	case 2:
++		rtw_write16(padapter, addr, (u16)val);
++		break;
++	case 4:
++		rtw_write32(padapter, addr, val);
++		break;
++	default:
++		break;
++	}
++
++}
++
++u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask)
++{
++	return rtw_hal_read_bbreg(padapter, addr, bitmask);
++}
++
++void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val)
++{
++	rtw_hal_write_bbreg(padapter, addr, bitmask, val);
++}
++
++u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask)
++{
++	return rtw_hal_read_rfreg(padapter, rfpath, addr, bitmask);
++}
++
++void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val)
++{
++	rtw_hal_write_rfreg(padapter, rfpath, addr, bitmask, val);
++}
++
++u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr)
++{
++	return _read_rfreg(padapter, rfpath, addr, bRFRegOffsetMask);
++}
++
++void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val)
++{
++	_write_rfreg(padapter, rfpath, addr, bRFRegOffsetMask, val);
++}
++
++static void _init_mp_priv_(struct mp_priv *pmp_priv)
++{
++	WLAN_BSSID_EX *pnetwork;
++
++	_rtw_memset(pmp_priv, 0, sizeof(struct mp_priv));
++
++	pmp_priv->mode = MP_OFF;
++
++	pmp_priv->channel = 1;
++	pmp_priv->bandwidth = CHANNEL_WIDTH_20;
++	pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++	pmp_priv->rateidx = RATE_1M;
++	pmp_priv->txpoweridx = 0x2A;
++
++	pmp_priv->antenna_tx = ANTENNA_A;
++	pmp_priv->antenna_rx = ANTENNA_AB;
++
++	pmp_priv->check_mp_pkt = 0;
++
++	pmp_priv->tx_pktcount = 0;
++
++	pmp_priv->rx_bssidpktcount = 0;
++	pmp_priv->rx_pktcount = 0;
++	pmp_priv->rx_crcerrpktcount = 0;
++
++	pmp_priv->network_macaddr[0] = 0x00;
++	pmp_priv->network_macaddr[1] = 0xE0;
++	pmp_priv->network_macaddr[2] = 0x4C;
++	pmp_priv->network_macaddr[3] = 0x87;
++	pmp_priv->network_macaddr[4] = 0x66;
++	pmp_priv->network_macaddr[5] = 0x55;
++
++	pmp_priv->bSetRxBssid = _FALSE;
++	pmp_priv->bRTWSmbCfg = _FALSE;
++	pmp_priv->bloopback = _FALSE;
++
++	pmp_priv->bloadefusemap = _FALSE;
++	pmp_priv->brx_filter_beacon = _FALSE;
++	pmp_priv->mplink_brx = _FALSE;
++
++	pnetwork = &pmp_priv->mp_network.network;
++	_rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN);
++
++	pnetwork->Ssid.SsidLength = 8;
++	_rtw_memcpy(pnetwork->Ssid.Ssid, "mp_871x", pnetwork->Ssid.SsidLength);
++
++	pmp_priv->tx.payload = MP_TX_Payload_default_random;
++#ifdef CONFIG_80211N_HT
++	pmp_priv->tx.attrib.ht_en = 1;
++#endif
++
++	pmp_priv->mpt_ctx.mpt_rate_index = 1;
++
++}
++
++
++static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	struct pkt_attrib *pattrib;
++
++	/* init xmitframe attribute */
++	pattrib = &pmptx->attrib;
++	_rtw_memset(pattrib, 0, sizeof(struct pkt_attrib));
++	_rtw_memset(pmptx->desc, 0, TXDESC_SIZE);
++
++	pattrib->ether_type = 0x8712;
++#if 0
++	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++#endif
++	_rtw_memset(pattrib->dst, 0xFF, ETH_ALEN);
++
++	/*	pattrib->dhcp_pkt = 0;
++	 *	pattrib->pktlen = 0; */
++	pattrib->ack_policy = 0;
++	/*	pattrib->pkt_hdrlen = ETH_HLEN; */
++	pattrib->hdrlen = WLAN_HDR_A3_LEN;
++	pattrib->subtype = WIFI_DATA;
++	pattrib->priority = 0;
++	pattrib->qsel = pattrib->priority;
++	/*	do_queue_select(padapter, pattrib); */
++	pattrib->nr_frags = 1;
++	pattrib->encrypt = 0;
++	pattrib->bswenc = _FALSE;
++	pattrib->qos_en = _FALSE;
++
++	pattrib->pktlen = 1500;
++
++	if (pHalData->rf_type == RF_2T2R)
++		pattrib->raid = RATEID_IDX_BGN_40M_2SS;
++	else
++		pattrib->raid = RATEID_IDX_BGN_40M_1SS;
++
++#ifdef CONFIG_80211AC_VHT
++	if (pHalData->rf_type == RF_1T1R)
++		pattrib->raid = RATEID_IDX_VHT_1SS;
++	else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
++		pattrib->raid = RATEID_IDX_VHT_2SS;
++	else if (pHalData->rf_type == RF_3T3R)
++		pattrib->raid = RATEID_IDX_VHT_3SS;
++	else
++		pattrib->raid = RATEID_IDX_BGN_40M_1SS;
++#endif
++}
++
++s32 init_mp_priv(PADAPTER padapter)
++{
++	struct mp_priv *pmppriv = &padapter->mppriv;
++	PHAL_DATA_TYPE pHalData;
++
++	pHalData = GET_HAL_DATA(padapter);
++
++	_init_mp_priv_(pmppriv);
++	pmppriv->papdater = padapter;
++	if (IS_HARDWARE_TYPE_8822C(padapter))
++		pmppriv->mp_dm = 1;/* default enable dpk tracking */
++	else
++		pmppriv->mp_dm = 0;
++
++	pmppriv->tx.stop = 1;
++	pmppriv->bSetTxPower = 0;		/*for  manually set tx power*/
++	pmppriv->bTxBufCkFail = _FALSE;
++	pmppriv->pktInterval = 0;
++	pmppriv->pktLength = 1000;
++	pmppriv->bprocess_mp_mode = _FALSE;
++
++	mp_init_xmit_attrib(&pmppriv->tx, padapter);
++
++	switch (GET_HAL_RFPATH(padapter)) {
++	case RF_1T1R:
++		pmppriv->antenna_tx = ANTENNA_A;
++		pmppriv->antenna_rx = ANTENNA_A;
++		break;
++	case RF_1T2R:
++	default:
++		pmppriv->antenna_tx = ANTENNA_A;
++		pmppriv->antenna_rx = ANTENNA_AB;
++		break;
++	case RF_2T2R:
++		pmppriv->antenna_tx = ANTENNA_AB;
++		pmppriv->antenna_rx = ANTENNA_AB;
++		break;
++	case RF_2T4R:
++		pmppriv->antenna_tx = ANTENNA_BC;
++		pmppriv->antenna_rx = ANTENNA_ABCD;
++		break;
++	}
++
++	pHalData->AntennaRxPath = pmppriv->antenna_rx;
++	pHalData->antenna_tx_path = pmppriv->antenna_tx;
++
++	return _SUCCESS;
++}
++
++void free_mp_priv(struct mp_priv *pmp_priv)
++{
++	if (pmp_priv->pallocated_mp_xmitframe_buf) {
++		rtw_mfree(pmp_priv->pallocated_mp_xmitframe_buf, 0);
++		pmp_priv->pallocated_mp_xmitframe_buf = NULL;
++	}
++	pmp_priv->pmp_xmtframe_buf = NULL;
++}
++
++#if 0
++static void PHY_IQCalibrate_default(
++		PADAPTER	pAdapter,
++		BOOLEAN	bReCovery
++)
++{
++	RTW_INFO("%s\n", __func__);
++}
++
++static void PHY_LCCalibrate_default(
++		PADAPTER	pAdapter
++)
++{
++	RTW_INFO("%s\n", __func__);
++}
++
++static void PHY_SetRFPathSwitch_default(
++		PADAPTER	pAdapter,
++		BOOLEAN		bMain
++)
++{
++	RTW_INFO("%s\n", __func__);
++}
++#endif
++
++void mpt_InitHWConfig(PADAPTER Adapter)
++{
++	PHAL_DATA_TYPE hal;
++
++	hal = GET_HAL_DATA(Adapter);
++
++	if (IS_HARDWARE_TYPE_8723B(Adapter)) {
++		/* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */
++		/* TODO:  A better solution is configure it according EFUSE during the run-time. */
++
++		phy_set_mac_reg(Adapter, 0x64, BIT20, 0x0);		/* 0x66[4]=0		 */
++		phy_set_mac_reg(Adapter, 0x64, BIT24, 0x0);		/* 0x66[8]=0 */
++		phy_set_mac_reg(Adapter, 0x40, BIT4, 0x0);		/* 0x40[4]=0		 */
++		phy_set_mac_reg(Adapter, 0x40, BIT3, 0x1);		/* 0x40[3]=1		 */
++		phy_set_mac_reg(Adapter, 0x4C, BIT24, 0x1);		/* 0x4C[24:23]=10 */
++		phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0);		/* 0x4C[24:23]=10 */
++		phy_set_bb_reg(Adapter, 0x944, BIT1 | BIT0, 0x3);	/* 0x944[1:0]=11	 */
++		phy_set_bb_reg(Adapter, 0x930, bMaskByte0, 0x77);/* 0x930[7:0]=77	  */
++		phy_set_mac_reg(Adapter, 0x38, BIT11, 0x1);/* 0x38[11]=1 */
++
++		/* TODO: <20130206, Kordan> The default setting is wrong, hard-coded here. */
++		phy_set_mac_reg(Adapter, 0x778, 0x3, 0x3);					/* Turn off hardware PTA control (Asked by Scott) */
++		phy_set_mac_reg(Adapter, 0x64, bMaskDWord, 0x36000000);/* Fix BT S0/S1 */
++		phy_set_mac_reg(Adapter, 0x948, bMaskDWord, 0x0);		/* Fix BT can't Tx */
++
++		/* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou) */
++		phy_set_bb_reg(Adapter, 0xA00, BIT8, 0x0);			/*0xA01[0] = 0*/
++	} else if (IS_HARDWARE_TYPE_8821(Adapter)) {
++		/* <20131121, VincentL> Add for 8821AU DPDT setting and fix switching antenna issue (Asked by Rock)
++		<20131122, VincentL> Enable for all 8821A/8811AU  (Asked by Alex)*/
++		phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0);		/*0x4C[23:22]=01*/
++		phy_set_mac_reg(Adapter, 0x4C, BIT22, 0x1);		/*0x4C[23:22]=01*/
++	} else if (IS_HARDWARE_TYPE_8188ES(Adapter))
++		phy_set_mac_reg(Adapter, 0x4C , BIT23, 0);		/*select DPDT_P and DPDT_N as output pin*/
++#ifdef CONFIG_RTL8814A
++	else if (IS_HARDWARE_TYPE_8814A(Adapter))
++		PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814A, 0x2000);
++#endif
++
++#ifdef CONFIG_RTL8812A
++	else if (IS_HARDWARE_TYPE_8812(Adapter)) {
++		rtw_write32(Adapter, 0x520, rtw_read32(Adapter, 0x520) | 0x8000);
++		rtw_write32(Adapter, 0x524, rtw_read32(Adapter, 0x524) & (~0x800));
++	}
++#endif
++
++
++#ifdef CONFIG_RTL8822B
++	else if (IS_HARDWARE_TYPE_8822B(Adapter)) {
++		u32 tmp_reg = 0;
++
++		PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8822B, 0x2000);
++		/* fixed wifi can't 2.4g tx suggest by Szuyitasi 20160504 */
++		phy_set_bb_reg(Adapter, 0x70, bMaskByte3, 0x0e);
++		RTW_INFO(" 0x73 = 0x%x\n", phy_query_bb_reg(Adapter, 0x70, bMaskByte3));
++		phy_set_bb_reg(Adapter, 0x1704, bMaskDWord, 0x0000ff00);
++		RTW_INFO(" 0x1704 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1704, bMaskDWord));
++		phy_set_bb_reg(Adapter, 0x1700, bMaskDWord, 0xc00f0038);
++		RTW_INFO(" 0x1700 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1700, bMaskDWord));
++	}
++#endif /* CONFIG_RTL8822B */
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(Adapter))
++		PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8821C, 0x2000);
++#endif /* CONFIG_RTL8821C */
++#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
++	else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
++		if (IS_A_CUT(hal->version_id) || IS_B_CUT(hal->version_id)) {
++			RTW_INFO("%s() Active large power detection\n", __func__);
++			phy_active_large_power_detection_8188f(&(GET_HAL_DATA(Adapter)->odmpriv));
++		}
++	}
++#endif
++#if defined(CONFIG_RTL8822C)
++	else if( IS_HARDWARE_TYPE_8822C(Adapter)) {
++		rtw_write16(Adapter, REG_RXFLTMAP1_8822C, 0x2000);
++		/* 0x7D8[31] : time out enable when cca is not assert
++			0x60D[7:0] : time out value (Unit : us)*/
++		rtw_write8(Adapter, 0x7db, 0xc0);
++		RTW_INFO(" 0x7d8 = 0x%x\n", rtw_read8(Adapter, 0x7d8));
++		rtw_write8(Adapter, 0x60d, 0x0c);
++		RTW_INFO(" 0x60d = 0x%x\n", rtw_read8(Adapter, 0x60d));
++		phy_set_bb_reg(Adapter, 0x1c44, BIT10, 0x1);
++		RTW_INFO(" 0x1c44 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1c44, bMaskDWord));
++	}
++#endif
++#if defined(CONFIG_RTL8814B)
++	else if(IS_HARDWARE_TYPE_8814B(Adapter))
++	{
++		PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814B, 0x2000);
++	}
++#endif
++
++}
++
++static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery)
++{
++	halrf_iqk_trigger(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery);
++}
++
++static void PHY_LCCalibrate(PADAPTER padapter)
++{
++	halrf_lck_trigger(&(GET_HAL_DATA(padapter)->odmpriv));
++}
++
++static u8 PHY_QueryRFPathSwitch(PADAPTER padapter)
++{
++	u8 bmain = 0;
++/*
++	if (IS_HARDWARE_TYPE_8723B(padapter)) {
++#ifdef CONFIG_RTL8723B
++		bmain = PHY_QueryRFPathSwitch_8723B(padapter);
++#endif
++	} else if (IS_HARDWARE_TYPE_8188E(padapter)) {
++#ifdef CONFIG_RTL8188E
++		bmain = PHY_QueryRFPathSwitch_8188E(padapter);
++#endif
++	} else if (IS_HARDWARE_TYPE_8814A(padapter)) {
++#ifdef CONFIG_RTL8814A
++		bmain = PHY_QueryRFPathSwitch_8814A(padapter);
++#endif
++	} else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
++#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
++		bmain = PHY_QueryRFPathSwitch_8812A(padapter);
++#endif
++	} else if (IS_HARDWARE_TYPE_8192E(padapter)) {
++#ifdef CONFIG_RTL8192E
++		bmain = PHY_QueryRFPathSwitch_8192E(padapter);
++#endif
++	} else if (IS_HARDWARE_TYPE_8703B(padapter)) {
++#ifdef CONFIG_RTL8703B
++		bmain = PHY_QueryRFPathSwitch_8703B(padapter);
++#endif
++	} else if (IS_HARDWARE_TYPE_8188F(padapter)) {
++#ifdef CONFIG_RTL8188F
++		bmain = PHY_QueryRFPathSwitch_8188F(padapter);
++#endif
++	} else if (IS_HARDWARE_TYPE_8188GTV(padapter)) {
++#ifdef CONFIG_RTL8188GTV
++		bmain = PHY_QueryRFPathSwitch_8188GTV(padapter);
++#endif
++	} else if (IS_HARDWARE_TYPE_8822B(padapter)) {
++#ifdef CONFIG_RTL8822B
++		bmain = PHY_QueryRFPathSwitch_8822B(padapter);
++#endif
++	} else if (IS_HARDWARE_TYPE_8723D(padapter)) {
++#ifdef CONFIG_RTL8723D
++		bmain = PHY_QueryRFPathSwitch_8723D(padapter);
++#endif
++	} else
++*/
++
++	if (IS_HARDWARE_TYPE_8821C(padapter)) {
++#ifdef CONFIG_RTL8821C
++		bmain = phy_query_rf_path_switch_8821c(padapter);
++#endif
++	}
++
++	return bmain;
++}
++
++static void  PHY_SetRFPathSwitch(PADAPTER padapter , BOOLEAN bMain) {
++
++	PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
++	struct dm_struct *phydm = &hal->odmpriv;
++
++	if (IS_HARDWARE_TYPE_8723B(padapter)) {
++#ifdef CONFIG_RTL8723B
++		phy_set_rf_path_switch_8723b(phydm, bMain);
++#endif
++	} else if (IS_HARDWARE_TYPE_8188E(padapter)) {
++#ifdef CONFIG_RTL8188E
++		phy_set_rf_path_switch_8188e(phydm, bMain);
++#endif
++	} else if (IS_HARDWARE_TYPE_8814A(padapter)) {
++#ifdef CONFIG_RTL8814A
++		phy_set_rf_path_switch_8814a(phydm, bMain);
++#endif
++	} else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
++#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
++		phy_set_rf_path_switch_8812a(phydm, bMain);
++#endif
++	} else if (IS_HARDWARE_TYPE_8192E(padapter)) {
++#ifdef CONFIG_RTL8192E
++		phy_set_rf_path_switch_8192e(phydm, bMain);
++#endif
++	} else if (IS_HARDWARE_TYPE_8703B(padapter)) {
++#ifdef CONFIG_RTL8703B
++		phy_set_rf_path_switch_8703b(phydm, bMain);
++#endif
++	} else if (IS_HARDWARE_TYPE_8188F(padapter) || IS_HARDWARE_TYPE_8188GTV(padapter)) {
++#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
++		phy_set_rf_path_switch_8188f(phydm, bMain);
++#endif
++	} else if (IS_HARDWARE_TYPE_8192F(padapter)) {
++#ifdef CONFIG_RTL8192F
++		phy_set_rf_path_switch_8192f(padapter, bMain);
++#endif
++	} else if (IS_HARDWARE_TYPE_8822B(padapter)) {
++#ifdef CONFIG_RTL8822B
++		phy_set_rf_path_switch_8822b(phydm, bMain);
++#endif
++	} else if (IS_HARDWARE_TYPE_8723D(padapter)) {
++#ifdef CONFIG_RTL8723D
++		phy_set_rf_path_switch_8723d(phydm, bMain);
++#endif
++	} else if (IS_HARDWARE_TYPE_8821C(padapter)) {
++#ifdef CONFIG_RTL8821C
++		phy_set_rf_path_switch_8821c(phydm, bMain);
++#endif
++	} else if (IS_HARDWARE_TYPE_8822C(padapter)) {
++#ifdef CONFIG_RTL8822C
++		phy_set_rf_path_switch_8822c(phydm, bMain);
++#endif
++	} else if (IS_HARDWARE_TYPE_8814B(padapter)) {
++#ifdef CONFIG_RTL8814B
++		/* phy_set_rf_path_switch_8814b(phydm, bMain); */
++#endif
++	}
++}
++
++
++static void phy_switch_rf_path_set(PADAPTER padapter , u8 *prf_set_State) {
++#ifdef CONFIG_RTL8821C
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++	struct dm_struct *p_dm = &pHalData->odmpriv;
++
++	if (IS_HARDWARE_TYPE_8821C(padapter)) {
++		config_phydm_set_ant_path(p_dm, *prf_set_State, p_dm->current_ant_num_8821c);
++		/* Do IQK when switching to BTG/WLG, requested by RF Binson */
++		if (*prf_set_State == SWITCH_TO_BTG || *prf_set_State == SWITCH_TO_WLG)
++			PHY_IQCalibrate(padapter, FALSE);
++	}
++#endif
++
++}
++
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++	u8 cur_ant, change_ant;
++
++	if (!pHalData->AntDivCfg)
++		return _FALSE;
++	/*rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL);*/
++	change_ant = (bMain == MAIN_ANT) ? MAIN_ANT : AUX_ANT;
++
++	RTW_INFO("%s: config %s\n", __func__, (bMain == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
++	rtw_antenna_select_cmd(padapter, change_ant, _FALSE);
++
++	return _TRUE;
++}
++#endif
++
++s32
++MPT_InitializeAdapter(
++		PADAPTER			pAdapter,
++		u8				Channel
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++	s32		rtStatus = _SUCCESS;
++	PMPT_CONTEXT	pMptCtx = &pAdapter->mppriv.mpt_ctx;
++	u32		ledsetting;
++
++	pMptCtx->bMptDrvUnload = _FALSE;
++	pMptCtx->bMassProdTest = _FALSE;
++	pMptCtx->bMptIndexEven = _TRUE;	/* default gain index is -6.0db */
++	pMptCtx->h2cReqNum = 0x0;
++	/* init for BT MP */
++#if defined(CONFIG_RTL8723B)
++	pMptCtx->bMPh2c_timeout = _FALSE;
++	pMptCtx->MptH2cRspEvent = _FALSE;
++	pMptCtx->MptBtC2hEvent = _FALSE;
++	_rtw_init_sema(&pMptCtx->MPh2c_Sema, 0);
++	rtw_init_timer(&pMptCtx->MPh2c_timeout_timer, pAdapter, MPh2c_timeout_handle, pAdapter);
++#endif
++
++	mpt_InitHWConfig(pAdapter);
++
++#ifdef CONFIG_RTL8723B
++	rtl8723b_InitAntenna_Selection(pAdapter);
++	if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
++
++		/* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou)*/
++		phy_set_bb_reg(pAdapter, 0xA00, BIT8, 0x0);
++		PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /*default use Main*/
++
++		if (pHalData->PackageType == PACKAGE_DEFAULT)
++			phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
++		else
++			phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6F10E);
++
++	}
++	/*set ant to wifi side in mp mode*/
++	rtw_write16(pAdapter, 0x870, 0x300);
++	rtw_write16(pAdapter, 0x860, 0x110);
++#endif
++
++	pMptCtx->bMptWorkItemInProgress = _FALSE;
++	pMptCtx->CurrMptAct = NULL;
++	pMptCtx->mpt_rf_path = RF_PATH_A;
++	/* ------------------------------------------------------------------------- */
++	/* Don't accept any packets */
++	rtw_write32(pAdapter, REG_RCR, 0);
++
++	/* ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); */
++	/* rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS); */
++
++	/* rtw_write32(pAdapter, REG_LEDCFG0, 0x08080); */
++	ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
++
++
++	PHY_LCCalibrate(pAdapter);
++	PHY_IQCalibrate(pAdapter, _FALSE);
++	/* dm_check_txpowertracking(&pHalData->odmpriv);	*/ /* trigger thermal meter */
++
++	PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /* default use Main */
++
++	pMptCtx->backup0xc50 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
++	pMptCtx->backup0xc58 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
++	pMptCtx->backup0xc30 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
++	pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
++	pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
++#ifdef CONFIG_RTL8188E
++	rtw_write32(pAdapter, REG_MACID_NO_LINK_0, 0x0);
++	rtw_write32(pAdapter, REG_MACID_NO_LINK_1, 0x0);
++#endif
++#ifdef CONFIG_RTL8814A
++	if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
++		pHalData->BackUp_IG_REG_4_Chnl_Section[0] = (u8)phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
++		pHalData->BackUp_IG_REG_4_Chnl_Section[1] = (u8)phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
++		pHalData->BackUp_IG_REG_4_Chnl_Section[2] = (u8)phy_query_bb_reg(pAdapter, rC_IGI_Jaguar2, bMaskByte0);
++		pHalData->BackUp_IG_REG_4_Chnl_Section[3] = (u8)phy_query_bb_reg(pAdapter, rD_IGI_Jaguar2, bMaskByte0);
++	}
++#endif
++	return	rtStatus;
++}
++
++/*-----------------------------------------------------------------------------
++ * Function:	MPT_DeInitAdapter()
++ *
++ * Overview:	Extra DeInitialization for Mass Production Test.
++ *
++ * Input:		PADAPTER	pAdapter
++ *
++ * Output:		NONE
++ *
++ * Return:		NONE
++ *
++ * Revised History:
++ *	When		Who		Remark
++ *	05/08/2007	MHC		Create Version 0.
++ *	05/18/2007	MHC		Add normal driver MPHalt code.
++ *
++ *---------------------------------------------------------------------------*/
++void
++MPT_DeInitAdapter(
++		PADAPTER	pAdapter
++)
++{
++	PMPT_CONTEXT		pMptCtx = &pAdapter->mppriv.mpt_ctx;
++
++	pMptCtx->bMptDrvUnload = _TRUE;
++#if defined(CONFIG_RTL8723B)
++	_rtw_free_sema(&(pMptCtx->MPh2c_Sema));
++	_cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);
++#endif
++#if	defined(CONFIG_RTL8723B)
++	phy_set_bb_reg(pAdapter, 0xA01, BIT0, 1); /* /suggestion  by jerry for MP Rx. */
++#endif
++#if 0 /* for Windows */
++	PlatformFreeWorkItem(&(pMptCtx->MptWorkItem));
++
++	while (pMptCtx->bMptWorkItemInProgress) {
++		if (NdisWaitEvent(&(pMptCtx->MptWorkItemEvent), 50))
++			break;
++	}
++	NdisFreeSpinLock(&(pMptCtx->MptWorkItemSpinLock));
++#endif
++}
++
++static u8 mpt_ProStartTest(PADAPTER padapter)
++{
++	PMPT_CONTEXT pMptCtx = &padapter->mppriv.mpt_ctx;
++
++	pMptCtx->bMassProdTest = _TRUE;
++	pMptCtx->is_start_cont_tx = _FALSE;
++	pMptCtx->bCckContTx = _FALSE;
++	pMptCtx->bOfdmContTx = _FALSE;
++	pMptCtx->bSingleCarrier = _FALSE;
++	pMptCtx->is_carrier_suppression = _FALSE;
++	pMptCtx->is_single_tone = _FALSE;
++	pMptCtx->HWTxmode = PACKETS_TX;
++
++	return _SUCCESS;
++}
++
++/*
++ * General use
++ */
++s32 SetPowerTracking(PADAPTER padapter, u8 enable)
++{
++
++	hal_mpt_SetPowerTracking(padapter, enable);
++	return 0;
++}
++
++void GetPowerTracking(PADAPTER padapter, u8 *enable)
++{
++	hal_mpt_GetPowerTracking(padapter, enable);
++}
++
++void rtw_mp_trigger_iqk(PADAPTER padapter)
++{
++	PHY_IQCalibrate(padapter, _FALSE);
++}
++
++void rtw_mp_trigger_lck(PADAPTER padapter)
++{
++	PHY_LCCalibrate(padapter);
++}
++
++void rtw_mp_trigger_dpk(PADAPTER padapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
++
++	halrf_dpk_trigger(pDM_Odm);
++}
++
++static void init_mp_data(PADAPTER padapter)
++{
++	u8 v8;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
++
++	/*disable BCN*/
++#ifdef CONFIG_PROTSEL_PORT
++	rtw_hal_hw_port_disable(padapter);
++#else
++	v8 = rtw_read8(padapter, REG_BCN_CTRL);
++	v8 &= ~EN_BCN_FUNCTION;
++	rtw_write8(padapter, REG_BCN_CTRL, v8);
++#endif
++
++	pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
++}
++
++
++void MPT_PwrCtlDM(PADAPTER padapter, u32 trk_type)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
++	u32	rf_ability;
++
++	padapter->mppriv.tssitrk_on = trk_type == 3;
++
++	if (trk_type == 0) { /* thermal PwrTrk off*/
++		struct txpwrtrack_cfg c;
++		u8	chnl = 0 ;
++
++		RTW_INFO("in Thermal tracking off\n");
++		rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) & ~HAL_RF_TX_PWR_TRACK;
++		halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);
++		halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_POWER_TRACK_CONTROL, trk_type);
++		halrf_set_pwr_track(pDM_Odm, FALSE);
++		pDM_Odm->rf_calibrate_info.txpowertrack_control = trk_type;
++		if (IS_HARDWARE_TYPE_8822C(padapter))
++			padapter->mppriv.mp_dm = 1; /* default enable dpk tracking */
++		else
++			padapter->mppriv.mp_dm = 0;
++
++		_rtw_memset(&c, 0, sizeof(struct txpwrtrack_cfg));
++		configure_txpower_track(pDM_Odm, &c);
++		odm_clear_txpowertracking_state(pDM_Odm);
++		if (*c.odm_tx_pwr_track_set_pwr) {
++			if (pDM_Odm->support_ic_type == ODM_RTL8188F)
++				(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl);
++			else if (pDM_Odm->support_ic_type == ODM_RTL8723D) {
++				(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);
++				SetTxPower(padapter);
++			} else if (pDM_Odm->support_ic_type == ODM_RTL8192F) {
++				(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl);
++				(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_B, chnl);
++			} else {
++				(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);
++				(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_B, chnl);
++			}
++		}
++		return ;
++	}
++
++	rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) | HAL_RF_TX_PWR_TRACK;
++	halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);
++	halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_POWER_TRACK_CONTROL, trk_type);
++	if (trk_type == 1 || trk_type == 3) /* Thermal PwrTrk ON , TSSI PwrTrk ON */
++		halrf_set_pwr_track(pDM_Odm, TRUE);
++	else
++		halrf_set_pwr_track(pDM_Odm, false);/* TSSI K */
++	pDM_Odm->rf_calibrate_info.txpowertrack_control = trk_type;
++	padapter->mppriv.mp_dm = 1;
++
++}
++
++
++u32 mp_join(PADAPTER padapter, u8 mode)
++{
++	WLAN_BSSID_EX bssid;
++	struct sta_info *psta;
++	u32 length;
++	_irqL irqL;
++	s32 res = _SUCCESS;
++
++	struct mp_priv *pmppriv = &padapter->mppriv;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct wlan_network *tgt_network = &pmlmepriv->cur_network;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
++
++	/* 1. initialize a new WLAN_BSSID_EX */
++	_rtw_memset(&bssid, 0, sizeof(WLAN_BSSID_EX));
++	RTW_INFO("%s ,pmppriv->network_macaddr=%x %x %x %x %x %x\n", __func__,
++		pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],
++		 pmppriv->network_macaddr[5]);
++	_rtw_memcpy(bssid.MacAddress, pmppriv->network_macaddr, ETH_ALEN);
++
++	if (mode == WIFI_FW_ADHOC_STATE) {
++		bssid.Ssid.SsidLength = strlen("mp_pseudo_adhoc");
++		_rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_adhoc", bssid.Ssid.SsidLength);
++		bssid.InfrastructureMode = Ndis802_11IBSS;
++		bssid.IELength = 0;
++		bssid.Configuration.DSConfig = pmppriv->channel;
++
++	} else if (mode == WIFI_FW_STATION_STATE) {
++		bssid.Ssid.SsidLength = strlen("mp_pseudo_STATION");
++		_rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_STATION", bssid.Ssid.SsidLength);
++		bssid.InfrastructureMode = Ndis802_11Infrastructure;
++		bssid.IELength = 0;
++	}
++
++	length = get_WLAN_BSSID_EX_sz(&bssid);
++	if (length % 4)
++		bssid.Length = ((length >> 2) + 1) << 2; /* round up to multiple of 4 bytes. */
++	else
++		bssid.Length = length;
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++	if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
++		goto end_of_mp_start_test;
++
++	/* init mp_start_test status */
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++		rtw_disassoc_cmd(padapter, 500, 0);
++		rtw_indicate_disconnect(padapter, 0, _FALSE);
++		rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
++	}
++	pmppriv->prev_fw_state = get_fwstate(pmlmepriv);
++	/*pmlmepriv->fw_state = WIFI_MP_STATE;*/
++	init_fwstate(pmlmepriv, WIFI_MP_STATE);
++
++	set_fwstate(pmlmepriv, WIFI_UNDER_LINKING);
++
++	/* 3 2. create a new psta for mp driver */
++	/* clear psta in the cur_network, if any */
++	psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
++	if (psta)
++		rtw_free_stainfo(padapter, psta);
++
++	psta = rtw_alloc_stainfo(&padapter->stapriv, bssid.MacAddress);
++	if (psta == NULL) {
++		/*pmlmepriv->fw_state = pmppriv->prev_fw_state;*/
++		init_fwstate(pmlmepriv, pmppriv->prev_fw_state);
++		res = _FAIL;
++		goto end_of_mp_start_test;
++	}
++	if (mode == WIFI_FW_ADHOC_STATE)
++	set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
++	else
++		set_fwstate(pmlmepriv, WIFI_STATION_STATE);
++	/* 3 3. join psudo AdHoc */
++	tgt_network->join_res = 1;
++	tgt_network->aid = psta->cmn.aid = 1;
++
++	_rtw_memcpy(&padapter->registrypriv.dev_network, &bssid, length);
++	rtw_update_registrypriv_dev_network(padapter);
++	_rtw_memcpy(&tgt_network->network, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
++	_rtw_memcpy(pnetwork, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
++
++	rtw_indicate_connect(padapter);
++	_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
++	set_fwstate(pmlmepriv, WIFI_ASOC_STATE);
++
++end_of_mp_start_test:
++
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++	if (1) { /* (res == _SUCCESS) */
++		/* set MSR to WIFI_FW_ADHOC_STATE */
++		if (mode == WIFI_FW_ADHOC_STATE) {
++			/* set msr to WIFI_FW_ADHOC_STATE */
++			pmlmeinfo->state = WIFI_FW_ADHOC_STATE;
++			Set_MSR(padapter, (pmlmeinfo->state & 0x3));
++			rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress);
++			rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);
++			pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
++		} else {
++			Set_MSR(padapter, WIFI_FW_STATION_STATE);
++
++			RTW_INFO("%s , pmppriv->network_macaddr =%x %x %x %x %x %x\n", __func__,
++				pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],
++				 pmppriv->network_macaddr[5]);
++
++			rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmppriv->network_macaddr);
++		}
++	}
++
++	return res;
++}
++/* This function initializes the DUT to the MP test mode */
++s32 mp_start_test(PADAPTER padapter)
++{
++	struct mp_priv *pmppriv = &padapter->mppriv;
++#ifdef CONFIG_PCI_HCI
++	PHAL_DATA_TYPE hal;
++#endif
++	s32 res = _SUCCESS;
++
++	padapter->registrypriv.mp_mode = 1;
++
++	init_mp_data(padapter);
++#ifdef CONFIG_RTL8814A
++	rtl8814_InitHalDm(padapter);
++#endif /* CONFIG_RTL8814A */
++#ifdef CONFIG_RTL8812A
++	rtl8812_InitHalDm(padapter);
++#endif /* CONFIG_RTL8812A */
++#ifdef CONFIG_RTL8723B
++	rtl8723b_InitHalDm(padapter);
++#endif /* CONFIG_RTL8723B */
++#ifdef CONFIG_RTL8703B
++	rtl8703b_InitHalDm(padapter);
++#endif /* CONFIG_RTL8703B */
++#ifdef CONFIG_RTL8192E
++	rtl8192e_InitHalDm(padapter);
++#endif
++#ifdef CONFIG_RTL8188F
++	rtl8188f_InitHalDm(padapter);
++#endif
++#ifdef CONFIG_RTL8188GTV
++	rtl8188gtv_InitHalDm(padapter);
++#endif
++#ifdef CONFIG_RTL8188E
++	rtl8188e_InitHalDm(padapter);
++#endif
++#ifdef CONFIG_RTL8723D
++	rtl8723d_InitHalDm(padapter);
++#endif /* CONFIG_RTL8723D */
++
++#ifdef CONFIG_PCI_HCI
++	hal = GET_HAL_DATA(padapter);
++	hal->pci_backdoor_ctrl = 0;
++	rtw_pci_aspm_config(padapter);
++#endif
++
++
++	/* 3 0. update mp_priv */
++	switch (GET_HAL_RFPATH(padapter)) {
++		case RF_1T1R:
++			pmppriv->antenna_tx = ANTENNA_A;
++			pmppriv->antenna_rx = ANTENNA_A;
++			break;
++		case RF_1T2R:
++		default:
++			pmppriv->antenna_tx = ANTENNA_A;
++			pmppriv->antenna_rx = ANTENNA_AB;
++			break;
++		case RF_2T2R:
++			pmppriv->antenna_tx = ANTENNA_AB;
++			pmppriv->antenna_rx = ANTENNA_AB;
++			break;
++		case RF_2T4R:
++			pmppriv->antenna_tx = ANTENNA_AB;
++			pmppriv->antenna_rx = ANTENNA_ABCD;
++			break;
++	}
++
++	mpt_ProStartTest(padapter);
++
++	mp_join(padapter, WIFI_FW_ADHOC_STATE);
++
++	return res;
++}
++/* ------------------------------------------------------------------------------
++ * This function change the DUT from the MP test mode into normal mode */
++void mp_stop_test(PADAPTER padapter)
++{
++	struct mp_priv *pmppriv = &padapter->mppriv;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct wlan_network *tgt_network = &pmlmepriv->cur_network;
++	struct sta_info *psta;
++#ifdef CONFIG_PCI_HCI
++	struct registry_priv  *registry_par = &padapter->registrypriv;
++	PHAL_DATA_TYPE hal;
++#endif
++
++	_irqL irqL;
++
++	if (pmppriv->mode == MP_ON) {
++		pmppriv->bSetTxPower = 0;
++		_enter_critical_bh(&pmlmepriv->lock, &irqL);
++		if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)
++			goto end_of_mp_stop_test;
++
++		/* 3 1. disconnect psudo AdHoc */
++		rtw_indicate_disconnect(padapter, 0, _FALSE);
++
++		/* 3 2. clear psta used in mp test mode.
++		*	rtw_free_assoc_resources(padapter, _TRUE); */
++		psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
++		if (psta)
++			rtw_free_stainfo(padapter, psta);
++
++		/* 3 3. return to normal state (default:station mode) */
++		/*pmlmepriv->fw_state = pmppriv->prev_fw_state; */ /* WIFI_STATION_STATE;*/
++		init_fwstate(pmlmepriv, pmppriv->prev_fw_state);
++
++		/* flush the cur_network */
++		_rtw_memset(tgt_network, 0, sizeof(struct wlan_network));
++
++		_clr_fwstate_(pmlmepriv, WIFI_MP_STATE);
++
++end_of_mp_stop_test:
++
++		_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++#ifdef CONFIG_PCI_HCI
++		hal = GET_HAL_DATA(padapter);
++		hal->pci_backdoor_ctrl = registry_par->pci_aspm_config;
++		rtw_pci_aspm_config(padapter);
++#endif
++
++#ifdef CONFIG_RTL8812A
++		rtl8812_InitHalDm(padapter);
++#endif
++#ifdef CONFIG_RTL8723B
++		rtl8723b_InitHalDm(padapter);
++#endif
++#ifdef CONFIG_RTL8703B
++		rtl8703b_InitHalDm(padapter);
++#endif
++#ifdef CONFIG_RTL8192E
++		rtl8192e_InitHalDm(padapter);
++#endif
++#ifdef CONFIG_RTL8188F
++		rtl8188f_InitHalDm(padapter);
++#endif
++#ifdef CONFIG_RTL8188GTV
++		rtl8188gtv_InitHalDm(padapter);
++#endif
++#ifdef CONFIG_RTL8723D
++		rtl8723d_InitHalDm(padapter);
++#endif
++	}
++}
++/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
++#if 0
++/* #ifdef CONFIG_USB_HCI */
++static void mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Channel, u8 BandWidthID)
++{
++	u8		eRFPath;
++	u32		rfReg0x26;
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);
++
++
++	if (RateIdx < MPT_RATE_6M) 	/* CCK rate,for 88cu */
++		rfReg0x26 = 0xf400;
++	else if ((RateIdx >= MPT_RATE_6M) && (RateIdx <= MPT_RATE_54M)) {/* OFDM rate,for 88cu */
++		if ((4 == Channel) || (8 == Channel) || (12 == Channel))
++			rfReg0x26 = 0xf000;
++		else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
++			rfReg0x26 = 0xf400;
++		else
++			rfReg0x26 = 0x4f200;
++	} else if ((RateIdx >= MPT_RATE_MCS0) && (RateIdx <= MPT_RATE_MCS15)) {
++		/* MCS 20M ,for 88cu */ /* MCS40M rate,for 88cu */
++
++		if (CHANNEL_WIDTH_20 == BandWidthID) {
++			if ((4 == Channel) || (8 == Channel))
++				rfReg0x26 = 0xf000;
++			else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
++				rfReg0x26 = 0xf400;
++			else
++				rfReg0x26 = 0x4f200;
++		} else {
++			if ((4 == Channel) || (8 == Channel))
++				rfReg0x26 = 0xf000;
++			else if ((5 == Channel) || (7 == Channel))
++				rfReg0x26 = 0xf400;
++			else
++				rfReg0x26 = 0x4f200;
++		}
++	}
++
++	for (eRFPath = 0; eRFPath < hal_spec->rf_reg_path_num; eRFPath++)
++		write_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26);
++}
++#endif
++/*-----------------------------------------------------------------------------
++ * Function:	mpt_SwitchRfSetting
++ *
++ * Overview:	Change RF Setting when we siwthc channel/rate/BW for MP.
++ *
++ * Input:       	PADAPTER				pAdapter
++ *
++ * Output:      NONE
++ *
++ * Return:      NONE
++ *
++ * Revised History:
++ * When			Who		Remark
++ * 01/08/2009	MHC		Suggestion from SD3 Willis for 92S series.
++ * 01/09/2009	MHC		Add CCK modification for 40MHZ. Suggestion from SD3.
++ *
++ *---------------------------------------------------------------------------*/
++#if 0
++static void mpt_SwitchRfSetting(PADAPTER pAdapter)
++{
++	hal_mpt_SwitchRfSetting(pAdapter);
++}
++
++/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
++/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
++static void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
++{
++	hal_mpt_CCKTxPowerAdjust(Adapter, bInCH14);
++}
++#endif
++
++/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
++
++/*
++ * SetChannel
++ * Description
++ *	Use H2C command to change channel,
++ *	not only modify rf register, but also other setting need to be done.
++ */
++void SetChannel(PADAPTER pAdapter)
++{
++	hal_mpt_SetChannel(pAdapter);
++}
++
++/*
++ * Notice
++ *	Switch bandwitdth may change center frequency(channel)
++ */
++void SetBandwidth(PADAPTER pAdapter)
++{
++	hal_mpt_SetBandwidth(pAdapter);
++
++}
++
++void SetAntenna(PADAPTER pAdapter)
++{
++	hal_mpt_SetAntenna(pAdapter);
++}
++
++int SetTxPower(PADAPTER pAdapter)
++{
++
++	hal_mpt_SetTxPower(pAdapter);
++	return _TRUE;
++}
++
++void SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)
++{
++	u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
++
++	TxAGCOffset_B = (ulTxAGCOffset & 0x000000ff);
++	TxAGCOffset_C = ((ulTxAGCOffset & 0x0000ff00) >> 8);
++	TxAGCOffset_D = ((ulTxAGCOffset & 0x00ff0000) >> 16);
++
++	tmpAGC = (TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B);
++	write_bbreg(pAdapter, rFPGA0_TxGainStage,
++		    (bXBTxAGC | bXCTxAGC | bXDTxAGC), tmpAGC);
++}
++
++void SetDataRate(PADAPTER pAdapter)
++{
++	hal_mpt_SetDataRate(pAdapter);
++}
++
++void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain)
++{
++
++	PHY_SetRFPathSwitch(pAdapter, bMain);
++
++}
++
++void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate)
++{
++
++	phy_switch_rf_path_set(pAdapter, pstate);
++
++}
++
++u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter)
++{
++	return PHY_QueryRFPathSwitch(pAdapter);
++}
++
++s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
++{
++	return hal_mpt_SetThermalMeter(pAdapter, target_ther);
++}
++
++#if 0
++static void TriggerRFThermalMeter(PADAPTER pAdapter)
++{
++	hal_mpt_TriggerRFThermalMeter(pAdapter);
++}
++
++static u8 ReadRFThermalMeter(PADAPTER pAdapter)
++{
++	return hal_mpt_ReadRFThermalMeter(pAdapter);
++}
++#endif
++
++void GetThermalMeter(PADAPTER pAdapter, u8 rfpath ,u8 *value)
++{
++	hal_mpt_GetThermalMeter(pAdapter, rfpath, value);
++}
++
++void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
++{
++	PhySetTxPowerLevel(pAdapter);
++	hal_mpt_SetSingleCarrierTx(pAdapter, bStart);
++}
++
++void SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
++{
++	PhySetTxPowerLevel(pAdapter);
++	hal_mpt_SetSingleToneTx(pAdapter, bStart);
++}
++
++void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
++{
++	PhySetTxPowerLevel(pAdapter);
++	hal_mpt_SetCarrierSuppressionTx(pAdapter, bStart);
++}
++
++void SetContinuousTx(PADAPTER pAdapter, u8 bStart)
++{
++	PhySetTxPowerLevel(pAdapter);
++	hal_mpt_SetContinuousTx(pAdapter, bStart);
++}
++
++
++void PhySetTxPowerLevel(PADAPTER pAdapter)
++{
++	struct mp_priv *pmp_priv = &pAdapter->mppriv;
++
++
++	if (pmp_priv->bSetTxPower == 0) /* for NO manually set power index */
++		rtw_hal_set_tx_power_level(pAdapter, pmp_priv->channel);
++}
++
++/* ------------------------------------------------------------------------------ */
++static void dump_mpframe(PADAPTER padapter, struct xmit_frame *pmpframe)
++{
++	rtw_hal_mgnt_xmit(padapter, pmpframe);
++}
++
++static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv)
++{
++	struct xmit_frame	*pmpframe;
++	struct xmit_buf	*pxmitbuf;
++
++	pmpframe = rtw_alloc_xmitframe(pxmitpriv, 0);
++	if (pmpframe == NULL)
++		return NULL;
++
++	pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
++	if (pxmitbuf == NULL) {
++		rtw_free_xmitframe(pxmitpriv, pmpframe);
++		return NULL;
++	}
++
++	pmpframe->frame_tag = MP_FRAMETAG;
++
++	pmpframe->pxmitbuf = pxmitbuf;
++
++	pmpframe->buf_addr = pxmitbuf->pbuf;
++
++	pxmitbuf->priv_data = pmpframe;
++
++	return pmpframe;
++
++}
++
++#ifdef CONFIG_PCI_HCI
++static u8 check_nic_enough_desc(_adapter *padapter, struct pkt_attrib *pattrib)
++{
++	u32 prio;
++	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
++	struct rtw_tx_ring	*ring;
++
++	switch (pattrib->qsel) {
++	case 0:
++	case 3:
++		prio = BE_QUEUE_INX;
++		break;
++	case 1:
++	case 2:
++		prio = BK_QUEUE_INX;
++		break;
++	case 4:
++	case 5:
++		prio = VI_QUEUE_INX;
++		break;
++	case 6:
++	case 7:
++		prio = VO_QUEUE_INX;
++		break;
++	default:
++		prio = BE_QUEUE_INX;
++		break;
++	}
++
++	ring = &pxmitpriv->tx_ring[prio];
++
++	/*
++	 * for now we reserve two free descriptor as a safety boundary
++	 * between the tail and the head
++	 */
++	if ((ring->entries - ring->qlen) >= 2)
++		return _TRUE;
++	else
++		return _FALSE;
++}
++#endif
++
++static thread_return mp_xmit_packet_thread(thread_context context)
++{
++	struct xmit_frame	*pxmitframe;
++	struct mp_tx		*pmptx;
++	struct mp_priv	*pmp_priv;
++	struct xmit_priv	*pxmitpriv;
++	PADAPTER padapter;
++
++	pmp_priv = (struct mp_priv *)context;
++	pmptx = &pmp_priv->tx;
++	padapter = pmp_priv->papdater;
++	pxmitpriv = &(padapter->xmitpriv);
++
++	thread_enter("RTW_MP_THREAD");
++
++	RTW_INFO("%s:pkTx Start\n", __func__);
++	while (1) {
++		pxmitframe = alloc_mp_xmitframe(pxmitpriv);
++#ifdef CONFIG_PCI_HCI
++		if(check_nic_enough_desc(padapter, &pmptx->attrib) == _FALSE) {
++			rtw_usleep_os(1000);
++			continue;
++		}
++#endif
++		if (pxmitframe == NULL) {
++			if (pmptx->stop ||
++			    RTW_CANNOT_RUN(padapter))
++				goto exit;
++			else {
++				rtw_usleep_os(10);
++				continue;
++			}
++		}
++		_rtw_memcpy((u8 *)(pxmitframe->buf_addr + TXDESC_OFFSET), pmptx->buf, pmptx->write_size);
++		_rtw_memcpy(&(pxmitframe->attrib), &(pmptx->attrib), sizeof(struct pkt_attrib));
++
++
++		rtw_usleep_os(padapter->mppriv.pktInterval);
++		dump_mpframe(padapter, pxmitframe);
++
++		pmptx->sended++;
++		pmp_priv->tx_pktcount++;
++
++		if (pmptx->stop ||
++		    RTW_CANNOT_RUN(padapter))
++			goto exit;
++		if ((pmptx->count != 0) &&
++		    (pmptx->count == pmptx->sended))
++			goto exit;
++
++		flush_signals_thread();
++	}
++
++exit:
++	/* RTW_INFO("%s:pkTx Exit\n", __func__); */
++	rtw_mfree(pmptx->pallocated_buf, pmptx->buf_size);
++	pmptx->pallocated_buf = NULL;
++	pmptx->stop = 1;
++
++	thread_exit(NULL);
++	return 0;
++}
++
++void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc)
++{
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++	_rtw_memcpy(ptxdesc, pmp_priv->tx.desc, TXDESC_SIZE);
++}
++
++#if defined(CONFIG_RTL8188E)
++void fill_tx_desc_8188e(PADAPTER padapter)
++{
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++	struct tx_desc *desc   = (struct tx_desc *)&(pmp_priv->tx.desc);
++	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
++	u32	pkt_size = pattrib->last_txcmdsz;
++	s32 bmcast = IS_MCAST(pattrib->ra);
++	/* offset 0 */
++#if !defined(CONFIG_RTL8188E_SDIO) && !defined(CONFIG_PCI_HCI)
++	desc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
++	desc->txdw0 |= cpu_to_le32(pkt_size & 0x0000FFFF); /* packet size */
++	desc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00FF0000); /* 32 bytes for TX Desc */
++	if (bmcast)
++		desc->txdw0 |= cpu_to_le32(BMC); /* broadcast packet */
++
++	desc->txdw1 |= cpu_to_le32((0x01 << 26) & 0xff000000);
++#endif
++
++	desc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x3F); /* CAM_ID(MAC_ID) */
++	desc->txdw1 |= cpu_to_le32((pattrib->qsel << QSEL_SHT) & 0x00001F00); /* Queue Select, TID */
++	desc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000); /* Rate Adaptive ID */
++	/* offset 8 */
++	/* desc->txdw2 |= cpu_to_le32(AGG_BK); */ /* AGG BK */
++
++	desc->txdw3 |= cpu_to_le32((pattrib->seqnum << 16) & 0x0fff0000);
++	desc->txdw4 |= cpu_to_le32(HW_SSN);
++
++	desc->txdw4 |= cpu_to_le32(USERATE);
++	desc->txdw4 |= cpu_to_le32(DISDATAFB);
++
++	if (pmp_priv->preamble) {
++		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
++			desc->txdw4 |= cpu_to_le32(DATA_SHORT); /* CCK Short Preamble */
++	}
++
++	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
++		desc->txdw4 |= cpu_to_le32(DATA_BW);
++
++	/* offset 20 */
++	desc->txdw5 |= cpu_to_le32(pmp_priv->rateidx & 0x0000001F);
++
++	if (pmp_priv->preamble) {
++		if (HwRateToMPTRate(pmp_priv->rateidx) > MPT_RATE_54M)
++			desc->txdw5 |= cpu_to_le32(SGI); /* MCS Short Guard Interval */
++	}
++
++	desc->txdw5 |= cpu_to_le32(RTY_LMT_EN); /* retry limit enable */
++	desc->txdw5 |= cpu_to_le32(0x00180000); /* DATA/RTS Rate Fallback Limit	 */
++
++
++}
++#endif
++
++#if defined(CONFIG_RTL8814A)
++void fill_tx_desc_8814a(PADAPTER padapter)
++{
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++	u8 *pDesc   = (u8 *)&(pmp_priv->tx.desc);
++	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
++
++	u32	pkt_size = pattrib->last_txcmdsz;
++	s32 bmcast = IS_MCAST(pattrib->ra);
++	u8 offset;
++
++	/* SET_TX_DESC_FIRST_SEG_8814A(pDesc, 1); */
++	SET_TX_DESC_LAST_SEG_8814A(pDesc, 1);
++	/* SET_TX_DESC_OWN_(pDesc, 1); */
++
++	SET_TX_DESC_PKT_SIZE_8814A(pDesc, pkt_size);
++
++	offset = TXDESC_SIZE + OFFSET_SZ;
++
++	SET_TX_DESC_OFFSET_8814A(pDesc, offset);
++#if defined(CONFIG_PCI_HCI)
++	SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 0); /* 8814AE pkt_offset is 0 */
++#else
++	SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 1);
++#endif
++
++	if (bmcast)
++		SET_TX_DESC_BMC_8814A(pDesc, 1);
++
++	SET_TX_DESC_MACID_8814A(pDesc, pattrib->mac_id);
++	SET_TX_DESC_RATE_ID_8814A(pDesc, pattrib->raid);
++
++	/* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */
++	SET_TX_DESC_QUEUE_SEL_8814A(pDesc,  pattrib->qsel);
++	/* SET_TX_DESC_QUEUE_SEL_8812(pDesc,  QSLT_MGNT); */
++
++	if (pmp_priv->preamble)
++		SET_TX_DESC_DATA_SHORT_8814A(pDesc, 1);
++
++	if (!pattrib->qos_en) {
++		SET_TX_DESC_HWSEQ_EN_8814A(pDesc, 1); /* Hw set sequence number */
++	} else
++		SET_TX_DESC_SEQ_8814A(pDesc, pattrib->seqnum);
++
++	if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
++		SET_TX_DESC_DATA_BW_8814A(pDesc, pmp_priv->bandwidth);
++	else {
++		RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
++		SET_TX_DESC_DATA_BW_8814A(pDesc, CHANNEL_WIDTH_20);
++	}
++
++	SET_TX_DESC_DISABLE_FB_8814A(pDesc, 1);
++	SET_TX_DESC_USE_RATE_8814A(pDesc, 1);
++	SET_TX_DESC_TX_RATE_8814A(pDesc, pmp_priv->rateidx);
++
++}
++#endif
++
++#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
++void fill_tx_desc_8812a(PADAPTER padapter)
++{
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++	u8 *pDesc   = (u8 *)&(pmp_priv->tx.desc);
++	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
++
++	u32	pkt_size = pattrib->last_txcmdsz;
++	s32 bmcast = IS_MCAST(pattrib->ra);
++	u8 data_rate, pwr_status, offset;
++
++	SET_TX_DESC_FIRST_SEG_8812(pDesc, 1);
++	SET_TX_DESC_LAST_SEG_8812(pDesc, 1);
++	SET_TX_DESC_OWN_8812(pDesc, 1);
++
++	SET_TX_DESC_PKT_SIZE_8812(pDesc, pkt_size);
++
++	offset = TXDESC_SIZE + OFFSET_SZ;
++
++	SET_TX_DESC_OFFSET_8812(pDesc, offset);
++
++#if defined(CONFIG_PCI_HCI)
++	SET_TX_DESC_PKT_OFFSET_8812(pDesc, 0);
++#else
++	SET_TX_DESC_PKT_OFFSET_8812(pDesc, 1);
++#endif
++	if (bmcast)
++		SET_TX_DESC_BMC_8812(pDesc, 1);
++
++	SET_TX_DESC_MACID_8812(pDesc, pattrib->mac_id);
++	SET_TX_DESC_RATE_ID_8812(pDesc, pattrib->raid);
++
++	/* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */
++	SET_TX_DESC_QUEUE_SEL_8812(pDesc,  pattrib->qsel);
++	/* SET_TX_DESC_QUEUE_SEL_8812(pDesc,  QSLT_MGNT); */
++
++	if (!pattrib->qos_en) {
++		SET_TX_DESC_HWSEQ_EN_8812(pDesc, 1); /* Hw set sequence number */
++	} else
++		SET_TX_DESC_SEQ_8812(pDesc, pattrib->seqnum);
++
++	if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
++		SET_TX_DESC_DATA_BW_8812(pDesc, pmp_priv->bandwidth);
++	else {
++		RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
++		SET_TX_DESC_DATA_BW_8812(pDesc, CHANNEL_WIDTH_20);
++	}
++
++	SET_TX_DESC_DISABLE_FB_8812(pDesc, 1);
++	SET_TX_DESC_USE_RATE_8812(pDesc, 1);
++	SET_TX_DESC_TX_RATE_8812(pDesc, pmp_priv->rateidx);
++
++}
++#endif
++#if defined(CONFIG_RTL8192E)
++void fill_tx_desc_8192e(PADAPTER padapter)
++{
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++	u8 *pDesc	= (u8 *)&(pmp_priv->tx.desc);
++	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
++
++	u32 pkt_size = pattrib->last_txcmdsz;
++	s32 bmcast = IS_MCAST(pattrib->ra);
++	u8 data_rate, pwr_status, offset;
++
++
++	SET_TX_DESC_PKT_SIZE_92E(pDesc, pkt_size);
++
++	offset = TXDESC_SIZE + OFFSET_SZ;
++
++	SET_TX_DESC_OFFSET_92E(pDesc, offset);
++#if defined(CONFIG_PCI_HCI) /* 8192EE */
++
++	SET_TX_DESC_PKT_OFFSET_92E(pDesc, 0); /* 8192EE pkt_offset is 0 */
++#else /* 8192EU 8192ES */
++	SET_TX_DESC_PKT_OFFSET_92E(pDesc, 1);
++#endif
++
++	if (bmcast)
++		SET_TX_DESC_BMC_92E(pDesc, 1);
++
++	SET_TX_DESC_MACID_92E(pDesc, pattrib->mac_id);
++	SET_TX_DESC_RATE_ID_92E(pDesc, pattrib->raid);
++
++
++	SET_TX_DESC_QUEUE_SEL_92E(pDesc,  pattrib->qsel);
++	/* SET_TX_DESC_QUEUE_SEL_8812(pDesc,  QSLT_MGNT); */
++
++	if (!pattrib->qos_en) {
++		SET_TX_DESC_EN_HWSEQ_92E(pDesc, 1);/* Hw set sequence number */
++		SET_TX_DESC_HWSEQ_SEL_92E(pDesc, pattrib->hw_ssn_sel);
++	} else
++		SET_TX_DESC_SEQ_92E(pDesc, pattrib->seqnum);
++
++	if ((pmp_priv->bandwidth == CHANNEL_WIDTH_20) || (pmp_priv->bandwidth == CHANNEL_WIDTH_40))
++		SET_TX_DESC_DATA_BW_92E(pDesc, pmp_priv->bandwidth);
++	else {
++		RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
++		SET_TX_DESC_DATA_BW_92E(pDesc, CHANNEL_WIDTH_20);
++	}
++
++	/* SET_TX_DESC_DATA_SC_92E(pDesc, SCMapping_92E(padapter,pattrib)); */
++
++	SET_TX_DESC_DISABLE_FB_92E(pDesc, 1);
++	SET_TX_DESC_USE_RATE_92E(pDesc, 1);
++	SET_TX_DESC_TX_RATE_92E(pDesc, pmp_priv->rateidx);
++
++}
++#endif
++
++#if defined(CONFIG_RTL8723B)
++void fill_tx_desc_8723b(PADAPTER padapter)
++{
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
++	u8 *ptxdesc = pmp_priv->tx.desc;
++
++	SET_TX_DESC_AGG_BREAK_8723B(ptxdesc, 1);
++	SET_TX_DESC_MACID_8723B(ptxdesc, pattrib->mac_id);
++	SET_TX_DESC_QUEUE_SEL_8723B(ptxdesc, pattrib->qsel);
++
++	SET_TX_DESC_RATE_ID_8723B(ptxdesc, pattrib->raid);
++	SET_TX_DESC_SEQ_8723B(ptxdesc, pattrib->seqnum);
++	SET_TX_DESC_HWSEQ_EN_8723B(ptxdesc, 1);
++	SET_TX_DESC_USE_RATE_8723B(ptxdesc, 1);
++	SET_TX_DESC_DISABLE_FB_8723B(ptxdesc, 1);
++
++	if (pmp_priv->preamble) {
++		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
++			SET_TX_DESC_DATA_SHORT_8723B(ptxdesc, 1);
++	}
++
++	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
++		SET_TX_DESC_DATA_BW_8723B(ptxdesc, 1);
++
++	SET_TX_DESC_TX_RATE_8723B(ptxdesc, pmp_priv->rateidx);
++
++	SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(ptxdesc, 0x1F);
++	SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(ptxdesc, 0xF);
++}
++#endif
++
++#if defined(CONFIG_RTL8703B)
++void fill_tx_desc_8703b(PADAPTER padapter)
++{
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
++	u8 *ptxdesc = pmp_priv->tx.desc;
++
++	SET_TX_DESC_AGG_BREAK_8703B(ptxdesc, 1);
++	SET_TX_DESC_MACID_8703B(ptxdesc, pattrib->mac_id);
++	SET_TX_DESC_QUEUE_SEL_8703B(ptxdesc, pattrib->qsel);
++
++	SET_TX_DESC_RATE_ID_8703B(ptxdesc, pattrib->raid);
++	SET_TX_DESC_SEQ_8703B(ptxdesc, pattrib->seqnum);
++	SET_TX_DESC_HWSEQ_EN_8703B(ptxdesc, 1);
++	SET_TX_DESC_USE_RATE_8703B(ptxdesc, 1);
++	SET_TX_DESC_DISABLE_FB_8703B(ptxdesc, 1);
++
++	if (pmp_priv->preamble) {
++		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
++			SET_TX_DESC_DATA_SHORT_8703B(ptxdesc, 1);
++	}
++
++	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
++		SET_TX_DESC_DATA_BW_8703B(ptxdesc, 1);
++
++	SET_TX_DESC_TX_RATE_8703B(ptxdesc, pmp_priv->rateidx);
++
++	SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(ptxdesc, 0x1F);
++	SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(ptxdesc, 0xF);
++}
++#endif
++
++#if defined(CONFIG_RTL8188F)
++void fill_tx_desc_8188f(PADAPTER padapter)
++{
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
++	u8 *ptxdesc = pmp_priv->tx.desc;
++
++	SET_TX_DESC_AGG_BREAK_8188F(ptxdesc, 1);
++	SET_TX_DESC_MACID_8188F(ptxdesc, pattrib->mac_id);
++	SET_TX_DESC_QUEUE_SEL_8188F(ptxdesc, pattrib->qsel);
++
++	SET_TX_DESC_RATE_ID_8188F(ptxdesc, pattrib->raid);
++	SET_TX_DESC_SEQ_8188F(ptxdesc, pattrib->seqnum);
++	SET_TX_DESC_HWSEQ_EN_8188F(ptxdesc, 1);
++	SET_TX_DESC_USE_RATE_8188F(ptxdesc, 1);
++	SET_TX_DESC_DISABLE_FB_8188F(ptxdesc, 1);
++
++	if (pmp_priv->preamble)
++		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
++			SET_TX_DESC_DATA_SHORT_8188F(ptxdesc, 1);
++
++	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
++		SET_TX_DESC_DATA_BW_8188F(ptxdesc, 1);
++
++	SET_TX_DESC_TX_RATE_8188F(ptxdesc, pmp_priv->rateidx);
++
++	SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(ptxdesc, 0x1F);
++	SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(ptxdesc, 0xF);
++}
++#endif
++
++#if defined(CONFIG_RTL8188GTV)
++void fill_tx_desc_8188gtv(PADAPTER padapter)
++{
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
++	u8 *ptxdesc = pmp_priv->tx.desc;
++
++	SET_TX_DESC_AGG_BREAK_8188GTV(ptxdesc, 1);
++	SET_TX_DESC_MACID_8188GTV(ptxdesc, pattrib->mac_id);
++	SET_TX_DESC_QUEUE_SEL_8188GTV(ptxdesc, pattrib->qsel);
++
++	SET_TX_DESC_RATE_ID_8188GTV(ptxdesc, pattrib->raid);
++	SET_TX_DESC_SEQ_8188GTV(ptxdesc, pattrib->seqnum);
++	SET_TX_DESC_HWSEQ_EN_8188GTV(ptxdesc, 1);
++	SET_TX_DESC_USE_RATE_8188GTV(ptxdesc, 1);
++	SET_TX_DESC_DISABLE_FB_8188GTV(ptxdesc, 1);
++
++	if (pmp_priv->preamble)
++		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
++			SET_TX_DESC_DATA_SHORT_8188GTV(ptxdesc, 1);
++
++	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
++		SET_TX_DESC_DATA_BW_8188GTV(ptxdesc, 1);
++
++	SET_TX_DESC_TX_RATE_8188GTV(ptxdesc, pmp_priv->rateidx);
++
++	SET_TX_DESC_DATA_RATE_FB_LIMIT_8188GTV(ptxdesc, 0x1F);
++	SET_TX_DESC_RTS_RATE_FB_LIMIT_8188GTV(ptxdesc, 0xF);
++}
++#endif
++
++#if defined(CONFIG_RTL8723D)
++void fill_tx_desc_8723d(PADAPTER padapter)
++{
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
++	u8 *ptxdesc = pmp_priv->tx.desc;
++
++	SET_TX_DESC_BK_8723D(ptxdesc, 1);
++	SET_TX_DESC_MACID_8723D(ptxdesc, pattrib->mac_id);
++	SET_TX_DESC_QUEUE_SEL_8723D(ptxdesc, pattrib->qsel);
++
++	SET_TX_DESC_RATE_ID_8723D(ptxdesc, pattrib->raid);
++	SET_TX_DESC_SEQ_8723D(ptxdesc, pattrib->seqnum);
++	SET_TX_DESC_HWSEQ_EN_8723D(ptxdesc, 1);
++	SET_TX_DESC_USE_RATE_8723D(ptxdesc, 1);
++	SET_TX_DESC_DISABLE_FB_8723D(ptxdesc, 1);
++
++	if (pmp_priv->preamble) {
++		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
++			SET_TX_DESC_DATA_SHORT_8723D(ptxdesc, 1);
++	}
++
++	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
++		SET_TX_DESC_DATA_BW_8723D(ptxdesc, 1);
++
++	SET_TX_DESC_TX_RATE_8723D(ptxdesc, pmp_priv->rateidx);
++
++	SET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(ptxdesc, 0x1F);
++	SET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(ptxdesc, 0xF);
++}
++#endif
++
++#if defined(CONFIG_RTL8710B)
++void fill_tx_desc_8710b(PADAPTER padapter)
++{
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
++	u8 *ptxdesc = pmp_priv->tx.desc;
++
++	SET_TX_DESC_BK_8710B(ptxdesc, 1);
++	SET_TX_DESC_MACID_8710B(ptxdesc, pattrib->mac_id);
++	SET_TX_DESC_QUEUE_SEL_8710B(ptxdesc, pattrib->qsel);
++
++	SET_TX_DESC_RATE_ID_8710B(ptxdesc, pattrib->raid);
++	SET_TX_DESC_SEQ_8710B(ptxdesc, pattrib->seqnum);
++	SET_TX_DESC_HWSEQ_EN_8710B(ptxdesc, 1);
++	SET_TX_DESC_USE_RATE_8710B(ptxdesc, 1);
++	SET_TX_DESC_DISABLE_FB_8710B(ptxdesc, 1);
++
++	if (pmp_priv->preamble) {
++		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
++			SET_TX_DESC_DATA_SHORT_8710B(ptxdesc, 1);
++	}
++
++	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
++		SET_TX_DESC_DATA_BW_8710B(ptxdesc, 1);
++
++	SET_TX_DESC_TX_RATE_8710B(ptxdesc, pmp_priv->rateidx);
++
++	SET_TX_DESC_DATA_RATE_FB_LIMIT_8710B(ptxdesc, 0x1F);
++	SET_TX_DESC_RTS_RATE_FB_LIMIT_8710B(ptxdesc, 0xF);
++}
++#endif
++
++#if defined(CONFIG_RTL8192F)
++void fill_tx_desc_8192f(PADAPTER padapter)
++{
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
++	u8 *ptxdesc = pmp_priv->tx.desc;
++
++	SET_TX_DESC_BK_8192F(ptxdesc, 1);
++	SET_TX_DESC_MACID_8192F(ptxdesc, pattrib->mac_id);
++	SET_TX_DESC_QUEUE_SEL_8192F(ptxdesc, pattrib->qsel);
++
++	SET_TX_DESC_RATE_ID_8192F(ptxdesc, pattrib->raid);
++	SET_TX_DESC_SEQ_8192F(ptxdesc, pattrib->seqnum);
++	SET_TX_DESC_HWSEQ_EN_8192F(ptxdesc, 1);
++	SET_TX_DESC_USE_RATE_8192F(ptxdesc, 1);
++	SET_TX_DESC_DISABLE_FB_8192F(ptxdesc, 1);
++
++	if (pmp_priv->preamble) {
++		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
++			SET_TX_DESC_DATA_SHORT_8192F(ptxdesc, 1);
++	}
++
++	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
++		SET_TX_DESC_DATA_BW_8192F(ptxdesc, 1);
++
++	SET_TX_DESC_TX_RATE_8192F(ptxdesc, pmp_priv->rateidx);
++
++	SET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(ptxdesc, 0x1F);
++	SET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(ptxdesc, 0xF);
++}
++
++#endif
++static void Rtw_MPSetMacTxEDCA(PADAPTER padapter)
++{
++
++	rtw_write32(padapter, 0x508 , 0x00a422); /* Disable EDCA BE Txop for MP pkt tx adjust Packet interval */
++	/* RTW_INFO("%s:write 0x508~~~~~~ 0x%x\n", __func__,rtw_read32(padapter, 0x508)); */
++	phy_set_mac_reg(padapter, 0x458 , bMaskDWord , 0x0);
++	/*RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" ,__func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));*/
++	phy_set_mac_reg(padapter, 0x460 , bMaskLWord , 0x0); /* fast EDCA queue packet interval & time out value*/
++	/*phy_set_mac_reg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C);*/
++	/*phy_set_mac_reg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C);*/
++	/*phy_set_mac_reg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C);*/
++	RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" , __func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));
++
++}
++
++void SetPacketTx(PADAPTER padapter)
++{
++	u8 *ptr, *pkt_start, *pkt_end;
++	u32 pkt_size = 0, i = 0, idx = 0, tmp_idx = 0;
++	struct rtw_ieee80211_hdr *hdr;
++	u8 payload;
++	s32 bmcast;
++	struct pkt_attrib *pattrib;
++	struct mp_priv *pmp_priv;
++
++	pmp_priv = &padapter->mppriv;
++
++	if (pmp_priv->tx.stop)
++		return;
++	pmp_priv->tx.sended = 0;
++	pmp_priv->tx.stop = 0;
++	pmp_priv->tx_pktcount = 0;
++
++	/* 3 1. update_attrib() */
++	pattrib = &pmp_priv->tx.attrib;
++	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++	_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
++	bmcast = IS_MCAST(pattrib->ra);
++	if (bmcast)
++		pattrib->psta = rtw_get_bcmc_stainfo(padapter);
++	else
++		pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
++
++	if (pattrib->psta == NULL) {
++		RTW_INFO("%s:psta = NULL !!\n", __func__);
++		return;
++	}
++
++	pattrib->mac_id = pattrib->psta->cmn.mac_id;
++	pattrib->mbssid = 0;
++
++	pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen;
++
++	/* 3 2. allocate xmit buffer */
++	pkt_size = pattrib->last_txcmdsz;
++
++	if (pmp_priv->tx.pallocated_buf)
++		rtw_mfree(pmp_priv->tx.pallocated_buf, pmp_priv->tx.buf_size);
++	pmp_priv->tx.write_size = pkt_size;
++	pmp_priv->tx.buf_size = pkt_size + XMITBUF_ALIGN_SZ;
++	pmp_priv->tx.pallocated_buf = rtw_zmalloc(pmp_priv->tx.buf_size);
++	if (pmp_priv->tx.pallocated_buf == NULL) {
++		RTW_INFO("%s: malloc(%d) fail!!\n", __func__, pmp_priv->tx.buf_size);
++		return;
++	}
++	pmp_priv->tx.buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pmp_priv->tx.pallocated_buf), XMITBUF_ALIGN_SZ);
++	ptr = pmp_priv->tx.buf;
++
++	_rtw_memset(pmp_priv->tx.desc, 0, TXDESC_SIZE);
++	pkt_start = ptr;
++	pkt_end = pkt_start + pkt_size;
++
++	/* 3 3. init TX descriptor */
++#if defined(CONFIG_RTL8188E)
++	if (IS_HARDWARE_TYPE_8188E(padapter))
++		fill_tx_desc_8188e(padapter);
++#endif
++
++#if defined(CONFIG_RTL8814A)
++	if (IS_HARDWARE_TYPE_8814A(padapter))
++		fill_tx_desc_8814a(padapter);
++#endif /* defined(CONFIG_RTL8814A) */
++
++#if defined(CONFIG_RTL8822B)
++	if (IS_HARDWARE_TYPE_8822B(padapter))
++		rtl8822b_prepare_mp_txdesc(padapter, pmp_priv);
++#endif /* CONFIG_RTL8822B */
++
++#if defined(CONFIG_RTL8822C)
++	if (IS_HARDWARE_TYPE_8822C(padapter))
++		rtl8822c_prepare_mp_txdesc(padapter, pmp_priv);
++#endif /* CONFIG_RTL8822C */
++
++#if defined(CONFIG_RTL8821C)
++	if (IS_HARDWARE_TYPE_8821C(padapter))
++		rtl8821c_prepare_mp_txdesc(padapter, pmp_priv);
++#endif /* CONFIG_RTL8821C */
++
++#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
++	if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter))
++		fill_tx_desc_8812a(padapter);
++#endif
++
++#if defined(CONFIG_RTL8192E)
++	if (IS_HARDWARE_TYPE_8192E(padapter))
++		fill_tx_desc_8192e(padapter);
++#endif
++#if defined(CONFIG_RTL8723B)
++	if (IS_HARDWARE_TYPE_8723B(padapter))
++		fill_tx_desc_8723b(padapter);
++#endif
++#if defined(CONFIG_RTL8703B)
++	if (IS_HARDWARE_TYPE_8703B(padapter))
++		fill_tx_desc_8703b(padapter);
++#endif
++
++#if defined(CONFIG_RTL8188F)
++	if (IS_HARDWARE_TYPE_8188F(padapter))
++		fill_tx_desc_8188f(padapter);
++#endif
++
++#if defined(CONFIG_RTL8188GTV)
++	if (IS_HARDWARE_TYPE_8188GTV(padapter))
++		fill_tx_desc_8188gtv(padapter);
++#endif
++
++#if defined(CONFIG_RTL8723D)
++	if (IS_HARDWARE_TYPE_8723D(padapter))
++		fill_tx_desc_8723d(padapter);
++#endif
++#if defined(CONFIG_RTL8192F)
++		if (IS_HARDWARE_TYPE_8192F(padapter))
++			fill_tx_desc_8192f(padapter);
++#endif
++
++#if defined(CONFIG_RTL8710B)
++	if (IS_HARDWARE_TYPE_8710B(padapter))
++		fill_tx_desc_8710b(padapter);
++#endif
++
++#if defined(CONFIG_RTL8814B)
++	if (IS_HARDWARE_TYPE_8814B(padapter))
++		rtl8814b_prepare_mp_txdesc(padapter, pmp_priv);
++#endif /* CONFIG_RTL8814B */
++
++	/* 3 4. make wlan header, make_wlanhdr() */
++	hdr = (struct rtw_ieee80211_hdr *)pkt_start;
++	set_frame_sub_type(&hdr->frame_ctl, pattrib->subtype);
++
++	_rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); /* DA */
++	_rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); /* SA */
++	_rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); /* RA, BSSID */
++
++	/* 3 5. make payload */
++	ptr = pkt_start + pattrib->hdrlen;
++
++	if (pmp_priv->mplink_btx == _TRUE) {
++		_rtw_memcpy(ptr, pmp_priv->mplink_buf, pkt_end - ptr);
++	} else {
++		switch (pmp_priv->tx.payload) {
++		case MP_TX_Payload_00:
++			RTW_INFO("MP packet tx 0x00 payload!\n");
++			payload = 0x00;
++			_rtw_memset(ptr, 0x00, pkt_end - ptr);
++			break;
++		case MP_TX_Payload_5a:
++			RTW_INFO("MP packet tx 0x5a payload!\n");
++			payload = 0x5a;
++			_rtw_memset(ptr, 0x5a, pkt_end - ptr);
++			break;
++		case MP_TX_Payload_a5:
++			RTW_INFO("MP packet tx 0xa5 payload!\n");
++			payload = 0xa5;
++			_rtw_memset(ptr, 0xa5, pkt_end - ptr);
++			break;
++		case MP_TX_Payload_ff:
++			RTW_INFO("MP packet tx 0xff payload!\n");
++			payload = 0xff;
++			_rtw_memset(ptr, 0xff, pkt_end - ptr);
++			break;
++		case MP_TX_Payload_prbs9:
++			RTW_INFO("MP packet tx PRBS9 payload!\n");
++			while (idx <= pkt_end - ptr) {
++				int start = 0x02;
++				int a = start;
++
++				for (i = 0;; i++) {
++						int newbit = (((a >> 8) ^ (a >> 4)) & 1);
++						a = ((a << 1) | newbit) & 0x1ff;
++						RTW_DBG("%x ", a);
++						ptr[idx + i] = a;
++
++						if (a == start) {
++							RTW_INFO("payload repetition period is %d , end %d\n", i , idx);
++							tmp_idx += i;
++							break;
++						}
++						if (idx + i >= (pkt_end - ptr)) {
++							tmp_idx += (idx + i);
++							RTW_INFO(" repetition period payload end curr ptr %d\n", idx + i);
++							break;
++						}
++				}
++				idx = tmp_idx;
++			}
++			break;
++		case MP_TX_Payload_default_random:
++			RTW_INFO("MP packet tx default random payload!\n");
++			for (i = 0; i < pkt_end - ptr; i++)
++				ptr[i] = rtw_random32() % 0xFF;
++			break;
++		default:
++			RTW_INFO("Config payload type default use 0x%x\n!", pmp_priv->tx.payload);
++			_rtw_memset(ptr, pmp_priv->tx.payload, pkt_end - ptr);
++			break;
++		}
++	}
++	/* 3 6. start thread */
++#ifdef PLATFORM_LINUX
++	pmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD");
++	if (IS_ERR(pmp_priv->tx.PktTxThread)) {
++		RTW_ERR("Create PktTx Thread Fail !!!!!\n");
++		pmp_priv->tx.PktTxThread = NULL;
++	}
++#endif
++#ifdef PLATFORM_FREEBSD
++	{
++		struct proc *p;
++		struct thread *td;
++		pmp_priv->tx.PktTxThread = kproc_kthread_add(mp_xmit_packet_thread, pmp_priv,
++			&p, &td, RFHIGHPID, 0, "MPXmitThread", "MPXmitThread");
++
++		if (pmp_priv->tx.PktTxThread < 0)
++			RTW_INFO("Create PktTx Thread Fail !!!!!\n");
++	}
++#endif
++
++	Rtw_MPSetMacTxEDCA(padapter);
++	return;
++}
++
++void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
++	struct mp_priv *pmppriv = &pAdapter->mppriv;
++
++
++	if (bStartRx) {
++#ifdef CONFIG_RTL8723B
++		phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x3); /* Power on adc  (in RX_WAIT_CCA state) */
++		write_bbreg(pAdapter, 0xa01, BIT0, bDisable);/* improve Rx performance by jerry	 */
++#endif
++		pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AMF | RCR_HTC_LOC_CTRL;
++		pHalData->ReceiveConfig |= RCR_ACRC32;
++		pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
++
++		if (pmppriv->bSetRxBssid == _TRUE) {
++			RTW_INFO("%s: pmppriv->network_macaddr=" MAC_FMT "\n", __func__,
++				 MAC_ARG(pmppriv->network_macaddr));
++			pHalData->ReceiveConfig = 0;
++			pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN |RCR_APM | RCR_AM | RCR_AB |RCR_AMF;
++			pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF;
++
++#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
++			write_bbreg(pAdapter, 0x550, BIT3, bEnable);
++#endif
++			rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFEF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
++			pmppriv->brx_filter_beacon = _TRUE;
++
++		} else {
++			pHalData->ReceiveConfig |= RCR_ADF;
++			/* Accept all data frames */
++			rtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF);
++		}
++
++		if (bAB)
++			pHalData->ReceiveConfig |= RCR_AB;
++	} else {
++#ifdef CONFIG_RTL8723B
++		phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x00); /* Power off adc  (in RX_WAIT_CCA state)*/
++		write_bbreg(pAdapter, 0xa01, BIT0, bEnable);/* improve Rx performance by jerry	 */
++#endif
++		pHalData->ReceiveConfig = 0;
++		rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFFF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
++	}
++
++	rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig);
++}
++
++void ResetPhyRxPktCount(PADAPTER pAdapter)
++{
++	u32 i, phyrx_set = 0;
++
++	for (i = 0; i <= 0xF; i++) {
++		phyrx_set = 0;
++		phyrx_set |= _RXERR_RPT_SEL(i);	/* select */
++		phyrx_set |= RXERR_RPT_RST;	/* set counter to zero */
++		rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
++	}
++}
++
++static u32 GetPhyRxPktCounts(PADAPTER pAdapter, u32 selbit)
++{
++	/* selection */
++	u32 phyrx_set = 0, count = 0;
++
++	phyrx_set = _RXERR_RPT_SEL(selbit & 0xF);
++	rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
++
++	/* Read packet count */
++	count = rtw_read32(pAdapter, REG_RXERR_RPT) & RXERR_COUNTER_MASK;
++
++	return count;
++}
++
++u32 GetPhyRxPktReceived(PADAPTER pAdapter)
++{
++	u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
++
++	OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_OK);
++	CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_OK);
++	HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_OK);
++
++	return OFDM_cnt + CCK_cnt + HT_cnt;
++}
++
++u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter)
++{
++	u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
++
++	OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_FAIL);
++	CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_FAIL);
++	HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_FAIL);
++
++	return OFDM_cnt + CCK_cnt + HT_cnt;
++}
++
++struct psd_init_regs {
++	/* 3 wire */
++	int reg_88c;
++	int reg_c00;
++	int reg_e00;
++	int reg_1800;
++	int reg_1a00;
++	/* cck */
++	int reg_800;
++	int reg_808;
++};
++
++static int rtw_mp_psd_init(PADAPTER padapter, struct psd_init_regs *regs)
++{
++	HAL_DATA_TYPE	*phal_data	= GET_HAL_DATA(padapter);
++
++	switch (phal_data->rf_type) {
++	/* 1R */
++	case RF_1T1R:
++		if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
++			/* 11AC 1R PSD Setting 3wire & cck off */
++			regs->reg_c00 = rtw_read32(padapter, 0xC00);
++			phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
++			regs->reg_808 = rtw_read32(padapter, 0x808);
++			phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
++		} else {
++			/* 11N 3-wire off 1 */
++			regs->reg_88c = rtw_read32(padapter, 0x88C);
++			phy_set_bb_reg(padapter, 0x88C, 0x300000, 0x3);
++			/* 11N CCK off */
++			regs->reg_800 = rtw_read32(padapter, 0x800);
++			phy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0);
++		}
++	break;
++
++	/* 2R */
++	case RF_1T2R:
++	case RF_2T2R:
++		if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
++			/* 11AC 2R PSD Setting 3wire & cck off */
++			regs->reg_c00 = rtw_read32(padapter, 0xC00);
++			regs->reg_e00 = rtw_read32(padapter, 0xE00);
++			phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
++			phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
++			regs->reg_808 = rtw_read32(padapter, 0x808);
++			phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
++		} else {
++			/* 11N 3-wire off 2 */
++			regs->reg_88c = rtw_read32(padapter, 0x88C);
++			phy_set_bb_reg(padapter, 0x88C, 0xF00000, 0xF);
++			/* 11N CCK off */
++			regs->reg_800 = rtw_read32(padapter, 0x800);
++			phy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0);
++		}
++	break;
++
++	/* 3R */
++	case RF_2T3R:
++	case RF_3T3R:
++		if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
++			/* 11AC 3R PSD Setting 3wire & cck off */
++			regs->reg_c00 = rtw_read32(padapter, 0xC00);
++			regs->reg_e00 = rtw_read32(padapter, 0xE00);
++			regs->reg_1800 = rtw_read32(padapter, 0x1800);
++			phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
++			phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
++			phy_set_bb_reg(padapter, 0x1800, 0x3, 0x00);
++			regs->reg_808 = rtw_read32(padapter, 0x808);
++			phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
++		} else {
++			RTW_ERR("%s: 11n don't support 3R\n", __func__);
++			return -1;
++		}
++		break;
++
++	/* 4R */
++	case RF_2T4R:
++	case RF_3T4R:
++	case RF_4T4R:
++		if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
++			/* 11AC 4R PSD Setting 3wire & cck off */
++			regs->reg_c00 = rtw_read32(padapter, 0xC00);
++			regs->reg_e00 = rtw_read32(padapter, 0xE00);
++			regs->reg_1800 = rtw_read32(padapter, 0x1800);
++			regs->reg_1a00 = rtw_read32(padapter, 0x1A00);
++			phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
++			phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
++			phy_set_bb_reg(padapter, 0x1800, 0x3, 0x00);
++			phy_set_bb_reg(padapter, 0x1A00, 0x3, 0x00);
++			regs->reg_808 = rtw_read32(padapter, 0x808);
++			phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
++		} else {
++			RTW_ERR("%s: 11n don't support 4R\n", __func__);
++			return -1;
++		}
++		break;
++
++	default:
++		RTW_ERR("%s: unknown %d rf type\n", __func__, phal_data->rf_type);
++		return -1;
++	}
++
++	/* Set PSD points, 0=128, 1=256, 2=512, 3=1024 */
++	if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC))
++		phy_set_bb_reg(padapter, 0x910, 0xC000, 3);
++	else
++		phy_set_bb_reg(padapter, 0x808, 0xC000, 3);
++
++	RTW_INFO("%s: set %d rf type done\n", __func__, phal_data->rf_type);
++	return 0;
++}
++
++static int rtw_mp_psd_close(PADAPTER padapter, struct psd_init_regs *regs)
++{
++	HAL_DATA_TYPE	*phal_data	= GET_HAL_DATA(padapter);
++
++
++	if (!hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
++		/* 11n 3wire restore */
++		rtw_write32(padapter, 0x88C, regs->reg_88c);
++		/* 11n cck restore */
++		rtw_write32(padapter, 0x800, regs->reg_800);
++		RTW_INFO("%s: restore %d rf type\n", __func__, phal_data->rf_type);
++		return 0;
++	}
++
++	/* 11ac 3wire restore */
++	switch (phal_data->rf_type) {
++	case RF_1T1R:
++		rtw_write32(padapter, 0xC00, regs->reg_c00);
++		break;
++	case RF_1T2R:
++	case RF_2T2R:
++		rtw_write32(padapter, 0xC00, regs->reg_c00);
++		rtw_write32(padapter, 0xE00, regs->reg_e00);
++		break;
++	case RF_2T3R:
++	case RF_3T3R:
++		rtw_write32(padapter, 0xC00, regs->reg_c00);
++		rtw_write32(padapter, 0xE00, regs->reg_e00);
++		rtw_write32(padapter, 0x1800, regs->reg_1800);
++		break;
++	case RF_2T4R:
++	case RF_3T4R:
++	case RF_4T4R:
++		rtw_write32(padapter, 0xC00, regs->reg_c00);
++		rtw_write32(padapter, 0xE00, regs->reg_e00);
++		rtw_write32(padapter, 0x1800, regs->reg_1800);
++		rtw_write32(padapter, 0x1A00, regs->reg_1a00);
++		break;
++	default:
++		RTW_WARN("%s: unknown %d rf type\n", __func__, phal_data->rf_type);
++		break;
++	}
++
++	/* 11ac cck restore */
++	rtw_write32(padapter, 0x808, regs->reg_808);
++	RTW_INFO("%s: restore %d rf type done\n", __func__, phal_data->rf_type);
++	return 0;
++}
++
++/* reg 0x808[9:0]: FFT data x
++ * reg 0x808[22]:  0  -->  1  to get 1 FFT data y
++ * reg 0x8B4[15:0]: FFT data y report */
++static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point)
++{
++	u32 psd_val = 0;
++
++#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
++	u16 psd_reg = 0x910;
++	u16 psd_regL = 0xF44;
++#else
++	u16 psd_reg = 0x808;
++	u16 psd_regL = 0x8B4;
++#endif
++
++	psd_val = rtw_read32(pAdapter, psd_reg);
++
++	psd_val &= 0xFFBFFC00;
++	psd_val |= point;
++
++	rtw_write32(pAdapter, psd_reg, psd_val);
++	rtw_mdelay_os(1);
++	psd_val |= 0x00400000;
++
++	rtw_write32(pAdapter, psd_reg, psd_val);
++	rtw_mdelay_os(1);
++
++	psd_val = rtw_read32(pAdapter, psd_regL);
++#if defined(CONFIG_RTL8821C)
++	psd_val = (psd_val & 0x00FFFFFF) / 32;
++#else
++	psd_val &= 0x0000FFFF;
++#endif
++
++	return psd_val;
++}
++
++/*
++ * pts	start_point_min		stop_point_max
++ * 128	64			64 + 128 = 192
++ * 256	128			128 + 256 = 384
++ * 512	256			256 + 512 = 768
++ * 1024	512			512 + 1024 = 1536
++ *
++ */
++u32 mp_query_psd(PADAPTER pAdapter, u8 *data)
++{
++	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
++	struct dm_struct *p_dm = adapter_to_phydm(pAdapter);
++
++	u32 i, psd_pts = 0, psd_start = 0, psd_stop = 0;
++	u32 psd_data = 0;
++	struct psd_init_regs regs = {};
++	int psd_analysis = 0;
++	char *pdata = NULL;
++
++
++#ifdef PLATFORM_LINUX
++	if (!netif_running(pAdapter->pnetdev)) {
++		return 0;
++	}
++#endif
++
++	if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
++		return 0;
++	}
++
++	if (strlen(data) == 0) { /* default value */
++		psd_pts = 128;
++		psd_start = 64;
++		psd_stop = 128;
++	} else if (strncmp(data, "analysis,", 9) == 0) {
++		if (rtw_mp_psd_init(pAdapter, &regs) != 0)
++			return 0;
++		psd_analysis = 1;
++		sscanf(data + 9, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop);
++	} else
++		sscanf(data, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop);
++
++	data[0] = '\0';
++	pdata = data;
++
++	if (psd_stop > 1536 || psd_stop < 1) {
++		rtw_warn_on(1);
++		psd_stop = 1536;
++	}
++
++	if (IS_HARDWARE_TYPE_8822C(pAdapter)) {
++			u32 *psdbuf = rtw_zmalloc(sizeof(u32)*256);
++
++			if (psdbuf == NULL) {
++				RTW_INFO("%s: psd buf malloc fail!!\n", __func__);
++				return 0;
++			}
++
++			halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_POINT, psd_pts);
++			halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_START_POINT, psd_start);
++			halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_STOP_POINT, psd_stop);
++			halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_AVERAGE, 0x20000);
++
++			halrf_psd_init(p_dm);
++#ifdef CONFIG_LONG_DELAY_ISSUE
++		rtw_msleep_os(100);
++#else
++		rtw_mdelay_os(10);
++#endif
++			halrf_psd_query(p_dm, psdbuf, 256);
++
++			i = 0;
++			while (i < 256) {
++				pdata += sprintf(pdata, "%x ", (psdbuf[i]));
++				i++;
++			}
++
++		if (psdbuf)
++			rtw_mfree(psdbuf, sizeof(u32)*256);
++
++	} else {
++			i = psd_start;
++
++			while (i < psd_stop) {
++				if (i >= psd_pts)
++					psd_data = rtw_GetPSDData(pAdapter, i - psd_pts);
++				else
++					psd_data = rtw_GetPSDData(pAdapter, i);
++
++				pdata += sprintf(pdata, "%x ", psd_data);
++				i++;
++			}
++
++	}
++
++#ifdef CONFIG_LONG_DELAY_ISSUE
++	rtw_msleep_os(100);
++#else
++	rtw_mdelay_os(100);
++#endif
++
++	if (psd_analysis)
++		rtw_mp_psd_close(pAdapter, &regs);
++
++	return strlen(data) + 1;
++}
++
++
++#if 0
++void _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv)
++{
++	int i, res;
++	_adapter *padapter = pxmitpriv->adapter;
++	struct xmit_frame	*pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;
++	struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;
++
++	u32 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
++	u32 num_xmit_extbuf = NR_XMIT_EXTBUFF;
++	if (padapter->registrypriv.mp_mode == 0) {
++		max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
++		num_xmit_extbuf = NR_XMIT_EXTBUFF;
++	} else {
++		max_xmit_extbuf_size = 6000;
++		num_xmit_extbuf = 8;
++	}
++
++	pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
++	for (i = 0; i < num_xmit_extbuf; i++) {
++		rtw_os_xmit_resource_free(padapter, pxmitbuf, (max_xmit_extbuf_size + XMITBUF_ALIGN_SZ), _FALSE);
++
++		pxmitbuf++;
++	}
++
++	if (pxmitpriv->pallocated_xmit_extbuf)
++		rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
++
++	if (padapter->registrypriv.mp_mode == 0) {
++		max_xmit_extbuf_size = 6000;
++		num_xmit_extbuf = 8;
++	} else {
++		max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
++		num_xmit_extbuf = NR_XMIT_EXTBUFF;
++	}
++
++	/* Init xmit extension buff */
++	_rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue);
++
++	pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
++
++	if (pxmitpriv->pallocated_xmit_extbuf  == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4);
++
++	pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
++
++	for (i = 0; i < num_xmit_extbuf; i++) {
++		_rtw_init_listhead(&pxmitbuf->list);
++
++		pxmitbuf->priv_data = NULL;
++		pxmitbuf->padapter = padapter;
++		pxmitbuf->buf_tag = XMITBUF_MGNT;
++
++		res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, max_xmit_extbuf_size + XMITBUF_ALIGN_SZ, _TRUE);
++		if (res == _FAIL) {
++			res = _FAIL;
++			goto exit;
++		}
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++		pxmitbuf->phead = pxmitbuf->pbuf;
++		pxmitbuf->pend = pxmitbuf->pbuf + max_xmit_extbuf_size;
++		pxmitbuf->len = 0;
++		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
++#endif
++
++		rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue));
++#ifdef DBG_XMIT_BUF_EXT
++		pxmitbuf->no = i;
++#endif
++		pxmitbuf++;
++
++	}
++
++	pxmitpriv->free_xmit_extbuf_cnt = num_xmit_extbuf;
++
++exit:
++	;
++}
++#endif
++
++u8
++mpt_to_mgnt_rate(
++		u32	MptRateIdx
++)
++{
++	/* Mapped to MGN_XXX defined in MgntGen.h */
++	switch (MptRateIdx) {
++	/* CCK rate. */
++	case	MPT_RATE_1M:
++		return MGN_1M;
++	case	MPT_RATE_2M:
++		return MGN_2M;
++	case	MPT_RATE_55M:
++		return MGN_5_5M;
++	case	MPT_RATE_11M:
++		return MGN_11M;
++
++	/* OFDM rate. */
++	case	MPT_RATE_6M:
++		return MGN_6M;
++	case	MPT_RATE_9M:
++		return MGN_9M;
++	case	MPT_RATE_12M:
++		return MGN_12M;
++	case	MPT_RATE_18M:
++		return MGN_18M;
++	case	MPT_RATE_24M:
++		return MGN_24M;
++	case	MPT_RATE_36M:
++		return MGN_36M;
++	case	MPT_RATE_48M:
++		return MGN_48M;
++	case	MPT_RATE_54M:
++		return MGN_54M;
++
++	/* HT rate. */
++	case	MPT_RATE_MCS0:
++		return MGN_MCS0;
++	case	MPT_RATE_MCS1:
++		return MGN_MCS1;
++	case	MPT_RATE_MCS2:
++		return MGN_MCS2;
++	case	MPT_RATE_MCS3:
++		return MGN_MCS3;
++	case	MPT_RATE_MCS4:
++		return MGN_MCS4;
++	case	MPT_RATE_MCS5:
++		return MGN_MCS5;
++	case	MPT_RATE_MCS6:
++		return MGN_MCS6;
++	case	MPT_RATE_MCS7:
++		return MGN_MCS7;
++	case	MPT_RATE_MCS8:
++		return MGN_MCS8;
++	case	MPT_RATE_MCS9:
++		return MGN_MCS9;
++	case	MPT_RATE_MCS10:
++		return MGN_MCS10;
++	case	MPT_RATE_MCS11:
++		return MGN_MCS11;
++	case	MPT_RATE_MCS12:
++		return MGN_MCS12;
++	case	MPT_RATE_MCS13:
++		return MGN_MCS13;
++	case	MPT_RATE_MCS14:
++		return MGN_MCS14;
++	case	MPT_RATE_MCS15:
++		return MGN_MCS15;
++	case	MPT_RATE_MCS16:
++		return MGN_MCS16;
++	case	MPT_RATE_MCS17:
++		return MGN_MCS17;
++	case	MPT_RATE_MCS18:
++		return MGN_MCS18;
++	case	MPT_RATE_MCS19:
++		return MGN_MCS19;
++	case	MPT_RATE_MCS20:
++		return MGN_MCS20;
++	case	MPT_RATE_MCS21:
++		return MGN_MCS21;
++	case	MPT_RATE_MCS22:
++		return MGN_MCS22;
++	case	MPT_RATE_MCS23:
++		return MGN_MCS23;
++	case	MPT_RATE_MCS24:
++		return MGN_MCS24;
++	case	MPT_RATE_MCS25:
++		return MGN_MCS25;
++	case	MPT_RATE_MCS26:
++		return MGN_MCS26;
++	case	MPT_RATE_MCS27:
++		return MGN_MCS27;
++	case	MPT_RATE_MCS28:
++		return MGN_MCS28;
++	case	MPT_RATE_MCS29:
++		return MGN_MCS29;
++	case	MPT_RATE_MCS30:
++		return MGN_MCS30;
++	case	MPT_RATE_MCS31:
++		return MGN_MCS31;
++
++	/* VHT rate. */
++	case	MPT_RATE_VHT1SS_MCS0:
++		return MGN_VHT1SS_MCS0;
++	case	MPT_RATE_VHT1SS_MCS1:
++		return MGN_VHT1SS_MCS1;
++	case	MPT_RATE_VHT1SS_MCS2:
++		return MGN_VHT1SS_MCS2;
++	case	MPT_RATE_VHT1SS_MCS3:
++		return MGN_VHT1SS_MCS3;
++	case	MPT_RATE_VHT1SS_MCS4:
++		return MGN_VHT1SS_MCS4;
++	case	MPT_RATE_VHT1SS_MCS5:
++		return MGN_VHT1SS_MCS5;
++	case	MPT_RATE_VHT1SS_MCS6:
++		return MGN_VHT1SS_MCS6;
++	case	MPT_RATE_VHT1SS_MCS7:
++		return MGN_VHT1SS_MCS7;
++	case	MPT_RATE_VHT1SS_MCS8:
++		return MGN_VHT1SS_MCS8;
++	case	MPT_RATE_VHT1SS_MCS9:
++		return MGN_VHT1SS_MCS9;
++	case	MPT_RATE_VHT2SS_MCS0:
++		return MGN_VHT2SS_MCS0;
++	case	MPT_RATE_VHT2SS_MCS1:
++		return MGN_VHT2SS_MCS1;
++	case	MPT_RATE_VHT2SS_MCS2:
++		return MGN_VHT2SS_MCS2;
++	case	MPT_RATE_VHT2SS_MCS3:
++		return MGN_VHT2SS_MCS3;
++	case	MPT_RATE_VHT2SS_MCS4:
++		return MGN_VHT2SS_MCS4;
++	case	MPT_RATE_VHT2SS_MCS5:
++		return MGN_VHT2SS_MCS5;
++	case	MPT_RATE_VHT2SS_MCS6:
++		return MGN_VHT2SS_MCS6;
++	case	MPT_RATE_VHT2SS_MCS7:
++		return MGN_VHT2SS_MCS7;
++	case	MPT_RATE_VHT2SS_MCS8:
++		return MGN_VHT2SS_MCS8;
++	case	MPT_RATE_VHT2SS_MCS9:
++		return MGN_VHT2SS_MCS9;
++	case	MPT_RATE_VHT3SS_MCS0:
++		return MGN_VHT3SS_MCS0;
++	case	MPT_RATE_VHT3SS_MCS1:
++		return MGN_VHT3SS_MCS1;
++	case	MPT_RATE_VHT3SS_MCS2:
++		return MGN_VHT3SS_MCS2;
++	case	MPT_RATE_VHT3SS_MCS3:
++		return MGN_VHT3SS_MCS3;
++	case	MPT_RATE_VHT3SS_MCS4:
++		return MGN_VHT3SS_MCS4;
++	case	MPT_RATE_VHT3SS_MCS5:
++		return MGN_VHT3SS_MCS5;
++	case	MPT_RATE_VHT3SS_MCS6:
++		return MGN_VHT3SS_MCS6;
++	case	MPT_RATE_VHT3SS_MCS7:
++		return MGN_VHT3SS_MCS7;
++	case	MPT_RATE_VHT3SS_MCS8:
++		return MGN_VHT3SS_MCS8;
++	case	MPT_RATE_VHT3SS_MCS9:
++		return MGN_VHT3SS_MCS9;
++	case	MPT_RATE_VHT4SS_MCS0:
++		return MGN_VHT4SS_MCS0;
++	case	MPT_RATE_VHT4SS_MCS1:
++		return MGN_VHT4SS_MCS1;
++	case	MPT_RATE_VHT4SS_MCS2:
++		return MGN_VHT4SS_MCS2;
++	case	MPT_RATE_VHT4SS_MCS3:
++		return MGN_VHT4SS_MCS3;
++	case	MPT_RATE_VHT4SS_MCS4:
++		return MGN_VHT4SS_MCS4;
++	case	MPT_RATE_VHT4SS_MCS5:
++		return MGN_VHT4SS_MCS5;
++	case	MPT_RATE_VHT4SS_MCS6:
++		return MGN_VHT4SS_MCS6;
++	case	MPT_RATE_VHT4SS_MCS7:
++		return MGN_VHT4SS_MCS7;
++	case	MPT_RATE_VHT4SS_MCS8:
++		return MGN_VHT4SS_MCS8;
++	case	MPT_RATE_VHT4SS_MCS9:
++		return MGN_VHT4SS_MCS9;
++
++	case	MPT_RATE_LAST:	/* fully automatiMGN_VHT2SS_MCS1;	 */
++	default:
++		RTW_INFO("<===mpt_to_mgnt_rate(), Invalid Rate: %d!!\n", MptRateIdx);
++		return 0x0;
++	}
++}
++
++
++u8 HwRateToMPTRate(u8 rate)
++{
++	u8	ret_rate = MGN_1M;
++
++	switch (rate) {
++	case DESC_RATE1M:
++		ret_rate = MPT_RATE_1M;
++		break;
++	case DESC_RATE2M:
++		ret_rate = MPT_RATE_2M;
++		break;
++	case DESC_RATE5_5M:
++		ret_rate = MPT_RATE_55M;
++		break;
++	case DESC_RATE11M:
++		ret_rate = MPT_RATE_11M;
++		break;
++	case DESC_RATE6M:
++		ret_rate = MPT_RATE_6M;
++		break;
++	case DESC_RATE9M:
++		ret_rate = MPT_RATE_9M;
++		break;
++	case DESC_RATE12M:
++		ret_rate = MPT_RATE_12M;
++		break;
++	case DESC_RATE18M:
++		ret_rate = MPT_RATE_18M;
++		break;
++	case DESC_RATE24M:
++		ret_rate = MPT_RATE_24M;
++		break;
++	case DESC_RATE36M:
++		ret_rate = MPT_RATE_36M;
++		break;
++	case DESC_RATE48M:
++		ret_rate = MPT_RATE_48M;
++		break;
++	case DESC_RATE54M:
++		ret_rate = MPT_RATE_54M;
++		break;
++	case DESC_RATEMCS0:
++		ret_rate = MPT_RATE_MCS0;
++		break;
++	case DESC_RATEMCS1:
++		ret_rate = MPT_RATE_MCS1;
++		break;
++	case DESC_RATEMCS2:
++		ret_rate = MPT_RATE_MCS2;
++		break;
++	case DESC_RATEMCS3:
++		ret_rate = MPT_RATE_MCS3;
++		break;
++	case DESC_RATEMCS4:
++		ret_rate = MPT_RATE_MCS4;
++		break;
++	case DESC_RATEMCS5:
++		ret_rate = MPT_RATE_MCS5;
++		break;
++	case DESC_RATEMCS6:
++		ret_rate = MPT_RATE_MCS6;
++		break;
++	case DESC_RATEMCS7:
++		ret_rate = MPT_RATE_MCS7;
++		break;
++	case DESC_RATEMCS8:
++		ret_rate = MPT_RATE_MCS8;
++		break;
++	case DESC_RATEMCS9:
++		ret_rate = MPT_RATE_MCS9;
++		break;
++	case DESC_RATEMCS10:
++		ret_rate = MPT_RATE_MCS10;
++		break;
++	case DESC_RATEMCS11:
++		ret_rate = MPT_RATE_MCS11;
++		break;
++	case DESC_RATEMCS12:
++		ret_rate = MPT_RATE_MCS12;
++		break;
++	case DESC_RATEMCS13:
++		ret_rate = MPT_RATE_MCS13;
++		break;
++	case DESC_RATEMCS14:
++		ret_rate = MPT_RATE_MCS14;
++		break;
++	case DESC_RATEMCS15:
++		ret_rate = MPT_RATE_MCS15;
++		break;
++	case DESC_RATEMCS16:
++		ret_rate = MPT_RATE_MCS16;
++		break;
++	case DESC_RATEMCS17:
++		ret_rate = MPT_RATE_MCS17;
++		break;
++	case DESC_RATEMCS18:
++		ret_rate = MPT_RATE_MCS18;
++		break;
++	case DESC_RATEMCS19:
++		ret_rate = MPT_RATE_MCS19;
++		break;
++	case DESC_RATEMCS20:
++		ret_rate = MPT_RATE_MCS20;
++		break;
++	case DESC_RATEMCS21:
++		ret_rate = MPT_RATE_MCS21;
++		break;
++	case DESC_RATEMCS22:
++		ret_rate = MPT_RATE_MCS22;
++		break;
++	case DESC_RATEMCS23:
++		ret_rate = MPT_RATE_MCS23;
++		break;
++	case DESC_RATEMCS24:
++		ret_rate = MPT_RATE_MCS24;
++		break;
++	case DESC_RATEMCS25:
++		ret_rate = MPT_RATE_MCS25;
++		break;
++	case DESC_RATEMCS26:
++		ret_rate = MPT_RATE_MCS26;
++		break;
++	case DESC_RATEMCS27:
++		ret_rate = MPT_RATE_MCS27;
++		break;
++	case DESC_RATEMCS28:
++		ret_rate = MPT_RATE_MCS28;
++		break;
++	case DESC_RATEMCS29:
++		ret_rate = MPT_RATE_MCS29;
++		break;
++	case DESC_RATEMCS30:
++		ret_rate = MPT_RATE_MCS30;
++		break;
++	case DESC_RATEMCS31:
++		ret_rate = MPT_RATE_MCS31;
++		break;
++	case DESC_RATEVHTSS1MCS0:
++		ret_rate = MPT_RATE_VHT1SS_MCS0;
++		break;
++	case DESC_RATEVHTSS1MCS1:
++		ret_rate = MPT_RATE_VHT1SS_MCS1;
++		break;
++	case DESC_RATEVHTSS1MCS2:
++		ret_rate = MPT_RATE_VHT1SS_MCS2;
++		break;
++	case DESC_RATEVHTSS1MCS3:
++		ret_rate = MPT_RATE_VHT1SS_MCS3;
++		break;
++	case DESC_RATEVHTSS1MCS4:
++		ret_rate = MPT_RATE_VHT1SS_MCS4;
++		break;
++	case DESC_RATEVHTSS1MCS5:
++		ret_rate = MPT_RATE_VHT1SS_MCS5;
++		break;
++	case DESC_RATEVHTSS1MCS6:
++		ret_rate = MPT_RATE_VHT1SS_MCS6;
++		break;
++	case DESC_RATEVHTSS1MCS7:
++		ret_rate = MPT_RATE_VHT1SS_MCS7;
++		break;
++	case DESC_RATEVHTSS1MCS8:
++		ret_rate = MPT_RATE_VHT1SS_MCS8;
++		break;
++	case DESC_RATEVHTSS1MCS9:
++		ret_rate = MPT_RATE_VHT1SS_MCS9;
++		break;
++	case DESC_RATEVHTSS2MCS0:
++		ret_rate = MPT_RATE_VHT2SS_MCS0;
++		break;
++	case DESC_RATEVHTSS2MCS1:
++		ret_rate = MPT_RATE_VHT2SS_MCS1;
++		break;
++	case DESC_RATEVHTSS2MCS2:
++		ret_rate = MPT_RATE_VHT2SS_MCS2;
++		break;
++	case DESC_RATEVHTSS2MCS3:
++		ret_rate = MPT_RATE_VHT2SS_MCS3;
++		break;
++	case DESC_RATEVHTSS2MCS4:
++		ret_rate = MPT_RATE_VHT2SS_MCS4;
++		break;
++	case DESC_RATEVHTSS2MCS5:
++		ret_rate = MPT_RATE_VHT2SS_MCS5;
++		break;
++	case DESC_RATEVHTSS2MCS6:
++		ret_rate = MPT_RATE_VHT2SS_MCS6;
++		break;
++	case DESC_RATEVHTSS2MCS7:
++		ret_rate = MPT_RATE_VHT2SS_MCS7;
++		break;
++	case DESC_RATEVHTSS2MCS8:
++		ret_rate = MPT_RATE_VHT2SS_MCS8;
++		break;
++	case DESC_RATEVHTSS2MCS9:
++		ret_rate = MPT_RATE_VHT2SS_MCS9;
++		break;
++	case DESC_RATEVHTSS3MCS0:
++		ret_rate = MPT_RATE_VHT3SS_MCS0;
++		break;
++	case DESC_RATEVHTSS3MCS1:
++		ret_rate = MPT_RATE_VHT3SS_MCS1;
++		break;
++	case DESC_RATEVHTSS3MCS2:
++		ret_rate = MPT_RATE_VHT3SS_MCS2;
++		break;
++	case DESC_RATEVHTSS3MCS3:
++		ret_rate = MPT_RATE_VHT3SS_MCS3;
++		break;
++	case DESC_RATEVHTSS3MCS4:
++		ret_rate = MPT_RATE_VHT3SS_MCS4;
++		break;
++	case DESC_RATEVHTSS3MCS5:
++		ret_rate = MPT_RATE_VHT3SS_MCS5;
++		break;
++	case DESC_RATEVHTSS3MCS6:
++		ret_rate = MPT_RATE_VHT3SS_MCS6;
++		break;
++	case DESC_RATEVHTSS3MCS7:
++		ret_rate = MPT_RATE_VHT3SS_MCS7;
++		break;
++	case DESC_RATEVHTSS3MCS8:
++		ret_rate = MPT_RATE_VHT3SS_MCS8;
++		break;
++	case DESC_RATEVHTSS3MCS9:
++		ret_rate = MPT_RATE_VHT3SS_MCS9;
++		break;
++	case DESC_RATEVHTSS4MCS0:
++		ret_rate = MPT_RATE_VHT4SS_MCS0;
++		break;
++	case DESC_RATEVHTSS4MCS1:
++		ret_rate = MPT_RATE_VHT4SS_MCS1;
++		break;
++	case DESC_RATEVHTSS4MCS2:
++		ret_rate = MPT_RATE_VHT4SS_MCS2;
++		break;
++	case DESC_RATEVHTSS4MCS3:
++		ret_rate = MPT_RATE_VHT4SS_MCS3;
++		break;
++	case DESC_RATEVHTSS4MCS4:
++		ret_rate = MPT_RATE_VHT4SS_MCS4;
++		break;
++	case DESC_RATEVHTSS4MCS5:
++		ret_rate = MPT_RATE_VHT4SS_MCS5;
++		break;
++	case DESC_RATEVHTSS4MCS6:
++		ret_rate = MPT_RATE_VHT4SS_MCS6;
++		break;
++	case DESC_RATEVHTSS4MCS7:
++		ret_rate = MPT_RATE_VHT4SS_MCS7;
++		break;
++	case DESC_RATEVHTSS4MCS8:
++		ret_rate = MPT_RATE_VHT4SS_MCS8;
++		break;
++	case DESC_RATEVHTSS4MCS9:
++		ret_rate = MPT_RATE_VHT4SS_MCS9;
++		break;
++
++	default:
++		RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate);
++		break;
++	}
++	return ret_rate;
++}
++
++u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr)
++{
++	u16 i = 0;
++	u8 *rateindex_Array[] = { "1M", "2M", "5.5M", "11M", "6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M",
++		"HTMCS0", "HTMCS1", "HTMCS2", "HTMCS3", "HTMCS4", "HTMCS5", "HTMCS6", "HTMCS7",
++		"HTMCS8", "HTMCS9", "HTMCS10", "HTMCS11", "HTMCS12", "HTMCS13", "HTMCS14", "HTMCS15",
++		"HTMCS16", "HTMCS17", "HTMCS18", "HTMCS19", "HTMCS20", "HTMCS21", "HTMCS22", "HTMCS23",
++		"HTMCS24", "HTMCS25", "HTMCS26", "HTMCS27", "HTMCS28", "HTMCS29", "HTMCS30", "HTMCS31",
++		"VHT1MCS0", "VHT1MCS1", "VHT1MCS2", "VHT1MCS3", "VHT1MCS4", "VHT1MCS5", "VHT1MCS6", "VHT1MCS7", "VHT1MCS8", "VHT1MCS9",
++		"VHT2MCS0", "VHT2MCS1", "VHT2MCS2", "VHT2MCS3", "VHT2MCS4", "VHT2MCS5", "VHT2MCS6", "VHT2MCS7", "VHT2MCS8", "VHT2MCS9",
++		"VHT3MCS0", "VHT3MCS1", "VHT3MCS2", "VHT3MCS3", "VHT3MCS4", "VHT3MCS5", "VHT3MCS6", "VHT3MCS7", "VHT3MCS8", "VHT3MCS9",
++		"VHT4MCS0", "VHT4MCS1", "VHT4MCS2", "VHT4MCS3", "VHT4MCS4", "VHT4MCS5", "VHT4MCS6", "VHT4MCS7", "VHT4MCS8", "VHT4MCS9"
++				};
++
++	for (i = 0; i <= 83; i++) {
++		if (strcmp(targetStr, rateindex_Array[i]) == 0) {
++			RTW_INFO("%s , index = %d\n", __func__ , i);
++			return i;
++		}
++	}
++
++	printk("%s ,please input a Data RATE String as:", __func__);
++	for (i = 0; i <= 83; i++) {
++		printk("%s ", rateindex_Array[i]);
++		if (i % 10 == 0)
++			printk("\n");
++	}
++	return _FAIL;
++}
++
++u8 rtw_mp_mode_check(PADAPTER pAdapter)
++{
++	PADAPTER primary_adapter = GET_PRIMARY_ADAPTER(pAdapter);
++
++	if (primary_adapter->registrypriv.mp_mode == 1 || primary_adapter->mppriv.bprocess_mp_mode == _TRUE)
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++bool rtw_is_mp_tssitrk_on(_adapter *adapter)
++{
++	_adapter *primary_adapter = GET_PRIMARY_ADAPTER(adapter);
++
++	return primary_adapter->mppriv.tssitrk_on;
++}
++
++u32 mpt_ProQueryCalTxPower(
++	PADAPTER	pAdapter,
++	u8		RfPath
++)
++{
++
++	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
++	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
++
++	u32			TxPower = 1;
++	struct txpwr_idx_comp tic;
++	u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
++	RATE_SECTION rs = mgn_rate_to_rs(mgn_rate);
++
++	TxPower = rtw_hal_get_tx_power_index(pAdapter, RfPath, rs, mgn_rate
++		, pHalData->current_channel_bw, pHalData->current_band_type, pHalData->current_channel, 0, &tic);
++
++	dump_tx_power_index_inline(RTW_DBGDUMP, pAdapter, RfPath
++		, pHalData->current_channel_bw, pHalData->current_channel
++		, mgn_rate, TxPower, &tic);
++
++	pAdapter->mppriv.txpoweridx = (u8)TxPower;
++	if (RfPath == RF_PATH_A)
++		pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)TxPower;
++	else if (RfPath == RF_PATH_B)
++		pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)TxPower;
++	else if (RfPath == RF_PATH_C)
++		pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)TxPower;
++	else if (RfPath == RF_PATH_D)
++		pMptCtx->TxPwrLevel[RF_PATH_D] = (u8)TxPower;
++	hal_mpt_SetTxPower(pAdapter);
++
++	return TxPower;
++}
++
++u32 mpt_get_tx_power_finalabs_val(PADAPTER	padapter, u8 rf_path)
++{
++	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
++	PMPT_CONTEXT		pMptCtx = &(padapter->mppriv.mpt_ctx);
++
++	u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
++	u32 powerdbm = 0;
++
++	powerdbm = phy_get_tx_power_final_absolute_value(padapter, rf_path, mgn_rate, pHalData->current_channel_bw, pHalData->current_channel);
++	
++	RTW_INFO("bw=%d, ch=%d, rateid=%d, TSSI Power(dBm):%d\n",
++		pHalData->current_channel_bw, pHalData->current_channel, mgn_rate ,powerdbm);
++
++	return powerdbm;
++}
++
++#ifdef CONFIG_MP_VHT_HW_TX_MODE
++static inline void dump_buf(u8 *buf, u32 len)
++{
++	u32 i;
++
++	RTW_INFO("-----------------Len %d----------------\n", len);
++	for (i = 0; i < len; i++)
++		RTW_INFO("%2.2x-", *(buf + i));
++	RTW_INFO("\n");
++}
++
++void ByteToBit(
++	u8	*out,
++	bool	*in,
++	u8	in_size)
++{
++	u8 i = 0, j = 0;
++
++	for (i = 0; i < in_size; i++) {
++		for (j = 0; j < 8; j++) {
++			if (in[8 * i + j])
++				out[i] |= (1 << j);
++		}
++	}
++}
++
++
++void CRC16_generator(
++	bool *out,
++	bool *in,
++	u8 in_size
++)
++{
++	u8 i = 0;
++	bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
++
++	for (i = 0; i < in_size; i++) {/* take one's complement and bit reverse*/
++		temp = in[i] ^ reg[15];
++		reg[15]	= reg[14];
++		reg[14]	= reg[13];
++		reg[13]	= reg[12];
++		reg[12]	= reg[11];
++		reg[11]	= reg[10];
++		reg[10]	= reg[9];
++		reg[9]	= reg[8];
++		reg[8]	= reg[7];
++
++		reg[7]	= reg[6];
++		reg[6]	= reg[5];
++		reg[5]	= reg[4];
++		reg[4]	= reg[3];
++		reg[3]	= reg[2];
++		reg[2]	= reg[1];
++		reg[1]	= reg[0];
++		reg[12]	= reg[12] ^ temp;
++		reg[5]	= reg[5] ^ temp;
++		reg[0]	= temp;
++	}
++	for (i = 0; i < 16; i++)	/* take one's complement and bit reverse*/
++		out[i] = 1 - reg[15 - i];
++}
++
++
++
++/*========================================
++	SFD		SIGNAL	SERVICE	LENGTH	CRC
++	16 bit	8 bit	8 bit	16 bit	16 bit
++========================================*/
++void CCK_generator(
++	PRT_PMAC_TX_INFO	pPMacTxInfo,
++	PRT_PMAC_PKT_INFO	pPMacPktInfo
++)
++{
++	double	ratio = 0;
++	bool	crc16_in[32] = {0}, crc16_out[16] = {0};
++	bool LengthExtBit;
++	double LengthExact;
++	double LengthPSDU;
++	u8 i;
++	u32 PacketLength = pPMacTxInfo->PacketLength;
++
++	if (pPMacTxInfo->bSPreamble)
++		pPMacTxInfo->SFD = 0x05CF;
++	else
++		pPMacTxInfo->SFD = 0xF3A0;
++
++	switch (pPMacPktInfo->MCS) {
++	case 0:
++		pPMacTxInfo->SignalField = 0xA;
++		ratio = 8;
++		/*CRC16_in(1,0:7)=[0 1 0 1 0 0 0 0]*/
++		crc16_in[1] = crc16_in[3] = 1;
++		break;
++	case 1:
++		pPMacTxInfo->SignalField = 0x14;
++		ratio = 4;
++		/*CRC16_in(1,0:7)=[0 0 1 0 1 0 0 0];*/
++		crc16_in[2] = crc16_in[4] = 1;
++		break;
++	case 2:
++		pPMacTxInfo->SignalField = 0x37;
++		ratio = 8.0 / 5.5;
++		/*CRC16_in(1,0:7)=[1 1 1 0 1 1 0 0];*/
++		crc16_in[0] = crc16_in[1] = crc16_in[2] = crc16_in[4] = crc16_in[5] = 1;
++		break;
++	case 3:
++		pPMacTxInfo->SignalField = 0x6E;
++		ratio = 8.0 / 11.0;
++		/*CRC16_in(1,0:7)=[0 1 1 1 0 1 1 0];*/
++		crc16_in[1] = crc16_in[2] = crc16_in[3] = crc16_in[5] = crc16_in[6] = 1;
++		break;
++	}
++
++	LengthExact = PacketLength * ratio;
++	LengthPSDU = ceil(LengthExact);
++
++	if ((pPMacPktInfo->MCS == 3) &&
++	    ((LengthPSDU - LengthExact) >= 0.727 || (LengthPSDU - LengthExact) <= -0.727))
++		LengthExtBit = 1;
++	else
++		LengthExtBit = 0;
++
++
++	pPMacTxInfo->LENGTH = (u32)LengthPSDU;
++	/* CRC16_in(1,16:31) = LengthPSDU[0:15]*/
++	for (i = 0; i < 16; i++)
++		crc16_in[i + 16] = (pPMacTxInfo->LENGTH >> i) & 0x1;
++
++	if (LengthExtBit == 0) {
++		pPMacTxInfo->ServiceField = 0x0;
++		/* CRC16_in(1,8:15) = [0 0 0 0 0 0 0 0];*/
++	} else {
++		pPMacTxInfo->ServiceField = 0x80;
++		/*CRC16_in(1,8:15)=[0 0 0 0 0 0 0 1];*/
++		crc16_in[15] = 1;
++	}
++
++	CRC16_generator(crc16_out, crc16_in, 32);
++
++	_rtw_memset(pPMacTxInfo->CRC16, 0, 2);
++	ByteToBit(pPMacTxInfo->CRC16, crc16_out, 2);
++
++}
++
++
++void PMAC_Get_Pkt_Param(
++	PRT_PMAC_TX_INFO	pPMacTxInfo,
++	PRT_PMAC_PKT_INFO	pPMacPktInfo)
++{
++
++	u8		TX_RATE_HEX = 0, MCS = 0;
++	u8		TX_RATE = pPMacTxInfo->TX_RATE;
++
++	/*	TX_RATE & Nss	*/
++	if (MPT_IS_2SS_RATE(TX_RATE))
++		pPMacPktInfo->Nss = 2;
++	else if (MPT_IS_3SS_RATE(TX_RATE))
++		pPMacPktInfo->Nss = 3;
++	else if (MPT_IS_4SS_RATE(TX_RATE))
++		pPMacPktInfo->Nss = 4;
++	else
++		pPMacPktInfo->Nss = 1;
++
++	RTW_INFO("PMacTxInfo.Nss =%d\n", pPMacPktInfo->Nss);
++
++	/*	MCS & TX_RATE_HEX*/
++	if (MPT_IS_CCK_RATE(TX_RATE)) {
++		switch (TX_RATE) {
++		case MPT_RATE_1M:
++			TX_RATE_HEX = MCS = 0;
++			break;
++		case MPT_RATE_2M:
++			TX_RATE_HEX = MCS = 1;
++			break;
++		case MPT_RATE_55M:
++			TX_RATE_HEX = MCS = 2;
++			break;
++		case MPT_RATE_11M:
++			TX_RATE_HEX = MCS = 3;
++			break;
++		}
++	} else if (MPT_IS_OFDM_RATE(TX_RATE)) {
++		MCS = TX_RATE - MPT_RATE_6M;
++		TX_RATE_HEX = MCS + 4;
++	} else if (MPT_IS_HT_RATE(TX_RATE)) {
++		MCS = TX_RATE - MPT_RATE_MCS0;
++		TX_RATE_HEX = MCS + 12;
++	} else if (MPT_IS_VHT_RATE(TX_RATE)) {
++		TX_RATE_HEX = TX_RATE - MPT_RATE_VHT1SS_MCS0 + 44;
++
++		if (MPT_IS_VHT_2S_RATE(TX_RATE))
++			MCS = TX_RATE - MPT_RATE_VHT2SS_MCS0;
++		else if (MPT_IS_VHT_3S_RATE(TX_RATE))
++			MCS = TX_RATE - MPT_RATE_VHT3SS_MCS0;
++		else if (MPT_IS_VHT_4S_RATE(TX_RATE))
++			MCS = TX_RATE - MPT_RATE_VHT4SS_MCS0;
++		else
++			MCS = TX_RATE - MPT_RATE_VHT1SS_MCS0;
++	}
++
++	pPMacPktInfo->MCS = MCS;
++	pPMacTxInfo->TX_RATE_HEX = TX_RATE_HEX;
++
++	RTW_INFO(" MCS=%d, TX_RATE_HEX =0x%x\n", MCS, pPMacTxInfo->TX_RATE_HEX);
++	/*	mSTBC & Nsts*/
++	pPMacPktInfo->Nsts = pPMacPktInfo->Nss;
++	if (pPMacTxInfo->bSTBC) {
++		if (pPMacPktInfo->Nss == 1) {
++			pPMacTxInfo->m_STBC = 2;
++			pPMacPktInfo->Nsts = pPMacPktInfo->Nss * 2;
++		} else
++			pPMacTxInfo->m_STBC = 1;
++	} else
++		pPMacTxInfo->m_STBC = 1;
++}
++
++
++u32 LDPC_parameter_generator(
++	u32 N_pld_int,
++	u32 N_CBPSS,
++	u32 N_SS,
++	u32 R,
++	u32 m_STBC,
++	u32 N_TCB_int
++)
++{
++	double	CR = 0.;
++	double	N_pld = (double)N_pld_int;
++	double	N_TCB = (double)N_TCB_int;
++	double	N_CW = 0., N_shrt = 0., N_spcw = 0., N_fshrt = 0.;
++	double	L_LDPC = 0., K_LDPC = 0., L_LDPC_info = 0.;
++	double	N_punc = 0., N_ppcw = 0., N_fpunc = 0., N_rep = 0., N_rpcw = 0., N_frep = 0.;
++	double	R_eff = 0.;
++	u32	VHTSIGA2B3  = 0;/* extra symbol from VHT-SIG-A2 Bit 3*/
++
++	if (R == 0)
++		CR	= 0.5;
++	else if (R == 1)
++		CR = 2. / 3.;
++	else if (R == 2)
++		CR = 3. / 4.;
++	else if (R == 3)
++		CR = 5. / 6.;
++
++	if (N_TCB <= 648.) {
++		N_CW	= 1.;
++		if (N_TCB >= N_pld + 912.*(1. - CR))
++			L_LDPC	= 1296.;
++		else
++			L_LDPC	= 648.;
++	} else if (N_TCB <= 1296.) {
++		N_CW	= 1.;
++		if (N_TCB >= (double)N_pld + 1464.*(1. - CR))
++			L_LDPC	= 1944.;
++		else
++			L_LDPC	= 1296.;
++	} else if	(N_TCB <= 1944.) {
++		N_CW	= 1.;
++		L_LDPC	= 1944.;
++	} else if (N_TCB <= 2592.) {
++		N_CW	= 2.;
++		if (N_TCB >= N_pld + 2916.*(1. - CR))
++			L_LDPC	= 1944.;
++		else
++			L_LDPC	= 1296.;
++	} else {
++		N_CW = ceil(N_pld / 1944. / CR);
++		L_LDPC	= 1944.;
++	}
++	/*	Number of information bits per CW*/
++	K_LDPC = L_LDPC * CR;
++	/*	Number of shortening bits					max(0, (N_CW * L_LDPC * R) - N_pld)*/
++	N_shrt = (N_CW * K_LDPC - N_pld) > 0. ? (N_CW * K_LDPC - N_pld) : 0.;
++	/*	Number of shortening bits per CW			N_spcw = rtfloor(N_shrt/N_CW)*/
++	N_spcw = rtfloor(N_shrt / N_CW);
++	/*	The first N_fshrt CWs shorten 1 bit more*/
++	N_fshrt = (double)((int)N_shrt % (int)N_CW);
++	/*	Number of data bits for the last N_CW-N_fshrt CWs*/
++	L_LDPC_info = K_LDPC - N_spcw;
++	/*	Number of puncturing bits*/
++	N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;
++	if (((N_punc > .1 * N_CW * L_LDPC * (1. - CR)) && (N_shrt < 1.2 * N_punc * CR / (1. - CR))) ||
++	    (N_punc > 0.3 * N_CW * L_LDPC * (1. - CR))) {
++		/*cout << "*** N_TCB and N_punc are Recomputed ***" << endl;*/
++		VHTSIGA2B3 = 1;
++		N_TCB += (double)N_CBPSS * N_SS * m_STBC;
++		N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;
++	} else
++		VHTSIGA2B3 = 0;
++
++	return VHTSIGA2B3;
++}	/* function end of LDPC_parameter_generator */
++
++/*========================================
++	Data field of PPDU
++	Get N_sym and SIGA2BB3
++========================================*/
++void PMAC_Nsym_generator(
++	PRT_PMAC_TX_INFO	pPMacTxInfo,
++	PRT_PMAC_PKT_INFO	pPMacPktInfo)
++{
++	u32	SIGA2B3 = 0;
++	u8	TX_RATE = pPMacTxInfo->TX_RATE;
++
++	u32 R, R_list[10] = {0, 0, 2, 0, 2, 1, 2, 3, 2, 3};
++	double CR = 0;
++	u32 N_SD, N_BPSC_list[10] = {1, 2, 2, 4, 4, 6, 6, 6, 8, 8};
++	u32 N_BPSC = 0, N_CBPS = 0, N_DBPS = 0, N_ES = 0, N_SYM = 0, N_pld = 0, N_TCB = 0;
++	int D_R = 0;
++
++	RTW_INFO("TX_RATE = %d\n", TX_RATE);
++	/*	N_SD*/
++	if (pPMacTxInfo->BandWidth == 0)
++		N_SD = 52;
++	else if (pPMacTxInfo->BandWidth == 1)
++		N_SD = 108;
++	else
++		N_SD = 234;
++
++	if (MPT_IS_HT_RATE(TX_RATE)) {
++		u8 MCS_temp;
++
++		if (pPMacPktInfo->MCS > 23)
++			MCS_temp = pPMacPktInfo->MCS - 24;
++		else if (pPMacPktInfo->MCS > 15)
++			MCS_temp = pPMacPktInfo->MCS - 16;
++		else if (pPMacPktInfo->MCS > 7)
++			MCS_temp = pPMacPktInfo->MCS - 8;
++		else
++			MCS_temp = pPMacPktInfo->MCS;
++
++		R = R_list[MCS_temp];
++
++		switch (R) {
++		case 0:
++			CR = .5;
++			break;
++		case 1:
++			CR = 2. / 3.;
++			break;
++		case 2:
++			CR = 3. / 4.;
++			break;
++		case 3:
++			CR = 5. / 6.;
++			break;
++		}
++
++		N_BPSC = N_BPSC_list[MCS_temp];
++		N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;
++		N_DBPS = (u32)((double)N_CBPS * CR);
++
++		if (pPMacTxInfo->bLDPC == FALSE) {
++			N_ES = (u32)ceil((double)(N_DBPS * pPMacPktInfo->Nss) / 4. / 300.);
++			RTW_INFO("N_ES = %d\n", N_ES);
++
++			/*	N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/
++			N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) /
++					(double)(N_DBPS * pPMacTxInfo->m_STBC));
++
++		} else {
++			N_ES = 1;
++			/*	N_pld = length * 8 + 16*/
++			N_pld = pPMacTxInfo->PacketLength * 8 + 16;
++			RTW_INFO("N_pld = %d\n", N_pld);
++			N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(N_pld) /
++					(double)(N_DBPS * pPMacTxInfo->m_STBC));
++			RTW_INFO("N_SYM = %d\n", N_SYM);
++			/*	N_avbits = N_CBPS *m_STBC *(N_pld/N_CBPS*R*m_STBC)*/
++			N_TCB = N_CBPS * N_SYM;
++			RTW_INFO("N_TCB = %d\n", N_TCB);
++			SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);
++			RTW_INFO("SIGA2B3 = %d\n", SIGA2B3);
++			N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;
++			RTW_INFO("N_SYM = %d\n", N_SYM);
++		}
++	} else if (MPT_IS_VHT_RATE(TX_RATE)) {
++		R = R_list[pPMacPktInfo->MCS];
++
++		switch (R) {
++		case 0:
++			CR = .5;
++			break;
++		case 1:
++			CR = 2. / 3.;
++			break;
++		case 2:
++			CR = 3. / 4.;
++			break;
++		case 3:
++			CR = 5. / 6.;
++			break;
++		}
++		N_BPSC = N_BPSC_list[pPMacPktInfo->MCS];
++		N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;
++		N_DBPS = (u32)((double)N_CBPS * CR);
++		if (pPMacTxInfo->bLDPC == FALSE) {
++			if (pPMacTxInfo->bSGI)
++				N_ES = (u32)ceil((double)(N_DBPS) / 3.6 / 600.);
++			else
++				N_ES = (u32)ceil((double)(N_DBPS) / 4. / 600.);
++			/*	N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/
++			N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) / (double)(N_DBPS * pPMacTxInfo->m_STBC));
++			SIGA2B3 = 0;
++		} else {
++			N_ES = 1;
++			/*	N_SYM = m_STBC* (8*length+N_service) / (m_STBC*N_DBPS)*/
++			N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16) / (double)(N_DBPS * pPMacTxInfo->m_STBC));
++			/*	N_avbits = N_sys_init * N_CBPS*/
++			N_TCB = N_CBPS * N_SYM;
++			/*	N_pld = N_sys_init * N_DBPS*/
++			N_pld = N_SYM * N_DBPS;
++			SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);
++			N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;
++		}
++
++		switch (R) {
++		case 0:
++			D_R = 2;
++			break;
++		case 1:
++			D_R = 3;
++			break;
++		case 2:
++			D_R = 4;
++			break;
++		case 3:
++			D_R = 6;
++			break;
++		}
++
++		if (((N_CBPS / N_ES) % D_R) != 0) {
++			RTW_INFO("MCS= %d is not supported when Nss=%d and BW= %d !!\n",  pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);
++			return;
++		}
++
++		RTW_INFO("MCS= %d Nss=%d and BW= %d !!\n",  pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);
++	}
++
++	pPMacPktInfo->N_sym = N_SYM;
++	pPMacPktInfo->SIGA2B3 = SIGA2B3;
++}
++
++/*========================================
++	L-SIG	Rate	R	Length	P	Tail
++			4b		1b	12b		1b	6b
++========================================*/
++
++void L_SIG_generator(
++	u32	N_SYM,		/* Max: 750*/
++	PRT_PMAC_TX_INFO	pPMacTxInfo,
++	PRT_PMAC_PKT_INFO	pPMacPktInfo)
++{
++	u8	sig_bi[24] = {0};	/* 24 BIT*/
++	u32	mode, LENGTH;
++	int i;
++
++	if (MPT_IS_OFDM_RATE(pPMacTxInfo->TX_RATE)) {
++		mode = pPMacPktInfo->MCS;
++		LENGTH = pPMacTxInfo->PacketLength;
++	} else {
++		u8	N_LTF;
++		double	T_data;
++		u32	OFDM_symbol;
++
++		mode = 0;
++
++		/*	Table 20-13 Num of HT-DLTFs request*/
++		if (pPMacPktInfo->Nsts <= 2)
++			N_LTF = pPMacPktInfo->Nsts;
++		else
++			N_LTF = 4;
++
++		if (pPMacTxInfo->bSGI)
++			T_data = 3.6;
++		else
++			T_data = 4.0;
++
++		/*(L-SIG, HT-SIG, HT-STF, HT-LTF....HT-LTF, Data)*/
++		if (MPT_IS_VHT_RATE(pPMacTxInfo->TX_RATE))
++			OFDM_symbol = (u32)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data + 4) / 4.);
++		else
++			OFDM_symbol = (u32)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data) / 4.);
++
++		RTW_INFO("%s , OFDM_symbol =%d\n", __func__, OFDM_symbol);
++		LENGTH = OFDM_symbol * 3 - 3;
++		RTW_INFO("%s , LENGTH =%d\n", __func__, LENGTH);
++
++	}
++	/*	Rate Field*/
++	switch (mode) {
++	case	0:
++		sig_bi[0] = 1;
++		sig_bi[1] = 1;
++		sig_bi[2] = 0;
++		sig_bi[3] = 1;
++		break;
++	case	1:
++		sig_bi[0] = 1;
++		sig_bi[1] = 1;
++		sig_bi[2] = 1;
++		sig_bi[3] = 1;
++		break;
++	case	2:
++		sig_bi[0] = 0;
++		sig_bi[1] = 1;
++		sig_bi[2] = 0;
++		sig_bi[3] = 1;
++		break;
++	case	3:
++		sig_bi[0] = 0;
++		sig_bi[1] = 1;
++		sig_bi[2] = 1;
++		sig_bi[3] = 1;
++		break;
++	case	4:
++		sig_bi[0] = 1;
++		sig_bi[1] = 0;
++		sig_bi[2] = 0;
++		sig_bi[3] = 1;
++		break;
++	case	5:
++		sig_bi[0] = 1;
++		sig_bi[1] = 0;
++		sig_bi[2] = 1;
++		sig_bi[3] = 1;
++		break;
++	case	6:
++		sig_bi[0] = 0;
++		sig_bi[1] = 0;
++		sig_bi[2] = 0;
++		sig_bi[3] = 1;
++		break;
++	case	7:
++		sig_bi[0] = 0;
++		sig_bi[1] = 0;
++		sig_bi[2] = 1;
++		sig_bi[3] = 1;
++		break;
++	}
++	/*Reserved bit*/
++	sig_bi[4] = 0;
++
++	/*	Length Field*/
++	for (i = 0; i < 12; i++)
++		sig_bi[i + 5] = (LENGTH >> i) & 1;
++
++	/* Parity Bit*/
++	sig_bi[17] = 0;
++	for (i = 0; i < 17; i++)
++		sig_bi[17] = sig_bi[17] + sig_bi[i];
++
++	sig_bi[17] %= 2;
++
++	/*	Tail Field*/
++	for (i = 18; i < 24; i++)
++		sig_bi[i] = 0;
++
++	/* dump_buf(sig_bi,24);*/
++	_rtw_memset(pPMacTxInfo->LSIG, 0, 3);
++	ByteToBit(pPMacTxInfo->LSIG, (bool *)sig_bi, 3);
++}
++
++
++void CRC8_generator(
++	bool	*out,
++	bool	*in,
++	u8	in_size
++)
++{
++	u8 i = 0;
++	bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1};
++
++	for (i = 0; i < in_size; i++) { /* take one's complement and bit reverse*/
++		temp = in[i] ^ reg[7];
++		reg[7]	= reg[6];
++		reg[6]	= reg[5];
++		reg[5]	= reg[4];
++		reg[4]	= reg[3];
++		reg[3]	= reg[2];
++		reg[2]	= reg[1] ^ temp;
++		reg[1]	= reg[0] ^ temp;
++		reg[0]	= temp;
++	}
++	for (i = 0; i < 8; i++)/* take one's complement and bit reverse*/
++		out[i] = reg[7 - i] ^ 1;
++}
++
++/*/================================================================================
++	HT-SIG1	MCS	CW	Length		24BIT + 24BIT
++			7b	1b	16b
++	HT-SIG2	Smoothing	Not sounding	Rsvd		AGG	STBC	FEC	SGI	N_ELTF	CRC	Tail
++			1b			1b			1b		1b	2b		1b	1b	2b		8b	6b
++================================================================================*/
++void HT_SIG_generator(
++	PRT_PMAC_TX_INFO	pPMacTxInfo,
++	PRT_PMAC_PKT_INFO	pPMacPktInfo
++)
++{
++	u32 i;
++	bool sig_bi[48] = {0}, crc8[8] = {0};
++	/*	MCS Field*/
++	for (i = 0; i < 7; i++)
++		sig_bi[i] = (pPMacPktInfo->MCS >> i) & 0x1;
++	/*	Packet BW Setting*/
++	sig_bi[7] = pPMacTxInfo->BandWidth;
++	/*	HT-Length Field*/
++	for (i = 0; i < 16; i++)
++		sig_bi[i + 8] = (pPMacTxInfo->PacketLength >> i) & 0x1;
++	/*	Smoothing;	1->allow smoothing*/
++	sig_bi[24] = 1;
++	/*Not Sounding*/
++	sig_bi[25] = 1 - pPMacTxInfo->NDP_sound;
++	/*Reserved bit*/
++	sig_bi[26] = 1;
++	/*/Aggregate*/
++	sig_bi[27] = 0;
++	/*STBC Field*/
++	if (pPMacTxInfo->bSTBC) {
++		sig_bi[28] = 1;
++		sig_bi[29] = 0;
++	} else {
++		sig_bi[28] = 0;
++		sig_bi[29] = 0;
++	}
++	/*Advance Coding,	0: BCC, 1: LDPC*/
++	sig_bi[30] = pPMacTxInfo->bLDPC;
++	/* Short GI*/
++	sig_bi[31] = pPMacTxInfo->bSGI;
++	/* N_ELTFs*/
++	if (pPMacTxInfo->NDP_sound == FALSE) {
++		sig_bi[32]	= 0;
++		sig_bi[33]	= 0;
++	} else {
++		int	N_ELTF = pPMacTxInfo->Ntx - pPMacPktInfo->Nss;
++
++		for (i = 0; i < 2; i++)
++			sig_bi[32 + i] = (N_ELTF >> i) % 2;
++	}
++	/*	CRC-8*/
++	CRC8_generator(crc8, sig_bi, 34);
++
++	for (i = 0; i < 8; i++)
++		sig_bi[34 + i] = crc8[i];
++
++	/*Tail*/
++	for (i = 42; i < 48; i++)
++		sig_bi[i] = 0;
++
++	_rtw_memset(pPMacTxInfo->HT_SIG, 0, 6);
++	ByteToBit(pPMacTxInfo->HT_SIG, sig_bi, 6);
++}
++
++
++/*======================================================================================
++	VHT-SIG-A1
++	BW	Reserved	STBC	G_ID	SU_Nsts	P_AID	TXOP_PS_NOT_ALLOW	Reserved
++	2b	1b			1b		6b	3b	9b		1b		2b					1b
++	VHT-SIG-A2
++	SGI	SGI_Nsym	SU/MU coding	LDPC_Extra	SU_NCS	Beamformed	Reserved	CRC	Tail
++	1b	1b			1b				1b			4b		1b			1b			8b	6b
++======================================================================================*/
++void VHT_SIG_A_generator(
++	PRT_PMAC_TX_INFO	pPMacTxInfo,
++	PRT_PMAC_PKT_INFO	pPMacPktInfo)
++{
++	u32 i;
++	bool sig_bi[48], crc8[8];
++
++	_rtw_memset(sig_bi, 0, 48);
++	_rtw_memset(crc8, 0, 8);
++
++	/*	BW Setting*/
++	for (i = 0; i < 2; i++)
++		sig_bi[i] = (pPMacTxInfo->BandWidth >> i) & 0x1;
++	/* Reserved Bit*/
++	sig_bi[2] = 1;
++	/*STBC Field*/
++	sig_bi[3] = pPMacTxInfo->bSTBC;
++	/*Group ID: Single User->A value of 0 or 63 indicates an SU PPDU. */
++	for (i = 0; i < 6; i++)
++		sig_bi[4 + i] = 0;
++	/*	N_STS/Partial AID*/
++	for (i = 0; i < 12; i++) {
++		if (i < 3)
++			sig_bi[10 + i] = ((pPMacPktInfo->Nsts - 1) >> i) & 0x1;
++		else
++			sig_bi[10 + i] = 0;
++	}
++	/*TXOP_PS_NOT_ALLPWED*/
++	sig_bi[22]	= 0;
++	/*Reserved Bits*/
++	sig_bi[23]	= 1;
++	/*Short GI*/
++	sig_bi[24] = pPMacTxInfo->bSGI;
++	if (pPMacTxInfo->bSGI > 0 && (pPMacPktInfo->N_sym % 10) == 9)
++		sig_bi[25] = 1;
++	else
++		sig_bi[25] = 0;
++	/* SU/MU[0] Coding*/
++	sig_bi[26] = pPMacTxInfo->bLDPC;	/*	0:BCC, 1:LDPC		*/
++	sig_bi[27] = pPMacPktInfo->SIGA2B3;	/*/	Record Extra OFDM Symols is added or not when LDPC is used*/
++	/*SU MCS/MU[1-3] Coding*/
++	for (i = 0; i < 4; i++)
++		sig_bi[28 + i] = (pPMacPktInfo->MCS >> i) & 0x1;
++	/*SU Beamform */
++	sig_bi[32] = 0;	/*packet.TXBF_en;*/
++	/*Reserved Bit*/
++	sig_bi[33] = 1;
++	/*CRC-8*/
++	CRC8_generator(crc8, sig_bi, 34);
++	for (i = 0; i < 8; i++)
++		sig_bi[34 + i]	= crc8[i];
++	/*Tail*/
++	for (i = 42; i < 48; i++)
++		sig_bi[i] = 0;
++
++	_rtw_memset(pPMacTxInfo->VHT_SIG_A, 0, 6);
++	ByteToBit(pPMacTxInfo->VHT_SIG_A, sig_bi, 6);
++}
++
++/*======================================================================================
++	VHT-SIG-B
++	Length				Resesrved	Trail
++	17/19/21 BIT		3/2/2 BIT	6b
++======================================================================================*/
++void VHT_SIG_B_generator(
++	PRT_PMAC_TX_INFO	pPMacTxInfo)
++{
++	bool sig_bi[32], crc8_bi[8];
++	u32 i, len, res, tail = 6, total_len, crc8_in_len;
++	u32 sigb_len;
++
++	_rtw_memset(sig_bi, 0, 32);
++	_rtw_memset(crc8_bi, 0, 8);
++
++	/*Sounding Packet*/
++	if (pPMacTxInfo->NDP_sound == 1) {
++		if (pPMacTxInfo->BandWidth == 0) {
++			bool sigb_temp[26] = {0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};
++
++			_rtw_memcpy(sig_bi, sigb_temp, 26);
++		} else if (pPMacTxInfo->BandWidth == 1) {
++			bool sigb_temp[27] = {1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0};
++
++			_rtw_memcpy(sig_bi, sigb_temp, 27);
++		} else if (pPMacTxInfo->BandWidth == 2) {
++			bool sigb_temp[29] = {0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};
++
++			_rtw_memcpy(sig_bi, sigb_temp, 29);
++		}
++	} else {	/* Not NDP Sounding*/
++		bool *sigb_temp[29] = {0};
++
++		if (pPMacTxInfo->BandWidth == 0) {
++			len = 17;
++			res = 3;
++		} else if (pPMacTxInfo->BandWidth == 1) {
++			len = 19;
++			res = 2;
++		} else if (pPMacTxInfo->BandWidth == 2) {
++			len	= 21;
++			res	= 2;
++		} else {
++			len	= 21;
++			res	= 2;
++		}
++		total_len = len + res + tail;
++		crc8_in_len = len + res;
++
++		/*Length Field*/
++		sigb_len = (pPMacTxInfo->PacketLength + 3) >> 2;
++
++		for (i = 0; i < len; i++)
++			sig_bi[i] = (sigb_len >> i) & 0x1;
++		/*Reserved Field*/
++		for (i = 0; i < res; i++)
++			sig_bi[len + i] = 1;
++		/* CRC-8*/
++		CRC8_generator(crc8_bi, sig_bi, crc8_in_len);
++
++		/* Tail */
++		for (i = 0; i < tail; i++)
++			sig_bi[len + res + i] = 0;
++	}
++
++	_rtw_memset(pPMacTxInfo->VHT_SIG_B, 0, 4);
++	ByteToBit(pPMacTxInfo->VHT_SIG_B, sig_bi, 4);
++
++	pPMacTxInfo->VHT_SIG_B_CRC = 0;
++	ByteToBit(&(pPMacTxInfo->VHT_SIG_B_CRC), crc8_bi, 1);
++}
++
++/*=======================
++ VHT Delimiter
++=======================*/
++void VHT_Delimiter_generator(
++	PRT_PMAC_TX_INFO	pPMacTxInfo
++)
++{
++	bool sig_bi[32] = {0}, crc8[8] = {0};
++	u32 crc8_in_len = 16;
++	u32 PacketLength = pPMacTxInfo->PacketLength;
++	int j;
++
++	/* Delimiter[0]: EOF*/
++	sig_bi[0] = 1;
++	/* Delimiter[1]: Reserved*/
++	sig_bi[1] = 0;
++	/* Delimiter[3:2]: MPDU Length High*/
++	sig_bi[2] = ((PacketLength - 4) >> 12) % 2;
++	sig_bi[3] = ((PacketLength - 4) >> 13) % 2;
++	/* Delimiter[15:4]: MPDU Length Low*/
++	for (j = 4; j < 16; j++)
++		sig_bi[j] = ((PacketLength - 4) >> (j - 4)) % 2;
++	CRC8_generator(crc8, sig_bi, crc8_in_len);
++	for (j = 16; j < 24; j++) /* Delimiter[23:16]: CRC 8*/
++		sig_bi[j] = crc8[j - 16];
++	for (j = 24; j < 32; j++) /* Delimiter[31:24]: Signature ('4E' in Hex, 78 in Dec)*/
++		sig_bi[j]	= (78 >> (j - 24)) % 2;
++
++	_rtw_memset(pPMacTxInfo->VHT_Delimiter, 0, 4);
++	ByteToBit(pPMacTxInfo->VHT_Delimiter, sig_bi, 4);
++}
++
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_odm.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_odm.c
+new file mode 100644
+index 000000000..750598cc6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_odm.c
+@@ -0,0 +1,586 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <rtw_odm.h>
++#include <hal_data.h>
++
++u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
++	struct dm_struct *podmpriv = &pHalData->odmpriv;
++	u32 result = 0;
++
++	switch (ops) {
++	case HAL_PHYDM_DIS_ALL_FUNC:
++		podmpriv->support_ability = DYNAMIC_FUNC_DISABLE;
++		halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, DYNAMIC_FUNC_DISABLE);
++		break;
++	case HAL_PHYDM_FUNC_SET:
++		podmpriv->support_ability |= ability;
++		break;
++	case HAL_PHYDM_FUNC_CLR:
++		podmpriv->support_ability &= ~(ability);
++		break;
++	case HAL_PHYDM_ABILITY_BK:
++		/* dm flag backup*/
++		podmpriv->bk_support_ability = podmpriv->support_ability;
++		pHalData->bk_rf_ability = halrf_cmn_info_get(podmpriv, HALRF_CMNINFO_ABILITY);
++		break;
++	case HAL_PHYDM_ABILITY_RESTORE:
++		/* restore dm flag */
++		podmpriv->support_ability = podmpriv->bk_support_ability;
++		halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, pHalData->bk_rf_ability);
++		break;
++	case HAL_PHYDM_ABILITY_SET:
++		podmpriv->support_ability = ability;
++		break;
++	case HAL_PHYDM_ABILITY_GET:
++		result = podmpriv->support_ability;
++		break;
++	}
++	return result;
++}
++
++/* set ODM_CMNINFO_IC_TYPE based on chip_type */
++void rtw_odm_init_ic_type(_adapter *adapter)
++{
++	struct dm_struct *odm = adapter_to_phydm(adapter);
++	u32 ic_type = chip_type_to_odm_ic_type(rtw_get_chip_type(adapter));
++
++	rtw_warn_on(!ic_type);
++
++	odm_cmn_info_init(odm, ODM_CMNINFO_IC_TYPE, ic_type);
++}
++
++void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)
++{
++	RTW_PRINT_SEL(sel, "ADAPTIVITY_VERSION "ADAPTIVITY_VERSION"\n");
++}
++
++#define RTW_ADAPTIVITY_EN_DISABLE 0
++#define RTW_ADAPTIVITY_EN_ENABLE 1
++
++void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter)
++{
++	struct registry_priv *regsty = &adapter->registrypriv;
++
++	RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_EN_");
++
++	if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_DISABLE)
++		_RTW_PRINT_SEL(sel, "DISABLE\n");
++	else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
++		_RTW_PRINT_SEL(sel, "ENABLE\n");
++	else
++		_RTW_PRINT_SEL(sel, "INVALID\n");
++}
++
++#define RTW_ADAPTIVITY_MODE_NORMAL 0
++#define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1
++
++void rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter)
++{
++	struct registry_priv *regsty = &adapter->registrypriv;
++
++	RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_MODE_");
++
++	if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_NORMAL)
++		_RTW_PRINT_SEL(sel, "NORMAL\n");
++	else if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_CARRIER_SENSE)
++		_RTW_PRINT_SEL(sel, "CARRIER_SENSE\n");
++	else
++		_RTW_PRINT_SEL(sel, "INVALID\n");
++}
++
++void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter)
++{
++	rtw_odm_adaptivity_ver_msg(sel, adapter);
++	rtw_odm_adaptivity_en_msg(sel, adapter);
++	rtw_odm_adaptivity_mode_msg(sel, adapter);
++}
++
++bool rtw_odm_adaptivity_needed(_adapter *adapter)
++{
++	struct registry_priv *regsty = &adapter->registrypriv;
++	bool ret = _FALSE;
++
++	if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
++		ret = _TRUE;
++
++	return ret;
++}
++
++void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter)
++{
++	struct dm_struct *odm = adapter_to_phydm(adapter);
++
++	rtw_odm_adaptivity_config_msg(sel, adapter);
++
++	RTW_PRINT_SEL(sel, "%10s %16s\n"
++		, "th_l2h_ini", "th_edcca_hl_diff");
++	RTW_PRINT_SEL(sel, "0x%-8x %-16d\n"
++		, (u8)odm->th_l2h_ini
++		, odm->th_edcca_hl_diff
++	);
++}
++
++void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff)
++{
++	struct dm_struct *odm = adapter_to_phydm(adapter);
++
++	odm->th_l2h_ini = th_l2h_ini;
++	odm->th_edcca_hl_diff = th_edcca_hl_diff;
++}
++
++void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter)
++{
++	struct dm_struct *odm = adapter_to_phydm(adapter);
++
++	RTW_PRINT_SEL(sel, "rx_rate = %s, rssi_a = %d(%%), rssi_b = %d(%%)\n",
++		      HDATA_RATE(odm->rx_rate), odm->rssi_a, odm->rssi_b);
++}
++
++
++void rtw_odm_acquirespinlock(_adapter *adapter,	enum rt_spinlock_type type)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(adapter);
++	_irqL irqL;
++
++	switch (type) {
++	case RT_IQK_SPINLOCK:
++		_enter_critical_bh(&pHalData->IQKSpinLock, &irqL);
++	default:
++		break;
++	}
++}
++
++void rtw_odm_releasespinlock(_adapter *adapter,	enum rt_spinlock_type type)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(adapter);
++	_irqL irqL;
++
++	switch (type) {
++	case RT_IQK_SPINLOCK:
++		_exit_critical_bh(&pHalData->IQKSpinLock, &irqL);
++	default:
++		break;
++	}
++}
++
++s16 rtw_odm_get_tx_power_mbm(struct dm_struct *dm, u8 rfpath, u8 rate, u8 bw, u8 cch)
++{
++	return phy_get_txpwr_single_mbm(dm->adapter, rfpath, mgn_rate_to_rs(rate), rate, bw, cch, 0, NULL);
++}
++
++#ifdef CONFIG_DFS_MASTER
++inline void rtw_odm_radar_detect_reset(_adapter *adapter)
++{
++	phydm_radar_detect_reset(adapter_to_phydm(adapter));
++}
++
++inline void rtw_odm_radar_detect_disable(_adapter *adapter)
++{
++	phydm_radar_detect_disable(adapter_to_phydm(adapter));
++}
++
++/* called after ch, bw is set */
++inline void rtw_odm_radar_detect_enable(_adapter *adapter)
++{
++	phydm_radar_detect_enable(adapter_to_phydm(adapter));
++}
++
++inline BOOLEAN rtw_odm_radar_detect(_adapter *adapter)
++{
++	return phydm_radar_detect(adapter_to_phydm(adapter));
++}
++
++inline u8 rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv *dvobj)
++{
++	return phydm_dfs_polling_time(dvobj_to_phydm(dvobj));
++}
++#endif /* CONFIG_DFS_MASTER */
++
++void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys)
++{
++#ifndef DBG_RX_PHYSTATUS_CHINFO
++#define DBG_RX_PHYSTATUS_CHINFO 0
++#endif
++
++#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
++	_adapter *adapter = rframe->u.hdr.adapter;
++	struct dm_struct *phydm = adapter_to_phydm(adapter);
++	struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib;
++	u8 *wlanhdr = get_recvframe_data(rframe);
++
++	if (phydm->support_ic_type & PHYSTS_2ND_TYPE_IC) {
++		/*
++		* 8723D:
++		* type_0(CCK)
++		*     l_rxsc
++		*         is filled with primary channel SC, not real rxsc.
++		*         0:LSC, 1:USC
++		* type_1(OFDM)
++		*     rf_mode
++		*         RF bandwidth when RX
++		*     l_rxsc(legacy), ht_rxsc
++		*         see below RXSC N-series
++		* type_2(Not used)
++		*/
++		/*
++		* 8821C, 8822B:
++		* type_0(CCK)
++		*     l_rxsc
++		*         is filled with primary channel SC, not real rxsc.
++		*         0:LSC, 1:USC
++		* type_1(OFDM)
++		*     rf_mode
++		*         RF bandwidth when RX
++		*     l_rxsc(legacy), ht_rxsc
++		*         see below RXSC AC-series
++		* type_2(Not used)
++		*/
++
++		if ((*phys & 0xf) == 0) {
++			struct phy_sts_rpt_jgr2_type0 *phys_t0 = (struct phy_sts_rpt_jgr2_type0 *)phys;
++
++			if (DBG_RX_PHYSTATUS_CHINFO) {
++				RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u)\n"
++					, *phys & 0xf
++					, MAC_ARG(get_ta(wlanhdr))
++					, is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
++					, HDATA_RATE(attrib->data_rate)
++					, phys_t0->band, phys_t0->channel, phys_t0->rxsc
++				);
++			}
++
++		} else if ((*phys & 0xf) == 1) {
++			struct phy_sts_rpt_jgr2_type1 *phys_t1 = (struct phy_sts_rpt_jgr2_type1 *)phys;
++			u8 rxsc = (attrib->data_rate > DESC_RATE11M && attrib->data_rate < DESC_RATEMCS0) ? phys_t1->l_rxsc : phys_t1->ht_rxsc;
++			u8 pkt_cch = 0;
++			u8 pkt_bw = CHANNEL_WIDTH_20;
++
++			#if	ODM_IC_11N_SERIES_SUPPORT
++			if (phydm->support_ic_type & ODM_IC_11N_SERIES) {
++				/* RXSC N-series */
++				#define RXSC_DUP	0
++				#define RXSC_LSC	1
++				#define RXSC_USC	2
++				#define RXSC_40M	3
++
++				static const s8 cch_offset_by_rxsc[4] = {0, -2, 2, 0};
++
++				if (phys_t1->rf_mode == 0) {
++					pkt_cch = phys_t1->channel;
++					pkt_bw = CHANNEL_WIDTH_20;
++				} else if (phys_t1->rf_mode == 1) {
++					if (rxsc == RXSC_LSC || rxsc == RXSC_USC) {
++						pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
++						pkt_bw = CHANNEL_WIDTH_20;
++					} else if (rxsc == RXSC_40M) {
++						pkt_cch = phys_t1->channel;
++						pkt_bw = CHANNEL_WIDTH_40;
++					}
++				} else
++					rtw_warn_on(1);
++
++				goto type1_end;
++			}
++			#endif /* ODM_IC_11N_SERIES_SUPPORT */
++
++			#if	ODM_IC_11AC_SERIES_SUPPORT
++			if (phydm->support_ic_type & ODM_IC_11AC_SERIES) {
++				/* RXSC AC-series */
++				#define RXSC_DUP			0 /* 0: RX from all SC of current rf_mode */
++
++				#define RXSC_LL20M_OF_160M	8 /* 1~8: RX from 20MHz SC */
++				#define RXSC_L20M_OF_160M	6
++				#define RXSC_L20M_OF_80M	4
++				#define RXSC_L20M_OF_40M	2
++				#define RXSC_U20M_OF_40M	1
++				#define RXSC_U20M_OF_80M	3
++				#define RXSC_U20M_OF_160M	5
++				#define RXSC_UU20M_OF_160M	7
++
++				#define RXSC_L40M_OF_160M	12 /* 9~12: RX from 40MHz SC */
++				#define RXSC_L40M_OF_80M	10
++				#define RXSC_U40M_OF_80M	9
++				#define RXSC_U40M_OF_160M	11
++
++				#define RXSC_L80M_OF_160M	14 /* 13~14: RX from 80MHz SC */
++				#define RXSC_U80M_OF_160M	13
++
++				static const s8 cch_offset_by_rxsc[15] = {0, 2, -2, 6, -6, 10, -10, 14, -14, 4, -4, 12, -12, 8, -8};
++
++				if (phys_t1->rf_mode == 0) {
++					/* RF 20MHz */
++					pkt_cch = phys_t1->channel;
++					pkt_bw = CHANNEL_WIDTH_20;
++					goto type1_end;
++				}
++
++				if (rxsc == 0) {
++					/* RF and RX with same BW */
++					if (attrib->data_rate >= DESC_RATEMCS0) {
++						pkt_cch = phys_t1->channel;
++						pkt_bw = phys_t1->rf_mode;
++					}
++					goto type1_end;
++				}
++
++				if ((phys_t1->rf_mode == 1 && rxsc >= 1 && rxsc <= 2) /* RF 40MHz, RX 20MHz */
++					|| (phys_t1->rf_mode == 2 && rxsc >= 1 && rxsc <= 4) /* RF 80MHz, RX 20MHz */
++					|| (phys_t1->rf_mode == 3 && rxsc >= 1 && rxsc <= 8) /* RF 160MHz, RX 20MHz */
++				) {
++					pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
++					pkt_bw = CHANNEL_WIDTH_20;
++				} else if ((phys_t1->rf_mode == 2 && rxsc >= 9 && rxsc <= 10) /* RF 80MHz, RX 40MHz */
++					|| (phys_t1->rf_mode == 3 && rxsc >= 9 && rxsc <= 12) /* RF 160MHz, RX 40MHz */
++				) {
++					if (attrib->data_rate >= DESC_RATEMCS0) {
++						pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
++						pkt_bw = CHANNEL_WIDTH_40;
++					}
++				} else if ((phys_t1->rf_mode == 3 && rxsc >= 13 && rxsc <= 14) /* RF 160MHz, RX 80MHz */
++				) {
++					if (attrib->data_rate >= DESC_RATEMCS0) {
++						pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
++						pkt_bw = CHANNEL_WIDTH_80;
++					}
++				} else
++					rtw_warn_on(1);
++
++			}
++			#endif /* ODM_IC_11AC_SERIES_SUPPORT */
++
++type1_end:
++			if (DBG_RX_PHYSTATUS_CHINFO) {
++				RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, rf_mode:%u, l_rxsc:%u, ht_rxsc:%u) => %u,%u\n"
++					, *phys & 0xf
++					, MAC_ARG(get_ta(wlanhdr))
++					, is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
++					, HDATA_RATE(attrib->data_rate)
++					, phys_t1->band, phys_t1->channel, phys_t1->rf_mode, phys_t1->l_rxsc, phys_t1->ht_rxsc
++					, pkt_cch, pkt_bw
++				);
++			}
++
++			/* for now, only return cneter channel of 20MHz packet */
++			if (pkt_cch && pkt_bw == CHANNEL_WIDTH_20)
++				attrib->ch = pkt_cch;
++
++		} else {
++			struct phy_sts_rpt_jgr2_type2 *phys_t2 = (struct phy_sts_rpt_jgr2_type2 *)phys;
++
++			if (DBG_RX_PHYSTATUS_CHINFO) {
++				RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u, ht_rxsc:%u)\n"
++					, *phys & 0xf
++					, MAC_ARG(get_ta(wlanhdr))
++					, is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
++					, HDATA_RATE(attrib->data_rate)
++					, phys_t2->band, phys_t2->channel, phys_t2->l_rxsc, phys_t2->ht_rxsc
++				);
++			}
++		}
++	}
++#endif /* (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) */
++
++}
++
++#if defined(CONFIG_RTL8822C) && defined(CONFIG_LPS_PG)
++void
++debug_DACK(
++	struct dm_struct *dm
++)
++{
++	//P_PHYDM_FUNC dm;
++	//dm = &(SysMib.ODM.Phydm);
++	//PIQK_OFFLOAD_PARM pIQK_info;
++	//pIQK_info= &(SysMib.ODM.IQKParm);
++	u8 i;
++	u32 temp1, temp2, temp3;
++
++	temp1 = odm_get_bb_reg(dm, 0x1860, bMaskDWord);
++	temp2 = odm_get_bb_reg(dm, 0x4160, bMaskDWord);
++	temp3 = odm_get_bb_reg(dm, 0x9b4, bMaskDWord);
++
++	odm_set_bb_reg(dm, 0x9b4, bMaskDWord, 0xdb66db00);
++
++	//pathA
++	odm_set_bb_reg(dm, 0x1830, BIT(30), 0x0);
++	odm_set_bb_reg(dm, 0x1860, 0xfc000000, 0x3c);
++
++	RTW_INFO("path A i\n");
++	//i
++	for (i = 0; i < 0xf; i++) {
++		odm_set_bb_reg(dm, 0x18b0, 0xf0000000, i);
++		RTW_INFO("[0][0][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000));
++		//pIQK_info->msbk_d[0][0][i] = (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000);
++	}
++	RTW_INFO("path A q\n");
++	//q
++	for (i = 0; i < 0xf; i++) {
++		odm_set_bb_reg(dm, 0x18cc, 0xf0000000, i);
++		RTW_INFO("[0][1][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000));
++		//pIQK_info->msbk_d[0][1][i] = (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000);
++	}
++	//pathB
++	odm_set_bb_reg(dm, 0x4130, BIT(30), 0x0);
++	odm_set_bb_reg(dm, 0x4160, 0xfc000000, 0x3c);
++
++	RTW_INFO("\npath B i\n");
++	//i
++	for (i = 0; i < 0xf; i++) {
++		odm_set_bb_reg(dm, 0x41b0, 0xf0000000, i);
++		RTW_INFO("[1][0][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x4510,0x7fc0000));
++		//pIQK_info->msbk_d[1][0][i] = (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000);
++	}
++	RTW_INFO("path B q\n");
++	//q
++	for (i = 0; i < 0xf; i++) {
++		odm_set_bb_reg(dm, 0x41cc, 0xf0000000, i);
++		RTW_INFO("[1][1][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x453c,0x7fc0000));
++		//pIQK_info->msbk_d[1][1][i] = (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000);
++	}
++
++	//restore to normal
++	odm_set_bb_reg(dm, 0x1830, BIT(30), 0x1);
++	odm_set_bb_reg(dm, 0x4130, BIT(30), 0x1);
++	odm_set_bb_reg(dm, 0x1860, bMaskDWord, temp1);
++	odm_set_bb_reg(dm, 0x4160, bMaskDWord, temp2);
++	odm_set_bb_reg(dm, 0x9b4, bMaskDWord, temp3);
++
++
++}
++
++void
++debug_IQK(
++	struct dm_struct *dm,
++	IN	u8 idx,
++	IN	u8 path
++)
++{
++	u8 i, ch;
++	u32 tmp;
++	u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
++
++	RTW_INFO("idx = %d, path = %d\n", idx, path);
++
++	odm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0x8 | path << 1);
++
++	if (idx == TX_IQK) {//TXCFIR
++		odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x3);
++	} else {//RXCFIR
++		odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);		
++	}
++	odm_set_bb_reg(dm, R_0x1bd4, BIT(21), 0x1);
++	odm_set_bb_reg(dm, R_0x1bd4, bit_mask_20_16, 0x10);
++	for (i = 0; i <= 16; i++) {
++		odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001 | i << 2);
++		tmp = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
++		RTW_INFO("iqk_cfir_real[%d][%d][%d] = 0x%x\n", path, idx, i, ((tmp & 0x0fff0000) >> 16));
++		//iqk_info->iqk_cfir_real[ch][path][idx][i] =
++		//				(tmp & 0x0fff0000) >> 16;
++		RTW_INFO("iqk_cfir_imag[%d][%d][%d] = 0x%x\n", path, idx, i, (tmp & 0x0fff));
++		//iqk_info->iqk_cfir_imag[ch][path][idx][i] = tmp & 0x0fff;		
++	}
++	odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);
++	//odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
++}
++
++__odm_func__ void
++debug_information_8822c(
++	struct dm_struct *dm)
++{
++	struct dm_dpk_info *dpk_info = &dm->dpk_info;
++
++	u32  reg_rf18;
++
++	if (odm_get_bb_reg(dm, R_0x1e7c, BIT(30)))
++		dpk_info->is_tssi_mode = true;
++	else
++		dpk_info->is_tssi_mode = false;
++
++	reg_rf18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK);
++
++	dpk_info->dpk_band = (u8)((reg_rf18 & BIT(16)) >> 16); /*0/1:G/A*/
++	dpk_info->dpk_ch = (u8)reg_rf18 & 0xff;
++	dpk_info->dpk_bw = (u8)((reg_rf18 & 0x3000) >> 12); /*3/2/1:20/40/80*/
++
++	RTW_INFO("[DPK] TSSI/ Band/ CH/ BW = %d / %s / %d / %s\n",
++	       dpk_info->is_tssi_mode, dpk_info->dpk_band == 0 ? "2G" : "5G",
++	       dpk_info->dpk_ch,
++	       dpk_info->dpk_bw == 3 ? "20M" : (dpk_info->dpk_bw == 2 ? "40M" : "80M"));
++}
++
++extern void _dpk_get_coef_8822c(void *dm_void, u8 path);
++
++__odm_func__ void
++debug_reload_data_8822c(
++	void *dm_void)
++{	
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_dpk_info *dpk_info = &dm->dpk_info;
++
++	u8 path;
++	u32 u32tmp;
++
++	debug_information_8822c(dm);
++
++	for (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {
++
++		RTW_INFO("[DPK] Reload path: 0x%x\n", path);
++
++		odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | (path << 1));
++
++		 /*txagc bnd*/
++		if (dpk_info->dpk_band == 0x0)
++			u32tmp = odm_get_bb_reg(dm, R_0x1b60, MASKDWORD);
++		else
++			u32tmp = odm_get_bb_reg(dm, R_0x1b60, MASKDWORD);
++
++ 		RTW_INFO("[DPK] txagc bnd = 0x%08x\n", u32tmp);
++
++		u32tmp = odm_get_bb_reg(dm, R_0x1b64, MASKBYTE3);
++		RTW_INFO("[DPK] dpk_txagc = 0x%08x\n", u32tmp);
++		
++		//debug_coef_write_8822c(dm, path, dpk_info->dpk_path_ok & BIT(path) >> path);
++		_dpk_get_coef_8822c(dm, path);
++
++		//debug_one_shot_8822c(dm, path, DPK_ON);
++
++		odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc);
++
++		if (path == RF_PATH_A)
++			u32tmp = odm_get_bb_reg(dm, R_0x1b04, 0x0fffffff);
++		else 
++			u32tmp = odm_get_bb_reg(dm, R_0x1b5c, 0x0fffffff);
++
++		RTW_INFO("[DPK] dpk_gs = 0x%08x\n", u32tmp);
++		
++	}
++}
++
++void odm_lps_pg_debug_8822c(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	debug_DACK(dm);
++	debug_IQK(dm, TX_IQK, RF_PATH_A);
++	debug_IQK(dm, RX_IQK, RF_PATH_A);
++	debug_IQK(dm, TX_IQK, RF_PATH_B);
++	debug_IQK(dm, RX_IQK, RF_PATH_B);	
++	debug_reload_data_8822c(dm);
++}
++#endif /* defined(CONFIG_RTL8822C) && defined(CONFIG_LPS_PG) */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_p2p.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_p2p.c
+new file mode 100644
+index 000000000..0f7d0819b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_p2p.c
+@@ -0,0 +1,5437 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_P2P_C_
++
++#include <drv_types.h>
++
++#ifdef CONFIG_P2P
++
++int rtw_p2p_is_channel_list_ok(u8 desired_ch, u8 *ch_list, u8 ch_cnt)
++{
++	int found = 0, i = 0;
++
++	for (i = 0; i < ch_cnt; i++) {
++		if (ch_list[i] == desired_ch) {
++			found = 1;
++			break;
++		}
++	}
++	return found ;
++}
++
++int is_any_client_associated(_adapter *padapter)
++{
++	return padapter->stapriv.asoc_list_cnt ? _TRUE : _FALSE;
++}
++
++static u32 go_add_group_info_attr(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++	_irqL irqL;
++	_list	*phead, *plist;
++	u32 len = 0;
++	u16 attr_len = 0;
++	u8 tmplen, *pdata_attr, *pstart, *pcur;
++	struct sta_info *psta = NULL;
++	_adapter *padapter = pwdinfo->padapter;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++	pdata_attr = rtw_zmalloc(MAX_P2P_IE_LEN);
++
++	if (NULL == pdata_attr) {
++		RTW_INFO("%s pdata_attr malloc failed\n", __FUNCTION__);
++		goto _exit;
++	}
++
++	pstart = pdata_attr;
++	pcur = pdata_attr;
++
++	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++	phead = &pstapriv->asoc_list;
++	plist = get_next(phead);
++
++	/* look up sta asoc_queue */
++	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++
++		plist = get_next(plist);
++
++
++		if (psta->is_p2p_device) {
++			tmplen = 0;
++
++			pcur++;
++
++			/* P2P device address */
++			_rtw_memcpy(pcur, psta->dev_addr, ETH_ALEN);
++			pcur += ETH_ALEN;
++
++			/* P2P interface address */
++			_rtw_memcpy(pcur, psta->cmn.mac_addr, ETH_ALEN);
++			pcur += ETH_ALEN;
++
++			*pcur = psta->dev_cap;
++			pcur++;
++
++			/* *(u16*)(pcur) = cpu_to_be16(psta->config_methods); */
++			RTW_PUT_BE16(pcur, psta->config_methods);
++			pcur += 2;
++
++			_rtw_memcpy(pcur, psta->primary_dev_type, 8);
++			pcur += 8;
++
++			*pcur = psta->num_of_secdev_type;
++			pcur++;
++
++			_rtw_memcpy(pcur, psta->secdev_types_list, psta->num_of_secdev_type * 8);
++			pcur += psta->num_of_secdev_type * 8;
++
++			if (psta->dev_name_len > 0) {
++				/* *(u16*)(pcur) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */
++				RTW_PUT_BE16(pcur, WPS_ATTR_DEVICE_NAME);
++				pcur += 2;
++
++				/* *(u16*)(pcur) = cpu_to_be16( psta->dev_name_len ); */
++				RTW_PUT_BE16(pcur, psta->dev_name_len);
++				pcur += 2;
++
++				_rtw_memcpy(pcur, psta->dev_name, psta->dev_name_len);
++				pcur += psta->dev_name_len;
++			}
++
++
++			tmplen = (u8)(pcur - pstart);
++
++			*pstart = (tmplen - 1);
++
++			attr_len += tmplen;
++
++			/* pstart += tmplen; */
++			pstart = pcur;
++
++		}
++
++
++	}
++	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++	if (attr_len > 0)
++		len = rtw_set_p2p_attr_content(pbuf, P2P_ATTR_GROUP_INFO, attr_len, pdata_attr);
++
++	rtw_mfree(pdata_attr, MAX_P2P_IE_LEN);
++
++_exit:
++	return len;
++
++}
++
++static void issue_group_disc_req(struct wifidirect_info *pwdinfo, u8 *da)
++{
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	_adapter *padapter = pwdinfo->padapter;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	unsigned char category = RTW_WLAN_CATEGORY_P2P;/* P2P action frame	 */
++	u32	p2poui = cpu_to_be32(P2POUI);
++	u8	oui_subtype = P2P_GO_DISC_REQUEST;
++	u8	dialogToken = 0;
++
++	RTW_INFO("[%s]\n", __FUNCTION__);
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	/* Build P2P action frame header */
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
++
++	/* there is no IE in this P2P action frame */
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(padapter, pmgntframe);
++
++}
++
++static void issue_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken)
++{
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	_adapter *padapter = pwdinfo->padapter;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++	u8			action = P2P_PUB_ACTION_ACTION;
++	u32			p2poui = cpu_to_be32(P2POUI);
++	u8			oui_subtype = P2P_DEVDISC_RESP;
++	u8 p2pie[8] = { 0x00 };
++	u32 p2pielen = 0;
++
++	RTW_INFO("[%s]\n", __FUNCTION__);
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, pwdinfo->device_addr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, pwdinfo->device_addr, ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	/* Build P2P public action frame header */
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
++
++
++	/* Build P2P IE */
++	/*	P2P OUI */
++	p2pielen = 0;
++	p2pie[p2pielen++] = 0x50;
++	p2pie[p2pielen++] = 0x6F;
++	p2pie[p2pielen++] = 0x9A;
++	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
++
++	/* P2P_ATTR_STATUS */
++	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status);
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &pattrib->pktlen);
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(padapter, pmgntframe);
++
++}
++
++static void issue_p2p_provision_resp(struct wifidirect_info *pwdinfo, u8 *raddr, u8 *frame_body, u16 config_method)
++{
++	_adapter *padapter = pwdinfo->padapter;
++	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++	u8			action = P2P_PUB_ACTION_ACTION;
++	u8			dialogToken = frame_body[7];	/*	The Dialog Token of provisioning discovery request frame. */
++	u32			p2poui = cpu_to_be32(P2POUI);
++	u8			oui_subtype = P2P_PROVISION_DISC_RESP;
++	u8			wpsie[100] = { 0x00 };
++	u8			wpsielen = 0;
++#ifdef CONFIG_WFD
++	u32					wfdielen = 0;
++#endif
++
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
++
++	wpsielen = 0;
++	/*	WPS OUI */
++	/* *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); */
++	RTW_PUT_BE32(wpsie, WPSOUI);
++	wpsielen += 4;
++
++#if 0
++	/*	WPS version */
++	/*	Type: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
++	wpsielen += 2;
++
++	/*	Length: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
++	wpsielen += 2;
++
++	/*	Value: */
++	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
++#endif
++
++	/*	Config Method */
++	/*	Type: */
++	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); */
++	RTW_PUT_BE16(wpsie + wpsielen, WPS_ATTR_CONF_METHOD);
++	wpsielen += 2;
++
++	/*	Length: */
++	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); */
++	RTW_PUT_BE16(wpsie + wpsielen, 0x0002);
++	wpsielen += 2;
++
++	/*	Value: */
++	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( config_method ); */
++	RTW_PUT_BE16(wpsie + wpsielen, config_method);
++	wpsielen += 2;
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
++
++#ifdef CONFIG_WFD
++	wfdielen = build_provdisc_resp_wfd_ie(pwdinfo, pframe);
++	pframe += wfdielen;
++	pattrib->pktlen += wfdielen;
++#endif
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(padapter, pmgntframe);
++
++	return;
++
++}
++
++static void issue_p2p_presence_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken)
++{
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	_adapter *padapter = pwdinfo->padapter;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	unsigned char category = RTW_WLAN_CATEGORY_P2P;/* P2P action frame	 */
++	u32	p2poui = cpu_to_be32(P2POUI);
++	u8	oui_subtype = P2P_PRESENCE_RESPONSE;
++	u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };
++	u8 noa_attr_content[32] = { 0x00 };
++	u32 p2pielen = 0;
++
++	RTW_INFO("[%s]\n", __FUNCTION__);
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	/* Build P2P action frame header */
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
++
++
++	/* Add P2P IE header */
++	/*	P2P OUI */
++	p2pielen = 0;
++	p2pie[p2pielen++] = 0x50;
++	p2pie[p2pielen++] = 0x6F;
++	p2pie[p2pielen++] = 0x9A;
++	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
++
++	/* Add Status attribute in P2P IE */
++	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status);
++
++	/* Add NoA attribute in P2P IE */
++	noa_attr_content[0] = 0x1;/* index */
++	noa_attr_content[1] = 0x0;/* CTWindow and OppPS Parameters */
++
++	/* todo: Notice of Absence Descriptor(s) */
++
++	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_NOA, 2, noa_attr_content);
++
++
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &(pattrib->pktlen));
++
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(padapter, pmgntframe);
++
++}
++
++u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++	u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };
++	u16 capability = 0;
++	u32 len = 0, p2pielen = 0;
++
++
++	/*	P2P OUI */
++	p2pielen = 0;
++	p2pie[p2pielen++] = 0x50;
++	p2pie[p2pielen++] = 0x6F;
++	p2pie[p2pielen++] = 0x9A;
++	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
++
++
++	/*	According to the P2P Specification, the beacon frame should contain 3 P2P attributes */
++	/*	1. P2P Capability */
++	/*	2. P2P Device ID */
++	/*	3. Notice of Absence ( NOA )	 */
++
++	/*	P2P Capability ATTR */
++	/*	Type: */
++	/*	Length: */
++	/*	Value: */
++	/*	Device Capability Bitmap, 1 byte */
++	/*	Be able to participate in additional P2P Groups and */
++	/*	support the P2P Invitation Procedure	 */
++	/*	Group Capability Bitmap, 1 byte	 */
++	capability = P2P_DEVCAP_INVITATION_PROC | P2P_DEVCAP_CLIENT_DISCOVERABILITY;
++	capability |= ((P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS) << 8);
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))
++		capability |= (P2P_GRPCAP_GROUP_FORMATION << 8);
++
++	capability = cpu_to_le16(capability);
++
++	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_CAPABILITY, 2, (u8 *)&capability);
++
++
++	/* P2P Device ID ATTR */
++	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_DEVICE_ID, ETH_ALEN, pwdinfo->device_addr);
++
++
++	/* Notice of Absence ATTR */
++	/*	Type:  */
++	/*	Length: */
++	/*	Value: */
++
++	/* go_add_noa_attr(pwdinfo); */
++
++
++	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);
++
++
++	return len;
++
++}
++
++#ifdef CONFIG_WFD
++u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
++	u16 val16 = 0;
++	u32 len = 0, wfdielen = 0;
++	_adapter *padapter = pwdinfo->padapter;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
++
++	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
++		goto exit;
++
++	/*	WFD OUI */
++	wfdielen = 0;
++	wfdie[wfdielen++] = 0x50;
++	wfdie[wfdielen++] = 0x6F;
++	wfdie[wfdielen++] = 0x9A;
++	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
++
++	/*	Commented by Albert 20110812 */
++	/*	According to the WFD Specification, the beacon frame should contain 4 WFD attributes */
++	/*	1. WFD Device Information */
++	/*	2. Associated BSSID */
++	/*	3. Coupled Sink Information */
++
++
++	/*	WFD Device Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value1: */
++	/*	WFD device information */
++
++	if (P2P_ROLE_GO == pwdinfo->role) {
++		if (is_any_client_associated(pwdinfo->padapter)) {
++			/*	WFD primary sink + WiFi Direct mode + WSD (WFD Service Discovery) */
++			val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD;
++			RTW_PUT_BE16(wfdie + wfdielen, val16);
++		} else {
++			/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD (WFD Service Discovery) */
++			val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
++			RTW_PUT_BE16(wfdie + wfdielen, val16);
++		}
++
++	} else {
++		/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
++		val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
++		RTW_PUT_BE16(wfdie + wfdielen, val16);
++	}
++
++	wfdielen += 2;
++
++	/*	Value2: */
++	/*	Session Management Control Port */
++	/*	Default TCP port for RTSP messages is 554 */
++	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
++	wfdielen += 2;
++
++	/*	Value3: */
++	/*	WFD Device Maximum Throughput */
++	/*	300Mbps is the maximum throughput */
++	RTW_PUT_BE16(wfdie + wfdielen, 300);
++	wfdielen += 2;
++
++	/*	Associated BSSID ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Associated BSSID */
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
++	else
++		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
++
++	wfdielen += ETH_ALEN;
++
++	/*	Coupled Sink Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Coupled Sink Status bitmap */
++	/*	Not coupled/available for Coupling */
++	wfdie[wfdielen++] = 0;
++	/* MAC Addr. */
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++
++	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++exit:
++	return len;
++}
++
++u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
++	u16 val16 = 0;
++	u32 len = 0, wfdielen = 0;
++	_adapter *padapter = pwdinfo->padapter;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
++
++	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
++		goto exit;
++
++	/*	WFD OUI */
++	wfdielen = 0;
++	wfdie[wfdielen++] = 0x50;
++	wfdie[wfdielen++] = 0x6F;
++	wfdie[wfdielen++] = 0x9A;
++	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
++
++	/*	Commented by Albert 20110812 */
++	/*	According to the WFD Specification, the probe request frame should contain 4 WFD attributes */
++	/*	1. WFD Device Information */
++	/*	2. Associated BSSID */
++	/*	3. Coupled Sink Information */
++
++
++	/*	WFD Device Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value1: */
++	/*	WFD device information */
++
++	if (1 == pwdinfo->wfd_tdls_enable) {
++		/*	WFD primary sink + available for WFD session + WiFi TDLS mode + WSC ( WFD Service Discovery )	 */
++		val16 = pwfd_info->wfd_device_type |
++			WFD_DEVINFO_SESSION_AVAIL |
++			WFD_DEVINFO_WSD |
++			WFD_DEVINFO_PC_TDLS;
++		RTW_PUT_BE16(wfdie + wfdielen, val16);
++	} else {
++		/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSC ( WFD Service Discovery )	 */
++		val16 = pwfd_info->wfd_device_type |
++			WFD_DEVINFO_SESSION_AVAIL |
++			WFD_DEVINFO_WSD;
++		RTW_PUT_BE16(wfdie + wfdielen, val16);
++	}
++
++	wfdielen += 2;
++
++	/*	Value2: */
++	/*	Session Management Control Port */
++	/*	Default TCP port for RTSP messages is 554 */
++	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
++	wfdielen += 2;
++
++	/*	Value3: */
++	/*	WFD Device Maximum Throughput */
++	/*	300Mbps is the maximum throughput */
++	RTW_PUT_BE16(wfdie + wfdielen, 300);
++	wfdielen += 2;
++
++	/*	Associated BSSID ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Associated BSSID */
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
++	else
++		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
++
++	wfdielen += ETH_ALEN;
++
++	/*	Coupled Sink Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Coupled Sink Status bitmap */
++	/*	Not coupled/available for Coupling */
++	wfdie[wfdielen++] = 0;
++	/* MAC Addr. */
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++
++	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++exit:
++	return len;
++}
++
++u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled)
++{
++	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
++	u32 len = 0, wfdielen = 0;
++	_adapter *padapter = pwdinfo->padapter;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
++	u16 v16 = 0;
++
++	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
++		goto exit;
++
++	/*	WFD OUI */
++	wfdielen = 0;
++	wfdie[wfdielen++] = 0x50;
++	wfdie[wfdielen++] = 0x6F;
++	wfdie[wfdielen++] = 0x9A;
++	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
++
++	/*	Commented by Albert 20110812 */
++	/*	According to the WFD Specification, the probe response frame should contain 4 WFD attributes */
++	/*	1. WFD Device Information */
++	/*	2. Associated BSSID */
++	/*	3. Coupled Sink Information */
++	/*	4. WFD Session Information */
++
++
++	/*	WFD Device Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value1: */
++	/*	WFD device information */
++	/*	WFD primary sink + available for WFD session + WiFi Direct mode */
++
++	if (_TRUE == pwdinfo->session_available) {
++		if (P2P_ROLE_GO == pwdinfo->role) {
++			if (is_any_client_associated(pwdinfo->padapter)) {
++				if (pwdinfo->wfd_tdls_enable) {
++					/*	TDLS mode + WSD ( WFD Service Discovery ) */
++					v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;
++					RTW_PUT_BE16(wfdie + wfdielen, v16);
++				} else {
++					/*	WiFi Direct mode + WSD ( WFD Service Discovery ) */
++					v16 =  pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;
++					RTW_PUT_BE16(wfdie + wfdielen, v16);
++				}
++			} else {
++				if (pwdinfo->wfd_tdls_enable) {
++					/*	available for WFD session + TDLS mode + WSD ( WFD Service Discovery ) */
++					v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;
++					RTW_PUT_BE16(wfdie + wfdielen, v16);
++				} else {
++					/*	available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
++					v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;
++					RTW_PUT_BE16(wfdie + wfdielen, v16);
++				}
++			}
++		} else {
++			if (pwdinfo->wfd_tdls_enable) {
++				/*	available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
++				v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;
++				RTW_PUT_BE16(wfdie + wfdielen, v16);
++			} else {
++				/*	available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
++				v16 =  pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;
++				RTW_PUT_BE16(wfdie + wfdielen, v16);
++			}
++		}
++	} else {
++		if (pwdinfo->wfd_tdls_enable) {
++			v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;
++			RTW_PUT_BE16(wfdie + wfdielen, v16);
++		} else {
++			v16 =  pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;
++			RTW_PUT_BE16(wfdie + wfdielen, v16);
++		}
++	}
++
++	wfdielen += 2;
++
++	/*	Value2: */
++	/*	Session Management Control Port */
++	/*	Default TCP port for RTSP messages is 554 */
++	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
++	wfdielen += 2;
++
++	/*	Value3: */
++	/*	WFD Device Maximum Throughput */
++	/*	300Mbps is the maximum throughput */
++	RTW_PUT_BE16(wfdie + wfdielen, 300);
++	wfdielen += 2;
++
++	/*	Associated BSSID ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Associated BSSID */
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
++	else
++		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
++
++	wfdielen += ETH_ALEN;
++
++	/*	Coupled Sink Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Coupled Sink Status bitmap */
++	/*	Not coupled/available for Coupling */
++	wfdie[wfdielen++] = 0;
++	/* MAC Addr. */
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++		/*	WFD Session Information ATTR */
++		/*	Type: */
++		wfdie[wfdielen++] = WFD_ATTR_SESSION_INFO;
++
++		/*	Length: */
++		/*	Note: In the WFD specification, the size of length field is 2. */
++		RTW_PUT_BE16(wfdie + wfdielen, 0x0000);
++		wfdielen += 2;
++
++		/*	Todo: to add the list of WFD device info descriptor in WFD group. */
++
++	}
++#ifdef CONFIG_CONCURRENT_MODE
++#ifdef CONFIG_TDLS
++	{
++		int i;
++		_adapter *iface = NULL;
++		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			iface = dvobj->padapters[i];
++			if ((iface) && rtw_is_adapter_up(iface)) {
++				if (iface == padapter)
++					continue;
++
++				if ((tunneled == 0) && (iface->wdinfo.wfd_tdls_enable == 1)) {
++					/*	Alternative MAC Address ATTR
++						Type:					*/
++					wfdie[wfdielen++] = WFD_ATTR_ALTER_MAC;
++
++					/*	Length:
++						Note: In the WFD specification, the size of length field is 2.*/
++					RTW_PUT_BE16(wfdie + wfdielen,  ETH_ALEN);
++					wfdielen += 2;
++
++					/*	Value:
++						Alternative MAC Address*/
++					_rtw_memcpy(wfdie + wfdielen, adapter_mac_addr(iface), ETH_ALEN);
++					wfdielen += ETH_ALEN;
++				}
++			}
++		}
++	}
++
++#endif /* CONFIG_TDLS*/
++#endif /* CONFIG_CONCURRENT_MODE */
++
++	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++exit:
++	return len;
++}
++
++u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
++	u16 val16 = 0;
++	u32 len = 0, wfdielen = 0;
++	_adapter					*padapter = NULL;
++	struct mlme_priv			*pmlmepriv = NULL;
++	struct wifi_display_info		*pwfd_info = NULL;
++
++	padapter = pwdinfo->padapter;
++	pmlmepriv = &padapter->mlmepriv;
++	pwfd_info = padapter->wdinfo.wfd_info;
++
++	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
++		goto exit;
++
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE))
++		goto exit;
++
++	/* WFD OUI */
++	wfdielen = 0;
++	wfdie[wfdielen++] = 0x50;
++	wfdie[wfdielen++] = 0x6F;
++	wfdie[wfdielen++] = 0x9A;
++	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
++
++	/*	Commented by Albert 20110812 */
++	/*	According to the WFD Specification, the probe request frame should contain 4 WFD attributes */
++	/*	1. WFD Device Information */
++	/*	2. Associated BSSID */
++	/*	3. Coupled Sink Information */
++
++
++	/*	WFD Device Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value1: */
++	/*	WFD device information */
++	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
++	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
++	RTW_PUT_BE16(wfdie + wfdielen, val16);
++	wfdielen += 2;
++
++	/*	Value2: */
++	/*	Session Management Control Port */
++	/*	Default TCP port for RTSP messages is 554 */
++	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
++	wfdielen += 2;
++
++	/*	Value3: */
++	/*	WFD Device Maximum Throughput */
++	/*	300Mbps is the maximum throughput */
++	RTW_PUT_BE16(wfdie + wfdielen, 300);
++	wfdielen += 2;
++
++	/*	Associated BSSID ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Associated BSSID */
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
++	else
++		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
++
++	wfdielen += ETH_ALEN;
++
++	/*	Coupled Sink Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Coupled Sink Status bitmap */
++	/*	Not coupled/available for Coupling */
++	wfdie[wfdielen++] = 0;
++	/* MAC Addr. */
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++
++	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++exit:
++	return len;
++}
++
++u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
++	u32 len = 0, wfdielen = 0;
++	u16 val16 = 0;
++	_adapter *padapter = pwdinfo->padapter;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
++
++	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
++		goto exit;
++
++	/*	WFD OUI */
++	wfdielen = 0;
++	wfdie[wfdielen++] = 0x50;
++	wfdie[wfdielen++] = 0x6F;
++	wfdie[wfdielen++] = 0x9A;
++	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
++
++	/*	Commented by Albert 20110812 */
++	/*	According to the WFD Specification, the probe request frame should contain 4 WFD attributes */
++	/*	1. WFD Device Information */
++	/*	2. Associated BSSID */
++	/*	3. Coupled Sink Information */
++
++
++	/*	WFD Device Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value1: */
++	/*	WFD device information */
++	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
++	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
++	RTW_PUT_BE16(wfdie + wfdielen, val16);
++	wfdielen += 2;
++
++	/*	Value2: */
++	/*	Session Management Control Port */
++	/*	Default TCP port for RTSP messages is 554 */
++	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
++	wfdielen += 2;
++
++	/*	Value3: */
++	/*	WFD Device Maximum Throughput */
++	/*	300Mbps is the maximum throughput */
++	RTW_PUT_BE16(wfdie + wfdielen, 300);
++	wfdielen += 2;
++
++	/*	Associated BSSID ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Associated BSSID */
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
++	else
++		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
++
++	wfdielen += ETH_ALEN;
++
++	/*	Coupled Sink Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Coupled Sink Status bitmap */
++	/*	Not coupled/available for Coupling */
++	wfdie[wfdielen++] = 0;
++	/* MAC Addr. */
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++
++	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++exit:
++	return len;
++}
++
++u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
++	u32 len = 0, wfdielen = 0;
++	u16 val16 = 0;
++	_adapter *padapter = pwdinfo->padapter;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
++
++	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
++		goto exit;
++
++	/*	WFD OUI */
++	wfdielen = 0;
++	wfdie[wfdielen++] = 0x50;
++	wfdie[wfdielen++] = 0x6F;
++	wfdie[wfdielen++] = 0x9A;
++	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
++
++	/*	Commented by Albert 20110825 */
++	/*	According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes */
++	/*	1. WFD Device Information */
++	/*	2. Associated BSSID ( Optional ) */
++	/*	3. Local IP Adress ( Optional ) */
++
++
++	/*	WFD Device Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value1: */
++	/*	WFD device information */
++	/*	WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available */
++	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL;
++	RTW_PUT_BE16(wfdie + wfdielen, val16);
++	wfdielen += 2;
++
++	/*	Value2: */
++	/*	Session Management Control Port */
++	/*	Default TCP port for RTSP messages is 554 */
++	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
++	wfdielen += 2;
++
++	/*	Value3: */
++	/*	WFD Device Maximum Throughput */
++	/*	300Mbps is the maximum throughput */
++	RTW_PUT_BE16(wfdie + wfdielen, 300);
++	wfdielen += 2;
++
++	/*	Associated BSSID ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Associated BSSID */
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
++	else
++		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
++
++	wfdielen += ETH_ALEN;
++
++	/*	Coupled Sink Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Coupled Sink Status bitmap */
++	/*	Not coupled/available for Coupling */
++	wfdie[wfdielen++] = 0;
++	/* MAC Addr. */
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++
++	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++exit:
++	return len;
++}
++
++u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
++	u32 len = 0, wfdielen = 0;
++	u16 val16 = 0;
++	_adapter *padapter = pwdinfo->padapter;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
++
++	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
++		goto exit;
++
++	/*	WFD OUI */
++	wfdielen = 0;
++	wfdie[wfdielen++] = 0x50;
++	wfdie[wfdielen++] = 0x6F;
++	wfdie[wfdielen++] = 0x9A;
++	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
++
++	/*	Commented by Albert 20110825 */
++	/*	According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes */
++	/*	1. WFD Device Information */
++	/*	2. Associated BSSID ( Optional ) */
++	/*	3. Local IP Adress ( Optional ) */
++
++
++	/*	WFD Device Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value1: */
++	/*	WFD device information */
++	/*	WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available */
++	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL;
++	RTW_PUT_BE16(wfdie + wfdielen, val16);
++	wfdielen += 2;
++
++	/*	Value2: */
++	/*	Session Management Control Port */
++	/*	Default TCP port for RTSP messages is 554 */
++	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
++	wfdielen += 2;
++
++	/*	Value3: */
++	/*	WFD Device Maximum Throughput */
++	/*	300Mbps is the maximum throughput */
++	RTW_PUT_BE16(wfdie + wfdielen, 300);
++	wfdielen += 2;
++
++	/*	Associated BSSID ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Associated BSSID */
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
++	else
++		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
++
++	wfdielen += ETH_ALEN;
++
++	/*	Coupled Sink Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Coupled Sink Status bitmap */
++	/*	Not coupled/available for Coupling */
++	wfdie[wfdielen++] = 0;
++	/* MAC Addr. */
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++
++
++	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++exit:
++	return len;
++}
++
++u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
++	u32 len = 0, wfdielen = 0;
++	u16 val16 = 0;
++	_adapter *padapter = pwdinfo->padapter;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
++
++	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
++		goto exit;
++
++	/*	WFD OUI */
++	wfdielen = 0;
++	wfdie[wfdielen++] = 0x50;
++	wfdie[wfdielen++] = 0x6F;
++	wfdie[wfdielen++] = 0x9A;
++	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
++
++	/*	Commented by Albert 20110825 */
++	/*	According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes */
++	/*	1. WFD Device Information */
++	/*	2. Associated BSSID ( Optional ) */
++	/*	3. Local IP Adress ( Optional ) */
++
++
++	/*	WFD Device Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value1: */
++	/*	WFD device information */
++	/*	WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available */
++	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL;
++	RTW_PUT_BE16(wfdie + wfdielen, val16);
++	wfdielen += 2;
++
++	/*	Value2: */
++	/*	Session Management Control Port */
++	/*	Default TCP port for RTSP messages is 554 */
++	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
++	wfdielen += 2;
++
++	/*	Value3: */
++	/*	WFD Device Maximum Throughput */
++	/*	300Mbps is the maximum throughput */
++	RTW_PUT_BE16(wfdie + wfdielen, 300);
++	wfdielen += 2;
++
++	/*	Associated BSSID ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Associated BSSID */
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
++	else
++		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
++
++	wfdielen += ETH_ALEN;
++
++	/*	Coupled Sink Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Coupled Sink Status bitmap */
++	/*	Not coupled/available for Coupling */
++	wfdie[wfdielen++] = 0;
++	/* MAC Addr. */
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++
++
++	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++exit:
++	return len;
++}
++
++u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
++	u32 len = 0, wfdielen = 0;
++	u16 val16 = 0;
++	_adapter *padapter = pwdinfo->padapter;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
++
++	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
++		goto exit;
++
++	/*	WFD OUI */
++	wfdielen = 0;
++	wfdie[wfdielen++] = 0x50;
++	wfdie[wfdielen++] = 0x6F;
++	wfdie[wfdielen++] = 0x9A;
++	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
++
++	/*	Commented by Albert 20110825 */
++	/*	According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes */
++	/*	1. WFD Device Information */
++	/*	2. Associated BSSID ( Optional ) */
++	/*	3. Local IP Adress ( Optional ) */
++
++
++	/*	WFD Device Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value1: */
++	/*	WFD device information */
++	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
++	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
++	RTW_PUT_BE16(wfdie + wfdielen, val16);
++	wfdielen += 2;
++
++	/*	Value2: */
++	/*	Session Management Control Port */
++	/*	Default TCP port for RTSP messages is 554 */
++	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
++	wfdielen += 2;
++
++	/*	Value3: */
++	/*	WFD Device Maximum Throughput */
++	/*	300Mbps is the maximum throughput */
++	RTW_PUT_BE16(wfdie + wfdielen, 300);
++	wfdielen += 2;
++
++	/*	Associated BSSID ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Associated BSSID */
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
++	else
++		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
++
++	wfdielen += ETH_ALEN;
++
++	/*	Coupled Sink Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Coupled Sink Status bitmap */
++	/*	Not coupled/available for Coupling */
++	wfdie[wfdielen++] = 0;
++	/* MAC Addr. */
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++
++	if (P2P_ROLE_GO == pwdinfo->role) {
++		/*	WFD Session Information ATTR */
++		/*	Type: */
++		wfdie[wfdielen++] = WFD_ATTR_SESSION_INFO;
++
++		/*	Length: */
++		/*	Note: In the WFD specification, the size of length field is 2. */
++		RTW_PUT_BE16(wfdie + wfdielen, 0x0000);
++		wfdielen += 2;
++
++		/*	Todo: to add the list of WFD device info descriptor in WFD group. */
++
++	}
++
++	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++exit:
++	return len;
++}
++
++u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
++	u16 val16 = 0;
++	u32 len = 0, wfdielen = 0;
++	_adapter *padapter = pwdinfo->padapter;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
++
++	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
++		goto exit;
++
++	/*	WFD OUI */
++	wfdielen = 0;
++	wfdie[wfdielen++] = 0x50;
++	wfdie[wfdielen++] = 0x6F;
++	wfdie[wfdielen++] = 0x9A;
++	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
++
++	/*	Commented by Albert 20110825 */
++	/*	According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes */
++	/*	1. WFD Device Information */
++	/*	2. Associated BSSID ( Optional ) */
++	/*	3. Local IP Adress ( Optional ) */
++
++
++	/*	WFD Device Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value1: */
++	/*	WFD device information */
++	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
++	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
++	RTW_PUT_BE16(wfdie + wfdielen, val16);
++	wfdielen += 2;
++
++	/*	Value2: */
++	/*	Session Management Control Port */
++	/*	Default TCP port for RTSP messages is 554 */
++	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
++	wfdielen += 2;
++
++	/*	Value3: */
++	/*	WFD Device Maximum Throughput */
++	/*	300Mbps is the maximum throughput */
++	RTW_PUT_BE16(wfdie + wfdielen, 300);
++	wfdielen += 2;
++
++	/*	Associated BSSID ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Associated BSSID */
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
++	else
++		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
++
++	wfdielen += ETH_ALEN;
++
++	/*	Coupled Sink Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Coupled Sink Status bitmap */
++	/*	Not coupled/available for Coupling */
++	wfdie[wfdielen++] = 0;
++	/* MAC Addr. */
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++
++	if (P2P_ROLE_GO == pwdinfo->role) {
++		/*	WFD Session Information ATTR */
++		/*	Type: */
++		wfdie[wfdielen++] = WFD_ATTR_SESSION_INFO;
++
++		/*	Length: */
++		/*	Note: In the WFD specification, the size of length field is 2. */
++		RTW_PUT_BE16(wfdie + wfdielen, 0x0000);
++		wfdielen += 2;
++
++		/*	Todo: to add the list of WFD device info descriptor in WFD group. */
++
++	}
++
++	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++exit:
++	return len;
++}
++
++u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
++	u32 len = 0, wfdielen = 0;
++	u16 val16 = 0;
++	_adapter *padapter = pwdinfo->padapter;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
++
++	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
++		goto exit;
++
++	/*	WFD OUI */
++	wfdielen = 0;
++	wfdie[wfdielen++] = 0x50;
++	wfdie[wfdielen++] = 0x6F;
++	wfdie[wfdielen++] = 0x9A;
++	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
++
++	/*	Commented by Albert 20110825 */
++	/*	According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes */
++	/*	1. WFD Device Information */
++	/*	2. Associated BSSID ( Optional ) */
++	/*	3. Local IP Adress ( Optional ) */
++
++
++	/*	WFD Device Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value1: */
++	/*	WFD device information */
++	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
++	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
++	RTW_PUT_BE16(wfdie + wfdielen, val16);
++	wfdielen += 2;
++
++	/*	Value2: */
++	/*	Session Management Control Port */
++	/*	Default TCP port for RTSP messages is 554 */
++	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
++	wfdielen += 2;
++
++	/*	Value3: */
++	/*	WFD Device Maximum Throughput */
++	/*	300Mbps is the maximum throughput */
++	RTW_PUT_BE16(wfdie + wfdielen, 300);
++	wfdielen += 2;
++
++	/*	Associated BSSID ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Associated BSSID */
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
++	else
++		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
++
++	wfdielen += ETH_ALEN;
++
++	/*	Coupled Sink Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Coupled Sink Status bitmap */
++	/*	Not coupled/available for Coupling */
++	wfdie[wfdielen++] = 0;
++	/* MAC Addr. */
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++
++
++	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++exit:
++	return len;
++}
++
++u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
++	u32 len = 0, wfdielen = 0;
++	u16 val16 = 0;
++	_adapter *padapter = pwdinfo->padapter;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
++
++	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
++		goto exit;
++
++	/*	WFD OUI */
++	wfdielen = 0;
++	wfdie[wfdielen++] = 0x50;
++	wfdie[wfdielen++] = 0x6F;
++	wfdie[wfdielen++] = 0x9A;
++	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
++
++	/*	Commented by Albert 20110825 */
++	/*	According to the WFD Specification, the provision discovery response frame should contain 3 WFD attributes */
++	/*	1. WFD Device Information */
++	/*	2. Associated BSSID ( Optional ) */
++	/*	3. Local IP Adress ( Optional ) */
++
++
++	/*	WFD Device Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value1: */
++	/*	WFD device information */
++	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
++	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
++	RTW_PUT_BE16(wfdie + wfdielen, val16);
++	wfdielen += 2;
++
++	/*	Value2: */
++	/*	Session Management Control Port */
++	/*	Default TCP port for RTSP messages is 554 */
++	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
++	wfdielen += 2;
++
++	/*	Value3: */
++	/*	WFD Device Maximum Throughput */
++	/*	300Mbps is the maximum throughput */
++	RTW_PUT_BE16(wfdie + wfdielen, 300);
++	wfdielen += 2;
++
++	/*	Associated BSSID ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Associated BSSID */
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
++	else
++		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
++
++	wfdielen += ETH_ALEN;
++
++	/*	Coupled Sink Information ATTR */
++	/*	Type: */
++	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
++
++	/*	Length: */
++	/*	Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
++	wfdielen += 2;
++
++	/*	Value: */
++	/*	Coupled Sink Status bitmap */
++	/*	Not coupled/available for Coupling */
++	wfdie[wfdielen++] = 0;
++	/* MAC Addr. */
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++	wfdie[wfdielen++] = 0;
++
++	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
++
++exit:
++	return len;
++}
++#endif /* CONFIG_WFD */
++
++u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++	u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };
++	u32 len = 0, p2pielen = 0;
++
++	/*	P2P OUI */
++	p2pielen = 0;
++	p2pie[p2pielen++] = 0x50;
++	p2pie[p2pielen++] = 0x6F;
++	p2pie[p2pielen++] = 0x9A;
++	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
++
++	/*	Commented by Albert 20100907 */
++	/*	According to the P2P Specification, the probe response frame should contain 5 P2P attributes */
++	/*	1. P2P Capability */
++	/*	2. Extended Listen Timing */
++	/*	3. Notice of Absence ( NOA )	( Only GO needs this ) */
++	/*	4. Device Info */
++	/*	5. Group Info	( Only GO need this ) */
++
++	/*	P2P Capability ATTR */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
++
++	/*	Length: */
++	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); */
++	RTW_PUT_LE16(p2pie + p2pielen, 0x0002);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Device Capability Bitmap, 1 byte */
++	p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
++
++	/*	Group Capability Bitmap, 1 byte */
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++		p2pie[p2pielen] = (P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS);
++
++		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))
++			p2pie[p2pielen] |= P2P_GRPCAP_GROUP_FORMATION;
++
++		p2pielen++;
++	} else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) {
++		/*	Group Capability Bitmap, 1 byte */
++		if (pwdinfo->persistent_supported)
++			p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;
++		else
++			p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT;
++	}
++
++	/*	Extended Listen Timing ATTR */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING;
++
++	/*	Length: */
++	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); */
++	RTW_PUT_LE16(p2pie + p2pielen, 0x0004);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Availability Period */
++	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); */
++	RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF);
++	p2pielen += 2;
++
++	/*	Availability Interval */
++	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); */
++	RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF);
++	p2pielen += 2;
++
++
++	/* Notice of Absence ATTR */
++	/*	Type:  */
++	/*	Length: */
++	/*	Value: */
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++		/* go_add_noa_attr(pwdinfo); */
++	}
++
++	/*	Device Info ATTR */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
++	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
++	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); */
++	RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	P2P Device Address */
++	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN);
++	p2pielen += ETH_ALEN;
++
++	/*	Config Method */
++	/*	This field should be big endian. Noted by P2P specification. */
++	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); */
++	RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->supported_wps_cm);
++	p2pielen += 2;
++
++	{
++		/*	Primary Device Type */
++		/*	Category ID */
++		/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); */
++		RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA);
++		p2pielen += 2;
++
++		/*	OUI */
++		/* *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); */
++		RTW_PUT_BE32(p2pie + p2pielen, WPSOUI);
++		p2pielen += 4;
++
++		/*	Sub Category ID */
++		/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); */
++		RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER);
++		p2pielen += 2;
++	}
++
++	/*	Number of Secondary Device Types */
++	p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
++
++	/*	Device Name */
++	/*	Type: */
++	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */
++	RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME);
++	p2pielen += 2;
++
++	/*	Length: */
++	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); */
++	RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len);
++	p2pielen += 2;
++
++	/*	Value: */
++	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len);
++	p2pielen += pwdinfo->device_name_len;
++
++	/* Group Info ATTR */
++	/*	Type: */
++	/*	Length: */
++	/*	Value: */
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++		p2pielen += go_add_group_info_attr(pwdinfo, p2pie + p2pielen);
++
++
++	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);
++
++
++	return len;
++
++}
++
++u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 *pssid, u8 ussidlen, u8 *pdev_raddr)
++{
++	u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };
++	u32 len = 0, p2pielen = 0;
++
++	/*	P2P OUI */
++	p2pielen = 0;
++	p2pie[p2pielen++] = 0x50;
++	p2pie[p2pielen++] = 0x6F;
++	p2pie[p2pielen++] = 0x9A;
++	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
++
++	/*	Commented by Albert 20110301 */
++	/*	According to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes */
++	/*	1. P2P Capability */
++	/*	2. Device Info */
++	/*	3. Group ID ( When joining an operating P2P Group ) */
++
++	/*	P2P Capability ATTR */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
++
++	/*	Length: */
++	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); */
++	RTW_PUT_LE16(p2pie + p2pielen, 0x0002);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Device Capability Bitmap, 1 byte */
++	p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
++
++	/*	Group Capability Bitmap, 1 byte */
++	if (pwdinfo->persistent_supported)
++		p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;
++	else
++		p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT;
++
++
++	/*	Device Info ATTR */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
++	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
++	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); */
++	RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	P2P Device Address */
++	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN);
++	p2pielen += ETH_ALEN;
++
++	/*	Config Method */
++	/*	This field should be big endian. Noted by P2P specification. */
++	if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC) {
++		/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_PBC ); */
++		RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_PBC);
++	} else {
++		/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY ); */
++		RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_DISPLAY);
++	}
++
++	p2pielen += 2;
++
++	/*	Primary Device Type */
++	/*	Category ID */
++	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); */
++	RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA);
++	p2pielen += 2;
++
++	/*	OUI */
++	/* *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); */
++	RTW_PUT_BE32(p2pie + p2pielen, WPSOUI);
++	p2pielen += 4;
++
++	/*	Sub Category ID */
++	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); */
++	RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER);
++	p2pielen += 2;
++
++	/*	Number of Secondary Device Types */
++	p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
++
++	/*	Device Name */
++	/*	Type: */
++	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */
++	RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME);
++	p2pielen += 2;
++
++	/*	Length: */
++	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); */
++	RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len);
++	p2pielen += 2;
++
++	/*	Value: */
++	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len);
++	p2pielen += pwdinfo->device_name_len;
++
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
++		/*	Added by Albert 2011/05/19 */
++		/*	In this case, the pdev_raddr is the device address of the group owner. */
++
++		/*	P2P Group ID ATTR */
++		/*	Type: */
++		p2pie[p2pielen++] = P2P_ATTR_GROUP_ID;
++
++		/*	Length: */
++		/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + ussidlen ); */
++		RTW_PUT_LE16(p2pie + p2pielen, ETH_ALEN + ussidlen);
++		p2pielen += 2;
++
++		/*	Value: */
++		_rtw_memcpy(p2pie + p2pielen, pdev_raddr, ETH_ALEN);
++		p2pielen += ETH_ALEN;
++
++		_rtw_memcpy(p2pie + p2pielen, pssid, ussidlen);
++		p2pielen += ussidlen;
++
++	}
++
++	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);
++
++
++	return len;
++
++}
++
++
++u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code)
++{
++	u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };
++	u32 len = 0, p2pielen = 0;
++
++	/*	P2P OUI */
++	p2pielen = 0;
++	p2pie[p2pielen++] = 0x50;
++	p2pie[p2pielen++] = 0x6F;
++	p2pie[p2pielen++] = 0x9A;
++	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
++
++	/* According to the P2P Specification, the Association response frame should contain 2 P2P attributes */
++	/*	1. Status */
++	/*	2. Extended Listen Timing (optional) */
++
++
++	/*	Status ATTR */
++	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status_code);
++
++
++	/* Extended Listen Timing ATTR */
++	/*	Type: */
++	/*	Length: */
++	/*	Value: */
++
++
++	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);
++
++	return len;
++
++}
++
++u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
++{
++	u32 len = 0;
++
++	return len;
++}
++
++u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
++{
++	u8 *p;
++	u32 ret = _FALSE;
++	u8 *p2pie;
++	u32	p2pielen = 0;
++	int ssid_len = 0, rate_cnt = 0;
++
++	p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SUPPORTEDRATES_IE_, (int *)&rate_cnt,
++		       len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
++
++	if (rate_cnt <= 4) {
++		int i, g_rate = 0;
++
++		for (i = 0; i < rate_cnt; i++) {
++			if (((*(p + 2 + i) & 0xff) != 0x02) &&
++			    ((*(p + 2 + i) & 0xff) != 0x04) &&
++			    ((*(p + 2 + i) & 0xff) != 0x0B) &&
++			    ((*(p + 2 + i) & 0xff) != 0x16))
++				g_rate = 1;
++		}
++
++		if (g_rate == 0) {
++			/*	There is no OFDM rate included in SupportedRates IE of this probe request frame */
++			/*	The driver should response this probe request. */
++			return ret;
++		}
++	} else {
++		/*	rate_cnt > 4 means the SupportRates IE contains the OFDM rate because the count of CCK rates are 4. */
++		/*	We should proceed the following check for this probe request. */
++	}
++
++	/*	Added comments by Albert 20100906 */
++	/*	There are several items we should check here. */
++	/*	1. This probe request frame must contain the P2P IE. (Done) */
++	/*	2. This probe request frame must contain the wildcard SSID. (Done) */
++	/*	3. Wildcard BSSID. (Todo) */
++	/*	4. Destination Address. ( Done in mgt_dispatcher function ) */
++	/*	5. Requested Device Type in WSC IE. (Todo) */
++	/*	6. Device ID attribute in P2P IE. (Todo) */
++
++	p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ssid_len,
++		       len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
++
++	ssid_len &= 0xff;	/*	Just last 1 byte is valid for ssid len of the probe request */
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++		p2pie = rtw_get_p2p_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_ , len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_ , NULL, &p2pielen);
++		if (p2pie) {
++			if ((p != NULL) && _rtw_memcmp((void *)(p + 2), (void *) pwdinfo->p2p_wildcard_ssid , 7)) {
++				/* todo: */
++				/* Check Requested Device Type attributes in WSC IE. */
++				/* Check Device ID attribute in P2P IE */
++
++				ret = _TRUE;
++			} else if ((p != NULL) && (ssid_len == 0))
++				ret = _TRUE;
++		} else {
++			/* non -p2p device */
++		}
++
++	}
++
++
++	return ret;
++
++}
++
++u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta)
++{
++	u8 status_code = P2P_STATUS_SUCCESS;
++	u8 *pbuf, *pattr_content = NULL;
++	u32 attr_contentlen = 0;
++	u16 cap_attr = 0;
++	unsigned short	frame_type, ie_offset = 0;
++	u8 *ies;
++	u32 ies_len;
++	u8 *p2p_ie;
++	u32	p2p_ielen = 0;
++
++	if (!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
++		return P2P_STATUS_FAIL_REQUEST_UNABLE;
++
++	frame_type = get_frame_sub_type(pframe);
++	if (frame_type == WIFI_ASSOCREQ)
++		ie_offset = _ASOCREQ_IE_OFFSET_;
++	else /* WIFI_REASSOCREQ */
++		ie_offset = _REASOCREQ_IE_OFFSET_;
++
++	ies = pframe + WLAN_HDR_A3_LEN + ie_offset;
++	ies_len = len - WLAN_HDR_A3_LEN - ie_offset;
++
++	p2p_ie = rtw_get_p2p_ie(ies , ies_len , NULL, &p2p_ielen);
++
++	if (!p2p_ie) {
++		RTW_INFO("[%s] P2P IE not Found!!\n", __FUNCTION__);
++		status_code =  P2P_STATUS_FAIL_INVALID_PARAM;
++	} else
++		RTW_INFO("[%s] P2P IE Found!!\n", __FUNCTION__);
++
++	while (p2p_ie) {
++		/* Check P2P Capability ATTR */
++		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *) &attr_contentlen)) {
++			RTW_INFO("[%s] Got P2P Capability Attr!!\n", __FUNCTION__);
++			cap_attr = le16_to_cpu(cap_attr);
++			psta->dev_cap = cap_attr & 0xff;
++		}
++
++		/* Check Extended Listen Timing ATTR */
++
++
++		/* Check P2P Device Info ATTR */
++		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, NULL, (uint *)&attr_contentlen)) {
++			RTW_INFO("[%s] Got P2P DEVICE INFO Attr!!\n", __FUNCTION__);
++			pattr_content = pbuf = rtw_zmalloc(attr_contentlen);
++			if (pattr_content) {
++				u8 num_of_secdev_type;
++				u16 dev_name_len;
++
++
++				rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO , pattr_content, (uint *)&attr_contentlen);
++
++				_rtw_memcpy(psta->dev_addr, 	pattr_content, ETH_ALEN);/* P2P Device Address */
++
++				pattr_content += ETH_ALEN;
++
++				_rtw_memcpy(&psta->config_methods, pattr_content, 2);/* Config Methods */
++				psta->config_methods = be16_to_cpu(psta->config_methods);
++
++				pattr_content += 2;
++
++				_rtw_memcpy(psta->primary_dev_type, pattr_content, 8);
++
++				pattr_content += 8;
++
++				num_of_secdev_type = *pattr_content;
++				pattr_content += 1;
++
++				if (num_of_secdev_type == 0)
++					psta->num_of_secdev_type = 0;
++				else {
++					u32 len;
++
++					psta->num_of_secdev_type = num_of_secdev_type;
++
++					len = (sizeof(psta->secdev_types_list) < (num_of_secdev_type * 8)) ? (sizeof(psta->secdev_types_list)) : (num_of_secdev_type * 8);
++
++					_rtw_memcpy(psta->secdev_types_list, pattr_content, len);
++
++					pattr_content += (num_of_secdev_type * 8);
++				}
++
++
++				/* dev_name_len = attr_contentlen - ETH_ALEN - 2 - 8 - 1 - (num_of_secdev_type*8); */
++				psta->dev_name_len = 0;
++				if (WPS_ATTR_DEVICE_NAME == be16_to_cpu(*(u16 *)pattr_content)) {
++					dev_name_len = be16_to_cpu(*(u16 *)(pattr_content + 2));
++
++					psta->dev_name_len = (sizeof(psta->dev_name) < dev_name_len) ? sizeof(psta->dev_name) : dev_name_len;
++
++					_rtw_memcpy(psta->dev_name, pattr_content + 4, psta->dev_name_len);
++				}
++
++				rtw_mfree(pbuf, attr_contentlen);
++
++			}
++
++		}
++
++		/* Get the next P2P IE */
++		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
++
++	}
++
++	return status_code;
++
++}
++
++u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
++{
++	u8 *frame_body;
++	u8 status, dialogToken;
++	struct sta_info *psta = NULL;
++	_adapter *padapter = pwdinfo->padapter;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	u8 *p2p_ie;
++	u32	p2p_ielen = 0;
++
++	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++
++	dialogToken = frame_body[7];
++	status = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP;
++
++	p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen);
++	if (p2p_ie) {
++		u8 groupid[38] = { 0x00 };
++		u8 dev_addr[ETH_ALEN] = { 0x00 };
++		u32	attr_contentlen = 0;
++
++		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) {
++			if (_rtw_memcmp(pwdinfo->device_addr, groupid, ETH_ALEN) &&
++			    _rtw_memcmp(pwdinfo->p2p_group_ssid, groupid + ETH_ALEN, pwdinfo->p2p_group_ssid_len)) {
++				attr_contentlen = 0;
++				if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_ID, dev_addr, &attr_contentlen)) {
++					_irqL irqL;
++					_list	*phead, *plist;
++
++					_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++					phead = &pstapriv->asoc_list;
++					plist = get_next(phead);
++
++					/* look up sta asoc_queue */
++					while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++						psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++
++						plist = get_next(plist);
++
++						if (psta->is_p2p_device && (psta->dev_cap & P2P_DEVCAP_CLIENT_DISCOVERABILITY) &&
++						    _rtw_memcmp(psta->dev_addr, dev_addr, ETH_ALEN)) {
++
++							/* _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); */
++							/* issue GO Discoverability Request */
++							issue_group_disc_req(pwdinfo, psta->cmn.mac_addr);
++							/* _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); */
++
++							status = P2P_STATUS_SUCCESS;
++
++							break;
++						} else
++							status = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
++
++					}
++					_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++				} else
++					status = P2P_STATUS_FAIL_INVALID_PARAM;
++
++			} else
++				status = P2P_STATUS_FAIL_INVALID_PARAM;
++
++		}
++
++	}
++
++
++	/* issue Device Discoverability Response */
++	issue_p2p_devdisc_resp(pwdinfo, get_addr2_ptr(pframe), status, dialogToken);
++
++
++	return (status == P2P_STATUS_SUCCESS) ? _TRUE : _FALSE;
++
++}
++
++u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
++{
++	return _TRUE;
++}
++
++u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo,  u8 *pframe, uint len)
++{
++	u8 *frame_body;
++	u8 *wpsie;
++	uint	wps_ielen = 0, attr_contentlen = 0;
++	u16	uconfig_method = 0;
++
++
++	frame_body = (pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++
++	wpsie = rtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen);
++	if (wpsie) {
++		if (rtw_get_wps_attr_content(wpsie, wps_ielen, WPS_ATTR_CONF_METHOD , (u8 *) &uconfig_method, &attr_contentlen)) {
++			uconfig_method = be16_to_cpu(uconfig_method);
++			switch (uconfig_method) {
++			case WPS_CM_DISPLYA: {
++				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3);
++				break;
++			}
++			case WPS_CM_LABEL: {
++				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "lab", 3);
++				break;
++			}
++			case WPS_CM_PUSH_BUTTON: {
++				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3);
++				break;
++			}
++			case WPS_CM_KEYPAD: {
++				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3);
++				break;
++			}
++			}
++			issue_p2p_provision_resp(pwdinfo, get_addr2_ptr(pframe), frame_body, uconfig_method);
++		}
++	}
++	RTW_INFO("[%s] config method = %s\n", __FUNCTION__, pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req);
++	return _TRUE;
++
++}
++
++u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo,  u8 *pframe)
++{
++
++	return _TRUE;
++}
++
++u8 rtw_p2p_get_peer_ch_list(struct wifidirect_info *pwdinfo, u8 *ch_content, u8 ch_cnt, u8 *peer_ch_list)
++{
++	u8 i = 0, j = 0;
++	u8 temp = 0;
++	u8 ch_no = 0;
++	ch_content += 3;
++	ch_cnt -= 3;
++
++	while (ch_cnt > 0) {
++		ch_content += 1;
++		ch_cnt -= 1;
++		temp = *ch_content;
++		for (i = 0 ; i < temp ; i++, j++)
++			peer_ch_list[j] = *(ch_content + 1 + i);
++		ch_content += (temp + 1);
++		ch_cnt -= (temp + 1);
++		ch_no += temp ;
++	}
++
++	return ch_no;
++}
++
++u8 rtw_p2p_ch_inclusion(_adapter *adapter, u8 *peer_ch_list, u8 peer_ch_num, u8 *ch_list_inclusioned)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	int	i = 0, j = 0, temp = 0;
++	u8 ch_no = 0;
++
++	for (i = 0; i < peer_ch_num; i++) {
++		for (j = temp; j < rfctl->max_chan_nums; j++) {
++			if (*(peer_ch_list + i) == rfctl->channel_set[j].ChannelNum) {
++				ch_list_inclusioned[ch_no++] = *(peer_ch_list + i);
++				temp = j;
++				break;
++			}
++		}
++	}
++
++	return ch_no;
++}
++
++u8 process_p2p_group_negotation_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
++{
++	_adapter *padapter = pwdinfo->padapter;
++	u8	result = P2P_STATUS_SUCCESS;
++	u32	p2p_ielen = 0, wps_ielen = 0;
++	u8 *ies;
++	u32 ies_len;
++	u8 *p2p_ie;
++	u8 *wpsie;
++	u16		wps_devicepassword_id = 0x0000;
++	uint	wps_devicepassword_id_len = 0;
++#ifdef CONFIG_WFD
++#ifdef CONFIG_TDLS
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++#endif /* CONFIG_TDLS	 */
++#endif /* CONFIG_WFD */
++	wpsie = rtw_get_wps_ie(pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen);
++	if (wpsie) {
++		/*	Commented by Kurt 20120113 */
++		/*	If some device wants to do p2p handshake without sending prov_disc_req */
++		/*	We have to get peer_req_cm from here. */
++		if (_rtw_memcmp(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3)) {
++			rtw_get_wps_attr_content(wpsie, wps_ielen, WPS_ATTR_DEVICE_PWID, (u8 *) &wps_devicepassword_id, &wps_devicepassword_id_len);
++			wps_devicepassword_id = be16_to_cpu(wps_devicepassword_id);
++
++			if (wps_devicepassword_id == WPS_DPID_USER_SPEC)
++				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3);
++			else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)
++				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3);
++			else
++				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3);
++		}
++	} else {
++		RTW_INFO("[%s] WPS IE not Found!!\n", __FUNCTION__);
++		result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;
++		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++		return result ;
++	}
++
++	ies = pframe + _PUBLIC_ACTION_IE_OFFSET_;
++	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
++
++	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
++
++	if (!p2p_ie) {
++		RTW_INFO("[%s] P2P IE not Found!!\n", __FUNCTION__);
++		result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;
++		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++	}
++
++	while (p2p_ie) {
++		u8	attr_content = 0x00;
++		u32	attr_contentlen = 0;
++		u8	ch_content[100] = { 0x00 };
++		uint	ch_cnt = 0;
++		u8	peer_ch_list[100] = { 0x00 };
++		u8	peer_ch_num = 0;
++		u8	ch_list_inclusioned[100] = { 0x00 };
++		u8	ch_num_inclusioned = 0;
++		u16	cap_attr;
++		u8 listen_ch_attr[5] = { 0x00 };
++
++		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING);
++
++		/* Check P2P Capability ATTR */
++		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *)&attr_contentlen)) {
++			cap_attr = le16_to_cpu(cap_attr);
++
++#if defined(CONFIG_WFD) && defined(CONFIG_TDLS)
++			if (!(cap_attr & P2P_GRPCAP_INTRABSS))
++				ptdlsinfo->ap_prohibited = _TRUE;
++#endif /* defined(CONFIG_WFD) && defined(CONFIG_TDLS) */
++		}
++
++		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen)) {
++			RTW_INFO("[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01);
++			pwdinfo->peer_intent = attr_content;	/*	include both intent and tie breaker values. */
++
++			if (pwdinfo->intent == (pwdinfo->peer_intent >> 1)) {
++				/*	Try to match the tie breaker value */
++				if (pwdinfo->intent == P2P_MAX_INTENT) {
++					rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++					result = P2P_STATUS_FAIL_BOTH_GOINTENT_15;
++				} else {
++					if (attr_content & 0x01)
++						rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++					else
++						rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++				}
++			} else if (pwdinfo->intent > (pwdinfo->peer_intent >> 1))
++				rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++			else
++				rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++
++			if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++				/*	Store the group id information. */
++				_rtw_memcpy(pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN);
++				_rtw_memcpy(pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);
++			}
++		}
++
++		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, (u8 *)listen_ch_attr, (uint *) &attr_contentlen) && attr_contentlen == 5)
++			pwdinfo->nego_req_info.peer_ch = listen_ch_attr[4];
++
++		RTW_INFO(FUNC_ADPT_FMT" listen channel :%u\n", FUNC_ADPT_ARG(padapter), pwdinfo->nego_req_info.peer_ch);
++
++		attr_contentlen = 0;
++		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) {
++			if (attr_contentlen != ETH_ALEN)
++				_rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN);
++		}
++
++		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, ch_content, &ch_cnt)) {
++			peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, ch_content, ch_cnt, peer_ch_list);
++			ch_num_inclusioned = rtw_p2p_ch_inclusion(padapter, peer_ch_list, peer_ch_num, ch_list_inclusioned);
++
++			if (ch_num_inclusioned == 0) {
++				RTW_INFO("[%s] No common channel in channel list!\n", __FUNCTION__);
++				result = P2P_STATUS_FAIL_NO_COMMON_CH;
++				rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++				break;
++			}
++
++			if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++				if (!rtw_p2p_is_channel_list_ok(pwdinfo->operating_channel,
++					ch_list_inclusioned, ch_num_inclusioned)) {
++#ifdef CONFIG_CONCURRENT_MODE
++					if (rtw_mi_check_status(padapter, MI_LINKED)
++					    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
++						RTW_INFO("[%s] desired channel NOT Found!\n", __FUNCTION__);
++						result = P2P_STATUS_FAIL_NO_COMMON_CH;
++						rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++						break;
++					} else
++#endif /* CONFIG_CONCURRENT_MODE */
++					{
++						u8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0;
++						attr_contentlen = 0;
++
++						if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen))
++							peer_operating_ch = operatingch_info[4];
++
++						if (rtw_p2p_is_channel_list_ok(peer_operating_ch,
++							ch_list_inclusioned, ch_num_inclusioned)) {
++							/**
++							 *	Change our operating channel as peer's for compatibility.
++							 */
++							pwdinfo->operating_channel = peer_operating_ch;
++							RTW_INFO("[%s] Change op ch to %02x as peer's\n", __FUNCTION__, pwdinfo->operating_channel);
++						} else {
++							/* Take first channel of ch_list_inclusioned as operating channel */
++							pwdinfo->operating_channel = ch_list_inclusioned[0];
++							RTW_INFO("[%s] Change op ch to %02x\n", __FUNCTION__, pwdinfo->operating_channel);
++						}
++					}
++
++				}
++			}
++		}
++
++		/* Get the next P2P IE */
++		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
++	}
++
++	if (pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO) {
++		result = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
++		rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INFOR_NOREADY);
++		return result;
++	}
++
++#ifdef CONFIG_WFD
++	rtw_process_wfd_ies(padapter, pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, __func__);
++#endif
++
++	return result ;
++}
++
++u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
++{
++	_adapter *padapter = pwdinfo->padapter;
++	u8	result = P2P_STATUS_SUCCESS;
++	u32	p2p_ielen, wps_ielen;
++	u8 *ies;
++	u32 ies_len;
++	u8 *p2p_ie;
++#ifdef CONFIG_WFD
++#ifdef CONFIG_TDLS
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++#endif /* CONFIG_TDLS	 */
++#endif /* CONFIG_WFD */
++
++	ies = pframe + _PUBLIC_ACTION_IE_OFFSET_;
++	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
++
++	/*	Be able to know which one is the P2P GO and which one is P2P client. */
++
++	if (rtw_get_wps_ie(ies, ies_len, NULL, &wps_ielen)) {
++
++	} else {
++		RTW_INFO("[%s] WPS IE not Found!!\n", __FUNCTION__);
++		result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;
++		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++	}
++
++	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
++	if (!p2p_ie) {
++		rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++		result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;
++	} else {
++
++		u8	attr_content = 0x00;
++		u32	attr_contentlen = 0;
++		u8	operatingch_info[5] = { 0x00 };
++		u8	groupid[38];
++		u16	cap_attr;
++		u8	peer_ch_list[100] = { 0x00 };
++		u8	peer_ch_num = 0;
++		u8	ch_list_inclusioned[100] = { 0x00 };
++		u8	ch_num_inclusioned = 0;
++
++		while (p2p_ie) {	/*	Found the P2P IE. */
++
++			/* Check P2P Capability ATTR */
++			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *)&attr_contentlen)) {
++				cap_attr = le16_to_cpu(cap_attr);
++#ifdef CONFIG_TDLS
++				if (!(cap_attr & P2P_GRPCAP_INTRABSS))
++					ptdlsinfo->ap_prohibited = _TRUE;
++#endif /* CONFIG_TDLS */
++			}
++
++			rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen);
++			if (attr_contentlen == 1) {
++				RTW_INFO("[%s] Status = %d\n", __FUNCTION__, attr_content);
++				if (attr_content == P2P_STATUS_SUCCESS) {
++					/*	Do nothing. */
++				} else {
++					if (P2P_STATUS_FAIL_INFO_UNAVAILABLE == attr_content)
++						rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INFOR_NOREADY);
++					else
++						rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++					rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++					result = attr_content;
++					break;
++				}
++			}
++
++			/*	Try to get the peer's interface address */
++			attr_contentlen = 0;
++			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) {
++				if (attr_contentlen != ETH_ALEN)
++					_rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN);
++			}
++
++			/*	Try to get the peer's intent and tie breaker value. */
++			attr_content = 0x00;
++			attr_contentlen = 0;
++			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen)) {
++				RTW_INFO("[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01);
++				pwdinfo->peer_intent = attr_content;	/*	include both intent and tie breaker values. */
++
++				if (pwdinfo->intent == (pwdinfo->peer_intent >> 1)) {
++					/*	Try to match the tie breaker value */
++					if (pwdinfo->intent == P2P_MAX_INTENT) {
++						rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++						result = P2P_STATUS_FAIL_BOTH_GOINTENT_15;
++						rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++					} else {
++						rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
++						rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
++						if (attr_content & 0x01)
++							rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++						else
++							rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++					}
++				} else if (pwdinfo->intent > (pwdinfo->peer_intent >> 1)) {
++					rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
++					rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
++					rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++				} else {
++					rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
++					rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
++					rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++				}
++
++				if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++					/*	Store the group id information. */
++					_rtw_memcpy(pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN);
++					_rtw_memcpy(pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);
++
++				}
++			}
++
++			/*	Try to get the operation channel information */
++
++			attr_contentlen = 0;
++			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) {
++				RTW_INFO("[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4]);
++				pwdinfo->peer_operating_ch = operatingch_info[4];
++			}
++
++			/*	Try to get the channel list information */
++			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, pwdinfo->channel_list_attr, &pwdinfo->channel_list_attr_len)) {
++				RTW_INFO("[%s] channel list attribute found, len = %d\n", __FUNCTION__,  pwdinfo->channel_list_attr_len);
++
++				peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, pwdinfo->channel_list_attr, pwdinfo->channel_list_attr_len, peer_ch_list);
++				ch_num_inclusioned = rtw_p2p_ch_inclusion(padapter, peer_ch_list, peer_ch_num, ch_list_inclusioned);
++
++				if (ch_num_inclusioned == 0) {
++					RTW_INFO("[%s] No common channel in channel list!\n", __FUNCTION__);
++					result = P2P_STATUS_FAIL_NO_COMMON_CH;
++					rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++					break;
++				}
++
++				if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++					if (!rtw_p2p_is_channel_list_ok(pwdinfo->operating_channel,
++						ch_list_inclusioned, ch_num_inclusioned)) {
++#ifdef CONFIG_CONCURRENT_MODE
++						if (rtw_mi_check_status(padapter, MI_LINKED)
++						    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
++							RTW_INFO("[%s] desired channel NOT Found!\n", __FUNCTION__);
++							result = P2P_STATUS_FAIL_NO_COMMON_CH;
++							rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++							break;
++						} else
++#endif /* CONFIG_CONCURRENT_MODE */
++						{
++							u8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0;
++							attr_contentlen = 0;
++
++							if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen))
++								peer_operating_ch = operatingch_info[4];
++
++							if (rtw_p2p_is_channel_list_ok(peer_operating_ch,
++								ch_list_inclusioned, ch_num_inclusioned)) {
++								/**
++								 *	Change our operating channel as peer's for compatibility.
++								 */
++								pwdinfo->operating_channel = peer_operating_ch;
++								RTW_INFO("[%s] Change op ch to %02x as peer's\n", __FUNCTION__, pwdinfo->operating_channel);
++							} else {
++								/* Take first channel of ch_list_inclusioned as operating channel */
++								pwdinfo->operating_channel = ch_list_inclusioned[0];
++								RTW_INFO("[%s] Change op ch to %02x\n", __FUNCTION__, pwdinfo->operating_channel);
++							}
++						}
++
++					}
++				}
++
++			} else
++				RTW_INFO("[%s] channel list attribute not found!\n", __FUNCTION__);
++
++			/*	Try to get the group id information if peer is GO */
++			attr_contentlen = 0;
++			_rtw_memset(groupid, 0x00, 38);
++			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) {
++				_rtw_memcpy(pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN);
++				_rtw_memcpy(pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN);
++			}
++
++			/* Get the next P2P IE */
++			p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
++		}
++
++	}
++
++#ifdef CONFIG_WFD
++	rtw_process_wfd_ies(padapter, pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, __func__);
++#endif
++
++	return result ;
++
++}
++
++u8 process_p2p_group_negotation_confirm(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
++{
++#ifdef CONFIG_CONCURRENT_MODE
++	_adapter *padapter = pwdinfo->padapter;
++#endif
++	u8 *ies;
++	u32 ies_len;
++	u8 *p2p_ie;
++	u32	p2p_ielen = 0;
++	u8	result = P2P_STATUS_SUCCESS;
++	ies = pframe + _PUBLIC_ACTION_IE_OFFSET_;
++	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
++
++	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
++	while (p2p_ie) {	/*	Found the P2P IE. */
++		u8	attr_content = 0x00, operatingch_info[5] = { 0x00 };
++		u8	groupid[38] = { 0x00 };
++		u32	attr_contentlen = 0;
++
++		pwdinfo->negotiation_dialog_token = 1;
++		rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen);
++		if (attr_contentlen == 1) {
++			RTW_INFO("[%s] Status = %d\n", __FUNCTION__, attr_content);
++			result = attr_content;
++
++			if (attr_content == P2P_STATUS_SUCCESS) {
++
++				_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
++
++				/*	Commented by Albert 20100911 */
++				/*	Todo: Need to handle the case which both Intents are the same. */
++				rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
++				rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
++				if ((pwdinfo->intent) > (pwdinfo->peer_intent >> 1))
++					rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++				else if ((pwdinfo->intent) < (pwdinfo->peer_intent >> 1))
++					rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++				else {
++					/*	Have to compare the Tie Breaker */
++					if (pwdinfo->peer_intent & 0x01)
++						rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++					else
++						rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++				}
++
++#ifdef CONFIG_CONCURRENT_MODE
++				if (rtw_mi_check_status(padapter, MI_LINKED)
++				    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
++					/*	Switch back to the AP channel soon. */
++					_set_timer(&pwdinfo->ap_p2p_switch_timer, 100);
++				}
++#endif
++			} else {
++				rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++				rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
++				break;
++			}
++		}
++
++		/*	Try to get the group id information */
++		attr_contentlen = 0;
++		_rtw_memset(groupid, 0x00, 38);
++		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) {
++			RTW_INFO("[%s] Ssid = %s, ssidlen = %zu\n", __FUNCTION__, &groupid[ETH_ALEN], strlen(&groupid[ETH_ALEN]));
++			_rtw_memcpy(pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN);
++			_rtw_memcpy(pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN);
++		}
++
++		attr_contentlen = 0;
++		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) {
++			RTW_INFO("[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4]);
++			pwdinfo->peer_operating_ch = operatingch_info[4];
++		}
++
++		/* Get the next P2P IE */
++		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
++
++	}
++
++	return result ;
++}
++
++u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
++{
++	u8 *frame_body;
++	u8 dialogToken = 0;
++	u8 status = P2P_STATUS_SUCCESS;
++
++	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++
++	dialogToken = frame_body[6];
++
++	/* todo: check NoA attribute */
++
++	issue_p2p_presence_resp(pwdinfo, get_addr2_ptr(pframe), status, dialogToken);
++
++	return _TRUE;
++}
++
++void find_phase_handler(_adapter	*padapter)
++{
++	struct wifidirect_info  *pwdinfo = &padapter->wdinfo;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct sitesurvey_parm parm;
++	_irqL				irqL;
++	u8					_status = 0;
++
++
++	rtw_init_sitesurvey_parm(padapter, &parm);
++	_rtw_memcpy(&parm.ssid[0].Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN);
++	parm.ssid[0].SsidLength = P2P_WILDCARD_SSID_LEN;
++	parm.ssid_num = 1;
++
++	rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++	_status = rtw_sitesurvey_cmd(padapter, &parm);
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++
++}
++
++void p2p_concurrent_handler(_adapter *padapter);
++
++void restore_p2p_state_handler(_adapter	*padapter)
++{
++	struct wifidirect_info  *pwdinfo = &padapter->wdinfo;
++
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL))
++		rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_check_status(padapter, MI_LINKED)) {
++		u8 union_ch = rtw_mi_get_union_chan(padapter);
++		u8 union_bw = rtw_mi_get_union_bw(padapter);
++		u8 union_offset = rtw_mi_get_union_offset(padapter);
++
++		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP)) {
++			set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
++			rtw_back_opch(padapter);
++		}
++	}
++#endif
++
++	rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
++
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) {
++#ifdef CONFIG_CONCURRENT_MODE
++		p2p_concurrent_handler(padapter);
++#else
++		/*	In the P2P client mode, the driver should not switch back to its listen channel */
++		/*	because this P2P client should stay at the operating channel of P2P GO. */
++		set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++#endif
++	}
++}
++
++void pre_tx_invitereq_handler(_adapter	*padapter)
++{
++	struct wifidirect_info  *pwdinfo = &padapter->wdinfo;
++	u8	val8 = 1;
++
++	set_channel_bwmode(padapter, pwdinfo->invitereq_info.peer_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++	issue_probereq_p2p(padapter, NULL);
++	_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
++
++}
++
++void pre_tx_provdisc_handler(_adapter	*padapter)
++{
++	struct wifidirect_info  *pwdinfo = &padapter->wdinfo;
++	u8	val8 = 1;
++
++	set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++	issue_probereq_p2p(padapter, NULL);
++	_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
++
++}
++
++void pre_tx_negoreq_handler(_adapter	*padapter)
++{
++	struct wifidirect_info  *pwdinfo = &padapter->wdinfo;
++	u8	val8 = 1;
++
++	set_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++	issue_probereq_p2p(padapter , NULL);
++	/* WIN Phone only accept unicast probe request when nego back */
++	issue_probereq_p2p(padapter , pwdinfo->nego_req_info.peerDevAddr);
++	_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
++
++}
++
++#ifdef CONFIG_CONCURRENT_MODE
++void p2p_concurrent_handler(_adapter	*padapter)
++{
++	struct rtw_wdev_priv	*pwdev_priv = adapter_wdev_data(padapter);
++	struct dvobj_priv	*pdvobj = adapter_to_dvobj(padapter);
++	struct wifidirect_info	*pwdinfo = &padapter->wdinfo;
++	u8			val8;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (pwdinfo->driver_interface == DRIVER_CFG80211
++		&& !rtw_cfg80211_get_is_roch(padapter))
++		return;
++#endif
++
++	if (rtw_mi_check_status(padapter, MI_LINKED)) {
++		u8 union_ch = rtw_mi_get_union_chan(padapter);
++		u8 union_bw = rtw_mi_get_union_bw(padapter);
++		u8 union_offset = rtw_mi_get_union_offset(padapter);
++		unsigned int duration;
++
++		pwdinfo->operating_channel = union_ch;
++
++		if (pwdinfo->driver_interface == DRIVER_CFG80211) {
++			_enter_critical_mutex(&pwdev_priv->roch_mutex, NULL);
++
++			if (rtw_get_oper_ch(padapter) != union_ch) {
++				/* Current channel is not AP's channel - switching to AP's channel */
++				RTW_INFO("%s, switch ch back to union=%u,%u, %u\n"
++					, __func__, union_ch, union_bw, union_offset);
++				set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
++				rtw_back_opch(padapter);
++
++				/* Now, the driver stays on AP's channel. We should stay on AP's
++				 * channel for min_home_dur (duration) and next switch channel is
++				 * listen channel.
++				 */
++				duration = pwdinfo->min_home_dur;
++			} else {
++				/* Current channel is AP's channel - switching to listen channel */
++				RTW_INFO("%s, switch ch to roch=%u\n"
++					, __func__, pwdinfo->listen_channel);
++				rtw_leave_opch(padapter);
++				set_channel_bwmode(padapter,
++						pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++
++				/* Now, the driver stays on listen channel. We should stay on listen
++				 * channel for max_away_dur (duration) and next switch channel is AP's
++				 * channel.
++				 */
++				duration = pwdinfo->max_away_dur;
++			}
++
++			/* set channel switch timer */
++			ATOMIC_SET(&pwdev_priv->switch_ch_to, 0);
++			_set_timer(&pwdinfo->ap_p2p_switch_timer, duration);
++			RTW_INFO("%s, set switch ch timer, duration=%d\n", __func__, duration);
++
++			_exit_critical_mutex(&pwdev_priv->roch_mutex, NULL);
++		} else if (pwdinfo->driver_interface == DRIVER_WEXT) {
++			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) {
++				/*	Now, the driver stays on the AP's channel. */
++				/*	If the pwdinfo->ext_listen_period = 0, that means the P2P listen state is not available on listen channel. */
++				if (pwdinfo->ext_listen_period > 0) {
++					RTW_INFO("[%s] P2P_STATE_IDLE, ext_listen_period = %d\n", __FUNCTION__, pwdinfo->ext_listen_period);
++
++					if (union_ch != pwdinfo->listen_channel) {
++						rtw_leave_opch(padapter);
++						set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++					}
++
++					rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
++
++					if (!rtw_mi_check_mlmeinfo_state(padapter, WIFI_FW_AP_STATE)) {
++						val8 = 1;
++						rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++					}
++					/*	Todo: To check the value of pwdinfo->ext_listen_period is equal to 0 or not. */
++					_set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_period);
++				}
++
++			} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) ||
++				rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL) ||
++				(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) && pwdinfo->nego_req_info.benable == _FALSE) ||
++				rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ)) {
++				/*	Now, the driver is in the listen state of P2P mode. */
++				RTW_INFO("[%s] P2P_STATE_IDLE, ext_listen_interval = %d\n", __FUNCTION__, pwdinfo->ext_listen_interval);
++
++				/*	Commented by Albert 2012/11/01 */
++				/*	If the AP's channel is the same as the listen channel, we should still be in the listen state */
++				/*	Other P2P device is still able to find this device out even this device is in the AP's channel. */
++				/*	So, configure this device to be able to receive the probe request frame and set it to listen state. */
++				if (union_ch != pwdinfo->listen_channel) {
++
++					set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
++					if (!rtw_mi_check_status(padapter, MI_AP_MODE)) {
++						val8 = 0;
++						rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++					}
++					rtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE);
++					rtw_back_opch(padapter);
++				}
++
++				/*	Todo: To check the value of pwdinfo->ext_listen_interval is equal to 0 or not. */
++				_set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_interval);
++
++			} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK)) {
++				/*	The driver had finished the P2P handshake successfully. */
++				val8 = 0;
++				rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++				set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
++				rtw_back_opch(padapter);
++
++			} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) {
++				val8 = 1;
++				set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++				rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++				issue_probereq_p2p(padapter, NULL);
++				_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
++			} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) && pwdinfo->nego_req_info.benable == _TRUE) {
++				val8 = 1;
++				set_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++				rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++				issue_probereq_p2p(padapter, NULL);
++				_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
++			} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ) && pwdinfo->invitereq_info.benable == _TRUE) {
++				/*
++				val8 = 1;
++				set_channel_bwmode(padapter, , HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++				rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++				issue_probereq_p2p(padapter, NULL);
++				_set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT );
++				*/
++			}
++		}
++	} else {
++		/* In p2p+softap. When in P2P_STATE_GONEGO_OK, not back to listen channel.*/
++		if (!rtw_p2p_chk_state(pwdinfo , P2P_STATE_GONEGO_OK) || padapter->registrypriv.full_ch_in_p2p_handshake == 0)
++			set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++		else
++			RTW_INFO("%s, buddy not linked, go nego ok, not back to listen channel\n", __func__);
++	}
++
++}
++#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++u8 roch_stay_in_cur_chan(_adapter *padapter)
++{
++	int i;
++	_adapter *iface;
++	struct mlme_priv *pmlmepriv;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	u8 rst = _FALSE;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (iface) {
++			pmlmepriv = &iface->mlmepriv;
++
++			if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS | WIFI_UNDER_KEY_HANDSHAKE) == _TRUE) {
++				RTW_INFO(ADPT_FMT"- WIFI_UNDER_LINKING |WIFI_UNDER_WPS | WIFI_UNDER_KEY_HANDSHAKE (mlme state:0x%x)\n",
++						ADPT_ARG(iface), get_fwstate(&iface->mlmepriv));
++				rst = _TRUE;
++				break;
++			}
++			#ifdef CONFIG_AP_MODE
++			if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) {
++				if (rtw_ap_sta_states_check(iface) == _TRUE) {
++					rst = _TRUE;
++					break;
++				}
++			}
++			#endif
++		}
++	}
++
++	return rst;
++}
++
++static int ro_ch_handler(_adapter *adapter, u8 *buf)
++{
++	int ret = H2C_SUCCESS;
++	struct p2p_roch_parm *roch_parm = (struct p2p_roch_parm *)buf;
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
++	struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &adapter->cfg80211_wdinfo;
++#ifdef CONFIG_CONCURRENT_MODE
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++#ifdef RTW_ROCH_BACK_OP
++	struct wifidirect_info *pwdinfo = &adapter->wdinfo;
++#endif
++#endif
++	u8 ready_on_channel = _FALSE;
++	u8 remain_ch;
++	unsigned int duration;
++
++	_enter_critical_mutex(&pwdev_priv->roch_mutex, NULL);
++
++	if (rtw_cfg80211_get_is_roch(adapter) != _TRUE)
++		goto exit;
++
++	remain_ch = (u8)ieee80211_frequency_to_channel(roch_parm->ch.center_freq);
++	duration = roch_parm->duration;
++
++	RTW_INFO(FUNC_ADPT_FMT" ch:%u duration:%d, cookie:0x%llx\n"
++		, FUNC_ADPT_ARG(adapter), remain_ch, roch_parm->duration, roch_parm->cookie);
++
++	if (roch_parm->wdev && roch_parm->cookie) {
++		if (pcfg80211_wdinfo->ro_ch_wdev != roch_parm->wdev) {
++			RTW_WARN(FUNC_ADPT_FMT" ongoing wdev:%p, wdev:%p\n"
++				, FUNC_ADPT_ARG(adapter), pcfg80211_wdinfo->ro_ch_wdev, roch_parm->wdev);
++			rtw_warn_on(1);
++		}
++
++		if (pcfg80211_wdinfo->remain_on_ch_cookie != roch_parm->cookie) {
++			RTW_WARN(FUNC_ADPT_FMT" ongoing cookie:0x%llx, cookie:0x%llx\n"
++				, FUNC_ADPT_ARG(adapter), pcfg80211_wdinfo->remain_on_ch_cookie, roch_parm->cookie);
++			rtw_warn_on(1);
++		}
++	}
++
++	if (roch_stay_in_cur_chan(adapter) == _TRUE) {
++		remain_ch = rtw_mi_get_union_chan(adapter);
++		RTW_INFO(FUNC_ADPT_FMT" stay in union ch:%d\n", FUNC_ADPT_ARG(adapter), remain_ch);
++	}
++
++	#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_check_status(adapter, MI_LINKED) && (0 != rtw_mi_get_union_chan(adapter))) {
++		if ((remain_ch != rtw_mi_get_union_chan(adapter)) && !check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE)) {
++			if (remain_ch != pmlmeext->cur_channel
++				#ifdef RTW_ROCH_BACK_OP
++				|| ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1
++				#endif
++			) {
++				rtw_leave_opch(adapter);
++
++				#ifdef RTW_ROCH_BACK_OP
++				RTW_INFO("%s, set switch ch timer, duration=%d\n", __func__, pwdinfo->max_away_dur);
++				ATOMIC_SET(&pwdev_priv->switch_ch_to, 0);
++				/* remain_ch is not same as union channel. duration is max_away_dur to
++				 * back to AP's channel.
++				 */
++				_set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->max_away_dur);
++				#endif
++			}
++		}
++		ready_on_channel = _TRUE;
++	} else
++	#endif /* CONFIG_CONCURRENT_MODE */
++	{
++		if (remain_ch != rtw_get_oper_ch(adapter))
++			ready_on_channel = _TRUE;
++	}
++
++	if (ready_on_channel == _TRUE) {
++		#ifndef RTW_SINGLE_WIPHY
++		if (!check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE))
++		#endif
++		{
++			#ifdef CONFIG_CONCURRENT_MODE
++			if (rtw_get_oper_ch(adapter) != remain_ch)
++			#endif
++			{
++				/* if (!padapter->mlmepriv.LinkDetectInfo.bBusyTraffic) */
++				set_channel_bwmode(adapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++			}
++		}
++	}
++
++	#ifdef CONFIG_BT_COEXIST
++	rtw_btcoex_ScanNotify(adapter, _TRUE);
++	#endif
++
++	RTW_INFO("%s, set ro ch timer, duration=%d\n", __func__, duration);
++	_set_timer(&pcfg80211_wdinfo->remain_on_ch_timer, duration);
++
++exit:
++	_exit_critical_mutex(&pwdev_priv->roch_mutex, NULL);
++
++	return ret;
++}
++
++static int cancel_ro_ch_handler(_adapter *padapter, u8 *buf)
++{
++	int ret = H2C_SUCCESS;
++	struct p2p_roch_parm *roch_parm = (struct p2p_roch_parm *)buf;
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++	struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;
++	struct wireless_dev *wdev;
++	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++	u8 ch, bw, offset;
++
++	_enter_critical_mutex(&pwdev_priv->roch_mutex, NULL);
++
++	if (rtw_cfg80211_get_is_roch(padapter) != _TRUE)
++		goto exit;
++
++	if (roch_parm->wdev && roch_parm->cookie) {
++		if (pcfg80211_wdinfo->ro_ch_wdev != roch_parm->wdev) {
++			RTW_WARN(FUNC_ADPT_FMT" ongoing wdev:%p, wdev:%p\n"
++				, FUNC_ADPT_ARG(padapter), pcfg80211_wdinfo->ro_ch_wdev, roch_parm->wdev);
++			rtw_warn_on(1);
++		}
++
++		if (pcfg80211_wdinfo->remain_on_ch_cookie != roch_parm->cookie) {
++			RTW_WARN(FUNC_ADPT_FMT" ongoing cookie:0x%llx, cookie:0x%llx\n"
++				, FUNC_ADPT_ARG(padapter), pcfg80211_wdinfo->remain_on_ch_cookie, roch_parm->cookie);
++			rtw_warn_on(1);
++		}
++	}
++
++#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE)
++	_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);
++	ATOMIC_SET(&pwdev_priv->switch_ch_to, 1);
++#endif
++
++	if (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) {
++		if (0)
++			RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n",
++				 FUNC_ADPT_ARG(padapter), ch, bw, offset);
++	} else if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->listen_channel) {
++		ch = pwdinfo->listen_channel;
++		bw = CHANNEL_WIDTH_20;
++		offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		if (0)
++			RTW_INFO(FUNC_ADPT_FMT" back to listen ch - ch:%u, bw:%u, offset:%u\n",
++				 FUNC_ADPT_ARG(padapter), ch, bw, offset);
++	} else {
++		ch = pcfg80211_wdinfo->restore_channel;
++		bw = CHANNEL_WIDTH_20;
++		offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		if (0)
++			RTW_INFO(FUNC_ADPT_FMT" back to restore ch - ch:%u, bw:%u, offset:%u\n",
++				 FUNC_ADPT_ARG(padapter), ch, bw, offset);
++	}
++
++	set_channel_bwmode(padapter, ch, offset, bw);
++	rtw_back_opch(padapter);
++
++	rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
++#ifdef CONFIG_DEBUG_CFG80211
++	RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));
++#endif
++
++	wdev = pcfg80211_wdinfo->ro_ch_wdev;
++
++	rtw_cfg80211_set_is_roch(padapter, _FALSE);
++	pcfg80211_wdinfo->ro_ch_wdev = NULL;
++	rtw_cfg80211_set_last_ro_ch_time(padapter);
++
++	rtw_cfg80211_remain_on_channel_expired(wdev
++		, pcfg80211_wdinfo->remain_on_ch_cookie
++		, &pcfg80211_wdinfo->remain_on_ch_channel
++		, pcfg80211_wdinfo->remain_on_ch_type, GFP_KERNEL);
++
++	RTW_INFO("cfg80211_remain_on_channel_expired cookie:0x%llx\n"
++		, pcfg80211_wdinfo->remain_on_ch_cookie);
++
++#ifdef CONFIG_BT_COEXIST
++	rtw_btcoex_ScanNotify(padapter, _FALSE);
++#endif
++
++exit:
++	_exit_critical_mutex(&pwdev_priv->roch_mutex, NULL);
++
++	return ret;
++}
++
++static void ro_ch_timer_process(void *FunctionContext)
++{
++	_adapter *adapter = (_adapter *)FunctionContext;
++
++	p2p_cancel_roch_cmd(adapter, 0, NULL, 0);
++}
++
++#if 0
++static void rtw_change_p2pie_op_ch(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch)
++{
++	u8 *ies, *p2p_ie;
++	u32 ies_len, p2p_ielen;
++
++#ifdef CONFIG_MCC_MODE
++	if (MCC_EN(padapter))
++		return;
++#endif /* CONFIG_MCC_MODE */
++
++	ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
++	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
++
++	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
++
++	while (p2p_ie) {
++		u32	attr_contentlen = 0;
++		u8 *pattr = NULL;
++
++		/* Check P2P_ATTR_OPERATING_CH */
++		attr_contentlen = 0;
++		pattr = NULL;
++		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint *)&attr_contentlen);
++		if (pattr != NULL)
++			*(pattr + 4) = ch;
++
++		/* Get the next P2P IE */
++		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
++	}
++}
++#endif
++
++#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
++static void rtw_change_p2pie_ch_list(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch)
++{
++	u8 *ies, *p2p_ie;
++	u32 ies_len, p2p_ielen;
++
++#ifdef CONFIG_MCC_MODE
++	if (MCC_EN(padapter))
++		return;
++#endif /* CONFIG_MCC_MODE */
++
++	ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
++	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
++
++	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
++
++	while (p2p_ie) {
++		u32	attr_contentlen = 0;
++		u8 *pattr = NULL;
++
++		/* Check P2P_ATTR_CH_LIST */
++		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint *)&attr_contentlen);
++		if (pattr != NULL) {
++			int i;
++			u32 num_of_ch;
++			u8 *pattr_temp = pattr + 3 ;
++
++			attr_contentlen -= 3;
++
++			while (attr_contentlen > 0) {
++				num_of_ch = *(pattr_temp + 1);
++
++				for (i = 0; i < num_of_ch; i++)
++					*(pattr_temp + 2 + i) = ch;
++
++				pattr_temp += (2 + num_of_ch);
++				attr_contentlen -= (2 + num_of_ch);
++			}
++		}
++
++		/* Get the next P2P IE */
++		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
++	}
++}
++#endif
++
++#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
++static bool rtw_chk_p2pie_ch_list_with_buddy(_adapter *padapter, const u8 *frame_body, u32 len)
++{
++	bool fit = _FALSE;
++	u8 *ies, *p2p_ie;
++	u32 ies_len, p2p_ielen;
++	u8 union_ch = rtw_mi_get_union_chan(padapter);
++
++	ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
++	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
++
++	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
++
++	while (p2p_ie) {
++		u32	attr_contentlen = 0;
++		u8 *pattr = NULL;
++
++		/* Check P2P_ATTR_CH_LIST */
++		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint *)&attr_contentlen);
++		if (pattr != NULL) {
++			int i;
++			u32 num_of_ch;
++			u8 *pattr_temp = pattr + 3 ;
++
++			attr_contentlen -= 3;
++
++			while (attr_contentlen > 0) {
++				num_of_ch = *(pattr_temp + 1);
++
++				for (i = 0; i < num_of_ch; i++) {
++					if (*(pattr_temp + 2 + i) == union_ch) {
++						RTW_INFO(FUNC_ADPT_FMT" ch_list fit buddy_ch:%u\n", FUNC_ADPT_ARG(padapter), union_ch);
++						fit = _TRUE;
++						break;
++					}
++				}
++
++				pattr_temp += (2 + num_of_ch);
++				attr_contentlen -= (2 + num_of_ch);
++			}
++		}
++
++		/* Get the next P2P IE */
++		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
++	}
++
++	return fit;
++}
++
++#if defined(CONFIG_P2P_INVITE_IOT)
++static bool rtw_chk_p2pie_op_ch_with_buddy(_adapter *padapter, const u8 *frame_body, u32 len)
++{
++	bool fit = _FALSE;
++	u8 *ies, *p2p_ie;
++	u32 ies_len, p2p_ielen;
++	u8 union_ch = rtw_mi_get_union_chan(padapter);
++
++	ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
++	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
++
++	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
++
++	while (p2p_ie) {
++		u32	attr_contentlen = 0;
++		u8 *pattr = NULL;
++
++		/* Check P2P_ATTR_OPERATING_CH */
++		attr_contentlen = 0;
++		pattr = NULL;
++		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint *)&attr_contentlen);
++		if (pattr != NULL) {
++			if (*(pattr + 4) == union_ch) {
++				RTW_INFO(FUNC_ADPT_FMT" op_ch fit buddy_ch:%u\n", FUNC_ADPT_ARG(padapter), union_ch);
++				fit = _TRUE;
++				break;
++			}
++		}
++
++		/* Get the next P2P IE */
++		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
++	}
++
++	return fit;
++}
++#endif
++
++static void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *frame_body, u32 len)
++{
++	u8 *ies, *p2p_ie;
++	u32 ies_len, p2p_ielen;
++	u8 union_ch = rtw_mi_get_union_chan(padapter);
++
++#ifdef CONFIG_MCC_MODE
++	if (MCC_EN(padapter))
++		return;
++#endif /* CONFIG_MCC_MODE */
++
++	ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
++	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
++
++	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
++
++	while (p2p_ie) {
++		u32	attr_contentlen = 0;
++		u8 *pattr = NULL;
++
++		/* Check P2P_ATTR_CH_LIST */
++		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint *)&attr_contentlen);
++		if (pattr != NULL) {
++			int i;
++			u32 num_of_ch;
++			u8 *pattr_temp = pattr + 3 ;
++
++			attr_contentlen -= 3;
++
++			while (attr_contentlen > 0) {
++				num_of_ch = *(pattr_temp + 1);
++
++				for (i = 0; i < num_of_ch; i++) {
++					if (*(pattr_temp + 2 + i) && *(pattr_temp + 2 + i) != union_ch) {
++						#ifdef RTW_SINGLE_WIPHY
++						RTW_ERR("replace ch_list:%u with:%u\n", *(pattr_temp + 2 + i), union_ch);
++						#endif
++						*(pattr_temp + 2 + i) = union_ch; /*forcing to the same channel*/
++					}
++				}
++
++				pattr_temp += (2 + num_of_ch);
++				attr_contentlen -= (2 + num_of_ch);
++			}
++		}
++
++		/* Check P2P_ATTR_OPERATING_CH */
++		attr_contentlen = 0;
++		pattr = NULL;
++		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint *)&attr_contentlen);
++		if (pattr != NULL) {
++			if (*(pattr + 4) && *(pattr + 4) != union_ch) {
++				#ifdef RTW_SINGLE_WIPHY
++				RTW_ERR("replace op_ch:%u with:%u\n", *(pattr + 4), union_ch);
++				#endif
++				*(pattr + 4) = union_ch; /*forcing to the same channel	*/
++			}
++		}
++
++		/* Get the next P2P IE */
++		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
++
++	}
++
++}
++#endif
++
++#ifdef CONFIG_WFD
++u32 rtw_xframe_build_wfd_ie(struct xmit_frame *xframe)
++{
++	_adapter *adapter = xframe->padapter;
++	struct wifidirect_info *wdinfo = &adapter->wdinfo;
++	u8 *frame = xframe->buf_addr + TXDESC_OFFSET;
++	u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr);
++	u8 *frame_tail = frame + xframe->attrib.pktlen;
++	u8 category, action, OUI_Subtype, dialogToken = 0;
++	u32	wfdielen = 0;
++
++	category = frame_body[0];
++	if (category == RTW_WLAN_CATEGORY_PUBLIC) {
++		action = frame_body[1];
++		if (action == ACT_PUBLIC_VENDOR
++		    && _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE
++		   ) {
++			OUI_Subtype = frame_body[6];
++			dialogToken = frame_body[7];
++
++			switch (OUI_Subtype) {
++			case P2P_GO_NEGO_REQ:
++				wfdielen = build_nego_req_wfd_ie(wdinfo, frame_tail);
++				break;
++			case P2P_GO_NEGO_RESP:
++				wfdielen = build_nego_resp_wfd_ie(wdinfo, frame_tail);
++				break;
++			case P2P_GO_NEGO_CONF:
++				wfdielen = build_nego_confirm_wfd_ie(wdinfo, frame_tail);
++				break;
++			case P2P_INVIT_REQ:
++				wfdielen = build_invitation_req_wfd_ie(wdinfo, frame_tail);
++				break;
++			case P2P_INVIT_RESP:
++				wfdielen = build_invitation_resp_wfd_ie(wdinfo, frame_tail);
++				break;
++			case P2P_PROVISION_DISC_REQ:
++				wfdielen = build_provdisc_req_wfd_ie(wdinfo, frame_tail);
++				break;
++			case P2P_PROVISION_DISC_RESP:
++				wfdielen = build_provdisc_resp_wfd_ie(wdinfo, frame_tail);
++				break;
++			case P2P_DEVDISC_REQ:
++			case P2P_DEVDISC_RESP:
++			default:
++				break;
++			}
++
++		}
++	} else if (category == RTW_WLAN_CATEGORY_P2P) {
++		OUI_Subtype = frame_body[5];
++		dialogToken = frame_body[6];
++
++#ifdef CONFIG_DEBUG_CFG80211
++		RTW_INFO("ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n"
++			, cpu_to_be32(*((u32 *)(frame_body + 1))), OUI_Subtype, dialogToken);
++#endif
++
++		switch (OUI_Subtype) {
++		case P2P_NOTICE_OF_ABSENCE:
++			break;
++		case P2P_PRESENCE_REQUEST:
++			break;
++		case P2P_PRESENCE_RESPONSE:
++			break;
++		case P2P_GO_DISC_REQUEST:
++			break;
++		default:
++			break;
++		}
++	} else
++		RTW_INFO("%s, action frame category=%d\n", __func__, category);
++
++	xframe->attrib.pktlen += wfdielen;
++
++	return wfdielen;
++}
++#endif /* CONFIG_WFD */
++
++bool rtw_xframe_del_wfd_ie(struct xmit_frame *xframe)
++{
++#define DBG_XFRAME_DEL_WFD_IE 0
++	u8 *frame = xframe->buf_addr + TXDESC_OFFSET;
++	u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr);
++	u8 *frame_tail = frame + xframe->attrib.pktlen;
++	u8 category, action, OUI_Subtype;
++	u8 *ies = NULL;
++	uint ies_len_ori = 0;
++	uint ies_len = 0;
++
++	category = frame_body[0];
++	if (category == RTW_WLAN_CATEGORY_PUBLIC) {
++		action = frame_body[1];
++		if (action == ACT_PUBLIC_VENDOR
++		    && _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE
++		   ) {
++			OUI_Subtype = frame_body[6];
++
++			switch (OUI_Subtype) {
++			case P2P_GO_NEGO_REQ:
++			case P2P_GO_NEGO_RESP:
++			case P2P_GO_NEGO_CONF:
++			case P2P_INVIT_REQ:
++			case P2P_INVIT_RESP:
++			case P2P_PROVISION_DISC_REQ:
++			case P2P_PROVISION_DISC_RESP:
++				ies = frame_body + 8;
++				ies_len_ori = frame_tail - (frame_body + 8);
++				break;
++			}
++		}
++	}
++
++	if (ies && ies_len_ori) {
++		ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_XFRAME_DEL_WFD_IE ? __func__ : NULL);
++		xframe->attrib.pktlen -= (ies_len_ori - ies_len);
++	}
++
++	return ies_len_ori != ies_len;
++}
++
++/*
++* rtw_xframe_chk_wfd_ie -
++*
++*/
++void rtw_xframe_chk_wfd_ie(struct xmit_frame *xframe)
++{
++	_adapter *adapter = xframe->padapter;
++#ifdef CONFIG_IOCTL_CFG80211
++	struct wifidirect_info *wdinfo = &adapter->wdinfo;
++#endif
++	u8 build = 0;
++	u8 del = 0;
++
++	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
++		del = 1;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (wdinfo->wfd_info->wfd_enable == _TRUE)
++#endif
++		del = build = 1;
++
++	if (del)
++		rtw_xframe_del_wfd_ie(xframe);
++
++#ifdef CONFIG_WFD
++	if (build)
++		rtw_xframe_build_wfd_ie(xframe);
++#endif
++}
++
++u8 *dump_p2p_attr_ch_list(u8 *p2p_ie, uint p2p_ielen, u8 *buf, u32 buf_len)
++{
++	uint attr_contentlen = 0;
++	u8 *pattr = NULL;
++	int w_sz = 0;
++	u8 ch_cnt = 0;
++	u8 ch_list[40];
++
++	pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, &attr_contentlen);
++	if (pattr != NULL) {
++		int i, j;
++		u32 num_of_ch;
++		u8 *pattr_temp = pattr + 3 ;
++
++		attr_contentlen -= 3;
++
++		_rtw_memset(ch_list, 0, 40);
++
++		while (attr_contentlen > 0) {
++			num_of_ch = *(pattr_temp + 1);
++
++			for (i = 0; i < num_of_ch; i++) {
++				for (j = 0; j < ch_cnt; j++) {
++					if (ch_list[j] == *(pattr_temp + 2 + i))
++						break;
++				}
++				if (j >= ch_cnt)
++					ch_list[ch_cnt++] = *(pattr_temp + 2 + i);
++
++			}
++
++			pattr_temp += (2 + num_of_ch);
++			attr_contentlen -= (2 + num_of_ch);
++		}
++
++		for (j = 0; j < ch_cnt; j++) {
++			if (j == 0)
++				w_sz += snprintf(buf + w_sz, buf_len - w_sz, "%u", ch_list[j]);
++			else if (ch_list[j] - ch_list[j - 1] != 1)
++				w_sz += snprintf(buf + w_sz, buf_len - w_sz, ", %u", ch_list[j]);
++			else if (j != ch_cnt - 1 && ch_list[j + 1] - ch_list[j] == 1) {
++				/* empty */
++			} else
++				w_sz += snprintf(buf + w_sz, buf_len - w_sz, "-%u", ch_list[j]);
++		}
++	}
++	return buf;
++}
++
++/*
++ * return _TRUE if requester is GO, _FALSE if responder is GO
++ */
++bool rtw_p2p_nego_intent_compare(u8 req, u8 resp)
++{
++	if (req >> 1 == resp >> 1)
++		return  req & 0x01 ? _TRUE : _FALSE;
++	else if (req >> 1 > resp >> 1)
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
++{
++	int is_p2p_frame = (-1);
++	unsigned char	*frame_body;
++	u8 category, action, OUI_Subtype, dialogToken = 0;
++	u8 *p2p_ie = NULL;
++	uint p2p_ielen = 0;
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++	int status = -1;
++	u8 ch_list_buf[128] = {'\0'};
++	int op_ch = -1;
++	int listen_ch = -1;
++	u8 intent = 0;
++	u8 *iaddr = NULL;
++	u8 *gbssid = NULL;
++
++	frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr));
++	category = frame_body[0];
++	/* just for check */
++	if (category == RTW_WLAN_CATEGORY_PUBLIC) {
++		action = frame_body[1];
++		if (action == ACT_PUBLIC_VENDOR
++			&& _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE
++		) {
++			OUI_Subtype = frame_body[6];
++			dialogToken = frame_body[7];
++			is_p2p_frame = OUI_Subtype;
++
++			#ifdef CONFIG_DEBUG_CFG80211
++			RTW_INFO("ACTION_CATEGORY_PUBLIC: ACT_PUBLIC_VENDOR, OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n",
++				cpu_to_be32(*((u32 *)(frame_body + 2))), OUI_Subtype, dialogToken);
++			#endif
++
++			p2p_ie = rtw_get_p2p_ie(
++				(u8 *)buf + sizeof(struct rtw_ieee80211_hdr_3addr) + _PUBLIC_ACTION_IE_OFFSET_
++				, len - sizeof(struct rtw_ieee80211_hdr_3addr) - _PUBLIC_ACTION_IE_OFFSET_
++				, NULL, &p2p_ielen);
++
++			switch (OUI_Subtype) { /* OUI Subtype */
++				u8 *cont;
++				uint cont_len;
++			case P2P_GO_NEGO_REQ: {
++				struct rtw_wdev_nego_info *nego_info = &pwdev_priv->nego_info;
++
++				if (tx) {
++					#ifdef CONFIG_DRV_ISSUE_PROV_REQ /* IOT FOR S2 */
++					if (pwdev_priv->provdisc_req_issued == _FALSE)
++						rtw_cfg80211_issue_p2p_provision_request(padapter, buf, len);
++					#endif /* CONFIG_DRV_ISSUE_PROV_REQ */
++
++					/* pwdev_priv->provdisc_req_issued = _FALSE; */
++
++					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
++					if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
++						rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
++					#endif
++				}
++
++				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
++				if (cont)
++					op_ch = *(cont + 4);
++				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, NULL, &cont_len);
++				if (cont)
++					listen_ch = *(cont + 4);
++				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT, NULL, &cont_len);
++				if (cont)
++					intent = *cont;
++				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, NULL, &cont_len);
++				if (cont && cont_len == 6)
++					iaddr = cont;
++
++				if (nego_info->token != dialogToken)
++					rtw_wdev_nego_info_init(nego_info);
++
++				_rtw_memcpy(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN);
++				if (iaddr)
++					_rtw_memcpy(tx ? nego_info->iface_addr : nego_info->peer_iface_addr, iaddr, ETH_ALEN);
++				nego_info->active = tx ? 1 : 0;
++				nego_info->token = dialogToken;
++				nego_info->req_op_ch = op_ch;
++				nego_info->req_listen_ch = listen_ch;
++				nego_info->req_intent = intent;
++				nego_info->state = 0;
++
++				dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
++				RTW_INFO("RTW_%s:P2P_GO_NEGO_REQ, dialogToken=%d, intent:%u%s, listen_ch:%d, op_ch:%d, ch_list:%s"
++					, (tx == _TRUE) ? "Tx" : "Rx" , dialogToken , (intent >> 1) , intent & 0x1 ? "+" : "-" , listen_ch , op_ch , ch_list_buf);
++				if (iaddr)
++					_RTW_INFO(", iaddr:"MAC_FMT, MAC_ARG(iaddr));
++				_RTW_INFO("\n");
++
++				if (!tx) {
++					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
++					if (rtw_mi_check_status(padapter, MI_LINKED)
++					    && rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE
++					    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
++						RTW_INFO(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter));
++						rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);
++					}
++					#endif
++				}
++
++				break;
++			}
++			case P2P_GO_NEGO_RESP: {
++				struct rtw_wdev_nego_info *nego_info = &pwdev_priv->nego_info;
++
++				if (tx) {
++					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
++					if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
++						rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
++					#endif
++				}
++
++				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
++				if (cont)
++					op_ch = *(cont + 4);
++				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT, NULL, &cont_len);
++				if (cont)
++					intent = *cont;
++				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);
++				if (cont)
++					status = *cont;
++				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, NULL, &cont_len);
++				if (cont && cont_len == 6)
++					iaddr = cont;
++
++				if (nego_info->token == dialogToken && nego_info->state == 0
++					&& _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE
++				) {
++					if (iaddr)
++						_rtw_memcpy(tx ? nego_info->iface_addr : nego_info->peer_iface_addr, iaddr, ETH_ALEN);
++					nego_info->status = (status == -1) ? 0xff : status;
++					nego_info->rsp_op_ch = op_ch;
++					nego_info->rsp_intent = intent;
++					nego_info->state = 1;
++					if (status != 0)
++						nego_info->token = 0; /* init */
++				}
++
++				dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
++				RTW_INFO("RTW_%s:P2P_GO_NEGO_RESP, dialogToken=%d, intent:%u%s, status:%d, op_ch:%d, ch_list:%s"
++					, (tx == _TRUE) ? "Tx" : "Rx", dialogToken, (intent >> 1), intent & 0x1 ? "+" : "-", status, op_ch, ch_list_buf);
++				if (iaddr)
++					_RTW_INFO(", iaddr:"MAC_FMT, MAC_ARG(iaddr));
++				_RTW_INFO("\n");
++
++				if (!tx) {
++					pwdev_priv->provdisc_req_issued = _FALSE;
++					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
++					if (rtw_mi_check_status(padapter, MI_LINKED)
++					    && rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE
++					    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
++						RTW_INFO(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter));
++						rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);
++					}
++					#endif
++				}
++
++				break;
++			}
++			case P2P_GO_NEGO_CONF: {
++				struct rtw_wdev_nego_info *nego_info = &pwdev_priv->nego_info;
++				bool is_go = _FALSE;
++
++				if (tx) {
++					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
++					if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
++						rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
++					#endif
++				}
++
++				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
++				if (cont)
++					op_ch = *(cont + 4);
++				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);
++				if (cont)
++					status = *cont;
++
++				if (nego_info->token == dialogToken && nego_info->state == 1
++				    && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE
++				   ) {
++					nego_info->status = (status == -1) ? 0xff : status;
++					nego_info->conf_op_ch = (op_ch == -1) ? 0 : op_ch;
++					nego_info->state = 2;
++
++					if (status == 0) {
++						if (rtw_p2p_nego_intent_compare(nego_info->req_intent, nego_info->rsp_intent) ^ !tx)
++							is_go = _TRUE;
++					}
++
++					nego_info->token = 0; /* init */
++				}
++
++				dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
++				RTW_INFO("RTW_%s:P2P_GO_NEGO_CONF, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s\n"
++					, (tx == _TRUE) ? "Tx" : "Rx", dialogToken, status, op_ch, ch_list_buf);
++
++				if (!tx) {
++				}
++
++				break;
++			}
++			case P2P_INVIT_REQ: {
++				struct rtw_wdev_invit_info *invit_info = &pwdev_priv->invit_info;
++				int flags = -1;
++
++				if (tx) {
++					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
++					if (rtw_mi_check_status(padapter, MI_LINKED)
++					    && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
++						rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
++					#endif
++				}
++
++				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INVITATION_FLAGS, NULL, &cont_len);
++				if (cont)
++					flags = *cont;
++				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
++				if (cont)
++					op_ch = *(cont + 4);
++				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_BSSID, NULL, &cont_len);
++				if (cont && cont_len == 6)
++					gbssid = cont;
++
++				if (invit_info->token != dialogToken)
++					rtw_wdev_invit_info_init(invit_info);
++
++				_rtw_memcpy(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN);
++				if (gbssid)
++					_rtw_memcpy(invit_info->group_bssid, gbssid, ETH_ALEN);
++				invit_info->active = tx ? 1 : 0;
++				invit_info->token = dialogToken;
++				invit_info->flags = (flags == -1) ? 0x0 : flags;
++				invit_info->req_op_ch = op_ch;
++				invit_info->state = 0;
++
++				dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
++				RTW_INFO("RTW_%s:P2P_INVIT_REQ, dialogToken=%d, flags:0x%02x, op_ch:%d, ch_list:%s"
++					, (tx == _TRUE) ? "Tx" : "Rx", dialogToken, flags, op_ch, ch_list_buf);
++				if (gbssid)
++					_RTW_INFO(", gbssid:"MAC_FMT, MAC_ARG(gbssid));
++				_RTW_INFO("\n");
++
++				if (!tx) {
++					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
++					if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
++						#if defined(CONFIG_P2P_INVITE_IOT)
++						if (op_ch != -1 && rtw_chk_p2pie_op_ch_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) {
++							RTW_INFO(FUNC_ADPT_FMT" op_ch:%u has no intersect with buddy\n", FUNC_ADPT_ARG(padapter), op_ch);
++							rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);
++						} else
++						#endif
++						if (rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) {
++							RTW_INFO(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter));
++							rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);
++						}
++					}
++					#endif
++				}
++
++				break;
++			}
++			case P2P_INVIT_RESP: {
++				struct rtw_wdev_invit_info *invit_info = &pwdev_priv->invit_info;
++
++				if (tx) {
++					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
++					if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
++						rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
++					#endif
++				}
++
++				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);
++				if (cont) {
++					#ifdef CONFIG_P2P_INVITE_IOT
++					if (tx && *cont == 7) {
++						RTW_INFO("TX_P2P_INVITE_RESP, status is no common channel, change to unknown group\n");
++						*cont = 8; /* unknow group status */
++					}
++					#endif /* CONFIG_P2P_INVITE_IOT */
++					status = *cont;
++				}
++				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
++				if (cont)
++					op_ch = *(cont + 4);
++				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_BSSID, NULL, &cont_len);
++				if (cont && cont_len == 6)
++					gbssid = cont;
++
++				if (invit_info->token == dialogToken && invit_info->state == 0
++				    && _rtw_memcmp(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE
++				   ) {
++					invit_info->status = (status == -1) ? 0xff : status;
++					invit_info->rsp_op_ch = op_ch;
++					invit_info->state = 1;
++					invit_info->token = 0; /* init */
++				}
++
++				dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
++				RTW_INFO("RTW_%s:P2P_INVIT_RESP, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s"
++					, (tx == _TRUE) ? "Tx" : "Rx", dialogToken, status, op_ch, ch_list_buf);
++				if (gbssid)
++					_RTW_INFO(", gbssid:"MAC_FMT, MAC_ARG(gbssid));
++				_RTW_INFO("\n");
++
++				if (!tx) {
++				}
++
++				break;
++			}
++			case P2P_DEVDISC_REQ:
++				RTW_INFO("RTW_%s:P2P_DEVDISC_REQ, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
++				break;
++			case P2P_DEVDISC_RESP:
++				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);
++				RTW_INFO("RTW_%s:P2P_DEVDISC_RESP, dialogToken=%d, status:%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken, cont ? *cont : -1);
++				break;
++			case P2P_PROVISION_DISC_REQ: {
++				size_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr);
++				u8 *p2p_ie;
++				uint p2p_ielen = 0;
++				uint contentlen = 0;
++
++				RTW_INFO("RTW_%s:P2P_PROVISION_DISC_REQ, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
++
++				/* if(tx) */
++				{
++					pwdev_priv->provdisc_req_issued = _FALSE;
++
++					p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen);
++					if (p2p_ie) {
++
++						if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, NULL, &contentlen)) {
++							pwdev_priv->provdisc_req_issued = _FALSE;/* case: p2p_client join p2p GO */
++						} else {
++							#ifdef CONFIG_DEBUG_CFG80211
++							RTW_INFO("provdisc_req_issued is _TRUE\n");
++							#endif /*CONFIG_DEBUG_CFG80211*/
++							pwdev_priv->provdisc_req_issued = _TRUE;/* case: p2p_devices connection before Nego req. */
++						}
++
++					}
++				}
++			}
++			break;
++			case P2P_PROVISION_DISC_RESP:
++				RTW_INFO("RTW_%s:P2P_PROVISION_DISC_RESP, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
++				break;
++			default:
++				RTW_INFO("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", OUI_Subtype, dialogToken);
++				break;
++			}
++
++		}
++
++	} else if (category == RTW_WLAN_CATEGORY_P2P) {
++		OUI_Subtype = frame_body[5];
++		dialogToken = frame_body[6];
++
++		#ifdef CONFIG_DEBUG_CFG80211
++		RTW_INFO("ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n",
++			cpu_to_be32(*((u32 *)(frame_body + 1))), OUI_Subtype, dialogToken);
++		#endif
++
++		is_p2p_frame = OUI_Subtype;
++
++		switch (OUI_Subtype) {
++		case P2P_NOTICE_OF_ABSENCE:
++			RTW_INFO("RTW_%s:P2P_NOTICE_OF_ABSENCE, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
++			break;
++		case P2P_PRESENCE_REQUEST:
++			RTW_INFO("RTW_%s:P2P_PRESENCE_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
++			break;
++		case P2P_PRESENCE_RESPONSE:
++			RTW_INFO("RTW_%s:P2P_PRESENCE_RESPONSE, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
++			break;
++		case P2P_GO_DISC_REQUEST:
++			RTW_INFO("RTW_%s:P2P_GO_DISC_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
++			break;
++		default:
++			RTW_INFO("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", OUI_Subtype, dialogToken);
++			break;
++		}
++
++	}
++
++	return is_p2p_frame;
++}
++
++void rtw_init_cfg80211_wifidirect_info(_adapter	*padapter)
++{
++	struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;
++
++	_rtw_memset(pcfg80211_wdinfo, 0x00, sizeof(struct cfg80211_wifidirect_info));
++
++	rtw_init_timer(&pcfg80211_wdinfo->remain_on_ch_timer, padapter, ro_ch_timer_process, padapter);
++}
++#endif /* CONFIG_IOCTL_CFG80211	 */
++
++s32 p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf)
++{
++	int ret = H2C_SUCCESS;
++
++	switch (intCmdType) {
++	case P2P_FIND_PHASE_WK:
++		find_phase_handler(padapter);
++		break;
++
++	case P2P_RESTORE_STATE_WK:
++		restore_p2p_state_handler(padapter);
++		break;
++
++	case P2P_PRE_TX_PROVDISC_PROCESS_WK:
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_check_status(padapter, MI_LINKED))
++			p2p_concurrent_handler(padapter);
++		else
++			pre_tx_provdisc_handler(padapter);
++#else
++		pre_tx_provdisc_handler(padapter);
++#endif
++		break;
++
++	case P2P_PRE_TX_INVITEREQ_PROCESS_WK:
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_check_status(padapter, MI_LINKED))
++			p2p_concurrent_handler(padapter);
++		else
++			pre_tx_invitereq_handler(padapter);
++#else
++		pre_tx_invitereq_handler(padapter);
++#endif
++		break;
++
++	case P2P_PRE_TX_NEGOREQ_PROCESS_WK:
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_check_status(padapter, MI_LINKED))
++			p2p_concurrent_handler(padapter);
++		else
++			pre_tx_negoreq_handler(padapter);
++#else
++		pre_tx_negoreq_handler(padapter);
++#endif
++		break;
++
++#ifdef CONFIG_CONCURRENT_MODE
++	case P2P_AP_P2P_CH_SWITCH_PROCESS_WK:
++		p2p_concurrent_handler(padapter);
++		break;
++#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++	case P2P_RO_CH_WK:
++		ret = ro_ch_handler(padapter, buf);
++		break;
++	case P2P_CANCEL_RO_CH_WK:
++		ret = cancel_ro_ch_handler(padapter, buf);
++		break;
++#endif
++
++	default:
++		rtw_warn_on(1);
++		break;
++	}
++
++	return ret;
++}
++
++int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength)
++{
++	int ret = _TRUE;
++	u8 *ies;
++	u32 ies_len;
++	u8 *p2p_ie;
++	u32	p2p_ielen = 0;
++	u8	p2p_attr[MAX_P2P_IE_LEN] = { 0x00 };/* NoA length should be n*(13) + 2 */
++	u32	attr_contentlen = 0;
++
++
++
++	if (IELength <= _BEACON_IE_OFFSET_)
++		return ret;
++
++	ies = IEs + _BEACON_IE_OFFSET_;
++	ies_len = IELength - _BEACON_IE_OFFSET_;
++
++	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
++
++	while (p2p_ie) {
++		/* Get P2P Manageability IE. */
++		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_MANAGEABILITY, p2p_attr, &attr_contentlen)) {
++			if ((p2p_attr[0] & (BIT(0) | BIT(1))) == 0x01)
++				ret = _FALSE;
++			break;
++		}
++		/* Get the next P2P IE */
++		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
++	}
++
++	return ret;
++}
++
++#ifdef CONFIG_P2P_PS
++void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength)
++{
++	u8 *ies;
++	u32 ies_len;
++	u8 *p2p_ie;
++	u32	p2p_ielen = 0;
++	u8 *noa_attr; /* NoA length should be n*(13) + 2 */
++	u32	attr_contentlen = 0;
++
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++	u8	find_p2p = _FALSE, find_p2p_ps = _FALSE;
++	u8	noa_offset, noa_num, noa_index;
++
++
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++		return;
++#ifdef CONFIG_CONCURRENT_MODE
++#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
++	if (padapter->hw_port != HW_PORT0)
++		return;
++#endif
++#endif
++	if (IELength <= _BEACON_IE_OFFSET_)
++		return;
++
++	ies = IEs + _BEACON_IE_OFFSET_;
++	ies_len = IELength - _BEACON_IE_OFFSET_;
++
++	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
++
++	while (p2p_ie) {
++		find_p2p = _TRUE;
++		/* Get Notice of Absence IE. */
++		noa_attr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_NOA, NULL, &attr_contentlen);
++		if (noa_attr) {
++			find_p2p_ps = _TRUE;
++			noa_index = noa_attr[0];
++
++			if ((pwdinfo->p2p_ps_mode == P2P_PS_NONE) ||
++			    (noa_index != pwdinfo->noa_index)) { /* if index change, driver should reconfigure related setting. */
++				pwdinfo->noa_index = noa_index;
++				pwdinfo->opp_ps = noa_attr[1] >> 7;
++				if (pwdinfo->opp_ps != 1)
++					pwdinfo->ctwindow = 0;
++				else
++					pwdinfo->ctwindow = noa_attr[1] & 0x7F;
++				noa_offset = 2;
++				noa_num = 0;
++				/* NoA length should be n*(13) + 2 */
++				if (attr_contentlen > 2 && (attr_contentlen - 2) % 13 == 0) {
++					while (noa_offset < attr_contentlen && noa_num < P2P_MAX_NOA_NUM) {
++						/* _rtw_memcpy(&wifidirect_info->noa_count[noa_num], &noa_attr[noa_offset], 1); */
++						pwdinfo->noa_count[noa_num] = noa_attr[noa_offset];
++						noa_offset += 1;
++
++						_rtw_memcpy(&pwdinfo->noa_duration[noa_num], &noa_attr[noa_offset], 4);
++						noa_offset += 4;
++
++						_rtw_memcpy(&pwdinfo->noa_interval[noa_num], &noa_attr[noa_offset], 4);
++						noa_offset += 4;
++
++						_rtw_memcpy(&pwdinfo->noa_start_time[noa_num], &noa_attr[noa_offset], 4);
++						noa_offset += 4;
++
++						noa_num++;
++					}
++				}
++				pwdinfo->noa_num = noa_num;
++
++				if (pwdinfo->opp_ps == 1) {
++					pwdinfo->p2p_ps_mode = P2P_PS_CTWINDOW;
++					/* driver should wait LPS for entering CTWindow */
++					if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE)
++						p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1);
++				} else if (pwdinfo->noa_num > 0) {
++					pwdinfo->p2p_ps_mode = P2P_PS_NOA;
++					p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1);
++				} else if (pwdinfo->p2p_ps_mode > P2P_PS_NONE)
++					p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1);
++			}
++
++			break; /* find target, just break. */
++		}
++
++		/* Get the next P2P IE */
++		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
++
++	}
++
++	if (find_p2p == _TRUE) {
++		if ((pwdinfo->p2p_ps_mode > P2P_PS_NONE) && (find_p2p_ps == _FALSE))
++			p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1);
++	}
++
++}
++
++void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state)
++{
++	struct pwrctrl_priv		*pwrpriv = adapter_to_pwrctl(padapter);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++	u32 ps_deny = 0;
++
++	/* Pre action for p2p state */
++	switch (p2p_ps_state) {
++	case P2P_PS_DISABLE:
++		pwdinfo->p2p_ps_state = p2p_ps_state;
++
++		rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state));
++
++#ifdef CONFIG_LPS
++		if (pwdinfo->opp_ps == 1) {
++			if (pwrpriv->smart_ps == 0) {
++				pwrpriv->smart_ps = 2;
++				if (pwrpriv->pwr_mode != PS_MODE_ACTIVE)
++					rtw_exec_lps(padapter, pwrpriv->pwr_mode);
++			}
++		}
++#endif /* CONFIG_LPS */
++
++		pwdinfo->noa_index = 0;
++		pwdinfo->ctwindow = 0;
++		pwdinfo->opp_ps = 0;
++		pwdinfo->noa_num = 0;
++		pwdinfo->p2p_ps_mode = P2P_PS_NONE;
++
++		break;
++	case P2P_PS_ENABLE:
++		_enter_pwrlock(&adapter_to_pwrctl(padapter)->lock);
++		ps_deny = rtw_ps_deny_get(padapter);
++		_exit_pwrlock(&adapter_to_pwrctl(padapter)->lock);
++
++		if ((ps_deny & (PS_DENY_SCAN | PS_DENY_JOIN))
++			|| rtw_mi_check_fwstate(padapter, (WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING))) {
++			pwdinfo->p2p_ps_mode = P2P_PS_NONE;
++			RTW_DBG(FUNC_ADPT_FMT" Block P2P PS under site survey or LINKING\n", FUNC_ADPT_ARG(padapter));
++			return;
++		}
++		if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) {
++#ifdef CONFIG_MCC_MODE
++			if (MCC_EN(padapter)) {
++				if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
++					RTW_INFO("P2P PS enble under MCC\n");
++					rtw_warn_on(1);
++				}
++
++			}
++#endif /* CONFIG_MCC_MODE */
++			pwdinfo->p2p_ps_state = p2p_ps_state;
++
++#ifdef CONFIG_LPS
++			if (pwdinfo->ctwindow > 0) {
++				if (pwrpriv->smart_ps != 0) {
++					pwrpriv->smart_ps = 0;
++					RTW_INFO("%s(): Enter CTW, change SmartPS\n", __FUNCTION__);
++					if (pwrpriv->pwr_mode != PS_MODE_ACTIVE)
++						rtw_exec_lps(padapter, pwrpriv->pwr_mode);
++				}
++			}
++#endif /* CONFIG_LPS */
++
++			rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state));
++		}
++		break;
++	case P2P_PS_SCAN:
++	case P2P_PS_SCAN_DONE:
++	case P2P_PS_ALLSTASLEEP:
++		if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) {
++			pwdinfo->p2p_ps_state = p2p_ps_state;
++			rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state));
++		}
++		break;
++	default:
++		break;
++	}
++
++#ifdef CONFIG_MCC_MODE
++	rtw_hal_mcc_process_noa(padapter);
++#endif /* CONFIG_MCC_MODE */
++}
++
++u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue)
++{
++	struct cmd_obj	*ph2c;
++	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
++	u8	res = _SUCCESS;
++
++
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
++#ifdef CONFIG_CONCURRENT_MODE
++#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
++	    || (padapter->hw_port != HW_PORT0)
++#endif
++#endif
++	   )
++		return res;
++
++	if (enqueue) {
++		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++		if (ph2c == NULL) {
++			res = _FAIL;
++			goto exit;
++		}
++
++		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++		if (pdrvextra_cmd_parm == NULL) {
++			rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++			res = _FAIL;
++			goto exit;
++		}
++
++		pdrvextra_cmd_parm->ec_id = P2P_PS_WK_CID;
++		pdrvextra_cmd_parm->type = p2p_ps_state;
++		pdrvextra_cmd_parm->size = 0;
++		pdrvextra_cmd_parm->pbuf = NULL;
++
++		init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++	} else
++		p2p_ps_wk_hdl(padapter, p2p_ps_state);
++
++exit:
++
++
++	return res;
++
++}
++#endif /* CONFIG_P2P_PS */
++
++static void reset_ch_sitesurvey_timer_process(void *FunctionContext)
++{
++	_adapter *adapter = (_adapter *)FunctionContext;
++	struct	wifidirect_info		*pwdinfo = &adapter->wdinfo;
++
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++		return;
++
++	RTW_INFO("[%s] In\n", __FUNCTION__);
++	/*	Reset the operation channel information */
++	pwdinfo->rx_invitereq_info.operation_ch[0] = 0;
++#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
++	pwdinfo->rx_invitereq_info.operation_ch[1] = 0;
++	pwdinfo->rx_invitereq_info.operation_ch[2] = 0;
++	pwdinfo->rx_invitereq_info.operation_ch[3] = 0;
++#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
++	pwdinfo->rx_invitereq_info.scan_op_ch_only = 0;
++}
++
++static void reset_ch_sitesurvey_timer_process2(void *FunctionContext)
++{
++	_adapter *adapter = (_adapter *)FunctionContext;
++	struct	wifidirect_info		*pwdinfo = &adapter->wdinfo;
++
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++		return;
++
++	RTW_INFO("[%s] In\n", __FUNCTION__);
++	/*	Reset the operation channel information */
++	pwdinfo->p2p_info.operation_ch[0] = 0;
++#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
++	pwdinfo->p2p_info.operation_ch[1] = 0;
++	pwdinfo->p2p_info.operation_ch[2] = 0;
++	pwdinfo->p2p_info.operation_ch[3] = 0;
++#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
++	pwdinfo->p2p_info.scan_op_ch_only = 0;
++}
++
++static void restore_p2p_state_timer_process(void *FunctionContext)
++{
++	_adapter *adapter = (_adapter *)FunctionContext;
++	struct	wifidirect_info		*pwdinfo = &adapter->wdinfo;
++
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++		return;
++
++	p2p_protocol_wk_cmd(adapter, P2P_RESTORE_STATE_WK);
++}
++
++static void pre_tx_scan_timer_process(void *FunctionContext)
++{
++	_adapter							*adapter = (_adapter *) FunctionContext;
++	struct	wifidirect_info				*pwdinfo = &adapter->wdinfo;
++	_irqL							irqL;
++	struct mlme_priv					*pmlmepriv = &adapter->mlmepriv;
++
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++		return;
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++
++
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) {
++		if (_TRUE == pwdinfo->tx_prov_disc_info.benable) {	/*	the provision discovery request frame is trigger to send or not */
++			p2p_protocol_wk_cmd(adapter, P2P_PRE_TX_PROVDISC_PROCESS_WK);
++			/* issue_probereq_p2p(adapter, NULL); */
++			/* _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); */
++		}
++	} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) {
++		if (_TRUE == pwdinfo->nego_req_info.benable)
++			p2p_protocol_wk_cmd(adapter, P2P_PRE_TX_NEGOREQ_PROCESS_WK);
++	} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ)) {
++		if (_TRUE == pwdinfo->invitereq_info.benable)
++			p2p_protocol_wk_cmd(adapter, P2P_PRE_TX_INVITEREQ_PROCESS_WK);
++	} else
++		RTW_INFO("[%s] p2p_state is %d, ignore!!\n", __FUNCTION__, rtw_p2p_state(pwdinfo));
++
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++}
++
++static void find_phase_timer_process(void *FunctionContext)
++{
++	_adapter *adapter = (_adapter *)FunctionContext;
++	struct	wifidirect_info		*pwdinfo = &adapter->wdinfo;
++
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++		return;
++
++	adapter->wdinfo.find_phase_state_exchange_cnt++;
++
++	p2p_protocol_wk_cmd(adapter, P2P_FIND_PHASE_WK);
++}
++
++#ifdef CONFIG_CONCURRENT_MODE
++void ap_p2p_switch_timer_process(void *FunctionContext)
++{
++	_adapter *adapter = (_adapter *)FunctionContext;
++	struct	wifidirect_info		*pwdinfo = &adapter->wdinfo;
++#ifdef CONFIG_IOCTL_CFG80211
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
++#endif
++
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++		return;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	ATOMIC_SET(&pwdev_priv->switch_ch_to, 1);
++#endif
++
++	p2p_protocol_wk_cmd(adapter, P2P_AP_P2P_CH_SWITCH_PROCESS_WK);
++}
++#endif
++
++void reset_global_wifidirect_info(_adapter *padapter)
++{
++	struct wifidirect_info	*pwdinfo;
++
++	pwdinfo = &padapter->wdinfo;
++	pwdinfo->persistent_supported = 0;
++	pwdinfo->session_available = _TRUE;
++	rtw_tdls_wfd_enable(padapter, 0);
++	pwdinfo->wfd_tdls_weaksec = _TRUE;
++}
++
++#ifdef CONFIG_WFD
++int rtw_init_wifi_display_info(_adapter *padapter)
++{
++	int	res = _SUCCESS;
++	struct wifi_display_info *pwfd_info = &padapter->wfd_info;
++
++	/* Used in P2P and TDLS */
++	pwfd_info->init_rtsp_ctrlport = 554;
++#ifdef CONFIG_IOCTL_CFG80211
++	pwfd_info->rtsp_ctrlport = 0;
++#else
++	pwfd_info->rtsp_ctrlport = pwfd_info->init_rtsp_ctrlport; /* set non-zero value for legacy wfd */
++#endif
++	pwfd_info->tdls_rtsp_ctrlport = 0;
++	pwfd_info->peer_rtsp_ctrlport = 0;	/*	Reset to 0 */
++	pwfd_info->wfd_enable = _FALSE;
++	pwfd_info->wfd_device_type = WFD_DEVINFO_PSINK;
++	pwfd_info->scan_result_type = SCAN_RESULT_P2P_ONLY;
++
++	/* Used in P2P */
++	pwfd_info->peer_session_avail = _TRUE;
++	pwfd_info->wfd_pc = _FALSE;
++
++	/* Used in TDLS */
++	_rtw_memset(pwfd_info->ip_address, 0x00, 4);
++	_rtw_memset(pwfd_info->peer_ip_address, 0x00, 4);
++	return res;
++
++}
++
++inline void rtw_wfd_enable(_adapter *adapter, bool on)
++{
++	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
++
++	if (on) {
++		wfdinfo->rtsp_ctrlport = wfdinfo->init_rtsp_ctrlport;
++		wfdinfo->wfd_enable = _TRUE;
++
++	} else {
++		wfdinfo->wfd_enable = _FALSE;
++		wfdinfo->rtsp_ctrlport = 0;
++	}
++}
++
++inline void rtw_wfd_set_ctrl_port(_adapter *adapter, u16 port)
++{
++	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
++
++	wfdinfo->init_rtsp_ctrlport = port;
++	if (wfdinfo->wfd_enable == _TRUE)
++		wfdinfo->rtsp_ctrlport = port;
++	if (adapter->wdinfo.wfd_tdls_enable == 1)
++		wfdinfo->tdls_rtsp_ctrlport = port;
++}
++
++inline void rtw_tdls_wfd_enable(_adapter *adapter, bool on)
++{
++	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
++
++	if (on) {
++		wfdinfo->tdls_rtsp_ctrlport = wfdinfo->init_rtsp_ctrlport;
++		adapter->wdinfo.wfd_tdls_enable = 1;
++
++	} else {
++		adapter->wdinfo.wfd_tdls_enable = 0;
++		wfdinfo->tdls_rtsp_ctrlport = 0;
++	}
++}
++
++u32 rtw_append_beacon_wfd_ie(_adapter *adapter, u8 *pbuf)
++{
++	struct wifidirect_info *wdinfo = &adapter->wdinfo;
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++	u8 build_ie_by_self = 0;
++	u32 len = 0;
++
++	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
++		goto exit;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (_TRUE == wdinfo->wfd_info->wfd_enable)
++#endif
++		build_ie_by_self = 1;
++
++	if (build_ie_by_self)
++		len = build_beacon_wfd_ie(wdinfo, pbuf);
++#ifdef CONFIG_IOCTL_CFG80211
++	else if (mlme->wfd_beacon_ie && mlme->wfd_beacon_ie_len > 0) {
++		len = mlme->wfd_beacon_ie_len;
++		_rtw_memcpy(pbuf, mlme->wfd_beacon_ie, len);
++	}
++#endif
++
++exit:
++	return len;
++}
++
++u32 rtw_append_probe_req_wfd_ie(_adapter *adapter, u8 *pbuf)
++{
++	struct wifidirect_info *wdinfo = &adapter->wdinfo;
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++	u8 build_ie_by_self = 0;
++	u32 len = 0;
++
++	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
++		goto exit;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (_TRUE == wdinfo->wfd_info->wfd_enable)
++#endif
++		build_ie_by_self = 1;
++
++	if (build_ie_by_self)
++		len = build_probe_req_wfd_ie(wdinfo, pbuf);
++#ifdef CONFIG_IOCTL_CFG80211
++	else if (mlme->wfd_probe_req_ie && mlme->wfd_probe_req_ie_len > 0) {
++		len = mlme->wfd_probe_req_ie_len;
++		_rtw_memcpy(pbuf, mlme->wfd_probe_req_ie, len);
++	}
++#endif
++
++exit:
++	return len;
++}
++
++u32 rtw_append_probe_resp_wfd_ie(_adapter *adapter, u8 *pbuf)
++{
++	struct wifidirect_info *wdinfo = &adapter->wdinfo;
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++	u8 build_ie_by_self = 0;
++	u32 len = 0;
++
++	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
++		goto exit;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (_TRUE == wdinfo->wfd_info->wfd_enable)
++#endif
++		build_ie_by_self = 1;
++
++	if (build_ie_by_self)
++		len = build_probe_resp_wfd_ie(wdinfo, pbuf, 0);
++#ifdef CONFIG_IOCTL_CFG80211
++	else if (mlme->wfd_probe_resp_ie && mlme->wfd_probe_resp_ie_len > 0) {
++		len = mlme->wfd_probe_resp_ie_len;
++		_rtw_memcpy(pbuf, mlme->wfd_probe_resp_ie, len);
++	}
++#endif
++
++exit:
++	return len;
++}
++
++u32 rtw_append_assoc_req_wfd_ie(_adapter *adapter, u8 *pbuf)
++{
++	struct wifidirect_info *wdinfo = &adapter->wdinfo;
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++	u8 build_ie_by_self = 0;
++	u32 len = 0;
++
++	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
++		goto exit;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (_TRUE == wdinfo->wfd_info->wfd_enable)
++#endif
++		build_ie_by_self = 1;
++
++	if (build_ie_by_self)
++		len = build_assoc_req_wfd_ie(wdinfo, pbuf);
++#ifdef CONFIG_IOCTL_CFG80211
++	else if (mlme->wfd_assoc_req_ie && mlme->wfd_assoc_req_ie_len > 0) {
++		len = mlme->wfd_assoc_req_ie_len;
++		_rtw_memcpy(pbuf, mlme->wfd_assoc_req_ie, len);
++	}
++#endif
++
++exit:
++	return len;
++}
++
++u32 rtw_append_assoc_resp_wfd_ie(_adapter *adapter, u8 *pbuf)
++{
++	struct wifidirect_info *wdinfo = &adapter->wdinfo;
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++	u8 build_ie_by_self = 0;
++	u32 len = 0;
++
++	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
++		goto exit;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (_TRUE == wdinfo->wfd_info->wfd_enable)
++#endif
++		build_ie_by_self = 1;
++
++	if (build_ie_by_self)
++		len = build_assoc_resp_wfd_ie(wdinfo, pbuf);
++#ifdef CONFIG_IOCTL_CFG80211
++	else if (mlme->wfd_assoc_resp_ie && mlme->wfd_assoc_resp_ie_len > 0) {
++		len = mlme->wfd_assoc_resp_ie_len;
++		_rtw_memcpy(pbuf, mlme->wfd_assoc_resp_ie, len);
++	}
++#endif
++
++exit:
++	return len;
++}
++
++#endif /* CONFIG_WFD */
++
++void rtw_init_wifidirect_timers(_adapter *padapter)
++{
++	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++
++	rtw_init_timer(&pwdinfo->find_phase_timer, padapter, find_phase_timer_process, padapter);
++	rtw_init_timer(&pwdinfo->restore_p2p_state_timer, padapter, restore_p2p_state_timer_process, padapter);
++	rtw_init_timer(&pwdinfo->pre_tx_scan_timer, padapter, pre_tx_scan_timer_process, padapter);
++	rtw_init_timer(&pwdinfo->reset_ch_sitesurvey, padapter, reset_ch_sitesurvey_timer_process, padapter);
++	rtw_init_timer(&pwdinfo->reset_ch_sitesurvey2, padapter, reset_ch_sitesurvey_timer_process2, padapter);
++#ifdef CONFIG_CONCURRENT_MODE
++	rtw_init_timer(&pwdinfo->ap_p2p_switch_timer, padapter, ap_p2p_switch_timer_process, padapter);
++#endif
++}
++
++void rtw_init_wifidirect_addrs(_adapter *padapter, u8 *dev_addr, u8 *iface_addr)
++{
++#ifdef CONFIG_P2P
++	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++
++	/*init device&interface address */
++	if (dev_addr)
++		_rtw_memcpy(pwdinfo->device_addr, dev_addr, ETH_ALEN);
++	if (iface_addr)
++		_rtw_memcpy(pwdinfo->interface_addr, iface_addr, ETH_ALEN);
++#endif
++}
++
++void init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role)
++{
++	struct wifidirect_info	*pwdinfo;
++#ifdef CONFIG_WFD
++	struct wifi_display_info	*pwfd_info = &padapter->wfd_info;
++#endif
++	pwdinfo = &padapter->wdinfo;
++
++	pwdinfo->padapter = padapter;
++
++	/*	1, 6, 11 are the social channel defined in the WiFi Direct specification. */
++	pwdinfo->social_chan[0] = 1;
++	pwdinfo->social_chan[1] = 6;
++	pwdinfo->social_chan[2] = 11;
++	pwdinfo->social_chan[3] = 0;	/*	channel 0 for scanning ending in site survey function. */
++
++	if (role != P2P_ROLE_DISABLE
++		&& pwdinfo->driver_interface != DRIVER_CFG80211
++	) {
++		#ifdef CONFIG_CONCURRENT_MODE
++		u8 union_ch = 0;
++
++		if (rtw_mi_check_status(padapter, MI_LINKED))
++			union_ch = rtw_mi_get_union_chan(padapter);
++
++		if (union_ch != 0 &&
++			(union_ch == 1 || union_ch == 6 || union_ch == 11)
++		) {
++			/* Use the AP's channel as the listen channel */
++			/* This will avoid the channel switch between AP's channel and listen channel */
++			pwdinfo->listen_channel = union_ch;
++		} else
++		#endif /* CONFIG_CONCURRENT_MODE */
++		{
++			/* Use the channel 11 as the listen channel */
++			pwdinfo->listen_channel = 11;
++		}
++	}
++
++	if (role == P2P_ROLE_DEVICE) {
++		rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_check_status(padapter, MI_LINKED))
++			rtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE);
++		else
++#endif
++			rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
++
++		pwdinfo->intent = 1;
++		rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_LISTEN);
++	} else if (role == P2P_ROLE_CLIENT) {
++		rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
++		pwdinfo->intent = 1;
++		rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
++	} else if (role == P2P_ROLE_GO) {
++		rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
++		pwdinfo->intent = 15;
++		rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
++	}
++
++	/*	Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 )	 */
++	pwdinfo->support_rate[0] = 0x8c;	/*	6(B) */
++	pwdinfo->support_rate[1] = 0x92;	/*	9(B) */
++	pwdinfo->support_rate[2] = 0x18;	/*	12 */
++	pwdinfo->support_rate[3] = 0x24;	/*	18 */
++	pwdinfo->support_rate[4] = 0x30;	/*	24 */
++	pwdinfo->support_rate[5] = 0x48;	/*	36 */
++	pwdinfo->support_rate[6] = 0x60;	/*	48 */
++	pwdinfo->support_rate[7] = 0x6c;	/*	54 */
++
++	_rtw_memcpy((void *) pwdinfo->p2p_wildcard_ssid, "DIRECT-", 7);
++
++	_rtw_memset(pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN);
++	pwdinfo->device_name_len = 0;
++
++	_rtw_memset(&pwdinfo->invitereq_info, 0x00, sizeof(struct tx_invite_req_info));
++	pwdinfo->invitereq_info.token = 3;	/*	Token used for P2P invitation request frame. */
++
++	_rtw_memset(&pwdinfo->inviteresp_info, 0x00, sizeof(struct tx_invite_resp_info));
++	pwdinfo->inviteresp_info.token = 0;
++
++	pwdinfo->profileindex = 0;
++	_rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM);
++
++	rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);
++
++	pwdinfo->listen_dwell = (u8)((rtw_get_current_time() % 3) + 1);
++	/* RTW_INFO( "[%s] listen_dwell time is %d00ms\n", __FUNCTION__, pwdinfo->listen_dwell ); */
++
++	_rtw_memset(&pwdinfo->tx_prov_disc_info, 0x00, sizeof(struct tx_provdisc_req_info));
++	pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_NONE;
++
++	_rtw_memset(&pwdinfo->nego_req_info, 0x00, sizeof(struct tx_nego_req_info));
++
++	pwdinfo->device_password_id_for_nego = WPS_DPID_PBC;
++	pwdinfo->negotiation_dialog_token = 1;
++
++	_rtw_memset(pwdinfo->nego_ssid, 0x00, WLAN_SSID_MAXLEN);
++	pwdinfo->nego_ssidlen = 0;
++
++	pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO;
++#ifdef CONFIG_WFD
++	pwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY  | WPS_CONFIG_METHOD_PBC;
++	pwdinfo->wfd_info = pwfd_info;
++#else
++	pwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY | WPS_CONFIG_METHOD_PBC | WPS_CONFIG_METHOD_KEYPAD;
++#endif /* CONFIG_WFD */
++	pwdinfo->channel_list_attr_len = 0;
++	_rtw_memset(pwdinfo->channel_list_attr, 0x00, 100);
++
++	_rtw_memset(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, 0x00, 4);
++	_rtw_memset(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, '0', 3);
++	_rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info));
++#ifdef CONFIG_CONCURRENT_MODE
++#ifdef CONFIG_IOCTL_CFG80211
++	pwdinfo->ext_listen_interval = 1000; /* The interval to be available with legacy AP during p2p0-find/scan */
++	pwdinfo->ext_listen_period = 3000; /* The time period to be available for P2P during nego */
++
++	pwdinfo->min_home_dur = 1500; 		/* min duration for traffic, home_time */
++	pwdinfo->max_away_dur = 250;		/* max acceptable away duration, home_away_time */
++#else /* !CONFIG_IOCTL_CFG80211 */
++	/* pwdinfo->ext_listen_interval = 3000; */
++	/* pwdinfo->ext_listen_period = 400; */
++	pwdinfo->ext_listen_interval = 1000;
++	pwdinfo->ext_listen_period = 1000;
++#endif /* !CONFIG_IOCTL_CFG80211 */
++#endif
++
++	/* Commented by Kurt 20130319
++	 * For WiDi purpose: Use CFG80211 interface but controled WFD/RDS frame by driver itself. */
++#ifdef CONFIG_IOCTL_CFG80211
++	pwdinfo->driver_interface = DRIVER_CFG80211;
++#else
++	pwdinfo->driver_interface = DRIVER_WEXT;
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++	pwdinfo->wfd_tdls_enable = 0;
++	_rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN);
++	_rtw_memset(pwdinfo->p2p_peer_device_addr, 0x00, ETH_ALEN);
++
++	pwdinfo->rx_invitereq_info.operation_ch[0] = 0;
++	pwdinfo->rx_invitereq_info.operation_ch[1] = 0;	/*	Used to indicate the scan end in site survey function */
++#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
++	pwdinfo->rx_invitereq_info.operation_ch[2] = 0;
++	pwdinfo->rx_invitereq_info.operation_ch[3] = 0;
++	pwdinfo->rx_invitereq_info.operation_ch[4] = 0;
++#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
++	pwdinfo->rx_invitereq_info.scan_op_ch_only = 0;
++	pwdinfo->p2p_info.operation_ch[0] = 0;
++	pwdinfo->p2p_info.operation_ch[1] = 0;			/*	Used to indicate the scan end in site survey function */
++#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
++	pwdinfo->p2p_info.operation_ch[2] = 0;
++	pwdinfo->p2p_info.operation_ch[3] = 0;
++	pwdinfo->p2p_info.operation_ch[4] = 0;
++#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
++	pwdinfo->p2p_info.scan_op_ch_only = 0;
++}
++
++void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role)
++{
++	if (wdinfo->role != role) {
++		wdinfo->role = role;
++		rtw_mi_update_iface_status(&(wdinfo->padapter->mlmepriv), 0);
++	}
++}
++
++#ifdef CONFIG_DBG_P2P
++
++/**
++ * rtw_p2p_role_txt - Get the p2p role name as a text string
++ * @role: P2P role
++ * Returns: The state name as a printable text string
++ */
++const char *rtw_p2p_role_txt(enum P2P_ROLE role)
++{
++	switch (role) {
++	case P2P_ROLE_DISABLE:
++		return "P2P_ROLE_DISABLE";
++	case P2P_ROLE_DEVICE:
++		return "P2P_ROLE_DEVICE";
++	case P2P_ROLE_CLIENT:
++		return "P2P_ROLE_CLIENT";
++	case P2P_ROLE_GO:
++		return "P2P_ROLE_GO";
++	default:
++		return "UNKNOWN";
++	}
++}
++
++/**
++ * rtw_p2p_state_txt - Get the p2p state name as a text string
++ * @state: P2P state
++ * Returns: The state name as a printable text string
++ */
++const char *rtw_p2p_state_txt(enum P2P_STATE state)
++{
++	switch (state) {
++	case P2P_STATE_NONE:
++		return "P2P_STATE_NONE";
++	case P2P_STATE_IDLE:
++		return "P2P_STATE_IDLE";
++	case P2P_STATE_LISTEN:
++		return "P2P_STATE_LISTEN";
++	case P2P_STATE_SCAN:
++		return "P2P_STATE_SCAN";
++	case P2P_STATE_FIND_PHASE_LISTEN:
++		return "P2P_STATE_FIND_PHASE_LISTEN";
++	case P2P_STATE_FIND_PHASE_SEARCH:
++		return "P2P_STATE_FIND_PHASE_SEARCH";
++	case P2P_STATE_TX_PROVISION_DIS_REQ:
++		return "P2P_STATE_TX_PROVISION_DIS_REQ";
++	case P2P_STATE_RX_PROVISION_DIS_RSP:
++		return "P2P_STATE_RX_PROVISION_DIS_RSP";
++	case P2P_STATE_RX_PROVISION_DIS_REQ:
++		return "P2P_STATE_RX_PROVISION_DIS_REQ";
++	case P2P_STATE_GONEGO_ING:
++		return "P2P_STATE_GONEGO_ING";
++	case P2P_STATE_GONEGO_OK:
++		return "P2P_STATE_GONEGO_OK";
++	case P2P_STATE_GONEGO_FAIL:
++		return "P2P_STATE_GONEGO_FAIL";
++	case P2P_STATE_RECV_INVITE_REQ_MATCH:
++		return "P2P_STATE_RECV_INVITE_REQ_MATCH";
++	case P2P_STATE_PROVISIONING_ING:
++		return "P2P_STATE_PROVISIONING_ING";
++	case P2P_STATE_PROVISIONING_DONE:
++		return "P2P_STATE_PROVISIONING_DONE";
++	case P2P_STATE_TX_INVITE_REQ:
++		return "P2P_STATE_TX_INVITE_REQ";
++	case P2P_STATE_RX_INVITE_RESP_OK:
++		return "P2P_STATE_RX_INVITE_RESP_OK";
++	case P2P_STATE_RECV_INVITE_REQ_DISMATCH:
++		return "P2P_STATE_RECV_INVITE_REQ_DISMATCH";
++	case P2P_STATE_RECV_INVITE_REQ_GO:
++		return "P2P_STATE_RECV_INVITE_REQ_GO";
++	case P2P_STATE_RECV_INVITE_REQ_JOIN:
++		return "P2P_STATE_RECV_INVITE_REQ_JOIN";
++	case P2P_STATE_RX_INVITE_RESP_FAIL:
++		return "P2P_STATE_RX_INVITE_RESP_FAIL";
++	case P2P_STATE_RX_INFOR_NOREADY:
++		return "P2P_STATE_RX_INFOR_NOREADY";
++	case P2P_STATE_TX_INFOR_NOREADY:
++		return "P2P_STATE_TX_INFOR_NOREADY";
++	default:
++		return "UNKNOWN";
++	}
++}
++
++void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line)
++{
++	if (!_rtw_p2p_chk_state(wdinfo, state)) {
++		enum P2P_STATE old_state = _rtw_p2p_state(wdinfo);
++		_rtw_p2p_set_state(wdinfo, state);
++		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_state from %s to %s\n", caller, line
++			, rtw_p2p_state_txt(old_state), rtw_p2p_state_txt(_rtw_p2p_state(wdinfo))
++			);
++	} else {
++		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_state to same state %s\n", caller, line
++			 , rtw_p2p_state_txt(_rtw_p2p_state(wdinfo))
++			);
++	}
++}
++void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line)
++{
++	if (_rtw_p2p_pre_state(wdinfo) != state) {
++		enum P2P_STATE old_state = _rtw_p2p_pre_state(wdinfo);
++		_rtw_p2p_set_pre_state(wdinfo, state);
++		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_pre_state from %s to %s\n", caller, line
++			, rtw_p2p_state_txt(old_state), rtw_p2p_state_txt(_rtw_p2p_pre_state(wdinfo))
++			);
++	} else {
++		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_pre_state to same state %s\n", caller, line
++			 , rtw_p2p_state_txt(_rtw_p2p_pre_state(wdinfo))
++			);
++	}
++}
++#if 0
++void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line)
++{
++	if (wdinfo->pre_p2p_state != -1) {
++		RTW_INFO("[CONFIG_DBG_P2P]%s:%d restore from %s to %s\n", caller, line
++			, p2p_state_str[wdinfo->p2p_state], p2p_state_str[wdinfo->pre_p2p_state]
++			);
++		_rtw_p2p_restore_state(wdinfo);
++	} else {
++		RTW_INFO("[CONFIG_DBG_P2P]%s:%d restore no pre state, cur state %s\n", caller, line
++			 , p2p_state_str[wdinfo->p2p_state]
++			);
++	}
++}
++#endif
++void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line)
++{
++	if (wdinfo->role != role) {
++		enum P2P_ROLE old_role = wdinfo->role;
++		_rtw_p2p_set_role(wdinfo, role);
++		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_role from %s to %s\n", caller, line
++			, rtw_p2p_role_txt(old_role), rtw_p2p_role_txt(wdinfo->role)
++			);
++	} else {
++		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_role to same role %s\n", caller, line
++			 , rtw_p2p_role_txt(wdinfo->role)
++			);
++	}
++}
++#endif /* CONFIG_DBG_P2P */
++
++
++int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role)
++{
++	int ret = _SUCCESS;
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++
++	if (role == P2P_ROLE_DEVICE || role == P2P_ROLE_CLIENT || role == P2P_ROLE_GO) {
++#if defined(CONFIG_CONCURRENT_MODE) && (!defined(RTW_P2P_GROUP_INTERFACE) || !RTW_P2P_GROUP_INTERFACE)
++		/*	Commented by Albert 2011/12/30 */
++		/*	The driver just supports 1 P2P group operation. */
++		/*	So, this function will do nothing if the buddy adapter had enabled the P2P function. */
++		/*if(!rtw_p2p_chk_state(pbuddy_wdinfo, P2P_STATE_NONE))
++			return ret;*/
++		/* Only selected interface can be P2P interface */
++		if (padapter->iface_id != padapter->registrypriv.sel_p2p_iface) {
++			RTW_ERR("%s, iface_id:%d is not P2P interface!\n", __func__, padapter->iface_id);
++			ret = _FAIL;
++			return ret;
++		}
++#endif /* CONFIG_CONCURRENT_MODE */
++
++		/* leave IPS/Autosuspend */
++		if (_FAIL == rtw_pwr_wakeup(padapter)) {
++			ret = _FAIL;
++			goto exit;
++		}
++
++		/*	Added by Albert 2011/03/22 */
++		/*	In the P2P mode, the driver should not support the b mode. */
++		/*	So, the Tx packet shouldn't use the CCK rate */
++		#ifdef CONFIG_IOCTL_CFG80211
++		if (rtw_cfg80211_iface_has_p2p_group_cap(padapter))
++		#endif
++			update_tx_basic_rate(padapter, WIRELESS_11AGN);
++
++		/* Enable P2P function */
++		init_wifidirect_info(padapter, role);
++
++		#ifdef CONFIG_IOCTL_CFG80211
++		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211)
++			adapter_wdev_data(padapter)->p2p_enabled = _TRUE;
++		#endif
++
++		rtw_hal_set_odm_var(padapter, HAL_ODM_P2P_STATE, NULL, _TRUE);
++#ifdef CONFIG_WFD
++		if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
++			rtw_hal_set_odm_var(padapter, HAL_ODM_WIFI_DISPLAY_STATE, NULL, _TRUE);
++#endif
++
++	} else if (role == P2P_ROLE_DISABLE) {
++
++		#ifdef CONFIG_IOCTL_CFG80211
++		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211)
++			adapter_wdev_data(padapter)->p2p_enabled = _FALSE;
++		#endif
++
++		pwdinfo->listen_channel = 0;
++
++		/* Disable P2P function */
++		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
++			_cancel_timer_ex(&pwdinfo->find_phase_timer);
++			_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
++			_cancel_timer_ex(&pwdinfo->pre_tx_scan_timer);
++			_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);
++			_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey2);
++			reset_ch_sitesurvey_timer_process(padapter);
++			reset_ch_sitesurvey_timer_process2(padapter);
++#ifdef CONFIG_CONCURRENT_MODE
++			_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);
++#endif
++			rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE);
++			rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_NONE);
++			rtw_p2p_set_role(pwdinfo, P2P_ROLE_DISABLE);
++			_rtw_memset(&pwdinfo->rx_prov_disc_info, 0x00, sizeof(struct rx_provdisc_req_info));
++
++			/* Remove profiles in wifidirect_info structure. */
++			_rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM);
++			pwdinfo->profileindex = 0;
++		}
++
++		rtw_hal_set_odm_var(padapter, HAL_ODM_P2P_STATE, NULL, _FALSE);
++#ifdef CONFIG_WFD
++		if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
++			rtw_hal_set_odm_var(padapter, HAL_ODM_WIFI_DISPLAY_STATE, NULL, _FALSE);
++#endif
++
++		if (_FAIL == rtw_pwr_wakeup(padapter)) {
++			ret = _FAIL;
++			goto exit;
++		}
++
++		/* Restore to initial setting. */
++		update_tx_basic_rate(padapter, padapter->registrypriv.wireless_mode);
++
++		/* For WiDi purpose. */
++#ifdef CONFIG_IOCTL_CFG80211
++		pwdinfo->driver_interface = DRIVER_CFG80211;
++#else
++		pwdinfo->driver_interface = DRIVER_WEXT;
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++	}
++
++exit:
++	return ret;
++}
++
++#endif /* CONFIG_P2P */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_pwrctrl.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_pwrctrl.c
+new file mode 100644
+index 000000000..e917d7325
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_pwrctrl.c
+@@ -0,0 +1,2943 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_PWRCTRL_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++#include <hal_com_h2c.h>
++
++#ifdef DBG_CHECK_FW_PS_STATE
++int rtw_fw_ps_state(PADAPTER padapter)
++{
++	struct dvobj_priv *psdpriv = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
++	int ret = _FAIL, dont_care = 0;
++	u16 fw_ps_state = 0;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct registry_priv  *registry_par = &padapter->registrypriv;
++
++	if (registry_par->check_fw_ps != 1)
++		return _SUCCESS;
++
++	_enter_pwrlock(&pwrpriv->check_32k_lock);
++
++	if (RTW_CANNOT_RUN(padapter)) {
++		RTW_INFO("%s: bSurpriseRemoved=%s , hw_init_completed=%d, bDriverStopped=%s\n", __func__
++			 , rtw_is_surprise_removed(padapter) ? "True" : "False"
++			 , rtw_get_hw_init_completed(padapter)
++			 , rtw_is_drv_stopped(padapter) ? "True" : "False");
++		goto exit_fw_ps_state;
++	}
++	#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
++	rtw_hal_get_hwreg(padapter, HW_VAR_FW_PS_STATE, (u8 *)&fw_ps_state);
++	if ((fw_ps_state & BIT_LPS_STATUS) == 0)
++		ret = _SUCCESS;
++	else {
++		pdbgpriv->dbg_poll_fail_cnt++;
++		RTW_INFO("%s: fw_ps_state=%04x\n", __FUNCTION__, fw_ps_state);
++	}
++	#else
++	rtw_hal_set_hwreg(padapter, HW_VAR_SET_REQ_FW_PS, (u8 *)&dont_care);
++	{
++		/* 4. if 0x88[7]=1, driver set cmd to leave LPS/IPS. */
++		/* Else, hw will keep in active mode. */
++		/* debug info: */
++		/* 0x88[7] = 32kpermission, */
++		/* 0x88[6:0] = current_ps_state */
++		/* 0x89[7:0] = last_rpwm */
++
++		rtw_hal_get_hwreg(padapter, HW_VAR_FW_PS_STATE, (u8 *)&fw_ps_state);
++
++		if ((fw_ps_state & 0x80) == 0)
++			ret = _SUCCESS;
++		else {
++			pdbgpriv->dbg_poll_fail_cnt++;
++			RTW_INFO("%s: fw_ps_state=%04x\n", __FUNCTION__, fw_ps_state);
++		}
++	}
++	#endif
++
++exit_fw_ps_state:
++	_exit_pwrlock(&pwrpriv->check_32k_lock);
++	return ret;
++}
++#endif /*DBG_CHECK_FW_PS_STATE*/
++#ifdef CONFIG_IPS
++void _ips_enter(_adapter *padapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++
++	pwrpriv->bips_processing = _TRUE;
++
++	/* syn ips_mode with request */
++	pwrpriv->ips_mode = pwrpriv->ips_mode_req;
++
++	pwrpriv->ips_enter_cnts++;
++	RTW_INFO("==>ips_enter cnts:%d\n", pwrpriv->ips_enter_cnts);
++
++	if (rf_off == pwrpriv->change_rfpwrstate) {
++		pwrpriv->bpower_saving = _TRUE;
++		RTW_PRINT("nolinked power save enter\n");
++
++		if (pwrpriv->ips_mode == IPS_LEVEL_2)
++			pwrpriv->bkeepfwalive = _TRUE;
++
++#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS		
++		pwrpriv->pwr_saving_start_time = rtw_get_current_time();
++#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
++
++		rtw_ips_pwr_down(padapter);
++		pwrpriv->rf_pwrstate = rf_off;
++	}
++	pwrpriv->bips_processing = _FALSE;
++
++}
++
++void ips_enter(_adapter *padapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++
++
++#ifdef CONFIG_BT_COEXIST
++	rtw_btcoex_IpsNotify(padapter, pwrpriv->ips_mode_req);
++#endif /* CONFIG_BT_COEXIST */
++
++	_enter_pwrlock(&pwrpriv->lock);
++	_ips_enter(padapter);
++	_exit_pwrlock(&pwrpriv->lock);
++
++#ifdef CONFIG_PCI_DYNAMIC_ASPM
++	rtw_pci_dynamic_aspm_set_mode(padapter, ASPM_MODE_PS);
++#endif
++}
++
++int _ips_leave(_adapter *padapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	int result = _SUCCESS;
++
++	if ((pwrpriv->rf_pwrstate == rf_off) && (!pwrpriv->bips_processing)) {
++		pwrpriv->bips_processing = _TRUE;
++		pwrpriv->change_rfpwrstate = rf_on;
++		pwrpriv->ips_leave_cnts++;
++		RTW_INFO("==>ips_leave cnts:%d\n", pwrpriv->ips_leave_cnts);
++
++		result = rtw_ips_pwr_up(padapter);
++		if (result == _SUCCESS)
++			pwrpriv->rf_pwrstate = rf_on;
++		
++#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS	
++		pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);
++#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
++
++		RTW_PRINT("nolinked power save leave\n");
++
++		RTW_INFO("==> ips_leave.....LED(0x%08x)...\n", rtw_read32(padapter, 0x4c));
++		pwrpriv->bips_processing = _FALSE;
++
++		pwrpriv->bkeepfwalive = _FALSE;
++		pwrpriv->bpower_saving = _FALSE;
++	}
++
++	return result;
++}
++
++int ips_leave(_adapter *padapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++#ifdef DBG_CHECK_FW_PS_STATE
++	struct dvobj_priv *psdpriv = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
++#endif
++	int ret;
++
++	if (!is_primary_adapter(padapter))
++		return _SUCCESS;
++
++	_enter_pwrlock(&pwrpriv->lock);
++	ret = _ips_leave(padapter);
++#ifdef DBG_CHECK_FW_PS_STATE
++	if (rtw_fw_ps_state(padapter) == _FAIL) {
++		RTW_INFO("ips leave doesn't leave 32k\n");
++		pdbgpriv->dbg_leave_ips_fail_cnt++;
++	}
++#endif /* DBG_CHECK_FW_PS_STATE */
++	_exit_pwrlock(&pwrpriv->lock);
++
++#ifdef CONFIG_PCI_DYNAMIC_ASPM
++	rtw_pci_dynamic_aspm_set_mode(padapter, ASPM_MODE_PERF);
++#endif
++
++	if (_SUCCESS == ret)
++		odm_dm_reset(&GET_HAL_DATA(padapter)->odmpriv);
++
++#ifdef CONFIG_BT_COEXIST
++	if (_SUCCESS == ret)
++		rtw_btcoex_IpsNotify(padapter, IPS_NONE);
++#endif /* CONFIG_BT_COEXIST */
++
++	return ret;
++}
++#endif /* CONFIG_IPS */
++
++#ifdef SUPPORT_HW_RFOFF_DETECTED
++	int rtw_hw_suspend(_adapter *padapter);
++	int rtw_hw_resume(_adapter *padapter);
++#endif
++
++bool rtw_pwr_unassociated_idle(_adapter *adapter)
++{
++	u8 i;
++	_adapter *iface;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct xmit_priv *pxmit_priv = &adapter->xmitpriv;
++	struct mlme_priv *pmlmepriv;
++#ifdef CONFIG_P2P
++	struct wifidirect_info	*pwdinfo;
++#endif
++
++	bool ret = _FALSE;
++
++	if (adapter_to_pwrctl(adapter)->bpower_saving == _TRUE) {
++		/* RTW_INFO("%s: already in LPS or IPS mode\n", __func__); */
++		goto exit;
++	}
++
++	if (rtw_time_after(adapter_to_pwrctl(adapter)->ips_deny_time, rtw_get_current_time())) {
++		/* RTW_INFO("%s ips_deny_time\n", __func__); */
++		goto exit;
++	}
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if ((iface) && rtw_is_adapter_up(iface)) {
++			pmlmepriv = &(iface->mlmepriv);
++#ifdef CONFIG_P2P
++			pwdinfo = &(iface->wdinfo);
++#endif
++			if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_UNDER_SURVEY)
++				|| check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)
++				|| MLME_IS_AP(iface)
++				|| MLME_IS_MESH(iface)
++				|| check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE)
++				#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211)
++				|| rtw_cfg80211_get_is_roch(iface) == _TRUE
++				|| (rtw_cfg80211_is_ro_ch_once(adapter)
++					&& rtw_cfg80211_get_last_ro_ch_passing_ms(adapter) < 3000)
++				#elif defined(CONFIG_P2P)
++				|| rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)
++				|| rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN)
++				#endif
++			)
++				goto exit;
++
++		}
++	}
++
++#if (MP_DRIVER == 1)
++	if (adapter->registrypriv.mp_mode == 1)
++		goto exit;
++#endif
++
++	if (pxmit_priv->free_xmitbuf_cnt != NR_XMITBUFF ||
++	    pxmit_priv->free_xmit_extbuf_cnt != NR_XMIT_EXTBUFF) {
++		RTW_PRINT("There are some pkts to transmit\n");
++		RTW_PRINT("free_xmitbuf_cnt: %d, free_xmit_extbuf_cnt: %d\n",
++			pxmit_priv->free_xmitbuf_cnt, pxmit_priv->free_xmit_extbuf_cnt);
++		goto exit;
++	}
++
++	ret = _TRUE;
++
++exit:
++	return ret;
++}
++
++
++/*
++ * ATTENTION:
++ *	rtw_ps_processor() doesn't handle LPS.
++ */
++void rtw_ps_processor(_adapter *padapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct dvobj_priv *psdpriv = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
++#ifdef SUPPORT_HW_RFOFF_DETECTED
++	rt_rf_power_state rfpwrstate;
++#endif /* SUPPORT_HW_RFOFF_DETECTED */
++	u32 ps_deny = 0;
++
++	_enter_pwrlock(&adapter_to_pwrctl(padapter)->lock);
++	ps_deny = rtw_ps_deny_get(padapter);
++	_exit_pwrlock(&adapter_to_pwrctl(padapter)->lock);
++	if (ps_deny != 0) {
++		if (!MLME_IS_MONITOR(padapter)) {
++			RTW_INFO(FUNC_ADPT_FMT ": ps_deny=0x%08X, skip power save!\n",
++				 FUNC_ADPT_ARG(padapter), ps_deny);
++		}
++		goto exit;
++	}
++
++	if (pwrpriv->bInSuspend == _TRUE) { /* system suspend or autosuspend */
++		pdbgpriv->dbg_ps_insuspend_cnt++;
++		RTW_INFO("%s, pwrpriv->bInSuspend == _TRUE ignore this process\n", __FUNCTION__);
++		return;
++	}
++
++	pwrpriv->ps_processing = _TRUE;
++
++#ifdef SUPPORT_HW_RFOFF_DETECTED
++	if (pwrpriv->bips_processing == _TRUE)
++		goto exit;
++
++	/* RTW_INFO("==> fw report state(0x%x)\n",rtw_read8(padapter,0x1ca));	 */
++	if (pwrpriv->bHWPwrPindetect) {
++		
++		rfpwrstate = RfOnOffDetect(padapter);
++		RTW_INFO("@@@@- #2  %s==> rfstate:%s\n", __FUNCTION__, (rfpwrstate == rf_on) ? "rf_on" : "rf_off");
++
++		if (rfpwrstate != pwrpriv->rf_pwrstate) {
++			if (rfpwrstate == rf_off) {
++				pwrpriv->change_rfpwrstate = rf_off;
++				pwrpriv->brfoffbyhw = _TRUE;
++				rtw_hw_suspend(padapter);
++			} else {
++				pwrpriv->change_rfpwrstate = rf_on;
++				rtw_hw_resume(padapter);
++			}
++			RTW_INFO("current rf_pwrstate(%s)\n", (pwrpriv->rf_pwrstate == rf_off) ? "rf_off" : "rf_on");
++		}
++		
++		pwrpriv->pwr_state_check_cnts++;
++	}
++#endif /* SUPPORT_HW_RFOFF_DETECTED */
++
++	if (pwrpriv->ips_mode_req == IPS_NONE)
++		goto exit;
++
++	if (rtw_pwr_unassociated_idle(padapter) == _FALSE)
++		goto exit;
++
++	if ((pwrpriv->rf_pwrstate == rf_on) && ((pwrpriv->pwr_state_check_cnts % 4) == 0)) {
++		RTW_INFO("==>%s .fw_state(%x)\n", __FUNCTION__, get_fwstate(pmlmepriv));
++		pwrpriv->change_rfpwrstate = rf_off;	
++
++#ifdef CONFIG_IPS
++			ips_enter(padapter);
++#endif
++
++	}
++exit:
++#ifndef CONFIG_IPS_CHECK_IN_WD
++	rtw_set_pwr_state_check_timer(pwrpriv);
++#endif
++	pwrpriv->ps_processing = _FALSE;
++	return;
++}
++
++void pwr_state_check_handler(void *ctx)
++{
++	_adapter *padapter = (_adapter *)ctx;
++	rtw_ps_cmd(padapter);
++}
++
++#ifdef CONFIG_LPS
++#ifdef CONFIG_CHECK_LEAVE_LPS
++#ifdef CONFIG_LPS_CHK_BY_TP
++void traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info *sta)
++{
++	struct stainfo_stats *pstats = &sta->sta_stats;
++	u64 cur_acc_tx_bytes = 0, cur_acc_rx_bytes = 0;
++	u32 tx_tp_kbyte = 0, rx_tp_kbyte = 0;
++	u32 tx_tp_th = 0, rx_tp_th = 0;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	u8	leave_lps = _FALSE;
++
++	if (tx) { /* from tx */
++		cur_acc_tx_bytes = pstats->tx_bytes - pstats->acc_tx_bytes;
++		tx_tp_kbyte = cur_acc_tx_bytes >> 10;
++		tx_tp_th = pwrpriv->lps_tx_tp_th * 1024 / 8 * 2; /*KBytes @2s*/
++
++		if (tx_tp_kbyte >= tx_tp_th ||
++			padapter->mlmepriv.LinkDetectInfo.NumTxOkInPeriod >= pwrpriv->lps_tx_pkts){
++			if (pwrpriv->bLeisurePs
++				&& (pwrpriv->pwr_mode != PS_MODE_ACTIVE)
++				#ifdef CONFIG_BT_COEXIST
++				&& (rtw_btcoex_IsBtControlLps(padapter) == _FALSE)
++				#endif
++			) {
++				leave_lps = _TRUE;
++			}
++		}
++
++	} else { /* from rx path */
++		cur_acc_rx_bytes = pstats->rx_bytes - pstats->acc_rx_bytes;
++		rx_tp_kbyte = cur_acc_rx_bytes >> 10;
++		rx_tp_th = pwrpriv->lps_rx_tp_th * 1024 / 8 * 2;
++
++		if (rx_tp_kbyte>= rx_tp_th ||
++			padapter->mlmepriv.LinkDetectInfo.NumRxUnicastOkInPeriod >= pwrpriv->lps_rx_pkts) {
++			if (pwrpriv->bLeisurePs
++				&& (pwrpriv->pwr_mode != PS_MODE_ACTIVE)
++				#ifdef CONFIG_BT_COEXIST
++				&& (rtw_btcoex_IsBtControlLps(padapter) == _FALSE)
++				#endif
++			) {
++				leave_lps = _TRUE;
++			}
++		}
++	}
++
++	if (leave_lps) {
++		#ifdef DBG_LPS_CHK_BY_TP
++		RTW_INFO("leave lps via %s, ", tx ? "Tx" : "Rx");
++		if (tx)
++			RTW_INFO("Tx = %d [%d] (KB)\n", tx_tp_kbyte, tx_tp_th);
++		else
++			RTW_INFO("Rx = %d [%d] (KB)\n", rx_tp_kbyte, rx_tp_th);
++		#endif
++		pwrpriv->lps_chk_cnt = pwrpriv->lps_chk_cnt_th;
++		/* rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0); */
++		rtw_lps_ctrl_wk_cmd(padapter, tx ? LPS_CTRL_TX_TRAFFIC_LEAVE : LPS_CTRL_RX_TRAFFIC_LEAVE, 0);
++	}
++}
++#endif /*CONFIG_LPS_CHK_BY_TP*/
++
++void	traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets)
++{
++	static systime start_time = 0;
++	static u32 xmit_cnt = 0;
++	u8	bLeaveLPS = _FALSE;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++
++
++
++	if (tx) { /* from tx */
++		xmit_cnt += tx_packets;
++
++		if (start_time == 0)
++			start_time = rtw_get_current_time();
++
++		if (rtw_get_passing_time_ms(start_time) > 2000) { /* 2 sec == watch dog timer */
++			if (xmit_cnt > 8) {
++				if ((adapter_to_pwrctl(padapter)->bLeisurePs)
++				    && (adapter_to_pwrctl(padapter)->pwr_mode != PS_MODE_ACTIVE)
++#ifdef CONFIG_BT_COEXIST
++				    && (rtw_btcoex_IsBtControlLps(padapter) == _FALSE)
++#endif
++				   ) {
++					/* RTW_INFO("leave lps via Tx = %d\n", xmit_cnt);			 */
++					bLeaveLPS = _TRUE;
++				}
++			}
++
++			start_time = rtw_get_current_time();
++			xmit_cnt = 0;
++		}
++
++	} else { /* from rx path */
++		if (pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 4/*2*/) {
++			if ((adapter_to_pwrctl(padapter)->bLeisurePs)
++			    && (adapter_to_pwrctl(padapter)->pwr_mode != PS_MODE_ACTIVE)
++#ifdef CONFIG_BT_COEXIST
++			    && (rtw_btcoex_IsBtControlLps(padapter) == _FALSE)
++#endif
++			   ) {
++				/* RTW_INFO("leave lps via Rx = %d\n", pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod);	 */
++				bLeaveLPS = _TRUE;
++			}
++		}
++	}
++
++	if (bLeaveLPS) {
++		/* RTW_INFO("leave lps via %s, Tx = %d, Rx = %d\n", tx?"Tx":"Rx", pmlmepriv->LinkDetectInfo.NumTxOkInPeriod,pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod);	 */
++		/* rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0); */
++		rtw_lps_ctrl_wk_cmd(padapter, tx ? LPS_CTRL_TX_TRAFFIC_LEAVE : LPS_CTRL_RX_TRAFFIC_LEAVE, tx ? RTW_CMDF_DIRECTLY : 0);
++	}
++}
++#endif /* CONFIG_CHECK_LEAVE_LPS */
++
++#ifdef CONFIG_LPS_LCLK
++#define LPS_CPWM_TIMEOUT_MS	10 /*ms*/
++#define LPS_RPWM_RETRY_CNT		3
++
++u8 rtw_cpwm_polling(_adapter *adapter, u8 rpwm, u8 cpwm_orig)
++{
++	u8 rst = _FAIL;
++	u8 cpwm_now = 0;
++	systime start_time;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	#ifdef DBG_CHECK_FW_PS_STATE
++	struct debug_priv *pdbgpriv = &(adapter_to_dvobj(adapter)->drv_dbg);
++	#endif
++
++	pwrpriv->rpwm_retry = 0;
++
++	do {
++		start_time = rtw_get_current_time();
++		do {
++			rtw_msleep_os(1);
++			rtw_hal_get_hwreg(adapter, HW_VAR_CPWM, &cpwm_now);
++
++			if ((cpwm_orig ^ cpwm_now) & 0x80) {
++				pwrpriv->cpwm = PS_STATE_S4;
++				pwrpriv->cpwm_tog = cpwm_now & PS_TOGGLE;
++				rst = _SUCCESS;
++				break;
++			}
++		} while (rtw_get_passing_time_ms(start_time) < LPS_CPWM_TIMEOUT_MS && !RTW_CANNOT_RUN(adapter));
++
++		if (rst == _SUCCESS)
++			break;
++		else {
++			/* rpwm retry */
++			cpwm_orig = cpwm_now;
++			rpwm &= ~PS_TOGGLE;
++			rpwm |= pwrpriv->tog;
++			rtw_hal_set_hwreg(adapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));
++			pwrpriv->tog += 0x80;
++		}
++	} while (pwrpriv->rpwm_retry++ < LPS_RPWM_RETRY_CNT && !RTW_CANNOT_RUN(adapter));
++
++	if (rst == _SUCCESS) {
++		#ifdef DBG_CHECK_FW_PS_STATE
++		RTW_INFO("%s: polling cpwm OK! rpwm_retry=%d, cpwm_orig=%02x, cpwm_now=%02x , 0x100=0x%x\n"
++			, __func__, pwrpriv->rpwm_retry, cpwm_orig, cpwm_now, rtw_read8(adapter, REG_CR));
++		if (rtw_fw_ps_state(adapter) == _FAIL) {
++			RTW_INFO("leave 32k but fw state in 32k\n");
++			pdbgpriv->dbg_rpwm_toogle_cnt++;
++		}
++		#endif /* DBG_CHECK_FW_PS_STATE */
++	} else {
++		RTW_ERR("%s: polling cpwm timeout! rpwm_retry=%d, cpwm_orig=%02x, cpwm_now=%02x\n"
++				, __func__, pwrpriv->rpwm_retry, cpwm_orig, cpwm_now);
++		#ifdef DBG_CHECK_FW_PS_STATE
++		if (rtw_fw_ps_state(adapter) == _FAIL) {
++			RTW_INFO("rpwm timeout and fw ps state in 32k\n");
++			pdbgpriv->dbg_rpwm_timeout_fail_cnt++;
++		}
++		#endif /* DBG_CHECK_FW_PS_STATE */
++
++		#ifdef CONFIG_LPS_RPWM_TIMER
++		_set_timer(&pwrpriv->pwr_rpwm_timer, 1);
++		#endif /* CONFIG_LPS_RPWM_TIMER */
++	}
++
++	return rst;
++}
++#endif
++/*
++ * Description:
++ *	This function MUST be called under power lock protect
++ *
++ * Parameters
++ *	padapter
++ *	pslv			power state level, only could be PS_STATE_S0 ~ PS_STATE_S4
++ *
++ */
++u8 rtw_set_rpwm(PADAPTER padapter, u8 pslv)
++{
++	u8	rpwm = 0xFF;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++#ifdef CONFIG_LPS_LCLK
++	u8 cpwm_orig;
++#endif
++
++	pslv = PS_STATE(pslv);
++
++#ifdef CONFIG_LPS_RPWM_TIMER
++	if (pwrpriv->brpwmtimeout == _TRUE)
++		RTW_INFO("%s: RPWM timeout, force to set RPWM(0x%02X) again!\n", __FUNCTION__, pslv);
++	else
++#endif /* CONFIG_LPS_RPWM_TIMER */
++	{
++		if ((pwrpriv->rpwm == pslv)
++#ifdef CONFIG_LPS_LCLK
++		    || ((pwrpriv->rpwm >= PS_STATE_S2) && (pslv >= PS_STATE_S2))
++#endif
++			|| (pwrpriv->lps_level == LPS_NORMAL)
++		   ) {
++			return rpwm;
++		}
++	}
++
++	if (rtw_is_surprise_removed(padapter) ||
++	    (!rtw_is_hw_init_completed(padapter))) {
++
++		pwrpriv->cpwm = PS_STATE_S4;
++
++		return rpwm;
++	}
++
++	if (rtw_is_drv_stopped(padapter))
++		if (pslv < PS_STATE_S2)
++			return rpwm;
++
++	rpwm = pslv | pwrpriv->tog;
++#ifdef CONFIG_LPS_LCLK
++	/* only when from PS_STATE S0/S1 to S2 and higher needs ACK */
++	if ((pwrpriv->cpwm < PS_STATE_S2) && (pslv >= PS_STATE_S2))
++		rpwm |= PS_ACK;
++#endif
++
++	pwrpriv->rpwm = pslv;
++
++#ifdef CONFIG_LPS_LCLK
++	cpwm_orig = 0;
++	if (rpwm & PS_ACK)
++		rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
++#endif
++
++#if defined(CONFIG_LPS_RPWM_TIMER) && !defined(CONFIG_DETECT_CPWM_BY_POLLING)
++	if (rpwm & PS_ACK) {
++		#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)
++		if (pwrpriv->wowlan_mode != _TRUE &&
++			pwrpriv->wowlan_ap_mode != _TRUE &&
++			pwrpriv->wowlan_p2p_mode != _TRUE)
++		#endif
++		_set_timer(&pwrpriv->pwr_rpwm_timer, LPS_CPWM_TIMEOUT_MS);
++	}
++#endif /* CONFIG_LPS_RPWM_TIMER & !CONFIG_DETECT_CPWM_BY_POLLING */
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));
++
++	pwrpriv->tog += 0x80;
++
++#ifdef CONFIG_LPS_LCLK
++	/* No LPS 32K, No Ack */
++	if (rpwm & PS_ACK) {
++		#ifdef CONFIG_DETECT_CPWM_BY_POLLING
++		rtw_cpwm_polling(padapter, rpwm, cpwm_orig);
++		#else
++		#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)
++		if (pwrpriv->wowlan_mode == _TRUE ||
++			pwrpriv->wowlan_ap_mode == _TRUE ||
++			pwrpriv->wowlan_p2p_mode == _TRUE)
++				rtw_cpwm_polling(padapter, rpwm, cpwm_orig);
++		#endif /*#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)*/
++		#endif /*#ifdef CONFIG_DETECT_CPWM_BY_POLLING*/
++	} else
++#endif /* CONFIG_LPS_LCLK */
++	{
++		pwrpriv->cpwm = pslv;
++	}
++
++	return rpwm;
++}
++
++u8 PS_RDY_CHECK(_adapter *padapter)
++{
++	struct pwrctrl_priv	*pwrpriv = adapter_to_pwrctl(padapter);
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++	if (_TRUE == pwrpriv->bInSuspend && pwrpriv->wowlan_mode)
++		return _TRUE;
++	else if (_TRUE == pwrpriv->bInSuspend && pwrpriv->wowlan_ap_mode)
++		return _TRUE;
++	else if (_TRUE == pwrpriv->bInSuspend)
++		return _FALSE;
++#else
++	if (_TRUE == pwrpriv->bInSuspend)
++		return _FALSE;
++#endif
++
++	if (rtw_time_after(pwrpriv->lps_deny_time, rtw_get_current_time()))
++		return _FALSE;
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)
++		|| check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)
++		|| MLME_IS_AP(padapter)
++		|| MLME_IS_MESH(padapter)
++		|| MLME_IS_MONITOR(padapter)
++		|| check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE)
++		#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211)
++		|| rtw_cfg80211_get_is_roch(padapter) == _TRUE
++		#endif
++		|| rtw_is_scan_deny(padapter)
++		#ifdef CONFIG_TDLS
++		/* TDLS link is established. */
++		|| (padapter->tdlsinfo.link_established == _TRUE)
++		#endif /* CONFIG_TDLS		 */
++		#ifdef CONFIG_DFS_MASTER
++		|| adapter_to_rfctl(padapter)->radar_detect_enabled
++		#endif
++	)
++		return _FALSE;
++
++	if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) && (padapter->securitypriv.binstallGrpkey == _FALSE)) {
++		RTW_INFO("Group handshake still in progress !!!\n");
++		return _FALSE;
++	}
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (!rtw_cfg80211_pwr_mgmt(padapter))
++		return _FALSE;
++#endif
++
++	return _TRUE;
++}
++
++#if defined(CONFIG_FWLPS_IN_IPS)
++void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	int cnt = 0;
++	systime start_time;
++	u8 val8 = 0;
++	u8 cpwm_orig = 0, cpwm_now = 0;
++	u8 parm[H2C_INACTIVE_PS_LEN] = {0};
++
++	if (padapter->netif_up == _FALSE) {
++		RTW_INFO("%s: ERROR, netif is down\n", __func__);
++		return;
++	}
++
++	/* u8 cmd_param; */ /* BIT0:enable, BIT1:NoConnect32k */
++	if (enable) {
++#ifdef CONFIG_BT_COEXIST
++		rtw_btcoex_IpsNotify(padapter, pwrpriv->ips_mode_req);
++#endif
++		/* Enter IPS */
++		RTW_INFO("%s: issue H2C to FW when entering IPS\n", __func__);
++
++		parm[0] = 0x1;/* suggest by Isaac.Hsu*/
++#ifdef CONFIG_PNO_SUPPORT
++		if (pwrpriv->pno_inited) {
++			parm[1] = pwrpriv->pnlo_info->fast_scan_iterations;
++			parm[2] = pwrpriv->pnlo_info->slow_scan_period;
++		}
++#endif
++
++		rtw_hal_fill_h2c_cmd(padapter, /* H2C_FWLPS_IN_IPS_, */
++				     H2C_INACTIVE_PS_,
++				     H2C_INACTIVE_PS_LEN, parm);
++		/* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW. */
++		do {
++			val8 = rtw_read8(padapter, REG_HMETFR);
++			cnt++;
++			RTW_INFO("%s  polling REG_HMETFR=0x%x, cnt=%d\n",
++				 __func__, val8, cnt);
++			rtw_mdelay_os(10);
++		} while (cnt < 100 && (val8 != 0));
++
++#ifdef CONFIG_LPS_LCLK
++		/* H2C done, enter 32k */
++		if (val8 == 0) {
++			/* ser rpwm to enter 32k */
++			rtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &val8);
++			RTW_INFO("%s: read rpwm=%02x\n", __FUNCTION__, val8);
++			val8 += 0x80;
++			val8 |= BIT(0);
++			rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&val8));
++			RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
++			adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
++			cnt = val8 = 0;
++			if (parm[1] == 0 || parm[2] == 0) {
++				do {
++					val8 = rtw_read8(padapter, REG_CR);
++					cnt++;
++					RTW_INFO("%s  polling 0x100=0x%x, cnt=%d\n",
++						 __func__, val8, cnt);
++					RTW_INFO("%s 0x08:%02x, 0x03:%02x\n",
++						 __func__,
++						 rtw_read8(padapter, 0x08),
++						 rtw_read8(padapter, 0x03));
++					rtw_mdelay_os(10);
++				} while (cnt < 20 && (val8 != 0xEA));
++			}
++		}
++#endif
++	} else {
++		/* Leave IPS */
++		RTW_INFO("%s: Leaving IPS in FWLPS state\n", __func__);
++
++#ifdef CONFIG_LPS_LCLK
++		/* for polling cpwm */
++		cpwm_orig = 0;
++		rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
++
++		/* ser rpwm */
++		rtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &val8);
++		val8 += 0x80;
++		val8 |= BIT(6);
++		rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&val8));
++		RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
++		adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
++
++		/* do polling cpwm */
++		start_time = rtw_get_current_time();
++		do {
++
++			rtw_mdelay_os(1);
++
++			rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
++			if ((cpwm_orig ^ cpwm_now) & 0x80)
++				break;
++
++			if (rtw_get_passing_time_ms(start_time) > 100) {
++				RTW_INFO("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __FUNCTION__);
++				break;
++			}
++		} while (1);
++
++#endif
++		parm[0] = 0x0;
++		parm[1] = 0x0;
++		parm[2] = 0x0;
++		rtw_hal_fill_h2c_cmd(padapter, H2C_INACTIVE_PS_,
++				     H2C_INACTIVE_PS_LEN, parm);
++#ifdef CONFIG_BT_COEXIST
++		rtw_btcoex_IpsNotify(padapter, IPS_NONE);
++#endif
++	}
++}
++#endif /* CONFIG_PNO_SUPPORT */
++
++void rtw_exec_lps(_adapter *padapter, u8 ps_mode)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++
++	if (ps_mode == PS_MODE_ACTIVE) {
++#ifdef CONFIG_LPS_ACK
++		_enter_critical_mutex(&pwrpriv->lps_ack_mutex, NULL);
++		rtw_sctx_init(&pwrpriv->lps_ack_sctx, 100);
++#endif /* CONFIG_LPS_ACK */
++
++		rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode));
++		rtw_hal_set_hwreg(padapter, HW_VAR_LPS_STATE_CHK, (u8 *)(&ps_mode));
++
++#ifdef CONFIG_LPS_ACK
++		_exit_critical_mutex(&pwrpriv->lps_ack_mutex, NULL);
++#endif /* CONFIG_LPS_ACK */
++	} else {
++		if (MLME_IS_ASOC(padapter))
++			rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode));
++		else
++			RTW_INFO(FUNC_ADPT_FMT": It can't execute LPS without Wi-Fi connection!\n",
++				FUNC_ADPT_ARG(padapter));
++	}
++}
++
++void rtw_lps_rfon_ctrl(_adapter *padapter, u8 rfon_ctrl)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	u8 rpwm = 0;
++
++	if (pwrpriv->bFwCurrentInPSMode && pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
++		if (rfon_ctrl == rf_on) {
++#ifdef CONFIG_LPS_LCLK
++			if (pwrpriv->lps_level >= LPS_LCLK) {
++				s32 ready = _FAIL;
++				systime stime;
++				s32 utime;
++				u32 timeout; /* unit: ms */
++
++#ifdef LPS_RPWM_WAIT_MS
++				timeout = LPS_RPWM_WAIT_MS;
++#else
++				timeout = 30;
++#endif /* !LPS_RPWM_WAIT_MS */
++
++				stime = rtw_get_current_time();
++				do {
++					ready = rtw_register_task_alive(padapter, LPS_ALIVE);
++					if (ready == _SUCCESS)
++						break;
++
++					utime = rtw_get_passing_time_ms(stime);
++					if (utime > timeout)
++						break;
++
++					rtw_msleep_os(1);
++				} while (1);
++
++				if (ready == _FAIL)
++					RTW_INFO(FUNC_ADPT_FMT": It is not ready to leave 32K !!!\n", 
++						FUNC_ADPT_ARG(padapter));
++			}
++#endif /* CONFIG_LPS_LCLK */
++
++#ifdef CONFIG_LPS_ACK
++			_enter_critical_mutex(&pwrpriv->lps_ack_mutex, NULL);
++			rtw_sctx_init(&pwrpriv->lps_ack_sctx, 100);
++#endif /* CONFIG_LPS_ACK */
++
++			rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE_RFON_CTRL, (u8 *)(&rfon_ctrl));
++			rtw_hal_set_hwreg(padapter, HW_VAR_LPS_RFON_CHK, (u8 *)(&rfon_ctrl));
++
++#ifdef CONFIG_LPS_ACK
++			_exit_critical_mutex(&pwrpriv->lps_ack_mutex, NULL);
++#endif /* CONFIG_LPS_ACK */
++		} else {
++			if (MLME_IS_ASOC(padapter)) {
++#ifdef CONFIG_LPS_PG
++				if (pwrpriv->lps_level == LPS_PG) {
++						 if (rtw_hal_set_lps_pg_info_cmd(padapter) == _FAIL)
++						 	RTW_INFO(FUNC_ADPT_FMT": Send PG H2C command Fail! \n", 
++						 			    FUNC_ADPT_ARG(padapter));
++				}
++#endif /* CONFIG_LPS_PG */
++				rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE_RFON_CTRL, (u8 *)(&rfon_ctrl));
++			} else {
++				RTW_INFO(FUNC_ADPT_FMT": It can't execute RFON without Wi-Fi connection!\n",
++					FUNC_ADPT_ARG(padapter));
++			}
++
++#ifdef CONFIG_LPS_LCLK
++			if (pwrpriv->lps_level >= LPS_LCLK) {
++				rtw_unregister_task_alive(padapter, LPS_ALIVE);
++
++				if (pwrpriv->alives == 0) {
++					u8 polling_cnt = 0;
++					u8 reg_val8 = 0;
++					u8 result = _FAIL;
++
++					do {
++						rtw_msleep_os(1);
++						reg_val8 = rtw_read8(padapter, REG_CR);
++						if (reg_val8 == 0xEA) {
++							result= _SUCCESS;
++							break;
++						}
++						polling_cnt++;
++					} while (polling_cnt < 100);
++
++					if (result == _FAIL )
++						RTW_INFO(FUNC_ADPT_FMT": It is not finished to enter 32K !!!\n", 
++							FUNC_ADPT_ARG(padapter));
++				}
++			}
++#endif /* CONFIG_LPS_LCLK */
++		}
++	} else {
++		RTW_INFO(FUNC_ADPT_FMT": RFON can't work due to ps state is not in LPS !\n", 
++							FUNC_ADPT_ARG(padapter));
++	}
++}
++
++void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)
++	struct dvobj_priv *psdpriv = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
++#endif
++#ifdef CONFIG_WMMPS_STA	
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++#endif
++#ifdef CONFIG_P2P
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++#endif /* CONFIG_P2P */
++#ifdef CONFIG_TDLS
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	_irqL irqL;
++	int i, j;
++	_list	*plist, *phead;
++	struct sta_info *ptdls_sta;
++#endif /* CONFIG_TDLS */
++#ifdef CONFIG_LPS_PG
++	u8 lps_pg_hdl_id = 0;
++#endif
++
++
++
++	if (ps_mode > PM_Card_Disable) {
++		return;
++	}
++
++	if (pwrpriv->pwr_mode == ps_mode) {
++		if (PS_MODE_ACTIVE == ps_mode)
++			return;
++
++#ifndef CONFIG_BT_COEXIST
++#ifdef CONFIG_WMMPS_STA	
++		if (!rtw_is_wmmps_mode(padapter))
++#endif /* CONFIG_WMMPS_STA */
++			if ((pwrpriv->smart_ps == smart_ps) &&
++			    (pwrpriv->bcn_ant_mode == bcn_ant_mode))
++				return;
++#endif /* !CONFIG_BT_COEXIST */
++	}
++
++#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++	if (PS_MODE_ACTIVE != ps_mode) {
++		rtw_set_ps_rsvd_page(padapter);
++		rtw_set_default_port_id(padapter);
++	}
++#endif
++
++#ifdef CONFIG_LPS_PG
++	if ((PS_MODE_ACTIVE != ps_mode) && (pwrpriv->lps_level == LPS_PG)) {
++		if (pwrpriv->wowlan_mode != _TRUE) {
++				/*rtw_hal_set_lps_pg_info(padapter);*/
++				lps_pg_hdl_id = LPS_PG_INFO_CFG;
++				rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));
++		}
++	}
++#endif
++
++#ifdef CONFIG_LPS_LCLK
++	_enter_pwrlock(&pwrpriv->lock);
++#endif
++
++	/* if(pwrpriv->pwr_mode == PS_MODE_ACTIVE) */
++	if (ps_mode == PS_MODE_ACTIVE) {
++		if (1
++#ifdef CONFIG_BT_COEXIST
++		    && (((rtw_btcoex_IsBtControlLps(padapter) == _FALSE)
++#ifdef CONFIG_P2P_PS
++			 && (pwdinfo->opp_ps == 0)
++#endif /* CONFIG_P2P_PS */
++			)
++			|| ((rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
++			    && (rtw_btcoex_IsLpsOn(padapter) == _FALSE))
++		       )
++#else /* !CONFIG_BT_COEXIST */
++#ifdef CONFIG_P2P_PS
++		    && (pwdinfo->opp_ps == 0)
++#endif /* CONFIG_P2P_PS */
++#endif /* !CONFIG_BT_COEXIST */
++		   ) {
++			RTW_INFO(FUNC_ADPT_FMT" Leave 802.11 power save - %s\n",
++				 FUNC_ADPT_ARG(padapter), msg);
++
++			if (pwrpriv->lps_leave_cnts < UINT_MAX)
++				pwrpriv->lps_leave_cnts++;
++			else
++				pwrpriv->lps_leave_cnts = 0;
++#ifdef CONFIG_TDLS
++			for (i = 0; i < NUM_STA; i++) {
++				phead = &(pstapriv->sta_hash[i]);
++				plist = get_next(phead);
++
++				while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++					ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++
++					if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)
++						issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 0, 0);
++					plist = get_next(plist);
++				}
++			}
++#endif /* CONFIG_TDLS */
++
++			pwrpriv->pwr_mode = ps_mode;
++			rtw_set_rpwm(padapter, PS_STATE_S4);
++
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)
++			if (pwrpriv->wowlan_mode == _TRUE ||
++			    pwrpriv->wowlan_ap_mode == _TRUE ||
++			    pwrpriv->wowlan_p2p_mode == _TRUE) {
++				systime start_time;
++				u32 delay_ms;
++				u8 val8;
++				delay_ms = 20;
++				start_time = rtw_get_current_time();
++				do {
++					rtw_hal_get_hwreg(padapter, HW_VAR_SYS_CLKR, &val8);
++					if (!(val8 & BIT(4))) { /* 0x08 bit4 =1 --> in 32k, bit4 = 0 --> leave 32k */
++						pwrpriv->cpwm = PS_STATE_S4;
++						break;
++					}
++					if (rtw_get_passing_time_ms(start_time) > delay_ms) {
++						RTW_INFO("%s: Wait for FW 32K leave more than %u ms!!!\n",
++							__FUNCTION__, delay_ms);
++						pdbgpriv->dbg_wow_leave_ps_fail_cnt++;
++						break;
++					}
++					rtw_usleep_os(100);
++				} while (1);
++			}
++#endif
++#ifdef CONFIG_LPS_PG
++			if (pwrpriv->lps_level == LPS_PG) {
++				lps_pg_hdl_id = LPS_PG_REDLEMEM;
++				rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));
++			}
++#endif
++#ifdef CONFIG_WOWLAN
++			if (pwrpriv->wowlan_mode == _TRUE)
++				rtw_hal_set_hwreg(padapter, HW_VAR_H2C_INACTIVE_IPS, (u8 *)(&ps_mode));
++#endif /* CONFIG_WOWLAN */
++
++			rtw_exec_lps(padapter, ps_mode);
++
++#ifdef CONFIG_LPS_PG
++			if (pwrpriv->lps_level == LPS_PG) {
++				lps_pg_hdl_id = LPS_PG_PHYDM_EN;
++				rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));
++			}
++#endif
++
++#ifdef CONFIG_LPS_POFF
++			rtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_SET_MODE,
++					  (u8 *)(&ps_mode));
++#endif /*CONFIG_LPS_POFF*/
++
++			pwrpriv->bFwCurrentInPSMode = _FALSE;
++
++#ifdef CONFIG_BT_COEXIST
++			rtw_btcoex_LpsNotify(padapter, ps_mode);
++#endif /* CONFIG_BT_COEXIST */
++		}
++	} else {
++		if ((PS_RDY_CHECK(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE))
++#ifdef CONFIG_BT_COEXIST
++		    || ((rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
++			&& (rtw_btcoex_IsLpsOn(padapter) == _TRUE))
++#endif
++#ifdef CONFIG_P2P_WOWLAN
++		    || (_TRUE == pwrpriv->wowlan_p2p_mode)
++#endif /* CONFIG_P2P_WOWLAN */
++#ifdef CONFIG_WOWLAN
++			|| WOWLAN_IS_STA_MIX_MODE(padapter)
++#endif /* CONFIG_WOWLAN */
++		   ) {
++			u8 pslv;
++
++			RTW_INFO(FUNC_ADPT_FMT" Enter 802.11 power save - %s\n",
++				 FUNC_ADPT_ARG(padapter), msg);
++
++			if (pwrpriv->lps_enter_cnts < UINT_MAX)
++				pwrpriv->lps_enter_cnts++;
++			else
++				pwrpriv->lps_enter_cnts = 0;
++#ifdef CONFIG_TDLS
++			for (i = 0; i < NUM_STA; i++) {
++				phead = &(pstapriv->sta_hash[i]);
++				plist = get_next(phead);
++
++				while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++					ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++
++					if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)
++						issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 1, 0, 0);
++					plist = get_next(plist);
++				}
++			}
++#endif /* CONFIG_TDLS */
++
++#ifdef CONFIG_BT_COEXIST
++			rtw_btcoex_LpsNotify(padapter, ps_mode);
++#endif /* CONFIG_BT_COEXIST */
++
++#ifdef CONFIG_LPS_POFF
++			rtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_SET_MODE,
++					  (u8 *)(&ps_mode));
++#endif /*CONFIG_LPS_POFF*/
++
++			pwrpriv->bFwCurrentInPSMode = _TRUE;
++			pwrpriv->pwr_mode = ps_mode;
++			pwrpriv->smart_ps = smart_ps;
++			pwrpriv->bcn_ant_mode = bcn_ant_mode;
++#ifdef CONFIG_LPS_PG
++			if (pwrpriv->lps_level == LPS_PG) {
++				lps_pg_hdl_id = LPS_PG_PHYDM_DIS;
++				rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));
++			}
++#endif
++
++#ifdef CONFIG_WMMPS_STA	
++			pwrpriv->wmm_smart_ps = pregistrypriv->wmm_smart_ps;
++#endif /* CONFIG_WMMPS_STA */
++			
++			rtw_exec_lps(padapter, ps_mode);
++			
++#ifdef CONFIG_WOWLAN
++			if (pwrpriv->wowlan_mode == _TRUE)
++				rtw_hal_set_hwreg(padapter, HW_VAR_H2C_INACTIVE_IPS, (u8 *)(&ps_mode));
++#endif /* CONFIG_WOWLAN */
++
++#ifdef CONFIG_P2P_PS
++			/* Set CTWindow after LPS */
++			if (pwdinfo->opp_ps == 1)
++				p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 0);
++#endif /* CONFIG_P2P_PS */
++
++			pslv = PS_STATE_S2;
++#ifdef CONFIG_LPS_LCLK
++			if (pwrpriv->alives == 0)
++				pslv = PS_STATE_S0;
++#endif /* CONFIG_LPS_LCLK */
++
++#ifdef CONFIG_BT_COEXIST
++			if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE)
++			    && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) {
++				u8 val8;
++
++				val8 = rtw_btcoex_LpsVal(padapter);
++				if (val8 & BIT(4))
++					pslv = PS_STATE_S2;
++
++			}
++#endif /* CONFIG_BT_COEXIST */
++
++			rtw_set_rpwm(padapter, pslv);
++		}
++	}
++
++#ifdef CONFIG_LPS_LCLK
++	_exit_pwrlock(&pwrpriv->lock);
++#endif
++
++}
++
++const char * const LPS_CTRL_PHYDM = "LPS_CTRL_PHYDM";
++
++/*
++ *	Description:
++ *		Enter the leisure power save mode.
++ *   */
++void LPS_Enter(PADAPTER padapter, const char *msg)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct pwrctrl_priv	*pwrpriv = dvobj_to_pwrctl(dvobj);
++	int i;
++	char buf[32] = {0};
++#ifdef DBG_LA_MODE
++	struct registry_priv *registry_par = &(padapter->registrypriv);
++#endif
++
++	/*	RTW_INFO("+LeisurePSEnter\n"); */
++	if (GET_HAL_DATA(padapter)->bFWReady == _FALSE)
++		return;
++
++#ifdef CONFIG_BT_COEXIST
++	if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
++		return;
++#endif
++
++#ifdef DBG_LA_MODE
++	if(registry_par->la_mode_en == 1) {
++		RTW_INFO("%s LA debug mode lps_leave \n", __func__);
++		return;
++	}
++#endif
++	/* Skip lps enter request if number of assocated adapters is not 1 */
++	if (rtw_mi_get_assoc_if_num(padapter) != 1)
++		return;
++
++#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
++	/* Skip lps enter request for adapter not port0 */
++	if (get_hw_port(padapter) != HW_PORT0)
++		return;
++#endif
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		if (PS_RDY_CHECK(dvobj->padapters[i]) == _FALSE)
++			return;
++	}
++
++#ifdef CONFIG_CLIENT_PORT_CFG
++	if ((rtw_hal_get_port(padapter) == CLT_PORT_INVALID) ||
++		get_clt_num(padapter) > MAX_CLIENT_PORT_NUM){
++		RTW_ERR(ADPT_FMT" cannot get client port or clt num(%d) over than 4\n", ADPT_ARG(padapter), get_clt_num(padapter));
++		return;
++	}
++#endif
++
++#ifdef CONFIG_P2P_PS
++	if (padapter->wdinfo.p2p_ps_mode == P2P_PS_NOA) {
++		return;/* supporting p2p client ps NOA via H2C_8723B_P2P_PS_OFFLOAD */
++	}
++#endif /* CONFIG_P2P_PS */
++
++	if (pwrpriv->bLeisurePs) {
++		/* Idle for a while if we connect to AP a while ago. */
++		if (pwrpriv->LpsIdleCount >= 2) { /* 4 Sec */
++			if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) {
++
++#ifdef CONFIG_WMMPS_STA
++				if (rtw_is_wmmps_mode(padapter))
++					msg = "WMMPS_IDLE";
++#endif /* CONFIG_WMMPS_STA */
++				
++				sprintf(buf, "WIFI-%s", msg);
++				pwrpriv->bpower_saving = _TRUE;
++				
++#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
++				pwrpriv->pwr_saving_start_time = rtw_get_current_time();
++#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
++
++				rtw_set_ps_mode(padapter, pwrpriv->power_mgnt, padapter->registrypriv.smart_ps, 0, buf);
++
++#ifdef CONFIG_PCI_DYNAMIC_ASPM
++				if (msg != LPS_CTRL_PHYDM)
++					rtw_pci_dynamic_aspm_set_mode(padapter, ASPM_MODE_PS);
++#endif
++			}
++		} else
++			pwrpriv->LpsIdleCount++;
++	}
++
++	/*	RTW_INFO("-LeisurePSEnter\n"); */
++
++}
++
++/*
++ *	Description:
++ *		Leave the leisure power save mode.
++ *   */
++void LPS_Leave(PADAPTER padapter, const char *msg)
++{
++#define LPS_LEAVE_TIMEOUT_MS 100
++
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct pwrctrl_priv	*pwrpriv = dvobj_to_pwrctl(dvobj);
++	char buf[32] = {0};
++#ifdef DBG_CHECK_FW_PS_STATE
++	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
++#endif
++
++
++	/*	RTW_INFO("+LeisurePSLeave\n"); */
++
++#ifdef CONFIG_BT_COEXIST
++	if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
++		return;
++#endif
++
++	if (pwrpriv->bLeisurePs) {
++		if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
++#ifdef CONFIG_PCI_DYNAMIC_ASPM
++			if (msg != LPS_CTRL_PHYDM)
++				rtw_pci_dynamic_aspm_set_mode(padapter, ASPM_MODE_PERF);
++#endif
++#ifdef CONFIG_WMMPS_STA
++			if (rtw_is_wmmps_mode(padapter))
++				msg = "WMMPS_BUSY";
++#endif /* CONFIG_WMMPS_STA */
++			
++			sprintf(buf, "WIFI-%s", msg);
++			rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, buf);
++
++#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS	
++			pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);
++#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
++		}
++	}
++
++	pwrpriv->bpower_saving = _FALSE;
++#ifdef DBG_CHECK_FW_PS_STATE
++	if (rtw_fw_ps_state(padapter) == _FAIL) {
++		RTW_INFO("leave lps, fw in 32k\n");
++		pdbgpriv->dbg_leave_lps_fail_cnt++;
++	}
++#endif /* DBG_CHECK_FW_PS_STATE
++ * 	RTW_INFO("-LeisurePSLeave\n"); */
++
++}
++
++#ifdef CONFIG_WOWLAN
++void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
++
++	if (wow_en) {
++		pwrpriv->lps_level_bk = pwrpriv->lps_level;
++		pwrpriv->lps_level = pwrpriv->wowlan_lps_level;
++		#ifdef CONFIG_LPS_1T1R
++		pwrpriv->lps_1t1r_bk = pwrpriv->lps_1t1r;
++		pwrpriv->lps_1t1r = pwrpriv->wowlan_lps_1t1r;
++		#endif
++	} else {
++		pwrpriv->lps_level = pwrpriv->lps_level_bk;
++		#ifdef CONFIG_LPS_1T1R
++		pwrpriv->lps_1t1r = pwrpriv->lps_1t1r_bk;
++		#endif
++	}
++}
++#endif /* CONFIG_WOWLAN */
++#endif /* CONFIG_LPS */
++
++void LeaveAllPowerSaveModeDirect(PADAPTER Adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);
++	PADAPTER pri_padapter = GET_PRIMARY_ADAPTER(Adapter);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter);
++#ifdef CONFIG_LPS_LCLK
++#ifndef CONFIG_DETECT_CPWM_BY_POLLING
++	u8 cpwm_orig;
++#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
++	u8 rpwm;
++#endif
++	int i;
++
++	RTW_INFO("%s.....\n", __FUNCTION__);
++
++	if (rtw_is_surprise_removed(Adapter)) {
++		RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=_TRUE Skip!\n", FUNC_ADPT_ARG(Adapter));
++		return;
++	}
++
++	if (rtw_mi_check_status(Adapter, MI_LINKED)) { /*connect*/
++
++		if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) {
++			RTW_INFO("%s: Driver Already Leave LPS\n", __FUNCTION__);
++			return;
++		}
++
++#ifdef CONFIG_LPS_LCLK
++		_enter_pwrlock(&pwrpriv->lock);
++
++#ifndef CONFIG_DETECT_CPWM_BY_POLLING
++		cpwm_orig = 0;
++		rtw_hal_get_hwreg(Adapter, HW_VAR_CPWM, &cpwm_orig);
++#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
++		rpwm = rtw_set_rpwm(Adapter, PS_STATE_S4);
++
++#ifndef CONFIG_DETECT_CPWM_BY_POLLING
++		if (rpwm != 0xFF && rpwm & PS_ACK)
++			rtw_cpwm_polling(Adapter, rpwm, cpwm_orig);
++#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
++
++		_exit_pwrlock(&pwrpriv->lock);
++#endif/*CONFIG_LPS_LCLK*/
++
++#ifdef CONFIG_P2P_PS
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			_adapter *iface = dvobj->padapters[i];
++			struct wifidirect_info *pwdinfo = &(iface->wdinfo);
++
++			if (pwdinfo->p2p_ps_mode > P2P_PS_NONE)
++				p2p_ps_wk_cmd(iface, P2P_PS_DISABLE, 0);
++		}
++#endif /* CONFIG_P2P_PS */
++
++#ifdef CONFIG_LPS
++		rtw_lps_ctrl_wk_cmd(pri_padapter, LPS_CTRL_LEAVE, RTW_CMDF_DIRECTLY);
++#endif
++	} else {
++		if (pwrpriv->rf_pwrstate == rf_off) {
++
++#if defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_RTL8188E)
++#ifdef CONFIG_IPS
++			if (_FALSE == ips_leave(pri_padapter))
++				RTW_INFO("======> ips_leave fail.............\n");
++#endif
++#endif /* CONFIG_SWLPS_IN_IPS || (CONFIG_PLATFORM_SPRD && CONFIG_RTL8188E) */
++
++		}
++	}
++
++}
++
++/*
++ * Description: Leave all power save mode: LPS, FwLPS, IPS if needed.
++ * Move code to function by tynli. 2010.03.26.
++ *   */
++void LeaveAllPowerSaveMode(PADAPTER Adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);
++	u8	enqueue = 0;
++	int i;
++
++	#ifndef CONFIG_NEW_NETDEV_HDL
++	if (_FALSE == Adapter->bup) {
++		RTW_INFO(FUNC_ADPT_FMT ": bup=%d Skip!\n",
++			 FUNC_ADPT_ARG(Adapter), Adapter->bup);
++		return;
++	}
++	#endif
++
++/*	RTW_INFO(FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(Adapter));*/
++
++	if (rtw_is_surprise_removed(Adapter)) {
++		RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=_TRUE Skip!\n", FUNC_ADPT_ARG(Adapter));
++		return;
++	}
++
++	if (rtw_mi_get_assoc_if_num(Adapter)) {
++		/* connect */
++#ifdef CONFIG_LPS_LCLK
++		enqueue = 1;
++#endif
++
++#ifdef CONFIG_P2P_PS
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			_adapter *iface = dvobj->padapters[i];
++			struct wifidirect_info *pwdinfo = &(iface->wdinfo);
++
++			if (pwdinfo->p2p_ps_mode > P2P_PS_NONE)
++				p2p_ps_wk_cmd(iface, P2P_PS_DISABLE, enqueue);
++		}
++#endif /* CONFIG_P2P_PS */
++
++#ifdef CONFIG_LPS
++		rtw_lps_ctrl_wk_cmd(Adapter, LPS_CTRL_LEAVE, enqueue ? 0 : RTW_CMDF_DIRECTLY);
++#endif
++
++#ifdef CONFIG_LPS_LCLK
++		LPS_Leave_check(Adapter);
++#endif
++	} else {
++		if (adapter_to_pwrctl(Adapter)->rf_pwrstate == rf_off) {
++			
++#if defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) || (defined(CONFIG_PLATFORM_SPRD) && defined(CONFIG_RTL8188E))
++#ifdef CONFIG_IPS
++			if (_FALSE == ips_leave(Adapter))
++				RTW_INFO("======> ips_leave fail.............\n");
++#endif
++#endif /* CONFIG_SWLPS_IN_IPS || (CONFIG_PLATFORM_SPRD && CONFIG_RTL8188E) */
++			
++		}
++	}
++
++}
++
++#ifdef CONFIG_LPS_LCLK
++void LPS_Leave_check(
++	PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrpriv;
++	systime	start_time;
++	u8	bReady;
++
++
++	pwrpriv = adapter_to_pwrctl(padapter);
++
++	bReady = _FALSE;
++	start_time = rtw_get_current_time();
++
++	rtw_yield_os();
++
++	while (1) {
++		_enter_pwrlock(&pwrpriv->lock);
++
++		if (rtw_is_surprise_removed(padapter)
++		    || (!rtw_is_hw_init_completed(padapter))
++#ifdef CONFIG_USB_HCI
++		    || rtw_is_drv_stopped(padapter)
++#endif
++		    || (pwrpriv->pwr_mode == PS_MODE_ACTIVE)
++		   )
++			bReady = _TRUE;
++
++		_exit_pwrlock(&pwrpriv->lock);
++
++		if (_TRUE == bReady)
++			break;
++
++		if (rtw_get_passing_time_ms(start_time) > 100) {
++			RTW_ERR("Wait for cpwm event  than 100 ms!!!\n");
++			break;
++		}
++		rtw_msleep_os(1);
++	}
++
++}
++
++/*
++ * Caller:ISR handler...
++ *
++ * This will be called when CPWM interrupt is up.
++ *
++ * using to update cpwn of drv; and drv willl make a decision to up or down pwr level
++ */
++void cpwm_int_hdl(
++	PADAPTER padapter,
++	struct reportpwrstate_parm *preportpwrstate)
++{
++	struct pwrctrl_priv *pwrpriv;
++
++	if (!padapter)
++		goto exit;
++
++	if (RTW_CANNOT_RUN(padapter))
++		goto exit;
++
++	pwrpriv = adapter_to_pwrctl(padapter);
++#if 0
++	if (pwrpriv->cpwm_tog == (preportpwrstate->state & PS_TOGGLE)) {
++		goto exit;
++	}
++#endif
++
++	_enter_pwrlock(&pwrpriv->lock);
++
++#ifdef CONFIG_LPS_RPWM_TIMER
++	if (pwrpriv->rpwm < PS_STATE_S2) {
++		RTW_INFO("%s: Redundant CPWM Int. RPWM=0x%02X CPWM=0x%02x\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm);
++		_exit_pwrlock(&pwrpriv->lock);
++		goto exit;
++	}
++#endif /* CONFIG_LPS_RPWM_TIMER */
++
++	pwrpriv->cpwm = PS_STATE(preportpwrstate->state);
++	pwrpriv->cpwm_tog = preportpwrstate->state & PS_TOGGLE;
++
++	if (pwrpriv->cpwm >= PS_STATE_S2) {
++		if (pwrpriv->alives & CMD_ALIVE)
++			_rtw_up_sema(&padapter->cmdpriv.cmd_queue_sema);
++
++		if (pwrpriv->alives & XMIT_ALIVE)
++			_rtw_up_sema(&padapter->xmitpriv.xmit_sema);
++	}
++
++	_exit_pwrlock(&pwrpriv->lock);
++
++exit:
++	return;
++}
++
++static void cpwm_event_callback(struct work_struct *work)
++{
++	struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, cpwm_event);
++	struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
++	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
++	struct reportpwrstate_parm report;
++
++	/* RTW_INFO("%s\n",__FUNCTION__); */
++
++	report.state = PS_STATE_S2;
++	cpwm_int_hdl(adapter, &report);
++}
++
++static void dma_event_callback(struct work_struct *work)
++{
++	struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, dma_event);
++	struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
++	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
++
++	rtw_unregister_tx_alive(adapter);
++}
++
++#ifdef CONFIG_LPS_RPWM_TIMER
++
++#define DBG_CPWM_CHK_FAIL
++#if defined(DBG_CPWM_CHK_FAIL) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)) 
++#define CPU_EXCEPTION_CODE 0xFAFAFAFA
++static void rtw_cpwm_chk_fail_debug(_adapter *padapter)
++{
++	u32 cpu_state;
++
++	cpu_state = rtw_read32(padapter, 0x10FC);
++
++	RTW_INFO("[PS-DBG] Reg_10FC =0x%08x\n", cpu_state);
++	RTW_INFO("[PS-DBG] Reg_10F8 =0x%08x\n", rtw_read32(padapter, 0x10F8));
++	RTW_INFO("[PS-DBG] Reg_11F8 =0x%08x\n", rtw_read32(padapter, 0x11F8));
++	RTW_INFO("[PS-DBG] Reg_4A4 =0x%08x\n", rtw_read32(padapter, 0x4A4));
++	RTW_INFO("[PS-DBG] Reg_4A8 =0x%08x\n", rtw_read32(padapter, 0x4A8));
++
++	if (cpu_state == CPU_EXCEPTION_CODE) {
++		RTW_INFO("[PS-DBG] Reg_48C =0x%08x\n", rtw_read32(padapter, 0x48C));
++		RTW_INFO("[PS-DBG] Reg_490 =0x%08x\n", rtw_read32(padapter, 0x490));
++		RTW_INFO("[PS-DBG] Reg_494 =0x%08x\n", rtw_read32(padapter, 0x494));
++		RTW_INFO("[PS-DBG] Reg_498 =0x%08x\n", rtw_read32(padapter, 0x498));
++		RTW_INFO("[PS-DBG] Reg_49C =0x%08x\n", rtw_read32(padapter, 0x49C));
++		RTW_INFO("[PS-DBG] Reg_4A0 =0x%08x\n", rtw_read32(padapter, 0x4A0));
++		RTW_INFO("[PS-DBG] Reg_1BC =0x%08x\n", rtw_read32(padapter, 0x1BC));
++
++		RTW_INFO("[PS-DBG] Reg_008 =0x%08x\n", rtw_read32(padapter, 0x08));
++		RTW_INFO("[PS-DBG] Reg_2F0 =0x%08x\n", rtw_read32(padapter, 0x2F0));
++		RTW_INFO("[PS-DBG] Reg_2F4 =0x%08x\n", rtw_read32(padapter, 0x2F4));
++		RTW_INFO("[PS-DBG] Reg_2F8 =0x%08x\n", rtw_read32(padapter, 0x2F8));
++		RTW_INFO("[PS-DBG] Reg_2FC =0x%08x\n", rtw_read32(padapter, 0x2FC));
++
++		rtw_dump_fifo(RTW_DBGDUMP, padapter, 5, 0, 3072);
++	}
++}
++#endif
++static void rpwmtimeout_workitem_callback(struct work_struct *work)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *dvobj;
++	struct pwrctrl_priv *pwrpriv;
++
++
++	pwrpriv = container_of(work, struct pwrctrl_priv, rpwmtimeoutwi);
++	dvobj = pwrctl_to_dvobj(pwrpriv);
++	padapter = dvobj_get_primary_adapter(dvobj);
++
++	if (!padapter)
++		return;
++
++	if (RTW_CANNOT_RUN(padapter))
++		return;
++
++	_enter_pwrlock(&pwrpriv->lock);
++	if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) {
++		RTW_INFO("%s: rpwm=0x%02X cpwm=0x%02X CPWM done!\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm);
++		goto exit;
++	}
++
++	if (pwrpriv->rpwm_retry++ < LPS_RPWM_RETRY_CNT) {
++		u8 rpwm = (pwrpriv->rpwm | pwrpriv->tog | PS_ACK);
++
++		rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));
++
++		pwrpriv->tog += 0x80;
++		_set_timer(&pwrpriv->pwr_rpwm_timer, LPS_CPWM_TIMEOUT_MS);
++		goto exit;
++	}
++
++	pwrpriv->rpwm_retry = 0;
++	_exit_pwrlock(&pwrpriv->lock);
++
++#if defined(DBG_CPWM_CHK_FAIL) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C))
++	RTW_INFO("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm);
++	rtw_cpwm_chk_fail_debug(padapter);
++#endif
++
++	if (rtw_read8(padapter, 0x100) != 0xEA) {
++#if 1
++		struct reportpwrstate_parm report;
++
++		report.state = PS_STATE_S2;
++		RTW_INFO("\n%s: FW already leave 32K!\n\n", __func__);
++		cpwm_int_hdl(padapter, &report);
++#else
++		RTW_INFO("\n%s: FW already leave 32K!\n\n", __func__);
++		cpwm_event_callback(&pwrpriv->cpwm_event);
++#endif
++		return;
++	}
++
++	_enter_pwrlock(&pwrpriv->lock);
++
++	if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) {
++		RTW_INFO("%s: cpwm=%d, nothing to do!\n", __func__, pwrpriv->cpwm);
++		goto exit;
++	}
++	pwrpriv->brpwmtimeout = _TRUE;
++	rtw_set_rpwm(padapter, pwrpriv->rpwm);
++	pwrpriv->brpwmtimeout = _FALSE;
++
++exit:
++	_exit_pwrlock(&pwrpriv->lock);
++}
++
++/*
++ * This function is a timer handler, can't do any IO in it.
++ */
++static void pwr_rpwm_timeout_handler(void *FunctionContext)
++{
++	PADAPTER padapter;
++	struct pwrctrl_priv *pwrpriv;
++
++
++	padapter = (PADAPTER)FunctionContext;
++	pwrpriv = adapter_to_pwrctl(padapter);
++	if (!padapter)
++		return;
++
++	if (RTW_CANNOT_RUN(padapter))
++		return;
++
++	RTW_INFO("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm);
++
++	if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) {
++		RTW_INFO("+%s: cpwm=%d, nothing to do!\n", __func__, pwrpriv->cpwm);
++		return;
++	}
++
++	_set_workitem(&pwrpriv->rpwmtimeoutwi);
++}
++#endif /* CONFIG_LPS_RPWM_TIMER */
++
++__inline static void register_task_alive(struct pwrctrl_priv *pwrctrl, u32 tag)
++{
++	pwrctrl->alives |= tag;
++}
++
++__inline static void unregister_task_alive(struct pwrctrl_priv *pwrctrl, u32 tag)
++{
++	pwrctrl->alives &= ~tag;
++}
++
++
++/*
++ * Description:
++ *	Check if the fw_pwrstate is okay for I/O.
++ *	If not (cpwm is less than S2), then the sub-routine
++ *	will raise the cpwm to be greater than or equal to S2.
++ *
++ *	Calling Context: Passive
++ *
++ *	Constraint:
++ *		1. this function will request pwrctrl->lock
++ *
++ * Return Value:
++ *	_SUCCESS	hardware is ready for I/O
++ *	_FAIL		can't I/O right now
++ */
++s32 rtw_register_task_alive(PADAPTER padapter, u32 task)
++{
++	s32 res;
++	struct pwrctrl_priv *pwrctrl;
++	u8 pslv;
++
++
++	res = _SUCCESS;
++	pwrctrl = adapter_to_pwrctl(padapter);
++	pslv = PS_STATE_S2;
++
++	_enter_pwrlock(&pwrctrl->lock);
++
++	register_task_alive(pwrctrl, task);
++
++	if (pwrctrl->bFwCurrentInPSMode == _TRUE) {
++
++		if (pwrctrl->cpwm < pslv) {
++			if (pwrctrl->cpwm < PS_STATE_S2)
++				res = _FAIL;
++			if (pwrctrl->rpwm < pslv)
++				rtw_set_rpwm(padapter, pslv);
++		}
++	}
++
++	_exit_pwrlock(&pwrctrl->lock);
++
++#ifdef CONFIG_DETECT_CPWM_BY_POLLING
++	if (_FAIL == res) {
++		if (pwrctrl->cpwm >= PS_STATE_S2)
++			res = _SUCCESS;
++	}
++#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
++
++
++	return res;
++}
++
++/*
++ * Description:
++ *	If task is done, call this func. to power down firmware again.
++ *
++ *	Constraint:
++ *		1. this function will request pwrctrl->lock
++ *
++ * Return Value:
++ *	none
++ */
++void rtw_unregister_task_alive(PADAPTER padapter, u32 task)
++{
++	struct pwrctrl_priv *pwrctrl;
++	u8 pslv;
++
++
++	pwrctrl = adapter_to_pwrctl(padapter);
++	pslv = PS_STATE_S0;
++
++#ifdef CONFIG_BT_COEXIST
++	if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE)
++	    && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) {
++		u8 val8;
++
++		val8 = rtw_btcoex_LpsVal(padapter);
++		if (val8 & BIT(4))
++			pslv = PS_STATE_S2;
++
++	}
++#endif /* CONFIG_BT_COEXIST */
++
++	_enter_pwrlock(&pwrctrl->lock);
++
++	unregister_task_alive(pwrctrl, task);
++
++	if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE)
++	    && (pwrctrl->bFwCurrentInPSMode == _TRUE)) {
++
++		if (pwrctrl->cpwm > pslv) {
++			if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0))
++				rtw_set_rpwm(padapter, pslv);
++		}
++	}
++
++	_exit_pwrlock(&pwrctrl->lock);
++
++}
++
++/*
++ * Caller: rtw_xmit_thread
++ *
++ * Check if the fw_pwrstate is okay for xmit.
++ * If not (cpwm is less than S3), then the sub-routine
++ * will raise the cpwm to be greater than or equal to S3.
++ *
++ * Calling Context: Passive
++ *
++ * Return Value:
++ *	 _SUCCESS	rtw_xmit_thread can write fifo/txcmd afterwards.
++ *	 _FAIL		rtw_xmit_thread can not do anything.
++ */
++s32 rtw_register_tx_alive(PADAPTER padapter)
++{
++	s32 res;
++	struct pwrctrl_priv *pwrctrl;
++	u8 pslv;
++
++
++	res = _SUCCESS;
++	pwrctrl = adapter_to_pwrctl(padapter);
++	pslv = PS_STATE_S2;
++
++	_enter_pwrlock(&pwrctrl->lock);
++
++	register_task_alive(pwrctrl, XMIT_ALIVE);
++
++	if (pwrctrl->bFwCurrentInPSMode == _TRUE) {
++
++		if (pwrctrl->cpwm < pslv) {
++			if (pwrctrl->cpwm < PS_STATE_S2)
++				res = _FAIL;
++			if (pwrctrl->rpwm < pslv)
++				rtw_set_rpwm(padapter, pslv);
++		}
++	}
++
++	_exit_pwrlock(&pwrctrl->lock);
++
++#ifdef CONFIG_DETECT_CPWM_BY_POLLING
++	if (_FAIL == res) {
++		if (pwrctrl->cpwm >= PS_STATE_S2)
++			res = _SUCCESS;
++	}
++#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
++
++
++	return res;
++}
++
++/*
++ * Caller: rtw_cmd_thread
++ *
++ * Check if the fw_pwrstate is okay for issuing cmd.
++ * If not (cpwm should be is less than S2), then the sub-routine
++ * will raise the cpwm to be greater than or equal to S2.
++ *
++ * Calling Context: Passive
++ *
++ * Return Value:
++ *	_SUCCESS	rtw_cmd_thread can issue cmds to firmware afterwards.
++ *	_FAIL		rtw_cmd_thread can not do anything.
++ */
++s32 rtw_register_cmd_alive(PADAPTER padapter)
++{
++	s32 res;
++	struct pwrctrl_priv *pwrctrl;
++	u8 pslv;
++
++
++	res = _SUCCESS;
++	pwrctrl = adapter_to_pwrctl(padapter);
++	pslv = PS_STATE_S2;
++
++	_enter_pwrlock(&pwrctrl->lock);
++
++	register_task_alive(pwrctrl, CMD_ALIVE);
++
++	if (pwrctrl->bFwCurrentInPSMode == _TRUE) {
++
++		if (pwrctrl->cpwm < pslv) {
++			if (pwrctrl->cpwm < PS_STATE_S2)
++				res = _FAIL;
++			if (pwrctrl->rpwm < pslv)
++				rtw_set_rpwm(padapter, pslv);
++		}
++	}
++
++	_exit_pwrlock(&pwrctrl->lock);
++
++#ifdef CONFIG_DETECT_CPWM_BY_POLLING
++	if (_FAIL == res) {
++		if (pwrctrl->cpwm >= PS_STATE_S2)
++			res = _SUCCESS;
++	}
++#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
++
++
++	return res;
++}
++
++/*
++ * Caller: rx_isr
++ *
++ * Calling Context: Dispatch/ISR
++ *
++ * Return Value:
++ *	_SUCCESS
++ *	_FAIL
++ */
++s32 rtw_register_rx_alive(PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrctrl;
++
++
++	pwrctrl = adapter_to_pwrctl(padapter);
++
++	_enter_pwrlock(&pwrctrl->lock);
++
++	register_task_alive(pwrctrl, RECV_ALIVE);
++
++	_exit_pwrlock(&pwrctrl->lock);
++
++
++	return _SUCCESS;
++}
++
++/*
++ * Caller: evt_isr or evt_thread
++ *
++ * Calling Context: Dispatch/ISR or Passive
++ *
++ * Return Value:
++ *	_SUCCESS
++ *	_FAIL
++ */
++s32 rtw_register_evt_alive(PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrctrl;
++
++
++	pwrctrl = adapter_to_pwrctl(padapter);
++
++	_enter_pwrlock(&pwrctrl->lock);
++
++	register_task_alive(pwrctrl, EVT_ALIVE);
++
++	_exit_pwrlock(&pwrctrl->lock);
++
++
++	return _SUCCESS;
++}
++
++/*
++ * Caller: ISR
++ *
++ * If ISR's txdone,
++ * No more pkts for TX,
++ * Then driver shall call this fun. to power down firmware again.
++ */
++void rtw_unregister_tx_alive(PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrctrl;
++	_adapter *iface;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	u8 pslv, i;
++
++
++	pwrctrl = adapter_to_pwrctl(padapter);
++	pslv = PS_STATE_S0;
++
++#ifdef CONFIG_BT_COEXIST
++	if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE)
++	    && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) {
++		u8 val8;
++
++		val8 = rtw_btcoex_LpsVal(padapter);
++		if (val8 & BIT(4))
++			pslv = PS_STATE_S2;
++
++	}
++#endif /* CONFIG_BT_COEXIST */
++
++#ifdef CONFIG_P2P_PS
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if ((iface) && rtw_is_adapter_up(iface)) {
++			if (iface->wdinfo.p2p_ps_mode > P2P_PS_NONE) {
++				pslv = PS_STATE_S2;
++				break;
++			}
++		}
++	}
++#endif
++	_enter_pwrlock(&pwrctrl->lock);
++
++	unregister_task_alive(pwrctrl, XMIT_ALIVE);
++
++	if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE)
++	    && (pwrctrl->bFwCurrentInPSMode == _TRUE)) {
++
++		if (pwrctrl->cpwm > pslv) {
++			if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0))
++				rtw_set_rpwm(padapter, pslv);
++		}
++	}
++
++	_exit_pwrlock(&pwrctrl->lock);
++
++}
++
++/*
++ * Caller: ISR
++ *
++ * If all commands have been done,
++ * and no more command to do,
++ * then driver shall call this fun. to power down firmware again.
++ */
++void rtw_unregister_cmd_alive(PADAPTER padapter)
++{
++	_adapter *iface;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct pwrctrl_priv *pwrctrl;
++	u8 pslv, i;
++
++
++	pwrctrl = adapter_to_pwrctl(padapter);
++	pslv = PS_STATE_S0;
++
++#ifdef CONFIG_BT_COEXIST
++	if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE)
++	    && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) {
++		u8 val8;
++
++		val8 = rtw_btcoex_LpsVal(padapter);
++		if (val8 & BIT(4))
++			pslv = PS_STATE_S2;
++
++	}
++#endif /* CONFIG_BT_COEXIST */
++
++#ifdef CONFIG_P2P_PS
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if ((iface) && rtw_is_adapter_up(iface)) {
++			if (iface->wdinfo.p2p_ps_mode > P2P_PS_NONE) {
++				pslv = PS_STATE_S2;
++				break;
++			}
++		}
++	}
++#endif
++
++	_enter_pwrlock(&pwrctrl->lock);
++
++	unregister_task_alive(pwrctrl, CMD_ALIVE);
++
++	if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE)
++	    && (pwrctrl->bFwCurrentInPSMode == _TRUE)) {
++
++		if (pwrctrl->cpwm > pslv) {
++			if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0))
++				rtw_set_rpwm(padapter, pslv);
++		}
++	}
++
++	_exit_pwrlock(&pwrctrl->lock);
++
++}
++
++/*
++ * Caller: ISR
++ */
++void rtw_unregister_rx_alive(PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrctrl;
++
++
++	pwrctrl = adapter_to_pwrctl(padapter);
++
++	_enter_pwrlock(&pwrctrl->lock);
++
++	unregister_task_alive(pwrctrl, RECV_ALIVE);
++
++
++	_exit_pwrlock(&pwrctrl->lock);
++
++}
++
++void rtw_unregister_evt_alive(PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrctrl;
++
++
++	pwrctrl = adapter_to_pwrctl(padapter);
++
++	unregister_task_alive(pwrctrl, EVT_ALIVE);
++
++
++	_exit_pwrlock(&pwrctrl->lock);
++
++}
++#endif	/* CONFIG_LPS_LCLK */
++
++#ifdef CONFIG_RESUME_IN_WORKQUEUE
++	static void resume_workitem_callback(struct work_struct *work);
++#endif /* CONFIG_RESUME_IN_WORKQUEUE */
++
++void rtw_init_pwrctrl_priv(PADAPTER padapter)
++{
++#ifdef CONFIG_LPS_1T1R
++#define LPS_1T1R_FMT ", LPS_1T1R=%d"
++#define LPS_1T1R_ARG , pwrctrlpriv->lps_1t1r
++#else
++#define LPS_1T1R_FMT ""
++#define LPS_1T1R_ARG
++#endif
++
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++#ifdef CONFIG_WOWLAN
++	struct registry_priv  *registry_par = &padapter->registrypriv;
++#endif
++#ifdef CONFIG_GPIO_WAKEUP
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++#endif
++
++#if defined(CONFIG_CONCURRENT_MODE)
++	if (!is_primary_adapter(padapter))
++		return;
++#endif
++
++	_init_pwrlock(&pwrctrlpriv->lock);
++	_init_pwrlock(&pwrctrlpriv->check_32k_lock);
++	pwrctrlpriv->rf_pwrstate = rf_on;
++	pwrctrlpriv->ips_enter_cnts = 0;
++	pwrctrlpriv->ips_leave_cnts = 0;
++	pwrctrlpriv->lps_enter_cnts = 0;
++	pwrctrlpriv->lps_leave_cnts = 0;
++	pwrctrlpriv->bips_processing = _FALSE;
++#ifdef CONFIG_LPS_CHK_BY_TP
++	pwrctrlpriv->lps_chk_by_tp = padapter->registrypriv.lps_chk_by_tp;
++	pwrctrlpriv->lps_tx_tp_th = LPS_TX_TP_TH;
++	pwrctrlpriv->lps_rx_tp_th = LPS_RX_TP_TH;
++	pwrctrlpriv->lps_bi_tp_th = LPS_BI_TP_TH;
++	pwrctrlpriv->lps_chk_cnt = pwrctrlpriv->lps_chk_cnt_th = LPS_TP_CHK_CNT;
++	pwrctrlpriv->lps_tx_pkts = LPS_CHK_PKTS_TX;
++	pwrctrlpriv->lps_rx_pkts = LPS_CHK_PKTS_RX;
++#endif
++
++	pwrctrlpriv->ips_mode = padapter->registrypriv.ips_mode;
++	pwrctrlpriv->ips_mode_req = padapter->registrypriv.ips_mode;
++	pwrctrlpriv->ips_deny_time = rtw_get_current_time();
++	pwrctrlpriv->lps_level = padapter->registrypriv.lps_level;
++#ifdef CONFIG_LPS_1T1R
++	pwrctrlpriv->lps_1t1r = padapter->registrypriv.lps_1t1r;
++#endif
++
++	pwrctrlpriv->pwr_state_check_interval = RTW_PWR_STATE_CHK_INTERVAL;
++	pwrctrlpriv->pwr_state_check_cnts = 0;
++	pwrctrlpriv->bInSuspend = _FALSE;
++	pwrctrlpriv->bkeepfwalive = _FALSE;
++	pwrctrlpriv->LpsIdleCount = 0;
++
++	/* pwrctrlpriv->FWCtrlPSMode =padapter->registrypriv.power_mgnt; */ /* PS_MODE_MIN; */
++	if (padapter->registrypriv.mp_mode == 1)
++		pwrctrlpriv->power_mgnt = PS_MODE_ACTIVE ;
++	else
++		pwrctrlpriv->power_mgnt = padapter->registrypriv.power_mgnt; /* PS_MODE_MIN; */
++	pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt) ? _TRUE : _FALSE;
++
++	pwrctrlpriv->bFwCurrentInPSMode = _FALSE;
++	pwrctrlpriv->lps_deny_time = rtw_get_current_time();
++
++	pwrctrlpriv->rpwm = 0;
++	pwrctrlpriv->cpwm = PS_STATE_S4;
++
++	pwrctrlpriv->pwr_mode = PS_MODE_ACTIVE;
++	pwrctrlpriv->smart_ps = padapter->registrypriv.smart_ps;
++	pwrctrlpriv->bcn_ant_mode = 0;
++	pwrctrlpriv->dtim = 0;
++
++	pwrctrlpriv->tog = 0x80;
++	pwrctrlpriv->rpwm_retry = 0;
++
++	RTW_INFO("%s: IPS_mode=%d, LPS_mode=%d, LPS_level=%d"LPS_1T1R_FMT"\n", 
++		__func__, pwrctrlpriv->ips_mode, pwrctrlpriv->power_mgnt, pwrctrlpriv->lps_level
++		LPS_1T1R_ARG
++	);
++
++#ifdef CONFIG_LPS_LCLK
++	rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&pwrctrlpriv->rpwm));
++
++	_init_workitem(&pwrctrlpriv->cpwm_event, cpwm_event_callback, NULL);
++
++	_init_workitem(&pwrctrlpriv->dma_event, dma_event_callback, NULL);
++
++#ifdef CONFIG_LPS_RPWM_TIMER
++	pwrctrlpriv->brpwmtimeout = _FALSE;
++	_init_workitem(&pwrctrlpriv->rpwmtimeoutwi, rpwmtimeout_workitem_callback, NULL);
++	rtw_init_timer(&pwrctrlpriv->pwr_rpwm_timer, padapter, pwr_rpwm_timeout_handler, padapter);
++#endif /* CONFIG_LPS_RPWM_TIMER */
++#endif /* CONFIG_LPS_LCLK */
++
++#ifdef CONFIG_LPS_PG
++	pwrctrlpriv->lpspg_info.name = "LPSPG_INFO";
++	#ifdef CONFIG_RTL8822C
++	pwrctrlpriv->lpspg_dpk_info.name = "LPSPG_DPK_INFO";
++	pwrctrlpriv->lpspg_iqk_info.name = "LPSPG_IQK_INFO";
++	#endif
++#endif
++
++	rtw_init_timer(&pwrctrlpriv->pwr_state_check_timer, padapter, pwr_state_check_handler, padapter);
++
++	pwrctrlpriv->wowlan_mode = _FALSE;
++	pwrctrlpriv->wowlan_ap_mode = _FALSE;
++	pwrctrlpriv->wowlan_p2p_mode = _FALSE;
++	pwrctrlpriv->wowlan_in_resume = _FALSE;
++	pwrctrlpriv->wowlan_last_wake_reason = 0;
++
++#ifdef CONFIG_RESUME_IN_WORKQUEUE
++	_init_workitem(&pwrctrlpriv->resume_work, resume_workitem_callback, NULL);
++	pwrctrlpriv->rtw_workqueue = create_singlethread_workqueue("rtw_workqueue");
++#endif /* CONFIG_RESUME_IN_WORKQUEUE */
++
++#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
++	pwrctrlpriv->early_suspend.suspend = NULL;
++	rtw_register_early_suspend(pwrctrlpriv);
++#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */
++
++#ifdef CONFIG_GPIO_WAKEUP
++	pwrctrlpriv->wowlan_gpio_index = WAKEUP_GPIO_IDX;
++	/* set output low state in initial */
++	pwrctrlpriv->wowlan_gpio_output_state = GPIO_OUTPUT_LOW;
++	/*default low active*/
++	pwrctrlpriv->is_high_active = HIGH_ACTIVE_DEV2HST;
++	pwrctrlpriv->hst2dev_high_active = HIGH_ACTIVE_HST2DEV;
++
++#if (defined(CONFIG_RTL8192F) && defined(CONFIG_USB_HCI) && defined(CONFIG_BT_COEXIST))
++	if (pHalData->EEPROMBluetoothCoexist == _TRUE) {
++		/* for 8725AU case */
++		pwrctrlpriv->wowlan_gpio_index = WAKEUP_GPIO_IDX_8725AU;
++		pwrctrlpriv->is_high_active = HIGH_ACTIVE_DEV2HST_8725AU;
++	}
++#endif
++#ifdef CONFIG_RTW_ONE_PIN_GPIO
++	rtw_hal_switch_gpio_wl_ctrl(padapter, pwrctrlpriv->wowlan_gpio_index, _TRUE);
++	rtw_hal_set_input_gpio(padapter, pwrctrlpriv->wowlan_gpio_index);
++#else
++	#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
++	if (pwrctrlpriv->is_high_active == 0)
++		rtw_hal_set_input_gpio(padapter, pwrctrlpriv->wowlan_gpio_index);
++	else
++		rtw_hal_set_output_gpio(padapter, pwrctrlpriv->wowlan_gpio_index,
++			GPIO_OUTPUT_LOW);
++	#else
++	rtw_hal_set_output_gpio(padapter, pwrctrlpriv->wowlan_gpio_index
++		, pwrctrlpriv->wowlan_gpio_output_state);
++	rtw_hal_switch_gpio_wl_ctrl(padapter, pwrctrlpriv->wowlan_gpio_index, _TRUE);
++	RTW_INFO("%s: set GPIO_%d to OUTPUT %s state in initial and %s_ACTIVE.\n",
++		 __func__, pwrctrlpriv->wowlan_gpio_index, 
++		 pwrctrlpriv->wowlan_gpio_output_state ? "HIGH" : "LOW",
++		 pwrctrlpriv->is_high_active ? "HIGI" : "LOW");
++	#endif /*CONFIG_WAKEUP_GPIO_INPUT_MODE*/
++#endif /* CONFIG_RTW_ONE_PIN_GPIO */
++#endif /* CONFIG_GPIO_WAKEUP */
++
++#ifdef CONFIG_WOWLAN
++#ifdef CONFIG_LPS_1T1R
++#define WOW_LPS_1T1R_FMT ", WOW_LPS_1T1R=%d"
++#define WOW_LPS_1T1R_ARG , pwrctrlpriv->wowlan_lps_1t1r
++#else
++#define WOW_LPS_1T1R_FMT ""
++#define WOW_LPS_1T1R_ARG
++#endif
++
++	pwrctrlpriv->wowlan_power_mgmt = padapter->registrypriv.wow_power_mgnt;
++	pwrctrlpriv->wowlan_lps_level = padapter->registrypriv.wow_lps_level;
++#ifdef CONFIG_LPS_1T1R
++	pwrctrlpriv->wowlan_lps_1t1r = padapter->registrypriv.wow_lps_1t1r;
++#endif
++
++	RTW_INFO("%s: WOW_LPS_mode=%d, WOW_LPS_level=%d"WOW_LPS_1T1R_FMT"\n",
++		__func__, pwrctrlpriv->wowlan_power_mgmt, pwrctrlpriv->wowlan_lps_level
++		WOW_LPS_1T1R_ARG
++	);
++
++	if (registry_par->wakeup_event & BIT(1))
++		pwrctrlpriv->default_patterns_en = _TRUE;
++	else
++		pwrctrlpriv->default_patterns_en = _FALSE;
++
++	rtw_wow_pattern_sw_reset(padapter);
++#ifdef CONFIG_PNO_SUPPORT
++	pwrctrlpriv->pno_inited = _FALSE;
++	pwrctrlpriv->pnlo_info = NULL;
++	pwrctrlpriv->pscan_info = NULL;
++	pwrctrlpriv->pno_ssid_list = NULL;
++#endif /* CONFIG_PNO_SUPPORT */
++#ifdef CONFIG_WOW_PATTERN_HW_CAM
++	_rtw_mutex_init(&pwrctrlpriv->wowlan_pattern_cam_mutex);
++#endif
++	pwrctrlpriv->wowlan_aoac_rpt_loc = 0;
++#endif /* CONFIG_WOWLAN */
++
++#ifdef CONFIG_LPS_POFF
++	rtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_INIT, 0);
++#endif
++
++#ifdef CONFIG_LPS_ACK
++	_rtw_mutex_init(&pwrctrlpriv->lps_ack_mutex);
++	pwrctrlpriv->lps_ack_status = -1;
++#endif /* CONFIG_LPS_ACK */
++}
++
++
++void rtw_free_pwrctrl_priv(PADAPTER adapter)
++{
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter);
++
++#if defined(CONFIG_CONCURRENT_MODE)
++	if (!is_primary_adapter(adapter))
++		return;
++#endif
++
++
++	/* _rtw_memset((unsigned char *)pwrctrlpriv, 0, sizeof(struct pwrctrl_priv)); */
++
++
++#ifdef CONFIG_RESUME_IN_WORKQUEUE
++	if (pwrctrlpriv->rtw_workqueue) {
++		flush_workqueue(pwrctrlpriv->rtw_workqueue);
++		destroy_workqueue(pwrctrlpriv->rtw_workqueue);
++	}
++#endif
++
++#ifdef CONFIG_LPS_POFF
++	rtw_hal_set_hwreg(adapter, HW_VAR_LPS_POFF_DEINIT, 0);
++#endif
++
++#ifdef CONFIG_LPS_LCLK
++	_cancel_workitem_sync(&pwrctrlpriv->cpwm_event);
++	_cancel_workitem_sync(&pwrctrlpriv->dma_event);
++	#ifdef CONFIG_LPS_RPWM_TIMER
++	_cancel_workitem_sync(&pwrctrlpriv->rpwmtimeoutwi);
++	#endif
++#endif /* CONFIG_LPS_LCLK */
++
++#ifdef CONFIG_LPS_PG
++	rsvd_page_cache_free(&pwrctrlpriv->lpspg_info);
++	#ifdef CONFIG_RTL8822C
++	rsvd_page_cache_free(&pwrctrlpriv->lpspg_dpk_info);
++	rsvd_page_cache_free(&pwrctrlpriv->lpspg_iqk_info);
++	#endif
++#endif
++
++#ifdef CONFIG_WOWLAN
++#ifdef CONFIG_PNO_SUPPORT
++	if (pwrctrlpriv->pnlo_info != NULL)
++		printk("****** pnlo_info memory leak********\n");
++
++	if (pwrctrlpriv->pscan_info != NULL)
++		printk("****** pscan_info memory leak********\n");
++
++	if (pwrctrlpriv->pno_ssid_list != NULL)
++		printk("****** pno_ssid_list memory leak********\n");
++#endif
++#ifdef CONFIG_WOW_PATTERN_HW_CAM
++	_rtw_mutex_free(&pwrctrlpriv->wowlan_pattern_cam_mutex);
++#endif
++
++#endif /* CONFIG_WOWLAN */
++
++#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
++	rtw_unregister_early_suspend(pwrctrlpriv);
++#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */
++
++	_free_pwrlock(&pwrctrlpriv->lock);
++	_free_pwrlock(&pwrctrlpriv->check_32k_lock);
++
++#ifdef CONFIG_LPS_ACK
++	_rtw_mutex_free(&pwrctrlpriv->lps_ack_mutex);
++#endif /* CONFIG_LPS_ACK */
++}
++
++#ifdef CONFIG_RESUME_IN_WORKQUEUE
++extern int rtw_resume_process(_adapter *padapter);
++
++static void resume_workitem_callback(struct work_struct *work)
++{
++	struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, resume_work);
++	struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
++	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	rtw_resume_process(adapter);
++
++	rtw_resume_unlock_suspend();
++}
++
++void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv)
++{
++	/* accquire system's suspend lock preventing from falliing asleep while resume in workqueue */
++	/* rtw_lock_suspend(); */
++
++	rtw_resume_lock_suspend();
++
++#if 1
++	queue_work(pwrpriv->rtw_workqueue, &pwrpriv->resume_work);
++#else
++	_set_workitem(&pwrpriv->resume_work);
++#endif
++}
++#endif /* CONFIG_RESUME_IN_WORKQUEUE */
++
++#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
++inline bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv)
++{
++	return (pwrpriv->early_suspend.suspend) ? _TRUE : _FALSE;
++}
++
++inline bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv)
++{
++	return (pwrpriv->do_late_resume) ? _TRUE : _FALSE;
++}
++
++inline void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable)
++{
++	pwrpriv->do_late_resume = enable;
++}
++#endif
++
++#ifdef CONFIG_HAS_EARLYSUSPEND
++extern int rtw_resume_process(_adapter *padapter);
++static void rtw_early_suspend(struct early_suspend *h)
++{
++	struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	rtw_set_do_late_resume(pwrpriv, _FALSE);
++}
++
++static void rtw_late_resume(struct early_suspend *h)
++{
++	struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
++	struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
++	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	if (pwrpriv->do_late_resume) {
++		rtw_set_do_late_resume(pwrpriv, _FALSE);
++		rtw_resume_process(adapter);
++	}
++}
++
++void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv)
++{
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	/* jeff: set the early suspend level before blank screen, so we wll do late resume after scree is lit */
++	pwrpriv->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20;
++	pwrpriv->early_suspend.suspend = rtw_early_suspend;
++	pwrpriv->early_suspend.resume = rtw_late_resume;
++	register_early_suspend(&pwrpriv->early_suspend);
++
++
++}
++
++void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv)
++{
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	rtw_set_do_late_resume(pwrpriv, _FALSE);
++
++	if (pwrpriv->early_suspend.suspend)
++		unregister_early_suspend(&pwrpriv->early_suspend);
++
++	pwrpriv->early_suspend.suspend = NULL;
++	pwrpriv->early_suspend.resume = NULL;
++}
++#endif /* CONFIG_HAS_EARLYSUSPEND */
++
++#ifdef CONFIG_ANDROID_POWER
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	extern int rtw_resume_process(PADAPTER padapter);
++#endif
++static void rtw_early_suspend(android_early_suspend_t *h)
++{
++	struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	rtw_set_do_late_resume(pwrpriv, _FALSE);
++}
++
++static void rtw_late_resume(android_early_suspend_t *h)
++{
++	struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
++	struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
++	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
++
++	RTW_INFO("%s\n", __FUNCTION__);
++	if (pwrpriv->do_late_resume) {
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++		rtw_set_do_late_resume(pwrpriv, _FALSE);
++		rtw_resume_process(adapter);
++#endif
++	}
++}
++
++void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv)
++{
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	/* jeff: set the early suspend level before blank screen, so we wll do late resume after scree is lit */
++	pwrpriv->early_suspend.level = ANDROID_EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20;
++	pwrpriv->early_suspend.suspend = rtw_early_suspend;
++	pwrpriv->early_suspend.resume = rtw_late_resume;
++	android_register_early_suspend(&pwrpriv->early_suspend);
++}
++
++void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv)
++{
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	rtw_set_do_late_resume(pwrpriv, _FALSE);
++
++	if (pwrpriv->early_suspend.suspend)
++		android_unregister_early_suspend(&pwrpriv->early_suspend);
++
++	pwrpriv->early_suspend.suspend = NULL;
++	pwrpriv->early_suspend.resume = NULL;
++}
++#endif /* CONFIG_ANDROID_POWER */
++
++u8 rtw_interface_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val)
++{
++	u8 bResult = _TRUE;
++	rtw_hal_intf_ps_func(padapter, efunc_id, val);
++
++	return bResult;
++}
++
++
++inline void rtw_set_ips_deny(_adapter *padapter, u32 ms)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ms);
++}
++
++/*
++* rtw_pwr_wakeup - Wake the NIC up from: 1)IPS. 2)USB autosuspend
++* @adapter: pointer to _adapter structure
++* @ips_deffer_ms: the ms wiil prevent from falling into IPS after wakeup
++* Return _SUCCESS or _FAIL
++*/
++
++int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
++	struct mlme_priv *pmlmepriv;
++	int ret = _SUCCESS;
++	systime start = rtw_get_current_time();
++
++	/*RTW_INFO(FUNC_ADPT_FMT "===>\n", FUNC_ADPT_ARG(padapter));*/
++	/* for LPS */
++	LeaveAllPowerSaveMode(padapter);
++
++	/* IPS still bound with primary adapter */
++	padapter = GET_PRIMARY_ADAPTER(padapter);
++	pmlmepriv = &padapter->mlmepriv;
++
++	if (rtw_time_after(rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms), pwrpriv->ips_deny_time))
++		pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms);
++
++
++	if (pwrpriv->ps_processing) {
++		RTW_INFO("%s wait ps_processing...\n", __func__);
++		while (pwrpriv->ps_processing && rtw_get_passing_time_ms(start) <= 3000)
++			rtw_msleep_os(10);
++		if (pwrpriv->ps_processing)
++			RTW_INFO("%s wait ps_processing timeout\n", __func__);
++		else
++			RTW_INFO("%s wait ps_processing done\n", __func__);
++	}
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++	if (rtw_hal_sreset_inprogress(padapter)) {
++		RTW_INFO("%s wait sreset_inprogress...\n", __func__);
++		while (rtw_hal_sreset_inprogress(padapter) && rtw_get_passing_time_ms(start) <= 4000)
++			rtw_msleep_os(10);
++		if (rtw_hal_sreset_inprogress(padapter))
++			RTW_INFO("%s wait sreset_inprogress timeout\n", __func__);
++		else
++			RTW_INFO("%s wait sreset_inprogress done\n", __func__);
++	}
++#endif
++
++	if (pwrpriv->bInSuspend) {
++		RTW_INFO("%s wait bInSuspend...\n", __func__);
++		while (pwrpriv->bInSuspend
++		       && ((rtw_get_passing_time_ms(start) <= 3000 && !rtw_is_do_late_resume(pwrpriv))
++			|| (rtw_get_passing_time_ms(start) <= 500 && rtw_is_do_late_resume(pwrpriv)))
++		      )
++			rtw_msleep_os(10);
++		if (pwrpriv->bInSuspend)
++			RTW_INFO("%s wait bInSuspend timeout\n", __func__);
++		else
++			RTW_INFO("%s wait bInSuspend done\n", __func__);
++	}
++
++	/* System suspend is not allowed to wakeup */
++	if (_TRUE == pwrpriv->bInSuspend) {
++		ret = _FAIL;
++		goto exit;
++	}
++	/* I think this should be check in IPS, LPS, autosuspend functions... */
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++		ret = _SUCCESS;
++		goto exit;
++	}
++
++	if (rf_off == pwrpriv->rf_pwrstate) {
++		
++#ifdef CONFIG_IPS
++		RTW_INFO("%s call ips_leave....\n", __FUNCTION__);
++		if (_FAIL ==  ips_leave(padapter)) {
++			RTW_INFO("======> ips_leave fail.............\n");
++			ret = _FAIL;
++			goto exit;
++		}
++#endif
++		
++	}
++
++	/* TODO: the following checking need to be merged... */
++	if (rtw_is_drv_stopped(padapter)
++	    || !padapter->bup
++	    || !rtw_is_hw_init_completed(padapter)
++	   ) {
++		RTW_INFO("%s: bDriverStopped=%s, bup=%d, hw_init_completed=%u\n"
++			 , caller
++			 , rtw_is_drv_stopped(padapter) ? "True" : "False"
++			 , padapter->bup
++			 , rtw_get_hw_init_completed(padapter));
++		ret = _FALSE;
++		goto exit;
++	}
++
++exit:
++	if (rtw_time_after(rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms), pwrpriv->ips_deny_time))
++		pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms);
++	/*RTW_INFO(FUNC_ADPT_FMT "<===\n", FUNC_ADPT_ARG(padapter));*/
++	return ret;
++
++}
++
++int rtw_pm_set_lps(_adapter *padapter, u8 mode)
++{
++	int	ret = 0;
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++
++	if (mode < PS_MODE_NUM) {
++		if (pwrctrlpriv->power_mgnt != mode) {
++			if (PS_MODE_ACTIVE == mode)
++				LeaveAllPowerSaveMode(padapter);
++			else
++				pwrctrlpriv->LpsIdleCount = 2;
++			pwrctrlpriv->power_mgnt = mode;
++			pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt) ? _TRUE : _FALSE;
++		}
++	} else
++		ret = -EINVAL;
++
++	return ret;
++}
++
++int rtw_pm_set_lps_level(_adapter *padapter, u8 level)
++{
++	int	ret = 0;
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++
++	if (level < LPS_LEVEL_MAX) {
++		if (pwrctrlpriv->lps_level != level) {
++			#ifdef CONFIG_LPS
++			if (rtw_lps_ctrl_leave_set_level_cmd(padapter, level, RTW_CMDF_WAIT_ACK) != _SUCCESS)
++			#endif
++				pwrctrlpriv->lps_level = level;
++		}
++	} else
++		ret = -EINVAL;
++
++	return ret;
++}
++
++#ifdef CONFIG_LPS_1T1R
++int rtw_pm_set_lps_1t1r(_adapter *padapter, u8 en)
++{
++	int	ret = 0;
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++
++	en = en ? 1 : 0;
++	if (pwrctrlpriv->lps_1t1r != en) {
++		if (rtw_lps_ctrl_leave_set_1t1r_cmd(padapter, en, RTW_CMDF_WAIT_ACK) != _SUCCESS)
++			pwrctrlpriv->lps_1t1r = en;
++	}
++
++	return ret;
++}
++#endif
++
++inline void rtw_set_lps_deny(_adapter *adapter, u32 ms)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	pwrpriv->lps_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ms);
++}
++
++#ifdef CONFIG_WOWLAN
++int rtw_pm_set_wow_lps(_adapter *padapter, u8 mode)
++{
++	int	ret = 0;
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++
++	if (mode < PS_MODE_NUM) {
++		if (pwrctrlpriv->wowlan_power_mgmt != mode) 
++			pwrctrlpriv->wowlan_power_mgmt = mode;
++	} else
++		ret = -EINVAL;
++
++	return ret;
++}
++int rtw_pm_set_wow_lps_level(_adapter *padapter, u8 level)
++{
++	int	ret = 0;
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++
++	if (level < LPS_LEVEL_MAX)
++		pwrctrlpriv->wowlan_lps_level = level;
++	else
++		ret = -EINVAL;
++
++	return ret;
++}
++
++#ifdef CONFIG_LPS_1T1R
++int rtw_pm_set_wow_lps_1t1r(_adapter *padapter, u8 en)
++{
++	int	ret = 0;
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++
++	en = en ? 1 : 0;
++	pwrctrlpriv->wowlan_lps_1t1r = en;
++
++	return ret;
++}
++#endif /* CONFIG_LPS_1T1R */
++#endif /* CONFIG_WOWLAN */
++
++int rtw_pm_set_ips(_adapter *padapter, u8 mode)
++{
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++
++	if (mode == IPS_NORMAL || mode == IPS_LEVEL_2) {
++		rtw_ips_mode_req(pwrctrlpriv, mode);
++		RTW_INFO("%s %s\n", __FUNCTION__, mode == IPS_NORMAL ? "IPS_NORMAL" : "IPS_LEVEL_2");
++		return 0;
++	} else if (mode == IPS_NONE) {
++		rtw_ips_mode_req(pwrctrlpriv, mode);
++		RTW_INFO("%s %s\n", __FUNCTION__, "IPS_NONE");
++		if (!rtw_is_surprise_removed(padapter) && (_FAIL == rtw_pwr_wakeup(padapter)))
++			return -EFAULT;
++	} else
++		return -EINVAL;
++	return 0;
++}
++
++/*
++ * ATTENTION:
++ *	This function will request pwrctrl LOCK!
++ */
++void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason)
++{
++	struct pwrctrl_priv *pwrpriv;
++
++	/* 	RTW_INFO("+" FUNC_ADPT_FMT ": Request PS deny for %d (0x%08X)\n",
++	 *		FUNC_ADPT_ARG(padapter), reason, BIT(reason)); */
++
++	pwrpriv = adapter_to_pwrctl(padapter);
++
++	_enter_pwrlock(&pwrpriv->lock);
++	if (pwrpriv->ps_deny & BIT(reason)) {
++		RTW_INFO(FUNC_ADPT_FMT ": [WARNING] Reason %d had been set before!!\n",
++			 FUNC_ADPT_ARG(padapter), reason);
++	}
++	pwrpriv->ps_deny |= BIT(reason);
++	_exit_pwrlock(&pwrpriv->lock);
++
++	/* 	RTW_INFO("-" FUNC_ADPT_FMT ": Now PS deny for 0x%08X\n",
++	 *		FUNC_ADPT_ARG(padapter), pwrpriv->ps_deny); */
++}
++
++/*
++ * ATTENTION:
++ *	This function will request pwrctrl LOCK!
++ */
++void rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason)
++{
++	struct pwrctrl_priv *pwrpriv;
++
++
++	/* 	RTW_INFO("+" FUNC_ADPT_FMT ": Cancel PS deny for %d(0x%08X)\n",
++	 *		FUNC_ADPT_ARG(padapter), reason, BIT(reason)); */
++
++	pwrpriv = adapter_to_pwrctl(padapter);
++
++	_enter_pwrlock(&pwrpriv->lock);
++	if ((pwrpriv->ps_deny & BIT(reason)) == 0) {
++		RTW_INFO(FUNC_ADPT_FMT ": [ERROR] Reason %d had been canceled before!!\n",
++			 FUNC_ADPT_ARG(padapter), reason);
++	}
++	pwrpriv->ps_deny &= ~BIT(reason);
++	_exit_pwrlock(&pwrpriv->lock);
++
++	/* 	RTW_INFO("-" FUNC_ADPT_FMT ": Now PS deny for 0x%08X\n",
++	 *		FUNC_ADPT_ARG(padapter), pwrpriv->ps_deny); */
++}
++
++/*
++ * ATTENTION:
++ *	Before calling this function pwrctrl lock should be occupied already,
++ *	otherwise it may return incorrect value.
++ */
++u32 rtw_ps_deny_get(PADAPTER padapter)
++{
++	u32 deny;
++
++
++	deny = adapter_to_pwrctl(padapter)->ps_deny;
++
++	return deny;
++}
++
++static void _rtw_ssmps(_adapter *adapter, struct sta_info *sta)
++{
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	if (MLME_IS_STA(adapter)) {
++		issue_action_SM_PS_wait_ack(adapter , get_my_bssid(&(pmlmeinfo->network)),
++			sta->cmn.sm_ps, 3 , 1);
++	}
++	else if (MLME_IS_AP(adapter)) {
++
++	}
++	rtw_phydm_ra_registed(adapter, sta);
++}
++void rtw_ssmps_enter(_adapter *adapter, struct sta_info *sta)
++{
++	if (sta->cmn.sm_ps == SM_PS_STATIC)
++		return;
++
++	RTW_INFO(ADPT_FMT" STA [" MAC_FMT "]\n", ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
++
++	sta->cmn.sm_ps = SM_PS_STATIC;
++	_rtw_ssmps(adapter, sta);
++}
++void rtw_ssmps_leave(_adapter *adapter, struct sta_info *sta)
++{
++	if (sta->cmn.sm_ps == SM_PS_DISABLE)
++		return;
++
++	RTW_INFO(ADPT_FMT" STA [" MAC_FMT "] \n", ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
++	sta->cmn.sm_ps = SM_PS_DISABLE;
++	_rtw_ssmps(adapter, sta);
++}
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_recv.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_recv.c
+new file mode 100755
+index 000000000..25e55e83f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_recv.c
+@@ -0,0 +1,4687 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_RECV_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++#include <uapi/linux/sched/types.h>
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++static void rtw_signal_stat_timer_hdl(void *ctx);
++
++enum {
++	SIGNAL_STAT_CALC_PROFILE_0 = 0,
++	SIGNAL_STAT_CALC_PROFILE_1,
++	SIGNAL_STAT_CALC_PROFILE_2,
++	SIGNAL_STAT_CALC_PROFILE_MAX
++};
++
++u8 signal_stat_calc_profile[SIGNAL_STAT_CALC_PROFILE_MAX][3] = {
++	{4, 1},	/* Profile 0 => pre_stat : curr_stat = 4 : 1 */
++	{3, 7},	/* Profile 1 => pre_stat : curr_stat = 3 : 7 */
++	{0, 10}	/* Profile 2 => pre_stat : curr_stat = 0 : 10 */
++};
++
++#ifndef RTW_SIGNAL_STATE_CALC_PROFILE
++	#define RTW_SIGNAL_STATE_CALC_PROFILE SIGNAL_STAT_CALC_PROFILE_1
++#endif
++
++#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
++
++u8 rtw_bridge_tunnel_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 };
++u8 rtw_rfc1042_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 };
++static u8 SNAP_ETH_TYPE_IPX[2] = {0x81, 0x37};
++static u8 SNAP_ETH_TYPE_APPLETALK_AARP[2] = {0x80, 0xf3};
++#ifdef CONFIG_TDLS
++static u8 SNAP_ETH_TYPE_TDLS[2] = {0x89, 0x0d};
++#endif
++
++void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv)
++{
++
++
++
++	_rtw_memset((u8 *)psta_recvpriv, 0, sizeof(struct sta_recv_priv));
++
++	_rtw_spinlock_init(&psta_recvpriv->lock);
++
++	/* for(i=0; i<MAX_RX_NUMBLKS; i++) */
++	/*	_rtw_init_queue(&psta_recvpriv->blk_strms[i]); */
++
++	_rtw_init_queue(&psta_recvpriv->defrag_q);
++
++
++}
++
++sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter)
++{
++	sint i;
++
++	union recv_frame *precvframe;
++	sint	res = _SUCCESS;
++
++
++	/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
++	/* _rtw_memset((unsigned char *)precvpriv, 0, sizeof (struct  recv_priv)); */
++
++	_rtw_spinlock_init(&precvpriv->lock);
++
++#ifdef CONFIG_RECV_THREAD_MODE
++	_rtw_init_sema(&precvpriv->recv_sema, 0);
++
++#endif
++
++	_rtw_init_queue(&precvpriv->free_recv_queue);
++	_rtw_init_queue(&precvpriv->recv_pending_queue);
++	_rtw_init_queue(&precvpriv->uc_swdec_pending_queue);
++
++	precvpriv->adapter = padapter;
++
++	precvpriv->free_recvframe_cnt = NR_RECVFRAME;
++
++	precvpriv->sink_udpport = 0;
++	precvpriv->pre_rtp_rxseq = 0;
++	precvpriv->cur_rtp_rxseq = 0;
++
++#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
++	precvpriv->store_law_data_flag = 1;
++#else
++	precvpriv->store_law_data_flag = 0;
++#endif
++
++	rtw_os_recv_resource_init(precvpriv, padapter);
++
++	precvpriv->pallocated_frame_buf = rtw_zvmalloc(NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ);
++
++	if (precvpriv->pallocated_frame_buf == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++	/* _rtw_memset(precvpriv->pallocated_frame_buf, 0, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); */
++
++	precvpriv->precv_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_frame_buf), RXFRAME_ALIGN_SZ);
++	/* precvpriv->precv_frame_buf = precvpriv->pallocated_frame_buf + RXFRAME_ALIGN_SZ - */
++	/*						((SIZE_PTR) (precvpriv->pallocated_frame_buf) &(RXFRAME_ALIGN_SZ-1)); */
++
++	precvframe = (union recv_frame *) precvpriv->precv_frame_buf;
++
++
++	for (i = 0; i < NR_RECVFRAME ; i++) {
++		_rtw_init_listhead(&(precvframe->u.list));
++
++		rtw_list_insert_tail(&(precvframe->u.list), &(precvpriv->free_recv_queue.queue));
++
++		rtw_os_recv_resource_alloc(padapter, precvframe);
++
++		precvframe->u.hdr.len = 0;
++
++		precvframe->u.hdr.adapter = padapter;
++		precvframe++;
++
++	}
++
++#ifdef CONFIG_USB_HCI
++
++	ATOMIC_SET(&(precvpriv->rx_pending_cnt), 1);
++
++	_rtw_init_sema(&precvpriv->allrxreturnevt, 0);
++
++#endif
++
++	res = rtw_hal_init_recv_priv(padapter);
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++	rtw_init_timer(&precvpriv->signal_stat_timer, padapter, rtw_signal_stat_timer_hdl, padapter);
++
++	precvpriv->signal_stat_sampling_interval = 2000; /* ms */
++	/* precvpriv->signal_stat_converging_constant = 5000; */ /* ms */
++
++	rtw_set_signal_stat_timer(precvpriv);
++#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
++
++exit:
++
++
++	return res;
++
++}
++
++void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv);
++void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv)
++{
++	_rtw_spinlock_free(&precvpriv->lock);
++#ifdef CONFIG_RECV_THREAD_MODE
++	_rtw_free_sema(&precvpriv->recv_sema);
++#endif
++
++	_rtw_spinlock_free(&precvpriv->free_recv_queue.lock);
++	_rtw_spinlock_free(&precvpriv->recv_pending_queue.lock);
++
++	_rtw_spinlock_free(&precvpriv->free_recv_buf_queue.lock);
++
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
++	_rtw_spinlock_free(&precvpriv->recv_buf_pending_queue.lock);
++#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
++}
++
++void _rtw_free_recv_priv(struct recv_priv *precvpriv)
++{
++	_adapter	*padapter = precvpriv->adapter;
++
++
++	rtw_free_uc_swdec_pending_queue(padapter);
++
++	rtw_mfree_recv_priv_lock(precvpriv);
++
++	rtw_os_recv_resource_free(precvpriv);
++
++	if (precvpriv->pallocated_frame_buf)
++		rtw_vmfree(precvpriv->pallocated_frame_buf, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ);
++
++	rtw_hal_free_recv_priv(padapter);
++
++
++}
++
++bool rtw_rframe_del_wfd_ie(union recv_frame *rframe, u8 ies_offset)
++{
++#define DBG_RFRAME_DEL_WFD_IE 0
++	u8 *ies = rframe->u.hdr.rx_data + sizeof(struct rtw_ieee80211_hdr_3addr) + ies_offset;
++	uint ies_len_ori = rframe->u.hdr.len - (ies - rframe->u.hdr.rx_data);
++	uint ies_len;
++
++	ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_RFRAME_DEL_WFD_IE ? __func__ : NULL);
++	rframe->u.hdr.len -= ies_len_ori - ies_len;
++
++	return ies_len_ori != ies_len;
++}
++
++union recv_frame *_rtw_alloc_recvframe(_queue *pfree_recv_queue)
++{
++
++	union recv_frame  *precvframe;
++	_list	*plist, *phead;
++	_adapter *padapter;
++	struct recv_priv *precvpriv;
++
++	if (_rtw_queue_empty(pfree_recv_queue) == _TRUE)
++		precvframe = NULL;
++	else {
++		phead = get_list_head(pfree_recv_queue);
++
++		plist = get_next(phead);
++
++		precvframe = LIST_CONTAINOR(plist, union recv_frame, u);
++
++		rtw_list_delete(&precvframe->u.hdr.list);
++		padapter = precvframe->u.hdr.adapter;
++		if (padapter != NULL) {
++			precvpriv = &padapter->recvpriv;
++			if (pfree_recv_queue == &precvpriv->free_recv_queue)
++				precvpriv->free_recvframe_cnt--;
++		}
++	}
++
++
++	return precvframe;
++
++}
++
++union recv_frame *rtw_alloc_recvframe(_queue *pfree_recv_queue)
++{
++	_irqL irqL;
++	union recv_frame  *precvframe;
++
++	_enter_critical_bh(&pfree_recv_queue->lock, &irqL);
++
++	precvframe = _rtw_alloc_recvframe(pfree_recv_queue);
++
++	_exit_critical_bh(&pfree_recv_queue->lock, &irqL);
++
++	return precvframe;
++}
++
++void rtw_init_recvframe(union recv_frame *precvframe, struct recv_priv *precvpriv)
++{
++	/* Perry: This can be removed */
++	_rtw_init_listhead(&precvframe->u.hdr.list);
++
++	precvframe->u.hdr.len = 0;
++}
++
++int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue)
++{
++	_irqL irqL;
++	_adapter *padapter = precvframe->u.hdr.adapter;
++	struct recv_priv *precvpriv = &padapter->recvpriv;
++
++
++#ifdef CONFIG_CONCURRENT_MODE
++	padapter = GET_PRIMARY_ADAPTER(padapter);
++	precvpriv = &padapter->recvpriv;
++	pfree_recv_queue = &precvpriv->free_recv_queue;
++	precvframe->u.hdr.adapter = padapter;
++#endif
++
++
++	rtw_os_free_recvframe(precvframe);
++
++
++	_enter_critical_bh(&pfree_recv_queue->lock, &irqL);
++
++	rtw_list_delete(&(precvframe->u.hdr.list));
++
++	precvframe->u.hdr.len = 0;
++	precvframe->u.hdr.attrib.phy_info.physts_rpt_valid = _FALSE;
++
++	rtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(pfree_recv_queue));
++
++	if (padapter != NULL) {
++		if (pfree_recv_queue == &precvpriv->free_recv_queue)
++			precvpriv->free_recvframe_cnt++;
++	}
++
++	_exit_critical_bh(&pfree_recv_queue->lock, &irqL);
++
++
++	return _SUCCESS;
++
++}
++
++
++
++
++sint _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue)
++{
++
++	_adapter *padapter = precvframe->u.hdr.adapter;
++	struct recv_priv *precvpriv = &padapter->recvpriv;
++
++
++	/* _rtw_init_listhead(&(precvframe->u.hdr.list)); */
++	rtw_list_delete(&(precvframe->u.hdr.list));
++
++
++	rtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(queue));
++
++	if (padapter != NULL) {
++		if (queue == &precvpriv->free_recv_queue)
++			precvpriv->free_recvframe_cnt++;
++	}
++
++
++	return _SUCCESS;
++}
++
++sint rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue)
++{
++	sint ret;
++	_irqL irqL;
++
++	/* _spinlock(&pfree_recv_queue->lock); */
++	_enter_critical_bh(&queue->lock, &irqL);
++	ret = _rtw_enqueue_recvframe(precvframe, queue);
++	/* _rtw_spinunlock(&pfree_recv_queue->lock); */
++	_exit_critical_bh(&queue->lock, &irqL);
++
++	return ret;
++}
++
++/*
++sint	rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue)
++{
++	return rtw_free_recvframe(precvframe, queue);
++}
++*/
++
++
++
++
++/*
++caller : defrag ; recvframe_chk_defrag in recv_thread  (passive)
++pframequeue: defrag_queue : will be accessed in recv_thread  (passive)
++
++using spinlock to protect
++
++*/
++
++void rtw_free_recvframe_queue(_queue *pframequeue,  _queue *pfree_recv_queue)
++{
++	union	recv_frame	*precvframe;
++	_list	*plist, *phead;
++
++	_rtw_spinlock(&pframequeue->lock);
++
++	phead = get_list_head(pframequeue);
++	plist = get_next(phead);
++
++	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
++		precvframe = LIST_CONTAINOR(plist, union recv_frame, u);
++
++		plist = get_next(plist);
++
++		/* rtw_list_delete(&precvframe->u.hdr.list); */ /* will do this in rtw_free_recvframe() */
++
++		rtw_free_recvframe(precvframe, pfree_recv_queue);
++	}
++
++	_rtw_spinunlock(&pframequeue->lock);
++
++
++}
++
++u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter)
++{
++	u32 cnt = 0;
++	union recv_frame *pending_frame;
++	while ((pending_frame = rtw_alloc_recvframe(&adapter->recvpriv.uc_swdec_pending_queue))) {
++		rtw_free_recvframe(pending_frame, &adapter->recvpriv.free_recv_queue);
++		cnt++;
++	}
++
++	if (cnt)
++		RTW_INFO(FUNC_ADPT_FMT" dequeue %d\n", FUNC_ADPT_ARG(adapter), cnt);
++
++	return cnt;
++}
++
++
++sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue)
++{
++	_irqL irqL;
++
++	_enter_critical_bh(&queue->lock, &irqL);
++
++	rtw_list_delete(&precvbuf->list);
++	rtw_list_insert_head(&precvbuf->list, get_list_head(queue));
++
++	_exit_critical_bh(&queue->lock, &irqL);
++
++	return _SUCCESS;
++}
++
++sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue)
++{
++	_irqL irqL;
++#ifdef CONFIG_SDIO_HCI
++	_enter_critical_bh(&queue->lock, &irqL);
++#else
++	_enter_critical_ex(&queue->lock, &irqL);
++#endif/*#ifdef CONFIG_SDIO_HCI*/
++
++	rtw_list_delete(&precvbuf->list);
++
++	rtw_list_insert_tail(&precvbuf->list, get_list_head(queue));
++#ifdef CONFIG_SDIO_HCI
++	_exit_critical_bh(&queue->lock, &irqL);
++#else
++	_exit_critical_ex(&queue->lock, &irqL);
++#endif/*#ifdef CONFIG_SDIO_HCI*/
++	return _SUCCESS;
++
++}
++
++struct recv_buf *rtw_dequeue_recvbuf(_queue *queue)
++{
++	_irqL irqL;
++	struct recv_buf *precvbuf;
++	_list	*plist, *phead;
++
++#ifdef CONFIG_SDIO_HCI
++	_enter_critical_bh(&queue->lock, &irqL);
++#else
++	_enter_critical_ex(&queue->lock, &irqL);
++#endif/*#ifdef CONFIG_SDIO_HCI*/
++
++	if (_rtw_queue_empty(queue) == _TRUE)
++		precvbuf = NULL;
++	else {
++		phead = get_list_head(queue);
++
++		plist = get_next(phead);
++
++		precvbuf = LIST_CONTAINOR(plist, struct recv_buf, list);
++
++		rtw_list_delete(&precvbuf->list);
++
++	}
++
++#ifdef CONFIG_SDIO_HCI
++	_exit_critical_bh(&queue->lock, &irqL);
++#else
++	_exit_critical_ex(&queue->lock, &irqL);
++#endif/*#ifdef CONFIG_SDIO_HCI*/
++
++	return precvbuf;
++
++}
++
++sint recvframe_chkmic(_adapter *adapter,  union recv_frame *precvframe);
++sint recvframe_chkmic(_adapter *adapter,  union recv_frame *precvframe)
++{
++
++	sint	i, res = _SUCCESS;
++	u32	datalen;
++	u8	miccode[8];
++	u8	bmic_err = _FALSE, brpt_micerror = _TRUE;
++	u8	*pframe, *payload, *pframemic;
++	u8	*mickey;
++	/* u8	*iv,rxdata_key_idx=0; */
++	struct	sta_info		*stainfo;
++	struct	rx_pkt_attrib	*prxattrib = &precvframe->u.hdr.attrib;
++	struct	security_priv	*psecuritypriv = &adapter->securitypriv;
++
++	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	stainfo = rtw_get_stainfo(&adapter->stapriv , &prxattrib->ta[0]);
++
++	if (prxattrib->encrypt == _TKIP_) {
++
++		/* calculate mic code */
++		if (stainfo != NULL) {
++			if (IS_MCAST(prxattrib->ra)) {
++				/* mickey=&psecuritypriv->dot118021XGrprxmickey.skey[0]; */
++				/* iv = precvframe->u.hdr.rx_data+prxattrib->hdrlen; */
++				/* rxdata_key_idx =( ((iv[3])>>6)&0x3) ; */
++				mickey = &psecuritypriv->dot118021XGrprxmickey[prxattrib->key_index].skey[0];
++
++				/* RTW_INFO("\n recvframe_chkmic: bcmc key psecuritypriv->dot118021XGrpKeyid(%d),pmlmeinfo->key_index(%d) ,recv key_id(%d)\n", */
++				/*								psecuritypriv->dot118021XGrpKeyid,pmlmeinfo->key_index,rxdata_key_idx); */
++
++				if (psecuritypriv->binstallGrpkey == _FALSE) {
++					res = _FAIL;
++					RTW_INFO("\n recvframe_chkmic:didn't install group key!!!!!!!!!!\n");
++					goto exit;
++				}
++			} else {
++				mickey = &stainfo->dot11tkiprxmickey.skey[0];
++			}
++
++			datalen = precvframe->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len - prxattrib->icv_len - 8; /* icv_len included the mic code */
++			pframe = precvframe->u.hdr.rx_data;
++			payload = pframe + prxattrib->hdrlen + prxattrib->iv_len;
++
++
++			/* rtw_seccalctkipmic(&stainfo->dot11tkiprxmickey.skey[0],pframe,payload, datalen ,&miccode[0],(unsigned char)prxattrib->priority); */ /* care the length of the data */
++
++			rtw_seccalctkipmic(mickey, pframe, payload, datalen , &miccode[0], (unsigned char)prxattrib->priority); /* care the length of the data */
++
++			pframemic = payload + datalen;
++
++			bmic_err = _FALSE;
++
++			for (i = 0; i < 8; i++) {
++				if (miccode[i] != *(pframemic + i)) {
++					bmic_err = _TRUE;
++				}
++			}
++
++
++			if (bmic_err == _TRUE) {
++
++
++
++				/* double check key_index for some timing issue , */
++				/* cannot compare with psecuritypriv->dot118021XGrpKeyid also cause timing issue */
++				if ((IS_MCAST(prxattrib->ra) == _TRUE)  && (prxattrib->key_index != pmlmeinfo->key_index))
++					brpt_micerror = _FALSE;
++
++				if ((prxattrib->bdecrypted == _TRUE) && (brpt_micerror == _TRUE)) {
++					rtw_handle_tkip_mic_err(adapter, stainfo, (u8)IS_MCAST(prxattrib->ra));
++					RTW_INFO(" mic error :prxattrib->bdecrypted=%d\n", prxattrib->bdecrypted);
++				} else {
++					RTW_INFO(" mic error :prxattrib->bdecrypted=%d\n", prxattrib->bdecrypted);
++				}
++
++				res = _FAIL;
++
++			} else {
++				/* mic checked ok */
++				if ((psecuritypriv->bcheck_grpkey == _FALSE) && (IS_MCAST(prxattrib->ra) == _TRUE)) {
++					psecuritypriv->bcheck_grpkey = _TRUE;
++				}
++			}
++
++		}
++
++		recvframe_pull_tail(precvframe, 8);
++
++	}
++
++exit:
++
++
++	return res;
++
++}
++
++/*#define DBG_RX_SW_DECRYPTOR*/
++
++/* decrypt and set the ivlen,icvlen of the recv_frame */
++union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame);
++union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame)
++{
++
++	struct rx_pkt_attrib *prxattrib = &precv_frame->u.hdr.attrib;
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	union recv_frame *return_packet = precv_frame;
++	u32	 res = _SUCCESS;
++
++
++	DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt);
++
++
++	if (prxattrib->encrypt > 0) {
++		u8 *iv = precv_frame->u.hdr.rx_data + prxattrib->hdrlen;
++		prxattrib->key_index = (((iv[3]) >> 6) & 0x3) ;
++
++		if (prxattrib->key_index > WEP_KEYS) {
++			RTW_INFO("prxattrib->key_index(%d) > WEP_KEYS\n", prxattrib->key_index);
++
++			switch (prxattrib->encrypt) {
++			case _WEP40_:
++			case _WEP104_:
++				prxattrib->key_index = psecuritypriv->dot11PrivacyKeyIndex;
++				break;
++			case _TKIP_:
++			case _AES_:
++			case _GCMP_:
++			case _GCMP_256_:
++			case _CCMP_256_:
++			default:
++				prxattrib->key_index = psecuritypriv->dot118021XGrpKeyid;
++				break;
++			}
++		}
++	}
++
++	if (prxattrib->encrypt && !prxattrib->bdecrypted) {
++		if (GetFrameType(get_recvframe_data(precv_frame)) == WIFI_DATA
++			#ifdef CONFIG_CONCURRENT_MODE
++			&& !IS_MCAST(prxattrib->ra) /* bc/mc packets may use sw decryption for concurrent mode */
++			#endif
++		)
++			psecuritypriv->hw_decrypted = _FALSE;
++
++#ifdef DBG_RX_SW_DECRYPTOR
++		RTW_INFO(ADPT_FMT" - sec_type:%s DO SW decryption\n",
++			ADPT_ARG(padapter), security_type_str(prxattrib->encrypt));
++#endif
++
++#ifdef DBG_RX_DECRYPTOR
++		RTW_INFO("[%s] %d:prxstat->bdecrypted:%d,  prxattrib->encrypt:%d,  Setting psecuritypriv->hw_decrypted = %d\n",
++			 __FUNCTION__,
++			 __LINE__,
++			 prxattrib->bdecrypted,
++			 prxattrib->encrypt,
++			 psecuritypriv->hw_decrypted);
++#endif
++
++		switch (prxattrib->encrypt) {
++		case _WEP40_:
++		case _WEP104_:
++			DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_wep);
++			rtw_wep_decrypt(padapter, (u8 *)precv_frame);
++			break;
++		case _TKIP_:
++			DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_tkip);
++			res = rtw_tkip_decrypt(padapter, (u8 *)precv_frame);
++			break;
++		case _AES_:
++		case _CCMP_256_:
++			DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_aes);
++			res = rtw_aes_decrypt(padapter, (u8 *)precv_frame);
++			break;
++		case _GCMP_:
++		case _GCMP_256_:
++			DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_gcmp);
++			res = rtw_gcmp_decrypt(padapter, (u8 *)precv_frame);
++			break;
++#ifdef CONFIG_WAPI_SUPPORT
++		case _SMS4_:
++			DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_wapi);
++			rtw_sms4_decrypt(padapter, (u8 *)precv_frame);
++			break;
++#endif
++		default:
++			break;
++		}
++	} else if (prxattrib->bdecrypted == 1
++		   && prxattrib->encrypt > 0
++		&& (psecuritypriv->busetkipkey == 1 || prxattrib->encrypt != _TKIP_)
++		  ) {
++#if 0
++		if ((prxstat->icv == 1) && (prxattrib->encrypt != _AES_)) {
++			psecuritypriv->hw_decrypted = _FALSE;
++
++
++			rtw_free_recvframe(precv_frame, &padapter->recvpriv.free_recv_queue);
++
++			return_packet = NULL;
++
++		} else
++#endif
++		{
++			DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_hw);
++
++			psecuritypriv->hw_decrypted = _TRUE;
++#ifdef DBG_RX_DECRYPTOR
++			RTW_INFO("[%s] %d:prxstat->bdecrypted:%d,  prxattrib->encrypt:%d,  Setting psecuritypriv->hw_decrypted = %d\n",
++				 __FUNCTION__,
++				 __LINE__,
++				 prxattrib->bdecrypted,
++				 prxattrib->encrypt,
++				 psecuritypriv->hw_decrypted);
++
++#endif
++		}
++	} else {
++		DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_unknown);
++#ifdef DBG_RX_DECRYPTOR
++		RTW_INFO("[%s] %d:prxstat->bdecrypted:%d,  prxattrib->encrypt:%d,  Setting psecuritypriv->hw_decrypted = %d\n",
++			 __FUNCTION__,
++			 __LINE__,
++			 prxattrib->bdecrypted,
++			 prxattrib->encrypt,
++			 psecuritypriv->hw_decrypted);
++#endif
++	}
++
++	#ifdef CONFIG_RTW_MESH
++	if (res != _FAIL
++		&& !prxattrib->amsdu
++		&& prxattrib->mesh_ctrl_present)
++		res = rtw_mesh_rx_validate_mctrl_non_amsdu(padapter, precv_frame);
++	#endif
++
++	if (res == _FAIL) {
++		rtw_free_recvframe(return_packet, &padapter->recvpriv.free_recv_queue);
++		return_packet = NULL;
++	} else
++		prxattrib->bdecrypted = _TRUE;
++	/* recvframe_chkmic(adapter, precv_frame);   */ /* move to recvframme_defrag function */
++
++
++	return return_packet;
++
++}
++/* ###set the security information in the recv_frame */
++union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame);
++union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame)
++{
++	u8 *psta_addr = NULL;
++	u8 *ptr;
++	uint  auth_alg;
++	struct recv_frame_hdr *pfhdr;
++	struct sta_info *psta;
++	struct sta_priv *pstapriv ;
++	union recv_frame *prtnframe;
++	u16	ether_type = 0;
++	u16  eapol_type = 0x888e;/* for Funia BD's WPA issue  */
++	struct rx_pkt_attrib *pattrib;
++
++
++	pstapriv = &adapter->stapriv;
++
++	auth_alg = adapter->securitypriv.dot11AuthAlgrthm;
++
++	ptr = get_recvframe_data(precv_frame);
++	pfhdr = &precv_frame->u.hdr;
++	pattrib = &pfhdr->attrib;
++	psta_addr = pattrib->ta;
++
++	prtnframe = NULL;
++
++	psta = rtw_get_stainfo(pstapriv, psta_addr);
++
++
++	if (auth_alg == dot11AuthAlgrthm_8021X) {
++		if ((psta != NULL) && (psta->ieee8021x_blocked)) {
++			/* blocked */
++			/* only accept EAPOL frame */
++
++			prtnframe = precv_frame;
++
++			/* get ether_type */
++			ptr = ptr + pfhdr->attrib.hdrlen + pfhdr->attrib.iv_len + LLC_HEADER_SIZE;
++			_rtw_memcpy(&ether_type, ptr, 2);
++			ether_type = ntohs((unsigned short)ether_type);
++
++			if (ether_type == eapol_type)
++				prtnframe = precv_frame;
++			else {
++				/* free this frame */
++				rtw_free_recvframe(precv_frame, &adapter->recvpriv.free_recv_queue);
++				prtnframe = NULL;
++			}
++		} else {
++			/* allowed */
++			/* check decryption status, and decrypt the frame if needed */
++
++
++			prtnframe = precv_frame;
++			/* check is the EAPOL frame or not (Rekey) */
++			/* if(ether_type == eapol_type){ */
++			/* check Rekey */
++
++			/*	prtnframe=precv_frame; */
++			/* } */
++		}
++	} else
++		prtnframe = precv_frame;
++
++
++	return prtnframe;
++
++}
++
++/* VALID_PN_CHK
++ * Return true when PN is legal, otherwise false.
++ * Legal PN:
++ *	1. If old PN is 0, any PN is legal
++ *	2. PN > old PN
++ */
++#define PN_LESS_CHK(a, b)	(((a-b) & 0x800000000000) != 0)
++#define VALID_PN_CHK(new, old)	(((old) == 0) || PN_LESS_CHK(old, new))
++#define CCMPH_2_KEYID(ch)	(((ch) & 0x00000000c0000000) >> 30)
++sint recv_ucast_pn_decache(union recv_frame *precv_frame);
++sint recv_ucast_pn_decache(union recv_frame *precv_frame)
++{
++	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++	struct sta_info *sta = precv_frame->u.hdr.psta;
++	struct stainfo_rxcache *prxcache = &sta->sta_recvpriv.rxcache;
++	u8 *pdata = precv_frame->u.hdr.rx_data;
++	sint tid = precv_frame->u.hdr.attrib.priority;
++	u64 tmp_iv_hdr = 0;
++	u64 curr_pn = 0, pkt_pn = 0;
++
++	if (tid > 15)
++		return _FAIL;
++
++	if (pattrib->encrypt == _AES_) {
++		tmp_iv_hdr = le64_to_cpu(*(u64*)(pdata + pattrib->hdrlen));
++		pkt_pn = CCMPH_2_PN(tmp_iv_hdr);
++		tmp_iv_hdr = le64_to_cpu(*(u64*)prxcache->iv[tid]);
++		curr_pn = CCMPH_2_PN(tmp_iv_hdr);
++
++		if (!VALID_PN_CHK(pkt_pn, curr_pn)) {
++			/* return _FAIL; */
++		} else {
++			prxcache->last_tid = tid;
++			_rtw_memcpy(prxcache->iv[tid],
++				    (pdata + pattrib->hdrlen),
++				    sizeof(prxcache->iv[tid]));
++		}
++	}
++
++	return _SUCCESS;
++}
++
++sint recv_bcast_pn_decache(union recv_frame *precv_frame);
++sint recv_bcast_pn_decache(union recv_frame *precv_frame)
++{
++	_adapter *padapter = precv_frame->u.hdr.adapter;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++	u8 *pdata = precv_frame->u.hdr.rx_data;
++	u64 tmp_iv_hdr = 0;
++	u64 curr_pn = 0, pkt_pn = 0;
++	u8 key_id;
++
++	if ((pattrib->encrypt == _AES_) &&
++		(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) {
++
++		tmp_iv_hdr = le64_to_cpu(*(u64*)(pdata + pattrib->hdrlen));
++		key_id = CCMPH_2_KEYID(tmp_iv_hdr);
++		pkt_pn = CCMPH_2_PN(tmp_iv_hdr);
++
++		curr_pn = le64_to_cpu(*(u64*)psecuritypriv->iv_seq[key_id]);
++		curr_pn &= 0x0000ffffffffffff;
++
++		if (!VALID_PN_CHK(pkt_pn, curr_pn))
++			return _FAIL;
++
++		*(u64*)psecuritypriv->iv_seq[key_id] = cpu_to_le64(pkt_pn);
++	}
++
++	return _SUCCESS;
++}
++
++sint recv_decache(union recv_frame *precv_frame)
++{
++	struct sta_info *psta = precv_frame->u.hdr.psta;
++	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++	_adapter *adapter = psta->padapter;
++	sint tid = pattrib->priority;
++	u16 seq_ctrl = ((precv_frame->u.hdr.attrib.seq_num & 0xffff) << 4) |
++		       (precv_frame->u.hdr.attrib.frag_num & 0xf);
++	u16 *prxseq;
++
++	if (tid > 15)
++		return _FAIL;
++
++	if (pattrib->qos) {
++		if (IS_MCAST(pattrib->ra))
++			prxseq = &psta->sta_recvpriv.bmc_tid_rxseq[tid];
++		else
++			prxseq = &psta->sta_recvpriv.rxcache.tid_rxseq[tid];
++	} else {
++		if (IS_MCAST(pattrib->ra)) {
++			prxseq = &psta->sta_recvpriv.nonqos_bmc_rxseq;
++			#ifdef DBG_RX_SEQ
++			RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" nonqos bmc seq_num:%d\n"
++				, FUNC_ADPT_ARG(adapter), pattrib->seq_num);
++			#endif
++
++		} else {
++			prxseq = &psta->sta_recvpriv.nonqos_rxseq;
++			#ifdef DBG_RX_SEQ
++			RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" nonqos seq_num:%d\n"
++				, FUNC_ADPT_ARG(adapter), pattrib->seq_num);
++			#endif
++		}
++	}
++
++	if (seq_ctrl == *prxseq) {
++		/* for non-AMPDU case	*/
++		psta->sta_stats.duplicate_cnt++;
++
++		if (psta->sta_stats.duplicate_cnt % 100 == 0)
++			RTW_INFO("%s: tid=%u seq=%d frag=%d\n", __func__
++				, tid, precv_frame->u.hdr.attrib.seq_num
++				, precv_frame->u.hdr.attrib.frag_num);
++
++		#ifdef DBG_RX_DROP_FRAME
++		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_decache _FAIL for sta="MAC_FMT"\n"
++			, FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr));
++		#endif
++		return _FAIL;
++	}
++	*prxseq = seq_ctrl;
++
++	return _SUCCESS;
++}
++
++void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta)
++{
++#ifdef CONFIG_AP_MODE
++	unsigned char pwrbit;
++	u8 *ptr = precv_frame->u.hdr.rx_data;
++
++	pwrbit = GetPwrMgt(ptr);
++
++	if (pwrbit) {
++		if (!(psta->state & WIFI_SLEEP_STATE)) {
++			/* psta->state |= WIFI_SLEEP_STATE; */
++			/* rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, BIT(psta->cmn.aid)); */
++
++			stop_sta_xmit(padapter, psta);
++			/* RTW_INFO_DUMP("to sleep, sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); */
++		}
++	} else {
++		if (psta->state & WIFI_SLEEP_STATE) {
++			/* psta->state ^= WIFI_SLEEP_STATE; */
++			/* rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, BIT(psta->cmn.aid)); */
++
++			wakeup_sta_to_xmit(padapter, psta);
++			/* RTW_INFO_DUMP("to wakeup, sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); */
++		}
++	}
++#endif
++}
++
++void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta)
++{
++#ifdef CONFIG_AP_MODE
++	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++
++#ifdef CONFIG_TDLS
++	if (!(psta->tdls_sta_state & TDLS_LINKED_STATE)) {
++#endif /* CONFIG_TDLS */
++
++		if (!psta->qos_option)
++			return;
++
++		if (!(psta->qos_info & 0xf))
++			return;
++
++#ifdef CONFIG_TDLS
++	}
++#endif /* CONFIG_TDLS		 */
++
++	if (psta->state & WIFI_SLEEP_STATE) {
++		u8 wmmps_ac = 0;
++
++		switch (pattrib->priority) {
++		case 1:
++		case 2:
++			wmmps_ac = psta->uapsd_bk & BIT(1);
++			break;
++		case 4:
++		case 5:
++			wmmps_ac = psta->uapsd_vi & BIT(1);
++			break;
++		case 6:
++		case 7:
++			wmmps_ac = psta->uapsd_vo & BIT(1);
++			break;
++		case 0:
++		case 3:
++		default:
++			wmmps_ac = psta->uapsd_be & BIT(1);
++			break;
++		}
++
++		if (wmmps_ac) {
++			if (psta->sleepq_ac_len > 0) {
++				/* process received triggered frame */
++				xmit_delivery_enabled_frames(padapter, psta);
++			} else {
++				/* issue one qos null frame with More data bit = 0 and the EOSP bit set (=1) */
++				issue_qos_nulldata(padapter, psta->cmn.mac_addr, (u16)pattrib->priority, 0, 0, 0);
++			}
++		}
++
++	}
++
++
++#endif
++
++}
++
++#ifdef CONFIG_TDLS
++sint OnTDLS(_adapter *adapter, union recv_frame *precv_frame)
++{
++	struct rx_pkt_attrib	*pattrib = &precv_frame->u.hdr.attrib;
++	sint ret = _SUCCESS;
++	u8 *paction = get_recvframe_data(precv_frame);
++	u8 category_field = 1;
++#ifdef CONFIG_WFD
++	u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a };
++#endif /* CONFIG_WFD */
++	struct tdls_info *ptdlsinfo = &(adapter->tdlsinfo);
++	u8 *ptr = precv_frame->u.hdr.rx_data;
++	struct sta_priv *pstapriv = &(adapter->stapriv);
++	struct sta_info *ptdls_sta = NULL;
++
++	/* point to action field */
++	paction += pattrib->hdrlen
++		   + pattrib->iv_len
++		   + SNAP_SIZE
++		   + ETH_TYPE_LEN
++		   + PAYLOAD_TYPE_LEN
++		   + category_field;
++
++	RTW_INFO("[TDLS] Recv %s from "MAC_FMT" with SeqNum = %d\n", rtw_tdls_action_txt(*paction), MAC_ARG(pattrib->src), GetSequence(get_recvframe_data(precv_frame)));
++
++	if (hal_chk_wl_func(adapter, WL_FUNC_TDLS) == _FALSE) {
++		RTW_INFO("Ignore tdls frame since hal doesn't support tdls\n");
++		ret = _FAIL;
++		return ret;
++	}
++
++	if (rtw_is_tdls_enabled(adapter) == _FALSE) {
++		RTW_INFO("recv tdls frame, "
++			 "but tdls haven't enabled\n");
++		ret = _FAIL;
++		return ret;
++	}
++
++	ptdls_sta = rtw_get_stainfo(pstapriv, get_sa(ptr));
++	if (ptdls_sta == NULL) {
++		switch (*paction) {
++		case TDLS_SETUP_REQUEST:
++		case TDLS_DISCOVERY_REQUEST:
++			break;
++		default:
++			RTW_INFO("[TDLS] %s - Direct Link Peer = "MAC_FMT" not found for action = %d\n", __func__, MAC_ARG(get_sa(ptr)), *paction);
++			ret = _FAIL;
++			goto exit;
++		}
++	}
++
++	switch (*paction) {
++	case TDLS_SETUP_REQUEST:
++		ret = On_TDLS_Setup_Req(adapter, precv_frame, ptdls_sta);
++		break;
++	case TDLS_SETUP_RESPONSE:
++		ret = On_TDLS_Setup_Rsp(adapter, precv_frame, ptdls_sta);
++		break;
++	case TDLS_SETUP_CONFIRM:
++		ret = On_TDLS_Setup_Cfm(adapter, precv_frame, ptdls_sta);
++		break;
++	case TDLS_TEARDOWN:
++		ret = On_TDLS_Teardown(adapter, precv_frame, ptdls_sta);
++		break;
++	case TDLS_DISCOVERY_REQUEST:
++		ret = On_TDLS_Dis_Req(adapter, precv_frame);
++		break;
++	case TDLS_PEER_TRAFFIC_INDICATION:
++		ret = On_TDLS_Peer_Traffic_Indication(adapter, precv_frame, ptdls_sta);
++		break;
++	case TDLS_PEER_TRAFFIC_RESPONSE:
++		ret = On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame, ptdls_sta);
++		break;
++#ifdef CONFIG_TDLS_CH_SW
++	case TDLS_CHANNEL_SWITCH_REQUEST:
++		ret = On_TDLS_Ch_Switch_Req(adapter, precv_frame, ptdls_sta);
++		break;
++	case TDLS_CHANNEL_SWITCH_RESPONSE:
++		ret = On_TDLS_Ch_Switch_Rsp(adapter, precv_frame, ptdls_sta);
++		break;
++#endif
++#ifdef CONFIG_WFD
++	/* First byte of WFA OUI */
++	case 0x50:
++		if (_rtw_memcmp(WFA_OUI, paction, 3)) {
++			/* Probe request frame */
++			if (*(paction + 3) == 0x04) {
++				/* WFDTDLS: for sigma test, do not setup direct link automatically */
++				ptdlsinfo->dev_discovered = _TRUE;
++				RTW_INFO("recv tunneled probe request frame\n");
++				issue_tunneled_probe_rsp(adapter, precv_frame);
++			}
++			/* Probe response frame */
++			if (*(paction + 3) == 0x05) {
++				/* WFDTDLS: for sigma test, do not setup direct link automatically */
++				ptdlsinfo->dev_discovered = _TRUE;
++				RTW_INFO("recv tunneled probe response frame\n");
++			}
++		}
++		break;
++#endif /* CONFIG_WFD */
++	default:
++		RTW_INFO("receive TDLS frame %d but not support\n", *paction);
++		ret = _FAIL;
++		break;
++	}
++
++exit:
++	return ret;
++
++}
++
++sint rtw_tdls_rx_data_validate_hdr(
++	_adapter *adapter,
++	union recv_frame *precv_frame,
++	struct sta_info **psta
++)
++{
++	u8 *ptr = precv_frame->u.hdr.rx_data;
++	sint ret = _SUCCESS;
++	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++	struct	sta_priv		*pstapriv = &adapter->stapriv;
++	struct	mlme_priv	*pmlmepriv = &adapter->mlmepriv;
++	u8 *mybssid  = get_bssid(pmlmepriv);
++	u8 *myhwaddr = adapter_mac_addr(adapter);
++	u8 *sta_addr = pattrib->ta;
++	sint bmcast = IS_MCAST(pattrib->dst);
++
++	struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
++#ifdef CONFIG_TDLS_CH_SW
++	struct tdls_ch_switch *pchsw_info = &ptdlsinfo->chsw_info;
++#endif
++	struct sta_info *ptdls_sta = NULL;
++	u8 *psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE;
++	/* frame body located after [+2]: ether-type, [+1]: payload type */
++	u8 *pframe_body = psnap_type + 2 + 1;
++
++	*psta = ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->ta);
++	if (ptdls_sta == NULL) {
++		ret = _FAIL;
++		goto exit;
++	} else if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {
++		/* filter packets that SA is myself or multicast or broadcast */
++		if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) {
++			ret = _FAIL;
++			goto exit;
++		}
++		/* da should be for me */
++		if ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast)) {
++			ret = _FAIL;
++			goto exit;
++		}
++		/* check BSSID */
++		if (_rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
++		    _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
++		    (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))) {
++			ret = _FAIL;
++			goto exit;
++		}
++
++#ifdef CONFIG_TDLS_CH_SW
++		if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) {
++			if (adapter->mlmeextpriv.cur_channel != rtw_get_oper_ch(adapter)) {
++				pchsw_info->ch_sw_state |= TDLS_PEER_AT_OFF_STATE;
++				if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
++					_cancel_timer_ex(&ptdls_sta->ch_sw_timer);
++				/* On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame); */
++			}
++		}
++#endif
++
++		/* process UAPSD tdls sta */
++		process_pwrbit_data(adapter, precv_frame, ptdls_sta);
++
++		/* if NULL-frame, check pwrbit */
++		if ((get_frame_sub_type(ptr) & WIFI_DATA_NULL) == WIFI_DATA_NULL) {
++			/* NULL-frame with pwrbit=1, buffer_STA should buffer frames for sleep_STA */
++			if (GetPwrMgt(ptr)) {
++				/* it would be triggered when we are off channel and receiving NULL DATA */
++				/* we can confirm that peer STA is at off channel */
++				RTW_INFO("TDLS: recv peer null frame with pwr bit 1\n");
++				/* ptdls_sta->tdls_sta_state|=TDLS_PEER_SLEEP_STATE; */
++			}
++
++			/* TODO: Updated BSSID's seq. */
++			/* RTW_INFO("drop Null Data\n"); */
++			ptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE);
++			ret = _FAIL;
++			goto exit;
++		}
++
++		/* receive some of all TDLS management frames, process it at ON_TDLS */
++		if (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_TDLS, 2)) {
++			ret = OnTDLS(adapter, precv_frame);
++			goto exit;
++		}
++
++		if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE)
++			process_wmmps_data(adapter, precv_frame, ptdls_sta);
++
++		ptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE);
++
++	}
++
++exit:
++	return ret;
++}
++#endif /* CONFIG_TDLS */
++
++void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta)
++{
++	int	sz;
++	struct sta_info		*psta = NULL;
++	struct stainfo_stats	*pstats = NULL;
++	struct rx_pkt_attrib	*pattrib = &prframe->u.hdr.attrib;
++	struct recv_priv		*precvpriv = &padapter->recvpriv;
++
++	sz = get_recvframe_len(prframe);
++	precvpriv->rx_bytes += sz;
++
++	padapter->mlmepriv.LinkDetectInfo.NumRxOkInPeriod++;
++
++	if ((!MacAddr_isBcst(pattrib->dst)) && (!IS_MCAST(pattrib->dst)))
++		padapter->mlmepriv.LinkDetectInfo.NumRxUnicastOkInPeriod++;
++
++	if (sta)
++		psta = sta;
++	else
++		psta = prframe->u.hdr.psta;
++
++	if (psta) {
++		u8 is_ra_bmc = IS_MCAST(pattrib->ra);
++
++		pstats = &psta->sta_stats;
++
++		pstats->last_rx_time = rtw_get_current_time();
++		pstats->rx_data_pkts++;
++		pstats->rx_bytes += sz;
++		if (is_broadcast_mac_addr(pattrib->ra)) {
++			pstats->rx_data_bc_pkts++;
++			pstats->rx_bc_bytes += sz;
++		} else if (is_ra_bmc) {
++			pstats->rx_data_mc_pkts++;
++			pstats->rx_mc_bytes += sz;
++		}
++
++		if (!is_ra_bmc) {
++			pstats->rxratecnt[pattrib->data_rate]++;
++			/*record rx packets for every tid*/
++			pstats->rx_data_qos_pkts[pattrib->priority]++;
++		}
++#ifdef CONFIG_DYNAMIC_SOML
++		rtw_dyn_soml_byte_update(padapter, pattrib->data_rate, sz);
++#endif
++#if defined(CONFIG_CHECK_LEAVE_LPS) && defined(CONFIG_LPS_CHK_BY_TP)
++		if (adapter_to_pwrctl(padapter)->lps_chk_by_tp)
++			traffic_check_for_leave_lps_by_tp(padapter, _FALSE, psta);
++#endif /* CONFIG_LPS */
++
++	}
++
++#ifdef CONFIG_CHECK_LEAVE_LPS
++#ifdef CONFIG_LPS_CHK_BY_TP
++	if (!adapter_to_pwrctl(padapter)->lps_chk_by_tp)
++#endif
++		traffic_check_for_leave_lps(padapter, _FALSE, 0);
++#endif /* CONFIG_CHECK_LEAVE_LPS */
++
++}
++
++int rtw_sta_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta)
++{
++	struct sta_priv *stapriv = &adapter->stapriv;
++	u8 *mybssid  = get_bssid(&adapter->mlmepriv);
++	u8 *myhwaddr = adapter_mac_addr(adapter);
++	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
++	u8 *whdr = get_recvframe_data(rframe);
++	u8 is_ra_bmc = IS_MCAST(GetAddr1Ptr(whdr)) ? 1 : 0;
++	sint ret = _FAIL;
++
++	if (rattrib->to_fr_ds == 0) {
++		_rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);
++		_rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);
++		_rtw_memcpy(rattrib->dst, GetAddr1Ptr(whdr), ETH_ALEN);
++		_rtw_memcpy(rattrib->src, get_addr2_ptr(whdr), ETH_ALEN);
++		_rtw_memcpy(rattrib->bssid, GetAddr3Ptr(whdr), ETH_ALEN);
++
++		#ifdef CONFIG_TDLS
++		if (adapter->tdlsinfo.link_established == _TRUE)
++			ret = rtw_tdls_rx_data_validate_hdr(adapter, rframe, sta);
++		else
++		#endif
++		{
++			/* For Station mode, sa and bssid should always be BSSID, and DA is my mac-address */
++			if (!_rtw_memcmp(rattrib->bssid, rattrib->src, ETH_ALEN))
++				goto exit;
++
++			*sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr));
++			if (*sta)
++				ret = _SUCCESS;
++		}
++		goto exit;
++	}
++
++	if (!(MLME_STATE(adapter) & (WIFI_ASOC_STATE | WIFI_UNDER_LINKING))) {
++		if (!is_ra_bmc) {
++			/* for AP multicast issue , modify by yiwei */
++			static systime send_issue_deauth_time = 0;
++
++			/* RTW_INFO("After send deauth , %u ms has elapsed.\n", rtw_get_passing_time_ms(send_issue_deauth_time)); */
++			if (rtw_get_passing_time_ms(send_issue_deauth_time) > 10000 || send_issue_deauth_time == 0) {
++				send_issue_deauth_time = rtw_get_current_time();
++				RTW_INFO(FUNC_ADPT_FMT" issue_deauth to "MAC_FMT" with reason(7), mlme_state:0x%x\n"
++					, FUNC_ADPT_ARG(adapter), MAC_ARG(get_addr2_ptr(whdr)), MLME_STATE(adapter));
++				issue_deauth(adapter, get_addr2_ptr(whdr), WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
++			}
++		}
++		#ifdef DBG_RX_DROP_FRAME
++		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" fw_state:0x%x\n"
++			, FUNC_ADPT_ARG(adapter), MLME_STATE(adapter));
++		#endif
++		goto exit;
++	}
++
++	_rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);
++	_rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);
++
++	switch (rattrib->to_fr_ds) {
++	case 1:
++		_rtw_memcpy(rattrib->dst, GetAddr1Ptr(whdr), ETH_ALEN);
++		_rtw_memcpy(rattrib->src, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
++		_rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN);
++		break;
++	case 3:
++		_rtw_memcpy(rattrib->dst, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
++		_rtw_memcpy(rattrib->src, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
++		_rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN);
++		break;
++	default:
++		ret = RTW_RX_HANDLED; /* don't count for drop */
++		goto exit;
++	}
++
++	/* filter packets that SA is myself */
++	if (!rattrib->amsdu && _rtw_memcmp(myhwaddr, rattrib->src, ETH_ALEN)) {
++		#ifdef DBG_RX_DROP_FRAME
++		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" SA="MAC_FMT", myhwaddr="MAC_FMT"\n"
++			, FUNC_ADPT_ARG(adapter), MAC_ARG(rattrib->src), MAC_ARG(myhwaddr));
++		#endif
++		goto exit;
++	}
++
++	*sta = rtw_get_stainfo(stapriv, rattrib->ta);
++	if (*sta == NULL) {
++		#ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL
++		if (!is_ra_bmc && !IS_RADAR_DETECTED(adapter_to_rfctl(adapter))) {
++			RTW_INFO(FUNC_ADPT_FMT" issue_deauth to "MAC_FMT" with reason(7), unknown TA\n"
++				, FUNC_ADPT_ARG(adapter), MAC_ARG(rattrib->ta));
++			issue_deauth(adapter, rattrib->ta, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
++		}
++		#endif
++		#ifdef DBG_RX_DROP_FRAME
++		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under STATION_MODE ; drop pkt\n"
++			, FUNC_ADPT_ARG(adapter));
++		#endif
++		goto exit;
++	}
++
++#ifdef CONFIG_RTW_WDS_AUTO_EN
++	if (rattrib->to_fr_ds == 3 && !(sta->flags & WLAN_STA_WDS))
++		sta->flags |= WLAN_STA_WDS;
++#endif
++
++	/*if ((get_frame_sub_type(whdr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) {
++	}
++	*/
++
++	if (get_frame_sub_type(whdr) & BIT(6)) {
++		/* No data, will not indicate to upper layer, temporily count it here */
++		count_rx_stats(adapter, rframe, *sta);
++		ret = RTW_RX_HANDLED;
++		goto exit;
++	}
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++
++sint sta2sta_data_frame(
++	_adapter *adapter,
++	union recv_frame *precv_frame,
++	struct sta_info **psta
++)
++{
++	u8 *ptr = precv_frame->u.hdr.rx_data;
++	sint ret = _SUCCESS;
++	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++	struct	sta_priv		*pstapriv = &adapter->stapriv;
++	struct	mlme_priv	*pmlmepriv = &adapter->mlmepriv;
++	u8 *mybssid  = get_bssid(pmlmepriv);
++	u8 *myhwaddr = adapter_mac_addr(adapter);
++	u8 *sta_addr = pattrib->ta;
++	sint bmcast = IS_MCAST(pattrib->dst);
++
++	/* RTW_INFO("[%s] %d, seqnum:%d\n", __FUNCTION__, __LINE__, pattrib->seq_num); */
++
++	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ||
++	    (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
++
++		/* filter packets that SA is myself or multicast or broadcast */
++		if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) {
++			ret = _FAIL;
++			goto exit;
++		}
++
++		if ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN))	&& (!bmcast)) {
++			ret = _FAIL;
++			goto exit;
++		}
++
++		if (_rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
++		    _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
++		    (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))) {
++			ret = _FAIL;
++			goto exit;
++		}
++
++	} else if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) {
++		_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
++		_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++		sta_addr = mybssid;
++	} else
++		ret  = _FAIL;
++
++	*psta = rtw_get_stainfo(pstapriv, sta_addr);
++	if (*psta == NULL) {
++#ifdef CONFIG_MP_INCLUDED
++		if (adapter->registrypriv.mp_mode == 1) {
++			if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
++				adapter->mppriv.rx_pktloss++;
++		}
++#endif
++		ret = _FAIL;
++		goto exit;
++	}
++
++exit:
++	return ret;
++}
++
++sint ap2sta_data_frame(
++	_adapter *adapter,
++	union recv_frame *precv_frame,
++	struct sta_info **psta)
++{
++	u8 *ptr = precv_frame->u.hdr.rx_data;
++	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++	sint ret = _SUCCESS;
++	struct	sta_priv		*pstapriv = &adapter->stapriv;
++	struct	mlme_priv	*pmlmepriv = &adapter->mlmepriv;
++	u8 *myhwaddr = adapter_mac_addr(adapter);
++	sint bmcast = IS_MCAST(pattrib->dst);
++
++	if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) &&
++		   (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) {
++		_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
++		_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++
++		*psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */
++		if (*psta == NULL) {
++			#ifdef DBG_RX_DROP_FRAME
++			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under WIFI_MP_STATE ; drop pkt\n"
++				, FUNC_ADPT_ARG(adapter));
++			#endif
++			ret = _FAIL;
++			goto exit;
++		}
++
++	} else {
++		if (_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN) && (!bmcast)) {
++			*psta = rtw_get_stainfo(pstapriv, pattrib->ta);
++			if (*psta == NULL) {
++
++				/* for AP multicast issue , modify by yiwei */
++				static systime send_issue_deauth_time = 0;
++
++				/* RTW_INFO("After send deauth , %u ms has elapsed.\n", rtw_get_passing_time_ms(send_issue_deauth_time)); */
++
++				if (rtw_get_passing_time_ms(send_issue_deauth_time) > 10000 || send_issue_deauth_time == 0) {
++					send_issue_deauth_time = rtw_get_current_time();
++
++					RTW_INFO("issue_deauth to the ap=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->bssid));
++
++					issue_deauth(adapter, pattrib->bssid, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
++				}
++			}
++		}
++
++		ret = _FAIL;
++		#ifdef DBG_RX_DROP_FRAME
++		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" fw_state:0x%x\n"
++			, FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv));
++		#endif
++	}
++
++exit:
++	return ret;
++
++}
++
++sint sta2ap_data_frame(
++	_adapter *adapter,
++	union recv_frame *precv_frame,
++	struct sta_info **psta)
++{
++	u8 *ptr = precv_frame->u.hdr.rx_data;
++	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++	struct	sta_priv		*pstapriv = &adapter->stapriv;
++	struct	mlme_priv	*pmlmepriv = &adapter->mlmepriv;
++	unsigned char *mybssid  = get_bssid(pmlmepriv);
++	sint ret = _SUCCESS;
++
++	if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) &&
++		   (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) {
++		/* RTW_INFO("%s ,in WIFI_MP_STATE\n",__func__); */
++		_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
++		_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++
++		*psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */
++		if (*psta == NULL) {
++			#ifdef DBG_RX_DROP_FRAME
++			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under WIFI_MP_STATE ; drop pkt\n"
++				, FUNC_ADPT_ARG(adapter));
++			#endif
++			ret = _FAIL;
++			goto exit;
++		}
++
++	} else {
++		u8 *myhwaddr = adapter_mac_addr(adapter);
++		if (!_rtw_memcmp(pattrib->ra, myhwaddr, ETH_ALEN)) {
++			ret = RTW_RX_HANDLED;
++			goto exit;
++		}
++#ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL
++		RTW_INFO("issue_deauth to sta=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->src));
++		issue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
++#endif
++		ret = RTW_RX_HANDLED;
++		goto exit;
++	}
++
++exit:
++
++
++	return ret;
++
++}
++
++sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame);
++sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame)
++{
++	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	struct sta_info *psta = NULL;
++	/* uint len = precv_frame->u.hdr.len; */
++
++	/* RTW_INFO("+validate_recv_ctrl_frame\n"); */
++
++	if (GetFrameType(pframe) != WIFI_CTRL_TYPE)
++		return _FAIL;
++
++	/* receive the frames that ra(a1) is my address */
++	if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN))
++		return _FAIL;
++
++	psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
++	if (psta == NULL)
++		return _FAIL;
++
++	/* for rx pkt statistics */
++	psta->sta_stats.last_rx_time = rtw_get_current_time();
++	psta->sta_stats.rx_ctrl_pkts++;
++
++	/* only handle ps-poll */
++	if (get_frame_sub_type(pframe) == WIFI_PSPOLL) {
++#ifdef CONFIG_AP_MODE
++		u16 aid;
++		u8 wmmps_ac = 0;
++
++		aid = GetAid(pframe);
++		if (psta->cmn.aid != aid)
++			return _FAIL;
++
++		switch (pattrib->priority) {
++		case 1:
++		case 2:
++			wmmps_ac = psta->uapsd_bk & BIT(0);
++			break;
++		case 4:
++		case 5:
++			wmmps_ac = psta->uapsd_vi & BIT(0);
++			break;
++		case 6:
++		case 7:
++			wmmps_ac = psta->uapsd_vo & BIT(0);
++			break;
++		case 0:
++		case 3:
++		default:
++			wmmps_ac = psta->uapsd_be & BIT(0);
++			break;
++		}
++
++		if (wmmps_ac)
++			return _FAIL;
++
++		if (psta->state & WIFI_STA_ALIVE_CHK_STATE) {
++			RTW_INFO("%s alive check-rx ps-poll\n", __func__);
++			psta->expire_to = pstapriv->expire_to;
++			psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
++		}
++
++		if ((psta->state & WIFI_SLEEP_STATE) && (rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid))) {
++			_irqL irqL;
++			_list	*xmitframe_plist, *xmitframe_phead;
++			struct xmit_frame *pxmitframe = NULL;
++			struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++			/* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */
++			_enter_critical_bh(&pxmitpriv->lock, &irqL);
++
++			xmitframe_phead = get_list_head(&psta->sleep_q);
++			xmitframe_plist = get_next(xmitframe_phead);
++
++			if ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
++				pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
++
++				xmitframe_plist = get_next(xmitframe_plist);
++
++				rtw_list_delete(&pxmitframe->list);
++
++				psta->sleepq_len--;
++
++				if (psta->sleepq_len > 0)
++					pxmitframe->attrib.mdata = 1;
++				else
++					pxmitframe->attrib.mdata = 0;
++
++				pxmitframe->attrib.triggered = 1;
++
++				/* RTW_INFO("handling ps-poll, q_len=%d\n", psta->sleepq_len); */
++				/* RTW_INFO_DUMP("handling, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
++
++#if 0
++				_exit_critical_bh(&psta->sleep_q.lock, &irqL);
++				if (rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
++					rtw_os_xmit_complete(padapter, pxmitframe);
++				_enter_critical_bh(&psta->sleep_q.lock, &irqL);
++#endif
++				rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
++
++				if (psta->sleepq_len == 0) {
++					rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
++
++					/* RTW_INFO("after handling ps-poll\n"); */
++					/* RTW_INFO_DUMP("after handling, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
++
++					/* upate BCN for TIM IE */
++					/* update_BCNTIM(padapter);		 */
++					update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0);
++				}
++
++				/* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */
++				_exit_critical_bh(&pxmitpriv->lock, &irqL);
++
++			} else {
++				/* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */
++				_exit_critical_bh(&pxmitpriv->lock, &irqL);
++
++				/* RTW_INFO("no buffered packets to xmit\n"); */
++				if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) {
++					if (psta->sleepq_len == 0) {
++						RTW_INFO("no buffered packets to xmit\n");
++
++						/* issue nulldata with More data bit = 0 to indicate we have no buffered packets */
++						issue_nulldata(padapter, psta->cmn.mac_addr, 0, 0, 0);
++					} else {
++						RTW_INFO("error!psta->sleepq_len=%d\n", psta->sleepq_len);
++						psta->sleepq_len = 0;
++					}
++
++					rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
++
++					/* upate BCN for TIM IE */
++					/* update_BCNTIM(padapter); */
++					update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0);
++				}
++			}
++		}
++#endif /* CONFIG_AP_MODE */
++	} else if (get_frame_sub_type(pframe) == WIFI_NDPA) {
++#ifdef CONFIG_BEAMFORMING
++		rtw_beamforming_get_ndpa_frame(padapter, precv_frame);
++#endif/*CONFIG_BEAMFORMING*/
++	} else if (get_frame_sub_type(pframe) == WIFI_BAR) {
++		rtw_process_bar_frame(padapter, precv_frame);
++	}
++
++	return _FAIL;
++
++}
++
++#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
++static sint validate_mgmt_protect(_adapter *adapter, union recv_frame *precv_frame)
++{
++#define DBG_VALIDATE_MGMT_PROTECT 0
++#define DBG_VALIDATE_MGMT_DEC 0
++
++	struct security_priv *sec = &adapter->securitypriv;
++	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++	struct sta_info	*psta = precv_frame->u.hdr.psta;
++	u8 *ptr;
++	u8 type;
++	u8 subtype;
++	u8 is_bmc;
++	u8 category = 0xFF;
++
++#ifdef CONFIG_IEEE80211W
++	const u8 *igtk;
++	u16 igtk_id;
++	u64* ipn;
++	enum security_type bip_cipher;
++#endif
++
++	u8 *mgmt_DATA;
++	u32 data_len = 0;
++
++	sint ret;
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(adapter)) {
++		if (!adapter->mesh_info.mesh_auth_id)
++			return pattrib->privacy ? _FAIL : _SUCCESS;
++	} else
++#endif
++	if (SEC_IS_BIP_KEY_INSTALLED(sec) == _FALSE)
++		return _SUCCESS;
++
++	ptr = precv_frame->u.hdr.rx_data;
++	type = GetFrameType(ptr);
++	subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */
++	is_bmc = IS_MCAST(GetAddr1Ptr(ptr));
++
++#if DBG_VALIDATE_MGMT_PROTECT
++	if (subtype == WIFI_DEAUTH) {
++		RTW_INFO(FUNC_ADPT_FMT" bmc:%u, deauth, privacy:%u, encrypt:%u, bdecrypted:%u\n"
++			, FUNC_ADPT_ARG(adapter)
++			, is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);
++	} else if (subtype == WIFI_DISASSOC) {
++		RTW_INFO(FUNC_ADPT_FMT" bmc:%u, disassoc, privacy:%u, encrypt:%u, bdecrypted:%u\n"
++			, FUNC_ADPT_ARG(adapter)
++			, is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);
++	} if (subtype == WIFI_ACTION) {
++		if (pattrib->privacy) {
++			RTW_INFO(FUNC_ADPT_FMT" bmc:%u, action(?), privacy:%u, encrypt:%u, bdecrypted:%u\n"
++				, FUNC_ADPT_ARG(adapter)
++				, is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);
++		} else {
++			RTW_INFO(FUNC_ADPT_FMT" bmc:%u, action(%u), privacy:%u, encrypt:%u, bdecrypted:%u\n"
++				, FUNC_ADPT_ARG(adapter), is_bmc
++				, *(ptr + sizeof(struct rtw_ieee80211_hdr_3addr))
++				, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);
++		}
++	}
++#endif
++
++	if (!pattrib->privacy) {
++		if (!psta || !(psta->flags & WLAN_STA_MFP)) {
++			/* peer is not MFP capable, no need to check */
++			goto exit;
++		}
++
++		if (subtype == WIFI_ACTION)
++			category = *(ptr + sizeof(struct rtw_ieee80211_hdr_3addr));
++
++		if (is_bmc) {
++			/* broadcast cases */
++			if (subtype == WIFI_ACTION) {
++				if (CATEGORY_IS_GROUP_PRIVACY(category)) {
++					/* drop broadcast group privacy action frame without encryption */
++					#if DBG_VALIDATE_MGMT_PROTECT
++					RTW_INFO(FUNC_ADPT_FMT" broadcast gp action(%u) w/o encrypt\n"
++						, FUNC_ADPT_ARG(adapter), category);
++					#endif
++					goto fail;
++				}
++				if (CATEGORY_IS_ROBUST(category)) {
++					/* broadcast robust action frame need BIP check */
++					goto bip_verify;
++				}
++			}
++			if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) {
++				/* broadcast deauth or disassoc frame need BIP check */
++				goto bip_verify;
++			}
++			goto exit;
++
++		} else {
++			/* unicast cases */
++			#ifdef CONFIG_IEEE80211W
++			if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) {
++				if (!MLME_IS_MESH(adapter)) {
++					unsigned short reason = le16_to_cpu(*(unsigned short *)(ptr + WLAN_HDR_A3_LEN));
++
++					#if DBG_VALIDATE_MGMT_PROTECT
++					RTW_INFO(FUNC_ADPT_FMT" unicast %s, reason=%d w/o encrypt\n"
++						, FUNC_ADPT_ARG(adapter), subtype == WIFI_DEAUTH ? "deauth" : "disassoc", reason);
++					#endif
++					if (reason == 6 || reason == 7) {
++						/* issue sa query request */
++						issue_action_SA_Query(adapter, psta->cmn.mac_addr, 0, 0, IEEE80211W_RIGHT_KEY);
++					}
++				}
++				goto fail;
++			}
++			#endif
++
++			if (subtype == WIFI_ACTION && CATEGORY_IS_ROBUST(category)) {
++				if (psta->bpairwise_key_installed == _TRUE) {
++					#if DBG_VALIDATE_MGMT_PROTECT
++					RTW_INFO(FUNC_ADPT_FMT" unicast robust action(%d) w/o encrypt\n"
++						, FUNC_ADPT_ARG(adapter), category);
++					#endif
++					goto fail;
++				}
++			}
++			goto exit;
++		}
++
++bip_verify:
++#ifdef CONFIG_IEEE80211W
++		#ifdef CONFIG_RTW_MESH
++		if (MLME_IS_MESH(adapter)) {
++			if (psta->igtk_bmp) {
++				bip_cipher = psta->dot11wCipher;
++				igtk = psta->igtk.skey;
++				igtk_id = psta->igtk_id;
++				ipn = &psta->igtk_pn.val;
++			} else {
++				/* mesh MFP without IGTK */
++				goto exit;
++			}
++		} else
++		#endif
++		{
++			bip_cipher = sec->dot11wCipher;
++			igtk = sec->dot11wBIPKey[sec->dot11wBIPKeyid].skey;
++			igtk_id = sec->dot11wBIPKeyid;
++			ipn = &sec->dot11wBIPrxpn.val;
++		}
++
++		/* verify BIP MME IE */
++		ret = rtw_bip_verify(bip_cipher, pattrib->pkt_len,
++			get_recvframe_data(precv_frame),
++			get_recvframe_len(precv_frame),
++			igtk, igtk_id, ipn);
++
++		if (ret == _FAIL) {
++			/* RTW_INFO("802.11w BIP verify fail\n"); */
++			goto fail;
++
++		} else if (ret == RTW_RX_HANDLED) {
++			#if DBG_VALIDATE_MGMT_PROTECT
++			RTW_INFO(FUNC_ADPT_FMT" none protected packet\n", FUNC_ADPT_ARG(adapter));
++			#endif
++			goto fail;
++		}
++#endif /* CONFIG_IEEE80211W */
++		goto exit;
++	}
++
++	if (!psta || !(psta->flags & WLAN_STA_MFP)) {
++		/* not peer or peer is not MFP capable, drop it */
++		goto fail;
++	}
++
++	/* cases to decrypt mgmt frame */
++	pattrib->bdecrypted = 0;
++#ifdef CONFIG_RTW_MESH
++	if (is_bmc)
++		pattrib->encrypt = psta->group_privacy;
++	else
++#endif
++	pattrib->encrypt = psta->dot118021XPrivacy;
++	pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	/* set iv and icv length */
++	SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt);
++	_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
++	_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
++
++	/* actual management data frame body */
++	data_len = pattrib->pkt_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
++	mgmt_DATA = rtw_zmalloc(data_len);
++	if (mgmt_DATA == NULL) {
++		RTW_INFO(FUNC_ADPT_FMT" mgmt allocate fail  !!!!!!!!!\n", FUNC_ADPT_ARG(adapter));
++		goto fail;
++	}
++
++#if DBG_VALIDATE_MGMT_DEC
++	/* dump the packet content before decrypt */
++	{
++		int pp;
++
++		printk("pattrib->pktlen = %d =>", pattrib->pkt_len);
++		for (pp = 0; pp < pattrib->pkt_len; pp++)
++		printk(" %02x ", ptr[pp]);
++		printk("\n");
++	}
++#endif
++
++	precv_frame = decryptor(adapter, precv_frame);
++	/* save actual management data frame body */
++	_rtw_memcpy(mgmt_DATA, ptr + pattrib->hdrlen + pattrib->iv_len, data_len);
++	/* overwrite the iv field */
++	_rtw_memcpy(ptr + pattrib->hdrlen, mgmt_DATA, data_len);
++	/* remove the iv and icv length */
++	pattrib->pkt_len = pattrib->pkt_len - pattrib->iv_len - pattrib->icv_len;
++	rtw_mfree(mgmt_DATA, data_len);
++
++#if DBG_VALIDATE_MGMT_DEC
++	/* print packet content after decryption */
++	{
++		int pp;
++
++		printk("after decryption pattrib->pktlen = %d @@=>", pattrib->pkt_len);
++		for (pp = 0; pp < pattrib->pkt_len; pp++)
++		printk(" %02x ", ptr[pp]);
++		printk("\n");
++	}
++#endif
++
++	if (!precv_frame) {
++		#if DBG_VALIDATE_MGMT_PROTECT
++		RTW_INFO(FUNC_ADPT_FMT" mgmt descrypt fail  !!!!!!!!!\n", FUNC_ADPT_ARG(adapter));
++		#endif
++		goto fail;
++	}
++
++exit:
++	return _SUCCESS;
++
++fail:
++	return _FAIL;
++
++}
++#endif /* defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) */
++
++union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame);
++
++sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame)
++{
++	struct sta_info *psta = precv_frame->u.hdr.psta
++		= rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(precv_frame->u.hdr.rx_data));
++
++#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
++	if (validate_mgmt_protect(padapter, precv_frame) == _FAIL) {
++		DBG_COUNTER(padapter->rx_logs.core_rx_pre_mgmt_err_80211w);
++		goto exit;
++	}
++#endif
++
++	precv_frame = recvframe_chk_defrag(padapter, precv_frame);
++	if (precv_frame == NULL)
++		return _SUCCESS;
++
++	/* for rx pkt statistics */
++	if (psta) {
++		psta->sta_stats.last_rx_time = rtw_get_current_time();
++		psta->sta_stats.rx_mgnt_pkts++;
++		if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_BEACON)
++			psta->sta_stats.rx_beacon_pkts++;
++		else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBEREQ)
++			psta->sta_stats.rx_probereq_pkts++;
++		else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBERSP) {
++			if (_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(precv_frame->u.hdr.rx_data), ETH_ALEN) == _TRUE)
++				psta->sta_stats.rx_probersp_pkts++;
++			else if (is_broadcast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data))
++				|| is_multicast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data)))
++				psta->sta_stats.rx_probersp_bm_pkts++;
++			else
++				psta->sta_stats.rx_probersp_uo_pkts++;
++		}
++	}
++
++	mgt_dispatcher(padapter, precv_frame);
++
++#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
++exit:
++#endif
++	return _SUCCESS;
++
++}
++
++sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame)
++{
++	u8 bretry, a4_shift;
++	struct sta_info *psta = NULL;
++	u8 *ptr = precv_frame->u.hdr.rx_data;
++	struct rx_pkt_attrib	*pattrib = &precv_frame->u.hdr.attrib;
++	struct security_priv	*psecuritypriv = &adapter->securitypriv;
++	sint ret = _SUCCESS;
++
++	bretry = GetRetry(ptr);
++	a4_shift = (pattrib->to_fr_ds == 3) ? ETH_ALEN : 0;
++
++	/* some address fields are different when using AMSDU */
++	if (pattrib->qos)
++		pattrib->amsdu = GetAMsdu(ptr + WLAN_HDR_A3_LEN + a4_shift);
++	else
++		pattrib->amsdu = 0;
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(adapter)) {
++		ret = rtw_mesh_rx_data_validate_hdr(adapter, precv_frame, &psta);
++		goto pre_validate_status_chk;
++	} else
++#endif
++#ifdef CONFIG_AP_MODE
++	if (MLME_IS_AP(adapter)) {
++		ret = rtw_ap_rx_data_validate_hdr(adapter, precv_frame, &psta);
++		goto pre_validate_status_chk;
++	} else
++#endif
++	if (MLME_IS_STA(adapter)) {
++		ret = rtw_sta_rx_data_validate_hdr(adapter, precv_frame, &psta);
++		goto pre_validate_status_chk;
++	}
++
++	switch (pattrib->to_fr_ds) {
++	case 0:
++		_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
++		ret = sta2sta_data_frame(adapter, precv_frame, &psta);
++		break;
++
++	case 1:
++		_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->src, GetAddr3Ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->bssid, get_addr2_ptr(ptr), ETH_ALEN);
++		ret = ap2sta_data_frame(adapter, precv_frame, &psta);
++		break;
++
++	case 2:
++		_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->dst, GetAddr3Ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
++		_rtw_memcpy(pattrib->bssid, GetAddr1Ptr(ptr), ETH_ALEN);
++		ret = sta2ap_data_frame(adapter, precv_frame, &psta);
++		break;
++
++	case 3:
++	default:
++		/* WDS is not supported */
++		ret = _FAIL;
++		break;
++	}
++
++pre_validate_status_chk:
++
++	if (ret == _FAIL) {
++		#ifdef DBG_RX_DROP_FRAME
++		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" case:%d, res:%d, ra="MAC_FMT", ta="MAC_FMT"\n"
++			, FUNC_ADPT_ARG(adapter), pattrib->to_fr_ds, ret, MAC_ARG(GetAddr1Ptr(ptr)), MAC_ARG(get_addr2_ptr(ptr)));
++		#endif
++		goto exit;
++	} else if (ret == RTW_RX_HANDLED)
++		goto exit;
++
++
++	if (psta == NULL) {
++		#ifdef DBG_RX_DROP_FRAME
++		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" psta == NULL, ra="MAC_FMT", ta="MAC_FMT"\n"
++			, FUNC_ADPT_ARG(adapter), MAC_ARG(GetAddr1Ptr(ptr)), MAC_ARG(get_addr2_ptr(ptr)));
++		#endif
++		ret = _FAIL;
++		goto exit;
++	}
++
++	precv_frame->u.hdr.psta = psta;
++	precv_frame->u.hdr.preorder_ctrl = NULL;
++	pattrib->ack_policy = 0;
++
++	/* parsing QC field */
++	if (pattrib->qos == 1) {
++		pattrib->priority = GetPriority((ptr + WLAN_HDR_A3_LEN + a4_shift)); /* point to Qos field*/
++		pattrib->ack_policy = GetAckpolicy((ptr + WLAN_HDR_A3_LEN + a4_shift));
++		pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN + a4_shift;
++		if (pattrib->priority != 0 && pattrib->priority != 3)
++			adapter->recvpriv.is_any_non_be_pkts = _TRUE;
++		else
++			adapter->recvpriv.is_any_non_be_pkts = _FALSE;
++	} else {
++		pattrib->priority = 0;
++		pattrib->hdrlen = WLAN_HDR_A3_LEN + a4_shift;
++	}
++
++	if (pattrib->order) /* HT-CTRL 11n */
++		pattrib->hdrlen += 4;
++
++	/* decache, drop duplicate recv packets */
++	ret = recv_decache(precv_frame);
++	if (ret  == _FAIL)
++		goto exit;
++
++	if (!IS_MCAST(pattrib->ra)) {
++
++		if (pattrib->qos)
++			precv_frame->u.hdr.preorder_ctrl = &psta->recvreorder_ctrl[pattrib->priority];
++
++		if (recv_ucast_pn_decache(precv_frame) == _FAIL) {
++			#ifdef DBG_RX_DROP_FRAME
++			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_ucast_pn_decache return _FAIL for sta="MAC_FMT"\n"
++				, FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr));
++			#endif
++			ret = _FAIL;
++			goto exit;
++		}
++	} else {
++		if (recv_bcast_pn_decache(precv_frame) == _FAIL) {
++			#ifdef DBG_RX_DROP_FRAME
++			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_bcast_pn_decache return _FAIL for sta="MAC_FMT"\n"
++				, FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr));
++			#endif
++			ret = _FAIL;
++			goto exit;
++		}
++	}
++
++	if (pattrib->privacy) {
++#ifdef CONFIG_TDLS
++		if ((psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta->dot118021XPrivacy == _AES_))
++			pattrib->encrypt = psta->dot118021XPrivacy;
++		else
++#endif /* CONFIG_TDLS */
++			GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, IS_MCAST(pattrib->ra));
++
++
++		SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt);
++	} else {
++		pattrib->encrypt = 0;
++		pattrib->iv_len = pattrib->icv_len = 0;
++	}
++
++#ifdef CONFIG_RTW_MESH
++	if (!pattrib->amsdu
++		&& pattrib->mesh_ctrl_present
++		&& (!pattrib->encrypt || pattrib->bdecrypted))
++		ret = rtw_mesh_rx_validate_mctrl_non_amsdu(adapter, precv_frame);
++#endif
++
++exit:
++	return ret;
++}
++
++static inline void dump_rx_packet(u8 *ptr)
++{
++	int i;
++
++	RTW_INFO("#############################\n");
++	for (i = 0; i < 64; i = i + 8)
++		RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr + i),
++			*(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7));
++	RTW_INFO("#############################\n");
++}
++
++sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame);
++sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
++{
++	/* shall check frame subtype, to / from ds, da, bssid */
++
++	/* then call check if rx seq/frag. duplicated. */
++
++	u8 type;
++	u8 subtype;
++	sint retval = _SUCCESS;
++
++	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++	struct recv_priv  *precvpriv = &adapter->recvpriv;
++
++	u8 *ptr = precv_frame->u.hdr.rx_data;
++	u8  ver = (unsigned char)(*ptr) & 0x3 ;
++#ifdef CONFIG_FIND_BEST_CHANNEL
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++#endif
++
++#ifdef CONFIG_TDLS
++	struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
++#endif /* CONFIG_TDLS */
++#ifdef CONFIG_WAPI_SUPPORT
++	PRT_WAPI_T	pWapiInfo = &adapter->wapiInfo;
++	struct recv_frame_hdr *phdr = &precv_frame->u.hdr;
++	u8 wai_pkt = 0;
++	u16 sc;
++	u8	external_len = 0;
++#endif
++
++
++#ifdef CONFIG_FIND_BEST_CHANNEL
++	if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {
++		int ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, rtw_get_oper_ch(adapter));
++		if (ch_set_idx >= 0)
++			rfctl->channel_set[ch_set_idx].rx_count++;
++	}
++#endif
++
++#ifdef CONFIG_TDLS
++	if (ptdlsinfo->ch_sensing == 1 && ptdlsinfo->cur_channel != 0)
++		ptdlsinfo->collect_pkt_num[ptdlsinfo->cur_channel - 1]++;
++#endif /* CONFIG_TDLS */
++
++#ifdef RTK_DMP_PLATFORM
++	if (0) {
++		RTW_INFO("++\n");
++		{
++			int i;
++			for (i = 0; i < 64; i = i + 8)
++				RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:", *(ptr + i),
++					*(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7));
++
++		}
++		RTW_INFO("--\n");
++	}
++#endif /* RTK_DMP_PLATFORM */
++
++	/* add version chk */
++	if (ver != 0) {
++		retval = _FAIL;
++		DBG_COUNTER(adapter->rx_logs.core_rx_pre_ver_err);
++		goto exit;
++	}
++
++	type =  GetFrameType(ptr);
++	subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */
++
++	pattrib->to_fr_ds = get_tofr_ds(ptr);
++
++	pattrib->frag_num = GetFragNum(ptr);
++	pattrib->seq_num = GetSequence(ptr);
++
++	pattrib->pw_save = GetPwrMgt(ptr);
++	pattrib->mfrag = GetMFrag(ptr);
++	pattrib->mdata = GetMData(ptr);
++	pattrib->privacy = GetPrivacy(ptr);
++	pattrib->order = GetOrder(ptr);
++#ifdef CONFIG_WAPI_SUPPORT
++	sc = (pattrib->seq_num << 4) | pattrib->frag_num;
++#endif
++
++#if 1 /* Dump rx packets */
++	{
++		u8 bDumpRxPkt = 0;
++
++		rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt));
++		if (bDumpRxPkt == 1) /* dump all rx packets */
++			dump_rx_packet(ptr);
++		else if ((bDumpRxPkt == 2) && (type == WIFI_MGT_TYPE))
++			dump_rx_packet(ptr);
++		else if ((bDumpRxPkt == 3) && (type == WIFI_DATA_TYPE))
++			dump_rx_packet(ptr);
++	}
++#endif
++	switch (type) {
++	case WIFI_MGT_TYPE: /* mgnt */
++		DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt);
++		retval = validate_recv_mgnt_frame(adapter, precv_frame);
++		if (retval == _FAIL) {
++			DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt_err);
++		}
++		retval = _FAIL; /* only data frame return _SUCCESS */
++		break;
++	case WIFI_CTRL_TYPE: /* ctrl */
++		DBG_COUNTER(adapter->rx_logs.core_rx_pre_ctrl);
++		retval = validate_recv_ctrl_frame(adapter, precv_frame);
++		if (retval == _FAIL) {
++			DBG_COUNTER(adapter->rx_logs.core_rx_pre_ctrl_err);
++		}
++		retval = _FAIL; /* only data frame return _SUCCESS */
++		break;
++	case WIFI_DATA_TYPE: /* data */
++		DBG_COUNTER(adapter->rx_logs.core_rx_pre_data);
++#ifdef CONFIG_WAPI_SUPPORT
++		if (pattrib->qos)
++			external_len = 2;
++		else
++			external_len = 0;
++
++		wai_pkt = rtw_wapi_is_wai_packet(adapter, ptr);
++
++		phdr->bIsWaiPacket = wai_pkt;
++
++		if (wai_pkt != 0) {
++			if (sc != adapter->wapiInfo.wapiSeqnumAndFragNum)
++				adapter->wapiInfo.wapiSeqnumAndFragNum = sc;
++			else {
++				retval = _FAIL;
++				DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_wapi_seq_err);
++				break;
++			}
++		} else {
++
++			if (rtw_wapi_drop_for_key_absent(adapter, get_addr2_ptr(ptr))) {
++				retval = _FAIL;
++				WAPI_TRACE(WAPI_RX, "drop for key absent for rx\n");
++				DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_wapi_key_err);
++				break;
++			}
++		}
++
++#endif
++
++		pattrib->qos = (subtype & BIT(7)) ? 1 : 0;
++		retval = validate_recv_data_frame(adapter, precv_frame);
++		if (retval == _FAIL) {
++			precvpriv->dbg_rx_drop_count++;
++			DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_err);
++		} else if (retval == _SUCCESS) {
++			#ifdef DBG_RX_DUMP_EAP
++			if (!pattrib->encrypt || pattrib->bdecrypted) {
++				u8 bDumpRxPkt;
++				u16 eth_type;
++
++				/* dump eapol */
++				rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt));
++				/* get ether_type */
++				_rtw_memcpy(&eth_type, ptr + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + LLC_HEADER_SIZE, 2);
++				eth_type = ntohs((unsigned short) eth_type);
++				if ((bDumpRxPkt == 4) && (eth_type == 0x888e))
++					dump_rx_packet(ptr);
++			}
++			#endif
++		} else
++			DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_handled);
++		break;
++	default:
++		DBG_COUNTER(adapter->rx_logs.core_rx_pre_unknown);
++		#ifdef DBG_RX_DROP_FRAME
++		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" fail! type=0x%x\n"
++			, FUNC_ADPT_ARG(adapter), type);
++		#endif
++		retval = _FAIL;
++		break;
++	}
++
++exit:
++
++
++	return retval;
++}
++
++/* Reture expected handling for LLC */
++enum rtw_rx_llc_hdl rtw_recv_llc_parse(u8 *msdu, u16 msdu_len)
++{
++	u16	eth_type;
++
++	if (msdu_len < 8)
++		return RTW_RX_LLC_KEEP;
++
++	eth_type = RTW_GET_BE16(msdu + SNAP_SIZE);
++
++	if ((_rtw_memcmp(msdu, rtw_rfc1042_header, SNAP_SIZE)
++			&& eth_type != ETH_P_AARP && eth_type != ETH_P_IPX)
++		|| _rtw_memcmp(msdu, rtw_bridge_tunnel_header, SNAP_SIZE)) {
++		/* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */
++		return RTW_RX_LLC_REMOVE;
++	} else {
++		/* Leave Ethernet header part of hdr and full payload */
++		return RTW_RX_LLC_KEEP;
++	}
++
++	/* TODO: VLAN tagged */
++}
++
++/* remove the wlanhdr and add the eth_hdr */
++sint wlanhdr_to_ethhdr(union recv_frame *precvframe, enum rtw_rx_llc_hdl llc_hdl)
++{
++	u8	*ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */
++	struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
++	sint rmv_len;
++	u16	eth_type, len;
++	sint ret = _SUCCESS;
++
++	if (pattrib->encrypt)
++		recvframe_pull_tail(precvframe, pattrib->icv_len);
++
++	rmv_len = pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + (llc_hdl ? SNAP_SIZE : 0);
++	len = precvframe->u.hdr.len - rmv_len;
++
++	ptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + (llc_hdl ? 2 : 0)));
++	if (!ptr) {
++		ret = _FAIL;
++		goto exiting;
++	}
++
++	_rtw_memcpy(ptr, pattrib->dst, ETH_ALEN);
++	_rtw_memcpy(ptr + ETH_ALEN, pattrib->src, ETH_ALEN);
++
++	if (!llc_hdl) {
++		len = htons(len);
++		_rtw_memcpy(ptr + 12, &len, 2);
++	}
++
++	rtw_rframe_set_os_pkt(precvframe);
++
++exiting:
++	return ret;
++}
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++#ifndef CONFIG_SDIO_RX_COPY
++#ifdef PLATFORM_LINUX
++static void recvframe_expand_pkt(
++	PADAPTER padapter,
++	union recv_frame *prframe)
++{
++	struct recv_frame_hdr *pfhdr;
++	_pkt *ppkt;
++	u8 shift_sz;
++	u32 alloc_sz;
++	u8 *ptr;
++
++
++	pfhdr = &prframe->u.hdr;
++
++	/*	6 is for IP header 8 bytes alignment in QoS packet case. */
++	if (pfhdr->attrib.qos)
++		shift_sz = 6;
++	else
++		shift_sz = 0;
++
++	/* for first fragment packet, need to allocate */
++	/* (1536 + RXDESC_SIZE + drvinfo_sz) to reassemble packet */
++	/*	8 is for skb->data 8 bytes alignment.
++	*	alloc_sz = _RND(1536 + RXDESC_SIZE + pfhdr->attrib.drvinfosize + shift_sz + 8, 128); */
++	alloc_sz = 1664; /* round (1536 + 24 + 32 + shift_sz + 8) to 128 bytes alignment */
++
++	/* 3 1. alloc new skb */
++	/* prepare extra space for 4 bytes alignment */
++	ppkt = rtw_skb_alloc(alloc_sz);
++
++	if (!ppkt)
++		return; /* no way to expand */
++
++	/* 3 2. Prepare new skb to replace & release old skb */
++	/* force ppkt->data at 8-byte alignment address */
++	skb_reserve(ppkt, 8 - ((SIZE_PTR)ppkt->data & 7));
++	/* force ip_hdr at 8-byte alignment address according to shift_sz */
++	skb_reserve(ppkt, shift_sz);
++
++	/* copy data to new pkt */
++	ptr = skb_put(ppkt, pfhdr->len);
++	if (ptr)
++		_rtw_memcpy(ptr, pfhdr->rx_data, pfhdr->len);
++
++	rtw_skb_free(pfhdr->pkt);
++
++	/* attach new pkt to recvframe */
++	pfhdr->pkt = ppkt;
++	pfhdr->rx_head = ppkt->head;
++	pfhdr->rx_data = ppkt->data;
++	pfhdr->rx_tail = skb_tail_pointer(ppkt);
++	pfhdr->rx_end = skb_end_pointer(ppkt);
++}
++#else /*!= PLATFORM_LINUX*/
++#warning "recvframe_expand_pkt not implement, defrag may crash system"
++#endif
++#endif /*#ifndef CONFIG_SDIO_RX_COPY*/
++#endif
++
++/* perform defrag */
++union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q);
++union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q)
++{
++	_list	*plist, *phead;
++	u8	*data, wlanhdr_offset;
++	u8	curfragnum;
++	struct recv_frame_hdr *pfhdr, *pnfhdr;
++	union recv_frame *prframe, *pnextrframe;
++	_queue	*pfree_recv_queue;
++
++
++	curfragnum = 0;
++	pfree_recv_queue = &adapter->recvpriv.free_recv_queue;
++
++	phead = get_list_head(defrag_q);
++	plist = get_next(phead);
++	prframe = LIST_CONTAINOR(plist, union recv_frame, u);
++	pfhdr = &prframe->u.hdr;
++	rtw_list_delete(&(prframe->u.list));
++
++	if (curfragnum != pfhdr->attrib.frag_num) {
++		/* the first fragment number must be 0 */
++		/* free the whole queue */
++		rtw_free_recvframe(prframe, pfree_recv_queue);
++		rtw_free_recvframe_queue(defrag_q, pfree_recv_queue);
++
++		return NULL;
++	}
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++#ifndef CONFIG_SDIO_RX_COPY
++	recvframe_expand_pkt(adapter, prframe);
++#endif
++#endif
++
++	curfragnum++;
++
++	plist = get_list_head(defrag_q);
++
++	plist = get_next(plist);
++
++	data = get_recvframe_data(prframe);
++
++	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
++		pnextrframe = LIST_CONTAINOR(plist, union recv_frame , u);
++		pnfhdr = &pnextrframe->u.hdr;
++
++
++		/* check the fragment sequence  (2nd ~n fragment frame) */
++
++		if (curfragnum != pnfhdr->attrib.frag_num) {
++			/* the fragment number must be increasing  (after decache) */
++			/* release the defrag_q & prframe */
++			rtw_free_recvframe(prframe, pfree_recv_queue);
++			rtw_free_recvframe_queue(defrag_q, pfree_recv_queue);
++			return NULL;
++		}
++
++		curfragnum++;
++
++		/* copy the 2nd~n fragment frame's payload to the first fragment */
++		/* get the 2nd~last fragment frame's payload */
++
++		wlanhdr_offset = pnfhdr->attrib.hdrlen + pnfhdr->attrib.iv_len;
++
++		recvframe_pull(pnextrframe, wlanhdr_offset);
++
++		/* append  to first fragment frame's tail (if privacy frame, pull the ICV) */
++		recvframe_pull_tail(prframe, pfhdr->attrib.icv_len);
++
++		/* memcpy */
++		_rtw_memcpy(pfhdr->rx_tail, pnfhdr->rx_data, pnfhdr->len);
++
++		recvframe_put(prframe, pnfhdr->len);
++
++		pfhdr->attrib.icv_len = pnfhdr->attrib.icv_len;
++		plist = get_next(plist);
++
++	};
++
++	/* free the defrag_q queue and return the prframe */
++	rtw_free_recvframe_queue(defrag_q, pfree_recv_queue);
++
++
++
++	return prframe;
++}
++
++/* check if need to defrag, if needed queue the frame to defrag_q */
++union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame)
++{
++	u8	ismfrag;
++	u8	fragnum;
++	u8	*psta_addr;
++	struct recv_frame_hdr *pfhdr;
++	struct sta_info *psta;
++	struct sta_priv *pstapriv;
++	_list *phead;
++	union recv_frame *prtnframe = NULL;
++	_queue *pfree_recv_queue, *pdefrag_q = NULL;
++
++
++	pstapriv = &padapter->stapriv;
++
++	pfhdr = &precv_frame->u.hdr;
++
++	pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
++
++	/* need to define struct of wlan header frame ctrl */
++	ismfrag = pfhdr->attrib.mfrag;
++	fragnum = pfhdr->attrib.frag_num;
++
++	psta_addr = pfhdr->attrib.ta;
++	psta = rtw_get_stainfo(pstapriv, psta_addr);
++	if (psta == NULL) {
++		u8 type = GetFrameType(pfhdr->rx_data);
++		if (type != WIFI_DATA_TYPE) {
++			psta = rtw_get_bcmc_stainfo(padapter);
++			if (psta)
++				pdefrag_q = &psta->sta_recvpriv.defrag_q;
++		} else
++			pdefrag_q = NULL;
++	} else
++		pdefrag_q = &psta->sta_recvpriv.defrag_q;
++
++	if ((ismfrag == 0) && (fragnum == 0)) {
++		prtnframe = precv_frame;/* isn't a fragment frame */
++	}
++
++	if (ismfrag == 1) {
++		/* 0~(n-1) fragment frame */
++		/* enqueue to defraf_g */
++		if (pdefrag_q != NULL) {
++			if (fragnum == 0) {
++				/* the first fragment */
++				if (_rtw_queue_empty(pdefrag_q) == _FALSE) {
++					/* free current defrag_q */
++					rtw_free_recvframe_queue(pdefrag_q, pfree_recv_queue);
++				}
++			}
++
++
++			/* Then enqueue the 0~(n-1) fragment into the defrag_q */
++
++			/* _rtw_spinlock(&pdefrag_q->lock); */
++			phead = get_list_head(pdefrag_q);
++			rtw_list_insert_tail(&pfhdr->list, phead);
++			/* _rtw_spinunlock(&pdefrag_q->lock); */
++
++
++			prtnframe = NULL;
++
++		} else {
++			/* can't find this ta's defrag_queue, so free this recv_frame */
++			rtw_free_recvframe(precv_frame, pfree_recv_queue);
++			prtnframe = NULL;
++		}
++
++	}
++
++	if ((ismfrag == 0) && (fragnum != 0)) {
++		/* the last fragment frame */
++		/* enqueue the last fragment */
++		if (pdefrag_q != NULL) {
++			/* _rtw_spinlock(&pdefrag_q->lock); */
++			phead = get_list_head(pdefrag_q);
++			rtw_list_insert_tail(&pfhdr->list, phead);
++			/* _rtw_spinunlock(&pdefrag_q->lock); */
++
++			/* call recvframe_defrag to defrag */
++			precv_frame = recvframe_defrag(padapter, pdefrag_q);
++			prtnframe = precv_frame;
++
++		} else {
++			/* can't find this ta's defrag_queue, so free this recv_frame */
++			rtw_free_recvframe(precv_frame, pfree_recv_queue);
++			prtnframe = NULL;
++		}
++
++	}
++
++
++	if ((prtnframe != NULL) && (prtnframe->u.hdr.attrib.privacy)) {
++		/* after defrag we must check tkip mic code */
++		if (recvframe_chkmic(padapter,  prtnframe) == _FAIL) {
++			rtw_free_recvframe(prtnframe, pfree_recv_queue);
++			prtnframe = NULL;
++		}
++	}
++
++
++	return prtnframe;
++
++}
++
++static int rtw_recv_indicatepkt_check(union recv_frame *rframe, u8 *ehdr_pos, u32 pkt_len)
++{
++	_adapter *adapter = rframe->u.hdr.adapter;
++	struct recv_priv *recvpriv = &adapter->recvpriv;
++	struct ethhdr *ehdr = (struct ethhdr *)ehdr_pos;
++#ifdef DBG_IP_R_MONITOR
++	int i;
++	struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib;
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++	struct mlme_priv	*pmlmepriv = &adapter->mlmepriv;
++	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
++#endif/*DBG_IP_R_MONITOR*/
++	int ret = _FAIL;
++
++#ifdef CONFIG_WAPI_SUPPORT
++	if (rtw_wapi_check_for_drop(adapter, rframe, ehdr_pos)) {
++		#ifdef DBG_RX_DROP_FRAME
++		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_wapi_check_for_drop\n"
++			, FUNC_ADPT_ARG(adapter));
++		#endif
++		goto exit;
++	}
++#endif
++
++	if (rframe->u.hdr.psta)
++		rtw_st_ctl_rx(rframe->u.hdr.psta, ehdr_pos);
++
++	if (ntohs(ehdr->h_proto) == 0x888e)
++		parsing_eapol_packet(adapter, ehdr_pos + ETH_HLEN, rframe->u.hdr.psta, 0);
++#ifdef DBG_ARP_DUMP
++	else if (ntohs(ehdr->h_proto) == ETH_P_ARP)
++		dump_arp_pkt(RTW_DBGDUMP, ehdr->h_dest, ehdr->h_source, ehdr_pos + ETH_HLEN, 0);
++#endif
++
++	if (recvpriv->sink_udpport > 0)
++		rtw_sink_rtp_seq_dbg(adapter, ehdr_pos);
++
++#ifdef DBG_UDP_PKT_LOSE_11AC
++	#define PAYLOAD_LEN_LOC_OF_IP_HDR 0x10 /*ethernet payload length location of ip header (DA + SA+eth_type+(version&hdr_len)) */
++
++	if (ntohs(ehdr->h_proto) == ETH_P_ARP) {
++		/* ARP Payload length will be 42bytes or 42+18(tailer)=60bytes*/
++		if (pkt_len != 42 && pkt_len != 60)
++			RTW_INFO("Error !!%s,ARP Payload length %u not correct\n" , __func__ , pkt_len);
++	} else if (ntohs(ehdr->h_proto) == ETH_P_IP) {
++		if (be16_to_cpu(*((u16 *)(ehdr_pos + PAYLOAD_LEN_LOC_OF_IP_HDR))) != (pkt_len) - ETH_HLEN) {
++			RTW_INFO("Error !!%s,Payload length not correct\n" , __func__);
++			RTW_INFO("%s, IP header describe Total length=%u\n" , __func__ , be16_to_cpu(*((u16 *)(ehdr_pos + PAYLOAD_LEN_LOC_OF_IP_HDR))));
++			RTW_INFO("%s, Pkt real length=%u\n" , __func__ , (pkt_len) - ETH_HLEN);
++		}
++	}
++#endif
++
++#ifdef DBG_IP_R_MONITOR
++	#define LEN_ARP_OP_HDR 7 /*ARP OERATION */
++	if (ntohs(ehdr->h_proto) == ETH_P_ARP) {
++
++		if(check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE){
++			if(ehdr_pos[ETHERNET_HEADER_SIZE+LEN_ARP_OP_HDR] == 2) {
++
++				RTW_INFO("%s,[DBG_ARP] Rx ARP RSP Packet;SeqNum = %d !\n",
++					__FUNCTION__, pattrib->seq_num);
++
++				dump_arp_pkt(RTW_DBGDUMP, ehdr->h_dest, ehdr->h_source, ehdr_pos + ETH_HLEN, 0);
++
++			}
++		}
++	}
++#endif/*DBG_IP_R_MONITOR*/
++
++#ifdef CONFIG_AUTO_AP_MODE
++	if (ntohs(ehdr->h_proto) == 0x8899)
++		rtw_auto_ap_rx_msg_dump(adapter, rframe, ehdr_pos);
++#endif
++
++	ret = _SUCCESS;
++
++#ifdef CONFIG_WAPI_SUPPORT
++exit:
++#endif
++	return ret;
++}
++
++#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
++static void recv_free_fwd_resource(_adapter *adapter, struct xmit_frame *fwd_frame, _list *b2u_list)
++{
++	struct xmit_priv *xmitpriv = &adapter->xmitpriv;
++
++	if (fwd_frame)
++		rtw_free_xmitframe(xmitpriv, fwd_frame);
++
++#if CONFIG_RTW_DATA_BMC_TO_UC
++	if (!rtw_is_list_empty(b2u_list)) {
++		struct xmit_frame *b2uframe;
++		_list *list;
++
++		list = get_next(b2u_list);
++		while (rtw_end_of_queue_search(b2u_list, list) == _FALSE) {
++			b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list);
++			list = get_next(list);
++			rtw_list_delete(&b2uframe->list);
++			rtw_free_xmitframe(xmitpriv, b2uframe);
++		}
++	}
++#endif
++}
++
++static void recv_fwd_pkt_hdl(_adapter *adapter, _pkt *pkt
++	, u8 act, struct xmit_frame *fwd_frame, _list *b2u_list)
++{
++	struct xmit_priv *xmitpriv = &adapter->xmitpriv;
++	_pkt *fwd_pkt = pkt;
++
++	if (act & RTW_RX_MSDU_ACT_INDICATE) {
++		fwd_pkt = rtw_os_pkt_copy(pkt);
++		if (!fwd_pkt) {
++			#ifdef DBG_TX_DROP_FRAME
++			RTW_INFO("DBG_TX_DROP_FRAME %s rtw_os_pkt_copy fail\n", __func__);
++			#endif
++			recv_free_fwd_resource(adapter, fwd_frame, b2u_list);
++			goto exit;
++		}
++	}
++
++#if CONFIG_RTW_DATA_BMC_TO_UC
++	if (!rtw_is_list_empty(b2u_list)) {
++		_list *list = get_next(b2u_list);
++		struct xmit_frame *b2uframe;
++
++		while (rtw_end_of_queue_search(b2u_list, list) == _FALSE) {
++			b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list);
++			list = get_next(list);
++			rtw_list_delete(&b2uframe->list);
++
++			if (!fwd_frame && rtw_is_list_empty(b2u_list)) /* the last fwd_pkt */
++				b2uframe->pkt = fwd_pkt;
++			else
++				b2uframe->pkt = rtw_os_pkt_copy(fwd_pkt);
++			if (!b2uframe->pkt) {
++				rtw_free_xmitframe(xmitpriv, b2uframe);
++				continue;
++			}
++
++			rtw_xmit_posthandle(adapter, b2uframe, b2uframe->pkt);
++		}
++	}
++#endif
++
++	if (fwd_frame) {
++		fwd_frame->pkt = fwd_pkt;
++		if (rtw_xmit_posthandle(adapter, fwd_frame, fwd_pkt) < 0) {
++			#ifdef DBG_TX_DROP_FRAME
++			RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit_posthandle fail\n", __func__);
++			#endif
++			xmitpriv->tx_drop++;
++		}
++	}
++
++exit:
++	return;
++}
++#endif /* defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH) */
++
++int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe)
++{
++	struct rx_pkt_attrib *rattrib = &prframe->u.hdr.attrib;
++	int	a_len, padding_len;
++	u16	nSubframe_Length;
++	u8	nr_subframes, i;
++	u8	*pdata;
++	_pkt *sub_pkt, *subframes[MAX_SUBFRAME_COUNT];
++	struct recv_priv *precvpriv = &padapter->recvpriv;
++	_queue *pfree_recv_queue = &(precvpriv->free_recv_queue);
++	const u8 *da, *sa;
++	int act;
++#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
++	struct xmit_frame *fwd_frame;
++	_list b2u_list;
++#endif
++	enum rtw_rx_llc_hdl llc_hdl;
++	u8 mctrl_len = 0;
++	int	ret = _SUCCESS;
++
++	nr_subframes = 0;
++
++	recvframe_pull(prframe, rattrib->hdrlen);
++
++	if (rattrib->iv_len > 0)
++		recvframe_pull(prframe, rattrib->iv_len);
++	if (rattrib->encrypt)
++		recvframe_pull_tail(prframe, rattrib->icv_len);
++
++	a_len = prframe->u.hdr.len;
++	pdata = prframe->u.hdr.rx_data;
++
++	while (a_len > ETH_HLEN) {
++		/* Offset 12 denote 2 mac address */
++		nSubframe_Length = RTW_GET_BE16(pdata + 12);
++		if (a_len < (ETHERNET_HEADER_SIZE + nSubframe_Length)) {
++			RTW_INFO("nRemain_Length is %d and nSubframe_Length is : %d\n", a_len, nSubframe_Length);
++			break;
++		}
++
++		act = RTW_RX_MSDU_ACT_INDICATE;
++		#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
++		fwd_frame = NULL;
++		#endif
++
++		#ifdef CONFIG_RTW_MESH
++		if (MLME_IS_MESH(padapter)) {
++			u8 *mda = pdata, *msa = pdata + ETH_ALEN;
++			struct rtw_ieee80211s_hdr *mctrl = (struct rtw_ieee80211s_hdr *)(pdata + ETH_HLEN);
++			int v_ret;
++
++			v_ret = rtw_mesh_rx_data_validate_mctrl(padapter, prframe
++				, mctrl, mda, msa, &mctrl_len, &da, &sa);
++			if (v_ret != _SUCCESS)
++				goto move_to_next;
++
++			llc_hdl = rtw_recv_llc_parse(pdata + ETH_HLEN + mctrl_len, nSubframe_Length - mctrl_len);
++			act = rtw_mesh_rx_msdu_act_check(prframe
++				, mda, msa, da, sa, mctrl
++				, pdata + ETH_HLEN + mctrl_len, llc_hdl
++				, &fwd_frame, &b2u_list);
++		} else
++		#endif
++		{
++			da = pdata;
++			sa = pdata + ETH_ALEN;
++			llc_hdl = rtw_recv_llc_parse(pdata + ETH_HLEN, nSubframe_Length);
++			#ifdef CONFIG_AP_MODE
++			if (MLME_IS_AP(padapter)) {
++				act = rtw_ap_rx_msdu_act_check(prframe, da, sa
++					, pdata + ETH_HLEN, llc_hdl, &fwd_frame, &b2u_list);
++			}
++			#endif
++		}
++
++		#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
++		if (!act)
++			goto move_to_next;
++		#endif
++
++		rtw_led_rx_control(padapter, da);
++
++		sub_pkt = rtw_os_alloc_msdu_pkt(prframe, da, sa
++			, pdata + ETH_HLEN + mctrl_len, nSubframe_Length - mctrl_len, llc_hdl);
++		if (sub_pkt == NULL) {
++			if (act & RTW_RX_MSDU_ACT_INDICATE) {
++				#ifdef DBG_RX_DROP_FRAME
++				RTW_INFO("DBG_RX_DROP_FRAME %s rtw_os_alloc_msdu_pkt fail\n", __func__);
++				#endif
++			}
++			#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
++			if (act & RTW_RX_MSDU_ACT_FORWARD) {
++				#ifdef DBG_TX_DROP_FRAME
++				RTW_INFO("DBG_TX_DROP_FRAME %s rtw_os_alloc_msdu_pkt fail\n", __func__);
++				#endif
++				recv_free_fwd_resource(padapter, fwd_frame, &b2u_list);
++			}
++			#endif
++			break;
++		}
++
++		#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
++		if (act & RTW_RX_MSDU_ACT_FORWARD) {
++			recv_fwd_pkt_hdl(padapter, sub_pkt, act, fwd_frame, &b2u_list);
++			if (!(act & RTW_RX_MSDU_ACT_INDICATE))
++				goto move_to_next;
++		}
++		#endif
++
++		if (rtw_recv_indicatepkt_check(prframe, rtw_os_pkt_data(sub_pkt), rtw_os_pkt_len(sub_pkt)) == _SUCCESS)
++			subframes[nr_subframes++] = sub_pkt;
++		else
++			rtw_os_pkt_free(sub_pkt);
++
++#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
++move_to_next:
++#endif
++		/* move the data point to data content */
++		pdata += ETH_HLEN;
++		a_len -= ETH_HLEN;
++
++		if (nr_subframes >= MAX_SUBFRAME_COUNT) {
++			RTW_WARN("ParseSubframe(): Too many Subframes! Packets dropped!\n");
++			break;
++		}
++
++		pdata += nSubframe_Length;
++		a_len -= nSubframe_Length;
++		if (a_len != 0) {
++			padding_len = 4 - ((nSubframe_Length + ETH_HLEN) & (4 - 1));
++			if (padding_len == 4)
++				padding_len = 0;
++
++			if (a_len < padding_len) {
++				RTW_INFO("ParseSubframe(): a_len < padding_len !\n");
++				break;
++			}
++			pdata += padding_len;
++			a_len -= padding_len;
++		}
++	}
++
++	for (i = 0; i < nr_subframes; i++) {
++		sub_pkt = subframes[i];
++
++		/* Indicat the packets to upper layer */
++		if (sub_pkt)
++			rtw_os_recv_indicate_pkt(padapter, sub_pkt, prframe);
++	}
++
++	prframe->u.hdr.len = 0;
++	rtw_free_recvframe(prframe, pfree_recv_queue);/* free this recv_frame */
++
++	return ret;
++}
++
++static int recv_process_mpdu(_adapter *padapter, union recv_frame *prframe)
++{
++	_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
++	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
++	int ret;
++
++	if (pattrib->amsdu) {
++		ret = amsdu_to_msdu(padapter, prframe);
++		if (ret != _SUCCESS) {
++			#ifdef DBG_RX_DROP_FRAME
++			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" amsdu_to_msdu fail\n"
++				, FUNC_ADPT_ARG(padapter));
++			#endif
++			rtw_free_recvframe(prframe, pfree_recv_queue);
++			goto exit;
++		}
++	} else {
++		u8 *msdu = get_recvframe_data(prframe)
++			+ pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib);
++		u16 msdu_len = prframe->u.hdr.len
++			- pattrib->hdrlen - pattrib->iv_len - RATTRIB_GET_MCTRL_LEN(pattrib)
++			- (pattrib->encrypt ? pattrib->icv_len : 0);
++		enum rtw_rx_llc_hdl llc_hdl = rtw_recv_llc_parse(msdu, msdu_len);
++		int act = RTW_RX_MSDU_ACT_INDICATE;
++
++		#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
++		struct xmit_frame *fwd_frame = NULL;
++		_list b2u_list;
++
++		#ifdef CONFIG_RTW_MESH
++		if (MLME_IS_MESH(padapter)) {
++			if (pattrib->mesh_ctrl_present)
++				act = rtw_mesh_rx_msdu_act_check(prframe
++					, pattrib->mda, pattrib->msa
++					, pattrib->dst, pattrib->src
++					, (struct rtw_ieee80211s_hdr *)(msdu - RATTRIB_GET_MCTRL_LEN(pattrib))
++					, msdu, llc_hdl
++					, &fwd_frame, &b2u_list);
++		} else
++		#endif
++		if (MLME_IS_AP(padapter))
++			act = rtw_ap_rx_msdu_act_check(prframe, pattrib->dst, pattrib->src
++					, msdu, llc_hdl, &fwd_frame, &b2u_list);
++		#endif
++
++		#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
++		if (!act) {
++			rtw_free_recvframe(prframe, pfree_recv_queue);
++			ret = _FAIL;
++			goto exit;
++		}
++		#endif
++
++		rtw_led_rx_control(padapter, pattrib->dst);
++
++		ret = wlanhdr_to_ethhdr(prframe, llc_hdl);
++		if (ret != _SUCCESS) {
++			if (act & RTW_RX_MSDU_ACT_INDICATE) {
++				#ifdef DBG_RX_DROP_FRAME
++				RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" wlanhdr_to_ethhdr: drop pkt\n"
++					, FUNC_ADPT_ARG(padapter));
++				#endif
++			}
++			#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
++			if (act & RTW_RX_MSDU_ACT_FORWARD) {
++				#ifdef DBG_TX_DROP_FRAME
++				RTW_INFO("DBG_TX_DROP_FRAME %s wlanhdr_to_ethhdr fail\n", __func__);
++				#endif
++				recv_free_fwd_resource(padapter, fwd_frame, &b2u_list);
++			}
++			#endif
++			rtw_free_recvframe(prframe, pfree_recv_queue);
++			goto exit;
++		}
++
++		#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
++		if (act & RTW_RX_MSDU_ACT_FORWARD) {
++			recv_fwd_pkt_hdl(padapter, prframe->u.hdr.pkt, act, fwd_frame, &b2u_list);
++			if (!(act & RTW_RX_MSDU_ACT_INDICATE)) {
++				prframe->u.hdr.pkt = NULL;
++				rtw_free_recvframe(prframe, pfree_recv_queue);
++				goto exit;
++			}
++		}
++		#endif
++
++		if (!RTW_CANNOT_RUN(padapter)) {
++			ret = rtw_recv_indicatepkt_check(prframe
++				, get_recvframe_data(prframe), get_recvframe_len(prframe));
++			if (ret != _SUCCESS) {
++				rtw_free_recvframe(prframe, pfree_recv_queue);
++				goto exit;
++			}
++
++			/* indicate this recv_frame */
++			ret = rtw_recv_indicatepkt(padapter, prframe);
++			if (ret != _SUCCESS) {
++				#ifdef DBG_RX_DROP_FRAME
++				RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_recv_indicatepkt fail!\n"
++					, FUNC_ADPT_ARG(padapter));
++				#endif
++				goto exit;
++			}
++		} else {
++			#ifdef DBG_RX_DROP_FRAME
++			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DS:%u SR:%u\n"
++				, FUNC_ADPT_ARG(padapter)
++				, rtw_is_drv_stopped(padapter)
++				, rtw_is_surprise_removed(padapter));
++			#endif
++			ret = _SUCCESS; /* don't count as packet drop */
++			rtw_free_recvframe(prframe, pfree_recv_queue);
++		}
++	}
++
++exit:
++	return ret;
++}
++
++#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
++static int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num)
++{
++	PADAPTER padapter = preorder_ctrl->padapter;
++	struct recv_priv  *precvpriv = &padapter->recvpriv;
++	u8	wsize = preorder_ctrl->wsize_b;
++	u16	wend;
++
++	/* Rx Reorder initialize condition. */
++	if (preorder_ctrl->indicate_seq == 0xFFFF) {
++		preorder_ctrl->indicate_seq = seq_num;
++		#ifdef DBG_RX_SEQ
++		RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_INIT indicate_seq:%d, seq_num:%d\n"
++			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);
++		#endif
++	}
++	wend = (preorder_ctrl->indicate_seq + wsize - 1) & 0xFFF; /* % 4096; */
++
++	/* Drop out the packet which SeqNum is smaller than WinStart */
++	if (SN_LESS(seq_num, preorder_ctrl->indicate_seq)) {
++		#ifdef DBG_RX_DROP_FRAME
++		RTW_INFO(FUNC_ADPT_FMT" tid:%u indicate_seq:%d > seq_num:%d\n"
++			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);
++		#endif
++		return _FALSE;
++	}
++
++	/*
++	* Sliding window manipulation. Conditions includes:
++	* 1. Incoming SeqNum is equal to WinStart =>Window shift 1
++	* 2. Incoming SeqNum is larger than the WinEnd => Window shift N
++	*/
++	if (SN_EQUAL(seq_num, preorder_ctrl->indicate_seq)) {
++		preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF;
++		#ifdef DBG_RX_SEQ
++		RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_EQUAL indicate_seq:%d, seq_num:%d\n"
++			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);
++		#endif
++
++	} else if (SN_LESS(wend, seq_num)) {
++		/* boundary situation, when seq_num cross 0xFFF */
++		if (seq_num >= (wsize - 1))
++			preorder_ctrl->indicate_seq = seq_num + 1 - wsize;
++		else
++			preorder_ctrl->indicate_seq = 0xFFF - (wsize - (seq_num + 1)) + 1;
++
++		precvpriv->dbg_rx_ampdu_window_shift_cnt++;
++		#ifdef DBG_RX_SEQ
++		RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_LESS(wend, seq_num) indicate_seq:%d, seq_num:%d\n"
++			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);
++		#endif
++	}
++
++	return _TRUE;
++}
++
++static int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe)
++{
++	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
++	_queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
++	_list	*phead, *plist;
++	union recv_frame *pnextrframe;
++	struct rx_pkt_attrib *pnextattrib;
++
++	/* DbgPrint("+enqueue_reorder_recvframe()\n"); */
++
++	/* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */
++	/* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */
++
++
++	phead = get_list_head(ppending_recvframe_queue);
++	plist = get_next(phead);
++
++	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
++		pnextrframe = LIST_CONTAINOR(plist, union recv_frame, u);
++		pnextattrib = &pnextrframe->u.hdr.attrib;
++
++		if (SN_LESS(pnextattrib->seq_num, pattrib->seq_num))
++			plist = get_next(plist);
++		else if (SN_EQUAL(pnextattrib->seq_num, pattrib->seq_num)) {
++			/* Duplicate entry is found!! Do not insert current entry. */
++
++			/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
++
++			return _FALSE;
++		} else
++			break;
++
++		/* DbgPrint("enqueue_reorder_recvframe():while\n"); */
++
++	}
++
++
++	/* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */
++	/* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */
++
++	rtw_list_delete(&(prframe->u.hdr.list));
++
++	rtw_list_insert_tail(&(prframe->u.hdr.list), plist);
++
++	/* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */
++	/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
++
++
++	return _TRUE;
++
++}
++
++static void recv_indicatepkts_pkt_loss_cnt(_adapter *padapter, u64 prev_seq, u64 current_seq)
++{
++	struct recv_priv *precvpriv = &padapter->recvpriv;
++
++	if (current_seq < prev_seq) {
++		precvpriv->dbg_rx_ampdu_loss_count += (4096 + current_seq - prev_seq);
++		precvpriv->rx_drop += (4096 + current_seq - prev_seq);
++	} else {
++		precvpriv->dbg_rx_ampdu_loss_count += (current_seq - prev_seq);
++		precvpriv->rx_drop += (current_seq - prev_seq);
++	}
++}
++
++static int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced)
++{
++	/* _irqL irql; */
++	_list	*phead, *plist;
++	union recv_frame *prframe;
++	struct rx_pkt_attrib *pattrib;
++	/* u8 index = 0; */
++	int bPktInBuf = _FALSE;
++	struct recv_priv *precvpriv = &padapter->recvpriv;
++	_queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
++
++	DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_in_oder);
++
++	/* DbgPrint("+recv_indicatepkts_in_order\n"); */
++
++	/* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */
++	/* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */
++
++	phead =	get_list_head(ppending_recvframe_queue);
++	plist = get_next(phead);
++
++#if 0
++	/* Check if there is any other indication thread running. */
++	if (pTS->RxIndicateState == RXTS_INDICATE_PROCESSING)
++		return;
++#endif
++
++	/* Handling some condition for forced indicate case. */
++	if (bforced == _TRUE) {
++		precvpriv->dbg_rx_ampdu_forced_indicate_count++;
++		if (rtw_is_list_empty(phead)) {
++			/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
++			/* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */
++			return _TRUE;
++		}
++
++		prframe = LIST_CONTAINOR(plist, union recv_frame, u);
++		pattrib = &prframe->u.hdr.attrib;
++
++		#ifdef DBG_RX_SEQ
++		RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u FORCE indicate_seq:%d, seq_num:%d\n"
++			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pattrib->seq_num);
++		#endif
++		recv_indicatepkts_pkt_loss_cnt(padapter, preorder_ctrl->indicate_seq, pattrib->seq_num);
++		preorder_ctrl->indicate_seq = pattrib->seq_num;
++	}
++
++	/* Prepare indication list and indication. */
++	/* Check if there is any packet need indicate. */
++	while (!rtw_is_list_empty(phead)) {
++
++		prframe = LIST_CONTAINOR(plist, union recv_frame, u);
++		pattrib = &prframe->u.hdr.attrib;
++
++		if (!SN_LESS(preorder_ctrl->indicate_seq, pattrib->seq_num)) {
++
++#if 0
++			/* This protect buffer from overflow. */
++			if (index >= REORDER_WIN_SIZE) {
++				RT_ASSERT(FALSE, ("IndicateRxReorderList(): Buffer overflow!!\n"));
++				bPktInBuf = TRUE;
++				break;
++			}
++#endif
++
++			plist = get_next(plist);
++			rtw_list_delete(&(prframe->u.hdr.list));
++
++			if (SN_EQUAL(preorder_ctrl->indicate_seq, pattrib->seq_num)) {
++				preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF;
++				#ifdef DBG_RX_SEQ
++				RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_EQUAL indicate_seq:%d, seq_num:%d\n"
++					, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pattrib->seq_num);
++				#endif
++			}
++
++#if 0
++			index++;
++			if (index == 1) {
++				/* Cancel previous pending timer. */
++				/* PlatformCancelTimer(Adapter, &pTS->RxPktPendingTimer); */
++				if (bforced != _TRUE) {
++					/* RTW_INFO("_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);\n"); */
++					_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
++				}
++			}
++#endif
++
++			/* Set this as a lock to make sure that only one thread is indicating packet. */
++			/* pTS->RxIndicateState = RXTS_INDICATE_PROCESSING; */
++
++			/* Indicate packets */
++			/* RT_ASSERT((index<=REORDER_WIN_SIZE), ("RxReorderIndicatePacket(): Rx Reorder buffer full!!\n")); */
++
++
++			/* indicate this recv_frame */
++			/* DbgPrint("recv_indicatepkts_in_order, indicate_seq=%d, seq_num=%d\n", precvpriv->indicate_seq, pattrib->seq_num); */
++			if (recv_process_mpdu(padapter, prframe) != _SUCCESS)
++				precvpriv->dbg_rx_drop_count++;
++
++			/* Update local variables. */
++			bPktInBuf = _FALSE;
++
++		} else {
++			bPktInBuf = _TRUE;
++			break;
++		}
++
++		/* DbgPrint("recv_indicatepkts_in_order():while\n"); */
++
++	}
++
++	/* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */
++	/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
++
++#if 0
++	/* Release the indication lock and set to new indication step. */
++	if (bPktInBuf) {
++		/*  Set new pending timer. */
++		/* pTS->RxIndicateState = RXTS_INDICATE_REORDER; */
++		/* PlatformSetTimer(Adapter, &pTS->RxPktPendingTimer, pHTInfo->RxReorderPendingTime); */
++
++		_set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME);
++	} else {
++		/* pTS->RxIndicateState = RXTS_INDICATE_IDLE; */
++	}
++#endif
++	/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
++
++	/* return _TRUE; */
++	return bPktInBuf;
++
++}
++
++static int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe)
++{
++	_irqL irql;
++	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
++	struct recv_reorder_ctrl *preorder_ctrl = prframe->u.hdr.preorder_ctrl;
++	_queue *ppending_recvframe_queue = preorder_ctrl ? &preorder_ctrl->pending_recvframe_queue : NULL;
++	struct recv_priv  *precvpriv = &padapter->recvpriv;
++
++	if (!pattrib->qos || !preorder_ctrl || preorder_ctrl->enable == _FALSE)
++		goto _success_exit;
++
++
++	DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_reoder);
++
++	_enter_critical_bh(&ppending_recvframe_queue->lock, &irql);
++
++
++	if(rtw_test_and_clear_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack))
++		preorder_ctrl->indicate_seq = 0xFFFF;
++	#ifdef DBG_RX_SEQ
++	RTW_INFO("DBG_RX_SEQ %s:preorder_ctrl->rec_abba_rsp_ack = %u,indicate_seq = %d\n"
++		, __func__
++		, preorder_ctrl->rec_abba_rsp_ack
++		, preorder_ctrl->indicate_seq);
++	#endif
++
++	/* s2. check if winstart_b(indicate_seq) needs to been updated */
++	if (!check_indicate_seq(preorder_ctrl, pattrib->seq_num)) {
++		precvpriv->dbg_rx_ampdu_drop_count++;
++		/* pHTInfo->RxReorderDropCounter++; */
++		/* ReturnRFDList(Adapter, pRfd); */
++		/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
++		/* return _FAIL; */
++
++		#ifdef DBG_RX_DROP_FRAME
++		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" check_indicate_seq fail\n"
++			, FUNC_ADPT_ARG(padapter));
++		#endif
++#if 0
++		rtw_recv_indicatepkt(padapter, prframe);
++
++		_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
++
++		goto _success_exit;
++#else
++		goto _err_exit;
++#endif
++	}
++
++
++	/* s3. Insert all packet into Reorder Queue to maintain its ordering. */
++	if (!enqueue_reorder_recvframe(preorder_ctrl, prframe)) {
++		/* DbgPrint("recv_indicatepkt_reorder, enqueue_reorder_recvframe fail!\n"); */
++		/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
++		/* return _FAIL; */
++		#ifdef DBG_RX_DROP_FRAME
++		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" enqueue_reorder_recvframe fail\n"
++			, FUNC_ADPT_ARG(padapter));
++		#endif
++		goto _err_exit;
++	}
++
++
++	/* s4. */
++	/* Indication process. */
++	/* After Packet dropping and Sliding Window shifting as above, we can now just indicate the packets */
++	/* with the SeqNum smaller than latest WinStart and buffer other packets. */
++	/*  */
++	/* For Rx Reorder condition: */
++	/* 1. All packets with SeqNum smaller than WinStart => Indicate */
++	/* 2. All packets with SeqNum larger than or equal to WinStart => Buffer it. */
++	/*  */
++
++	/* recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE); */
++	if (recv_indicatepkts_in_order(padapter, preorder_ctrl, _FALSE) == _TRUE) {
++		if (!preorder_ctrl->bReorderWaiting) {
++			preorder_ctrl->bReorderWaiting = _TRUE;
++			_set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME);
++		}
++		_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
++	} else {
++		preorder_ctrl->bReorderWaiting = _FALSE;
++		_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
++		_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
++	}
++
++	return RTW_RX_HANDLED;
++
++_success_exit:
++
++	return _SUCCESS;
++
++_err_exit:
++
++	_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
++
++	return _FAIL;
++}
++
++
++void rtw_reordering_ctrl_timeout_handler(void *pcontext)
++{
++	_irqL irql;
++	struct recv_reorder_ctrl *preorder_ctrl = (struct recv_reorder_ctrl *)pcontext;
++	_adapter *padapter = NULL;
++	_queue *ppending_recvframe_queue = NULL;
++
++
++	if (preorder_ctrl == NULL)
++		return;
++
++	padapter = preorder_ctrl->padapter;
++	if (RTW_CANNOT_RUN(padapter))
++		return;
++
++	ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
++
++	/* RTW_INFO("+rtw_reordering_ctrl_timeout_handler()=>\n"); */
++
++	_enter_critical_bh(&ppending_recvframe_queue->lock, &irql);
++
++	preorder_ctrl->bReorderWaiting = _FALSE;
++
++	if (recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE) == _TRUE)
++		_set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME);
++
++	_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
++
++}
++#endif /* defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) */
++
++static void recv_set_iseq_before_mpdu_process(union recv_frame *rframe, u16 seq_num, const char *caller)
++{
++#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
++	struct recv_reorder_ctrl *reorder_ctrl = rframe->u.hdr.preorder_ctrl;
++
++	if (reorder_ctrl) {
++		reorder_ctrl->indicate_seq = seq_num;
++		#ifdef DBG_RX_SEQ
++		RTW_INFO("DBG_RX_SEQ %s("ADPT_FMT")-B tid:%u indicate_seq:%d, seq_num:%d\n"
++			, caller, ADPT_ARG(reorder_ctrl->padapter)
++			, reorder_ctrl->tid, reorder_ctrl->indicate_seq, seq_num);
++		#endif
++	}
++#endif
++}
++
++static void recv_set_iseq_after_mpdu_process(union recv_frame *rframe, u16 seq_num, const char *caller)
++{
++#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
++	struct recv_reorder_ctrl *reorder_ctrl = rframe->u.hdr.preorder_ctrl;
++
++	if (reorder_ctrl) {
++		reorder_ctrl->indicate_seq = (reorder_ctrl->indicate_seq + 1) % 4096;
++		#ifdef DBG_RX_SEQ
++		RTW_INFO("DBG_RX_SEQ %s("ADPT_FMT")-A tid:%u indicate_seq:%d, seq_num:%d\n"
++			, caller, ADPT_ARG(reorder_ctrl->padapter)
++			, reorder_ctrl->tid, reorder_ctrl->indicate_seq, seq_num);
++		#endif
++	}
++#endif
++}
++
++#ifdef CONFIG_MP_INCLUDED
++int validate_mp_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
++{
++	int ret = _SUCCESS;
++	u8 *ptr = precv_frame->u.hdr.rx_data;
++	u8 type, subtype;
++	struct mp_priv *pmppriv = &adapter->mppriv;
++	struct mp_tx		*pmptx;
++	unsigned char	*sa , *da, *bs;
++	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
++	u32 i = 0;
++	u8 rtk_prefix[]={0x52, 0x65, 0x61, 0x6C, 0x4C, 0x6F, 0x76, 0x65, 0x54, 0x65, 0x6B};
++	u8 *prx_data;
++	pmptx = &pmppriv->tx;
++
++
++	if (pmppriv->mplink_brx == _FALSE) {
++
++		u8 bDumpRxPkt = 0;
++		type =  GetFrameType(ptr);
++		subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2)	 */
++
++		RTW_DBG("hdr len = %d iv_len=%d \n", pattrib->hdrlen , pattrib->iv_len);
++		prx_data = ptr + pattrib->hdrlen + pattrib->iv_len;
++
++		for (i = 0; i < precv_frame->u.hdr.len; i++) {
++			if (precv_frame->u.hdr.len < (11 + i))
++				break;
++
++			if (_rtw_memcmp(prx_data + i, (void *)&rtk_prefix, 11) == _FALSE) {
++				bDumpRxPkt = 0;
++				RTW_DBG("prx_data = %02X != rtk_prefix[%d] = %02X \n", *(prx_data + i), i , rtk_prefix[i]);
++				} else {
++				bDumpRxPkt = 1;
++				RTW_DBG("prx_data = %02X = rtk_prefix[%d] = %02X \n", *(prx_data + i), i , rtk_prefix[i]);
++				break;
++				}
++		}
++
++		if (bDumpRxPkt == 1) { /* dump all rx packets */
++			int i;
++			RTW_INFO("############ type:0x%02x subtype:0x%02x #################\n", type, subtype);
++
++			for (i = 0; i < precv_frame->u.hdr.len; i = i + 8)
++				RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr + i),
++					*(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7));
++				RTW_INFO("#############################\n");
++				_rtw_memset(pmppriv->mplink_buf, '\0' , sizeof(pmppriv->mplink_buf));
++				_rtw_memcpy(pmppriv->mplink_buf, ptr, precv_frame->u.hdr.len);
++				pmppriv->mplink_rx_len = precv_frame->u.hdr.len;
++				pmppriv->mplink_brx =_TRUE;
++		}
++	}
++	if (pmppriv->bloopback) {
++		if (_rtw_memcmp(ptr + 24, pmptx->buf + 24, precv_frame->u.hdr.len - 24) == _FALSE) {
++			RTW_INFO("Compare payload content Fail !!!\n");
++			ret = _FAIL;
++		}
++	}
++ 	if (pmppriv->bSetRxBssid == _TRUE) {
++
++		sa = get_addr2_ptr(ptr);
++		da = GetAddr1Ptr(ptr);
++		bs = GetAddr3Ptr(ptr);
++		type =	GetFrameType(ptr);
++		subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2)  */
++
++		if (_rtw_memcmp(bs, adapter->mppriv.network_macaddr, ETH_ALEN) == _FALSE)
++			ret = _FAIL;
++
++		RTW_DBG("############ type:0x%02x subtype:0x%02x #################\n", type, subtype);
++		RTW_DBG("A2 sa %02X:%02X:%02X:%02X:%02X:%02X \n", *(sa) , *(sa + 1), *(sa+ 2), *(sa + 3), *(sa + 4), *(sa + 5));
++		RTW_DBG("A1 da %02X:%02X:%02X:%02X:%02X:%02X \n", *(da) , *(da + 1), *(da+ 2), *(da + 3), *(da + 4), *(da + 5));
++		RTW_DBG("A3 bs %02X:%02X:%02X:%02X:%02X:%02X \n --------------------------\n", *(bs) , *(bs + 1), *(bs+ 2), *(bs + 3), *(bs + 4), *(bs + 5));
++	}
++
++	if (!adapter->mppriv.bmac_filter)
++		return ret;
++
++	if (_rtw_memcmp(get_addr2_ptr(ptr), adapter->mppriv.mac_filter, ETH_ALEN) == _FALSE)
++		ret = _FAIL;
++
++	return ret;
++}
++
++static sint MPwlanhdr_to_ethhdr(union recv_frame *precvframe)
++{
++	sint	rmv_len;
++	u16 len;
++	u8 mcastheadermac[] = {0x01, 0x00, 0x5e};
++	sint ret = _SUCCESS;
++	_adapter			*adapter = precvframe->u.hdr.adapter;
++
++	u8	*ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */
++	struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
++	enum rtw_rx_llc_hdl llc_hdl;
++
++
++	if (pattrib->encrypt)
++		recvframe_pull_tail(precvframe, pattrib->icv_len);
++
++	llc_hdl = rtw_recv_llc_parse(ptr + pattrib->hdrlen + pattrib->iv_len
++				, precvframe->u.hdr.len - pattrib->hdrlen - pattrib->iv_len);
++
++	rmv_len = pattrib->hdrlen + pattrib->iv_len + (llc_hdl ? SNAP_SIZE : 0);
++	len = precvframe->u.hdr.len - rmv_len;
++
++	ptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + (llc_hdl ? 2 : 0)));
++
++	_rtw_memcpy(ptr, pattrib->dst, ETH_ALEN);
++	_rtw_memcpy(ptr + ETH_ALEN, pattrib->src, ETH_ALEN);
++
++	if (!llc_hdl) {
++		len = htons(len);
++		_rtw_memcpy(ptr + 12, &len, 2);
++	}
++
++
++	len = htons(pattrib->seq_num);
++	/* RTW_INFO("wlan seq = %d ,seq_num =%x\n",len,pattrib->seq_num); */
++	_rtw_memcpy(ptr + 12, &len, 2);
++	if (adapter->mppriv.bRTWSmbCfg == _TRUE) {
++		/* if(_rtw_memcmp(mcastheadermac, pattrib->dst, 3) == _TRUE) */ /* SimpleConfig Dest. */
++		/*			_rtw_memcpy(ptr+ETH_ALEN, pattrib->bssid, ETH_ALEN); */
++
++		if (_rtw_memcmp(mcastheadermac, pattrib->bssid, 3) == _TRUE) /* SimpleConfig Dest. */
++			_rtw_memcpy(ptr, pattrib->bssid, ETH_ALEN);
++
++	}
++
++
++	return ret;
++
++}
++
++
++int mp_recv_frame(_adapter *padapter, union recv_frame *rframe)
++{
++	int ret = _SUCCESS;
++	struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib;
++	_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
++#ifdef CONFIG_MP_INCLUDED
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct mp_priv *pmppriv = &padapter->mppriv;
++#endif /* CONFIG_MP_INCLUDED */
++	u8 type;
++	u8 *ptr = rframe->u.hdr.rx_data;
++	u8 *psa, *pda, *pbssid;
++	struct sta_info *psta = NULL;
++	DBG_COUNTER(padapter->rx_logs.core_rx_pre);
++
++	if ((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) { /* &&(padapter->mppriv.check_mp_pkt == 0)) */
++		if (pattrib->crc_err == 1)
++			padapter->mppriv.rx_crcerrpktcount++;
++		else {
++			if (_SUCCESS == validate_mp_recv_frame(padapter, rframe))
++				padapter->mppriv.rx_pktcount++;
++			else
++				padapter->mppriv.rx_pktcount_filter_out++;
++		}
++
++		if (pmppriv->rx_bindicatePkt == _FALSE) {
++			ret = _FAIL;
++			rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
++			goto exit;
++		} else {
++			type =	GetFrameType(ptr);
++			pattrib->to_fr_ds = get_tofr_ds(ptr);
++			pattrib->frag_num = GetFragNum(ptr);
++			pattrib->seq_num = GetSequence(ptr);
++			pattrib->pw_save = GetPwrMgt(ptr);
++			pattrib->mfrag = GetMFrag(ptr);
++			pattrib->mdata = GetMData(ptr);
++			pattrib->privacy = GetPrivacy(ptr);
++			pattrib->order = GetOrder(ptr);
++
++			if (type == WIFI_DATA_TYPE) {
++				pda = get_da(ptr);
++				psa = get_sa(ptr);
++				pbssid = get_hdr_bssid(ptr);
++
++				_rtw_memcpy(pattrib->dst, pda, ETH_ALEN);
++				_rtw_memcpy(pattrib->src, psa, ETH_ALEN);
++				_rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN);
++
++				switch (pattrib->to_fr_ds) {
++				case 0:
++					_rtw_memcpy(pattrib->ra, pda, ETH_ALEN);
++					_rtw_memcpy(pattrib->ta, psa, ETH_ALEN);
++					ret = sta2sta_data_frame(padapter, rframe, &psta);
++					break;
++
++				case 1:
++					_rtw_memcpy(pattrib->ra, pda, ETH_ALEN);
++					_rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN);
++					ret = ap2sta_data_frame(padapter, rframe, &psta);
++					break;
++
++				case 2:
++					_rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN);
++					_rtw_memcpy(pattrib->ta, psa, ETH_ALEN);
++					ret = sta2ap_data_frame(padapter, rframe, &psta);
++					break;
++				case 3:
++					_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
++					_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
++					ret = _FAIL;
++					break;
++				default:
++					ret = _FAIL;
++					break;
++				}
++
++				if (ret != _SUCCESS) {
++#ifdef DBG_RX_DROP_FRAME
++					RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" 2_data_frame fail: drop pkt\n"
++															, FUNC_ADPT_ARG(padapter));
++#endif
++					ret = _FAIL;
++					goto exit;
++				}
++
++				ret = MPwlanhdr_to_ethhdr(rframe);
++
++				if (ret != _SUCCESS) {
++					#ifdef DBG_RX_DROP_FRAME
++					RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" wlanhdr_to_ethhdr: drop pkt\n"
++						, FUNC_ADPT_ARG(padapter));
++					#endif
++					ret = _FAIL;
++					goto exit;
++				}
++				if (!RTW_CANNOT_RUN(padapter)) {
++					/* indicate this recv_frame */
++					ret = rtw_recv_indicatepkt(padapter, rframe);
++					if (ret != _SUCCESS) {
++						#ifdef DBG_RX_DROP_FRAME
++						RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_recv_indicatepkt fail!\n"
++							, FUNC_ADPT_ARG(padapter));
++						#endif
++						ret = _FAIL;
++						goto exit;
++					}
++				} else {
++					#ifdef DBG_RX_DROP_FRAME
++					RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" bDriverStopped(%s) OR bSurpriseRemoved(%s)\n"
++						, FUNC_ADPT_ARG(padapter)
++						, rtw_is_drv_stopped(padapter) ? "True" : "False"
++						, rtw_is_surprise_removed(padapter) ? "True" : "False");
++					#endif
++					ret = _FAIL;
++					goto exit;
++				}
++
++			}
++		}
++	}
++exit:
++	rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
++	ret = _FAIL;
++	return ret;
++
++}
++#endif
++
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
++int recv_frame_monitor(_adapter *padapter, union recv_frame *rframe)
++{
++	int ret = _SUCCESS;
++	_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
++
++#ifdef CONFIG_WIFI_MONITOR
++	struct net_device *ndev = padapter->pnetdev;
++	_pkt *pskb = NULL;
++
++	if (rframe == NULL)
++		goto exit;
++
++	/* read skb information from recv frame */
++	pskb = rframe->u.hdr.pkt;
++	pskb->len = rframe->u.hdr.len;
++	pskb->data = rframe->u.hdr.rx_data;
++	skb_set_tail_pointer(pskb, rframe->u.hdr.len);
++
++	if (ndev->type == ARPHRD_IEEE80211_RADIOTAP) {
++		/* fill radiotap header */
++		if (rtw_fill_radiotap_hdr(padapter, &rframe->u.hdr.attrib, (u8 *)pskb) == _FAIL) {
++			ret = _FAIL;
++			goto exit;
++		}
++	}
++
++	/* write skb information to recv frame */
++	skb_reset_mac_header(pskb);
++	rframe->u.hdr.len = pskb->len;
++	rframe->u.hdr.rx_data = pskb->data;
++	rframe->u.hdr.rx_head = pskb->head;
++	rframe->u.hdr.rx_tail = skb_tail_pointer(pskb);
++	rframe->u.hdr.rx_end = skb_end_pointer(pskb);
++
++	if (!RTW_CANNOT_RUN(padapter)) {
++		/* indicate this recv_frame */
++		ret = rtw_recv_monitor(padapter, rframe);
++	} else 
++		ret = _FAIL;
++
++exit:
++#endif /* CONFIG_WIFI_MONITOR */
++
++	if (rframe) /* free this recv_frame */
++		rtw_free_recvframe(rframe, pfree_recv_queue);
++
++	return ret;
++}
++#endif
++int recv_func_prehandle(_adapter *padapter, union recv_frame *rframe)
++{
++	int ret = _SUCCESS;
++#ifdef DBG_RX_COUNTER_DUMP
++	struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib;
++#endif
++	_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
++
++#ifdef DBG_RX_COUNTER_DUMP
++	if (padapter->dump_rx_cnt_mode & DUMP_DRV_RX_COUNTER) {
++		if (pattrib->crc_err == 1)
++			padapter->drv_rx_cnt_crcerror++;
++		else
++			padapter->drv_rx_cnt_ok++;
++	}
++#endif
++
++#ifdef CONFIG_MP_INCLUDED
++	if (padapter->registrypriv.mp_mode == 1 || padapter->mppriv.bRTWSmbCfg == _TRUE) {
++		mp_recv_frame(padapter, rframe);
++		ret = _FAIL;
++		goto exit;
++	} else
++#endif
++	{
++		/* check the frame crtl field and decache */
++		ret = validate_recv_frame(padapter, rframe);
++		if (ret != _SUCCESS) {
++			rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
++			goto exit;
++		}
++	}
++exit:
++	return ret;
++}
++
++/*#define DBG_RX_BMC_FRAME*/
++int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe)
++{
++	int ret = _SUCCESS;
++	union recv_frame *orig_prframe = prframe;
++	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
++	struct recv_priv *precvpriv = &padapter->recvpriv;
++	_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
++#ifdef CONFIG_TDLS
++	u8 *psnap_type, *pcategory;
++#endif /* CONFIG_TDLS */
++
++	DBG_COUNTER(padapter->rx_logs.core_rx_post);
++
++	prframe = decryptor(padapter, prframe);
++	if (prframe == NULL) {
++		#ifdef DBG_RX_DROP_FRAME
++		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" decryptor: drop pkt\n"
++			, FUNC_ADPT_ARG(padapter));
++		#endif
++		ret = _FAIL;
++		DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_err);
++		goto _recv_data_drop;
++	}
++
++#ifdef DBG_RX_BMC_FRAME
++	if (IS_MCAST(pattrib->ra))
++		RTW_INFO("%s =>"ADPT_FMT" Rx BC/MC from "MAC_FMT"\n", __func__, ADPT_ARG(padapter), MAC_ARG(pattrib->ta));
++#endif
++
++#if 0
++	if (is_primary_adapter(padapter)) {
++		RTW_INFO("+++\n");
++		{
++			int i;
++			u8	*ptr = get_recvframe_data(prframe);
++			for (i = 0; i < 140; i = i + 8)
++				RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:", *(ptr + i),
++					*(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7));
++
++		}
++		RTW_INFO("---\n");
++	}
++#endif
++
++#ifdef CONFIG_TDLS
++	/* check TDLS frame */
++	psnap_type = get_recvframe_data(orig_prframe) + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE;
++	pcategory = psnap_type + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
++
++	if ((_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_TDLS, ETH_TYPE_LEN)) &&
++	    ((*pcategory == RTW_WLAN_CATEGORY_TDLS) || (*pcategory == RTW_WLAN_CATEGORY_P2P))) {
++		ret = OnTDLS(padapter, prframe);
++		if (ret == _FAIL)
++			goto _exit_recv_func;
++	}
++#endif /* CONFIG_TDLS */
++
++	prframe = recvframe_chk_defrag(padapter, prframe);
++	if (prframe == NULL)	{
++		#ifdef DBG_RX_DROP_FRAME
++		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recvframe_chk_defrag: drop pkt\n"
++			, FUNC_ADPT_ARG(padapter));
++		#endif
++		DBG_COUNTER(padapter->rx_logs.core_rx_post_defrag_err);
++		goto _recv_data_drop;
++	}
++
++	prframe = portctrl(padapter, prframe);
++	if (prframe == NULL) {
++		#ifdef DBG_RX_DROP_FRAME
++		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" portctrl: drop pkt\n"
++			, FUNC_ADPT_ARG(padapter));
++		#endif
++		ret = _FAIL;
++		DBG_COUNTER(padapter->rx_logs.core_rx_post_portctrl_err);
++		goto _recv_data_drop;
++	}
++
++	count_rx_stats(padapter, prframe, NULL);
++
++#ifdef CONFIG_WAPI_SUPPORT
++	rtw_wapi_update_info(padapter, prframe);
++#endif
++
++#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
++	/* including perform A-MPDU Rx Ordering Buffer Control */
++	ret = recv_indicatepkt_reorder(padapter, prframe);
++	if (ret == _FAIL) {
++		rtw_free_recvframe(orig_prframe, pfree_recv_queue);
++		goto _recv_data_drop;
++	} else if (ret == RTW_RX_HANDLED) /* queued OR indicated in order */
++		goto _exit_recv_func;
++#endif
++
++	recv_set_iseq_before_mpdu_process(prframe, pattrib->seq_num, __func__);
++	ret = recv_process_mpdu(padapter, prframe);
++	recv_set_iseq_after_mpdu_process(prframe, pattrib->seq_num, __func__);
++	if (ret == _FAIL)
++		goto _recv_data_drop;
++
++_exit_recv_func:
++	return ret;
++
++_recv_data_drop:
++	precvpriv->dbg_rx_drop_count++;
++	return ret;
++}
++
++int recv_func(_adapter *padapter, union recv_frame *rframe)
++{
++	int ret;
++	struct rx_pkt_attrib *prxattrib = &rframe->u.hdr.attrib;
++	struct recv_priv *recvpriv = &padapter->recvpriv;
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	struct mlme_priv *mlmepriv = &padapter->mlmepriv;
++	u8 *ptr = rframe->u.hdr.rx_data;
++#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
++	u8 type;
++#endif
++
++	if (check_fwstate(mlmepriv, WIFI_MONITOR_STATE) 
++#ifdef RTW_SIMPLE_CONFIG
++		|| (check_fwstate(mlmepriv, WIFI_AP_STATE) && padapter->rtw_simple_config == _TRUE && IS_MCAST(get_ra(ptr)))
++#endif
++		) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
++		recv_frame_monitor(padapter, rframe);
++#endif
++		ret = _SUCCESS;
++		goto exit;
++	}
++
++#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
++	type = GetFrameType(ptr);
++	if ((type == WIFI_DATA_TYPE)&& check_fwstate(mlmepriv, WIFI_STATION_STATE)) {
++		struct wlan_network *cur_network = &(mlmepriv->cur_network);
++		if ( _rtw_memcmp(get_addr2_ptr(ptr), cur_network->network.MacAddress, ETH_ALEN)==0) {
++			recv_frame_monitor(padapter, rframe);
++			ret = _SUCCESS;
++			goto exit;
++		}
++	}
++#endif
++		/* check if need to handle uc_swdec_pending_queue*/
++		if (check_fwstate(mlmepriv, WIFI_STATION_STATE) && psecuritypriv->busetkipkey) {
++			union recv_frame *pending_frame;
++			int cnt = 0;
++
++			while ((pending_frame = rtw_alloc_recvframe(&padapter->recvpriv.uc_swdec_pending_queue))) {
++				cnt++;
++				DBG_COUNTER(padapter->rx_logs.core_rx_dequeue);
++				recv_func_posthandle(padapter, pending_frame);
++			}
++
++			if (cnt)
++				RTW_INFO(FUNC_ADPT_FMT" dequeue %d from uc_swdec_pending_queue\n",
++					 FUNC_ADPT_ARG(padapter), cnt);
++		}
++
++	DBG_COUNTER(padapter->rx_logs.core_rx);
++	ret = recv_func_prehandle(padapter, rframe);
++
++	if (ret == _SUCCESS) {
++
++		/* check if need to enqueue into uc_swdec_pending_queue*/
++		if (check_fwstate(mlmepriv, WIFI_STATION_STATE) &&
++		    !IS_MCAST(prxattrib->ra) && prxattrib->encrypt > 0 &&
++		    (prxattrib->bdecrypted == 0 || psecuritypriv->sw_decrypt == _TRUE) &&
++		    psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPAPSK &&
++		    !psecuritypriv->busetkipkey) {
++			DBG_COUNTER(padapter->rx_logs.core_rx_enqueue);
++			rtw_enqueue_recvframe(rframe, &padapter->recvpriv.uc_swdec_pending_queue);
++			/* RTW_INFO("%s: no key, enqueue uc_swdec_pending_queue\n", __func__); */
++
++			if (recvpriv->free_recvframe_cnt < NR_RECVFRAME / 4) {
++				/* to prevent from recvframe starvation, get recvframe from uc_swdec_pending_queue to free_recvframe_cnt */
++				rframe = rtw_alloc_recvframe(&padapter->recvpriv.uc_swdec_pending_queue);
++				if (rframe)
++					goto do_posthandle;
++			}
++			goto exit;
++		}
++
++do_posthandle:
++		ret = recv_func_posthandle(padapter, rframe);
++	}
++
++exit:
++	return ret;
++}
++
++
++s32 rtw_recv_entry(union recv_frame *precvframe)
++{
++	_adapter *padapter;
++	struct recv_priv *precvpriv;
++	s32 ret = _SUCCESS;
++
++
++
++	padapter = precvframe->u.hdr.adapter;
++
++	precvpriv = &padapter->recvpriv;
++
++
++	ret = recv_func(padapter, precvframe);
++	if (ret == _FAIL) {
++		goto _recv_entry_drop;
++	}
++
++
++	precvpriv->rx_pkts++;
++
++
++	return ret;
++
++_recv_entry_drop:
++
++#ifdef CONFIG_MP_INCLUDED
++	if (padapter->registrypriv.mp_mode == 1)
++		padapter->mppriv.rx_pktloss = precvpriv->rx_drop;
++#endif
++
++
++
++	return ret;
++}
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++static void rtw_signal_stat_timer_hdl(void *ctx)
++{
++	_adapter *adapter = (_adapter *)ctx;
++	struct recv_priv *recvpriv = &adapter->recvpriv;
++
++	u32 tmp_s, tmp_q;
++	u8 avg_signal_strength = 0;
++	u8 avg_signal_qual = 0;
++	u32 num_signal_strength = 0;
++	u32 num_signal_qual = 0;
++	u8 ratio_pre_stat = 0, ratio_curr_stat = 0, ratio_total = 0, ratio_profile = SIGNAL_STAT_CALC_PROFILE_0;
++
++	if (adapter->recvpriv.is_signal_dbg) {
++		/* update the user specific value, signal_strength_dbg, to signal_strength, rssi */
++		adapter->recvpriv.signal_strength = adapter->recvpriv.signal_strength_dbg;
++		adapter->recvpriv.rssi = (s8)translate_percentage_to_dbm((u8)adapter->recvpriv.signal_strength_dbg);
++	} else {
++
++		if (recvpriv->signal_strength_data.update_req == 0) { /* update_req is clear, means we got rx */
++			avg_signal_strength = recvpriv->signal_strength_data.avg_val;
++			num_signal_strength = recvpriv->signal_strength_data.total_num;
++			/* after avg_vals are accquired, we can re-stat the signal values */
++			recvpriv->signal_strength_data.update_req = 1;
++		}
++
++		if (recvpriv->signal_qual_data.update_req == 0) { /* update_req is clear, means we got rx */
++			avg_signal_qual = recvpriv->signal_qual_data.avg_val;
++			num_signal_qual = recvpriv->signal_qual_data.total_num;
++			/* after avg_vals are accquired, we can re-stat the signal values */
++			recvpriv->signal_qual_data.update_req = 1;
++		}
++
++		if (num_signal_strength == 0) {
++			if (rtw_get_on_cur_ch_time(adapter) == 0
++			    || rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) < 2 * adapter->mlmeextpriv.mlmext_info.bcn_interval
++			   )
++				goto set_timer;
++		}
++
++		if (check_fwstate(&adapter->mlmepriv, WIFI_UNDER_SURVEY) == _TRUE
++		    || check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE) == _FALSE
++		   )
++			goto set_timer;
++
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_buddy_check_fwstate(adapter, WIFI_UNDER_SURVEY) == _TRUE)
++			goto set_timer;
++#endif
++		if (adapter->registrypriv.mp_mode == 1)
++			ratio_profile = SIGNAL_STAT_CALC_PROFILE_2;
++		else if (RTW_SIGNAL_STATE_CALC_PROFILE < SIGNAL_STAT_CALC_PROFILE_MAX)
++			ratio_profile = RTW_SIGNAL_STATE_CALC_PROFILE;
++
++		ratio_pre_stat = signal_stat_calc_profile[ratio_profile][0];
++		ratio_curr_stat = signal_stat_calc_profile[ratio_profile][1];
++		ratio_total = ratio_pre_stat + ratio_curr_stat;
++
++		/* update value of signal_strength, rssi, signal_qual */
++		tmp_s = (ratio_curr_stat * avg_signal_strength + ratio_pre_stat * recvpriv->signal_strength);
++		if (tmp_s % ratio_total)
++			tmp_s = tmp_s / ratio_total + 1;
++		else
++			tmp_s = tmp_s / ratio_total;
++		if (tmp_s > 100)
++			tmp_s = 100;
++
++		tmp_q = (ratio_curr_stat * avg_signal_qual + ratio_pre_stat * recvpriv->signal_qual);
++		if (tmp_q % ratio_total)
++			tmp_q = tmp_q / ratio_total + 1;
++		else
++			tmp_q = tmp_q / ratio_total;
++		if (tmp_q > 100)
++			tmp_q = 100;
++
++		recvpriv->signal_strength = tmp_s;
++		recvpriv->rssi = (s8)translate_percentage_to_dbm(tmp_s);
++		recvpriv->signal_qual = tmp_q;
++
++#if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1
++		RTW_INFO(FUNC_ADPT_FMT" signal_strength:%3u, rssi:%3d, signal_qual:%3u"
++			 ", num_signal_strength:%u, num_signal_qual:%u"
++			 ", on_cur_ch_ms:%d"
++			 "\n"
++			 , FUNC_ADPT_ARG(adapter)
++			 , recvpriv->signal_strength
++			 , recvpriv->rssi
++			 , recvpriv->signal_qual
++			 , num_signal_strength, num_signal_qual
++			, rtw_get_on_cur_ch_time(adapter) ? rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) : 0
++			);
++#endif
++	}
++
++set_timer:
++	rtw_set_signal_stat_timer(recvpriv);
++
++}
++#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
++
++static void rx_process_rssi(_adapter *padapter, union recv_frame *prframe)
++{
++	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++	struct signal_stat *signal_stat = &padapter->recvpriv.signal_strength_data;
++#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
++	u32 last_rssi, tmp_val;
++#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
++
++	/* RTW_INFO("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->recv_signal_power,pattrib->signal_strength); */
++	/* if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon) */
++	{
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++		if (signal_stat->update_req) {
++			signal_stat->total_num = 0;
++			signal_stat->total_val = 0;
++			signal_stat->update_req = 0;
++		}
++
++		signal_stat->total_num++;
++		signal_stat->total_val  += pattrib->phy_info.signal_strength;
++		signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
++#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
++
++		/* Adapter->RxStats.RssiCalculateCnt++;	 */ /* For antenna Test */
++		if (padapter->recvpriv.signal_strength_data.total_num++ >= PHY_RSSI_SLID_WIN_MAX) {
++			padapter->recvpriv.signal_strength_data.total_num = PHY_RSSI_SLID_WIN_MAX;
++			last_rssi = padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index];
++			padapter->recvpriv.signal_strength_data.total_val -= last_rssi;
++		}
++		padapter->recvpriv.signal_strength_data.total_val  += pattrib->phy_info.signal_strength;
++
++		padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->phy_info.signal_strength;
++		if (padapter->recvpriv.signal_strength_data.index >= PHY_RSSI_SLID_WIN_MAX)
++			padapter->recvpriv.signal_strength_data.index = 0;
++
++
++		tmp_val = padapter->recvpriv.signal_strength_data.total_val / padapter->recvpriv.signal_strength_data.total_num;
++
++		if (padapter->recvpriv.is_signal_dbg) {
++			padapter->recvpriv.signal_strength = padapter->recvpriv.signal_strength_dbg;
++			padapter->recvpriv.rssi = (s8)translate_percentage_to_dbm(padapter->recvpriv.signal_strength_dbg);
++		} else {
++			padapter->recvpriv.signal_strength = tmp_val;
++			padapter->recvpriv.rssi = (s8)translate_percentage_to_dbm(tmp_val);
++		}
++
++#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
++	}
++}
++
++static void rx_process_link_qual(_adapter *padapter, union recv_frame *prframe)
++{
++	struct rx_pkt_attrib *pattrib;
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++	struct signal_stat *signal_stat;
++#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
++	u32 last_evm = 0, tmpVal;
++#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
++
++	if (prframe == NULL || padapter == NULL)
++		return;
++
++	pattrib = &prframe->u.hdr.attrib;
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++	signal_stat = &padapter->recvpriv.signal_qual_data;
++#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
++
++	/* RTW_INFO("process_link_qual=> pattrib->signal_qual(%d)\n ",pattrib->signal_qual); */
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++	if (signal_stat->update_req) {
++		signal_stat->total_num = 0;
++		signal_stat->total_val = 0;
++		signal_stat->update_req = 0;
++	}
++
++	signal_stat->total_num++;
++	signal_stat->total_val  += pattrib->phy_info.signal_quality;
++	signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
++
++#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
++	if (pattrib->phy_info.signal_quality != 0) {
++		/*  */
++		/* 1. Record the general EVM to the sliding window. */
++		/*  */
++		if (padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) {
++			padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX;
++			last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index];
++			padapter->recvpriv.signal_qual_data.total_val -= last_evm;
++		}
++		padapter->recvpriv.signal_qual_data.total_val += pattrib->phy_info.signal_quality;
++
++		padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->phy_info.signal_quality;
++		if (padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX)
++			padapter->recvpriv.signal_qual_data.index = 0;
++
++
++		/* <1> Showed on UI for user, in percentage. */
++		tmpVal = padapter->recvpriv.signal_qual_data.total_val / padapter->recvpriv.signal_qual_data.total_num;
++		padapter->recvpriv.signal_qual = (u8)tmpVal;
++
++	}
++#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
++}
++
++void rx_process_phy_info(_adapter *padapter, union recv_frame *rframe)
++{
++	/* Check RSSI */
++	rx_process_rssi(padapter, rframe);
++
++	/* Check PWDB */
++	/* process_PWDB(padapter, rframe); */
++
++	/* UpdateRxSignalStatistics8192C(Adapter, pRfd); */
++
++	/* Check EVM */
++	rx_process_link_qual(padapter, rframe);
++	rtw_store_phy_info(padapter, rframe);
++}
++
++void rx_query_phy_status(
++	union recv_frame	*precvframe,
++	u8 *pphy_status)
++{
++	PADAPTER			padapter = precvframe->u.hdr.adapter;
++	struct rx_pkt_attrib	*pattrib = &precvframe->u.hdr.attrib;
++	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
++	struct phydm_phyinfo_struct *p_phy_info = &pattrib->phy_info;
++	u8					*wlanhdr;
++	struct phydm_perpkt_info_struct pkt_info;
++	u8 *ta, *ra;
++	u8 is_ra_bmc;
++	struct sta_priv *pstapriv;
++	struct sta_info *psta = NULL;
++	struct recv_priv  *precvpriv = &padapter->recvpriv;
++	/* _irqL		irqL; */
++
++	pkt_info.is_packet_match_bssid = _FALSE;
++	pkt_info.is_packet_to_self = _FALSE;
++	pkt_info.is_packet_beacon = _FALSE;
++	pkt_info.ppdu_cnt = pattrib->ppdu_cnt;
++	pkt_info.station_id = 0xFF;
++
++	wlanhdr = get_recvframe_data(precvframe);
++
++	ta = get_ta(wlanhdr);
++	ra = get_ra(wlanhdr);
++	is_ra_bmc = IS_MCAST(ra);
++
++	if (_rtw_memcmp(adapter_mac_addr(padapter), ta, ETH_ALEN) == _TRUE) {
++		static systime start_time = 0;
++
++#if 0 /*For debug */
++		if (IsFrameTypeCtrl(wlanhdr)) {
++			RTW_INFO("-->Control frame: Y\n");
++			RTW_INFO("-->pkt_len: %d\n", pattrib->pkt_len);
++			RTW_INFO("-->Sub Type = 0x%X\n", get_frame_sub_type(wlanhdr));
++		}
++
++		/* Dump first 40 bytes of header */
++		int i = 0;
++
++		for (i = 0; i < 40; i++)
++			RTW_INFO("%d: %X\n", i, *((u8 *)wlanhdr + i));
++
++		RTW_INFO("\n");
++#endif
++
++		if ((start_time == 0) || (rtw_get_passing_time_ms(start_time) > 5000)) {
++			RTW_PRINT("Warning!!! %s: Confilc mac addr!!\n", __func__);
++			start_time = rtw_get_current_time();
++		}
++		precvpriv->dbg_rx_conflic_mac_addr_cnt++;
++	} else {
++		pstapriv = &padapter->stapriv;
++		psta = rtw_get_stainfo(pstapriv, ta);
++		if (psta)
++			pkt_info.station_id = psta->cmn.mac_id;
++	}
++
++	pkt_info.is_packet_match_bssid = (!IsFrameTypeCtrl(wlanhdr))
++		&& (!pattrib->icv_err) && (!pattrib->crc_err)
++		&& ((!MLME_IS_MESH(padapter) && _rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN))
++			|| (MLME_IS_MESH(padapter) && psta));
++
++	pkt_info.is_to_self = (!pattrib->icv_err) && (!pattrib->crc_err)
++		&& _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN);
++
++	pkt_info.is_packet_to_self = pkt_info.is_packet_match_bssid
++		&& _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN);
++
++	pkt_info.is_packet_beacon = pkt_info.is_packet_match_bssid
++				 && (get_frame_sub_type(wlanhdr) == WIFI_BEACON);
++
++	if (psta && IsFrameTypeData(wlanhdr)) {
++		if (is_ra_bmc)
++			psta->curr_rx_rate_bmc = pattrib->data_rate;
++		else
++			psta->curr_rx_rate = pattrib->data_rate;
++	}
++	pkt_info.data_rate = pattrib->data_rate;
++
++	odm_phy_status_query(&pHalData->odmpriv, p_phy_info, pphy_status, &pkt_info);
++
++	/* If bw is initial value, get from phy status */
++	if (pattrib->bw == CHANNEL_WIDTH_MAX)
++		pattrib->bw = p_phy_info->band_width;
++
++	if (p_phy_info->physts_rpt_valid == _TRUE) {
++		precvframe->u.hdr.psta = NULL;
++		if (padapter->registrypriv.mp_mode != 1) {
++			if ((!MLME_IS_MESH(padapter) && pkt_info.is_packet_match_bssid)
++				|| (MLME_IS_MESH(padapter) && psta)) {
++				if (psta) {
++					precvframe->u.hdr.psta = psta;
++					rx_process_phy_info(padapter, precvframe);
++				}
++			} else if (pkt_info.is_packet_to_self || pkt_info.is_packet_beacon) {
++				if (psta)
++					precvframe->u.hdr.psta = psta;
++				rx_process_phy_info(padapter, precvframe);
++			}
++		} else {
++#ifdef CONFIG_MP_INCLUDED
++			if (padapter->mppriv.brx_filter_beacon == _TRUE) {
++				if (pkt_info.is_packet_beacon) {
++					RTW_INFO("in MP Rx is_packet_beacon\n");
++					if (psta)
++						precvframe->u.hdr.psta = psta;
++					rx_process_phy_info(padapter, precvframe);
++				}
++			} else
++#endif
++			{
++					if (psta)
++						precvframe->u.hdr.psta = psta;
++					rx_process_phy_info(padapter, precvframe);
++			}
++		}
++	}
++
++	rtw_odm_parse_rx_phy_status_chinfo(precvframe, pphy_status);
++}
++/*
++* Increase and check if the continual_no_rx_packet of this @param pmlmepriv is larger than MAX_CONTINUAL_NORXPACKET_COUNT
++* @return _TRUE:
++* @return _FALSE:
++*/
++int rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index)
++{
++
++	int ret = _FALSE;
++	int value = ATOMIC_INC_RETURN(&sta->continual_no_rx_packet[tid_index]);
++
++	if (value >= MAX_CONTINUAL_NORXPACKET_COUNT)
++		ret = _TRUE;
++
++	return ret;
++}
++
++/*
++* Set the continual_no_rx_packet of this @param pmlmepriv to 0
++*/
++void rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index)
++{
++	ATOMIC_SET(&sta->continual_no_rx_packet[tid_index], 0);
++}
++
++u8 adapter_allow_bmc_data_rx(_adapter *adapter)
++{
++	if (check_fwstate(&adapter->mlmepriv, WIFI_MONITOR_STATE | WIFI_MP_STATE) == _TRUE)
++		return 1;
++
++#ifdef RTW_SIMPLE_CONFIG
++	/* allow AP to receive multicast packet for RtwSimpleConfigV4 */
++	if (MLME_IS_AP(adapter) && adapter->rtw_simple_config)
++		return 1;
++#endif
++
++	if (MLME_IS_AP(adapter))
++		return 0;
++
++	if (rtw_linked_check(adapter) == _FALSE)
++		return 0;
++
++	return 1;
++}
++
++s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status)
++{
++	s32 ret = _SUCCESS;
++	u8 *pbuf = precvframe->u.hdr.rx_data;
++	u8 *pda = get_ra(pbuf);
++	u8 ra_is_bmc = IS_MCAST(pda);
++	_adapter *primary_padapter = precvframe->u.hdr.adapter;
++#ifdef CONFIG_CONCURRENT_MODE
++	_adapter *iface = NULL;
++
++	#ifdef CONFIG_MP_INCLUDED
++	if (rtw_mp_mode_check(primary_padapter))
++		goto bypass_concurrent_hdl;
++	#endif
++
++	if (ra_is_bmc == _FALSE) { /*unicast packets*/
++		iface = rtw_get_iface_by_macddr(primary_padapter , pda);
++		if (NULL == iface) {
++		#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++			if (_rtw_memcmp(pda, adapter_pno_mac_addr(primary_padapter),
++					ETH_ALEN) != _TRUE)
++		#endif
++			RTW_INFO("%s [WARN] Cannot find appropriate adapter - mac_addr : "MAC_FMT"\n", __func__, MAC_ARG(pda));
++			/*rtw_warn_on(1);*/
++		} else
++			precvframe->u.hdr.adapter = iface;
++	} else   /* Handle BC/MC Packets	*/
++		rtw_mi_buddy_clone_bcmc_packet(primary_padapter, precvframe, pphy_status);
++bypass_concurrent_hdl:
++#endif /* CONFIG_CONCURRENT_MODE */
++	if (primary_padapter->registrypriv.mp_mode != 1) {
++		/* skip unnecessary bmc data frame for primary adapter */
++		if (ra_is_bmc == _TRUE && GetFrameType(pbuf) == WIFI_DATA_TYPE
++			&& !adapter_allow_bmc_data_rx(precvframe->u.hdr.adapter)
++		) {
++			rtw_free_recvframe(precvframe, &precvframe->u.hdr.adapter->recvpriv.free_recv_queue);
++			goto exit;
++		}
++	}
++
++	if (pphy_status) {
++		rx_query_phy_status(precvframe, pphy_status);
++
++#ifdef CONFIG_WIFI_MONITOR
++		rx_query_moinfo(&precvframe->u.hdr.attrib, pphy_status);
++#endif
++	}
++	ret = rtw_recv_entry(precvframe);
++
++exit:
++	return ret;
++}
++
++#ifdef CONFIG_RECV_THREAD_MODE
++thread_return rtw_recv_thread(thread_context context)
++{
++	_adapter *adapter = (_adapter *)context;
++	struct recv_priv *recvpriv = &adapter->recvpriv;
++	s32 err = _SUCCESS;
++#ifdef RTW_RECV_THREAD_HIGH_PRIORITY
++#ifdef PLATFORM_LINUX
++	struct sched_param param = { .sched_priority = 1 };
++
++	sched_setscheduler(current, SCHED_FIFO, &param);
++#endif /* PLATFORM_LINUX */
++#endif /*RTW_RECV_THREAD_HIGH_PRIORITY*/
++	thread_enter("RTW_RECV_THREAD");
++
++	RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(adapter));
++
++	do {
++		err = _rtw_down_sema(&recvpriv->recv_sema);
++		if (_FAIL == err) {
++			RTW_ERR(FUNC_ADPT_FMT" down recv_sema fail!\n", FUNC_ADPT_ARG(adapter));
++			goto exit;
++		}
++
++		if (RTW_CANNOT_RUN(adapter)) {
++			RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n",
++				FUNC_ADPT_ARG(adapter),
++				rtw_is_drv_stopped(adapter) ? "True" : "False",
++				rtw_is_surprise_removed(adapter) ? "True" : "False");
++			goto exit;
++		}
++
++		err = rtw_hal_recv_hdl(adapter);
++
++		if (err == RTW_RFRAME_UNAVAIL
++			|| err == RTW_RFRAME_PKT_UNAVAIL
++		) {
++			rtw_msleep_os(1);
++			_rtw_up_sema(&recvpriv->recv_sema);
++		}
++
++		flush_signals_thread();
++
++	} while (err != _FAIL);
++
++exit:
++
++	RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(adapter));
++
++	rtw_thread_wait_stop();
++
++	return 0;
++}
++#endif /* CONFIG_RECV_THREAD_MODE */
++
++#if DBG_RX_BH_TRACKING
++void rx_bh_tk_set_stage(struct recv_priv *recv, u32 s)
++{
++	recv->rx_bh_stage = s;
++}
++
++void rx_bh_tk_set_buf(struct recv_priv *recv, void *buf, void *data, u32 dlen)
++{
++	if (recv->rx_bh_cbuf)
++		recv->rx_bh_lbuf = recv->rx_bh_cbuf;
++	recv->rx_bh_cbuf = buf;
++	if (buf) {
++		recv->rx_bh_cbuf_data = data;
++		recv->rx_bh_cbuf_dlen = dlen;
++		recv->rx_bh_buf_dq_cnt++;
++	} else {
++		recv->rx_bh_cbuf_data = NULL;
++		recv->rx_bh_cbuf_dlen = 0;
++	}
++}
++
++void rx_bh_tk_set_buf_pos(struct recv_priv *recv, void *pos)
++{
++	if (recv->rx_bh_cbuf) {
++		recv->rx_bh_cbuf_pos = pos - recv->rx_bh_cbuf_data;
++	} else {
++		rtw_warn_on(1);
++		recv->rx_bh_cbuf_pos = 0;
++	}
++}
++
++void rx_bh_tk_set_frame(struct recv_priv *recv, void *frame)
++{
++	recv->rx_bh_cframe = frame;
++}
++
++void dump_rx_bh_tk(void *sel, struct recv_priv *recv)
++{
++	RTW_PRINT_SEL(sel, "[RXBHTK]s:%u, buf_dqc:%u, lbuf:%p, cbuf:%p, dlen:%u, pos:%u, cframe:%p\n"
++		, recv->rx_bh_stage
++		, recv->rx_bh_buf_dq_cnt
++		, recv->rx_bh_lbuf
++		, recv->rx_bh_cbuf
++		, recv->rx_bh_cbuf_dlen
++		, recv->rx_bh_cbuf_pos
++		, recv->rx_bh_cframe
++	);
++}
++#endif /* DBG_RX_BH_TRACKING */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_rf.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_rf.c
+new file mode 100644
+index 000000000..12cca5615
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_rf.c
+@@ -0,0 +1,2126 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_RF_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++u8 center_ch_2g[CENTER_CH_2G_NUM] = {
++/* G00 */1, 2,
++/* G01 */3, 4, 5,
++/* G02 */6, 7, 8,
++/* G03 */9, 10, 11,
++/* G04 */12, 13,
++/* G05 */14
++};
++
++#define ch_to_cch_2g_idx(ch) ((ch) - 1)
++
++u8 center_ch_2g_40m[CENTER_CH_2G_40M_NUM] = {
++	3,
++	4,
++	5,
++	6,
++	7,
++	8,
++	9,
++	10,
++	11,
++};
++
++u8 op_chs_of_cch_2g_40m[CENTER_CH_2G_40M_NUM][2] = {
++	{1, 5}, /* 3 */
++	{2, 6}, /* 4 */
++	{3, 7}, /* 5 */
++	{4, 8}, /* 6 */
++	{5, 9}, /* 7 */
++	{6, 10}, /* 8 */
++	{7, 11}, /* 9 */
++	{8, 12}, /* 10 */
++	{9, 13}, /* 11 */
++};
++
++u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM] = {
++/* G00 */36, 38, 40,
++	42,
++/* G01 */44, 46, 48,
++	/* 50, */
++/* G02 */52, 54, 56,
++	58,
++/* G03 */60, 62, 64,
++/* G04 */100, 102, 104,
++	106,
++/* G05 */108, 110, 112,
++	/* 114, */
++/* G06 */116, 118, 120,
++	122,
++/* G07 */124, 126, 128,
++/* G08 */132, 134, 136,
++	138,
++/* G09 */140, 142, 144,
++/* G10 */149, 151, 153,
++	155,
++/* G11 */157, 159, 161,
++	/* 163, */
++/* G12 */165, 167, 169,
++	171,
++/* G13 */173, 175, 177
++};
++
++u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM] = {
++/* G00 */36, 40,
++/* G01 */44, 48,
++/* G02 */52, 56,
++/* G03 */60, 64,
++/* G04 */100, 104,
++/* G05 */108, 112,
++/* G06 */116, 120,
++/* G07 */124, 128,
++/* G08 */132, 136,
++/* G09 */140, 144,
++/* G10 */149, 153,
++/* G11 */157, 161,
++/* G12 */165, 169,
++/* G13 */173, 177
++};
++
++#define ch_to_cch_5g_20m_idx(ch) \
++	( \
++		((ch) >= 36 && (ch) <= 64) ? (((ch) - 36) >> 2) : \
++		((ch) >= 100 && (ch) <= 144) ? 8 + (((ch) - 100) >> 2) : \
++		((ch) >= 149 && (ch) <= 177) ? 20 + (((ch) - 149) >> 2) : 255 \
++	)
++
++u8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM] = {
++/* G00 */38,
++/* G01 */46,
++/* G02 */54,
++/* G03 */62,
++/* G04 */102,
++/* G05 */110,
++/* G06 */118,
++/* G07 */126,
++/* G08 */134,
++/* G09 */142,
++/* G10 */151,
++/* G11 */159,
++/* G12 */167,
++/* G13 */175
++};
++
++u8 center_ch_5g_20m_40m[CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM] = {
++/* G00 */36, 38, 40,
++/* G01 */44, 46, 48,
++/* G02 */52, 54, 56,
++/* G03 */60, 62, 64,
++/* G04 */100, 102, 104,
++/* G05 */108, 110, 112,
++/* G06 */116, 118, 120,
++/* G07 */124, 126, 128,
++/* G08 */132, 134, 136,
++/* G09 */140, 142, 144,
++/* G10 */149, 151, 153,
++/* G11 */157, 159, 161,
++/* G12 */165, 167, 169,
++/* G13 */173, 175, 177
++};
++
++u8 op_chs_of_cch_5g_40m[CENTER_CH_5G_40M_NUM][2] = {
++	{36, 40}, /* 38 */
++	{44, 48}, /* 46 */
++	{52, 56}, /* 54 */
++	{60, 64}, /* 62 */
++	{100, 104}, /* 102 */
++	{108, 112}, /* 110 */
++	{116, 120}, /* 118 */
++	{124, 128}, /* 126 */
++	{132, 136}, /* 134 */
++	{140, 144}, /* 142 */
++	{149, 153}, /* 151 */
++	{157, 161}, /* 159 */
++	{165, 169}, /* 167 */
++	{173, 177}, /* 175 */
++};
++
++u8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM] = {
++/* G00 ~ G01*/42,
++/* G02 ~ G03*/58,
++/* G04 ~ G05*/106,
++/* G06 ~ G07*/122,
++/* G08 ~ G09*/138,
++/* G10 ~ G11*/155,
++/* G12 ~ G13*/171
++};
++
++u8 op_chs_of_cch_5g_80m[CENTER_CH_5G_80M_NUM][4] = {
++	{36, 40, 44, 48}, /* 42 */
++	{52, 56, 60, 64}, /* 58 */
++	{100, 104, 108, 112}, /* 106 */
++	{116, 120, 124, 128}, /* 122 */
++	{132, 136, 140, 144}, /* 138 */
++	{149, 153, 157, 161}, /* 155 */
++	{165, 169, 173, 177}, /* 171 */
++};
++
++u8 center_ch_5g_160m[CENTER_CH_5G_160M_NUM] = {
++/* G00 ~ G03*/50,
++/* G04 ~ G07*/114,
++/* G10 ~ G13*/163
++};
++
++u8 op_chs_of_cch_5g_160m[CENTER_CH_5G_160M_NUM][8] = {
++	{36, 40, 44, 48, 52, 56, 60, 64}, /* 50 */
++	{100, 104, 108, 112, 116, 120, 124, 128}, /* 114 */
++	{149, 153, 157, 161, 165, 169, 173, 177}, /* 163 */
++};
++
++struct center_chs_ent_t {
++	u8 ch_num;
++	u8 *chs;
++};
++
++struct center_chs_ent_t center_chs_2g_by_bw[] = {
++	{CENTER_CH_2G_NUM, center_ch_2g},
++	{CENTER_CH_2G_40M_NUM, center_ch_2g_40m},
++};
++
++struct center_chs_ent_t center_chs_5g_by_bw[] = {
++	{CENTER_CH_5G_20M_NUM, center_ch_5g_20m},
++	{CENTER_CH_5G_40M_NUM, center_ch_5g_40m},
++	{CENTER_CH_5G_80M_NUM, center_ch_5g_80m},
++	{CENTER_CH_5G_160M_NUM, center_ch_5g_160m},
++};
++
++/*
++ * Get center channel of smaller bandwidth by @param cch, @param bw, @param offset
++ * @cch: the given center channel
++ * @bw: the given bandwidth
++ * @offset: the given primary SC offset of the given bandwidth
++ *
++ * return center channel of smaller bandiwdth if valid, or 0
++ */
++u8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset)
++{
++	u8 t_cch = 0;
++
++	if (bw == CHANNEL_WIDTH_20) {
++		t_cch = cch;
++		goto exit;
++	}
++
++	if (offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	/* 2.4G, 40MHz */
++	if (cch >= 3 && cch <= 11 && bw == CHANNEL_WIDTH_40) {
++		t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2;
++		goto exit;
++	}
++
++	/* 5G, 160MHz */
++	if (cch >= 50 && cch <= 163 && bw == CHANNEL_WIDTH_160) {
++		t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 8 : cch - 8;
++		goto exit;
++
++	/* 5G, 80MHz */
++	} else if (cch >= 42 && cch <= 171 && bw == CHANNEL_WIDTH_80) {
++		t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 4 : cch - 4;
++		goto exit;
++
++	/* 5G, 40MHz */
++	} else if (cch >= 38 && cch <= 175 && bw == CHANNEL_WIDTH_40) {
++		t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2;
++		goto exit;
++
++	} else {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++exit:
++	return t_cch;
++}
++
++/*
++ * Get center channel of smaller bandwidth by @param cch, @param bw, @param opch
++ * @cch: the given center channel
++ * @bw: the given bandwidth
++ * @opch: the given operating channel
++ *
++ * return center channel of smaller bandiwdth if valid, or 0
++ */
++u8 rtw_get_scch_by_cch_opch(u8 cch, u8 bw, u8 opch)
++{
++	u8 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++	if (opch > cch)
++		offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++	else if (opch < cch)
++		offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++
++	return rtw_get_scch_by_cch_offset(cch, bw, offset);
++}
++
++struct op_chs_ent_t {
++	u8 ch_num;
++	u8 *chs;
++};
++
++struct op_chs_ent_t op_chs_of_cch_2g_by_bw[] = {
++	{1, center_ch_2g},
++	{2, (u8 *)op_chs_of_cch_2g_40m},
++};
++
++struct op_chs_ent_t op_chs_of_cch_5g_by_bw[] = {
++	{1, center_ch_5g_20m},
++	{2, (u8 *)op_chs_of_cch_5g_40m},
++	{4, (u8 *)op_chs_of_cch_5g_80m},
++	{8, (u8 *)op_chs_of_cch_5g_160m},
++};
++
++inline u8 center_chs_2g_num(u8 bw)
++{
++	if (bw > CHANNEL_WIDTH_40)
++		return 0;
++
++	return center_chs_2g_by_bw[bw].ch_num;
++}
++
++inline u8 center_chs_2g(u8 bw, u8 id)
++{
++	if (bw > CHANNEL_WIDTH_40)
++		return 0;
++
++	if (id >= center_chs_2g_num(bw))
++		return 0;
++
++	return center_chs_2g_by_bw[bw].chs[id];
++}
++
++inline u8 center_chs_5g_num(u8 bw)
++{
++	if (bw > CHANNEL_WIDTH_160)
++		return 0;
++
++	return center_chs_5g_by_bw[bw].ch_num;
++}
++
++inline u8 center_chs_5g(u8 bw, u8 id)
++{
++	if (bw > CHANNEL_WIDTH_160)
++		return 0;
++
++	if (id >= center_chs_5g_num(bw))
++		return 0;
++
++	return center_chs_5g_by_bw[bw].chs[id];
++}
++
++/*
++ * Get available op channels by @param cch, @param bw
++ * @cch: the given center channel
++ * @bw: the given bandwidth
++ * @op_chs: the pointer to return pointer of op channel array
++ * @op_ch_num: the pointer to return pointer of op channel number
++ *
++ * return valid (1) or not (0)
++ */
++u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num)
++{
++	int i;
++	struct center_chs_ent_t *c_chs_ent = NULL;
++	struct op_chs_ent_t *op_chs_ent = NULL;
++	u8 valid = 1;
++
++	if (cch <= 14
++		&& bw <= CHANNEL_WIDTH_40
++	) {
++		c_chs_ent = &center_chs_2g_by_bw[bw];
++		op_chs_ent = &op_chs_of_cch_2g_by_bw[bw];
++	} else if (cch >= 36 && cch <= 177
++		&& bw <= CHANNEL_WIDTH_160
++	) {
++		c_chs_ent = &center_chs_5g_by_bw[bw];
++		op_chs_ent = &op_chs_of_cch_5g_by_bw[bw];
++	} else {
++		valid = 0;
++		goto exit;
++	}
++
++	for (i = 0; i < c_chs_ent->ch_num; i++)
++		if (cch == *(c_chs_ent->chs + i))
++			break;
++
++	if (i == c_chs_ent->ch_num) {
++		valid = 0;
++		goto exit;
++	}
++
++	*op_chs = op_chs_ent->chs + op_chs_ent->ch_num * i;
++	*op_ch_num = op_chs_ent->ch_num;
++
++exit:
++	return valid;
++}
++
++u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset)
++{
++	u8 valid = 1;
++	u8 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++	if (bw == CHANNEL_WIDTH_20)
++		goto exit;
++
++	if (bw >= CHANNEL_WIDTH_80 && ch <= 14) {
++		valid = 0;
++		goto exit;
++	}
++
++	if (ch >= 1 && ch <= 4)
++		offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++	else if (ch >= 5 && ch <= 9) {
++		if (*r_offset == HAL_PRIME_CHNL_OFFSET_LOWER || *r_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
++			offset = *r_offset; /* both lower and upper is valid, obey input value */
++		else
++			offset = HAL_PRIME_CHNL_OFFSET_UPPER; /* default use upper */
++	} else if (ch >= 10 && ch <= 13)
++		offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++	else if (ch == 14) {
++		valid = 0; /* ch14 doesn't support 40MHz bandwidth */
++		goto exit;
++	} else if (ch >= 36 && ch <= 177) {
++		switch (ch) {
++		case 36:
++		case 44:
++		case 52:
++		case 60:
++		case 100:
++		case 108:
++		case 116:
++		case 124:
++		case 132:
++		case 140:
++		case 149:
++		case 157:
++		case 165:
++		case 173:
++			offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++			break;
++		case 40:
++		case 48:
++		case 56:
++		case 64:
++		case 104:
++		case 112:
++		case 120:
++		case 128:
++		case 136:
++		case 144:
++		case 153:
++		case 161:
++		case 169:
++		case 177:
++			offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++			break;
++		default:
++			valid = 0;
++			break;
++		}
++	} else
++		valid = 0;
++
++exit:
++	if (valid && r_offset)
++		*r_offset = offset;
++	return valid;
++}
++
++u8 rtw_get_center_ch(u8 ch, u8 bw, u8 offset)
++{
++	u8 cch = ch;
++
++	if (bw == CHANNEL_WIDTH_160) {
++		if (ch % 4 == 0) {
++			if (ch >= 36 && ch <= 64)
++				cch = 50;
++			else if (ch >= 100 && ch <= 128)
++				cch = 114;
++		} else if (ch % 4 == 1) {
++			if (ch >= 149 && ch <= 177)
++				cch = 163;
++		}
++
++	} else if (bw == CHANNEL_WIDTH_80) {
++		if (ch <= 14)
++			cch = 7; /* special case for 2.4G */
++		else if (ch % 4 == 0) {
++			if (ch >= 36 && ch <= 48)
++				cch = 42;
++			else if (ch >= 52 && ch <= 64)
++				cch = 58;
++			else if (ch >= 100 && ch <= 112)
++				cch = 106;
++			else if (ch >= 116 && ch <= 128)
++				cch = 122;
++			else if (ch >= 132 && ch <= 144)
++				cch = 138;
++		} else if (ch % 4 == 1) {
++			if (ch >= 149 && ch <= 161)
++				cch = 155;
++			else if (ch >= 165 && ch <= 177)
++				cch = 171;
++		}
++
++	} else if (bw == CHANNEL_WIDTH_40) {
++		if (offset == HAL_PRIME_CHNL_OFFSET_LOWER)
++			cch = ch + 2;
++		else if (offset == HAL_PRIME_CHNL_OFFSET_UPPER)
++			cch = ch - 2;
++
++	} else if (bw == CHANNEL_WIDTH_20
++		|| bw == CHANNEL_WIDTH_10
++		|| bw == CHANNEL_WIDTH_5
++	)
++		; /* same as ch */
++	else
++		rtw_warn_on(1);
++
++	return cch;
++}
++
++u8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group)
++{
++	BAND_TYPE band = BAND_MAX;
++	s8 gp = -1, cck_gp = -1;
++
++	if (ch <= 14) {
++		band = BAND_ON_2_4G;
++
++		if (1 <= ch && ch <= 2)
++			gp = 0;
++		else if (3  <= ch && ch <= 5)
++			gp = 1;
++		else if (6  <= ch && ch <= 8)
++			gp = 2;
++		else if (9  <= ch && ch <= 11)
++			gp = 3;
++		else if (12 <= ch && ch <= 14)
++			gp = 4;
++		else
++			band = BAND_MAX;
++
++		if (ch == 14)
++			cck_gp = 5;
++		else
++			cck_gp = gp;
++	} else {
++		band = BAND_ON_5G;
++
++		if (36 <= ch && ch <= 42)
++			gp = 0;
++		else if (44   <= ch && ch <=  48)
++			gp = 1;
++		else if (50   <= ch && ch <=  58)
++			gp = 2;
++		else if (60   <= ch && ch <=  64)
++			gp = 3;
++		else if (100  <= ch && ch <= 106)
++			gp = 4;
++		else if (108  <= ch && ch <= 114)
++			gp = 5;
++		else if (116  <= ch && ch <= 122)
++			gp = 6;
++		else if (124  <= ch && ch <= 130)
++			gp = 7;
++		else if (132  <= ch && ch <= 138)
++			gp = 8;
++		else if (140  <= ch && ch <= 144)
++			gp = 9;
++		else if (149  <= ch && ch <= 155)
++			gp = 10;
++		else if (157  <= ch && ch <= 161)
++			gp = 11;
++		else if (165  <= ch && ch <= 171)
++			gp = 12;
++		else if (173  <= ch && ch <= 177)
++			gp = 13;
++		else
++			band = BAND_MAX;
++	}
++
++	if (band == BAND_MAX
++		|| (band == BAND_ON_2_4G && cck_gp == -1)
++		|| gp == -1
++	) {
++		RTW_WARN("%s invalid channel:%u", __func__, ch);
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (group)
++		*group = gp;
++	if (cck_group && band == BAND_ON_2_4G)
++		*cck_group = cck_gp;
++
++exit:
++	return band;
++}
++
++int rtw_ch2freq(int chan)
++{
++	/* see 802.11 17.3.8.3.2 and Annex J
++	* there are overlapping channel numbers in 5GHz and 2GHz bands */
++
++	/*
++	* RTK: don't consider the overlapping channel numbers: 5G channel <= 14,
++	* because we don't support it. simply judge from channel number
++	*/
++
++	if (chan >= 1 && chan <= 14) {
++		if (chan == 14)
++			return 2484;
++		else if (chan < 14)
++			return 2407 + chan * 5;
++	} else if (chan >= 36 && chan <= 177)
++		return 5000 + chan * 5;
++
++	return 0; /* not supported */
++}
++
++int rtw_freq2ch(int freq)
++{
++	/* see 802.11 17.3.8.3.2 and Annex J */
++	if (freq == 2484)
++		return 14;
++	else if (freq < 2484)
++		return (freq - 2407) / 5;
++	else if (freq >= 4910 && freq <= 4980)
++		return (freq - 4000) / 5;
++	else if (freq <= 45000) /* DMG band lower limit */
++		return (freq - 5000) / 5;
++	else if (freq >= 58320 && freq <= 64800)
++		return (freq - 56160) / 2160;
++	else
++		return 0;
++}
++
++bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo)
++{
++	u8 c_ch;
++	u32 freq;
++	u32 hi_ret = 0, lo_ret = 0;
++	bool valid = _FALSE;
++
++	if (hi)
++		*hi = 0;
++	if (lo)
++		*lo = 0;
++
++	c_ch = rtw_get_center_ch(ch, bw, offset);
++	freq = rtw_ch2freq(c_ch);
++
++	if (!freq) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (bw == CHANNEL_WIDTH_160) {
++		hi_ret = freq + 80;
++		lo_ret = freq - 80;
++	} else if (bw == CHANNEL_WIDTH_80) {
++		hi_ret = freq + 40;
++		lo_ret = freq - 40;
++	} else if (bw == CHANNEL_WIDTH_40) {
++		hi_ret = freq + 20;
++		lo_ret = freq - 20;
++	} else if (bw == CHANNEL_WIDTH_20) {
++		hi_ret = freq + 10;
++		lo_ret = freq - 10;
++	} else
++		rtw_warn_on(1);
++
++	if (hi)
++		*hi = hi_ret;
++	if (lo)
++		*lo = lo_ret;
++
++	valid = _TRUE;
++
++exit:
++	return valid;
++}
++
++const char *const _ch_width_str[CHANNEL_WIDTH_MAX] = {
++	"20MHz",
++	"40MHz",
++	"80MHz",
++	"160MHz",
++	"80_80MHz",
++	"5MHz",
++	"10MHz",
++};
++
++const u8 _ch_width_to_bw_cap[CHANNEL_WIDTH_MAX] = {
++	BW_CAP_20M,
++	BW_CAP_40M,
++	BW_CAP_80M,
++	BW_CAP_160M,
++	BW_CAP_80_80M,
++	BW_CAP_5M,
++	BW_CAP_10M,
++};
++
++const char *const _band_str[] = {
++	"2.4G",
++	"5G",
++	"BAND_MAX",
++};
++
++const u8 _band_to_band_cap[] = {
++	BAND_CAP_2G,
++	BAND_CAP_5G,
++	0,
++};
++
++const char *const _opc_bw_str[OPC_BW_NUM] = {
++	"20M ",		/* OPC_BW20 */
++	"40M+",		/* OPC_BW40PLUS */
++	"40M-",		/* OPC_BW40MINUS */
++	"80M ",		/* OPC_BW80 */
++	"160M ",	/* OPC_BW160 */
++	"80+80M ",	/* OPC_BW80P80 */
++};
++
++const u8 _opc_bw_to_ch_width[OPC_BW_NUM] = {
++	CHANNEL_WIDTH_20,		/* OPC_BW20 */
++	CHANNEL_WIDTH_40,		/* OPC_BW40PLUS */
++	CHANNEL_WIDTH_40,		/* OPC_BW40MINUS */
++	CHANNEL_WIDTH_80,		/* OPC_BW80 */
++	CHANNEL_WIDTH_160,		/* OPC_BW160 */
++	CHANNEL_WIDTH_80_80,	/* OPC_BW80P80 */
++};
++
++/* 802.11-2016 Table E-4, partial */
++static const struct op_class_map global_op_class[RTW_GLOBAL_OP_CLASS_NUM] = {
++	/* 2G ch1~13, 20M */
++	{81,	BAND_ON_2_4G,	OPC_BW20,		0x00001FFF},
++	/* 2G ch14, 20M */
++	{82,	BAND_ON_2_4G,	OPC_BW20,		0x00002000},
++	/* 2G, 40M */
++	{83,	BAND_ON_2_4G,	OPC_BW40PLUS,	0x000001FF},
++	{84,	BAND_ON_2_4G,	OPC_BW40MINUS,	0x00001FF0},
++	/* 5G band 1, 20M & 40M */
++	{115,	BAND_ON_5G,		OPC_BW20,		0x0000000F},
++	{116,	BAND_ON_5G,		OPC_BW40PLUS,	0x00000005},
++	{117,	BAND_ON_5G,		OPC_BW40MINUS,	0x0000000A},
++	/* 5G band 2, 20M & 40M */
++	{118,	BAND_ON_5G,		OPC_BW20,		0x000000F0},
++	{119,	BAND_ON_5G,		OPC_BW40PLUS,	0x00000050},
++	{120,	BAND_ON_5G,		OPC_BW40MINUS,	0x000000A0},
++	/* 5G band 3, 20M & 40M */
++	{121,	BAND_ON_5G,		OPC_BW20,		0x000FFF00},
++	{122,	BAND_ON_5G,		OPC_BW40PLUS,	0x00055500},
++	{123,	BAND_ON_5G,		OPC_BW40MINUS,	0x000AAA00},
++	/* 5G band 4, 20M & 40M */
++	{124,	BAND_ON_5G,		OPC_BW20,		0x00F00000},
++	{125,	BAND_ON_5G,		OPC_BW20,		0x03F00000},
++	{126,	BAND_ON_5G,		OPC_BW40PLUS,	0x00500000},
++	{127,	BAND_ON_5G,		OPC_BW40MINUS,	0x00A00000},
++	/* 5G, 80M & 160M */
++	{128,	BAND_ON_5G,		OPC_BW80,		0x00FFFFFF},
++	{129,	BAND_ON_5G,		OPC_BW160,		0x0000FFFF},
++	#if 0 /* TODO */
++	/* 5G, 80+80M */
++	{130,	BAND_ON_5G,		OPC_BW80P80,	0x0FFFFFF},
++	#endif
++};
++
++static u8 global_op_class_get_ch(u8 gid, u8 cid)
++{
++	if (global_op_class[gid].band == BAND_ON_2_4G)
++		return center_ch_2g[cid];
++	if (global_op_class[gid].band == BAND_ON_5G)
++		return center_ch_5g_20m[cid];
++
++	return 0;
++}
++
++static u8 global_op_class_get_cid(u8 gid, u8 ch)
++{
++	if (global_op_class[gid].band == BAND_ON_2_4G)
++		return ch_to_cch_2g_idx(ch);
++	else if (global_op_class[gid].band == BAND_ON_5G)
++		return ch_to_cch_5g_20m_idx(ch);
++
++	return 255;
++}
++
++static void dump_op_class_ch_title(void *sel)
++{
++	RTW_PRINT_SEL(sel, "%-5s %-4s %-7s ch_list\n"
++		, "class", "band", "bw");
++}
++
++static void dump_op_class_ch_single(void *sel, u8 gid, u32 ch_bmp, bool negtive)
++{
++	u8 i;
++	u8 ch;
++
++	RTW_PRINT_SEL(sel, "%5u %4s %7s"
++		, global_op_class[gid].op_class
++		, band_str(global_op_class[gid].band)
++		, opc_bw_str(global_op_class[gid].bw)
++	);
++
++	if ((ch_bmp | global_op_class[gid].ch_bmp) != global_op_class[gid].ch_bmp) {
++		RTW_WARN("invalid ch_map:0x%x of global op_class:%u", ch_bmp, global_op_class[gid].op_class);
++		rtw_warn_on(1);
++	}
++
++	ch_bmp &= global_op_class[gid].ch_bmp;
++	if (negtive)
++		ch_bmp = (~ch_bmp) & global_op_class[gid].ch_bmp;
++
++	for (i = 0; i < 32; i++) {
++		if (!(ch_bmp & BIT(i)))
++			continue;
++
++		ch = global_op_class_get_ch(gid, i);
++		if (!ch) {
++			rtw_warn_on(1);
++			continue;
++		}
++
++		_RTW_PRINT_SEL(sel, " %u", ch);
++	}
++
++	_RTW_PRINT_SEL(sel, "\n");
++}
++
++void dump_global_op_class(void *sel)
++{
++	u8 i;
++
++	dump_op_class_ch_title(sel);
++
++	for (i = 0; i < RTW_GLOBAL_OP_CLASS_NUM; i++)
++		dump_op_class_ch_single(sel, i, global_op_class[i].ch_bmp, 0);
++}
++
++u8 rtw_get_op_class_by_chbw(u8 ch, u8 bw, u8 offset)
++{
++	BAND_TYPE band = BAND_MAX;
++	int i, j;
++	u8 op_class = 0; /* invalid */
++
++	if (rtw_is_2g_ch(ch))
++		band = BAND_ON_2_4G;
++	else if (rtw_is_5g_ch(ch))
++		band = BAND_ON_5G;
++	else
++		goto exit;
++
++	switch (bw) {
++	case CHANNEL_WIDTH_20:
++	case CHANNEL_WIDTH_40:
++	case CHANNEL_WIDTH_80:
++	case CHANNEL_WIDTH_160:
++	#if 0 /* TODO */
++	case CHANNEL_WIDTH_80_80:
++	#endif
++		break;
++	default:
++		goto exit;
++	}
++
++	for (i = 0; i < RTW_GLOBAL_OP_CLASS_NUM; i++) {
++		if (band != global_op_class[i].band)
++			continue;
++
++		if (opc_bw_to_ch_width(global_op_class[i].bw) != bw)
++			continue;
++
++		if ((global_op_class[i].bw == OPC_BW40PLUS
++				&& offset != HAL_PRIME_CHNL_OFFSET_LOWER)
++			|| (global_op_class[i].bw == OPC_BW40MINUS
++				&& offset != HAL_PRIME_CHNL_OFFSET_UPPER)
++		)
++			continue;
++
++		for (j = 0; j < 32; j++) {
++			if (!(global_op_class[i].ch_bmp & BIT(j)))
++				continue;
++			if (ch == global_op_class_get_ch(i, j))
++				goto get;
++		}
++	}
++
++get:
++	if (i < RTW_GLOBAL_OP_CLASS_NUM) {
++		#if 0 /* TODO */
++		if (bw == CHANNEL_WIDTH_80_80) {
++			/* search another ch */
++			u8 k;
++
++			for (k = 0; k < 32; k++) {
++				if (k == j || !(global_op_class[i].ch_bmp & BIT(k)))
++					continue;
++				if (ch2 == global_op_class_get_ch(i, k))
++					break;
++			}
++
++			if (k >= 32)
++				goto exit;
++		}
++		#endif
++
++		op_class = global_op_class[i].op_class;
++	}
++
++exit:
++	return op_class;
++}
++
++u8 rtw_get_bw_offset_by_op_class_ch(u8 op_class, u8 ch, u8 *bw, u8 *offset)
++{
++	u8 valid = 0;
++	int i;
++
++	for (i = 0; i < RTW_GLOBAL_OP_CLASS_NUM; i++) {
++		if (global_op_class[i].op_class != op_class)
++			continue;
++	}
++
++	if (i >= RTW_GLOBAL_OP_CLASS_NUM)
++		goto exit;
++
++	*bw = opc_bw_to_ch_width(global_op_class[i].bw);
++
++	if (global_op_class[i].bw == OPC_BW40PLUS)
++		*offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++	else if (global_op_class[i].bw == OPC_BW40MINUS)
++		*offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++
++	if (rtw_get_offset_by_chbw(ch, *bw, offset))
++		valid = 1;
++
++exit:
++	return valid;
++}
++
++/*
++* @chset: if specified, init op_class_ch_bmp to fit in current channel plan
++*             if not, init, only according to capability setting
++*/
++u8 init_op_class_ch_bmp(_adapter *adapter, RT_CHANNEL_INFO *chset, u32 op_class_ch_bmp[])
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	struct registry_priv *regsty = adapter_to_regsty(adapter);
++	u8 ch, bw, offset, pre_cch, cch;
++	int i, j;
++	u8 op_class_num = 0;
++	u8 band_bmp = 0;
++	u8 bw_bmp[BAND_MAX] = {0};
++	u32 tmp_ch_bmp;
++
++	if (IsSupported24G(regsty->wireless_mode) && hal_chk_band_cap(adapter, BAND_CAP_2G))
++		band_bmp |= BAND_CAP_2G;
++	if (is_supported_5g(regsty->wireless_mode) && hal_chk_band_cap(adapter, BAND_CAP_5G))
++		band_bmp |= BAND_CAP_5G;
++
++	bw_bmp[BAND_ON_2_4G] = (ch_width_to_bw_cap(REGSTY_BW_2G(regsty) + 1) - 1) & (GET_HAL_SPEC(adapter)->bw_cap);
++	bw_bmp[BAND_ON_5G] = (ch_width_to_bw_cap(REGSTY_BW_5G(regsty) + 1) - 1) & (GET_HAL_SPEC(adapter)->bw_cap);
++	if (!REGSTY_IS_11AC_ENABLE(regsty)
++		|| !is_supported_vht(regsty->wireless_mode)
++		|| (chset && rfctl->country_ent && !COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
++	)
++		bw_bmp[BAND_ON_5G] &= ~(BW_CAP_80M | BW_CAP_160M);
++
++	if (0) {
++		RTW_INFO("REGSTY_BW_2G(regsty):%u\n", REGSTY_BW_2G(regsty));
++		RTW_INFO("REGSTY_BW_5G(regsty):%u\n", REGSTY_BW_5G(regsty));
++		RTW_INFO("GET_HAL_SPEC(adapter)->bw_cap:0x%x\n", GET_HAL_SPEC(adapter)->bw_cap);
++		RTW_INFO("band_bmp:0x%x\n", band_bmp);
++		RTW_INFO("bw_bmp[2G]:0x%x\n", bw_bmp[BAND_ON_2_4G]);
++		RTW_INFO("bw_bmp[5G]:0x%x\n", bw_bmp[BAND_ON_5G]);
++	}
++
++	for (i = 0; i < RTW_GLOBAL_OP_CLASS_NUM; i++) {
++		tmp_ch_bmp = 0;
++
++		if (!(band_bmp & band_to_band_cap(global_op_class[i].band)))
++			goto assign_ch_bmp;
++
++		switch (global_op_class[i].bw) {
++		case OPC_BW20:
++			bw = CHANNEL_WIDTH_20;
++			offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++			break;
++		case OPC_BW40PLUS:
++			bw = CHANNEL_WIDTH_40;
++			offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++			break;
++		case OPC_BW40MINUS:
++			bw = CHANNEL_WIDTH_40;
++			offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++			break;
++		case OPC_BW80:
++			bw = CHANNEL_WIDTH_80;
++			offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++			break;
++		case OPC_BW160:
++			bw = CHANNEL_WIDTH_160;
++			offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++			break;
++		case OPC_BW80P80: /* TODO */
++		default:
++			goto assign_ch_bmp;
++		}
++
++		if (!(bw_bmp[global_op_class[i].band] & ch_width_to_bw_cap(bw)))
++			goto assign_ch_bmp;
++
++		pre_cch = 0;
++		for (j = 0; j < 32; j++) {
++			u8 *op_chs;
++			u8 op_ch_num;
++			u8 k;
++			int chset_idx;
++
++			if (!(global_op_class[i].ch_bmp & BIT(j)))
++				continue;
++
++			ch = global_op_class_get_ch(i, j);
++			cch = rtw_get_center_ch(ch ,bw, offset);
++			/* bypass invalid or the same with previous one(already cheked) */
++			if (!cch || cch == pre_cch)
++				continue;
++			pre_cch = cch;
++
++			if (!rtw_get_op_chs_by_cch_bw(cch, bw, &op_chs, &op_ch_num))
++				continue;
++
++			for (k = 0; k < op_ch_num; k++) {
++				if ((offset == HAL_PRIME_CHNL_OFFSET_LOWER
++						&& *(op_chs + k) > cch)
++					|| (offset == HAL_PRIME_CHNL_OFFSET_UPPER
++						&& *(op_chs + k) < cch))
++					continue;
++				if (chset) {
++					chset_idx = rtw_chset_search_ch(chset, *(op_chs + k));
++					if (chset_idx == -1)
++						break;
++				}
++
++				if (chset) {
++					if (chset[chset_idx].dfs && rtw_rfctl_dfs_domain_unknown(rfctl))
++						break;
++					if (chset[chset_idx].ScanType == SCAN_PASSIVE)
++						break;
++				}
++			}
++			if (k < op_ch_num) /* not all op_chs are usable */
++				continue;
++
++			for (k = 0; k < op_ch_num; k++) {
++				if ((offset == HAL_PRIME_CHNL_OFFSET_LOWER
++						&& *(op_chs + k) > cch)
++					|| (offset == HAL_PRIME_CHNL_OFFSET_UPPER
++						&& *(op_chs + k) < cch))
++					continue;
++				tmp_ch_bmp |= BIT(global_op_class_get_cid(i, *(op_chs + k)));
++			}
++		}
++
++assign_ch_bmp:
++		op_class_ch_bmp[i] = tmp_ch_bmp;
++
++		if (op_class_ch_bmp[i])
++			op_class_num++;
++	}
++
++	return op_class_num;
++}
++
++void dump_cap_spt_op_class_ch(void *sel, struct rf_ctl_t *rfctl, bool negtive)
++{
++	u8 i;
++
++	dump_op_class_ch_title(sel);
++
++	for (i = 0; i < RTW_GLOBAL_OP_CLASS_NUM; i++) {
++		if (!rfctl->cap_spt_op_class_ch_bmp[i])
++			continue;
++		dump_op_class_ch_single(sel, i, rfctl->cap_spt_op_class_ch_bmp[i], negtive);
++	}
++
++	RTW_PRINT_SEL(sel, "supported op_class number:%d\n", rfctl->cap_spt_op_class_num);
++}
++
++void dump_cur_spt_op_class_ch(void *sel, struct rf_ctl_t *rfctl, bool negtive)
++{
++	u8 i;
++
++	dump_op_class_ch_title(sel);
++
++	for (i = 0; i < RTW_GLOBAL_OP_CLASS_NUM; i++) {
++		if (!rfctl->cur_spt_op_class_ch_bmp[i])
++			continue;
++		dump_op_class_ch_single(sel, i, rfctl->cur_spt_op_class_ch_bmp[i], negtive);
++	}
++
++	RTW_PRINT_SEL(sel, "supported op_class number:%d\n", rfctl->cur_spt_op_class_num);
++}
++
++const u8 _rf_type_to_rf_tx_cnt[RF_TYPE_MAX] = {
++	1, /* RF_1T1R */
++	1, /* RF_1T2R */
++	2, /* RF_2T1R */
++	2, /* RF_2T2R */
++	1, /* RF_1T3R */
++	2, /* RF_2T3R */
++	3, /* RF_3T1R */
++	3, /* RF_3T2R */
++	3, /* RF_3T3R */
++	1, /* RF_1T4R */
++	2, /* RF_2T4R */
++	3, /* RF_3T4R */
++	4, /* RF_4T1R */
++	4, /* RF_4T2R */
++	4, /* RF_4T3R */
++	4, /* RF_4T4R */
++};
++
++const u8 _rf_type_to_rf_rx_cnt[RF_TYPE_MAX] = {
++	1, /* RF_1T1R */
++	2, /* RF_1T2R */
++	1, /* RF_2T1R */
++	2, /* RF_2T2R */
++	3, /* RF_1T3R */
++	3, /* RF_2T3R */
++	1, /* RF_3T1R */
++	2, /* RF_3T2R */
++	3, /* RF_3T3R */
++	4, /* RF_1T4R */
++	4, /* RF_2T4R */
++	4, /* RF_3T4R */
++	1, /* RF_4T1R */
++	2, /* RF_4T2R */
++	3, /* RF_4T3R */
++	4, /* RF_4T4R */
++};
++
++const char *const _rf_type_to_rfpath_str[RF_TYPE_MAX] = {
++	"RF_1T1R",		/* RF_1T1R */
++	"RF_1T2R",		/* RF_1T2R */
++	"RF_2T1R",		/* RF_2T1R */
++	"RF_2T2R",		/* RF_2T2R */
++	"RF_1T3R",		/* RF_1T3R */
++	"RF_2T3R",		/* RF_2T3R */
++	"RF_3T1R",		/* RF_3T1R */
++	"RF_3T2R",		/* RF_3T2R */
++	"RF_3T3R",		/* RF_3T3R */
++	"RF_1T4R",		/* RF_1T4R */
++	"RF_2T4R",		/* RF_2T4R */
++	"RF_3T4R",		/* RF_3T4R */
++	"RF_4T1R",		/* RF_4T1R */
++	"RF_4T2R",		/* RF_4T2R */
++	"RF_4T3R",		/* RF_4T3R */
++	"RF_4T4R",		/* RF_4T4R */
++};
++
++void rf_type_to_default_trx_bmp(enum rf_type rf, enum bb_path *tx, enum bb_path *rx)
++{
++	u8 tx_num = rf_type_to_rf_tx_cnt(rf);
++	u8 rx_num = rf_type_to_rf_rx_cnt(rf);
++	int i;
++
++	*tx = *rx = 0;
++
++	for (i = 0; i < tx_num; i++)
++		*tx |= BIT(i);
++	for (i = 0; i < rx_num; i++)
++		*rx |= BIT(i);
++}
++
++static const u8 _trx_num_to_rf_type[RF_PATH_MAX][RF_PATH_MAX] = {
++	{RF_1T1R,	RF_1T2R,	RF_1T3R,	RF_1T4R},
++	{RF_2T1R,	RF_2T2R,	RF_2T3R,	RF_2T4R},
++	{RF_3T1R,	RF_3T2R,	RF_3T3R,	RF_3T4R},
++	{RF_4T1R,	RF_4T2R,	RF_4T3R,	RF_4T4R},
++};
++
++enum rf_type trx_num_to_rf_type(u8 tx_num, u8 rx_num)
++{
++	if (tx_num > 0 && tx_num <= RF_PATH_MAX && rx_num > 0 && rx_num <= RF_PATH_MAX)
++		return _trx_num_to_rf_type[tx_num - 1][rx_num - 1];
++	return RF_TYPE_MAX;
++}
++
++enum rf_type trx_bmp_to_rf_type(u8 tx_bmp, u8 rx_bmp)
++{
++	u8 tx_num = 0;
++	u8 rx_num = 0;
++	int i;
++
++	for (i = 0; i < RF_PATH_MAX; i++) {
++		if (tx_bmp >> i & BIT0)
++			tx_num++;
++		if (rx_bmp >> i & BIT0)
++			rx_num++;
++	}
++
++	return trx_num_to_rf_type(tx_num, rx_num);
++}
++
++bool rf_type_is_a_in_b(enum rf_type a, enum rf_type b)
++{
++	return rf_type_to_rf_tx_cnt(a) <= rf_type_to_rf_tx_cnt(b)
++		&& rf_type_to_rf_rx_cnt(a) <= rf_type_to_rf_rx_cnt(b);
++}
++
++static void rtw_path_bmp_limit_from_higher(u8 *bmp, u8 *bmp_bit_cnt, u8 bit_cnt_lmt)
++{
++	int i;
++
++	for (i = RF_PATH_MAX - 1; *bmp_bit_cnt > bit_cnt_lmt && i >= 0; i--) {
++		if (*bmp & BIT(i)) {
++			*bmp &= ~BIT(i);
++			(*bmp_bit_cnt)--;
++		}
++	}
++}
++
++u8 rtw_restrict_trx_path_bmp_by_trx_num_lmt(u8 trx_path_bmp, u8 tx_num_lmt, u8 rx_num_lmt, u8 *tx_num, u8 *rx_num)
++{
++	u8 bmp_tx = (trx_path_bmp & 0xF0) >> 4;
++	u8 bmp_rx = trx_path_bmp & 0x0F;
++	u8 bmp_tx_num = 0, bmp_rx_num = 0;
++	enum rf_type ret_type = RF_TYPE_MAX;
++	int i, j;
++
++	for (i = 0; i < RF_PATH_MAX; i++) {
++		if (bmp_tx & BIT(i))
++			bmp_tx_num++;
++		if (bmp_rx & BIT(i))
++			bmp_rx_num++;
++	}
++
++	/* limit higher bit first according to input type */
++	if (tx_num_lmt)
++		rtw_path_bmp_limit_from_higher(&bmp_tx, &bmp_tx_num, tx_num_lmt);
++	if (rx_num_lmt)
++		rtw_path_bmp_limit_from_higher(&bmp_rx, &bmp_rx_num, rx_num_lmt);
++
++	/* search for valid rf_type (larger RX prefer) */
++	for (j = bmp_rx_num; j > 0; j--) {
++		for (i = bmp_tx_num; i > 0; i--) {
++			ret_type = trx_num_to_rf_type(i, j);
++			if (RF_TYPE_VALID(ret_type)) {
++				rtw_path_bmp_limit_from_higher(&bmp_tx, &bmp_tx_num, i);
++				rtw_path_bmp_limit_from_higher(&bmp_rx, &bmp_rx_num, j);
++				if (tx_num)
++					*tx_num = bmp_tx_num;
++				if (rx_num)
++					*rx_num = bmp_rx_num;
++				goto exit;
++			}
++		}
++	}
++
++exit:
++	return RF_TYPE_VALID(ret_type) ? ((bmp_tx << 4) | bmp_rx) : 0x00;
++}
++
++u8 rtw_restrict_trx_path_bmp_by_rftype(u8 trx_path_bmp, enum rf_type type, u8 *tx_num, u8 *rx_num)
++{
++	return rtw_restrict_trx_path_bmp_by_trx_num_lmt(trx_path_bmp
++		, rf_type_to_rf_tx_cnt(type), rf_type_to_rf_rx_cnt(type), tx_num, rx_num);
++}
++
++/* config to non N-TX value, path with lower index prefer */
++void tx_path_nss_set_default(enum bb_path txpath_nss[], u8 txpath_num_nss[], u8 txpath)
++{
++	int i, j;
++	u8 cnt;
++
++	for (i = 4; i > 0; i--) {
++		cnt = 0;
++		txpath_nss[i - 1] = 0;
++		for (j = 0; j < RF_PATH_MAX; j++) {
++			if (txpath & BIT(j)) {
++				txpath_nss[i - 1] |= BIT(j);
++				if (++cnt == i)
++					break;
++			}
++		}
++		txpath_num_nss[i - 1] = i;
++	}
++}
++
++/* config to full N-TX value */
++void tx_path_nss_set_full_tx(enum bb_path txpath_nss[], u8 txpath_num_nss[], u8 txpath)
++{
++	u8 tx_num = 0;
++	int i;
++
++	for (i = 0; i < RF_PATH_MAX; i++)
++		if (txpath & BIT(i))
++			tx_num++;
++
++	for (i = 4; i > 0; i--) {
++		txpath_nss[i - 1] = txpath;
++		txpath_num_nss[i - 1] = tx_num;
++	}
++}
++
++const char *const _regd_str[] = {
++	"NONE",
++	"FCC",
++	"MKK",
++	"ETSI",
++	"IC",
++	"KCC",
++	"ACMA",
++	"CHILE",
++	"UKRAINE",
++	"MEXICO",
++	"CN",
++	"WW",
++};
++
++/*
++* input with txpwr value in unit of txpwr index
++* return string in length 6 at least (for -xx.xx)
++*/
++void txpwr_idx_get_dbm_str(s8 idx, u8 txgi_max, u8 txgi_pdbm, SIZE_T cwidth, char dbm_str[], u8 dbm_str_len)
++{
++	char fmt[16];
++
++	if (idx == txgi_max) {
++		snprintf(fmt, 16, "%%%zus", cwidth >= 6 ? cwidth + 1 : 6);
++		snprintf(dbm_str, dbm_str_len, fmt, "NA");
++	} else if (idx > -txgi_pdbm && idx < 0) { /* -0.xx */
++		snprintf(fmt, 16, "%%%zus-0.%%02d", cwidth >= 6 ? cwidth - 4 : 1);
++		snprintf(dbm_str, dbm_str_len, fmt, "", (rtw_abs(idx) % txgi_pdbm) * 100 / txgi_pdbm);
++	} else if (idx % txgi_pdbm) { /* d.xx */
++		snprintf(fmt, 16, "%%%zud.%%02d", cwidth >= 6 ? cwidth - 2 : 3);
++		snprintf(dbm_str, dbm_str_len, fmt, idx / txgi_pdbm, (rtw_abs(idx) % txgi_pdbm) * 100 / txgi_pdbm);
++	} else { /* d */
++		snprintf(fmt, 16, "%%%zud", cwidth >= 6 ? cwidth + 1 : 6);
++		snprintf(dbm_str, dbm_str_len, fmt, idx / txgi_pdbm);
++	}
++}
++
++/*
++* input with txpwr value in unit of mbm
++* return string in length 6 at least (for -xx.xx)
++*/
++void txpwr_mbm_get_dbm_str(s16 mbm, SIZE_T cwidth, char dbm_str[], u8 dbm_str_len)
++{
++	char fmt[16];
++
++	if (mbm == UNSPECIFIED_MBM) {
++		snprintf(fmt, 16, "%%%zus", cwidth >= 6 ? cwidth + 1 : 6);
++		snprintf(dbm_str, dbm_str_len, fmt, "NA");
++	} else if (mbm > -MBM_PDBM && mbm < 0) { /* -0.xx */
++		snprintf(fmt, 16, "%%%zus-0.%%02d", cwidth >= 6 ? cwidth - 4 : 1);
++		snprintf(dbm_str, dbm_str_len, fmt, "", (rtw_abs(mbm) % MBM_PDBM) * 100 / MBM_PDBM);
++	} else if (mbm % MBM_PDBM) { /* d.xx */
++		snprintf(fmt, 16, "%%%zud.%%02d", cwidth >= 6 ? cwidth - 2 : 3);
++		snprintf(dbm_str, dbm_str_len, fmt, mbm / MBM_PDBM, (rtw_abs(mbm) % MBM_PDBM) * 100 / MBM_PDBM);
++	} else { /* d */
++		snprintf(fmt, 16, "%%%zud", cwidth >= 6 ? cwidth + 1 : 6);
++		snprintf(dbm_str, dbm_str_len, fmt, mbm / MBM_PDBM);
++	}
++}
++
++static const s16 _mb_of_ntx[] = {
++	0,		/* 1TX */
++	301,	/* 2TX */
++	477,	/* 3TX */
++	602,	/* 4TX */
++	699,	/* 5TX */
++	778,	/* 6TX */
++	845,	/* 7TX */
++	903,	/* 8TX */
++};
++
++/* get mB(100 *dB) for specifc TX count relative to 1TX */
++s16 mb_of_ntx(u8 ntx)
++{
++	if (ntx == 0 || ntx > 8) {
++		RTW_ERR("ntx=%u, out of range\n", ntx);
++		rtw_warn_on(1);
++	}
++
++	return _mb_of_ntx[ntx - 1];
++}
++
++#if CONFIG_TXPWR_LIMIT
++void _dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl)
++{
++	struct regd_exc_ent *ent;
++	_list *cur, *head;
++
++	RTW_PRINT_SEL(sel, "regd_exc_num:%u\n", rfctl->regd_exc_num);
++
++	if (!rfctl->regd_exc_num)
++		goto exit;
++
++	RTW_PRINT_SEL(sel, "%-7s %-6s %-9s\n", "country", "domain", "regd_name");
++
++	head = &rfctl->reg_exc_list;
++	cur = get_next(head);
++
++	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
++		u8 has_country;
++
++		ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);
++		cur = get_next(cur);
++		has_country = (ent->country[0] == '\0' && ent->country[1] == '\0') ? 0 : 1;
++
++		RTW_PRINT_SEL(sel, "     %c%c   0x%02x %s\n"
++			, has_country ? ent->country[0] : '0'
++			, has_country ? ent->country[1] : '0'
++			, ent->domain
++			, ent->regd_name
++		);
++	}
++
++exit:
++	return;
++}
++
++inline void dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl)
++{
++	_irqL irqL;
++
++	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++	_dump_regd_exc_list(sel, rfctl);
++	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++}
++
++void rtw_regd_exc_add_with_nlen(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name, u32 nlen)
++{
++	struct regd_exc_ent *ent;
++	_irqL irqL;
++
++	if (!regd_name || !nlen) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	ent = (struct regd_exc_ent *)rtw_zmalloc(sizeof(struct regd_exc_ent) + nlen + 1);
++	if (!ent)
++		goto exit;
++
++	_rtw_init_listhead(&ent->list);
++	if (country)
++		_rtw_memcpy(ent->country, country, 2);
++	ent->domain = domain;
++	_rtw_memcpy(ent->regd_name, regd_name, nlen);
++
++	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++
++	rtw_list_insert_tail(&ent->list, &rfctl->reg_exc_list);
++	rfctl->regd_exc_num++;
++
++	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++
++exit:
++	return;
++}
++
++inline void rtw_regd_exc_add(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name)
++{
++	rtw_regd_exc_add_with_nlen(rfctl, country, domain, regd_name, strlen(regd_name));
++}
++
++struct regd_exc_ent *_rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain)
++{
++	struct regd_exc_ent *ent;
++	_list *cur, *head;
++	u8 match = 0;
++
++	head = &rfctl->reg_exc_list;
++	cur = get_next(head);
++
++	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
++		u8 has_country;
++
++		ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);
++		cur = get_next(cur);
++		has_country = (ent->country[0] == '\0' && ent->country[1] == '\0') ? 0 : 1;
++
++		/* entry has country condition to match */
++		if (has_country) {
++			if (!country)
++				continue;
++			if (ent->country[0] != country[0]
++				|| ent->country[1] != country[1])
++				continue;
++		}
++
++		/* entry has domain condition to match */
++		if (ent->domain != 0xFF) {
++			if (domain == 0xFF)
++				continue;
++			if (ent->domain != domain)
++				continue;
++		}
++
++		match = 1;
++		break;
++	}
++
++	if (match)
++		return ent;
++	else
++		return NULL;
++}
++
++inline struct regd_exc_ent *rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain)
++{
++	struct regd_exc_ent *ent;
++	_irqL irqL;
++
++	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++	ent = _rtw_regd_exc_search(rfctl, country, domain);
++	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++
++	return ent;
++}
++
++void rtw_regd_exc_list_free(struct rf_ctl_t *rfctl)
++{
++	struct regd_exc_ent *ent;
++	_irqL irqL;
++	_list *cur, *head;
++
++	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++
++	head = &rfctl->reg_exc_list;
++	cur = get_next(head);
++
++	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
++		ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);
++		cur = get_next(cur);
++		rtw_list_delete(&ent->list);
++		rtw_mfree((u8 *)ent, sizeof(struct regd_exc_ent) + strlen(ent->regd_name) + 1);
++	}
++	rfctl->regd_exc_num = 0;
++
++	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++}
++
++void dump_txpwr_lmt(void *sel, _adapter *adapter)
++{
++#define TMP_STR_LEN 16
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	_irqL irqL;
++	char fmt[16];
++	char tmp_str[TMP_STR_LEN];
++	s8 *lmt_idx = NULL;
++	int bw, band, ch_num, tlrs, ntx_idx, rs, i, path;
++	u8 ch, n, rfpath_num;
++
++	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++
++	_dump_regd_exc_list(sel, rfctl);
++	RTW_PRINT_SEL(sel, "\n");
++
++	if (!rfctl->txpwr_regd_num)
++		goto release_lock;
++
++	lmt_idx = rtw_malloc(sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num);
++	if (!lmt_idx) {
++		RTW_ERR("%s alloc fail\n", __func__);
++		goto release_lock;
++	}
++
++	RTW_PRINT_SEL(sel, "txpwr_lmt_2g_cck_ofdm_state:0x%02x\n", rfctl->txpwr_lmt_2g_cck_ofdm_state);
++	#if CONFIG_IEEE80211_BAND_5GHZ
++	if (IS_HARDWARE_TYPE_JAGUAR_ALL(adapter)) {
++		RTW_PRINT_SEL(sel, "txpwr_lmt_5g_cck_ofdm_state:0x%02x\n", rfctl->txpwr_lmt_5g_cck_ofdm_state);
++		RTW_PRINT_SEL(sel, "txpwr_lmt_5g_20_40_ref:0x%02x\n", rfctl->txpwr_lmt_5g_20_40_ref);
++	}
++	#endif
++	RTW_PRINT_SEL(sel, "\n");
++
++	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
++		if (!hal_is_band_support(adapter, band))
++			continue;
++
++		rfpath_num = (band == BAND_ON_2_4G ? hal_spec->rfpath_num_2g : hal_spec->rfpath_num_5g);
++
++		for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; bw++) {
++
++			if (bw >= CHANNEL_WIDTH_160)
++				break;
++			if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80)
++				break;
++
++			if (band == BAND_ON_2_4G)
++				ch_num = CENTER_CH_2G_NUM;
++			else
++				ch_num = center_chs_5g_num(bw);
++
++			if (ch_num == 0) {
++				rtw_warn_on(1);
++				break;
++			}
++
++			for (tlrs = TXPWR_LMT_RS_CCK; tlrs < TXPWR_LMT_RS_NUM; tlrs++) {
++
++				if (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT)
++					continue;
++				if (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK)
++					continue;
++				if (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM))
++					continue;
++				if (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT)
++					continue;
++				if (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
++					continue;
++
++				for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
++					struct txpwr_lmt_ent *ent;
++					_list *cur, *head;
++
++					if (ntx_idx + 1 > hal_data->max_tx_cnt)
++						continue;
++
++					/* bypass CCK multi-TX is not defined */
++					if (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) {
++						if (band == BAND_ON_2_4G
++							&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx)))
++							continue;
++					}
++
++					/* bypass OFDM multi-TX is not defined */
++					if (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) {
++						if (band == BAND_ON_2_4G
++							&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
++							continue;
++						#if CONFIG_IEEE80211_BAND_5GHZ
++						if (band == BAND_ON_5G
++							&& !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
++							continue;
++						#endif
++					}
++
++					/* bypass 5G 20M, 40M pure reference */
++					#if CONFIG_IEEE80211_BAND_5GHZ
++					if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) {
++						if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) {
++							if (tlrs == TXPWR_LMT_RS_HT)
++								continue;
++						} else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) {
++							if (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40)
++								continue;
++						}
++					}
++					#endif
++
++					/* choose n-SS mapping rate section to get lmt diff value */
++					if (tlrs == TXPWR_LMT_RS_CCK)
++						rs = CCK;
++					else if (tlrs == TXPWR_LMT_RS_OFDM)
++						rs = OFDM;
++					else if (tlrs == TXPWR_LMT_RS_HT)
++						rs = HT_1SS + ntx_idx;
++					else if (tlrs == TXPWR_LMT_RS_VHT)
++						rs = VHT_1SS + ntx_idx;
++					else {
++						RTW_ERR("%s invalid tlrs %u\n", __func__, tlrs);
++						continue;
++					}
++
++					RTW_PRINT_SEL(sel, "[%s][%s][%s][%uT]\n"
++						, band_str(band)
++						, ch_width_str(bw)
++						, txpwr_lmt_rs_str(tlrs)
++						, ntx_idx + 1
++					);
++
++					/* header for limit in db */
++					RTW_PRINT_SEL(sel, "%3s ", "ch");
++
++					head = &rfctl->txpwr_lmt_list;
++					cur = get_next(head);
++					while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
++						ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
++						cur = get_next(cur);
++
++						sprintf(fmt, "%%%zus%%s ", strlen(ent->regd_name) >= 6 ? 1 : 6 - strlen(ent->regd_name));
++						snprintf(tmp_str, TMP_STR_LEN, fmt
++							, strcmp(ent->regd_name, rfctl->regd_name) == 0 ? "*" : ""
++							, ent->regd_name);
++						_RTW_PRINT_SEL(sel, "%s", tmp_str);
++					}
++					sprintf(fmt, "%%%zus%%s ", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? 1 : 6 - strlen(regd_str(TXPWR_LMT_WW)));
++					snprintf(tmp_str, TMP_STR_LEN, fmt
++						, strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? "*" : ""
++						, regd_str(TXPWR_LMT_WW));
++					_RTW_PRINT_SEL(sel, "%s", tmp_str);
++
++					/* header for limit offset */
++					for (path = 0; path < RF_PATH_MAX; path++) {
++						if (path >= rfpath_num)
++							break;
++						_RTW_PRINT_SEL(sel, "|");
++						head = &rfctl->txpwr_lmt_list;
++						cur = get_next(head);
++						while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
++							ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
++							cur = get_next(cur);
++							_RTW_PRINT_SEL(sel, "%3c "
++								, strcmp(ent->regd_name, rfctl->regd_name) == 0 ? rf_path_char(path) : ' ');
++						}
++						_RTW_PRINT_SEL(sel, "%3c "
++								, strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? rf_path_char(path) : ' ');
++					}
++					_RTW_PRINT_SEL(sel, "\n");
++
++					for (n = 0; n < ch_num; n++) {
++						s8 lmt;
++						s8 lmt_offset;
++						u8 base;
++
++						if (band == BAND_ON_2_4G)
++							ch = n + 1;
++						else
++							ch = center_chs_5g(bw, n);
++
++						if (ch == 0) {
++							rtw_warn_on(1);
++							break;
++						}
++
++						/* dump limit in dBm */
++						RTW_PRINT_SEL(sel, "%3u ", ch);
++						head = &rfctl->txpwr_lmt_list;
++						cur = get_next(head);
++						while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
++							ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
++							cur = get_next(cur);
++							lmt = phy_get_txpwr_lmt(adapter, ent->regd_name, band, bw, tlrs, ntx_idx, ch, 0);
++							txpwr_idx_get_dbm_str(lmt, hal_spec->txgi_max, hal_spec->txgi_pdbm, strlen(ent->regd_name), tmp_str, TMP_STR_LEN);
++							_RTW_PRINT_SEL(sel, "%s ", tmp_str);
++						}
++						lmt = phy_get_txpwr_lmt(adapter, regd_str(TXPWR_LMT_WW), band, bw, tlrs, ntx_idx, ch, 0);
++						txpwr_idx_get_dbm_str(lmt, hal_spec->txgi_max, hal_spec->txgi_pdbm, strlen(regd_str(TXPWR_LMT_WW)), tmp_str, TMP_STR_LEN);
++						_RTW_PRINT_SEL(sel, "%s ", tmp_str);
++
++						/* dump limit offset of each path */
++						for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
++							if (path >= rfpath_num)
++								break;
++
++							base = phy_get_target_txpwr(adapter, band, path, rs);
++
++							_RTW_PRINT_SEL(sel, "|");
++							head = &rfctl->txpwr_lmt_list;
++							cur = get_next(head);
++							i = 0;
++							while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
++								ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
++								cur = get_next(cur);
++								lmt_offset = phy_get_txpwr_lmt_diff(adapter, ent->regd_name, band, bw, path, rs, tlrs, ntx_idx, ch, 0);
++								if (lmt_offset == hal_spec->txgi_max) {
++									*(lmt_idx + i * RF_PATH_MAX + path) = hal_spec->txgi_max;
++									_RTW_PRINT_SEL(sel, "%3s ", "NA");
++								} else {
++									*(lmt_idx + i * RF_PATH_MAX + path) = lmt_offset + base;
++									_RTW_PRINT_SEL(sel, "%3d ", lmt_offset);
++								}
++								i++;
++							}
++							lmt_offset = phy_get_txpwr_lmt_diff(adapter, regd_str(TXPWR_LMT_WW), band, bw, path, rs, tlrs, ntx_idx, ch, 0);
++							if (lmt_offset == hal_spec->txgi_max)
++								_RTW_PRINT_SEL(sel, "%3s ", "NA");
++							else
++								_RTW_PRINT_SEL(sel, "%3d ", lmt_offset);
++
++						}
++
++						/* compare limit_idx of each path, print 'x' when mismatch */
++						if (rfpath_num > 1) {
++							for (i = 0; i < rfctl->txpwr_regd_num; i++) {
++								for (path = 0; path < RF_PATH_MAX; path++) {
++									if (path >= rfpath_num)
++										break;
++									if (*(lmt_idx + i * RF_PATH_MAX + path) != *(lmt_idx + i * RF_PATH_MAX + ((path + 1) % rfpath_num)))
++										break;
++								}
++								if (path >= rfpath_num)
++									_RTW_PRINT_SEL(sel, " ");
++								else
++									_RTW_PRINT_SEL(sel, "x");
++							}
++						}
++						_RTW_PRINT_SEL(sel, "\n");
++
++					}
++					RTW_PRINT_SEL(sel, "\n");
++				}
++			} /* loop for rate sections */
++		} /* loop for bandwidths */
++	} /* loop for bands */
++
++	if (lmt_idx)
++		rtw_mfree(lmt_idx, sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num);
++
++release_lock:
++	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++}
++
++/* search matcing first, if not found, alloc one */
++void rtw_txpwr_lmt_add_with_nlen(struct rf_ctl_t *rfctl, const char *regd_name, u32 nlen
++	, u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(dvobj_get_primary_adapter(rfctl_to_dvobj(rfctl)));
++	struct txpwr_lmt_ent *ent;
++	_irqL irqL;
++	_list *cur, *head;
++	s8 pre_lmt;
++
++	if (!regd_name || !nlen) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++
++	/* search for existed entry */
++	head = &rfctl->txpwr_lmt_list;
++	cur = get_next(head);
++	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
++		ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
++		cur = get_next(cur);
++
++		if (strlen(ent->regd_name) == nlen
++			&& _rtw_memcmp(ent->regd_name, regd_name, nlen) == _TRUE)
++			goto chk_lmt_val;
++	}
++
++	/* alloc new one */
++	ent = (struct txpwr_lmt_ent *)rtw_zvmalloc(sizeof(struct txpwr_lmt_ent) + nlen + 1);
++	if (!ent)
++		goto release_lock;
++
++	_rtw_init_listhead(&ent->list);
++	_rtw_memcpy(ent->regd_name, regd_name, nlen);
++	{
++		u8 j, k, l, m;
++
++		for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j)
++			for (k = 0; k < TXPWR_LMT_RS_NUM_2G; ++k)
++				for (m = 0; m < CENTER_CH_2G_NUM; ++m)
++					for (l = 0; l < MAX_TX_COUNT; ++l)
++						ent->lmt_2g[j][k][m][l] = hal_spec->txgi_max;
++		#if CONFIG_IEEE80211_BAND_5GHZ
++		for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j)
++			for (k = 0; k < TXPWR_LMT_RS_NUM_5G; ++k)
++				for (m = 0; m < CENTER_CH_5G_ALL_NUM; ++m)
++					for (l = 0; l < MAX_TX_COUNT; ++l)
++						ent->lmt_5g[j][k][m][l] = hal_spec->txgi_max;
++		#endif
++	}
++
++	rtw_list_insert_tail(&ent->list, &rfctl->txpwr_lmt_list);
++	rfctl->txpwr_regd_num++;
++
++chk_lmt_val:
++	if (band == BAND_ON_2_4G)
++		pre_lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx];
++	#if CONFIG_IEEE80211_BAND_5GHZ
++	else if (band == BAND_ON_5G)
++		pre_lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx];
++	#endif
++	else
++		goto release_lock;
++
++	if (pre_lmt != hal_spec->txgi_max)
++		RTW_PRINT("duplicate txpwr_lmt for [%s][%s][%s][%s][%uT][%d]\n"
++			, regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1
++			, band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx]);
++
++	lmt = rtw_min(pre_lmt, lmt);
++	if (band == BAND_ON_2_4G)
++		ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] = lmt;
++	#if CONFIG_IEEE80211_BAND_5GHZ
++	else if (band == BAND_ON_5G)
++		ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] = lmt;
++	#endif
++
++	if (0)
++		RTW_PRINT("%s, %4s, %6s, %7s, %uT, ch%3d = %d\n"
++			, regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1
++			, band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx]
++			, lmt);
++
++release_lock:
++	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++
++exit:
++	return;
++}
++
++inline void rtw_txpwr_lmt_add(struct rf_ctl_t *rfctl, const char *regd_name
++	, u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt)
++{
++	rtw_txpwr_lmt_add_with_nlen(rfctl, regd_name, strlen(regd_name)
++		, band, bw, tlrs, ntx_idx, ch_idx, lmt);
++}
++
++struct txpwr_lmt_ent *_rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name)
++{
++	struct txpwr_lmt_ent *ent;
++	_list *cur, *head;
++	u8 found = 0;
++
++	head = &rfctl->txpwr_lmt_list;
++	cur = get_next(head);
++
++	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
++		ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
++		cur = get_next(cur);
++
++		if (strcmp(ent->regd_name, regd_name) == 0) {
++			found = 1;
++			break;
++		}
++	}
++
++	if (found)
++		return ent;
++	return NULL;
++}
++
++inline struct txpwr_lmt_ent *rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name)
++{
++	struct txpwr_lmt_ent *ent;
++	_irqL irqL;
++
++	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++	ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name);
++	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++
++	return ent;
++}
++
++void rtw_txpwr_lmt_list_free(struct rf_ctl_t *rfctl)
++{
++	struct txpwr_lmt_ent *ent;
++	_irqL irqL;
++	_list *cur, *head;
++
++	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++
++	head = &rfctl->txpwr_lmt_list;
++	cur = get_next(head);
++
++	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
++		ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
++		cur = get_next(cur);
++		if (ent->regd_name == rfctl->regd_name)
++			rfctl->regd_name = regd_str(TXPWR_LMT_NONE);
++		rtw_list_delete(&ent->list);
++		rtw_vmfree((u8 *)ent, sizeof(struct txpwr_lmt_ent) + strlen(ent->regd_name) + 1);
++	}
++	rfctl->txpwr_regd_num = 0;
++
++	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++}
++#endif /* CONFIG_TXPWR_LIMIT */
++
++int rtw_ch_to_bb_gain_sel(int ch)
++{
++	int sel = -1;
++
++	if (ch >= 1 && ch <= 14)
++		sel = BB_GAIN_2G;
++#if CONFIG_IEEE80211_BAND_5GHZ
++	else if (ch >= 36 && ch < 48)
++		sel = BB_GAIN_5GLB1;
++	else if (ch >= 52 && ch <= 64)
++		sel = BB_GAIN_5GLB2;
++	else if (ch >= 100 && ch <= 120)
++		sel = BB_GAIN_5GMB1;
++	else if (ch >= 124 && ch <= 144)
++		sel = BB_GAIN_5GMB2;
++	else if (ch >= 149 && ch <= 177)
++		sel = BB_GAIN_5GHB;
++#endif
++
++	return sel;
++}
++
++s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch)
++{
++	s8 kfree_offset = 0;
++
++#ifdef CONFIG_RF_POWER_TRIM
++	struct kfree_data_t *kfree_data = GET_KFREE_DATA(padapter);
++	s8 bb_gain_sel = rtw_ch_to_bb_gain_sel(ch);
++
++	if (bb_gain_sel < BB_GAIN_2G || bb_gain_sel >= BB_GAIN_NUM) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (kfree_data->flag & KFREE_FLAG_ON) {
++		kfree_offset = kfree_data->bb_gain[bb_gain_sel][path];
++		if (IS_HARDWARE_TYPE_8723D(padapter))
++			RTW_INFO("%s path:%s, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n"
++				, __func__, (path == 0)?"S1":"S0", 
++				ch, bb_gain_sel, kfree_offset);
++		else
++			RTW_INFO("%s path:%u, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n"
++				, __func__, path, ch, bb_gain_sel, kfree_offset);
++	}
++exit:
++#endif /* CONFIG_RF_POWER_TRIM */
++	return kfree_offset;
++}
++
++void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset)
++{
++#if !defined(CONFIG_RTL8814A) && !defined(CONFIG_RTL8822B) && !defined(CONFIG_RTL8821C) && !defined(CONFIG_RTL8822C)
++	u8 write_value;
++#endif
++	u8 target_path = 0;
++	u32 val32 = 0;
++
++	if (IS_HARDWARE_TYPE_8723D(adapter)) {
++		target_path = RF_PATH_A; /*in 8723D case path means S0/S1*/
++		if (path == PPG_8723D_S1)
++			RTW_INFO("kfree gain_offset 0x55:0x%x ",
++			rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff));
++		else if (path == PPG_8723D_S0)
++			RTW_INFO("kfree gain_offset 0x65:0x%x ",
++			rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff));
++	} else {
++		target_path = path;
++		RTW_INFO("kfree gain_offset 0x55:0x%x ", rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff));
++	}
++	
++	switch (rtw_get_chip_type(adapter)) {
++#ifdef CONFIG_RTL8723D
++	case RTL8723D:
++		write_value = RF_TX_GAIN_OFFSET_8723D(offset);
++		if (path == PPG_8723D_S1)
++			rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);
++		else if (path == PPG_8723D_S0)
++			rtw_hal_write_rfreg(adapter, target_path, 0x65, 0x0f8000, write_value);
++		break;
++#endif /* CONFIG_RTL8723D */
++#ifdef CONFIG_RTL8703B
++	case RTL8703B:
++		write_value = RF_TX_GAIN_OFFSET_8703B(offset);
++		rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value);
++		break;
++#endif /* CONFIG_RTL8703B */
++#ifdef CONFIG_RTL8188F
++	case RTL8188F:
++		write_value = RF_TX_GAIN_OFFSET_8188F(offset);
++		rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value);
++		break;
++#endif /* CONFIG_RTL8188F */
++#ifdef CONFIG_RTL8188GTV
++	case RTL8188GTV:
++		write_value = RF_TX_GAIN_OFFSET_8188GTV(offset);
++		rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value);
++		break;
++#endif /* CONFIG_RTL8188GTV */
++#ifdef CONFIG_RTL8192E
++	case RTL8192E:
++		write_value = RF_TX_GAIN_OFFSET_8192E(offset);
++		rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);
++		break;
++#endif /* CONFIG_RTL8188F */
++
++#ifdef CONFIG_RTL8821A
++	case RTL8821:
++		write_value = RF_TX_GAIN_OFFSET_8821A(offset);
++		rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);
++		break;
++#endif /* CONFIG_RTL8821A */
++#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822C)
++	case RTL8814A:
++	case RTL8822B:
++	case RTL8822C:	
++	case RTL8821C:
++	case RTL8192F:
++		RTW_INFO("\nkfree by PhyDM on the sw CH. path %d\n", path);
++		break;
++#endif /* CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
++
++	default:
++		rtw_warn_on(1);
++		break;
++	}
++	
++	if (IS_HARDWARE_TYPE_8723D(adapter)) {
++		if (path == PPG_8723D_S1)
++			val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff);
++		else if (path == PPG_8723D_S0)
++			val32 = rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff);
++	} else {
++		val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff);
++	}
++	RTW_INFO(" after :0x%x\n", val32);
++}
++
++void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	s8 kfree_offset = 0;
++	s8 tx_pwr_track_offset = 0; /* TODO: 8814A should consider tx pwr track when setting tx gain offset */
++	s8 total_offset;
++	int i, total = 0;
++
++	if (IS_HARDWARE_TYPE_8723D(adapter))
++		total = 2; /* S1 and S0 */
++	else
++		total = hal_spec->rf_reg_path_num;
++
++	for (i = 0; i < total; i++) {
++		kfree_offset = rtw_rf_get_kfree_tx_gain_offset(adapter, i, ch);
++		total_offset = kfree_offset + tx_pwr_track_offset;
++		rtw_rf_set_tx_gain_offset(adapter, i, total_offset);
++	}
++}
++
++bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region)
++{
++	return (dfs_region == PHYDM_DFS_DOMAIN_ETSI && rtw_is_range_overlap(hi, lo, 5650, 5600)) ? _TRUE : _FALSE;
++}
++
++bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region)
++{
++	u32 hi, lo;
++
++	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
++		return _FALSE;
++
++	return rtw_is_long_cac_range(hi, lo, dfs_region) ? _TRUE : _FALSE;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_rm.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_rm.c
+new file mode 100644
+index 000000000..47a27654a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_rm.c
+@@ -0,0 +1,2471 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <drv_types.h>
++#include <hal_data.h>
++#ifdef CONFIG_RTW_80211K
++#include "rtw_rm_fsm.h"
++#include "rtw_rm_util.h"
++#endif
++
++#define pstr(s) s+strlen(s)
++
++u8 rm_post_event_hdl(_adapter *padapter, u8 *pbuf)
++{
++#ifdef CONFIG_RTW_80211K
++	struct rm_event *pev = (struct rm_event *)pbuf;
++
++	_rm_post_event(padapter, pev->rmid, pev->evid);
++	rm_handler(padapter, pev);
++#endif
++	return H2C_SUCCESS;
++}
++
++#ifdef CONFIG_RTW_80211K
++struct cmd_meas_type_ {
++	u8 id;
++	char *name;
++};
++
++char *rm_type_req_name(u8 meas_type) {
++
++	switch (meas_type) {
++	case basic_req:
++		return "basic_req";
++	case cca_req:
++		return "cca_req";
++	case rpi_histo_req:
++		return "rpi_histo_req";
++	case ch_load_req:
++		return "ch_load_req";
++	case noise_histo_req:
++		return "noise_histo_req";
++	case bcn_req:
++		return "bcn_req";
++	case frame_req:
++		return "frame_req";
++	case sta_statis_req:
++		return "sta_statis_req";
++	}
++	return "unknown_req";
++};
++
++char *rm_type_rep_name(u8 meas_type) {
++
++	switch (meas_type) {
++	case basic_rep:
++		return "basic_rep";
++	case cca_rep:
++		return "cca_rep";
++	case rpi_histo_rep:
++		return "rpi_histo_rep";
++	case ch_load_rep:
++		return "ch_load_rep";
++	case noise_histo_rep:
++		return "noise_histo_rep";
++	case bcn_rep:
++		return "bcn_rep";
++	case frame_rep:
++		return "frame_rep";
++	case sta_statis_rep:
++		return "sta_statis_rep";
++	}
++	return "unknown_rep";
++};
++
++char *rm_en_cap_name(enum rm_cap_en en)
++{
++	switch (en) {
++	case RM_LINK_MEAS_CAP_EN:
++		return "RM_LINK_MEAS_CAP_EN";
++	case RM_NB_REP_CAP_EN:
++		return "RM_NB_REP_CAP_EN";
++	case RM_PARAL_MEAS_CAP_EN:
++		return "RM_PARAL_MEAS_CAP_EN";
++	case RM_REPEAT_MEAS_CAP_EN:
++		return "RM_REPEAT_MEAS_CAP_EN";
++	case RM_BCN_PASSIVE_MEAS_CAP_EN:
++		return "RM_BCN_PASSIVE_MEAS_CAP_EN";
++	case RM_BCN_ACTIVE_MEAS_CAP_EN:
++		return "RM_BCN_ACTIVE_MEAS_CAP_EN";
++	case RM_BCN_TABLE_MEAS_CAP_EN:
++		return "RM_BCN_TABLE_MEAS_CAP_EN";
++	case RM_BCN_MEAS_REP_COND_CAP_EN:
++		return "RM_BCN_MEAS_REP_COND_CAP_EN";
++
++	case RM_FRAME_MEAS_CAP_EN:
++		return "RM_FRAME_MEAS_CAP_EN";
++	case RM_CH_LOAD_CAP_EN:
++		return "RM_CH_LOAD_CAP_EN";
++	case RM_NOISE_HISTO_CAP_EN:
++		return "RM_NOISE_HISTO_CAP_EN";
++	case RM_STATIS_MEAS_CAP_EN:
++		return "RM_STATIS_MEAS_CAP_EN";
++	case RM_LCI_MEAS_CAP_EN:
++		return "RM_LCI_MEAS_CAP_EN";
++	case RM_LCI_AMIMUTH_CAP_EN:
++		return "RM_LCI_AMIMUTH_CAP_EN";
++	case RM_TRANS_STREAM_CAT_MEAS_CAP_EN:
++		return "RM_TRANS_STREAM_CAT_MEAS_CAP_EN";
++	case RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN:
++		return "RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN";
++
++	case RM_AP_CH_REP_CAP_EN:
++		return "RM_AP_CH_REP_CAP_EN";
++	case RM_RM_MIB_CAP_EN:
++		return "RM_RM_MIB_CAP_EN";
++	case RM_OP_CH_MAX_MEAS_DUR0:
++		return "RM_OP_CH_MAX_MEAS_DUR0";
++	case RM_OP_CH_MAX_MEAS_DUR1:
++		return "RM_OP_CH_MAX_MEAS_DUR1";
++	case RM_OP_CH_MAX_MEAS_DUR2:
++		return "RM_OP_CH_MAX_MEAS_DUR2";
++	case RM_NONOP_CH_MAX_MEAS_DUR0:
++		return "RM_NONOP_CH_MAX_MEAS_DUR0";
++	case RM_NONOP_CH_MAX_MEAS_DUR1:
++		return "RM_NONOP_CH_MAX_MEAS_DUR1";
++	case RM_NONOP_CH_MAX_MEAS_DUR2:
++		return "RM_NONOP_CH_MAX_MEAS_DUR2";
++
++	case RM_MEAS_PILOT_CAP0:
++		return "RM_MEAS_PILOT_CAP0";		/* 24-26 */
++	case RM_MEAS_PILOT_CAP1:
++		return "RM_MEAS_PILOT_CAP1";
++	case RM_MEAS_PILOT_CAP2:
++		return "RM_MEAS_PILOT_CAP2";
++	case RM_MEAS_PILOT_TRANS_INFO_CAP_EN:
++		return "RM_MEAS_PILOT_TRANS_INFO_CAP_EN";
++	case RM_NB_REP_TSF_OFFSET_CAP_EN:
++		return "RM_NB_REP_TSF_OFFSET_CAP_EN";
++	case RM_RCPI_MEAS_CAP_EN:
++		return "RM_RCPI_MEAS_CAP_EN";		/* 29 */
++	case RM_RSNI_MEAS_CAP_EN:
++		return "RM_RSNI_MEAS_CAP_EN";
++	case RM_BSS_AVG_ACCESS_DELAY_CAP_EN:
++		return "RM_BSS_AVG_ACCESS_DELAY_CAP_EN";
++
++	case RM_AVALB_ADMIS_CAPACITY_CAP_EN:
++		return "RM_AVALB_ADMIS_CAPACITY_CAP_EN";
++	case RM_ANT_CAP_EN:
++		return "RM_ANT_CAP_EN";
++	case RM_RSVD:
++	case RM_MAX:
++	default:
++		break;
++	}
++	return "unknown";
++}
++
++int rm_en_cap_chk_and_set(struct rm_obj *prm, enum rm_cap_en en)
++{
++	int idx;
++	u8 cap;
++
++
++	if (en >= RM_MAX)
++		return _FALSE;
++
++	idx = en / 8;
++	cap = prm->psta->padapter->rmpriv.rm_en_cap_def[idx];
++
++	if (!(cap & BIT(en - (idx*8)))) {
++		RTW_INFO("RM: %s incapable\n",rm_en_cap_name(en));
++		rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
++		return _FALSE;
++	}
++	return _SUCCESS;
++}
++
++/* for caller outside rm */
++u8 rm_add_nb_req(_adapter *padapter, struct sta_info *psta)
++{
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
++	struct rm_obj *prm;
++
++
++	prm = rm_alloc_rmobj(padapter);
++
++	if (prm == NULL) {
++		RTW_ERR("RM: unable to alloc rm obj for requeset\n");
++		return _FALSE;
++	}
++
++	prm->psta = psta;
++	prm->q.category = RTW_WLAN_CATEGORY_RADIO_MEAS;
++	do {
++		pmlmeinfo->dialogToken++;
++	} while (pmlmeinfo->dialogToken == 0);
++
++	prm->q.diag_token = pmlmeinfo->dialogToken;
++	prm->q.m_token = 1;
++
++	prm->rmid = psta->cmn.aid << 16
++		| prm->q.diag_token << 8
++		| RM_MASTER;
++
++	prm->q.action_code = RM_ACT_NB_REP_REQ;
++
++	#if 0
++	if (pmac) { /* find sta_info according to bssid */
++		pmac += 4; /* skip mac= */
++		if (hwaddr_parse(pmac, bssid) == NULL) {
++			sprintf(pstr(s), "Err: \nincorrect mac format\n");
++			return _FAIL;
++		}
++		psta = rm_get_sta(padapter, 0xff, bssid);
++	}
++	#endif
++
++	/* enquee rmobj */
++	rm_enqueue_rmobj(padapter, prm, _FALSE);
++
++	RTW_INFO("RM: rmid=%x add req to " MAC_FMT "\n",
++		prm->rmid, MAC_ARG(psta->cmn.mac_addr));
++
++	return _SUCCESS;
++}
++
++static u8 *build_wlan_hdr(_adapter *padapter, struct xmit_frame *pmgntframe,
++	struct sta_info *psta, u16 frame_type)
++{
++	u8 *pframe;
++	u16 *fctrl;
++	struct pkt_attrib *pattr;
++	struct rtw_ieee80211_hdr *pwlanhdr;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
++
++
++	/* update attribute */
++	pattr = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattr);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, psta->cmn.mac_addr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3,
++		get_my_bssid(&(pmlmeinfo->network)),ETH_ALEN);
++
++	RTW_INFO("RM: dst = " MAC_FMT "\n", MAC_ARG(pwlanhdr->addr1));
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	SetFragNum(pframe, 0);
++
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattr->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	return pframe;
++}
++
++void rm_set_rep_mode(struct rm_obj *prm, u8 mode)
++{
++
++	RTW_INFO("RM: rmid=%x set %s\n",
++		prm->rmid,
++		mode|MEAS_REP_MOD_INCAP?"INCAP":
++		mode|MEAS_REP_MOD_REFUSE?"REFUSE":
++		mode|MEAS_REP_MOD_LATE?"LATE":"");
++
++	prm->p.m_mode |= mode;
++}
++
++int issue_null_reply(struct rm_obj *prm)
++{
++	int len=0, my_len;
++	u8 *pframe, m_mode;
++	_adapter *padapter = prm->psta->padapter;
++	struct pkt_attrib *pattr;
++	struct xmit_frame *pmgntframe;
++	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++
++
++	m_mode = prm->p.m_mode;
++	if (m_mode || prm->p.rpt == 0) {
++		RTW_INFO("RM: rmid=%x reply (%s repeat=%d)\n",
++			prm->rmid,
++			m_mode&MEAS_REP_MOD_INCAP?"INCAP":
++			m_mode&MEAS_REP_MOD_REFUSE?"REFUSE":
++			m_mode&MEAS_REP_MOD_LATE?"LATE":"no content",
++			prm->p.rpt);
++	}
++
++	switch (prm->p.action_code) {
++	case RM_ACT_RADIO_MEAS_REQ:
++		len = 8;
++		break;
++	case RM_ACT_NB_REP_REQ:
++		len = 3;
++		break;
++	case RM_ACT_LINK_MEAS_REQ:
++		len = 3;
++		break;
++	default:
++		break;
++	}
++
++	if (len==0)
++		return _FALSE;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL) {
++		RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__);
++		return _FALSE;
++	}
++	pattr = &pmgntframe->attrib;
++	pframe = build_wlan_hdr(padapter, pmgntframe, prm->psta, WIFI_ACTION);
++	pframe = rtw_set_fixed_ie(pframe, 3, &prm->p.category, &pattr->pktlen);
++
++	my_len = 0;
++	if (len>5) {
++		prm->p.len = len - 3 - 2;
++		pframe = rtw_set_fixed_ie(pframe, len - 3,
++			&prm->p.e_id, &my_len);
++	}
++
++	pattr->pktlen += my_len;
++	pattr->last_txcmdsz = pattr->pktlen;
++	dump_mgntframe(padapter, pmgntframe);
++
++	return _SUCCESS;
++}
++
++int ready_for_scan(struct rm_obj *prm)
++{
++	_adapter *padapter = prm->psta->padapter;
++	u8 ssc_chk;
++
++	if (!rtw_is_adapter_up(padapter))
++		return _FALSE;
++
++	ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
++
++	if (ssc_chk == SS_ALLOW)
++		return _SUCCESS;
++
++	return _FALSE;
++}
++
++int rm_sitesurvey(struct rm_obj *prm)
++{
++	int meas_ch_num=0;
++	u8 ch_num=0, op_class=0, val8;
++	struct rtw_ieee80211_channel *pch_set;
++	struct sitesurvey_parm parm;
++
++
++	RTW_INFO("RM: rmid=%x %s\n",prm->rmid, __func__);
++
++	pch_set = &prm->q.ch_set[0];
++
++	_rtw_memset(pch_set, 0,
++		sizeof(struct rtw_ieee80211_channel) * MAX_OP_CHANNEL_SET_NUM);
++
++	if (prm->q.ch_num == 0) {
++		/* ch_num=0   : scan all ch in operating class */
++		op_class = prm->q.op_class;
++
++	} else if (prm->q.ch_num == 255) {
++		/* 802.11 p.499 */
++		/* ch_num=255 : scan all ch in current operating class */
++		op_class = rm_get_oper_class_via_ch(
++			(u8)prm->psta->padapter->mlmeextpriv.cur_channel);
++	} else
++		ch_num = prm->q.ch_num;
++
++	/* get means channel */
++	meas_ch_num = rm_get_ch_set(pch_set, op_class, ch_num);
++	prm->q.ch_set_ch_amount = meas_ch_num;
++
++	_rtw_memset(&parm, 0, sizeof(struct sitesurvey_parm));
++	_rtw_memcpy(parm.ch, pch_set,
++		sizeof(struct rtw_ieee80211_channel) * MAX_OP_CHANNEL_SET_NUM);
++
++	_rtw_memcpy(&parm.ssid[0], &prm->q.opt.bcn.ssid, IW_ESSID_MAX_SIZE);
++
++	parm.ssid_num = 1;
++	parm.scan_mode = prm->q.m_mode;
++	parm.ch_num = meas_ch_num;
++	parm.igi = 0;
++	parm.token = prm->rmid;
++	parm.duration = prm->q.meas_dur;
++	/* parm.bw = BW_20M; */
++
++	rtw_sitesurvey_cmd(prm->psta->padapter, &parm);
++
++	return _SUCCESS;
++}
++
++static int rm_parse_ch_load_s_elem(struct rm_obj *prm, u8 *pbody, int req_len)
++{
++	u8 *popt_id;
++	int i, p=0; /* position */
++	int len = req_len;
++
++
++	prm->q.opt_s_elem_len = len;
++#if (RM_MORE_DBG_MSG)
++	RTW_INFO("RM: opt_s_elem_len=%d\n", len);
++#endif
++	while (len) {
++
++		switch (pbody[p]) {
++		case ch_load_rep_info:
++			/* check RM_EN */
++			rm_en_cap_chk_and_set(prm, RM_CH_LOAD_CAP_EN);
++
++			_rtw_memcpy(&(prm->q.opt.clm.rep_cond),
++				&pbody[p+2], sizeof(prm->q.opt.clm.rep_cond));
++
++			RTW_INFO("RM: ch_load_rep_info=%u:%u\n",
++				prm->q.opt.clm.rep_cond.cond,
++				prm->q.opt.clm.rep_cond.threshold);
++			break;
++		default:
++			break;
++
++		}
++		len = len - (int)pbody[p+1] - 2;
++		p = p + (int)pbody[p+1] + 2;
++#if (RM_MORE_DBG_MSG)
++		RTW_INFO("RM: opt_s_elem_len=%d\n",len);
++#endif
++	}
++	return _SUCCESS;
++}
++
++static int rm_parse_noise_histo_s_elem(struct rm_obj *prm,
++	u8 *pbody, int req_len)
++{
++	u8 *popt_id;
++	int i, p=0; /* position */
++	int len = req_len;
++
++
++	prm->q.opt_s_elem_len = len;
++#if (RM_MORE_DBG_MSG)
++	RTW_INFO("RM: opt_s_elem_len=%d\n", len);
++#endif
++
++	while (len) {
++
++		switch (pbody[p]) {
++		case noise_histo_rep_info:
++			/* check RM_EN */
++			rm_en_cap_chk_and_set(prm, RM_NOISE_HISTO_CAP_EN);
++
++			_rtw_memcpy(&(prm->q.opt.nhm.rep_cond),
++				&pbody[p+2], sizeof(prm->q.opt.nhm.rep_cond));
++
++			RTW_INFO("RM: noise_histo_rep_info=%u:%u\n",
++				prm->q.opt.nhm.rep_cond.cond,
++				prm->q.opt.nhm.rep_cond.threshold);
++			break;
++		default:
++			break;
++
++       		}
++		len = len - (int)pbody[p+1] - 2;
++		p = p + (int)pbody[p+1] + 2;
++#if (RM_MORE_DBG_MSG)
++		RTW_INFO("RM: opt_s_elem_len=%d\n",len);
++#endif
++	}
++	return _SUCCESS;
++}
++
++static int rm_parse_bcn_req_s_elem(struct rm_obj *prm, u8 *pbody, int req_len)
++{
++	u8 *popt_id;
++	int i, p=0; /* position */
++	int len = req_len;
++
++
++	/* opt length,2:pbody[0]+ pbody[1] */
++	/* first opt id : pbody[18] */
++
++	prm->q.opt_s_elem_len = len;
++#if (RM_MORE_DBG_MSG)
++	RTW_INFO("RM: opt_s_elem_len=%d\n", len);
++#endif
++
++	popt_id = prm->q.opt.bcn.opt_id;
++	while (len && prm->q.opt.bcn.opt_id_num < BCN_REQ_OPT_MAX_NUM) {
++
++		switch (pbody[p]) {
++		case bcn_req_ssid:
++			RTW_INFO("bcn_req_ssid\n");
++
++#if (DBG_BCN_REQ_WILDCARD)
++			RTW_INFO("DBG set ssid to WILDCARD\n");
++#else
++#if (DBG_BCN_REQ_SSID)
++			RTW_INFO("DBG set ssid to %s\n",DBG_BCN_REQ_SSID_NAME);
++			i = strlen(DBG_BCN_REQ_SSID_NAME);
++			prm->q.opt.bcn.ssid.SsidLength = i;
++			_rtw_memcpy(&(prm->q.opt.bcn.ssid.Ssid),
++				DBG_BCN_REQ_SSID_NAME, i);
++
++#else /* original */
++			prm->q.opt.bcn.ssid.SsidLength = pbody[p+1];
++			_rtw_memcpy(&(prm->q.opt.bcn.ssid.Ssid),
++				&pbody[p+2], pbody[p+1]);
++#endif
++#endif
++
++			RTW_INFO("RM: bcn_req_ssid=%s\n",
++				prm->q.opt.bcn.ssid.Ssid);
++
++			popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];
++			break;
++
++		case bcn_req_rep_info:
++			/* check RM_EN */
++			rm_en_cap_chk_and_set(prm, RM_BCN_MEAS_REP_COND_CAP_EN);
++
++			_rtw_memcpy(&(prm->q.opt.bcn.rep_cond),
++				&pbody[p+2], sizeof(prm->q.opt.bcn.rep_cond));
++
++			RTW_INFO("bcn_req_rep_info=%u:%u\n",
++				prm->q.opt.bcn.rep_cond.cond,
++				prm->q.opt.bcn.rep_cond.threshold);
++
++			/*popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];*/
++			break;
++
++		case bcn_req_rep_detail:
++#if DBG_BCN_REQ_DETAIL
++			prm->q.opt.bcn.rep_detail = 2; /* all IE in beacon */
++#else
++			prm->q.opt.bcn.rep_detail = pbody[p+2];
++#endif
++			popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];
++
++#if (RM_MORE_DBG_MSG)
++			RTW_INFO("RM: report_detail=%d\n",
++				prm->q.opt.bcn.rep_detail);
++#endif
++			break;
++
++		case bcn_req_req:
++			RTW_INFO("RM: bcn_req_req\n");
++
++			prm->q.opt.bcn.req_start = rtw_malloc(pbody[p+1]);
++
++			if (prm->q.opt.bcn.req_start == NULL) {
++				RTW_ERR("RM: req_start malloc fail!!\n");
++				break;
++			}
++
++			for (i = 0; i < pbody[p+1]; i++)
++				*((prm->q.opt.bcn.req_start)+i) =
++					pbody[p+2+i];
++
++			prm->q.opt.bcn.req_len = pbody[p+1];
++			popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];
++			break;
++
++		case bcn_req_ac_ch_rep:
++#if (RM_MORE_DBG_MSG)
++			RTW_INFO("RM: bcn_req_ac_ch_rep\n");
++#endif
++			popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];
++			break;
++
++		default:
++			break;
++
++       		}
++		len = len - (int)pbody[p+1] - 2;
++		p = p + (int)pbody[p+1] + 2;
++#if (RM_MORE_DBG_MSG)
++		RTW_INFO("RM: opt_s_elem_len=%d\n",len);
++#endif
++	}
++
++	return _SUCCESS;
++}
++
++static int rm_parse_meas_req(struct rm_obj *prm, u8 *pbody)
++{
++	int p; /* position */
++	int req_len;
++
++
++	req_len = (int)pbody[1];
++	p = 5;
++
++	prm->q.op_class = pbody[p++];
++	prm->q.ch_num = pbody[p++];
++	prm->q.rand_intvl = le16_to_cpu(*(u16*)(&pbody[p]));
++	p+=2;
++	prm->q.meas_dur = le16_to_cpu(*(u16*)(&pbody[p]));
++	p+=2;
++
++	if (prm->q.m_type == bcn_req) {
++		/*
++		 * 0: passive
++		 * 1: active
++		 * 2: bcn_table
++		 */
++		prm->q.m_mode = pbody[p++];
++
++		/* BSSID */
++		_rtw_memcpy(&(prm->q.bssid), &pbody[p], 6);
++		p+=6;
++
++		/*
++		 * default, used when Reporting detail subelement
++		 * is not included in Beacon Request
++		 */
++		prm->q.opt.bcn.rep_detail = 2;
++	}
++
++	if (req_len-(p-2) <= 0) /* without sub-element */
++		return _SUCCESS;
++
++	switch (prm->q.m_type) {
++	case bcn_req:
++		rm_parse_bcn_req_s_elem(prm, &pbody[p], req_len-(p-2));
++		break;
++	case ch_load_req:
++		rm_parse_ch_load_s_elem(prm, &pbody[p], req_len-(p-2));
++		break;
++	case noise_histo_req:
++		rm_parse_noise_histo_s_elem(prm, &pbody[p], req_len-(p-2));
++		break;
++	default:
++		break;
++	}
++
++	return _SUCCESS;
++}
++
++/* receive measurement request */
++int rm_recv_radio_mens_req(_adapter *padapter,
++	union recv_frame *precv_frame, struct sta_info *psta)
++{
++	struct rm_obj *prm;
++	struct rm_priv *prmpriv = &padapter->rmpriv;
++	u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +
++		sizeof(struct rtw_ieee80211_hdr_3addr));
++	u8 *pmeas_body = &pdiag_body[5];
++	u8 rmid, update = 0;
++
++
++#if 0
++	/* search existing rm_obj */
++	rmid = psta->cmn.aid << 16
++		| pdiag_body[2] << 8
++		| RM_SLAVE;
++
++	prm = rm_get_rmobj(padapter, rmid);
++	if (prm) {
++		RTW_INFO("RM: Found an exist meas rmid=%u\n", rmid);
++		update = 1;
++	} else
++#endif
++	prm = rm_alloc_rmobj(padapter);
++
++	if (prm == NULL) {
++		RTW_ERR("RM: unable to alloc rm obj for requeset\n");
++		return _FALSE;
++	}
++
++	prm->psta = psta;
++	prm->q.diag_token = pdiag_body[2];
++	prm->q.rpt = le16_to_cpu(*(u16*)(&pdiag_body[3]));
++
++	/* Figure 8-104 Measurement Requested format */
++	prm->q.e_id = pmeas_body[0];
++	prm->q.m_token = pmeas_body[2];
++	prm->q.m_mode = pmeas_body[3];
++	prm->q.m_type = pmeas_body[4];
++
++	prm->rmid = psta->cmn.aid << 16
++		| prm->q.diag_token << 8
++		| RM_SLAVE;
++
++	RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid,
++		MAC_ARG(prm->psta->cmn.mac_addr));
++
++#if (RM_MORE_DBG_MSG)
++	RTW_INFO("RM: element_id = %d\n", prm->q.e_id);
++	RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]);
++	RTW_INFO("RM: meas_token = %d\n", prm->q.m_token);
++	RTW_INFO("RM: meas_mode = %d\n", prm->q.m_mode);
++	RTW_INFO("RM: meas_type = %d\n", prm->q.m_type);
++#endif
++
++	if (prm->q.e_id != _MEAS_REQ_IE_) /* 38 */
++		return _FALSE;
++
++	switch (prm->q.m_type) {
++	case bcn_req:
++		RTW_INFO("RM: recv beacon_request\n");
++		switch (prm->q.m_mode) {
++		case bcn_req_passive:
++			rm_en_cap_chk_and_set(prm, RM_BCN_PASSIVE_MEAS_CAP_EN);
++			break;
++		case bcn_req_active:
++			rm_en_cap_chk_and_set(prm, RM_BCN_ACTIVE_MEAS_CAP_EN);
++			break;
++		case bcn_req_bcn_table:
++			rm_en_cap_chk_and_set(prm, RM_BCN_TABLE_MEAS_CAP_EN);
++			break;
++		default:
++			rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
++			break;
++		}
++		break;
++	case ch_load_req:
++		RTW_INFO("RM: recv ch_load_request\n");
++		rm_en_cap_chk_and_set(prm, RM_CH_LOAD_CAP_EN);
++		break;
++	case noise_histo_req:
++		RTW_INFO("RM: recv noise_histogram_request\n");
++		rm_en_cap_chk_and_set(prm, RM_NOISE_HISTO_CAP_EN);
++		break;
++	default:
++		RTW_INFO("RM: recv unknown request type 0x%02x\n",
++			prm->q.m_type);
++		rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
++		goto done;
++       }
++	rm_parse_meas_req(prm, pmeas_body);
++done:
++	if (!update)
++		rm_enqueue_rmobj(padapter, prm, _FALSE);
++
++	return _SUCCESS;
++}
++
++/* receive measurement report */
++int rm_recv_radio_mens_rep(_adapter *padapter,
++	union recv_frame *precv_frame, struct sta_info *psta)
++{
++	int ret = _FALSE;
++	struct rm_obj *prm;
++	u32 rmid;
++	u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +
++		sizeof(struct rtw_ieee80211_hdr_3addr));
++	u8 *pmeas_body = &pdiag_body[3];
++
++
++	rmid = psta->cmn.aid << 16
++		| pdiag_body[2] << 8
++		| RM_MASTER;
++
++	prm = rm_get_rmobj(padapter, rmid);
++	if (prm == NULL) {
++		/* not belong to us, report to upper */
++		rtw_cfg80211_rx_rrm_action(psta->padapter, precv_frame);
++		return _TRUE;
++	}
++
++	prm->p.action_code = pdiag_body[1];
++	prm->p.diag_token = pdiag_body[2];
++
++	/* Figure 8-140 Measuremnt Report format */
++	prm->p.e_id = pmeas_body[0];
++	prm->p.m_token = pmeas_body[2];
++	prm->p.m_mode = pmeas_body[3];
++	prm->p.m_type = pmeas_body[4];
++
++	RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid,
++		MAC_ARG(prm->psta->cmn.mac_addr));
++
++#if (RM_MORE_DBG_MSG)
++	RTW_INFO("RM: element_id = %d\n", prm->p.e_id);
++	RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]);
++	RTW_INFO("RM: meas_token = %d\n", prm->p.m_token);
++	RTW_INFO("RM: meas_mode = %d\n", prm->p.m_mode);
++	RTW_INFO("RM: meas_type = %d\n", prm->p.m_type);
++#endif
++	if (prm->p.e_id != _MEAS_RSP_IE_) /* 39 */
++		return _FALSE;
++
++	RTW_INFO("RM: recv %s\n", rm_type_rep_name(prm->p.m_type));
++	rm_post_event(padapter, prm->rmid, RM_EV_recv_rep);
++
++	return ret;
++}
++
++/* receive link measurement request */
++int rm_recv_link_mens_req(_adapter *padapter,
++	union recv_frame *precv_frame, struct sta_info *psta)
++{
++	struct rm_obj *prm;
++	struct rm_priv *prmpriv = &padapter->rmpriv;
++	u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +
++		sizeof(struct rtw_ieee80211_hdr_3addr));
++	u8 *pmeas_body = &pdiag_body[3];
++	u8 rmid, update = 0;
++	int i;
++
++
++	prm = rm_alloc_rmobj(padapter);
++
++	if (prm == NULL) {
++		RTW_ERR("RM: unable to alloc rm obj for requeset\n");
++		return _FALSE;
++	}
++
++	prm->psta = psta;
++	prm->q.action_code = pdiag_body[1];
++	prm->q.diag_token = pdiag_body[2];
++
++	prm->q.tx_pwr_used = pmeas_body[0];
++	prm->q.tx_pwr_max = pmeas_body[1];
++	prm->q.rx_pwr = precv_frame->u.hdr.attrib.phy_info.rx_power;
++	prm->q.rx_rate = hw_rate_to_m_rate(precv_frame->u.hdr.attrib.data_rate);
++	prm->q.rx_bw = precv_frame->u.hdr.attrib.bw;
++	prm->q.rx_rsni = rm_get_frame_rsni(prm, precv_frame);
++
++	prm->rmid = psta->cmn.aid << 16
++		| prm->q.diag_token << 8
++		| RM_SLAVE;
++
++	RTW_INFO("RM: rmid=%x, bssid" MAC_FMT " rx_pwr=%ddBm, rate=%s\n",
++		prm->rmid, MAC_ARG(prm->psta->cmn.mac_addr), prm->q.rx_pwr,
++		MGN_RATE_STR(prm->q.rx_rate));
++
++#if (RM_MORE_DBG_MSG)
++	RTW_INFO("RM: tx_pwr_used =%d dBm\n", prm->q.tx_pwr_used);
++	RTW_INFO("RM: tx_pwr_max  =%d dBm\n", prm->q.tx_pwr_max);
++#endif
++
++	if (!update)
++		rm_enqueue_rmobj(padapter, prm, _FALSE);
++
++	return _SUCCESS;
++}
++
++/* receive link measurement report */
++int rm_recv_link_mens_rep(_adapter *padapter,
++	union recv_frame *precv_frame, struct sta_info *psta)
++{
++	int ret = _FALSE;
++	struct rm_obj *prm;
++	u32 rmid;
++	u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +
++		sizeof(struct rtw_ieee80211_hdr_3addr));
++	u8 *pmeas_body = pdiag_body + 3;
++	s8 val;
++
++
++	rmid = psta->cmn.aid << 16
++		| pdiag_body[2] << 8
++		| RM_MASTER;
++
++	prm = rm_get_rmobj(padapter, rmid);
++	if (prm == NULL) {
++		/* not belong to us, report to upper */
++		rtw_cfg80211_rx_rrm_action(psta->padapter, precv_frame);
++		return _TRUE;
++	}
++
++	RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid,
++		MAC_ARG(prm->psta->cmn.mac_addr));
++
++	prm->p.action_code = pdiag_body[1];
++	prm->p.diag_token = pdiag_body[2];
++
++#if (RM_MORE_DBG_MSG)
++	RTW_INFO("RM: action_code = %d\n", prm->p.action_code);
++	RTW_INFO("RM: diag_token  = %d\n", prm->p.diag_token);
++	RTW_INFO("RM: xmit_power  = %d dBm\n", pmeas_body[2]);
++	RTW_INFO("RM: link_margin = %d dBm\n", pmeas_body[3]);
++	RTW_INFO("RM: xmit_ant    = %d\n", pmeas_body[4]);
++	RTW_INFO("RM: recv_ant    = %d\n", pmeas_body[5]);
++	RTW_INFO("RM: RCPI        = %d\n", pmeas_body[6]);
++	RTW_INFO("RM: RSNI        = %d\n", pmeas_body[7]);
++#endif
++	RTW_INFO("RM: recv link meas report ...\n");
++	ret = rm_post_event(padapter, prm->rmid, RM_EV_recv_rep);
++
++	return ret;
++}
++
++
++int rm_radio_mens_nb_rep(_adapter *padapter,
++	union recv_frame *precv_frame, struct sta_info *psta)
++{
++	u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +
++		sizeof(struct rtw_ieee80211_hdr_3addr));
++	u8 *pmeas_body = &pdiag_body[3];
++	u32 len = precv_frame->u.hdr.len;
++	u32 rmid;
++	struct rm_obj *prm;
++
++
++	rmid = psta->cmn.aid << 16
++		| pdiag_body[2] << 8
++		| RM_MASTER;
++
++	prm = rm_get_rmobj(padapter, rmid);
++
++	if (prm == NULL) {
++		/* not belong to us, report to upper */
++		rtw_cfg80211_rx_rrm_action(psta->padapter, precv_frame);
++		return _TRUE;
++	}
++
++	prm->p.action_code = pdiag_body[1];
++	prm->p.diag_token = pdiag_body[2];
++	prm->p.e_id = pmeas_body[0];
++
++	RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid,
++		MAC_ARG(prm->psta->cmn.mac_addr));
++
++#if (RM_MORE_DBG_MSG)
++	RTW_INFO("RM: element_id = %d\n", prm->p.e_id);
++	RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]);
++#endif
++	rm_post_event(padapter, prm->rmid, RM_EV_recv_rep);
++
++#ifdef CONFIG_LAYER2_ROAMING
++	if (rtw_wnm_btm_candidates_survey(padapter
++			,(pdiag_body + 3)
++			,(len - sizeof(struct rtw_ieee80211_hdr_3addr))
++			,_FALSE) == _FAIL)
++		return _FALSE;
++#endif
++	rtw_cfg80211_rx_rrm_action(padapter, precv_frame);
++
++	return _TRUE;
++}
++
++unsigned int rm_on_action(_adapter *padapter, union recv_frame *precv_frame)
++{
++	u32 ret = _FAIL;
++	u8 *pframe = NULL;
++	u8 *pframe_body = NULL;
++	u8 action_code = 0;
++	u8 diag_token = 0;
++	struct rtw_ieee80211_hdr_3addr *whdr;
++	struct sta_info *psta;
++
++
++	pframe = precv_frame->u.hdr.rx_data;
++
++	/* check RA matches or not */
++	if (!_rtw_memcmp(adapter_mac_addr(padapter),
++		GetAddr1Ptr(pframe), ETH_ALEN))
++		goto exit;
++
++	whdr = (struct rtw_ieee80211_hdr_3addr *)pframe;
++	RTW_INFO("RM: %s bssid = " MAC_FMT "\n",
++		__func__, MAC_ARG(whdr->addr2));
++
++	psta = rtw_get_stainfo(&padapter->stapriv, whdr->addr2);
++
++        if (!psta) {
++		RTW_ERR("RM: psta not found\n");
++                goto exit;
++        }
++
++	pframe_body = (unsigned char *)(pframe +
++		sizeof(struct rtw_ieee80211_hdr_3addr));
++
++	/* Figure 8-438 radio measurement request frame Action field format */
++	/* Category = pframe_body[0] = 5 (Radio Measurement) */
++	action_code = pframe_body[1];
++	diag_token = pframe_body[2];
++
++#if (RM_MORE_DBG_MSG)
++	RTW_INFO("RM: %s radio_action=%x, diag_token=%x\n", __func__,
++		action_code, diag_token);
++#endif
++
++	switch (action_code) {
++
++	case RM_ACT_RADIO_MEAS_REQ:
++		RTW_INFO("RM: RM_ACT_RADIO_MEAS_REQ\n");
++		ret = rm_recv_radio_mens_req(padapter, precv_frame, psta);
++		break;
++
++	case RM_ACT_RADIO_MEAS_REP:
++		RTW_INFO("RM: RM_ACT_RADIO_MEAS_REP\n");
++		ret = rm_recv_radio_mens_rep(padapter, precv_frame, psta);
++		break;
++
++	case RM_ACT_LINK_MEAS_REQ:
++		RTW_INFO("RM: RM_ACT_LINK_MEAS_REQ\n");
++		ret = rm_recv_link_mens_req(padapter, precv_frame, psta);
++		break;
++
++	case RM_ACT_LINK_MEAS_REP:
++		RTW_INFO("RM: RM_ACT_LINK_MEAS_REP\n");
++		ret = rm_recv_link_mens_rep(padapter, precv_frame, psta);
++		break;
++
++	case RM_ACT_NB_REP_REQ:
++		RTW_INFO("RM: RM_ACT_NB_REP_REQ\n");
++		break;
++
++	case RM_ACT_NB_REP_RESP:
++		RTW_INFO("RM: RM_ACT_NB_REP_RESP\n");
++		ret = rm_radio_mens_nb_rep(padapter, precv_frame, psta);
++		break;
++
++	default:
++		/* TODO reply incabable */
++		RTW_ERR("RM: unknown specturm management action %2x\n",
++			action_code);
++		break;
++	}
++exit:
++	return ret;
++}
++
++static u8 *rm_gen_bcn_detail_elem(_adapter *padapter, u8 *pframe,
++	struct rm_obj *prm, struct wlan_network *pnetwork,
++	unsigned int *fr_len)
++{
++	WLAN_BSSID_EX *pbss = &pnetwork->network;
++	unsigned int my_len;
++	int j, k, len;
++	u8 *plen;
++	u8 *ptr;
++	u8 val8, eid;
++
++
++	my_len = 0;
++	/* Reporting Detail values
++	 * 0: No fixed length fields or elements
++	 * 1: All fixed length fields and any requested elements
++	 *    in the Request info element if present
++	 * 2: All fixed length fields and elements
++	 * 3-255: Reserved
++	 */
++
++	/* report_detail = 0 */
++	if (prm->q.opt.bcn.rep_detail == 0
++		|| prm->q.opt.bcn.rep_detail > 2) {
++		return pframe;
++	}
++
++	/* ID */
++	val8 = 1; /* 1:reported frame body */
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	plen = pframe;
++	val8 = 0;
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	/* report_detail = 2 */
++	if (prm->q.opt.bcn.rep_detail == 2) {
++		pframe = rtw_set_fixed_ie(pframe, pbss->IELength - 4,
++			pbss->IEs, &my_len); /* -4 remove FCS */
++		goto done;
++	}
++
++	/* report_detail = 1 */
++	/* all fixed lenght fields */
++	pframe = rtw_set_fixed_ie(pframe,
++		_FIXED_IE_LENGTH_, pbss->IEs, &my_len);
++
++	for (j = 0; j < prm->q.opt.bcn.opt_id_num; j++) {
++		switch (prm->q.opt.bcn.opt_id[j]) {
++		case bcn_req_ssid:
++			/* SSID */
++#if (RM_MORE_DBG_MSG)
++			RTW_INFO("RM: bcn_req_ssid\n");
++#endif
++			pframe = rtw_set_ie(pframe, _SSID_IE_,
++				pbss->Ssid.SsidLength,
++				pbss->Ssid.Ssid, &my_len);
++			break;
++		case bcn_req_req:
++			if (prm->q.opt.bcn.req_start == NULL)
++				break;
++#if (RM_MORE_DBG_MSG)
++			RTW_INFO("RM: bcn_req_req");
++#endif
++			for (k=0; k<prm->q.opt.bcn.req_len; k++) {
++				eid = prm->q.opt.bcn.req_start[k];
++
++				val8 = pbss->IELength - _FIXED_IE_LENGTH_;
++				ptr = rtw_get_ie(pbss->IEs + _FIXED_IE_LENGTH_,
++					eid, &len, val8);
++
++				if (!ptr)
++					continue;
++#if (RM_MORE_DBG_MSG)
++				switch (eid) {
++				case EID_QBSSLoad:
++					RTW_INFO("RM: EID_QBSSLoad\n");
++					break;
++				case EID_HTCapability:
++					RTW_INFO("RM: EID_HTCapability\n");
++					break;
++				case _MDIE_:
++					RTW_INFO("RM: EID_MobilityDomain\n");
++					break;
++				default:
++					RTW_INFO("RM: EID %d todo\n",eid);
++					break;
++				}
++#endif
++				pframe = rtw_set_ie(pframe, eid,
++					len,ptr+2, &my_len);
++			} /* for() */
++			break;
++		case bcn_req_ac_ch_rep:
++		default:
++			RTW_INFO("RM: OPT %d TODO\n",prm->q.opt.bcn.opt_id[j]);
++			break;
++		}
++	}
++done:
++	/*
++	 * update my length
++	 * content length does NOT include ID and LEN
++	 */
++	val8 = my_len - 2;
++	rtw_set_fixed_ie(plen, 1, &val8, &j);
++
++	/* update length to caller */
++	*fr_len += my_len;
++
++	return pframe;
++}
++
++u8 rm_bcn_req_cond_mach(struct rm_obj *prm, struct wlan_network *pnetwork)
++{
++	u8 val8;
++
++
++	switch(prm->q.opt.bcn.rep_cond.cond) {
++	case bcn_rep_cond_immediately:
++		return _SUCCESS;
++	case bcn_req_cond_rcpi_greater:
++		val8 = rm_get_bcn_rcpi(prm, pnetwork);
++		if (val8 > prm->q.opt.bcn.rep_cond.threshold)
++			return _SUCCESS;
++		break;
++	case bcn_req_cond_rcpi_less:
++		val8 = rm_get_bcn_rcpi(prm, pnetwork);
++		if (val8 < prm->q.opt.bcn.rep_cond.threshold)
++			return _SUCCESS;
++		break;
++	case bcn_req_cond_rsni_greater:
++		val8 = rm_get_bcn_rsni(prm, pnetwork);
++		if (val8 != 255 && val8 > prm->q.opt.bcn.rep_cond.threshold)
++			return _SUCCESS;
++		break;
++	case bcn_req_cond_rsni_less:
++		val8 = rm_get_bcn_rsni(prm, pnetwork);
++		if (val8 != 255 && val8 < prm->q.opt.bcn.rep_cond.threshold)
++			return _SUCCESS;
++		break;
++	default:
++		RTW_ERR("RM: bcn_req cond %u not support\n",
++			prm->q.opt.bcn.rep_cond.cond);
++		break;
++	}
++	return _FALSE;
++}
++
++static u8 *rm_gen_bcn_rep_ie (struct rm_obj *prm,
++	u8 *pframe, struct wlan_network *pnetwork, unsigned int *fr_len)
++{
++	int snr, i;
++	u8 val8, *plen;
++	u16 val16;
++	u32 val32;
++	u64 val64;
++	unsigned int my_len;
++	_adapter *padapter = prm->psta->padapter;
++
++
++	my_len = 0;
++	plen = pframe + 1;
++	pframe = rtw_set_fixed_ie(pframe, 7, &prm->p.e_id, &my_len);
++
++	/* Actual Measurement StartTime */
++	val64 = cpu_to_le64(prm->meas_start_time);
++	pframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len);
++
++	/* Measurement Duration */
++	val16 = prm->meas_end_time - prm->meas_start_time;
++	val16 = cpu_to_le16(val16);
++	pframe = rtw_set_fixed_ie(pframe, 2, (u8*)&val16, &my_len);
++
++	/* TODO
++	* ReportedFrameInformation:
++	* 0 :beacon or probe rsp
++	* 1 :pilot frame
++	*/
++	val8 = 0; /* report frame info */
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	/* RCPI */
++	val8 = rm_get_bcn_rcpi(prm, pnetwork);
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	/* RSNI */
++	val8 = rm_get_bcn_rsni(prm, pnetwork);
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	/* BSSID */
++	pframe = rtw_set_fixed_ie(pframe, 6,
++		(u8 *)&pnetwork->network.MacAddress, &my_len);
++
++	/*
++	 * AntennaID
++	 * 0: unknown
++	 * 255: multiple antenna (Diversity)
++	 */
++	val8 = 0;
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	/* ParentTSF */
++	val32 = pnetwork->network.PhyInfo.free_cnt;
++	if (prm->free_run_counter_valid)
++		val32 += prm->meas_start_time;
++
++	pframe = rtw_set_fixed_ie(pframe, 4, (u8 *)&val32, &my_len);
++
++	/* Generate Beacon detail */
++	pframe = rm_gen_bcn_detail_elem(padapter, pframe,
++		prm, pnetwork, &my_len);
++	/*
++	* update my length
++	* content length does NOT include ID and LEN
++	*/
++	val8 = my_len - 2;
++	rtw_set_fixed_ie(plen, 1, &val8, &i);
++
++	/* update length to caller */
++	*fr_len += my_len;
++
++	return pframe;
++}
++
++static int retrieve_scan_result(struct rm_obj *prm)
++{
++	_irqL irqL;
++	_list *plist, *phead;
++	_queue *queue;
++	_adapter *padapter = prm->psta->padapter;
++	struct rtw_ieee80211_channel *pch_set;
++	struct wlan_network *pnetwork = NULL;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	int i, meas_ch_num=0;
++	PWLAN_BSSID_EX pbss;
++	unsigned int matched_network;
++	int len, my_len;
++	u8 buf_idx, *pbuf = NULL, *tmp_buf = NULL;
++
++
++	tmp_buf = rtw_malloc(MAX_XMIT_EXTBUF_SZ);
++	if (tmp_buf == NULL)
++		return 0;
++
++	my_len = 0;
++	buf_idx = 0;
++	matched_network = 0;
++	queue = &(pmlmepriv->scanned_queue);
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++
++	/* get requested measurement channel set */
++	pch_set = prm->q.ch_set;
++	meas_ch_num = prm->q.ch_set_ch_amount;
++
++	/* search scan queue to find requested SSID */
++	while (1) {
++
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++		pbss = &pnetwork->network;
++
++		/*
++		* report network if requested channel set contains
++		* the channel matchs selected network
++		*/
++		if (rtw_chset_search_ch(adapter_to_chset(padapter),
++			pbss->Configuration.DSConfig) == 0)
++			goto next;
++
++		if (rtw_mlme_band_check(padapter, pbss->Configuration.DSConfig)
++			== _FALSE)
++			goto next;
++
++		if (rtw_validate_ssid(&(pbss->Ssid)) == _FALSE)
++			goto next;
++
++		/* go through measurement requested channels */
++		for (i = 0; i < meas_ch_num; i++) {
++
++			/* match channel */
++			if (pch_set[i].hw_value != pbss->Configuration.DSConfig)
++				continue;
++
++			/* match bssid */
++			if (is_wildcard_bssid(prm->q.bssid) == FALSE)
++				if (_rtw_memcmp(prm->q.bssid,
++					pbss->MacAddress, 6) == _FALSE) {
++					continue;
++				}
++			/*
++			 * default wildcard SSID. wildcard SSID:
++			 * A SSID value (null) used to represent all SSIDs
++			 */
++
++			/* match ssid */
++			if ((prm->q.opt.bcn.ssid.SsidLength > 0) &&
++				_rtw_memcmp(prm->q.opt.bcn.ssid.Ssid,
++				pbss->Ssid.Ssid,
++				prm->q.opt.bcn.ssid.SsidLength) == _FALSE)
++				continue;
++
++			/* match condition */
++			if (rm_bcn_req_cond_mach(prm, pnetwork) == _FALSE) {
++				RTW_INFO("RM: condition mismatch ch %u ssid %s bssid "MAC_FMT"\n",
++					pch_set[i].hw_value, pbss->Ssid.Ssid,
++					MAC_ARG(pbss->MacAddress));
++				RTW_INFO("RM: condition %u:%u\n",
++					prm->q.opt.bcn.rep_cond.cond,
++					prm->q.opt.bcn.rep_cond.threshold);
++				continue;
++			}
++
++			/* Found a matched SSID */
++			matched_network++;
++
++			RTW_INFO("RM: ch %u Found %s bssid "MAC_FMT"\n",
++				pch_set[i].hw_value, pbss->Ssid.Ssid,
++				MAC_ARG(pbss->MacAddress));
++
++			len = 0;
++			_rtw_memset(tmp_buf, 0, MAX_XMIT_EXTBUF_SZ);
++			rm_gen_bcn_rep_ie(prm, tmp_buf, pnetwork, &len);
++new_packet:
++			if (my_len == 0) {
++				pbuf = rtw_malloc(MAX_XMIT_EXTBUF_SZ);
++				if (pbuf == NULL)
++					goto fail;
++				prm->buf[buf_idx].pbuf = pbuf;
++			}
++
++			if ((MAX_XMIT_EXTBUF_SZ - (my_len+len+24+4)) > 0) {
++				pbuf = rtw_set_fixed_ie(pbuf,
++					len, tmp_buf, &my_len);
++				prm->buf[buf_idx].len = my_len;
++			} else {
++				if (my_len == 0) /* not enough space */
++					goto fail;
++
++				my_len = 0;
++				buf_idx++;
++				goto new_packet;
++			}
++		} /* for() */
++next:
++		plist = get_next(plist);
++	} /* while() */
++fail:
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	if (tmp_buf)
++		rtw_mfree(tmp_buf, MAX_XMIT_EXTBUF_SZ);
++
++	RTW_INFO("RM: Found %d matched %s\n", matched_network,
++		prm->q.opt.bcn.ssid.Ssid);
++
++	if (prm->buf[buf_idx].pbuf)
++		return buf_idx+1;
++
++	return 0;
++}
++
++int issue_beacon_rep(struct rm_obj *prm)
++{
++	int i, my_len;
++	u8 *pframe;
++	_adapter *padapter = prm->psta->padapter;
++	struct pkt_attrib *pattr;
++	struct xmit_frame *pmgntframe;
++	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++	int pkt_num;
++
++
++	pkt_num = retrieve_scan_result(prm);
++
++	if (pkt_num == 0) {
++		issue_null_reply(prm);
++		return _SUCCESS;
++	}
++
++	for (i=0;i<pkt_num;i++) {
++
++		pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++		if (pmgntframe == NULL) {
++			RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__);
++			goto fail;
++		}
++		pattr = &pmgntframe->attrib;
++		pframe = build_wlan_hdr(padapter,
++			pmgntframe, prm->psta, WIFI_ACTION);
++		pframe = rtw_set_fixed_ie(pframe,
++			3, &prm->p.category, &pattr->pktlen);
++
++		my_len = 0;
++		pframe = rtw_set_fixed_ie(pframe,
++			prm->buf[i].len, prm->buf[i].pbuf, &my_len);
++
++		pattr->pktlen += my_len;
++		pattr->last_txcmdsz = pattr->pktlen;
++		dump_mgntframe(padapter, pmgntframe);
++	}
++fail:
++	for (i=0;i<pkt_num;i++) {
++		if (prm->buf[i].pbuf) {
++			rtw_mfree(prm->buf[i].pbuf, MAX_XMIT_EXTBUF_SZ);
++			prm->buf[i].pbuf = NULL;
++			prm->buf[i].len = 0;
++		}
++	}
++	return _SUCCESS;
++}
++
++/* neighbor request */
++int issue_nb_req(struct rm_obj *prm)
++{
++	_adapter *padapter = prm->psta->padapter;
++	struct sta_info *psta = prm->psta;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	struct xmit_frame *pmgntframe = NULL;
++	struct pkt_attrib *pattr = NULL;
++	u8 val8;
++	u8 *pframe = NULL;
++
++
++	RTW_INFO("RM: %s\n", __func__);
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL) {
++		RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__);
++		return _FALSE;
++	}
++	pattr = &pmgntframe->attrib;
++	pframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION);
++	pframe = rtw_set_fixed_ie(pframe,
++		3, &prm->q.category, &pattr->pktlen);
++
++	if (prm->q.pssid) {
++
++		u8 sub_ie[64] = {0};
++		u8 *pie = &sub_ie[2];
++
++		RTW_INFO("RM: Send NB Req to "MAC_FMT" for(SSID) %s searching\n",
++			MAC_ARG(pmlmepriv->cur_network.network.MacAddress),
++			pmlmepriv->cur_network.network.Ssid.Ssid);
++
++		val8 = strlen(prm->q.pssid);
++		sub_ie[0] = 0; /*SSID*/
++		sub_ie[1] = val8;
++
++		_rtw_memcpy(pie, prm->q.pssid, val8);
++
++		pframe = rtw_set_fixed_ie(pframe, val8 + 2,
++			sub_ie, &pattr->pktlen);
++	} else {
++
++		if (!pmlmepriv->cur_network.network.Ssid.SsidLength)
++			RTW_INFO("RM: Send NB Req to "MAC_FMT"\n",
++				MAC_ARG(pmlmepriv->cur_network.network.MacAddress));
++		else {
++			u8 sub_ie[64] = {0};
++			u8 *pie = &sub_ie[2];
++
++			RTW_INFO("RM: Send NB Req to "MAC_FMT" for(SSID) %s searching\n",
++				MAC_ARG(pmlmepriv->cur_network.network.MacAddress),
++				pmlmepriv->cur_network.network.Ssid.Ssid);
++
++			sub_ie[0] = 0; /*SSID*/
++			sub_ie[1] = pmlmepriv->cur_network.network.Ssid.SsidLength;
++
++			_rtw_memcpy(pie, pmlmepriv->cur_network.network.Ssid.Ssid,
++				pmlmepriv->cur_network.network.Ssid.SsidLength);
++
++			pframe = rtw_set_fixed_ie(pframe,
++				pmlmepriv->cur_network.network.Ssid.SsidLength + 2,
++				sub_ie, &pattr->pktlen);
++		}
++	}
++
++	pattr->last_txcmdsz = pattr->pktlen;
++	dump_mgntframe(padapter, pmgntframe);
++
++	return _SUCCESS;
++}
++
++/* issue link measurement request */
++int issue_link_meas_req(struct rm_obj *prm)
++{
++	_adapter *padapter = prm->psta->padapter;
++	struct sta_info *psta = prm->psta;
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	struct xmit_frame *pmgntframe = NULL;
++	struct pkt_attrib *pattr = NULL;
++	u8 *pframe = NULL;
++	s8 pwr_used, path_a_pwr;
++
++
++	RTW_INFO("RM: %s\n", __func__);
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL) {
++		RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__);
++		return _FALSE;
++	}
++	pattr = &pmgntframe->attrib;
++	pframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION);
++
++	/* Category, Action code, Dialog token */
++	pframe = rtw_set_fixed_ie(pframe,
++		3, &prm->q.category, &pattr->pktlen);
++
++	/* xmit power used */
++	/* we don't know actual TX power due to RA may change TX rate;
++	 * But if we fix TX rate then we can get specific tx power
++	 */
++	pattr->rate = MGN_6M;
++	rm_get_tx_power(padapter, RF_PATH_A, MGN_6M, &pwr_used);
++	pframe = rtw_set_fixed_ie(pframe,
++		1, &pwr_used, &pattr->pktlen);
++
++	/* Max xmit power */
++	rm_get_path_a_max_tx_power(padapter, &path_a_pwr);
++	pframe = rtw_set_fixed_ie(pframe,
++		1, &path_a_pwr, &pattr->pktlen);
++
++	pattr->last_txcmdsz = pattr->pktlen;
++	dump_mgntframe(padapter, pmgntframe);
++
++	return _SUCCESS;
++}
++
++/* issue link measurement report */
++int issue_link_meas_rep(struct rm_obj *prm)
++{
++	u8 val8;
++	u8 *pframe;
++	unsigned int my_len;
++	_adapter *padapter = prm->psta->padapter;
++	struct xmit_frame *pmgntframe;
++	struct pkt_attrib *pattr;
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct sta_info *psta = prm->psta;
++	int i;
++	u8 tpc[4];
++	s8 pwr_used;
++
++
++	RTW_INFO("RM: %s\n", __func__);
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL) {
++		RTW_ERR("RM: ERR %s alloc xmit_frame fail\n",__func__);
++		return _FALSE;
++	}
++	pattr = &pmgntframe->attrib;
++	pframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION);
++	/* Category, action code, Dialog token */
++	pframe = rtw_set_fixed_ie(pframe, 3,
++		&prm->p.category, &pattr->pktlen);
++
++	my_len = 0;
++
++	/* TPC report */
++	rm_get_tx_power(padapter, RF_PATH_A, MGN_6M, &pwr_used);
++	tpc[0] = EID_TPC;
++	tpc[1] = 2; /* length */
++
++	/* TX power */
++	tpc[2] = pwr_used;
++
++	/* link margin */
++	rm_get_rx_sensitivity(padapter, prm->q.rx_bw, prm->q.rx_rate, &pwr_used);
++	tpc[3] = prm->q.rx_pwr - pwr_used; /* RX sensitivity */
++	pattr->rate = MGN_6M; /* use fix rate to get fixed RX sensitivity */
++
++#if (RM_MORE_DBG_MSG)
++	RTW_INFO("RM: rx_pwr=%ddBm - rx_sensitivity=%ddBm = link_margin=%ddB\n",
++		prm->q.rx_pwr, pwr_used, tpc[3]);
++#endif
++	pframe = rtw_set_fixed_ie(pframe, 4, tpc, &my_len);
++
++	/* RECV antenna ID */
++	val8 = 0; /* unknown antenna */
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	/* XMIT antenna ID */
++	/* Fix rate 6M(1T) always use main antenna to TX */
++	val8 = 1; /* main antenna */
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	/* RCPI */
++	val8 = translate_dbm_to_rcpi(prm->q.rx_pwr);
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	/* RSNI */
++	val8 = prm->q.rx_rsni;
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	/* length */
++	//val8 = (u8)my_len-2;
++	//rtw_set_fixed_ie(plen, 1, &val8, &i); /* use variable i to ignore it */
++
++	pattr->pktlen += my_len;
++	pattr->last_txcmdsz = pattr->pktlen;
++	dump_mgntframe(padapter, pmgntframe);
++
++	return _SUCCESS;
++}
++
++static u8 *rm_gen_bcn_req_s_elem(_adapter *padapter,
++	u8 *pframe, unsigned int *fr_len)
++{
++	u8 val8;
++	unsigned int my_len = 0;
++	u8 bssid[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++
++
++	val8 = bcn_req_active; /* measurement mode T8-64 */
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	pframe = rtw_set_fixed_ie(pframe, 6, bssid, &my_len);
++
++	/* update length to caller */
++	*fr_len += my_len;
++
++	/* optional subelements */
++	return pframe;
++}
++
++static u8 *rm_gen_ch_load_req_s_elem(_adapter *padapter,
++	u8 *pframe, unsigned int *fr_len)
++{
++	u8 val8;
++	unsigned int my_len = 0;
++
++
++	val8 = 1; /* 1: channel load T8-60 */
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	val8 = 2; /* channel load length = 2 (extensible)  */
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	val8 = 0; /* channel load condition : 0 (issue when meas done) T8-61 */
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	val8 = 0; /* channel load reference value : 0 */
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	/* update length to caller */
++	*fr_len += my_len;
++
++	return pframe;
++}
++
++static u8 *rm_gen_noise_histo_req_s_elem(_adapter *padapter,
++	u8 *pframe, unsigned int *fr_len)
++{
++	u8 val8;
++	unsigned int my_len = 0;
++
++
++	val8 = 1; /* 1: noise histogram T8-62 */
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	val8 = 2; /* noise histogram length = 2 (extensible)  */
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	val8 = 0; /* noise histogram condition : 0 (issue when meas done) T8-63 */
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	val8 = 0; /* noise histogram reference value : 0 */
++	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++
++	/* update length to caller */
++	*fr_len += my_len;
++
++	return pframe;
++}
++
++int issue_radio_meas_req(struct rm_obj *prm)
++{
++	u8 val8;
++	u8 *pframe;
++	u8 *plen;
++	u16 val16;
++	int my_len, i;
++	struct xmit_frame *pmgntframe;
++	struct pkt_attrib *pattr;
++	_adapter *padapter = prm->psta->padapter;
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++
++	RTW_INFO("RM: %s - %s\n", __func__, rm_type_req_name(prm->q.m_type));
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL) {
++		RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__);
++		return _FALSE;
++	}
++	pattr = &pmgntframe->attrib;
++	pframe = build_wlan_hdr(padapter, pmgntframe, prm->psta, WIFI_ACTION);
++	pframe = rtw_set_fixed_ie(pframe, 3, &prm->q.category, &pattr->pktlen);
++
++	/* repeat */
++	val16 = cpu_to_le16(prm->q.rpt);
++	pframe = rtw_set_fixed_ie(pframe, 2,
++		(unsigned char *)&(val16), &pattr->pktlen);
++
++	my_len = 0;
++	plen = pframe + 1;
++	pframe = rtw_set_fixed_ie(pframe, 7, &prm->q.e_id, &my_len);
++
++	/* random interval */
++	val16 = 100; /* 100 TU */
++	val16 = cpu_to_le16(val16);
++	pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);
++
++	/* measurement duration */
++	val16 = 100;
++	val16 = cpu_to_le16(val16);
++	pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);
++
++	/* optional subelement */
++	switch (prm->q.m_type) {
++	case bcn_req:
++		pframe = rm_gen_bcn_req_s_elem(padapter, pframe, &my_len);
++		break;
++	case ch_load_req:
++		pframe = rm_gen_ch_load_req_s_elem(padapter, pframe, &my_len);
++		break;
++	case noise_histo_req:
++		pframe = rm_gen_noise_histo_req_s_elem(padapter,
++			pframe, &my_len);
++		break;
++	case basic_req:
++	default:
++		break;
++	}
++
++	/* length */
++	val8 = (u8)my_len - 2;
++	rtw_set_fixed_ie(plen, 1, &val8, &i);
++
++	pattr->pktlen += my_len;
++
++	pattr->last_txcmdsz = pattr->pktlen;
++	dump_mgntframe(padapter, pmgntframe);
++
++	return _SUCCESS;
++}
++
++int rm_radio_meas_report_cond(struct rm_obj *prm)
++{
++	u8 val8;
++	int i;
++
++
++	switch (prm->q.m_type) {
++	case ch_load_req:
++
++		val8 = prm->p.ch_load;
++		switch (prm->q.opt.clm.rep_cond.cond) {
++		case ch_load_cond_immediately:
++			return _SUCCESS;
++		case ch_load_cond_anpi_equal_greater:
++			if (val8 >= prm->q.opt.clm.rep_cond.threshold)
++				return _SUCCESS;
++		case ch_load_cond_anpi_equal_less:
++			if (val8 <= prm->q.opt.clm.rep_cond.threshold)
++				return _SUCCESS;
++		default:
++			break;
++		}
++		break;
++	case noise_histo_req:
++		val8 = prm->p.anpi;
++		switch (prm->q.opt.nhm.rep_cond.cond) {
++		case noise_histo_cond_immediately:
++			return _SUCCESS;
++		case noise_histo_cond_anpi_equal_greater:
++			if (val8 >= prm->q.opt.nhm.rep_cond.threshold)
++				return _SUCCESS;
++			break;
++		case noise_histo_cond_anpi_equal_less:
++			if (val8 <= prm->q.opt.nhm.rep_cond.threshold)
++				return _SUCCESS;
++			break;
++		default:
++			break;
++		}
++		break;
++	default:
++		break;
++	}
++	return _FAIL;
++}
++
++int retrieve_radio_meas_result(struct rm_obj *prm)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(prm->psta->padapter);
++	int i, ch = -1;
++	u8 val8;
++
++
++	ch = rtw_chset_search_ch(adapter_to_chset(prm->psta->padapter),
++		prm->q.ch_num);
++
++	if ((ch == -1) || (ch >= MAX_CHANNEL_NUM)) {
++		RTW_ERR("RM: get ch(CH:%d) fail\n", prm->q.ch_num);
++		ch = 0;
++	}
++
++	switch (prm->q.m_type) {
++	case ch_load_req:
++#ifdef CONFIG_RTW_ACS
++		val8 = hal_data->acs.clm_ratio[ch];
++#else
++		val8 = 0;
++#endif
++		prm->p.ch_load = val8;
++		break;
++	case noise_histo_req:
++#ifdef CONFIG_RTW_ACS
++		/* ANPI */
++		prm->p.anpi = hal_data->acs.nhm_ratio[ch];
++
++		/* IPI 0~10 */
++		for (i=0;i<11;i++)
++			prm->p.ipi[i] = hal_data->acs.nhm[ch][i];
++		
++#else
++		val8 = 0;
++		prm->p.anpi = val8;
++		for (i=0;i<11;i++)
++			prm->p.ipi[i] = val8;
++#endif
++		break;
++	default:
++		break;
++	}
++	return _SUCCESS;
++}
++
++int issue_radio_meas_rep(struct rm_obj *prm)
++{
++	u8 val8;
++	u8 *pframe;
++	u8 *plen;
++	u16 val16;
++	u64 val64;
++	unsigned int my_len;
++	_adapter *padapter = prm->psta->padapter;
++	struct xmit_frame *pmgntframe;
++	struct pkt_attrib *pattr;
++	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++	struct sta_info *psta = prm->psta;
++	int i;
++
++
++	RTW_INFO("RM: %s\n", __func__);
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL) {
++		RTW_ERR("RM: ERR %s alloc xmit_frame fail\n",__func__);
++		return _FALSE;
++	}
++	pattr = &pmgntframe->attrib;
++	pframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION);
++	pframe = rtw_set_fixed_ie(pframe, 3,
++		&prm->p.category, &pattr->pktlen);
++
++	my_len = 0;
++	plen = pframe + 1;
++	pframe = rtw_set_fixed_ie(pframe, 7, &prm->p.e_id, &my_len);
++
++	/* Actual Meas start time - 8 bytes */
++	val64 = cpu_to_le64(prm->meas_start_time);
++	pframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len);
++
++	/* measurement duration */
++	val16 = prm->meas_end_time - prm->meas_start_time;
++	val16 = cpu_to_le16(val16);
++	pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);
++
++	/* optional subelement */
++	switch (prm->q.m_type) {
++	case ch_load_req:
++		val8 = prm->p.ch_load;
++		pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++		break;
++	case noise_histo_req:
++		/*
++		 * AntennaID
++		 * 0: unknown
++		 * 255: multiple antenna (Diversity)
++		 */
++		val8 = 0;
++		pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++		/* ANPI */
++		val8 = prm->p.anpi;
++		pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++		/* IPI 0~10 */
++		for (i=0;i<11;i++) {
++			val8 = prm->p.ipi[i];
++			pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
++		}
++		break;
++	default:
++		break;
++	}
++	/* length */
++	val8 = (u8)my_len-2;
++	rtw_set_fixed_ie(plen, 1, &val8, &i); /* use variable i to ignore it */
++
++	pattr->pktlen += my_len;
++	pattr->last_txcmdsz = pattr->pktlen;
++	dump_mgntframe(padapter, pmgntframe);
++
++	return _SUCCESS;
++}
++
++void rtw_ap_parse_sta_rm_en_cap(_adapter *padapter,
++	struct sta_info *psta, struct rtw_ieee802_11_elems *elem)
++{
++	if (elem->rm_en_cap) {
++		RTW_INFO("assoc.rm_en_cap="RM_CAP_FMT"\n",
++			RM_CAP_ARG(elem->rm_en_cap));
++		_rtw_memcpy(psta->rm_en_cap,
++			(elem->rm_en_cap), elem->rm_en_cap_len);
++	}
++}
++
++void RM_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++	int i;
++
++	_rtw_memcpy(&padapter->rmpriv.rm_en_cap_assoc, pIE->data, pIE->Length);
++	RTW_INFO("assoc.rm_en_cap="RM_CAP_FMT"\n", RM_CAP_ARG(pIE->data));
++}
++
++/* Debug command */
++
++#if (RM_SUPPORT_IWPRIV_DBG)
++static int hex2num(char c)
++{
++	if (c >= '0' && c <= '9')
++		return c - '0';
++	if (c >= 'a' && c <= 'f')
++		return c - 'a' + 10;
++	if (c >= 'A' && c <= 'F')
++		return c - 'A' + 10;
++	return -1;
++}
++
++int hex2byte(const char *hex)
++{
++	int a, b;
++	a = hex2num(*hex++);
++	if (a < 0)
++		return -1;
++	b = hex2num(*hex++);
++	if (b < 0)
++		return -1;
++	return (a << 4) | b;
++}
++
++static char * hwaddr_parse(char *txt, u8 *addr)
++{
++	size_t i;
++
++	for (i = 0; i < ETH_ALEN; i++) {
++		int a;
++
++		a = hex2byte(txt);
++		if (a < 0)
++			return NULL;
++		txt += 2;
++		addr[i] = a;
++		if (i < ETH_ALEN - 1 && *txt++ != ':')
++			return NULL;
++	}
++	return txt;
++}
++
++void rm_dbg_list_sta(_adapter *padapter, char *s)
++{
++	int i;
++	_irqL irqL;
++	struct sta_info *psta;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	_list *plist, *phead;
++
++
++	sprintf(pstr(s), "\n");
++	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++	for (i = 0; i < NUM_STA; i++) {
++		phead = &(pstapriv->sta_hash[i]);
++		plist = get_next(phead);
++
++		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++			psta = LIST_CONTAINOR(plist,
++				struct sta_info, hash_list);
++
++			plist = get_next(plist);
++
++			sprintf(pstr(s), "=========================================\n");
++			sprintf(pstr(s), "mac=" MAC_FMT "\n",
++				MAC_ARG(psta->cmn.mac_addr));
++			sprintf(pstr(s), "state=0x%x, aid=%d, macid=%d\n",
++				psta->state, psta->cmn.aid, psta->cmn.mac_id);
++			sprintf(pstr(s), "rm_cap="RM_CAP_FMT"\n",
++				RM_CAP_ARG(psta->rm_en_cap));
++		}
++
++	}
++	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++	sprintf(pstr(s), "=========================================\n");
++}
++
++void rm_dbg_help(_adapter *padapter, char *s)
++{
++	int i;
++
++
++	sprintf(pstr(s), "\n");
++	sprintf(pstr(s), "rrm list_sta\n");
++	sprintf(pstr(s), "rrm list_meas\n");
++
++	sprintf(pstr(s), "rrm add_meas <aid=1|mac=>,m=<bcn|clm|nhm|nb|link>,rpt=\n");
++	sprintf(pstr(s), "rrm run_meas <aid=1|evid=>\n");
++	sprintf(pstr(s), "rrm del_meas\n");
++
++	sprintf(pstr(s), "rrm run_meas rmid=xxxx,ev=xx\n");
++	sprintf(pstr(s), "rrm activate\n");
++
++	for (i=0;i<RM_EV_max;i++)
++		sprintf(pstr(s), "\t%2d %s\n",i, rm_event_name(i) );
++	sprintf(pstr(s), "\n");
++}
++
++struct sta_info *rm_get_sta(_adapter *padapter, u16 aid, u8* pbssid)
++{
++	int i;
++	_irqL irqL;
++	struct sta_info *psta = NULL;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	_list *plist, *phead;
++
++
++	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++	for (i = 0; i < NUM_STA; i++) {
++		phead = &(pstapriv->sta_hash[i]);
++		plist = get_next(phead);
++
++		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++			psta = LIST_CONTAINOR(plist,
++				struct sta_info, hash_list);
++
++			plist = get_next(plist);
++
++			if (psta->cmn.aid == aid)
++				goto done;
++
++			if (pbssid && _rtw_memcmp(psta->cmn.mac_addr,
++				pbssid, 6))
++				goto done;
++		}
++
++	}
++	psta = NULL;
++done:
++	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++	return psta;
++}
++
++static int rm_dbg_modify_meas(_adapter *padapter, char *s)
++{
++	struct rm_priv *prmpriv = &padapter->rmpriv;
++	struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;
++	struct rm_obj *prm;
++	struct sta_info *psta;
++	char *pmac, *ptr, *paid, *prpt, *pnbp, *pclm, *pnhm, *pbcn, *plnk;
++	unsigned val;
++	u8 bssid[ETH_ALEN];
++
++
++	/* example :
++	* rrm add_meas <aid=1|mac=>,m=<nb|clm|nhm|bcn|link>,<rept=>
++	* rrm run_meas <aid=1|evid=>
++	*/
++	paid = strstr(s, "aid=");
++	pmac = strstr(s, "mac=");
++	pbcn = strstr(s, "m=bcn");
++	pclm = strstr(s, "m=clm");
++	pnhm = strstr(s, "m=nhm");
++	pnbp = strstr(s, "m=nb");
++	plnk = strstr(s, "m=link");
++	prpt = strstr(s, "rpt=");
++
++	/* set all ',' to NULL (end of line) */
++	ptr = s;
++	while (ptr) {
++		ptr = strchr(ptr, ',');
++		if (ptr) {
++			*(ptr) = 0x0;
++			ptr++;
++		}
++	}
++	prm = (struct rm_obj *)prmpriv->prm_sel;
++	prm->q.m_token = 1;
++	psta = prm->psta;
++
++	if (paid) { /* find sta_info according to aid */
++		paid += 4; /* skip aid= */
++		sscanf(paid, "%u", &val); /* aid=x */
++		psta = rm_get_sta(padapter, val, NULL);
++
++	} else if (pmac) { /* find sta_info according to bssid */
++		pmac += 4; /* skip mac= */
++		if (hwaddr_parse(pmac, bssid) == NULL) {
++			sprintf(pstr(s), "Err: \nincorrect mac format\n");
++			return _FAIL;
++		}
++		psta = rm_get_sta(padapter, 0xff, bssid);
++	}
++
++	if (psta) {
++		prm->psta = psta;
++
++#if 0
++		prm->q.diag_token = psta->rm_diag_token++;
++#else
++		/* TODO dialog should base on sta_info */
++		do {
++			pmlmeinfo->dialogToken++;
++		} while (pmlmeinfo->dialogToken == 0);
++
++		prm->q.diag_token = pmlmeinfo->dialogToken;
++#endif
++		prm->rmid = psta->cmn.aid << 16
++			| prm->q.diag_token << 8
++			| RM_MASTER;
++	} else
++		return _FAIL;
++
++	prm->q.action_code = RM_ACT_RADIO_MEAS_REQ;
++	if (pbcn) {
++		prm->q.m_type = bcn_req;
++	} else if (pnhm) {
++		prm->q.m_type = noise_histo_req;
++	} else if (pclm) {
++		prm->q.m_type = ch_load_req;
++	} else if (pnbp) {
++		prm->q.action_code = RM_ACT_NB_REP_REQ;
++	} else if (plnk) {
++		prm->q.action_code = RM_ACT_LINK_MEAS_REQ;
++	} else
++		return _FAIL;
++
++	if (prpt) {
++		prpt += 4; /* skip rpt= */
++		sscanf(prpt, "%u", &val);
++		prm->q.rpt = (u8)val;
++	}
++
++	return _SUCCESS;
++}
++
++static void rm_dbg_activate_meas(_adapter *padapter, char *s)
++{
++	struct rm_priv *prmpriv = &(padapter->rmpriv);
++	struct rm_obj *prm;
++
++
++	if (prmpriv->prm_sel == NULL) {
++		sprintf(pstr(s), "\nErr: No inActivate measurement\n");
++		return;
++	}
++	prm = (struct rm_obj *)prmpriv->prm_sel;
++
++	/* verify attributes */
++	if (prm->psta == NULL) {
++		sprintf(pstr(s), "\nErr: inActivate meas has no psta\n");
++		return;
++	}
++
++	/* measure current channel */
++	prm->q.ch_num = padapter->mlmeextpriv.cur_channel;
++	prm->q.op_class = rm_get_oper_class_via_ch(prm->q.ch_num);
++
++	/* enquee rmobj */
++	rm_enqueue_rmobj(padapter, prm, _FALSE);
++
++	sprintf(pstr(s), "\nActivate rmid=%x, state=%s, meas_type=%s\n",
++		prm->rmid, rm_state_name(prm->state),
++		rm_type_req_name(prm->q.m_type));
++
++	sprintf(pstr(s), "aid=%d, mac=" MAC_FMT "\n",
++		prm->psta->cmn.aid, MAC_ARG(prm->psta->cmn.mac_addr));
++
++	/* clearn inActivate prm info */
++	prmpriv->prm_sel = NULL;
++}
++
++static void rm_dbg_add_meas(_adapter *padapter, char *s)
++{
++	struct rm_priv *prmpriv = &(padapter->rmpriv);
++	struct rm_obj *prm;
++	char *pact;
++
++
++	/* example :
++	* rrm add_meas <aid=1|mac=>,m=<nb|clm|nhm|link>
++	* rrm run_meas <aid=1|evid=>
++	*/
++	prm = (struct rm_obj *)prmpriv->prm_sel;
++	if (prm == NULL)
++		prm = rm_alloc_rmobj(padapter);
++
++	if (prm == NULL) {
++		sprintf(pstr(s), "\nErr: alloc meas fail\n");
++		return;
++	}
++
++        prmpriv->prm_sel = prm;
++
++	pact = strstr(s, "act");
++	if (rm_dbg_modify_meas(padapter, s) == _FAIL) {
++
++		sprintf(pstr(s), "\nErr: add meas fail\n");
++		rm_free_rmobj(prm);
++		prmpriv->prm_sel = NULL;
++		return;
++	}
++	prm->q.category = RTW_WLAN_CATEGORY_RADIO_MEAS;
++	prm->q.e_id = _MEAS_REQ_IE_; /* 38 */
++
++	sprintf(pstr(s), "\nAdd rmid=%x, meas_type=%s ok\n",
++		prm->rmid, rm_type_req_name(prm->q.m_type));
++
++	if (prm->psta)
++		sprintf(pstr(s), "mac="MAC_FMT"\n",
++			MAC_ARG(prm->psta->cmn.mac_addr));
++
++	if (pact)
++		rm_dbg_activate_meas(padapter, pstr(s));
++}
++
++static void rm_dbg_del_meas(_adapter *padapter, char *s)
++{
++	struct rm_priv *prmpriv = &padapter->rmpriv;
++	struct rm_obj *prm = (struct rm_obj *)prmpriv->prm_sel;
++
++
++	if (prm) {
++		sprintf(pstr(s), "\ndelete rmid=%x\n",prm->rmid);
++
++		/* free inActivate meas - enqueue yet  */
++		prmpriv->prm_sel = NULL;
++		rtw_mfree(prmpriv->prm_sel, sizeof(struct rm_obj));
++	} else
++		sprintf(pstr(s), "Err: no inActivate measurement\n");
++}
++
++static void rm_dbg_run_meas(_adapter *padapter, char *s)
++{
++	struct rm_obj *prm;
++	char *pevid, *prmid;
++	u32 rmid, evid;
++
++
++	prmid = strstr(s, "rmid="); /* hex */
++	pevid = strstr(s, "evid="); /* dec */
++
++	if (prmid && pevid) {
++		prmid += 5; /* rmid= */
++		sscanf(prmid, "%x", &rmid);
++
++		pevid += 5; /* evid= */
++		sscanf(pevid, "%u", &evid);
++	} else {
++		sprintf(pstr(s), "\nErr: incorrect attribute\n");
++		return;
++	}
++
++	prm = rm_get_rmobj(padapter, rmid);
++
++	if (!prm) {
++		sprintf(pstr(s), "\nErr: measurement not found\n");
++		return;
++	}
++
++	if (evid >= RM_EV_max) {
++		sprintf(pstr(s), "\nErr: wrong event id\n");
++		return;
++	}
++
++	rm_post_event(padapter, prm->rmid, evid);
++	sprintf(pstr(s), "\npost %s to rmid=%x\n",rm_event_name(evid), rmid);
++}
++
++static void rm_dbg_show_meas(struct rm_obj *prm, char *s)
++{
++	struct sta_info *psta;
++
++	psta = prm->psta;
++
++	if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
++
++		sprintf(pstr(s), "\nrmid=%x, meas_type=%s\n",
++			prm->rmid, rm_type_req_name(prm->q.m_type));
++
++	} else  if (prm->q.action_code == RM_ACT_NB_REP_REQ) {
++
++		sprintf(pstr(s), "\nrmid=%x, action=neighbor_req\n",
++			prm->rmid);
++	} else
++		sprintf(pstr(s), "\nrmid=%x, action=unknown\n",
++			prm->rmid);
++
++	if (psta)
++		sprintf(pstr(s), "aid=%d, mac="MAC_FMT"\n",
++			psta->cmn.aid, MAC_ARG(psta->cmn.mac_addr));
++
++	sprintf(pstr(s), "clock=%d, state=%s, rpt=%u/%u\n",
++		(int)ATOMIC_READ(&prm->pclock->counter),
++		rm_state_name(prm->state), prm->p.rpt, prm->q.rpt);
++}
++
++static void rm_dbg_list_meas(_adapter *padapter, char *s)
++{
++	int meas_amount;
++	_irqL irqL;
++	struct rm_obj *prm;
++	struct sta_info *psta;
++	struct rm_priv *prmpriv = &padapter->rmpriv;
++	_queue *queue = &prmpriv->rm_queue;
++	_list *plist, *phead;
++
++
++	sprintf(pstr(s), "\n");
++	_enter_critical(&queue->lock, &irqL);
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++	meas_amount = 0;
++
++	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++		prm = LIST_CONTAINOR(plist, struct rm_obj, list);
++		meas_amount++;
++		plist = get_next(plist);
++		psta = prm->psta;
++		sprintf(pstr(s), "=========================================\n");
++
++		rm_dbg_show_meas(prm, s);
++	}
++	_exit_critical(&queue->lock, &irqL);
++
++	sprintf(pstr(s), "=========================================\n");
++
++	if (meas_amount==0) {
++		sprintf(pstr(s), "No Activate measurement\n");
++		sprintf(pstr(s), "=========================================\n");
++	}
++
++	if (prmpriv->prm_sel == NULL)
++		sprintf(pstr(s), "\nNo inActivate measurement\n");
++	else {
++		sprintf(pstr(s), "\ninActivate measurement\n");
++		rm_dbg_show_meas((struct rm_obj *)prmpriv->prm_sel, s);
++	}
++}
++#endif /* RM_SUPPORT_IWPRIV_DBG */
++
++void rm_dbg_cmd(_adapter *padapter, char *s)
++{
++	unsigned val;
++	char *paid;
++	struct sta_info *psta=NULL;
++
++#if (RM_SUPPORT_IWPRIV_DBG)
++	if (_rtw_memcmp(s, "help", 4)) {
++		rm_dbg_help(padapter, s);
++
++	} else if (_rtw_memcmp(s, "list_sta", 8)) {
++		rm_dbg_list_sta(padapter, s);
++
++	} else if (_rtw_memcmp(s, "list_meas", 9)) {
++		rm_dbg_list_meas(padapter, s);
++
++	} else if (_rtw_memcmp(s, "add_meas", 8)) {
++		rm_dbg_add_meas(padapter, s);
++
++	} else if (_rtw_memcmp(s, "del_meas", 8)) {
++		rm_dbg_del_meas(padapter, s);
++
++	} else if (_rtw_memcmp(s, "activate", 8)) {
++		rm_dbg_activate_meas(padapter, s);
++
++	} else if (_rtw_memcmp(s, "run_meas", 8)) {
++		rm_dbg_run_meas(padapter, s);
++
++	} else if (_rtw_memcmp(s, "nb", 2)) {
++
++		paid = strstr(s, "aid=");
++
++		if (paid) { /* find sta_info according to aid */
++			paid += 4; /* skip aid= */
++			sscanf(paid, "%u", &val); /* aid=x */
++			psta = rm_get_sta(padapter, val, NULL);
++
++			if (psta)
++				rm_add_nb_req(padapter, psta);
++		}
++	}
++#else
++	sprintf(pstr(s), "\n");
++	sprintf(pstr(s), "rrm debug command was disabled\n");
++#endif
++}
++#endif /* CONFIG_RTW_80211K */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_rm_fsm.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_rm_fsm.c
+new file mode 100644
+index 000000000..3e2dd8a24
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_rm_fsm.c
+@@ -0,0 +1,1016 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <drv_types.h>
++#include <hal_data.h>
++#ifdef CONFIG_RTW_80211K
++#include "rtw_rm_fsm.h"
++#include "rtw_rm_util.h"
++
++struct fsm_state {
++	u8 *name;
++	int(*fsm_func)(struct rm_obj *prm, enum RM_EV_ID evid);
++};
++
++static void rm_state_initial(struct rm_obj *prm);
++static void rm_state_goto(struct rm_obj *prm, enum RM_STATE rm_state);
++static void rm_state_run(struct rm_obj *prm, enum RM_EV_ID evid);
++static struct rm_event *rm_dequeue_ev(_queue *queue);
++static struct rm_obj *rm_dequeue_rm(_queue *queue);
++
++void rm_timer_callback(void *data)
++{
++	int i;
++	_adapter *padapter = (_adapter *)data;
++	struct rm_priv *prmpriv = &padapter->rmpriv;
++	struct rm_clock *pclock;
++
++
++	/* deal with clock */
++	for (i=0;i<RM_TIMER_NUM;i++) {
++		pclock = &prmpriv->clock[i];
++		if (pclock->prm == NULL
++			||(ATOMIC_READ(&(pclock->counter)) == 0))
++			continue;
++
++		ATOMIC_DEC(&(pclock->counter));
++
++		if (ATOMIC_READ(&(pclock->counter)) == 0)
++			rm_post_event(pclock->prm->psta->padapter,
++				pclock->prm->rmid, prmpriv->clock[i].evid);
++	}
++	_set_timer(&prmpriv->rm_timer, CLOCK_UNIT);
++}
++
++int rtw_init_rm(_adapter *padapter)
++{
++	struct rm_priv *prmpriv = &padapter->rmpriv;
++
++
++	RTW_INFO("RM: %s\n",__func__);
++	_rtw_init_queue(&(prmpriv->rm_queue));
++	_rtw_init_queue(&(prmpriv->ev_queue));
++
++	/* bit 0-7 */
++	prmpriv->rm_en_cap_def[0] = 0
++		| BIT(RM_LINK_MEAS_CAP_EN)
++		| BIT(RM_NB_REP_CAP_EN)
++		/*| BIT(RM_PARAL_MEAS_CAP_EN)*/
++		| BIT(RM_REPEAT_MEAS_CAP_EN)
++		| BIT(RM_BCN_PASSIVE_MEAS_CAP_EN)
++		| BIT(RM_BCN_ACTIVE_MEAS_CAP_EN)
++		| BIT(RM_BCN_TABLE_MEAS_CAP_EN)
++		/*| BIT(RM_BCN_MEAS_REP_COND_CAP_EN)*/;
++
++	/* bit  8-15 */
++	prmpriv->rm_en_cap_def[1] = 0
++		/*| BIT(RM_FRAME_MEAS_CAP_EN - 8)*/
++#ifdef CONFIG_RTW_ACS
++		| BIT(RM_CH_LOAD_CAP_EN - 8)
++		| BIT(RM_NOISE_HISTO_CAP_EN - 8)
++#endif
++		/*| BIT(RM_STATIS_MEAS_CAP_EN - 8)*/
++		/*| BIT(RM_LCI_MEAS_CAP_EN - 8)*/
++		/*| BIT(RM_LCI_AMIMUTH_CAP_EN - 8)*/
++		/*| BIT(RM_TRANS_STREAM_CAT_MEAS_CAP_EN - 8)*/
++		/*| BIT(RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN - 8)*/;
++
++	/* bit 16-23 */
++	prmpriv->rm_en_cap_def[2] = 0
++		/*| BIT(RM_AP_CH_REP_CAP_EN - 16)*/
++		/*| BIT(RM_RM_MIB_CAP_EN - 16)*/
++		/*| BIT(RM_OP_CH_MAX_MEAS_DUR0 - 16)*/
++		/*| BIT(RM_OP_CH_MAX_MEAS_DUR1 - 16)*/
++		/*| BIT(RM_OP_CH_MAX_MEAS_DUR2 - 16)*/
++		/*| BIT(RM_NONOP_CH_MAX_MEAS_DUR0 - 16)*/
++		/*| BIT(RM_NONOP_CH_MAX_MEAS_DUR1 - 16)*/
++		/*| BIT(RM_NONOP_CH_MAX_MEAS_DUR2 - 16)*/;
++
++	/* bit 24-31 */
++	prmpriv->rm_en_cap_def[3] = 0
++		/*| BIT(RM_MEAS_PILOT_CAP0 - 24)*/
++		/*| BIT(RM_MEAS_PILOT_CAP1 - 24)*/
++		/*| BIT(RM_MEAS_PILOT_CAP2 - 24)*/
++		/*| BIT(RM_MEAS_PILOT_TRANS_INFO_CAP_EN - 24)*/
++		/*| BIT(RM_NB_REP_TSF_OFFSET_CAP_EN - 24)*/
++		| BIT(RM_RCPI_MEAS_CAP_EN - 24)
++		| BIT(RM_RSNI_MEAS_CAP_EN - 24)
++		/*| BIT(RM_BSS_AVG_ACCESS_DELAY_CAP_EN - 24)*/;
++
++	/* bit 32-39 */
++	prmpriv->rm_en_cap_def[4] = 0
++		/*| BIT(RM_BSS_AVG_ACCESS_DELAY_CAP_EN - 32)*/
++		/*| BIT(RM_AVALB_ADMIS_CAPACITY_CAP_EN - 32)*/
++		/*| BIT(RM_ANT_CAP_EN - 32)*/;
++
++	prmpriv->enable = _TRUE;
++
++	/* clock timer */
++	rtw_init_timer(&prmpriv->rm_timer,
++		padapter, rm_timer_callback, padapter);
++	_set_timer(&prmpriv->rm_timer, CLOCK_UNIT);
++
++	return _SUCCESS;
++}
++
++int rtw_deinit_rm(_adapter *padapter)
++{
++	struct rm_priv *prmpriv = &padapter->rmpriv;
++	struct rm_obj *prm;
++	struct rm_event *pev;
++
++
++	RTW_INFO("RM: %s\n",__func__);
++	prmpriv->enable = _FALSE;
++	_cancel_timer_ex(&prmpriv->rm_timer);
++
++	/* free all events and measurements */
++	while((pev = rm_dequeue_ev(&prmpriv->ev_queue)) != NULL)
++		rtw_mfree((void *)pev, sizeof(struct rm_event));
++
++	while((prm = rm_dequeue_rm(&prmpriv->rm_queue)) != NULL)
++		rm_state_run(prm, RM_EV_cancel);
++
++	_rtw_deinit_queue(&(prmpriv->rm_queue));
++	_rtw_deinit_queue(&(prmpriv->ev_queue));
++
++	return _SUCCESS;
++}
++
++int rtw_free_rm_priv(_adapter *padapter)
++{
++	return rtw_deinit_rm(padapter);
++}
++
++static int rm_enqueue_ev(_queue *queue, struct rm_event *obj, bool to_head)
++{
++	_irqL irqL;
++
++
++	if (obj == NULL)
++		return _FAIL;
++
++	_enter_critical(&queue->lock, &irqL);
++
++	if (to_head)
++		rtw_list_insert_head(&obj->list, &queue->queue);
++	else
++		rtw_list_insert_tail(&obj->list, &queue->queue);
++
++	_exit_critical(&queue->lock, &irqL);
++
++	return _SUCCESS;
++}
++
++static void rm_set_clock(struct rm_obj *prm, u32 ms, enum RM_EV_ID evid)
++{
++	ATOMIC_SET(&(prm->pclock->counter), (ms/CLOCK_UNIT));
++	prm->pclock->evid = evid;
++}
++
++static struct rm_clock *rm_alloc_clock(_adapter *padapter, struct rm_obj *prm)
++{
++	int i;
++	struct rm_priv *prmpriv = &padapter->rmpriv;
++	struct rm_clock *pclock = NULL;
++
++
++	for (i=0;i<RM_TIMER_NUM;i++) {
++		pclock = &prmpriv->clock[i];
++
++		if (pclock->prm == NULL) {
++			pclock->prm = prm;
++			ATOMIC_SET(&(pclock->counter), 0);
++			pclock->evid = RM_EV_max;
++			break;
++		}
++	}
++	return pclock;
++}
++
++static void rm_cancel_clock(struct rm_obj *prm)
++{
++	ATOMIC_SET(&(prm->pclock->counter), 0);
++	prm->pclock->evid = RM_EV_max;
++}
++
++static void rm_free_clock(struct rm_clock *pclock)
++{
++	pclock->prm = NULL;
++	ATOMIC_SET(&(pclock->counter), 0);
++	pclock->evid = RM_EV_max;
++}
++
++static int is_list_linked(const struct list_head *head)
++{
++	return head->prev != NULL;
++}
++
++void rm_free_rmobj(struct rm_obj *prm)
++{
++	if (is_list_linked(&prm->list))
++		rtw_list_delete(&prm->list);
++
++	if (prm->q.pssid)
++		rtw_mfree(prm->q.pssid, strlen(prm->q.pssid)+1);
++
++	if (prm->q.opt.bcn.req_start)
++		rtw_mfree(prm->q.opt.bcn.req_start,
++			prm->q.opt.bcn.req_len);
++
++	if (prm->pclock)
++		rm_free_clock(prm->pclock);
++
++	rtw_mfree((void *)prm, sizeof(struct rm_obj));
++}
++
++struct rm_obj *rm_alloc_rmobj(_adapter *padapter)
++{
++	struct rm_obj *prm;
++
++
++	prm = (struct rm_obj *)rtw_malloc(sizeof(struct rm_obj));
++	if (prm == NULL)
++		return NULL;
++
++	_rtw_memset(prm, 0, sizeof(struct rm_obj));
++
++	/* alloc timer */
++	if ((prm->pclock = rm_alloc_clock(padapter, prm)) == NULL) {
++		rm_free_rmobj(prm);
++		return NULL;
++	}
++	return prm;
++}
++
++int rm_enqueue_rmobj(_adapter *padapter, struct rm_obj *prm, bool to_head)
++{
++	_irqL irqL;
++	struct rm_priv *prmpriv = &padapter->rmpriv;
++	_queue *queue = &prmpriv->rm_queue;
++
++
++	if (prm == NULL)
++		return _FAIL;
++
++	_enter_critical(&queue->lock, &irqL);
++	if (to_head)
++		rtw_list_insert_head(&prm->list, &queue->queue);
++	else
++		rtw_list_insert_tail(&prm->list, &queue->queue);
++	_exit_critical(&queue->lock, &irqL);
++
++	rm_state_initial(prm);
++
++	return _SUCCESS;
++}
++
++static struct rm_obj *rm_dequeue_rm(_queue *queue)
++{
++	_irqL irqL;
++	struct rm_obj *prm;
++
++
++	_enter_critical(&queue->lock, &irqL);
++	if (rtw_is_list_empty(&(queue->queue)))
++		prm = NULL;
++	else {
++		prm = LIST_CONTAINOR(get_next(&(queue->queue)),
++			struct rm_obj, list);
++		/* rtw_list_delete(&prm->list); */
++	}
++	_exit_critical(&queue->lock, &irqL);
++
++	return prm;
++}
++
++static struct rm_event *rm_dequeue_ev(_queue *queue)
++{
++	_irqL irqL;
++	struct rm_event *ev;
++
++
++	_enter_critical(&queue->lock, &irqL);
++	if (rtw_is_list_empty(&(queue->queue)))
++		ev = NULL;
++	else {
++		ev = LIST_CONTAINOR(get_next(&(queue->queue)),
++			struct rm_event, list);
++		rtw_list_delete(&ev->list);
++	}
++	_exit_critical(&queue->lock, &irqL);
++
++	return ev;
++}
++
++static struct rm_obj *_rm_get_rmobj(_queue *queue, u32 rmid)
++{
++	_irqL irqL;
++	_list *phead, *plist;
++	struct rm_obj *prm = NULL;
++
++
++	if (rmid == 0)
++		return NULL;
++
++	_enter_critical(&queue->lock, &irqL);
++
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++
++		prm = LIST_CONTAINOR(plist, struct rm_obj, list);
++		if (rmid == (prm->rmid)) {
++			_exit_critical(&queue->lock, &irqL);
++			return prm;
++		}
++		plist = get_next(plist);
++	}
++	_exit_critical(&queue->lock, &irqL);
++
++	return NULL;
++}
++
++struct sta_info *rm_get_psta(_adapter *padapter, u32 rmid)
++{
++	struct rm_priv *prmpriv = &padapter->rmpriv;
++	struct rm_obj *prm;
++
++
++	prm = _rm_get_rmobj(&prmpriv->rm_queue, rmid);
++
++	if (prm)
++		return prm->psta;
++
++	return NULL;
++}
++
++struct rm_obj *rm_get_rmobj(_adapter *padapter, u32 rmid)
++{
++	struct rm_priv *prmpriv = &padapter->rmpriv;
++
++	return _rm_get_rmobj(&prmpriv->rm_queue, rmid);
++}
++
++u8 rtw_rm_post_envent_cmd(_adapter *padapter, u32 rmid, u8 evid)
++{
++	struct cmd_obj *pcmd;
++	struct rm_event *pev;
++	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++	u8 res = _SUCCESS;
++
++
++	pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (pcmd == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++	pev = (struct rm_event*)rtw_zmalloc(sizeof(struct rm_event));
++
++	if (pev == NULL) {
++		rtw_mfree((u8 *) pcmd, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++	pev->rmid = rmid;
++	pev->evid = evid;
++
++	init_h2fwcmd_w_parm_no_rsp(pcmd, pev, CMD_RM_POST_EVENT);
++	res = rtw_enqueue_cmd(pcmdpriv, pcmd);
++exit:
++	return res;
++}
++
++int rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid)
++{
++	if (padapter->rmpriv.enable == _FALSE)
++		return _FALSE;
++
++	RTW_INFO("RM: post asyn %s to rmid=%x\n", rm_event_name(evid), rmid);
++	rtw_rm_post_envent_cmd(padapter, rmid, evid);
++	return _SUCCESS;
++}
++
++int _rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid)
++{
++	struct rm_priv *prmpriv = &padapter->rmpriv;
++	struct rm_event *pev;
++
++	if (evid >= RM_EV_max || rmid == 0)
++		return _FALSE;
++
++	pev = (struct rm_event *)rtw_malloc(sizeof(struct rm_event));
++	if (pev == NULL)
++		return _FALSE;
++
++	pev->rmid = rmid;
++	pev->evid = evid;
++
++	RTW_INFO("RM: post sync %s to rmid=%x\n", rm_event_name(evid), rmid);
++	rm_enqueue_ev(&prmpriv->ev_queue, pev, FALSE);
++
++	return _SUCCESS;
++}
++
++static void rm_bcast_aid_handler(_adapter *padapter, struct rm_event *pev)
++{
++	_irqL irqL;
++	_list *phead, *plist;
++	_queue *queue = &padapter->rmpriv.rm_queue;
++	struct rm_obj *prm;
++
++
++	_enter_critical(&queue->lock, &irqL);
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++
++		prm = LIST_CONTAINOR(plist, struct rm_obj, list);
++		plist = get_next(plist);
++		if (RM_GET_AID(pev->rmid) == RM_GET_AID(prm->rmid)) {
++			_exit_critical(&queue->lock, &irqL);
++			rm_state_run(prm, pev->evid);
++			_enter_critical(&queue->lock, &irqL);
++		}
++	}
++	_exit_critical(&queue->lock, &irqL);
++	return;
++}
++
++/* main handler of RM (Resource Management) */
++void rm_handler(_adapter *padapter, struct rm_event *pe)
++{
++	int i;
++	struct rm_priv *prmpriv = &padapter->rmpriv;
++	struct rm_obj *prm;
++	struct rm_event *pev;
++
++
++	/* dequeue event */
++	while((pev = rm_dequeue_ev(&prmpriv->ev_queue)) != NULL)
++	{
++		if (RM_IS_ID_FOR_ALL(pev->rmid)) {
++			/* apply to all aid mateched measurement */
++			rm_bcast_aid_handler(padapter, pev);
++			rtw_mfree((void *)pev, sizeof(struct rm_event));
++			continue;
++		}
++
++		/* retrieve rmobj */
++		prm = _rm_get_rmobj(&prmpriv->rm_queue, pev->rmid);
++		if (prm == NULL) {
++			RTW_ERR("RM: rmid=%x event=%s doesn't find rm obj\n",
++				pev->rmid, rm_event_name(pev->evid));
++			rtw_mfree((void *)pev, sizeof(struct rm_event));
++			return;
++		}
++		/* run state machine */
++		rm_state_run(prm, pev->evid);
++		rtw_mfree((void *)pev, sizeof(struct rm_event));
++	}
++}
++
++static int rm_issue_meas_req(struct rm_obj *prm)
++{
++	switch (prm->q.action_code) {
++	case RM_ACT_RADIO_MEAS_REQ:
++		switch (prm->q.m_type) {
++		case bcn_req:
++		case ch_load_req:
++		case noise_histo_req:
++			issue_radio_meas_req(prm);
++			break;
++		default:
++			break;
++		} /* meas_type */
++		break;
++	case RM_ACT_NB_REP_REQ:
++		/* issue neighbor request */
++		issue_nb_req(prm);
++		break;
++	case RM_ACT_LINK_MEAS_REQ:
++		issue_link_meas_req(prm);
++		break;
++	default:
++		return _FALSE;
++	} /* action_code */
++
++	return _SUCCESS;
++}
++
++/*
++* RM state machine
++*/
++
++static int rm_state_idle(struct rm_obj *prm, enum RM_EV_ID evid)
++{
++	_adapter *padapter = prm->psta->padapter;
++	u8 val8;
++	u32 val32;
++
++
++	prm->p.category = RTW_WLAN_CATEGORY_RADIO_MEAS;
++
++	switch (evid) {
++	case RM_EV_state_in:
++		switch (prm->q.action_code) {
++		case RM_ACT_RADIO_MEAS_REQ:
++			/* copy attrib from meas_req to meas_rep */
++			prm->p.action_code = RM_ACT_RADIO_MEAS_REP;
++			prm->p.diag_token = prm->q.diag_token;
++			prm->p.e_id = _MEAS_RSP_IE_;
++			prm->p.m_token = prm->q.m_token;
++			prm->p.m_type = prm->q.m_type;
++			prm->p.rpt = prm->q.rpt;
++			prm->p.ch_num = prm->q.ch_num;
++			prm->p.op_class = prm->q.op_class;
++
++			if (prm->q.m_type == ch_load_req
++				|| prm->q.m_type == noise_histo_req) {
++				/*
++				 * phydm measure current ch periodically
++				 * scan current ch is not necessary
++				 */
++				val8 = padapter->mlmeextpriv.cur_channel;
++				if (prm->q.ch_num == val8)
++					prm->poll_mode = 1;
++			}
++			RTW_INFO("RM: rmid=%x %s switch in repeat=%u\n",
++				prm->rmid, rm_type_req_name(prm->q.m_type),
++				prm->q.rpt);
++			break;
++		case RM_ACT_NB_REP_REQ:
++			prm->p.action_code = RM_ACT_NB_REP_RESP;
++			RTW_INFO("RM: rmid=%x Neighbor request switch in\n",
++				prm->rmid);
++			break;
++		case RM_ACT_LINK_MEAS_REQ:
++			prm->p.diag_token = prm->q.diag_token;
++			prm->p.action_code = RM_ACT_LINK_MEAS_REP;
++			RTW_INFO("RM: rmid=%x Link meas switch in\n",
++				prm->rmid);
++			break;
++		default:
++			prm->p.action_code = prm->q.action_code;
++			rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
++			RTW_INFO("RM: rmid=%x recv unknown action %d\n",
++				prm->rmid,prm->p.action_code);
++			break;
++		} /* switch() */
++
++		if (prm->rmid & RM_MASTER) {
++			if (rm_issue_meas_req(prm) == _SUCCESS)
++				rm_state_goto(prm, RM_ST_WAIT_MEAS);
++			else
++				rm_state_goto(prm, RM_ST_END);
++			return _SUCCESS;
++		} else {
++			rm_state_goto(prm, RM_ST_DO_MEAS);
++			return _SUCCESS;
++		}
++
++		if (prm->p.m_mode) {
++			issue_null_reply(prm);
++			rm_state_goto(prm, RM_ST_END);
++			return _SUCCESS;
++		}
++		if (prm->q.rand_intvl) {
++			/* get low tsf to generate random interval */
++			val32 = rtw_read32(padapter, REG_TSFTR);
++			val32 = val32 % prm->q.rand_intvl;
++			RTW_INFO("RM: rmid=%x rand_intval=%d, rand=%d\n",
++				prm->rmid, (int)prm->q.rand_intvl,val32);
++			rm_set_clock(prm, prm->q.rand_intvl,
++				RM_EV_delay_timer_expire);
++			return _SUCCESS;
++		}
++		break;
++	case RM_EV_delay_timer_expire:
++		rm_state_goto(prm, RM_ST_DO_MEAS);
++		break;
++	case RM_EV_cancel:
++		rm_state_goto(prm, RM_ST_END);
++		break;
++	case RM_EV_state_out:
++		rm_cancel_clock(prm);
++		break;
++	default:
++		break;
++	}
++	return _SUCCESS;
++}
++
++/* we do the measuring */
++static int rm_state_do_meas(struct rm_obj *prm, enum RM_EV_ID evid)
++{
++	_adapter *padapter = prm->psta->padapter;
++	u8 val8;
++	u64 val64;
++
++
++	switch (evid) {
++	case RM_EV_state_in:
++		if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
++			switch (prm->q.m_type) {
++			case bcn_req:
++				if (prm->q.m_mode == bcn_req_bcn_table) {
++					RTW_INFO("RM: rmid=%x Beacon table\n",
++						prm->rmid);
++					_rm_post_event(padapter, prm->rmid,
++						RM_EV_survey_done);
++					return _SUCCESS;
++				}
++				break;
++			case ch_load_req:
++			case noise_histo_req:
++				if (prm->poll_mode)
++					_rm_post_event(padapter, prm->rmid,
++						RM_EV_survey_done);
++				return _SUCCESS;
++			default:
++				rm_state_goto(prm, RM_ST_END);
++				return _SUCCESS;
++			}
++
++			if (!ready_for_scan(prm)) {
++				prm->wait_busy = RM_BUSY_TRAFFIC_TIMES;
++				RTW_INFO("RM: wait busy traffic - %d\n",
++					prm->wait_busy);
++				rm_set_clock(prm, RM_WAIT_BUSY_TIMEOUT,
++					RM_EV_busy_timer_expire);
++				return _SUCCESS;
++			}
++		} else if (prm->q.action_code == RM_ACT_LINK_MEAS_REQ) {
++			; /* do nothing */
++			rm_state_goto(prm, RM_ST_SEND_REPORT);
++			return _SUCCESS;
++		}
++		_rm_post_event(padapter, prm->rmid, RM_EV_start_meas);
++		break;
++	case RM_EV_start_meas:
++		if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
++			/* resotre measurement start time */
++			prm->meas_start_time = rtw_hal_get_tsftr_by_port(padapter
++									, rtw_hal_get_port(padapter));
++
++			switch (prm->q.m_type) {
++			case bcn_req:
++				val8 = 1; /* Enable free run counter */
++				prm->free_run_counter_valid = rtw_hal_set_hwreg(
++					padapter, HW_VAR_FREECNT, &val8);
++
++				rm_sitesurvey(prm);
++				break;
++			case ch_load_req:
++			case noise_histo_req:
++				rm_sitesurvey(prm);
++				break;
++			default:
++				rm_state_goto(prm, RM_ST_END);
++				return _SUCCESS;
++				break;
++			}
++		}
++		/* handle measurement timeout */
++		rm_set_clock(prm, RM_MEAS_TIMEOUT, RM_EV_meas_timer_expire);
++		break;
++	case RM_EV_survey_done:
++		if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
++			switch (prm->q.m_type) {
++			case bcn_req:
++				rm_cancel_clock(prm);
++				rm_state_goto(prm, RM_ST_SEND_REPORT);
++				return _SUCCESS;
++			case ch_load_req:
++			case noise_histo_req:
++				retrieve_radio_meas_result(prm);
++
++				if (rm_radio_meas_report_cond(prm) == _SUCCESS)
++					rm_state_goto(prm, RM_ST_SEND_REPORT);
++				else
++					rm_set_clock(prm, RM_COND_INTVL,
++						RM_EV_retry_timer_expire);
++				break;
++			default:
++				rm_state_goto(prm, RM_ST_END);
++				return _SUCCESS;
++			}
++		}
++		break;
++	case RM_EV_meas_timer_expire:
++		RTW_INFO("RM: rmid=%x measurement timeount\n",prm->rmid);
++		rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);
++		issue_null_reply(prm);
++		rm_state_goto(prm, RM_ST_END);
++		break;
++	case RM_EV_busy_timer_expire:
++		if (!ready_for_scan(prm) && prm->wait_busy--) {
++			RTW_INFO("RM: wait busy - %d\n",prm->wait_busy);
++			rm_set_clock(prm, RM_WAIT_BUSY_TIMEOUT,
++				RM_EV_busy_timer_expire);
++			break;
++		}
++		else if (prm->wait_busy <= 0) {
++			RTW_INFO("RM: wait busy timeout\n");
++			rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);
++			issue_null_reply(prm);
++			rm_state_goto(prm, RM_ST_END);
++			return _SUCCESS;
++		}
++		_rm_post_event(padapter, prm->rmid, RM_EV_start_meas);
++		break;
++	case RM_EV_request_timer_expire:
++		rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);
++		issue_null_reply(prm);
++		rm_state_goto(prm, RM_ST_END);
++		break;
++	case RM_EV_retry_timer_expire:
++		/* expired due to meas condition mismatch, meas again */
++		_rm_post_event(padapter, prm->rmid, RM_EV_start_meas);
++		break;
++	case RM_EV_cancel:
++		rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);
++		issue_null_reply(prm);
++		rm_state_goto(prm, RM_ST_END);
++		break;
++	case RM_EV_state_out:
++		rm_cancel_clock(prm);
++		/* resotre measurement end time */
++		prm->meas_end_time = rtw_hal_get_tsftr_by_port(padapter
++								, rtw_hal_get_port(padapter));
++
++		val8 = 0; /* Disable free run counter */
++		rtw_hal_set_hwreg(padapter, HW_VAR_FREECNT, &val8);
++		break;
++	default:
++		break;
++	}
++
++	return _SUCCESS;
++}
++
++static int rm_state_wait_meas(struct rm_obj *prm, enum RM_EV_ID evid)
++{
++	u8 val8;
++	u64 val64;
++
++
++	switch (evid) {
++	case RM_EV_state_in:
++		/* we create meas_req, waiting for peer report */
++		rm_set_clock(prm, RM_REQ_TIMEOUT,
++			RM_EV_request_timer_expire);
++		break;
++	case RM_EV_recv_rep:
++		rm_state_goto(prm, RM_ST_RECV_REPORT);
++		break;
++	case RM_EV_request_timer_expire:
++	case RM_EV_cancel:
++		rm_state_goto(prm, RM_ST_END);
++		break;
++	case RM_EV_state_out:
++		rm_cancel_clock(prm);
++		break;
++	default:
++		break;
++	}
++	return _SUCCESS;
++}
++
++static int rm_state_send_report(struct rm_obj *prm, enum RM_EV_ID evid)
++{
++	u8 val8;
++
++
++	switch (evid) {
++	case RM_EV_state_in:
++		/* we have to issue report */
++		if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
++			switch (prm->q.m_type) {
++			case bcn_req:
++				issue_beacon_rep(prm);
++				break;
++			case ch_load_req:
++			case noise_histo_req:
++				issue_radio_meas_rep(prm);
++				break;
++			default:
++				rm_state_goto(prm, RM_ST_END);
++				return _SUCCESS;
++			}
++
++		} else if (prm->q.action_code == RM_ACT_LINK_MEAS_REQ) {
++			issue_link_meas_rep(prm);
++			rm_state_goto(prm, RM_ST_END);
++			return _SUCCESS;
++
++		} else {
++			rm_state_goto(prm, RM_ST_END);
++			return _SUCCESS;
++		}
++
++		/* check repeat */
++		if (prm->p.rpt) {
++			RTW_INFO("RM: rmid=%x repeat=%u/%u\n",
++				prm->rmid, prm->p.rpt,
++				prm->q.rpt);
++			prm->p.rpt--;
++			/*
++			* we recv meas_req,
++			* delay for a wihile and than meas again
++			*/
++			if (prm->poll_mode)
++				rm_set_clock(prm, RM_REPT_POLL_INTVL,
++					RM_EV_repeat_delay_expire);
++			else
++				rm_set_clock(prm, RM_REPT_SCAN_INTVL,
++					RM_EV_repeat_delay_expire);
++			return _SUCCESS;
++		}
++		/* we are done */
++		rm_state_goto(prm, RM_ST_END);
++		break;
++	case RM_EV_repeat_delay_expire:
++		rm_state_goto(prm, RM_ST_DO_MEAS);
++		break;
++	case RM_EV_cancel:
++		rm_state_goto(prm, RM_ST_END);
++		break;
++	case RM_EV_state_out:
++		rm_cancel_clock(prm);
++		break;
++	default:
++		break;
++	}
++	return _SUCCESS;
++}
++
++static int rm_state_recv_report(struct rm_obj *prm, enum RM_EV_ID evid)
++{
++	u8 val8;
++
++
++	switch (evid) {
++	case RM_EV_state_in:
++		/* we issue meas_req, got peer's meas report */
++		switch (prm->p.action_code) {
++		case RM_ACT_RADIO_MEAS_REP:
++			/* check refuse, incapable and repeat */
++			val8 = prm->p.m_mode;
++			if (val8) {
++				RTW_INFO("RM: rmid=%x peer reject (%s repeat=%d)\n",
++					prm->rmid,
++					val8|MEAS_REP_MOD_INCAP?"INCAP":
++					val8|MEAS_REP_MOD_REFUSE?"REFUSE":
++					val8|MEAS_REP_MOD_LATE?"LATE":"",
++					prm->p.rpt);
++				rm_state_goto(prm, RM_ST_END);
++				return _SUCCESS;
++			}
++			break;
++		case RM_ACT_NB_REP_RESP:
++			/* report to upper layer if needing */
++			rm_state_goto(prm, RM_ST_END);
++			return _SUCCESS;
++		default:
++			rm_state_goto(prm, RM_ST_END);
++			return _SUCCESS;
++		}
++		/* check repeat */
++		if (prm->p.rpt) {
++			RTW_INFO("RM: rmid=%x repeat=%u/%u\n",
++				prm->rmid, prm->p.rpt,
++				prm->q.rpt);
++			prm->p.rpt--;
++			/* waitting more report */
++			rm_state_goto(prm, RM_ST_WAIT_MEAS);
++			break;
++		}
++		/* we are done */
++		rm_state_goto(prm, RM_ST_END);
++		break;
++	case RM_EV_cancel:
++		rm_state_goto(prm, RM_ST_END);
++		break;
++	case RM_EV_state_out:
++		rm_cancel_clock(prm);
++		break;
++	default:
++		break;
++	}
++	return _SUCCESS;
++}
++
++static int rm_state_end(struct rm_obj *prm, enum RM_EV_ID evid)
++{
++	switch (evid) {
++	case RM_EV_state_in:
++		_rm_post_event(prm->psta->padapter, prm->rmid, RM_EV_state_out);
++		break;
++
++	case RM_EV_cancel:
++	case RM_EV_state_out:
++	default:
++		rm_free_rmobj(prm);
++		break;
++	}
++	return _SUCCESS;
++}
++
++struct fsm_state rm_fsm[] = {
++	{"RM_ST_IDLE",		rm_state_idle},
++	{"RM_ST_DO_MEAS",	rm_state_do_meas},
++	{"RM_ST_WAIT_MEAS", 	rm_state_wait_meas},
++	{"RM_ST_SEND_REPORT", 	rm_state_send_report},
++	{"RM_ST_RECV_REPORT", 	rm_state_recv_report},
++	{"RM_ST_END", 		rm_state_end}
++};
++
++char *rm_state_name(enum RM_STATE state)
++{
++	return rm_fsm[state].name;
++}
++
++char *rm_event_name(enum RM_EV_ID evid)
++{
++	switch(evid) {
++	case RM_EV_state_in:
++		return "RM_EV_state_in";
++	case RM_EV_busy_timer_expire:
++		return "RM_EV_busy_timer_expire";
++	case RM_EV_delay_timer_expire:
++		return "RM_EV_delay_timer_expire";
++	case RM_EV_meas_timer_expire:
++		return "RM_EV_meas_timer_expire";
++	case RM_EV_repeat_delay_expire:
++		return "RM_EV_repeat_delay_expire";
++	case RM_EV_retry_timer_expire:
++		return "RM_EV_retry_timer_expire";
++	case RM_EV_request_timer_expire:
++		return "RM_EV_request_timer_expire";
++	case RM_EV_wait_report:
++		return "RM_EV_wait_report";
++	case RM_EV_start_meas:
++		return "RM_EV_start_meas";
++	case RM_EV_survey_done:
++		return "RM_EV_survey_done";
++	case RM_EV_recv_rep:
++		return "RM_EV_recv_report";
++	case RM_EV_cancel:
++		return "RM_EV_cancel";
++	case RM_EV_state_out:
++		return "RM_EV_state_out";
++	case RM_EV_max:
++		return "RM_EV_max";
++	default:
++		return "RM_EV_unknown";
++	}
++	return "UNKNOWN";
++}
++
++static void rm_state_initial(struct rm_obj *prm)
++{
++	prm->state = RM_ST_IDLE;
++
++	RTW_INFO("\n");
++	RTW_INFO("RM: rmid=%x %-18s -> %s\n",prm->rmid,
++		"new measurement", rm_fsm[prm->state].name);
++
++	rm_post_event(prm->psta->padapter, prm->rmid, RM_EV_state_in);
++}
++
++static void rm_state_run(struct rm_obj *prm, enum RM_EV_ID evid)
++{
++	RTW_INFO("RM: rmid=%x %-18s    %s\n",prm->rmid,
++		rm_fsm[prm->state].name,rm_event_name(evid));
++
++	rm_fsm[prm->state].fsm_func(prm, evid);
++}
++
++static void rm_state_goto(struct rm_obj *prm, enum RM_STATE rm_state)
++{
++	if (prm->state == rm_state)
++		return;
++
++	rm_state_run(prm, RM_EV_state_out);
++
++	RTW_INFO("\n");
++	RTW_INFO("RM: rmid=%x %-18s -> %s\n",prm->rmid,
++		rm_fsm[prm->state].name, rm_fsm[rm_state].name);
++
++	prm->state = rm_state;
++	rm_state_run(prm, RM_EV_state_in);
++}
++#endif /* CONFIG_RTW_80211K */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_rm_util.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_rm_util.c
+new file mode 100644
+index 000000000..053152f2b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_rm_util.c
+@@ -0,0 +1,434 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <drv_types.h>
++#include <hal_data.h>
++#ifdef CONFIG_RTW_80211K
++#include "rtw_rm_fsm.h"
++#include "rtw_rm_util.h"
++
++/* 802.11-2012 Table E-1 Operationg classes in United States */
++static RT_OPERATING_CLASS RTW_OP_CLASS_US[] = {
++	/* 0, OP_CLASS_NULL */	{  0,  0, {}},
++	/* 1, OP_CLASS_1 */	{115,  4, {36, 40, 44, 48}},
++	/* 2, OP_CLASS_2 */	{118,  4, {52, 56, 60, 64}},
++	/* 3, OP_CLASS_3 */	{124,  4, {149, 153, 157, 161}},
++	/* 4, OP_CLASS_4 */	{121, 11, {100, 104, 108, 112, 116, 120, 124,
++						128, 132, 136, 140}},
++	/* 5, OP_CLASS_5 */	{125,  5, {149, 153, 157, 161, 165}},
++	/* 6, OP_CLASS_12 */	{ 81, 11, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}}
++};
++
++u8 rm_get_ch_set(
++	struct rtw_ieee80211_channel *pch_set, u8 op_class, u8 ch_num)
++{
++	int i,j,sz;
++	u8 ch_amount = 0;
++
++
++	sz = sizeof(RTW_OP_CLASS_US)/sizeof(struct _RT_OPERATING_CLASS);
++
++	if (ch_num != 0) {
++		pch_set[0].hw_value = ch_num;
++		ch_amount = 1;
++		RTW_INFO("RM: meas_ch->hw_value = %u\n", pch_set->hw_value);
++		goto done;
++	}
++
++	for (i = 0; i < sz; i++) {
++
++		if (RTW_OP_CLASS_US[i].global_op_class == op_class) {
++
++			for (j = 0; j < RTW_OP_CLASS_US[i].Len; j++) {
++				pch_set[j].hw_value =
++					RTW_OP_CLASS_US[i].Channel[j];
++				RTW_INFO("RM: meas_ch[%d].hw_value = %u\n",
++					j, pch_set[j].hw_value);
++			}
++			ch_amount = RTW_OP_CLASS_US[i].Len;
++			break;
++		}
++	}
++done:
++	return ch_amount;
++}
++
++u8 rm_get_oper_class_via_ch(u8 ch)
++{
++	int i,j,sz;
++
++
++	sz = sizeof(RTW_OP_CLASS_US)/sizeof(struct _RT_OPERATING_CLASS);
++
++	for (i = 0; i < sz; i++) {
++		for (j = 0; j < RTW_OP_CLASS_US[i].Len; j++) {
++			if ( ch == RTW_OP_CLASS_US[i].Channel[j]) {
++				RTW_INFO("RM: ch %u in oper_calss %u\n",
++					ch, RTW_OP_CLASS_US[i].global_op_class);
++				return RTW_OP_CLASS_US[i].global_op_class;
++				break;
++			}
++		}
++	}
++	return 0;
++}
++
++int is_wildcard_bssid(u8 *bssid)
++{
++	int i;
++	u8 val8 = 0xff;
++
++
++	for (i=0;i<6;i++)
++		val8 &= bssid[i];
++
++	if (val8 == 0xff)
++		return _SUCCESS;
++	return _FALSE;
++}
++
++u8 translate_dbm_to_rcpi(s8 SignalPower)
++{
++	/* RCPI = Int{(Power in dBm + 110)*2} for 0dBm > Power > -110dBm
++	 *    0	: power <= -110.0 dBm
++	 *    1	: power =  -109.5 dBm
++	 *    2	: power =  -109.0 dBm
++	 */
++	return (SignalPower + 110)*2;
++}
++
++u8 translate_percentage_to_rcpi(u32 SignalStrengthIndex)
++{
++	/* Translate to dBm (x=y-100) */
++	return translate_dbm_to_rcpi(SignalStrengthIndex - 100);
++}
++
++u8 rm_get_bcn_rcpi(struct rm_obj *prm, struct wlan_network *pnetwork)
++{
++	return translate_percentage_to_rcpi(
++		pnetwork->network.PhyInfo.SignalStrength);
++}
++
++u8 rm_get_frame_rsni(struct rm_obj *prm, union recv_frame *pframe)
++{
++	int i;
++	u8 val8, snr, rx_num;
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(prm->psta->padapter);
++
++	if (IS_CCK_RATE((hw_rate_to_m_rate(pframe->u.hdr.attrib.data_rate))))
++		val8 = 255;
++	else {
++		snr = rx_num = 0;
++		for (i = 0; i < hal_spec->rf_reg_path_num; i++) {
++			if (GET_HAL_RX_PATH_BMP(prm->psta->padapter) & BIT(i)) {
++				snr += pframe->u.hdr.attrib.phy_info.rx_snr[i];
++				rx_num++;
++			}
++		}
++		snr = snr / rx_num;
++		val8 = (u8)(snr + 10)*2;
++	}
++	return val8;
++}
++
++u8 rm_get_bcn_rsni(struct rm_obj *prm, struct wlan_network *pnetwork)
++{
++	int i;
++	u8 val8, snr, rx_num;
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(prm->psta->padapter);
++
++	if (pnetwork->network.PhyInfo.is_cck_rate) {
++		/* current HW doesn't have CCK RSNI */
++		/* 255 indicates RSNI is unavailable */
++		val8 = 255;
++	} else {
++		snr = rx_num = 0;
++		for (i = 0; i < hal_spec->rf_reg_path_num; i++) {
++			if (GET_HAL_RX_PATH_BMP(prm->psta->padapter) & BIT(i)) {
++				snr += pnetwork->network.PhyInfo.rx_snr[i];
++				rx_num++;
++			}
++		}
++		snr = snr / rx_num;
++		val8 = (u8)(snr + 10)*2;
++	}
++	return val8;
++}
++
++/* output: pwr (unit dBm) */
++int rm_get_tx_power(PADAPTER adapter, enum rf_path path, enum MGN_RATE rate, s8 *pwr)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	int tx_num, band, bw, ch, n, rs;
++	u8 base;
++	s8 limt_offset = 127; /* max value of s8 */
++	s8 rate_offset;
++	s8 powr_offset;
++	int rate_pos;
++
++
++	band = hal_data->current_band_type;
++	bw = hal_data->current_channel_bw;
++	ch = hal_data->current_channel;
++
++	if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
++		return -1;
++
++	if (HAL_IsLegalChannel(adapter, ch) == _FALSE) {
++		RTW_INFO("Illegal channel!!\n");
++		return -2;
++	}
++
++	*pwr = phy_get_tx_power_final_absolute_value(adapter, path, rate, bw, ch);
++
++	return 0;
++}
++
++int rm_get_rx_sensitivity(PADAPTER adapter, enum channel_width bw, enum MGN_RATE rate, s8 *pwr)
++{
++	s8 rx_sensitivity = -110;
++
++	switch(rate) {
++	case MGN_1M:
++		rx_sensitivity= -101;
++		break;
++	case MGN_2M:
++		rx_sensitivity= -98;
++		break;
++	case MGN_5_5M:
++		rx_sensitivity= -92;
++		break;
++	case MGN_11M:
++		rx_sensitivity= -89;
++		break;
++	case MGN_6M:
++	case MGN_9M:
++	case MGN_12M:
++		rx_sensitivity = -92;
++		break;
++	case MGN_18M:
++		rx_sensitivity = -90;
++		break;
++	case MGN_24M:
++		rx_sensitivity = -88;
++		break;
++	case MGN_36M:
++		rx_sensitivity = -84;
++		break;
++	case MGN_48M:
++		rx_sensitivity = -79;
++		break;
++	case MGN_54M:
++		rx_sensitivity = -78;
++		break;
++
++	case MGN_MCS0:
++	case MGN_MCS8:
++	case MGN_MCS16:
++	case MGN_MCS24:
++	case MGN_VHT1SS_MCS0:
++	case MGN_VHT2SS_MCS0:
++	case MGN_VHT3SS_MCS0:
++	case MGN_VHT4SS_MCS0:
++		/* BW20 BPSK 1/2 */
++		rx_sensitivity = -82;
++		break;
++
++	case MGN_MCS1:
++	case MGN_MCS9:
++	case MGN_MCS17:
++	case MGN_MCS25:
++	case MGN_VHT1SS_MCS1:
++	case MGN_VHT2SS_MCS1:
++	case MGN_VHT3SS_MCS1:
++	case MGN_VHT4SS_MCS1:
++		/* BW20 QPSK 1/2 */
++		rx_sensitivity = -79;
++		break;
++
++	case MGN_MCS2:
++	case MGN_MCS10:
++	case MGN_MCS18:
++	case MGN_MCS26:
++	case MGN_VHT1SS_MCS2:
++	case MGN_VHT2SS_MCS2:
++	case MGN_VHT3SS_MCS2:
++	case MGN_VHT4SS_MCS2:
++		/* BW20 QPSK 3/4 */
++		rx_sensitivity = -77;
++		break;
++
++	case MGN_MCS3:
++	case MGN_MCS11:
++	case MGN_MCS19:
++	case MGN_MCS27:
++	case MGN_VHT1SS_MCS3:
++	case MGN_VHT2SS_MCS3:
++	case MGN_VHT3SS_MCS3:
++	case MGN_VHT4SS_MCS3:
++		/* BW20 16-QAM 1/2 */
++		rx_sensitivity = -74;
++		break;
++
++	case MGN_MCS4:
++	case MGN_MCS12:
++	case MGN_MCS20:
++	case MGN_MCS28:
++	case MGN_VHT1SS_MCS4:
++	case MGN_VHT2SS_MCS4:
++	case MGN_VHT3SS_MCS4:
++	case MGN_VHT4SS_MCS4:
++		/* BW20 16-QAM 3/4 */
++		rx_sensitivity = -70;
++		break;
++
++	case MGN_MCS5:
++	case MGN_MCS13:
++	case MGN_MCS21:
++	case MGN_MCS29:
++	case MGN_VHT1SS_MCS5:
++	case MGN_VHT2SS_MCS5:
++	case MGN_VHT3SS_MCS5:
++	case MGN_VHT4SS_MCS5:
++		/* BW20 64-QAM 2/3 */
++		rx_sensitivity = -66;
++		break;
++
++	case MGN_MCS6:
++	case MGN_MCS14:
++	case MGN_MCS22:
++	case MGN_MCS30:
++	case MGN_VHT1SS_MCS6:
++	case MGN_VHT2SS_MCS6:
++	case MGN_VHT3SS_MCS6:
++	case MGN_VHT4SS_MCS6:
++		/* BW20 64-QAM 3/4 */
++		rx_sensitivity = -65;
++		break;
++
++	case MGN_MCS7:
++	case MGN_MCS15:
++	case MGN_MCS23:
++	case MGN_MCS31:
++	case MGN_VHT1SS_MCS7:
++	case MGN_VHT2SS_MCS7:
++	case MGN_VHT3SS_MCS7:
++	case MGN_VHT4SS_MCS7:
++		/* BW20 64-QAM 5/6 */
++		rx_sensitivity = -64;
++		break;
++
++	case MGN_VHT1SS_MCS8:
++	case MGN_VHT2SS_MCS8:
++	case MGN_VHT3SS_MCS8:
++	case MGN_VHT4SS_MCS8:
++		/* BW20 256-QAM 3/4 */
++		rx_sensitivity = -59;
++		break;
++
++	case MGN_VHT1SS_MCS9:
++	case MGN_VHT2SS_MCS9:
++	case MGN_VHT3SS_MCS9:
++	case MGN_VHT4SS_MCS9:
++		/* BW20 256-QAM 5/6 */
++		rx_sensitivity = -57;
++		break;
++
++	default:
++		return -1;
++		break;
++
++	}
++
++	switch(bw) {
++	case CHANNEL_WIDTH_20:
++		break;
++	case CHANNEL_WIDTH_40:
++		rx_sensitivity -= 3;
++		break;
++	case CHANNEL_WIDTH_80:
++		rx_sensitivity -= 6;
++		break;
++	case CHANNEL_WIDTH_160:
++		rx_sensitivity -= 9;
++		break;
++	case CHANNEL_WIDTH_5:
++	case CHANNEL_WIDTH_10:
++	case CHANNEL_WIDTH_80_80:
++	default:
++		return -1;
++		break;
++	}
++	*pwr = rx_sensitivity;
++
++	return 0;
++}
++
++/* output: path_a max tx power in dBm */
++int rm_get_path_a_max_tx_power(_adapter *adapter, s8 *path_a)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	int path, tx_num, band, bw, ch, n, rs;
++	u8 rate_num;
++	s8 max_pwr[RF_PATH_MAX], pwr;
++
++
++	band = hal_data->current_band_type;
++	bw = hal_data->current_channel_bw;
++	ch = hal_data->current_channel;
++
++	for (path = 0; path < RF_PATH_MAX; path++) {
++		if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
++			break;
++
++		max_pwr[path] = -127; /* min value of s8 */
++#if (RM_MORE_DBG_MSG)
++		RTW_INFO("RM: [%s][%c]\n", band_str(band), rf_path_char(path));
++#endif
++		for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
++			tx_num = rate_section_to_tx_num(rs);
++
++			if (tx_num >= hal_spec->tx_nss_num)
++				continue;
++
++			if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
++				continue;
++
++			if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
++				continue;
++
++			rate_num = rate_section_rate_num(rs);
++
++			/* get power by rate in db */
++			for (n = rate_num - 1; n >= 0; n--) {
++				pwr = phy_get_tx_power_final_absolute_value(adapter, path, rates_by_sections[rs].rates[n], bw, ch);
++				max_pwr[path] = MAX(max_pwr[path], pwr);
++#if (RM_MORE_DBG_MSG)
++				RTW_INFO("RM: %9s = %2d\n",
++					MGN_RATE_STR(rates_by_sections[rs].rates[n]), pwr);
++#endif
++			}
++		}
++	}
++#if (RM_MORE_DBG_MSG)
++	RTW_INFO("RM: path_a max_pwr=%ddBm\n", max_pwr[0]);
++#endif
++	*path_a = max_pwr[0];
++	return 0;
++}
++
++#endif /* CONFIG_RTW_80211K */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_rson.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_rson.c
+new file mode 100644
+index 000000000..8a0e0b095
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_rson.c
+@@ -0,0 +1,588 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#define _RTW_RSON_C_
++
++#include <drv_types.h>
++
++#ifdef CONFIG_RTW_REPEATER_SON
++
++/********	Custommize Part	***********************/
++
++unsigned char	RTW_RSON_OUI[] = {0xFA, 0xFA, 0xFA};
++#define RSON_SCORE_DIFF_TH				8
++
++/*
++	Calculate the corresponding score.
++*/
++inline u8 rtw_cal_rson_score(struct rtw_rson_struct *cand_rson_data, NDIS_802_11_RSSI  Rssi)
++{
++	if ((cand_rson_data->hopcnt == RTW_RSON_HC_NOTREADY)
++		|| (cand_rson_data->connectible == RTW_RSON_DENYCONNECT))
++		return RTW_RSON_SCORE_NOTCNNT;
++
++	return RTW_RSON_SCORE_MAX - (cand_rson_data->hopcnt * 10) + (Rssi/10);
++}
++
++/*************************************************/
++
++
++static u8 rtw_rson_block_bssid_idx = 0;
++u8 rtw_rson_block_bssid[10][6] = {
++			/*{0x02, 0xE0, 0x4C, 0x07, 0xC3, 0xF6}*/
++};
++
++/* fake root, regard a real AP as a SO root */
++static u8 rtw_rson_root_bssid_idx = 0;
++u8 rtw_rson_root_bssid[10][6] = {
++			/*{0x1c, 0x5f, 0x2b, 0x5a, 0x60, 0x24}*/
++};
++
++int is_match_bssid(u8 *mac, u8 bssid_array[][6], int num)
++{
++	int i;
++
++	for (i = 0; i < num; i++)
++		if (_rtw_memcmp(mac, bssid_array[i], 6) == _TRUE)
++			return _TRUE;
++	return _FALSE;
++}
++
++void init_rtw_rson_data(struct dvobj_priv *dvobj)
++{
++	/*Aries  todo.  if pdvobj->rson_data.ver == 1 */
++	dvobj->rson_data.ver = RTW_RSON_VER;
++	dvobj->rson_data.id = CONFIG_RTW_REPEATER_SON_ID;
++#ifdef CONFIG_RTW_REPEATER_SON_ROOT
++	dvobj->rson_data.hopcnt = RTW_RSON_HC_ROOT;
++	dvobj->rson_data.connectible = RTW_RSON_ALLOWCONNECT;
++#else
++	dvobj->rson_data.hopcnt = RTW_RSON_HC_NOTREADY;
++	dvobj->rson_data.connectible = RTW_RSON_DENYCONNECT;
++#endif
++	dvobj->rson_data.loading = 0;
++	_rtw_memset(dvobj->rson_data.res, 0xAA, sizeof(dvobj->rson_data.res));
++}
++
++void	rtw_rson_get_property_str(_adapter *padapter, char *rson_data_str)
++{
++	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
++
++	sprintf(rson_data_str, "version : \t%d\nid : \t\t%08x\nhop count : \t%d\nconnectible : \t%s\nloading : \t%d\nreserve : \t%16ph\n",
++		pdvobj->rson_data.ver,
++		pdvobj->rson_data.id,
++		pdvobj->rson_data.hopcnt,
++		pdvobj->rson_data.connectible ? "connectable":"unconnectable",
++		pdvobj->rson_data.loading,
++		pdvobj->rson_data.res);
++}
++
++int str2hexbuf(char *str, u8 *hexbuf, int len)
++{
++	u8 *p;
++	int i, slen, idx = 0;
++
++	p = (unsigned char *)str;
++	if ((*p != '0') || (*(p+1) != 'x'))
++		return _FALSE;
++	slen = strlen(str);
++	if (slen > (len*2) + 2)
++		return _FALSE;
++	p += 2;
++	for (i = 0 ; i < len; i++, idx = idx+2) {
++		hexbuf[i] = key_2char2num(p[idx], p[idx + 1]);
++		if (slen <= idx+2)
++			break;
++	}
++	return _TRUE;
++}
++
++int rtw_rson_set_property(_adapter *padapter, char *field, char *value)
++{
++	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
++	int num = 0;
++
++	if (_rtw_memcmp(field, (u8 *)"ver", 3) == _TRUE)
++		pdvobj->rson_data.ver = rtw_atoi(value);
++	else if (_rtw_memcmp(field, (u8 *)"id", 2) == _TRUE)
++		num = sscanf(value, "%08x",   &(pdvobj->rson_data.id));
++	else if (_rtw_memcmp(field, (u8 *)"hc", 2) == _TRUE)
++		num = sscanf(value, "%hhu", &(pdvobj->rson_data.hopcnt));
++	else if (_rtw_memcmp(field, (u8 *)"cnt", 3) == _TRUE)
++		num = sscanf(value, "%hhu", &(pdvobj->rson_data.connectible));
++	else if (_rtw_memcmp(field, (u8 *)"loading", 2) == _TRUE)
++		num = sscanf(value, "%hhu", &(pdvobj->rson_data.loading));
++	else if (_rtw_memcmp(field, (u8 *)"res", 2) == _TRUE) {
++		str2hexbuf(value, pdvobj->rson_data.res, 16);
++		return 1;
++	} else
++		return _FALSE;
++	return num;
++}
++
++/*
++	return :	TRUE  -- competitor is taking advantage than condidate
++			FALSE -- we should continue keeping candidate
++*/
++int rtw_rson_choose(struct wlan_network **candidate, struct wlan_network *competitor)
++{
++	s16 comp_score = 0, cand_score = 0;
++	struct rtw_rson_struct rson_cand, rson_comp;
++
++	if (is_match_bssid(competitor->network.MacAddress, rtw_rson_block_bssid, rtw_rson_block_bssid_idx) == _TRUE)
++		return _FALSE;
++
++	if ((competitor == NULL)
++		|| (rtw_get_rson_struct(&(competitor->network), &rson_comp) != _TRUE)
++		|| (rson_comp.id != CONFIG_RTW_REPEATER_SON_ID))
++		return _FALSE;
++
++	comp_score = rtw_cal_rson_score(&rson_comp, competitor->network.Rssi);
++	if (comp_score == RTW_RSON_SCORE_NOTCNNT)
++		return _FALSE;
++
++	if (*candidate == NULL)
++		return _TRUE;
++	if (rtw_get_rson_struct(&((*candidate)->network), &rson_cand) != _TRUE)
++		return _FALSE;
++
++	cand_score = rtw_cal_rson_score(&rson_cand, (*candidate)->network.Rssi);
++	RTW_INFO("%s: competitor_score=%d,  candidate_score=%d\n", __func__, comp_score, cand_score);
++	if (comp_score - cand_score > RSON_SCORE_DIFF_TH)
++		return _TRUE;
++
++	return _FALSE;
++}
++
++inline u8 rtw_rson_varify_ie(u8 *p)
++{
++	u8 *ptr = NULL;
++	u8 ver;
++	u32 id;
++	u8 hopcnt;
++	u8 allcnnt;
++
++	ptr = p + 2 + sizeof(RTW_RSON_OUI);
++	ver = *ptr;
++
++	/*	for (ver == 1)	*/
++	if (ver != 1)
++		return _FALSE;
++
++	return _TRUE;
++}
++
++/*
++	Parsing RTK self-organization vendor IE
++*/
++int rtw_get_rson_struct(WLAN_BSSID_EX *bssid, struct  rtw_rson_struct *rson_data)
++{
++	sint  limit = 0;
++	u32	len;
++	u8	*p;
++
++	if ((rson_data == NULL) || (bssid == NULL))
++		return -EINVAL;
++
++	/*	Default		*/
++	rson_data->id = 0;
++	rson_data->ver = 0;
++	rson_data->hopcnt = 0;
++	rson_data->connectible = 0;
++	rson_data->loading = 0;
++	/*	fake root		*/
++	if (is_match_bssid(bssid->MacAddress, rtw_rson_root_bssid, rtw_rson_root_bssid_idx) == _TRUE) {
++		rson_data->id = CONFIG_RTW_REPEATER_SON_ID;
++		rson_data->ver = RTW_RSON_VER;
++		rson_data->hopcnt = RTW_RSON_HC_ROOT;
++		rson_data->connectible = RTW_RSON_ALLOWCONNECT;
++		rson_data->loading = 0;
++		return _TRUE;
++	}
++	limit = bssid->IELength - _BEACON_IE_OFFSET_;
++
++	for (p = bssid->IEs + _BEACON_IE_OFFSET_; ; p += (len + 2)) {
++		p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &len, limit);
++		limit -= len;
++		if ((p == NULL) || (len == 0))
++			break;
++		if (p && (_rtw_memcmp(p + 2, RTW_RSON_OUI, sizeof(RTW_RSON_OUI)) == _TRUE)
++			&& rtw_rson_varify_ie(p)) {
++			p = p + 2 + sizeof(RTW_RSON_OUI);
++			rson_data->ver = *p;
++			/*	for (ver == 1)		*/
++			p = p + 1;
++			rson_data->id = le32_to_cpup((__le32 *)p);
++			p = p + 4;
++			rson_data->hopcnt = *p;
++			p = p + 1;
++			rson_data->connectible = *p;
++			p = p + 1;
++			rson_data->loading = *p;
++
++			return _TRUE;
++		}
++	}
++	return -EBADMSG;
++}
++
++u32 rtw_rson_append_ie(_adapter *padapter, unsigned char *pframe, u32 *len)
++{
++	u8 *ptr, *ori, ie_len = 0;
++	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++/*	static int iii = 0;*/
++
++	if ((!pdvobj) || (!pframe))
++		return 0;
++	ptr = ori = pframe;
++	*ptr++ = _VENDOR_SPECIFIC_IE_;
++	*ptr++ = ie_len = sizeof(RTW_RSON_OUI)+sizeof(pdvobj->rson_data);
++	_rtw_memcpy(ptr, RTW_RSON_OUI, sizeof(RTW_RSON_OUI));
++	ptr = ptr + sizeof(RTW_RSON_OUI);
++	*ptr++ = pdvobj->rson_data.ver;
++	*(s32 *)ptr = cpu_to_le32(pdvobj->rson_data.id);
++	ptr = ptr + sizeof(pdvobj->rson_data.id);
++	*ptr++ = pdvobj->rson_data.hopcnt;
++	*ptr++ = pdvobj->rson_data.connectible;
++	*ptr++ = pdvobj->rson_data.loading;
++	_rtw_memcpy(ptr, pdvobj->rson_data.res, sizeof(pdvobj->rson_data.res));
++	pframe = ptr;
++/*
++	iii = iii % 20;
++	if (iii++ == 0)
++		RTW_INFO("%s : RTW RSON IE : %20ph\n", __func__, ori);
++*/
++	*len += (ie_len+2);
++	return ie_len;
++
++}
++
++void rtw_rson_do_disconnect(_adapter *padapter)
++{
++	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
++
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++#ifndef CONFIG_RTW_REPEATER_SON_ROOT
++	pdvobj->rson_data.ver = RTW_RSON_VER;
++	pdvobj->rson_data.id = CONFIG_RTW_REPEATER_SON_ID;
++	pdvobj->rson_data.hopcnt = RTW_RSON_HC_NOTREADY;
++	pdvobj->rson_data.connectible = RTW_RSON_DENYCONNECT;
++	pdvobj->rson_data.loading = 0;
++	rtw_mi_tx_beacon_hdl(padapter);
++#endif
++}
++
++void rtw_rson_join_done(_adapter *padapter)
++{
++	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
++	WLAN_BSSID_EX	*cur_network = NULL;
++	struct rtw_rson_struct  rson_data;
++
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++	if (!padapter->mlmepriv.cur_network_scanned)
++		return;
++	cur_network = &(padapter->mlmepriv.cur_network_scanned->network);
++	if (rtw_get_rson_struct(cur_network, &rson_data) != _TRUE) {
++		RTW_ERR("%s: try to join a improper network(%s)\n", __func__, cur_network->Ssid.Ssid);
++		return;
++	}
++
++#ifndef CONFIG_RTW_REPEATER_SON_ROOT
++	/* update rson_data */
++	pdvobj->rson_data.ver = RTW_RSON_VER;
++	pdvobj->rson_data.id = rson_data.id;
++	pdvobj->rson_data.hopcnt = rson_data.hopcnt + 1;
++	pdvobj->rson_data.connectible = RTW_RSON_ALLOWCONNECT;
++	pdvobj->rson_data.loading = 0;
++	rtw_mi_tx_beacon_hdl(padapter);
++#endif
++}
++
++int rtw_rson_isupdate_roamcan(struct mlme_priv *mlme
++	, struct wlan_network **candidate, struct wlan_network *competitor)
++{
++	struct rtw_rson_struct  rson_cand, rson_comp, rson_curr;
++	s16 comp_score, cand_score, curr_score;
++
++	if ((competitor == NULL)
++		|| (rtw_get_rson_struct(&(competitor->network), &rson_comp) != _TRUE)
++		|| (rson_comp.id != CONFIG_RTW_REPEATER_SON_ID))
++		return _FALSE;
++
++	if (is_match_bssid(competitor->network.MacAddress, rtw_rson_block_bssid, rtw_rson_block_bssid_idx) == _TRUE)
++		return _FALSE;
++
++	if ((!mlme->cur_network_scanned)
++		|| (mlme->cur_network_scanned == competitor)
++		|| (rtw_get_rson_struct(&(mlme->cur_network_scanned->network), &rson_curr)) != _TRUE)
++		return _FALSE;
++
++	if (rtw_get_passing_time_ms((u32)competitor->last_scanned) >= mlme->roam_scanr_exp_ms)
++		return _FALSE;
++
++	comp_score = rtw_cal_rson_score(&rson_comp, competitor->network.Rssi);
++	curr_score = rtw_cal_rson_score(&rson_curr, mlme->cur_network_scanned->network.Rssi);
++	if (comp_score - curr_score < RSON_SCORE_DIFF_TH)
++		return _FALSE;
++
++	if (*candidate == NULL)
++		return _TRUE;
++
++	if (rtw_get_rson_struct(&((*candidate)->network), &rson_cand) != _TRUE) {
++		RTW_ERR("%s : Unable to get rson_struct from candidate(%s -- " MAC_FMT")\n",
++				__func__, (*candidate)->network.Ssid.Ssid, MAC_ARG((*candidate)->network.MacAddress));
++		return _FALSE;
++	}
++	cand_score = rtw_cal_rson_score(&rson_cand, (*candidate)->network.Rssi);
++	RTW_DBG("comp_score=%d , cand_score=%d , curr_score=%d\n", comp_score, cand_score, curr_score);
++	if (cand_score < comp_score)
++		return _TRUE;
++
++#if 0		/*	Handle 11R protocol	*/
++#ifdef CONFIG_RTW_80211R
++	if (rtw_chk_ft_flags(adapter, RTW_FT_SUPPORTED)) {
++		ptmp = rtw_get_ie(&competitor->network.IEs[12], _MDIE_, &mdie_len, competitor->network.IELength-12);
++		if (ptmp) {
++			if (!_rtw_memcmp(&pftpriv->mdid, ptmp+2, 2))
++				goto exit;
++
++			/*The candidate don't support over-the-DS*/
++			if (rtw_chk_ft_flags(adapter, RTW_FT_STA_OVER_DS_SUPPORTED)) {
++				if ((rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && !(*(ptmp+4) & 0x01)) ||
++					(!rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && (*(ptmp+4) & 0x01))) {
++					RTW_INFO("FT: ignore the candidate(" MAC_FMT ") for over-the-DS\n", MAC_ARG(competitor->network.MacAddress));
++					rtw_clr_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED);
++					goto exit;
++				}
++			}
++		} else
++			goto exit;
++	}
++#endif
++#endif
++	return _FALSE;
++}
++
++void rtw_rson_show_survey_info(struct seq_file *m, _list *plist, _list *phead)
++{
++	struct wlan_network	*pnetwork = NULL;
++	struct rtw_rson_struct  rson_data;
++	s16 rson_score;
++	u16  index = 0;
++
++	RTW_PRINT_SEL(m, "%5s  %-17s  %3s  %5s %14s  %10s  %-3s  %5s %32s\n", "index", "bssid", "ch", "id", "hop_cnt", "loading", "RSSI", "score", "ssid");
++	while (1) {
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++		if (!pnetwork)
++			break;
++
++		_rtw_memset(&rson_data, 0, sizeof(rson_data));
++		rson_score = 0;
++		if (rtw_get_rson_struct(&(pnetwork->network), &rson_data) == _TRUE)
++			rson_score = rtw_cal_rson_score(&rson_data, pnetwork->network.Rssi);
++		RTW_PRINT_SEL(m, "%5d  "MAC_FMT" %3d  0x%08x %6d %10d   %6d %6d   %32s\n",
++			      ++index,
++			      MAC_ARG(pnetwork->network.MacAddress),
++			      pnetwork->network.Configuration.DSConfig,
++			      rson_data.id,
++			      rson_data.hopcnt,
++			      rson_data.loading,
++			      (int)pnetwork->network.Rssi,
++			      rson_score,
++			      pnetwork->network.Ssid.Ssid);
++		plist = get_next(plist);
++		}
++
++}
++
++/*
++	Description :	As a AP role, We need to check the qualify of associating STA.
++					We also need to check if we are ready to be associated.
++
++	return :	TRUE  -- AP REJECT this STA
++				FALSE -- AP ACCEPT this STA
++*/
++u8 rtw_rson_ap_check_sta(_adapter *padapter, u8 *pframe, uint pkt_len, unsigned short ie_offset)
++{
++	struct wlan_network	*pnetwork = NULL;
++	struct rtw_rson_struct  rson_target;
++	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
++	int len = 0;
++	u8 ret = _FALSE;
++	u8 *p;
++
++#ifndef CONFIG_RTW_REPEATER_SON_ROOT
++	_rtw_memset(&rson_target, 0, sizeof(rson_target));
++	for (p = pframe + WLAN_HDR_A3_LEN + ie_offset; ; p += (len + 2)) {
++		p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &len, pkt_len - WLAN_HDR_A3_LEN - ie_offset);
++
++		if ((p == NULL) || (len == 0))
++			break;
++
++		if (p && (_rtw_memcmp(p + 2, RTW_RSON_OUI, sizeof(RTW_RSON_OUI)) == _TRUE)
++			&& rtw_rson_varify_ie(p)) {
++			p = p + 2 + sizeof(RTW_RSON_OUI);
++			rson_target.ver = *p;
++			/*	for (ver == 1)		*/
++			p = p + 1;
++			rson_target.id = le32_to_cpup((__le32 *)p);
++			p = p + 4;
++			rson_target.hopcnt = *p;
++			p = p + 1;
++			rson_target.connectible = *p;
++			p = p + 1;
++			rson_target.loading = *p;
++			break;
++		}
++	}
++
++	if (rson_target.id == 0)		/*	Normal STA, not a RSON STA	*/
++		ret = _FALSE;
++	else if (rson_target.id != pdvobj->rson_data.id) {
++		ret = _TRUE;
++		RTW_INFO("%s : Reject AssoReq because RSON ID not match, STA=%08x, our=%08x\n",
++				__func__, rson_target.id, pdvobj->rson_data.id);
++	} else if ((pdvobj->rson_data.hopcnt == RTW_RSON_HC_NOTREADY)
++		|| (pdvobj->rson_data.connectible == RTW_RSON_DENYCONNECT)) {
++		ret = _TRUE;
++		RTW_INFO("%s : Reject AssoReq becuase our hopcnt=%d or connectbile=%d\n",
++				__func__, pdvobj->rson_data.hopcnt, pdvobj->rson_data.connectible);
++	}
++#endif
++	return ret;
++}
++
++u8 rtw_rson_scan_wk_cmd(_adapter *padapter, int op)
++{
++	struct cmd_obj *ph2c;
++	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++	u8 *extra_cmd_buf;
++	u8 res = _SUCCESS;
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++	pdrvextra_cmd_parm->ec_id = RSON_SCAN_WK_CID;
++	pdrvextra_cmd_parm->type = op;
++	pdrvextra_cmd_parm->size = 0;
++	pdrvextra_cmd_parm->pbuf = NULL;
++
++	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++
++	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++	return res;
++
++}
++
++void rtw_rson_scan_cmd_hdl(_adapter *padapter, int op)
++{
++	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	u8 val8;
++
++	if (mlmeext_chk_scan_state(pmlmeext, SCAN_DISABLE) != _TRUE)
++		return;
++	if (op == RSON_SCAN_PROCESS) {
++		padapter->rtw_rson_scanstage = RSON_SCAN_PROCESS;
++		val8 = 0x1e;
++		rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &val8, _FALSE);
++		val8 = 1;
++		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++		issue_probereq(padapter, NULL, NULL);
++		/*	stop rson_scan after 100ms	*/
++		_set_timer(&(pmlmeext->rson_scan_timer), 100);
++	} else if  (op == RSON_SCAN_DISABLE) {
++		padapter->rtw_rson_scanstage = RSON_SCAN_DISABLE;
++		val8 = 0;
++		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
++		val8 = 0xff;
++		rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &val8, _FALSE);
++		/*	report_surveydone_event(padapter);*/
++		if (pmlmepriv->to_join == _TRUE) {
++			if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) != _TRUE) {
++				int s_ret;
++
++				set_fwstate(pmlmepriv, WIFI_UNDER_LINKING);
++				pmlmepriv->to_join = _FALSE;
++				s_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv);
++				if (s_ret == _SUCCESS)
++					_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
++				else if (s_ret == 2) {
++					_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
++					rtw_indicate_connect(padapter);
++				} else {
++					RTW_INFO("try_to_join, but select scanning queue fail, to_roam:%d\n", rtw_to_roam(padapter));
++					if (rtw_to_roam(padapter) != 0) {
++						if (rtw_dec_to_roam(padapter) == 0) {
++							rtw_set_to_roam(padapter, 0);
++							rtw_free_assoc_resources(padapter, _TRUE);
++							rtw_indicate_disconnect(padapter, 0, _FALSE);
++						} else
++							pmlmepriv->to_join = _TRUE;
++					} else
++						rtw_indicate_disconnect(padapter, 0, _FALSE);
++					_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
++				}
++			}
++		} else {
++			if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) {
++				if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
++				    && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
++					if (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) {
++#ifdef CONFIG_RTW_80211R
++						if (rtw_chk_ft_flags(padapter, RTW_FT_OVER_DS_SUPPORTED)) {
++							start_clnt_ft_action(adapter, (u8 *)pmlmepriv->roam_network->network.MacAddress);
++						} else {
++							/*wait a little time to retrieve packets buffered in the current ap while scan*/
++							_set_timer(&pmlmeext->ft_roam_timer, 30);
++						}
++#else
++						receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress
++							, WLAN_REASON_ACTIVE_ROAM, _FALSE);
++#endif
++					}
++				}
++			}
++			issue_action_BSSCoexistPacket(padapter);
++			issue_action_BSSCoexistPacket(padapter);
++			issue_action_BSSCoexistPacket(padapter);
++		}
++	} else {
++		RTW_ERR("%s : improper parameter -- op = %d\n", __func__, op);
++	}
++}
++
++#endif	/* CONFIG_RTW_REPEATER_SON */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_sdio.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_sdio.c
+new file mode 100644
+index 000000000..cdadbaff7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_sdio.c
+@@ -0,0 +1,157 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2015 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_SDIO_C_
++
++#include <drv_types.h>		/* struct dvobj_priv and etc. */
++#include <drv_types_sdio.h>	/* RTW_SDIO_ADDR_CMD52_GEN */
++
++/*
++ * Description:
++ *	Use SDIO cmd52 or cmd53 to read/write data
++ *
++ * Parameters:
++ *	d	pointer of device object(struct dvobj_priv)
++ *	addr	SDIO address, 17 bits
++ *	buf	buffer for I/O
++ *	len	length
++ *	write	0:read, 1:write
++ *	cmd52	0:cmd52, 1:cmd53
++ *
++ * Return:
++ *	_SUCCESS	I/O ok.
++ *	_FAIL		I/O fail.
++ */
++static u8 sdio_io(struct dvobj_priv *d, u32 addr, void *buf, size_t len, u8 write, u8 cmd52)
++{
++#ifdef DBG_SDIO
++#if (DBG_SDIO >= 3)
++	struct sdio_data *sdio;
++#endif /* DBG_SDIO >= 3 */
++#endif /* DBG_SDIO */
++	u32 addr_drv;	/* address with driver defined bit */
++	int err;
++	u8 retry = 0;
++	u8 stop_retry = _FALSE;	/* flag for stopping retry or not */
++
++
++#ifdef DBG_SDIO
++#if (DBG_SDIO >= 3)
++	sdio = &d->intf_data;
++#endif /* DBG_SDIO >= 3 */
++#endif /* DBG_SDIO */
++
++	if (rtw_is_surprise_removed(dvobj_get_primary_adapter(d))) {
++		RTW_ERR("%s: bSurpriseRemoved, skip %s 0x%05x, %zu bytes\n",
++			__FUNCTION__, write?"write":"read", addr, len);
++		return _FAIL;
++	}
++
++	addr_drv = addr;
++	if (cmd52)
++		addr_drv = RTW_SDIO_ADDR_CMD52_GEN(addr_drv);
++
++	do {
++		if (write)
++			err = d->intf_ops->write(d, addr_drv, buf, len, 0);
++		else
++			err = d->intf_ops->read(d, addr_drv, buf, len, 0);
++		if (!err) {
++			if (retry) {
++				RTW_INFO("%s: Retry %s OK! addr=0x%05x %zu bytes, retry=%u,%u\n",
++					 __FUNCTION__, write?"write":"read",
++					 addr, len, retry, ATOMIC_READ(&d->continual_io_error));
++				RTW_INFO_DUMP("Data: ", buf, len);
++			}
++			rtw_reset_continual_io_error(d);
++			break;
++		}
++		RTW_ERR("%s: %s FAIL! error(%d) addr=0x%05x %zu bytes, retry=%u,%u\n",
++			__FUNCTION__, write?"write":"read", err, addr, len,
++			retry, ATOMIC_READ(&d->continual_io_error));
++
++#ifdef DBG_SDIO
++#if (DBG_SDIO >= 3)
++		if (sdio->dbg_enable) {
++			if (sdio->err_test && sdio->err_test_triggered)
++				sdio->err_test = 0;
++
++			if (sdio->err_stop) {
++				RTW_ERR("%s: I/O error! Set surprise remove flag ON!\n",
++					__FUNCTION__);
++				rtw_set_surprise_removed(dvobj_get_primary_adapter(d));
++				return _FAIL;
++			}
++		}
++#endif /* DBG_SDIO >= 3 */
++#endif /* DBG_SDIO */
++
++		retry++;
++		stop_retry = rtw_inc_and_chk_continual_io_error(d);
++		if ((err == -1) || (stop_retry == _TRUE) || (retry > SD_IO_TRY_CNT)) {
++			/* critical error, unrecoverable */
++			RTW_ERR("%s: Fatal error! Set surprise remove flag ON! (retry=%u,%u)\n",
++				__FUNCTION__, retry, ATOMIC_READ(&d->continual_io_error));
++			rtw_set_surprise_removed(dvobj_get_primary_adapter(d));
++			return _FAIL;
++		}
++
++		/* WLAN IOREG or SDIO Local */
++		if ((addr & 0x10000) || !(addr & 0xE000)) {
++			RTW_WARN("%s: Retry %s addr=0x%05x %zu bytes, retry=%u,%u\n",
++				 __FUNCTION__, write?"write":"read", addr, len,
++				 retry, ATOMIC_READ(&d->continual_io_error));
++			continue;
++		}
++		return _FAIL;
++	} while (1);
++
++	return _SUCCESS;
++}
++
++u8 rtw_sdio_read_cmd52(struct dvobj_priv *d, u32 addr, void *buf, size_t len)
++{
++	return sdio_io(d, addr, buf, len, 0, 1);
++}
++
++u8 rtw_sdio_read_cmd53(struct dvobj_priv *d, u32 addr, void *buf, size_t len)
++{
++	return sdio_io(d, addr, buf, len, 0, 0);
++}
++
++u8 rtw_sdio_write_cmd52(struct dvobj_priv *d, u32 addr, void *buf, size_t len)
++{
++	return sdio_io(d, addr, buf, len, 1, 1);
++}
++
++u8 rtw_sdio_write_cmd53(struct dvobj_priv *d, u32 addr, void *buf, size_t len)
++{
++	return sdio_io(d, addr, buf, len, 1, 0);
++}
++
++u8 rtw_sdio_f0_read(struct dvobj_priv *d, u32 addr, void *buf, size_t len)
++{
++	int err;
++	u8 ret;
++
++
++	ret = _SUCCESS;
++	addr = RTW_SDIO_ADDR_F0_GEN(addr);
++
++	err = d->intf_ops->read(d, addr, buf, len, 0);
++	if (err)
++		ret = _FAIL;
++
++	return ret;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_security.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_security.c
+new file mode 100644
+index 000000000..c54161f92
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_security.c
+@@ -0,0 +1,2872 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define  _RTW_SECURITY_C_
++
++#include <drv_types.h>
++#include <rtw_swcrypto.h>
++
++static const char *_security_type_str[] = {
++	"N/A",
++	"WEP40",
++	"TKIP",
++	"TKIP_WM",
++	"AES",
++	"WEP104",
++	"SMS4",
++	"GCMP",
++};
++
++static const char *_security_type_bip_str[] = {
++	"BIP_CMAC_128",
++	"BIP_GMAC_128",
++	"BIP_GMAC_256",
++	"BIP_CMAC_256",
++};
++
++const char *security_type_str(u8 value)
++{
++#ifdef CONFIG_IEEE80211W
++	if ((_BIP_MAX_ > value) && (value >= _BIP_CMAC_128_))
++		return _security_type_bip_str[value & ~_SEC_TYPE_BIT_];
++#endif
++
++	if (_CCMP_256_ == value)
++		return "CCMP_256";
++	if (_GCMP_256_ == value)
++		return "GCMP_256";
++
++	if (_SEC_TYPE_MAX_ > value)
++		return _security_type_str[value];
++
++	return NULL;
++}
++
++#ifdef CONFIG_IEEE80211W
++u32 security_type_bip_to_gmcs(enum security_type type)
++{
++	switch (type) {
++	case _BIP_CMAC_128_:
++		return WPA_CIPHER_BIP_CMAC_128;
++	case _BIP_GMAC_128_:
++		return WPA_CIPHER_BIP_GMAC_128;
++	case _BIP_GMAC_256_:
++		return WPA_CIPHER_BIP_GMAC_256;
++	case _BIP_CMAC_256_:
++		return WPA_CIPHER_BIP_CMAC_256;
++	default:
++		return 0;
++	}
++}
++#endif
++
++#ifdef DBG_SW_SEC_CNT
++#define WEP_SW_ENC_CNT_INC(sec, ra) do {\
++	if (is_broadcast_mac_addr(ra)) \
++		sec->wep_sw_enc_cnt_bc++; \
++	else if (is_multicast_mac_addr(ra)) \
++		sec->wep_sw_enc_cnt_mc++; \
++	else \
++		sec->wep_sw_enc_cnt_uc++; \
++	} while (0)
++
++#define WEP_SW_DEC_CNT_INC(sec, ra) do {\
++	if (is_broadcast_mac_addr(ra)) \
++		sec->wep_sw_dec_cnt_bc++; \
++	else if (is_multicast_mac_addr(ra)) \
++		sec->wep_sw_dec_cnt_mc++; \
++	else \
++		sec->wep_sw_dec_cnt_uc++; \
++	} while (0)
++
++#define TKIP_SW_ENC_CNT_INC(sec, ra) do {\
++	if (is_broadcast_mac_addr(ra)) \
++		sec->tkip_sw_enc_cnt_bc++; \
++	else if (is_multicast_mac_addr(ra)) \
++		sec->tkip_sw_enc_cnt_mc++; \
++	else \
++		sec->tkip_sw_enc_cnt_uc++; \
++	} while (0)
++
++#define TKIP_SW_DEC_CNT_INC(sec, ra) do {\
++	if (is_broadcast_mac_addr(ra)) \
++		sec->tkip_sw_dec_cnt_bc++; \
++	else if (is_multicast_mac_addr(ra)) \
++		sec->tkip_sw_dec_cnt_mc++; \
++	else \
++		sec->tkip_sw_dec_cnt_uc++; \
++	} while (0)
++
++#define AES_SW_ENC_CNT_INC(sec, ra) do {\
++	if (is_broadcast_mac_addr(ra)) \
++		sec->aes_sw_enc_cnt_bc++; \
++	else if (is_multicast_mac_addr(ra)) \
++		sec->aes_sw_enc_cnt_mc++; \
++	else \
++		sec->aes_sw_enc_cnt_uc++; \
++	} while (0)
++
++#define AES_SW_DEC_CNT_INC(sec, ra) do {\
++	if (is_broadcast_mac_addr(ra)) \
++		sec->aes_sw_dec_cnt_bc++; \
++	else if (is_multicast_mac_addr(ra)) \
++		sec->aes_sw_dec_cnt_mc++; \
++	else \
++		sec->aes_sw_dec_cnt_uc++; \
++	} while (0)
++
++#define GCMP_SW_ENC_CNT_INC(sec, ra) do {\
++	if (is_broadcast_mac_addr(ra)) \
++		sec->gcmp_sw_enc_cnt_bc++; \
++	else if (is_multicast_mac_addr(ra)) \
++		sec->gcmp_sw_enc_cnt_mc++; \
++	else \
++		sec->gcmp_sw_enc_cnt_uc++; \
++	} while (0)
++
++#define GCMP_SW_DEC_CNT_INC(sec, ra) do {\
++	if (is_broadcast_mac_addr(ra)) \
++		sec->gcmp_sw_dec_cnt_bc++; \
++	else if (is_multicast_mac_addr(ra)) \
++		sec->gcmp_sw_dec_cnt_mc++; \
++	else \
++		sec->gcmp_sw_dec_cnt_uc++; \
++	} while (0)
++#else
++#define WEP_SW_ENC_CNT_INC(sec, ra)
++#define WEP_SW_DEC_CNT_INC(sec, ra)
++#define TKIP_SW_ENC_CNT_INC(sec, ra)
++#define TKIP_SW_DEC_CNT_INC(sec, ra)
++#define AES_SW_ENC_CNT_INC(sec, ra)
++#define AES_SW_DEC_CNT_INC(sec, ra)
++#define GCMP_SW_ENC_CNT_INC(sec, ra)
++#define GCMP_SW_DEC_CNT_INC(sec, ra)
++#endif /* DBG_SW_SEC_CNT */
++
++/* *****WEP related***** */
++
++#define CRC32_POLY 0x04c11db7
++
++struct arc4context {
++	u32 x;
++	u32 y;
++	u8 state[256];
++};
++
++
++static void arcfour_init(struct arc4context	*parc4ctx, u8 *key, u32	key_len)
++{
++	u32	t, u;
++	u32	keyindex;
++	u32	stateindex;
++	u8 *state;
++	u32	counter;
++	state = parc4ctx->state;
++	parc4ctx->x = 0;
++	parc4ctx->y = 0;
++	for (counter = 0; counter < 256; counter++)
++		state[counter] = (u8)counter;
++	keyindex = 0;
++	stateindex = 0;
++	for (counter = 0; counter < 256; counter++) {
++		t = state[counter];
++		stateindex = (stateindex + key[keyindex] + t) & 0xff;
++		u = state[stateindex];
++		state[stateindex] = (u8)t;
++		state[counter] = (u8)u;
++		if (++keyindex >= key_len)
++			keyindex = 0;
++	}
++}
++static u32 arcfour_byte(struct arc4context	*parc4ctx)
++{
++	u32 x;
++	u32 y;
++	u32 sx, sy;
++	u8 *state;
++	state = parc4ctx->state;
++	x = (parc4ctx->x + 1) & 0xff;
++	sx = state[x];
++	y = (sx + parc4ctx->y) & 0xff;
++	sy = state[y];
++	parc4ctx->x = x;
++	parc4ctx->y = y;
++	state[y] = (u8)sx;
++	state[x] = (u8)sy;
++	return state[(sx + sy) & 0xff];
++}
++
++
++static void arcfour_encrypt(struct arc4context	*parc4ctx,
++			    u8 *dest,
++			    u8 *src,
++			    u32 len)
++{
++	u32	i;
++	for (i = 0; i < len; i++)
++		dest[i] = src[i] ^ (unsigned char)arcfour_byte(parc4ctx);
++}
++
++static sint bcrc32initialized = 0;
++static u32 crc32_table[256];
++
++
++static u8 crc32_reverseBit(u8 data)
++{
++	return (u8)((data << 7) & 0x80) | ((data << 5) & 0x40) | ((data << 3) & 0x20) | ((data << 1) & 0x10) | ((data >> 1) & 0x08) | ((data >> 3) & 0x04) | ((data >> 5) & 0x02) | ((
++				data >> 7) & 0x01) ;
++}
++
++static void crc32_init(void)
++{
++	if (bcrc32initialized == 1)
++		goto exit;
++	else {
++		sint i, j;
++		u32 c;
++		u8 *p = (u8 *)&c, *p1;
++		u8 k;
++
++		c = 0x12340000;
++
++		for (i = 0; i < 256; ++i) {
++			k = crc32_reverseBit((u8)i);
++			for (c = ((u32)k) << 24, j = 8; j > 0; --j)
++				c = c & 0x80000000 ? (c << 1) ^ CRC32_POLY : (c << 1);
++			p1 = (u8 *)&crc32_table[i];
++
++			p1[0] = crc32_reverseBit(p[3]);
++			p1[1] = crc32_reverseBit(p[2]);
++			p1[2] = crc32_reverseBit(p[1]);
++			p1[3] = crc32_reverseBit(p[0]);
++		}
++		bcrc32initialized = 1;
++	}
++exit:
++	return;
++}
++
++static u32 getcrc32(u8 *buf, sint len)
++{
++	u8 *p;
++	u32  crc;
++	if (bcrc32initialized == 0)
++		crc32_init();
++
++	crc = 0xffffffff;       /* preload shift register, per CRC-32 spec */
++
++	for (p = buf; len > 0; ++p, --len)
++		crc = crc32_table[(crc ^ *p) & 0xff] ^ (crc >> 8);
++	return ~crc;    /* transmit complement, per CRC-32 spec */
++}
++
++
++/*
++	Need to consider the fragment  situation
++*/
++void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe)
++{
++	/* exclude ICV */
++
++	unsigned char	crc[4];
++	struct arc4context	 mycontext;
++
++	sint	curfragnum, length;
++	u32	keylength;
++
++	u8	*pframe, *payload, *iv;   /* ,*wepkey */
++	u8	wepkey[16];
++	u8   hw_hdr_offset = 0;
++	struct	pkt_attrib	*pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
++	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
++	struct	xmit_priv		*pxmitpriv = &padapter->xmitpriv;
++
++
++
++	if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
++		return;
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++	hw_hdr_offset = TXDESC_SIZE +
++		(((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);
++#else
++#ifdef CONFIG_TX_EARLY_MODE
++	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
++#else
++	hw_hdr_offset = TXDESC_OFFSET;
++#endif
++#endif
++
++	pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset;
++
++	/* start to encrypt each fragment */
++	if ((pattrib->encrypt == _WEP40_) || (pattrib->encrypt == _WEP104_)) {
++		keylength = psecuritypriv->dot11DefKeylen[psecuritypriv->dot11PrivacyKeyIndex];
++
++		for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {
++			iv = pframe + pattrib->hdrlen;
++			_rtw_memcpy(&wepkey[0], iv, 3);
++			_rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0], keylength);
++			payload = pframe + pattrib->iv_len + pattrib->hdrlen;
++
++			if ((curfragnum + 1) == pattrib->nr_frags) {
++				/* the last fragment */
++
++				length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
++
++				*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length));
++
++				arcfour_init(&mycontext, wepkey, 3 + keylength);
++				arcfour_encrypt(&mycontext, payload, payload, length);
++				arcfour_encrypt(&mycontext, payload + length, crc, 4);
++
++			} else {
++				length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ;
++				*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length));
++				arcfour_init(&mycontext, wepkey, 3 + keylength);
++				arcfour_encrypt(&mycontext, payload, payload, length);
++				arcfour_encrypt(&mycontext, payload + length, crc, 4);
++
++				pframe += pxmitpriv->frag_len;
++				pframe = (u8 *)RND4((SIZE_PTR)(pframe));
++
++			}
++
++		}
++
++		WEP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra);
++	}
++
++
++}
++
++void rtw_wep_decrypt(_adapter  *padapter, u8 *precvframe)
++{
++	/* exclude ICV */
++	u8	crc[4];
++	struct arc4context	 mycontext;
++	sint	length;
++	u32	keylength;
++	u8	*pframe, *payload, *iv, wepkey[16];
++	u8	 keyindex;
++	struct	rx_pkt_attrib	*prxattrib = &(((union recv_frame *)precvframe)->u.hdr.attrib);
++	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
++
++
++	pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;
++
++	/* start to decrypt recvframe */
++	if ((prxattrib->encrypt == _WEP40_) || (prxattrib->encrypt == _WEP104_)) {
++		iv = pframe + prxattrib->hdrlen;
++		/* keyindex=(iv[3]&0x3); */
++		keyindex = prxattrib->key_index;
++		keylength = psecuritypriv->dot11DefKeylen[keyindex];
++		_rtw_memcpy(&wepkey[0], iv, 3);
++		/* _rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0],keylength); */
++		_rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[keyindex].skey[0], keylength);
++		length = ((union recv_frame *)precvframe)->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len;
++
++		payload = pframe + prxattrib->iv_len + prxattrib->hdrlen;
++
++		/* decrypt payload include icv */
++		arcfour_init(&mycontext, wepkey, 3 + keylength);
++		arcfour_encrypt(&mycontext, payload, payload,  length);
++
++		/* calculate icv and compare the icv */
++		*((u32 *)crc) = le32_to_cpu(getcrc32(payload, length - 4));
++
++
++		WEP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);
++	}
++
++
++	return;
++
++}
++
++/* 3		=====TKIP related===== */
++
++static u32 secmicgetuint32(u8 *p)
++/* Convert from Byte[] to Us4Byte32 in a portable way */
++{
++	s32 i;
++	u32 res = 0;
++	for (i = 0; i < 4; i++)
++		res |= ((u32)(*p++)) << (8 * i);
++	return res;
++}
++
++static void secmicputuint32(u8 *p, u32 val)
++/* Convert from Us4Byte32 to Byte[] in a portable way */
++{
++	long i;
++	for (i = 0; i < 4; i++) {
++		*p++ = (u8)(val & 0xff);
++		val >>= 8;
++	}
++}
++
++static void secmicclear(struct mic_data *pmicdata)
++{
++	/* Reset the state to the empty message. */
++	pmicdata->L = pmicdata->K0;
++	pmicdata->R = pmicdata->K1;
++	pmicdata->nBytesInM = 0;
++	pmicdata->M = 0;
++}
++
++void rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key)
++{
++	/* Set the key */
++	pmicdata->K0 = secmicgetuint32(key);
++	pmicdata->K1 = secmicgetuint32(key + 4);
++	/* and reset the message */
++	secmicclear(pmicdata);
++}
++
++void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b)
++{
++	/* Append the byte to our word-sized buffer */
++	pmicdata->M |= ((unsigned long)b) << (8 * pmicdata->nBytesInM);
++	pmicdata->nBytesInM++;
++	/* Process the word if it is full. */
++	if (pmicdata->nBytesInM >= 4) {
++		pmicdata->L ^= pmicdata->M;
++		pmicdata->R ^= ROL32(pmicdata->L, 17);
++		pmicdata->L += pmicdata->R;
++		pmicdata->R ^= ((pmicdata->L & 0xff00ff00) >> 8) | ((pmicdata->L & 0x00ff00ff) << 8);
++		pmicdata->L += pmicdata->R;
++		pmicdata->R ^= ROL32(pmicdata->L, 3);
++		pmicdata->L += pmicdata->R;
++		pmicdata->R ^= ROR32(pmicdata->L, 2);
++		pmicdata->L += pmicdata->R;
++		/* Clear the buffer */
++		pmicdata->M = 0;
++		pmicdata->nBytesInM = 0;
++	}
++}
++
++void rtw_secmicappend(struct mic_data *pmicdata, u8 *src, u32 nbytes)
++{
++	/* This is simple */
++	while (nbytes > 0) {
++		rtw_secmicappendbyte(pmicdata, *src++);
++		nbytes--;
++	}
++}
++
++void rtw_secgetmic(struct mic_data *pmicdata, u8 *dst)
++{
++	/* Append the minimum padding */
++	rtw_secmicappendbyte(pmicdata, 0x5a);
++	rtw_secmicappendbyte(pmicdata, 0);
++	rtw_secmicappendbyte(pmicdata, 0);
++	rtw_secmicappendbyte(pmicdata, 0);
++	rtw_secmicappendbyte(pmicdata, 0);
++	/* and then zeroes until the length is a multiple of 4 */
++	while (pmicdata->nBytesInM != 0)
++		rtw_secmicappendbyte(pmicdata, 0);
++	/* The appendByte function has already computed the result. */
++	secmicputuint32(dst, pmicdata->L);
++	secmicputuint32(dst + 4, pmicdata->R);
++	/* Reset to the empty message. */
++	secmicclear(pmicdata);
++}
++
++
++void rtw_seccalctkipmic(u8 *key, u8 *header, u8 *data, u32 data_len, u8 *mic_code, u8 pri)
++{
++
++	struct mic_data	micdata;
++	u8 priority[4] = {0x0, 0x0, 0x0, 0x0};
++	rtw_secmicsetkey(&micdata, key);
++	priority[0] = pri;
++
++	/* Michael MIC pseudo header: DA, SA, 3 x 0, Priority */
++	if (header[1] & 1) { /* ToDS==1 */
++		rtw_secmicappend(&micdata, &header[16], 6);  /* DA */
++		if (header[1] & 2) /* From Ds==1 */
++			rtw_secmicappend(&micdata, &header[24], 6);
++		else
++			rtw_secmicappend(&micdata, &header[10], 6);
++	} else {	/* ToDS==0 */
++		rtw_secmicappend(&micdata, &header[4], 6);   /* DA */
++		if (header[1] & 2) /* From Ds==1 */
++			rtw_secmicappend(&micdata, &header[16], 6);
++		else
++			rtw_secmicappend(&micdata, &header[10], 6);
++
++	}
++	rtw_secmicappend(&micdata, &priority[0], 4);
++
++
++	rtw_secmicappend(&micdata, data, data_len);
++
++	rtw_secgetmic(&micdata, mic_code);
++}
++
++
++
++
++/* macros for extraction/creation of unsigned char/unsigned short values */
++#define RotR1(v16)   ((((v16) >> 1) & 0x7FFF) ^ (((v16) & 1) << 15))
++#define   Lo8(v16)   ((u8)((v16)       & 0x00FF))
++#define   Hi8(v16)   ((u8)(((v16) >> 8) & 0x00FF))
++#define  Lo16(v32)   ((u16)((v32)       & 0xFFFF))
++#define  Hi16(v32)   ((u16)(((v32) >> 16) & 0xFFFF))
++#define  Mk16(hi, lo) ((lo) ^ (((u16)(hi)) << 8))
++
++/* select the Nth 16-bit word of the temporal key unsigned char array TK[]  */
++#define  TK16(N)     Mk16(tk[2*(N)+1], tk[2*(N)])
++
++/* S-box lookup: 16 bits --> 16 bits */
++#define _S_(v16)     (Sbox1[0][Lo8(v16)] ^ Sbox1[1][Hi8(v16)])
++
++/* fixed algorithm "parameters" */
++#define PHASE1_LOOP_CNT   8    /* this needs to be "big enough"     */
++#define TA_SIZE           6    /*  48-bit transmitter address      */
++#define TK_SIZE          16    /* 128-bit temporal key             */
++#define P1K_SIZE         10    /*  80-bit Phase1 key               */
++#define RC4_KEY_SIZE     16    /* 128-bit RC4KEY (104 bits unknown) */
++
++
++/* 2-unsigned char by 2-unsigned char subset of the full AES S-box table */
++static const unsigned short Sbox1[2][256] =      /* Sbox for hash (can be in ROM)    */
++{ {
++		0xC6A5, 0xF884, 0xEE99, 0xF68D, 0xFF0D, 0xD6BD, 0xDEB1, 0x9154,
++		0x6050, 0x0203, 0xCEA9, 0x567D, 0xE719, 0xB562, 0x4DE6, 0xEC9A,
++		0x8F45, 0x1F9D, 0x8940, 0xFA87, 0xEF15, 0xB2EB, 0x8EC9, 0xFB0B,
++		0x41EC, 0xB367, 0x5FFD, 0x45EA, 0x23BF, 0x53F7, 0xE496, 0x9B5B,
++		0x75C2, 0xE11C, 0x3DAE, 0x4C6A, 0x6C5A, 0x7E41, 0xF502, 0x834F,
++		0x685C, 0x51F4, 0xD134, 0xF908, 0xE293, 0xAB73, 0x6253, 0x2A3F,
++		0x080C, 0x9552, 0x4665, 0x9D5E, 0x3028, 0x37A1, 0x0A0F, 0x2FB5,
++		0x0E09, 0x2436, 0x1B9B, 0xDF3D, 0xCD26, 0x4E69, 0x7FCD, 0xEA9F,
++		0x121B, 0x1D9E, 0x5874, 0x342E, 0x362D, 0xDCB2, 0xB4EE, 0x5BFB,
++		0xA4F6, 0x764D, 0xB761, 0x7DCE, 0x527B, 0xDD3E, 0x5E71, 0x1397,
++		0xA6F5, 0xB968, 0x0000, 0xC12C, 0x4060, 0xE31F, 0x79C8, 0xB6ED,
++		0xD4BE, 0x8D46, 0x67D9, 0x724B, 0x94DE, 0x98D4, 0xB0E8, 0x854A,
++		0xBB6B, 0xC52A, 0x4FE5, 0xED16, 0x86C5, 0x9AD7, 0x6655, 0x1194,
++		0x8ACF, 0xE910, 0x0406, 0xFE81, 0xA0F0, 0x7844, 0x25BA, 0x4BE3,
++		0xA2F3, 0x5DFE, 0x80C0, 0x058A, 0x3FAD, 0x21BC, 0x7048, 0xF104,
++		0x63DF, 0x77C1, 0xAF75, 0x4263, 0x2030, 0xE51A, 0xFD0E, 0xBF6D,
++		0x814C, 0x1814, 0x2635, 0xC32F, 0xBEE1, 0x35A2, 0x88CC, 0x2E39,
++		0x9357, 0x55F2, 0xFC82, 0x7A47, 0xC8AC, 0xBAE7, 0x322B, 0xE695,
++		0xC0A0, 0x1998, 0x9ED1, 0xA37F, 0x4466, 0x547E, 0x3BAB, 0x0B83,
++		0x8CCA, 0xC729, 0x6BD3, 0x283C, 0xA779, 0xBCE2, 0x161D, 0xAD76,
++		0xDB3B, 0x6456, 0x744E, 0x141E, 0x92DB, 0x0C0A, 0x486C, 0xB8E4,
++		0x9F5D, 0xBD6E, 0x43EF, 0xC4A6, 0x39A8, 0x31A4, 0xD337, 0xF28B,
++		0xD532, 0x8B43, 0x6E59, 0xDAB7, 0x018C, 0xB164, 0x9CD2, 0x49E0,
++		0xD8B4, 0xACFA, 0xF307, 0xCF25, 0xCAAF, 0xF48E, 0x47E9, 0x1018,
++		0x6FD5, 0xF088, 0x4A6F, 0x5C72, 0x3824, 0x57F1, 0x73C7, 0x9751,
++		0xCB23, 0xA17C, 0xE89C, 0x3E21, 0x96DD, 0x61DC, 0x0D86, 0x0F85,
++		0xE090, 0x7C42, 0x71C4, 0xCCAA, 0x90D8, 0x0605, 0xF701, 0x1C12,
++		0xC2A3, 0x6A5F, 0xAEF9, 0x69D0, 0x1791, 0x9958, 0x3A27, 0x27B9,
++		0xD938, 0xEB13, 0x2BB3, 0x2233, 0xD2BB, 0xA970, 0x0789, 0x33A7,
++		0x2DB6, 0x3C22, 0x1592, 0xC920, 0x8749, 0xAAFF, 0x5078, 0xA57A,
++		0x038F, 0x59F8, 0x0980, 0x1A17, 0x65DA, 0xD731, 0x84C6, 0xD0B8,
++		0x82C3, 0x29B0, 0x5A77, 0x1E11, 0x7BCB, 0xA8FC, 0x6DD6, 0x2C3A,
++	},
++
++
++	{  /* second half of table is unsigned char-reversed version of first! */
++		0xA5C6, 0x84F8, 0x99EE, 0x8DF6, 0x0DFF, 0xBDD6, 0xB1DE, 0x5491,
++		0x5060, 0x0302, 0xA9CE, 0x7D56, 0x19E7, 0x62B5, 0xE64D, 0x9AEC,
++		0x458F, 0x9D1F, 0x4089, 0x87FA, 0x15EF, 0xEBB2, 0xC98E, 0x0BFB,
++		0xEC41, 0x67B3, 0xFD5F, 0xEA45, 0xBF23, 0xF753, 0x96E4, 0x5B9B,
++		0xC275, 0x1CE1, 0xAE3D, 0x6A4C, 0x5A6C, 0x417E, 0x02F5, 0x4F83,
++		0x5C68, 0xF451, 0x34D1, 0x08F9, 0x93E2, 0x73AB, 0x5362, 0x3F2A,
++		0x0C08, 0x5295, 0x6546, 0x5E9D, 0x2830, 0xA137, 0x0F0A, 0xB52F,
++		0x090E, 0x3624, 0x9B1B, 0x3DDF, 0x26CD, 0x694E, 0xCD7F, 0x9FEA,
++		0x1B12, 0x9E1D, 0x7458, 0x2E34, 0x2D36, 0xB2DC, 0xEEB4, 0xFB5B,
++		0xF6A4, 0x4D76, 0x61B7, 0xCE7D, 0x7B52, 0x3EDD, 0x715E, 0x9713,
++		0xF5A6, 0x68B9, 0x0000, 0x2CC1, 0x6040, 0x1FE3, 0xC879, 0xEDB6,
++		0xBED4, 0x468D, 0xD967, 0x4B72, 0xDE94, 0xD498, 0xE8B0, 0x4A85,
++		0x6BBB, 0x2AC5, 0xE54F, 0x16ED, 0xC586, 0xD79A, 0x5566, 0x9411,
++		0xCF8A, 0x10E9, 0x0604, 0x81FE, 0xF0A0, 0x4478, 0xBA25, 0xE34B,
++		0xF3A2, 0xFE5D, 0xC080, 0x8A05, 0xAD3F, 0xBC21, 0x4870, 0x04F1,
++		0xDF63, 0xC177, 0x75AF, 0x6342, 0x3020, 0x1AE5, 0x0EFD, 0x6DBF,
++		0x4C81, 0x1418, 0x3526, 0x2FC3, 0xE1BE, 0xA235, 0xCC88, 0x392E,
++		0x5793, 0xF255, 0x82FC, 0x477A, 0xACC8, 0xE7BA, 0x2B32, 0x95E6,
++		0xA0C0, 0x9819, 0xD19E, 0x7FA3, 0x6644, 0x7E54, 0xAB3B, 0x830B,
++		0xCA8C, 0x29C7, 0xD36B, 0x3C28, 0x79A7, 0xE2BC, 0x1D16, 0x76AD,
++		0x3BDB, 0x5664, 0x4E74, 0x1E14, 0xDB92, 0x0A0C, 0x6C48, 0xE4B8,
++		0x5D9F, 0x6EBD, 0xEF43, 0xA6C4, 0xA839, 0xA431, 0x37D3, 0x8BF2,
++		0x32D5, 0x438B, 0x596E, 0xB7DA, 0x8C01, 0x64B1, 0xD29C, 0xE049,
++		0xB4D8, 0xFAAC, 0x07F3, 0x25CF, 0xAFCA, 0x8EF4, 0xE947, 0x1810,
++		0xD56F, 0x88F0, 0x6F4A, 0x725C, 0x2438, 0xF157, 0xC773, 0x5197,
++		0x23CB, 0x7CA1, 0x9CE8, 0x213E, 0xDD96, 0xDC61, 0x860D, 0x850F,
++		0x90E0, 0x427C, 0xC471, 0xAACC, 0xD890, 0x0506, 0x01F7, 0x121C,
++		0xA3C2, 0x5F6A, 0xF9AE, 0xD069, 0x9117, 0x5899, 0x273A, 0xB927,
++		0x38D9, 0x13EB, 0xB32B, 0x3322, 0xBBD2, 0x70A9, 0x8907, 0xA733,
++		0xB62D, 0x223C, 0x9215, 0x20C9, 0x4987, 0xFFAA, 0x7850, 0x7AA5,
++		0x8F03, 0xF859, 0x8009, 0x171A, 0xDA65, 0x31D7, 0xC684, 0xB8D0,
++		0xC382, 0xB029, 0x775A, 0x111E, 0xCB7B, 0xFCA8, 0xD66D, 0x3A2C,
++	}
++};
++
++/*
++**********************************************************************
++* Routine: Phase 1 -- generate P1K, given TA, TK, IV32
++*
++* Inputs:
++*     tk[]      = temporal key                         [128 bits]
++*     ta[]      = transmitter's MAC address            [ 48 bits]
++*     iv32      = upper 32 bits of IV                  [ 32 bits]
++* Output:
++*     p1k[]     = Phase 1 key                          [ 80 bits]
++*
++* Note:
++*     This function only needs to be called every 2**16 packets,
++*     although in theory it could be called every packet.
++*
++**********************************************************************
++*/
++static void phase1(u16 *p1k, const u8 *tk, const u8 *ta, u32 iv32)
++{
++	sint  i;
++	/* Initialize the 80 bits of P1K[] from IV32 and TA[0..5]    */
++	p1k[0]      = Lo16(iv32);
++	p1k[1]      = Hi16(iv32);
++	p1k[2]      = Mk16(ta[1], ta[0]); /* use TA[] as little-endian */
++	p1k[3]      = Mk16(ta[3], ta[2]);
++	p1k[4]      = Mk16(ta[5], ta[4]);
++
++	/* Now compute an unbalanced Feistel cipher with 80-bit block */
++	/* size on the 80-bit block P1K[], using the 128-bit key TK[] */
++	for (i = 0; i < PHASE1_LOOP_CNT ; i++) {
++		/* Each add operation here is mod 2**16 */
++		p1k[0] += _S_(p1k[4] ^ TK16((i & 1) + 0));
++		p1k[1] += _S_(p1k[0] ^ TK16((i & 1) + 2));
++		p1k[2] += _S_(p1k[1] ^ TK16((i & 1) + 4));
++		p1k[3] += _S_(p1k[2] ^ TK16((i & 1) + 6));
++		p1k[4] += _S_(p1k[3] ^ TK16((i & 1) + 0));
++		p1k[4] += (unsigned short)i;                     /* avoid "slide attacks" */
++	}
++}
++
++
++/*
++**********************************************************************
++* Routine: Phase 2 -- generate RC4KEY, given TK, P1K, IV16
++*
++* Inputs:
++*     tk[]      = Temporal key                         [128 bits]
++*     p1k[]     = Phase 1 output key                   [ 80 bits]
++*     iv16      = low 16 bits of IV counter            [ 16 bits]
++* Output:
++*     rc4key[]  = the key used to encrypt the packet   [128 bits]
++*
++* Note:
++*     The value {TA,IV32,IV16} for Phase1/Phase2 must be unique
++*     across all packets using the same key TK value. Then, for a
++*     given value of TK[], this TKIP48 construction guarantees that
++*     the final RC4KEY value is unique across all packets.
++*
++* Suggested implementation optimization: if PPK[] is "overlaid"
++*     appropriately on RC4KEY[], there is no need for the final
++*     for loop below that copies the PPK[] result into RC4KEY[].
++*
++**********************************************************************
++*/
++static void phase2(u8 *rc4key, const u8 *tk, const u16 *p1k, u16 iv16)
++{
++	sint  i;
++	u16 PPK[6];                          /* temporary key for mixing   */
++	/* Note: all adds in the PPK[] equations below are mod 2**16        */
++	for (i = 0; i < 5; i++)
++		PPK[i] = p1k[i];    /* first, copy P1K to PPK     */
++	PPK[5]  =  p1k[4] + iv16;            /* next,  add in IV16         */
++
++	/* Bijective non-linear mixing of the 96 bits of PPK[0..5]          */
++	PPK[0] +=    _S_(PPK[5] ^ TK16(0));   /* Mix key in each "round"     */
++	PPK[1] +=    _S_(PPK[0] ^ TK16(1));
++	PPK[2] +=    _S_(PPK[1] ^ TK16(2));
++	PPK[3] +=    _S_(PPK[2] ^ TK16(3));
++	PPK[4] +=    _S_(PPK[3] ^ TK16(4));
++	PPK[5] +=    _S_(PPK[4] ^ TK16(5));   /* Total # S-box lookups == 6 */
++
++	/* Final sweep: bijective, "linear". Rotates kill LSB correlations   */
++	PPK[0] +=  RotR1(PPK[5] ^ TK16(6));
++	PPK[1] +=  RotR1(PPK[0] ^ TK16(7));   /* Use all of TK[] in Phase2  */
++	PPK[2] +=  RotR1(PPK[1]);
++	PPK[3] +=  RotR1(PPK[2]);
++	PPK[4] +=  RotR1(PPK[3]);
++	PPK[5] +=  RotR1(PPK[4]);
++	/* Note: At this point, for a given key TK[0..15], the 96-bit output */
++	/*       value PPK[0..5] is guaranteed to be unique, as a function  */
++	/*       of the 96-bit "input" value   {TA,IV32,IV16}. That is, P1K  */
++	/*       is now a keyed permutation of {TA,IV32,IV16}.              */
++
++	/* Set RC4KEY[0..3], which includes "cleartext" portion of RC4 key   */
++	rc4key[0] = Hi8(iv16);                /* RC4KEY[0..2] is the WEP IV */
++	rc4key[1] = (Hi8(iv16) | 0x20) & 0x7F; /* Help avoid weak (FMS) keys */
++	rc4key[2] = Lo8(iv16);
++	rc4key[3] = Lo8((PPK[5] ^ TK16(0)) >> 1);
++
++
++	/* Copy 96 bits of PPK[0..5] to RC4KEY[4..15]  (little-endian)      */
++	for (i = 0; i < 6; i++) {
++		rc4key[4 + 2 * i] = Lo8(PPK[i]);
++		rc4key[5 + 2 * i] = Hi8(PPK[i]);
++	}
++}
++
++
++/* The hlen isn't include the IV */
++u32	rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe)
++{
++	/* exclude ICV */
++	u16	pnl;
++	u32	pnh;
++	u8	rc4key[16];
++	u8   ttkey[16];
++	u8	crc[4];
++	u8   hw_hdr_offset = 0;
++	struct arc4context mycontext;
++	sint			curfragnum, length;
++	u32	prwskeylen;
++
++	u8	*pframe, *payload, *iv, *prwskey;
++	union pn48 dot11txpn;
++	/* struct	sta_info		*stainfo; */
++	struct	pkt_attrib	*pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
++	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
++	struct	xmit_priv		*pxmitpriv = &padapter->xmitpriv;
++	u32	res = _SUCCESS;
++
++	if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
++		return _FAIL;
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++	hw_hdr_offset = TXDESC_SIZE +
++		(((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);
++#else
++#ifdef CONFIG_TX_EARLY_MODE
++	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
++#else
++	hw_hdr_offset = TXDESC_OFFSET;
++#endif
++#endif
++
++	pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset;
++	/* 4 start to encrypt each fragment */
++	if (pattrib->encrypt == _TKIP_) {
++
++		/*
++				if(pattrib->psta)
++				{
++					stainfo = pattrib->psta;
++				}
++				else
++				{
++					RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
++					stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] );
++				}
++		*/
++		/* if (stainfo!=NULL) */
++		{
++			/*
++						if(!(stainfo->state &WIFI_ASOC_STATE))
++						{
++							RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, stainfo->state);
++							return _FAIL;
++						}
++			*/
++
++			if (IS_MCAST(pattrib->ra))
++				prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;
++			else {
++				/* prwskey=&stainfo->dot118021x_UncstKey.skey[0]; */
++				prwskey = pattrib->dot118021x_UncstKey.skey;
++			}
++
++			prwskeylen = 16;
++
++			for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {
++				iv = pframe + pattrib->hdrlen;
++				payload = pframe + pattrib->iv_len + pattrib->hdrlen;
++
++				GET_TKIP_PN(iv, dot11txpn);
++
++				pnl = (u16)(dot11txpn.val);
++				pnh = (u32)(dot11txpn.val >> 16);
++
++				phase1((u16 *)&ttkey[0], prwskey, &pattrib->ta[0], pnh);
++
++				phase2(&rc4key[0], prwskey, (u16 *)&ttkey[0], pnl);
++
++				if ((curfragnum + 1) == pattrib->nr_frags) {	/* 4 the last fragment */
++					length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
++					*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); /* modified by Amy*/
++
++					arcfour_init(&mycontext, rc4key, 16);
++					arcfour_encrypt(&mycontext, payload, payload, length);
++					arcfour_encrypt(&mycontext, payload + length, crc, 4);
++
++				} else {
++					length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ;
++					*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); /* modified by Amy*/
++					arcfour_init(&mycontext, rc4key, 16);
++					arcfour_encrypt(&mycontext, payload, payload, length);
++					arcfour_encrypt(&mycontext, payload + length, crc, 4);
++
++					pframe += pxmitpriv->frag_len;
++					pframe = (u8 *)RND4((SIZE_PTR)(pframe));
++
++				}
++			}
++
++			TKIP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra);
++		}
++		/*
++				else{
++					RTW_INFO("%s, psta==NUL\n", __func__);
++					res=_FAIL;
++				}
++		*/
++
++	}
++	return res;
++
++}
++
++
++/* The hlen isn't include the IV */
++u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe)
++{
++	/* exclude ICV */
++	u16 pnl;
++	u32 pnh;
++	u8   rc4key[16];
++	u8   ttkey[16];
++	u8	crc[4];
++	struct arc4context mycontext;
++	sint			length;
++	u32	prwskeylen;
++
++	u8	*pframe, *payload, *iv, *prwskey;
++	union pn48 dot11txpn;
++	struct	sta_info		*stainfo;
++	struct	rx_pkt_attrib	*prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;
++	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
++	/*	struct	recv_priv		*precvpriv=&padapter->recvpriv; */
++	u32		res = _SUCCESS;
++
++
++	pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;
++
++	/* 4 start to decrypt recvframe */
++	if (prxattrib->encrypt == _TKIP_) {
++
++		stainfo = rtw_get_stainfo(&padapter->stapriv , &prxattrib->ta[0]);
++		if (stainfo != NULL) {
++
++			if (IS_MCAST(prxattrib->ra)) {
++				static systime start = 0;
++				static u32 no_gkey_bc_cnt = 0;
++				static u32 no_gkey_mc_cnt = 0;
++
++				if (psecuritypriv->binstallGrpkey == _FALSE) {
++					res = _FAIL;
++
++					if (start == 0)
++						start = rtw_get_current_time();
++
++					if (is_broadcast_mac_addr(prxattrib->ra))
++						no_gkey_bc_cnt++;
++					else
++						no_gkey_mc_cnt++;
++
++					if (rtw_get_passing_time_ms(start) > 1000) {
++						if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
++							RTW_PRINT(FUNC_ADPT_FMT" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
++								FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
++						}
++						start = rtw_get_current_time();
++						no_gkey_bc_cnt = 0;
++						no_gkey_mc_cnt = 0;
++					}
++					goto exit;
++				}
++
++				if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
++					RTW_PRINT(FUNC_ADPT_FMT" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
++						FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
++				}
++				start = 0;
++				no_gkey_bc_cnt = 0;
++				no_gkey_mc_cnt = 0;
++
++				/* RTW_INFO("rx bc/mc packets, to perform sw rtw_tkip_decrypt\n"); */
++				/* prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; */
++				prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey;
++				prwskeylen = 16;
++			} else {
++				prwskey = &stainfo->dot118021x_UncstKey.skey[0];
++				prwskeylen = 16;
++			}
++
++			iv = pframe + prxattrib->hdrlen;
++			payload = pframe + prxattrib->iv_len + prxattrib->hdrlen;
++			length = ((union recv_frame *)precvframe)->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len;
++
++			GET_TKIP_PN(iv, dot11txpn);
++
++			pnl = (u16)(dot11txpn.val);
++			pnh = (u32)(dot11txpn.val >> 16);
++
++			phase1((u16 *)&ttkey[0], prwskey, &prxattrib->ta[0], pnh);
++			phase2(&rc4key[0], prwskey, (unsigned short *)&ttkey[0], pnl);
++
++			/* 4 decrypt payload include icv */
++
++			arcfour_init(&mycontext, rc4key, 16);
++			arcfour_encrypt(&mycontext, payload, payload, length);
++
++			*((u32 *)crc) = le32_to_cpu(getcrc32(payload, length - 4));
++
++			if (crc[3] != payload[length - 1] || crc[2] != payload[length - 2] || crc[1] != payload[length - 3] || crc[0] != payload[length - 4]) {
++				res = _FAIL;
++			}
++
++			TKIP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);
++		} else {
++			res = _FAIL;
++		}
++
++	}
++exit:
++	return res;
++
++}
++
++
++/* 3			=====AES related===== */
++#if (NEW_CRYPTO == 0)
++
++#define MAX_MSG_SIZE	2048
++/*****************************/
++/******** SBOX Table *********/
++/*****************************/
++
++static  u8 sbox_table[256] = {
++	0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5,
++	0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
++	0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0,
++	0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
++	0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc,
++	0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
++	0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a,
++	0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
++	0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0,
++	0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
++	0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b,
++	0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
++	0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85,
++	0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
++	0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5,
++	0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
++	0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17,
++	0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
++	0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88,
++	0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
++	0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c,
++	0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
++	0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9,
++	0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
++	0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6,
++	0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
++	0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e,
++	0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
++	0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94,
++	0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
++	0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68,
++	0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
++};
++
++/*****************************/
++/**** Function Prototypes ****/
++/*****************************/
++
++static void bitwise_xor(u8 *ina, u8 *inb, u8 *out);
++static void construct_mic_iv(
++	u8 *mic_header1,
++	sint qc_exists,
++	sint a4_exists,
++	u8 *mpdu,
++	uint payload_length,
++	u8 *pn_vector,
++	uint frtype);/* add for CONFIG_IEEE80211W, none 11w also can use */
++static void construct_mic_header1(
++	u8 *mic_header1,
++	sint header_length,
++	u8 *mpdu,
++	uint frtype);/* add for CONFIG_IEEE80211W, none 11w also can use */
++static void construct_mic_header2(
++	u8 *mic_header2,
++	u8 *mpdu,
++	sint a4_exists,
++	sint qc_exists);
++static void construct_ctr_preload(
++	u8 *ctr_preload,
++	sint a4_exists,
++	sint qc_exists,
++	u8 *mpdu,
++	u8 *pn_vector,
++	sint c,
++	uint frtype);/* add for CONFIG_IEEE80211W, none 11w also can use */
++static void xor_128(u8 *a, u8 *b, u8 *out);
++static void xor_32(u8 *a, u8 *b, u8 *out);
++static u8 sbox(u8 a);
++static void next_key(u8 *key, sint round);
++static void byte_sub(u8 *in, u8 *out);
++static void shift_row(u8 *in, u8 *out);
++static void mix_column(u8 *in, u8 *out);
++static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext);
++
++
++/****************************************/
++/* aes128k128d()                       */
++/* Performs a 128 bit AES encrypt with */
++/* 128 bit data.                       */
++/****************************************/
++static void xor_128(u8 *a, u8 *b, u8 *out)
++{
++	sint i;
++	for (i = 0; i < 16; i++)
++		out[i] = a[i] ^ b[i];
++}
++
++
++static void xor_32(u8 *a, u8 *b, u8 *out)
++{
++	sint i;
++	for (i = 0; i < 4; i++)
++		out[i] = a[i] ^ b[i];
++}
++
++
++static u8 sbox(u8 a)
++{
++	return sbox_table[(sint)a];
++}
++
++
++static void next_key(u8 *key, sint round)
++{
++	u8 rcon;
++	u8 sbox_key[4];
++	u8 rcon_table[12] = {
++		0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80,
++		0x1b, 0x36, 0x36, 0x36
++	};
++	sbox_key[0] = sbox(key[13]);
++	sbox_key[1] = sbox(key[14]);
++	sbox_key[2] = sbox(key[15]);
++	sbox_key[3] = sbox(key[12]);
++
++	rcon = rcon_table[round];
++
++	xor_32(&key[0], sbox_key, &key[0]);
++	key[0] = key[0] ^ rcon;
++
++	xor_32(&key[4], &key[0], &key[4]);
++	xor_32(&key[8], &key[4], &key[8]);
++	xor_32(&key[12], &key[8], &key[12]);
++}
++
++
++static void byte_sub(u8 *in, u8 *out)
++{
++	sint i;
++	for (i = 0; i < 16; i++)
++		out[i] = sbox(in[i]);
++}
++
++
++static void shift_row(u8 *in, u8 *out)
++{
++	out[0] =  in[0];
++	out[1] =  in[5];
++	out[2] =  in[10];
++	out[3] =  in[15];
++	out[4] =  in[4];
++	out[5] =  in[9];
++	out[6] =  in[14];
++	out[7] =  in[3];
++	out[8] =  in[8];
++	out[9] =  in[13];
++	out[10] = in[2];
++	out[11] = in[7];
++	out[12] = in[12];
++	out[13] = in[1];
++	out[14] = in[6];
++	out[15] = in[11];
++}
++
++
++static void mix_column(u8 *in, u8 *out)
++{
++	sint i;
++	u8 add1b[4];
++	u8 add1bf7[4];
++	u8 rotl[4];
++	u8 swap_halfs[4];
++	u8 andf7[4];
++	u8 rotr[4];
++	u8 temp[4];
++	u8 tempb[4];
++	for (i = 0 ; i < 4; i++) {
++		if ((in[i] & 0x80) == 0x80)
++			add1b[i] = 0x1b;
++		else
++			add1b[i] = 0x00;
++	}
++
++	swap_halfs[0] = in[2];    /* Swap halfs */
++	swap_halfs[1] = in[3];
++	swap_halfs[2] = in[0];
++	swap_halfs[3] = in[1];
++
++	rotl[0] = in[3];        /* Rotate left 8 bits */
++	rotl[1] = in[0];
++	rotl[2] = in[1];
++	rotl[3] = in[2];
++
++	andf7[0] = in[0] & 0x7f;
++	andf7[1] = in[1] & 0x7f;
++	andf7[2] = in[2] & 0x7f;
++	andf7[3] = in[3] & 0x7f;
++
++	for (i = 3; i > 0; i--) { /* logical shift left 1 bit */
++		andf7[i] = andf7[i] << 1;
++		if ((andf7[i - 1] & 0x80) == 0x80)
++			andf7[i] = (andf7[i] | 0x01);
++	}
++	andf7[0] = andf7[0] << 1;
++	andf7[0] = andf7[0] & 0xfe;
++
++	xor_32(add1b, andf7, add1bf7);
++
++	xor_32(in, add1bf7, rotr);
++
++	temp[0] = rotr[0];         /* Rotate right 8 bits */
++	rotr[0] = rotr[1];
++	rotr[1] = rotr[2];
++	rotr[2] = rotr[3];
++	rotr[3] = temp[0];
++
++	xor_32(add1bf7, rotr, temp);
++	xor_32(swap_halfs, rotl, tempb);
++	xor_32(temp, tempb, out);
++}
++
++
++static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext)
++{
++	sint round;
++	sint i;
++	u8 intermediatea[16];
++	u8 intermediateb[16];
++	u8 round_key[16];
++	for (i = 0; i < 16; i++)
++		round_key[i] = key[i];
++
++	for (round = 0; round < 11; round++) {
++		if (round == 0) {
++			xor_128(round_key, data, ciphertext);
++			next_key(round_key, round);
++		} else if (round == 10) {
++			byte_sub(ciphertext, intermediatea);
++			shift_row(intermediatea, intermediateb);
++			xor_128(intermediateb, round_key, ciphertext);
++		} else { /* 1 - 9 */
++			byte_sub(ciphertext, intermediatea);
++			shift_row(intermediatea, intermediateb);
++			mix_column(&intermediateb[0], &intermediatea[0]);
++			mix_column(&intermediateb[4], &intermediatea[4]);
++			mix_column(&intermediateb[8], &intermediatea[8]);
++			mix_column(&intermediateb[12], &intermediatea[12]);
++			xor_128(intermediatea, round_key, ciphertext);
++			next_key(round_key, round);
++		}
++	}
++}
++
++
++/************************************************/
++/* construct_mic_iv()                          */
++/* Builds the MIC IV from header fields and PN */
++/* Baron think the function is construct CCM   */
++/* nonce                                       */
++/************************************************/
++static void construct_mic_iv(
++	u8 *mic_iv,
++	sint qc_exists,
++	sint a4_exists,
++	u8 *mpdu,
++	uint payload_length,
++	u8 *pn_vector,
++	uint frtype/* add for CONFIG_IEEE80211W, none 11w also can use */
++)
++{
++	sint i;
++	mic_iv[0] = 0x59;
++	if (qc_exists && a4_exists)
++		mic_iv[1] = mpdu[30] & 0x0f;    /* QoS_TC          */
++	if (qc_exists && !a4_exists)
++		mic_iv[1] = mpdu[24] & 0x0f;   /* mute bits 7-4   */
++	if (!qc_exists)
++		mic_iv[1] = 0x00;
++#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
++	/* 802.11w management frame should set management bit(4) */
++	if (frtype == WIFI_MGT_TYPE)
++		mic_iv[1] |= BIT(4);
++#endif
++	for (i = 2; i < 8; i++)
++		mic_iv[i] = mpdu[i + 8];                    /* mic_iv[2:7] = A2[0:5] = mpdu[10:15] */
++#ifdef CONSISTENT_PN_ORDER
++	for (i = 8; i < 14; i++)
++		mic_iv[i] = pn_vector[i - 8];           /* mic_iv[8:13] = PN[0:5] */
++#else
++	for (i = 8; i < 14; i++)
++		mic_iv[i] = pn_vector[13 - i];          /* mic_iv[8:13] = PN[5:0] */
++#endif
++	mic_iv[14] = (unsigned char)(payload_length / 256);
++	mic_iv[15] = (unsigned char)(payload_length % 256);
++}
++
++
++/************************************************/
++/* construct_mic_header1()                     */
++/* Builds the first MIC header block from      */
++/* header fields.                              */
++/* Build AAD SC,A1,A2                          */
++/************************************************/
++static void construct_mic_header1(
++	u8 *mic_header1,
++	sint header_length,
++	u8 *mpdu,
++	uint frtype/* add for CONFIG_IEEE80211W, none 11w also can use */
++)
++{
++	mic_header1[0] = (u8)((header_length - 2) / 256);
++	mic_header1[1] = (u8)((header_length - 2) % 256);
++#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
++	/* 802.11w management frame don't AND subtype bits 4,5,6 of frame control field */
++	if (frtype == WIFI_MGT_TYPE)
++		mic_header1[2] = mpdu[0];
++	else
++#endif
++		mic_header1[2] = mpdu[0] & 0xcf;    /* Mute CF poll & CF ack bits */
++
++	mic_header1[3] = mpdu[1] & 0xc7;    /* Mute retry, more data and pwr mgt bits */
++	mic_header1[4] = mpdu[4];       /* A1 */
++	mic_header1[5] = mpdu[5];
++	mic_header1[6] = mpdu[6];
++	mic_header1[7] = mpdu[7];
++	mic_header1[8] = mpdu[8];
++	mic_header1[9] = mpdu[9];
++	mic_header1[10] = mpdu[10];     /* A2 */
++	mic_header1[11] = mpdu[11];
++	mic_header1[12] = mpdu[12];
++	mic_header1[13] = mpdu[13];
++	mic_header1[14] = mpdu[14];
++	mic_header1[15] = mpdu[15];
++}
++
++
++/************************************************/
++/* construct_mic_header2()                     */
++/* Builds the last MIC header block from       */
++/* header fields.                              */
++/************************************************/
++static void construct_mic_header2(
++	u8 *mic_header2,
++	u8 *mpdu,
++	sint a4_exists,
++	sint qc_exists
++)
++{
++	sint i;
++	for (i = 0; i < 16; i++)
++		mic_header2[i] = 0x00;
++
++	mic_header2[0] = mpdu[16];    /* A3 */
++	mic_header2[1] = mpdu[17];
++	mic_header2[2] = mpdu[18];
++	mic_header2[3] = mpdu[19];
++	mic_header2[4] = mpdu[20];
++	mic_header2[5] = mpdu[21];
++
++	/* mic_header2[6] = mpdu[22] & 0xf0;    SC */
++	mic_header2[6] = 0x00;
++	mic_header2[7] = 0x00; /* mpdu[23]; */
++
++
++	if (!qc_exists && a4_exists) {
++		for (i = 0; i < 6; i++)
++			mic_header2[8 + i] = mpdu[24 + i]; /* A4 */
++
++	}
++
++	if (qc_exists && !a4_exists) {
++		mic_header2[8] = mpdu[24] & 0x0f; /* mute bits 15 - 4 */
++		mic_header2[9] = mpdu[25] & 0x00;
++	}
++
++	if (qc_exists && a4_exists) {
++		for (i = 0; i < 6; i++)
++			mic_header2[8 + i] = mpdu[24 + i]; /* A4 */
++
++		mic_header2[14] = mpdu[30] & 0x0f;
++		mic_header2[15] = mpdu[31] & 0x00;
++	}
++
++}
++
++
++/************************************************/
++/* construct_mic_header2()                     */
++/* Builds the last MIC header block from       */
++/* header fields.                              */
++/* Baron think the function is construct CCM   */
++/* nonce                                       */
++/************************************************/
++static void construct_ctr_preload(
++	u8 *ctr_preload,
++	sint a4_exists,
++	sint qc_exists,
++	u8 *mpdu,
++	u8 *pn_vector,
++	sint c,
++	uint frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
++)
++{
++	sint i = 0;
++	for (i = 0; i < 16; i++)
++		ctr_preload[i] = 0x00;
++	i = 0;
++
++	ctr_preload[0] = 0x01;                                  /* flag */
++	if (qc_exists && a4_exists)
++		ctr_preload[1] = mpdu[30] & 0x0f;   /* QoC_Control */
++	if (qc_exists && !a4_exists)
++		ctr_preload[1] = mpdu[24] & 0x0f;
++#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
++	/* 802.11w management frame should set management bit(4) */
++	if (frtype == WIFI_MGT_TYPE)
++		ctr_preload[1] |= BIT(4);
++#endif
++	for (i = 2; i < 8; i++)
++		ctr_preload[i] = mpdu[i + 8];                       /* ctr_preload[2:7] = A2[0:5] = mpdu[10:15] */
++#ifdef CONSISTENT_PN_ORDER
++	for (i = 8; i < 14; i++)
++		ctr_preload[i] =    pn_vector[i - 8];           /* ctr_preload[8:13] = PN[0:5] */
++#else
++	for (i = 8; i < 14; i++)
++		ctr_preload[i] =    pn_vector[13 - i];          /* ctr_preload[8:13] = PN[5:0] */
++#endif
++	ctr_preload[14] = (unsigned char)(c / 256);   /* Ctr */
++	ctr_preload[15] = (unsigned char)(c % 256);
++}
++
++
++/************************************/
++/* bitwise_xor()                   */
++/* A 128 bit, bitwise exclusive or */
++/************************************/
++static void bitwise_xor(u8 *ina, u8 *inb, u8 *out)
++{
++	sint i;
++	for (i = 0; i < 16; i++)
++		out[i] = ina[i] ^ inb[i];
++}
++
++
++static sint aes_cipher(u8 *key, uint	hdrlen,
++		       u8 *pframe, uint plen)
++{
++	/*	static unsigned char	message[MAX_MSG_SIZE]; */
++	uint	qc_exists, a4_exists, i, j, payload_remainder,
++		num_blocks, payload_index;
++
++	u8 pn_vector[6];
++	u8 mic_iv[16];
++	u8 mic_header1[16];
++	u8 mic_header2[16];
++	u8 ctr_preload[16];
++
++	/* Intermediate Buffers */
++	u8 chain_buffer[16];
++	u8 aes_out[16];
++	u8 padded_buffer[16];
++	u8 mic[8];
++	/*	uint	offset = 0; */
++	uint	frtype  = GetFrameType(pframe);
++	uint	frsubtype  = get_frame_sub_type(pframe);
++
++	frsubtype = frsubtype >> 4;
++
++
++	_rtw_memset((void *)mic_iv, 0, 16);
++	_rtw_memset((void *)mic_header1, 0, 16);
++	_rtw_memset((void *)mic_header2, 0, 16);
++	_rtw_memset((void *)ctr_preload, 0, 16);
++	_rtw_memset((void *)chain_buffer, 0, 16);
++	_rtw_memset((void *)aes_out, 0, 16);
++	_rtw_memset((void *)padded_buffer, 0, 16);
++
++	if ((hdrlen == WLAN_HDR_A3_LEN) || (hdrlen ==  WLAN_HDR_A3_QOS_LEN))
++		a4_exists = 0;
++	else
++		a4_exists = 1;
++
++	if (
++		((frtype | frsubtype) == WIFI_DATA_CFACK) ||
++		((frtype | frsubtype) == WIFI_DATA_CFPOLL) ||
++		((frtype | frsubtype) == WIFI_DATA_CFACKPOLL)) {
++		qc_exists = 1;
++		if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)
++			hdrlen += 2;
++	}
++	/* add for CONFIG_IEEE80211W, none 11w also can use */
++	else if ((frtype == WIFI_DATA) &&
++		 ((frsubtype == 0x08) ||
++		  (frsubtype == 0x09) ||
++		  (frsubtype == 0x0a) ||
++		  (frsubtype == 0x0b))) {
++		if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)
++			hdrlen += 2;
++		qc_exists = 1;
++	} else
++		qc_exists = 0;
++
++	pn_vector[0] = pframe[hdrlen];
++	pn_vector[1] = pframe[hdrlen + 1];
++	pn_vector[2] = pframe[hdrlen + 4];
++	pn_vector[3] = pframe[hdrlen + 5];
++	pn_vector[4] = pframe[hdrlen + 6];
++	pn_vector[5] = pframe[hdrlen + 7];
++
++	construct_mic_iv(
++		mic_iv,
++		qc_exists,
++		a4_exists,
++		pframe,	 /* message, */
++		plen,
++		pn_vector,
++		frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
++	);
++
++	construct_mic_header1(
++		mic_header1,
++		hdrlen,
++		pframe,	/* message */
++		frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
++	);
++	construct_mic_header2(
++		mic_header2,
++		pframe,	/* message, */
++		a4_exists,
++		qc_exists
++	);
++
++
++	payload_remainder = plen % 16;
++	num_blocks = plen / 16;
++
++	/* Find start of payload */
++	payload_index = (hdrlen + 8);
++
++	/* Calculate MIC */
++	aes128k128d(key, mic_iv, aes_out);
++	bitwise_xor(aes_out, mic_header1, chain_buffer);
++	aes128k128d(key, chain_buffer, aes_out);
++	bitwise_xor(aes_out, mic_header2, chain_buffer);
++	aes128k128d(key, chain_buffer, aes_out);
++
++	for (i = 0; i < num_blocks; i++) {
++		bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);/* bitwise_xor(aes_out, &message[payload_index], chain_buffer); */
++
++		payload_index += 16;
++		aes128k128d(key, chain_buffer, aes_out);
++	}
++
++	/* Add on the final payload block if it needs padding */
++	if (payload_remainder > 0) {
++		for (j = 0; j < 16; j++)
++			padded_buffer[j] = 0x00;
++		for (j = 0; j < payload_remainder; j++) {
++			padded_buffer[j] = pframe[payload_index++];/* padded_buffer[j] = message[payload_index++]; */
++		}
++		bitwise_xor(aes_out, padded_buffer, chain_buffer);
++		aes128k128d(key, chain_buffer, aes_out);
++
++	}
++
++	for (j = 0 ; j < 8; j++)
++		mic[j] = aes_out[j];
++
++	/* Insert MIC into payload */
++	for (j = 0; j < 8; j++)
++		pframe[payload_index + j] = mic[j];	/* message[payload_index+j] = mic[j]; */
++
++	payload_index = hdrlen + 8;
++	for (i = 0; i < num_blocks; i++) {
++		construct_ctr_preload(
++			ctr_preload,
++			a4_exists,
++			qc_exists,
++			pframe,	/* message, */
++			pn_vector,
++			i + 1,
++			frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
++		aes128k128d(key, ctr_preload, aes_out);
++		bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);/* bitwise_xor(aes_out, &message[payload_index], chain_buffer); */
++		for (j = 0; j < 16; j++)
++			pframe[payload_index++] = chain_buffer[j];/* for (j=0; j<16;j++) message[payload_index++] = chain_buffer[j]; */
++	}
++
++	if (payload_remainder > 0) {        /* If there is a short final block, then pad it,*/
++		/* encrypt it and copy the unpadded part back  */
++		construct_ctr_preload(
++			ctr_preload,
++			a4_exists,
++			qc_exists,
++			pframe,	/* message, */
++			pn_vector,
++			num_blocks + 1,
++			frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
++
++		for (j = 0; j < 16; j++)
++			padded_buffer[j] = 0x00;
++		for (j = 0; j < payload_remainder; j++) {
++			padded_buffer[j] = pframe[payload_index + j]; /* padded_buffer[j] = message[payload_index+j]; */
++		}
++		aes128k128d(key, ctr_preload, aes_out);
++		bitwise_xor(aes_out, padded_buffer, chain_buffer);
++		for (j = 0; j < payload_remainder; j++)
++			pframe[payload_index++] = chain_buffer[j];/* for (j=0; j<payload_remainder;j++) message[payload_index++] = chain_buffer[j]; */
++	}
++
++	/* Encrypt the MIC */
++	construct_ctr_preload(
++		ctr_preload,
++		a4_exists,
++		qc_exists,
++		pframe,	/* message, */
++		pn_vector,
++		0,
++		frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
++
++	for (j = 0; j < 16; j++)
++		padded_buffer[j] = 0x00;
++	for (j = 0; j < 8; j++) {
++		padded_buffer[j] = pframe[j + hdrlen + 8 + plen]; /* padded_buffer[j] = message[j+hdrlen+8+plen]; */
++	}
++
++	aes128k128d(key, ctr_preload, aes_out);
++	bitwise_xor(aes_out, padded_buffer, chain_buffer);
++	for (j = 0; j < 8; j++)
++		pframe[payload_index++] = chain_buffer[j];/* for (j=0; j<8;j++) message[payload_index++] = chain_buffer[j]; */
++	return _SUCCESS;
++}
++#endif /* (NEW_CRYPTO == 0) */
++
++
++#if NEW_CRYPTO
++u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe)
++{
++	/* Intermediate Buffers */
++	struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	sint curfragnum, plen;
++	u32 prwskeylen;
++	u8 *pframe;
++	u8 *prwskey;
++	u8 hw_hdr_offset = 0;
++
++	u32 res = _SUCCESS;
++
++	if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
++		return _FAIL;
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++	hw_hdr_offset = TXDESC_SIZE +
++		(((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);
++#else
++#ifdef CONFIG_TX_EARLY_MODE
++	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
++#else
++	hw_hdr_offset = TXDESC_OFFSET;
++#endif
++#endif
++
++	pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset;
++
++	/* start to encrypt each fragment */
++	if ((pattrib->encrypt == _AES_) ||
++	    (pattrib->encrypt == _CCMP_256_)) {
++
++		if (IS_MCAST(pattrib->ra))
++			prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;
++		else {
++			prwskey = pattrib->dot118021x_UncstKey.skey;
++		}
++
++#ifdef CONFIG_TDLS
++		{
++			/* Swencryption */
++			struct	sta_info		*ptdls_sta;
++			ptdls_sta = rtw_get_stainfo(&padapter->stapriv, &pattrib->dst[0]);
++			if ((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) {
++				RTW_INFO("[%s] for tdls link\n", __FUNCTION__);
++				prwskey = &ptdls_sta->tpk.tk[0];
++			}
++		}
++#endif /* CONFIG_TDLS */
++
++		prwskeylen = (pattrib->encrypt == _CCMP_256_) ? 32 : 16;
++
++		for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {
++
++			if ((curfragnum + 1) == pattrib->nr_frags) {    /* the last fragment */
++				plen = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
++
++				_rtw_ccmp_encrypt(prwskey, prwskeylen, pattrib->hdrlen, pframe, plen);
++			} else {
++				plen = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
++
++				_rtw_ccmp_encrypt(prwskey, prwskeylen, pattrib->hdrlen, pframe, plen);
++				pframe += pxmitpriv->frag_len;
++				pframe = (u8 *)RND4((SIZE_PTR)(pframe));
++
++			}
++		}
++
++		AES_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra);
++
++	}
++
++
++
++	return res;
++}
++#else
++u32	rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe)
++{
++	/* exclude ICV */
++
++
++	/*static*/
++	/*	unsigned char	message[MAX_MSG_SIZE]; */
++
++	/* Intermediate Buffers */
++	sint	curfragnum, length;
++	u32	prwskeylen;
++	u8	*pframe, *prwskey;	/* , *payload,*iv */
++	u8   hw_hdr_offset = 0;
++	/* struct	sta_info		*stainfo=NULL; */
++	struct	pkt_attrib	*pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
++	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
++	struct	xmit_priv		*pxmitpriv = &padapter->xmitpriv;
++
++	/*	uint	offset = 0; */
++	u32 res = _SUCCESS;
++
++	if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
++		return _FAIL;
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++	hw_hdr_offset = TXDESC_SIZE +
++		(((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);
++#else
++#ifdef CONFIG_TX_EARLY_MODE
++	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
++#else
++	hw_hdr_offset = TXDESC_OFFSET;
++#endif
++#endif
++
++	pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset;
++
++	/* 4 start to encrypt each fragment */
++	if ((pattrib->encrypt == _AES_)) {
++		/*
++				if(pattrib->psta)
++				{
++					stainfo = pattrib->psta;
++				}
++				else
++				{
++					RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
++					stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] );
++				}
++		*/
++		/* if (stainfo!=NULL) */
++		{
++			/*
++						if(!(stainfo->state &WIFI_ASOC_STATE))
++						{
++							RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, stainfo->state);
++							return _FAIL;
++						}
++			*/
++
++			if (IS_MCAST(pattrib->ra))
++				prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;
++			else {
++				/* prwskey=&stainfo->dot118021x_UncstKey.skey[0]; */
++				prwskey = pattrib->dot118021x_UncstKey.skey;
++			}
++
++#ifdef CONFIG_TDLS
++			{
++				/* Swencryption */
++				struct	sta_info		*ptdls_sta;
++				ptdls_sta = rtw_get_stainfo(&padapter->stapriv , &pattrib->dst[0]);
++				if ((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) {
++					RTW_INFO("[%s] for tdls link\n", __FUNCTION__);
++					prwskey = &ptdls_sta->tpk.tk[0];
++				}
++			}
++#endif /* CONFIG_TDLS */
++
++			prwskeylen = 16;
++
++			for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {
++
++				if ((curfragnum + 1) == pattrib->nr_frags) {	/* 4 the last fragment */
++					length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
++
++					aes_cipher(prwskey, pattrib->hdrlen, pframe, length);
++				} else {
++					length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ;
++
++					aes_cipher(prwskey, pattrib->hdrlen, pframe, length);
++					pframe += pxmitpriv->frag_len;
++					pframe = (u8 *)RND4((SIZE_PTR)(pframe));
++
++				}
++			}
++
++			AES_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra);
++		}
++		/*
++				else{
++					RTW_INFO("%s, psta==NUL\n", __func__);
++					res=_FAIL;
++				}
++		*/
++	}
++
++
++
++	return res;
++}
++#endif
++
++#if (NEW_CRYPTO == 0)
++static sint aes_decipher(u8 *key, uint	hdrlen,
++			 u8 *pframe, uint plen)
++{
++	static u8	message[MAX_MSG_SIZE];
++	uint	qc_exists, a4_exists, i, j, payload_remainder,
++		num_blocks, payload_index;
++	sint res = _SUCCESS;
++	u8 pn_vector[6];
++	u8 mic_iv[16];
++	u8 mic_header1[16];
++	u8 mic_header2[16];
++	u8 ctr_preload[16];
++
++	/* Intermediate Buffers */
++	u8 chain_buffer[16];
++	u8 aes_out[16];
++	u8 padded_buffer[16];
++	u8 mic[8];
++
++
++	/*	uint	offset = 0; */
++	uint	frtype  = GetFrameType(pframe);
++	uint	frsubtype  = get_frame_sub_type(pframe);
++	frsubtype = frsubtype >> 4;
++
++
++	_rtw_memset((void *)mic_iv, 0, 16);
++	_rtw_memset((void *)mic_header1, 0, 16);
++	_rtw_memset((void *)mic_header2, 0, 16);
++	_rtw_memset((void *)ctr_preload, 0, 16);
++	_rtw_memset((void *)chain_buffer, 0, 16);
++	_rtw_memset((void *)aes_out, 0, 16);
++	_rtw_memset((void *)padded_buffer, 0, 16);
++
++	/* start to decrypt the payload */
++
++	num_blocks = (plen - 8) / 16; /* (plen including LLC, payload_length and mic ) */
++
++	payload_remainder = (plen - 8) % 16;
++
++	pn_vector[0]  = pframe[hdrlen];
++	pn_vector[1]  = pframe[hdrlen + 1];
++	pn_vector[2]  = pframe[hdrlen + 4];
++	pn_vector[3]  = pframe[hdrlen + 5];
++	pn_vector[4]  = pframe[hdrlen + 6];
++	pn_vector[5]  = pframe[hdrlen + 7];
++
++	if ((hdrlen == WLAN_HDR_A3_LEN) || (hdrlen ==  WLAN_HDR_A3_QOS_LEN))
++		a4_exists = 0;
++	else
++		a4_exists = 1;
++
++	if (
++		((frtype | frsubtype) == WIFI_DATA_CFACK) ||
++		((frtype | frsubtype) == WIFI_DATA_CFPOLL) ||
++		((frtype | frsubtype) == WIFI_DATA_CFACKPOLL)) {
++		qc_exists = 1;
++		if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)
++			hdrlen += 2;
++	} /* only for data packet . add for CONFIG_IEEE80211W, none 11w also can use */
++	else if ((frtype == WIFI_DATA) &&
++		 ((frsubtype == 0x08) ||
++		  (frsubtype == 0x09) ||
++		  (frsubtype == 0x0a) ||
++		  (frsubtype == 0x0b))) {
++		if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)
++			hdrlen += 2;
++		qc_exists = 1;
++	} else
++		qc_exists = 0;
++
++
++	/* now, decrypt pframe with hdrlen offset and plen long */
++
++	payload_index = hdrlen + 8; /* 8 is for extiv */
++
++	for (i = 0; i < num_blocks; i++) {
++		construct_ctr_preload(
++			ctr_preload,
++			a4_exists,
++			qc_exists,
++			pframe,
++			pn_vector,
++			i + 1,
++			frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
++		);
++
++		aes128k128d(key, ctr_preload, aes_out);
++		bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);
++
++		for (j = 0; j < 16; j++)
++			pframe[payload_index++] = chain_buffer[j];
++	}
++
++	if (payload_remainder > 0) {        /* If there is a short final block, then pad it,*/
++		/* encrypt it and copy the unpadded part back  */
++		construct_ctr_preload(
++			ctr_preload,
++			a4_exists,
++			qc_exists,
++			pframe,
++			pn_vector,
++			num_blocks + 1,
++			frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
++		);
++
++		for (j = 0; j < 16; j++)
++			padded_buffer[j] = 0x00;
++		for (j = 0; j < payload_remainder; j++)
++			padded_buffer[j] = pframe[payload_index + j];
++		aes128k128d(key, ctr_preload, aes_out);
++		bitwise_xor(aes_out, padded_buffer, chain_buffer);
++		for (j = 0; j < payload_remainder; j++)
++			pframe[payload_index++] = chain_buffer[j];
++	}
++
++	/* start to calculate the mic	 */
++	if ((hdrlen + plen + 8) <= MAX_MSG_SIZE)
++		_rtw_memcpy((void *)message, pframe, (hdrlen + plen + 8)); /* 8 is for ext iv len */
++
++
++	pn_vector[0] = pframe[hdrlen];
++	pn_vector[1] = pframe[hdrlen + 1];
++	pn_vector[2] = pframe[hdrlen + 4];
++	pn_vector[3] = pframe[hdrlen + 5];
++	pn_vector[4] = pframe[hdrlen + 6];
++	pn_vector[5] = pframe[hdrlen + 7];
++
++
++
++	construct_mic_iv(
++		mic_iv,
++		qc_exists,
++		a4_exists,
++		message,
++		plen - 8,
++		pn_vector,
++		frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
++	);
++
++	construct_mic_header1(
++		mic_header1,
++		hdrlen,
++		message,
++		frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
++	);
++	construct_mic_header2(
++		mic_header2,
++		message,
++		a4_exists,
++		qc_exists
++	);
++
++
++	payload_remainder = (plen - 8) % 16;
++	num_blocks = (plen - 8) / 16;
++
++	/* Find start of payload */
++	payload_index = (hdrlen + 8);
++
++	/* Calculate MIC */
++	aes128k128d(key, mic_iv, aes_out);
++	bitwise_xor(aes_out, mic_header1, chain_buffer);
++	aes128k128d(key, chain_buffer, aes_out);
++	bitwise_xor(aes_out, mic_header2, chain_buffer);
++	aes128k128d(key, chain_buffer, aes_out);
++
++	for (i = 0; i < num_blocks; i++) {
++		bitwise_xor(aes_out, &message[payload_index], chain_buffer);
++
++		payload_index += 16;
++		aes128k128d(key, chain_buffer, aes_out);
++	}
++
++	/* Add on the final payload block if it needs padding */
++	if (payload_remainder > 0) {
++		for (j = 0; j < 16; j++)
++			padded_buffer[j] = 0x00;
++		for (j = 0; j < payload_remainder; j++)
++			padded_buffer[j] = message[payload_index++];
++		bitwise_xor(aes_out, padded_buffer, chain_buffer);
++		aes128k128d(key, chain_buffer, aes_out);
++
++	}
++
++	for (j = 0 ; j < 8; j++)
++		mic[j] = aes_out[j];
++
++	/* Insert MIC into payload */
++	for (j = 0; j < 8; j++)
++		message[payload_index + j] = mic[j];
++
++	payload_index = hdrlen + 8;
++	for (i = 0; i < num_blocks; i++) {
++		construct_ctr_preload(
++			ctr_preload,
++			a4_exists,
++			qc_exists,
++			message,
++			pn_vector,
++			i + 1,
++			frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
++		aes128k128d(key, ctr_preload, aes_out);
++		bitwise_xor(aes_out, &message[payload_index], chain_buffer);
++		for (j = 0; j < 16; j++)
++			message[payload_index++] = chain_buffer[j];
++	}
++
++	if (payload_remainder > 0) {        /* If there is a short final block, then pad it,*/
++		/* encrypt it and copy the unpadded part back  */
++		construct_ctr_preload(
++			ctr_preload,
++			a4_exists,
++			qc_exists,
++			message,
++			pn_vector,
++			num_blocks + 1,
++			frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
++
++		for (j = 0; j < 16; j++)
++			padded_buffer[j] = 0x00;
++		for (j = 0; j < payload_remainder; j++)
++			padded_buffer[j] = message[payload_index + j];
++		aes128k128d(key, ctr_preload, aes_out);
++		bitwise_xor(aes_out, padded_buffer, chain_buffer);
++		for (j = 0; j < payload_remainder; j++)
++			message[payload_index++] = chain_buffer[j];
++	}
++
++	/* Encrypt the MIC */
++	construct_ctr_preload(
++		ctr_preload,
++		a4_exists,
++		qc_exists,
++		message,
++		pn_vector,
++		0,
++		frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
++
++	for (j = 0; j < 16; j++)
++		padded_buffer[j] = 0x00;
++	for (j = 0; j < 8; j++)
++		padded_buffer[j] = message[j + hdrlen + 8 + plen - 8];
++
++	aes128k128d(key, ctr_preload, aes_out);
++	bitwise_xor(aes_out, padded_buffer, chain_buffer);
++	for (j = 0; j < 8; j++)
++		message[payload_index++] = chain_buffer[j];
++
++	/* compare the mic */
++	for (i = 0; i < 8; i++) {
++		if (pframe[hdrlen + 8 + plen - 8 + i] != message[hdrlen + 8 + plen - 8 + i]) {
++			RTW_INFO("aes_decipher:mic check error mic[%d]: pframe(%x) != message(%x)\n",
++				i, pframe[hdrlen + 8 + plen - 8 + i], message[hdrlen + 8 + plen - 8 + i]);
++			res = _FAIL;
++		}
++	}
++	return res;
++}
++#endif /* (NEW_CRYPTO == 0) */
++
++#if NEW_CRYPTO
++u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe)
++{
++	struct sta_info *stainfo;
++	struct rx_pkt_attrib *prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	u8 *pframe;
++	u8 *prwskey;
++	u32 res = _SUCCESS;
++
++	pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;
++	/* start to encrypt each fragment */
++	if ((prxattrib->encrypt == _AES_) ||
++	    (prxattrib->encrypt == _CCMP_256_)) {
++
++		stainfo = rtw_get_stainfo(&padapter->stapriv, &prxattrib->ta[0]);
++		if (stainfo != NULL) {
++
++			if (IS_MCAST(prxattrib->ra)) {
++				static systime start = 0;
++				static u32 no_gkey_bc_cnt = 0;
++				static u32 no_gkey_mc_cnt = 0;
++
++				if ((!MLME_IS_MESH(padapter) && psecuritypriv->binstallGrpkey == _FALSE)
++					#ifdef CONFIG_RTW_MESH
++					|| !(stainfo->gtk_bmp | BIT(prxattrib->key_index))
++					#endif
++				) {
++					res = _FAIL;
++
++					if (start == 0)
++						start = rtw_get_current_time();
++
++					if (is_broadcast_mac_addr(prxattrib->ra))
++						no_gkey_bc_cnt++;
++					else
++						no_gkey_mc_cnt++;
++
++					if (rtw_get_passing_time_ms(start) > 1000) {
++						if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
++							RTW_PRINT(FUNC_ADPT_FMT" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
++								FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
++						}
++						start = rtw_get_current_time();
++						no_gkey_bc_cnt = 0;
++						no_gkey_mc_cnt = 0;
++					}
++
++					goto exit;
++				}
++
++				if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
++					RTW_PRINT(FUNC_ADPT_FMT" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
++						FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
++				}
++				start = 0;
++				no_gkey_bc_cnt = 0;
++				no_gkey_mc_cnt = 0;
++
++				#ifdef CONFIG_RTW_MESH
++				if (MLME_IS_MESH(padapter)) {
++					/* TODO: multiple GK? */
++					prwskey = &stainfo->gtk.skey[0];
++				} else
++				#endif
++				{
++					prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey;
++					if (psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) {
++						RTW_DBG("not match packet_index=%d, install_index=%d\n"
++							, prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid);
++						res = _FAIL;
++						goto exit;
++					}
++				}
++			} else
++				prwskey = &stainfo->dot118021x_UncstKey.skey[0];
++
++			res = _rtw_ccmp_decrypt(prwskey,
++				prxattrib->encrypt == _CCMP_256_ ? 32 : 16,
++				prxattrib->hdrlen, pframe,
++				((union recv_frame *)precvframe)->u.hdr.len);
++
++			AES_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);
++		} else {
++			res = _FAIL;
++		}
++
++	}
++exit:
++	return res;
++}
++#else
++u32	rtw_aes_decrypt(_adapter *padapter, u8 *precvframe)
++{
++	/* exclude ICV */
++
++
++	/*static*/
++	/*	unsigned char	message[MAX_MSG_SIZE]; */
++
++
++	/* Intermediate Buffers */
++
++
++	sint		length;
++	u8	*pframe, *prwskey;	/* , *payload,*iv */
++	struct	sta_info		*stainfo;
++	struct	rx_pkt_attrib	*prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;
++	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
++	/*	struct	recv_priv		*precvpriv=&padapter->recvpriv; */
++	u32	res = _SUCCESS;
++	pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;
++	/* 4 start to encrypt each fragment */
++	if ((prxattrib->encrypt == _AES_)) {
++
++		stainfo = rtw_get_stainfo(&padapter->stapriv , &prxattrib->ta[0]);
++		if (stainfo != NULL) {
++
++			if (IS_MCAST(prxattrib->ra)) {
++				static systime start = 0;
++				static u32 no_gkey_bc_cnt = 0;
++				static u32 no_gkey_mc_cnt = 0;
++
++				/* RTW_INFO("rx bc/mc packets, to perform sw rtw_aes_decrypt\n"); */
++				/* prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; */
++				if ((!MLME_IS_MESH(padapter) && psecuritypriv->binstallGrpkey == _FALSE)
++					#ifdef CONFIG_RTW_MESH
++					|| !(stainfo->gtk_bmp | BIT(prxattrib->key_index))
++					#endif
++				) {
++					res = _FAIL;
++
++					if (start == 0)
++						start = rtw_get_current_time();
++
++					if (is_broadcast_mac_addr(prxattrib->ra))
++						no_gkey_bc_cnt++;
++					else
++						no_gkey_mc_cnt++;
++
++					if (rtw_get_passing_time_ms(start) > 1000) {
++						if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
++							RTW_PRINT(FUNC_ADPT_FMT" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
++								FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
++						}
++						start = rtw_get_current_time();
++						no_gkey_bc_cnt = 0;
++						no_gkey_mc_cnt = 0;
++					}
++
++					goto exit;
++				}
++
++				if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
++					RTW_PRINT(FUNC_ADPT_FMT" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
++						FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
++				}
++				start = 0;
++				no_gkey_bc_cnt = 0;
++				no_gkey_mc_cnt = 0;
++
++				#ifdef CONFIG_RTW_MESH
++				if (MLME_IS_MESH(padapter)) {
++					/* TODO: multiple GK? */
++					prwskey = &stainfo->gtk.skey[0];
++				} else
++				#endif
++				{
++					prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey;
++					if (psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) {
++						RTW_DBG("not match packet_index=%d, install_index=%d\n"
++							, prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid);
++						res = _FAIL;
++						goto exit;
++					}
++				}
++			} else
++				prwskey = &stainfo->dot118021x_UncstKey.skey[0];
++
++			length = ((union recv_frame *)precvframe)->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len;
++#if 0
++			/*  add for CONFIG_IEEE80211W, debug */
++			if (0)
++				printk("@@@@@@@@@@@@@@@@@@ length=%d, prxattrib->hdrlen=%d, prxattrib->pkt_len=%d\n"
++				       , length, prxattrib->hdrlen, prxattrib->pkt_len);
++			if (0) {
++				int no;
++				/* test print PSK */
++				printk("PSK key below:\n");
++				for (no = 0; no < 16; no++)
++					printk(" %02x ", prwskey[no]);
++				printk("\n");
++			}
++			if (0) {
++				int no;
++				/* test print PSK */
++				printk("frame:\n");
++				for (no = 0; no < prxattrib->pkt_len; no++)
++					printk(" %02x ", pframe[no]);
++				printk("\n");
++			}
++#endif
++
++			res = aes_decipher(prwskey, prxattrib->hdrlen, pframe, length);
++
++			AES_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);
++		} else {
++			res = _FAIL;
++		}
++
++	}
++exit:
++	return res;
++}
++#endif
++
++#ifdef CONFIG_RTW_MESH_AEK
++/* for AES-SIV, wrapper to ase_siv_encrypt and aes_siv_decrypt */
++int rtw_aes_siv_encrypt(const u8 *key, size_t key_len, const u8 *pw,
++	size_t pwlen, size_t num_elem,
++	const u8 *addr[], const size_t *len, u8 *out)
++{
++	return _aes_siv_encrypt(key, key_len, pw, pwlen,
++		num_elem, addr, len, out);
++}
++
++int rtw_aes_siv_decrypt(const u8 *key, size_t key_len, const u8 *iv_crypt, size_t iv_c_len,
++	size_t num_elem, const u8 *addr[], const size_t *len, u8 *out)
++{
++	return _aes_siv_decrypt(key, key_len, iv_crypt,
++		iv_c_len, num_elem, addr, len, out);
++}
++#endif /* CONFIG_RTW_MESH_AEK */
++
++#ifdef CONFIG_TDLS
++void wpa_tdls_generate_tpk(_adapter *padapter, void *sta)
++{
++	struct sta_info *psta = (struct sta_info *)sta;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++	_tdls_generate_tpk(psta, adapter_mac_addr(padapter), get_bssid(pmlmepriv));
++}
++
++/**
++ * wpa_tdls_ftie_mic - Calculate TDLS FTIE MIC
++ * @kck: TPK-KCK
++ * @lnkid: Pointer to the beginning of Link Identifier IE
++ * @rsnie: Pointer to the beginning of RSN IE used for handshake
++ * @timeoutie: Pointer to the beginning of Timeout IE used for handshake
++ * @ftie: Pointer to the beginning of FT IE
++ * @mic: Pointer for writing MIC
++ *
++ * Calculate MIC for TDLS frame.
++ */
++int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq,
++		      u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie,
++		      u8 *mic)
++{
++	u8 *buf, *pos;
++	struct wpa_tdls_ftie *_ftie;
++	struct wpa_tdls_lnkid *_lnkid;
++	int ret;
++	int len = 2 * ETH_ALEN + 1 + 2 + lnkid[1] + 2 + rsnie[1] +
++		  2 + timeoutie[1] + 2 + ftie[1];
++	buf = rtw_zmalloc(len);
++	if (!buf) {
++		RTW_INFO("TDLS: No memory for MIC calculation\n");
++		return -1;
++	}
++
++	pos = buf;
++	_lnkid = (struct wpa_tdls_lnkid *) lnkid;
++	/* 1) TDLS initiator STA MAC address */
++	_rtw_memcpy(pos, _lnkid->init_sta, ETH_ALEN);
++	pos += ETH_ALEN;
++	/* 2) TDLS responder STA MAC address */
++	_rtw_memcpy(pos, _lnkid->resp_sta, ETH_ALEN);
++	pos += ETH_ALEN;
++	/* 3) Transaction Sequence number */
++	*pos++ = trans_seq;
++	/* 4) Link Identifier IE */
++	_rtw_memcpy(pos, lnkid, 2 + lnkid[1]);
++	pos += 2 + lnkid[1];
++	/* 5) RSN IE */
++	_rtw_memcpy(pos, rsnie, 2 + rsnie[1]);
++	pos += 2 + rsnie[1];
++	/* 6) Timeout Interval IE */
++	_rtw_memcpy(pos, timeoutie, 2 + timeoutie[1]);
++	pos += 2 + timeoutie[1];
++	/* 7) FTIE, with the MIC field of the FTIE set to 0 */
++	_rtw_memcpy(pos, ftie, 2 + ftie[1]);
++	_ftie = (struct wpa_tdls_ftie *) pos;
++	_rtw_memset(_ftie->mic, 0, TDLS_MIC_LEN);
++	pos += 2 + ftie[1];
++
++	/* ret = omac1_aes_128(kck, buf, pos - buf, mic); */
++	ret = _bip_ccmp_protect(kck, 16, buf, pos - buf, mic);
++	rtw_mfree(buf, len);
++	return ret;
++
++}
++
++/**
++ * wpa_tdls_teardown_ftie_mic - Calculate TDLS TEARDOWN FTIE MIC
++ * @kck: TPK-KCK
++ * @lnkid: Pointer to the beginning of Link Identifier IE
++ * @reason: Reason code of TDLS Teardown
++ * @dialog_token: Dialog token that was used in the MIC calculation for TPK Handshake Message 3
++ * @trans_seq: Transaction Sequence number (1 octet) which shall be set to the value 4
++ * @ftie: Pointer to the beginning of FT IE
++ * @mic: Pointer for writing MIC
++ *
++ * Calculate MIC for TDLS TEARDOWN frame according to Section 10.22.5 in IEEE 802.11 - 2012.
++ */
++int wpa_tdls_teardown_ftie_mic(u8 *kck, u8 *lnkid, u16 reason,
++			       u8 dialog_token, u8 trans_seq, u8 *ftie, u8 *mic)
++{
++	u8 *buf, *pos;
++	struct wpa_tdls_ftie *_ftie;
++	int ret;
++	int len = 2 + lnkid[1] + 2 + 1 + 1 + 2 + ftie[1];
++
++	buf = rtw_zmalloc(len);
++	if (!buf) {
++		RTW_INFO("TDLS: No memory for MIC calculation\n");
++		return -1;
++	}
++
++	pos = buf;
++	/* 1) Link Identifier IE */
++	_rtw_memcpy(pos, lnkid, 2 + lnkid[1]);
++	pos += 2 + lnkid[1];
++	/* 2) Reason Code */
++	_rtw_memcpy(pos, (u8 *)&reason, 2);
++	pos += 2;
++	/* 3) Dialog Token */
++	*pos++ = dialog_token;
++	/* 4) Transaction Sequence number */
++	*pos++ = trans_seq;
++	/* 5) FTIE, with the MIC field of the FTIE set to 0 */
++	_rtw_memcpy(pos, ftie, 2 + ftie[1]);
++	_ftie = (struct wpa_tdls_ftie *) pos;
++	_rtw_memset(_ftie->mic, 0, TDLS_MIC_LEN);
++	pos += 2 + ftie[1];
++
++	/* ret = omac1_aes_128(kck, buf, pos - buf, mic); */
++	ret = _bip_ccmp_protect(kck, 16, buf, pos - buf, mic);
++	rtw_mfree(buf, len);
++	return ret;
++
++}
++
++int tdls_verify_mic(u8 *kck, u8 trans_seq,
++		    u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie)
++{
++	u8 *buf, *pos;
++	int len;
++	u8 mic[16];
++	int ret;
++	u8 *rx_ftie, *tmp_ftie;
++
++	if (lnkid == NULL || rsnie == NULL ||
++	    timeoutie == NULL || ftie == NULL)
++		return _FAIL;
++
++	len = 2 * ETH_ALEN + 1 + 2 + 18 + 2 + *(rsnie + 1) + 2 + *(timeoutie + 1) + 2 + *(ftie + 1);
++
++	buf = rtw_zmalloc(len);
++	if (buf == NULL)
++		return _FAIL;
++
++	pos = buf;
++	/* 1) TDLS initiator STA MAC address */
++	_rtw_memcpy(pos, lnkid + ETH_ALEN + 2, ETH_ALEN);
++	pos += ETH_ALEN;
++	/* 2) TDLS responder STA MAC address */
++	_rtw_memcpy(pos, lnkid + 2 * ETH_ALEN + 2, ETH_ALEN);
++	pos += ETH_ALEN;
++	/* 3) Transaction Sequence number */
++	*pos++ = trans_seq;
++	/* 4) Link Identifier IE */
++	_rtw_memcpy(pos, lnkid, 2 + 18);
++	pos += 2 + 18;
++	/* 5) RSN IE */
++	_rtw_memcpy(pos, rsnie, 2 + *(rsnie + 1));
++	pos += 2 + *(rsnie + 1);
++	/* 6) Timeout Interval IE */
++	_rtw_memcpy(pos, timeoutie, 2 + *(timeoutie + 1));
++	pos += 2 + *(timeoutie + 1);
++	/* 7) FTIE, with the MIC field of the FTIE set to 0 */
++	_rtw_memcpy(pos, ftie, 2 + *(ftie + 1));
++	pos += 2;
++	tmp_ftie = (u8 *)(pos + 2);
++	_rtw_memset(tmp_ftie, 0, 16);
++	pos += *(ftie + 1);
++
++	/* ret = omac1_aes_128(kck, buf, pos - buf, mic); */
++	ret = _bip_ccmp_protect(kck, 16, buf, pos - buf, mic);
++	rtw_mfree(buf, len);
++	if (ret == _FAIL)
++		return _FAIL;
++	rx_ftie = ftie + 4;
++
++	if (_rtw_memcmp2(mic, rx_ftie, 16) == 0) {
++		/* Valid MIC */
++		return _SUCCESS;
++	}
++
++	/* Invalid MIC */
++	RTW_INFO("[%s] Invalid MIC\n", __FUNCTION__);
++	return _FAIL;
++
++}
++#endif /* CONFIG_TDLS */
++
++/* Restore HW wep key setting according to key_mask */
++void rtw_sec_restore_wep_key(_adapter *adapter)
++{
++	struct security_priv *securitypriv = &(adapter->securitypriv);
++	sint keyid;
++
++	if ((_WEP40_ == securitypriv->dot11PrivacyAlgrthm) || (_WEP104_ == securitypriv->dot11PrivacyAlgrthm)) {
++		for (keyid = 0; keyid < 4; keyid++) {
++			if (securitypriv->key_mask & BIT(keyid)) {
++				if (keyid == securitypriv->dot11PrivacyKeyIndex)
++					rtw_set_key(adapter, securitypriv, keyid, 1, _FALSE);
++				else
++					rtw_set_key(adapter, securitypriv, keyid, 0, _FALSE);
++			}
++		}
++	}
++}
++
++u8 rtw_handle_tkip_countermeasure(_adapter *adapter, const char *caller)
++{
++	struct security_priv *securitypriv = &(adapter->securitypriv);
++	u8 status = _SUCCESS;
++
++	if (securitypriv->btkip_countermeasure == _TRUE) {
++		u32 passing_ms = rtw_get_passing_time_ms(securitypriv->btkip_countermeasure_time);
++		if (passing_ms > 60 * 1000) {
++			RTW_PRINT("%s("ADPT_FMT") countermeasure time:%ds > 60s\n",
++				  caller, ADPT_ARG(adapter), passing_ms / 1000);
++			securitypriv->btkip_countermeasure = _FALSE;
++			securitypriv->btkip_countermeasure_time = 0;
++		} else {
++			RTW_PRINT("%s("ADPT_FMT") countermeasure time:%ds < 60s\n",
++				  caller, ADPT_ARG(adapter), passing_ms / 1000);
++			status = _FAIL;
++		}
++	}
++
++	return status;
++}
++
++#ifdef CONFIG_WOWLAN
++u16 rtw_cal_crc16(u8 data, u16 crc)
++{
++	u8 shift_in, data_bit;
++	u8 crc_bit4, crc_bit11, crc_bit15;
++	u16 crc_result;
++	int index;
++
++	for (index = 0; index < 8; index++) {
++		crc_bit15 = ((crc & BIT15) ? 1 : 0);
++		data_bit = (data & (BIT0 << index) ? 1 : 0);
++		shift_in = crc_bit15 ^ data_bit;
++		/*printf("crc_bit15=%d, DataBit=%d, shift_in=%d\n",
++		 * crc_bit15, data_bit, shift_in);*/
++
++		crc_result = crc << 1;
++
++		if (shift_in == 0)
++			crc_result &= (~BIT0);
++		else
++			crc_result |= BIT0;
++		/*printf("CRC =%x\n",CRC_Result);*/
++
++		crc_bit11 = ((crc & BIT11) ? 1 : 0) ^ shift_in;
++
++		if (crc_bit11 == 0)
++			crc_result &= (~BIT12);
++		else
++			crc_result |= BIT12;
++
++		/*printf("bit12 CRC =%x\n",CRC_Result);*/
++
++		crc_bit4 = ((crc & BIT4) ? 1 : 0) ^ shift_in;
++
++		if (crc_bit4 == 0)
++			crc_result &= (~BIT5);
++		else
++			crc_result |= BIT5;
++
++		/* printf("bit5 CRC =%x\n",CRC_Result); */
++		/* repeat using the last result*/
++		crc = crc_result;
++	}
++	return crc;
++}
++
++/*
++ * function name :rtw_calc_crc
++ *
++ * input: char* pattern , pattern size
++ *
++ */
++u16 rtw_calc_crc(u8  *pdata, int length)
++{
++	u16 crc = 0xffff;
++	int i;
++
++	for (i = 0; i < length; i++)
++		crc = rtw_cal_crc16(pdata[i], crc);
++	/* get 1' complement */
++	crc = ~crc;
++
++	return crc;
++}
++#endif /*CONFIG_WOWLAN*/
++
++u32 rtw_calc_crc32(u8 *data, size_t len)
++{
++	size_t i;
++	u32 crc = 0xFFFFFFFF;
++
++	if (bcrc32initialized == 0)
++		crc32_init();
++
++	for (i = 0; i < len; i++)
++		crc = crc32_table[(crc ^ data[i]) & 0xff] ^ (crc >> 8);
++
++	/* return 1' complement */
++	return ~crc;
++}
++
++
++/**
++ * rtw_gcmp_encrypt - 
++ * @padapter:
++ * @pxmitframe:
++ *
++ */
++u32 rtw_gcmp_encrypt(_adapter *padapter, u8 *pxmitframe)
++{
++	struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	/* Intermediate Buffers */
++	sint curfragnum, plen;
++	u32 prwskeylen;
++	u8 *pframe = NULL;
++	u8 *prwskey = NULL;
++	u8 hw_hdr_offset = 0;
++	u32 res = _SUCCESS;
++
++	if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
++		return _FAIL;
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++	hw_hdr_offset = TXDESC_SIZE +
++		(((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);
++#else
++#ifdef CONFIG_TX_EARLY_MODE
++	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
++#else
++	hw_hdr_offset = TXDESC_OFFSET;
++#endif
++#endif
++
++	pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset;
++
++	/* start to encrypt each fragment */
++	if ((pattrib->encrypt == _GCMP_) ||
++		(pattrib->encrypt == _GCMP_256_)) {
++
++		if (IS_MCAST(pattrib->ra))
++			prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;
++		else
++			prwskey = pattrib->dot118021x_UncstKey.skey;
++
++		prwskeylen = (pattrib->encrypt == _GCMP_256_) ? 32 : 16;
++
++		for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {
++			if ((curfragnum + 1) == pattrib->nr_frags) {
++				/* the last fragment */
++				plen = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
++
++				_rtw_gcmp_encrypt(prwskey, prwskeylen, pattrib->hdrlen, pframe, plen);
++			} else {
++				plen = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
++
++				_rtw_gcmp_encrypt(prwskey, prwskeylen, pattrib->hdrlen, pframe, plen);
++				pframe += pxmitpriv->frag_len;
++				pframe = (u8 *)RND4((SIZE_PTR)(pframe));
++			}
++		}
++
++		GCMP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra);
++	}
++
++	return res;
++}
++
++u32 rtw_gcmp_decrypt(_adapter *padapter, u8 *precvframe)
++{
++	u32 prwskeylen;
++	u8 * pframe,*prwskey;
++	struct sta_info *stainfo;
++	struct rx_pkt_attrib *prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	u32 res = _SUCCESS;
++	pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;
++
++	if ((prxattrib->encrypt == _GCMP_) ||
++		(prxattrib->encrypt == _GCMP_256_)) {
++		stainfo = rtw_get_stainfo(&padapter->stapriv, &prxattrib->ta[0]);
++		if (stainfo != NULL) {
++			if (IS_MCAST(prxattrib->ra)) {
++				static systime start = 0;
++				static u32 no_gkey_bc_cnt = 0;
++				static u32 no_gkey_mc_cnt = 0;
++
++				if ((!MLME_IS_MESH(padapter) && psecuritypriv->binstallGrpkey == _FALSE)
++					#ifdef CONFIG_RTW_MESH
++					|| !(stainfo->gtk_bmp | BIT(prxattrib->key_index))
++					#endif
++				) {
++					res = _FAIL;
++
++					if (start == 0)
++						start = rtw_get_current_time();
++
++					if (is_broadcast_mac_addr(prxattrib->ra))
++						no_gkey_bc_cnt++;
++					else
++						no_gkey_mc_cnt++;
++
++					if (rtw_get_passing_time_ms(start) > 1000) {
++						if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
++							RTW_PRINT(FUNC_ADPT_FMT" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
++								FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
++						}
++						start = rtw_get_current_time();
++						no_gkey_bc_cnt = 0;
++						no_gkey_mc_cnt = 0;
++					}
++
++					goto exit;
++				}
++
++				if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
++					RTW_PRINT(FUNC_ADPT_FMT" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
++						FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
++				}
++				start = 0;
++				no_gkey_bc_cnt = 0;
++				no_gkey_mc_cnt = 0;
++
++				#ifdef CONFIG_RTW_MESH
++				if (MLME_IS_MESH(padapter)) {
++					/* TODO: multiple GK? */
++					prwskey = &stainfo->gtk.skey[0];
++				} else
++				#endif
++				{
++					prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey;
++					if (psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) {
++						RTW_DBG("not match packet_index=%d, install_index=%d\n"
++							, prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid);
++						res = _FAIL;
++						goto exit;
++					}
++				}
++			} else
++				prwskey = &stainfo->dot118021x_UncstKey.skey[0];
++
++			res = _rtw_gcmp_decrypt(prwskey,
++				prxattrib->encrypt == _GCMP_256_ ? 32 : 16,
++				prxattrib->hdrlen, pframe,
++				((union recv_frame *)precvframe)->u.hdr.len);
++
++			GCMP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);
++		} else {
++			res = _FAIL;
++		}
++
++	}
++exit:
++	return res;
++}
++
++
++#ifdef CONFIG_IEEE80211W
++u8 rtw_calculate_bip_mic(enum security_type gmcs, u8 *whdr_pos, s32 len,
++	const u8 *key, const u8 *data, size_t data_len, u8 *mic)
++{
++	u8 res = _SUCCESS;
++
++	if (gmcs == _BIP_CMAC_128_) {
++		if (_bip_ccmp_protect(key, 16, data, data_len, mic) == _FALSE) {
++			res = _FAIL;
++			RTW_ERR("%s : _bip_ccmp_protect(128) fail!", __func__);
++		}
++	} else if (gmcs == _BIP_CMAC_256_) {
++		if (_bip_ccmp_protect(key, 32, data, data_len, mic) == _FALSE) {
++			res = _FAIL;
++			RTW_ERR("%s : _bip_ccmp_protect(256) fail!", __func__);
++		}
++	} else if (gmcs == _BIP_GMAC_128_) {
++		if (_bip_gcmp_protect(whdr_pos, len, key, 16,
++				data, data_len, mic) == _FALSE) {
++			res = _FAIL;
++			RTW_ERR("%s : _bip_gcmp_protect(128) fail!", __func__);
++		}
++	} else if (gmcs == _BIP_GMAC_256_) {
++		if (_bip_gcmp_protect(whdr_pos, len, key, 32,
++				data, data_len, mic) == _FALSE) {
++			res = _FAIL;
++			RTW_ERR("%s : _bip_gcmp_protect(256) fail!", __func__);
++		}
++	} else {
++		res = _FAIL;
++		RTW_ERR("%s : unsupport dot11wCipher !\n", __func__);
++	}
++
++	return res;
++}
++
++
++u32 rtw_bip_verify(enum security_type gmcs, u16 pkt_len,
++	u8 *whdr_pos, sint flen, const u8 *key, u16 keyid, u64 *ipn)
++{
++	u8 * BIP_AAD,*mme;
++	u32 res = _FAIL;
++	uint len, ori_len;
++	u16 pkt_keyid = 0;
++	u64 pkt_ipn = 0;
++	struct rtw_ieee80211_hdr *pwlanhdr;
++	u8 mic[16];
++	u8 mic_len, mme_offset;
++
++	mic_len = (gmcs == _BIP_CMAC_128_) ? 8 : 16;
++
++	if (flen < WLAN_HDR_A3_LEN || flen - WLAN_HDR_A3_LEN < mic_len)
++		return RTW_RX_HANDLED;
++
++	mme_offset = (mic_len == 8) ? 18 : 26;
++	mme = whdr_pos + flen - mme_offset;
++	if (*mme != _MME_IE_)
++		return RTW_RX_HANDLED;
++
++	/* copy key index */
++	_rtw_memcpy(&pkt_keyid, mme + 2, 2);
++	pkt_keyid = le16_to_cpu(pkt_keyid);
++	if (pkt_keyid != keyid) {
++		RTW_INFO("BIP key index error!\n");
++		return _FAIL;
++	}
++
++	/* save packet number */
++	_rtw_memcpy(&pkt_ipn, mme + 4, 6);
++	pkt_ipn = le64_to_cpu(pkt_ipn);
++	/* BIP packet number should bigger than previous BIP packet */
++	if (pkt_ipn <= *ipn) { /* wrap around? */
++		RTW_INFO("replay BIP packet\n");
++		return _FAIL;
++	}
++
++	ori_len = flen - WLAN_HDR_A3_LEN + BIP_AAD_SIZE;
++	BIP_AAD = rtw_zmalloc(ori_len);
++	if (BIP_AAD == NULL) {
++		RTW_INFO("BIP AAD allocate fail\n");
++		return _FAIL;
++	}
++
++	/* mapping to wlan header */
++	pwlanhdr = (struct rtw_ieee80211_hdr *)whdr_pos;
++
++	/* save the frame body + MME (w/o mic) */
++	_rtw_memcpy(BIP_AAD + BIP_AAD_SIZE,
++		whdr_pos + WLAN_HDR_A3_LEN,
++		flen - WLAN_HDR_A3_LEN - mic_len);
++
++	/* conscruct AAD, copy frame control field */
++	_rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2);
++	ClearRetry(BIP_AAD);
++	ClearPwrMgt(BIP_AAD);
++	ClearMData(BIP_AAD);
++	/* conscruct AAD, copy address 1 to address 3 */
++	_rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18);
++
++	if (rtw_calculate_bip_mic(gmcs, whdr_pos,
++			pkt_len, key, BIP_AAD, ori_len, mic) == _FAIL)
++		goto BIP_exit;
++
++	/* MIC field should be last 8 bytes of packet (packet without FCS) */
++	if (_rtw_memcmp(mic, whdr_pos + flen - mic_len, mic_len)) {
++		*ipn = pkt_ipn;
++		res = _SUCCESS;
++	} else
++		RTW_INFO("BIP MIC error!\n");
++
++#if 0
++	/* management packet content */
++	{
++		int pp;
++		RTW_INFO("pkt: ");
++		RTW_INFO_DUMP("", whdr_pos, flen);
++		RTW_INFO("\n");
++		/* BIP AAD + management frame body + MME(MIC is zero) */
++		RTW_INFO("AAD+PKT: ");
++		RTW_INFO_DUMP("", BIP_AAD, ori_len);
++		RTW_INFO("\n");
++		/* show the MIC result */
++		RTW_INFO("mic: ");
++		RTW_INFO_DUMP("", mic, mic_len);
++		RTW_INFO("\n");
++	}
++#endif
++
++BIP_exit:
++
++	rtw_mfree(BIP_AAD, ori_len);
++	return res;
++}
++
++#endif /* CONFIG_IEEE80211W */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_sreset.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_sreset.c
+new file mode 100644
+index 000000000..c04360bc7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_sreset.c
+@@ -0,0 +1,316 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <drv_types.h>
++#include <hal_data.h>
++#include <rtw_sreset.h>
++
++void sreset_init_value(_adapter *padapter)
++{
++#if defined(DBG_CONFIG_ERROR_DETECT)
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++
++	_rtw_mutex_init(&psrtpriv->silentreset_mutex);
++	psrtpriv->silent_reset_inprogress = _FALSE;
++	psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
++	psrtpriv->last_tx_time = 0;
++	psrtpriv->last_tx_complete_time = 0;
++#endif
++}
++void sreset_reset_value(_adapter *padapter)
++{
++#if defined(DBG_CONFIG_ERROR_DETECT)
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++
++	psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
++	psrtpriv->last_tx_time = 0;
++	psrtpriv->last_tx_complete_time = 0;
++#endif
++}
++
++u8 sreset_get_wifi_status(_adapter *padapter)
++{
++#if defined(DBG_CONFIG_ERROR_DETECT)
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++	u8 status = WIFI_STATUS_SUCCESS;
++	u32 val32 = 0;
++
++	if (psrtpriv->silent_reset_inprogress == _TRUE)
++		return status;
++	val32 = rtw_read32(padapter, REG_TXDMA_STATUS);
++	if (val32 == 0xeaeaeaea)
++		psrtpriv->Wifi_Error_Status = WIFI_IF_NOT_EXIST;
++	else if (val32 != 0) {
++		RTW_INFO("txdmastatu(%x)\n", val32);
++		psrtpriv->Wifi_Error_Status = WIFI_MAC_TXDMA_ERROR;
++	}
++
++	if (WIFI_STATUS_SUCCESS != psrtpriv->Wifi_Error_Status) {
++		RTW_INFO("==>%s error_status(0x%x)\n", __FUNCTION__, psrtpriv->Wifi_Error_Status);
++		status = (psrtpriv->Wifi_Error_Status & (~(USB_READ_PORT_FAIL | USB_WRITE_PORT_FAIL)));
++	}
++	RTW_INFO("==> %s wifi_status(0x%x)\n", __FUNCTION__, status);
++
++	/* status restore */
++	psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
++
++	return status;
++#else
++	return WIFI_STATUS_SUCCESS;
++#endif
++}
++
++void sreset_set_wifi_error_status(_adapter *padapter, u32 status)
++{
++#if defined(DBG_CONFIG_ERROR_DETECT)
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	pHalData->srestpriv.Wifi_Error_Status = status;
++#endif
++}
++
++void sreset_set_trigger_point(_adapter *padapter, s32 tgp)
++{
++#if defined(DBG_CONFIG_ERROR_DETECT)
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	pHalData->srestpriv.dbg_trigger_point = tgp;
++#endif
++}
++
++bool sreset_inprogress(_adapter *padapter)
++{
++#if defined(DBG_CONFIG_ERROR_RESET)
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	return pHalData->srestpriv.silent_reset_inprogress;
++#else
++	return _FALSE;
++#endif
++}
++
++void sreset_restore_security_station(_adapter *padapter)
++{
++	struct mlme_priv *mlmepriv = &padapter->mlmepriv;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct sta_info *psta;
++	struct mlme_ext_info	*pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;
++
++	{
++		u8 val8;
++
++		if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) {
++			val8 = 0xcc;
++#ifdef CONFIG_WAPI_SUPPORT
++		} else if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) {
++			/* Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey. */
++			val8 = 0x4c;
++#endif
++		} else
++			val8 = 0xcf;
++		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
++	}
++
++	if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
++	    (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) {
++		psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv));
++		if (psta == NULL) {
++			/* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */
++		} else {
++			/* pairwise key */
++			rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _FALSE);
++			/* group key */
++			rtw_set_key(padapter, &padapter->securitypriv, padapter->securitypriv.dot118021XGrpKeyid, 0, _FALSE);
++		}
++	}
++}
++
++void sreset_restore_network_station(_adapter *padapter)
++{
++	struct mlme_priv *mlmepriv = &padapter->mlmepriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8 doiqk = _FALSE;
++
++	rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, RTW_CMDF_DIRECTLY);
++
++	{
++		u8 threshold;
++#ifdef CONFIG_USB_HCI
++		/* TH=1 => means that invalidate usb rx aggregation */
++		/* TH=0 => means that validate usb rx aggregation, use init value. */
++#ifdef CONFIG_80211N_HT
++		if (mlmepriv->htpriv.ht_option) {
++			if (padapter->registrypriv.wifi_spec == 1)
++				threshold = 1;
++			else
++				threshold = 0;
++			rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
++		} else {
++			threshold = 1;
++			rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
++		}
++#endif /* CONFIG_80211N_HT */
++#endif
++	}
++
++	doiqk = _TRUE;
++	rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK , &doiqk);
++
++	set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++
++	doiqk = _FALSE;
++	rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
++	/* disable dynamic functions, such as high power, DIG */
++	/*rtw_phydm_func_disable_all(padapter);*/
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
++
++	{
++		u8	join_type = 0;
++
++		rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTING);
++		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
++
++		rtw_btcoex_connect_notify(padapter, join_type);
++	}
++
++	Set_MSR(padapter, (pmlmeinfo->state & 0x3));
++
++	mlmeext_joinbss_event_callback(padapter, 1);
++	/* restore Sequence No. */
++	rtw_hal_set_hwreg(padapter, HW_VAR_RESTORE_HW_SEQ, 0);
++
++	sreset_restore_security_station(padapter);
++}
++
++
++void sreset_restore_network_status(_adapter *padapter)
++{
++	struct mlme_priv *mlmepriv = &padapter->mlmepriv;
++
++	if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) {
++		RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
++		sreset_restore_network_station(padapter);
++	} else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
++		RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(padapter), MLME_IS_AP(padapter) ? "AP" : "MESH");
++		rtw_ap_restore_network(padapter);
++	} else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE))
++		RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
++	else
++		RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
++}
++
++void sreset_stop_adapter(_adapter *padapter)
++{
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
++
++	if (padapter == NULL)
++		return;
++
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++	rtw_netif_stop_queue(padapter->pnetdev);
++
++	rtw_cancel_all_timer(padapter);
++
++	/* TODO: OS and HCI independent */
++#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)
++	tasklet_kill(&pxmitpriv->xmit_tasklet);
++#endif
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY))
++		rtw_scan_abort(padapter);
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING)) {
++		rtw_set_to_roam(padapter, 0);
++		rtw_join_timeout_handler(padapter);
++	}
++
++}
++
++void sreset_start_adapter(_adapter *padapter)
++{
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
++
++	if (padapter == NULL)
++		return;
++
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
++		sreset_restore_network_status(padapter);
++
++	/* TODO: OS and HCI independent */
++#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)
++	tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
++#endif
++
++	if (is_primary_adapter(padapter))
++		_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
++
++	rtw_netif_wake_queue(padapter->pnetdev);
++}
++
++void sreset_reset(_adapter *padapter)
++{
++#ifdef DBG_CONFIG_ERROR_RESET
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
++	_irqL irqL;
++	systime start = rtw_get_current_time();
++	struct dvobj_priv *psdpriv = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
++
++
++#ifdef CONFIG_LPS
++	rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "SRESET");
++#endif/* #ifdef CONFIG_LPS */
++
++	_enter_pwrlock(&pwrpriv->lock);
++
++	psrtpriv->silent_reset_inprogress = _TRUE;
++	pwrpriv->change_rfpwrstate = rf_off;
++
++	rtw_mi_sreset_adapter_hdl(padapter, _FALSE);/*sreset_stop_adapter*/
++#ifdef CONFIG_IPS
++	_ips_enter(padapter);
++	_ips_leave(padapter);
++#endif
++#ifdef CONFIG_CONCURRENT_MODE
++	rtw_mi_ap_info_restore(padapter);
++#endif
++	rtw_mi_sreset_adapter_hdl(padapter, _TRUE);/*sreset_start_adapter*/
++
++	psrtpriv->silent_reset_inprogress = _FALSE;
++
++	_exit_pwrlock(&pwrpriv->lock);
++
++	RTW_INFO("%s done in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
++	pdbgpriv->dbg_sreset_cnt++;
++
++	psrtpriv->self_dect_fw = _FALSE;
++	psrtpriv->rx_cnt = 0;
++#endif
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_sta_mgt.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_sta_mgt.c
+new file mode 100644
+index 000000000..ef4720cfb
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_sta_mgt.c
+@@ -0,0 +1,1352 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_STA_MGT_C_
++
++#include <drv_types.h>
++
++bool test_st_match_rule(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
++{
++	if (ntohs(*((u16 *)local_port)) == 5001 || ntohs(*((u16 *)remote_port)) == 5001)
++		return _TRUE;
++	return _FALSE;
++}
++
++struct st_register test_st_reg = {
++	.s_proto = 0x06,
++	.rule = test_st_match_rule,
++};
++
++inline void rtw_st_ctl_init(struct st_ctl_t *st_ctl)
++{
++	_rtw_memset(st_ctl->reg, 0 , sizeof(struct st_register) * SESSION_TRACKER_REG_ID_NUM);
++	_rtw_init_queue(&st_ctl->tracker_q);
++}
++
++inline void rtw_st_ctl_clear_tracker_q(struct st_ctl_t *st_ctl)
++{
++	_irqL irqL;
++	_list *plist, *phead;
++	struct session_tracker *st;
++
++	_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);
++	phead = &st_ctl->tracker_q.queue;
++	plist = get_next(phead);
++	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
++		st = LIST_CONTAINOR(plist, struct session_tracker, list);
++		plist = get_next(plist);
++		rtw_list_delete(&st->list);
++		rtw_mfree((u8 *)st, sizeof(struct session_tracker));
++	}
++	_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
++}
++
++inline void rtw_st_ctl_deinit(struct st_ctl_t *st_ctl)
++{
++	rtw_st_ctl_clear_tracker_q(st_ctl);
++	_rtw_deinit_queue(&st_ctl->tracker_q);
++}
++
++inline void rtw_st_ctl_register(struct st_ctl_t *st_ctl, u8 st_reg_id, struct st_register *reg)
++{
++	if (st_reg_id >= SESSION_TRACKER_REG_ID_NUM) {
++		rtw_warn_on(1);
++		return;
++	}
++
++	st_ctl->reg[st_reg_id].s_proto = reg->s_proto;
++	st_ctl->reg[st_reg_id].rule = reg->rule;
++}
++
++inline void rtw_st_ctl_unregister(struct st_ctl_t *st_ctl, u8 st_reg_id)
++{
++	int i;
++
++	if (st_reg_id >= SESSION_TRACKER_REG_ID_NUM) {
++		rtw_warn_on(1);
++		return;
++	}
++
++	st_ctl->reg[st_reg_id].s_proto = 0;
++	st_ctl->reg[st_reg_id].rule = NULL;
++
++	/* clear tracker queue if no session trecker registered */
++	for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++)
++		if (st_ctl->reg[i].s_proto != 0)
++			break;
++	if (i >= SESSION_TRACKER_REG_ID_NUM)
++		rtw_st_ctl_clear_tracker_q(st_ctl);
++}
++
++inline bool rtw_st_ctl_chk_reg_s_proto(struct st_ctl_t *st_ctl, u8 s_proto)
++{
++	bool ret = _FALSE;
++	int i;
++
++	for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) {
++		if (st_ctl->reg[i].s_proto == s_proto) {
++			ret = _TRUE;
++			break;
++		}
++	}
++
++	return ret;
++}
++
++inline bool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
++{
++	bool ret = _FALSE;
++	int i;
++	st_match_rule rule;
++
++	for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) {
++		rule = st_ctl->reg[i].rule;
++		if (rule && rule(adapter, local_naddr, local_port, remote_naddr, remote_port) == _TRUE) {
++			ret = _TRUE;
++			break;
++		}
++	}
++
++	return ret;
++}
++
++void rtw_st_ctl_rx(struct sta_info *sta, u8 *ehdr_pos)
++{
++	_adapter *adapter = sta->padapter;
++	struct ethhdr *etherhdr = (struct ethhdr *)ehdr_pos;
++
++	if (ntohs(etherhdr->h_proto) == ETH_P_IP) {
++		u8 *ip = ehdr_pos + ETH_HLEN;
++
++		if (GET_IPV4_PROTOCOL(ip) == 0x06  /* TCP */
++			&& rtw_st_ctl_chk_reg_s_proto(&sta->st_ctl, 0x06) == _TRUE
++		) {
++			u8 *tcp = ip + GET_IPV4_IHL(ip) * 4;
++
++			if (rtw_st_ctl_chk_reg_rule(&sta->st_ctl, adapter, IPV4_DST(ip), TCP_DST(tcp), IPV4_SRC(ip), TCP_SRC(tcp)) == _TRUE) {
++				if (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) {
++					session_tracker_add_cmd(adapter, sta
++						, IPV4_DST(ip), TCP_DST(tcp)
++						, IPV4_SRC(ip), TCP_SRC(tcp));
++					if (DBG_SESSION_TRACKER)
++						RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" SYN-ACK\n"
++							, FUNC_ADPT_ARG(adapter)
++							, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp))
++							, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp)));
++				}
++				if (GET_TCP_FIN(tcp)) {
++					session_tracker_del_cmd(adapter, sta
++						, IPV4_DST(ip), TCP_DST(tcp)
++						, IPV4_SRC(ip), TCP_SRC(tcp));
++					if (DBG_SESSION_TRACKER)
++						RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" FIN\n"
++							, FUNC_ADPT_ARG(adapter)
++							, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp))
++							, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp)));
++				}
++			}
++
++		}
++	}
++}
++
++#define SESSION_TRACKER_FMT IP_FMT":"PORT_FMT" "IP_FMT":"PORT_FMT" %u %d"
++#define SESSION_TRACKER_ARG(st) IP_ARG(&(st)->local_naddr), PORT_ARG(&(st)->local_port), IP_ARG(&(st)->remote_naddr), PORT_ARG(&(st)->remote_port), (st)->status, rtw_get_passing_time_ms((st)->set_time)
++
++void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl)
++{
++	int i;
++	_irqL irqL;
++	_list *plist, *phead;
++	struct session_tracker *st;
++
++	if (!DBG_SESSION_TRACKER)
++		return;
++
++	for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++)
++		RTW_PRINT_SEL(sel, "reg%d: %u %p\n", i, st_ctl->reg[i].s_proto, st_ctl->reg[i].rule);
++
++	_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);
++	phead = &st_ctl->tracker_q.queue;
++	plist = get_next(phead);
++	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
++		st = LIST_CONTAINOR(plist, struct session_tracker, list);
++		plist = get_next(plist);
++
++		RTW_PRINT_SEL(sel, SESSION_TRACKER_FMT"\n", SESSION_TRACKER_ARG(st));
++	}
++	_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
++
++}
++
++void _rtw_init_stainfo(struct sta_info *psta);
++void _rtw_init_stainfo(struct sta_info *psta)
++{
++	_rtw_memset((u8 *)psta, 0, sizeof(struct sta_info));
++
++	_rtw_spinlock_init(&psta->lock);
++	_rtw_init_listhead(&psta->list);
++	_rtw_init_listhead(&psta->hash_list);
++	/* _rtw_init_listhead(&psta->asoc_list); */
++	/* _rtw_init_listhead(&psta->sleep_list); */
++	/* _rtw_init_listhead(&psta->wakeup_list);	 */
++
++	_rtw_init_queue(&psta->sleep_q);
++
++	_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);
++	_rtw_init_sta_recv_priv(&psta->sta_recvpriv);
++
++#ifdef CONFIG_AP_MODE
++	_rtw_init_listhead(&psta->asoc_list);
++	_rtw_init_listhead(&psta->auth_list);
++	psta->bpairwise_key_installed = _FALSE;
++
++#ifdef CONFIG_RTW_80211R
++	psta->ft_pairwise_key_installed = _FALSE;
++#endif
++#endif /* CONFIG_AP_MODE	 */
++
++	rtw_st_ctl_init(&psta->st_ctl);
++}
++
++u32	_rtw_init_sta_priv(struct	sta_priv *pstapriv)
++{
++	_adapter *adapter = container_of(pstapriv, _adapter, stapriv);
++	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
++	struct sta_info *psta;
++	s32 i;
++	u32 ret = _FAIL;
++
++	pstapriv->padapter = adapter;
++
++	pstapriv->pallocated_stainfo_buf = rtw_zvmalloc(
++		sizeof(struct sta_info) * NUM_STA + MEM_ALIGNMENT_OFFSET);
++	if (!pstapriv->pallocated_stainfo_buf)
++		goto exit;
++
++	pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf;
++	if ((SIZE_PTR)pstapriv->pstainfo_buf & MEM_ALIGNMENT_PADDING)
++		pstapriv->pstainfo_buf += MEM_ALIGNMENT_OFFSET -
++			((SIZE_PTR)pstapriv->pstainfo_buf & MEM_ALIGNMENT_PADDING);
++
++	_rtw_init_queue(&pstapriv->free_sta_queue);
++
++	_rtw_spinlock_init(&pstapriv->sta_hash_lock);
++
++	/* _rtw_init_queue(&pstapriv->asoc_q); */
++	pstapriv->asoc_sta_count = 0;
++	_rtw_init_queue(&pstapriv->sleep_q);
++	_rtw_init_queue(&pstapriv->wakeup_q);
++
++	psta = (struct sta_info *)(pstapriv->pstainfo_buf);
++
++
++	for (i = 0; i < NUM_STA; i++) {
++		_rtw_init_stainfo(psta);
++
++		_rtw_init_listhead(&(pstapriv->sta_hash[i]));
++
++		rtw_list_insert_tail(&psta->list, get_list_head(&pstapriv->free_sta_queue));
++
++		psta++;
++	}
++
++	pstapriv->adhoc_expire_to = 4; /* 4 * 2 = 8 sec */
++
++#ifdef CONFIG_AP_MODE
++	pstapriv->max_aid = macid_ctl->num;
++	pstapriv->rr_aid = 0;
++	pstapriv->started_aid = 1;
++	pstapriv->sta_aid = rtw_zmalloc(pstapriv->max_aid * sizeof(struct sta_info *));
++	if (!pstapriv->sta_aid)
++		goto exit;
++	pstapriv->aid_bmp_len = AID_BMP_LEN(pstapriv->max_aid);
++	pstapriv->sta_dz_bitmap = rtw_zmalloc(pstapriv->aid_bmp_len);
++	if (!pstapriv->sta_dz_bitmap)
++		goto exit;
++	pstapriv->tim_bitmap = rtw_zmalloc(pstapriv->aid_bmp_len);
++	if (!pstapriv->tim_bitmap)
++		goto exit;
++
++	_rtw_init_listhead(&pstapriv->asoc_list);
++	_rtw_init_listhead(&pstapriv->auth_list);
++	_rtw_spinlock_init(&pstapriv->asoc_list_lock);
++	_rtw_spinlock_init(&pstapriv->auth_list_lock);
++	pstapriv->asoc_list_cnt = 0;
++	pstapriv->auth_list_cnt = 0;
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	pstapriv->tbtx_asoc_list_cnt = 0;
++#endif
++
++	pstapriv->auth_to = 3; /* 3*2 = 6 sec */
++	pstapriv->assoc_to = 3;
++	/* pstapriv->expire_to = 900; */ /* 900*2 = 1800 sec = 30 min, expire after no any traffic. */
++	/* pstapriv->expire_to = 30; */ /* 30*2 = 60 sec = 1 min, expire after no any traffic. */
++#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++	pstapriv->expire_to = 3; /* 3*2 = 6 sec */
++#else
++	pstapriv->expire_to = 60;/* 60*2 = 120 sec = 2 min, expire after no any traffic. */
++#endif
++#ifdef CONFIG_ATMEL_RC_PATCH
++	_rtw_memset(pstapriv->atmel_rc_pattern, 0, ETH_ALEN);
++#endif
++	pstapriv->max_num_sta = NUM_STA;
++
++#endif
++
++#if CONFIG_RTW_MACADDR_ACL
++	for (i = 0; i < RTW_ACL_PERIOD_NUM; i++)
++		rtw_macaddr_acl_init(adapter, i);
++#endif
++
++#if CONFIG_RTW_PRE_LINK_STA
++	rtw_pre_link_sta_ctl_init(pstapriv);
++#endif
++
++#if defined(DBG_ROAMING_TEST) || defined(CONFIG_RTW_REPEATER_SON)
++	rtw_set_rx_chk_limit(adapter,1);
++#elif defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && !defined(CONFIG_LPS_LCLK_WD_TIMER)
++	rtw_set_rx_chk_limit(adapter,4);
++#else
++	rtw_set_rx_chk_limit(adapter,8);
++#endif
++
++	ret = _SUCCESS;
++
++exit:
++	if (ret != _SUCCESS) {
++		if (pstapriv->pallocated_stainfo_buf)
++			rtw_vmfree(pstapriv->pallocated_stainfo_buf,
++				sizeof(struct sta_info) * NUM_STA + MEM_ALIGNMENT_OFFSET);
++		#ifdef CONFIG_AP_MODE
++		if (pstapriv->sta_aid)
++			rtw_mfree(pstapriv->sta_aid, pstapriv->max_aid * sizeof(struct sta_info *));
++		if (pstapriv->sta_dz_bitmap)
++			rtw_mfree(pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);
++		#endif
++	}
++
++	return ret;
++}
++
++inline int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta)
++{
++	int offset = (((u8 *)sta) - stapriv->pstainfo_buf) / sizeof(struct sta_info);
++
++	if (!stainfo_offset_valid(offset))
++		RTW_INFO("%s invalid offset(%d), out of range!!!", __func__, offset);
++
++	return offset;
++}
++
++inline struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset)
++{
++	if (!stainfo_offset_valid(offset))
++		RTW_INFO("%s invalid offset(%d), out of range!!!", __func__, offset);
++
++	return (struct sta_info *)(stapriv->pstainfo_buf + offset * sizeof(struct sta_info));
++}
++
++void	_rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv);
++void	_rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv)
++{
++
++	_rtw_spinlock_free(&psta_xmitpriv->lock);
++
++	_rtw_spinlock_free(&(psta_xmitpriv->be_q.sta_pending.lock));
++	_rtw_spinlock_free(&(psta_xmitpriv->bk_q.sta_pending.lock));
++	_rtw_spinlock_free(&(psta_xmitpriv->vi_q.sta_pending.lock));
++	_rtw_spinlock_free(&(psta_xmitpriv->vo_q.sta_pending.lock));
++}
++
++static void	_rtw_free_sta_recv_priv_lock(struct sta_recv_priv *psta_recvpriv)
++{
++
++	_rtw_spinlock_free(&psta_recvpriv->lock);
++
++	_rtw_spinlock_free(&(psta_recvpriv->defrag_q.lock));
++
++
++}
++
++void rtw_mfree_stainfo(struct sta_info *psta);
++void rtw_mfree_stainfo(struct sta_info *psta)
++{
++
++	if (&psta->lock != NULL)
++		_rtw_spinlock_free(&psta->lock);
++
++	_rtw_free_sta_xmit_priv_lock(&psta->sta_xmitpriv);
++	_rtw_free_sta_recv_priv_lock(&psta->sta_recvpriv);
++
++}
++
++
++/* this function is used to free the memory of lock || sema for all stainfos */
++void rtw_mfree_all_stainfo(struct sta_priv *pstapriv);
++void rtw_mfree_all_stainfo(struct sta_priv *pstapriv)
++{
++	_irqL	 irqL;
++	_list	*plist, *phead;
++	struct sta_info *psta = NULL;
++
++
++	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++	phead = get_list_head(&pstapriv->free_sta_queue);
++	plist = get_next(phead);
++
++	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++		psta = LIST_CONTAINOR(plist, struct sta_info , list);
++		plist = get_next(plist);
++
++		rtw_mfree_stainfo(psta);
++	}
++
++	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++
++}
++
++void rtw_mfree_sta_priv_lock(struct	sta_priv *pstapriv);
++void rtw_mfree_sta_priv_lock(struct	sta_priv *pstapriv)
++{
++	rtw_mfree_all_stainfo(pstapriv); /* be done before free sta_hash_lock */
++
++	_rtw_spinlock_free(&pstapriv->free_sta_queue.lock);
++
++	_rtw_spinlock_free(&pstapriv->sta_hash_lock);
++	_rtw_spinlock_free(&pstapriv->wakeup_q.lock);
++	_rtw_spinlock_free(&pstapriv->sleep_q.lock);
++
++#ifdef CONFIG_AP_MODE
++	_rtw_spinlock_free(&pstapriv->asoc_list_lock);
++	_rtw_spinlock_free(&pstapriv->auth_list_lock);
++#endif
++
++}
++
++u32	_rtw_free_sta_priv(struct	sta_priv *pstapriv)
++{
++	_irqL	irqL;
++	_list	*phead, *plist;
++	struct sta_info *psta = NULL;
++	struct recv_reorder_ctrl *preorder_ctrl;
++	int	index;
++
++	if (pstapriv) {
++
++		/*	delete all reordering_ctrl_timer		*/
++		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++		for (index = 0; index < NUM_STA; index++) {
++			phead = &(pstapriv->sta_hash[index]);
++			plist = get_next(phead);
++
++			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++				int i;
++				psta = LIST_CONTAINOR(plist, struct sta_info , hash_list);
++				plist = get_next(plist);
++
++				for (i = 0; i < 16 ; i++) {
++					preorder_ctrl = &psta->recvreorder_ctrl[i];
++					_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
++				}
++			}
++		}
++		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++		/*===============================*/
++
++		rtw_mfree_sta_priv_lock(pstapriv);
++
++#if CONFIG_RTW_MACADDR_ACL
++		for (index = 0; index < RTW_ACL_PERIOD_NUM; index++)
++			rtw_macaddr_acl_deinit(pstapriv->padapter, index);
++#endif
++
++#if CONFIG_RTW_PRE_LINK_STA
++		rtw_pre_link_sta_ctl_deinit(pstapriv);
++#endif
++
++		if (pstapriv->pallocated_stainfo_buf)
++			rtw_vmfree(pstapriv->pallocated_stainfo_buf,
++				sizeof(struct sta_info) * NUM_STA + MEM_ALIGNMENT_OFFSET);
++		#ifdef CONFIG_AP_MODE
++		if (pstapriv->sta_aid)
++			rtw_mfree(pstapriv->sta_aid, pstapriv->max_aid * sizeof(struct sta_info *));
++		if (pstapriv->sta_dz_bitmap)
++			rtw_mfree(pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);
++		if (pstapriv->tim_bitmap)
++			rtw_mfree(pstapriv->tim_bitmap, pstapriv->aid_bmp_len);
++		#endif
++	}
++
++	return _SUCCESS;
++}
++
++
++static void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl)
++{
++	_adapter *padapter = preorder_ctrl->padapter;
++
++#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
++	rtw_init_timer(&(preorder_ctrl->reordering_ctrl_timer), padapter, rtw_reordering_ctrl_timeout_handler, preorder_ctrl);
++#endif
++}
++
++/* struct	sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr) */
++struct	sta_info *rtw_alloc_stainfo(struct	sta_priv *pstapriv, const u8 *hwaddr)
++{
++	_irqL irqL2;
++	s32	index;
++	_list	*phash_list;
++	struct sta_info	*psta;
++	_queue *pfree_sta_queue;
++	struct recv_reorder_ctrl *preorder_ctrl;
++	int i = 0;
++	u16  wRxSeqInitialValue = 0xffff;
++
++
++	pfree_sta_queue = &pstapriv->free_sta_queue;
++
++	/* _enter_critical_bh(&(pfree_sta_queue->lock), &irqL); */
++	_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
++	if (_rtw_queue_empty(pfree_sta_queue) == _TRUE) {
++		/* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL); */
++		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */
++		psta = NULL;
++	} else {
++		psta = LIST_CONTAINOR(get_next(&pfree_sta_queue->queue), struct sta_info, list);
++
++		rtw_list_delete(&(psta->list));
++
++		/* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL); */
++		_rtw_init_stainfo(psta);
++
++		psta->padapter = pstapriv->padapter;
++
++		_rtw_memcpy(psta->cmn.mac_addr, hwaddr, ETH_ALEN);
++
++		index = wifi_mac_hash(hwaddr);
++
++
++		if (index >= NUM_STA) {
++			psta = NULL;
++			goto exit;
++		}
++		phash_list = &(pstapriv->sta_hash[index]);
++
++		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */
++
++		rtw_list_insert_tail(&psta->hash_list, phash_list);
++
++		pstapriv->asoc_sta_count++;
++
++		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */
++
++		/* Commented by Albert 2009/08/13
++		 * For the SMC router, the sequence number of first packet of WPS handshake will be 0.
++		 * In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable.
++		 * So, we initialize the tid_rxseq variable as the 0xffff. */
++
++		for (i = 0; i < 16; i++) {
++			_rtw_memcpy(&psta->sta_recvpriv.rxcache.tid_rxseq[i], &wRxSeqInitialValue, 2);
++			_rtw_memcpy(&psta->sta_recvpriv.bmc_tid_rxseq[i], &wRxSeqInitialValue, 2);
++			_rtw_memset(&psta->sta_recvpriv.rxcache.iv[i], 0, sizeof(psta->sta_recvpriv.rxcache.iv[i]));
++		}
++
++		rtw_init_timer(&psta->addba_retry_timer, psta->padapter, addba_timer_hdl, psta);
++#ifdef CONFIG_IEEE80211W
++		rtw_init_timer(&psta->dot11w_expire_timer, psta->padapter, sa_query_timer_hdl, psta);
++#endif /* CONFIG_IEEE80211W */
++#ifdef CONFIG_TDLS
++		rtw_init_tdls_timer(pstapriv->padapter, psta);
++#endif /* CONFIG_TDLS */
++
++		/* for A-MPDU Rx reordering buffer control */
++		for (i = 0; i < 16 ; i++) {
++			preorder_ctrl = &psta->recvreorder_ctrl[i];
++			preorder_ctrl->padapter = pstapriv->padapter;
++			preorder_ctrl->tid = i;
++			preorder_ctrl->enable = _FALSE;
++			preorder_ctrl->indicate_seq = 0xffff;
++			#ifdef DBG_RX_SEQ
++			RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%d\n"
++				, FUNC_ADPT_ARG(pstapriv->padapter), i, preorder_ctrl->indicate_seq);
++			#endif
++			preorder_ctrl->wend_b = 0xffff;
++			/* preorder_ctrl->wsize_b = (NR_RECVBUFF-2); */
++			preorder_ctrl->wsize_b = 64;/* 64; */
++			preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID;
++
++			_rtw_init_queue(&preorder_ctrl->pending_recvframe_queue);
++
++			rtw_init_recv_timer(preorder_ctrl);
++			rtw_clear_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack);
++
++		}
++
++
++		/* init for DM */
++		psta->cmn.rssi_stat.rssi = (-1);
++		psta->cmn.rssi_stat.rssi_cck = (-1);
++		psta->cmn.rssi_stat.rssi_ofdm = (-1);
++#ifdef CONFIG_ATMEL_RC_PATCH
++		psta->flag_atmel_rc = 0;
++#endif
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++		psta->tbtx_enable = _FALSE;
++#endif
++		/* init for the sequence number of received management frame */
++		psta->RxMgmtFrameSeqNum = 0xffff;
++		_rtw_memset(&psta->sta_stats, 0, sizeof(struct stainfo_stats));
++
++		rtw_alloc_macid(pstapriv->padapter, psta);
++
++		psta->tx_q_enable = 0;
++		_rtw_init_queue(&psta->tx_queue);
++		_init_workitem(&psta->tx_q_work, rtw_xmit_dequeue_callback, NULL);
++	}
++
++exit:
++
++	_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
++
++
++	if (psta)
++		rtw_mi_update_iface_status(&(pstapriv->padapter->mlmepriv), 0);
++
++	return psta;
++}
++
++
++/* using pstapriv->sta_hash_lock to protect */
++u32	rtw_free_stainfo(_adapter *padapter , struct sta_info *psta)
++{
++	int i;
++	_irqL irqL0;
++	_queue *pfree_sta_queue;
++	struct recv_reorder_ctrl *preorder_ctrl;
++	struct	sta_xmit_priv	*pstaxmitpriv;
++	struct	xmit_priv	*pxmitpriv = &padapter->xmitpriv;
++	struct	sta_priv *pstapriv = &padapter->stapriv;
++	struct hw_xmit *phwxmit;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	int pending_qcnt[4];
++	u8 is_pre_link_sta = _FALSE;
++
++	if (psta == NULL)
++		goto exit;
++
++#ifdef CONFIG_RTW_80211K
++	rm_post_event(padapter, RM_ID_FOR_ALL(psta->cmn.aid), RM_EV_cancel);
++#endif
++
++	is_pre_link_sta = rtw_is_pre_link_sta(pstapriv, psta->cmn.mac_addr);
++
++	if (is_pre_link_sta == _FALSE) {
++		_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
++		rtw_list_delete(&psta->hash_list);
++		pstapriv->asoc_sta_count--;
++		_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
++		rtw_mi_update_iface_status(&(padapter->mlmepriv), 0);
++	} else {
++		_enter_critical_bh(&psta->lock, &irqL0);
++		psta->state = WIFI_FW_PRE_LINK;
++		_exit_critical_bh(&psta->lock, &irqL0);
++	}
++
++	_enter_critical_bh(&psta->lock, &irqL0);
++	psta->state &= ~WIFI_ASOC_STATE;
++	_exit_critical_bh(&psta->lock, &irqL0);
++
++	pfree_sta_queue = &pstapriv->free_sta_queue;
++
++
++	pstaxmitpriv = &psta->sta_xmitpriv;
++
++	/* rtw_list_delete(&psta->sleep_list); */
++
++	/* rtw_list_delete(&psta->wakeup_list); */
++
++	rtw_free_xmitframe_queue(pxmitpriv, &psta->tx_queue);
++	_rtw_deinit_queue(&psta->tx_queue);
++
++	_enter_critical_bh(&pxmitpriv->lock, &irqL0);
++
++	rtw_free_xmitframe_queue(pxmitpriv, &psta->sleep_q);
++	psta->sleepq_len = 0;
++
++	/* vo */
++	/* _enter_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); */
++	rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->vo_q.sta_pending);
++	rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));
++	phwxmit = pxmitpriv->hwxmits;
++	phwxmit->accnt -= pstaxmitpriv->vo_q.qcnt;
++	pending_qcnt[0] = pstaxmitpriv->vo_q.qcnt;
++	pstaxmitpriv->vo_q.qcnt = 0;
++	/* _exit_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); */
++
++	/* vi */
++	/* _enter_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); */
++	rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->vi_q.sta_pending);
++	rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));
++	phwxmit = pxmitpriv->hwxmits + 1;
++	phwxmit->accnt -= pstaxmitpriv->vi_q.qcnt;
++	pending_qcnt[1] = pstaxmitpriv->vi_q.qcnt;
++	pstaxmitpriv->vi_q.qcnt = 0;
++	/* _exit_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); */
++
++	/* be */
++	/* _enter_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); */
++	rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->be_q.sta_pending);
++	rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));
++	phwxmit = pxmitpriv->hwxmits + 2;
++	phwxmit->accnt -= pstaxmitpriv->be_q.qcnt;
++	pending_qcnt[2] = pstaxmitpriv->be_q.qcnt;
++	pstaxmitpriv->be_q.qcnt = 0;
++	/* _exit_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); */
++
++	/* bk */
++	/* _enter_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); */
++	rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->bk_q.sta_pending);
++	rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));
++	phwxmit = pxmitpriv->hwxmits + 3;
++	phwxmit->accnt -= pstaxmitpriv->bk_q.qcnt;
++	pending_qcnt[3] = pstaxmitpriv->bk_q.qcnt;
++	pstaxmitpriv->bk_q.qcnt = 0;
++	/* _exit_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); */
++
++	rtw_os_wake_queue_at_free_stainfo(padapter, pending_qcnt);
++
++	_exit_critical_bh(&pxmitpriv->lock, &irqL0);
++
++
++	/* re-init sta_info; 20061114 */ /* will be init in alloc_stainfo */
++	/* _rtw_init_sta_xmit_priv(&psta->sta_xmitpriv); */
++	/* _rtw_init_sta_recv_priv(&psta->sta_recvpriv); */
++#ifdef CONFIG_IEEE80211W
++	_cancel_timer_ex(&psta->dot11w_expire_timer);
++#endif /* CONFIG_IEEE80211W */
++	_cancel_timer_ex(&psta->addba_retry_timer);
++
++#ifdef CONFIG_TDLS
++	psta->tdls_sta_state = TDLS_STATE_NONE;
++#endif /* CONFIG_TDLS */
++
++	/* for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer */
++	for (i = 0; i < 16 ; i++) {
++		_irqL irqL;
++		_list	*phead, *plist;
++		union recv_frame *prframe;
++		_queue *ppending_recvframe_queue;
++		_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
++
++		preorder_ctrl = &psta->recvreorder_ctrl[i];
++		rtw_clear_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack);
++		
++		_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
++
++
++		ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
++
++		_enter_critical_bh(&ppending_recvframe_queue->lock, &irqL);
++
++		phead =	get_list_head(ppending_recvframe_queue);
++		plist = get_next(phead);
++
++		while (!rtw_is_list_empty(phead)) {
++			prframe = LIST_CONTAINOR(plist, union recv_frame, u);
++
++			plist = get_next(plist);
++
++			rtw_list_delete(&(prframe->u.hdr.list));
++
++			rtw_free_recvframe(prframe, pfree_recv_queue);
++		}
++
++		_exit_critical_bh(&ppending_recvframe_queue->lock, &irqL);
++
++	}
++
++	if (!((psta->state & WIFI_AP_STATE) || MacAddr_isBcst(psta->cmn.mac_addr)) && is_pre_link_sta == _FALSE)
++		rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _FALSE);
++
++
++	/* release mac id for non-bc/mc station, */
++	if (is_pre_link_sta == _FALSE)
++		rtw_release_macid(pstapriv->padapter, psta);
++
++#ifdef CONFIG_AP_MODE
++
++	/*
++		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL0);
++		rtw_list_delete(&psta->asoc_list);
++		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL0);
++	*/
++	_enter_critical_bh(&pstapriv->auth_list_lock, &irqL0);
++	if (!rtw_is_list_empty(&psta->auth_list)) {
++		rtw_list_delete(&psta->auth_list);
++		pstapriv->auth_list_cnt--;
++	}
++	_exit_critical_bh(&pstapriv->auth_list_lock, &irqL0);
++
++	psta->expire_to = 0;
++#ifdef CONFIG_ATMEL_RC_PATCH
++	psta->flag_atmel_rc = 0;
++#endif
++	psta->sleepq_ac_len = 0;
++	psta->qos_info = 0;
++
++	psta->max_sp_len = 0;
++	psta->uapsd_bk = 0;
++	psta->uapsd_be = 0;
++	psta->uapsd_vi = 0;
++	psta->uapsd_vo = 0;
++
++	psta->has_legacy_ac = 0;
++
++#ifdef CONFIG_NATIVEAP_MLME
++
++	if (pmlmeinfo->state == _HW_STATE_AP_) {
++		rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid);
++		rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
++
++		/* rtw_indicate_sta_disassoc_event(padapter, psta); */
++
++		if ((psta->cmn.aid > 0) && (pstapriv->sta_aid[psta->cmn.aid - 1] == psta)) {
++			pstapriv->sta_aid[psta->cmn.aid - 1] = NULL;
++			psta->cmn.aid = 0;
++		}
++	}
++
++#endif /* CONFIG_NATIVEAP_MLME	 */
++
++#if !defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && defined(CONFIG_80211N_HT)
++	psta->under_exist_checking = 0;
++#endif
++
++#endif /* CONFIG_AP_MODE	 */
++
++	rtw_st_ctl_deinit(&psta->st_ctl);
++
++	if (is_pre_link_sta == _FALSE) {
++		_rtw_spinlock_free(&psta->lock);
++
++		/* _enter_critical_bh(&(pfree_sta_queue->lock), &irqL0); */
++		_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
++		rtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue));
++		_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
++		/* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL0); */
++	}
++
++exit:
++	return _SUCCESS;
++}
++
++/* free all stainfo which in sta_hash[all] */
++void rtw_free_all_stainfo(_adapter *padapter)
++{
++	_irqL	 irqL;
++	_list	*plist, *phead;
++	s32	index;
++	struct sta_info *psta = NULL;
++	struct	sta_priv *pstapriv = &padapter->stapriv;
++	struct sta_info *pbcmc_stainfo = rtw_get_bcmc_stainfo(padapter);
++	u8 free_sta_num = 0;
++	char free_sta_list[NUM_STA];
++	int stainfo_offset;
++
++
++	if (pstapriv->asoc_sta_count == 1)
++		goto exit;
++
++	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++	for (index = 0; index < NUM_STA; index++) {
++		phead = &(pstapriv->sta_hash[index]);
++		plist = get_next(phead);
++
++		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++			psta = LIST_CONTAINOR(plist, struct sta_info , hash_list);
++
++			plist = get_next(plist);
++
++			if (pbcmc_stainfo != psta) {
++				if (rtw_is_pre_link_sta(pstapriv, psta->cmn.mac_addr) == _FALSE)
++					rtw_list_delete(&psta->hash_list);
++
++				stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
++				if (stainfo_offset_valid(stainfo_offset))
++					free_sta_list[free_sta_num++] = stainfo_offset;
++			}
++
++		}
++	}
++
++	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++
++	for (index = 0; index < free_sta_num; index++) {
++		psta = rtw_get_stainfo_by_offset(pstapriv, free_sta_list[index]);
++		rtw_free_stainfo(padapter , psta);
++	}
++
++exit:
++	return;
++}
++
++/* any station allocated can be searched by hash list */
++struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr)
++{
++
++	_irqL	 irqL;
++
++	_list	*plist, *phead;
++
++	struct sta_info *psta = NULL;
++
++	u32	index;
++
++	const u8 *addr;
++
++	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++
++
++	if (hwaddr == NULL)
++		return NULL;
++
++	if (IS_MCAST(hwaddr))
++		addr = bc_addr;
++	else
++		addr = hwaddr;
++
++	index = wifi_mac_hash(addr);
++
++	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++	phead = &(pstapriv->sta_hash[index]);
++	plist = get_next(phead);
++
++
++	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++
++		psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++
++		if ((_rtw_memcmp(psta->cmn.mac_addr, addr, ETH_ALEN)) == _TRUE) {
++			/* if found the matched address */
++			break;
++		}
++		psta = NULL;
++		plist = get_next(plist);
++	}
++
++	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++	return psta;
++
++}
++
++u32 rtw_init_bcmc_stainfo(_adapter *padapter)
++{
++
++	struct sta_info	*psta;
++	struct tx_servq	*ptxservq;
++	u32 res = _SUCCESS;
++	NDIS_802_11_MAC_ADDRESS	bcast_addr = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++
++	struct	sta_priv *pstapriv = &padapter->stapriv;
++	/* _queue	*pstapending = &padapter->xmitpriv.bm_pending; */
++
++
++	psta = rtw_alloc_stainfo(pstapriv, bcast_addr);
++
++	if (psta == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++#ifdef CONFIG_BEAMFORMING
++	psta->cmn.bf_info.g_id = 63;
++	psta->cmn.bf_info.p_aid = 0;
++#endif
++
++	ptxservq = &(psta->sta_xmitpriv.be_q);
++
++	/*
++		_enter_critical(&pstapending->lock, &irqL0);
++
++		if (rtw_is_list_empty(&ptxservq->tx_pending))
++			rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(pstapending));
++
++		_exit_critical(&pstapending->lock, &irqL0);
++	*/
++
++exit:
++	return _SUCCESS;
++
++}
++
++
++struct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter)
++{
++	struct sta_info	*psta;
++	struct sta_priv	*pstapriv = &padapter->stapriv;
++	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	psta = rtw_get_stainfo(pstapriv, bc_addr);
++	return psta;
++
++}
++
++#ifdef CONFIG_AP_MODE
++u16 rtw_aid_alloc(_adapter *adapter, struct sta_info *sta)
++{
++	struct sta_priv *stapriv = &adapter->stapriv;
++	u16 aid, i, used_cnt = 0;
++
++	for (i = 0; i < stapriv->max_aid; i++) {
++		aid = ((i + stapriv->started_aid - 1) % stapriv->max_aid) + 1;
++		if (stapriv->sta_aid[aid - 1] == NULL)
++			break;
++		if (++used_cnt >= stapriv->max_num_sta)
++			break;
++	}
++
++	/* check for aid limit and assoc limit  */
++	if (i >= stapriv->max_aid || used_cnt >= stapriv->max_num_sta)
++		aid = 0;
++
++	sta->cmn.aid = aid;
++	if (aid) {
++		stapriv->sta_aid[aid - 1] = sta;
++		if (stapriv->rr_aid)
++			stapriv->started_aid = (aid % stapriv->max_aid) + 1;
++	}
++
++	return aid;
++}
++
++void dump_aid_status(void *sel, _adapter *adapter)
++{
++	struct sta_priv *stapriv = &adapter->stapriv;
++	u8 *aid_bmp;
++	u16 i, used_cnt = 0;
++
++	aid_bmp = rtw_zmalloc(stapriv->aid_bmp_len);
++	if (!aid_bmp)
++		return;
++
++	for (i = 1; i <= stapriv->max_aid; i++) {
++		if (stapriv->sta_aid[i - 1]) {
++			aid_bmp[i / 8] |= BIT(i % 8);
++			++used_cnt;
++		}
++	}
++
++	RTW_PRINT_SEL(sel, "used_cnt:%u/%u\n", used_cnt, stapriv->max_aid);
++	RTW_MAP_DUMP_SEL(sel, "aid_map:", aid_bmp, stapriv->aid_bmp_len);
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "%-2s %-11s\n", "rr", "started_aid");
++	RTW_PRINT_SEL(sel, "%2d %11d\n", stapriv->rr_aid, stapriv->started_aid);
++
++	rtw_mfree(aid_bmp, stapriv->aid_bmp_len);
++}
++#endif /* CONFIG_AP_MODE */
++
++#if CONFIG_RTW_MACADDR_ACL
++const char *const _acl_period_str[RTW_ACL_PERIOD_NUM] = {
++	"DEV",
++	"BSS",
++};
++
++const char *const _acl_mode_str[RTW_ACL_MODE_MAX] = {
++	"DISABLED",
++	"ACCEPT_UNLESS_LISTED",
++	"DENY_UNLESS_LISTED",
++};
++
++u8 _rtw_access_ctrl(_adapter *adapter, u8 period, const u8 *mac_addr)
++{
++	u8 res = _TRUE;
++	_irqL irqL;
++	_list *list, *head;
++	struct rtw_wlan_acl_node *acl_node;
++	u8 match = _FALSE;
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct wlan_acl_pool *acl;
++	_queue	*acl_node_q;
++
++	if (period >= RTW_ACL_PERIOD_NUM) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	acl = &stapriv->acl_list[period];
++	acl_node_q = &acl->acl_node_q;
++
++	if (acl->mode != RTW_ACL_MODE_ACCEPT_UNLESS_LISTED
++		&& acl->mode != RTW_ACL_MODE_DENY_UNLESS_LISTED)
++		goto exit;
++
++	_enter_critical_bh(&(acl_node_q->lock), &irqL);
++	head = get_list_head(acl_node_q);
++	list = get_next(head);
++	while (rtw_end_of_queue_search(head, list) == _FALSE) {
++		acl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list);
++		list = get_next(list);
++
++		if (_rtw_memcmp(acl_node->addr, mac_addr, ETH_ALEN)) {
++			if (acl_node->valid == _TRUE) {
++				match = _TRUE;
++				break;
++			}
++		}
++	}
++	_exit_critical_bh(&(acl_node_q->lock), &irqL);
++
++	if (acl->mode == RTW_ACL_MODE_ACCEPT_UNLESS_LISTED)
++		res = (match == _TRUE) ?  _FALSE : _TRUE;
++	else /* RTW_ACL_MODE_DENY_UNLESS_LISTED */
++		res = (match == _TRUE) ?  _TRUE : _FALSE;
++
++exit:
++	return res;
++}
++
++u8 rtw_access_ctrl(_adapter *adapter, const u8 *mac_addr)
++{
++	int i;
++
++	for (i = 0; i < RTW_ACL_PERIOD_NUM; i++)
++		if (_rtw_access_ctrl(adapter, i, mac_addr) == _FALSE)
++			return _FALSE;
++
++	return _TRUE;
++}
++
++void dump_macaddr_acl(void *sel, _adapter *adapter)
++{
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct wlan_acl_pool *acl;
++	int i, j;
++
++	for (j = 0; j < RTW_ACL_PERIOD_NUM; j++) {
++		RTW_PRINT_SEL(sel, "period:%s(%d)\n", acl_period_str(j), j);
++
++		acl = &stapriv->acl_list[j];
++		RTW_PRINT_SEL(sel, "mode:%s(%d)\n", acl_mode_str(acl->mode), acl->mode);
++		RTW_PRINT_SEL(sel, "num:%d/%d\n", acl->num, NUM_ACL);
++		for (i = 0; i < NUM_ACL; i++) {
++			if (acl->aclnode[i].valid == _FALSE)
++				continue;
++			RTW_PRINT_SEL(sel, MAC_FMT"\n", MAC_ARG(acl->aclnode[i].addr));
++		}
++		RTW_PRINT_SEL(sel, "\n");
++	}
++}
++#endif /* CONFIG_RTW_MACADDR_ACL */
++
++bool rtw_is_pre_link_sta(struct sta_priv *stapriv, u8 *addr)
++{
++#if CONFIG_RTW_PRE_LINK_STA
++	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
++	struct sta_info *sta = NULL;
++	u8 exist = _FALSE;
++	int i;
++	_irqL irqL;
++
++	_enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
++	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
++		if (pre_link_sta_ctl->node[i].valid == _TRUE
++			&& _rtw_memcmp(pre_link_sta_ctl->node[i].addr, addr, ETH_ALEN) == _TRUE
++		) {
++			exist = _TRUE;
++			break;
++		}
++	}
++	_exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
++
++	return exist;
++#else
++	return _FALSE;
++#endif
++}
++
++#if CONFIG_RTW_PRE_LINK_STA
++struct sta_info *rtw_pre_link_sta_add(struct sta_priv *stapriv, u8 *hwaddr)
++{
++	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
++	struct pre_link_sta_node_t *node = NULL;
++	struct sta_info *sta = NULL;
++	u8 exist = _FALSE;
++	int i;
++	_irqL irqL;
++
++	if (rtw_check_invalid_mac_address(hwaddr, _FALSE) == _TRUE)
++		goto exit;
++
++	_enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
++	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
++		if (pre_link_sta_ctl->node[i].valid == _TRUE
++			&& _rtw_memcmp(pre_link_sta_ctl->node[i].addr, hwaddr, ETH_ALEN) == _TRUE
++		) {
++			node = &pre_link_sta_ctl->node[i];
++			exist = _TRUE;
++			break;
++		}
++
++		if (node == NULL && pre_link_sta_ctl->node[i].valid == _FALSE)
++			node = &pre_link_sta_ctl->node[i];
++	}
++
++	if (exist == _FALSE && node) {
++		_rtw_memcpy(node->addr, hwaddr, ETH_ALEN);
++		node->valid = _TRUE;
++		pre_link_sta_ctl->num++;
++	}
++	_exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
++
++	if (node == NULL)
++		goto exit;
++
++	sta = rtw_get_stainfo(stapriv, hwaddr);
++	if (sta)
++		goto odm_hook;
++
++	sta = rtw_alloc_stainfo(stapriv, hwaddr);
++	if (!sta)
++		goto exit;
++
++	sta->state = WIFI_FW_PRE_LINK;
++
++odm_hook:
++	rtw_hal_set_odm_var(stapriv->padapter, HAL_ODM_STA_INFO, sta, _TRUE);
++
++exit:
++	return sta;
++}
++
++void rtw_pre_link_sta_del(struct sta_priv *stapriv, u8 *hwaddr)
++{
++	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
++	struct pre_link_sta_node_t *node = NULL;
++	struct sta_info *sta = NULL;
++	u8 exist = _FALSE;
++	int i;
++	_irqL irqL;
++
++	if (rtw_check_invalid_mac_address(hwaddr, _FALSE) == _TRUE)
++		goto exit;
++
++	_enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
++	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
++		if (pre_link_sta_ctl->node[i].valid == _TRUE
++			&& _rtw_memcmp(pre_link_sta_ctl->node[i].addr, hwaddr, ETH_ALEN) == _TRUE
++		) {
++			node = &pre_link_sta_ctl->node[i];
++			exist = _TRUE;
++			break;
++		}
++	}
++
++	if (exist == _TRUE && node) {
++		node->valid = _FALSE;
++		pre_link_sta_ctl->num--;
++	}
++	_exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
++
++	if (exist == _FALSE)
++		goto exit;
++
++	sta = rtw_get_stainfo(stapriv, hwaddr);
++	if (!sta)
++		goto exit;
++
++	if (sta->state == WIFI_FW_PRE_LINK)
++		rtw_free_stainfo(stapriv->padapter, sta);
++
++exit:
++	return;
++}
++
++void rtw_pre_link_sta_ctl_reset(struct sta_priv *stapriv)
++{
++	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
++	struct pre_link_sta_node_t *node = NULL;
++	struct sta_info *sta = NULL;
++	int i, j = 0;
++	_irqL irqL;
++
++	u8 addrs[RTW_PRE_LINK_STA_NUM][ETH_ALEN];
++
++	_rtw_memset(addrs, 0, RTW_PRE_LINK_STA_NUM * ETH_ALEN);
++
++	_enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
++	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
++		if (pre_link_sta_ctl->node[i].valid == _FALSE)
++			continue;
++		_rtw_memcpy(&(addrs[j][0]), pre_link_sta_ctl->node[i].addr, ETH_ALEN);
++		pre_link_sta_ctl->node[i].valid = _FALSE;
++		pre_link_sta_ctl->num--;
++		j++;
++	}
++	_exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
++
++	for (i = 0; i < j; i++) {
++		sta = rtw_get_stainfo(stapriv, &(addrs[i][0]));
++		if (!sta)
++			continue;
++
++		if (sta->state == WIFI_FW_PRE_LINK)
++			rtw_free_stainfo(stapriv->padapter, sta);
++	}
++}
++
++void rtw_pre_link_sta_ctl_init(struct sta_priv *stapriv)
++{
++	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
++	int i;
++
++	_rtw_spinlock_init(&pre_link_sta_ctl->lock);
++	pre_link_sta_ctl->num = 0;
++	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++)
++		pre_link_sta_ctl->node[i].valid = _FALSE;
++}
++
++void rtw_pre_link_sta_ctl_deinit(struct sta_priv *stapriv)
++{
++	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
++	int i;
++
++	rtw_pre_link_sta_ctl_reset(stapriv);
++
++	_rtw_spinlock_free(&pre_link_sta_ctl->lock);
++}
++
++void dump_pre_link_sta_ctl(void *sel, struct sta_priv *stapriv)
++{
++	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
++	int i;
++
++	RTW_PRINT_SEL(sel, "num:%d/%d\n", pre_link_sta_ctl->num, RTW_PRE_LINK_STA_NUM);
++
++	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
++		if (pre_link_sta_ctl->node[i].valid == _FALSE)
++			continue;
++		RTW_PRINT_SEL(sel, MAC_FMT"\n", MAC_ARG(pre_link_sta_ctl->node[i].addr));
++	}
++}
++#endif /* CONFIG_RTW_PRE_LINK_STA */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_swcrypto.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_swcrypto.c
+new file mode 100644
+index 000000000..3659b3576
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_swcrypto.c
+@@ -0,0 +1,296 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#include <drv_types.h>
++#include <hal_data.h>
++#include <aes.h>
++#include <aes_siv.h>
++#include <aes_wrap.h>
++#include <sha256.h>
++#include <wlancrypto_wrap.h>
++
++/**
++ * rtw_ccmp_encrypt - 
++ * @key: the temporal key 
++ * @hdrlen: mac header length
++ * @frame: the frame including the mac header, pn and payload
++ * @plen: payload length, i.e., length of the plain text, without PN and MIC
++ */
++int _rtw_ccmp_encrypt(u8 *key, u32 key_len, uint hdrlen, u8 *frame, uint plen)
++{
++	u8 *enc = NULL;
++	size_t enc_len = 0;
++
++	if (key_len == 16) { /* 128 bits */
++		enc = ccmp_encrypt(key,
++			frame,
++			hdrlen + plen,
++			hdrlen,
++			(hdrlen == 26) ? (frame + hdrlen - 2) : NULL,
++			NULL, 0, &enc_len);
++	} else if (key_len == 32) { /* 256 bits */
++		enc = ccmp_256_encrypt(key,
++			frame,
++			hdrlen + plen,
++			hdrlen,
++			(hdrlen == 26) ? (frame + hdrlen - 2) : NULL,
++			NULL, 0, &enc_len);
++	}
++
++	if (enc == NULL) {
++		RTW_INFO("Failed to encrypt CCMP(%u) frame", key_len);
++		return _FAIL;
++	}
++
++	/* Copy @enc back to @frame and free @enc */
++	_rtw_memcpy(frame, enc, enc_len);
++	rtw_mfree(enc, enc_len + AES_BLOCK_SIZE);
++
++	return _SUCCESS;
++}
++
++
++/**
++ * rtw_ccmp_decrypt -
++ * @key: the temporal key
++ * @hdrlen: length of the mac header
++ * @frame: the raw frame (@hdrlen + PN + enc_data + MIC)
++ * @plen: length of the frame (@hdrlen + PN + enc_data + MIC)
++ */
++int _rtw_ccmp_decrypt(u8 *key, u32 key_len, uint hdrlen, u8 *frame,
++	uint plen)
++{
++	u8 *plain = NULL;
++	size_t plain_len = 0;
++	const struct ieee80211_hdr *hdr;
++
++	hdr = (const struct ieee80211_hdr *)frame;
++
++	if (key_len == 16) { /* 128 bits */
++		plain = ccmp_decrypt(key,
++			hdr,
++			frame + hdrlen, /* PN + enc_data + MIC */
++			plen - hdrlen, /* PN + enc_data + MIC */
++			&plain_len);
++	} else if (key_len == 32) { /* 256 bits */
++		plain = ccmp_256_decrypt(key,
++			hdr,
++			frame + hdrlen, /* PN + enc_data + MIC */
++			plen - hdrlen, /* PN + enc_data + MIC */
++			&plain_len);
++	}
++
++	if (plain == NULL) {
++		RTW_INFO("Failed to decrypt CCMP(%u) frame", key_len);
++		return _FAIL;
++	}
++
++	/* Copy @plain back to @frame and free @plain */
++	_rtw_memcpy(frame + hdrlen + 8, plain, plain_len);
++	rtw_mfree(plain, plen - hdrlen + AES_BLOCK_SIZE);
++
++	RTW_DBG_DUMP("ccmp_decrypt(): decrypted frame\n",
++		frame, hdrlen + 8 + plen);
++
++	return _SUCCESS;
++}
++
++
++#ifdef CONFIG_RTW_MESH_AEK
++/* wrapper to ase_siv_encrypt and aes_siv_decrypt */
++int _aes_siv_encrypt(const u8 *key, size_t key_len,
++	const u8 *pw, size_t pwlen,
++	size_t num_elem, const u8 *addr[], const size_t *len, u8 *out)
++{
++	return aes_siv_encrypt(key, key_len, pw, pwlen, num_elem, addr, len, out);
++}
++int _aes_siv_decrypt(const u8 *key, size_t key_len,
++	const u8 *iv_crypt, size_t iv_c_len,
++	size_t num_elem, const u8 *addr[], const size_t *len, u8 *out)
++{
++	return aes_siv_decrypt(key, key_len, iv_crypt, iv_c_len, num_elem, addr, len, out);
++}
++#endif
++
++
++/**
++ * _rtw_gcmp_encrypt - 
++ * @key: the temporal key 
++ * @hdrlen: mac header length
++ * @frame: the frame including the mac header, pn and payload
++ * @plen: payload length, i.e., length of the plain text, without PN and MIC
++ */
++int _rtw_gcmp_encrypt(u8 *key, u32 key_len, uint hdrlen, u8 *frame, uint plen)
++{
++	u8 *enc = NULL;
++	size_t enc_len = 0;
++
++	enc = gcmp_encrypt(key, key_len,
++		frame,
++		hdrlen + plen,
++		hdrlen,
++		(hdrlen == 26) ? (frame + hdrlen - 2) : NULL,
++		NULL, 0, &enc_len);
++	if (enc == NULL) {
++		RTW_INFO("Failed to encrypt GCMP frame");
++		return _FAIL;
++	}
++
++	/* Copy @enc back to @frame and free @enc */
++	_rtw_memcpy(frame, enc, enc_len);
++	rtw_mfree(enc, enc_len + AES_BLOCK_SIZE);
++
++	return _SUCCESS;
++}
++
++
++/**
++ * _rtw_gcmp_decrypt -
++ * @key: the temporal key
++ * @hdrlen: length of the mac header
++ * @frame: the raw frame (@hdrlen + PN + enc_data + MIC)
++ * @plen: length of the frame (@hdrlen + PN + enc_data + MIC)
++ */
++int _rtw_gcmp_decrypt(u8 *key, u32 key_len, uint hdrlen, u8 *frame, uint plen)
++{
++	u8 *plain = NULL;
++	size_t plain_len = 0;
++	const struct ieee80211_hdr *hdr;
++
++	hdr = (const struct ieee80211_hdr *)frame;
++
++	plain = gcmp_decrypt(key, key_len,
++		hdr,
++		frame + hdrlen, /* PN + enc_data + MIC */
++		plen - hdrlen, /* PN + enc_data + MIC */
++		&plain_len);
++
++	if (plain == NULL) {
++		RTW_INFO("Failed to decrypt GCMP(%u) frame", key_len);
++		return _FAIL;
++	}
++
++	/* Copy @plain back to @frame and free @plain */
++	_rtw_memcpy(frame + hdrlen + 8, plain, plain_len);
++	rtw_mfree(plain, plen - hdrlen + AES_BLOCK_SIZE);
++
++	RTW_DBG_DUMP("gcmp_decipher(): decrypted frame\n",
++		frame, hdrlen + 8 + plen);
++
++	return _SUCCESS;
++}
++
++
++#if  defined(CONFIG_IEEE80211W) | defined(CONFIG_TDLS)
++u8 _bip_ccmp_protect(const u8 *key, size_t key_len,
++	const u8 *data, size_t data_len, u8 *mic)
++{
++	u8 res = _SUCCESS;
++
++	if (key_len == 16) {
++		if (omac1_aes_128(key, data, data_len, mic)) {
++			res = _FAIL;
++			RTW_ERR("%s : omac1_aes_128 fail!", __func__);
++		}
++	} else if (key_len == 32) {
++		if (omac1_aes_256(key, data, data_len, mic)) {
++			res = _FAIL;
++			RTW_ERR("%s : omac1_aes_256 fail!", __func__);
++		}
++	} else {
++		RTW_ERR("%s : key_len not match!", __func__);
++		res = _FAIL;
++	}
++
++	return  res;
++}
++
++
++u8 _bip_gcmp_protect(u8 *whdr_pos, size_t len,
++	const u8 *key, size_t key_len,
++	const u8 *data, size_t data_len, u8 *mic)
++{
++	u8 res = _SUCCESS;
++	u32 mic_len = 16;
++	u8 nonce[12], *npos;
++	const u8 *gcmp_ipn;
++
++	gcmp_ipn = whdr_pos + len - mic_len - 6;
++
++	/* Nonce: A2 | IPN */
++	_rtw_memcpy(nonce, get_addr2_ptr(whdr_pos), ETH_ALEN);
++	npos = nonce + ETH_ALEN;
++	*npos++ = gcmp_ipn[5];
++	*npos++ = gcmp_ipn[4];
++	*npos++ = gcmp_ipn[3];
++	*npos++ = gcmp_ipn[2];
++	*npos++ = gcmp_ipn[1];
++	*npos++ = gcmp_ipn[0];
++
++	if (aes_gmac(key, key_len, nonce, sizeof(nonce),
++			data, data_len, mic)) {
++		res = _FAIL;
++		RTW_ERR("%s : aes_gmac fail!", __func__);
++	}
++
++	return res;
++}
++#endif /* CONFIG_IEEE80211W */
++
++
++#ifdef CONFIG_TDLS
++void _tdls_generate_tpk(void *sta, const u8 *own_addr, const u8 *bssid)
++{
++	struct sta_info *psta = (struct sta_info *)sta;
++	u8 *SNonce = psta->SNonce;
++	u8 *ANonce = psta->ANonce;
++
++	u8 key_input[SHA256_MAC_LEN];
++	const u8 *nonce[2];
++	size_t len[2];
++	u8 data[3 * ETH_ALEN];
++
++	/* IEEE Std 802.11z-2010 8.5.9.1:
++	 * TPK-Key-Input = SHA-256(min(SNonce, ANonce) || max(SNonce, ANonce))
++	 */
++	len[0] = 32;
++	len[1] = 32;
++	if (_rtw_memcmp2(SNonce, ANonce, 32) < 0) {
++		nonce[0] = SNonce;
++		nonce[1] = ANonce;
++	} else {
++		nonce[0] = ANonce;
++		nonce[1] = SNonce;
++	}
++
++	sha256_vector(2, nonce, len, key_input);
++
++	/*
++	 * TPK = KDF-Hash-Length(TPK-Key-Input, "TDLS PMK",
++	 *	min(MAC_I, MAC_R) || max(MAC_I, MAC_R) || BSSID)
++	 */
++
++	if (_rtw_memcmp2(own_addr, psta->cmn.mac_addr, ETH_ALEN) < 0) {
++		_rtw_memcpy(data, own_addr, ETH_ALEN);
++		_rtw_memcpy(data + ETH_ALEN, psta->cmn.mac_addr, ETH_ALEN);
++	} else {
++		_rtw_memcpy(data, psta->cmn.mac_addr, ETH_ALEN);
++		_rtw_memcpy(data + ETH_ALEN, own_addr, ETH_ALEN);
++	}
++
++	_rtw_memcpy(data + 2 * ETH_ALEN, bssid, ETH_ALEN);
++
++	sha256_prf(key_input, SHA256_MAC_LEN, "TDLS PMK", data, sizeof(data), (u8 *)&psta->tpk, sizeof(psta->tpk));
++}
++#endif /* CONFIG_TDLS */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_tdls.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_tdls.c
+new file mode 100644
+index 000000000..6b7480ec4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_tdls.c
+@@ -0,0 +1,3507 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_TDLS_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++#ifdef CONFIG_TDLS
++#define ONE_SEC 	1000 /* 1000 ms */
++
++extern unsigned char MCS_rate_2R[16];
++extern unsigned char MCS_rate_1R[16];
++
++inline void rtw_tdls_set_link_established(_adapter *adapter, bool en)
++{
++	adapter->tdlsinfo.link_established = en;
++	rtw_mi_update_iface_status(&(adapter->mlmepriv), 0);
++}
++
++void rtw_reset_tdls_info(_adapter *padapter)
++{
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++
++	ptdlsinfo->ap_prohibited = _FALSE;
++
++	/* For TDLS channel switch, currently we only allow it to work in wifi logo test mode */
++	if (padapter->registrypriv.wifi_spec == 1)
++		ptdlsinfo->ch_switch_prohibited = _FALSE;
++	else
++		ptdlsinfo->ch_switch_prohibited = _TRUE;
++
++	rtw_tdls_set_link_established(padapter, _FALSE);
++	ptdlsinfo->sta_cnt = 0;
++	ptdlsinfo->sta_maximum = _FALSE;
++
++#ifdef CONFIG_TDLS_CH_SW
++	ptdlsinfo->chsw_info.ch_sw_state = TDLS_STATE_NONE;
++	ATOMIC_SET(&ptdlsinfo->chsw_info.chsw_on, _FALSE);
++	ptdlsinfo->chsw_info.off_ch_num = 0;
++	ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++	ptdlsinfo->chsw_info.cur_time = 0;
++	ptdlsinfo->chsw_info.delay_switch_back = _FALSE;
++	ptdlsinfo->chsw_info.dump_stack = _FALSE;
++#endif
++
++	ptdlsinfo->ch_sensing = 0;
++	ptdlsinfo->watchdog_count = 0;
++	ptdlsinfo->dev_discovered = _FALSE;
++
++#ifdef CONFIG_WFD
++	ptdlsinfo->wfd_info = &padapter->wfd_info;
++#endif
++
++	ptdlsinfo->tdls_sctx = NULL;
++}
++
++int rtw_init_tdls_info(_adapter *padapter)
++{
++	int	res = _SUCCESS;
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++
++	rtw_reset_tdls_info(padapter);
++
++#ifdef CONFIG_TDLS_DRIVER_SETUP
++	ptdlsinfo->driver_setup = _TRUE;
++#else
++	ptdlsinfo->driver_setup = _FALSE;
++#endif /* CONFIG_TDLS_DRIVER_SETUP */
++
++	_rtw_spinlock_init(&ptdlsinfo->cmd_lock);
++	_rtw_spinlock_init(&ptdlsinfo->hdl_lock);
++
++	return res;
++
++}
++
++void rtw_free_tdls_info(struct tdls_info *ptdlsinfo)
++{
++	_rtw_spinlock_free(&ptdlsinfo->cmd_lock);
++	_rtw_spinlock_free(&ptdlsinfo->hdl_lock);
++
++	_rtw_memset(ptdlsinfo, 0, sizeof(struct tdls_info));
++
++}
++
++void rtw_free_all_tdls_sta(_adapter *padapter, u8 enqueue_cmd)
++{
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++	_irqL	 irqL;
++	_list	*plist, *phead;
++	s32	index;
++	struct sta_info *psta = NULL;
++	struct sta_info *ptdls_sta[NUM_STA];
++	u8 empty_hwaddr[ETH_ALEN] = { 0x00 };
++
++	_rtw_memset(ptdls_sta, 0x00, sizeof(ptdls_sta));
++
++	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++	for (index = 0; index < NUM_STA; index++) {
++		phead = &(pstapriv->sta_hash[index]);
++		plist = get_next(phead);
++
++		while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
++			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++
++			plist = get_next(plist);
++
++			if (psta->tdls_sta_state != TDLS_STATE_NONE)
++				ptdls_sta[index] = psta;
++		}
++	}
++	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++	for (index = 0; index < NUM_STA; index++) {
++		if (ptdls_sta[index]) {
++			struct TDLSoption_param tdls_param;
++
++			psta = ptdls_sta[index];
++
++			RTW_INFO("Do tear down to "MAC_FMT" by enqueue_cmd = %d\n", MAC_ARG(psta->cmn.mac_addr), enqueue_cmd);
++
++			_rtw_memcpy(&(tdls_param.addr), psta->cmn.mac_addr, ETH_ALEN);
++			tdls_param.option = TDLS_TEARDOWN_STA_NO_WAIT;
++			tdls_hdl(padapter, (unsigned char *)&(tdls_param));
++
++			rtw_tdls_teardown_pre_hdl(padapter, psta);
++
++			if (enqueue_cmd == _TRUE)
++				rtw_tdls_cmd(padapter, psta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
++			else
++			 {
++				tdls_param.option = TDLS_TEARDOWN_STA_LOCALLY_POST;
++				tdls_hdl(padapter, (unsigned char *)&(tdls_param));
++			}
++		}
++	}
++}
++
++int check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len)
++{
++	u8 tdls_prohibited_bit = 0x40; /* bit(38); TDLS_prohibited */
++
++	if (pkt_len < 5)
++		return _FALSE;
++
++	pframe += 4;
++	if ((*pframe) & tdls_prohibited_bit)
++		return _TRUE;
++
++	return _FALSE;
++}
++
++int check_ap_tdls_ch_switching_prohibited(u8 *pframe, u8 pkt_len)
++{
++	u8 tdls_ch_swithcing_prohibited_bit = 0x80; /* bit(39); TDLS_channel_switching prohibited */
++
++	if (pkt_len < 5)
++		return _FALSE;
++
++	pframe += 4;
++	if ((*pframe) & tdls_ch_swithcing_prohibited_bit)
++		return _TRUE;
++
++	return _FALSE;
++}
++
++u8 rtw_is_tdls_enabled(_adapter *padapter)
++{
++	return padapter->registrypriv.en_tdls;
++}
++
++void rtw_set_tdls_enable(_adapter *padapter, u8 enable)
++{
++	padapter->registrypriv.en_tdls = enable;
++	RTW_INFO("%s: en_tdls = %d\n", __func__, rtw_is_tdls_enabled(padapter));
++}
++
++void rtw_enable_tdls_func(_adapter *padapter)
++{
++	if (rtw_is_tdls_enabled(padapter) == _TRUE)
++		return;
++
++#if 0
++#ifdef CONFIG_MCC_MODE
++	if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC) == _TRUE) {
++		RTW_INFO("[TDLS] MCC is running, can't enable TDLS !\n");
++		return;
++	}
++#endif
++#endif
++	rtw_set_tdls_enable(padapter, _TRUE);
++}
++
++void rtw_disable_tdls_func(_adapter *padapter, u8 enqueue_cmd)
++{
++	if (rtw_is_tdls_enabled(padapter) == _FALSE)
++		return;
++
++	rtw_free_all_tdls_sta(padapter, enqueue_cmd);
++	rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR);
++	rtw_reset_tdls_info(padapter);
++
++	rtw_set_tdls_enable(padapter, _FALSE);
++}
++
++u8 rtw_is_tdls_sta_existed(_adapter *padapter)
++{
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct sta_info *psta;
++	int i = 0;
++	_irqL irqL;
++	_list	*plist, *phead;
++	u8 ret = _FALSE;
++
++	if (rtw_is_tdls_enabled(padapter) == _FALSE)
++		return _FALSE;
++
++	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++	for (i = 0; i < NUM_STA; i++) {
++		phead = &(pstapriv->sta_hash[i]);
++		plist = get_next(phead);
++		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++			plist = get_next(plist);
++			if (psta->tdls_sta_state != TDLS_STATE_NONE) {
++				ret = _TRUE;
++				goto Exit;
++			}
++		}
++	}
++
++Exit:
++
++	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++	return ret;
++}
++
++u8 rtw_tdls_is_setup_allowed(_adapter *padapter)
++{
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++
++	if (is_client_associated_to_ap(padapter) == _FALSE)
++		return _FALSE;
++
++	if (ptdlsinfo->ap_prohibited == _TRUE)
++		return _FALSE;
++
++	return _TRUE;
++}
++
++#ifdef CONFIG_TDLS_CH_SW
++u8 rtw_tdls_is_chsw_allowed(_adapter *padapter)
++{
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++
++	if (ptdlsinfo->ch_switch_prohibited == _TRUE)
++		return _FALSE;
++
++	if (padapter->registrypriv.wifi_spec == 0)
++		return _FALSE;
++
++	return _TRUE;
++}
++#endif
++
++int _issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ms)
++{
++	int ret = _FAIL;
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl, *qc;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	pattrib->hdrlen += 2;
++	pattrib->qos_en = _TRUE;
++	pattrib->eosp = 1;
++	pattrib->ack_policy = 0;
++	pattrib->mdata = 0;
++	pattrib->retry_ctrl = _FALSE;
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	if (power_mode)
++		SetPwrMgt(fctrl);
++
++	qc = (unsigned short *)(pframe + pattrib->hdrlen - 2);
++
++	SetPriority(qc, 7);	/* Set priority to VO */
++
++	SetEOSP(qc, pattrib->eosp);
++
++	SetAckpolicy(qc, pattrib->ack_policy);
++
++	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos);
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	if (wait_ms)
++		ret = dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, wait_ms);
++	else {
++		dump_mgntframe(padapter, pmgntframe);
++		ret = _SUCCESS;
++	}
++
++exit:
++	return ret;
++
++}
++
++/*
++ *wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
++ *wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
++ *try_cnt means the maximal TX count to try
++ */
++int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms)
++{
++	int ret;
++	int i = 0;
++	systime start = rtw_get_current_time();
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++#if 0
++	psta = rtw_get_stainfo(&padapter->stapriv, da);
++	if (psta) {
++		if (power_mode)
++			rtw_hal_macid_sleep(padapter, psta->cmn.mac_id);
++		else
++			rtw_hal_macid_wakeup(padapter, psta->cmn.mac_id);
++	} else {
++		RTW_INFO(FUNC_ADPT_FMT ": Can't find sta info for " MAC_FMT ", skip macid %s!!\n",
++			FUNC_ADPT_ARG(padapter), MAC_ARG(da), power_mode ? "sleep" : "wakeup");
++		rtw_warn_on(1);
++	}
++#endif
++
++	do {
++		ret = _issue_nulldata_to_TDLS_peer_STA(padapter, da, power_mode, wait_ms);
++
++		i++;
++
++		if (RTW_CANNOT_RUN(padapter))
++			break;
++
++		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
++			rtw_msleep_os(wait_ms);
++
++	} while ((i < try_cnt) && (ret == _FAIL || wait_ms == 0));
++
++	if (ret != _FAIL) {
++		ret = _SUCCESS;
++#ifndef DBG_XMIT_ACK
++		goto exit;
++#endif
++	}
++
++	if (try_cnt && wait_ms) {
++		if (da)
++			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
++				FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
++				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
++		else
++			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
++				FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
++				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
++	}
++exit:
++	return ret;
++}
++
++/* TDLS encryption(if needed) will always be CCMP */
++void rtw_tdls_set_key(_adapter *padapter, struct sta_info *ptdls_sta)
++{
++	ptdls_sta->dot118021XPrivacy = _AES_;
++	rtw_setstakey_cmd(padapter, ptdls_sta, TDLS_KEY, _TRUE);
++}
++
++#ifdef CONFIG_80211N_HT
++void rtw_tdls_process_ht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)
++{
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct ht_priv			*phtpriv = &pmlmepriv->htpriv;
++	u8	max_AMPDU_len, min_MPDU_spacing;
++	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0;
++
++	/* Save HT capabilities in the sta object */
++	_rtw_memset(&ptdls_sta->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap));
++	if (data && Length >= sizeof(struct rtw_ieee80211_ht_cap)) {
++		ptdls_sta->flags |= WLAN_STA_HT;
++		ptdls_sta->flags |= WLAN_STA_WME;
++
++		_rtw_memcpy(&ptdls_sta->htpriv.ht_cap, data, sizeof(struct rtw_ieee80211_ht_cap));
++	} else {
++		ptdls_sta->flags &= ~WLAN_STA_HT;
++		return;
++	}
++
++	if (ptdls_sta->flags & WLAN_STA_HT) {
++		if (padapter->registrypriv.ht_enable == _TRUE && is_supported_ht(padapter->registrypriv.wireless_mode) ) {
++			ptdls_sta->htpriv.ht_option = _TRUE;
++			ptdls_sta->qos_option = _TRUE;
++		} else {
++			ptdls_sta->htpriv.ht_option = _FALSE;
++			ptdls_sta->qos_option = _FALSE;
++		}
++	}
++
++	/* HT related cap */
++	if (ptdls_sta->htpriv.ht_option) {
++		/* Check if sta supports rx ampdu */
++		if (padapter->registrypriv.ampdu_enable == 1)
++			ptdls_sta->htpriv.ampdu_enable = _TRUE;
++
++		/* AMPDU Parameters field */
++		/* Get MIN of MAX AMPDU Length Exp */
++		if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3) > (data[2] & 0x3))
++			max_AMPDU_len = (data[2] & 0x3);
++		else
++			max_AMPDU_len = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3);
++		/* Get MAX of MIN MPDU Start Spacing */
++		if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) > (data[2] & 0x1c))
++			min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c);
++		else
++			min_MPDU_spacing = (data[2] & 0x1c);
++		ptdls_sta->htpriv.rx_ampdu_min_spacing = max_AMPDU_len | min_MPDU_spacing;
++
++		/* Check if sta support s Short GI 20M */
++		if ((phtpriv->sgi_20m == _TRUE) && (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_20)))
++			ptdls_sta->htpriv.sgi_20m = _TRUE;
++
++		/* Check if sta support s Short GI 40M */
++		if ((phtpriv->sgi_40m == _TRUE) && (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)))
++			ptdls_sta->htpriv.sgi_40m = _TRUE;
++
++		/* Bwmode would still followed AP's setting */
++		if (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH)) {
++			if (padapter->mlmeextpriv.cur_bwmode >= CHANNEL_WIDTH_40)
++				ptdls_sta->cmn.bw_mode = CHANNEL_WIDTH_40;
++			ptdls_sta->htpriv.ch_offset = padapter->mlmeextpriv.cur_ch_offset;
++		}
++
++		/* Config LDPC Coding Capability */
++		if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX) && GET_HT_CAP_ELE_LDPC_CAP(data)) {
++			SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX));
++			RTW_INFO("Enable HT Tx LDPC!\n");
++		}
++		ptdls_sta->htpriv.ldpc_cap = cur_ldpc_cap;
++
++		/* Config STBC setting */
++		if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(data)) {
++			SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX));
++			RTW_INFO("Enable HT Tx STBC!\n");
++		}
++		ptdls_sta->htpriv.stbc_cap = cur_stbc_cap;
++
++#ifdef CONFIG_BEAMFORMING
++		/* Config Tx beamforming setting */
++		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
++		    GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(data))
++			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
++
++		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
++		    GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(data))
++			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
++		ptdls_sta->htpriv.beamform_cap = cur_beamform_cap;
++		if (cur_beamform_cap)
++			RTW_INFO("Client HT Beamforming Cap = 0x%02X\n", cur_beamform_cap);
++#endif /* CONFIG_BEAMFORMING */
++	}
++
++}
++
++u8 *rtw_tdls_set_ht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
++{
++	rtw_ht_use_default_setting(padapter);
++
++	if (padapter->registrypriv.wifi_spec == 1) {
++		padapter->mlmepriv.htpriv.sgi_20m = _FALSE;
++		padapter->mlmepriv.htpriv.sgi_40m = _FALSE;
++	}
++
++	rtw_restructure_ht_ie(padapter, NULL, pframe, 0, &(pattrib->pktlen), padapter->mlmeextpriv.cur_channel);
++
++	return pframe + pattrib->pktlen;
++}
++#endif
++
++#ifdef CONFIG_80211AC_VHT
++void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct vht_priv			*pvhtpriv = &pmlmepriv->vhtpriv;
++	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0, tx_nss = 0;
++	u16 cur_beamform_cap = 0;
++	u8	*pcap_mcs;
++
++	_rtw_memset(&ptdls_sta->vhtpriv, 0, sizeof(struct vht_priv));
++	if (data && Length == 12) {
++		ptdls_sta->flags |= WLAN_STA_VHT;
++
++		_rtw_memcpy(ptdls_sta->vhtpriv.vht_cap, data, 12);
++
++#if 0
++		if (elems.vht_op_mode_notify && elems.vht_op_mode_notify_len == 1)
++			_rtw_memcpy(&pstat->vhtpriv.vht_op_mode_notify, elems.vht_op_mode_notify, 1);
++		else /* for Frame without Operating Mode notify ie; default: 80M */
++			pstat->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80;
++#else
++		ptdls_sta->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80;
++#endif
++	} else {
++		ptdls_sta->flags &= ~WLAN_STA_VHT;
++		return;
++	}
++
++	if (ptdls_sta->flags & WLAN_STA_VHT) {
++		if (REGSTY_IS_11AC_ENABLE(&padapter->registrypriv)
++		    && is_supported_vht(padapter->registrypriv.wireless_mode)
++		    && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))) {
++			ptdls_sta->vhtpriv.vht_option = _TRUE;
++			ptdls_sta->cmn.ra_info.is_vht_enable = _TRUE;
++		}
++		else
++			ptdls_sta->vhtpriv.vht_option = _FALSE;
++	}
++
++	/* B4 Rx LDPC */
++	if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
++	    GET_VHT_CAPABILITY_ELE_RX_LDPC(data)) {
++		SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
++		RTW_INFO("Current VHT LDPC Setting = %02X\n", cur_ldpc_cap);
++	}
++	ptdls_sta->vhtpriv.ldpc_cap = cur_ldpc_cap;
++
++	/* B5 Short GI for 80 MHz */
++	ptdls_sta->vhtpriv.sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(data) & pvhtpriv->sgi_80m) ? _TRUE : _FALSE;
++
++	/* B8 B9 B10 Rx STBC */
++	if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX) &&
++	    GET_VHT_CAPABILITY_ELE_RX_STBC(data)) {
++		SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
++		RTW_INFO("Current VHT STBC Setting = %02X\n", cur_stbc_cap);
++	}
++	ptdls_sta->vhtpriv.stbc_cap = cur_stbc_cap;
++
++	#ifdef CONFIG_BEAMFORMING
++	/* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */
++	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
++	    GET_VHT_CAPABILITY_ELE_SU_BFEE(data))
++		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
++
++	/* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */
++	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
++	    GET_VHT_CAPABILITY_ELE_SU_BFER(data))
++		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
++	ptdls_sta->vhtpriv.beamform_cap = cur_beamform_cap;
++	ptdls_sta->cmn.bf_info.vht_beamform_cap = cur_beamform_cap;
++	if (cur_beamform_cap)
++		RTW_INFO("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap);
++	#endif /*CONFIG_BEAMFORMING*/
++
++	/* B23 B24 B25 Maximum A-MPDU Length Exponent */
++	ptdls_sta->vhtpriv.ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(data);
++
++	pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(data);
++	tx_nss = GET_HAL_TX_NSS(padapter);
++	rtw_vht_nss_to_mcsmap(tx_nss, ptdls_sta->vhtpriv.vht_mcs_map, pcap_mcs);
++	ptdls_sta->vhtpriv.vht_highest_rate = rtw_get_vht_highest_rate(ptdls_sta->vhtpriv.vht_mcs_map);
++}
++
++void rtw_tdls_process_vht_operation(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)
++{
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct registry_priv *regsty = adapter_to_regsty(padapter);
++	u8 operation_bw = 0;
++
++	if (GET_VHT_OPERATION_ELE_CHL_WIDTH(data) >= 1) {
++
++		operation_bw = CHANNEL_WIDTH_80;
++
++		if (hal_is_bw_support(padapter, operation_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, operation_bw)
++			&& (operation_bw <= pmlmeext->cur_bwmode))
++			ptdls_sta->cmn.bw_mode = operation_bw;
++		else
++			ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode;
++	} else
++		ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode;
++}
++
++void rtw_tdls_process_vht_op_mode_notify(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)
++{
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct registry_priv *regsty = adapter_to_regsty(padapter);
++	u8	target_bw;
++	u8	target_rxss, current_rxss;
++
++	if (pvhtpriv->vht_option == _FALSE)
++		return;
++
++	target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(data);
++	target_rxss = (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(data) + 1);
++
++	if (hal_is_bw_support(padapter, target_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw)
++		&& (target_bw <= pmlmeext->cur_bwmode))
++		ptdls_sta->cmn.bw_mode = target_bw;
++	else
++		ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode;
++
++	current_rxss = rtw_vht_mcsmap_to_nss(ptdls_sta->vhtpriv.vht_mcs_map);
++	if (target_rxss != current_rxss) {
++		u8	vht_mcs_map[2] = {};
++
++		rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, ptdls_sta->vhtpriv.vht_mcs_map);
++		_rtw_memcpy(ptdls_sta->vhtpriv.vht_mcs_map, vht_mcs_map, 2);
++	}
++}
++
++u8 *rtw_tdls_set_aid(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
++{
++	return rtw_set_ie(pframe, EID_AID, 2, (u8 *)&(padapter->mlmepriv.cur_network.aid), &(pattrib->pktlen));
++}
++
++u8 *rtw_tdls_set_vht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
++{
++	u32 ie_len = 0;
++
++	rtw_vht_use_default_setting(padapter);
++
++	ie_len = rtw_build_vht_cap_ie(padapter, pframe);
++	pattrib->pktlen += ie_len;
++
++	return pframe + ie_len;
++}
++
++u8 *rtw_tdls_set_vht_operation(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib, u8 channel)
++{
++	u32 ie_len = 0;
++
++	ie_len = rtw_build_vht_operation_ie(padapter, pframe, channel);
++	pattrib->pktlen += ie_len;
++
++	return pframe + ie_len;
++}
++
++u8 *rtw_tdls_set_vht_op_mode_notify(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib, u8 bw)
++{
++	u32 ie_len = 0;
++
++	ie_len = rtw_build_vht_op_mode_notify_ie(padapter, pframe, bw);
++	pattrib->pktlen += ie_len;
++
++	return pframe + ie_len;
++}
++#endif
++
++
++u8 *rtw_tdls_set_sup_ch(_adapter *adapter, u8 *pframe, struct pkt_attrib *pattrib)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	u8 sup_ch[30 * 2] = {0x00}, ch_set_idx = 0, sup_ch_idx = 2;
++
++	while (ch_set_idx < rfctl->max_chan_nums && rfctl->channel_set[ch_set_idx].ChannelNum != 0) {
++		if (rfctl->channel_set[ch_set_idx].ChannelNum <= 14) {
++			/* TODO: fix 2.4G supported channel when channel doesn't start from 1 and continuous */
++			sup_ch[0] = 1;	/* First channel number */
++			sup_ch[1] = rfctl->channel_set[ch_set_idx].ChannelNum;	/* Number of channel */
++		} else {
++			sup_ch[sup_ch_idx++] = rfctl->channel_set[ch_set_idx].ChannelNum;
++			sup_ch[sup_ch_idx++] = 1;
++		}
++		ch_set_idx++;
++	}
++
++	return rtw_set_ie(pframe, _SUPPORTED_CH_IE_, sup_ch_idx, sup_ch, &(pattrib->pktlen));
++}
++
++u8 *rtw_tdls_set_rsnie(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib *pattrib,  int init, struct sta_info *ptdls_sta)
++{
++	u8 *p = NULL;
++	int len = 0;
++
++	if (ptxmgmt->len > 0)
++		p = rtw_get_ie(ptxmgmt->buf, _RSN_IE_2_, &len, ptxmgmt->len);
++
++	if (p != NULL)
++		return rtw_set_ie(pframe, _RSN_IE_2_, len, p + 2, &(pattrib->pktlen));
++	else if (init == _TRUE)
++		return rtw_set_ie(pframe, _RSN_IE_2_, sizeof(TDLS_RSNIE), TDLS_RSNIE, &(pattrib->pktlen));
++	else
++		return rtw_set_ie(pframe, _RSN_IE_2_, sizeof(ptdls_sta->TDLS_RSNIE), ptdls_sta->TDLS_RSNIE, &(pattrib->pktlen));
++}
++
++u8 *rtw_tdls_set_ext_cap(u8 *pframe, struct pkt_attrib *pattrib)
++{
++	return rtw_set_ie(pframe, _EXT_CAP_IE_ , sizeof(TDLS_EXT_CAPIE), TDLS_EXT_CAPIE, &(pattrib->pktlen));
++}
++
++u8 *rtw_tdls_set_qos_cap(u8 *pframe, struct pkt_attrib *pattrib)
++{
++	return rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, sizeof(TDLS_WMMIE), TDLS_WMMIE,  &(pattrib->pktlen));
++}
++
++u8 *rtw_tdls_set_ftie(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib *pattrib, u8 *ANonce, u8 *SNonce)
++{
++	struct wpa_tdls_ftie FTIE = {0};
++	u8 *p = NULL;
++	int len = 0;
++
++	if (ptxmgmt->len > 0)
++		p = rtw_get_ie(ptxmgmt->buf, _FTIE_, &len, ptxmgmt->len);
++
++	if (p != NULL)
++		return rtw_set_ie(pframe, _FTIE_, len, p + 2, &(pattrib->pktlen));
++	else {
++		if (ANonce != NULL)
++			_rtw_memcpy(FTIE.Anonce, ANonce, WPA_NONCE_LEN);
++		if (SNonce != NULL)
++			_rtw_memcpy(FTIE.Snonce, SNonce, WPA_NONCE_LEN);
++
++		return rtw_set_ie(pframe, _FTIE_, TDLS_FTIE_DATA_LEN,
++						  (u8 *)FTIE.data, &(pattrib->pktlen));
++	}
++}
++
++u8 *rtw_tdls_set_timeout_interval(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib *pattrib, int init, struct sta_info *ptdls_sta)
++{
++	u8 timeout_itvl[5];	/* set timeout interval to maximum value */
++	u32 timeout_interval = TDLS_TPK_RESEND_COUNT;
++	u8 *p = NULL;
++	int len = 0;
++
++	if (ptxmgmt->len > 0)
++		p = rtw_get_ie(ptxmgmt->buf, _TIMEOUT_ITVL_IE_, &len, ptxmgmt->len);
++
++	if (p != NULL)
++		return rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, len, p + 2, &(pattrib->pktlen));
++	else {
++		/* Timeout interval */
++		timeout_itvl[0] = 0x02;
++		if (init == _TRUE)
++			_rtw_memcpy(timeout_itvl + 1, &timeout_interval, 4);
++		else
++			_rtw_memcpy(timeout_itvl + 1, (u8 *)(&ptdls_sta->TDLS_PeerKey_Lifetime), 4);
++
++		return rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen));
++	}
++}
++
++u8 *rtw_tdls_set_bss_coexist(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
++{
++	u8 iedata = 0;
++
++	if (padapter->mlmepriv.num_FortyMHzIntolerant > 0)
++		iedata |= BIT(2);	/* 20 MHz BSS Width Request */
++
++	/* Information Bit should be set by TDLS test plan 5.9 */
++	iedata |= BIT(0);
++	return rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen));
++}
++
++u8 *rtw_tdls_set_payload_type(u8 *pframe, struct pkt_attrib *pattrib)
++{
++	u8 payload_type = 0x02;
++	return rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen));
++}
++
++u8 *rtw_tdls_set_category(u8 *pframe, struct pkt_attrib *pattrib, u8 category)
++{
++	return rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++}
++
++u8 *rtw_tdls_set_action(u8 *pframe, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt)
++{
++	return rtw_set_fixed_ie(pframe, 1, &(ptxmgmt->action_code), &(pattrib->pktlen));
++}
++
++u8 *rtw_tdls_set_status_code(u8 *pframe, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt)
++{
++	return rtw_set_fixed_ie(pframe, 2, (u8 *)&(ptxmgmt->status_code), &(pattrib->pktlen));
++}
++
++u8 *rtw_tdls_set_dialog(u8 *pframe, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt)
++{
++	u8 dialogtoken = 1;
++	if (ptxmgmt->dialog_token)
++		return rtw_set_fixed_ie(pframe, 1, &(ptxmgmt->dialog_token), &(pattrib->pktlen));
++	else
++		return rtw_set_fixed_ie(pframe, 1, &(dialogtoken), &(pattrib->pktlen));
++}
++
++u8 *rtw_tdls_set_reg_class(u8 *pframe, struct pkt_attrib *pattrib, struct sta_info *ptdls_sta)
++{
++	u8 reg_class = 22;
++	return rtw_set_fixed_ie(pframe, 1, &(reg_class), &(pattrib->pktlen));
++}
++
++u8 *rtw_tdls_set_second_channel_offset(u8 *pframe, struct pkt_attrib *pattrib, u8 ch_offset)
++{
++	return rtw_set_ie(pframe, EID_SecondaryChnlOffset , 1, &ch_offset, &(pattrib->pktlen));
++}
++
++u8 *rtw_tdls_set_capability(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
++{
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &pmlmeext->mlmext_info;
++	u8 cap_from_ie[2] = {0};
++
++	_rtw_memcpy(cap_from_ie, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2);
++
++	return rtw_set_fixed_ie(pframe, 2, cap_from_ie, &(pattrib->pktlen));
++}
++
++u8 *rtw_tdls_set_supported_rate(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
++{
++	u8 bssrate[NDIS_802_11_LENGTH_RATES_EX];
++	int bssrate_len = 0;
++	u8 more_supportedrates = 0;
++
++	rtw_set_supported_rate(bssrate, (padapter->registrypriv.wireless_mode == WIRELESS_MODE_MAX) ? padapter->mlmeextpriv.cur_wireless_mode : padapter->registrypriv.wireless_mode);
++	bssrate_len = rtw_get_rateset_len(bssrate);
++
++	if (bssrate_len > 8) {
++		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen));
++		more_supportedrates = 1;
++	} else
++		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));
++
++	/* extended supported rates */
++	if (more_supportedrates == 1)
++		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen));
++
++	return pframe;
++}
++
++u8 *rtw_tdls_set_sup_reg_class(u8 *pframe, struct pkt_attrib *pattrib)
++{
++	return rtw_set_ie(pframe, _SRC_IE_ , sizeof(TDLS_SRC), TDLS_SRC, &(pattrib->pktlen));
++}
++
++u8 *rtw_tdls_set_linkid(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib, u8 init)
++{
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	u8 link_id_addr[18] = {0};
++
++	_rtw_memcpy(link_id_addr, get_my_bssid(&(pmlmeinfo->network)), 6);
++
++	if (init == _TRUE) {
++		_rtw_memcpy((link_id_addr + 6), pattrib->src, 6);
++		_rtw_memcpy((link_id_addr + 12), pattrib->dst, 6);
++	} else {
++		_rtw_memcpy((link_id_addr + 6), pattrib->dst, 6);
++		_rtw_memcpy((link_id_addr + 12), pattrib->src, 6);
++	}
++	return rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen));
++}
++
++#ifdef CONFIG_TDLS_CH_SW
++u8 *rtw_tdls_set_target_ch(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
++{
++	u8 target_ch = 1;
++	if (padapter->tdlsinfo.chsw_info.off_ch_num)
++		return rtw_set_fixed_ie(pframe, 1, &(padapter->tdlsinfo.chsw_info.off_ch_num), &(pattrib->pktlen));
++	else
++		return rtw_set_fixed_ie(pframe, 1, &(target_ch), &(pattrib->pktlen));
++}
++
++u8 *rtw_tdls_set_ch_sw(u8 *pframe, struct pkt_attrib *pattrib, struct sta_info *ptdls_sta)
++{
++	u8 ch_switch_timing[4] = {0};
++	u16 switch_time = (ptdls_sta->ch_switch_time >= TDLS_CH_SWITCH_TIME * 1000) ?
++			  ptdls_sta->ch_switch_time : TDLS_CH_SWITCH_TIME;
++	u16 switch_timeout = (ptdls_sta->ch_switch_timeout >= TDLS_CH_SWITCH_TIMEOUT * 1000) ?
++		     ptdls_sta->ch_switch_timeout : TDLS_CH_SWITCH_TIMEOUT;
++
++	_rtw_memcpy(ch_switch_timing, &switch_time, 2);
++	_rtw_memcpy(ch_switch_timing + 2, &switch_timeout, 2);
++
++	return rtw_set_ie(pframe, _CH_SWITCH_TIMING_,  4, ch_switch_timing, &(pattrib->pktlen));
++}
++
++void rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++	if (enable == _TRUE) {
++#ifdef CONFIG_TDLS_CH_SW_V2
++		pHalData->ch_switch_offload = _TRUE;
++#endif
++
++#ifdef CONFIG_TDLS_CH_SW_BY_DRV
++		pHalData->ch_switch_offload = _FALSE;
++#endif
++	}
++	else
++		pHalData->ch_switch_offload = _FALSE;
++	
++	if (ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on) != enable)
++		ATOMIC_SET(&padapter->tdlsinfo.chsw_info.chsw_on, enable);
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_BCN_EARLY_C2H_RPT, &enable);
++	RTW_INFO("[TDLS] %s Bcn Early C2H Report\n", (enable == _TRUE) ? "Start" : "Stop");
++}
++
++void rtw_tdls_ch_sw_back_to_base_chnl(_adapter *padapter)
++{
++	struct mlme_priv *pmlmepriv;
++	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
++
++	pmlmepriv = &padapter->mlmepriv;
++
++	if ((ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) &&
++	    (padapter->mlmeextpriv.cur_channel != rtw_get_oper_ch(padapter)))
++		rtw_tdls_cmd(padapter, pchsw_info->addr, TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED);
++}
++
++static void rtw_tdls_chsw_oper_init(_adapter *padapter, u32 timeout_ms)
++{
++	struct submit_ctx	*chsw_sctx = &padapter->tdlsinfo.chsw_info.chsw_sctx;
++
++	rtw_sctx_init(chsw_sctx, timeout_ms);
++}
++
++static int rtw_tdls_chsw_oper_wait(_adapter *padapter)
++{
++	struct submit_ctx	*chsw_sctx = &padapter->tdlsinfo.chsw_info.chsw_sctx;
++
++	return rtw_sctx_wait(chsw_sctx, __func__);
++}
++
++void rtw_tdls_chsw_oper_done(_adapter *padapter)
++{
++	struct submit_ctx	*chsw_sctx = &padapter->tdlsinfo.chsw_info.chsw_sctx;
++
++	rtw_sctx_done(&chsw_sctx);
++}
++
++s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_type, u8 channel, u8 channel_offset, u16 bwmode, u16 ch_switch_time)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++	u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++	u32 ch_sw_time_start, ch_sw_time_spent, wait_time;
++	u8 take_care_iqk;
++	s32 ret = _FAIL;
++
++	ch_sw_time_start = rtw_systime_to_ms(rtw_get_current_time());
++
++	/* set mac_id sleep before channel switch */
++	rtw_hal_macid_sleep(padapter, ptdls_sta->cmn.mac_id);
++
++#if defined(CONFIG_TDLS_CH_SW_BY_DRV) || defined(CONFIG_TDLS_CH_SW_V2)
++	set_channel_bwmode(padapter, channel, channel_offset, bwmode);
++	ret = _SUCCESS;
++#else
++	rtw_tdls_chsw_oper_init(padapter, TDLS_CH_SWITCH_OPER_OFFLOAD_TIMEOUT);
++
++	/* channel switch IOs offload to FW */
++	if (rtw_hal_ch_sw_oper_offload(padapter, channel, channel_offset, bwmode) == _SUCCESS) {
++		if (rtw_tdls_chsw_oper_wait(padapter) == _SUCCESS) {
++			/* set channel and bw related variables in driver */
++			_enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
++
++			rtw_set_oper_ch(padapter, channel);
++			rtw_set_oper_choffset(padapter, channel_offset);
++			rtw_set_oper_bw(padapter, bwmode);
++
++			center_ch = rtw_get_center_ch(channel, bwmode, channel_offset);
++			pHalData->current_channel = center_ch;
++			pHalData->CurrentCenterFrequencyIndex1 = center_ch;
++			pHalData->current_channel_bw = bwmode;
++			pHalData->nCur40MhzPrimeSC = channel_offset;
++
++			if (bwmode == CHANNEL_WIDTH_80) {
++				if (center_ch > channel)
++					chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
++				else if (center_ch < channel)
++					chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
++				else
++					chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++			}
++			pHalData->nCur80MhzPrimeSC = chnl_offset80;
++
++			pHalData->CurrentCenterFrequencyIndex1 = center_ch;
++
++			_exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
++
++			rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
++			if (take_care_iqk == _TRUE)
++				rtw_hal_ch_sw_iqk_info_restore(padapter, CH_SW_USE_CASE_TDLS);
++
++			ret = _SUCCESS;
++		} else
++			RTW_INFO("[TDLS] chsw oper wait fail !!\n");
++	}
++#endif
++
++	if (ret == _SUCCESS) {
++		ch_sw_time_spent = rtw_systime_to_ms(rtw_get_current_time()) - ch_sw_time_start;
++		if (chnl_type == TDLS_CH_SW_OFF_CHNL) {
++			if ((u32)ch_switch_time / 1000 > ch_sw_time_spent)
++				wait_time = (u32)ch_switch_time / 1000 - ch_sw_time_spent;
++			else
++				wait_time = 0;
++
++			if (wait_time > 0)
++				rtw_msleep_os(wait_time);
++		}
++	}
++
++	/* set mac_id wakeup after channel switch */
++	rtw_hal_macid_wakeup(padapter, ptdls_sta->cmn.mac_id);
++
++	return ret;
++}
++#endif
++
++u8 *rtw_tdls_set_wmm_params(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
++{
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8 wmm_param_ele[24] = {0};
++
++	if (&pmlmeinfo->WMM_param) {
++		_rtw_memcpy(wmm_param_ele, WMM_PARA_OUI, 6);
++		if (_rtw_memcmp(&pmlmeinfo->WMM_param, &wmm_param_ele[6], 18) == _TRUE)
++			/* Use default WMM Param */
++			_rtw_memcpy(wmm_param_ele + 6, (u8 *)&TDLS_WMM_PARAM_IE, sizeof(TDLS_WMM_PARAM_IE));
++		else
++			_rtw_memcpy(wmm_param_ele + 6, (u8 *)&pmlmeinfo->WMM_param, sizeof(pmlmeinfo->WMM_param));
++		return rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_,  24, wmm_param_ele, &(pattrib->pktlen));
++	} else
++		return pframe;
++}
++
++#ifdef CONFIG_WFD
++void rtw_tdls_process_wfd_ie(struct tdls_info *ptdlsinfo, u8 *ptr, u8 length)
++{
++	u8 *wfd_ie;
++	u32	wfd_ielen = 0;
++
++	if (!hal_chk_wl_func(tdls_info_to_adapter(ptdlsinfo), WL_FUNC_MIRACAST))
++		return;
++
++	/* Try to get the TCP port information when receiving the negotiation response. */
++
++	wfd_ie = rtw_get_wfd_ie(ptr, length, NULL, &wfd_ielen);
++	while (wfd_ie) {
++		u8 *attr_content;
++		u32	attr_contentlen = 0;
++		int	i;
++
++		RTW_INFO("[%s] WFD IE Found!!\n", __FUNCTION__);
++		attr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen);
++		if (attr_content && attr_contentlen) {
++			ptdlsinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16(attr_content + 2);
++			RTW_INFO("[%s] Peer PORT NUM = %d\n", __FUNCTION__, ptdlsinfo->wfd_info->peer_rtsp_ctrlport);
++		}
++
++		attr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_LOCAL_IP_ADDR, NULL, &attr_contentlen);
++		if (attr_content && attr_contentlen) {
++			_rtw_memcpy(ptdlsinfo->wfd_info->peer_ip_address, (attr_content + 1), 4);
++			RTW_INFO("[%s] Peer IP = %02u.%02u.%02u.%02u\n", __FUNCTION__,
++				ptdlsinfo->wfd_info->peer_ip_address[0], ptdlsinfo->wfd_info->peer_ip_address[1],
++				ptdlsinfo->wfd_info->peer_ip_address[2], ptdlsinfo->wfd_info->peer_ip_address[3]);
++		}
++
++		wfd_ie = rtw_get_wfd_ie(wfd_ie + wfd_ielen, (ptr + length) - (wfd_ie + wfd_ielen), NULL, &wfd_ielen);
++	}
++}
++
++int issue_tunneled_probe_req(_adapter *padapter)
++{
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	u8 baddr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	struct tdls_txmgmt txmgmt;
++	int ret = _FAIL;
++
++	RTW_INFO("[%s]\n", __FUNCTION__);
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++	txmgmt.action_code = TUNNELED_PROBE_REQ;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	pattrib = &pmgntframe->attrib;
++
++	pmgntframe->frame_tag = DATA_FRAMETAG;
++	pattrib->ether_type = 0x890d;
++
++	_rtw_memcpy(pattrib->dst, baddr, ETH_ALEN);
++	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
++	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++	update_tdls_attrib(padapter, pattrib);
++	pattrib->qsel = pattrib->priority;
++	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) {
++		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++		rtw_free_xmitframe(pxmitpriv, pmgntframe);
++		goto exit;
++	}
++	dump_mgntframe(padapter, pmgntframe);
++	ret = _SUCCESS;
++exit:
++
++	return ret;
++}
++
++int issue_tunneled_probe_rsp(_adapter *padapter, union recv_frame *precv_frame)
++{
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct tdls_txmgmt txmgmt;
++	int ret = _FAIL;
++
++	RTW_INFO("[%s]\n", __FUNCTION__);
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++	txmgmt.action_code = TUNNELED_PROBE_RSP;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	pattrib = &pmgntframe->attrib;
++
++	pmgntframe->frame_tag = DATA_FRAMETAG;
++	pattrib->ether_type = 0x890d;
++
++	_rtw_memcpy(pattrib->dst, precv_frame->u.hdr.attrib.src, ETH_ALEN);
++	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
++	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++	update_tdls_attrib(padapter, pattrib);
++	pattrib->qsel = pattrib->priority;
++	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) {
++		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++		rtw_free_xmitframe(pxmitpriv, pmgntframe);
++		goto exit;
++	}
++	dump_mgntframe(padapter, pmgntframe);
++	ret = _SUCCESS;
++exit:
++
++	return ret;
++}
++#endif /* CONFIG_WFD */
++
++int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack)
++{
++	struct tdls_info	*ptdlsinfo = &padapter->tdlsinfo;
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct sta_info *ptdls_sta = NULL;
++	_irqL irqL;
++	int ret = _FAIL;
++	/* Retry timer should be set at least 301 sec, using TPK_count counting 301 times. */
++	u32 timeout_interval = TDLS_TPK_RESEND_COUNT;
++
++	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
++
++	if (rtw_tdls_is_setup_allowed(padapter) == _FALSE)
++		goto exit;
++
++	if (IS_MCAST(ptxmgmt->peer))
++		goto exit;
++
++	ptdls_sta = rtw_get_stainfo(pstapriv, ptxmgmt->peer);
++	if (ptdlsinfo->sta_maximum == _TRUE) {
++		if (ptdls_sta == NULL)
++			goto exit;
++		else if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE))
++			goto exit;
++	}
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	if (ptdls_sta == NULL) {
++		ptdls_sta = rtw_alloc_stainfo(pstapriv, ptxmgmt->peer);
++		if (ptdls_sta == NULL) {
++			RTW_INFO("[%s] rtw_alloc_stainfo fail\n", __FUNCTION__);
++			rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++			rtw_free_xmitframe(pxmitpriv, pmgntframe);
++			goto exit;
++		}
++		ptdlsinfo->sta_cnt++;
++	}
++
++	ptxmgmt->action_code = TDLS_SETUP_REQUEST;
++
++	pattrib = &pmgntframe->attrib;
++	pmgntframe->frame_tag = DATA_FRAMETAG;
++	pattrib->ether_type = 0x890d;
++
++	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
++	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
++	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++	update_tdls_attrib(padapter, pattrib);
++
++	if (ptdlsinfo->sta_cnt == MAX_ALLOWED_TDLS_STA_NUM)
++		ptdlsinfo->sta_maximum  = _TRUE;
++
++	ptdls_sta->tdls_sta_state |= TDLS_RESPONDER_STATE;
++
++	if (rtw_tdls_is_driver_setup(padapter) == _TRUE) {
++		ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval;
++		_set_timer(&ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME);
++	}
++
++	pattrib->qsel = pattrib->priority;
++
++	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
++		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++		rtw_free_xmitframe(pxmitpriv, pmgntframe);
++		goto exit;
++	}
++
++	if (wait_ack)
++		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
++	else {
++		dump_mgntframe(padapter, pmgntframe);
++		ret = _SUCCESS;
++	}
++
++exit:
++
++	return ret;
++}
++
++int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta, u8 wait_ack)
++{
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	_irqL irqL;
++	int ret = _FAIL;
++
++	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
++
++	ptxmgmt->action_code = TDLS_TEARDOWN;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	rtw_mi_set_scan_deny(padapter, 550);
++	rtw_mi_scan_abort(padapter, _TRUE);
++
++	pattrib = &pmgntframe->attrib;
++
++	pmgntframe->frame_tag = DATA_FRAMETAG;
++	pattrib->ether_type = 0x890d;
++
++	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
++	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
++
++	if (ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_)
++		_rtw_memcpy(pattrib->ra, ptxmgmt->peer, ETH_ALEN);
++	else
++		_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
++
++	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++	update_tdls_attrib(padapter, pattrib);
++	pattrib->qsel = pattrib->priority;
++	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
++		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++		rtw_free_xmitframe(pxmitpriv, pmgntframe);
++		goto exit;
++	}
++
++	if (rtw_tdls_is_driver_setup(padapter) == _TRUE)
++		if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)
++			if (pattrib->encrypt)
++				_cancel_timer_ex(&ptdls_sta->TPK_timer);
++
++	if (wait_ack)
++		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
++	else {
++		dump_mgntframe(padapter, pmgntframe);
++		ret = _SUCCESS;
++	}
++
++exit:
++
++	return ret;
++}
++
++int issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait_ack)
++{
++	struct sta_info *ptdls_sta = NULL;
++	int ret = _FAIL;
++
++	ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), ptxmgmt->peer);
++	if (ptdls_sta == NULL) {
++		RTW_INFO("No tdls_sta for tearing down\n");
++		goto exit;
++	}
++
++	ret = _issue_tdls_teardown(padapter, ptxmgmt, ptdls_sta, wait_ack);
++	if ((ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_) && (ret == _FAIL)) {
++		/* Change status code and send teardown again via AP */
++		ptxmgmt->status_code = _RSON_TDLS_TEAR_TOOFAR_;
++		ret = _issue_tdls_teardown(padapter, ptxmgmt, ptdls_sta, wait_ack);
++	}
++
++	if (rtw_tdls_is_driver_setup(padapter)) {
++		rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
++		rtw_tdls_cmd(padapter, ptxmgmt->peer, TDLS_TEARDOWN_STA_LOCALLY_POST);
++	}
++
++exit:
++	return ret;
++}
++
++int issue_tdls_dis_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt)
++{
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	int ret = _FAIL;
++
++	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
++
++	ptxmgmt->action_code = TDLS_DISCOVERY_REQUEST;
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	pattrib = &pmgntframe->attrib;
++	pmgntframe->frame_tag = DATA_FRAMETAG;
++	pattrib->ether_type = 0x890d;
++
++	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
++	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
++	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++	update_tdls_attrib(padapter, pattrib);
++	pattrib->qsel = pattrib->priority;
++	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
++		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++		rtw_free_xmitframe(pxmitpriv, pmgntframe);
++		goto exit;
++	}
++	dump_mgntframe(padapter, pmgntframe);
++	RTW_INFO("issue tdls dis req\n");
++
++	ret = _SUCCESS;
++exit:
++
++	return ret;
++}
++
++int issue_tdls_setup_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt)
++{
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	int ret = _FAIL;
++
++	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
++
++	ptxmgmt->action_code = TDLS_SETUP_RESPONSE;
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	pattrib = &pmgntframe->attrib;
++	pmgntframe->frame_tag = DATA_FRAMETAG;
++	pattrib->ether_type = 0x890d;
++
++	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
++	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pattrib->ra, get_bssid(&(padapter->mlmepriv)), ETH_ALEN);
++	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++	update_tdls_attrib(padapter, pattrib);
++	pattrib->qsel = pattrib->priority;
++	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
++		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++		rtw_free_xmitframe(pxmitpriv, pmgntframe);
++		goto exit;
++	}
++
++	dump_mgntframe(padapter, pmgntframe);
++
++	ret = _SUCCESS;
++exit:
++
++	return ret;
++
++}
++
++int issue_tdls_setup_cfm(_adapter *padapter, struct tdls_txmgmt *ptxmgmt)
++{
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	int ret = _FAIL;
++
++	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
++
++	ptxmgmt->action_code = TDLS_SETUP_CONFIRM;
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	pattrib = &pmgntframe->attrib;
++	pmgntframe->frame_tag = DATA_FRAMETAG;
++	pattrib->ether_type = 0x890d;
++
++	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
++	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pattrib->ra, get_bssid(&padapter->mlmepriv), ETH_ALEN);
++	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++	update_tdls_attrib(padapter, pattrib);
++	pattrib->qsel = pattrib->priority;
++	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
++		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++		rtw_free_xmitframe(pxmitpriv, pmgntframe);
++		goto exit;
++	}
++
++	dump_mgntframe(padapter, pmgntframe);
++
++	ret = _SUCCESS;
++exit:
++
++	return ret;
++
++}
++
++/* TDLS Discovery Response frame is a management action frame */
++int issue_tdls_dis_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 privacy)
++{
++	struct xmit_frame		*pmgntframe;
++	struct pkt_attrib		*pattrib;
++	unsigned char			*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short		*fctrl;
++	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	int ret = _FAIL;
++
++	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	/* unicast probe request frame */
++	_rtw_memcpy(pwlanhdr->addr1, ptxmgmt->peer, ETH_ALEN);
++	_rtw_memcpy(pattrib->dst, pwlanhdr->addr1, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pattrib->src, pwlanhdr->addr2, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN);
++	_rtw_memcpy(pattrib->ra, pwlanhdr->addr3, ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	rtw_build_tdls_dis_rsp_ies(padapter, pmgntframe, pframe, ptxmgmt, privacy);
++
++	pattrib->nr_frags = 1;
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(padapter, pmgntframe);
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++
++int issue_tdls_peer_traffic_rsp(_adapter *padapter, struct sta_info *ptdls_sta, struct tdls_txmgmt *ptxmgmt)
++{
++	struct xmit_frame	*pmgntframe;
++	struct pkt_attrib	*pattrib;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
++	int ret = _FAIL;
++
++	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
++
++	ptxmgmt->action_code = TDLS_PEER_TRAFFIC_RESPONSE;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	pattrib = &pmgntframe->attrib;
++
++	pmgntframe->frame_tag = DATA_FRAMETAG;
++	pattrib->ether_type = 0x890d;
++
++	_rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN);
++	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pattrib->ra, ptdls_sta->cmn.mac_addr, ETH_ALEN);
++	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++	update_tdls_attrib(padapter, pattrib);
++	pattrib->qsel = pattrib->priority;
++
++	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
++		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++		rtw_free_xmitframe(pxmitpriv, pmgntframe);
++		goto exit;
++	}
++
++	dump_mgntframe(padapter, pmgntframe);
++	ret = _SUCCESS;
++
++exit:
++
++	return ret;
++}
++
++int issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *ptdls_sta)
++{
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct tdls_txmgmt txmgmt;
++	int ret = _FAIL;
++
++	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++	txmgmt.action_code = TDLS_PEER_TRAFFIC_INDICATION;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	pattrib = &pmgntframe->attrib;
++
++	pmgntframe->frame_tag = DATA_FRAMETAG;
++	pattrib->ether_type = 0x890d;
++
++	_rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN);
++	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
++	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++	/* PTI frame's priority should be AC_VO */
++	pattrib->priority = 7;
++
++	update_tdls_attrib(padapter, pattrib);
++	pattrib->qsel = pattrib->priority;
++	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) {
++		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++		rtw_free_xmitframe(pxmitpriv, pmgntframe);
++		goto exit;
++	}
++
++	dump_mgntframe(padapter, pmgntframe);
++	ret = _SUCCESS;
++
++exit:
++
++	return ret;
++}
++
++#ifdef CONFIG_TDLS_CH_SW
++int issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta)
++{
++	struct xmit_frame	*pmgntframe;
++	struct pkt_attrib	*pattrib;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
++	struct tdls_txmgmt txmgmt;
++	int ret = _FAIL;
++
++	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
++
++	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
++		RTW_INFO("[TDLS] Ignore %s since channel switch is not allowed\n", __func__);
++		goto exit;
++	}
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++	txmgmt.action_code = TDLS_CHANNEL_SWITCH_REQUEST;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	pattrib = &pmgntframe->attrib;
++
++	pmgntframe->frame_tag = DATA_FRAMETAG;
++	pattrib->ether_type = 0x890d;
++
++	_rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN);
++	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pattrib->ra, ptdls_sta->cmn.mac_addr, ETH_ALEN);
++	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++	update_tdls_attrib(padapter, pattrib);
++	pattrib->qsel = pattrib->priority;
++	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) {
++		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++		rtw_free_xmitframe(pxmitpriv, pmgntframe);
++		goto exit;
++	}
++
++	dump_mgntframe(padapter, pmgntframe);
++	ret = _SUCCESS;
++exit:
++
++	return ret;
++}
++
++int issue_tdls_ch_switch_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack)
++{
++	struct xmit_frame	*pmgntframe;
++	struct pkt_attrib	*pattrib;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
++	int ret = _FAIL;
++
++	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
++
++	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
++		RTW_INFO("[TDLS] Ignore %s since channel switch is not allowed\n", __func__);
++		goto exit;
++	}
++
++	ptxmgmt->action_code = TDLS_CHANNEL_SWITCH_RESPONSE;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		goto exit;
++
++	pattrib = &pmgntframe->attrib;
++
++	pmgntframe->frame_tag = DATA_FRAMETAG;
++	pattrib->ether_type = 0x890d;
++
++	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
++	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pattrib->ra, ptxmgmt->peer, ETH_ALEN);
++	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++
++	update_tdls_attrib(padapter, pattrib);
++	pattrib->qsel = pattrib->priority;
++	/*
++		_enter_critical_bh(&pxmitpriv->lock, &irqL);
++		if(xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pmgntframe)==_TRUE){
++			_exit_critical_bh(&pxmitpriv->lock, &irqL);
++			return _FALSE;
++		}
++	*/
++	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
++		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
++		rtw_free_xmitframe(pxmitpriv, pmgntframe);
++		goto exit;
++	}
++
++	if (wait_ack)
++		ret = dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, 10);
++	else {
++		dump_mgntframe(padapter, pmgntframe);
++		ret = _SUCCESS;
++	}
++exit:
++
++	return ret;
++}
++#endif
++
++int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame)
++{
++	struct sta_info *ptdls_sta = NULL, *psta = rtw_get_stainfo(&(padapter->stapriv), get_bssid(&(padapter->mlmepriv)));
++	struct recv_priv *precvpriv = &(padapter->recvpriv);
++	u8 *ptr = precv_frame->u.hdr.rx_data, *psa;
++	struct rx_pkt_attrib *pattrib = &(precv_frame->u.hdr.attrib);
++	struct tdls_info *ptdlsinfo = &(padapter->tdlsinfo);
++	u8 empty_addr[ETH_ALEN] = { 0x00 };
++	int rssi = 0;
++	struct tdls_txmgmt txmgmt;
++	int ret = _SUCCESS;
++
++	if (psta)
++		rssi = psta->cmn.rssi_stat.rssi;
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++	/* WFDTDLS: for sigma test, not to setup direct link automatically */
++	ptdlsinfo->dev_discovered = _TRUE;
++
++	psa = get_sa(ptr);
++	ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), psa);
++	if (ptdls_sta != NULL)
++		ptdls_sta->sta_stats.rx_tdls_disc_rsp_pkts++;
++
++#ifdef CONFIG_TDLS_AUTOSETUP
++	if (ptdls_sta != NULL) {
++		/* Record the tdls sta with lowest signal strength */
++		if (ptdlsinfo->sta_maximum == _TRUE && ptdls_sta->alive_count >= 1) {
++			if (_rtw_memcmp(ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN)) {
++				_rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN);
++				ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.rx_pwdb_all;
++			} else {
++				if (ptdlsinfo->ss_record.RxPWDBAll < pattrib->phy_info.rx_pwdb_all) {
++					_rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN);
++					ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.rx_pwdb_all;
++				}
++			}
++		}
++	} else {
++		if (ptdlsinfo->sta_maximum == _TRUE) {
++			if (_rtw_memcmp(ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN)) {
++				/* All traffics are busy, do not set up another direct link. */
++				ret = _FAIL;
++				goto exit;
++			} else {
++				if (pattrib->phy_info.rx_pwdb_all > ptdlsinfo->ss_record.RxPWDBAll) {
++					_rtw_memcpy(txmgmt.peer, ptdlsinfo->ss_record.macaddr, ETH_ALEN);
++					/* issue_tdls_teardown(padapter, ptdlsinfo->ss_record.macaddr, _FALSE); */
++				} else {
++					ret = _FAIL;
++					goto exit;
++				}
++			}
++		}
++
++
++		if (pattrib->phy_info.rx_pwdb_all + TDLS_SIGNAL_THRESH >= rssi) {
++			RTW_INFO("pattrib->RxPWDBAll=%d, pdmpriv->undecorated_smoothed_pwdb=%d\n", pattrib->phy_info.rx_pwdb_all, rssi);
++			_rtw_memcpy(txmgmt.peer, psa, ETH_ALEN);
++			issue_tdls_setup_req(padapter, &txmgmt, _FALSE);
++		}
++	}
++exit:
++#endif /* CONFIG_TDLS_AUTOSETUP */
++
++	return ret;
++
++}
++
++sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
++{
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++	u8 *psa, *pmyid;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	u8 *ptr = precv_frame->u.hdr.rx_data;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	_irqL irqL;
++	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
++	u8 *prsnie, *ppairwise_cipher;
++	u8 i, k;
++	u8 ccmp_included = 0, rsnie_included = 0;
++	u16 j, pairwise_count;
++	u8 SNonce[32];
++	u32 timeout_interval = TDLS_TPK_RESEND_COUNT;
++	sint parsing_length;	/* Frame body length, without icv_len */
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++	u8 FIXED_IE = 5;
++	unsigned char		supportRate[16];
++	int				supportRateNum = 0;
++	struct tdls_txmgmt txmgmt;
++
++	if (rtw_tdls_is_setup_allowed(padapter) == _FALSE)
++		goto exit;
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++	psa = get_sa(ptr);
++
++	if (ptdlsinfo->sta_maximum == _TRUE) {
++		if (ptdls_sta == NULL)
++			goto exit;
++		else if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE))
++			goto exit;
++	}
++
++	pmyid = adapter_mac_addr(padapter);
++	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
++	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
++			 - prx_pkt_attrib->hdrlen
++			 - prx_pkt_attrib->iv_len
++			 - prx_pkt_attrib->icv_len
++			 - LLC_HEADER_SIZE
++			 - ETH_TYPE_LEN
++			 - PAYLOAD_TYPE_LEN;
++
++	if (ptdls_sta == NULL) {
++		ptdls_sta = rtw_alloc_stainfo(pstapriv, psa);
++		if (ptdls_sta == NULL)
++			goto exit;
++		
++		ptdlsinfo->sta_cnt++;
++	}
++	else {
++		if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {
++			/* If the direct link is already set up */
++			/* Process as re-setup after tear down */
++			RTW_INFO("re-setup a direct link\n");
++		}
++		/* Already receiving TDLS setup request */
++		else if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) {
++			RTW_INFO("receive duplicated TDLS setup request frame in handshaking\n");
++			goto exit;
++		}
++		/* When receiving and sending setup_req to the same link at the same time */
++		/* STA with higher MAC_addr would be initiator */
++		else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) {
++			RTW_INFO("receive setup_req after sending setup_req\n");
++			for (i = 0; i < 6; i++) {
++				if (*(pmyid + i) == *(psa + i)) {
++				} else if (*(pmyid + i) > *(psa + i)) {
++					ptdls_sta->tdls_sta_state = TDLS_INITIATOR_STATE;
++					break;
++				} else if (*(pmyid + i) < *(psa + i))
++					goto exit;
++			}
++		}
++	}
++
++	if (ptdls_sta) {
++		txmgmt.dialog_token = *(ptr + 2);	/* Copy dialog token */
++		txmgmt.status_code = _STATS_SUCCESSFUL_;
++
++		/* Parsing information element */
++		for (j = FIXED_IE; j < parsing_length;) {
++
++			pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
++
++			switch (pIE->ElementID) {
++			case _SUPPORTEDRATES_IE_:
++				_rtw_memcpy(supportRate, pIE->data, pIE->Length);
++				supportRateNum = pIE->Length;
++				break;
++			case _COUNTRY_IE_:
++				break;
++			case _EXT_SUPPORTEDRATES_IE_:
++				if (supportRateNum < sizeof(supportRate)) {
++					_rtw_memcpy(supportRate + supportRateNum, pIE->data, pIE->Length);
++					supportRateNum += pIE->Length;
++				}
++				break;
++			case _SUPPORTED_CH_IE_:
++				break;
++			case _RSN_IE_2_:
++				rsnie_included = 1;
++				if (prx_pkt_attrib->encrypt) {
++					prsnie = (u8 *)pIE;
++					/* Check CCMP pairwise_cipher presence. */
++					ppairwise_cipher = prsnie + 10;
++					_rtw_memcpy(ptdls_sta->TDLS_RSNIE, pIE->data, pIE->Length);
++					pairwise_count = *(u16 *)(ppairwise_cipher - 2);
++					for (k = 0; k < pairwise_count; k++) {
++						if (_rtw_memcmp(ppairwise_cipher + 4 * k, RSN_CIPHER_SUITE_CCMP, 4) == _TRUE)
++							ccmp_included = 1;
++					}
++
++					if (ccmp_included == 0)
++						txmgmt.status_code = _STATS_INVALID_RSNIE_;
++				}
++				break;
++			case _EXT_CAP_IE_:
++				break;
++			case _VENDOR_SPECIFIC_IE_:
++				break;
++			case _FTIE_:
++				if (prx_pkt_attrib->encrypt)
++					_rtw_memcpy(SNonce, (ptr + j + 52), 32);
++				break;
++			case _TIMEOUT_ITVL_IE_:
++				if (prx_pkt_attrib->encrypt)
++					timeout_interval = cpu_to_le32(*(u32 *)(ptr + j + 3));
++				break;
++			case _RIC_Descriptor_IE_:
++				break;
++#ifdef CONFIG_80211N_HT
++			case _HT_CAPABILITY_IE_:
++				rtw_tdls_process_ht_cap(padapter, ptdls_sta, pIE->data, pIE->Length);
++				break;
++#endif
++#ifdef CONFIG_80211AC_VHT
++			case EID_AID:
++				break;
++			case EID_VHTCapability:
++				rtw_tdls_process_vht_cap(padapter, ptdls_sta, pIE->data, pIE->Length);
++				break;
++#endif
++			case EID_BSSCoexistence:
++				break;
++			case _LINK_ID_IE_:
++				if (_rtw_memcmp(get_bssid(pmlmepriv), pIE->data, 6) == _FALSE)
++					txmgmt.status_code = _STATS_NOT_IN_SAME_BSS_;
++				break;
++			default:
++				break;
++			}
++
++			j += (pIE->Length + 2);
++
++		}
++
++		/* Check status code */
++		/* If responder STA has/hasn't security on AP, but request hasn't/has RSNIE, it should reject */
++		if (txmgmt.status_code == _STATS_SUCCESSFUL_) {
++			if (rsnie_included && prx_pkt_attrib->encrypt == 0)
++				txmgmt.status_code = _STATS_SEC_DISABLED_;
++			else if (rsnie_included == 0 && prx_pkt_attrib->encrypt)
++				txmgmt.status_code = _STATS_INVALID_PARAMETERS_;
++
++#ifdef CONFIG_WFD
++			/* WFD test plan version 0.18.2 test item 5.1.5 */
++			/* SoUT does not use TDLS if AP uses weak security */
++			if (padapter->wdinfo.wfd_tdls_enable && (rsnie_included && prx_pkt_attrib->encrypt != _AES_))
++				txmgmt.status_code = _STATS_SEC_DISABLED_;
++#endif /* CONFIG_WFD */
++		}
++
++		ptdls_sta->tdls_sta_state |= TDLS_INITIATOR_STATE;
++		if (prx_pkt_attrib->encrypt) {
++			_rtw_memcpy(ptdls_sta->SNonce, SNonce, 32);
++
++			if (timeout_interval <= 300)
++				ptdls_sta->TDLS_PeerKey_Lifetime = TDLS_TPK_RESEND_COUNT;
++			else
++				ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval;
++		}
++
++		/* Update station supportRate */
++		ptdls_sta->bssratelen = supportRateNum;
++		_rtw_memcpy(ptdls_sta->bssrateset, supportRate, supportRateNum);
++
++		/* -2: AP + BC/MC sta, -4: default key */
++		if (ptdlsinfo->sta_cnt == MAX_ALLOWED_TDLS_STA_NUM)
++			ptdlsinfo->sta_maximum = _TRUE;
++
++#ifdef CONFIG_WFD
++		rtw_tdls_process_wfd_ie(ptdlsinfo, ptr + FIXED_IE, parsing_length);
++#endif
++
++	} else
++		goto exit;
++
++	_rtw_memcpy(txmgmt.peer, prx_pkt_attrib->src, ETH_ALEN);
++
++	if (rtw_tdls_is_driver_setup(padapter)) {
++		issue_tdls_setup_rsp(padapter, &txmgmt);
++
++		if (txmgmt.status_code == _STATS_SUCCESSFUL_)
++			_set_timer(&ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME);
++		else {
++			rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
++			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
++		}
++	}
++
++exit:
++
++	return _SUCCESS;
++}
++
++int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
++{
++	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	u8 *ptr = precv_frame->u.hdr.rx_data;
++	_irqL irqL;
++	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
++	u8 *psa;
++	u16 status_code = 0;
++	sint parsing_length;	/* Frame body length, without icv_len */
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++	u8 FIXED_IE = 7;
++	u8 ANonce[32];
++	u8  *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL, *ppairwise_cipher = NULL;
++	u16 pairwise_count, j, k;
++	u8 verify_ccmp = 0;
++	unsigned char		supportRate[16];
++	int				supportRateNum = 0;
++	struct tdls_txmgmt txmgmt;
++	int ret = _SUCCESS;
++	u32 timeout_interval = TDLS_TPK_RESEND_COUNT;
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++	psa = get_sa(ptr);
++
++	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
++	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
++			 - prx_pkt_attrib->hdrlen
++			 - prx_pkt_attrib->iv_len
++			 - prx_pkt_attrib->icv_len
++			 - LLC_HEADER_SIZE
++			 - ETH_TYPE_LEN
++			 - PAYLOAD_TYPE_LEN;
++
++	_rtw_memcpy(&status_code, ptr + 2, 2);
++
++	if (status_code != 0) {
++		RTW_INFO("[TDLS] %s status_code = %d, free_tdls_sta\n", __FUNCTION__, status_code);
++		rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
++		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
++		ret = _FAIL;
++		goto exit;
++	}
++
++	status_code = 0;
++
++	/* parsing information element */
++	for (j = FIXED_IE; j < parsing_length;) {
++		pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
++
++		switch (pIE->ElementID) {
++		case _SUPPORTEDRATES_IE_:
++			_rtw_memcpy(supportRate, pIE->data, pIE->Length);
++			supportRateNum = pIE->Length;
++			break;
++		case _COUNTRY_IE_:
++			break;
++		case _EXT_SUPPORTEDRATES_IE_:
++			if (supportRateNum < sizeof(supportRate)) {
++				_rtw_memcpy(supportRate + supportRateNum, pIE->data, pIE->Length);
++				supportRateNum += pIE->Length;
++			}
++			break;
++		case _SUPPORTED_CH_IE_:
++			break;
++		case _RSN_IE_2_:
++			prsnie = (u8 *)pIE;
++			/* Check CCMP pairwise_cipher presence. */
++			ppairwise_cipher = prsnie + 10;
++			_rtw_memcpy(&pairwise_count, (u16 *)(ppairwise_cipher - 2), 2);
++			for (k = 0; k < pairwise_count; k++) {
++				if (_rtw_memcmp(ppairwise_cipher + 4 * k, RSN_CIPHER_SUITE_CCMP, 4) == _TRUE)
++					verify_ccmp = 1;
++			}
++		case _EXT_CAP_IE_:
++			break;
++		case _VENDOR_SPECIFIC_IE_:
++			if (_rtw_memcmp((u8 *)pIE + 2, WMM_INFO_OUI, 6) == _TRUE) {
++				/* WMM Info ID and OUI */
++				if ((pregistrypriv->wmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE))
++					ptdls_sta->qos_option = _TRUE;
++			}
++			break;
++		case _FTIE_:
++			pftie = (u8 *)pIE;
++			_rtw_memcpy(ANonce, (ptr + j + 20), 32);
++			break;
++		case _TIMEOUT_ITVL_IE_:
++			ptimeout_ie = (u8 *)pIE;
++			timeout_interval = cpu_to_le32(*(u32 *)(ptimeout_ie + 3));
++			break;
++		case _RIC_Descriptor_IE_:
++			break;
++#ifdef CONFIG_80211N_HT
++		case _HT_CAPABILITY_IE_:
++			rtw_tdls_process_ht_cap(padapter, ptdls_sta, pIE->data, pIE->Length);
++			break;
++#endif
++#ifdef CONFIG_80211AC_VHT
++		case EID_AID:
++			/* todo in the future if necessary */
++			break;
++		case EID_VHTCapability:
++			rtw_tdls_process_vht_cap(padapter, ptdls_sta, pIE->data, pIE->Length);
++			break;
++		case EID_OpModeNotification:
++			rtw_tdls_process_vht_op_mode_notify(padapter, ptdls_sta, pIE->data, pIE->Length);
++			break;
++#endif
++		case EID_BSSCoexistence:
++			break;
++		case _LINK_ID_IE_:
++			plinkid_ie = (u8 *)pIE;
++			break;
++		default:
++			break;
++		}
++
++		j += (pIE->Length + 2);
++
++	}
++
++	ptdls_sta->bssratelen = supportRateNum;
++	_rtw_memcpy(ptdls_sta->bssrateset, supportRate, supportRateNum);
++	_rtw_memcpy(ptdls_sta->ANonce, ANonce, 32);
++
++#ifdef CONFIG_WFD
++	rtw_tdls_process_wfd_ie(ptdlsinfo, ptr + FIXED_IE, parsing_length);
++#endif
++
++	if (prx_pkt_attrib->encrypt) {
++		if (verify_ccmp == 1) {
++			txmgmt.status_code = _STATS_SUCCESSFUL_;
++			if (rtw_tdls_is_driver_setup(padapter) == _TRUE) {
++				wpa_tdls_generate_tpk(padapter, ptdls_sta);
++				if (tdls_verify_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL) {
++					RTW_INFO("[TDLS] %s tdls_verify_mic fail, free_tdls_sta\n", __FUNCTION__);
++					rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
++					rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
++					ret = _FAIL;
++					goto exit;
++				}
++				ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval;
++			}
++		} else
++			txmgmt.status_code = _STATS_INVALID_RSNIE_;
++	} else
++		txmgmt.status_code = _STATS_SUCCESSFUL_;
++
++	if (rtw_tdls_is_driver_setup(padapter) == _TRUE) {
++		_rtw_memcpy(txmgmt.peer, prx_pkt_attrib->src, ETH_ALEN);
++		issue_tdls_setup_cfm(padapter, &txmgmt);
++
++		if (txmgmt.status_code == _STATS_SUCCESSFUL_) {
++			rtw_tdls_set_link_established(padapter, _TRUE);
++
++			if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) {
++				ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE;
++				ptdls_sta->state |= WIFI_ASOC_STATE;
++				_cancel_timer_ex(&ptdls_sta->handshake_timer);
++			}
++
++			if (prx_pkt_attrib->encrypt)
++				rtw_tdls_set_key(padapter, ptdls_sta);
++
++			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ESTABLISHED);
++
++		}
++	}
++
++exit:
++	if (rtw_tdls_is_driver_setup(padapter) == _TRUE)
++		return ret;
++	else
++		return _SUCCESS;
++
++}
++
++int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
++{
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	u8 *ptr = precv_frame->u.hdr.rx_data;
++	_irqL irqL;
++	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
++	u8 *psa;
++	u16 status_code = 0;
++	sint parsing_length;
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++	u8 FIXED_IE = 5;
++	u8  *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL, *ppairwise_cipher = NULL;
++	u16 j, pairwise_count;
++	int ret = _SUCCESS;
++
++	psa = get_sa(ptr);
++
++	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
++	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
++			 - prx_pkt_attrib->hdrlen
++			 - prx_pkt_attrib->iv_len
++			 - prx_pkt_attrib->icv_len
++			 - LLC_HEADER_SIZE
++			 - ETH_TYPE_LEN
++			 - PAYLOAD_TYPE_LEN;
++
++	_rtw_memcpy(&status_code, ptr + 2, 2);
++
++	if (status_code != 0) {
++		RTW_INFO("[%s] status_code = %d\n, free_tdls_sta", __FUNCTION__, status_code);
++		rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
++		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
++		ret = _FAIL;
++		goto exit;
++	}
++
++	/* Parsing information element */
++	for (j = FIXED_IE; j < parsing_length;) {
++
++		pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
++
++		switch (pIE->ElementID) {
++		case _RSN_IE_2_:
++			prsnie = (u8 *)pIE;
++			break;
++		case _VENDOR_SPECIFIC_IE_:
++			if (_rtw_memcmp((u8 *)pIE + 2, WMM_PARA_OUI, 6) == _TRUE) {
++				/* WMM Parameter ID and OUI */
++				ptdls_sta->qos_option = _TRUE;
++			}
++			break;
++		case _FTIE_:
++			pftie = (u8 *)pIE;
++			break;
++		case _TIMEOUT_ITVL_IE_:
++			ptimeout_ie = (u8 *)pIE;
++			break;
++#ifdef CONFIG_80211N_HT
++		case _HT_EXTRA_INFO_IE_:
++			break;
++#endif
++#ifdef CONFIG_80211AC_VHT
++		case EID_VHTOperation:
++			rtw_tdls_process_vht_operation(padapter, ptdls_sta, pIE->data, pIE->Length);
++			break;
++		case EID_OpModeNotification:
++			rtw_tdls_process_vht_op_mode_notify(padapter, ptdls_sta, pIE->data, pIE->Length);
++			break;
++#endif
++		case _LINK_ID_IE_:
++			plinkid_ie = (u8 *)pIE;
++			break;
++		default:
++			break;
++		}
++
++		j += (pIE->Length + 2);
++
++	}
++
++	if (prx_pkt_attrib->encrypt) {
++		/* Verify mic in FTIE MIC field */
++		if (rtw_tdls_is_driver_setup(padapter) &&
++		    (tdls_verify_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL)) {
++			rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
++			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
++			ret = _FAIL;
++			goto exit;
++		}
++	}
++
++	if (rtw_tdls_is_driver_setup(padapter)) {
++		rtw_tdls_set_link_established(padapter, _TRUE);
++
++		if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) {
++			ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE;
++			ptdls_sta->state |= WIFI_ASOC_STATE;
++			_cancel_timer_ex(&ptdls_sta->handshake_timer);
++		}
++
++		if (prx_pkt_attrib->encrypt) {
++			rtw_tdls_set_key(padapter, ptdls_sta);
++
++			/* Start  TPK timer */
++			ptdls_sta->TPK_count = 0;
++			_set_timer(&ptdls_sta->TPK_timer, ONE_SEC);
++		}
++
++		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ESTABLISHED);
++	}
++
++exit:
++	return ret;
++
++}
++
++int On_TDLS_Dis_Req(_adapter *padapter, union recv_frame *precv_frame)
++{
++	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct sta_info *psta_ap;
++	u8 *ptr = precv_frame->u.hdr.rx_data;
++	sint parsing_length;	/* Frame body length, without icv_len */
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++	u8 FIXED_IE = 3, *dst;
++	u16 j;
++	struct tdls_txmgmt txmgmt;
++	int ret = _SUCCESS;
++
++	if (rtw_tdls_is_driver_setup(padapter) == _FALSE)
++		goto exit;
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
++	txmgmt.dialog_token = *(ptr + 2);
++	_rtw_memcpy(&txmgmt.peer, precv_frame->u.hdr.attrib.src, ETH_ALEN);
++	txmgmt.action_code = TDLS_DISCOVERY_RESPONSE;
++	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
++			 - prx_pkt_attrib->hdrlen
++			 - prx_pkt_attrib->iv_len
++			 - prx_pkt_attrib->icv_len
++			 - LLC_HEADER_SIZE
++			 - ETH_TYPE_LEN
++			 - PAYLOAD_TYPE_LEN;
++
++	/* Parsing information element */
++	for (j = FIXED_IE; j < parsing_length;) {
++
++		pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
++
++		switch (pIE->ElementID) {
++		case _LINK_ID_IE_:
++			psta_ap = rtw_get_stainfo(pstapriv, pIE->data);
++			if (psta_ap == NULL)
++				goto exit;
++			dst = pIE->data + 12;
++			if (MacAddr_isBcst(dst) == _FALSE && (_rtw_memcmp(adapter_mac_addr(padapter), dst, ETH_ALEN) == _FALSE))
++				goto exit;
++			break;
++		default:
++			break;
++		}
++
++		j += (pIE->Length + 2);
++
++	}
++
++	issue_tdls_dis_rsp(padapter, &txmgmt, prx_pkt_attrib->privacy);
++
++exit:
++	return ret;
++
++}
++
++int On_TDLS_Teardown(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
++{
++	u8 *ptr = precv_frame->u.hdr.rx_data;
++	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct sta_priv	*pstapriv = &padapter->stapriv;
++	_irqL irqL;
++	u8 reason;
++
++	reason = *(ptr + prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN + 2);
++	RTW_INFO("[TDLS] %s Reason code(%d)\n", __FUNCTION__, reason);
++
++	if (rtw_tdls_is_driver_setup(padapter)) {
++		rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
++		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
++	}
++
++	return _SUCCESS;
++
++}
++
++#if 0
++u8 TDLS_check_ch_state(uint state)
++{
++	if (state & TDLS_CH_SWITCH_ON_STATE &&
++	    state & TDLS_PEER_AT_OFF_STATE) {
++		if (state & TDLS_PEER_SLEEP_STATE)
++			return 2;	/* U-APSD + ch. switch */
++		else
++			return 1;	/* ch. switch */
++	} else
++		return 0;
++}
++#endif
++
++int On_TDLS_Peer_Traffic_Indication(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
++{
++	struct rx_pkt_attrib	*pattrib = &precv_frame->u.hdr.attrib;
++	u8 *ptr = precv_frame->u.hdr.rx_data;
++	struct tdls_txmgmt txmgmt;
++
++	ptr += pattrib->hdrlen + pattrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++
++		txmgmt.dialog_token = *(ptr + 2);
++		issue_tdls_peer_traffic_rsp(padapter, ptdls_sta, &txmgmt);
++		/* issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 0, 0); */
++
++	return _SUCCESS;
++}
++
++/* We process buffered data for 1. U-APSD, 2. ch. switch, 3. U-APSD + ch. switch here */
++int On_TDLS_Peer_Traffic_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
++{
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct rx_pkt_attrib	*pattrib = &precv_frame->u.hdr.attrib;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	u8 wmmps_ac = 0;
++	/* u8 state=TDLS_check_ch_state(ptdls_sta->tdls_sta_state); */
++	int i;
++
++	ptdls_sta->sta_stats.rx_data_pkts++;
++
++	ptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE);
++
++	/* Check 4-AC queue bit */
++	if (ptdls_sta->uapsd_vo || ptdls_sta->uapsd_vi || ptdls_sta->uapsd_be || ptdls_sta->uapsd_bk)
++		wmmps_ac = 1;
++
++	/* If it's a direct link and have buffered frame */
++	if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {
++		if (wmmps_ac) {
++			_irqL irqL;
++			_list	*xmitframe_plist, *xmitframe_phead;
++			struct xmit_frame *pxmitframe = NULL;
++
++			_enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);
++
++			xmitframe_phead = get_list_head(&ptdls_sta->sleep_q);
++			xmitframe_plist = get_next(xmitframe_phead);
++
++			/* transmit buffered frames */
++			while (rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist) == _FALSE) {
++				pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
++				xmitframe_plist = get_next(xmitframe_plist);
++				rtw_list_delete(&pxmitframe->list);
++
++				ptdls_sta->sleepq_len--;
++				ptdls_sta->sleepq_ac_len--;
++				if (ptdls_sta->sleepq_len > 0) {
++					pxmitframe->attrib.mdata = 1;
++					pxmitframe->attrib.eosp = 0;
++				} else {
++					pxmitframe->attrib.mdata = 0;
++					pxmitframe->attrib.eosp = 1;
++				}
++				pxmitframe->attrib.triggered = 1;
++
++				rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
++			}
++
++			if (ptdls_sta->sleepq_len == 0)
++				RTW_INFO("no buffered packets for tdls to xmit\n");
++			else {
++				RTW_INFO("error!psta->sleepq_len=%d\n", ptdls_sta->sleepq_len);
++				ptdls_sta->sleepq_len = 0;
++			}
++
++			_exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);
++
++		}
++
++	}
++
++	return _SUCCESS;
++}
++
++#ifdef CONFIG_TDLS_CH_SW
++sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
++{
++	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	u8 *ptr = precv_frame->u.hdr.rx_data;
++	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
++	sint parsing_length;
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++	u8 FIXED_IE = 4;
++	u16 j;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	u8 zaddr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
++	u16 switch_time = TDLS_CH_SWITCH_TIME * 1000, switch_timeout = TDLS_CH_SWITCH_TIMEOUT * 1000;
++	u8 take_care_iqk;
++
++	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
++		RTW_INFO("[TDLS] Ignore %s since channel switch is not allowed\n", __func__);
++		return _FAIL;
++	}
++
++	ptdls_sta->ch_switch_time = switch_time;
++	ptdls_sta->ch_switch_timeout = switch_timeout;
++
++	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
++	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
++			 - prx_pkt_attrib->hdrlen
++			 - prx_pkt_attrib->iv_len
++			 - prx_pkt_attrib->icv_len
++			 - LLC_HEADER_SIZE
++			 - ETH_TYPE_LEN
++			 - PAYLOAD_TYPE_LEN;
++
++	pchsw_info->off_ch_num = *(ptr + 2);
++
++	if ((*(ptr + 2) == 2) && (hal_is_band_support(padapter, BAND_ON_5G)))
++		pchsw_info->off_ch_num = 44;
++
++	if (pchsw_info->off_ch_num != pmlmeext->cur_channel)
++		pchsw_info->delay_switch_back = _FALSE;
++
++	/* Parsing information element */
++	for (j = FIXED_IE; j < parsing_length;) {
++		pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
++
++		switch (pIE->ElementID) {
++		case EID_SecondaryChnlOffset:
++			switch (*(pIE->data)) {
++			case EXTCHNL_OFFSET_UPPER:
++				pchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++				break;
++
++			case EXTCHNL_OFFSET_LOWER:
++				pchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++				break;
++
++			default:
++				pchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++				break;
++			}
++			break;
++		case _LINK_ID_IE_:
++			break;
++		case _CH_SWITCH_TIMING_:
++			ptdls_sta->ch_switch_time = (RTW_GET_LE16(pIE->data) >= TDLS_CH_SWITCH_TIME * 1000) ?
++				RTW_GET_LE16(pIE->data) : TDLS_CH_SWITCH_TIME * 1000;
++			ptdls_sta->ch_switch_timeout = (RTW_GET_LE16(pIE->data + 2) >= TDLS_CH_SWITCH_TIMEOUT * 1000) ?
++				RTW_GET_LE16(pIE->data + 2) : TDLS_CH_SWITCH_TIMEOUT * 1000;
++			RTW_INFO("[TDLS] %s ch_switch_time:%d, ch_switch_timeout:%d\n"
++				, __FUNCTION__, RTW_GET_LE16(pIE->data), RTW_GET_LE16(pIE->data + 2));
++		default:
++			break;
++		}
++
++		j += (pIE->Length + 2);
++	}
++
++	rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
++	if (take_care_iqk == _TRUE) {
++		u8 central_chnl;
++		u8 bw_mode;
++
++		bw_mode = (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20;
++		central_chnl = rtw_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset);
++		if (rtw_hal_ch_sw_iqk_info_search(padapter, central_chnl, bw_mode) < 0) {
++			if (!(pchsw_info->ch_sw_state & TDLS_CH_SWITCH_PREPARE_STATE))
++				rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_PREPARE);
++
++			return _FAIL;
++		}
++	}
++
++	/* cancel ch sw monitor timer for responder */
++	if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
++		_cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer);
++
++	if (_rtw_memcmp(pchsw_info->addr, zaddr, ETH_ALEN) == _TRUE)
++		_rtw_memcpy(pchsw_info->addr, ptdls_sta->cmn.mac_addr, ETH_ALEN);
++
++	if (ATOMIC_READ(&pchsw_info->chsw_on) == _FALSE)
++		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);
++
++	rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_RESP);
++
++	return _SUCCESS;
++}
++
++sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
++{
++	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	u8 *ptr = precv_frame->u.hdr.rx_data;
++	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
++	sint parsing_length;
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++	u8 FIXED_IE = 4;
++	u16 status_code, j, switch_time, switch_timeout;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	int ret = _SUCCESS;
++
++	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
++		RTW_INFO("[TDLS] Ignore %s since channel switch is not allowed\n", __func__);
++		return _SUCCESS;
++	}
++
++	/* If we receive Unsolicited TDLS Channel Switch Response when channel switch is running, */
++	/* we will go back to base channel and terminate this channel switch procedure */
++	if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) {
++		if (pmlmeext->cur_channel != rtw_get_oper_ch(padapter)) {
++			RTW_INFO("[TDLS] Rx unsolicited channel switch response\n");
++			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL);
++			goto exit;
++		}
++	}
++
++	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
++	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
++			 - prx_pkt_attrib->hdrlen
++			 - prx_pkt_attrib->iv_len
++			 - prx_pkt_attrib->icv_len
++			 - LLC_HEADER_SIZE
++			 - ETH_TYPE_LEN
++			 - PAYLOAD_TYPE_LEN;
++
++	_rtw_memcpy(&status_code, ptr + 2, 2);
++
++	if (status_code != 0) {
++		RTW_INFO("[TDLS] %s status_code:%d\n", __func__, status_code);
++		pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE);
++		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END);
++		ret = _FAIL;
++		goto exit;
++	}
++
++	/* Parsing information element */
++	for (j = FIXED_IE; j < parsing_length;) {
++		pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
++
++		switch (pIE->ElementID) {
++		case _LINK_ID_IE_:
++			break;
++		case _CH_SWITCH_TIMING_:
++			_rtw_memcpy(&switch_time, pIE->data, 2);
++			if (switch_time > ptdls_sta->ch_switch_time)
++				_rtw_memcpy(&ptdls_sta->ch_switch_time, &switch_time, 2);
++
++			_rtw_memcpy(&switch_timeout, pIE->data + 2, 2);
++			if (switch_timeout > ptdls_sta->ch_switch_timeout)
++				_rtw_memcpy(&ptdls_sta->ch_switch_timeout, &switch_timeout, 2);
++			break;
++		default:
++			break;
++		}
++
++		j += (pIE->Length + 2);
++	}
++
++	if ((pmlmeext->cur_channel == rtw_get_oper_ch(padapter)) &&
++	    (pchsw_info->ch_sw_state & TDLS_WAIT_CH_RSP_STATE)) {
++		if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE)
++			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_OFF_CHNL);
++	}
++
++exit:
++	return ret;
++}
++#endif /* CONFIG_TDLS_CH_SW */
++
++#ifdef CONFIG_WFD
++void wfd_ie_tdls(_adapter *padapter, u8 *pframe, u32 *pktlen)
++{
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct wifi_display_info	*pwfd_info = padapter->tdlsinfo.wfd_info;
++	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
++	u32 wfdielen = 0;
++	u16 v16 = 0;
++
++	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
++		return;
++
++	/* WFD OUI */
++	wfdielen = 0;
++	wfdie[wfdielen++] = 0x50;
++	wfdie[wfdielen++] = 0x6F;
++	wfdie[wfdielen++] = 0x9A;
++	wfdie[wfdielen++] = 0x0A;	/* WFA WFD v1.0 */
++
++	/*
++	 *	Commented by Albert 20110825
++	 *	According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes
++	 *	1. WFD Device Information
++	 *	2. Associated BSSID ( Optional )
++	 *	3. Local IP Adress ( Optional )
++	 */
++
++	/* WFD Device Information ATTR */
++	/* Type: */
++	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
++
++	/* Length: */
++	/* Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/* Value1: */
++	/* WFD device information */
++	/* available for WFD session + Preferred TDLS + WSD ( WFD Service Discovery ) */
++	v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL
++		| WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_WSD;
++	RTW_PUT_BE16(wfdie + wfdielen, v16);
++	wfdielen += 2;
++
++	/* Value2: */
++	/* Session Management Control Port */
++	/* Default TCP port for RTSP messages is 554 */
++	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->tdls_rtsp_ctrlport);
++	wfdielen += 2;
++
++	/* Value3: */
++	/* WFD Device Maximum Throughput */
++	/* 300Mbps is the maximum throughput */
++	RTW_PUT_BE16(wfdie + wfdielen, 300);
++	wfdielen += 2;
++
++	/* Associated BSSID ATTR */
++	/* Type: */
++	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
++
++	/* Length: */
++	/* Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
++	wfdielen += 2;
++
++	/* Value: */
++	/* Associated BSSID */
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
++	else
++		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
++
++	/* Local IP Address ATTR */
++	wfdie[wfdielen++] = WFD_ATTR_LOCAL_IP_ADDR;
++
++	/* Length: */
++	/* Note: In the WFD specification, the size of length field is 2. */
++	RTW_PUT_BE16(wfdie + wfdielen, 0x0005);
++	wfdielen += 2;
++
++	/* Version: */
++	/* 0x01: Version1;IPv4 */
++	wfdie[wfdielen++] = 0x01;
++
++	/* IPv4 Address */
++	_rtw_memcpy(wfdie + wfdielen, pwfd_info->ip_address, 4);
++	wfdielen += 4;
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, pktlen);
++
++}
++#endif /* CONFIG_WFD */
++
++void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
++	int i = 0 ;
++	u32 time;
++	u8 *pframe_head;
++
++	/* SNonce */
++	if (pattrib->encrypt) {
++		for (i = 0; i < 8; i++) {
++			time = rtw_get_current_time();
++			_rtw_memcpy(&ptdls_sta->SNonce[4 * i], (u8 *)&time, 4);
++		}
++	}
++
++	pframe_head = pframe;	/* For rtw_tdls_set_ht_cap() */
++
++	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
++	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
++	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
++	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
++
++	pframe = rtw_tdls_set_capability(padapter, pframe, pattrib);
++	pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib);
++	pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib);
++	pframe = rtw_tdls_set_sup_reg_class(pframe, pattrib);
++
++	if (pattrib->encrypt)
++		pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib,  _TRUE, ptdls_sta);
++
++	pframe = rtw_tdls_set_ext_cap(pframe, pattrib);
++
++	if (pattrib->encrypt) {
++		pframe = rtw_tdls_set_ftie(ptxmgmt
++					   , pframe
++					   , pattrib
++					   , NULL
++					   , ptdls_sta->SNonce);
++
++		pframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib, _TRUE, ptdls_sta);
++	}
++
++#ifdef CONFIG_80211N_HT
++	/* Sup_reg_classes(optional) */
++	if (pregistrypriv->ht_enable == _TRUE)
++		pframe = rtw_tdls_set_ht_cap(padapter, pframe_head, pattrib);
++#endif
++
++	pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib);
++
++	pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
++
++	if ((pregistrypriv->wmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE))
++		pframe = rtw_tdls_set_qos_cap(pframe, pattrib);
++
++#ifdef CONFIG_80211AC_VHT
++	if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14)
++	    && REGSTY_IS_11AC_ENABLE(pregistrypriv)
++	    && is_supported_vht(pregistrypriv->wireless_mode)
++	    && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
++	   ) {
++		pframe = rtw_tdls_set_aid(padapter, pframe, pattrib);
++		pframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib);
++	}
++#endif
++
++#ifdef CONFIG_WFD
++	if (padapter->wdinfo.wfd_tdls_enable == 1)
++		wfd_ie_tdls(padapter, pframe, &(pattrib->pktlen));
++#endif
++
++}
++
++void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
++	u8 k; /* for random ANonce */
++	u8  *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL;
++	u32 time;
++	u8 *pframe_head;
++
++	if (pattrib->encrypt) {
++		for (k = 0; k < 8; k++) {
++			time = rtw_get_current_time();
++			_rtw_memcpy(&ptdls_sta->ANonce[4 * k], (u8 *)&time, 4);
++		}
++	}
++
++	pframe_head = pframe;
++
++	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
++	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
++	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
++	pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt);
++
++	if (ptxmgmt->status_code != 0) {
++		RTW_INFO("[%s] status_code:%04x\n", __FUNCTION__, ptxmgmt->status_code);
++		return;
++	}
++
++	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
++	pframe = rtw_tdls_set_capability(padapter, pframe, pattrib);
++	pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib);
++	pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib);
++	pframe = rtw_tdls_set_sup_reg_class(pframe, pattrib);
++
++	if (pattrib->encrypt) {
++		prsnie = pframe;
++		pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib,  _FALSE, ptdls_sta);
++	}
++
++	pframe = rtw_tdls_set_ext_cap(pframe, pattrib);
++
++	if (pattrib->encrypt) {
++		if (rtw_tdls_is_driver_setup(padapter) == _TRUE)
++			wpa_tdls_generate_tpk(padapter, ptdls_sta);
++
++		pftie = pframe;
++		pftie_mic = pframe + 4;
++		pframe = rtw_tdls_set_ftie(ptxmgmt
++					   , pframe
++					   , pattrib
++					   , ptdls_sta->ANonce
++					   , ptdls_sta->SNonce);
++
++		ptimeout_ie = pframe;
++		pframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib, _FALSE, ptdls_sta);
++	}
++
++#ifdef CONFIG_80211N_HT
++	/* Sup_reg_classes(optional) */
++	if (pregistrypriv->ht_enable == _TRUE)
++		pframe = rtw_tdls_set_ht_cap(padapter, pframe_head, pattrib);
++#endif
++
++	pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib);
++
++	plinkid_ie = pframe;
++	pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
++
++	/* Fill FTIE mic */
++	if (pattrib->encrypt && rtw_tdls_is_driver_setup(padapter) == _TRUE)
++		wpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic);
++
++	if ((pregistrypriv->wmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE))
++		pframe = rtw_tdls_set_qos_cap(pframe, pattrib);
++
++#ifdef CONFIG_80211AC_VHT
++	if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14)
++	    && REGSTY_IS_11AC_ENABLE(pregistrypriv)
++	    && is_supported_vht(pregistrypriv->wireless_mode)
++	    && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
++	   ) {
++		pframe = rtw_tdls_set_aid(padapter, pframe, pattrib);
++		pframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib);
++		pframe = rtw_tdls_set_vht_op_mode_notify(padapter, pframe, pattrib, pmlmeext->cur_bwmode);
++	}
++#endif
++
++#ifdef CONFIG_WFD
++	if (padapter->wdinfo.wfd_tdls_enable)
++		wfd_ie_tdls(padapter, pframe, &(pattrib->pktlen));
++#endif
++
++}
++
++void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
++
++	unsigned int ie_len;
++	unsigned char *p;
++	u8 wmm_param_ele[24] = {0};
++	u8  *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL;
++
++	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
++	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
++	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
++	pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt);
++	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
++
++	if (ptxmgmt->status_code != 0)
++		return;
++
++	if (pattrib->encrypt) {
++		prsnie = pframe;
++		pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib, _TRUE, ptdls_sta);
++	}
++
++	if (pattrib->encrypt) {
++		pftie = pframe;
++		pftie_mic = pframe + 4;
++		pframe = rtw_tdls_set_ftie(ptxmgmt
++					   , pframe
++					   , pattrib
++					   , ptdls_sta->ANonce
++					   , ptdls_sta->SNonce);
++
++		ptimeout_ie = pframe;
++		pframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib, _TRUE, ptdls_sta);
++
++		if (rtw_tdls_is_driver_setup(padapter) == _TRUE) {
++			/* Start TPK timer */
++			ptdls_sta->TPK_count = 0;
++			_set_timer(&ptdls_sta->TPK_timer, ONE_SEC);
++		}
++	}
++
++	/* HT operation; todo */
++
++	plinkid_ie = pframe;
++	pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
++
++	if (pattrib->encrypt && (rtw_tdls_is_driver_setup(padapter) == _TRUE))
++		wpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic);
++
++	if (ptdls_sta->qos_option == _TRUE)
++		pframe = rtw_tdls_set_wmm_params(padapter, pframe, pattrib);
++
++#ifdef CONFIG_80211AC_VHT
++	if ((padapter->mlmepriv.htpriv.ht_option == _TRUE)
++	    && (ptdls_sta->vhtpriv.vht_option == _TRUE) && (pmlmeext->cur_channel > 14)
++	    && REGSTY_IS_11AC_ENABLE(pregistrypriv)
++	    && is_supported_vht(pregistrypriv->wireless_mode)
++	    && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
++	   ) {
++		pframe = rtw_tdls_set_vht_operation(padapter, pframe, pattrib, pmlmeext->cur_channel);
++		pframe = rtw_tdls_set_vht_op_mode_notify(padapter, pframe, pattrib, pmlmeext->cur_bwmode);
++	}
++#endif
++}
++
++void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
++{
++	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
++	u8  *pftie = NULL, *pftie_mic = NULL, *plinkid_ie = NULL;
++
++	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
++	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
++	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
++	pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt);
++
++	if (pattrib->encrypt) {
++		pftie = pframe;
++		pftie_mic = pframe + 4;
++		pframe = rtw_tdls_set_ftie(ptxmgmt
++					   , pframe
++					   , pattrib
++					   , ptdls_sta->ANonce
++					   , ptdls_sta->SNonce);
++	}
++
++	plinkid_ie = pframe;
++	if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
++		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
++	else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
++		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
++
++	if (pattrib->encrypt && (rtw_tdls_is_driver_setup(padapter) == _TRUE))
++		wpa_tdls_teardown_ftie_mic(ptdls_sta->tpk.kck, plinkid_ie, ptxmgmt->status_code, 1, 4, pftie, pftie_mic);
++}
++
++void rtw_build_tdls_dis_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt)
++{
++	struct pkt_attrib *pattrib = &pxmitframe->attrib;
++
++	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
++	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
++	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
++	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
++	pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
++
++}
++
++void rtw_build_tdls_dis_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, u8 privacy)
++{
++	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
++	u8 *pframe_head, pktlen_index;
++
++	pktlen_index = pattrib->pktlen;
++	pframe_head = pframe;
++
++	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_PUBLIC);
++	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
++	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
++	pframe = rtw_tdls_set_capability(padapter, pframe, pattrib);
++
++	pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib);
++
++	pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib);
++
++	if (privacy)
++		pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib, _TRUE, NULL);
++
++	pframe = rtw_tdls_set_ext_cap(pframe, pattrib);
++
++	if (privacy) {
++		pframe = rtw_tdls_set_ftie(ptxmgmt, pframe, pattrib, NULL, NULL);
++		pframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib,  _TRUE, NULL);
++	}
++
++#ifdef CONFIG_80211N_HT
++	if (pregistrypriv->ht_enable == _TRUE)
++		pframe = rtw_tdls_set_ht_cap(padapter, pframe_head - pktlen_index, pattrib);
++#endif
++
++	pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib);
++	pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
++
++}
++
++
++void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
++{
++
++	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
++	u8 AC_queue = 0;
++
++	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
++	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
++	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
++	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
++
++	if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
++		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
++	else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
++		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
++
++	/* PTI control */
++	/* PU buffer status */
++	if (ptdls_sta->uapsd_bk & BIT(1))
++		AC_queue = BIT(0);
++	if (ptdls_sta->uapsd_be & BIT(1))
++		AC_queue = BIT(1);
++	if (ptdls_sta->uapsd_vi & BIT(1))
++		AC_queue = BIT(2);
++	if (ptdls_sta->uapsd_vo & BIT(1))
++		AC_queue = BIT(3);
++	pframe = rtw_set_ie(pframe, _PTI_BUFFER_STATUS_, 1, &AC_queue, &(pattrib->pktlen));
++
++}
++
++void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
++{
++
++	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
++
++	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
++	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
++	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
++	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
++
++	if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
++		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
++	else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
++		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
++}
++
++#ifdef CONFIG_TDLS_CH_SW
++void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
++{
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
++	struct sta_priv	*pstapriv = &padapter->stapriv;
++	u16 switch_time = TDLS_CH_SWITCH_TIME * 1000, switch_timeout = TDLS_CH_SWITCH_TIMEOUT * 1000;
++
++	ptdls_sta->ch_switch_time = switch_time;
++	ptdls_sta->ch_switch_timeout = switch_timeout;
++
++	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
++	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
++	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
++	pframe = rtw_tdls_set_target_ch(padapter, pframe, pattrib);
++	pframe = rtw_tdls_set_reg_class(pframe, pattrib, ptdls_sta);
++
++	if (ptdlsinfo->chsw_info.ch_offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE) {
++		switch (ptdlsinfo->chsw_info.ch_offset) {
++		case HAL_PRIME_CHNL_OFFSET_LOWER:
++			pframe = rtw_tdls_set_second_channel_offset(pframe, pattrib, SCA);
++			break;
++		case HAL_PRIME_CHNL_OFFSET_UPPER:
++			pframe = rtw_tdls_set_second_channel_offset(pframe, pattrib, SCB);
++			break;
++		}
++	}
++
++	if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
++		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
++	else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
++		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
++
++	pframe = rtw_tdls_set_ch_sw(pframe, pattrib, ptdls_sta);
++
++}
++
++void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
++{
++
++	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
++	struct sta_priv	*pstapriv = &padapter->stapriv;
++
++	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
++	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
++	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
++	pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt);
++
++	if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
++		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
++	else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
++		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
++
++	pframe = rtw_tdls_set_ch_sw(pframe, pattrib, ptdls_sta);
++}
++#endif
++
++#ifdef CONFIG_WFD
++void rtw_build_tunneled_probe_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe)
++{
++	u8 i;
++	_adapter *iface = NULL;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct pkt_attrib *pattrib = &pxmitframe->attrib;
++	struct wifidirect_info *pwdinfo;
++
++	u8 category = RTW_WLAN_CATEGORY_P2P;
++	u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a};
++	u8 probe_req = 4;
++	u8 wfdielen = 0;
++
++	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 3, WFA_OUI, &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(probe_req), &(pattrib->pktlen));
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if ((iface) && rtw_is_adapter_up(iface)) {
++			pwdinfo = &iface->wdinfo;
++			if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
++				wfdielen = build_probe_req_wfd_ie(pwdinfo, pframe);
++				pframe += wfdielen;
++				pattrib->pktlen += wfdielen;
++			}
++		}
++	}
++}
++
++void rtw_build_tunneled_probe_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe)
++{
++	u8 i;
++	_adapter *iface = NULL;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
++	struct wifidirect_info *pwdinfo;
++	u8 category = RTW_WLAN_CATEGORY_P2P;
++	u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a};
++	u8 probe_rsp = 5;
++	u8 wfdielen = 0;
++
++	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 3, WFA_OUI, &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(probe_rsp), &(pattrib->pktlen));
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if ((iface) && rtw_is_adapter_up(iface)) {
++			pwdinfo = &iface->wdinfo;
++			if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
++				wfdielen = build_probe_resp_wfd_ie(pwdinfo, pframe, 1);
++				pframe += wfdielen;
++				pattrib->pktlen += wfdielen;
++			}
++		}
++	}
++}
++#endif /* CONFIG_WFD */
++
++void _tdls_tpk_timer_hdl(void *FunctionContext)
++{
++	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
++	struct tdls_txmgmt txmgmt;
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++	ptdls_sta->TPK_count++;
++	/* TPK_timer expired in a second */
++	/* Retry timer should set at least 301 sec. */
++	if (ptdls_sta->TPK_count >= (ptdls_sta->TDLS_PeerKey_Lifetime - 3)) {
++		RTW_INFO("[TDLS] %s, Re-Setup TDLS link with "MAC_FMT" since TPK lifetime expires!\n",
++			__FUNCTION__, MAC_ARG(ptdls_sta->cmn.mac_addr));
++		ptdls_sta->TPK_count = 0;
++		_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
++		issue_tdls_setup_req(ptdls_sta->padapter, &txmgmt, _FALSE);
++	}
++
++	_set_timer(&ptdls_sta->TPK_timer, ONE_SEC);
++}
++
++#ifdef CONFIG_TDLS_CH_SW
++void _tdls_ch_switch_timer_hdl(void *FunctionContext)
++{
++	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
++	_adapter *padapter = ptdls_sta->padapter;
++	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
++
++	rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL);
++	RTW_INFO("[TDLS] %s, can't get traffic from op_ch:%d\n", __func__, rtw_get_oper_ch(padapter));
++}
++
++void _tdls_delay_timer_hdl(void *FunctionContext)
++{
++	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
++	_adapter *padapter = ptdls_sta->padapter;
++	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
++
++	RTW_INFO("[TDLS] %s, op_ch:%d, tdls_state:0x%08x\n", __func__, rtw_get_oper_ch(padapter), ptdls_sta->tdls_sta_state);
++	pchsw_info->delay_switch_back = _TRUE;
++}
++
++void _tdls_stay_on_base_chnl_timer_hdl(void *FunctionContext)
++{
++	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
++	_adapter *padapter = ptdls_sta->padapter;
++	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
++
++	if (ptdls_sta != NULL) {
++		issue_tdls_ch_switch_req(padapter, ptdls_sta);
++		pchsw_info->ch_sw_state |= TDLS_WAIT_CH_RSP_STATE;
++	}
++}
++
++void _tdls_ch_switch_monitor_timer_hdl(void *FunctionContext)
++{
++	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
++	_adapter *padapter = ptdls_sta->padapter;
++	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
++
++	rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END);
++	RTW_INFO("[TDLS] %s, does not receive ch sw req\n", __func__);
++}
++
++#endif
++
++void _tdls_handshake_timer_hdl(void *FunctionContext)
++{
++	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
++	_adapter *padapter = NULL;
++	struct tdls_txmgmt txmgmt;
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++	_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
++	txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;
++
++	if (ptdls_sta != NULL) {
++		padapter = ptdls_sta->padapter;
++
++		RTW_INFO("[TDLS] Handshake time out\n");
++		if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)
++			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA);
++		else
++			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY);
++	}
++}
++
++void _tdls_pti_timer_hdl(void *FunctionContext)
++{
++	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
++	_adapter *padapter = NULL;
++	struct tdls_txmgmt txmgmt;
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++	_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
++	txmgmt.status_code = _RSON_TDLS_TEAR_TOOFAR_;
++
++	if (ptdls_sta != NULL) {
++		padapter = ptdls_sta->padapter;
++
++		if (ptdls_sta->tdls_sta_state & TDLS_WAIT_PTR_STATE) {
++			RTW_INFO("[TDLS] Doesn't receive PTR from peer dev:"MAC_FMT"; "
++				"Send TDLS Tear Down\n", MAC_ARG(ptdls_sta->cmn.mac_addr));
++			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA);
++		}
++	}
++}
++
++void rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta)
++{
++	psta->padapter = padapter;
++	rtw_init_timer(&psta->TPK_timer, padapter, _tdls_tpk_timer_hdl, psta);
++#ifdef CONFIG_TDLS_CH_SW
++	rtw_init_timer(&psta->ch_sw_timer, padapter, _tdls_ch_switch_timer_hdl, psta);
++	rtw_init_timer(&psta->delay_timer, padapter, _tdls_delay_timer_hdl, psta);
++	rtw_init_timer(&psta->stay_on_base_chnl_timer, padapter, _tdls_stay_on_base_chnl_timer_hdl, psta);
++	rtw_init_timer(&psta->ch_sw_monitor_timer, padapter, _tdls_ch_switch_monitor_timer_hdl, psta);
++#endif
++	rtw_init_timer(&psta->handshake_timer, padapter, _tdls_handshake_timer_hdl, psta);
++	rtw_init_timer(&psta->pti_timer, padapter, _tdls_pti_timer_hdl, psta);
++}
++
++void rtw_cancel_tdls_timer(struct sta_info *psta)
++{
++	_cancel_timer_ex(&psta->TPK_timer);
++#ifdef CONFIG_TDLS_CH_SW
++	_cancel_timer_ex(&psta->ch_sw_timer);
++	_cancel_timer_ex(&psta->delay_timer);
++	_cancel_timer_ex(&psta->stay_on_base_chnl_timer);
++	_cancel_timer_ex(&psta->ch_sw_monitor_timer);
++#endif
++	_cancel_timer_ex(&psta->handshake_timer);
++	_cancel_timer_ex(&psta->pti_timer);
++}
++
++void rtw_tdls_teardown_pre_hdl(_adapter *padapter, struct sta_info *psta)
++{
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	_irqL irqL;
++
++	rtw_cancel_tdls_timer(psta);
++
++	_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++	if (ptdlsinfo->sta_cnt != 0)
++		ptdlsinfo->sta_cnt--;
++	_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
++
++	if (ptdlsinfo->sta_cnt < MAX_ALLOWED_TDLS_STA_NUM) {
++		ptdlsinfo->sta_maximum = _FALSE;
++		_rtw_memset(&ptdlsinfo->ss_record, 0x00, sizeof(struct tdls_ss_record));
++	}
++
++	if (ptdlsinfo->sta_cnt == 0)
++		rtw_tdls_set_link_established(padapter, _FALSE);
++	else
++		RTW_INFO("Remain tdls sta:%02x\n", ptdlsinfo->sta_cnt);
++}
++
++void rtw_tdls_teardown_post_hdl(_adapter *padapter, struct sta_info *psta, u8 enqueue_cmd)
++{
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++
++	/* Clear cam */
++	rtw_clearstakey_cmd(padapter, psta, enqueue_cmd);
++
++	/* Update sta media status */
++	if (enqueue_cmd)
++		rtw_sta_media_status_rpt_cmd(padapter, psta, 0);
++	else
++		rtw_sta_media_status_rpt(padapter, psta, 0);
++
++	/* Set RCR if necessary */
++	if (ptdlsinfo->sta_cnt == 0) {
++		if (enqueue_cmd)
++			rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR);
++		else
++			rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_NOLINK);
++	}
++
++	/* Free tdls sta info */
++	rtw_free_stainfo(padapter,  psta);
++}
++
++int rtw_tdls_is_driver_setup(_adapter *padapter)
++{
++	return padapter->tdlsinfo.driver_setup;
++}
++
++const char *rtw_tdls_action_txt(enum TDLS_ACTION_FIELD action)
++{
++	switch (action) {
++	case TDLS_SETUP_REQUEST:
++		return "TDLS_SETUP_REQUEST";
++	case TDLS_SETUP_RESPONSE:
++		return "TDLS_SETUP_RESPONSE";
++	case TDLS_SETUP_CONFIRM:
++		return "TDLS_SETUP_CONFIRM";
++	case TDLS_TEARDOWN:
++		return "TDLS_TEARDOWN";
++	case TDLS_PEER_TRAFFIC_INDICATION:
++		return "TDLS_PEER_TRAFFIC_INDICATION";
++	case TDLS_CHANNEL_SWITCH_REQUEST:
++		return "TDLS_CHANNEL_SWITCH_REQUEST";
++	case TDLS_CHANNEL_SWITCH_RESPONSE:
++		return "TDLS_CHANNEL_SWITCH_RESPONSE";
++	case TDLS_PEER_PSM_REQUEST:
++		return "TDLS_PEER_PSM_REQUEST";
++	case TDLS_PEER_PSM_RESPONSE:
++		return "TDLS_PEER_PSM_RESPONSE";
++	case TDLS_PEER_TRAFFIC_RESPONSE:
++		return "TDLS_PEER_TRAFFIC_RESPONSE";
++	case TDLS_DISCOVERY_REQUEST:
++		return "TDLS_DISCOVERY_REQUEST";
++	case TDLS_DISCOVERY_RESPONSE:
++		return "TDLS_DISCOVERY_RESPONSE";
++	default:
++		return "UNKNOWN";
++	}
++}
++
++#endif /* CONFIG_TDLS */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_vht.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_vht.c
+new file mode 100644
+index 000000000..11537e4d3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_vht.c
+@@ -0,0 +1,1134 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_VHT_C
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++#ifdef CONFIG_80211AC_VHT
++const u16 _vht_max_mpdu_len[] = {
++	3895,
++	7991,
++	11454,
++	0,
++};
++
++const u8 _vht_sup_ch_width_set_to_bw_cap[] = {
++	BW_CAP_80M,
++	BW_CAP_80M | BW_CAP_160M,
++	BW_CAP_80M | BW_CAP_160M | BW_CAP_80_80M,
++	0,
++};
++
++const char *const _vht_sup_ch_width_set_str[] = {
++	"80MHz",
++	"160MHz",
++	"160MHz & 80+80MHz",
++	"BW-RSVD",
++};
++
++void dump_vht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len)
++{
++	if (buf_len != VHT_CAP_IE_LEN) {
++		RTW_PRINT_SEL(sel, "Invalid VHT capability IE len:%d != %d\n", buf_len, VHT_CAP_IE_LEN);
++		return;
++	}
++
++	RTW_PRINT_SEL(sel, "cap_info:%02x %02x %02x %02x: MAX_MPDU_LEN:%u %s%s%s%s%s RX-STBC:%u MAX_AMPDU_LEN:%u\n"
++		, *(buf), *(buf + 1), *(buf + 2), *(buf + 3)
++		, vht_max_mpdu_len(GET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(buf))
++		, vht_sup_ch_width_set_str(GET_VHT_CAPABILITY_ELE_CHL_WIDTH(buf))
++		, GET_VHT_CAPABILITY_ELE_RX_LDPC(buf) ? " RX-LDPC" : ""
++		, GET_VHT_CAPABILITY_ELE_SHORT_GI80M(buf) ? " SGI-80" : ""
++		, GET_VHT_CAPABILITY_ELE_SHORT_GI160M(buf) ? " SGI-160" : ""
++		, GET_VHT_CAPABILITY_ELE_TX_STBC(buf) ? " TX-STBC" : ""
++		, GET_VHT_CAPABILITY_ELE_RX_STBC(buf)
++		, VHT_MAX_AMPDU_LEN(GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(buf))
++	);
++}
++
++void dump_vht_cap_ie(void *sel, const u8 *ie, u32 ie_len)
++{
++	const u8 *vht_cap_ie;
++	sint vht_cap_ielen;
++
++	vht_cap_ie = rtw_get_ie(ie, WLAN_EID_VHT_CAPABILITY, &vht_cap_ielen, ie_len);
++	if (!ie || vht_cap_ie != ie)
++		return;
++
++	dump_vht_cap_ie_content(sel, vht_cap_ie + 2, vht_cap_ielen);
++}
++
++const char *const _vht_op_ch_width_str[] = {
++	"20 or 40MHz",
++	"80MHz",
++	"160MHz",
++	"80+80MHz",
++	"BW-RSVD",
++};
++
++void dump_vht_op_ie_content(void *sel, const u8 *buf, u32 buf_len)
++{
++	if (buf_len != VHT_OP_IE_LEN) {
++		RTW_PRINT_SEL(sel, "Invalid VHT operation IE len:%d != %d\n", buf_len, VHT_OP_IE_LEN);
++		return;
++	}
++
++	RTW_PRINT_SEL(sel, "%s, ch0:%u, ch1:%u\n"
++		, vht_op_ch_width_str(GET_VHT_OPERATION_ELE_CHL_WIDTH(buf))
++		, GET_VHT_OPERATION_ELE_CENTER_FREQ1(buf)
++		, GET_VHT_OPERATION_ELE_CENTER_FREQ2(buf)
++	);
++}
++
++void dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len)
++{
++	const u8 *vht_op_ie;
++	sint vht_op_ielen;
++
++	vht_op_ie = rtw_get_ie(ie, WLAN_EID_VHT_OPERATION, &vht_op_ielen, ie_len);
++	if (!ie || vht_op_ie != ie)
++		return;
++
++	dump_vht_op_ie_content(sel, vht_op_ie + 2, vht_op_ielen);
++}
++
++/*				20/40/80,	ShortGI,	MCS Rate  */
++const u16 VHT_MCS_DATA_RATE[3][2][40] = {	/* unit: 0.5M */
++	{	{
++			13, 26, 39, 52, 78, 104, 117, 130, 156, 156,
++			26, 52, 78, 104, 156, 208, 234, 260, 312, 312,
++			39, 78, 117, 156, 234, 312, 351, 390, 468, 520,
++			52, 104, 156, 208, 312, 416, 468, 520, 624, 624,
++		},			/* Long GI, 20MHz */
++		{
++			14, 29, 43, 58, 87, 116, 130, 144, 173, 173,
++			29, 58, 87, 116, 173, 231, 260, 289, 347, 347,
++			43, 87, 130, 173, 260, 347, 390, 433, 520, 578,
++			58, 116, 173, 231, 347, 462, 520, 578, 693, 693,
++		}
++	},		/* Short GI, 20MHz */
++	{	{
++			27, 54, 81, 108, 162, 216, 243, 270, 324, 360,
++			54, 108, 162, 216, 324, 432, 486, 540, 648, 720,
++			81, 162, 243, 324, 486, 648, 729, 810, 972, 1080,
++			108, 216, 324, 432, 648, 864, 972, 1080, 1296, 1440,
++		}, 		/* Long GI, 40MHz */
++		{
++			30, 60, 90, 120, 180, 240, 270, 300, 360, 400,
++			60, 120, 180, 240, 360, 480, 540, 600, 720, 800,
++			90, 180, 270, 360, 540, 720, 810, 900, 1080, 1200,
++			120, 240, 360, 480, 720, 960, 1080, 1200, 1440, 1600,
++		}
++	},		/* Short GI, 40MHz */
++	{	{
++			59, 117, 176, 234, 351, 468, 527, 585, 702, 780,
++			117, 234, 351, 468, 702, 936, 1053, 1170, 1404, 1560,
++			176, 351, 527, 702, 1053, 1404, 1580, 1755, 2106, 2340,
++			234, 468, 702, 936, 1404, 1872, 2106, 2340, 2808, 3120,
++		},	/* Long GI, 80MHz */
++		{
++			65, 130, 195, 260, 390, 520, 585, 650, 780, 867,
++			130, 260, 390, 520, 780, 1040, 1170, 1300, 1560, 1734,
++			195, 390, 585, 780, 1170, 1560, 1755, 1950, 2340, 2600,
++			260, 520, 780, 1040, 1560, 2080, 2340, 2600, 3120, 3467,
++		}
++	}	/* Short GI, 80MHz */
++};
++
++u8	rtw_get_vht_highest_rate(u8 *pvht_mcs_map)
++{
++	u8	i, j;
++	u8	bit_map;
++	u8	vht_mcs_rate = 0;
++
++	for (i = 0; i < 2; i++) {
++		if (pvht_mcs_map[i] != 0xff) {
++			for (j = 0; j < 8; j += 2) {
++				bit_map = (pvht_mcs_map[i] >> j) & 3;
++
++				if (bit_map != 3)
++					vht_mcs_rate = MGN_VHT1SS_MCS7 + 10 * j / 2 + i * 40 + bit_map; /* VHT rate indications begin from 0x90 */
++			}
++		}
++	}
++
++	/* RTW_INFO("HighestVHTMCSRate is %x\n", vht_mcs_rate); */
++	return vht_mcs_rate;
++}
++
++u8	rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map)
++{
++	u8	i, j;
++	u8	bit_map;
++	u8	nss = 0;
++
++	for (i = 0; i < 2; i++) {
++		if (pvht_mcs_map[i] != 0xff) {
++			for (j = 0; j < 8; j += 2) {
++				bit_map = (pvht_mcs_map[i] >> j) & 3;
++
++				if (bit_map != 3)
++					nss++;
++			}
++		}
++	}
++
++	/* RTW_INFO("%s : %dSS\n", __FUNCTION__, nss); */
++	return nss;
++}
++
++void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map)
++{
++	u8	i, j;
++	u8	cur_rate, target_rate;
++
++	for (i = 0; i < 2; i++) {
++		target_mcs_map[i] = 0;
++		for (j = 0; j < 8; j += 2) {
++			cur_rate = (cur_mcs_map[i] >> j) & 3;
++			if (cur_rate == 3) /* 0x3 indicates not supported that num of SS */
++				target_rate = 3;
++			else if (nss <= ((j / 2) + i * 4))
++				target_rate = 3;
++			else
++				target_rate = cur_rate;
++
++			target_mcs_map[i] |= (target_rate << j);
++		}
++	}
++
++	/* RTW_INFO("%s : %dSS\n", __FUNCTION__, nss); */
++}
++
++u16	rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate)
++{
++	if (vht_mcs_rate > MGN_VHT4SS_MCS9)
++		vht_mcs_rate = MGN_VHT4SS_MCS9;
++	/* RTW_INFO("bw=%d, short_GI=%d, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)=%d\n", bw, short_GI, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)); */
++	return VHT_MCS_DATA_RATE[bw][short_GI][((vht_mcs_rate - MGN_VHT1SS_MCS0) & 0x3f)];
++}
++
++void	rtw_vht_use_default_setting(_adapter *padapter)
++{
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
++	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
++	BOOLEAN		bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE;
++#ifdef CONFIG_BEAMFORMING
++	BOOLEAN		bHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE;
++	u8	mu_bfer, mu_bfee;
++#endif /* CONFIG_BEAMFORMING */
++	u8 tx_nss, rx_nss;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	pvhtpriv->sgi_80m = TEST_FLAG(pregistrypriv->short_gi, BIT2) ? _TRUE : _FALSE;
++
++	/* LDPC support */
++	rtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport);
++	CLEAR_FLAGS(pvhtpriv->ldpc_cap);
++	if (bHwLDPCSupport) {
++		if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT0))
++			SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX);
++	}
++	rtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport);
++	if (bHwLDPCSupport) {
++		if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT1))
++			SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX);
++	}
++	if (pvhtpriv->ldpc_cap)
++		RTW_INFO("[VHT] Support LDPC = 0x%02X\n", pvhtpriv->ldpc_cap);
++
++	/* STBC */
++	rtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport);
++	CLEAR_FLAGS(pvhtpriv->stbc_cap);
++	if (bHwSTBCSupport) {
++		if (TEST_FLAG(pregistrypriv->stbc_cap, BIT1))
++			SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX);
++	}
++	rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport);
++	if (bHwSTBCSupport) {
++		if (TEST_FLAG(pregistrypriv->stbc_cap, BIT0))
++			SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX);
++	}
++	if (pvhtpriv->stbc_cap)
++		RTW_INFO("[VHT] Support STBC = 0x%02X\n", pvhtpriv->stbc_cap);
++
++	/* Beamforming setting */
++	CLEAR_FLAGS(pvhtpriv->beamform_cap);
++#ifdef CONFIG_BEAMFORMING
++#ifdef RTW_BEAMFORMING_VERSION_2
++	/* only enable beamforming in STA client mode */
++	if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter)
++				  && !MLME_IS_ADHOC(padapter)
++				  && !MLME_IS_MESH(padapter))
++#endif
++	{
++		rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER,
++			(u8 *)&bHwSupportBeamformer);
++		rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE,
++			(u8 *)&bHwSupportBeamformee);
++		mu_bfer = _FALSE;
++		mu_bfee = _FALSE;
++		rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMER, &mu_bfer);
++		rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMEE, &mu_bfee);
++		if (TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer) {
++#ifdef CONFIG_CONCURRENT_MODE
++			if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
++				SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
++				RTW_INFO("[VHT] CONCURRENT AP Support Beamformer\n");
++				if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2))
++				    && (_TRUE == mu_bfer)) {
++					SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
++					RTW_INFO("[VHT] Support MU-MIMO AP\n");
++				}
++			} else
++				RTW_INFO("[VHT] CONCURRENT not AP ;not allow  Support Beamformer\n");
++#else
++			SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
++			RTW_INFO("[VHT] Support Beamformer\n");
++			if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2))
++			    && (_TRUE == mu_bfer)
++			    && ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {
++				SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
++				RTW_INFO("[VHT] Support MU-MIMO AP\n");
++			}
++#endif
++		}
++		if (TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee) {
++			SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
++			RTW_INFO("[VHT] Support Beamformee\n");
++			if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(3))
++			    && (_TRUE == mu_bfee)
++			    && ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)) {
++				SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);
++				RTW_INFO("[VHT] Support MU-MIMO STA\n");
++			}
++		}
++	}
++#endif /* CONFIG_BEAMFORMING */
++
++	pvhtpriv->ampdu_len = pregistrypriv->ampdu_factor;
++
++	tx_nss = GET_HAL_TX_NSS(padapter);
++	rx_nss = GET_HAL_RX_NSS(padapter);
++
++	/* for now, vhtpriv.vht_mcs_map comes from RX NSS */
++	rtw_vht_nss_to_mcsmap(rx_nss, pvhtpriv->vht_mcs_map, pregistrypriv->vht_rx_mcs_map);
++	pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map);
++}
++
++u64	rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss)
++{
++	u8 i, j, tmp;
++	u64 bitmap = 0;
++	u8 bits_nss = nss * 2;
++
++	for (i = j = 0; i < bits_nss; i += 2, j += 10) {
++		/* every two bits means single sptial stream */
++		tmp = (mcs_map[i / 8] >> i) & 3;
++
++		switch (tmp) {
++		case 2:
++			bitmap = bitmap | (0x03ff << j);
++			break;
++		case 1:
++			bitmap = bitmap | (0x01ff << j);
++			break;
++		case 0:
++			bitmap = bitmap | (0x00ff << j);
++			break;
++		default:
++			break;
++		}
++	}
++
++	RTW_INFO("vht_mcs_map=%02x %02x, nss=%u => bitmap=%016llx\n"
++		, mcs_map[0], mcs_map[1], nss, bitmap);
++
++	return bitmap;
++}
++
++#ifdef CONFIG_BEAMFORMING
++void update_sta_vht_info_apmode_bf_cap(_adapter *padapter, struct sta_info *psta)
++{
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	struct vht_priv	*pvhtpriv_ap = &pmlmepriv->vhtpriv;
++	struct vht_priv	*pvhtpriv_sta = &psta->vhtpriv;
++	u16	cur_beamform_cap = 0;
++
++	/* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */
++	if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
++	    GET_VHT_CAPABILITY_ELE_SU_BFEE(pvhtpriv_sta->vht_cap)) {
++		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
++		/*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/
++		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pvhtpriv_sta->vht_cap) << 8);
++	}
++
++	/* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */
++	if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
++	    GET_VHT_CAPABILITY_ELE_SU_BFER(pvhtpriv_sta->vht_cap)) {
++		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
++		/*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/
++		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pvhtpriv_sta->vht_cap) << 12);
++	}
++
++	if (cur_beamform_cap)
++		RTW_INFO("Current STA(%d) VHT Beamforming Setting = %02X\n", psta->cmn.aid, cur_beamform_cap);
++
++	pvhtpriv_sta->beamform_cap = cur_beamform_cap;
++	psta->cmn.bf_info.vht_beamform_cap = cur_beamform_cap;
++}
++#endif
++
++void	update_sta_vht_info_apmode(_adapter *padapter, void *sta)
++{
++	struct sta_info	*psta = (struct sta_info *)sta;
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct vht_priv	*pvhtpriv_ap = &pmlmepriv->vhtpriv;
++	struct vht_priv	*pvhtpriv_sta = &psta->vhtpriv;
++	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0;
++	s8 bw_mode = -1;
++	u8	*pcap_mcs;
++
++	if (pvhtpriv_sta->vht_option == _FALSE)
++		return;
++
++	if (pvhtpriv_sta->op_present) {
++		switch (GET_VHT_OPERATION_ELE_CHL_WIDTH(pvhtpriv_sta->vht_op)) {
++		case 1: /* 80MHz */
++		case 2: /* 160MHz */
++		case 3: /* 80+80 */
++			bw_mode = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */
++			break;
++		}
++	}
++
++	if (pvhtpriv_sta->notify_present)
++		bw_mode = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&pvhtpriv_sta->vht_op_mode_notify);
++	else if (MLME_IS_AP(padapter)) {
++		/* for VHT client without Operating Mode Notify IE; minimal 80MHz */
++		if (bw_mode < CHANNEL_WIDTH_80)
++			bw_mode = CHANNEL_WIDTH_80;
++	}
++
++	if (bw_mode != -1)
++		psta->cmn.bw_mode = bw_mode; /* update bw_mode only if get value from VHT IEs */
++
++	psta->cmn.ra_info.is_vht_enable = _TRUE;
++
++	/* B4 Rx LDPC */
++	if (TEST_FLAG(pvhtpriv_ap->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
++	    GET_VHT_CAPABILITY_ELE_RX_LDPC(pvhtpriv_sta->vht_cap)) {
++		SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
++		RTW_INFO("Current STA(%d) VHT LDPC = %02X\n", psta->cmn.aid, cur_ldpc_cap);
++	}
++	pvhtpriv_sta->ldpc_cap = cur_ldpc_cap;
++
++	if (psta->cmn.bw_mode > pmlmeext->cur_bwmode)
++		psta->cmn.bw_mode = pmlmeext->cur_bwmode;
++
++	if (psta->cmn.bw_mode == CHANNEL_WIDTH_80) {
++		/* B5 Short GI for 80 MHz */
++		pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;
++		/* RTW_INFO("Current STA ShortGI80MHz = %d\n", pvhtpriv_sta->sgi_80m); */
++	} else if (psta->cmn.bw_mode >= CHANNEL_WIDTH_160) {
++		/* B5 Short GI for 80 MHz */
++		pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;
++		/* RTW_INFO("Current STA ShortGI160MHz = %d\n", pvhtpriv_sta->sgi_80m); */
++	}
++
++	/* B8 B9 B10 Rx STBC */
++	if (TEST_FLAG(pvhtpriv_ap->stbc_cap, STBC_VHT_ENABLE_TX) &&
++	    GET_VHT_CAPABILITY_ELE_RX_STBC(pvhtpriv_sta->vht_cap)) {
++		SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
++		RTW_INFO("Current STA(%d) VHT STBC = %02X\n", psta->cmn.aid, cur_stbc_cap);
++	}
++	pvhtpriv_sta->stbc_cap = cur_stbc_cap;
++
++#ifdef CONFIG_BEAMFORMING
++	update_sta_vht_info_apmode_bf_cap(padapter, psta);
++#endif
++
++	/* B23 B24 B25 Maximum A-MPDU Length Exponent */
++	pvhtpriv_sta->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pvhtpriv_sta->vht_cap);
++
++	pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pvhtpriv_sta->vht_cap);
++	_rtw_memcpy(pvhtpriv_sta->vht_mcs_map, pcap_mcs, 2);
++	pvhtpriv_sta->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv_sta->vht_mcs_map);
++}
++
++void	update_hw_vht_param(_adapter *padapter)
++{
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8	ht_AMPDU_len;
++
++	ht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
++
++	if (pvhtpriv->ampdu_len > ht_AMPDU_len)
++		rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len));
++}
++
++#ifdef ROKU_PRIVATE
++u8 VHT_get_ss_from_map(u8 *vht_mcs_map)
++{
++	u8 i, j;
++	u8 ss = 0;
++
++	for (i = 0; i < 2; i++) {
++		if (vht_mcs_map[i] != 0xff) {
++			for (j = 0; j < 8; j += 2) {
++				if (((vht_mcs_map[i] >> j) & 0x03) == 0x03)
++					break;
++				ss++;
++			}
++		}
++
++	}
++
++return ss;
++}
++
++void VHT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct vht_priv_infra_ap	*pvhtpriv = &pmlmepriv->vhtpriv_infra_ap;
++	u8      cur_stbc_cap_infra_ap = 0;
++	u16	cur_beamform_cap_infra_ap = 0;
++	u8	*pcap_mcs;
++	u8	*pcap_mcs_tx;
++	u8	Rx_ss = 0, Tx_ss = 0;
++
++	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info		*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	if (pIE == NULL)
++		return;
++
++	pmlmeinfo->ht_vht_received |= BIT(1);
++
++	pvhtpriv->ldpc_cap_infra_ap = GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data);
++
++	if (GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data))
++		SET_FLAG(cur_stbc_cap_infra_ap, STBC_VHT_ENABLE_RX);
++	if (GET_VHT_CAPABILITY_ELE_TX_STBC(pIE->data))
++		SET_FLAG(cur_stbc_cap_infra_ap, STBC_VHT_ENABLE_TX);
++	pvhtpriv->stbc_cap_infra_ap = cur_stbc_cap_infra_ap;
++
++	/*store ap info for channel bandwidth*/
++	pvhtpriv->channel_width_infra_ap = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(pIE->data);
++
++	/*check B11: SU Beamformer Capable and B12: SU Beamformee B19: MU Beamformer B20:MU Beamformee*/
++	if (GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data))
++		SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
++	if (GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data))
++		SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
++	if (GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data))
++		SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
++	if (GET_VHT_CAPABILITY_ELE_MU_BFEE(pIE->data))
++		SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);
++	pvhtpriv->beamform_cap_infra_ap = cur_beamform_cap_infra_ap;
++
++	/*store information about vht_mcs_set*/
++	pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data);
++	pcap_mcs_tx = GET_VHT_CAPABILITY_ELE_TX_MCS(pIE->data);
++	_rtw_memcpy(pvhtpriv->vht_mcs_map_infra_ap, pcap_mcs, 2);
++	_rtw_memcpy(pvhtpriv->vht_mcs_map_tx_infra_ap, pcap_mcs_tx, 2);
++
++	Rx_ss = VHT_get_ss_from_map(pvhtpriv->vht_mcs_map_infra_ap);
++	Tx_ss = VHT_get_ss_from_map(pvhtpriv->vht_mcs_map_tx_infra_ap);
++	if (Rx_ss >= Tx_ss) {
++		pvhtpriv->number_of_streams_infra_ap = Rx_ss;
++	} else{
++		pvhtpriv->number_of_streams_infra_ap = Tx_ss;
++	}
++
++}
++#endif /* ROKU_PRIVATE */
++
++void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0, rx_nss = 0;
++	u16	cur_beamform_cap = 0;
++	u8	*pcap_mcs;
++
++	if (pIE == NULL)
++		return;
++
++	if (pvhtpriv->vht_option == _FALSE)
++		return;
++
++	pmlmeinfo->VHT_enable = 1;
++
++	/* B4 Rx LDPC */
++	if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
++	    GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data)) {
++		SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
++		RTW_INFO("Current VHT LDPC Setting = %02X\n", cur_ldpc_cap);
++	}
++	pvhtpriv->ldpc_cap = cur_ldpc_cap;
++
++	/* B5 Short GI for 80 MHz */
++	pvhtpriv->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pIE->data) & pvhtpriv->sgi_80m) ? _TRUE : _FALSE;
++	/* RTW_INFO("Current ShortGI80MHz = %d\n", pvhtpriv->sgi_80m); */
++
++	/* B8 B9 B10 Rx STBC */
++	if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX) &&
++	    GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data)) {
++		SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
++		RTW_INFO("Current VHT STBC Setting = %02X\n", cur_stbc_cap);
++	}
++	pvhtpriv->stbc_cap = cur_stbc_cap;
++#ifdef CONFIG_BEAMFORMING
++#ifdef RTW_BEAMFORMING_VERSION_2
++	/*
++	 * B11 SU Beamformer Capable,
++	 * the target supports Beamformer and we are Beamformee
++	 */
++	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)
++	    && GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data)) {
++		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
++
++		/* Shift to BEAMFORMING_VHT_BEAMFORMEE_STS_CAP */
++		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pIE->data) << 8);
++
++		/*
++		 * B19 MU Beamformer Capable,
++		 * the target supports Beamformer and we are Beamformee
++		 */
++		if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)
++		    && GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data))
++			SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);
++	}
++
++	/*
++	 * B12 SU Beamformee Capable,
++	 * the target supports Beamformee and we are Beamformer
++	 */
++	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)
++	    && GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data)) {
++		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
++
++		/* Shit to BEAMFORMING_VHT_BEAMFORMER_SOUND_DIM */
++		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data) << 12);
++
++		/*
++		 * B20 MU Beamformee Capable,
++		 * the target supports Beamformee and we are Beamformer
++		 */
++		if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)
++		    && GET_VHT_CAPABILITY_ELE_MU_BFEE(pIE->data))
++			SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
++	}
++
++	pvhtpriv->beamform_cap = cur_beamform_cap;
++	RTW_INFO("Current VHT Beamforming Setting=0x%04X\n", cur_beamform_cap);
++#else /* !RTW_BEAMFORMING_VERSION_2 */
++	/* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */
++	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
++	    GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data)) {
++		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
++		/*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/
++		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pIE->data) << 8);
++	}
++
++	/* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */
++	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
++	    GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data)) {
++		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
++		/*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/
++		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data) << 12);
++
++	}
++	pvhtpriv->beamform_cap = cur_beamform_cap;
++	if (cur_beamform_cap)
++		RTW_INFO("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap);
++#endif /* !RTW_BEAMFORMING_VERSION_2 */
++#endif /* CONFIG_BEAMFORMING */
++	/* B23 B24 B25 Maximum A-MPDU Length Exponent */
++	pvhtpriv->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pIE->data);
++
++	pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data);
++	rx_nss = GET_HAL_RX_NSS(padapter);
++	rtw_vht_nss_to_mcsmap(rx_nss, pvhtpriv->vht_mcs_map, pcap_mcs);
++	pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map);
++}
++
++void VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
++
++	if (pIE == NULL)
++		return;
++
++	if (pvhtpriv->vht_option == _FALSE)
++		return;
++}
++
++void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, void *sta)
++{
++	struct sta_info		*psta = (struct sta_info *)sta;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
++	struct registry_priv *regsty = adapter_to_regsty(padapter);
++	u8	target_bw;
++	u8	target_rxss, current_rxss;
++	u8	update_ra = _FALSE;
++	u8 tx_nss = 0;
++
++	if (pvhtpriv->vht_option == _FALSE)
++		return;
++
++	target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(pframe);
++	tx_nss = GET_HAL_TX_NSS(padapter);
++	target_rxss = rtw_min(tx_nss, (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(pframe) + 1));
++
++	if (target_bw != psta->cmn.bw_mode) {
++		if (hal_is_bw_support(padapter, target_bw)
++		    && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw)
++		   ) {
++			update_ra = _TRUE;
++			psta->cmn.bw_mode = target_bw;
++		}
++	}
++
++	current_rxss = rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map);
++	if (target_rxss != current_rxss) {
++		u8	vht_mcs_map[2] = {};
++
++		update_ra = _TRUE;
++
++		rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, psta->vhtpriv.vht_mcs_map);
++		_rtw_memcpy(psta->vhtpriv.vht_mcs_map, vht_mcs_map, 2);
++
++		rtw_hal_update_sta_ra_info(padapter, psta);
++	}
++
++	if (update_ra)
++		rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta);
++}
++
++u32	rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel)
++{
++	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
++	/* struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv; */
++	u8	ChnlWidth, center_freq, bw_mode;
++	u32	len = 0;
++	u8	operation[5];
++
++	_rtw_memset(operation, 0, 5);
++
++	bw_mode = REGSTY_BW_5G(pregistrypriv); /* TODO: control op bw with other info */
++
++	if (hal_chk_bw_cap(padapter, BW_CAP_80M | BW_CAP_160M)
++	    && REGSTY_BW_5G(pregistrypriv) >= CHANNEL_WIDTH_80
++	   ) {
++		center_freq = rtw_get_center_ch(channel, bw_mode, HAL_PRIME_CHNL_OFFSET_LOWER);
++		ChnlWidth = 1;
++	} else {
++		center_freq = 0;
++		ChnlWidth = 0;
++	}
++
++
++	SET_VHT_OPERATION_ELE_CHL_WIDTH(operation, ChnlWidth);
++	/* center frequency */
++	SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(operation, center_freq);/* Todo: need to set correct center channel */
++	SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(operation, 0);
++
++	_rtw_memcpy(operation + 3, pvhtpriv->vht_mcs_map, 2);
++
++	rtw_set_ie(pbuf, EID_VHTOperation, 5, operation, &len);
++
++	return len;
++}
++
++u32	rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw)
++{
++	/* struct registry_priv *pregistrypriv = &padapter->registrypriv; */
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct vht_priv	*pvhtpriv = &pmlmepriv->vhtpriv;
++	u32	len = 0;
++	u8	opmode = 0;
++	u8	chnl_width, rx_nss;
++
++	chnl_width = bw;
++	rx_nss = rtw_vht_mcsmap_to_nss(pvhtpriv->vht_mcs_map);
++
++	SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&opmode, chnl_width);
++	SET_VHT_OPERATING_MODE_FIELD_RX_NSS(&opmode, (rx_nss - 1));
++	SET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(&opmode, 0); /* Todo */
++
++	pvhtpriv->vht_op_mode_notify = opmode;
++
++	pbuf = rtw_set_ie(pbuf, EID_OpModeNotification, 1, &opmode, &len);
++
++	return len;
++}
++
++u32	rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)
++{
++	u8	bw, rf_num, rx_stbc_nss = 0;
++	u16	HighestRate;
++	u8	*pcap, *pcap_mcs;
++	u32	len = 0;
++	u32 rx_packet_offset, max_recvbuf_sz;
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct vht_priv	*pvhtpriv = &pmlmepriv->vhtpriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	pcap = pvhtpriv->vht_cap;
++	_rtw_memset(pcap, 0, 32);
++
++	/* B0 B1 Maximum MPDU Length */
++	rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset);
++	rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz);
++
++	RTW_DBG("%s, line%d, Available RX buf size = %d bytes\n", __FUNCTION__, __LINE__, max_recvbuf_sz - rx_packet_offset);
++
++	if ((max_recvbuf_sz - rx_packet_offset) >= 11454) {
++		SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 2);
++		RTW_INFO("%s, line%d, Set MAX MPDU len = 11454 bytes\n", __FUNCTION__, __LINE__);
++	} else if ((max_recvbuf_sz - rx_packet_offset) >= 7991) {
++		SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 1);
++		RTW_INFO("%s, line%d, Set MAX MPDU len = 7991 bytes\n", __FUNCTION__, __LINE__);
++	} else if ((max_recvbuf_sz - rx_packet_offset) >= 3895) {
++		SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 0);
++		RTW_INFO("%s, line%d, Set MAX MPDU len = 3895 bytes\n", __FUNCTION__, __LINE__);
++	} else
++		RTW_ERR("%s, line%d, Error!! Available RX buf size < 3895 bytes\n", __FUNCTION__, __LINE__);
++
++	/* B2 B3 Supported Channel Width Set */
++	if (hal_chk_bw_cap(padapter, BW_CAP_160M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_160)) {
++		if (hal_chk_bw_cap(padapter, BW_CAP_80_80M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_80_80))
++			SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 2);
++		else
++			SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 1);
++	} else
++		SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 0);
++
++	/* B4 Rx LDPC */
++	if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) {
++		SET_VHT_CAPABILITY_ELE_RX_LDPC(pcap, 1);
++		RTW_INFO("[VHT] Declare supporting RX LDPC\n");
++	}
++
++	/* B5 ShortGI for 80MHz */
++	SET_VHT_CAPABILITY_ELE_SHORT_GI80M(pcap, pvhtpriv->sgi_80m ? 1 : 0); /* We can receive Short GI of 80M */
++	if (pvhtpriv->sgi_80m)
++		RTW_INFO("[VHT] Declare supporting SGI 80MHz\n");
++
++	/* B6 ShortGI for 160MHz */
++	/* SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pcap, pvhtpriv->sgi_80m? 1 : 0); */
++
++	/* B7 Tx STBC */
++	if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) {
++		SET_VHT_CAPABILITY_ELE_TX_STBC(pcap, 1);
++		RTW_INFO("[VHT] Declare supporting TX STBC\n");
++	}
++
++	/* B8 B9 B10 Rx STBC */
++	if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) {
++		rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss));
++
++		SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, rx_stbc_nss);
++		RTW_INFO("[VHT] Declare supporting RX STBC = %d\n", rx_stbc_nss);
++	}
++	#ifdef CONFIG_BEAMFORMING
++	/* B11 SU Beamformer Capable */
++	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
++		SET_VHT_CAPABILITY_ELE_SU_BFER(pcap, 1);
++		RTW_INFO("[VHT] Declare supporting SU Bfer\n");
++		/* B16 17 18 Number of Sounding Dimensions */
++		rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num);
++		SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(pcap, rf_num);
++		/* B19 MU Beamformer Capable */
++		if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) {
++			SET_VHT_CAPABILITY_ELE_MU_BFER(pcap, 1);
++			RTW_INFO("[VHT] Declare supporting MU Bfer\n");
++		}
++	}
++
++	/* B12 SU Beamformee Capable */
++	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {
++		SET_VHT_CAPABILITY_ELE_SU_BFEE(pcap, 1);
++		RTW_INFO("[VHT] Declare supporting SU Bfee\n");
++
++		rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);
++
++		/* IOT action suggested by Yu Chen 2017/3/3 */
++#ifdef CONFIG_80211AC_VHT
++		if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) &&
++			!pvhtpriv->ap_bf_cap.is_mu_bfer &&
++			pvhtpriv->ap_bf_cap.su_sound_dim == 2)
++			rf_num = (rf_num >= 2 ? 2 : rf_num);
++#endif
++		/* B13 14 15 Compressed Steering Number of Beamformer Antennas Supported */
++		SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(pcap, rf_num);
++		/* B20 SU Beamformee Capable */
++		if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) {
++			SET_VHT_CAPABILITY_ELE_MU_BFEE(pcap, 1);
++			RTW_INFO("[VHT] Declare supporting MU Bfee\n");
++		}
++	}
++	#endif/*CONFIG_BEAMFORMING*/
++
++	/* B21 VHT TXOP PS */
++	SET_VHT_CAPABILITY_ELE_TXOP_PS(pcap, 0);
++	/* B22 +HTC-VHT Capable */
++	SET_VHT_CAPABILITY_ELE_HTC_VHT(pcap, 1);
++	/* B23 24 25 Maximum A-MPDU Length Exponent */
++	if (pregistrypriv->ampdu_factor != 0xFE)
++		SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, pregistrypriv->ampdu_factor);
++	else
++		SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, 7);
++	/* B26 27 VHT Link Adaptation Capable */
++	SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(pcap, 0);
++
++	pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pcap);
++	_rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2);
++
++	pcap_mcs = GET_VHT_CAPABILITY_ELE_TX_MCS(pcap);
++	_rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2);
++
++	/* find the largest bw supported by both registry and hal */
++	bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv));
++
++	HighestRate = VHT_MCS_DATA_RATE[bw][pvhtpriv->sgi_80m][((pvhtpriv->vht_highest_rate - MGN_VHT1SS_MCS0) & 0x3f)];
++	HighestRate = (HighestRate + 1) >> 1;
++
++	SET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(pcap, HighestRate); /* indicate we support highest rx rate is 600Mbps. */
++	SET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(pcap, HighestRate); /* indicate we support highest tx rate is 600Mbps. */
++
++	pbuf = rtw_set_ie(pbuf, EID_VHTCapability, 12, pcap, &len);
++
++	return len;
++}
++
++u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	RT_CHANNEL_INFO *chset = rfctl->channel_set;
++	u32	ielen;
++	u8 max_bw;
++	u8 oper_ch, oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++	u8 *out_vht_op_ie, *ht_op_ie, *vht_cap_ie, *vht_op_ie;
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct vht_priv	*pvhtpriv = &pmlmepriv->vhtpriv;
++
++	rtw_vht_use_default_setting(padapter);
++
++	ht_op_ie = rtw_get_ie(in_ie + 12, WLAN_EID_HT_OPERATION, &ielen, in_len - 12);
++	if (!ht_op_ie || ielen != HT_OP_IE_LEN)
++		goto exit;
++	vht_cap_ie = rtw_get_ie(in_ie + 12, EID_VHTCapability, &ielen, in_len - 12);
++	if (!vht_cap_ie || ielen != VHT_CAP_IE_LEN)
++		goto exit;
++	vht_op_ie = rtw_get_ie(in_ie + 12, EID_VHTOperation, &ielen, in_len - 12);
++	if (!vht_op_ie || ielen != VHT_OP_IE_LEN)
++		goto exit;
++
++	/* VHT Capabilities element */
++	*pout_len += rtw_build_vht_cap_ie(padapter, out_ie + *pout_len);
++
++
++	/* VHT Operation element */
++	out_vht_op_ie = out_ie + *pout_len;
++	rtw_set_ie(out_vht_op_ie, EID_VHTOperation, VHT_OP_IE_LEN, vht_op_ie + 2 , pout_len);
++
++	/* get primary channel from HT_OP_IE */
++	oper_ch = GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2);
++
++	/* find the largest bw supported by both registry and hal */
++	max_bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv));
++
++	if (max_bw >= CHANNEL_WIDTH_40) {
++		/* get bw offset form HT_OP_IE */
++		if (GET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2)) {
++			switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2)) {
++			case SCA:
++				oper_bw = CHANNEL_WIDTH_40;
++				oper_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++				break;
++			case SCB:
++				oper_bw = CHANNEL_WIDTH_40;
++				oper_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++				break;
++			}
++		}
++
++		if (oper_bw == CHANNEL_WIDTH_40) {
++			switch (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2)) {
++			case 1: /* 80MHz */
++			case 2: /* 160MHz */
++			case 3: /* 80+80 */
++				oper_bw = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */
++				break;
++			}
++
++			oper_bw = rtw_min(oper_bw, max_bw);
++
++			/* try downgrage bw to fit in channel plan setting */
++			while (!rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset, 1, 1)
++				|| (IS_DFS_SLAVE_WITH_RD(rfctl)
++					&& !rtw_rfctl_dfs_domain_unknown(rfctl)
++					&& rtw_chset_is_chbw_non_ocp(chset, oper_ch, oper_bw, oper_offset))
++			) {
++				oper_bw--;
++				if (oper_bw == CHANNEL_WIDTH_20) {
++					oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++					break;
++				}
++			}
++		}
++	}
++
++	rtw_warn_on(!rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset, 1, 1));
++	if (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_rfctl_dfs_domain_unknown(rfctl))
++		rtw_warn_on(rtw_chset_is_chbw_non_ocp(chset, oper_ch, oper_bw, oper_offset));
++
++	/* update VHT_OP_IE */
++	if (oper_bw < CHANNEL_WIDTH_80) {
++		SET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 0);
++		SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, 0);
++		SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0);
++	} else if (oper_bw == CHANNEL_WIDTH_80) {
++		u8 cch = rtw_get_center_ch(oper_ch, oper_bw, oper_offset);
++
++		SET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 1);
++		SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, cch);
++		SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0);
++	} else {
++		RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(padapter), oper_bw);
++		rtw_warn_on(1);
++	}
++
++	/* Operating Mode Notification element */
++	*pout_len += rtw_build_vht_op_mode_notify_ie(padapter, out_ie + *pout_len, oper_bw);
++
++	pvhtpriv->vht_option = _TRUE;
++
++exit:
++	return pvhtpriv->vht_option;
++
++}
++
++void VHTOnAssocRsp(_adapter *padapter)
++{
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8	ht_AMPDU_len;
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	if (!pmlmeinfo->HT_enable)
++		return;
++
++	if (!pmlmeinfo->VHT_enable)
++		return;
++
++	ht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
++
++	if (pvhtpriv->ampdu_len > ht_AMPDU_len)
++		rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len));
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MAX_TIME, (u8 *)(&pvhtpriv->vht_highest_rate));
++}
++
++void rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pnetwork)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	u8 cap_len, operation_len;
++	uint len = 0;
++	sint ie_len = 0;
++	u8 *p = NULL;
++
++	p = rtw_get_ie(pnetwork->IEs + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len,
++			(pnetwork->IELength - _BEACON_IE_OFFSET_));
++	if (p && ie_len > 0)
++		return;
++
++	rtw_vht_use_default_setting(padapter);
++
++	/* VHT Operation mode notifiy bit in Extended IE (127) */
++	SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(pmlmepriv->ext_capab_ie_data, 1);
++	pmlmepriv->ext_capab_ie_len = 10;
++	rtw_set_ie(pnetwork->IEs + pnetwork->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len);
++	pnetwork->IELength += pmlmepriv->ext_capab_ie_len;
++
++	/* VHT Capabilities element */
++	cap_len = rtw_build_vht_cap_ie(padapter, pnetwork->IEs + pnetwork->IELength);
++	pnetwork->IELength += cap_len;
++
++	/* VHT Operation element */
++	operation_len = rtw_build_vht_operation_ie(padapter, pnetwork->IEs + pnetwork->IELength,
++										pnetwork->Configuration.DSConfig);
++	pnetwork->IELength += operation_len;
++
++	rtw_check_for_vht20(padapter, pnetwork->IEs + _BEACON_IE_OFFSET_, pnetwork->IELength - _BEACON_IE_OFFSET_);
++
++	pmlmepriv->vhtpriv.vht_option = _TRUE;
++}
++
++void rtw_vht_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pnetwork)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++	rtw_remove_bcn_ie(padapter, pnetwork, EID_EXTCapability);
++	rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTCapability);
++	rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTOperation);
++
++	pmlmepriv->vhtpriv.vht_option = _FALSE;
++}
++
++void rtw_check_for_vht20(_adapter *adapter, u8 *ies, int ies_len)
++{
++	u8 ht_ch, ht_bw, ht_offset;
++	u8 vht_ch, vht_bw, vht_offset;
++
++	rtw_ies_get_chbw(ies, ies_len, &ht_ch, &ht_bw, &ht_offset, 1, 0);
++	rtw_ies_get_chbw(ies, ies_len, &vht_ch, &vht_bw, &vht_offset, 1, 1);
++
++	if (ht_bw == CHANNEL_WIDTH_20 && vht_bw >= CHANNEL_WIDTH_80) {
++		u8 *vht_op_ie;
++		int vht_op_ielen;
++
++		RTW_INFO(FUNC_ADPT_FMT" vht80 is not allowed without ht40\n", FUNC_ADPT_ARG(adapter));
++		vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len);
++		if (vht_op_ie && vht_op_ielen) {
++			RTW_INFO(FUNC_ADPT_FMT" switch to vht20\n", FUNC_ADPT_ARG(adapter));
++			SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0);
++			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0);
++			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0);
++		}
++	}
++}
++#endif /* CONFIG_80211AC_VHT */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_wapi.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_wapi.c
+new file mode 100644
+index 000000000..94b26e725
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_wapi.c
+@@ -0,0 +1,1320 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifdef CONFIG_WAPI_SUPPORT
++
++#include <linux/unistd.h>
++#include <linux/etherdevice.h>
++#include <drv_types.h>
++#include <rtw_wapi.h>
++
++
++u32 wapi_debug_component =
++	/*				WAPI_INIT	|
++	 *				WAPI_API	|
++	 *				WAPI_TX	|
++	 *				WAPI_RX	| */
++	WAPI_ERR ; /* always open err flags on */
++
++void WapiFreeAllStaInfo(_adapter *padapter)
++{
++	PRT_WAPI_T				pWapiInfo;
++	PRT_WAPI_STA_INFO		pWapiStaInfo;
++	PRT_WAPI_BKID			pWapiBkid;
++
++	WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__);
++	pWapiInfo = &padapter->wapiInfo;
++
++	/* Pust to Idle List */
++	rtw_wapi_return_all_sta_info(padapter);
++
++	/* Sta Info List */
++	while (!list_empty(&(pWapiInfo->wapiSTAIdleList))) {
++		pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAIdleList.next, RT_WAPI_STA_INFO, list);
++		list_del_init(&pWapiStaInfo->list);
++	}
++
++	/* BKID List */
++	while (!list_empty(&(pWapiInfo->wapiBKIDIdleList))) {
++		pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDIdleList.next, RT_WAPI_BKID, list);
++		list_del_init(&pWapiBkid->list);
++	}
++	WAPI_TRACE(WAPI_INIT, "<=========== %s\n", __FUNCTION__);
++	return;
++}
++
++void WapiSetIE(_adapter *padapter)
++{
++	PRT_WAPI_T		pWapiInfo = &(padapter->wapiInfo);
++	/* PRT_WAPI_BKID	pWapiBkid; */
++	u16		protocolVer = 1;
++	u16		akmCnt = 1;
++	u16		suiteCnt = 1;
++	u16		capability = 0;
++	u8		OUI[3];
++
++	OUI[0] = 0x00;
++	OUI[1] = 0x14;
++	OUI[2] = 0x72;
++
++	pWapiInfo->wapiIELength = 0;
++	/* protocol version */
++	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &protocolVer, 2);
++	pWapiInfo->wapiIELength += 2;
++	/* akm */
++	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &akmCnt, 2);
++	pWapiInfo->wapiIELength += 2;
++
++	if (pWapiInfo->bWapiPSK) {
++		memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3);
++		pWapiInfo->wapiIELength += 3;
++		pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x2;
++		pWapiInfo->wapiIELength += 1;
++	} else {
++		memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3);
++		pWapiInfo->wapiIELength += 3;
++		pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1;
++		pWapiInfo->wapiIELength += 1;
++	}
++
++	/* usk */
++	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &suiteCnt, 2);
++	pWapiInfo->wapiIELength += 2;
++	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3);
++	pWapiInfo->wapiIELength += 3;
++	pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1;
++	pWapiInfo->wapiIELength += 1;
++
++	/* msk */
++	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3);
++	pWapiInfo->wapiIELength += 3;
++	pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1;
++	pWapiInfo->wapiIELength += 1;
++
++	/* Capbility */
++	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &capability, 2);
++	pWapiInfo->wapiIELength += 2;
++}
++
++
++/*  PN1 > PN2, return 1,
++ *  else return 0.
++ */
++u32 WapiComparePN(u8 *PN1, u8 *PN2)
++{
++	char i;
++
++	if ((NULL == PN1) || (NULL == PN2))
++		return 1;
++
++	/* overflow case */
++	if ((PN2[15] - PN1[15]) & 0x80)
++		return 1;
++
++	for (i = 16; i > 0; i--) {
++		if (PN1[i - 1] == PN2[i - 1])
++			continue;
++		else if (PN1[i - 1] > PN2[i - 1])
++			return 1;
++		else
++			return 0;
++	}
++
++	return 0;
++}
++
++u8
++WapiGetEntryForCamWrite(_adapter *padapter, u8 *pMacAddr, u8 KID, BOOLEAN IsMsk)
++{
++	PRT_WAPI_T		pWapiInfo = NULL;
++	/* PRT_WAPI_CAM_ENTRY	pEntry=NULL; */
++	u8 i = 0;
++	u8 ret = 0xff;
++
++	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
++
++	pWapiInfo =  &padapter->wapiInfo;
++
++	/* exist? */
++	for (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {
++		if (pWapiInfo->wapiCamEntry[i].IsUsed
++		    && (_rtw_memcmp(pMacAddr, pWapiInfo->wapiCamEntry[i].PeerMacAddr, ETH_ALEN) == _TRUE)
++		    && pWapiInfo->wapiCamEntry[i].keyidx == KID
++		    && pWapiInfo->wapiCamEntry[i].type == IsMsk) {
++			ret = pWapiInfo->wapiCamEntry[i].entry_idx; /* cover it */
++			break;
++		}
++	}
++
++	if (i == WAPI_CAM_ENTRY_NUM) { /* not found */
++		for (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {
++			if (pWapiInfo->wapiCamEntry[i].IsUsed == 0) {
++				pWapiInfo->wapiCamEntry[i].IsUsed = 1;
++				pWapiInfo->wapiCamEntry[i].type = IsMsk;
++				pWapiInfo->wapiCamEntry[i].keyidx = KID;
++				_rtw_memcpy(pWapiInfo->wapiCamEntry[i].PeerMacAddr, pMacAddr, ETH_ALEN);
++				ret = pWapiInfo->wapiCamEntry[i].entry_idx;
++				break;
++			}
++		}
++	}
++
++	WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
++	return ret;
++
++	/*
++		if(RTIsListEmpty(&pWapiInfo->wapiCamIdleList)) {
++			return 0;
++		}
++
++		pEntry = (PRT_WAPI_CAM_ENTRY)RTRemoveHeadList(&pWapiInfo->wapiCamIdleList);
++		RTInsertTailList(&pWapiInfo->wapiCamUsedList, &pEntry->list);
++
++
++		return pEntry->entry_idx;*/
++}
++
++u8 WapiGetEntryForCamClear(_adapter *padapter, u8 *pPeerMac, u8 keyid, u8 IsMsk)
++{
++	PRT_WAPI_T		pWapiInfo = NULL;
++	u8		i = 0;
++
++	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
++
++	pWapiInfo =  &padapter->wapiInfo;
++
++	for (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {
++		if (pWapiInfo->wapiCamEntry[i].IsUsed
++		    && (_rtw_memcmp(pPeerMac, pWapiInfo->wapiCamEntry[i].PeerMacAddr, ETH_ALEN) == _TRUE)
++		    && pWapiInfo->wapiCamEntry[i].keyidx == keyid
++		    && pWapiInfo->wapiCamEntry[i].type == IsMsk) {
++			pWapiInfo->wapiCamEntry[i].IsUsed = 0;
++			pWapiInfo->wapiCamEntry[i].keyidx = 2;
++			_rtw_memset(pWapiInfo->wapiCamEntry[i].PeerMacAddr, 0, ETH_ALEN);
++
++			WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
++			return pWapiInfo->wapiCamEntry[i].entry_idx;
++		}
++	}
++
++	WAPI_TRACE(WAPI_API, "<====WapiGetReturnCamEntry(), No this cam entry.\n");
++	return 0xff;
++	/*
++		if(RTIsListEmpty(&pWapiInfo->wapiCamUsedList)) {
++			return FALSE;
++		}
++
++		pList = &pWapiInfo->wapiCamUsedList;
++		while(pList->Flink != &pWapiInfo->wapiCamUsedList)
++		{
++			pEntry = (PRT_WAPI_CAM_ENTRY)pList->Flink;
++			if(PlatformCompareMemory(pPeerMac,pEntry->PeerMacAddr, ETHER_ADDRLEN)== 0
++				&& keyid == pEntry->keyidx)
++			{
++				RTRemoveEntryList(pList);
++				RTInsertHeadList(&pWapiInfo->wapiCamIdleList, pList);
++				return pEntry->entry_idx;
++			}
++			pList = pList->Flink;
++		}
++
++		return 0;
++	*/
++}
++
++void
++WapiResetAllCamEntry(_adapter *padapter)
++{
++	PRT_WAPI_T		pWapiInfo;
++	int				i;
++
++	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
++
++	pWapiInfo =  &padapter->wapiInfo;
++
++	for (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {
++		_rtw_memset(pWapiInfo->wapiCamEntry[i].PeerMacAddr, 0, ETH_ALEN);
++		pWapiInfo->wapiCamEntry[i].IsUsed = 0;
++		pWapiInfo->wapiCamEntry[i].keyidx = 2; /* invalid */
++		pWapiInfo->wapiCamEntry[i].entry_idx = 4 + i * 2;
++	}
++
++	WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
++
++	return;
++}
++
++u8 WapiWriteOneCamEntry(
++	_adapter	*padapter,
++	u8			*pMacAddr,
++	u8			KeyId,
++	u8			EntryId,
++	u8			EncAlg,
++	u8			bGroupKey,
++	u8			*pKey
++)
++{
++	u8 retVal = 0;
++	u16 usConfig = 0;
++
++	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
++
++	if (EntryId >= 32) {
++		WAPI_TRACE(WAPI_ERR, "<=== CamAddOneEntry(): ulKeyId exceed!\n");
++		return retVal;
++	}
++
++	usConfig = usConfig | (0x01 << 15) | ((u16)(EncAlg) << 2) | (KeyId);
++
++	if (EncAlg == _SMS4_) {
++		if (bGroupKey == 1)
++			usConfig |= (0x01 << 6);
++		if ((EntryId % 2) == 1) /* ==0 sec key; == 1mic key */
++			usConfig |= (0x01 << 5);
++	}
++
++	write_cam(padapter, EntryId, usConfig, pMacAddr, pKey);
++
++	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
++	return 1;
++}
++
++void rtw_wapi_init(_adapter *padapter)
++{
++	PRT_WAPI_T		pWapiInfo;
++	int				i;
++
++	WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__);
++	RT_ASSERT_RET(padapter);
++
++	if (!padapter->WapiSupport) {
++		WAPI_TRACE(WAPI_INIT, "<========== %s, WAPI not supported!\n", __FUNCTION__);
++		return;
++	}
++
++	pWapiInfo =  &padapter->wapiInfo;
++	pWapiInfo->bWapiEnable = false;
++
++	/* Init BKID List */
++	INIT_LIST_HEAD(&pWapiInfo->wapiBKIDIdleList);
++	INIT_LIST_HEAD(&pWapiInfo->wapiBKIDStoreList);
++	for (i = 0; i < WAPI_MAX_BKID_NUM; i++)
++		list_add_tail(&pWapiInfo->wapiBKID[i].list, &pWapiInfo->wapiBKIDIdleList);
++
++	/* Init STA List */
++	INIT_LIST_HEAD(&pWapiInfo->wapiSTAIdleList);
++	INIT_LIST_HEAD(&pWapiInfo->wapiSTAUsedList);
++	for (i = 0; i < WAPI_MAX_STAINFO_NUM; i++)
++		list_add_tail(&pWapiInfo->wapiSta[i].list, &pWapiInfo->wapiSTAIdleList);
++
++	for (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {
++		pWapiInfo->wapiCamEntry[i].IsUsed = 0;
++		pWapiInfo->wapiCamEntry[i].keyidx = 2; /* invalid */
++		pWapiInfo->wapiCamEntry[i].entry_idx = 4 + i * 2;
++	}
++
++	WAPI_TRACE(WAPI_INIT, "<========== %s\n", __FUNCTION__);
++}
++
++void rtw_wapi_free(_adapter *padapter)
++{
++	WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__);
++	RT_ASSERT_RET(padapter);
++
++	if (!padapter->WapiSupport) {
++		WAPI_TRACE(WAPI_INIT, "<========== %s, WAPI not supported!\n", __FUNCTION__);
++		return;
++	}
++
++	WapiFreeAllStaInfo(padapter);
++
++	WAPI_TRACE(WAPI_INIT, "<========== %s\n", __FUNCTION__);
++}
++
++void rtw_wapi_disable_tx(_adapter *padapter)
++{
++	WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__);
++	RT_ASSERT_RET(padapter);
++
++	if (!padapter->WapiSupport) {
++		WAPI_TRACE(WAPI_INIT, "<========== %s, WAPI not supported!\n", __FUNCTION__);
++		return;
++	}
++
++	padapter->wapiInfo.wapiTxMsk.bTxEnable = false;
++	padapter->wapiInfo.wapiTxMsk.bSet = false;
++
++	WAPI_TRACE(WAPI_INIT, "<========== %s\n", __FUNCTION__);
++}
++
++u8 rtw_wapi_is_wai_packet(_adapter *padapter, u8 *pkt_data)
++{
++	PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo);
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct security_priv   *psecuritypriv = &padapter->securitypriv;
++	PRT_WAPI_STA_INFO pWapiSta = NULL;
++	u8 WaiPkt = 0, *pTaddr, bFind = false;
++	u8 Offset_TypeWAI = 0 ;	/* (mac header len + llc length) */
++
++	WAPI_TRACE(WAPI_TX | WAPI_RX, "===========> %s\n", __FUNCTION__);
++
++	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
++		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
++		return 0;
++	}
++
++	Offset_TypeWAI = 24 + 6 ;
++
++	/* YJ,add,091103. Data frame may also have skb->data[30]=0x88 and skb->data[31]=0xb4. */
++	if ((pkt_data[1] & 0x40) != 0) {
++		/* RTW_INFO("data is privacy\n"); */
++		return 0;
++	}
++
++	pTaddr = get_addr2_ptr(pkt_data);
++	if (list_empty(&pWapiInfo->wapiSTAUsedList))
++		bFind = false;
++	else {
++		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
++			if (_rtw_memcmp(pTaddr, pWapiSta->PeerMacAddr, 6) == _TRUE) {
++				bFind = true;
++				break;
++			}
++		}
++	}
++
++	WAPI_TRACE(WAPI_TX | WAPI_RX, "%s: bFind=%d pTaddr="MAC_FMT"\n", __FUNCTION__, bFind, MAC_ARG(pTaddr));
++
++	if (pkt_data[0] == WIFI_QOS_DATA_TYPE)
++		Offset_TypeWAI += 2;
++
++	/* 88b4? */
++	if ((pkt_data[Offset_TypeWAI] == 0x88) && (pkt_data[Offset_TypeWAI + 1] == 0xb4)) {
++		WaiPkt = pkt_data[Offset_TypeWAI + 5];
++
++		psecuritypriv->hw_decrypted = _TRUE;
++	} else
++		WAPI_TRACE(WAPI_TX | WAPI_RX, "%s(): non wai packet\n", __FUNCTION__);
++
++	WAPI_TRACE(WAPI_TX | WAPI_RX, "%s(): Recvd WAI frame. IsWAIPkt(%d)\n", __FUNCTION__, WaiPkt);
++
++	return	WaiPkt;
++}
++
++
++void rtw_wapi_update_info(_adapter *padapter, union recv_frame *precv_frame)
++{
++	PRT_WAPI_T     pWapiInfo = &(padapter->wapiInfo);
++	struct recv_frame_hdr *precv_hdr;
++	u8	*ptr;
++	u8	*pTA;
++	u8	*pRecvPN;
++
++
++	WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__);
++
++	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
++		WAPI_TRACE(WAPI_RX, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
++		return;
++	}
++
++	precv_hdr = &precv_frame->u.hdr;
++	ptr = precv_hdr->rx_data;
++
++	if (precv_hdr->attrib.qos == 1)
++		precv_hdr->UserPriority = GetTid(ptr);
++	else
++		precv_hdr->UserPriority = 0;
++
++	pTA = get_addr2_ptr(ptr);
++	_rtw_memcpy((u8 *)precv_hdr->WapiSrcAddr, pTA, 6);
++	pRecvPN = ptr + precv_hdr->attrib.hdrlen + 2;
++	_rtw_memcpy((u8 *)precv_hdr->WapiTempPN, pRecvPN, 16);
++
++	WAPI_TRACE(WAPI_RX, "<========== %s\n", __FUNCTION__);
++}
++
++/****************************************************************************
++TRUE-----------------Drop
++FALSE---------------- handle
++add to support WAPI to N-mode
++*****************************************************************************/
++u8 rtw_wapi_check_for_drop(
++	_adapter *padapter,
++	union recv_frame *precv_frame,
++	u8 *ehdr_ops
++)
++{
++	PRT_WAPI_T     pWapiInfo = &(padapter->wapiInfo);
++	u8			*pLastRecvPN = NULL;
++	u8			bFind = false;
++	PRT_WAPI_STA_INFO	pWapiSta = NULL;
++	u8			bDrop = false;
++	struct recv_frame_hdr *precv_hdr = &precv_frame->u.hdr;
++	u8					WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
++	u8					WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
++	u8					*ptr = ehdr_ops;
++	int					i;
++
++	WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__);
++
++	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
++		WAPI_TRACE(WAPI_RX, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
++		return false;
++	}
++
++	if (precv_hdr->bIsWaiPacket != 0) {
++		if (precv_hdr->bIsWaiPacket == 0x8) {
++
++			RTW_INFO("rtw_wapi_check_for_drop: dump packet\n");
++			for (i = 0; i < 50; i++) {
++				RTW_INFO("%02X  ", ptr[i]);
++				if ((i + 1) % 8 == 0)
++					RTW_INFO("\n");
++			}
++			RTW_INFO("\n rtw_wapi_check_for_drop: dump packet\n");
++
++			for (i = 0; i < 16; i++) {
++				if (ptr[i + 27] != 0)
++					break;
++			}
++
++			if (i == 16) {
++				WAPI_TRACE(WAPI_RX, "rtw_wapi_check_for_drop: drop with zero BKID\n");
++				return true;
++			} else
++				return false;
++		} else
++			return false;
++	}
++
++	if (list_empty(&pWapiInfo->wapiSTAUsedList))
++		bFind = false;
++	else {
++		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
++			if (_rtw_memcmp(precv_hdr->WapiSrcAddr, pWapiSta->PeerMacAddr, ETH_ALEN) == _TRUE) {
++				bFind = true;
++				break;
++			}
++		}
++	}
++	WAPI_TRACE(WAPI_RX, "%s: bFind=%d prxb->WapiSrcAddr="MAC_FMT"\n", __FUNCTION__, bFind, MAC_ARG(precv_hdr->WapiSrcAddr));
++
++	if (bFind) {
++		if (IS_MCAST(precv_hdr->attrib.ra)) {
++			WAPI_TRACE(WAPI_RX, "rtw_wapi_check_for_drop: multicast case\n");
++			pLastRecvPN = pWapiSta->lastRxMulticastPN;
++		} else {
++			WAPI_TRACE(WAPI_RX, "rtw_wapi_check_for_drop: unicast case\n");
++			switch (precv_hdr->UserPriority) {
++			case 0:
++			case 3:
++				pLastRecvPN = pWapiSta->lastRxUnicastPNBEQueue;
++				break;
++			case 1:
++			case 2:
++				pLastRecvPN = pWapiSta->lastRxUnicastPNBKQueue;
++				break;
++			case 4:
++			case 5:
++				pLastRecvPN = pWapiSta->lastRxUnicastPNVIQueue;
++				break;
++			case 6:
++			case 7:
++				pLastRecvPN = pWapiSta->lastRxUnicastPNVOQueue;
++				break;
++			default:
++				WAPI_TRACE(WAPI_ERR, "%s: Unknown TID\n", __FUNCTION__);
++				break;
++			}
++		}
++
++		if (!WapiComparePN(precv_hdr->WapiTempPN, pLastRecvPN)) {
++			WAPI_TRACE(WAPI_RX, "%s: Equal PN!!\n", __FUNCTION__);
++			if (IS_MCAST(precv_hdr->attrib.ra))
++				_rtw_memcpy(pLastRecvPN, WapiAEMultiCastPNInitialValueSrc, 16);
++			else
++				_rtw_memcpy(pLastRecvPN, WapiAEPNInitialValueSrc, 16);
++			bDrop = true;
++		} else
++			_rtw_memcpy(pLastRecvPN, precv_hdr->WapiTempPN, 16);
++	}
++
++	WAPI_TRACE(WAPI_RX, "<========== %s\n", __FUNCTION__);
++	return bDrop;
++}
++
++void rtw_build_probe_resp_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib)
++{
++	PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo);
++	u8 WapiIELength = 0;
++
++	WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__);
++
++	if ((!padapter->WapiSupport)  || (!pWapiInfo->bWapiEnable)) {
++		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported!\n", __FUNCTION__);
++		return;
++	}
++
++	WapiSetIE(padapter);
++	WapiIELength = pWapiInfo->wapiIELength;
++	pframe[0] = _WAPI_IE_;
++	pframe[1] = WapiIELength;
++	_rtw_memcpy(pframe + 2, pWapiInfo->wapiIE, WapiIELength);
++	pframe += WapiIELength + 2;
++	pattrib->pktlen += WapiIELength + 2;
++
++	WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__);
++}
++
++void rtw_build_beacon_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib)
++{
++	PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo);
++	u8 WapiIELength = 0;
++	WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__);
++
++	if ((!padapter->WapiSupport)  || (!pWapiInfo->bWapiEnable)) {
++		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported!\n", __FUNCTION__);
++		return;
++	}
++
++	WapiSetIE(padapter);
++	WapiIELength = pWapiInfo->wapiIELength;
++	pframe[0] = _WAPI_IE_;
++	pframe[1] = WapiIELength;
++	_rtw_memcpy(pframe + 2, pWapiInfo->wapiIE, WapiIELength);
++	pframe += WapiIELength + 2;
++	pattrib->pktlen += WapiIELength + 2;
++
++	WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__);
++}
++
++void rtw_build_assoc_req_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib)
++{
++	PRT_WAPI_BKID		pWapiBKID;
++	u16					bkidNum;
++	PRT_WAPI_T			pWapiInfo = &(padapter->wapiInfo);
++	u8					WapiIELength = 0;
++
++	WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__);
++
++	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
++		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported!\n", __FUNCTION__);
++		return;
++	}
++
++	WapiSetIE(padapter);
++	WapiIELength = pWapiInfo->wapiIELength;
++	bkidNum = 0;
++	if (!list_empty(&(pWapiInfo->wapiBKIDStoreList))) {
++		list_for_each_entry(pWapiBKID, &pWapiInfo->wapiBKIDStoreList, list) {
++			bkidNum++;
++			_rtw_memcpy(pWapiInfo->wapiIE + WapiIELength + 2, pWapiBKID->bkid, 16);
++			WapiIELength += 16;
++		}
++	}
++	_rtw_memcpy(pWapiInfo->wapiIE + WapiIELength, &bkidNum, 2);
++	WapiIELength += 2;
++
++	pframe[0] = _WAPI_IE_;
++	pframe[1] = WapiIELength;
++	_rtw_memcpy(pframe + 2, pWapiInfo->wapiIE, WapiIELength);
++	pframe += WapiIELength + 2;
++	pattrib->pktlen += WapiIELength + 2;
++	WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__);
++}
++
++void rtw_wapi_on_assoc_ok(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++	PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo);
++	PRT_WAPI_STA_INFO pWapiSta;
++	u8 WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
++	/* u8 WapiASUEPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; */
++	u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
++
++	WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__);
++
++	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
++		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
++		return;
++	}
++
++	pWapiSta = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAIdleList.next, RT_WAPI_STA_INFO, list);
++	list_del_init(&pWapiSta->list);
++	list_add_tail(&pWapiSta->list, &pWapiInfo->wapiSTAUsedList);
++	_rtw_memcpy(pWapiSta->PeerMacAddr, padapter->mlmeextpriv.mlmext_info.network.MacAddress, 6);
++	_rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16);
++	_rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiAEPNInitialValueSrc, 16);
++
++	/* For chenk PN error with Qos Data after s3: add by ylb 20111114 */
++	_rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiAEPNInitialValueSrc, 16);
++	_rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiAEPNInitialValueSrc, 16);
++	_rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiAEPNInitialValueSrc, 16);
++	_rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiAEPNInitialValueSrc, 16);
++
++	WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__);
++}
++
++
++void rtw_wapi_return_one_sta_info(_adapter *padapter, u8 *MacAddr)
++{
++	PRT_WAPI_T				pWapiInfo;
++	PRT_WAPI_STA_INFO		pWapiStaInfo = NULL;
++	PRT_WAPI_BKID			pWapiBkid = NULL;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++
++	pWapiInfo = &padapter->wapiInfo;
++
++	WAPI_TRACE(WAPI_API, "==========> %s\n", __FUNCTION__);
++
++	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
++		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
++		return;
++	}
++
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
++		while (!list_empty(&(pWapiInfo->wapiBKIDStoreList))) {
++			pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDStoreList.next, RT_WAPI_BKID, list);
++			list_del_init(&pWapiBkid->list);
++			_rtw_memset(pWapiBkid->bkid, 0, 16);
++			list_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDIdleList);
++		}
++	}
++
++
++	WAPI_TRACE(WAPI_API, " %s: after clear bkid\n", __FUNCTION__);
++
++
++	/* Remove STA info */
++	if (list_empty(&(pWapiInfo->wapiSTAUsedList))) {
++		WAPI_TRACE(WAPI_API, " %s: wapiSTAUsedList is null\n", __FUNCTION__);
++		return;
++	} else {
++
++		WAPI_TRACE(WAPI_API, " %s: wapiSTAUsedList is not null\n", __FUNCTION__);
++#if 0
++		pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry((pWapiInfo->wapiSTAUsedList.next), RT_WAPI_STA_INFO, list);
++
++		list_for_each_entry(pWapiStaInfo, &(pWapiInfo->wapiSTAUsedList), list) {
++
++			RTW_INFO("MAC Addr %02x-%02x-%02x-%02x-%02x-%02x\n", MacAddr[0], MacAddr[1], MacAddr[2], MacAddr[3], MacAddr[4], MacAddr[5]);
++
++
++			RTW_INFO("peer Addr %02x-%02x-%02x-%02x-%02x-%02x\n", pWapiStaInfo->PeerMacAddr[0], pWapiStaInfo->PeerMacAddr[1], pWapiStaInfo->PeerMacAddr[2], pWapiStaInfo->PeerMacAddr[3],
++				pWapiStaInfo->PeerMacAddr[4], pWapiStaInfo->PeerMacAddr[5]);
++
++			if (pWapiStaInfo == NULL) {
++				WAPI_TRACE(WAPI_API, " %s: pWapiStaInfo == NULL Case\n", __FUNCTION__);
++				return;
++			}
++
++			if (pWapiStaInfo->PeerMacAddr == NULL) {
++				WAPI_TRACE(WAPI_API, " %s: pWapiStaInfo->PeerMacAddr == NULL Case\n", __FUNCTION__);
++				return;
++			}
++
++			if (MacAddr == NULL) {
++				WAPI_TRACE(WAPI_API, " %s: MacAddr == NULL Case\n", __FUNCTION__);
++				return;
++			}
++
++			if (_rtw_memcmp(pWapiStaInfo->PeerMacAddr, MacAddr, ETH_ALEN) == _TRUE) {
++				pWapiStaInfo->bAuthenticateInProgress = false;
++				pWapiStaInfo->bSetkeyOk = false;
++				_rtw_memset(pWapiStaInfo->PeerMacAddr, 0, ETH_ALEN);
++				list_del_init(&pWapiStaInfo->list);
++				list_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList);
++				break;
++			}
++
++		}
++#endif
++
++		while (!list_empty(&(pWapiInfo->wapiSTAUsedList))) {
++			pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAUsedList.next, RT_WAPI_STA_INFO, list);
++
++			RTW_INFO("peer Addr %02x-%02x-%02x-%02x-%02x-%02x\n", pWapiStaInfo->PeerMacAddr[0], pWapiStaInfo->PeerMacAddr[1], pWapiStaInfo->PeerMacAddr[2], pWapiStaInfo->PeerMacAddr[3],
++				pWapiStaInfo->PeerMacAddr[4], pWapiStaInfo->PeerMacAddr[5]);
++
++			list_del_init(&pWapiStaInfo->list);
++			memset(pWapiStaInfo->PeerMacAddr, 0, ETH_ALEN);
++			pWapiStaInfo->bSetkeyOk = 0;
++			list_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList);
++		}
++
++	}
++
++	WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
++	return;
++}
++
++void rtw_wapi_return_all_sta_info(_adapter *padapter)
++{
++	PRT_WAPI_T				pWapiInfo;
++	PRT_WAPI_STA_INFO		pWapiStaInfo;
++	PRT_WAPI_BKID			pWapiBkid;
++	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
++
++	pWapiInfo = &padapter->wapiInfo;
++
++	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
++		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
++		return;
++	}
++
++	/* Sta Info List */
++	while (!list_empty(&(pWapiInfo->wapiSTAUsedList))) {
++		pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAUsedList.next, RT_WAPI_STA_INFO, list);
++		list_del_init(&pWapiStaInfo->list);
++		memset(pWapiStaInfo->PeerMacAddr, 0, ETH_ALEN);
++		pWapiStaInfo->bSetkeyOk = 0;
++		list_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList);
++	}
++
++	/* BKID List */
++	while (!list_empty(&(pWapiInfo->wapiBKIDStoreList))) {
++		pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDStoreList.next, RT_WAPI_BKID, list);
++		list_del_init(&pWapiBkid->list);
++		memset(pWapiBkid->bkid, 0, 16);
++		list_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDIdleList);
++	}
++	WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
++}
++
++void CAM_empty_entry(
++	PADAPTER	Adapter,
++	u8			ucIndex
++)
++{
++	rtw_hal_set_hwreg(Adapter, HW_VAR_CAM_EMPTY_ENTRY, (u8 *)(&ucIndex));
++}
++
++void rtw_wapi_clear_cam_entry(_adapter *padapter, u8 *pMacAddr)
++{
++	u8 UcIndex = 0;
++
++	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
++
++	if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {
++		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
++		return;
++	}
++
++	UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 0, 0);
++	if (UcIndex != 0xff) {
++		/* CAM_mark_invalid(Adapter, UcIndex); */
++		CAM_empty_entry(padapter, UcIndex);
++	}
++
++	UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 1, 0);
++	if (UcIndex != 0xff) {
++		/* CAM_mark_invalid(Adapter, UcIndex); */
++		CAM_empty_entry(padapter, UcIndex);
++	}
++
++	UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 0, 1);
++	if (UcIndex != 0xff) {
++		/* CAM_mark_invalid(Adapter, UcIndex); */
++		CAM_empty_entry(padapter, UcIndex);
++	}
++
++	UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 1, 1);
++	if (UcIndex != 0xff) {
++		/* CAM_mark_invalid(padapter, UcIndex); */
++		CAM_empty_entry(padapter, UcIndex);
++	}
++
++	WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
++}
++
++void rtw_wapi_clear_all_cam_entry(_adapter *padapter)
++{
++	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
++
++	if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {
++		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
++		return;
++	}
++
++	invalidate_cam_all(padapter); /* is this ok? */
++	WapiResetAllCamEntry(padapter);
++
++	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
++}
++
++void rtw_wapi_set_key(_adapter *padapter, RT_WAPI_KEY *pWapiKey, RT_WAPI_STA_INFO *pWapiSta, u8 bGroupKey, u8 bUseDefaultKey)
++{
++	PRT_WAPI_T		pWapiInfo =  &padapter->wapiInfo;
++	u8				*pMacAddr = pWapiSta->PeerMacAddr;
++	u32 EntryId = 0;
++	BOOLEAN IsPairWise = false ;
++	u8 EncAlgo;
++
++	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
++
++	if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {
++		WAPI_TRACE(WAPI_API, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
++		return;
++	}
++
++	EncAlgo = _SMS4_;
++
++	/* For Tx bc/mc pkt,use defualt key entry */
++	if (bUseDefaultKey) {
++		/* when WAPI update key, keyid will be 0 or 1 by turns. */
++		if (pWapiKey->keyId == 0)
++			EntryId = 0;
++		else
++			EntryId = 2;
++	} else {
++		/* tx/rx unicast pkt, or rx broadcast, find the key entry by peer's MacAddr */
++		EntryId = WapiGetEntryForCamWrite(padapter, pMacAddr, pWapiKey->keyId, bGroupKey);
++	}
++
++	if (EntryId == 0xff) {
++		WAPI_TRACE(WAPI_API, "===>No entry for WAPI setkey! !!\n");
++		return;
++	}
++
++	/* EntryId is also used to diff Sec key and Mic key */
++	/* Sec Key */
++	WapiWriteOneCamEntry(padapter,
++			     pMacAddr,
++			     pWapiKey->keyId, /* keyid */
++			     EntryId,	/* entry */
++			     EncAlgo, /* type */
++			     bGroupKey, /* pairwise or group key */
++			     pWapiKey->dataKey);
++	/* MIC key */
++	WapiWriteOneCamEntry(padapter,
++			     pMacAddr,
++			     pWapiKey->keyId, /* keyid */
++			     EntryId + 1,	/* entry */
++			     EncAlgo, /* type */
++			     bGroupKey, /* pairwise or group key */
++			     pWapiKey->micKey);
++
++	WAPI_TRACE(WAPI_API, "Set Wapi Key :KeyId:%d,EntryId:%d,PairwiseKey:%d.\n", pWapiKey->keyId, EntryId, !bGroupKey);
++	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
++
++}
++
++#if 0
++/* YJ,test,091013 */
++void wapi_test_set_key(struct _adapter *padapter, u8 *buf)
++{
++	/*Data: keyType(1) + bTxEnable(1) + bAuthenticator(1) + bUpdate(1) + PeerAddr(6) + DataKey(16) + MicKey(16) + KeyId(1)*/
++	PRT_WAPI_T			pWapiInfo = &padapter->wapiInfo;
++	PRT_WAPI_BKID		pWapiBkid;
++	PRT_WAPI_STA_INFO	pWapiSta;
++	u8					data[43];
++	bool					bTxEnable;
++	bool					bUpdate;
++	bool					bAuthenticator;
++	u8					PeerAddr[6];
++	u8					WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
++	u8					WapiASUEPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
++	u8					WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
++
++	WAPI_TRACE(WAPI_INIT, "===========>%s\n", __FUNCTION__);
++
++	if (!padapter->WapiSupport)
++		return;
++
++	copy_from_user(data, buf, 43);
++	bTxEnable = data[1];
++	bAuthenticator = data[2];
++	bUpdate = data[3];
++	memcpy(PeerAddr, data + 4, 6);
++
++	if (data[0] == 0x3) {
++		if (!list_empty(&(pWapiInfo->wapiBKIDIdleList))) {
++			pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDIdleList.next, RT_WAPI_BKID, list);
++			list_del_init(&pWapiBkid->list);
++			memcpy(pWapiBkid->bkid, data + 10, 16);
++			WAPI_DATA(WAPI_INIT, "SetKey - BKID", pWapiBkid->bkid, 16);
++			list_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDStoreList);
++		}
++	} else {
++		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
++			if (!memcmp(pWapiSta->PeerMacAddr, PeerAddr, 6)) {
++				pWapiSta->bAuthenticatorInUpdata = false;
++				switch (data[0]) {
++				case 1:              /* usk */
++					if (bAuthenticator) {       /* authenticator */
++						memcpy(pWapiSta->lastTxUnicastPN, WapiAEPNInitialValueSrc, 16);
++						if (!bUpdate) {    /* first */
++							WAPI_TRACE(WAPI_INIT, "AE fisrt set usk\n");
++							pWapiSta->wapiUsk.bSet = true;
++							memcpy(pWapiSta->wapiUsk.dataKey, data + 10, 16);
++							memcpy(pWapiSta->wapiUsk.micKey, data + 26, 16);
++							pWapiSta->wapiUsk.keyId = *(data + 42);
++							pWapiSta->wapiUsk.bTxEnable = true;
++							WAPI_DATA(WAPI_INIT, "SetKey - AE USK Data Key", pWapiSta->wapiUsk.dataKey, 16);
++							WAPI_DATA(WAPI_INIT, "SetKey - AE USK Mic Key", pWapiSta->wapiUsk.micKey, 16);
++						} else {           /* update */
++							WAPI_TRACE(WAPI_INIT, "AE update usk\n");
++							pWapiSta->wapiUskUpdate.bSet = true;
++							pWapiSta->bAuthenticatorInUpdata = true;
++							memcpy(pWapiSta->wapiUskUpdate.dataKey, data + 10, 16);
++							memcpy(pWapiSta->wapiUskUpdate.micKey, data + 26, 16);
++							memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiASUEPNInitialValueSrc, 16);
++							memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiASUEPNInitialValueSrc, 16);
++							memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiASUEPNInitialValueSrc, 16);
++							memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiASUEPNInitialValueSrc, 16);
++							memcpy(pWapiSta->lastRxUnicastPN, WapiASUEPNInitialValueSrc, 16);
++							pWapiSta->wapiUskUpdate.keyId = *(data + 42);
++							pWapiSta->wapiUskUpdate.bTxEnable = true;
++						}
++					} else {
++						if (!bUpdate) {
++							WAPI_TRACE(WAPI_INIT, "ASUE fisrt set usk\n");
++							if (bTxEnable) {
++								pWapiSta->wapiUsk.bTxEnable = true;
++								memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16);
++							} else {
++								pWapiSta->wapiUsk.bSet = true;
++								memcpy(pWapiSta->wapiUsk.dataKey, data + 10, 16);
++								memcpy(pWapiSta->wapiUsk.micKey, data + 26, 16);
++								pWapiSta->wapiUsk.keyId = *(data + 42);
++								pWapiSta->wapiUsk.bTxEnable = false;
++							}
++						} else {
++							WAPI_TRACE(WAPI_INIT, "ASUE update usk\n");
++							if (bTxEnable) {
++								pWapiSta->wapiUskUpdate.bTxEnable = true;
++								if (pWapiSta->wapiUskUpdate.bSet) {
++									memcpy(pWapiSta->wapiUsk.dataKey, pWapiSta->wapiUskUpdate.dataKey, 16);
++									memcpy(pWapiSta->wapiUsk.micKey, pWapiSta->wapiUskUpdate.micKey, 16);
++									pWapiSta->wapiUsk.keyId = pWapiSta->wapiUskUpdate.keyId;
++									memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiASUEPNInitialValueSrc, 16);
++									memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiASUEPNInitialValueSrc, 16);
++									memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiASUEPNInitialValueSrc, 16);
++									memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiASUEPNInitialValueSrc, 16);
++									memcpy(pWapiSta->lastRxUnicastPN, WapiASUEPNInitialValueSrc, 16);
++									pWapiSta->wapiUskUpdate.bTxEnable = false;
++									pWapiSta->wapiUskUpdate.bSet = false;
++								}
++								memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16);
++							} else {
++								pWapiSta->wapiUskUpdate.bSet = true;
++								memcpy(pWapiSta->wapiUskUpdate.dataKey, data + 10, 16);
++								memcpy(pWapiSta->wapiUskUpdate.micKey, data + 26, 16);
++								pWapiSta->wapiUskUpdate.keyId = *(data + 42);
++								pWapiSta->wapiUskUpdate.bTxEnable = false;
++							}
++						}
++					}
++					break;
++				case 2:		/* msk */
++					if (bAuthenticator) {        /* authenticator */
++						pWapiInfo->wapiTxMsk.bSet = true;
++						memcpy(pWapiInfo->wapiTxMsk.dataKey, data + 10, 16);
++						memcpy(pWapiInfo->wapiTxMsk.micKey, data + 26, 16);
++						pWapiInfo->wapiTxMsk.keyId = *(data + 42);
++						pWapiInfo->wapiTxMsk.bTxEnable = true;
++						memcpy(pWapiInfo->lastTxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16);
++
++						if (!bUpdate) {    /* first */
++							WAPI_TRACE(WAPI_INIT, "AE fisrt set msk\n");
++							if (!pWapiSta->bSetkeyOk)
++								pWapiSta->bSetkeyOk = true;
++							pWapiInfo->bFirstAuthentiateInProgress = false;
++						} else                /* update */
++							WAPI_TRACE(WAPI_INIT, "AE update msk\n");
++
++						WAPI_DATA(WAPI_INIT, "SetKey - AE MSK Data Key", pWapiInfo->wapiTxMsk.dataKey, 16);
++						WAPI_DATA(WAPI_INIT, "SetKey - AE MSK Mic Key", pWapiInfo->wapiTxMsk.micKey, 16);
++					} else {
++						if (!bUpdate) {
++							WAPI_TRACE(WAPI_INIT, "ASUE fisrt set msk\n");
++							pWapiSta->wapiMsk.bSet = true;
++							memcpy(pWapiSta->wapiMsk.dataKey, data + 10, 16);
++							memcpy(pWapiSta->wapiMsk.micKey, data + 26, 16);
++							pWapiSta->wapiMsk.keyId = *(data + 42);
++							pWapiSta->wapiMsk.bTxEnable = false;
++							if (!pWapiSta->bSetkeyOk)
++								pWapiSta->bSetkeyOk = true;
++							pWapiInfo->bFirstAuthentiateInProgress = false;
++							WAPI_DATA(WAPI_INIT, "SetKey - ASUE MSK Data Key", pWapiSta->wapiMsk.dataKey, 16);
++							WAPI_DATA(WAPI_INIT, "SetKey - ASUE MSK Mic Key", pWapiSta->wapiMsk.micKey, 16);
++						} else {
++							WAPI_TRACE(WAPI_INIT, "ASUE update msk\n");
++							pWapiSta->wapiMskUpdate.bSet = true;
++							memcpy(pWapiSta->wapiMskUpdate.dataKey, data + 10, 16);
++							memcpy(pWapiSta->wapiMskUpdate.micKey, data + 26, 16);
++							pWapiSta->wapiMskUpdate.keyId = *(data + 42);
++							pWapiSta->wapiMskUpdate.bTxEnable = false;
++						}
++					}
++					break;
++				default:
++					WAPI_TRACE(WAPI_ERR, "Unknown Flag\n");
++					break;
++				}
++			}
++		}
++	}
++	WAPI_TRACE(WAPI_INIT, "<===========%s\n", __FUNCTION__);
++}
++
++
++void wapi_test_init(struct _adapter *padapter)
++{
++	u8 keybuf[100];
++	u8 mac_addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x72, 0x04, 0x70};
++	u8 UskDataKey[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f};
++	u8 UskMicKey[16] = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f};
++	u8 UskId = 0;
++	u8 MskDataKey[16] = {0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f};
++	u8 MskMicKey[16] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f};
++	u8 MskId = 0;
++
++	WAPI_TRACE(WAPI_INIT, "===========>%s\n", __FUNCTION__);
++
++	/* Enable Wapi */
++	WAPI_TRACE(WAPI_INIT, "%s: Enable wapi!!!!\n", __FUNCTION__);
++	padapter->wapiInfo.bWapiEnable = true;
++	padapter->pairwise_key_type = KEY_TYPE_SMS4;
++	ieee->group_key_type = KEY_TYPE_SMS4;
++	padapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN;
++	padapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN;
++
++	/* set usk */
++	WAPI_TRACE(WAPI_INIT, "%s: Set USK!!!!\n", __FUNCTION__);
++	memset(keybuf, 0, 100);
++	keybuf[0] = 1;                           /* set usk */
++	keybuf[1] = 1; 				/* enable tx */
++	keybuf[2] = 1; 				/* AE */
++	keybuf[3] = 0; 				/* not update */
++
++	memcpy(keybuf + 4, mac_addr, ETH_ALEN);
++	memcpy(keybuf + 10, UskDataKey, 16);
++	memcpy(keybuf + 26, UskMicKey, 16);
++	keybuf[42] = UskId;
++	wapi_test_set_key(padapter, keybuf);
++
++	memset(keybuf, 0, 100);
++	keybuf[0] = 1;                           /* set usk */
++	keybuf[1] = 1; 				/* enable tx */
++	keybuf[2] = 0; 				/* AE */
++	keybuf[3] = 0; 				/* not update */
++
++	memcpy(keybuf + 4, mac_addr, ETH_ALEN);
++	memcpy(keybuf + 10, UskDataKey, 16);
++	memcpy(keybuf + 26, UskMicKey, 16);
++	keybuf[42] = UskId;
++	wapi_test_set_key(padapter, keybuf);
++
++	/* set msk */
++	WAPI_TRACE(WAPI_INIT, "%s: Set MSK!!!!\n", __FUNCTION__);
++	memset(keybuf, 0, 100);
++	keybuf[0] = 2;                                /* set msk */
++	keybuf[1] = 1;                               /* Enable TX */
++	keybuf[2] = 1; 				/* AE */
++	keybuf[3] = 0;                              /* not update */
++	memcpy(keybuf + 4, mac_addr, ETH_ALEN);
++	memcpy(keybuf + 10, MskDataKey, 16);
++	memcpy(keybuf + 26, MskMicKey, 16);
++	keybuf[42] = MskId;
++	wapi_test_set_key(padapter, keybuf);
++
++	memset(keybuf, 0, 100);
++	keybuf[0] = 2;                                /* set msk */
++	keybuf[1] = 1;                               /* Enable TX */
++	keybuf[2] = 0; 				/* AE */
++	keybuf[3] = 0;                              /* not update */
++	memcpy(keybuf + 4, mac_addr, ETH_ALEN);
++	memcpy(keybuf + 10, MskDataKey, 16);
++	memcpy(keybuf + 26, MskMicKey, 16);
++	keybuf[42] = MskId;
++	wapi_test_set_key(padapter, keybuf);
++	WAPI_TRACE(WAPI_INIT, "<===========%s\n", __FUNCTION__);
++}
++#endif
++
++void rtw_wapi_get_iv(_adapter *padapter, u8 *pRA, u8 *IV)
++{
++	PWLAN_HEADER_WAPI_EXTENSION pWapiExt = NULL;
++	PRT_WAPI_T         pWapiInfo = &padapter->wapiInfo;
++	bool	bPNOverflow = false;
++	bool	bFindMatchPeer = false;
++	PRT_WAPI_STA_INFO  pWapiSta = NULL;
++
++	pWapiExt = (PWLAN_HEADER_WAPI_EXTENSION)IV;
++
++	WAPI_DATA(WAPI_RX, "wapi_get_iv: pra", pRA, 6);
++
++	if (IS_MCAST(pRA)) {
++		if (!pWapiInfo->wapiTxMsk.bTxEnable) {
++			WAPI_TRACE(WAPI_ERR, "%s: bTxEnable = 0!!\n", __FUNCTION__);
++			return;
++		}
++
++		if (pWapiInfo->wapiTxMsk.keyId <= 1) {
++			pWapiExt->KeyIdx = pWapiInfo->wapiTxMsk.keyId;
++			pWapiExt->Reserved = 0;
++			bPNOverflow = WapiIncreasePN(pWapiInfo->lastTxMulticastPN, 1);
++			memcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16);
++		}
++	} else {
++		if (list_empty(&pWapiInfo->wapiSTAUsedList)) {
++			WAPI_TRACE(WAPI_RX, "rtw_wapi_get_iv: list is empty\n");
++			_rtw_memset(IV, 10, 18);
++			return;
++		} else {
++			list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
++				WAPI_DATA(WAPI_RX, "rtw_wapi_get_iv: peermacaddr ", pWapiSta->PeerMacAddr, 6);
++				if (_rtw_memcmp((u8 *)pWapiSta->PeerMacAddr, pRA, 6) == _TRUE) {
++					bFindMatchPeer = true;
++					break;
++				}
++			}
++
++			WAPI_TRACE(WAPI_RX, "bFindMatchPeer: %d\n", bFindMatchPeer);
++			WAPI_DATA(WAPI_RX, "Addr", pRA, 6);
++
++			if (bFindMatchPeer) {
++				if ((!pWapiSta->wapiUskUpdate.bTxEnable) && (!pWapiSta->wapiUsk.bTxEnable))
++					return;
++
++				if (pWapiSta->wapiUsk.keyId <= 1) {
++					if (pWapiSta->wapiUskUpdate.bTxEnable)
++						pWapiExt->KeyIdx = pWapiSta->wapiUskUpdate.keyId;
++					else
++						pWapiExt->KeyIdx = pWapiSta->wapiUsk.keyId;
++
++					pWapiExt->Reserved = 0;
++					bPNOverflow = WapiIncreasePN(pWapiSta->lastTxUnicastPN, 2);
++					_rtw_memcpy(pWapiExt->PN, pWapiSta->lastTxUnicastPN, 16);
++
++				}
++			}
++		}
++
++	}
++
++}
++
++bool rtw_wapi_drop_for_key_absent(_adapter *padapter, u8 *pRA)
++{
++	PRT_WAPI_T         pWapiInfo = &padapter->wapiInfo;
++	bool				bFindMatchPeer = false;
++	bool				bDrop = false;
++	PRT_WAPI_STA_INFO  pWapiSta = NULL;
++	struct security_priv		*psecuritypriv = &padapter->securitypriv;
++
++	WAPI_DATA(WAPI_RX, "rtw_wapi_drop_for_key_absent: ra ", pRA, 6);
++
++	if (psecuritypriv->dot11PrivacyAlgrthm == _SMS4_) {
++		if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable))
++			return true;
++
++		if (IS_MCAST(pRA)) {
++			if (!pWapiInfo->wapiTxMsk.bTxEnable) {
++				bDrop = true;
++				WAPI_TRACE(WAPI_RX, "rtw_wapi_drop_for_key_absent: multicast key is absent\n");
++				return bDrop;
++			}
++		} else {
++			if (!list_empty(&pWapiInfo->wapiSTAUsedList)) {
++				list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
++					WAPI_DATA(WAPI_RX, "rtw_wapi_drop_for_key_absent: pWapiSta->PeerMacAddr ", pWapiSta->PeerMacAddr, 6);
++					if (_rtw_memcmp(pRA, pWapiSta->PeerMacAddr, 6) == _TRUE) {
++						bFindMatchPeer = true;
++						break;
++					}
++				}
++				if (bFindMatchPeer)	{
++					if (!pWapiSta->wapiUsk.bTxEnable) {
++						bDrop = true;
++						WAPI_TRACE(WAPI_RX, "rtw_wapi_drop_for_key_absent: unicast key is absent\n");
++						return bDrop;
++					}
++				} else {
++					bDrop = true;
++					WAPI_TRACE(WAPI_RX, "rtw_wapi_drop_for_key_absent: no peer find\n");
++					return bDrop;
++				}
++
++			} else {
++				bDrop = true;
++				WAPI_TRACE(WAPI_RX, "rtw_wapi_drop_for_key_absent: no sta  exist\n");
++				return bDrop;
++			}
++		}
++	} else
++		return bDrop;
++
++	return bDrop;
++}
++
++void rtw_wapi_set_set_encryption(_adapter *padapter, struct ieee_param *param)
++{
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	PRT_WAPI_T			pWapiInfo = &padapter->wapiInfo;
++	PRT_WAPI_STA_INFO	pWapiSta;
++	u8					WapiASUEPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
++	u8					WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
++	u8					WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
++
++	if (param->u.crypt.set_tx == 1) {
++		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
++			if (_rtw_memcmp(pWapiSta->PeerMacAddr, param->sta_addr, 6)) {
++				_rtw_memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16);
++
++				pWapiSta->wapiUsk.bSet = true;
++				_rtw_memcpy(pWapiSta->wapiUsk.dataKey, param->u.crypt.key, 16);
++				_rtw_memcpy(pWapiSta->wapiUsk.micKey, param->u.crypt.key + 16, 16);
++				pWapiSta->wapiUsk.keyId = param->u.crypt.idx ;
++				pWapiSta->wapiUsk.bTxEnable = true;
++
++				_rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiAEPNInitialValueSrc, 16);
++				_rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiAEPNInitialValueSrc, 16);
++				_rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiAEPNInitialValueSrc, 16);
++				_rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiAEPNInitialValueSrc, 16);
++				_rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiAEPNInitialValueSrc, 16);
++				pWapiSta->wapiUskUpdate.bTxEnable = false;
++				pWapiSta->wapiUskUpdate.bSet = false;
++
++				if (psecuritypriv->sw_encrypt == false || psecuritypriv->sw_decrypt == false) {
++					/* set unicast key for ASUE */
++					rtw_wapi_set_key(padapter, &pWapiSta->wapiUsk, pWapiSta, false, false);
++				}
++			}
++		}
++	} else {
++		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
++			if (_rtw_memcmp(pWapiSta->PeerMacAddr, get_bssid(pmlmepriv), 6)) {
++				pWapiSta->wapiMsk.bSet = true;
++				_rtw_memcpy(pWapiSta->wapiMsk.dataKey, param->u.crypt.key, 16);
++				_rtw_memcpy(pWapiSta->wapiMsk.micKey, param->u.crypt.key + 16, 16);
++				pWapiSta->wapiMsk.keyId = param->u.crypt.idx ;
++				pWapiSta->wapiMsk.bTxEnable = false;
++				if (!pWapiSta->bSetkeyOk)
++					pWapiSta->bSetkeyOk = true;
++				pWapiSta->bAuthenticateInProgress = false;
++
++				_rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16);
++
++				if (psecuritypriv->sw_decrypt == false) {
++					/* set rx broadcast key for ASUE */
++					rtw_wapi_set_key(padapter, &pWapiSta->wapiMsk, pWapiSta, true, false);
++				}
++			}
++		}
++	}
++}
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_wapi_sms4.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_wapi_sms4.c
+new file mode 100644
+index 000000000..4b7cf957c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_wapi_sms4.c
+@@ -0,0 +1,922 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifdef CONFIG_WAPI_SUPPORT
++
++#include <linux/unistd.h>
++#include <linux/etherdevice.h>
++#include <drv_types.h>
++#include <rtw_wapi.h>
++
++
++#ifdef CONFIG_WAPI_SW_SMS4
++
++#define WAPI_LITTLE_ENDIAN
++/* #define BIG_ENDIAN */
++#define ENCRYPT  0
++#define DECRYPT  1
++
++
++/**********************************************************
++ **********************************************************/
++const u8 Sbox[256] = {
++	0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7, 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
++	0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3, 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
++	0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a, 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
++	0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95, 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
++	0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba, 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
++	0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b, 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
++	0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2, 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
++	0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52, 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
++	0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5, 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
++	0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55, 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
++	0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60, 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
++	0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f, 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
++	0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f, 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
++	0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd, 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
++	0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e, 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
++	0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20, 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48
++};
++
++const u32 CK[32] = {
++	0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269,
++	0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9,
++	0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249,
++	0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9,
++	0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229,
++	0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299,
++	0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209,
++	0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279
++};
++
++#define Rotl(_x, _y) (((_x) << (_y)) | ((_x) >> (32 - (_y))))
++
++#define ByteSub(_A) (Sbox[(_A) >> 24 & 0xFF] << 24 | \
++		     Sbox[(_A) >> 16 & 0xFF] << 16 | \
++		     Sbox[(_A) >>  8 & 0xFF] <<  8 | \
++		     Sbox[(_A) & 0xFF])
++
++#define L1(_B) ((_B) ^ Rotl(_B, 2) ^ Rotl(_B, 10) ^ Rotl(_B, 18) ^ Rotl(_B, 24))
++#define L2(_B) ((_B) ^ Rotl(_B, 13) ^ Rotl(_B, 23))
++
++static void
++xor_block(void *dst, void *src1, void *src2)
++/* 128-bit xor: *dst = *src1 xor *src2. Pointers must be 32-bit aligned */
++{
++	((u32 *)dst)[0] = ((u32 *)src1)[0] ^ ((u32 *)src2)[0];
++	((u32 *)dst)[1] = ((u32 *)src1)[1] ^ ((u32 *)src2)[1];
++	((u32 *)dst)[2] = ((u32 *)src1)[2] ^ ((u32 *)src2)[2];
++	((u32 *)dst)[3] = ((u32 *)src1)[3] ^ ((u32 *)src2)[3];
++}
++
++
++void SMS4Crypt(u8 *Input, u8 *Output, u32 *rk)
++{
++	u32 r, mid, x0, x1, x2, x3, *p;
++	p = (u32 *)Input;
++	x0 = p[0];
++	x1 = p[1];
++	x2 = p[2];
++	x3 = p[3];
++#ifdef WAPI_LITTLE_ENDIAN
++	x0 = Rotl(x0, 16);
++	x0 = ((x0 & 0x00FF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);
++	x1 = Rotl(x1, 16);
++	x1 = ((x1 & 0x00FF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);
++	x2 = Rotl(x2, 16);
++	x2 = ((x2 & 0x00FF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);
++	x3 = Rotl(x3, 16);
++	x3 = ((x3 & 0x00FF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);
++#endif
++	for (r = 0; r < 32; r += 4) {
++		mid = x1 ^ x2 ^ x3 ^ rk[r + 0];
++		mid = ByteSub(mid);
++		x0 ^= L1(mid);
++		mid = x2 ^ x3 ^ x0 ^ rk[r + 1];
++		mid = ByteSub(mid);
++		x1 ^= L1(mid);
++		mid = x3 ^ x0 ^ x1 ^ rk[r + 2];
++		mid = ByteSub(mid);
++		x2 ^= L1(mid);
++		mid = x0 ^ x1 ^ x2 ^ rk[r + 3];
++		mid = ByteSub(mid);
++		x3 ^= L1(mid);
++	}
++#ifdef WAPI_LITTLE_ENDIAN
++	x0 = Rotl(x0, 16);
++	x0 = ((x0 & 0x00FF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);
++	x1 = Rotl(x1, 16);
++	x1 = ((x1 & 0x00FF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);
++	x2 = Rotl(x2, 16);
++	x2 = ((x2 & 0x00FF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);
++	x3 = Rotl(x3, 16);
++	x3 = ((x3 & 0x00FF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);
++#endif
++	p = (u32 *)Output;
++	p[0] = x3;
++	p[1] = x2;
++	p[2] = x1;
++	p[3] = x0;
++}
++
++
++
++void SMS4KeyExt(u8 *Key, u32 *rk, u32 CryptFlag)
++{
++	u32 r, mid, x0, x1, x2, x3, *p;
++
++	p = (u32 *)Key;
++	x0 = p[0];
++	x1 = p[1];
++	x2 = p[2];
++	x3 = p[3];
++#ifdef WAPI_LITTLE_ENDIAN
++	x0 = Rotl(x0, 16);
++	x0 = ((x0 & 0xFF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);
++	x1 = Rotl(x1, 16);
++	x1 = ((x1 & 0xFF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);
++	x2 = Rotl(x2, 16);
++	x2 = ((x2 & 0xFF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);
++	x3 = Rotl(x3, 16);
++	x3 = ((x3 & 0xFF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);
++#endif
++
++	x0 ^= 0xa3b1bac6;
++	x1 ^= 0x56aa3350;
++	x2 ^= 0x677d9197;
++	x3 ^= 0xb27022dc;
++	for (r = 0; r < 32; r += 4) {
++		mid = x1 ^ x2 ^ x3 ^ CK[r + 0];
++		mid = ByteSub(mid);
++		rk[r + 0] = x0 ^= L2(mid);
++		mid = x2 ^ x3 ^ x0 ^ CK[r + 1];
++		mid = ByteSub(mid);
++		rk[r + 1] = x1 ^= L2(mid);
++		mid = x3 ^ x0 ^ x1 ^ CK[r + 2];
++		mid = ByteSub(mid);
++		rk[r + 2] = x2 ^= L2(mid);
++		mid = x0 ^ x1 ^ x2 ^ CK[r + 3];
++		mid = ByteSub(mid);
++		rk[r + 3] = x3 ^= L2(mid);
++	}
++	if (CryptFlag == DECRYPT) {
++		for (r = 0; r < 16; r++)
++			mid = rk[r], rk[r] = rk[31 - r], rk[31 - r] = mid;
++	}
++}
++
++
++void WapiSMS4Cryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,
++		      u8 *Output, u16 *OutputLength, u32 CryptFlag)
++{
++	u32 blockNum, i, j, rk[32];
++	u16 remainder;
++	u8 blockIn[16], blockOut[16], tempIV[16], k;
++
++	*OutputLength = 0;
++	remainder = InputLength & 0x0F;
++	blockNum = InputLength >> 4;
++	if (remainder != 0)
++		blockNum++;
++	else
++		remainder = 16;
++
++	for (k = 0; k < 16; k++)
++		tempIV[k] = IV[15 - k];
++
++	memcpy(blockIn, tempIV, 16);
++
++	SMS4KeyExt((u8 *)Key, rk, CryptFlag);
++
++	for (i = 0; i < blockNum - 1; i++) {
++		SMS4Crypt((u8 *)blockIn, blockOut, rk);
++		xor_block(&Output[i * 16], &Input[i * 16], blockOut);
++		memcpy(blockIn, blockOut, 16);
++	}
++
++	*OutputLength = i * 16;
++
++	SMS4Crypt((u8 *)blockIn, blockOut, rk);
++
++	for (j = 0; j < remainder; j++)
++		Output[i * 16 + j] = Input[i * 16 + j] ^ blockOut[j];
++	*OutputLength += remainder;
++
++}
++
++void WapiSMS4Encryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,
++			u8 *Output, u16 *OutputLength)
++{
++
++	WapiSMS4Cryption(Key, IV, Input, InputLength, Output, OutputLength, ENCRYPT);
++}
++
++void WapiSMS4Decryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,
++			u8 *Output, u16 *OutputLength)
++{
++	/* OFB mode: is also ENCRYPT flag */
++	WapiSMS4Cryption(Key, IV, Input, InputLength, Output, OutputLength, ENCRYPT);
++}
++
++void WapiSMS4CalculateMic(u8 *Key, u8 *IV, u8 *Input1, u8 Input1Length,
++		  u8 *Input2, u16 Input2Length, u8 *Output, u8 *OutputLength)
++{
++	u32 blockNum, i, remainder, rk[32];
++	u8 BlockIn[16], BlockOut[16], TempBlock[16], tempIV[16], k;
++
++	*OutputLength = 0;
++	remainder = Input1Length & 0x0F;
++	blockNum = Input1Length >> 4;
++
++	for (k = 0; k < 16; k++)
++		tempIV[k] = IV[15 - k];
++
++	memcpy(BlockIn, tempIV, 16);
++
++	SMS4KeyExt((u8 *)Key, rk, ENCRYPT);
++
++	SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
++
++	for (i = 0; i < blockNum; i++) {
++		xor_block(BlockIn, (Input1 + i * 16), BlockOut);
++		SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
++	}
++
++	if (remainder != 0) {
++		memset(TempBlock, 0, 16);
++		memcpy(TempBlock, (Input1 + blockNum * 16), remainder);
++
++		xor_block(BlockIn, TempBlock, BlockOut);
++		SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
++	}
++
++	remainder = Input2Length & 0x0F;
++	blockNum = Input2Length >> 4;
++
++	for (i = 0; i < blockNum; i++) {
++		xor_block(BlockIn, (Input2 + i * 16), BlockOut);
++		SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
++	}
++
++	if (remainder != 0) {
++		memset(TempBlock, 0, 16);
++		memcpy(TempBlock, (Input2 + blockNum * 16), remainder);
++
++		xor_block(BlockIn, TempBlock, BlockOut);
++		SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
++	}
++
++	memcpy(Output, BlockOut, 16);
++	*OutputLength = 16;
++}
++
++void SecCalculateMicSMS4(
++	u8		KeyIdx,
++	u8        *MicKey,
++	u8        *pHeader,
++	u8        *pData,
++	u16       DataLen,
++	u8        *MicBuffer
++)
++{
++#if 0
++	struct ieee80211_hdr_3addr_qos *header;
++	u8 TempBuf[34], TempLen = 32, MicLen, QosOffset, *IV;
++	u16 *pTemp, fc;
++
++	WAPI_TRACE(WAPI_TX | WAPI_RX, "=========>%s\n", __FUNCTION__);
++
++	header = (struct ieee80211_hdr_3addr_qos *)pHeader;
++	memset(TempBuf, 0, 34);
++	memcpy(TempBuf, pHeader, 2); /* FrameCtrl */
++	pTemp = (u16 *)TempBuf;
++	*pTemp &= 0xc78f;       /* bit4,5,6,11,12,13 */
++
++	memcpy((TempBuf + 2), (pHeader + 4), 12); /* Addr1, Addr2 */
++	memcpy((TempBuf + 14), (pHeader + 22), 2); /* SeqCtrl */
++	pTemp = (u16 *)(TempBuf + 14);
++	*pTemp &= 0x000f;
++
++	memcpy((TempBuf + 16), (pHeader + 16), 6); /* Addr3 */
++
++	fc = le16_to_cpu(header->frame_ctl);
++
++
++
++	if (GetFrDs((u16 *)&fc) && GetToDs((u16 *)&fc)) {
++		memcpy((TempBuf + 22), (pHeader + 24), 6);
++		QosOffset = 30;
++	} else {
++		memset((TempBuf + 22), 0, 6);
++		QosOffset = 24;
++	}
++
++	if ((fc & 0x0088) == 0x0088) {
++		memcpy((TempBuf + 28), (pHeader + QosOffset), 2);
++		TempLen += 2;
++		/* IV = pHeader + QosOffset + 2 + SNAP_SIZE + sizeof(u16) + 2; */
++		IV = pHeader + QosOffset + 2 + 2;
++	} else {
++		IV = pHeader + QosOffset + 2;
++		/* IV = pHeader + QosOffset + SNAP_SIZE + sizeof(u16) + 2; */
++	}
++
++	TempBuf[TempLen - 1] = (u8)(DataLen & 0xff);
++	TempBuf[TempLen - 2] = (u8)((DataLen & 0xff00) >> 8);
++	TempBuf[TempLen - 4] = KeyIdx;
++
++	WAPI_DATA(WAPI_TX, "CalculateMic - KEY", MicKey, 16);
++	WAPI_DATA(WAPI_TX, "CalculateMic - IV", IV, 16);
++	WAPI_DATA(WAPI_TX, "CalculateMic - TempBuf", TempBuf, TempLen);
++	WAPI_DATA(WAPI_TX, "CalculateMic - pData", pData, DataLen);
++
++	WapiSMS4CalculateMic(MicKey, IV, TempBuf, TempLen,
++			     pData, DataLen, MicBuffer, &MicLen);
++
++	if (MicLen != 16)
++		WAPI_TRACE(WAPI_ERR, "%s: MIC Length Error!!\n", __FUNCTION__);
++
++	WAPI_TRACE(WAPI_TX | WAPI_RX, "<=========%s\n", __FUNCTION__);
++#endif
++}
++
++/* AddCount: 1 or 2.
++ *  If overflow, return 1,
++ *  else return 0.
++ */
++u8 WapiIncreasePN(u8 *PN, u8 AddCount)
++{
++	u8  i;
++
++	if (NULL == PN)
++		return 1;
++	/* YJ,test,091102 */
++	/*
++	if(AddCount == 2){
++		RTW_INFO("############################%s(): PN[0]=0x%x\n", __FUNCTION__, PN[0]);
++		if(PN[0] == 0x48){
++			PN[0] += AddCount;
++			return 1;
++		}else{
++			PN[0] += AddCount;
++			return 0;
++		}
++	}
++	*/
++	/* YJ,test,091102,end */
++
++	for (i = 0; i < 16; i++) {
++		if (PN[i] + AddCount <= 0xff) {
++			PN[i] += AddCount;
++			return 0;
++		} else {
++			PN[i] += AddCount;
++			AddCount = 1;
++		}
++	}
++	return 1;
++}
++
++
++void WapiGetLastRxUnicastPNForQoSData(
++	u8			UserPriority,
++	PRT_WAPI_STA_INFO    pWapiStaInfo,
++	u8 *PNOut
++)
++{
++	WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__);
++	switch (UserPriority) {
++	case 0:
++	case 3:
++		memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNBEQueue, 16);
++		break;
++	case 1:
++	case 2:
++		memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNBKQueue, 16);
++		break;
++	case 4:
++	case 5:
++		memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNVIQueue, 16);
++		break;
++	case 6:
++	case 7:
++		memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNVOQueue, 16);
++		break;
++	default:
++		WAPI_TRACE(WAPI_ERR, "%s: Unknown TID\n", __FUNCTION__);
++		break;
++	}
++	WAPI_TRACE(WAPI_RX, "<=========== %s\n", __FUNCTION__);
++}
++
++
++void WapiSetLastRxUnicastPNForQoSData(
++	u8		UserPriority,
++	u8           *PNIn,
++	PRT_WAPI_STA_INFO    pWapiStaInfo
++)
++{
++	WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__);
++	switch (UserPriority) {
++	case 0:
++	case 3:
++		memcpy(pWapiStaInfo->lastRxUnicastPNBEQueue, PNIn, 16);
++		break;
++	case 1:
++	case 2:
++		memcpy(pWapiStaInfo->lastRxUnicastPNBKQueue, PNIn, 16);
++		break;
++	case 4:
++	case 5:
++		memcpy(pWapiStaInfo->lastRxUnicastPNVIQueue, PNIn, 16);
++		break;
++	case 6:
++	case 7:
++		memcpy(pWapiStaInfo->lastRxUnicastPNVOQueue, PNIn, 16);
++		break;
++	default:
++		WAPI_TRACE(WAPI_ERR, "%s: Unknown TID\n", __FUNCTION__);
++		break;
++	}
++	WAPI_TRACE(WAPI_RX, "<=========== %s\n", __FUNCTION__);
++}
++
++
++/****************************************************************************
++ FALSE not RX-Reorder
++ TRUE do RX Reorder
++add to support WAPI to N-mode
++*****************************************************************************/
++u8 WapiCheckPnInSwDecrypt(
++	_adapter *padapter,
++	struct sk_buff *pskb
++)
++{
++	u8				ret = false;
++
++#if 0
++	struct ieee80211_hdr_3addr_qos *header;
++	u16				fc;
++	u8				*pDaddr, *pTaddr, *pRaddr;
++
++	header = (struct ieee80211_hdr_3addr_qos *)pskb->data;
++	pTaddr = header->addr2;
++	pRaddr = header->addr1;
++	fc = le16_to_cpu(header->frame_ctl);
++
++	if (GetToDs(&fc))
++		pDaddr = header->addr3;
++	else
++		pDaddr = header->addr1;
++
++	if ((_rtw_memcmp(pRaddr, padapter->pnetdev->dev_addr, ETH_ALEN) == 0)
++	    &&	!(pDaddr)
++	    && (GetFrameType(&fc) == WIFI_QOS_DATA_TYPE))
++		/* && ieee->pHTInfo->bCurrentHTSupport && */
++		/* ieee->pHTInfo->bCurRxReorderEnable) */
++		ret = false;
++	else
++		ret = true;
++#endif
++	WAPI_TRACE(WAPI_RX, "%s: return %d\n", __FUNCTION__, ret);
++	return ret;
++}
++
++int SecSMS4HeaderFillIV(_adapter *padapter, u8 *pxmitframe)
++{
++	struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
++	u8 *frame = ((struct xmit_frame *)pxmitframe)->buf_addr + TXDESC_OFFSET;
++	u8 *pSecHeader = NULL, *pos = NULL, *pRA = NULL;
++	u8 bPNOverflow = false, bFindMatchPeer = false, hdr_len = 0;
++	PWLAN_HEADER_WAPI_EXTENSION pWapiExt = NULL;
++	PRT_WAPI_T         pWapiInfo = &padapter->wapiInfo;
++	PRT_WAPI_STA_INFO  pWapiSta = NULL;
++	int ret = 0;
++
++	WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__);
++
++	return ret;
++#if 0
++	hdr_len = sMacHdrLng;
++	if (GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE)
++		hdr_len += 2;
++	/* hdr_len += SNAP_SIZE + sizeof(u16); */
++
++	pos = skb_push(pskb, padapter->wapiInfo.extra_prefix_len);
++	memmove(pos, pos + padapter->wapiInfo.extra_prefix_len, hdr_len);
++
++	pSecHeader = pskb->data + hdr_len;
++	pWapiExt = (PWLAN_HEADER_WAPI_EXTENSION)pSecHeader;
++	pRA = pskb->data + 4;
++
++	WAPI_DATA(WAPI_TX, "FillIV - Before Fill IV", pskb->data, pskb->len);
++
++	/* Address 1 is always receiver's address */
++	if (IS_MCAST(pRA)) {
++		if (!pWapiInfo->wapiTxMsk.bTxEnable) {
++			WAPI_TRACE(WAPI_ERR, "%s: bTxEnable = 0!!\n", __FUNCTION__);
++			return -2;
++		}
++		if (pWapiInfo->wapiTxMsk.keyId <= 1) {
++			pWapiExt->KeyIdx = pWapiInfo->wapiTxMsk.keyId;
++			pWapiExt->Reserved = 0;
++			bPNOverflow = WapiIncreasePN(pWapiInfo->lastTxMulticastPN, 1);
++			memcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16);
++			if (bPNOverflow) {
++				/* Update MSK Notification. */
++				WAPI_TRACE(WAPI_ERR, "===============>%s():multicast PN overflow\n", __FUNCTION__);
++				rtw_wapi_app_event_handler(padapter, NULL, 0, pRA, false, false, true, 0, false);
++			}
++		} else {
++			WAPI_TRACE(WAPI_ERR, "%s: Invalid Wapi Multicast KeyIdx!!\n", __FUNCTION__);
++			ret = -3;
++		}
++	} else {
++		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
++			if (!memcmp(pWapiSta->PeerMacAddr, pRA, 6)) {
++				bFindMatchPeer = true;
++				break;
++			}
++		}
++		if (bFindMatchPeer) {
++			if ((!pWapiSta->wapiUskUpdate.bTxEnable) && (!pWapiSta->wapiUsk.bTxEnable)) {
++				WAPI_TRACE(WAPI_ERR, "%s: bTxEnable = 0!!\n", __FUNCTION__);
++				return -4;
++			}
++			if (pWapiSta->wapiUsk.keyId <= 1) {
++				if (pWapiSta->wapiUskUpdate.bTxEnable)
++					pWapiExt->KeyIdx = pWapiSta->wapiUskUpdate.keyId;
++				else
++					pWapiExt->KeyIdx = pWapiSta->wapiUsk.keyId;
++
++				pWapiExt->Reserved = 0;
++				bPNOverflow = WapiIncreasePN(pWapiSta->lastTxUnicastPN, 2);
++				memcpy(pWapiExt->PN, pWapiSta->lastTxUnicastPN, 16);
++				if (bPNOverflow) {
++					/* Update USK Notification. */
++					WAPI_TRACE(WAPI_ERR, "===============>%s():unicast PN overflow\n", __FUNCTION__);
++					rtw_wapi_app_event_handler(padapter, NULL, 0, pWapiSta->PeerMacAddr, false, true, false, 0, false);
++				}
++			} else {
++				WAPI_TRACE(WAPI_ERR, "%s: Invalid Wapi Unicast KeyIdx!!\n", __FUNCTION__);
++				ret = -5;
++			}
++		} else {
++			WAPI_TRACE(WAPI_ERR, "%s: Can not find Peer Sta "MAC_FMT"!!\n", __FUNCTION__, MAC_ARG(pRA));
++			ret = -6;
++		}
++	}
++
++	WAPI_DATA(WAPI_TX, "FillIV - After Fill IV", pskb->data, pskb->len);
++	WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__);
++	return ret;
++#endif
++}
++
++/* WAPI SW Enc: must have done Coalesce! */
++void SecSWSMS4Encryption(
++	_adapter *padapter,
++	u8 *pxmitframe
++)
++{
++	PRT_WAPI_T		pWapiInfo = &padapter->wapiInfo;
++	PRT_WAPI_STA_INFO   pWapiSta = NULL;
++	u8 *pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + TXDESC_SIZE;
++	struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
++
++	u8 *SecPtr = NULL, *pRA, *pMicKey = NULL, *pDataKey = NULL, *pIV = NULL;
++	u8 IVOffset, DataOffset, bFindMatchPeer = false, KeyIdx = 0, MicBuffer[16];
++	u16 OutputLength;
++
++	WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__);
++
++	WAPI_TRACE(WAPI_TX, "hdrlen: %d\n", pattrib->hdrlen);
++
++	return;
++
++	DataOffset = pattrib->hdrlen + pattrib->iv_len;
++
++	pRA = pframe + 4;
++
++
++	if (IS_MCAST(pRA)) {
++		KeyIdx = pWapiInfo->wapiTxMsk.keyId;
++		pIV = pWapiInfo->lastTxMulticastPN;
++		pMicKey = pWapiInfo->wapiTxMsk.micKey;
++		pDataKey = pWapiInfo->wapiTxMsk.dataKey;
++	} else {
++		if (!list_empty(&(pWapiInfo->wapiSTAUsedList))) {
++			list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
++				if (0 == memcmp(pWapiSta->PeerMacAddr, pRA, 6)) {
++					bFindMatchPeer = true;
++					break;
++				}
++			}
++
++			if (bFindMatchPeer) {
++				if (pWapiSta->wapiUskUpdate.bTxEnable) {
++					KeyIdx = pWapiSta->wapiUskUpdate.keyId;
++					WAPI_TRACE(WAPI_TX, "%s(): Use update USK!! KeyIdx=%d\n", __FUNCTION__, KeyIdx);
++					pIV = pWapiSta->lastTxUnicastPN;
++					pMicKey = pWapiSta->wapiUskUpdate.micKey;
++					pDataKey = pWapiSta->wapiUskUpdate.dataKey;
++				} else {
++					KeyIdx = pWapiSta->wapiUsk.keyId;
++					WAPI_TRACE(WAPI_TX, "%s(): Use USK!! KeyIdx=%d\n", __FUNCTION__, KeyIdx);
++					pIV = pWapiSta->lastTxUnicastPN;
++					pMicKey = pWapiSta->wapiUsk.micKey;
++					pDataKey = pWapiSta->wapiUsk.dataKey;
++				}
++			} else {
++				WAPI_TRACE(WAPI_ERR, "%s: Can not find Peer Sta!!\n", __FUNCTION__);
++				return;
++			}
++		} else {
++			WAPI_TRACE(WAPI_ERR, "%s: wapiSTAUsedList is empty!!\n", __FUNCTION__);
++			return;
++		}
++	}
++
++	SecPtr = pframe;
++	SecCalculateMicSMS4(KeyIdx, pMicKey, SecPtr, (SecPtr + DataOffset), pattrib->pktlen, MicBuffer);
++
++	WAPI_DATA(WAPI_TX, "Encryption - MIC", MicBuffer, padapter->wapiInfo.extra_postfix_len);
++
++	memcpy(pframe + pattrib->hdrlen + pattrib->iv_len + pattrib->pktlen - pattrib->icv_len,
++	       (u8 *)MicBuffer,
++	       padapter->wapiInfo.extra_postfix_len
++	      );
++
++
++	WapiSMS4Encryption(pDataKey, pIV, (SecPtr + DataOffset), pattrib->pktlen + pattrib->icv_len, (SecPtr + DataOffset), &OutputLength);
++
++	WAPI_DATA(WAPI_TX, "Encryption - After SMS4 encryption", pframe, pattrib->hdrlen + pattrib->iv_len + pattrib->pktlen);
++
++	WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__);
++}
++
++u8 SecSWSMS4Decryption(
++	_adapter *padapter,
++	u8		*precv_frame,
++	struct recv_priv *precv_priv
++)
++{
++	PRT_WAPI_T pWapiInfo = &padapter->wapiInfo;
++	struct recv_frame_hdr *precv_hdr;
++	PRT_WAPI_STA_INFO   pWapiSta = NULL;
++	u8 IVOffset, DataOffset, bFindMatchPeer = false, bUseUpdatedKey = false;
++	u8 KeyIdx, MicBuffer[16], lastRxPNforQoS[16];
++	u8 *pRA, *pTA, *pMicKey, *pDataKey, *pLastRxPN, *pRecvPN, *pSecData, *pRecvMic, *pos;
++	u8 TID = 0;
++	u16 OutputLength, DataLen;
++	u8   bQosData;
++	struct sk_buff	*pskb;
++
++	WAPI_TRACE(WAPI_RX, "=========>%s\n", __FUNCTION__);
++
++	return 0;
++
++	precv_hdr = &((union recv_frame *)precv_frame)->u.hdr;
++	pskb = (struct sk_buff *)(precv_hdr->rx_data);
++	precv_hdr->bWapiCheckPNInDecrypt = WapiCheckPnInSwDecrypt(padapter, pskb);
++	WAPI_TRACE(WAPI_RX, "=========>%s: check PN  %d\n", __FUNCTION__, precv_hdr->bWapiCheckPNInDecrypt);
++	WAPI_DATA(WAPI_RX, "Decryption - Before decryption", pskb->data, pskb->len);
++
++	IVOffset = sMacHdrLng;
++	bQosData = GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE;
++	if (bQosData)
++		IVOffset += 2;
++
++	/* if(GetHTC()) */
++	/*	IVOffset += 4; */
++
++	/* IVOffset += SNAP_SIZE + sizeof(u16); */
++
++	DataOffset = IVOffset + padapter->wapiInfo.extra_prefix_len;
++
++	pRA = pskb->data + 4;
++	pTA = pskb->data + 10;
++	KeyIdx = *(pskb->data + IVOffset);
++	pRecvPN = pskb->data + IVOffset + 2;
++	pSecData = pskb->data + DataOffset;
++	DataLen = pskb->len - DataOffset;
++	pRecvMic = pskb->data + pskb->len - padapter->wapiInfo.extra_postfix_len;
++	TID = GetTid(pskb->data);
++
++	if (!list_empty(&(pWapiInfo->wapiSTAUsedList))) {
++		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
++			if (0 == memcmp(pWapiSta->PeerMacAddr, pTA, 6)) {
++				bFindMatchPeer = true;
++				break;
++			}
++		}
++	}
++
++	if (!bFindMatchPeer) {
++		WAPI_TRACE(WAPI_ERR, "%s: Can not find Peer Sta "MAC_FMT" for Key Info!!!\n", __FUNCTION__, MAC_ARG(pTA));
++		return false;
++	}
++
++	if (IS_MCAST(pRA)) {
++		WAPI_TRACE(WAPI_RX, "%s: Multicast decryption !!!\n", __FUNCTION__);
++		if (pWapiSta->wapiMsk.keyId == KeyIdx && pWapiSta->wapiMsk.bSet) {
++			pLastRxPN = pWapiSta->lastRxMulticastPN;
++			if (!WapiComparePN(pRecvPN, pLastRxPN)) {
++				WAPI_TRACE(WAPI_ERR, "%s: MSK PN is not larger than last, Dropped!!!\n", __FUNCTION__);
++				WAPI_DATA(WAPI_ERR, "pRecvPN:", pRecvPN, 16);
++				WAPI_DATA(WAPI_ERR, "pLastRxPN:", pLastRxPN, 16);
++				return false;
++			}
++
++			memcpy(pLastRxPN, pRecvPN, 16);
++			pMicKey = pWapiSta->wapiMsk.micKey;
++			pDataKey = pWapiSta->wapiMsk.dataKey;
++		} else if (pWapiSta->wapiMskUpdate.keyId == KeyIdx && pWapiSta->wapiMskUpdate.bSet) {
++			WAPI_TRACE(WAPI_RX, "%s: Use Updated MSK for Decryption !!!\n", __FUNCTION__);
++			bUseUpdatedKey = true;
++			memcpy(pWapiSta->lastRxMulticastPN, pRecvPN, 16);
++			pMicKey = pWapiSta->wapiMskUpdate.micKey;
++			pDataKey = pWapiSta->wapiMskUpdate.dataKey;
++		} else {
++			WAPI_TRACE(WAPI_ERR, "%s: Can not find MSK with matched KeyIdx(%d), Dropped !!!\n", __FUNCTION__, KeyIdx);
++			return false;
++		}
++	} else {
++		WAPI_TRACE(WAPI_RX, "%s: Unicast decryption !!!\n", __FUNCTION__);
++		if (pWapiSta->wapiUsk.keyId == KeyIdx && pWapiSta->wapiUsk.bSet) {
++			WAPI_TRACE(WAPI_RX, "%s: Use USK for Decryption!!!\n", __FUNCTION__);
++			if (precv_hdr->bWapiCheckPNInDecrypt) {
++				if (GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE) {
++					WapiGetLastRxUnicastPNForQoSData(TID, pWapiSta, lastRxPNforQoS);
++					pLastRxPN = lastRxPNforQoS;
++				} else
++					pLastRxPN = pWapiSta->lastRxUnicastPN;
++				if (!WapiComparePN(pRecvPN, pLastRxPN))
++					return false;
++				if (bQosData)
++					WapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta);
++				else
++					memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16);
++			} else
++				memcpy(precv_hdr->WapiTempPN, pRecvPN, 16);
++
++			if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE)) {
++				if ((pRecvPN[0] & 0x1) == 0) {
++					WAPI_TRACE(WAPI_ERR, "%s: Rx USK PN is not odd when Infra STA mode, Dropped !!!\n", __FUNCTION__);
++					return false;
++				}
++			}
++
++			pMicKey = pWapiSta->wapiUsk.micKey;
++			pDataKey = pWapiSta->wapiUsk.dataKey;
++		} else if (pWapiSta->wapiUskUpdate.keyId == KeyIdx && pWapiSta->wapiUskUpdate.bSet) {
++			WAPI_TRACE(WAPI_RX, "%s: Use Updated USK for Decryption!!!\n", __FUNCTION__);
++			if (pWapiSta->bAuthenticatorInUpdata)
++				bUseUpdatedKey = true;
++			else
++				bUseUpdatedKey = false;
++
++			if (bQosData)
++				WapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta);
++			else
++				memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16);
++			pMicKey = pWapiSta->wapiUskUpdate.micKey;
++			pDataKey = pWapiSta->wapiUskUpdate.dataKey;
++		} else {
++			WAPI_TRACE(WAPI_ERR, "%s: No valid USK!!!KeyIdx=%d pWapiSta->wapiUsk.keyId=%d pWapiSta->wapiUskUpdate.keyId=%d\n", __FUNCTION__, KeyIdx, pWapiSta->wapiUsk.keyId,
++				   pWapiSta->wapiUskUpdate.keyId);
++			/* dump_buf(pskb->data,pskb->len); */
++			return false;
++		}
++	}
++
++	WAPI_DATA(WAPI_RX, "Decryption - DataKey", pDataKey, 16);
++	WAPI_DATA(WAPI_RX, "Decryption - IV", pRecvPN, 16);
++	WapiSMS4Decryption(pDataKey, pRecvPN, pSecData, DataLen, pSecData, &OutputLength);
++
++	if (OutputLength != DataLen)
++		WAPI_TRACE(WAPI_ERR, "%s:  Output Length Error!!!!\n", __FUNCTION__);
++
++	WAPI_DATA(WAPI_RX, "Decryption - After decryption", pskb->data, pskb->len);
++
++	DataLen -= padapter->wapiInfo.extra_postfix_len;
++
++	SecCalculateMicSMS4(KeyIdx, pMicKey, pskb->data, pSecData, DataLen, MicBuffer);
++
++	WAPI_DATA(WAPI_RX, "Decryption - MIC received", pRecvMic, SMS4_MIC_LEN);
++	WAPI_DATA(WAPI_RX, "Decryption - MIC calculated", MicBuffer, SMS4_MIC_LEN);
++
++	if (0 == memcmp(MicBuffer, pRecvMic, padapter->wapiInfo.extra_postfix_len)) {
++		WAPI_TRACE(WAPI_RX, "%s: Check MIC OK!!\n", __FUNCTION__);
++		if (bUseUpdatedKey) {
++			/* delete the old key */
++			if (IS_MCAST(pRA)) {
++				WAPI_TRACE(WAPI_API, "%s(): AE use new update MSK!!\n", __FUNCTION__);
++				pWapiSta->wapiMsk.keyId = pWapiSta->wapiMskUpdate.keyId;
++				memcpy(pWapiSta->wapiMsk.dataKey, pWapiSta->wapiMskUpdate.dataKey, 16);
++				memcpy(pWapiSta->wapiMsk.micKey, pWapiSta->wapiMskUpdate.micKey, 16);
++				pWapiSta->wapiMskUpdate.bTxEnable = pWapiSta->wapiMskUpdate.bSet = false;
++			} else {
++				WAPI_TRACE(WAPI_API, "%s(): AE use new update USK!!\n", __FUNCTION__);
++				pWapiSta->wapiUsk.keyId = pWapiSta->wapiUskUpdate.keyId;
++				memcpy(pWapiSta->wapiUsk.dataKey, pWapiSta->wapiUskUpdate.dataKey, 16);
++				memcpy(pWapiSta->wapiUsk.micKey, pWapiSta->wapiUskUpdate.micKey, 16);
++				pWapiSta->wapiUskUpdate.bTxEnable = pWapiSta->wapiUskUpdate.bSet = false;
++			}
++		}
++	} else {
++		WAPI_TRACE(WAPI_ERR, "%s:  Check MIC Error, Dropped !!!!\n", __FUNCTION__);
++		return false;
++	}
++
++	pos = pskb->data;
++	memmove(pos + padapter->wapiInfo.extra_prefix_len, pos, IVOffset);
++	skb_pull(pskb, padapter->wapiInfo.extra_prefix_len);
++
++	WAPI_TRACE(WAPI_RX, "<=========%s\n", __FUNCTION__);
++
++	return true;
++}
++
++u32	rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe)
++{
++
++	u8	*pframe;
++	u32 res = _SUCCESS;
++
++	WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__);
++
++	if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {
++		WAPI_TRACE(WAPI_TX, "<========== %s, WAPI not supported or enabled!\n", __FUNCTION__);
++		return _FAIL;
++	}
++
++	if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
++		return _FAIL;
++
++	pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + TXDESC_OFFSET;
++
++	SecSWSMS4Encryption(padapter, pxmitframe);
++
++	WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__);
++	return res;
++}
++
++u32	rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe)
++{
++	u8	*pframe;
++	u32 res = _SUCCESS;
++
++	WAPI_TRACE(WAPI_RX, "=========>%s\n", __FUNCTION__);
++
++	if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {
++		WAPI_TRACE(WAPI_RX, "<========== %s, WAPI not supported or enabled!\n", __FUNCTION__);
++		return _FAIL;
++	}
++
++
++	/* drop packet when hw decrypt fail
++	* return tempraily */
++	return _FAIL;
++
++	/* pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; */
++
++	if (false == SecSWSMS4Decryption(padapter, precvframe, &padapter->recvpriv)) {
++		WAPI_TRACE(WAPI_ERR, "%s():SMS4 decrypt frame error\n", __FUNCTION__);
++		return _FAIL;
++	}
++
++	WAPI_TRACE(WAPI_RX, "<=========%s\n", __FUNCTION__);
++	return res;
++}
++
++#else
++
++u32	rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe)
++{
++	WAPI_TRACE(WAPI_TX, "=========>Dummy %s\n", __FUNCTION__);
++	WAPI_TRACE(WAPI_TX, "<=========Dummy %s\n", __FUNCTION__);
++	return _SUCCESS;
++}
++
++u32	rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe)
++{
++	WAPI_TRACE(WAPI_RX, "=========>Dummy %s\n", __FUNCTION__);
++	WAPI_TRACE(WAPI_RX, "<=========Dummy %s\n", __FUNCTION__);
++	return _SUCCESS;
++}
++
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_wlan_util.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_wlan_util.c
+new file mode 100755
+index 000000000..82bb6f282
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_wlan_util.c
+@@ -0,0 +1,5029 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_WLAN_UTIL_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++	#include <linux/inetdevice.h>
++	#define ETH_TYPE_OFFSET	12
++	#define PROTOCOL_OFFSET	23
++	#define IP_OFFSET	30
++	#define IPv6_OFFSET	38
++	#define IPv6_PROTOCOL_OFFSET	20
++#endif
++
++unsigned char ARTHEROS_OUI1[] = {0x00, 0x03, 0x7f};
++unsigned char ARTHEROS_OUI2[] = {0x00, 0x13, 0x74};
++
++unsigned char BROADCOM_OUI1[] = {0x00, 0x10, 0x18};
++unsigned char BROADCOM_OUI2[] = {0x00, 0x0a, 0xf7};
++unsigned char BROADCOM_OUI3[] = {0x00, 0x05, 0xb5};
++
++
++unsigned char CISCO_OUI[] = {0x00, 0x40, 0x96};
++unsigned char MARVELL_OUI[] = {0x00, 0x50, 0x43};
++unsigned char RALINK_OUI[] = {0x00, 0x0c, 0x43};
++unsigned char REALTEK_OUI[] = {0x00, 0xe0, 0x4c};
++unsigned char AIRGOCAP_OUI[] = {0x00, 0x0a, 0xf5};
++
++unsigned char REALTEK_96B_IE[] = {0x00, 0xe0, 0x4c, 0x02, 0x01, 0x20};
++
++extern unsigned char RTW_WPA_OUI[];
++extern unsigned char WPA_TKIP_CIPHER[4];
++extern unsigned char RSN_TKIP_CIPHER[4];
++
++#define R2T_PHY_DELAY	(0)
++
++/* #define WAIT_FOR_BCN_TO_MIN	(3000) */
++#define WAIT_FOR_BCN_TO_MIN	(6000)
++#define WAIT_FOR_BCN_TO_MAX	(20000)
++
++static u8 rtw_basic_rate_cck[4] = {
++	IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK,
++	IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK
++};
++
++static u8 rtw_basic_rate_ofdm[3] = {
++	IEEE80211_OFDM_RATE_6MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_12MB | IEEE80211_BASIC_RATE_MASK,
++	IEEE80211_OFDM_RATE_24MB | IEEE80211_BASIC_RATE_MASK
++};
++
++static u8 rtw_basic_rate_mix[7] = {
++	IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK,
++	IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK,
++	IEEE80211_OFDM_RATE_6MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_12MB | IEEE80211_BASIC_RATE_MASK,
++	IEEE80211_OFDM_RATE_24MB | IEEE80211_BASIC_RATE_MASK
++};
++
++extern u8	WIFI_CCKRATES[];
++bool rtw_is_cck_rate(u8 rate)
++{
++	int i;
++
++	for (i = 0; i < 4; i++)
++		if ((WIFI_CCKRATES[i] & 0x7F) == (rate & 0x7F))
++			return 1;
++	return 0;
++}
++
++extern u8	WIFI_OFDMRATES[];
++bool rtw_is_ofdm_rate(u8 rate)
++{
++	int i;
++
++	for (i = 0; i < 8; i++)
++		if ((WIFI_OFDMRATES[i] & 0x7F) == (rate & 0x7F))
++			return 1;
++	return 0;
++}
++
++/* test if rate is defined in rtw_basic_rate_cck */
++bool rtw_is_basic_rate_cck(u8 rate)
++{
++	int i;
++
++	for (i = 0; i < 4; i++)
++		if ((rtw_basic_rate_cck[i] & 0x7F) == (rate & 0x7F))
++			return 1;
++	return 0;
++}
++
++/* test if rate is defined in rtw_basic_rate_ofdm */
++bool rtw_is_basic_rate_ofdm(u8 rate)
++{
++	int i;
++
++	for (i = 0; i < 3; i++)
++		if ((rtw_basic_rate_ofdm[i] & 0x7F) == (rate & 0x7F))
++			return 1;
++	return 0;
++}
++
++/* test if rate is defined in rtw_basic_rate_mix */
++bool rtw_is_basic_rate_mix(u8 rate)
++{
++	int i;
++
++	for (i = 0; i < 7; i++)
++		if ((rtw_basic_rate_mix[i] & 0x7F) == (rate & 0x7F))
++			return 1;
++	return 0;
++}
++#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
++int new_bcn_max = 3;
++#endif
++int cckrates_included(unsigned char *rate, int ratelen)
++{
++	int	i;
++
++	for (i = 0; i < ratelen; i++) {
++		if ((((rate[i]) & 0x7f) == 2)	|| (((rate[i]) & 0x7f) == 4) ||
++		    (((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) == 22))
++			return _TRUE;
++	}
++
++	return _FALSE;
++
++}
++
++int cckratesonly_included(unsigned char *rate, int ratelen)
++{
++	int	i;
++
++	for (i = 0; i < ratelen; i++) {
++		if ((((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) &&
++		    (((rate[i]) & 0x7f) != 11)  && (((rate[i]) & 0x7f) != 22))
++			return _FALSE;
++	}
++
++	return _TRUE;
++}
++
++s8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta)
++{
++	s8 nss = 1;
++
++	if (!psta)
++		return nss;
++
++	nss = GET_HAL_RX_NSS(adapter);
++
++#ifdef CONFIG_80211N_HT
++	#ifdef CONFIG_80211AC_VHT
++	if (psta->vhtpriv.vht_option)
++		nss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map));
++	else
++	#endif /* CONFIG_80211AC_VHT */
++	if (psta->htpriv.ht_option)
++		nss = rtw_min(nss, rtw_ht_mcsset_to_nss(psta->htpriv.ht_cap.supp_mcs_set));
++#endif /*CONFIG_80211N_HT*/
++	RTW_INFO("%s: %d ss\n", __func__, nss);
++	return nss;
++}
++
++s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta)
++{
++	s8 nss = 1;
++
++	if (!psta)
++		return nss;
++
++	nss = GET_HAL_TX_NSS(adapter);
++
++#ifdef CONFIG_80211N_HT
++	#ifdef CONFIG_80211AC_VHT
++	if (psta->vhtpriv.vht_option)
++		nss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map));
++	else
++	#endif /* CONFIG_80211AC_VHT */
++	if (psta->htpriv.ht_option)
++		nss = rtw_min(nss, rtw_ht_mcsset_to_nss(psta->htpriv.ht_cap.supp_mcs_set));
++#endif /*CONFIG_80211N_HT*/
++	RTW_INFO("%s: %d SS\n", __func__, nss);
++	return nss;
++}
++
++u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen)
++{
++	u8 network_type = 0;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++
++	if (pmlmeext->cur_channel > 14) {
++		if (pmlmeinfo->VHT_enable)
++			network_type = WIRELESS_11AC;
++		else if (pmlmeinfo->HT_enable)
++			network_type = WIRELESS_11_5N;
++
++		network_type |= WIRELESS_11A;
++	} else {
++		if (pmlmeinfo->HT_enable)
++			network_type = WIRELESS_11_24N;
++
++		if ((cckratesonly_included(rate, ratelen)) == _TRUE)
++			network_type |= WIRELESS_11B;
++		else if ((cckrates_included(rate, ratelen)) == _TRUE)
++			network_type |= WIRELESS_11BG;
++		else
++			network_type |= WIRELESS_11G;
++	}
++
++	return	network_type;
++}
++
++unsigned char ratetbl_val_2wifirate(unsigned char rate);
++unsigned char ratetbl_val_2wifirate(unsigned char rate)
++{
++	unsigned char val = 0;
++
++	switch (rate & 0x7f) {
++	case 0:
++		val = IEEE80211_CCK_RATE_1MB;
++		break;
++
++	case 1:
++		val = IEEE80211_CCK_RATE_2MB;
++		break;
++
++	case 2:
++		val = IEEE80211_CCK_RATE_5MB;
++		break;
++
++	case 3:
++		val = IEEE80211_CCK_RATE_11MB;
++		break;
++
++	case 4:
++		val = IEEE80211_OFDM_RATE_6MB;
++		break;
++
++	case 5:
++		val = IEEE80211_OFDM_RATE_9MB;
++		break;
++
++	case 6:
++		val = IEEE80211_OFDM_RATE_12MB;
++		break;
++
++	case 7:
++		val = IEEE80211_OFDM_RATE_18MB;
++		break;
++
++	case 8:
++		val = IEEE80211_OFDM_RATE_24MB;
++		break;
++
++	case 9:
++		val = IEEE80211_OFDM_RATE_36MB;
++		break;
++
++	case 10:
++		val = IEEE80211_OFDM_RATE_48MB;
++		break;
++
++	case 11:
++		val = IEEE80211_OFDM_RATE_54MB;
++		break;
++
++	}
++
++	return val;
++
++}
++
++int is_basicrate(_adapter *padapter, unsigned char rate);
++int is_basicrate(_adapter *padapter, unsigned char rate)
++{
++	int i;
++	unsigned char val;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++	for (i = 0; i < NumRates; i++) {
++		val = pmlmeext->basicrate[i];
++
++		if ((val != 0xff) && (val != 0xfe)) {
++			if (rate == ratetbl_val_2wifirate(val))
++				return _TRUE;
++		}
++	}
++
++	return _FALSE;
++}
++
++unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset);
++unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset)
++{
++	int i;
++	unsigned char rate;
++	unsigned int	len = 0;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++	for (i = 0; i < NumRates; i++) {
++		rate = pmlmeext->datarate[i];
++
++		if (rtw_get_oper_ch(padapter) > 14 && rate < _6M_RATE_) /*5G no support CCK rate*/
++			continue;
++
++		switch (rate) {
++		case 0xff:
++			return len;
++
++		case 0xfe:
++			continue;
++
++		default:
++			rate = ratetbl_val_2wifirate(rate);
++
++			if (is_basicrate(padapter, rate) == _TRUE)
++				rate |= IEEE80211_BASIC_RATE_MASK;
++
++			rateset[len] = rate;
++			len++;
++			break;
++		}
++	}
++	return len;
++}
++
++void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len)
++{
++	unsigned char supportedrates[NumRates];
++
++	_rtw_memset(supportedrates, 0, NumRates);
++	*bssrate_len = ratetbl2rateset(padapter, supportedrates);
++	_rtw_memcpy(pbssrate, supportedrates, *bssrate_len);
++}
++
++void set_mcs_rate_by_mask(u8 *mcs_set, u32 mask)
++{
++	u8 mcs_rate_1r = (u8)(mask & 0xff);
++	u8 mcs_rate_2r = (u8)((mask >> 8) & 0xff);
++	u8 mcs_rate_3r = (u8)((mask >> 16) & 0xff);
++	u8 mcs_rate_4r = (u8)((mask >> 24) & 0xff);
++
++	mcs_set[0] &= mcs_rate_1r;
++	mcs_set[1] &= mcs_rate_2r;
++	mcs_set[2] &= mcs_rate_3r;
++	mcs_set[3] &= mcs_rate_4r;
++}
++
++void UpdateBrateTbl(
++	PADAPTER		Adapter,
++	u8			*mBratesOS
++)
++{
++	u8	i;
++	u8	rate;
++
++	/* 1M, 2M, 5.5M, 11M, 6M, 12M, 24M are mandatory. */
++	for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
++		rate = mBratesOS[i] & 0x7f;
++		switch (rate) {
++		case IEEE80211_CCK_RATE_1MB:
++		case IEEE80211_CCK_RATE_2MB:
++		case IEEE80211_CCK_RATE_5MB:
++		case IEEE80211_CCK_RATE_11MB:
++		case IEEE80211_OFDM_RATE_6MB:
++		case IEEE80211_OFDM_RATE_12MB:
++		case IEEE80211_OFDM_RATE_24MB:
++			mBratesOS[i] |= IEEE80211_BASIC_RATE_MASK;
++			break;
++		}
++	}
++
++}
++
++void UpdateBrateTblForSoftAP(u8 *bssrateset, u32 bssratelen)
++{
++	u8	i;
++	u8	rate;
++
++	for (i = 0; i < bssratelen; i++) {
++		rate = bssrateset[i] & 0x7f;
++		switch (rate) {
++		case IEEE80211_CCK_RATE_1MB:
++		case IEEE80211_CCK_RATE_2MB:
++		case IEEE80211_CCK_RATE_5MB:
++		case IEEE80211_CCK_RATE_11MB:
++			bssrateset[i] |= IEEE80211_BASIC_RATE_MASK;
++			break;
++		}
++	}
++
++}
++void Set_MSR(_adapter *padapter, u8 type)
++{
++	rtw_hal_set_hwreg(padapter, HW_VAR_MEDIA_STATUS, (u8 *)(&type));
++}
++
++inline u8 rtw_get_oper_ch(_adapter *adapter)
++{
++	return adapter_to_dvobj(adapter)->oper_channel;
++}
++
++inline void rtw_set_oper_ch(_adapter *adapter, u8 ch)
++{
++#ifdef DBG_CH_SWITCH
++	const int len = 128;
++	char msg[128] = {0};
++	int cnt = 0;
++	int i = 0;
++#endif  /* DBG_CH_SWITCH */
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++	if (dvobj->oper_channel != ch) {
++		dvobj->on_oper_ch_time = rtw_get_current_time();
++
++#ifdef DBG_CH_SWITCH
++		cnt += snprintf(msg + cnt, len - cnt, "switch to ch %3u", ch);
++
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			_adapter *iface = dvobj->padapters[i];
++			cnt += snprintf(msg + cnt, len - cnt, " ["ADPT_FMT":", ADPT_ARG(iface));
++			if (iface->mlmeextpriv.cur_channel == ch)
++				cnt += snprintf(msg + cnt, len - cnt, "C");
++			else
++				cnt += snprintf(msg + cnt, len - cnt, "_");
++			if (iface->wdinfo.listen_channel == ch && !rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_NONE))
++				cnt += snprintf(msg + cnt, len - cnt, "L");
++			else
++				cnt += snprintf(msg + cnt, len - cnt, "_");
++			cnt += snprintf(msg + cnt, len - cnt, "]");
++		}
++
++		RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(adapter), msg);
++#endif /* DBG_CH_SWITCH */
++	}
++
++	dvobj->oper_channel = ch;
++}
++
++inline u8 rtw_get_oper_bw(_adapter *adapter)
++{
++	return adapter_to_dvobj(adapter)->oper_bwmode;
++}
++
++inline void rtw_set_oper_bw(_adapter *adapter, u8 bw)
++{
++	adapter_to_dvobj(adapter)->oper_bwmode = bw;
++}
++
++inline u8 rtw_get_oper_choffset(_adapter *adapter)
++{
++	return adapter_to_dvobj(adapter)->oper_ch_offset;
++}
++
++inline void rtw_set_oper_choffset(_adapter *adapter, u8 offset)
++{
++	adapter_to_dvobj(adapter)->oper_ch_offset = offset;
++}
++
++inline systime rtw_get_on_oper_ch_time(_adapter *adapter)
++{
++	return adapter_to_dvobj(adapter)->on_oper_ch_time;
++}
++
++inline systime rtw_get_on_cur_ch_time(_adapter *adapter)
++{
++	if (adapter->mlmeextpriv.cur_channel == adapter_to_dvobj(adapter)->oper_channel)
++		return adapter_to_dvobj(adapter)->on_oper_ch_time;
++	else
++		return 0;
++}
++
++void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode)
++{
++	u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE)
++	u8 iqk_info_backup = _FALSE;
++#endif
++
++	if (padapter->bNotifyChannelChange)
++		RTW_INFO("[%s] ch = %d, offset = %d, bwmode = %d\n", __FUNCTION__, channel, channel_offset, bwmode);
++
++	center_ch = rtw_get_center_ch(channel, bwmode, channel_offset);
++
++	if (bwmode == CHANNEL_WIDTH_80) {
++		if (center_ch > channel)
++			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
++		else if (center_ch < channel)
++			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
++		else
++			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++	}
++	_enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
++
++#ifdef CONFIG_MCC_MODE
++	if (MCC_EN(padapter)) {
++		/* driver doesn't set channel setting reg under MCC */
++		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
++			RTW_INFO("Warning: Do not set channel setting reg MCC mode\n");
++	}
++#endif
++
++#ifdef CONFIG_DFS_MASTER
++	{
++		struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++		bool ori_overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl);
++		bool new_overlap_radar_detect_ch = _rtw_rfctl_overlap_radar_detect_ch(rfctl, channel, bwmode, channel_offset);
++
++		if (new_overlap_radar_detect_ch && IS_CH_WAITING(rfctl)) {
++			u8 pause = 0xFF;
++
++			rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause);
++		}
++#endif /* CONFIG_DFS_MASTER */
++
++		/* set Channel */
++		/* saved channel/bw info */
++		rtw_set_oper_ch(padapter, channel);
++		rtw_set_oper_bw(padapter, bwmode);
++		rtw_set_oper_choffset(padapter, channel_offset);
++
++#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE)
++		/* To check if we need to backup iqk info after switch chnl & bw */
++		{
++			u8 take_care_iqk, do_iqk;
++
++			rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
++			rtw_hal_get_hwreg(padapter, HW_VAR_DO_IQK, &do_iqk);
++			if ((take_care_iqk == _TRUE) && (do_iqk == _TRUE))
++				iqk_info_backup = _TRUE;
++		}
++#endif
++
++		rtw_hal_set_chnl_bw(padapter, center_ch, bwmode, channel_offset, chnl_offset80); /* set center channel */
++
++#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE)
++		if (iqk_info_backup == _TRUE)
++			rtw_hal_ch_sw_iqk_info_backup(padapter);
++#endif
++
++#ifdef CONFIG_DFS_MASTER
++		if (new_overlap_radar_detect_ch)
++			rtw_odm_radar_detect_enable(padapter);
++		else if (ori_overlap_radar_detect_ch) {
++			u8 pause = 0x00;
++
++			rtw_odm_radar_detect_disable(padapter);
++			rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause);
++		}
++	}
++#endif /* CONFIG_DFS_MASTER */
++
++	_exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
++}
++
++__inline u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork)
++{
++	return pnetwork->MacAddress;
++}
++
++u16 get_beacon_interval(WLAN_BSSID_EX *bss)
++{
++	unsigned short val;
++	_rtw_memcpy((unsigned char *)&val, rtw_get_beacon_interval_from_ie(bss->IEs), 2);
++
++	return le16_to_cpu(val);
++
++}
++
++int is_client_associated_to_ap(_adapter *padapter)
++{
++	struct mlme_ext_priv	*pmlmeext;
++	struct mlme_ext_info	*pmlmeinfo;
++
++	if (!padapter)
++		return _FAIL;
++
++	pmlmeext = &padapter->mlmeextpriv;
++	pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE))
++		return _TRUE;
++	else
++		return _FAIL;
++}
++
++int is_client_associated_to_ibss(_adapter *padapter)
++{
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE))
++		return _TRUE;
++	else
++		return _FAIL;
++}
++
++int is_IBSS_empty(_adapter *padapter)
++{
++	int i;
++	struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl;
++
++	for (i = 0; i < macid_ctl->num; i++) {
++		if (!rtw_macid_is_used(macid_ctl, i))
++			continue;
++		if (!rtw_macid_is_iface_specific(macid_ctl, i, padapter))
++			continue;
++		if (!GET_H2CCMD_MSRRPT_PARM_OPMODE(&macid_ctl->h2c_msr[i]))
++			continue;
++		if (GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]) == H2C_MSR_ROLE_ADHOC)
++			return _FAIL;
++	}
++
++	return _TRUE;
++}
++
++unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval)
++{
++	if ((bcn_interval << 2) < WAIT_FOR_BCN_TO_MIN)
++		return WAIT_FOR_BCN_TO_MIN;
++	else if ((bcn_interval << 2) > WAIT_FOR_BCN_TO_MAX)
++		return WAIT_FOR_BCN_TO_MAX;
++	else
++		return bcn_interval << 2;
++}
++
++void invalidate_cam_all(_adapter *padapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	u8 bmc_id = rtw_iface_bcmc_id_get(padapter);
++	_irqL irqL;
++	u8 val8 = 0;
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_CAM_INVALID_ALL, &val8);
++
++	_enter_critical_bh(&cam_ctl->lock, &irqL);
++
++	rtw_sec_cam_map_clr_all(&cam_ctl->used);
++
++#ifndef SEC_DEFAULT_KEY_SEARCH
++	/* for BMC data TX with force camid */
++	if (bmc_id != INVALID_SEC_MAC_CAM_ID) {
++		rtw_sec_cam_map_set(&cam_ctl->used, bmc_id);
++		if (_rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_EXTRA_SEC))
++			rtw_sec_cam_map_set(&cam_ctl->used, bmc_id + 1);
++	}
++#endif
++
++	_rtw_memset(dvobj->cam_cache, 0, sizeof(struct sec_cam_ent) * SEC_CAM_ENT_NUM_SW_LIMIT);
++	_exit_critical_bh(&cam_ctl->lock, &irqL);
++
++#ifdef SEC_DEFAULT_KEY_SEARCH//!BMC TX force camid
++	/* clear default key related key search setting */
++	rtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8 *)_FALSE);
++#endif
++}
++
++void _clear_cam_entry(_adapter *padapter, u8 entry)
++{
++	unsigned char null_sta[6] = {0};
++	unsigned char null_key[32] = {0};
++
++	rtw_sec_write_cam_ent(padapter, entry, 0, null_sta, null_key);
++}
++
++inline void _write_cam(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)
++{
++#ifdef CONFIG_WRITE_CACHE_ONLY
++	write_cam_cache(adapter, id , ctrl, mac, key);
++#else
++	rtw_sec_write_cam_ent(adapter, id, ctrl, mac, key);
++	write_cam_cache(adapter, id , ctrl, mac, key);
++#endif
++}
++
++inline void write_cam(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)
++{
++	if (ctrl & BIT(9)) {
++		_write_cam(adapter, id, ctrl, mac, key);
++		_write_cam(adapter, (id + 1), ctrl | BIT(5), mac, (key + 16));
++		RTW_INFO_DUMP("key-0: ", key, 16);
++		RTW_INFO_DUMP("key-1: ", (key + 16), 16);
++	} else
++		_write_cam(adapter, id, ctrl, mac, key);
++}
++
++inline void clear_cam_entry(_adapter *adapter, u8 id)
++{
++	_clear_cam_entry(adapter, id);
++	clear_cam_cache(adapter, id);
++}
++
++inline void write_cam_from_cache(_adapter *adapter, u8 id)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	_irqL irqL;
++	struct sec_cam_ent cache;
++
++	_enter_critical_bh(&cam_ctl->lock, &irqL);
++	_rtw_memcpy(&cache, &dvobj->cam_cache[id], sizeof(struct sec_cam_ent));
++	_exit_critical_bh(&cam_ctl->lock, &irqL);
++
++	rtw_sec_write_cam_ent(adapter, id, cache.ctrl, cache.mac, cache.key);
++}
++void write_cam_cache(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	_irqL irqL;
++
++	_enter_critical_bh(&cam_ctl->lock, &irqL);
++
++	dvobj->cam_cache[id].ctrl = ctrl;
++	_rtw_memcpy(dvobj->cam_cache[id].mac, mac, ETH_ALEN);
++	_rtw_memcpy(dvobj->cam_cache[id].key, key, 16);
++
++	_exit_critical_bh(&cam_ctl->lock, &irqL);
++}
++
++void clear_cam_cache(_adapter *adapter, u8 id)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	_irqL irqL;
++
++	_enter_critical_bh(&cam_ctl->lock, &irqL);
++
++	_rtw_memset(&(dvobj->cam_cache[id]), 0, sizeof(struct sec_cam_ent));
++
++	_exit_critical_bh(&cam_ctl->lock, &irqL);
++}
++
++inline bool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++
++	if (cam_ctl->sec_cap & cap)
++		return _TRUE;
++	return _FALSE;
++}
++
++inline void _rtw_camctl_set_flags(_adapter *adapter, u32 flags)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++
++	cam_ctl->flags |= flags;
++}
++
++inline void rtw_camctl_set_flags(_adapter *adapter, u32 flags)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	_irqL irqL;
++
++	_enter_critical_bh(&cam_ctl->lock, &irqL);
++	_rtw_camctl_set_flags(adapter, flags);
++	_exit_critical_bh(&cam_ctl->lock, &irqL);
++}
++
++inline void _rtw_camctl_clr_flags(_adapter *adapter, u32 flags)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++
++	cam_ctl->flags &= ~flags;
++}
++
++inline void rtw_camctl_clr_flags(_adapter *adapter, u32 flags)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	_irqL irqL;
++
++	_enter_critical_bh(&cam_ctl->lock, &irqL);
++	_rtw_camctl_clr_flags(adapter, flags);
++	_exit_critical_bh(&cam_ctl->lock, &irqL);
++}
++
++inline bool _rtw_camctl_chk_flags(_adapter *adapter, u32 flags)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++
++	if (cam_ctl->flags & flags)
++		return _TRUE;
++	return _FALSE;
++}
++
++void dump_sec_cam_map(void *sel, struct sec_cam_bmp *map, u8 max_num)
++{
++	RTW_PRINT_SEL(sel, "0x%08x\n", map->m0);
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
++	if (max_num && max_num > 32)
++		RTW_PRINT_SEL(sel, "0x%08x\n", map->m1);
++#endif
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
++	if (max_num && max_num > 64)
++		RTW_PRINT_SEL(sel, "0x%08x\n", map->m2);
++#endif
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
++	if (max_num && max_num > 96)
++		RTW_PRINT_SEL(sel, "0x%08x\n", map->m3);
++#endif
++}
++
++inline bool rtw_sec_camid_is_set(struct sec_cam_bmp *map, u8 id)
++{
++	if (id < 32)
++		return map->m0 & BIT(id);
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
++	else if (id < 64)
++		return map->m1 & BIT(id - 32);
++#endif
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
++	else if (id < 96)
++		return map->m2 & BIT(id - 64);
++#endif
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
++	else if (id < 128)
++		return map->m3 & BIT(id - 96);
++#endif
++	else
++		rtw_warn_on(1);
++
++	return 0;
++}
++
++inline void rtw_sec_cam_map_set(struct sec_cam_bmp *map, u8 id)
++{
++	if (id < 32)
++		map->m0 |= BIT(id);
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
++	else if (id < 64)
++		map->m1 |= BIT(id - 32);
++#endif
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
++	else if (id < 96)
++		map->m2 |= BIT(id - 64);
++#endif
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
++	else if (id < 128)
++		map->m3 |= BIT(id - 96);
++#endif
++	else
++		rtw_warn_on(1);
++}
++
++inline void rtw_sec_cam_map_clr(struct sec_cam_bmp *map, u8 id)
++{
++	if (id < 32)
++		map->m0 &= ~BIT(id);
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
++	else if (id < 64)
++		map->m1 &= ~BIT(id - 32);
++#endif
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
++	else if (id < 96)
++		map->m2 &= ~BIT(id - 64);
++#endif
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
++	else if (id < 128)
++		map->m3 &= ~BIT(id - 96);
++#endif
++	else
++		rtw_warn_on(1);
++}
++
++inline void rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map)
++{
++	map->m0 = 0;
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
++	map->m1 = 0;
++#endif
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
++	map->m2 = 0;
++#endif
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
++	map->m3 = 0;
++#endif
++}
++
++inline bool rtw_sec_camid_is_drv_forbid(struct cam_ctl_t *cam_ctl, u8 id)
++{
++	struct sec_cam_bmp forbid_map;
++
++	forbid_map.m0 = 0x00000ff0;
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
++	forbid_map.m1 = 0x00000000;
++#endif
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
++	forbid_map.m2 = 0x00000000;
++#endif
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
++	forbid_map.m3 = 0x00000000;
++#endif
++
++	if (id < 32)
++		return forbid_map.m0 & BIT(id);
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
++	else if (id < 64)
++		return forbid_map.m1 & BIT(id - 32);
++#endif
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
++	else if (id < 96)
++		return forbid_map.m2 & BIT(id - 64);
++#endif
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
++	else if (id < 128)
++		return forbid_map.m3 & BIT(id - 96);
++#endif
++	else
++		rtw_warn_on(1);
++
++	return 1;
++}
++
++bool _rtw_sec_camid_is_used(struct cam_ctl_t *cam_ctl, u8 id)
++{
++	bool ret = _FALSE;
++
++	if (id >= cam_ctl->num) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++#if 0 /* for testing */
++	if (rtw_sec_camid_is_drv_forbid(cam_ctl, id)) {
++		ret = _TRUE;
++		goto exit;
++	}
++#endif
++
++	ret = rtw_sec_camid_is_set(&cam_ctl->used, id);
++
++exit:
++	return ret;
++}
++
++inline bool rtw_sec_camid_is_used(struct cam_ctl_t *cam_ctl, u8 id)
++{
++	_irqL irqL;
++	bool ret;
++
++	_enter_critical_bh(&cam_ctl->lock, &irqL);
++	ret = _rtw_sec_camid_is_used(cam_ctl, id);
++	_exit_critical_bh(&cam_ctl->lock, &irqL);
++
++	return ret;
++}
++u8 rtw_get_sec_camid(_adapter *adapter, u8 max_bk_key_num, u8 *sec_key_id)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	int i;
++	_irqL irqL;
++	u8 sec_cam_num = 0;
++
++	_enter_critical_bh(&cam_ctl->lock, &irqL);
++	for (i = 0; i < cam_ctl->num; i++) {
++		if (_rtw_sec_camid_is_used(cam_ctl, i)) {
++			sec_key_id[sec_cam_num++] = i;
++			if (sec_cam_num == max_bk_key_num)
++				break;
++		}
++	}
++	_exit_critical_bh(&cam_ctl->lock, &irqL);
++
++	return sec_cam_num;
++}
++
++inline bool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	bool ret = _FALSE;
++
++	if (cam_id >= cam_ctl->num) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (_rtw_sec_camid_is_used(cam_ctl, cam_id) == _FALSE)
++		goto exit;
++
++	ret = (dvobj->cam_cache[cam_id].ctrl & BIT6) ? _TRUE : _FALSE;
++
++exit:
++	return ret;
++}
++
++inline bool rtw_camid_is_gk(_adapter *adapter, u8 cam_id)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	_irqL irqL;
++	bool ret;
++
++	_enter_critical_bh(&cam_ctl->lock, &irqL);
++	ret = _rtw_camid_is_gk(adapter, cam_id);
++	_exit_critical_bh(&cam_ctl->lock, &irqL);
++
++	return ret;
++}
++
++bool cam_cache_chk(_adapter *adapter, u8 id, u8 *addr, s16 kid, s8 gk)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	bool ret = _FALSE;
++
++	if (addr && _rtw_memcmp(dvobj->cam_cache[id].mac, addr, ETH_ALEN) == _FALSE)
++		goto exit;
++	if (kid >= 0 && kid != (dvobj->cam_cache[id].ctrl & 0x03))
++		goto exit;
++	if (gk != -1 && (gk ? _TRUE : _FALSE) != _rtw_camid_is_gk(adapter, id))
++		goto exit;
++
++	ret = _TRUE;
++
++exit:
++	return ret;
++}
++
++s16 _rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	int i;
++	s16 cam_id = -1;
++
++	for (i = 0; i < cam_ctl->num; i++) {
++		if (cam_cache_chk(adapter, i, addr, kid, gk)) {
++			cam_id = i;
++			break;
++		}
++	}
++
++	if (0) {
++		if (addr)
++			RTW_INFO(FUNC_ADPT_FMT" addr:"MAC_FMT" kid:%d, gk:%d, return cam_id:%d\n"
++				, FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid, gk, cam_id);
++		else
++			RTW_INFO(FUNC_ADPT_FMT" addr:%p kid:%d, gk:%d, return cam_id:%d\n"
++				, FUNC_ADPT_ARG(adapter), addr, kid, gk, cam_id);
++	}
++
++	return cam_id;
++}
++
++s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	_irqL irqL;
++	s16 cam_id = -1;
++
++	_enter_critical_bh(&cam_ctl->lock, &irqL);
++	cam_id = _rtw_camid_search(adapter, addr, kid, gk);
++	_exit_critical_bh(&cam_ctl->lock, &irqL);
++
++	return cam_id;
++}
++
++s16 rtw_get_camid(_adapter *adapter, u8 *addr, s16 kid, u8 gk, bool ext_sec)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	int i;
++#if 0 /* for testing */
++	static u8 start_id = 0;
++#else
++	u8 start_id = 0;
++#endif
++	s16 cam_id = -1;
++
++	if (addr == NULL) {
++		RTW_PRINT(FUNC_ADPT_FMT" mac_address is NULL\n"
++			  , FUNC_ADPT_ARG(adapter));
++		rtw_warn_on(1);
++		goto _exit;
++	}
++
++	/* find cam entry which has the same addr, kid (, gk bit) */
++	if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC) == _TRUE)
++		i = _rtw_camid_search(adapter, addr, kid, gk);
++	else
++		i = _rtw_camid_search(adapter, addr, kid, -1);
++
++	if (i >= 0) {
++		cam_id = i;
++		goto _exit;
++	}
++
++	for (i = 0; i < cam_ctl->num; i++) {
++		/* bypass default key which is allocated statically */
++#ifdef SEC_DEFAULT_KEY_SEARCH
++		if (((i + start_id) % cam_ctl->num) < 4)
++			continue;
++#endif
++		if (_rtw_sec_camid_is_used(cam_ctl, ((i + start_id) % cam_ctl->num)) == _FALSE) {
++			if (ext_sec) {
++				/* look out continue slot */
++				if (((i + 1) < cam_ctl->num) &&
++					(_rtw_sec_camid_is_used(cam_ctl, (((i + 1) + start_id) % cam_ctl->num)) == _FALSE))
++					break;
++				else
++					continue;
++			} else
++				break;
++		}
++	}
++
++	if (i == cam_ctl->num) {
++		RTW_PRINT(FUNC_ADPT_FMT" %s key with "MAC_FMT" id:%u no room\n"
++			, FUNC_ADPT_ARG(adapter), gk ? "group" : "pairwise", MAC_ARG(addr), kid);
++		rtw_warn_on(1);
++		goto _exit;
++	}
++
++	cam_id = ((i + start_id) % cam_ctl->num);
++	start_id = ((i + start_id + 1) % cam_ctl->num);
++
++_exit:
++	return cam_id;
++}
++
++s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, u8 gk, bool ext_sec, bool *used)
++{
++	struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	_irqL irqL;
++	s16 cam_id = -1;
++
++	*used = _FALSE;
++
++	_enter_critical_bh(&cam_ctl->lock, &irqL);
++
++	if ((((mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE))
++	    && !sta) {
++		/*
++		* 1. non-STA mode WEP key
++		* 2. group TX key
++		*/
++#ifdef SEC_DEFAULT_KEY_SEARCH
++		/* static alloction to default key by key ID when concurrent is not defined */
++		if (kid > 3) {
++			RTW_PRINT(FUNC_ADPT_FMT" group key with invalid key id:%u\n"
++				  , FUNC_ADPT_ARG(adapter), kid);
++			rtw_warn_on(1);
++			goto bitmap_handle;
++		}
++		cam_id = kid;
++#else
++		u8 *addr = adapter_mac_addr(adapter);
++
++		cam_id = rtw_get_camid(adapter, addr, kid, gk, ext_sec);
++		if (1)
++			RTW_PRINT(FUNC_ADPT_FMT" group key with "MAC_FMT" assigned cam_id:%u\n"
++				, FUNC_ADPT_ARG(adapter), MAC_ARG(addr), cam_id);
++#endif
++	} else {
++		/*
++		* 1. STA mode WEP key
++		* 2. STA mode group RX key
++		* 3. sta key (pairwise, group RX)
++		*/
++		u8 *addr = sta ? sta->cmn.mac_addr : NULL;
++
++		if (!sta) {
++			if (!(mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) {
++				/* bypass STA mode group key setting before connected(ex:WEP) because bssid is not ready */
++				goto bitmap_handle;
++			}
++			addr = get_bssid(&adapter->mlmepriv);/*A2*/
++		}
++		cam_id = rtw_get_camid(adapter, addr, kid, gk, ext_sec);
++	}
++
++
++bitmap_handle:
++	if (cam_id >= 0) {
++		*used = _rtw_sec_camid_is_used(cam_ctl, cam_id);
++		rtw_sec_cam_map_set(&cam_ctl->used, cam_id);
++		if (ext_sec)
++			rtw_sec_cam_map_set(&cam_ctl->used, cam_id + 1);
++	}
++
++	_exit_critical_bh(&cam_ctl->lock, &irqL);
++
++	return cam_id;
++}
++
++void rtw_camid_set(_adapter *adapter, u8 cam_id)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	_irqL irqL;
++
++	_enter_critical_bh(&cam_ctl->lock, &irqL);
++
++	if (cam_id < cam_ctl->num)
++		rtw_sec_cam_map_set(&cam_ctl->used, cam_id);
++
++	_exit_critical_bh(&cam_ctl->lock, &irqL);
++}
++
++void rtw_camid_free(_adapter *adapter, u8 cam_id)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	_irqL irqL;
++
++	_enter_critical_bh(&cam_ctl->lock, &irqL);
++
++	if (cam_id < cam_ctl->num)
++		rtw_sec_cam_map_clr(&cam_ctl->used, cam_id);
++
++	_exit_critical_bh(&cam_ctl->lock, &irqL);
++}
++
++/*Must pause TX/RX before use this API*/
++inline void rtw_sec_cam_swap(_adapter *adapter, u8 cam_id_a, u8 cam_id_b)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	struct sec_cam_ent cache_a, cache_b;
++	_irqL irqL;
++	bool cam_a_used, cam_b_used;
++
++	if (1)
++		RTW_INFO(ADPT_FMT" - sec_cam %d,%d swap\n", ADPT_ARG(adapter), cam_id_a, cam_id_b);
++
++	if (cam_id_a == cam_id_b)
++		return;
++
++	rtw_mi_update_ap_bmc_camid(adapter, cam_id_a, cam_id_b);
++
++	/*setp-1. backup org cam_info*/
++	_enter_critical_bh(&cam_ctl->lock, &irqL);
++
++	cam_a_used = _rtw_sec_camid_is_used(cam_ctl, cam_id_a);
++	cam_b_used = _rtw_sec_camid_is_used(cam_ctl, cam_id_b);
++
++	if (cam_a_used)
++		_rtw_memcpy(&cache_a, &dvobj->cam_cache[cam_id_a], sizeof(struct sec_cam_ent));
++
++	if (cam_b_used)
++		_rtw_memcpy(&cache_b, &dvobj->cam_cache[cam_id_b], sizeof(struct sec_cam_ent));
++
++	_exit_critical_bh(&cam_ctl->lock, &irqL);
++
++	/*setp-2. clean cam_info*/
++	if (cam_a_used) {
++		rtw_camid_free(adapter, cam_id_a);
++		clear_cam_entry(adapter, cam_id_a);
++	}
++	if (cam_b_used) {
++		rtw_camid_free(adapter, cam_id_b);
++		clear_cam_entry(adapter, cam_id_b);
++	}
++
++	/*setp-3. set cam_info*/
++	if (cam_a_used) {
++		write_cam(adapter, cam_id_b, cache_a.ctrl, cache_a.mac, cache_a.key);
++		rtw_camid_set(adapter, cam_id_b);
++	}
++
++	if (cam_b_used) {
++		write_cam(adapter, cam_id_a, cache_b.ctrl, cache_b.mac, cache_b.key);
++		rtw_camid_set(adapter, cam_id_a);
++	}
++}
++
++s16 rtw_get_empty_cam_entry(_adapter *adapter, u8 start_camid)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	_irqL irqL;
++	int i;
++	s16 cam_id = -1;
++
++	_enter_critical_bh(&cam_ctl->lock, &irqL);
++	for (i = start_camid; i < cam_ctl->num; i++) {
++		if (_FALSE == _rtw_sec_camid_is_used(cam_ctl, i)) {
++			cam_id = i;
++			break;
++		}
++	}
++	_exit_critical_bh(&cam_ctl->lock, &irqL);
++
++	return cam_id;
++}
++void rtw_clean_dk_section(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);
++	s16 ept_cam_id;
++	int i;
++
++	for (i = 0; i < 4; i++) {
++		if (rtw_sec_camid_is_used(cam_ctl, i)) {
++			ept_cam_id = rtw_get_empty_cam_entry(adapter, 4);
++			if (ept_cam_id > 0)
++				rtw_sec_cam_swap(adapter, i, ept_cam_id);
++		}
++	}
++}
++void rtw_clean_hw_dk_cam(_adapter *adapter)
++{
++	int i;
++
++	for (i = 0; i < 4; i++)
++		rtw_sec_clr_cam_ent(adapter, i);
++		/*_clear_cam_entry(adapter, i);*/
++}
++
++void flush_all_cam_entry(_adapter *padapter)
++{
++#ifdef CONFIG_CONCURRENT_MODE
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
++		struct sta_priv	*pstapriv = &padapter->stapriv;
++		struct sta_info		*psta;
++
++		psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
++		if (psta) {
++			if (psta->state & WIFI_AP_STATE) {
++				/*clear cam when ap free per sta_info*/
++			} else
++				rtw_clearstakey_cmd(padapter, psta, _FALSE);
++		}
++	} else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
++#ifndef SEC_DEFAULT_KEY_SEARCH
++		int cam_id = -1;
++		u8 *addr = adapter_mac_addr(padapter);
++		u8 bmc_id = rtw_iface_bcmc_id_get(padapter);
++
++		while ((cam_id = rtw_camid_search(padapter, addr, -1, -1)) >= 0) {
++			RTW_PRINT("clear wep or group key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(addr), cam_id);
++			clear_cam_entry(padapter, cam_id);
++			/* clear cam_ctl.used bit for data BMC TX force camid in rtw_release_macid() */
++			if (bmc_id == INVALID_SEC_MAC_CAM_ID || cam_id != bmc_id)
++				rtw_camid_free(padapter, cam_id);
++		}
++#else
++		/* clear default key */
++		int i, cam_id;
++		u8 null_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
++
++		for (i = 0; i < 4; i++) {
++			cam_id = rtw_camid_search(padapter, null_addr, i, -1);
++			if (cam_id >= 0) {
++				clear_cam_entry(padapter, cam_id);
++				rtw_camid_free(padapter, cam_id);
++			}
++		}
++		/* clear default key related key search setting */
++		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8 *)_FALSE);
++#endif
++	}
++
++#else /*NON CONFIG_CONCURRENT_MODE*/
++
++	invalidate_cam_all(padapter);
++#endif
++}
++
++#if defined(CONFIG_P2P) && defined(CONFIG_WFD)
++void rtw_process_wfd_ie(_adapter *adapter, u8 *wfd_ie, u8 wfd_ielen, const char *tag)
++{
++	struct wifidirect_info *wdinfo = &adapter->wdinfo;
++
++	u8 *attr_content;
++	u32 attr_contentlen = 0;
++
++	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
++		return;
++
++	RTW_INFO("[%s] Found WFD IE\n", tag);
++	attr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen);
++	if (attr_content && attr_contentlen) {
++		wdinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16(attr_content + 2);
++		RTW_INFO("[%s] Peer PORT NUM = %d\n", tag, wdinfo->wfd_info->peer_rtsp_ctrlport);
++	}
++}
++
++void rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag)
++{
++	u8 *wfd_ie;
++	u32	wfd_ielen;
++
++	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
++		return;
++
++	wfd_ie = rtw_get_wfd_ie(ies, ies_len, NULL, &wfd_ielen);
++	while (wfd_ie) {
++		rtw_process_wfd_ie(adapter, wfd_ie, wfd_ielen, tag);
++		wfd_ie = rtw_get_wfd_ie(wfd_ie + wfd_ielen, (ies + ies_len) - (wfd_ie + wfd_ielen), NULL, &wfd_ielen);
++	}
++}
++#endif /* defined(CONFIG_P2P) && defined(CONFIG_WFD) */
++
++int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs	pIE)
++{
++	/* struct registry_priv	*pregpriv = &padapter->registrypriv; */
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	if (pmlmepriv->qospriv.qos_option == 0) {
++		pmlmeinfo->WMM_enable = 0;
++		return _FALSE;
++	}
++
++	if (_rtw_memcmp(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element)))
++		return _FALSE;
++	else
++		_rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element));
++	pmlmeinfo->WMM_enable = 1;
++	return _TRUE;
++
++#if 0
++	if (pregpriv->wifi_spec == 1) {
++		if (pmlmeinfo->WMM_enable == 1) {
++			/* todo: compare the parameter set count & decide wheher to update or not */
++			return _FAIL;
++		} else {
++			pmlmeinfo->WMM_enable = 1;
++			_rtw_rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element));
++			return _TRUE;
++		}
++	} else {
++		pmlmeinfo->WMM_enable = 0;
++		return _FAIL;
++	}
++#endif
++
++}
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++u8 rtw_is_tbtx_capabilty(u8 *p, u8 len){
++	int i;
++	u8 tbtx_cap_ie[8] = {0x00, 0xe0, 0x4c, 0x01, 0x00, 0x00, 0x00, 0x00};
++
++	for (i = 0; i < len; i++) {
++		if (*(p + i) != tbtx_cap_ie[i]) 
++			return _FALSE;
++		else
++			continue;
++	}
++	return _TRUE;
++}
++#endif
++
++void WMMOnAssocRsp(_adapter *padapter)
++{
++	u8	ACI, ACM, AIFS, ECWMin, ECWMax, aSifsTime;
++	u8	acm_mask;
++	u16	TXOP;
++	u32	acParm, i;
++	u32	edca[4], inx[4];
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct xmit_priv		*pxmitpriv = &padapter->xmitpriv;
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++#ifdef CONFIG_WMMPS_STA
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	struct qos_priv	*pqospriv = &pmlmepriv->qospriv;
++#endif /* CONFIG_WMMPS_STA */	
++
++	acm_mask = 0;
++
++	if (is_supported_5g(pmlmeext->cur_wireless_mode) ||
++	    (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
++		aSifsTime = 16;
++	else
++		aSifsTime = 10;
++
++	if (pmlmeinfo->WMM_enable == 0) {
++		padapter->mlmepriv.acm_mask = 0;
++
++		AIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
++
++		if (pmlmeext->cur_wireless_mode & (WIRELESS_11G | WIRELESS_11A)) {
++			ECWMin = 4;
++			ECWMax = 10;
++		} else if (pmlmeext->cur_wireless_mode & WIRELESS_11B) {
++			ECWMin = 5;
++			ECWMax = 10;
++		} else {
++			ECWMin = 4;
++			ECWMax = 10;
++		}
++
++		TXOP = 0;
++		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));
++
++		ECWMin = 2;
++		ECWMax = 3;
++		TXOP = 0x2f;
++		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
++		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));
++	} else {
++		edca[0] = edca[1] = edca[2] = edca[3] = 0;
++
++		for (i = 0; i < 4; i++) {
++			ACI = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 5) & 0x03;
++			ACM = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 4) & 0x01;
++
++			/* AIFS = AIFSN * slot time + SIFS - r2t phy delay */
++			AIFS = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN & 0x0f) * pmlmeinfo->slotTime + aSifsTime;
++
++			ECWMin = (pmlmeinfo->WMM_param.ac_param[i].CW & 0x0f);
++			ECWMax = (pmlmeinfo->WMM_param.ac_param[i].CW & 0xf0) >> 4;
++			TXOP = le16_to_cpu(pmlmeinfo->WMM_param.ac_param[i].TXOP_limit);
++
++			acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
++
++			switch (ACI) {
++			case 0x0:
++				rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));
++				acm_mask |= (ACM ? BIT(1) : 0);
++				edca[XMIT_BE_QUEUE] = acParm;
++				break;
++
++			case 0x1:
++				rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));
++				/* acm_mask |= (ACM? BIT(0):0); */
++				edca[XMIT_BK_QUEUE] = acParm;
++				break;
++
++			case 0x2:
++				rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));
++				acm_mask |= (ACM ? BIT(2) : 0);
++				edca[XMIT_VI_QUEUE] = acParm;
++				break;
++
++			case 0x3:
++				rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));
++				acm_mask |= (ACM ? BIT(3) : 0);
++				edca[XMIT_VO_QUEUE] = acParm;
++				break;
++			}
++
++			RTW_INFO("WMM(%x): %x, %x\n", ACI, ACM, acParm);
++		}
++
++		if (padapter->registrypriv.acm_method == 1)
++			rtw_hal_set_hwreg(padapter, HW_VAR_ACM_CTRL, (u8 *)(&acm_mask));
++		else
++			padapter->mlmepriv.acm_mask = acm_mask;
++
++		inx[0] = 0;
++		inx[1] = 1;
++		inx[2] = 2;
++		inx[3] = 3;
++
++		if (pregpriv->wifi_spec == 1) {
++			u32	j, tmp, change_inx = _FALSE;
++
++			/* entry indx: 0->vo, 1->vi, 2->be, 3->bk. */
++			for (i = 0; i < 4; i++) {
++				for (j = i + 1; j < 4; j++) {
++					/* compare CW and AIFS */
++					if ((edca[j] & 0xFFFF) < (edca[i] & 0xFFFF))
++						change_inx = _TRUE;
++					else if ((edca[j] & 0xFFFF) == (edca[i] & 0xFFFF)) {
++						/* compare TXOP */
++						if ((edca[j] >> 16) > (edca[i] >> 16))
++							change_inx = _TRUE;
++					}
++
++					if (change_inx) {
++						tmp = edca[i];
++						edca[i] = edca[j];
++						edca[j] = tmp;
++
++						tmp = inx[i];
++						inx[i] = inx[j];
++						inx[j] = tmp;
++
++						change_inx = _FALSE;
++					}
++				}
++			}
++		}
++
++		for (i = 0; i < 4; i++) {
++			pxmitpriv->wmm_para_seq[i] = inx[i];
++			RTW_INFO("wmm_para_seq(%d): %d\n", i, pxmitpriv->wmm_para_seq[i]);
++		}
++		
++#ifdef CONFIG_WMMPS_STA
++		/* if AP supports UAPSD function, driver must set each uapsd TID to coresponding mac register 0x693 */
++		if (pmlmeinfo->WMM_param.QoS_info & AP_SUPPORTED_UAPSD) {
++			pqospriv->uapsd_ap_supported = 1;
++			rtw_hal_set_hwreg(padapter, HW_VAR_UAPSD_TID, NULL);
++		}
++#endif /* CONFIG_WMMPS_STA */
++	}
++}
++
++static void bwmode_update_check(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++#ifdef CONFIG_80211N_HT
++	unsigned char	 new_bwmode;
++	unsigned char  new_ch_offset;
++	struct HT_info_element	*pHT_info;
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++	struct ht_priv			*phtpriv = &pmlmepriv->htpriv;
++	u8	cbw40_enable = 0;
++
++	if (!pIE)
++		return;
++
++	if (phtpriv->ht_option == _FALSE)
++		return;
++
++	if (pmlmeext->cur_bwmode >= CHANNEL_WIDTH_80)
++		return;
++
++	if (pIE->Length > sizeof(struct HT_info_element))
++		return;
++
++	pHT_info = (struct HT_info_element *)pIE->data;
++
++	if (hal_chk_bw_cap(padapter, BW_CAP_40M)) {
++		if (pmlmeext->cur_channel > 14) {
++			if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
++				cbw40_enable = 1;
++		} else {
++			if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
++				cbw40_enable = 1;
++		}
++	}
++
++	if ((pHT_info->infos[0] & BIT(2)) && cbw40_enable) {
++		new_bwmode = CHANNEL_WIDTH_40;
++
++		switch (pHT_info->infos[0] & 0x3) {
++		case 1:
++			new_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++			break;
++
++		case 3:
++			new_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++			break;
++
++		default:
++			new_bwmode = CHANNEL_WIDTH_20;
++			new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++			break;
++		}
++	} else {
++		new_bwmode = CHANNEL_WIDTH_20;
++		new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++	}
++
++
++	if ((new_bwmode != pmlmeext->cur_bwmode || new_ch_offset != pmlmeext->cur_ch_offset)
++	    && new_bwmode < pmlmeext->cur_bwmode
++	   ) {
++		pmlmeinfo->bwmode_updated = _TRUE;
++
++		pmlmeext->cur_bwmode = new_bwmode;
++		pmlmeext->cur_ch_offset = new_ch_offset;
++
++		/* update HT info also */
++		HT_info_handler(padapter, pIE);
++	} else
++		pmlmeinfo->bwmode_updated = _FALSE;
++
++
++	if (_TRUE == pmlmeinfo->bwmode_updated) {
++		struct sta_info *psta;
++		WLAN_BSSID_EX	*cur_network = &(pmlmeinfo->network);
++		struct sta_priv	*pstapriv = &padapter->stapriv;
++
++		/* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */
++
++
++		/* update ap's stainfo */
++		psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
++		if (psta) {
++			struct ht_priv	*phtpriv_sta = &psta->htpriv;
++
++			if (phtpriv_sta->ht_option) {
++				/* bwmode				 */
++				psta->cmn.bw_mode = pmlmeext->cur_bwmode;
++				phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset;
++			} else {
++				psta->cmn.bw_mode = CHANNEL_WIDTH_20;
++				phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++			}
++
++			rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta);
++		}
++
++		/* pmlmeinfo->bwmode_updated = _FALSE; */ /* bwmode_updated done, reset it! */
++	}
++#endif /* CONFIG_80211N_HT */
++}
++
++#ifdef ROKU_PRIVATE
++void Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++	unsigned int	i;
++	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info		*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	if (pIE == NULL)
++		return;
++
++	for (i = 0 ; i < pIE->Length; i++)
++		pmlmeinfo->SupportedRates_infra_ap[i] = (pIE->data[i]);
++
++}
++
++void Extended_Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++	unsigned int i, j;
++	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info		*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	if (pIE == NULL)
++		return;
++
++	if (pIE->Length > 0) {
++		for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
++			if (pmlmeinfo->SupportedRates_infra_ap[i] == 0)
++				break;
++		}
++		for (j = 0; j < pIE->Length; j++)
++			pmlmeinfo->SupportedRates_infra_ap[i+j] = (pIE->data[j]);
++	}
++
++}
++
++void HT_get_ss_from_mcs_set(u8 *mcs_set, u8 *Rx_ss)
++{
++	u8 i, j;
++	u8 r_ss = 0, t_ss = 0;
++
++	for (i = 0; i < 4; i++) {
++		if ((mcs_set[3-i] & 0xff) != 0x00) {
++			r_ss = 4-i;
++			break;
++		}
++	}
++
++	*Rx_ss = r_ss;
++}
++
++void HT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++	unsigned int	i;
++	u8	cur_stbc_cap_infra_ap = 0;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct ht_priv_infra_ap		*phtpriv = &pmlmepriv->htpriv_infra_ap;
++
++	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info		*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	if (pIE == NULL)
++		return;
++
++	pmlmeinfo->ht_vht_received |= BIT(0);
++
++	/*copy MCS_SET*/
++	for (i = 3; i < 19; i++)
++		phtpriv->MCS_set_infra_ap[i-3] = (pIE->data[i]);
++
++	/*get number of stream from mcs set*/
++	HT_get_ss_from_mcs_set(phtpriv->MCS_set_infra_ap, &phtpriv->Rx_ss_infra_ap);
++
++	phtpriv->rx_highest_data_rate_infra_ap = le16_to_cpu(GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(pIE->data));
++
++	phtpriv->ldpc_cap_infra_ap = GET_HT_CAP_ELE_LDPC_CAP(pIE->data);
++
++	if (GET_HT_CAP_ELE_RX_STBC(pIE->data))
++		SET_FLAG(cur_stbc_cap_infra_ap, STBC_HT_ENABLE_RX);
++	if (GET_HT_CAP_ELE_TX_STBC(pIE->data))
++		SET_FLAG(cur_stbc_cap_infra_ap, STBC_HT_ENABLE_TX);
++	phtpriv->stbc_cap_infra_ap = cur_stbc_cap_infra_ap;
++
++	/*store ap info SGI 20m 40m*/
++	phtpriv->sgi_20m_infra_ap = GET_HT_CAP_ELE_SHORT_GI20M(pIE->data);
++	phtpriv->sgi_40m_infra_ap = GET_HT_CAP_ELE_SHORT_GI40M(pIE->data);
++
++	/*store ap info for supported channel bandwidth*/
++	phtpriv->channel_width_infra_ap = GET_HT_CAP_ELE_CHL_WIDTH(pIE->data);
++}
++#endif /* ROKU_PRIVATE */
++
++void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++#ifdef CONFIG_80211N_HT
++	unsigned int	i;
++	u8	max_AMPDU_len, min_MPDU_spacing;
++	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0, rx_nss = 0;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct ht_priv			*phtpriv = &pmlmepriv->htpriv;
++#ifdef CONFIG_DISABLE_MCS13TO15
++	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
++#endif
++
++	if (pIE == NULL)
++		return;
++
++	if (phtpriv->ht_option == _FALSE)
++		return;
++
++	pmlmeinfo->HT_caps_enable = 1;
++
++	for (i = 0; i < (pIE->Length); i++) {
++		if (i != 2) {
++			/*	Commented by Albert 2010/07/12 */
++			/*	Got the endian issue here. */
++			pmlmeinfo->HT_caps.u.HT_cap[i] &= (pIE->data[i]);
++		} else {
++			/* AMPDU Parameters field */
++
++			/* Get MIN of MAX AMPDU Length Exp */
++			if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3) > (pIE->data[i] & 0x3))
++				max_AMPDU_len = (pIE->data[i] & 0x3);
++			else
++				max_AMPDU_len = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3);
++
++			/* Get MAX of MIN MPDU Start Spacing */
++			if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) > (pIE->data[i] & 0x1c))
++				min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c);
++			else
++				min_MPDU_spacing = (pIE->data[i] & 0x1c);
++
++			pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para = max_AMPDU_len | min_MPDU_spacing;
++		}
++	}
++
++	/*	Commented by Albert 2010/07/12 */
++	/*	Have to handle the endian issue after copying. */
++	/*	HT_ext_caps didn't be used yet.	 */
++	pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info);
++	pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps);
++
++	/* update the MCS set */
++	for (i = 0; i < 16; i++)
++		pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i];
++
++	rx_nss = GET_HAL_RX_NSS(padapter);
++
++	switch (rx_nss) {
++	case 1:
++		set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R);
++		break;
++	case 2:
++		#ifdef CONFIG_DISABLE_MCS13TO15
++		if (pmlmeext->cur_bwmode == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1)
++			set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R_13TO15_OFF);
++		else
++		#endif
++			set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R);
++		break;
++	case 3:
++		set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R);
++		break;
++	case 4:
++		set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_4R);
++		break;
++	default:
++		RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", GET_HAL_RFPATH(padapter), rx_nss);
++	}
++
++	if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
++		/* Config STBC setting */
++		if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(pIE->data)) {
++			SET_FLAG(cur_stbc_cap, STBC_HT_ENABLE_TX);
++			RTW_INFO("Enable HT Tx STBC !\n");
++		}
++		phtpriv->stbc_cap = cur_stbc_cap;
++
++#ifdef CONFIG_BEAMFORMING
++		/* Config Tx beamforming setting */
++		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
++		    GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) {
++			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
++			/* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/
++			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6);
++		}
++
++		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
++		    GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) {
++			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
++			/* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/
++			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4);
++		}
++		phtpriv->beamform_cap = cur_beamform_cap;
++		if (cur_beamform_cap)
++			RTW_INFO("AP HT Beamforming Cap = 0x%02X\n", cur_beamform_cap);
++#endif /*CONFIG_BEAMFORMING*/
++	} else {
++		/*WIFI_STATION_STATEorI_ADHOC_STATE or WIFI_ADHOC_MASTER_STATE*/
++		/* Config LDPC Coding Capability */
++		if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX) && GET_HT_CAP_ELE_LDPC_CAP(pIE->data)) {
++			SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX));
++			RTW_INFO("Enable HT Tx LDPC!\n");
++		}
++		phtpriv->ldpc_cap = cur_ldpc_cap;
++
++		/* Config STBC setting */
++		if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(pIE->data)) {
++			SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX));
++			RTW_INFO("Enable HT Tx STBC!\n");
++		}
++		phtpriv->stbc_cap = cur_stbc_cap;
++
++#ifdef CONFIG_BEAMFORMING
++#ifdef RTW_BEAMFORMING_VERSION_2
++		/* Config beamforming setting */
++		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
++		    GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) {
++			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
++			/* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/
++			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6);
++		}
++
++		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
++		    GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) {
++			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
++			/* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/
++			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4);
++		}
++#else /* !RTW_BEAMFORMING_VERSION_2 */
++		/* Config Tx beamforming setting */
++		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
++		    GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) {
++			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
++			/* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/
++			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6);
++		}
++
++		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
++		    GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) {
++			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
++			/* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/
++			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4);
++		}
++#endif /* !RTW_BEAMFORMING_VERSION_2 */
++		phtpriv->beamform_cap = cur_beamform_cap;
++		if (cur_beamform_cap)
++			RTW_INFO("Client HT Beamforming Cap = 0x%02X\n", cur_beamform_cap);
++#endif /*CONFIG_BEAMFORMING*/
++	}
++
++#endif /* CONFIG_80211N_HT */
++}
++
++void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++#ifdef CONFIG_80211N_HT
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct ht_priv			*phtpriv = &pmlmepriv->htpriv;
++
++	if (pIE == NULL)
++		return;
++
++	if (phtpriv->ht_option == _FALSE)
++		return;
++
++
++	if (pIE->Length > sizeof(struct HT_info_element))
++		return;
++
++	pmlmeinfo->HT_info_enable = 1;
++	_rtw_memcpy(&(pmlmeinfo->HT_info), pIE->data, pIE->Length);
++#endif /* CONFIG_80211N_HT */
++	return;
++}
++
++void HTOnAssocRsp(_adapter *padapter)
++{
++	unsigned char		max_AMPDU_len;
++	unsigned char		min_MPDU_spacing;
++	/* struct registry_priv	 *pregpriv = &padapter->registrypriv; */
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable))
++		pmlmeinfo->HT_enable = 1;
++	else {
++		pmlmeinfo->HT_enable = 0;
++		/* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */
++		return;
++	}
++
++	/* handle A-MPDU parameter field */
++	/*
++		AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k
++		AMPDU_para [4:2]:Min MPDU Start Spacing
++	*/
++	max_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
++
++	min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2;
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing));
++#ifdef CONFIG_80211N_HT
++	rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len));
++#endif /* CONFIG_80211N_HT */
++#if 0 /* move to rtw_update_ht_cap() */
++	if ((pregpriv->bw_mode > 0) &&
++	    (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) &&
++	    (pmlmeinfo->HT_info.infos[0] & BIT(2))) {
++		/* switch to the 40M Hz mode accoring to the AP */
++		pmlmeext->cur_bwmode = CHANNEL_WIDTH_40;
++		switch ((pmlmeinfo->HT_info.infos[0] & 0x3)) {
++		case EXTCHNL_OFFSET_UPPER:
++			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++			break;
++
++		case EXTCHNL_OFFSET_LOWER:
++			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++			break;
++
++		default:
++			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++			break;
++		}
++	}
++#endif
++
++	/* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */
++
++#if 0 /* move to rtw_update_ht_cap() */
++	/*  */
++	/* Config SM Power Save setting */
++	/*  */
++	pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2;
++	if (pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) {
++#if 0
++		u8 i;
++		/* update the MCS rates */
++		for (i = 0; i < 16; i++)
++			pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
++#endif
++		RTW_INFO("%s(): WLAN_HT_CAP_SM_PS_STATIC\n", __FUNCTION__);
++	}
++
++	/*  */
++	/* Config current HT Protection mode. */
++	/*  */
++	pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3;
++#endif
++
++}
++
++void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	if (pIE->Length > 1)
++		return;
++
++	pmlmeinfo->ERP_enable = 1;
++	_rtw_memcpy(&(pmlmeinfo->ERP_IE), pIE->data, pIE->Length);
++}
++
++void VCS_update(_adapter *padapter, struct sta_info *psta)
++{
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	switch (pregpriv->vrtl_carrier_sense) { /* 0:off 1:on 2:auto */
++	case 0: /* off */
++		psta->rtsen = 0;
++		psta->cts2self = 0;
++		break;
++
++	case 1: /* on */
++		if (pregpriv->vcs_type == 1) { /* 1:RTS/CTS 2:CTS to self */
++			psta->rtsen = 1;
++			psta->cts2self = 0;
++		} else {
++			psta->rtsen = 0;
++			psta->cts2self = 1;
++		}
++		break;
++
++	case 2: /* auto */
++	default:
++		if (((pmlmeinfo->ERP_enable) && (pmlmeinfo->ERP_IE & BIT(1)))
++			/*||(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/
++		) {
++			if (pregpriv->vcs_type == 1) {
++				psta->rtsen = 1;
++				psta->cts2self = 0;
++			} else {
++				psta->rtsen = 0;
++				psta->cts2self = 1;
++			}
++		} else {
++			psta->rtsen = 0;
++			psta->cts2self = 0;
++		}
++		break;
++	}
++}
++
++void	update_ldpc_stbc_cap(struct sta_info *psta)
++{
++#ifdef CONFIG_80211N_HT
++
++#ifdef CONFIG_80211AC_VHT
++	if (psta->vhtpriv.vht_option) {
++		if (TEST_FLAG(psta->vhtpriv.ldpc_cap, LDPC_VHT_ENABLE_TX))
++			psta->cmn.ldpc_en = VHT_LDPC_EN;
++		else
++			psta->cmn.ldpc_en = 0;
++
++		if (TEST_FLAG(psta->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX))
++			psta->cmn.stbc_en = VHT_STBC_EN;
++		else
++			psta->cmn.stbc_en = 0;
++	} else
++#endif /* CONFIG_80211AC_VHT */
++		if (psta->htpriv.ht_option) {
++			if (TEST_FLAG(psta->htpriv.ldpc_cap, LDPC_HT_ENABLE_TX))
++				psta->cmn.ldpc_en = HT_LDPC_EN;
++			else
++				psta->cmn.ldpc_en = 0;
++
++			if (TEST_FLAG(psta->htpriv.stbc_cap, STBC_HT_ENABLE_TX))
++				psta->cmn.stbc_en = HT_STBC_EN;
++			else
++				psta->cmn.stbc_en = 0;
++		} else {
++			psta->cmn.ldpc_en = 0;
++			psta->cmn.stbc_en = 0;
++		}
++
++#endif /* CONFIG_80211N_HT */
++}
++
++int check_ielen(u8 *start, uint len)
++{
++	int left = len;
++	u8 *pos = start;
++	u8 id, elen;
++
++	while (left >= 2) {
++		id = *pos++;
++		elen = *pos++;
++		left -= 2;
++
++		if (elen > left) {
++			RTW_INFO("IEEE 802.11 element parse failed (id=%d elen=%d left=%lu)\n",
++					id, elen, (unsigned long) left);
++			return _FALSE;
++		}
++		if ((id == WLAN_EID_VENDOR_SPECIFIC) && (elen < 3))
++				return _FALSE;
++
++		left -= elen;
++		pos += elen;
++	}
++	if (left)
++		return _FALSE;
++
++	return _TRUE;
++}
++
++int validate_beacon_len(u8 *pframe, u32 len)
++{
++	u8 ie_offset = _BEACON_IE_OFFSET_ + sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	if (len < ie_offset) {
++		RTW_INFO("%s: incorrect beacon length(%d)\n", __func__, len);
++		return _FALSE;
++	}
++
++	if (check_ielen(pframe + ie_offset, len - ie_offset) == _FALSE)
++		return _FALSE;
++
++	return _TRUE;
++}
++
++
++u8 support_rate_ranges[] = {
++	IEEE80211_CCK_RATE_1MB,
++	IEEE80211_CCK_RATE_2MB,
++	IEEE80211_CCK_RATE_5MB,
++	IEEE80211_CCK_RATE_11MB,
++	IEEE80211_OFDM_RATE_6MB,
++	IEEE80211_OFDM_RATE_9MB,
++	IEEE80211_OFDM_RATE_12MB,
++	IEEE80211_OFDM_RATE_18MB,
++	IEEE80211_PBCC_RATE_22MB,
++	IEEE80211_FREAK_RATE_22_5MB,
++	IEEE80211_OFDM_RATE_24MB,
++	IEEE80211_OFDM_RATE_36MB,
++	IEEE80211_OFDM_RATE_48MB,
++	IEEE80211_OFDM_RATE_54MB,
++};
++
++inline bool match_ranges(u16 EID, u32 value)
++{
++	int i;
++	int nr_range;
++
++	switch (EID) {
++	case _EXT_SUPPORTEDRATES_IE_:
++	case _SUPPORTEDRATES_IE_:
++		nr_range = sizeof(support_rate_ranges)/sizeof(u8);
++		for (i = 0; i < nr_range; i++) {
++			/*	clear bit7 before searching.	*/
++			value &= ~BIT(7);
++			if (value == support_rate_ranges[i])
++				return _TRUE;
++		}
++		break;
++	default:
++		break;
++	};
++	return _FALSE;
++}
++
++/*
++ * rtw_validate_value: validate the IE contain.
++ *
++ *	Input : 
++ *		EID : Element ID
++ *		p	: IE buffer (without EID & length)
++ *		len	: IE length
++ *	return: 
++ * 		_TRUE	: All Values are validated.
++ *		_FALSE	: At least one value is NOT validated.
++ */
++bool rtw_validate_value(u16 EID, u8 *p, u16 len)
++{
++	u8 rate;
++	u32 i, nr_val;
++
++	switch (EID) {
++	case _EXT_SUPPORTEDRATES_IE_:
++	case _SUPPORTEDRATES_IE_:
++		nr_val = len;
++		for (i=0; i<nr_val; i++) {
++			rate = *(p+i);
++			if (match_ranges(EID, rate) == _FALSE)
++				return _FALSE;
++		}
++		break;
++	default:
++		break;
++	};
++	return _TRUE;
++}
++
++bool is_hidden_ssid(char *ssid, int len)
++{
++	return len == 0 || is_all_null(ssid, len) == _TRUE;
++}
++
++inline bool hidden_ssid_ap(WLAN_BSSID_EX *snetwork)
++{
++	return is_hidden_ssid(snetwork->Ssid.Ssid, snetwork->Ssid.SsidLength);
++}
++
++/*
++	Get SSID if this ilegal frame(probe resp) comes from a hidden SSID AP.
++	Update the SSID to the corresponding pnetwork in scan queue.
++*/
++void rtw_absorb_ssid_ifneed(_adapter *padapter, WLAN_BSSID_EX *bssid, u8 *pframe)
++{
++	struct wlan_network *scanned = NULL;
++	WLAN_BSSID_EX	*snetwork;
++	u8 ie_offset, *p=NULL, *next_ie=NULL, *mac = get_addr2_ptr(pframe);
++	sint ssid_len_ori;
++	u32 remain_len = 0;
++	u8 backupIE[MAX_IE_SZ];
++	u16 subtype = get_frame_sub_type(pframe);
++	_irqL irqL;
++
++	if (subtype == WIFI_BEACON) {
++		bssid->Reserved[0] = BSS_TYPE_BCN;
++		ie_offset = _BEACON_IE_OFFSET_;
++	} else {
++		/* FIXME : more type */
++		if (subtype == WIFI_PROBERSP) {
++			ie_offset = _PROBERSP_IE_OFFSET_;
++			bssid->Reserved[0] = BSS_TYPE_PROB_RSP;
++		} else if (subtype == WIFI_PROBEREQ) {
++			ie_offset = _PROBEREQ_IE_OFFSET_;
++			bssid->Reserved[0] = BSS_TYPE_PROB_REQ;
++		} else {
++			bssid->Reserved[0] = BSS_TYPE_UNDEF;
++			ie_offset = _FIXED_IE_LENGTH_;
++		}
++	}
++	
++	_enter_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL);
++	scanned = _rtw_find_network(&padapter->mlmepriv.scanned_queue, mac);
++	if (!scanned) {
++		_exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL);
++		return;
++	}
++
++	snetwork = &(scanned->network);
++	/* scan queue records as Hidden SSID && Input frame is NOT Hidden SSID	*/
++	if (hidden_ssid_ap(snetwork) && !hidden_ssid_ap(bssid)) {
++		p = rtw_get_ie(snetwork->IEs+ie_offset, _SSID_IE_, &ssid_len_ori, snetwork->IELength-ie_offset);
++		if (!p) {
++			_exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL);
++			return;
++		}
++		next_ie = p + 2 + ssid_len_ori;
++		remain_len = snetwork->IELength - (next_ie - snetwork->IEs);
++		scanned->network.Ssid.SsidLength = bssid->Ssid.SsidLength;
++		_rtw_memcpy(scanned->network.Ssid.Ssid, bssid->Ssid.Ssid, bssid->Ssid.SsidLength);
++
++		//update pnetwork->ssid, pnetwork->ssidlen
++		_rtw_memcpy(backupIE, next_ie, remain_len);
++		*(p+1) = bssid->Ssid.SsidLength;
++		_rtw_memcpy(p+2, bssid->Ssid.Ssid, bssid->Ssid.SsidLength);
++		_rtw_memcpy(p+2+bssid->Ssid.SsidLength, backupIE, remain_len);
++		snetwork->IELength += bssid->Ssid.SsidLength;
++	}
++	_exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL);
++}
++
++#ifdef DBG_RX_BCN
++void rtw_debug_rx_bcn(_adapter *adapter, u8 *pframe, u32 packet_len)
++{
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++	struct mlme_ext_info *mlmeinfo = &(pmlmeext->mlmext_info);
++	u16 sn = ((struct rtw_ieee80211_hdr_3addr *)pframe)->seq_ctl >> 4;
++	u64 tsf, tsf_offset;
++	u8 dtim_cnt, dtim_period, tim_bmap, tim_pvbit;
++
++	update_TSF(pmlmeext, pframe, packet_len);
++	tsf = pmlmeext->TSFValue;
++	tsf_offset = rtw_modular64(pmlmeext->TSFValue, (mlmeinfo->bcn_interval * 1024));
++
++	/*get TIM IE*/
++	/*DTIM Count*/
++	dtim_cnt = pmlmeext->tim[0];
++	/*DTIM Period*/
++	dtim_period = pmlmeext->tim[1];
++	/*Bitmap*/
++	tim_bmap = pmlmeext->tim[2];
++	/*Partial VBitmap AID 0 ~ 7*/
++	tim_pvbit = pmlmeext->tim[3];
++
++	RTW_INFO("[BCN] SN-%d, TSF-%lld(us), offset-%lld, bcn_interval-%d DTIM-%d[%d] bitmap-0x%02x-0x%02x\n",
++		sn, tsf, tsf_offset, mlmeinfo->bcn_interval, dtim_period, dtim_cnt, tim_bmap, tim_pvbit);
++}
++#endif
++
++/*
++ * rtw_get_bcn_keys: get beacon keys from recv frame
++ *
++ * TODO:
++ *	WLAN_EID_COUNTRY
++ *	WLAN_EID_ERP_INFO
++ *	WLAN_EID_CHANNEL_SWITCH
++ *	WLAN_EID_PWR_CONSTRAINT
++ */
++int _rtw_get_bcn_keys(u8 *cap_info, u32 buf_len, u8 def_ch, ADAPTER *adapter
++	, struct beacon_keys *recv_beacon)
++{
++	int left;
++	u16 capability;
++	unsigned char *pos;
++	struct rtw_ieee802_11_elems elems;
++
++	_rtw_memset(recv_beacon, 0, sizeof(*recv_beacon));
++
++	/* checking capabilities */
++	capability = le16_to_cpu(*(unsigned short *)(cap_info));
++
++	/* checking IEs */
++	left = buf_len - 2;
++	pos = cap_info + 2;
++	if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed)
++		return _FALSE;
++
++	if (elems.ht_capabilities) {
++		if (elems.ht_capabilities_len != 26)
++			return _FALSE;
++	}
++
++	if (elems.ht_operation) {
++		if (elems.ht_operation_len != 22)
++			return _FALSE;
++	}
++
++	if (elems.vht_capabilities) {
++		if (elems.vht_capabilities_len != 12)
++			return _FALSE;
++	}
++
++	if (elems.vht_operation) {
++		if (elems.vht_operation_len != 5)
++			return _FALSE;
++	}
++
++	if (rtw_ies_get_supported_rate(pos, left, recv_beacon->rate_set, &recv_beacon->rate_num) == _FAIL)
++		return _FALSE;
++
++	if (cckratesonly_included(recv_beacon->rate_set, recv_beacon->rate_num) == _TRUE)
++		recv_beacon->proto_cap |= PROTO_CAP_11B;
++	else if (cckrates_included(recv_beacon->rate_set, recv_beacon->rate_num) == _TRUE)
++		recv_beacon->proto_cap |= PROTO_CAP_11B | PROTO_CAP_11G;
++	else
++		recv_beacon->proto_cap |= PROTO_CAP_11G;
++
++	if (elems.ht_capabilities && elems.ht_operation)
++		recv_beacon->proto_cap |= PROTO_CAP_11N;
++
++	if (elems.vht_capabilities && elems.vht_operation)
++		recv_beacon->proto_cap |= PROTO_CAP_11AC;
++
++	/* check bw and channel offset */
++	rtw_ies_get_chbw(pos, left, &recv_beacon->ch, &recv_beacon->bw, &recv_beacon->offset, 1, 1);
++	if (!recv_beacon->ch)
++		recv_beacon->ch = def_ch;
++
++	/* checking SSID */
++	if (elems.ssid) {
++		if (elems.ssid_len > sizeof(recv_beacon->ssid))
++			return _FALSE;
++
++		_rtw_memcpy(recv_beacon->ssid, elems.ssid, elems.ssid_len);
++		recv_beacon->ssid_len = elems.ssid_len;
++	}
++
++	/* checking RSN first */
++	if (elems.rsn_ie && elems.rsn_ie_len) {
++		recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA2;
++		rtw_parse_wpa2_ie(elems.rsn_ie - 2, elems.rsn_ie_len + 2,
++			&recv_beacon->group_cipher, &recv_beacon->pairwise_cipher,
++			NULL, &recv_beacon->akm, NULL);
++	}
++	/* checking WPA secon */
++	else if (elems.wpa_ie && elems.wpa_ie_len) {
++		recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA;
++		rtw_parse_wpa_ie(elems.wpa_ie - 2, elems.wpa_ie_len + 2,
++			&recv_beacon->group_cipher, &recv_beacon->pairwise_cipher,
++				 &recv_beacon->akm);
++	} else if (capability & BIT(4))
++		recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WEP;
++
++	if (adapter) {
++		struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++
++		if (elems.tim && elems.tim_len) {
++			#ifdef DBG_RX_BCN
++			_rtw_memcpy(pmlmeext->tim, elems.tim, 4);
++			#endif
++			pmlmeext->dtim = elems.tim[1];
++		}
++
++		/* checking RTW TBTX */
++		#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++		if (elems.tbtx_cap && elems.tbtx_cap_len) {
++			struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++			if (rtw_is_tbtx_capabilty(elems.tbtx_cap, elems.tbtx_cap_len))
++				RTW_DBG("AP support TBTX\n");
++		}
++		#endif
++	}
++
++	return _TRUE;
++}
++
++int rtw_get_bcn_keys(_adapter *adapter, u8 *whdr, u32 flen, struct beacon_keys *bcn_keys)
++{
++	return _rtw_get_bcn_keys(
++		whdr + WLAN_HDR_A3_LEN + 10
++		, flen - WLAN_HDR_A3_LEN - 10
++		, adapter->mlmeextpriv.cur_channel, adapter
++		, bcn_keys);
++}
++
++int rtw_get_bcn_keys_from_bss(WLAN_BSSID_EX *bss, struct beacon_keys *bcn_keys)
++{
++	return _rtw_get_bcn_keys(
++		bss->IEs + 10
++		, bss->IELength - 10
++		, bss->Configuration.DSConfig, NULL
++		, bcn_keys);
++}
++
++int rtw_update_bcn_keys_of_network(struct wlan_network *network)
++{
++	network->bcn_keys_valid = rtw_get_bcn_keys_from_bss(&network->network, &network->bcn_keys);
++	return network->bcn_keys_valid;
++}
++
++void rtw_dump_bcn_keys(void *sel, struct beacon_keys *recv_beacon)
++{
++	u8 ssid[IW_ESSID_MAX_SIZE + 1];
++
++	_rtw_memcpy(ssid, recv_beacon->ssid, recv_beacon->ssid_len);
++	ssid[recv_beacon->ssid_len] = '\0';
++
++	RTW_PRINT_SEL(sel, "ssid = %s (len = %u)\n", ssid, recv_beacon->ssid_len);
++	RTW_PRINT_SEL(sel, "ch = %u,%u,%u\n"
++		, recv_beacon->ch, recv_beacon->bw, recv_beacon->offset);
++	RTW_PRINT_SEL(sel, "proto_cap = 0x%02x\n", recv_beacon->proto_cap);
++	RTW_MAP_DUMP_SEL(sel, "rate_set = "
++		, recv_beacon->rate_set, recv_beacon->rate_num);
++	RTW_PRINT_SEL(sel, "sec = %d, group = 0x%x, pair = 0x%x, akm = 0x%08x\n"
++		, recv_beacon->encryp_protocol, recv_beacon->group_cipher
++		, recv_beacon->pairwise_cipher, recv_beacon->akm);
++}
++
++bool rtw_bcn_key_compare(struct beacon_keys *cur, struct beacon_keys *recv)
++{
++#define BCNKEY_VERIFY_PROTO_CAP 0
++#define BCNKEY_VERIFY_WHOLE_RATE_SET 0
++
++	struct beacon_keys tmp;
++	bool ret = _FALSE;
++
++	if (!rtw_is_chbw_grouped(cur->ch, cur->bw, cur->offset
++			, recv->ch, recv->bw, recv->offset))
++		goto exit;
++
++	_rtw_memcpy(&tmp, cur, sizeof(tmp));
++
++	/* check fields excluding below */
++	tmp.ch = recv->ch;
++	tmp.bw = recv->bw;
++	tmp.offset = recv->offset;
++	if (!BCNKEY_VERIFY_PROTO_CAP)
++		tmp.proto_cap = recv->proto_cap;
++	if (!BCNKEY_VERIFY_WHOLE_RATE_SET) {
++		tmp.rate_num = recv->rate_num;
++		_rtw_memcpy(tmp.rate_set, recv->rate_set, 12);
++	}
++
++	if (_rtw_memcmp(&tmp, recv, sizeof(*recv)) == _FALSE)
++		goto exit;
++
++	ret = _TRUE;
++
++exit:
++	return ret;
++}
++
++int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len)
++{
++	u8 *pbssid = GetAddr3Ptr(pframe);
++	struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
++	struct wlan_network *cur_network = &(Adapter->mlmepriv.cur_network);
++	struct beacon_keys *cur_beacon = &pmlmepriv->cur_beacon_keys;
++	struct beacon_keys recv_beacon;
++	int ret = 0;
++
++	if (is_client_associated_to_ap(Adapter) == _FALSE)
++		goto exit_success;
++
++	if (rtw_get_bcn_keys(Adapter, pframe, packet_len, &recv_beacon) == _FALSE)
++		goto exit_success; /* parsing failed => broken IE */
++
++#ifdef DBG_RX_BCN
++	rtw_debug_rx_bcn(Adapter, pframe, packet_len);
++#endif
++
++	/* hidden ssid, replace with current beacon ssid directly */
++	if (is_hidden_ssid(recv_beacon.ssid, recv_beacon.ssid_len)) {
++		_rtw_memcpy(recv_beacon.ssid, cur_beacon->ssid, cur_beacon->ssid_len);
++		recv_beacon.ssid_len = cur_beacon->ssid_len;
++	}
++
++#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
++	if (_rtw_memcmp(&recv_beacon, cur_beacon, sizeof(recv_beacon)) == _TRUE)
++		pmlmepriv->new_beacon_cnts = 0;
++	else if ((pmlmepriv->new_beacon_cnts == 0) ||
++		_rtw_memcmp(&recv_beacon, &pmlmepriv->new_beacon_keys, sizeof(recv_beacon)) == _FALSE) {
++		RTW_DBG("%s: start new beacon (seq=%d)\n", __func__, GetSequence(pframe));
++
++		if (pmlmepriv->new_beacon_cnts == 0) {
++			RTW_ERR("%s: cur beacon key\n", __func__);
++			RTW_DBG_EXPR(rtw_dump_bcn_keys(RTW_DBGDUMP, cur_beacon));
++		}
++
++		RTW_DBG("%s: new beacon key\n", __func__);
++		RTW_DBG_EXPR(rtw_dump_bcn_keys(RTW_DBGDUMP, &recv_beacon));
++
++		_rtw_memcpy(&pmlmepriv->new_beacon_keys, &recv_beacon, sizeof(recv_beacon));
++		pmlmepriv->new_beacon_cnts = 1;
++	} else {
++		RTW_DBG("%s: new beacon again (seq=%d)\n", __func__, GetSequence(pframe));
++		pmlmepriv->new_beacon_cnts++;
++	}
++
++	/* if counter >= max, it means beacon is changed really */
++	if (pmlmepriv->new_beacon_cnts >= new_bcn_max)
++#else
++	if (_rtw_memcmp(&recv_beacon, cur_beacon, sizeof(recv_beacon)) == _FALSE)
++#endif
++	{
++		RTW_INFO(FUNC_ADPT_FMT" new beacon occur!!\n", FUNC_ADPT_ARG(Adapter));
++		RTW_INFO(FUNC_ADPT_FMT" cur beacon key:\n", FUNC_ADPT_ARG(Adapter));
++		rtw_dump_bcn_keys(RTW_DBGDUMP, cur_beacon);
++		RTW_INFO(FUNC_ADPT_FMT" new beacon key:\n", FUNC_ADPT_ARG(Adapter));
++		rtw_dump_bcn_keys(RTW_DBGDUMP, &recv_beacon);
++
++		if (rtw_bcn_key_compare(cur_beacon, &recv_beacon) == _FALSE)
++			goto exit;
++
++		_rtw_memcpy(cur_beacon, &recv_beacon, sizeof(recv_beacon));
++		#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
++		pmlmepriv->new_beacon_cnts = 0;
++		#endif
++	}
++
++exit_success:
++	ret = 1;
++
++exit:
++	return ret;
++}
++
++void update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta_info *psta)
++{
++	unsigned int i;
++	unsigned int len;
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++
++#ifdef CONFIG_TDLS
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++	u8 tdls_prohibited[] = { 0x00, 0x00, 0x00, 0x00, 0x10 }; /* bit(38): TDLS_prohibited */
++#endif /* CONFIG_TDLS */
++
++	len = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN);
++
++	for (i = 0; i < len;) {
++		pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i);
++
++		switch (pIE->ElementID) {
++		case _VENDOR_SPECIFIC_IE_:
++			/* to update WMM paramter set while receiving beacon */
++			if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6) && pIE->Length == WLAN_WMM_LEN)	/* WMM */
++				(WMM_param_handler(padapter, pIE)) ? report_wmm_edca_update(padapter) : 0;
++
++			break;
++
++		case _HT_EXTRA_INFO_IE_:	/* HT info */
++			/* HT_info_handler(padapter, pIE); */
++			bwmode_update_check(padapter, pIE);
++			break;
++#ifdef CONFIG_80211AC_VHT
++		case EID_OpModeNotification:
++			rtw_process_vht_op_mode_notify(padapter, pIE->data, psta);
++			break;
++#endif /* CONFIG_80211AC_VHT */
++		case _ERPINFO_IE_:
++			ERP_IE_handler(padapter, pIE);
++			VCS_update(padapter, psta);
++			break;
++
++#ifdef CONFIG_TDLS
++		case _EXT_CAP_IE_:
++			if (check_ap_tdls_prohibited(pIE->data, pIE->Length) == _TRUE)
++				ptdlsinfo->ap_prohibited = _TRUE;
++			if (check_ap_tdls_ch_switching_prohibited(pIE->data, pIE->Length) == _TRUE)
++				ptdlsinfo->ch_switch_prohibited = _TRUE;
++			break;
++#endif /* CONFIG_TDLS */
++		default:
++			break;
++		}
++
++		i += (pIE->Length + 2);
++	}
++}
++
++#if CONFIG_DFS
++void process_csa_ie(_adapter *padapter, u8 *ies, uint ies_len)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	unsigned int i;
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++	u8 ch = 0;
++
++	/* TODO: compare with scheduling CSA */
++	if (rfctl->csa_ch)
++		return;
++
++	for (i = 0; i + 1 < ies_len;) {
++		pIE = (PNDIS_802_11_VARIABLE_IEs)(ies + i);
++
++		switch (pIE->ElementID) {
++		case _CH_SWTICH_ANNOUNCE_:
++			ch = *(pIE->data + 1);
++			break;
++		default:
++			break;
++		}
++
++		i += (pIE->Length + 2);
++	}
++
++	if (ch != 0) {
++		rfctl->csa_ch = ch;
++		if (rtw_set_csa_cmd(padapter) != _SUCCESS)
++			rfctl->csa_ch = 0;
++	}
++}
++#endif /* CONFIG_DFS */
++
++void parsing_eapol_packet(_adapter *padapter, u8 *key_payload, struct sta_info *psta, u8 trx_type)
++{
++	struct security_priv *psecuritypriv = &(padapter->securitypriv);
++	struct ieee802_1x_hdr *hdr;
++	struct wpa_eapol_key *key;
++	u16 key_info, key_data_length;
++	char *trx_msg = trx_type ? "send" : "recv";
++
++	hdr = (struct ieee802_1x_hdr *) key_payload;
++
++	 /* WPS - eapol start packet */
++	if (hdr->type == 1 && hdr->length == 0) {
++		RTW_INFO("%s eapol start packet\n", trx_msg);
++		return;
++	}
++
++	if (hdr->type == 0) { /* WPS - eapol packet */
++		RTW_INFO("%s eapol packet\n", trx_msg);
++		return;
++	}
++
++	key = (struct wpa_eapol_key *) (hdr + 1);
++	key_info = be16_to_cpu(*((u16 *)(key->key_info)));
++	key_data_length = be16_to_cpu(*((u16 *)(key->key_data_length)));
++
++	if (!(key_info & WPA_KEY_INFO_KEY_TYPE)) { /* WPA group key handshake */
++		if (key_info & WPA_KEY_INFO_ACK) {
++			RTW_PRINT("%s eapol packet - WPA Group Key 1/2\n", trx_msg);
++		} else {
++			RTW_PRINT("%s eapol packet - WPA Group Key 2/2\n", trx_msg);
++
++			/* WPA key-handshake has completed */
++			if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPAPSK)
++				psta->state &= (~WIFI_UNDER_KEY_HANDSHAKE);
++		}
++	} else if (key_info & WPA_KEY_INFO_MIC) {
++		if (key_data_length == 0)
++			RTW_PRINT("%s eapol packet 4/4\n", trx_msg);
++		else if (key_info & WPA_KEY_INFO_ACK)
++			RTW_PRINT("%s eapol packet 3/4\n", trx_msg);
++		else
++			RTW_PRINT("%s eapol packet 2/4\n", trx_msg);
++	} else {
++		RTW_PRINT("%s eapol packet 1/4\n", trx_msg);
++	}
++
++}
++
++unsigned int is_ap_in_tkip(_adapter *padapter)
++{
++	u32 i;
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
++
++	if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) {
++		for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) {
++			pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i);
++
++			switch (pIE->ElementID) {
++			case _VENDOR_SPECIFIC_IE_:
++				if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) && (_rtw_memcmp((pIE->data + 12), WPA_TKIP_CIPHER, 4)))
++					return _TRUE;
++				break;
++
++			case _RSN_IE_2_:
++				if (_rtw_memcmp((pIE->data + 8), RSN_TKIP_CIPHER, 4))
++					return _TRUE;
++
++			default:
++				break;
++			}
++
++			i += (pIE->Length + 2);
++		}
++
++		return _FALSE;
++	} else
++		return _FALSE;
++
++}
++
++unsigned int should_forbid_n_rate(_adapter *padapter)
++{
++	u32 i;
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	WLAN_BSSID_EX  *cur_network = &pmlmepriv->cur_network.network;
++
++	if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) {
++		for (i = sizeof(NDIS_802_11_FIXED_IEs); i < cur_network->IELength;) {
++			pIE = (PNDIS_802_11_VARIABLE_IEs)(cur_network->IEs + i);
++
++			switch (pIE->ElementID) {
++			case _VENDOR_SPECIFIC_IE_:
++				if (_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4) &&
++				    ((_rtw_memcmp((pIE->data + 12), WPA_CIPHER_SUITE_CCMP, 4)) ||
++				     (_rtw_memcmp((pIE->data + 16), WPA_CIPHER_SUITE_CCMP, 4))))
++					return _FALSE;
++				break;
++
++			case _RSN_IE_2_:
++				if ((_rtw_memcmp((pIE->data + 8), RSN_CIPHER_SUITE_CCMP, 4))  ||
++				    (_rtw_memcmp((pIE->data + 12), RSN_CIPHER_SUITE_CCMP, 4)))
++					return _FALSE;
++
++			default:
++				break;
++			}
++
++			i += (pIE->Length + 2);
++		}
++
++		return _TRUE;
++	} else
++		return _FALSE;
++
++}
++
++
++unsigned int is_ap_in_wep(_adapter *padapter)
++{
++	u32 i;
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
++
++	if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) {
++		for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) {
++			pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i);
++
++			switch (pIE->ElementID) {
++			case _VENDOR_SPECIFIC_IE_:
++				if (_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4))
++					return _FALSE;
++				break;
++
++			case _RSN_IE_2_:
++				return _FALSE;
++
++			default:
++				break;
++			}
++
++			i += (pIE->Length + 2);
++		}
++
++		return _TRUE;
++	} else
++		return _FALSE;
++
++}
++
++int wifirate2_ratetbl_inx(unsigned char rate);
++int wifirate2_ratetbl_inx(unsigned char rate)
++{
++	int	inx = 0;
++	rate = rate & 0x7f;
++
++	switch (rate) {
++	case 54*2:
++		inx = 11;
++		break;
++
++	case 48*2:
++		inx = 10;
++		break;
++
++	case 36*2:
++		inx = 9;
++		break;
++
++	case 24*2:
++		inx = 8;
++		break;
++
++	case 18*2:
++		inx = 7;
++		break;
++
++	case 12*2:
++		inx = 6;
++		break;
++
++	case 9*2:
++		inx = 5;
++		break;
++
++	case 6*2:
++		inx = 4;
++		break;
++
++	case 11*2:
++		inx = 3;
++		break;
++	case 11:
++		inx = 2;
++		break;
++
++	case 2*2:
++		inx = 1;
++		break;
++
++	case 1*2:
++		inx = 0;
++		break;
++
++	}
++	return inx;
++}
++
++unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz)
++{
++	unsigned int i, num_of_rate;
++	unsigned int mask = 0;
++
++	num_of_rate = (ptn_sz > NumRates) ? NumRates : ptn_sz;
++
++	for (i = 0; i < num_of_rate; i++) {
++		if ((*(ptn + i)) & 0x80)
++			mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i));
++	}
++	return mask;
++}
++
++unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz)
++{
++	unsigned int i, num_of_rate;
++	unsigned int mask = 0;
++
++	num_of_rate = (ptn_sz > NumRates) ? NumRates : ptn_sz;
++
++	for (i = 0; i < num_of_rate; i++)
++		mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i));
++
++	return mask;
++}
++
++int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode)
++{
++	unsigned char					bit_offset;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	if (!(pmlmeinfo->HT_enable))
++		return _FAIL;
++
++	bit_offset = (bwmode & CHANNEL_WIDTH_40) ? 6 : 5;
++
++	if (pHT_caps->u.HT_cap_element.HT_caps_info & (0x1 << bit_offset))
++		return _SUCCESS;
++	else
++		return _FAIL;
++}
++
++unsigned char get_highest_rate_idx(u64 mask)
++{
++	int i;
++	unsigned char rate_idx = 0;
++
++	for (i = 63; i >= 0; i--) {
++		if ((mask >> i) & 0x01) {
++			rate_idx = i;
++			break;
++		}
++	}
++
++	return rate_idx;
++}
++unsigned char get_lowest_rate_idx_ex(u64 mask, int start_bit)
++{
++	int i;
++	unsigned char rate_idx = 0;
++
++	for (i = start_bit; i < 64; i++) {
++		if ((mask >> i) & 0x01) {
++			rate_idx = i;
++			break;
++		}
++	}
++
++	return rate_idx;
++}
++
++void Update_RA_Entry(_adapter *padapter, struct sta_info *psta)
++{
++	rtw_hal_update_ra_mask(psta);
++}
++
++void set_sta_rate(_adapter *padapter, struct sta_info *psta)
++{
++	/* rate adaptive	 */
++	rtw_hal_update_ra_mask(psta);
++}
++
++/* Update RRSR and Rate for USERATE */
++void update_tx_basic_rate(_adapter *padapter, u8 wirelessmode)
++{
++	NDIS_802_11_RATES_EX	supported_rates;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++#ifdef CONFIG_P2P
++	struct wifidirect_info	*pwdinfo = &padapter->wdinfo;
++
++	/*	Added by Albert 2011/03/22 */
++	/*	In the P2P mode, the driver should not support the b mode. */
++	/*	So, the Tx packet shouldn't use the CCK rate */
++	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++		return;
++#endif /* CONFIG_P2P */
++
++	_rtw_memset(supported_rates, 0, NDIS_802_11_LENGTH_RATES_EX);
++
++	/* clear B mod if current channel is in 5G band, avoid tx cck rate in 5G band. */
++	if (pmlmeext->cur_channel > 14)
++		wirelessmode &= ~(WIRELESS_11B);
++
++	if ((wirelessmode & WIRELESS_11B) && (wirelessmode == WIRELESS_11B))
++		_rtw_memcpy(supported_rates, rtw_basic_rate_cck, 4);
++	else if (wirelessmode & WIRELESS_11B)
++		_rtw_memcpy(supported_rates, rtw_basic_rate_mix, 7);
++	else
++		_rtw_memcpy(supported_rates, rtw_basic_rate_ofdm, 3);
++
++	if (wirelessmode & WIRELESS_11B)
++		update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB);
++	else
++		update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB);
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, supported_rates);
++}
++
++unsigned char check_assoc_AP(u8 *pframe, uint len)
++{
++	unsigned int	i;
++	PNDIS_802_11_VARIABLE_IEs	pIE;
++
++	for (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;) {
++		pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i);
++
++		switch (pIE->ElementID) {
++		case _VENDOR_SPECIFIC_IE_:
++			if ((_rtw_memcmp(pIE->data, ARTHEROS_OUI1, 3)) || (_rtw_memcmp(pIE->data, ARTHEROS_OUI2, 3))) {
++				RTW_INFO("link to Artheros AP\n");
++				return HT_IOT_PEER_ATHEROS;
++			} else if ((_rtw_memcmp(pIE->data, BROADCOM_OUI1, 3))
++				   || (_rtw_memcmp(pIE->data, BROADCOM_OUI2, 3))
++				|| (_rtw_memcmp(pIE->data, BROADCOM_OUI3, 3))) {
++				RTW_INFO("link to Broadcom AP\n");
++				return HT_IOT_PEER_BROADCOM;
++			} else if (_rtw_memcmp(pIE->data, MARVELL_OUI, 3)) {
++				RTW_INFO("link to Marvell AP\n");
++				return HT_IOT_PEER_MARVELL;
++			} else if (_rtw_memcmp(pIE->data, RALINK_OUI, 3)) {
++				RTW_INFO("link to Ralink AP\n");
++				return HT_IOT_PEER_RALINK;
++			} else if (_rtw_memcmp(pIE->data, CISCO_OUI, 3)) {
++				RTW_INFO("link to Cisco AP\n");
++				return HT_IOT_PEER_CISCO;
++			} else if (_rtw_memcmp(pIE->data, REALTEK_OUI, 3)) {
++				u32	Vender = HT_IOT_PEER_REALTEK;
++
++				if (pIE->Length >= 5) {
++					if (pIE->data[4] == 1) {
++						/* if(pIE->data[5] & RT_HT_CAP_USE_LONG_PREAMBLE) */
++						/*	bssDesc->BssHT.RT2RT_HT_Mode |= RT_HT_CAP_USE_LONG_PREAMBLE; */
++
++						if (pIE->data[5] & RT_HT_CAP_USE_92SE) {
++							/* bssDesc->BssHT.RT2RT_HT_Mode |= RT_HT_CAP_USE_92SE; */
++							Vender = HT_IOT_PEER_REALTEK_92SE;
++						}
++					}
++
++					if (pIE->data[5] & RT_HT_CAP_USE_SOFTAP)
++						Vender = HT_IOT_PEER_REALTEK_SOFTAP;
++
++					if (pIE->data[4] == 2) {
++						if (pIE->data[6] & RT_HT_CAP_USE_JAGUAR_BCUT) {
++							Vender = HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP;
++							RTW_INFO("link to Realtek JAGUAR_BCUTAP\n");
++						}
++						if (pIE->data[6] & RT_HT_CAP_USE_JAGUAR_CCUT) {
++							Vender = HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP;
++							RTW_INFO("link to Realtek JAGUAR_CCUTAP\n");
++						}
++					}
++				}
++
++				RTW_INFO("link to Realtek AP\n");
++				return Vender;
++			} else if (_rtw_memcmp(pIE->data, AIRGOCAP_OUI, 3)) {
++				RTW_INFO("link to Airgo Cap\n");
++				return HT_IOT_PEER_AIRGO;
++			} else
++				break;
++
++		default:
++			break;
++		}
++
++		i += (pIE->Length + 2);
++	}
++
++	RTW_INFO("link to new AP\n");
++	return HT_IOT_PEER_UNKNOWN;
++}
++
++void get_assoc_AP_Vendor(char *vendor, u8 assoc_AP_vendor)
++{
++	switch (assoc_AP_vendor) {
++	
++	case HT_IOT_PEER_UNKNOWN:
++	sprintf(vendor, "%s", "unknown");
++	break;
++
++	case HT_IOT_PEER_REALTEK:
++	case HT_IOT_PEER_REALTEK_92SE:
++	case HT_IOT_PEER_REALTEK_SOFTAP:
++	case HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP:
++	case HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP:
++
++	sprintf(vendor, "%s", "Realtek");
++	break;
++
++	case HT_IOT_PEER_BROADCOM:
++	sprintf(vendor, "%s", "Broadcom");
++	break;
++
++	case HT_IOT_PEER_MARVELL:
++	sprintf(vendor, "%s", "Marvell");
++	break;
++
++	case HT_IOT_PEER_RALINK:
++	sprintf(vendor, "%s", "Ralink");
++	break;
++
++	case HT_IOT_PEER_CISCO:
++	sprintf(vendor, "%s", "Cisco");
++	break;
++
++	case HT_IOT_PEER_AIRGO:
++	sprintf(vendor, "%s", "Airgo");
++	break;
++
++	case HT_IOT_PEER_ATHEROS:
++	sprintf(vendor, "%s", "Atheros");
++	break;
++
++	default:
++	sprintf(vendor, "%s", "unkown");
++	break;
++	}
++
++}
++#ifdef CONFIG_RTS_FULL_BW
++void rtw_parse_sta_vendor_ie_8812(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len)
++{
++	unsigned char REALTEK_OUI[] = {0x00,0xe0, 0x4c};
++	u8 *p;
++
++	p = rtw_get_ie_ex(tlv_ies, tlv_ies_len, WLAN_EID_VENDOR_SPECIFIC, REALTEK_OUI, 3, NULL, NULL);
++	if (!p)
++		goto exit;
++	else {
++		if(*(p+1) > 6 ) {
++
++			if(*(p+6) != 2)
++				goto exit;
++			
++			if(*(p+8) == RT_HT_CAP_USE_JAGUAR_BCUT)
++				sta->vendor_8812 = TRUE;
++			else if (*(p+8) == RT_HT_CAP_USE_JAGUAR_CCUT)
++				sta->vendor_8812 = TRUE;
++		}
++	}
++exit:
++	return;
++}
++#endif/*CONFIG_RTS_FULL_BW*/
++
++#ifdef CONFIG_80211AC_VHT
++void get_vht_bf_cap(u8 *pframe, uint len, struct vht_bf_cap *bf_cap)
++{
++	unsigned int i;
++	PNDIS_802_11_VARIABLE_IEs pIE;
++
++	for (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;) {
++		pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i);
++
++		switch (pIE->ElementID) {
++
++		case EID_VHTCapability:
++			bf_cap->is_mu_bfer = GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data);
++			bf_cap->su_sound_dim = GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data);
++			break;
++		default:
++			break;
++		}
++		i += (pIE->Length + 2);
++	}
++}
++#endif
++
++void update_capinfo(PADAPTER Adapter, u16 updateCap)
++{
++	struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	BOOLEAN		ShortPreamble;
++
++	/* Check preamble mode, 2005.01.06, by rcnjko. */
++	/* Mark to update preamble value forever, 2008.03.18 by lanhsin */
++	/* if( pMgntInfo->RegPreambleMode == PREAMBLE_AUTO ) */
++	{
++
++		if (updateCap & cShortPreamble) {
++			/* Short Preamble */
++			if (pmlmeinfo->preamble_mode != PREAMBLE_SHORT) { /* PREAMBLE_LONG or PREAMBLE_AUTO */
++				ShortPreamble = _TRUE;
++				pmlmeinfo->preamble_mode = PREAMBLE_SHORT;
++				rtw_hal_set_hwreg(Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble);
++			}
++		} else {
++			/* Long Preamble */
++			if (pmlmeinfo->preamble_mode != PREAMBLE_LONG) { /* PREAMBLE_SHORT or PREAMBLE_AUTO */
++				ShortPreamble = _FALSE;
++				pmlmeinfo->preamble_mode = PREAMBLE_LONG;
++				rtw_hal_set_hwreg(Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble);
++			}
++		}
++	}
++
++	if (updateCap & cIBSS) {
++		/* Filen: See 802.11-2007 p.91 */
++		pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME;
++	} else {
++		/* Filen: See 802.11-2007 p.90 */
++		if (pmlmeext->cur_wireless_mode & (WIRELESS_11_24N | WIRELESS_11A | WIRELESS_11_5N | WIRELESS_11AC))
++			pmlmeinfo->slotTime = SHORT_SLOT_TIME;
++		else if (pmlmeext->cur_wireless_mode & (WIRELESS_11G)) {
++			if ((updateCap & cShortSlotTime) /* && (!(pMgntInfo->pHTInfo->RT2RT_HT_Mode & RT_HT_CAP_USE_LONG_PREAMBLE)) */) {
++				/* Short Slot Time */
++				pmlmeinfo->slotTime = SHORT_SLOT_TIME;
++			} else {
++				/* Long Slot Time */
++				pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME;
++			}
++		} else {
++			/* B Mode */
++			pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME;
++		}
++	}
++
++	rtw_hal_set_hwreg(Adapter, HW_VAR_SLOT_TIME, &pmlmeinfo->slotTime);
++
++}
++
++/*
++* set adapter.mlmeextpriv.mlmext_info.HT_enable
++* set adapter.mlmeextpriv.cur_wireless_mode
++* set SIFS register
++* set mgmt tx rate
++*/
++void update_wireless_mode(_adapter *padapter)
++{
++	int ratelen, network_type = 0;
++	u32 SIFS_Timer;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
++	unsigned char			*rate = cur_network->SupportedRates;
++#ifdef CONFIG_P2P
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++#endif /* CONFIG_P2P */
++
++	ratelen = rtw_get_rateset_len(cur_network->SupportedRates);
++
++	if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable))
++		pmlmeinfo->HT_enable = 1;
++
++	if (pmlmeext->cur_channel > 14) {
++		if (pmlmeinfo->VHT_enable)
++			network_type = WIRELESS_11AC;
++		else if (pmlmeinfo->HT_enable)
++			network_type = WIRELESS_11_5N;
++
++		network_type |= WIRELESS_11A;
++	} else {
++		if (pmlmeinfo->VHT_enable)
++			network_type = WIRELESS_11AC;
++		else if (pmlmeinfo->HT_enable)
++			network_type = WIRELESS_11_24N;
++
++		if ((cckratesonly_included(rate, ratelen)) == _TRUE)
++			network_type |= WIRELESS_11B;
++		else if ((cckrates_included(rate, ratelen)) == _TRUE)
++			network_type |= WIRELESS_11BG;
++		else
++			network_type |= WIRELESS_11G;
++	}
++
++	pmlmeext->cur_wireless_mode = network_type & padapter->registrypriv.wireless_mode;
++	/* RTW_INFO("network_type=%02x, padapter->registrypriv.wireless_mode=%02x\n", network_type, padapter->registrypriv.wireless_mode); */
++
++#ifndef RTW_HALMAC
++	/* HALMAC IC do not set HW_VAR_RESP_SIFS here */
++#if 0
++	if ((pmlmeext->cur_wireless_mode == WIRELESS_11G) ||
++	    (pmlmeext->cur_wireless_mode == WIRELESS_11BG)) /* WIRELESS_MODE_G) */
++		SIFS_Timer = 0x0a0a;/* CCK */
++	else
++		SIFS_Timer = 0x0e0e;/* pHalData->SifsTime; //OFDM */
++#endif
++
++	SIFS_Timer = 0x0a0a0808; /* 0x0808->for CCK, 0x0a0a->for OFDM
++                              * change this value if having IOT issues. */
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_RESP_SIFS, (u8 *)&SIFS_Timer);
++#endif
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_WIRELESS_MODE, (u8 *)&(pmlmeext->cur_wireless_mode));
++
++	if ((pmlmeext->cur_wireless_mode & WIRELESS_11B)
++		#ifdef CONFIG_P2P
++		&& (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
++			#ifdef CONFIG_IOCTL_CFG80211
++			|| !rtw_cfg80211_iface_has_p2p_group_cap(padapter)
++			#endif
++			)
++		#endif
++	)
++		update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB);
++	else
++		update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB);
++}
++
++void fire_write_MAC_cmd(_adapter *padapter, unsigned int addr, unsigned int value);
++void fire_write_MAC_cmd(_adapter *padapter, unsigned int addr, unsigned int value)
++{
++#if 0
++	struct cmd_obj					*ph2c;
++	struct reg_rw_parm			*pwriteMacPara;
++	struct cmd_priv					*pcmdpriv = &(padapter->cmdpriv);
++
++	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (ph2c == NULL)
++		return;
++
++	pwriteMacPara = (struct reg_rw_parm *)rtw_malloc(sizeof(struct reg_rw_parm));
++	if (pwriteMacPara == NULL) {
++		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
++		return;
++	}
++
++	pwriteMacPara->rw = 1;
++	pwriteMacPara->addr = addr;
++	pwriteMacPara->value = value;
++
++	init_h2fwcmd_w_parm_no_rsp(ph2c, pwriteMacPara, GEN_CMD_CODE(_Write_MACREG));
++	rtw_enqueue_cmd(pcmdpriv, ph2c);
++#endif
++}
++
++void update_sta_basic_rate(struct sta_info *psta, u8 wireless_mode)
++{
++	if (IsSupportedTxCCK(wireless_mode)) {
++		/* Only B, B/G, and B/G/N AP could use CCK rate */
++		_rtw_memcpy(psta->bssrateset, rtw_basic_rate_cck, 4);
++		psta->bssratelen = 4;
++	} else {
++		_rtw_memcpy(psta->bssrateset, rtw_basic_rate_ofdm, 3);
++		psta->bssratelen = 3;
++	}
++}
++
++int rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num)
++{
++	u8 *ie, *p;
++	unsigned int ie_len;
++	int i, j;
++
++	struct support_rate_handler support_rate_tbl[] = {
++		{IEEE80211_CCK_RATE_1MB, 		_FALSE,		_FALSE},
++		{IEEE80211_CCK_RATE_2MB, 		_FALSE,		_FALSE},
++		{IEEE80211_CCK_RATE_5MB, 		_FALSE,		_FALSE},
++		{IEEE80211_CCK_RATE_11MB,		_FALSE,		_FALSE},
++		{IEEE80211_OFDM_RATE_6MB,		_FALSE,		_FALSE},
++		{IEEE80211_OFDM_RATE_9MB,		_FALSE,		_FALSE},
++		{IEEE80211_OFDM_RATE_12MB,		_FALSE,		_FALSE},
++		{IEEE80211_OFDM_RATE_18MB,		_FALSE,		_FALSE},
++		{IEEE80211_OFDM_RATE_24MB,		_FALSE,		_FALSE},
++		{IEEE80211_OFDM_RATE_36MB,		_FALSE,		_FALSE},
++		{IEEE80211_OFDM_RATE_48MB,		_FALSE,		_FALSE},
++		{IEEE80211_OFDM_RATE_54MB,		_FALSE,		_FALSE},
++	};
++		
++	if (!rate_set || !rate_num)
++		return _FALSE;
++
++	*rate_num = 0;
++	ie = rtw_get_ie(ies, _SUPPORTEDRATES_IE_, &ie_len, ies_len);
++	if (ie == NULL)
++		goto ext_rate;
++
++	/* get valid supported rates */
++	for (i = 0; i < 12; i++) {
++		p = ie + 2;
++		for (j = 0; j < ie_len; j++) {
++			if ((*p & ~BIT(7)) == support_rate_tbl[i].rate){
++				support_rate_tbl[i].existence = _TRUE;
++				if ((*p) & BIT(7))
++					support_rate_tbl[i].basic = _TRUE;
++			}
++			p++;
++		}
++	}
++
++ext_rate:
++	ie = rtw_get_ie(ies, _EXT_SUPPORTEDRATES_IE_, &ie_len, ies_len);
++	if (ie) {
++		/* get valid extended supported rates */
++		for (i = 0; i < 12; i++) {
++			p = ie + 2;
++			for (j = 0; j < ie_len; j++) {
++				if ((*p & ~BIT(7)) == support_rate_tbl[i].rate){
++					support_rate_tbl[i].existence = _TRUE;
++					if ((*p) & BIT(7))
++						support_rate_tbl[i].basic = _TRUE;
++				}
++				p++;
++			}
++		}
++	}
++
++	for (i = 0; i < 12; i++){
++		if (support_rate_tbl[i].existence){
++			if (support_rate_tbl[i].basic)
++				rate_set[*rate_num] = support_rate_tbl[i].rate | IEEE80211_BASIC_RATE_MASK;
++			else
++				rate_set[*rate_num] = support_rate_tbl[i].rate;
++			*rate_num += 1;
++		}
++	}
++
++	if (*rate_num == 0)
++		return _FAIL;
++
++	if (0) {
++		int i;
++
++		for (i = 0; i < *rate_num; i++)
++			RTW_INFO("rate:0x%02x\n", *(rate_set + i));
++	}
++
++	return _SUCCESS;
++}
++
++void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr)
++{
++	struct sta_info *psta;
++	u16 tid, start_seq, param;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct ADDBA_request	*preq = (struct ADDBA_request *)paddba_req;
++	u8 size, accept = _FALSE;
++
++	psta = rtw_get_stainfo(pstapriv, addr);
++	if (!psta)
++		goto exit;
++
++	start_seq = le16_to_cpu(preq->BA_starting_seqctrl) >> 4;
++
++	param = le16_to_cpu(preq->BA_para_set);
++	tid = (param >> 2) & 0x0f;
++
++
++	accept = rtw_rx_ampdu_is_accept(padapter);
++	if (padapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID)
++		size = padapter->fix_rx_ampdu_size;
++	else {
++		size = rtw_rx_ampdu_size(padapter);
++		size = rtw_min(size, rx_ampdu_size_sta_limit(padapter, psta));
++	}
++
++	if (accept == _TRUE)
++		rtw_addbarsp_cmd(padapter, addr, tid, 0, size, start_seq);
++	else
++		rtw_addbarsp_cmd(padapter, addr, tid, 37, size, start_seq); /* reject ADDBA Req */
++
++exit:
++	return;
++}
++
++void rtw_process_bar_frame(_adapter *padapter, union recv_frame *precv_frame)
++{
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	struct sta_info *psta = NULL;
++	struct recv_reorder_ctrl *preorder_ctrl = NULL;
++	u8 tid = 0;
++	u16 start_seq=0;
++
++	psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
++	if (psta == NULL)
++		goto exit;
++
++	tid = ((cpu_to_le16((*(u16 *)(pframe + 16))) & 0xf000) >> 12);
++	preorder_ctrl = &psta->recvreorder_ctrl[tid];
++	start_seq = ((cpu_to_le16(*(u16 *)(pframe + 18))) >> 4);
++	preorder_ctrl->indicate_seq = start_seq;
++
++	/* for Debug use */
++	if (0)
++		RTW_INFO(FUNC_ADPT_FMT" tid=%d, start_seq=%d\n", FUNC_ADPT_ARG(padapter),  tid, start_seq);
++
++exit:
++	return;
++}
++
++void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len)
++{
++	u8 *pIE;
++	u32 *pbuf;
++
++	pIE = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
++	pbuf = (u32 *)pIE;
++
++	pmlmeext->TSFValue = le32_to_cpu(*(pbuf + 1));
++
++	pmlmeext->TSFValue = pmlmeext->TSFValue << 32;
++
++	pmlmeext->TSFValue |= le32_to_cpu(*pbuf);
++}
++
++void correct_TSF(_adapter *padapter, u8 mlme_state)
++{
++	u8 m_state = mlme_state;
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_CORRECT_TSF, (u8 *)&m_state);
++}
++
++#ifdef CONFIG_BCN_RECV_TIME
++/*	calculate beacon receiving time
++	1.RxBCNTime(CCK_1M) = [192us(preamble)] + [length of beacon(byte)*8us] + [10us]
++	2.RxBCNTime(OFDM_6M) = [8us(S) + 8us(L) + 4us(L-SIG)] + [(length of beacon(byte)/3 + 1] *4us] + [10us]
++*/
++inline u16 _rx_bcn_time_calculate(uint bcn_len, u8 data_rate)
++{
++	u16 rx_bcn_time = 0;/*us*/
++
++	if (data_rate == DESC_RATE1M)
++		rx_bcn_time = 192 + bcn_len * 8 + 10;
++	else if(data_rate == DESC_RATE6M)
++		rx_bcn_time = 8 + 8 + 4 + (bcn_len /3 + 1) * 4 + 10;
++/*
++	else
++		RTW_ERR("%s invalid data rate(0x%02x)\n", __func__, data_rate);
++*/
++	return rx_bcn_time;
++}
++void rtw_rx_bcn_time_update(_adapter *adapter, uint bcn_len, u8 data_rate)
++{
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++
++	pmlmeext->bcn_rx_time = _rx_bcn_time_calculate(bcn_len, data_rate);
++}
++#endif
++
++void beacon_timing_control(_adapter *padapter)
++{
++	rtw_hal_bcn_related_reg_setting(padapter);
++}
++
++inline bool _rtw_macid_ctl_chk_cap(_adapter *adapter, u8 cap)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct macid_ctl_t *macid_ctl = &dvobj->macid_ctl;
++
++	if (macid_ctl->macid_cap & cap)
++		return _TRUE;
++	return _FALSE;
++}
++
++
++void dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num)
++{
++	RTW_PRINT_SEL(sel, "0x%08x\n", map->m0);
++#if (MACID_NUM_SW_LIMIT > 32)
++	if (max_num && max_num > 32)
++		RTW_PRINT_SEL(sel, "0x%08x\n", map->m1);
++#endif
++#if (MACID_NUM_SW_LIMIT > 64)
++	if (max_num && max_num > 64)
++		RTW_PRINT_SEL(sel, "0x%08x\n", map->m2);
++#endif
++#if (MACID_NUM_SW_LIMIT > 96)
++	if (max_num && max_num > 96)
++		RTW_PRINT_SEL(sel, "0x%08x\n", map->m3);
++#endif
++}
++
++inline bool rtw_macid_is_set(struct macid_bmp *map, u8 id)
++{
++	if (id < 32)
++		return map->m0 & BIT(id);
++#if (MACID_NUM_SW_LIMIT > 32)
++	else if (id < 64)
++		return map->m1 & BIT(id - 32);
++#endif
++#if (MACID_NUM_SW_LIMIT > 64)
++	else if (id < 96)
++		return map->m2 & BIT(id - 64);
++#endif
++#if (MACID_NUM_SW_LIMIT > 96)
++	else if (id < 128)
++		return map->m3 & BIT(id - 96);
++#endif
++	else
++		rtw_warn_on(1);
++
++	return 0;
++}
++
++inline void rtw_macid_map_set(struct macid_bmp *map, u8 id)
++{
++	if (id < 32)
++		map->m0 |= BIT(id);
++#if (MACID_NUM_SW_LIMIT > 32)
++	else if (id < 64)
++		map->m1 |= BIT(id - 32);
++#endif
++#if (MACID_NUM_SW_LIMIT > 64)
++	else if (id < 96)
++		map->m2 |= BIT(id - 64);
++#endif
++#if (MACID_NUM_SW_LIMIT > 96)
++	else if (id < 128)
++		map->m3 |= BIT(id - 96);
++#endif
++	else
++		rtw_warn_on(1);
++}
++
++inline void rtw_macid_map_clr(struct macid_bmp *map, u8 id)
++{
++	if (id < 32)
++		map->m0 &= ~BIT(id);
++#if (MACID_NUM_SW_LIMIT > 32)
++	else if (id < 64)
++		map->m1 &= ~BIT(id - 32);
++#endif
++#if (MACID_NUM_SW_LIMIT > 64)
++	else if (id < 96)
++		map->m2 &= ~BIT(id - 64);
++#endif
++#if (MACID_NUM_SW_LIMIT > 96)
++	else if (id < 128)
++		map->m3 &= ~BIT(id - 96);
++#endif
++	else
++		rtw_warn_on(1);
++}
++
++inline bool rtw_macid_is_used(struct macid_ctl_t *macid_ctl, u8 id)
++{
++	return rtw_macid_is_set(&macid_ctl->used, id);
++}
++
++inline bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id)
++{
++	return rtw_macid_is_set(&macid_ctl->bmc, id);
++}
++
++inline u8 rtw_macid_get_iface_bmp(struct macid_ctl_t *macid_ctl, u8 id)
++{
++	int i;
++	u8 iface_bmp = 0;
++
++	for (i = 0; i < CONFIG_IFACE_NUMBER; i++) {
++		if (rtw_macid_is_set(&macid_ctl->if_g[i], id))
++			iface_bmp |= BIT(i);
++	}
++	return iface_bmp;
++}
++
++inline bool rtw_macid_is_iface_shared(struct macid_ctl_t *macid_ctl, u8 id)
++{
++#if CONFIG_IFACE_NUMBER >= 2
++	int i;
++	u8 iface_bmp = 0;
++
++	for (i = 0; i < CONFIG_IFACE_NUMBER; i++) {
++		if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) {
++			if (iface_bmp)
++				return 1;
++			iface_bmp |= BIT(i);
++		}
++	}
++#endif
++	return 0;
++}
++
++inline bool rtw_macid_is_iface_specific(struct macid_ctl_t *macid_ctl, u8 id, _adapter *adapter)
++{
++	int i;
++	u8 iface_bmp = 0;
++
++	for (i = 0; i < CONFIG_IFACE_NUMBER; i++) {
++		if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) {
++			if (iface_bmp || i != adapter->iface_id)
++				return 0;
++			iface_bmp |= BIT(i);
++		}
++	}
++
++	return iface_bmp ? 1 : 0;
++}
++
++inline s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id)
++{
++	int i;
++
++	for (i = 0; i < 2; i++) {
++		if (rtw_macid_is_set(&macid_ctl->ch_g[i], id))
++			return i;
++	}
++	return -1;
++}
++
++/*Record bc's mac-id and sec-cam-id*/
++inline void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++
++	macid_ctl->iface_bmc[padapter->iface_id] = mac_id;
++}
++inline u8 rtw_iface_bcmc_id_get(_adapter *padapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++
++	return macid_ctl->iface_bmc[padapter->iface_id];
++}
++#if defined(DBG_CONFIG_ERROR_RESET)
++void rtw_iface_bcmc_sec_cam_map_restore(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);
++	int cam_id = -1;
++
++	cam_id = rtw_iface_bcmc_id_get(adapter);
++	if (cam_id != INVALID_SEC_MAC_CAM_ID)
++		rtw_sec_cam_map_set(&cam_ctl->used, cam_id);
++}
++#endif
++void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta)
++{
++	int i;
++	_irqL irqL;
++	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++	struct macid_bmp *used_map = &macid_ctl->used;
++	/* static u8 last_id = 0;  for testing */
++	u8 last_id = 0;
++	u8 is_bc_sta = _FALSE;
++
++	if (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN)) {
++		psta->cmn.mac_id = macid_ctl->num;
++		return;
++	}
++
++	if (_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)) {
++		is_bc_sta = _TRUE;
++		rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID);	/*init default value*/
++	}
++
++	if (is_bc_sta
++		#ifndef SEC_DEFAULT_KEY_SEARCH
++		&& (MLME_IS_STA(padapter) || MLME_IS_NULL(padapter))
++		#endif
++	) {
++		/* STA mode have no BMC data TX, shared with this macid */
++		/* When non-concurrent, only one BMC data TX is used, shared with this macid */
++		/* TODO: When concurrent, non-security BMC data TX may use this, but will not control by specific macid sleep */
++		i = RTW_DEFAULT_MGMT_MACID;
++		goto assigned;
++	}
++
++	_enter_critical_bh(&macid_ctl->lock, &irqL);
++
++	for (i = last_id; i < macid_ctl->num; i++) {
++#ifdef CONFIG_MCC_MODE
++		/* macid 0/1 reserve for mcc for mgnt queue macid */
++		if (MCC_EN(padapter)) {
++			if (i == MCC_ROLE_STA_GC_MGMT_QUEUE_MACID)
++				continue;
++			if (i == MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID)
++				continue;
++		}
++#endif /* CONFIG_MCC_MODE */
++
++		#ifndef SEC_DEFAULT_KEY_SEARCH
++		/* for BMC data TX with force camid */
++		if (is_bc_sta && rtw_sec_camid_is_used(dvobj_to_sec_camctl(dvobj), i))
++			continue;
++		#endif
++
++		if (!rtw_macid_is_used(macid_ctl, i))
++			break;
++	}
++
++	if (i < macid_ctl->num) {
++
++		rtw_macid_map_set(used_map, i);
++
++		#ifndef SEC_DEFAULT_KEY_SEARCH
++		/* for BMC data TX with force camid */
++		if (is_bc_sta) {
++			struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);
++
++			rtw_macid_map_set(&macid_ctl->bmc, i);
++			rtw_iface_bcmc_id_set(padapter, i);
++			rtw_sec_cam_map_set(&cam_ctl->used, i);
++			if (_rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_EXTRA_SEC))
++				rtw_sec_cam_map_set(&cam_ctl->used, i + 1);
++		}
++		#endif
++
++		rtw_macid_map_set(&macid_ctl->if_g[padapter->iface_id], i);
++		macid_ctl->sta[i] = psta;
++
++		/* TODO ch_g? */
++
++		last_id++;
++		last_id %= macid_ctl->num;
++	}
++
++	_exit_critical_bh(&macid_ctl->lock, &irqL);
++
++	if (i >= macid_ctl->num) {
++		psta->cmn.mac_id = macid_ctl->num;
++		RTW_ERR(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" no available macid\n"
++			, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->cmn.mac_addr));
++		rtw_warn_on(1);
++		goto exit;
++	} else
++		goto assigned;
++
++assigned:
++	psta->cmn.mac_id = i;
++	RTW_INFO(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u\n"
++		, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);
++
++exit:
++	return;
++}
++
++void rtw_release_macid(_adapter *padapter, struct sta_info *psta)
++{
++	_irqL irqL;
++	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++	u8 ifbmp;
++	int i;
++
++	if (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN))
++		goto exit;
++
++	if (psta->cmn.mac_id >= macid_ctl->num) {
++		RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not valid\n"
++			, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1
++			, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (psta->cmn.mac_id == RTW_DEFAULT_MGMT_MACID)
++		goto msg;
++
++	_enter_critical_bh(&macid_ctl->lock, &irqL);
++
++	if (!rtw_macid_is_used(macid_ctl, psta->cmn.mac_id)) {
++		RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not used\n"
++			, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1
++			, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);
++		_exit_critical_bh(&macid_ctl->lock, &irqL);
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	ifbmp = rtw_macid_get_iface_bmp(macid_ctl, psta->cmn.mac_id);
++	if (!(ifbmp & BIT(padapter->iface_id))) {
++		RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not used by self\n"
++			, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1
++			, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);
++		_exit_critical_bh(&macid_ctl->lock, &irqL);
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)) {
++		struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);
++		u8 id = rtw_iface_bcmc_id_get(padapter);
++
++		if ((id != INVALID_SEC_MAC_CAM_ID) && (id < cam_ctl->num)) {
++			rtw_sec_cam_map_clr(&cam_ctl->used, id);
++			if (_rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_EXTRA_SEC))
++				rtw_sec_cam_map_clr(&cam_ctl->used, id + 1);
++		}
++
++		rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID);
++	}
++
++	rtw_macid_map_clr(&macid_ctl->if_g[padapter->iface_id], psta->cmn.mac_id);
++
++	ifbmp &= ~BIT(padapter->iface_id);
++	if (!ifbmp) { /* only used by self */
++		rtw_macid_map_clr(&macid_ctl->used, psta->cmn.mac_id);
++		rtw_macid_map_clr(&macid_ctl->bmc, psta->cmn.mac_id);
++		for (i = 0; i < 2; i++)
++			rtw_macid_map_clr(&macid_ctl->ch_g[i], psta->cmn.mac_id);
++		macid_ctl->sta[psta->cmn.mac_id] = NULL;
++	}
++
++	_exit_critical_bh(&macid_ctl->lock, &irqL);
++
++msg:
++	RTW_INFO(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u\n"
++		, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1
++		, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id
++	);
++
++exit:
++	psta->cmn.mac_id = macid_ctl->num;
++}
++
++/* For 8188E RA */
++u8 rtw_search_max_mac_id(_adapter *padapter)
++{
++	u8 max_mac_id = 0;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++	int i;
++	_irqL irqL;
++
++	/* TODO: Only search for connected macid? */
++
++	_enter_critical_bh(&macid_ctl->lock, &irqL);
++	for (i = (macid_ctl->num - 1); i > 0 ; i--) {
++		if (rtw_macid_is_used(macid_ctl, i))
++			break;
++	}
++	_exit_critical_bh(&macid_ctl->lock, &irqL);
++	max_mac_id = i;
++
++	return max_mac_id;
++}
++
++inline u8 rtw_macid_ctl_set_h2c_msr(struct macid_ctl_t *macid_ctl, u8 id, u8 h2c_msr)
++{
++	u8 op_num_change_bmp = 0;
++
++	if (id >= macid_ctl->num) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (GET_H2CCMD_MSRRPT_PARM_OPMODE(&macid_ctl->h2c_msr[id])
++		&& !GET_H2CCMD_MSRRPT_PARM_OPMODE(&h2c_msr)
++	) {
++		u8 role = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[id]);
++
++		if (role < H2C_MSR_ROLE_MAX) {
++			macid_ctl->op_num[role]--;
++			op_num_change_bmp |= BIT(role);
++		}
++	} else if (!GET_H2CCMD_MSRRPT_PARM_OPMODE(&macid_ctl->h2c_msr[id])
++		&& GET_H2CCMD_MSRRPT_PARM_OPMODE(&h2c_msr)
++	) {
++		u8 role = GET_H2CCMD_MSRRPT_PARM_ROLE(&h2c_msr);
++
++		if (role < H2C_MSR_ROLE_MAX) {
++			macid_ctl->op_num[role]++;
++			op_num_change_bmp |= BIT(role);
++		}
++	}
++
++	macid_ctl->h2c_msr[id] = h2c_msr;
++	if (0)
++		RTW_INFO("macid:%u, h2c_msr:"H2C_MSR_FMT"\n", id, H2C_MSR_ARG(&macid_ctl->h2c_msr[id]));
++
++exit:
++	return op_num_change_bmp;
++}
++
++inline void rtw_macid_ctl_set_bw(struct macid_ctl_t *macid_ctl, u8 id, u8 bw)
++{
++	if (id >= macid_ctl->num) {
++		rtw_warn_on(1);
++		return;
++	}
++
++	macid_ctl->bw[id] = bw;
++	if (0)
++		RTW_INFO("macid:%u, bw:%s\n", id, ch_width_str(macid_ctl->bw[id]));
++}
++
++inline void rtw_macid_ctl_set_vht_en(struct macid_ctl_t *macid_ctl, u8 id, u8 en)
++{
++	if (id >= macid_ctl->num) {
++		rtw_warn_on(1);
++		return;
++	}
++
++	macid_ctl->vht_en[id] = en;
++	if (0)
++		RTW_INFO("macid:%u, vht_en:%u\n", id, macid_ctl->vht_en[id]);
++}
++
++inline void rtw_macid_ctl_set_rate_bmp0(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp)
++{
++	if (id >= macid_ctl->num) {
++		rtw_warn_on(1);
++		return;
++	}
++
++	macid_ctl->rate_bmp0[id] = bmp;
++	if (0)
++		RTW_INFO("macid:%u, rate_bmp0:0x%08X\n", id, macid_ctl->rate_bmp0[id]);
++}
++
++inline void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp)
++{
++	if (id >= macid_ctl->num) {
++		rtw_warn_on(1);
++		return;
++	}
++
++	macid_ctl->rate_bmp1[id] = bmp;
++	if (0)
++		RTW_INFO("macid:%u, rate_bmp1:0x%08X\n", id, macid_ctl->rate_bmp1[id]);
++}
++
++#ifdef CONFIG_PROTSEL_MACSLEEP
++inline void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 reg_ctrl, u16 reg_info)
++{
++	macid_ctl->reg_sleep_ctrl = reg_ctrl;
++	macid_ctl->reg_sleep_info = reg_info;
++}
++inline void rtw_macid_ctl_init_drop_reg(struct macid_ctl_t *macid_ctl, u16 reg_ctrl, u16 reg_info)
++{
++	macid_ctl->reg_drop_ctrl = reg_ctrl;
++	macid_ctl->reg_drop_info = reg_info;
++}
++#else
++inline void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3)
++{
++	macid_ctl->reg_sleep_m0 = m0;
++#if (MACID_NUM_SW_LIMIT > 32)
++	macid_ctl->reg_sleep_m1 = m1;
++#endif
++#if (MACID_NUM_SW_LIMIT > 64)
++	macid_ctl->reg_sleep_m2 = m2;
++#endif
++#if (MACID_NUM_SW_LIMIT > 96)
++	macid_ctl->reg_sleep_m3 = m3;
++#endif
++}
++inline void rtw_macid_ctl_init_drop_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3)
++{
++	macid_ctl->reg_drop_m0 = m0;
++#if (MACID_NUM_SW_LIMIT > 32)
++	macid_ctl->reg_drop_m1 = m1;
++#endif
++#if (MACID_NUM_SW_LIMIT > 64)
++	macid_ctl->reg_drop_m2 = m2;
++#endif
++#if (MACID_NUM_SW_LIMIT > 96)
++	macid_ctl->reg_drop_m3 = m3;
++#endif
++}
++#endif
++
++inline void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl)
++{
++	int i;
++	u8 id = RTW_DEFAULT_MGMT_MACID;
++
++	rtw_macid_map_set(&macid_ctl->used, id);
++	rtw_macid_map_set(&macid_ctl->bmc, id);
++	for (i = 0; i < CONFIG_IFACE_NUMBER; i++)
++		rtw_macid_map_set(&macid_ctl->if_g[i], id);
++	macid_ctl->sta[id] = NULL;
++
++	_rtw_spinlock_init(&macid_ctl->lock);
++}
++
++inline void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl)
++{
++	_rtw_spinlock_free(&macid_ctl->lock);
++}
++
++inline bool rtw_bmp_is_set(const u8 *bmp, u8 bmp_len, u8 id)
++{
++	if (id / 8 >= bmp_len)
++		return 0;
++
++	return bmp[id / 8] & BIT(id % 8);
++}
++
++inline void rtw_bmp_set(u8 *bmp, u8 bmp_len, u8 id)
++{
++	if (id / 8 < bmp_len)
++		bmp[id / 8] |= BIT(id % 8);
++}
++
++inline void rtw_bmp_clear(u8 *bmp, u8 bmp_len, u8 id)
++{
++	if (id / 8 < bmp_len)
++		bmp[id / 8] &= ~BIT(id % 8);
++}
++
++inline bool rtw_bmp_not_empty(const u8 *bmp, u8 bmp_len)
++{
++	int i;
++
++	for (i = 0; i < bmp_len; i++) {
++		if (bmp[i])
++			return 1;
++	}
++
++	return 0;
++}
++
++inline bool rtw_bmp_not_empty_exclude_bit0(const u8 *bmp, u8 bmp_len)
++{
++	int i;
++
++	for (i = 0; i < bmp_len; i++) {
++		if (i == 0) {
++			if (bmp[i] & 0xFE)
++				return 1;
++		} else {
++			if (bmp[i])
++				return 1;
++		}
++	}
++
++	return 0;
++}
++
++#ifdef CONFIG_AP_MODE
++/* Check the id be set or not in map , if yes , return a none zero value*/
++bool rtw_tim_map_is_set(_adapter *padapter, const u8 *map, u8 id)
++{
++	return rtw_bmp_is_set(map, padapter->stapriv.aid_bmp_len, id);
++}
++
++/* Set the id into map array*/
++void rtw_tim_map_set(_adapter *padapter, u8 *map, u8 id)
++{
++	rtw_bmp_set(map, padapter->stapriv.aid_bmp_len, id);
++}
++
++/* Clear the id from map array*/
++void rtw_tim_map_clear(_adapter *padapter, u8 *map, u8 id)
++{
++	rtw_bmp_clear(map, padapter->stapriv.aid_bmp_len, id);
++}
++
++/* Check have anyone bit be set , if yes return true*/
++bool rtw_tim_map_anyone_be_set(_adapter *padapter, const u8 *map)
++{
++	return rtw_bmp_not_empty(map, padapter->stapriv.aid_bmp_len);
++}
++
++/* Check have anyone bit be set exclude bit0 , if yes return true*/
++bool rtw_tim_map_anyone_be_set_exclude_aid0(_adapter *padapter, const u8 *map)
++{
++	return rtw_bmp_not_empty_exclude_bit0(map, padapter->stapriv.aid_bmp_len);
++}
++#endif /* CONFIG_AP_MODE */
++
++#if 0
++unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame)
++{
++	unsigned short				ATIMWindow;
++	unsigned char					*pframe;
++	struct tx_desc				*ptxdesc;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	unsigned int					rate_len, len = 0;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
++	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++
++	_rtw_memset(beacon_frame, 0, 256);
++
++	pframe = beacon_frame + TXDESC_SIZE;
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
++
++	set_frame_sub_type(pframe, WIFI_BEACON);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	len = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	/* timestamp will be inserted by hardware */
++	pframe += 8;
++	len += 8;
++
++	/* beacon interval: 2 bytes */
++	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
++
++	pframe += 2;
++	len += 2;
++
++	/* capability info: 2 bytes */
++	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
++
++	pframe += 2;
++	len += 2;
++
++	/* SSID */
++	pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &len);
++
++	/* supported rates... */
++	rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
++	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &len);
++
++	/* DS parameter set */
++	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &len);
++
++	/* IBSS Parameter Set... */
++	/* ATIMWindow = cur->Configuration.ATIMWindow; */
++	ATIMWindow = 0;
++	pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &len);
++
++	/* todo: ERP IE */
++
++	/* EXTERNDED SUPPORTED RATE */
++	if (rate_len > 8)
++		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &len);
++
++	if ((len + TXDESC_SIZE) > 256) {
++		/* RTW_INFO("marc: beacon frame too large\n"); */
++		return 0;
++	}
++
++	/* fill the tx descriptor */
++	ptxdesc = (struct tx_desc *)beacon_frame;
++
++	/* offset 0	 */
++	ptxdesc->txdw0 |= cpu_to_le32(len & 0x0000ffff);
++	ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00ff0000); /* default = 32 bytes for TX Desc */
++
++	/* offset 4	 */
++	ptxdesc->txdw1 |= cpu_to_le32((0x10 << QSEL_SHT) & 0x00001f00);
++
++	/* offset 8		 */
++	ptxdesc->txdw2 |= cpu_to_le32(BMC);
++	ptxdesc->txdw2 |= cpu_to_le32(BK);
++
++	/* offset 16		 */
++	ptxdesc->txdw4 = 0x80000000;
++
++	/* offset 20 */
++	ptxdesc->txdw5 = 0x00000000; /* 1M	 */
++
++	return len + TXDESC_SIZE;
++}
++#endif
++
++_adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj)
++{
++	_adapter *port0_iface = NULL;
++	int i;
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		if (get_hw_port(dvobj->padapters[i]) == HW_PORT0)
++			break;
++	}
++
++	if (i < 0 || i >= dvobj->iface_nums)
++		rtw_warn_on(1);
++	else
++		port0_iface = dvobj->padapters[i];
++
++	return port0_iface;
++}
++
++_adapter *dvobj_get_unregisterd_adapter(struct dvobj_priv *dvobj)
++{
++	_adapter *adapter = NULL;
++	int i;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		if (dvobj->padapters[i]->registered == 0)
++			break;
++	}
++
++	if (i < dvobj->iface_nums)
++		adapter = dvobj->padapters[i];
++
++	return adapter;
++}
++
++_adapter *dvobj_get_adapter_by_addr(struct dvobj_priv *dvobj, u8 *addr)
++{
++	_adapter *adapter = NULL;
++	int i;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		if (_rtw_memcmp(dvobj->padapters[i]->mac_addr, addr, ETH_ALEN) == _TRUE)
++			break;
++	}
++
++	if (i < dvobj->iface_nums)
++		adapter = dvobj->padapters[i];
++
++	return adapter;
++}
++
++#ifdef CONFIG_WOWLAN
++bool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern,
++				   int *pattern_len, char *bit_mask)
++{
++	char *cp = NULL;
++	size_t len = 0;
++	int pos = 0, mask_pos = 0, res = 0;
++
++	/* To get the pattern string after "=", when we use :
++	 * iwpriv wlanX pattern=XX:XX:..:XX
++	 */
++	cp = strchr(input, '=');
++	if (cp) {
++		*cp = 0;
++		cp++;
++		input = cp;
++	}
++
++	/* To take off the newline character '\n'(0x0a) at the end of pattern string,
++	 * when we use echo xxxx > /proc/xxxx
++	 */
++	cp = strchr(input, '\n');
++	if (cp)
++		*cp = 0;
++
++	while (input) {
++		cp = strsep((char **)(&input), ":");
++
++		if (bit_mask && (strcmp(cp, "-") == 0 ||
++				 strcmp(cp, "xx") == 0 ||
++				 strcmp(cp, "--") == 0)) {
++			/* skip this byte and leave mask bit unset */
++		} else {
++			u8 hex;
++
++			if (strlen(cp) != 2) {
++				RTW_ERR("%s:[ERROR] hex len != 2, input=[%s]\n",
++					__func__, cp);
++				goto error;
++			}
++
++			if (hexstr2bin(cp, &hex, 1) < 0) {
++				RTW_ERR("%s:[ERROR] pattern is invalid, input=[%s]\n",
++					__func__, cp);
++				goto error;
++			}
++
++			pattern[pos] = hex;
++			mask_pos = pos / 8;
++			if (bit_mask)
++				bit_mask[mask_pos] |= 1 << (pos % 8);
++		}
++
++		pos++;
++	}
++
++	(*pattern_len) = pos;
++
++	return _TRUE;
++error:
++	return _FALSE;
++}
++
++void rtw_wow_pattern_sw_reset(_adapter *adapter)
++{
++	int i;
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter);
++
++	if (pwrctrlpriv->default_patterns_en == _TRUE)
++		pwrctrlpriv->wowlan_pattern_idx = DEFAULT_PATTERN_NUM;
++	else
++		pwrctrlpriv->wowlan_pattern_idx = 0;
++
++	for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) {
++		_rtw_memset(pwrctrlpriv->patterns[i].content, '\0', sizeof(pwrctrlpriv->patterns[i].content));
++		_rtw_memset(pwrctrlpriv->patterns[i].mask, '\0', sizeof(pwrctrlpriv->patterns[i].mask));
++		pwrctrlpriv->patterns[i].len = 0;
++	}
++}
++
++u8 rtw_set_default_pattern(_adapter *adapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
++	u8 index = 0;
++	u8 multicast_addr[3] = {0x01, 0x00, 0x5e};
++	u8 multicast_ip[4] = {0xe0, 0x28, 0x28, 0x2a};
++
++	u8 unicast_mask[5] = {0x3f, 0x70, 0x80, 0xc0, 0x03};
++	u8 icmpv6_mask[7] = {0x00, 0x70, 0x10, 0x00, 0xc0, 0xc0, 0x3f};
++	u8 multicast_mask[5] = {0x07, 0x70, 0x80, 0xc0, 0x03};
++
++	u8 ip_protocol[3] = {0x08, 0x00, 0x45};
++	u8 ipv6_protocol[3] = {0x86, 0xdd, 0x60};
++
++	u8 *target = NULL;
++
++	if (pwrpriv->default_patterns_en == _FALSE)
++		return 0;
++
++	for (index = 0 ; index < DEFAULT_PATTERN_NUM ; index++) {
++		_rtw_memset(pwrpriv->patterns[index].content, 0,
++			    sizeof(pwrpriv->patterns[index].content));
++		_rtw_memset(pwrpriv->patterns[index].mask, 0,
++			    sizeof(pwrpriv->patterns[index].mask));
++		pwrpriv->patterns[index].len = 0;
++	}
++
++	/*TCP/ICMP unicast*/
++	for (index = 0 ; index < DEFAULT_PATTERN_NUM ; index++) {
++		switch (index) {
++		case 0:
++			target = pwrpriv->patterns[index].content;
++			_rtw_memcpy(target, adapter_mac_addr(adapter),
++				    ETH_ALEN);
++
++			target += ETH_TYPE_OFFSET;
++			_rtw_memcpy(target, &ip_protocol,
++				    sizeof(ip_protocol));
++
++			/* TCP */
++			target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET);
++			_rtw_memset(target, 0x06, 1);
++
++			target += (IP_OFFSET - PROTOCOL_OFFSET);
++
++			_rtw_memcpy(target, pmlmeinfo->ip_addr,
++				    RTW_IP_ADDR_LEN);
++
++			_rtw_memcpy(pwrpriv->patterns[index].mask,
++				    &unicast_mask, sizeof(unicast_mask));
++
++			pwrpriv->patterns[index].len =
++				IP_OFFSET + RTW_IP_ADDR_LEN;
++			break;
++		case 1:
++			target = pwrpriv->patterns[index].content;
++			_rtw_memcpy(target, adapter_mac_addr(adapter),
++				    ETH_ALEN);
++
++			target += ETH_TYPE_OFFSET;
++			_rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol));
++
++			/* ICMP */
++			target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET);
++			_rtw_memset(target, 0x01, 1);
++
++			target += (IP_OFFSET - PROTOCOL_OFFSET);
++			_rtw_memcpy(target, pmlmeinfo->ip_addr,
++				    RTW_IP_ADDR_LEN);
++
++			_rtw_memcpy(pwrpriv->patterns[index].mask,
++				    &unicast_mask, sizeof(unicast_mask));
++			pwrpriv->patterns[index].len =
++
++				IP_OFFSET + RTW_IP_ADDR_LEN;
++			break;
++#ifdef CONFIG_IPV6
++		case 2:
++			if (pwrpriv->wowlan_ns_offload_en == _TRUE) {
++				target = pwrpriv->patterns[index].content;
++				target += ETH_TYPE_OFFSET;
++
++				_rtw_memcpy(target, &ipv6_protocol,
++					    sizeof(ipv6_protocol));
++
++				/* ICMPv6 */
++				target += (IPv6_PROTOCOL_OFFSET -
++					   ETH_TYPE_OFFSET);
++				_rtw_memset(target, 0x3a, 1);
++
++				target += (IPv6_OFFSET - IPv6_PROTOCOL_OFFSET);
++				_rtw_memcpy(target, pmlmeinfo->ip6_addr,
++					    RTW_IPv6_ADDR_LEN);
++
++				_rtw_memcpy(pwrpriv->patterns[index].mask,
++					    &icmpv6_mask, sizeof(icmpv6_mask));
++				pwrpriv->patterns[index].len =
++					IPv6_OFFSET + RTW_IPv6_ADDR_LEN;
++			}
++			break;
++#endif /*CONFIG_IPV6*/
++		case 3:
++			target = pwrpriv->patterns[index].content;
++			_rtw_memcpy(target, &multicast_addr,
++				    sizeof(multicast_addr));
++
++			target += ETH_TYPE_OFFSET;
++			_rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol));
++
++			/* UDP */
++			target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET);
++			_rtw_memset(target, 0x11, 1);
++
++			target += (IP_OFFSET - PROTOCOL_OFFSET);
++			_rtw_memcpy(target, &multicast_ip,
++				    sizeof(multicast_ip));
++
++			_rtw_memcpy(pwrpriv->patterns[index].mask,
++				    &multicast_mask, sizeof(multicast_mask));
++
++			pwrpriv->patterns[index].len =
++				IP_OFFSET + sizeof(multicast_ip);
++			break;
++		default:
++			break;
++		}
++	}
++	return index;
++}
++
++void rtw_dump_priv_pattern(_adapter *adapter, u8 idx)
++{
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
++	char str_1[128];
++	char *p_str;
++	u8 val8 = 0;
++	int i = 0, j = 0, len = 0, max_len = 0;
++
++	RTW_INFO("=========[%d]========\n", idx);
++
++	RTW_INFO(">>>priv_pattern_content:\n");
++	p_str = str_1;
++	max_len = sizeof(str_1);
++	for (i = 0 ; i < MAX_WKFM_PATTERN_SIZE / 8 ; i++) {
++		_rtw_memset(p_str, 0, max_len);
++		len = 0;
++		for (j = 0 ; j < 8 ; j++) {
++			val8 = pwrctl->patterns[idx].content[i * 8 + j];
++			len += snprintf(p_str + len, max_len - len,
++					"%02x ", val8);
++		}
++		RTW_INFO("%s\n", p_str);
++	}
++
++	RTW_INFO(">>>priv_pattern_mask:\n");
++	for (i = 0 ; i < MAX_WKFM_SIZE / 8 ; i++) {
++		_rtw_memset(p_str, 0, max_len);
++		len = 0;
++		for (j = 0 ; j < 8 ; j++) {
++			val8 = pwrctl->patterns[idx].mask[i * 8 + j];
++			len += snprintf(p_str + len, max_len - len,
++					"%02x ", val8);
++		}
++		RTW_INFO("%s\n", p_str);
++	}
++
++	RTW_INFO(">>>priv_pattern_len:\n");
++	RTW_INFO("%s: len: %d\n", __func__, pwrctl->patterns[idx].len);
++}
++
++void rtw_wow_pattern_sw_dump(_adapter *adapter)
++{
++	int i;
++
++	RTW_INFO("********[RTK priv-patterns]*********\n");
++	for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++)
++		rtw_dump_priv_pattern(adapter, i);
++}
++
++void rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr)
++{
++	struct sta_info		*psta;
++	struct security_priv *psecpriv = &padapter->securitypriv;
++
++	_rtw_memset(pcur_dot11txpn, 0, 8);
++	if (NULL == StaAddr)
++		return;
++	psta = rtw_get_stainfo(&padapter->stapriv, StaAddr);
++	RTW_INFO("%s(): StaAddr: %02x %02x %02x %02x %02x %02x\n",
++		 __func__, StaAddr[0], StaAddr[1], StaAddr[2],
++		 StaAddr[3], StaAddr[4], StaAddr[5]);
++
++	if (psta) {
++		if ((psecpriv->dot11PrivacyAlgrthm == _AES_) ||
++			(psecpriv->dot11PrivacyAlgrthm == _CCMP_256_))
++			AES_IV(pcur_dot11txpn, psta->dot11txpn, 0);
++		else if (psecpriv->dot11PrivacyAlgrthm == _TKIP_)
++			TKIP_IV(pcur_dot11txpn, psta->dot11txpn, 0);
++		else if ((psecpriv->dot11PrivacyAlgrthm == _GCMP_) ||
++				(psecpriv->dot11PrivacyAlgrthm == _GCMP_256_))
++			GCMP_IV(pcur_dot11txpn, psta->dot11txpn, 0);
++
++		RTW_INFO("%s(): CurrentIV: %02x %02x %02x %02x %02x %02x %02x %02x\n"
++			 , __func__, pcur_dot11txpn[0], pcur_dot11txpn[1],
++			pcur_dot11txpn[2], pcur_dot11txpn[3], pcur_dot11txpn[4],
++			pcur_dot11txpn[5], pcur_dot11txpn[6], pcur_dot11txpn[7]);
++	}
++}
++#endif /* CONFIG_WOWLAN */
++
++inline bool _rtw_wow_chk_cap(_adapter *adapter, u8 cap)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct wow_ctl_t *wow_ctl = &dvobj->wow_ctl;
++
++	if (wow_ctl->wow_cap & cap)
++		return _TRUE;
++	return _FALSE;
++}
++
++#ifdef CONFIG_PNO_SUPPORT
++#define	CSCAN_TLV_TYPE_SSID_IE	'S'
++#define CIPHER_IE "key_mgmt="
++#define CIPHER_NONE "NONE"
++#define CIPHER_WPA_PSK "WPA-PSK"
++#define CIPHER_WPA_EAP "WPA-EAP IEEE8021X"
++/*
++ *  SSIDs list parsing from cscan tlv list
++ */
++int rtw_parse_ssid_list_tlv(char **list_str, pno_ssid_t *ssid,
++			    int max, int *bytes_left)
++{
++	char *str;
++
++	int idx = 0;
++
++	if ((list_str == NULL) || (*list_str == NULL) || (*bytes_left < 0)) {
++		RTW_INFO("%s error paramters\n", __func__);
++		return -1;
++	}
++
++	str = *list_str;
++	while (*bytes_left > 0) {
++
++		if (str[0] != CSCAN_TLV_TYPE_SSID_IE) {
++			*list_str = str;
++			RTW_INFO("nssid=%d left_parse=%d %d\n", idx, *bytes_left, str[0]);
++			return idx;
++		}
++
++		/* Get proper CSCAN_TLV_TYPE_SSID_IE */
++		*bytes_left -= 1;
++		str += 1;
++
++		if (str[0] == 0) {
++			/* Broadcast SSID */
++			ssid[idx].SSID_len = 0;
++			memset((char *)ssid[idx].SSID, 0x0, WLAN_SSID_MAXLEN);
++			*bytes_left -= 1;
++			str += 1;
++
++			RTW_INFO("BROADCAST SCAN  left=%d\n", *bytes_left);
++		} else if (str[0] <= WLAN_SSID_MAXLEN) {
++			/* Get proper SSID size */
++			ssid[idx].SSID_len = str[0];
++			*bytes_left -= 1;
++			str += 1;
++
++			/* Get SSID */
++			if (ssid[idx].SSID_len > *bytes_left) {
++				RTW_INFO("%s out of memory range len=%d but left=%d\n",
++					__func__, ssid[idx].SSID_len, *bytes_left);
++				return -1;
++			}
++
++			memcpy((char *)ssid[idx].SSID, str, ssid[idx].SSID_len);
++
++			*bytes_left -= ssid[idx].SSID_len;
++			str += ssid[idx].SSID_len;
++
++			RTW_INFO("%s :size=%d left=%d\n",
++				(char *)ssid[idx].SSID, ssid[idx].SSID_len, *bytes_left);
++		} else {
++			RTW_INFO("### SSID size more that %d\n", str[0]);
++			return -1;
++		}
++
++		if (idx++ >  max) {
++			RTW_INFO("%s number of SSIDs more that %d\n", __func__, idx);
++			return -1;
++		}
++	}
++
++	*list_str = str;
++	return idx;
++}
++
++int rtw_parse_cipher_list(struct pno_nlo_info *nlo_info, char *list_str)
++{
++
++	char *pch, *pnext, *pend;
++	u8 key_len = 0, index = 0;
++
++	pch = list_str;
++
++	if (nlo_info == NULL || list_str == NULL) {
++		RTW_INFO("%s error paramters\n", __func__);
++		return -1;
++	}
++
++	while (strlen(pch) != 0) {
++		pnext = strstr(pch, "key_mgmt=");
++		if (pnext != NULL) {
++			pch = pnext + strlen(CIPHER_IE);
++			pend = strstr(pch, "}");
++			if (strncmp(pch, CIPHER_NONE,
++				    strlen(CIPHER_NONE)) == 0)
++				nlo_info->ssid_cipher_info[index] = 0x00;
++			else if (strncmp(pch, CIPHER_WPA_PSK,
++					 strlen(CIPHER_WPA_PSK)) == 0)
++				nlo_info->ssid_cipher_info[index] = 0x66;
++			else if (strncmp(pch, CIPHER_WPA_EAP,
++					 strlen(CIPHER_WPA_EAP)) == 0)
++				nlo_info->ssid_cipher_info[index] = 0x01;
++			index++;
++			pch = pend + 1;
++		} else
++			break;
++	}
++	return 0;
++}
++
++int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid,
++		 int num, int pno_time, int pno_repeat, int pno_freq_expo_max)
++{
++
++	int i = 0;
++	struct file *fp;
++	mm_segment_t fs;
++	loff_t pos = 0;
++	u8 *source = NULL;
++	long len = 0;
++
++	RTW_INFO("+%s+\n", __func__);
++
++	nlo_info->fast_scan_period = pno_time;
++	nlo_info->ssid_num = num & BIT_LEN_MASK_32(8);
++	nlo_info->hidden_ssid_num = num & BIT_LEN_MASK_32(8);
++	nlo_info->slow_scan_period = (pno_time * 2);
++	nlo_info->fast_scan_iterations = 5;
++
++	if (nlo_info->hidden_ssid_num > 8)
++		nlo_info->hidden_ssid_num = 8;
++
++	/* TODO: channel list and probe index is all empty. */
++	for (i = 0 ; i < num ; i++) {
++		nlo_info->ssid_length[i]
++			= ssid[i].SSID_len;
++	}
++
++	/* cipher array */
++	fp = filp_open("/data/misc/wifi/wpa_supplicant.conf", O_RDONLY,  0644);
++	if (IS_ERR(fp)) {
++		RTW_INFO("Error, wpa_supplicant.conf doesn't exist.\n");
++		RTW_INFO("Error, cipher array using default value.\n");
++		return 0;
++	}
++
++	len = i_size_read(fp->f_path.dentry->d_inode);
++	if (len < 0 || len > 2048) {
++		RTW_INFO("Error, file size is bigger than 2048.\n");
++		RTW_INFO("Error, cipher array using default value.\n");
++		return 0;
++	}
++
++	fs = get_fs();
++	set_fs(KERNEL_DS);
++
++	source = rtw_zmalloc(2048);
++
++	if (source != NULL) {
++		len = vfs_read(fp, source, len, &pos);
++		rtw_parse_cipher_list(nlo_info, source);
++		rtw_mfree(source, 2048);
++	}
++
++	set_fs(fs);
++	filp_close(fp, NULL);
++
++	RTW_INFO("-%s-\n", __func__);
++	return 0;
++}
++
++int rtw_dev_ssid_list_set(struct pno_ssid_list *pno_ssid_list,
++			  pno_ssid_t *ssid, u8 num)
++{
++
++	int i = 0;
++	if (num > MAX_PNO_LIST_COUNT)
++		num = MAX_PNO_LIST_COUNT;
++
++	for (i = 0 ; i < num ; i++) {
++		_rtw_memcpy(&pno_ssid_list->node[i].SSID,
++			    ssid[i].SSID, ssid[i].SSID_len);
++		pno_ssid_list->node[i].SSID_len = ssid[i].SSID_len;
++	}
++	return 0;
++}
++
++int rtw_dev_scan_info_set(_adapter *padapter, pno_ssid_t *ssid,
++	  unsigned char ch, unsigned char ch_offset, unsigned short bw_mode)
++{
++
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
++	struct pno_scan_info *scan_info = pwrctl->pscan_info;
++	u8 band = ch <= 14 ? BAND_ON_2_4G : BAND_ON_5G;
++	int i;
++
++	scan_info->channel_num = MAX_SCAN_LIST_COUNT;
++	scan_info->orig_ch = ch;
++	scan_info->orig_bw = bw_mode;
++	scan_info->orig_40_offset = ch_offset;
++
++	for (i = 0 ; i < scan_info->channel_num ; i++) {
++		if (i < 11)
++			scan_info->ssid_channel_info[i].active = 1;
++		else
++			scan_info->ssid_channel_info[i].active = 0;
++
++		scan_info->ssid_channel_info[i].timeout = 100;
++
++		scan_info->ssid_channel_info[i].tx_power =
++			phy_get_tx_power_index_ex(padapter, 0, CCK, MGN_1M, bw_mode, band, i + 1, i + 1);
++
++		scan_info->ssid_channel_info[i].channel = i + 1;
++	}
++
++	RTW_INFO("%s, channel_num: %d, orig_ch: %d, orig_bw: %d orig_40_offset: %d\n",
++		 __func__, scan_info->channel_num, scan_info->orig_ch,
++		 scan_info->orig_bw, scan_info->orig_40_offset);
++	return 0;
++}
++
++int rtw_dev_pno_set(struct net_device *net, pno_ssid_t *ssid, int num,
++		    int pno_time, int pno_repeat, int pno_freq_expo_max)
++{
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++
++	int ret = -1;
++
++	if (num == 0) {
++		RTW_INFO("%s, nssid is zero, no need to setup pno ssid list\n", __func__);
++		return 0;
++	}
++
++	if (pwrctl == NULL) {
++		RTW_INFO("%s, ERROR: pwrctl is NULL\n", __func__);
++		return -1;
++	} else {
++		pwrctl->pnlo_info =
++			(pno_nlo_info_t *)rtw_zmalloc(sizeof(pno_nlo_info_t));
++		pwrctl->pno_ssid_list =
++			(pno_ssid_list_t *)rtw_zmalloc(sizeof(pno_ssid_list_t));
++		pwrctl->pscan_info =
++			(pno_scan_info_t *)rtw_zmalloc(sizeof(pno_scan_info_t));
++	}
++
++	if (pwrctl->pnlo_info == NULL ||
++	    pwrctl->pscan_info == NULL ||
++	    pwrctl->pno_ssid_list == NULL) {
++		RTW_INFO("%s, ERROR: alloc nlo_info, ssid_list, scan_info fail\n", __func__);
++		goto failing;
++	}
++
++	pwrctl->wowlan_in_resume = _FALSE;
++
++	pwrctl->pno_inited = _TRUE;
++	/* NLO Info */
++	ret = rtw_dev_nlo_info_set(pwrctl->pnlo_info, ssid, num,
++				   pno_time, pno_repeat, pno_freq_expo_max);
++
++	/* SSID Info */
++	ret = rtw_dev_ssid_list_set(pwrctl->pno_ssid_list, ssid, num);
++
++	/* SCAN Info */
++	ret = rtw_dev_scan_info_set(padapter, ssid, pmlmeext->cur_channel,
++			    pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++
++	RTW_INFO("+%s num: %d, pno_time: %d, pno_repeat:%d, pno_freq_expo_max:%d+\n",
++		 __func__, num, pno_time, pno_repeat, pno_freq_expo_max);
++
++	return 0;
++
++failing:
++	if (pwrctl->pnlo_info) {
++		rtw_mfree((u8 *)pwrctl->pnlo_info, sizeof(pno_nlo_info_t));
++		pwrctl->pnlo_info = NULL;
++	}
++	if (pwrctl->pno_ssid_list) {
++		rtw_mfree((u8 *)pwrctl->pno_ssid_list, sizeof(pno_ssid_list_t));
++		pwrctl->pno_ssid_list = NULL;
++	}
++	if (pwrctl->pscan_info) {
++		rtw_mfree((u8 *)pwrctl->pscan_info, sizeof(pno_scan_info_t));
++		pwrctl->pscan_info = NULL;
++	}
++
++	return -1;
++}
++
++#ifdef CONFIG_PNO_SET_DEBUG
++void rtw_dev_pno_debug(struct net_device *net)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
++	int i = 0, j = 0;
++
++	RTW_INFO("*******NLO_INFO********\n");
++	RTW_INFO("ssid_num: %d\n", pwrctl->pnlo_info->ssid_num);
++	RTW_INFO("fast_scan_iterations: %d\n",
++		 pwrctl->pnlo_info->fast_scan_iterations);
++	RTW_INFO("fast_scan_period: %d\n", pwrctl->pnlo_info->fast_scan_period);
++	RTW_INFO("slow_scan_period: %d\n", pwrctl->pnlo_info->slow_scan_period);
++
++
++
++	for (i = 0 ; i < MAX_PNO_LIST_COUNT ; i++) {
++		RTW_INFO("%d SSID (%s) length (%d) cipher(%x) channel(%d)\n",
++			i, pwrctl->pno_ssid_list->node[i].SSID, pwrctl->pnlo_info->ssid_length[i],
++			pwrctl->pnlo_info->ssid_cipher_info[i], pwrctl->pnlo_info->ssid_channel_info[i]);
++	}
++
++	RTW_INFO("******SCAN_INFO******\n");
++	RTW_INFO("ch_num: %d\n", pwrctl->pscan_info->channel_num);
++	RTW_INFO("orig_ch: %d\n", pwrctl->pscan_info->orig_ch);
++	RTW_INFO("orig bw: %d\n", pwrctl->pscan_info->orig_bw);
++	RTW_INFO("orig 40 offset: %d\n", pwrctl->pscan_info->orig_40_offset);
++	for (i = 0 ; i < MAX_SCAN_LIST_COUNT ; i++) {
++		RTW_INFO("[%02d] avtive:%d, timeout:%d, tx_power:%d, ch:%02d\n",
++			 i, pwrctl->pscan_info->ssid_channel_info[i].active,
++			 pwrctl->pscan_info->ssid_channel_info[i].timeout,
++			 pwrctl->pscan_info->ssid_channel_info[i].tx_power,
++			 pwrctl->pscan_info->ssid_channel_info[i].channel);
++	}
++	RTW_INFO("*****************\n");
++}
++#endif /* CONFIG_PNO_SET_DEBUG */
++#endif /* CONFIG_PNO_SUPPORT */
++
++inline void rtw_collect_bcn_info(_adapter *adapter)
++{
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++
++	if (!is_client_associated_to_ap(adapter))
++		return;
++
++	pmlmeext->cur_bcn_cnt = pmlmeext->bcn_cnt - pmlmeext->last_bcn_cnt;
++	pmlmeext->last_bcn_cnt = pmlmeext->bcn_cnt;
++	/*TODO get offset of bcn's timestamp*/
++	/*pmlmeext->bcn_timestamp;*/
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_wnm.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_wnm.c
+new file mode 100755
+index 000000000..85e9f3f31
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_wnm.c
+@@ -0,0 +1,865 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++#ifndef RTW_WNM_DBG
++	#define RTW_WNM_DBG	0
++#endif
++#if RTW_WNM_DBG
++	#define RTW_WNM_INFO(fmt, arg...)	\
++		RTW_INFO(fmt, arg)
++	#define RTW_WNM_DUMP(str, data, len)	\
++		RTW_INFO_DUMP(str, data, len)
++#else
++	#define RTW_WNM_INFO(fmt, arg...) do {} while (0)
++	#define RTW_WNM_DUMP(str, data, len) do {} while (0)
++#endif
++
++#ifdef CONFIG_RTW_WNM
++
++static u32 wnm_defualt_validity_time = 6000;
++static u32 wnm_default_disassoc_time = 5000;
++static u32 wnm_disassoc_wait_time = 500;
++
++/* for wifi test, need more validity time to wait scan done */
++static u32 wnm_ext_validity_time = 4000;
++
++static void rtw_wmn_btm_cache_update(_adapter *padapter, struct btm_req_hdr *phdr)
++{
++	struct btm_rpt_cache *pcache = &(padapter->mlmepriv.nb_info.btm_cache);
++
++	pcache->dialog_token = phdr->dialog_token;
++	pcache->req_mode = phdr->req_mode;
++	pcache->disassoc_timer = le16_to_cpu(phdr->disassoc_timer);
++
++	if (phdr->validity_interval  > 0)
++		pcache->validity_interval = phdr->validity_interval;
++
++	pcache->term_duration.id = phdr->term_duration.id;
++	pcache->term_duration.len = phdr->term_duration.len;
++	pcache->term_duration.tsf = le64_to_cpu(phdr->term_duration.tsf);
++	pcache->term_duration.duration =  le16_to_cpu(phdr->term_duration.duration);
++
++	RTW_WNM_INFO("%s: req_mode(0x%02x), disassoc_timer(0x%04x), "
++		"validity_interval(0x%02x %s), tsf(0x%llx), duration(0x%02x)\n",
++		__func__, pcache->req_mode, pcache->disassoc_timer,
++		pcache->validity_interval, (!phdr->validity_interval)?"default":"",
++		pcache->term_duration.tsf,
++		pcache->term_duration.duration);
++
++	if (pcache->validity_interval > 0) {
++		pcache->validity_time = pcache->validity_interval * 100;
++	#ifdef CONFIG_RTW_MBO
++		if (rtw_mbo_wifi_logo_test(padapter))
++			pcache->validity_time += wnm_ext_validity_time;
++	#endif
++	}
++
++	if (pcache->disassoc_timer > 0) {
++		pcache->disassoc_time= pcache->disassoc_timer * 100;
++	#ifdef CONFIG_RTW_MBO
++		if (rtw_mbo_wifi_logo_test(padapter))
++			pcache->disassoc_time += wnm_ext_validity_time;
++	#endif
++	}
++
++	pcache->req_stime = rtw_get_current_time();
++
++	RTW_WNM_INFO("%s: validity_time=%u, disassoc_time=%u\n",
++		__func__, pcache->validity_time, pcache->disassoc_time);
++}
++
++static u8 rtw_wnm_btm_candidate_validity(struct btm_rpt_cache *pcache, u8 flag)
++{
++	u8 is_validity =_TRUE;
++	u32 req_validity_time = rtw_get_passing_time_ms(pcache->req_stime);
++
++	if ((flag & BIT(0)) && (req_validity_time > pcache->validity_time))
++		is_validity = _FALSE;
++
++	if ((flag & BIT(1)) && (req_validity_time > pcache->disassoc_time))
++		is_validity = _FALSE;
++
++	RTW_WNM_INFO("%s : validity=%u, rtime=%u, vtime=%u. dtime=%u\n",
++			__func__, is_validity, req_validity_time,
++			pcache->validity_time, pcache->disassoc_time);
++	return is_validity;
++}
++
++u8 rtw_wmn_btm_rsp_reason_decision(_adapter *padapter, u8* req_mode)
++{
++	struct recv_priv *precvpriv = &padapter->recvpriv;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	u8 reason = 0;
++
++	if (!rtw_wnm_btm_diff_bss(padapter)) {
++		/* Reject - No suitable BSS transition candidates */
++		reason = 7;
++		goto candidate_remove;
++	}
++
++#ifdef CONFIG_RTW_80211R
++	if (rtw_ft_chk_flags(padapter, RTW_FT_BTM_ROAM)) {
++		/* Accept */
++		reason = 0;
++		goto under_survey;
++	}	
++#endif
++
++	if (((*req_mode) & DISASSOC_IMMINENT) == 0) {
++		/* Reject - Unspecified reject reason */
++		reason = 1;
++		goto candidate_remove;
++	}	
++
++	if (precvpriv->signal_strength_data.avg_val >= pmlmepriv->roam_rssi_threshold) {
++		reason = 1;
++		RTW_WNM_INFO("%s : Reject - under high roam rssi(%u, %u) \n",
++			__func__, precvpriv->signal_strength_data.avg_val,
++			pmlmepriv->roam_rssi_threshold);
++		goto candidate_remove;
++	}
++
++#ifdef CONFIG_RTW_80211R
++under_survey:	
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)) {
++		RTW_WNM_INFO("%s reject due to _FW_UNDER_SURVEY\n", __func__);
++		reason = 1;
++	}
++#endif
++
++candidate_remove:
++	if (reason !=0)
++		rtw_wnm_reset_btm_candidate(&pmlmepriv->nb_info);
++
++	return reason;
++}
++
++static u32 rtw_wnm_btm_candidates_offset_get(u8* pframe)
++{
++	u32 offset = 0;
++
++	if (!pframe)
++		return 0;
++
++	offset += 7;
++
++	/* BSS Termination Duration check */
++	if (wnm_btm_bss_term_inc(pframe))
++		offset += 12;
++
++	/* Session Information URL check*/
++	if (wnm_btm_ess_disassoc_im(pframe)) {
++		/*URL length field + URL variable length*/
++		offset = 1 + *(pframe + offset);
++	}
++
++	RTW_WNM_INFO("%s : hdr offset=%u\n", __func__, offset);
++	return offset;
++}
++
++static void rtw_wnm_btm_req_hdr_parsing(u8* pframe, struct btm_req_hdr *phdr)
++{
++	u8 *pos;
++	u32 offset = 0;
++
++	if (!pframe || !phdr)
++		return;
++
++	_rtw_memset(phdr, 0, sizeof(struct btm_req_hdr));
++	phdr->dialog_token = wnm_btm_dialog_token(pframe);
++	phdr->req_mode  = wnm_btm_req_mode(pframe);
++	phdr->disassoc_timer = wnm_btm_disassoc_timer(pframe);
++	phdr->validity_interval = wnm_btm_valid_interval(pframe);
++	if (wnm_btm_bss_term_inc(pframe)) {
++		pos = wnm_btm_term_duration_offset(pframe);
++		if (*pos == WNM_BTM_TERM_DUR_SUBEID) {
++			phdr->term_duration.id = *pos;
++			phdr->term_duration.len = *(pos + 1);
++			phdr->term_duration.tsf = *((u64*)(pos + 2));
++			phdr->term_duration.duration= *((u16*)(pos + 10));
++		} else
++			RTW_WNM_INFO("%s : invaild BSS Termination Duration content!\n", __func__);
++	}
++
++	RTW_WNM_INFO("WNM: req_mode(0x%02x), disassoc_timer(0x%04x), validity_interval(0x%02x)\n",
++		phdr->req_mode, phdr->disassoc_timer, phdr->validity_interval);
++	if (wnm_btm_bss_term_inc(pframe))
++		RTW_WNM_INFO("WNM: tsf(0x%llx), duration(0x%4x)\n",
++			phdr->term_duration.tsf, phdr->term_duration.duration);
++}
++
++u8 rtw_wnm_btm_reassoc_req(_adapter *padapter)
++{
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct roam_nb_info *pnb = &(pmlmepriv->nb_info);
++	u8 breassoc = _FALSE;
++
++	if (_rtw_memcmp(get_my_bssid(&(pmlmeinfo->network)),
++		pnb->roam_target_addr, ETH_ALEN)) {
++		RTW_WNM_INFO("%s : bss "MAC_FMT" found in roam_target "MAC_FMT"\n",
++			__func__, MAC_ARG(get_my_bssid(&(pmlmeinfo->network))),
++			MAC_ARG(pnb->roam_target_addr));
++
++		breassoc = _TRUE;
++	}
++
++	return breassoc;
++}
++
++void rtw_wnm_roam_scan_hdl(void *ctx)
++{
++	_adapter *padapter = (_adapter *)ctx;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++	if (rtw_is_scan_deny(padapter)) 
++		RTW_WNM_INFO("%s: roam scan would abort by scan_deny!\n", __func__);
++
++#ifdef CONFIG_RTW_80211R
++	if (rtw_ft_chk_flags(padapter, RTW_FT_BTM_ROAM)) {
++		pmlmepriv->need_to_roam = _TRUE;
++		rtw_set_to_roam(padapter, padapter->registrypriv.max_roaming_times);
++		RTW_WNM_INFO("%s : enable roaming\n", __func__);
++	}
++
++	rtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM);
++#endif
++}
++
++static void rtw_wnm_roam_scan(_adapter *padapter)
++{
++	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
++
++	if (rtw_is_scan_deny(padapter)) {
++		_cancel_timer_ex(&pnb->roam_scan_timer);
++		_set_timer(&pnb->roam_scan_timer, 1000);
++	} else
++		rtw_wnm_roam_scan_hdl((void *)padapter);
++}
++
++void rtw_wnm_disassoc_chk_hdl(void *ctx)
++{
++	_adapter *padapter = (_adapter *)ctx;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct roam_nb_info *pnb = &(pmlmepriv->nb_info);
++
++	RTW_WNM_INFO("%s : expired\n", __func__);
++	if (pnb->disassoc_waiting <= 0 ) {
++		RTW_WNM_INFO("%s : btm roam is interrupted by disassoc\n", __func__);
++		return;
++	}
++
++	pnb->disassoc_waiting = _FALSE;
++	rtw_wnm_roam_scan(padapter);
++}
++
++u8 rtw_wnm_try_btm_roam_imnt(_adapter *padapter)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct roam_nb_info *pnb = &(pmlmepriv->nb_info);
++	struct btm_rpt_cache *pcache = &(pnb->btm_cache);
++	u8 reason = 0, flag = 0;
++
++	if (!rtw_wnm_btm_preference_cap(padapter)) {
++		RTW_WNM_INFO("%s : no btm candidate can be used!\n", __func__);
++		return 1;
++	}
++
++	flag = BIT(0) | BIT(1);
++	if (!rtw_wnm_btm_candidate_validity(pcache, flag))
++		return 1;
++
++#ifdef CONFIG_RTW_MBO
++	if (!rtw_mbo_wifi_logo_test(padapter)
++		&& !(pcache->req_mode & DISASSOC_IMMINENT)) {
++		RTW_WNM_INFO("%s : non-disassoc imminet req\n",  __func__);
++		return 1;
++	}
++#endif
++
++	RTW_WNM_INFO("%s : disassoc_waiting(%d)\n", __func__, pnb->disassoc_waiting);
++	if (pnb->disassoc_waiting) {
++		_cancel_timer_ex(&pnb->disassoc_chk_timer);
++		pnb->disassoc_waiting = _FALSE;
++		rtw_wnm_roam_scan_hdl((void *)padapter);
++	} else if (!pnb->disassoc_waiting)
++		RTW_WNM_INFO("%s : waiting for btm roaming start/finish\n", __func__);
++	else
++		reason = 1;
++
++	return reason;
++}
++
++void rtw_wnm_process_btm_req(_adapter *padapter, u8* pframe, u32 frame_len)
++{
++	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
++	struct btm_req_hdr req_hdr;
++	u8 *ptr, reason;
++	u32 elem_len, offset;
++
++	rtw_wnm_btm_req_hdr_parsing(pframe, &req_hdr);
++	offset = rtw_wnm_btm_candidates_offset_get(pframe);
++	if (offset == 0)
++		return;
++
++	if ((frame_len - offset) <= 15) {
++		RTW_INFO("WNM : Reject - no suitable BSS transition candidates!\n");
++		rtw_wnm_issue_action(padapter, 
++			RTW_WLAN_ACTION_WNM_BTM_RSP, 7, req_hdr.dialog_token);
++		return;
++	}
++
++	rtw_wmn_btm_cache_update(padapter, &req_hdr);
++
++	ptr = (pframe + offset);
++	elem_len = (frame_len - offset);
++	rtw_wnm_btm_candidates_survey(padapter, ptr, elem_len, _TRUE);
++	reason = rtw_wmn_btm_rsp_reason_decision(padapter, &pframe[3]);
++
++#ifdef CONFIG_RTW_MBO
++	/* for wifi-test; AP2 could power-off when BTM-req received */
++	if ((reason > 0) && (rtw_mbo_wifi_logo_test(padapter))) {
++		_rtw_memcpy(pnb->roam_target_addr, pnb->nb_rpt[0].bssid, ETH_ALEN);
++		RTW_WNM_INFO("%s : used report 0 as roam_target_addr(reason=%u)\n",
++			__func__, reason);
++		reason = 0;
++		pnb->preference_en = _TRUE;
++		pnb->nb_rpt_valid = _FALSE;
++	}
++#endif
++
++	rtw_wnm_issue_action(padapter, 
++		RTW_WLAN_ACTION_WNM_BTM_RSP, reason, req_hdr.dialog_token);
++
++	if (reason == 0) {
++		pnb->disassoc_waiting = _TRUE;
++		_set_timer(&pnb->disassoc_chk_timer, wnm_disassoc_wait_time);
++	}
++
++}
++
++void rtw_wnm_reset_btm_candidate(struct roam_nb_info *pnb)
++{
++	pnb->preference_en = _FALSE;
++	_rtw_memset(pnb->roam_target_addr, 0, ETH_ALEN);
++}
++
++void rtw_wnm_reset_btm_cache(_adapter *padapter)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct roam_nb_info *pnb = &(pmlmepriv->nb_info);
++	struct btm_rpt_cache *pcache = &(pnb->btm_cache);
++	u8 flag = 0;
++
++	flag |= BIT(0);
++	if (rtw_wnm_btm_candidate_validity(pcache, flag))
++		return;
++
++	rtw_wnm_reset_btm_candidate(pnb);
++	_rtw_memset(pcache, 0, sizeof(struct btm_rpt_cache));
++	pcache->validity_time = wnm_defualt_validity_time;
++	pcache->disassoc_time= wnm_default_disassoc_time;
++
++#ifdef CONFIG_RTW_80211R
++	if (rtw_ft_chk_flags(padapter, RTW_FT_BTM_ROAM)) {
++		pmlmepriv->need_to_roam = _FALSE;
++		rtw_set_to_roam(padapter, 0);
++		RTW_WNM_INFO("%s : disabled roaming\n", __func__);
++	}
++#endif
++}
++
++void rtw_wnm_reset_btm_state(_adapter *padapter)
++{
++	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
++
++	pnb->last_nb_rpt_entries = 0;
++	pnb->nb_rpt_is_same = _TRUE;
++	pnb->nb_rpt_valid = _FALSE;
++	pnb->nb_rpt_ch_list_num = 0;
++	pnb->disassoc_waiting = -1;
++	_rtw_memset(&pnb->nb_rpt, 0, sizeof(pnb->nb_rpt));
++	_rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list));
++	rtw_wnm_reset_btm_cache(padapter);
++}
++
++void rtw_wnm_issue_action(_adapter *padapter, u8 action, u8 reason, u8 dialog)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct xmit_frame *pmgntframe;
++	struct rtw_ieee80211_hdr *pwlanhdr;
++	struct pkt_attrib *pattrib;
++	u8 category, termination_delay, *pframe, dialog_token = 0;
++#ifdef CONFIG_RTW_MBO
++	u8 mbo_trans_rej_res = 1;  /* Unspecified reason */
++	u8 mbo_notif_req_type ;
++#endif
++	u16 *fctrl;
++
++	if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
++		return ;
++	
++	pattrib = &(pmgntframe->attrib);
++	update_mgntframe_attrib(padapter, pattrib);
++	_rtw_memset(pmgntframe->buf_addr, 0, (WLANHDR_OFFSET + TXDESC_OFFSET));
++
++	pframe = (u8 *)(pmgntframe->buf_addr + TXDESC_OFFSET);
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	category = RTW_WLAN_CATEGORY_WNM;
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++
++	switch (action) {
++		case RTW_WLAN_ACTION_WNM_BTM_QUERY:
++			dialog_token++;
++			pframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen));
++			pframe = rtw_set_fixed_ie(pframe, 1, &(reason), &(pattrib->pktlen));
++			RTW_INFO("WNM: BSS Transition Management Query sent\n");
++			break;
++		case RTW_WLAN_ACTION_WNM_BTM_RSP:
++			dialog_token = dialog;
++			termination_delay = 0;
++			pframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen));
++			pframe = rtw_set_fixed_ie(pframe, 1, &(reason), &(pattrib->pktlen));
++			pframe = rtw_set_fixed_ie(pframe, 1, &(termination_delay), &(pattrib->pktlen));
++			if (!reason && !is_zero_mac_addr(pmlmepriv->nb_info.roam_target_addr)) {
++				pframe = rtw_set_fixed_ie(pframe, 6, 
++					pmlmepriv->nb_info.roam_target_addr, &(pattrib->pktlen));
++			}
++
++#ifdef CONFIG_RTW_MBO
++			rtw_mbo_build_trans_reject_reason_attr(padapter, 
++				&pframe, pattrib, &mbo_trans_rej_res);
++#endif
++
++			RTW_INFO("WNM: BSS Transition Management Response sent(reason:%d)\n", reason);			
++			break;
++		case RTW_WLAN_ACTION_WNM_NOTIF_REQ:
++#ifdef CONFIG_RTW_MBO			
++			dialog_token++;
++			mbo_notif_req_type = WLAN_EID_VENDOR_SPECIFIC;
++			pframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen));
++			pframe = rtw_set_fixed_ie(pframe, 1, &(mbo_notif_req_type), &(pattrib->pktlen));
++			rtw_mbo_build_wnm_notification(padapter, &pframe, pattrib);
++			RTW_INFO("WNM: Notification request sent\n");
++#endif
++			break;
++		default:
++			goto exit;
++	}	
++	
++	pattrib->last_txcmdsz = pattrib->pktlen;
++	dump_mgntframe(padapter, pmgntframe);
++
++exit:	
++	return;
++}
++
++/* argument req_ie@cfg80211_roamed()/cfg80211_connect_result()
++	is association request IEs format. if driver used reassoc-req format,
++	RSN IE could not be parsed @supplicant process */
++void rtw_wnm_update_reassoc_req_ie(_adapter *padapter)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	u32 dup_len, offset;
++	u8 *pdup;
++
++	if (!pmlmepriv->assoc_req || !pmlmepriv->assoc_req_len)
++		return;
++
++	/* total len is assoc req len without Current AP Field*/
++	dup_len = pmlmepriv->assoc_req_len - ETH_ALEN;
++
++	/* offset is a len of 80211 header +  capability(2B) + listen interval(2B) */
++	offset =  sizeof(struct rtw_ieee80211_hdr_3addr) + 4;
++
++	pdup = rtw_zmalloc(dup_len);
++	if (pdup) {
++		/* remove Current AP Field @reassoc req IE */
++		_rtw_memcpy(pdup, pmlmepriv->assoc_req, offset);
++		_rtw_memcpy(pdup + offset, pmlmepriv->assoc_req + offset + ETH_ALEN,
++				pmlmepriv->assoc_req_len - offset);
++		rtw_buf_update(&pmlmepriv->assoc_req,
++			&pmlmepriv->assoc_req_len, pdup, dup_len);
++		rtw_mfree(pdup, dup_len);
++	}
++}
++#endif /* CONFIG_RTW_WNM */
++
++#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
++void rtw_roam_nb_info_init(_adapter *padapter)
++{
++	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
++	struct btm_rpt_cache *pcache = &(pnb->btm_cache);
++	
++	_rtw_memset(&pnb->nb_rpt, 0, sizeof(pnb->nb_rpt));
++	_rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list));
++	_rtw_memset(&pnb->roam_target_addr, 0, ETH_ALEN);
++	pnb->nb_rpt_valid = _FALSE;
++	pnb->nb_rpt_ch_list_num = 0;
++	pnb->preference_en = _FALSE;
++	pnb->nb_rpt_is_same = _TRUE;
++	pnb->last_nb_rpt_entries = 0;
++	pnb->disassoc_waiting = -1;
++#ifdef CONFIG_RTW_WNM
++	rtw_init_timer(&pnb->roam_scan_timer, 
++		padapter, rtw_wnm_roam_scan_hdl, 
++		padapter);
++	rtw_init_timer(&pnb->disassoc_chk_timer,
++		padapter, rtw_wnm_disassoc_chk_hdl,
++		padapter);
++
++	_rtw_memset(pcache, 0, sizeof(struct btm_rpt_cache));
++	pcache->validity_time = wnm_defualt_validity_time;
++	pcache->disassoc_time= wnm_default_disassoc_time ;
++#endif
++}
++
++u8 rtw_roam_nb_scan_list_set(
++	_adapter *padapter, struct sitesurvey_parm *pparm)
++{
++	u8 ret = _FALSE;
++	u32 i;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct roam_nb_info *pnb = &(pmlmepriv->nb_info);
++
++#ifdef CONFIG_RTW_80211R
++	if (!rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)
++		&& !rtw_ft_chk_flags(padapter, RTW_FT_BTM_ROAM))
++		return ret;
++#endif
++
++	if (!pmlmepriv->need_to_roam)
++		return ret;
++
++	if ((!pmlmepriv->nb_info.nb_rpt_valid) || (!pnb->nb_rpt_ch_list_num))
++		return ret;
++
++	if (!pparm)
++		return ret;
++
++	rtw_init_sitesurvey_parm(padapter, pparm);
++	if (rtw_roam_busy_scan(padapter, pnb)) {
++		pparm->ch_num = 1;
++		pparm->ch[pmlmepriv->ch_cnt].hw_value = 
++			pnb->nb_rpt_ch_list[pmlmepriv->ch_cnt].hw_value;
++		pmlmepriv->ch_cnt++;
++		ret = _TRUE;
++
++		RTW_WNM_INFO("%s: ch_cnt=%u, (%u)hw_value=%u\n",
++			__func__, pparm->ch_num, pmlmepriv->ch_cnt,
++			pparm->ch[pmlmepriv->ch_cnt].hw_value);
++
++		if (pmlmepriv->ch_cnt == pnb->nb_rpt_ch_list_num) {
++			pmlmepriv->nb_info.nb_rpt_valid = _FALSE;
++			pmlmepriv->ch_cnt = 0;
++		}
++		goto set_bssid_list;
++	}
++
++	pparm->ch_num = (pnb->nb_rpt_ch_list_num > RTW_CHANNEL_SCAN_AMOUNT)?
++		(RTW_CHANNEL_SCAN_AMOUNT):(pnb->nb_rpt_ch_list_num);
++	for (i=0; i<pparm->ch_num; i++) {
++		pparm->ch[i].hw_value = pnb->nb_rpt_ch_list[i].hw_value;
++		pparm->ch[i].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN;
++	}
++
++	pmlmepriv->nb_info.nb_rpt_valid = _FALSE;
++	pmlmepriv->ch_cnt = 0;		
++	ret = _TRUE;
++
++set_bssid_list:
++	rtw_set_802_11_bssid_list_scan(padapter, pparm);
++	return ret;
++}
++
++static u8 rtw_wnm_nb_elem_parsing(
++	u8* pdata, u32 data_len, u8 from_btm, 
++	u32 *nb_rpt_num, u8 *nb_rpt_is_same,
++	struct roam_nb_info *pnb, struct wnm_btm_cant *pcandidates)
++{
++	u8 bfound = _FALSE, ret = _SUCCESS;
++	u8 *ptr, *pend, *op;
++	u32 elem_len, subelem_len, op_len;
++	u32 i, nb_rpt_entries = 0;
++	struct nb_rpt_hdr *pie;
++	struct wnm_btm_cant *pcandidate;
++
++	if ((!pdata) || (!pnb))
++		return _FAIL;
++
++	if ((from_btm) && (!pcandidates))
++		return _FAIL;
++
++	ptr = pdata;
++	pend = ptr + data_len;
++	elem_len = data_len;
++	subelem_len = (u32)*(pdata+1);
++
++	for (i=0; i < RTW_MAX_NB_RPT_NUM; i++) {
++		if (((ptr + 7) > pend) || (elem_len < subelem_len)) 
++			break;
++
++		if (*ptr != RTW_WLAN_ACTION_WNM_NB_RPT_ELEM) {
++			RTW_WNM_INFO("WNM: end of data(0x%2x)!\n", *ptr);
++			break;
++		}
++
++		pie = (struct nb_rpt_hdr *)ptr;		
++		if (from_btm) {
++			op = rtw_get_ie((u8 *)(ptr+15), 
++				WNM_BTM_CAND_PREF_SUBEID, 
++				&op_len, (subelem_len - 15));
++		}
++
++		ptr = (u8 *)(ptr + subelem_len + 2);
++		elem_len -= (subelem_len +2);
++		subelem_len = *(ptr+1);
++		if (from_btm) {
++			pcandidate = (pcandidates + i);
++			_rtw_memcpy(&pcandidate->nb_rpt, pie, sizeof(struct nb_rpt_hdr));
++			if (op && (op_len !=0)) {
++				pcandidate->preference = *(op + 2);
++				bfound = _TRUE;
++			} else
++				pcandidate->preference = 0;
++
++			RTW_WNM_INFO("WNM: preference check bssid("MAC_FMT
++				") ,bss_info(0x%04X), reg_class(0x%02X), ch(%d),"
++				" phy_type(0x%02X), preference(0x%02X)\n",
++				MAC_ARG(pcandidate->nb_rpt.bssid), pcandidate->nb_rpt.bss_info, 
++				pcandidate->nb_rpt.reg_class, pcandidate->nb_rpt.ch_num, 
++				pcandidate->nb_rpt.phy_type, pcandidate->preference);
++		} else {
++			if (_rtw_memcmp(&pnb->nb_rpt[i], pie, sizeof(struct nb_rpt_hdr)) == _FALSE)
++				*nb_rpt_is_same = _FALSE;
++			_rtw_memcpy(&pnb->nb_rpt[i], pie, sizeof(struct nb_rpt_hdr));
++		}
++		nb_rpt_entries++;			
++	} 
++
++	if (from_btm) 
++		pnb->preference_en = (bfound)?_TRUE:_FALSE; 
++
++	*nb_rpt_num = nb_rpt_entries;
++	return ret;
++}	
++
++/* selection sorting based on preference value
++ * IN : 		nb_rpt_entries - candidate num
++ * IN/OUT :	pcandidates	- candidate list
++ * return : TRUE - means pcandidates is updated.  
++ */
++static u8 rtw_wnm_candidates_sorting(
++	u32 nb_rpt_entries, struct wnm_btm_cant *pcandidates)
++{
++	u8 updated = _FALSE;
++	u32 i, j, pos;
++	struct wnm_btm_cant swap;
++	struct wnm_btm_cant *pcant_1, *pcant_2;
++
++	if ((!nb_rpt_entries) || (!pcandidates))
++		return updated;
++
++	for (i=0; i < (nb_rpt_entries - 1); i++) {
++		pos = i;
++		for (j=(i + 1); j < nb_rpt_entries; j++) {
++			pcant_1 = pcandidates+pos;
++			pcant_2 = pcandidates+j;
++			if ((pcant_1->preference) < (pcant_2->preference))
++				pos = j;
++		}
++
++		if (pos != i) {
++			updated = _TRUE;
++			_rtw_memcpy(&swap, (pcandidates+i), sizeof(struct wnm_btm_cant));
++			_rtw_memcpy((pcandidates+i), (pcandidates+pos), sizeof(struct wnm_btm_cant));
++			_rtw_memcpy((pcandidates+pos), &swap, sizeof(struct wnm_btm_cant));
++		}
++	}	
++	return updated;
++}	
++
++static void rtw_wnm_nb_info_update(
++	u32 nb_rpt_entries, u8 from_btm, 
++	struct roam_nb_info *pnb, struct wnm_btm_cant *pcandidates, 
++	u8 *nb_rpt_is_same)
++{
++	u8 is_found;
++	u32 i, j;
++	struct wnm_btm_cant *pcand;
++
++	if (!pnb)
++		return;
++
++	pnb->nb_rpt_ch_list_num = 0;
++	for (i=0; i<nb_rpt_entries; i++) {
++		is_found = _FALSE;
++		if (from_btm) {
++			pcand = (pcandidates+i);
++			if (_rtw_memcmp(&pnb->nb_rpt[i], &pcand->nb_rpt,
++					sizeof(struct nb_rpt_hdr)) == _FALSE)
++				*nb_rpt_is_same = _FALSE;
++			_rtw_memcpy(&pnb->nb_rpt[i], &pcand->nb_rpt, sizeof(struct nb_rpt_hdr));
++		}
++
++		RTW_WNM_INFO("WNM: bssid(" MAC_FMT
++			") , bss_info(0x%04X), reg_class(0x%02X), ch_num(%d), phy_type(0x%02X)\n",
++			MAC_ARG(pnb->nb_rpt[i].bssid), pnb->nb_rpt[i].bss_info, 
++			pnb->nb_rpt[i].reg_class, pnb->nb_rpt[i].ch_num, 
++			pnb->nb_rpt[i].phy_type);
++
++		if (pnb->nb_rpt[i].ch_num == 0)
++			continue;
++
++		for (j=0; j<nb_rpt_entries; j++) {
++			if (pnb->nb_rpt[i].ch_num == pnb->nb_rpt_ch_list[j].hw_value) {
++				is_found = _TRUE;
++				break;
++			}
++		}
++							
++		if (!is_found) {
++			pnb->nb_rpt_ch_list[pnb->nb_rpt_ch_list_num].hw_value = pnb->nb_rpt[i].ch_num;
++				pnb->nb_rpt_ch_list_num++;
++		}
++	}
++}
++
++static void rtw_wnm_btm_candidate_select(_adapter *padapter)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
++	struct wlan_network *pnetwork;
++	u8 bfound = _FALSE;
++	u8 ignore_currrent = _FALSE;
++	u32 i;
++
++#ifdef CONFIG_RTW_80211R
++	if (rtw_ft_chk_flags(padapter, RTW_FT_BTM_ROAM))
++		ignore_currrent = _TRUE;
++#endif
++
++	for (i = 0; i < pnb->last_nb_rpt_entries; i++) {
++		if (ignore_currrent &&
++			(_rtw_memcmp(pnb->nb_rpt[i].bssid,\
++				padapter->mlmepriv.cur_network.network.MacAddress, ETH_ALEN))) {
++			RTW_WNM_INFO("WNM : ignore candidate "MAC_FMT" for it's connected(%u)!\n",
++					MAC_ARG(pnb->nb_rpt[i].bssid), i);	
++			continue;
++		}
++		
++		pnetwork = rtw_find_network(
++				&(pmlmepriv->scanned_queue), 
++				pnb->nb_rpt[i].bssid);
++
++		if (pnetwork) {
++			bfound = _TRUE;
++			break;
++		}
++	}
++
++	if (bfound) {
++		_rtw_memcpy(pnb->roam_target_addr, pnb->nb_rpt[i].bssid, ETH_ALEN);
++		RTW_INFO("WNM : select btm entry(%d) - %s("MAC_FMT", ch:%u) rssi:%d\n"
++			, i
++			, pnetwork->network.Ssid.Ssid
++			, MAC_ARG(pnetwork->network.MacAddress)
++			, pnetwork->network.Configuration.DSConfig
++			, (int)pnetwork->network.Rssi);
++	} else 
++		_rtw_memset(pnb->roam_target_addr,0, ETH_ALEN);
++}
++
++u32 rtw_wnm_btm_candidates_survey(
++	_adapter *padapter, u8* pframe, u32 elem_len, u8 from_btm)
++{
++	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
++	struct wnm_btm_cant *pcandidate_list = NULL;
++	u8 nb_rpt_is_same = _TRUE;
++	u32	ret = _FAIL;
++	u32 nb_rpt_entries = 0;	
++
++	if (from_btm) {
++		u32 mlen = sizeof(struct wnm_btm_cant) * RTW_MAX_NB_RPT_NUM;
++		pcandidate_list = (struct wnm_btm_cant *)rtw_malloc(mlen);
++		if (pcandidate_list == NULL) 
++			goto exit;				
++	}
++
++	/*clean the status set last time*/
++	_rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list));
++	pnb->nb_rpt_valid = _FALSE;
++	if (!rtw_wnm_nb_elem_parsing(
++			pframe, elem_len, from_btm, 
++			&nb_rpt_entries, &nb_rpt_is_same,
++			pnb, pcandidate_list))
++		goto exit;
++
++	if (nb_rpt_entries != 0) {
++		if ((from_btm) && (rtw_wnm_btm_preference_cap(padapter)))
++			rtw_wnm_candidates_sorting(nb_rpt_entries, pcandidate_list);
++
++		rtw_wnm_nb_info_update(
++			nb_rpt_entries, from_btm, 
++			pnb, pcandidate_list, &nb_rpt_is_same);
++	}
++
++	RTW_WNM_INFO("nb_rpt_is_same = %d, nb_rpt_entries = %d, last_nb_rpt_entries = %d\n",
++		nb_rpt_is_same, nb_rpt_entries, pnb->last_nb_rpt_entries);
++	if ((nb_rpt_is_same == _TRUE) && (nb_rpt_entries == pnb->last_nb_rpt_entries))
++		pnb->nb_rpt_is_same = _TRUE;
++	else {
++		pnb->nb_rpt_is_same = _FALSE;
++		pnb->last_nb_rpt_entries = nb_rpt_entries;
++	}
++
++	if ((from_btm) && (nb_rpt_entries != 0))
++		rtw_wnm_btm_candidate_select(padapter);
++	
++	pnb->nb_rpt_valid = _TRUE;
++	ret = _SUCCESS;
++
++exit:
++	if (from_btm && pcandidate_list)
++		rtw_mfree((u8 *)pcandidate_list, sizeof(struct wnm_btm_cant) * RTW_MAX_NB_RPT_NUM);
++	
++	return ret;
++}
++
++#endif /*defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_xmit.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_xmit.c
+new file mode 100644
+index 000000000..09df1b65e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/rtw_xmit.c
+@@ -0,0 +1,6338 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_XMIT_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++static u8 P802_1H_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0xf8 };
++static u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 };
++
++static void _init_txservq(struct tx_servq *ptxservq)
++{
++	_rtw_init_listhead(&ptxservq->tx_pending);
++	_rtw_init_queue(&ptxservq->sta_pending);
++	ptxservq->qcnt = 0;
++}
++
++
++void	_rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv)
++{
++
++
++	_rtw_memset((unsigned char *)psta_xmitpriv, 0, sizeof(struct sta_xmit_priv));
++
++	_rtw_spinlock_init(&psta_xmitpriv->lock);
++
++	/* for(i = 0 ; i < MAX_NUMBLKS; i++) */
++	/*	_init_txservq(&(psta_xmitpriv->blk_q[i])); */
++
++	_init_txservq(&psta_xmitpriv->be_q);
++	_init_txservq(&psta_xmitpriv->bk_q);
++	_init_txservq(&psta_xmitpriv->vi_q);
++	_init_txservq(&psta_xmitpriv->vo_q);
++	_rtw_init_listhead(&psta_xmitpriv->legacy_dz);
++	_rtw_init_listhead(&psta_xmitpriv->apsd);
++
++
++}
++
++void rtw_init_xmit_block(_adapter *padapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++	_rtw_spinlock_init(&dvobj->xmit_block_lock);
++	dvobj->xmit_block = XMIT_BLOCK_NONE;
++
++}
++void rtw_free_xmit_block(_adapter *padapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++	_rtw_spinlock_free(&dvobj->xmit_block_lock);
++}
++
++s32	_rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter)
++{
++	int i;
++	struct xmit_buf *pxmitbuf;
++	struct xmit_frame *pxframe;
++	sint	res = _SUCCESS;
++
++
++	/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
++	/* _rtw_memset((unsigned char *)pxmitpriv, 0, sizeof(struct xmit_priv)); */
++
++	_rtw_spinlock_init(&pxmitpriv->lock);
++	_rtw_spinlock_init(&pxmitpriv->lock_sctx);
++	_rtw_init_sema(&pxmitpriv->xmit_sema, 0);
++
++	/*
++	Please insert all the queue initializaiton using _rtw_init_queue below
++	*/
++
++	pxmitpriv->adapter = padapter;
++
++	/* for(i = 0 ; i < MAX_NUMBLKS; i++) */
++	/*	_rtw_init_queue(&pxmitpriv->blk_strms[i]); */
++
++	_rtw_init_queue(&pxmitpriv->be_pending);
++	_rtw_init_queue(&pxmitpriv->bk_pending);
++	_rtw_init_queue(&pxmitpriv->vi_pending);
++	_rtw_init_queue(&pxmitpriv->vo_pending);
++	_rtw_init_queue(&pxmitpriv->bm_pending);
++
++	/* _rtw_init_queue(&pxmitpriv->legacy_dz_queue); */
++	/* _rtw_init_queue(&pxmitpriv->apsd_queue); */
++
++	_rtw_init_queue(&pxmitpriv->free_xmit_queue);
++
++	/*
++	Please allocate memory with the sz = (struct xmit_frame) * NR_XMITFRAME,
++	and initialize free_xmit_frame below.
++	Please also apply  free_txobj to link_up all the xmit_frames...
++	*/
++
++	pxmitpriv->pallocated_frame_buf = rtw_zvmalloc(NR_XMITFRAME * sizeof(struct xmit_frame) + 4);
++
++	if (pxmitpriv->pallocated_frame_buf  == NULL) {
++		pxmitpriv->pxmit_frame_buf = NULL;
++		res = _FAIL;
++		goto exit;
++	}
++	pxmitpriv->pxmit_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_frame_buf), 4);
++	/* pxmitpriv->pxmit_frame_buf = pxmitpriv->pallocated_frame_buf + 4 - */
++	/*						((SIZE_PTR) (pxmitpriv->pallocated_frame_buf) &3); */
++
++	pxframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;
++
++	for (i = 0; i < NR_XMITFRAME; i++) {
++		_rtw_init_listhead(&(pxframe->list));
++
++		pxframe->padapter = padapter;
++		pxframe->frame_tag = NULL_FRAMETAG;
++
++		pxframe->pkt = NULL;
++
++		pxframe->buf_addr = NULL;
++		pxframe->pxmitbuf = NULL;
++
++		rtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xmit_queue.queue));
++
++		pxframe++;
++	}
++
++	pxmitpriv->free_xmitframe_cnt = NR_XMITFRAME;
++
++	pxmitpriv->frag_len = MAX_FRAG_THRESHOLD;
++
++
++	/* init xmit_buf */
++	_rtw_init_queue(&pxmitpriv->free_xmitbuf_queue);
++	_rtw_init_queue(&pxmitpriv->pending_xmitbuf_queue);
++
++	pxmitpriv->pallocated_xmitbuf = rtw_zvmalloc(NR_XMITBUFF * sizeof(struct xmit_buf) + 4);
++
++	if (pxmitpriv->pallocated_xmitbuf  == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pxmitpriv->pxmitbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmitbuf), 4);
++	/* pxmitpriv->pxmitbuf = pxmitpriv->pallocated_xmitbuf + 4 - */
++	/*						((SIZE_PTR) (pxmitpriv->pallocated_xmitbuf) &3); */
++
++	pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;
++
++	for (i = 0; i < NR_XMITBUFF; i++) {
++		_rtw_init_listhead(&pxmitbuf->list);
++
++		pxmitbuf->priv_data = NULL;
++		pxmitbuf->padapter = padapter;
++		pxmitbuf->buf_tag = XMITBUF_DATA;
++
++		/* Tx buf allocation may fail sometimes, so sleep and retry. */
++		res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE);
++		if (res == _FAIL) {
++			rtw_msleep_os(10);
++			res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE);
++			if (res == _FAIL)
++				goto exit;
++		}
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++		pxmitbuf->phead = pxmitbuf->pbuf;
++		pxmitbuf->pend = pxmitbuf->pbuf + MAX_XMITBUF_SZ;
++		pxmitbuf->len = 0;
++		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
++#endif
++
++		pxmitbuf->flags = XMIT_VO_QUEUE;
++
++		rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmitbuf_queue.queue));
++#ifdef DBG_XMIT_BUF
++		pxmitbuf->no = i;
++#endif
++
++		pxmitbuf++;
++
++	}
++
++	pxmitpriv->free_xmitbuf_cnt = NR_XMITBUFF;
++
++	/* init xframe_ext queue,  the same count as extbuf */
++	_rtw_init_queue(&pxmitpriv->free_xframe_ext_queue);
++
++	pxmitpriv->xframe_ext_alloc_addr = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_frame) + 4);
++
++	if (pxmitpriv->xframe_ext_alloc_addr  == NULL) {
++		pxmitpriv->xframe_ext = NULL;
++		res = _FAIL;
++		goto exit;
++	}
++	pxmitpriv->xframe_ext = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->xframe_ext_alloc_addr), 4);
++	pxframe = (struct xmit_frame *)pxmitpriv->xframe_ext;
++
++	for (i = 0; i < NR_XMIT_EXTBUFF; i++) {
++		_rtw_init_listhead(&(pxframe->list));
++
++		pxframe->padapter = padapter;
++		pxframe->frame_tag = NULL_FRAMETAG;
++
++		pxframe->pkt = NULL;
++
++		pxframe->buf_addr = NULL;
++		pxframe->pxmitbuf = NULL;
++
++		pxframe->ext_tag = 1;
++
++		rtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xframe_ext_queue.queue));
++
++		pxframe++;
++	}
++	pxmitpriv->free_xframe_ext_cnt = NR_XMIT_EXTBUFF;
++
++	/* Init xmit extension buff */
++	_rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue);
++
++	pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4);
++
++	if (pxmitpriv->pallocated_xmit_extbuf  == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4);
++
++	pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
++
++	for (i = 0; i < NR_XMIT_EXTBUFF; i++) {
++		_rtw_init_listhead(&pxmitbuf->list);
++
++		pxmitbuf->priv_data = NULL;
++		pxmitbuf->padapter = padapter;
++		pxmitbuf->buf_tag = XMITBUF_MGNT;
++
++		res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, MAX_XMIT_EXTBUF_SZ + XMITBUF_ALIGN_SZ, _TRUE);
++		if (res == _FAIL) {
++			res = _FAIL;
++			goto exit;
++		}
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++		pxmitbuf->phead = pxmitbuf->pbuf;
++		pxmitbuf->pend = pxmitbuf->pbuf + MAX_XMIT_EXTBUF_SZ;
++		pxmitbuf->len = 0;
++		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
++#endif
++
++		rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue));
++#ifdef DBG_XMIT_BUF_EXT
++		pxmitbuf->no = i;
++#endif
++		pxmitbuf++;
++
++	}
++
++	pxmitpriv->free_xmit_extbuf_cnt = NR_XMIT_EXTBUFF;
++
++	for (i = 0; i < CMDBUF_MAX; i++) {
++		pxmitbuf = &pxmitpriv->pcmd_xmitbuf[i];
++		if (pxmitbuf) {
++			_rtw_init_listhead(&pxmitbuf->list);
++
++			pxmitbuf->priv_data = NULL;
++			pxmitbuf->padapter = padapter;
++			pxmitbuf->buf_tag = XMITBUF_CMD;
++
++			res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ, _TRUE);
++			if (res == _FAIL) {
++				res = _FAIL;
++				goto exit;
++			}
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++			pxmitbuf->phead = pxmitbuf->pbuf;
++			pxmitbuf->pend = pxmitbuf->pbuf + MAX_CMDBUF_SZ;
++			pxmitbuf->len = 0;
++			pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
++#endif
++			pxmitbuf->alloc_sz = MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ;
++		}
++	}
++
++	rtw_alloc_hwxmits(padapter);
++	rtw_init_hwxmits(pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);
++
++	for (i = 0; i < 4; i++)
++		pxmitpriv->wmm_para_seq[i] = i;
++
++#ifdef CONFIG_USB_HCI
++	pxmitpriv->txirp_cnt = 1;
++
++	_rtw_init_sema(&(pxmitpriv->tx_retevt), 0);
++
++	/* per AC pending irp */
++	pxmitpriv->beq_cnt = 0;
++	pxmitpriv->bkq_cnt = 0;
++	pxmitpriv->viq_cnt = 0;
++	pxmitpriv->voq_cnt = 0;
++#endif
++
++
++#ifdef CONFIG_XMIT_ACK
++	pxmitpriv->ack_tx = _FALSE;
++	_rtw_mutex_init(&pxmitpriv->ack_tx_mutex);
++	rtw_sctx_init(&pxmitpriv->ack_tx_ops, 0);
++#endif
++
++#ifdef CONFIG_TX_AMSDU
++	rtw_init_timer(&(pxmitpriv->amsdu_vo_timer), padapter,
++		rtw_amsdu_vo_timeout_handler, padapter);
++	pxmitpriv->amsdu_vo_timeout = RTW_AMSDU_TIMER_UNSET;
++
++	rtw_init_timer(&(pxmitpriv->amsdu_vi_timer), padapter,
++		rtw_amsdu_vi_timeout_handler, padapter);
++	pxmitpriv->amsdu_vi_timeout = RTW_AMSDU_TIMER_UNSET;
++
++	rtw_init_timer(&(pxmitpriv->amsdu_be_timer), padapter,
++		rtw_amsdu_be_timeout_handler, padapter);
++	pxmitpriv->amsdu_be_timeout = RTW_AMSDU_TIMER_UNSET;
++
++	rtw_init_timer(&(pxmitpriv->amsdu_bk_timer), padapter,
++		rtw_amsdu_bk_timeout_handler, padapter);
++	pxmitpriv->amsdu_bk_timeout = RTW_AMSDU_TIMER_UNSET;
++
++	pxmitpriv->amsdu_debug_set_timer = 0;
++	pxmitpriv->amsdu_debug_timeout = 0;
++	pxmitpriv->amsdu_debug_coalesce_one = 0;
++	pxmitpriv->amsdu_debug_coalesce_two = 0;
++#endif
++#ifdef DBG_TXBD_DESC_DUMP
++	pxmitpriv->dump_txbd_desc = 0;
++#endif
++	rtw_init_xmit_block(padapter);
++	rtw_hal_init_xmit_priv(padapter);
++
++exit:
++
++
++	return res;
++}
++
++void  rtw_mfree_xmit_priv_lock(struct xmit_priv *pxmitpriv);
++void  rtw_mfree_xmit_priv_lock(struct xmit_priv *pxmitpriv)
++{
++	_rtw_spinlock_free(&pxmitpriv->lock);
++	_rtw_free_sema(&pxmitpriv->xmit_sema);
++
++	_rtw_spinlock_free(&pxmitpriv->be_pending.lock);
++	_rtw_spinlock_free(&pxmitpriv->bk_pending.lock);
++	_rtw_spinlock_free(&pxmitpriv->vi_pending.lock);
++	_rtw_spinlock_free(&pxmitpriv->vo_pending.lock);
++	_rtw_spinlock_free(&pxmitpriv->bm_pending.lock);
++
++	/* _rtw_spinlock_free(&pxmitpriv->legacy_dz_queue.lock); */
++	/* _rtw_spinlock_free(&pxmitpriv->apsd_queue.lock); */
++
++	_rtw_spinlock_free(&pxmitpriv->free_xmit_queue.lock);
++	_rtw_spinlock_free(&pxmitpriv->free_xmitbuf_queue.lock);
++	_rtw_spinlock_free(&pxmitpriv->pending_xmitbuf_queue.lock);
++}
++
++
++void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv)
++{
++	int i;
++	_adapter *padapter = pxmitpriv->adapter;
++	struct xmit_frame	*pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;
++	struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;
++
++
++	rtw_hal_free_xmit_priv(padapter);
++
++	rtw_mfree_xmit_priv_lock(pxmitpriv);
++
++	if (pxmitpriv->pxmit_frame_buf == NULL)
++		goto out;
++
++	for (i = 0; i < NR_XMITFRAME; i++) {
++		rtw_os_xmit_complete(padapter, pxmitframe);
++
++		pxmitframe++;
++	}
++
++	for (i = 0; i < NR_XMITBUFF; i++) {
++		rtw_os_xmit_resource_free(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE);
++
++		pxmitbuf++;
++	}
++
++	if (pxmitpriv->pallocated_frame_buf)
++		rtw_vmfree(pxmitpriv->pallocated_frame_buf, NR_XMITFRAME * sizeof(struct xmit_frame) + 4);
++
++
++	if (pxmitpriv->pallocated_xmitbuf)
++		rtw_vmfree(pxmitpriv->pallocated_xmitbuf, NR_XMITBUFF * sizeof(struct xmit_buf) + 4);
++
++	/* free xframe_ext queue,  the same count as extbuf */
++	if ((pxmitframe = (struct xmit_frame *)pxmitpriv->xframe_ext)) {
++		for (i = 0; i < NR_XMIT_EXTBUFF; i++) {
++			rtw_os_xmit_complete(padapter, pxmitframe);
++			pxmitframe++;
++		}
++	}
++	if (pxmitpriv->xframe_ext_alloc_addr)
++		rtw_vmfree(pxmitpriv->xframe_ext_alloc_addr, NR_XMIT_EXTBUFF * sizeof(struct xmit_frame) + 4);
++	_rtw_spinlock_free(&pxmitpriv->free_xframe_ext_queue.lock);
++
++	/* free xmit extension buff */
++	_rtw_spinlock_free(&pxmitpriv->free_xmit_extbuf_queue.lock);
++
++	pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
++	for (i = 0; i < NR_XMIT_EXTBUFF; i++) {
++		rtw_os_xmit_resource_free(padapter, pxmitbuf, (MAX_XMIT_EXTBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE);
++
++		pxmitbuf++;
++	}
++
++	if (pxmitpriv->pallocated_xmit_extbuf)
++		rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4);
++
++	for (i = 0; i < CMDBUF_MAX; i++) {
++		pxmitbuf = &pxmitpriv->pcmd_xmitbuf[i];
++		if (pxmitbuf != NULL)
++			rtw_os_xmit_resource_free(padapter, pxmitbuf, MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ , _TRUE);
++	}
++
++	rtw_free_hwxmits(padapter);
++
++#ifdef CONFIG_XMIT_ACK
++	_rtw_mutex_free(&pxmitpriv->ack_tx_mutex);
++#endif
++	rtw_free_xmit_block(padapter);
++out:
++	return;
++}
++
++u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta)
++{
++	u8 bw;
++
++	bw = sta->cmn.bw_mode;
++	if (MLME_STATE(adapter) & WIFI_ASOC_STATE) {
++		if (adapter->mlmeextpriv.cur_channel <= 14)
++			bw = rtw_min(bw, ADAPTER_TX_BW_2G(adapter));
++		else
++			bw = rtw_min(bw, ADAPTER_TX_BW_5G(adapter));
++	}
++
++	return bw;
++}
++
++void rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u64 *r_bmp_vht)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++	u8 fix_bw = 0xFF;
++	u16 bmp_cck_ofdm = 0;
++	u32 bmp_ht = 0;
++	u64 bmp_vht = 0;
++	int i;
++
++	if (adapter->fix_rate != 0xFF && adapter->fix_bw != 0xFF)
++		fix_bw = adapter->fix_bw;
++
++	/* TODO: adapter->fix_rate */
++
++	for (i = 0; i < macid_ctl->num; i++) {
++		if (!rtw_macid_is_used(macid_ctl, i))
++			continue;
++		if (!rtw_macid_is_iface_specific(macid_ctl, i, adapter))
++			continue;
++
++		if (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */
++			bmp_cck_ofdm |= macid_ctl->rate_bmp0[i] & 0x00000FFF;
++
++		/* bypass mismatch bandwidth for HT, VHT */
++		if ((fix_bw != 0xFF && fix_bw != bw) || (fix_bw == 0xFF && macid_ctl->bw[i] != bw))
++			continue;
++
++		if (macid_ctl->vht_en[i])
++			bmp_vht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);
++		else
++			bmp_ht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);
++	}
++
++	/* TODO: mlmeext->tx_rate*/
++
++	if (r_bmp_cck_ofdm)
++		*r_bmp_cck_ofdm = bmp_cck_ofdm;
++	if (r_bmp_ht)
++		*r_bmp_ht = bmp_ht;
++	if (r_bmp_vht)
++		*r_bmp_vht = bmp_vht;
++}
++
++void rtw_get_shared_macid_tx_rate_bmp_by_bw(struct dvobj_priv *dvobj, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u64 *r_bmp_vht)
++{
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++	u16 bmp_cck_ofdm = 0;
++	u32 bmp_ht = 0;
++	u64 bmp_vht = 0;
++	int i;
++
++	for (i = 0; i < macid_ctl->num; i++) {
++		if (!rtw_macid_is_used(macid_ctl, i))
++			continue;
++		if (!rtw_macid_is_iface_shared(macid_ctl, i))
++			continue;
++
++		if (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */
++			bmp_cck_ofdm |= macid_ctl->rate_bmp0[i] & 0x00000FFF;
++
++		/* bypass mismatch bandwidth for HT, VHT */
++		if (macid_ctl->bw[i] != bw)
++			continue;
++
++		if (macid_ctl->vht_en[i])
++			bmp_vht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);
++		else
++			bmp_ht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);
++	}
++
++	if (r_bmp_cck_ofdm)
++		*r_bmp_cck_ofdm = bmp_cck_ofdm;
++	if (r_bmp_ht)
++		*r_bmp_ht = bmp_ht;
++	if (r_bmp_vht)
++		*r_bmp_vht = bmp_vht;
++}
++
++void rtw_get_adapter_tx_rate_bmp(_adapter *adapter, u16 r_bmp_cck_ofdm[], u32 r_bmp_ht[], u64 r_bmp_vht[])
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	u8 bw;
++	u16 bmp_cck_ofdm, tmp_cck_ofdm;
++	u32 bmp_ht, tmp_ht;
++	u64 bmp_vht, tmp_vht;
++	int i;
++
++	for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) {
++		bmp_cck_ofdm = bmp_ht = bmp_vht = 0;
++		if (hal_is_bw_support(adapter, bw)) {
++			{
++				rtw_get_adapter_tx_rate_bmp_by_bw(adapter, bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht);
++				bmp_cck_ofdm |= tmp_cck_ofdm;
++				bmp_ht |= tmp_ht;
++				bmp_vht |= tmp_vht;
++			}
++			rtw_get_shared_macid_tx_rate_bmp_by_bw(dvobj, bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht);
++			bmp_cck_ofdm |= tmp_cck_ofdm;
++			bmp_ht |= tmp_ht;
++			bmp_vht |= tmp_vht;
++		}
++		if (bw == CHANNEL_WIDTH_20)
++			r_bmp_cck_ofdm[bw] = bmp_cck_ofdm;
++		if (bw <= CHANNEL_WIDTH_40)
++			r_bmp_ht[bw] = bmp_ht;
++		if (bw <= CHANNEL_WIDTH_160)
++			r_bmp_vht[bw] = bmp_vht;
++	}
++}
++
++void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj)
++{
++	struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
++	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	u8 bw;
++	u16 bmp_cck_ofdm, tmp_cck_ofdm;
++	u32 bmp_ht, tmp_ht, ori_bmp_ht[2];
++	u64 bmp_vht, tmp_vht, ori_bmp_vht[4];
++	int i;
++
++	for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) {
++		/* backup the original ht & vht bmp */
++		if (bw <= CHANNEL_WIDTH_40)
++			ori_bmp_ht[bw] = rf_ctl->rate_bmp_ht_by_bw[bw];
++		if (bw <= CHANNEL_WIDTH_160)
++			ori_bmp_vht[bw] = rf_ctl->rate_bmp_vht_by_bw[bw];
++
++		bmp_cck_ofdm = bmp_ht = bmp_vht = 0;
++		if (hal_is_bw_support(dvobj_get_primary_adapter(dvobj), bw)) {
++			for (i = 0; i < dvobj->iface_nums; i++) {
++				if (!dvobj->padapters[i])
++					continue;
++				rtw_get_adapter_tx_rate_bmp_by_bw(dvobj->padapters[i], bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht);
++				bmp_cck_ofdm |= tmp_cck_ofdm;
++				bmp_ht |= tmp_ht;
++				bmp_vht |= tmp_vht;
++			}
++			rtw_get_shared_macid_tx_rate_bmp_by_bw(dvobj, bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht);
++			bmp_cck_ofdm |= tmp_cck_ofdm;
++			bmp_ht |= tmp_ht;
++			bmp_vht |= tmp_vht;
++		}
++		if (bw == CHANNEL_WIDTH_20)
++			rf_ctl->rate_bmp_cck_ofdm = bmp_cck_ofdm;
++		if (bw <= CHANNEL_WIDTH_40)
++			rf_ctl->rate_bmp_ht_by_bw[bw] = bmp_ht;
++		if (bw <= CHANNEL_WIDTH_160)
++			rf_ctl->rate_bmp_vht_by_bw[bw] = bmp_vht;
++	}
++
++#if CONFIG_TXPWR_LIMIT
++#ifndef DBG_HIGHEST_RATE_BMP_BW_CHANGE
++#define DBG_HIGHEST_RATE_BMP_BW_CHANGE 0
++#endif
++
++	if (hal_data->txpwr_limit_loaded) {
++		u8 ori_highest_ht_rate_bw_bmp;
++		u8 ori_highest_vht_rate_bw_bmp;
++		u8 highest_rate_bw;
++		u8 highest_rate_bw_bmp;
++		u8 update_ht_rs = _FALSE;
++		u8 update_vht_rs = _FALSE;
++
++		/* backup the original ht & vht highest bw bmp */
++		ori_highest_ht_rate_bw_bmp = rf_ctl->highest_ht_rate_bw_bmp;
++		ori_highest_vht_rate_bw_bmp = rf_ctl->highest_vht_rate_bw_bmp;
++
++		highest_rate_bw_bmp = BW_CAP_20M;
++		highest_rate_bw = CHANNEL_WIDTH_20;
++		for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_40; bw++) {
++			if (rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw] < rf_ctl->rate_bmp_ht_by_bw[bw]) {
++				highest_rate_bw_bmp = ch_width_to_bw_cap(bw);
++				highest_rate_bw = bw;
++			} else if (rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw] == rf_ctl->rate_bmp_ht_by_bw[bw])
++				highest_rate_bw_bmp |= ch_width_to_bw_cap(bw);
++		}
++		rf_ctl->highest_ht_rate_bw_bmp = highest_rate_bw_bmp;
++
++		if (ori_highest_ht_rate_bw_bmp != rf_ctl->highest_ht_rate_bw_bmp
++			|| largest_bit(ori_bmp_ht[highest_rate_bw]) != largest_bit(rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw])
++		) {
++			if (DBG_HIGHEST_RATE_BMP_BW_CHANGE) {
++				RTW_INFO("highest_ht_rate_bw_bmp:0x%02x=>0x%02x\n", ori_highest_ht_rate_bw_bmp, rf_ctl->highest_ht_rate_bw_bmp);
++				RTW_INFO("rate_bmp_ht_by_bw[%u]:0x%08x=>0x%08x\n", highest_rate_bw, ori_bmp_ht[highest_rate_bw], rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw]);
++			}
++			if (rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw])
++				update_ht_rs = _TRUE;
++		}
++
++		highest_rate_bw_bmp = BW_CAP_20M;
++		highest_rate_bw = CHANNEL_WIDTH_20;
++		for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) {
++			if (rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw] < rf_ctl->rate_bmp_vht_by_bw[bw]) {
++				highest_rate_bw_bmp = ch_width_to_bw_cap(bw);
++				highest_rate_bw = bw;
++			} else if (rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw] == rf_ctl->rate_bmp_vht_by_bw[bw])
++				highest_rate_bw_bmp |= ch_width_to_bw_cap(bw);
++		}
++		rf_ctl->highest_vht_rate_bw_bmp = highest_rate_bw_bmp;
++
++		if (ori_highest_vht_rate_bw_bmp != rf_ctl->highest_vht_rate_bw_bmp
++			|| largest_bit_64(ori_bmp_vht[highest_rate_bw]) != largest_bit_64(rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw])
++		) {
++			if (DBG_HIGHEST_RATE_BMP_BW_CHANGE) {
++				RTW_INFO("highest_vht_rate_bw_bmp:0x%02x=>0x%02x\n", ori_highest_vht_rate_bw_bmp, rf_ctl->highest_vht_rate_bw_bmp);
++				RTW_INFO("rate_bmp_vht_by_bw[%u]:0x%016llx=>0x%016llx\n", highest_rate_bw, ori_bmp_vht[highest_rate_bw], rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw]);
++			}
++			if (rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw])
++				update_vht_rs = _TRUE;
++		}
++
++		/* TODO: per rfpath and rate section handling? */
++		if (update_ht_rs == _TRUE || update_vht_rs == _TRUE)
++			rtw_hal_set_tx_power_level(dvobj_get_primary_adapter(dvobj), hal_data->current_channel);
++	}
++#endif /* CONFIG_TXPWR_LIMIT */
++}
++
++u8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw)
++{
++	struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
++	u8 bw;
++	u8 bw_bmp = 0;
++	u32 rate_bmp;
++
++	if (!IS_HT_RATE(rate)) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	rate_bmp = 1 << (rate - MGN_MCS0);
++
++	if (max_bw > CHANNEL_WIDTH_40)
++		max_bw = CHANNEL_WIDTH_40;
++
++	for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) {
++		/* RA may use lower rate for retry */
++		if (rf_ctl->rate_bmp_ht_by_bw[bw] >= rate_bmp)
++			bw_bmp |= ch_width_to_bw_cap(bw);
++	}
++
++exit:
++	return bw_bmp;
++}
++
++u8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw)
++{
++	struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
++	u8 bw;
++	u8 bw_bmp = 0;
++	u64 rate_bmp;
++
++	if (!IS_VHT_RATE(rate)) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	rate_bmp = BIT_ULL(rate - MGN_VHT1SS_MCS0);
++
++	if (max_bw > CHANNEL_WIDTH_160)
++		max_bw = CHANNEL_WIDTH_160;
++
++	for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) {
++		/* RA may use lower rate for retry */
++		if (rf_ctl->rate_bmp_vht_by_bw[bw] >= rate_bmp)
++			bw_bmp |= ch_width_to_bw_cap(bw);
++	}
++
++exit:
++	return bw_bmp;
++}
++
++s16 rtw_adapter_get_oper_txpwr_max_mbm(_adapter *adapter)
++{
++	s16 mbm = -100 * MBM_PDBM;
++
++	if (MLME_IS_ASOC(adapter)) {
++		struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++		u8 ch = mlmeext->cur_channel;
++		u8 bw = mlmeext->cur_bwmode;
++		u8 offset = mlmeext->cur_ch_offset;
++		u8 cch = rtw_get_center_ch(ch, bw, offset);
++		u8 hw_rate = MRateToHwRate(mlmeext->tx_rate);
++		u16 bmp_cck_ofdm_by_bw[1] = {0};
++		u32 bmp_ht_by_bw[2] = {0};
++		u64 bmp_vht_by_bw[4] = {0};
++		u16 bmp_cck_ofdm = 0;
++		u32 bmp_ht = 0;
++		u64 bmp_vht = 0;
++		int i;
++
++		rtw_get_adapter_tx_rate_bmp(adapter, bmp_cck_ofdm_by_bw, bmp_ht_by_bw, bmp_vht_by_bw);
++
++		bmp_cck_ofdm |= bmp_cck_ofdm_by_bw[0];
++		for (i = 0; i < 2; i++)
++			bmp_ht |= bmp_ht_by_bw[i];
++		for (i = 0; i < 4; i++)
++			bmp_vht |= bmp_vht_by_bw[i];
++
++		if (IS_LEGACY_HRATE(hw_rate))
++			bmp_cck_ofdm |= BIT(hw_rate);
++		else if (IS_HT_HRATE(hw_rate))
++			bmp_ht |= BIT(hw_rate - DESC_RATEMCS0);
++		else if (IS_VHT_HRATE(hw_rate))
++			bmp_vht |= BIT(hw_rate - DESC_RATEVHTSS1MCS0);
++
++		mbm = phy_get_txpwr_total_max_mbm(adapter
++			, bw, cch, ch, bmp_cck_ofdm, bmp_ht, bmp_vht);
++	}
++
++	return mbm;
++}
++
++s16 rtw_get_oper_txpwr_max_mbm(struct dvobj_priv *dvobj)
++{
++	struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
++	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
++	s16 mbm = -100 * MBM_PDBM;
++	u8 ch, bw, offset;
++
++	if (rtw_mi_get_ch_setting_union(adapter, &ch, &bw, &offset)) {
++		u8 cch = rtw_get_center_ch(ch, bw, offset);
++		u16 bmp_cck_ofdm = 0;
++		u32 bmp_ht = 0;
++		u64 bmp_vht = 0;
++		int i;
++
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			if (dvobj->padapters[i] && MLME_IS_ASOC(dvobj->padapters[i])) {
++				struct mlme_ext_priv *mlmeext = &(dvobj->padapters[i]->mlmeextpriv);
++				u8 hw_rate = MRateToHwRate(mlmeext->tx_rate);
++
++				if (IS_LEGACY_HRATE(hw_rate))
++					bmp_cck_ofdm |= BIT(hw_rate);
++				else if (IS_HT_HRATE(hw_rate))
++					bmp_ht |= BIT(hw_rate - DESC_RATEMCS0);
++				else if (IS_VHT_HRATE(hw_rate))
++					bmp_vht |= BIT(hw_rate - DESC_RATEVHTSS1MCS0);
++			}
++		}
++
++		bmp_cck_ofdm |= rfctl->rate_bmp_cck_ofdm;
++		for (i = 0; i < 2; i++)
++			bmp_ht |= rfctl->rate_bmp_ht_by_bw[i];
++		for (i = 0; i < 4; i++)
++			bmp_vht |= rfctl->rate_bmp_vht_by_bw[i];
++
++		mbm = phy_get_txpwr_total_max_mbm(adapter
++			, bw, cch, ch, bmp_cck_ofdm, bmp_ht, bmp_vht);
++	}
++
++	return mbm;
++}
++
++u8 query_ra_short_GI(struct sta_info *psta, u8 bw)
++{
++	u8	sgi = _FALSE, sgi_20m = _FALSE, sgi_40m = _FALSE, sgi_80m = _FALSE;
++
++#ifdef CONFIG_80211N_HT
++#ifdef CONFIG_80211AC_VHT
++	if (psta->vhtpriv.vht_option)
++		sgi_80m = psta->vhtpriv.sgi_80m;
++#endif
++	sgi_20m = psta->htpriv.sgi_20m;
++	sgi_40m = psta->htpriv.sgi_40m;
++#endif
++
++	switch (bw) {
++	case CHANNEL_WIDTH_80:
++		sgi = sgi_80m;
++		break;
++	case CHANNEL_WIDTH_40:
++		sgi = sgi_40m;
++		break;
++	case CHANNEL_WIDTH_20:
++	default:
++		sgi = sgi_20m;
++		break;
++	}
++
++	return sgi;
++}
++
++/* This function references driver insmond parameters to decide vcs mode. */
++/* Driver insmond parameters: rtw_vrtl_carrier_sense and rtw_vcs_type */
++static u8 validate_vcs(_adapter *padapter, u8  mode) {
++
++	u8 vcs_mode = NONE_VCS;
++
++	switch(padapter->registrypriv.vrtl_carrier_sense) {
++
++		case DISABLE_VCS:
++			vcs_mode = NONE_VCS;
++			break;
++
++		case ENABLE_VCS:
++			vcs_mode = padapter->registrypriv.vcs_type;
++			break;
++
++		case AUTO_VCS:
++			vcs_mode = mode;
++			break;
++
++		default:
++			vcs_mode = NONE_VCS;
++			break;
++	}
++
++	return vcs_mode;
++
++}
++
++static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++	u32	sz;
++	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
++	/* struct sta_info	*psta = pattrib->psta; */
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	/*
++		if(pattrib->psta)
++		{
++			psta = pattrib->psta;
++		}
++		else
++		{
++			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
++			psta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] );
++		}
++
++		if(psta==NULL)
++		{
++			RTW_INFO("%s, psta==NUL\n", __func__);
++			return;
++		}
++
++		if(!(psta->state &WIFI_ASOC_STATE))
++		{
++			RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
++			return;
++		}
++	*/
++
++	if (pattrib->nr_frags != 1)
++		sz = padapter->xmitpriv.frag_len;
++	else /* no frag */
++		sz = pattrib->last_txcmdsz;
++
++	/* (1) RTS_Threshold is compared to the MPDU, not MSDU. */
++	/* (2) If there are more than one frag in  this MSDU, only the first frag uses protection frame. */
++	/*		Other fragments are protected by previous fragment. */
++	/*		So we only need to check the length of first fragment. */
++	if (pmlmeext->cur_wireless_mode < WIRELESS_11_24N  || padapter->registrypriv.wifi_spec) {
++		if (sz > padapter->registrypriv.rts_thresh)
++			pattrib->vcs_mode = RTS_CTS;
++		else {
++			if (pattrib->rtsen)
++				pattrib->vcs_mode = RTS_CTS;
++			else if (pattrib->cts2self)
++				pattrib->vcs_mode = CTS_TO_SELF;
++			else
++				pattrib->vcs_mode = NONE_VCS;
++		}
++	} else {
++		while (_TRUE) {
++#if 0 /* Todo */
++			/* check IOT action */
++			if (pHTInfo->IOTAction & HT_IOT_ACT_FORCED_CTS2SELF) {
++				pattrib->vcs_mode = CTS_TO_SELF;
++				pattrib->rts_rate = MGN_24M;
++				break;
++			} else if (pHTInfo->IOTAction & (HT_IOT_ACT_FORCED_RTS | HT_IOT_ACT_PURE_N_MODE)) {
++				pattrib->vcs_mode = RTS_CTS;
++				pattrib->rts_rate = MGN_24M;
++				break;
++			}
++#endif
++
++			/* IOT action */
++			if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS) && (pattrib->ampdu_en == _TRUE) &&
++			    (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) {
++				pattrib->vcs_mode = CTS_TO_SELF;
++				break;
++			}
++
++
++			/* check ERP protection */
++			if (pattrib->rtsen || pattrib->cts2self) {
++				if (pattrib->rtsen)
++					pattrib->vcs_mode = RTS_CTS;
++				else if (pattrib->cts2self)
++					pattrib->vcs_mode = CTS_TO_SELF;
++
++				break;
++			}
++
++			/* check HT op mode */
++			if (pattrib->ht_en) {
++				u8 HTOpMode = pmlmeinfo->HT_protection;
++				if ((pmlmeext->cur_bwmode && (HTOpMode == 2 || HTOpMode == 3)) ||
++				    (!pmlmeext->cur_bwmode && HTOpMode == 3)) {
++					pattrib->vcs_mode = RTS_CTS;
++					break;
++				}
++			}
++
++			/* check rts */
++			if (sz > padapter->registrypriv.rts_thresh) {
++				pattrib->vcs_mode = RTS_CTS;
++				break;
++			}
++
++			/* to do list: check MIMO power save condition. */
++
++			/* check AMPDU aggregation for TXOP */
++			if ((pattrib->ampdu_en == _TRUE) && (!IS_HARDWARE_TYPE_8812(padapter))) {
++				pattrib->vcs_mode = RTS_CTS;
++				break;
++			}
++
++			pattrib->vcs_mode = NONE_VCS;
++			break;
++		}
++	}
++
++	pattrib->vcs_mode = validate_vcs(padapter, pattrib->vcs_mode);
++
++	/* for debug : force driver control vrtl_carrier_sense. */
++	if (padapter->driver_vcs_en == 1) {
++		/* u8 driver_vcs_en; */ /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */
++		/* u8 driver_vcs_type; */ /* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */
++		pattrib->vcs_mode = padapter->driver_vcs_type;
++	}
++
++}
++
++#ifdef CONFIG_WMMPS_STA
++/*
++ * update_attrib_trigger_frame_info
++ * For Station mode, if a specific TID of driver setting and an AP support uapsd function, the data 
++ * frame with corresponding TID will be a trigger frame when driver is in wmm power saving mode.
++ * 
++ * Arguments:
++ * @padapter: _adapter pointer.
++ * @pattrib: pkt_attrib pointer.
++ *
++ * Auther: Arvin Liu
++ * Date: 2017/06/05
++ */
++static void update_attrib_trigger_frame_info(_adapter *padapter, struct pkt_attrib *pattrib) {
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct pwrctrl_priv 	*pwrpriv = adapter_to_pwrctl(padapter); 
++	struct qos_priv 	*pqospriv = &pmlmepriv->qospriv;
++	u8 trigger_frame_en = 0;
++
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
++		if ((pwrpriv->pwr_mode == PS_MODE_MIN) || (pwrpriv->pwr_mode == PS_MODE_MAX)) {
++			if((pqospriv->uapsd_ap_supported) && ((pqospriv->uapsd_tid & BIT(pattrib->priority)) == _TRUE)) {
++				trigger_frame_en = 1;
++				RTW_INFO("[WMMPS]"FUNC_ADPT_FMT": This is a Trigger Frame\n", FUNC_ADPT_ARG(padapter));
++			}
++		}
++	}
++
++	pattrib->trigger_frame = trigger_frame_en;
++}
++#endif /* CONFIG_WMMPS_STA */
++
++static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta)
++{
++	struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv;
++	u8 bw;
++
++	pattrib->rtsen = psta->rtsen;
++	pattrib->cts2self = psta->cts2self;
++
++	pattrib->mdata = 0;
++	pattrib->eosp = 0;
++	pattrib->triggered = 0;
++	pattrib->ampdu_spacing = 0;
++
++	/* ht_en, init rate, ,bw, ch_offset, sgi */
++
++	pattrib->raid = psta->cmn.ra_info.rate_id;
++
++	bw = rtw_get_tx_bw_mode(padapter, psta);
++	pattrib->bwmode = rtw_min(bw, mlmeext->cur_bwmode);
++	pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode);
++
++	pattrib->ldpc = psta->cmn.ldpc_en;
++	pattrib->stbc = psta->cmn.stbc_en;
++
++#ifdef CONFIG_80211N_HT
++	if(padapter->registrypriv.ht_enable &&
++		is_supported_ht(padapter->registrypriv.wireless_mode)) {
++		pattrib->ht_en = psta->htpriv.ht_option;
++		pattrib->ch_offset = psta->htpriv.ch_offset;
++		pattrib->ampdu_en = _FALSE;
++
++		if (padapter->driver_ampdu_spacing != 0xFF) /* driver control AMPDU Density for peer sta's rx */
++			pattrib->ampdu_spacing = padapter->driver_ampdu_spacing;
++		else
++			pattrib->ampdu_spacing = psta->htpriv.rx_ampdu_min_spacing;
++
++		/* check if enable ampdu */
++		if (pattrib->ht_en && psta->htpriv.ampdu_enable) {
++			if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) {
++				pattrib->ampdu_en = _TRUE;
++				if (psta->htpriv.tx_amsdu_enable == _TRUE)
++					pattrib->amsdu_ampdu_en = _TRUE;
++				else
++					pattrib->amsdu_ampdu_en = _FALSE;
++			}
++		}
++	}
++#endif /* CONFIG_80211N_HT */
++	/* if(pattrib->ht_en && psta->htpriv.ampdu_enable) */
++	/* { */
++	/*	if(psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) */
++	/*		pattrib->ampdu_en = _TRUE; */
++	/* }	 */
++
++#ifdef CONFIG_TDLS
++	if (pattrib->direct_link == _TRUE) {
++		psta = pattrib->ptdls_sta;
++
++		pattrib->raid = psta->cmn.ra_info.rate_id;
++#ifdef CONFIG_80211N_HT
++	if(padapter->registrypriv.ht_enable &&
++		is_supported_ht(padapter->registrypriv.wireless_mode)) {
++			pattrib->bwmode = rtw_get_tx_bw_mode(padapter, psta);
++			pattrib->ht_en = psta->htpriv.ht_option;
++			pattrib->ch_offset = psta->htpriv.ch_offset;
++			pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode);
++	}
++#endif /* CONFIG_80211N_HT */
++	}
++#endif /* CONFIG_TDLS */
++
++	pattrib->retry_ctrl = _FALSE;
++}
++
++static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta)
++{
++	sint res = _SUCCESS;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	sint bmcast = IS_MCAST(pattrib->ra);
++
++	_rtw_memset(pattrib->dot118021x_UncstKey.skey,  0, 16);
++	_rtw_memset(pattrib->dot11tkiptxmickey.skey,  0, 16);
++	pattrib->mac_id = psta->cmn.mac_id;
++
++	if (psta->ieee8021x_blocked == _TRUE) {
++
++		pattrib->encrypt = 0;
++
++		if ((pattrib->ether_type != 0x888e) && (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)) {
++#ifdef DBG_TX_DROP_FRAME
++			RTW_INFO("DBG_TX_DROP_FRAME %s psta->ieee8021x_blocked == _TRUE,  pattrib->ether_type(%04x) != 0x888e\n", __FUNCTION__, pattrib->ether_type);
++#endif
++			res = _FAIL;
++			goto exit;
++		}
++	} else {
++		GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, bmcast);
++
++#ifdef CONFIG_WAPI_SUPPORT
++		if (pattrib->ether_type == 0x88B4)
++			pattrib->encrypt = _NO_PRIVACY_;
++#endif
++
++		switch (psecuritypriv->dot11AuthAlgrthm) {
++		case dot11AuthAlgrthm_Open:
++		case dot11AuthAlgrthm_Shared:
++		case dot11AuthAlgrthm_Auto:
++			pattrib->key_idx = (u8)psecuritypriv->dot11PrivacyKeyIndex;
++			break;
++		case dot11AuthAlgrthm_8021X:
++			if (bmcast)
++				pattrib->key_idx = (u8)psecuritypriv->dot118021XGrpKeyid;
++			else
++				pattrib->key_idx = 0;
++			break;
++		default:
++			pattrib->key_idx = 0;
++			break;
++		}
++
++		/* For WPS 1.0 WEP, driver should not encrypt EAPOL Packet for WPS handshake. */
++		if (((pattrib->encrypt == _WEP40_) || (pattrib->encrypt == _WEP104_)) && (pattrib->ether_type == 0x888e))
++			pattrib->encrypt = _NO_PRIVACY_;
++
++	}
++
++#ifdef CONFIG_TDLS
++	if (pattrib->direct_link == _TRUE) {
++		if (pattrib->encrypt > 0)
++			pattrib->encrypt = _AES_;
++	}
++#endif
++
++	switch (pattrib->encrypt) {
++	case _WEP40_:
++	case _WEP104_:
++		pattrib->iv_len = 4;
++		pattrib->icv_len = 4;
++		WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
++		break;
++
++	case _TKIP_:
++		pattrib->iv_len = 8;
++		pattrib->icv_len = 4;
++
++		if (psecuritypriv->busetkipkey == _FAIL) {
++#ifdef DBG_TX_DROP_FRAME
++			RTW_INFO("DBG_TX_DROP_FRAME %s psecuritypriv->busetkipkey(%d)==_FAIL drop packet\n", __FUNCTION__, psecuritypriv->busetkipkey);
++#endif
++			res = _FAIL;
++			goto exit;
++		}
++
++		if (bmcast)
++			TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
++		else
++			TKIP_IV(pattrib->iv, psta->dot11txpn, 0);
++
++
++		_rtw_memcpy(pattrib->dot11tkiptxmickey.skey, psta->dot11tkiptxmickey.skey, 16);
++
++		break;
++
++	case _AES_:
++
++		pattrib->iv_len = 8;
++		pattrib->icv_len = 8;
++
++		if (bmcast)
++			AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
++		else
++			AES_IV(pattrib->iv, psta->dot11txpn, 0);
++
++		break;
++
++	case _GCMP_:
++	case _GCMP_256_:
++
++		pattrib->iv_len = 8;
++		pattrib->icv_len = 16;
++
++		if (bmcast)
++			GCMP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
++		else
++			GCMP_IV(pattrib->iv, psta->dot11txpn, 0);
++
++		break;
++
++	case _CCMP_256_:
++
++		pattrib->iv_len = 8;
++		pattrib->icv_len = 16;
++
++		if (bmcast)
++			GCMP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
++		else
++			GCMP_IV(pattrib->iv, psta->dot11txpn, 0);
++
++		break;
++
++#ifdef CONFIG_WAPI_SUPPORT
++	case _SMS4_:
++		pattrib->iv_len = 18;
++		pattrib->icv_len = 16;
++		rtw_wapi_get_iv(padapter, pattrib->ra, pattrib->iv);
++		break;
++#endif
++	default:
++		pattrib->iv_len = 0;
++		pattrib->icv_len = 0;
++		break;
++	}
++
++	if (pattrib->encrypt > 0) {
++		_rtw_memcpy(pattrib->dot118021x_UncstKey.skey
++			, psta->dot118021x_UncstKey.skey
++			, (pattrib->encrypt & _SEC_TYPE_256_) ? 32 : 16);
++	}
++
++
++	if (pattrib->encrypt &&
++	    ((padapter->securitypriv.sw_encrypt == _TRUE) || (psecuritypriv->hw_decrypted == _FALSE))) {
++		pattrib->bswenc = _TRUE;
++	} else {
++		pattrib->bswenc = _FALSE;
++	}
++
++	pattrib->bmc_camid = padapter->securitypriv.dot118021x_bmc_cam_id;
++
++	if (pattrib->encrypt && bmcast && _rtw_camctl_chk_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH))
++		pattrib->bswenc = _TRUE;
++
++#ifdef CONFIG_WAPI_SUPPORT
++	if (pattrib->encrypt == _SMS4_)
++		pattrib->bswenc = _FALSE;
++#endif
++
++exit:
++
++	return res;
++
++}
++
++u8	qos_acm(u8 acm_mask, u8 priority)
++{
++	u8	change_priority = priority;
++
++	switch (priority) {
++	case 0:
++	case 3:
++		if (acm_mask & BIT(1))
++			change_priority = 1;
++		break;
++	case 1:
++	case 2:
++		break;
++	case 4:
++	case 5:
++		if (acm_mask & BIT(2))
++			change_priority = 0;
++		break;
++	case 6:
++	case 7:
++		if (acm_mask & BIT(3))
++			change_priority = 5;
++		break;
++	default:
++		RTW_INFO("qos_acm(): invalid pattrib->priority: %d!!!\n", priority);
++		break;
++	}
++
++	return change_priority;
++}
++
++/* refer to IEEE802.11-2016 Table R-3; Comply with IETF RFC4594 */
++static u8 tos_to_up(u8 tos)
++{
++	u8 up = 0;
++	u8 dscp;
++	u8 mode = CONFIG_RTW_UP_MAPPING_RULE;
++
++
++	/* tos precedence mapping */
++	if (mode == 0) {
++		up = tos >> 5;
++		return up;
++	}
++
++	/* refer to IEEE802.11-2016 Table R-3;
++	 * DCSP 32(CS4) comply with IETF RFC4594
++	 */
++	dscp = (tos >> 2);
++
++	if ( dscp == 0 )
++		up = 0;
++	else if ( dscp >= 1 && dscp <= 9)
++		up = 1;
++	else if ( dscp >= 10 && dscp <= 16)
++		up = 2;
++	else if ( dscp >= 17 && dscp <= 23)
++		up = 3;
++	else if ( dscp >= 24 && dscp <= 31)
++		up = 4;
++	else if ( dscp >= 33 && dscp <= 40)
++		up = 5;
++	else if ((dscp >= 41 && dscp <= 47) || (dscp == 32))
++		up = 6;
++	else if ( dscp >= 48 && dscp <= 63)
++		up = 7;
++
++	return up;
++}
++
++static void set_qos(_pkt *pkt, struct pkt_attrib *pattrib)
++{
++	s32 UserPriority = 0;
++
++	if (!pkt)
++		goto null_pkt;
++
++	/* get UserPriority from IP hdr */
++	if (pattrib->ether_type == 0x0800) {
++		struct pkt_file ppktfile;
++		struct ethhdr etherhdr;
++		struct iphdr ip_hdr;
++
++		_rtw_open_pktfile(pkt, &ppktfile);
++		_rtw_pktfile_read(&ppktfile, (unsigned char *)&etherhdr, ETH_HLEN);
++		_rtw_pktfile_read(&ppktfile, (u8 *)&ip_hdr, sizeof(ip_hdr));
++		/*		UserPriority = (ntohs(ip_hdr.tos) >> 5) & 0x3; */
++		UserPriority = tos_to_up(ip_hdr.tos);
++	}
++	/*
++		else if (pattrib->ether_type == 0x888e) {
++
++
++			UserPriority = 7;
++		}
++	*/
++
++	#ifdef CONFIG_ICMP_VOQ
++	if(pattrib->icmp_pkt==1)/*use VO queue to send icmp packet*/
++		UserPriority = 7;
++	#endif
++	#ifdef CONFIG_IP_R_MONITOR
++	if (pattrib->ether_type == ETH_P_ARP)
++		UserPriority = 7;
++	#endif/*CONFIG_IP_R_MONITOR*/
++
++null_pkt:
++	pattrib->priority = UserPriority;
++	pattrib->hdrlen = XATTRIB_GET_WDS(pattrib) ? WLAN_HDR_A4_QOS_LEN : WLAN_HDR_A3_QOS_LEN;
++	pattrib->subtype = WIFI_QOS_DATA_TYPE;
++}
++
++#ifdef CONFIG_TDLS
++u8 rtw_check_tdls_established(_adapter *padapter, struct pkt_attrib *pattrib)
++{
++	pattrib->ptdls_sta = NULL;
++
++	pattrib->direct_link = _FALSE;
++	if (padapter->tdlsinfo.link_established == _TRUE) {
++		pattrib->ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst);
++#if 1
++		if ((pattrib->ptdls_sta != NULL) &&
++		    (pattrib->ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) &&
++		    (pattrib->ether_type != 0x0806)) {
++			pattrib->direct_link = _TRUE;
++			/* RTW_INFO("send ptk to "MAC_FMT" using direct link\n", MAC_ARG(pattrib->dst)); */
++		}
++#else
++		if (pattrib->ptdls_sta != NULL &&
++		    pattrib->ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {
++			pattrib->direct_link = _TRUE;
++#if 0
++			RTW_INFO("send ptk to "MAC_FMT" using direct link\n", MAC_ARG(pattrib->dst));
++#endif
++		}
++
++		/* ARP frame may be helped by AP*/
++		if (pattrib->ether_type != 0x0806)
++			pattrib->direct_link = _FALSE;
++#endif
++	}
++
++	return pattrib->direct_link;
++}
++
++s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
++{
++
++	struct sta_info *psta = NULL;
++	struct sta_priv		*pstapriv = &padapter->stapriv;
++	struct security_priv	*psecuritypriv = &padapter->securitypriv;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
++
++	s32 res = _SUCCESS;
++
++	psta = rtw_get_stainfo(pstapriv, pattrib->ra);
++	if (psta == NULL)	{
++		res = _FAIL;
++		goto exit;
++	}
++
++	pattrib->mac_id = psta->cmn.mac_id;
++	pattrib->psta = psta;
++	pattrib->ack_policy = 0;
++	/* get ether_hdr_len */
++	pattrib->pkt_hdrlen = ETH_HLEN;
++
++	pattrib->qos_en = psta->qos_option;
++
++	/* [TDLS] TODO: setup req/rsp should be AC_BK */
++	if (pqospriv->qos_option &&  psta->qos_option) {
++		pattrib->priority = 4;	/* tdls management frame should be AC_VI */
++		pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN;
++		pattrib->subtype = WIFI_QOS_DATA_TYPE;
++	} else {
++		pattrib->priority = 0;
++		pattrib->hdrlen = WLAN_HDR_A3_LEN;
++		pattrib->subtype = WIFI_DATA_TYPE;
++	}
++
++	/* TODO:_lock */
++	if (update_attrib_sec_info(padapter, pattrib, psta) == _FAIL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	update_attrib_phy_info(padapter, pattrib, psta);
++
++
++exit:
++
++	return res;
++}
++
++#endif /* CONFIG_TDLS */
++
++/*get non-qos hw_ssn control register,mapping to REG_HW_SEQ 0,1,2,3*/
++inline u8 rtw_get_hwseq_no(_adapter *padapter)
++{
++	u8 hwseq_num = 0;
++
++#ifdef CONFIG_CONCURRENT_MODE
++	#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
++	hwseq_num = padapter->iface_id;
++	if (hwseq_num > 3)
++		hwseq_num = 3;
++	#else
++	if (!is_primary_adapter(padapter))
++		hwseq_num = 1;
++	#endif
++#endif /* CONFIG_CONCURRENT_MODE */
++	return hwseq_num;
++}
++#ifdef CONFIG_LPS
++#define LPS_PT_NORMAL	0
++#define LPS_PT_SP		1/* only DHCP packets is as SPECIAL_PACKET*/
++#define LPS_PT_ICMP		2
++
++/*If EAPOL , ARP , OR DHCP packet, driver must be in active mode.*/
++static u8 _rtw_lps_chk_packet_type(struct pkt_attrib *pattrib)
++{
++	u8 pkt_type = LPS_PT_NORMAL; /*normal data frame*/
++
++	#ifdef CONFIG_WAPI_SUPPORT
++	if ((pattrib->ether_type == 0x88B4) || (pattrib->ether_type == 0x0806) || (pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1))
++		pkt_type = LPS_PT_SP;
++	#else /* !CONFIG_WAPI_SUPPORT */
++
++	#ifndef CONFIG_LPS_NOT_LEAVE_FOR_ICMP
++	if (pattrib->icmp_pkt == 1)
++		pkt_type = LPS_PT_ICMP;
++	else
++	#endif
++		if (pattrib->dhcp_pkt == 1)
++			pkt_type = LPS_PT_SP;
++	#endif
++	return pkt_type;
++}
++#endif
++static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattrib)
++{
++	uint i;
++	struct pkt_file pktfile;
++	struct sta_info *psta = NULL;
++	struct ethhdr etherhdr;
++
++	sint bmcast;
++	struct sta_priv		*pstapriv = &padapter->stapriv;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
++	struct xmit_priv		*pxmitpriv = &padapter->xmitpriv;
++	sint res = _SUCCESS;
++#ifdef CONFIG_LPS
++	u8 pkt_type = 0;
++#endif
++
++	DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib);
++
++	_rtw_open_pktfile(pkt, &pktfile);
++	i = _rtw_pktfile_read(&pktfile, (u8 *)&etherhdr, ETH_HLEN);
++
++	pattrib->ether_type = ntohs(etherhdr.h_proto);
++
++	if (MLME_STATE(padapter) & (WIFI_AP_STATE | WIFI_MESH_STATE)) /* address resolve is done for ap/mesh */
++		goto get_sta_info;
++
++	_rtw_memcpy(pattrib->dst, &etherhdr.h_dest, ETH_ALEN);
++	_rtw_memcpy(pattrib->src, &etherhdr.h_source, ETH_ALEN);
++	_rtw_memcpy(pattrib->ta, adapter_mac_addr(padapter), ETH_ALEN);
++
++	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ||
++	    (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
++		_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
++		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_adhoc);
++	} else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
++		#ifdef CONFIG_TDLS
++		if (rtw_check_tdls_established(padapter, pattrib) == _TRUE)
++			_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);	/* For TDLS direct link Tx, set ra to be same to dst */
++		else
++		#endif
++		{
++			_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
++			#ifdef CONFIG_RTW_WDS
++			if (adapter_use_wds(padapter)
++				&& _rtw_memcmp(pattrib->src, pattrib->ta, ETH_ALEN) == _FALSE)
++				pattrib->wds = 1;
++			#endif
++		}
++		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_sta);
++	} else
++		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_unknown);
++
++get_sta_info:
++	bmcast = IS_MCAST(pattrib->ra);
++	if (bmcast) {
++		psta = rtw_get_bcmc_stainfo(padapter);
++		if (psta == NULL) { /* if we cannot get psta => drop the pkt */
++			DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sta);
++			#ifdef DBG_TX_DROP_FRAME
++			RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra));
++			#endif
++			res = _FAIL;
++			goto exit;
++		}
++	} else {
++		psta = rtw_get_stainfo(pstapriv, pattrib->ra);
++		if (psta == NULL) { /* if we cannot get psta => drop the pkt */
++			DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_sta);
++			#ifdef DBG_TX_DROP_FRAME
++			RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra));
++			#endif
++			res = _FAIL;
++			goto exit;
++		} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && !(psta->state & WIFI_ASOC_STATE)) {
++			DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_ap_link);
++			res = _FAIL;
++			goto exit;
++		}
++
++		#ifdef CONFIG_RTW_WDS
++		if (XATTRIB_GET_WDS(pattrib) && !(psta->flags & WLAN_STA_WDS))
++			pattrib->wds = 0;
++		#endif
++	}
++
++	if (!(psta->state & WIFI_ASOC_STATE)) {
++		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_link);
++		RTW_INFO("%s-"ADPT_FMT" psta("MAC_FMT")->state(0x%x) != WIFI_ASOC_STATE\n",
++			__func__, ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr), psta->state);
++		res = _FAIL;
++		goto exit;
++	}
++
++	pattrib->pktlen = pktfile.pkt_len;
++
++	/* TODO: 802.1Q VLAN header */
++	/* TODO: IPV6 */
++
++	if (ETH_P_IP == pattrib->ether_type) {
++		u8 ip[20];
++
++		_rtw_pktfile_read(&pktfile, ip, 20);
++
++		if (GET_IPV4_IHL(ip) * 4 > 20)
++			_rtw_pktfile_read(&pktfile, NULL, GET_IPV4_IHL(ip) - 20);
++
++		pattrib->icmp_pkt = 0;
++		pattrib->dhcp_pkt = 0;
++		pattrib->hipriority_pkt = 0;
++
++		if (GET_IPV4_PROTOCOL(ip) == 0x01) { /* ICMP */
++			pattrib->icmp_pkt = 1;
++			DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_icmp);
++
++		} else if (GET_IPV4_PROTOCOL(ip) == 0x11) { /* UDP */
++			u8 udp[24];
++
++			_rtw_pktfile_read(&pktfile, udp, 24);
++
++			if ((GET_UDP_SRC(udp) == 68 && GET_UDP_DST(udp) == 67)
++				|| (GET_UDP_SRC(udp) == 67 && GET_UDP_DST(udp) == 68)
++			) {
++				/* 67 : UDP BOOTP server, 68 : UDP BOOTP client */
++				if (pattrib->pktlen > 282) { /* MINIMUM_DHCP_PACKET_SIZE */
++					pattrib->dhcp_pkt = 1;
++					DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_dhcp);
++					if (0)
++						RTW_INFO("send DHCP packet\n");
++				}
++			}
++
++			/* WaveAgent packet, increase priority so that the system can read data in time */
++			if (((GET_UDP_SIG1(udp) == 0xcc) || (GET_UDP_SIG1(udp) == 0xdd)) &&
++				(GET_UDP_SIG2(udp) == 0xe2)) {
++				pattrib->hipriority_pkt = 1;
++			}
++
++		} else if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */
++			&& rtw_st_ctl_chk_reg_s_proto(&psta->st_ctl, 0x06) == _TRUE
++		) {
++			u8 tcp[20];
++
++			_rtw_pktfile_read(&pktfile, tcp, 20);
++
++			if (rtw_st_ctl_chk_reg_rule(&psta->st_ctl, padapter, IPV4_SRC(ip), TCP_SRC(tcp), IPV4_DST(ip), TCP_DST(tcp)) == _TRUE) {
++				if (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) {
++					session_tracker_add_cmd(padapter, psta
++						, IPV4_SRC(ip), TCP_SRC(tcp)
++						, IPV4_SRC(ip), TCP_DST(tcp));
++					if (DBG_SESSION_TRACKER)
++						RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" SYN-ACK\n"
++							, FUNC_ADPT_ARG(padapter)
++							, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))
++							, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)));
++				}
++				if (GET_TCP_FIN(tcp)) {
++					session_tracker_del_cmd(padapter, psta
++						, IPV4_SRC(ip), TCP_SRC(tcp)
++						, IPV4_SRC(ip), TCP_DST(tcp));
++					if (DBG_SESSION_TRACKER)
++						RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" FIN\n"
++							, FUNC_ADPT_ARG(padapter)
++							, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))
++							, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)));
++				}
++			}
++		}
++
++	} else if (0x888e == pattrib->ether_type)
++		parsing_eapol_packet(padapter, pktfile.cur_addr, psta, 1);
++#if defined (DBG_ARP_DUMP) || defined (DBG_IP_R_MONITOR)
++	else if (pattrib->ether_type == ETH_P_ARP) {
++		u8 arp[28] = {0};
++
++		_rtw_pktfile_read(&pktfile, arp, 28);
++		dump_arp_pkt(RTW_DBGDUMP, etherhdr.h_dest, etherhdr.h_source, arp, 1);
++	}
++#endif
++
++	if ((pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1))
++		rtw_mi_set_scan_deny(padapter, 3000);
++
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) &&
++		pattrib->ether_type == ETH_P_ARP &&
++		!IS_MCAST(pattrib->dst)) {
++		rtw_mi_set_scan_deny(padapter, 1000);
++		rtw_mi_scan_abort(padapter, _FALSE); /*rtw_scan_abort_no_wait*/
++	}
++
++#ifdef CONFIG_LPS
++	pkt_type = _rtw_lps_chk_packet_type(pattrib);
++
++	if (pkt_type == LPS_PT_SP) {/*packet is as SPECIAL_PACKET*/
++		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_active);
++		rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SPECIAL_PACKET, 0);
++	} else if (pkt_type == LPS_PT_ICMP)
++		rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0);
++#endif /* CONFIG_LPS */
++
++#ifdef CONFIG_BEAMFORMING
++	update_attrib_txbf_info(padapter, pattrib, psta);
++#endif
++
++	/* TODO:_lock */
++	if (update_attrib_sec_info(padapter, pattrib, psta) == _FAIL) {
++		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sec);
++		res = _FAIL;
++		goto exit;
++	}
++
++	/* get ether_hdr_len */
++	pattrib->pkt_hdrlen = ETH_HLEN;/* (pattrib->ether_type == 0x8100) ? (14 + 4 ): 14; */ /* vlan tag */
++
++	pattrib->hdrlen = XATTRIB_GET_WDS(pattrib) ? WLAN_HDR_A4_LEN : WLAN_HDR_A3_LEN;
++	pattrib->subtype = WIFI_DATA_TYPE;
++	pattrib->qos_en = psta->qos_option;
++	pattrib->priority = 0;
++
++	if (check_fwstate(pmlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE
++		| WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)
++	) {
++		if (pattrib->qos_en) {
++			set_qos(pkt, pattrib);
++			#ifdef CONFIG_RTW_MESH
++			if (MLME_IS_MESH(padapter))
++				rtw_mesh_tx_set_whdr_mctrl_len(pattrib->mesh_frame_mode, pattrib);
++			#endif
++		}
++	} else {
++#ifdef CONFIG_TDLS
++		if (pattrib->direct_link == _TRUE) {
++			if (pattrib->qos_en)
++				set_qos(pkt, pattrib);
++		} else
++#endif
++		{
++			if (pqospriv->qos_option) {
++				set_qos(pkt, pattrib);
++
++				if (pmlmepriv->acm_mask != 0)
++					pattrib->priority = qos_acm(pmlmepriv->acm_mask, pattrib->priority);
++			}
++		}
++	}
++	
++	update_attrib_phy_info(padapter, pattrib, psta);
++
++	/* RTW_INFO("%s ==> mac_id(%d)\n",__FUNCTION__,pattrib->mac_id ); */
++
++	pattrib->psta = psta;
++	/* TODO:_unlock */
++
++#ifdef CONFIG_AUTO_AP_MODE
++	if (psta->isrc && psta->pid > 0)
++		pattrib->pctrl = _TRUE;
++	else
++#endif
++		pattrib->pctrl = 0;
++
++	pattrib->ack_policy = 0;
++
++	if (bmcast)
++		pattrib->rate = psta->init_rate;
++
++
++#ifdef CONFIG_WMMPS_STA
++	update_attrib_trigger_frame_info(padapter, pattrib);
++#endif /* CONFIG_WMMPS_STA */	
++
++	/* pattrib->priority = 5; */ /* force to used VI queue, for testing */
++	pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no;
++	rtw_set_tx_chksum_offload(pkt, pattrib);
++
++exit:
++
++
++	return res;
++}
++
++static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++	sint			curfragnum, length;
++	u8	*pframe, *payload, mic[8];
++	struct	mic_data		micdata;
++	/* struct	sta_info		*stainfo; */
++	struct	pkt_attrib	*pattrib = &pxmitframe->attrib;
++	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
++	struct	xmit_priv		*pxmitpriv = &padapter->xmitpriv;
++	u8 priority[4] = {0x0, 0x0, 0x0, 0x0};
++	u8 hw_hdr_offset = 0;
++	sint bmcst = IS_MCAST(pattrib->ra);
++
++	/*
++		if(pattrib->psta)
++		{
++			stainfo = pattrib->psta;
++		}
++		else
++		{
++			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
++			stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]);
++		}
++
++		if(stainfo==NULL)
++		{
++			RTW_INFO("%s, psta==NUL\n", __func__);
++			return _FAIL;
++		}
++
++		if(!(stainfo->state &WIFI_ASOC_STATE))
++		{
++			RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, stainfo->state);
++			return _FAIL;
++		}
++	*/
++
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++	hw_hdr_offset = TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);;
++#else
++#ifdef CONFIG_TX_EARLY_MODE
++	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
++#else
++	hw_hdr_offset = TXDESC_OFFSET;
++#endif
++#endif
++
++	if (pattrib->encrypt == _TKIP_) { /* if(psecuritypriv->dot11PrivacyAlgrthm==_TKIP_PRIVACY_) */
++		/* encode mic code */
++		/* if(stainfo!= NULL) */
++		{
++			u8 null_key[16] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
++
++			pframe = pxmitframe->buf_addr + hw_hdr_offset;
++
++			if (bmcst) {
++				if (_rtw_memcmp(psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey, null_key, 16) == _TRUE) {
++					/* DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); */
++					/* rtw_msleep_os(10); */
++					return _FAIL;
++				}
++				/* start to calculate the mic code */
++				rtw_secmicsetkey(&micdata, psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey);
++			} else {
++				if (_rtw_memcmp(&pattrib->dot11tkiptxmickey.skey[0], null_key, 16) == _TRUE) {
++					/* DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); */
++					/* rtw_msleep_os(10); */
++					return _FAIL;
++				}
++				/* start to calculate the mic code */
++				rtw_secmicsetkey(&micdata, &pattrib->dot11tkiptxmickey.skey[0]);
++			}
++
++			if (pframe[1] & 1) { /* ToDS==1 */
++				rtw_secmicappend(&micdata, &pframe[16], 6);  /* DA */
++				if (pframe[1] & 2) /* From Ds==1 */
++					rtw_secmicappend(&micdata, &pframe[24], 6);
++				else
++					rtw_secmicappend(&micdata, &pframe[10], 6);
++			} else {	/* ToDS==0 */
++				rtw_secmicappend(&micdata, &pframe[4], 6);   /* DA */
++				if (pframe[1] & 2) /* From Ds==1 */
++					rtw_secmicappend(&micdata, &pframe[16], 6);
++				else
++					rtw_secmicappend(&micdata, &pframe[10], 6);
++
++			}
++
++			if (pattrib->qos_en)
++				priority[0] = (u8)pxmitframe->attrib.priority;
++
++
++			rtw_secmicappend(&micdata, &priority[0], 4);
++
++			payload = pframe;
++
++			for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {
++				payload = (u8 *)RND4((SIZE_PTR)(payload));
++
++				payload = payload + pattrib->hdrlen + pattrib->iv_len;
++				if ((curfragnum + 1) == pattrib->nr_frags) {
++					length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0);
++					rtw_secmicappend(&micdata, payload, length);
++					payload = payload + length;
++				} else {
++					length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0);
++					rtw_secmicappend(&micdata, payload, length);
++					payload = payload + length + pattrib->icv_len;
++				}
++			}
++			rtw_secgetmic(&micdata, &(mic[0]));
++			/* add mic code  and add the mic code length in last_txcmdsz */
++
++			_rtw_memcpy(payload, &(mic[0]), 8);
++			pattrib->last_txcmdsz += 8;
++
++			payload = payload - pattrib->last_txcmdsz + 8;
++		}
++	}
++
++
++	return _SUCCESS;
++}
++
++/*#define DBG_TX_SW_ENCRYPTOR*/
++
++static s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++
++	struct	pkt_attrib	*pattrib = &pxmitframe->attrib;
++	/* struct 	security_priv	*psecuritypriv=&padapter->securitypriv; */
++
++
++	/* if((psecuritypriv->sw_encrypt)||(pattrib->bswenc))	 */
++	if (pattrib->bswenc) {
++#ifdef DBG_TX_SW_ENCRYPTOR
++		RTW_INFO(ADPT_FMT" - sec_type:%s DO SW encryption\n",
++			ADPT_ARG(padapter), security_type_str(pattrib->encrypt));
++#endif
++
++		switch (pattrib->encrypt) {
++		case _WEP40_:
++		case _WEP104_:
++			rtw_wep_encrypt(padapter, (u8 *)pxmitframe);
++			break;
++		case _TKIP_:
++			rtw_tkip_encrypt(padapter, (u8 *)pxmitframe);
++			break;
++		case _AES_:
++		case _CCMP_256_:
++			rtw_aes_encrypt(padapter, (u8 *)pxmitframe);
++			break;
++		case _GCMP_:
++		case _GCMP_256_:
++			rtw_gcmp_encrypt(padapter, (u8 *)pxmitframe);
++			break;
++#ifdef CONFIG_WAPI_SUPPORT
++		case _SMS4_:
++			rtw_sms4_encrypt(padapter, (u8 *)pxmitframe);
++#endif
++		default:
++			break;
++		}
++
++	}
++
++
++	return _SUCCESS;
++}
++
++s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib)
++{
++	u16 *qc;
++
++	struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct qos_priv *pqospriv = &pmlmepriv->qospriv;
++	u8 qos_option = _FALSE;
++	sint res = _SUCCESS;
++	u16 *fctrl = &pwlanhdr->frame_ctl;
++
++	/* struct sta_info *psta; */
++
++	/* sint bmcst = IS_MCAST(pattrib->ra); */
++
++
++	/*
++		psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
++		if(pattrib->psta != psta)
++		{
++			RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
++			return;
++		}
++
++		if(psta==NULL)
++		{
++			RTW_INFO("%s, psta==NUL\n", __func__);
++			return _FAIL;
++		}
++
++		if(!(psta->state &WIFI_ASOC_STATE))
++		{
++			RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
++			return _FAIL;
++		}
++	*/
++
++	_rtw_memset(hdr, 0, WLANHDR_OFFSET);
++
++	set_frame_sub_type(fctrl, pattrib->subtype);
++
++	if (pattrib->subtype & WIFI_DATA_TYPE) {
++		if ((check_fwstate(pmlmepriv,  WIFI_STATION_STATE) == _TRUE)) {
++#ifdef CONFIG_TDLS
++			if (pattrib->direct_link == _TRUE) {
++				/* TDLS data transfer, ToDS=0, FrDs=0 */
++				_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
++				_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
++				_rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
++
++				if (pattrib->qos_en)
++					qos_option = _TRUE;
++			} else
++#endif /* CONFIG_TDLS */
++			{
++				#ifdef CONFIG_RTW_WDS
++				if (pattrib->wds) {
++					SetToDs(fctrl);
++					SetFrDs(fctrl);
++					_rtw_memcpy(pwlanhdr->addr1, pattrib->ra, ETH_ALEN);
++					_rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN);
++					_rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
++					_rtw_memcpy(pwlanhdr->addr4, pattrib->src, ETH_ALEN);
++				} else
++				#endif
++				{
++					/* to_ds = 1, fr_ds = 0; */
++					/* 1.Data transfer to AP */
++					/* 2.Arp pkt will relayed by AP */
++					SetToDs(fctrl);
++					_rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN);
++					_rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN);
++					_rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
++				}
++
++				if (pqospriv->qos_option)
++					qos_option = _TRUE;
++			}
++		} else if ((check_fwstate(pmlmepriv,  WIFI_AP_STATE) == _TRUE)) {
++			#ifdef CONFIG_RTW_WDS
++			if (pattrib->wds) {
++				SetToDs(fctrl);
++				SetFrDs(fctrl);
++				_rtw_memcpy(pwlanhdr->addr1, pattrib->ra, ETH_ALEN);
++				_rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN);
++				_rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
++				_rtw_memcpy(pwlanhdr->addr4, pattrib->src, ETH_ALEN);
++			} else
++			#endif
++			{
++				/* to_ds = 0, fr_ds = 1; */
++				SetFrDs(fctrl);
++				_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
++				_rtw_memcpy(pwlanhdr->addr2, get_bssid(pmlmepriv), ETH_ALEN);
++				_rtw_memcpy(pwlanhdr->addr3, pattrib->src, ETH_ALEN);
++			}
++
++			if (pattrib->qos_en)
++				qos_option = _TRUE;
++		} else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ||
++			(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
++			_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
++			_rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN);
++			_rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
++
++			if (pattrib->qos_en)
++				qos_option = _TRUE;
++#ifdef CONFIG_RTW_MESH
++		} else if (check_fwstate(pmlmepriv, WIFI_MESH_STATE) == _TRUE) {
++			rtw_mesh_tx_build_whdr(padapter, pattrib, fctrl, pwlanhdr);
++			if (pattrib->qos_en)
++				qos_option = _TRUE;
++			else {
++				RTW_WARN("[%s] !qos_en in Mesh\n", __FUNCTION__);
++				res = _FAIL;
++				goto exit;
++			}
++#endif
++		} else {
++			res = _FAIL;
++			goto exit;
++		}
++
++		if (pattrib->mdata)
++			SetMData(fctrl);
++
++		if (pattrib->encrypt)
++			SetPrivacy(fctrl);
++
++		if (qos_option) {
++			qc = (unsigned short *)(hdr + pattrib->hdrlen - 2);
++
++			if (pattrib->priority)
++				SetPriority(qc, pattrib->priority);
++
++			SetEOSP(qc, pattrib->eosp);
++
++			SetAckpolicy(qc, pattrib->ack_policy);
++
++			if(pattrib->amsdu)
++				SetAMsdu(qc, pattrib->amsdu);
++#ifdef CONFIG_RTW_MESH
++			if (MLME_IS_MESH(padapter)) {
++				/* active: don't care, light sleep: 0, deep sleep: 1*/
++				set_mps_lv(qc, 0); //TBD
++
++				/* TBD: temporary set (rspi, eosp) = (0, 1) which means End MPSP */
++				set_rspi(qc, 0);
++				SetEOSP(qc, 1);
++				
++				set_mctrl_present(qc, 1);
++			}
++#endif
++		}
++
++		/* TODO: fill HT Control Field */
++
++		/* Update Seq Num will be handled by f/w */
++		{
++			struct sta_info *psta;
++			psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
++			if (pattrib->psta != psta) {
++				RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
++				return _FAIL;
++			}
++
++			if (psta == NULL) {
++				RTW_INFO("%s, psta==NUL\n", __func__);
++				return _FAIL;
++			}
++
++			if (!(psta->state & WIFI_ASOC_STATE)) {
++				RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
++				return _FAIL;
++			}
++
++
++			if (psta) {
++				psta->sta_xmitpriv.txseq_tid[pattrib->priority]++;
++				psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF;
++				pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority];
++
++				SetSeqNum(hdr, pattrib->seqnum);
++
++#ifdef CONFIG_80211N_HT
++#if 0 /* move into update_attrib_phy_info(). */
++				/* check if enable ampdu */
++				if (pattrib->ht_en && psta->htpriv.ampdu_enable) {
++					if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority))
++						pattrib->ampdu_en = _TRUE;
++				}
++#endif
++				/* re-check if enable ampdu by BA_starting_seqctrl */
++				if (pattrib->ampdu_en == _TRUE) {
++					u16 tx_seq;
++
++					tx_seq = psta->BA_starting_seqctrl[pattrib->priority & 0x0f];
++
++					/* check BA_starting_seqctrl */
++					if (SN_LESS(pattrib->seqnum, tx_seq)) {
++						/* RTW_INFO("tx ampdu seqnum(%d) < tx_seq(%d)\n", pattrib->seqnum, tx_seq); */
++						pattrib->ampdu_en = _FALSE;/* AGG BK */
++					} else if (SN_EQUAL(pattrib->seqnum, tx_seq)) {
++						psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (tx_seq + 1) & 0xfff;
++
++						pattrib->ampdu_en = _TRUE;/* AGG EN */
++					} else {
++						/* RTW_INFO("tx ampdu over run\n"); */
++						psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (pattrib->seqnum + 1) & 0xfff;
++						pattrib->ampdu_en = _TRUE;/* AGG EN */
++					}
++
++				}
++#endif /* CONFIG_80211N_HT */
++			}
++		}
++
++	} else {
++
++	}
++
++exit:
++
++
++	return res;
++}
++
++s32 rtw_txframes_pending(_adapter *padapter)
++{
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++	return ((_rtw_queue_empty(&pxmitpriv->be_pending) == _FALSE) ||
++		(_rtw_queue_empty(&pxmitpriv->bk_pending) == _FALSE) ||
++		(_rtw_queue_empty(&pxmitpriv->vi_pending) == _FALSE) ||
++		(_rtw_queue_empty(&pxmitpriv->vo_pending) == _FALSE));
++}
++
++s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib)
++{
++	struct sta_info *psta;
++	struct tx_servq *ptxservq;
++	int priority = pattrib->priority;
++	/*
++		if(pattrib->psta)
++		{
++			psta = pattrib->psta;
++		}
++		else
++		{
++			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
++			psta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]);
++		}
++	*/
++	psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
++	if (pattrib->psta != psta) {
++		RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
++		return 0;
++	}
++
++	if (psta == NULL) {
++		RTW_INFO("%s, psta==NUL\n", __func__);
++		return 0;
++	}
++
++	if (!(psta->state & WIFI_ASOC_STATE)) {
++		RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
++		return 0;
++	}
++
++	switch (priority) {
++	case 1:
++	case 2:
++		ptxservq = &(psta->sta_xmitpriv.bk_q);
++		break;
++	case 4:
++	case 5:
++		ptxservq = &(psta->sta_xmitpriv.vi_q);
++		break;
++	case 6:
++	case 7:
++		ptxservq = &(psta->sta_xmitpriv.vo_q);
++		break;
++	case 0:
++	case 3:
++	default:
++		ptxservq = &(psta->sta_xmitpriv.be_q);
++		break;
++
++	}
++
++	return ptxservq->qcnt;
++}
++
++#ifdef CONFIG_TDLS
++
++int rtw_build_tdls_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt)
++{
++	struct pkt_attrib *pattrib = &pxmitframe->attrib;
++	struct sta_info *ptdls_sta = NULL;
++	int res = _SUCCESS;
++
++	ptdls_sta = rtw_get_stainfo((&padapter->stapriv), pattrib->dst);
++	if (ptdls_sta == NULL) {
++		switch (ptxmgmt->action_code) {
++		case TDLS_DISCOVERY_REQUEST:
++		case TUNNELED_PROBE_REQ:
++		case TUNNELED_PROBE_RSP:
++			break;
++		default:
++			RTW_INFO("[TDLS] %s - Direct Link Peer = "MAC_FMT" not found for action = %d\n", __func__, MAC_ARG(pattrib->dst), ptxmgmt->action_code);
++			res = _FAIL;
++			goto exit;
++		}
++	}
++
++	switch (ptxmgmt->action_code) {
++	case TDLS_SETUP_REQUEST:
++		rtw_build_tdls_setup_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
++		break;
++	case TDLS_SETUP_RESPONSE:
++		rtw_build_tdls_setup_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
++		break;
++	case TDLS_SETUP_CONFIRM:
++		rtw_build_tdls_setup_cfm_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
++		break;
++	case TDLS_TEARDOWN:
++		rtw_build_tdls_teardown_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
++		break;
++	case TDLS_DISCOVERY_REQUEST:
++		rtw_build_tdls_dis_req_ies(padapter, pxmitframe, pframe, ptxmgmt);
++		break;
++	case TDLS_PEER_TRAFFIC_INDICATION:
++		rtw_build_tdls_peer_traffic_indication_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
++		break;
++#ifdef CONFIG_TDLS_CH_SW
++	case TDLS_CHANNEL_SWITCH_REQUEST:
++		rtw_build_tdls_ch_switch_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
++		break;
++	case TDLS_CHANNEL_SWITCH_RESPONSE:
++		rtw_build_tdls_ch_switch_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
++		break;
++#endif
++	case TDLS_PEER_TRAFFIC_RESPONSE:
++		rtw_build_tdls_peer_traffic_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
++		break;
++#ifdef CONFIG_WFD
++	case TUNNELED_PROBE_REQ:
++		rtw_build_tunneled_probe_req_ies(padapter, pxmitframe, pframe);
++		break;
++	case TUNNELED_PROBE_RSP:
++		rtw_build_tunneled_probe_rsp_ies(padapter, pxmitframe, pframe);
++		break;
++#endif /* CONFIG_WFD */
++	default:
++		res = _FAIL;
++		break;
++	}
++
++exit:
++	return res;
++}
++
++s32 rtw_make_tdls_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt)
++{
++	u16 *qc;
++	struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct qos_priv *pqospriv = &pmlmepriv->qospriv;
++	struct sta_priv	*pstapriv = &padapter->stapriv;
++	struct sta_info *psta = NULL, *ptdls_sta = NULL;
++	u8 tdls_seq = 0, baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
++
++	sint res = _SUCCESS;
++	u16 *fctrl = &pwlanhdr->frame_ctl;
++
++
++	_rtw_memset(hdr, 0, WLANHDR_OFFSET);
++
++	set_frame_sub_type(fctrl, pattrib->subtype);
++
++	switch (ptxmgmt->action_code) {
++	case TDLS_SETUP_REQUEST:
++	case TDLS_SETUP_RESPONSE:
++	case TDLS_SETUP_CONFIRM:
++	case TDLS_PEER_TRAFFIC_INDICATION:
++	case TDLS_PEER_PSM_REQUEST:
++	case TUNNELED_PROBE_REQ:
++	case TUNNELED_PROBE_RSP:
++	case TDLS_DISCOVERY_REQUEST:
++		SetToDs(fctrl);
++		_rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
++		break;
++	case TDLS_CHANNEL_SWITCH_REQUEST:
++	case TDLS_CHANNEL_SWITCH_RESPONSE:
++	case TDLS_PEER_PSM_RESPONSE:
++	case TDLS_PEER_TRAFFIC_RESPONSE:
++		_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
++		tdls_seq = 1;
++		break;
++	case TDLS_TEARDOWN:
++		if (ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_) {
++			_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
++			_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
++			_rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
++			tdls_seq = 1;
++		} else {
++			SetToDs(fctrl);
++			_rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN);
++			_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
++			_rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
++		}
++		break;
++	}
++
++	if (pattrib->encrypt)
++		SetPrivacy(fctrl);
++
++	if (ptxmgmt->action_code == TDLS_PEER_TRAFFIC_RESPONSE)
++		SetPwrMgt(fctrl);
++
++	if (pqospriv->qos_option) {
++		qc = (unsigned short *)(hdr + pattrib->hdrlen - 2);
++		if (pattrib->priority)
++			SetPriority(qc, pattrib->priority);
++		SetAckpolicy(qc, pattrib->ack_policy);
++	}
++
++	psta = pattrib->psta;
++
++	/* 1. update seq_num per link by sta_info */
++	/* 2. rewrite encrypt to _AES_, also rewrite iv_len, icv_len */
++	if (tdls_seq == 1) {
++		ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst);
++		if (ptdls_sta) {
++			ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]++;
++			ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF;
++			pattrib->seqnum = ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority];
++			SetSeqNum(hdr, pattrib->seqnum);
++
++			if (pattrib->encrypt) {
++				pattrib->encrypt = _AES_;
++				pattrib->iv_len = 8;
++				pattrib->icv_len = 8;
++				pattrib->bswenc = _FALSE;
++			}
++			pattrib->mac_id = ptdls_sta->cmn.mac_id;
++		} else {
++			res = _FAIL;
++			goto exit;
++		}
++	} else if (psta) {
++		psta->sta_xmitpriv.txseq_tid[pattrib->priority]++;
++		psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF;
++		pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority];
++		SetSeqNum(hdr, pattrib->seqnum);
++	}
++
++
++exit:
++
++
++	return res;
++}
++
++s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt)
++{
++	s32 llc_sz;
++
++	u8 *pframe, *mem_start;
++
++	struct sta_info		*psta;
++	struct sta_priv		*pstapriv = &padapter->stapriv;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
++	u8 *pbuf_start;
++	s32 bmcst = IS_MCAST(pattrib->ra);
++	s32 res = _SUCCESS;
++
++
++	if (pattrib->psta)
++		psta = pattrib->psta;
++	else {
++		if (bmcst)
++			psta = rtw_get_bcmc_stainfo(padapter);
++		else
++			psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
++	}
++
++	if (psta == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	if (pxmitframe->buf_addr == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pbuf_start = pxmitframe->buf_addr;
++	mem_start = pbuf_start + TXDESC_OFFSET;
++
++	if (rtw_make_tdls_wlanhdr(padapter, mem_start, pattrib, ptxmgmt) == _FAIL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pframe = mem_start;
++	pframe += pattrib->hdrlen;
++
++	/* adding icv, if necessary... */
++	if (pattrib->iv_len) {
++		if (psta != NULL) {
++			switch (pattrib->encrypt) {
++			case _WEP40_:
++			case _WEP104_:
++				WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
++				break;
++			case _TKIP_:
++				if (bmcst)
++					TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
++				else
++					TKIP_IV(pattrib->iv, psta->dot11txpn, 0);
++				break;
++			case _AES_:
++				if (bmcst)
++					AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
++				else
++					AES_IV(pattrib->iv, psta->dot11txpn, 0);
++				break;
++			}
++		}
++
++		_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);
++		pframe += pattrib->iv_len;
++
++	}
++
++	llc_sz = rtw_put_snap(pframe, pattrib->ether_type);
++	pframe += llc_sz;
++
++	/* pattrib->pktlen will be counted in rtw_build_tdls_ies */
++	pattrib->pktlen = 0;
++
++	rtw_build_tdls_ies(padapter, pxmitframe, pframe, ptxmgmt);
++
++	if ((pattrib->icv_len > 0) && (pattrib->bswenc)) {
++		pframe += pattrib->pktlen;
++		_rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);
++		pframe += pattrib->icv_len;
++	}
++
++	pattrib->nr_frags = 1;
++	pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + llc_sz +
++		((pattrib->bswenc) ? pattrib->icv_len : 0) + pattrib->pktlen;
++
++	if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	xmitframe_swencrypt(padapter, pxmitframe);
++
++	update_attrib_vcs_info(padapter, pxmitframe);
++
++exit:
++
++
++	return res;
++}
++#endif /* CONFIG_TDLS */
++
++/*
++ * Calculate wlan 802.11 packet MAX size from pkt_attrib
++ * This function doesn't consider fragment case
++ */
++u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib)
++{
++	u32	len = 0;
++
++	len = pattrib->hdrlen /* WLAN Header */
++		+ pattrib->iv_len /* IV */
++		+ XATTRIB_GET_MCTRL_LEN(pattrib)
++		+ SNAP_SIZE + sizeof(u16) /* LLC */
++		+ pattrib->pktlen
++		+ (pattrib->encrypt == _TKIP_ ? 8 : 0) /* MIC */
++		+ (pattrib->bswenc ? pattrib->icv_len : 0) /* ICV */
++		;
++
++	return len;
++}
++
++#ifdef CONFIG_TX_AMSDU
++s32 check_amsdu(struct xmit_frame *pxmitframe)
++{
++	struct pkt_attrib *pattrib;
++	s32 ret = _TRUE;
++
++	if (!pxmitframe)
++		ret = _FALSE;
++
++	pattrib = &pxmitframe->attrib;
++
++	if (IS_MCAST(pattrib->ra))
++		ret = _FALSE;
++
++	if ((pattrib->ether_type == 0x888e) ||
++		(pattrib->ether_type == 0x0806) ||
++		(pattrib->ether_type == 0x88b4) ||
++		(pattrib->dhcp_pkt == 1))
++		ret = _FALSE;
++
++	if ((pattrib->encrypt == _WEP40_) ||
++	    (pattrib->encrypt == _WEP104_) ||
++	    (pattrib->encrypt == _TKIP_))
++		ret = _FALSE;
++
++	if (!pattrib->qos_en)
++		ret = _FALSE;
++
++	if (IS_AMSDU_AMPDU_NOT_VALID(pattrib))
++		ret = _FALSE;
++
++	return ret;
++}
++
++s32 check_amsdu_tx_support(_adapter *padapter)
++{
++	struct dvobj_priv *pdvobjpriv;
++	int tx_amsdu;
++	int tx_amsdu_rate;
++	int current_tx_rate;
++	s32 ret = _FALSE;
++
++	pdvobjpriv = adapter_to_dvobj(padapter);
++	tx_amsdu = padapter->tx_amsdu;
++	tx_amsdu_rate = padapter->tx_amsdu_rate;
++	current_tx_rate = pdvobjpriv->traffic_stat.cur_tx_tp;
++
++	if (tx_amsdu == 1)
++		ret = _TRUE;
++	else if (tx_amsdu == 2 && (tx_amsdu_rate == 0 || current_tx_rate > tx_amsdu_rate))
++		ret = _TRUE;
++	else
++		ret = _FALSE;
++
++	return ret;
++}
++
++s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue)
++{
++
++	struct pkt_file pktfile;
++	struct pkt_attrib *pattrib;
++	_pkt *pkt;
++
++	struct pkt_file pktfile_queue;
++	struct pkt_attrib *pattrib_queue;
++	_pkt *pkt_queue;
++
++	s32 llc_sz, mem_sz;
++
++	s32 padding = 0;
++
++	u8 *pframe, *mem_start;
++	u8 hw_hdr_offset;
++
++	u16* len;
++	u8 *pbuf_start;
++	s32 res = _SUCCESS;
++
++	if (pxmitframe->buf_addr == NULL) {
++		RTW_INFO("==> %s buf_addr==NULL\n", __FUNCTION__);
++		return _FAIL;
++	}
++
++
++	pbuf_start = pxmitframe->buf_addr;
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++	hw_hdr_offset =  TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);
++#else
++#ifdef CONFIG_TX_EARLY_MODE /* for SDIO && Tx Agg */
++	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
++#else
++	hw_hdr_offset = TXDESC_OFFSET;
++#endif
++#endif
++
++	mem_start = pbuf_start + hw_hdr_offset; //for DMA
++
++	pattrib = &pxmitframe->attrib;
++
++	pattrib->amsdu = 1;
++
++	if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) {
++		RTW_INFO("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n");
++		res = _FAIL;
++		goto exit;
++	}
++
++	llc_sz = 0;
++
++	pframe = mem_start;
++
++	//SetMFrag(mem_start);
++	ClearMFrag(mem_start);
++
++	pframe += pattrib->hdrlen;
++
++	/* adding icv, if necessary... */
++	if (pattrib->iv_len) {
++		_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); // queue or new?
++
++		RTW_DBG("rtw_xmitframe_coalesce: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\n",
++			padapter->securitypriv.dot11PrivacyKeyIndex, pattrib->iv[3], *pframe, *(pframe + 1), *(pframe + 2), *(pframe + 3));
++
++		pframe += pattrib->iv_len;
++	}
++
++	pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len;
++
++	if(pxmitframe_queue)
++	{
++		pattrib_queue = &pxmitframe_queue->attrib;
++		pkt_queue = pxmitframe_queue->pkt;
++
++		_rtw_open_pktfile(pkt_queue, &pktfile_queue);
++		_rtw_pktfile_read(&pktfile_queue, NULL, pattrib_queue->pkt_hdrlen);
++
++		#ifdef CONFIG_RTW_MESH
++		if (MLME_IS_MESH(padapter)) {
++			/* mDA(6), mSA(6), len(2), mctrl */
++			_rtw_memcpy(pframe, pattrib_queue->mda, ETH_ALEN);
++			pframe += ETH_ALEN;
++			_rtw_memcpy(pframe, pattrib_queue->msa, ETH_ALEN);
++			pframe += ETH_ALEN;
++			len = (u16*)pframe;
++			pframe += 2;
++			rtw_mesh_tx_build_mctrl(padapter, pattrib_queue, pframe);
++			pframe += XATTRIB_GET_MCTRL_LEN(pattrib_queue);
++		} else
++		#endif
++		{
++			/* 802.3 MAC Header DA(6)  SA(6)  Len(2)*/
++			_rtw_memcpy(pframe, pattrib_queue->dst, ETH_ALEN);
++			pframe += ETH_ALEN;
++			_rtw_memcpy(pframe, pattrib_queue->src, ETH_ALEN);
++			pframe += ETH_ALEN;
++			len = (u16*)pframe;
++			pframe += 2;
++		}
++
++		llc_sz = rtw_put_snap(pframe, pattrib_queue->ether_type);
++		pframe += llc_sz;
++
++		mem_sz = _rtw_pktfile_read(&pktfile_queue, pframe, pattrib_queue->pktlen);
++		pframe += mem_sz;
++
++		*len = htons(XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz);
++
++		//calc padding
++		padding = 4 - ((ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz) & (4-1));
++		if(padding == 4)
++			padding = 0;
++
++		//_rtw_memset(pframe,0xaa, padding);
++		pframe += padding;
++
++		pattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz + padding ;
++	}
++
++	//2nd mpdu
++
++	pkt = pxmitframe->pkt;
++	_rtw_open_pktfile(pkt, &pktfile);
++	_rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen);
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(padapter)) {
++		/* mDA(6), mSA(6), len(2), mctrl */
++		_rtw_memcpy(pframe, pattrib->mda, ETH_ALEN);
++		pframe += ETH_ALEN;
++		_rtw_memcpy(pframe, pattrib->msa, ETH_ALEN);
++		pframe += ETH_ALEN;
++		len = (u16*)pframe;
++		pframe += 2;
++		rtw_mesh_tx_build_mctrl(padapter, pattrib, pframe);
++		pframe += XATTRIB_GET_MCTRL_LEN(pattrib);
++	} else
++#endif
++	{
++		/* 802.3 MAC Header  DA(6)  SA(6)  Len(2) */
++		_rtw_memcpy(pframe, pattrib->dst, ETH_ALEN);
++		pframe += ETH_ALEN;
++		_rtw_memcpy(pframe, pattrib->src, ETH_ALEN);
++		pframe += ETH_ALEN;
++		len = (u16*)pframe;
++		pframe += 2;
++	}
++
++	llc_sz = rtw_put_snap(pframe, pattrib->ether_type);
++	pframe += llc_sz;
++
++	mem_sz = _rtw_pktfile_read(&pktfile, pframe, pattrib->pktlen);
++
++	pframe += mem_sz;
++
++	*len = htons(XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz);
++
++	//the last ampdu has no padding
++	padding = 0;
++
++	pattrib->nr_frags = 1;
++
++	pattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz + padding +
++		((pattrib->bswenc) ? pattrib->icv_len : 0) ;
++
++	if ((pattrib->icv_len > 0) && (pattrib->bswenc)) {
++		_rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);
++		pframe += pattrib->icv_len;
++	}
++
++	if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) {
++		RTW_INFO("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n");
++		res = _FAIL;
++		goto exit;
++	}
++
++	xmitframe_swencrypt(padapter, pxmitframe);
++
++	update_attrib_vcs_info(padapter, pxmitframe);
++
++exit:
++	return res;
++}
++#endif /* CONFIG_TX_AMSDU */
++
++/*
++
++This sub-routine will perform all the following:
++
++1. remove 802.3 header.
++2. create wlan_header, based on the info in pxmitframe
++3. append sta's iv/ext-iv
++4. append LLC
++5. move frag chunk from pframe to pxmitframe->mem
++6. apply sw-encrypt, if necessary.
++
++*/
++s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe)
++{
++	struct pkt_file pktfile;
++
++	s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz;
++
++	SIZE_PTR addr;
++
++	u8 *pframe, *mem_start;
++	u8 hw_hdr_offset;
++
++	/* struct sta_info		*psta; */
++	/* struct sta_priv		*pstapriv = &padapter->stapriv; */
++	/* struct mlme_priv	*pmlmepriv = &padapter->mlmepriv; */
++	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
++
++	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
++
++	u8 *pbuf_start;
++
++	s32 bmcst = IS_MCAST(pattrib->ra);
++	s32 res = _SUCCESS;
++
++
++	/*
++		if (pattrib->psta)
++		{
++			psta = pattrib->psta;
++		} else
++		{
++			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
++			psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
++		}
++
++		if(psta==NULL)
++		{
++
++			RTW_INFO("%s, psta==NUL\n", __func__);
++			return _FAIL;
++		}
++
++
++		if(!(psta->state &WIFI_ASOC_STATE))
++		{
++			RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
++			return _FAIL;
++		}
++	*/
++	if (pxmitframe->buf_addr == NULL) {
++		RTW_INFO("==> %s buf_addr==NULL\n", __FUNCTION__);
++		return _FAIL;
++	}
++
++	pbuf_start = pxmitframe->buf_addr;
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++	hw_hdr_offset =  TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);
++#else
++#ifdef CONFIG_TX_EARLY_MODE /* for SDIO && Tx Agg */
++	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
++#else
++	hw_hdr_offset = TXDESC_OFFSET;
++#endif
++#endif
++
++	mem_start = pbuf_start +	hw_hdr_offset;
++
++	if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) {
++		RTW_INFO("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n");
++		res = _FAIL;
++		goto exit;
++	}
++
++	_rtw_open_pktfile(pkt, &pktfile);
++	_rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen);
++
++	frg_inx = 0;
++	frg_len = pxmitpriv->frag_len - 4;/* 2346-4 = 2342 */
++
++	while (1) {
++		llc_sz = 0;
++
++		mpdu_len = frg_len;
++
++		pframe = mem_start;
++
++		SetMFrag(mem_start);
++
++		pframe += pattrib->hdrlen;
++		mpdu_len -= pattrib->hdrlen;
++
++		/* adding icv, if necessary... */
++		if (pattrib->iv_len) {
++#if 0
++			/* if (check_fwstate(pmlmepriv, WIFI_MP_STATE)) */
++			/*	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); */
++			/* else */
++			/*	psta = rtw_get_stainfo(pstapriv, pattrib->ra); */
++
++			if (psta != NULL) {
++				switch (pattrib->encrypt) {
++				case _WEP40_:
++				case _WEP104_:
++					WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
++					break;
++				case _TKIP_:
++					if (bmcst)
++						TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
++					else
++						TKIP_IV(pattrib->iv, psta->dot11txpn, 0);
++					break;
++				case _AES_:
++					if (bmcst)
++						AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
++					else
++						AES_IV(pattrib->iv, psta->dot11txpn, 0);
++					break;
++#ifdef CONFIG_WAPI_SUPPORT
++				case _SMS4_:
++					rtw_wapi_get_iv(padapter, pattrib->ra, pattrib->iv);
++					break;
++#endif
++				}
++			}
++#endif
++			_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);
++
++
++			pframe += pattrib->iv_len;
++
++			mpdu_len -= pattrib->iv_len;
++		}
++
++		if (frg_inx == 0) {
++			#ifdef CONFIG_RTW_MESH
++			if (MLME_IS_MESH(padapter)) {
++				rtw_mesh_tx_build_mctrl(padapter, pattrib, pframe);
++				pframe += XATTRIB_GET_MCTRL_LEN(pattrib);
++				mpdu_len -= XATTRIB_GET_MCTRL_LEN(pattrib);
++			}
++			#endif
++
++			llc_sz = rtw_put_snap(pframe, pattrib->ether_type);
++			pframe += llc_sz;
++			mpdu_len -= llc_sz;
++		}
++
++		if ((pattrib->icv_len > 0) && (pattrib->bswenc))
++			mpdu_len -= pattrib->icv_len;
++
++
++		if (bmcst) {
++			/* don't do fragment to broadcat/multicast packets */
++			mem_sz = _rtw_pktfile_read(&pktfile, pframe, pattrib->pktlen);
++		} else
++			mem_sz = _rtw_pktfile_read(&pktfile, pframe, mpdu_len);
++
++		pframe += mem_sz;
++
++		if ((pattrib->icv_len > 0) && (pattrib->bswenc)) {
++			_rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);
++			pframe += pattrib->icv_len;
++		}
++
++		frg_inx++;
++
++		if (bmcst || (rtw_endofpktfile(&pktfile) == _TRUE)) {
++			pattrib->nr_frags = frg_inx;
++
++			pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len +
++				((pattrib->nr_frags == 1) ? (XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz) : 0) +
++				((pattrib->bswenc) ? pattrib->icv_len : 0) + mem_sz;
++
++			ClearMFrag(mem_start);
++
++			break;
++		}
++
++		addr = (SIZE_PTR)(pframe);
++
++		mem_start = (unsigned char *)RND4(addr) + hw_hdr_offset;
++		_rtw_memcpy(mem_start, pbuf_start + hw_hdr_offset, pattrib->hdrlen);
++
++	}
++
++	if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) {
++		RTW_INFO("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n");
++		res = _FAIL;
++		goto exit;
++	}
++
++	xmitframe_swencrypt(padapter, pxmitframe);
++
++	if (bmcst == _FALSE)
++		update_attrib_vcs_info(padapter, pxmitframe);
++	else
++		pattrib->vcs_mode = NONE_VCS;
++
++exit:
++
++
++	return res;
++}
++
++#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
++/*
++ * CCMP encryption for unicast robust mgmt frame and broadcast group privicy action
++ * BIP for broadcast robust mgmt frame
++ */
++s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe)
++{
++#define DBG_MGMT_XMIT_COALESEC_DUMP 0
++#define DBG_MGMT_XMIT_BIP_DUMP 0
++#define DBG_MGMT_XMIT_ENC_DUMP 0
++
++	struct pkt_file pktfile;
++	s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz;
++	SIZE_PTR addr;
++	u8 *pframe, *mem_start = NULL, *tmp_buf = NULL;
++	u8 hw_hdr_offset, subtype ;
++	u8 category = 0xFF;
++	struct sta_info		*psta = NULL;
++	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
++	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
++	u8 *pbuf_start;
++	s32 bmcst = IS_MCAST(pattrib->ra);
++	s32 res = _FAIL;
++	u8 *BIP_AAD = NULL;
++	u8 *MGMT_body = NULL;
++
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	u8 mme_cont[_MME_IE_LENGTH_ - 2];
++	u8 mme_clen;
++
++	_irqL irqL;
++	u32	ori_len;
++	union pn48 *pn = NULL;
++	enum security_type cipher = _NO_PRIVACY_;
++	u8 kid;
++
++	if (pxmitframe->buf_addr == NULL) {
++		RTW_WARN(FUNC_ADPT_FMT" pxmitframe->buf_addr\n"
++			, FUNC_ADPT_ARG(padapter));
++		return _FAIL;
++	}
++
++	mem_start = pframe = (u8 *)(pxmitframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++	subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */
++
++	/* check if robust mgmt frame */
++	if (subtype != WIFI_DEAUTH && subtype != WIFI_DISASSOC && subtype != WIFI_ACTION)
++		return _SUCCESS;
++	if (subtype == WIFI_ACTION) {
++		category = *(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
++		if (CATEGORY_IS_NON_ROBUST(category))
++			return _SUCCESS;
++	}
++	if (!bmcst) {
++		if (pattrib->psta)
++			psta = pattrib->psta;
++		else
++			pattrib->psta = psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
++		if (psta == NULL) {
++			RTW_INFO(FUNC_ADPT_FMT" unicast sta == NULL\n", FUNC_ADPT_ARG(padapter));
++			return _FAIL;
++		}
++		if (!(psta->flags & WLAN_STA_MFP)) {
++			/* peer is not MFP capable, no need to encrypt */
++			return _SUCCESS;
++		}
++		if (psta->bpairwise_key_installed != _TRUE) {
++			RTW_INFO(FUNC_ADPT_FMT" PTK is not installed\n"
++				, FUNC_ADPT_ARG(padapter));
++			return _FAIL;
++		}
++	}
++
++	ori_len = BIP_AAD_SIZE + pattrib->pktlen + _MME_IE_LENGTH_;
++	tmp_buf = BIP_AAD = rtw_zmalloc(ori_len);
++	if (BIP_AAD == NULL)
++		return _FAIL;
++
++	_enter_critical_bh(&padapter->security_key_mutex, &irqL);
++
++	if (bmcst) {
++		if (subtype == WIFI_ACTION && CATEGORY_IS_GROUP_PRIVACY(category)) {
++			/* broadcast group privacy action frame */
++			#if DBG_MGMT_XMIT_COALESEC_DUMP
++			RTW_INFO(FUNC_ADPT_FMT" broadcast gp action(%u)\n"
++				, FUNC_ADPT_ARG(padapter), category);
++			#endif
++
++			if (pattrib->psta)
++				psta = pattrib->psta;
++			else
++				pattrib->psta = psta = rtw_get_bcmc_stainfo(padapter);
++			if (psta == NULL) {
++				RTW_INFO(FUNC_ADPT_FMT" broadcast sta == NULL\n"
++					, FUNC_ADPT_ARG(padapter));
++				goto xmitframe_coalesce_fail;
++			}
++			if (padapter->securitypriv.binstallGrpkey != _TRUE) {
++				RTW_INFO(FUNC_ADPT_FMT" GTK is not installed\n"
++					, FUNC_ADPT_ARG(padapter));
++				goto xmitframe_coalesce_fail;
++			}
++
++			pn = &psta->dot11txpn;
++			cipher = padapter->securitypriv.dot118021XGrpPrivacy;
++			kid = padapter->securitypriv.dot118021XGrpKeyid;
++		} else {
++			#ifdef CONFIG_IEEE80211W
++			/* broadcast robust mgmt frame, using BIP */
++			int frame_body_len;
++			u8 mic[16];
++
++			/* IGTK key is not install ex: mesh MFP without IGTK */
++			if (SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) != _TRUE)
++				goto xmitframe_coalesce_success;
++
++			#if DBG_MGMT_XMIT_COALESEC_DUMP
++			if (subtype == WIFI_DEAUTH)
++				RTW_INFO(FUNC_ADPT_FMT" braodcast deauth\n", FUNC_ADPT_ARG(padapter));
++			else if (subtype == WIFI_DISASSOC)
++				RTW_INFO(FUNC_ADPT_FMT" braodcast disassoc\n", FUNC_ADPT_ARG(padapter));
++			else if (subtype == WIFI_ACTION) {
++				RTW_INFO(FUNC_ADPT_FMT" braodcast action(%u)\n"
++					, FUNC_ADPT_ARG(padapter), category);
++			}
++			#endif
++
++			_rtw_memset(mme_cont, 0, _MME_IE_LENGTH_ - 2);
++			mme_clen = padapter->securitypriv.dot11wCipher == _BIP_CMAC_128_ ? 16 : 24;
++
++			MGMT_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
++			pframe += pattrib->pktlen;
++
++			/* octent 0 and 1 is key index ,BIP keyid is 4 or 5, LSB only need octent 0 */
++			mme_cont[0] = padapter->securitypriv.dot11wBIPKeyid;
++			/* increase PN and apply to packet */
++			padapter->securitypriv.dot11wBIPtxpn.val++;
++			RTW_PUT_LE64(&mme_cont[2], padapter->securitypriv.dot11wBIPtxpn.val);
++
++			/* add MME IE with MIC all zero, MME string doesn't include element id and length */
++			pframe = rtw_set_ie(pframe, _MME_IE_ , mme_clen , mme_cont, &(pattrib->pktlen));
++			pattrib->last_txcmdsz = pattrib->pktlen;
++			/* total frame length - header length */
++			frame_body_len = pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr);
++
++			/* conscruct AAD, copy frame control field */
++			_rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2);
++			ClearRetry(BIP_AAD);
++			ClearPwrMgt(BIP_AAD);
++			ClearMData(BIP_AAD);
++			/* conscruct AAD, copy address 1 to address 3 */
++			_rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18);
++			/* copy management fram body */
++			_rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, MGMT_body, frame_body_len);
++
++			#if DBG_MGMT_XMIT_BIP_DUMP
++			/* dump total packet include MME with zero MIC */
++			{
++				int i;
++				printk("Total packet: ");
++				for (i = 0; i < BIP_AAD_SIZE + frame_body_len; i++)
++					printk(" %02x ", BIP_AAD[i]);
++				printk("\n");
++			}
++			#endif
++
++			/* calculate mic */
++			if (rtw_calculate_bip_mic(padapter->securitypriv.dot11wCipher,
++				(u8 *)pwlanhdr, pattrib->pktlen,
++				padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey, 
++				BIP_AAD, (BIP_AAD_SIZE + frame_body_len), mic) == _FAIL)
++				goto xmitframe_coalesce_fail;
++
++			#if DBG_MGMT_XMIT_BIP_DUMP
++			/* dump calculated mic result */
++			{
++				int i;
++				printk("Calculated mic result: ");
++				for (i = 0; i < 16; i++)
++					printk(" %02x ", mic[i]);
++				printk("\n");
++			}
++			#endif
++
++			/* copy right BIP mic value, total is 128bits, we use the 0~63 bits */
++			if (padapter->securitypriv.dot11wCipher == _BIP_CMAC_128_)
++				_rtw_memcpy(pframe - 8, mic, 8);
++			else
++				_rtw_memcpy(pframe - 16, mic, 16);
++
++			#if DBG_MGMT_XMIT_BIP_DUMP
++			/*dump all packet after mic ok */
++			{
++				int pp;
++				printk("pattrib->pktlen = %d\n", pattrib->pktlen);
++				for(pp=0;pp< pattrib->pktlen; pp++)
++					printk(" %02x ", mem_start[pp]);
++				printk("\n");
++			}
++			#endif
++
++			#endif /* CONFIG_IEEE80211W */
++
++			goto xmitframe_coalesce_success;
++		}
++	}
++	else {
++		/* unicast robust mgmt frame */
++		#if DBG_MGMT_XMIT_COALESEC_DUMP
++		if (subtype == WIFI_DEAUTH) {
++			RTW_INFO(FUNC_ADPT_FMT" unicast deauth to "MAC_FMT"\n"
++				, FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra));
++		} else if (subtype == WIFI_DISASSOC) {
++			RTW_INFO(FUNC_ADPT_FMT" unicast disassoc to "MAC_FMT"\n"
++				, FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra));
++		} else if (subtype == WIFI_ACTION) {
++			RTW_INFO(FUNC_ADPT_FMT" unicast action(%u) to "MAC_FMT"\n"
++				, FUNC_ADPT_ARG(padapter), category, MAC_ARG(pattrib->ra));
++		}
++		#endif
++
++		pn = &psta->dot11txpn;
++		cipher = psta->dot118021XPrivacy;
++		kid = 0;
++
++		_rtw_memcpy(pattrib->dot118021x_UncstKey.skey
++			, psta->dot118021x_UncstKey.skey
++			, (cipher & _SEC_TYPE_256_) ? 32 : 16);
++
++		/* To use wrong key */
++		if (pattrib->key_type == IEEE80211W_WRONG_KEY) {
++			RTW_INFO("use wrong key\n");
++			pattrib->dot118021x_UncstKey.skey[0] = 0xff;
++		}
++	}
++
++	#if DBG_MGMT_XMIT_ENC_DUMP
++	/* before encrypt dump the management packet content */
++	{
++		int i;
++		printk("Management pkt: ");
++		for(i=0; i<pattrib->pktlen; i++)
++		printk(" %02x ", pframe[i]);
++		printk("=======\n");
++	}
++	#endif
++
++	/* bakeup original management packet */
++	_rtw_memcpy(tmp_buf, pframe, pattrib->pktlen);
++	/* move to data portion */
++	pframe += pattrib->hdrlen;
++
++	if (pattrib->key_type != IEEE80211W_NO_KEY) {
++		pattrib->encrypt = cipher;
++		pattrib->bswenc = _TRUE;
++	}
++
++	/*
++	* 802.11w encrypted management packet must be:
++	* _AES_, _CCMP_256_, _GCMP_, _GCMP_256_
++	*/
++	switch (pattrib->encrypt) {
++	case _AES_:
++		pattrib->iv_len = 8;
++		pattrib->icv_len = 8;
++		AES_IV(pattrib->iv, (*pn), kid);
++		break;
++	case _CCMP_256_:
++		pattrib->iv_len = 8;
++		pattrib->icv_len = 16;
++		AES_IV(pattrib->iv, (*pn), kid);
++		break;
++	case _GCMP_:
++	case _GCMP_256_:
++		pattrib->iv_len = 8;
++		pattrib->icv_len = 16;
++		GCMP_IV(pattrib->iv, (*pn), kid);
++		break;
++	default:
++		goto xmitframe_coalesce_fail;
++	}
++
++	/* insert iv header into management frame */
++	_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);
++	pframe += pattrib->iv_len;
++	/* copy mgmt data portion after CCMP header */
++	_rtw_memcpy(pframe, tmp_buf + pattrib->hdrlen, pattrib->pktlen - pattrib->hdrlen);
++	/* move pframe to end of mgmt pkt */
++	pframe += pattrib->pktlen - pattrib->hdrlen;
++	/* add 8 bytes CCMP IV header to length */
++	pattrib->pktlen += pattrib->iv_len;
++
++	#if DBG_MGMT_XMIT_ENC_DUMP
++	/* dump management packet include AES IV header */
++	{
++		int i;
++		printk("Management pkt + IV: ");
++		/* for(i=0; i<pattrib->pktlen; i++) */
++
++		printk("@@@@@@@@@@@@@\n");
++	}
++	#endif
++
++	if ((pattrib->icv_len > 0) && (pattrib->bswenc)) {
++		_rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);
++		pframe += pattrib->icv_len;
++	}
++	/* add 8 bytes MIC */
++	pattrib->pktlen += pattrib->icv_len;
++	/* set final tx command size */
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	/* set protected bit must be beofre SW encrypt */
++	SetPrivacy(mem_start);
++
++	#if DBG_MGMT_XMIT_ENC_DUMP
++	/* dump management packet include AES header */
++	{
++		int i;
++		printk("prepare to enc Management pkt + IV: ");
++		for (i = 0; i < pattrib->pktlen; i++)
++			printk(" %02x ", mem_start[i]);
++		printk("@@@@@@@@@@@@@\n");
++	}
++	#endif
++
++	/* software encrypt */
++	xmitframe_swencrypt(padapter, pxmitframe);
++
++xmitframe_coalesce_success:
++	_exit_critical_bh(&padapter->security_key_mutex, &irqL);
++	rtw_mfree(BIP_AAD, ori_len);
++	return _SUCCESS;
++
++xmitframe_coalesce_fail:
++	_exit_critical_bh(&padapter->security_key_mutex, &irqL);
++	rtw_mfree(BIP_AAD, ori_len);
++
++	return _FAIL;
++}
++#endif /* defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) */
++
++/* Logical Link Control(LLC) SubNetwork Attachment Point(SNAP) header
++ * IEEE LLC/SNAP header contains 8 octets
++ * First 3 octets comprise the LLC portion
++ * SNAP portion, 5 octets, is divided into two fields:
++ *	Organizationally Unique Identifier(OUI), 3 octets,
++ *	type, defined by that organization, 2 octets.
++ */
++s32 rtw_put_snap(u8 *data, u16 h_proto)
++{
++	struct ieee80211_snap_hdr *snap;
++	u8 *oui;
++
++
++	snap = (struct ieee80211_snap_hdr *)data;
++	snap->dsap = 0xaa;
++	snap->ssap = 0xaa;
++	snap->ctrl = 0x03;
++
++	if (h_proto == 0x8137 || h_proto == 0x80f3)
++		oui = P802_1H_OUI;
++	else
++		oui = RFC1042_OUI;
++
++	snap->oui[0] = oui[0];
++	snap->oui[1] = oui[1];
++	snap->oui[2] = oui[2];
++
++	*(u16 *)(data + SNAP_SIZE) = htons(h_proto);
++
++
++	return SNAP_SIZE + sizeof(u16);
++}
++
++void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len)
++{
++
++	uint	protection;
++	u8	*perp;
++	sint	 erp_len;
++	struct	xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	struct	registry_priv *pregistrypriv = &padapter->registrypriv;
++
++
++	switch (pxmitpriv->vcs_setting) {
++	case DISABLE_VCS:
++		pxmitpriv->vcs = NONE_VCS;
++		break;
++
++	case ENABLE_VCS:
++		break;
++
++	case AUTO_VCS:
++	default:
++		perp = rtw_get_ie(ie, _ERPINFO_IE_, &erp_len, ie_len);
++		if (perp == NULL)
++			pxmitpriv->vcs = NONE_VCS;
++		else {
++			protection = (*(perp + 2)) & BIT(1);
++			if (protection) {
++				if (pregistrypriv->vcs_type == RTS_CTS)
++					pxmitpriv->vcs = RTS_CTS;
++				else
++					pxmitpriv->vcs = CTS_TO_SELF;
++			} else
++				pxmitpriv->vcs = NONE_VCS;
++		}
++
++		break;
++
++	}
++
++
++}
++
++void rtw_count_tx_stats(PADAPTER padapter, struct xmit_frame *pxmitframe, int sz)
++{
++	struct sta_info *psta = NULL;
++	struct stainfo_stats *pstats = NULL;
++	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	u8	pkt_num = 1;
++
++	if ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) {
++#if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++		pkt_num = pxmitframe->agg_num;
++#endif
++		pmlmepriv->LinkDetectInfo.NumTxOkInPeriod += pkt_num;
++
++		pxmitpriv->tx_pkts += pkt_num;
++
++		pxmitpriv->tx_bytes += sz;
++
++		psta = pxmitframe->attrib.psta;
++		if (psta) {
++			pstats = &psta->sta_stats;
++
++			pstats->tx_pkts += pkt_num;
++
++			pstats->tx_bytes += sz;
++			#if defined(CONFIG_CHECK_LEAVE_LPS) && defined(CONFIG_LPS_CHK_BY_TP)
++			if (adapter_to_pwrctl(padapter)->lps_chk_by_tp)
++				traffic_check_for_leave_lps_by_tp(padapter, _TRUE, psta);
++			#endif /* CONFIG_LPS */
++		}
++
++#ifdef CONFIG_CHECK_LEAVE_LPS
++		/* traffic_check_for_leave_lps(padapter, _TRUE); */
++#endif /* CONFIG_CHECK_LEAVE_LPS */
++
++	}
++}
++
++static struct xmit_buf *__rtw_alloc_cmd_xmitbuf(struct xmit_priv *pxmitpriv,
++		enum cmdbuf_type buf_type)
++{
++	struct xmit_buf *pxmitbuf =  NULL;
++
++
++	pxmitbuf = &pxmitpriv->pcmd_xmitbuf[buf_type];
++	if (pxmitbuf !=  NULL) {
++		pxmitbuf->priv_data = NULL;
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++		pxmitbuf->len = 0;
++		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
++		pxmitbuf->agg_num = 0;
++		pxmitbuf->pg_num = 0;
++#endif
++#ifdef CONFIG_PCI_HCI
++		pxmitbuf->len = 0;
++#ifdef CONFIG_TRX_BD_ARCH
++		/*pxmitbuf->buf_desc = NULL;*/
++#else
++		pxmitbuf->desc = NULL;
++#endif
++#endif
++
++		if (pxmitbuf->sctx) {
++			RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__);
++			rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC);
++		}
++	} else
++		RTW_INFO("%s fail, no xmitbuf available !!!\n", __func__);
++
++	return pxmitbuf;
++}
++
++struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv,
++		enum cmdbuf_type buf_type)
++{
++	struct xmit_frame		*pcmdframe;
++	struct xmit_buf		*pxmitbuf;
++
++	pcmdframe = rtw_alloc_xmitframe(pxmitpriv, 0);
++	if (pcmdframe == NULL) {
++		RTW_INFO("%s, alloc xmitframe fail\n", __FUNCTION__);
++		return NULL;
++	}
++
++	pxmitbuf = __rtw_alloc_cmd_xmitbuf(pxmitpriv, buf_type);
++	if (pxmitbuf == NULL) {
++		RTW_INFO("%s, alloc xmitbuf fail\n", __FUNCTION__);
++		rtw_free_xmitframe(pxmitpriv, pcmdframe);
++		return NULL;
++	}
++
++	pcmdframe->frame_tag = MGNT_FRAMETAG;
++
++	pcmdframe->pxmitbuf = pxmitbuf;
++
++	pcmdframe->buf_addr = pxmitbuf->pbuf;
++
++	/* initial memory to zero */
++	_rtw_memset(pcmdframe->buf_addr, 0, MAX_CMDBUF_SZ);
++
++	pxmitbuf->priv_data = pcmdframe;
++
++	return pcmdframe;
++
++}
++
++struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv)
++{
++	_irqL irqL;
++	struct xmit_buf *pxmitbuf =  NULL;
++	_list *plist, *phead;
++	_queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue;
++
++
++	_enter_critical(&pfree_queue->lock, &irqL);
++
++	if (_rtw_queue_empty(pfree_queue) == _TRUE)
++		pxmitbuf = NULL;
++	else {
++
++		phead = get_list_head(pfree_queue);
++
++		plist = get_next(phead);
++
++		pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
++
++		rtw_list_delete(&(pxmitbuf->list));
++	}
++
++	if (pxmitbuf !=  NULL) {
++		pxmitpriv->free_xmit_extbuf_cnt--;
++#ifdef DBG_XMIT_BUF_EXT
++		RTW_INFO("DBG_XMIT_BUF_EXT ALLOC no=%d,  free_xmit_extbuf_cnt=%d\n", pxmitbuf->no, pxmitpriv->free_xmit_extbuf_cnt);
++#endif
++
++
++		pxmitbuf->priv_data = NULL;
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++		pxmitbuf->len = 0;
++		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
++		pxmitbuf->agg_num = 1;
++#endif
++#ifdef CONFIG_PCI_HCI
++		pxmitbuf->len = 0;
++#ifdef CONFIG_TRX_BD_ARCH
++		/*pxmitbuf->buf_desc = NULL;*/
++#else
++		pxmitbuf->desc = NULL;
++#endif
++#endif
++
++		if (pxmitbuf->sctx) {
++			RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__);
++			rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC);
++		}
++
++	}
++
++	_exit_critical(&pfree_queue->lock, &irqL);
++
++
++	return pxmitbuf;
++}
++
++s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
++{
++	_irqL irqL;
++	_queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue;
++
++
++	if (pxmitbuf == NULL)
++		return _FAIL;
++
++	_enter_critical(&pfree_queue->lock, &irqL);
++
++	rtw_list_delete(&pxmitbuf->list);
++
++	rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_queue));
++	pxmitpriv->free_xmit_extbuf_cnt++;
++#ifdef DBG_XMIT_BUF_EXT
++	RTW_INFO("DBG_XMIT_BUF_EXT FREE no=%d, free_xmit_extbuf_cnt=%d\n", pxmitbuf->no , pxmitpriv->free_xmit_extbuf_cnt);
++#endif
++
++	_exit_critical(&pfree_queue->lock, &irqL);
++
++
++	return _SUCCESS;
++}
++
++struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv)
++{
++	_irqL irqL;
++	struct xmit_buf *pxmitbuf =  NULL;
++	_list *plist, *phead;
++	_queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue;
++
++
++	/* RTW_INFO("+rtw_alloc_xmitbuf\n"); */
++
++	_enter_critical(&pfree_xmitbuf_queue->lock, &irqL);
++
++	if (_rtw_queue_empty(pfree_xmitbuf_queue) == _TRUE)
++		pxmitbuf = NULL;
++	else {
++
++		phead = get_list_head(pfree_xmitbuf_queue);
++
++		plist = get_next(phead);
++
++		pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
++
++		rtw_list_delete(&(pxmitbuf->list));
++	}
++
++	if (pxmitbuf !=  NULL) {
++		pxmitpriv->free_xmitbuf_cnt--;
++#ifdef DBG_XMIT_BUF
++		RTW_INFO("DBG_XMIT_BUF ALLOC no=%d,  free_xmitbuf_cnt=%d\n", pxmitbuf->no, pxmitpriv->free_xmitbuf_cnt);
++#endif
++		/* RTW_INFO("alloc, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); */
++
++		pxmitbuf->priv_data = NULL;
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++		pxmitbuf->len = 0;
++		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
++		pxmitbuf->agg_num = 0;
++		pxmitbuf->pg_num = 0;
++#endif
++#ifdef CONFIG_PCI_HCI
++		pxmitbuf->len = 0;
++#ifdef CONFIG_TRX_BD_ARCH
++		/*pxmitbuf->buf_desc = NULL;*/
++#else
++		pxmitbuf->desc = NULL;
++#endif
++#endif
++
++		if (pxmitbuf->sctx) {
++			RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__);
++			rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC);
++		}
++	}
++#ifdef DBG_XMIT_BUF
++	else
++		RTW_INFO("DBG_XMIT_BUF rtw_alloc_xmitbuf return NULL\n");
++#endif
++
++	_exit_critical(&pfree_xmitbuf_queue->lock, &irqL);
++
++
++	return pxmitbuf;
++}
++
++s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
++{
++	_irqL irqL;
++	_queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue;
++
++
++	/* RTW_INFO("+rtw_free_xmitbuf\n"); */
++
++	if (pxmitbuf == NULL)
++		return _FAIL;
++
++	if (pxmitbuf->sctx) {
++		RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__);
++		rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_FREE);
++	}
++
++	if (pxmitbuf->buf_tag == XMITBUF_CMD) {
++	} else if (pxmitbuf->buf_tag == XMITBUF_MGNT)
++		rtw_free_xmitbuf_ext(pxmitpriv, pxmitbuf);
++	else {
++		_enter_critical(&pfree_xmitbuf_queue->lock, &irqL);
++
++		rtw_list_delete(&pxmitbuf->list);
++
++		rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_xmitbuf_queue));
++
++		pxmitpriv->free_xmitbuf_cnt++;
++		/* RTW_INFO("FREE, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); */
++#ifdef DBG_XMIT_BUF
++		RTW_INFO("DBG_XMIT_BUF FREE no=%d, free_xmitbuf_cnt=%d\n", pxmitbuf->no , pxmitpriv->free_xmitbuf_cnt);
++#endif
++		_exit_critical(&pfree_xmitbuf_queue->lock, &irqL);
++	}
++
++
++	return _SUCCESS;
++}
++
++void rtw_init_xmitframe(struct xmit_frame *pxframe)
++{
++	if (pxframe !=  NULL) { /* default value setting */
++		pxframe->buf_addr = NULL;
++		pxframe->pxmitbuf = NULL;
++
++		_rtw_memset(&pxframe->attrib, 0, sizeof(struct pkt_attrib));
++		/* pxframe->attrib.psta = NULL; */
++
++		pxframe->frame_tag = DATA_FRAMETAG;
++
++#ifdef CONFIG_USB_HCI
++		pxframe->pkt = NULL;
++#ifdef USB_PACKET_OFFSET_SZ
++		pxframe->pkt_offset = (PACKET_OFFSET_SZ / 8);
++#else
++		pxframe->pkt_offset = 1;/* default use pkt_offset to fill tx desc */
++#endif
++
++#ifdef CONFIG_USB_TX_AGGREGATION
++		pxframe->agg_num = 1;
++#endif
++
++#endif /* #ifdef CONFIG_USB_HCI */
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++		pxframe->pg_num = 1;
++		pxframe->agg_num = 1;
++#endif
++
++#ifdef CONFIG_XMIT_ACK
++		pxframe->ack_report = 0;
++#endif
++
++	}
++}
++
++/*
++Calling context:
++1. OS_TXENTRY
++2. RXENTRY (rx_thread or RX_ISR/RX_CallBack)
++
++If we turn on USE_RXTHREAD, then, no need for critical section.
++Otherwise, we must use _enter/_exit critical to protect free_xmit_queue...
++
++Must be very very cautious...
++
++*/
++struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv, u16 os_qid)
++{
++	/*
++		Please remember to use all the osdep_service api,
++		and lock/unlock or _enter/_exit critical to protect
++		pfree_xmit_queue
++	*/
++
++	_irqL irqL;
++	struct xmit_frame *pxframe = NULL;
++	_list *plist, *phead;
++	_queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue;
++
++	_enter_critical_bh(&pfree_xmit_queue->lock, &irqL);
++
++	if (_rtw_queue_empty(pfree_xmit_queue) == _TRUE) {
++		pxframe =  NULL;
++	} else {
++		phead = get_list_head(pfree_xmit_queue);
++
++		plist = get_next(phead);
++
++		pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
++
++		rtw_list_delete(&(pxframe->list));
++		pxmitpriv->free_xmitframe_cnt--;
++		pxframe->os_qid = os_qid;
++	}
++
++	_exit_critical_bh(&pfree_xmit_queue->lock, &irqL);
++
++	if (pxframe)
++		rtw_os_check_stop_queue(pxmitpriv->adapter, os_qid);
++
++	rtw_init_xmitframe(pxframe);
++
++
++	return pxframe;
++}
++
++struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv)
++{
++	_irqL irqL;
++	struct xmit_frame *pxframe = NULL;
++	_list *plist, *phead;
++	_queue *queue = &pxmitpriv->free_xframe_ext_queue;
++
++
++	_enter_critical_bh(&queue->lock, &irqL);
++
++	if (_rtw_queue_empty(queue) == _TRUE) {
++		pxframe =  NULL;
++	} else {
++		phead = get_list_head(queue);
++		plist = get_next(phead);
++		pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
++
++		rtw_list_delete(&(pxframe->list));
++		pxmitpriv->free_xframe_ext_cnt--;
++	}
++
++	_exit_critical_bh(&queue->lock, &irqL);
++
++	rtw_init_xmitframe(pxframe);
++
++
++	return pxframe;
++}
++
++struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv)
++{
++	struct xmit_frame *pxframe = NULL;
++	u8 *alloc_addr;
++
++	alloc_addr = rtw_zmalloc(sizeof(struct xmit_frame) + 4);
++
++	if (alloc_addr == NULL)
++		goto exit;
++
++	pxframe = (struct xmit_frame *)N_BYTE_ALIGMENT((SIZE_PTR)(alloc_addr), 4);
++	pxframe->alloc_addr = alloc_addr;
++
++	pxframe->padapter = pxmitpriv->adapter;
++	pxframe->frame_tag = NULL_FRAMETAG;
++
++	pxframe->pkt = NULL;
++
++	pxframe->buf_addr = NULL;
++	pxframe->pxmitbuf = NULL;
++
++	rtw_init_xmitframe(pxframe);
++
++	RTW_INFO("################## %s ##################\n", __func__);
++
++exit:
++	return pxframe;
++}
++
++s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe)
++{
++	_irqL irqL;
++	_queue *queue = NULL;
++	_adapter *padapter = pxmitpriv->adapter;
++	_pkt *pndis_pkt = NULL;
++
++
++	if (pxmitframe == NULL) {
++		goto exit;
++	}
++
++	if (pxmitframe->pkt) {
++		pndis_pkt = pxmitframe->pkt;
++		pxmitframe->pkt = NULL;
++	}
++
++	if (pxmitframe->alloc_addr) {
++		RTW_INFO("################## %s with alloc_addr ##################\n", __func__);
++		rtw_mfree(pxmitframe->alloc_addr, sizeof(struct xmit_frame) + 4);
++		goto check_pkt_complete;
++	}
++
++	if (pxmitframe->ext_tag == 0)
++		queue = &pxmitpriv->free_xmit_queue;
++	else if (pxmitframe->ext_tag == 1)
++		queue = &pxmitpriv->free_xframe_ext_queue;
++	else
++		rtw_warn_on(1);
++
++	_enter_critical_bh(&queue->lock, &irqL);
++
++	rtw_list_delete(&pxmitframe->list);
++	rtw_list_insert_tail(&pxmitframe->list, get_list_head(queue));
++	if (pxmitframe->ext_tag == 0) {
++		pxmitpriv->free_xmitframe_cnt++;
++	} else if (pxmitframe->ext_tag == 1) {
++		pxmitpriv->free_xframe_ext_cnt++;
++	} else {
++	}
++
++	_exit_critical_bh(&queue->lock, &irqL);
++
++	if (queue == &pxmitpriv->free_xmit_queue)
++		rtw_os_check_wakup_queue(padapter, pxmitframe->os_qid);
++
++check_pkt_complete:
++
++	if (pndis_pkt)
++		rtw_os_pkt_complete(padapter, pndis_pkt);
++
++exit:
++
++
++	return _SUCCESS;
++}
++
++void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue)
++{
++	_irqL irqL;
++	_list	*plist, *phead;
++	struct	xmit_frame	*pxmitframe;
++
++
++	_enter_critical_bh(&(pframequeue->lock), &irqL);
++
++	phead = get_list_head(pframequeue);
++	plist = get_next(phead);
++
++	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
++
++		pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
++
++		plist = get_next(plist);
++
++		rtw_free_xmitframe(pxmitpriv, pxmitframe);
++
++	}
++	_exit_critical_bh(&(pframequeue->lock), &irqL);
++
++}
++
++s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++	DBG_COUNTER(padapter->tx_logs.core_tx_enqueue);
++	if (rtw_xmit_classifier(padapter, pxmitframe) == _FAIL) {
++		/*		pxmitframe->pkt = NULL; */
++		return _FAIL;
++	}
++
++	return _SUCCESS;
++}
++
++static struct xmit_frame *dequeue_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, _queue *pframe_queue)
++{
++	_list	*xmitframe_plist, *xmitframe_phead;
++	struct	xmit_frame	*pxmitframe = NULL;
++
++	xmitframe_phead = get_list_head(pframe_queue);
++	xmitframe_plist = get_next(xmitframe_phead);
++
++	while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
++		pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
++
++		/* xmitframe_plist = get_next(xmitframe_plist); */
++
++		/*#ifdef RTK_DMP_PLATFORM
++		#ifdef CONFIG_USB_TX_AGGREGATION
++				if((ptxservq->qcnt>0) && (ptxservq->qcnt<=2))
++				{
++					pxmitframe = NULL;
++
++					tasklet_schedule(&pxmitpriv->xmit_tasklet);
++
++					break;
++				}
++		#endif
++		#endif*/
++		rtw_list_delete(&pxmitframe->list);
++
++		ptxservq->qcnt--;
++
++		/* rtw_list_insert_tail(&pxmitframe->list, &phwxmit->pending); */
++
++		/* ptxservq->qcnt--; */
++
++		break;
++
++		/* pxmitframe = NULL; */
++
++	}
++
++	return pxmitframe;
++}
++
++static struct xmit_frame *get_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, _queue *pframe_queue)
++{
++	_list	*xmitframe_plist, *xmitframe_phead;
++	struct	xmit_frame	*pxmitframe = NULL;
++
++	xmitframe_phead = get_list_head(pframe_queue);
++	xmitframe_plist = get_next(xmitframe_phead);
++
++	while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
++		pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
++		break;
++	}
++
++	return pxmitframe;
++}
++
++struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame)
++{
++	_irqL irqL0;
++	_list *sta_plist, *sta_phead;
++	struct hw_xmit *phwxmit_i = pxmitpriv->hwxmits;
++	sint entry =  pxmitpriv->hwxmit_entry;
++
++	struct hw_xmit *phwxmit;
++	struct tx_servq *ptxservq = NULL;
++	_queue *pframe_queue = NULL;
++	struct xmit_frame *pxmitframe = NULL;
++	_adapter *padapter = pxmitpriv->adapter;
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++	int i, inx[4];
++
++	inx[0] = 0;
++	inx[1] = 1;
++	inx[2] = 2;
++	inx[3] = 3;
++
++	*num_frame = 0;
++
++	/*No amsdu when wifi_spec on*/
++	if (pregpriv->wifi_spec == 1) {
++		return NULL;
++	}
++
++	_enter_critical_bh(&pxmitpriv->lock, &irqL0);
++
++	for (i = 0; i < entry; i++) {
++		phwxmit = phwxmit_i + inx[i];
++
++		sta_phead = get_list_head(phwxmit->sta_queue);
++		sta_plist = get_next(sta_phead);
++
++		while ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) {
++
++			ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending);
++			pframe_queue = &ptxservq->sta_pending;
++
++			if(ptxservq->qcnt)
++			{
++				*num_frame = ptxservq->qcnt;
++				pxmitframe = get_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue);
++				goto exit;
++			}
++			sta_plist = get_next(sta_plist);
++		}
++	}
++
++exit:
++
++	_exit_critical_bh(&pxmitpriv->lock, &irqL0);
++
++	return pxmitframe;
++}
++
++
++struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry)
++{
++	_irqL irqL0;
++	_list *sta_plist, *sta_phead;
++	struct hw_xmit *phwxmit;
++	struct tx_servq *ptxservq = NULL;
++	_queue *pframe_queue = NULL;
++	struct xmit_frame *pxmitframe = NULL;
++	_adapter *padapter = pxmitpriv->adapter;
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++	int i, inx[4];
++
++	inx[0] = 0;
++	inx[1] = 1;
++	inx[2] = 2;
++	inx[3] = 3;
++
++	if (pregpriv->wifi_spec == 1) {
++		int j;
++#if 0
++		if (flags < XMIT_QUEUE_ENTRY) {
++			/* priority exchange according to the completed xmitbuf flags. */
++			inx[flags] = 0;
++			inx[0] = flags;
++		}
++#endif
++
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_PCI_HCI)
++		for (j = 0; j < 4; j++)
++			inx[j] = pxmitpriv->wmm_para_seq[j];
++#endif
++	}
++
++	_enter_critical_bh(&pxmitpriv->lock, &irqL0);
++
++	for (i = 0; i < entry; i++) {
++		phwxmit = phwxmit_i + inx[i];
++
++		/* _enter_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */
++
++		sta_phead = get_list_head(phwxmit->sta_queue);
++		sta_plist = get_next(sta_phead);
++
++		while ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) {
++
++			ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending);
++
++			pframe_queue = &ptxservq->sta_pending;
++
++			pxmitframe = dequeue_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue);
++
++			if (pxmitframe) {
++				phwxmit->accnt--;
++
++				/* Remove sta node when there is no pending packets. */
++				if (_rtw_queue_empty(pframe_queue)) /* must be done after get_next and before break */
++					rtw_list_delete(&ptxservq->tx_pending);
++
++				/* _exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */
++
++				goto exit;
++			}
++
++			sta_plist = get_next(sta_plist);
++
++		}
++
++		/* _exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */
++
++	}
++
++exit:
++
++	_exit_critical_bh(&pxmitpriv->lock, &irqL0);
++
++	return pxmitframe;
++}
++
++#if 1
++struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac)
++{
++	struct tx_servq *ptxservq = NULL;
++
++
++	switch (up) {
++	case 1:
++	case 2:
++		ptxservq = &(psta->sta_xmitpriv.bk_q);
++		*(ac) = 3;
++		break;
++
++	case 4:
++	case 5:
++		ptxservq = &(psta->sta_xmitpriv.vi_q);
++		*(ac) = 1;
++		break;
++
++	case 6:
++	case 7:
++		ptxservq = &(psta->sta_xmitpriv.vo_q);
++		*(ac) = 0;
++		break;
++
++	case 0:
++	case 3:
++	default:
++		ptxservq = &(psta->sta_xmitpriv.be_q);
++		*(ac) = 2;
++		break;
++
++	}
++
++
++	return ptxservq;
++}
++#else
++__inline static struct tx_servq *rtw_get_sta_pending
++(_adapter *padapter, _queue **ppstapending, struct sta_info *psta, sint up)
++{
++	struct tx_servq *ptxservq;
++	struct hw_xmit *phwxmits =  padapter->xmitpriv.hwxmits;
++
++
++#ifdef CONFIG_RTL8711
++
++	if (IS_MCAST(psta->cmn.mac_addr)) {
++		ptxservq = &(psta->sta_xmitpriv.be_q); /* we will use be_q to queue bc/mc frames in BCMC_stainfo */
++		*ppstapending = &padapter->xmitpriv.bm_pending;
++	} else
++#endif
++	{
++		switch (up) {
++		case 1:
++		case 2:
++			ptxservq = &(psta->sta_xmitpriv.bk_q);
++			*ppstapending = &padapter->xmitpriv.bk_pending;
++			(phwxmits + 3)->accnt++;
++			break;
++
++		case 4:
++		case 5:
++			ptxservq = &(psta->sta_xmitpriv.vi_q);
++			*ppstapending = &padapter->xmitpriv.vi_pending;
++			(phwxmits + 1)->accnt++;
++			break;
++
++		case 6:
++		case 7:
++			ptxservq = &(psta->sta_xmitpriv.vo_q);
++			*ppstapending = &padapter->xmitpriv.vo_pending;
++			(phwxmits + 0)->accnt++;
++			break;
++
++		case 0:
++		case 3:
++		default:
++			ptxservq = &(psta->sta_xmitpriv.be_q);
++			*ppstapending = &padapter->xmitpriv.be_pending;
++			(phwxmits + 2)->accnt++;
++			break;
++
++		}
++
++	}
++
++
++	return ptxservq;
++}
++#endif
++
++/*
++ * Will enqueue pxmitframe to the proper queue,
++ * and indicate it to xx_pending list.....
++ */
++s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++	/* _irqL irqL0; */
++	u8	ac_index;
++	struct sta_info	*psta;
++	struct tx_servq	*ptxservq;
++	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
++	struct hw_xmit	*phwxmits =  padapter->xmitpriv.hwxmits;
++	sint res = _SUCCESS;
++
++
++	DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class);
++
++	/*
++		if (pattrib->psta) {
++			psta = pattrib->psta;
++		} else {
++			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
++			psta = rtw_get_stainfo(pstapriv, pattrib->ra);
++		}
++	*/
++
++	psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
++	if (pattrib->psta != psta) {
++		DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_sta);
++		RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
++		return _FAIL;
++	}
++
++	if (psta == NULL) {
++		DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_nosta);
++		res = _FAIL;
++		RTW_INFO("rtw_xmit_classifier: psta == NULL\n");
++		goto exit;
++	}
++
++	if (!(psta->state & WIFI_ASOC_STATE)) {
++		DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_fwlink);
++		RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
++		return _FAIL;
++	}
++
++	ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index));
++
++	/* _enter_critical(&pstapending->lock, &irqL0); */
++
++	if (rtw_is_list_empty(&ptxservq->tx_pending))
++		rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(phwxmits[ac_index].sta_queue));
++
++	/* _enter_critical(&ptxservq->sta_pending.lock, &irqL1); */
++
++	rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptxservq->sta_pending));
++	ptxservq->qcnt++;
++	phwxmits[ac_index].accnt++;
++
++	/* _exit_critical(&ptxservq->sta_pending.lock, &irqL1); */
++
++	/* _exit_critical(&pstapending->lock, &irqL0); */
++
++exit:
++
++
++	return res;
++}
++
++void rtw_alloc_hwxmits(_adapter *padapter)
++{
++	struct hw_xmit *hwxmits;
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++	pxmitpriv->hwxmit_entry = HWXMIT_ENTRY;
++
++	pxmitpriv->hwxmits = NULL;
++
++	pxmitpriv->hwxmits = (struct hw_xmit *)rtw_zmalloc(sizeof(struct hw_xmit) * pxmitpriv->hwxmit_entry);
++
++	if (pxmitpriv->hwxmits == NULL) {
++		RTW_INFO("alloc hwxmits fail!...\n");
++		return;
++	}
++
++	hwxmits = pxmitpriv->hwxmits;
++
++	if (pxmitpriv->hwxmit_entry == 5) {
++		/* pxmitpriv->bmc_txqueue.head = 0; */
++		/* hwxmits[0] .phwtxqueue = &pxmitpriv->bmc_txqueue; */
++		hwxmits[0] .sta_queue = &pxmitpriv->bm_pending;
++
++		/* pxmitpriv->vo_txqueue.head = 0; */
++		/* hwxmits[1] .phwtxqueue = &pxmitpriv->vo_txqueue; */
++		hwxmits[1] .sta_queue = &pxmitpriv->vo_pending;
++
++		/* pxmitpriv->vi_txqueue.head = 0; */
++		/* hwxmits[2] .phwtxqueue = &pxmitpriv->vi_txqueue; */
++		hwxmits[2] .sta_queue = &pxmitpriv->vi_pending;
++
++		/* pxmitpriv->bk_txqueue.head = 0; */
++		/* hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; */
++		hwxmits[3] .sta_queue = &pxmitpriv->bk_pending;
++
++		/* pxmitpriv->be_txqueue.head = 0; */
++		/* hwxmits[4] .phwtxqueue = &pxmitpriv->be_txqueue; */
++		hwxmits[4] .sta_queue = &pxmitpriv->be_pending;
++
++	} else if (pxmitpriv->hwxmit_entry == 4) {
++
++		/* pxmitpriv->vo_txqueue.head = 0; */
++		/* hwxmits[0] .phwtxqueue = &pxmitpriv->vo_txqueue; */
++		hwxmits[0] .sta_queue = &pxmitpriv->vo_pending;
++
++		/* pxmitpriv->vi_txqueue.head = 0; */
++		/* hwxmits[1] .phwtxqueue = &pxmitpriv->vi_txqueue; */
++		hwxmits[1] .sta_queue = &pxmitpriv->vi_pending;
++
++		/* pxmitpriv->be_txqueue.head = 0; */
++		/* hwxmits[2] .phwtxqueue = &pxmitpriv->be_txqueue; */
++		hwxmits[2] .sta_queue = &pxmitpriv->be_pending;
++
++		/* pxmitpriv->bk_txqueue.head = 0; */
++		/* hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; */
++		hwxmits[3] .sta_queue = &pxmitpriv->bk_pending;
++	} else {
++
++
++	}
++
++
++}
++
++void rtw_free_hwxmits(_adapter *padapter)
++{
++	struct hw_xmit *hwxmits;
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++	hwxmits = pxmitpriv->hwxmits;
++	if (hwxmits)
++		rtw_mfree((u8 *)hwxmits, (sizeof(struct hw_xmit) * pxmitpriv->hwxmit_entry));
++}
++
++void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry)
++{
++	sint i;
++	for (i = 0; i < entry; i++, phwxmit++) {
++		/* _rtw_spinlock_init(&phwxmit->xmit_lock); */
++		/* _rtw_init_listhead(&phwxmit->pending);		 */
++		/* phwxmit->txcmdcnt = 0; */
++		phwxmit->accnt = 0;
++	}
++}
++
++#ifdef CONFIG_BR_EXT
++int rtw_br_client_tx(_adapter *padapter, struct sk_buff **pskb)
++{
++	struct sk_buff *skb = *pskb;
++	_irqL irqL;
++	/* if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) */
++	{
++		void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb);
++		int res, is_vlan_tag = 0, i, do_nat25 = 1;
++		unsigned short vlan_hdr = 0;
++		void *br_port = NULL;
++
++		/* mac_clone_handle_frame(priv, skb); */
++
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++		br_port = padapter->pnetdev->br_port;
++#else   /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
++		rcu_read_lock();
++		br_port = rcu_dereference(padapter->pnetdev->rx_handler_data);
++		rcu_read_unlock();
++#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
++		_enter_critical_bh(&padapter->br_ext_lock, &irqL);
++		if (!(skb->data[0] & 1) &&
++		    br_port &&
++		    memcmp(skb->data + MACADDRLEN, padapter->br_mac, MACADDRLEN) &&
++		    *((unsigned short *)(skb->data + MACADDRLEN * 2)) != __constant_htons(ETH_P_8021Q) &&
++		    *((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP) &&
++		    !memcmp(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN) && padapter->scdb_entry) {
++			memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
++			padapter->scdb_entry->ageing_timer = jiffies;
++			_exit_critical_bh(&padapter->br_ext_lock, &irqL);
++		} else
++			/* if (!priv->pmib->ethBrExtInfo.nat25_disable)		 */
++		{
++			/*			if (priv->dev->br_port &&
++			 *				 !memcmp(skb->data+MACADDRLEN, priv->br_mac, MACADDRLEN)) { */
++#if 1
++			if (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_8021Q)) {
++				is_vlan_tag = 1;
++				vlan_hdr = *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2));
++				for (i = 0; i < 6; i++)
++					*((unsigned short *)(skb->data + MACADDRLEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + MACADDRLEN * 2 - 2 - i * 2));
++				skb_pull(skb, 4);
++			}
++			/* if SA == br_mac && skb== IP  => copy SIP to br_ip ?? why */
++			if (!memcmp(skb->data + MACADDRLEN, padapter->br_mac, MACADDRLEN) &&
++			    (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP)))
++				memcpy(padapter->br_ip, skb->data + WLAN_ETHHDR_LEN + 12, 4);
++
++			if (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP)) {
++				if (memcmp(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN)) {
++					void *scdb_findEntry(_adapter *priv, unsigned char *macAddr, unsigned char *ipAddr);
++
++					padapter->scdb_entry = (struct nat25_network_db_entry *)scdb_findEntry(padapter,
++						skb->data + MACADDRLEN, skb->data + WLAN_ETHHDR_LEN + 12);
++					if (padapter->scdb_entry != NULL) {
++						memcpy(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN);
++						memcpy(padapter->scdb_ip, skb->data + WLAN_ETHHDR_LEN + 12, 4);
++						padapter->scdb_entry->ageing_timer = jiffies;
++						do_nat25 = 0;
++					}
++				} else {
++					if (padapter->scdb_entry) {
++						padapter->scdb_entry->ageing_timer = jiffies;
++						do_nat25 = 0;
++					} else {
++						memset(padapter->scdb_mac, 0, MACADDRLEN);
++						memset(padapter->scdb_ip, 0, 4);
++					}
++				}
++			}
++			_exit_critical_bh(&padapter->br_ext_lock, &irqL);
++#endif /* 1 */
++			if (do_nat25) {
++				int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method);
++				if (nat25_db_handle(padapter, skb, NAT25_CHECK) == 0) {
++					struct sk_buff *newskb;
++
++					if (is_vlan_tag) {
++						skb_push(skb, 4);
++						for (i = 0; i < 6; i++)
++							*((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2));
++						*((unsigned short *)(skb->data + MACADDRLEN * 2)) = __constant_htons(ETH_P_8021Q);
++						*((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)) = vlan_hdr;
++					}
++
++					newskb = rtw_skb_copy(skb);
++					if (newskb == NULL) {
++						/* priv->ext_stats.tx_drops++; */
++						DEBUG_ERR("TX DROP: rtw_skb_copy fail!\n");
++						/* goto stop_proc; */
++						return -1;
++					}
++					rtw_skb_free(skb);
++
++					*pskb = skb = newskb;
++					if (is_vlan_tag) {
++						vlan_hdr = *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2));
++						for (i = 0; i < 6; i++)
++							*((unsigned short *)(skb->data + MACADDRLEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + MACADDRLEN * 2 - 2 - i * 2));
++						skb_pull(skb, 4);
++					}
++				}
++
++				if (skb_is_nonlinear(skb))
++					DEBUG_ERR("%s(): skb_is_nonlinear!!\n", __FUNCTION__);
++
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
++				res = skb_linearize(skb, GFP_ATOMIC);
++#else	/* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) */
++				res = skb_linearize(skb);
++#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) */
++				if (res < 0) {
++					DEBUG_ERR("TX DROP: skb_linearize fail!\n");
++					/* goto free_and_stop; */
++					return -1;
++				}
++
++				res = nat25_db_handle(padapter, skb, NAT25_INSERT);
++				if (res < 0) {
++					if (res == -2) {
++						/* priv->ext_stats.tx_drops++; */
++						DEBUG_ERR("TX DROP: nat25_db_handle fail!\n");
++						/* goto free_and_stop; */
++						return -1;
++
++					}
++					/* we just print warning message and let it go */
++					/* DEBUG_WARN("%s()-%d: nat25_db_handle INSERT Warning!\n", __FUNCTION__, __LINE__); */
++					/* return -1; */ /* return -1 will cause system crash on 2011/08/30! */
++					return 0;
++				}
++			}
++
++			memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
++
++			dhcp_flag_bcast(padapter, skb);
++
++			if (is_vlan_tag) {
++				skb_push(skb, 4);
++				for (i = 0; i < 6; i++)
++					*((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2));
++				*((unsigned short *)(skb->data + MACADDRLEN * 2)) = __constant_htons(ETH_P_8021Q);
++				*((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)) = vlan_hdr;
++			}
++		}
++#if 0
++		else {
++			if (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_8021Q))
++				is_vlan_tag = 1;
++
++			if (is_vlan_tag) {
++				if (ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A_VALN(skb->data))
++					memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
++			} else {
++				if (ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A(skb->data))
++					memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
++			}
++		}
++#endif /* 0 */
++
++		/* check if SA is equal to our MAC */
++		if (memcmp(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN)) {
++			/* priv->ext_stats.tx_drops++; */
++			DEBUG_ERR("TX DROP: untransformed frame SA:%02X%02X%02X%02X%02X%02X!\n",
++				skb->data[6], skb->data[7], skb->data[8], skb->data[9], skb->data[10], skb->data[11]);
++			/* goto free_and_stop; */
++			return -1;
++		}
++	}
++	return 0;
++}
++#endif /* CONFIG_BR_EXT */
++
++u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe)
++{
++	u32 addr;
++	struct pkt_attrib *pattrib = &pxmitframe->attrib;
++
++	switch (pattrib->qsel) {
++	case 0:
++	case 3:
++		addr = BE_QUEUE_INX;
++		break;
++	case 1:
++	case 2:
++		addr = BK_QUEUE_INX;
++		break;
++	case 4:
++	case 5:
++		addr = VI_QUEUE_INX;
++		break;
++	case 6:
++	case 7:
++		addr = VO_QUEUE_INX;
++		break;
++	case 0x10:
++		addr = BCN_QUEUE_INX;
++		break;
++	case 0x11: /* BC/MC in PS (HIQ) */
++		addr = HIGH_QUEUE_INX;
++		break;
++	case 0x13:
++		addr = TXCMD_QUEUE_INX;
++		break;
++	case 0x12:
++	default:
++		addr = MGT_QUEUE_INX;
++		break;
++
++	}
++
++	return addr;
++
++}
++
++static void do_queue_select(_adapter	*padapter, struct pkt_attrib *pattrib)
++{
++	u8 qsel;
++
++	qsel = pattrib->priority;
++
++#ifdef CONFIG_MCC_MODE
++	if (MCC_EN(padapter)) {
++		/* Under MCC */
++		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
++			if (padapter->mcc_adapterpriv.role == MCC_ROLE_GO
++			    || padapter->mcc_adapterpriv.role == MCC_ROLE_AP) {
++				pattrib->qsel = QSLT_VO; /* AP interface VO queue */
++				pattrib->priority  = QSLT_VO;
++			} else {
++				pattrib->qsel = QSLT_BE; /* STA interface BE queue */
++				pattrib->priority  = QSLT_BE;
++			}
++		} else
++			/* Not Under MCC */
++			pattrib->qsel = qsel;
++	} else
++		/* Not enable MCC */
++		pattrib->qsel = qsel;
++#else /* !CONFIG_MCC_MODE */
++	pattrib->qsel = qsel;
++#endif /* CONFIG_MCC_MODE */
++
++	/* high priority packet */
++	if (pattrib->hipriority_pkt) {
++		pattrib->qsel = QSLT_VO;
++		pattrib->priority  = QSLT_VO;
++	}
++}
++
++/*
++ * The main transmit(tx) entry
++ *
++ * Return
++ *	1	enqueue
++ *	0	success, hardware will handle this xmit frame(packet)
++ *	<0	fail
++ */
++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
++s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev)
++{
++	u16 frame_ctl;
++	struct ieee80211_radiotap_header rtap_hdr;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct pkt_file pktfile;
++	struct rtw_ieee80211_hdr *pwlanhdr;
++	struct pkt_attrib	*pattrib;
++	struct xmit_frame		*pmgntframe;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
++	unsigned char	*pframe;
++	u8 dummybuf[32];
++	int len = skb->len, rtap_len;
++
++
++	rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize);
++
++#ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL
++	if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header)))
++		goto fail;
++
++	_rtw_open_pktfile((_pkt *)skb, &pktfile);
++	_rtw_pktfile_read(&pktfile, (u8 *)(&rtap_hdr), sizeof(struct ieee80211_radiotap_header));
++	rtap_len = ieee80211_get_radiotap_len((u8 *)(&rtap_hdr));
++	if (unlikely(rtap_hdr.it_version))
++		goto fail;
++
++	if (unlikely(skb->len < rtap_len))
++		goto fail;
++
++	if (rtap_len != 12) {
++		RTW_INFO("radiotap len (should be 14): %d\n", rtap_len);
++		goto fail;
++	}
++	_rtw_pktfile_read(&pktfile, dummybuf, rtap_len-sizeof(struct ieee80211_radiotap_header));
++	len = len - rtap_len;
++#endif
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL) {
++		rtw_udelay_os(500);
++		goto fail;
++	}
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++//	_rtw_memcpy(pframe, (void *)checking, len);
++	_rtw_pktfile_read(&pktfile, pframe, len);
++
++
++	/* Check DATA/MGNT frames */
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++	frame_ctl = le16_to_cpu(pwlanhdr->frame_ctl);
++	if ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) {
++
++		pattrib = &pmgntframe->attrib;
++		update_monitor_frame_attrib(padapter, pattrib);
++
++		if (is_broadcast_mac_addr(pwlanhdr->addr3) || is_broadcast_mac_addr(pwlanhdr->addr1))
++			pattrib->rate = MGN_24M;
++
++	} else {
++
++		pattrib = &pmgntframe->attrib;
++		update_mgntframe_attrib(padapter, pattrib);
++
++	}
++	pattrib->retry_ctrl = _FALSE;
++	pattrib->pktlen = len;
++	pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
++	pattrib->seqnum = pmlmeext->mgnt_seq;
++	pmlmeext->mgnt_seq++;
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(padapter, pmgntframe);
++
++fail:
++	rtw_skb_free(skb);
++	return 0;
++}
++#endif
++
++/*
++ *
++ * Return _TRUE when frame has been put to queue, otherwise return _FALSE.
++ */
++static u8 xmit_enqueue(struct _ADAPTER *a, struct xmit_frame *frame)
++{
++	struct sta_info *sta = NULL;
++	struct pkt_attrib *attrib = NULL;
++	_irqL irqL;
++	_list *head;
++	u8 ret = _TRUE;
++
++
++	attrib = &frame->attrib;
++	sta = attrib->psta;
++	if (!sta)
++		return _FALSE;
++
++	_enter_critical_bh(&sta->tx_queue.lock, &irqL);
++
++	head = get_list_head(&sta->tx_queue);
++
++	if ((rtw_is_list_empty(head) == _TRUE) && (!sta->tx_q_enable)) {
++		ret = _FALSE;
++		goto exit;
++	}
++
++	rtw_list_insert_tail(&frame->list, head);
++	RTW_INFO(FUNC_ADPT_FMT ": en-queue tx pkt for macid=%d\n",
++		 FUNC_ADPT_ARG(a), sta->cmn.mac_id);
++
++exit:
++	_exit_critical_bh(&sta->tx_queue.lock, &irqL);
++
++	return ret;
++}
++
++static void xmit_dequeue(struct sta_info *sta)
++{
++	struct _ADAPTER *a;
++	_irqL irqL;
++	_list *head, *list;
++	struct xmit_frame *frame;
++
++
++	a = sta->padapter;
++
++	_enter_critical_bh(&sta->tx_queue.lock, &irqL);
++
++	head = get_list_head(&sta->tx_queue);
++
++	do {
++		if (rtw_is_list_empty(head) == _TRUE)
++			break;
++
++		list = get_next(head);
++		rtw_list_delete(list);
++		frame = LIST_CONTAINOR(list, struct xmit_frame, list);
++		RTW_INFO(FUNC_ADPT_FMT ": de-queue tx frame of macid=%d\n",
++			 FUNC_ADPT_ARG(a), sta->cmn.mac_id);
++
++		rtw_hal_xmit(a, frame);
++	} while (1);
++
++	_exit_critical_bh(&sta->tx_queue.lock, &irqL);
++}
++
++void rtw_xmit_dequeue_callback(_workitem *work)
++{
++	struct sta_info *sta;
++
++
++	sta = container_of(work, struct sta_info, tx_q_work);
++	xmit_dequeue(sta);
++}
++
++void rtw_xmit_queue_set(struct sta_info *sta)
++{
++	_irqL irqL;
++
++	_enter_critical_bh(&sta->tx_queue.lock, &irqL);
++
++	if (sta->tx_q_enable) {
++		RTW_WARN(FUNC_ADPT_FMT ": duplicated set!\n",
++			 FUNC_ADPT_ARG(sta->padapter));
++		goto exit;
++	}
++	sta->tx_q_enable = 1;
++	RTW_INFO(FUNC_ADPT_FMT ": enable queue TX for macid=%d\n",
++		 FUNC_ADPT_ARG(sta->padapter), sta->cmn.mac_id);
++
++exit:
++	_exit_critical_bh(&sta->tx_queue.lock, &irqL);
++}
++
++void rtw_xmit_queue_clear(struct sta_info *sta)
++{
++	_irqL irqL;
++
++	_enter_critical_bh(&sta->tx_queue.lock, &irqL);
++
++	if (!sta->tx_q_enable) {
++		RTW_WARN(FUNC_ADPT_FMT ": tx queue for macid=%d "
++			 "not be enabled!\n",
++			 FUNC_ADPT_ARG(sta->padapter), sta->cmn.mac_id);
++		goto exit;
++	}
++
++	sta->tx_q_enable = 0;
++	RTW_INFO(FUNC_ADPT_FMT ": disable queue TX for macid=%d\n",
++		 FUNC_ADPT_ARG(sta->padapter), sta->cmn.mac_id);
++
++	_set_workitem(&sta->tx_q_work);
++
++exit:
++	_exit_critical_bh(&sta->tx_queue.lock, &irqL);
++}
++
++/*
++ * The main transmit(tx) entry post handle
++ *
++ * Return
++ *	1	enqueue
++ *	0	success, hardware will handle this xmit frame(packet)
++ *	<0	fail
++ */
++s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, _pkt *pkt)
++{
++#ifdef CONFIG_AP_MODE
++	_irqL irqL0;
++#endif
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	s32 res;
++
++	res = update_attrib(padapter, pkt, &pxmitframe->attrib);
++
++#ifdef CONFIG_MCC_MODE
++	/* record data kernel TX to driver to check MCC concurrent TX */
++	rtw_hal_mcc_calc_tx_bytes_from_kernel(padapter, pxmitframe->attrib.pktlen);
++#endif /* CONFIG_MCC_MODE */
++
++#ifdef CONFIG_WAPI_SUPPORT
++	if (pxmitframe->attrib.ether_type != 0x88B4) {
++		if (rtw_wapi_drop_for_key_absent(padapter, pxmitframe->attrib.ra)) {
++			WAPI_TRACE(WAPI_RX, "drop for key absend when tx\n");
++			res = _FAIL;
++		}
++	}
++#endif
++	if (res == _FAIL) {
++		/*RTW_INFO("%s-"ADPT_FMT" update attrib fail\n", __func__, ADPT_ARG(padapter));*/
++#ifdef DBG_TX_DROP_FRAME
++		RTW_INFO("DBG_TX_DROP_FRAME %s update attrib fail\n", __FUNCTION__);
++#endif
++		rtw_free_xmitframe(pxmitpriv, pxmitframe);
++		return -1;
++	}
++	pxmitframe->pkt = pkt;
++
++	rtw_led_tx_control(padapter, pxmitframe->attrib.dst);
++
++	do_queue_select(padapter, &pxmitframe->attrib);
++
++#ifdef CONFIG_AP_MODE
++	_enter_critical_bh(&pxmitpriv->lock, &irqL0);
++	if (xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) {
++		_exit_critical_bh(&pxmitpriv->lock, &irqL0);
++		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue);
++		return 1;
++	}
++	_exit_critical_bh(&pxmitpriv->lock, &irqL0);
++#endif
++
++	if (xmit_enqueue(padapter, pxmitframe) == _TRUE)
++		return 1;
++
++	/* pre_xmitframe */
++	if (rtw_hal_xmit(padapter, pxmitframe) == _FALSE)
++		return 1;
++
++	return 0;
++}
++
++/*
++ * The main transmit(tx) entry
++ *
++ * Return
++ *	1	enqueue
++ *	0	success, hardware will handle this xmit frame(packet)
++ *	<0	fail
++ */
++s32 rtw_xmit(_adapter *padapter, _pkt **ppkt, u16 os_qid)
++{
++	static systime start = 0;
++	static u32 drop_cnt = 0;
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	struct xmit_frame *pxmitframe = NULL;
++	s32 res;
++
++	DBG_COUNTER(padapter->tx_logs.core_tx);
++
++	if (IS_CH_WAITING(adapter_to_rfctl(padapter)))
++		return -1;
++
++	if (rtw_linked_check(padapter) == _FALSE)
++		return -1;
++
++	if (start == 0)
++		start = rtw_get_current_time();
++
++	pxmitframe = rtw_alloc_xmitframe(pxmitpriv, os_qid);
++
++	if (rtw_get_passing_time_ms(start) > 2000) {
++		if (drop_cnt)
++			RTW_INFO("DBG_TX_DROP_FRAME %s no more pxmitframe, drop_cnt:%u\n", __FUNCTION__, drop_cnt);
++		start = rtw_get_current_time();
++		drop_cnt = 0;
++	}
++
++	if (pxmitframe == NULL) {
++		drop_cnt++;
++		/*RTW_INFO("%s-"ADPT_FMT" no more xmitframe\n", __func__, ADPT_ARG(padapter));*/
++		DBG_COUNTER(padapter->tx_logs.core_tx_err_pxmitframe);
++		return -1;
++	}
++
++#ifdef CONFIG_BR_EXT
++	if (!adapter_use_wds(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) {
++		void *br_port = NULL;
++
++		#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++		br_port = padapter->pnetdev->br_port;
++		#else
++		rcu_read_lock();
++		br_port = rcu_dereference(padapter->pnetdev->rx_handler_data);
++		rcu_read_unlock();
++		#endif
++
++		if (br_port) {
++			res = rtw_br_client_tx(padapter, ppkt);
++			if (res == -1) {
++				rtw_free_xmitframe(pxmitpriv, pxmitframe);
++				DBG_COUNTER(padapter->tx_logs.core_tx_err_brtx);
++				return -1;
++			}
++		}
++	}
++#endif /* CONFIG_BR_EXT */
++
++#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
++	if (MLME_STATE(padapter) & (WIFI_AP_STATE | WIFI_MESH_STATE)) {
++		_list b2u_list;
++
++		#ifdef CONFIG_RTW_MESH
++		if (MLME_IS_MESH(padapter))
++			res = rtw_mesh_addr_resolve(padapter, os_qid, pxmitframe, *ppkt, &b2u_list);
++		else
++		#endif
++			res = rtw_ap_addr_resolve(padapter, os_qid, pxmitframe, *ppkt, &b2u_list);
++		if (res == RTW_RA_RESOLVING)
++			return 1;
++		if (res == _FAIL)
++			return -1;
++
++		#if CONFIG_RTW_DATA_BMC_TO_UC
++		if (!rtw_is_list_empty(&b2u_list)) {
++			_list *list = get_next(&b2u_list);
++			struct xmit_frame *b2uframe;
++
++			while ((rtw_end_of_queue_search(&b2u_list, list)) == _FALSE) {
++				b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list);
++				list = get_next(list);
++				rtw_list_delete(&b2uframe->list);
++
++				b2uframe->pkt = rtw_os_pkt_copy(*ppkt);
++				if (!b2uframe->pkt) {
++					if (res == RTW_BMC_NO_NEED)
++						res = _SUCCESS;
++					rtw_free_xmitframe(pxmitpriv, b2uframe);
++					continue;
++				}
++
++				rtw_xmit_posthandle(padapter, b2uframe, b2uframe->pkt);
++			}
++		}
++		#endif
++
++		if (res == RTW_BMC_NO_NEED) {
++			rtw_free_xmitframe(&padapter->xmitpriv, pxmitframe);
++			return 0;
++		}
++	}
++#endif /* defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH) */
++
++	pxmitframe->pkt = NULL; /* let rtw_xmit_posthandle not to free pkt inside */
++	res = rtw_xmit_posthandle(padapter, pxmitframe, *ppkt);
++
++	return res;
++}
++
++#ifdef CONFIG_TDLS
++sint xmitframe_enqueue_for_tdls_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++	sint ret = _FALSE;
++
++	_irqL irqL;
++	struct sta_info *ptdls_sta = NULL;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct pkt_attrib *pattrib = &pxmitframe->attrib;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	int i;
++
++	ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst);
++	if (ptdls_sta == NULL)
++		return ret;
++	else if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {
++
++		if (pattrib->triggered == 1) {
++			ret = _TRUE;
++			return ret;
++		}
++
++		_enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);
++
++		if (ptdls_sta->state & WIFI_SLEEP_STATE) {
++			rtw_list_delete(&pxmitframe->list);
++
++			/* _enter_critical_bh(&psta->sleep_q.lock, &irqL);	 */
++
++			rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptdls_sta->sleep_q));
++
++			ptdls_sta->sleepq_len++;
++			ptdls_sta->sleepq_ac_len++;
++
++			/* indicate 4-AC queue bit in TDLS peer traffic indication */
++			switch (pattrib->priority) {
++			case 1:
++			case 2:
++				ptdls_sta->uapsd_bk |= BIT(1);
++				break;
++			case 4:
++			case 5:
++				ptdls_sta->uapsd_vi |= BIT(1);
++				break;
++			case 6:
++			case 7:
++				ptdls_sta->uapsd_vo |= BIT(1);
++				break;
++			case 0:
++			case 3:
++			default:
++				ptdls_sta->uapsd_be |= BIT(1);
++				break;
++			}
++
++			/* Transmit TDLS PTI via AP */
++			if (ptdls_sta->sleepq_len == 1)
++				rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ISSUE_PTI);
++
++			ret = _TRUE;
++		}
++
++		_exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);
++	}
++
++	return ret;
++
++}
++#endif /* CONFIG_TDLS */
++
++#define RTW_HIQ_FILTER_ALLOW_ALL 0
++#define RTW_HIQ_FILTER_ALLOW_SPECIAL 1
++#define RTW_HIQ_FILTER_DENY_ALL 2
++
++inline bool xmitframe_hiq_filter(struct xmit_frame *xmitframe)
++{
++	bool allow = _FALSE;
++	_adapter *adapter = xmitframe->padapter;
++	struct registry_priv *registry = &adapter->registrypriv;
++
++	if (adapter->registrypriv.wifi_spec == 1)
++		allow = _TRUE;
++	else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_SPECIAL) {
++
++		struct pkt_attrib *attrib = &xmitframe->attrib;
++
++		if (attrib->ether_type == 0x0806
++		    || attrib->ether_type == 0x888e
++#ifdef CONFIG_WAPI_SUPPORT
++		    || attrib->ether_type == 0x88B4
++#endif
++		    || attrib->dhcp_pkt
++		   ) {
++			if (0)
++				RTW_INFO(FUNC_ADPT_FMT" ether_type:0x%04x%s\n", FUNC_ADPT_ARG(xmitframe->padapter)
++					, attrib->ether_type, attrib->dhcp_pkt ? " DHCP" : "");
++			allow = _TRUE;
++		}
++	} else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_ALL)
++		allow = _TRUE;
++	else if (registry->hiq_filter == RTW_HIQ_FILTER_DENY_ALL)
++		allow = _FALSE;
++	else
++		rtw_warn_on(1);
++
++	return allow;
++}
++
++#if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS)
++
++sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++	_irqL irqL;
++	sint ret = _FALSE;
++	struct sta_info *psta = NULL;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct pkt_attrib *pattrib = &pxmitframe->attrib;
++	sint bmcst = IS_MCAST(pattrib->ra);
++	bool update_tim = _FALSE;
++#ifdef CONFIG_TDLS
++
++	if (padapter->tdlsinfo.link_established == _TRUE)
++		ret = xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pxmitframe);
++#endif /* CONFIG_TDLS */
++
++	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) {
++		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_fwstate);
++		return ret;
++	}
++	/*
++		if(pattrib->psta)
++		{
++			psta = pattrib->psta;
++		}
++		else
++		{
++			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
++			psta=rtw_get_stainfo(pstapriv, pattrib->ra);
++		}
++	*/
++	psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
++	if (pattrib->psta != psta) {
++		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_sta);
++		RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
++		return _FALSE;
++	}
++
++	if (psta == NULL) {
++		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_nosta);
++		RTW_INFO("%s, psta==NUL\n", __func__);
++		return _FALSE;
++	}
++
++	if (!(psta->state & WIFI_ASOC_STATE)) {
++		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_link);
++		RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
++		return _FALSE;
++	}
++
++	if (pattrib->triggered == 1) {
++		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_trigger);
++		/* RTW_INFO("directly xmit pspoll_triggered packet\n"); */
++
++		/* pattrib->triggered=0; */
++		if (bmcst && xmitframe_hiq_filter(pxmitframe) == _TRUE)
++			pattrib->qsel = QSLT_HIGH;/* HIQ */
++
++		return ret;
++	}
++
++
++	if (bmcst) {
++		_enter_critical_bh(&psta->sleep_q.lock, &irqL);
++
++		if (rtw_tim_map_anyone_be_set(padapter, pstapriv->sta_dz_bitmap)) { /* if anyone sta is in ps mode */
++			/* pattrib->qsel = QSLT_HIGH; */ /* HIQ */
++
++			rtw_list_delete(&pxmitframe->list);
++
++			/*_enter_critical_bh(&psta->sleep_q.lock, &irqL);*/
++
++			rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q));
++
++			psta->sleepq_len++;
++
++			if (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)))
++				update_tim = _TRUE;
++
++			rtw_tim_map_set(padapter, pstapriv->tim_bitmap, 0);
++			rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, 0);
++
++			/* RTW_INFO("enqueue, sq_len=%d\n", psta->sleepq_len); */
++			/* RTW_INFO_DUMP("enqueue, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
++			if (update_tim == _TRUE) {
++				if (is_broadcast_mac_addr(pattrib->ra))
++					_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, "buffer BC");
++				else
++					_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, "buffer MC");
++			} else
++				chk_bmc_sleepq_cmd(padapter);
++
++			/*_exit_critical_bh(&psta->sleep_q.lock, &irqL);*/
++
++			ret = _TRUE;
++
++			DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_mcast);
++		}
++
++		_exit_critical_bh(&psta->sleep_q.lock, &irqL);
++
++		return ret;
++
++	}
++
++
++	_enter_critical_bh(&psta->sleep_q.lock, &irqL);
++
++	if (psta->state & WIFI_SLEEP_STATE) {
++		u8 wmmps_ac = 0;
++
++		if (rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid)) {
++			rtw_list_delete(&pxmitframe->list);
++
++			/* _enter_critical_bh(&psta->sleep_q.lock, &irqL);	 */
++
++			rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q));
++
++			psta->sleepq_len++;
++
++			switch (pattrib->priority) {
++			case 1:
++			case 2:
++				wmmps_ac = psta->uapsd_bk & BIT(0);
++				break;
++			case 4:
++			case 5:
++				wmmps_ac = psta->uapsd_vi & BIT(0);
++				break;
++			case 6:
++			case 7:
++				wmmps_ac = psta->uapsd_vo & BIT(0);
++				break;
++			case 0:
++			case 3:
++			default:
++				wmmps_ac = psta->uapsd_be & BIT(0);
++				break;
++			}
++
++			if (wmmps_ac)
++				psta->sleepq_ac_len++;
++
++			if (((psta->has_legacy_ac) && (!wmmps_ac)) || ((!psta->has_legacy_ac) && (wmmps_ac))) {
++				if (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)))
++					update_tim = _TRUE;
++
++				rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
++
++				/* RTW_INFO("enqueue, sq_len=%d\n", psta->sleepq_len); */
++				/* RTW_INFO_DUMP("enqueue, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
++
++				if (update_tim == _TRUE) {
++					/* RTW_INFO("sleepq_len==1, update BCNTIM\n"); */
++					/* upate BCN for TIM IE */
++					_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, "buffer UC");
++				}
++			}
++
++			/* _exit_critical_bh(&psta->sleep_q.lock, &irqL);			 */
++
++			/* if(psta->sleepq_len > (NR_XMITFRAME>>3)) */
++			/* { */
++			/*	wakeup_sta_to_xmit(padapter, psta); */
++			/* }	 */
++
++			ret = _TRUE;
++
++			DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_ucast);
++		}
++
++	}
++
++	_exit_critical_bh(&psta->sleep_q.lock, &irqL);
++
++	return ret;
++
++}
++
++static void dequeue_xmitframes_to_sleeping_queue(_adapter *padapter, struct sta_info *psta, _queue *pframequeue)
++{
++	sint ret;
++	_list	*plist, *phead;
++	u8	ac_index;
++	struct tx_servq	*ptxservq;
++	struct pkt_attrib	*pattrib;
++	struct xmit_frame	*pxmitframe;
++	struct hw_xmit *phwxmits =  padapter->xmitpriv.hwxmits;
++
++	phead = get_list_head(pframequeue);
++	plist = get_next(phead);
++
++	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
++		pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
++
++		plist = get_next(plist);
++
++		pattrib = &pxmitframe->attrib;
++
++		pattrib->triggered = 0;
++
++		ret = xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe);
++
++		if (_TRUE == ret) {
++			ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index));
++
++			ptxservq->qcnt--;
++			phwxmits[ac_index].accnt--;
++		} else {
++			/* RTW_INFO("xmitframe_enqueue_for_sleeping_sta return _FALSE\n"); */
++		}
++
++	}
++
++}
++
++void stop_sta_xmit(_adapter *padapter, struct sta_info *psta)
++{
++	_irqL irqL0;
++	struct sta_info *psta_bmc;
++	struct sta_xmit_priv *pstaxmitpriv;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++	pstaxmitpriv = &psta->sta_xmitpriv;
++
++	/* for BC/MC Frames */
++	psta_bmc = rtw_get_bcmc_stainfo(padapter);
++	if (!psta_bmc)
++		rtw_warn_on(1);
++
++	_enter_critical_bh(&pxmitpriv->lock, &irqL0);
++
++	psta->state |= WIFI_SLEEP_STATE;
++
++#ifdef CONFIG_TDLS
++	if (!(psta->tdls_sta_state & TDLS_LINKED_STATE))
++#endif /* CONFIG_TDLS */
++		rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid);
++
++	dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vo_q.sta_pending);
++	rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));
++	dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vi_q.sta_pending);
++	rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));
++	dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->be_q.sta_pending);
++	rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));
++	dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->bk_q.sta_pending);
++	rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));
++
++	if (psta_bmc != NULL
++		#ifdef CONFIG_TDLS
++		&& !(psta->tdls_sta_state & TDLS_LINKED_STATE)
++		#endif
++	)
++	{
++		/* for BC/MC Frames */
++		pstaxmitpriv = &psta_bmc->sta_xmitpriv;
++		dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->vo_q.sta_pending);
++		rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));
++		dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->vi_q.sta_pending);
++		rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));
++		dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->be_q.sta_pending);
++		rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));
++		dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->bk_q.sta_pending);
++		rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));
++	}
++	_exit_critical_bh(&pxmitpriv->lock, &irqL0);
++
++
++}
++
++void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta)
++{
++	_irqL irqL;
++	u8 update_mask = 0, wmmps_ac = 0;
++	struct sta_info *psta_bmc;
++	_list	*xmitframe_plist, *xmitframe_phead;
++	struct xmit_frame *pxmitframe = NULL;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++	psta_bmc = rtw_get_bcmc_stainfo(padapter);
++
++
++	/* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */
++	_enter_critical_bh(&pxmitpriv->lock, &irqL);
++
++	xmitframe_phead = get_list_head(&psta->sleep_q);
++	xmitframe_plist = get_next(xmitframe_phead);
++
++	while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
++		pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
++
++		xmitframe_plist = get_next(xmitframe_plist);
++
++		rtw_list_delete(&pxmitframe->list);
++
++		switch (pxmitframe->attrib.priority) {
++		case 1:
++		case 2:
++			wmmps_ac = psta->uapsd_bk & BIT(1);
++			break;
++		case 4:
++		case 5:
++			wmmps_ac = psta->uapsd_vi & BIT(1);
++			break;
++		case 6:
++		case 7:
++			wmmps_ac = psta->uapsd_vo & BIT(1);
++			break;
++		case 0:
++		case 3:
++		default:
++			wmmps_ac = psta->uapsd_be & BIT(1);
++			break;
++		}
++
++		psta->sleepq_len--;
++		if (psta->sleepq_len > 0)
++			pxmitframe->attrib.mdata = 1;
++		else
++			pxmitframe->attrib.mdata = 0;
++
++		if (wmmps_ac) {
++			psta->sleepq_ac_len--;
++			if (psta->sleepq_ac_len > 0) {
++				pxmitframe->attrib.mdata = 1;
++				pxmitframe->attrib.eosp = 0;
++			} else {
++				pxmitframe->attrib.mdata = 0;
++				pxmitframe->attrib.eosp = 1;
++			}
++		}
++
++		pxmitframe->attrib.triggered = 1;
++
++		/*
++				_exit_critical_bh(&psta->sleep_q.lock, &irqL);
++				if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
++				{
++					rtw_os_xmit_complete(padapter, pxmitframe);
++				}
++				_enter_critical_bh(&psta->sleep_q.lock, &irqL);
++		*/
++		rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
++
++
++	}
++
++	if (psta->sleepq_len == 0) {
++#ifdef CONFIG_TDLS
++		if (psta->tdls_sta_state & TDLS_LINKED_STATE) {
++			if (psta->state & WIFI_SLEEP_STATE)
++				psta->state ^= WIFI_SLEEP_STATE;
++
++			_exit_critical_bh(&pxmitpriv->lock, &irqL);
++			return;
++		}
++#endif /* CONFIG_TDLS */
++
++		if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) {
++			/* RTW_INFO("wakeup to xmit, qlen==0\n"); */
++			/* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
++			/* upate BCN for TIM IE */
++			/* update_BCNTIM(padapter); */
++			update_mask = BIT(0);
++		}
++
++		rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
++
++		if (psta->state & WIFI_SLEEP_STATE)
++			psta->state ^= WIFI_SLEEP_STATE;
++
++		if (psta->state & WIFI_STA_ALIVE_CHK_STATE) {
++			RTW_INFO("%s alive check\n", __func__);
++			psta->expire_to = pstapriv->expire_to;
++			psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
++		}
++
++		rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid);
++	}
++
++	/* for BC/MC Frames */
++	if (!psta_bmc)
++		goto _exit;
++
++	if (!(rtw_tim_map_anyone_be_set_exclude_aid0(padapter, pstapriv->sta_dz_bitmap))) { /* no any sta in ps mode */
++		xmitframe_phead = get_list_head(&psta_bmc->sleep_q);
++		xmitframe_plist = get_next(xmitframe_phead);
++
++		while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
++			pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
++
++			xmitframe_plist = get_next(xmitframe_plist);
++
++			rtw_list_delete(&pxmitframe->list);
++
++			psta_bmc->sleepq_len--;
++			if (psta_bmc->sleepq_len > 0)
++				pxmitframe->attrib.mdata = 1;
++			else
++				pxmitframe->attrib.mdata = 0;
++
++
++			pxmitframe->attrib.triggered = 1;
++			/*
++						_exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
++						if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
++						{
++							rtw_os_xmit_complete(padapter, pxmitframe);
++						}
++						_enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
++
++			*/
++			rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
++
++		}
++
++		if (psta_bmc->sleepq_len == 0) {
++			if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) {
++				/* RTW_INFO("wakeup to xmit, qlen==0\n"); */
++				/* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
++				/* upate BCN for TIM IE */
++				/* update_BCNTIM(padapter); */
++				update_mask |= BIT(1);
++			}
++			rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0);
++			rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0);
++		}
++
++	}
++
++_exit:
++
++	/* _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);	 */
++	_exit_critical_bh(&pxmitpriv->lock, &irqL);
++
++	if (update_mask) {
++		/* update_BCNTIM(padapter); */
++		if ((update_mask & (BIT(0) | BIT(1))) == (BIT(0) | BIT(1)))
++			_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, "clear UC&BMC");
++		else if ((update_mask & BIT(1)) == BIT(1))
++			_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, "clear BMC");
++		else
++			_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, "clear UC");
++	}
++
++}
++
++void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta)
++{
++	_irqL irqL;
++	u8 wmmps_ac = 0;
++	_list	*xmitframe_plist, *xmitframe_phead;
++	struct xmit_frame *pxmitframe = NULL;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++
++	/* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */
++	_enter_critical_bh(&pxmitpriv->lock, &irqL);
++
++	xmitframe_phead = get_list_head(&psta->sleep_q);
++	xmitframe_plist = get_next(xmitframe_phead);
++
++	while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
++		pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
++
++		xmitframe_plist = get_next(xmitframe_plist);
++
++		switch (pxmitframe->attrib.priority) {
++		case 1:
++		case 2:
++			wmmps_ac = psta->uapsd_bk & BIT(1);
++			break;
++		case 4:
++		case 5:
++			wmmps_ac = psta->uapsd_vi & BIT(1);
++			break;
++		case 6:
++		case 7:
++			wmmps_ac = psta->uapsd_vo & BIT(1);
++			break;
++		case 0:
++		case 3:
++		default:
++			wmmps_ac = psta->uapsd_be & BIT(1);
++			break;
++		}
++
++		if (!wmmps_ac)
++			continue;
++
++		rtw_list_delete(&pxmitframe->list);
++
++		psta->sleepq_len--;
++		psta->sleepq_ac_len--;
++
++		if (psta->sleepq_ac_len > 0) {
++			pxmitframe->attrib.mdata = 1;
++			pxmitframe->attrib.eosp = 0;
++		} else {
++			pxmitframe->attrib.mdata = 0;
++			pxmitframe->attrib.eosp = 1;
++		}
++
++		pxmitframe->attrib.triggered = 1;
++		rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
++
++		if ((psta->sleepq_ac_len == 0) && (!psta->has_legacy_ac) && (wmmps_ac)) {
++#ifdef CONFIG_TDLS
++			if (psta->tdls_sta_state & TDLS_LINKED_STATE) {
++				/* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */
++				goto exit;
++			}
++#endif /* CONFIG_TDLS */
++			rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
++
++			/* RTW_INFO("wakeup to xmit, qlen==0\n"); */
++			/* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
++			/* upate BCN for TIM IE */
++			/* update_BCNTIM(padapter); */
++			update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0);
++			/* update_mask = BIT(0); */
++		}
++
++	}
++
++#ifdef CONFIG_TDLS
++exit:
++#endif
++	/* _exit_critical_bh(&psta->sleep_q.lock, &irqL);	 */
++	_exit_critical_bh(&pxmitpriv->lock, &irqL);
++
++	return;
++}
++
++#endif /* defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) */
++
++#ifdef CONFIG_XMIT_THREAD_MODE
++void enqueue_pending_xmitbuf(
++	struct xmit_priv *pxmitpriv,
++	struct xmit_buf *pxmitbuf)
++{
++	_irqL irql;
++	_queue *pqueue;
++	_adapter *pri_adapter = pxmitpriv->adapter;
++
++	pqueue = &pxmitpriv->pending_xmitbuf_queue;
++
++	_enter_critical_bh(&pqueue->lock, &irql);
++	rtw_list_delete(&pxmitbuf->list);
++	rtw_list_insert_tail(&pxmitbuf->list, get_list_head(pqueue));
++	_exit_critical_bh(&pqueue->lock, &irql);
++
++#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_CONCURRENT_MODE)
++	pri_adapter = GET_PRIMARY_ADAPTER(pri_adapter);
++#endif /*SDIO_HCI + CONCURRENT*/
++	_rtw_up_sema(&(pri_adapter->xmitpriv.xmit_sema));
++}
++
++void enqueue_pending_xmitbuf_to_head(
++	struct xmit_priv *pxmitpriv,
++	struct xmit_buf *pxmitbuf)
++{
++	_irqL irql;
++	_queue *pqueue = &pxmitpriv->pending_xmitbuf_queue;
++
++	_enter_critical_bh(&pqueue->lock, &irql);
++	rtw_list_delete(&pxmitbuf->list);
++	rtw_list_insert_head(&pxmitbuf->list, get_list_head(pqueue));
++	_exit_critical_bh(&pqueue->lock, &irql);
++}
++
++struct xmit_buf *dequeue_pending_xmitbuf(
++	struct xmit_priv *pxmitpriv)
++{
++	_irqL irql;
++	struct xmit_buf *pxmitbuf;
++	_queue *pqueue;
++
++
++	pxmitbuf = NULL;
++	pqueue = &pxmitpriv->pending_xmitbuf_queue;
++
++	_enter_critical_bh(&pqueue->lock, &irql);
++
++	if (_rtw_queue_empty(pqueue) == _FALSE) {
++		_list *plist, *phead;
++
++		phead = get_list_head(pqueue);
++		plist = get_next(phead);
++		pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
++		rtw_list_delete(&pxmitbuf->list);
++	}
++
++	_exit_critical_bh(&pqueue->lock, &irql);
++
++	return pxmitbuf;
++}
++
++static struct xmit_buf *dequeue_pending_xmitbuf_ext(
++	struct xmit_priv *pxmitpriv)
++{
++	_irqL irql;
++	struct xmit_buf *pxmitbuf;
++	_queue *pqueue;
++
++	pxmitbuf = NULL;
++	pqueue = &pxmitpriv->pending_xmitbuf_queue;
++
++	_enter_critical_bh(&pqueue->lock, &irql);
++
++	if (_rtw_queue_empty(pqueue) == _FALSE) {
++		_list *plist, *phead;
++
++		phead = get_list_head(pqueue);
++		plist = phead;
++		do {
++			plist = get_next(plist);
++			if (plist == phead)
++				break;
++
++			pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
++
++			if (pxmitbuf->buf_tag == XMITBUF_MGNT) {
++				rtw_list_delete(&pxmitbuf->list);
++				break;
++			}
++			pxmitbuf = NULL;
++		} while (1);
++	}
++
++	_exit_critical_bh(&pqueue->lock, &irql);
++
++	return pxmitbuf;
++}
++
++struct xmit_buf *select_and_dequeue_pending_xmitbuf(_adapter *padapter)
++{
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	struct xmit_buf *pxmitbuf = NULL;
++
++	if (_TRUE == rtw_is_xmit_blocked(padapter))
++		return pxmitbuf;
++
++	pxmitbuf = dequeue_pending_xmitbuf_ext(pxmitpriv);
++	if (pxmitbuf == NULL && rtw_xmit_ac_blocked(padapter) != _TRUE)
++		pxmitbuf = dequeue_pending_xmitbuf(pxmitpriv);
++
++	return pxmitbuf;
++}
++
++sint check_pending_xmitbuf(
++	struct xmit_priv *pxmitpriv)
++{
++	_irqL irql;
++	_queue *pqueue;
++	sint	ret = _FALSE;
++
++	pqueue = &pxmitpriv->pending_xmitbuf_queue;
++
++	_enter_critical_bh(&pqueue->lock, &irql);
++
++	if (_rtw_queue_empty(pqueue) == _FALSE)
++		ret = _TRUE;
++
++	_exit_critical_bh(&pqueue->lock, &irql);
++
++	return ret;
++}
++
++thread_return rtw_xmit_thread(thread_context context)
++{
++	s32 err;
++	PADAPTER padapter;
++#ifdef RTW_XMIT_THREAD_HIGH_PRIORITY
++#ifdef PLATFORM_LINUX
++	struct sched_param param = { .sched_priority = 1 };
++
++	sched_setscheduler(current, SCHED_FIFO, &param);
++#endif /* PLATFORM_LINUX */
++#endif /* RTW_XMIT_THREAD_HIGH_PRIORITY */
++
++	err = _SUCCESS;
++	padapter = (PADAPTER)context;
++
++	thread_enter("RTW_XMIT_THREAD");
++
++	do {
++		err = rtw_hal_xmit_thread_handler(padapter);
++		flush_signals_thread();
++	} while (_SUCCESS == err);
++
++	RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(padapter));
++
++	rtw_thread_wait_stop();
++
++	return 0;
++}
++#endif
++
++#ifdef DBG_XMIT_BLOCK
++void dump_xmit_block(void *sel, _adapter *padapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++	RTW_PRINT_SEL(sel, "[XMIT-BLOCK] xmit_block :0x%02x\n", dvobj->xmit_block);
++	if (dvobj->xmit_block & XMIT_BLOCK_REDLMEM)
++		RTW_PRINT_SEL(sel, "Reason:%s\n", "XMIT_BLOCK_REDLMEM");
++	if (dvobj->xmit_block & XMIT_BLOCK_SUSPEND)
++		RTW_PRINT_SEL(sel, "Reason:%s\n", "XMIT_BLOCK_SUSPEND");
++	if (dvobj->xmit_block == XMIT_BLOCK_NONE)
++		RTW_PRINT_SEL(sel, "Reason:%s\n", "XMIT_BLOCK_NONE");
++}
++void dump_xmit_block_info(void *sel, const char *fun_name, _adapter *padapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++	RTW_INFO("\n"ADPT_FMT" call %s\n", ADPT_ARG(padapter), fun_name);
++	dump_xmit_block(sel, padapter);
++}
++#define DBG_XMIT_BLOCK_DUMP(adapter)	dump_xmit_block_info(RTW_DBGDUMP, __func__, adapter)
++#endif
++
++void rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason)
++{
++	_irqL irqL;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++	_enter_critical_bh(&dvobj->xmit_block_lock, &irqL);
++	dvobj->xmit_block |= reason;
++	_exit_critical_bh(&dvobj->xmit_block_lock, &irqL);
++
++	#ifdef DBG_XMIT_BLOCK
++	DBG_XMIT_BLOCK_DUMP(padapter);
++	#endif
++}
++
++void rtw_clr_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason)
++{
++	_irqL irqL;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++	_enter_critical_bh(&dvobj->xmit_block_lock, &irqL);
++	dvobj->xmit_block &= ~reason;
++	_exit_critical_bh(&dvobj->xmit_block_lock, &irqL);
++
++	#ifdef DBG_XMIT_BLOCK
++	DBG_XMIT_BLOCK_DUMP(padapter);
++	#endif
++}
++bool rtw_is_xmit_blocked(_adapter *padapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++	#ifdef DBG_XMIT_BLOCK
++	DBG_XMIT_BLOCK_DUMP(padapter);
++	#endif
++	return ((dvobj->xmit_block) ? _TRUE : _FALSE);
++}
++
++bool rtw_xmit_ac_blocked(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	_adapter *iface;
++	struct mlme_ext_priv *mlmeext;
++	bool blocked = _FALSE;
++	int i;
++#ifdef DBG_CONFIG_ERROR_DETECT
++#ifdef DBG_CONFIG_ERROR_RESET
++#ifdef CONFIG_USB_HCI
++	if (rtw_hal_sreset_inprogress(adapter) == _TRUE) {
++		blocked = _TRUE;
++		goto exit;
++	}
++#endif/* #ifdef CONFIG_USB_HCI */
++#endif/* #ifdef DBG_CONFIG_ERROR_RESET */
++#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */
++
++	if (rfctl->offch_state != OFFCHS_NONE
++		#if CONFIG_DFS
++		|| IS_RADAR_DETECTED(rfctl) || rfctl->csa_ch
++		#endif
++	) {
++		blocked = _TRUE;
++		goto exit;
++	}
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		mlmeext = &iface->mlmeextpriv;
++
++		/* check scan state */
++		if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE
++			&& mlmeext_scan_state(mlmeext) != SCAN_BACK_OP
++		) {
++			blocked = _TRUE;
++			goto exit;
++		}
++
++		if (mlmeext_scan_state(mlmeext) == SCAN_BACK_OP
++			&& !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME)
++		) {
++			blocked = _TRUE;
++			goto exit;
++		}
++	}
++
++#ifdef CONFIG_MCC_MODE
++	if (MCC_EN(adapter)) {
++		if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
++			if (MCC_STOP(adapter)) {
++				blocked = _TRUE;
++				goto exit;
++			}
++		}
++	}
++#endif /*  CONFIG_MCC_MODE */
++
++exit:
++	return blocked;
++}
++
++#ifdef CONFIG_TX_AMSDU
++void rtw_amsdu_vo_timeout_handler(void *FunctionContext)
++{
++	_adapter *adapter = (_adapter *)FunctionContext;
++
++	adapter->xmitpriv.amsdu_vo_timeout = RTW_AMSDU_TIMER_TIMEOUT;
++
++	tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);
++}
++
++void rtw_amsdu_vi_timeout_handler(void *FunctionContext)
++{
++	_adapter *adapter = (_adapter *)FunctionContext;
++
++	adapter->xmitpriv.amsdu_vi_timeout = RTW_AMSDU_TIMER_TIMEOUT;
++
++	tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);
++}
++
++void rtw_amsdu_be_timeout_handler(void *FunctionContext)
++{
++	_adapter *adapter = (_adapter *)FunctionContext;
++
++	adapter->xmitpriv.amsdu_be_timeout = RTW_AMSDU_TIMER_TIMEOUT;
++
++	if (printk_ratelimit())
++		RTW_INFO("%s Timeout!\n",__FUNCTION__);
++
++	tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);
++}
++
++void rtw_amsdu_bk_timeout_handler(void *FunctionContext)
++{
++	_adapter *adapter = (_adapter *)FunctionContext;
++
++	adapter->xmitpriv.amsdu_bk_timeout = RTW_AMSDU_TIMER_TIMEOUT;
++
++	tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);
++}
++
++u8 rtw_amsdu_get_timer_status(_adapter *padapter, u8 priority)
++{
++	struct xmit_priv        *pxmitpriv = &padapter->xmitpriv;
++
++	u8 status =  RTW_AMSDU_TIMER_UNSET;
++
++	switch(priority)
++	{
++		case 1:
++		case 2:
++			status = pxmitpriv->amsdu_bk_timeout;
++			break;
++		case 4:
++		case 5:
++			status = pxmitpriv->amsdu_vi_timeout;
++			break;
++		case 6:
++		case 7:
++			status = pxmitpriv->amsdu_vo_timeout;
++			break;
++		case 0:
++		case 3:
++		default:
++			status = pxmitpriv->amsdu_be_timeout;
++			break;
++	}
++	return status;
++}
++
++void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status)
++{
++	struct xmit_priv        *pxmitpriv = &padapter->xmitpriv;
++
++	switch(priority)
++	{
++		case 1:
++		case 2:
++			pxmitpriv->amsdu_bk_timeout = status;
++			break;
++		case 4:
++		case 5:
++			pxmitpriv->amsdu_vi_timeout = status;
++			break;
++		case 6:
++		case 7:
++			pxmitpriv->amsdu_vo_timeout = status;
++			break;
++		case 0:
++		case 3:
++		default:
++			pxmitpriv->amsdu_be_timeout = status;
++			break;
++	}
++}
++
++void rtw_amsdu_set_timer(_adapter *padapter, u8 priority)
++{
++	struct xmit_priv        *pxmitpriv = &padapter->xmitpriv;
++
++	_timer* amsdu_timer = NULL;
++
++	switch(priority)
++	{
++		case 1:
++		case 2:
++			amsdu_timer = &pxmitpriv->amsdu_bk_timer;
++			break;
++		case 4:
++		case 5:
++			amsdu_timer = &pxmitpriv->amsdu_vi_timer;
++			break;
++		case 6:
++		case 7:
++			amsdu_timer = &pxmitpriv->amsdu_vo_timer;
++			break;
++		case 0:
++		case 3:
++		default:
++			amsdu_timer = &pxmitpriv->amsdu_be_timer;
++			break;
++	}
++	_set_timer(amsdu_timer, 1);
++}
++
++void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority)
++{
++	struct xmit_priv        *pxmitpriv = &padapter->xmitpriv;
++	_timer* amsdu_timer = NULL;
++
++	switch(priority)
++	{
++		case 1:
++		case 2:
++			amsdu_timer = &pxmitpriv->amsdu_bk_timer;
++			break;
++		case 4:
++		case 5:
++			amsdu_timer = &pxmitpriv->amsdu_vi_timer;
++			break;
++		case 6:
++		case 7:
++			amsdu_timer = &pxmitpriv->amsdu_vo_timer;
++			break;
++		case 0:
++		case 3:
++		default:
++			amsdu_timer = &pxmitpriv->amsdu_be_timer;
++			break;
++	}
++	_cancel_timer_ex(amsdu_timer);
++}
++#endif /* CONFIG_TX_AMSDU */
++
++#ifdef DBG_TXBD_DESC_DUMP
++static struct rtw_tx_desc_backup tx_backup[HW_QUEUE_ENTRY][TX_BAK_FRMAE_CNT];
++static u8 backup_idx[HW_QUEUE_ENTRY];
++
++void rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 desc_size, u8 hwq)
++{
++	u32 tmp32;
++	u8 *pxmit_buf;
++
++	if (rtw_get_hw_init_completed(padapter) == _FALSE)
++		return;
++
++	pxmit_buf = pxmitframe->pxmitbuf->pbuf;
++
++	_rtw_memcpy(tx_backup[hwq][backup_idx[hwq]].tx_bak_desc, pxmit_buf, desc_size);
++	_rtw_memcpy(tx_backup[hwq][backup_idx[hwq]].tx_bak_data_hdr, pxmit_buf+desc_size, TX_BAK_DATA_LEN);
++
++	tmp32 = rtw_read32(padapter, get_txbd_rw_reg(hwq));
++
++	tx_backup[hwq][backup_idx[hwq]].tx_bak_rp = (tmp32>>16)&0xfff;
++	tx_backup[hwq][backup_idx[hwq]].tx_bak_wp = tmp32&0xfff;
++
++	tx_backup[hwq][backup_idx[hwq]].tx_desc_size = desc_size;
++
++	backup_idx[hwq] = (backup_idx[hwq] + 1) % TX_BAK_FRMAE_CNT;
++}
++
++void rtw_tx_desc_backup_reset(void)
++{
++	int i, j;
++
++	for (i = 0; i < HW_QUEUE_ENTRY; i++) {
++		for (j = 0; j < TX_BAK_FRMAE_CNT; j++)
++			_rtw_memset(&tx_backup[i][j], 0, sizeof(struct rtw_tx_desc_backup));
++
++		backup_idx[i] = 0;
++	}
++}
++
++u8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup **pbak)
++{
++	*pbak = &tx_backup[hwq][0];
++
++	return backup_idx[hwq];
++}
++#endif
++
++#ifdef CONFIG_PCI_TX_POLLING
++void rtw_tx_poll_init(_adapter *padapter)
++{
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	_timer* timer = &pxmitpriv->tx_poll_timer;
++
++	if (!is_primary_adapter(padapter))
++		return;
++
++	if (timer->function != NULL) {
++		RTW_INFO("tx polling timer has been init.\n");
++		return;
++	}
++
++	rtw_init_timer(timer, padapter, rtw_tx_poll_timeout_handler, padapter);
++	rtw_tx_poll_timer_set(padapter, 1);
++	RTW_INFO("Tx poll timer init!\n");
++}
++
++void rtw_tx_poll_timeout_handler(void *FunctionContext)
++{
++	_adapter *adapter = (_adapter *)FunctionContext;
++
++	rtw_tx_poll_timer_set(adapter, 1);
++
++	if (adapter->hal_func.tx_poll_handler)
++		adapter->hal_func.tx_poll_handler(adapter);
++	else
++		RTW_WARN("hal ops: tx_poll_handler is NULL\n");
++}
++
++void rtw_tx_poll_timer_set(_adapter *padapter, u32 delay)
++{
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	_timer* timer = NULL;
++
++	timer = &pxmitpriv->tx_poll_timer;
++	_set_timer(timer, delay);
++}
++
++void rtw_tx_poll_timer_cancel(_adapter *padapter)
++{
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	_timer* timer = NULL;
++
++	if (!is_primary_adapter(padapter))
++		return;
++
++	timer = &pxmitpriv->tx_poll_timer;
++	_cancel_timer_ex(timer);
++	timer->function = NULL;
++	RTW_INFO("Tx poll timer cancel !\n");
++}
++#endif /* CONFIG_PCI_TX_POLLING */
++
++void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms)
++{
++	sctx->timeout_ms = timeout_ms;
++	sctx->submit_time = rtw_get_current_time();
++#ifdef PLATFORM_LINUX /* TODO: add condition wating interface for other os */
++	init_completion(&sctx->done);
++#endif
++	sctx->status = RTW_SCTX_SUBMITTED;
++}
++
++int rtw_sctx_wait(struct submit_ctx *sctx, const char *msg)
++{
++	int ret = _FAIL;
++	unsigned long expire;
++	int status = 0;
++
++#ifdef PLATFORM_LINUX
++	expire = sctx->timeout_ms ? msecs_to_jiffies(sctx->timeout_ms) : MAX_SCHEDULE_TIMEOUT;
++	if (!wait_for_completion_timeout(&sctx->done, expire)) {
++		/* timeout, do something?? */
++		status = RTW_SCTX_DONE_TIMEOUT;
++		RTW_INFO("%s timeout: %s\n", __func__, msg);
++	} else
++		status = sctx->status;
++#endif
++
++	if (status == RTW_SCTX_DONE_SUCCESS)
++		ret = _SUCCESS;
++
++	return ret;
++}
++
++bool rtw_sctx_chk_waring_status(int status)
++{
++	switch (status) {
++	case RTW_SCTX_DONE_UNKNOWN:
++	case RTW_SCTX_DONE_BUF_ALLOC:
++	case RTW_SCTX_DONE_BUF_FREE:
++
++	case RTW_SCTX_DONE_DRV_STOP:
++	case RTW_SCTX_DONE_DEV_REMOVE:
++		return _TRUE;
++	default:
++		return _FALSE;
++	}
++}
++
++void rtw_sctx_done_err(struct submit_ctx **sctx, int status)
++{
++	if (*sctx) {
++		if (rtw_sctx_chk_waring_status(status))
++			RTW_INFO("%s status:%d\n", __func__, status);
++		(*sctx)->status = status;
++#ifdef PLATFORM_LINUX
++		complete(&((*sctx)->done));
++#endif
++		*sctx = NULL;
++	}
++}
++
++void rtw_sctx_done(struct submit_ctx **sctx)
++{
++	rtw_sctx_done_err(sctx, RTW_SCTX_DONE_SUCCESS);
++}
++
++#ifdef CONFIG_XMIT_ACK
++int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms)
++{
++	struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops;
++
++	pack_tx_ops->submit_time = rtw_get_current_time();
++	pack_tx_ops->timeout_ms = timeout_ms;
++	pack_tx_ops->status = RTW_SCTX_SUBMITTED;
++
++	return rtw_sctx_wait(pack_tx_ops, __func__);
++}
++
++void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status)
++{
++	struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops;
++
++	if (pxmitpriv->ack_tx)
++		rtw_sctx_done_err(&pack_tx_ops, status);
++	else
++		RTW_INFO("%s ack_tx not set\n", __func__);
++}
++#endif /* CONFIG_XMIT_ACK */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/wds/rtw_wds.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/wds/rtw_wds.c
+new file mode 100644
+index 000000000..9dd0baccc
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/wds/rtw_wds.c
+@@ -0,0 +1,463 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_WDS_C_
++
++#include <drv_types.h>
++
++#if defined(CONFIG_RTW_WDS) && defined(CONFIG_AP_MODE)
++#include <linux/jhash.h>
++
++#ifdef PLATFORM_LINUX
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++static void rtw_wpath_free_rcu(struct rtw_wds_path *wpath)
++{
++	kfree_rcu(wpath, rcu);
++	rtw_mstat_update(MSTAT_TYPE_PHY, MSTAT_FREE, sizeof(struct rtw_wds_path));
++}
++#else
++static void rtw_wpath_free_rcu_callback(rtw_rcu_head *head)
++{
++	struct rtw_wds_path *wpath;
++
++	wpath = container_of(head, struct rtw_wds_path, rcu);
++	rtw_mfree(wpath, sizeof(struct rtw_wds_path));
++}
++
++static void rtw_wpath_free_rcu(struct rtw_wds_path *wpath)
++{
++	call_rcu(&wpath->rcu, rtw_wpath_free_rcu_callback);
++}
++#endif
++#endif /* PLATFORM_LINUX */
++
++static void rtw_wds_path_free_rcu(struct rtw_wds_table *tbl, struct rtw_wds_path *wpath);
++
++static u32 rtw_wds_table_hash(const void *addr, u32 len, u32 seed)
++{
++	/* Use last four bytes of hw addr as hash index */
++	return jhash_1word(*(u32 *)(addr+2), seed);
++}
++
++static const rtw_rhashtable_params rtw_wds_rht_params = {
++	.nelem_hint = 2,
++	.automatic_shrinking = true,
++	.key_len = ETH_ALEN,
++	.key_offset = offsetof(struct rtw_wds_path, dst),
++	.head_offset = offsetof(struct rtw_wds_path, rhash),
++	.hashfn = rtw_wds_table_hash,
++};
++
++static void rtw_wds_path_rht_free(void *ptr, void *tblptr)
++{
++	struct rtw_wds_path *wpath = ptr;
++	struct rtw_wds_table *tbl = tblptr;
++
++	rtw_wds_path_free_rcu(tbl, wpath);
++}
++
++static struct rtw_wds_table *rtw_wds_table_alloc(void)
++{
++	struct rtw_wds_table *newtbl;
++
++	newtbl = rtw_malloc(sizeof(struct rtw_wds_table));
++	if (!newtbl)
++		return NULL;
++
++	return newtbl;
++}
++
++static void rtw_wds_table_free(struct rtw_wds_table *tbl)
++{
++	rtw_rhashtable_free_and_destroy(&tbl->rhead,
++				    rtw_wds_path_rht_free, tbl);
++	rtw_mfree(tbl, sizeof(struct rtw_wds_table));
++}
++
++void rtw_wds_path_assign_nexthop(struct rtw_wds_path *wpath, struct sta_info *sta)
++{
++	rtw_rcu_assign_pointer(wpath->next_hop, sta);
++}
++
++static struct rtw_wds_path *rtw_wpath_lookup(struct rtw_wds_table *tbl, const u8 *dst)
++{
++	struct rtw_wds_path *wpath;
++
++	if (!tbl)
++		return NULL;
++
++	wpath = rtw_rhashtable_lookup_fast(&tbl->rhead, dst, rtw_wds_rht_params);
++
++	return wpath;
++}
++
++struct rtw_wds_path *rtw_wds_path_lookup(_adapter *adapter, const u8 *dst)
++{
++	return rtw_wpath_lookup(adapter->wds_paths, dst);
++}
++
++static struct rtw_wds_path *
++__rtw_wds_path_lookup_by_idx(struct rtw_wds_table *tbl, int idx)
++{
++	int i = 0, ret;
++	struct rtw_wds_path *wpath = NULL;
++	rtw_rhashtable_iter iter;
++
++	if (!tbl)
++		return NULL;
++
++	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
++	if (ret)
++		return NULL;
++
++	ret = rtw_rhashtable_walk_start(&iter);
++	if (ret && ret != -EAGAIN)
++		goto err;
++
++	while ((wpath = rtw_rhashtable_walk_next(&iter))) {
++		if (IS_ERR(wpath) && PTR_ERR(wpath) == -EAGAIN)
++			continue;
++		if (IS_ERR(wpath))
++			break;
++		if (i++ == idx)
++			break;
++	}
++err:
++	rtw_rhashtable_walk_stop(&iter);
++	rtw_rhashtable_walk_exit(&iter);
++
++	if (IS_ERR(wpath) || !wpath)
++		return NULL;
++
++	return wpath;
++}
++
++/**
++ * Locking: must be called within a read rcu section.
++ */
++struct rtw_wds_path *
++rtw_wds_path_lookup_by_idx(_adapter *adapter, int idx)
++{
++	return __rtw_wds_path_lookup_by_idx(adapter->wds_paths, idx);
++}
++
++void dump_wpath(void *sel, _adapter *adapter)
++{
++	struct rtw_wds_path *wpath;
++	int idx = 0;
++	char dst[ETH_ALEN];
++	char next_hop[ETH_ALEN];
++	u32 age_ms;
++
++	RTW_PRINT_SEL(sel, "num:%d\n", ATOMIC_READ(&adapter->wds_path_num));
++	RTW_PRINT_SEL(sel, "%-17s %-17s %-6s\n"
++		, "dst", "next_hop", "age"
++	);
++
++	do {
++		rtw_rcu_read_lock();
++
++		wpath = rtw_wds_path_lookup_by_idx(adapter, idx);
++		if (wpath) {
++			_rtw_memcpy(dst, wpath->dst, ETH_ALEN);
++			_rtw_memcpy(next_hop, wpath->next_hop->cmn.mac_addr, ETH_ALEN);
++			age_ms = rtw_get_passing_time_ms(wpath->last_update);
++		}
++
++		rtw_rcu_read_unlock();
++
++		if (wpath) {
++			RTW_PRINT_SEL(sel, MAC_FMT" "MAC_FMT" %6u\n"
++				, MAC_ARG(dst), MAC_ARG(next_hop)
++				, age_ms < 999999 ? age_ms : 999999
++			);
++		}
++
++		idx++;
++	} while (wpath);
++}
++
++static
++struct rtw_wds_path *rtw_wds_path_new(_adapter *adapter,
++				const u8 *dst)
++{
++	struct rtw_wds_path *new_wpath;
++
++	new_wpath = rtw_zmalloc(sizeof(struct rtw_wds_path));
++	if (!new_wpath)
++		return NULL;
++
++	new_wpath->adapter = adapter;
++	_rtw_memcpy(new_wpath->dst, dst, ETH_ALEN);
++	new_wpath->last_update = rtw_get_current_time();
++
++	return new_wpath;
++}
++
++/**
++ * Returns: 0 on success
++ *
++ * State: the initial state of the new path is set to 0
++ */
++struct rtw_wds_path *rtw_wds_path_add(_adapter *adapter,
++	const u8 *dst, struct sta_info *next_hop)
++{
++	struct rtw_wds_table *tbl = adapter->wds_paths;
++	struct rtw_wds_path *wpath, *new_wpath;
++	int ret;
++
++	if (!tbl)
++		return ERR_PTR(-ENOTSUPP);
++
++	if (_rtw_memcmp(dst, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)
++		/* never add ourselves as neighbours */
++		return ERR_PTR(-ENOTSUPP);
++
++	if (IS_MCAST(dst))
++		return ERR_PTR(-ENOTSUPP);
++
++	if (ATOMIC_INC_UNLESS(&adapter->wds_path_num, RTW_WDS_MAX_PATHS) == 0)
++		return ERR_PTR(-ENOSPC);
++
++	new_wpath = rtw_wds_path_new(adapter, dst);
++	if (!new_wpath)
++		return ERR_PTR(-ENOMEM);
++
++	do {
++		ret = rtw_rhashtable_lookup_insert_fast(&tbl->rhead,
++						    &new_wpath->rhash,
++						    rtw_wds_rht_params);
++
++		if (ret == -EEXIST)
++			wpath = rtw_rhashtable_lookup_fast(&tbl->rhead,
++						       dst,
++						       rtw_wds_rht_params);
++
++	} while (unlikely(ret == -EEXIST && !wpath));
++
++	if (ret && ret != -EEXIST)
++		return ERR_PTR(ret);
++
++	/* At this point either new_wpath was added, or we found a
++	 * matching entry already in the table; in the latter case
++	 * free the unnecessary new entry.
++	 */
++	if (ret == -EEXIST) {
++		rtw_mfree(new_wpath, sizeof(struct rtw_wds_path));
++		new_wpath = wpath;
++	}
++	rtw_wds_path_assign_nexthop(new_wpath, next_hop);
++
++	return new_wpath;
++}
++
++static void rtw_wds_path_free_rcu(struct rtw_wds_table *tbl,
++			       struct rtw_wds_path *wpath)
++{
++	_adapter *adapter = wpath->adapter;
++
++	ATOMIC_DEC(&adapter->wds_path_num);
++
++	rtw_wpath_free_rcu(wpath);
++}
++
++static void __rtw_wds_path_del(struct rtw_wds_table *tbl, struct rtw_wds_path *wpath)
++{
++	rtw_rhashtable_remove_fast(&tbl->rhead, &wpath->rhash, rtw_wds_rht_params);
++	rtw_wds_path_free_rcu(tbl, wpath);
++}
++
++void rtw_wds_path_flush_by_nexthop(struct sta_info *sta)
++{
++	_adapter *adapter = sta->padapter;
++	struct rtw_wds_table *tbl = adapter->wds_paths;
++	struct rtw_wds_path *wpath;
++	rtw_rhashtable_iter iter;
++	int ret;
++
++	if (!tbl)
++		return;
++
++	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
++	if (ret)
++		return;
++
++	ret = rtw_rhashtable_walk_start(&iter);
++	if (ret && ret != -EAGAIN)
++		goto out;
++
++	while ((wpath = rtw_rhashtable_walk_next(&iter))) {
++		if (IS_ERR(wpath) && PTR_ERR(wpath) == -EAGAIN)
++			continue;
++		if (IS_ERR(wpath))
++			break;
++
++		if (rtw_rcu_access_pointer(wpath->next_hop) == sta)
++			__rtw_wds_path_del(tbl, wpath);
++	}
++out:
++	rtw_rhashtable_walk_stop(&iter);
++	rtw_rhashtable_walk_exit(&iter);
++}
++
++static void rtw_wds_table_flush_by_iface(struct rtw_wds_table *tbl)
++{
++	struct rtw_wds_path *wpath;
++	rtw_rhashtable_iter iter;
++	int ret;
++
++	if (!tbl)
++		return;
++	
++	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
++	if (ret)
++		return;
++
++	ret = rtw_rhashtable_walk_start(&iter);
++	if (ret && ret != -EAGAIN)
++		goto out;
++
++	while ((wpath = rtw_rhashtable_walk_next(&iter))) {
++		if (IS_ERR(wpath) && PTR_ERR(wpath) == -EAGAIN)
++			continue;
++		if (IS_ERR(wpath))
++			break;
++		__rtw_wds_path_del(tbl, wpath);
++	}
++out:
++	rtw_rhashtable_walk_stop(&iter);
++	rtw_rhashtable_walk_exit(&iter);
++}
++
++void rtw_wds_path_flush_by_iface(_adapter *adapter)
++{
++	rtw_wds_table_flush_by_iface(adapter->wds_paths);
++}
++
++static int rtw_wds_table_path_del(struct rtw_wds_table *tbl,
++			  const u8 *addr)
++{
++	struct rtw_wds_path *wpath;
++
++	if (!tbl)
++		return -ENXIO;
++
++	rtw_rcu_read_lock();
++	wpath = rtw_rhashtable_lookup_fast(&tbl->rhead, addr, rtw_wds_rht_params);
++	if (!wpath) {
++		rtw_rcu_read_unlock();
++		return -ENXIO;
++	}
++
++	__rtw_wds_path_del(tbl, wpath);
++	rtw_rcu_read_unlock();
++	return 0;
++}
++
++int rtw_wds_path_del(_adapter *adapter, const u8 *addr)
++{
++	int err;
++
++	err = rtw_wds_table_path_del(adapter->wds_paths, addr);
++	return err;
++}
++
++int rtw_wds_pathtbl_init(_adapter *adapter)
++{
++	struct rtw_wds_table *tbl_path;
++	int ret;
++
++	tbl_path = rtw_wds_table_alloc();
++	if (!tbl_path)
++		return -ENOMEM;
++
++	rtw_rhashtable_init(&tbl_path->rhead, &rtw_wds_rht_params);
++
++	ATOMIC_SET(&adapter->wds_path_num, 0);
++	adapter->wds_paths = tbl_path;
++
++	return 0;
++}
++
++static
++void rtw_wds_path_tbl_expire(_adapter *adapter,
++			  struct rtw_wds_table *tbl)
++{
++	struct rtw_wds_path *wpath;
++	rtw_rhashtable_iter iter;
++	int ret;
++
++	if (!tbl)
++		return;
++
++	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
++	if (ret)
++		return;
++
++	ret = rtw_rhashtable_walk_start(&iter);
++	if (ret && ret != -EAGAIN)
++		goto out;
++
++	while ((wpath = rtw_rhashtable_walk_next(&iter))) {
++		if (IS_ERR(wpath) && PTR_ERR(wpath) == -EAGAIN)
++			continue;
++		if (IS_ERR(wpath))
++			break;
++		if (rtw_time_after(rtw_get_current_time(), wpath->last_update + RTW_WDS_PATH_EXPIRE))
++			__rtw_wds_path_del(tbl, wpath);
++	}
++
++out:
++	rtw_rhashtable_walk_stop(&iter);
++	rtw_rhashtable_walk_exit(&iter);
++}
++
++void rtw_wds_path_expire(_adapter *adapter)
++{
++	rtw_wds_path_tbl_expire(adapter, adapter->wds_paths);
++}
++
++void rtw_wds_pathtbl_unregister(_adapter *adapter)
++{
++	if (adapter->wds_paths) {
++		rtw_wds_table_free(adapter->wds_paths);
++		adapter->wds_paths = NULL;
++	}
++}
++
++int rtw_wds_nexthop_lookup(_adapter *adapter, const u8 *da, u8 *ra)
++{
++	struct rtw_wds_path *wpath;
++	struct sta_info *next_hop;
++	int err = -ENOENT;
++
++	rtw_rcu_read_lock();
++	wpath = rtw_wds_path_lookup(adapter, da);
++
++	if (!wpath)
++		goto endlookup;
++
++	next_hop = rtw_rcu_dereference(wpath->next_hop);
++	if (next_hop) {
++		_rtw_memcpy(ra, next_hop->cmn.mac_addr, ETH_ALEN);
++		err = 0;
++	}
++
++endlookup:
++	rtw_rcu_read_unlock();
++	return err;
++}
++
++#endif /* defined(CONFIG_RTW_WDS) && defined(CONFIG_AP_MODE) */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/wds/rtw_wds.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/wds/rtw_wds.h
+new file mode 100644
+index 000000000..166c37989
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/core/wds/rtw_wds.h
+@@ -0,0 +1,54 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_WDS_H_
++#define __RTW_WDS_H_
++
++#ifdef CONFIG_AP_MODE
++struct rtw_wds_path {
++	u8 dst[ETH_ALEN];
++	rtw_rhash_head rhash;
++	_adapter *adapter;
++	struct sta_info __rcu *next_hop;
++	rtw_rcu_head rcu;
++	systime last_update;
++};
++
++struct rtw_wds_table {
++	rtw_rhashtable rhead;
++};
++
++#define RTW_WDS_PATH_EXPIRE (600 * HZ)
++
++/* Maximum number of paths per interface */
++#define RTW_WDS_MAX_PATHS		1024
++
++int rtw_wds_nexthop_lookup(_adapter *adapter, const u8 *da, u8 *ra);
++
++struct rtw_wds_path *rtw_wds_path_lookup(_adapter *adapter, const u8 *dst);
++void dump_wpath(void *sel, _adapter *adapter);
++
++void rtw_wds_path_expire(_adapter *adapter);
++
++struct rtw_wds_path *rtw_wds_path_add(_adapter *adapter, const u8 *dst, struct sta_info *next_hop);
++void rtw_wds_path_assign_nexthop(struct rtw_wds_path *path, struct sta_info *sta);
++
++int rtw_wds_pathtbl_init(_adapter *adapter);
++void rtw_wds_pathtbl_unregister(_adapter *adapter);
++
++void rtw_wds_path_flush_by_nexthop(struct sta_info *sta);
++#endif /* CONFIG_AP_MODE */
++
++#endif /* __RTW_WDSH_ */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/HalPwrSeqCmd.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/HalPwrSeqCmd.c
+new file mode 100644
+index 000000000..389785c2b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/HalPwrSeqCmd.c
+@@ -0,0 +1,185 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*++
++Copyright (c) Realtek Semiconductor Corp. All rights reserved.
++
++Module Name:
++	HalPwrSeqCmd.c
++
++Abstract:
++	Implement HW Power sequence configuration CMD handling routine for Realtek devices.
++
++Major Change History:
++	When       Who               What
++	---------- ---------------   -------------------------------
++	2011-10-26 Lucas            Modify to be compatible with SD4-CE driver.
++	2011-07-07 Roger            Create.
++
++--*/
++#include <HalPwrSeqCmd.h>
++
++
++/*
++ *	Description:
++ *		This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
++ *
++ *	Assumption:
++ *		We should follow specific format which was released from HW SD.
++ *
++ *	2011.07.07, added by Roger.
++ *   */
++u8 HalPwrSeqCmdParsing(
++	PADAPTER		padapter,
++	u8				CutVersion,
++	u8				FabVersion,
++	u8				InterfaceType,
++	WLAN_PWR_CFG	PwrSeqCmd[])
++{
++	WLAN_PWR_CFG	PwrCfgCmd = {0};
++	u8				bPollingBit = _FALSE;
++	u8				bHWICSupport = _FALSE;
++	u32				AryIdx = 0;
++	u8				value = 0;
++	u32				offset = 0;
++	u8				flag = 0;
++	u32				pollingCount = 0; /* polling autoload done. */
++	u32				maxPollingCnt = 5000;
++
++	do {
++		PwrCfgCmd = PwrSeqCmd[AryIdx];
++
++
++		/* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
++		if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
++		    (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
++		    (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) {
++			switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
++			case PWR_CMD_READ:
++				break;
++
++			case PWR_CMD_WRITE:
++				offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
++
++#ifdef CONFIG_SDIO_HCI
++				/*  */
++				/* <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */
++				/* 2011.07.07. */
++				/*  */
++				if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
++					/* Read Back SDIO Local value */
++					value = SdioLocalCmd52Read1Byte(padapter, offset);
++
++					value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
++					value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
++
++					/* Write Back SDIO Local value */
++					SdioLocalCmd52Write1Byte(padapter, offset, value);
++				} else
++#endif
++				{
++#ifdef CONFIG_GSPI_HCI
++					if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
++						offset = SPI_LOCAL_OFFSET | offset;
++#endif
++					/* Read the value from system register */
++					value = rtw_read8(padapter, offset);
++
++					value = value & (~(GET_PWR_CFG_MASK(PwrCfgCmd)));
++					value = value | (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
++
++					/* Write the value back to sytem register */
++					rtw_write8(padapter, offset, value);
++				}
++				break;
++
++			case PWR_CMD_POLLING:
++
++				bPollingBit = _FALSE;
++				offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
++
++				rtw_hal_get_hwreg(padapter, HW_VAR_PWR_CMD, &bHWICSupport);
++				if (bHWICSupport && offset == 0x06) {
++					flag = 0;
++					maxPollingCnt = 100000;
++				} else
++					maxPollingCnt = 5000;
++
++#ifdef CONFIG_GSPI_HCI
++				if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
++					offset = SPI_LOCAL_OFFSET | offset;
++#endif
++				do {
++#ifdef CONFIG_SDIO_HCI
++					if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
++						value = SdioLocalCmd52Read1Byte(padapter, offset);
++					else
++#endif
++						value = rtw_read8(padapter, offset);
++
++					value = value & GET_PWR_CFG_MASK(PwrCfgCmd);
++					if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
++						bPollingBit = _TRUE;
++					else
++						rtw_udelay_os(10);
++
++					if (pollingCount++ > maxPollingCnt) {
++						RTW_ERR("HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
++
++						/* For PCIE + USB package poll power bit timeout issue only modify 8821AE and 8723BE */
++						if (bHWICSupport && offset == 0x06  && flag == 0) {
++
++							RTW_ERR("[WARNING] PCIE polling(0x%X) timeout(%d), Toggle 0x04[3] and try again.\n", offset, maxPollingCnt);
++							if (IS_HARDWARE_TYPE_8723DE(padapter))
++								PlatformEFIOWrite1Byte(padapter, 0x40, (PlatformEFIORead1Byte(padapter, 0x40)) & (~BIT3));
++
++							PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) | BIT3);
++							PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) & ~BIT3);
++
++							if (IS_HARDWARE_TYPE_8723DE(padapter))
++								PlatformEFIOWrite1Byte(padapter, 0x40, PlatformEFIORead1Byte(padapter, 0x40)|BIT3);
++
++							/* Retry Polling Process one more time */
++							pollingCount = 0;
++							flag = 1;
++						} else {
++							return _FALSE;
++						}
++					}
++				} while (!bPollingBit);
++
++				break;
++
++			case PWR_CMD_DELAY:
++				if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
++					rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
++				else
++					rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd) * 1000);
++				break;
++
++			case PWR_CMD_END:
++				/* When this command is parsed, end the process */
++				return _TRUE;
++				break;
++
++			default:
++				break;
++			}
++		}
++
++		AryIdx++;/* Add Array Index */
++	} while (1);
++
++	return _TRUE;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/btc_basic_types.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/btc_basic_types.h
+new file mode 100644
+index 000000000..c2a27a264
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/btc_basic_types.h
+@@ -0,0 +1,53 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __BTC_BASIC_TYPES_H__
++#define __BTC_BASIC_TYPES_H__
++
++#define IN
++#define OUT
++#define VOID void
++typedef void *PVOID;
++
++#define u1Byte		u8
++#define pu1Byte		u8*
++
++#define u2Byte		u16
++#define pu2Byte		u16*
++
++#define u4Byte		u32
++#define pu4Byte		u32*
++
++#define u8Byte		u64
++#define pu8Byte		u64*
++
++#define s1Byte		s8
++#define ps1Byte		s8*
++
++#define s2Byte		s16
++#define ps2Byte		s16*
++
++#define s4Byte		s32
++#define ps4Byte		s32*
++
++#define s8Byte		s64
++#define ps8Byte		s64*
++
++#define UCHAR u8
++#define USHORT u16
++#define UINT u32
++#define ULONG u32
++#define PULONG u32*
++
++#endif /* __BTC_BASIC_TYPES_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/halbtc8723d1ant.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/halbtc8723d1ant.c
+new file mode 100644
+index 000000000..889e5576a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/halbtc8723d1ant.c
+@@ -0,0 +1,5319 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/* ************************************************************
++ * Description:
++ *
++ * This file is for RTL8723D Co-exist mechanism
++ *
++ * History
++ * 2012/11/15 Cosa first check in.
++ *
++ * ************************************************************ */
++
++/* ************************************************************
++ * include files
++ * ************************************************************ */
++#include "mp_precomp.h"
++
++#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
++
++#if (RTL8723D_SUPPORT == 1)
++/* ************************************************************
++ * Global variables, these are static variables
++ * ************************************************************ */
++static u8	*trace_buf = &gl_btc_trace_buf[0];
++static struct  coex_dm_8723d_1ant		glcoex_dm_8723d_1ant;
++static struct  coex_dm_8723d_1ant	*coex_dm = &glcoex_dm_8723d_1ant;
++static struct  coex_sta_8723d_1ant		glcoex_sta_8723d_1ant;
++static struct  coex_sta_8723d_1ant	*coex_sta = &glcoex_sta_8723d_1ant;
++static struct  psdscan_sta_8723d_1ant	gl_psd_scan_8723d_1ant;
++static struct  psdscan_sta_8723d_1ant *psd_scan = &gl_psd_scan_8723d_1ant;
++
++
++const char *const glbt_info_src_8723d_1ant[] = {
++	"BT Info[wifi fw]",
++	"BT Info[bt rsp]",
++	"BT Info[bt auto report]",
++};
++
++u32	glcoex_ver_date_8723d_1ant = 20200103;
++u32	glcoex_ver_8723d_1ant = 0x35;
++u32	glcoex_ver_btdesired_8723d_1ant = 0x35;
++
++#if 0
++static
++void halbtc8723d1ant_update_ra_mask(IN struct btc_coexist *btcoexist,
++				    IN boolean force_exec, IN u32 dis_rate_mask)
++{
++	coex_dm->cur_ra_mask = dis_rate_mask;
++
++	if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
++		btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
++				   &coex_dm->cur_ra_mask);
++	coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
++}
++
++static
++void halbtc8723d1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
++		IN boolean force_exec, IN u8 type)
++{
++	boolean	wifi_under_b_mode = FALSE;
++
++	coex_dm->cur_arfr_type = type;
++
++	if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
++		switch (coex_dm->cur_arfr_type) {
++		case 0:	/* normal mode */
++			btcoexist->btc_write_4byte(btcoexist, 0x430,
++						   coex_dm->backup_arfr_cnt1);
++			btcoexist->btc_write_4byte(btcoexist, 0x434,
++						   coex_dm->backup_arfr_cnt2);
++			break;
++		case 1:
++			btcoexist->btc_get(btcoexist,
++					   BTC_GET_BL_WIFI_UNDER_B_MODE,
++					   &wifi_under_b_mode);
++			if (wifi_under_b_mode) {
++				btcoexist->btc_write_4byte(btcoexist,
++							   0x430, 0x0);
++				btcoexist->btc_write_4byte(btcoexist,
++							   0x434, 0x01010101);
++			} else {
++				btcoexist->btc_write_4byte(btcoexist,
++							   0x430, 0x0);
++				btcoexist->btc_write_4byte(btcoexist,
++							   0x434, 0x04030201);
++			}
++			break;
++		default:
++			break;
++		}
++	}
++
++	coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
++}
++
++static
++void halbtc8723d1ant_retry_limit(IN struct btc_coexist *btcoexist,
++				 IN boolean force_exec, IN u8 type)
++{
++	coex_dm->cur_retry_limit_type = type;
++
++	if (force_exec ||
++	    (coex_dm->pre_retry_limit_type !=
++	     coex_dm->cur_retry_limit_type)) {
++		switch (coex_dm->cur_retry_limit_type) {
++		case 0:	/* normal mode */
++			btcoexist->btc_write_2byte(btcoexist, 0x42a,
++						   coex_dm->backup_retry_limit);
++			break;
++		case 1:	/* retry limit=8 */
++			btcoexist->btc_write_2byte(btcoexist, 0x42a,
++						   0x0808);
++			break;
++		default:
++			break;
++		}
++	}
++
++	coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
++}
++
++static
++void halbtc8723d1ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
++				    IN boolean force_exec, IN u8 type)
++{
++	coex_dm->cur_ampdu_time_type = type;
++
++	if (force_exec ||
++	    (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
++		switch (coex_dm->cur_ampdu_time_type) {
++		case 0:	/* normal mode */
++			btcoexist->btc_write_1byte(btcoexist, 0x455,
++					   coex_dm->backup_ampdu_max_time);
++			break;
++		case 1:	/* AMPDU timw = 0x38 * 32us */
++			btcoexist->btc_write_1byte(btcoexist, 0x455,
++						   0x38);
++			break;
++		default:
++			break;
++		}
++	}
++
++	coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
++}
++#endif
++
++static void
++halbtc8723d1ant_limited_tx(struct btc_coexist *btcoexist, boolean force_exec,
++			   boolean tx_limit_en,  boolean ampdu_limit_en)
++{
++	boolean wifi_under_b_mode = FALSE;
++	u32	wifi_link_status = 0, num_of_wifi_link = 0;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
++			   &wifi_link_status);
++
++	num_of_wifi_link = wifi_link_status >> 16;
++
++	/* Force Max Tx retry limit = 8*/
++	if (!coex_sta->wl_tx_limit_en) {
++		coex_sta->wl_0x430_backup =
++			btcoexist->btc_read_4byte(btcoexist, 0x430);
++		coex_sta->wl_0x434_backup =
++			btcoexist->btc_read_4byte(btcoexist, 0x434);
++		coex_sta->wl_0x42a_backup =
++			btcoexist->btc_read_2byte(btcoexist, 0x42a);
++	}
++
++	if (!coex_sta->wl_ampdu_limit_en)
++		coex_sta->wl_0x456_backup = btcoexist->btc_read_1byte(btcoexist,
++								      0x456);
++
++	if (!force_exec && tx_limit_en == coex_sta->wl_tx_limit_en &&
++	    ampdu_limit_en == coex_sta->wl_ampdu_limit_en)
++		return;
++
++	coex_sta->wl_tx_limit_en = tx_limit_en;
++	coex_sta->wl_ampdu_limit_en = ampdu_limit_en;
++
++	if (tx_limit_en) {
++		/* Set BT polluted packet on for Tx rate adaptive not
++		 *including Tx retry break by PTA, 0x45c[19] =1
++		 *
++		 * Set queue life time to avoid can't reach tx retry limit
++		 * if tx is always break by GNT_BT.
++		 */
++		if ((wifi_link_status & WIFI_STA_CONNECTED) &&
++		     num_of_wifi_link == 1) {
++			btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1);
++			btcoexist->btc_write_1byte_bitmask(btcoexist, 0x426, 0xf, 0xf);
++		}
++
++		/* Max Tx retry limit = 8*/
++		btcoexist->btc_write_2byte(btcoexist, 0x42a, 0x0808);
++
++		/* AMPDU duration limit*/
++		btcoexist->btc_write_1byte(btcoexist, 0x456, 0x20);
++
++		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
++				   &wifi_under_b_mode);
++
++		/* Auto rate fallback step within 8 retry*/
++		if (wifi_under_b_mode) {
++			btcoexist->btc_write_4byte(btcoexist, 0x430, 0x1000000);
++			btcoexist->btc_write_4byte(btcoexist, 0x434, 0x1010101);
++		} else {
++			btcoexist->btc_write_4byte(btcoexist, 0x430, 0x1000000);
++			btcoexist->btc_write_4byte(btcoexist, 0x434, 0x4030201);
++		}
++	} else {
++		/* Set BT polluted packet on for Tx rate adaptive not
++		 *including Tx retry break by PTA, 0x45c[19] =1
++		 */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x0);
++
++		/* Set queue life time to avoid can't reach tx retry limit
++		 * if tx is always break by GNT_BT.
++		 */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x426, 0xf, 0x0);
++
++		/* Recovery Max Tx retry limit*/
++		btcoexist->btc_write_2byte(btcoexist, 0x42a,
++					   coex_sta->wl_0x42a_backup);
++		btcoexist->btc_write_4byte(btcoexist, 0x430,
++					   coex_sta->wl_0x430_backup);
++		btcoexist->btc_write_4byte(btcoexist, 0x434,
++					   coex_sta->wl_0x434_backup);
++	}
++
++	if (ampdu_limit_en)
++		btcoexist->btc_write_1byte(btcoexist, 0x456, 0x20);
++	else
++		btcoexist->btc_write_1byte(btcoexist, 0x456,
++					   coex_sta->wl_0x456_backup);
++}
++
++static void
++halbtc8723d1ant_limited_rx(struct btc_coexist *btcoexist, boolean force_exec,
++			   boolean rej_ap_agg_pkt, boolean bt_ctrl_agg_buf_size,
++			   u8 agg_buf_size)
++{
++#if 0
++	boolean reject_rx_agg = rej_ap_agg_pkt;
++	boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
++	u8 rx_agg_size = agg_buf_size;
++
++	if (!force_exec &&
++	    bt_ctrl_agg_buf_size == coex_sta->wl_rxagg_limit_en &&
++	    agg_buf_size == coex_sta->wl_rxagg_size)
++		return;
++
++	coex_sta->wl_rxagg_limit_en = bt_ctrl_agg_buf_size;
++	coex_sta->wl_rxagg_size = agg_buf_size;
++
++	/*btc->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
++	 *&reject_rx_agg);
++	 */
++	/* decide BT control aggregation buf size or not */
++	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
++			   &bt_ctrl_rx_agg_size);
++	/* aggregation buf size, only work
++	 * when BT control Rx aggregation size
++	 */
++	btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
++	/* real update aggregation setting */
++	btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
++#endif
++}
++static void
++halbtc8723d1ant_set_tdma_timer_base(struct btc_coexist *btc, u8 type)
++{
++	u16 tbtt_interval = 100;
++	u8 h2c_para[2] = {0xb, 0x1};
++			   
++	btc->btc_get(btc, BTC_GET_U2_BEACON_PERIOD, &tbtt_interval);
++			   
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], tbtt_interval = %d\n", tbtt_interval);
++	BTC_TRACE(trace_buf);
++			   
++	/* Add for JIRA coex-256 */
++	if (type == 3 && tbtt_interval < 120) { /* 4-slot  */
++		if (coex_sta->tdma_timer_base == 3)
++			return;
++			   
++		h2c_para[1] = 0xc1; /* 4-slot */
++		coex_sta->tdma_timer_base = 3;
++	} else if (tbtt_interval < 80 && tbtt_interval > 0) {
++		if (coex_sta->tdma_timer_base == 2)
++			return;
++		h2c_para[1] = (100 / tbtt_interval);
++			   
++		if (100 % tbtt_interval != 0)
++			h2c_para[1] = h2c_para[1] + 1;
++			   
++		h2c_para[1] = h2c_para[1] & 0x3f;
++		coex_sta->tdma_timer_base = 2;
++	} else if (tbtt_interval >= 180) {
++		if (coex_sta->tdma_timer_base == 1)
++			return;
++		h2c_para[1] = (tbtt_interval / 100);
++			   
++		if (tbtt_interval % 100 <= 80)
++			h2c_para[1] = h2c_para[1] - 1;
++			   
++		h2c_para[1] = h2c_para[1] & 0x3f;
++		h2c_para[1] = h2c_para[1] | 0x80;
++		coex_sta->tdma_timer_base = 1;
++	} else {
++		if (coex_sta->tdma_timer_base == 0)
++			return;
++		h2c_para[1] = 0x1;
++		coex_sta->tdma_timer_base = 0;
++	}
++			   
++	btc->btc_fill_h2c(btc, 0x69, 2, h2c_para);
++			   
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], %s() h2c_0x69 = 0x%x\n", __func__, h2c_para[1]);
++	BTC_TRACE(trace_buf);
++			   
++#if 0
++	/* no 5ms_wl_slot_extend for 4-slot mode  */
++	if (coex_sta->tdma_timer_base == 3)
++		halbtc8822b2ant_ccklock_action(btc);
++#endif
++}
++
++static
++void halbtc8723d1ant_set_fw_low_penalty_ra(IN struct btc_coexist *btcoexist,
++					   IN boolean low_penalty_ra)
++{
++	u8  h2c_parameter[6] = {0};
++
++	h2c_parameter[0] = 0x6;	/* op_code, 0x6= Retry_Penalty */
++
++	if (low_penalty_ra) {
++		h2c_parameter[1] |= BIT(0);
++
++		/* normal rate except MCS7/6/5, OFDM54/48/36 */
++		h2c_parameter[2] = 0x00;
++		h2c_parameter[3] = 0xf7;  /* MCS7 or OFDM54 */
++		h2c_parameter[4] = 0xf8;  /* MCS6 or OFDM48 */
++		h2c_parameter[5] = 0xf9;  /* MCS5 or OFDM36 */
++	}
++
++	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
++}
++
++static
++void halbtc8723d1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
++				    IN boolean force_exec,
++				    IN boolean low_penalty_ra)
++{
++	coex_dm->cur_low_penalty_ra = low_penalty_ra;
++
++	if (!force_exec) {
++		if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
++			return;
++	}
++
++	halbtc8723d1ant_set_fw_low_penalty_ra(btcoexist,
++					      coex_dm->cur_low_penalty_ra);
++
++#if 0
++	if (low_penalty_ra)
++		btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15);
++	else
++		btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0);
++#endif
++	coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
++}
++
++static
++void halbtc8723d1ant_query_bt_info(IN struct btc_coexist *btcoexist)
++{
++	u8			h2c_parameter[1] = {0};
++
++	h2c_parameter[0] |= BIT(0);	/* trigger */
++
++	btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], WL query BT info!!\n");
++	BTC_TRACE(trace_buf);
++}
++
++static
++boolean halbtc8723d1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
++{
++	u32 reg_hp_txrx, reg_lp_txrx, u32tmp, cnt_bt_all;
++	u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
++	static u8	num_of_bt_counter_chk = 0, cnt_overhead = 0,
++		cnt_autoslot_hang = 0;
++	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++	static u32 cnt_bt_pre = 0;
++	boolean is_run_coex = FALSE;
++
++	/* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */
++	/* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */
++
++	reg_hp_txrx = 0x770;
++	reg_lp_txrx = 0x774;
++
++	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
++	reg_hp_tx = u32tmp & MASKLWORD;
++	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
++
++	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
++	reg_lp_tx = u32tmp & MASKLWORD;
++	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
++
++	coex_sta->high_priority_tx = reg_hp_tx;
++	coex_sta->high_priority_rx = reg_hp_rx;
++	coex_sta->low_priority_tx = reg_lp_tx;
++	coex_sta->low_priority_rx = reg_lp_rx;
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
++				reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
++
++	BTC_TRACE(trace_buf);
++	
++	/* reset counter */
++	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
++
++	if (coex_sta->under_lps || coex_sta->under_ips ||
++	    (coex_sta->high_priority_tx == 65535 &&
++	     coex_sta->high_priority_rx == 65535 &&
++	     coex_sta->low_priority_tx == 65535 &&
++	     coex_sta->low_priority_rx == 65535))
++		coex_sta->bt_ctr_ok = FALSE;
++	else
++		coex_sta->bt_ctr_ok = TRUE;
++
++	if (!coex_sta->bt_ctr_ok)
++		return FALSE;
++
++	if (coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE) {
++		if (coex_sta->high_priority_rx >= 15) {
++			if (cnt_overhead < 3)
++				cnt_overhead++;
++
++			if (cnt_overhead == 3)
++				coex_sta->is_hipri_rx_overhead = TRUE;
++		} else {
++			if (cnt_overhead > 0)
++				cnt_overhead--;
++
++			if (cnt_overhead == 0)
++				coex_sta->is_hipri_rx_overhead = FALSE;
++		}
++	} else {
++		coex_sta->is_hipri_rx_overhead = FALSE;
++	}
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
++		    reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
++
++	BTC_TRACE(trace_buf);
++
++	if (coex_sta->low_priority_tx > 1150 &&
++	    !coex_sta->c2h_bt_inquiry_page)
++		coex_sta->pop_event_cnt++;
++
++	if (coex_sta->is_tdma_btautoslot) {
++		if (coex_sta->low_priority_tx >= 1300 &&
++		    coex_sta->low_priority_rx <= 150) {
++			if (cnt_autoslot_hang >= 2) {
++				coex_sta->is_tdma_btautoslot_hang = TRUE;
++				cnt_autoslot_hang = 2;
++			} else
++				cnt_autoslot_hang++;
++		} else {
++			if (cnt_autoslot_hang == 0)	{
++				coex_sta->is_tdma_btautoslot_hang = FALSE;
++				cnt_autoslot_hang = 0;
++			} else
++				cnt_autoslot_hang--;
++		}
++	}
++
++	if (bt_link_info->hid_only) {
++		if (coex_sta->low_priority_tx > 50)
++			coex_sta->is_hid_low_pri_tx_overhead = true;
++		else
++			coex_sta->is_hid_low_pri_tx_overhead = false;
++	}
++
++	if (!coex_sta->bt_disabled) {
++		if (coex_sta->high_priority_tx == 0 &&
++		    coex_sta->high_priority_rx == 0 &&
++		    coex_sta->low_priority_tx == 0 &&
++		    coex_sta->low_priority_rx == 0) {
++			num_of_bt_counter_chk++;
++			if (num_of_bt_counter_chk >= 3) {
++				halbtc8723d1ant_query_bt_info(btcoexist);
++				num_of_bt_counter_chk = 0;
++			}
++		}
++	}
++
++	cnt_bt_all = coex_sta->high_priority_tx +
++		     coex_sta->high_priority_rx +
++		     coex_sta->low_priority_tx +
++		     coex_sta->low_priority_rx;
++
++	if ((cnt_bt_pre > (cnt_bt_all + 50) ||
++	    cnt_bt_all > (cnt_bt_pre + 50)) &&
++	    coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE)
++		is_run_coex = TRUE;
++
++	cnt_bt_pre = cnt_bt_all;
++
++	return is_run_coex;
++}
++
++static
++void halbtc8723d1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
++{
++	s32 wifi_rssi = 0;
++	boolean wifi_busy = FALSE, wifi_under_b_mode = FALSE,
++			wifi_scan = FALSE, wifi_connected = FALSE;
++	boolean bt_idle = FALSE, wl_idle = FALSE, is_cck_deadlock = FALSE;
++	static u8 cck_lock_counter = 0, wl_noisy_count0 = 0,
++		  wl_noisy_count1 = 3, wl_noisy_count2 = 0;
++	u32 total_cnt, reg_val1, reg_val2, cnt_cck;
++	u32 cnt_crcok = 0, cnt_crcerr = 0;
++	static u8 cnt = 0, cnt_ccklocking;
++	u8	h2c_parameter[1] = {0};
++	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++
++	/*send h2c to query WL FW dbg info	*/
++	if (coex_dm->cur_ps_tdma_on) {
++		h2c_parameter[0] = 0x8;
++		btcoexist->btc_fill_h2c(btcoexist, 0x69, 1, h2c_parameter);
++	}
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
++			   &wifi_under_b_mode);
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
++
++	coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter(
++						btcoexist,
++						PHYDM_INFO_CRC32_OK_CCK);
++	coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter(
++						btcoexist,
++						PHYDM_INFO_CRC32_OK_LEGACY);
++	coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter(
++						btcoexist,
++						PHYDM_INFO_CRC32_OK_HT);
++	coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter(
++						btcoexist,
++						PHYDM_INFO_CRC32_OK_VHT);
++
++	coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter(
++						btcoexist, PHYDM_INFO_CRC32_ERROR_CCK);
++	coex_sta->crc_err_11g =  btcoexist->btc_phydm_query_PHY_counter(
++						btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY);
++	coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter(
++						btcoexist, PHYDM_INFO_CRC32_ERROR_HT);
++	coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter(
++						btcoexist,
++						PHYDM_INFO_CRC32_ERROR_VHT);
++
++	cnt_crcok =  coex_sta->crc_ok_cck + coex_sta->crc_ok_11g
++				+ coex_sta->crc_ok_11n
++				+ coex_sta->crc_ok_11n_vht;
++
++	cnt_crcerr =  coex_sta->crc_err_cck + coex_sta->crc_err_11g
++				+ coex_sta->crc_err_11n
++				+ coex_sta->crc_err_11n_vht;
++
++	/*	CCK lock identification	*/
++	if (coex_sta->cck_lock)
++		cnt_ccklocking++;
++	else if (cnt_ccklocking != 0)
++		cnt_ccklocking--;
++
++	if (cnt_ccklocking >= 3) {
++		cnt_ccklocking = 3;
++		coex_sta->cck_lock_ever = TRUE;
++	}
++
++	/* WiFi environment noisy identification */
++	cnt_cck = coex_sta->crc_ok_cck + coex_sta->crc_err_cck;
++
++	if ((!wifi_busy) && (!coex_sta->cck_lock)) {
++		if (cnt_cck > 250) {
++			if (wl_noisy_count2 < 3)
++				wl_noisy_count2++;
++
++			if (wl_noisy_count2 == 3) {
++				wl_noisy_count0 = 0;
++				wl_noisy_count1 = 0;
++			}
++
++		} else if (cnt_cck < 50) {
++			if (wl_noisy_count0 < 3)
++				wl_noisy_count0++;
++
++			if (wl_noisy_count0 == 3) {
++				wl_noisy_count1 = 0;
++				wl_noisy_count2 = 0;
++			}
++
++		} else {
++			if (wl_noisy_count1 < 3)
++				wl_noisy_count1++;
++
++			if (wl_noisy_count1 == 3) {
++				wl_noisy_count0 = 0;
++				wl_noisy_count2 = 0;
++			}
++	}
++
++		if (wl_noisy_count2 == 3)
++			coex_sta->wl_noisy_level = 2;
++		else if (wl_noisy_count1 == 3)
++			coex_sta->wl_noisy_level = 1;
++		else
++			coex_sta->wl_noisy_level = 0;
++	}
++
++}
++
++static
++void halbtc8723d1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
++{
++	struct btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
++	boolean		bt_hs_on = FALSE, bt_busy = FALSE;
++	u32		val = 0, wifi_link_status = 0, num_of_wifi_link = 0;
++	static u8		pre_num_of_profile, cur_num_of_profile, cnt;
++	static boolean	pre_ble_scan_en;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
++			   &wifi_link_status);
++
++	num_of_wifi_link = wifi_link_status >> 16;
++
++	if (coex_sta->is_ble_scan_en && !pre_ble_scan_en) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n");
++				BTC_TRACE(trace_buf);
++		coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt(btcoexist);
++
++		if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1)
++			coex_sta->bt_ble_scan_para[0]  =
++				btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x1);
++		if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2)
++			coex_sta->bt_ble_scan_para[1]  =
++				btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x2);
++		if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4)
++			coex_sta->bt_ble_scan_para[2]  =
++				btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x4);
++	}
++
++	pre_ble_scan_en = coex_sta->is_ble_scan_en;
++	coex_sta->num_of_profile = 0;
++
++	/* set link exist status */
++	if (!(coex_sta->bt_info & BT_INFO_8723D_1ANT_B_CONNECTION)) {
++		coex_sta->bt_link_exist = FALSE;
++		coex_sta->pan_exist = FALSE;
++		coex_sta->a2dp_exist = FALSE;
++		coex_sta->hid_exist = FALSE;
++		coex_sta->sco_exist = FALSE;
++	} else {	/* connection exists */
++		coex_sta->bt_link_exist = TRUE;
++		if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_FTP) {
++			coex_sta->pan_exist = TRUE;
++			coex_sta->num_of_profile++;
++		} else
++			coex_sta->pan_exist = FALSE;
++
++		if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_A2DP) {
++			coex_sta->a2dp_exist = TRUE;
++			coex_sta->num_of_profile++;
++		} else
++			coex_sta->a2dp_exist = FALSE;
++
++		if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_HID) {
++			coex_sta->hid_exist = TRUE;
++			coex_sta->num_of_profile++;
++		} else
++			coex_sta->hid_exist = FALSE;
++
++		if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_ESCO) {
++			coex_sta->sco_exist = TRUE;
++			coex_sta->num_of_profile++;
++		} else
++			coex_sta->sco_exist = FALSE;
++
++	}
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
++
++	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
++	bt_link_info->sco_exist = coex_sta->sco_exist;
++	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
++	bt_link_info->pan_exist = coex_sta->pan_exist;
++	bt_link_info->hid_exist = coex_sta->hid_exist;
++	bt_link_info->acl_busy = coex_sta->acl_busy;
++
++	/* work around for HS mode. */
++	if (bt_hs_on) {
++		bt_link_info->pan_exist = TRUE;
++		bt_link_info->bt_link_exist = TRUE;
++	}
++
++	/* check if Sco only */
++	if (bt_link_info->sco_exist &&
++	    !bt_link_info->a2dp_exist &&
++	    !bt_link_info->pan_exist &&
++	    !bt_link_info->hid_exist)
++		bt_link_info->sco_only = TRUE;
++	else
++		bt_link_info->sco_only = FALSE;
++
++	/* check if A2dp only */
++	if (!bt_link_info->sco_exist &&
++	    bt_link_info->a2dp_exist &&
++	    !bt_link_info->pan_exist &&
++	    !bt_link_info->hid_exist)
++		bt_link_info->a2dp_only = TRUE;
++	else
++		bt_link_info->a2dp_only = FALSE;
++
++	/* check if Pan only */
++	if (!bt_link_info->sco_exist &&
++	    !bt_link_info->a2dp_exist &&
++	    bt_link_info->pan_exist &&
++	    !bt_link_info->hid_exist)
++		bt_link_info->pan_only = TRUE;
++	else
++		bt_link_info->pan_only = FALSE;
++
++	/* check if Hid only */
++	if (!bt_link_info->sco_exist &&
++	    !bt_link_info->a2dp_exist &&
++	    !bt_link_info->pan_exist &&
++	    bt_link_info->hid_exist)
++		bt_link_info->hid_only = TRUE;
++	else
++		bt_link_info->hid_only = FALSE;
++
++	if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_INQ_PAGE) {
++		coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_INQ_PAGE;
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], BtInfoNotify(), BT Inq/page!!!\n");
++	} else if (!(coex_sta->bt_info & BT_INFO_8723D_1ANT_B_CONNECTION)) {
++		coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
++	} else if (coex_sta->bt_info == BT_INFO_8723D_1ANT_B_CONNECTION) {
++		/* connection exists but no busy */
++		coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE;
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
++	} else if (((coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_ESCO) ||
++		    (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_BUSY)) &&
++		   (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_ACL_BUSY)) {
++		coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY;
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n");
++	} else if ((coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_ESCO) ||
++		   (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_BUSY)) {
++		coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_SCO_BUSY;
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
++	} else if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_ACL_BUSY) {
++		coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_ACL_BUSY;
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
++	} else {
++		coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_MAX;
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
++	}
++
++	BTC_TRACE(trace_buf);
++
++	if ((BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
++	    (BT_8723D_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
++	    (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
++		bt_busy = TRUE;
++	else
++		bt_busy = FALSE;
++
++	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
++
++	cur_num_of_profile = coex_sta->num_of_profile;
++
++	if (cur_num_of_profile != pre_num_of_profile)
++		cnt = 2;
++
++	if (bt_link_info->a2dp_exist) {
++
++		if (((coex_sta->bt_a2dp_vendor_id == 0) &&
++			(coex_sta->bt_a2dp_device_name == 0)) ||
++			(cur_num_of_profile != pre_num_of_profile)) {
++
++			btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_DEVICE_INFO, &val);
++
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], BtInfoNotify(), get BT DEVICE_INFO = %x\n",
++				    val);
++			BTC_TRACE(trace_buf);
++
++			coex_sta->bt_a2dp_vendor_id = (u8)(val & 0xff);
++			coex_sta->bt_a2dp_device_name = (val & 0xffffff00) >> 8;
++		}
++
++		if (((coex_sta->legacy_forbidden_slot == 0) &&
++			(coex_sta->le_forbidden_slot == 0)) ||
++			(cur_num_of_profile != pre_num_of_profile) ||
++			(cnt > 0)) {
++
++			if (cnt > 0)
++				cnt--;
++
++			btcoexist->btc_get(btcoexist,
++					   BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL,
++					   &val);
++
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], BtInfoNotify(), get BT FORBIDDEN_SLOT_VAL = %x, cnt = %d\n",
++				    val, cnt);
++			BTC_TRACE(trace_buf);
++
++			coex_sta->legacy_forbidden_slot = (u16)(val & 0xffff);
++			coex_sta->le_forbidden_slot = (u16)((val & 0xffff0000) >> 16);
++		}
++	}
++
++	pre_num_of_profile = coex_sta->num_of_profile;
++
++	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
++		return;
++
++	if (num_of_wifi_link == 0 ||
++	    coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE) {
++		halbtc8723d1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d1ant_limited_tx(btcoexist, NORMAL_EXEC, FALSE,
++					   FALSE);
++		halbtc8723d1ant_limited_rx(btcoexist, NM_EXCU, FALSE, TRUE, 64);
++	} else if (wifi_link_status & WIFI_P2P_GO_CONNECTED ||
++		   wifi_link_status & WIFI_P2P_GC_CONNECTED) {
++		halbtc8723d1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, TRUE);
++		halbtc8723d1ant_limited_tx(btcoexist, NM_EXCU, TRUE, TRUE);
++		halbtc8723d1ant_limited_rx(btcoexist, NM_EXCU, FALSE, TRUE, 16);
++	} else {
++		halbtc8723d1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, TRUE);
++
++		if (bt_link_info->hid_exist || coex_sta->hid_pair_cnt > 0 ||
++		    bt_link_info->sco_exist) {
++			halbtc8723d1ant_limited_tx(btcoexist, NM_EXCU, TRUE,
++						   TRUE);
++			halbtc8723d1ant_limited_rx(btcoexist, NM_EXCU, FALSE,
++						   TRUE, 16);
++		} else {
++			halbtc8723d1ant_limited_tx(btcoexist, NM_EXCU, TRUE,
++						   FALSE);
++			halbtc8723d1ant_limited_rx(btcoexist, NM_EXCU, FALSE,
++						   TRUE, 64);
++		}
++	}
++}
++
++static
++void halbtc8723d1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist,
++		IN u8 type)
++{
++	u8			h2c_parameter[3] = {0};
++	u32			wifi_bw;
++	u8			wifi_central_chnl;
++
++	/* only 2.4G we need to inform bt the chnl mask */
++	btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
++			   &wifi_central_chnl);
++	if ((BTC_MEDIA_CONNECT == type) &&
++	    (wifi_central_chnl <= 14)) {
++		h2c_parameter[0] =
++			0x1;  /* enable BT AFH skip WL channel for 8723d because BT Rx LO interference */
++		/* h2c_parameter[0] = 0x0; */
++		h2c_parameter[1] = wifi_central_chnl;
++		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
++		if (BTC_WIFI_BW_HT40 == wifi_bw)
++			h2c_parameter[2] = 0x30;
++		else
++			h2c_parameter[2] = 0x20;
++	}
++
++	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
++	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
++	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
++
++	btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
++
++}
++
++static
++u8 halbtc8723d1ant_action_algorithm(IN struct btc_coexist *btcoexist)
++{
++	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
++	boolean				bt_hs_on = FALSE;
++	u8				algorithm = BT_8723D_1ANT_COEX_ALGO_UNDEFINED;
++	u8				num_of_diff_profile = 0;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
++
++	if (!bt_link_info->bt_link_exist) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], No BT link exists!!!\n");
++		BTC_TRACE(trace_buf);
++		return algorithm;
++	}
++
++	if (bt_link_info->sco_exist)
++		num_of_diff_profile++;
++	if (bt_link_info->hid_exist)
++		num_of_diff_profile++;
++	if (bt_link_info->pan_exist)
++		num_of_diff_profile++;
++	if (bt_link_info->a2dp_exist)
++		num_of_diff_profile++;
++
++	if (num_of_diff_profile == 1) {
++		if (bt_link_info->sco_exist) {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], BT Profile = SCO only\n");
++			BTC_TRACE(trace_buf);
++			algorithm = BT_8723D_1ANT_COEX_ALGO_SCO;
++		} else {
++			if (bt_link_info->hid_exist) {
++				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"[BTCoex], BT Profile = HID only\n");
++				BTC_TRACE(trace_buf);
++				algorithm = BT_8723D_1ANT_COEX_ALGO_HID;
++			} else if (bt_link_info->a2dp_exist) {
++				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"[BTCoex], BT Profile = A2DP only\n");
++				BTC_TRACE(trace_buf);
++				algorithm = BT_8723D_1ANT_COEX_ALGO_A2DP;
++			} else if (bt_link_info->pan_exist) {
++				if (bt_hs_on) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], BT Profile = PAN(HS) only\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_1ANT_COEX_ALGO_PANHS;
++				} else {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], BT Profile = PAN(EDR) only\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_1ANT_COEX_ALGO_PANEDR;
++				}
++			}
++		}
++	} else if (num_of_diff_profile == 2) {
++		if (bt_link_info->sco_exist) {
++			if (bt_link_info->hid_exist) {
++				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"[BTCoex], BT Profile = SCO + HID\n");
++				BTC_TRACE(trace_buf);
++				algorithm = BT_8723D_1ANT_COEX_ALGO_HID;
++			} else if (bt_link_info->a2dp_exist) {
++				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"[BTCoex], BT Profile = SCO + A2DP ==> SCO\n");
++				BTC_TRACE(trace_buf);
++				algorithm = BT_8723D_1ANT_COEX_ALGO_SCO;
++			} else if (bt_link_info->pan_exist) {
++				if (bt_hs_on) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], BT Profile = SCO + PAN(HS)\n");
++					BTC_TRACE(trace_buf);
++					algorithm = BT_8723D_1ANT_COEX_ALGO_SCO;
++				} else {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], BT Profile = SCO + PAN(EDR)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_1ANT_COEX_ALGO_PANEDR_HID;
++				}
++			}
++		} else {
++			if (bt_link_info->hid_exist &&
++			    bt_link_info->a2dp_exist) {
++				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"[BTCoex], BT Profile = HID + A2DP\n");
++				BTC_TRACE(trace_buf);
++				algorithm = BT_8723D_1ANT_COEX_ALGO_HID_A2DP;
++			} else if (bt_link_info->hid_exist &&
++				   bt_link_info->pan_exist) {
++				if (bt_hs_on) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], BT Profile = HID + PAN(HS)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_1ANT_COEX_ALGO_HID_A2DP;
++				} else {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], BT Profile = HID + PAN(EDR)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_1ANT_COEX_ALGO_PANEDR_HID;
++				}
++			} else if (bt_link_info->pan_exist &&
++				   bt_link_info->a2dp_exist) {
++				if (bt_hs_on) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], BT Profile = A2DP + PAN(HS)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_1ANT_COEX_ALGO_A2DP_PANHS;
++				} else {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_1ANT_COEX_ALGO_PANEDR_A2DP;
++				}
++			}
++		}
++	} else if (num_of_diff_profile == 3) {
++		if (bt_link_info->sco_exist) {
++			if (bt_link_info->hid_exist &&
++			    bt_link_info->a2dp_exist) {
++				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n");
++				BTC_TRACE(trace_buf);
++				algorithm = BT_8723D_1ANT_COEX_ALGO_HID;
++			} else if (bt_link_info->hid_exist &&
++				   bt_link_info->pan_exist) {
++				if (bt_hs_on) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], BT Profile = SCO + HID + PAN(HS)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_1ANT_COEX_ALGO_HID_A2DP;
++				} else {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_1ANT_COEX_ALGO_PANEDR_HID;
++				}
++			} else if (bt_link_info->pan_exist &&
++				   bt_link_info->a2dp_exist) {
++				if (bt_hs_on) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n");
++					BTC_TRACE(trace_buf);
++					algorithm = BT_8723D_1ANT_COEX_ALGO_SCO;
++				} else {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_1ANT_COEX_ALGO_PANEDR_HID;
++				}
++			}
++		} else {
++			if (bt_link_info->hid_exist &&
++			    bt_link_info->pan_exist &&
++			    bt_link_info->a2dp_exist) {
++				if (bt_hs_on) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_1ANT_COEX_ALGO_HID_A2DP;
++				} else {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
++				}
++			}
++		}
++	} else if (num_of_diff_profile >= 3) {
++		if (bt_link_info->sco_exist) {
++			if (bt_link_info->hid_exist &&
++			    bt_link_info->pan_exist &&
++			    bt_link_info->a2dp_exist) {
++				if (bt_hs_on) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n");
++					BTC_TRACE(trace_buf);
++
++				} else {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_1ANT_COEX_ALGO_PANEDR_HID;
++				}
++			}
++		}
++	}
++
++	return algorithm;
++}
++
++static
++void halbtc8723d1ant_write_score_board(
++	IN	struct  btc_coexist		*btcoexist,
++	IN	u16				bitpos,
++	IN	boolean		state
++)
++{
++
++	static u16 originalval = 0x8002, preval = 0x0;
++
++	if (state)
++		originalval = originalval | bitpos;
++	else
++		originalval = originalval & (~bitpos);
++
++	coex_sta->score_board_WB = originalval;
++
++	if (originalval != preval) {
++
++		preval = originalval;
++	btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
++	} else {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], halbtc8723d1ant_write_score_board: return for nochange\n");
++		BTC_TRACE(trace_buf);
++	}
++}
++
++static
++void halbtc8723d1ant_read_score_board(
++	IN	struct  btc_coexist		*btcoexist,
++	IN   u16				*score_board_val
++)
++{
++
++	*score_board_val = (btcoexist->btc_read_2byte(btcoexist,
++			    0xaa)) & 0x7fff;
++}
++
++static
++void halbtc8723d1ant_post_state_to_bt(
++	IN	struct  btc_coexist		*btcoexist,
++	IN	u16						type,
++	IN  boolean                 state
++)
++{
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], halbtc8723d1ant_post_state_to_bt: type = %d, state =%d\n",
++		type, state);
++	BTC_TRACE(trace_buf);
++
++	halbtc8723d1ant_write_score_board(btcoexist, (u16) type, state);
++}
++
++static
++boolean halbtc8723d1ant_is_wifibt_status_changed(IN struct btc_coexist
++		*btcoexist)
++{
++	static boolean	pre_wifi_busy = FALSE, pre_under_4way = FALSE,
++			pre_bt_hs_on = FALSE, pre_bt_off = FALSE,
++			pre_bt_slave = FALSE, pre_hid_low_pri_tx_overhead = FALSE,
++			pre_wifi_under_lps = FALSE, pre_bt_setup_link = FALSE,
++			pre_cck_lock = FALSE, pre_cck_lock_warn = FALSE;
++	static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0;
++	boolean wifi_busy = FALSE, under_4way = FALSE, bt_hs_on = FALSE;
++	boolean wifi_connected = FALSE;
++	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
++			   &wifi_connected);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
++			   &under_4way);
++
++	if (coex_sta->bt_disabled != pre_bt_off) {
++		pre_bt_off = coex_sta->bt_disabled;
++
++		if (coex_sta->bt_disabled)
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], BT is disabled !!\n");
++		else
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], BT is enabled !!\n");
++
++		BTC_TRACE(trace_buf);
++
++		coex_sta->bt_coex_supported_feature = 0;
++		coex_sta->bt_coex_supported_version = 0;
++		coex_sta->bt_ble_scan_type = 0;
++		coex_sta->bt_ble_scan_para[0] = 0;
++		coex_sta->bt_ble_scan_para[1] = 0;
++		coex_sta->bt_ble_scan_para[2] = 0;
++		coex_sta->bt_reg_vendor_ac = 0xffff;
++		coex_sta->bt_reg_vendor_ae = 0xffff;
++		coex_sta->legacy_forbidden_slot = 0;
++		coex_sta->le_forbidden_slot = 0;
++		coex_sta->bt_a2dp_vendor_id = 0;
++		coex_sta->bt_a2dp_device_name = 0;
++		return TRUE;
++	}
++
++	if (wifi_connected) {
++		if (wifi_busy != pre_wifi_busy) {
++			pre_wifi_busy = wifi_busy;
++
++			if (wifi_busy)
++				halbtc8723d1ant_post_state_to_bt(btcoexist,
++						BT_8723D_1ANT_SCOREBOARD_UNDERTEST, TRUE);
++			else
++				halbtc8723d1ant_post_state_to_bt(btcoexist,
++						BT_8723D_1ANT_SCOREBOARD_UNDERTEST, FALSE);
++			return TRUE;
++		}
++		if (under_4way != pre_under_4way) {
++			pre_under_4way = under_4way;
++			return TRUE;
++		}
++		if (bt_hs_on != pre_bt_hs_on) {
++			pre_bt_hs_on = bt_hs_on;
++			return TRUE;
++		}
++		if (coex_sta->wl_noisy_level != pre_wl_noisy_level) {
++			pre_wl_noisy_level = coex_sta->wl_noisy_level;
++			return TRUE;
++		}
++		if (coex_sta->under_lps != pre_wifi_under_lps) {
++			pre_wifi_under_lps = coex_sta->under_lps;
++			if (coex_sta->under_lps == TRUE)
++				return TRUE;
++		}
++		if (coex_sta->cck_lock != pre_cck_lock) {
++			pre_cck_lock = coex_sta->cck_lock;
++			return TRUE;
++		}
++		if (coex_sta->cck_lock_warn != pre_cck_lock_warn) {
++			pre_cck_lock_warn = coex_sta->cck_lock_warn;
++			return TRUE;
++		}
++	}
++
++	if (!coex_sta->bt_disabled) {
++		if (coex_sta->hid_busy_num != pre_hid_busy_num) {
++			pre_hid_busy_num = coex_sta->hid_busy_num;
++			return TRUE;
++		}
++
++		if (bt_link_info->slave_role != pre_bt_slave) {
++			pre_bt_slave = bt_link_info->slave_role;
++			return TRUE;
++		}
++
++		if (pre_hid_low_pri_tx_overhead != coex_sta->is_hid_low_pri_tx_overhead) {
++			pre_hid_low_pri_tx_overhead = coex_sta->is_hid_low_pri_tx_overhead;
++			return TRUE;
++		}
++
++		if (pre_bt_setup_link != coex_sta->is_setup_link) {
++			pre_bt_setup_link = coex_sta->is_setup_link;
++			return TRUE;
++		}
++	}
++
++	return FALSE;
++}
++
++static
++void halbtc8723d1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
++{
++	static u32		bt_disable_cnt = 0;
++	boolean		bt_active = TRUE, bt_disabled = FALSE;
++	u16		u16tmp;
++
++	/* This function check if bt is disabled
++	 * Read BT on/off status from scoreboard[1],
++	 *enable this only if BT patch support this feature
++	 */
++	halbtc8723d1ant_read_score_board(btcoexist, &u16tmp);
++	bt_active = u16tmp & BIT(1);
++
++	if (bt_active) {
++		bt_disable_cnt = 0;
++		bt_disabled = FALSE;
++		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
++				   &bt_disabled);
++	} else {
++
++		bt_disable_cnt++;
++		if (bt_disable_cnt >= 2) {
++			bt_disabled = TRUE;
++			bt_disable_cnt = 2;
++		}
++
++		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
++				   &bt_disabled);
++	}
++
++	if (coex_sta->bt_disabled != bt_disabled) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], BT is from %s to %s!!\n",
++			    (coex_sta->bt_disabled ? "disabled" : "enabled"),
++			    (bt_disabled ? "disabled" : "enabled"));
++		BTC_TRACE(trace_buf);
++		coex_sta->bt_disabled = bt_disabled;
++	}
++
++}
++
++static
++void halbtc8723d1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist,
++					boolean isenable)
++{
++#if BT_8723D_1ANT_COEX_DBG
++	if (isenable) {
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);
++
++		/* enable GNT_BT to GPIO debug */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0);
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0);
++
++		/* 0x48[20] = 0  for GPIO14 =  GNT_WL*/
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x0);
++		/* 0x40[17] = 0  for GPIO14 =  GNT_WL*/
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, 0x02, 0x0);
++
++		/* 0x66[9] = 0   for GPIO15 =  GNT_B T*/
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x02, 0x0);
++		/* 0x66[7] = 0
++		for GPIO15 =  GNT_BT*/
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, 0x80, 0x0);
++		/* 0x8[8] = 0    for GPIO15 =  GNT_BT*/
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x9, 0x1, 0x0);
++
++		/* BT Vendor Reg 0x76[0] = 0  for GPIO15 =  GNT_BT, this is not set here*/
++	} else {
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0);
++
++		/* Disable GNT_BT debug to GPIO, and enable chip_wakeup_host */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x1);
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x1);
++
++		/* 0x48[20] = 0  for GPIO14 =  GNT_WL*/
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x1);
++	}
++
++#endif
++}
++
++static
++u32 halbtc8723d1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
++		IN u16 reg_addr)
++{
++	u32 j = 0, delay_count = 0;
++
++	while (1) {
++		if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3)&BIT(5)) == 0) {
++			delay_ms(10);
++			delay_count++;
++			if (delay_count >= 10) {
++				delay_count = 0;
++				break;
++			}
++		} else
++			break;
++	}
++
++	/* wait for ready bit before access 0x7c0		 */
++	btcoexist->btc_write_4byte(btcoexist, 0x7c0, 0x800F0000 | reg_addr);
++
++	return btcoexist->btc_read_4byte(btcoexist,
++					 0x7c8);  /* get read data */
++
++}
++
++static
++void halbtc8723d1ant_ltecoex_indirect_write_reg(IN struct btc_coexist
++		*btcoexist,
++		IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value)
++{
++	u32 val, i = 0, j = 0, bitpos = 0, delay_count = 0;
++
++
++	if (bit_mask == 0x0)
++		return;
++	if (bit_mask == 0xffffffff) {
++		/* wait for ready bit before access 0x7c0/0x7c4 */
++		while (1) {
++			if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3)&BIT(5)) == 0) {
++				delay_ms(10);
++				delay_count++;
++				if (delay_count >= 10) {
++					delay_count = 0;
++					break;
++				}
++			} else
++				break;
++		}
++
++		btcoexist->btc_write_4byte(btcoexist, 0x7c4,
++					   reg_value); /* put write data */
++
++		btcoexist->btc_write_4byte(btcoexist, 0x7c0,
++					   0xc00F0000 | reg_addr);
++	} else {
++		for (i = 0; i <= 31; i++) {
++			if (((bit_mask >> i) & 0x1) == 0x1) {
++				bitpos = i;
++				break;
++			}
++		}
++
++		/* read back register value before write */
++		val = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
++				reg_addr);
++		val = (val & (~bit_mask)) | (reg_value << bitpos);
++
++		/* wait for ready bit before access 0x7c0/0x7c4 */
++		while (1) {
++			if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3)&BIT(5)) == 0) {
++				delay_ms(50);
++				delay_count++;
++				if (delay_count >= 10) {
++					delay_count = 0;
++					break;
++				}
++			} else
++				break;
++		}
++
++		btcoexist->btc_write_4byte(btcoexist, 0x7c4,
++					   val); /* put write data */
++
++		btcoexist->btc_write_4byte(btcoexist, 0x7c0,
++					   0xc00F0000 | reg_addr);
++
++	}
++
++}
++
++static
++void halbtc8723d1ant_ltecoex_enable(IN struct btc_coexist *btcoexist,
++				    IN boolean enable)
++{
++	u8 val;
++
++	val = (enable) ? 1 : 0;
++	halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80,
++			val);  /* 0x38[7] */
++
++}
++
++static
++void halbtc8723d1ant_coex_ctrl_owner(IN struct btc_coexist *btcoexist,
++				     IN boolean wifi_control)
++{
++	u8 val;
++
++	val = (wifi_control) ? 1 : 0;
++	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4,
++					   val); /* 0x70[26] */
++
++}
++
++static
++void halbtc8723d1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist,
++			IN u8 control_block, IN boolean sw_control, IN u8 state)
++{
++	u32 val = 0, val_orig = 0;
++
++	if (!sw_control)
++		val = 0x0;
++	else if (state & 0x1)
++		val = 0x3;
++	else
++		val = 0x1;
++
++	val_orig = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
++				0x38);
++
++	switch (control_block) {
++	case BT_8723D_1ANT_GNT_BLOCK_RFC_BB:
++	default:
++		val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff);
++		break;
++	case BT_8723D_1ANT_GNT_BLOCK_RFC:
++		val = (val << 14) | (val_orig & 0xffff3fff);
++		break;
++	case BT_8723D_1ANT_GNT_BLOCK_BB:
++		val = (val << 10) | (val_orig & 0xfffff3ff);
++		break;
++	}
++
++	halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist,
++				0x38, 0xffffffff, val);
++}
++
++static
++void halbtc8723d1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist,
++			IN u8 control_block, IN boolean sw_control, IN u8 state)
++{
++	u32 val = 0, val_orig = 0;
++
++	if (!sw_control)
++		val = 0x0;
++	else if (state & 0x1)
++		val = 0x3;
++	else
++		val = 0x1;
++
++	val_orig = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
++				0x38);
++
++	switch (control_block) {
++	case BT_8723D_1ANT_GNT_BLOCK_RFC_BB:
++	default:
++		val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff);
++		break;
++	case BT_8723D_1ANT_GNT_BLOCK_RFC:
++		val = (val << 12) | (val_orig & 0xffffcfff);
++		break;
++	case BT_8723D_1ANT_GNT_BLOCK_BB:
++		val = (val << 8) | (val_orig & 0xfffffcff);
++		break;
++	}
++
++	halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, 0x38,
++		0xffffffff, val);
++}
++
++static
++void halbtc8723d1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist,
++		IN u8 table_type, IN u16 table_content)
++{
++	u16 reg_addr = 0x0000;
++
++	switch (table_type) {
++	case BT_8723D_1ANT_CTT_WL_VS_LTE:
++		reg_addr = 0xa0;
++		break;
++	case BT_8723D_1ANT_CTT_BT_VS_LTE:
++		reg_addr = 0xa4;
++		break;
++	}
++
++	if (reg_addr != 0x0000)
++		halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
++			0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */
++
++
++}
++
++static
++void halbtc8723d1ant_coex_table(IN struct btc_coexist *btcoexist,
++				IN boolean force_exec, IN u32 val0x6c0,
++				IN u32 val0x6c4, IN u32 val0x6c8,
++				IN u8 val0x6cc)
++{
++	if (!force_exec) {
++		if (val0x6c0 == coex_dm->cur_val0x6c0 &&
++		    val0x6c4 == coex_dm->cur_val0x6c4 &&
++		    val0x6c8 == coex_dm->cur_val0x6c8 &&
++		    val0x6cc == coex_dm->cur_val0x6cc)
++			return;
++	}
++
++	btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
++	btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
++	btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
++	btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
++
++	coex_dm->cur_val0x6c0 = val0x6c0;
++	coex_dm->cur_val0x6c4 = val0x6c4;
++	coex_dm->cur_val0x6c8 = val0x6c8;
++	coex_dm->cur_val0x6cc = val0x6cc;
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], 0x6c0 = 0x%x, 0x6c4 = 0x%x, 0x6c8 = 0x%x, 0x6cc = 0x%x,\n",
++		    coex_dm->cur_val0x6c0, coex_dm->cur_val0x6c4,
++		    coex_dm->cur_val0x6c8, coex_dm->cur_val0x6cc);
++	BTC_TRACE(trace_buf);
++
++}
++
++static
++void halbtc8723d1ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
++		IN boolean force_exec, IN u8 type)
++{
++	u32	break_table;
++	u8	select_table;
++
++	coex_sta->coex_table_type = type;
++
++	if (coex_sta->concurrent_rx_mode_on == TRUE) {
++		break_table = 0xf0ffffff;  /* set WL hi-pri can break BT */
++		/* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */
++		select_table = 0xb;
++	} else {
++		break_table = 0xffffff;
++		select_table = 0x3;
++	}
++
++	switch (type) {
++	case 0:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0x55555555, 0x55555555, break_table,
++					   select_table);
++		break;
++	case 1:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0xa5555555, 0xaa5a5a5a, break_table,
++					   select_table);
++		break;
++	case 2:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0xaa5a5a5a, 0xaa5a5a5a, break_table,
++					   select_table);
++		break;
++	case 3:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0x55555555, 0x5a5a5a5a, break_table,
++					   select_table);
++		break;
++	case 4:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0xa5555555, 0xaa5a5a5a, break_table,
++					   select_table);
++		break;
++	case 5:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0x5a5a5a5a, 0x5a5a5a5a, break_table,
++					   select_table);
++		break;
++	case 6:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0xa5555555, 0xaa5a5a5a, break_table,
++					   select_table);
++		break;
++	case 7:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0xaa555555, 0xaa555555, break_table,
++					   select_table);
++		break;
++	case 8:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0xa5555555, 0xaaaa5aaa, break_table,
++					   select_table);
++		break;
++	case 9:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0x5a5a5a5a, 0xaaaa5aaa, break_table,
++					   select_table);
++		break;
++	case 10:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0xaaaaaaaa, 0xaaaaaaaa, break_table,
++					   select_table);
++		break;
++	case 11:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0xa5a55555, 0xaaaa5a5a, break_table,
++					   select_table);
++		break;
++	case 12:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0xa5555555, 0xaaaa5a5a, break_table,
++					   select_table);
++		break;
++	case 13:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0x65555555, 0xaa5a5a5a, break_table,
++					   select_table);
++		break;
++	case 14:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0x65555555, 0x5a5a5a5a, break_table,
++					   select_table);
++		break;
++	case 15:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0xaaaaaaaa, 0x5a5a5a5a, break_table,
++					   select_table);
++		break;
++	case 16:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0x55555555, 0xaaaaaaaa, break_table,
++					   select_table);
++		break;
++	case 17:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0x65555555, 0x65555555, break_table,
++					   select_table);
++		break;
++	case 18:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0x65555555, 0xaaaaaaaa, break_table,
++					   select_table);
++		break;
++	case 19:
++		halbtc8723d1ant_coex_table(btcoexist, force_exec,
++					   0x66555555, 0x6a5a5a5a, break_table,
++					   select_table);
++		break;
++	default:
++		break;
++	}
++}
++
++static
++void halbtc8723d1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
++		IN boolean enable)
++{
++	u8			h2c_parameter[1] = {0};
++
++	if (enable) {
++		h2c_parameter[0] |= BIT(0);		/* function enable */
++	}
++
++	btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
++}
++
++static
++void halbtc8723d1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
++				     IN boolean force_exec, IN boolean enable)
++{
++	coex_dm->cur_ignore_wlan_act = enable;
++
++	if (!force_exec) {
++		if (coex_dm->pre_ignore_wlan_act ==
++		    coex_dm->cur_ignore_wlan_act)
++			return;
++	}
++	halbtc8723d1ant_set_fw_ignore_wlan_act(btcoexist, enable);
++
++	coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
++}
++
++static
++void halbtc8723d1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
++				  IN u8 lps_val, IN u8 rpwm_val)
++{
++	u8	lps = lps_val;
++	u8	rpwm = rpwm_val;
++
++	btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
++	btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
++}
++
++static
++void halbtc8723d1ant_lps_rpwm(IN struct btc_coexist *btcoexist,
++		      IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
++{
++	coex_dm->cur_lps = lps_val;
++	coex_dm->cur_rpwm = rpwm_val;
++
++	if (!force_exec) {
++		if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
++		    (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
++			return;
++	}
++	halbtc8723d1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
++
++	coex_dm->pre_lps = coex_dm->cur_lps;
++	coex_dm->pre_rpwm = coex_dm->cur_rpwm;
++}
++
++static
++void halbtc8723d1ant_ps_tdma_check_for_power_save_state(
++	IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
++{
++	u8	lps_mode = 0x0;
++	u8	h2c_parameter[5] = {0x8, 0, 0, 0, 0};
++
++	btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
++
++	if (lps_mode) {	/* already under LPS state */
++		if (new_ps_state) {
++			/* keep state under LPS, do nothing. */
++		} else {
++			/* will leave LPS state, turn off psTdma first */
++			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
++						h2c_parameter);
++		}
++	} else {					/* NO PS state */
++		if (new_ps_state) {
++			/* will enter LPS state, turn off psTdma first */
++			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
++						h2c_parameter);
++		} else {
++			/* keep state under NO PS state, do nothing. */
++		}
++	}
++}
++
++static
++void halbtc8723d1ant_power_save_state(IN struct btc_coexist *btcoexist,
++			      IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
++{
++	boolean		low_pwr_disable = FALSE;
++
++	switch (ps_type) {
++	case BTC_PS_WIFI_NATIVE:
++		/* recover to original 32k low power setting */
++		coex_sta->force_lps_ctrl = FALSE;
++		low_pwr_disable = FALSE;
++		/* btcoexist->btc_set(btcoexist,
++				   BTC_SET_ACT_DISABLE_LOW_POWER,
++				   &low_pwr_disable); */
++		btcoexist->btc_set(btcoexist, BTC_SET_ACT_PRE_NORMAL_LPS,
++				   NULL);
++
++		break;
++	case BTC_PS_LPS_ON:
++		coex_sta->force_lps_ctrl = TRUE;
++		halbtc8723d1ant_ps_tdma_check_for_power_save_state(
++			btcoexist, TRUE);
++		halbtc8723d1ant_lps_rpwm(btcoexist, NORMAL_EXEC,
++					 lps_val, rpwm_val);
++		/* when coex force to enter LPS, do not enter 32k low power. */
++		low_pwr_disable = TRUE;
++		btcoexist->btc_set(btcoexist,
++				   BTC_SET_ACT_DISABLE_LOW_POWER,
++				   &low_pwr_disable);
++		/* power save must executed before psTdma.*/
++		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
++				   NULL);
++
++		break;
++	case BTC_PS_LPS_OFF:
++		coex_sta->force_lps_ctrl = TRUE;
++		halbtc8723d1ant_ps_tdma_check_for_power_save_state(
++			btcoexist, FALSE);
++		btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
++				   NULL);
++
++		break;
++	default:
++		break;
++	}
++}
++
++static
++void halbtc8723d1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
++	   IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
++{
++	u8			h2c_parameter[5] = {0};
++	u8			real_byte1 = byte1, real_byte5 = byte5;
++	boolean			ap_enable = FALSE;
++	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++	u8		ps_type = BTC_PS_WIFI_NATIVE;
++
++	if (byte5 & BIT(2))
++		coex_sta->is_tdma_btautoslot = TRUE;
++	else
++		coex_sta->is_tdma_btautoslot = FALSE;
++
++	/* release bt-auto slot for auto-slot hang is detected!! */
++	if (coex_sta->is_tdma_btautoslot)
++		if ((coex_sta->is_tdma_btautoslot_hang) ||
++			(bt_link_info->slave_role))
++			byte5 = byte5 & 0xfb;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
++			   &ap_enable);
++
++	if ((ap_enable) && (byte1 & BIT(4) && !(byte1 & BIT(5)))) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], FW for AP mode\n");
++		BTC_TRACE(trace_buf);
++		real_byte1 &= ~BIT(4);
++		real_byte1 |= BIT(5);
++
++		real_byte5 |= BIT(5);
++		real_byte5 &= ~BIT(6);
++
++		ps_type = BTC_PS_WIFI_NATIVE;
++		halbtc8723d1ant_power_save_state(btcoexist,
++					ps_type, 0x0,
++					0x0);
++	} else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
++
++		ps_type = BTC_PS_LPS_ON;
++		halbtc8723d1ant_power_save_state(
++			btcoexist, ps_type, 0x50,
++			0x4);
++	} else {
++		ps_type = BTC_PS_WIFI_NATIVE;
++		halbtc8723d1ant_power_save_state(btcoexist, ps_type,
++						 0x0,
++						 0x0);
++	}
++
++	h2c_parameter[0] = real_byte1;
++	h2c_parameter[1] = byte2;
++	h2c_parameter[2] = byte3;
++	h2c_parameter[3] = byte4;
++	h2c_parameter[4] = real_byte5;
++
++	coex_dm->ps_tdma_para[0] = real_byte1;
++	coex_dm->ps_tdma_para[1] = byte2;
++	coex_dm->ps_tdma_para[2] = byte3;
++	coex_dm->ps_tdma_para[3] = byte4;
++	coex_dm->ps_tdma_para[4] = real_byte5;
++
++	btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
++
++	if (ps_type == BTC_PS_WIFI_NATIVE)
++		btcoexist->btc_set(btcoexist, BTC_SET_ACT_POST_NORMAL_LPS, NULL);
++}
++
++static
++void halbtc8723d1ant_ps_tdma(IN struct btc_coexist *btcoexist,
++		     IN boolean force_exec, IN boolean turn_on, IN u8 tcase)
++{
++	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++	struct  btc_board_info	*board_info = &btcoexist->board_info;
++	boolean	wifi_busy = FALSE;
++	static u8 tdma_byte4_modify, pre_tdma_byte4_modify, type;
++	static boolean	 pre_wifi_busy = FALSE;
++	
++	btcoexist->btc_set_atomic(btcoexist, &coex_dm->setting_tdma, TRUE);
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++
++	/* tcase: bit0~7 --> tdma case index
++	 *        bit8   --> for 4-slot (50ms) mode
++	 */
++	if (tcase & TDMA_4SLOT)/* 4-slot (50ms) mode */
++		halbtc8723d1ant_set_tdma_timer_base(btcoexist, 3);
++	else
++		halbtc8723d1ant_set_tdma_timer_base(btcoexist, 0);
++	
++	type = tcase & 0xff;
++
++	if (wifi_busy != pre_wifi_busy) {
++		force_exec = TRUE;
++		pre_wifi_busy = wifi_busy;
++	}
++
++	/* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
++	if (bt_link_info->slave_role && bt_link_info->a2dp_exist)
++		tdma_byte4_modify = 0x1;
++	else
++		tdma_byte4_modify = 0x0;
++
++	if (pre_tdma_byte4_modify != tdma_byte4_modify) {
++		force_exec = TRUE;
++		pre_tdma_byte4_modify = tdma_byte4_modify;
++	}
++
++	if (!force_exec) {
++		if (turn_on == coex_dm->cur_ps_tdma_on &&
++		    type == coex_dm->cur_ps_tdma) {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n",
++				    (coex_dm->cur_ps_tdma_on ? "on" : "off"),
++				    coex_dm->cur_ps_tdma);
++			BTC_TRACE(trace_buf);
++
++			btcoexist->btc_set_atomic(btcoexist,
++						  &coex_dm->setting_tdma,
++						  FALSE);
++			return;
++		}
++	}
++
++	if (turn_on) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], ********** TDMA(on, %d)\n", type);
++		BTC_TRACE(trace_buf);
++		
++		if (coex_sta->a2dp_exist && coex_sta->bt_inq_page_remain)
++			halbtc8723d1ant_post_state_to_bt(btcoexist,
++						 BT_8723D_1ANT_SCOREBOARD_TDMA,
++						 FALSE);
++		else
++			halbtc8723d1ant_post_state_to_bt(btcoexist,
++						 BT_8723D_1ANT_SCOREBOARD_TDMA,
++						 TRUE);
++		
++		/* enable TBTT interrupt */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, 0x1);
++	} else {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], ********** TDMA(off, %d)\n", type);
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d1ant_post_state_to_bt(btcoexist,
++						 BT_8723D_1ANT_SCOREBOARD_TDMA,
++						 FALSE);
++	}
++
++
++	if (turn_on) {
++		switch (type) {
++		default:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x35, 0x03, 0x11, 0x11);
++			break;
++		case 3:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x30, 0x03, 0x10, 0x50);
++			break;
++		case 4:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x21, 0x03, 0x10, 0x50);
++			break;
++		case 5:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x3a, 0x03, 0x11, 0x11);
++			break;
++		case 6:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x20, 0x03, 0x11, 0x11);
++			break;
++		case 7:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x10, 0x03, 0x10,  0x54 |
++						      tdma_byte4_modify);
++			break;
++		case 8:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x10, 0x03, 0x10,  0x54 |
++						      tdma_byte4_modify);
++			break;
++		case 9:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x10, 0x03, 0x10,  0x54 |
++						      tdma_byte4_modify);
++			break;
++		case 10:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x30, 0x03, 0x11, 0x10);
++			break;
++		case 11:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x25, 0x03, 0x11,  0x11 |
++						      tdma_byte4_modify);
++			break;
++		case 12:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x35, 0x03, 0x10,  0x50 |
++						      tdma_byte4_modify);
++			break;
++		case 13:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x10, 0x07, 0x10,  0x54 |
++						      tdma_byte4_modify);
++			break;
++		case 14:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x15, 0x03, 0x10,  0x50 |
++						      tdma_byte4_modify);
++			break;
++		case 15:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x10, 0x03, 0x10,  0x50);
++			break;
++		case 16:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x10, 0x03, 0x11,  0x15 |
++						      tdma_byte4_modify);
++			break;
++		case 17:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x10, 0x03, 0x11, 0x14);
++			break;
++		case 18:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x30, 0x03, 0x10,  0x50 |
++						      tdma_byte4_modify);
++			break;
++		case 19:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x15, 0x03, 0x11, 0x10);
++			break;
++		case 20:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x30, 0x03, 0x11, 0x10);
++			break;
++		case 21:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x30, 0x03, 0x11, 0x10);
++			break;
++		case 22:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x25, 0x03, 0x11, 0x10);
++			break;
++		case 23:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x10, 0x03, 0x11, 0x10);
++			break;
++		case 24:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x08, 0x03, 0x10,  0x54 |
++						      tdma_byte4_modify);
++			break;
++		case 25:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x3a, 0x03, 0x11, 0x50);
++			break;
++		case 26:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x10, 0x03, 0x10,  0x55);
++			break;
++		case 27:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x10, 0x03, 0x11, 0x15);
++			break;
++		case 28:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x10, 0x0b, 0x10,  0x54);
++			break;
++		case 29:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x0c, 0x03, 0x10,  0x54);
++			break;
++		case 32:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x35, 0x03, 0x11, 0x11);
++			break;
++		case 33:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x35, 0x03, 0x11, 0x10);
++			break;
++		case 34:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x3f, 0x03, 0x11, 0x10);
++			break;	
++		case 36:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x48, 0x03, 0x11, 0x10);
++			break;
++		case 57:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x10, 0x03, 0x10,  0x50 |
++						      tdma_byte4_modify);
++			break;
++		case 58:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x10, 0x03, 0x10,  0x51);
++			break;
++		case 67:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x10, 0x03, 0x11,  0x10 |
++						      tdma_byte4_modify);
++			break;
++		/*     1-Ant to 2-Ant      TDMA case */
++		case 103:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0xd3,
++						      0x3a, 0x03, 0x70, 0x10);
++			break;
++		case 104:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0xd3,
++						      0x21, 0x03, 0x70, 0x10);
++			break;
++		case 105:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0xe3,
++						      0x15, 0x03, 0x71, 0x11);
++			break;
++		case 106:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0xe3,
++						      0x20, 0x03, 0x71, 0x11);
++			break;
++		case 107:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0xd3,
++						      0x10, 0x03, 0x70,  0x14 |
++						      tdma_byte4_modify);
++			break;
++		case 108:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0xd3,
++						      0x10, 0x03, 0x70,  0x14 |
++						      tdma_byte4_modify);
++			break;
++		case 113:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0xd3,
++						      0x25, 0x03, 0x70,  0x10 |
++						      tdma_byte4_modify);
++			break;
++		case 114:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0xd3,
++						      0x15, 0x03, 0x70,  0x10 |
++						      tdma_byte4_modify);
++			break;
++		case 115:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0xd3,
++						      0x20, 0x03, 0x70,  0x10 |
++						      tdma_byte4_modify);
++			break;
++		case 117:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0xe3,
++						      0x10, 0x03, 0x71,  0x14 |
++						      tdma_byte4_modify);
++			break;
++		case 119:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0xe3,
++						      0x15, 0x03, 0x71, 0x10);
++			break;
++		case 120:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0xe3,
++						      0x30, 0x03, 0x71, 0x10);
++			break;
++		case 121:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0xe3,
++						      0x30, 0x03, 0x71, 0x10);
++			break;
++		case 122:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0xe3,
++						      0x25, 0x03, 0x71, 0x10);
++			break;
++		case 132:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0xe3,
++						      0x35, 0x03, 0x71, 0x11);
++			break;
++		case 133:
++			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0xe3,
++						      0x35, 0x03, 0x71, 0x10);
++			break;
++		}
++	} else {
++
++		/* disable PS tdma */
++		switch (type) {
++		case 8: /* PTA Control */
++			halbtc8723d1ant_set_fw_pstdma(btcoexist,
++						      0x8, 0x0, 0x0, 0x0, 0x0);
++			break;
++		case 0:
++		default:  /* Software control, Antenna at BT side */
++			halbtc8723d1ant_set_fw_pstdma(btcoexist,
++						      0x0, 0x0, 0x0, 0x0, 0x0);
++			break;
++		case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */
++			halbtc8723d1ant_set_fw_pstdma(btcoexist,
++						      0x0, 0x0, 0x0, 0x48, 0x0);
++			break;
++		}
++	}
++
++	/* update pre state */
++	coex_dm->cur_ps_tdma_on = turn_on;
++	coex_dm->cur_ps_tdma = type;
++
++	btcoexist->btc_set_atomic(btcoexist, &coex_dm->setting_tdma, FALSE);
++}
++
++static
++void halbtc8723d1ant_set_ant_path(IN struct btc_coexist *btcoexist,
++				  IN u8 ant_pos_type, IN boolean force_exec,
++				  IN u8 phase)
++{
++	struct  btc_board_info *board_info = &btcoexist->board_info;
++	u32			cnt_bt_cal_chk = 0;
++	boolean			is_in_mp_mode = FALSE, is_hw_ant_div_on = FALSE;
++	u8			u8tmp0 = 0, u8tmp1 = 0;
++	u32			u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
++	u16			u16tmp0, u16tmp1 = 0;
++
++#if 0
++
++	if (ant_pos_type == BTC_ANT_PATH_PTA) {
++		if ((board_info->btdm_ant_det_finish) &&
++		    (board_info->btdm_ant_num_by_ant_det == 2)) {
++			if (board_info->btdm_ant_pos ==
++			    BTC_ANTENNA_AT_MAIN_PORT)
++				ant_pos_type = BTC_ANT_PATH_WIFI;
++			else
++				ant_pos_type = BTC_ANT_PATH_BT;
++		}
++	}
++
++#endif
++
++#if BT_8723D_1ANT_COEX_DBG
++
++	u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
++
++	/* To avoid indirect access fail	*/
++	if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) {
++		force_exec = TRUE;
++		coex_sta->gnt_error_cnt++;
++	}
++
++	u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
++	u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0xaa);
++	u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948);
++	u8tmp1  = btcoexist->btc_read_1byte(btcoexist, 0x73);
++	u8tmp0 =  btcoexist->btc_read_1byte(btcoexist, 0x67);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(Before Set Ant Pat)\n",
++		    u8tmp0, u16tmp1, u8tmp1);
++	BTC_TRACE(trace_buf);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], **********0x38= 0x%x, 0x54= 0x%x, 0xaa = 0x%x(Before Set Ant Path)\n",
++		    u32tmp1, u32tmp2, u16tmp0);
++	BTC_TRACE(trace_buf);
++#endif
++
++	coex_dm->cur_ant_pos_type = ant_pos_type;
++
++	if (!force_exec) {
++		if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], Skip Antenna Path Setup because no change!!\n");
++			BTC_TRACE(trace_buf);
++			return;
++		}
++	}
++
++	coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
++
++
++	switch (phase) {
++	case BT_8723D_1ANT_PHASE_COEX_POWERON:
++		/* Set Path control to WL */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67,
++						   0x80, 0x0);
++
++		/* set Path control owner to WL at initial step */
++		halbtc8723d1ant_coex_ctrl_owner(btcoexist,
++						BT_8723D_1ANT_PCO_BTSIDE);
++
++		if (BTC_ANT_PATH_AUTO == ant_pos_type)
++			ant_pos_type = BTC_ANT_PATH_BT;
++
++		coex_sta->run_time_state = FALSE;
++
++		break;
++	case BT_8723D_1ANT_PHASE_COEX_INIT:
++		/* Disable LTE Coex Function in WiFi side
++		 *(this should be on if LTE coex is required)
++		 */
++		halbtc8723d1ant_ltecoex_enable(btcoexist, 0x0);
++
++		/* GNT_WL_LTE always = 1
++		 *(this should be config if LTE coex is required)
++		 */
++		halbtc8723d1ant_ltecoex_set_coex_table(btcoexist,
++				       BT_8723D_1ANT_CTT_WL_VS_LTE, 0xffff);
++
++		/* GNT_BT_LTE always = 1
++		 *(this should be config if LTE coex is required)
++		 */
++		halbtc8723d1ant_ltecoex_set_coex_table(btcoexist,
++				       BT_8723D_1ANT_CTT_BT_VS_LTE, 0xffff);
++
++		/* Wait If BT IQK running, because Path control owner is
++		 *at BT during BT IQK (setup by WiFi firmware)
++		 */
++		while (cnt_bt_cal_chk <= 20) {
++			u8tmp0 = btcoexist->btc_read_1byte(btcoexist,
++							   0x49d);
++			cnt_bt_cal_chk++;
++			if (u8tmp0 & BIT(0)) {
++				BTC_SPRINTF(trace_buf,
++					    BT_TMP_BUF_SIZE,
++					    "[BTCoex],  BT is calibrating (wait cnt=%d)\n",
++					    cnt_bt_cal_chk);
++				BTC_TRACE(trace_buf);
++				delay_ms(50);
++			} else {
++				BTC_SPRINTF(trace_buf,
++					    BT_TMP_BUF_SIZE,
++					    "[BTCoex], WL is NOT calibrating (wait cnt=%d)\n",
++					    cnt_bt_cal_chk);
++				BTC_TRACE(trace_buf);
++				break;
++			}
++		}
++
++		/* Set Path control to WL */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1);
++
++		/* set Path control owner to WL at initial step */
++		halbtc8723d1ant_coex_ctrl_owner(btcoexist,
++						BT_8723D_1ANT_PCO_WLSIDE);
++
++		/* set GNT_BT to SW high */
++		halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist,
++					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
++		/* Set GNT_WL to SW low */
++		halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist,
++					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
++
++		if (BTC_ANT_PATH_AUTO == ant_pos_type)
++			ant_pos_type = BTC_ANT_PATH_BT;
++
++		coex_sta->run_time_state = FALSE;
++		break;
++	case BT_8723D_1ANT_PHASE_WLANONLY_INIT:
++		/* Disable LTE Coex Function in WiFi side
++		 *(this should be on if LTE coex is required)
++		 */
++		halbtc8723d1ant_ltecoex_enable(btcoexist, 0x0);
++
++		/* GNT_WL_LTE always = 1
++		 *(this should be config if LTE coex is required)
++		 */
++		halbtc8723d1ant_ltecoex_set_coex_table(btcoexist,
++				       BT_8723D_1ANT_CTT_WL_VS_LTE, 0xffff);
++
++		/* GNT_BT_LTE always = 1
++		 *(this should be config if LTE coex is required)
++		 */
++		halbtc8723d1ant_ltecoex_set_coex_table(btcoexist,
++				       BT_8723D_1ANT_CTT_BT_VS_LTE, 0xffff);
++
++		/* Set Path control to WL */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1);
++
++		/* set Path control owner to WL at initial step */
++		halbtc8723d1ant_coex_ctrl_owner(btcoexist,
++						BT_8723D_1ANT_PCO_WLSIDE);
++
++		/* set GNT_BT to SW low */
++		halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist,
++					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_1ANT_SIG_STA_SET_TO_LOW);
++		/* Set GNT_WL to SW high */
++		halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist,
++					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
++
++		if (BTC_ANT_PATH_AUTO == ant_pos_type)
++			ant_pos_type = BTC_ANT_PATH_WIFI;
++
++		coex_sta->run_time_state = FALSE;
++		break;
++	case BT_8723D_1ANT_PHASE_WLAN_OFF:
++		/* Disable LTE Coex Function in WiFi side */
++		halbtc8723d1ant_ltecoex_enable(btcoexist, 0x0);
++
++		/* Set Path control to BT */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67,
++						   0x80, 0x0);
++
++		/* set Path control owner to BT */
++		halbtc8723d1ant_coex_ctrl_owner(btcoexist,
++						BT_8723D_1ANT_PCO_BTSIDE);
++
++		/* halbtc8723d1ant_ignore_wlan_act
++		 * (btcoexist, FORCE_EXEC, TRUE);
++		 */
++
++		if (BTC_ANT_PATH_AUTO == ant_pos_type)
++			ant_pos_type = BTC_ANT_PATH_BT;
++
++		coex_sta->run_time_state = FALSE;
++		break;
++	case BT_8723D_1ANT_PHASE_2G_RUNTIME:
++
++		/* wait for WL/BT IQK finish, keep 0x38 = 0xff00 for WL IQK */
++		while (cnt_bt_cal_chk <= 20) {
++			u8tmp0 = btcoexist->btc_read_1byte(btcoexist, 0x1e6);
++
++			u8tmp1 = btcoexist->btc_read_1byte(btcoexist, 0x49d);
++
++			cnt_bt_cal_chk++;
++			if ((u8tmp0 & BIT(0)) || (u8tmp1 & BIT(0))) {
++				BTC_SPRINTF(trace_buf,
++					    BT_TMP_BUF_SIZE,
++					    "[BTCoex], ########### WL or BT is IQK (wait cnt=%d)\n",
++					    cnt_bt_cal_chk);
++				BTC_TRACE(trace_buf);
++				delay_ms(50);
++			} else {
++				BTC_SPRINTF(trace_buf,
++					    BT_TMP_BUF_SIZE,
++					    "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n",
++					    cnt_bt_cal_chk);
++				BTC_TRACE(trace_buf);
++				break;
++			}
++		}
++
++
++		/* Set Path control to WL */
++		/* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1); */
++
++		halbtc8723d1ant_coex_ctrl_owner(btcoexist,
++						BT_8723D_1ANT_PCO_WLSIDE);
++
++		/* set GNT_BT to PTA */
++		halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist,
++					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_PTA,
++					   BT_8723D_1ANT_SIG_STA_SET_BY_HW);
++		/* Set GNT_WL to PTA */
++		halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist,
++					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_PTA,
++					   BT_8723D_1ANT_SIG_STA_SET_BY_HW);
++
++		if (BTC_ANT_PATH_AUTO == ant_pos_type)
++			ant_pos_type = BTC_ANT_PATH_PTA;
++
++		coex_sta->run_time_state = TRUE;
++		break;
++	case BT_8723D_1ANT_PHASE_BTMPMODE:
++		halbtc8723d1ant_coex_ctrl_owner(btcoexist,
++						BT_8723D_1ANT_PCO_WLSIDE);
++
++		/* Set Path control to WL */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1);
++
++		/* set GNT_BT to high */
++		halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist,
++					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
++		/* Set GNT_WL to low */
++		halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist,
++					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_1ANT_SIG_STA_SET_TO_LOW);
++
++		if (BTC_ANT_PATH_AUTO == ant_pos_type)
++			ant_pos_type = BTC_ANT_PATH_BT;
++
++		coex_sta->run_time_state = FALSE;
++		break;
++	case BT_8723D_1ANT_PHASE_ANTENNA_DET:
++		halbtc8723d1ant_coex_ctrl_owner(btcoexist,
++						BT_8723D_1ANT_PCO_WLSIDE);
++
++		/* Set Path control to WL */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1);
++
++		/* set GNT_BT to high */
++		halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist,
++					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
++		/* Set GNT_WL to high */
++		halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist,
++					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
++
++		if (BTC_ANT_PATH_AUTO == ant_pos_type)
++			ant_pos_type = BTC_ANT_PATH_BT;
++
++		coex_sta->run_time_state = FALSE;
++
++		break;
++	}
++
++
++	is_hw_ant_div_on = board_info->ant_div_cfg;
++
++	if ((is_hw_ant_div_on) && (phase != BT_8723D_1ANT_PHASE_ANTENNA_DET))
++
++		if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT)
++			/* 0x948 = 0x200, 0x0 while antenna diversity */
++			btcoexist->btc_write_2byte(btcoexist, 0x948, 0x100);
++		else /* 0x948 = 0x80, 0x0 while antenna diversity */
++			btcoexist->btc_write_2byte(btcoexist, 0x948, 0x40);
++
++	else if ((is_hw_ant_div_on == FALSE) &&
++		(phase != BT_8723D_1ANT_PHASE_WLAN_OFF)) {
++		/* internal switch setting */
++
++		switch (ant_pos_type) {
++
++		case BTC_ANT_PATH_WIFI:
++			if (board_info->btdm_ant_pos ==
++			    BTC_ANTENNA_AT_MAIN_PORT)
++
++				btcoexist->btc_write_2byte(btcoexist,
++							   0x948, 0x0);
++			else
++				btcoexist->btc_write_2byte(btcoexist,
++							   0x948, 0x280);
++
++			break;
++		case BTC_ANT_PATH_BT:
++			if (board_info->btdm_ant_pos ==
++			    BTC_ANTENNA_AT_MAIN_PORT)
++				btcoexist->btc_write_2byte(btcoexist,
++							   0x948, 0x280);
++			else
++				btcoexist->btc_write_2byte(btcoexist,
++							   0x948, 0x0);
++
++			break;
++		default:
++		case BTC_ANT_PATH_PTA:
++			if (board_info->btdm_ant_pos ==
++			    BTC_ANTENNA_AT_MAIN_PORT)
++				btcoexist->btc_write_2byte(btcoexist,
++							   0x948, 0x200);
++			else
++				btcoexist->btc_write_2byte(btcoexist,
++							   0x948, 0x80);
++			break;
++		}
++	}
++
++
++#if BT_8723D_1ANT_COEX_DBG
++	u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
++	u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
++	u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0xaa);
++	u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948);
++	u8tmp1  = btcoexist->btc_read_1byte(btcoexist, 0x73);
++	u8tmp0 =  btcoexist->btc_read_1byte(btcoexist, 0x67);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(After Set Ant Pat)\n",
++		    u8tmp0, u16tmp1, u8tmp1);
++	BTC_TRACE(trace_buf);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], 0x38= 0x%x, 0x54= 0x%x, 0xaa = 0x%x(After Set Ant Path)\n",
++		    u32tmp1, u32tmp2, u16tmp0);
++	BTC_TRACE(trace_buf);
++#endif
++
++}
++
++static
++boolean halbtc8723d1ant_is_common_action(IN struct btc_coexist *btcoexist)
++{
++	boolean			common = FALSE, wifi_connected = FALSE, wifi_busy = FALSE;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
++			   &wifi_connected);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++
++	if (!wifi_connected &&
++	    BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
++	    coex_dm->bt_status) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n");
++		BTC_TRACE(trace_buf);
++		common = TRUE;
++	} else if (wifi_connected &&
++		   (BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
++		    coex_dm->bt_status)) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], Wifi connected + BT non connected-idle!!\n");
++		BTC_TRACE(trace_buf);
++		common = TRUE;
++	} else if (!wifi_connected &&
++		   (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE ==
++		    coex_dm->bt_status)) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], Wifi non connected-idle + BT connected-idle!!\n");
++		BTC_TRACE(trace_buf);
++		common = TRUE;
++	} else if (wifi_connected &&
++		   (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE ==
++		    coex_dm->bt_status)) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], Wifi connected + BT connected-idle!!\n");
++		BTC_TRACE(trace_buf);
++		common = TRUE;
++	} else if (!wifi_connected &&
++		   (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE !=
++		    coex_dm->bt_status)) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], Wifi non connected-idle + BT Busy!!\n");
++		BTC_TRACE(trace_buf);
++		common = TRUE;
++	} else {
++		if (wifi_busy) {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
++			BTC_TRACE(trace_buf);
++		} else {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
++			BTC_TRACE(trace_buf);
++		}
++
++		common = FALSE;
++	}
++
++	return common;
++}
++
++
++/* *********************************************
++ *
++ *	Non-Software Coex Mechanism start
++ *
++ * ********************************************* */
++static
++void halbtc8723d1ant_action_bt_whql_test(IN struct btc_coexist *btcoexist)
++{
++	halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
++				     BT_8723D_1ANT_PHASE_2G_RUNTIME);
++	halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++	halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
++}
++
++static
++void halbtc8723d1ant_action_bt_hs(IN struct btc_coexist *btcoexist)
++{
++	halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
++	halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 5);
++}
++
++static
++void halbtc8723d1ant_action_bt_relink(IN struct btc_coexist *btcoexist)
++{
++	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++
++	if ((!coex_sta->is_bt_multi_link && !bt_link_info->pan_exist) ||
++	    (bt_link_info->a2dp_exist && bt_link_info->hid_exist)) {
++		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
++	}
++}
++
++static
++void halbtc8723d1ant_action_bt_idle(IN struct btc_coexist *btcoexist)
++{
++	boolean wifi_busy = FALSE;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++
++	if (!wifi_busy) {
++		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
++		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 6);
++	} else {
++		/* if wl busy and not support mesh mode*/
++		if (!coex_sta->is_bt_mesh_ver) {
++			if (BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE == coex_dm->bt_status) {
++				halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
++				halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 34);
++			} else {
++				halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
++				halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32);
++			}
++		} else {
++		/*Support BT mesh*/
++			if (coex_sta->bt_mesh_on) {
++				halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
++				halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 19);
++			} else {
++				halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
++				halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33);
++			}
++		}
++	}
++}
++
++static
++void halbtc8723d1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
++{
++	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++	boolean wifi_connected = FALSE, wifi_busy = FALSE, bt_busy = FALSE;
++	boolean wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
++			   &wifi_connected);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
++
++	if (coex_sta->bt_create_connection &&
++	    (coex_sta->wifi_is_high_pri_task || coex_sta->wifi_in_scan_task)) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], Wifi Scan/hi-pri-task + BT Inq/Page!!\n");
++		BTC_TRACE(trace_buf);
++
++		if (bt_link_info->a2dp_exist && !bt_link_info->pan_exist) {
++			halbtc8723d1ant_coex_table_with_type(btcoexist,
++							     NORMAL_EXEC, 1);
++			halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 17);
++		} else if (coex_sta->wifi_is_high_pri_task) {
++			halbtc8723d1ant_coex_table_with_type(btcoexist,
++							     NORMAL_EXEC, 16);
++			halbtc8723d1ant_ps_tdma(btcoexist,
++						NORMAL_EXEC, TRUE, 36);
++		} else if (coex_sta->wifi_in_scan_task) {
++			halbtc8723d1ant_coex_table_with_type(btcoexist,
++							     NORMAL_EXEC, 1);
++			halbtc8723d1ant_ps_tdma(btcoexist,
++						NORMAL_EXEC, TRUE, 33);
++		}
++	} else if (!wifi_connected && !wifi_scan) {
++		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
++	} else if (bt_link_info->pan_exist) {
++		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
++
++		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22);
++	} else if (bt_link_info->a2dp_exist) {
++		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
++
++		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16);
++	} else {
++		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
++
++		if (coex_sta->wifi_in_scan_task ||
++		    coex_sta->wifi_is_high_pri_task)
++			halbtc8723d1ant_ps_tdma(btcoexist,
++						NORMAL_EXEC, TRUE, 21);
++		else
++			halbtc8723d1ant_ps_tdma(btcoexist,
++						NORMAL_EXEC, TRUE, 23);
++	}
++}
++
++static
++void halbtc8723d1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
++		*btcoexist)
++{
++	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++	boolean	wifi_connected = FALSE, wifi_busy = FALSE, wifi_cckdeadlock_ap = FALSE;
++	u32  wifi_bw = 1;
++	u8	iot_peer = BTC_IOT_PEER_UNKNOWN;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++	btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
++
++	if ((iot_peer == BTC_IOT_PEER_ATHEROS) && (coex_sta->cck_lock_ever))
++		wifi_cckdeadlock_ap = TRUE;
++
++	if (bt_link_info->sco_exist) {
++		if (coex_sta->is_bt_multi_link) {
++			if (coex_sta->specific_pkt_period_cnt > 0)
++				halbtc8723d1ant_coex_table_with_type(btcoexist,
++								     FALSE,
++								     15);
++			else
++				halbtc8723d1ant_coex_table_with_type(btcoexist,
++								     FALSE,
++								     3);
++			halbtc8723d1ant_ps_tdma(btcoexist,
++						NORMAL_EXEC, TRUE, 25);
++		} else {
++			halbtc8723d1ant_coex_table_with_type(btcoexist,
++							     NORMAL_EXEC, 1);
++			halbtc8723d1ant_ps_tdma(btcoexist,
++						NORMAL_EXEC, TRUE, 5);
++		}
++	} else if (coex_sta->is_hid_rcu) {
++		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
++
++		if (wifi_busy)
++			halbtc8723d1ant_ps_tdma(btcoexist,
++						NORMAL_EXEC, TRUE, 36);
++		else
++			halbtc8723d1ant_ps_tdma(btcoexist,
++						NORMAL_EXEC, TRUE, 6);
++	} else {
++
++		if (wifi_cckdeadlock_ap &&
++		    coex_sta->is_hid_low_pri_tx_overhead) {
++			if (coex_sta->hid_busy_num < 2)
++				halbtc8723d1ant_coex_table_with_type(btcoexist,
++								     FALSE,
++								     14);
++			else
++				halbtc8723d1ant_coex_table_with_type(btcoexist,
++								     FALSE,
++								     13);
++			halbtc8723d1ant_ps_tdma(btcoexist,
++						NORMAL_EXEC, TRUE, 18);
++		} else if (coex_sta->is_hid_low_pri_tx_overhead) {
++			if (coex_sta->hid_busy_num < 2)
++				halbtc8723d1ant_coex_table_with_type(btcoexist,
++								     FALSE,
++								     3);
++			else
++				halbtc8723d1ant_coex_table_with_type(btcoexist,
++								     FALSE,
++								     6);
++			halbtc8723d1ant_ps_tdma(btcoexist,
++						NORMAL_EXEC, TRUE, 18);
++		} else if (coex_sta->hid_busy_num < 2) {
++			halbtc8723d1ant_coex_table_with_type(btcoexist,
++							     NORMAL_EXEC, 3);
++			halbtc8723d1ant_ps_tdma(btcoexist,
++						NORMAL_EXEC, TRUE, 11);
++		} else if (wifi_bw == 0) { /* if 11bg mode */
++			halbtc8723d1ant_coex_table_with_type(btcoexist,
++							     NORMAL_EXEC, 11);
++			halbtc8723d1ant_ps_tdma(btcoexist,
++						NORMAL_EXEC, TRUE, 11);
++		} else {
++			halbtc8723d1ant_coex_table_with_type(btcoexist,
++							     NORMAL_EXEC, 6);
++			halbtc8723d1ant_ps_tdma(btcoexist,
++						NORMAL_EXEC, TRUE, 11);
++		}
++	}
++}
++
++static
++void halbtc8723d1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
++{
++	halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
++				     BT_8723D_1ANT_PHASE_2G_RUNTIME);
++	halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 10);
++	halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8);
++}
++
++static
++void halbtc8723d1ant_action_wifi_native_lps(IN struct btc_coexist *btcoexist)
++{
++	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++
++	if (bt_link_info->pan_exist)
++		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
++	else
++		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++	halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
++}
++
++static
++void halbtc8723d1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
++{
++	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++	struct btc_wifi_link_info *link_info = &btcoexist->wifi_link_info;
++	u8 multi_port_type;
++	u32 traffic_dir, wifi_link_status;
++	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
++
++	halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
++				     BT_8723D_1ANT_PHASE_2G_RUNTIME);
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
++			   &traffic_dir);
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
++			   &wifi_link_status);
++
++	if (coex_sta->bt_disabled) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], %s(): BT Disable!!\n", __func__);
++		BTC_TRACE(trace_buf);
++		
++		halbtc8723d1ant_coex_table_with_type(btcoexist, FALSE, 10);
++		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
++	} else if (coex_sta->is_setup_link) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], %s(): BT Relink!!\n", __func__);
++		BTC_TRACE(trace_buf);
++		
++		halbtc8723d1ant_coex_table_with_type(btcoexist, FALSE, 0);
++		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
++	} else if (coex_sta->c2h_bt_inquiry_page) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], %s(): BT Inq-Page!!\n", __func__);
++		BTC_TRACE(trace_buf);
++		
++		halbtc8723d1ant_coex_table_with_type(btcoexist, FALSE, 18);
++		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 5);
++	 } else if (coex_sta->num_of_profile == 0) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], %s(): BT idle!!\n", __func__);
++		BTC_TRACE(trace_buf);
++		
++		if (btcoexist->chip_interface == BTC_INTF_PCI &&
++			(link_info->link_mode == BTC_LINK_ONLY_GO ||
++			 link_info->link_mode == BTC_LINK_ONLY_GC))
++			halbtc8723d1ant_coex_table_with_type(btcoexist, FALSE,
++							     10);
++		else
++			halbtc8723d1ant_coex_table_with_type(btcoexist, FALSE,
++							     17);
++		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
++	} else {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], %s(): BT busy!!\n", __func__);
++		BTC_TRACE(trace_buf);
++
++		switch (link_info->link_mode) {
++		case BTC_LINK_ONLY_GO:
++		case BTC_LINK_ONLY_GC:
++			if (btcoexist->chip_interface == BTC_INTF_PCI &&
++			    bt_link_info->a2dp_exist && !coex_sta->is_bt_multi_link)
++				halbtc8723d1ant_coex_table_with_type(btcoexist,
++								FALSE, 10);
++			else
++				halbtc8723d1ant_coex_table_with_type(btcoexist,
++								FALSE, 17);
++
++			halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
++			break;
++		default:
++			halbtc8723d1ant_coex_table_with_type(btcoexist, FALSE, 17);
++			halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
++			break;
++		}
++	}
++}
++
++static
++void halbtc8723d1ant_action_wifi_linkscan_process(IN struct btc_coexist
++		*btcoexist)
++{
++	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++
++	halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
++
++	if (bt_link_info->pan_exist)
++		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22);
++	else if (bt_link_info->a2dp_exist)
++		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 27);
++	else
++		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21);
++}
++
++static
++void halbtc8723d1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist
++		*btcoexist)
++{
++	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++	boolean wifi_busy = FALSE, wifi_turbo = FALSE, wifi_cckdeadlock_ap = FALSE;
++	u32	wifi_bw = 1;
++	u8	iot_peer = BTC_IOT_PEER_UNKNOWN, table_case, tdma_case;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
++			   &coex_sta->scan_ap_num);
++	btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
++	
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "############# [BTCoex],  scan_ap_num = %d, wl_noisy_level = %d\n",
++		    coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
++	BTC_TRACE(trace_buf);
++
++	if (wifi_busy && coex_sta->wl_noisy_level == 0)
++		wifi_turbo = TRUE;
++
++	if (coex_sta->cck_lock_ever)
++		wifi_cckdeadlock_ap = TRUE;
++
++	if (bt_link_info->a2dp_exist && coex_sta->is_bt_a2dp_sink) {
++		if (wifi_cckdeadlock_ap) {
++			table_case = 13;
++			tdma_case = 15;
++		}
++		else if(wifi_busy) {
++			table_case = 3;
++			tdma_case = 15;
++		}
++		else {
++			table_case = 3;
++			tdma_case = 58;
++		}
++		halbtc8723d1ant_coex_table_with_type(btcoexist,
++						     NORMAL_EXEC, table_case);
++		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, tdma_case);	
++	} else if (bt_link_info->a2dp_only) { /* A2DP		 */
++
++		if (wifi_cckdeadlock_ap)
++			table_case = 13;
++		else if (wifi_turbo)
++			table_case = 8;
++		else
++			table_case = 4;
++
++		halbtc8723d1ant_coex_table_with_type(btcoexist,
++						     NORMAL_EXEC, table_case);
++
++		if (coex_sta->connect_ap_period_cnt > 0)
++			halbtc8723d1ant_ps_tdma(btcoexist,
++						NORMAL_EXEC, TRUE, 26);
++		else
++			halbtc8723d1ant_ps_tdma(btcoexist,
++						NORMAL_EXEC, TRUE, 7);
++
++	} else if ((bt_link_info->a2dp_exist &&
++			bt_link_info->pan_exist) ||
++			(bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
++			bt_link_info->pan_exist)) {
++		/* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
++		if (wifi_cckdeadlock_ap) {
++			if (bt_link_info->hid_exist &&
++			    coex_sta->hid_busy_num < 2)
++				table_case = 14;
++			else
++				table_case = 13;
++		} else if (bt_link_info->hid_exist) {
++			if (coex_sta->hid_busy_num < 2)
++				table_case = 3;
++			else
++				table_case = 1;
++		} else if (wifi_turbo) {
++			table_case = 8;
++		} else {
++			table_case = 4;
++		}
++
++		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
++						     table_case);
++		if (wifi_busy)
++			halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE,
++						13);
++		else
++			halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE,
++						14);
++	} else if (bt_link_info->hid_exist &&
++		   bt_link_info->a2dp_exist) { /* HID+A2DP */
++
++		if (wifi_cckdeadlock_ap) {
++			if (coex_sta->hid_busy_num < 2)
++				table_case = 14;
++			else
++				table_case = 13;
++
++			halbtc8723d1ant_coex_table_with_type(btcoexist,
++							     NORMAL_EXEC,
++							     table_case);
++
++			if (coex_sta->hid_pair_cnt > 1)
++				halbtc8723d1ant_ps_tdma(btcoexist,
++							NORMAL_EXEC, TRUE, 24);
++			else
++				halbtc8723d1ant_ps_tdma(btcoexist,
++							NORMAL_EXEC, TRUE, 8);
++		} else {
++			if (coex_sta->hid_busy_num < 2) /* 2/18 HID */
++				table_case = 3;
++			else if (wifi_bw == 0)/* if 11bg mode */
++				table_case = 12;
++			else
++				table_case = 1;
++
++			halbtc8723d1ant_coex_table_with_type(btcoexist,
++							     NORMAL_EXEC,
++							     table_case);
++
++			if (coex_sta->hid_pair_cnt > 1)
++				halbtc8723d1ant_ps_tdma(btcoexist,
++							NORMAL_EXEC, TRUE, 24);
++			else
++				halbtc8723d1ant_ps_tdma(btcoexist,
++							NORMAL_EXEC, TRUE, 8);
++		}
++	} else if (bt_link_info->pan_only
++		   || (bt_link_info->hid_exist && bt_link_info->pan_exist)) {
++			/* PAN(OPP,FTP), HID+PAN(OPP,FTP) */
++
++		if (coex_sta->cck_lock_ever) {
++			if (bt_link_info->hid_exist &&
++			    coex_sta->hid_busy_num < 2)
++				table_case = 14;
++			else
++				table_case = 13;
++		} else if (bt_link_info->hid_exist) {
++			if (coex_sta->hid_busy_num < 2)
++				table_case = 3;
++			else
++				table_case = 1;
++		} else if (wifi_turbo) {
++			table_case = 8;
++		} else {
++			table_case = 4;
++		}
++
++		halbtc8723d1ant_coex_table_with_type(btcoexist,
++						     NORMAL_EXEC, table_case);
++		if (!wifi_busy)
++			halbtc8723d1ant_ps_tdma(btcoexist,
++						NORMAL_EXEC, TRUE, 4);
++		else
++			halbtc8723d1ant_ps_tdma(btcoexist,
++						NORMAL_EXEC, TRUE, 3);
++	} else {
++		/* BT no-profile busy (0x9) */
++		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
++		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33);
++	}
++
++}
++
++static
++void halbtc8723d1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
++{
++	halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
++				     BT_8723D_1ANT_PHASE_2G_RUNTIME);
++	/* tdma and coex table */
++	halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++	halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8);
++}
++
++static
++void halbtc8723d1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
++{
++	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++	boolean wifi_busy = FALSE;
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], CoexForWifiConnect()===>\n");
++	BTC_TRACE(trace_buf);
++
++	halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
++					 NORMAL_EXEC,
++					 BT_8723D_1ANT_PHASE_2G_RUNTIME);
++
++	if ((coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_ACL_BUSY) ||
++		(coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY)) {
++
++		if (bt_link_info->hid_only)  /* HID only */
++		   halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist);
++		else
++			halbtc8723d1ant_action_wifi_connected_bt_acl_busy(btcoexist);
++
++	} else if (coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_SCO_BUSY)
++		halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist);
++	else
++		halbtc8723d1ant_action_bt_idle(btcoexist);
++}
++
++static
++void halbtc8723d1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist)
++{
++	u8				algorithm = 0;
++
++	algorithm = halbtc8723d1ant_action_algorithm(btcoexist);
++	coex_dm->cur_algorithm = algorithm;
++
++	if (halbtc8723d1ant_is_common_action(btcoexist)) {
++
++	} else {
++		switch (coex_dm->cur_algorithm) {
++		case BT_8723D_1ANT_COEX_ALGO_SCO:
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], Action algorithm = SCO.\n");
++			BTC_TRACE(trace_buf);
++			break;
++		case BT_8723D_1ANT_COEX_ALGO_HID:
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], Action algorithm = HID.\n");
++			BTC_TRACE(trace_buf);
++			break;
++		case BT_8723D_1ANT_COEX_ALGO_A2DP:
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], Action algorithm = A2DP.\n");
++			BTC_TRACE(trace_buf);
++			break;
++		case BT_8723D_1ANT_COEX_ALGO_A2DP_PANHS:
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], Action algorithm = A2DP+PAN(HS).\n");
++			BTC_TRACE(trace_buf);
++			break;
++		case BT_8723D_1ANT_COEX_ALGO_PANEDR:
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], Action algorithm = PAN(EDR).\n");
++			BTC_TRACE(trace_buf);
++			break;
++		case BT_8723D_1ANT_COEX_ALGO_PANHS:
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], Action algorithm = HS mode.\n");
++			BTC_TRACE(trace_buf);
++			break;
++		case BT_8723D_1ANT_COEX_ALGO_PANEDR_A2DP:
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], Action algorithm = PAN+A2DP.\n");
++			BTC_TRACE(trace_buf);
++			break;
++		case BT_8723D_1ANT_COEX_ALGO_PANEDR_HID:
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], Action algorithm = PAN(EDR)+HID.\n");
++			BTC_TRACE(trace_buf);
++			break;
++		case BT_8723D_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], Action algorithm = HID+A2DP+PAN.\n");
++			BTC_TRACE(trace_buf);
++			break;
++		case BT_8723D_1ANT_COEX_ALGO_HID_A2DP:
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], Action algorithm = HID+A2DP.\n");
++			BTC_TRACE(trace_buf);
++			break;
++		default:
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], Action algorithm = coexist All Off!!\n");
++			BTC_TRACE(trace_buf);
++			break;
++		}
++		coex_dm->pre_algorithm = coex_dm->cur_algorithm;
++	}
++}
++
++static
++void halbtc8723d1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
++{
++	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++	struct	btc_wifi_link_info linfo;
++	boolean wifi_connected = FALSE, bt_hs_on = FALSE;
++	boolean increase_scan_dev_num = FALSE;
++	boolean bt_ctrl_agg_buf_size = FALSE;
++	boolean miracast_plus_bt = FALSE, wifi_under_5g = FALSE;
++	u8	agg_buf_size = 5, iot_peer = BTC_IOT_PEER_UNKNOWN;
++	u32	wifi_link_status = 0, num_of_wifi_link = 0, wifi_bw;
++	boolean scan = FALSE, link = FALSE, roam = FALSE, under_4way = FALSE;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
++			   &under_4way);
++	btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
++				   &increase_scan_dev_num);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK_INFO, &linfo);
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
++				   &wifi_link_status);
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
++			   &wifi_connected);
++	num_of_wifi_link = wifi_link_status >> 16;
++	btcoexist->wifi_link_info = linfo;
++	
++	/* coex-276  P2P-Go beacon request can't release issue
++	* Only PCIe can set 0x454[6] = 1 to solve this issue,
++	* WL SDIO/USB interface need driver support.
++	*/
++#ifdef PLATFORM_WINDOWS
++	if (btcoexist->chip_interface != BTC_INTF_SDIO)
++#else
++	if (btcoexist->chip_interface == BTC_INTF_PCI)
++#endif
++		btcoexist->btc_write_1byte_bitmask(btcoexist, REG_CCK_CHECK,
++					     BIT_EN_BCN_PKT_REL, 0x1);
++	else
++		btcoexist->btc_write_1byte_bitmask(btcoexist, REG_CCK_CHECK,
++					     BIT_EN_BCN_PKT_REL, 0x0);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], RunCoexistMechanism()===>\n");
++	BTC_TRACE(trace_buf);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], under_lps = %d, force_lps_ctrl = %d, acl_busy = %d!!!\n",
++			coex_sta->under_lps, coex_sta->force_lps_ctrl, coex_sta->acl_busy);
++	BTC_TRACE(trace_buf);
++
++	if (btcoexist->manual_control) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
++		BTC_TRACE(trace_buf);
++		return;
++	}
++
++	if (btcoexist->stop_coex_dm) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
++		BTC_TRACE(trace_buf);
++		return;
++	}
++
++	if (coex_sta->under_ips) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], wifi is under IPS !!!\n");
++		BTC_TRACE(trace_buf);
++		return;
++	}
++
++	if (!coex_sta->run_time_state) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], return for run_time_state = FALSE !!!\n");
++		BTC_TRACE(trace_buf);
++		return;
++	}
++
++	if (coex_sta->freeze_coexrun_by_btinfo && !coex_sta->is_setup_link) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], return for freeze_coexrun_by_btinfo\n");
++		BTC_TRACE(trace_buf);
++		return;
++	}
++
++	if (coex_sta->under_lps && !coex_sta->force_lps_ctrl) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d1ant_action_wifi_native_lps(btcoexist);
++		return;
++	}
++
++	if (coex_sta->bt_whck_test) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], BT is under WHCK TEST!!!\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d1ant_action_bt_whql_test(btcoexist);
++		return;
++	}
++
++	if (coex_sta->bt_disabled) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], BT is disabled !!!\n");
++		halbtc8723d1ant_action_wifi_only(btcoexist);
++		return;
++	}
++
++	if (coex_sta->is_setup_link || coex_sta->bt_relink_downcount != 0) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], BT is re-link !!!\n");
++		halbtc8723d1ant_action_bt_relink(btcoexist);
++		return;
++	}
++
++	if (coex_sta->c2h_bt_inquiry_page) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], BT is under inquiry/page scan !!\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d1ant_action_bt_inquiry(btcoexist);
++		return;
++	}
++
++	if ((BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
++		(BT_8723D_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
++		(BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
++		increase_scan_dev_num = TRUE;
++
++	if ((num_of_wifi_link >= 2) || 
++		(wifi_link_status & WIFI_P2P_GO_CONNECTED) ||
++		(linfo.link_mode == BTC_LINK_ONLY_GO) ||
++		(linfo.link_mode == BTC_LINK_ONLY_GC) ) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"############# [BTCoex],  Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
++				num_of_wifi_link, wifi_link_status);
++		BTC_TRACE(trace_buf);
++
++		if (scan || link || roam || under_4way) {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n",
++				    scan, link, roam, under_4way);
++			BTC_TRACE(trace_buf);
++
++			if (bt_link_info->bt_link_exist)
++				miracast_plus_bt = TRUE;
++			else
++				miracast_plus_bt = FALSE;
++
++			btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
++				   &miracast_plus_bt);
++
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], wifi is under linkscan process + Multi-Port !!\n");
++			BTC_TRACE(trace_buf);
++
++			halbtc8723d1ant_action_wifi_linkscan_process(btcoexist);
++		} else
++
++			halbtc8723d1ant_action_wifi_multi_port(btcoexist);
++
++		return;
++	}
++
++#if 0
++	if ((bt_link_info->bt_link_exist) && (wifi_connected)) {
++
++		btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
++
++		if (BTC_IOT_PEER_CISCO == iot_peer) {
++
++			if (BTC_WIFI_BW_HT40 == wifi_bw)
++				halbtc8723d1ant_limited_rx(btcoexist,
++						NORMAL_EXEC, FALSE, TRUE, 0x10);
++			else
++				halbtc8723d1ant_limited_rx(btcoexist,
++						NORMAL_EXEC, FALSE, TRUE, 0x8);
++			}
++	}
++#endif
++	halbtc8723d1ant_run_sw_coexist_mechanism(
++			btcoexist);  /* just print debug message */
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
++
++	if (bt_hs_on) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"############# [BTCoex],  BT Is hs\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d1ant_action_bt_hs(btcoexist);
++		return;
++	}
++
++	if ((coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE ||
++	     coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE)
++	     && wifi_connected) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"############# [BTCoex],  BT Is idle\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d1ant_action_bt_idle(btcoexist);
++		return;
++	}
++
++	if (scan || link || roam || under_4way) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		   "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n",
++					scan, link, roam, under_4way);
++		BTC_TRACE(trace_buf);
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		   "[BTCoex], wifi is under linkscan process!!\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d1ant_action_wifi_linkscan_process(btcoexist);
++	} else if (wifi_connected) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		   "[BTCoex], wifi is under connected!!\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d1ant_action_wifi_connected(btcoexist);
++	} else {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		   "[BTCoex], wifi is under not-connected!!\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d1ant_action_wifi_not_connected(btcoexist);
++	 }
++}
++
++static
++void halbtc8723d1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
++{
++	/* force to reset coex mechanism */
++	halbtc8723d1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], Coex Mechanism Init!!\n");
++	BTC_TRACE(trace_buf);
++
++	coex_sta->pop_event_cnt = 0;
++	coex_sta->cnt_remotenamereq = 0;
++	coex_sta->cnt_reinit = 0;
++	coex_sta->cnt_setuplink = 0;
++	coex_sta->cnt_ignwlanact = 0;
++	coex_sta->cnt_page = 0;
++	coex_sta->cnt_roleswitch = 0;
++
++	halbtc8723d1ant_query_bt_info(btcoexist);
++}
++
++static
++void halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist,
++				    IN boolean back_up, IN boolean wifi_only)
++{
++	u32			u32tmp1 = 0, u32tmp2 = 0;
++	u16			u16tmp1 = 0;
++	u8	u8tmp0 = 0, u8tmp1 = 0;
++	struct  btc_board_info *board_info = &btcoexist->board_info;
++	u8 i = 0;
++	boolean tmp;
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], 1Ant Init HW Config!!\n");
++	BTC_TRACE(trace_buf);
++
++#if BT_8723D_1ANT_COEX_DBG
++	u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
++			0x38);
++	u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
++			0x54);
++	u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948);
++	u8tmp1	= btcoexist->btc_read_1byte(btcoexist, 0x73);
++	u8tmp0 =  btcoexist->btc_read_1byte(btcoexist, 0x67);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(Before init_hw_config)\n",
++		    u8tmp0, u16tmp1, u8tmp1);
++	BTC_TRACE(trace_buf);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], **********0x38= 0x%x, 0x54= 0x%x (Before init_hw_config)\n",
++		    u32tmp1, u32tmp2);
++	BTC_TRACE(trace_buf);
++#endif
++
++	coex_sta->bt_coex_supported_feature = 0;
++	coex_sta->bt_coex_supported_version = 0;
++	coex_sta->bt_ble_scan_type = 0;
++	coex_sta->bt_ble_scan_para[0] = 0;
++	coex_sta->bt_ble_scan_para[1] = 0;
++	coex_sta->bt_ble_scan_para[2] = 0;
++	coex_sta->bt_reg_vendor_ac = 0xffff;
++	coex_sta->bt_reg_vendor_ae = 0xffff;
++	coex_sta->isolation_btween_wb = BT_8723D_1ANT_DEFAULT_ISOLATION;
++	coex_sta->gnt_error_cnt = 0;
++	coex_sta->bt_relink_downcount = 0;
++	coex_sta->wl_rx_rate = BTC_UNKNOWN;
++
++	for (i = 0; i <= 9; i++)
++		coex_sta->bt_afh_map[i] = 0;
++
++	/* 0xf0[15:12] --> kt_ver */
++	coex_sta->kt_ver = (btcoexist->btc_read_1byte(btcoexist,
++						      0xf1) & 0xf0) >> 4;
++
++	if (coex_sta->kt_ver >= 0x3)
++		tmp =  TRUE;
++	else
++		tmp =  FALSE;
++
++	halbtc8723d1ant_post_state_to_bt(btcoexist,
++					 BT_8723D_1ANT_SCOREBOARD_DKTOPP2M,
++					 tmp);
++	/* enable TBTT nterrupt */
++	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, 0x1);
++
++	/* BT report packet sample rate	 */
++	btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5);
++
++	/* Init 0x778 = 0x1 for 1-Ant */
++	btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
++
++	/* Enable PTA (3-wire function form BT side) */
++	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
++	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1);
++
++	/* Enable PTA (tx/rx signal form WiFi side) */
++	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1);
++
++	halbtc8723d1ant_enable_gnt_to_gpio(btcoexist, TRUE);
++
++	/* PTA parameter */
++	halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
++
++	halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8);
++
++	psd_scan->ant_det_is_ant_det_available = TRUE;
++
++	/* Antenna config */
++	if (coex_sta->is_rf_state_off) {
++
++		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
++					     FORCE_EXEC,
++					     BT_8723D_1ANT_PHASE_WLAN_OFF);
++
++		btcoexist->stop_coex_dm = TRUE;
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], **********  halbtc8723d1ant_init_hw_config (RF Off)**********\n");
++		BTC_TRACE(trace_buf);
++	} else if (wifi_only) {
++		coex_sta->concurrent_rx_mode_on = FALSE;
++		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI,
++					     FORCE_EXEC,
++					     BT_8723D_1ANT_PHASE_WLANONLY_INIT);
++
++		btcoexist->stop_coex_dm = TRUE;
++	} else {
++		coex_sta->concurrent_rx_mode_on = TRUE;
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1);
++		/* RF 0x1[0] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx */
++		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x1, 0x0);
++		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
++					     FORCE_EXEC,
++					     BT_8723D_1ANT_PHASE_COEX_INIT);
++
++		btcoexist->stop_coex_dm = FALSE;
++	}
++
++	if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], **********  Single Antenna, Antenna at Main Port: S1**********\n");
++		BTC_TRACE(trace_buf);
++	} else {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], **********  Single Antenna, Antenna at Aux Port: S0**********\n");
++		BTC_TRACE(trace_buf);
++	}
++
++}
++
++#ifdef PLATFORM_WINDOWS
++#pragma optimize("", off)
++#endif
++
++/* ************************************************************
++ * work around function start with wa_halbtc8723d1ant_
++ * ************************************************************
++ * ************************************************************
++ * extern function start with ex_halbtc8723d1ant_
++ * ************************************************************ */
++void ex_halbtc8723d1ant_power_on_setting(IN struct btc_coexist *btcoexist)
++{
++	struct  btc_board_info	*board_info = &btcoexist->board_info;
++	u8 u8tmp = 0x0;
++	u16 u16tmp = 0x0;
++	u32	value = 0;
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"xxxxxxxxxxxxxxxx Execute 8723d 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n");
++	BTC_TRACE(trace_buf);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "Ant Det Finish = %s, Ant Det Number  = %d\n",
++		    (board_info->btdm_ant_det_finish ? "Yes" : "No"),
++		    board_info->btdm_ant_num_by_ant_det);
++	BTC_TRACE(trace_buf);
++
++	btcoexist->stop_coex_dm = TRUE;
++	coex_sta->is_rf_state_off = FALSE;
++	psd_scan->ant_det_is_ant_det_available = FALSE;
++
++	/* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */
++	u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
++	btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
++
++	/* Local setting bit define */
++	/*	BIT0: "0" for no antenna inverse; "1" for antenna inverse  */
++	/*	BIT1: "0" for internal switch; "1" for external switch */
++	/*	BIT2: "0" for one antenna; "1" for two antenna */
++	/* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
++
++	/* Set Antenna Path to BT side */
++	/* Check efuse 0xc3[6] for Single Antenna Path */
++	if (board_info->single_ant_path == 0) {
++		/* set to S1 */
++		board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
++		u8tmp = 0;
++		value = 1;
++	} else if (board_info->single_ant_path == 1) {
++		/* set to S0 */
++		board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
++		u8tmp = 1;
++		value = 0;
++	}
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], ********** (Power On) single_ant_path  = %d, btdm_ant_pos = %d **********\n",
++		    board_info->single_ant_path , board_info->btdm_ant_pos);
++	BTC_TRACE(trace_buf);
++
++	/* Set Antenna Path to BT side */
++	halbtc8723d1ant_set_ant_path(btcoexist,
++				     BTC_ANT_PATH_AUTO,
++				     FORCE_EXEC,
++				     BT_8723D_1ANT_PHASE_COEX_POWERON);
++
++	/* Write Single Antenna Position to Registry to tell BT for 8723d. This line can be removed
++	since BT EFuse also add "single antenna position" in EFuse for 8723d*/
++	btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL,
++			   &value);
++
++	/* Save"single antenna position" info in Local register setting for FW reading, because FW may not ready at  power on */
++	if (btcoexist->chip_interface == BTC_INTF_PCI)
++		btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp);
++	else if (btcoexist->chip_interface == BTC_INTF_USB)
++		btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
++	else if (btcoexist->chip_interface == BTC_INTF_SDIO)
++		btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp);
++
++	/* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
++	halbtc8723d1ant_enable_gnt_to_gpio(btcoexist, TRUE);
++
++#if BT_8723D_1ANT_COEX_DBG
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], **********  LTE coex Reg 0x38 (Power-On) = 0x%x**********\n",
++		    halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38));
++	BTC_TRACE(trace_buf);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], **********  MAC Reg 0x70/ BB Reg 0x948 (Power-On) = 0x%x / 0x%x**********\n",
++		    btcoexist->btc_read_4byte(btcoexist, 0x70),
++		    btcoexist->btc_read_2byte(btcoexist, 0x948));
++	BTC_TRACE(trace_buf);
++
++#endif
++
++}
++
++void ex_halbtc8723d1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
++{
++}
++
++void ex_halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist,
++				       IN boolean wifi_only)
++{
++	halbtc8723d1ant_init_hw_config(btcoexist, TRUE, wifi_only);
++}
++
++void ex_halbtc8723d1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
++{
++	halbtc8723d1ant_init_coex_dm(btcoexist);
++}
++
++void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist)
++{
++	struct  btc_board_info		*board_info = &btcoexist->board_info;
++	struct  btc_stack_info		*stack_info = &btcoexist->stack_info;
++	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
++	u8				*cli_buf = btcoexist->cli_buf;
++	u8				u8tmp[4], i, ps_tdma_case = 0;
++	u16				u16tmp[4];
++	u32				u32tmp[4];
++	u32				fa_ofdm, fa_cck, cca_ofdm, cca_cck;
++	u32				fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0;
++	static u8			pop_report_in_10s = 0, cnt = 0;
++	u32			phyver = 0;
++	boolean			lte_coex_on = FALSE;
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n ============[BT Coexist info 8723D]============");
++	CL_PRINTF(cli_buf);
++
++	if (btcoexist->manual_control) {
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			"\r\n ============[Under Manual Control]============");
++		CL_PRINTF(cli_buf);
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n ==========================================");
++		CL_PRINTF(cli_buf);
++	}
++	if (btcoexist->stop_coex_dm) {
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n ============[Coex is STOPPED]============");
++		CL_PRINTF(cli_buf);
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n ==========================================");
++		CL_PRINTF(cli_buf);
++	}
++
++	if (!coex_sta->bt_disabled) {
++		if (coex_sta->bt_coex_supported_feature == 0) {
++			btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE,
++						&coex_sta->bt_coex_supported_feature);
++
++			if (coex_sta->bt_coex_supported_feature & BIT(13))
++				coex_sta->is_bt_mesh_ver = TRUE;
++		}
++		
++		if ((coex_sta->bt_coex_supported_version == 0) ||
++			 (coex_sta->bt_coex_supported_version == 0xffff))
++			btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION,
++						&coex_sta->bt_coex_supported_version);
++
++		if (coex_sta->bt_reg_vendor_ac == 0xffff)
++			coex_sta->bt_reg_vendor_ac = (u16)(
++						btcoexist->btc_get_bt_reg(btcoexist, 3,
++						0xac) & 0xffff);
++
++		if (coex_sta->bt_reg_vendor_ae == 0xffff)
++			coex_sta->bt_reg_vendor_ae = (u16)(
++						btcoexist->btc_get_bt_reg(btcoexist, 3,
++						0xae) & 0xffff);
++
++		btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
++						&bt_patch_ver);
++		btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
++
++		if (coex_sta->num_of_profile > 0) {
++			cnt++;
++
++			if (cnt >= 3) {
++				btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0,
++					&coex_sta->bt_afh_map[0]);
++				cnt = 0;
++			}
++		}
++	}
++
++	if (psd_scan->ant_det_try_count == 0) {
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s/ %s",
++			   "Ant PG Num/ Mech/ Pos",
++			   board_info->pg_ant_num,
++			   (board_info->btdm_ant_num == 1 ?
++			   "Shared" : "Non-Shared"),
++			   (board_info->btdm_ant_pos == 1 ?
++			   "S1" : "S0"));
++		CL_PRINTF(cli_buf);
++	} else {
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n %-35s = %d/ %d/ %s  (%d/%d/%d)",
++			   "Ant PG Num/ Mech(Ant_Det)/ Pos",
++			   board_info->pg_ant_num,
++			   board_info->btdm_ant_num_by_ant_det,
++			   (board_info->btdm_ant_pos == 1 ? "S1" : "S0"),
++			   psd_scan->ant_det_try_count,
++			   psd_scan->ant_det_fail_count,
++			   psd_scan->ant_det_result);
++		CL_PRINTF(cli_buf);
++
++		if (board_info->btdm_ant_det_finish) {
++
++			if (psd_scan->ant_det_result != 12)
++				CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++					   "\r\n %-35s = %s",
++					   "Ant Det PSD Value",
++					   psd_scan->ant_det_peak_val);
++			else
++				CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++					   "\r\n %-35s = %d",
++					   "Ant Det PSD Value",
++					   psd_scan->ant_det_psd_scan_peak_val
++					   / 100);
++			CL_PRINTF(cli_buf);
++		}
++	}
++
++	if (board_info->ant_det_result_five_complete) {
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n %-35s = %d/ %d",
++			   "AntDet(Registry) Num/PSD Value",
++			   board_info->btdm_ant_num_by_ant_det,
++			   (board_info->antdetval & 0x7f));
++		CL_PRINTF(cli_buf);
++	}
++
++	bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
++	phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
++
++	bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++				"\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
++				"CoexVer WL/  BT_Desired/ BT_Report",
++				glcoex_ver_date_8723d_1ant, glcoex_ver_8723d_1ant,
++				glcoex_ver_btdesired_8723d_1ant,
++				bt_coex_ver,
++				(bt_coex_ver == 0xff ? "Unknown" :
++				(coex_sta->bt_disabled ? "BT-disable" :
++				(bt_coex_ver >= glcoex_ver_btdesired_8723d_1ant ?
++				"Match" : "Mis-Match"))));
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c",
++		   "W_FW/ B_FW/ Phy/ Kt",
++		   fw_ver, bt_patch_ver, phyver,
++		   coex_sta->kt_ver + 65);
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
++		   "Wifi channel informed to BT",
++		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
++		   coex_dm->wifi_chnl_info[2]);
++	CL_PRINTF(cli_buf);
++
++	/* wifi status */
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
++		   "============[Wifi Status]============");
++	CL_PRINTF(cli_buf);
++	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
++		   "============[BT Status]============");
++	CL_PRINTF(cli_buf);
++
++	pop_report_in_10s++;
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = %s/ %ddBm/ %d/ %d",
++		   "BT status/ rssi/ retryCnt/ popCnt",
++		   ((coex_sta->bt_disabled) ? ("disabled") :	((
++			   coex_sta->c2h_bt_inquiry_page) ? ("inquiry-page")
++			   : ((BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
++			       coex_dm->bt_status) ? "non-connected-idle" :
++		((BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
++				       ? "connected-idle" : "busy")))),
++		   coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
++		   coex_sta->pop_event_cnt);
++	CL_PRINTF(cli_buf);
++
++	if (pop_report_in_10s >= 5) {
++		coex_sta->pop_event_cnt = 0;
++		pop_report_in_10s = 0;
++	}
++
++	if (coex_sta->num_of_profile != 0)
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++				"\r\n %-35s = %s%s%s%s%s (multilink = %d)",
++				"Profiles",
++				((bt_link_info->a2dp_exist) ?
++				((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," :
++				"A2DP,") : ""),
++				((bt_link_info->sco_exist) ?  "HFP," : ""),
++				((bt_link_info->hid_exist) ?
++				((coex_sta->is_hid_rcu) ? "HID(RCU)" :
++				((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," :
++				"HID(2/18),")) : ""),
++				((bt_link_info->pan_exist) ?
++				((coex_sta->is_bt_opp_exist) ? "OPP," : "PAN,") : ""),
++				((coex_sta->voice_over_HOGP) ? "Voice" : ""),
++				coex_sta->is_bt_multi_link);
++	else
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n %-35s = None", "Profiles");
++
++	CL_PRINTF(cli_buf);
++
++	if (bt_link_info->a2dp_exist) {
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n %-35s = %s/ %d/ 0x%x/ 0x%x",
++			   "CQDDR/Bitpool/V_ID/D_name",
++			   ((coex_sta->is_A2DP_3M) ? "On" : "Off"),
++			   coex_sta->a2dp_bit_pool,
++			   coex_sta->bt_a2dp_vendor_id,
++			   coex_sta->bt_a2dp_device_name);
++		CL_PRINTF(cli_buf);
++	}
++
++	if (bt_link_info->hid_exist) {
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
++			   "HID PairNum/Forbid_Slot",
++			   coex_sta->hid_pair_cnt
++			  );
++		CL_PRINTF(cli_buf);
++	}
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x",
++				"Role/RoleSwCnt/IgnWlact/Feature",
++				((bt_link_info->slave_role) ? "Slave" : "Master"),
++				coex_sta->cnt_roleswitch,
++				((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"),
++				coex_sta->bt_coex_supported_feature);
++	CL_PRINTF(cli_buf);
++
++	if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) {
++			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++				"\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
++				"BLEScan Type/TV/Init/Ble",
++				coex_sta->bt_ble_scan_type,
++				(coex_sta->bt_ble_scan_type & 0x1 ?
++				coex_sta->bt_ble_scan_para[0] : 0x0),
++				(coex_sta->bt_ble_scan_type & 0x2 ?
++				coex_sta->bt_ble_scan_para[1] : 0x0),
++				(coex_sta->bt_ble_scan_type & 0x4 ?
++				coex_sta->bt_ble_scan_para[2] : 0x0));
++			CL_PRINTF(cli_buf);
++	}
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d",
++		   "ReInit/ReLink/IgnWlact/Page/NameReq",
++		   coex_sta->cnt_reinit,
++		   coex_sta->cnt_setuplink,
++		   coex_sta->cnt_ignwlanact,
++		   coex_sta->cnt_page,
++		   coex_sta->cnt_remotenamereq
++		  );
++	CL_PRINTF(cli_buf);
++
++	halbtc8723d1ant_read_score_board(btcoexist,	&u16tmp[0]);
++
++	if ((coex_sta->bt_reg_vendor_ae == 0xffff) ||
++	    (coex_sta->bt_reg_vendor_ac == 0xffff))
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ 0x%04x",
++			   "0xae[4]/0xac[1:0]/Scoreboard(B->W)", u16tmp[0]);
++	else
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x",
++			   "0xae[4]/0xac[1:0]/Scoreboard(B->W)",
++			   (int)((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4),
++			   coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]);
++	CL_PRINTF(cli_buf);
++
++	if (coex_sta->num_of_profile > 0) {
++
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			"\r\n %-35s = %02x%02x%02x%02x %02x%02x%02x%02x %02x %02x",
++			"AFH MAP",
++			coex_sta->bt_afh_map[0],
++			coex_sta->bt_afh_map[1],
++			coex_sta->bt_afh_map[2],
++			coex_sta->bt_afh_map[3],
++			coex_sta->bt_afh_map[4],
++			coex_sta->bt_afh_map[5],
++			coex_sta->bt_afh_map[6],
++			coex_sta->bt_afh_map[7],
++			coex_sta->bt_afh_map[8],
++			coex_sta->bt_afh_map[9]
++			   );
++		CL_PRINTF(cli_buf);
++	}
++
++	for (i = 0; i < BT_INFO_SRC_8723D_1ANT_MAX; i++) {
++		if (coex_sta->bt_info_c2h_cnt[i]) {
++			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++				"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x (%d)",
++				   glbt_info_src_8723d_1ant[i],
++				   coex_sta->bt_info_c2h[i][0],
++				   coex_sta->bt_info_c2h[i][1],
++				   coex_sta->bt_info_c2h[i][2],
++				   coex_sta->bt_info_c2h[i][3],
++				   coex_sta->bt_info_c2h[i][4],
++				   coex_sta->bt_info_c2h[i][5],
++				   coex_sta->bt_info_c2h[i][6],
++				   coex_sta->bt_info_c2h_cnt[i]);
++			CL_PRINTF(cli_buf);
++		}
++	}
++
++
++	if (btcoexist->manual_control)
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
++			"============[mechanisms] (before Manual)============");
++	else
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
++			   "============[Mechanisms]============");
++
++	CL_PRINTF(cli_buf);
++
++	ps_tdma_case = coex_dm->cur_ps_tdma;
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s, Timer:%d)",
++		   "TDMA",
++		   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
++		   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
++		   coex_dm->ps_tdma_para[4], ps_tdma_case,
++		   (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off"),
++		   coex_sta->tdma_timer_base);
++
++	CL_PRINTF(cli_buf);
++
++	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
++	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
++	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x",
++		   "Table/0x6c0/0x6c4/0x6c8",
++		   coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]);
++	CL_PRINTF(cli_buf);
++
++	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
++	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x",
++		   "0x778/0x6cc/Scoreboard(W->B)",
++		   u8tmp[0], u32tmp[0], coex_sta->score_board_WB);
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s",
++		   "AntDiv/ ForceLPS",
++		   ((board_info->ant_div_cfg) ? "On" : "Off"),
++		   ((coex_sta->force_lps_ctrl) ? "On" : "Off"));
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
++		   "BT_Empty/BT_Late",
++		   coex_sta->wl_fw_dbg_info[4],
++		   coex_sta->wl_fw_dbg_info[5]);
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s",
++		   "TDMA_Togg_cnt/WL5ms_cnt/WL5ms_off",
++		   coex_sta->wl_fw_dbg_info[6], coex_sta->wl_fw_dbg_info[7],
++		   ((coex_sta->is_no_wl_5ms_extend) ? "Yes" : "No"));
++	CL_PRINTF(cli_buf);
++
++	u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
++	lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ?  TRUE : FALSE;
++
++	if (lte_coex_on) {
++
++		u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
++				0xa0);
++		u32tmp[1] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
++				0xa4);
++
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
++			   "LTE Coex  Table W_L/B_L",
++			   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff);
++		CL_PRINTF(cli_buf);
++
++		u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
++				0xa8);
++		u32tmp[1] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
++				0xac);
++		u32tmp[2] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
++				0xb0);
++		u32tmp[3] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
++				0xb4);
++
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
++			   "LTE Break Table W_L/B_L/L_W/L_B",
++			   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
++			   u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
++		CL_PRINTF(cli_buf);
++
++	}
++
++	/* Hw setting		 */
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
++		   "============[Hw setting]============");
++	CL_PRINTF(cli_buf);
++
++	u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
++	u32tmp[1] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
++	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s",
++		   "LTE Coex/Path Owner",
++		   ((lte_coex_on) ? "On" : "Off") ,
++		   ((u8tmp[0] & BIT(2)) ? "WL" : "BT"));
++	CL_PRINTF(cli_buf);
++
++	if (lte_coex_on) {
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n %-35s = %d/ %d/ %d/ %d",
++			   "LTE 3Wire/OPMode/UART/UARTMode",
++			   (int)((u32tmp[0] & BIT(6)) >> 6),
++			   (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
++			   (int)((u32tmp[0] & BIT(3)) >> 3),
++			   (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
++		CL_PRINTF(cli_buf);
++
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
++			   "LTE_Busy/UART_Busy",
++			(int)((u32tmp[1] & BIT(1)) >> 1), (int)(u32tmp[1] & BIT(0)));
++		CL_PRINTF(cli_buf);
++	}
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s (gnt_err = %d)",
++			   "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg",
++			   ((u32tmp[0] & BIT(12)) ? "SW" : "HW"),
++			   ((u32tmp[0] & BIT(8)) ?	"SW" : "HW"),
++			   ((u32tmp[0] & BIT(14)) ? "SW" : "HW"),
++			   ((u32tmp[0] & BIT(10)) ?  "SW" : "HW"),
++			   ((u8tmp[0] & BIT(3)) ? "On" : "Off"),
++			   coex_sta->gnt_error_cnt);
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
++		   "GNT_WL/GNT_BT",
++		   (int)((u32tmp[1] & BIT(2)) >> 2),
++		   (int)((u32tmp[1] & BIT(3)) >> 3));
++	CL_PRINTF(cli_buf);
++
++	u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x948);
++	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
++		   "0x948/0x67[7]",
++		   u16tmp[0], (int)((u8tmp[0] & BIT(7)) >> 7));
++	CL_PRINTF(cli_buf);
++
++	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x964);
++	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x864);
++	u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xab7);
++	u8tmp[3] = btcoexist->btc_read_1byte(btcoexist, 0xa01);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
++		   "0x964[1]/0x864[0]/0xab7[5]/0xa01[7]",
++		   (int)((u8tmp[0] & BIT(1)) >> 1), (int)((u8tmp[1] & BIT(0))),
++		   (int)((u8tmp[2] & BIT(3)) >> 3),
++		   (int)((u8tmp[3] & BIT(7)) >> 7));
++	CL_PRINTF(cli_buf);
++
++	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
++	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
++	u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
++	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x426);
++	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x45e);
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x/ 0x%x",
++		   "0x430/0x434/0x42a/0x426/0x45e[3]",
++		   u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0],
++		   (int)((u8tmp[1] & BIT(3)) >> 3));
++	CL_PRINTF(cli_buf);
++
++	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
++	u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x40);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = 0x%x/ 0x%x", "0x4c6[4]/0x40[5]",
++		   (int)((u8tmp[0] & BIT(4)) >> 4),
++		   (int)((u16tmp[0] & BIT(5)) >> 5));
++	CL_PRINTF(cli_buf);
++
++	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
++	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
++	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s",
++		   "0x550/0x522/4-RxAGC",
++		   u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off");
++	CL_PRINTF(cli_buf);
++
++	fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_OFDM);
++	fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_CCK);
++	cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_OFDM);
++	cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_CCK);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
++		   "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
++		   cca_cck, fa_cck, cca_ofdm, fa_ofdm);
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d (Rx_rate Data/RTS= %d/%d)",
++		   "CRC_OK CCK/11g/11n/11ac",
++		   coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
++		   coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht,
++		   coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate);
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
++		   "CRC_Err CCK/11g/11n/11n-agg",
++		   coex_sta->crc_err_cck, coex_sta->crc_err_11g,
++		   coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d",
++		   "WlHiPri/ Locking/ Locked/ Noisy",
++		   (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
++		   (coex_sta->cck_lock ? "Yes" : "No"),
++		   (coex_sta->cck_lock_ever ? "Yes" : "No"),
++		   coex_sta->wl_noisy_level);
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
++		   "0x770(Hi-pri rx/tx)",
++		   coex_sta->high_priority_rx, coex_sta->high_priority_tx,
++		   (coex_sta->is_hipri_rx_overhead ? "(scan overhead!!)" : ""));
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
++		   "0x774(Lo-pri rx/tx)",
++		   coex_sta->low_priority_rx, coex_sta->low_priority_tx,
++		   (bt_link_info->slave_role ? "(Slave!!)" : (
++		   coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : "")));
++	CL_PRINTF(cli_buf);
++
++	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
++}
++
++
++void ex_halbtc8723d1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
++{
++	if (btcoexist->manual_control ||	btcoexist->stop_coex_dm)
++		return;
++
++	if (BTC_IPS_ENTER == type) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], IPS ENTER notify\n");
++		BTC_TRACE(trace_buf);
++		coex_sta->under_ips = TRUE;
++
++		/* Write WL "Active" in Score-board for LPS off */
++		halbtc8723d1ant_post_state_to_bt(btcoexist,
++				BT_8723D_1ANT_SCOREBOARD_ACTIVE |
++				BT_8723D_1ANT_SCOREBOARD_ONOFF |
++				BT_8723D_1ANT_SCOREBOARD_SCAN |
++				BT_8723D_1ANT_SCOREBOARD_UNDERTEST,
++				FALSE);
++
++		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
++					     FORCE_EXEC,
++					     BT_8723D_1ANT_PHASE_WLAN_OFF);
++
++		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++
++	} else if (BTC_IPS_LEAVE == type) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], IPS LEAVE notify\n");
++		BTC_TRACE(trace_buf);
++#if 0
++		halbtc8723d1ant_post_state_to_bt(btcoexist,
++					 BT_8723D_1ANT_SCOREBOARD_ACTIVE, TRUE);
++
++		halbtc8723d1ant_post_state_to_bt(btcoexist,
++				 BT_8723D_1ANT_SCOREBOARD_ONOFF, TRUE);
++#endif
++
++		halbtc8723d1ant_init_hw_config(btcoexist, FALSE, FALSE);
++		halbtc8723d1ant_init_coex_dm(btcoexist);
++
++		coex_sta->under_ips = FALSE;
++	}
++}
++
++void ex_halbtc8723d1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
++{
++	static boolean  pre_force_lps_on = FALSE;
++
++	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
++		return;
++
++	if (BTC_LPS_ENABLE == type) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], LPS ENABLE notify\n");
++		BTC_TRACE(trace_buf);
++		coex_sta->under_lps = TRUE;
++
++		if (coex_sta->force_lps_ctrl == TRUE) { /* LPS No-32K */
++			/* Write WL "Active" in Score-board for PS-TDMA */
++			pre_force_lps_on = TRUE;
++			halbtc8723d1ant_post_state_to_bt(btcoexist,
++					 BT_8723D_1ANT_SCOREBOARD_ACTIVE, TRUE);
++
++		} else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */
++			/* Write WL "Non-Active" in Score-board for Native-PS */
++			pre_force_lps_on = FALSE;
++			halbtc8723d1ant_post_state_to_bt(btcoexist,
++				 BT_8723D_1ANT_SCOREBOARD_ACTIVE, FALSE);
++
++			halbtc8723d1ant_action_wifi_native_lps(btcoexist);
++		}
++	} else if (BTC_LPS_DISABLE == type) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], LPS DISABLE notify\n");
++		BTC_TRACE(trace_buf);
++		coex_sta->under_lps = FALSE;
++
++		/* Write WL "Active" in Score-board for LPS off */
++		halbtc8723d1ant_post_state_to_bt(btcoexist,
++					 BT_8723D_1ANT_SCOREBOARD_ACTIVE, TRUE);
++
++		if ((!pre_force_lps_on) && (!coex_sta->force_lps_ctrl))
++			halbtc8723d1ant_query_bt_info(btcoexist);
++	}
++}
++
++void ex_halbtc8723d1ant_scan_notify(IN struct btc_coexist *btcoexist,
++				    IN u8 type)
++{
++	boolean wifi_connected = FALSE;
++
++	if (btcoexist->manual_control ||
++	    btcoexist->stop_coex_dm)
++		return;
++
++	coex_sta->freeze_coexrun_by_btinfo = FALSE;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
++			   &wifi_connected);
++
++	if (BTC_SCAN_START == type) {
++
++		if (!wifi_connected)
++			coex_sta->wifi_in_scan_task = TRUE;
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], SCAN START notify\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d1ant_post_state_to_bt(btcoexist,
++					BT_8723D_1ANT_SCOREBOARD_ACTIVE |
++					BT_8723D_1ANT_SCOREBOARD_SCAN |
++					BT_8723D_1ANT_SCOREBOARD_ONOFF,
++					TRUE);
++
++		/*halbtc8723d1ant_query_bt_info(btcoexist);*/
++
++		/* Force antenna setup for no scan result issue */
++		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
++					     FORCE_EXEC,
++					     BT_8723D_1ANT_PHASE_2G_RUNTIME);
++
++		halbtc8723d1ant_run_coexist_mechanism(btcoexist);
++
++	} else {
++
++		coex_sta->wifi_in_scan_task = FALSE;
++
++		btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
++				   &coex_sta->scan_ap_num);
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], SCAN FINISH notify  (Scan-AP = %d)\n",
++			    coex_sta->scan_ap_num);
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d1ant_run_coexist_mechanism(btcoexist);
++	}
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], SCAN Notify() end\n");
++	BTC_TRACE(trace_buf);
++
++}
++
++void ex_halbtc8723d1ant_connect_notify(IN struct btc_coexist *btcoexist,
++				       IN u8 type)
++{
++	boolean	wifi_connected = FALSE;
++
++	if (btcoexist->manual_control ||
++	    btcoexist->stop_coex_dm)
++		return;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
++			   &wifi_connected);
++
++	if (BTC_ASSOCIATE_START == type) {
++
++		coex_sta->wifi_is_high_pri_task = TRUE;
++
++		halbtc8723d1ant_post_state_to_bt(btcoexist,
++					 BT_8723D_1ANT_SCOREBOARD_ACTIVE |
++					 BT_8723D_1ANT_SCOREBOARD_SCAN |
++					 BT_8723D_1ANT_SCOREBOARD_ONOFF,
++					 TRUE);
++
++		/* Force antenna setup for no scan result issue */
++		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
++					     FORCE_EXEC,
++					     BT_8723D_1ANT_PHASE_2G_RUNTIME);
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], CONNECT START notify\n");
++		BTC_TRACE(trace_buf);
++
++		coex_dm->arp_cnt = 0;
++		coex_sta->connect_ap_period_cnt = 2;
++
++		halbtc8723d1ant_run_coexist_mechanism(btcoexist);
++
++		/* To keep TDMA case during connect process,
++		to avoid changed by Btinfo and runcoexmechanism */
++		coex_sta->freeze_coexrun_by_btinfo = TRUE;
++	} else {
++
++		coex_sta->wifi_is_high_pri_task = FALSE;
++		coex_sta->freeze_coexrun_by_btinfo = FALSE;
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], CONNECT FINISH notify\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d1ant_run_coexist_mechanism(btcoexist);
++	}
++
++}
++
++void ex_halbtc8723d1ant_media_status_notify(IN struct btc_coexist *btcoexist,
++		IN u8 type)
++{
++	boolean			wifi_under_b_mode = FALSE;
++
++	if (btcoexist->manual_control ||
++	    btcoexist->stop_coex_dm)
++		return;
++
++	if (BTC_MEDIA_CONNECT == type) {
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], MEDIA connect notify\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d1ant_post_state_to_bt(btcoexist,
++					 BT_8723D_1ANT_SCOREBOARD_ACTIVE |
++					 BT_8723D_1ANT_SCOREBOARD_ONOFF,
++					 TRUE);
++
++		/* Force antenna setup for no scan result issue */
++		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
++					     FORCE_EXEC,
++					     BT_8723D_1ANT_PHASE_2G_RUNTIME);
++
++		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
++				   &wifi_under_b_mode);
++
++		/* Set CCK Tx/Rx high Pri except 11b mode */
++		if (wifi_under_b_mode) {
++			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
++						   0x00); /* CCK Tx */
++			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
++						   0x00); /* CCK Rx */
++		} else {
++			/* btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); */ /*CCK Tx */
++			/* btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); */ /*CCK Rx */
++			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
++						   0x00); /* CCK Tx */
++			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
++						   0x10); /* CCK Rx */
++		}
++	} else {
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], MEDIA disconnect notify\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d1ant_post_state_to_bt(btcoexist,
++				 BT_8723D_1ANT_SCOREBOARD_ACTIVE, FALSE);
++
++		btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
++		btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
++
++		coex_sta->cck_lock_ever = FALSE;
++	}
++	btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &coex_sta->wl_iot_peer);
++	halbtc8723d1ant_update_wifi_channel_info(btcoexist, type);
++
++}
++
++void ex_halbtc8723d1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
++		IN u8 type)
++{
++	boolean	under_4way = FALSE;
++	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++
++	if (btcoexist->manual_control ||
++	    btcoexist->stop_coex_dm)
++		return;
++
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
++			   &under_4way);
++
++	if (under_4way) {
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], specific Packet ---- under_4way!!\n");
++		BTC_TRACE(trace_buf);
++
++		coex_sta->wifi_is_high_pri_task = TRUE;
++		coex_sta->specific_pkt_period_cnt = 2;
++	} else if (BTC_PACKET_ARP == type) {
++
++		coex_dm->arp_cnt++;
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], specific Packet ARP notify -cnt = %d\n",
++			    coex_dm->arp_cnt);
++		BTC_TRACE(trace_buf);
++
++		coex_sta->specific_pkt_period_cnt = 1;
++
++		if (bt_link_info->sco_exist)
++			halbtc8723d1ant_run_coexist_mechanism(btcoexist);
++	} else {
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n",
++			    type);
++		BTC_TRACE(trace_buf);
++
++		coex_sta->wifi_is_high_pri_task = TRUE;
++		coex_sta->specific_pkt_period_cnt = 2;
++	}
++
++	if (coex_sta->wifi_is_high_pri_task || coex_sta->wifi_in_scan_task) {
++		halbtc8723d1ant_post_state_to_bt(btcoexist,
++						 BT_8723D_1ANT_SCOREBOARD_SCAN,
++						 TRUE);
++		halbtc8723d1ant_run_coexist_mechanism(btcoexist);
++	}
++}
++
++void ex_halbtc8723d1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
++				       IN u8 *tmp_buf, IN u8 length)
++{
++	struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++	u8 i, rsp_source = 0;
++	boolean	wifi_connected = FALSE;
++	boolean	wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE,
++		wifi_busy = FALSE;
++	static boolean is_scoreboard_scan = FALSE;
++
++	if (psd_scan->is_antdet_running) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], bt_info_notify return for AntDet is running\n");
++		BTC_TRACE(trace_buf);
++		return;
++	}
++
++	rsp_source = tmp_buf[0] & 0xf;
++	if (rsp_source >= BT_INFO_SRC_8723D_1ANT_MAX)
++		rsp_source = BT_INFO_SRC_8723D_1ANT_WIFI_FW;
++	coex_sta->bt_info_c2h_cnt[rsp_source]++;
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source,
++		    length);
++	BTC_TRACE(trace_buf);
++
++	for (i = 0; i < length; i++) {
++		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
++
++		if (i == length - 1) {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
++				    tmp_buf[i]);
++			BTC_TRACE(trace_buf);
++		} else {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
++				    tmp_buf[i]);
++			BTC_TRACE(trace_buf);
++		}
++	}
++
++	coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1];
++	coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4];
++	coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5];
++
++	if (BT_INFO_SRC_8723D_1ANT_WIFI_FW != rsp_source) {
++
++		/* if 0xff, it means BT is under WHCK test */
++		coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? TRUE :
++					  FALSE);
++
++		coex_sta->bt_create_connection = ((
++			coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? TRUE :
++						  FALSE);
++
++		/* unit: %, value-100 to translate to unit: dBm */
++		coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 +
++				    10;
++
++		coex_sta->c2h_bt_remote_name_req = ((
++			coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? TRUE :
++						    FALSE);
++
++		coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] &
++					 0x10) ? TRUE : FALSE);
++
++		coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] &
++				       0x8) ? TRUE : FALSE);
++
++		coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ?
++					     TRUE : FALSE);
++
++		coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info &
++			  BT_INFO_8723D_1ANT_B_INQ_PAGE) ? TRUE : FALSE);
++		
++		if (coex_sta->bt_inq_page_pre != coex_sta->c2h_bt_inquiry_page) {
++			coex_sta->bt_inq_page_pre = coex_sta->c2h_bt_inquiry_page;
++			coex_sta->bt_inq_page_remain = TRUE;
++					
++			if (!coex_sta->c2h_bt_inquiry_page)
++				coex_sta->bt_inq_page_downcount = 2;
++		}
++
++		coex_sta->a2dp_bit_pool = (((
++			coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ?
++			(coex_sta->bt_info_c2h[rsp_source][6]  & 0x7f) : 0);
++		
++		coex_sta->bt_mesh_on = ((coex_sta->bt_info_c2h[rsp_source][2]
++					   & 0x40) ? TRUE : FALSE);
++		
++		coex_sta->is_bt_a2dp_sink = (coex_sta->bt_info_c2h[rsp_source][6] & 0x80) ?
++									TRUE : FALSE;
++
++		coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] &
++					 0xf;
++
++		bt_link_info->slave_role  = coex_sta->bt_info_ext2 & 0x8;
++
++		coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7;
++
++		coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4;
++
++		coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6;
++
++		coex_sta->is_bt_opp_exist = (coex_sta->bt_info_ext2 & 0x1) ? TRUE : FALSE;
++
++		if (coex_sta->bt_retry_cnt >= 1)
++			coex_sta->pop_event_cnt++;
++
++		if (coex_sta->c2h_bt_remote_name_req)
++			coex_sta->cnt_remotenamereq++;
++
++		if (coex_sta->bt_info_ext & BIT(1))
++			coex_sta->cnt_reinit++;
++
++		if (coex_sta->bt_info_ext & BIT(2) ||
++		    (coex_sta->bt_create_connection &&
++		    coex_sta->pnp_awake_period_cnt > 0)) {
++			coex_sta->cnt_setuplink++;
++			coex_sta->is_setup_link = TRUE;
++			coex_sta->bt_relink_downcount = 2;
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], Re-Link start in BT info!!\n");
++			BTC_TRACE(trace_buf);
++		}
++
++		if (coex_sta->bt_info_ext & BIT(3))
++			coex_sta->cnt_ignwlanact++;
++
++		if (coex_sta->bt_info_ext & BIT(6))
++			coex_sta->cnt_roleswitch++;
++
++		if (coex_sta->bt_info_ext & BIT(7))
++			coex_sta->is_bt_multi_link = TRUE;
++		else
++			coex_sta->is_bt_multi_link = FALSE;
++
++		if (coex_sta->bt_info_ext & BIT(0))
++			coex_sta->is_hid_rcu = TRUE;
++		else
++			coex_sta->is_hid_rcu = FALSE;
++
++		if (coex_sta->bt_info_ext & BIT(5))
++			coex_sta->is_ble_scan_en = TRUE;
++		else
++			coex_sta->is_ble_scan_en = FALSE;
++
++		if (coex_sta->bt_create_connection) {
++			coex_sta->cnt_page++;
++
++			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY,
++					   &wifi_busy);
++
++			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
++			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
++			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
++
++			if (wifi_link || wifi_roam ||
++			    coex_sta->wifi_in_scan_task ||
++			    coex_sta->wifi_is_high_pri_task || wifi_busy) {
++
++				is_scoreboard_scan = TRUE;
++				halbtc8723d1ant_post_state_to_bt(btcoexist,
++					 BT_8723D_1ANT_SCOREBOARD_SCAN, TRUE);
++
++			} else
++				halbtc8723d1ant_post_state_to_bt(btcoexist,
++					 BT_8723D_1ANT_SCOREBOARD_SCAN, FALSE);
++
++		} else {
++				if (is_scoreboard_scan) {
++					halbtc8723d1ant_post_state_to_bt(btcoexist,
++						 BT_8723D_1ANT_SCOREBOARD_SCAN, FALSE);
++					is_scoreboard_scan = FALSE;
++				}
++		}
++
++		/* Here we need to resend some wifi info to BT */
++		/* because bt is reset and loss of the info. */
++
++		if ((!btcoexist->manual_control) &&
++		    (!btcoexist->stop_coex_dm)) {
++
++			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
++					   &wifi_connected);
++
++			/*	Re-Init */
++			if ((coex_sta->bt_info_ext & BIT(1))) {
++				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
++				BTC_TRACE(trace_buf);
++				if (wifi_connected)
++					halbtc8723d1ant_update_wifi_channel_info(
++						btcoexist, BTC_MEDIA_CONNECT);
++				else
++					halbtc8723d1ant_update_wifi_channel_info(
++						btcoexist,
++						BTC_MEDIA_DISCONNECT);
++			}
++
++
++	  /*	If Ignore_WLanAct && not SetUp_Link or Role_Switch */
++			if ((coex_sta->bt_info_ext & BIT(3)) &&
++				(!(coex_sta->bt_info_ext & BIT(2))) &&
++				(!(coex_sta->bt_info_ext & BIT(6)))) {
++
++				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
++				BTC_TRACE(trace_buf);
++				halbtc8723d1ant_ignore_wlan_act(btcoexist,
++							FORCE_EXEC, FALSE);
++			} else {
++				if (coex_sta->bt_info_ext & BIT(2)) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"[BTCoex], BT ignore Wlan active because Re-link!!\n");
++					BTC_TRACE(trace_buf);
++				} else if (coex_sta->bt_info_ext & BIT(6)) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"[BTCoex], BT ignore Wlan active because Role-Switch!!\n");
++					BTC_TRACE(trace_buf);
++				}
++			}
++		}
++
++	}
++
++	halbtc8723d1ant_update_bt_link_info(btcoexist);
++
++	halbtc8723d1ant_run_coexist_mechanism(btcoexist);
++}
++
++void ex_halbtc8723d1ant_wl_fwdbginfo_notify(IN struct btc_coexist *btcoexist,
++				       IN u8 *tmp_buf, IN u8 length)
++{
++	u8 i = 0;
++	static u8 tmp_buf_pre[10], cnt;
++	u8 h2c_parameter[2] = {0};
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], WiFi Fw Dbg info = %d %d %d %d %d %d %d %d (len = %d)\n",
++		    tmp_buf[0], tmp_buf[1], tmp_buf[2], tmp_buf[3], tmp_buf[4],
++		    tmp_buf[5], tmp_buf[6], tmp_buf[7], length);
++	BTC_TRACE(trace_buf);
++
++	if (tmp_buf[0] == 0x8) {
++		for (i = 1; i <= 7; i++) {
++			coex_sta->wl_fw_dbg_info[i] =
++				(tmp_buf[i] >= tmp_buf_pre[i]) ?
++					(tmp_buf[i] - tmp_buf_pre[i]) :
++					(255 - tmp_buf_pre[i] + tmp_buf[i]);
++
++			tmp_buf_pre[i] = tmp_buf[i];
++		}
++	}
++
++	if (!coex_sta->is_no_wl_5ms_extend && coex_sta->force_lps_ctrl &&
++	    !coex_sta->cck_lock_ever) {
++		if (coex_sta->wl_fw_dbg_info[7] <= 5)
++			cnt++;
++		else
++			cnt = 0;
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], 5ms WL slot extend cnt = %d!!\n", cnt);
++		BTC_TRACE(trace_buf);
++
++		if (cnt == 7) {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], set h2c 0x69 opcode 12 to turn off 5ms WL slot extend!!\n");
++			BTC_TRACE(trace_buf);
++
++			h2c_parameter[0] = 0xc;
++			h2c_parameter[1] = 0x1;
++			btcoexist->btc_fill_h2c(btcoexist, 0x69, 2,
++						h2c_parameter);
++			coex_sta->is_no_wl_5ms_extend = TRUE;
++			cnt = 0;
++		}
++	}
++
++	if (coex_sta->is_no_wl_5ms_extend && coex_sta->cck_lock) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], set h2c 0x69 opcode 12 to turn on 5ms WL slot extend!!\n");
++		BTC_TRACE(trace_buf);
++
++		h2c_parameter[0] = 0xc;
++		h2c_parameter[1] = 0x0;
++		btcoexist->btc_fill_h2c(btcoexist, 0x69, 2, h2c_parameter);
++		coex_sta->is_no_wl_5ms_extend = FALSE;
++	}
++}
++
++void ex_halbtc8723d1ant_rx_rate_change_notify(IN struct btc_coexist *btcoexist,
++		IN BOOLEAN is_data_frame, IN u8 btc_rate_id)
++{
++	BOOLEAN wifi_connected = FALSE;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
++			   &wifi_connected);
++
++	if (is_data_frame) {
++		coex_sta->wl_rx_rate = btc_rate_id;
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], rx_rate_change_notify data rate id = %d, RTS_Rate = %d\n",
++			coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate);
++		BTC_TRACE(trace_buf);
++	} else {
++		coex_sta->wl_rts_rx_rate = btc_rate_id;
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], rts_rate_change_notify RTS rate id = %d, RTS_Rate = %d\n",
++			coex_sta->wl_rts_rx_rate, coex_sta->wl_rts_rx_rate);
++		BTC_TRACE(trace_buf);
++	}
++
++	if (wifi_connected &&
++	    (coex_dm->bt_status ==  BT_8723D_1ANT_BT_STATUS_ACL_BUSY ||
++	     coex_dm->bt_status ==  BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY ||
++	     coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_SCO_BUSY)) {
++
++		if (coex_sta->wl_rx_rate == BTC_CCK_5_5 ||
++		    coex_sta->wl_rx_rate == BTC_OFDM_6 ||
++		    coex_sta->wl_rx_rate == BTC_MCS_0) {
++
++			coex_sta->cck_lock_warn = TRUE;
++
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], cck lock warning...\n");
++			BTC_TRACE(trace_buf);
++		} else if (coex_sta->wl_rx_rate == BTC_CCK_1 ||
++			   coex_sta->wl_rx_rate == BTC_CCK_2 ||
++			   coex_sta->wl_rts_rx_rate == BTC_CCK_1 ||
++			   coex_sta->wl_rts_rx_rate == BTC_CCK_2) {
++
++			coex_sta->cck_lock = TRUE;
++			coex_sta->cck_lock_ever = TRUE;
++
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], cck locking...\n");
++			BTC_TRACE(trace_buf);
++		} else {
++			coex_sta->cck_lock_warn = FALSE;
++			coex_sta->cck_lock = FALSE;
++
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], cck unlock...\n");
++			BTC_TRACE(trace_buf);
++		}
++	} else {
++		if (coex_dm->bt_status ==
++		    BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE ||
++		    coex_dm->bt_status ==
++		    BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE) {
++			coex_sta->cck_lock_warn = FALSE;
++			coex_sta->cck_lock = FALSE;
++		}
++	}
++
++}
++
++
++
++void ex_halbtc8723d1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
++		IN u8 type)
++{
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
++	BTC_TRACE(trace_buf);
++
++	if (BTC_RF_ON == type) {
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], RF is turned ON!!\n");
++		BTC_TRACE(trace_buf);
++
++		btcoexist->stop_coex_dm = FALSE;
++		coex_sta->is_rf_state_off = FALSE;
++#if 0
++		halbtc8723d1ant_post_state_to_bt(btcoexist,
++					 BT_8723D_1ANT_SCOREBOARD_ACTIVE, TRUE);
++		halbtc8723d1ant_post_state_to_bt(btcoexist,
++					 BT_8723D_1ANT_SCOREBOARD_ONOFF, TRUE);
++#endif
++
++	} else if (BTC_RF_OFF == type) {
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], RF is turned OFF!!\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d1ant_post_state_to_bt(btcoexist,
++				BT_8723D_1ANT_SCOREBOARD_ACTIVE |
++				BT_8723D_1ANT_SCOREBOARD_ONOFF |
++				BT_8723D_1ANT_SCOREBOARD_SCAN |
++				BT_8723D_1ANT_SCOREBOARD_UNDERTEST,
++				FALSE);
++
++		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
++					     FORCE_EXEC,
++					     BT_8723D_1ANT_PHASE_WLAN_OFF);
++
++		halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0);
++
++		btcoexist->stop_coex_dm = TRUE;
++		coex_sta->is_rf_state_off = TRUE;
++	}
++}
++
++void ex_halbtc8723d1ant_halt_notify(IN struct btc_coexist *btcoexist)
++{
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
++	BTC_TRACE(trace_buf);
++
++	halbtc8723d1ant_post_state_to_bt(btcoexist,
++				BT_8723D_1ANT_SCOREBOARD_ACTIVE |
++				BT_8723D_1ANT_SCOREBOARD_ONOFF |
++				BT_8723D_1ANT_SCOREBOARD_SCAN |
++				BT_8723D_1ANT_SCOREBOARD_UNDERTEST,
++				FALSE);
++
++	halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
++				     BT_8723D_1ANT_PHASE_WLAN_OFF);
++
++	/*halbtc8723d1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, TRUE);*/
++
++	ex_halbtc8723d1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
++
++	halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0);
++
++	btcoexist->stop_coex_dm = TRUE;
++}
++
++void ex_halbtc8723d1ant_pnp_notify(IN struct btc_coexist *btcoexist,
++				   IN u8 pnp_state)
++{
++	static u8 pre_pnp_state;
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
++	BTC_TRACE(trace_buf);
++
++	if ((BTC_WIFI_PNP_SLEEP == pnp_state) ||
++	    (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], Pnp notify to SLEEP\n");
++		BTC_TRACE(trace_buf);
++
++		coex_sta->under_ips = FALSE;
++		coex_sta->under_lps = FALSE;
++
++		halbtc8723d1ant_post_state_to_bt(btcoexist,
++				BT_8723D_1ANT_SCOREBOARD_ACTIVE |
++				BT_8723D_1ANT_SCOREBOARD_ONOFF |
++				BT_8723D_1ANT_SCOREBOARD_SCAN |
++				BT_8723D_1ANT_SCOREBOARD_UNDERTEST,
++				FALSE);
++
++		if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) {
++
++			halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
++						     FORCE_EXEC,
++					     BT_8723D_1ANT_PHASE_2G_RUNTIME);
++		} else {
++
++			halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
++						     FORCE_EXEC,
++					     BT_8723D_1ANT_PHASE_WLAN_OFF);
++		}
++
++		btcoexist->stop_coex_dm = TRUE;
++	} else {
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], Pnp notify to WAKE UP\n");
++		BTC_TRACE(trace_buf);
++
++		coex_sta->pnp_awake_period_cnt = 3;
++
++		/*WoWLAN*/
++		if (pre_pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT ||
++		    pnp_state == BTC_WIFI_PNP_WOWLAN) {
++			coex_sta->run_time_state = TRUE;
++			btcoexist->stop_coex_dm = FALSE;
++			halbtc8723d1ant_run_coexist_mechanism(btcoexist);
++		}
++#if 0
++		halbtc8723d1ant_post_state_to_bt(btcoexist,
++					 BT_8723D_1ANT_SCOREBOARD_ACTIVE, TRUE);
++		halbtc8723d1ant_post_state_to_bt(btcoexist,
++					 BT_8723D_1ANT_SCOREBOARD_ONOFF, TRUE);
++#endif
++		/*btcoexist->stop_coex_dm = FALSE;*/
++	}
++
++	pre_pnp_state = pnp_state;
++}
++
++
++void ex_halbtc8723d1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
++{
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], *****************Coex DM Reset*****************\n");
++	BTC_TRACE(trace_buf);
++
++	halbtc8723d1ant_init_hw_config(btcoexist, FALSE, FALSE);
++	halbtc8723d1ant_init_coex_dm(btcoexist);
++}
++
++void ex_halbtc8723d1ant_periodical(IN struct btc_coexist *btcoexist)
++{
++
++	struct  btc_board_info	*board_info = &btcoexist->board_info;
++	boolean wifi_busy = FALSE, bt_ctr_change = FALSE;
++	u4Byte	value = 0;
++	u32	bt_patch_ver;
++	static u8 cnt = 0;
++	boolean bt_relink_finish = FALSE, special_pkt_finish = FALSE;
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], ************* Periodical *************\n");
++	BTC_TRACE(trace_buf);
++
++#if (BT_AUTO_REPORT_ONLY_8723D_1ANT == 0)
++	halbtc8723d1ant_query_bt_info(btcoexist);
++
++#endif
++
++	bt_ctr_change = halbtc8723d1ant_monitor_bt_ctr(btcoexist);
++	halbtc8723d1ant_monitor_wifi_ctr(btcoexist);
++
++	halbtc8723d1ant_monitor_bt_enable_disable(btcoexist);
++
++	if (coex_sta->bt_relink_downcount != 0) {
++		coex_sta->bt_relink_downcount--;
++
++		if (coex_sta->bt_relink_downcount == 0) {
++			coex_sta->is_setup_link = FALSE;
++			bt_relink_finish = TRUE;
++		}
++	}
++	
++	if (coex_sta->bt_inq_page_downcount != 0) {
++		coex_sta->bt_inq_page_downcount--;
++		if (coex_sta->bt_relink_downcount == 0)
++			coex_sta->bt_inq_page_remain = FALSE;
++	}
++
++	/* for 4-way, DHCP, EAPOL packet */
++	if (coex_sta->specific_pkt_period_cnt > 0) {
++
++		coex_sta->specific_pkt_period_cnt--;
++
++		if ((coex_sta->specific_pkt_period_cnt == 0) &&
++		    (coex_sta->wifi_is_high_pri_task)) {
++			coex_sta->wifi_is_high_pri_task = FALSE;
++			special_pkt_finish = TRUE;
++		}
++	}
++
++	if (coex_sta->pnp_awake_period_cnt > 0)
++		coex_sta->pnp_awake_period_cnt--;
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], pnp_awake_period_cnt = %d\n",
++				coex_sta->pnp_awake_period_cnt);
++	BTC_TRACE(trace_buf);
++
++	/*for A2DP glitch during connecting AP*/
++	if (coex_sta->connect_ap_period_cnt > 0)
++		coex_sta->connect_ap_period_cnt--;
++
++	if (halbtc8723d1ant_is_wifibt_status_changed(btcoexist) ||
++	    bt_relink_finish || special_pkt_finish || bt_ctr_change)
++		halbtc8723d1ant_run_coexist_mechanism(btcoexist);
++}
++
++void ex_halbtc8723d1ant_set_antenna_notify(IN struct btc_coexist *btcoexist,
++		IN u8 type)
++{
++	struct  btc_board_info	*board_info = &btcoexist->board_info;
++
++	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
++		return;
++
++	if (type == 2) { /* two antenna */
++		board_info->ant_div_cfg = TRUE;
++		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI,
++					     FORCE_EXEC,
++					     BT_8723D_1ANT_PHASE_2G_RUNTIME);
++	} else { /* one antenna */
++		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
++					     FORCE_EXEC,
++					     BT_8723D_1ANT_PHASE_2G_RUNTIME);
++	}
++}
++
++#ifdef PLATFORM_WINDOWS
++#pragma optimize("", off)
++#endif
++void ex_halbtc8723d1ant_antenna_detection(IN struct btc_coexist *btcoexist,
++		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
++{
++
++	static u32 ant_det_count = 0, ant_det_fail_count = 0;
++	struct  btc_board_info	*board_info = &btcoexist->board_info;
++	u16		u16tmp;
++	u8			AntDetval = 0;
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "xxxxxxxxxxxxxxxx Ext Call AntennaDetect()!!\n");
++	BTC_TRACE(trace_buf);
++}
++
++
++void ex_halbtc8723d1ant_display_ant_detection(IN struct btc_coexist *btcoexist)
++{
++#if 0
++	struct  btc_board_info	*board_info = &btcoexist->board_info;
++
++	if (psd_scan->ant_det_try_count != 0)	{
++		halbtc8723d1ant_psd_show_antenna_detect_result(btcoexist);
++
++		if (board_info->btdm_ant_det_finish)
++			halbtc8723d1ant_psd_showdata(btcoexist);
++	}
++#endif
++
++}
++
++void ex_halbtc8723d1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
++		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
++{
++
++
++}
++
++void ex_halbtc8723d1ant_psd_scan(IN struct btc_coexist *btcoexist,
++		 IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
++{
++
++
++}
++
++
++#endif
++
++#endif	/* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/halbtc8723d1ant.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/halbtc8723d1ant.h
+new file mode 100644
+index 000000000..fb2819722
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/halbtc8723d1ant.h
+@@ -0,0 +1,475 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++
++#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
++
++#if (RTL8723D_SUPPORT == 1)
++
++/* *******************************************
++ * The following is for 8723D 1ANT BT Co-exist definition
++ * ******************************************* */
++#define	BT_8723D_1ANT_COEX_DBG					0
++#define	BT_AUTO_REPORT_ONLY_8723D_1ANT				1
++
++#define	BT_INFO_8723D_1ANT_B_FTP				BIT(7)
++#define	BT_INFO_8723D_1ANT_B_A2DP				BIT(6)
++#define	BT_INFO_8723D_1ANT_B_HID				BIT(5)
++#define	BT_INFO_8723D_1ANT_B_SCO_BUSY				BIT(4)
++#define	BT_INFO_8723D_1ANT_B_ACL_BUSY				BIT(3)
++#define	BT_INFO_8723D_1ANT_B_INQ_PAGE				BIT(2)
++#define	BT_INFO_8723D_1ANT_B_SCO_ESCO				BIT(1)
++#define	BT_INFO_8723D_1ANT_B_CONNECTION				BIT(0)
++
++#define	BT_INFO_8723D_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_)	\
++	(((_BT_INFO_EXT_&BIT(0))) ? TRUE : FALSE)
++
++#define	BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT		2
++
++#define  BT_8723D_1ANT_WIFI_NOISY_THRESH			30 /*max: 255*/
++#define  BT_8723D_1ANT_DEFAULT_ISOLATION			15 /*unit: dB*/
++
++
++/* for Antenna detection */
++#define	BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND			50
++#define	BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION			70
++#define	BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION		55
++#define	BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT				35
++#define	BT_8723D_1ANT_ANTDET_RETRY_INTERVAL				10
++#define	BT_8723D_1ANT_ANTDET_SWEEPPOINT_DELAY				60000
++#define	BT_8723D_1ANT_ANTDET_ENABLE					0
++#define	BT_8723D_1ANT_ANTDET_BTTXTIME					100
++#define	BT_8723D_1ANT_ANTDET_BTTXCHANNEL				39
++#define	BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT				50
++
++#define	BT_8723D_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT		30000
++
++enum bt_8723d_1ant_signal_state {
++	BT_8723D_1ANT_SIG_STA_SET_TO_LOW	= 0x0,
++	BT_8723D_1ANT_SIG_STA_SET_BY_HW		= 0x0,
++	BT_8723D_1ANT_SIG_STA_SET_TO_HIGH	= 0x1,
++	BT_8723D_1ANT_SIG_STA_MAX
++};
++
++enum bt_8723d_1ant_path_ctrl_owner {
++	BT_8723D_1ANT_PCO_BTSIDE		= 0x0,
++	BT_8723D_1ANT_PCO_WLSIDE		= 0x1,
++	BT_8723D_1ANT_PCO_MAX
++};
++
++enum bt_8723d_1ant_gnt_ctrl_type {
++	BT_8723D_1ANT_GNT_TYPE_CTRL_BY_PTA	= 0x0,
++	BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW	= 0x1,
++	BT_8723D_1ANT_GNT_TYPE_MAX
++};
++
++enum bt_8723d_1ant_gnt_ctrl_block {
++	BT_8723D_1ANT_GNT_BLOCK_RFC_BB		= 0x0,
++	BT_8723D_1ANT_GNT_BLOCK_RFC		= 0x1,
++	BT_8723D_1ANT_GNT_BLOCK_BB		= 0x2,
++	BT_8723D_1ANT_GNT_BLOCK_MAX
++};
++
++enum bt_8723d_1ant_lte_coex_table_type {
++	BT_8723D_1ANT_CTT_WL_VS_LTE		= 0x0,
++	BT_8723D_1ANT_CTT_BT_VS_LTE		= 0x1,
++	BT_8723D_1ANT_CTT_MAX
++};
++
++enum bt_8723d_1ant_lte_break_table_type {
++	BT_8723D_1ANT_LBTT_WL_BREAK_LTE		= 0x0,
++	BT_8723D_1ANT_LBTT_BT_BREAK_LTE		= 0x1,
++	BT_8723D_1ANT_LBTT_LTE_BREAK_WL		= 0x2,
++	BT_8723D_1ANT_LBTT_LTE_BREAK_BT		= 0x3,
++	BT_8723D_1ANT_LBTT_MAX
++};
++
++enum bt_info_src_8723d_1ant {
++	BT_INFO_SRC_8723D_1ANT_WIFI_FW			= 0x0,
++	BT_INFO_SRC_8723D_1ANT_BT_RSP			= 0x1,
++	BT_INFO_SRC_8723D_1ANT_BT_ACTIVE_SEND		= 0x2,
++	BT_INFO_SRC_8723D_1ANT_MAX
++};
++
++enum bt_8723d_1ant_bt_status {
++	BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE	= 0x0,
++	BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE		= 0x1,
++	BT_8723D_1ANT_BT_STATUS_INQ_PAGE		= 0x2,
++	BT_8723D_1ANT_BT_STATUS_ACL_BUSY		= 0x3,
++	BT_8723D_1ANT_BT_STATUS_SCO_BUSY		= 0x4,
++	BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY		= 0x5,
++	BT_8723D_1ANT_BT_STATUS_MAX
++};
++
++enum bt_8723d_1ant_wifi_status {
++	BT_8723D_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE		= 0x0,
++	BT_8723D_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN	= 0x1,
++	BT_8723D_1ANT_WIFI_STATUS_CONNECTED_SCAN		= 0x2,
++	BT_8723D_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT	= 0x3,
++	BT_8723D_1ANT_WIFI_STATUS_CONNECTED_IDLE		= 0x4,
++	BT_8723D_1ANT_WIFI_STATUS_CONNECTED_BUSY		= 0x5,
++	BT_8723D_1ANT_WIFI_STATUS_MAX
++};
++
++enum bt_8723d_1ant_coex_algo {
++	BT_8723D_1ANT_COEX_ALGO_UNDEFINED			= 0x0,
++	BT_8723D_1ANT_COEX_ALGO_SCO				= 0x1,
++	BT_8723D_1ANT_COEX_ALGO_HID				= 0x2,
++	BT_8723D_1ANT_COEX_ALGO_A2DP				= 0x3,
++	BT_8723D_1ANT_COEX_ALGO_A2DP_PANHS			= 0x4,
++	BT_8723D_1ANT_COEX_ALGO_PANEDR				= 0x5,
++	BT_8723D_1ANT_COEX_ALGO_PANHS				= 0x6,
++	BT_8723D_1ANT_COEX_ALGO_PANEDR_A2DP			= 0x7,
++	BT_8723D_1ANT_COEX_ALGO_PANEDR_HID			= 0x8,
++	BT_8723D_1ANT_COEX_ALGO_HID_A2DP_PANEDR			= 0x9,
++	BT_8723D_1ANT_COEX_ALGO_HID_A2DP			= 0xa,
++	BT_8723D_1ANT_COEX_ALGO_MAX				= 0xb,
++};
++
++enum bt_8723d_1ant_phase {
++	BT_8723D_1ANT_PHASE_COEX_INIT				= 0x0,
++	BT_8723D_1ANT_PHASE_WLANONLY_INIT			= 0x1,
++	BT_8723D_1ANT_PHASE_WLAN_OFF				= 0x2,
++	BT_8723D_1ANT_PHASE_2G_RUNTIME				= 0x3,
++	BT_8723D_1ANT_PHASE_5G_RUNTIME				= 0x4,
++	BT_8723D_1ANT_PHASE_BTMPMODE				= 0x5,
++	BT_8723D_1ANT_PHASE_ANTENNA_DET				= 0x6,
++	BT_8723D_1ANT_PHASE_COEX_POWERON			= 0x7,
++	BT_8723D_1ANT_PHASE_MAX
++};
++
++enum bt_8723d_1ant_Scoreboard {
++	BT_8723D_1ANT_SCOREBOARD_ACTIVE				= BIT(0),
++	BT_8723D_1ANT_SCOREBOARD_ONOFF				= BIT(1),
++	BT_8723D_1ANT_SCOREBOARD_SCAN				= BIT(2),
++	BT_8723D_1ANT_SCOREBOARD_UNDERTEST			= BIT(3),
++	BT_8723D_1ANT_SCOREBOARD_RXGAIN				= BIT(4),
++	BT_8723D_1ANT_SCOREBOARD_DKTOPP2M			= BIT(5),
++	BT_8723D_1ANT_SCOREBOARD_WLBUSY				= BIT(6),
++	BT_8723D_1ANT_SCOREBOARD_TDMA				= BIT(9),
++};
++
++struct coex_dm_8723d_1ant {
++	/* hw setting */
++	u8		pre_ant_pos_type;
++	u8		cur_ant_pos_type;
++	/* fw mechanism */
++	boolean		cur_ignore_wlan_act;
++	boolean		pre_ignore_wlan_act;
++	u8		cur_ps_tdma;
++	u8		ps_tdma_para[5];
++	u8		ps_tdma_du_adj_type;
++	boolean		cur_ps_tdma_on;
++	boolean		pre_bt_auto_report;
++	boolean		cur_bt_auto_report;
++	u8		pre_lps;
++	u8		cur_lps;
++	u8		pre_rpwm;
++	u8		cur_rpwm;
++
++	/* sw mechanism */
++	boolean	pre_low_penalty_ra;
++	boolean		cur_low_penalty_ra;
++	u32		cur_val0x6c0;
++	u32		cur_val0x6c4;
++	u32		cur_val0x6c8;
++	u8		cur_val0x6cc;
++	boolean		limited_dig;
++
++	u32		backup_arfr_cnt1;
++	u32		backup_arfr_cnt2;
++	u16		backup_retry_limit;
++	u8		backup_ampdu_max_time;
++
++	/* algorithm related */
++	u8		pre_algorithm;
++	u8		cur_algorithm;
++	u8		bt_status;
++	u8		wifi_chnl_info[3];
++
++	u32		pre_ra_mask;
++	u32		cur_ra_mask;
++	u8		pre_arfr_type;
++	u8		cur_arfr_type;
++	u8		pre_retry_limit_type;
++	u8		cur_retry_limit_type;
++	u8		pre_ampdu_time_type;
++	u8		cur_ampdu_time_type;
++	u32		arp_cnt;
++
++	u8		error_condition;
++	u32		setting_tdma;
++};
++
++struct coex_sta_8723d_1ant {
++	boolean		bt_disabled;
++	boolean		bt_link_exist;
++	boolean		sco_exist;
++	boolean		a2dp_exist;
++	boolean		hid_exist;
++	boolean		pan_exist;
++	boolean		bt_hi_pri_link_exist;
++	u8		num_of_profile;
++
++	boolean		under_lps;
++	boolean		under_ips;
++	u32		specific_pkt_period_cnt;
++	u8		connect_ap_period_cnt;
++	u8		pnp_awake_period_cnt;
++	u32		high_priority_tx;
++	u32		high_priority_rx;
++	u32		low_priority_tx;
++	u32		low_priority_rx;
++	boolean		bt_ctr_ok;
++	boolean		is_hipri_rx_overhead;
++	s8		bt_rssi;
++	boolean		bt_tx_rx_mask;
++	boolean		bt_mesh_on;
++	u8		pre_bt_rssi_state;
++	u8		pre_wifi_rssi_state[4];
++	u8		bt_info_c2h[BT_INFO_SRC_8723D_1ANT_MAX][10];
++	u32		bt_info_c2h_cnt[BT_INFO_SRC_8723D_1ANT_MAX];
++	boolean		bt_whck_test;
++	boolean		c2h_bt_inquiry_page;
++	boolean		bt_inq_page_pre;
++	boolean 	bt_inq_page_remain;
++	boolean		c2h_bt_remote_name_req;
++	boolean		c2h_bt_page;
++	boolean		wifi_is_high_pri_task;
++	boolean		wifi_in_scan_task;
++	u8		bt_retry_cnt;
++	u8		bt_info_ext;
++	u8		bt_info_ext2;
++	u32		pop_event_cnt;
++	u8		scan_ap_num;
++
++	u32		crc_ok_cck;
++	u32		crc_ok_11g;
++	u32		crc_ok_11n;
++	u32		crc_ok_11n_vht;
++
++	u32		crc_err_cck;
++	u32		crc_err_11g;
++	u32		crc_err_11n;
++	u32		crc_err_11n_vht;
++
++	boolean		cck_lock;
++	boolean		cck_lock_ever;
++	boolean		cck_lock_warn;
++
++	u8		coex_table_type;
++	boolean		force_lps_ctrl;
++	boolean		concurrent_rx_mode_on;
++
++	u16		score_board;
++	u8		isolation_btween_wb;   /* 0~ 50 */
++
++	u8		a2dp_bit_pool;
++	u8		kt_ver;
++	boolean		acl_busy;
++	boolean		bt_create_connection;
++
++	u32		bt_coex_supported_feature;
++	u32		bt_coex_supported_version;
++
++	u8		bt_ble_scan_type;
++	u32		bt_ble_scan_para[3];
++
++	boolean		run_time_state;
++	boolean		freeze_coexrun_by_btinfo;
++
++	boolean		is_A2DP_3M;
++	boolean		voice_over_HOGP;
++	u8		bt_info;
++	u8		forbidden_slot;
++	u8		hid_busy_num;
++	u8		hid_pair_cnt;
++
++	u32		cnt_remotenamereq;
++	u32		cnt_setuplink;
++	u32		cnt_reinit;
++	u32		cnt_ignwlanact;
++	u32		cnt_page;
++	u32		cnt_roleswitch;
++
++	u16		bt_reg_vendor_ac;
++	u16		bt_reg_vendor_ae;
++
++	boolean		is_setup_link;
++	u8		wl_noisy_level;
++	u32		gnt_error_cnt;
++
++	u8		bt_afh_map[10];
++	u8		bt_relink_downcount;
++	u8		bt_inq_page_downcount;
++	boolean		is_tdma_btautoslot;
++	boolean		is_tdma_btautoslot_hang;
++
++	boolean		is_rf_state_off;
++
++	boolean		is_hid_low_pri_tx_overhead;
++	boolean		is_bt_multi_link;
++	boolean		is_bt_a2dp_sink;
++	boolean		is_bt_mesh_ver;
++
++	u8		wl_fw_dbg_info[10];
++	u8		wl_rx_rate;
++	u8		wl_rts_rx_rate;
++
++	u16		score_board_WB;
++
++	boolean		is_hid_rcu;
++	boolean		is_ble_scan_en;
++
++	u16		legacy_forbidden_slot;
++	u16		le_forbidden_slot;
++	u8		bt_a2dp_vendor_id;
++	u32		bt_a2dp_device_name;
++	boolean		is_bt_opp_exist;
++	boolean		is_no_wl_5ms_extend;
++
++	u16		wl_0x42a_backup;
++	u32		wl_0x430_backup;
++	u32		wl_0x434_backup;
++	u8		wl_0x456_backup;
++
++	boolean		wl_tx_limit_en;
++	boolean		wl_ampdu_limit_en;
++	boolean		wl_rxagg_limit_en;
++	u8		wl_rxagg_size;
++	
++	u8	tdma_timer_base;
++	u8	wl_iot_peer;
++	
++};
++
++#define  BT_8723D_1ANT_ANTDET_PSD_POINTS			256
++#define  BT_8723D_1ANT_ANTDET_PSD_AVGNUM			1
++#define	BT_8723D_1ANT_ANTDET_BUF_LEN			16
++
++struct psdscan_sta_8723d_1ant {
++
++	u32	ant_det_bt_le_channel;  /* BT LE Channel ex:2412 */
++	u32	ant_det_bt_tx_time;
++	u32	ant_det_pre_psdscan_peak_val;
++	boolean	ant_det_is_ant_det_available;
++	u32	ant_det_psd_scan_peak_val;
++	boolean	ant_det_is_btreply_available;
++	u32	ant_det_psd_scan_peak_freq;
++
++	u8	ant_det_result;
++	u8	ant_det_peak_val[BT_8723D_1ANT_ANTDET_BUF_LEN];
++	u8	ant_det_peak_freq[BT_8723D_1ANT_ANTDET_BUF_LEN];
++	u32	ant_det_try_count;
++	u32	ant_det_fail_count;
++	u32	ant_det_inteval_count;
++	u32	ant_det_thres_offset;
++
++	u32	real_cent_freq;
++	s32	real_offset;
++	u32	real_span;
++
++	u32	psd_band_width;
++	u32	psd_point;
++	u32	psd_report[1024];
++	u32	psd_report_max_hold[1024];
++	u32	psd_start_point;
++	u32	psd_stop_point;
++	u32	psd_max_value_point;
++	u32	psd_max_value;
++	u32	psd_max_value2;
++	u32	psd_avg_value;
++	u32	psd_loop_max_value[BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT];
++	u32	psd_start_base;
++	u32	psd_avg_num;	/* 1/8/16/32 */
++	u32	psd_gen_count;
++	boolean	is_antdet_running;
++	boolean	is_psd_show_max_only;
++};
++
++/* *******************************************
++ * The following is interface which will notify coex module.
++ * ******************************************* */
++void ex_halbtc8723d1ant_power_on_setting(IN struct btc_coexist *btcoexist);
++void ex_halbtc8723d1ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
++void ex_halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist,
++				       IN boolean wifi_only);
++void ex_halbtc8723d1ant_init_coex_dm(IN struct btc_coexist *btcoexist);
++void ex_halbtc8723d1ant_ips_notify(IN struct btc_coexist *btcoexist,
++				   IN u8 type);
++void ex_halbtc8723d1ant_lps_notify(IN struct btc_coexist *btcoexist,
++				   IN u8 type);
++void ex_halbtc8723d1ant_scan_notify(IN struct btc_coexist *btcoexist,
++				    IN u8 type);
++void ex_halbtc8723d1ant_connect_notify(IN struct btc_coexist *btcoexist,
++				       IN u8 type);
++void ex_halbtc8723d1ant_media_status_notify(IN struct btc_coexist *btcoexist,
++		IN u8 type);
++void ex_halbtc8723d1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
++		IN u8 type);
++void ex_halbtc8723d1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
++				       IN u8 *tmp_buf, IN u8 length);
++void ex_halbtc8723d1ant_wl_fwdbginfo_notify(IN struct btc_coexist *btcoexist,
++				       IN u8 *tmp_buf, IN u8 length);
++void ex_halbtc8723d1ant_rx_rate_change_notify(IN struct btc_coexist *btcoexist,
++		IN BOOLEAN is_data_frame, IN u8 btc_rate_id);
++void ex_halbtc8723d1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
++		IN u8 type);
++void ex_halbtc8723d1ant_halt_notify(IN struct btc_coexist *btcoexist);
++void ex_halbtc8723d1ant_pnp_notify(IN struct btc_coexist *btcoexist,
++				   IN u8 pnp_state);
++void ex_halbtc8723d1ant_coex_dm_reset(IN struct btc_coexist *btcoexist);
++void ex_halbtc8723d1ant_periodical(IN struct btc_coexist *btcoexist);
++void ex_halbtc8723d1ant_set_antenna_notify(IN struct btc_coexist *btcoexist,
++		IN u8 type);
++void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist);
++void ex_halbtc8723d1ant_antenna_detection(IN struct btc_coexist *btcoexist,
++		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
++void ex_halbtc8723d1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
++		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
++
++void ex_halbtc8723d1ant_psd_scan(IN struct btc_coexist *btcoexist,
++		 IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
++void ex_halbtc8723d1ant_display_ant_detection(IN struct btc_coexist *btcoexist);
++
++#else
++#define	ex_halbtc8723d1ant_power_on_setting(btcoexist)
++#define	ex_halbtc8723d1ant_pre_load_firmware(btcoexist)
++#define	ex_halbtc8723d1ant_init_hw_config(btcoexist, wifi_only)
++#define	ex_halbtc8723d1ant_init_coex_dm(btcoexist)
++#define	ex_halbtc8723d1ant_ips_notify(btcoexist, type)
++#define	ex_halbtc8723d1ant_lps_notify(btcoexist, type)
++#define	ex_halbtc8723d1ant_scan_notify(btcoexist, type)
++#define	ex_halbtc8723d1ant_connect_notify(btcoexist, type)
++#define	ex_halbtc8723d1ant_media_status_notify(btcoexist, type)
++#define	ex_halbtc8723d1ant_specific_packet_notify(btcoexist, type)
++#define	ex_halbtc8723d1ant_bt_info_notify(btcoexist, tmp_buf, length)
++#define ex_halbtc8723d1ant_wl_fwdbginfo_notify(btcoexist, tmp_buf, length)
++#define	ex_halbtc8723d1ant_rx_rate_change_notify(btcoexist, is_data_frame, btc_rate_id)
++#define	ex_halbtc8723d1ant_rf_status_notify(btcoexist, type)
++#define	ex_halbtc8723d1ant_halt_notify(btcoexist)
++#define	ex_halbtc8723d1ant_pnp_notify(btcoexist, pnp_state)
++#define	ex_halbtc8723d1ant_coex_dm_reset(btcoexist)
++#define	ex_halbtc8723d1ant_periodical(btcoexist)
++#define	ex_halbtc8723d1ant_display_coex_info(btcoexist)
++#define	ex_halbtc8723d1ant_set_antenna_notify(btcoexist, type)
++#define	ex_halbtc8723d1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds)
++#define	ex_halbtc8723d1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds)
++#define	ex_halbtc8723d1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds)
++#define	ex_halbtc8723d1ant_display_ant_detection(btcoexist)
++#endif
++
++#endif
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/halbtc8723d2ant.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/halbtc8723d2ant.c
+new file mode 100644
+index 000000000..b4c1720a9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/halbtc8723d2ant.c
+@@ -0,0 +1,6236 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/* ************************************************************
++ * Description:
++ *
++ * This file is for RTL8723D Co-exist mechanism
++ *
++ * History
++ * 2012/11/15 Cosa first check in.
++ *
++ * ************************************************************ */
++
++/* ************************************************************
++ * include files
++ * ************************************************************ */
++#include "mp_precomp.h"
++
++#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
++
++#if (RTL8723D_SUPPORT == 1)
++/* ************************************************************
++ * Global variables, these are static variables
++ * ************************************************************ */
++static u8	*trace_buf = &gl_btc_trace_buf[0];
++static struct  coex_dm_8723d_2ant		glcoex_dm_8723d_2ant;
++static struct  coex_dm_8723d_2ant	*coex_dm = &glcoex_dm_8723d_2ant;
++static struct  coex_sta_8723d_2ant		glcoex_sta_8723d_2ant;
++static struct  coex_sta_8723d_2ant	*coex_sta = &glcoex_sta_8723d_2ant;
++static struct  psdscan_sta_8723d_2ant	gl_psd_scan_8723d_2ant;
++static struct  psdscan_sta_8723d_2ant *psd_scan = &gl_psd_scan_8723d_2ant;
++
++const char *const glbt_info_src_8723d_2ant[] = {
++	"BT Info[wifi fw]",
++	"BT Info[bt rsp]",
++	"BT Info[bt auto report]",
++};
++
++u32	glcoex_ver_date_8723d_2ant = 20200103;
++u32	glcoex_ver_8723d_2ant = 0x35;
++u32	glcoex_ver_btdesired_8723d_2ant = 0x35;
++
++static
++u8 halbtc8723d2ant_bt_rssi_state(IN struct btc_coexist *btcoexist,
++	u8 *ppre_bt_rssi_state, u8 level_num,
++	u8 rssi_thresh, u8 rssi_thresh1)
++{
++	s32			bt_rssi = 0;
++	u8			bt_rssi_state = *ppre_bt_rssi_state;
++
++	bt_rssi = coex_sta->bt_rssi;
++
++	if (level_num == 2) {
++		if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
++		    (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
++			if (bt_rssi >= (rssi_thresh +
++					BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
++				bt_rssi_state = BTC_RSSI_STATE_HIGH;
++			else
++				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
++		} else {
++			if (bt_rssi < rssi_thresh)
++				bt_rssi_state = BTC_RSSI_STATE_LOW;
++			else
++				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
++		}
++	} else if (level_num == 3) {
++		if (rssi_thresh > rssi_thresh1) {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], BT Rssi thresh error!!\n");
++			BTC_TRACE(trace_buf);
++			return *ppre_bt_rssi_state;
++		}
++
++		if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
++		    (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
++			if (bt_rssi >= (rssi_thresh +
++					BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
++				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
++			else
++				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
++		} else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
++			(*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
++			if (bt_rssi >= (rssi_thresh1 +
++					BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
++				bt_rssi_state = BTC_RSSI_STATE_HIGH;
++			else if (bt_rssi < rssi_thresh)
++				bt_rssi_state = BTC_RSSI_STATE_LOW;
++			else
++				bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
++		} else {
++			if (bt_rssi < rssi_thresh1)
++				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
++			else
++				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
++		}
++	}
++
++	*ppre_bt_rssi_state = bt_rssi_state;
++
++	return bt_rssi_state;
++}
++
++static
++u8 halbtc8723d2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
++	   IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh,
++				   IN u8 rssi_thresh1)
++{
++	s32			wifi_rssi = 0;
++	u8			wifi_rssi_state = *pprewifi_rssi_state;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
++
++	if (level_num == 2) {
++		if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
++		    (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
++			if (wifi_rssi >= (rssi_thresh +
++					  BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
++				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
++			else
++				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
++		} else {
++			if (wifi_rssi < rssi_thresh)
++				wifi_rssi_state = BTC_RSSI_STATE_LOW;
++			else
++				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
++		}
++	} else if (level_num == 3) {
++		if (rssi_thresh > rssi_thresh1) {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], wifi RSSI thresh error!!\n");
++			BTC_TRACE(trace_buf);
++			return *pprewifi_rssi_state;
++		}
++
++		if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
++		    (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
++			if (wifi_rssi >= (rssi_thresh +
++					  BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
++				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
++			else
++				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
++		} else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
++			(*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
++			if (wifi_rssi >= (rssi_thresh1 +
++					  BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
++				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
++			else if (wifi_rssi < rssi_thresh)
++				wifi_rssi_state = BTC_RSSI_STATE_LOW;
++			else
++				wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
++		} else {
++			if (wifi_rssi < rssi_thresh1)
++				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
++			else
++				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
++		}
++	}
++
++	*pprewifi_rssi_state = wifi_rssi_state;
++
++	return wifi_rssi_state;
++}
++
++static
++void halbtc8723d2ant_coex_switch_threshold(IN struct btc_coexist *btcoexist,
++		IN u8 isolation_measuared)
++{
++	s8	interference_wl_tx = 0, interference_bt_tx = 0;
++
++
++	interference_wl_tx = BT_8723D_2ANT_WIFI_MAX_TX_POWER -
++			     isolation_measuared;
++	interference_bt_tx = BT_8723D_2ANT_BT_MAX_TX_POWER -
++			     isolation_measuared;
++
++
++
++	coex_sta->wifi_coex_thres		 = BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1;
++	coex_sta->wifi_coex_thres2	 = BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES2;
++
++	coex_sta->bt_coex_thres		 = BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1;
++	coex_sta->bt_coex_thres2		 = BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES2;
++}
++
++static void
++halbtc8723d2ant_limited_tx(struct btc_coexist *btcoexist, boolean force_exec,
++			   boolean tx_limit_en,  boolean ampdu_limit_en)
++{
++	boolean wifi_under_b_mode = FALSE;
++	u32	wifi_link_status = 0, num_of_wifi_link = 0;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
++			   &wifi_link_status);
++
++	num_of_wifi_link = wifi_link_status >> 16;
++
++	/* Force Max Tx retry limit = 8*/
++	if (!coex_sta->wl_tx_limit_en) {
++		coex_sta->wl_0x430_backup =
++			btcoexist->btc_read_4byte(btcoexist, 0x430);
++		coex_sta->wl_0x434_backup =
++			btcoexist->btc_read_4byte(btcoexist, 0x434);
++		coex_sta->wl_0x42a_backup =
++			btcoexist->btc_read_2byte(btcoexist, 0x42a);
++	}
++
++	if (!coex_sta->wl_ampdu_limit_en)
++		coex_sta->wl_0x456_backup = btcoexist->btc_read_1byte(btcoexist,
++								      0x456);
++
++	if (!force_exec && tx_limit_en == coex_sta->wl_tx_limit_en &&
++	    ampdu_limit_en == coex_sta->wl_ampdu_limit_en)
++		return;
++
++	coex_sta->wl_tx_limit_en = tx_limit_en;
++	coex_sta->wl_ampdu_limit_en = ampdu_limit_en;
++
++	if (tx_limit_en) {
++		/* Set BT polluted packet on for Tx rate adaptive not
++		 * including Tx retry break by PTA, 0x45c[19] =1
++		 *
++		 * Set queue life time to avoid can't reach tx retry limit
++		 * if tx is always break by GNT_BT.
++		 */
++		if ((wifi_link_status & WIFI_STA_CONNECTED) &&
++		     num_of_wifi_link == 1) {
++			btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1);
++			btcoexist->btc_write_1byte_bitmask(btcoexist, 0x426, 0xf, 0xf);
++		}
++
++		/* Max Tx retry limit = 8*/
++		btcoexist->btc_write_2byte(btcoexist, 0x42a, 0x0808);
++
++		/* AMPDU duration limit*/
++		btcoexist->btc_write_1byte(btcoexist, 0x456, 0x20);
++
++		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
++				   &wifi_under_b_mode);
++
++		/* Auto rate fallback step within 8 retry*/
++		if (wifi_under_b_mode) {
++			btcoexist->btc_write_4byte(btcoexist, 0x430, 0x1000000);
++			btcoexist->btc_write_4byte(btcoexist, 0x434, 0x1010101);
++		} else {
++			btcoexist->btc_write_4byte(btcoexist, 0x430, 0x1000000);
++			btcoexist->btc_write_4byte(btcoexist, 0x434, 0x4030201);
++		}
++	} else {
++		/* Set BT polluted packet on for Tx rate adaptive not
++		 *including Tx retry break by PTA, 0x45c[19] =1
++		 */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x0);
++
++		/* Set queue life time to avoid can't reach tx retry limit
++		 * if tx is always break by GNT_BT.
++		 */
++		if (num_of_wifi_link  == 1)
++			btcoexist->btc_write_1byte_bitmask(btcoexist, 0x426, 0xf, 0x0);
++
++		/* Recovery Max Tx retry limit*/
++		btcoexist->btc_write_2byte(btcoexist, 0x42a,
++					   coex_sta->wl_0x42a_backup);
++		btcoexist->btc_write_4byte(btcoexist, 0x430,
++					   coex_sta->wl_0x430_backup);
++		btcoexist->btc_write_4byte(btcoexist, 0x434,
++					   coex_sta->wl_0x434_backup);
++	}
++
++	if (ampdu_limit_en)
++		btcoexist->btc_write_1byte(btcoexist, 0x456, 0x20);
++	else
++		btcoexist->btc_write_1byte(btcoexist, 0x456,
++					   coex_sta->wl_0x456_backup);
++}
++
++static void
++halbtc8723d2ant_limited_rx(struct btc_coexist *btcoexist, boolean force_exec,
++			   boolean rej_ap_agg_pkt, boolean bt_ctrl_agg_buf_size,
++			   u8 agg_buf_size)
++{
++#if 0
++	boolean reject_rx_agg = rej_ap_agg_pkt;
++	boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
++	u8 rx_agg_size = agg_buf_size;
++
++	if (!force_exec &&
++	    bt_ctrl_agg_buf_size == coex_sta->wl_rxagg_limit_en &&
++	    agg_buf_size == coex_sta->wl_rxagg_size)
++		return;
++
++	coex_sta->wl_rxagg_limit_en = bt_ctrl_agg_buf_size;
++	coex_sta->wl_rxagg_size = agg_buf_size;
++
++	/*btc->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
++	 *&reject_rx_agg);
++	 */
++	/* decide BT control aggregation buf size or not */
++	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
++			   &bt_ctrl_rx_agg_size);
++	/* aggregation buf size, only work
++	 * when BT control Rx aggregation size
++	 */
++	btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
++	/* real update aggregation setting */
++	btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
++#endif
++}
++
++static void
++halbtc8723d2ant_set_tdma_timer_base(struct btc_coexist *btc, u8 type)
++{
++	u16 tbtt_interval = 100;
++	u8 h2c_para[2] = {0xb, 0x1};
++
++	btc->btc_get(btc, BTC_GET_U2_BEACON_PERIOD, &tbtt_interval);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		 "[BTCoex], tbtt_interval = %d\n", tbtt_interval);
++	BTC_TRACE(trace_buf);
++
++	/* Add for JIRA coex-256 */
++	if (type == 3 && tbtt_interval < 120) { /* 4-slot  */
++		if (coex_sta->tdma_timer_base == 3)
++			return;
++
++		h2c_para[1] = 0xc1; /* 4-slot */
++		coex_sta->tdma_timer_base = 3;
++	} else if (tbtt_interval < 80 && tbtt_interval > 0) {
++		if (coex_sta->tdma_timer_base == 2)
++			return;
++		h2c_para[1] = (100 / tbtt_interval);
++
++		if (100 % tbtt_interval != 0)
++			h2c_para[1] = h2c_para[1] + 1;
++
++		h2c_para[1] = h2c_para[1] & 0x3f;
++		coex_sta->tdma_timer_base = 2;
++	} else if (tbtt_interval >= 180) {
++		if (coex_sta->tdma_timer_base == 1)
++			return;
++		h2c_para[1] = (tbtt_interval / 100);
++
++		if (tbtt_interval % 100 <= 80)
++			h2c_para[1] = h2c_para[1] - 1;
++
++		h2c_para[1] = h2c_para[1] & 0x3f;
++		h2c_para[1] = h2c_para[1] | 0x80;
++		coex_sta->tdma_timer_base = 1;
++	} else {
++		if (coex_sta->tdma_timer_base == 0)
++			return;
++		h2c_para[1] = 0x1;
++		coex_sta->tdma_timer_base = 0;
++	}
++
++	btc->btc_fill_h2c(btc, 0x69, 2, h2c_para);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		 "[BTCoex], %s() h2c_0x69 = 0x%x\n", __func__, h2c_para[1]);
++	BTC_TRACE(trace_buf);
++
++#if 0
++	/* no 5ms_wl_slot_extend for 4-slot mode  */
++	if (coex_sta->tdma_timer_base == 3)
++		halbtc8822b2ant_ccklock_action(btc);
++#endif
++}
++
++
++static
++void halbtc8723d2ant_set_fw_low_penalty_ra(IN struct btc_coexist
++		*btcoexist, IN boolean low_penalty_ra)
++{
++	u8 h2c_parameter[6] = {0};
++
++	h2c_parameter[0] = 0x6;	/* op_code, 0x6= Retry_Penalty */
++
++	if (low_penalty_ra) {
++		h2c_parameter[1] |= BIT(0);
++		h2c_parameter[2] =
++			0x00;  /* normal rate except MCS7/6/5, OFDM54/48/36 */
++		h2c_parameter[3] = 0xf7;  /* MCS7 or OFDM54 */
++		h2c_parameter[4] = 0xf8;  /* MCS6 or OFDM48 */
++		h2c_parameter[5] = 0xf9;	/* MCS5 or OFDM36	 */
++	}
++
++	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
++}
++
++static
++void halbtc8723d2ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
++				    IN boolean force_exec,
++				    IN boolean low_penalty_ra)
++{
++	coex_dm->cur_low_penalty_ra = low_penalty_ra;
++
++	if (!force_exec) {
++		if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
++			return;
++	}
++
++	halbtc8723d2ant_set_fw_low_penalty_ra(btcoexist,
++					      coex_dm->cur_low_penalty_ra);
++
++#if 0
++	if (low_penalty_ra)
++		btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15);
++	else
++		btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0);
++#endif
++	coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
++}
++
++static
++void halbtc8723d2ant_query_bt_info(IN struct btc_coexist *btcoexist)
++{
++	u8			h2c_parameter[1] = {0};
++
++
++	h2c_parameter[0] |= BIT(0);	/* trigger */
++
++	btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
++}
++
++static
++boolean halbtc8723d2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
++{
++	u32 reg_hp_txrx, reg_lp_txrx, u32tmp, cnt_bt_all;
++	u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
++	static u8	num_of_bt_counter_chk = 0, cnt_overhead = 0,
++		cnt_autoslot_hang = 0;
++	static u32 cnt_bt_pre = 0;
++	boolean is_run_coex = FALSE;
++
++	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++
++	reg_hp_txrx = 0x770;
++	reg_lp_txrx = 0x774;
++
++	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
++	reg_hp_tx = u32tmp & MASKLWORD;
++	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
++
++	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
++	reg_lp_tx = u32tmp & MASKLWORD;
++	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
++
++	coex_sta->high_priority_tx = reg_hp_tx;
++	coex_sta->high_priority_rx = reg_hp_rx;
++	coex_sta->low_priority_tx = reg_lp_tx;
++	coex_sta->low_priority_rx = reg_lp_rx;
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
++		    reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
++
++	BTC_TRACE(trace_buf);
++	
++	/* reset counter */
++	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
++	
++	if (coex_sta->under_lps || coex_sta->under_ips ||
++	     (coex_sta->high_priority_tx == 65535 &&
++	      coex_sta->high_priority_rx == 65535 &&
++	      coex_sta->low_priority_tx == 65535 &&
++	      coex_sta->low_priority_rx == 65535))
++		coex_sta->bt_ctr_ok = FALSE;
++	else
++		coex_sta->bt_ctr_ok = TRUE;
++	
++	if (!coex_sta->bt_ctr_ok)
++		return FALSE;
++
++	if (coex_dm->bt_status == BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE) {
++		if (coex_sta->high_priority_rx >= 15) {
++			if (cnt_overhead < 3)
++				cnt_overhead++;
++
++			if (cnt_overhead == 3)
++				coex_sta->is_hipri_rx_overhead = TRUE;
++		} else {
++			if (cnt_overhead > 0)
++				cnt_overhead--;
++
++			if (cnt_overhead == 0)
++				coex_sta->is_hipri_rx_overhead = FALSE;
++		}
++	} else {
++		coex_sta->is_hipri_rx_overhead = FALSE;
++	}
++
++	if (coex_sta->low_priority_tx > 1050  &&
++	    !coex_sta->c2h_bt_inquiry_page)
++		coex_sta->pop_event_cnt++;
++
++	if (coex_sta->is_tdma_btautoslot) {
++		if (coex_sta->low_priority_tx >= 1300 &&
++		    coex_sta->low_priority_rx <= 150) {
++			if (cnt_autoslot_hang >= 2) {
++				coex_sta->is_tdma_btautoslot_hang = TRUE;
++				cnt_autoslot_hang = 2;
++			} else
++				cnt_autoslot_hang++;
++		} else {
++			if (cnt_autoslot_hang == 0)	{
++				coex_sta->is_tdma_btautoslot_hang = FALSE;
++				cnt_autoslot_hang = 0;
++			} else
++				cnt_autoslot_hang--;
++		}
++	}
++
++	if (coex_sta->sco_exist) {
++		if (coex_sta->high_priority_tx >= 400 &&
++		    coex_sta->high_priority_rx >= 400)
++			coex_sta->is_esco_mode = FALSE;
++		else
++			coex_sta->is_esco_mode = TRUE;
++	}
++
++	if (bt_link_info->hid_only) {
++		if (coex_sta->low_priority_tx > 50)
++			coex_sta->is_hid_low_pri_tx_overhead = true;
++		else
++			coex_sta->is_hid_low_pri_tx_overhead = false;
++	}
++
++	if (!coex_sta->bt_disabled) {
++		if (coex_sta->high_priority_tx == 0 &&
++		    coex_sta->high_priority_rx == 0 &&
++		    coex_sta->low_priority_tx == 0 &&
++		    coex_sta->low_priority_rx == 0) {
++			num_of_bt_counter_chk++;
++			if (num_of_bt_counter_chk >= 3) {
++				halbtc8723d2ant_query_bt_info(btcoexist);
++				num_of_bt_counter_chk = 0;
++			}
++		}
++	}
++
++	cnt_bt_all = coex_sta->high_priority_tx +
++		     coex_sta->high_priority_rx +
++		     coex_sta->low_priority_tx +
++		     coex_sta->low_priority_rx;
++
++	if ((cnt_bt_pre > (cnt_bt_all + 50) ||
++	    cnt_bt_all > (cnt_bt_pre + 50)) &&
++	    coex_dm->bt_status == BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE)
++		is_run_coex = TRUE;
++
++	cnt_bt_pre = cnt_bt_all;
++
++	return is_run_coex;
++}
++
++static
++void halbtc8723d2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
++{
++	s32 wifi_rssi = 0;
++	boolean wifi_busy = FALSE, wifi_under_b_mode = FALSE,
++			wifi_scan = FALSE, wifi_connected = FALSE;
++	boolean bt_idle = FALSE, wl_idle = FALSE, is_cck_deadlock = FALSE;
++	static u8 cck_lock_counter = 0, wl_noisy_count0 = 0,
++		  wl_noisy_count1 = 3, wl_noisy_count2 = 0;
++	u32 total_cnt, reg_val1, reg_val2, cnt_cck;
++	u32 cnt_crcok = 0, cnt_crcerr = 0;
++	static u8 cnt = 0, cnt_cal = 0, cnt_ccklocking = 0;
++	u8	h2c_parameter[1] = {0};
++	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++
++
++	/*send h2c to query WL FW dbg info	*/
++	if (coex_dm->cur_ps_tdma_on) {
++		h2c_parameter[0] = 0x8;
++		btcoexist->btc_fill_h2c(btcoexist, 0x69, 1, h2c_parameter);
++	}
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
++			   &wifi_under_b_mode);
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
++
++	coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter(
++						btcoexist,
++						PHYDM_INFO_CRC32_OK_CCK);
++	coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter(
++						btcoexist,
++						PHYDM_INFO_CRC32_OK_LEGACY);
++	coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter(
++						btcoexist,
++						PHYDM_INFO_CRC32_OK_HT);
++	coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter(
++						btcoexist,
++						PHYDM_INFO_CRC32_OK_VHT);
++
++	coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter(
++						btcoexist, PHYDM_INFO_CRC32_ERROR_CCK);
++	coex_sta->crc_err_11g =  btcoexist->btc_phydm_query_PHY_counter(
++						btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY);
++	coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter(
++						btcoexist, PHYDM_INFO_CRC32_ERROR_HT);
++	coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter(
++						btcoexist,
++						PHYDM_INFO_CRC32_ERROR_VHT);
++
++	cnt_crcok =  coex_sta->crc_ok_cck + coex_sta->crc_ok_11g
++				+ coex_sta->crc_ok_11n
++				+ coex_sta->crc_ok_11n_vht;
++
++	cnt_crcerr =  coex_sta->crc_err_cck + coex_sta->crc_err_11g
++				+ coex_sta->crc_err_11n
++				+ coex_sta->crc_err_11n_vht;
++
++
++	if ((wifi_busy) && (cnt_crcerr != 0)) {
++		if (cnt_cal == 0)
++			coex_sta->cnt_crcok_max_in_10s = 0;
++
++		cnt_cal++;
++
++		if (cnt_crcok > coex_sta->cnt_crcok_max_in_10s)
++			coex_sta->cnt_crcok_max_in_10s = cnt_crcok;
++
++		if (cnt_cal == 5)
++			cnt_cal = 0;
++
++		coex_sta->now_crc_ratio = cnt_crcok/cnt_crcerr;
++
++		if (cnt == 0)
++			coex_sta->acc_crc_ratio = coex_sta->now_crc_ratio;
++		else
++			coex_sta->acc_crc_ratio = (coex_sta->acc_crc_ratio * 7 +
++				coex_sta->now_crc_ratio * 3)/10;
++
++		if (cnt >= 10)
++			cnt = 0;
++		else
++			cnt++;
++	}
++
++	/*	CCK lock identification	*/
++	if (coex_sta->cck_lock)
++		cnt_ccklocking++;
++	else if (cnt_ccklocking != 0)
++		cnt_ccklocking--;
++
++	if (cnt_ccklocking >= 3) {
++		cnt_ccklocking = 3;
++		coex_sta->cck_lock_ever = TRUE;
++	}
++
++	/* WiFi environment noisy identification */
++	cnt_cck = coex_sta->crc_ok_cck + coex_sta->crc_err_cck;
++
++	if ((!wifi_busy) && (!coex_sta->cck_lock)) {
++		if (cnt_cck > 250) {
++			if (wl_noisy_count2 < 3)
++				wl_noisy_count2++;
++
++			if (wl_noisy_count2 == 3) {
++				wl_noisy_count0 = 0;
++				wl_noisy_count1 = 0;
++			}
++
++		} else if (cnt_cck < 50) {
++			if (wl_noisy_count0 < 3)
++				wl_noisy_count0++;
++
++			if (wl_noisy_count0 == 3) {
++				wl_noisy_count1 = 0;
++				wl_noisy_count2 = 0;
++			}
++
++		} else {
++			if (wl_noisy_count1 < 3)
++				wl_noisy_count1++;
++
++			if (wl_noisy_count1 == 3) {
++				wl_noisy_count0 = 0;
++				wl_noisy_count2 = 0;
++			}
++		}
++
++		if (wl_noisy_count2 == 3)
++			coex_sta->wl_noisy_level = 2;
++		else if (wl_noisy_count1 == 3)
++			coex_sta->wl_noisy_level = 1;
++		else
++			coex_sta->wl_noisy_level = 0;
++	}
++}
++
++static
++void halbtc8723d2ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
++{
++	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++	boolean		bt_hs_on = FALSE, bt_busy = FALSE;
++	u32		val = 0, wifi_link_status = 0, num_of_wifi_link = 0;
++	static u8		pre_num_of_profile, cur_num_of_profile, cnt;
++	static boolean	pre_ble_scan_en;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
++			   &wifi_link_status);
++
++	num_of_wifi_link = wifi_link_status >> 16;
++
++	if (coex_sta->is_ble_scan_en && !pre_ble_scan_en) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n");
++				BTC_TRACE(trace_buf);
++		coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt(btcoexist);
++
++		if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1)
++			coex_sta->bt_ble_scan_para[0]  =
++				btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x1);
++		if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2)
++			coex_sta->bt_ble_scan_para[1]  =
++				btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x2);
++		if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4)
++			coex_sta->bt_ble_scan_para[2]  =
++				btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x4);
++	}
++
++	pre_ble_scan_en = coex_sta->is_ble_scan_en;
++	coex_sta->num_of_profile = 0;
++
++	/* set link exist status */
++	if (!(coex_sta->bt_info & BT_INFO_8723D_2ANT_B_CONNECTION)) {
++		coex_sta->bt_link_exist = FALSE;
++		coex_sta->pan_exist = FALSE;
++		coex_sta->a2dp_exist = FALSE;
++		coex_sta->hid_exist = FALSE;
++		coex_sta->sco_exist = FALSE;
++	} else {	/* connection exists */
++		coex_sta->bt_link_exist = TRUE;
++		if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_FTP) {
++			coex_sta->pan_exist = TRUE;
++			coex_sta->num_of_profile++;
++		} else
++			coex_sta->pan_exist = FALSE;
++
++		if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_A2DP) {
++			coex_sta->a2dp_exist = TRUE;
++			coex_sta->num_of_profile++;
++		} else
++			coex_sta->a2dp_exist = FALSE;
++
++		if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_HID) {
++			coex_sta->hid_exist = TRUE;
++			coex_sta->num_of_profile++;
++		} else
++			coex_sta->hid_exist = FALSE;
++
++		if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_ESCO) {
++			coex_sta->sco_exist = TRUE;
++			coex_sta->num_of_profile++;
++		} else
++			coex_sta->sco_exist = FALSE;
++
++	}
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
++
++	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
++	bt_link_info->sco_exist = coex_sta->sco_exist;
++	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
++	bt_link_info->pan_exist = coex_sta->pan_exist;
++	bt_link_info->hid_exist = coex_sta->hid_exist;
++	bt_link_info->acl_busy = coex_sta->acl_busy;
++
++	/* work around for HS mode. */
++	if (bt_hs_on) {
++		bt_link_info->pan_exist = TRUE;
++		bt_link_info->bt_link_exist = TRUE;
++	}
++
++	/* check if Sco only */
++	if (bt_link_info->sco_exist &&
++	    !bt_link_info->a2dp_exist &&
++	    !bt_link_info->pan_exist &&
++	    !bt_link_info->hid_exist)
++		bt_link_info->sco_only = TRUE;
++	else
++		bt_link_info->sco_only = FALSE;
++
++	/* check if A2dp only */
++	if (!bt_link_info->sco_exist &&
++	    bt_link_info->a2dp_exist &&
++	    !bt_link_info->pan_exist &&
++	    !bt_link_info->hid_exist)
++		bt_link_info->a2dp_only = TRUE;
++	else
++		bt_link_info->a2dp_only = FALSE;
++
++	/* check if Pan only */
++	if (!bt_link_info->sco_exist &&
++	    !bt_link_info->a2dp_exist &&
++	    bt_link_info->pan_exist &&
++	    !bt_link_info->hid_exist)
++		bt_link_info->pan_only = TRUE;
++	else
++		bt_link_info->pan_only = FALSE;
++
++	/* check if Hid only */
++	if (!bt_link_info->sco_exist &&
++	    !bt_link_info->a2dp_exist &&
++	    !bt_link_info->pan_exist &&
++	    bt_link_info->hid_exist)
++		bt_link_info->hid_only = TRUE;
++	else
++		bt_link_info->hid_only = FALSE;
++
++	if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_INQ_PAGE) {
++		coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_INQ_PAGE;
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], BtInfoNotify(), BT Inq/page!!!\n");
++	} else if (!(coex_sta->bt_info & BT_INFO_8723D_2ANT_B_CONNECTION)) {
++		coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
++	} else if (coex_sta->bt_info == BT_INFO_8723D_2ANT_B_CONNECTION) {
++		/* connection exists but no busy */
++		coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE;
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
++	} else if (((coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_ESCO) ||
++		    (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_BUSY)) &&
++		   (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_ACL_BUSY)) {
++		coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY;
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n");
++	} else if ((coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_ESCO) ||
++		   (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_BUSY)) {
++		coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_SCO_BUSY;
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
++	} else if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_ACL_BUSY) {
++		coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_ACL_BUSY;
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
++	} else {
++		coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_MAX;
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
++	}
++
++	BTC_TRACE(trace_buf);
++
++	if ((BT_8723D_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
++	    (BT_8723D_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
++	    (BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
++		bt_busy = TRUE;
++	else
++		bt_busy = FALSE;
++
++	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
++
++	cur_num_of_profile = coex_sta->num_of_profile;
++
++	if (cur_num_of_profile != pre_num_of_profile)
++		cnt = 2;
++
++	if (bt_link_info->a2dp_exist) {
++
++		if (((coex_sta->bt_a2dp_vendor_id == 0) &&
++			(coex_sta->bt_a2dp_device_name == 0)) ||
++			(cur_num_of_profile != pre_num_of_profile)) {
++
++			btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_DEVICE_INFO, &val);
++
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], BtInfoNotify(), get BT DEVICE_INFO = %x\n",
++				    val);
++			BTC_TRACE(trace_buf);
++
++			coex_sta->bt_a2dp_vendor_id = (u8)(val & 0xff);
++			coex_sta->bt_a2dp_device_name = (val & 0xffffff00) >> 8;
++		}
++
++		if (((coex_sta->legacy_forbidden_slot == 0) &&
++			(coex_sta->le_forbidden_slot == 0)) ||
++			(cur_num_of_profile != pre_num_of_profile) ||
++			(cnt > 0)) {
++
++			if (cnt > 0)
++				cnt--;
++
++			btcoexist->btc_get(btcoexist,
++					   BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL,
++					   &val);
++
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], BtInfoNotify(), get BT FORBIDDEN_SLOT_VAL = %x, cnt = %d\n",
++				    val, cnt);
++			BTC_TRACE(trace_buf);
++
++			coex_sta->legacy_forbidden_slot = (u16)(val & 0xffff);
++			coex_sta->le_forbidden_slot = (u16)((val & 0xffff0000) >> 16);
++		}
++	}
++
++	pre_num_of_profile = coex_sta->num_of_profile;
++
++	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
++		return;
++
++	if (num_of_wifi_link == 0 ||
++	    coex_dm->bt_status == BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE) {
++		halbtc8723d2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_limited_tx(btcoexist, NORMAL_EXEC, FALSE,
++					   FALSE);
++		halbtc8723d2ant_limited_rx(btcoexist, NM_EXCU, FALSE, TRUE, 64);
++	} else if (wifi_link_status & WIFI_P2P_GO_CONNECTED ||
++		    wifi_link_status & WIFI_P2P_GC_CONNECTED) {
++		halbtc8723d2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, TRUE);
++		halbtc8723d2ant_limited_tx(btcoexist, NM_EXCU, TRUE, TRUE);
++		halbtc8723d2ant_limited_rx(btcoexist, NM_EXCU, FALSE, TRUE, 16);
++	} else {
++		halbtc8723d2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, TRUE);
++
++		if (bt_link_info->hid_exist || coex_sta->hid_pair_cnt > 0 ||
++		    bt_link_info->sco_exist) {
++			halbtc8723d2ant_limited_tx(btcoexist, NM_EXCU, TRUE,
++						   TRUE);
++			halbtc8723d2ant_limited_rx(btcoexist, NM_EXCU, FALSE,
++						   TRUE, 16);
++		} else {
++			halbtc8723d2ant_limited_tx(btcoexist, NM_EXCU, TRUE,
++						   FALSE);
++			halbtc8723d2ant_limited_rx(btcoexist, NM_EXCU, FALSE,
++						   TRUE, 64);
++		}
++	}
++}
++
++static
++void halbtc8723d2ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist,
++		IN u8 type)
++{
++	u8			h2c_parameter[3] = {0};
++	u32			wifi_bw;
++	u8			wifi_central_chnl;
++
++	/* only 2.4G we need to inform bt the chnl mask */
++	btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
++			   &wifi_central_chnl);
++	if (type == BTC_MEDIA_CONNECT && wifi_central_chnl <= 14) {
++		/* enable BT AFH skip WL channel for 8723d
++		 * because BT Rx LO interference
++		 * h2c_parameter[0] = 0x0;
++		 */
++		h2c_parameter[0] = 0x1;
++		h2c_parameter[1] = wifi_central_chnl;
++		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
++		if (wifi_bw == BTC_WIFI_BW_HT40)
++			h2c_parameter[2] = 0x30;
++		else
++			h2c_parameter[2] = 0x20;
++	}
++
++	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
++	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
++	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
++
++	btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
++
++}
++
++static
++void halbtc8723d2ant_write_score_board(
++	IN	struct  btc_coexist		*btcoexist,
++	IN	u16				bitpos,
++	IN	boolean		state
++)
++{
++
++	static u16 originalval = 0x8002, preval = 0x0;
++
++	if (state)
++		originalval = originalval | bitpos;
++	else
++		originalval = originalval & (~bitpos);
++
++	coex_sta->score_board_WB = originalval;
++
++	if (originalval != preval) {
++		preval = originalval;
++		btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
++	} else {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], halbtc8723d2ant_write_score_board: return for nochange\n");
++		BTC_TRACE(trace_buf);
++	}
++}
++
++static
++void halbtc8723d2ant_read_score_board(
++	IN	struct  btc_coexist		*btcoexist,
++	IN   u16				*score_board_val
++)
++{
++	*score_board_val = (btcoexist->btc_read_2byte(btcoexist, 0xaa)) &
++				0x7fff;
++}
++
++static
++void halbtc8723d2ant_post_state_to_bt(
++	IN struct  btc_coexist	*btcoexist,
++	IN u16		type,
++	IN boolean	state
++)
++{
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], %s: type = %d, state =%d\n",
++		    __func__, type, state);
++	BTC_TRACE(trace_buf);
++
++	halbtc8723d2ant_write_score_board(btcoexist, (u16) type, state);
++}
++
++static
++void halbtc8723d2ant_adjust_wl_tx_power(IN struct btc_coexist *btcoexist,
++			      IN boolean force_exec, IN u8 fw_dac_swing_lvl)
++{
++
++	coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
++
++	if (!force_exec) {
++		if (coex_dm->pre_fw_dac_swing_lvl ==
++		    coex_dm->cur_fw_dac_swing_lvl)
++			return;
++	}
++
++	btcoexist->btc_write_1byte(btcoexist, 0x883, fw_dac_swing_lvl);
++
++	coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
++}
++
++static
++void halbtc8723d2ant_adjust_bt_tx_power(IN struct btc_coexist *btcoexist,
++				IN boolean force_exec, IN u8 dec_bt_pwr_lvl)
++{
++	u8	h2c_parameter[1] = {0};
++
++	coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl;
++
++	if (!force_exec) {
++		if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl)
++			return;
++	}
++
++	h2c_parameter[0] = 0 - dec_bt_pwr_lvl;
++
++	btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
++
++	coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl;
++}
++
++static
++void halbtc8723d2ant_adjust_wl_rx_gain(IN struct btc_coexist *btcoexist,
++			       IN boolean force_exec, IN boolean agc_table_en)
++{
++	u32 rx_gain_value_enable[] = {0xec120101, 0xeb130101, 0xce140101,
++				      0xcd150101, 0xcc160101, 0xcb170101,
++				      0xca180101, 0x8d190101, 0x8c1a0101,
++				      0x8b1b0101, 0x4f1c0101, 0x4e1d0101,
++				      0x4d1e0101, 0x4c1f0101, 0x0e200101,
++				      0x0d210101, 0x0c220101, 0x0b230101,
++				      0xcf240001, 0xce250001, 0xcd260001,
++				      0xcc270001, 0x8f280001, 0xffffffff};
++	u32 rx_gain_value_disable[] = {0xec120101, 0xeb130101, 0xea140101,
++				       0xe9150101, 0xe8160101, 0xe7170101,
++				       0xe6180101, 0xe5190101, 0xe41a0101,
++				       0xe31b0101, 0xe21c0101, 0xe11d0101,
++				       0xe01e0101, 0x861f0101, 0x85200101,
++				       0x84210101, 0x83220101, 0x82230101,
++				       0x81240101, 0x80250101, 0x44260101,
++				       0x43270101, 0x42280101, 0xffffffff};
++
++	u8 i;
++
++	coex_dm->cur_agc_table_en = agc_table_en;
++
++	if (!force_exec) {
++		if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
++			return;
++	}
++
++	if (agc_table_en) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], BB Agc Table On!\n");
++		BTC_TRACE(trace_buf);
++
++		for (i = 0; i < ARRAY_SIZE(rx_gain_value_enable); i++) {
++			if (rx_gain_value_enable[i] == 0xffffffff)
++				break;
++
++			btcoexist->btc_write_4byte(btcoexist,
++				0xc78, rx_gain_value_enable[i]);
++		}
++
++	} else {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], BB Agc Table Off!\n");
++		BTC_TRACE(trace_buf);
++
++		for (i = 0; i < ARRAY_SIZE(rx_gain_value_disable); i++) {
++			if (rx_gain_value_disable[i] == 0xffffffff)
++				break;
++
++			btcoexist->btc_write_4byte(btcoexist,
++				0xc78, rx_gain_value_disable[i]);
++		}
++	}
++
++	coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
++}
++
++static
++void halbtc8723d2ant_adjust_bt_rx_gain(IN struct btc_coexist *btcoexist,
++			       IN boolean force_exec, IN boolean rx_gain_en)
++{
++	u8 lna_lvl = 1;
++
++	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL,
++			   &lna_lvl);
++
++	/* use scoreboard[4] to notify BT Rx gain table change   */
++	halbtc8723d2ant_post_state_to_bt(btcoexist,
++		BT_8723D_2ANT_SCOREBOARD_RXGAIN, rx_gain_en);
++}
++
++static
++boolean halbtc8723d2ant_is_wifibt_status_changed(IN struct btc_coexist
++		*btcoexist)
++{
++	static boolean	pre_wifi_busy = FALSE, pre_under_4way = FALSE,
++		pre_bt_hs_on = FALSE, pre_bt_off = FALSE,
++		pre_bt_slave = FALSE, pre_hid_low_pri_tx_overhead = FALSE,
++		pre_wifi_under_lps = FALSE, pre_bt_setup_link = FALSE,
++		pre_cck_lock = FALSE, pre_cck_lock_warn = FALSE;
++	static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0;
++	boolean wifi_busy = FALSE, under_4way = FALSE, bt_hs_on = FALSE;
++	boolean wifi_connected = FALSE;
++	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
++			   &wifi_connected);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
++			   &under_4way);
++
++	if (coex_sta->bt_disabled != pre_bt_off) {
++		pre_bt_off = coex_sta->bt_disabled;
++
++		if (coex_sta->bt_disabled)
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], BT is disabled !!\n");
++		else
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], BT is enabled !!\n");
++
++		BTC_TRACE(trace_buf);
++
++		coex_sta->bt_coex_supported_feature = 0;
++		coex_sta->bt_coex_supported_version = 0;
++		coex_sta->bt_ble_scan_type = 0;
++		coex_sta->bt_ble_scan_para[0] = 0;
++		coex_sta->bt_ble_scan_para[1] = 0;
++		coex_sta->bt_ble_scan_para[2] = 0;
++		coex_sta->bt_reg_vendor_ac = 0xffff;
++		coex_sta->bt_reg_vendor_ae = 0xffff;
++		coex_sta->legacy_forbidden_slot = 0;
++		coex_sta->le_forbidden_slot = 0;
++		coex_sta->bt_a2dp_vendor_id = 0;
++		coex_sta->bt_a2dp_device_name = 0;
++		return TRUE;
++	}
++
++	if (wifi_connected) {
++		if (wifi_busy != pre_wifi_busy) {
++			pre_wifi_busy = wifi_busy;
++
++			if (wifi_busy)
++				halbtc8723d2ant_post_state_to_bt(btcoexist,
++						BT_8723D_2ANT_SCOREBOARD_UNDERTEST, TRUE);
++			else
++				halbtc8723d2ant_post_state_to_bt(btcoexist,
++						BT_8723D_2ANT_SCOREBOARD_UNDERTEST, FALSE);
++			return TRUE;
++		}
++		if (under_4way != pre_under_4way) {
++			pre_under_4way = under_4way;
++			return TRUE;
++		}
++		if (bt_hs_on != pre_bt_hs_on) {
++			pre_bt_hs_on = bt_hs_on;
++			return TRUE;
++		}
++		if (coex_sta->wl_noisy_level != pre_wl_noisy_level) {
++			pre_wl_noisy_level = coex_sta->wl_noisy_level;
++			return TRUE;
++		}
++		if (coex_sta->under_lps != pre_wifi_under_lps) {
++			pre_wifi_under_lps = coex_sta->under_lps;
++			if (coex_sta->under_lps == TRUE)
++				return TRUE;
++		}
++		if (coex_sta->cck_lock != pre_cck_lock) {
++			pre_cck_lock = coex_sta->cck_lock;
++			return TRUE;
++		}
++		if (coex_sta->cck_lock_warn != pre_cck_lock_warn) {
++			pre_cck_lock_warn = coex_sta->cck_lock_warn;
++			return TRUE;
++		}
++	}
++
++	if (!coex_sta->bt_disabled) {
++		if (coex_sta->hid_busy_num != pre_hid_busy_num) {
++			pre_hid_busy_num = coex_sta->hid_busy_num;
++			return TRUE;
++		}
++
++		if (bt_link_info->slave_role != pre_bt_slave) {
++			pre_bt_slave = bt_link_info->slave_role;
++			return TRUE;
++		}
++
++		if (pre_hid_low_pri_tx_overhead != coex_sta->is_hid_low_pri_tx_overhead) {
++			pre_hid_low_pri_tx_overhead = coex_sta->is_hid_low_pri_tx_overhead;
++			return TRUE;
++		}
++
++		if (pre_bt_setup_link != coex_sta->is_setup_link) {
++			pre_bt_setup_link = coex_sta->is_setup_link;
++			return TRUE;
++		}
++	}
++
++	return FALSE;
++}
++
++static
++void halbtc8723d2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
++{
++	static u32		bt_disable_cnt = 0;
++	boolean			bt_active = TRUE, bt_disabled = FALSE;
++	u16			u16tmp;
++
++	/* This function check if bt is disabled
++	 * Read BT on/off status from scoreboard[1],
++	 * enable this only if BT patch support this feature
++	 */
++	halbtc8723d2ant_read_score_board(btcoexist, &u16tmp);
++	bt_active = u16tmp & BIT(1);
++
++	if (bt_active) {
++		bt_disable_cnt = 0;
++		bt_disabled = FALSE;
++		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
++				   &bt_disabled);
++	} else {
++
++		bt_disable_cnt++;
++		if (bt_disable_cnt >= 2) {
++			bt_disabled = TRUE;
++			bt_disable_cnt = 2;
++		}
++
++		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
++				   &bt_disabled);
++	}
++
++	if (coex_sta->bt_disabled != bt_disabled) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], BT is from %s to %s!!\n",
++			    (coex_sta->bt_disabled ? "disabled" : "enabled"),
++			    (bt_disabled ? "disabled" : "enabled"));
++		BTC_TRACE(trace_buf);
++		coex_sta->bt_disabled = bt_disabled;
++	}
++
++}
++
++static
++void halbtc8723d2ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist,
++					boolean isenable)
++{
++#if BT_8723D_2ANT_COEX_DBG
++	if (isenable) {
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);
++
++		/* enable GNT_BT to GPIO debug */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0);
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0);
++
++		/* 0x48[20] = 0  for GPIO14 =  GNT_WL*/
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x0);
++		/* 0x40[17] = 0  for GPIO14 =  GNT_WL*/
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, 0x02, 0x0);
++
++		/* 0x66[9] = 0   for GPIO15 =  GNT_BT*/
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x02, 0x0);
++		/* 0x66[7] = 0
++		for GPIO15 =  GNT_BT*/
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, 0x80, 0x0);
++		/* 0x8[8] = 0    for GPIO15 =  GNT_BT*/
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x9, 0x1, 0x0);
++
++		/* BT Vendor Reg 0x76[0] = 0  for GPIO15 =  GNT_BT, this is not set here*/
++	} else {
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0);
++
++		/* Disable GNT_BT debug to GPIO, and enable chip_wakeup_host */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x1);
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x1);
++
++		/* 0x48[20] = 0  for GPIO14 =  GNT_WL*/
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x1);
++	}
++
++#endif
++}
++
++static
++u32 halbtc8723d2ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
++		IN u16 reg_addr)
++{
++	u32 j = 0, delay_count = 0;
++
++	/* wait for ready bit before access 0x7c0/0x7c4 */
++	while (1) {
++		if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3)&BIT(5)) == 0) {
++			delay_ms(10);
++			delay_count++;
++			if (delay_count >= 10) {
++				delay_count = 0;
++				break;
++			}
++		} else
++			break;
++	}
++
++	btcoexist->btc_write_4byte(btcoexist, 0x7c0, 0x800F0000 | reg_addr);
++
++	return btcoexist->btc_read_4byte(btcoexist,
++					 0x7c8);  /* get read data */
++
++}
++
++static
++void halbtc8723d2ant_ltecoex_indirect_write_reg(IN struct btc_coexist
++		*btcoexist,
++		IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value)
++{
++	u32 val, i = 0, j = 0, bitpos = 0, delay_count = 0;
++
++
++	if (bit_mask == 0x0)
++		return;
++	if (bit_mask == 0xffffffff) {
++		/* wait for ready bit before access 0x7c0/0x7c4 */
++		while (1) {
++			if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3)&BIT(5)) == 0) {
++				delay_ms(10);
++				delay_count++;
++				if (delay_count >= 10) {
++					delay_count = 0;
++					break;
++				}
++			} else
++				break;
++		}
++
++		btcoexist->btc_write_4byte(btcoexist, 0x7c4,
++					   reg_value); /* put write data */
++
++		btcoexist->btc_write_4byte(btcoexist, 0x7c0,
++					   0xc00F0000 | reg_addr);
++	} else {
++		for (i = 0; i <= 31; i++) {
++			if (((bit_mask >> i) & 0x1) == 0x1) {
++				bitpos = i;
++				break;
++			}
++		}
++
++		/* read back register value before write */
++		val = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
++				reg_addr);
++		val = (val & (~bit_mask)) | (reg_value << bitpos);
++
++		/* wait for ready bit before access 0x7c0/0x7c4	*/
++		while (1) {
++			if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3)&BIT(5)) == 0) {
++				delay_ms(10);
++				delay_count++;
++				if (delay_count >= 10) {
++					delay_count = 0;
++					break;
++				}
++			} else
++				break;
++		}
++
++		btcoexist->btc_write_4byte(btcoexist, 0x7c4,
++					   val); /* put write data */
++
++		btcoexist->btc_write_4byte(btcoexist, 0x7c0,
++					   0xc00F0000 | reg_addr);
++
++	}
++
++}
++
++static
++void halbtc8723d2ant_ltecoex_enable(IN struct btc_coexist *btcoexist,
++				    IN boolean enable)
++{
++	u8 val;
++
++	val = (enable) ? 1 : 0;
++	halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80,
++			val);  /* 0x38[7] */
++
++}
++
++static
++void halbtc8723d2ant_coex_ctrl_owner(IN struct btc_coexist *btcoexist,
++				     IN boolean wifi_control)
++{
++	u8 val;
++
++	val = (wifi_control) ? 1 : 0;
++	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4,
++					   val); /* 0x70[26] */
++
++}
++
++static
++void halbtc8723d2ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist,
++			IN u8 control_block, IN boolean sw_control, IN u8 state)
++{
++	u32 val = 0, val_orig = 0;
++
++	if (!sw_control)
++		val = 0x0;
++	else if (state & 0x1)
++		val = 0x3;
++	else
++		val = 0x1;
++
++	val_orig = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
++				0x38);
++
++	switch (control_block) {
++	case BT_8723D_2ANT_GNT_BLOCK_RFC_BB:
++	default:
++		val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff);
++		break;
++	case BT_8723D_2ANT_GNT_BLOCK_RFC:
++		val = (val << 14) | (val_orig & 0xffff3fff);
++		break;
++	case BT_8723D_2ANT_GNT_BLOCK_BB:
++		val = (val << 10) | (val_orig & 0xfffff3ff);
++		break;
++	}
++
++	halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist,
++				0x38, 0xffffffff, val);
++}
++
++static
++void halbtc8723d2ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist,
++			IN u8 control_block, IN boolean sw_control, IN u8 state)
++{
++	u32 val = 0, val_orig = 0;
++
++	if (!sw_control)
++		val = 0x0;
++	else if (state & 0x1)
++		val = 0x3;
++	else
++		val = 0x1;
++
++	val_orig = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
++				0x38);
++
++	switch (control_block) {
++	case BT_8723D_2ANT_GNT_BLOCK_RFC_BB:
++	default:
++		val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff);
++		break;
++	case BT_8723D_2ANT_GNT_BLOCK_RFC:
++		val = (val << 12) | (val_orig & 0xffffcfff);
++		break;
++	case BT_8723D_2ANT_GNT_BLOCK_BB:
++		val = (val << 8) | (val_orig & 0xfffffcff);
++		break;
++	}
++
++	halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist,
++				0x38, 0xffffffff, val);
++}
++
++static
++void halbtc8723d2ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist,
++		IN u8 table_type, IN u16 table_content)
++{
++	u16 reg_addr = 0x0000;
++
++	switch (table_type) {
++	case BT_8723D_2ANT_CTT_WL_VS_LTE:
++		reg_addr = 0xa0;
++		break;
++	case BT_8723D_2ANT_CTT_BT_VS_LTE:
++		reg_addr = 0xa4;
++		break;
++	}
++
++	if (reg_addr != 0x0000)
++		halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
++			0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */
++
++
++}
++
++static
++void halbtc8723d2ant_coex_table(IN struct btc_coexist *btcoexist,
++				IN boolean force_exec, IN u32 val0x6c0,
++				IN u32 val0x6c4, IN u32 val0x6c8,
++				IN u8 val0x6cc)
++{
++	if (!force_exec) {
++		if (val0x6c0 == coex_dm->cur_val0x6c0 &&
++		    val0x6c4 == coex_dm->cur_val0x6c4 &&
++		    val0x6c8 == coex_dm->cur_val0x6c8 &&
++		    val0x6cc == coex_dm->cur_val0x6cc)
++			return;
++	}
++
++	btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
++	btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
++	btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
++	btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
++
++	coex_dm->cur_val0x6c0 = val0x6c0;
++	coex_dm->cur_val0x6c4 = val0x6c4;
++	coex_dm->cur_val0x6c8 = val0x6c8;
++	coex_dm->cur_val0x6cc = val0x6cc;
++
++}
++
++static
++void halbtc8723d2ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
++		IN boolean force_exec, IN u8 type)
++{
++	u32	break_table;
++	u8	select_table;
++
++	coex_sta->coex_table_type = type;
++
++	if (coex_sta->concurrent_rx_mode_on == TRUE) {
++		break_table = 0xf0ffffff;  /* set WL hi-pri can break BT */
++		select_table =
++			0xb;		/* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */
++	} else {
++		break_table = 0xffffff;
++		select_table = 0x3;
++	}
++
++	switch (type) {
++	case 0:
++		halbtc8723d2ant_coex_table(btcoexist, force_exec,
++			   0xffffffff, 0xffffffff, break_table, select_table);
++		break;
++	case 1:
++		halbtc8723d2ant_coex_table(btcoexist, force_exec,
++			   0x55555555, 0xfafafafa, break_table, select_table);
++		break;
++	case 2:
++		halbtc8723d2ant_coex_table(btcoexist, force_exec,
++			   0x5a5a5a5a, 0x5a5a5a5a, break_table, select_table);
++		break;
++	case 3:
++		halbtc8723d2ant_coex_table(btcoexist, force_exec,
++			   0x55555555, 0x5a5a5a5a, break_table, select_table);
++		break;
++	case 4:
++		halbtc8723d2ant_coex_table(btcoexist, force_exec,
++			   0xffff55ff, 0xfafafafa, break_table, select_table);
++		break;
++	case 5:
++		halbtc8723d2ant_coex_table(btcoexist, force_exec,
++			   0x55555555, 0x55555555, break_table, select_table);
++		break;
++	case 6:
++		halbtc8723d2ant_coex_table(btcoexist, force_exec,
++			   0xaaffffaa, 0xfafafafa, break_table, select_table);
++		break;
++	case 7:
++		halbtc8723d2ant_coex_table(btcoexist, force_exec,
++			   0xaaffffaa, 0xfafafafa, break_table, select_table);
++		break;
++	case 8:
++		halbtc8723d2ant_coex_table(btcoexist, force_exec,
++			   0xffff55ff, 0xfafafafa, break_table, select_table);
++		break;
++	case 9:
++		halbtc8723d2ant_coex_table(btcoexist, force_exec,
++			   0x5a5a5a5a, 0xaaaa5aaa, break_table, select_table);
++		break;
++	default:
++		break;
++	}
++}
++
++static
++void halbtc8723d2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
++		IN boolean enable)
++{
++	u8			h2c_parameter[1] = {0};
++
++	if (enable) {
++		h2c_parameter[0] |= BIT(0);		/* function enable */
++	}
++
++	btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
++}
++
++static
++void halbtc8723d2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
++				     IN boolean force_exec, IN boolean enable)
++{
++	coex_dm->cur_ignore_wlan_act = enable;
++
++	if (!force_exec) {
++		if (coex_dm->pre_ignore_wlan_act ==
++		    coex_dm->cur_ignore_wlan_act)
++			return;
++	}
++	halbtc8723d2ant_set_fw_ignore_wlan_act(btcoexist, enable);
++
++	coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
++}
++
++static
++void halbtc8723d2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
++				  IN u8 lps_val, IN u8 rpwm_val)
++{
++	u8	lps = lps_val;
++	u8	rpwm = rpwm_val;
++
++	btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
++	btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
++}
++
++static
++void halbtc8723d2ant_lps_rpwm(IN struct btc_coexist *btcoexist,
++		      IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
++{
++	coex_dm->cur_lps = lps_val;
++	coex_dm->cur_rpwm = rpwm_val;
++
++	if (!force_exec) {
++		if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
++		    (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
++			return;
++	}
++	halbtc8723d2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
++
++	coex_dm->pre_lps = coex_dm->cur_lps;
++	coex_dm->pre_rpwm = coex_dm->cur_rpwm;
++}
++
++static
++void halbtc8723d2ant_ps_tdma_check_for_power_save_state(
++	IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
++{
++	u8	lps_mode = 0x0;
++	u8	h2c_parameter[5] = {0, 0, 0, 0x40, 0};
++
++	btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
++
++	if (lps_mode) {	/* already under LPS state */
++		if (new_ps_state) {
++			/* keep state under LPS, do nothing. */
++		} else {
++			/* will leave LPS state, turn off psTdma first */
++			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
++						h2c_parameter);
++		}
++	} else {					/* NO PS state */
++		if (new_ps_state) {
++			/* will enter LPS state, turn off psTdma first */
++			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
++						h2c_parameter);
++		} else {
++			/* keep state under NO PS state, do nothing. */
++		}
++	}
++}
++
++static
++void halbtc8723d2ant_power_save_state(IN struct btc_coexist *btcoexist,
++			      IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
++{
++	boolean		low_pwr_disable = FALSE;
++
++	switch (ps_type) {
++	case BTC_PS_WIFI_NATIVE:
++		coex_sta->force_lps_ctrl = FALSE;
++		/* recover to original 32k low power setting */
++		low_pwr_disable = FALSE;
++		/* btcoexist->btc_set(btcoexist,
++				   BTC_SET_ACT_DISABLE_LOW_POWER,
++				   &low_pwr_disable); */
++		btcoexist->btc_set(btcoexist, BTC_SET_ACT_PRE_NORMAL_LPS,
++				   NULL);
++		break;
++	case BTC_PS_LPS_ON:
++		coex_sta->force_lps_ctrl = TRUE;
++		halbtc8723d2ant_ps_tdma_check_for_power_save_state(
++			btcoexist, TRUE);
++		halbtc8723d2ant_lps_rpwm(btcoexist, NORMAL_EXEC,
++					 lps_val, rpwm_val);
++		/* when coex force to enter LPS, do not enter 32k low power. */
++		low_pwr_disable = TRUE;
++		btcoexist->btc_set(btcoexist,
++				   BTC_SET_ACT_DISABLE_LOW_POWER,
++				   &low_pwr_disable);
++		/* power save must executed before psTdma.			 */
++		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
++				   NULL);
++		break;
++	case BTC_PS_LPS_OFF:
++		coex_sta->force_lps_ctrl = TRUE;
++		halbtc8723d2ant_ps_tdma_check_for_power_save_state(
++			btcoexist, FALSE);
++		btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
++				   NULL);
++		break;
++	default:
++		break;
++	}
++}
++
++static
++void halbtc8723d2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
++	   IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
++{
++	u8			h2c_parameter[5] = {0};
++	u8			real_byte1 = byte1, real_byte5 = byte5;
++	boolean			ap_enable = FALSE;
++	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++	u8		ps_type = BTC_PS_WIFI_NATIVE;
++
++	if (byte5 & BIT(2))
++		coex_sta->is_tdma_btautoslot = TRUE;
++	else
++		coex_sta->is_tdma_btautoslot = FALSE;
++
++	/* release bt-auto slot for auto-slot hang is detected!! */
++	if (coex_sta->is_tdma_btautoslot)
++		if ((coex_sta->is_tdma_btautoslot_hang) ||
++			(bt_link_info->slave_role))
++			byte5 = byte5 & 0xfb;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
++			   &ap_enable);
++
++	if ((ap_enable) && (byte1 & BIT(4) && !(byte1 & BIT(5)))) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], FW for AP mode\n");
++		BTC_TRACE(trace_buf);
++		real_byte1 &= ~BIT(4);
++		real_byte1 |= BIT(5);
++
++		real_byte5 |= BIT(5);
++		real_byte5 &= ~BIT(6);
++
++		ps_type = BTC_PS_WIFI_NATIVE;
++		halbtc8723d2ant_power_save_state(btcoexist,
++					ps_type, 0x0,
++					0x0);
++	} else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
++
++		ps_type = BTC_PS_LPS_ON;
++		halbtc8723d2ant_power_save_state(
++			btcoexist, ps_type, 0x50,
++			0x4);
++	} else {
++		ps_type = BTC_PS_WIFI_NATIVE;
++		halbtc8723d2ant_power_save_state(btcoexist, ps_type,
++						 0x0,
++						 0x0);
++	}
++
++
++	h2c_parameter[0] = real_byte1;
++	h2c_parameter[1] = byte2;
++	h2c_parameter[2] = byte3;
++	h2c_parameter[3] = byte4;
++	h2c_parameter[4] = real_byte5;
++
++	coex_dm->ps_tdma_para[0] = real_byte1;
++	coex_dm->ps_tdma_para[1] = byte2;
++	coex_dm->ps_tdma_para[2] = byte3;
++	coex_dm->ps_tdma_para[3] = byte4;
++	coex_dm->ps_tdma_para[4] = real_byte5;
++
++	btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
++
++	if (ps_type == BTC_PS_WIFI_NATIVE)
++		btcoexist->btc_set(btcoexist, BTC_SET_ACT_POST_NORMAL_LPS, NULL);
++}
++
++static
++void halbtc8723d2ant_ps_tdma(IN struct btc_coexist *btcoexist,
++		     IN boolean force_exec, IN boolean turn_on, IN u8 tcase)
++{
++
++	static u8 tdma_byte4_modify, pre_tdma_byte4_modify;
++	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++	u8 type;
++	
++	btcoexist->btc_set_atomic(btcoexist, &coex_dm->setting_tdma, TRUE);
++
++	/* tcase: bit0~7 --> tdma case index
++	 *        bit8   --> for 4-slot (50ms) mode
++	 */
++	if (tcase &  TDMA_4SLOT)/* 4-slot (50ms) mode */
++		halbtc8723d2ant_set_tdma_timer_base(btcoexist, 3);
++	else
++		halbtc8723d2ant_set_tdma_timer_base(btcoexist, 0);
++	
++	type = tcase & 0xff;
++	
++	/* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
++	if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist))
++		tdma_byte4_modify = 0x1;
++	else
++		tdma_byte4_modify = 0x0;
++
++	if (pre_tdma_byte4_modify != tdma_byte4_modify) {
++		force_exec = TRUE;
++		pre_tdma_byte4_modify = tdma_byte4_modify;
++	}
++
++	if (!force_exec) {
++		if (turn_on == coex_dm->cur_ps_tdma_on &&
++		    type == coex_dm->cur_ps_tdma) {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n",
++				    (coex_dm->cur_ps_tdma_on ? "on" : "off"),
++				    coex_dm->cur_ps_tdma);
++			BTC_TRACE(trace_buf);
++
++			btcoexist->btc_set_atomic(btcoexist,
++						  &coex_dm->setting_tdma,
++						  FALSE);
++			return;
++		}
++	}
++
++	if (turn_on) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], ********** TDMA(on, %d)\n", type);
++		BTC_TRACE(trace_buf);
++		
++		if (coex_sta->a2dp_exist && coex_sta->bt_inq_page_remain)
++			halbtc8723d2ant_post_state_to_bt(btcoexist,
++						 BT_8723D_2ANT_SCOREBOARD_TDMA,
++						 FALSE);
++		else
++			halbtc8723d2ant_post_state_to_bt(btcoexist,
++						 BT_8723D_2ANT_SCOREBOARD_TDMA,
++						 TRUE);
++
++		/* enable TBTT interrupt */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, 0x1);
++	} else {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], ********** TDMA(off, %d)\n", type);
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d2ant_post_state_to_bt(btcoexist,
++						 BT_8723D_2ANT_SCOREBOARD_TDMA,
++						 FALSE);
++	}
++
++
++	if (turn_on) {
++		switch (type) {
++		case 1:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x10, 0x03, 0x91, 0x54 |
++						      tdma_byte4_modify);
++			break;
++		case 2:
++		default:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x35, 0x03, 0x11, 0x11 |
++						      tdma_byte4_modify);
++			break;
++		case 3:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x3a, 0x3, 0x91, 0x10 |
++						      tdma_byte4_modify);
++			break;
++		case 4:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x21, 0x3, 0x91, 0x10 |
++						      tdma_byte4_modify);
++			break;
++		case 5:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x25, 0x3, 0x91, 0x10 |
++						      tdma_byte4_modify);
++			break;
++		case 6:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x10, 0x3, 0x91, 0x10 |
++						      tdma_byte4_modify);
++			break;
++		case 7:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x20, 0x3, 0x91, 0x10 |
++						      tdma_byte4_modify);
++			break;
++		case 8:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x15, 0x03, 0x11, 0x11);
++			break;
++		case 10:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x30, 0x03, 0x11, 0x10);
++			break;
++		case 11:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x35, 0x03, 0x11, 0x10 |
++						      tdma_byte4_modify);
++			break;
++		case 12:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x35, 0x03, 0x11, 0x11);
++			break;
++		case 13:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x1c, 0x03, 0x11, 0x10 |
++						      tdma_byte4_modify);
++			break;
++		case 14:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x20, 0x03, 0x11, 0x11);
++			break;
++		case 15:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x10, 0x03, 0x11, 0x14);
++			break;
++		case 16:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x10, 0x03, 0x11, 0x15);
++			break;
++		case 17:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x10, 0x07, 0x11, 0x14);
++			break;
++		case 21:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x30, 0x03, 0x11, 0x10);
++			break;
++		case 22:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x25, 0x03, 0x11, 0x10);
++			break;
++		case 23:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x10, 0x03, 0x11, 0x10);
++			break;
++		case 51:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x10, 0x03, 0x91, 0x10 |
++						      tdma_byte4_modify);
++			break;
++		case 101:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x10, 0x03, 0x10, 0x54 |
++						      tdma_byte4_modify);
++			break;
++		case 102:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x35, 0x03, 0x11, 0x11 |
++						      tdma_byte4_modify);
++			break;
++		case 103:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x30, 0x3, 0x10, 0x50 |
++						      tdma_byte4_modify);
++			break;
++		case 104:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x21, 0x3, 0x10, 0x50 |
++						      tdma_byte4_modify);
++			break;
++		case 105:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x35, 0x3, 0x10, 0x50 |
++						      tdma_byte4_modify);
++			break;
++		case 106:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x08, 0x3, 0x10, 0x50 |
++						      tdma_byte4_modify);
++			break;
++		case 107:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x08, 0x7, 0x10, 0x54);
++			break;
++		case 108:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x30, 0x3, 0x10, 0x50 |
++						      tdma_byte4_modify);
++			break;
++		case 109:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x10, 0x03, 0x10, 0x54 |
++						      tdma_byte4_modify);
++			break;
++		case 110:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x30, 0x03, 0x10, 0x50 |
++						      tdma_byte4_modify);
++			break;
++		case 111:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x25, 0x03, 0x11, 0x11);
++			break;
++		case 112:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x4a, 0x3, 0x10, 0x50);
++			break;
++		case 113:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x48, 0x03, 0x11, 0x10);
++			break;
++		case 116:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x08, 0x03, 0x10, 0x54 |
++						      tdma_byte4_modify);
++			break;
++		case 117:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x08, 0x03, 0x10, 0x14 |
++						      tdma_byte4_modify);
++			break;
++		case 119:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x10, 0x03, 0x11, 0x14 |
++						      tdma_byte4_modify);
++			break;
++		case 120:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x10, 0x03, 0x10, 0x55);
++			break;
++		case 121:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
++						      0x10, 0x03, 0x11, 0x15);
++			break;
++		case 151:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
++						      0x10, 0x03, 0x10, 0x50 |
++						      tdma_byte4_modify);
++			break;
++		}
++	} else {
++		/* disable PS tdma */
++		switch (type) {
++		case 0:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x0,
++						      0x0, 0x0, 0x40, 0x01);
++			break;
++		case 1:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x0,
++						      0x0, 0x0, 0x48, 0x0);
++			break;
++		default:
++			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x0,
++						      0x0, 0x0, 0x40, 0x0);
++			break;
++		}
++	}
++
++	coex_dm->cur_ps_tdma_on = turn_on;
++	coex_dm->cur_ps_tdma = type;
++
++	btcoexist->btc_set_atomic(btcoexist, &coex_dm->setting_tdma, FALSE);
++}
++
++static
++void halbtc8723d2ant_set_ant_path(IN struct btc_coexist *btcoexist,
++				  IN u8 ant_pos_type, IN boolean force_exec,
++				  IN u8 phase)
++{
++	struct  btc_board_info *board_info = &btcoexist->board_info;
++	u32			u32tmp = 0;
++	boolean			pg_ext_switch = FALSE,  is_hw_ant_div_on = FALSE;
++	u8			h2c_parameter[2] = {0};
++	u32			cnt_bt_cal_chk = 0;
++	u8			u8tmp0 = 0, u8tmp1 = 0;
++	boolean			is_in_mp_mode = FALSE;
++	u32				u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0;
++	u16				u16tmp0 = 0,  u16tmp1 = 0;
++
++
++#if BT_8723D_2ANT_COEX_DBG
++
++	u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
++
++     /* To avoid indirect access fail   */
++	if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) {
++		force_exec = TRUE;
++		coex_sta->gnt_error_cnt++;
++	}
++
++	u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
++	u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0xaa);
++	u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948);
++	u8tmp1  = btcoexist->btc_read_1byte(btcoexist, 0x73);
++	u8tmp0 =  btcoexist->btc_read_1byte(btcoexist, 0x67);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(Before Set Ant Pat)\n",
++		    u8tmp0, u16tmp1, u8tmp1);
++	BTC_TRACE(trace_buf);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], **********0x38= 0x%x, 0x54= 0x%x, 0xaa = 0x%x (Before Set Ant Path)\n",
++		    u32tmp1, u32tmp2, u16tmp0);
++	BTC_TRACE(trace_buf);
++#endif
++
++	coex_sta->is_2g_freerun = ((phase == BT_8723D_2ANT_PHASE_2G_FREERUN) ? TRUE : FALSE);
++
++	coex_dm->cur_ant_pos_type = ant_pos_type;
++
++	if (!force_exec) {
++		if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) {
++
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], Skip Antenna Path Setup because no change!!\n");
++			BTC_TRACE(trace_buf);
++			return;
++		}
++	}
++
++	coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
++
++	switch (phase) {
++	case BT_8723D_2ANT_PHASE_COEX_POWERON:
++		/* Set Path control to WL */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x0);
++
++		/* set Path control owner to WL at initial step */
++		halbtc8723d2ant_coex_ctrl_owner(btcoexist,
++						BT_8723D_2ANT_PCO_BTSIDE);
++
++		if (BTC_ANT_PATH_AUTO == ant_pos_type)
++			ant_pos_type = BTC_ANT_PATH_WIFI;
++
++		coex_sta->run_time_state = FALSE;
++
++		break;
++	case BT_8723D_2ANT_PHASE_COEX_INIT:
++		/* Disable LTE Coex Function in WiFi side
++		 * (this should be on if LTE coex is required)
++		 */
++		halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0);
++
++		/* GNT_WL_LTE always = 1
++		 * (this should be config if LTE coex is required)
++		 */
++		halbtc8723d2ant_ltecoex_set_coex_table(
++			btcoexist,
++			BT_8723D_2ANT_CTT_WL_VS_LTE,
++			0xffff);
++
++		/* GNT_BT_LTE always = 1
++		 * (this should be config if LTE coex is required)
++		 */
++		halbtc8723d2ant_ltecoex_set_coex_table(
++			btcoexist,
++			BT_8723D_2ANT_CTT_BT_VS_LTE,
++			0xffff);
++
++		/* Wait If BT IQK running, because Path control owner is
++		 * at BT during BT IQK (setup by WiFi firmware)
++		 */
++		while (cnt_bt_cal_chk <= 20) {
++			u8tmp0 = btcoexist->btc_read_1byte(btcoexist, 0x49d);
++			cnt_bt_cal_chk++;
++			if (u8tmp0 & BIT(0)) {
++				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					    "[BTCoex],  BT is calibrating (wait cnt=%d)\n",
++					    cnt_bt_cal_chk);
++				BTC_TRACE(trace_buf);
++				delay_ms(50);
++			} else {
++				BTC_SPRINTF(trace_buf,
++					    BT_TMP_BUF_SIZE,
++					    "[BTCoex], BT is NOT calibrating (wait cnt=%d)\n",
++					    cnt_bt_cal_chk);
++				BTC_TRACE(trace_buf);
++				break;
++			}
++		}
++
++
++		/* Set Path control to WL */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1);
++
++		/* set Path control owner to WL at initial step */
++		halbtc8723d2ant_coex_ctrl_owner(btcoexist,
++						BT_8723D_2ANT_PCO_WLSIDE);
++
++		/* set GNT_BT to SW high */
++		halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist,
++					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
++		/* Set GNT_WL to SW high */
++		halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist,
++					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
++
++		coex_sta->run_time_state = FALSE;
++
++		if (BTC_ANT_PATH_AUTO == ant_pos_type) {
++			if (board_info->btdm_ant_pos ==
++			    BTC_ANTENNA_AT_MAIN_PORT)
++				ant_pos_type = BTC_ANT_WIFI_AT_MAIN;
++			else
++				ant_pos_type = BTC_ANT_WIFI_AT_AUX;
++		}
++
++		break;
++	case BT_8723D_2ANT_PHASE_WLANONLY_INIT:
++		/* Disable LTE Coex Function in WiFi side
++		 * (this should be on if LTE coex is required)
++		 */
++		halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0);
++
++		/* GNT_WL_LTE always = 1
++		 * (this should be config if LTE coex is required)
++		 */
++		halbtc8723d2ant_ltecoex_set_coex_table(
++			btcoexist,
++			BT_8723D_2ANT_CTT_WL_VS_LTE,
++			0xffff);
++
++		/* GNT_BT_LTE always = 1
++		 *(this should be config if LTE coex is required)
++		 */
++		halbtc8723d2ant_ltecoex_set_coex_table(
++			btcoexist,
++			BT_8723D_2ANT_CTT_BT_VS_LTE,
++			0xffff);
++
++		/* Set Path control to WL */
++		btcoexist->btc_write_1byte_bitmask(btcoexist,
++						   0x67, 0x80, 0x1);
++
++		/* set Path control owner to WL at initial step */
++		halbtc8723d2ant_coex_ctrl_owner(btcoexist,
++						BT_8723D_2ANT_PCO_WLSIDE);
++
++		/* set GNT_BT to SW Low */
++		halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist,
++					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_2ANT_SIG_STA_SET_TO_LOW);
++		/* Set GNT_WL to SW high */
++		halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist,
++					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
++
++		coex_sta->run_time_state = FALSE;
++
++		if (BTC_ANT_PATH_AUTO == ant_pos_type) {
++			if (board_info->btdm_ant_pos ==
++			    BTC_ANTENNA_AT_MAIN_PORT)
++				ant_pos_type = BTC_ANT_WIFI_AT_MAIN;
++			else
++				ant_pos_type = BTC_ANT_WIFI_AT_AUX;
++		}
++
++		break;
++	case BT_8723D_2ANT_PHASE_WLAN_OFF:
++		/* Disable LTE Coex Function in WiFi side */
++		halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0);
++
++		/* Set Path control to BT */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x0);
++
++		/* set Path control owner to BT */
++		halbtc8723d2ant_coex_ctrl_owner(btcoexist,
++						BT_8723D_2ANT_PCO_BTSIDE);
++
++		coex_sta->run_time_state = FALSE;
++		break;
++	case BT_8723D_2ANT_PHASE_2G_RUNTIME:
++
++		/* wait for WL/BT IQK finish, keep 0x38 = 0xff00 for WL IQK */
++		while (cnt_bt_cal_chk <= 20) {
++			u8tmp0 = btcoexist->btc_read_1byte(
++					 btcoexist,
++					 0x1e6);
++
++			u8tmp1 = btcoexist->btc_read_1byte(
++					 btcoexist,
++					 0x49d);
++
++			cnt_bt_cal_chk++;
++			if ((u8tmp0 & BIT(0)) || (u8tmp1 & BIT(0))) {
++				BTC_SPRINTF(trace_buf,
++					    BT_TMP_BUF_SIZE,
++					    "[BTCoex], ########### WL or BT is IQK (wait cnt=%d)\n",
++					    cnt_bt_cal_chk);
++				BTC_TRACE(trace_buf);
++				delay_ms(50);
++			} else {
++				BTC_SPRINTF(trace_buf,
++					    BT_TMP_BUF_SIZE,
++					    "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n",
++					    cnt_bt_cal_chk);
++				BTC_TRACE(trace_buf);
++				break;
++			}
++		}
++
++		/* Set Path control to WL
++		 * btcoexist->btc_write_1byte_bitmask(
++		 * btcoexist, 0x67, 0x80, 0x1);
++		 * set Path control owner to WL at runtime step
++		 */
++		halbtc8723d2ant_coex_ctrl_owner(btcoexist,
++						BT_8723D_2ANT_PCO_WLSIDE);
++
++		halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist,
++					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_PTA,
++					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
++
++		/* Set GNT_WL to PTA */
++		halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist,
++					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_PTA,
++					   BT_8723D_2ANT_SIG_STA_SET_BY_HW);
++
++		coex_sta->run_time_state = TRUE;
++
++		if (BTC_ANT_PATH_AUTO == ant_pos_type) {
++			if (board_info->btdm_ant_pos ==
++			    BTC_ANTENNA_AT_MAIN_PORT)
++				ant_pos_type = BTC_ANT_WIFI_AT_MAIN;
++			else
++				ant_pos_type = BTC_ANT_WIFI_AT_AUX;
++		}
++
++		break;
++	case BT_8723D_2ANT_PHASE_2G_FREERUN:
++
++		/* set Path control owner to WL at runtime step */
++		halbtc8723d2ant_coex_ctrl_owner(btcoexist,
++						BT_8723D_2ANT_PCO_WLSIDE);
++
++		/* set GNT_BT to SW Hi */
++		halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist,
++					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
++		/* Set GNT_WL to SW Hi */
++		halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist,
++					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
++
++		coex_sta->run_time_state = TRUE;
++
++		break;
++	case BT_8723D_2ANT_PHASE_BTMPMODE:
++		/* Disable LTE Coex Function in WiFi side */
++		halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0);
++
++		/* Set Path control to WL */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1);
++
++		/* set Path control owner to WL */
++		halbtc8723d2ant_coex_ctrl_owner(btcoexist,
++						BT_8723D_2ANT_PCO_WLSIDE);
++
++		/* set GNT_BT to SW Hi */
++		halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist,
++					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
++
++		/* Set GNT_WL to SW Lo */
++		halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist,
++					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_2ANT_SIG_STA_SET_TO_LOW);
++
++		coex_sta->run_time_state = FALSE;
++
++		if (BTC_ANT_PATH_AUTO == ant_pos_type) {
++			if (board_info->btdm_ant_pos ==
++			    BTC_ANTENNA_AT_MAIN_PORT)
++				ant_pos_type = BTC_ANT_WIFI_AT_MAIN;
++			else
++				ant_pos_type = BTC_ANT_WIFI_AT_AUX;
++		}
++
++		break;
++	case BT_8723D_2ANT_PHASE_ANTENNA_DET:
++
++		/* Set Path control to WL */
++		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1);
++
++		/* set Path control owner to WL */
++		halbtc8723d2ant_coex_ctrl_owner(btcoexist,
++						BT_8723D_2ANT_PCO_WLSIDE);
++
++		/* Set Antenna Path,  both GNT_WL/GNT_BT = 1,
++		 *and control by SW
++		 * set GNT_BT to SW high
++		 */
++		halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist,
++					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
++
++		/* Set GNT_WL to SW high */
++		halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist,
++					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
++					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
++					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
++
++		if (BTC_ANT_PATH_AUTO == ant_pos_type)
++			ant_pos_type = BTC_ANT_WIFI_AT_AUX;
++
++		coex_sta->run_time_state = FALSE;
++
++		break;
++	}
++
++	is_hw_ant_div_on = board_info->ant_div_cfg;
++
++	if (is_hw_ant_div_on && phase != BT_8723D_2ANT_PHASE_ANTENNA_DET)
++		btcoexist->btc_write_2byte(btcoexist, 0x948, 0x140);
++	else if ((is_hw_ant_div_on == FALSE) &&
++		 (phase != BT_8723D_2ANT_PHASE_WLAN_OFF)) {
++
++		switch (ant_pos_type) {
++		case BTC_ANT_WIFI_AT_MAIN:
++			btcoexist->btc_write_2byte(btcoexist, 0x948, 0x0);
++			break;
++		case BTC_ANT_WIFI_AT_AUX:
++			btcoexist->btc_write_2byte(btcoexist, 0x948, 0x280);
++			break;
++		}
++	}
++
++
++#if BT_8723D_2ANT_COEX_DBG
++	u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
++	u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
++	u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0xaa);
++	u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948);
++	u8tmp1  = btcoexist->btc_read_1byte(btcoexist, 0x73);
++	u8tmp0 =  btcoexist->btc_read_1byte(btcoexist, 0x67);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(After Set Ant Pat)\n",
++		    u8tmp0, u16tmp1, u8tmp1);
++	BTC_TRACE(trace_buf);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], **********0x38= 0x%x, 0x54= 0x%x, 0xaa= 0x%x (After Set Ant Path)\n",
++		    u32tmp1, u32tmp2, u16tmp0);
++	BTC_TRACE(trace_buf);
++#endif
++
++}
++
++static
++u8 halbtc8723d2ant_action_algorithm(IN struct btc_coexist *btcoexist)
++{
++	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
++	boolean				bt_hs_on = FALSE;
++	u8				algorithm = BT_8723D_2ANT_COEX_ALGO_UNDEFINED;
++	u8				num_of_diff_profile = 0;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
++
++	if (!bt_link_info->bt_link_exist) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], No BT link exists!!!\n");
++		BTC_TRACE(trace_buf);
++		return algorithm;
++	}
++
++	if (bt_link_info->sco_exist)
++		num_of_diff_profile++;
++	if (bt_link_info->hid_exist)
++		num_of_diff_profile++;
++	if (bt_link_info->pan_exist)
++		num_of_diff_profile++;
++	if (bt_link_info->a2dp_exist)
++		num_of_diff_profile++;
++
++	if (num_of_diff_profile == 0) {
++
++		if (bt_link_info->acl_busy) {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], No-Profile busy\n");
++			BTC_TRACE(trace_buf);
++			algorithm = BT_8723D_2ANT_COEX_ALGO_NOPROFILEBUSY;
++		}
++	} else if ((bt_link_info->a2dp_exist) && (coex_sta->is_bt_a2dp_sink)) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], A2DP Sink\n");
++		BTC_TRACE(trace_buf);
++		algorithm = BT_8723D_2ANT_COEX_ALGO_A2DPSINK;
++	} else if (num_of_diff_profile == 1) {
++		if (bt_link_info->sco_exist) {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], SCO only\n");
++			BTC_TRACE(trace_buf);
++			algorithm = BT_8723D_2ANT_COEX_ALGO_SCO;
++		} else {
++			if (bt_link_info->hid_exist) {
++				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					    "[BTCoex], HID only\n");
++				BTC_TRACE(trace_buf);
++				algorithm = BT_8723D_2ANT_COEX_ALGO_HID;
++			} else if (bt_link_info->a2dp_exist) {
++				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					    "[BTCoex], A2DP only\n");
++				BTC_TRACE(trace_buf);
++				algorithm = BT_8723D_2ANT_COEX_ALGO_A2DP;
++			} else if (bt_link_info->pan_exist) {
++				if (bt_hs_on) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						    "[BTCoex], PAN(HS) only\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_2ANT_COEX_ALGO_PANHS;
++				} else {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], PAN(EDR) only\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_2ANT_COEX_ALGO_PANEDR;
++				}
++			}
++		}
++	} else if (num_of_diff_profile == 2) {
++		if (bt_link_info->sco_exist) {
++			if (bt_link_info->hid_exist) {
++				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					    "[BTCoex], SCO + HID\n");
++				BTC_TRACE(trace_buf);
++				algorithm = BT_8723D_2ANT_COEX_ALGO_SCO;
++			} else if (bt_link_info->a2dp_exist) {
++				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					    "[BTCoex], SCO + A2DP ==> A2DP\n");
++				BTC_TRACE(trace_buf);
++				algorithm = BT_8723D_2ANT_COEX_ALGO_A2DP;
++			} else if (bt_link_info->pan_exist) {
++				if (bt_hs_on) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], SCO + PAN(HS)\n");
++					BTC_TRACE(trace_buf);
++					algorithm = BT_8723D_2ANT_COEX_ALGO_SCO;
++				} else {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], SCO + PAN(EDR)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_2ANT_COEX_ALGO_PANEDR;
++				}
++			}
++		} else {
++			if (bt_link_info->hid_exist &&
++			    bt_link_info->a2dp_exist) {
++				{
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						    "[BTCoex], HID + A2DP\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_2ANT_COEX_ALGO_HID_A2DP;
++				}
++			} else if (bt_link_info->hid_exist &&
++				   bt_link_info->pan_exist) {
++				if (bt_hs_on) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], HID + PAN(HS)\n");
++					BTC_TRACE(trace_buf);
++					algorithm = BT_8723D_2ANT_COEX_ALGO_HID;
++				} else {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], HID + PAN(EDR)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_2ANT_COEX_ALGO_PANEDR_HID;
++				}
++			} else if (bt_link_info->pan_exist &&
++				   bt_link_info->a2dp_exist) {
++				if (bt_hs_on) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], A2DP + PAN(HS)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_2ANT_COEX_ALGO_A2DP_PANHS;
++				} else {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], A2DP + PAN(EDR)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP;
++				}
++			}
++		}
++	} else if (num_of_diff_profile == 3) {
++		if (bt_link_info->sco_exist) {
++			if (bt_link_info->hid_exist &&
++			    bt_link_info->a2dp_exist) {
++				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"[BTCoex], SCO + HID + A2DP ==> HID + A2DP\n");
++				BTC_TRACE(trace_buf);
++				algorithm = BT_8723D_2ANT_COEX_ALGO_HID_A2DP;
++			} else if (bt_link_info->hid_exist &&
++				   bt_link_info->pan_exist) {
++				if (bt_hs_on) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						    "[BTCoex], SCO + HID + PAN(HS)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_2ANT_COEX_ALGO_PANEDR_HID;
++				} else {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						    "[BTCoex], SCO + HID + PAN(EDR)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_2ANT_COEX_ALGO_PANEDR_HID;
++				}
++			} else if (bt_link_info->pan_exist &&
++				   bt_link_info->a2dp_exist) {
++				if (bt_hs_on) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], SCO + A2DP + PAN(HS)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP;
++				} else {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP;
++				}
++			}
++		} else {
++			if (bt_link_info->hid_exist &&
++			    bt_link_info->pan_exist &&
++			    bt_link_info->a2dp_exist) {
++				if (bt_hs_on) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], HID + A2DP + PAN(HS)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
++				} else {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], HID + A2DP + PAN(EDR)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
++				}
++			}
++		}
++	} else if (num_of_diff_profile >= 3) {
++		if (bt_link_info->sco_exist) {
++			if (bt_link_info->hid_exist &&
++			    bt_link_info->pan_exist &&
++			    bt_link_info->a2dp_exist) {
++				if (bt_hs_on) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
++				} else {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++						"[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
++					BTC_TRACE(trace_buf);
++					algorithm =
++						BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
++				}
++			}
++		}
++	}
++
++	return algorithm;
++}
++
++static
++void halbtc8723d2ant_action_coex_all_off(IN struct btc_coexist *btcoexist)
++{
++
++	halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++	halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++	halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++	halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++	halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++	/* fw all off */
++	halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++}
++
++static
++void halbtc8723d2ant_action_bt_whql_test(IN struct btc_coexist *btcoexist)
++{
++	halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++	halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++	halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++	halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++	halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++	halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++}
++
++static
++void halbtc8723d2ant_action_freerun(IN struct btc_coexist *btcoexist)
++{
++	boolean wifi_busy = FALSE;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], wifi_freerun!!\n");
++	BTC_TRACE(trace_buf);
++
++	halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0x90);
++	halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, TRUE);
++	halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++
++	/* just for GNT_WL = 1 && GNT_BT = 1, not for antenna control  */
++	halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
++								 BT_8723D_2ANT_PHASE_2G_FREERUN);
++	if (wifi_busy)
++		//halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, TRUE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++	else
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++	halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++	halbtc8723d2ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0);
++}
++
++static
++void halbtc8723d2ant_action_bt_hs(IN struct btc_coexist *btcoexist)
++{
++	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state, bt_rssi_state;
++
++	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state2, bt_rssi_state2;
++	boolean wifi_busy = FALSE, wifi_turbo = FALSE;
++
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
++			   &coex_sta->scan_ap_num);
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"############# [BTCoex],  scan_ap_num = %d, wl_noisy = %d\n",
++			coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
++	BTC_TRACE(trace_buf);
++
++#if 1
++	if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
++		wifi_turbo = TRUE;
++#endif
++
++
++	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			  &prewifi_rssi_state, 2,
++			  coex_sta->wifi_coex_thres , 0);
++
++	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			   &prewifi_rssi_state2, 2,
++			   coex_sta->wifi_coex_thres2, 0);
++
++	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state, 2,
++			coex_sta->bt_coex_thres, 0);
++
++	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state2, 2,
++			coex_sta->bt_coex_thres2, 0);
++
++	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
++		BTC_RSSI_HIGH(bt_rssi_state)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
++		   BTC_RSSI_HIGH(bt_rssi_state2)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0x90);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 2);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++
++	} else {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = TRUE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++	}
++
++}
++
++static
++void halbtc8723d2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
++{
++
++	boolean wifi_connected = FALSE;
++	boolean wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE;
++	boolean wifi_busy = FALSE;
++	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
++			   &wifi_connected);
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
++
++	halbtc8723d2ant_adjust_wl_tx_power(btcoexist, FORCE_EXEC, 0xb2);
++	halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++	halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++	halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++	if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam)
++		|| (wifi_scan) || (coex_sta->wifi_is_high_pri_task))) {
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
++							 8);
++
++		if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist))
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE,
++						15);
++		else
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE,
++						11);
++	}  else if ((!wifi_connected) && (!wifi_scan)) {
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], Wifi no-link + no-scan + BT Inq/Page!!\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++	} else if (wifi_busy) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], bt inq/page +  wifi busy\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++	} else if (wifi_connected) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], bt inq/page +  wifi connected\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++	} else if (bt_link_info->pan_exist) {
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
++
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22);
++	} else if (bt_link_info->a2dp_exist) {
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
++
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16);
++	} else {
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
++
++		if ((wifi_link) || (wifi_roam) || (wifi_scan)
++			|| (coex_sta->wifi_is_high_pri_task))
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21);
++		else
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 23);
++	}
++
++}
++
++static
++void halbtc8723d2ant_action_bt_relink(IN struct btc_coexist *btcoexist)
++{
++	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++#if 0
++	if ((!coex_sta->is_bt_multi_link && !bt_link_info->pan_exist) ||
++	    (bt_link_info->a2dp_exist && bt_link_info->hid_exist)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, FORCE_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist,
++						  NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist,
++						  NORMAL_EXEC, FALSE);
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 8);
++	}
++#endif
++	halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++	halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++}
++
++static
++void halbtc8723d2ant_action_bt_idle(IN struct btc_coexist *btcoexist)
++{
++	boolean wifi_busy = FALSE;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++
++	halbtc8723d2ant_adjust_wl_tx_power(btcoexist, FORCE_EXEC, 0xb2);
++	halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++	halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++	halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++	if (!wifi_busy) {
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist,
++						     NORMAL_EXEC, 8);
++
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 14);
++	} else {  /* if wl busy */
++
++		if (BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
++			coex_dm->bt_status) {
++
++			halbtc8723d2ant_coex_table_with_type(btcoexist,
++								 NORMAL_EXEC, 0);
++
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++	   } else {
++
++			halbtc8723d2ant_coex_table_with_type(btcoexist,
++									NORMAL_EXEC, 8);
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE,
++							12);
++		}
++	}
++
++}
++
++
++
++/* SCO only or SCO+PAN(HS) */
++static
++void halbtc8723d2ant_action_sco(IN struct btc_coexist *btcoexist)
++{
++	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
++	u8	wifi_rssi_state, bt_rssi_state;
++
++	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
++	u8	wifi_rssi_state2, bt_rssi_state2;
++	boolean	wifi_busy = FALSE;
++	u32  wifi_bw = 1;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW,
++			   &wifi_bw);
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++
++	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			  &prewifi_rssi_state, 2,
++			  coex_sta->wifi_coex_thres , 0);
++
++	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			   &prewifi_rssi_state2, 2,
++			   coex_sta->wifi_coex_thres2, 0);
++
++	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state, 2,
++			coex_sta->bt_coex_thres, 0);
++
++	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state2, 2,
++			coex_sta->bt_coex_thres2, 0);
++
++
++	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
++		BTC_RSSI_HIGH(bt_rssi_state)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++	}  else {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		if (coex_sta->is_esco_mode)
++			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
++		else  /* 2-Ant free run if eSCO mode */
++			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 8);
++	}
++
++}
++
++static
++void halbtc8723d2ant_action_hid(IN struct btc_coexist *btcoexist)
++{
++	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state, bt_rssi_state;
++
++	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state2, bt_rssi_state2;
++	boolean wifi_busy = FALSE;
++	u32  wifi_bw = 1;
++
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW,  &wifi_bw);
++
++	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			  &prewifi_rssi_state, 2,
++			  coex_sta->wifi_coex_thres , 0);
++
++	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			   &prewifi_rssi_state2, 2,
++			   coex_sta->wifi_coex_thres2, 0);
++
++	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state, 2,
++			coex_sta->bt_coex_thres, 0);
++
++	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state2, 2,
++			coex_sta->bt_coex_thres2, 0);
++
++
++	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
++		BTC_RSSI_HIGH(bt_rssi_state)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++	}  else {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		if (coex_sta->is_hid_low_pri_tx_overhead) {
++
++			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 108);
++		} else if (coex_sta->is_hid_rcu) {
++
++			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 113);
++		} else if (wifi_bw == 0) {   /* if 11bg mode */
++
++			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 111);
++		} else {
++
++			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 111);
++		}
++	}
++
++}
++
++static
++void halbtc8723d2ant_action_a2dpsink(IN struct btc_coexist *btcoexist)
++{
++	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state, bt_rssi_state;
++
++	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state2, bt_rssi_state2;
++	boolean wifi_busy = FALSE, wifi_turbo = FALSE;
++	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
++			   &coex_sta->scan_ap_num);
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"############# [BTCoex],  scan_ap_num = %d, wl_noisy = %d\n",
++			coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
++	BTC_TRACE(trace_buf);
++
++#if 1
++	if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
++		wifi_turbo = TRUE;
++#endif
++
++	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			  &prewifi_rssi_state, 2,
++			  coex_sta->wifi_coex_thres, 0);
++
++	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			   &prewifi_rssi_state2, 2,
++			   coex_sta->wifi_coex_thres2, 0);
++
++	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state, 2,
++			coex_sta->bt_coex_thres, 0);
++
++	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state2, 2,
++			coex_sta->bt_coex_thres2, 0);
++
++
++	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
++		BTC_RSSI_HIGH(bt_rssi_state)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
++		   BTC_RSSI_HIGH(bt_rssi_state2)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0x90);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 2);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
++
++		if (wifi_busy)
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 1);
++		else
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16);
++	} else {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = TRUE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 104);
++	}
++
++}
++
++/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
++static
++void halbtc8723d2ant_action_a2dp(IN struct btc_coexist *btcoexist)
++{
++	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state, bt_rssi_state;
++
++	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state2, bt_rssi_state2;
++
++	static u8	prewifi_rssi_state3 = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state3 = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state3, bt_rssi_state3;
++
++	boolean wifi_busy = FALSE, wifi_turbo = FALSE;
++	u8	iot_peer = BTC_IOT_PEER_UNKNOWN;
++	u32	wifi_link_status = 0;
++
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
++			   &coex_sta->scan_ap_num);
++	btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
++			   &wifi_link_status);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"############# [BTCoex],  scan_ap_num = %d, wl_noisy = %d\n",
++			coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
++	BTC_TRACE(trace_buf);
++
++#if 1
++	if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
++		wifi_turbo = TRUE;
++#endif
++
++	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			  &prewifi_rssi_state, 2,
++			  coex_sta->wifi_coex_thres , 0);
++
++	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			   &prewifi_rssi_state2, 2,
++			   coex_sta->wifi_coex_thres2, 0);
++
++	wifi_rssi_state3 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			   &prewifi_rssi_state3, 2,
++			   40, 0);
++
++	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state, 2,
++			coex_sta->bt_coex_thres, 0);
++
++	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state2, 2,
++			coex_sta->bt_coex_thres2, 0);
++
++	bt_rssi_state3 = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state3, 2,
++			80, 0);
++
++#if 1
++	if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) {
++		halbtc8723d2ant_action_freerun(btcoexist);
++	} else {
++
++		if (wifi_link_status & WIFI_P2P_GC_CONNECTED) {
++			halbtc8723d2ant_adjust_wl_tx_power(btcoexist,
++							   NORMAL_EXEC, 0xb2);
++			halbtc8723d2ant_adjust_bt_tx_power(btcoexist,
++							   NORMAL_EXEC, 15);
++
++		} else {
++			halbtc8723d2ant_adjust_wl_tx_power(btcoexist,
++							   NORMAL_EXEC, 0x90);
++			halbtc8723d2ant_adjust_bt_tx_power(btcoexist,
++							   NORMAL_EXEC, 0x0);
++		}
++
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist,
++						  NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist,
++						  NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = TRUE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
++
++		if (BTC_RSSI_HIGH(wifi_rssi_state3)) {
++			if (coex_sta->connect_ap_period_cnt > 0)
++				//halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
++				//			TRUE, 121);
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
++							TRUE, 23);
++			else
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
++							TRUE, 119);
++		} else {
++			if (coex_sta->connect_ap_period_cnt > 0)
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
++							TRUE, 120);
++			else
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
++							TRUE, 101);
++		}
++
++	}
++
++#else
++
++	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
++		BTC_RSSI_HIGH(bt_rssi_state)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
++		   BTC_RSSI_HIGH(bt_rssi_state2)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0x90);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 2);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
++
++		if (wifi_busy)
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 1);
++		else
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16);
++	} else {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = TRUE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 101);
++	}
++#endif
++
++}
++
++static
++void halbtc8723d2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
++{
++	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state, bt_rssi_state;
++
++	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state2, bt_rssi_state2;
++	boolean wifi_busy = FALSE, wifi_turbo = FALSE;
++
++	static u8	prewifi_rssi_state3 = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state3 = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state3, bt_rssi_state3;
++
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &coex_sta->scan_ap_num);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"############# [BTCoex],  scan_ap_num = %d, wl_noisy = %d\n",
++			coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
++	BTC_TRACE(trace_buf);
++
++#if 1
++	if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
++		wifi_turbo = TRUE;
++#endif
++
++	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			  &prewifi_rssi_state, 2,
++			  coex_sta->wifi_coex_thres , 0);
++
++	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			   &prewifi_rssi_state2, 2,
++			   coex_sta->wifi_coex_thres2, 0);
++
++	wifi_rssi_state3 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			   &prewifi_rssi_state3, 2,
++			   58, 0);
++
++	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state, 2,
++			coex_sta->bt_coex_thres, 0);
++
++	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state2, 2,
++			coex_sta->bt_coex_thres2, 0);
++
++	bt_rssi_state3 = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state3, 2,
++			47, 0);
++
++#if 0
++	halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++	halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++	halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++	halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++	coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++	halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++	halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++#endif
++
++
++#if 1
++	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
++		BTC_RSSI_HIGH(bt_rssi_state)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
++		   BTC_RSSI_HIGH(bt_rssi_state2)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0x90);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 2);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
++
++		if (wifi_busy)
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 3);
++		else
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 4);
++	} else {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = TRUE;
++
++		/* for Lenovo CPT_For_WiFi OPP test  */
++		if (btcoexist->board_info.customer_id == RT_CID_LENOVO_CHINA &&
++		    BTC_RSSI_HIGH(wifi_rssi_state3) && wifi_busy) {
++			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
++
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 112);
++		} else {
++
++			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
++
++			if (wifi_busy)
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 103);
++			else
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 104);
++		}
++	}
++
++#endif
++
++}
++
++static
++void halbtc8723d2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
++{
++	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state, bt_rssi_state;
++
++	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state2, bt_rssi_state2;
++
++	static u8	prewifi_rssi_state3 = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state3 = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state3, bt_rssi_state3;
++
++
++	boolean wifi_busy = FALSE;
++	u32 wifi_bw = 1;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW,
++			   &wifi_bw);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++
++	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			  &prewifi_rssi_state, 2,
++			  coex_sta->wifi_coex_thres , 0);
++
++	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			   &prewifi_rssi_state2, 2,
++			   coex_sta->wifi_coex_thres2, 0);
++
++	wifi_rssi_state3 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			   &prewifi_rssi_state3, 2,
++			   40, 0);
++
++	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state, 2,
++			coex_sta->bt_coex_thres, 0);
++
++	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state2, 2,
++			coex_sta->bt_coex_thres2, 0);
++
++	bt_rssi_state3 = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state3, 2,
++			40, 0);
++
++#if 1
++
++	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
++		BTC_RSSI_HIGH(bt_rssi_state)) {
++
++		halbtc8723d2ant_action_freerun(btcoexist);
++	} else {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0x90);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0x0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = TRUE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
++
++		if (coex_sta->hid_pair_cnt > 1) {
++			if (BTC_RSSI_HIGH(wifi_rssi_state3))
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 117);
++			else
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 116);
++		} else {
++		if (BTC_RSSI_HIGH(wifi_rssi_state3))
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 119);
++		else
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 109);
++		}
++	}
++
++#else
++
++	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
++		BTC_RSSI_HIGH(bt_rssi_state)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
++		   BTC_RSSI_HIGH(bt_rssi_state2)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0x90);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 2);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
++
++		if (wifi_busy)
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 1);
++		else
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16);
++	} else {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = TRUE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
++
++		if (coex_sta->hid_pair_cnt > 1) {
++			if (BTC_RSSI_HIGH(wifi_rssi_state3))
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 117);
++			else
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 116);
++		} else {
++		if (BTC_RSSI_HIGH(wifi_rssi_state3))
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 119);
++		else
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 109);
++		}
++	}
++#endif
++}
++
++static
++void halbtc8723d2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
++{
++	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state, bt_rssi_state;
++
++	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state2, bt_rssi_state2;
++	boolean wifi_busy = FALSE, wifi_turbo = FALSE;
++
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
++			   &coex_sta->scan_ap_num);
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"############# [BTCoex],  scan_ap_num = %d, wl_noisy = %d\n",
++			coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
++	BTC_TRACE(trace_buf);
++
++#if 1
++	if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
++		wifi_turbo = TRUE;
++#endif
++
++
++	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			  &prewifi_rssi_state, 2,
++			  coex_sta->wifi_coex_thres , 0);
++
++	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			   &prewifi_rssi_state2, 2,
++			   coex_sta->wifi_coex_thres2, 0);
++
++	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state, 2,
++			coex_sta->bt_coex_thres, 0);
++
++	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state2, 2,
++			coex_sta->bt_coex_thres2, 0);
++
++
++	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
++		BTC_RSSI_HIGH(bt_rssi_state)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
++		   BTC_RSSI_HIGH(bt_rssi_state2)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0x90);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 2);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
++
++		if (wifi_busy) {
++
++			if ((coex_sta->a2dp_bit_pool > 40) &&
++				(coex_sta->a2dp_bit_pool < 255))
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
++							TRUE, 7);
++			else
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
++							TRUE, 5);
++		} else
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE,
++						6);
++
++	} else {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = TRUE;
++
++		if (wifi_turbo)
++			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
++		else
++			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
++
++		if (wifi_busy) {
++
++			if ((coex_sta->a2dp_bit_pool > 40) &&
++				(coex_sta->a2dp_bit_pool < 255))
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 107);
++			else
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 105);
++		} else
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 106);
++
++	}
++
++}
++
++
++/* PAN(EDR)+A2DP */
++static
++void halbtc8723d2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
++{
++	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state, bt_rssi_state;
++
++	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state2, bt_rssi_state2;
++
++	static u8	prewifi_rssi_state3 = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state3 = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state3, bt_rssi_state3;
++
++	boolean	wifi_busy = FALSE, wifi_turbo = FALSE;
++	u8	iot_peer = BTC_IOT_PEER_UNKNOWN;
++
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
++			   &coex_sta->scan_ap_num);
++	btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"############# [BTCoex],  scan_ap_num = %d, wl_noisy = %d\n",
++			coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
++	BTC_TRACE(trace_buf);
++
++#if 1
++	if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
++		wifi_turbo = TRUE;
++#endif
++
++
++	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			  &prewifi_rssi_state, 2,
++			  coex_sta->wifi_coex_thres , 0);
++
++	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			   &prewifi_rssi_state2, 2,
++			   coex_sta->wifi_coex_thres2, 0);
++
++	wifi_rssi_state3 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			   &prewifi_rssi_state3, 2,
++			   40, 0);
++
++	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state, 2,
++			coex_sta->bt_coex_thres, 0);
++
++	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state2, 2,
++			coex_sta->bt_coex_thres2, 0);
++
++	bt_rssi_state3 = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state3, 2,
++			45, 0);
++
++	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
++		BTC_RSSI_HIGH(bt_rssi_state)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
++		   BTC_RSSI_HIGH(bt_rssi_state2)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0x90);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 2);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
++
++		if (wifi_busy) {
++
++			if (((coex_sta->a2dp_bit_pool > 40) &&
++				 (coex_sta->a2dp_bit_pool < 255)) ||
++				(!coex_sta->is_A2DP_3M))
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 7);
++			else
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 5);
++		} else
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 6);
++	} else {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = TRUE;
++
++		/* for Lenovo coex test case    */
++		if (btcoexist->board_info.customer_id == RT_CID_LENOVO_CHINA &&
++		    coex_sta->scan_ap_num <= 10) {
++
++			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
++
++			/* for CPT_for_WiFi   */
++			if (BTC_RSSI_HIGH(bt_rssi_state3) && BTC_RSSI_LOW(wifi_rssi_state3)) {
++				halbtc8723d2ant_adjust_bt_tx_power(btcoexist, FORCE_EXEC, 10);
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 105);
++			} else {  /* for CPT_for_BT   */
++				halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 107);
++			}
++		} else {
++
++			halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++			//halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
++			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
++
++			if (wifi_busy)
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 107);
++			else
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 106);
++		}
++	}
++
++}
++
++static
++void halbtc8723d2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
++{
++	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
++	u8		wifi_rssi_state, bt_rssi_state;
++
++	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
++	u8	wifi_rssi_state2, bt_rssi_state2;
++	boolean	wifi_busy = FALSE;
++	u32 wifi_bw = 1;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW,
++			   &wifi_bw);
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++
++	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			  &prewifi_rssi_state, 2,
++			  coex_sta->wifi_coex_thres , 0);
++
++	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			   &prewifi_rssi_state2, 2,
++			   coex_sta->wifi_coex_thres2, 0);
++
++	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state, 2,
++			coex_sta->bt_coex_thres, 0);
++
++	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state2, 2,
++			coex_sta->bt_coex_thres2, 0);
++
++
++	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
++		BTC_RSSI_HIGH(bt_rssi_state)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
++		   BTC_RSSI_HIGH(bt_rssi_state2)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0x90);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 2);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
++
++		if (wifi_busy)
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 3);
++		else
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 4);
++	} else {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = TRUE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
++
++		if (wifi_busy)
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 103);
++		else
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 104);
++	}
++
++}
++
++
++/* HID+A2DP+PAN(EDR) */
++static
++void halbtc8723d2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
++{
++	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
++	u8	wifi_rssi_state, bt_rssi_state;
++
++	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
++	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
++	u8	wifi_rssi_state2, bt_rssi_state2;
++	boolean	wifi_busy = FALSE;
++	u32 wifi_bw = 1;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW,
++			   &wifi_bw);
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++
++	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			  &prewifi_rssi_state, 2,
++			  coex_sta->wifi_coex_thres, 0);
++
++	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
++			   &prewifi_rssi_state2, 2,
++			   coex_sta->wifi_coex_thres2 , 0);
++
++	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state, 2,
++			coex_sta->bt_coex_thres, 0);
++
++	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(btcoexist,
++			&pre_bt_rssi_state2, 2,
++			coex_sta->bt_coex_thres2, 0);
++
++
++	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
++		BTC_RSSI_HIGH(bt_rssi_state)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
++		   BTC_RSSI_HIGH(bt_rssi_state2)) {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0x90);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 2);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = FALSE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
++
++		if (wifi_busy) {
++
++			if (((coex_sta->a2dp_bit_pool > 40) &&
++				 (coex_sta->a2dp_bit_pool < 255)) ||
++				(!coex_sta->is_A2DP_3M))
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 7);
++			else
++				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 5);
++		} else
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 6);
++	} else {
++
++		halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++		halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++		halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++		halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++		coex_dm->is_switch_to_1dot5_ant = TRUE;
++
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
++
++		if (wifi_busy)
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 107);
++		else
++			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 106);
++	}
++
++}
++
++static
++void halbtc8723d2ant_action_wifi_native_lps(IN struct btc_coexist *btcoexist)
++{
++	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++
++	if (bt_link_info->pan_exist)
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
++	else
++		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
++	halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++}
++
++static
++void halbtc8723d2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
++{
++	halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++	halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 15);
++	halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++	halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++	/* hw all off */
++	halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++	halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++}
++
++static
++void halbtc8723d2ant_action_wifi_linkscan_process(IN struct btc_coexist *btcoexist)
++{
++	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++	boolean	link = FALSE, wifi_connected = FALSE;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
++			   &wifi_connected);
++	halbtc8723d2ant_adjust_wl_tx_power(btcoexist, FORCE_EXEC, 0xb2);
++	halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++	halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++	halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++	halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
++#if 0
++	if (bt_link_info->pan_exist)
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22);
++	else if (bt_link_info->a2dp_exist)
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16);
++	else
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21);
++#endif
++	if (bt_link_info->a2dp_exist && 
++	   (bt_link_info->pan_exist || coex_sta->is_bt_multi_link || 
++		link || !wifi_connected))
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 23);
++	else if (bt_link_info->a2dp_exist)
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 15);
++	else if (bt_link_info->pan_exist)
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22);
++	else
++		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21);
++}
++
++static
++void halbtc8723d2ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
++{
++	halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++	halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++	halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++	halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++	halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
++
++	/* fw all off */
++	halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
++}
++
++static
++void halbtc8723d2ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
++{
++	switch (coex_dm->cur_algorithm) {
++
++	case BT_8723D_2ANT_COEX_ALGO_SCO:
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], Action 2-Ant, algorithm = SCO.\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_sco(btcoexist);
++		break;
++	case BT_8723D_2ANT_COEX_ALGO_HID:
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], Action 2-Ant, algorithm = HID.\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_hid(btcoexist);
++		break;
++	case BT_8723D_2ANT_COEX_ALGO_A2DP:
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], Action 2-Ant, algorithm = A2DP.\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_a2dp(btcoexist);
++		break;
++	case BT_8723D_2ANT_COEX_ALGO_A2DPSINK:
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], Action 2-Ant, algorithm = A2DP Sink.\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_a2dpsink(btcoexist);
++		break;
++	case BT_8723D_2ANT_COEX_ALGO_A2DP_PANHS:
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_a2dp_pan_hs(btcoexist);
++		break;
++	case BT_8723D_2ANT_COEX_ALGO_PANEDR:
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_pan_edr(btcoexist);
++		break;
++	case BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP:
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_pan_edr_a2dp(btcoexist);
++		break;
++	case BT_8723D_2ANT_COEX_ALGO_PANEDR_HID:
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_pan_edr_hid(btcoexist);
++		break;
++	case BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_hid_a2dp_pan_edr(
++			btcoexist);
++		break;
++	case BT_8723D_2ANT_COEX_ALGO_HID_A2DP:
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_hid_a2dp(btcoexist);
++		break;
++	case BT_8723D_2ANT_COEX_ALGO_NOPROFILEBUSY:
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_bt_idle(btcoexist);
++		break;
++	default:
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_coex_all_off(btcoexist);
++		break;
++		}
++
++	 coex_dm->pre_algorithm = coex_dm->cur_algorithm;
++
++}
++
++static
++void halbtc8723d2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
++{
++	u8	algorithm = 0;
++	u32	num_of_wifi_link = 0;
++	u32	wifi_link_status = 0;
++	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++	boolean miracast_plus_bt = FALSE;
++	boolean	scan = FALSE, link = FALSE, roam = FALSE,
++			under_4way = FALSE, wifi_busy,
++			wifi_connected = FALSE, wifi_under_5g = FALSE,
++			bt_hs_on = FALSE;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
++			   &under_4way);
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
++	
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], RunCoexistMechanism()===>\n");
++	BTC_TRACE(trace_buf);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], under_lps = %d, force_lps_ctrl = %d, acl_busy = %d!!!\n",
++			coex_sta->under_lps, coex_sta->force_lps_ctrl, coex_sta->acl_busy);
++	BTC_TRACE(trace_buf);
++
++	if (btcoexist->manual_control) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
++		BTC_TRACE(trace_buf);
++		return;
++	}
++
++	if (btcoexist->stop_coex_dm) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
++		BTC_TRACE(trace_buf);
++		return;
++	}
++
++	if (coex_sta->under_ips) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], wifi is under IPS !!!\n");
++		BTC_TRACE(trace_buf);
++		return;
++	}
++
++	if (!coex_sta->run_time_state) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], return for run_time_state = FALSE !!!\n");
++		BTC_TRACE(trace_buf);
++		return;
++	}
++
++	if (coex_sta->freeze_coexrun_by_btinfo) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], return for freeze_coexrun_by_btinfo\n");
++		BTC_TRACE(trace_buf);
++		return;
++	}
++
++	/*If wifi connect-idle, we don't need to inform BT wifi's channel*/
++	if(!wifi_busy)
++		halbtc8723d2ant_update_wifi_channel_info(btcoexist, BTC_MEDIA_DISCONNECT);
++	else
++		halbtc8723d2ant_update_wifi_channel_info(btcoexist, BTC_MEDIA_CONNECT);
++	
++	if (coex_sta->under_lps && !coex_sta->force_lps_ctrl) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_wifi_native_lps(btcoexist);
++		return;
++	}
++
++	if (coex_sta->bt_whck_test) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], BT is under WHCK TEST!!!\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_bt_whql_test(btcoexist);
++		return;
++	}
++
++	if (coex_sta->bt_disabled) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				 "[BTCoex], BT is disabled!!!\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_coex_all_off(btcoexist);
++		return;
++	}
++
++	if (coex_sta->c2h_bt_inquiry_page) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], BT is under inquiry/page scan !!\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_bt_inquiry(btcoexist);
++		return;
++	}
++
++	if (coex_sta->is_setup_link || coex_sta->bt_relink_downcount != 0) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], BT is re-link !!!\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_bt_relink(btcoexist);
++		return;
++	}
++
++	/* for P2P */
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
++			   &wifi_link_status);
++	num_of_wifi_link = wifi_link_status >> 16;
++
++	if ((num_of_wifi_link >= 2) ||
++		(wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"############# [BTCoex],  Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
++				num_of_wifi_link, wifi_link_status);
++		BTC_TRACE(trace_buf);
++
++		if (bt_link_info->bt_link_exist)
++			miracast_plus_bt = TRUE;
++		else
++			miracast_plus_bt = FALSE;
++
++		btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
++				   &miracast_plus_bt);
++
++		if (scan || link || roam || under_4way) {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n",
++				    scan, link, roam, under_4way);
++			BTC_TRACE(trace_buf);
++
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], wifi is under linkscan process + Multi-Port !!\n");
++			BTC_TRACE(trace_buf);
++
++			halbtc8723d2ant_action_wifi_linkscan_process(btcoexist);
++		} else
++
++			halbtc8723d2ant_action_wifi_multi_port(btcoexist);
++
++		return;
++	}
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
++
++	if (bt_hs_on) {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"############# [BTCoex],  BT Is hs\n");
++			BTC_TRACE(trace_buf);
++			halbtc8723d2ant_action_bt_hs(btcoexist);
++			return;
++	}
++
++	if ((coex_dm->bt_status == BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE ||
++	     coex_dm->bt_status == BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE)
++	     && wifi_connected) {
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], Action 2-Ant, bt idle!!.\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d2ant_action_bt_idle(btcoexist);
++		return;
++	}
++
++	algorithm = halbtc8723d2ant_action_algorithm(btcoexist);
++	coex_dm->cur_algorithm = algorithm;
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n",
++			coex_dm->cur_algorithm);
++	BTC_TRACE(trace_buf);
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
++			   &wifi_connected);
++
++	if (scan || link || roam || under_4way) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], WiFi is under Link Process !!\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_wifi_linkscan_process(btcoexist);
++	} else if (wifi_connected) {
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], Action 2-Ant, wifi connected!!.\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_wifi_connected(btcoexist);
++
++	} else {
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], Action 2-Ant, wifi not-connected!!.\n");
++		BTC_TRACE(trace_buf);
++		halbtc8723d2ant_action_wifi_not_connected(btcoexist);
++	}
++}
++
++static
++void halbtc8723d2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
++{
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], Coex Mechanism Init!!\n");
++	BTC_TRACE(trace_buf);
++
++	halbtc8723d2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xb2);
++	halbtc8723d2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
++	halbtc8723d2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++	halbtc8723d2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
++
++	/* sw all off */
++	halbtc8723d2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE);
++
++	coex_sta->pop_event_cnt = 0;
++	coex_sta->cnt_remotenamereq = 0;
++	coex_sta->cnt_reinit = 0;
++	coex_sta->cnt_setuplink = 0;
++	coex_sta->cnt_ignwlanact = 0;
++	coex_sta->cnt_page = 0;
++	coex_sta->cnt_roleswitch = 0;
++
++	halbtc8723d2ant_query_bt_info(btcoexist);
++}
++
++static
++void halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist,
++				    IN boolean wifi_only)
++{
++	u8	u8tmp0 = 0, u8tmp1 = 0;
++	u32	vendor;
++	u32	u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0;
++	u16 u16tmp1 = 0;
++	u8 i = 0;
++
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], 2Ant Init HW Config!!\n");
++	BTC_TRACE(trace_buf);
++
++#if BT_8723D_2ANT_COEX_DBG
++	u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
++			0x38);
++	u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
++			0x54);
++	u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948);
++	u8tmp1	= btcoexist->btc_read_1byte(btcoexist, 0x73);
++	u8tmp0 =  btcoexist->btc_read_1byte(btcoexist, 0x67);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(Before init_hw_config)\n",
++		    u8tmp0, u16tmp1, u8tmp1);
++	BTC_TRACE(trace_buf);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], **********0x38= 0x%x, 0x54= 0x%x (Before init_hw_config)\n",
++		    u32tmp1, u32tmp2);
++	BTC_TRACE(trace_buf);
++#endif
++
++
++	coex_sta->bt_coex_supported_feature = 0;
++	coex_sta->bt_coex_supported_version = 0;
++	coex_sta->bt_ble_scan_type = 0;
++	coex_sta->bt_ble_scan_para[0] = 0;
++	coex_sta->bt_ble_scan_para[1] = 0;
++	coex_sta->bt_ble_scan_para[2] = 0;
++	coex_sta->bt_reg_vendor_ac = 0xffff;
++	coex_sta->bt_reg_vendor_ae = 0xffff;
++	coex_sta->gnt_error_cnt = 0;
++	coex_sta->bt_relink_downcount = 0;
++	coex_sta->wl_rx_rate = BTC_UNKNOWN;
++
++	for (i = 0; i <= 9; i++)
++		coex_sta->bt_afh_map[i] = 0;
++
++	/* 0xf0[15:12] --> kt_ver */
++	coex_sta->kt_ver = (btcoexist->btc_read_1byte(btcoexist,
++				 0xf1) & 0xf0) >> 4;
++
++	coex_sta->dis_ver_info_cnt = 0;
++
++	/* default isolation = 15dB */
++	coex_sta->isolation_btween_wb = BT_8723D_2ANT_DEFAULT_ISOLATION;
++	halbtc8723d2ant_coex_switch_threshold(btcoexist,
++					      coex_sta->isolation_btween_wb);
++
++	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
++					   0x1);  /* enable TBTT nterrupt */
++
++	/* BT report packet sample rate	 */
++	btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5);
++
++	/* Init 0x778 = 0x1 for 2-Ant */
++	btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
++
++	/* Enable PTA (3-wire function form BT side) */
++	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
++	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1);
++
++	/* Enable PTA (tx/rx signal form WiFi side) */
++	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1);
++
++	halbtc8723d2ant_enable_gnt_to_gpio(btcoexist, TRUE);
++
++	/* Enable counter statistics */
++	btcoexist->btc_write_1byte(btcoexist, 0x76e,
++			   0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */
++
++	/* WLAN_Tx by GNT_WL  0x950[29] = 0 */
++	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x20, 0x0);
++
++	psd_scan->ant_det_is_ant_det_available = TRUE;
++
++	if (coex_sta->is_rf_state_off) {
++
++		halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
++					     FORCE_EXEC,
++					     BT_8723D_2ANT_PHASE_WLAN_OFF);
++
++		btcoexist->stop_coex_dm = TRUE;
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], **********  halbtc8723d2ant_init_hw_config (RF Off)**********\n");
++		BTC_TRACE(trace_buf);
++	} else if (wifi_only) {
++		coex_sta->concurrent_rx_mode_on = FALSE;
++		/* Path config	 */
++		/* Set Antenna Path */
++		halbtc8723d2ant_set_ant_path(btcoexist,
++					     BTC_ANT_PATH_AUTO,
++					     FORCE_EXEC,
++					     BT_8723D_2ANT_PHASE_WLANONLY_INIT);
++
++		btcoexist->stop_coex_dm = TRUE;
++	} else {
++		coex_sta->concurrent_rx_mode_on = TRUE;
++		/* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); */
++
++		/* RF 0x1[0] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx */
++		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x1, 0x0);
++
++		/* Path config	 */
++		halbtc8723d2ant_set_ant_path(btcoexist,
++					     BTC_ANT_PATH_AUTO,
++					     FORCE_EXEC,
++					     BT_8723D_2ANT_PHASE_COEX_INIT);
++
++		btcoexist->stop_coex_dm = FALSE;
++	}
++
++	halbtc8723d2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
++
++	halbtc8723d2ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0);
++}
++
++#ifdef PLATFORM_WINDOWS
++#pragma optimize("", off)
++#endif
++
++/* ************************************************************
++ * work around function start with wa_halbtc8723d2ant_
++ * ************************************************************
++ * ************************************************************
++ * extern function start with ex_halbtc8723d2ant_
++ * ************************************************************ */
++void ex_halbtc8723d2ant_power_on_setting(IN struct btc_coexist *btcoexist)
++{
++	struct  btc_board_info	*board_info = &btcoexist->board_info;
++	u8 u8tmp = 0x0;
++	u16 u16tmp = 0x0;
++	u32	value = 0;
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"xxxxxxxxxxxxxxxx Execute 8723d 2-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n");
++	BTC_TRACE(trace_buf);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "Ant Det Finish = %s, Ant Det Number  = %d\n",
++		    (board_info->btdm_ant_det_finish ? "Yes" : "No"),
++		    board_info->btdm_ant_num_by_ant_det);
++	BTC_TRACE(trace_buf);
++
++
++	btcoexist->stop_coex_dm = TRUE;
++	coex_sta->is_rf_state_off = FALSE;
++	psd_scan->ant_det_is_ant_det_available = FALSE;
++
++	/* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */
++	u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
++	btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
++
++
++	/* Local setting bit define */
++	/*	BIT0: "0" for no antenna inverse; "1" for antenna inverse  */
++	/*	BIT1: "0" for internal switch; "1" for external switch */
++	/*	BIT2: "0" for one antenna; "1" for two antenna */
++	/* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
++
++	/* Set path control to WL */
++	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1);
++	btcoexist->btc_write_2byte(btcoexist, 0x948, 0x0);
++
++	/* Check efuse 0xc3[6] for Single Antenna Path */
++	if (board_info->single_ant_path == 0) {
++		/* set to S1 */
++		board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
++		u8tmp = 4;
++		value = 1;
++	} else if (board_info->single_ant_path == 1) {
++		/* set to S0 */
++		board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
++		u8tmp = 5;
++		value = 0;
++	}
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], ********** (Power On) single_ant_path  = %d, btdm_ant_pos = %d **********\n",
++		    board_info->single_ant_path , board_info->btdm_ant_pos);
++	BTC_TRACE(trace_buf);
++
++	/* Set Antenna Path to BT side */
++	halbtc8723d2ant_set_ant_path(btcoexist,
++				     BTC_ANT_PATH_AUTO,
++				     FORCE_EXEC,
++				     BT_8723D_1ANT_PHASE_COEX_POWERON);
++
++	/* Write Single Antenna Position to Registry to tell BT for 872db. This line can be removed
++	since BT EFuse also add "single antenna position" in EFuse for 8723d*/
++	btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL,
++			   &value);
++
++	/* Save"single antenna position" info in Local register setting for FW reading, because FW may not ready at  power on */
++	if (btcoexist->chip_interface == BTC_INTF_PCI)
++		btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp);
++	else if (btcoexist->chip_interface == BTC_INTF_USB)
++		btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
++	else if (btcoexist->chip_interface == BTC_INTF_SDIO)
++		btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp);
++
++	/* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
++	halbtc8723d2ant_enable_gnt_to_gpio(btcoexist, TRUE);
++
++#if BT_8723D_2ANT_COEX_DBG
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], **********  LTE coex Reg 0x38 (Power-On) = 0x%x**********\n",
++		    halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38));
++	BTC_TRACE(trace_buf);
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], **********  MAC Reg 0x70/ BB Reg 0x948 (Power-On) = 0x%x / 0x%x**********\n",
++		    btcoexist->btc_read_4byte(btcoexist, 0x70),
++		    btcoexist->btc_read_2byte(btcoexist, 0x948));
++	BTC_TRACE(trace_buf);
++
++#endif
++}
++
++void ex_halbtc8723d2ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
++{
++	struct  btc_board_info	*board_info = &btcoexist->board_info;
++	u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */
++
++	/* */
++	/* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */
++	/* Local setting bit define */
++	/*	BIT0: "0" for no antenna inverse; "1" for antenna inverse  */
++	/*	BIT1: "0" for internal switch; "1" for external switch */
++	/*	BIT2: "0" for one antenna; "1" for two antenna */
++	/* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
++	if (btcoexist->chip_interface == BTC_INTF_USB) {
++		/* fixed at S0 for USB interface */
++		u8tmp |= 0x1;	/* antenna inverse */
++		btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
++	} else {
++		/* for PCIE and SDIO interface, we check efuse 0xc3[6] */
++		if (board_info->single_ant_path == 0) {
++		} else if (board_info->single_ant_path == 1) {
++			/* set to S0 */
++			u8tmp |= 0x1;	/* antenna inverse */
++		}
++
++		if (btcoexist->chip_interface == BTC_INTF_PCI)
++			btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0,
++							     u8tmp);
++		else if (btcoexist->chip_interface == BTC_INTF_SDIO)
++			btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60,
++							     u8tmp);
++	}
++}
++
++
++void ex_halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist,
++				       IN boolean wifi_only)
++{
++	halbtc8723d2ant_init_hw_config(btcoexist, wifi_only);
++}
++
++void ex_halbtc8723d2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
++{
++
++	halbtc8723d2ant_init_coex_dm(btcoexist);
++}
++
++void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist)
++{
++	struct  btc_board_info		*board_info = &btcoexist->board_info;
++	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
++	u8				*cli_buf = btcoexist->cli_buf;
++	u8				u8tmp[4], i, ps_tdma_case = 0;
++	u32				u32tmp[4];
++	u16				u16tmp[4];
++	u32				fa_ofdm, fa_cck, cca_ofdm, cca_cck, bt_coex_ver = 0;
++	u32				fw_ver = 0, bt_patch_ver = 0;
++	static u8			pop_report_in_10s = 0, cnt = 0;
++	u32			phyver = 0;
++	boolean			lte_coex_on = FALSE;
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n ============[BT Coexist info 8723D]============");
++	CL_PRINTF(cli_buf);
++
++	if (btcoexist->manual_control) {
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			"\r\n ============[Under Manual Control]============");
++		CL_PRINTF(cli_buf);
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n ==========================================");
++		CL_PRINTF(cli_buf);
++	}
++
++	if (!coex_sta->bt_disabled) {
++
++		if (coex_sta->bt_coex_supported_feature == 0)
++			btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE,
++						&coex_sta->bt_coex_supported_feature);
++
++		if ((coex_sta->bt_coex_supported_version == 0) ||
++			 (coex_sta->bt_coex_supported_version == 0xffff))
++			btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION,
++						&coex_sta->bt_coex_supported_version);
++
++		if (coex_sta->bt_reg_vendor_ac == 0xffff)
++			coex_sta->bt_reg_vendor_ac = (u16)(
++						btcoexist->btc_get_bt_reg(btcoexist, 3,
++						0xac) & 0xffff);
++
++		if (coex_sta->bt_reg_vendor_ae == 0xffff)
++			coex_sta->bt_reg_vendor_ae = (u16)(
++						btcoexist->btc_get_bt_reg(btcoexist, 3,
++						0xae) & 0xffff);
++
++		btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
++						&bt_patch_ver);
++		btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
++
++		if (coex_sta->num_of_profile > 0) {
++			cnt++;
++
++			if (cnt >= 3) {
++				btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0,
++					&coex_sta->bt_afh_map[0]);
++				cnt = 0;
++			}
++		}
++	}
++
++	if (psd_scan->ant_det_try_count == 0) {
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s/ %s",
++			   "Ant PG Num/ Mech/ Pos",
++			   board_info->pg_ant_num,
++			   (board_info->btdm_ant_num == 1 ?
++			   "Shared" : "Non-Shared"),
++			   (board_info->btdm_ant_pos == 1 ?
++			   "S1" : "S0"));
++		CL_PRINTF(cli_buf);
++	} else {
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			"\r\n %-35s = %d/ %d/ %s  (retry=%d/fail=%d/result=%d)",
++			   "Ant PG Num/ Mech(Ant_Det)/ Pos",
++			   board_info->pg_ant_num,
++			   board_info->btdm_ant_num_by_ant_det,
++			   (board_info->btdm_ant_pos == 1 ? "S1" : "S0"),
++			   psd_scan->ant_det_try_count,
++			   psd_scan->ant_det_fail_count,
++			   psd_scan->ant_det_result);
++		CL_PRINTF(cli_buf);
++
++		if (board_info->btdm_ant_det_finish) {
++
++			if (psd_scan->ant_det_result != 12)
++				CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++					   "\r\n %-35s = %s",
++					   "Ant Det PSD Value",
++					   psd_scan->ant_det_peak_val);
++			else
++				CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++					   "\r\n %-35s = %d",
++					   "Ant Det PSD Value",
++					   psd_scan->ant_det_psd_scan_peak_val
++					   / 100);
++			CL_PRINTF(cli_buf);
++		}
++	}
++
++	if (board_info->ant_det_result_five_complete) {
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n %-35s = %d/ %d",
++			   "AntDet(Registry) Num/PSD Value",
++			   board_info->btdm_ant_num_by_ant_det,
++			   (board_info->antdetval & 0x7f));
++		CL_PRINTF(cli_buf);
++	}
++
++
++	bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
++	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
++	phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
++
++	bt_coex_ver = coex_sta->bt_coex_supported_version & 0xff;
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++				"\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
++				"CoexVer WL/  BT_Desired/ BT_Report",
++				glcoex_ver_date_8723d_2ant, glcoex_ver_8723d_2ant,
++				glcoex_ver_btdesired_8723d_2ant,
++				bt_coex_ver,
++				(bt_coex_ver == 0xff ? "Unknown" :
++				(coex_sta->bt_disabled ? "BT-disable" :
++				(bt_coex_ver >= glcoex_ver_btdesired_8723d_2ant ?
++				"Match" : "Mis-Match"))));
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c",
++		   "W_FW/ B_FW/ Phy/ Kt",
++		   fw_ver, bt_patch_ver, phyver,
++		   coex_sta->kt_ver + 65);
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
++		   "Wifi channel informed to BT",
++		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
++		   coex_dm->wifi_chnl_info[2]);
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d ",
++		   "Isolation/WL_Thres/BT_Thres",
++		   coex_sta->isolation_btween_wb,
++		   coex_sta->wifi_coex_thres,
++		   coex_sta->bt_coex_thres);
++	CL_PRINTF(cli_buf);
++
++	/* wifi status */
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
++		   "============[Wifi Status]============");
++	CL_PRINTF(cli_buf);
++	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
++		   "============[BT Status]============");
++	CL_PRINTF(cli_buf);
++
++	pop_report_in_10s++;
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = %s/ %ddBm/ %d/ %d",
++		   "BT status/ rssi/ retryCnt/ popCnt",
++		   ((coex_sta->bt_disabled) ? ("disabled") :	((
++			   coex_sta->c2h_bt_inquiry_page) ? ("inquiry-page")
++			   : ((BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
++			       coex_dm->bt_status) ? "non-connected idle" :
++		((BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
++				       ? "connected-idle" : "busy")))),
++		   coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
++		   coex_sta->pop_event_cnt);
++	CL_PRINTF(cli_buf);
++
++	if (pop_report_in_10s >= 5) {
++		coex_sta->pop_event_cnt = 0;
++		pop_report_in_10s = 0;
++	}
++
++	if (coex_sta->num_of_profile != 0)
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++				"\r\n %-35s = %s%s%s%s%s (multilink = %d)",
++				"Profiles",
++				((bt_link_info->a2dp_exist) ?
++				((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," :
++				"A2DP,") : ""),
++				((bt_link_info->sco_exist) ?  "HFP," : ""),
++				((bt_link_info->hid_exist) ?
++				((coex_sta->is_hid_rcu) ? "HID(RCU)" :
++				((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," :
++				"HID(2/18),")) : ""),
++				((bt_link_info->pan_exist) ?
++				((coex_sta->is_bt_opp_exist) ? "OPP," : "PAN,") : ""),
++				((coex_sta->voice_over_HOGP) ? "Voice" : ""),
++				coex_sta->is_bt_multi_link);
++	else
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n %-35s = None", "Profiles");
++
++	CL_PRINTF(cli_buf);
++
++
++	if (bt_link_info->a2dp_exist) {
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n %-35s = %s/ %d/ 0x%x/ 0x%x",
++			   "CQDDR/Bitpool/V_ID/D_name",
++			   ((coex_sta->is_A2DP_3M) ? "On" : "Off"),
++			   coex_sta->a2dp_bit_pool,
++			   coex_sta->bt_a2dp_vendor_id,
++			   coex_sta->bt_a2dp_device_name);
++		CL_PRINTF(cli_buf);
++	}
++
++	if (bt_link_info->hid_exist) {
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
++			   "HID PairNum",
++			   coex_sta->hid_pair_cnt
++			  );
++		CL_PRINTF(cli_buf);
++	}
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x",
++				"Role/RoleSwCnt/IgnWlact/Feature",
++				((bt_link_info->slave_role) ? "Slave" : "Master"),
++				coex_sta->cnt_roleswitch,
++				((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"),
++				coex_sta->bt_coex_supported_feature);
++	CL_PRINTF(cli_buf);
++
++	if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) {
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			"\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
++			"BLEScan Type/TV/Init/Ble",
++			coex_sta->bt_ble_scan_type,
++			(coex_sta->bt_ble_scan_type & 0x1 ?
++			coex_sta->bt_ble_scan_para[0] : 0x0),
++			(coex_sta->bt_ble_scan_type & 0x2 ?
++			coex_sta->bt_ble_scan_para[1] : 0x0),
++			(coex_sta->bt_ble_scan_type & 0x4 ?
++			coex_sta->bt_ble_scan_para[2] : 0x0));
++		CL_PRINTF(cli_buf);
++	}
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d",
++		   "ReInit/ReLink/IgnWlact/Page/NameReq",
++		   coex_sta->cnt_reinit,
++		   coex_sta->cnt_setuplink,
++		   coex_sta->cnt_ignwlanact,
++		   coex_sta->cnt_page,
++		   coex_sta->cnt_remotenamereq);
++	CL_PRINTF(cli_buf);
++
++	halbtc8723d2ant_read_score_board(btcoexist,	&u16tmp[0]);
++
++	if ((coex_sta->bt_reg_vendor_ae == 0xffff) ||
++	    (coex_sta->bt_reg_vendor_ac == 0xffff))
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ 0x%04x",
++			   "0xae[4]/0xac[1:0]/Scoreboard(B->W)", u16tmp[0]);
++	else
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x",
++			   "0xae[4]/0xac[1:0]/Scoreboard(B->W)",
++			   (int)((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4),
++			   coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]);
++	CL_PRINTF(cli_buf);
++
++	if (coex_sta->num_of_profile > 0) {
++
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			"\r\n %-35s = %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x",
++			"AFH MAP",
++			coex_sta->bt_afh_map[0],
++			coex_sta->bt_afh_map[1],
++			coex_sta->bt_afh_map[2],
++			coex_sta->bt_afh_map[3],
++			coex_sta->bt_afh_map[4],
++			coex_sta->bt_afh_map[5],
++			coex_sta->bt_afh_map[6],
++			coex_sta->bt_afh_map[7],
++			coex_sta->bt_afh_map[8],
++			coex_sta->bt_afh_map[9]
++			   );
++		CL_PRINTF(cli_buf);
++	}
++
++	for (i = 0; i < BT_INFO_SRC_8723D_2ANT_MAX; i++) {
++		if (coex_sta->bt_info_c2h_cnt[i]) {
++			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++				"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x (%d)",
++				   glbt_info_src_8723d_2ant[i],
++				   coex_sta->bt_info_c2h[i][0],
++				   coex_sta->bt_info_c2h[i][1],
++				   coex_sta->bt_info_c2h[i][2],
++				   coex_sta->bt_info_c2h[i][3],
++				   coex_sta->bt_info_c2h[i][4],
++				   coex_sta->bt_info_c2h[i][5],
++				   coex_sta->bt_info_c2h[i][6],
++				   coex_sta->bt_info_c2h_cnt[i]);
++			CL_PRINTF(cli_buf);
++		}
++	}
++
++	/* Sw mechanism	 */
++	if (btcoexist->manual_control)
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
++			"============[mechanism] (before Manual)============");
++	else
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
++			   "============[Mechanism]============");
++
++	CL_PRINTF(cli_buf);
++
++
++	ps_tdma_case = coex_dm->cur_ps_tdma;
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s, %s, Timer:%d)",
++		   "TDMA",
++		   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
++		   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
++		   coex_dm->ps_tdma_para[4], ps_tdma_case,
++		   (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off"),
++		   (coex_dm->is_switch_to_1dot5_ant ? "1.5Ant" : "2Ant"),
++		   coex_sta->tdma_timer_base);
++	CL_PRINTF(cli_buf);
++
++	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
++	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
++	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x",
++		   "Table/0x6c0/0x6c4/0x6c8",
++		   coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]);
++	CL_PRINTF(cli_buf);
++
++	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
++	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x",
++		   "0x778/0x6cc/Scoreboard(W->B)",
++		   u8tmp[0], u32tmp[0], coex_sta->score_board_WB);
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s",
++		   "AntDiv/ ForceLPS",
++		   ((board_info->ant_div_cfg) ? "On" : "Off"),
++		   ((coex_sta->force_lps_ctrl) ? "On" : "Off"));
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
++		   "WL_Pwr/ BT_Pwr", coex_dm->cur_fw_dac_swing_lvl,
++		   coex_dm->cur_bt_dec_pwr_lvl);
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
++		   "BT_Empty/BT_Late",
++		   coex_sta->wl_fw_dbg_info[4],
++		   coex_sta->wl_fw_dbg_info[5]);
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s",
++		   "TDMA_Togg_cnt/WL5ms_cnt/WL5ms_off",
++		   coex_sta->wl_fw_dbg_info[6], coex_sta->wl_fw_dbg_info[7],
++		   ((coex_sta->is_no_wl_5ms_extend) ? "Yes" : "No"));
++	CL_PRINTF(cli_buf);
++
++	u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
++	lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ?  TRUE : FALSE;
++
++	if (lte_coex_on) {
++
++		u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
++				0xa0);
++		u32tmp[1] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
++				0xa4);
++
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
++			   "LTE Coex  Table W_L/B_L",
++			   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff);
++		CL_PRINTF(cli_buf);
++
++		u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
++				0xa8);
++		u32tmp[1] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
++				0xac);
++		u32tmp[2] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
++				0xb0);
++		u32tmp[3] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
++				0xb4);
++
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
++			   "LTE Break Table W_L/B_L/L_W/L_B",
++			   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
++			   u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
++		CL_PRINTF(cli_buf);
++
++	}
++
++	/* Hw setting		 */
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
++		   "============[Hw setting]============");
++	CL_PRINTF(cli_buf);
++
++	u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
++	u32tmp[1] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
++	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s",
++		   "LTE Coex/Path Owner",
++		   ((lte_coex_on) ? "On" : "Off") ,
++		   ((u8tmp[0] & BIT(2)) ? "WL" : "BT"));
++	CL_PRINTF(cli_buf);
++
++	if (lte_coex_on) {
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n %-35s = %d/ %d/ %d/ %d",
++			   "LTE 3Wire/OPMode/UART/UARTMode",
++			   (int)((u32tmp[0] & BIT(6)) >> 6),
++			   (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
++			   (int)((u32tmp[0] & BIT(3)) >> 3),
++			   (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
++		CL_PRINTF(cli_buf);
++
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
++			   "LTE_Busy/UART_Busy",
++			(int)((u32tmp[1] & BIT(1)) >> 1), (int)(u32tmp[1] & BIT(0)));
++		CL_PRINTF(cli_buf);
++	}
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++			   "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s (gnt_err = %d)",
++			   "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg",
++			   ((u32tmp[0] & BIT(12)) ? "SW" : "HW"),
++			   ((u32tmp[0] & BIT(8)) ? "SW" : "HW"),
++			   ((u32tmp[0] & BIT(14)) ? "SW" : "HW"),
++			   ((u32tmp[0] & BIT(10)) ?  "SW" : "HW"),
++			   ((u8tmp[0] & BIT(3)) ? "On" : "Off"),
++			   coex_sta->gnt_error_cnt);
++		CL_PRINTF(cli_buf);
++
++		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
++		   "GNT_WL/GNT_BT",
++		   (int)((u32tmp[1] & BIT(2)) >> 2),
++		   (int)((u32tmp[1] & BIT(3)) >> 3));
++	CL_PRINTF(cli_buf);
++
++	u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x948);
++	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67);
++	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x883);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
++		   "0x948/0x67[7]/0x883",
++		   u16tmp[0], (int)((u8tmp[0] & BIT(7)) >> 7),
++		   u8tmp[1]);
++	CL_PRINTF(cli_buf);
++
++	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x964);
++	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x864);
++	u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xab7);
++	u8tmp[3] = btcoexist->btc_read_1byte(btcoexist, 0xa01);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
++		   "0x964[1]/0x864[0]/0xab7[5]/0xa01[7]",
++		   (int)((u8tmp[0] & BIT(1)) >> 1), (int)((u8tmp[1] & BIT(0))),
++		   (int)((u8tmp[2] & BIT(3)) >> 3),
++		   (int)((u8tmp[3] & BIT(7)) >> 7));
++	CL_PRINTF(cli_buf);
++
++	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
++	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
++	u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
++	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x426);
++	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x45e);
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x/ 0x%x",
++		   "0x430/0x434/0x42a/0x426/0x45e[3]",
++		   u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0],
++		   (int)((u8tmp[1] & BIT(3)) >> 3));
++	CL_PRINTF(cli_buf);
++
++	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
++	u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x40);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = 0x%x/ 0x%x", "0x4c6[4]/0x40[5]",
++		   (int)((u8tmp[0] & BIT(4)) >> 4),
++		   (int)((u16tmp[0] & BIT(5)) >> 5));
++	CL_PRINTF(cli_buf);
++
++	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
++	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
++	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s",
++		   "0x550/0x522/4-RxAGC",
++		   u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off");
++	CL_PRINTF(cli_buf);
++
++	fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_OFDM);
++	fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_CCK);
++	cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_OFDM);
++	cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_CCK);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
++		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
++		   "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
++		   cca_cck, fa_cck, cca_ofdm, fa_ofdm);
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d (Rx_rate Data/RTS= %d/%d)",
++		   "CRC_OK CCK/11g/11n/11ac",
++		   coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
++		   coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht,
++		   coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate);
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
++		   "CRC_Err CCK/11g/11n/11n-agg",
++		   coex_sta->crc_err_cck, coex_sta->crc_err_11g,
++		   coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d",
++		   "WlHiPri/ Locking/ Locked/ Noisy",
++		   (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
++		   (coex_sta->cck_lock ? "Yes" : "No"),
++		   (coex_sta->cck_lock_ever ? "Yes" : "No"),
++		   coex_sta->wl_noisy_level);
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
++		   "0x770(Hi-pri rx/tx)",
++		   coex_sta->high_priority_rx, coex_sta->high_priority_tx,
++		   (coex_sta->is_hipri_rx_overhead ? "(scan overhead!!)" : ""));
++	CL_PRINTF(cli_buf);
++
++	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
++		   "0x774(Lo-pri rx/tx)",
++		   coex_sta->low_priority_rx, coex_sta->low_priority_tx,
++		   (bt_link_info->slave_role ? "(Slave!!)" : (
++		   coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : "")));
++	CL_PRINTF(cli_buf);
++
++	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
++}
++
++
++void ex_halbtc8723d2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
++{
++	if (btcoexist->manual_control ||	btcoexist->stop_coex_dm)
++		return;
++
++	if (BTC_IPS_ENTER == type) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], IPS ENTER notify\n");
++		BTC_TRACE(trace_buf);
++		coex_sta->under_ips = TRUE;
++		coex_sta->under_lps = FALSE;
++
++		halbtc8723d2ant_post_state_to_bt(btcoexist,
++				BT_8723D_2ANT_SCOREBOARD_ACTIVE |
++				BT_8723D_2ANT_SCOREBOARD_ONOFF |
++				BT_8723D_2ANT_SCOREBOARD_SCAN |
++				BT_8723D_2ANT_SCOREBOARD_UNDERTEST,
++				FALSE);
++
++		halbtc8723d2ant_set_ant_path(btcoexist,
++					     BTC_ANT_PATH_AUTO,
++					     FORCE_EXEC,
++					     BT_8723D_2ANT_PHASE_WLAN_OFF);
++
++		halbtc8723d2ant_action_coex_all_off(btcoexist);
++	} else if (BTC_IPS_LEAVE == type) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], IPS LEAVE notify\n");
++		BTC_TRACE(trace_buf);
++		coex_sta->under_ips = FALSE;
++#if 0
++		halbtc8723d2ant_post_state_to_bt(btcoexist,
++					 BT_8723D_2ANT_SCOREBOARD_ACTIVE, TRUE);
++
++		halbtc8723d2ant_post_state_to_bt(btcoexist,
++					BT_8723D_2ANT_SCOREBOARD_ONOFF, TRUE);
++#endif
++		halbtc8723d2ant_init_hw_config(btcoexist, FALSE);
++		halbtc8723d2ant_init_coex_dm(btcoexist);
++		halbtc8723d2ant_query_bt_info(btcoexist);
++	}
++}
++
++void ex_halbtc8723d2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
++{
++	static boolean  pre_force_lps_on = FALSE;
++
++	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
++		return;
++
++	if (BTC_LPS_ENABLE == type) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], LPS ENABLE notify\n");
++		BTC_TRACE(trace_buf);
++		coex_sta->under_lps = TRUE;
++		coex_sta->under_ips = FALSE;
++
++		if (coex_sta->force_lps_ctrl == TRUE) { /* LPS No-32K */
++			/* Write WL "Active" in Score-board for PS-TDMA */
++			pre_force_lps_on = TRUE;
++			halbtc8723d2ant_post_state_to_bt(btcoexist,
++					 BT_8723D_2ANT_SCOREBOARD_ACTIVE, TRUE);
++
++		} else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */
++			/* Write WL "Non-Active" in Score-board for Native-PS */
++			pre_force_lps_on = FALSE;
++			halbtc8723d2ant_post_state_to_bt(btcoexist,
++				 BT_8723D_2ANT_SCOREBOARD_ACTIVE, FALSE);
++
++			halbtc8723d2ant_action_wifi_native_lps(btcoexist);
++		}
++
++	} else if (BTC_LPS_DISABLE == type) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], LPS DISABLE notify\n");
++		BTC_TRACE(trace_buf);
++		coex_sta->under_lps = FALSE;
++
++		halbtc8723d2ant_post_state_to_bt(btcoexist,
++					 BT_8723D_2ANT_SCOREBOARD_ACTIVE, TRUE);
++
++		if ((!pre_force_lps_on) && (!coex_sta->force_lps_ctrl))
++			halbtc8723d2ant_query_bt_info(btcoexist);
++	}
++}
++
++void ex_halbtc8723d2ant_scan_notify(IN struct btc_coexist *btcoexist,
++				    IN u8 type)
++{
++	u32	u32tmp;
++	u8	u8tmpa, u8tmpb;
++	boolean	wifi_connected = FALSE;
++
++
++	if (btcoexist->manual_control ||
++	    btcoexist->stop_coex_dm)
++		return;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
++			   &wifi_connected);
++
++	/*  this can't be removed for RF off_on event, or BT would dis-connect */
++
++	if (BTC_SCAN_START == type) {
++
++		if (!wifi_connected)
++			coex_sta->wifi_is_high_pri_task = TRUE;
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], SCAN START notify\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d2ant_post_state_to_bt(btcoexist,
++					BT_8723D_2ANT_SCOREBOARD_ACTIVE |
++					BT_8723D_2ANT_SCOREBOARD_SCAN |
++					BT_8723D_2ANT_SCOREBOARD_ONOFF,
++					TRUE);
++
++		halbtc8723d2ant_query_bt_info(btcoexist);
++
++		halbtc8723d2ant_set_ant_path(btcoexist,
++					     BTC_ANT_PATH_AUTO,
++					     FORCE_EXEC,
++					     BT_8723D_2ANT_PHASE_2G_RUNTIME);
++
++		halbtc8723d2ant_run_coexist_mechanism(btcoexist);
++
++	} else if (BTC_SCAN_FINISH == type) {
++
++		coex_sta->wifi_is_high_pri_task = FALSE;
++
++		btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
++				   &coex_sta->scan_ap_num);
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], SCAN FINISH notify  (Scan-AP = %d)\n",
++			    coex_sta->scan_ap_num);
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d2ant_post_state_to_bt(btcoexist,
++					 BT_8723D_2ANT_SCOREBOARD_SCAN, FALSE);
++
++		halbtc8723d2ant_run_coexist_mechanism(btcoexist);
++	}
++
++}
++
++void ex_halbtc8723d2ant_connect_notify(IN struct btc_coexist *btcoexist,
++				       IN u8 type)
++{
++	if (btcoexist->manual_control ||
++	    btcoexist->stop_coex_dm)
++		return;
++
++	if (BTC_ASSOCIATE_START == type) {
++
++		coex_sta->wifi_is_high_pri_task = TRUE;
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], CONNECT START notify\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d2ant_post_state_to_bt(btcoexist,
++					 BT_8723D_2ANT_SCOREBOARD_ACTIVE |
++					 BT_8723D_2ANT_SCOREBOARD_SCAN |
++					 BT_8723D_2ANT_SCOREBOARD_ONOFF,
++					 TRUE);
++
++		halbtc8723d2ant_set_ant_path(btcoexist,
++					     BTC_ANT_PATH_AUTO,
++					     FORCE_EXEC,
++					     BT_8723D_2ANT_PHASE_2G_RUNTIME);
++
++		halbtc8723d2ant_run_coexist_mechanism(btcoexist);
++		/* To keep TDMA case during connect process,
++		to avoid changed by Btinfo and runcoexmechanism */
++		coex_sta->freeze_coexrun_by_btinfo = TRUE;
++
++		coex_dm->arp_cnt = 0;
++		coex_sta->connect_ap_period_cnt = 2;
++
++	} else if (BTC_ASSOCIATE_FINISH == type) {
++
++		coex_sta->wifi_is_high_pri_task = FALSE;
++		coex_sta->freeze_coexrun_by_btinfo = FALSE;
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], CONNECT FINISH notify\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d2ant_run_coexist_mechanism(btcoexist);
++	}
++}
++
++void ex_halbtc8723d2ant_media_status_notify(IN struct btc_coexist *btcoexist,
++		IN u8 type)
++{
++	u8			h2c_parameter[3] = {0};
++	u32			wifi_bw;
++	u8			wifi_central_chnl;
++	u8			ap_num = 0;
++	boolean		wifi_under_b_mode = FALSE;
++
++	if (btcoexist->manual_control ||
++	    btcoexist->stop_coex_dm)
++		return;
++
++	if (BTC_MEDIA_CONNECT == type) {
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], MEDIA connect notify\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d2ant_post_state_to_bt(btcoexist,
++					 BT_8723D_2ANT_SCOREBOARD_ACTIVE |
++					 BT_8723D_2ANT_SCOREBOARD_ONOFF,
++					 TRUE);
++
++		halbtc8723d2ant_set_ant_path(btcoexist,
++					     BTC_ANT_PATH_AUTO,
++					     FORCE_EXEC,
++					     BT_8723D_2ANT_PHASE_2G_RUNTIME);
++
++		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
++				   &wifi_under_b_mode);
++
++		/* Set CCK Tx/Rx high Pri except 11b mode */
++		if (wifi_under_b_mode) {
++			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
++						   0x00); /* CCK Tx */
++			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
++						   0x00); /* CCK Rx */
++		} else {
++
++			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
++						   0x00); /* CCK Tx */
++			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
++						   0x10); /* CCK Rx */
++		}
++
++	} else {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], MEDIA disconnect notify\n");
++		BTC_TRACE(trace_buf);
++
++		btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
++		btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
++
++		halbtc8723d2ant_post_state_to_bt(btcoexist,
++				 BT_8723D_2ANT_SCOREBOARD_ACTIVE, FALSE);
++	}
++	btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &coex_sta->wl_iot_peer);
++	halbtc8723d2ant_update_wifi_channel_info(btcoexist, type);
++	
++}
++
++void ex_halbtc8723d2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
++		IN u8 type)
++{
++	boolean under_4way = FALSE;
++
++	if (btcoexist->manual_control ||
++	    btcoexist->stop_coex_dm)
++		return;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
++			   &under_4way);
++
++	if (under_4way) {
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], specific Packet ---- under_4way!!\n");
++		BTC_TRACE(trace_buf);
++
++		coex_sta->wifi_is_high_pri_task = TRUE;
++		coex_sta->specific_pkt_period_cnt = 2;
++
++	} else if (BTC_PACKET_ARP == type) {
++
++		coex_dm->arp_cnt++;
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], specific Packet ARP notify -cnt = %d\n",
++			    coex_dm->arp_cnt);
++		BTC_TRACE(trace_buf);
++
++	} else {
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n",
++			    type);
++		BTC_TRACE(trace_buf);
++
++		coex_sta->wifi_is_high_pri_task = TRUE;
++		coex_sta->specific_pkt_period_cnt = 2;
++	}
++
++	if (coex_sta->wifi_is_high_pri_task) {
++		halbtc8723d2ant_post_state_to_bt(btcoexist,
++					 BT_8723D_2ANT_SCOREBOARD_ACTIVE, TRUE);
++		halbtc8723d2ant_run_coexist_mechanism(btcoexist);
++	}
++
++}
++
++void ex_halbtc8723d2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
++				       IN u8 *tmp_buf, IN u8 length)
++{
++	struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
++	u8 i, rsp_source = 0;
++	boolean	wifi_connected = FALSE;
++	boolean	wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE,
++		wifi_busy = FALSE;
++	static boolean is_scoreboard_scan = FALSE;
++
++	if (psd_scan->is_antdet_running) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], bt_info_notify return for AntDet is running\n");
++		BTC_TRACE(trace_buf);
++		return;
++	}
++
++	rsp_source = tmp_buf[0] & 0xf;
++	if (rsp_source >= BT_INFO_SRC_8723D_2ANT_MAX)
++		rsp_source = BT_INFO_SRC_8723D_2ANT_WIFI_FW;
++	coex_sta->bt_info_c2h_cnt[rsp_source]++;
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source,
++		    length);
++	BTC_TRACE(trace_buf);
++
++	for (i = 0; i < length; i++) {
++		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
++
++		if (i == length - 1) {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
++				    tmp_buf[i]);
++			BTC_TRACE(trace_buf);
++		} else {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
++				    tmp_buf[i]);
++			BTC_TRACE(trace_buf);
++		}
++	}
++
++	coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1];
++	coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4];
++	coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5];
++
++	if (BT_INFO_SRC_8723D_2ANT_WIFI_FW != rsp_source) {
++
++		/* if 0xff, it means BT is under WHCK test */
++		coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? TRUE :
++					  FALSE);
++
++		coex_sta->bt_create_connection = ((
++			coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? TRUE :
++						  FALSE);
++
++		/* unit: %, value-100 to translate to unit: dBm */
++		coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 +
++				    10;
++
++		coex_sta->c2h_bt_remote_name_req = ((
++			coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? TRUE :
++						    FALSE);
++
++		coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] &
++					 0x10) ? TRUE : FALSE);
++
++		coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] &
++				       0x8) ? TRUE : FALSE);
++
++		coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ?
++					     TRUE : FALSE);
++
++		coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info &
++			  BT_INFO_8723D_2ANT_B_INQ_PAGE) ? TRUE : FALSE);
++		
++		if (coex_sta->bt_inq_page_pre != coex_sta->c2h_bt_inquiry_page) {
++			coex_sta->bt_inq_page_pre = coex_sta->c2h_bt_inquiry_page;
++			coex_sta->bt_inq_page_remain = TRUE;
++					
++			if (!coex_sta->c2h_bt_inquiry_page)
++				coex_sta->bt_inq_page_downcount = 2;
++		}
++
++		coex_sta->a2dp_bit_pool = (((
++			coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ?
++			(coex_sta->bt_info_c2h[rsp_source][6] & 0x7f) : 0);
++
++		coex_sta->is_bt_a2dp_sink = (coex_sta->bt_info_c2h[rsp_source][6] & 0x80) ?
++									TRUE : FALSE;
++
++		coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] &
++					 0xf;
++
++		bt_link_info->slave_role  = coex_sta->bt_info_ext2 & 0x8;
++
++		coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7;
++
++		coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4;
++
++		coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6;
++
++		coex_sta->is_bt_opp_exist = (coex_sta->bt_info_ext2 & 0x1) ? TRUE : FALSE;
++
++		if (coex_sta->bt_retry_cnt >= 1)
++			coex_sta->pop_event_cnt++;
++
++		if (coex_sta->c2h_bt_remote_name_req)
++			coex_sta->cnt_remotenamereq++;
++
++		if (coex_sta->bt_info_ext & BIT(1))
++			coex_sta->cnt_reinit++;
++
++		if (coex_sta->bt_info_ext & BIT(2) ||
++		    (coex_sta->bt_create_connection &&
++		    coex_sta->pnp_awake_period_cnt > 0)) {
++			coex_sta->cnt_setuplink++;
++			coex_sta->is_setup_link = TRUE;
++			coex_sta->bt_relink_downcount = 2;
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], Re-Link start in BT info!!\n");
++			BTC_TRACE(trace_buf);
++		}
++
++		if (coex_sta->bt_info_ext & BIT(3))
++			coex_sta->cnt_ignwlanact++;
++
++		if (coex_sta->bt_info_ext & BIT(6))
++			coex_sta->cnt_roleswitch++;
++
++		if (coex_sta->bt_info_ext & BIT(7))
++			coex_sta->is_bt_multi_link = TRUE;
++		else
++			coex_sta->is_bt_multi_link = FALSE;
++
++		if (coex_sta->bt_info_ext & BIT(0))
++			coex_sta->is_hid_rcu = TRUE;
++		else
++			coex_sta->is_hid_rcu = FALSE;
++
++		if (coex_sta->bt_info_ext & BIT(5))
++			coex_sta->is_ble_scan_en = TRUE;
++		else
++			coex_sta->is_ble_scan_en = FALSE;
++
++		if (coex_sta->bt_create_connection) {
++			coex_sta->cnt_page++;
++
++			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY,
++					   &wifi_busy);
++
++			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
++			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
++			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
++
++			if ((wifi_link) || (wifi_roam) || (wifi_scan) ||
++			    (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) {
++
++				is_scoreboard_scan = TRUE;
++				halbtc8723d2ant_post_state_to_bt(btcoexist,
++					 BT_8723D_2ANT_SCOREBOARD_SCAN, TRUE);
++
++			} else
++				halbtc8723d2ant_post_state_to_bt(btcoexist,
++					 BT_8723D_2ANT_SCOREBOARD_SCAN, FALSE);
++
++		} else {
++				if (is_scoreboard_scan) {
++					halbtc8723d2ant_post_state_to_bt(btcoexist,
++						 BT_8723D_2ANT_SCOREBOARD_SCAN, FALSE);
++					is_scoreboard_scan = FALSE;
++				}
++		}
++
++		/* Here we need to resend some wifi info to BT */
++		/* because bt is reset and loss of the info. */
++
++		if ((!btcoexist->manual_control) &&
++		    (!btcoexist->stop_coex_dm)) {
++
++			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
++					   &wifi_connected);
++
++			/*  Re-Init */
++			if ((coex_sta->bt_info_ext & BIT(1))) {
++				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
++				BTC_TRACE(trace_buf);
++				if (wifi_connected)
++					halbtc8723d2ant_update_wifi_channel_info(
++						btcoexist, BTC_MEDIA_CONNECT);
++				else
++					halbtc8723d2ant_update_wifi_channel_info(
++						btcoexist,
++						BTC_MEDIA_DISCONNECT);
++			}
++
++
++			/*  If Ignore_WLanAct && not SetUp_Link or Role_Switch */
++			if ((coex_sta->bt_info_ext & BIT(3)) &&
++				(!(coex_sta->bt_info_ext & BIT(2))) &&
++				(!(coex_sta->bt_info_ext & BIT(6)))) {
++
++				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
++				BTC_TRACE(trace_buf);
++				halbtc8723d2ant_ignore_wlan_act(btcoexist,
++							FORCE_EXEC, FALSE);
++			} else {
++				if (coex_sta->bt_info_ext & BIT(2)) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"[BTCoex], BT ignore Wlan active because Re-link!!\n");
++					BTC_TRACE(trace_buf);
++				} else if (coex_sta->bt_info_ext & BIT(6)) {
++					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++					"[BTCoex], BT ignore Wlan active because Role-Switch!!\n");
++					BTC_TRACE(trace_buf);
++				}
++			}
++		}
++
++	}
++
++	halbtc8723d2ant_update_bt_link_info(btcoexist);
++
++	halbtc8723d2ant_run_coexist_mechanism(btcoexist);
++}
++
++void ex_halbtc8723d2ant_wl_fwdbginfo_notify(IN struct btc_coexist *btcoexist,
++				       IN u8 *tmp_buf, IN u8 length)
++{
++	u8 i = 0;
++	static u8 tmp_buf_pre[10], cnt;
++	u8 h2c_parameter[2] = {0};
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], WiFi Fw Dbg info = %d %d %d %d %d %d %d %d (len = %d)\n",
++		    tmp_buf[0], tmp_buf[1], tmp_buf[2], tmp_buf[3], tmp_buf[4],
++		    tmp_buf[5], tmp_buf[6], tmp_buf[7], length);
++	BTC_TRACE(trace_buf);
++
++	if (tmp_buf[0] == 0x8) {
++		for (i = 1; i <= 7; i++) {
++			coex_sta->wl_fw_dbg_info[i] =
++				(tmp_buf[i] >= tmp_buf_pre[i]) ?
++					(tmp_buf[i] - tmp_buf_pre[i]) :
++					(255 - tmp_buf_pre[i] + tmp_buf[i]);
++
++			tmp_buf_pre[i] = tmp_buf[i];
++		}
++	}
++#if 0
++	if (!coex_sta->is_no_wl_5ms_extend && coex_sta->force_lps_ctrl &&
++	    !coex_sta->cck_lock_ever) {
++		if (coex_sta->wl_fw_dbg_info[7] <= 5)
++			cnt++;
++		else
++			cnt = 0;
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], 5ms WL slot extend cnt = %d!!\n", cnt);
++		BTC_TRACE(trace_buf);
++
++		if (cnt == 7) {
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				    "[BTCoex], set h2c 0x69 opcode 12 to turn off 5ms WL slot extend!!\n");
++			BTC_TRACE(trace_buf);
++
++			h2c_parameter[0] = 0xc;
++			h2c_parameter[1] = 0x1;
++			btcoexist->btc_fill_h2c(btcoexist, 0x69, 2,
++						h2c_parameter);
++			coex_sta->is_no_wl_5ms_extend = TRUE;
++			cnt = 0;
++		}
++	}
++
++	if (coex_sta->is_no_wl_5ms_extend && coex_sta->cck_lock) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], set h2c 0x69 opcode 12 to turn on 5ms WL slot extend!!\n");
++		BTC_TRACE(trace_buf);
++
++		h2c_parameter[0] = 0xc;
++		h2c_parameter[1] = 0x0;
++		btcoexist->btc_fill_h2c(btcoexist, 0x69, 2, h2c_parameter);
++		coex_sta->is_no_wl_5ms_extend = FALSE;
++	}
++#endif
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		"[BTCoex], set h2c 0x69 opcode 12 to turn off 5ms WL slot extend!!\n");
++	BTC_TRACE(trace_buf);
++
++	h2c_parameter[0] = 0xc;
++	h2c_parameter[1] = 0x1;
++	btcoexist->btc_fill_h2c(btcoexist, 0x69, 2,
++					h2c_parameter);
++	coex_sta->is_no_wl_5ms_extend = TRUE;
++}
++
++void ex_halbtc8723d2ant_rx_rate_change_notify(IN struct btc_coexist *btcoexist,
++		IN BOOLEAN is_data_frame, IN u8 btc_rate_id)
++{
++	BOOLEAN wifi_connected = FALSE;
++
++	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
++			   &wifi_connected);
++
++	if (is_data_frame) {
++		coex_sta->wl_rx_rate = btc_rate_id;
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], rx_rate_change_notify data rate id = %d, RTS_Rate = %d\n",
++			coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate);
++		BTC_TRACE(trace_buf);
++	} else {
++		coex_sta->wl_rts_rx_rate = btc_rate_id;
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			"[BTCoex], rts_rate_change_notify RTS rate id = %d, RTS_Rate = %d\n",
++			coex_sta->wl_rts_rx_rate, coex_sta->wl_rts_rx_rate);
++		BTC_TRACE(trace_buf);
++	}
++
++	if (wifi_connected &&
++	    (coex_dm->bt_status ==  BT_8723D_2ANT_BT_STATUS_ACL_BUSY ||
++	     coex_dm->bt_status ==  BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY ||
++	     coex_dm->bt_status == BT_8723D_2ANT_BT_STATUS_SCO_BUSY)) {
++
++		if (coex_sta->wl_rx_rate == BTC_CCK_5_5 ||
++		    coex_sta->wl_rx_rate == BTC_OFDM_6 ||
++		    coex_sta->wl_rx_rate == BTC_MCS_0) {
++
++			coex_sta->cck_lock_warn = TRUE;
++
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], cck lock warning...\n");
++			BTC_TRACE(trace_buf);
++		} else if (coex_sta->wl_rx_rate == BTC_CCK_1 ||
++			   coex_sta->wl_rx_rate == BTC_CCK_2 ||
++			   coex_sta->wl_rts_rx_rate == BTC_CCK_1 ||
++			   coex_sta->wl_rts_rx_rate == BTC_CCK_2) {
++
++			coex_sta->cck_lock = TRUE;
++			coex_sta->cck_lock_ever = TRUE;
++
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], cck locking...\n");
++			BTC_TRACE(trace_buf);
++		} else {
++			coex_sta->cck_lock_warn = FALSE;
++			coex_sta->cck_lock = FALSE;
++
++			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++				"[BTCoex], cck unlock...\n");
++			BTC_TRACE(trace_buf);
++		}
++	} else {
++		if (coex_dm->bt_status ==
++		    BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE ||
++		    coex_dm->bt_status ==
++		    BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE) {
++			coex_sta->cck_lock_warn = FALSE;
++			coex_sta->cck_lock = FALSE;
++		}
++	}
++
++}
++
++
++
++void ex_halbtc8723d2ant_rf_status_notify(IN struct btc_coexist *btcoexist,
++		IN u8 type)
++{
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
++	BTC_TRACE(trace_buf);
++
++	if (BTC_RF_ON == type) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], RF is turned ON!!\n");
++		BTC_TRACE(trace_buf);
++
++		btcoexist->stop_coex_dm = FALSE;
++		coex_sta->is_rf_state_off = FALSE;
++#if 0
++		halbtc8723d2ant_post_state_to_bt(btcoexist,
++					 BT_8723D_2ANT_SCOREBOARD_ACTIVE, TRUE);
++		halbtc8723d2ant_post_state_to_bt(btcoexist,
++					 BT_8723D_2ANT_SCOREBOARD_ONOFF, TRUE);
++#endif
++	} else if (BTC_RF_OFF == type) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], RF is turned OFF!!\n");
++		BTC_TRACE(trace_buf);
++
++		halbtc8723d2ant_set_ant_path(btcoexist,
++					     BTC_ANT_PATH_AUTO,
++					     FORCE_EXEC,
++					     BT_8723D_2ANT_PHASE_WLAN_OFF);
++
++		halbtc8723d2ant_action_coex_all_off(btcoexist);
++
++		halbtc8723d2ant_post_state_to_bt(btcoexist,
++				BT_8723D_2ANT_SCOREBOARD_ACTIVE |
++				BT_8723D_2ANT_SCOREBOARD_ONOFF |
++				BT_8723D_2ANT_SCOREBOARD_SCAN |
++				BT_8723D_2ANT_SCOREBOARD_UNDERTEST,
++				FALSE);
++
++		btcoexist->stop_coex_dm = TRUE;
++		coex_sta->is_rf_state_off = FALSE;
++	}
++}
++
++void ex_halbtc8723d2ant_halt_notify(IN struct btc_coexist *btcoexist)
++{
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
++	BTC_TRACE(trace_buf);
++
++	halbtc8723d2ant_set_ant_path(btcoexist,
++				     BTC_ANT_PATH_AUTO,
++				     FORCE_EXEC,
++				     BT_8723D_2ANT_PHASE_WLAN_OFF);
++
++	/*halbtc8723d2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, TRUE);*/
++
++	ex_halbtc8723d2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
++
++	halbtc8723d2ant_post_state_to_bt(btcoexist,
++				BT_8723D_2ANT_SCOREBOARD_ACTIVE |
++				BT_8723D_2ANT_SCOREBOARD_ONOFF |
++				BT_8723D_2ANT_SCOREBOARD_SCAN |
++				BT_8723D_2ANT_SCOREBOARD_UNDERTEST,
++				FALSE);
++}
++
++void ex_halbtc8723d2ant_pnp_notify(IN struct btc_coexist *btcoexist,
++				   IN u8 pnp_state)
++{
++	static u8 pre_pnp_state;
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
++	BTC_TRACE(trace_buf);
++
++	if ((BTC_WIFI_PNP_SLEEP == pnp_state) ||
++	    (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], Pnp notify to SLEEP\n");
++		BTC_TRACE(trace_buf);
++
++		/* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */
++		/* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */
++		/* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */
++		coex_sta->under_ips = FALSE;
++		coex_sta->under_lps = FALSE;
++
++		halbtc8723d2ant_post_state_to_bt(btcoexist,
++				BT_8723D_2ANT_SCOREBOARD_ACTIVE |
++				BT_8723D_2ANT_SCOREBOARD_ONOFF |
++				BT_8723D_2ANT_SCOREBOARD_SCAN |
++				BT_8723D_2ANT_SCOREBOARD_UNDERTEST,
++				FALSE);
++
++		if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) {
++
++			halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
++						     FORCE_EXEC,
++					     BT_8723D_2ANT_PHASE_2G_RUNTIME);
++		} else {
++
++			halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
++						     FORCE_EXEC,
++					     BT_8723D_2ANT_PHASE_WLAN_OFF);
++		}
++
++		btcoexist->stop_coex_dm = TRUE;
++
++	} else {
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], Pnp notify to WAKE UP\n");
++		BTC_TRACE(trace_buf);
++
++		coex_sta->pnp_awake_period_cnt = 3;
++
++		/*WoWLAN*/
++		if (pre_pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT ||
++		    pnp_state == BTC_WIFI_PNP_WOWLAN) {
++			coex_sta->run_time_state = TRUE;
++			btcoexist->stop_coex_dm = FALSE;
++			halbtc8723d2ant_run_coexist_mechanism(btcoexist);
++		}
++
++#if 0
++		halbtc8723d2ant_post_state_to_bt(btcoexist,
++					BT_8723D_2ANT_SCOREBOARD_ACTIVE, TRUE);
++		halbtc8723d2ant_post_state_to_bt(btcoexist,
++					BT_8723D_2ANT_SCOREBOARD_ONOFF, TRUE);
++#endif
++	}
++
++	pre_pnp_state = pnp_state;
++}
++
++void ex_halbtc8723d2ant_periodical(IN struct btc_coexist *btcoexist)
++{
++	struct  btc_board_info	*board_info = &btcoexist->board_info;
++	boolean wifi_busy = FALSE, bt_ctr_change = FALSE;
++	u32	bt_patch_ver;
++	static u8 cnt = 0;
++	boolean bt_relink_finish = FALSE;
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], ************* Periodical *************\n");
++	BTC_TRACE(trace_buf);
++
++#if (BT_AUTO_REPORT_ONLY_8723D_2ANT == 0)
++	halbtc8723d2ant_query_bt_info(btcoexist);
++#endif
++
++	bt_ctr_change = halbtc8723d2ant_monitor_bt_ctr(btcoexist);
++	halbtc8723d2ant_monitor_wifi_ctr(btcoexist);
++	halbtc8723d2ant_monitor_bt_enable_disable(btcoexist);
++
++	if (coex_sta->bt_relink_downcount != 0) {
++		coex_sta->bt_relink_downcount--;
++
++		if (coex_sta->bt_relink_downcount == 0) {
++			coex_sta->is_setup_link = FALSE;
++			bt_relink_finish = TRUE;
++		}
++	}
++	
++	if (coex_sta->bt_inq_page_downcount != 0) {
++		coex_sta->bt_inq_page_downcount--;
++		if (coex_sta->bt_relink_downcount == 0)
++			coex_sta->bt_inq_page_remain = FALSE;
++	}
++
++	if (coex_sta->pnp_awake_period_cnt > 0)
++		coex_sta->pnp_awake_period_cnt--;
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "[BTCoex], pnp_awake_period_cnt = %d\n",
++				coex_sta->pnp_awake_period_cnt);
++	BTC_TRACE(trace_buf);
++
++	/*for A2DP glitch during connecting AP*/
++	if (coex_sta->connect_ap_period_cnt > 0)
++		coex_sta->connect_ap_period_cnt--;
++
++	/* for 4-way, DHCP, EAPOL packet */
++	if (coex_sta->specific_pkt_period_cnt > 0) {
++
++		coex_sta->specific_pkt_period_cnt--;
++
++		if ((coex_sta->specific_pkt_period_cnt == 0) &&
++		    (coex_sta->wifi_is_high_pri_task))
++			coex_sta->wifi_is_high_pri_task = FALSE;
++
++		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++			   "[BTCoex], ***************** Hi-Pri Task = %s\n",
++			    (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"));
++		BTC_TRACE(trace_buf);
++
++	}
++
++	if (halbtc8723d2ant_is_wifibt_status_changed(btcoexist) ||
++	    bt_relink_finish || bt_ctr_change)
++		halbtc8723d2ant_run_coexist_mechanism(btcoexist);
++}
++
++void ex_halbtc8723d2ant_set_antenna_notify(IN struct btc_coexist *btcoexist,
++		IN u8 type)
++{
++	struct  btc_board_info	*board_info = &btcoexist->board_info;
++
++	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
++		return;
++
++	if (type == 2) { /* two antenna */
++		board_info->ant_div_cfg = TRUE;
++
++		halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI,
++					     FORCE_EXEC,
++					     BT_8723D_2ANT_PHASE_2G_RUNTIME);
++
++	} else { /* one antenna */
++		halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
++					     FORCE_EXEC,
++					     BT_8723D_2ANT_PHASE_2G_RUNTIME);
++	}
++}
++
++#ifdef PLATFORM_WINDOWS
++#pragma optimize("", off)
++#endif
++void ex_halbtc8723d2ant_antenna_detection(IN struct btc_coexist *btcoexist,
++		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
++{
++
++	static u32 ant_det_count = 0, ant_det_fail_count = 0;
++	struct  btc_board_info	*board_info = &btcoexist->board_info;
++	u16		u16tmp;
++	u8			AntDetval = 0;
++
++	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
++		    "xxxxxxxxxxxxxxxx Ext Call AntennaDetect()!!\n");
++	BTC_TRACE(trace_buf);
++}
++
++
++void ex_halbtc8723d2ant_display_ant_detection(IN struct btc_coexist *btcoexist)
++{
++#if 0
++	struct  btc_board_info	*board_info = &btcoexist->board_info;
++
++	if (psd_scan->ant_det_try_count != 0)	{
++		halbtc8723d2ant_psd_show_antenna_detect_result(btcoexist);
++
++		if (board_info->btdm_ant_det_finish)
++			halbtc8723d2ant_psd_showdata(btcoexist);
++	}
++#endif
++}
++
++
++#endif
++
++#endif	/*  #if (RTL8723D_SUPPORT == 1) */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/halbtc8723d2ant.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/halbtc8723d2ant.h
+new file mode 100644
+index 000000000..4de14054c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/halbtc8723d2ant.h
+@@ -0,0 +1,486 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++
++#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
++
++#if (RTL8723D_SUPPORT == 1)
++
++/* *******************************************
++ * The following is for 8723D 2Ant BT Co-exist definition
++ * ******************************************* */
++#define	BT_8723D_2ANT_COEX_DBG					0
++#define	BT_AUTO_REPORT_ONLY_8723D_2ANT				1
++
++
++#define	BT_INFO_8723D_2ANT_B_FTP				BIT(7)
++#define	BT_INFO_8723D_2ANT_B_A2DP				BIT(6)
++#define	BT_INFO_8723D_2ANT_B_HID				BIT(5)
++#define	BT_INFO_8723D_2ANT_B_SCO_BUSY				BIT(4)
++#define	BT_INFO_8723D_2ANT_B_ACL_BUSY				BIT(3)
++#define	BT_INFO_8723D_2ANT_B_INQ_PAGE				BIT(2)
++#define	BT_INFO_8723D_2ANT_B_SCO_ESCO				BIT(1)
++#define	BT_INFO_8723D_2ANT_B_CONNECTION				BIT(0)
++
++#define		BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT		2
++
++
++#define	BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1		80
++#define	BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1			80
++#define	BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES2		80
++#define	BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES2			80
++#define	BT_8723D_2ANT_DEFAULT_ISOLATION				15
++#define   BT_8723D_2ANT_WIFI_MAX_TX_POWER				15
++#define   BT_8723D_2ANT_BT_MAX_TX_POWER				3
++#define   BT_8723D_2ANT_WIFI_SIR_THRES1				-15
++#define   BT_8723D_2ANT_WIFI_SIR_THRES2				-30
++#define   BT_8723D_2ANT_BT_SIR_THRES1				-15
++#define   BT_8723D_2ANT_BT_SIR_THRES2				-30
++
++
++/* for Antenna detection */
++#define	BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND		50
++#define	BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION		70
++#define	BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION	52
++#define	BT_8723D_2ANT_ANTDET_PSDTHRES_1ANT			40
++#define	BT_8723D_2ANT_ANTDET_RETRY_INTERVAL			10
++#define	BT_8723D_2ANT_ANTDET_SWEEPPOINT_DELAY			60000
++#define	BT_8723D_2ANT_ANTDET_ENABLE				0
++#define	BT_8723D_2ANT_ANTDET_BTTXTIME				100
++#define	BT_8723D_2ANT_ANTDET_BTTXCHANNEL			39
++#define	BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT			50
++
++
++#define	BT_8723D_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT	30000
++
++enum bt_8723d_2ant_signal_state {
++	BT_8723D_2ANT_SIG_STA_SET_TO_LOW	= 0x0,
++	BT_8723D_2ANT_SIG_STA_SET_BY_HW		= 0x0,
++	BT_8723D_2ANT_SIG_STA_SET_TO_HIGH	= 0x1,
++	BT_8723D_2ANT_SIG_STA_MAX
++};
++
++enum bt_8723d_2ant_path_ctrl_owner {
++	BT_8723D_2ANT_PCO_BTSIDE		= 0x0,
++	BT_8723D_2ANT_PCO_WLSIDE		= 0x1,
++	BT_8723D_2ANT_PCO_MAX
++};
++
++enum bt_8723d_2ant_gnt_ctrl_type {
++	BT_8723D_2ANT_GNT_TYPE_CTRL_BY_PTA	= 0x0,
++	BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW	= 0x1,
++	BT_8723D_2ANT_GNT_TYPE_MAX
++};
++
++enum bt_8723d_2ant_gnt_ctrl_block {
++	BT_8723D_2ANT_GNT_BLOCK_RFC_BB		= 0x0,
++	BT_8723D_2ANT_GNT_BLOCK_RFC		= 0x1,
++	BT_8723D_2ANT_GNT_BLOCK_BB		= 0x2,
++	BT_8723D_2ANT_GNT_BLOCK_MAX
++};
++
++enum bt_8723d_2ant_lte_coex_table_type {
++	BT_8723D_2ANT_CTT_WL_VS_LTE		= 0x0,
++	BT_8723D_2ANT_CTT_BT_VS_LTE		= 0x1,
++	BT_8723D_2ANT_CTT_MAX
++};
++
++enum bt_8723d_2ant_lte_break_table_type {
++	BT_8723D_2ANT_LBTT_WL_BREAK_LTE		= 0x0,
++	BT_8723D_2ANT_LBTT_BT_BREAK_LTE		= 0x1,
++	BT_8723D_2ANT_LBTT_LTE_BREAK_WL		= 0x2,
++	BT_8723D_2ANT_LBTT_LTE_BREAK_BT		= 0x3,
++	BT_8723D_2ANT_LBTT_MAX
++};
++
++enum bt_info_src_8723d_2ant {
++	BT_INFO_SRC_8723D_2ANT_WIFI_FW		= 0x0,
++	BT_INFO_SRC_8723D_2ANT_BT_RSP		= 0x1,
++	BT_INFO_SRC_8723D_2ANT_BT_ACTIVE_SEND	= 0x2,
++	BT_INFO_SRC_8723D_2ANT_MAX
++};
++
++enum bt_8723d_2ant_bt_status {
++	BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE	= 0x0,
++	BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE		= 0x1,
++	BT_8723D_2ANT_BT_STATUS_INQ_PAGE		= 0x2,
++	BT_8723D_2ANT_BT_STATUS_ACL_BUSY		= 0x3,
++	BT_8723D_2ANT_BT_STATUS_SCO_BUSY		= 0x4,
++	BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY		= 0x5,
++	BT_8723D_2ANT_BT_STATUS_MAX
++};
++
++enum bt_8723d_2ant_coex_algo {
++	BT_8723D_2ANT_COEX_ALGO_UNDEFINED		= 0x0,
++	BT_8723D_2ANT_COEX_ALGO_SCO			= 0x1,
++	BT_8723D_2ANT_COEX_ALGO_HID			= 0x2,
++	BT_8723D_2ANT_COEX_ALGO_A2DP			= 0x3,
++	BT_8723D_2ANT_COEX_ALGO_A2DP_PANHS		= 0x4,
++	BT_8723D_2ANT_COEX_ALGO_PANEDR			= 0x5,
++	BT_8723D_2ANT_COEX_ALGO_PANHS			= 0x6,
++	BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP		= 0x7,
++	BT_8723D_2ANT_COEX_ALGO_PANEDR_HID		= 0x8,
++	BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR		= 0x9,
++	BT_8723D_2ANT_COEX_ALGO_HID_A2DP		= 0xa,
++	BT_8723D_2ANT_COEX_ALGO_NOPROFILEBUSY		= 0xb,
++	BT_8723D_2ANT_COEX_ALGO_A2DPSINK		= 0xc,
++	BT_8723D_2ANT_COEX_ALGO_MAX
++};
++
++enum bt_8723d_2ant_phase {
++	BT_8723D_2ANT_PHASE_COEX_INIT			= 0x0,
++	BT_8723D_2ANT_PHASE_WLANONLY_INIT		= 0x1,
++	BT_8723D_2ANT_PHASE_WLAN_OFF			= 0x2,
++	BT_8723D_2ANT_PHASE_2G_RUNTIME			= 0x3,
++	BT_8723D_2ANT_PHASE_5G_RUNTIME			= 0x4,
++	BT_8723D_2ANT_PHASE_BTMPMODE			= 0x5,
++	BT_8723D_2ANT_PHASE_ANTENNA_DET			= 0x6,
++	BT_8723D_2ANT_PHASE_COEX_POWERON		= 0x7,
++	BT_8723D_2ANT_PHASE_2G_FREERUN			= 0x8,
++	BT_8723D_2ANT_PHASE_MAX
++};
++
++enum bt_8723d_2ant_Scoreboard {
++	BT_8723D_2ANT_SCOREBOARD_ACTIVE			= BIT(0),
++	BT_8723D_2ANT_SCOREBOARD_ONOFF			= BIT(1),
++	BT_8723D_2ANT_SCOREBOARD_SCAN			= BIT(2),
++	BT_8723D_2ANT_SCOREBOARD_UNDERTEST		= BIT(3),
++	BT_8723D_2ANT_SCOREBOARD_RXGAIN			= BIT(4),
++	BT_8723D_2ANT_SCOREBOARD_WLBUSY			= BIT(6),
++	BT_8723D_2ANT_SCOREBOARD_TDMA			= BIT(9),
++};
++
++
++
++struct coex_dm_8723d_2ant {
++	/* fw mechanism */
++	u8		pre_bt_dec_pwr_lvl;
++	u8		cur_bt_dec_pwr_lvl;
++	u8		pre_fw_dac_swing_lvl;
++	u8		cur_fw_dac_swing_lvl;
++	boolean		cur_ignore_wlan_act;
++	boolean		pre_ignore_wlan_act;
++	u8		cur_ps_tdma;
++	u8		ps_tdma_para[5];
++	u8		ps_tdma_du_adj_type;
++	boolean		reset_tdma_adjust;
++	boolean		cur_ps_tdma_on;
++	boolean		pre_bt_auto_report;
++	boolean		cur_bt_auto_report;
++
++	/* sw mechanism */
++	boolean		pre_rf_rx_lpf_shrink;
++	boolean		cur_rf_rx_lpf_shrink;
++	u32		bt_rf_0x1e_backup;
++	boolean		pre_low_penalty_ra;
++	boolean		cur_low_penalty_ra;
++	boolean		pre_dac_swing_on;
++	u32		pre_dac_swing_lvl;
++	boolean		cur_dac_swing_on;
++	u32		cur_dac_swing_lvl;
++	boolean		pre_adc_back_off;
++	boolean		cur_adc_back_off;
++	boolean		pre_agc_table_en;
++	boolean		cur_agc_table_en;
++	u32		cur_val0x6c0;
++	u32		cur_val0x6c4;
++	u32		cur_val0x6c8;
++	u8		cur_val0x6cc;
++	boolean		limited_dig;
++
++	/* algorithm related */
++	u8		pre_algorithm;
++	u8		cur_algorithm;
++	u8		bt_status;
++	u8		wifi_chnl_info[3];
++
++	boolean		need_recover0x948;
++	u32		backup0x948;
++
++	u8		pre_lps;
++	u8		cur_lps;
++	u8		pre_rpwm;
++	u8		cur_rpwm;
++
++	boolean		is_switch_to_1dot5_ant;
++	u8		switch_thres_offset;
++	u32		arp_cnt;
++
++	u8		pre_ant_pos_type;
++	u8		cur_ant_pos_type;
++	u32		setting_tdma;
++};
++
++struct coex_sta_8723d_2ant {
++	boolean		bt_disabled;
++	boolean		bt_link_exist;
++	boolean		sco_exist;
++	boolean		a2dp_exist;
++	boolean		hid_exist;
++	boolean		pan_exist;
++
++	boolean		under_lps;
++	boolean		under_ips;
++	u8		connect_ap_period_cnt;
++	u8		pnp_awake_period_cnt;
++	u32		high_priority_tx;
++	u32		high_priority_rx;
++	u32		low_priority_tx;
++	u32		low_priority_rx;
++	boolean		bt_ctr_ok;
++	boolean         is_hipri_rx_overhead;
++	u8		bt_rssi;
++	boolean		bt_tx_rx_mask;
++	u8		pre_bt_rssi_state;
++	u8		pre_wifi_rssi_state[4];
++	u8		bt_info_c2h[BT_INFO_SRC_8723D_2ANT_MAX][10];
++	u32		bt_info_c2h_cnt[BT_INFO_SRC_8723D_2ANT_MAX];
++	boolean		bt_whck_test;
++	boolean		c2h_bt_inquiry_page;
++	boolean		bt_inq_page_pre;
++	boolean 	bt_inq_page_remain;
++	boolean		c2h_bt_remote_name_req;
++	u8		bt_retry_cnt;
++	u8		bt_info_ext;
++	u8		bt_info_ext2;
++	u32		pop_event_cnt;
++	u8		scan_ap_num;
++
++	u32		crc_ok_cck;
++	u32		crc_ok_11g;
++	u32		crc_ok_11n;
++	u32		crc_ok_11n_vht;
++
++	u32		crc_err_cck;
++	u32		crc_err_11g;
++	u32		crc_err_11n;
++	u32		crc_err_11n_vht;
++
++	u32		acc_crc_ratio;
++	u32		now_crc_ratio;
++	u32		cnt_crcok_max_in_10s;
++
++	boolean		cck_lock;
++	boolean		cck_lock_ever;
++	boolean		cck_lock_warn;
++
++	u8		coex_table_type;
++	boolean		force_lps_ctrl;
++
++	u8		dis_ver_info_cnt;
++
++	u8		a2dp_bit_pool;
++	u8		kt_ver;
++
++	boolean		concurrent_rx_mode_on;
++
++	u16		score_board;
++	u8		isolation_btween_wb;   /* 0~ 50 */
++	u8		wifi_coex_thres;
++	u8		bt_coex_thres;
++	u8		wifi_coex_thres2;
++	u8		bt_coex_thres2;
++
++	u8		num_of_profile;
++	boolean		acl_busy;
++	boolean		bt_create_connection;
++	boolean		wifi_is_high_pri_task;
++	u32		specific_pkt_period_cnt;
++	u32		bt_coex_supported_feature;
++	u32		bt_coex_supported_version;
++
++	u8		bt_ble_scan_type;
++	u32		bt_ble_scan_para[3];
++
++	boolean		run_time_state;
++	boolean		freeze_coexrun_by_btinfo;
++
++	boolean		is_A2DP_3M;
++	boolean		voice_over_HOGP;
++	u8		bt_info;
++	u8		forbidden_slot;
++	u8		hid_busy_num;
++	u8		hid_pair_cnt;
++
++	u32		cnt_remotenamereq;
++	u32		cnt_setuplink;
++	u32		cnt_reinit;
++	u32		cnt_ignwlanact;
++	u32		cnt_page;
++	u32		cnt_roleswitch;
++
++	u16		bt_reg_vendor_ac;
++	u16		bt_reg_vendor_ae;
++
++	boolean		is_setup_link;
++	boolean		wl_noisy_level;
++	u32		gnt_error_cnt;
++
++	u8		bt_afh_map[10];
++	u8		bt_relink_downcount;
++	u8		bt_inq_page_downcount;
++	boolean		is_tdma_btautoslot;
++	boolean		is_tdma_btautoslot_hang;
++
++	boolean		is_esco_mode;
++
++	boolean		is_rf_state_off;
++
++	boolean		is_hid_low_pri_tx_overhead;
++	boolean		is_bt_multi_link;
++	boolean		is_bt_a2dp_sink;
++
++	u8		wl_fw_dbg_info[10];
++	u8		wl_rx_rate;
++	u8		wl_rts_rx_rate;
++
++	u16		score_board_WB;
++	boolean		is_2g_freerun;
++
++	boolean		is_hid_rcu;
++	boolean		is_ble_scan_en;
++
++	u16		legacy_forbidden_slot;
++	u16		le_forbidden_slot;
++	u8		bt_a2dp_vendor_id;
++	u32		bt_a2dp_device_name;
++	boolean		is_bt_opp_exist;
++	boolean		is_no_wl_5ms_extend;
++
++	u16		wl_0x42a_backup;
++	u32		wl_0x430_backup;
++	u32		wl_0x434_backup;
++	u8		wl_0x456_backup;
++
++	boolean		wl_tx_limit_en;
++	boolean		wl_ampdu_limit_en;
++	boolean		wl_rxagg_limit_en;
++	u8		wl_rxagg_size;
++	
++	u8	tdma_timer_base;
++	u8	wl_iot_peer;
++};
++
++#define BT_8723D_2ANT_ANTDET_PSD_POINTS		256	/* MAX:1024 */
++#define BT_8723D_2ANT_ANTDET_PSD_AVGNUM		1	/* MAX:3 */
++#define BT_8723D_2ANT_ANTDET_BUF_LEN		16
++
++struct psdscan_sta_8723d_2ant {
++
++	u32	ant_det_bt_le_channel;  /* BT LE Channel ex:2412 */
++	u32	ant_det_bt_tx_time;
++	u32	ant_det_pre_psdscan_peak_val;
++	boolean	ant_det_is_ant_det_available;
++	u32	ant_det_psd_scan_peak_val;
++	boolean	ant_det_is_btreply_available;
++	u32	ant_det_psd_scan_peak_freq;
++
++	u8	ant_det_result;
++	u8	ant_det_peak_val[BT_8723D_2ANT_ANTDET_BUF_LEN];
++	u8	ant_det_peak_freq[BT_8723D_2ANT_ANTDET_BUF_LEN];
++	u32	ant_det_try_count;
++	u32	ant_det_fail_count;
++	u32	ant_det_inteval_count;
++	u32	ant_det_thres_offset;
++
++	u32	real_cent_freq;
++	s32	real_offset;
++	u32	real_span;
++
++	u32	psd_band_width;
++	u32	psd_point;
++	u32	psd_report[1024];
++	u32	psd_report_max_hold[1024];
++	u32	psd_start_point;
++	u32	psd_stop_point;
++	u32	psd_max_value_point;
++	u32	psd_max_value;
++	u32	psd_max_value2;
++	u32	psd_avg_value;
++	u32	psd_loop_max_value[BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT];
++	u32	psd_start_base;
++	u32	psd_avg_num;	/* 1/8/16/32 */
++	u32	psd_gen_count;
++	boolean	is_antdet_running;
++	boolean	is_psd_show_max_only;
++};
++
++
++/* *******************************************
++ * The following is interface which will notify coex module.
++ * ******************************************* */
++void ex_halbtc8723d2ant_power_on_setting(IN struct btc_coexist *btcoexist);
++void ex_halbtc8723d2ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
++void ex_halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist,
++				       IN boolean wifi_only);
++void ex_halbtc8723d2ant_init_coex_dm(IN struct btc_coexist *btcoexist);
++void ex_halbtc8723d2ant_ips_notify(IN struct btc_coexist *btcoexist,
++				   IN u8 type);
++void ex_halbtc8723d2ant_lps_notify(IN struct btc_coexist *btcoexist,
++				   IN u8 type);
++void ex_halbtc8723d2ant_scan_notify(IN struct btc_coexist *btcoexist,
++				    IN u8 type);
++void ex_halbtc8723d2ant_connect_notify(IN struct btc_coexist *btcoexist,
++				       IN u8 type);
++void ex_halbtc8723d2ant_media_status_notify(IN struct btc_coexist *btcoexist,
++		IN u8 type);
++void ex_halbtc8723d2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
++		IN u8 type);
++void ex_halbtc8723d2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
++				       IN u8 *tmp_buf, IN u8 length);
++void ex_halbtc8723d2ant_wl_fwdbginfo_notify(IN struct btc_coexist *btcoexist,
++				       IN u8 *tmp_buf, IN u8 length);
++void ex_halbtc8723d2ant_rx_rate_change_notify(IN struct btc_coexist *btcoexist,
++		IN BOOLEAN is_data_frame, IN u8 btc_rate_id);
++void ex_halbtc8723d2ant_rf_status_notify(IN struct btc_coexist *btcoexist,
++		IN u8 type);
++void ex_halbtc8723d2ant_halt_notify(IN struct btc_coexist *btcoexist);
++void ex_halbtc8723d2ant_pnp_notify(IN struct btc_coexist *btcoexist,
++				   IN u8 pnp_state);
++void ex_halbtc8723d2ant_set_antenna_notify(IN struct btc_coexist *btcoexist,
++		IN u8 type);
++void ex_halbtc8723d2ant_periodical(IN struct btc_coexist *btcoexist);
++void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist);
++void ex_halbtc8723d2ant_antenna_detection(IN struct btc_coexist *btcoexist,
++		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
++void ex_halbtc8723d2ant_display_ant_detection(IN struct btc_coexist *btcoexist);
++
++
++#else
++#define	ex_halbtc8723d2ant_power_on_setting(btcoexist)
++#define	ex_halbtc8723d2ant_pre_load_firmware(btcoexist)
++#define	ex_halbtc8723d2ant_init_hw_config(btcoexist, wifi_only)
++#define	ex_halbtc8723d2ant_init_coex_dm(btcoexist)
++#define	ex_halbtc8723d2ant_ips_notify(btcoexist, type)
++#define	ex_halbtc8723d2ant_lps_notify(btcoexist, type)
++#define	ex_halbtc8723d2ant_scan_notify(btcoexist, type)
++#define	ex_halbtc8723d2ant_connect_notify(btcoexist, type)
++#define	ex_halbtc8723d2ant_media_status_notify(btcoexist, type)
++#define	ex_halbtc8723d2ant_specific_packet_notify(btcoexist, type)
++#define	ex_halbtc8723d2ant_bt_info_notify(btcoexist, tmp_buf, length)
++#define ex_halbtc8723d2ant_wl_fwdbginfo_notify(btcoexist, tmp_buf, length)
++#define	ex_halbtc8723d2ant_rx_rate_change_notify(btcoexist, is_data_frame, btc_rate_id)
++#define	ex_halbtc8723d2ant_rf_status_notify(btcoexist, type)
++#define	ex_halbtc8723d2ant_halt_notify(btcoexist)
++#define	ex_halbtc8723d2ant_pnp_notify(btcoexist, pnp_state)
++#define	ex_halbtc8723d2ant_periodical(btcoexist)
++#define	ex_halbtc8723d2ant_display_coex_info(btcoexist)
++#define	ex_halbtc8723d2ant_set_antenna_notify(btcoexist, type)
++#define	ex_halbtc8723d2ant_display_ant_detection(btcoexist)
++#define	ex_halbtc8723d2ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds)
++#endif
++
++#endif
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/halbtcoutsrc.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/halbtcoutsrc.h
+new file mode 100644
+index 000000000..dfeba6bbf
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/halbtcoutsrc.h
+@@ -0,0 +1,2061 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef	__HALBTC_OUT_SRC_H__
++#define __HALBTC_OUT_SRC_H__
++
++enum {
++	BTC_CCK_1,
++	BTC_CCK_2,
++	BTC_CCK_5_5,
++	BTC_CCK_11,
++	BTC_OFDM_6,
++	BTC_OFDM_9,
++	BTC_OFDM_12,
++	BTC_OFDM_18,
++	BTC_OFDM_24,
++	BTC_OFDM_36,
++	BTC_OFDM_48,
++	BTC_OFDM_54,
++	BTC_MCS_0,
++	BTC_MCS_1,
++	BTC_MCS_2,
++	BTC_MCS_3,
++	BTC_MCS_4,
++	BTC_MCS_5,
++	BTC_MCS_6,
++	BTC_MCS_7,
++	BTC_MCS_8,
++	BTC_MCS_9,
++	BTC_MCS_10,
++	BTC_MCS_11,
++	BTC_MCS_12,
++	BTC_MCS_13,
++	BTC_MCS_14,
++	BTC_MCS_15,
++	BTC_MCS_16,
++	BTC_MCS_17,
++	BTC_MCS_18,
++	BTC_MCS_19,
++	BTC_MCS_20,
++	BTC_MCS_21,
++	BTC_MCS_22,
++	BTC_MCS_23,
++	BTC_MCS_24,
++	BTC_MCS_25,
++	BTC_MCS_26,
++	BTC_MCS_27,
++	BTC_MCS_28,
++	BTC_MCS_29,
++	BTC_MCS_30,
++	BTC_MCS_31,
++	BTC_VHT_1SS_MCS_0,
++	BTC_VHT_1SS_MCS_1,
++	BTC_VHT_1SS_MCS_2,
++	BTC_VHT_1SS_MCS_3,
++	BTC_VHT_1SS_MCS_4,
++	BTC_VHT_1SS_MCS_5,
++	BTC_VHT_1SS_MCS_6,
++	BTC_VHT_1SS_MCS_7,
++	BTC_VHT_1SS_MCS_8,
++	BTC_VHT_1SS_MCS_9,
++	BTC_VHT_2SS_MCS_0,
++	BTC_VHT_2SS_MCS_1,
++	BTC_VHT_2SS_MCS_2,
++	BTC_VHT_2SS_MCS_3,
++	BTC_VHT_2SS_MCS_4,
++	BTC_VHT_2SS_MCS_5,
++	BTC_VHT_2SS_MCS_6,
++	BTC_VHT_2SS_MCS_7,
++	BTC_VHT_2SS_MCS_8,
++	BTC_VHT_2SS_MCS_9,
++	BTC_VHT_3SS_MCS_0,
++	BTC_VHT_3SS_MCS_1,
++	BTC_VHT_3SS_MCS_2,
++	BTC_VHT_3SS_MCS_3,
++	BTC_VHT_3SS_MCS_4,
++	BTC_VHT_3SS_MCS_5,
++	BTC_VHT_3SS_MCS_6,
++	BTC_VHT_3SS_MCS_7,
++	BTC_VHT_3SS_MCS_8,
++	BTC_VHT_3SS_MCS_9,
++	BTC_VHT_4SS_MCS_0,
++	BTC_VHT_4SS_MCS_1,
++	BTC_VHT_4SS_MCS_2,
++	BTC_VHT_4SS_MCS_3,
++	BTC_VHT_4SS_MCS_4,
++	BTC_VHT_4SS_MCS_5,
++	BTC_VHT_4SS_MCS_6,
++	BTC_VHT_4SS_MCS_7,
++	BTC_VHT_4SS_MCS_8,
++	BTC_VHT_4SS_MCS_9,
++	BTC_MCS_32,
++	BTC_UNKNOWN,
++	BTC_PKT_MGNT,
++	BTC_PKT_CTRL,
++	BTC_PKT_UNKNOWN,
++	BTC_PKT_NOT_FOR_ME,
++	BTC_RATE_MAX
++};
++
++enum {
++	BTC_MULTIPORT_SCC,
++	BTC_MULTIPORT_MCC_DUAL_CHANNEL,
++	BTC_MULTIPORT_MCC_DUAL_BAND,
++	BTC_MULTIPORT_MAX
++};
++
++#define		BTC_COEX_8822B_COMMON_CODE	0
++#define		BTC_COEX_OFFLOAD			0
++#define		BTC_TMP_BUF_SHORT		20
++
++extern u1Byte	gl_btc_trace_buf[];
++#define		BTC_SPRINTF			rsprintf
++#define		BTC_TRACE(_MSG_)\
++do {\
++	if (GLBtcDbgType[COMP_COEX] & BIT(DBG_LOUD)) {\
++		RTW_INFO("%s", _MSG_);\
++	} \
++} while (0)
++#define		BT_PrintData(adapter, _MSG_, len, data)	RTW_DBG_DUMP((_MSG_), data, len)
++
++
++#define		NORMAL_EXEC					FALSE
++#define		FORCE_EXEC						TRUE
++
++#define		NM_EXCU						FALSE
++#define		FC_EXCU						TRUE
++
++#define		BTC_RF_OFF					0x0
++#define		BTC_RF_ON					0x1
++
++#define		BTC_RF_A					0x0
++#define		BTC_RF_B					0x1
++#define		BTC_RF_C					0x2
++#define		BTC_RF_D					0x3
++
++#define		BTC_SMSP				SINGLEMAC_SINGLEPHY
++#define		BTC_DMDP				DUALMAC_DUALPHY
++#define		BTC_DMSP				DUALMAC_SINGLEPHY
++#define		BTC_MP_UNKNOWN		0xff
++
++#define		BT_COEX_ANT_TYPE_PG			0
++#define		BT_COEX_ANT_TYPE_ANTDIV		1
++#define		BT_COEX_ANT_TYPE_DETECTED	2
++
++#define		BTC_MIMO_PS_STATIC			0	/* 1ss */
++#define		BTC_MIMO_PS_DYNAMIC			1	/* 2ss */
++
++#define		BTC_RATE_DISABLE			0
++#define		BTC_RATE_ENABLE				1
++
++/* single Antenna definition */
++#define		BTC_ANT_PATH_WIFI			0
++#define		BTC_ANT_PATH_BT				1
++#define		BTC_ANT_PATH_PTA			2
++#define		BTC_ANT_PATH_WIFI5G			3
++#define		BTC_ANT_PATH_AUTO			4
++/* dual Antenna definition */
++#define		BTC_ANT_WIFI_AT_MAIN		0
++#define		BTC_ANT_WIFI_AT_AUX			1
++#define		BTC_ANT_WIFI_AT_DIVERSITY	2
++/* coupler Antenna definition */
++#define		BTC_ANT_WIFI_AT_CPL_MAIN	0
++#define		BTC_ANT_WIFI_AT_CPL_AUX		1
++
++/* for common code request */
++#define REG_LTE_IDR_COEX_CTRL	0x0038
++#define REG_SYS_SDIO_CTRL		0x0070
++#define REG_SYS_SDIO_CTRL3		0x0073
++/* #define REG_RETRY_LIMIT		0x042a */
++/* #define REG_DARFRC			0x0430 */
++#define REG_DARFRCH				0x0434
++#define REG_CCK_CHECK			0x0454
++#define REG_AMPDU_MAX_TIME_V1	0x0455
++#define REG_TX_HANG_CTRL		0x045E
++#define REG_LIFETIME_EN			0x0426
++#define REG_BT_COEX_TABLE0		0x06C0
++#define REG_BT_COEX_TABLE1		0x06C4
++#define REG_BT_COEX_BRK_TABLE	0x06C8
++#define REG_BT_COEX_TABLE_H		0x06CC
++#define REG_BT_ACT_STATISTICS	0x0770
++#define REG_BT_ACT_STATISTICS_1	0x0774
++#define REG_BT_STAT_CTRL		0x0778
++
++#define BIT_EN_GNT_BT_AWAKE	BIT(3)
++#define BIT_EN_BCN_FUNCTION	BIT(3)
++#define BIT_EN_BCN_PKT_REL	BIT(6)
++#define BIT_FEN_BB_GLB_RST	BIT(1)
++#define BIT_FEN_BB_RSTB		BIT(0)
++
++#define TDMA_4SLOT			BIT(8)
++
++typedef enum _BTC_POWERSAVE_TYPE {
++	BTC_PS_WIFI_NATIVE			= 0,	/* wifi original power save behavior */
++	BTC_PS_LPS_ON				= 1,
++	BTC_PS_LPS_OFF				= 2,
++	BTC_PS_MAX
++} BTC_POWERSAVE_TYPE, *PBTC_POWERSAVE_TYPE;
++
++typedef enum _BTC_BT_REG_TYPE {
++	BTC_BT_REG_RF						= 0,
++	BTC_BT_REG_MODEM					= 1,
++	BTC_BT_REG_BLUEWIZE					= 2,
++	BTC_BT_REG_VENDOR					= 3,
++	BTC_BT_REG_LE						= 4,
++	BTC_BT_REG_MAX
++} BTC_BT_REG_TYPE, *PBTC_BT_REG_TYPE;
++
++typedef enum _BTC_CHIP_INTERFACE {
++	BTC_INTF_UNKNOWN	= 0,
++	BTC_INTF_PCI			= 1,
++	BTC_INTF_USB			= 2,
++	BTC_INTF_SDIO		= 3,
++	BTC_INTF_MAX
++} BTC_CHIP_INTERFACE, *PBTC_CHIP_INTERFACE;
++
++typedef enum _BTC_CHIP_TYPE {
++	BTC_CHIP_UNDEF		= 0,
++	BTC_CHIP_CSR_BC4		= 1,
++	BTC_CHIP_CSR_BC8		= 2,
++	BTC_CHIP_RTL8723A		= 3,
++	BTC_CHIP_RTL8821		= 4,
++	BTC_CHIP_RTL8723B		= 5,
++	BTC_CHIP_RTL8822B 		= 6,
++	BTC_CHIP_RTL8822C 		= 7,
++	BTC_CHIP_RTL8821C 		= 8,
++	BTC_CHIP_RTL8821A 		= 9,
++	BTC_CHIP_RTL8723D 		= 10,
++	BTC_CHIP_RTL8703B 		= 11,
++	BTC_CHIP_RTL8725A 		= 12,
++	BTC_CHIP_MAX
++} BTC_CHIP_TYPE, *PBTC_CHIP_TYPE;
++
++/* following is for wifi link status */
++#define		WIFI_STA_CONNECTED				BIT0
++#define		WIFI_AP_CONNECTED				BIT1
++#define		WIFI_HS_CONNECTED				BIT2
++#define		WIFI_P2P_GO_CONNECTED			BIT3
++#define		WIFI_P2P_GC_CONNECTED			BIT4
++
++/* following is for command line utility */
++#define	CL_SPRINTF	rsprintf
++#define	CL_PRINTF	DCMD_Printf
++#define CL_STRNCAT(dst, dst_size, src, src_size) rstrncat(dst, src, src_size)
++
++static const char *const glbt_info_src[] = {
++	"BT Info[wifi fw]",
++	"BT Info[bt rsp]",
++	"BT Info[bt auto report]",
++};
++
++#define BTC_INFO_FTP		BIT(7)
++#define BTC_INFO_A2DP		BIT(6)
++#define BTC_INFO_HID		BIT(5)
++#define BTC_INFO_SCO_BUSY		BIT(4)
++#define BTC_INFO_ACL_BUSY		BIT(3)
++#define BTC_INFO_INQ_PAGE		BIT(2)
++#define BTC_INFO_SCO_ESCO		BIT(1)
++#define BTC_INFO_CONNECTION	BIT(0)
++
++#define BTC_BTINFO_LENGTH_MAX 10
++
++enum btc_gnt_setup_state {
++	BTC_GNT_SET_SW_LOW	= 0x0,
++	BTC_GNT_SET_SW_HIGH	= 0x1,
++	BTC_GNT_SET_HW_PTA	= 0x2,
++	BTC_GNT_SET_MAX
++};
++
++enum btc_gnt_setup_state_2 {
++	BTC_GNT_HW_PTA		= 0x0,
++	BTC_GNT_SW_LOW		= 0x1,
++	BTC_GNT_SW_HIGH		= 0x3,
++	BTC_GNT_MAX
++};
++
++enum btc_path_ctrl_owner {
++	BTC_OWNER_BT		= 0x0,
++	BTC_OWNER_WL		= 0x1,
++	BTC_OWNER_MAX
++};
++
++enum btc_gnt_ctrl_type {
++	BTC_GNT_CTRL_BY_PTA	= 0x0,
++	BTC_GNT_CTRL_BY_SW	= 0x1,
++	BTC_GNT_CTRL_MAX
++};
++
++enum btc_gnt_ctrl_block {
++	BTC_GNT_BLOCK_RFC_BB	= 0x0,
++	BTC_GNT_BLOCK_RFC	= 0x1,
++	BTC_GNT_BLOCK_BB	= 0x2,
++	BTC_GNT_BLOCK_MAX
++};
++
++enum btc_lte_coex_table_type {
++	BTC_CTT_WL_VS_LTE	= 0x0,
++	BTC_CTT_BT_VS_LTE	= 0x1,
++	BTC_CTT_MAX
++};
++
++enum btc_lte_break_table_type {
++	BTC_LBTT_WL_BREAK_LTE	= 0x0,
++	BTC_LBTT_BT_BREAK_LTE	= 0x1,
++	BTC_LBTT_LTE_BREAK_WL	= 0x2,
++	BTC_LBTT_LTE_BREAK_BT	= 0x3,
++	BTC_LBTT_MAX
++};
++
++enum btc_btinfo_src {
++	BTC_BTINFO_SRC_WL_FW	= 0x0,
++	BTC_BTINFO_SRC_BT_RSP	= 0x1,
++	BTC_BTINFO_SRC_BT_ACT	= 0x2,
++	BTC_BTINFO_SRC_BT_IQK	= 0x3,
++	BTC_BTINFO_SRC_BT_SCBD	= 0x4,
++	BTC_BTINFO_SRC_H2C60	= 0x5,
++	BTC_BTINFO_SRC_MAX
++};
++
++enum btc_bt_profile {
++	BTC_BTPROFILE_NONE		= 0,
++	BTC_BTPROFILE_HFP		= BIT(0),
++	BTC_BTPROFILE_HID		= BIT(1),
++	BTC_BTPROFILE_A2DP		= BIT(2),
++	BTC_BTPROFILE_PAN		= BIT(3),
++	BTC_BTPROFILE_MAX		= 0xf
++};
++
++static const char *const bt_profile_string[] = {
++	"None",
++	"HFP",
++	"HID",
++	"HID + HFP",
++	"A2DP",
++	"A2DP + HFP",
++	"A2DP + HID",
++	"PAN + HID + HFP",
++	"PAN",
++	"PAN + HFP",
++	"PAN + HID",
++	"PAN + HID + HFP",
++	"PAN + A2DP",
++	"PAN + A2DP + HFP",
++	"PAN + A2DP + HID",
++	"PAN + A2DP + HID + HFP"
++};
++
++enum btc_bt_status {
++	BTC_BTSTATUS_NCON_IDLE		= 0x0,
++	BTC_BTSTATUS_CON_IDLE		= 0x1,
++	BTC_BTSTATUS_INQ_PAGE		= 0x2,
++	BTC_BTSTATUS_ACL_BUSY		= 0x3,
++	BTC_BTSTATUS_SCO_BUSY		= 0x4,
++	BTC_BTSTATUS_ACL_SCO_BUSY	= 0x5,
++	BTC_BTSTATUS_MAX
++};
++
++static const char *const bt_status_string[] = {
++	"BT Non-Connected-idle",
++	"BT Connected-idle",
++	"BT Inq-page",
++	"BT ACL-busy",
++	"BT SCO-busy",
++	"BT ACL-SCO-busy",
++	"BT Non-Defined-state"
++};
++
++enum btc_coex_algo {
++	BTC_COEX_NOPROFILE		= 0x0,
++	BTC_COEX_HFP			= 0x1,
++	BTC_COEX_HID			= 0x2,
++	BTC_COEX_A2DP			= 0x3,
++	BTC_COEX_PAN			= 0x4,
++	BTC_COEX_A2DP_HID		= 0x5,
++	BTC_COEX_A2DP_PAN		= 0x6,
++	BTC_COEX_PAN_HID		= 0x7,
++	BTC_COEX_A2DP_PAN_HID		= 0x8,
++	BTC_COEX_MAX
++};
++
++static const char *const coex_algo_string[] = {
++	"No Profile",
++	"HFP",
++	"HID",
++	"A2DP",
++	"PAN",
++	"A2DP + HID",
++	"A2DP + PAN",
++	"PAN + HID",
++	"A2DP + PAN + HID"
++};
++
++enum btc_ext_ant_switch_type {
++	BTC_SWITCH_NONE	= 0x0,
++	BTC_SWITCH_SPDT	= 0x1,
++	BTC_SWITCH_SP3T	= 0x2,
++	BTC_SWITCH_ANTMAX
++};
++
++enum btc_ext_ant_switch_ctrl_type {
++	BTC_SWITCH_CTRL_BY_BBSW		= 0x0,
++	BTC_SWITCH_CTRL_BY_PTA		= 0x1,
++	BTC_SWITCH_CTRL_BY_ANTDIV	= 0x2,
++	BTC_SWITCH_CTRL_BY_MAC		= 0x3,
++	BTC_SWITCH_CTRL_BY_BT		= 0x4,
++	BTC_SWITCH_CTRL_BY_FW		= 0x5,
++	BTC_SWITCH_CTRL_MAX
++};
++
++enum btc_ext_ant_switch_pos_type {
++	BTC_SWITCH_TO_BT		= 0x0,
++	BTC_SWITCH_TO_WLG		= 0x1,
++	BTC_SWITCH_TO_WLA		= 0x2,
++	BTC_SWITCH_TO_NOCARE		= 0x3,
++	BTC_SWITCH_TO_WLG_BT		= 0x4,
++	BTC_SWITCH_TO_MAX
++};
++
++enum btx_set_ant_phase {
++	BTC_ANT_INIT			= 0x0,
++	BTC_ANT_WONLY			= 0x1,
++	BTC_ANT_WOFF			= 0x2,
++	BTC_ANT_2G			= 0x3,
++	BTC_ANT_5G			= 0x4,
++	BTC_ANT_BTMP			= 0x5,
++	BTC_ANT_POWERON			= 0x6,
++	BTC_ANT_2G_WL			= 0x7,
++	BTC_ANT_2G_BT			= 0x8,
++	BTC_ANT_MCC			= 0x9,
++	BTC_ANT_2G_WLBT			= 0xa,
++	BTC_ANT_2G_FREERUN		= 0xb,
++	BTC_ANT_MAX
++};
++
++/*ADD SCOREBOARD TO FIX BT LPS 32K ISSUE WHILE WL BUSY*/
++enum btc_wl2bt_scoreboard {
++	BTC_SCBD_ACTIVE		= BIT(0),
++	BTC_SCBD_ON			= BIT(1),
++	BTC_SCBD_SCAN		= BIT(2),
++	BTC_SCBD_UNDERTEST	= BIT(3),
++	BTC_SCBD_RXGAIN		= BIT(4),
++	BTC_SCBD_WLBUSY		= BIT(7),
++	BTC_SCBD_EXTFEM		= BIT(8),
++	BTC_SCBD_TDMA		= BIT(9),
++	BTC_SCBD_FIX2M		= BIT(10),
++	BTC_SCBD_ALL		= 0xffff
++};
++
++enum btc_bt2wl_scoreboard {
++	BTC_SCBD_BT_ONOFF	= BIT(1),
++	BTC_SCBD_BT_LPS		= BIT(7)
++};
++
++enum btc_runreason {
++	BTC_RSN_2GSCANSTART	= 0x0,
++	BTC_RSN_5GSCANSTART	= 0x1,
++	BTC_RSN_SCANFINISH	= 0x2,
++	BTC_RSN_2GSWITCHBAND	= 0x3,
++	BTC_RSN_5GSWITCHBAND	= 0x4,
++	BTC_RSN_2GCONSTART	= 0x5,
++	BTC_RSN_5GCONSTART	= 0x6,
++	BTC_RSN_2GCONFINISH	= 0x7,
++	BTC_RSN_5GCONFINISH	= 0x8,
++	BTC_RSN_2GMEDIA		= 0x9,
++	BTC_RSN_5GMEDIA		= 0xa,
++	BTC_RSN_MEDIADISCON	= 0xb,
++	BTC_RSN_2GSPECIALPKT	= 0xc,
++	BTC_RSN_5GSPECIALPKT	= 0xd,
++	BTC_RSN_BTINFO		= 0xe,
++	BTC_RSN_PERIODICAL	= 0xf,
++	BTC_RSN_PNP		= 0x10,
++	BTC_RSN_LPS		= 0x11,
++	BTC_RSN_TIMERUP		= 0x12,
++	BTC_RSN_WLSTATUS	= 0x13,
++	BTC_RSN_MAX
++};
++
++static const char *const run_reason_string[] = {
++	"2G_SCAN_START",
++	"5G_SCAN_START",
++	"SCAN_FINISH",
++	"2G_SWITCH_BAND",
++	"5G_SWITCH_BAND",
++	"2G_CONNECT_START",
++	"5G_CONNECT_START",
++	"2G_CONNECT_FINISH",
++	"5G_CONNECT_FINISH",
++	"2G_MEDIA_STATUS",
++	"5G_MEDIA_STATUS",
++	"MEDIA_DISCONNECT",
++	"2G_SPECIALPKT",
++	"5G_SPECIALPKT",
++	"BTINFO",
++	"PERIODICAL",
++	"PNPNotify",
++	"LPSNotify",
++	"TimerUp",
++	"WL_STATUS_CHANGE",
++};
++
++enum btc_wl_link_mode {
++	BTC_WLINK_2G1PORT	= 0x0,
++	BTC_WLINK_2GMPORT	= 0x1,
++	BTC_WLINK_25GMPORT	= 0x2,
++	BTC_WLINK_5G		= 0x3,
++	BTC_WLINK_2GGO		= 0x4,
++	BTC_WLINK_2GGC		= 0x5,
++	BTC_WLINK_BTMR		= 0x6,
++	BTC_WLINK_MAX
++};
++
++static const char *const coex_mode_string[] = {
++	"2G-SP",
++	"2G-MP",
++	"25G-MP",
++	"5G",
++	"2G-P2P-GO",
++	"2G-P2P-GC",
++	"BT-MR"
++};
++
++enum btc_bt_state_cnt {
++	BTC_CNT_BT_RETRY	= 0x0,
++	BTC_CNT_BT_REINIT	= 0x1,
++	BTC_CNT_BT_POPEVENT	= 0x2,
++	BTC_CNT_BT_SETUPLINK	= 0x3,
++	BTC_CNT_BT_IGNWLANACT	= 0x4,
++	BTC_CNT_BT_INQ		= 0x5,
++	BTC_CNT_BT_PAGE		= 0x6,
++	BTC_CNT_BT_ROLESWITCH	= 0x7,
++	BTC_CNT_BT_AFHUPDATE	= 0x8,
++	BTC_CNT_BT_DISABLE	= 0x9,
++	BTC_CNT_BT_INFOUPDATE	= 0xa,
++	BTC_CNT_BT_IQK		= 0xb,
++	BTC_CNT_BT_IQKFAIL	= 0xc,
++	BTC_CNT_BT_MAX
++};
++
++enum btc_wl_state_cnt {
++	BTC_CNT_WL_SCANAP		= 0x0,
++	BTC_CNT_WL_ARP			= 0x1,
++	BTC_CNT_WL_GNTERR		= 0x2,
++	BTC_CNT_WL_PSFAIL		= 0x3,
++	BTC_CNT_WL_COEXRUN		= 0x4,
++	BTC_CNT_WL_COEXINFO1		= 0x5,
++	BTC_CNT_WL_COEXINFO2		= 0x6,
++	BTC_CNT_WL_AUTOSLOT_HANG	= 0x7,
++	BTC_CNT_WL_NOISY0		= 0x8,
++	BTC_CNT_WL_NOISY1		= 0x9,
++	BTC_CNT_WL_NOISY2		= 0xa,
++	BTC_CNT_WL_ACTIVEPORT		= 0xb,
++	BTC_CNT_WL_5MS_NOEXTEND		= 0xc,
++	BTC_CNT_WL_FW_NOTIFY		= 0xd,
++	BTC_CNT_WL_MAX
++};
++
++enum btc_wl_crc_cnt {
++	BTC_WLCRC_11BOK		= 0x0,
++	BTC_WLCRC_11GOK		= 0x1,
++	BTC_WLCRC_11NOK		= 0x2,
++	BTC_WLCRC_11VHTOK	= 0x3,
++	BTC_WLCRC_11BERR	= 0x4,
++	BTC_WLCRC_11GERR	= 0x5,
++	BTC_WLCRC_11NERR	= 0x6,
++	BTC_WLCRC_11VHTERR	= 0x7,
++	BTC_WLCRC_MAX
++};
++
++enum btc_timer_cnt {
++	BTC_TIMER_WL_STAYBUSY	= 0x0,
++	BTC_TIMER_WL_COEXFREEZE	= 0x1,
++	BTC_TIMER_WL_SPECPKT	= 0x2,
++	BTC_TIMER_WL_CONNPKT	= 0x3,
++	BTC_TIMER_WL_PNPWAKEUP	= 0x4,
++	BTC_TIMER_WL_CCKLOCK	= 0x5,
++	BTC_TIMER_WL_FWDBG	= 0x6,
++	BTC_TIMER_BT_RELINK	= 0x7,
++	BTC_TIMER_BT_REENABLE	= 0x8,
++	BTC_TIMER_BT_MULTILINK	= 0x9,
++	BTC_TIMER_MAX
++};
++
++enum btc_wl_status_change {
++	BTC_WLSTATUS_CHANGE_TOIDLE	= 0x0,
++	BTC_WLSTATUS_CHANGE_TOBUSY	= 0x1,
++	BTC_WLSTATUS_CHANGE_RSSI	= 0x2,
++	BTC_WLSTATUS_CHANGE_LINKINFO	= 0x3,
++	BTC_WLSTATUS_CHANGE_DIR	= 0x4,
++	BTC_WLSTATUS_CHANGE_NOISY	= 0x5,
++	BTC_WLSTATUS_CHANGE_MAX
++};
++
++enum btc_commom_chip_setup {
++	BTC_CSETUP_INIT_HW		= 0x0,
++	BTC_CSETUP_ANT_SWITCH	= 0x1,
++	BTC_CSETUP_GNT_FIX		= 0x2,
++	BTC_CSETUP_GNT_DEBUG	= 0x3,
++	BTC_CSETUP_RFE_TYPE		= 0x4,
++	BTC_CSETUP_COEXINFO_HW	= 0x5,
++	BTC_CSETUP_WL_TX_POWER	= 0x6,
++	BTC_CSETUP_WL_RX_GAIN	= 0x7,
++	BTC_CSETUP_WLAN_ACT_IPS = 0x8,
++	BTC_CSETUP_MAX
++};
++
++enum btc_indirect_reg_type {
++	BTC_INDIRECT_1700	= 0x0,
++	BTC_INDIRECT_7C0	= 0x1,
++	BTC_INDIRECT_MAX
++};
++
++enum btc_pstdma_type {
++	BTC_PSTDMA_FORCE_LPSOFF	= 0x0,
++	BTC_PSTDMA_FORCE_LPSON	= 0x1,
++	BTC_PSTDMA_MAX
++};
++
++enum btc_btrssi_type {
++	BTC_BTRSSI_RATIO	= 0x0,
++	BTC_BTRSSI_DBM		= 0x1,
++	BTC_BTRSSI_MAX
++};
++
++enum btc_wl_priority_mask {
++	BTC_WLPRI_RX_RSP	= 2,
++	BTC_WLPRI_TX_RSP	= 3,
++	BTC_WLPRI_TX_BEACON	= 4,
++	BTC_WLPRI_TX_OFDM	= 11,
++	BTC_WLPRI_TX_CCK	= 12,
++	BTC_WLPRI_TX_BEACONQ	= 27,
++	BTC_WLPRI_RX_CCK	= 28,
++	BTC_WLPRI_RX_OFDM	= 29,
++	BTC_WLPRI_MAX
++};
++
++struct btc_board_info {
++	/* The following is some board information */
++	u8				bt_chip_type;
++	u8				pg_ant_num;	/* pg ant number */
++	u8				btdm_ant_num;	/* ant number for btdm */
++	u8				btdm_ant_num_by_ant_det;	/* ant number for btdm after antenna detection */
++	u8				btdm_ant_pos;		/* Bryant Add to indicate Antenna Position for (pg_ant_num = 2) && (btdm_ant_num =1)  (DPDT+1Ant case) */
++	u8				single_ant_path;	/* current used for 8723b only, 1=>s0,  0=>s1 */
++	boolean			tfbga_package;    /* for Antenna detect threshold */
++	boolean			btdm_ant_det_finish;
++	boolean			btdm_ant_det_already_init_phydm;
++	u8				ant_type;
++	u8				rfe_type;
++	u8				ant_div_cfg;
++	boolean			btdm_ant_det_complete_fail;
++	u8				ant_det_result;
++	boolean			ant_det_result_five_complete;
++	u32				antdetval;
++	u8				customerID;
++	u8				customer_id;
++	u8				ant_distance;	/* WL-BT antenna space for non-shared antenna  */
++};
++
++struct btc_coex_dm {
++	boolean cur_ignore_wlan_act;
++	boolean cur_ps_tdma_on;
++	boolean cur_low_penalty_ra;
++	boolean cur_wl_rx_low_gain_en;
++
++	u8	bt_rssi_state[4];
++	u8	wl_rssi_state[4];
++	u8	cur_ps_tdma;
++	u8	ps_tdma_para[5];
++	u8	fw_tdma_para[5];
++	u8	cur_lps;
++	u8	cur_rpwm;
++	u8	cur_bt_pwr_lvl;
++	u8	cur_bt_lna_lvl;
++	u8	cur_wl_pwr_lvl;
++	u8	cur_algorithm;
++	u8	bt_status;
++	u8	wl_chnl_info[3];
++	u8	cur_toggle_para[6];
++	u32	cur_ant_pos_type;
++	u32	cur_switch_status;
++	u32	setting_tdma;
++};
++
++struct btc_coex_sta {
++	boolean coex_freeze;
++	boolean coex_freerun;
++	boolean rf4ce_en;
++	boolean is_no_wl_5ms_extend;
++
++	boolean bt_disabled;
++	boolean bt_disabled_pre;
++	boolean bt_link_exist;
++	boolean bt_whck_test;
++	boolean bt_inq_page;
++	boolean bt_inq;
++	boolean bt_page;
++	boolean bt_ble_voice;
++	boolean bt_ble_exist;
++	boolean bt_hfp_exist;
++	boolean bt_a2dp_exist;
++	boolean bt_hid_exist;
++	boolean bt_pan_exist; // PAN or OPP
++	boolean bt_opp_exist; //OPP only
++	boolean bt_msft_mr_exist;
++	boolean bt_acl_busy;
++	boolean bt_fix_2M;
++	boolean bt_setup_link;
++	boolean bt_multi_link;
++	boolean bt_multi_link_pre;
++	boolean bt_multi_link_remain;
++	boolean bt_a2dp_sink;
++	boolean bt_reenable;
++	boolean bt_ble_scan_en;
++	boolean bt_slave;
++	boolean bt_a2dp_active;
++	boolean bt_slave_latency;
++	boolean bt_init_scan;
++	boolean bt_418_hid_exist;
++	boolean bt_ble_hid_exist;
++	boolean bt_mesh;
++
++	boolean wl_under_lps;
++	boolean wl_under_ips;
++	boolean wl_under_4way;
++	boolean	wl_hi_pri_task1;
++	boolean	wl_hi_pri_task2;
++	boolean wl_cck_lock;
++	boolean wl_cck_lock_pre;
++	boolean wl_cck_lock_ever;
++	boolean wl_force_lps_ctrl;
++	boolean wl_busy_pre;
++	boolean wl_gl_busy;
++	boolean wl_gl_busy_pre;
++	boolean wl_linkscan_proc;
++	boolean wl_mimo_ps;
++	boolean wl_cck_dead_lock_ap;
++	boolean wl_tx_limit_en;
++	boolean wl_ampdu_limit_en;
++	boolean wl_rxagg_limit_en;
++	boolean wl_connecting;
++	boolean wl_pnp_wakeup;
++	boolean wl_slot_toggle;
++	boolean wl_slot_toggle_change; /* if toggle to no-toggle */
++
++	u8	coex_table_type;
++	u8 	coex_run_reason;
++	u8	tdma_byte4_modify_pre;
++	u8	kt_ver;
++	u8	gnt_workaround_state;
++	u8	tdma_timer_base;
++	u8	bt_rssi;
++	u8	bt_profile_num;
++	u8	bt_profile_num_pre;
++	u8	bt_info_c2h[BTC_BTINFO_SRC_MAX][BTC_BTINFO_LENGTH_MAX];
++	u8	bt_info_lb2;
++	u8	bt_info_lb3;
++	u8	bt_info_hb0;
++	u8	bt_info_hb1;
++	u8	bt_info_hb2;
++	u8	bt_info_hb3;
++	u8	bt_ble_scan_type;
++	u8	bt_afh_map[10];
++	u8	bt_a2dp_vendor_id;
++	u8	bt_hid_pair_num;
++	u8	bt_hid_slot;
++	u8	bt_a2dp_bitpool;
++	u8	bt_iqk_state;
++	u8	bt_sut_pwr_lvl[4];
++	u8	bt_golden_rx_shift[4];
++	u8	bt_ext_autoslot_thres;
++
++	u8	wl_pnp_state_pre;
++	u8	wl_noisy_level;
++	u8	wl_fw_dbg_info[10];
++	u8	wl_fw_dbg_info_pre[10];
++	u8	wl_rx_rate;
++	u8	wl_tx_rate;
++	u8	wl_rts_rx_rate;
++	u8	wl_center_ch;
++	u8	wl_tx_macid;
++	u8	wl_tx_retry_ratio;
++	u8	wl_coex_mode;
++	u8	wl_iot_peer;
++	u8	wl_ra_thres;
++	u8	wl_ampdulen;
++	u8	wl_rxagg_size;
++	u8	wl_toggle_para[6];
++	u8	wl_toggle_interval;
++
++	u16	score_board_BW;
++	u16	score_board_WB;
++	u16	bt_reg_vendor_ac;
++	u16	bt_reg_vendor_ae;
++	u16	bt_reg_modem_a;
++	u16	bt_reg_rf_2;
++	u16	wl_txlimit;
++
++	u32	hi_pri_tx;
++	u32	hi_pri_rx;
++	u32	lo_pri_tx;
++	u32	lo_pri_rx;
++	u32	bt_supported_feature;
++	u32	bt_supported_version;
++	u32	bt_ble_scan_para[3];
++	u32	bt_a2dp_device_name;
++	u32	bt_a2dp_flush_time;
++	u32	wl_arfb1;
++	u32	wl_arfb2;
++	u32	wl_traffic_dir;
++	u32	wl_bw;
++	u32	cnt_bt_info_c2h[BTC_BTINFO_SRC_MAX];
++	u32	cnt_bt[BTC_CNT_BT_MAX];
++	u32	cnt_wl[BTC_CNT_WL_MAX];
++	u32	cnt_timer[BTC_TIMER_MAX];
++};
++
++struct btc_rfe_type {
++	boolean ant_switch_exist;
++	boolean ant_switch_diversity; /* If diversity on */
++	boolean ant_switch_with_bt; /* If WL_2G/BT use ext-switch at shared-ant */
++	u8	rfe_module_type;
++	u8	ant_switch_type;
++	u8	ant_switch_polarity;
++	
++	boolean band_switch_exist;
++	u8	band_switch_type; /* 0:DPDT, 1:SPDT */
++	u8	band_switch_polarity;
++
++	/*  If TRUE:  WLG at BTG, If FALSE: WLG at WLAG */
++	boolean wlg_at_btg;
++};
++
++
++struct btc_wifi_link_info_ext {
++	boolean is_all_under_5g;
++	boolean is_mcc_25g;
++	boolean is_p2p_connected;
++	boolean is_ap_mode;
++	boolean is_scan;
++	boolean is_link;
++	boolean is_roam;
++	boolean is_4way;
++	boolean is_32k;
++	boolean is_connected;
++	u8	num_of_active_port;
++	u32	port_connect_status;
++	u32	traffic_dir;
++	u32	wifi_bw;
++};
++
++struct btc_coex_table_para {
++	u32 bt;	//0x6c0
++	u32 wl;	//0x6c4
++};
++
++struct btc_tdma_para {
++	u8 para[5];
++};
++
++struct btc_reg_byte_modify {
++	u32 addr;
++	u8 bitmask;
++	u8 val;
++};
++
++struct btc_5g_afh_map {
++	u32 wl_5g_ch;
++	u8 bt_skip_ch;
++	u8 bt_skip_span;
++};
++
++struct btc_rf_para {
++	u8 wl_pwr_dec_lvl;
++	u8 bt_pwr_dec_lvl;
++	boolean wl_low_gain_en;
++	u8 bt_lna_lvl;
++};
++
++typedef enum _BTC_DBG_OPCODE {
++	BTC_DBG_SET_COEX_NORMAL				= 0x0,
++	BTC_DBG_SET_COEX_WIFI_ONLY				= 0x1,
++	BTC_DBG_SET_COEX_BT_ONLY				= 0x2,
++	BTC_DBG_SET_COEX_DEC_BT_PWR				= 0x3,
++	BTC_DBG_SET_COEX_BT_AFH_MAP				= 0x4,
++	BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT		= 0x5,
++	BTC_DBG_SET_COEX_MANUAL_CTRL				= 0x6,
++	BTC_DBG_MAX
++} BTC_DBG_OPCODE, *PBTC_DBG_OPCODE;
++
++typedef enum _BTC_RSSI_STATE {
++	BTC_RSSI_STATE_HIGH						= 0x0,
++	BTC_RSSI_STATE_MEDIUM					= 0x1,
++	BTC_RSSI_STATE_LOW						= 0x2,
++	BTC_RSSI_STATE_STAY_HIGH					= 0x3,
++	BTC_RSSI_STATE_STAY_MEDIUM				= 0x4,
++	BTC_RSSI_STATE_STAY_LOW					= 0x5,
++	BTC_RSSI_MAX
++} BTC_RSSI_STATE, *PBTC_RSSI_STATE;
++#define	BTC_RSSI_HIGH(_rssi_)	((_rssi_ == BTC_RSSI_STATE_HIGH || _rssi_ == BTC_RSSI_STATE_STAY_HIGH) ? TRUE:FALSE)
++#define	BTC_RSSI_MEDIUM(_rssi_)	((_rssi_ == BTC_RSSI_STATE_MEDIUM || _rssi_ == BTC_RSSI_STATE_STAY_MEDIUM) ? TRUE:FALSE)
++#define	BTC_RSSI_LOW(_rssi_)	((_rssi_ == BTC_RSSI_STATE_LOW || _rssi_ == BTC_RSSI_STATE_STAY_LOW) ? TRUE:FALSE)
++
++typedef enum _BTC_WIFI_ROLE {
++	BTC_ROLE_STATION						= 0x0,
++	BTC_ROLE_AP								= 0x1,
++	BTC_ROLE_IBSS							= 0x2,
++	BTC_ROLE_HS_MODE						= 0x3,
++	BTC_ROLE_MAX
++} BTC_WIFI_ROLE, *PBTC_WIFI_ROLE;
++
++typedef enum _BTC_WIRELESS_FREQ {
++	BTC_FREQ_2_4G					= 0x0,
++	BTC_FREQ_5G						= 0x1,
++	BTC_FREQ_25G					= 0x2,
++	BTC_FREQ_MAX
++} BTC_WIRELESS_FREQ, *PBTC_WIRELESS_FREQ;
++
++typedef enum _BTC_WIFI_BW_MODE {
++	BTC_WIFI_BW_LEGACY					= 0x0,
++	BTC_WIFI_BW_HT20					= 0x1,
++	BTC_WIFI_BW_HT40					= 0x2,
++	BTC_WIFI_BW_HT80					= 0x3,
++	BTC_WIFI_BW_HT160					= 0x4,
++	BTC_WIFI_BW_MAX
++} BTC_WIFI_BW_MODE, *PBTC_WIFI_BW_MODE;
++
++typedef enum _BTC_WIFI_TRAFFIC_DIR {
++	BTC_WIFI_TRAFFIC_TX					= 0x0,
++	BTC_WIFI_TRAFFIC_RX					= 0x1,
++	BTC_WIFI_TRAFFIC_MAX
++} BTC_WIFI_TRAFFIC_DIR, *PBTC_WIFI_TRAFFIC_DIR;
++
++typedef enum _BTC_WIFI_PNP {
++	BTC_WIFI_PNP_WAKE_UP					= 0x0,
++	BTC_WIFI_PNP_SLEEP						= 0x1,
++	BTC_WIFI_PNP_SLEEP_KEEP_ANT				= 0x2,
++	BTC_WIFI_PNP_WOWLAN					= 0x3,
++	BTC_WIFI_PNP_MAX
++} BTC_WIFI_PNP, *PBTC_WIFI_PNP;
++
++typedef enum _BTC_IOT_PEER {
++	BTC_IOT_PEER_UNKNOWN = 0,
++	BTC_IOT_PEER_REALTEK = 1,
++	BTC_IOT_PEER_REALTEK_92SE = 2,
++	BTC_IOT_PEER_BROADCOM = 3,
++	BTC_IOT_PEER_RALINK = 4,
++	BTC_IOT_PEER_ATHEROS = 5,
++	BTC_IOT_PEER_CISCO = 6,
++	BTC_IOT_PEER_MERU = 7,
++	BTC_IOT_PEER_MARVELL = 8,
++	BTC_IOT_PEER_REALTEK_SOFTAP = 9, /* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */
++	BTC_IOT_PEER_SELF_SOFTAP = 10, /* Self is SoftAP */
++	BTC_IOT_PEER_AIRGO = 11,
++	BTC_IOT_PEER_INTEL				= 12,
++	BTC_IOT_PEER_RTK_APCLIENT		= 13,
++	BTC_IOT_PEER_REALTEK_81XX		= 14,
++	BTC_IOT_PEER_REALTEK_WOW		= 15,
++	BTC_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 16,
++	BTC_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 17,
++	BTC_IOT_PEER_MAX,
++} BTC_IOT_PEER, *PBTC_IOT_PEER;
++
++/* for 8723b-d cut large current issue */
++typedef enum _BTC_WIFI_COEX_STATE {
++	BTC_WIFI_STAT_INIT,
++	BTC_WIFI_STAT_IQK,
++	BTC_WIFI_STAT_NORMAL_OFF,
++	BTC_WIFI_STAT_MP_OFF,
++	BTC_WIFI_STAT_NORMAL,
++	BTC_WIFI_STAT_ANT_DIV,
++	BTC_WIFI_STAT_MAX
++} BTC_WIFI_COEX_STATE, *PBTC_WIFI_COEX_STATE;
++
++typedef enum _BTC_ANT_TYPE {
++	BTC_ANT_TYPE_0,
++	BTC_ANT_TYPE_1,
++	BTC_ANT_TYPE_2,
++	BTC_ANT_TYPE_3,
++	BTC_ANT_TYPE_4,
++	BTC_ANT_TYPE_MAX
++} BTC_ANT_TYPE, *PBTC_ANT_TYPE;
++
++typedef enum _BTC_VENDOR {
++	BTC_VENDOR_LENOVO,
++	BTC_VENDOR_ASUS,
++	BTC_VENDOR_OTHER
++} BTC_VENDOR, *PBTC_VENDOR;
++
++
++/* defined for BFP_BTC_GET */
++typedef enum _BTC_GET_TYPE {
++	/* type BOOLEAN */
++	BTC_GET_BL_HS_OPERATION,
++	BTC_GET_BL_HS_CONNECTING,
++	BTC_GET_BL_WIFI_FW_READY,
++	BTC_GET_BL_WIFI_CONNECTED,
++	BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED,
++	BTC_GET_BL_WIFI_LINK_INFO,
++	BTC_GET_BL_WIFI_BUSY,
++	BTC_GET_BL_WIFI_SCAN,
++	BTC_GET_BL_WIFI_LINK,
++	BTC_GET_BL_WIFI_ROAM,
++	BTC_GET_BL_WIFI_4_WAY_PROGRESS,
++	BTC_GET_BL_WIFI_UNDER_5G,
++	BTC_GET_BL_WIFI_AP_MODE_ENABLE,
++	BTC_GET_BL_WIFI_ENABLE_ENCRYPTION,
++	BTC_GET_BL_WIFI_UNDER_B_MODE,
++	BTC_GET_BL_EXT_SWITCH,
++	BTC_GET_BL_WIFI_IS_IN_MP_MODE,
++	BTC_GET_BL_IS_ASUS_8723B,
++	BTC_GET_BL_RF4CE_CONNECTED,
++	BTC_GET_BL_WIFI_LW_PWR_STATE,
++
++	/* type s4Byte */
++	BTC_GET_S4_WIFI_RSSI,
++	BTC_GET_S4_HS_RSSI,
++
++	/* type u4Byte */
++	BTC_GET_U4_WIFI_BW,
++	BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
++	BTC_GET_U4_WIFI_TRAFFIC_DIR,
++	BTC_GET_U4_WIFI_FW_VER,
++	BTC_GET_U4_WIFI_PHY_VER,
++	BTC_GET_U4_WIFI_LINK_STATUS,
++	BTC_GET_U4_BT_PATCH_VER,
++	BTC_GET_U4_VENDOR,
++	BTC_GET_U4_SUPPORTED_VERSION,
++	BTC_GET_U4_SUPPORTED_FEATURE,
++	BTC_GET_U4_BT_DEVICE_INFO,
++	BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL,
++	BTC_GET_U4_BT_A2DP_FLUSH_VAL,
++	BTC_GET_U4_WIFI_IQK_TOTAL,
++	BTC_GET_U4_WIFI_IQK_OK,
++	BTC_GET_U4_WIFI_IQK_FAIL,
++
++	/* type u1Byte */
++	BTC_GET_U1_WIFI_DOT11_CHNL,
++	BTC_GET_U1_WIFI_CENTRAL_CHNL,
++	BTC_GET_U1_WIFI_HS_CHNL,
++	BTC_GET_U1_WIFI_P2P_CHNL,
++	BTC_GET_U1_MAC_PHY_MODE,
++	BTC_GET_U1_AP_NUM,
++	BTC_GET_U1_ANT_TYPE,
++	BTC_GET_U1_IOT_PEER,
++
++	/* type u2Byte */
++	BTC_GET_U2_BEACON_PERIOD,
++
++	/*===== for 1Ant ======*/
++	BTC_GET_U1_LPS_MODE,
++
++	BTC_GET_MAX
++} BTC_GET_TYPE, *PBTC_GET_TYPE;
++
++/* defined for BFP_BTC_SET */
++typedef enum _BTC_SET_TYPE {
++	/* type BOOLEAN */
++	BTC_SET_BL_BT_DISABLE,
++	BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE,
++	BTC_SET_BL_BT_TRAFFIC_BUSY,
++	BTC_SET_BL_BT_LIMITED_DIG,
++	BTC_SET_BL_FORCE_TO_ROAM,
++	BTC_SET_BL_TO_REJ_AP_AGG_PKT,
++	BTC_SET_BL_BT_CTRL_AGG_SIZE,
++	BTC_SET_BL_INC_SCAN_DEV_NUM,
++	BTC_SET_BL_BT_TX_RX_MASK,
++	BTC_SET_BL_MIRACAST_PLUS_BT,
++	BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL,
++	BTC_SET_BL_BT_GOLDEN_RX_RANGE,
++
++	/* type u1Byte */
++	BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
++	BTC_SET_U1_AGG_BUF_SIZE,
++
++	/* type trigger some action */
++	BTC_SET_ACT_GET_BT_RSSI,
++	BTC_SET_ACT_AGGREGATE_CTRL,
++	BTC_SET_ACT_ANTPOSREGRISTRY_CTRL,
++
++	// for mimo ps mode setting
++	BTC_SET_MIMO_PS_MODE,
++	/*===== for 1Ant ======*/
++	/* type BOOLEAN */
++
++	/* type u1Byte */
++	BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE,
++	BTC_SET_U1_LPS_VAL,
++	BTC_SET_U1_RPWM_VAL,
++	/* type trigger some action */
++	BTC_SET_ACT_LEAVE_LPS,
++	BTC_SET_ACT_ENTER_LPS,
++	BTC_SET_ACT_NORMAL_LPS,
++	BTC_SET_ACT_PRE_NORMAL_LPS,
++	BTC_SET_ACT_POST_NORMAL_LPS,
++	BTC_SET_ACT_DISABLE_LOW_POWER,
++	BTC_SET_ACT_UPDATE_RAMASK,
++	BTC_SET_ACT_SEND_MIMO_PS,
++	/* BT Coex related */
++	BTC_SET_ACT_CTRL_BT_INFO,
++	BTC_SET_ACT_CTRL_BT_COEX,
++	BTC_SET_ACT_CTRL_8723B_ANT,
++	BTC_SET_RESET_COEX_VAR,
++	/*=================*/
++	BTC_SET_MAX
++} BTC_SET_TYPE, *PBTC_SET_TYPE;
++
++typedef enum _BTC_DBG_DISP_TYPE {
++	BTC_DBG_DISP_COEX_STATISTICS				= 0x0,
++	BTC_DBG_DISP_BT_LINK_INFO				= 0x1,
++	BTC_DBG_DISP_WIFI_STATUS				= 0x2,
++	BTC_DBG_DISP_MAX
++} BTC_DBG_DISP_TYPE, *PBTC_DBG_DISP_TYPE;
++
++typedef enum _BTC_NOTIFY_TYPE_IPS {
++	BTC_IPS_LEAVE							= 0x0,
++	BTC_IPS_ENTER							= 0x1,
++	BTC_IPS_MAX
++} BTC_NOTIFY_TYPE_IPS, *PBTC_NOTIFY_TYPE_IPS;
++typedef enum _BTC_NOTIFY_TYPE_LPS {
++	BTC_LPS_DISABLE							= 0x0,
++	BTC_LPS_ENABLE							= 0x1,
++	BTC_LPS_MAX
++} BTC_NOTIFY_TYPE_LPS, *PBTC_NOTIFY_TYPE_LPS;
++typedef enum _BTC_NOTIFY_TYPE_SCAN {
++	BTC_SCAN_FINISH							= 0x0,
++	BTC_SCAN_START							= 0x1,
++	BTC_SCAN_START_2G						= 0x2,
++	BTC_SCAN_START_5G						= 0x3,
++	BTC_SCAN_MAX
++} BTC_NOTIFY_TYPE_SCAN, *PBTC_NOTIFY_TYPE_SCAN;
++typedef enum _BTC_NOTIFY_TYPE_SWITCHBAND {
++	BTC_NOT_SWITCH							= 0x0,
++	BTC_SWITCH_TO_24G						= 0x1,
++	BTC_SWITCH_TO_5G						= 0x2,
++	BTC_SWITCH_TO_24G_NOFORSCAN				= 0x3,
++	BTC_SWITCH_MAX
++} BTC_NOTIFY_TYPE_SWITCHBAND, *PBTC_NOTIFY_TYPE_SWITCHBAND;
++typedef enum _BTC_NOTIFY_TYPE_ASSOCIATE {
++	BTC_ASSOCIATE_FINISH						= 0x0,
++	BTC_ASSOCIATE_START						= 0x1,
++	BTC_ASSOCIATE_5G_FINISH						= 0x2,
++	BTC_ASSOCIATE_5G_START						= 0x3,
++	BTC_ASSOCIATE_MAX
++} BTC_NOTIFY_TYPE_ASSOCIATE, *PBTC_NOTIFY_TYPE_ASSOCIATE;
++typedef enum _BTC_NOTIFY_TYPE_MEDIA_STATUS {
++	BTC_MEDIA_DISCONNECT					= 0x0,
++	BTC_MEDIA_CONNECT						= 0x1,
++	BTC_MEDIA_CONNECT_5G					= 0x02,
++	BTC_MEDIA_MAX
++} BTC_NOTIFY_TYPE_MEDIA_STATUS, *PBTC_NOTIFY_TYPE_MEDIA_STATUS;
++typedef enum _BTC_NOTIFY_TYPE_SPECIFIC_PACKET {
++	BTC_PACKET_UNKNOWN					= 0x0,
++	BTC_PACKET_DHCP							= 0x1,
++	BTC_PACKET_ARP							= 0x2,
++	BTC_PACKET_EAPOL						= 0x3,
++	BTC_PACKET_MAX
++} BTC_NOTIFY_TYPE_SPECIFIC_PACKET, *PBTC_NOTIFY_TYPE_SPECIFIC_PACKET;
++typedef enum _BTC_NOTIFY_TYPE_STACK_OPERATION {
++	BTC_STACK_OP_NONE					= 0x0,
++	BTC_STACK_OP_INQ_PAGE_PAIR_START		= 0x1,
++	BTC_STACK_OP_INQ_PAGE_PAIR_FINISH	= 0x2,
++	BTC_STACK_OP_MAX
++} BTC_NOTIFY_TYPE_STACK_OPERATION, *PBTC_NOTIFY_TYPE_STACK_OPERATION;
++
++/* Bryant Add */
++typedef enum _BTC_ANTENNA_POS {
++	BTC_ANTENNA_AT_MAIN_PORT				= 0x1,
++	BTC_ANTENNA_AT_AUX_PORT				= 0x2,
++} BTC_ANTENNA_POS, *PBTC_ANTENNA_POS;
++
++/* Bryant Add */
++typedef enum _BTC_BT_OFFON {
++	BTC_BT_OFF				= 0x0,
++	BTC_BT_ON				= 0x1,
++} BTC_BTOFFON, *PBTC_BT_OFFON;
++
++#define BTC_5G_BAND 0x80
++
++/*==================================================
++For following block is for coex offload
++==================================================*/
++typedef struct _COL_H2C {
++	u1Byte	opcode;
++	u1Byte	opcode_ver:4;
++	u1Byte	req_num:4;
++	u1Byte	buf[1];
++} COL_H2C, *PCOL_H2C;
++
++#define	COL_C2H_ACK_HDR_LEN	3
++typedef struct _COL_C2H_ACK {
++	u1Byte	status;
++	u1Byte	opcode_ver:4;
++	u1Byte	req_num:4;
++	u1Byte	ret_len;
++	u1Byte	buf[1];
++} COL_C2H_ACK, *PCOL_C2H_ACK;
++
++#define	COL_C2H_IND_HDR_LEN	3
++typedef struct _COL_C2H_IND {
++	u1Byte	type;
++	u1Byte	version;
++	u1Byte	length;
++	u1Byte	data[1];
++} COL_C2H_IND, *PCOL_C2H_IND;
++
++/*============================================
++NOTE: for debug message, the following define should match
++the strings in coexH2cResultString.
++============================================*/
++typedef enum _COL_H2C_STATUS {
++	/* c2h status */
++	COL_STATUS_C2H_OK								= 0x00, /* Wifi received H2C request and check content ok. */
++	COL_STATUS_C2H_UNKNOWN							= 0x01,	/* Not handled routine */
++	COL_STATUS_C2H_UNKNOWN_OPCODE					= 0x02,	/* Invalid OP code, It means that wifi firmware received an undefiend OP code. */
++	COL_STATUS_C2H_OPCODE_VER_MISMATCH			= 0x03, /* Wifi firmware and wifi driver mismatch, need to update wifi driver or wifi or. */
++	COL_STATUS_C2H_PARAMETER_ERROR				= 0x04, /* Error paraneter.(ex: parameters = NULL but it should have values) */
++	COL_STATUS_C2H_PARAMETER_OUT_OF_RANGE		= 0x05, /* Wifi firmware needs to check the parameters from H2C request and return the status.(ex: ch = 500, it's wrong) */
++	/* other COL status start from here */
++	COL_STATUS_C2H_REQ_NUM_MISMATCH			, /* c2h req_num mismatch, means this c2h is not we expected. */
++	COL_STATUS_H2C_HALMAC_FAIL					, /* HALMAC return fail. */
++	COL_STATUS_H2C_TIMTOUT						, /* not received the c2h response from fw */
++	COL_STATUS_INVALID_C2H_LEN					, /* invalid coex offload c2h ack length, must >= 3 */
++	COL_STATUS_COEX_DATA_OVERFLOW				, /* coex returned length over the c2h ack length. */
++	COL_STATUS_MAX
++} COL_H2C_STATUS, *PCOL_H2C_STATUS;
++
++#define	COL_MAX_H2C_REQ_NUM		16
++
++#define	COL_H2C_BUF_LEN			20
++typedef enum _COL_OPCODE {
++	COL_OP_WIFI_STATUS_NOTIFY					= 0x0,
++	COL_OP_WIFI_PROGRESS_NOTIFY					= 0x1,
++	COL_OP_WIFI_INFO_NOTIFY						= 0x2,
++	COL_OP_WIFI_POWER_STATE_NOTIFY				= 0x3,
++	COL_OP_SET_CONTROL							= 0x4,
++	COL_OP_GET_CONTROL							= 0x5,
++	COL_OP_WIFI_OPCODE_MAX
++} COL_OPCODE, *PCOL_OPCODE;
++
++typedef enum _COL_IND_TYPE {
++	COL_IND_BT_INFO								= 0x0,
++	COL_IND_PSTDMA								= 0x1,
++	COL_IND_LIMITED_TX_RX						= 0x2,
++	COL_IND_COEX_TABLE							= 0x3,
++	COL_IND_REQ									= 0x4,
++	COL_IND_MAX
++} COL_IND_TYPE, *PCOL_IND_TYPE;
++
++typedef struct _COL_SINGLE_H2C_RECORD {
++	u1Byte					h2c_buf[COL_H2C_BUF_LEN];	/* the latest sent h2c buffer */
++	u4Byte					h2c_len;
++	u1Byte					c2h_ack_buf[COL_H2C_BUF_LEN];	/* the latest received c2h buffer */
++	u4Byte					c2h_ack_len;
++	u4Byte					count;									/* the total number of the sent h2c command */
++	u4Byte					status[COL_STATUS_MAX];					/* the c2h status for the sent h2c command */
++} COL_SINGLE_H2C_RECORD, *PCOL_SINGLE_H2C_RECORD;
++
++typedef struct _COL_SINGLE_C2H_IND_RECORD {
++	u1Byte					ind_buf[COL_H2C_BUF_LEN];	/* the latest received c2h indication buffer */
++	u4Byte					ind_len;
++	u4Byte					count;									/* the total number of the rcvd c2h indication */
++	u4Byte					status[COL_STATUS_MAX];					/* the c2h indication verified status */
++} COL_SINGLE_C2H_IND_RECORD, *PCOL_SINGLE_C2H_IND_RECORD;
++
++typedef struct _BTC_OFFLOAD {
++	/* H2C command related */
++	u1Byte					h2c_req_num;
++	u4Byte					cnt_h2c_sent;
++	COL_SINGLE_H2C_RECORD	h2c_record[COL_OP_WIFI_OPCODE_MAX];
++
++	/* C2H Ack related */
++	u4Byte					cnt_c2h_ack;
++	u4Byte					status[COL_STATUS_MAX];
++	struct completion		c2h_event[COL_MAX_H2C_REQ_NUM];	/* for req_num = 1~COL_MAX_H2C_REQ_NUM */
++	u1Byte					c2h_ack_buf[COL_MAX_H2C_REQ_NUM][COL_H2C_BUF_LEN];
++	u1Byte					c2h_ack_len[COL_MAX_H2C_REQ_NUM];
++
++	/* C2H Indication related */
++	u4Byte						cnt_c2h_ind;
++	COL_SINGLE_C2H_IND_RECORD	c2h_ind_record[COL_IND_MAX];
++	u4Byte						c2h_ind_status[COL_STATUS_MAX];
++	u1Byte						c2h_ind_buf[COL_H2C_BUF_LEN];
++	u1Byte						c2h_ind_len;
++} BTC_OFFLOAD, *PBTC_OFFLOAD;
++extern BTC_OFFLOAD				gl_coex_offload;
++/*==================================================*/
++
++/* BTC_LINK_MODE same as WIFI_LINK_MODE */
++typedef enum _BTC_LINK_MODE{
++	BTC_LINK_NONE=0,
++	BTC_LINK_ONLY_GO,
++	BTC_LINK_ONLY_GC,
++	BTC_LINK_ONLY_STA,
++	BTC_LINK_ONLY_AP,
++	BTC_LINK_2G_MCC_GO_STA,
++	BTC_LINK_5G_MCC_GO_STA,
++	BTC_LINK_25G_MCC_GO_STA,
++	BTC_LINK_2G_MCC_GC_STA,
++	BTC_LINK_5G_MCC_GC_STA,
++	BTC_LINK_25G_MCC_GC_STA,
++	BTC_LINK_2G_SCC_GO_STA,
++	BTC_LINK_5G_SCC_GO_STA,
++	BTC_LINK_2G_SCC_GC_STA,
++	BTC_LINK_5G_SCC_GC_STA,
++	BTC_LINK_MAX=30
++}BTC_LINK_MODE, *PBTC_LINK_MODE;
++
++
++struct btc_wifi_link_info {
++	BTC_LINK_MODE link_mode; /* LinkMode */
++	u1Byte sta_center_channel; /* StaCenterChannel */
++	u1Byte p2p_center_channel; /* P2PCenterChannel	*/
++	BOOLEAN bany_client_join_go;
++	BOOLEAN benable_noa;
++	BOOLEAN bhotspot;
++};
++
++#if 0
++typedef enum _BTC_MULTI_PORT_TDMA_MODE {
++	BTC_MULTI_PORT_TDMA_MODE_NONE=0,
++	BTC_MULTI_PORT_TDMA_MODE_2G_SCC_GO,
++	BTC_MULTI_PORT_TDMA_MODE_2G_P2P_GO,
++	BTC_MULTI_PORT_TDMA_MODE_2G_HOTSPOT_GO
++} BTC_MULTI_PORT_TDMA_MODE, *PBTC_MULTI_PORT_TDMA_MODE;
++
++typedef struct btc_multi_port_tdma_info {
++	BTC_MULTI_PORT_TDMA_MODE btc_multi_port_tdma_mode;
++	u1Byte start_time_from_bcn;
++	u1Byte bt_time;
++} BTC_MULTI_PORT_TDMA_INFO, *PBTC_MULTI_PORT_TDMA_INFO;
++#endif
++
++typedef enum _btc_concurrent_mode {
++	btc_concurrent_mode_none = 0,
++	btc_concurrent_mode_2g_go_miracast,
++	btc_concurrent_mode_2g_go_hotspot,
++	btc_concurrent_mode_2g_scc_go_miracast_sta,
++	btc_concurrent_mode_2g_scc_go_hotspot_sta,
++	btc_concurrent_mode_2g_gc,
++} btc_concurrent_mode, *pbtc_concurrent_mode;
++
++struct btc_concurrent_setting {
++	btc_concurrent_mode btc_concurrent_mode;
++	u1Byte start_time_from_bcn;
++	u1Byte bt_time;
++};
++
++typedef u1Byte
++(*BFP_BTC_R1)(
++	IN	PVOID			pBtcContext,
++	IN	u4Byte			RegAddr
++	);
++typedef u2Byte
++(*BFP_BTC_R2)(
++	IN	PVOID			pBtcContext,
++	IN	u4Byte			RegAddr
++	);
++typedef u4Byte
++(*BFP_BTC_R4)(
++	IN	PVOID			pBtcContext,
++	IN	u4Byte			RegAddr
++	);
++typedef VOID
++(*BFP_BTC_W1)(
++	IN	PVOID			pBtcContext,
++	IN	u4Byte			RegAddr,
++	IN	u1Byte			Data
++	);
++typedef VOID
++(*BFP_BTC_W1_BIT_MASK)(
++	IN	PVOID			pBtcContext,
++	IN	u4Byte			regAddr,
++	IN	u1Byte			bitMask,
++	IN	u1Byte			data1b
++	);
++typedef VOID
++(*BFP_BTC_W2)(
++	IN	PVOID			pBtcContext,
++	IN	u4Byte			RegAddr,
++	IN	u2Byte			Data
++	);
++typedef VOID
++(*BFP_BTC_W4)(
++	IN	PVOID			pBtcContext,
++	IN	u4Byte			RegAddr,
++	IN	u4Byte			Data
++	);
++typedef VOID
++(*BFP_BTC_LOCAL_REG_W1)(
++	IN	PVOID			pBtcContext,
++	IN	u4Byte			RegAddr,
++	IN	u1Byte			Data
++	);
++typedef u4Byte
++(*BFP_BTC_R_LINDIRECT)(
++	IN 	PVOID			pBtcContext,
++	IN	u2Byte			reg_addr
++	);
++typedef u2Byte
++(*BFP_BTC_R_SCBD)(
++	IN 	PVOID			pBtcContext,
++	IN	pu2Byte			score_board_val
++	);
++typedef VOID
++(*BFP_BTC_W_SCBD)(
++	IN 	PVOID			pBtcContext,
++	IN	u2Byte			bitpos,
++	IN	BOOLEAN			state
++	);
++typedef VOID
++(*BFP_BTC_W_LINDIRECT)(
++	IN 	PVOID			pBtcContext,
++	IN	u2Byte			reg_addr,
++	IN	u4Byte			bit_mask,
++	IN	u4Byte 			reg_value
++	);
++typedef VOID
++(*BFP_BTC_SET_BB_REG)(
++	IN	PVOID			pBtcContext,
++	IN	u4Byte			RegAddr,
++	IN	u4Byte			BitMask,
++	IN	u4Byte			Data
++	);
++typedef u4Byte
++(*BFP_BTC_GET_BB_REG)(
++	IN	PVOID			pBtcContext,
++	IN	u4Byte			RegAddr,
++	IN	u4Byte			BitMask
++	);
++typedef VOID
++(*BFP_BTC_SET_RF_REG)(
++	IN	PVOID			pBtcContext,
++	IN	enum rf_path		eRFPath,
++	IN	u4Byte			RegAddr,
++	IN	u4Byte			BitMask,
++	IN	u4Byte			Data
++	);
++typedef u4Byte
++(*BFP_BTC_GET_RF_REG)(
++	IN	PVOID			pBtcContext,
++	IN	enum rf_path		eRFPath,
++	IN	u4Byte			RegAddr,
++	IN	u4Byte			BitMask
++	);
++typedef VOID
++(*BFP_BTC_FILL_H2C)(
++	IN	PVOID			pBtcContext,
++	IN	u1Byte			elementId,
++	IN	u4Byte			cmdLen,
++	IN	pu1Byte			pCmdBuffer
++	);
++
++typedef	BOOLEAN
++(*BFP_BTC_GET)(
++	IN	PVOID			pBtCoexist,
++	IN	u1Byte			getType,
++	OUT	PVOID			pOutBuf
++	);
++
++typedef	BOOLEAN
++(*BFP_BTC_SET)(
++	IN	PVOID			pBtCoexist,
++	IN	u1Byte			setType,
++	OUT	PVOID			pInBuf
++	);
++typedef u2Byte
++(*BFP_BTC_SET_BT_REG)(
++	IN	PVOID			pBtcContext,
++	IN	u1Byte			regType,
++	IN	u4Byte			offset,
++	IN	u4Byte			value
++	);
++typedef BOOLEAN
++(*BFP_BTC_SET_BT_ANT_DETECTION)(
++	IN	PVOID			pBtcContext,
++	IN	u1Byte			txTime,
++	IN	u1Byte			btChnl
++	);
++
++typedef BOOLEAN
++(*BFP_BTC_SET_BT_TRX_MASK)(
++	IN	PVOID			pBtcContext,
++	IN	u1Byte			bt_trx_mask
++	);
++
++typedef u4Byte
++(*BFP_BTC_GET_BT_REG)(
++	IN	PVOID			pBtcContext,
++	IN	u1Byte			regType,
++	IN	u4Byte			offset
++	);
++typedef VOID
++(*BFP_BTC_DISP_DBG_MSG)(
++	IN	PVOID			pBtCoexist,
++	IN	u1Byte			dispType
++	);
++
++typedef COL_H2C_STATUS
++(*BFP_BTC_COEX_H2C_PROCESS)(
++	IN	PVOID			pBtCoexist,
++	IN	u1Byte			opcode,
++	IN	u1Byte			opcode_ver,
++	IN	pu1Byte			ph2c_par,
++	IN	u1Byte			h2c_par_len
++	);
++
++typedef u4Byte
++(*BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE)(
++	IN	PVOID			pBtcContext
++	);
++
++typedef u4Byte
++(*BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION)(
++	IN	PVOID			pBtcContext
++	);
++
++typedef u4Byte
++(*BFP_BTC_GET_PHYDM_VERSION)(
++	IN	PVOID			pBtcContext
++	);
++
++typedef u1Byte
++(*BFP_BTC_SET_TIMER) 	(
++	IN	PVOID			pBtcContext,
++	IN	u4Byte 			type,
++	IN	u4Byte			val
++	);
++
++typedef u4Byte
++(*BFP_BTC_SET_ATOMIC) 	(
++	IN	PVOID			pBtcContext,
++	IN	pu4Byte 		target,
++	IN	u4Byte			val
++	);
++
++
++typedef VOID
++(*BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD)(
++	IN	PVOID		pDM_Odm,
++	IN	u1Byte		RA_offset_direction,
++	IN	u1Byte		RA_threshold_offset
++	);
++
++typedef u4Byte
++(*BTC_PHYDM_CMNINFOQUERY)(
++	IN		PVOID	pDM_Odm,
++	IN		u1Byte	info_type
++	);
++
++typedef VOID
++(*BTC_REDUCE_WL_TX_POWER)(
++	IN		PVOID		pDM_Odm,
++	IN		s1Byte		tx_power
++	);
++
++typedef VOID
++(*BTC_PHYDM_MODIFY_ANTDIV_HWSW)(
++	IN		PVOID	pDM_Odm,
++	IN		u1Byte	type
++	);
++
++typedef u1Byte
++(*BFP_BTC_GET_ANT_DET_VAL_FROM_BT)(
++
++	IN	PVOID			pBtcContext
++	);
++
++typedef u1Byte
++(*BFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT)(
++	IN	PVOID			pBtcContext
++	);
++
++typedef u4Byte
++(*BFP_BTC_GET_BLE_SCAN_PARA_FROM_BT)(
++	IN	PVOID			pBtcContext,
++	IN  u1Byte			scanType
++	);
++
++typedef BOOLEAN
++(*BFP_BTC_GET_BT_AFH_MAP_FROM_BT)(
++	IN	PVOID			pBtcContext,
++	IN	u1Byte			mapType,
++	OUT	pu1Byte			afhMap
++	);
++
++struct  btc_bt_info {
++	boolean					bt_disabled;
++	boolean				bt_enable_disable_change;
++	u8					rssi_adjust_for_agc_table_on;
++	u8					rssi_adjust_for_1ant_coex_type;
++	boolean					pre_bt_ctrl_agg_buf_size;
++	boolean					bt_ctrl_agg_buf_size;
++	boolean					pre_reject_agg_pkt;
++	boolean					reject_agg_pkt;
++	boolean					increase_scan_dev_num;
++	boolean					bt_tx_rx_mask;
++	u8					pre_agg_buf_size;
++	u8					agg_buf_size;
++	boolean					bt_busy;
++	boolean					limited_dig;
++	u16					bt_hci_ver;
++	u32					bt_real_fw_ver;
++	u32					get_bt_fw_ver_cnt;
++	u32					bt_get_fw_ver;
++	boolean					miracast_plus_bt;
++
++	boolean					bt_disable_low_pwr;
++
++	boolean					bt_ctrl_lps;
++	boolean					bt_lps_on;
++	boolean					force_to_roam;	/* for 1Ant solution */
++	u8					lps_val;
++	u8					rpwm_val;
++	u32					ra_mask;
++};
++
++struct btc_stack_info {
++	boolean					profile_notified;
++	u16					hci_version;	/* stack hci version */
++	u8					num_of_link;
++	boolean					bt_link_exist;
++	boolean					sco_exist;
++	boolean					acl_exist;
++	boolean					a2dp_exist;
++	boolean					hid_exist;
++	u8					num_of_hid;
++	boolean					pan_exist;
++	boolean					unknown_acl_exist;
++	s8					min_bt_rssi;
++};
++
++struct btc_bt_link_info {
++	boolean					bt_link_exist;
++	boolean					bt_hi_pri_link_exist;
++	boolean					sco_exist;
++	boolean					sco_only;
++	boolean					a2dp_exist;
++	boolean					a2dp_only;
++	boolean					hid_exist;
++	boolean					hid_only;
++	boolean					pan_exist;
++	boolean					pan_only;
++	boolean					slave_role;
++	boolean					acl_busy;
++};
++
++#ifdef CONFIG_RF4CE_COEXIST
++struct btc_rf4ce_info {
++	u8					link_state;
++};
++#endif
++
++struct btc_statistics {
++	u32					cnt_bind;
++	u32					cnt_power_on;
++	u32					cnt_pre_load_firmware;
++	u32					cnt_init_hw_config;
++	u32					cnt_init_coex_dm;
++	u32					cnt_ips_notify;
++	u32					cnt_lps_notify;
++	u32					cnt_scan_notify;
++	u32					cnt_connect_notify;
++	u32					cnt_media_status_notify;
++	u32					cnt_specific_packet_notify;
++	u32					cnt_bt_info_notify;
++	u32					cnt_rf_status_notify;
++	u32					cnt_periodical;
++	u32					cnt_coex_dm_switch;
++	u32					cnt_stack_operation_notify;
++	u32					cnt_dbg_ctrl;
++	u32					cnt_rate_id_notify;
++	u32					cnt_halt_notify;
++	u32					cnt_pnp_notify;
++};
++
++struct btc_coexist {
++	BOOLEAN				bBinded;		/*make sure only one adapter can bind the data context*/
++	PVOID				Adapter;		/*default adapter*/
++	struct  btc_board_info		board_info;
++	struct  btc_bt_info			bt_info;		/*some bt info referenced by non-bt module*/
++	struct  btc_stack_info		stack_info;
++	struct  btc_bt_link_info		bt_link_info;
++	struct btc_wifi_link_info	wifi_link_info;
++	struct btc_wifi_link_info_ext		wifi_link_info_ext;
++	struct btc_coex_dm			coex_dm;
++	struct btc_coex_sta			coex_sta;
++	struct btc_rfe_type			rfe_type;
++	const struct btc_chip_para		*chip_para;
++
++#ifdef CONFIG_RF4CE_COEXIST
++	struct  btc_rf4ce_info		rf4ce_info;
++#endif
++	BTC_CHIP_INTERFACE		chip_interface;
++	PVOID					odm_priv;
++
++	BOOLEAN					initilized;
++	BOOLEAN					stop_coex_dm;
++	BOOLEAN					manual_control;
++	BOOLEAN					bdontenterLPS;
++	pu1Byte					cli_buf;
++	struct btc_statistics		statistics;
++	u1Byte				pwrModeVal[10];
++	BOOLEAN dbg_mode;
++	BOOLEAN auto_report;
++	u8	chip_type;
++	BOOLEAN wl_rf_state_off;
++
++	/* function pointers */
++	/* io related */
++	BFP_BTC_R1			btc_read_1byte;
++	BFP_BTC_W1			btc_write_1byte;
++	BFP_BTC_W1_BIT_MASK	btc_write_1byte_bitmask;
++	BFP_BTC_R2			btc_read_2byte;
++	BFP_BTC_W2			btc_write_2byte;
++	BFP_BTC_R4			btc_read_4byte;
++	BFP_BTC_W4			btc_write_4byte;
++	BFP_BTC_LOCAL_REG_W1	btc_write_local_reg_1byte;
++	BFP_BTC_R_LINDIRECT		btc_read_linderct;
++	BFP_BTC_W_LINDIRECT		btc_write_linderct;
++	BFP_BTC_R_SCBD			btc_read_scbd;
++	BFP_BTC_W_SCBD			btc_write_scbd;
++	/* read/write bb related */
++	BFP_BTC_SET_BB_REG	btc_set_bb_reg;
++	BFP_BTC_GET_BB_REG	btc_get_bb_reg;
++
++	/* read/write rf related */
++	BFP_BTC_SET_RF_REG	btc_set_rf_reg;
++	BFP_BTC_GET_RF_REG	btc_get_rf_reg;
++
++	/* fill h2c related */
++	BFP_BTC_FILL_H2C		btc_fill_h2c;
++	/* other */
++	BFP_BTC_DISP_DBG_MSG	btc_disp_dbg_msg;
++	/* normal get/set related */
++	BFP_BTC_GET			btc_get;
++	BFP_BTC_SET			btc_set;
++
++	BFP_BTC_GET_BT_REG	btc_get_bt_reg;
++	BFP_BTC_SET_BT_REG	btc_set_bt_reg;
++
++	BFP_BTC_SET_BT_ANT_DETECTION	btc_set_bt_ant_detection;
++
++	BFP_BTC_COEX_H2C_PROCESS	btc_coex_h2c_process;
++	BFP_BTC_SET_BT_TRX_MASK		btc_set_bt_trx_mask;
++	BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE btc_get_bt_coex_supported_feature;
++	BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION btc_get_bt_coex_supported_version;
++	BFP_BTC_GET_PHYDM_VERSION		btc_get_bt_phydm_version;
++	BFP_BTC_SET_TIMER				btc_set_timer;
++	BFP_BTC_SET_ATOMIC			btc_set_atomic;
++	BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD	btc_phydm_modify_RA_PCR_threshold;
++	BTC_PHYDM_CMNINFOQUERY				btc_phydm_query_PHY_counter;
++	BTC_REDUCE_WL_TX_POWER				btc_reduce_wl_tx_power;
++	BTC_PHYDM_MODIFY_ANTDIV_HWSW		btc_phydm_modify_antdiv_hwsw;
++	BFP_BTC_GET_ANT_DET_VAL_FROM_BT		btc_get_ant_det_val_from_bt;
++	BFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT	btc_get_ble_scan_type_from_bt;
++	BFP_BTC_GET_BLE_SCAN_PARA_FROM_BT	btc_get_ble_scan_para_from_bt;
++	BFP_BTC_GET_BT_AFH_MAP_FROM_BT		btc_get_bt_afh_map_from_bt;
++
++	union {
++		#ifdef CONFIG_RTL8822B
++		struct coex_dm_8822b_1ant	coex_dm_8822b_1ant;
++		struct coex_dm_8822b_2ant	coex_dm_8822b_2ant;
++		#endif /* 8822B */
++		#ifdef CONFIG_RTL8821C
++		struct coex_dm_8821c_1ant	coex_dm_8821c_1ant;
++		struct coex_dm_8821c_2ant	coex_dm_8821c_2ant;
++		#endif /* 8821C */
++        #ifdef CONFIG_RTL8723D
++        struct coex_dm_8723d_1ant   coex_dm_8723d_1ant;
++        struct coex_dm_8723d_2ant   coex_dm_8723d_2ant;
++        #endif /* 8723D */
++	};
++
++	union {
++		#ifdef CONFIG_RTL8822B
++		struct coex_sta_8822b_1ant	coex_sta_8822b_1ant;
++		struct coex_sta_8822b_2ant	coex_sta_8822b_2ant;
++		#endif /* 8822B */
++		#ifdef CONFIG_RTL8821C
++		struct coex_sta_8821c_1ant	coex_sta_8821c_1ant;
++		struct coex_sta_8821c_2ant	coex_sta_8821c_2ant;
++		#endif /* 8821C */
++        #ifdef CONFIG_RTL8723D
++        struct coex_sta_8723d_1ant  coex_sta_8723d_1ant;
++        struct coex_sta_8723d_2ant  coex_sta_8723d_2ant;
++        #endif /* 8723D */
++	};
++
++	union {
++		#ifdef CONFIG_RTL8822B
++		struct rfe_type_8822b_1ant	rfe_type_8822b_1ant;
++		struct rfe_type_8822b_2ant	rfe_type_8822b_2ant;
++		#endif /* 8822B */
++		#ifdef CONFIG_RTL8821C
++		struct rfe_type_8821c_1ant	rfe_type_8821c_1ant;
++		struct rfe_type_8821c_2ant	rfe_type_8821c_2ant;
++		#endif /* 8821C */
++	};
++
++	union {
++		#ifdef CONFIG_RTL8822B
++		struct wifi_link_info_8822b_1ant	wifi_link_info_8822b_1ant;
++		struct wifi_link_info_8822b_2ant	wifi_link_info_8822b_2ant;
++		#endif /* 8822B */
++		#ifdef CONFIG_RTL8821C
++		struct wifi_link_info_8821c_1ant	wifi_link_info_8821c_1ant;
++		struct wifi_link_info_8821c_2ant	wifi_link_info_8821c_2ant;
++		#endif /* 8821C */
++	};
++
++};
++typedef struct btc_coexist *PBTC_COEXIST;
++
++extern struct btc_coexist	GLBtCoexist;
++
++typedef	void
++(*BFP_BTC_CHIP_SETUP)(
++	IN	PBTC_COEXIST	pBtCoexist,
++	IN	u1Byte			setType
++	);
++
++struct btc_chip_para {
++	const char				*chip_name;
++	u32				para_ver_date;
++	u32				para_ver;
++	u32				bt_desired_ver;
++	boolean			scbd_support;
++	boolean			mailbox_support;
++	boolean			lte_indirect_access;
++	boolean			new_scbd10_def; /* TRUE: 1:fix 2M(8822c) */
++	u8				indirect_type;	/* 0:17xx, 1:7cx */
++	u8				pstdma_type; /* 0: LPSoff, 1:LPSon */
++	u8				bt_rssi_type;
++	u8				ant_isolation;
++	u8				rssi_tolerance;
++	u8				rx_path_num;
++	u8				wl_rssi_step_num;
++	const u8				*wl_rssi_step;
++	u8				bt_rssi_step_num;
++	const u8				*bt_rssi_step;
++	u8				table_sant_num;
++	const struct btc_coex_table_para 	*table_sant;
++	u8				table_nsant_num;
++	const struct btc_coex_table_para 	*table_nsant;
++	u8				tdma_sant_num;
++	const struct btc_tdma_para 	*tdma_sant;
++	u8				tdma_nsant_num;
++	const struct btc_tdma_para 	*tdma_nsant;
++	u8				wl_rf_para_tx_num;
++	const struct btc_rf_para		*wl_rf_para_tx;
++	const struct btc_rf_para		*wl_rf_para_rx;
++	u8				bt_afh_span_bw20;
++	u8				bt_afh_span_bw40;
++	u8				afh_5g_num;
++	const struct btc_5g_afh_map	*afh_5g;
++	BFP_BTC_CHIP_SETUP		chip_setup;
++};
++
++BOOLEAN
++EXhalbtcoutsrc_InitlizeVariables(
++	IN	PVOID		Adapter
++	);
++VOID
++EXhalbtcoutsrc_PowerOnSetting(
++	IN	PBTC_COEXIST		pBtCoexist
++	);
++VOID
++EXhalbtcoutsrc_PreLoadFirmware(
++	IN	PBTC_COEXIST		pBtCoexist
++	);
++VOID
++EXhalbtcoutsrc_InitHwConfig(
++	IN	PBTC_COEXIST		pBtCoexist,
++	IN	BOOLEAN				bWifiOnly
++	);
++VOID
++EXhalbtcoutsrc_InitCoexDm(
++	IN	PBTC_COEXIST		pBtCoexist
++	);
++VOID
++EXhalbtcoutsrc_IpsNotify(
++	IN	PBTC_COEXIST		pBtCoexist,
++	IN	u1Byte			type
++	);
++VOID
++EXhalbtcoutsrc_LpsNotify(
++	IN	PBTC_COEXIST		pBtCoexist,
++	IN	u1Byte			type
++	);
++VOID
++EXhalbtcoutsrc_ScanNotify(
++	IN	PBTC_COEXIST		pBtCoexist,
++	IN	u1Byte			type
++	);
++VOID
++EXhalbtcoutsrc_SetAntennaPathNotify(
++	IN	PBTC_COEXIST	pBtCoexist,
++	IN	u1Byte			type
++	);
++VOID
++EXhalbtcoutsrc_ConnectNotify(
++	IN	PBTC_COEXIST		pBtCoexist,
++	IN	u1Byte			action
++	);
++VOID
++EXhalbtcoutsrc_MediaStatusNotify(
++	IN	PBTC_COEXIST		pBtCoexist,
++	IN	RT_MEDIA_STATUS	mediaStatus
++	);
++VOID
++EXhalbtcoutsrc_SpecificPacketNotify(
++	IN	PBTC_COEXIST		pBtCoexist,
++	IN	u1Byte			pktType
++	);
++VOID
++EXhalbtcoutsrc_BtInfoNotify(
++	IN	PBTC_COEXIST		pBtCoexist,
++	IN	pu1Byte			tmpBuf,
++	IN	u1Byte			length
++	);
++VOID
++EXhalbtcoutsrc_RfStatusNotify(
++	IN	PBTC_COEXIST		pBtCoexist,
++	IN	u1Byte				type
++	);
++u4Byte
++EXhalbtcoutsrc_CoexTimerCheck(
++	IN	PBTC_COEXIST		pBtCoexist
++	);
++u4Byte
++EXhalbtcoutsrc_WLStatusCheck(
++	IN	PBTC_COEXIST		pBtCoexist
++	);
++VOID
++EXhalbtcoutsrc_WlFwDbgInfoNotify(
++	IN	PBTC_COEXIST		pBtCoexist,
++	IN	pu1Byte			tmpBuf,
++	IN	u1Byte			length
++	);
++VOID
++EXhalbtcoutsrc_rx_rate_change_notify(
++	IN	PBTC_COEXIST	pBtCoexist,
++	IN 	BOOLEAN			is_data_frame,
++	IN	u1Byte			btc_rate_id
++	);
++VOID
++EXhalbtcoutsrc_StackOperationNotify(
++	IN	PBTC_COEXIST		pBtCoexist,
++	IN	u1Byte			type
++	);
++VOID
++EXhalbtcoutsrc_HaltNotify(
++	IN	PBTC_COEXIST		pBtCoexist
++	);
++VOID
++EXhalbtcoutsrc_PnpNotify(
++	IN	PBTC_COEXIST		pBtCoexist,
++	IN	u1Byte			pnpState
++	);
++VOID
++EXhalbtcoutsrc_TimerNotify(
++	IN	PBTC_COEXIST		pBtCoexist,
++	IN	u4Byte timer_type
++);
++VOID
++EXhalbtcoutsrc_WLStatusChangeNotify(
++	IN	PBTC_COEXIST		pBtCoexist,
++	IN	u4Byte change_type
++);
++VOID
++EXhalbtcoutsrc_CoexDmSwitch(
++	IN	PBTC_COEXIST		pBtCoexist
++	);
++VOID
++EXhalbtcoutsrc_Periodical(
++	IN	PBTC_COEXIST		pBtCoexist
++	);
++VOID
++EXhalbtcoutsrc_DbgControl(
++	IN	PBTC_COEXIST			pBtCoexist,
++	IN	u1Byte				opCode,
++	IN	u1Byte				opLen,
++	IN	pu1Byte				pData
++	);
++VOID
++EXhalbtcoutsrc_AntennaDetection(
++	IN	PBTC_COEXIST			pBtCoexist,
++	IN	u4Byte					centFreq,
++	IN	u4Byte					offset,
++	IN	u4Byte					span,
++	IN	u4Byte					seconds
++	);
++VOID
++EXhalbtcoutsrc_StackUpdateProfileInfo(
++	VOID
++	);
++VOID
++EXhalbtcoutsrc_SetHciVersion(
++	IN	u2Byte	hciVersion
++	);
++VOID
++EXhalbtcoutsrc_SetBtPatchVersion(
++	IN	u2Byte	btHciVersion,
++	IN	u2Byte	btPatchVersion
++	);
++VOID
++EXhalbtcoutsrc_UpdateMinBtRssi(
++	IN	s1Byte	btRssi
++	);
++#if 0
++VOID
++EXhalbtcoutsrc_SetBtExist(
++	IN	BOOLEAN		bBtExist
++	);
++#endif
++VOID
++EXhalbtcoutsrc_SetChipType(
++	IN	u1Byte		chipType
++	);
++VOID
++EXhalbtcoutsrc_SetAntNum(
++	IN	u1Byte		type,
++	IN	u1Byte		antNum
++	);
++VOID
++EXhalbtcoutsrc_SetSingleAntPath(
++	IN	u1Byte		singleAntPath
++	);
++VOID
++EXhalbtcoutsrc_DisplayBtCoexInfo(
++	IN	PBTC_COEXIST		pBtCoexist
++	);
++VOID
++EXhalbtcoutsrc_DisplayAntDetection(
++	IN	PBTC_COEXIST		pBtCoexist
++	);
++
++#define	MASKBYTE0		0xff
++#define	MASKBYTE1		0xff00
++#define	MASKBYTE2		0xff0000
++#define	MASKBYTE3		0xff000000
++#define	MASKHWORD	0xffff0000
++#define	MASKLWORD		0x0000ffff
++#define	MASKDWORD	0xffffffff
++#define	MASK12BITS		0xfff
++#define	MASKH4BITS		0xf0000000
++#define	MASKOFDM_D	0xffc00000
++#define	MASKCCK		0x3f3f3f3f
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/mp_precomp.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/mp_precomp.h
+new file mode 100644
+index 000000000..262593693
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/btc/mp_precomp.h
+@@ -0,0 +1,159 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __MP_PRECOMP_H__
++#define __MP_PRECOMP_H__
++
++#include <drv_types.h>
++#include <hal_data.h>
++#include "btc_basic_types.h"
++
++#define BT_TMP_BUF_SIZE	100
++
++#ifdef PLATFORM_LINUX
++#define rsprintf snprintf
++#define rstrncat(dst, src, src_size) strncat(dst, src, src_size)
++#elif defined(PLATFORM_WINDOWS)
++#define rsprintf sprintf_s
++#endif
++
++#define DCMD_Printf			DBG_BT_INFO
++
++#define delay_ms(ms)		rtw_mdelay_os(ms)
++
++#ifdef bEnable
++#undef bEnable
++#endif
++
++#define WPP_SOFTWARE_TRACE 0
++
++typedef enum _BTC_MSG_COMP_TYPE {
++	COMP_COEX		= 0,
++	COMP_MAX
++} BTC_MSG_COMP_TYPE;
++extern u4Byte GLBtcDbgType[];
++
++#define DBG_OFF			0
++#define DBG_SEC			1
++#define DBG_SERIOUS		2
++#define DBG_WARNING		3
++#define DBG_LOUD		4
++#define DBG_TRACE		5
++
++#ifdef CONFIG_BT_COEXIST
++#define BT_SUPPORT		1
++#define COEX_SUPPORT	1
++#define HS_SUPPORT		1
++#else
++#define BT_SUPPORT		0
++#define COEX_SUPPORT	0
++#define HS_SUPPORT		0
++#endif
++
++/* for wifi only mode */
++#include "hal_btcoex_wifionly.h"
++
++#ifdef CONFIG_BT_COEXIST
++#define BTC_BTINFO_LENGTH_MAX 10
++
++struct wifi_only_cfg;
++struct btc_coexist;
++
++#ifdef CONFIG_RTL8192E
++#include "halbtc8192e1ant.h"
++#include "halbtc8192e2ant.h"
++#endif
++
++#ifdef CONFIG_RTL8723B
++#include "halbtc8723bwifionly.h"
++#include "halbtc8723b1ant.h"
++#include "halbtc8723b2ant.h"
++#endif
++
++#ifdef CONFIG_RTL8812A
++#include "halbtc8812a1ant.h"
++#include "halbtc8812a2ant.h"
++#endif
++
++#ifdef CONFIG_RTL8821A
++#include "halbtc8821a1ant.h"
++#include "halbtc8821a2ant.h"
++#endif
++
++#ifdef CONFIG_RTL8703B
++#include "halbtc8703b1ant.h"
++#endif
++
++#ifdef CONFIG_RTL8723D
++#include "halbtc8723d1ant.h"
++#include "halbtc8723d2ant.h"
++#endif
++
++#ifdef CONFIG_RTL8822B
++#include "halbtc8822bwifionly.h"
++#include "halbtc8822b1ant.h"
++#include "halbtc8822b2ant.h"
++#endif
++
++#ifdef CONFIG_RTL8821C
++#include "halbtc8821cwifionly.h"
++#include "halbtc8821c1ant.h"
++#include "halbtc8821c2ant.h"
++#endif
++
++#ifdef CONFIG_RTL8814A
++#include "halbtc8814a2ant.h"
++#endif
++
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++#include "halbtccommon.h"
++
++#ifdef CONFIG_RTL8822C
++#include "halbtc8822cwifionly.h"
++#include "halbtc8822c.h"
++#endif
++
++#ifdef CONFIG_RTL8192F
++#include "halbtc8192f.h"
++#endif
++
++#endif
++
++#include "halbtcoutsrc.h"
++
++#else /* CONFIG_BT_COEXIST */
++
++#ifdef CONFIG_RTL8723B
++#include "halbtc8723bwifionly.h"
++#endif
++
++#ifdef CONFIG_RTL8822B
++#include "halbtc8822bwifionly.h"
++#endif
++
++#ifdef CONFIG_RTL8821C
++#include "halbtc8821cwifionly.h"
++#endif
++
++#ifdef CONFIG_RTL8822C
++#include "halbtc8822cwifionly.h"
++#endif
++
++#ifdef CONFIG_RTL8814B
++#include "halbtc8814bwifionly.h"
++#endif
++
++#endif /* CONFIG_BT_COEXIST */
++
++#endif /*  __MP_PRECOMP_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/efuse_mask.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/efuse_mask.h
+new file mode 100644
+index 000000000..139a1efd6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/efuse_mask.h
+@@ -0,0 +1,181 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifdef CONFIG_USB_HCI
++
++	#if defined(CONFIG_RTL8188E)
++		#include "rtl8188e/HalEfuseMask8188E_USB.h"
++	#endif
++
++	#if defined(CONFIG_RTL8812A)
++		#include "rtl8812a/HalEfuseMask8812A_USB.h"
++	#endif
++
++	#if defined(CONFIG_RTL8821A)
++		#include "rtl8812a/HalEfuseMask8821A_USB.h"
++	#endif
++
++	#if defined(CONFIG_RTL8192E)
++		#include "rtl8192e/HalEfuseMask8192E_USB.h"
++	#endif
++
++	#if defined(CONFIG_RTL8723B)
++		#include "rtl8723b/HalEfuseMask8723B_USB.h"
++	#endif
++
++	#if defined(CONFIG_RTL8814A)
++		#include "rtl8814a/HalEfuseMask8814A_USB.h"
++	#endif
++
++	#if defined(CONFIG_RTL8703B)
++		#include "rtl8703b/HalEfuseMask8703B_USB.h"
++	#endif
++
++	#if defined(CONFIG_RTL8723D)
++		#include "rtl8723d/HalEfuseMask8723D_USB.h"
++	#endif
++
++	#if defined(CONFIG_RTL8188F)
++		#include "rtl8188f/HalEfuseMask8188F_USB.h"
++	#endif
++
++	#if defined(CONFIG_RTL8188GTV)
++		#include "rtl8188gtv/HalEfuseMask8188GTV_USB.h"
++	#endif
++
++	#if defined(CONFIG_RTL8822B)
++		#include "rtl8822b/HalEfuseMask8822B_USB.h"
++	#endif
++
++	#if defined(CONFIG_RTL8821C)
++		#include "rtl8821c/HalEfuseMask8821C_USB.h"
++	#endif
++	
++	#if defined(CONFIG_RTL8710B)
++		#include "rtl8710b/HalEfuseMask8710B_USB.h"
++	#endif
++	
++	#if defined(CONFIG_RTL8192F)
++		#include "rtl8192f/HalEfuseMask8192F_USB.h"
++	#endif
++	#if defined(CONFIG_RTL8822C)
++		#include "rtl8822c/HalEfuseMask8822C_USB.h"
++	#endif
++	#if defined(CONFIG_RTL8814B)
++		#include "rtl8814b/HalEfuseMask8814B_USB.h"
++	#endif
++#endif /*CONFIG_USB_HCI*/
++
++#ifdef CONFIG_PCI_HCI
++
++	#if defined(CONFIG_RTL8188E)
++		#include "rtl8188e/HalEfuseMask8188E_PCIE.h"
++	#endif
++
++	#if defined(CONFIG_RTL8812A)
++		#include "rtl8812a/HalEfuseMask8812A_PCIE.h"
++	#endif
++
++	#if defined(CONFIG_RTL8821A)
++		#include "rtl8812a/HalEfuseMask8821A_PCIE.h"
++	#endif
++
++	#if defined(CONFIG_RTL8192E)
++		#include "rtl8192e/HalEfuseMask8192E_PCIE.h"
++	#endif
++
++	#if defined(CONFIG_RTL8723B)
++		#include "rtl8723b/HalEfuseMask8723B_PCIE.h"
++	#endif
++
++	#if defined(CONFIG_RTL8814A)
++		#include "rtl8814a/HalEfuseMask8814A_PCIE.h"
++	#endif
++
++	#if defined(CONFIG_RTL8703B)
++		#include "rtl8703b/HalEfuseMask8703B_PCIE.h"
++	#endif
++
++	#if defined(CONFIG_RTL8822B)
++		#include "rtl8822b/HalEfuseMask8822B_PCIE.h"
++	#endif
++	#if defined(CONFIG_RTL8723D)
++		#include "rtl8723d/HalEfuseMask8723D_PCIE.h"
++	#endif
++	#if defined(CONFIG_RTL8821C)
++		#include "rtl8821c/HalEfuseMask8821C_PCIE.h"
++	#endif
++
++	#if defined(CONFIG_RTL8192F)
++		#include "rtl8192f/HalEfuseMask8192F_PCIE.h"
++	#endif
++	#if defined(CONFIG_RTL8822C)
++		#include "rtl8822c/HalEfuseMask8822C_PCIE.h"
++	#endif
++	#if defined(CONFIG_RTL8814B)
++		#include "rtl8814b/HalEfuseMask8814B_PCIE.h"
++	#endif
++#endif /*CONFIG_PCI_HCI*/
++#ifdef CONFIG_SDIO_HCI
++	#if defined(CONFIG_RTL8723B)
++		#include "rtl8723b/HalEfuseMask8723B_SDIO.h"
++	#endif
++
++	#if defined(CONFIG_RTL8188E)
++		#include "rtl8188e/HalEfuseMask8188E_SDIO.h"
++	#endif
++
++	#if defined(CONFIG_RTL8703B)
++		#include "rtl8703b/HalEfuseMask8703B_SDIO.h"
++	#endif
++
++	#if defined(CONFIG_RTL8188F)
++		#include "rtl8188f/HalEfuseMask8188F_SDIO.h"
++	#endif
++
++	#if defined(CONFIG_RTL8188GTV)
++		#include "rtl8188gtv/HalEfuseMask8188GTV_SDIO.h"
++	#endif
++
++	#if defined(CONFIG_RTL8723D)
++		#include "rtl8723d/HalEfuseMask8723D_SDIO.h"
++	#endif
++
++	#if defined(CONFIG_RTL8192E)
++		#include "rtl8192e/HalEfuseMask8192E_SDIO.h"
++	#endif
++
++	#if defined(CONFIG_RTL8821A)
++		#include "rtl8812a/HalEfuseMask8821A_SDIO.h"
++	#endif
++
++	#if defined(CONFIG_RTL8821C)
++		#include "rtl8821c/HalEfuseMask8821C_SDIO.h"
++	#endif
++
++	#if defined(CONFIG_RTL8822B)
++		#include "rtl8822b/HalEfuseMask8822B_SDIO.h"
++	#endif
++
++	#if defined(CONFIG_RTL8192F)
++		#include "rtl8192f/HalEfuseMask8192F_SDIO.h"
++	#endif
++
++
++	#if defined(CONFIG_RTL8822C)
++		#include "rtl8822c/HalEfuseMask8822C_SDIO.h"
++	#endif
++
++#endif /*CONFIG_SDIO_HCI*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_PCIE.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_PCIE.c
+new file mode 100644
+index 000000000..635ab7b99
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_PCIE.c
+@@ -0,0 +1,91 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/*#include "Mp_Precomp.h"*/
++#include <drv_types.h>
++
++#include "HalEfuseMask8723D_PCIE.h"
++
++/******************************************************************************
++*                           MPCIE.TXT
++******************************************************************************/
++
++u8 Array_MP_8723D_MPCIE[] = {
++	0xFF,
++	0xF3,
++	0x00,
++	0x0E,
++	0x70,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x07,
++	0xF3,
++	0xFF,
++	0xFF,
++	0x7C,
++	0x30,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++};
++
++u16
++EFUSE_GetArrayLen_MP_8723D_MPCIE(void)
++{
++	return sizeof(Array_MP_8723D_MPCIE) / sizeof(u8);
++}
++
++void
++EFUSE_GetMaskArray_MP_8723D_MPCIE(
++		u8 *Array
++)
++{
++	u16 len = EFUSE_GetArrayLen_MP_8723D_MPCIE(), i = 0;
++
++	for (i = 0; i < len; ++i)
++		Array[i] = Array_MP_8723D_MPCIE[i];
++}
++BOOLEAN
++EFUSE_IsAddressMasked_MP_8723D_MPCIE(
++		u16 Offset
++)
++{
++	int r = Offset / 16;
++	int c = (Offset % 16) / 2;
++	int result = 0;
++
++	if (c < 4) /* Upper double word */
++		result = (Array_MP_8723D_MPCIE[r] & (0x10 << c));
++	else
++		result = (Array_MP_8723D_MPCIE[r] & (0x01 << (c - 4)));
++
++	return (result > 0) ? 0 : 1;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_PCIE.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_PCIE.h
+new file mode 100644
+index 000000000..ff2c96dc3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_PCIE.h
+@@ -0,0 +1,32 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/******************************************************************************
++*                           MPCIE.TXT
++******************************************************************************/
++
++
++u16
++EFUSE_GetArrayLen_MP_8723D_MPCIE(void);
++
++void
++EFUSE_GetMaskArray_MP_8723D_MPCIE(
++		u8 *Array
++);
++
++BOOLEAN
++EFUSE_IsAddressMasked_MP_8723D_MPCIE(/* TC: Test Chip, MP: MP Chip */
++		u16 Offset
++);
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_SDIO.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_SDIO.c
+new file mode 100644
+index 000000000..d6cc4efc5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_SDIO.c
+@@ -0,0 +1,89 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <drv_types.h>
++#include "HalEfuseMask8723D_SDIO.h"
++
++/******************************************************************************
++*                           MSDIO.TXT
++******************************************************************************/
++
++u8 Array_MP_8723D_MSDIO[] = {
++	0xFF,
++	0xF3,
++	0x00,
++	0x0E,
++	0x70,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x07,
++	0xF3,
++	0xFF,
++	0xFF,
++	0xFF,
++	0xFF,
++	0xFF,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++};
++
++u16
++EFUSE_GetArrayLen_MP_8723D_MSDIO(void)
++{
++	return sizeof(Array_MP_8723D_MSDIO) / sizeof(u8);
++}
++
++void
++EFUSE_GetMaskArray_MP_8723D_MSDIO(
++		u8 *Array
++)
++{
++	u16 len = EFUSE_GetArrayLen_MP_8723D_MSDIO(), i = 0;
++
++	for (i = 0; i < len; ++i)
++		Array[i] = Array_MP_8723D_MSDIO[i];
++}
++BOOLEAN
++EFUSE_IsAddressMasked_MP_8723D_MSDIO(
++		u16 Offset
++)
++{
++	int r = Offset / 16;
++	int c = (Offset % 16) / 2;
++	int result = 0;
++	/* Upper double word */
++	if (c < 4)
++		result = (Array_MP_8723D_MSDIO[r] & (0x10 << c));
++	else
++		result = (Array_MP_8723D_MSDIO[r] & (0x01 << (c - 4)));
++
++	return (result > 0) ? 0 : 1;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_SDIO.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_SDIO.h
+new file mode 100644
+index 000000000..701b1915d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_SDIO.h
+@@ -0,0 +1,31 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/******************************************************************************
++*                           MSDIO.TXT
++******************************************************************************/
++
++u16
++EFUSE_GetArrayLen_MP_8723D_MSDIO(void);
++
++void
++EFUSE_GetMaskArray_MP_8723D_MSDIO(
++		u8 *Array
++);
++/* TC: Test Chip, MP: MP Chip */
++BOOLEAN
++EFUSE_IsAddressMasked_MP_8723D_MSDIO(
++		u16 Offset
++);
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_USB.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_USB.c
+new file mode 100644
+index 000000000..2b1caf241
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_USB.c
+@@ -0,0 +1,92 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/* #include "Mp_Precomp.h" */
++/* #include "../odm_precomp.h" */
++
++#include <drv_types.h>
++#include "HalEfuseMask8723D_USB.h"
++/******************************************************************************
++*                           MUSB.TXT
++******************************************************************************/
++
++u8 Array_MP_8723D_MUSB[] = {
++	0xFF,
++	0xF3,
++	0x00,
++	0x0E,
++	0x70,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x07,
++	0xF3,
++	0x00,
++	0x00,
++	0x00,
++	0xFF,
++	0xFF,
++	0xFF,
++	0xFF,
++	0xB0,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++	0x00,
++
++};
++
++u16
++EFUSE_GetArrayLen_MP_8723D_MUSB(void)
++{
++	return sizeof(Array_MP_8723D_MUSB) / sizeof(u8);
++}
++
++void
++EFUSE_GetMaskArray_MP_8723D_MUSB(
++		u8 *Array
++)
++{
++	u16 len = EFUSE_GetArrayLen_MP_8723D_MUSB(), i = 0;
++
++	for (i = 0; i < len; ++i)
++		Array[i] = Array_MP_8723D_MUSB[i];
++}
++BOOLEAN
++EFUSE_IsAddressMasked_MP_8723D_MUSB(
++		u16 Offset
++)
++{
++	int r = Offset / 16;
++	int c = (Offset % 16) / 2;
++	int result = 0;
++
++	if (c < 4) /* Upper double word */
++		result = (Array_MP_8723D_MUSB[r] & (0x10 << c));
++	else
++		result = (Array_MP_8723D_MUSB[r] & (0x01 << (c - 4)));
++
++	return (result > 0) ? 0 : 1;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_USB.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_USB.h
+new file mode 100644
+index 000000000..b43838238
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/efuse/rtl8723d/HalEfuseMask8723D_USB.h
+@@ -0,0 +1,34 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++
++
++/******************************************************************************
++*                           MUSB.TXT
++******************************************************************************/
++
++
++u16
++EFUSE_GetArrayLen_MP_8723D_MUSB(void);
++
++void
++EFUSE_GetMaskArray_MP_8723D_MUSB(
++		u8 *Array
++);
++
++BOOLEAN
++EFUSE_IsAddressMasked_MP_8723D_MUSB(/* TC: Test Chip, MP: MP Chip */
++		u16 Offset
++);
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_btcoex.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_btcoex.c
+new file mode 100644
+index 000000000..46a08b000
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_btcoex.c
+@@ -0,0 +1,6388 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define __HAL_BTCOEX_C__
++
++#ifdef CONFIG_BT_COEXIST
++
++#include <hal_data.h>
++#include <hal_btcoex.h>
++#include "btc/mp_precomp.h"
++
++/* ************************************
++ *		Global variables
++ * ************************************ */
++const char *const BtProfileString[] = {
++	"NONE",
++	"A2DP",
++	"PAN",
++	"HID",
++	"SCO",
++};
++
++const char *const BtSpecString[] = {
++	"1.0b",
++	"1.1",
++	"1.2",
++	"2.0+EDR",
++	"2.1+EDR",
++	"3.0+HS",
++	"4.0",
++};
++
++const char *const BtLinkRoleString[] = {
++	"Master",
++	"Slave",
++};
++
++const char *const h2cStaString[] = {
++	"successful",
++	"h2c busy",
++	"rf off",
++	"fw not read",
++};
++
++const char *const ioStaString[] = {
++	"success",
++	"can not IO",
++	"rf off",
++	"fw not read",
++	"wait io timeout",
++	"invalid len",
++	"idle Q empty",
++	"insert waitQ fail",
++	"unknown fail",
++	"wrong level",
++	"h2c stopped",
++};
++
++const char *const GLBtcWifiBwString[] = {
++	"11bg",
++	"HT20",
++	"HT40",
++	"VHT80",
++	"VHT160"
++};
++
++const char *const GLBtcWifiFreqString[] = {
++	"2.4G",
++	"5G",
++	"2.4G+5G"
++};
++
++const char *const GLBtcIotPeerString[] = {
++	"UNKNOWN",
++	"REALTEK",
++	"REALTEK_92SE",
++	"BROADCOM",
++	"RALINK",
++	"ATHEROS",
++	"CISCO",
++	"MERU",
++	"MARVELL",
++	"REALTEK_SOFTAP", /* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */
++	"SELF_SOFTAP", /* Self is SoftAP */
++	"AIRGO",
++	"INTEL",
++	"RTK_APCLIENT",
++	"REALTEK_81XX",
++	"REALTEK_WOW",
++	"REALTEK_JAGUAR_BCUTAP",
++	"REALTEK_JAGUAR_CCUTAP"
++};
++
++const char *const coexOpcodeString[] = {
++	"Wifi status notify",
++	"Wifi progress",
++	"Wifi info",
++	"Power state",
++	"Set Control",
++	"Get Control"
++};
++
++const char *const coexIndTypeString[] = {
++	"bt info",
++	"pstdma",
++	"limited tx/rx",
++	"coex table",
++	"request"
++};
++
++const char *const coexH2cResultString[] = {
++	"ok",
++	"unknown",
++	"un opcode",
++	"opVer MM",
++	"par Err",
++	"par OoR",
++	"reqNum MM",
++	"halMac Fail",
++	"h2c TimeOut",
++	"Invalid c2h Len",
++	"data overflow"
++};
++
++#define HALBTCOUTSRC_AGG_CHK_WINDOW_IN_MS	8000
++
++struct btc_coexist GLBtCoexist;
++BTC_OFFLOAD gl_coex_offload;
++u8 GLBtcWiFiInScanState;
++u8 GLBtcWiFiInIQKState;
++u8 GLBtcWiFiInIPS;
++u8 GLBtcWiFiInLPS;
++u8 GLBtcBtCoexAliveRegistered;
++
++/*
++ * BT control H2C/C2H
++ */
++/* EXT_EID */
++typedef enum _bt_ext_eid {
++	C2H_WIFI_FW_ACTIVE_RSP	= 0,
++	C2H_TRIG_BY_BT_FW
++} BT_EXT_EID;
++
++/* C2H_STATUS */
++typedef enum _bt_c2h_status {
++	BT_STATUS_OK = 0,
++	BT_STATUS_VERSION_MISMATCH,
++	BT_STATUS_UNKNOWN_OPCODE,
++	BT_STATUS_ERROR_PARAMETER
++} BT_C2H_STATUS;
++
++/* C2H BT OP CODES */
++typedef enum _bt_op_code {
++	BT_OP_GET_BT_VERSION					= 0x00,
++	BT_OP_WRITE_REG_ADDR					= 0x0c,
++	BT_OP_WRITE_REG_VALUE					= 0x0d,
++
++	BT_OP_READ_REG							= 0x11,
++
++	BT_LO_OP_GET_AFH_MAP_L					= 0x1e,
++	BT_LO_OP_GET_AFH_MAP_M					= 0x1f,
++	BT_LO_OP_GET_AFH_MAP_H					= 0x20,
++
++	BT_OP_SET_BT_TRX_MASK					= 0x29,
++	BT_OP_GET_BT_COEX_SUPPORTED_FEATURE		= 0x2a,
++	BT_OP_GET_BT_COEX_SUPPORTED_VERSION		= 0x2b,
++	BT_OP_GET_BT_ANT_DET_VAL				= 0x2c,
++	BT_OP_GET_BT_BLE_SCAN_TYPE				= 0x2d,
++	BT_OP_GET_BT_BLE_SCAN_PARA				= 0x2e,
++	BT_OP_GET_BT_DEVICE_INFO				= 0x30,
++	BT_OP_GET_BT_FORBIDDEN_SLOT_VAL			= 0x31,
++	BT_OP_SET_BT_LANCONSTRAIN_LEVEL			= 0x32,
++	BT_OP_SET_BT_TEST_MODE_VAL				= 0x33,
++	BT_OP_MAX
++} BT_OP_CODE;
++
++#define BTC_MPOPER_TIMEOUT	50	/* unit: ms */
++
++#define C2H_MAX_SIZE		16
++u8 GLBtcBtMpOperSeq;
++_mutex GLBtcBtMpOperLock;
++_timer GLBtcBtMpOperTimer;
++_sema GLBtcBtMpRptSema;
++u8 GLBtcBtMpRptSeq;
++u8 GLBtcBtMpRptStatus;
++u8 GLBtcBtMpRptRsp[C2H_MAX_SIZE];
++u8 GLBtcBtMpRptRspSize;
++u8 GLBtcBtMpRptWait;
++u8 GLBtcBtMpRptWiFiOK;
++u8 GLBtcBtMpRptBTOK;
++
++/*
++ * Debug
++ */
++u32 GLBtcDbgType[COMP_MAX];
++u8 GLBtcDbgBuf[BT_TMP_BUF_SIZE];
++u8	gl_btc_trace_buf[BT_TMP_BUF_SIZE];
++
++typedef struct _btcoexdbginfo {
++	u8 *info;
++	u32 size; /* buffer total size */
++	u32 len; /* now used length */
++} BTCDBGINFO, *PBTCDBGINFO;
++
++BTCDBGINFO GLBtcDbgInfo;
++
++#define	BT_Operation(Adapter)						_FALSE
++
++static void DBG_BT_INFO_INIT(PBTCDBGINFO pinfo, u8 *pbuf, u32 size)
++{
++	if (NULL == pinfo)
++		return;
++
++	_rtw_memset(pinfo, 0, sizeof(BTCDBGINFO));
++
++	if (pbuf && size) {
++		pinfo->info = pbuf;
++		pinfo->size = size;
++	}
++}
++
++void DBG_BT_INFO(u8 *dbgmsg)
++{
++	PBTCDBGINFO pinfo;
++	u32 msglen, buflen;
++	u8 *pbuf;
++
++
++	pinfo = &GLBtcDbgInfo;
++
++	if (NULL == pinfo->info)
++		return;
++
++	msglen = strlen(dbgmsg);
++	if (pinfo->len + msglen > pinfo->size)
++		return;
++
++	pbuf = pinfo->info + pinfo->len;
++	_rtw_memcpy(pbuf, dbgmsg, msglen);
++	pinfo->len += msglen;
++}
++
++/* ************************************
++ *		Debug related function
++ * ************************************ */
++static u8 halbtcoutsrc_IsBtCoexistAvailable(PBTC_COEXIST pBtCoexist)
++{
++	if (!pBtCoexist->bBinded ||
++	    NULL == pBtCoexist->Adapter)
++		return _FALSE;
++	return _TRUE;
++}
++
++static void halbtcoutsrc_DbgInit(void)
++{
++	u8	i;
++
++	for (i = 0; i < COMP_MAX; i++)
++		GLBtcDbgType[i] = 0;
++}
++
++static void halbtcoutsrc_EnterPwrLock(PBTC_COEXIST pBtCoexist)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj((PADAPTER)pBtCoexist->Adapter);
++	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
++
++	_enter_pwrlock(&pwrpriv->lock);
++}
++
++static void halbtcoutsrc_ExitPwrLock(PBTC_COEXIST pBtCoexist)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj((PADAPTER)pBtCoexist->Adapter);
++	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
++
++	_exit_pwrlock(&pwrpriv->lock);
++}
++
++static u8 halbtcoutsrc_IsHwMailboxExist(PBTC_COEXIST pBtCoexist)
++{
++	if (pBtCoexist->board_info.bt_chip_type == BTC_CHIP_CSR_BC4
++	    || pBtCoexist->board_info.bt_chip_type == BTC_CHIP_CSR_BC8
++	   )
++		return _FALSE;
++	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter))
++		return _FALSE;
++	else
++		return _TRUE;
++}
++
++static u8 halbtcoutsrc_LeaveLps(PBTC_COEXIST pBtCoexist)
++{
++	PADAPTER padapter;
++
++
++	padapter = pBtCoexist->Adapter;
++
++	pBtCoexist->bt_info.bt_ctrl_lps = _TRUE;
++	pBtCoexist->bt_info.bt_lps_on = _FALSE;
++
++	return rtw_btcoex_LPS_Leave(padapter);
++}
++
++void halbtcoutsrc_EnterLps(PBTC_COEXIST pBtCoexist)
++{
++	PADAPTER padapter;
++
++
++	padapter = pBtCoexist->Adapter;
++
++	if (pBtCoexist->bdontenterLPS == _FALSE) {
++		pBtCoexist->bt_info.bt_ctrl_lps = _TRUE;
++		pBtCoexist->bt_info.bt_lps_on = _TRUE;
++
++		rtw_btcoex_LPS_Enter(padapter);
++	}
++}
++
++void halbtcoutsrc_NormalLps(PBTC_COEXIST pBtCoexist)
++{
++	PADAPTER padapter;
++
++
++
++	padapter = pBtCoexist->Adapter;
++
++	if (pBtCoexist->bt_info.bt_ctrl_lps) {
++		pBtCoexist->bt_info.bt_lps_on = _FALSE;
++		rtw_btcoex_LPS_Leave(padapter);
++		pBtCoexist->bt_info.bt_ctrl_lps = _FALSE;
++
++		/* recover the LPS state to the original */
++#if 0
++		padapter->hal_func.UpdateLPSStatusHandler(
++			padapter,
++			pPSC->RegLeisurePsMode,
++			pPSC->RegPowerSaveMode);
++#endif
++	}
++}
++
++void halbtcoutsrc_Pre_NormalLps(PBTC_COEXIST pBtCoexist)
++{
++	PADAPTER padapter;
++
++	padapter = pBtCoexist->Adapter;
++
++	if (pBtCoexist->bt_info.bt_ctrl_lps) {
++		pBtCoexist->bt_info.bt_lps_on = _FALSE;
++		rtw_btcoex_LPS_Leave(padapter);
++	}
++}
++
++void halbtcoutsrc_Post_NormalLps(PBTC_COEXIST pBtCoexist)
++{
++	if (pBtCoexist->bt_info.bt_ctrl_lps)
++		pBtCoexist->bt_info.bt_ctrl_lps = _FALSE;
++}
++
++/*
++ *  Constraint:
++ *	   1. this function will request pwrctrl->lock
++ */
++void halbtcoutsrc_LeaveLowPower(PBTC_COEXIST pBtCoexist)
++{
++#ifdef CONFIG_LPS_LCLK
++	PADAPTER padapter;
++	PHAL_DATA_TYPE pHalData;
++	struct pwrctrl_priv *pwrctrl;
++	s32 ready;
++	systime stime;
++	s32 utime;
++	u32 timeout; /* unit: ms */
++
++
++	padapter = pBtCoexist->Adapter;
++	pHalData = GET_HAL_DATA(padapter);
++	pwrctrl = adapter_to_pwrctl(padapter);
++	ready = _FAIL;
++#ifdef LPS_RPWM_WAIT_MS
++	timeout = LPS_RPWM_WAIT_MS;
++#else /* !LPS_RPWM_WAIT_MS */
++	timeout = 30;
++#endif /* !LPS_RPWM_WAIT_MS */
++
++	if (GLBtcBtCoexAliveRegistered == _TRUE)
++		return;
++
++	stime = rtw_get_current_time();
++	do {
++		ready = rtw_register_task_alive(padapter, BTCOEX_ALIVE);
++		if (_SUCCESS == ready)
++			break;
++
++		utime = rtw_get_passing_time_ms(stime);
++		if (utime > timeout)
++			break;
++
++		rtw_msleep_os(1);
++	} while (1);
++
++	GLBtcBtCoexAliveRegistered = _TRUE;
++#endif /* CONFIG_LPS_LCLK */
++}
++
++/*
++ *  Constraint:
++ *	   1. this function will request pwrctrl->lock
++ */
++void halbtcoutsrc_NormalLowPower(PBTC_COEXIST pBtCoexist)
++{
++#ifdef CONFIG_LPS_LCLK
++	PADAPTER padapter;
++
++	if (GLBtcBtCoexAliveRegistered == _FALSE)
++		return;
++
++	padapter = pBtCoexist->Adapter;
++	rtw_unregister_task_alive(padapter, BTCOEX_ALIVE);
++
++	GLBtcBtCoexAliveRegistered = _FALSE;
++#endif /* CONFIG_LPS_LCLK */
++}
++
++void halbtcoutsrc_DisableLowPower(PBTC_COEXIST pBtCoexist, u8 bLowPwrDisable)
++{
++	pBtCoexist->bt_info.bt_disable_low_pwr = bLowPwrDisable;
++	if (bLowPwrDisable)
++		halbtcoutsrc_LeaveLowPower(pBtCoexist);		/* leave 32k low power. */
++	else
++		halbtcoutsrc_NormalLowPower(pBtCoexist);	/* original 32k low power behavior. */
++}
++
++void halbtcoutsrc_AggregationCheck(PBTC_COEXIST pBtCoexist)
++{
++	PADAPTER padapter;
++	BOOLEAN bNeedToAct = _FALSE;
++	static u32 preTime = 0;
++	u32 curTime = 0;
++
++	padapter = pBtCoexist->Adapter;
++
++	/* ===================================== */
++	/* To void continuous deleteBA=>addBA=>deleteBA=>addBA */
++	/* This function is not allowed to continuous called. */
++	/* It can only be called after 8 seconds. */
++	/* ===================================== */
++
++	curTime = rtw_systime_to_ms(rtw_get_current_time());
++	if ((curTime - preTime) < HALBTCOUTSRC_AGG_CHK_WINDOW_IN_MS)	/* over 8 seconds you can execute this function again. */
++		return;
++	else
++		preTime = curTime;
++
++	if (pBtCoexist->bt_info.reject_agg_pkt) {
++		bNeedToAct = _TRUE;
++		pBtCoexist->bt_info.pre_reject_agg_pkt = pBtCoexist->bt_info.reject_agg_pkt;
++	} else {
++		if (pBtCoexist->bt_info.pre_reject_agg_pkt) {
++			bNeedToAct = _TRUE;
++			pBtCoexist->bt_info.pre_reject_agg_pkt = pBtCoexist->bt_info.reject_agg_pkt;
++		}
++
++		if (pBtCoexist->bt_info.pre_bt_ctrl_agg_buf_size !=
++		    pBtCoexist->bt_info.bt_ctrl_agg_buf_size) {
++			bNeedToAct = _TRUE;
++			pBtCoexist->bt_info.pre_bt_ctrl_agg_buf_size = pBtCoexist->bt_info.bt_ctrl_agg_buf_size;
++		}
++
++		if (pBtCoexist->bt_info.bt_ctrl_agg_buf_size) {
++			if (pBtCoexist->bt_info.pre_agg_buf_size !=
++			    pBtCoexist->bt_info.agg_buf_size)
++				bNeedToAct = _TRUE;
++			pBtCoexist->bt_info.pre_agg_buf_size = pBtCoexist->bt_info.agg_buf_size;
++		}
++	}
++
++	if (bNeedToAct)
++		rtw_btcoex_rx_ampdu_apply(padapter);
++}
++
++u8 halbtcoutsrc_is_autoload_fail(PBTC_COEXIST pBtCoexist)
++{
++	PADAPTER padapter;
++	PHAL_DATA_TYPE pHalData;
++
++	padapter = pBtCoexist->Adapter;
++	pHalData = GET_HAL_DATA(padapter);
++
++	return pHalData->bautoload_fail_flag;
++}
++
++u8 halbtcoutsrc_is_fw_ready(PBTC_COEXIST pBtCoexist)
++{
++	PADAPTER padapter;
++
++	padapter = pBtCoexist->Adapter;
++
++	return GET_HAL_DATA(padapter)->bFWReady;
++}
++
++u8 halbtcoutsrc_IsDualBandConnected(PADAPTER padapter)
++{
++	u8 ret = BTC_MULTIPORT_SCC;
++
++#ifdef CONFIG_MCC_MODE
++	if (MCC_EN(padapter) && (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))) {
++		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++		struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
++		u8 band0 = mccobjpriv->iface[0]->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
++		u8 band1 = mccobjpriv->iface[1]->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
++
++		if (band0 != band1)
++			ret = BTC_MULTIPORT_MCC_DUAL_BAND;
++		else
++			ret = BTC_MULTIPORT_MCC_DUAL_CHANNEL;
++	}
++#endif
++
++	return ret;
++}
++
++u8 halbtcoutsrc_IsWifiBusy(PADAPTER padapter)
++{
++	if (rtw_mi_check_status(padapter, MI_AP_ASSOC))
++		return _TRUE;
++	if (rtw_mi_busy_traffic_check(padapter))
++		return _TRUE;
++
++	return _FALSE;
++}
++
++static u32 _halbtcoutsrc_GetWifiLinkStatus(PADAPTER padapter)
++{
++	struct mlme_priv *pmlmepriv;
++	u8 bp2p;
++	u32 portConnectedStatus;
++
++
++	pmlmepriv = &padapter->mlmepriv;
++	bp2p = _FALSE;
++	portConnectedStatus = 0;
++
++#ifdef CONFIG_P2P
++	if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE))
++		bp2p = _TRUE;
++#endif /* CONFIG_P2P */
++
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++		if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
++			if (_TRUE == bp2p)
++				portConnectedStatus |= WIFI_P2P_GO_CONNECTED;
++			else
++				portConnectedStatus |= WIFI_AP_CONNECTED;
++		} else {
++			if (_TRUE == bp2p)
++				portConnectedStatus |= WIFI_P2P_GC_CONNECTED;
++			else
++				portConnectedStatus |= WIFI_STA_CONNECTED;
++		}
++	}
++
++	return portConnectedStatus;
++}
++
++u32 halbtcoutsrc_GetWifiLinkStatus(PBTC_COEXIST pBtCoexist)
++{
++	/* ================================= */
++	/* return value: */
++	/* [31:16]=> connected port number */
++	/* [15:0]=> port connected bit define */
++	/* ================================ */
++
++	PADAPTER padapter;
++	u32 retVal;
++	u32 portConnectedStatus, numOfConnectedPort;
++	struct dvobj_priv *dvobj;
++	_adapter *iface;
++	int i;
++
++	padapter = pBtCoexist->Adapter;
++	retVal = 0;
++	portConnectedStatus = 0;
++	numOfConnectedPort = 0;
++	dvobj = adapter_to_dvobj(padapter);
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if ((iface) && rtw_is_adapter_up(iface)) {
++			retVal = _halbtcoutsrc_GetWifiLinkStatus(iface);
++			if (retVal) {
++				portConnectedStatus |= retVal;
++				numOfConnectedPort++;
++			}
++		}
++	}
++	retVal = (numOfConnectedPort << 16) | portConnectedStatus;
++
++	return retVal;
++}
++
++struct btc_wifi_link_info halbtcoutsrc_getwifilinkinfo(PBTC_COEXIST pBtCoexist)
++{
++	u8 n_assoc_iface = 0, i =0, mcc_en = _FALSE;
++	PADAPTER adapter = NULL;
++	PADAPTER iface = NULL;
++	PADAPTER sta_iface = NULL, p2p_iface = NULL, ap_iface = NULL;
++	BTC_LINK_MODE btc_link_moe = BTC_LINK_MAX;
++	struct dvobj_priv *dvobj = NULL;
++	struct mlme_ext_priv *mlmeext = NULL;
++	struct btc_wifi_link_info wifi_link_info;
++
++	adapter = (PADAPTER)pBtCoexist->Adapter;
++	dvobj = adapter_to_dvobj(adapter);
++	n_assoc_iface = rtw_mi_get_assoc_if_num(adapter);
++
++	/* init value */
++	wifi_link_info.link_mode = BTC_LINK_NONE;
++	wifi_link_info.sta_center_channel = 0;
++	wifi_link_info.p2p_center_channel = 0;
++	wifi_link_info.bany_client_join_go = _FALSE;
++	wifi_link_info.benable_noa = _FALSE;
++	wifi_link_info.bhotspot = _FALSE;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (!iface)
++			continue;
++		
++		mlmeext = &iface->mlmeextpriv;
++		if (MLME_IS_GO(iface)) {
++			wifi_link_info.link_mode = BTC_LINK_ONLY_GO;
++			wifi_link_info.p2p_center_channel =
++				rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
++			p2p_iface	 = iface;
++			if (rtw_linked_check(iface))
++				wifi_link_info.bany_client_join_go = _TRUE;
++		} else if (MLME_IS_GC(iface)) {
++			wifi_link_info.link_mode = BTC_LINK_ONLY_GC;
++			wifi_link_info.p2p_center_channel =
++				rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
++			p2p_iface = iface;
++		} else if (MLME_IS_AP(iface)) {
++			wifi_link_info.link_mode = BTC_LINK_ONLY_AP;
++			ap_iface = iface;
++			wifi_link_info.p2p_center_channel =
++				rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
++		} else if (MLME_IS_STA(iface) && rtw_linked_check(iface)) {
++			wifi_link_info.link_mode = BTC_LINK_ONLY_STA;
++			wifi_link_info.sta_center_channel =
++				rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
++			sta_iface = iface;
++		}
++	}
++
++#ifdef CONFIG_MCC_MODE
++	if (MCC_EN(adapter)) {
++		if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
++			mcc_en = _TRUE;
++	}
++#endif/* CONFIG_MCC_MODE */
++
++	if (n_assoc_iface == 0) {
++		wifi_link_info.link_mode = BTC_LINK_NONE;
++	} else if (n_assoc_iface == 1) {
++		/* by pass */
++	} else if (n_assoc_iface == 2) {	
++		if (sta_iface && p2p_iface) {
++			u8 band_sta = sta_iface->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
++			u8 band_p2p = p2p_iface->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
++			if (band_sta == band_p2p) {
++				switch (band_sta) {
++				case BAND_ON_2_4G:
++					if (MLME_IS_GO(p2p_iface)) {
++						#ifdef CONFIG_MCC_MODE
++						wifi_link_info.link_mode =
++							mcc_en == _TRUE ?  BTC_LINK_2G_MCC_GO_STA : BTC_LINK_2G_SCC_GO_STA;
++						#else /* !CONFIG_MCC_MODE */
++							wifi_link_info.link_mode = BTC_LINK_2G_SCC_GO_STA;
++						#endif /* CONFIG_MCC_MODE */
++					} else if (MLME_IS_GC(p2p_iface)) {
++						#ifdef CONFIG_MCC_MODE
++						wifi_link_info.link_mode =
++							mcc_en == _TRUE ?  BTC_LINK_2G_MCC_GC_STA : BTC_LINK_2G_SCC_GC_STA;
++						#else /* !CONFIG_MCC_MODE */
++							wifi_link_info.link_mode = BTC_LINK_2G_SCC_GC_STA;
++						#endif /* CONFIG_MCC_MODE */
++					}
++					break;
++				case BAND_ON_5G:
++					if (MLME_IS_GO(p2p_iface)) {
++						#ifdef CONFIG_MCC_MODE
++						wifi_link_info.link_mode =
++							mcc_en == _TRUE ?  BTC_LINK_5G_MCC_GO_STA : BTC_LINK_5G_SCC_GO_STA;
++						#else /* !CONFIG_MCC_MODE */
++							wifi_link_info.link_mode = BTC_LINK_5G_SCC_GO_STA;
++						#endif /* CONFIG_MCC_MODE */
++					} else if (MLME_IS_GC(p2p_iface)) {
++						#ifdef CONFIG_MCC_MODE
++						wifi_link_info.link_mode =
++							mcc_en == _TRUE ?  BTC_LINK_5G_MCC_GC_STA : BTC_LINK_5G_SCC_GC_STA;
++						#else /* !CONFIG_MCC_MODE */
++							wifi_link_info.link_mode = BTC_LINK_5G_SCC_GC_STA;
++						#endif /* CONFIG_MCC_MODE */
++					}
++					break;
++				}
++			} else {
++				if (MLME_IS_GO(p2p_iface))
++					wifi_link_info.link_mode = BTC_LINK_25G_MCC_GO_STA;
++				else if (MLME_IS_GC(p2p_iface))
++					wifi_link_info.link_mode = BTC_LINK_25G_MCC_GC_STA;
++			}
++		}
++	} else {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			RTW_ERR("%s do not support n_assoc_iface > 2 (ant_num == 1)", __func__);
++	}
++
++	return wifi_link_info;
++}
++
++
++static void _btmpoper_timer_hdl(void *p)
++{
++	if (GLBtcBtMpRptWait == _TRUE) {
++		GLBtcBtMpRptWait = _FALSE;
++		_rtw_up_sema(&GLBtcBtMpRptSema);
++	}
++}
++
++/*
++ * !IMPORTANT!
++ *	Before call this function, caller should acquire "GLBtcBtMpOperLock"!
++ *	Othrewise there will be racing problem and something may go wrong.
++ */
++static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cmd, u8 size)
++{
++	PADAPTER padapter;
++	u8 buf[H2C_BTMP_OPER_LEN] = {0};
++	u8 buflen;
++	u8 seq;
++	s32 ret;
++
++
++	if (!cmd && size)
++		size = 0;
++	if ((size + 2) > H2C_BTMP_OPER_LEN)
++		return BT_STATUS_H2C_LENGTH_EXCEEDED;
++	buflen = size + 2;
++
++	seq = GLBtcBtMpOperSeq & 0xF;
++	GLBtcBtMpOperSeq++;
++
++	buf[0] = (opcodever & 0xF) | (seq << 4);
++	buf[1] = opcode;
++	if (cmd && size)
++		_rtw_memcpy(buf + 2, cmd, size);
++
++	GLBtcBtMpRptWait = _TRUE;
++	GLBtcBtMpRptWiFiOK = _FALSE;
++	GLBtcBtMpRptBTOK = _FALSE;
++	GLBtcBtMpRptStatus = 0;
++	padapter = pBtCoexist->Adapter;
++	_set_timer(&GLBtcBtMpOperTimer, BTC_MPOPER_TIMEOUT);
++	if (rtw_hal_fill_h2c_cmd(padapter, H2C_BT_MP_OPER, buflen, buf) == _FAIL) {
++		_cancel_timer_ex(&GLBtcBtMpOperTimer);
++		ret = BT_STATUS_H2C_FAIL;
++		goto exit;
++	}
++
++	_rtw_down_sema(&GLBtcBtMpRptSema);
++	/* GLBtcBtMpRptWait should be _FALSE here*/
++
++	if (GLBtcBtMpRptWiFiOK == _FALSE) {
++		RTW_DBG("%s: Didn't get H2C Rsp Event!\n", __FUNCTION__);
++		ret = BT_STATUS_H2C_TIMTOUT;
++		goto exit;
++	}
++	if (GLBtcBtMpRptBTOK == _FALSE) {
++		RTW_DBG("%s: Didn't get BT response!\n", __FUNCTION__);
++		ret = BT_STATUS_H2C_BT_NO_RSP;
++		goto exit;
++	}
++
++	if (seq != GLBtcBtMpRptSeq) {
++		RTW_ERR("%s: Sequence number not match!(%d!=%d)!\n",
++			 __FUNCTION__, seq, GLBtcBtMpRptSeq);
++		ret = BT_STATUS_C2H_REQNUM_MISMATCH;
++		goto exit;
++	}
++
++	switch (GLBtcBtMpRptStatus) {
++	/* Examine the status reported from C2H */
++	case BT_STATUS_OK:
++		ret = BT_STATUS_BT_OP_SUCCESS;
++		RTW_DBG("%s: C2H status = BT_STATUS_BT_OP_SUCCESS\n", __FUNCTION__);
++		break;
++	case BT_STATUS_VERSION_MISMATCH:
++		ret = BT_STATUS_OPCODE_L_VERSION_MISMATCH;
++		RTW_DBG("%s: C2H status = BT_STATUS_OPCODE_L_VERSION_MISMATCH\n", __FUNCTION__);
++		break;
++	case BT_STATUS_UNKNOWN_OPCODE:
++		ret = BT_STATUS_UNKNOWN_OPCODE_L;
++		RTW_DBG("%s: C2H status = MP_BT_STATUS_UNKNOWN_OPCODE_L\n", __FUNCTION__);
++		break;
++	case BT_STATUS_ERROR_PARAMETER:
++		ret = BT_STATUS_PARAMETER_FORMAT_ERROR_L;
++		RTW_DBG("%s: C2H status = MP_BT_STATUS_PARAMETER_FORMAT_ERROR_L\n", __FUNCTION__);
++		break;
++	default:
++		ret = BT_STATUS_UNKNOWN_STATUS_L;
++		RTW_DBG("%s: C2H status = MP_BT_STATUS_UNKNOWN_STATUS_L\n", __FUNCTION__);
++		break;
++	}
++
++exit:
++	return ret;
++}
++
++u32 halbtcoutsrc_GetBtPatchVer(PBTC_COEXIST pBtCoexist)
++{
++	if (pBtCoexist->bt_info.get_bt_fw_ver_cnt <= 5) {
++		if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
++			_irqL irqL;
++			u8 ret;
++
++			_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++			ret = _btmpoper_cmd(pBtCoexist, BT_OP_GET_BT_VERSION, 0, NULL, 0);
++			if (BT_STATUS_BT_OP_SUCCESS == ret) {
++				pBtCoexist->bt_info.bt_real_fw_ver = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
++				pBtCoexist->bt_info.get_bt_fw_ver_cnt++;
++			}
++
++			_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++		} else {
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++			u8 dataLen = 2;
++			u8 buf[4] = {0};
++
++			buf[0] = 0x0;	/* OP_Code */
++			buf[1] = 0x0;	/* OP_Code_Length */
++			BT_SendEventExtBtCoexControl(pBtCoexist->Adapter, _FALSE, dataLen, &buf[0]);
++#endif /* !CONFIG_BT_COEXIST_SOCKET_TRX */
++		}
++	}
++
++	return pBtCoexist->bt_info.bt_real_fw_ver;
++}
++
++s32 halbtcoutsrc_GetWifiRssi(PADAPTER padapter)
++{
++	return rtw_dm_get_min_rssi(padapter);
++}
++
++u32 halbtcoutsrc_GetBtCoexSupportedFeature(void *pBtcContext)
++{
++	PBTC_COEXIST pBtCoexist;
++	u32 ret = BT_STATUS_BT_OP_SUCCESS;
++	u32 data = 0;
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++
++	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
++		u8 buf[3] = {0};
++		_irqL irqL;
++		u8 op_code;
++		u8 status;
++
++		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++		op_code = BT_OP_GET_BT_COEX_SUPPORTED_FEATURE;
++		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
++		if (status == BT_STATUS_BT_OP_SUCCESS)
++			data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
++		else
++			ret = SET_BT_MP_OPER_RET(op_code, status);
++
++		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++	} else
++		ret = BT_STATUS_NOT_IMPLEMENT;
++
++	return data;
++}
++
++u32 halbtcoutsrc_GetBtCoexSupportedVersion(void *pBtcContext)
++{
++	PBTC_COEXIST pBtCoexist;
++	u32 ret = BT_STATUS_BT_OP_SUCCESS;
++	u32 data = 0xFFFF;
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++
++	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
++		u8 buf[3] = {0};
++		_irqL irqL;
++		u8 op_code;
++		u8 status;
++
++		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++		op_code = BT_OP_GET_BT_COEX_SUPPORTED_VERSION;
++		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
++		if (status == BT_STATUS_BT_OP_SUCCESS)
++			data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
++		else
++			ret = SET_BT_MP_OPER_RET(op_code, status);
++
++		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++	} else
++		ret = BT_STATUS_NOT_IMPLEMENT;
++
++	return data;
++}
++
++u32 halbtcoutsrc_GetBtDeviceInfo(void *pBtcContext)
++{
++	PBTC_COEXIST pBtCoexist;
++	u32 ret = BT_STATUS_BT_OP_SUCCESS;
++	u32 btDeviceInfo = 0;
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++
++	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
++		u8 buf[3] = {0};
++		_irqL irqL;
++		u8 op_code;
++		u8 status;
++
++		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++		op_code = BT_OP_GET_BT_DEVICE_INFO;
++		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
++		if (status == BT_STATUS_BT_OP_SUCCESS)
++			btDeviceInfo = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
++		else
++			ret = SET_BT_MP_OPER_RET(op_code, status);
++
++		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++	} else
++		ret = BT_STATUS_NOT_IMPLEMENT;
++
++	return btDeviceInfo;
++}
++
++u32 halbtcoutsrc_GetBtForbiddenSlotVal(void *pBtcContext)
++{
++	PBTC_COEXIST pBtCoexist;
++	u32 ret = BT_STATUS_BT_OP_SUCCESS;
++	u32 btForbiddenSlotVal = 0;
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++
++	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
++		u8 buf[3] = {0};
++		_irqL irqL;
++		u8 op_code;
++		u8 status;
++
++		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++		op_code = BT_OP_GET_BT_FORBIDDEN_SLOT_VAL;
++		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
++		if (status == BT_STATUS_BT_OP_SUCCESS)
++			btForbiddenSlotVal = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
++		else
++			ret = SET_BT_MP_OPER_RET(op_code, status);
++
++		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++	} else
++		ret = BT_STATUS_NOT_IMPLEMENT;
++
++	return btForbiddenSlotVal;
++}
++
++static u8 halbtcoutsrc_GetWifiScanAPNum(PADAPTER padapter)
++{
++	struct mlme_priv *pmlmepriv;
++	struct mlme_ext_priv *pmlmeext;
++	static u8 scan_AP_num = 0;
++
++
++	pmlmepriv = &padapter->mlmepriv;
++	pmlmeext = &padapter->mlmeextpriv;
++
++	if (GLBtcWiFiInScanState == _FALSE) {
++		if (pmlmepriv->num_of_scanned > 0xFF)
++			scan_AP_num = 0xFF;
++		else
++			scan_AP_num = (u8)pmlmepriv->num_of_scanned;
++	}
++
++	return scan_AP_num;
++}
++
++u32 halbtcoutsrc_GetPhydmVersion(void *pBtcContext)
++{
++	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
++	PADAPTER		Adapter = pBtCoexist->Adapter;
++
++#ifdef CONFIG_RTL8192E
++	return RELEASE_VERSION_8192E;
++#endif
++
++#ifdef CONFIG_RTL8821A
++	return RELEASE_VERSION_8821A;
++#endif
++
++#ifdef CONFIG_RTL8723B
++	return RELEASE_VERSION_8723B;
++#endif
++
++#ifdef CONFIG_RTL8812A
++	return RELEASE_VERSION_8812A;
++#endif
++
++#ifdef CONFIG_RTL8703B
++	return RELEASE_VERSION_8703B;
++#endif
++
++#ifdef CONFIG_RTL8822B
++	return RELEASE_VERSION_8822B;
++#endif
++
++#ifdef CONFIG_RTL8723D
++	return RELEASE_VERSION_8723D;
++#endif
++
++#ifdef CONFIG_RTL8821C
++	return RELEASE_VERSION_8821C;
++#endif
++
++#ifdef CONFIG_RTL8192F
++	return RELEASE_VERSION_8192F;
++#endif
++
++#ifdef CONFIG_RTL8822C
++	return RELEASE_VERSION_8822C;
++#endif
++
++#ifdef CONFIG_RTL8814A
++	return RELEASE_VERSION_8814A;
++#endif
++
++#ifdef CONFIG_RTL8814B
++	return RELEASE_VERSION_8814B;
++#endif
++}
++
++u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
++{
++	PBTC_COEXIST pBtCoexist;
++	PADAPTER padapter;
++	PHAL_DATA_TYPE pHalData;
++	struct mlme_ext_priv *mlmeext;
++	struct btc_wifi_link_info *wifi_link_info;
++	u8 bSoftApExist, bVwifiExist;
++	u8 *pu8;
++	s32 *pS4Tmp;
++	u32 *pU4Tmp;
++	u8 *pU1Tmp;
++	u16 *pU2Tmp;
++	u8 ret;
++
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return _FALSE;
++
++	padapter = pBtCoexist->Adapter;
++	pHalData = GET_HAL_DATA(padapter);
++	mlmeext = &padapter->mlmeextpriv;
++	bSoftApExist = _FALSE;
++	bVwifiExist = _FALSE;
++	pu8 = (u8 *)pOutBuf;
++	pS4Tmp = (s32 *)pOutBuf;
++	pU4Tmp = (u32 *)pOutBuf;
++	pU1Tmp = (u8 *)pOutBuf;
++	pU2Tmp = (u16*)pOutBuf;
++	wifi_link_info = (struct btc_wifi_link_info *)pOutBuf;
++	ret = _TRUE;
++
++	switch (getType) {
++	case BTC_GET_BL_HS_OPERATION:
++		*pu8 = _FALSE;
++		ret = _FALSE;
++		break;
++
++	case BTC_GET_BL_HS_CONNECTING:
++		*pu8 = _FALSE;
++		ret = _FALSE;
++		break;
++
++	case BTC_GET_BL_WIFI_FW_READY:
++		*pu8 = halbtcoutsrc_is_fw_ready(pBtCoexist);
++		break;
++
++	case BTC_GET_BL_WIFI_CONNECTED:
++		*pu8 = (rtw_mi_check_status(padapter, MI_LINKED)) ? _TRUE : _FALSE;
++		break;
++
++	case BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED:
++		*pu8 = halbtcoutsrc_IsDualBandConnected(padapter);
++		break;
++
++	case BTC_GET_BL_WIFI_BUSY:
++		*pu8 = halbtcoutsrc_IsWifiBusy(padapter);
++		break;
++
++	case BTC_GET_BL_WIFI_SCAN:
++#if 0
++		*pu8 = (rtw_mi_check_fwstate(padapter, WIFI_UNDER_SURVEY)) ? _TRUE : _FALSE;
++#else
++		/* Use the value of the new variable GLBtcWiFiInScanState to judge whether WiFi is in scan state or not, since the originally used flag
++			WIFI_UNDER_SURVEY in fwstate may not be cleared in time */
++		*pu8 = GLBtcWiFiInScanState;
++#endif
++		break;
++
++	case BTC_GET_BL_WIFI_LINK:
++		*pu8 = (rtw_mi_check_status(padapter, MI_STA_LINKING)) ? _TRUE : _FALSE;
++		break;
++
++	case BTC_GET_BL_WIFI_ROAM:
++		*pu8 = (rtw_mi_check_status(padapter, MI_STA_LINKING)) ? _TRUE : _FALSE;
++		break;
++
++	case BTC_GET_BL_WIFI_4_WAY_PROGRESS:
++		*pu8 = _FALSE;
++		break;
++
++	case BTC_GET_BL_WIFI_UNDER_5G:
++		*pu8 = (pHalData->current_band_type == BAND_ON_5G) ? _TRUE : _FALSE;
++		break;
++
++	case BTC_GET_BL_WIFI_AP_MODE_ENABLE:
++		*pu8 = (rtw_mi_check_status(padapter, MI_AP_MODE)) ? _TRUE : _FALSE;
++		break;
++
++	case BTC_GET_BL_WIFI_ENABLE_ENCRYPTION:
++		*pu8 = padapter->securitypriv.dot11PrivacyAlgrthm == 0 ? _FALSE : _TRUE;
++		break;
++
++	case BTC_GET_BL_WIFI_UNDER_B_MODE:
++		if (mlmeext->cur_wireless_mode == WIRELESS_11B)
++			*pu8 = _TRUE;
++		else
++			*pu8 = _FALSE;
++		break;
++
++	case BTC_GET_BL_WIFI_IS_IN_MP_MODE:
++		if (padapter->registrypriv.mp_mode == 0)
++			*pu8 = _FALSE;
++		else
++			*pu8 = _TRUE;
++		break;
++
++	case BTC_GET_BL_EXT_SWITCH:
++		*pu8 = _FALSE;
++		break;
++	case BTC_GET_BL_IS_ASUS_8723B:
++		/* Always return FALSE in linux driver since this case is added only for windows driver */
++		*pu8 = _FALSE;
++		break;
++
++	case BTC_GET_BL_RF4CE_CONNECTED:
++#ifdef CONFIG_RF4CE_COEXIST
++		if (hal_btcoex_get_rf4ce_link_state() == 0)
++			*pu8 = FALSE;
++		else
++			*pu8 = TRUE;
++#else
++		*pu8 = FALSE;
++#endif
++		break;
++
++	case BTC_GET_BL_WIFI_LW_PWR_STATE:
++		/* return false due to coex do not run during 32K */
++		*pu8 = FALSE;
++		break;
++
++	case BTC_GET_S4_WIFI_RSSI:
++		*pS4Tmp = halbtcoutsrc_GetWifiRssi(padapter);
++		break;
++
++	case BTC_GET_S4_HS_RSSI:
++		*pS4Tmp = 0;
++		ret = _FALSE;
++		break;
++
++	case BTC_GET_U4_WIFI_BW:
++		if (IsLegacyOnly(mlmeext->cur_wireless_mode))
++			*pU4Tmp = BTC_WIFI_BW_LEGACY;
++		else {
++			switch (pHalData->current_channel_bw) {
++			case CHANNEL_WIDTH_20:
++				*pU4Tmp = BTC_WIFI_BW_HT20;
++				break;
++			case CHANNEL_WIDTH_40:
++				*pU4Tmp = BTC_WIFI_BW_HT40;
++				break;
++			case CHANNEL_WIDTH_80:
++				*pU4Tmp = BTC_WIFI_BW_HT80;
++				break;
++			case CHANNEL_WIDTH_160:
++				*pU4Tmp = BTC_WIFI_BW_HT160;
++				break;
++			default:
++				RTW_INFO("[BTCOEX] unknown bandwidth(%d)\n", pHalData->current_channel_bw);
++				*pU4Tmp = BTC_WIFI_BW_HT40;
++				break;
++			}
++
++		}
++		break;
++
++	case BTC_GET_U4_WIFI_TRAFFIC_DIRECTION: 
++	case BTC_GET_U4_WIFI_TRAFFIC_DIR:
++		{
++			PRT_LINK_DETECT_T plinkinfo;
++			plinkinfo = &padapter->mlmepriv.LinkDetectInfo;
++
++			if (plinkinfo->NumTxOkInPeriod > plinkinfo->NumRxOkInPeriod)
++				*pU4Tmp = BTC_WIFI_TRAFFIC_TX;
++			else
++				*pU4Tmp = BTC_WIFI_TRAFFIC_RX;
++		}
++		break;
++
++	case BTC_GET_U4_WIFI_FW_VER:
++		*pU4Tmp = pHalData->firmware_version << 16;
++		*pU4Tmp |= pHalData->firmware_sub_version;
++		break;
++
++	case BTC_GET_U4_WIFI_PHY_VER:
++		*pU4Tmp = halbtcoutsrc_GetPhydmVersion(pBtCoexist);
++		break;
++
++	case BTC_GET_U4_WIFI_LINK_STATUS:
++		*pU4Tmp = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist);
++		break;
++	case BTC_GET_BL_WIFI_LINK_INFO:
++		*wifi_link_info = halbtcoutsrc_getwifilinkinfo(pBtCoexist);
++		break;
++	case BTC_GET_U4_BT_PATCH_VER:
++		*pU4Tmp = halbtcoutsrc_GetBtPatchVer(pBtCoexist);
++		break;
++
++	case BTC_GET_U4_VENDOR:
++		*pU4Tmp = BTC_VENDOR_OTHER;
++		break;
++
++	case BTC_GET_U4_SUPPORTED_VERSION:
++		*pU4Tmp = halbtcoutsrc_GetBtCoexSupportedVersion(pBtCoexist);
++		break;
++	case BTC_GET_U4_SUPPORTED_FEATURE:
++		*pU4Tmp = halbtcoutsrc_GetBtCoexSupportedFeature(pBtCoexist);
++		break;
++
++	case BTC_GET_U4_BT_DEVICE_INFO:
++		*pU4Tmp = halbtcoutsrc_GetBtDeviceInfo(pBtCoexist);
++		break;
++
++	case BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL:
++	case BTC_GET_U4_BT_A2DP_FLUSH_VAL:
++		*pU4Tmp = halbtcoutsrc_GetBtForbiddenSlotVal(pBtCoexist);
++		break;
++
++	case BTC_GET_U4_WIFI_IQK_TOTAL:
++		*pU4Tmp = pHalData->odmpriv.n_iqk_cnt;
++		break;
++
++	case BTC_GET_U4_WIFI_IQK_OK:
++		*pU4Tmp = pHalData->odmpriv.n_iqk_ok_cnt;
++		break;
++
++	case BTC_GET_U4_WIFI_IQK_FAIL:
++		*pU4Tmp = pHalData->odmpriv.n_iqk_fail_cnt;
++		break;
++
++	case BTC_GET_U1_WIFI_DOT11_CHNL:
++		*pU1Tmp = padapter->mlmeextpriv.cur_channel;
++		break;
++
++	case BTC_GET_U1_WIFI_CENTRAL_CHNL:
++		*pU1Tmp = pHalData->current_channel;
++		break;
++
++	case BTC_GET_U1_WIFI_HS_CHNL:
++		*pU1Tmp = 0;
++		ret = _FALSE;
++		break;
++
++	case BTC_GET_U1_WIFI_P2P_CHNL:
++#ifdef CONFIG_P2P
++		{
++			struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++			
++			*pU1Tmp = pwdinfo->operating_channel;
++		}
++#else
++		*pU1Tmp = 0;
++#endif
++		break;
++
++	case BTC_GET_U1_MAC_PHY_MODE:
++		/*			*pU1Tmp = BTC_SMSP;
++		 *			*pU1Tmp = BTC_DMSP;
++		 *			*pU1Tmp = BTC_DMDP;
++		 *			*pU1Tmp = BTC_MP_UNKNOWN; */
++		break;
++
++	case BTC_GET_U1_AP_NUM:
++		*pU1Tmp = halbtcoutsrc_GetWifiScanAPNum(padapter);
++		break;
++	case BTC_GET_U1_ANT_TYPE:
++		switch (pHalData->bt_coexist.btAntisolation) {
++		case 0:
++			*pU1Tmp = (u8)BTC_ANT_TYPE_0;
++			pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_0;
++			break;
++		case 1:
++			*pU1Tmp = (u8)BTC_ANT_TYPE_1;
++			pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_1;
++			break;
++		case 2:
++			*pU1Tmp = (u8)BTC_ANT_TYPE_2;
++			pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_2;
++			break;
++		case 3:
++			*pU1Tmp = (u8)BTC_ANT_TYPE_3;
++			pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_3;
++			break;
++		case 4:
++			*pU1Tmp = (u8)BTC_ANT_TYPE_4;
++			pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_4;
++			break;
++		}
++		break;
++	case BTC_GET_U1_IOT_PEER:
++		*pU1Tmp = mlmeext->mlmext_info.assoc_AP_vendor;
++		break;
++
++	/* =======1Ant=========== */
++	case BTC_GET_U1_LPS_MODE:
++		*pU1Tmp = padapter->dvobj->pwrctl_priv.pwr_mode;
++		break;
++
++	case BTC_GET_U2_BEACON_PERIOD:
++		*pU2Tmp = mlmeext->mlmext_info.bcn_interval;
++		break;
++
++	default:
++		ret = _FALSE;
++		break;
++	}
++
++	return ret;
++}
++
++u16 halbtcoutsrc_LnaConstrainLvl(void *pBtcContext, u8 *lna_constrain_level)
++{
++	PBTC_COEXIST pBtCoexist;
++	u16 ret = BT_STATUS_BT_OP_SUCCESS;
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++
++	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
++		_irqL irqL;
++		u8 op_code;
++
++		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++		ret = _btmpoper_cmd(pBtCoexist, BT_OP_SET_BT_LANCONSTRAIN_LEVEL, 0, lna_constrain_level, 1);
++
++		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++	} else { 
++		ret = BT_STATUS_NOT_IMPLEMENT;
++		RTW_INFO("%s halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == FALSE\n", __func__);
++	}
++
++	return ret;
++}
++
++u8 halbtcoutsrc_SetBtGoldenRxRange(void *pBtcContext, u8 profile, u8 range_shift)
++{
++	/* wait for implementation if necessary */
++
++	return 0;
++}
++
++u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf)
++{
++	PBTC_COEXIST pBtCoexist;
++	PADAPTER padapter;
++	PHAL_DATA_TYPE pHalData;
++	u8 *pu8;
++	u8 *pU1Tmp;
++	u16 *pU2Tmp;
++	u32	*pU4Tmp;
++	u8 ret;
++	u8 result = _TRUE;
++
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return _FALSE;
++
++	padapter = pBtCoexist->Adapter;
++	pHalData = GET_HAL_DATA(padapter);
++	pu8 = (u8 *)pInBuf;
++	pU1Tmp = (u8 *)pInBuf;
++	pU2Tmp = (u16*)pInBuf;
++	pU4Tmp = (u32 *)pInBuf;
++	ret = _TRUE;
++
++	switch (setType) {
++	/* set some u8 type variables. */
++	case BTC_SET_BL_BT_DISABLE:
++		pBtCoexist->bt_info.bt_disabled = *pu8;
++		break;
++
++	case BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE:
++		pBtCoexist->bt_info.bt_enable_disable_change = *pu8;
++		break;
++
++	case BTC_SET_BL_BT_TRAFFIC_BUSY:
++		pBtCoexist->bt_info.bt_busy = *pu8;
++		break;
++
++	case BTC_SET_BL_BT_LIMITED_DIG:
++		pBtCoexist->bt_info.limited_dig = *pu8;
++		break;
++
++	case BTC_SET_BL_FORCE_TO_ROAM:
++		pBtCoexist->bt_info.force_to_roam = *pu8;
++		break;
++
++	case BTC_SET_BL_TO_REJ_AP_AGG_PKT:
++		pBtCoexist->bt_info.reject_agg_pkt = *pu8;
++		break;
++
++	case BTC_SET_BL_BT_CTRL_AGG_SIZE:
++		pBtCoexist->bt_info.bt_ctrl_agg_buf_size = *pu8;
++		break;
++
++	case BTC_SET_BL_INC_SCAN_DEV_NUM:
++		pBtCoexist->bt_info.increase_scan_dev_num = *pu8;
++		break;
++
++	case BTC_SET_BL_BT_TX_RX_MASK:
++		pBtCoexist->bt_info.bt_tx_rx_mask = *pu8;
++		break;
++
++	case BTC_SET_BL_MIRACAST_PLUS_BT:
++		pBtCoexist->bt_info.miracast_plus_bt = *pu8;
++		break;
++
++	/* set some u8 type variables. */
++	case BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON:
++		pBtCoexist->bt_info.rssi_adjust_for_agc_table_on = *pU1Tmp;
++		break;
++
++	case BTC_SET_U1_AGG_BUF_SIZE:
++		pBtCoexist->bt_info.agg_buf_size = *pU1Tmp;
++		break;
++
++	/* the following are some action which will be triggered */
++	case BTC_SET_ACT_GET_BT_RSSI:
++#if 0
++		BT_SendGetBtRssiEvent(padapter);
++#else
++		ret = _FALSE;
++#endif
++		break;
++
++	case BTC_SET_ACT_AGGREGATE_CTRL:
++		halbtcoutsrc_AggregationCheck(pBtCoexist);
++		break;
++
++	/* =======1Ant=========== */
++	/* set some u8 type variables. */
++	case BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE:
++		pBtCoexist->bt_info.rssi_adjust_for_1ant_coex_type = *pU1Tmp;
++		break;
++
++	case BTC_SET_U1_LPS_VAL:
++		pBtCoexist->bt_info.lps_val = *pU1Tmp;
++		break;
++
++	case BTC_SET_U1_RPWM_VAL:
++		pBtCoexist->bt_info.rpwm_val = *pU1Tmp;
++		break;
++
++	/* the following are some action which will be triggered */
++	case BTC_SET_ACT_LEAVE_LPS:
++		result = halbtcoutsrc_LeaveLps(pBtCoexist);
++		break;
++
++	case BTC_SET_ACT_ENTER_LPS:
++		halbtcoutsrc_EnterLps(pBtCoexist);
++		break;
++
++	case BTC_SET_ACT_NORMAL_LPS:
++		halbtcoutsrc_NormalLps(pBtCoexist);
++		break;
++
++	case BTC_SET_ACT_PRE_NORMAL_LPS:
++		halbtcoutsrc_Pre_NormalLps(pBtCoexist);
++		break;
++
++	case BTC_SET_ACT_POST_NORMAL_LPS:
++		halbtcoutsrc_Post_NormalLps(pBtCoexist);
++		break;
++
++	case BTC_SET_ACT_DISABLE_LOW_POWER:
++		halbtcoutsrc_DisableLowPower(pBtCoexist, *pu8);
++		break;
++
++	case BTC_SET_ACT_UPDATE_RAMASK:
++		/*
++		pBtCoexist->bt_info.ra_mask = *pU4Tmp;
++
++		if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++			struct sta_info *psta;
++			PWLAN_BSSID_EX cur_network;
++
++			cur_network = &padapter->mlmeextpriv.mlmext_info.network;
++			psta = rtw_get_stainfo(&padapter->stapriv, cur_network->MacAddress);
++			rtw_hal_update_ra_mask(psta);
++		}
++		*/
++		break;
++
++	case BTC_SET_ACT_SEND_MIMO_PS: {
++		u8 newMimoPsMode = 3;
++		struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++		struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++		/* *pU1Tmp = 0 use SM_PS static type */
++		/* *pU1Tmp = 1 disable SM_PS */
++		if (*pU1Tmp == 0)
++			newMimoPsMode = WLAN_HT_CAP_SM_PS_STATIC;
++		else if (*pU1Tmp == 1)
++			newMimoPsMode = WLAN_HT_CAP_SM_PS_DISABLED;
++
++		if (check_fwstate(&padapter->mlmepriv , WIFI_ASOC_STATE) == _TRUE) {
++			/* issue_action_SM_PS(padapter, get_my_bssid(&(pmlmeinfo->network)), newMimoPsMode); */
++			issue_action_SM_PS_wait_ack(padapter , get_my_bssid(&(pmlmeinfo->network)) , newMimoPsMode, 3 , 1);
++		}
++	}
++	break;
++
++	case BTC_SET_ACT_CTRL_BT_INFO:
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++		{
++			u8 dataLen = *pU1Tmp;
++			u8 tmpBuf[BTC_TMP_BUF_SHORT];
++			if (dataLen)
++				_rtw_memcpy(tmpBuf, pU1Tmp + 1, dataLen);
++			BT_SendEventExtBtInfoControl(padapter, dataLen, &tmpBuf[0]);
++		}
++#else /* !CONFIG_BT_COEXIST_SOCKET_TRX */
++		ret = _FALSE;
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++		break;
++
++	case BTC_SET_ACT_CTRL_BT_COEX:
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++		{
++			u8 dataLen = *pU1Tmp;
++			u8 tmpBuf[BTC_TMP_BUF_SHORT];
++			if (dataLen)
++				_rtw_memcpy(tmpBuf, pU1Tmp + 1, dataLen);
++			BT_SendEventExtBtCoexControl(padapter, _FALSE, dataLen, &tmpBuf[0]);
++		}
++#else /* !CONFIG_BT_COEXIST_SOCKET_TRX */
++		ret = _FALSE;
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++		break;
++	case BTC_SET_ACT_CTRL_8723B_ANT:
++#if 0
++		{
++			u8	dataLen = *pU1Tmp;
++			u8	tmpBuf[BTC_TMP_BUF_SHORT];
++			if (dataLen)
++				PlatformMoveMemory(&tmpBuf[0], pU1Tmp + 1, dataLen);
++			BT_Set8723bAnt(Adapter, dataLen, &tmpBuf[0]);
++		}
++#else
++		ret = _FALSE;
++#endif
++		break;
++	case BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL:
++		halbtcoutsrc_LnaConstrainLvl(pBtCoexist, pu8);
++		break;
++	case BTC_SET_BL_BT_GOLDEN_RX_RANGE:
++		halbtcoutsrc_SetBtGoldenRxRange(pBtCoexist, (*pU2Tmp & 0xff00) >> 8, (*pU2Tmp & 0xff));
++		break;
++	case BTC_SET_RESET_COEX_VAR:
++		_rtw_memset(&pBtCoexist->coex_dm, 0x00, sizeof(pBtCoexist->coex_dm));
++		_rtw_memset(&pBtCoexist->coex_sta, 0x00, sizeof(pBtCoexist->coex_sta));
++
++		switch(pBtCoexist->chip_type) {
++#ifdef CONFIG_RTL8822B
++		case BTC_CHIP_RTL8822B:
++			_rtw_memset(&pBtCoexist->coex_dm_8822b_1ant, 0x00, sizeof(pBtCoexist->coex_dm_8822b_1ant));
++			_rtw_memset(&pBtCoexist->coex_dm_8822b_2ant, 0x00, sizeof(pBtCoexist->coex_dm_8822b_2ant));
++			_rtw_memset(&pBtCoexist->coex_sta_8822b_1ant, 0x00, sizeof(pBtCoexist->coex_sta_8822b_1ant));
++			_rtw_memset(&pBtCoexist->coex_sta_8822b_2ant, 0x00, sizeof(pBtCoexist->coex_sta_8822b_2ant));
++			break;
++#endif
++#ifdef CONFIG_RTL8821C
++		case BTC_CHIP_RTL8821C:
++			_rtw_memset(&pBtCoexist->coex_dm_8821c_1ant, 0x00, sizeof(pBtCoexist->coex_dm_8821c_1ant));
++			_rtw_memset(&pBtCoexist->coex_dm_8821c_2ant, 0x00, sizeof(pBtCoexist->coex_dm_8821c_2ant));
++			_rtw_memset(&pBtCoexist->coex_sta_8821c_1ant, 0x00, sizeof(pBtCoexist->coex_sta_8821c_1ant));
++			_rtw_memset(&pBtCoexist->coex_sta_8821c_2ant, 0x00, sizeof(pBtCoexist->coex_sta_8821c_2ant));
++			break;
++#endif
++#ifdef CONFIG_RTL8723D
++		case BTC_CHIP_RTL8723D:
++			_rtw_memset(&pBtCoexist->coex_dm_8723d_1ant, 0x00, sizeof(pBtCoexist->coex_dm_8723d_1ant));
++			_rtw_memset(&pBtCoexist->coex_dm_8723d_2ant, 0x00, sizeof(pBtCoexist->coex_dm_8723d_2ant));
++			_rtw_memset(&pBtCoexist->coex_sta_8723d_1ant, 0x00, sizeof(pBtCoexist->coex_sta_8723d_1ant));
++			_rtw_memset(&pBtCoexist->coex_sta_8723d_2ant, 0x00, sizeof(pBtCoexist->coex_sta_8723d_2ant));
++			break;
++#endif
++		}
++		break;
++	/* ===================== */
++	default:
++		ret = _FALSE;
++		break;
++	}
++
++	return result;
++}
++
++u8 halbtcoutsrc_UnderIps(PBTC_COEXIST pBtCoexist)
++{
++	PADAPTER padapter;
++	struct pwrctrl_priv *pwrpriv;
++	u8 bMacPwrCtrlOn;
++
++	padapter = pBtCoexist->Adapter;
++	pwrpriv = &padapter->dvobj->pwrctl_priv;
++	bMacPwrCtrlOn = _FALSE;
++
++	if ((_TRUE == pwrpriv->bips_processing)
++	    && (IPS_NONE != pwrpriv->ips_mode_req)
++	   )
++		return _TRUE;
++
++	if (rf_off == pwrpriv->rf_pwrstate)
++		return _TRUE;
++
++	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++	if (_FALSE == bMacPwrCtrlOn)
++		return _TRUE;
++
++	return _FALSE;
++}
++
++u8 halbtcoutsrc_UnderLps(PBTC_COEXIST pBtCoexist)
++{
++	return GLBtcWiFiInLPS;
++}
++
++u8 halbtcoutsrc_Under32K(PBTC_COEXIST pBtCoexist)
++{
++	/* todo: the method to check whether wifi is under 32K or not */
++	return _FALSE;
++}
++
++void halbtcoutsrc_DisplayCoexStatistics(PBTC_COEXIST pBtCoexist)
++{
++#if 0
++	PADAPTER padapter = (PADAPTER)pBtCoexist->Adapter;
++	PBT_MGNT pBtMgnt = &padapter->MgntInfo.BtInfo.BtMgnt;
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++	u8 *cliBuf = pBtCoexist->cliBuf;
++	u8			i, j;
++	u8			tmpbuf[BTC_TMP_BUF_SHORT];
++
++
++	if (gl_coex_offload.cnt_h2c_sent) {
++		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Coex h2c notify]============");
++		CL_PRINTF(cliBuf);
++
++		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = H2c(%d)/Ack(%d)", "Coex h2c/c2h overall statistics",
++			gl_coex_offload.cnt_h2c_sent, gl_coex_offload.cnt_c2h_ack);
++		for (j = 0; j < COL_STATUS_MAX; j++) {
++			if (gl_coex_offload.status[j]) {
++				CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, ", %s:%d", coexH2cResultString[j], gl_coex_offload.status[j]);
++				CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, BTC_TMP_BUF_SHORT);
++			}
++		}
++		CL_PRINTF(cliBuf);
++	}
++	for (i = 0; i < COL_OP_WIFI_OPCODE_MAX; i++) {
++		if (gl_coex_offload.h2c_record[i].count) {
++			/*==========================================*/
++			/*	H2C result statistics*/
++			/*==========================================*/
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = total:%d", coexOpcodeString[i], gl_coex_offload.h2c_record[i].count);
++			for (j = 0; j < COL_STATUS_MAX; j++) {
++				if (gl_coex_offload.h2c_record[i].status[j]) {
++					CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, ", %s:%d", coexH2cResultString[j], gl_coex_offload.h2c_record[i].status[j]);
++					CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, BTC_TMP_BUF_SHORT);
++				}
++			}
++			CL_PRINTF(cliBuf);
++			/*==========================================*/
++			/*	H2C/C2H content*/
++			/*==========================================*/
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = ", "H2C / C2H content");
++			for (j = 0; j < gl_coex_offload.h2c_record[i].h2c_len; j++) {
++				CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, "%02x ", gl_coex_offload.h2c_record[i].h2c_buf[j]);
++				CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, 3);
++			}
++			if (gl_coex_offload.h2c_record[i].c2h_ack_len) {
++				CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, "/ ", 2);
++				for (j = 0; j < gl_coex_offload.h2c_record[i].c2h_ack_len; j++) {
++					CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, "%02x ", gl_coex_offload.h2c_record[i].c2h_ack_buf[j]);
++					CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, 3);
++				}
++			}
++			CL_PRINTF(cliBuf);
++			/*==========================================*/
++		}
++	}
++
++	if (gl_coex_offload.cnt_c2h_ind) {
++		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Coex c2h indication]============");
++		CL_PRINTF(cliBuf);
++
++		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = Ind(%d)", "C2H indication statistics",
++			   gl_coex_offload.cnt_c2h_ind);
++		for (j = 0; j < COL_STATUS_MAX; j++) {
++			if (gl_coex_offload.c2h_ind_status[j]) {
++				CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, ", %s:%d", coexH2cResultString[j], gl_coex_offload.c2h_ind_status[j]);
++				CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, BTC_TMP_BUF_SHORT);
++			}
++		}
++		CL_PRINTF(cliBuf);
++	}
++	for (i = 0; i < COL_IND_MAX; i++) {
++		if (gl_coex_offload.c2h_ind_record[i].count) {
++			/*==========================================*/
++			/*	H2C result statistics*/
++			/*==========================================*/
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = total:%d", coexIndTypeString[i], gl_coex_offload.c2h_ind_record[i].count);
++			for (j = 0; j < COL_STATUS_MAX; j++) {
++				if (gl_coex_offload.c2h_ind_record[i].status[j]) {
++					CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, ", %s:%d", coexH2cResultString[j], gl_coex_offload.c2h_ind_record[i].status[j]);
++					CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, BTC_TMP_BUF_SHORT);
++				}
++			}
++			CL_PRINTF(cliBuf);
++			/*==========================================*/
++			/*	content*/
++			/*==========================================*/
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = ", "C2H indication content");
++			for (j = 0; j < gl_coex_offload.c2h_ind_record[i].ind_len; j++) {
++				CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, "%02x ", gl_coex_offload.c2h_ind_record[i].ind_buf[j]);
++				CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, 3);
++			}
++			CL_PRINTF(cliBuf);
++			/*==========================================*/
++		}
++	}
++
++	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Statistics]============");
++	CL_PRINTF(cliBuf);
++
++#if (H2C_USE_IO_THREAD != 1)
++	for (i = 0; i < H2C_STATUS_MAX; i++) {
++		if (pHalData->h2cStatistics[i]) {
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s] = %d", "H2C statistics", \
++				   h2cStaString[i], pHalData->h2cStatistics[i]);
++			CL_PRINTF(cliBuf);
++		}
++	}
++#else
++	for (i = 0; i < IO_STATUS_MAX; i++) {
++		if (Adapter->ioComStr.ioH2cStatistics[i]) {
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s] = %d", "H2C statistics", \
++				ioStaString[i], Adapter->ioComStr.ioH2cStatistics[i]);
++			CL_PRINTF(cliBuf);
++		}
++	}
++#endif
++#if 0
++	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "lastHMEBoxNum", \
++		   pHalData->LastHMEBoxNum);
++	CL_PRINTF(cliBuf);
++	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x / 0x%x", "LastOkH2c/FirstFailH2c(fwNotRead)", \
++		   pHalData->lastSuccessH2cEid, pHalData->firstFailedH2cEid);
++	CL_PRINTF(cliBuf);
++
++	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "c2hIsr/c2hIntr/clr1AF/noRdy/noBuf", \
++		pHalData->InterruptLog.nIMR_C2HCMD, DBG_Var.c2hInterruptCnt, DBG_Var.c2hClrReadC2hCnt,
++		   DBG_Var.c2hNotReadyCnt, DBG_Var.c2hBufAlloFailCnt);
++	CL_PRINTF(cliBuf);
++
++	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "c2hPacket", \
++		   DBG_Var.c2hPacketCnt);
++	CL_PRINTF(cliBuf);
++#endif
++	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "Periodical/ DbgCtrl", \
++		pBtCoexist->statistics.cntPeriodical, pBtCoexist->statistics.cntDbgCtrl);
++	CL_PRINTF(cliBuf);
++	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "PowerOn/InitHw/InitCoexDm/RfStatus", \
++		pBtCoexist->statistics.cntPowerOn, pBtCoexist->statistics.cntInitHwConfig, pBtCoexist->statistics.cntInitCoexDm,
++		   pBtCoexist->statistics.cntRfStatusNotify);
++	CL_PRINTF(cliBuf);
++	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "Ips/Lps/Scan/Connect/Mstatus", \
++		pBtCoexist->statistics.cntIpsNotify, pBtCoexist->statistics.cntLpsNotify,
++		pBtCoexist->statistics.cntScanNotify, pBtCoexist->statistics.cntConnectNotify,
++		   pBtCoexist->statistics.cntMediaStatusNotify);
++	CL_PRINTF(cliBuf);
++	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", "Special pkt/Bt info/ bind",
++		pBtCoexist->statistics.cntSpecialPacketNotify, pBtCoexist->statistics.cntBtInfoNotify,
++		   pBtCoexist->statistics.cntBind);
++	CL_PRINTF(cliBuf);
++#endif
++	PADAPTER		padapter = pBtCoexist->Adapter;
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++	u8				*cliBuf = pBtCoexist->cli_buf;
++
++	if (pHalData->EEPROMBluetoothCoexist == 1) {
++		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Coex Status]============");
++		CL_PRINTF(cliBuf);
++		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", "IsBtDisabled", rtw_btcoex_IsBtDisabled(padapter));
++		CL_PRINTF(cliBuf);
++		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", "IsBtControlLps", rtw_btcoex_IsBtControlLps(padapter));
++		CL_PRINTF(cliBuf);
++	}
++}
++
++void halbtcoutsrc_DisplayBtLinkInfo(PBTC_COEXIST pBtCoexist)
++{
++#if 0
++	PADAPTER padapter = (PADAPTER)pBtCoexist->Adapter;
++	PBT_MGNT pBtMgnt = &padapter->MgntInfo.BtInfo.BtMgnt;
++	u8 *cliBuf = pBtCoexist->cliBuf;
++	u8 i;
++
++
++	if (pBtCoexist->stack_info.profile_notified) {
++		for (i = 0; i < pBtMgnt->ExtConfig.NumberOfACL; i++) {
++			if (pBtMgnt->ExtConfig.HCIExtensionVer >= 1) {
++				CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", "Bt link type/spec/role", \
++					BtProfileString[pBtMgnt->ExtConfig.aclLink[i].BTProfile],
++					BtSpecString[pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec],
++					BtLinkRoleString[pBtMgnt->ExtConfig.aclLink[i].linkRole]);
++				CL_PRINTF(cliBuf);
++			} else {
++				CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", "Bt link type/spec", \
++					BtProfileString[pBtMgnt->ExtConfig.aclLink[i].BTProfile],
++					BtSpecString[pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec]);
++				CL_PRINTF(cliBuf);
++			}
++		}
++	}
++#endif
++}
++
++void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist)
++{
++	PADAPTER	padapter = pBtCoexist->Adapter;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	u8			*cliBuf = pBtCoexist->cli_buf;
++	s32			wifiRssi = 0, btHsRssi = 0;
++	BOOLEAN	bScan = _FALSE, bLink = _FALSE, bRoam = _FALSE, bWifiBusy = _FALSE, bWifiUnderBMode = _FALSE;
++	u32			wifiBw = BTC_WIFI_BW_HT20, wifiTrafficDir = BTC_WIFI_TRAFFIC_TX, wifiFreq = BTC_FREQ_2_4G;
++	u32			wifiLinkStatus = 0x0;
++	BOOLEAN	bBtHsOn = _FALSE, bLowPower = _FALSE;
++	u8			wifiChnl = 0, wifiP2PChnl = 0, nScanAPNum = 0, FwPSState;
++	u32			iqk_cnt_total = 0, iqk_cnt_ok = 0, iqk_cnt_fail = 0;
++	u16			wifiBcnInterval = 0;
++	PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
++	struct btc_wifi_link_info wifi_link_info;
++
++	wifi_link_info = halbtcoutsrc_getwifilinkinfo(pBtCoexist);
++
++	switch (wifi_link_info.link_mode) {
++		case BTC_LINK_NONE:
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
++					"None", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
++			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
++			break;
++		case BTC_LINK_ONLY_GO:
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
++					"ONLY_GO", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
++			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
++			break;
++		case BTC_LINK_ONLY_GC:
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
++					"ONLY_GC", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
++			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
++			break;
++		case BTC_LINK_ONLY_STA:
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
++					"ONLY_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
++			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
++			break;
++		case BTC_LINK_ONLY_AP:
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
++					"ONLY_AP", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
++			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
++			break;
++		case BTC_LINK_2G_MCC_GO_STA:
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
++					"24G_MCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
++			wifiFreq = BTC_FREQ_2_4G;
++			break;
++		case BTC_LINK_5G_MCC_GO_STA:
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
++					"5G_MCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
++			wifiFreq = BTC_FREQ_5G;
++			break;
++		case BTC_LINK_25G_MCC_GO_STA:
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
++					"2BANDS_MCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
++			wifiFreq = BTC_FREQ_25G;
++			break;
++		case BTC_LINK_2G_MCC_GC_STA:
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
++					"24G_MCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
++			wifiFreq = BTC_FREQ_2_4G;
++			break;
++		case BTC_LINK_5G_MCC_GC_STA:
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
++					"5G_MCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
++			wifiFreq = BTC_FREQ_5G;
++			break;
++		case BTC_LINK_25G_MCC_GC_STA:
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
++					"2BANDS_MCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
++			wifiFreq = BTC_FREQ_25G;
++			break;
++		case BTC_LINK_2G_SCC_GO_STA:
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
++					"24G_SCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
++			wifiFreq = BTC_FREQ_2_4G;
++			break;
++		case BTC_LINK_5G_SCC_GO_STA:
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
++					"5G_SCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
++			wifiFreq = BTC_FREQ_5G;
++			break;
++		case BTC_LINK_2G_SCC_GC_STA:
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
++					"24G_SCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
++			wifiFreq = BTC_FREQ_2_4G;
++			break;
++		case BTC_LINK_5G_SCC_GC_STA:
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
++					"5G_SCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
++			wifiFreq = BTC_FREQ_5G;
++			break;
++		default:
++			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
++					"UNKNOWN", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
++			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
++			break;
++	}
++
++	CL_PRINTF(cliBuf);
++
++	wifiLinkStatus = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist);
++	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "STA/vWifi/HS/p2pGo/p2pGc",
++		((wifiLinkStatus & WIFI_STA_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_AP_CONNECTED) ? 1 : 0),
++		((wifiLinkStatus & WIFI_HS_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_P2P_GO_CONNECTED) ? 1 : 0),
++		((wifiLinkStatus & WIFI_P2P_GC_CONNECTED) ? 1 : 0));
++	CL_PRINTF(cliBuf);
++
++	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
++	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
++	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
++	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "Link/ Roam/ Scan",
++		bLink, bRoam, bScan);
++	CL_PRINTF(cliBuf);	
++
++	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_TOTAL, &iqk_cnt_total);
++	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_OK, &iqk_cnt_ok);
++	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_FAIL, &iqk_cnt_fail);
++	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d %s %s",
++		"IQK All/ OK/ Fail/AutoLoad/FWDL", iqk_cnt_total, iqk_cnt_ok, iqk_cnt_fail,
++		((halbtcoutsrc_is_autoload_fail(pBtCoexist) == _TRUE) ? "fail":"ok"), ((halbtcoutsrc_is_fw_ready(pBtCoexist) == _TRUE) ? "ok":"fail"));
++	CL_PRINTF(cliBuf);
++	
++	if (wifiLinkStatus & WIFI_STA_CONNECTED) {
++		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "IOT Peer", GLBtcIotPeerString[padapter->mlmeextpriv.mlmext_info.assoc_AP_vendor]);
++		CL_PRINTF(cliBuf);
++	}
++
++	pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);
++	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U2_BEACON_PERIOD, &wifiBcnInterval);
++	wifiChnl = wifi_link_info.sta_center_channel;
++	wifiP2PChnl = wifi_link_info.p2p_center_channel;
++
++	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dBm/ %d/ %d/ %d", "RSSI/ STA_Chnl/ P2P_Chnl/ BI",
++		wifiRssi-100, wifiChnl, wifiP2PChnl, wifiBcnInterval);
++	CL_PRINTF(cliBuf);
++
++	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
++	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
++	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
++	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode);
++	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_AP_NUM, &nScanAPNum);
++	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s/ %d ", "Band/ BW/ Traffic/ APCnt",
++		GLBtcWifiFreqString[wifiFreq], ((bWifiUnderBMode) ? "11b" : GLBtcWifiBwString[wifiBw]),
++		((!bWifiBusy) ? "idle" : ((BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) ? "uplink" : "downlink")),
++		   nScanAPNum);
++	CL_PRINTF(cliBuf);
++
++	/* power status */
++	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s%s%s", "Power Status", \
++		((halbtcoutsrc_UnderIps(pBtCoexist) == _TRUE) ? "IPS ON" : "IPS OFF"),
++		((halbtcoutsrc_UnderLps(pBtCoexist) == _TRUE) ? ", LPS ON" : ", LPS OFF"),
++		((halbtcoutsrc_Under32K(pBtCoexist) == _TRUE) ? ", 32k" : ""));
++	CL_PRINTF(cliBuf);
++
++	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x (0x%x/0x%x)", "Power mode cmd(lps/rpwm)",
++		   pBtCoexist->pwrModeVal[0], pBtCoexist->pwrModeVal[1],
++		   pBtCoexist->pwrModeVal[2], pBtCoexist->pwrModeVal[3],
++		   pBtCoexist->pwrModeVal[4], pBtCoexist->pwrModeVal[5],
++		   pBtCoexist->bt_info.lps_val,
++		   pBtCoexist->bt_info.rpwm_val);
++	CL_PRINTF(cliBuf);
++}
++
++void halbtcoutsrc_DisplayDbgMsg(void *pBtcContext, u8 dispType)
++{
++	PBTC_COEXIST pBtCoexist;
++
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++	switch (dispType) {
++	case BTC_DBG_DISP_COEX_STATISTICS:
++		halbtcoutsrc_DisplayCoexStatistics(pBtCoexist);
++		break;
++	case BTC_DBG_DISP_BT_LINK_INFO:
++		halbtcoutsrc_DisplayBtLinkInfo(pBtCoexist);
++		break;
++	case BTC_DBG_DISP_WIFI_STATUS:
++		halbtcoutsrc_DisplayWifiStatus(pBtCoexist);
++		break;
++	default:
++		break;
++	}
++}
++
++/* ************************************
++ *		IO related function
++ * ************************************ */
++u8 halbtcoutsrc_Read1Byte(void *pBtcContext, u32 RegAddr)
++{
++	PBTC_COEXIST pBtCoexist;
++	PADAPTER padapter;
++
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++	padapter = pBtCoexist->Adapter;
++
++	return rtw_read8(padapter, RegAddr);
++}
++
++u16 halbtcoutsrc_Read2Byte(void *pBtcContext, u32 RegAddr)
++{
++	PBTC_COEXIST pBtCoexist;
++	PADAPTER padapter;
++
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++	padapter = pBtCoexist->Adapter;
++
++	return	rtw_read16(padapter, RegAddr);
++}
++
++u32 halbtcoutsrc_Read4Byte(void *pBtcContext, u32 RegAddr)
++{
++	PBTC_COEXIST pBtCoexist;
++	PADAPTER padapter;
++
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++	padapter = pBtCoexist->Adapter;
++
++	return	rtw_read32(padapter, RegAddr);
++}
++
++void halbtcoutsrc_Write1Byte(void *pBtcContext, u32 RegAddr, u8 Data)
++{
++	PBTC_COEXIST pBtCoexist;
++	PADAPTER padapter;
++
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++	padapter = pBtCoexist->Adapter;
++
++	rtw_write8(padapter, RegAddr, Data);
++}
++
++void halbtcoutsrc_BitMaskWrite1Byte(void *pBtcContext, u32 regAddr, u8 bitMask, u8 data1b)
++{
++	PBTC_COEXIST pBtCoexist;
++	PADAPTER padapter;
++	u8 originalValue, bitShift;
++	u8 i;
++
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++	padapter = pBtCoexist->Adapter;
++	originalValue = 0;
++	bitShift = 0;
++
++	if (bitMask != 0xff) {
++		originalValue = rtw_read8(padapter, regAddr);
++
++		for (i = 0; i <= 7; i++) {
++			if ((bitMask >> i) & 0x1)
++				break;
++		}
++		bitShift = i;
++
++		data1b = (originalValue & ~bitMask) | ((data1b << bitShift) & bitMask);
++	}
++
++	rtw_write8(padapter, regAddr, data1b);
++}
++
++void halbtcoutsrc_Write2Byte(void *pBtcContext, u32 RegAddr, u16 Data)
++{
++	PBTC_COEXIST pBtCoexist;
++	PADAPTER padapter;
++
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++	padapter = pBtCoexist->Adapter;
++
++	rtw_write16(padapter, RegAddr, Data);
++}
++
++void halbtcoutsrc_Write4Byte(void *pBtcContext, u32 RegAddr, u32 Data)
++{
++	PBTC_COEXIST pBtCoexist;
++	PADAPTER padapter;
++
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++	padapter = pBtCoexist->Adapter;
++
++	rtw_write32(padapter, RegAddr, Data);
++}
++
++void halbtcoutsrc_WriteLocalReg1Byte(void *pBtcContext, u32 RegAddr, u8 Data)
++{
++	PBTC_COEXIST		pBtCoexist = (PBTC_COEXIST)pBtcContext;
++	PADAPTER			Adapter = pBtCoexist->Adapter;
++
++	if (BTC_INTF_SDIO == pBtCoexist->chip_interface)
++		rtw_write8(Adapter, SDIO_LOCAL_BASE | RegAddr, Data);
++	else
++		rtw_write8(Adapter, RegAddr, Data);
++}
++
++u32 halbtcoutsrc_WaitLIndirectReg_Ready(void *pBtcContext)
++{
++	PBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;
++	u32 delay_count = 0, reg = 0;
++
++	if (!btc->chip_para->lte_indirect_access)
++		return 0;
++
++	switch (btc->chip_para->indirect_type) {
++	case BTC_INDIRECT_1700:
++		reg = 0x1703;
++		break;
++	case BTC_INDIRECT_7C0:
++		reg = 0x7C3;
++		break;
++	default:
++		return 0;
++	}
++
++	/* wait for ready bit before access */
++	while (1) {
++		if ((halbtcoutsrc_Read1Byte(btc, reg) & BIT(5)) == 0) {
++			rtw_mdelay_os(10);
++			if (++delay_count >= 10)
++				break;
++		} else {
++			break;
++		}
++	}
++
++	return delay_count;
++}
++
++u32 halbtcoutsrc_ReadLIndirectReg(void *pBtcContext, u16 reg_addr)
++{
++	PBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;
++	u32 val = 0;
++
++	if (!btc->chip_para->lte_indirect_access)
++		return 0;
++
++	/* wait for ready bit before access */
++	halbtcoutsrc_WaitLIndirectReg_Ready(btc);
++
++	switch (btc->chip_para->indirect_type) {
++	case BTC_INDIRECT_1700:
++		halbtcoutsrc_Write4Byte(btc, 0x1700, 0x800F0000 | reg_addr);
++		val = halbtcoutsrc_Read4Byte(btc, 0x1708); /* get read data */
++		break;
++	case BTC_INDIRECT_7C0:
++		halbtcoutsrc_Write4Byte(btc, 0x7c0, 0x800F0000 | reg_addr);
++		val = halbtcoutsrc_Read4Byte(btc, 0x7c8); /* get read data */
++		break;
++	}
++
++	return val;
++}
++
++void halbtcoutsrc_WriteLIndirectReg(void *pBtcContext, u16 reg_addr, u32 bit_mask, u32 reg_value)
++{
++	PBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;
++	u32 val, i = 0, bitpos = 0, reg0, reg1;
++
++	if (!btc->chip_para->lte_indirect_access)
++		return;
++
++	if (bit_mask == 0x0)
++		return;
++
++	switch (btc->chip_para->indirect_type) {
++	case BTC_INDIRECT_1700:
++		reg0 = 0x1700;
++		reg1 = 0x1704;
++		break;
++	case BTC_INDIRECT_7C0:
++		reg0 = 0x7C0;
++		reg1 = 0x7C4;
++		break;
++	default:
++		return;
++	}
++
++	if (bit_mask == 0xffffffff) {
++		/* wait for ready bit before access 0x1700 */
++		halbtcoutsrc_WaitLIndirectReg_Ready(btc);
++
++		/* put write data */
++		halbtcoutsrc_Write4Byte(btc, reg1, reg_value);
++		halbtcoutsrc_Write4Byte(btc, reg0, 0xc00F0000 | reg_addr);
++	} else {
++		for (i = 0; i <= 31; i++) {
++			if (((bit_mask >> i) & 0x1) == 0x1) {
++				bitpos = i;
++				break;
++			}
++		}
++
++		/* read back register value before write */
++		val = halbtcoutsrc_ReadLIndirectReg(btc, reg_addr);
++		val = (val & (~bit_mask)) | (reg_value << bitpos);
++
++		/* wait for ready bit before access 0x1700 */
++		halbtcoutsrc_WaitLIndirectReg_Ready(btc);
++
++		halbtcoutsrc_Write4Byte(btc, reg1, val); /* put write data */
++		halbtcoutsrc_Write4Byte(btc, reg0, 0xc00F0000 | reg_addr);
++	}
++}
++
++u16 halbtcoutsrc_Read_scbd(void *pBtcContext, u16* score_board_val)
++{
++	PBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;
++	struct btc_coex_sta *coex_sta = &btc->coex_sta;
++	const struct btc_chip_para *chip_para = btc->chip_para;
++
++	if (!chip_para->scbd_support)
++		return 0;
++
++	*score_board_val = (btc->btc_read_2byte(btc, 0xaa)) & 0x7fff;
++	coex_sta->score_board_BW = *score_board_val;
++
++	return coex_sta->score_board_BW;
++}
++
++void halbtcoutsrc_Write_scbd(void *pBtcContext, u16 bitpos, u8 state)
++{
++	PBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;
++	struct btc_coex_sta *coex_sta = &btc->coex_sta;
++	const struct btc_chip_para *chip_para = btc->chip_para;
++	u16 val = 0x2;
++	u8* btc_dbg_buf = &gl_btc_trace_buf[0];
++
++	if (!chip_para->scbd_support)
++		return;
++
++	val = val | coex_sta->score_board_WB;
++
++	/* for 8822b, Scoreboard[10]: 0: CQDDR off, 1: CQDDR on
++	 * for 8822c, Scoreboard[10]: 0: CQDDR on, 1:CQDDR fix 2M
++	 */
++	if (!btc->chip_para->new_scbd10_def && (bitpos & BTC_SCBD_FIX2M)) {
++		if (state)
++			val = val & (~BTC_SCBD_FIX2M);
++		else
++			val = val | BTC_SCBD_FIX2M;
++	} else {
++		if (state)
++			val = val | bitpos;
++		else
++			val = val & (~bitpos);
++	}
++
++	if (val != coex_sta->score_board_WB) {
++		coex_sta->score_board_WB = val;
++		val = val | 0x8000;
++		btc->btc_write_2byte(btc, 0xaa, val);
++
++		BTC_SPRINTF(btc_dbg_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], write scoreboard 0x%x\n", val);
++	} else {
++		BTC_SPRINTF(btc_dbg_buf, BT_TMP_BUF_SIZE,
++			    "[BTCoex], %s: return for nochange\n", __func__);
++	}
++
++	BTC_TRACE(btc_dbg_buf);
++}
++
++void halbtcoutsrc_SetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask, u32 Data)
++{
++	PBTC_COEXIST pBtCoexist;
++	PADAPTER padapter;
++
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++	padapter = pBtCoexist->Adapter;
++
++	phy_set_bb_reg(padapter, RegAddr, BitMask, Data);
++}
++
++
++u32 halbtcoutsrc_GetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask)
++{
++	PBTC_COEXIST pBtCoexist;
++	PADAPTER padapter;
++
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++	padapter = pBtCoexist->Adapter;
++
++	return phy_query_bb_reg(padapter, RegAddr, BitMask);
++}
++
++void halbtcoutsrc_SetRfReg(void *pBtcContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
++{
++	PBTC_COEXIST pBtCoexist;
++	PADAPTER padapter;
++
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++	padapter = pBtCoexist->Adapter;
++
++	phy_set_rf_reg(padapter, eRFPath, RegAddr, BitMask, Data);
++}
++
++u32 halbtcoutsrc_GetRfReg(void *pBtcContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask)
++{
++	PBTC_COEXIST pBtCoexist;
++	PADAPTER padapter;
++
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++	padapter = pBtCoexist->Adapter;
++
++	return phy_query_rf_reg(padapter, eRFPath, RegAddr, BitMask);
++}
++
++u16 halbtcoutsrc_SetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr, u32 Data)
++{
++	PBTC_COEXIST pBtCoexist;
++	u16 ret = BT_STATUS_BT_OP_SUCCESS;
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++
++	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
++		u8 buf[3] = {0};
++		_irqL irqL;
++		u8 op_code;
++		u8 status;
++
++		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++		Data = cpu_to_le32(Data);
++		op_code = BT_OP_WRITE_REG_VALUE;
++		status = _btmpoper_cmd(pBtCoexist, op_code, 0, (u8 *)&Data, 3);
++		if (status != BT_STATUS_BT_OP_SUCCESS)
++			ret = SET_BT_MP_OPER_RET(op_code, status);
++		else {
++			buf[0] = RegType;
++			*(u16 *)(buf + 1) = cpu_to_le16((u16)RegAddr);
++			op_code = BT_OP_WRITE_REG_ADDR;
++			status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 3);
++			if (status != BT_STATUS_BT_OP_SUCCESS)
++				ret = SET_BT_MP_OPER_RET(op_code, status);
++		}
++
++		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++	} else
++		ret = BT_STATUS_NOT_IMPLEMENT;
++
++	return ret;
++}
++
++u8 halbtcoutsrc_SetBtAntDetection(void *pBtcContext, u8 txTime, u8 btChnl)
++{
++	/* Always return _FALSE since we don't implement this yet */
++#if 0
++	PBTC_COEXIST		pBtCoexist = (PBTC_COEXIST)pBtcContext;
++	PADAPTER			Adapter = pBtCoexist->Adapter;
++	u8				btCanTx = 0;
++	BOOLEAN			bStatus = FALSE;
++
++	bStatus = NDBG_SetBtAntDetection(Adapter, txTime, btChnl, &btCanTx);
++	if (bStatus && btCanTx)
++		return _TRUE;
++	else
++		return _FALSE;
++#else
++	return _FALSE;
++#endif
++}
++
++u8 halbtcoutsrc_SetBtTRXMASK(void *pBtcContext, u8 bt_trx_mask)
++{
++	PBTC_COEXIST 	pBtCoexist;
++	u8			bStatus = _FALSE;
++	u8			btCanTx = 0;
++	u16 		ret = BT_STATUS_BT_OP_SUCCESS;
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++
++	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter) || IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)
++			|| IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++
++		if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
++			u8 buf[3] = {0};
++			u8 len = 0;
++			_irqL irqL;
++			u8 op_code;
++			u8 status;
++
++			if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++				buf[0] = bt_trx_mask;
++				len = 1;
++			} else {
++				buf[0] = (bt_trx_mask & 0x80) >> 7;
++				buf[1] = bt_trx_mask & 0x7f;
++				len = 2;
++			}
++
++			_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++			op_code = BT_OP_SET_BT_TRX_MASK;
++			status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, len);
++			if (status != BT_STATUS_BT_OP_SUCCESS)
++				ret = SET_BT_MP_OPER_RET(op_code, status);
++
++			_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++		} else
++			ret = BT_STATUS_NOT_IMPLEMENT;
++	}
++
++	if (ret == BT_STATUS_BT_OP_SUCCESS)
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++u16 halbtcoutsrc_GetBtReg_with_status(void *pBtcContext, u8 RegType, u32 RegAddr, u32 *data)
++{
++	PBTC_COEXIST pBtCoexist;
++	u16 ret = BT_STATUS_BT_OP_SUCCESS;
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++
++	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
++		u8 buf[3] = {0};
++		_irqL irqL;
++		u8 op_code;
++		u8 status;
++
++		buf[0] = RegType;
++		*(u16 *)(buf + 1) = cpu_to_le16((u16)RegAddr);
++
++		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++		op_code = BT_OP_READ_REG;
++		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 3);
++		if (status == BT_STATUS_BT_OP_SUCCESS)
++			*data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
++		else
++			ret = SET_BT_MP_OPER_RET(op_code, status);
++
++		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++	} else
++		ret = BT_STATUS_NOT_IMPLEMENT;
++
++	return ret;
++}
++
++u32 halbtcoutsrc_GetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr)
++{
++	u32 regVal;
++	
++	return (BT_STATUS_BT_OP_SUCCESS == halbtcoutsrc_GetBtReg_with_status(pBtcContext, RegType, RegAddr, &regVal)) ? regVal : 0xffffffff;
++}
++
++u16 halbtcoutsrc_setbttestmode(void *pBtcContext, u8 Type)
++{
++	PBTC_COEXIST pBtCoexist;
++	u16 ret = BT_STATUS_BT_OP_SUCCESS;
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++
++	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
++		_irqL irqL;
++		u8 op_code;
++		u8 status;
++
++		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++		Type = cpu_to_le32(Type);
++		op_code = BT_OP_SET_BT_TEST_MODE_VAL;
++		status = _btmpoper_cmd(pBtCoexist, op_code, 0, (u8 *)&Type, 3);
++		if (status != BT_STATUS_BT_OP_SUCCESS)
++			ret = SET_BT_MP_OPER_RET(op_code, status);
++
++		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++	} else
++		ret = BT_STATUS_NOT_IMPLEMENT;
++
++	return ret;
++
++}
++
++
++void halbtcoutsrc_FillH2cCmd(void *pBtcContext, u8 elementId, u32 cmdLen, u8 *pCmdBuffer)
++{
++	PBTC_COEXIST pBtCoexist;
++	PADAPTER padapter;
++	s32 ret = 0;
++
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++	padapter = pBtCoexist->Adapter;
++
++	ret = rtw_hal_fill_h2c_cmd(padapter, elementId, cmdLen, pCmdBuffer);
++
++#ifdef CONFIG_RTL8192F
++	if (ret == _SUCCESS) {
++		switch (elementId) {
++		case H2C_BT_INFO:
++		case H2C_BT_IGNORE_WLANACT:
++		case H2C_WL_OPMODE:
++		case H2C_BT_MP_OPER:
++		case H2C_BT_CONTROL:
++			rtw_msleep_os(20);
++			break;
++		}
++	}
++#endif
++}
++
++static void halbtcoutsrc_coex_offload_init(void)
++{
++	u8	i;
++
++	gl_coex_offload.h2c_req_num = 0;
++	gl_coex_offload.cnt_h2c_sent = 0;
++	gl_coex_offload.cnt_c2h_ack = 0;
++	gl_coex_offload.cnt_c2h_ind = 0;
++
++	for (i = 0; i < COL_MAX_H2C_REQ_NUM; i++)
++		init_completion(&gl_coex_offload.c2h_event[i]);
++}
++
++static COL_H2C_STATUS halbtcoutsrc_send_h2c(PADAPTER Adapter, PCOL_H2C pcol_h2c, u16 h2c_cmd_len)
++{
++	COL_H2C_STATUS		h2c_status = COL_STATUS_C2H_OK;
++	u8				i;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0))
++	reinit_completion(&gl_coex_offload.c2h_event[pcol_h2c->req_num]);		/* set event to un signaled state */
++#else
++	INIT_COMPLETION(gl_coex_offload.c2h_event[pcol_h2c->req_num]);
++#endif
++
++	if (TRUE) {
++#if 0	/*(USE_HAL_MAC_API == 1) */
++		if (RT_STATUS_SUCCESS == HAL_MAC_Send_BT_COEX(&GET_HAL_MAC_INFO(Adapter), (u8 *)(pcol_h2c), (u32)h2c_cmd_len, 1)) {
++			if (!wait_for_completion_timeout(&gl_coex_offload.c2h_event[pcol_h2c->req_num], 20)) {
++				h2c_status = COL_STATUS_H2C_TIMTOUT;
++			}
++		} else {
++			h2c_status = COL_STATUS_H2C_HALMAC_FAIL;
++		}
++#endif
++	}
++
++	return h2c_status;
++}
++
++static COL_H2C_STATUS halbtcoutsrc_check_c2h_ack(PADAPTER Adapter, PCOL_SINGLE_H2C_RECORD pH2cRecord)
++{
++	COL_H2C_STATUS	c2h_status = COL_STATUS_C2H_OK;
++	PCOL_H2C		p_h2c_cmd = (PCOL_H2C)&pH2cRecord->h2c_buf[0];
++	u8			req_num = p_h2c_cmd->req_num;
++	PCOL_C2H_ACK	p_c2h_ack = (PCOL_C2H_ACK)&gl_coex_offload.c2h_ack_buf[req_num];
++
++
++	if ((COL_C2H_ACK_HDR_LEN + p_c2h_ack->ret_len) > gl_coex_offload.c2h_ack_len[req_num]) {
++		c2h_status = COL_STATUS_COEX_DATA_OVERFLOW;
++		return c2h_status;
++	}
++	/* else */
++	{
++		_rtw_memmove(&pH2cRecord->c2h_ack_buf[0], &gl_coex_offload.c2h_ack_buf[req_num], gl_coex_offload.c2h_ack_len[req_num]);
++		pH2cRecord->c2h_ack_len = gl_coex_offload.c2h_ack_len[req_num];
++	}
++
++
++	if (p_c2h_ack->req_num != p_h2c_cmd->req_num) {
++		c2h_status = COL_STATUS_C2H_REQ_NUM_MISMATCH;
++	} else if (p_c2h_ack->opcode_ver != p_h2c_cmd->opcode_ver) {
++		c2h_status = COL_STATUS_C2H_OPCODE_VER_MISMATCH;
++	} else {
++		c2h_status = p_c2h_ack->status;
++	}
++
++	return c2h_status;
++}
++
++COL_H2C_STATUS halbtcoutsrc_CoexH2cProcess(void *pBtCoexist,
++		u8 opcode, u8 opcode_ver, u8 *ph2c_par, u8 h2c_par_len)
++{
++	PADAPTER			Adapter = ((struct btc_coexist *)pBtCoexist)->Adapter;
++	u8				H2C_Parameter[BTC_TMP_BUF_SHORT] = {0};
++	PCOL_H2C			pcol_h2c = (PCOL_H2C)&H2C_Parameter[0];
++	u16				paraLen = 0;
++	COL_H2C_STATUS		h2c_status = COL_STATUS_C2H_OK, c2h_status = COL_STATUS_C2H_OK;
++	COL_H2C_STATUS		ret_status = COL_STATUS_C2H_OK;
++	u16				i, col_h2c_len = 0;
++
++	pcol_h2c->opcode = opcode;
++	pcol_h2c->opcode_ver = opcode_ver;
++	pcol_h2c->req_num = gl_coex_offload.h2c_req_num;
++	gl_coex_offload.h2c_req_num++;
++	gl_coex_offload.h2c_req_num %= 16;
++
++	_rtw_memmove(&pcol_h2c->buf[0], ph2c_par, h2c_par_len);
++
++
++	col_h2c_len = h2c_par_len + 2;	/* 2=sizeof(OPCode, OPCode_version and  Request number) */
++	BT_PrintData(Adapter, "[COL], H2C cmd: ", col_h2c_len, H2C_Parameter);
++
++	gl_coex_offload.cnt_h2c_sent++;
++
++	gl_coex_offload.h2c_record[opcode].count++;
++	gl_coex_offload.h2c_record[opcode].h2c_len = col_h2c_len;
++	_rtw_memmove((void *)&gl_coex_offload.h2c_record[opcode].h2c_buf[0], (void *)pcol_h2c, col_h2c_len);
++
++	h2c_status = halbtcoutsrc_send_h2c(Adapter, pcol_h2c, col_h2c_len);
++
++	gl_coex_offload.h2c_record[opcode].c2h_ack_len = 0;
++
++	if (COL_STATUS_C2H_OK == h2c_status) {
++		/* if reach here, it means H2C get the correct c2h response, */
++		c2h_status = halbtcoutsrc_check_c2h_ack(Adapter, &gl_coex_offload.h2c_record[opcode]);
++		ret_status = c2h_status;
++	} else {
++		/* check h2c status error, return error status code to upper layer. */
++		ret_status = h2c_status;
++	}
++	gl_coex_offload.h2c_record[opcode].status[ret_status]++;
++	gl_coex_offload.status[ret_status]++;
++
++	return ret_status;
++}
++
++u8 halbtcoutsrc_GetAntDetValFromBt(void *pBtcContext)
++{
++	/* Always return 0 since we don't implement this yet */
++#if 0
++	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
++	PADAPTER			Adapter = pBtCoexist->Adapter;
++	u8				AntDetVal = 0x0;
++	u8				opcodeVer = 1;
++	BOOLEAN				status = false;
++
++	status = NDBG_GetAntDetValFromBt(Adapter, opcodeVer, &AntDetVal);
++
++	RT_TRACE(COMP_DBG, DBG_LOUD, ("$$$ halbtcoutsrc_GetAntDetValFromBt(): status = %d, feature = %x\n", status, AntDetVal));
++
++	return AntDetVal;
++#else
++	return 0;
++#endif
++}
++
++u8 halbtcoutsrc_GetBleScanTypeFromBt(void *pBtcContext)
++{
++	PBTC_COEXIST pBtCoexist;
++	u32 ret = BT_STATUS_BT_OP_SUCCESS;
++	u8 data = 0;
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++
++	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
++		u8 buf[3] = {0};
++		_irqL irqL;
++		u8 op_code;
++		u8 status;
++
++
++		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++		op_code = BT_OP_GET_BT_BLE_SCAN_TYPE;
++		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
++		if (status == BT_STATUS_BT_OP_SUCCESS)
++			data = *(u8 *)GLBtcBtMpRptRsp;
++		else
++			ret = SET_BT_MP_OPER_RET(op_code, status);
++
++		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++	} else
++		ret = BT_STATUS_NOT_IMPLEMENT;
++
++	return data;
++}
++
++u32 halbtcoutsrc_GetBleScanParaFromBt(void *pBtcContext, u8 scanType)
++{
++	PBTC_COEXIST pBtCoexist;
++	u32 ret = BT_STATUS_BT_OP_SUCCESS;
++	u32 data = 0;
++
++	pBtCoexist = (PBTC_COEXIST)pBtcContext;
++
++	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
++		u8 buf[3] = {0};
++		_irqL irqL;
++		u8 op_code;
++		u8 status;
++		
++		buf[0] = scanType;
++
++		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++		op_code = BT_OP_GET_BT_BLE_SCAN_PARA;
++		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 1);
++		if (status == BT_STATUS_BT_OP_SUCCESS)
++			data = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
++		else
++			ret = SET_BT_MP_OPER_RET(op_code, status);
++
++		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++	} else
++		ret = BT_STATUS_NOT_IMPLEMENT;
++
++	return data;
++}
++
++u8 halbtcoutsrc_GetBtAFHMapFromBt(void *pBtcContext, u8 mapType, u8 *afhMap)
++{
++	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
++	u8 buf[2] = {0};
++	_irqL irqL;
++	u8 op_code;
++	u32 *AfhMapL = (u32 *)&(afhMap[0]);
++	u32 *AfhMapM = (u32 *)&(afhMap[4]);
++	u16 *AfhMapH = (u16 *)&(afhMap[8]);
++	u8 status;
++	u32 ret = BT_STATUS_BT_OP_SUCCESS;
++
++	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _FALSE)
++		return _FALSE;
++
++	buf[0] = 0;
++	buf[1] = mapType;
++
++	_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++	op_code = BT_LO_OP_GET_AFH_MAP_L;
++	status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
++	if (status == BT_STATUS_BT_OP_SUCCESS)
++		*AfhMapL = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
++	else {
++		ret = SET_BT_MP_OPER_RET(op_code, status);
++		goto exit;
++	}
++
++	op_code = BT_LO_OP_GET_AFH_MAP_M;
++	status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
++	if (status == BT_STATUS_BT_OP_SUCCESS)
++		*AfhMapM = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
++	else {
++		ret = SET_BT_MP_OPER_RET(op_code, status);
++		goto exit;
++	}
++
++	op_code = BT_LO_OP_GET_AFH_MAP_H;
++	status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
++	if (status == BT_STATUS_BT_OP_SUCCESS)
++		*AfhMapH = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
++	else {
++		ret = SET_BT_MP_OPER_RET(op_code, status);
++		goto exit;
++	}
++
++exit:
++
++	_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
++
++	return (ret == BT_STATUS_BT_OP_SUCCESS) ? _TRUE : _FALSE;
++}
++
++u8 halbtcoutsrc_SetTimer(void *pBtcContext, u32 type, u32 val)
++{
++	struct btc_coexist *pBtCoexist=(struct btc_coexist *)pBtcContext;
++
++	if (type >= BTC_TIMER_MAX)
++		return _FALSE;
++
++	pBtCoexist->coex_sta.cnt_timer[type] = val;
++
++	RTW_DBG("[BTC], Set Timer: type = %d, val = %d\n", type, val);
++
++	return _TRUE;
++}
++
++u32 halbtcoutsrc_SetAtomic (void *btc_ctx, u32 *target, u32 val)
++{
++	*target = val;
++	return _SUCCESS;
++}
++
++void halbtcoutsrc_phydm_modify_AntDiv_HwSw(void *pBtcContext, u8 is_hw)
++{
++	/* empty function since we don't need it */
++}
++
++void halbtcoutsrc_phydm_modify_RA_PCR_threshold(void *pBtcContext, u8 RA_offset_direction, u8 RA_threshold_offset)
++{
++	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
++
++/* switch to #if 0 in case the phydm version does not provide the function */
++#if 1
++	phydm_modify_RA_PCR_threshold(pBtCoexist->odm_priv, RA_offset_direction, RA_threshold_offset);
++#endif
++}
++
++u32 halbtcoutsrc_phydm_query_PHY_counter(void *pBtcContext, u8 info_type)
++{
++	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
++
++/* switch to #if 0 in case the phydm version does not provide the function */
++#if 1
++	return phydm_cmn_info_query((struct dm_struct *)pBtCoexist->odm_priv, (enum phydm_info_query)info_type);
++#else
++	return 0;
++#endif
++}
++
++void halbtcoutsrc_reduce_wl_tx_power(void *pBtcContext, s8 tx_power)
++{
++	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA((PADAPTER)pBtCoexist->Adapter);
++
++	/* The reduction of wl tx pwr should be processed inside the set tx pwr lvl function */
++	if (IS_HARDWARE_TYPE_8822C(pBtCoexist->Adapter))
++		rtw_hal_set_tx_power_level(pBtCoexist->Adapter, pHalData->current_channel);
++}
++
++#if 0
++static void BT_CoexOffloadRecordErrC2hAck(PADAPTER	Adapter)
++{
++	PADAPTER		pDefaultAdapter = GetDefaultAdapter(Adapter);
++
++	if (pDefaultAdapter != Adapter)
++		return;
++
++	if (!hal_btcoex_IsBtExist(Adapter))
++		return;
++
++	gl_coex_offload.cnt_c2h_ack++;
++
++	gl_coex_offload.status[COL_STATUS_INVALID_C2H_LEN]++;
++}
++
++static void BT_CoexOffloadC2hAckCheck(PADAPTER	Adapter, u8 *tmpBuf, u8 length)
++{
++	PADAPTER		pDefaultAdapter = GetDefaultAdapter(Adapter);
++	PCOL_C2H_ACK	p_c2h_ack = NULL;
++	u8			req_num = 0xff;
++
++	if (pDefaultAdapter != Adapter)
++		return;
++
++	if (!hal_btcoex_IsBtExist(Adapter))
++		return;
++
++	gl_coex_offload.cnt_c2h_ack++;
++
++	if (length < COL_C2H_ACK_HDR_LEN) {		/* c2h ack length must >= 3 (status, opcode_ver, req_num and ret_len) */
++		gl_coex_offload.status[COL_STATUS_INVALID_C2H_LEN]++;
++	} else {
++		BT_PrintData(Adapter, "[COL], c2h ack:", length, tmpBuf);
++
++		p_c2h_ack = (PCOL_C2H_ACK)tmpBuf;
++		req_num = p_c2h_ack->req_num;
++
++		_rtw_memmove(&gl_coex_offload.c2h_ack_buf[req_num][0], tmpBuf, length);
++		gl_coex_offload.c2h_ack_len[req_num] = length;
++
++		complete(&gl_coex_offload.c2h_event[req_num]);
++	}
++}
++
++static void BT_CoexOffloadC2hIndCheck(PADAPTER Adapter, u8 *tmpBuf, u8 length)
++{
++	PADAPTER		pDefaultAdapter = GetDefaultAdapter(Adapter);
++	PCOL_C2H_IND	p_c2h_ind = NULL;
++	u8			ind_type = 0, ind_version = 0, ind_length = 0;
++
++	if (pDefaultAdapter != Adapter)
++		return;
++
++	if (!hal_btcoex_IsBtExist(Adapter))
++		return;
++
++	gl_coex_offload.cnt_c2h_ind++;
++
++	if (length < COL_C2H_IND_HDR_LEN) {		/* c2h indication length must >= 3 (type, version and length) */
++		gl_coex_offload.c2h_ind_status[COL_STATUS_INVALID_C2H_LEN]++;
++	} else {
++		BT_PrintData(Adapter, "[COL], c2h indication:", length, tmpBuf);
++
++		p_c2h_ind = (PCOL_C2H_IND)tmpBuf;
++		ind_type = p_c2h_ind->type;
++		ind_version = p_c2h_ind->version;
++		ind_length = p_c2h_ind->length;
++
++		_rtw_memmove(&gl_coex_offload.c2h_ind_buf[0], tmpBuf, length);
++		gl_coex_offload.c2h_ind_len = length;
++
++		/* log */
++		gl_coex_offload.c2h_ind_record[ind_type].count++;
++		gl_coex_offload.c2h_ind_record[ind_type].status[COL_STATUS_C2H_OK]++;
++		_rtw_memmove(&gl_coex_offload.c2h_ind_record[ind_type].ind_buf[0], tmpBuf, length);
++		gl_coex_offload.c2h_ind_record[ind_type].ind_len = length;
++
++		gl_coex_offload.c2h_ind_status[COL_STATUS_C2H_OK]++;
++		/*TODO: need to check c2h indication length*/
++		/* TODO: Notification */
++	}
++}
++
++void BT_CoexOffloadC2hCheck(PADAPTER Adapter, u8 *Buffer, u8 Length)
++{
++#if 0 /*(USE_HAL_MAC_API == 1)*/
++	u8	c2hSubCmdId = 0, c2hAckLen = 0, h2cCmdId = 0, h2cSubCmdId = 0, c2hIndLen = 0;
++
++	BT_PrintData(Adapter, "[COL], c2h packet:", Length - 2, Buffer + 2);
++	c2hSubCmdId = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(Buffer);
++
++	if (c2hSubCmdId == C2H_SUB_CMD_ID_H2C_ACK_HDR ||
++	    c2hSubCmdId == C2H_SUB_CMD_ID_BT_COEX_INFO) {
++		if (c2hSubCmdId == C2H_SUB_CMD_ID_H2C_ACK_HDR) {
++			/* coex c2h ack */
++			h2cCmdId = (u8)H2C_ACK_HDR_GET_H2C_CMD_ID(Buffer);
++			h2cSubCmdId = (u8)H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(Buffer);
++			if (h2cCmdId == 0xff && h2cSubCmdId == 0x60) {
++				c2hAckLen = (u8)C2H_HDR_GET_LEN(Buffer);
++				if (c2hAckLen >= 8)
++					BT_CoexOffloadC2hAckCheck(Adapter, &Buffer[12], (u8)(c2hAckLen - 8));
++				else
++					BT_CoexOffloadRecordErrC2hAck(Adapter);
++			}
++		} else if (c2hSubCmdId == C2H_SUB_CMD_ID_BT_COEX_INFO) {
++			/* coex c2h indication */
++			c2hIndLen = (u8)C2H_HDR_GET_LEN(Buffer);
++			BT_CoexOffloadC2hIndCheck(Adapter, &Buffer[4], (u8)c2hIndLen);
++		}
++	}
++#endif
++}
++#endif
++
++/* ************************************
++ *		Extern functions called by other module
++ * ************************************ */
++u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter)
++{
++	PBTC_COEXIST		pBtCoexist = &GLBtCoexist;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA((PADAPTER)padapter);
++
++	if (pBtCoexist->bBinded)
++		return _FALSE;
++	else
++		pBtCoexist->bBinded = _TRUE;
++
++	pBtCoexist->statistics.cnt_bind++;
++
++	pBtCoexist->Adapter = padapter;
++	pBtCoexist->odm_priv = (void *)&(pHalData->odmpriv);
++
++	pBtCoexist->stack_info.profile_notified = _FALSE;
++
++	pBtCoexist->bt_info.bt_ctrl_agg_buf_size = _FALSE;
++	pBtCoexist->bt_info.agg_buf_size = 5;
++
++	pBtCoexist->bt_info.increase_scan_dev_num = _FALSE;
++	pBtCoexist->bt_info.miracast_plus_bt = _FALSE;
++
++	/* for btc common architecture, inform chip type to coex. mechanism */
++	if(IS_HARDWARE_TYPE_8822C(padapter)) {
++#ifdef CONFIG_RTL8822C
++		pBtCoexist->chip_type = BTC_CHIP_RTL8822C;
++		pBtCoexist->chip_para = &btc_chip_para_8822c;
++#endif
++	}
++#ifdef CONFIG_RTL8192F
++	else if (IS_HARDWARE_TYPE_8192F(padapter)) {
++		pBtCoexist->chip_type = BTC_CHIP_RTL8725A;
++		pBtCoexist->chip_para = &btc_chip_para_8192f;
++	}
++#endif
++	else {
++		pBtCoexist->chip_type = BTC_CHIP_UNDEF;
++		pBtCoexist->chip_para = NULL;
++	}
++
++	return _TRUE;
++}
++
++void EXhalbtcoutsrc_AntInfoSetting(void *padapter)
++{
++	PBTC_COEXIST		pBtCoexist = &GLBtCoexist;
++	u8	antNum = 1, singleAntPath = 0;
++
++	antNum = rtw_btcoex_get_pg_ant_num((PADAPTER)padapter);
++	EXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_PG, antNum);
++
++	if (antNum == 1) {
++		singleAntPath = rtw_btcoex_get_pg_single_ant_path((PADAPTER)padapter);
++		EXhalbtcoutsrc_SetSingleAntPath(singleAntPath);
++	}
++
++	pBtCoexist->board_info.customerID = RT_CID_DEFAULT;
++	pBtCoexist->board_info.customer_id = RT_CID_DEFAULT;
++
++	/* set default antenna position to main  port */
++	pBtCoexist->board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
++
++	pBtCoexist->board_info.btdm_ant_det_finish = _FALSE;
++	pBtCoexist->board_info.btdm_ant_num_by_ant_det = 1;
++
++	pBtCoexist->board_info.tfbga_package = rtw_btcoex_is_tfbga_package_type((PADAPTER)padapter);
++
++	pBtCoexist->board_info.rfe_type = rtw_btcoex_get_pg_rfe_type((PADAPTER)padapter);
++
++	pBtCoexist->board_info.ant_div_cfg = rtw_btcoex_get_ant_div_cfg((PADAPTER)padapter);
++
++	pBtCoexist->board_info.ant_distance = 10;
++}
++
++u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter)
++{
++	PBTC_COEXIST pBtCoexist = &GLBtCoexist;
++
++	/* pBtCoexist->statistics.cntBind++; */
++
++	halbtcoutsrc_DbgInit();
++
++	halbtcoutsrc_coex_offload_init();
++
++#ifdef CONFIG_PCI_HCI
++	pBtCoexist->chip_interface = BTC_INTF_PCI;
++#elif defined(CONFIG_USB_HCI)
++	pBtCoexist->chip_interface = BTC_INTF_USB;
++#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	pBtCoexist->chip_interface = BTC_INTF_SDIO;
++#else
++	pBtCoexist->chip_interface = BTC_INTF_UNKNOWN;
++#endif
++
++	EXhalbtcoutsrc_BindBtCoexWithAdapter(padapter);
++
++	pBtCoexist->btc_read_1byte = halbtcoutsrc_Read1Byte;
++	pBtCoexist->btc_write_1byte = halbtcoutsrc_Write1Byte;
++	pBtCoexist->btc_write_1byte_bitmask = halbtcoutsrc_BitMaskWrite1Byte;
++	pBtCoexist->btc_read_2byte = halbtcoutsrc_Read2Byte;
++	pBtCoexist->btc_write_2byte = halbtcoutsrc_Write2Byte;
++	pBtCoexist->btc_read_4byte = halbtcoutsrc_Read4Byte;
++	pBtCoexist->btc_write_4byte = halbtcoutsrc_Write4Byte;
++	pBtCoexist->btc_write_local_reg_1byte = halbtcoutsrc_WriteLocalReg1Byte;
++
++	pBtCoexist->btc_read_linderct = halbtcoutsrc_ReadLIndirectReg;
++	pBtCoexist->btc_write_linderct = halbtcoutsrc_WriteLIndirectReg;
++
++	pBtCoexist->btc_read_scbd = halbtcoutsrc_Read_scbd;
++	pBtCoexist->btc_write_scbd = halbtcoutsrc_Write_scbd;
++
++	pBtCoexist->btc_set_bb_reg = halbtcoutsrc_SetBbReg;
++	pBtCoexist->btc_get_bb_reg = halbtcoutsrc_GetBbReg;
++
++	pBtCoexist->btc_set_rf_reg = halbtcoutsrc_SetRfReg;
++	pBtCoexist->btc_get_rf_reg = halbtcoutsrc_GetRfReg;
++
++	pBtCoexist->btc_fill_h2c = halbtcoutsrc_FillH2cCmd;
++	pBtCoexist->btc_disp_dbg_msg = halbtcoutsrc_DisplayDbgMsg;
++
++	pBtCoexist->btc_get = halbtcoutsrc_Get;
++	pBtCoexist->btc_set = halbtcoutsrc_Set;
++	pBtCoexist->btc_get_bt_reg = halbtcoutsrc_GetBtReg;
++	pBtCoexist->btc_set_bt_reg = halbtcoutsrc_SetBtReg;
++	pBtCoexist->btc_set_bt_ant_detection = halbtcoutsrc_SetBtAntDetection;
++	pBtCoexist->btc_set_bt_trx_mask = halbtcoutsrc_SetBtTRXMASK;
++	pBtCoexist->btc_coex_h2c_process = halbtcoutsrc_CoexH2cProcess;
++	pBtCoexist->btc_get_bt_coex_supported_feature = halbtcoutsrc_GetBtCoexSupportedFeature;
++	pBtCoexist->btc_get_bt_coex_supported_version= halbtcoutsrc_GetBtCoexSupportedVersion;
++	pBtCoexist->btc_get_ant_det_val_from_bt = halbtcoutsrc_GetAntDetValFromBt;
++	pBtCoexist->btc_get_ble_scan_type_from_bt = halbtcoutsrc_GetBleScanTypeFromBt;
++	pBtCoexist->btc_get_ble_scan_para_from_bt = halbtcoutsrc_GetBleScanParaFromBt;
++	pBtCoexist->btc_get_bt_afh_map_from_bt = halbtcoutsrc_GetBtAFHMapFromBt;
++	pBtCoexist->btc_get_bt_phydm_version = halbtcoutsrc_GetPhydmVersion;
++	pBtCoexist->btc_set_timer = halbtcoutsrc_SetTimer;
++	pBtCoexist->btc_set_atomic= halbtcoutsrc_SetAtomic;
++	pBtCoexist->btc_phydm_modify_RA_PCR_threshold = halbtcoutsrc_phydm_modify_RA_PCR_threshold;
++	pBtCoexist->btc_phydm_query_PHY_counter = halbtcoutsrc_phydm_query_PHY_counter;
++	pBtCoexist->btc_reduce_wl_tx_power = halbtcoutsrc_reduce_wl_tx_power;
++	pBtCoexist->btc_phydm_modify_antdiv_hwsw = halbtcoutsrc_phydm_modify_AntDiv_HwSw;
++
++	pBtCoexist->cli_buf = &GLBtcDbgBuf[0];
++
++	GLBtcWiFiInScanState = _FALSE;
++
++	GLBtcWiFiInIQKState = _FALSE;
++
++	GLBtcWiFiInIPS = _FALSE;
++
++	GLBtcWiFiInLPS = _FALSE;
++
++	GLBtcBtCoexAliveRegistered = _FALSE;
++
++	/* BT Control H2C/C2H*/
++	GLBtcBtMpOperSeq = 0;
++	_rtw_mutex_init(&GLBtcBtMpOperLock);
++	rtw_init_timer(&GLBtcBtMpOperTimer, padapter, _btmpoper_timer_hdl, pBtCoexist);
++	_rtw_init_sema(&GLBtcBtMpRptSema, 0);
++	GLBtcBtMpRptSeq = 0;
++	GLBtcBtMpRptStatus = 0;
++	_rtw_memset(GLBtcBtMpRptRsp, 0, C2H_MAX_SIZE);
++	GLBtcBtMpRptRspSize = 0;
++	GLBtcBtMpRptWait = _FALSE;
++	GLBtcBtMpRptWiFiOK = _FALSE;
++	GLBtcBtMpRptBTOK = _FALSE;
++
++	return _TRUE;
++}
++
++void EXhalbtcoutsrc_PowerOnSetting(PBTC_COEXIST pBtCoexist)
++{
++	HAL_DATA_TYPE	*pHalData = NULL;
++
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	pHalData = GET_HAL_DATA((PADAPTER)pBtCoexist->Adapter);
++
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	rtw_btc_ex_power_on_setting(pBtCoexist);
++
++#else
++	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8723B
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723b2ant_power_on_setting(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_power_on_setting(pBtCoexist);
++#endif
++	}
++
++#ifdef CONFIG_RTL8703B
++	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8703b1ant_power_on_setting(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_power_on_setting(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_power_on_setting(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821A
++	else if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821a1ant_power_on_setting(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821a2ant_power_on_setting(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8822B
++	else if ((IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8822b1ant_power_on_setting(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8822b2ant_power_on_setting(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if ((IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_power_on_setting(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_power_on_setting(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8814A
++	if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8814a2ant_power_on_setting(pBtCoexist);
++		/* else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8814a1ant_power_on_setting(pBtCoexist); */
++	}
++#endif
++
++#endif
++}
++
++void EXhalbtcoutsrc_PreLoadFirmware(PBTC_COEXIST pBtCoexist)
++{
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	pBtCoexist->statistics.cnt_pre_load_firmware++;
++
++	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8723B
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723b2ant_pre_load_firmware(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_pre_load_firmware(pBtCoexist);
++#endif
++	}
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_pre_load_firmware(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_pre_load_firmware(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_pre_load_firmware(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_pre_load_firmware(pBtCoexist);
++	}
++#endif
++}
++
++void EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly)
++{
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	pBtCoexist->statistics.cnt_init_hw_config++;
++
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	rtw_btc_ex_init_hw_config(pBtCoexist, bWifiOnly);
++#else
++
++	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8821A
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821a2ant_init_hw_config(pBtCoexist, bWifiOnly);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821a1ant_init_hw_config(pBtCoexist, bWifiOnly);
++#endif
++	}
++
++#ifdef CONFIG_RTL8723B
++	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723b2ant_init_hw_config(pBtCoexist, bWifiOnly);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_init_hw_config(pBtCoexist, bWifiOnly);
++	}
++#endif
++
++#ifdef CONFIG_RTL8703B
++	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8703b1ant_init_hw_config(pBtCoexist, bWifiOnly);
++	}
++#endif
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_init_hw_config(pBtCoexist, bWifiOnly);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_init_hw_config(pBtCoexist, bWifiOnly);
++	}
++#endif
++
++#ifdef CONFIG_RTL8192E
++	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8192e2ant_init_hw_config(pBtCoexist, bWifiOnly);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8192e1ant_init_hw_config(pBtCoexist, bWifiOnly);
++	}
++#endif
++
++#ifdef CONFIG_RTL8812A
++	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8812a2ant_init_hw_config(pBtCoexist, bWifiOnly);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8812a1ant_init_hw_config(pBtCoexist, bWifiOnly);
++	}
++#endif
++
++#ifdef CONFIG_RTL8822B
++	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8822b1ant_init_hw_config(pBtCoexist, bWifiOnly);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8822b2ant_init_hw_config(pBtCoexist, bWifiOnly);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_init_hw_config(pBtCoexist, bWifiOnly);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_init_hw_config(pBtCoexist, bWifiOnly);
++	}
++#endif
++
++#ifdef CONFIG_RTL8814A
++	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8814a2ant_init_hw_config(pBtCoexist, bWifiOnly);
++	}
++#endif
++
++#endif
++}
++
++void EXhalbtcoutsrc_init_coex_dm(PBTC_COEXIST pBtCoexist)
++{
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	pBtCoexist->statistics.cnt_init_coex_dm++;
++
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	rtw_btc_ex_init_coex_dm(pBtCoexist);
++#else
++
++	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8821A
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821a2ant_init_coex_dm(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821a1ant_init_coex_dm(pBtCoexist);
++#endif
++	}
++
++#ifdef CONFIG_RTL8723B
++	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723b2ant_init_coex_dm(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_init_coex_dm(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8703B
++	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8703b1ant_init_coex_dm(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_init_coex_dm(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_init_coex_dm(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8192E
++	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8192e2ant_init_coex_dm(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8192e1ant_init_coex_dm(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8812A
++	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8812a2ant_init_coex_dm(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8812a1ant_init_coex_dm(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8822B
++	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8822b1ant_init_coex_dm(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8822b2ant_init_coex_dm(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_init_coex_dm(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_init_coex_dm(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8814A
++	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8814a2ant_init_coex_dm(pBtCoexist);
++	}
++#endif
++
++#endif
++
++	pBtCoexist->initilized = _TRUE;
++}
++
++void EXhalbtcoutsrc_ips_notify(PBTC_COEXIST pBtCoexist, u8 type)
++{
++	u8	ipsType;
++
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	pBtCoexist->statistics.cnt_ips_notify++;
++	if (pBtCoexist->manual_control)
++		return;
++
++	if (IPS_NONE == type) {
++		ipsType = BTC_IPS_LEAVE;
++		GLBtcWiFiInIPS = _FALSE;
++	} else {
++		ipsType = BTC_IPS_ENTER;
++		GLBtcWiFiInIPS = _TRUE;
++	}
++
++	/* All notify is called in cmd thread, don't need to leave low power again
++	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
++
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	rtw_btc_ex_ips_notify(pBtCoexist, ipsType);
++#else
++
++	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8821A
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821a2ant_ips_notify(pBtCoexist, ipsType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821a1ant_ips_notify(pBtCoexist, ipsType);
++#endif
++	}
++
++#ifdef CONFIG_RTL8723B
++	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723b2ant_ips_notify(pBtCoexist, ipsType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_ips_notify(pBtCoexist, ipsType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8703B
++	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8703b1ant_ips_notify(pBtCoexist, ipsType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_ips_notify(pBtCoexist, ipsType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_ips_notify(pBtCoexist, ipsType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8192E
++	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8192e2ant_ips_notify(pBtCoexist, ipsType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8192e1ant_ips_notify(pBtCoexist, ipsType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8812A
++	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8812a2ant_ips_notify(pBtCoexist, ipsType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8812a1ant_ips_notify(pBtCoexist, ipsType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8822B
++	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8822b1ant_ips_notify(pBtCoexist, ipsType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8822b2ant_ips_notify(pBtCoexist, ipsType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_ips_notify(pBtCoexist, ipsType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_ips_notify(pBtCoexist, ipsType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8814A
++	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8814a2ant_ips_notify(pBtCoexist, ipsType);
++	}
++#endif
++
++#endif
++	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
++}
++
++void EXhalbtcoutsrc_lps_notify(PBTC_COEXIST pBtCoexist, u8 type)
++{
++	u8 lpsType;
++
++
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	pBtCoexist->statistics.cnt_lps_notify++;
++	if (pBtCoexist->manual_control)
++		return;
++
++	if (PS_MODE_ACTIVE == type) {
++		lpsType = BTC_LPS_DISABLE;
++		GLBtcWiFiInLPS = _FALSE;
++	} else {
++		lpsType = BTC_LPS_ENABLE;
++		GLBtcWiFiInLPS = _TRUE;
++	}
++
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	rtw_btc_ex_lps_notify(pBtCoexist, lpsType);
++#else
++
++	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8821A
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821a2ant_lps_notify(pBtCoexist, lpsType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821a1ant_lps_notify(pBtCoexist, lpsType);
++#endif
++	}
++
++#ifdef CONFIG_RTL8723B
++	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723b2ant_lps_notify(pBtCoexist, lpsType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_lps_notify(pBtCoexist, lpsType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8703B
++	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8703b1ant_lps_notify(pBtCoexist, lpsType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_lps_notify(pBtCoexist, lpsType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_lps_notify(pBtCoexist, lpsType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8192E
++	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8192e2ant_lps_notify(pBtCoexist, lpsType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8192e1ant_lps_notify(pBtCoexist, lpsType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8812A
++	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8812a2ant_lps_notify(pBtCoexist, lpsType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8812a1ant_lps_notify(pBtCoexist, lpsType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8822B
++	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8822b1ant_lps_notify(pBtCoexist, lpsType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8822b2ant_lps_notify(pBtCoexist, lpsType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_lps_notify(pBtCoexist, lpsType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_lps_notify(pBtCoexist, lpsType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8814A
++	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8814a2ant_lps_notify(pBtCoexist, lpsType);
++	}
++#endif
++
++#endif
++}
++
++void EXhalbtcoutsrc_scan_notify(PBTC_COEXIST pBtCoexist, u8 type)
++{
++	u8	scanType;
++
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++	pBtCoexist->statistics.cnt_scan_notify++;
++	if (pBtCoexist->manual_control)
++		return;
++
++	if (type) {
++		scanType = BTC_SCAN_START;
++		GLBtcWiFiInScanState = _TRUE;
++	} else {
++		scanType = BTC_SCAN_FINISH;
++		GLBtcWiFiInScanState = _FALSE;
++	}
++
++	/* All notify is called in cmd thread, don't need to leave low power again
++	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
++
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	rtw_btc_ex_scan_notify(pBtCoexist, scanType);
++#else
++
++	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8821A
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821a2ant_scan_notify(pBtCoexist, scanType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821a1ant_scan_notify(pBtCoexist, scanType);
++#endif
++	}
++
++#ifdef CONFIG_RTL8723B
++	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723b2ant_scan_notify(pBtCoexist, scanType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_scan_notify(pBtCoexist, scanType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8703B
++	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8703b1ant_scan_notify(pBtCoexist, scanType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_scan_notify(pBtCoexist, scanType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_scan_notify(pBtCoexist, scanType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8192E
++	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8192e2ant_scan_notify(pBtCoexist, scanType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8192e1ant_scan_notify(pBtCoexist, scanType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8812A
++	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8812a2ant_scan_notify(pBtCoexist, scanType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8812a1ant_scan_notify(pBtCoexist, scanType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8822B
++	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8822b1ant_scan_notify(pBtCoexist, scanType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8822b2ant_scan_notify(pBtCoexist, scanType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_scan_notify(pBtCoexist, scanType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_scan_notify(pBtCoexist, scanType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8814A
++	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8814a2ant_scan_notify(pBtCoexist, scanType);
++	}
++#endif
++
++#endif
++
++	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
++}
++
++void EXhalbtcoutsrc_SetAntennaPathNotify(PBTC_COEXIST pBtCoexist, u8 type)
++{
++#if 0
++	u8	switchType;
++
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	if (pBtCoexist->manual_control)
++		return;
++
++	halbtcoutsrc_LeaveLowPower(pBtCoexist);
++
++	switchType = type;
++
++	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_set_antenna_notify(pBtCoexist, type);
++	}
++	if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_set_antenna_notify(pBtCoexist, type);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_set_antenna_notify(pBtCoexist, type);
++	}
++
++	halbtcoutsrc_NormalLowPower(pBtCoexist);
++#endif
++}
++
++void EXhalbtcoutsrc_connect_notify(PBTC_COEXIST pBtCoexist, u8 assoType)
++{
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++	pBtCoexist->statistics.cnt_connect_notify++;
++	if (pBtCoexist->manual_control)
++		return;
++	
++	/* All notify is called in cmd thread, don't need to leave low power again
++	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	rtw_btc_ex_connect_notify(pBtCoexist, assoType);
++#else
++
++	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8821A
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821a2ant_connect_notify(pBtCoexist, assoType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821a1ant_connect_notify(pBtCoexist, assoType);
++#endif
++	}
++
++#ifdef CONFIG_RTL8723B
++	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723b2ant_connect_notify(pBtCoexist, assoType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_connect_notify(pBtCoexist, assoType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8703B
++	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8703b1ant_connect_notify(pBtCoexist, assoType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_connect_notify(pBtCoexist, assoType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_connect_notify(pBtCoexist, assoType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8192E
++	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8192e2ant_connect_notify(pBtCoexist, assoType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8192e1ant_connect_notify(pBtCoexist, assoType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8812A
++	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8812a2ant_connect_notify(pBtCoexist, assoType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8812a1ant_connect_notify(pBtCoexist, assoType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8822B
++	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8822b1ant_connect_notify(pBtCoexist, assoType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8822b2ant_connect_notify(pBtCoexist, assoType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_connect_notify(pBtCoexist, assoType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_connect_notify(pBtCoexist, assoType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8814A
++	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8814a2ant_connect_notify(pBtCoexist, assoType);
++	}
++#endif
++
++#endif
++
++	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
++}
++
++void EXhalbtcoutsrc_media_status_notify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS mediaStatus)
++{
++	u8 mStatus = BTC_MEDIA_MAX;
++	PADAPTER adapter = NULL;
++	HAL_DATA_TYPE *hal = NULL;
++
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	if (pBtCoexist->manual_control)
++		return;
++
++	pBtCoexist->statistics.cnt_media_status_notify++;
++	adapter = (PADAPTER)pBtCoexist->Adapter;
++	hal = GET_HAL_DATA(adapter);
++
++	if (RT_MEDIA_CONNECT == mediaStatus) {
++		if (hal->current_band_type == BAND_ON_2_4G)
++			mStatus = BTC_MEDIA_CONNECT;
++		else if (hal->current_band_type == BAND_ON_5G)
++			mStatus = BTC_MEDIA_CONNECT_5G;
++		else {
++			mStatus = BTC_MEDIA_CONNECT;
++			RTW_ERR("%s unknow band type\n", __func__);
++		}
++	} else
++		mStatus = BTC_MEDIA_DISCONNECT;
++
++	/* All notify is called in cmd thread, don't need to leave low power again
++	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	rtw_btc_ex_media_status_notify(pBtCoexist, mStatus);
++#else
++
++	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8821A
++		/* compatible for 8821A */
++		if (mStatus == BTC_MEDIA_CONNECT_5G)
++			mStatus = BTC_MEDIA_CONNECT;
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821a2ant_media_status_notify(pBtCoexist, mStatus);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821a1ant_media_status_notify(pBtCoexist, mStatus);
++#endif
++	}
++
++#ifdef CONFIG_RTL8723B
++	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723b2ant_media_status_notify(pBtCoexist, mStatus);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_media_status_notify(pBtCoexist, mStatus);
++	}
++#endif
++
++#ifdef CONFIG_RTL8703B
++	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8703b1ant_media_status_notify(pBtCoexist, mStatus);
++	}
++#endif
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_media_status_notify(pBtCoexist, mStatus);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_media_status_notify(pBtCoexist, mStatus);
++	}
++#endif
++
++#ifdef CONFIG_RTL8192E
++	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8192e2ant_media_status_notify(pBtCoexist, mStatus);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8192e1ant_media_status_notify(pBtCoexist, mStatus);
++	}
++#endif
++
++#ifdef CONFIG_RTL8812A
++	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
++		/* compatible for 8812A */
++		if (mStatus == BTC_MEDIA_CONNECT_5G)
++			mStatus = BTC_MEDIA_CONNECT;
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8812a2ant_media_status_notify(pBtCoexist, mStatus);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8812a1ant_media_status_notify(pBtCoexist, mStatus);
++	}
++#endif
++
++#ifdef CONFIG_RTL8822B
++	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8822b1ant_media_status_notify(pBtCoexist, mStatus);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8822b2ant_media_status_notify(pBtCoexist, mStatus);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_media_status_notify(pBtCoexist, mStatus);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_media_status_notify(pBtCoexist, mStatus);
++	}
++#endif
++
++#ifdef CONFIG_RTL8814A
++	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8814a2ant_media_status_notify(pBtCoexist, mStatus);
++	}
++#endif
++
++#endif
++
++	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
++}
++
++void EXhalbtcoutsrc_specific_packet_notify(PBTC_COEXIST pBtCoexist, u8 pktType)
++{
++	u8 packetType;
++	PADAPTER adapter = NULL;
++	HAL_DATA_TYPE *hal = NULL;
++
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++	
++	if (pBtCoexist->manual_control)
++		return;
++
++	pBtCoexist->statistics.cnt_specific_packet_notify++;
++	adapter = (PADAPTER)pBtCoexist->Adapter;
++	hal = GET_HAL_DATA(adapter);
++
++	if (PACKET_DHCP == pktType)
++		packetType = BTC_PACKET_DHCP;
++	else if (PACKET_EAPOL == pktType)
++		packetType = BTC_PACKET_EAPOL;
++	else if (PACKET_ARP == pktType)
++		packetType = BTC_PACKET_ARP;
++	else {
++		packetType = BTC_PACKET_UNKNOWN;
++		return;
++	}
++
++	if (hal->current_band_type == BAND_ON_5G)
++		packetType |=  BTC_5G_BAND;
++
++	/* All notify is called in cmd thread, don't need to leave low power again
++	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	rtw_btc_ex_specific_packet_notify(pBtCoexist, packetType);
++#else
++
++	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8821A
++		/* compatible for 8821A */
++		if (hal->current_band_type == BAND_ON_5G)
++			packetType &= ~BTC_5G_BAND;
++
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821a2ant_specific_packet_notify(pBtCoexist, packetType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821a1ant_specific_packet_notify(pBtCoexist, packetType);
++#endif
++	}
++
++#ifdef CONFIG_RTL8723B
++	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723b2ant_specific_packet_notify(pBtCoexist, packetType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_specific_packet_notify(pBtCoexist, packetType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8703B
++	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8703b1ant_specific_packet_notify(pBtCoexist, packetType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_specific_packet_notify(pBtCoexist, packetType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_specific_packet_notify(pBtCoexist, packetType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8192E
++	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8192e2ant_specific_packet_notify(pBtCoexist, packetType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8192e1ant_specific_packet_notify(pBtCoexist, packetType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8812A
++	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
++		/* compatible for 8812A */
++		if (hal->current_band_type == BAND_ON_5G)
++			packetType &= ~BTC_5G_BAND;
++		
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8812a2ant_specific_packet_notify(pBtCoexist, packetType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8812a1ant_specific_packet_notify(pBtCoexist, packetType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8822B
++	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8822b1ant_specific_packet_notify(pBtCoexist, packetType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8822b2ant_specific_packet_notify(pBtCoexist, packetType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_specific_packet_notify(pBtCoexist, packetType);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_specific_packet_notify(pBtCoexist, packetType);
++	}
++#endif
++
++#ifdef CONFIG_RTL8814A
++	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8814a2ant_specific_packet_notify(pBtCoexist, packetType);
++	}
++#endif
++
++#endif
++
++	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
++}
++
++void EXhalbtcoutsrc_bt_info_notify(PBTC_COEXIST pBtCoexist, u8 *tmpBuf, u8 length)
++{
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	pBtCoexist->statistics.cnt_bt_info_notify++;
++
++	/* All notify is called in cmd thread, don't need to leave low power again
++	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	rtw_btc_ex_bt_info_notify(pBtCoexist, tmpBuf, length);
++#else
++
++	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8821A
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821a2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821a1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
++#endif
++	}
++
++#ifdef CONFIG_RTL8723B
++	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723b2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
++	}
++#endif
++
++#ifdef CONFIG_RTL8703B
++	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8703b1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
++	}
++#endif
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
++	}
++#endif
++
++#ifdef CONFIG_RTL8192E
++	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8192e2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8192e1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
++	}
++#endif
++
++#ifdef CONFIG_RTL8812A
++	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8812a2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8812a1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
++	}
++#endif
++
++#ifdef CONFIG_RTL8822B
++	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8822b1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8822b2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
++	}
++#endif
++
++#ifdef CONFIG_RTL8814A
++	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8814a2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
++	}
++#endif
++
++#endif
++
++	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
++}
++
++void EXhalbtcoutsrc_WlFwDbgInfoNotify(PBTC_COEXIST pBtCoexist, u8* tmpBuf, u8 length)
++{
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	rtw_btc_ex_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
++#else
++
++	if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8703B
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8703b1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
++#endif
++	}
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
++	}
++#endif
++
++#endif
++}
++
++void EXhalbtcoutsrc_rx_rate_change_notify(PBTC_COEXIST pBtCoexist, u8 is_data_frame, u8 btc_rate_id)
++{
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	pBtCoexist->statistics.cnt_rate_id_notify++;
++
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	rtw_btc_ex_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
++#else
++
++	if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8703B
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8703b1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
++#endif
++	}
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
++	}
++#endif
++
++#endif
++}
++
++void
++EXhalbtcoutsrc_RfStatusNotify(
++		PBTC_COEXIST		pBtCoexist,
++		u8				type
++)
++{
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++	pBtCoexist->statistics.cnt_rf_status_notify++;
++
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	rtw_btc_ex_rf_status_notify(pBtCoexist, type);
++#else
++
++	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8723B
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_rf_status_notify(pBtCoexist, type);
++#endif
++	}
++
++#ifdef CONFIG_RTL8703B
++	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8703b1ant_rf_status_notify(pBtCoexist, type);
++	}
++#endif
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_rf_status_notify(pBtCoexist, type);
++	}
++#endif
++
++#ifdef CONFIG_RTL8822B
++	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8822b1ant_rf_status_notify(pBtCoexist, type);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8822b2ant_rf_status_notify(pBtCoexist, type);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_rf_status_notify(pBtCoexist, type);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_rf_status_notify(pBtCoexist, type);
++	}
++#endif
++
++#ifdef CONFIG_RTL8814A
++	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8814a2ant_rf_status_notify(pBtCoexist, type);
++	}
++#endif
++
++#endif
++}
++
++void EXhalbtcoutsrc_StackOperationNotify(PBTC_COEXIST pBtCoexist, u8 type)
++{
++#if 0
++	u8	stackOpType;
++
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++	pBtCoexist->statistics.cntStackOperationNotify++;
++	if (pBtCoexist->manual_control)
++		return;
++
++	if ((HCI_BT_OP_INQUIRY_START == type) ||
++	    (HCI_BT_OP_PAGING_START == type) ||
++	    (HCI_BT_OP_PAIRING_START == type))
++		stackOpType = BTC_STACK_OP_INQ_PAGE_PAIR_START;
++	else if ((HCI_BT_OP_INQUIRY_FINISH == type) ||
++		 (HCI_BT_OP_PAGING_SUCCESS == type) ||
++		 (HCI_BT_OP_PAGING_UNSUCCESS == type) ||
++		 (HCI_BT_OP_PAIRING_FINISH == type))
++		stackOpType = BTC_STACK_OP_INQ_PAGE_PAIR_FINISH;
++	else
++		stackOpType = BTC_STACK_OP_NONE;
++
++#endif
++}
++
++void EXhalbtcoutsrc_halt_notify(PBTC_COEXIST pBtCoexist)
++{
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	pBtCoexist->statistics.cnt_halt_notify++;
++
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	rtw_btc_ex_halt_notify(pBtCoexist);
++#else
++
++	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8821A
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821a2ant_halt_notify(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821a1ant_halt_notify(pBtCoexist);
++#endif
++	}
++
++#ifdef CONFIG_RTL8723B
++	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723b2ant_halt_notify(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_halt_notify(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8703B
++	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8703b1ant_halt_notify(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_halt_notify(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_halt_notify(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8192E
++	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8192e2ant_halt_notify(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8192e1ant_halt_notify(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8812A
++	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8812a2ant_halt_notify(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8812a1ant_halt_notify(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8822B
++	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8822b1ant_halt_notify(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8822b2ant_halt_notify(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_halt_notify(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_halt_notify(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8814A
++	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8814a2ant_halt_notify(pBtCoexist);
++	}
++#endif
++
++#endif
++}
++
++void EXhalbtcoutsrc_SwitchBtTRxMask(PBTC_COEXIST pBtCoexist)
++{
++	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2) {
++			halbtcoutsrc_SetBtReg(pBtCoexist, 0, 0x3c, 0x01); /* BT goto standby while GNT_BT 1-->0 */
++		} else if (pBtCoexist->board_info.btdm_ant_num == 1) {
++			halbtcoutsrc_SetBtReg(pBtCoexist, 0, 0x3c, 0x15); /* BT goto standby while GNT_BT 1-->0 */
++		}
++	}
++}
++
++void EXhalbtcoutsrc_pnp_notify(PBTC_COEXIST pBtCoexist, u8 pnpState)
++{
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	pBtCoexist->statistics.cnt_pnp_notify++;
++
++	/*  */
++	/* currently only 1ant we have to do the notification, */
++	/* once pnp is notified to sleep state, we have to leave LPS that we can sleep normally. */
++	/*  */
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	rtw_btc_ex_pnp_notify(pBtCoexist, pnpState);
++#else
++
++	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8723B
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_pnp_notify(pBtCoexist, pnpState);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723b2ant_pnp_notify(pBtCoexist, pnpState);
++#endif
++	}
++
++#ifdef CONFIG_RTL8703B
++	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8703b1ant_pnp_notify(pBtCoexist, pnpState);
++	}
++#endif
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_pnp_notify(pBtCoexist, pnpState);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_pnp_notify(pBtCoexist, pnpState);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821A
++	else if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821a1ant_pnp_notify(pBtCoexist, pnpState);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821a2ant_pnp_notify(pBtCoexist, pnpState);
++	}
++#endif
++
++#ifdef CONFIG_RTL8192E
++	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8192e1ant_pnp_notify(pBtCoexist, pnpState);
++	}
++#endif
++
++#ifdef CONFIG_RTL8812A
++	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8812a1ant_pnp_notify(pBtCoexist, pnpState);
++	}
++#endif
++
++#ifdef CONFIG_RTL8822B
++	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8822b1ant_pnp_notify(pBtCoexist, pnpState);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8822b2ant_pnp_notify(pBtCoexist, pnpState);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_pnp_notify(pBtCoexist, pnpState);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_pnp_notify(pBtCoexist, pnpState);
++	}
++#endif
++
++#ifdef CONFIG_RTL8814A
++	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8814a2ant_pnp_notify(pBtCoexist, pnpState);
++	}
++#endif
++
++#endif
++}
++
++void EXhalbtcoutsrc_CoexDmSwitch(PBTC_COEXIST pBtCoexist)
++{
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++	pBtCoexist->statistics.cnt_coex_dm_switch++;
++
++	halbtcoutsrc_LeaveLowPower(pBtCoexist);
++
++	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8723B
++		if (pBtCoexist->board_info.btdm_ant_num == 1) {
++			pBtCoexist->stop_coex_dm = TRUE;
++			ex_halbtc8723b1ant_coex_dm_reset(pBtCoexist);
++			EXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_DETECTED, 2);
++			ex_halbtc8723b2ant_init_hw_config(pBtCoexist, FALSE);
++			ex_halbtc8723b2ant_init_coex_dm(pBtCoexist);
++			pBtCoexist->stop_coex_dm = FALSE;
++		}
++#endif
++	}
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1) {
++			pBtCoexist->stop_coex_dm = TRUE;
++			ex_halbtc8723d1ant_coex_dm_reset(pBtCoexist);
++			EXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_DETECTED, 2);
++			ex_halbtc8723d2ant_init_hw_config(pBtCoexist, FALSE);
++			ex_halbtc8723d2ant_init_coex_dm(pBtCoexist);
++			pBtCoexist->stop_coex_dm = FALSE;
++		}
++	}
++#endif
++
++	halbtcoutsrc_NormalLowPower(pBtCoexist);
++}
++
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++void EXhalbtcoutsrc_TimerNotify(PBTC_COEXIST pBtCoexist, u32 timer_type)
++{
++	rtw_btc_ex_timerup_notify(pBtCoexist, timer_type);
++}
++
++void EXhalbtcoutsrc_WLStatusChangeNotify(PBTC_COEXIST pBtCoexist, u32 change_type)
++{
++	rtw_btc_ex_wl_status_change_notify(pBtCoexist, change_type);
++}
++
++u32 EXhalbtcoutsrc_CoexTimerCheck(PBTC_COEXIST pBtCoexist)
++{
++	u32 i, timer_map = 0;
++
++	for (i = 0; i < BTC_TIMER_MAX; i++) {
++		if (pBtCoexist->coex_sta.cnt_timer[i] > 0) {
++			if (pBtCoexist->coex_sta.cnt_timer[i] == 1) {
++				timer_map |= BIT(i);
++				RTW_DBG("[BTC], %s(): timer_map = 0x%x\n", __func__, timer_map);
++			}
++
++			pBtCoexist->coex_sta.cnt_timer[i]--;
++		}
++	}
++
++	return timer_map;
++}
++
++u32 EXhalbtcoutsrc_WLStatusCheck(PBTC_COEXIST pBtCoexist)
++{
++	struct btc_wifi_link_info link_info;
++	const struct btc_chip_para *chip_para = pBtCoexist->chip_para;
++	u32 change_map = 0;
++	static bool wl_busy_pre;
++	bool	wl_busy = _FALSE;
++	s32 wl_rssi;
++	u32 traffic_dir;
++	u8 i, tmp;
++	static u8 rssi_step_pre = 5, wl_noisy_level_pre = 4;
++
++	/* WL busy to idle or idle to busy */
++	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &wl_busy);
++	if (wl_busy != wl_busy_pre) {
++		if (wl_busy)
++			change_map |=  BIT(BTC_WLSTATUS_CHANGE_TOBUSY);
++		else
++			change_map |=  BIT(BTC_WLSTATUS_CHANGE_TOIDLE);
++
++		wl_busy_pre = wl_busy;
++	}
++
++	/* WL RSSI */
++	pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wl_rssi);
++	tmp = (u8)(wl_rssi & 0xff);
++	for (i = 0; i < 4; i++) {
++		if (tmp >= chip_para->wl_rssi_step[i])
++			break;
++	}
++
++	if (rssi_step_pre != i) {
++		rssi_step_pre = i;
++		change_map |=  BIT(BTC_WLSTATUS_CHANGE_RSSI);
++	}
++
++	/* WL Link info */
++	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK_INFO, &link_info);
++	if (link_info.link_mode != pBtCoexist->wifi_link_info.link_mode ||
++	    link_info.sta_center_channel !=
++	    		pBtCoexist->wifi_link_info.sta_center_channel ||
++	    link_info.p2p_center_channel !=
++	    		pBtCoexist->wifi_link_info.p2p_center_channel ||
++	    link_info.bany_client_join_go !=
++	    		pBtCoexist->wifi_link_info.bany_client_join_go) {
++		change_map |=  BIT(BTC_WLSTATUS_CHANGE_LINKINFO);
++		pBtCoexist->wifi_link_info = link_info;
++	}
++
++	/* WL Traffic Direction */
++	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIR, &traffic_dir);
++	if (wl_busy && traffic_dir != pBtCoexist->wifi_link_info_ext.traffic_dir) {
++		change_map |=  BIT(BTC_WLSTATUS_CHANGE_DIR);
++		pBtCoexist->wifi_link_info_ext.traffic_dir = traffic_dir;
++	}
++
++	/* Noisy Detect */
++	if (pBtCoexist->coex_sta.wl_noisy_level != wl_noisy_level_pre) {
++		change_map |=  BIT(BTC_WLSTATUS_CHANGE_NOISY);
++		wl_noisy_level_pre = pBtCoexist->coex_sta.wl_noisy_level;
++	}
++
++	RTW_DBG("[BTC], %s(): change_map = 0x%x\n", __func__, change_map);
++
++	return change_map;
++}
++
++void EXhalbtcoutsrc_status_monitor(PBTC_COEXIST pBtCoexist)
++{
++	u32 timer_up_type = 0, wl_status_change_type = 0;
++
++	timer_up_type = EXhalbtcoutsrc_CoexTimerCheck(pBtCoexist);
++	if (timer_up_type != 0)
++		EXhalbtcoutsrc_TimerNotify(pBtCoexist, timer_up_type);
++
++	wl_status_change_type =  EXhalbtcoutsrc_WLStatusCheck(pBtCoexist);
++	if (wl_status_change_type != 0)
++		EXhalbtcoutsrc_WLStatusChangeNotify(pBtCoexist, wl_status_change_type);
++
++	rtw_btc_ex_periodical(pBtCoexist);
++}
++#endif
++
++void EXhalbtcoutsrc_periodical(PBTC_COEXIST pBtCoexist)
++{
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++	pBtCoexist->statistics.cnt_periodical++;
++
++	/* Periodical should be called in cmd thread, */
++	/* don't need to leave low power again
++	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	EXhalbtcoutsrc_status_monitor(pBtCoexist);
++#else
++
++	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8821A
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821a2ant_periodical(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1) {
++			if (!halbtcoutsrc_UnderIps(pBtCoexist))
++				ex_halbtc8821a1ant_periodical(pBtCoexist);
++		}
++#endif
++	}
++
++#ifdef CONFIG_RTL8723B
++	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723b2ant_periodical(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_periodical(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_periodical(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_periodical(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8703B
++	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8703b1ant_periodical(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8192E
++	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8192e2ant_periodical(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8192e1ant_periodical(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8812A
++	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8812a2ant_periodical(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8812a1ant_periodical(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8822B
++	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8822b1ant_periodical(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8822b2ant_periodical(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_periodical(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_periodical(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8814A
++	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8814a2ant_periodical(pBtCoexist);
++	}
++#endif
++
++#endif
++
++	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
++}
++
++void EXhalbtcoutsrc_dbg_control(PBTC_COEXIST pBtCoexist, u8 opCode, u8 opLen, u8 *pData)
++{
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	pBtCoexist->statistics.cnt_dbg_ctrl++;
++
++	/* This function doesn't be called yet, */
++	/* default no need to leave low power to avoid deadlock
++	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	/* rtw_btc_ex_dbg_control(pBtCoexist, opCode, opLen, pData); */
++#else
++
++	if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8192E
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8192e1ant_dbg_control(pBtCoexist, opCode, opLen, pData);
++#endif
++	}
++
++#ifdef CONFIG_RTL8812A
++	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8812a2ant_dbg_control(pBtCoexist, opCode, opLen, pData);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8812a1ant_dbg_control(pBtCoexist, opCode, opLen, pData);
++	}
++#endif
++
++#ifdef CONFIG_RTL8822B
++	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter))
++		if(pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8822b1ant_dbg_control(pBtCoexist, opCode, opLen, pData);
++#endif
++
++#endif
++
++	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
++}
++
++#if 0
++void
++EXhalbtcoutsrc_AntennaDetection(
++		PBTC_COEXIST			pBtCoexist,
++		u32					centFreq,
++		u32					offset,
++		u32					span,
++		u32					seconds
++)
++{
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	/* Need to refine the following power save operations to enable this function in the future */
++#if 0
++	IPSDisable(pBtCoexist->Adapter, FALSE, 0);
++	LeisurePSLeave(pBtCoexist->Adapter, LPS_DISABLE_BT_COEX);
++#endif
++
++	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_AntennaDetection(pBtCoexist, centFreq, offset, span, seconds);
++	}
++
++	/* IPSReturn(pBtCoexist->Adapter, 0xff); */
++}
++#endif
++
++void EXhalbtcoutsrc_StackUpdateProfileInfo(void)
++{
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++	PBTC_COEXIST pBtCoexist = &GLBtCoexist;
++	PADAPTER padapter = NULL;
++	PBT_MGNT pBtMgnt = NULL;
++	u8 i;
++
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	padapter = (PADAPTER)pBtCoexist->Adapter;
++	pBtMgnt = &padapter->coex_info.BtMgnt;
++
++	pBtCoexist->stack_info.profile_notified = _TRUE;
++
++	pBtCoexist->stack_info.num_of_link =
++		pBtMgnt->ExtConfig.NumberOfACL + pBtMgnt->ExtConfig.NumberOfSCO;
++
++	/* reset first */
++	pBtCoexist->stack_info.bt_link_exist = _FALSE;
++	pBtCoexist->stack_info.sco_exist = _FALSE;
++	pBtCoexist->stack_info.acl_exist = _FALSE;
++	pBtCoexist->stack_info.a2dp_exist = _FALSE;
++	pBtCoexist->stack_info.hid_exist = _FALSE;
++	pBtCoexist->stack_info.num_of_hid = 0;
++	pBtCoexist->stack_info.pan_exist = _FALSE;
++
++	if (!pBtMgnt->ExtConfig.NumberOfACL)
++		pBtCoexist->stack_info.min_bt_rssi = 0;
++
++	if (pBtCoexist->stack_info.num_of_link) {
++		pBtCoexist->stack_info.bt_link_exist = _TRUE;
++		if (pBtMgnt->ExtConfig.NumberOfSCO)
++			pBtCoexist->stack_info.sco_exist = _TRUE;
++		if (pBtMgnt->ExtConfig.NumberOfACL)
++			pBtCoexist->stack_info.acl_exist = _TRUE;
++	}
++
++	for (i = 0; i < pBtMgnt->ExtConfig.NumberOfACL; i++) {
++		if (BT_PROFILE_A2DP == pBtMgnt->ExtConfig.aclLink[i].BTProfile)
++			pBtCoexist->stack_info.a2dp_exist = _TRUE;
++		else if (BT_PROFILE_PAN == pBtMgnt->ExtConfig.aclLink[i].BTProfile)
++			pBtCoexist->stack_info.pan_exist = _TRUE;
++		else if (BT_PROFILE_HID == pBtMgnt->ExtConfig.aclLink[i].BTProfile) {
++			pBtCoexist->stack_info.hid_exist = _TRUE;
++			pBtCoexist->stack_info.num_of_hid++;
++		} else
++			pBtCoexist->stack_info.unknown_acl_exist = _TRUE;
++	}
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++}
++
++void EXhalbtcoutsrc_UpdateMinBtRssi(s8 btRssi)
++{
++	PBTC_COEXIST pBtCoexist = &GLBtCoexist;
++
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	pBtCoexist->stack_info.min_bt_rssi = btRssi;
++}
++
++void EXhalbtcoutsrc_SetHciVersion(u16 hciVersion)
++{
++	PBTC_COEXIST pBtCoexist = &GLBtCoexist;
++
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	pBtCoexist->stack_info.hci_version = hciVersion;
++}
++
++void EXhalbtcoutsrc_SetBtPatchVersion(u16 btHciVersion, u16 btPatchVersion)
++{
++	PBTC_COEXIST pBtCoexist = &GLBtCoexist;
++
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	pBtCoexist->bt_info.bt_real_fw_ver = btPatchVersion;
++	pBtCoexist->bt_info.bt_hci_ver = btHciVersion;
++}
++
++#if 0
++void EXhalbtcoutsrc_SetBtExist(u8 bBtExist)
++{
++	GLBtCoexist.boardInfo.bBtExist = bBtExist;
++}
++#endif
++void EXhalbtcoutsrc_SetChipType(u8 chipType)
++{
++	switch (chipType) {
++	default:
++	case BT_2WIRE:
++	case BT_ISSC_3WIRE:
++	case BT_ACCEL:
++	case BT_RTL8756:
++		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_UNDEF;
++		break;
++	case BT_CSR_BC4:
++		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_CSR_BC4;
++		break;
++	case BT_CSR_BC8:
++		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_CSR_BC8;
++		break;
++	case BT_RTL8723A:
++		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_RTL8723A;
++		break;
++	case BT_RTL8821:
++		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_RTL8821;
++		break;
++	case BT_RTL8723B:
++		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_RTL8723B;
++		break;
++	}
++}
++
++void EXhalbtcoutsrc_SetAntNum(u8 type, u8 antNum)
++{
++	if (BT_COEX_ANT_TYPE_PG == type) {
++		GLBtCoexist.board_info.pg_ant_num = antNum;
++		GLBtCoexist.board_info.btdm_ant_num = antNum;
++#if 0
++		/* The antenna position: Main (default) or Aux for pgAntNum=2 && btdmAntNum =1 */
++		/* The antenna position should be determined by auto-detect mechanism */
++		/* The following is assumed to main, and those must be modified if y auto-detect mechanism is ready */
++		if ((GLBtCoexist.board_info.pg_ant_num == 2) && (GLBtCoexist.board_info.btdm_ant_num == 1))
++			GLBtCoexist.board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
++		else
++			GLBtCoexist.board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
++#endif
++	} else if (BT_COEX_ANT_TYPE_ANTDIV == type) {
++		GLBtCoexist.board_info.btdm_ant_num = antNum;
++		/* GLBtCoexist.boardInfo.btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT;	 */
++	} else if (BT_COEX_ANT_TYPE_DETECTED == type) {
++		GLBtCoexist.board_info.btdm_ant_num = antNum;
++		/* GLBtCoexist.boardInfo.btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; */
++	}
++}
++
++/*
++ * Currently used by 8723b only, S0 or S1
++ *   */
++void EXhalbtcoutsrc_SetSingleAntPath(u8 singleAntPath)
++{
++	GLBtCoexist.board_info.single_ant_path = singleAntPath;
++}
++
++void EXhalbtcoutsrc_DisplayBtCoexInfo(PBTC_COEXIST pBtCoexist)
++{
++	HAL_DATA_TYPE	*pHalData = NULL;
++
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	halbtcoutsrc_LeaveLowPower(pBtCoexist);
++
++	/* To prevent the racing with IPS enter */
++	halbtcoutsrc_EnterPwrLock(pBtCoexist);
++
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	pHalData = GET_HAL_DATA((PADAPTER)pBtCoexist->Adapter);
++
++	if (pHalData->EEPROMBluetoothCoexist == _TRUE)
++		rtw_btc_ex_display_coex_info(pBtCoexist);
++#else
++
++	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8821A
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821a2ant_display_coex_info(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821a1ant_display_coex_info(pBtCoexist);
++#endif
++	}
++
++#ifdef CONFIG_RTL8723B
++	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723b2ant_display_coex_info(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_display_coex_info(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8703B
++	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8703b1ant_display_coex_info(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8723D
++	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8723d2ant_display_coex_info(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723d1ant_display_coex_info(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8192E
++	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8192e2ant_display_coex_info(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8192e1ant_display_coex_info(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8812A
++	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8812a2ant_display_coex_info(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8812a1ant_display_coex_info(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8822B
++	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8822b1ant_display_coex_info(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8822b2ant_display_coex_info(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_display_coex_info(pBtCoexist);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_display_coex_info(pBtCoexist);
++	}
++#endif
++
++#ifdef CONFIG_RTL8814A
++	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8814a2ant_display_coex_info(pBtCoexist);
++	}
++#endif
++
++#endif
++
++	halbtcoutsrc_ExitPwrLock(pBtCoexist);
++
++	halbtcoutsrc_NormalLowPower(pBtCoexist);
++}
++
++void EXhalbtcoutsrc_DisplayAntDetection(PBTC_COEXIST pBtCoexist)
++{
++	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++
++	halbtcoutsrc_LeaveLowPower(pBtCoexist);
++
++	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8723B
++		if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8723b1ant_display_ant_detection(pBtCoexist);
++#endif
++	}
++
++	halbtcoutsrc_NormalLowPower(pBtCoexist);
++}
++
++void ex_halbtcoutsrc_pta_off_on_notify(PBTC_COEXIST pBtCoexist, u8 bBTON)
++{
++	if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8812A
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8812a2ant_pta_off_on_notify(pBtCoexist, (bBTON == _TRUE) ? BTC_BT_ON : BTC_BT_OFF);
++#endif
++	}
++
++#ifdef CONFIG_RTL8814A
++	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8814a2ant_pta_off_on_notify(pBtCoexist, (bBTON == _TRUE) ? BTC_BT_ON : BTC_BT_OFF);
++	}
++#endif
++}
++
++void EXhalbtcoutsrc_set_rfe_type(u8 type)
++{
++	GLBtCoexist.board_info.rfe_type= type;
++}
++
++#ifdef CONFIG_RF4CE_COEXIST
++void EXhalbtcoutsrc_set_rf4ce_link_state(u8 state)
++{
++	GLBtCoexist.rf4ce_info.link_state = state;
++}
++
++u8 EXhalbtcoutsrc_get_rf4ce_link_state(void)
++{
++	return GLBtCoexist.rf4ce_info.link_state;
++}
++#endif
++
++void EXhalbtcoutsrc_switchband_notify(struct btc_coexist *pBtCoexist, u8 type)
++{
++	if(!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
++		return;
++	
++	if(pBtCoexist->manual_control)
++		return;
++
++	/* Driver should guarantee that the HW status isn't in low power mode */
++	/* halbtcoutsrc_LeaveLowPower(pBtCoexist); */
++#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
++	rtw_btc_ex_switchband_notify(pBtCoexist, type);
++#else
++
++	if(IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
++#ifdef CONFIG_RTL8822B
++		if(pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8822b1ant_switchband_notify(pBtCoexist, type);
++		else if(pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8822b2ant_switchband_notify(pBtCoexist, type);
++#endif
++	}
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8821c2ant_switchband_notify(pBtCoexist, type);
++		else if (pBtCoexist->board_info.btdm_ant_num == 1)
++			ex_halbtc8821c1ant_switchband_notify(pBtCoexist, type);
++	}
++#endif
++
++#ifdef CONFIG_RTL8814A
++	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
++		if (pBtCoexist->board_info.btdm_ant_num == 2)
++			ex_halbtc8814a2ant_switchband_notify(pBtCoexist, type);
++	}
++#endif
++
++#endif
++
++	/* halbtcoutsrc_NormalLowPower(pBtCoexist); */
++}
++
++u8 EXhalbtcoutsrc_rate_id_to_btc_rate_id(u8 rate_id)
++{
++	u8 btc_rate_id = BTC_UNKNOWN;
++
++	switch (rate_id) {
++		/* CCK rates */
++		case DESC_RATE1M:
++			btc_rate_id = BTC_CCK_1;
++			break;
++		case DESC_RATE2M:
++			btc_rate_id = BTC_CCK_2;
++			break;
++		case DESC_RATE5_5M:
++			btc_rate_id = BTC_CCK_5_5;
++			break;
++		case DESC_RATE11M:
++			btc_rate_id = BTC_CCK_11;
++			break;
++
++		/* OFDM rates */
++		case DESC_RATE6M:
++			btc_rate_id = BTC_OFDM_6;
++			break;
++		case DESC_RATE9M:
++			btc_rate_id = BTC_OFDM_9;
++			break;
++		case DESC_RATE12M:
++			btc_rate_id = BTC_OFDM_12;
++			break;
++		case DESC_RATE18M:
++			btc_rate_id = BTC_OFDM_18;
++			break;
++		case DESC_RATE24M:
++			btc_rate_id = BTC_OFDM_24;
++			break;
++		case DESC_RATE36M:
++			btc_rate_id = BTC_OFDM_36;
++			break;
++		case DESC_RATE48M:
++			btc_rate_id = BTC_OFDM_48;
++			break;
++		case DESC_RATE54M:
++			btc_rate_id = BTC_OFDM_54;
++			break;
++
++		/* MCS rates */
++		case DESC_RATEMCS0:
++			btc_rate_id = BTC_MCS_0;
++			break;
++		case DESC_RATEMCS1:
++			btc_rate_id = BTC_MCS_1;
++			break;
++		case DESC_RATEMCS2:
++			btc_rate_id = BTC_MCS_2;
++			break;
++		case DESC_RATEMCS3:
++			btc_rate_id = BTC_MCS_3;
++			break;
++		case DESC_RATEMCS4:
++			btc_rate_id = BTC_MCS_4;
++			break;
++		case DESC_RATEMCS5:
++			btc_rate_id = BTC_MCS_5;
++			break;
++		case DESC_RATEMCS6:
++			btc_rate_id = BTC_MCS_6;
++			break;
++		case DESC_RATEMCS7:
++			btc_rate_id = BTC_MCS_7;
++			break;
++		case DESC_RATEMCS8:
++			btc_rate_id = BTC_MCS_8;
++			break;
++		case DESC_RATEMCS9:
++			btc_rate_id = BTC_MCS_9;
++			break;
++		case DESC_RATEMCS10:
++			btc_rate_id = BTC_MCS_10;
++			break;
++		case DESC_RATEMCS11:
++			btc_rate_id = BTC_MCS_11;
++			break;
++		case DESC_RATEMCS12:
++			btc_rate_id = BTC_MCS_12;
++			break;
++		case DESC_RATEMCS13:
++			btc_rate_id = BTC_MCS_13;
++			break;
++		case DESC_RATEMCS14:
++			btc_rate_id = BTC_MCS_14;
++			break;
++		case DESC_RATEMCS15:
++			btc_rate_id = BTC_MCS_15;
++			break;
++		case DESC_RATEMCS16:
++			btc_rate_id = BTC_MCS_16;
++			break;
++		case DESC_RATEMCS17:
++			btc_rate_id = BTC_MCS_17;
++			break;
++		case DESC_RATEMCS18:
++			btc_rate_id = BTC_MCS_18;
++			break;
++		case DESC_RATEMCS19:
++			btc_rate_id = BTC_MCS_19;
++			break;
++		case DESC_RATEMCS20:
++			btc_rate_id = BTC_MCS_20;
++			break;
++		case DESC_RATEMCS21:
++			btc_rate_id = BTC_MCS_21;
++			break;
++		case DESC_RATEMCS22:
++			btc_rate_id = BTC_MCS_22;
++			break;
++		case DESC_RATEMCS23:
++			btc_rate_id = BTC_MCS_23;
++			break;
++		case DESC_RATEMCS24:
++			btc_rate_id = BTC_MCS_24;
++			break;
++		case DESC_RATEMCS25:
++			btc_rate_id = BTC_MCS_25;
++			break;
++		case DESC_RATEMCS26:
++			btc_rate_id = BTC_MCS_26;
++			break;
++		case DESC_RATEMCS27:
++			btc_rate_id = BTC_MCS_27;
++			break;
++		case DESC_RATEMCS28:
++			btc_rate_id = BTC_MCS_28;
++			break;
++		case DESC_RATEMCS29:
++			btc_rate_id = BTC_MCS_29;
++			break;
++		case DESC_RATEMCS30:
++			btc_rate_id = BTC_MCS_30;
++			break;
++		case DESC_RATEMCS31:
++			btc_rate_id = BTC_MCS_31;
++			break;
++			
++		case DESC_RATEVHTSS1MCS0:
++			btc_rate_id = BTC_VHT_1SS_MCS_0;
++			break;
++		case DESC_RATEVHTSS1MCS1:
++			btc_rate_id = BTC_VHT_1SS_MCS_1;
++			break;
++		case DESC_RATEVHTSS1MCS2:
++			btc_rate_id = BTC_VHT_1SS_MCS_2;
++			break;
++		case DESC_RATEVHTSS1MCS3:
++			btc_rate_id = BTC_VHT_1SS_MCS_3;
++			break;
++		case DESC_RATEVHTSS1MCS4:
++			btc_rate_id = BTC_VHT_1SS_MCS_4;
++			break;
++		case DESC_RATEVHTSS1MCS5:
++			btc_rate_id = BTC_VHT_1SS_MCS_5;
++			break;
++		case DESC_RATEVHTSS1MCS6:
++			btc_rate_id = BTC_VHT_1SS_MCS_6;
++			break;
++		case DESC_RATEVHTSS1MCS7:
++			btc_rate_id = BTC_VHT_1SS_MCS_7;
++			break;
++		case DESC_RATEVHTSS1MCS8:
++			btc_rate_id = BTC_VHT_1SS_MCS_8;
++			break;
++		case DESC_RATEVHTSS1MCS9:
++			btc_rate_id = BTC_VHT_1SS_MCS_9;
++			break;
++
++		case DESC_RATEVHTSS2MCS0:
++			btc_rate_id = BTC_VHT_2SS_MCS_0;
++			break;
++		case DESC_RATEVHTSS2MCS1:
++			btc_rate_id = BTC_VHT_2SS_MCS_1;
++			break;
++		case DESC_RATEVHTSS2MCS2:
++			btc_rate_id = BTC_VHT_2SS_MCS_2;
++			break;
++		case DESC_RATEVHTSS2MCS3:
++			btc_rate_id = BTC_VHT_2SS_MCS_3;
++			break;
++		case DESC_RATEVHTSS2MCS4:
++			btc_rate_id = BTC_VHT_2SS_MCS_4;
++			break;
++		case DESC_RATEVHTSS2MCS5:
++			btc_rate_id = BTC_VHT_2SS_MCS_5;
++			break;
++		case DESC_RATEVHTSS2MCS6:
++			btc_rate_id = BTC_VHT_2SS_MCS_6;
++			break;
++		case DESC_RATEVHTSS2MCS7:
++			btc_rate_id = BTC_VHT_2SS_MCS_7;
++			break;
++		case DESC_RATEVHTSS2MCS8:
++			btc_rate_id = BTC_VHT_2SS_MCS_8;
++			break;
++		case DESC_RATEVHTSS2MCS9:
++			btc_rate_id = BTC_VHT_2SS_MCS_9;
++			break;
++
++		case DESC_RATEVHTSS3MCS0:
++			btc_rate_id = BTC_VHT_3SS_MCS_0;
++			break;
++		case DESC_RATEVHTSS3MCS1:
++			btc_rate_id = BTC_VHT_3SS_MCS_1;
++			break;
++		case DESC_RATEVHTSS3MCS2:
++			btc_rate_id = BTC_VHT_3SS_MCS_2;
++			break;
++		case DESC_RATEVHTSS3MCS3:
++			btc_rate_id = BTC_VHT_3SS_MCS_3;
++			break;
++		case DESC_RATEVHTSS3MCS4:
++			btc_rate_id = BTC_VHT_3SS_MCS_4;
++			break;
++		case DESC_RATEVHTSS3MCS5:
++			btc_rate_id = BTC_VHT_3SS_MCS_5;
++			break;
++		case DESC_RATEVHTSS3MCS6:
++			btc_rate_id = BTC_VHT_3SS_MCS_6;
++			break;
++		case DESC_RATEVHTSS3MCS7:
++			btc_rate_id = BTC_VHT_3SS_MCS_7;
++			break;
++		case DESC_RATEVHTSS3MCS8:
++			btc_rate_id = BTC_VHT_3SS_MCS_8;
++			break;
++		case DESC_RATEVHTSS3MCS9:
++			btc_rate_id = BTC_VHT_3SS_MCS_9;
++			break;
++
++		case DESC_RATEVHTSS4MCS0:
++			btc_rate_id = BTC_VHT_4SS_MCS_0;
++			break;
++		case DESC_RATEVHTSS4MCS1:
++			btc_rate_id = BTC_VHT_4SS_MCS_1;
++			break;
++		case DESC_RATEVHTSS4MCS2:
++			btc_rate_id = BTC_VHT_4SS_MCS_2;
++			break;
++		case DESC_RATEVHTSS4MCS3:
++			btc_rate_id = BTC_VHT_4SS_MCS_3;
++			break;
++		case DESC_RATEVHTSS4MCS4:
++			btc_rate_id = BTC_VHT_4SS_MCS_4;
++			break;
++		case DESC_RATEVHTSS4MCS5:
++			btc_rate_id = BTC_VHT_4SS_MCS_5;
++			break;
++		case DESC_RATEVHTSS4MCS6:
++			btc_rate_id = BTC_VHT_4SS_MCS_6;
++			break;
++		case DESC_RATEVHTSS4MCS7:
++			btc_rate_id = BTC_VHT_4SS_MCS_7;
++			break;
++		case DESC_RATEVHTSS4MCS8:
++			btc_rate_id = BTC_VHT_4SS_MCS_8;
++			break;
++		case DESC_RATEVHTSS4MCS9:
++			btc_rate_id = BTC_VHT_4SS_MCS_9;
++			break;
++	}
++	
++	return btc_rate_id;
++}
++
++/*
++ * Description:
++ *	Run BT-Coexist mechansim or not
++ *
++ */
++void hal_btcoex_SetBTCoexist(PADAPTER padapter, u8 bBtExist)
++{
++	PHAL_DATA_TYPE	pHalData;
++
++
++	pHalData = GET_HAL_DATA(padapter);
++	pHalData->bt_coexist.bBtExist = bBtExist;
++}
++
++/*
++ * Dewcription:
++ *	Check is co-exist mechanism enabled or not
++ *
++ * Return:
++ *	_TRUE	Enable BT co-exist mechanism
++ *	_FALSE	Disable BT co-exist mechanism
++ */
++u8 hal_btcoex_IsBtExist(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE	pHalData;
++
++
++	pHalData = GET_HAL_DATA(padapter);
++	return pHalData->bt_coexist.bBtExist;
++}
++
++u8 hal_btcoex_IsBtDisabled(PADAPTER padapter)
++{
++	if (!hal_btcoex_IsBtExist(padapter))
++		return _TRUE;
++
++	if (GLBtCoexist.bt_info.bt_disabled)
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++void hal_btcoex_SetChipType(PADAPTER padapter, u8 chipType)
++{
++	PHAL_DATA_TYPE	pHalData;
++
++	pHalData = GET_HAL_DATA(padapter);
++	pHalData->bt_coexist.btChipType = chipType;
++}
++
++void hal_btcoex_SetPgAntNum(PADAPTER padapter, u8 antNum)
++{
++	PHAL_DATA_TYPE	pHalData;
++
++	pHalData = GET_HAL_DATA(padapter);
++
++	pHalData->bt_coexist.btTotalAntNum = antNum;
++}
++
++u8 hal_btcoex_Initialize(PADAPTER padapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	u8 ret;
++
++	_rtw_memset(&GLBtCoexist, 0, sizeof(GLBtCoexist));
++
++	ret = EXhalbtcoutsrc_InitlizeVariables((void *)padapter);
++
++	return ret;
++}
++
++void hal_btcoex_PowerOnSetting(PADAPTER padapter)
++{
++	EXhalbtcoutsrc_PowerOnSetting(&GLBtCoexist);
++}
++
++void hal_btcoex_AntInfoSetting(PADAPTER padapter)
++{
++	hal_btcoex_SetBTCoexist(padapter, rtw_btcoex_get_bt_coexist(padapter));
++	hal_btcoex_SetChipType(padapter, rtw_btcoex_get_chip_type(padapter));
++	hal_btcoex_SetPgAntNum(padapter, rtw_btcoex_get_pg_ant_num(padapter));
++
++	EXhalbtcoutsrc_AntInfoSetting(padapter);
++}
++
++void hal_btcoex_PowerOffSetting(PADAPTER padapter)
++{
++	/* Clear the WiFi on/off bit in scoreboard reg. if necessary */
++	if (IS_HARDWARE_TYPE_8703B(padapter) || IS_HARDWARE_TYPE_8723D(padapter)
++		|| IS_HARDWARE_TYPE_8821C(padapter) || IS_HARDWARE_TYPE_8822B(padapter)
++		|| IS_HARDWARE_TYPE_8822C(padapter))
++		rtw_write16(padapter, 0xaa, 0x8000);
++}
++
++void hal_btcoex_PreLoadFirmware(PADAPTER padapter)
++{
++	EXhalbtcoutsrc_PreLoadFirmware(&GLBtCoexist);
++}
++
++void hal_btcoex_InitHwConfig(PADAPTER padapter, u8 bWifiOnly)
++{
++	if (!hal_btcoex_IsBtExist(padapter))
++		return;
++
++	EXhalbtcoutsrc_init_hw_config(&GLBtCoexist, bWifiOnly);
++	EXhalbtcoutsrc_init_coex_dm(&GLBtCoexist);
++}
++
++void hal_btcoex_IpsNotify(PADAPTER padapter, u8 type)
++{
++	EXhalbtcoutsrc_ips_notify(&GLBtCoexist, type);
++}
++
++void hal_btcoex_LpsNotify(PADAPTER padapter, u8 type)
++{
++	EXhalbtcoutsrc_lps_notify(&GLBtCoexist, type);
++}
++
++void hal_btcoex_ScanNotify(PADAPTER padapter, u8 type)
++{
++	EXhalbtcoutsrc_scan_notify(&GLBtCoexist, type);
++}
++
++void hal_btcoex_ConnectNotify(PADAPTER padapter, u8 action)
++{
++	u8 assoType = 0;
++	u8 is_5g_band = _FALSE;
++
++	is_5g_band = (padapter->mlmeextpriv.cur_channel > 14) ? _TRUE : _FALSE;
++
++	if (action == _TRUE) {
++		if (is_5g_band == _TRUE)
++			assoType = BTC_ASSOCIATE_5G_START;
++		else
++			assoType = BTC_ASSOCIATE_START;
++	}
++	else {
++		if (is_5g_band == _TRUE)
++			assoType = BTC_ASSOCIATE_5G_FINISH;
++		else
++			assoType = BTC_ASSOCIATE_FINISH;
++	}
++	
++	EXhalbtcoutsrc_connect_notify(&GLBtCoexist, assoType);
++}
++
++void hal_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus)
++{
++	EXhalbtcoutsrc_media_status_notify(&GLBtCoexist, mediaStatus);
++}
++
++void hal_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType)
++{
++	EXhalbtcoutsrc_specific_packet_notify(&GLBtCoexist, pktType);
++}
++
++void hal_btcoex_IQKNotify(PADAPTER padapter, u8 state)
++{
++	GLBtcWiFiInIQKState = state;
++}
++
++void hal_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
++{
++	if (GLBtcWiFiInIQKState == _TRUE)
++		return;
++
++	EXhalbtcoutsrc_bt_info_notify(&GLBtCoexist, tmpBuf, length);
++}
++
++void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
++{
++	u8 extid, status, len, seq;
++
++
++	if (GLBtcBtMpRptWait == _FALSE)
++		return;
++
++	if ((length < 3) || (!tmpBuf))
++		return;
++
++	extid = tmpBuf[0];
++	/* not response from BT FW then exit*/
++	switch (extid) {
++	case C2H_WIFI_FW_ACTIVE_RSP:
++		GLBtcBtMpRptWiFiOK = _TRUE;
++		break;
++
++	case C2H_TRIG_BY_BT_FW:
++		GLBtcBtMpRptBTOK = _TRUE;
++
++		status = tmpBuf[1] & 0xF;
++		len = length - 3;
++		seq = tmpBuf[2] >> 4;
++
++		GLBtcBtMpRptSeq = seq;
++		GLBtcBtMpRptStatus = status;
++		_rtw_memcpy(GLBtcBtMpRptRsp, tmpBuf + 3, len);
++		GLBtcBtMpRptRspSize = len;
++
++		break;
++
++	default:
++		return;
++	}
++
++	if ((GLBtcBtMpRptWiFiOK == _TRUE) && (GLBtcBtMpRptBTOK == _TRUE)) {
++		GLBtcBtMpRptWait = _FALSE;
++		_cancel_timer_ex(&GLBtcBtMpOperTimer);
++		_rtw_up_sema(&GLBtcBtMpRptSema);
++	}
++}
++
++void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state)
++{
++	switch (state) {
++	case BTCOEX_SUSPEND_STATE_SUSPEND:
++		EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP);
++		break;
++	case BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT:
++		/* should switch to "#if 1" once all ICs' coex. revision are upgraded to support the KEEP_ANT case */
++#if 0
++		EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP_KEEP_ANT);
++#else
++		EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP);
++		EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP_KEEP_ANT);
++#endif
++		break;
++	case BTCOEX_SUSPEND_STATE_RESUME:
++#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++		/* re-download FW after resume, inform WL FW port number */
++		rtw_hal_set_wifi_btc_port_id_cmd(GLBtCoexist.Adapter);
++#endif
++		EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_WAKE_UP);
++		break;
++	}
++}
++
++void hal_btcoex_HaltNotify(PADAPTER padapter, u8 do_halt)
++{
++	if (do_halt == 1)
++		EXhalbtcoutsrc_halt_notify(&GLBtCoexist);
++
++	GLBtCoexist.bBinded = _FALSE;
++	GLBtCoexist.Adapter = NULL;
++}
++
++void hal_btcoex_SwitchBtTRxMask(PADAPTER padapter)
++{
++	EXhalbtcoutsrc_SwitchBtTRxMask(&GLBtCoexist);
++}
++
++void hal_btcoex_Hanlder(PADAPTER padapter)
++{
++	u32	bt_patch_ver;
++
++	EXhalbtcoutsrc_periodical(&GLBtCoexist);
++
++	if (GLBtCoexist.bt_info.bt_get_fw_ver == 0) {
++		GLBtCoexist.btc_get(&GLBtCoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
++		GLBtCoexist.bt_info.bt_get_fw_ver = bt_patch_ver;
++	}
++}
++
++s32 hal_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter)
++{
++	return (s32)GLBtCoexist.bt_info.reject_agg_pkt;
++}
++
++s32 hal_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter)
++{
++	return (s32)GLBtCoexist.bt_info.bt_ctrl_agg_buf_size;
++}
++
++u32 hal_btcoex_GetAMPDUSize(PADAPTER padapter)
++{
++	return (u32)GLBtCoexist.bt_info.agg_buf_size;
++}
++
++void hal_btcoex_SetManualControl(PADAPTER padapter, u8 bmanual)
++{
++	GLBtCoexist.manual_control = bmanual;
++}
++
++u8 hal_btcoex_1Ant(PADAPTER padapter)
++{
++	if (hal_btcoex_IsBtExist(padapter) == _FALSE)
++		return _FALSE;
++
++	if (GLBtCoexist.board_info.btdm_ant_num == 1)
++		return _TRUE;
++
++	return _FALSE;
++}
++
++u8 hal_btcoex_IsBtControlLps(PADAPTER padapter)
++{
++	if (GLBtCoexist.bdontenterLPS == _TRUE)
++		return _TRUE;
++	
++	if (hal_btcoex_IsBtExist(padapter) == _FALSE)
++		return _FALSE;
++
++	if (GLBtCoexist.bt_info.bt_disabled)
++		return _FALSE;
++
++	if (GLBtCoexist.bt_info.bt_ctrl_lps)
++		return _TRUE;
++
++	return _FALSE;
++}
++
++u8 hal_btcoex_IsLpsOn(PADAPTER padapter)
++{
++	if (GLBtCoexist.bdontenterLPS == _TRUE)
++		return _FALSE;
++	
++	if (hal_btcoex_IsBtExist(padapter) == _FALSE)
++		return _FALSE;
++
++	if (GLBtCoexist.bt_info.bt_disabled)
++		return _FALSE;
++
++	if (GLBtCoexist.bt_info.bt_lps_on)
++		return _TRUE;
++
++	return _FALSE;
++}
++
++u8 hal_btcoex_RpwmVal(PADAPTER padapter)
++{
++	return GLBtCoexist.bt_info.rpwm_val;
++}
++
++u8 hal_btcoex_LpsVal(PADAPTER padapter)
++{
++	return GLBtCoexist.bt_info.lps_val;
++}
++
++u32 hal_btcoex_GetRaMask(PADAPTER padapter)
++{
++	if (!hal_btcoex_IsBtExist(padapter))
++		return 0;
++
++	if (GLBtCoexist.bt_info.bt_disabled)
++		return 0;
++
++	/* Modify by YiWei , suggest by Cosa and Jenyu
++	 * Remove the limit antenna number , because 2 antenna case (ex: 8192eu)also want to get BT coex report rate mask.
++	 */
++	/*if (GLBtCoexist.board_info.btdm_ant_num != 1)
++		return 0;*/
++
++	return GLBtCoexist.bt_info.ra_mask;
++}
++
++u8 hal_btcoex_query_reduced_wl_pwr_lvl(PADAPTER padapter)
++{
++	return GLBtCoexist.coex_dm.cur_wl_pwr_lvl;
++}
++
++void hal_btcoex_set_reduced_wl_pwr_lvl(PADAPTER padapter, u8 val)
++{
++	GLBtCoexist.coex_dm.cur_wl_pwr_lvl = val;
++}
++
++void hal_btcoex_do_reduce_wl_pwr_lvl(PADAPTER padapter)
++{
++	halbtcoutsrc_reduce_wl_tx_power(&GLBtCoexist, 0);
++}
++
++void hal_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen)
++{
++
++	_rtw_memcpy(GLBtCoexist.pwrModeVal, pCmdBuf, cmdLen);
++}
++
++void hal_btcoex_DisplayBtCoexInfo(PADAPTER padapter, u8 *pbuf, u32 bufsize)
++{
++	PBTCDBGINFO pinfo;
++
++
++	pinfo = &GLBtcDbgInfo;
++	DBG_BT_INFO_INIT(pinfo, pbuf, bufsize);
++	EXhalbtcoutsrc_DisplayBtCoexInfo(&GLBtCoexist);
++	DBG_BT_INFO_INIT(pinfo, NULL, 0);
++}
++
++void hal_btcoex_SetDBG(PADAPTER padapter, u32 *pDbgModule)
++{
++	u32 i;
++
++
++	if (NULL == pDbgModule)
++		return;
++
++	for (i = 0; i < COMP_MAX; i++)
++		GLBtcDbgType[i] = pDbgModule[i];
++}
++
++u32 hal_btcoex_GetDBG(PADAPTER padapter, u8 *pStrBuf, u32 bufSize)
++{
++	s32 count;
++	u8 *pstr;
++	u32 leftSize;
++
++
++	if ((NULL == pStrBuf) || (0 == bufSize))
++		return 0;
++
++	count = 0;
++	pstr = pStrBuf;
++	leftSize = bufSize;
++	/*	RTW_INFO(FUNC_ADPT_FMT ": bufsize=%d\n", FUNC_ADPT_ARG(padapter), bufSize); */
++
++	count = rtw_sprintf(pstr, leftSize, "#define DBG\t%d\n", DBG);
++	if ((count < 0) || (count >= leftSize))
++		goto exit;
++	pstr += count;
++	leftSize -= count;
++
++	count = rtw_sprintf(pstr, leftSize, "BTCOEX Debug Setting:\n");
++	if ((count < 0) || (count >= leftSize))
++		goto exit;
++	pstr += count;
++	leftSize -= count;
++
++	count = rtw_sprintf(pstr, leftSize,
++			    "COMP_COEX: 0x%08X\n\n",
++			    GLBtcDbgType[COMP_COEX]);
++	if ((count < 0) || (count >= leftSize))
++		goto exit;
++	pstr += count;
++	leftSize -= count;
++
++#if 0
++	count = rtw_sprintf(pstr, leftSize, "INTERFACE Debug Setting Definition:\n");
++	if ((count < 0) || (count >= leftSize))
++		goto exit;
++	pstr += count;
++	leftSize -= count;
++	count = rtw_sprintf(pstr, leftSize, "\tbit[0]=%d for INTF_INIT\n",
++		    GLBtcDbgType[BTC_MSG_INTERFACE] & INTF_INIT ? 1 : 0);
++	if ((count < 0) || (count >= leftSize))
++		goto exit;
++	pstr += count;
++	leftSize -= count;
++	count = rtw_sprintf(pstr, leftSize, "\tbit[2]=%d for INTF_NOTIFY\n\n",
++		    GLBtcDbgType[BTC_MSG_INTERFACE] & INTF_NOTIFY ? 1 : 0);
++	if ((count < 0) || (count >= leftSize))
++		goto exit;
++	pstr += count;
++	leftSize -= count;
++
++	count = rtw_sprintf(pstr, leftSize, "ALGORITHM Debug Setting Definition:\n");
++	if ((count < 0) || (count >= leftSize))
++		goto exit;
++	pstr += count;
++	leftSize -= count;
++	count = rtw_sprintf(pstr, leftSize, "\tbit[0]=%d for BT_RSSI_STATE\n",
++		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_BT_RSSI_STATE ? 1 : 0);
++	if ((count < 0) || (count >= leftSize))
++		goto exit;
++	pstr += count;
++	leftSize -= count;
++	count = rtw_sprintf(pstr, leftSize, "\tbit[1]=%d for WIFI_RSSI_STATE\n",
++		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_WIFI_RSSI_STATE ? 1 : 0);
++	if ((count < 0) || (count >= leftSize))
++		goto exit;
++	pstr += count;
++	leftSize -= count;
++	count = rtw_sprintf(pstr, leftSize, "\tbit[2]=%d for BT_MONITOR\n",
++		    GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_BT_MONITOR ? 1 : 0);
++	if ((count < 0) || (count >= leftSize))
++		goto exit;
++	pstr += count;
++	leftSize -= count;
++	count = rtw_sprintf(pstr, leftSize, "\tbit[3]=%d for TRACE\n",
++		    GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE ? 1 : 0);
++	if ((count < 0) || (count >= leftSize))
++		goto exit;
++	pstr += count;
++	leftSize -= count;
++	count = rtw_sprintf(pstr, leftSize, "\tbit[4]=%d for TRACE_FW\n",
++		    GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_FW ? 1 : 0);
++	if ((count < 0) || (count >= leftSize))
++		goto exit;
++	pstr += count;
++	leftSize -= count;
++	count = rtw_sprintf(pstr, leftSize, "\tbit[5]=%d for TRACE_FW_DETAIL\n",
++		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_FW_DETAIL ? 1 : 0);
++	if ((count < 0) || (count >= leftSize))
++		goto exit;
++	pstr += count;
++	leftSize -= count;
++	count = rtw_sprintf(pstr, leftSize, "\tbit[6]=%d for TRACE_FW_EXEC\n",
++		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_FW_EXEC ? 1 : 0);
++	if ((count < 0) || (count >= leftSize))
++		goto exit;
++	pstr += count;
++	leftSize -= count;
++	count = rtw_sprintf(pstr, leftSize, "\tbit[7]=%d for TRACE_SW\n",
++		    GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_SW ? 1 : 0);
++	if ((count < 0) || (count >= leftSize))
++		goto exit;
++	pstr += count;
++	leftSize -= count;
++	count = rtw_sprintf(pstr, leftSize, "\tbit[8]=%d for TRACE_SW_DETAIL\n",
++		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_SW_DETAIL ? 1 : 0);
++	if ((count < 0) || (count >= leftSize))
++		goto exit;
++	pstr += count;
++	leftSize -= count;
++	count = rtw_sprintf(pstr, leftSize, "\tbit[9]=%d for TRACE_SW_EXEC\n",
++		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_SW_EXEC ? 1 : 0);
++	if ((count < 0) || (count >= leftSize))
++		goto exit;
++	pstr += count;
++	leftSize -= count;
++#endif
++
++exit:
++	count = pstr - pStrBuf;
++	/*	RTW_INFO(FUNC_ADPT_FMT ": usedsize=%d\n", FUNC_ADPT_ARG(padapter), count); */
++
++	return count;
++}
++
++u8 hal_btcoex_IncreaseScanDeviceNum(PADAPTER padapter)
++{
++	if (!hal_btcoex_IsBtExist(padapter))
++		return _FALSE;
++
++	if (GLBtCoexist.bt_info.increase_scan_dev_num)
++		return _TRUE;
++
++	return _FALSE;
++}
++
++u8 hal_btcoex_IsBtLinkExist(PADAPTER padapter)
++{
++	if (GLBtCoexist.bt_link_info.bt_link_exist)
++		return _TRUE;
++
++	return _FALSE;
++}
++
++void hal_btcoex_SetBtPatchVersion(PADAPTER padapter, u16 btHciVer, u16 btPatchVer)
++{
++	EXhalbtcoutsrc_SetBtPatchVersion(btHciVer, btPatchVer);
++}
++
++void hal_btcoex_SetHciVersion(PADAPTER padapter, u16 hciVersion)
++{
++	EXhalbtcoutsrc_SetHciVersion(hciVersion);
++}
++
++void hal_btcoex_StackUpdateProfileInfo(void)
++{
++	EXhalbtcoutsrc_StackUpdateProfileInfo();
++}
++
++void hal_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON)
++{
++	ex_halbtcoutsrc_pta_off_on_notify(&GLBtCoexist, bBTON);
++}
++
++/*
++ *	Description:
++ *	Setting BT coex antenna isolation type .
++ *	coex mechanisn/ spital stream/ best throughput
++ *	anttype = 0	,	PSTDMA	/	2SS	/	0.5T	,	bad isolation , WiFi/BT ANT Distance<15cm , (<20dB) for 2,3 antenna
++ *	anttype = 1	,	PSTDMA	/	1SS	/	0.5T	,	normal isolaiton , 50cm>WiFi/BT ANT Distance>15cm , (>20dB) for 2 antenna
++ *	anttype = 2	,	TDMA	/	2SS	/	T ,		normal isolaiton , 50cm>WiFi/BT ANT Distance>15cm , (>20dB) for 3 antenna
++ *	anttype = 3	,	no TDMA	/	1SS	/	0.5T	,	good isolation , WiFi/BT ANT Distance >50cm , (>40dB) for 2 antenna
++ *	anttype = 4	,	no TDMA	/	2SS	/	T ,		good isolation , WiFi/BT ANT Distance >50cm , (>40dB) for 3 antenna
++ *	wifi only throughput ~ T
++ *	wifi/BT share one antenna with SPDT
++ */
++void hal_btcoex_SetAntIsolationType(PADAPTER padapter, u8 anttype)
++{
++	PHAL_DATA_TYPE pHalData;
++	PBTC_COEXIST	pBtCoexist = &GLBtCoexist;
++
++	/*RTW_INFO("####%s , anttype = %d  , %d\n" , __func__ , anttype , __LINE__); */
++	pHalData = GET_HAL_DATA(padapter);
++
++
++	pHalData->bt_coexist.btAntisolation = anttype;
++
++	switch (pHalData->bt_coexist.btAntisolation) {
++	case 0:
++		pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_0;
++		break;
++	case 1:
++		pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_1;
++		break;
++	case 2:
++		pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_2;
++		break;
++	case 3:
++		pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_3;
++		break;
++	case 4:
++		pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_4;
++		break;
++	}
++
++}
++
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++int
++hal_btcoex_ParseAntIsolationConfigFile(
++	PADAPTER		Adapter,
++	char			*buffer
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++	u32	i = 0 , j = 0;
++	char	*szLine , *ptmp;
++	int rtStatus = _SUCCESS;
++	char param_value_string[10];
++	u8 param_value;
++	u8 anttype = 4;
++
++	u8 ant_num = 3 , ant_distance = 50 , rfe_type = 1;
++
++	typedef struct ant_isolation {
++		char *param_name;  /* antenna isolation config parameter name */
++		u8 *value; /* antenna isolation config parameter value */
++	} ANT_ISOLATION;
++
++	ANT_ISOLATION ant_isolation_param[] = {
++		{"ANT_NUMBER" , &ant_num},
++		{"ANT_DISTANCE" , &ant_distance},
++		{"RFE_TYPE" , &rfe_type},
++		{NULL , 0}
++	};
++
++
++
++	/* RTW_INFO("===>Hal_ParseAntIsolationConfigFile()\n" ); */
++
++	ptmp = buffer;
++	for (szLine = GetLineFromBuffer(ptmp) ; szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
++		/* skip comment */
++		if (IsCommentString(szLine))
++			continue;
++
++		/* RTW_INFO("%s : szLine = %s , strlen(szLine) = %d\n" , __func__ , szLine , strlen(szLine));*/
++		for (j = 0 ; ant_isolation_param[j].param_name != NULL ; j++) {
++			if (strstr(szLine , ant_isolation_param[j].param_name) != NULL) {
++				i = 0;
++				while (i < strlen(szLine)) {
++					if (szLine[i] != '"')
++						++i;
++					else {
++						/* skip only has one " */
++						if (strpbrk(szLine , "\"") == strrchr(szLine , '"')) {
++							RTW_INFO("Fail to parse parameters , format error!\n");
++							break;
++						}
++						_rtw_memset((void *)param_value_string , 0 , 10);
++						if (!ParseQualifiedString(szLine , &i , param_value_string , '"' , '"')) {
++							RTW_INFO("Fail to parse parameters\n");
++							return _FAIL;
++						} else if (!GetU1ByteIntegerFromStringInDecimal(param_value_string , ant_isolation_param[j].value))
++							RTW_INFO("Fail to GetU1ByteIntegerFromStringInDecimal\n");
++
++						break;
++					}
++				}
++			}
++		}
++	}
++
++	/* YiWei 20140716 , for BT coex antenna isolation control */
++	/* rfe_type = 0 was SPDT , rfe_type = 1 was coupler */
++	if (ant_num == 3 && ant_distance >= 50)
++		anttype = 3;
++	else if (ant_num == 2 && ant_distance >= 50 && rfe_type == 1)
++		anttype = 2;
++	else if (ant_num == 3 && ant_distance >= 15 && ant_distance < 50)
++		anttype = 2;
++	else if (ant_num == 2 && ant_distance >= 15 && ant_distance < 50 && rfe_type == 1)
++		anttype = 2;
++	else if ((ant_num == 2 && ant_distance < 15 && rfe_type == 1) || (ant_num == 3 && ant_distance < 15))
++		anttype = 1;
++	else if (ant_num == 2 && rfe_type == 0)
++		anttype = 0;
++	else
++		anttype = 0;
++
++	hal_btcoex_SetAntIsolationType(Adapter, anttype);
++
++	RTW_INFO("%s : ant_num = %d\n" , __func__ , ant_num);
++	RTW_INFO("%s : ant_distance = %d\n" , __func__ , ant_distance);
++	RTW_INFO("%s : rfe_type = %d\n" , __func__ , rfe_type);
++	/* RTW_INFO("<===Hal_ParseAntIsolationConfigFile()\n"); */
++	return rtStatus;
++}
++
++
++int
++hal_btcoex_AntIsolationConfig_ParaFile(
++		PADAPTER	Adapter,
++		char		*pFileName
++)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++	int	rlen = 0 , rtStatus = _FAIL;
++
++	_rtw_memset(pHalData->para_file_buf , 0 , MAX_PARA_FILE_BUF_LEN);
++
++	rtw_get_phy_file_path(Adapter, pFileName);
++	if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
++		rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
++		if (rlen > 0)
++			rtStatus = _SUCCESS;
++	}
++
++
++	if (rtStatus == _SUCCESS) {
++		/*RTW_INFO("%s(): read %s ok\n", __func__ , pFileName);*/
++		rtStatus = hal_btcoex_ParseAntIsolationConfigFile(Adapter , pHalData->para_file_buf);
++	} else
++		RTW_INFO("%s(): No File %s, Load from *** Array!\n" , __func__ , pFileName);
++
++	return rtStatus;
++}
++#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */
++
++u16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data)
++{
++	u16 ret = 0;
++
++	halbtcoutsrc_LeaveLowPower(&GLBtCoexist);
++
++	ret = halbtcoutsrc_GetBtReg_with_status(&GLBtCoexist, type, addr, data);
++
++	halbtcoutsrc_NormalLowPower(&GLBtCoexist);
++
++	return ret;
++}
++
++u16 hal_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val)
++{
++	u16 ret = 0;
++
++	halbtcoutsrc_LeaveLowPower(&GLBtCoexist);
++
++	ret = halbtcoutsrc_SetBtReg(&GLBtCoexist, type, addr, val);
++
++	halbtcoutsrc_NormalLowPower(&GLBtCoexist);
++
++	return ret;
++}
++
++void hal_btcoex_set_rfe_type(u8 type)
++{
++	EXhalbtcoutsrc_set_rfe_type(type);
++}
++
++#ifdef CONFIG_RF4CE_COEXIST
++void hal_btcoex_set_rf4ce_link_state(u8 state)
++{
++	EXhalbtcoutsrc_set_rf4ce_link_state(state);
++}
++
++u8 hal_btcoex_get_rf4ce_link_state(void)
++{
++	return EXhalbtcoutsrc_get_rf4ce_link_state();
++}
++#endif /* CONFIG_RF4CE_COEXIST */
++
++void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type)
++{
++	switch (band_type) {
++	case BAND_ON_2_4G:
++		if (under_scan)
++			EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_24G);
++		else
++			EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_24G_NOFORSCAN);
++		break;
++	case BAND_ON_5G:
++		EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_5G);
++		break;
++	default:
++		RTW_INFO("[BTCOEX] unkown switch band type\n");
++		break;
++	}
++}
++
++void hal_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length)
++{
++	EXhalbtcoutsrc_WlFwDbgInfoNotify(&GLBtCoexist, tmpBuf, length);
++}
++
++void hal_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id)
++{
++	EXhalbtcoutsrc_rx_rate_change_notify(&GLBtCoexist, is_data_frame, EXhalbtcoutsrc_rate_id_to_btc_rate_id(rate_id));
++}
++
++u16 hal_btcoex_btset_testode(PADAPTER padapter, u8 type)
++{
++	u16 ret = 0;
++
++	halbtcoutsrc_LeaveLowPower(&GLBtCoexist);
++
++	ret = halbtcoutsrc_setbttestmode(&GLBtCoexist, type);
++
++	halbtcoutsrc_NormalLowPower(&GLBtCoexist);
++
++	return ret;
++}
++
++#endif /* CONFIG_BT_COEXIST */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_btcoex_wifionly.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_btcoex_wifionly.c
+new file mode 100644
+index 000000000..4752bc381
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_btcoex_wifionly.c
+@@ -0,0 +1,264 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#include <hal_btcoex_wifionly.h>
++
++#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1)
++
++#include "btc/mp_precomp.h"
++
++struct  wifi_only_cfg GLBtCoexistWifiOnly;
++
++void halwifionly_write1byte(void *pwifionlyContext, u32 RegAddr, u8 Data)
++{
++	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
++	PADAPTER		Adapter = pwifionlycfg->Adapter;
++
++	rtw_write8(Adapter, RegAddr, Data);
++}
++
++void halwifionly_write2byte(void *pwifionlyContext, u32 RegAddr, u16 Data)
++{
++	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
++	PADAPTER		Adapter = pwifionlycfg->Adapter;
++
++	rtw_write16(Adapter, RegAddr, Data);
++}
++
++void halwifionly_write4byte(void *pwifionlyContext, u32 RegAddr, u32 Data)
++{
++	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
++	PADAPTER		Adapter = pwifionlycfg->Adapter;
++
++	rtw_write32(Adapter, RegAddr, Data);
++}
++
++u8 halwifionly_read1byte(void *pwifionlyContext, u32 RegAddr)
++{
++	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
++	PADAPTER		Adapter = pwifionlycfg->Adapter;
++
++	return rtw_read8(Adapter, RegAddr);
++}
++
++u16 halwifionly_read2byte(void * pwifionlyContext, u32 RegAddr)
++{
++	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
++	PADAPTER		Adapter = pwifionlycfg->Adapter;
++
++	return rtw_read16(Adapter, RegAddr);
++}
++
++u32 halwifionly_read4byte(void *pwifionlyContext, u32 RegAddr)
++{
++	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
++	PADAPTER		Adapter = pwifionlycfg->Adapter;
++
++	return rtw_read32(Adapter, RegAddr);
++}
++
++void halwifionly_bitmaskwrite1byte(void *pwifionlyContext, u32 regAddr, u8 bitMask, u8 data)
++{
++	u8 originalValue, bitShift = 0;
++	u8 i;
++
++	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
++	PADAPTER		Adapter = pwifionlycfg->Adapter;
++
++	if (bitMask != 0xff) {
++		originalValue = rtw_read8(Adapter, regAddr);
++		for (i = 0; i <= 7; i++) {
++			if ((bitMask >> i) & 0x1)
++				break;
++		}
++		bitShift = i;
++		data = ((originalValue) & (~bitMask)) | (((data << bitShift)) & bitMask);
++	}
++	rtw_write8(Adapter, regAddr, data);
++}
++
++void halwifionly_phy_set_rf_reg(void *pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
++{
++	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
++	PADAPTER		Adapter = pwifionlycfg->Adapter;
++
++	phy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data);
++}
++
++void halwifionly_phy_set_bb_reg(void *pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data)
++{
++	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
++	PADAPTER		Adapter = pwifionlycfg->Adapter;
++
++	phy_set_bb_reg(Adapter, RegAddr, BitMask, Data);
++}
++
++void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	u8 is_5g = _FALSE;
++
++	if (pHalData->current_band_type == BAND_ON_5G)
++		is_5g = _TRUE;
++
++	if (IS_HARDWARE_TYPE_8822B(padapter)) {
++#ifdef CONFIG_RTL8822B
++		ex_hal8822b_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);
++#endif
++	}
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(padapter))
++		ex_hal8821c_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);
++#endif
++
++#ifdef CONFIG_RTL8822C
++	else if (IS_HARDWARE_TYPE_8822C(padapter))
++		ex_hal8822c_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);
++#endif
++
++#ifdef CONFIG_RTL8814B
++	else if (IS_HARDWARE_TYPE_8814B(padapter))
++		ex_hal8814b_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);
++#endif
++}
++
++void hal_btcoex_wifionly_scan_notify(PADAPTER padapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	u8 is_5g = _FALSE;
++
++	if (pHalData->current_band_type == BAND_ON_5G)
++		is_5g = _TRUE;
++
++	if (IS_HARDWARE_TYPE_8822B(padapter)) {
++#ifdef CONFIG_RTL8822B
++		ex_hal8822b_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);
++#endif
++	}
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(padapter))
++		ex_hal8821c_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);
++#endif
++
++#ifdef CONFIG_RTL8822C
++	else if (IS_HARDWARE_TYPE_8822C(padapter))
++		ex_hal8822c_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);
++#endif
++
++#ifdef CONFIG_RTL8814B
++	else if (IS_HARDWARE_TYPE_8814B(padapter))
++		ex_hal8814b_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);
++#endif
++}
++
++void hal_btcoex_wifionly_connect_notify(PADAPTER padapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	u8 is_5g = _FALSE;
++
++	if (pHalData->current_band_type == BAND_ON_5G)
++		is_5g = _TRUE;
++
++	if (IS_HARDWARE_TYPE_8822B(padapter)) {
++#ifdef CONFIG_RTL8822B
++		ex_hal8822b_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);
++#endif
++	}
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(padapter))
++		ex_hal8821c_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);
++#endif
++
++#ifdef CONFIG_RTL8822C
++	else if (IS_HARDWARE_TYPE_8822C(padapter))
++		ex_hal8822c_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);
++#endif
++
++#ifdef CONFIG_RTL8814B
++	else if (IS_HARDWARE_TYPE_8814B(padapter))
++		ex_hal8814b_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);
++#endif
++}
++
++void hal_btcoex_wifionly_hw_config(PADAPTER padapter)
++{
++	struct wifi_only_cfg *pwifionlycfg = &GLBtCoexistWifiOnly;
++
++	if (IS_HARDWARE_TYPE_8723B(padapter)) {
++#ifdef CONFIG_RTL8723B
++		ex_hal8723b_wifi_only_hw_config(pwifionlycfg);
++#endif
++	}
++
++#ifdef CONFIG_RTL8822B
++	else if (IS_HARDWARE_TYPE_8822B(padapter))
++		ex_hal8822b_wifi_only_hw_config(pwifionlycfg);
++#endif
++
++#ifdef CONFIG_RTL8821C
++	else if (IS_HARDWARE_TYPE_8821C(padapter))
++		ex_hal8821c_wifi_only_hw_config(pwifionlycfg);
++#endif
++
++#ifdef CONFIG_RTL8822C
++	else if (IS_HARDWARE_TYPE_8822C(padapter))
++		ex_hal8822c_wifi_only_hw_config(pwifionlycfg);
++#endif
++
++#ifdef CONFIG_RTL8814B
++	else if (IS_HARDWARE_TYPE_8814B(padapter))
++		ex_hal8814b_wifi_only_hw_config(pwifionlycfg);
++#endif
++}
++
++void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter)
++{
++	struct wifi_only_cfg		*pwifionlycfg = &GLBtCoexistWifiOnly;
++	struct wifi_only_haldata	*pwifionly_haldata = &pwifionlycfg->haldata_info;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	_rtw_memset(&GLBtCoexistWifiOnly, 0, sizeof(GLBtCoexistWifiOnly));
++
++	pwifionlycfg->Adapter = padapter;
++
++#ifdef CONFIG_PCI_HCI
++	pwifionlycfg->chip_interface = WIFIONLY_INTF_PCI;
++#elif defined(CONFIG_USB_HCI)
++	pwifionlycfg->chip_interface = WIFIONLY_INTF_USB;
++#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	pwifionlycfg->chip_interface = WIFIONLY_INTF_SDIO;
++#else
++	pwifionlycfg->chip_interface = WIFIONLY_INTF_UNKNOWN;
++#endif
++
++	pwifionly_haldata->customer_id = CUSTOMER_NORMAL;
++}
++
++void hal_btcoex_wifionly_AntInfoSetting(PADAPTER padapter)
++{
++	struct wifi_only_cfg		*pwifionlycfg = &GLBtCoexistWifiOnly;
++	struct wifi_only_haldata	*pwifionly_haldata = &pwifionlycfg->haldata_info;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	pwifionly_haldata->efuse_pg_antnum = pHalData->EEPROMBluetoothAntNum;
++	pwifionly_haldata->efuse_pg_antpath = pHalData->ant_path;
++	pwifionly_haldata->rfe_type = pHalData->rfe_type;
++	pwifionly_haldata->ant_div_cfg = pHalData->AntDivCfg;
++}
++
++#endif
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_com.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_com.c
+new file mode 100755
+index 000000000..b3557f72d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_com.c
+@@ -0,0 +1,15699 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _HAL_COM_C_
++
++#include <drv_types.h>
++#include "hal_com_h2c.h"
++
++#include "hal_data.h"
++
++#ifdef RTW_HALMAC
++#include "../../hal/hal_halmac.h"
++#endif
++
++void rtw_dump_fw_info(void *sel, _adapter *adapter)
++{
++	HAL_DATA_TYPE	*hal_data = NULL;
++
++	if (!adapter)
++		return;
++
++	hal_data = GET_HAL_DATA(adapter);
++	if (hal_data->bFWReady)
++		RTW_PRINT_SEL(sel, "FW VER -%d.%d\n", hal_data->firmware_version, hal_data->firmware_sub_version);
++	else
++		RTW_PRINT_SEL(sel, "FW not ready\n");
++}
++
++bool rsvd_page_cache_update_all(struct rsvd_page_cache_t *cache, u8 loc
++	, u8 txdesc_len, u32 page_size, u8 *info, u32 info_len)
++{
++	u8 page_num;
++	bool modified = 0;
++	bool loc_mod = 0, size_mod = 0, page_num_mod = 0;
++
++	page_num = info_len ? (u8)PageNum(txdesc_len + info_len, page_size) : 0;
++	if (!info_len)
++		loc = 0;
++
++	if (cache->loc != loc) {
++		RTW_INFO("%s %s loc change (%u -> %u)\n"
++			, __func__, cache->name, cache->loc, loc);
++		loc_mod = 1;
++	}
++	if (cache->size != info_len) {
++		RTW_INFO("%s %s size change (%u -> %u)\n"
++			, __func__, cache->name, cache->size, info_len);
++		size_mod = 1;
++	}
++	if (cache->page_num != page_num) {
++		RTW_INFO("%s %s page_num change (%u -> %u)\n"
++			, __func__, cache->name, cache->page_num, page_num);
++		page_num_mod = 1;
++	}
++
++	if (info && info_len) {
++		if (cache->data) {
++			if (cache->size == info_len) {
++				if (_rtw_memcmp(cache->data, info, info_len) != _TRUE) {
++					RTW_INFO("%s %s data change\n", __func__, cache->name);
++					modified = 1;
++				}
++			} else
++				rsvd_page_cache_free_data(cache);
++		}
++
++		if (!cache->data) {
++			cache->data = rtw_malloc(info_len);
++			if (!cache->data) {
++				RTW_ERR("%s %s alloc data with size(%u) fail\n"
++					, __func__, cache->name, info_len);
++				rtw_warn_on(1);
++			} else {
++				RTW_INFO("%s %s alloc data with size(%u)\n"
++					, __func__, cache->name, info_len);
++			}
++			modified = 1;
++		}
++
++		if (cache->data && modified)
++			_rtw_memcpy(cache->data, info, info_len);
++	} else {
++		if (cache->data && size_mod)
++			rsvd_page_cache_free_data(cache);
++	}
++
++	cache->loc = loc;
++	cache->page_num = page_num;
++	cache->size = info_len;
++
++	return modified | loc_mod | size_mod | page_num_mod;
++}
++
++bool rsvd_page_cache_update_data(struct rsvd_page_cache_t *cache, u8 *info, u32 info_len)
++{
++	bool modified = 0;
++
++	if (!info || !info_len) {
++		RTW_WARN("%s %s invalid input(info:%p, info_len:%u)\n"
++			, __func__, cache->name, info, info_len);
++		goto exit;
++	}
++
++	if (!cache->loc || !cache->page_num || !cache->size) {
++		RTW_ERR("%s %s layout not ready(loc:%u, page_num:%u, size:%u)\n"
++			, __func__, cache->name, cache->loc, cache->page_num, cache->size);
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (cache->size != info_len) {
++		RTW_ERR("%s %s size(%u) differ with info_len(%u)\n"
++			, __func__, cache->name, cache->size, info_len);
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (!cache->data) {
++		cache->data = rtw_zmalloc(cache->size);
++		if (!cache->data) {
++			RTW_ERR("%s %s alloc data with size(%u) fail\n"
++				, __func__, cache->name, cache->size);
++			rtw_warn_on(1);
++			goto exit;
++		} else {
++			RTW_INFO("%s %s alloc data with size(%u)\n"
++				, __func__, cache->name, info_len);
++		}
++		modified = 1;
++	}
++
++	if (_rtw_memcmp(cache->data, info, cache->size) == _FALSE) {
++		RTW_INFO("%s %s data change\n", __func__, cache->name);
++		_rtw_memcpy(cache->data, info, cache->size);
++		modified = 1;
++	}
++
++exit:
++	return modified;
++}
++
++void rsvd_page_cache_free_data(struct rsvd_page_cache_t *cache)
++{
++	if (cache->data) {
++		rtw_mfree(cache->data, cache->size);
++		cache->data = NULL;
++	}
++}
++
++void rsvd_page_cache_free(struct rsvd_page_cache_t *cache)
++{
++	cache->loc = 0;
++	cache->page_num = 0;
++	rsvd_page_cache_free_data(cache);
++	cache->size = 0;
++}
++
++/* #define CONFIG_GTK_OL_DBG */
++
++/*#define DBG_SEC_CAM_MOVE*/
++#ifdef DBG_SEC_CAM_MOVE
++void rtw_hal_move_sta_gk_to_dk(_adapter *adapter)
++{
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	int cam_id, index = 0;
++	u8 *addr = NULL;
++
++	if (!MLME_IS_STA(adapter))
++		return;
++
++	addr = get_bssid(pmlmepriv);
++
++	if (addr == NULL) {
++		RTW_INFO("%s: get bssid MAC addr fail!!\n", __func__);
++		return;
++	}
++
++	rtw_clean_dk_section(adapter);
++
++	do {
++		cam_id = rtw_camid_search(adapter, addr, index, 1);
++
++		if (cam_id == -1)
++			RTW_INFO("%s: cam_id: %d, key_id:%d\n", __func__, cam_id, index);
++		else
++			rtw_sec_cam_swap(adapter, cam_id, index);
++
++		index++;
++	} while (index < 4);
++
++}
++
++void rtw_hal_read_sta_dk_key(_adapter *adapter, u8 key_id)
++{
++	struct security_priv *psecuritypriv = &adapter->securitypriv;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	_irqL irqL;
++	u8 get_key[16];
++
++	_rtw_memset(get_key, 0, sizeof(get_key));
++
++	if (key_id > 4) {
++		RTW_INFO("%s [ERROR] gtk_keyindex:%d invalid\n", __func__, key_id);
++		rtw_warn_on(1);
++		return;
++	}
++	rtw_sec_read_cam_ent(adapter, key_id, NULL, NULL, get_key);
++
++	/*update key into related sw variable*/
++	_enter_critical_bh(&cam_ctl->lock, &irqL);
++	if (_rtw_camid_is_gk(adapter, key_id)) {
++		RTW_INFO("[HW KEY] -Key-id:%d "KEY_FMT"\n", key_id, KEY_ARG(get_key));
++		RTW_INFO("[cam_cache KEY] - Key-id:%d "KEY_FMT"\n", key_id, KEY_ARG(&dvobj->cam_cache[key_id].key));
++	}
++	_exit_critical_bh(&cam_ctl->lock, &irqL);
++
++}
++#endif
++
++
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++	char	rtw_phy_para_file_path[PATH_LENGTH_MAX];
++#endif
++
++void dump_chip_info(HAL_VERSION	ChipVersion)
++{
++	int cnt = 0;
++	u8 buf[128] = {0};
++
++	if (IS_8188E(ChipVersion))
++		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8188E_");
++	else if (IS_8188F(ChipVersion))
++		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8188F_");
++	else if (IS_8188GTV(ChipVersion))
++		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8188GTV_");
++	else if (IS_8812_SERIES(ChipVersion))
++		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8812_");
++	else if (IS_8192E(ChipVersion))
++		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8192E_");
++	else if (IS_8821_SERIES(ChipVersion))
++		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8821_");
++	else if (IS_8723B_SERIES(ChipVersion))
++		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8723B_");
++	else if (IS_8703B_SERIES(ChipVersion))
++		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8703B_");
++	else if (IS_8723D_SERIES(ChipVersion))
++		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8723D_");
++	else if (IS_8814A_SERIES(ChipVersion))
++		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8814A_");
++	else if (IS_8822B_SERIES(ChipVersion))
++		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8822B_");
++	else if (IS_8821C_SERIES(ChipVersion))
++		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8821C_");
++	else if (IS_8710B_SERIES(ChipVersion))
++		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8710B_");
++	else if (IS_8192F_SERIES(ChipVersion))
++		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8192F_");
++	else if (IS_8822C_SERIES(ChipVersion))
++		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8822C_");
++	else
++		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_UNKNOWN_");
++
++	cnt += sprintf((buf + cnt), "%s", IS_NORMAL_CHIP(ChipVersion) ? "" : "T_");
++	
++	if (IS_CHIP_VENDOR_TSMC(ChipVersion))
++		cnt += sprintf((buf + cnt), "%s", "T");
++	else if (IS_CHIP_VENDOR_UMC(ChipVersion))
++		cnt += sprintf((buf + cnt), "%s", "U");
++	else if (IS_CHIP_VENDOR_SMIC(ChipVersion))
++		cnt += sprintf((buf + cnt), "%s", "S");
++
++	if (IS_A_CUT(ChipVersion))
++		cnt += sprintf((buf + cnt), "1_");
++	else if (IS_B_CUT(ChipVersion))
++		cnt += sprintf((buf + cnt), "2_");
++	else if (IS_C_CUT(ChipVersion))
++		cnt += sprintf((buf + cnt), "3_");
++	else if (IS_D_CUT(ChipVersion))
++		cnt += sprintf((buf + cnt), "4_");
++	else if (IS_E_CUT(ChipVersion))
++		cnt += sprintf((buf + cnt), "5_");
++	else if (IS_F_CUT(ChipVersion))
++		cnt += sprintf((buf + cnt), "6_");
++	else if (IS_I_CUT(ChipVersion))
++		cnt += sprintf((buf + cnt), "9_");
++	else if (IS_J_CUT(ChipVersion))
++		cnt += sprintf((buf + cnt), "10_");
++	else if (IS_K_CUT(ChipVersion))
++		cnt += sprintf((buf + cnt), "11_");
++	else
++		cnt += sprintf((buf + cnt), "UNKNOWN_Cv(%d)_", ChipVersion.CUTVersion);
++
++	if (IS_1T1R(ChipVersion))
++		cnt += sprintf((buf + cnt), "1T1R_");
++	else if (IS_1T2R(ChipVersion))
++		cnt += sprintf((buf + cnt), "1T2R_");
++	else if (IS_2T2R(ChipVersion))
++		cnt += sprintf((buf + cnt), "2T2R_");
++	else if (IS_3T3R(ChipVersion))
++		cnt += sprintf((buf + cnt), "3T3R_");
++	else if (IS_3T4R(ChipVersion))
++		cnt += sprintf((buf + cnt), "3T4R_");
++	else if (IS_4T4R(ChipVersion))
++		cnt += sprintf((buf + cnt), "4T4R_");
++	else
++		cnt += sprintf((buf + cnt), "UNKNOWN_RFTYPE(%d)_", ChipVersion.RFType);
++
++	cnt += sprintf((buf + cnt), "RomVer(%d)\n", ChipVersion.ROMVer);
++
++	RTW_INFO("%s", buf);
++}
++
++u8 rtw_hal_get_port(_adapter *adapter)
++{
++	u8 hw_port = get_hw_port(adapter);
++#ifdef CONFIG_CLIENT_PORT_CFG
++	u8 clt_port = get_clt_port(adapter);
++
++	if (clt_port)
++		hw_port = clt_port;
++
++#ifdef DBG_HW_PORT
++	if (MLME_IS_STA(adapter) && (adapter->client_id != MAX_CLIENT_PORT_NUM)) {
++		if(hw_port == CLT_PORT_INVALID) {
++			RTW_ERR(ADPT_FMT" @@@@@ Client port == 0 @@@@@\n", ADPT_ARG(adapter));
++			rtw_warn_on(1);
++		}
++	}
++	else if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
++		if (hw_port != HW_PORT0) {
++			RTW_ERR(ADPT_FMT" @@@@@ AP / MESH port != 0 @@@@@\n", ADPT_ARG(adapter));
++			rtw_warn_on(1);
++		}
++	}
++	if (0)
++		RTW_INFO(ADPT_FMT" - HP:%d,CP:%d\n", ADPT_ARG(adapter), get_hw_port(adapter), get_clt_port(adapter));
++#endif /*DBG_HW_PORT*/
++
++#endif/*CONFIG_CLIENT_PORT_CFG*/
++
++	return hw_port;
++}
++
++#define	EEPROM_CHANNEL_PLAN_BY_HW_MASK	0x80
++
++/*
++ * Description:
++ *	Use hardware(efuse), driver parameter(registry) and default channel plan
++ *	to decide which one should be used.
++ *
++ * Parameters:
++ *	padapter			pointer of adapter
++ *	hw_alpha2		country code from HW (efuse/eeprom/mapfile)
++ *	hw_chplan		channel plan from HW (efuse/eeprom/mapfile)
++ *						BIT[7] software configure mode; 0:Enable, 1:disable
++ *						BIT[6:0] Channel Plan
++ *	sw_alpha2		country code from HW (registry/module param)
++ *	sw_chplan		channel plan from SW (registry/module param)
++ *	AutoLoadFail		efuse autoload fail or not
++ *
++ */
++void hal_com_config_channel_plan(
++		PADAPTER padapter,
++		char *hw_alpha2,
++		u8 hw_chplan,
++		char *sw_alpha2,
++		u8 sw_chplan,
++		BOOLEAN AutoLoadFail
++)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	PHAL_DATA_TYPE	pHalData;
++	u8 force_hw_chplan = _FALSE;
++	int chplan = -1;
++	const struct country_chplan *country_ent = NULL, *ent;
++	u8 def_chplan = 0x7F; /* Realtek define,  used when HW, SW both invalid */
++
++	pHalData = GET_HAL_DATA(padapter);
++
++	/* treat 0xFF as invalid value, bypass hw_chplan & force_hw_chplan parsing */
++	if (hw_chplan == 0xFF)
++		goto chk_hw_country_code;
++
++	if (AutoLoadFail == _TRUE)
++		goto chk_sw_config;
++
++#ifndef CONFIG_FORCE_SW_CHANNEL_PLAN
++	if (hw_chplan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)
++		force_hw_chplan = _TRUE;
++#endif
++
++	hw_chplan &= (~EEPROM_CHANNEL_PLAN_BY_HW_MASK);
++
++chk_hw_country_code:
++	if (hw_alpha2 && !IS_ALPHA2_NO_SPECIFIED(hw_alpha2)) {
++		ent = rtw_get_chplan_from_country(hw_alpha2);
++		if (ent) {
++			/* get chplan from hw country code, by pass hw chplan setting */
++			country_ent = ent;
++			chplan = ent->chplan;
++			goto chk_sw_config;
++		} else
++			RTW_PRINT("%s unsupported hw_alpha2:\"%c%c\"\n", __func__, hw_alpha2[0], hw_alpha2[1]);
++	}
++
++	if (rtw_is_channel_plan_valid(hw_chplan))
++		chplan = hw_chplan;
++	else if (force_hw_chplan == _TRUE) {
++		RTW_PRINT("%s unsupported hw_chplan:0x%02X\n", __func__, hw_chplan);
++		/* hw infomaton invalid, refer to sw information */
++		force_hw_chplan = _FALSE;
++	}
++
++chk_sw_config:
++	if (force_hw_chplan == _TRUE)
++		goto done;
++
++	if (sw_alpha2 && !IS_ALPHA2_NO_SPECIFIED(sw_alpha2)) {
++		ent = rtw_get_chplan_from_country(sw_alpha2);
++		if (ent) {
++			/* get chplan from sw country code, by pass sw chplan setting */
++			country_ent = ent;
++			chplan = ent->chplan;
++			goto done;
++		} else
++			RTW_PRINT("%s unsupported sw_alpha2:\"%c%c\"\n", __func__, sw_alpha2[0], sw_alpha2[1]);
++	}
++
++	if (rtw_is_channel_plan_valid(sw_chplan)) {
++		/* cancel hw_alpha2 because chplan is specified by sw_chplan*/
++		country_ent = NULL;
++		chplan = sw_chplan;
++	} else if (sw_chplan != RTW_CHPLAN_UNSPECIFIED)
++		RTW_PRINT("%s unsupported sw_chplan:0x%02X\n", __func__, sw_chplan);
++
++done:
++	if (chplan == -1) {
++		RTW_PRINT("%s use def_chplan:0x%02X\n", __func__, def_chplan);
++		chplan = def_chplan;
++	} else if (country_ent) {
++		RTW_PRINT("%s country code:\"%c%c\" with chplan:0x%02X\n", __func__
++			, country_ent->alpha2[0], country_ent->alpha2[1], country_ent->chplan);
++	} else
++		RTW_PRINT("%s chplan:0x%02X\n", __func__, chplan);
++
++	rfctl->country_ent = country_ent;
++	rfctl->ChannelPlan = chplan;
++	pHalData->bDisableSWChannelPlan = force_hw_chplan;
++}
++
++BOOLEAN
++HAL_IsLegalChannel(
++		PADAPTER	Adapter,
++		u32			Channel
++)
++{
++	BOOLEAN bLegalChannel = _TRUE;
++
++	if (Channel > 14) {
++		if (is_supported_5g(Adapter->registrypriv.wireless_mode) == _FALSE) {
++			bLegalChannel = _FALSE;
++			RTW_INFO("Channel > 14 but wireless_mode do not support 5G\n");
++		}
++	} else if ((Channel <= 14) && (Channel >= 1)) {
++		if (IsSupported24G(Adapter->registrypriv.wireless_mode) == _FALSE) {
++			bLegalChannel = _FALSE;
++			RTW_INFO("(Channel <= 14) && (Channel >=1) but wireless_mode do not support 2.4G\n");
++		}
++	} else {
++		bLegalChannel = _FALSE;
++		RTW_INFO("Channel is Invalid !!!\n");
++	}
++
++	return bLegalChannel;
++}
++
++u8	MRateToHwRate(u8 rate)
++{
++	u8	ret = DESC_RATE1M;
++
++	switch (rate) {
++	case MGN_1M:
++		ret = DESC_RATE1M;
++		break;
++	case MGN_2M:
++		ret = DESC_RATE2M;
++		break;
++	case MGN_5_5M:
++		ret = DESC_RATE5_5M;
++		break;
++	case MGN_11M:
++		ret = DESC_RATE11M;
++		break;
++	case MGN_6M:
++		ret = DESC_RATE6M;
++		break;
++	case MGN_9M:
++		ret = DESC_RATE9M;
++		break;
++	case MGN_12M:
++		ret = DESC_RATE12M;
++		break;
++	case MGN_18M:
++		ret = DESC_RATE18M;
++		break;
++	case MGN_24M:
++		ret = DESC_RATE24M;
++		break;
++	case MGN_36M:
++		ret = DESC_RATE36M;
++		break;
++	case MGN_48M:
++		ret = DESC_RATE48M;
++		break;
++	case MGN_54M:
++		ret = DESC_RATE54M;
++		break;
++
++	case MGN_MCS0:
++		ret = DESC_RATEMCS0;
++		break;
++	case MGN_MCS1:
++		ret = DESC_RATEMCS1;
++		break;
++	case MGN_MCS2:
++		ret = DESC_RATEMCS2;
++		break;
++	case MGN_MCS3:
++		ret = DESC_RATEMCS3;
++		break;
++	case MGN_MCS4:
++		ret = DESC_RATEMCS4;
++		break;
++	case MGN_MCS5:
++		ret = DESC_RATEMCS5;
++		break;
++	case MGN_MCS6:
++		ret = DESC_RATEMCS6;
++		break;
++	case MGN_MCS7:
++		ret = DESC_RATEMCS7;
++		break;
++	case MGN_MCS8:
++		ret = DESC_RATEMCS8;
++		break;
++	case MGN_MCS9:
++		ret = DESC_RATEMCS9;
++		break;
++	case MGN_MCS10:
++		ret = DESC_RATEMCS10;
++		break;
++	case MGN_MCS11:
++		ret = DESC_RATEMCS11;
++		break;
++	case MGN_MCS12:
++		ret = DESC_RATEMCS12;
++		break;
++	case MGN_MCS13:
++		ret = DESC_RATEMCS13;
++		break;
++	case MGN_MCS14:
++		ret = DESC_RATEMCS14;
++		break;
++	case MGN_MCS15:
++		ret = DESC_RATEMCS15;
++		break;
++	case MGN_MCS16:
++		ret = DESC_RATEMCS16;
++		break;
++	case MGN_MCS17:
++		ret = DESC_RATEMCS17;
++		break;
++	case MGN_MCS18:
++		ret = DESC_RATEMCS18;
++		break;
++	case MGN_MCS19:
++		ret = DESC_RATEMCS19;
++		break;
++	case MGN_MCS20:
++		ret = DESC_RATEMCS20;
++		break;
++	case MGN_MCS21:
++		ret = DESC_RATEMCS21;
++		break;
++	case MGN_MCS22:
++		ret = DESC_RATEMCS22;
++		break;
++	case MGN_MCS23:
++		ret = DESC_RATEMCS23;
++		break;
++	case MGN_MCS24:
++		ret = DESC_RATEMCS24;
++		break;
++	case MGN_MCS25:
++		ret = DESC_RATEMCS25;
++		break;
++	case MGN_MCS26:
++		ret = DESC_RATEMCS26;
++		break;
++	case MGN_MCS27:
++		ret = DESC_RATEMCS27;
++		break;
++	case MGN_MCS28:
++		ret = DESC_RATEMCS28;
++		break;
++	case MGN_MCS29:
++		ret = DESC_RATEMCS29;
++		break;
++	case MGN_MCS30:
++		ret = DESC_RATEMCS30;
++		break;
++	case MGN_MCS31:
++		ret = DESC_RATEMCS31;
++		break;
++
++	case MGN_VHT1SS_MCS0:
++		ret = DESC_RATEVHTSS1MCS0;
++		break;
++	case MGN_VHT1SS_MCS1:
++		ret = DESC_RATEVHTSS1MCS1;
++		break;
++	case MGN_VHT1SS_MCS2:
++		ret = DESC_RATEVHTSS1MCS2;
++		break;
++	case MGN_VHT1SS_MCS3:
++		ret = DESC_RATEVHTSS1MCS3;
++		break;
++	case MGN_VHT1SS_MCS4:
++		ret = DESC_RATEVHTSS1MCS4;
++		break;
++	case MGN_VHT1SS_MCS5:
++		ret = DESC_RATEVHTSS1MCS5;
++		break;
++	case MGN_VHT1SS_MCS6:
++		ret = DESC_RATEVHTSS1MCS6;
++		break;
++	case MGN_VHT1SS_MCS7:
++		ret = DESC_RATEVHTSS1MCS7;
++		break;
++	case MGN_VHT1SS_MCS8:
++		ret = DESC_RATEVHTSS1MCS8;
++		break;
++	case MGN_VHT1SS_MCS9:
++		ret = DESC_RATEVHTSS1MCS9;
++		break;
++	case MGN_VHT2SS_MCS0:
++		ret = DESC_RATEVHTSS2MCS0;
++		break;
++	case MGN_VHT2SS_MCS1:
++		ret = DESC_RATEVHTSS2MCS1;
++		break;
++	case MGN_VHT2SS_MCS2:
++		ret = DESC_RATEVHTSS2MCS2;
++		break;
++	case MGN_VHT2SS_MCS3:
++		ret = DESC_RATEVHTSS2MCS3;
++		break;
++	case MGN_VHT2SS_MCS4:
++		ret = DESC_RATEVHTSS2MCS4;
++		break;
++	case MGN_VHT2SS_MCS5:
++		ret = DESC_RATEVHTSS2MCS5;
++		break;
++	case MGN_VHT2SS_MCS6:
++		ret = DESC_RATEVHTSS2MCS6;
++		break;
++	case MGN_VHT2SS_MCS7:
++		ret = DESC_RATEVHTSS2MCS7;
++		break;
++	case MGN_VHT2SS_MCS8:
++		ret = DESC_RATEVHTSS2MCS8;
++		break;
++	case MGN_VHT2SS_MCS9:
++		ret = DESC_RATEVHTSS2MCS9;
++		break;
++	case MGN_VHT3SS_MCS0:
++		ret = DESC_RATEVHTSS3MCS0;
++		break;
++	case MGN_VHT3SS_MCS1:
++		ret = DESC_RATEVHTSS3MCS1;
++		break;
++	case MGN_VHT3SS_MCS2:
++		ret = DESC_RATEVHTSS3MCS2;
++		break;
++	case MGN_VHT3SS_MCS3:
++		ret = DESC_RATEVHTSS3MCS3;
++		break;
++	case MGN_VHT3SS_MCS4:
++		ret = DESC_RATEVHTSS3MCS4;
++		break;
++	case MGN_VHT3SS_MCS5:
++		ret = DESC_RATEVHTSS3MCS5;
++		break;
++	case MGN_VHT3SS_MCS6:
++		ret = DESC_RATEVHTSS3MCS6;
++		break;
++	case MGN_VHT3SS_MCS7:
++		ret = DESC_RATEVHTSS3MCS7;
++		break;
++	case MGN_VHT3SS_MCS8:
++		ret = DESC_RATEVHTSS3MCS8;
++		break;
++	case MGN_VHT3SS_MCS9:
++		ret = DESC_RATEVHTSS3MCS9;
++		break;
++	case MGN_VHT4SS_MCS0:
++		ret = DESC_RATEVHTSS4MCS0;
++		break;
++	case MGN_VHT4SS_MCS1:
++		ret = DESC_RATEVHTSS4MCS1;
++		break;
++	case MGN_VHT4SS_MCS2:
++		ret = DESC_RATEVHTSS4MCS2;
++		break;
++	case MGN_VHT4SS_MCS3:
++		ret = DESC_RATEVHTSS4MCS3;
++		break;
++	case MGN_VHT4SS_MCS4:
++		ret = DESC_RATEVHTSS4MCS4;
++		break;
++	case MGN_VHT4SS_MCS5:
++		ret = DESC_RATEVHTSS4MCS5;
++		break;
++	case MGN_VHT4SS_MCS6:
++		ret = DESC_RATEVHTSS4MCS6;
++		break;
++	case MGN_VHT4SS_MCS7:
++		ret = DESC_RATEVHTSS4MCS7;
++		break;
++	case MGN_VHT4SS_MCS8:
++		ret = DESC_RATEVHTSS4MCS8;
++		break;
++	case MGN_VHT4SS_MCS9:
++		ret = DESC_RATEVHTSS4MCS9;
++		break;
++	default:
++		break;
++	}
++
++	return ret;
++}
++
++u8	hw_rate_to_m_rate(u8 rate)
++{
++	u8	ret_rate = MGN_1M;
++
++	switch (rate) {
++
++	case DESC_RATE1M:
++		ret_rate = MGN_1M;
++		break;
++	case DESC_RATE2M:
++		ret_rate = MGN_2M;
++		break;
++	case DESC_RATE5_5M:
++		ret_rate = MGN_5_5M;
++		break;
++	case DESC_RATE11M:
++		ret_rate = MGN_11M;
++		break;
++	case DESC_RATE6M:
++		ret_rate = MGN_6M;
++		break;
++	case DESC_RATE9M:
++		ret_rate = MGN_9M;
++		break;
++	case DESC_RATE12M:
++		ret_rate = MGN_12M;
++		break;
++	case DESC_RATE18M:
++		ret_rate = MGN_18M;
++		break;
++	case DESC_RATE24M:
++		ret_rate = MGN_24M;
++		break;
++	case DESC_RATE36M:
++		ret_rate = MGN_36M;
++		break;
++	case DESC_RATE48M:
++		ret_rate = MGN_48M;
++		break;
++	case DESC_RATE54M:
++		ret_rate = MGN_54M;
++		break;
++	case DESC_RATEMCS0:
++		ret_rate = MGN_MCS0;
++		break;
++	case DESC_RATEMCS1:
++		ret_rate = MGN_MCS1;
++		break;
++	case DESC_RATEMCS2:
++		ret_rate = MGN_MCS2;
++		break;
++	case DESC_RATEMCS3:
++		ret_rate = MGN_MCS3;
++		break;
++	case DESC_RATEMCS4:
++		ret_rate = MGN_MCS4;
++		break;
++	case DESC_RATEMCS5:
++		ret_rate = MGN_MCS5;
++		break;
++	case DESC_RATEMCS6:
++		ret_rate = MGN_MCS6;
++		break;
++	case DESC_RATEMCS7:
++		ret_rate = MGN_MCS7;
++		break;
++	case DESC_RATEMCS8:
++		ret_rate = MGN_MCS8;
++		break;
++	case DESC_RATEMCS9:
++		ret_rate = MGN_MCS9;
++		break;
++	case DESC_RATEMCS10:
++		ret_rate = MGN_MCS10;
++		break;
++	case DESC_RATEMCS11:
++		ret_rate = MGN_MCS11;
++		break;
++	case DESC_RATEMCS12:
++		ret_rate = MGN_MCS12;
++		break;
++	case DESC_RATEMCS13:
++		ret_rate = MGN_MCS13;
++		break;
++	case DESC_RATEMCS14:
++		ret_rate = MGN_MCS14;
++		break;
++	case DESC_RATEMCS15:
++		ret_rate = MGN_MCS15;
++		break;
++	case DESC_RATEMCS16:
++		ret_rate = MGN_MCS16;
++		break;
++	case DESC_RATEMCS17:
++		ret_rate = MGN_MCS17;
++		break;
++	case DESC_RATEMCS18:
++		ret_rate = MGN_MCS18;
++		break;
++	case DESC_RATEMCS19:
++		ret_rate = MGN_MCS19;
++		break;
++	case DESC_RATEMCS20:
++		ret_rate = MGN_MCS20;
++		break;
++	case DESC_RATEMCS21:
++		ret_rate = MGN_MCS21;
++		break;
++	case DESC_RATEMCS22:
++		ret_rate = MGN_MCS22;
++		break;
++	case DESC_RATEMCS23:
++		ret_rate = MGN_MCS23;
++		break;
++	case DESC_RATEMCS24:
++		ret_rate = MGN_MCS24;
++		break;
++	case DESC_RATEMCS25:
++		ret_rate = MGN_MCS25;
++		break;
++	case DESC_RATEMCS26:
++		ret_rate = MGN_MCS26;
++		break;
++	case DESC_RATEMCS27:
++		ret_rate = MGN_MCS27;
++		break;
++	case DESC_RATEMCS28:
++		ret_rate = MGN_MCS28;
++		break;
++	case DESC_RATEMCS29:
++		ret_rate = MGN_MCS29;
++		break;
++	case DESC_RATEMCS30:
++		ret_rate = MGN_MCS30;
++		break;
++	case DESC_RATEMCS31:
++		ret_rate = MGN_MCS31;
++		break;
++	case DESC_RATEVHTSS1MCS0:
++		ret_rate = MGN_VHT1SS_MCS0;
++		break;
++	case DESC_RATEVHTSS1MCS1:
++		ret_rate = MGN_VHT1SS_MCS1;
++		break;
++	case DESC_RATEVHTSS1MCS2:
++		ret_rate = MGN_VHT1SS_MCS2;
++		break;
++	case DESC_RATEVHTSS1MCS3:
++		ret_rate = MGN_VHT1SS_MCS3;
++		break;
++	case DESC_RATEVHTSS1MCS4:
++		ret_rate = MGN_VHT1SS_MCS4;
++		break;
++	case DESC_RATEVHTSS1MCS5:
++		ret_rate = MGN_VHT1SS_MCS5;
++		break;
++	case DESC_RATEVHTSS1MCS6:
++		ret_rate = MGN_VHT1SS_MCS6;
++		break;
++	case DESC_RATEVHTSS1MCS7:
++		ret_rate = MGN_VHT1SS_MCS7;
++		break;
++	case DESC_RATEVHTSS1MCS8:
++		ret_rate = MGN_VHT1SS_MCS8;
++		break;
++	case DESC_RATEVHTSS1MCS9:
++		ret_rate = MGN_VHT1SS_MCS9;
++		break;
++	case DESC_RATEVHTSS2MCS0:
++		ret_rate = MGN_VHT2SS_MCS0;
++		break;
++	case DESC_RATEVHTSS2MCS1:
++		ret_rate = MGN_VHT2SS_MCS1;
++		break;
++	case DESC_RATEVHTSS2MCS2:
++		ret_rate = MGN_VHT2SS_MCS2;
++		break;
++	case DESC_RATEVHTSS2MCS3:
++		ret_rate = MGN_VHT2SS_MCS3;
++		break;
++	case DESC_RATEVHTSS2MCS4:
++		ret_rate = MGN_VHT2SS_MCS4;
++		break;
++	case DESC_RATEVHTSS2MCS5:
++		ret_rate = MGN_VHT2SS_MCS5;
++		break;
++	case DESC_RATEVHTSS2MCS6:
++		ret_rate = MGN_VHT2SS_MCS6;
++		break;
++	case DESC_RATEVHTSS2MCS7:
++		ret_rate = MGN_VHT2SS_MCS7;
++		break;
++	case DESC_RATEVHTSS2MCS8:
++		ret_rate = MGN_VHT2SS_MCS8;
++		break;
++	case DESC_RATEVHTSS2MCS9:
++		ret_rate = MGN_VHT2SS_MCS9;
++		break;
++	case DESC_RATEVHTSS3MCS0:
++		ret_rate = MGN_VHT3SS_MCS0;
++		break;
++	case DESC_RATEVHTSS3MCS1:
++		ret_rate = MGN_VHT3SS_MCS1;
++		break;
++	case DESC_RATEVHTSS3MCS2:
++		ret_rate = MGN_VHT3SS_MCS2;
++		break;
++	case DESC_RATEVHTSS3MCS3:
++		ret_rate = MGN_VHT3SS_MCS3;
++		break;
++	case DESC_RATEVHTSS3MCS4:
++		ret_rate = MGN_VHT3SS_MCS4;
++		break;
++	case DESC_RATEVHTSS3MCS5:
++		ret_rate = MGN_VHT3SS_MCS5;
++		break;
++	case DESC_RATEVHTSS3MCS6:
++		ret_rate = MGN_VHT3SS_MCS6;
++		break;
++	case DESC_RATEVHTSS3MCS7:
++		ret_rate = MGN_VHT3SS_MCS7;
++		break;
++	case DESC_RATEVHTSS3MCS8:
++		ret_rate = MGN_VHT3SS_MCS8;
++		break;
++	case DESC_RATEVHTSS3MCS9:
++		ret_rate = MGN_VHT3SS_MCS9;
++		break;
++	case DESC_RATEVHTSS4MCS0:
++		ret_rate = MGN_VHT4SS_MCS0;
++		break;
++	case DESC_RATEVHTSS4MCS1:
++		ret_rate = MGN_VHT4SS_MCS1;
++		break;
++	case DESC_RATEVHTSS4MCS2:
++		ret_rate = MGN_VHT4SS_MCS2;
++		break;
++	case DESC_RATEVHTSS4MCS3:
++		ret_rate = MGN_VHT4SS_MCS3;
++		break;
++	case DESC_RATEVHTSS4MCS4:
++		ret_rate = MGN_VHT4SS_MCS4;
++		break;
++	case DESC_RATEVHTSS4MCS5:
++		ret_rate = MGN_VHT4SS_MCS5;
++		break;
++	case DESC_RATEVHTSS4MCS6:
++		ret_rate = MGN_VHT4SS_MCS6;
++		break;
++	case DESC_RATEVHTSS4MCS7:
++		ret_rate = MGN_VHT4SS_MCS7;
++		break;
++	case DESC_RATEVHTSS4MCS8:
++		ret_rate = MGN_VHT4SS_MCS8;
++		break;
++	case DESC_RATEVHTSS4MCS9:
++		ret_rate = MGN_VHT4SS_MCS9;
++		break;
++
++	default:
++		RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate);
++		break;
++	}
++
++	return ret_rate;
++}
++
++void	HalSetBrateCfg(
++	PADAPTER		Adapter,
++	u8			*mBratesOS,
++	u16			*pBrateCfg)
++{
++	u8	i, is_brate, brate;
++
++	for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
++		is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
++		brate = mBratesOS[i] & 0x7f;
++
++		if (is_brate) {
++			switch (brate) {
++			case IEEE80211_CCK_RATE_1MB:
++				*pBrateCfg |= RATE_1M;
++				break;
++			case IEEE80211_CCK_RATE_2MB:
++				*pBrateCfg |= RATE_2M;
++				break;
++			case IEEE80211_CCK_RATE_5MB:
++				*pBrateCfg |= RATE_5_5M;
++				break;
++			case IEEE80211_CCK_RATE_11MB:
++				*pBrateCfg |= RATE_11M;
++				break;
++			case IEEE80211_OFDM_RATE_6MB:
++				*pBrateCfg |= RATE_6M;
++				break;
++			case IEEE80211_OFDM_RATE_9MB:
++				*pBrateCfg |= RATE_9M;
++				break;
++			case IEEE80211_OFDM_RATE_12MB:
++				*pBrateCfg |= RATE_12M;
++				break;
++			case IEEE80211_OFDM_RATE_18MB:
++				*pBrateCfg |= RATE_18M;
++				break;
++			case IEEE80211_OFDM_RATE_24MB:
++				*pBrateCfg |= RATE_24M;
++				break;
++			case IEEE80211_OFDM_RATE_36MB:
++				*pBrateCfg |= RATE_36M;
++				break;
++			case IEEE80211_OFDM_RATE_48MB:
++				*pBrateCfg |= RATE_48M;
++				break;
++			case IEEE80211_OFDM_RATE_54MB:
++				*pBrateCfg |= RATE_54M;
++				break;
++			}
++		}
++	}
++}
++
++static void
++_OneOutPipeMapping(
++		PADAPTER	pAdapter
++)
++{
++	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(pAdapter);
++
++	pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
++	pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
++	pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];/* BE */
++	pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
++
++	pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
++	pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
++	pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
++	pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
++}
++
++static void
++_TwoOutPipeMapping(
++		PADAPTER	pAdapter,
++		BOOLEAN		bWIFICfg
++)
++{
++	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(pAdapter);
++
++	if (bWIFICfg) { /* WMM */
++
++		/*	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA  */
++		/* {  0, 	1, 	0, 	1, 	0, 	0, 	0, 	0, 		0	}; */
++		/* 0:ep_0 num, 1:ep_1 num */
++
++		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];/* VO */
++		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
++		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
++		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
++
++		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
++		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
++		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
++		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
++
++	} else { /* typical setting */
++
++
++		/* BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA */
++		/* {  1, 	1, 	0, 	0, 	0, 	0, 	0, 	0, 		0	};			 */
++		/* 0:ep_0 num, 1:ep_1 num */
++
++		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
++		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
++		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
++		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
++
++		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
++		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
++		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
++		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD	 */
++
++	}
++
++}
++
++static void _ThreeOutPipeMapping(
++		PADAPTER	pAdapter,
++		BOOLEAN		bWIFICfg
++)
++{
++	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(pAdapter);
++
++	if (bWIFICfg) { /* for WMM */
++
++		/*	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA  */
++		/* {  1, 	2, 	1, 	0, 	0, 	0, 	0, 	0, 		0	}; */
++		/* 0:H, 1:N, 2:L */
++
++		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
++		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
++		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
++		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
++
++		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
++		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
++		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
++		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
++
++	} else { /* typical setting */
++
++
++		/*	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA  */
++		/* {  2, 	2, 	1, 	0, 	0, 	0, 	0, 	0, 		0	};			 */
++		/* 0:H, 1:N, 2:L */
++
++		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
++		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
++		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
++		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */
++
++		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
++		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
++		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
++		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD	 */
++	}
++
++}
++#if 0
++static void _FourOutPipeMapping(
++		PADAPTER	pAdapter,
++		BOOLEAN		bWIFICfg
++)
++{
++	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(pAdapter);
++
++	if (bWIFICfg) { /* for WMM */
++
++		/*	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA  */
++		/* {  1, 	2, 	1, 	0, 	0, 	0, 	0, 	0, 		0	}; */
++		/* 0:H, 1:N, 2:L ,3:E */
++
++		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
++		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
++		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
++		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
++
++		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
++		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
++		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[3];/* HIGH */
++		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
++
++	} else { /* typical setting */
++
++
++		/*	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA  */
++		/* {  2, 	2, 	1, 	0, 	0, 	0, 	0, 	0, 		0	};			 */
++		/* 0:H, 1:N, 2:L */
++
++		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
++		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
++		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
++		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */
++
++		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
++		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
++		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[3];/* HIGH */
++		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD	 */
++	}
++
++}
++#endif
++BOOLEAN
++Hal_MappingOutPipe(
++		PADAPTER	pAdapter,
++		u8		NumOutPipe
++)
++{
++	struct registry_priv *pregistrypriv = &pAdapter->registrypriv;
++
++	BOOLEAN	 bWIFICfg = (pregistrypriv->wifi_spec) ? _TRUE : _FALSE;
++
++	BOOLEAN result = _TRUE;
++
++	switch (NumOutPipe) {
++	case 2:
++		_TwoOutPipeMapping(pAdapter, bWIFICfg);
++		break;
++	case 3:
++	case 4:
++	case 5:
++	case 6:
++		_ThreeOutPipeMapping(pAdapter, bWIFICfg);
++		break;
++	case 1:
++		_OneOutPipeMapping(pAdapter);
++		break;
++	default:
++		result = _FALSE;
++		break;
++	}
++
++	return result;
++
++}
++
++void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid)
++{
++	if (padapter->hal_func.reqtxrpt)
++		padapter->hal_func.reqtxrpt(padapter, macid);
++}
++
++void rtw_hal_dump_macaddr(void *sel, _adapter *adapter)
++{
++	int i;
++	_adapter *iface;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	u8 mac_addr[ETH_ALEN];
++
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++	rtw_mbid_cam_dump(sel, __func__, adapter);
++#else
++	rtw_mi_hal_dump_macaddr(sel, adapter);
++#endif
++}
++
++#ifdef RTW_HALMAC
++void rtw_hal_hw_port_enable(_adapter *adapter)
++{
++#if 1
++	u8 port_enable = _TRUE;
++
++	rtw_hal_set_hwreg(adapter, HW_VAR_PORT_CFG, &port_enable);
++#else
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct rtw_halmac_bcn_ctrl bcn_ctrl;
++
++	_rtw_memset(&bcn_ctrl, 0, sizeof(struct rtw_halmac_bcn_ctrl));
++	bcn_ctrl.enable_bcn = 1;
++	bcn_ctrl.rx_bssid_fit = 1;
++	bcn_ctrl.rxbcn_rpt = 1;
++
++	/*rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport,
++				struct rtw_halmac_bcn_ctrl *bcn_ctrl)*/
++	if (rtw_halmac_set_bcn_ctrl(dvobj, get_hw_port(adapter), &bcn_ctrl) == -1) {
++		RTW_ERR(ADPT_FMT" - hw port(%d) enable fail!!\n", ADPT_ARG(adapter), get_hw_port(adapter));
++		rtw_warn_on(1);
++	}
++#endif
++}
++void rtw_hal_hw_port_disable(_adapter *adapter)
++{
++	u8 port_enable = _FALSE;
++
++	rtw_hal_set_hwreg(adapter, HW_VAR_PORT_CFG, &port_enable);
++}
++
++void rtw_restore_hw_port_cfg(_adapter *adapter)
++{
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++
++#else
++	int i;
++	_adapter *iface;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (iface)
++			rtw_hal_hw_port_enable(iface);
++	}
++#endif
++}
++#endif
++
++void rtw_mi_set_mac_addr(_adapter *adapter)
++{
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++	rtw_mi_set_mbid_cam(adapter);
++#else
++	int i;
++	_adapter *iface;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (iface)
++			rtw_hal_set_hwreg(iface, HW_VAR_MAC_ADDR, adapter_mac_addr(iface));
++	}
++#endif
++	if (0)
++		rtw_hal_dump_macaddr(RTW_DBGDUMP, adapter);
++}
++
++void rtw_init_hal_com_default_value(PADAPTER Adapter)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
++	struct registry_priv *regsty = adapter_to_regsty(Adapter);
++
++	pHalData->AntDetection = 1;
++	pHalData->antenna_test = _FALSE;
++	pHalData->RegIQKFWOffload = regsty->iqk_fw_offload;
++	pHalData->ch_switch_offload = regsty->ch_switch_offload;
++	pHalData->multi_ch_switch_mode = 0;
++#ifdef RTW_REDUCE_SCAN_SWITCH_CH_TIME
++	if (pHalData->ch_switch_offload == 0)
++		pHalData->ch_switch_offload = 1;
++#endif
++}
++
++#ifdef CONFIG_FW_C2H_REG
++void c2h_evt_clear(_adapter *adapter)
++{
++	rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
++}
++
++s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf)
++{
++	s32 ret = _FAIL;
++	int i;
++	u8 trigger;
++
++	if (buf == NULL)
++		goto exit;
++
++	trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
++
++	if (trigger == C2H_EVT_HOST_CLOSE) {
++		goto exit; /* Not ready */
++	} else if (trigger != C2H_EVT_FW_CLOSE) {
++		goto clear_evt; /* Not a valid value */
++	}
++
++	_rtw_memset(buf, 0, C2H_REG_LEN);
++
++	/* Read ID, LEN, SEQ */
++	SET_C2H_ID_88XX(buf, rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL));
++	SET_C2H_SEQ_88XX(buf, rtw_read8(adapter, REG_C2HEVT_CMD_SEQ_88XX));
++	SET_C2H_PLEN_88XX(buf, rtw_read8(adapter, REG_C2HEVT_CMD_LEN_88XX));
++
++	if (0) {
++		RTW_INFO("%s id=0x%02x, seq=%u, plen=%u, trigger=0x%02x\n", __func__
++			, C2H_ID_88XX(buf), C2H_SEQ_88XX(buf), C2H_PLEN_88XX(buf), trigger);
++	}
++
++	/* Read the content */
++	for (i = 0; i < C2H_PLEN_88XX(buf); i++)
++		*(C2H_PAYLOAD_88XX(buf) + i) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
++
++	RTW_DBG_DUMP("payload: ", C2H_PAYLOAD_88XX(buf), C2H_PLEN_88XX(buf));
++
++	ret = _SUCCESS;
++
++clear_evt:
++	/*
++	* Clear event to notify FW we have read the command.
++	* If this field isn't clear, the FW won't update the next command message.
++	*/
++	c2h_evt_clear(adapter);
++
++exit:
++	return ret;
++}
++#endif /* CONFIG_FW_C2H_REG */
++
++#ifdef CONFIG_FW_C2H_PKT
++#ifndef DBG_C2H_PKT_PRE_HDL
++#define DBG_C2H_PKT_PRE_HDL 0
++#endif
++#ifndef DBG_C2H_PKT_HDL
++#define DBG_C2H_PKT_HDL 0
++#endif
++void rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len)
++{
++#ifdef RTW_HALMAC
++	/* TODO: extract hal_mac IC's code here*/
++#else
++	u8 parse_fail = 0;
++	u8 hdl_here = 0;
++	s32 ret = _FAIL;
++	u8 id, seq, plen;
++	u8 *payload;
++
++	if (rtw_hal_c2h_pkt_hdr_parse(adapter, buf, len, &id, &seq, &plen, &payload) != _SUCCESS) {
++		parse_fail = 1;
++		goto exit;
++	}
++
++	hdl_here = rtw_hal_c2h_id_handle_directly(adapter, id, seq, plen, payload) == _TRUE ? 1 : 0;
++	if (hdl_here) 
++		ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
++	else
++		ret = rtw_c2h_packet_wk_cmd(adapter, buf, len);
++
++exit:
++	if (parse_fail)
++		RTW_ERR("%s parse fail, buf=%p, len=:%u\n", __func__, buf, len);
++	else if (ret != _SUCCESS || DBG_C2H_PKT_PRE_HDL > 0) {
++		RTW_PRINT("%s: id=0x%02x, seq=%u, plen=%u, %s %s\n", __func__, id, seq, plen
++			, hdl_here ? "handle" : "enqueue"
++			, ret == _SUCCESS ? "ok" : "fail"
++		);
++		if (DBG_C2H_PKT_PRE_HDL >= 2)
++			RTW_PRINT_DUMP("dump: ", buf, len);
++	}
++#endif
++}
++
++void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len)
++{
++#ifdef RTW_HALMAC
++	adapter->hal_func.hal_mac_c2h_handler(adapter, buf, len);
++#else
++	u8 parse_fail = 0;
++	u8 bypass = 0;
++	s32 ret = _FAIL;
++	u8 id, seq, plen;
++	u8 *payload;
++
++	if (rtw_hal_c2h_pkt_hdr_parse(adapter, buf, len, &id, &seq, &plen, &payload) != _SUCCESS) {
++		parse_fail = 1;
++		goto exit;
++	}
++
++#ifdef CONFIG_WOWLAN
++	if (adapter_to_pwrctl(adapter)->wowlan_mode == _TRUE) {
++		bypass = 1;
++		ret = _SUCCESS;
++		goto exit;
++	}
++#endif
++
++	ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
++
++exit:
++	if (parse_fail)
++		RTW_ERR("%s parse fail, buf=%p, len=:%u\n", __func__, buf, len);
++	else if (ret != _SUCCESS || bypass || DBG_C2H_PKT_HDL > 0) {
++		RTW_PRINT("%s: id=0x%02x, seq=%u, plen=%u, %s %s\n", __func__, id, seq, plen
++			, !bypass ? "handle" : "bypass"
++			, ret == _SUCCESS ? "ok" : "fail"
++		);
++		if (DBG_C2H_PKT_HDL >= 2)
++			RTW_PRINT_DUMP("dump: ", buf, len);
++	}
++#endif
++}
++#endif /* CONFIG_FW_C2H_PKT */
++
++void c2h_iqk_offload(_adapter *adapter, u8 *data, u8 len)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct submit_ctx *iqk_sctx = &hal_data->iqk_sctx;
++
++	RTW_INFO("IQK offload finish in %dms\n", rtw_get_passing_time_ms(iqk_sctx->submit_time));
++	if (0)
++		RTW_INFO_DUMP("C2H_IQK_FINISH: ", data, len);
++
++	rtw_sctx_done(&iqk_sctx);
++}
++
++int c2h_iqk_offload_wait(_adapter *adapter, u32 timeout_ms)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct submit_ctx *iqk_sctx = &hal_data->iqk_sctx;
++
++	iqk_sctx->submit_time = rtw_get_current_time();
++	iqk_sctx->timeout_ms = timeout_ms;
++	iqk_sctx->status = RTW_SCTX_SUBMITTED;
++
++	return rtw_sctx_wait(iqk_sctx, __func__);
++}
++
++#ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
++void c2h_txpwr_idx_offload_done(_adapter *adapter, u8 *data, u8 len)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct submit_ctx *sctx = &hal_data->txpwr_idx_offload_sctx;
++
++	if (0)
++		RTW_INFO("txpwr_idx offload finish in %dms\n", rtw_get_passing_time_ms(sctx->submit_time));
++	rtw_sctx_done(&sctx);
++}
++
++int c2h_txpwr_idx_offload_wait(_adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct submit_ctx *sctx = &hal_data->txpwr_idx_offload_sctx;
++
++	return rtw_sctx_wait(sctx, __func__);
++}
++#endif
++
++#define	GET_C2H_MAC_HIDDEN_RPT_UUID_X(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 0, 0, 8)
++#define	GET_C2H_MAC_HIDDEN_RPT_UUID_Y(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8)
++#define	GET_C2H_MAC_HIDDEN_RPT_UUID_Z(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 5)
++#define	GET_C2H_MAC_HIDDEN_RPT_UUID_CRC(_data)			LE_BITS_TO_2BYTE(((u8 *)(_data)) + 2, 5, 11)
++#define	GET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 0, 4)
++#define	GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 4, 3)
++#define	GET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 7, 1)
++#define	GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 0, 4)
++#define	GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 4, 4)
++#define	GET_C2H_MAC_HIDDEN_RPT_BW(_data)				LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 3)
++#define	GET_C2H_MAC_HIDDEN_RPT_ANT_NUM(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 5, 3)
++#define	GET_C2H_MAC_HIDDEN_RPT_80211_PROTOCOL(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 2, 2)
++#define	GET_C2H_MAC_HIDDEN_RPT_NIC_ROUTER(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 6, 2)
++
++#ifndef DBG_C2H_MAC_HIDDEN_RPT_HANDLE
++#define DBG_C2H_MAC_HIDDEN_RPT_HANDLE 0
++#endif
++
++#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
++int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
++{
++	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	enum rf_type rf_type;
++	u8 tx_path_num, rx_path_num;
++	int ret = _FAIL;
++
++	u8 uuid_x;
++	u8 uuid_y;
++	u8 uuid_z;
++	u16 uuid_crc;
++
++	u8 hci_type;
++	u8 package_type;
++	u8 tr_switch;
++	u8 wl_func;
++	u8 hw_stype;
++	u8 bw;
++	u8 ss_num = 4;
++	u8 ant_num;
++	u8 protocol;
++	u8 nic;
++
++	int i;
++
++	if (len < MAC_HIDDEN_RPT_LEN) {
++		RTW_WARN("%s len(%u) < %d\n", __func__, len, MAC_HIDDEN_RPT_LEN);
++		goto exit;
++	}
++
++	uuid_x = GET_C2H_MAC_HIDDEN_RPT_UUID_X(data);
++	uuid_y = GET_C2H_MAC_HIDDEN_RPT_UUID_Y(data);
++	uuid_z = GET_C2H_MAC_HIDDEN_RPT_UUID_Z(data);
++	uuid_crc = GET_C2H_MAC_HIDDEN_RPT_UUID_CRC(data);
++
++	hci_type = GET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(data);
++	package_type = GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(data);
++
++	tr_switch = GET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(data);
++
++	wl_func = GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(data);
++	hw_stype = GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(data);
++
++	bw = GET_C2H_MAC_HIDDEN_RPT_BW(data);
++	ant_num = GET_C2H_MAC_HIDDEN_RPT_ANT_NUM(data);
++
++	protocol = GET_C2H_MAC_HIDDEN_RPT_80211_PROTOCOL(data);
++	nic = GET_C2H_MAC_HIDDEN_RPT_NIC_ROUTER(data);
++
++	if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) {
++		for (i = 0; i < len; i++)
++			RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i));
++
++		RTW_PRINT("uuid x:0x%02x y:0x%02x z:0x%x crc:0x%x\n", uuid_x, uuid_y, uuid_z, uuid_crc);
++		RTW_PRINT("hci_type:0x%x\n", hci_type);
++		RTW_PRINT("package_type:0x%x\n", package_type);
++		RTW_PRINT("tr_switch:0x%x\n", tr_switch);
++		RTW_PRINT("wl_func:0x%x\n", wl_func);
++		RTW_PRINT("hw_stype:0x%x\n", hw_stype);
++		RTW_PRINT("bw:0x%x\n", bw);
++		RTW_PRINT("ant_num:0x%x\n", ant_num);
++		RTW_PRINT("protocol:0x%x\n", protocol);
++		RTW_PRINT("nic:0x%x\n", nic);
++	}
++
++#if defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
++	if (IS_8822C_SERIES(hal_data->version_id) || IS_8814B_SERIES(hal_data->version_id)) {
++		#define GET_C2H_MAC_HIDDEN_RPT_SS_NUM(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 3, 2)
++		ss_num = GET_C2H_MAC_HIDDEN_RPT_SS_NUM(data);
++
++		if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE)
++			RTW_PRINT("ss_num:0x%x\n", ss_num);
++
++		if (ss_num == 0x03)
++			ss_num = 4;
++	}
++#endif
++
++#if defined(CONFIG_RTL8822C)
++	if (IS_8822C_SERIES(hal_data->version_id)) {
++		if (ant_num == 1)
++			hal_spec->rf_reg_trx_path_bmp = 0x22; /* 1T1R pathB */
++		if (hw_stype == 0xE)
++			hal_spec->max_tx_cnt = rtw_min(hal_spec->max_tx_cnt, 1); /* limit 1TX only */
++	}
++#endif
++	hal_data->PackageType = package_type;
++	hal_spec->hci_type = hci_type;
++	hal_spec->wl_func &= mac_hidden_wl_func_to_hal_wl_func(wl_func);
++	hal_spec->bw_cap &= mac_hidden_max_bw_to_hal_bw_cap(bw);
++	hal_spec->proto_cap &= mac_hidden_proto_to_hal_proto_cap(protocol);
++
++	rf_type = rtw_chip_rftype_to_hal_rftype(adapter, 0);
++	if (!RF_TYPE_VALID(rf_type)) {
++		RTW_ERR("%s rtw_chip_rftype_to_hal_rftype failed\n", __func__);
++		goto exit;
++	}
++	hal_spec->rf_reg_path_avail_num = rtw_min(hal_spec->rf_reg_path_num, ant_num);
++	tx_path_num = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->rf_reg_path_avail_num);
++	rx_path_num = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rf_reg_path_avail_num);
++	hal_spec->rf_reg_trx_path_bmp = rtw_restrict_trx_path_bmp_by_trx_num_lmt(
++		hal_spec->rf_reg_trx_path_bmp, tx_path_num, rx_path_num, &tx_path_num, &rx_path_num);
++	if (!hal_spec->rf_reg_trx_path_bmp) {
++		RTW_ERR("%s rtw_restrict_trx_path_bmp_by_trx_num_lmt(0x%x, %u, %u) failed\n"
++			, __func__, hal_spec->rf_reg_trx_path_bmp, tx_path_num, rx_path_num);
++		goto exit;
++	}
++	hal_spec->rf_reg_path_avail_num = rtw_max(tx_path_num, rx_path_num);
++
++	/*
++	* RF TX path num >= max_tx_cnt >= tx_nss_num
++	* ex: RF TX path num(4) >= max_tx_cnt(2) >= tx_nss_num(1)
++	* Select at most 2 out of 4 TX RF path to do 1SS 2TX
++	*/
++	hal_spec->max_tx_cnt = rtw_min(hal_spec->max_tx_cnt, tx_path_num);
++	hal_spec->tx_nss_num = rtw_min(hal_spec->tx_nss_num, hal_spec->max_tx_cnt);
++	hal_spec->tx_nss_num = rtw_min(hal_spec->tx_nss_num, ss_num);
++
++	hal_spec->rx_nss_num = rtw_min(hal_spec->rx_nss_num, rx_path_num);
++	hal_spec->rx_nss_num = rtw_min(hal_spec->rx_nss_num, ss_num);
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++
++int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len)
++{
++	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(adapter);
++	int ret = _FAIL;
++
++	int i;
++
++	if (len < MAC_HIDDEN_RPT_2_LEN) {
++		RTW_WARN("%s len(%u) < %d\n", __func__, len, MAC_HIDDEN_RPT_2_LEN);
++		goto exit;
++	}
++
++	if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) {
++		for (i = 0; i < len; i++)
++			RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i));
++	}
++
++	#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
++	if (IS_8188F(hal_data->version_id) || IS_8188GTV(hal_data->version_id)) {
++		#define GET_C2H_MAC_HIDDEN_RPT_IRV(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)) + 0, 0, 4)
++		u8 irv = GET_C2H_MAC_HIDDEN_RPT_IRV(data);
++
++		if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE)
++			RTW_PRINT("irv:0x%x\n", irv);
++
++		if(irv != 0xf)
++			hal_data->version_id.CUTVersion = irv;
++	}
++	#endif
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++
++int hal_read_mac_hidden_rpt(_adapter *adapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(adapter);
++	int ret = _FAIL;
++	int ret_fwdl;
++	u8 mac_hidden_rpt[MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN] = {0};
++	systime start = rtw_get_current_time();
++	u32 cnt = 0;
++	u32 timeout_ms = 800;
++	u32 min_cnt = 10;
++	u8 id = C2H_DEFEATURE_RSVD;
++	int i;
++
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
++	u8 hci_type = rtw_get_intf_type(adapter);
++
++	if ((hci_type == RTW_USB || hci_type == RTW_PCIE)
++		&& !rtw_is_hw_init_completed(adapter))
++		rtw_hal_power_on(adapter);
++#endif
++
++	/* inform FW mac hidden rpt from reg is needed */
++	rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DEFEATURE_RSVD);
++
++	/* download FW */
++	pHalData->not_xmitframe_fw_dl = 1;
++	ret_fwdl = rtw_hal_fw_dl(adapter, _FALSE);
++	pHalData->not_xmitframe_fw_dl = 0;
++	if (ret_fwdl != _SUCCESS)
++		goto mac_hidden_rpt_hdl;
++
++	/* polling for data ready */
++	start = rtw_get_current_time();
++	do {
++		cnt++;
++		id = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
++		if (id == C2H_MAC_HIDDEN_RPT || RTW_CANNOT_IO(adapter))
++			break;
++		rtw_msleep_os(10);
++	} while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt);
++
++	if (id == C2H_MAC_HIDDEN_RPT) {
++		/* read data */
++		for (i = 0; i < MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN; i++)
++			mac_hidden_rpt[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
++	}
++
++	/* inform FW mac hidden rpt has read */
++	rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DBG);
++
++mac_hidden_rpt_hdl:
++	c2h_mac_hidden_rpt_hdl(adapter, mac_hidden_rpt, MAC_HIDDEN_RPT_LEN);
++	c2h_mac_hidden_rpt_2_hdl(adapter, mac_hidden_rpt + MAC_HIDDEN_RPT_LEN, MAC_HIDDEN_RPT_2_LEN);
++
++	if (ret_fwdl == _SUCCESS && id == C2H_MAC_HIDDEN_RPT)
++		ret = _SUCCESS;
++
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
++	if ((hci_type == RTW_USB || hci_type == RTW_PCIE)
++		&& !rtw_is_hw_init_completed(adapter))
++		rtw_hal_power_off(adapter);
++#endif
++
++	RTW_INFO("%s %s! (%u, %dms), fwdl:%d, id:0x%02x\n", __func__
++		, (ret == _SUCCESS) ? "OK" : "Fail", cnt, rtw_get_passing_time_ms(start), ret_fwdl, id);
++
++	return ret;
++}
++#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */
++
++int c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len)
++{
++	int ret = _FAIL;
++
++	int i;
++
++	if (len < DEFEATURE_DBG_LEN) {
++		RTW_WARN("%s len(%u) < %d\n", __func__, len, DEFEATURE_DBG_LEN);
++		goto exit;
++	}
++
++	for (i = 0; i < len; i++)
++		RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i));
++
++	ret = _SUCCESS;
++	
++exit:
++	return ret;
++}
++
++#ifndef DBG_CUSTOMER_STR_RPT_HANDLE
++#define DBG_CUSTOMER_STR_RPT_HANDLE 0
++#endif
++
++#ifdef CONFIG_RTW_CUSTOMER_STR
++s32 rtw_hal_h2c_customer_str_req(_adapter *adapter)
++{
++	u8 h2c_data[H2C_CUSTOMER_STR_REQ_LEN] = {0};
++
++	SET_H2CCMD_CUSTOMER_STR_REQ_EN(h2c_data, 1);
++	return rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_REQ, H2C_CUSTOMER_STR_REQ_LEN, h2c_data);
++}
++
++#define	C2H_CUSTOMER_STR_RPT_BYTE0(_data)		((u8 *)(_data))
++#define	C2H_CUSTOMER_STR_RPT_2_BYTE8(_data)		((u8 *)(_data))
++
++int c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	int ret = _FAIL;
++	int i;
++
++	if (len < CUSTOMER_STR_RPT_LEN) {
++		RTW_WARN("%s len(%u) < %d\n", __func__, len, CUSTOMER_STR_RPT_LEN);
++		goto exit;
++	}
++
++	if (DBG_CUSTOMER_STR_RPT_HANDLE)
++		RTW_PRINT_DUMP("customer_str_rpt: ", data, CUSTOMER_STR_RPT_LEN);
++
++	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
++
++	if (dvobj->customer_str_sctx != NULL) {
++		if (dvobj->customer_str_sctx->status != RTW_SCTX_SUBMITTED)
++			RTW_WARN("%s invalid sctx.status:%d\n", __func__, dvobj->customer_str_sctx->status);
++		_rtw_memcpy(dvobj->customer_str,  C2H_CUSTOMER_STR_RPT_BYTE0(data), CUSTOMER_STR_RPT_LEN);
++		dvobj->customer_str_sctx->status = RTX_SCTX_CSTR_WAIT_RPT2;
++	} else
++		RTW_WARN("%s sctx not set\n", __func__);
++
++	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++
++int c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	int ret = _FAIL;
++	int i;
++
++	if (len < CUSTOMER_STR_RPT_2_LEN) {
++		RTW_WARN("%s len(%u) < %d\n", __func__, len, CUSTOMER_STR_RPT_2_LEN);
++		goto exit;
++	}
++
++	if (DBG_CUSTOMER_STR_RPT_HANDLE)
++		RTW_PRINT_DUMP("customer_str_rpt_2: ", data, CUSTOMER_STR_RPT_2_LEN);
++
++	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
++
++	if (dvobj->customer_str_sctx != NULL) {
++		if (dvobj->customer_str_sctx->status != RTX_SCTX_CSTR_WAIT_RPT2)
++			RTW_WARN("%s rpt not ready\n", __func__);
++		_rtw_memcpy(dvobj->customer_str + CUSTOMER_STR_RPT_LEN,  C2H_CUSTOMER_STR_RPT_2_BYTE8(data), CUSTOMER_STR_RPT_2_LEN);
++		rtw_sctx_done(&dvobj->customer_str_sctx);
++	} else
++		RTW_WARN("%s sctx not set\n", __func__);
++
++	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++
++/* read customer str */
++s32 rtw_hal_customer_str_read(_adapter *adapter, u8 *cs)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct submit_ctx sctx;
++	s32 ret = _SUCCESS;
++
++	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
++	if (dvobj->customer_str_sctx != NULL)
++		ret = _FAIL;
++	else {
++		rtw_sctx_init(&sctx, 2 * 1000);
++		dvobj->customer_str_sctx = &sctx;
++	}
++	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
++
++	if (ret == _FAIL) {
++		RTW_WARN("%s another handle ongoing\n", __func__);
++		goto exit;
++	}
++
++	ret = rtw_customer_str_req_cmd(adapter);
++	if (ret != _SUCCESS) {
++		RTW_WARN("%s read cmd fail\n", __func__);
++		_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
++		dvobj->customer_str_sctx = NULL;
++		_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
++		goto exit;
++	}
++
++	/* wait till rpt done or timeout */
++	rtw_sctx_wait(&sctx, __func__);
++
++	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
++	dvobj->customer_str_sctx = NULL;
++	if (sctx.status == RTW_SCTX_DONE_SUCCESS)
++		_rtw_memcpy(cs, dvobj->customer_str, RTW_CUSTOMER_STR_LEN);
++	else
++		ret = _FAIL;
++	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
++
++exit:
++	return ret;
++}
++
++s32 rtw_hal_h2c_customer_str_write(_adapter *adapter, const u8 *cs)
++{
++	u8 h2c_data_w1[H2C_CUSTOMER_STR_W1_LEN] = {0};
++	u8 h2c_data_w2[H2C_CUSTOMER_STR_W2_LEN] = {0};
++	u8 h2c_data_w3[H2C_CUSTOMER_STR_W3_LEN] = {0};
++	s32 ret;
++
++	SET_H2CCMD_CUSTOMER_STR_W1_EN(h2c_data_w1, 1);
++	_rtw_memcpy(H2CCMD_CUSTOMER_STR_W1_BYTE0(h2c_data_w1), cs, 6);
++
++	SET_H2CCMD_CUSTOMER_STR_W2_EN(h2c_data_w2, 1);
++	_rtw_memcpy(H2CCMD_CUSTOMER_STR_W2_BYTE6(h2c_data_w2), cs + 6, 6);
++
++	SET_H2CCMD_CUSTOMER_STR_W3_EN(h2c_data_w3, 1);
++	_rtw_memcpy(H2CCMD_CUSTOMER_STR_W3_BYTE12(h2c_data_w3), cs + 6 + 6, 4);
++
++	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W1, H2C_CUSTOMER_STR_W1_LEN, h2c_data_w1);
++	if (ret != _SUCCESS) {
++		RTW_WARN("%s w1 fail\n", __func__);
++		goto exit;
++	}
++
++	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W2, H2C_CUSTOMER_STR_W2_LEN, h2c_data_w2);
++	if (ret != _SUCCESS) {
++		RTW_WARN("%s w2 fail\n", __func__);
++		goto exit;
++	}
++
++	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W3, H2C_CUSTOMER_STR_W3_LEN, h2c_data_w3);
++	if (ret != _SUCCESS) {
++		RTW_WARN("%s w3 fail\n", __func__);
++		goto exit;
++	}
++
++exit:
++	return ret;
++}
++
++/* write customer str and check if value reported is the same as requested */
++s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct submit_ctx sctx;
++	s32 ret = _SUCCESS;
++
++	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
++	if (dvobj->customer_str_sctx != NULL)
++		ret = _FAIL;
++	else {
++		rtw_sctx_init(&sctx, 2 * 1000);
++		dvobj->customer_str_sctx = &sctx;
++	}
++	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
++
++	if (ret == _FAIL) {
++		RTW_WARN("%s another handle ongoing\n", __func__);
++		goto exit;
++	}
++
++	ret = rtw_customer_str_write_cmd(adapter, cs);
++	if (ret != _SUCCESS) {
++		RTW_WARN("%s write cmd fail\n", __func__);
++		_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
++		dvobj->customer_str_sctx = NULL;
++		_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
++		goto exit;
++	}
++
++	ret = rtw_customer_str_req_cmd(adapter);
++	if (ret != _SUCCESS) {
++		RTW_WARN("%s read cmd fail\n", __func__);
++		_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
++		dvobj->customer_str_sctx = NULL;
++		_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
++		goto exit;
++	}
++
++	/* wait till rpt done or timeout */
++	rtw_sctx_wait(&sctx, __func__);
++
++	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
++	dvobj->customer_str_sctx = NULL;
++	if (sctx.status == RTW_SCTX_DONE_SUCCESS) {
++		if (_rtw_memcmp(cs, dvobj->customer_str, RTW_CUSTOMER_STR_LEN) != _TRUE) {
++			RTW_WARN("%s read back check fail\n", __func__);
++			RTW_INFO_DUMP("write req: ", cs, RTW_CUSTOMER_STR_LEN);
++			RTW_INFO_DUMP("read back: ", dvobj->customer_str, RTW_CUSTOMER_STR_LEN);
++			ret = _FAIL;
++		}
++	} else
++		ret = _FAIL;
++	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
++
++exit:
++	return ret;
++}
++#endif /* CONFIG_RTW_CUSTOMER_STR */
++
++#ifdef RTW_PER_CMD_SUPPORT_FW
++#define H2C_REQ_PER_RPT_LEN 5
++#define SET_H2CCMD_REQ_PER_RPT_GROUP_MACID(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
++#define SET_H2CCMD_REQ_PER_RPT_RPT_TYPE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
++#define SET_H2CCMD_REQ_PER_RPT_MACID_BMAP(__pH2CCmd, __Value)	SET_BITS_TO_LE_4BYTE(__pH2CCmd + 1, 0, 32, __Value)
++
++u8 rtw_hal_set_req_per_rpt_cmd(_adapter *adapter, u8 group_macid,
++				      u8 rpt_type, u32 macid_bitmap)
++{
++	u8 ret = _FAIL;
++	u8 cmd_buf[H2C_REQ_PER_RPT_LEN] = {0};
++
++	SET_H2CCMD_REQ_PER_RPT_GROUP_MACID(cmd_buf, group_macid);
++	SET_H2CCMD_REQ_PER_RPT_RPT_TYPE(cmd_buf, rpt_type);
++	SET_H2CCMD_REQ_PER_RPT_MACID_BMAP(cmd_buf, macid_bitmap);
++
++	ret = rtw_hal_fill_h2c_cmd(adapter, 
++				   H2C_REQ_PER_RPT, 
++				   H2C_REQ_PER_RPT_LEN, 
++				   cmd_buf);
++	return ret;
++}
++
++#define	GET_C2H_PER_RATE_RPT_TYPE0_MACID0(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)), 0, 8)
++#define	GET_C2H_PER_RATE_RPT_TYPE0_PER0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8)
++#define	GET_C2H_PER_RATE_RPT_TYPE0_RATE0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 8)
++#define	GET_C2H_PER_RATE_RPT_TYPE0_BW0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 3, 0, 2)
++#define	GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT0(_data)	LE_BITS_TO_2BYTE(((u8 *)(_data)) + 4, 0, 16)
++#define	GET_C2H_PER_RATE_RPT_TYPE0_MACID1(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 8)
++#define	GET_C2H_PER_RATE_RPT_TYPE0_PER1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 0, 8)
++#define	GET_C2H_PER_RATE_RPT_TYPE0_RATE1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 8, 0, 8)
++#define	GET_C2H_PER_RATE_RPT_TYPE0_BW1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 9, 0, 2)
++#define	GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT1(_data)	LE_BITS_TO_2BYTE(((u8 *)(_data)) + 10, 0, 16)
++
++#define	GET_C2H_PER_RATE_RPT_TYPE1_MACID0(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)), 0, 8)
++#define	GET_C2H_PER_RATE_RPT_TYPE1_PER0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8)
++#define	GET_C2H_PER_RATE_RPT_TYPE1_RATE0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 8)
++#define	GET_C2H_PER_RATE_RPT_TYPE1_BW0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 3, 0, 2)
++#define	GET_C2H_PER_RATE_RPT_TYPE1_MACID1(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 0, 8)
++#define	GET_C2H_PER_RATE_RPT_TYPE1_PER1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 0, 8)
++#define	GET_C2H_PER_RATE_RPT_TYPE1_RATE1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 8)
++#define	GET_C2H_PER_RATE_RPT_TYPE1_BW1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 0, 2)
++#define	GET_C2H_PER_RATE_RPT_TYPE1_MACID2(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)) + 8, 0, 8)
++#define	GET_C2H_PER_RATE_RPT_TYPE1_PER2(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 9, 0, 8)
++#define	GET_C2H_PER_RATE_RPT_TYPE1_RATE2(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 10, 0, 8)
++#define	GET_C2H_PER_RATE_RPT_TYPE1_BW2(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 11, 0, 2)
++
++static void per_rate_rpt_update(_adapter *adapter, u8 mac_id,
++				u8 per, u8 rate,
++				u8 bw, u8 total_pkt)
++{
++#ifdef CONFIG_RTW_MESH
++	rtw_ieee80211s_update_metric(adapter, mac_id,
++				     per, rate,
++				     bw, total_pkt);
++#endif
++}
++
++int c2h_per_rate_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
++{
++	/* Now only consider type0, since it covers all params in type1
++	 * type0: mac_id, per, rate, bw, total_pkt
++	 * type1: mac_id, per, rate, bw
++	 */
++	u8 mac_id[2] = {0}, per[2] = {0}, rate[2] = {0}, bw[2] = {0};
++	u16 total_pkt[2] = {0};
++	int ret = _FAIL, i, macid_cnt = 0;
++
++	/* type0:
++	 * 1 macid includes   6 bytes info + 1 byte 0xff
++	 * 2 macid includes 2*6 bytes info
++	 */
++	if (!(len == 7 || len == 12)) {
++		RTW_WARN("%s len(%u) != 7 or 12\n", __FUNCTION__, len);
++		goto exit;
++	}
++
++	macid_cnt++;
++	mac_id[0] = GET_C2H_PER_RATE_RPT_TYPE0_MACID0(data);
++	per[0] = GET_C2H_PER_RATE_RPT_TYPE0_PER0(data);
++	rate[0] = GET_C2H_PER_RATE_RPT_TYPE0_RATE0(data);
++	bw[0] = GET_C2H_PER_RATE_RPT_TYPE0_BW0(data);
++	total_pkt[0] = GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT0(data);
++
++	mac_id[1] = GET_C2H_PER_RATE_RPT_TYPE0_MACID1(data);
++	/* 0xff means no report anymore */
++	if (mac_id[1] == 0xff)
++		goto update_per;
++	if (len != 12) {
++		RTW_WARN("%s incorrect format\n", __FUNCTION__);
++		goto exit;
++	}
++	macid_cnt++;
++	per[1] = GET_C2H_PER_RATE_RPT_TYPE0_PER1(data);
++	rate[1] = GET_C2H_PER_RATE_RPT_TYPE0_RATE1(data);
++	bw[1] = GET_C2H_PER_RATE_RPT_TYPE0_BW1(data);
++	total_pkt[1] = GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT1(data);
++
++update_per:
++	for (i = 0; i < macid_cnt; i++) {
++		RTW_DBG("[%s] type0 rpt[%d]: macid = %u, per = %u, "
++			"rate = %u, bw = %u, total_pkt = %u\n",
++			__FUNCTION__, i, mac_id[i], per[i],
++			rate[i], bw[i], total_pkt[i]);
++		per_rate_rpt_update(adapter, mac_id[i],
++				    per[i], rate[i],
++				    bw[i], total_pkt[i]);
++	}
++	ret = _SUCCESS;
++exit:
++	return ret;
++}
++#endif /* RTW_PER_CMD_SUPPORT_FW */
++
++#ifdef CONFIG_LPS_ACK
++#define	GET_C2H_LPS_STATUS_RPT_GET_ACTION(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)), 0, 8)
++#define	GET_C2H_LPS_STATUS_RPT_GET_STATUS_CODE(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8)
++#define DBG_LPS_STATUS_RPT 0
++
++int c2h_lps_status_rpt(PADAPTER adapter, u8 *data, u8 len)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	struct submit_ctx *lps_sctx = &pwrpriv->lps_ack_sctx;
++	u8 action = 0;
++	s8 status_code = 0;
++	int ret = _FAIL;
++
++	if (len < LPS_STATUS_RPT_LEN) {
++		RTW_WARN("%s len(%u) < %d\n", __func__, len, LPS_STATUS_RPT_LEN);
++		goto exit;
++	}
++
++	action = GET_C2H_LPS_STATUS_RPT_GET_ACTION(data);
++	status_code = GET_C2H_LPS_STATUS_RPT_GET_STATUS_CODE(data);
++
++	/* action=0: report force leave null data status */
++	/* action=1: report Rf on status when receiving a SetPwrMode H2C with PwrState = RFON */
++	switch (action) {
++		case 0: 
++			/* status code 0: success, 1: no ack, 2: timeout, 3: cancel */
++		case 1: 
++			/* status code 0: FW has already turn to RFON */
++			pwrpriv->lps_ack_status = status_code;
++
++			if (DBG_LPS_STATUS_RPT)
++				RTW_INFO("=== [C2H LPS Action(%d)] LPS Status Code:%d ===\n", action, status_code);
++			
++			break;
++		default:
++			RTW_INFO("UnKnown Action(%d) for C2H LPS RPT\n", action);
++			break;
++	}
++
++	rtw_sctx_done(&lps_sctx);
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++#endif /* CONFIG_LPS_ACK */
++
++void rtw_hal_update_sta_wset(_adapter *adapter, struct sta_info *psta)
++{
++	u8 w_set = 0;
++
++	if (psta->wireless_mode & WIRELESS_11B)
++		w_set |= WIRELESS_CCK;
++
++	if ((psta->wireless_mode & WIRELESS_11G) || (psta->wireless_mode & WIRELESS_11A))
++		w_set |= WIRELESS_OFDM;
++
++	if (psta->wireless_mode & WIRELESS_11_24N)
++		w_set |= WIRELESS_HT;
++
++	if ((psta->wireless_mode & WIRELESS_11AC) || (psta->wireless_mode & WIRELESS_11_5N))
++		w_set |= WIRELESS_VHT;
++
++	psta->cmn.support_wireless_set = w_set;
++}
++
++void rtw_hal_update_sta_mimo_type(_adapter *adapter, struct sta_info *psta)
++{
++	s8 tx_nss, rx_nss;
++
++	tx_nss = rtw_get_sta_tx_nss(adapter, psta);
++	rx_nss =  rtw_get_sta_rx_nss(adapter, psta);
++	if ((tx_nss == 1) && (rx_nss == 1))
++		psta->cmn.mimo_type = RF_1T1R;
++	else if ((tx_nss == 1) && (rx_nss == 2))
++		psta->cmn.mimo_type = RF_1T2R;
++	else if ((tx_nss == 2) && (rx_nss == 2))
++		psta->cmn.mimo_type = RF_2T2R;
++	else if ((tx_nss == 2) && (rx_nss == 3))
++		psta->cmn.mimo_type = RF_2T3R;
++	else if ((tx_nss == 2) && (rx_nss == 4))
++		psta->cmn.mimo_type = RF_2T4R;
++	else if ((tx_nss == 3) && (rx_nss == 3))
++		psta->cmn.mimo_type = RF_3T3R;
++	else if ((tx_nss == 3) && (rx_nss == 4))
++		psta->cmn.mimo_type = RF_3T4R;
++	else if ((tx_nss == 4) && (rx_nss == 4))
++		psta->cmn.mimo_type = RF_4T4R;
++	else
++		rtw_warn_on(1);
++
++#ifdef CONFIG_CTRL_TXSS_BY_TP
++	rtw_ctrl_txss_update_mimo_type(adapter, psta);
++#endif
++
++	RTW_INFO("STA - MAC_ID:%d, Tx - %d SS, Rx - %d SS\n",
++			psta->cmn.mac_id, tx_nss, rx_nss);
++}
++
++void rtw_hal_update_sta_smps_cap(_adapter *adapter, struct sta_info *psta)
++{
++	/*Spatial Multiplexing Power Save*/
++#if 0
++	if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) {
++		#ifdef CONFIG_80211N_HT
++		if (psta->htpriv.ht_option) {
++			if (psta->htpriv.smps_cap == 0)
++				psta->cmn.sm_ps = SM_PS_STATIC;
++			else if (psta->htpriv.smps_cap == 1)
++				psta->cmn.sm_ps = SM_PS_DYNAMIC;
++			else
++				psta->cmn.sm_ps = SM_PS_DISABLE;
++		}
++		#endif /* CONFIG_80211N_HT */
++	} else
++#endif
++		psta->cmn.sm_ps = SM_PS_DISABLE;
++
++	RTW_INFO("STA - MAC_ID:%d, SM_PS %d\n",
++			psta->cmn.mac_id, psta->cmn.sm_ps);
++}
++
++u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type)
++{
++
++	u8 raid;
++	if (IS_NEW_GENERATION_IC(adapter)) {
++
++		raid = (network_type & WIRELESS_11B)	? RATEID_IDX_B
++		       : RATEID_IDX_G;
++	} else {
++		raid = (network_type & WIRELESS_11B)	? RATR_INX_WIRELESS_B
++		       : RATR_INX_WIRELESS_G;
++	}
++	return raid;
++}
++
++void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta)
++{
++	u8 i, tx_nss;
++	u64 tx_ra_bitmap = 0, tmp64=0;
++
++	if (psta == NULL)
++		return;
++
++	/* b/g mode ra_bitmap  */
++	for (i = 0; i < sizeof(psta->bssrateset); i++) {
++		if (psta->bssrateset[i])
++			tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i] & 0x7f);
++	}
++
++#ifdef CONFIG_80211N_HT
++if (padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode)) {
++	tx_nss = GET_HAL_TX_NSS(padapter);
++#ifdef CONFIG_80211AC_VHT
++	if (psta->vhtpriv.vht_option) {
++		/* AC mode ra_bitmap */
++		tx_ra_bitmap |= (rtw_vht_mcs_map_to_bitmap(psta->vhtpriv.vht_mcs_map, tx_nss) << 12);
++	} else
++#endif /* CONFIG_80211AC_VHT */
++	if (psta->htpriv.ht_option) {
++		/* n mode ra_bitmap */
++
++		/* Handling SMPS mode for AP MODE only*/
++		if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) {
++			/*0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/
++			if (psta->htpriv.smps_cap == 0 || psta->htpriv.smps_cap == 1) {
++				/*operate with only one active receive chain // 11n-MCS rate <= MSC7*/
++				tx_nss = rtw_min(tx_nss, 1);
++			}
++		}
++
++		tmp64 = rtw_ht_mcs_set_to_bitmap(psta->htpriv.ht_cap.supp_mcs_set, tx_nss);
++		tx_ra_bitmap |= (tmp64 << 12);
++	}
++}
++#endif /* CONFIG_80211N_HT */
++	psta->cmn.ra_info.ramask = tx_ra_bitmap;
++	psta->init_rate = get_highest_rate_idx(tx_ra_bitmap) & 0x3f;
++}
++
++void rtw_hal_update_sta_ra_info(PADAPTER padapter, struct sta_info *psta)
++{
++	rtw_hal_update_sta_mimo_type(padapter, psta);
++	rtw_hal_update_sta_smps_cap(padapter, psta);
++	rtw_hal_update_sta_rate_mask(padapter, psta);
++}
++
++#ifndef CONFIG_HAS_HW_VAR_BCN_CTRL_ADDR
++static u32 hw_bcn_ctrl_addr(_adapter *adapter, u8 hw_port)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++
++	if (hw_port >= hal_spec->port_num) {
++		RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port);
++		rtw_warn_on(1);
++		return 0;
++	}
++
++	switch (hw_port) {
++	case HW_PORT0:
++		return REG_BCN_CTRL;
++	case HW_PORT1:
++		return REG_BCN_CTRL_1;
++	}
++
++	return 0;
++}
++#endif
++
++static void rtw_hal_get_msr(_adapter *adapter, u8 *net_type)
++{
++#ifdef RTW_HALMAC
++	rtw_halmac_get_network_type(adapter_to_dvobj(adapter),
++				adapter->hw_port, net_type);
++#else /* !RTW_HALMAC */
++	switch (adapter->hw_port) {
++	case HW_PORT0:
++		/*REG_CR - BIT[17:16]-Network Type for port 1*/
++		*net_type = rtw_read8(adapter, MSR) & 0x03;
++		break;
++	case HW_PORT1:
++		/*REG_CR - BIT[19:18]-Network Type for port 1*/
++		*net_type = (rtw_read8(adapter, MSR) & 0x0C) >> 2;
++		break;
++#if defined(CONFIG_RTL8814A)
++	case HW_PORT2:
++		/*REG_CR_EXT- BIT[1:0]-Network Type for port 2*/
++		*net_type = rtw_read8(adapter, MSR1) & 0x03;
++		break;
++	case HW_PORT3:
++		/*REG_CR_EXT- BIT[3:2]-Network Type for port 3*/
++		*net_type = (rtw_read8(adapter, MSR1) & 0x0C) >> 2;
++		break;
++	case HW_PORT4:
++		/*REG_CR_EXT- BIT[5:4]-Network Type for port 4*/
++		*net_type = (rtw_read8(adapter, MSR1) & 0x30) >> 4;
++		break;
++#endif /*#if defined(CONFIG_RTL8814A)*/
++	default:
++		RTW_INFO("[WARN] "ADPT_FMT"- invalid hw port -%d\n",
++			 ADPT_ARG(adapter), adapter->hw_port);
++		rtw_warn_on(1);
++		break;
++	}
++#endif /* !RTW_HALMAC */
++}
++
++#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM) /*For 2 hw ports - 88E/92E/8812/8821/8723B*/
++static u8 rtw_hal_net_type_decision(_adapter *adapter, u8 net_type)
++{
++	if ((adapter->hw_port == HW_PORT0) && (rtw_get_mbid_cam_entry_num(adapter))) {
++		if (net_type != _HW_STATE_NOLINK_)
++			return _HW_STATE_AP_;
++	}
++	return net_type;
++}
++#endif
++static void rtw_hal_set_msr(_adapter *adapter, u8 net_type)
++{
++#ifdef RTW_HALMAC
++	#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM)
++	net_type = rtw_hal_net_type_decision(adapter, net_type);
++	#endif
++	rtw_halmac_set_network_type(adapter_to_dvobj(adapter),
++				adapter->hw_port, net_type);
++#else /* !RTW_HALMAC */
++	u8 val8 = 0;
++
++	switch (adapter->hw_port) {
++	case HW_PORT0:
++		#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM)
++		net_type = rtw_hal_net_type_decision(adapter, net_type);
++		#endif
++		/*REG_CR - BIT[17:16]-Network Type for port 0*/
++		val8 = rtw_read8(adapter, MSR) & 0x0C;
++		val8 |= net_type;
++		rtw_write8(adapter, MSR, val8);
++		break;
++	case HW_PORT1:
++		/*REG_CR - BIT[19:18]-Network Type for port 1*/
++		val8 = rtw_read8(adapter, MSR) & 0x03;
++		val8 |= net_type << 2;
++		rtw_write8(adapter, MSR, val8);
++		break;
++#if defined(CONFIG_RTL8814A)
++	case HW_PORT2:
++		/*REG_CR_EXT- BIT[1:0]-Network Type for port 2*/
++		val8 = rtw_read8(adapter, MSR1) & 0xFC;
++		val8 |= net_type;
++		rtw_write8(adapter, MSR1, val8);
++		break;
++	case HW_PORT3:
++		/*REG_CR_EXT- BIT[3:2]-Network Type for port 3*/
++		val8 = rtw_read8(adapter, MSR1) & 0xF3;
++		val8 |= net_type << 2;
++		rtw_write8(adapter, MSR1, val8);
++		break;
++	case HW_PORT4:
++		/*REG_CR_EXT- BIT[5:4]-Network Type for port 4*/
++		val8 = rtw_read8(adapter, MSR1) & 0xCF;
++		val8 |= net_type << 4;
++		rtw_write8(adapter, MSR1, val8);
++		break;
++#endif /* CONFIG_RTL8814A */
++	default:
++		RTW_INFO("[WARN] "ADPT_FMT"- invalid hw port -%d\n",
++			 ADPT_ARG(adapter), adapter->hw_port);
++		rtw_warn_on(1);
++		break;
++	}
++#endif /* !RTW_HALMAC */
++}
++
++#ifndef SEC_CAM_ACCESS_TIMEOUT_MS
++	#define SEC_CAM_ACCESS_TIMEOUT_MS 200
++#endif
++
++#ifndef DBG_SEC_CAM_ACCESS
++	#define DBG_SEC_CAM_ACCESS 0
++#endif
++
++u32 rtw_sec_read_cam(_adapter *adapter, u8 addr)
++{
++	_mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex;
++	u32 rdata;
++	u32 cnt = 0;
++	systime start = 0, end = 0;
++	u8 timeout = 0;
++	u8 sr = 0;
++
++	_enter_critical_mutex(mutex, NULL);
++
++	rtw_write32(adapter, REG_CAMCMD, CAM_POLLINIG | addr);
++
++	start = rtw_get_current_time();
++	while (1) {
++		if (rtw_is_surprise_removed(adapter)) {
++			sr = 1;
++			break;
++		}
++
++		cnt++;
++		if (0 == (rtw_read32(adapter, REG_CAMCMD) & CAM_POLLINIG))
++			break;
++
++		if (rtw_get_passing_time_ms(start) > SEC_CAM_ACCESS_TIMEOUT_MS) {
++			timeout = 1;
++			break;
++		}
++	}
++	end = rtw_get_current_time();
++
++	rdata = rtw_read32(adapter, REG_CAMREAD);
++
++	_exit_critical_mutex(mutex, NULL);
++
++	if (DBG_SEC_CAM_ACCESS || timeout) {
++		RTW_INFO(FUNC_ADPT_FMT" addr:0x%02x, rdata:0x%08x, to:%u, polling:%u, %d ms\n"
++			, FUNC_ADPT_ARG(adapter), addr, rdata, timeout, cnt, rtw_get_time_interval_ms(start, end));
++	}
++
++	return rdata;
++}
++
++void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata)
++{
++	_mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex;
++	u32 cnt = 0;
++	systime start = 0, end = 0;
++	u8 timeout = 0;
++	u8 sr = 0;
++
++	_enter_critical_mutex(mutex, NULL);
++
++	rtw_write32(adapter, REG_CAMWRITE, wdata);
++	rtw_write32(adapter, REG_CAMCMD, CAM_POLLINIG | CAM_WRITE | addr);
++
++	start = rtw_get_current_time();
++	while (1) {
++		if (rtw_is_surprise_removed(adapter)) {
++			sr = 1;
++			break;
++		}
++
++		cnt++;
++		if (0 == (rtw_read32(adapter, REG_CAMCMD) & CAM_POLLINIG))
++			break;
++
++		if (rtw_get_passing_time_ms(start) > SEC_CAM_ACCESS_TIMEOUT_MS) {
++			timeout = 1;
++			break;
++		}
++	}
++	end = rtw_get_current_time();
++
++	_exit_critical_mutex(mutex, NULL);
++
++	if (DBG_SEC_CAM_ACCESS || timeout) {
++		RTW_INFO(FUNC_ADPT_FMT" addr:0x%02x, wdata:0x%08x, to:%u, polling:%u, %d ms\n"
++			, FUNC_ADPT_ARG(adapter), addr, wdata, timeout, cnt, rtw_get_time_interval_ms(start, end));
++	}
++}
++
++void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key)
++{
++	u8 i;
++	u32 rdata;
++	u8 begin = 0;
++	u8 end = 5; /* TODO: consider other key length accordingly */
++
++	if (!ctrl && !mac && !key) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	/* TODO: check id range */
++
++	if (!ctrl && !mac)
++		begin = 2; /* read from key */
++
++	if (!key && !mac)
++		end = 0; /* read to ctrl */
++	else if (!key)
++		end = 2; /* read to mac */
++
++	for (i = begin; i <= end; i++) {
++		rdata = rtw_sec_read_cam(adapter, (id << 3) | i);
++
++		switch (i) {
++		case 0:
++			if (ctrl)
++				_rtw_memcpy(ctrl, (u8 *)(&rdata), 2);
++			if (mac)
++				_rtw_memcpy(mac, ((u8 *)(&rdata)) + 2, 2);
++			break;
++		case 1:
++			if (mac)
++				_rtw_memcpy(mac + 2, (u8 *)(&rdata), 4);
++			break;
++		default:
++			if (key)
++				_rtw_memcpy(key + (i - 2) * 4, (u8 *)(&rdata), 4);
++			break;
++		}
++	}
++
++exit:
++	return;
++}
++
++
++void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)
++{
++	unsigned int i;
++	int j;
++	u8 addr, addr1 = 0;
++	u32 wdata, wdata1 = 0;
++
++	/* TODO: consider other key length accordingly */
++#if 0
++	switch ((ctrl & 0x1c) >> 2) {
++	case _WEP40_:
++	case _TKIP_:
++	case _AES_:
++	case _WEP104_:
++
++	}
++#else
++	j = 7;
++#endif
++
++	for (; j >= 0; j--) {
++		switch (j) {
++		case 0:
++			wdata = (ctrl | (mac[0] << 16) | (mac[1] << 24));
++			break;
++		case 1:
++			wdata = (mac[2] | (mac[3] << 8) | (mac[4] << 16) | (mac[5] << 24));
++			break;
++		case 6:
++		case 7:
++			wdata = 0;
++			break;
++		default:
++			i = (j - 2) << 2;
++			wdata = (key[i] | (key[i + 1] << 8) | (key[i + 2] << 16) | (key[i + 3] << 24));
++			break;
++		}
++
++		addr = (id << 3) + j;
++
++#if defined(CONFIG_RTL8192F)
++		if(j == 1) {
++			wdata1 = wdata;
++			addr1 = addr;
++			continue;
++		}
++#endif
++
++		rtw_sec_write_cam(adapter, addr, wdata);
++	}
++
++#if defined(CONFIG_RTL8192F)
++	rtw_sec_write_cam(adapter, addr1, wdata1);
++#endif
++}
++
++void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id)
++{
++	u8 addr;
++
++	addr = (id << 3);
++	rtw_sec_write_cam(adapter, addr, 0);
++}
++
++bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id)
++{
++	bool res;
++	u16 ctrl;
++
++	rtw_sec_read_cam_ent(adapter, id, (u8 *)&ctrl, NULL, NULL);
++
++	res = (ctrl & BIT6) ? _TRUE : _FALSE;
++	return res;
++}
++#ifdef CONFIG_MBSSID_CAM
++void rtw_mbid_cam_init(struct dvobj_priv *dvobj)
++{
++	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
++
++	_rtw_spinlock_init(&mbid_cam_ctl->lock);
++	mbid_cam_ctl->bitmap = 0;
++	ATOMIC_SET(&mbid_cam_ctl->mbid_entry_num, 0);
++	_rtw_memset(&dvobj->mbid_cam_cache, 0, sizeof(dvobj->mbid_cam_cache));
++}
++
++void rtw_mbid_cam_deinit(struct dvobj_priv *dvobj)
++{
++	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
++
++	_rtw_spinlock_free(&mbid_cam_ctl->lock);
++}
++
++void rtw_mbid_cam_reset(_adapter *adapter)
++{
++	_irqL irqL;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
++
++	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
++	mbid_cam_ctl->bitmap = 0;
++	_rtw_memset(&dvobj->mbid_cam_cache, 0, sizeof(dvobj->mbid_cam_cache));
++	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
++
++	ATOMIC_SET(&mbid_cam_ctl->mbid_entry_num, 0);
++}
++static u8 _rtw_mbid_cam_search_by_macaddr(_adapter *adapter, u8 *mac_addr)
++{
++	u8 i;
++	u8 cam_id = INVALID_CAM_ID;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
++		if (mac_addr && _rtw_memcmp(dvobj->mbid_cam_cache[i].mac_addr, mac_addr, ETH_ALEN) == _TRUE) {
++			cam_id = i;
++			break;
++		}
++	}
++
++	RTW_INFO("%s mac:"MAC_FMT" - cam_id:%d\n", __func__, MAC_ARG(mac_addr), cam_id);
++	return cam_id;
++}
++
++u8 rtw_mbid_cam_search_by_macaddr(_adapter *adapter, u8 *mac_addr)
++{
++	_irqL irqL;
++
++	u8 cam_id = INVALID_CAM_ID;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
++
++	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
++	cam_id = _rtw_mbid_cam_search_by_macaddr(adapter, mac_addr);
++	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
++
++	return cam_id;
++}
++static u8 _rtw_mbid_cam_search_by_ifaceid(_adapter *adapter, u8 iface_id)
++{
++	u8 i;
++	u8 cam_id = INVALID_CAM_ID;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
++		if (iface_id == dvobj->mbid_cam_cache[i].iface_id) {
++			cam_id = i;
++			break;
++		}
++	}
++	if (cam_id != INVALID_CAM_ID)
++		RTW_INFO("%s iface_id:%d mac:"MAC_FMT" - cam_id:%d\n",
++			__func__, iface_id, MAC_ARG(dvobj->mbid_cam_cache[cam_id].mac_addr), cam_id);
++
++	return cam_id;
++}
++
++u8 rtw_mbid_cam_search_by_ifaceid(_adapter *adapter, u8 iface_id)
++{
++	_irqL irqL;
++	u8 cam_id = INVALID_CAM_ID;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
++
++	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
++	cam_id = _rtw_mbid_cam_search_by_ifaceid(adapter, iface_id);
++	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
++
++	return cam_id;
++}
++u8 rtw_get_max_mbid_cam_id(_adapter *adapter)
++{
++	_irqL irqL;
++	s8 i;
++	u8 cam_id = INVALID_CAM_ID;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
++
++	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
++	for (i = (TOTAL_MBID_CAM_NUM - 1); i >= 0; i--) {
++		if (mbid_cam_ctl->bitmap & BIT(i)) {
++			cam_id = i;
++			break;
++		}
++	}
++	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
++	/*RTW_INFO("%s max cam_id:%d\n", __func__, cam_id);*/
++	return cam_id;
++}
++
++inline u8 rtw_get_mbid_cam_entry_num(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
++
++	return ATOMIC_READ(&mbid_cam_ctl->mbid_entry_num);
++}
++
++static inline void mbid_cam_cache_init(_adapter *adapter, struct mbid_cam_cache *pmbid_cam, u8 *mac_addr)
++{
++	if (adapter && pmbid_cam && mac_addr) {
++		_rtw_memcpy(pmbid_cam->mac_addr, mac_addr, ETH_ALEN);
++		pmbid_cam->iface_id = adapter->iface_id;
++	}
++}
++static inline void mbid_cam_cache_clr(struct mbid_cam_cache *pmbid_cam)
++{
++	if (pmbid_cam) {
++		_rtw_memset(pmbid_cam->mac_addr, 0, ETH_ALEN);
++		pmbid_cam->iface_id = CONFIG_IFACE_NUMBER;
++	}
++}
++
++u8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr)
++{
++	_irqL irqL;
++	u8 cam_id = INVALID_CAM_ID, i;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
++	u8 entry_num = ATOMIC_READ(&mbid_cam_ctl->mbid_entry_num);
++
++	if (INVALID_CAM_ID != rtw_mbid_cam_search_by_macaddr(adapter, mac_addr))
++		goto exit;
++
++	if (entry_num >= TOTAL_MBID_CAM_NUM) {
++		RTW_INFO(FUNC_ADPT_FMT" failed !! MBSSID number :%d over TOTAL_CAM_ENTRY(8)\n", FUNC_ADPT_ARG(adapter), entry_num);
++		rtw_warn_on(1);
++	}
++
++	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
++	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
++		if (!(mbid_cam_ctl->bitmap & BIT(i))) {
++			mbid_cam_ctl->bitmap |= BIT(i);
++			cam_id = i;
++			break;
++		}
++	}
++	if ((cam_id != INVALID_CAM_ID) && (mac_addr))
++		mbid_cam_cache_init(adapter, &dvobj->mbid_cam_cache[cam_id], mac_addr);
++	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
++
++	if (cam_id != INVALID_CAM_ID) {
++		ATOMIC_INC(&mbid_cam_ctl->mbid_entry_num);
++		RTW_INFO("%s mac:"MAC_FMT" - cam_id:%d\n", __func__, MAC_ARG(mac_addr), cam_id);
++#ifdef DBG_MBID_CAM_DUMP
++		rtw_mbid_cam_cache_dump(RTW_DBGDUMP, __func__, adapter);
++#endif
++	} else
++		RTW_INFO("%s [WARN] "MAC_FMT" - invalid cam_id:%d\n", __func__, MAC_ARG(mac_addr), cam_id);
++exit:
++	return cam_id;
++}
++
++u8 rtw_mbid_cam_info_change(_adapter *adapter, u8 *mac_addr)
++{
++	_irqL irqL;
++	u8 entry_id = INVALID_CAM_ID;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
++
++	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
++	entry_id = _rtw_mbid_cam_search_by_ifaceid(adapter, adapter->iface_id);
++	if (entry_id != INVALID_CAM_ID)
++		mbid_cam_cache_init(adapter, &dvobj->mbid_cam_cache[entry_id], mac_addr);
++
++	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
++
++	return entry_id;
++}
++
++u8 rtw_mbid_cam_assign(_adapter *adapter, u8 *mac_addr, u8 camid)
++{
++	_irqL irqL;
++	u8 ret = _FALSE;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
++
++	if ((camid >= TOTAL_MBID_CAM_NUM) || (camid == INVALID_CAM_ID)) {
++		RTW_INFO(FUNC_ADPT_FMT" failed !! invlaid mbid_canid :%d\n", FUNC_ADPT_ARG(adapter), camid);
++		rtw_warn_on(1);
++	}
++	if (INVALID_CAM_ID != rtw_mbid_cam_search_by_macaddr(adapter, mac_addr))
++		goto exit;
++
++	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
++	if (!(mbid_cam_ctl->bitmap & BIT(camid))) {
++		if (mac_addr) {
++			mbid_cam_ctl->bitmap |= BIT(camid);
++			mbid_cam_cache_init(adapter, &dvobj->mbid_cam_cache[camid], mac_addr);
++			ret = _TRUE;
++		}
++	}
++	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
++
++	if (ret == _TRUE) {
++		ATOMIC_INC(&mbid_cam_ctl->mbid_entry_num);
++		RTW_INFO("%s mac:"MAC_FMT" - cam_id:%d\n", __func__, MAC_ARG(mac_addr), camid);
++#ifdef DBG_MBID_CAM_DUMP
++		rtw_mbid_cam_cache_dump(RTW_DBGDUMP, __func__, adapter);
++#endif
++	} else
++		RTW_INFO("%s  [WARN] mac:"MAC_FMT" - cam_id:%d assigned failed\n", __func__, MAC_ARG(mac_addr), camid);
++
++exit:
++	return ret;
++}
++
++void rtw_mbid_camid_clean(_adapter *adapter, u8 mbss_canid)
++{
++	_irqL irqL;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
++
++	if ((mbss_canid >= TOTAL_MBID_CAM_NUM) || (mbss_canid == INVALID_CAM_ID)) {
++		RTW_INFO(FUNC_ADPT_FMT" failed !! invlaid mbid_canid :%d\n", FUNC_ADPT_ARG(adapter), mbss_canid);
++		rtw_warn_on(1);
++	}
++	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
++	mbid_cam_cache_clr(&dvobj->mbid_cam_cache[mbss_canid]);
++	mbid_cam_ctl->bitmap &= (~BIT(mbss_canid));
++	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
++	ATOMIC_DEC(&mbid_cam_ctl->mbid_entry_num);
++	RTW_INFO("%s - cam_id:%d\n", __func__, mbss_canid);
++}
++int rtw_mbid_cam_cache_dump(void *sel, const char *fun_name, _adapter *adapter)
++{
++	_irqL irqL;
++	u8 i;
++	_adapter *iface;
++	u8 iface_id;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
++	u8 entry_num = ATOMIC_READ(&mbid_cam_ctl->mbid_entry_num);
++	u8 max_cam_id = rtw_get_max_mbid_cam_id(adapter);
++
++	RTW_PRINT_SEL(sel, "== MBSSID CAM DUMP (%s)==\n", fun_name);
++
++	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
++	RTW_PRINT_SEL(sel, "Entry numbers:%d, max_camid:%d, bitmap:0x%08x\n", entry_num, max_cam_id, mbid_cam_ctl->bitmap);
++	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
++		RTW_PRINT_SEL(sel, "CAM_ID = %d\t", i);
++
++		if (mbid_cam_ctl->bitmap & BIT(i)) {
++			iface_id = dvobj->mbid_cam_cache[i].iface_id;
++			_RTW_PRINT_SEL(sel, "IF_ID:%d\t", iface_id);
++			_RTW_PRINT_SEL(sel, "MAC Addr:"MAC_FMT"\t", MAC_ARG(dvobj->mbid_cam_cache[i].mac_addr));
++
++			iface = dvobj->padapters[iface_id];
++			if (iface) {
++				if (MLME_IS_STA(iface))
++					_RTW_PRINT_SEL(sel, "ROLE:%s\n", "STA");
++				else if (MLME_IS_AP(iface))
++					_RTW_PRINT_SEL(sel, "ROLE:%s\n", "AP");
++				else if (MLME_IS_MESH(iface))
++					_RTW_PRINT_SEL(sel, "ROLE:%s\n", "MESH");
++				else
++					_RTW_PRINT_SEL(sel, "ROLE:%s\n", "NONE");
++			}
++
++		} else
++			_RTW_PRINT_SEL(sel, "N/A\n");
++	}
++	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
++	return 0;
++}
++
++static void read_mbssid_cam(_adapter *padapter, u8 cam_addr, u8 *mac)
++{
++	u8 poll = 1;
++	u8 cam_ready = _FALSE;
++	u32 cam_data1 = 0;
++	u16 cam_data2 = 0;
++
++	if (RTW_CANNOT_RUN(padapter))
++		return;
++
++	rtw_write32(padapter, REG_MBIDCAMCFG_2, BIT_MBIDCAM_POLL | ((cam_addr & MBIDCAM_ADDR_MASK) << MBIDCAM_ADDR_SHIFT));
++
++	do {
++		if (0 == (rtw_read32(padapter, REG_MBIDCAMCFG_2) & BIT_MBIDCAM_POLL)) {
++			cam_ready = _TRUE;
++			break;
++		}
++		poll++;
++	} while ((poll % 10) != 0 && !RTW_CANNOT_RUN(padapter));
++
++	if (cam_ready) {
++		cam_data1 = rtw_read32(padapter, REG_MBIDCAMCFG_1);
++		mac[0] = cam_data1 & 0xFF;
++		mac[1] = (cam_data1 >> 8) & 0xFF;
++		mac[2] = (cam_data1 >> 16) & 0xFF;
++		mac[3] = (cam_data1 >> 24) & 0xFF;
++
++		cam_data2 = rtw_read16(padapter, REG_MBIDCAMCFG_2);
++		mac[4] = cam_data2 & 0xFF;
++		mac[5] = (cam_data2 >> 8) & 0xFF;
++	}
++
++}
++int rtw_mbid_cam_dump(void *sel, const char *fun_name, _adapter *adapter)
++{
++	/*_irqL irqL;*/
++	u8 i;
++	u8 mac_addr[ETH_ALEN];
++
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
++
++	RTW_PRINT_SEL(sel, "\n== MBSSID HW-CAM DUMP (%s)==\n", fun_name);
++
++	/*_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);*/
++	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
++		RTW_PRINT_SEL(sel, "CAM_ID = %d\t", i);
++		_rtw_memset(mac_addr, 0, ETH_ALEN);
++		read_mbssid_cam(adapter, i, mac_addr);
++		_RTW_PRINT_SEL(sel, "MAC Addr:"MAC_FMT"\n", MAC_ARG(mac_addr));
++	}
++	/*_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);*/
++	return 0;
++}
++
++static void write_mbssid_cam(_adapter *padapter, u8 cam_addr, u8 *mac)
++{
++	u32	cam_val[2] = {0};
++
++	cam_val[0] = (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0];
++	cam_val[1] = ((cam_addr & MBIDCAM_ADDR_MASK) << MBIDCAM_ADDR_SHIFT)  | (mac[5] << 8) | mac[4];
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_MBSSID_CAM_WRITE, (u8 *)cam_val);
++}
++
++/*
++static void clear_mbssid_cam(_adapter *padapter, u8 cam_addr)
++{
++	rtw_hal_set_hwreg(padapter, HW_VAR_MBSSID_CAM_CLEAR, &cam_addr);
++}
++*/
++
++void rtw_ap_set_mbid_num(_adapter *adapter, u8 ap_num)
++{
++	rtw_write8(adapter, REG_MBID_NUM,
++		((rtw_read8(adapter, REG_MBID_NUM) & 0xF8) | ((ap_num -1) & 0x07)));
++
++}
++void rtw_mbid_cam_enable(_adapter *adapter)
++{
++	/*enable MBSSID*/
++	rtw_hal_rcr_add(adapter, RCR_ENMBID);
++}
++void rtw_mi_set_mbid_cam(_adapter *adapter)
++{
++	u8 i;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
++
++#ifdef DBG_MBID_CAM_DUMP
++	rtw_mbid_cam_cache_dump(RTW_DBGDUMP, __func__, adapter);
++#endif
++
++	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
++		if (mbid_cam_ctl->bitmap & BIT(i)) {
++			write_mbssid_cam(adapter, i, dvobj->mbid_cam_cache[i].mac_addr);
++			RTW_INFO("%s - cam_id:%d => mac:"MAC_FMT"\n", __func__, i, MAC_ARG(dvobj->mbid_cam_cache[i].mac_addr));
++		}
++	}
++	rtw_mbid_cam_enable(adapter);
++}
++#endif /*CONFIG_MBSSID_CAM*/
++
++#ifdef CONFIG_FW_HANDLE_TXBCN
++#define H2C_BCN_OFFLOAD_LEN	1
++
++#define SET_H2CCMD_BCN_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_H2CCMD_BCN_ROOT_TBTT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_H2CCMD_BCN_VAP1_TBTT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
++#define SET_H2CCMD_BCN_VAP2_TBTT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
++#define SET_H2CCMD_BCN_VAP3_TBTT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
++#define SET_H2CCMD_BCN_VAP4_TBTT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
++
++void rtw_hal_set_fw_ap_bcn_offload_cmd(_adapter *adapter, bool fw_bcn_en, u8 tbtt_rpt_map)
++{
++	u8 fw_bcn_offload[1] = {0};
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++	if (fw_bcn_en)
++		SET_H2CCMD_BCN_OFFLOAD_EN(fw_bcn_offload, 1);
++
++	if (tbtt_rpt_map & BIT(0))
++		SET_H2CCMD_BCN_ROOT_TBTT_RPT(fw_bcn_offload, 1);
++	if (tbtt_rpt_map & BIT(1))
++		SET_H2CCMD_BCN_VAP1_TBTT_RPT(fw_bcn_offload, 1);
++	if (tbtt_rpt_map & BIT(2))
++		SET_H2CCMD_BCN_VAP2_TBTT_RPT(fw_bcn_offload, 1);
++	if (tbtt_rpt_map & BIT(3))
++			SET_H2CCMD_BCN_VAP3_TBTT_RPT(fw_bcn_offload, 1);
++
++	dvobj->vap_tbtt_rpt_map = tbtt_rpt_map;
++	dvobj->fw_bcn_offload = fw_bcn_en;
++	RTW_INFO("[FW BCN] Offload : %s\n", (dvobj->fw_bcn_offload) ? "EN" : "DIS");
++	RTW_INFO("[FW BCN] TBTT RPT map : 0x%02x\n", dvobj->vap_tbtt_rpt_map);
++
++	rtw_hal_fill_h2c_cmd(adapter, H2C_FW_BCN_OFFLOAD,
++					H2C_BCN_OFFLOAD_LEN, fw_bcn_offload);
++}
++
++void rtw_hal_set_bcn_rsvdpage_loc_cmd(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	u8 ret, vap_id;
++	u32 page_size = 0;
++	u8 bcn_rsvdpage[H2C_BCN_RSVDPAGE_LEN] = {0};
++
++	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&page_size);
++	#if 1
++	for (vap_id = 0; vap_id < CONFIG_LIMITED_AP_NUM; vap_id++) {
++		if (dvobj->vap_map & BIT(vap_id))
++			bcn_rsvdpage[vap_id] = vap_id * (MAX_BEACON_LEN / page_size);
++	}
++	#else
++#define SET_H2CCMD_BCN_RSVDPAGE_LOC_ROOT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP1(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 8, __Value)
++#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP2(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 8, __Value)
++#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP3(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 8, __Value)
++#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP4(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 8, __Value)
++
++	if (dvobj->vap_map & BIT(0))
++ 		SET_H2CCMD_BCN_RSVDPAGE_LOC_ROOT(bcn_rsvdpage, 0);
++	if (dvobj->vap_map & BIT(1))
++		SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP1(bcn_rsvdpage,
++					1 * (MAX_BEACON_LEN / page_size));
++	if (dvobj->vap_map & BIT(2))
++		SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP2(bcn_rsvdpage,
++					2 * (MAX_BEACON_LEN / page_size));
++	if (dvobj->vap_map & BIT(3))
++		SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP3(bcn_rsvdpage,
++					3 * (MAX_BEACON_LEN / page_size));
++	if (dvobj->vap_map & BIT(4))
++		SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP4(bcn_rsvdpage,
++					4 * (MAX_BEACON_LEN / page_size));
++	#endif
++	if (1) {
++		RTW_INFO("[BCN_LOC] vap_map : 0x%02x\n", dvobj->vap_map);
++		RTW_INFO("[BCN_LOC] page_size :%d, @bcn_page_num :%d\n"
++			, page_size, (MAX_BEACON_LEN / page_size));
++		RTW_INFO("[BCN_LOC] root ap : 0x%02x\n", *bcn_rsvdpage);
++		RTW_INFO("[BCN_LOC] vap_1 : 0x%02x\n", *(bcn_rsvdpage + 1));
++		RTW_INFO("[BCN_LOC] vap_2 : 0x%02x\n", *(bcn_rsvdpage + 2));
++		RTW_INFO("[BCN_LOC] vap_3 : 0x%02x\n", *(bcn_rsvdpage + 3));
++		RTW_INFO("[BCN_LOC] vap_4 : 0x%02x\n", *(bcn_rsvdpage + 4));
++	}
++	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_BCN_RSVDPAGE,
++					H2C_BCN_RSVDPAGE_LEN, bcn_rsvdpage);
++}
++
++void rtw_ap_multi_bcn_cfg(_adapter *adapter)
++{
++	u8 dft_bcn_space = DEFAULT_BCN_INTERVAL;
++	u8 sub_bcn_space = (DEFAULT_BCN_INTERVAL / CONFIG_LIMITED_AP_NUM);
++
++	/*enable to rx data frame*/
++	rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);
++
++	/*Disable Port0's beacon function*/
++	rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL) & ~BIT_EN_BCN_FUNCTION);
++	/*Reset Port0's TSF*/
++	rtw_write8(adapter, REG_DUAL_TSF_RST, BIT_TSFTR_RST);
++
++	rtw_ap_set_mbid_num(adapter, CONFIG_LIMITED_AP_NUM);
++
++	/*BCN space & BCN sub-space 0x554[15:0] = 0x64,0x5BC[23:16] = 0x21*/
++	rtw_halmac_set_bcn_interval(adapter_to_dvobj(adapter), HW_PORT0, dft_bcn_space);
++	rtw_write8(adapter, REG_MBSSID_BCN_SPACE3 + 2, sub_bcn_space);
++
++	#if 0 /*setting in hw_var_set_opmode_mbid - ResumeTxBeacon*/
++	/*BCN hold time  0x540[19:8] = 0x80*/
++	rtw_write8(adapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME & 0xFF);
++	rtw_write8(adapter, REG_TBTT_PROHIBIT + 2,
++		(rtw_read8(adapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME >> 8));
++	#endif
++
++	/*ATIM window -0x55A = 0x32, reg 0x570 = 0x32, reg 0x5A0 = 0x32 */
++	rtw_write8(adapter, REG_ATIMWND, 0x32);
++	rtw_write8(adapter, REG_ATIMWND1_V1, 0x32);
++	rtw_write8(adapter, REG_ATIMWND2, 0x32);
++	rtw_write8(adapter, REG_ATIMWND3, 0x32);
++	/*
++	rtw_write8(adapter, REG_ATIMWND4, 0x32);
++	rtw_write8(adapter, REG_ATIMWND5, 0x32);
++	rtw_write8(adapter, REG_ATIMWND6, 0x32);
++	rtw_write8(adapter, REG_ATIMWND7, 0x32);*/
++
++	/*no limit setting - 0x5A7 = 0xFF - Packet in Hi Queue Tx immediately*/
++	rtw_write8(adapter, REG_HIQ_NO_LMT_EN, 0xFF);
++
++	/*Mask all beacon*/
++	rtw_write8(adapter, REG_MBSSID_CTRL, 0);
++
++	/*BCN invalid bit setting 0x454[6] = 1*/
++	/*rtw_write8(adapter, REG_CCK_CHECK, rtw_read8(adapter, REG_CCK_CHECK) | BIT_EN_BCN_PKT_REL);*/
++
++	/*Enable Port0's beacon function*/
++	rtw_write8(adapter, REG_BCN_CTRL,
++	rtw_read8(adapter, REG_BCN_CTRL) | BIT_DIS_RX_BSSID_FIT | BIT_P0_EN_TXBCN_RPT | BIT_DIS_TSF_UDT  | BIT_EN_BCN_FUNCTION);
++
++	/* Enable HW seq for BCN
++	* 0x4FC[0]: EN_HWSEQ / 0x4FC[1]: EN_HWSEQEXT  */
++	 #ifdef CONFIG_RTL8822B
++	if (IS_HARDWARE_TYPE_8822B(adapter))
++		rtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822B, 0x01);
++	#endif
++
++	 #ifdef CONFIG_RTL8822C
++	if (IS_HARDWARE_TYPE_8822C(adapter))
++		rtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822C, 0x01);
++	#endif
++}
++static void _rtw_mbid_bcn_cfg(_adapter *adapter, bool mbcnq_en, u8 mbcnq_id)
++{
++	if (mbcnq_id >= CONFIG_LIMITED_AP_NUM) {
++		RTW_ERR(FUNC_ADPT_FMT"- mbid bcnq_id(%d) invalid\n", FUNC_ADPT_ARG(adapter), mbcnq_id);
++		rtw_warn_on(1);
++	}
++
++	if (mbcnq_en) {
++		rtw_write8(adapter, REG_MBSSID_CTRL,
++			rtw_read8(adapter, REG_MBSSID_CTRL) | BIT(mbcnq_id));
++		RTW_INFO(FUNC_ADPT_FMT"- mbid bcnq_id(%d) enabled\n", FUNC_ADPT_ARG(adapter), mbcnq_id);
++	} else {
++		rtw_write8(adapter, REG_MBSSID_CTRL,
++			rtw_read8(adapter, REG_MBSSID_CTRL) & (~BIT(mbcnq_id)));
++		RTW_INFO(FUNC_ADPT_FMT"- mbid bcnq_id(%d) disabled\n", FUNC_ADPT_ARG(adapter), mbcnq_id);
++	}
++}
++/*#define CONFIG_FW_TBTT_RPT*/
++void rtw_ap_mbid_bcn_en(_adapter *adapter, u8 ap_id)
++{
++	RTW_INFO(FUNC_ADPT_FMT"- ap_id(%d)\n", FUNC_ADPT_ARG(adapter), ap_id);
++
++	#ifdef CONFIG_FW_TBTT_RPT
++	if (rtw_ap_get_nums(adapter) >= 1) {
++		u8 tbtt_rpt_map = adapter_to_dvobj(adapter)->vap_tbtt_rpt_map;
++
++		rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _TRUE,
++			tbtt_rpt_map | BIT(ap_id));/*H2C-0xBA*/
++	}
++	#else
++	if (rtw_ap_get_nums(adapter) == 1)
++		rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _TRUE, 0);/*H2C-0xBA*/
++	#endif
++
++	rtw_hal_set_bcn_rsvdpage_loc_cmd(adapter);/*H2C-0x09*/
++
++	_rtw_mbid_bcn_cfg(adapter, _TRUE, ap_id);
++}
++void rtw_ap_mbid_bcn_dis(_adapter *adapter, u8 ap_id)
++{
++	RTW_INFO(FUNC_ADPT_FMT"- ap_id(%d)\n", FUNC_ADPT_ARG(adapter), ap_id);
++	_rtw_mbid_bcn_cfg(adapter, _FALSE, ap_id);
++
++	if (rtw_ap_get_nums(adapter) == 0)
++		rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _FALSE, 0);
++	#ifdef CONFIG_FW_TBTT_RPT
++	else if (rtw_ap_get_nums(adapter) >= 1) {
++		u8 tbtt_rpt_map = adapter_to_dvobj(adapter)->vap_tbtt_rpt_map;
++
++		rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _TRUE,
++			tbtt_rpt_map & ~BIT(ap_id));/*H2C-0xBA*/
++	}
++	#endif
++}
++#endif
++#ifdef CONFIG_SWTIMER_BASED_TXBCN
++void rtw_ap_multi_bcn_cfg(_adapter *adapter)
++{
++	#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
++	rtw_write8(adapter, REG_BCN_CTRL, DIS_TSF_UDT);
++	#else
++	rtw_write8(adapter, REG_BCN_CTRL, DIS_TSF_UDT | DIS_BCNQ_SUB);
++	#endif
++	/*enable to rx data frame*/
++	rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);
++
++	/*Beacon Control related register for first time*/
++	rtw_write8(adapter, REG_BCNDMATIM, 0x02); /* 2ms */
++
++	/*rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);*/
++	rtw_write8(adapter, REG_ATIMWND, 0x0c); /* 12ms */
++
++	#ifndef CONFIG_HW_P0_TSF_SYNC
++	rtw_write16(adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
++	#endif
++
++	/*reset TSF*/
++	rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(0));
++
++	/*enable BCN0 Function for if1*/
++	/*don't enable update TSF0 for if1 (due to TSF update when beacon,probe rsp are received)*/
++	#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
++	rtw_write8(adapter, REG_BCN_CTRL, BIT_DIS_RX_BSSID_FIT | BIT_P0_EN_TXBCN_RPT | BIT_DIS_TSF_UDT |BIT_EN_BCN_FUNCTION);
++	#else
++	rtw_write8(adapter, REG_BCN_CTRL, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB));
++	#endif
++	#ifdef CONFIG_BCN_XMIT_PROTECT
++	rtw_write8(adapter, REG_CCK_CHECK, rtw_read8(adapter, REG_CCK_CHECK) | BIT_EN_BCN_PKT_REL);
++	#endif
++
++	if (IS_HARDWARE_TYPE_8821(adapter) || IS_HARDWARE_TYPE_8192E(adapter))/* select BCN on port 0 for DualBeacon*/
++		rtw_write8(adapter, REG_CCK_CHECK, rtw_read8(adapter, REG_CCK_CHECK) & (~BIT_BCN_PORT_SEL));
++
++	/* Enable HW seq for BCN 
++	 * 0x4FC[0]: EN_HWSEQ / 0x4FC[1]: EN_HWSEQEXT  */
++	#ifdef CONFIG_RTL8822B
++	if (IS_HARDWARE_TYPE_8822B(adapter))
++		rtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822B, 0x01);
++	#endif
++
++	#ifdef CONFIG_RTL8822C
++	if (IS_HARDWARE_TYPE_8822C(adapter))
++		rtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822C, 0x01);
++	#endif
++}
++#endif
++
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr)
++{
++
++#if 0 /*TODO - modify for more flexible*/
++	u8 idx = 0;
++
++	if ((check_fwstate(&adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) &&
++	    (DEV_STA_NUM(adapter_to_dvobj(adapter)) == 1)) {
++		for (idx = 0; idx < 6; idx++)
++			rtw_write8(GET_PRIMARY_ADAPTER(adapter), (REG_MACID + idx), val[idx]);
++	}  else {
++		/*MBID entry_id = 0~7 ,0 for root AP, 1~7 for VAP*/
++		u8 entry_id;
++
++		if ((check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) &&
++		    (DEV_AP_NUM(adapter_to_dvobj(adapter)) == 1)) {
++			entry_id = 0;
++			if (rtw_mbid_cam_assign(adapter, val, entry_id)) {
++				RTW_INFO(FUNC_ADPT_FMT" Root AP assigned success\n", FUNC_ADPT_ARG(adapter));
++				write_mbssid_cam(adapter, entry_id, val);
++			}
++		} else {
++			entry_id = rtw_mbid_camid_alloc(adapter, val);
++			if (entry_id != INVALID_CAM_ID)
++				write_mbssid_cam(adapter, entry_id, val);
++		}
++	}
++#else
++	{
++		/*
++			MBID entry_id = 0~7 ,for IFACE_ID0 ~ IFACE_IDx
++		*/
++		u8 entry_id = rtw_mbid_camid_alloc(adapter, mac_addr);
++
++
++		if (entry_id != INVALID_CAM_ID) {
++			write_mbssid_cam(adapter, entry_id, mac_addr);
++			RTW_INFO("%s "ADPT_FMT"- mbid(%d) mac_addr ="MAC_FMT"\n", __func__,
++				ADPT_ARG(adapter), entry_id, MAC_ARG(mac_addr));
++		}
++	}
++#endif
++}
++
++void rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr)
++{
++	u8 idx = 0;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	u8 entry_id;
++
++	if (!mac_addr) {
++		rtw_warn_on(1);
++		return;
++	}
++
++
++	entry_id = rtw_mbid_cam_info_change(adapter, mac_addr);
++
++	if (entry_id != INVALID_CAM_ID)
++		write_mbssid_cam(adapter, entry_id, mac_addr);
++}
++
++#ifdef CONFIG_SWTIMER_BASED_TXBCN
++u16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval)
++{
++	if (adapter_to_dvobj(adapter)->inter_bcn_space != bcn_interval)
++		return adapter_to_dvobj(adapter)->inter_bcn_space;
++	else
++		return bcn_interval;
++}
++#endif/*CONFIG_SWTIMER_BASED_TXBCN*/
++
++#else
++
++#ifndef RTW_HALMAC
++static u32 _get_macaddr_reg(enum _hw_port hwport)
++{
++	u32 reg_macaddr = REG_MACID;
++
++	#ifdef CONFIG_CONCURRENT_MODE
++	if (hwport == HW_PORT1)
++		reg_macaddr = REG_MACID1;
++	#if defined(CONFIG_RTL8814A)
++	else if (hwport == HW_PORT2)
++		reg_macaddr = REG_MACID2;
++	else if (hwport == HW_PORT3)
++		reg_macaddr = REG_MACID3;
++	else if (hwport == HW_PORT4)
++		reg_macaddr = REG_MACID4;
++	#endif /*CONFIG_RTL8814A*/
++	#endif /*CONFIG_CONCURRENT_MODE*/
++
++	return reg_macaddr;
++}
++#endif /*!RTW_HALMAC*/
++
++static void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *mac_addr)
++{
++	enum _hw_port hwport;
++
++	if (mac_addr == NULL)
++		return;
++	hwport = get_hw_port(adapter);
++
++	RTW_INFO("%s "ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n",  __func__,
++		 ADPT_ARG(adapter), hwport, MAC_ARG(mac_addr));
++
++#ifdef RTW_HALMAC /*8822B ~ 8814B*/
++	rtw_halmac_set_mac_address(adapter_to_dvobj(adapter), hwport, mac_addr);
++#else /* !RTW_HALMAC */
++	{
++		u8 idx = 0;
++		u32 reg_macaddr = _get_macaddr_reg(hwport);
++
++		for (idx = 0; idx < ETH_ALEN; idx++)
++			rtw_write8(GET_PRIMARY_ADAPTER(adapter), (reg_macaddr + idx), mac_addr[idx]);
++	}
++#endif /* !RTW_HALMAC */
++}
++
++static void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr)
++{
++	enum _hw_port hwport;
++
++	if (mac_addr == NULL)
++		return;
++	hwport = get_hw_port(adapter);
++
++	_rtw_memset(mac_addr, 0, ETH_ALEN);
++#ifdef RTW_HALMAC /*8822B ~ 8814B*/
++	rtw_halmac_get_mac_address(adapter_to_dvobj(adapter), hwport, mac_addr);
++#else /* !RTW_HALMAC */
++	{
++		u8 idx = 0;
++		u32 reg_macaddr = _get_macaddr_reg(hwport);
++
++		for (idx = 0; idx < ETH_ALEN; idx++)
++			mac_addr[idx] = rtw_read8(GET_PRIMARY_ADAPTER(adapter), (reg_macaddr + idx));
++	}
++#endif /* !RTW_HALMAC */
++
++	RTW_DBG("%s "ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n",  __func__,
++		 ADPT_ARG(adapter), hwport, MAC_ARG(mac_addr));
++}
++#endif/*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/
++
++#ifndef RTW_HALMAC
++static u32 _get_bssid_reg(enum _hw_port hw_port)
++{
++	u32 reg_bssid = REG_BSSID;
++
++	#ifdef CONFIG_CONCURRENT_MODE
++	if (hw_port == HW_PORT1)
++		reg_bssid = REG_BSSID1;
++	#if defined(CONFIG_RTL8814A)
++	else if (hw_port == HW_PORT2)
++		reg_bssid = REG_BSSID2;
++	else if (hw_port == HW_PORT3)
++		reg_bssid = REG_BSSID3;
++	else if (hw_port == HW_PORT4)
++		reg_bssid = REG_BSSID4;
++	#endif /*CONFIG_RTL8814A*/
++	#endif /*CONFIG_CONCURRENT_MODE*/
++
++	return reg_bssid;
++}
++#endif /*!RTW_HALMAC*/
++static void rtw_hal_set_bssid(_adapter *adapter, u8 *val)
++{
++	enum _hw_port hw_port = rtw_hal_get_port(adapter);
++#ifdef RTW_HALMAC
++
++	rtw_halmac_set_bssid(adapter_to_dvobj(adapter), hw_port, val);
++#else /* !RTW_HALMAC */
++	u8 idx = 0;
++	u32 reg_bssid = _get_bssid_reg(hw_port);
++
++	for (idx = 0 ; idx < ETH_ALEN; idx++)
++		rtw_write8(adapter, (reg_bssid + idx), val[idx]);
++#endif /* !RTW_HALMAC */
++
++	RTW_INFO("%s "ADPT_FMT"- hw port -%d BSSID: "MAC_FMT"\n",
++		__func__, ADPT_ARG(adapter), hw_port, MAC_ARG(val));
++}
++
++#ifndef CONFIG_MI_WITH_MBSSID_CAM
++static void rtw_hal_set_tsf_update(_adapter *adapter, u8 en)
++{
++	u32 addr = 0;
++	u8 val8;
++
++	rtw_hal_get_hwreg(adapter, HW_VAR_BCN_CTRL_ADDR, (u8 *)&addr);
++	if (addr) {
++		rtw_enter_protsel_port(adapter, get_hw_port(adapter));
++		val8 = rtw_read8(adapter, addr);
++		if (en && (val8 & DIS_TSF_UDT)) {
++			rtw_write8(adapter, addr, val8 & ~DIS_TSF_UDT);
++			#ifdef DBG_TSF_UPDATE
++			RTW_INFO("port%u("ADPT_FMT") enable TSF update\n", adapter->hw_port, ADPT_ARG(adapter));
++			#endif
++		}
++		if (!en && !(val8 & DIS_TSF_UDT)) {
++			rtw_write8(adapter, addr, val8 | DIS_TSF_UDT);
++			#ifdef DBG_TSF_UPDATE
++			RTW_INFO("port%u("ADPT_FMT") disable TSF update\n", adapter->hw_port, ADPT_ARG(adapter));
++			#endif
++		}
++		rtw_leave_protsel_port(adapter);
++	} else {
++		RTW_WARN("unknown port%d("ADPT_FMT") %s TSF update\n"
++			, adapter->hw_port, ADPT_ARG(adapter), en ? "enable" : "disable");
++		rtw_warn_on(1);
++	}
++}
++#endif /*CONFIG_MI_WITH_MBSSID_CAM*/
++static void rtw_hal_set_hw_update_tsf(PADAPTER padapter)
++{
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++
++#else
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++	if (!pmlmeext->en_hw_update_tsf)
++		return;
++
++	/* check RCR */
++	if (!rtw_hal_rcr_check(padapter, RCR_CBSSID_BCN))
++		return;
++
++	if (pmlmeext->tsf_update_required) {
++		pmlmeext->tsf_update_pause_stime = 0;
++		rtw_hal_set_tsf_update(padapter, 1);
++	}
++
++	pmlmeext->en_hw_update_tsf = 0;
++#endif
++}
++
++void rtw_iface_enable_tsf_update(_adapter *adapter)
++{
++	adapter->mlmeextpriv.tsf_update_pause_stime = 0;
++	adapter->mlmeextpriv.tsf_update_required = 1;
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++
++#else
++	rtw_hal_set_tsf_update(adapter, 1);
++#endif
++}
++
++void rtw_iface_disable_tsf_update(_adapter *adapter)
++{
++	adapter->mlmeextpriv.tsf_update_required = 0;
++	adapter->mlmeextpriv.tsf_update_pause_stime = 0;
++	adapter->mlmeextpriv.en_hw_update_tsf = 0;
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++
++#else
++	rtw_hal_set_tsf_update(adapter, 0);
++#endif
++}
++
++static void rtw_hal_tsf_update_pause(_adapter *adapter)
++{
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++
++#else
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	_adapter *iface;
++	int i;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (!iface)
++			continue;
++
++		rtw_hal_set_tsf_update(iface, 0);
++		if (iface->mlmeextpriv.tsf_update_required) {
++			iface->mlmeextpriv.tsf_update_pause_stime = rtw_get_current_time();
++			if (!iface->mlmeextpriv.tsf_update_pause_stime)
++				iface->mlmeextpriv.tsf_update_pause_stime++;
++		}
++		iface->mlmeextpriv.en_hw_update_tsf = 0;
++	}
++#endif
++}
++
++static void rtw_hal_tsf_update_restore(_adapter *adapter)
++{
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++
++#else
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	_adapter *iface;
++	int i;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (!iface)
++			continue;
++
++		if (iface->mlmeextpriv.tsf_update_required) {
++			/* enable HW TSF update when recive beacon*/
++			iface->mlmeextpriv.en_hw_update_tsf = 1;
++			#ifdef DBG_TSF_UPDATE
++			RTW_INFO("port%d("ADPT_FMT") enabling TSF update...\n"
++				, iface->hw_port, ADPT_ARG(iface));
++			#endif
++		}
++	}
++#endif
++}
++
++void rtw_hal_periodic_tsf_update_chk(_adapter *adapter)
++{
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++
++#else
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	_adapter *iface;
++	struct mlme_ext_priv *mlmeext;
++	int i;
++	u32 restore_ms = 0;
++
++	if (dvobj->periodic_tsf_update_etime) {
++		if (rtw_time_after(rtw_get_current_time(), dvobj->periodic_tsf_update_etime)) {
++			/* end for restore status */
++			dvobj->periodic_tsf_update_etime = 0;
++			rtw_hal_rcr_set_chk_bssid(adapter, MLME_ACTION_NONE);
++		}
++		return;
++	}
++
++	if (dvobj->rf_ctl.offch_state != OFFCHS_NONE)
++		return;
++
++	/*
++	* all required ifaces can switch to restore status together
++	* loop all pause iface to get largest restore time required
++	*/
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (!iface)
++			continue;
++
++		mlmeext = &iface->mlmeextpriv;
++
++		if (mlmeext->tsf_update_required
++			&& mlmeext->tsf_update_pause_stime
++			&& rtw_get_passing_time_ms(mlmeext->tsf_update_pause_stime)
++				> mlmeext->mlmext_info.bcn_interval * mlmeext->tsf_update_pause_factor
++		) {
++			if (restore_ms < mlmeext->mlmext_info.bcn_interval * mlmeext->tsf_update_restore_factor)
++				restore_ms = mlmeext->mlmext_info.bcn_interval * mlmeext->tsf_update_restore_factor;
++		}
++	}
++
++	if (!restore_ms)
++		return;
++
++	dvobj->periodic_tsf_update_etime = rtw_get_current_time() + rtw_ms_to_systime(restore_ms);
++	if (!dvobj->periodic_tsf_update_etime)
++		dvobj->periodic_tsf_update_etime++;
++
++	rtw_hal_rcr_set_chk_bssid(adapter, MLME_ACTION_NONE);
++
++	/* set timer to end restore status */
++	_set_timer(&dvobj->periodic_tsf_update_end_timer, restore_ms);
++#endif
++}
++
++void rtw_hal_periodic_tsf_update_end_timer_hdl(void *ctx)
++{
++	struct dvobj_priv *dvobj = (struct dvobj_priv *)ctx;
++
++	if (dev_is_surprise_removed(dvobj) || dev_is_drv_stopped(dvobj))
++		return;
++
++	rtw_periodic_tsf_update_end_cmd(dvobj_get_primary_adapter(dvobj));
++}
++
++static inline u8 hw_var_rcr_config(_adapter *adapter, u32 rcr)
++{
++	int err;
++
++#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
++	rcr = RCR_AAP | RCR_APM | RCR_AM | RCR_AB | RCR_APWRMGT | RCR_ADF | RCR_AMF | RCR_APP_PHYST_RXFF | RCR_APP_MIC | RCR_APP_ICV;
++#endif
++	err = rtw_write32(adapter, REG_RCR, rcr);
++	if (err == _SUCCESS)
++		GET_HAL_DATA(adapter)->ReceiveConfig = rcr;
++	return err;
++}
++
++static inline u8 hw_var_rcr_get(_adapter *adapter, u32 *rcr)
++{
++	u32 v32;
++
++	v32 = rtw_read32(adapter, REG_RCR);
++	if (rcr)
++		*rcr = v32;
++	GET_HAL_DATA(adapter)->ReceiveConfig = v32;
++	return _SUCCESS;
++}
++
++/* only check SW RCR variable */
++inline u8 rtw_hal_rcr_check(_adapter *adapter, u32 check_bit)
++{
++	PHAL_DATA_TYPE hal;
++	u32 rcr;
++
++	hal = GET_HAL_DATA(adapter);
++
++	rcr = hal->ReceiveConfig;
++	if ((rcr & check_bit) == check_bit)
++		return 1;
++
++	return 0;
++}
++
++inline u8 rtw_hal_rcr_add(_adapter *adapter, u32 add)
++{
++	PHAL_DATA_TYPE hal;
++	u32 rcr;
++	u8 ret = _SUCCESS;
++
++	hal = GET_HAL_DATA(adapter);
++
++	rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
++	rcr |= add;
++	if (rcr != hal->ReceiveConfig)
++		ret = rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
++
++	return ret;
++}
++
++inline u8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear)
++{
++	PHAL_DATA_TYPE hal;
++	u32 rcr;
++	u8 ret = _SUCCESS;
++
++	hal = GET_HAL_DATA(adapter);
++
++	rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
++	rcr &= ~clear;
++	if (rcr != hal->ReceiveConfig)
++		ret = rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
++
++	return ret;
++}
++
++void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	u32 rcr, rcr_new;
++	struct mi_state mstate, mstate_s;
++
++	rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
++	rcr_new = rcr;
++
++#if defined(CONFIG_MI_WITH_MBSSID_CAM) && !defined(CONFIG_CLIENT_PORT_CFG)
++	rcr_new &= ~(RCR_CBSSID_BCN | RCR_CBSSID_DATA);
++#else
++	rtw_mi_status_no_self(adapter, &mstate);
++	rtw_mi_status_no_others(adapter, &mstate_s);
++
++	/* only adjust parameters interested */
++	switch (self_action) {
++	case MLME_SCAN_ENTER:
++		mstate_s.scan_num = 1;
++		mstate_s.scan_enter_num = 1;
++		break;
++	case MLME_SCAN_DONE:
++		mstate_s.scan_enter_num = 0;
++		break;
++	case MLME_STA_CONNECTING:
++		mstate_s.lg_sta_num = 1;
++		mstate_s.ld_sta_num = 0;
++		break;
++	case MLME_STA_CONNECTED:
++		mstate_s.lg_sta_num = 0;
++		mstate_s.ld_sta_num = 1;
++		break;
++	case MLME_STA_DISCONNECTED:
++		mstate_s.lg_sta_num = 0;
++		mstate_s.ld_sta_num = 0;
++		break;
++#ifdef CONFIG_TDLS
++	case MLME_TDLS_LINKED:
++		mstate_s.ld_tdls_num = 1;
++		break;
++	case MLME_TDLS_NOLINK:
++		mstate_s.ld_tdls_num = 0;
++		break;
++#endif
++#ifdef CONFIG_AP_MODE
++	case MLME_AP_STARTED:
++		mstate_s.ap_num = 1;
++		break;
++	case MLME_AP_STOPPED:
++		mstate_s.ap_num = 0;
++		mstate_s.ld_ap_num = 0;
++		break;
++#endif
++#ifdef CONFIG_RTW_MESH
++	case MLME_MESH_STARTED:
++		mstate_s.mesh_num = 1;
++		break;
++	case MLME_MESH_STOPPED:
++		mstate_s.mesh_num = 0;
++		mstate_s.ld_mesh_num = 0;
++		break;
++#endif
++	case MLME_ACTION_NONE:
++	case MLME_ADHOC_STARTED:
++		/* caller without effect of decision */
++		break;
++	default:
++		rtw_warn_on(1);
++	};
++
++	rtw_mi_status_merge(&mstate, &mstate_s);
++
++	if (MSTATE_AP_NUM(&mstate) || MSTATE_MESH_NUM(&mstate) || MSTATE_TDLS_LD_NUM(&mstate)
++		#ifdef CONFIG_FIND_BEST_CHANNEL
++		|| MSTATE_SCAN_ENTER_NUM(&mstate)
++		#endif
++		|| hal_data->in_cta_test
++	)
++		rcr_new &= ~RCR_CBSSID_DATA;
++	else
++		rcr_new |= RCR_CBSSID_DATA;
++
++	if (MSTATE_SCAN_ENTER_NUM(&mstate) || hal_data->in_cta_test)
++		rcr_new &= ~RCR_CBSSID_BCN;
++	else if (MSTATE_STA_LG_NUM(&mstate)
++		|| adapter_to_dvobj(adapter)->periodic_tsf_update_etime
++	)
++		rcr_new |= RCR_CBSSID_BCN;
++	else if ((MSTATE_AP_NUM(&mstate) && adapter->registrypriv.wifi_spec) /* for 11n Logo 4.2.31/4.2.32 */
++		|| MSTATE_MESH_NUM(&mstate)
++	)
++		rcr_new &= ~RCR_CBSSID_BCN;	
++	else
++		rcr_new |= RCR_CBSSID_BCN;
++
++	#ifdef CONFIG_CLIENT_PORT_CFG
++	if (get_clt_num(adapter) > MAX_CLIENT_PORT_NUM)
++		rcr_new &= ~RCR_CBSSID_BCN;
++	#endif
++#endif /* CONFIG_MI_WITH_MBSSID_CAM */
++
++	if (rcr == rcr_new)
++		return;
++
++	if (!hal_spec->rx_tsf_filter
++		&& (rcr & RCR_CBSSID_BCN) && !(rcr_new & RCR_CBSSID_BCN))
++		rtw_hal_tsf_update_pause(adapter);
++
++	rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr_new);
++
++	if (!hal_spec->rx_tsf_filter
++		&& !(rcr & RCR_CBSSID_BCN) && (rcr_new & RCR_CBSSID_BCN)
++		&& self_action != MLME_STA_CONNECTING)
++		rtw_hal_tsf_update_restore(adapter);
++}
++
++static void hw_var_set_rcr_am(_adapter *adapter, u8 enable)
++{
++	u32 rcr = RCR_AM;
++
++	if (enable)
++		rtw_hal_rcr_add(adapter, rcr);
++	else
++		rtw_hal_rcr_clear(adapter, rcr);
++}
++
++static void hw_var_set_bcn_interval(_adapter *adapter, u16 interval)
++{
++#ifdef CONFIG_SWTIMER_BASED_TXBCN
++	interval = rtw_hal_bcn_interval_adjust(adapter, interval);
++#endif
++
++#ifdef RTW_HALMAC
++	rtw_halmac_set_bcn_interval(adapter_to_dvobj(adapter), adapter->hw_port, interval);
++#else
++	rtw_write16(adapter, REG_MBSSID_BCN_SPACE, interval);
++#endif
++
++#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
++	{
++		struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
++		struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++		if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
++			RTW_INFO("%s==> bcn_interval:%d, eraly_int:%d\n", __func__, interval, interval >> 1);
++			rtw_write8(adapter, REG_DRVERLYINT, interval >> 1);
++		}
++	}
++#endif
++}
++
++#if CONFIG_TX_AC_LIFETIME
++const char *const _tx_aclt_conf_str[] = {
++	"DEFAULT",
++	"AP_M2U",
++	"MESH",
++	"INVALID",
++};
++
++void dump_tx_aclt_force_val(void *sel, struct dvobj_priv *dvobj)
++{
++#define TX_ACLT_FORCE_MSG_LEN 64
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(dvobj_get_primary_adapter(dvobj));
++	struct tx_aclt_conf_t *conf = &dvobj->tx_aclt_force_val;
++	char buf[TX_ACLT_FORCE_MSG_LEN];
++	int cnt = 0;
++
++	RTW_PRINT_SEL(sel, "unit:%uus, maximum:%uus\n"
++		, hal_spec->tx_aclt_unit_factor * 32
++		, 0xFFFF * hal_spec->tx_aclt_unit_factor * 32);
++
++	RTW_PRINT_SEL(sel, "%-5s %-12s %-12s\n", "en", "vo_vi(us)", "be_bk(us)");
++	RTW_PRINT_SEL(sel, " 0x%02x %12u %12u\n"
++		, conf->en
++		, conf->vo_vi * hal_spec->tx_aclt_unit_factor * 32
++		, conf->be_bk * hal_spec->tx_aclt_unit_factor * 32
++	);
++
++	cnt += snprintf(buf + cnt, TX_ACLT_FORCE_MSG_LEN - cnt - 1, "%5s", conf->en == 0xFF ? "AUTO" : "FORCE");
++	if (cnt >= TX_ACLT_FORCE_MSG_LEN - 1)
++		goto exit;
++
++	if (conf->vo_vi)
++		cnt += snprintf(buf + cnt, TX_ACLT_FORCE_MSG_LEN - cnt - 1, " FORCE:0x%04x", conf->vo_vi);
++	else
++		cnt += snprintf(buf + cnt, TX_ACLT_FORCE_MSG_LEN - cnt - 1, "         AUTO");
++	if (cnt >= TX_ACLT_FORCE_MSG_LEN - 1)
++		goto exit;
++
++
++	if (conf->be_bk)
++		cnt += snprintf(buf + cnt, TX_ACLT_FORCE_MSG_LEN - cnt - 1, " FORCE:0x%04x", conf->be_bk);
++	else
++		cnt += snprintf(buf + cnt, TX_ACLT_FORCE_MSG_LEN - cnt - 1, "         AUTO");
++	if (cnt >= TX_ACLT_FORCE_MSG_LEN - 1)
++		goto exit;
++
++	RTW_PRINT_SEL(sel, "%s\n", buf);
++
++exit:
++	return;
++}
++
++void rtw_hal_set_tx_aclt_force_val(_adapter *adapter, struct tx_aclt_conf_t *input, u8 arg_num)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct tx_aclt_conf_t *conf = &dvobj->tx_aclt_force_val;
++
++	if (arg_num >= 1) {
++		if (input->en == 0xFF)
++			conf->en = input->en;
++		else
++			conf->en = input->en & 0xF;
++	}
++	if (arg_num >= 2) {
++		conf->vo_vi = input->vo_vi / (hal_spec->tx_aclt_unit_factor * 32);
++		if (conf->vo_vi > 0xFFFF)
++			conf->vo_vi = 0xFFFF;
++	}
++	if (arg_num >= 3) {
++		conf->be_bk = input->be_bk / (hal_spec->tx_aclt_unit_factor * 32);
++		if (conf->be_bk > 0xFFFF)
++			conf->be_bk = 0xFFFF;
++	}
++}
++
++void dump_tx_aclt_confs(void *sel, struct dvobj_priv *dvobj)
++{
++#define TX_ACLT_CONF_MSG_LEN 32
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(dvobj_get_primary_adapter(dvobj));
++	struct tx_aclt_conf_t *conf;
++	char buf[TX_ACLT_CONF_MSG_LEN];
++	int cnt;
++	int i;
++
++	RTW_PRINT_SEL(sel, "unit:%uus, maximum:%uus\n"
++		, hal_spec->tx_aclt_unit_factor * 32
++		, 0xFFFF * hal_spec->tx_aclt_unit_factor * 32);
++
++	RTW_PRINT_SEL(sel, "%-7s %-1s %-3s %-9s %-9s %-10s %-10s\n"
++		, "name", "#", "en", "vo_vi(us)", "be_bk(us)", "vo_vi(reg)", "be_bk(reg)");
++
++	for (i = 0; i < TX_ACLT_CONF_NUM; i++) {
++		conf = &dvobj->tx_aclt_confs[i];
++		cnt = 0;
++
++		if (conf->vo_vi)
++			cnt += snprintf(buf + cnt, TX_ACLT_CONF_MSG_LEN - cnt - 1, "     0x%04x", conf->vo_vi);
++		else
++			cnt += snprintf(buf + cnt, TX_ACLT_CONF_MSG_LEN - cnt - 1, "        N/A");
++		if (cnt >= TX_ACLT_CONF_MSG_LEN - 1)
++			continue;
++		
++		if (conf->be_bk)
++			cnt += snprintf(buf + cnt, TX_ACLT_CONF_MSG_LEN - cnt - 1, "     0x%04x", conf->be_bk);
++		else
++			cnt += snprintf(buf + cnt, TX_ACLT_CONF_MSG_LEN - cnt - 1, "        N/A");
++		if (cnt >= TX_ACLT_CONF_MSG_LEN - 1)
++			continue;
++
++		RTW_PRINT_SEL(sel, "%7s %1u 0x%x %9u %9u%s\n"
++			, tx_aclt_conf_str(i), i
++			, conf->en
++			, conf->vo_vi * hal_spec->tx_aclt_unit_factor * 32
++			, conf->be_bk * hal_spec->tx_aclt_unit_factor * 32
++			, buf
++		);
++	}
++}
++
++void rtw_hal_set_tx_aclt_conf(_adapter *adapter, u8 conf_idx, struct tx_aclt_conf_t *input, u8 arg_num)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct tx_aclt_conf_t *conf;
++
++	if (conf_idx >= TX_ACLT_CONF_NUM)
++		return;
++
++	conf = &dvobj->tx_aclt_confs[conf_idx];
++
++	if (arg_num >= 1) {
++		if (input->en != 0xFF)
++			conf->en = input->en & 0xF;
++	}
++	if (arg_num >= 2) {
++		conf->vo_vi = input->vo_vi / (hal_spec->tx_aclt_unit_factor * 32);
++		if (conf->vo_vi > 0xFFFF)
++			conf->vo_vi = 0xFFFF;
++	}
++	if (arg_num >= 3) {
++		conf->be_bk = input->be_bk / (hal_spec->tx_aclt_unit_factor * 32);
++		if (conf->be_bk > 0xFFFF)
++			conf->be_bk = 0xFFFF;
++	}
++}
++
++void rtw_hal_update_tx_aclt(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
++	u8 lt_en = 0, lt_en_ori;
++	u16 lt_vo_vi = 0xFFFF, lt_be_bk = 0xFFFF;
++	u32 lt, lt_ori;
++	struct tx_aclt_conf_t *conf;
++	int i;
++#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++	_adapter *iface;
++	u8 ap_m2u_num = 0;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (!iface)
++			continue;
++		
++		if (MLME_IS_AP(iface)
++			&& ((iface->b2u_flags_ap_src & RTW_AP_B2U_IP_MCAST)
++				|| (iface->b2u_flags_ap_fwd & RTW_AP_B2U_IP_MCAST))
++		)
++			ap_m2u_num++;
++	}
++#endif
++
++	lt_en_ori = rtw_read8(adapter, REG_LIFETIME_EN);
++	lt_ori = rtw_read32(adapter, REG_PKT_LIFE_TIME);
++
++	for (i = 0; i < TX_ACLT_CONF_NUM; i++) {
++		if (!(dvobj->tx_aclt_flags & BIT(i)))
++			continue;
++
++		conf = &dvobj->tx_aclt_confs[i];
++
++		if (i == TX_ACLT_CONF_DEFAULT) {
++			/* first and default status, assign directly */
++			lt_en = conf->en;
++			if (conf->vo_vi)
++				lt_vo_vi = conf->vo_vi;
++			if (conf->be_bk)
++				lt_be_bk = conf->be_bk;
++		}
++		#if CONFIG_RTW_AP_DATA_BMC_TO_UC || defined(CONFIG_RTW_MESH)
++		else if (0
++			#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++			|| (i == TX_ACLT_CONF_AP_M2U
++				&& ap_m2u_num
++				&& macid_ctl->op_num[H2C_MSR_ROLE_STA] /* having AP mode with STA connected */)
++			#endif
++			#ifdef CONFIG_RTW_MESH
++			|| (i == TX_ACLT_CONF_MESH
++				&& macid_ctl->op_num[H2C_MSR_ROLE_MESH] > 1 /* implies only 1 MESH mode supported */)
++			#endif
++		) {
++			/* long term status, OR en and MIN lifetime */
++			lt_en |= conf->en;
++			if (conf->vo_vi && lt_vo_vi > conf->vo_vi)
++				lt_vo_vi = conf->vo_vi;
++			if (conf->be_bk && lt_be_bk > conf->be_bk)
++				lt_be_bk = conf->be_bk;
++		}
++		#endif
++	}
++
++	if (dvobj->tx_aclt_force_val.en != 0xFF)
++		lt_en = dvobj->tx_aclt_force_val.en;
++	if (dvobj->tx_aclt_force_val.vo_vi)
++		lt_vo_vi = dvobj->tx_aclt_force_val.vo_vi;
++	if (dvobj->tx_aclt_force_val.be_bk)
++		lt_be_bk = dvobj->tx_aclt_force_val.be_bk;
++
++	lt_en = (lt_en_ori & 0xF0) | (lt_en & 0x0F);
++	lt = (lt_be_bk << 16) | lt_vo_vi;
++
++	if (0)
++		RTW_INFO("lt_en:0x%x(0x%x), lt:0x%08x(0x%08x)\n", lt_en, lt_en_ori, lt, lt_ori);
++
++	if (lt_en != lt_en_ori)
++		rtw_write8(adapter, REG_LIFETIME_EN, lt_en);
++	if (lt != lt_ori)
++		rtw_write32(adapter, REG_PKT_LIFE_TIME, lt);
++}
++#endif /* CONFIG_TX_AC_LIFETIME */
++
++void hw_var_port_switch(_adapter *adapter)
++{
++#ifdef CONFIG_CONCURRENT_MODE
++#ifdef CONFIG_RUNTIME_PORT_SWITCH
++	/*
++	0x102: MSR
++	0x550: REG_BCN_CTRL
++	0x551: REG_BCN_CTRL_1
++	0x55A: REG_ATIMWND
++	0x560: REG_TSFTR
++	0x568: REG_TSFTR1
++	0x570: REG_ATIMWND_1
++	0x610: REG_MACID
++	0x618: REG_BSSID
++	0x700: REG_MACID1
++	0x708: REG_BSSID1
++	*/
++
++	int i;
++	u8 msr;
++	u8 bcn_ctrl;
++	u8 bcn_ctrl_1;
++	u8 atimwnd[2];
++	u8 atimwnd_1[2];
++	u8 tsftr[8];
++	u8 tsftr_1[8];
++	u8 macid[6];
++	u8 bssid[6];
++	u8 macid_1[6];
++	u8 bssid_1[6];
++#if defined(CONFIG_RTL8192F)
++	u16 wlan_act_mask_ctrl = 0;
++	u16 en_port_mask = EN_PORT_0_FUNCTION | EN_PORT_1_FUNCTION;
++#endif
++
++	u8 hw_port;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	_adapter *iface = NULL;
++
++	msr = rtw_read8(adapter, MSR);
++	bcn_ctrl = rtw_read8(adapter, REG_BCN_CTRL);
++	bcn_ctrl_1 = rtw_read8(adapter, REG_BCN_CTRL_1);
++#if defined(CONFIG_RTL8192F)
++	wlan_act_mask_ctrl = rtw_read16(adapter, REG_WLAN_ACT_MASK_CTRL_1);
++#endif
++
++	for (i = 0; i < 2; i++)
++		atimwnd[i] = rtw_read8(adapter, REG_ATIMWND + i);
++	for (i = 0; i < 2; i++)
++		atimwnd_1[i] = rtw_read8(adapter, REG_ATIMWND_1 + i);
++
++	for (i = 0; i < 8; i++)
++		tsftr[i] = rtw_read8(adapter, REG_TSFTR + i);
++	for (i = 0; i < 8; i++)
++		tsftr_1[i] = rtw_read8(adapter, REG_TSFTR1 + i);
++
++	for (i = 0; i < 6; i++)
++		macid[i] = rtw_read8(adapter, REG_MACID + i);
++
++	for (i = 0; i < 6; i++)
++		bssid[i] = rtw_read8(adapter, REG_BSSID + i);
++
++	for (i = 0; i < 6; i++)
++		macid_1[i] = rtw_read8(adapter, REG_MACID1 + i);
++
++	for (i = 0; i < 6; i++)
++		bssid_1[i] = rtw_read8(adapter, REG_BSSID1 + i);
++
++#ifdef DBG_RUNTIME_PORT_SWITCH
++	RTW_INFO(FUNC_ADPT_FMT" before switch\n"
++		 "msr:0x%02x\n"
++		 "bcn_ctrl:0x%02x\n"
++		 "bcn_ctrl_1:0x%02x\n"
++#if defined(CONFIG_RTL8192F)
++		 "wlan_act_mask_ctrl:0x%02x\n"
++#endif
++		 "atimwnd:0x%04x\n"
++		 "atimwnd_1:0x%04x\n"
++		 "tsftr:%llu\n"
++		 "tsftr1:%llu\n"
++		 "macid:"MAC_FMT"\n"
++		 "bssid:"MAC_FMT"\n"
++		 "macid_1:"MAC_FMT"\n"
++		 "bssid_1:"MAC_FMT"\n"
++		 , FUNC_ADPT_ARG(adapter)
++		 , msr
++		 , bcn_ctrl
++		 , bcn_ctrl_1
++#if defined(CONFIG_RTL8192F)
++		 , wlan_act_mask_ctrl
++#endif
++		 , *((u16 *)atimwnd)
++		 , *((u16 *)atimwnd_1)
++		 , *((u64 *)tsftr)
++		 , *((u64 *)tsftr_1)
++		 , MAC_ARG(macid)
++		 , MAC_ARG(bssid)
++		 , MAC_ARG(macid_1)
++		 , MAC_ARG(bssid_1)
++		);
++#endif /* DBG_RUNTIME_PORT_SWITCH */
++
++	/* disable bcn function, disable update TSF */
++	rtw_write8(adapter, REG_BCN_CTRL, (bcn_ctrl & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT);
++	rtw_write8(adapter, REG_BCN_CTRL_1, (bcn_ctrl_1 & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT);
++
++#if defined(CONFIG_RTL8192F)
++	rtw_write16(adapter, REG_WLAN_ACT_MASK_CTRL_1, wlan_act_mask_ctrl & ~en_port_mask);
++#endif
++
++	/* switch msr */
++	msr = (msr & 0xf0) | ((msr & 0x03) << 2) | ((msr & 0x0c) >> 2);
++	rtw_write8(adapter, MSR, msr);
++
++	/* write port0 */
++	rtw_write8(adapter, REG_BCN_CTRL, bcn_ctrl_1 & ~EN_BCN_FUNCTION);
++	for (i = 0; i < 2; i++)
++		rtw_write8(adapter, REG_ATIMWND + i, atimwnd_1[i]);
++	for (i = 0; i < 8; i++)
++		rtw_write8(adapter, REG_TSFTR + i, tsftr_1[i]);
++	for (i = 0; i < 6; i++)
++		rtw_write8(adapter, REG_MACID + i, macid_1[i]);
++	for (i = 0; i < 6; i++)
++		rtw_write8(adapter, REG_BSSID + i, bssid_1[i]);
++
++	/* write port1 */
++	rtw_write8(adapter, REG_BCN_CTRL_1, bcn_ctrl & ~EN_BCN_FUNCTION);
++	for (i = 0; i < 2; i++)
++		rtw_write8(adapter, REG_ATIMWND_1 + i, atimwnd[i]);
++	for (i = 0; i < 8; i++)
++		rtw_write8(adapter, REG_TSFTR1 + i, tsftr[i]);
++	for (i = 0; i < 6; i++)
++		rtw_write8(adapter, REG_MACID1 + i, macid[i]);
++	for (i = 0; i < 6; i++)
++		rtw_write8(adapter, REG_BSSID1 + i, bssid[i]);
++
++	/* write bcn ctl */
++#ifdef CONFIG_BT_COEXIST
++	/* always enable port0 beacon function for PSTDMA */
++	if (IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8703B(adapter)
++	    || IS_HARDWARE_TYPE_8723D(adapter))
++		bcn_ctrl_1 |= EN_BCN_FUNCTION;
++	/* always disable port1 beacon function for PSTDMA */
++	if (IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8703B(adapter))
++		bcn_ctrl &= ~EN_BCN_FUNCTION;
++#endif
++	rtw_write8(adapter, REG_BCN_CTRL, bcn_ctrl_1);
++	rtw_write8(adapter, REG_BCN_CTRL_1, bcn_ctrl);
++
++#if defined(CONFIG_RTL8192F)
++	/* if the setting of port0 and port1 are the same, it does not need to switch port setting*/
++	if(((wlan_act_mask_ctrl & en_port_mask) != 0) && ((wlan_act_mask_ctrl & en_port_mask)
++		!= (EN_PORT_0_FUNCTION | EN_PORT_1_FUNCTION)))
++		wlan_act_mask_ctrl ^= en_port_mask;
++	rtw_write16(adapter, REG_WLAN_ACT_MASK_CTRL_1, wlan_act_mask_ctrl);
++#endif
++
++	if (adapter->iface_id == IFACE_ID0)
++		iface = dvobj->padapters[IFACE_ID1];
++	else if (adapter->iface_id == IFACE_ID1)
++		iface = dvobj->padapters[IFACE_ID0];
++
++
++	if (adapter->hw_port == HW_PORT0) {
++		adapter->hw_port = HW_PORT1;
++		iface->hw_port = HW_PORT0;
++		RTW_PRINT("port switch - port0("ADPT_FMT"), port1("ADPT_FMT")\n",
++			  ADPT_ARG(iface), ADPT_ARG(adapter));
++	} else {
++		adapter->hw_port = HW_PORT0;
++		iface->hw_port = HW_PORT1;
++		RTW_PRINT("port switch - port0("ADPT_FMT"), port1("ADPT_FMT")\n",
++			  ADPT_ARG(adapter), ADPT_ARG(iface));
++	}
++
++#ifdef DBG_RUNTIME_PORT_SWITCH
++	msr = rtw_read8(adapter, MSR);
++	bcn_ctrl = rtw_read8(adapter, REG_BCN_CTRL);
++	bcn_ctrl_1 = rtw_read8(adapter, REG_BCN_CTRL_1);
++#if defined(CONFIG_RTL8192F)
++	wlan_act_mask_ctrl = rtw_read16(adapter, REG_WLAN_ACT_MASK_CTRL_1);
++#endif
++
++	for (i = 0; i < 2; i++)
++		atimwnd[i] = rtw_read8(adapter, REG_ATIMWND + i);
++	for (i = 0; i < 2; i++)
++		atimwnd_1[i] = rtw_read8(adapter, REG_ATIMWND_1 + i);
++
++	for (i = 0; i < 8; i++)
++		tsftr[i] = rtw_read8(adapter, REG_TSFTR + i);
++	for (i = 0; i < 8; i++)
++		tsftr_1[i] = rtw_read8(adapter, REG_TSFTR1 + i);
++
++	for (i = 0; i < 6; i++)
++		macid[i] = rtw_read8(adapter, REG_MACID + i);
++
++	for (i = 0; i < 6; i++)
++		bssid[i] = rtw_read8(adapter, REG_BSSID + i);
++
++	for (i = 0; i < 6; i++)
++		macid_1[i] = rtw_read8(adapter, REG_MACID1 + i);
++
++	for (i = 0; i < 6; i++)
++		bssid_1[i] = rtw_read8(adapter, REG_BSSID1 + i);
++
++	RTW_INFO(FUNC_ADPT_FMT" after switch\n"
++		 "msr:0x%02x\n"
++		 "bcn_ctrl:0x%02x\n"
++		 "bcn_ctrl_1:0x%02x\n"
++#if defined(CONFIG_RTL8192F)
++		 "wlan_act_mask_ctrl:0x%02x\n"
++#endif
++		 "atimwnd:%u\n"
++		 "atimwnd_1:%u\n"
++		 "tsftr:%llu\n"
++		 "tsftr1:%llu\n"
++		 "macid:"MAC_FMT"\n"
++		 "bssid:"MAC_FMT"\n"
++		 "macid_1:"MAC_FMT"\n"
++		 "bssid_1:"MAC_FMT"\n"
++		 , FUNC_ADPT_ARG(adapter)
++		 , msr
++		 , bcn_ctrl
++		 , bcn_ctrl_1
++#if defined(CONFIG_RTL8192F)
++		 , wlan_act_mask_ctrl
++#endif
++		 , *((u16 *)atimwnd)
++		 , *((u16 *)atimwnd_1)
++		 , *((u64 *)tsftr)
++		 , *((u64 *)tsftr_1)
++		 , MAC_ARG(macid)
++		 , MAC_ARG(bssid)
++		 , MAC_ARG(macid_1)
++		 , MAC_ARG(bssid_1)
++		);
++#endif /* DBG_RUNTIME_PORT_SWITCH */
++
++#endif /* CONFIG_RUNTIME_PORT_SWITCH */
++#endif /* CONFIG_CONCURRENT_MODE */
++}
++
++const char *const _h2c_msr_role_str[] = {
++	"RSVD",
++	"STA",
++	"AP",
++	"GC",
++	"GO",
++	"TDLS",
++	"ADHOC",
++	"MESH",
++	"INVALID",
++};
++
++#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++s32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id)
++{
++	s32 ret = _SUCCESS;
++	u8 parm[H2C_DEFAULT_PORT_ID_LEN] = {0};
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	u8 port_id = rtw_hal_get_port(adapter);
++
++	if ((dvobj->dft.port_id == port_id) && (dvobj->dft.mac_id == mac_id))
++		return ret;
++
++	SET_H2CCMD_DFTPID_PORT_ID(parm, port_id);
++	SET_H2CCMD_DFTPID_MAC_ID(parm, mac_id);
++
++	RTW_DBG_DUMP("DFT port id parm:", parm, H2C_DEFAULT_PORT_ID_LEN);
++	RTW_INFO("%s ("ADPT_FMT") port_id :%d, mad_id:%d\n",
++		__func__, ADPT_ARG(adapter), port_id, mac_id);
++
++	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_DEFAULT_PORT_ID, H2C_DEFAULT_PORT_ID_LEN, parm);
++	dvobj->dft.port_id = port_id;
++	dvobj->dft.mac_id = mac_id;
++
++	return ret;
++}
++s32 rtw_set_default_port_id(_adapter *adapter)
++{
++	s32 ret = _SUCCESS;
++	struct sta_info		*psta;
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++
++	if (is_client_associated_to_ap(adapter)) {
++		psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
++		if (psta)
++			ret = rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id);
++	} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
++
++	} else {
++	}
++
++	return ret;
++}
++s32 rtw_set_ps_rsvd_page(_adapter *adapter)
++{
++	s32 ret = _SUCCESS;
++	u16 media_status_rpt = RT_MEDIA_CONNECT;
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
++
++	if (adapter->iface_id == pwrctl->fw_psmode_iface_id)
++		return ret;
++
++	rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,
++			  (u8 *)&media_status_rpt);
++
++	return ret;
++}
++
++#if 0
++_adapter * _rtw_search_dp_iface(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	_adapter *iface;
++	_adapter *target_iface = NULL;
++	int i;
++	u8 sta_num = 0, tdls_num = 0, ap_num = 0, mesh_num = 0, adhoc_num = 0;
++	u8 p2p_go_num = 0, p2p_gc_num = 0;
++	_adapter *sta_ifs[8];
++	_adapter *ap_ifs[8];
++	_adapter *mesh_ifs[8];
++	_adapter *gc_ifs[8];
++	_adapter *go_ifs[8];
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++
++		if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) {
++			if (check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++				sta_ifs[sta_num++] = iface;
++
++				#ifdef CONFIG_TDLS
++				if (iface->tdlsinfo.link_established == _TRUE)
++					tdls_num++;
++				#endif
++				#ifdef CONFIG_P2P
++				if (MLME_IS_GC(iface))
++					gc_ifs[p2p_gc_num++] = iface;
++				#endif
++			}
++#ifdef CONFIG_AP_MODE
++		} else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE ) {
++			if (check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++				ap_ifs[ap_num++] = iface;
++				#ifdef CONFIG_P2P
++				if (MLME_IS_GO(iface))
++					go_ifs[p2p_go_num++] = iface;
++				#endif
++			}
++#endif
++		} else if (check_fwstate(&iface->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE
++			&& check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE
++		) {
++			adhoc_num++;
++
++#ifdef CONFIG_RTW_MESH
++		} else if (check_fwstate(&iface->mlmepriv, WIFI_MESH_STATE) == _TRUE
++			&& check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE
++		) {
++			mesh_ifs[mesh_num++] = iface;
++#endif
++		}
++	}
++
++	if (p2p_gc_num) {
++		target_iface = gc_ifs[0];
++	}
++	else if (sta_num) {
++		if(sta_num == 1) {
++			target_iface = sta_ifs[0];
++		} else if (sta_num >= 2) {
++			/*TODO get target_iface by timestamp*/
++			target_iface = sta_ifs[0];
++		}
++	} else if (ap_num) {
++		target_iface = ap_ifs[0];
++	}
++
++	RTW_INFO("[IFS_ASSOC_STATUS] - STA :%d", sta_num);
++	RTW_INFO("[IFS_ASSOC_STATUS] - TDLS :%d", tdls_num);
++	RTW_INFO("[IFS_ASSOC_STATUS] - AP:%d", ap_num);
++	RTW_INFO("[IFS_ASSOC_STATUS] - MESH :%d", mesh_num);
++	RTW_INFO("[IFS_ASSOC_STATUS] - ADHOC :%d", adhoc_num);
++	RTW_INFO("[IFS_ASSOC_STATUS] - P2P-GC :%d", p2p_gc_num);
++	RTW_INFO("[IFS_ASSOC_STATUS] - P2P-GO :%d", p2p_go_num);
++
++	if (target_iface)
++		RTW_INFO("%s => target_iface ("ADPT_FMT")\n",
++			__func__, ADPT_ARG(target_iface));
++	else
++		RTW_INFO("%s => target_iface NULL\n", __func__);
++
++	return target_iface;
++}
++
++void rtw_search_default_port(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	_adapter *adp_iface = NULL;
++#ifdef CONFIG_WOWLAN
++	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
++
++	if (pwrpriv->wowlan_mode == _TRUE) {
++		adp_iface = adapter;
++		goto exit;
++	}
++#endif
++	adp_iface = _rtw_search_dp_iface(adapter);
++
++exit :
++	if ((adp_iface != NULL) && (MLME_IS_STA(adp_iface)))
++		rtw_set_default_port_id(adp_iface);
++	else
++		rtw_hal_set_default_port_id_cmd(adapter, 0);
++
++	if (1) {
++		_adapter *tmp_adp;
++
++		tmp_adp = (adp_iface) ? adp_iface : adapter;
++
++		RTW_INFO("%s ("ADPT_FMT")=> hw_port :%d, default_port(%d)\n",
++			__func__, ADPT_ARG(adapter), get_hw_port(tmp_adp), get_dft_portid(tmp_adp));
++	}
++}
++#endif
++#endif /*CONFIG_FW_MULTI_PORT_SUPPORT*/
++
++#ifdef CONFIG_P2P_PS
++#ifdef RTW_HALMAC
++void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state)
++{
++	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
++	struct wifidirect_info *pwdinfo = &adapter->wdinfo;
++	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
++	struct sta_priv		*pstapriv = &adapter->stapriv;
++	struct sta_info		*psta;
++	HAL_P2P_PS_PARA p2p_ps_para;
++	int status = -1;
++	u8 i;
++	u8 hw_port = rtw_hal_get_port(adapter);
++
++	_rtw_memset(&p2p_ps_para, 0, sizeof(HAL_P2P_PS_PARA));
++	_rtw_memcpy((&p2p_ps_para) , &hal->p2p_ps_offload , sizeof(hal->p2p_ps_offload));
++
++	(&p2p_ps_para)->p2p_port_id = hw_port;
++	(&p2p_ps_para)->p2p_group = 0;
++	psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
++	if (psta) {
++		(&p2p_ps_para)->p2p_macid = psta->cmn.mac_id;
++	} else {
++		if (p2p_ps_state != P2P_PS_DISABLE) {
++			RTW_ERR("%s , psta was NULL\n", __func__);
++			return;
++		}
++	}
++
++
++	switch (p2p_ps_state) {
++	case P2P_PS_DISABLE:
++		RTW_INFO("P2P_PS_DISABLE\n");
++		_rtw_memset(&p2p_ps_para , 0, sizeof(HAL_P2P_PS_PARA));
++		break;
++
++	case P2P_PS_ENABLE:
++		RTW_INFO("P2P_PS_ENABLE\n");
++		/* update CTWindow value. */
++		if (pwdinfo->ctwindow > 0) {
++			(&p2p_ps_para)->ctwindow_en = 1;
++			(&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;
++			/*RTW_INFO("%s , ctwindow_length = %d\n" , __func__ , (&p2p_ps_para)->ctwindow_length);*/
++		}
++
++
++		if ((pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0)) {
++			(&p2p_ps_para)->offload_en = 1;
++			if (pwdinfo->role == P2P_ROLE_GO) {
++				(&p2p_ps_para)->role = 1;
++				(&p2p_ps_para)->all_sta_sleep = 0;
++			} else
++				(&p2p_ps_para)->role = 0;
++
++			(&p2p_ps_para)->discovery = 0;
++		}
++		/* hw only support 2 set of NoA */
++		for (i = 0; i < pwdinfo->noa_num; i++) {
++			/* To control the register setting for which NOA */
++			(&p2p_ps_para)->noa_sel = i;
++			(&p2p_ps_para)->noa_en = 1;
++			(&p2p_ps_para)->disable_close_rf = 0;
++#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
++#ifdef CONFIG_CONCURRENT_MODE
++			if (rtw_mi_buddy_check_fwstate(adapter, WIFI_ASOC_STATE))
++#endif /* CONFIG_CONCURRENT_MODE */
++				(&p2p_ps_para)->disable_close_rf = 1;
++#endif /* CONFIG_P2P_PS_NOA_USE_MACID_SLEEP */
++			/* config P2P NoA Descriptor Register */
++			/* config NOA duration */
++			(&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[i];
++			/* config NOA interval */
++			(&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[i];
++			/* config NOA start time */
++			(&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[i];
++			/* config NOA count */
++			(&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[i];
++			/*RTW_INFO("%s , noa_duration_para = %d , noa_interval_para = %d , noa_start_time_para = %d , noa_count_para = %d\n" , __func__ ,
++				(&p2p_ps_para)->noa_duration_para , (&p2p_ps_para)->noa_interval_para ,
++				(&p2p_ps_para)->noa_start_time_para , (&p2p_ps_para)->noa_count_para);*/
++			status = rtw_halmac_p2pps(adapter_to_dvobj(adapter) , (&p2p_ps_para));
++			if (status == -1)
++				RTW_ERR("%s , rtw_halmac_p2pps fail\n", __func__);
++		}
++
++		break;
++
++	case P2P_PS_SCAN:
++		/*This feature FW not ready 20161116 YiWei*/
++		return;
++		/*
++		RTW_INFO("P2P_PS_SCAN\n");
++		(&p2p_ps_para)->discovery = 1;
++		(&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;
++		(&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[0];
++		(&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[0];
++		(&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[0];
++		(&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[0];
++		*/
++		break;
++
++	case P2P_PS_SCAN_DONE:
++		/*This feature FW not ready 20161116 YiWei*/
++		return;
++		/*
++		RTW_INFO("P2P_PS_SCAN_DONE\n");
++		(&p2p_ps_para)->discovery = 0;
++		pwdinfo->p2p_ps_state = P2P_PS_ENABLE;
++		(&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;
++		(&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[0];
++		(&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[0];
++		(&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[0];
++		(&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[0];
++		*/
++		break;
++
++	default:
++		break;
++	}
++
++	if (p2p_ps_state != P2P_PS_ENABLE || (&p2p_ps_para)->noa_en == 0) {
++		status = rtw_halmac_p2pps(adapter_to_dvobj(adapter) , (&p2p_ps_para));
++		if (status == -1)
++			RTW_ERR("%s , rtw_halmac_p2pps fail\n", __func__);
++	}
++	_rtw_memcpy(&hal->p2p_ps_offload , (&p2p_ps_para) , sizeof(hal->p2p_ps_offload));
++
++}
++#endif /* RTW_HALMAC */
++#endif /* CONFIG_P2P */
++
++/*
++* rtw_hal_set_FwMediaStatusRpt_cmd -
++*
++* @adapter:
++* @opmode:  0:disconnect, 1:connect
++* @miracast: 0:it's not in miracast scenario. 1:it's in miracast scenario
++* @miracast_sink: 0:source. 1:sink
++* @role: The role of this macid. 0:rsvd. 1:STA. 2:AP. 3:GC. 4:GO. 5:TDLS
++* @macid:
++* @macid_ind:  0:update Media Status to macid.  1:update Media Status from macid to macid_end
++* @macid_end:
++*/
++s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, bool macid_ind, u8 macid_end)
++{
++	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
++	u8 parm[H2C_MEDIA_STATUS_RPT_LEN] = {0};
++	int i;
++	s32 ret;
++#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++	u8 hw_port = rtw_hal_get_port(adapter);
++#endif
++	u8 op_num_change_bmp = 0;
++
++	SET_H2CCMD_MSRRPT_PARM_OPMODE(parm, opmode);
++	SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, macid_ind);
++	SET_H2CCMD_MSRRPT_PARM_MIRACAST(parm, miracast);
++	SET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(parm, miracast_sink);
++	SET_H2CCMD_MSRRPT_PARM_ROLE(parm, role);
++	SET_H2CCMD_MSRRPT_PARM_MACID(parm, macid);
++	SET_H2CCMD_MSRRPT_PARM_MACID_END(parm, macid_end);
++#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++	SET_H2CCMD_MSRRPT_PARM_PORT_NUM(parm, hw_port);
++#endif
++	RTW_DBG_DUMP("MediaStatusRpt parm:", parm, H2C_MEDIA_STATUS_RPT_LEN);
++
++	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_MEDIA_STATUS_RPT, H2C_MEDIA_STATUS_RPT_LEN, parm);
++	if (ret != _SUCCESS)
++		goto exit;
++
++#if defined(CONFIG_RTL8188E)
++	if (rtw_get_chip_type(adapter) == RTL8188E) {
++		HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++
++		/* 8188E FW doesn't set macid no link, driver does it by self */
++		if (opmode)
++			rtw_hal_set_hwreg(adapter, HW_VAR_MACID_LINK, &macid);
++		else
++			rtw_hal_set_hwreg(adapter, HW_VAR_MACID_NOLINK, &macid);
++
++		/* for 8188E RA */
++#if (RATE_ADAPTIVE_SUPPORT == 1)
++		if (hal_data->fw_ractrl == _FALSE) {
++			u8 max_macid;
++
++			max_macid = rtw_search_max_mac_id(adapter);
++			rtw_hal_set_hwreg(adapter, HW_VAR_TX_RPT_MAX_MACID, &max_macid);
++		}
++#endif
++	}
++#endif
++
++#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
++	/* TODO: this should move to IOT issue area */
++	if (rtw_get_chip_type(adapter) == RTL8812
++		|| rtw_get_chip_type(adapter) == RTL8821
++	) {
++		if (MLME_IS_STA(adapter))
++			Hal_PatchwithJaguar_8812(adapter, opmode);
++	}
++#endif
++
++	SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, 0);
++	if (macid_ind == 0)
++		macid_end = macid;
++
++	for (i = macid; macid <= macid_end; macid++) {
++		op_num_change_bmp |= rtw_macid_ctl_set_h2c_msr(macid_ctl, macid, parm[0]);
++		if (!opmode) {
++			rtw_macid_ctl_set_bw(macid_ctl, macid, CHANNEL_WIDTH_20);
++			rtw_macid_ctl_set_vht_en(macid_ctl, macid, 0);
++			rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, 0);
++			rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, 0);
++		}
++	}
++
++#if CONFIG_TX_AC_LIFETIME
++	if (op_num_change_bmp)
++		rtw_hal_update_tx_aclt(adapter);
++#endif
++
++	if (!opmode)
++		rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
++
++exit:
++	return ret;
++}
++
++inline s32 rtw_hal_set_FwMediaStatusRpt_single_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid)
++{
++	return rtw_hal_set_FwMediaStatusRpt_cmd(adapter, opmode, miracast, miracast_sink, role, macid, 0, 0);
++}
++
++inline s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, u8 macid_end)
++{
++	return rtw_hal_set_FwMediaStatusRpt_cmd(adapter, opmode, miracast, miracast_sink, role, macid, 1, macid_end);
++}
++
++void rtw_hal_set_FwRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)
++{
++	u8	u1H2CRsvdPageParm[H2C_RSVDPAGE_LOC_LEN] = {0};
++	u8	ret = 0;
++
++	RTW_INFO("RsvdPageLoc: ProbeRsp=%d PsPoll=%d Null=%d QoSNull=%d BTNull=%d\n",
++		 rsvdpageloc->LocProbeRsp, rsvdpageloc->LocPsPoll,
++		 rsvdpageloc->LocNullData, rsvdpageloc->LocQosNull,
++		 rsvdpageloc->LocBTQosNull);
++
++	SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1H2CRsvdPageParm, rsvdpageloc->LocProbeRsp);
++	SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1H2CRsvdPageParm, rsvdpageloc->LocPsPoll);
++	SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocNullData);
++	SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocQosNull);
++	SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocBTQosNull);
++
++	ret = rtw_hal_fill_h2c_cmd(padapter,
++				   H2C_RSVD_PAGE,
++				   H2C_RSVDPAGE_LOC_LEN,
++				   u1H2CRsvdPageParm);
++
++}
++
++#ifdef CONFIG_GPIO_WAKEUP
++void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++
++	if (IS_8723D_SERIES(pHalData->version_id) || IS_8192F_SERIES(pHalData->version_id)
++		|| IS_8822B_SERIES(pHalData->version_id) || IS_8821C_SERIES(pHalData->version_id)
++		|| IS_8822C_SERIES(pHalData->version_id))
++		rtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable));
++	/*
++	* Switch GPIO_13, GPIO_14 to wlan control, or pull GPIO_13,14 MUST fail.
++	* It happended at 8723B/8192E/8821A. New IC will check multi function GPIO,
++	* and implement HAL function.
++	* TODO: GPIO_8 multi function?
++	*/
++
++	if ((index == 13 || index == 14)
++		#if defined(CONFIG_RTL8821A) && defined(CONFIG_SDIO_HCI)
++		/* 8821A's LED2 circuit(used by HW_LED strategy) needs enable WL GPIO control of GPIO[14:13], can't disable */
++		&& (!IS_HW_LED_STRATEGY(rtw_led_get_strategy(padapter)) || enable)
++		#endif
++	)
++		rtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable));
++}
++
++void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval)
++{
++#if defined(CONFIG_RTL8192F)
++	rtw_hal_set_hwreg(padapter, HW_VAR_WOW_OUTPUT_GPIO, (u8 *)(&outputval));
++#else
++	if (index <= 7) {
++		/* config GPIO mode */
++		rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3,
++			rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index));
++
++		/* config GPIO Sel */
++		/* 0: input */
++		/* 1: output */
++		rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2,
++			rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) | BIT(index));
++
++		/* set output value */
++		if (outputval) {
++			rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1,
++				rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) | BIT(index));
++		} else {
++			rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1,
++				rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) & ~BIT(index));
++		}
++	} else if (index <= 15) {
++		/* 88C Series: */
++		/* index: 11~8 transform to 3~0 */
++		/* 8723 Series: */
++		/* index: 12~8 transform to 4~0 */
++
++		index -= 8;
++
++		/* config GPIO mode */
++		rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3,
++			rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index));
++
++		/* config GPIO Sel */
++		/* 0: input */
++		/* 1: output */
++		rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2,
++			rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) | BIT(index));
++
++		/* set output value */
++		if (outputval) {
++			rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1,
++				rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) | BIT(index));
++		} else {
++			rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1,
++				rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) & ~BIT(index));
++		}
++	} else {
++		RTW_INFO("%s: invalid GPIO%d=%d\n",
++			 __FUNCTION__, index, outputval);
++	}
++#endif
++}
++void rtw_hal_set_input_gpio(_adapter *padapter, u8 index)
++{
++#if defined(CONFIG_RTL8192F)
++	rtw_hal_set_hwreg(padapter, HW_VAR_WOW_INPUT_GPIO, (u8 *)(&index));
++#else
++	if (index <= 7) {
++		/* config GPIO mode */
++		rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3,
++			rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index));
++
++		/* config GPIO Sel */
++		/* 0: input */
++		/* 1: output */
++		rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2,
++			rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) & ~BIT(index));
++
++	} else if (index <= 15) {
++		/* 88C Series: */
++		/* index: 11~8 transform to 3~0 */
++		/* 8723 Series: */
++		/* index: 12~8 transform to 4~0 */
++
++		index -= 8;
++
++		/* config GPIO mode */
++		rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3,
++			rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index));
++
++		/* config GPIO Sel */
++		/* 0: input */
++		/* 1: output */
++		rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2,
++			rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) & ~BIT(index));
++	} else
++		RTW_INFO("%s: invalid GPIO%d\n", __func__, index);
++#endif
++}
++
++#endif
++
++void rtw_hal_set_FwAoacRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)
++{
++	struct	pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	u8 ret = 0;
++#ifdef CONFIG_WOWLAN
++	u8 u1H2CAoacRsvdPageParm[H2C_AOAC_RSVDPAGE_LOC_LEN] = {0};
++
++	RTW_INFO("%s: RWC: %d ArpRsp: %d NbrAdv: %d LocNDPInfo: %d\n",
++		 __func__, rsvdpageloc->LocRemoteCtrlInfo,
++		 rsvdpageloc->LocArpRsp, rsvdpageloc->LocNbrAdv,
++		 rsvdpageloc->LocNDPInfo);
++	RTW_INFO("%s:GtkRsp: %d GtkInfo: %d ProbeReq: %d NetworkList: %d\n",
++		 __func__, rsvdpageloc->LocGTKRsp, rsvdpageloc->LocGTKInfo,
++		 rsvdpageloc->LocProbeReq, rsvdpageloc->LocNetList);
++
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
++		SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocRemoteCtrlInfo);
++		SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocArpRsp);
++		SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(u1H2CAoacRsvdPageParm,
++							rsvdpageloc->LocNbrAdv);
++		SET_H2CCMD_AOAC_RSVDPAGE_LOC_NDP_INFO(u1H2CAoacRsvdPageParm,
++						      rsvdpageloc->LocNDPInfo);
++#ifdef CONFIG_GTK_OL
++		SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKRsp);
++		SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKInfo);
++		SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKEXTMEM);
++#endif /* CONFIG_GTK_OL */
++		ret = rtw_hal_fill_h2c_cmd(padapter,
++					   H2C_AOAC_RSVD_PAGE,
++					   H2C_AOAC_RSVDPAGE_LOC_LEN,
++					   u1H2CAoacRsvdPageParm);
++
++		RTW_INFO("AOAC Report=%d\n", rsvdpageloc->LocAOACReport);
++		_rtw_memset(&u1H2CAoacRsvdPageParm, 0, sizeof(u1H2CAoacRsvdPageParm));
++		SET_H2CCMD_AOAC_RSVDPAGE_LOC_AOAC_REPORT(u1H2CAoacRsvdPageParm,
++					 rsvdpageloc->LocAOACReport);
++		ret = rtw_hal_fill_h2c_cmd(padapter,
++				   H2C_AOAC_RSVDPAGE3,
++				   H2C_AOAC_RSVDPAGE_LOC_LEN,
++				   u1H2CAoacRsvdPageParm);
++		pwrpriv->wowlan_aoac_rpt_loc = rsvdpageloc->LocAOACReport;
++	}
++#ifdef CONFIG_PNO_SUPPORT
++	else {
++
++		if (!pwrpriv->wowlan_in_resume) {
++			RTW_INFO("NLO_INFO=%d\n", rsvdpageloc->LocPNOInfo);
++			_rtw_memset(&u1H2CAoacRsvdPageParm, 0,
++				    sizeof(u1H2CAoacRsvdPageParm));
++			SET_H2CCMD_AOAC_RSVDPAGE_LOC_NLO_INFO(u1H2CAoacRsvdPageParm,
++						      rsvdpageloc->LocPNOInfo);
++			ret = rtw_hal_fill_h2c_cmd(padapter,
++						   H2C_AOAC_RSVDPAGE3,
++						   H2C_AOAC_RSVDPAGE_LOC_LEN,
++						   u1H2CAoacRsvdPageParm);
++		}
++	}
++#endif /* CONFIG_PNO_SUPPORT */
++#endif /* CONFIG_WOWLAN */
++}
++
++#ifdef DBG_FW_DEBUG_MSG_PKT
++void rtw_hal_set_fw_dbg_msg_pkt_rsvd_page_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)
++{
++	struct	hal_ops *pHalFunc = &padapter->hal_func;
++	u8	u1H2C_fw_dbg_msg_pkt_parm[H2C_FW_DBG_MSG_PKT_LEN] = {0};
++	u8	ret = 0;
++
++
++	RTW_INFO("RsvdPageLoc: loc_fw_dbg_msg_pkt =%d\n", rsvdpageloc->loc_fw_dbg_msg_pkt);
++
++	SET_H2CCMD_FW_DBG_MSG_PKT_EN(u1H2C_fw_dbg_msg_pkt_parm, 1);
++	SET_H2CCMD_RSVDPAGE_LOC_FW_DBG_MSG_PKT(u1H2C_fw_dbg_msg_pkt_parm, rsvdpageloc->loc_fw_dbg_msg_pkt);
++	ret = rtw_hal_fill_h2c_cmd(padapter,
++				   H2C_FW_DBG_MSG_PKT,
++				   H2C_FW_DBG_MSG_PKT_LEN,
++				   u1H2C_fw_dbg_msg_pkt_parm);
++
++}
++#endif /*DBG_FW_DEBUG_MSG_PKT*/
++
++/*#define DBG_GET_RSVD_PAGE*/
++int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset,
++	u32 page_num, u8 *buffer, u32 buffer_size)
++{
++	u32 addr = 0, size = 0, count = 0;
++	u32 page_size = 0, data_low = 0, data_high = 0;
++	u16 txbndy = 0, offset = 0;
++	u8 i = 0;
++	bool rst = _FALSE;
++
++#ifdef DBG_LA_MODE
++	struct registry_priv *registry_par = &adapter->registrypriv;
++
++	if(registry_par->la_mode_en == 1) {
++		RTW_INFO("%s LA debug mode can't dump rsvd pg \n", __func__);
++		return rst;
++	}
++#endif
++	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
++
++	addr = page_offset * page_size;
++	size = page_num * page_size;
++
++	if (buffer_size < size) {
++		RTW_ERR("%s buffer_size(%d) < get page total size(%d)\n",
++			__func__, buffer_size, size);
++		return rst;
++	}
++#ifdef RTW_HALMAC
++	if (rtw_halmac_dump_fifo(adapter_to_dvobj(adapter), 2, addr, size, buffer) < 0)
++		rst = _FALSE;
++	else
++		rst = _TRUE;
++#else
++	txbndy = rtw_read8(adapter, REG_TDECTRL + 1);
++
++	offset = (txbndy + page_offset) * page_size / 8;
++	count = (buffer_size / 8) + 1;
++
++	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, 0x69);
++
++	for (i = 0 ; i < count ; i++) {
++		rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, offset + i);
++		data_low = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
++		data_high = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
++		_rtw_memcpy(buffer + (i * 8),
++			&data_low, sizeof(data_low));
++		_rtw_memcpy(buffer + ((i * 8) + 4),
++			&data_high, sizeof(data_high));
++	}
++	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, 0x0);
++	rst = _TRUE;
++#endif /*RTW_HALMAC*/
++
++#ifdef DBG_GET_RSVD_PAGE
++	RTW_INFO("%s [page_offset:%d , page_num:%d][start_addr:0x%04x , size:%d]\n",
++		 __func__, page_offset, page_num, addr, size);
++	RTW_INFO_DUMP("\n", buffer, size);
++	RTW_INFO(" ==================================================\n");
++#endif
++	return rst;
++}
++
++void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num)
++{
++	u32 page_size = 0;
++	u8 *buffer = NULL;
++	u32 buf_size = 0;
++
++	if (page_num == 0)
++		return;
++
++	RTW_PRINT_SEL(sel, "======= RSVD PAGE DUMP =======\n");
++	RTW_PRINT_SEL(sel, "page_offset:%d, page_num:%d\n", page_offset, page_num);
++
++	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
++	if (page_size) {
++		buf_size = page_size * page_num;
++		buffer = rtw_zvmalloc(buf_size);
++
++		if (buffer) {
++			rtw_hal_get_rsvd_page(adapter, page_offset, page_num, buffer, buf_size);
++			RTW_DUMP_SEL(sel, buffer, buf_size);
++			rtw_vmfree(buffer, buf_size);
++		} else
++			RTW_PRINT_SEL(sel, "ERROR - rsvd_buf mem allocate failed\n");
++	} else
++			RTW_PRINT_SEL(sel, "ERROR - Tx page size is zero ??\n");
++
++	RTW_PRINT_SEL(sel, "==========================\n");
++}
++
++#ifdef CONFIG_SUPPORT_FIFO_DUMP
++void rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 fifo_size)
++{
++	u8 *buffer = NULL;
++	u32 buff_size = 0;
++	static const char * const fifo_sel_str[] = {
++		"TX", "RX", "RSVD_PAGE", "REPORT", "LLT", "RXBUF_FW"
++	};
++
++	if (fifo_sel > 5) {
++		RTW_ERR("fifo_sel:%d invalid\n", fifo_sel);
++		return;
++	}
++
++	RTW_PRINT_SEL(sel, "========= FIFO DUMP =========\n");
++	RTW_PRINT_SEL(sel, "%s FIFO DUMP [start_addr:0x%04x , size:%d]\n", fifo_sel_str[fifo_sel], fifo_addr, fifo_size);
++
++	if (fifo_size) {
++		buff_size = RND4(fifo_size);
++		buffer = rtw_zvmalloc(buff_size);
++		if (buffer == NULL)
++			buff_size = 0;
++	}
++
++	rtw_halmac_dump_fifo(adapter_to_dvobj(adapter), fifo_sel, fifo_addr, buff_size, buffer);
++
++	if (buffer) {
++		RTW_DUMP_SEL(sel, buffer, fifo_size);
++		rtw_vmfree(buffer, buff_size);
++	}
++
++	RTW_PRINT_SEL(sel, "==========================\n");
++}
++#endif
++
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++static void rtw_hal_force_enable_rxdma(_adapter *adapter)
++{
++	RTW_INFO("%s: Set 0x690=0x00\n", __func__);
++	rtw_write8(adapter, REG_WOW_CTRL,
++		   (rtw_read8(adapter, REG_WOW_CTRL) & 0xf0));
++	RTW_PRINT("%s: Release RXDMA\n", __func__);
++	rtw_write32(adapter, REG_RXPKT_NUM,
++		    (rtw_read32(adapter, REG_RXPKT_NUM) & (~RW_RELEASE_EN)));
++}
++#if defined(CONFIG_RTL8188E)
++static void rtw_hal_disable_tx_report(_adapter *adapter)
++{
++	rtw_write8(adapter, REG_TX_RPT_CTRL,
++		   ((rtw_read8(adapter, REG_TX_RPT_CTRL) & ~BIT(1))) & ~BIT(5));
++	RTW_INFO("disable TXRPT:0x%02x\n", rtw_read8(adapter, REG_TX_RPT_CTRL));
++}
++
++static void rtw_hal_enable_tx_report(_adapter *adapter)
++{
++	rtw_write8(adapter, REG_TX_RPT_CTRL,
++		   ((rtw_read8(adapter, REG_TX_RPT_CTRL) | BIT(1))) | BIT(5));
++	RTW_INFO("enable TX_RPT:0x%02x\n", rtw_read8(adapter, REG_TX_RPT_CTRL));
++}
++#endif
++static void rtw_hal_release_rx_dma(_adapter *adapter)
++{
++	u32 val32 = 0;
++
++	val32 = rtw_read32(adapter, REG_RXPKT_NUM);
++
++	rtw_write32(adapter, REG_RXPKT_NUM, (val32 & (~RW_RELEASE_EN)));
++
++	RTW_INFO("%s, [0x%04x]: 0x%08x\n",
++		 __func__, REG_RXPKT_NUM, (u32)(val32 & (~RW_RELEASE_EN)));
++}
++
++static u8 rtw_hal_pause_rx_dma(_adapter *adapter)
++{
++	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
++	u8 ret = 0;
++	s8 trycnt = 100;
++	u32 tmp = 0;
++	int res = 0;
++	/* RX DMA stop */
++	RTW_PRINT("Pause DMA\n");
++	rtw_write32(adapter, REG_RXPKT_NUM,
++		    (rtw_read32(adapter, REG_RXPKT_NUM) | RW_RELEASE_EN));
++	do {
++		if ((rtw_read32(adapter, REG_RXPKT_NUM) & RXDMA_IDLE)) {
++#ifdef CONFIG_USB_HCI
++			/* stop interface before leave */
++			if (_TRUE == hal->usb_intf_start) {
++				rtw_intf_stop(adapter);
++				RTW_ENABLE_FUNC(adapter, DF_RX_BIT);
++				RTW_ENABLE_FUNC(adapter, DF_TX_BIT);
++			}
++#endif /* CONFIG_USB_HCI */
++
++			RTW_PRINT("RX_DMA_IDLE is true\n");
++			ret = _SUCCESS;
++			break;
++		}
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++		else {
++			res = RecvOnePkt(adapter);
++			RTW_PRINT("RecvOnePkt Result: %d\n", res);
++		}
++#endif /* CONFIG_SDIO_HCI || CONFIG_GSPI_HCI */
++
++#ifdef CONFIG_USB_HCI
++		else {
++			/* to avoid interface start repeatedly  */
++			if (_FALSE == hal->usb_intf_start)
++				rtw_intf_start(adapter);
++		}
++#endif /* CONFIG_USB_HCI */
++	} while (trycnt--);
++
++	if (trycnt < 0) {
++		tmp = rtw_read16(adapter, REG_RXPKT_NUM + 2);
++
++		RTW_PRINT("Stop RX DMA failed......\n");
++#if defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
++		RTW_PRINT("%s, RXPKT_NUM: 0x%04x\n",
++			  __func__, rtw_read16(adapter, REG_RXPKTNUM));
++#else
++		RTW_PRINT("%s, RXPKT_NUM: 0x%02x\n",
++			  __func__, ((tmp & 0xFF00) >> 8));
++#endif
++		if (tmp & BIT(3))
++			RTW_PRINT("%s, RX DMA has req\n",
++				  __func__);
++		else
++			RTW_PRINT("%s, RX DMA no req\n",
++				  __func__);
++		ret = _FAIL;
++	}
++
++	return ret;
++}
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++#ifndef RTW_HALMAC
++static u8 rtw_hal_enable_cpwm2(_adapter *adapter)
++{
++	u8 ret = 0;
++	int res = 0;
++	u32 tmp = 0;
++#ifdef CONFIG_GPIO_WAKEUP
++	return _SUCCESS;
++#else
++	RTW_PRINT("%s\n", __func__);
++
++	res = sdio_local_read(adapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
++	if (!res)
++		RTW_INFO("read SDIO_REG_HIMR: 0x%08x\n", tmp);
++	else
++		RTW_INFO("sdio_local_read fail\n");
++
++	tmp = SDIO_HIMR_CPWM2_MSK;
++
++	res = sdio_local_write(adapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
++
++	if (!res) {
++		res = sdio_local_read(adapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
++		RTW_INFO("read again SDIO_REG_HIMR: 0x%08x\n", tmp);
++		ret = _SUCCESS;
++	} else {
++		RTW_INFO("sdio_local_write fail\n");
++		ret = _FAIL;
++	}
++	return ret;
++#endif /* CONFIG_CPIO_WAKEUP */
++}
++#endif
++#endif /* CONFIG_SDIO_HCI, CONFIG_GSPI_HCI */
++#endif /* CONFIG_WOWLAN || CONFIG_AP_WOWLAN */
++
++#ifdef CONFIG_WOWLAN
++/*
++ * rtw_hal_check_wow_ctrl
++ * chk_type: _TRUE means to check enable, if 0x690 & bit1 (for 8051), WOW enable successful.
++ *									If 0x1C7 == 0 (for 3081), WOW enable successful.
++ *		     _FALSE means to check disable, if 0x690 & bit1 (for 8051), WOW disable fail.
++ *									If 0x120 & bit16 || 0x284 & bit18 (for 3081), WOW disable fail.
++ */
++static u8 rtw_hal_check_wow_ctrl(_adapter *adapter, u8 chk_type)
++{
++	u32 fe1_imr = 0xFF, rxpkt_num = 0xFF;
++	u8 mstatus = 0;
++	u8 reason = 0xFF;
++	u8 trycnt = 25;
++	u8 res = _FALSE;
++
++	if (IS_HARDWARE_TYPE_JAGUAR2(adapter) || IS_HARDWARE_TYPE_JAGUAR3(adapter)) {
++		if (chk_type) {
++			reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
++			RTW_INFO("%s reason:0x%02x\n", __func__, reason);
++
++			while (reason && trycnt > 1) {
++				reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
++				RTW_PRINT("Loop index: %d :0x%02x\n",
++					  trycnt, reason);
++				trycnt--;
++				rtw_msleep_os(20);
++			}
++			if (!reason)
++				res = _TRUE;
++			else
++				res = _FALSE;
++		} else {
++			/* Wait FW to cleare 0x120 bit16, 0x284 bit18 to 0 */
++			fe1_imr = rtw_read32(adapter, REG_FE1IMR); /* RxDone IMR for 3081 */
++			rxpkt_num = rtw_read32(adapter, REG_RXPKT_NUM); /* Release RXDMA */
++			RTW_PRINT("%s REG_FE1IMR (reg120): 0x%x, REG_RXPKT_NUM(reg284): 0x%x\n", __func__, fe1_imr, rxpkt_num);
++
++			while (((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN)) && trycnt > 1) {
++				rtw_msleep_os(20);
++				fe1_imr = rtw_read32(adapter, REG_FE1IMR);
++				rxpkt_num = rtw_read32(adapter, REG_RXPKT_NUM);
++				RTW_PRINT("Loop index: %d :0x%x, 0x%x\n",
++					  trycnt, fe1_imr, rxpkt_num);
++				trycnt--;
++			}
++
++			if ((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN))
++				res = _FALSE;
++			else
++				res = _TRUE;
++		}
++	} else {
++		mstatus = rtw_read8(adapter, REG_WOW_CTRL);
++		RTW_INFO("%s mstatus:0x%02x\n", __func__, mstatus);
++
++
++		if (chk_type) {
++			while (!(mstatus & BIT1) && trycnt > 1) {
++				mstatus = rtw_read8(adapter, REG_WOW_CTRL);
++				RTW_PRINT("Loop index: %d :0x%02x\n",
++					  trycnt, mstatus);
++				trycnt--;
++				rtw_msleep_os(20);
++			}
++			if (mstatus & BIT1)
++				res = _TRUE;
++			else
++				res = _FALSE;
++		} else {
++			while (mstatus & BIT1 && trycnt > 1) {
++				mstatus = rtw_read8(adapter, REG_WOW_CTRL);
++				RTW_PRINT("Loop index: %d :0x%02x\n",
++					  trycnt, mstatus);
++				trycnt--;
++				rtw_msleep_os(20);
++			}
++
++			if (mstatus & BIT1)
++				res = _FALSE;
++			else
++				res = _TRUE;
++		}
++	}
++
++	RTW_PRINT("%s check_type: %d res: %d trycnt: %d\n",
++		  __func__, chk_type, res, (25 - trycnt));
++	return res;
++}
++
++#ifdef CONFIG_PNO_SUPPORT
++static u8 rtw_hal_check_pno_enabled(_adapter *adapter)
++{
++	struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
++	u8 res = 0, count = 0;
++	u8 ret = _FALSE;
++
++	if (ppwrpriv->wowlan_pno_enable && ppwrpriv->wowlan_in_resume == _FALSE) {
++		res = rtw_read8(adapter, REG_PNO_STATUS);
++		while (!(res & BIT(7)) && count < 25) {
++			RTW_INFO("[%d] cmd: 0x81 REG_PNO_STATUS: 0x%02x\n",
++				 count, res);
++			res = rtw_read8(adapter, REG_PNO_STATUS);
++			count++;
++			rtw_msleep_os(2);
++		}
++		if (res & BIT(7))
++			ret = _TRUE;
++		else
++			ret = _FALSE;
++		RTW_INFO("cmd: 0x81 REG_PNO_STATUS: ret(%d)\n", ret);
++	}
++	return ret;
++}
++#endif
++
++static void rtw_hal_backup_rate(_adapter *adapter)
++{
++	RTW_INFO("%s\n", __func__);
++	/* backup data rate to register 0x8b for wowlan FW */
++	rtw_write8(adapter, 0x8d, 1);
++	rtw_write8(adapter, 0x8c, 0);
++	rtw_write8(adapter, 0x8f, 0x40);
++	rtw_write8(adapter, 0x8b, rtw_read8(adapter, 0x2f0));
++}
++
++#ifdef CONFIG_GTK_OL
++static void rtw_hal_fw_sync_cam_id(_adapter *adapter)
++{
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	int cam_id, index = 0;
++	u8 *addr = NULL;
++
++	if (!MLME_IS_STA(adapter))
++		return;
++
++	addr = get_bssid(pmlmepriv);
++
++	if (addr == NULL) {
++		RTW_INFO("%s: get bssid MAC addr fail!!\n", __func__);
++		return;
++	}
++
++	rtw_clean_dk_section(adapter);
++
++	do {
++		cam_id = rtw_camid_search(adapter, addr, index, 1);
++
++		if (cam_id == -1)
++			RTW_INFO("%s: cam_id: %d, key_id:%d\n", __func__, cam_id, index);
++		else
++			rtw_sec_cam_swap(adapter, cam_id, index);
++
++		index++;
++	} while (index < 4);
++
++	rtw_write8(adapter, REG_SECCFG, 0xcc);
++}
++
++static void rtw_hal_update_gtk_offload_info(_adapter *adapter)
++{
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
++	struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	struct security_priv *psecuritypriv = &adapter->securitypriv;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	_irqL irqL;
++	u8 get_key[16];
++	u8 gtk_id = 0, offset = 0, i = 0, sz = 0, aoac_rpt_ver = 0, has_rekey = _FALSE;
++	u64 replay_count = 0, tmp_iv_hdr = 0, pkt_pn = 0;
++
++	if (!MLME_IS_STA(adapter))
++		return;
++
++	_rtw_memset(get_key, 0, sizeof(get_key));
++	_rtw_memcpy(&replay_count,
++		paoac_rpt->replay_counter_eapol_key, 8);
++
++	/*read gtk key index*/
++	gtk_id = paoac_rpt->key_index;
++	aoac_rpt_ver = paoac_rpt->version_info;
++
++	if (aoac_rpt_ver == 0) {
++		/* initial verison */
++		if (gtk_id == 5)
++			has_rekey = _FALSE;
++		else
++			has_rekey = _TRUE;
++	} else if (aoac_rpt_ver >= 1) {
++		/* Add krack patch */
++		if (gtk_id == 5)
++			RTW_WARN("%s FW check iv fail\n", __func__);
++
++		if (aoac_rpt_ver == 1)
++			RTW_WARN("%s aoac report version should be update to v2\n", __func__);
++
++		/* Fix key id mismatch */
++		if (aoac_rpt_ver == 2)
++			has_rekey = paoac_rpt->rekey_ok == 1 ? _TRUE : _FALSE;
++	}
++
++	if (has_rekey == _FALSE) {
++		RTW_INFO("%s no rekey event happened.\n", __func__);
++	} else if (has_rekey == _TRUE) {
++		RTW_INFO("%s update security key.\n", __func__);
++		/*read key from sec-cam,for DK ,keyindex is equal to cam-id*/
++		rtw_sec_read_cam_ent(adapter, gtk_id,
++				     NULL, NULL, get_key);
++		rtw_clean_hw_dk_cam(adapter);
++
++		if (_rtw_camid_is_gk(adapter, gtk_id)) {
++			_enter_critical_bh(&cam_ctl->lock, &irqL);
++			_rtw_memcpy(&dvobj->cam_cache[gtk_id].key,
++				    get_key, 16);
++			_exit_critical_bh(&cam_ctl->lock, &irqL);
++		} else {
++			struct setkey_parm parm_gtk;
++
++			parm_gtk.algorithm = paoac_rpt->security_type;
++			parm_gtk.keyid = gtk_id;
++			_rtw_memcpy(parm_gtk.key, get_key, 16);
++			setkey_hdl(adapter, (u8 *)&parm_gtk);
++		}
++
++		/*update key into related sw variable and sec-cam cache*/
++		psecuritypriv->dot118021XGrpKeyid = gtk_id;
++		_rtw_memcpy(&psecuritypriv->dot118021XGrpKey[gtk_id],
++				get_key, 16);
++		/* update SW TKIP TX/RX MIC value */
++		if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_) {
++			offset = RTW_KEK_LEN + RTW_TKIP_MIC_LEN;
++			_rtw_memcpy(
++				&psecuritypriv->dot118021XGrptxmickey[gtk_id],
++				&(paoac_rpt->group_key[offset]),
++				RTW_TKIP_MIC_LEN);
++
++			offset = RTW_KEK_LEN;
++			_rtw_memcpy(
++				&psecuritypriv->dot118021XGrprxmickey[gtk_id],
++				&(paoac_rpt->group_key[offset]),
++				RTW_TKIP_MIC_LEN);
++		}
++		RTW_PRINT("GTK (%d) "KEY_FMT"\n", gtk_id,
++			KEY_ARG(psecuritypriv->dot118021XGrpKey[gtk_id].skey));
++	}
++
++	/* Update broadcast RX IV */
++	if (psecuritypriv->dot118021XGrpPrivacy == _AES_) {
++		sz = sizeof(psecuritypriv->iv_seq[0]);
++		for (i = 0 ; i < 4 ; i++) {
++			_rtw_memcpy(&tmp_iv_hdr, paoac_rpt->rxgtk_iv[i], sz);
++			tmp_iv_hdr = le64_to_cpu(tmp_iv_hdr);
++			pkt_pn = CCMPH_2_PN(tmp_iv_hdr);
++			_rtw_memcpy(psecuritypriv->iv_seq[i], &pkt_pn, sz);
++		}
++	}
++
++	rtw_clean_dk_section(adapter);
++
++	rtw_write8(adapter, REG_SECCFG, 0x0c);
++
++	#ifdef CONFIG_GTK_OL_DBG
++	/* if (gtk_keyindex != 5) */
++	dump_sec_cam(RTW_DBGDUMP, adapter);
++	dump_sec_cam_cache(RTW_DBGDUMP, adapter);
++	#endif
++}
++#endif /*CONFIG_GTK_OL*/
++
++static void rtw_dump_aoac_rpt(_adapter *adapter)
++{
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
++	struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
++	int i = 0;
++
++	RTW_INFO_DUMP("[AOAC-RPT] IV -", paoac_rpt->iv, 8);
++	RTW_INFO_DUMP("[AOAC-RPT] Replay counter of EAPOL key - ",
++		paoac_rpt->replay_counter_eapol_key, 8);
++	RTW_INFO_DUMP("[AOAC-RPT] Group key - ", paoac_rpt->group_key, 32);
++	RTW_INFO("[AOAC-RPT] Key Index - %d\n", paoac_rpt->key_index);
++	RTW_INFO("[AOAC-RPT] Security Type - %d\n", paoac_rpt->security_type);
++	RTW_INFO("[AOAC-RPT] wow_pattern_idx - %d\n",
++		 paoac_rpt->wow_pattern_idx);
++	RTW_INFO("[AOAC-RPT] version_info - %d\n", paoac_rpt->version_info);
++	RTW_INFO("[AOAC-RPT] rekey_ok - %d\n", paoac_rpt->rekey_ok);
++	RTW_INFO_DUMP("[AOAC-RPT] RX PTK IV-", paoac_rpt->rxptk_iv, 8);
++	RTW_INFO_DUMP("[AOAC-RPT] RX GTK[0] IV-", paoac_rpt->rxgtk_iv[0], 8);
++	RTW_INFO_DUMP("[AOAC-RPT] RX GTK[1] IV-", paoac_rpt->rxgtk_iv[1], 8);
++	RTW_INFO_DUMP("[AOAC-RPT] RX GTK[2] IV-", paoac_rpt->rxgtk_iv[2], 8);
++	RTW_INFO_DUMP("[AOAC-RPT] RX GTK[3] IV-", paoac_rpt->rxgtk_iv[3], 8);
++}
++
++static void rtw_hal_get_aoac_rpt(_adapter *adapter)
++{
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
++	struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
++	u32 page_offset = 0, page_number = 0;
++	u32 page_size = 0, buf_size = 0;
++	u8 *buffer = NULL;
++	u8 i = 0, tmp = 0;
++	int ret = -1;
++
++	/* read aoac report from rsvd page */
++	page_offset = pwrctl->wowlan_aoac_rpt_loc;
++	page_number = 1;
++
++	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
++	buf_size = page_size * page_number;
++
++	buffer = rtw_zvmalloc(buf_size);
++
++	if (buffer == NULL) {
++		RTW_ERR("%s buffer allocate failed size(%d)\n",
++			__func__, buf_size);
++		return;
++	}
++
++	RTW_INFO("Get AOAC Report from rsvd page_offset:%d\n", page_offset);
++
++	ret = rtw_hal_get_rsvd_page(adapter, page_offset,
++		page_number, buffer, buf_size);
++
++	if (ret == _FALSE) {
++		RTW_ERR("%s get aoac report failed\n", __func__);
++		rtw_warn_on(1);
++		goto _exit;
++	}
++
++	_rtw_memset(paoac_rpt, 0, sizeof(struct aoac_report));
++	_rtw_memcpy(paoac_rpt, buffer, sizeof(struct aoac_report));
++
++	for (i = 0 ; i < 4 ; i++) {
++		tmp = paoac_rpt->replay_counter_eapol_key[i];
++		paoac_rpt->replay_counter_eapol_key[i] =
++			paoac_rpt->replay_counter_eapol_key[7 - i];
++		paoac_rpt->replay_counter_eapol_key[7 - i] = tmp;
++	}
++
++	rtw_dump_aoac_rpt(adapter);
++
++_exit:
++	if (buffer)
++		rtw_vmfree(buffer, buf_size);
++}
++
++static void rtw_hal_update_tx_iv(_adapter *adapter)
++{
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
++	struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
++	struct sta_info	*psta;
++	struct mlme_ext_priv	*pmlmeext = &(adapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct security_priv	*psecpriv = &adapter->securitypriv;
++
++	u16 val16 = 0;
++	u32 val32 = 0;
++	u64 txiv = 0;
++	u8 *pval = NULL;
++
++	psta = rtw_get_stainfo(&adapter->stapriv,
++			       get_my_bssid(&pmlmeinfo->network));
++
++	/* Update TX iv data. */
++	pval = (u8 *)&paoac_rpt->iv;
++
++	if (psecpriv->dot11PrivacyAlgrthm == _TKIP_) {
++		val16 = ((u16)(paoac_rpt->iv[2]) << 0) +
++			((u16)(paoac_rpt->iv[0]) << 8);
++		val32 = ((u32)(paoac_rpt->iv[4]) << 0) +
++			((u32)(paoac_rpt->iv[5]) << 8) +
++			((u32)(paoac_rpt->iv[6]) << 16) +
++			((u32)(paoac_rpt->iv[7]) << 24);
++	} else if (psecpriv->dot11PrivacyAlgrthm == _AES_) {
++		val16 = ((u16)(paoac_rpt->iv[0]) << 0) +
++			((u16)(paoac_rpt->iv[1]) << 8);
++		val32 = ((u32)(paoac_rpt->iv[4]) << 0) +
++			((u32)(paoac_rpt->iv[5]) << 8) +
++			((u32)(paoac_rpt->iv[6]) << 16) +
++			((u32)(paoac_rpt->iv[7]) << 24);
++	}
++
++	if (psta) {
++		txiv = val16 + ((u64)val32 << 16);
++		if (txiv != 0)
++			psta->dot11txpn.val = txiv;
++	}
++}
++
++static void rtw_hal_update_sw_security_info(_adapter *adapter)
++{
++	struct security_priv *psecpriv = &adapter->securitypriv;
++	u8 sz = sizeof (psecpriv->iv_seq);
++
++	rtw_hal_update_tx_iv(adapter);
++#ifdef CONFIG_GTK_OL
++	if (psecpriv->binstallKCK_KEK == _TRUE &&
++		(psecpriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK || _rtw_wow_chk_cap(adapter, WOW_CAP_TKIP_OL)))
++		rtw_hal_update_gtk_offload_info(adapter);
++#else
++	_rtw_memset(psecpriv->iv_seq, 0, sz);
++#endif
++}
++
++static u8 rtw_hal_set_gpio_custom_cmd(_adapter *adapter, u8 enable)
++{
++	u8 H2CGpioCustomParm[H2C_GPIO_CUSTOM_LEN] = {0};
++	u8 customid = 0x2, special_wakeup_reason = RX_MAGIC_PKT, custom_for_wakeup_reason=0x1;
++	u8 ret = _FAIL;
++
++	RTW_INFO("%s(): enable = %d\n", __func__, enable);
++	
++	if(enable) {
++		SET_H2CCMD_CUSTOMERID(H2CGpioCustomParm, customid);
++		SET_H2CCMD_SPECIAL_WAKE_REASON(H2CGpioCustomParm, special_wakeup_reason);
++		SET_H2CCMD_CUSTOM_WAKE_REASON(H2CGpioCustomParm, custom_for_wakeup_reason);
++	
++		ret = rtw_hal_fill_h2c_cmd(adapter,
++						H2C_GPIO_CUSTOM,
++						H2C_GPIO_CUSTOM_LEN,
++						H2CGpioCustomParm);
++		RTW_DBG("%s(): H2C_cmd=%x, cmd=%02x, %02x, %02x\n", __func__, H2C_GPIO_CUSTOM,
++		H2CGpioCustomParm[0], H2CGpioCustomParm[1], H2CGpioCustomParm[2]);
++	}
++
++	return ret;
++}
++
++static u8 rtw_hal_set_keep_alive_cmd(_adapter *adapter, u8 enable, u8 pkt_type)
++{
++	u8 u1H2CKeepAliveParm[H2C_KEEP_ALIVE_CTRL_LEN] = {0};
++	u8 adopt = 1, check_period = 5;
++	u8 ret = _FAIL;
++	u8 hw_port = rtw_hal_get_port(adapter);
++
++	SET_H2CCMD_KEEPALIVE_PARM_ENABLE(u1H2CKeepAliveParm, enable);
++	SET_H2CCMD_KEEPALIVE_PARM_ADOPT(u1H2CKeepAliveParm, adopt);
++	SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(u1H2CKeepAliveParm, pkt_type);
++	SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(u1H2CKeepAliveParm, check_period);
++#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++	SET_H2CCMD_KEEPALIVE_PARM_PORT_NUM(u1H2CKeepAliveParm, hw_port);
++	RTW_INFO("%s(): enable = %d, port = %d\n", __func__, enable, hw_port);
++#else
++	RTW_INFO("%s(): enable = %d\n", __func__, enable);
++#endif
++	ret = rtw_hal_fill_h2c_cmd(adapter,
++				   H2C_KEEP_ALIVE,
++				   H2C_KEEP_ALIVE_CTRL_LEN,
++				   u1H2CKeepAliveParm);
++
++	return ret;
++}
++
++static u8 rtw_hal_set_disconnect_decision_cmd(_adapter *adapter, u8 enable)
++{
++	u8 u1H2CDisconDecisionParm[H2C_DISCON_DECISION_LEN] = {0};
++	u8 adopt = 1, check_period = 100, trypkt_num = 5;
++	u8 ret = _FAIL;
++	struct registry_priv *pregistry = &adapter->registrypriv;
++	u8 hw_port = rtw_hal_get_port(adapter);
++
++	SET_H2CCMD_DISCONDECISION_PARM_ENABLE(u1H2CDisconDecisionParm, enable);
++	SET_H2CCMD_DISCONDECISION_PARM_ADOPT(u1H2CDisconDecisionParm, adopt);
++	if (!(pregistry->wakeup_event & BIT(2)))
++		SET_H2CCMD_DISCONDECISION_PARM_DISCONNECT_EN(u1H2CDisconDecisionParm, adopt);
++	SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(u1H2CDisconDecisionParm, check_period);
++	SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(u1H2CDisconDecisionParm, trypkt_num);
++#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++	SET_H2CCMD_DISCONDECISION_PORT_NUM(u1H2CDisconDecisionParm, hw_port);
++	RTW_INFO("%s(): enable = %d, port = %d\n", __func__, enable, hw_port);
++#else
++	RTW_INFO("%s(): enable = %d\n", __func__, enable);
++#endif
++
++	ret = rtw_hal_fill_h2c_cmd(adapter,
++				   H2C_DISCON_DECISION,
++				   H2C_DISCON_DECISION_LEN,
++				   u1H2CDisconDecisionParm);
++	return ret;
++}
++
++static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_unit)
++{
++	struct registry_priv  *registry_par = &adapter->registrypriv;
++	struct security_priv *psecpriv = &adapter->securitypriv;
++	struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
++	struct mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
++
++	u8 u1H2CWoWlanCtrlParm[H2C_WOWLAN_LEN] = {0};
++	u8 discont_wake = 0, gpionum = 0, gpio_dur = 0, no_wake = 0;
++	u8 hw_unicast = 0, gpio_pulse_cnt = 0, gpio_pulse_en = 0;
++	u8 sdio_wakeup_enable = 1;
++	u8 gpio_high_active = 0;
++	u8 magic_pkt = 0;
++	u8 gpio_unit = 0; /*0: 64ns, 1: 8ms*/
++	u8 ret = _FAIL;
++#ifdef CONFIG_DIS_UPHY
++	u8 dis_uphy = 0, dis_uphy_unit = 0, dis_uphy_time = 0;
++#endif /* CONFIG_DIS_UPHY */
++
++#ifdef CONFIG_GPIO_WAKEUP
++	gpio_high_active = ppwrpriv->is_high_active;
++	gpionum = ppwrpriv->wowlan_gpio_index;
++	sdio_wakeup_enable = 0;
++#endif /* CONFIG_GPIO_WAKEUP */
++	
++	if(registry_par->suspend_type == FW_IPS_DISABLE_BBRF &&
++	!check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
++		no_wake = 1;
++		
++	if (!ppwrpriv->wowlan_pno_enable &&
++		registry_par->wakeup_event & BIT(0) && !no_wake)
++		magic_pkt = enable;
++
++	if ((registry_par->wakeup_event & BIT(1)) &&
++		(psecpriv->dot11PrivacyAlgrthm == _WEP40_ ||
++		psecpriv->dot11PrivacyAlgrthm == _WEP104_) && !no_wake)
++			hw_unicast = 1;
++
++	if (registry_par->wakeup_event & BIT(2) && !no_wake)
++		discont_wake = enable;
++
++	RTW_INFO("%s(): enable=%d change_unit=%d\n", __func__,
++		 enable, change_unit);
++
++	/* time = (gpio_dur/2) * gpio_unit, default:256 ms */
++	if (enable && change_unit) {
++		gpio_dur = 0x40;
++		gpio_unit = 1;
++		gpio_pulse_en = 1;
++	}
++
++#ifdef CONFIG_PLATFORM_ARM_RK3188
++	if (enable) {
++		gpio_pulse_en = 1;
++		gpio_pulse_cnt = 0x04;
++	}
++#endif
++
++	SET_H2CCMD_WOWLAN_FUNC_ENABLE(u1H2CWoWlanCtrlParm, enable);
++	if(!no_wake)
++		SET_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(u1H2CWoWlanCtrlParm, enable);
++	SET_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(u1H2CWoWlanCtrlParm, magic_pkt);
++	SET_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(u1H2CWoWlanCtrlParm, hw_unicast);
++	SET_H2CCMD_WOWLAN_ALL_PKT_DROP(u1H2CWoWlanCtrlParm, 0);
++	SET_H2CCMD_WOWLAN_GPIO_ACTIVE(u1H2CWoWlanCtrlParm, gpio_high_active);
++
++#ifdef CONFIG_GTK_OL
++	if (psecpriv->binstallKCK_KEK == _TRUE &&
++		(psecpriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK || _rtw_wow_chk_cap(adapter, WOW_CAP_TKIP_OL)))
++		SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 0);
++	else
++		SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 1);
++#else
++	SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, enable);
++#endif
++	SET_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(u1H2CWoWlanCtrlParm, discont_wake);
++	SET_H2CCMD_WOWLAN_GPIONUM(u1H2CWoWlanCtrlParm, gpionum);
++	SET_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(u1H2CWoWlanCtrlParm, sdio_wakeup_enable);
++
++	SET_H2CCMD_WOWLAN_GPIO_DURATION(u1H2CWoWlanCtrlParm, gpio_dur);
++	SET_H2CCMD_WOWLAN_CHANGE_UNIT(u1H2CWoWlanCtrlParm, gpio_unit);
++
++	SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(u1H2CWoWlanCtrlParm, gpio_pulse_en);
++	SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(u1H2CWoWlanCtrlParm, gpio_pulse_cnt);
++
++#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
++	if (enable)
++		SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(u1H2CWoWlanCtrlParm, 1);
++#endif
++
++#ifdef CONFIG_DIS_UPHY
++	if (enable) {
++		dis_uphy = 1;
++		/* time unit: 0 -> ms, 1 -> 256 ms*/
++		dis_uphy_unit = 1;
++		dis_uphy_time = 0x4;
++	}
++
++	SET_H2CCMD_WOWLAN_DISABLE_UPHY(u1H2CWoWlanCtrlParm, dis_uphy);
++	SET_H2CCMD_WOWLAN_UNIT_FOR_UPHY_DISABLE(u1H2CWoWlanCtrlParm, dis_uphy_unit);
++	SET_H2CCMD_WOWLAN_TIME_FOR_UPHY_DISABLE(u1H2CWoWlanCtrlParm, dis_uphy_time);
++	if (ppwrpriv->hst2dev_high_active == 1)
++		SET_H2CCMD_WOWLAN_RISE_HST2DEV(u1H2CWoWlanCtrlParm, 1);
++#ifdef CONFIG_RTW_ONE_PIN_GPIO
++	SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(u1H2CWoWlanCtrlParm, 1);
++	SET_H2CCMD_WOWLAN_DEV2HST_EN(u1H2CWoWlanCtrlParm, 1);
++	SET_H2CCMD_WOWLAN_HST2DEV_EN(u1H2CWoWlanCtrlParm, 0);
++#else
++	SET_H2CCMD_WOWLAN_HST2DEV_EN(u1H2CWoWlanCtrlParm, 1);
++#endif /* CONFIG_RTW_ONE_PIN_GPIO */
++#endif /* CONFIG_DIS_UPHY */
++
++
++	ret = rtw_hal_fill_h2c_cmd(adapter,
++				   H2C_WOWLAN,
++				   H2C_WOWLAN_LEN,
++				   u1H2CWoWlanCtrlParm);
++	return ret;
++}
++
++static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable)
++{
++	struct security_priv *psecuritypriv = &(adapter->securitypriv);
++	struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
++	struct registry_priv *pregistrypriv = &adapter->registrypriv;
++	u8 u1H2CRemoteWakeCtrlParm[H2C_REMOTE_WAKE_CTRL_LEN] = {0};
++	u8 ret = _FAIL, count = 0, no_wake = 0;
++	struct mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
++
++	RTW_INFO("%s(): enable=%d\n", __func__, enable);
++
++	if(pregistrypriv->suspend_type == FW_IPS_DISABLE_BBRF &&
++	!check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
++		no_wake = 1;
++	if(no_wake) {
++		SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(
++			u1H2CRemoteWakeCtrlParm, enable);
++	} else {
++		if (!ppwrpriv->wowlan_pno_enable) {
++			SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(
++				u1H2CRemoteWakeCtrlParm, enable);
++			SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(
++				u1H2CRemoteWakeCtrlParm, 1);
++	#ifdef CONFIG_GTK_OL
++			if (psecuritypriv->binstallKCK_KEK == _TRUE &&
++				(psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK || _rtw_wow_chk_cap(adapter, WOW_CAP_TKIP_OL))) {
++				SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(
++					u1H2CRemoteWakeCtrlParm, 1);
++			} else {
++				RTW_INFO("no kck kek\n");
++				SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(
++					u1H2CRemoteWakeCtrlParm, 0);
++			}
++	#endif /* CONFIG_GTK_OL */
++	
++	#ifdef CONFIG_IPV6
++			if (ppwrpriv->wowlan_ns_offload_en == _TRUE) {
++				RTW_INFO("enable NS offload\n");
++				SET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(
++					u1H2CRemoteWakeCtrlParm, enable);
++			}
++	
++			/*
++			 * filter NetBios name service pkt to avoid being waked-up
++			 * by this kind of unicast pkt this exceptional modification
++			 * is used for match competitor's behavior
++			 */
++	
++			SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN(
++				u1H2CRemoteWakeCtrlParm, enable);
++	#endif /*CONFIG_IPV6*/
++#if 0 /* replaced by WOWLAN pattern match */
++	#ifdef CONFIG_RTL8192F
++			if (IS_HARDWARE_TYPE_8192F(adapter)){
++				SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(
++					u1H2CRemoteWakeCtrlParm, enable);
++			}
++	#endif /* CONFIG_RTL8192F */
++#endif
++			if ((psecuritypriv->dot11PrivacyAlgrthm == _AES_) ||
++				(psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) ||
++				(psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_)) {
++				SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(
++					u1H2CRemoteWakeCtrlParm, 0);
++			} else {
++				SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(
++					u1H2CRemoteWakeCtrlParm, 1);
++			}
++	
++			if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {
++#ifdef CONFIG_GTK_OL
++				if(_rtw_wow_chk_cap(adapter, WOW_CAP_TKIP_OL))
++					SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(
++						u1H2CRemoteWakeCtrlParm, enable);
++#endif /* CONFIG_GTK_OL */
++				if (IS_HARDWARE_TYPE_8188E(adapter) ||
++				    IS_HARDWARE_TYPE_8812(adapter)) {
++					SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(
++						u1H2CRemoteWakeCtrlParm, 0);
++					SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(
++						u1H2CRemoteWakeCtrlParm, 1);
++				}
++			}
++	
++			SET_H2CCMD_REMOTE_WAKE_CTRL_FW_PARSING_UNTIL_WAKEUP(
++				u1H2CRemoteWakeCtrlParm, 1);
++		}
++	#ifdef CONFIG_PNO_SUPPORT
++		else {
++			SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(
++				u1H2CRemoteWakeCtrlParm, enable);
++			SET_H2CCMD_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(
++				u1H2CRemoteWakeCtrlParm, enable);
++		}
++	#endif
++	
++	#ifdef CONFIG_P2P_WOWLAN
++		if (_TRUE == ppwrpriv->wowlan_p2p_mode) {
++			RTW_INFO("P2P OFFLOAD ENABLE\n");
++			SET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(u1H2CRemoteWakeCtrlParm, 1);
++		} else {
++			RTW_INFO("P2P OFFLOAD DISABLE\n");
++			SET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(u1H2CRemoteWakeCtrlParm, 0);
++		}
++	#endif /* CONFIG_P2P_WOWLAN */
++	}
++
++
++	ret = rtw_hal_fill_h2c_cmd(adapter,
++				   H2C_REMOTE_WAKE_CTRL,
++				   H2C_REMOTE_WAKE_CTRL_LEN,
++				   u1H2CRemoteWakeCtrlParm);
++	return ret;
++}
++
++static u8 rtw_hal_set_global_info_cmd(_adapter *adapter, u8 group_alg, u8 pairwise_alg)
++{
++	u8 ret = _FAIL;
++	u8 u1H2CAOACGlobalInfoParm[H2C_AOAC_GLOBAL_INFO_LEN] = {0};
++
++	RTW_INFO("%s(): group_alg=%d pairwise_alg=%d\n",
++		 __func__, group_alg, pairwise_alg);
++	SET_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(u1H2CAOACGlobalInfoParm,
++			pairwise_alg);
++	SET_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(u1H2CAOACGlobalInfoParm,
++			group_alg);
++
++	ret = rtw_hal_fill_h2c_cmd(adapter,
++				   H2C_AOAC_GLOBAL_INFO,
++				   H2C_AOAC_GLOBAL_INFO_LEN,
++				   u1H2CAOACGlobalInfoParm);
++
++	return ret;
++}
++
++#ifdef CONFIG_PNO_SUPPORT
++static u8 rtw_hal_set_scan_offload_info_cmd(_adapter *adapter,
++		PRSVDPAGE_LOC rsvdpageloc, u8 enable)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	u8 u1H2CScanOffloadInfoParm[H2C_SCAN_OFFLOAD_CTRL_LEN] = {0};
++	u8 res = 0, count = 0, ret = _FAIL;
++
++	RTW_INFO("%s: loc_probe_packet:%d, loc_scan_info: %d loc_ssid_info:%d\n",
++		 __func__, rsvdpageloc->LocProbePacket,
++		 rsvdpageloc->LocScanInfo, rsvdpageloc->LocSSIDInfo);
++
++	SET_H2CCMD_AOAC_NLO_FUN_EN(u1H2CScanOffloadInfoParm, enable);
++	SET_H2CCMD_AOAC_NLO_IPS_EN(u1H2CScanOffloadInfoParm, enable);
++	SET_H2CCMD_AOAC_RSVDPAGE_LOC_SCAN_INFO(u1H2CScanOffloadInfoParm,
++					       rsvdpageloc->LocScanInfo);
++	SET_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_PACKET(u1H2CScanOffloadInfoParm,
++			rsvdpageloc->LocProbePacket);
++	/*
++		SET_H2CCMD_AOAC_RSVDPAGE_LOC_SSID_INFO(u1H2CScanOffloadInfoParm,
++				rsvdpageloc->LocSSIDInfo);
++	*/
++	ret = rtw_hal_fill_h2c_cmd(adapter,
++				   H2C_D0_SCAN_OFFLOAD_INFO,
++				   H2C_SCAN_OFFLOAD_CTRL_LEN,
++				   u1H2CScanOffloadInfoParm);
++	return ret;
++}
++#endif /* CONFIG_PNO_SUPPORT */
++
++void rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable)
++{
++	struct security_priv *psecpriv = &padapter->securitypriv;
++	struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(padapter);
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct registry_priv *pregistry = &padapter->registrypriv;
++	u8	pkt_type = 0, no_wake = 0;
++	
++	if(pregistry->suspend_type == FW_IPS_DISABLE_BBRF &&
++	!check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
++		no_wake = 1;
++
++	RTW_PRINT("+%s()+: enable=%d\n", __func__, enable);
++
++	rtw_hal_set_wowlan_ctrl_cmd(padapter, enable, _FALSE);
++
++	if (enable) {
++		if(!no_wake)
++			rtw_hal_set_global_info_cmd(padapter,
++					    psecpriv->dot118021XGrpPrivacy,
++					    psecpriv->dot11PrivacyAlgrthm);
++
++		if (!(ppwrpriv->wowlan_pno_enable)) {
++			if (!no_wake)
++				rtw_hal_set_disconnect_decision_cmd(padapter,
++								    enable);
++#ifdef CONFIG_ARP_KEEP_ALIVE
++			if ((psecpriv->dot11PrivacyAlgrthm == _WEP40_) ||
++			    (psecpriv->dot11PrivacyAlgrthm == _WEP104_))
++				pkt_type = 0;
++			else
++				pkt_type = 1;
++#else
++			pkt_type = 0;
++#endif /* CONFIG_ARP_KEEP_ALIVE */
++			if(!no_wake)
++				rtw_hal_set_keep_alive_cmd(padapter, enable, pkt_type);
++		}
++#ifdef CONFIG_PNO_SUPPORT
++		rtw_hal_check_pno_enabled(padapter);
++#endif /* CONFIG_PNO_SUPPORT */
++	} else {
++#if 0
++		{
++			u32 PageSize = 0;
++			rtw_hal_get_def_var(padapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&PageSize);
++			dump_TX_FIFO(padapter, 4, PageSize);
++		}
++#endif
++	}
++#ifdef CONFIG_CUSTOM_PULSE
++	rtw_hal_set_gpio_custom_cmd(padapter, enable);
++#endif /* CONFIG_CUSTOM_PULSE */
++	rtw_hal_set_remote_wake_ctrl_cmd(padapter, enable);
++	RTW_PRINT("-%s()-\n", __func__);
++}
++#endif /* CONFIG_WOWLAN */
++
++#ifdef CONFIG_AP_WOWLAN
++static u8 rtw_hal_set_ap_wowlan_ctrl_cmd(_adapter *adapter, u8 enable)
++{
++	struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
++
++	u8 u1H2CAPWoWlanCtrlParm[H2C_AP_WOW_GPIO_CTRL_LEN] = {0};
++	u8 gpionum = 0, gpio_dur = 0;
++	u8 gpio_pulse = enable;
++	u8 sdio_wakeup_enable = 1;
++	u8 gpio_high_active = 0;
++	u8 ret = _FAIL;
++
++#ifdef CONFIG_GPIO_WAKEUP
++	gpio_high_active = ppwrpriv->is_high_active;
++	gpionum = ppwrpriv->wowlan_gpio_index;
++	sdio_wakeup_enable = 0;
++#endif /*CONFIG_GPIO_WAKEUP*/
++
++	RTW_INFO("%s(): enable=%d\n", __func__, enable);
++
++	SET_H2CCMD_AP_WOW_GPIO_CTRL_INDEX(u1H2CAPWoWlanCtrlParm,
++					  gpionum);
++	SET_H2CCMD_AP_WOW_GPIO_CTRL_PLUS(u1H2CAPWoWlanCtrlParm,
++					 gpio_pulse);
++	SET_H2CCMD_AP_WOW_GPIO_CTRL_HIGH_ACTIVE(u1H2CAPWoWlanCtrlParm,
++						gpio_high_active);
++	SET_H2CCMD_AP_WOW_GPIO_CTRL_EN(u1H2CAPWoWlanCtrlParm,
++				       enable);
++	SET_H2CCMD_AP_WOW_GPIO_CTRL_DURATION(u1H2CAPWoWlanCtrlParm,
++					     gpio_dur);
++
++	ret = rtw_hal_fill_h2c_cmd(adapter,
++				   H2C_AP_WOW_GPIO_CTRL,
++				   H2C_AP_WOW_GPIO_CTRL_LEN,
++				   u1H2CAPWoWlanCtrlParm);
++
++	return ret;
++}
++
++static u8 rtw_hal_set_ap_offload_ctrl_cmd(_adapter *adapter, u8 enable)
++{
++	u8 u1H2CAPOffloadCtrlParm[H2C_WOWLAN_LEN] = {0};
++	u8 ret = _FAIL;
++
++	RTW_INFO("%s(): bFuncEn=%d\n", __func__, enable);
++
++	SET_H2CCMD_AP_WOWLAN_EN(u1H2CAPOffloadCtrlParm, enable);
++
++	ret = rtw_hal_fill_h2c_cmd(adapter,
++				   H2C_AP_OFFLOAD,
++				   H2C_AP_OFFLOAD_LEN,
++				   u1H2CAPOffloadCtrlParm);
++
++	return ret;
++}
++
++static u8 rtw_hal_set_ap_ps_cmd(_adapter *adapter, u8 enable)
++{
++	u8 ap_ps_parm[H2C_AP_PS_LEN] = {0};
++	u8 ret = _FAIL;
++
++	RTW_INFO("%s(): enable=%d\n" , __func__ , enable);
++
++	SET_H2CCMD_AP_WOW_PS_EN(ap_ps_parm, enable);
++#ifndef CONFIG_USB_HCI
++	SET_H2CCMD_AP_WOW_PS_32K_EN(ap_ps_parm, enable);
++#endif /*CONFIG_USB_HCI*/
++	SET_H2CCMD_AP_WOW_PS_RF(ap_ps_parm, enable);
++
++	if (enable)
++		SET_H2CCMD_AP_WOW_PS_DURATION(ap_ps_parm, 0x32);
++	else
++		SET_H2CCMD_AP_WOW_PS_DURATION(ap_ps_parm, 0x0);
++
++	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_SAP_PS_,
++				   H2C_AP_PS_LEN, ap_ps_parm);
++
++	return ret;
++}
++
++static void rtw_hal_set_ap_rsvdpage_loc_cmd(PADAPTER padapter,
++		PRSVDPAGE_LOC rsvdpageloc)
++{
++	struct hal_ops *pHalFunc = &padapter->hal_func;
++	u8 rsvdparm[H2C_AOAC_RSVDPAGE_LOC_LEN] = {0};
++	u8 ret = _FAIL, header = 0;
++
++	if (pHalFunc->fill_h2c_cmd == NULL) {
++		RTW_INFO("%s: Please hook fill_h2c_cmd first!\n", __func__);
++		return;
++	}
++
++	header = rtw_read8(padapter, REG_BCNQ_BDNY);
++
++	RTW_INFO("%s: beacon: %d, probeRsp: %d, header:0x%02x\n", __func__,
++		 rsvdpageloc->LocApOffloadBCN,
++		 rsvdpageloc->LocProbeRsp,
++		 header);
++
++	SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_BCN(rsvdparm,
++				      rsvdpageloc->LocApOffloadBCN + header);
++
++	ret = rtw_hal_fill_h2c_cmd(padapter, H2C_BCN_RSVDPAGE,
++				   H2C_BCN_RSVDPAGE_LEN, rsvdparm);
++
++	if (ret == _FAIL)
++		RTW_INFO("%s: H2C_BCN_RSVDPAGE cmd fail\n", __func__);
++
++	rtw_msleep_os(10);
++
++	_rtw_memset(&rsvdparm, 0, sizeof(rsvdparm));
++
++	SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_ProbeRsp(rsvdparm,
++			rsvdpageloc->LocProbeRsp + header);
++
++	ret = rtw_hal_fill_h2c_cmd(padapter, H2C_PROBERSP_RSVDPAGE,
++				   H2C_PROBERSP_RSVDPAGE_LEN, rsvdparm);
++
++	if (ret == _FAIL)
++		RTW_INFO("%s: H2C_PROBERSP_RSVDPAGE cmd fail\n", __func__);
++
++	rtw_msleep_os(10);
++}
++
++static void rtw_hal_set_fw_ap_wow_related_cmd(_adapter *padapter, u8 enable)
++{
++	rtw_hal_set_ap_offload_ctrl_cmd(padapter, enable);
++	rtw_hal_set_ap_wowlan_ctrl_cmd(padapter, enable);
++	rtw_hal_set_ap_ps_cmd(padapter, enable);
++}
++
++static void rtw_hal_ap_wow_enable(_adapter *padapter)
++{
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct sta_info *psta = NULL;
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++#ifdef DBG_CHECK_FW_PS_STATE
++	struct dvobj_priv *psdpriv = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
++#endif /*DBG_CHECK_FW_PS_STATE*/
++	int res;
++	u16 media_status_rpt;
++#ifdef CONFIG_GPIO_WAKEUP
++	u8 val8 = 0;
++#endif
++
++	RTW_INFO("%s, WOWLAN_AP_ENABLE\n", __func__);
++#ifdef DBG_CHECK_FW_PS_STATE
++	if (rtw_fw_ps_state(padapter) == _FAIL) {
++		pdbgpriv->dbg_enwow_dload_fw_fail_cnt++;
++		RTW_PRINT("wowlan enable no leave 32k\n");
++	}
++#endif /*DBG_CHECK_FW_PS_STATE*/
++
++	/* 1. Download WOWLAN FW*/
++	rtw_hal_fw_dl(padapter, _TRUE);
++
++	media_status_rpt = RT_MEDIA_CONNECT;
++	rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT,
++			  (u8 *)&media_status_rpt);
++
++	issue_beacon(padapter, 0);
++
++	rtw_msleep_os(2);
++	#if defined(CONFIG_RTL8188E)
++	if (IS_HARDWARE_TYPE_8188E(padapter))
++		rtw_hal_disable_tx_report(padapter);
++	#endif
++	/* RX DMA stop */
++	res = rtw_hal_pause_rx_dma(padapter);
++	if (res == _FAIL)
++		RTW_PRINT("[WARNING] pause RX DMA fail\n");
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	/* Enable CPWM2 only. */
++	res = rtw_hal_enable_cpwm2(padapter);
++	if (res == _FAIL)
++		RTW_PRINT("[WARNING] enable cpwm2 fail\n");
++#endif
++
++#ifdef CONFIG_GPIO_WAKEUP
++#ifdef CONFIG_RTW_ONE_PIN_GPIO
++	rtw_hal_switch_gpio_wl_ctrl(padapter, pwrpriv->wowlan_gpio_index, _TRUE);
++	rtw_hal_set_input_gpio(padapter, pwrpriv->wowlan_gpio_index);
++#else
++#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
++	if (pwrctrlpriv->is_high_active == 0)
++		rtw_hal_set_input_gpio(padapter, pwrpriv->wowlan_gpio_index);
++	else
++		rtw_hal_set_output_gpio(padapter, pwrpriv->wowlan_gpio_index,
++			GPIO_OUTPUT_LOW);
++#else
++	val8 = (pwrpriv->is_high_active == 0) ? 1 : 0;
++	rtw_hal_set_output_gpio(padapter, pwrpriv->wowlan_gpio_index, val8);
++	rtw_hal_switch_gpio_wl_ctrl(padapter, pwrpriv->wowlan_gpio_index, _TRUE);
++	RTW_INFO("%s: set GPIO_%d to OUTPUT %s state in ap wow suspend and %s_ACTIVE.\n",
++		 __func__, pwrpriv->wowlan_gpio_index, 
++		 pwrpriv->wowlan_gpio_output_state ? "HIGH" : "LOW",
++		 pwrpriv->is_high_active ? "HIGI" : "LOW");
++#endif /* CONFIG_WAKEUP_GPIO_INPUT_MODE */
++#endif /* CONFIG_RTW_ONE_PIN_GPIO */
++#endif /* CONFIG_GPIO_WAKEUP */
++
++	/* 5. Set Enable WOWLAN H2C command. */
++	RTW_PRINT("Set Enable AP WOWLan cmd\n");
++	rtw_hal_set_fw_ap_wow_related_cmd(padapter, 1);
++
++	rtw_write8(padapter, REG_MCUTST_WOWLAN, 0);
++#ifdef CONFIG_USB_HCI
++	rtw_mi_intf_stop(padapter);
++#endif
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
++	/* Invoid SE0 reset signal during suspending*/
++	rtw_write8(padapter, REG_RSV_CTRL, 0x20);
++	if (IS_8188F(pHalData->version_id) == FALSE
++		&& IS_8188GTV(pHalData->version_id) == FALSE)
++		rtw_write8(padapter, REG_RSV_CTRL, 0x60);
++#endif
++}
++
++static void rtw_hal_ap_wow_disable(_adapter *padapter)
++{
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
++#ifdef DBG_CHECK_FW_PS_STATE
++	struct dvobj_priv *psdpriv = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
++#endif /*DBG_CHECK_FW_PS_STATE*/
++	u16 media_status_rpt;
++
++	RTW_INFO("%s, WOWLAN_AP_DISABLE\n", __func__);
++	/* 1. Read wakeup reason*/
++	pwrctl->wowlan_wake_reason = rtw_read8(padapter, REG_MCUTST_WOWLAN);
++
++	RTW_PRINT("wakeup_reason: 0x%02x\n",
++		  pwrctl->wowlan_wake_reason);
++
++	rtw_hal_set_fw_ap_wow_related_cmd(padapter, 0);
++
++	rtw_msleep_os(2);
++#ifdef DBG_CHECK_FW_PS_STATE
++	if (rtw_fw_ps_state(padapter) == _FAIL) {
++		pdbgpriv->dbg_diswow_dload_fw_fail_cnt++;
++		RTW_PRINT("wowlan enable no leave 32k\n");
++	}
++#endif /*DBG_CHECK_FW_PS_STATE*/
++
++	#if defined(CONFIG_RTL8188E)
++	if (IS_HARDWARE_TYPE_8188E(padapter))
++		rtw_hal_enable_tx_report(padapter);
++	#endif
++
++	rtw_hal_force_enable_rxdma(padapter);
++
++	rtw_hal_fw_dl(padapter, _FALSE);
++
++#ifdef CONFIG_GPIO_WAKEUP
++#ifdef CONFIG_RTW_ONE_PIN_GPIO
++	rtw_hal_set_input_gpio(padapter, pwrctl->wowlan_gpio_index);
++#else
++#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
++	if (pwrctl->is_high_active == 0)
++		rtw_hal_set_input_gpio(padapter, pwrctl->wowlan_gpio_index);
++	else
++		rtw_hal_set_output_gpio(padapter, pwrctl->wowlan_gpio_index
++			, GPIO_OUTPUT_LOW);
++#else
++	rtw_hal_set_output_gpio(padapter, pwrctl->wowlan_gpio_index, 
++		pwrctl->wowlan_gpio_output_state);
++	RTW_INFO("%s: set GPIO_%d to OUTPUT %s state in ap wow resume and %s_ACTIVE.\n",
++		 __func__, pwrctl->wowlan_gpio_index, 
++		 pwrctl->wowlan_gpio_output_state ? "HIGH" : "LOW",
++		 pwrctl->is_high_active ? "HIGI" : "LOW");
++#endif /*CONFIG_WAKEUP_GPIO_INPUT_MODE*/
++#endif /* CONFIG_RTW_ONE_PIN_GPIO */
++#endif /* CONFIG_GPIO_WAKEUP */
++	media_status_rpt = RT_MEDIA_CONNECT;
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT,
++			  (u8 *)&media_status_rpt);
++
++	issue_beacon(padapter, 0);
++}
++#endif /*CONFIG_AP_WOWLAN*/
++
++#ifdef CONFIG_P2P_WOWLAN
++static int update_hidden_ssid(u8 *ies, u32 ies_len, u8 hidden_ssid_mode)
++{
++	u8 *ssid_ie;
++	sint ssid_len_ori;
++	int len_diff = 0;
++
++	ssid_ie = rtw_get_ie(ies,  WLAN_EID_SSID, &ssid_len_ori, ies_len);
++
++	/* RTW_INFO("%s hidden_ssid_mode:%u, ssid_ie:%p, ssid_len_ori:%d\n", __FUNCTION__, hidden_ssid_mode, ssid_ie, ssid_len_ori); */
++
++	if (ssid_ie && ssid_len_ori > 0) {
++		switch (hidden_ssid_mode) {
++		case 1: {
++			u8 *next_ie = ssid_ie + 2 + ssid_len_ori;
++			u32 remain_len = 0;
++
++			remain_len = ies_len - (next_ie - ies);
++
++			ssid_ie[1] = 0;
++			_rtw_memcpy(ssid_ie + 2, next_ie, remain_len);
++			len_diff -= ssid_len_ori;
++
++			break;
++		}
++		case 2:
++			_rtw_memset(&ssid_ie[2], 0, ssid_len_ori);
++			break;
++		default:
++			break;
++		}
++	}
++
++	return len_diff;
++}
++
++static void rtw_hal_construct_P2PBeacon(_adapter *padapter, u8 *pframe, u32 *pLength)
++{
++	/* struct xmit_frame	*pmgntframe; */
++	/* struct pkt_attrib	*pattrib; */
++	/* unsigned char	*pframe; */
++	struct rtw_ieee80211_hdr *pwlanhdr;
++	unsigned short *fctrl;
++	unsigned int	rate_len;
++	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
++	u32	pktlen;
++	/* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
++	/*	_irqL irqL;
++	 *	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	 * #endif */ /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
++	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++#ifdef CONFIG_P2P
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++#endif /* CONFIG_P2P */
++
++	/* for debug */
++	u8 *dbgbuf = pframe;
++	u8 dbgbufLen = 0, index = 0;
++
++	RTW_INFO("%s\n", __FUNCTION__);
++	/* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
++	/*	_enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
++	 * #endif */ /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
++	/* pmlmeext->mgnt_seq++; */
++	set_frame_sub_type(pframe, WIFI_BEACON);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
++		/* RTW_INFO("ie len=%d\n", cur_network->IELength); */
++#ifdef CONFIG_P2P
++		/* for P2P : Primary Device Type & Device Name */
++		u32 wpsielen = 0, insert_len = 0;
++		u8 *wpsie = NULL;
++		wpsie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen);
++
++		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && wpsie && wpsielen > 0) {
++			uint wps_offset, remainder_ielen;
++			u8 *premainder_ie, *pframe_wscie;
++
++			wps_offset = (uint)(wpsie - cur_network->IEs);
++
++			premainder_ie = wpsie + wpsielen;
++
++			remainder_ielen = cur_network->IELength - wps_offset - wpsielen;
++
++#ifdef CONFIG_IOCTL_CFG80211
++			if (pwdinfo->driver_interface == DRIVER_CFG80211) {
++				if (pmlmepriv->wps_beacon_ie && pmlmepriv->wps_beacon_ie_len > 0) {
++					_rtw_memcpy(pframe, cur_network->IEs, wps_offset);
++					pframe += wps_offset;
++					pktlen += wps_offset;
++
++					_rtw_memcpy(pframe, pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len);
++					pframe += pmlmepriv->wps_beacon_ie_len;
++					pktlen += pmlmepriv->wps_beacon_ie_len;
++
++					/* copy remainder_ie to pframe */
++					_rtw_memcpy(pframe, premainder_ie, remainder_ielen);
++					pframe += remainder_ielen;
++					pktlen += remainder_ielen;
++				} else {
++					_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
++					pframe += cur_network->IELength;
++					pktlen += cur_network->IELength;
++				}
++			} else
++#endif /* CONFIG_IOCTL_CFG80211 */
++			{
++				pframe_wscie = pframe + wps_offset;
++				_rtw_memcpy(pframe, cur_network->IEs, wps_offset + wpsielen);
++				pframe += (wps_offset + wpsielen);
++				pktlen += (wps_offset + wpsielen);
++
++				/* now pframe is end of wsc ie, insert Primary Device Type & Device Name */
++				/*	Primary Device Type */
++				/*	Type: */
++				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);
++				insert_len += 2;
++
++				/*	Length: */
++				*(u16 *)(pframe + insert_len) = cpu_to_be16(0x0008);
++				insert_len += 2;
++
++				/*	Value: */
++				/*	Category ID */
++				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
++				insert_len += 2;
++
++				/*	OUI */
++				*(u32 *)(pframe + insert_len) = cpu_to_be32(WPSOUI);
++				insert_len += 4;
++
++				/*	Sub Category ID */
++				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
++				insert_len += 2;
++
++
++				/*	Device Name */
++				/*	Type: */
++				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
++				insert_len += 2;
++
++				/*	Length: */
++				*(u16 *)(pframe + insert_len) = cpu_to_be16(pwdinfo->device_name_len);
++				insert_len += 2;
++
++				/*	Value: */
++				_rtw_memcpy(pframe + insert_len, pwdinfo->device_name, pwdinfo->device_name_len);
++				insert_len += pwdinfo->device_name_len;
++
++
++				/* update wsc ie length */
++				*(pframe_wscie + 1) = (wpsielen - 2) + insert_len;
++
++				/* pframe move to end */
++				pframe += insert_len;
++				pktlen += insert_len;
++
++				/* copy remainder_ie to pframe */
++				_rtw_memcpy(pframe, premainder_ie, remainder_ielen);
++				pframe += remainder_ielen;
++				pktlen += remainder_ielen;
++			}
++		} else
++#endif /* CONFIG_P2P */
++		{
++			int len_diff;
++			_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
++			len_diff = update_hidden_ssid(
++					   pframe + _BEACON_IE_OFFSET_
++				   , cur_network->IELength - _BEACON_IE_OFFSET_
++					   , pmlmeinfo->hidden_ssid_mode
++				   );
++			pframe += (cur_network->IELength + len_diff);
++			pktlen += (cur_network->IELength + len_diff);
++		}
++#if 0
++		{
++			u8 *wps_ie;
++			uint wps_ielen;
++			u8 sr = 0;
++			wps_ie = rtw_get_wps_ie(pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_,
++				pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_, NULL, &wps_ielen);
++			if (wps_ie && wps_ielen > 0)
++				rtw_get_wps_attr_content(wps_ie,  wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);
++			if (sr != 0)
++				set_fwstate(pmlmepriv, WIFI_UNDER_WPS);
++			else
++				_clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS);
++		}
++#endif
++#ifdef CONFIG_P2P
++		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++			u32 len;
++#ifdef CONFIG_IOCTL_CFG80211
++			if (pwdinfo->driver_interface == DRIVER_CFG80211) {
++				len = pmlmepriv->p2p_beacon_ie_len;
++				if (pmlmepriv->p2p_beacon_ie && len > 0)
++					_rtw_memcpy(pframe, pmlmepriv->p2p_beacon_ie, len);
++			} else
++#endif /* CONFIG_IOCTL_CFG80211 */
++			{
++				len = build_beacon_p2p_ie(pwdinfo, pframe);
++			}
++
++			pframe += len;
++			pktlen += len;
++
++			#ifdef CONFIG_WFD
++			len = rtw_append_beacon_wfd_ie(padapter, pframe);
++			pframe += len;
++			pktlen += len;
++			#endif
++
++		}
++#endif /* CONFIG_P2P */
++
++		goto _issue_bcn;
++
++	}
++
++	/* below for ad-hoc mode */
++
++	/* timestamp will be inserted by hardware */
++	pframe += 8;
++	pktlen += 8;
++
++	/* beacon interval: 2 bytes */
++
++	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
++
++	pframe += 2;
++	pktlen += 2;
++
++	/* capability info: 2 bytes */
++
++	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
++
++	pframe += 2;
++	pktlen += 2;
++
++	/* SSID */
++	pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen);
++
++	/* supported rates... */
++	rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
++	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen);
++
++	/* DS parameter set */
++	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen);
++
++	/* if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) */
++	{
++		u8 erpinfo = 0;
++		u32 ATIMWindow;
++		/* IBSS Parameter Set... */
++		/* ATIMWindow = cur->Configuration.ATIMWindow; */
++		ATIMWindow = 0;
++		pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen);
++
++		/* ERP IE */
++		pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pktlen);
++	}
++
++
++	/* EXTERNDED SUPPORTED RATE */
++	if (rate_len > 8)
++		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen);
++
++
++	/* todo:HT for adhoc */
++
++_issue_bcn:
++
++	/* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
++	/*	pmlmepriv->update_bcn = _FALSE;
++	 *
++	 *	_exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
++	 * #endif */ /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
++
++	*pLength = pktlen;
++#if 0
++	/* printf dbg msg */
++	dbgbufLen = pktlen;
++	RTW_INFO("======> DBG MSG FOR CONSTRAUCT P2P BEACON\n");
++
++	for (index = 0; index < dbgbufLen; index++)
++		printk("%x ", *(dbgbuf + index));
++
++	printk("\n");
++	RTW_INFO("<====== DBG MSG FOR CONSTRAUCT P2P BEACON\n");
++
++#endif
++}
++
++static void rtw_hal_construct_P2PProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
++{
++	/* struct xmit_frame			*pmgntframe; */
++	/* struct pkt_attrib			*pattrib; */
++	/* unsigned char					*pframe; */
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	unsigned char					*mac;
++	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	/* WLAN_BSSID_EX 		*cur_network = &(pmlmeinfo->network); */
++	u16					beacon_interval = 100;
++	u16					capInfo = 0;
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++	u8					wpsie[255] = { 0x00 };
++	u32					wpsielen = 0, p2pielen = 0;
++	u32					pktlen;
++#ifdef CONFIG_WFD
++	u32					wfdielen = 0;
++#endif
++
++	/* for debug */
++	u8 *dbgbuf = pframe;
++	u8 dbgbufLen = 0, index = 0;
++
++	RTW_INFO("%s\n", __FUNCTION__);
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	mac = adapter_mac_addr(padapter);
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	/* DA filled by FW */
++	_rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
++
++	/*	Use the device address for BSSID field.	 */
++	_rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, 0);
++	set_frame_sub_type(fctrl, WIFI_PROBERSP);
++
++	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++	pframe += pktlen;
++
++
++	/* timestamp will be inserted by hardware */
++	pframe += 8;
++	pktlen += 8;
++
++	/* beacon interval: 2 bytes */
++	_rtw_memcpy(pframe, (unsigned char *) &beacon_interval, 2);
++	pframe += 2;
++	pktlen += 2;
++
++	/*	capability info: 2 bytes */
++	/*	ESS and IBSS bits must be 0 (defined in the 3.1.2.1.1 of WiFi Direct Spec) */
++	capInfo |= cap_ShortPremble;
++	capInfo |= cap_ShortSlot;
++
++	_rtw_memcpy(pframe, (unsigned char *) &capInfo, 2);
++	pframe += 2;
++	pktlen += 2;
++
++
++	/* SSID */
++	pframe = rtw_set_ie(pframe, _SSID_IE_, 7, pwdinfo->p2p_wildcard_ssid, &pktlen);
++
++	/* supported rates... */
++	/*	Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) */
++	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pktlen);
++
++	/* DS parameter set */
++	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&pwdinfo->listen_channel, &pktlen);
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (pwdinfo->driver_interface == DRIVER_CFG80211) {
++		if (pmlmepriv->wps_probe_resp_ie != NULL && pmlmepriv->p2p_probe_resp_ie != NULL) {
++			/* WPS IE */
++			_rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len);
++			pktlen += pmlmepriv->wps_probe_resp_ie_len;
++			pframe += pmlmepriv->wps_probe_resp_ie_len;
++
++			/* P2P IE */
++			_rtw_memcpy(pframe, pmlmepriv->p2p_probe_resp_ie, pmlmepriv->p2p_probe_resp_ie_len);
++			pktlen += pmlmepriv->p2p_probe_resp_ie_len;
++			pframe += pmlmepriv->p2p_probe_resp_ie_len;
++		}
++	} else
++#endif /* CONFIG_IOCTL_CFG80211		 */
++	{
++
++		/*	Todo: WPS IE */
++		/*	Noted by Albert 20100907 */
++		/*	According to the WPS specification, all the WPS attribute is presented by Big Endian. */
++
++		wpsielen = 0;
++		/*	WPS OUI */
++		*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
++		wpsielen += 4;
++
++		/*	WPS version */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
++		wpsielen += 2;
++
++		/*	Value: */
++		wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
++
++		/*	WiFi Simple Config State */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SIMPLE_CONF_STATE);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
++		wpsielen += 2;
++
++		/*	Value: */
++		wpsie[wpsielen++] = WPS_WSC_STATE_NOT_CONFIG;	/*	Not Configured. */
++
++		/*	Response Type */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_RESP_TYPE);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
++		wpsielen += 2;
++
++		/*	Value: */
++		wpsie[wpsielen++] = WPS_RESPONSE_TYPE_8021X;
++
++		/*	UUID-E */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_UUID_E);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0010);
++		wpsielen += 2;
++
++		/*	Value: */
++		if (pwdinfo->external_uuid == 0) {
++			_rtw_memset(wpsie + wpsielen, 0x0, 16);
++			_rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN);
++		} else
++			_rtw_memcpy(wpsie + wpsielen, pwdinfo->uuid, 0x10);
++		wpsielen += 0x10;
++
++		/*	Manufacturer */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MANUFACTURER);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0007);
++		wpsielen += 2;
++
++		/*	Value: */
++		_rtw_memcpy(wpsie + wpsielen, "Realtek", 7);
++		wpsielen += 7;
++
++		/*	Model Name */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NAME);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0006);
++		wpsielen += 2;
++
++		/*	Value: */
++		_rtw_memcpy(wpsie + wpsielen, "8192CU", 6);
++		wpsielen += 6;
++
++		/*	Model Number */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NUMBER);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
++		wpsielen += 2;
++
++		/*	Value: */
++		wpsie[wpsielen++] = 0x31;		/*	character 1 */
++
++		/*	Serial Number */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SERIAL_NUMBER);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(ETH_ALEN);
++		wpsielen += 2;
++
++		/*	Value: */
++		_rtw_memcpy(wpsie + wpsielen, "123456" , ETH_ALEN);
++		wpsielen += ETH_ALEN;
++
++		/*	Primary Device Type */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008);
++		wpsielen += 2;
++
++		/*	Value: */
++		/*	Category ID */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
++		wpsielen += 2;
++
++		/*	OUI */
++		*(u32 *)(wpsie + wpsielen) = cpu_to_be32(WPSOUI);
++		wpsielen += 4;
++
++		/*	Sub Category ID */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
++		wpsielen += 2;
++
++		/*	Device Name */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->device_name_len);
++		wpsielen += 2;
++
++		/*	Value: */
++		_rtw_memcpy(wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len);
++		wpsielen += pwdinfo->device_name_len;
++
++		/*	Config Method */
++		/*	Type: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);
++		wpsielen += 2;
++
++		/*	Length: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
++		wpsielen += 2;
++
++		/*	Value: */
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
++		wpsielen += 2;
++
++
++		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pktlen);
++
++
++		p2pielen = build_probe_resp_p2p_ie(pwdinfo, pframe);
++		pframe += p2pielen;
++		pktlen += p2pielen;
++	}
++
++#ifdef CONFIG_WFD
++	wfdielen = rtw_append_probe_resp_wfd_ie(padapter, pframe);
++	pframe += wfdielen;
++	pktlen += wfdielen;
++#endif
++
++	*pLength = pktlen;
++
++#if 0
++	/* printf dbg msg */
++	dbgbufLen = pktlen;
++	RTW_INFO("======> DBG MSG FOR CONSTRAUCT P2P Probe Rsp\n");
++
++	for (index = 0; index < dbgbufLen; index++)
++		printk("%x ", *(dbgbuf + index));
++
++	printk("\n");
++	RTW_INFO("<====== DBG MSG FOR CONSTRAUCT P2P Probe Rsp\n");
++#endif
++}
++static void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
++{
++	struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
++	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++	u8			action = P2P_PUB_ACTION_ACTION;
++	u32			p2poui = cpu_to_be32(P2POUI);
++	u8			oui_subtype = P2P_GO_NEGO_RESP;
++	u8			wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };
++	u8			p2pielen = 0, i;
++	uint			wpsielen = 0;
++	u16			wps_devicepassword_id = 0x0000;
++	uint			wps_devicepassword_id_len = 0;
++	u8			channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh;
++	u16			len_channellist_attr = 0;
++	u32			pktlen;
++	u8			dialogToken = 0;
++
++	/* struct xmit_frame			*pmgntframe; */
++	/* struct pkt_attrib			*pattrib; */
++	/* unsigned char					*pframe; */
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++	/* WLAN_BSSID_EX 		*cur_network = &(pmlmeinfo->network); */
++
++#ifdef CONFIG_WFD
++	u32					wfdielen = 0;
++#endif
++
++	/* for debug */
++	u8 *dbgbuf = pframe;
++	u8 dbgbufLen = 0, index = 0;
++
++	RTW_INFO("%s\n", __FUNCTION__);
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	/* RA, filled by FW */
++	_rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, 0);
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++	pframe += pktlen;
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pktlen));
++
++	/* dialog token, filled by FW */
++	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pktlen));
++
++	_rtw_memset(wpsie, 0x00, 255);
++	wpsielen = 0;
++
++	/*	WPS Section */
++	wpsielen = 0;
++	/*	WPS OUI */
++	*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
++	wpsielen += 4;
++
++	/*	WPS version */
++	/*	Type: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
++	wpsielen += 2;
++
++	/*	Length: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
++	wpsielen += 2;
++
++	/*	Value: */
++	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
++
++	/*	Device Password ID */
++	/*	Type: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);
++	wpsielen += 2;
++
++	/*	Length: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
++	wpsielen += 2;
++
++	/*	Value: */
++	if (wps_devicepassword_id == WPS_DPID_USER_SPEC)
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);
++	else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC);
++	else
++		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC);
++	wpsielen += 2;
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pktlen);
++
++
++	/*	P2P IE Section. */
++
++	/*	P2P OUI */
++	p2pielen = 0;
++	p2pie[p2pielen++] = 0x50;
++	p2pie[p2pielen++] = 0x6F;
++	p2pie[p2pielen++] = 0x9A;
++	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
++
++	/*	Commented by Albert 20100908 */
++	/*	According to the P2P Specification, the group negoitation response frame should contain 9 P2P attributes */
++	/*	1. Status */
++	/*	2. P2P Capability */
++	/*	3. Group Owner Intent */
++	/*	4. Configuration Timeout */
++	/*	5. Operating Channel */
++	/*	6. Intended P2P Interface Address */
++	/*	7. Channel List */
++	/*	8. Device Info */
++	/*	9. Group ID	( Only GO ) */
++
++
++	/*	ToDo: */
++
++	/*	P2P Status */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_STATUS;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
++	p2pielen += 2;
++
++	/*	Value, filled by FW */
++	p2pie[p2pielen++] = 1;
++
++	/*	P2P Capability */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Device Capability Bitmap, 1 byte */
++
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
++		/*	Commented by Albert 2011/03/08 */
++		/*	According to the P2P specification */
++		/*	if the sending device will be client, the P2P Capability should be reserved of group negotation response frame */
++		p2pie[p2pielen++] = 0;
++	} else {
++		/*	Be group owner or meet the error case */
++		p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
++	}
++
++	/*	Group Capability Bitmap, 1 byte */
++	if (pwdinfo->persistent_supported)
++		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;
++	else
++		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;
++
++	/*	Group Owner Intent */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_GO_INTENT;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
++	p2pielen += 2;
++
++	/*	Value: */
++	if (pwdinfo->peer_intent & 0x01) {
++		/*	Peer's tie breaker bit is 1, our tie breaker bit should be 0 */
++		p2pie[p2pielen++] = (pwdinfo->intent << 1);
++	} else {
++		/*	Peer's tie breaker bit is 0, our tie breaker bit should be 1 */
++		p2pie[p2pielen++] = ((pwdinfo->intent << 1) | BIT(0));
++	}
++
++
++	/*	Configuration Timeout */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
++	p2pielen += 2;
++
++	/*	Value: */
++	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
++	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
++
++	/*	Operating Channel */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Country String */
++	p2pie[p2pielen++] = 'X';
++	p2pie[p2pielen++] = 'X';
++
++	/*	The third byte should be set to 0x04. */
++	/*	Described in the "Operating Channel Attribute" section. */
++	p2pie[p2pielen++] = 0x04;
++
++	/*	Operating Class */
++	if (pwdinfo->operating_channel <= 14) {
++		/*	Operating Class */
++		p2pie[p2pielen++] = 0x51;
++	} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {
++		/*	Operating Class */
++		p2pie[p2pielen++] = 0x73;
++	} else {
++		/*	Operating Class */
++		p2pie[p2pielen++] = 0x7c;
++	}
++
++	/*	Channel Number */
++	p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
++
++	/*	Intended P2P Interface Address	 */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
++	p2pielen += 2;
++
++	/*	Value: */
++	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
++	p2pielen += ETH_ALEN;
++
++	/*	Channel List */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
++
++	/* Country String(3) */
++	/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
++	/* + number of channels in all classes */
++	len_channellist_attr = 3
++		       + (1 + 1) * (u16)ch_list->reg_classes
++		       + get_reg_classes_full_count(ch_list);
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_buddy_check_fwstate(padapter, WIFI_ASOC_STATE))
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
++	else
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
++
++#else
++
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
++
++#endif
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Country String */
++	p2pie[p2pielen++] = 'X';
++	p2pie[p2pielen++] = 'X';
++
++	/*	The third byte should be set to 0x04. */
++	/*	Described in the "Operating Channel Attribute" section. */
++	p2pie[p2pielen++] = 0x04;
++
++	/*	Channel Entry List */
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_check_status(padapter, MI_LINKED)) {
++		u8 union_ch = rtw_mi_get_union_chan(padapter);
++
++		/*	Operating Class */
++		if (union_ch > 14) {
++			if (union_ch >= 149)
++				p2pie[p2pielen++] = 0x7c;
++			else
++				p2pie[p2pielen++] = 0x73;
++		} else
++			p2pie[p2pielen++] = 0x51;
++
++
++		/*	Number of Channels */
++		/*	Just support 1 channel and this channel is AP's channel */
++		p2pie[p2pielen++] = 1;
++
++		/*	Channel List */
++		p2pie[p2pielen++] = union_ch;
++	} else
++#endif /* CONFIG_CONCURRENT_MODE */
++	{
++		int i, j;
++		for (j = 0; j < ch_list->reg_classes; j++) {
++			/*	Operating Class */
++			p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
++
++			/*	Number of Channels */
++			p2pie[p2pielen++] = ch_list->reg_class[j].channels;
++
++			/*	Channel List */
++			for (i = 0; i < ch_list->reg_class[j].channels; i++)
++				p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
++		}
++	}
++
++	/*	Device Info */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
++	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	P2P Device Address */
++	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
++	p2pielen += ETH_ALEN;
++
++	/*	Config Method */
++	/*	This field should be big endian. Noted by P2P specification. */
++
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
++
++	p2pielen += 2;
++
++	/*	Primary Device Type */
++	/*	Category ID */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
++	p2pielen += 2;
++
++	/*	OUI */
++	*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);
++	p2pielen += 4;
++
++	/*	Sub Category ID */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
++	p2pielen += 2;
++
++	/*	Number of Secondary Device Types */
++	p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
++
++	/*	Device Name */
++	/*	Type: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
++	p2pielen += 2;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);
++	p2pielen += 2;
++
++	/*	Value: */
++	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len);
++	p2pielen += pwdinfo->device_name_len;
++
++	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++		/*	Group ID Attribute */
++		/*	Type: */
++		p2pie[p2pielen++] = P2P_ATTR_GROUP_ID;
++
++		/*	Length: */
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen);
++		p2pielen += 2;
++
++		/*	Value: */
++		/*	p2P Device Address */
++		_rtw_memcpy(p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN);
++		p2pielen += ETH_ALEN;
++
++		/*	SSID */
++		_rtw_memcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);
++		p2pielen += pwdinfo->nego_ssidlen;
++
++	}
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pktlen);
++
++#ifdef CONFIG_WFD
++	wfdielen = build_nego_resp_wfd_ie(pwdinfo, pframe);
++	pframe += wfdielen;
++	pktlen += wfdielen;
++#endif
++
++	*pLength = pktlen;
++#if 0
++	/* printf dbg msg */
++	dbgbufLen = pktlen;
++	RTW_INFO("======> DBG MSG FOR CONSTRAUCT Nego Rsp\n");
++
++	for (index = 0; index < dbgbufLen; index++)
++		printk("%x ", *(dbgbuf + index));
++
++	printk("\n");
++	RTW_INFO("<====== DBG MSG FOR CONSTRAUCT Nego Rsp\n");
++#endif
++}
++
++static void rtw_hal_construct_P2PInviteRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
++{
++	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++	u8			action = P2P_PUB_ACTION_ACTION;
++	u32			p2poui = cpu_to_be32(P2POUI);
++	u8			oui_subtype = P2P_INVIT_RESP;
++	u8			p2pie[255] = { 0x00 };
++	u8			p2pielen = 0, i;
++	u8			channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0;
++	u16			len_channellist_attr = 0;
++	u32			pktlen;
++	u8			dialogToken = 0;
++#ifdef CONFIG_WFD
++	u32					wfdielen = 0;
++#endif
++
++	/* struct xmit_frame			*pmgntframe; */
++	/* struct pkt_attrib			*pattrib; */
++	/* unsigned char					*pframe; */
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++	/* for debug */
++	u8 *dbgbuf = pframe;
++	u8 dbgbufLen = 0, index = 0;
++
++
++	RTW_INFO("%s\n", __FUNCTION__);
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	/* RA fill by FW */
++	_rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++
++	/* BSSID fill by FW */
++	_rtw_memset(pwlanhdr->addr3, 0, ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, 0);
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pktlen));
++
++	/* dialog token, filled by FW */
++	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pktlen));
++
++	/*	P2P IE Section. */
++
++	/*	P2P OUI */
++	p2pielen = 0;
++	p2pie[p2pielen++] = 0x50;
++	p2pie[p2pielen++] = 0x6F;
++	p2pie[p2pielen++] = 0x9A;
++	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
++
++	/*	Commented by Albert 20101005 */
++	/*	According to the P2P Specification, the P2P Invitation response frame should contain 5 P2P attributes */
++	/*	1. Status */
++	/*	2. Configuration Timeout */
++	/*	3. Operating Channel	( Only GO ) */
++	/*	4. P2P Group BSSID	( Only GO ) */
++	/*	5. Channel List */
++
++	/*	P2P Status */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_STATUS;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
++	p2pielen += 2;
++
++	/*	Value: filled by FW, defult value is FAIL INFO UNAVAILABLE */
++	p2pie[p2pielen++] = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
++
++	/*	Configuration Timeout */
++	/*	Type: */
++	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
++
++	/*	Length: */
++	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
++	p2pielen += 2;
++
++	/*	Value: */
++	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
++	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
++
++	/* due to defult value is FAIL INFO UNAVAILABLE, so the following IE is not needed */
++#if 0
++	if (status_code == P2P_STATUS_SUCCESS) {
++		struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
++
++		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++			/*	The P2P Invitation request frame asks this Wi-Fi device to be the P2P GO */
++			/*	In this case, the P2P Invitation response frame should carry the two more P2P attributes. */
++			/*	First one is operating channel attribute. */
++			/*	Second one is P2P Group BSSID attribute. */
++
++			/*	Operating Channel */
++			/*	Type: */
++			p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
++
++			/*	Length: */
++			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
++			p2pielen += 2;
++
++			/*	Value: */
++			/*	Country String */
++			p2pie[p2pielen++] = 'X';
++			p2pie[p2pielen++] = 'X';
++
++			/*	The third byte should be set to 0x04. */
++			/*	Described in the "Operating Channel Attribute" section. */
++			p2pie[p2pielen++] = 0x04;
++
++			/*	Operating Class */
++			p2pie[p2pielen++] = 0x51;	/*	Copy from SD7 */
++
++			/*	Channel Number */
++			p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
++
++
++			/*	P2P Group BSSID */
++			/*	Type: */
++			p2pie[p2pielen++] = P2P_ATTR_GROUP_BSSID;
++
++			/*	Length: */
++			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
++			p2pielen += 2;
++
++			/*	Value: */
++			/*	P2P Device Address for GO */
++			_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
++			p2pielen += ETH_ALEN;
++
++		}
++
++		/*	Channel List */
++		/*	Type: */
++		p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
++
++		/*	Length: */
++		/* Country String(3) */
++		/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
++		/* + number of channels in all classes */
++		len_channellist_attr = 3
++			+ (1 + 1) * (u16)ch_list->reg_classes
++			+ get_reg_classes_full_count(ch_list);
++
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_check_status(padapter, MI_LINKED))
++			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
++		else
++			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
++
++#else
++
++		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
++
++#endif
++		p2pielen += 2;
++
++		/*	Value: */
++		/*	Country String */
++		p2pie[p2pielen++] = 'X';
++		p2pie[p2pielen++] = 'X';
++
++		/*	The third byte should be set to 0x04. */
++		/*	Described in the "Operating Channel Attribute" section. */
++		p2pie[p2pielen++] = 0x04;
++
++		/*	Channel Entry List */
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_check_status(padapter, MI_LINKED)) {
++			u8 union_ch = rtw_mi_get_union_chan(padapter);
++
++			/*	Operating Class */
++			if (union_ch > 14) {
++				if (union_ch >= 149)
++					p2pie[p2pielen++] = 0x7c;
++				else
++					p2pie[p2pielen++] = 0x73;
++
++			} else
++				p2pie[p2pielen++] = 0x51;
++
++
++			/*	Number of Channels */
++			/*	Just support 1 channel and this channel is AP's channel */
++			p2pie[p2pielen++] = 1;
++
++			/*	Channel List */
++			p2pie[p2pielen++] = union_ch;
++		} else
++#endif /* CONFIG_CONCURRENT_MODE */
++		{
++			int i, j;
++			for (j = 0; j < ch_list->reg_classes; j++) {
++				/*	Operating Class */
++				p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
++
++				/*	Number of Channels */
++				p2pie[p2pielen++] = ch_list->reg_class[j].channels;
++
++				/*	Channel List */
++				for (i = 0; i < ch_list->reg_class[j].channels; i++)
++					p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
++			}
++		}
++	}
++#endif
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pktlen);
++
++#ifdef CONFIG_WFD
++	wfdielen = build_invitation_resp_wfd_ie(pwdinfo, pframe);
++	pframe += wfdielen;
++	pktlen += wfdielen;
++#endif
++
++	*pLength = pktlen;
++
++#if 0
++	/* printf dbg msg */
++	dbgbufLen = pktlen;
++	RTW_INFO("======> DBG MSG FOR CONSTRAUCT Invite Rsp\n");
++
++	for (index = 0; index < dbgbufLen; index++)
++		printk("%x ", *(dbgbuf + index));
++
++	printk("\n");
++	RTW_INFO("<====== DBG MSG FOR CONSTRAUCT Invite Rsp\n");
++#endif
++}
++
++
++static void rtw_hal_construct_P2PProvisionDisRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
++{
++	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++	u8			action = P2P_PUB_ACTION_ACTION;
++	u8			dialogToken = 0;
++	u32			p2poui = cpu_to_be32(P2POUI);
++	u8			oui_subtype = P2P_PROVISION_DISC_RESP;
++	u8			wpsie[100] = { 0x00 };
++	u8			wpsielen = 0;
++	u32			pktlen;
++#ifdef CONFIG_WFD
++	u32					wfdielen = 0;
++#endif
++
++	/* struct xmit_frame			*pmgntframe; */
++	/* struct pkt_attrib			*pattrib; */
++	/* unsigned char					*pframe; */
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++	/* for debug */
++	u8 *dbgbuf = pframe;
++	u8 dbgbufLen = 0, index = 0;
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	/* RA filled by FW */
++	_rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, 0);
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pktlen));
++	/* dialog token, filled by FW */
++	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pktlen));
++
++	wpsielen = 0;
++	/*	WPS OUI */
++	/* *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); */
++	RTW_PUT_BE32(wpsie, WPSOUI);
++	wpsielen += 4;
++
++#if 0
++	/*	WPS version */
++	/*	Type: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
++	wpsielen += 2;
++
++	/*	Length: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
++	wpsielen += 2;
++
++	/*	Value: */
++	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
++#endif
++
++	/*	Config Method */
++	/*	Type: */
++	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); */
++	RTW_PUT_BE16(wpsie + wpsielen, WPS_ATTR_CONF_METHOD);
++	wpsielen += 2;
++
++	/*	Length: */
++	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); */
++	RTW_PUT_BE16(wpsie + wpsielen, 0x0002);
++	wpsielen += 2;
++
++	/*	Value: filled by FW, default value is PBC */
++	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( config_method ); */
++	RTW_PUT_BE16(wpsie + wpsielen, WPS_CM_PUSH_BUTTON);
++	wpsielen += 2;
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pktlen);
++
++#ifdef CONFIG_WFD
++	wfdielen = build_provdisc_resp_wfd_ie(pwdinfo, pframe);
++	pframe += wfdielen;
++	pktlen += wfdielen;
++#endif
++
++	*pLength = pktlen;
++
++	/* printf dbg msg */
++#if 0
++	dbgbufLen = pktlen;
++	RTW_INFO("======> DBG MSG FOR CONSTRAUCT  ProvisionDis Rsp\n");
++
++	for (index = 0; index < dbgbufLen; index++)
++		printk("%x ", *(dbgbuf + index));
++
++	printk("\n");
++	RTW_INFO("<====== DBG MSG FOR CONSTRAUCT ProvisionDis Rsp\n");
++#endif
++}
++
++u8 rtw_hal_set_FwP2PRsvdPage_cmd(_adapter *adapter, PRSVDPAGE_LOC rsvdpageloc)
++{
++	u8 u1H2CP2PRsvdPageParm[H2C_P2PRSVDPAGE_LOC_LEN] = {0};
++	struct hal_ops *pHalFunc = &adapter->hal_func;
++	u8 ret = _FAIL;
++
++	RTW_INFO("P2PRsvdPageLoc: P2PBeacon=%d P2PProbeRsp=%d NegoRsp=%d InviteRsp=%d PDRsp=%d\n",
++		 rsvdpageloc->LocP2PBeacon, rsvdpageloc->LocP2PProbeRsp,
++		 rsvdpageloc->LocNegoRsp, rsvdpageloc->LocInviteRsp,
++		 rsvdpageloc->LocPDRsp);
++
++	SET_H2CCMD_RSVDPAGE_LOC_P2P_BCN(u1H2CP2PRsvdPageParm, rsvdpageloc->LocProbeRsp);
++	SET_H2CCMD_RSVDPAGE_LOC_P2P_PROBE_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocPsPoll);
++	SET_H2CCMD_RSVDPAGE_LOC_P2P_NEGO_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocNullData);
++	SET_H2CCMD_RSVDPAGE_LOC_P2P_INVITE_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocQosNull);
++	SET_H2CCMD_RSVDPAGE_LOC_P2P_PD_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocBTQosNull);
++
++	/* FillH2CCmd8723B(padapter, H2C_8723B_P2P_OFFLOAD_RSVD_PAGE, H2C_P2PRSVDPAGE_LOC_LEN, u1H2CP2PRsvdPageParm); */
++	ret = rtw_hal_fill_h2c_cmd(adapter,
++				   H2C_P2P_OFFLOAD_RSVD_PAGE,
++				   H2C_P2PRSVDPAGE_LOC_LEN,
++				   u1H2CP2PRsvdPageParm);
++
++	return ret;
++}
++
++u8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter *adapter)
++{
++
++	u8 offload_cmd[H2C_P2P_OFFLOAD_LEN] = {0};
++	struct wifidirect_info	*pwdinfo = &(adapter->wdinfo);
++	struct P2P_WoWlan_Offload_t *p2p_wowlan_offload = (struct P2P_WoWlan_Offload_t *)offload_cmd;
++	struct hal_ops *pHalFunc = &adapter->hal_func;
++	u8 ret = _FAIL;
++
++	_rtw_memset(p2p_wowlan_offload, 0 , sizeof(struct P2P_WoWlan_Offload_t));
++	RTW_INFO("%s\n", __func__);
++	switch (pwdinfo->role) {
++	case P2P_ROLE_DEVICE:
++		RTW_INFO("P2P_ROLE_DEVICE\n");
++		p2p_wowlan_offload->role = 0;
++		break;
++	case P2P_ROLE_CLIENT:
++		RTW_INFO("P2P_ROLE_CLIENT\n");
++		p2p_wowlan_offload->role = 1;
++		break;
++	case P2P_ROLE_GO:
++		RTW_INFO("P2P_ROLE_GO\n");
++		p2p_wowlan_offload->role = 2;
++		break;
++	default:
++		RTW_INFO("P2P_ROLE_DISABLE\n");
++		break;
++	}
++	p2p_wowlan_offload->Wps_Config[0] = pwdinfo->supported_wps_cm >> 8;
++	p2p_wowlan_offload->Wps_Config[1] = pwdinfo->supported_wps_cm;
++	offload_cmd = (u8 *)p2p_wowlan_offload;
++	RTW_INFO("p2p_wowlan_offload: %x:%x:%x\n", offload_cmd[0], offload_cmd[1], offload_cmd[2]);
++
++	ret = rtw_hal_fill_h2c_cmd(adapter,
++				   H2C_P2P_OFFLOAD,
++				   H2C_P2P_OFFLOAD_LEN,
++				   offload_cmd);
++	return ret;
++
++	/* FillH2CCmd8723B(adapter, H2C_8723B_P2P_OFFLOAD, sizeof(struct P2P_WoWlan_Offload_t), (u8 *)p2p_wowlan_offload); */
++}
++#endif /* CONFIG_P2P_WOWLAN */
++
++void rtw_hal_construct_beacon(_adapter *padapter,
++				     u8 *pframe, u32 *pLength)
++{
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	u16					*fctrl;
++	u32					pktlen;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
++	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++
++
++	/* RTW_INFO("%s\n", __FUNCTION__); */
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
++	/* pmlmeext->mgnt_seq++; */
++	set_frame_sub_type(pframe, WIFI_BEACON);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	/* timestamp will be inserted by hardware */
++	pframe += 8;
++	pktlen += 8;
++
++	/* beacon interval: 2 bytes */
++	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
++
++	pframe += 2;
++	pktlen += 2;
++
++#if 0
++	/* capability info: 2 bytes */
++	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
++
++	pframe += 2;
++	pktlen += 2;
++
++	if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
++		/* RTW_INFO("ie len=%d\n", cur_network->IELength); */
++		pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs);
++		_rtw_memcpy(pframe, cur_network->IEs + sizeof(NDIS_802_11_FIXED_IEs), pktlen);
++
++		goto _ConstructBeacon;
++	}
++
++	/* below for ad-hoc mode */
++
++	/* SSID */
++	pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen);
++
++	/* supported rates... */
++	rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
++	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen);
++
++	/* DS parameter set */
++	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen);
++
++	if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
++		u32 ATIMWindow;
++		/* IBSS Parameter Set... */
++		/* ATIMWindow = cur->Configuration.ATIMWindow; */
++		ATIMWindow = 0;
++		pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen);
++	}
++
++
++	/* todo: ERP IE */
++
++
++	/* EXTERNDED SUPPORTED RATE */
++	if (rate_len > 8)
++		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen);
++
++	/* todo:HT for adhoc */
++
++_ConstructBeacon:
++#endif
++
++	if ((pktlen + TXDESC_SIZE) > MAX_BEACON_LEN) {
++		RTW_ERR("beacon frame too large ,len(%d,%d)\n",
++			(pktlen + TXDESC_SIZE), MAX_BEACON_LEN);
++		rtw_warn_on(1);
++		return;
++	}
++
++	*pLength = pktlen;
++
++	/* RTW_INFO("%s bcn_sz=%d\n", __FUNCTION__, pktlen); */
++
++}
++
++static void rtw_hal_construct_PSPoll(_adapter *padapter,
++				     u8 *pframe, u32 *pLength)
++{
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	u16					*fctrl;
++	u32					pktlen;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	/* RTW_INFO("%s\n", __FUNCTION__); */
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	/* Frame control. */
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++	SetPwrMgt(fctrl);
++	set_frame_sub_type(pframe, WIFI_PSPOLL);
++
++	/* AID. */
++	set_duration(pframe, (pmlmeinfo->aid | 0xc000));
++
++	/* BSSID. */
++	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++	/* TA. */
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++
++	*pLength = 16;
++}
++
++
++#ifdef DBG_FW_DEBUG_MSG_PKT
++void rtw_hal_construct_fw_dbg_msg_pkt(
++	PADAPTER padapter,
++	u8		*pframe,
++	u32		*plength)
++{
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	u16						*fctrl;
++	u32						pktlen;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct wlan_network		*cur_network = &pmlmepriv->cur_network;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++
++
++	/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &pwlanhdr->frame_ctl;
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, 0);
++
++	set_frame_sub_type(pframe, WIFI_DATA);
++
++	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	*plength = pktlen;
++}
++#endif /*DBG_FW_DEBUG_MSG_PKT*/
++
++void rtw_hal_construct_NullFunctionData(
++	PADAPTER padapter,
++	u8		*pframe,
++	u32		*pLength,
++	u8		bQoS,
++	u8		AC,
++	u8		bEosp,
++	u8		bForcePowerSave)
++{
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	u16						*fctrl;
++	u32						pktlen;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	struct wlan_network		*cur_network = &pmlmepriv->cur_network;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8 *sta_addr = NULL;
++	u8 bssid[ETH_ALEN] = {0};
++
++	/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &pwlanhdr->frame_ctl;
++	*(fctrl) = 0;
++	if (bForcePowerSave)
++		SetPwrMgt(fctrl);
++
++	sta_addr = get_my_bssid(&pmlmeinfo->network);
++	if (NULL == sta_addr) {
++		_rtw_memcpy(bssid, adapter_mac_addr(padapter), ETH_ALEN);
++		sta_addr = bssid;
++	}
++
++	switch (cur_network->network.InfrastructureMode) {
++	case Ndis802_11Infrastructure:
++		SetToDs(fctrl);
++		_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr3, sta_addr, ETH_ALEN);
++		break;
++	case Ndis802_11APMode:
++		SetFrDs(fctrl);
++		_rtw_memcpy(pwlanhdr->addr1, sta_addr, ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
++		break;
++	case Ndis802_11IBSS:
++	default:
++		_rtw_memcpy(pwlanhdr->addr1, sta_addr, ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++		_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++		break;
++	}
++
++	SetSeqNum(pwlanhdr, 0);
++	set_duration(pwlanhdr, 0);
++
++	if (bQoS == _TRUE) {
++		struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr;
++
++		set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL);
++
++		pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe;
++		SetPriority(&pwlanqoshdr->qc, AC);
++		SetEOSP(&pwlanqoshdr->qc, bEosp);
++
++		pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos);
++	} else {
++		set_frame_sub_type(pframe, WIFI_DATA_NULL);
++
++		pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++	}
++
++	*pLength = pktlen;
++}
++
++void rtw_hal_construct_ProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength,
++				BOOLEAN bHideSSID)
++{
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	u16					*fctrl;
++	u8					*mac, *bssid, *sta_addr;
++	u32					pktlen;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX  *cur_network = &(pmlmeinfo->network);
++
++	/*RTW_INFO("%s\n", __FUNCTION__);*/
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	mac = adapter_mac_addr(padapter);
++	bssid = cur_network->MacAddress;
++	sta_addr = get_my_bssid(&pmlmeinfo->network);
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++	_rtw_memcpy(pwlanhdr->addr1, sta_addr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, 0);
++	set_frame_sub_type(fctrl, WIFI_PROBERSP);
++
++	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++	pframe += pktlen;
++
++	if (cur_network->IELength > MAX_IE_SZ)
++		return;
++
++	_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
++	pframe += cur_network->IELength;
++	pktlen += cur_network->IELength;
++
++	*pLength = pktlen;
++}
++
++#ifdef CONFIG_WOWLAN
++static void rtw_hal_append_tkip_mic(PADAPTER padapter,
++				    u8 *pframe, u32 offset)
++{
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	struct mic_data	micdata;
++	struct sta_info	*psta = NULL;
++	int res = 0;
++
++	u8	*payload = (u8 *)(pframe + offset);
++
++	u8	mic[8];
++	u8	priority[4] = {0x0};
++	u8	null_key[16] = {0x0};
++
++	RTW_INFO("%s(): Add MIC, offset: %d\n", __func__, offset);
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	psta = rtw_get_stainfo(&padapter->stapriv,
++			get_my_bssid(&(pmlmeinfo->network)));
++	if (psta != NULL) {
++		res = _rtw_memcmp(&psta->dot11tkiptxmickey.skey[0],
++				  null_key, 16);
++		if (res == _TRUE)
++			RTW_INFO("%s(): STA dot11tkiptxmickey==0\n", __func__);
++		rtw_secmicsetkey(&micdata, &psta->dot11tkiptxmickey.skey[0]);
++	}
++
++	rtw_secmicappend(&micdata, pwlanhdr->addr3, 6);  /* DA */
++
++	rtw_secmicappend(&micdata, pwlanhdr->addr2, 6); /* SA */
++
++	priority[0] = 0;
++
++	rtw_secmicappend(&micdata, &priority[0], 4);
++
++	rtw_secmicappend(&micdata, payload, 36); /* payload length = 8 + 28 */
++
++	rtw_secgetmic(&micdata, &(mic[0]));
++
++	payload += 36;
++
++	_rtw_memcpy(payload, &(mic[0]), 8);
++}
++/*
++ * Description:
++ *	Construct the ARP response packet to support ARP offload.
++ *   */
++static void rtw_hal_construct_ARPRsp(
++	PADAPTER padapter,
++	u8			*pframe,
++	u32			*pLength,
++	u8			*pIPAddress
++)
++{
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	u16	*fctrl;
++	u32	pktlen;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct security_priv	*psecuritypriv = &padapter->securitypriv;
++	static u8	ARPLLCHeader[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x08, 0x06};
++	u8	*pARPRspPkt = pframe;
++	/* for TKIP Cal MIC */
++	u8	*payload = pframe;
++	u8	EncryptionHeadOverhead = 0, arp_offset = 0;
++	/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &pwlanhdr->frame_ctl;
++	*(fctrl) = 0;
++
++	/* ------------------------------------------------------------------------- */
++	/* MAC Header. */
++	/* ------------------------------------------------------------------------- */
++	SetFrameType(fctrl, WIFI_DATA);
++	/* set_frame_sub_type(fctrl, 0); */
++	SetToDs(fctrl);
++	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, 0);
++	set_duration(pwlanhdr, 0);
++	/* SET_80211_HDR_FRAME_CONTROL(pARPRspPkt, 0); */
++	/* SET_80211_HDR_TYPE_AND_SUBTYPE(pARPRspPkt, Type_Data); */
++	/* SET_80211_HDR_TO_DS(pARPRspPkt, 1); */
++	/* SET_80211_HDR_ADDRESS1(pARPRspPkt, pMgntInfo->Bssid); */
++	/* SET_80211_HDR_ADDRESS2(pARPRspPkt, Adapter->CurrentAddress); */
++	/* SET_80211_HDR_ADDRESS3(pARPRspPkt, pMgntInfo->Bssid); */
++
++	/* SET_80211_HDR_DURATION(pARPRspPkt, 0); */
++	/* SET_80211_HDR_FRAGMENT_SEQUENCE(pARPRspPkt, 0); */
++#ifdef CONFIG_WAPI_SUPPORT
++	*pLength = sMacHdrLng;
++#else
++	*pLength = 24;
++#endif
++	switch (psecuritypriv->dot11PrivacyAlgrthm) {
++	case _WEP40_:
++	case _WEP104_:
++		EncryptionHeadOverhead = 4;
++		break;
++	case _TKIP_:
++		EncryptionHeadOverhead = 8;
++		break;
++	case _AES_:
++		EncryptionHeadOverhead = 8;
++		break;
++#ifdef CONFIG_WAPI_SUPPORT
++	case _SMS4_:
++		EncryptionHeadOverhead = 18;
++		break;
++#endif
++	default:
++		EncryptionHeadOverhead = 0;
++	}
++
++	if (EncryptionHeadOverhead > 0) {
++		_rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);
++		*pLength += EncryptionHeadOverhead;
++		/* SET_80211_HDR_WEP(pARPRspPkt, 1);  */ /* Suggested by CCW. */
++		SetPrivacy(fctrl);
++	}
++
++	/* ------------------------------------------------------------------------- */
++	/* Frame Body. */
++	/* ------------------------------------------------------------------------- */
++	arp_offset = *pLength;
++	pARPRspPkt = (u8 *)(pframe + arp_offset);
++	payload = pARPRspPkt; /* Get Payload pointer */
++	/* LLC header */
++	_rtw_memcpy(pARPRspPkt, ARPLLCHeader, 8);
++	*pLength += 8;
++
++	/* ARP element */
++	pARPRspPkt += 8;
++	SET_ARP_HTYPE(pARPRspPkt, 1);
++	SET_ARP_PTYPE(pARPRspPkt, ETH_P_IP);	/* IP protocol */
++	SET_ARP_HLEN(pARPRspPkt, ETH_ALEN);
++	SET_ARP_PLEN(pARPRspPkt, RTW_IP_ADDR_LEN);
++	SET_ARP_OPER(pARPRspPkt, 2);	/* ARP response */
++	SET_ARP_SENDER_MAC_ADDR(pARPRspPkt, adapter_mac_addr(padapter));
++	SET_ARP_SENDER_IP_ADDR(pARPRspPkt, pIPAddress);
++#ifdef CONFIG_ARP_KEEP_ALIVE
++	if (!is_zero_mac_addr(pmlmepriv->gw_mac_addr)) {
++		SET_ARP_TARGET_MAC_ADDR(pARPRspPkt, pmlmepriv->gw_mac_addr);
++		SET_ARP_TARGET_IP_ADDR(pARPRspPkt, pmlmepriv->gw_ip);
++	} else
++#endif
++	{
++		SET_ARP_TARGET_MAC_ADDR(pARPRspPkt,
++				    get_my_bssid(&(pmlmeinfo->network)));
++		SET_ARP_TARGET_IP_ADDR(pARPRspPkt,
++					   pIPAddress);
++		RTW_INFO("%s Target Mac Addr:" MAC_FMT "\n", __FUNCTION__,
++			 MAC_ARG(get_my_bssid(&(pmlmeinfo->network))));
++		RTW_INFO("%s Target IP Addr" IP_FMT "\n", __FUNCTION__,
++			 IP_ARG(pIPAddress));
++	}
++
++	*pLength += 28;
++
++	if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {
++		if (IS_HARDWARE_TYPE_8188E(padapter) ||
++		    IS_HARDWARE_TYPE_8812(padapter)) {
++			rtw_hal_append_tkip_mic(padapter, pframe, arp_offset);
++		}
++		*pLength += 8;
++	}
++}
++
++#ifdef CONFIG_IPV6
++/*
++ * Description: Neighbor Discovery Offload.
++ */
++static void rtw_hal_construct_na_message(_adapter *padapter,
++				     u8 *pframe, u32 *pLength)
++{
++	struct rtw_ieee80211_hdr *pwlanhdr = NULL;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &pmlmeext->mlmext_info;
++	struct security_priv	*psecuritypriv = &padapter->securitypriv;
++
++	u32 pktlen = 0;
++	u16 *fctrl = NULL;
++
++	u8 ns_hdr[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x86, 0xDD};
++	u8 ipv6_info[4] = {0x60, 0x00, 0x00, 0x00};
++	u8 ipv6_contx[4] = {0x00, 0x20, 0x3a, 0xff};
++	u8 icmpv6_hdr[8] = {0x88, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00};
++	u8 val8 = 0;
++
++	u8 *p_na_msg = pframe;
++	/* for TKIP Cal MIC */
++	u8 *payload = pframe;
++	u8 EncryptionHeadOverhead = 0, na_msg_offset = 0;
++	/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &pwlanhdr->frame_ctl;
++	*(fctrl) = 0;
++
++	/* ------------------------------------------------------------------------- */
++	/* MAC Header. */
++	/* ------------------------------------------------------------------------- */
++	SetFrameType(fctrl, WIFI_DATA);
++	SetToDs(fctrl);
++	_rtw_memcpy(pwlanhdr->addr1,
++		    get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2,
++		    adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3,
++		    get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, 0);
++	set_duration(pwlanhdr, 0);
++
++#ifdef CONFIG_WAPI_SUPPORT
++	*pLength = sMacHdrLng;
++#else
++	*pLength = 24;
++#endif
++	switch (psecuritypriv->dot11PrivacyAlgrthm) {
++	case _WEP40_:
++	case _WEP104_:
++		EncryptionHeadOverhead = 4;
++		break;
++	case _TKIP_:
++		EncryptionHeadOverhead = 8;
++		break;
++	case _AES_:
++		EncryptionHeadOverhead = 8;
++		break;
++#ifdef CONFIG_WAPI_SUPPORT
++	case _SMS4_:
++		EncryptionHeadOverhead = 18;
++		break;
++#endif
++	default:
++		EncryptionHeadOverhead = 0;
++	}
++
++	if (EncryptionHeadOverhead > 0) {
++		_rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);
++		*pLength += EncryptionHeadOverhead;
++		/* SET_80211_HDR_WEP(pARPRspPkt, 1);  */ /* Suggested by CCW. */
++		SetPrivacy(fctrl);
++	}
++
++	/* ------------------------------------------------------------------------- */
++	/* Frame Body. */
++	/* ------------------------------------------------------------------------- */
++	na_msg_offset = *pLength;
++	p_na_msg = (u8 *)(pframe + na_msg_offset);
++	payload = p_na_msg; /* Get Payload pointer */
++
++	/* LLC header */
++	val8 = sizeof(ns_hdr);
++	_rtw_memcpy(p_na_msg, ns_hdr, val8);
++	*pLength += val8;
++	p_na_msg += val8;
++
++	/* IPv6 Header */
++	/* 1 . Information (4 bytes): 0x60 0x00 0x00 0x00 */
++	val8 = sizeof(ipv6_info);
++	_rtw_memcpy(p_na_msg, ipv6_info, val8);
++	*pLength += val8;
++	p_na_msg += val8;
++
++	/* 2 . playload : 0x00 0x20 , NextProt : 0x3a (ICMPv6) HopLim : 0xff */
++	val8 = sizeof(ipv6_contx);
++	_rtw_memcpy(p_na_msg, ipv6_contx, val8);
++	*pLength += val8;
++	p_na_msg += val8;
++
++	/* 3 . SA : 16 bytes , DA : 16 bytes ( Fw will filled ) */
++	_rtw_memset(&(p_na_msg[*pLength]), 0, 32);
++	*pLength += 32;
++	p_na_msg += 32;
++
++	/* ICMPv6 */
++	/* 1. Type : 0x88 (NA)
++	 * 2. Code : 0x00
++	 * 3. ChechSum : 0x00 0x00 (RSvd)
++	 * 4. NAFlag: 0x60 0x00 0x00 0x00 ( Solicited , Override)
++	 */
++	val8 = sizeof(icmpv6_hdr);
++	_rtw_memcpy(p_na_msg, icmpv6_hdr, val8);
++	*pLength += val8;
++	p_na_msg += val8;
++
++	/* TA: 16 bytes*/
++	_rtw_memset(&(p_na_msg[*pLength]), 0, 16);
++	*pLength += 16;
++	p_na_msg += 16;
++
++	/* ICMPv6 Target Link Layer Address */
++	p_na_msg[0] = 0x02; /* type */
++	p_na_msg[1] = 0x01; /* len 1 unit of 8 octes */
++	*pLength += 2;
++	p_na_msg += 2;
++
++	_rtw_memset(&(p_na_msg[*pLength]), 0, 6);
++	*pLength += 6;
++	p_na_msg += 6;
++
++	if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {
++		if (IS_HARDWARE_TYPE_8188E(padapter) ||
++		    IS_HARDWARE_TYPE_8812(padapter)) {
++			rtw_hal_append_tkip_mic(padapter, pframe,
++						na_msg_offset);
++		}
++		*pLength += 8;
++	}
++}
++/*
++ * Description: Neighbor Discovery Protocol Information.
++ */
++static void rtw_hal_construct_ndp_info(_adapter *padapter,
++				     u8 *pframe, u32 *pLength)
++{
++	struct mlme_ext_priv *pmlmeext = NULL;
++	struct mlme_ext_info *pmlmeinfo = NULL;
++	struct rtw_ndp_info ndp_info;
++	u8	*pndp_info = pframe;
++	u8	len = sizeof(struct rtw_ndp_info);
++
++	RTW_INFO("%s: len: %d\n", __func__, len);
++
++	pmlmeext =  &padapter->mlmeextpriv;
++	pmlmeinfo = &pmlmeext->mlmext_info;
++
++	_rtw_memset(pframe, 0, len);
++	_rtw_memset(&ndp_info, 0, len);
++
++	ndp_info.enable = 1;
++	ndp_info.check_remote_ip = 0;
++	ndp_info.num_of_target_ip = 1;
++
++	_rtw_memcpy(&ndp_info.target_link_addr, adapter_mac_addr(padapter),
++		    ETH_ALEN);
++	_rtw_memcpy(&ndp_info.target_ipv6_addr, pmlmeinfo->ip6_addr,
++		    RTW_IPv6_ADDR_LEN);
++
++	_rtw_memcpy(pndp_info, &ndp_info, len);
++}
++#endif /* CONFIG_IPV6 */
++
++#ifdef CONFIG_PNO_SUPPORT
++static void rtw_hal_construct_ProbeReq(_adapter *padapter, u8 *pframe,
++				       u32 *pLength, pno_ssid_t *ssid)
++{
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	u16				*fctrl;
++	u32				pktlen;
++	unsigned char			*mac;
++	unsigned char			bssrate[NumRates];
++	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	int	bssrate_len = 0;
++	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++	mac = adapter_mac_addr(padapter);
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN);
++
++	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, 0);
++	set_frame_sub_type(pframe, WIFI_PROBEREQ);
++
++	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++	pframe += pktlen;
++
++	if (ssid == NULL)
++		pframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &pktlen);
++	else {
++		/* RTW_INFO("%s len:%d\n", ssid->SSID, ssid->SSID_len); */
++		pframe = rtw_set_ie(pframe, _SSID_IE_, ssid->SSID_len, ssid->SSID, &pktlen);
++	}
++
++	get_rate_set(padapter, bssrate, &bssrate_len);
++
++	if (bssrate_len > 8) {
++		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &pktlen);
++		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &pktlen);
++	} else
++		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &pktlen);
++
++	*pLength = pktlen;
++}
++
++static void rtw_hal_construct_PNO_info(_adapter *padapter,
++				       u8 *pframe, u32 *pLength)
++{
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
++	int i;
++
++	u8	*pPnoInfoPkt = pframe;
++	pPnoInfoPkt = (u8 *)(pframe + *pLength);
++	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_num, 1);
++
++	pPnoInfoPkt += 1;
++	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->hidden_ssid_num, 1);
++
++	pPnoInfoPkt += 3;
++	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->fast_scan_period, 1);
++
++	pPnoInfoPkt += 4;
++	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->fast_scan_iterations, 4);
++
++	pPnoInfoPkt += 4;
++	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->slow_scan_period, 4);
++
++	pPnoInfoPkt += 4;
++	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_length, MAX_PNO_LIST_COUNT);
++
++	pPnoInfoPkt += MAX_PNO_LIST_COUNT;
++	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_cipher_info, MAX_PNO_LIST_COUNT);
++
++	pPnoInfoPkt += MAX_PNO_LIST_COUNT;
++	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_channel_info, MAX_PNO_LIST_COUNT);
++
++	pPnoInfoPkt += MAX_PNO_LIST_COUNT;
++	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->loc_probe_req, MAX_HIDDEN_AP);
++
++	pPnoInfoPkt += MAX_HIDDEN_AP;
++
++	/*
++	SSID is located at 128th Byte in NLO info Page
++	*/
++
++	*pLength += 128;
++	pPnoInfoPkt = pframe + 128;
++
++	for (i = 0; i < pwrctl->pnlo_info->ssid_num ; i++) {
++		_rtw_memcpy(pPnoInfoPkt, &pwrctl->pno_ssid_list->node[i].SSID,
++			    pwrctl->pnlo_info->ssid_length[i]);
++		*pLength += WLAN_SSID_MAXLEN;
++		pPnoInfoPkt += WLAN_SSID_MAXLEN;
++	}
++}
++
++static void rtw_hal_construct_ssid_list(_adapter *padapter,
++					u8 *pframe, u32 *pLength)
++{
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
++	u8 *pSSIDListPkt = pframe;
++	int i;
++
++	pSSIDListPkt = (u8 *)(pframe + *pLength);
++
++	for (i = 0; i < pwrctl->pnlo_info->ssid_num ; i++) {
++		_rtw_memcpy(pSSIDListPkt, &pwrctl->pno_ssid_list->node[i].SSID,
++			    pwrctl->pnlo_info->ssid_length[i]);
++
++		*pLength += WLAN_SSID_MAXLEN;
++		pSSIDListPkt += WLAN_SSID_MAXLEN;
++	}
++}
++
++static void rtw_hal_construct_scan_info(_adapter *padapter,
++					u8 *pframe, u32 *pLength)
++{
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
++	u8 *pScanInfoPkt = pframe;
++	int i;
++
++	pScanInfoPkt = (u8 *)(pframe + *pLength);
++
++	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->channel_num, 1);
++
++	*pLength += 1;
++	pScanInfoPkt += 1;
++	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_ch, 1);
++
++
++	*pLength += 1;
++	pScanInfoPkt += 1;
++	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_bw, 1);
++
++
++	*pLength += 1;
++	pScanInfoPkt += 1;
++	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_40_offset, 1);
++
++	*pLength += 1;
++	pScanInfoPkt += 1;
++	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_80_offset, 1);
++
++	*pLength += 1;
++	pScanInfoPkt += 1;
++	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->periodScan, 1);
++
++	*pLength += 1;
++	pScanInfoPkt += 1;
++	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->period_scan_time, 1);
++
++	*pLength += 1;
++	pScanInfoPkt += 1;
++	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->enableRFE, 1);
++
++	*pLength += 1;
++	pScanInfoPkt += 1;
++	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->rfe_type, 8);
++
++	*pLength += 8;
++	pScanInfoPkt += 8;
++
++	for (i = 0 ; i < MAX_SCAN_LIST_COUNT ; i++) {
++		_rtw_memcpy(pScanInfoPkt,
++			    &pwrctl->pscan_info->ssid_channel_info[i], 4);
++		*pLength += 4;
++		pScanInfoPkt += 4;
++	}
++}
++#endif /* CONFIG_PNO_SUPPORT */
++
++#ifdef CONFIG_GTK_OL
++static void rtw_hal_construct_GTKRsp(
++	PADAPTER	padapter,
++	u8		*pframe,
++	u32		*pLength
++)
++{
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	u16	*fctrl;
++	u32	pktlen;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct wlan_network	*cur_network = &pmlmepriv->cur_network;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct security_priv	*psecuritypriv = &padapter->securitypriv;
++	static u8	LLCHeader[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x88, 0x8E};
++	static u8	GTKbody_a[11] = {0x01, 0x03, 0x00, 0x5F, 0x02, 0x03, 0x12, 0x00, 0x10, 0x42, 0x0B};
++	u8	*pGTKRspPkt = pframe;
++	u8	EncryptionHeadOverhead = 0;
++	/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &pwlanhdr->frame_ctl;
++	*(fctrl) = 0;
++
++	/* ------------------------------------------------------------------------- */
++	/* MAC Header. */
++	/* ------------------------------------------------------------------------- */
++	SetFrameType(fctrl, WIFI_DATA);
++	/* set_frame_sub_type(fctrl, 0); */
++	SetToDs(fctrl);
++
++	_rtw_memcpy(pwlanhdr->addr1,
++		    get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++	_rtw_memcpy(pwlanhdr->addr2,
++		    adapter_mac_addr(padapter), ETH_ALEN);
++
++	_rtw_memcpy(pwlanhdr->addr3,
++		    get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, 0);
++	set_duration(pwlanhdr, 0);
++
++#ifdef CONFIG_WAPI_SUPPORT
++	*pLength = sMacHdrLng;
++#else
++	*pLength = 24;
++#endif /* CONFIG_WAPI_SUPPORT */
++
++	/* ------------------------------------------------------------------------- */
++	/* Security Header: leave space for it if necessary. */
++	/* ------------------------------------------------------------------------- */
++	switch (psecuritypriv->dot11PrivacyAlgrthm) {
++	case _WEP40_:
++	case _WEP104_:
++		EncryptionHeadOverhead = 4;
++		break;
++	case _TKIP_:
++		EncryptionHeadOverhead = 8;
++		break;
++	case _AES_:
++		EncryptionHeadOverhead = 8;
++		break;
++#ifdef CONFIG_WAPI_SUPPORT
++	case _SMS4_:
++		EncryptionHeadOverhead = 18;
++		break;
++#endif /* CONFIG_WAPI_SUPPORT */
++	default:
++		EncryptionHeadOverhead = 0;
++	}
++
++	if (EncryptionHeadOverhead > 0) {
++		_rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);
++		*pLength += EncryptionHeadOverhead;
++		/* SET_80211_HDR_WEP(pGTKRspPkt, 1);  */ /* Suggested by CCW. */
++		/* GTK's privacy bit is done by FW */
++		/* SetPrivacy(fctrl); */
++	}
++	/* ------------------------------------------------------------------------- */
++	/* Frame Body. */
++	/* ------------------------------------------------------------------------- */
++	pGTKRspPkt = (u8 *)(pframe + *pLength);
++	/* LLC header */
++	_rtw_memcpy(pGTKRspPkt, LLCHeader, 8);
++	*pLength += 8;
++
++	/* GTK element */
++	pGTKRspPkt += 8;
++
++	/* GTK frame body after LLC, part 1 */
++	/* TKIP key_length = 32, AES key_length = 16 */
++	if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_)
++		GTKbody_a[8] = 0x20;
++
++	/* GTK frame body after LLC, part 1 */
++	_rtw_memcpy(pGTKRspPkt, GTKbody_a, 11);
++	*pLength += 11;
++	pGTKRspPkt += 11;
++	/* GTK frame body after LLC, part 2 */
++	_rtw_memset(&(pframe[*pLength]), 0, 88);
++	*pLength += 88;
++	pGTKRspPkt += 88;
++
++	if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_)
++		*pLength += 8;
++}
++#endif /* CONFIG_GTK_OL */
++
++#define PN_2_CCMPH(ch,key_id)	((ch) & 0x000000000000ffff) \
++				| (((ch) & 0x0000ffffffff0000) << 16) \
++				| (((key_id) << 30)) \
++				| BIT(29)
++static void rtw_hal_construct_remote_control_info(_adapter *adapter,
++						  u8 *pframe, u32 *pLength)
++{
++	struct mlme_priv   *pmlmepriv = &adapter->mlmepriv;
++	struct sta_priv *pstapriv = &adapter->stapriv;
++	struct security_priv *psecuritypriv = &adapter->securitypriv;
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
++	struct sta_info *psta;
++	struct stainfo_rxcache *prxcache;
++	u8 cur_dot11rxiv[8], id = 0, tid_id = 0, i = 0;
++	size_t sz = 0, total = 0;
++	u64 ccmp_hdr = 0, tmp_key = 0;
++
++	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
++
++	if (psta == NULL) {
++		rtw_warn_on(1);
++		return;
++	}
++
++	prxcache = &psta->sta_recvpriv.rxcache;
++	sz = sizeof(cur_dot11rxiv);
++
++	/* 3 SEC IV * 1 page */
++	rtw_get_sec_iv(adapter, cur_dot11rxiv,
++		       get_my_bssid(&pmlmeinfo->network));
++
++	_rtw_memcpy(pframe, cur_dot11rxiv, sz);
++	*pLength += sz;
++	pframe += sz;
++
++	_rtw_memset(&cur_dot11rxiv, 0, sz);
++
++	if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) {
++		id = psecuritypriv->dot118021XGrpKeyid;
++		tid_id = prxcache->last_tid;
++		REMOTE_INFO_CTRL_SET_VALD_EN(cur_dot11rxiv, 0xdd);
++		REMOTE_INFO_CTRL_SET_PTK_EN(cur_dot11rxiv, 1);
++		REMOTE_INFO_CTRL_SET_GTK_EN(cur_dot11rxiv, 1);
++		REMOTE_INFO_CTRL_SET_GTK_IDX(cur_dot11rxiv, id);
++		_rtw_memcpy(pframe, cur_dot11rxiv, sz);
++		*pLength += sz;
++		pframe += sz;
++
++		_rtw_memcpy(pframe, prxcache->iv[tid_id], sz);
++		*pLength += sz;
++		pframe += sz;
++
++		total = sizeof(psecuritypriv->iv_seq);
++		total /= sizeof(psecuritypriv->iv_seq[0]);
++
++		for (i = 0 ; i < total ; i ++) {
++			ccmp_hdr =
++				le64_to_cpu(*(u64*)psecuritypriv->iv_seq[i]);
++			_rtw_memset(&cur_dot11rxiv, 0, sz);
++			if (ccmp_hdr != 0) {
++				tmp_key = i;
++				ccmp_hdr = PN_2_CCMPH(ccmp_hdr, tmp_key);
++				*(u64*)cur_dot11rxiv = cpu_to_le64(ccmp_hdr);
++				_rtw_memcpy(pframe, cur_dot11rxiv, sz);
++			}
++			*pLength += sz;
++			pframe += sz;
++		}
++	}
++}
++
++void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
++		  u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len,
++				  RSVDPAGE_LOC *rsvd_page_loc)
++{
++	struct security_priv *psecuritypriv = &adapter->securitypriv;
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
++	struct mlme_ext_priv	*pmlmeext;
++	struct mlme_ext_info	*pmlmeinfo;
++	u32	ARPLength = 0, GTKLength = 0, PNOLength = 0, ScanInfoLength = 0;
++	u32 ProbeReqLength = 0, ns_len = 0, rc_len = 0;
++	u8 CurtPktPageNum = 0;
++
++#ifdef CONFIG_GTK_OL
++	struct sta_priv *pstapriv = &adapter->stapriv;
++	struct sta_info *psta;
++	struct security_priv *psecpriv = &adapter->securitypriv;
++	u8 kek[RTW_KEK_LEN];
++	u8 kck[RTW_KCK_LEN];
++#endif /* CONFIG_GTK_OL */
++#ifdef CONFIG_PNO_SUPPORT
++	int pno_index;
++	u8 ssid_num;
++#endif /* CONFIG_PNO_SUPPORT */
++
++	pmlmeext = &adapter->mlmeextpriv;
++	pmlmeinfo = &pmlmeext->mlmext_info;
++
++	if (pwrctl->wowlan_pno_enable == _FALSE) {
++		/* ARP RSP * 1 page */
++
++		rsvd_page_loc->LocArpRsp = *page_num;
++
++		RTW_INFO("LocArpRsp: %d\n", rsvd_page_loc->LocArpRsp);
++
++		rtw_hal_construct_ARPRsp(adapter, &pframe[index],
++					 &ARPLength, pmlmeinfo->ip_addr);
++
++		rtw_hal_fill_fake_txdesc(adapter,
++					 &pframe[index - tx_desc],
++					 ARPLength, _FALSE, _FALSE, _TRUE);
++
++		CurtPktPageNum = (u8)PageNum(tx_desc + ARPLength, page_size);
++
++		*page_num += CurtPktPageNum;
++
++		index += (CurtPktPageNum * page_size);
++		RSVD_PAGE_CFG("WOW-ARPRsp", CurtPktPageNum, *page_num, 0);
++
++#ifdef CONFIG_IPV6
++		/* 2 NS offload and NDP Info*/
++		if (pwrctl->wowlan_ns_offload_en == _TRUE) {
++			rsvd_page_loc->LocNbrAdv = *page_num;
++			RTW_INFO("LocNbrAdv: %d\n", rsvd_page_loc->LocNbrAdv);
++			rtw_hal_construct_na_message(adapter,
++						     &pframe[index], &ns_len);
++			rtw_hal_fill_fake_txdesc(adapter,
++						 &pframe[index - tx_desc],
++						 ns_len, _FALSE,
++						 _FALSE, _TRUE);
++			CurtPktPageNum = (u8)PageNum(tx_desc + ns_len,
++						      page_size);
++			*page_num += CurtPktPageNum;
++			index += (CurtPktPageNum * page_size);
++			RSVD_PAGE_CFG("WOW-NbrAdv", CurtPktPageNum, *page_num, 0);
++
++			rsvd_page_loc->LocNDPInfo = *page_num;
++			RTW_INFO("LocNDPInfo: %d\n",
++				 rsvd_page_loc->LocNDPInfo);
++
++			rtw_hal_construct_ndp_info(adapter,
++						   &pframe[index - tx_desc],
++						   &ns_len);
++			CurtPktPageNum =
++				(u8)PageNum(tx_desc + ns_len, page_size);
++			*page_num += CurtPktPageNum;
++			index += (CurtPktPageNum * page_size);
++			RSVD_PAGE_CFG("WOW-NDPInfo", CurtPktPageNum, *page_num, 0);
++
++		}
++#endif /*CONFIG_IPV6*/
++		/* 3 Remote Control Info. * 1 page */
++		rsvd_page_loc->LocRemoteCtrlInfo = *page_num;
++		RTW_INFO("LocRemoteCtrlInfo: %d\n", rsvd_page_loc->LocRemoteCtrlInfo);
++		rtw_hal_construct_remote_control_info(adapter,
++						      &pframe[index - tx_desc],
++						      &rc_len);
++		CurtPktPageNum = (u8)PageNum(rc_len, page_size);
++		*page_num += CurtPktPageNum;
++		*total_pkt_len = index + rc_len;
++		RSVD_PAGE_CFG("WOW-RCI", CurtPktPageNum, *page_num, *total_pkt_len);
++#ifdef CONFIG_GTK_OL
++		index += (CurtPktPageNum * page_size);
++
++		/* if the ap staion info. exists, get the kek, kck from staion info. */
++		psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
++		if (psta == NULL) {
++			_rtw_memset(kek, 0, RTW_KEK_LEN);
++			_rtw_memset(kck, 0, RTW_KCK_LEN);
++			RTW_INFO("%s, KEK, KCK download rsvd page all zero\n",
++				 __func__);
++		} else {
++			_rtw_memcpy(kek, psta->kek, RTW_KEK_LEN);
++			_rtw_memcpy(kck, psta->kck, RTW_KCK_LEN);
++		}
++
++		/* 3 KEK, KCK */
++		rsvd_page_loc->LocGTKInfo = *page_num;
++		RTW_INFO("LocGTKInfo: %d\n", rsvd_page_loc->LocGTKInfo);
++
++		if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8812(adapter)) {
++			struct security_priv *psecpriv = NULL;
++
++			psecpriv = &adapter->securitypriv;
++			_rtw_memcpy(pframe + index - tx_desc,
++				    &psecpriv->dot11PrivacyAlgrthm, 1);
++			_rtw_memcpy(pframe + index - tx_desc + 1,
++				    &psecpriv->dot118021XGrpPrivacy, 1);
++			_rtw_memcpy(pframe + index - tx_desc + 2,
++				    kck, RTW_KCK_LEN);
++			_rtw_memcpy(pframe + index - tx_desc + 2 + RTW_KCK_LEN,
++				    kek, RTW_KEK_LEN);
++			CurtPktPageNum = (u8)PageNum(tx_desc + 2 + RTW_KCK_LEN + RTW_KEK_LEN, page_size);
++		} else {
++
++			_rtw_memcpy(pframe + index - tx_desc, kck, RTW_KCK_LEN);
++			_rtw_memcpy(pframe + index - tx_desc + RTW_KCK_LEN,
++				    kek, RTW_KEK_LEN);
++			GTKLength = tx_desc + RTW_KCK_LEN + RTW_KEK_LEN;
++
++			if (psta != NULL &&
++				psecuritypriv->dot118021XGrpPrivacy == _TKIP_) {
++				_rtw_memcpy(pframe + index - tx_desc + 56,
++					&psta->dot11tkiptxmickey, RTW_TKIP_MIC_LEN);
++				GTKLength += RTW_TKIP_MIC_LEN;
++			}
++			CurtPktPageNum = (u8)PageNum(GTKLength, page_size);
++		}
++#if 0
++		{
++			int i;
++			printk("\ntoFW KCK: ");
++			for (i = 0; i < 16; i++)
++				printk(" %02x ", kck[i]);
++			printk("\ntoFW KEK: ");
++			for (i = 0; i < 16; i++)
++				printk(" %02x ", kek[i]);
++			printk("\n");
++		}
++
++		RTW_INFO("%s(): HW_VAR_SET_TX_CMD: KEK KCK %p %d\n",
++			 __FUNCTION__, &pframe[index - tx_desc],
++			 (tx_desc + RTW_KCK_LEN + RTW_KEK_LEN));
++#endif
++
++		*page_num += CurtPktPageNum;
++
++		index += (CurtPktPageNum * page_size);
++		RSVD_PAGE_CFG("WOW-GTKInfo", CurtPktPageNum, *page_num, 0);
++
++		/* 3 GTK Response */
++		rsvd_page_loc->LocGTKRsp = *page_num;
++		RTW_INFO("LocGTKRsp: %d\n", rsvd_page_loc->LocGTKRsp);
++		rtw_hal_construct_GTKRsp(adapter, &pframe[index], &GTKLength);
++
++		rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
++					 GTKLength, _FALSE, _FALSE, _TRUE);
++#if 0
++		{
++			int gj;
++			printk("123GTK pkt=>\n");
++			for (gj = 0; gj < GTKLength + tx_desc; gj++) {
++				printk(" %02x ", pframe[index - tx_desc + gj]);
++				if ((gj + 1) % 16 == 0)
++					printk("\n");
++			}
++			printk(" <=end\n");
++		}
++
++		RTW_INFO("%s(): HW_VAR_SET_TX_CMD: GTK RSP %p %d\n",
++			 __FUNCTION__, &pframe[index - tx_desc],
++			 (tx_desc + GTKLength));
++#endif
++
++		CurtPktPageNum = (u8)PageNum(tx_desc + GTKLength, page_size);
++
++		*page_num += CurtPktPageNum;
++
++		index += (CurtPktPageNum * page_size);
++		RSVD_PAGE_CFG("WOW-GTKRsp", CurtPktPageNum, *page_num, 0);
++
++		/* below page is empty for GTK extension memory */
++		/* 3(11) GTK EXT MEM */
++		rsvd_page_loc->LocGTKEXTMEM = *page_num;
++		RTW_INFO("LocGTKEXTMEM: %d\n", rsvd_page_loc->LocGTKEXTMEM);
++		CurtPktPageNum = 2;
++
++		if (page_size >= 256)
++			CurtPktPageNum = 1;
++
++		*page_num += CurtPktPageNum;
++		/* extension memory for FW */
++		*total_pkt_len = index + (page_size * CurtPktPageNum);
++		RSVD_PAGE_CFG("WOW-GTKEXTMEM", CurtPktPageNum, *page_num, *total_pkt_len);
++#endif /* CONFIG_GTK_OL */
++
++		index += (CurtPktPageNum * page_size);
++
++		/*Reserve 1 page for AOAC report*/
++		rsvd_page_loc->LocAOACReport = *page_num;
++		RTW_INFO("LocAOACReport: %d\n", rsvd_page_loc->LocAOACReport);
++		*page_num += 1;
++		*total_pkt_len = index + (page_size * 1);
++		RSVD_PAGE_CFG("WOW-AOAC", 1, *page_num, *total_pkt_len);
++	} else {
++#ifdef CONFIG_PNO_SUPPORT
++		if (pwrctl->wowlan_in_resume == _FALSE &&
++		    pwrctl->pno_inited == _TRUE) {
++
++			/* Broadcast Probe Request */
++			rsvd_page_loc->LocProbePacket = *page_num;
++
++			RTW_INFO("loc_probe_req: %d\n",
++				 rsvd_page_loc->LocProbePacket);
++
++			rtw_hal_construct_ProbeReq(
++				adapter,
++				&pframe[index],
++				&ProbeReqLength,
++				NULL);
++
++			rtw_hal_fill_fake_txdesc(adapter,
++						 &pframe[index - tx_desc],
++				 ProbeReqLength, _FALSE, _FALSE, _FALSE);
++
++			CurtPktPageNum =
++				(u8)PageNum(tx_desc + ProbeReqLength, page_size);
++
++			*page_num += CurtPktPageNum;
++
++			index += (CurtPktPageNum * page_size);
++			RSVD_PAGE_CFG("WOW-ProbeReq", CurtPktPageNum, *page_num, 0);
++
++			/* Hidden SSID Probe Request */
++			ssid_num = pwrctl->pnlo_info->hidden_ssid_num;
++
++			for (pno_index = 0 ; pno_index < ssid_num ; pno_index++) {
++				pwrctl->pnlo_info->loc_probe_req[pno_index] =
++					*page_num;
++
++				rtw_hal_construct_ProbeReq(
++					adapter,
++					&pframe[index],
++					&ProbeReqLength,
++					&pwrctl->pno_ssid_list->node[pno_index]);
++
++				rtw_hal_fill_fake_txdesc(adapter,
++						 &pframe[index - tx_desc],
++					ProbeReqLength, _FALSE, _FALSE, _FALSE);
++
++				CurtPktPageNum =
++					(u8)PageNum(tx_desc + ProbeReqLength, page_size);
++
++				*page_num += CurtPktPageNum;
++
++				index += (CurtPktPageNum * page_size);
++				RSVD_PAGE_CFG("WOW-ProbeReq", CurtPktPageNum, *page_num, 0);
++			}
++
++			/* PNO INFO Page */
++			rsvd_page_loc->LocPNOInfo = *page_num;
++			RTW_INFO("LocPNOInfo: %d\n", rsvd_page_loc->LocPNOInfo);
++			rtw_hal_construct_PNO_info(adapter,
++						   &pframe[index - tx_desc],
++						   &PNOLength);
++
++			CurtPktPageNum = (u8)PageNum(PNOLength, page_size);
++			*page_num += CurtPktPageNum;
++			index += (CurtPktPageNum * page_size);
++			RSVD_PAGE_CFG("WOW-PNOInfo", CurtPktPageNum, *page_num, 0);
++
++			/* Scan Info Page */
++			rsvd_page_loc->LocScanInfo = *page_num;
++			RTW_INFO("LocScanInfo: %d\n", rsvd_page_loc->LocScanInfo);
++			rtw_hal_construct_scan_info(adapter,
++						    &pframe[index - tx_desc],
++						    &ScanInfoLength);
++
++			CurtPktPageNum = (u8)PageNum(ScanInfoLength, page_size);
++			*page_num += CurtPktPageNum;
++			*total_pkt_len = index + ScanInfoLength;
++			index += (CurtPktPageNum * page_size);
++			RSVD_PAGE_CFG("WOW-ScanInfo", CurtPktPageNum, *page_num, *total_pkt_len);
++		}
++#endif /* CONFIG_PNO_SUPPORT */
++	}
++}
++
++static void rtw_hal_gate_bb(_adapter *adapter, bool stop)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	u8 i = 0, val8 = 0, empty = _FAIL;
++
++	if (stop) {
++		/* checking TX queue status */
++		for (i = 0 ; i < 5 ; i++) {
++			rtw_hal_get_hwreg(adapter, HW_VAR_CHK_MGQ_CPU_EMPTY, &empty);
++			if (empty) {
++				break;
++			} else {
++				RTW_WARN("%s: MGQ_CPU is busy(%d)!\n",
++					 __func__, i);
++				rtw_mdelay_os(10);
++			}
++		}
++
++		if (val8 == 5)
++			RTW_ERR("%s: Polling MGQ_CPU empty fail!\n", __func__);
++
++		/* Pause TX*/
++		pwrpriv->wowlan_txpause_status = rtw_read8(adapter, REG_TXPAUSE);
++		rtw_write8(adapter, REG_TXPAUSE, 0xff);
++		val8 = rtw_read8(adapter, REG_SYS_FUNC_EN);
++		val8 &= ~BIT(0);
++		rtw_write8(adapter, REG_SYS_FUNC_EN, val8);
++		RTW_INFO("%s: BB gated: 0x%02x, store TXPAUSE: %02x\n",
++			 __func__,
++			 rtw_read8(adapter, REG_SYS_FUNC_EN),
++			 pwrpriv->wowlan_txpause_status);
++	} else {
++		val8 = rtw_read8(adapter, REG_SYS_FUNC_EN);
++		val8 |= BIT(0);
++		rtw_write8(adapter, REG_SYS_FUNC_EN, val8);
++		RTW_INFO("%s: BB release: 0x%02x, recover TXPAUSE:%02x\n",
++			 __func__, rtw_read8(adapter, REG_SYS_FUNC_EN),
++			 pwrpriv->wowlan_txpause_status);
++		/* release TX*/
++		rtw_write8(adapter, REG_TXPAUSE, pwrpriv->wowlan_txpause_status);
++	}
++}
++
++static u8 rtw_hal_wow_pattern_generate(_adapter *adapter, u8 idx, struct rtl_wow_pattern *pwow_pattern)
++{
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
++	 u8 *pattern;
++	 u8 len = 0;
++	 u8 *mask;
++
++	u8 mask_hw[MAX_WKFM_SIZE] = {0};
++	u8 content[MAX_WKFM_PATTERN_SIZE] = {0};
++	u8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	u8 multicast_addr1[2] = {0x33, 0x33};
++	u8 multicast_addr2[3] = {0x01, 0x00, 0x5e};
++	u8 mask_len = 0;
++	u8 mac_addr[ETH_ALEN] = {0};
++	u16 count = 0;
++	int i;
++
++	if (pwrctl->wowlan_pattern_idx > MAX_WKFM_CAM_NUM) {
++		RTW_INFO("%s pattern_idx is more than MAX_FMC_NUM: %d\n",
++			 __func__, MAX_WKFM_CAM_NUM);
++		return _FAIL;
++	}
++
++	pattern = pwrctl->patterns[idx].content;
++	len = pwrctl->patterns[idx].len;
++	mask = pwrctl->patterns[idx].mask;
++
++	_rtw_memcpy(mac_addr, adapter_mac_addr(adapter), ETH_ALEN);
++	_rtw_memset(pwow_pattern, 0, sizeof(struct rtl_wow_pattern));
++
++	mask_len = DIV_ROUND_UP(len, 8);
++
++	/* 1. setup A1 table */
++	if (memcmp(pattern, broadcast_addr, ETH_ALEN) == 0)
++		pwow_pattern->type = PATTERN_BROADCAST;
++	else if (memcmp(pattern, multicast_addr1, 2) == 0)
++		pwow_pattern->type = PATTERN_MULTICAST;
++	else if (memcmp(pattern, multicast_addr2, 3) == 0)
++		pwow_pattern->type = PATTERN_MULTICAST;
++	else if (memcmp(pattern, mac_addr, ETH_ALEN) == 0)
++		pwow_pattern->type = PATTERN_UNICAST;
++	else
++		pwow_pattern->type = PATTERN_INVALID;
++
++	/* translate mask from os to mask for hw */
++
++	/******************************************************************************
++	 * pattern from OS uses 'ethenet frame', like this:
++
++		|    6   |    6   |   2  |     20    |  Variable  |  4  |
++		|--------+--------+------+-----------+------------+-----|
++		|    802.3 Mac Header    | IP Header | TCP Packet | FCS |
++		|   DA   |   SA   | Type |
++
++	 * BUT, packet catched by our HW is in '802.11 frame', begin from LLC,
++
++		|     24 or 30      |    6   |   2  |     20    |  Variable  |  4  |
++		|-------------------+--------+------+-----------+------------+-----|
++		| 802.11 MAC Header |       LLC     | IP Header | TCP Packet | FCS |
++				    | Others | Tpye |
++
++	 * Therefore, we need translate mask_from_OS to mask_to_hw.
++	 * We should left-shift mask by 6 bits, then set the new bit[0~5] = 0,
++	 * because new mask[0~5] means 'SA', but our HW packet begins from LLC,
++	 * bit[0~5] corresponds to first 6 Bytes in LLC, they just don't match.
++	 ******************************************************************************/
++	/* Shift 6 bits */
++	for (i = 0; i < mask_len - 1; i++) {
++		mask_hw[i] = mask[i] >> 6;
++		mask_hw[i] |= (mask[i + 1] & 0x3F) << 2;
++	}
++
++	mask_hw[i] = (mask[i] >> 6) & 0x3F;
++	/* Set bit 0-5 to zero */
++	mask_hw[0] &= 0xC0;
++
++	for (i = 0; i < (MAX_WKFM_SIZE / 4); i++) {
++		pwow_pattern->mask[i] = mask_hw[i * 4];
++		pwow_pattern->mask[i] |= (mask_hw[i * 4 + 1] << 8);
++		pwow_pattern->mask[i] |= (mask_hw[i * 4 + 2] << 16);
++		pwow_pattern->mask[i] |= (mask_hw[i * 4 + 3] << 24);
++	}
++
++	/* To get the wake up pattern from the mask.
++	 * We do not count first 12 bits which means
++	 * DA[6] and SA[6] in the pattern to match HW design. */
++	count = 0;
++	for (i = 12; i < len; i++) {
++		if ((mask[i / 8] >> (i % 8)) & 0x01) {
++			content[count] = pattern[i];
++			count++;
++		}
++	}
++
++	pwow_pattern->crc = rtw_calc_crc(content, count);
++
++	if (pwow_pattern->crc != 0) {
++		if (pwow_pattern->type == PATTERN_INVALID)
++			pwow_pattern->type = PATTERN_VALID;
++	}
++
++	return _SUCCESS;
++}
++
++#ifndef CONFIG_WOW_PATTERN_HW_CAM
++static void rtw_hal_reset_mac_rx(_adapter *adapter)
++{
++	u8 val8 = 0;
++	/* Set REG_CR bit1, bit3, bit7 to 0*/
++	val8 = rtw_read8(adapter, REG_CR);
++	val8 &= 0x75;
++	rtw_write8(adapter, REG_CR, val8);
++	val8 = rtw_read8(adapter, REG_CR);
++	/* Set REG_CR bit1, bit3, bit7 to 1*/
++	val8 |= 0x8a;
++	rtw_write8(adapter, REG_CR, val8);
++	RTW_INFO("0x%04x: %02x\n", REG_CR, rtw_read8(adapter, REG_CR));
++}
++static void rtw_hal_set_wow_rxff_boundary(_adapter *adapter, bool wow_mode)
++{
++	u8 val8 = 0;
++	u16 rxff_bndy = 0;
++	u32 rx_dma_buff_sz = 0;
++
++	val8 = rtw_read8(adapter, REG_FIFOPAGE + 3);
++	if (val8 != 0)
++		RTW_INFO("%s:[%04x]some PKTs in TXPKTBUF\n",
++			 __func__, (REG_FIFOPAGE + 3));
++
++	rtw_hal_reset_mac_rx(adapter);
++
++	if (wow_mode) {
++		rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
++				    (u8 *)&rx_dma_buff_sz);
++		rxff_bndy = rx_dma_buff_sz - 1;
++
++		rtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
++		RTW_INFO("%s: wow mode, 0x%04x: 0x%04x\n", __func__,
++			 REG_TRXFF_BNDY + 2,
++			 rtw_read16(adapter, (REG_TRXFF_BNDY + 2)));
++	} else {
++		rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ,
++				    (u8 *)&rx_dma_buff_sz);
++		rxff_bndy = rx_dma_buff_sz - 1;
++		rtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
++		RTW_INFO("%s: normal mode, 0x%04x: 0x%04x\n", __func__,
++			 REG_TRXFF_BNDY + 2,
++			 rtw_read16(adapter, (REG_TRXFF_BNDY + 2)));
++	}
++}
++
++#ifndef CONFIG_WOW_PATTERN_IN_TXFIFO
++bool rtw_read_from_frame_mask(_adapter *adapter, u8 idx)
++{
++	u32 data_l = 0, data_h = 0, rx_dma_buff_sz = 0, page_sz = 0;
++	u16 offset, rx_buf_ptr = 0;
++	u16 cam_start_offset = 0;
++	u16 ctrl_l = 0, ctrl_h = 0;
++	u8 count = 0, tmp = 0;
++	int i = 0;
++	bool res = _TRUE;
++
++	if (idx > MAX_WKFM_CAM_NUM) {
++		RTW_INFO("[Error]: %s, pattern index is out of range\n",
++			 __func__);
++		return _FALSE;
++	}
++
++	rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
++			    (u8 *)&rx_dma_buff_sz);
++
++	if (rx_dma_buff_sz == 0) {
++		RTW_INFO("[Error]: %s, rx_dma_buff_sz is 0!!\n", __func__);
++		return _FALSE;
++	}
++
++	rtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz);
++
++	if (page_sz == 0) {
++		RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__);
++		return _FALSE;
++	}
++
++	offset = (u16)PageNum(rx_dma_buff_sz, page_sz);
++	cam_start_offset = offset * page_sz;
++
++	ctrl_l = 0x0;
++	ctrl_h = 0x0;
++
++	/* Enable RX packet buffer access */
++	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
++
++	/* Read the WKFM CAM */
++	for (i = 0; i < (WKFMCAM_ADDR_NUM / 2); i++) {
++		/*
++		 * Set Rx packet buffer offset.
++		 * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer.
++		 * CAM start offset (unit: 1 byte) =  Index*WKFMCAM_SIZE
++		 * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8
++		 * * Index: The index of the wake up frame mask
++		 * * WKFMCAM_SIZE: the total size of one WKFM CAM
++		 * * per entry offset of a WKFM CAM: Addr i * 4 bytes
++		 */
++		rx_buf_ptr =
++			(cam_start_offset + idx * WKFMCAM_SIZE + i * 8) >> 3;
++		rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr);
++
++		rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
++		data_l = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
++		data_h = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
++
++		RTW_INFO("[%d]: %08x %08x\n", i, data_h, data_l);
++
++		count = 0;
++
++		do {
++			tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL);
++			rtw_udelay_os(2);
++			count++;
++		} while (!tmp && count < 100);
++
++		if (count >= 100) {
++			RTW_INFO("%s count:%d\n", __func__, count);
++			res = _FALSE;
++		}
++	}
++
++	/* Disable RX packet buffer access */
++	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL,
++		   DISABLE_TRXPKT_BUF_ACCESS);
++	return res;
++}
++
++bool rtw_write_to_frame_mask(_adapter *adapter, u8 idx,
++			     struct  rtl_wow_pattern *context)
++{
++	u32 data = 0, rx_dma_buff_sz = 0, page_sz = 0;
++	u16 offset, rx_buf_ptr = 0;
++	u16 cam_start_offset = 0;
++	u16 ctrl_l = 0, ctrl_h = 0;
++	u8 count = 0, tmp = 0;
++	int res = 0, i = 0;
++
++	if (idx > MAX_WKFM_CAM_NUM) {
++		RTW_INFO("[Error]: %s, pattern index is out of range\n",
++			 __func__);
++		return _FALSE;
++	}
++
++	rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
++			    (u8 *)&rx_dma_buff_sz);
++
++	if (rx_dma_buff_sz == 0) {
++		RTW_INFO("[Error]: %s, rx_dma_buff_sz is 0!!\n", __func__);
++		return _FALSE;
++	}
++
++	rtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz);
++
++	if (page_sz == 0) {
++		RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__);
++		return _FALSE;
++	}
++
++	offset = (u16)PageNum(rx_dma_buff_sz, page_sz);
++
++	cam_start_offset = offset * page_sz;
++
++	if (IS_HARDWARE_TYPE_8188E(adapter)) {
++		ctrl_l = 0x0001;
++		ctrl_h = 0x0001;
++	} else {
++		ctrl_l = 0x0f01;
++		ctrl_h = 0xf001;
++	}
++
++	/* Enable RX packet buffer access */
++	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
++
++	/* Write the WKFM CAM */
++	for (i = 0; i < WKFMCAM_ADDR_NUM; i++) {
++		/*
++		 * Set Rx packet buffer offset.
++		 * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer.
++		 * CAM start offset (unit: 1 byte) =  Index*WKFMCAM_SIZE
++		 * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8
++		 * * Index: The index of the wake up frame mask
++		 * * WKFMCAM_SIZE: the total size of one WKFM CAM
++		 * * per entry offset of a WKFM CAM: Addr i * 4 bytes
++		 */
++		rx_buf_ptr =
++			(cam_start_offset + idx * WKFMCAM_SIZE + i * 4) >> 3;
++		rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr);
++
++		if (i == 0) {
++			if (context->type == PATTERN_VALID)
++				data = BIT(31);
++			else if (context->type == PATTERN_BROADCAST)
++				data = BIT(31) | BIT(26);
++			else if (context->type == PATTERN_MULTICAST)
++				data = BIT(31) | BIT(25);
++			else if (context->type == PATTERN_UNICAST)
++				data = BIT(31) | BIT(24);
++
++			if (context->crc != 0)
++				data |= context->crc;
++
++			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data);
++			rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
++		} else if (i == 1) {
++			data = 0;
++			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data);
++			rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h);
++		} else if (i == 2 || i == 4) {
++			data = context->mask[i - 2];
++			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data);
++			/* write to RX packet buffer*/
++			rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
++		} else if (i == 3 || i == 5) {
++			data = context->mask[i - 2];
++			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data);
++			/* write to RX packet buffer*/
++			rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h);
++		}
++
++		count = 0;
++		do {
++			tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL);
++			rtw_udelay_os(2);
++			count++;
++		} while (tmp && count < 100);
++
++		if (count >= 100)
++			res = _FALSE;
++		else
++			res = _TRUE;
++	}
++
++	/* Disable RX packet buffer access */
++	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL,
++		   DISABLE_TRXPKT_BUF_ACCESS);
++
++	return res;
++}
++#else /* CONFIG_WOW_PATTERN_IN_TXFIFO */
++bool rtw_read_from_frame_mask(_adapter *adapter, u8 idx)
++{
++	u32 data_l = 0, data_h = 0, rx_dma_buff_sz = 0, page_sz = 0;
++	u16 tx_page_start, tx_buf_ptr = 0;
++	u16 cam_start_offset = 0;
++	u16 ctrl_l = 0, ctrl_h = 0;
++	u8 count = 0, tmp = 0, last_entry = 0;
++	int i = 0;
++	bool res = _TRUE;
++
++	if (idx > MAX_WKFM_CAM_NUM) {
++		RTW_INFO("[Error]: %s, pattern index is out of range\n",
++			 __func__);
++		return _FALSE;
++	}
++
++	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&page_sz);
++	if (page_sz == 0) {
++		RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__);
++		return _FALSE;
++	}
++
++	rtw_hal_get_def_var(adapter, HAL_DEF_TX_BUFFER_LAST_ENTRY, (u8 *)&last_entry);
++	if (last_entry == 0) {
++		RTW_INFO("[Error]: %s, last entry of tx buffer is 0!!\n", __func__);
++		return _FALSE;
++	}
++
++	/* use the last 2 pages for wow pattern e.g. 0xfe and 0xff */
++	tx_page_start = last_entry - 1;
++	cam_start_offset = tx_page_start * page_sz / 8;
++	ctrl_l = 0x0;
++	ctrl_h = 0x0;
++
++	/* Enable TX packet buffer access */
++	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
++
++	/* Read the WKFM CAM */
++	for (i = 0; i < (WKFMCAM_ADDR_NUM / 2); i++) {
++		/*
++		 * Set Tx packet buffer offset.
++		 * TxBufer pointer increases 1, we can access 8 bytes in Tx packet buffer.
++		 * CAM start offset (unit: 1 byte) =  Index*WKFMCAM_SIZE
++		 * TxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8
++		 * * Index: The index of the wake up frame mask
++		 * * WKFMCAM_SIZE: the total size of one WKFM CAM
++		 * * per entry offset of a WKFM CAM: Addr i * 4 bytes
++		 */
++		tx_buf_ptr =
++			(cam_start_offset + idx * WKFMCAM_SIZE + i * 8) >> 3;
++		rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, tx_buf_ptr);
++		rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
++		data_l = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
++		data_h = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
++
++		RTW_INFO("[%d]: %08x %08x\n", i, data_h, data_l);
++
++		count = 0;
++
++		do {
++			tmp = rtw_read32(adapter, REG_PKTBUF_DBG_CTRL) & BIT23;
++			rtw_udelay_os(2);
++			count++;
++		} while (!tmp && count < 100);
++
++		if (count >= 100) {
++			RTW_INFO("%s count:%d\n", __func__, count);
++			res = _FALSE;
++		}
++	}
++
++	/* Disable RX packet buffer access */
++	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL,
++		   DISABLE_TRXPKT_BUF_ACCESS);
++	return res;
++}
++
++bool rtw_write_to_frame_mask(_adapter *adapter, u8 idx,
++			     struct  rtl_wow_pattern *context)
++{
++	u32 tx_page_start = 0, page_sz = 0;
++	u16 tx_buf_ptr = 0;
++	u16 cam_start_offset = 0;
++	u32 data_l = 0, data_h = 0;
++	u8 count = 0, tmp = 0, last_entry = 0;
++	int res = 0, i = 0;
++
++	if (idx > MAX_WKFM_CAM_NUM) {
++		RTW_INFO("[Error]: %s, pattern index is out of range\n",
++			 __func__);
++		return _FALSE;
++	}
++
++	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&page_sz);
++	if (page_sz == 0) {
++		RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__);
++		return _FALSE;
++	}
++
++	rtw_hal_get_def_var(adapter, HAL_DEF_TX_BUFFER_LAST_ENTRY, (u8 *)&last_entry);
++	if (last_entry == 0) {
++		RTW_INFO("[Error]: %s, last entry of tx buffer is 0!!\n", __func__);
++		return _FALSE;
++	}
++
++	/* use the last 2 pages for wow pattern e.g. 0xfe and 0xff */
++	tx_page_start = last_entry - 1;
++	cam_start_offset = tx_page_start * page_sz / 8;
++
++	/* Write the PATTERN location to BIT_TXBUF_WKCAM_OFFSET */
++	rtw_write8(adapter, REG_TXBUF_WKCAM_OFFSET, cam_start_offset & 0xFF);
++	rtw_write8(adapter, REG_TXBUF_WKCAM_OFFSET + 1, (cam_start_offset >> 8) & 0xFF);
++	/* Enable TX packet buffer access */
++	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
++
++	/* Write the WKFM CAM */
++	for (i = 0; i < WKFMCAM_ADDR_NUM / 2; i++) {
++		/*
++		 * Set Tx packet buffer offset.
++		 * TxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer.
++		 * CAM start offset (unit: 1 byte) =  Index*WKFMCAM_SIZE
++		 * TxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8
++		 * * Index: The index of the wake up frame mask
++		 * * WKFMCAM_SIZE: the total size of one WKFM CAM
++		 * * per entry offset of a WKFM CAM: Addr i * 4 bytes
++		 */
++		tx_buf_ptr = cam_start_offset + ((idx * WKFMCAM_SIZE + i * 8) >> 3);
++
++		if (i == 0) {
++			if (context->type == PATTERN_VALID)
++				data_l = BIT(31);
++			else if (context->type == PATTERN_BROADCAST)
++				data_l = BIT(31) | BIT(26);
++			else if (context->type == PATTERN_MULTICAST)
++				data_l = BIT(31) | BIT(25);
++			else if (context->type == PATTERN_UNICAST)
++				data_l = BIT(31) | BIT(24);
++
++			if (context->crc != 0)
++				data_l |= context->crc;
++
++			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data_l);
++		} else {
++			data_l = context->mask[i * 2 - 2];
++			data_h = context->mask[i * 2 - 1];
++			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data_l);
++			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data_h);
++		}
++
++		rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, (tx_buf_ptr & 0xFFFF) | BIT23 | (0xff <<24));
++		count = 0;
++		do {
++			tmp = rtw_read32(adapter, REG_PKTBUF_DBG_CTRL) & BIT23;
++			rtw_udelay_os(2);
++			count++;
++		} while (tmp && count < 100);
++
++		if (count >= 100) {
++			res = _FALSE;
++			RTW_INFO("%s write failed\n", __func__);
++		} else {
++			res = _TRUE;
++			RTW_INFO("%s write OK\n", __func__);
++		}
++	}
++
++	/* Disable TX packet buffer access */
++	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, DISABLE_TRXPKT_BUF_ACCESS);
++	return res;
++}
++#endif /* CONFIG_WOW_PATTERN_IN_TXFIFO */
++
++void rtw_clean_pattern(_adapter *adapter)
++{
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
++	struct rtl_wow_pattern zero_pattern;
++	int i = 0;
++
++	_rtw_memset(&zero_pattern, 0, sizeof(struct rtl_wow_pattern));
++
++	zero_pattern.type = PATTERN_INVALID;
++
++	for (i = 0; i < MAX_WKFM_CAM_NUM; i++)
++		rtw_write_to_frame_mask(adapter, i, &zero_pattern);
++
++	rtw_write8(adapter, REG_WKFMCAM_NUM, 0);
++}
++#if 0
++static int rtw_hal_set_pattern(_adapter *adapter, u8 *pattern,
++			       u8 len, u8 *mask, u8 idx)
++{
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
++	struct mlme_ext_priv *pmlmeext = NULL;
++	struct mlme_ext_info *pmlmeinfo = NULL;
++	struct rtl_wow_pattern wow_pattern;
++	u8 mask_hw[MAX_WKFM_SIZE] = {0};
++	u8 content[MAX_WKFM_PATTERN_SIZE] = {0};
++	u8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	u8 multicast_addr1[2] = {0x33, 0x33};
++	u8 multicast_addr2[3] = {0x01, 0x00, 0x5e};
++	u8 res = _FALSE, index = 0, mask_len = 0;
++	u8 mac_addr[ETH_ALEN] = {0};
++	u16 count = 0;
++	int i, j;
++
++	if (pwrctl->wowlan_pattern_idx > MAX_WKFM_CAM_NUM) {
++		RTW_INFO("%s pattern_idx is more than MAX_FMC_NUM: %d\n",
++			 __func__, MAX_WKFM_CAM_NUM);
++		return _FALSE;
++	}
++
++	pmlmeext = &adapter->mlmeextpriv;
++	pmlmeinfo = &pmlmeext->mlmext_info;
++	_rtw_memcpy(mac_addr, adapter_mac_addr(adapter), ETH_ALEN);
++	_rtw_memset(&wow_pattern, 0, sizeof(struct rtl_wow_pattern));
++
++	mask_len = DIV_ROUND_UP(len, 8);
++
++	/* 1. setup A1 table */
++	if (memcmp(pattern, broadcast_addr, ETH_ALEN) == 0)
++		wow_pattern.type = PATTERN_BROADCAST;
++	else if (memcmp(pattern, multicast_addr1, 2) == 0)
++		wow_pattern.type = PATTERN_MULTICAST;
++	else if (memcmp(pattern, multicast_addr2, 3) == 0)
++		wow_pattern.type = PATTERN_MULTICAST;
++	else if (memcmp(pattern, mac_addr, ETH_ALEN) == 0)
++		wow_pattern.type = PATTERN_UNICAST;
++	else
++		wow_pattern.type = PATTERN_INVALID;
++
++	/* translate mask from os to mask for hw */
++
++/******************************************************************************
++ * pattern from OS uses 'ethenet frame', like this:
++
++	|    6   |    6   |   2  |     20    |  Variable  |  4  |
++	|--------+--------+------+-----------+------------+-----|
++	|    802.3 Mac Header    | IP Header | TCP Packet | FCS |
++	|   DA   |   SA   | Type |
++
++ * BUT, packet catched by our HW is in '802.11 frame', begin from LLC,
++
++	|     24 or 30      |    6   |   2  |     20    |  Variable  |  4  |
++	|-------------------+--------+------+-----------+------------+-----|
++	| 802.11 MAC Header |       LLC     | IP Header | TCP Packet | FCS |
++			    | Others | Tpye |
++
++ * Therefore, we need translate mask_from_OS to mask_to_hw.
++ * We should left-shift mask by 6 bits, then set the new bit[0~5] = 0,
++ * because new mask[0~5] means 'SA', but our HW packet begins from LLC,
++ * bit[0~5] corresponds to first 6 Bytes in LLC, they just don't match.
++ ******************************************************************************/
++	/* Shift 6 bits */
++	for (i = 0; i < mask_len - 1; i++) {
++		mask_hw[i] = mask[i] >> 6;
++		mask_hw[i] |= (mask[i + 1] & 0x3F) << 2;
++	}
++
++	mask_hw[i] = (mask[i] >> 6) & 0x3F;
++	/* Set bit 0-5 to zero */
++	mask_hw[0] &= 0xC0;
++
++	for (i = 0; i < (MAX_WKFM_SIZE / 4); i++) {
++		wow_pattern.mask[i] = mask_hw[i * 4];
++		wow_pattern.mask[i] |= (mask_hw[i * 4 + 1] << 8);
++		wow_pattern.mask[i] |= (mask_hw[i * 4 + 2] << 16);
++		wow_pattern.mask[i] |= (mask_hw[i * 4 + 3] << 24);
++	}
++
++	/* To get the wake up pattern from the mask.
++	 * We do not count first 12 bits which means
++	 * DA[6] and SA[6] in the pattern to match HW design. */
++	count = 0;
++	for (i = 12; i < len; i++) {
++		if ((mask[i / 8] >> (i % 8)) & 0x01) {
++			content[count] = pattern[i];
++			count++;
++		}
++	}
++
++	wow_pattern.crc = rtw_calc_crc(content, count);
++
++	if (wow_pattern.crc != 0) {
++		if (wow_pattern.type == PATTERN_INVALID)
++			wow_pattern.type = PATTERN_VALID;
++	}
++
++	index = idx;
++
++	if (!pwrctl->bInSuspend)
++		index += 2;
++
++	/* write pattern */
++	res = rtw_write_to_frame_mask(adapter, index, &wow_pattern);
++
++	if (res == _FALSE)
++		RTW_INFO("%s: ERROR!! idx: %d write_to_frame_mask_cam fail\n",
++			 __func__, idx);
++
++	return res;
++}
++#endif
++
++void rtw_fill_pattern(_adapter *adapter)
++{
++	int i = 0, total = 0, index;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	struct rtl_wow_pattern wow_pattern;
++
++	total = pwrpriv->wowlan_pattern_idx;
++
++	if (total > MAX_WKFM_CAM_NUM)
++		total = MAX_WKFM_CAM_NUM;
++
++	for (i = 0 ; i < total ; i++) {
++		if (_SUCCESS == rtw_hal_wow_pattern_generate(adapter, i, &wow_pattern)) {
++
++			index = i;
++			if (!pwrpriv->bInSuspend)
++				index += 2;
++
++			if (rtw_write_to_frame_mask(adapter, index, &wow_pattern) == _FALSE)
++				RTW_INFO("%s: ERROR!! idx: %d write_to_frame_mask_cam fail\n", __func__, i);
++		}
++
++	}
++	rtw_write8(adapter, REG_WKFMCAM_NUM, total);
++
++}
++
++#else /*CONFIG_WOW_PATTERN_HW_CAM*/
++
++#define WOW_CAM_ACCESS_TIMEOUT_MS	200
++#define WOW_VALID_BIT	BIT31
++#define WOW_BC_BIT		BIT26
++#define WOW_MC_BIT		BIT25
++#define WOW_UC_BIT		BIT24
++
++static u32 _rtw_wow_pattern_read_cam(_adapter *adapter, u8 addr)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	_mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;
++
++	u32 rdata = 0;
++	u32 cnt = 0;
++	systime start = 0;
++	u8 timeout = 0;
++	u8 rst = _FALSE;
++
++	_enter_critical_mutex(mutex, NULL);
++
++	rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_ADDR_V2(addr));
++
++	start = rtw_get_current_time();
++	while (1) {
++		if (rtw_is_surprise_removed(adapter))
++			break;
++
++		cnt++;
++		if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1)) {
++			rst = _SUCCESS;
++			break;
++		}
++		if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {
++			timeout = 1;
++			break;
++		}
++	}
++
++	rdata = rtw_read32(adapter, REG_WKFMCAM_RWD);
++
++	_exit_critical_mutex(mutex, NULL);
++
++	/*RTW_INFO("%s ==> addr:0x%02x , rdata:0x%08x\n", __func__, addr, rdata);*/
++
++	if (timeout)
++		RTW_ERR(FUNC_ADPT_FMT" failed due to polling timeout\n", FUNC_ADPT_ARG(adapter));
++
++	return rdata;
++}
++void rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct  rtl_wow_pattern *context)
++{
++	int i;
++	u32 rdata;
++
++	_rtw_memset(context, 0, sizeof(struct  rtl_wow_pattern));
++
++	for (i = 4; i >= 0; i--) {
++		rdata = _rtw_wow_pattern_read_cam(adapter, (id << 3) | i);
++
++		switch (i) {
++		case 4:
++			if (rdata & WOW_BC_BIT)
++				context->type = PATTERN_BROADCAST;
++			else if (rdata & WOW_MC_BIT)
++				context->type = PATTERN_MULTICAST;
++			else if (rdata & WOW_UC_BIT)
++				context->type = PATTERN_UNICAST;
++			else
++				context->type = PATTERN_INVALID;
++
++			context->crc = rdata & 0xFFFF;
++			break;
++		default:
++			_rtw_memcpy(&context->mask[i], (u8 *)(&rdata), 4);
++			break;
++		}
++	}
++}
++
++static void _rtw_wow_pattern_write_cam(_adapter *adapter, u8 addr, u32 wdata)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	_mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;
++	u32 cnt = 0;
++	systime start = 0, end = 0;
++	u8 timeout = 0;
++
++	/*RTW_INFO("%s ==> addr:0x%02x , wdata:0x%08x\n", __func__, addr, wdata);*/
++	_enter_critical_mutex(mutex, NULL);
++
++	rtw_write32(adapter, REG_WKFMCAM_RWD, wdata);
++	rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_WE | BIT_WKFCAM_ADDR_V2(addr));
++
++	start = rtw_get_current_time();
++	while (1) {
++		if (rtw_is_surprise_removed(adapter))
++			break;
++
++		cnt++;
++		if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1))
++			break;
++
++		if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {
++			timeout = 1;
++			break;
++		}
++	}
++	end = rtw_get_current_time();
++
++	_exit_critical_mutex(mutex, NULL);
++
++	if (timeout) {
++		RTW_ERR(FUNC_ADPT_FMT" addr:0x%02x, wdata:0x%08x, to:%u, polling:%u, %d ms\n"
++			, FUNC_ADPT_ARG(adapter), addr, wdata, timeout, cnt, rtw_get_time_interval_ms(start, end));
++	}
++}
++
++void rtw_wow_pattern_write_cam_ent(_adapter *adapter, u8 id, struct  rtl_wow_pattern *context)
++{
++	int j;
++	u8 addr;
++	u32 wdata = 0;
++
++	for (j = 4; j >= 0; j--) {
++		switch (j) {
++		case 4:
++			wdata = context->crc;
++
++			if (PATTERN_BROADCAST == context->type)
++				wdata |= WOW_BC_BIT;
++			if (PATTERN_MULTICAST == context->type)
++				wdata |= WOW_MC_BIT;
++			if (PATTERN_UNICAST == context->type)
++				wdata |= WOW_UC_BIT;
++			if (PATTERN_INVALID != context->type)
++				wdata |= WOW_VALID_BIT;
++			break;
++		default:
++			wdata = context->mask[j];
++			break;
++		}
++
++		addr = (id << 3) + j;
++
++		_rtw_wow_pattern_write_cam(adapter, addr, wdata);
++	}
++}
++
++static u8 _rtw_wow_pattern_clean_cam(_adapter *adapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	_mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;
++	u32 cnt = 0;
++	systime start = 0;
++	u8 timeout = 0;
++	u8 rst = _FAIL;
++
++	_enter_critical_mutex(mutex, NULL);
++	rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_CLR_V1);
++
++	start = rtw_get_current_time();
++	while (1) {
++		if (rtw_is_surprise_removed(adapter))
++			break;
++
++		cnt++;
++		if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1)) {
++			rst = _SUCCESS;
++			break;
++		}
++		if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {
++			timeout = 1;
++			break;
++		}
++	}
++	_exit_critical_mutex(mutex, NULL);
++
++	if (timeout)
++		RTW_ERR(FUNC_ADPT_FMT" falied ,polling timeout\n", FUNC_ADPT_ARG(adapter));
++
++	return rst;
++}
++
++void rtw_clean_pattern(_adapter *adapter)
++{
++	if (_FAIL == _rtw_wow_pattern_clean_cam(adapter))
++		RTW_ERR("rtw_clean_pattern failed\n");
++}
++
++void rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx)
++{
++	int j;
++
++	RTW_PRINT_SEL(sel, "=======WOW CAM-ID[%d]=======\n", idx);
++	RTW_PRINT_SEL(sel, "[WOW CAM] type:%d\n", pwow_pattern->type);
++	RTW_PRINT_SEL(sel, "[WOW CAM] crc:0x%04x\n", pwow_pattern->crc);
++	for (j = 0; j < 4; j++)
++		RTW_PRINT_SEL(sel, "[WOW CAM] Mask:0x%08x\n", pwow_pattern->mask[j]);
++}
++
++void rtw_fill_pattern(_adapter *adapter)
++{
++	int i = 0, total = 0;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	struct rtl_wow_pattern wow_pattern;
++
++	total = pwrpriv->wowlan_pattern_idx;
++
++	if (total > MAX_WKFM_CAM_NUM)
++		total = MAX_WKFM_CAM_NUM;
++
++	for (i = 0 ; i < total ; i++) {
++		if (_SUCCESS == rtw_hal_wow_pattern_generate(adapter, i, &wow_pattern)) {
++			rtw_dump_wow_pattern(RTW_DBGDUMP, &wow_pattern, i);
++			rtw_wow_pattern_write_cam_ent(adapter, i, &wow_pattern);
++		}
++	}
++}
++
++#endif
++void rtw_wow_pattern_cam_dump(_adapter *adapter)
++{
++
++#ifndef CONFIG_WOW_PATTERN_HW_CAM
++	int i;
++
++	for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) {
++		RTW_INFO("=======[%d]=======\n", i);
++		rtw_read_from_frame_mask(adapter, i);
++	}
++#else
++	struct  rtl_wow_pattern context;
++	int i;
++
++	for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) {
++		rtw_wow_pattern_read_cam_ent(adapter, i, &context);
++		rtw_dump_wow_pattern(RTW_DBGDUMP, &context, i);
++	}
++
++#endif
++}
++
++
++static void rtw_hal_dl_pattern(_adapter *adapter, u8 mode)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++
++	switch (mode) {
++	case 0:
++		rtw_clean_pattern(adapter);
++		RTW_INFO("%s: total patterns: %d\n", __func__, pwrpriv->wowlan_pattern_idx);
++		break;
++	case 1:
++		rtw_set_default_pattern(adapter);
++		rtw_fill_pattern(adapter);
++		RTW_INFO("%s: pattern total: %d downloaded\n", __func__, pwrpriv->wowlan_pattern_idx);
++		break;
++	case 2:
++		rtw_clean_pattern(adapter);
++		rtw_wow_pattern_sw_reset(adapter);
++		RTW_INFO("%s: clean patterns\n", __func__);
++		break;
++	default:
++		RTW_INFO("%s: unknown mode\n", __func__);
++		break;
++	}
++}
++
++static void rtw_hal_wow_enable(_adapter *adapter)
++{
++	struct registry_priv  *registry_par = &adapter->registrypriv;
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
++	struct security_priv *psecuritypriv = &adapter->securitypriv;
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	struct sta_info *psta = NULL;
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
++	int res;
++	u16 media_status_rpt;
++	u8 no_wake = 0, i;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	_adapter *iface;
++#ifdef CONFIG_GPIO_WAKEUP
++	u8 val8 = 0;
++#endif
++
++#ifdef CONFIG_LPS_PG
++	u8 lps_pg_hdl_id = 0;
++#endif
++
++
++
++	if(registry_par->suspend_type == FW_IPS_DISABLE_BBRF &&
++	!check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
++		no_wake = 1;
++
++	RTW_PRINT(FUNC_ADPT_FMT " WOWLAN_ENABLE\n", FUNC_ADPT_ARG(adapter));
++	rtw_hal_gate_bb(adapter, _TRUE);
++	
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		/* Start Usb TxDMA */
++		if(iface) {
++			RTW_INFO(ADPT_FMT "enable TX\n", ADPT_ARG(iface));
++			RTW_ENABLE_FUNC(iface, DF_TX_BIT);
++		}
++	}
++	
++#ifdef CONFIG_GTK_OL
++	if (psecuritypriv->binstallKCK_KEK == _TRUE)
++		rtw_hal_fw_sync_cam_id(adapter);
++#endif
++	if (IS_HARDWARE_TYPE_8723B(adapter))
++		rtw_hal_backup_rate(adapter);
++
++	rtw_hal_fw_dl(adapter, _TRUE);
++	if(no_wake)
++		media_status_rpt = RT_MEDIA_DISCONNECT;
++	else
++		media_status_rpt = RT_MEDIA_CONNECT;
++	rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,
++			  (u8 *)&media_status_rpt);
++
++	/* RX DMA stop */
++	#if defined(CONFIG_RTL8188E)
++	if (IS_HARDWARE_TYPE_8188E(adapter))
++		rtw_hal_disable_tx_report(adapter);
++	#endif
++
++	res = rtw_hal_pause_rx_dma(adapter);
++	if (res == _FAIL)
++		RTW_PRINT("[WARNING] pause RX DMA fail\n");
++
++	#ifndef CONFIG_WOW_PATTERN_HW_CAM
++	/* Reconfig RX_FF Boundary */
++	rtw_hal_set_wow_rxff_boundary(adapter, _TRUE);
++	#endif
++
++	/* redownload wow pattern */
++	if(!no_wake)
++		rtw_hal_dl_pattern(adapter, 1);
++
++	if (!pwrctl->wowlan_pno_enable) {
++		psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
++
++		if (psta != NULL) {
++			#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++			adapter_to_dvobj(adapter)->dft.port_id = 0xFF;
++			adapter_to_dvobj(adapter)->dft.mac_id = 0xFF;
++			rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id);
++			#endif
++			if(!no_wake)
++				rtw_sta_media_status_rpt(adapter, psta, 1);
++		}
++#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++		else {
++			if(registry_par->suspend_type == FW_IPS_WRC) {
++				adapter_to_dvobj(adapter)->dft.port_id = 0xFF;
++				adapter_to_dvobj(adapter)->dft.mac_id = 0xFF;
++				rtw_hal_set_default_port_id_cmd(adapter, 0);
++			}
++		}
++#endif /* CONFIG_FW_MULTI_PORT_SUPPORT */
++	}
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	/* Enable CPWM2 only. */
++	res = rtw_hal_enable_cpwm2(adapter);
++	if (res == _FAIL)
++		RTW_PRINT("[WARNING] enable cpwm2 fail\n");
++#endif
++#ifdef CONFIG_GPIO_WAKEUP
++#ifdef CONFIG_RTW_ONE_PIN_GPIO
++	rtw_hal_switch_gpio_wl_ctrl(adapter, pwrctl->wowlan_gpio_index, _TRUE);
++	rtw_hal_set_input_gpio(adapter, pwrctl->wowlan_gpio_index);
++#else
++#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
++	if (pwrctl->is_high_active == 0)
++		rtw_hal_set_input_gpio(adapter, pwrctl->wowlan_gpio_index);
++	else
++		rtw_hal_set_output_gpio(adapter, pwrctl->wowlan_gpio_index,
++			GPIO_OUTPUT_LOW);
++#else
++	val8 = (pwrctl->is_high_active == 0) ? 1 : 0;
++	rtw_hal_set_output_gpio(adapter, pwrctl->wowlan_gpio_index, val8);
++	rtw_hal_switch_gpio_wl_ctrl(adapter, pwrctl->wowlan_gpio_index, _TRUE);
++	RTW_INFO("%s: set GPIO_%d to OUTPUT %s state in wow suspend and %s_ACTIVE.\n",
++		 __func__, pwrctl->wowlan_gpio_index, 
++		 pwrctl->wowlan_gpio_output_state ? "HIGH" : "LOW",
++		 pwrctl->is_high_active ? "HIGI" : "LOW");
++#endif /* CONFIG_WAKEUP_GPIO_INPUT_MODE */
++#endif /* CONFIG_RTW_ONE_PIN_GPIO */
++#endif /* CONFIG_GPIO_WAKEUP */
++	/* Set WOWLAN H2C command. */
++	RTW_PRINT("Set WOWLan cmd\n");
++	rtw_hal_set_fw_wow_related_cmd(adapter, 1);
++
++	res = rtw_hal_check_wow_ctrl(adapter, _TRUE);
++
++	if (res == _FALSE)
++		RTW_INFO("[Error]%s: set wowlan CMD fail!!\n", __func__);
++
++	pwrctl->wowlan_wake_reason =
++		rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
++
++	RTW_PRINT("wowlan_wake_reason: 0x%02x\n",
++		  pwrctl->wowlan_wake_reason);
++#ifdef CONFIG_GTK_OL_DBG
++	dump_sec_cam(RTW_DBGDUMP, adapter);
++	dump_sec_cam_cache(RTW_DBGDUMP, adapter);
++#endif
++
++#ifdef CONFIG_LPS_PG
++	if (pwrctl->lps_level == LPS_PG) {
++		lps_pg_hdl_id = LPS_PG_INFO_CFG;
++		rtw_hal_set_hwreg(adapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));
++	}
++#endif
++
++#ifdef CONFIG_USB_HCI
++	/* free adapter's resource */
++	rtw_mi_intf_stop(adapter);
++
++#endif
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
++	/* Invoid SE0 reset signal during suspending*/
++	rtw_write8(adapter, REG_RSV_CTRL, 0x20);
++	if (IS_8188F(pHalData->version_id) == FALSE
++		&& IS_8188GTV(pHalData->version_id) == FALSE)
++		rtw_write8(adapter, REG_RSV_CTRL, 0x60);
++#endif
++
++	rtw_hal_gate_bb(adapter, _FALSE);
++}
++
++#define DBG_WAKEUP_REASON
++#ifdef DBG_WAKEUP_REASON
++void _dbg_wake_up_reason_string(_adapter *adapter, const char *srt_res)
++{
++	RTW_INFO(ADPT_FMT "- wake up reason - %s\n", ADPT_ARG(adapter), srt_res);
++}
++void _dbg_rtw_wake_up_reason(_adapter *adapter, u8 reason)
++{
++	if (RX_PAIRWISEKEY == reason)
++		_dbg_wake_up_reason_string(adapter, "Rx pairwise key");
++	else if (RX_GTK == reason)
++		_dbg_wake_up_reason_string(adapter, "Rx GTK");
++	else if (RX_FOURWAY_HANDSHAKE == reason)
++		_dbg_wake_up_reason_string(adapter, "Rx four way handshake");
++	else if (RX_DISASSOC == reason)
++		_dbg_wake_up_reason_string(adapter, "Rx disassoc");
++	else if (RX_DEAUTH == reason)
++		_dbg_wake_up_reason_string(adapter, "Rx deauth");
++	else if (RX_ARP_REQUEST == reason)
++		_dbg_wake_up_reason_string(adapter, "Rx ARP request");
++	else if (FW_DECISION_DISCONNECT == reason)
++		_dbg_wake_up_reason_string(adapter, "FW detect disconnect");
++	else if (RX_MAGIC_PKT == reason)
++		_dbg_wake_up_reason_string(adapter, "Rx magic packet");
++	else if (RX_UNICAST_PKT == reason)
++		_dbg_wake_up_reason_string(adapter, "Rx unicast packet");
++	else if (RX_PATTERN_PKT == reason)
++		_dbg_wake_up_reason_string(adapter, "Rx pattern packet");
++	else if (RTD3_SSID_MATCH == reason)
++		_dbg_wake_up_reason_string(adapter, "RTD3 SSID match");
++	else if (RX_REALWOW_V2_WAKEUP_PKT == reason)
++		_dbg_wake_up_reason_string(adapter, "Rx real WOW V2 wakeup packet");
++	else if (RX_REALWOW_V2_ACK_LOST == reason)
++		_dbg_wake_up_reason_string(adapter, "Rx real WOW V2 ack lost");
++	else if (ENABLE_FAIL_DMA_IDLE == reason)
++		_dbg_wake_up_reason_string(adapter, "enable fail DMA idle");
++	else if (ENABLE_FAIL_DMA_PAUSE == reason)
++		_dbg_wake_up_reason_string(adapter, "enable fail DMA pause");
++	else if (AP_OFFLOAD_WAKEUP == reason)
++		_dbg_wake_up_reason_string(adapter, "AP offload wakeup");
++	else if (CLK_32K_UNLOCK == reason)
++		_dbg_wake_up_reason_string(adapter, "clk 32k unlock");
++	else if (RTIME_FAIL_DMA_IDLE == reason)
++		_dbg_wake_up_reason_string(adapter, "RTIME fail DMA idle");
++	else if (CLK_32K_LOCK == reason)
++		_dbg_wake_up_reason_string(adapter, "clk 32k lock");
++	else
++		_dbg_wake_up_reason_string(adapter, "unknown reasoen");
++}
++#endif
++
++static void rtw_hal_wow_disable(_adapter *adapter)
++{
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
++	struct security_priv *psecuritypriv = &adapter->securitypriv;
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	struct sta_info *psta = NULL;
++	struct registry_priv  *registry_par = &adapter->registrypriv;
++	int res;
++	u16 media_status_rpt;
++
++	RTW_PRINT("%s, WOWLAN_DISABLE\n", __func__);
++	
++	if(registry_par->suspend_type == FW_IPS_DISABLE_BBRF && !check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
++		RTW_INFO("FW_IPS_DISABLE_BBRF resume\n");
++		return;
++	}
++	
++	if (!pwrctl->wowlan_pno_enable) {
++		psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
++		if (psta != NULL)
++			rtw_sta_media_status_rpt(adapter, psta, 0);
++		else
++			RTW_INFO("%s: psta is null\n", __func__);
++	}
++
++	if (0) {
++		RTW_INFO("0x630:0x%02x\n", rtw_read8(adapter, 0x630));
++		RTW_INFO("0x631:0x%02x\n", rtw_read8(adapter, 0x631));
++		RTW_INFO("0x634:0x%02x\n", rtw_read8(adapter, 0x634));
++		RTW_INFO("0x1c7:0x%02x\n", rtw_read8(adapter, 0x1c7));
++	}
++
++	pwrctl->wowlan_wake_reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
++
++	RTW_PRINT("wakeup_reason: 0x%02x\n",
++		  pwrctl->wowlan_wake_reason);
++	#ifdef DBG_WAKEUP_REASON
++	_dbg_rtw_wake_up_reason(adapter, pwrctl->wowlan_wake_reason);
++	#endif
++
++	rtw_hal_set_fw_wow_related_cmd(adapter, 0);
++
++	res = rtw_hal_check_wow_ctrl(adapter, _FALSE);
++
++	if (res == _FALSE) {
++		RTW_INFO("[Error]%s: disable WOW cmd fail\n!!", __func__);
++		rtw_hal_force_enable_rxdma(adapter);
++	}
++
++	rtw_hal_gate_bb(adapter, _TRUE);
++
++	res = rtw_hal_pause_rx_dma(adapter);
++	if (res == _FAIL)
++		RTW_PRINT("[WARNING] pause RX DMA fail\n");
++
++	/* clean HW pattern match */
++	rtw_hal_dl_pattern(adapter, 0);
++
++	#ifndef CONFIG_WOW_PATTERN_HW_CAM
++	/* config RXFF boundary to original */
++	rtw_hal_set_wow_rxff_boundary(adapter, _FALSE);
++	#endif
++	rtw_hal_release_rx_dma(adapter);
++
++	#if defined(CONFIG_RTL8188E)
++	if (IS_HARDWARE_TYPE_8188E(adapter))
++		rtw_hal_enable_tx_report(adapter);
++	#endif
++
++	if ((pwrctl->wowlan_wake_reason != RX_DISASSOC) &&
++		(pwrctl->wowlan_wake_reason != RX_DEAUTH) &&
++		(pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT)) {
++		rtw_hal_get_aoac_rpt(adapter);
++		rtw_hal_update_sw_security_info(adapter);
++	}
++
++	rtw_hal_fw_dl(adapter, _FALSE);
++
++#ifdef CONFIG_GPIO_WAKEUP
++
++#ifdef CONFIG_RTW_ONE_PIN_GPIO
++	rtw_hal_set_input_gpio(adapter, pwrctl->wowlan_gpio_index);
++#else
++#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
++	if (pwrctl->is_high_active == 0)
++		rtw_hal_set_input_gpio(adapter, pwrctl->wowlan_gpio_index);
++	else
++		rtw_hal_set_output_gpio(adapter, pwrctl->wowlan_gpio_index,
++			GPIO_OUTPUT_LOW);
++#else
++	rtw_hal_set_output_gpio(adapter, pwrctl->wowlan_gpio_index
++		, pwrctl->wowlan_gpio_output_state);
++	RTW_INFO("%s: set GPIO_%d to OUTPUT %s state in wow resume and %s_ACTIVE.\n",
++		 __func__, pwrctl->wowlan_gpio_index, 
++		 pwrctl->wowlan_gpio_output_state ? "HIGH" : "LOW",
++		 pwrctl->is_high_active ? "HIGI" : "LOW");
++#endif /* CONFIG_WAKEUP_GPIO_INPUT_MODE */
++#endif /* CONFIG_RTW_ONE_PIN_GPIO */
++#endif /* CONFIG_GPIO_WAKEUP */
++	if ((pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT) &&
++	    (pwrctl->wowlan_wake_reason != RX_PAIRWISEKEY) &&
++	    (pwrctl->wowlan_wake_reason != RX_DISASSOC) &&
++	    (pwrctl->wowlan_wake_reason != RX_DEAUTH)) {
++
++		media_status_rpt = RT_MEDIA_CONNECT;
++		rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,
++				  (u8 *)&media_status_rpt);
++
++		if (psta != NULL) {
++			#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++			adapter_to_dvobj(adapter)->dft.port_id = 0xFF;
++			adapter_to_dvobj(adapter)->dft.mac_id = 0xFF;
++			rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id);
++			#endif
++			rtw_sta_media_status_rpt(adapter, psta, 1);
++		}
++	}
++	rtw_hal_gate_bb(adapter, _FALSE);
++}
++#endif /*CONFIG_WOWLAN*/
++
++#ifdef CONFIG_P2P_WOWLAN
++void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
++	      u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len,
++				      RSVDPAGE_LOC *rsvd_page_loc)
++{
++	u32 P2PNegoRspLength = 0, P2PInviteRspLength = 0;
++	u32 P2PPDRspLength = 0, P2PProbeRspLength = 0, P2PBCNLength = 0;
++	u8 CurtPktPageNum = 0;
++
++	/* P2P Beacon */
++	rsvd_page_loc->LocP2PBeacon = *page_num;
++	rtw_hal_construct_P2PBeacon(adapter, &pframe[index], &P2PBCNLength);
++	rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
++				 P2PBCNLength, _FALSE, _FALSE, _FALSE);
++
++#if 0
++	RTW_INFO("%s(): HW_VAR_SET_TX_CMD: PROBE RSP %p %d\n",
++		__FUNCTION__, &pframe[index - tx_desc], (P2PBCNLength + tx_desc));
++#endif
++
++	CurtPktPageNum = (u8)PageNum(tx_desc + P2PBCNLength, page_size);
++
++	*page_num += CurtPktPageNum;
++
++	index += (CurtPktPageNum * page_size);
++	RSVD_PAGE_CFG("WOW-P2P-Beacon", CurtPktPageNum, *page_num, 0);
++
++	/* P2P Probe rsp */
++	rsvd_page_loc->LocP2PProbeRsp = *page_num;
++	rtw_hal_construct_P2PProbeRsp(adapter, &pframe[index],
++				      &P2PProbeRspLength);
++	rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
++				 P2PProbeRspLength, _FALSE, _FALSE, _FALSE);
++
++	/* RTW_INFO("%s(): HW_VAR_SET_TX_CMD: PROBE RSP %p %d\n",  */
++	/*	__FUNCTION__, &pframe[index-tx_desc], (P2PProbeRspLength+tx_desc)); */
++
++	CurtPktPageNum = (u8)PageNum(tx_desc + P2PProbeRspLength, page_size);
++
++	*page_num += CurtPktPageNum;
++
++	index += (CurtPktPageNum * page_size);
++	RSVD_PAGE_CFG("WOW-P2P-ProbeRsp", CurtPktPageNum, *page_num, 0);
++
++	/* P2P nego rsp */
++	rsvd_page_loc->LocNegoRsp = *page_num;
++	rtw_hal_construct_P2PNegoRsp(adapter, &pframe[index],
++				     &P2PNegoRspLength);
++	rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
++				 P2PNegoRspLength, _FALSE, _FALSE, _FALSE);
++
++	/* RTW_INFO("%s(): HW_VAR_SET_TX_CMD: QOS NULL DATA %p %d\n",  */
++	/*	__FUNCTION__, &pframe[index-tx_desc], (NegoRspLength+tx_desc)); */
++
++	CurtPktPageNum = (u8)PageNum(tx_desc + P2PNegoRspLength, page_size);
++
++	*page_num += CurtPktPageNum;
++
++	index += (CurtPktPageNum * page_size);
++	RSVD_PAGE_CFG("WOW-P2P-NegoRsp", CurtPktPageNum, *page_num, 0);
++
++	/* P2P invite rsp */
++	rsvd_page_loc->LocInviteRsp = *page_num;
++	rtw_hal_construct_P2PInviteRsp(adapter, &pframe[index],
++				       &P2PInviteRspLength);
++	rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
++				 P2PInviteRspLength, _FALSE, _FALSE, _FALSE);
++
++	/* RTW_INFO("%s(): HW_VAR_SET_TX_CMD: QOS NULL DATA %p %d\n",  */
++	/* __FUNCTION__, &pframe[index-tx_desc], (InviteRspLength+tx_desc)); */
++
++	CurtPktPageNum = (u8)PageNum(tx_desc + P2PInviteRspLength, page_size);
++
++	*page_num += CurtPktPageNum;
++
++	index += (CurtPktPageNum * page_size);
++	RSVD_PAGE_CFG("WOW-P2P-InviteRsp", CurtPktPageNum, *page_num, 0);
++
++	/* P2P provision discovery rsp */
++	rsvd_page_loc->LocPDRsp = *page_num;
++	rtw_hal_construct_P2PProvisionDisRsp(adapter,
++					     &pframe[index], &P2PPDRspLength);
++
++	rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
++				 P2PPDRspLength, _FALSE, _FALSE, _FALSE);
++
++	/* RTW_INFO("%s(): HW_VAR_SET_TX_CMD: QOS NULL DATA %p %d\n",  */
++	/*	__FUNCTION__, &pframe[index-tx_desc], (PDRspLength+tx_desc)); */
++
++	CurtPktPageNum = (u8)PageNum(tx_desc + P2PPDRspLength, page_size);
++
++	*page_num += CurtPktPageNum;
++
++	*total_pkt_len = index + P2PPDRspLength;
++	RSVD_PAGE_CFG("WOW-P2P-PDR", CurtPktPageNum, *page_num, *total_pkt_len);
++
++	index += (CurtPktPageNum * page_size);
++
++
++}
++#endif /* CONFIG_P2P_WOWLAN */
++
++#ifdef CONFIG_LPS_PG
++#ifndef DBG_LPSPG_INFO_DUMP
++#define DBG_LPSPG_INFO_DUMP 1
++#endif
++
++#include "hal_halmac.h"
++
++#ifdef CONFIG_RTL8822C
++static int rtw_lps_pg_set_dpk_info_rsvd_page(_adapter *adapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct dm_struct *dm = adapter_to_phydm(adapter);
++	struct rsvd_page_cache_t *cache = &pwrpriv->lpspg_dpk_info;
++	u8 *info = NULL;
++	u32 info_len;
++	int ret = _FAIL;
++
++	/* get length */
++	halrf_dpk_info_rsvd_page(dm, NULL, &info_len);
++	if (!info_len) {
++		RTW_ERR("get %s length fail\n", cache->name);
++		goto exit;
++	}
++
++	/* allocate buf */
++	info = rtw_zmalloc(info_len);
++	if (!info) {
++		RTW_ERR("alloc %s buffer fail(len=%d)\n", cache->name, info_len);
++		goto exit;
++	}
++
++	/* get content */
++	halrf_dpk_info_rsvd_page(dm, info, NULL);
++
++	if (rsvd_page_cache_update_data(cache, info, info_len)) {
++
++		#if (DBG_LPSPG_INFO_DUMP >= 1)
++		RTW_INFO_DUMP(cache->name, info, info_len);
++		#endif
++
++		ret = rtw_halmac_download_rsvd_page(dvobj, cache->loc, info, info_len);
++		ret = !ret ? _SUCCESS : _FAIL;
++		if (ret != _SUCCESS) {
++			RTW_ERR("download %s rsvd page to offset:%u fail\n", cache->name, cache->loc);
++			goto free_mem;
++		}
++
++		#if (DBG_LPSPG_INFO_DUMP >= 2)
++		RTW_INFO("get %s from rsvd page offset:%d\n", cache->name, cache->loc);
++		rtw_dump_rsvd_page(RTW_DBGDUMP, adapter, cache->loc, cache->page_num);
++		#endif
++	}
++
++free_mem:
++	rtw_mfree(info, info_len);
++
++exit:
++	return ret;
++}
++
++static int rtw_lps_pg_set_iqk_info_rsvd_page(_adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct dm_struct *dm = adapter_to_phydm(adapter);
++	struct rsvd_page_cache_t *cache = &pwrpriv->lpspg_iqk_info;
++	u8 *info = NULL;
++	u32 info_len = 0;
++	int ret = _FAIL;
++
++	if (hal_data->RegIQKFWOffload) {
++		rsvd_page_cache_free_data(cache);
++		ret = _SUCCESS;
++		goto exit;
++	}
++
++	/* get length */
++	halrf_iqk_info_rsvd_page(dm, NULL, &info_len);
++	if (!info_len) {
++		RTW_ERR("get %s length fail\n", cache->name);
++		goto exit;
++	}
++
++	/* allocate buf */
++	info = rtw_zmalloc(info_len);
++	if (!info) {
++		RTW_ERR("alloc %s buffer fail(len=%d)\n", cache->name, info_len);
++		goto exit;
++	}
++
++	/* get content */
++	halrf_iqk_info_rsvd_page(dm, info, NULL);
++
++	if (rsvd_page_cache_update_data(cache, info, info_len)) {
++
++		#if (DBG_LPSPG_INFO_DUMP >= 1)
++		RTW_INFO_DUMP(cache->name, info, info_len);
++		#endif
++
++		ret = rtw_halmac_download_rsvd_page(dvobj, cache->loc, info, info_len);
++		ret = !ret ? _SUCCESS : _FAIL;
++		if (ret != _SUCCESS) {
++			RTW_ERR("download %s rsvd page to offset:%u fail\n", cache->name, cache->loc);
++			goto free_mem;
++		}
++
++		#if (DBG_LPSPG_INFO_DUMP >= 2)
++		RTW_INFO("get %s from rsvd page offset:%d\n", cache->name, cache->loc);
++		rtw_dump_rsvd_page(RTW_DBGDUMP, adapter, cache->loc, cache->page_num);
++		#endif
++	}
++
++free_mem:
++	rtw_mfree(info, info_len);
++
++exit:
++	return ret;
++}
++#endif /* CONFIG_RTL8822C */
++
++static void rtw_hal_build_lps_pg_info_rsvd_page(struct dvobj_priv *dvobj, _adapter *ld_sta_iface, u8 *buf, u32 *buf_size)
++{
++#define LPS_PG_INFO_RSVD_LEN	16
++
++	if (buf) {
++		_adapter *adapter = dvobj_get_primary_adapter(dvobj);
++		struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++		struct sta_info *psta;
++#ifdef CONFIG_MBSSID_CAM
++		u8 cam_id = INVALID_CAM_ID;
++#endif
++		u8 *psec_cam_id = buf + 8;
++		u8 sec_cam_num = 0;
++		u8 drv_rsvdpage_num = 0;
++
++		if (ld_sta_iface) {
++			psta = rtw_get_stainfo(&ld_sta_iface->stapriv, get_bssid(&ld_sta_iface->mlmepriv));
++			if (!psta) {
++				RTW_ERR("%s [ERROR] sta is NULL\n", __func__);
++				rtw_warn_on(1);
++				goto size_chk;
++			}
++			/*Byte 0 - used macid*/
++			LPSPG_RSVD_PAGE_SET_MACID(buf, psta->cmn.mac_id);
++			RTW_INFO("[LPSPG-INFO] mac_id:%d\n", psta->cmn.mac_id);
++		}
++
++#ifdef CONFIG_MBSSID_CAM
++		/*Byte 1 - used BSSID CAM entry*/
++		cam_id = rtw_mbid_cam_search_by_ifaceid(adapter, adapter->iface_id);
++		if (cam_id != INVALID_CAM_ID)
++			LPSPG_RSVD_PAGE_SET_MBSSCAMID(buf, cam_id);
++		RTW_INFO("[LPSPG-INFO] mbss_cam_id:%d\n", cam_id);
++#endif
++
++#ifdef CONFIG_WOWLAN /*&& pattern match cam used*/
++		/*Btye 2 - Max used Pattern Match CAM entry*/
++		if (pwrpriv->wowlan_mode == _TRUE
++			&& ld_sta_iface && check_fwstate(&ld_sta_iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++			LPSPG_RSVD_PAGE_SET_PMC_NUM(buf, pwrpriv->wowlan_pattern_idx);
++			RTW_INFO("[LPSPG-INFO] Max Pattern Match CAM entry :%d\n", pwrpriv->wowlan_pattern_idx);
++		}
++#endif
++#ifdef CONFIG_BEAMFORMING  /*&& MU BF*/
++		/*Btye 3 - Max MU rate table Group ID*/
++		LPSPG_RSVD_PAGE_SET_MU_RAID_GID(buf, 0);
++		RTW_INFO("[LPSPG-INFO] Max MU rate table Group ID :%d\n", 0);
++#endif
++
++		/*Btye 8 ~15 - used Security CAM entry */
++		sec_cam_num = rtw_get_sec_camid(adapter, 8, psec_cam_id);
++
++		/*Btye 4 - used Security CAM entry number*/
++		if (sec_cam_num < 8)
++			LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(buf, sec_cam_num);
++		RTW_INFO("[LPSPG-INFO] Security CAM entry number :%d\n", sec_cam_num);
++
++		/*Btye 5 - Txbuf used page number for fw offload*/
++		if (pwrpriv->wowlan_mode == _TRUE || pwrpriv->wowlan_ap_mode == _TRUE)
++			drv_rsvdpage_num = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE);
++		else
++			drv_rsvdpage_num = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE);
++		LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(buf, drv_rsvdpage_num);
++		RTW_INFO("[LPSPG-INFO] DRV's rsvd page numbers :%d\n", drv_rsvdpage_num);
++	}
++
++size_chk:
++	if (buf_size)
++		*buf_size = LPS_PG_INFO_RSVD_LEN;
++}
++
++static int rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct rsvd_page_cache_t *cache = &pwrpriv->lpspg_info;
++	u8 *info = NULL;
++	u32 info_len = 0;
++	int ret = _FAIL;
++
++	/* get length */
++	rtw_hal_build_lps_pg_info_rsvd_page(dvobj, adapter, NULL, &info_len);
++	if (!info_len) {
++		RTW_ERR("get %s length fail\n", cache->name);
++		goto exit;
++	}
++
++	/* allocate buf */
++	info = rtw_zmalloc(info_len);
++	if (!info) {
++		RTW_ERR("alloc %s buffer fail(len=%d)\n", cache->name, info_len);
++		goto exit;
++	}
++
++	/* get content */
++	rtw_hal_build_lps_pg_info_rsvd_page(dvobj, adapter, info, NULL);
++
++	if (rsvd_page_cache_update_data(cache, info, info_len)) {
++
++		#if (DBG_LPSPG_INFO_DUMP >= 1)
++		RTW_INFO_DUMP(cache->name, info, info_len);
++		#endif
++
++		ret = rtw_halmac_download_rsvd_page(dvobj, cache->loc, info, info_len);
++		ret = !ret ? _SUCCESS : _FAIL;
++		if (ret != _SUCCESS) {
++			RTW_ERR("download %s rsvd page to offset:%u fail\n", cache->name, cache->loc);
++			goto free_mem;
++		}
++
++		#if (DBG_LPSPG_INFO_DUMP >= 2)
++		RTW_INFO("get %s from rsvd page offset:%d\n", cache->name, cache->loc);
++		rtw_dump_rsvd_page(RTW_DBGDUMP, adapter, cache->loc, cache->page_num);
++		#endif
++	}
++
++free_mem:
++	rtw_mfree(info, info_len);
++
++exit:
++	return ret;
++}
++
++static void rtw_lps_pg_set_rsvd_page(_adapter *adapter, u8 *frame, u16 *index
++	, u8 txdesc_size, u32 page_size, u8 *total_page_num
++	, bool is_wow_mode, _adapter *ld_sta_iface, bool only_get_page_num)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
++	struct rsvd_page_cache_t *cache;
++	bool rsvd = 1;
++	u8 *pos;
++	u32 len;
++
++	if (is_wow_mode) {
++		/* lps_level will not change when enter wow_mode */
++		if (pwrctl->lps_level != LPS_PG)
++			rsvd = 0;
++	} else {
++		if (!only_get_page_num && !ld_sta_iface)
++			rsvd = 0;
++	}
++
++	pos = only_get_page_num ? NULL : frame + *index;
++
++#ifdef CONFIG_RTL8822C
++	if (IS_8822C_SERIES(hal_data->version_id)) {
++		/* LPSPG_DPK_INFO */
++		cache = &pwrctl->lpspg_dpk_info;
++		if (rsvd) {
++			if (pwrctl->lps_level != LPS_PG)
++				pos = NULL;
++			len = 0;
++			halrf_dpk_info_rsvd_page(adapter_to_phydm(adapter), pos, &len);
++			#if (DBG_LPSPG_INFO_DUMP >= 1)
++			if (pos)
++				RTW_INFO_DUMP(cache->name, pos, len);
++			#endif
++			rsvd_page_cache_update_all(cache, *total_page_num, txdesc_size, page_size, pos, len);
++			*total_page_num += cache->page_num;
++			*index += page_size * cache->page_num;
++			pos = only_get_page_num ? NULL : frame + *index;
++			RSVD_PAGE_CFG(cache->name, cache->page_num, *total_page_num, *index);
++		} else
++			rsvd_page_cache_free(cache);
++
++		/* LPSPG_IQK_INFO */
++		cache = &pwrctl->lpspg_iqk_info;
++		if (rsvd
++			/* RegIQKFWOffload will not change when enter wow_mode */
++			&& !(is_wow_mode && hal_data->RegIQKFWOffload)
++		) {
++			if (pwrctl->lps_level != LPS_PG || hal_data->RegIQKFWOffload)
++				pos = NULL;
++			len = 0;
++			halrf_iqk_info_rsvd_page(adapter_to_phydm(adapter), pos, &len);
++			#if (DBG_LPSPG_INFO_DUMP >= 1)
++			if (pos)
++				RTW_INFO_DUMP(cache->name, pos, len);
++			#endif
++			rsvd_page_cache_update_all(cache, *total_page_num, txdesc_size, page_size, pos, len);
++			*total_page_num += cache->page_num;
++			*index += page_size * cache->page_num;
++			pos = only_get_page_num ? NULL : frame + *index;
++			RSVD_PAGE_CFG(cache->name, cache->page_num, *total_page_num, *index);
++		} else
++			rsvd_page_cache_free(cache);
++	}
++#endif
++
++	/* LPSPG_INFO */
++	cache = &pwrctl->lpspg_info;
++	if (rsvd) {
++		if (pwrctl->lps_level != LPS_PG)
++			pos = NULL;
++		rtw_hal_build_lps_pg_info_rsvd_page(adapter_to_dvobj(adapter), ld_sta_iface, pos, &len);
++		#if (DBG_LPSPG_INFO_DUMP >= 1)
++		if (pos)
++			RTW_INFO_DUMP(cache->name, pos, len);
++		#endif
++		rsvd_page_cache_update_all(cache, *total_page_num, txdesc_size, page_size, pos, len);
++		*total_page_num += cache->page_num;
++		*index += page_size * cache->page_num;
++		pos = only_get_page_num ? NULL : frame + *index;
++		RSVD_PAGE_CFG(cache->name, cache->page_num, *total_page_num, *index);
++	} else
++		rsvd_page_cache_free(cache);
++}
++
++u8 rtw_hal_set_lps_pg_info_cmd(_adapter *adapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++
++	u8 lpspg_info[H2C_LPS_PG_INFO_LEN] = {0};
++	u8 ret = _FAIL;
++
++	if (_NO_PRIVACY_ != adapter->securitypriv.dot11PrivacyAlgrthm)
++		SET_H2CCMD_LPSPG_SEC_CAM_EN(lpspg_info, 1);	/*SecurityCAM_En*/
++
++#ifdef CONFIG_MBSSID_CAM
++	SET_H2CCMD_LPSPG_MBID_CAM_EN(lpspg_info, 1);		/*BSSIDCAM_En*/
++#endif
++
++#if defined(CONFIG_WOWLAN) && defined(CONFIG_WOW_PATTERN_HW_CAM)
++	if (pwrpriv->wowlan_mode == _TRUE &&
++	    check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++
++		SET_H2CCMD_LPSPG_PMC_CAM_EN(lpspg_info, 1);	/*PatternMatchCAM_En*/
++	}
++#endif
++
++#ifdef CONFIG_MACID_SEARCH
++	SET_H2CCMD_LPSPG_MACID_SEARCH_EN(lpspg_info, 1);	/*MACIDSearch_En*/
++#endif
++
++#ifdef CONFIG_TX_SC
++	SET_H2CCMD_LPSPG_TXSC_EN(lpspg_info, 1);	/*TXSC_En*/
++#endif
++
++#ifdef CONFIG_BEAMFORMING  /*&& MU BF*/
++	SET_H2CCMD_LPSPG_MU_RATE_TB_EN(lpspg_info, 1);	/*MURateTable_En*/
++#endif
++
++	SET_H2CCMD_LPSPG_LOC(lpspg_info, pwrpriv->lpspg_info.loc);
++
++#ifdef CONFIG_RTL8822C
++	if (pwrpriv->bFwCurrentInPSMode == _FALSE) {
++		SET_H2CCMD_LPSPG_DPK_INFO_LOC(lpspg_info, pwrpriv->lpspg_dpk_info.loc);
++		if (!GET_HAL_DATA(adapter)->RegIQKFWOffload)
++			SET_H2CCMD_LPSPG_IQK_INFO_LOC(lpspg_info, pwrpriv->lpspg_iqk_info.loc);
++	} else {
++		SET_H2CCMD_LPSPG_DPK_INFO_LOC(lpspg_info, 0);
++		if (!GET_HAL_DATA(adapter)->RegIQKFWOffload)
++			SET_H2CCMD_LPSPG_IQK_INFO_LOC(lpspg_info, 0);
++	}
++#endif
++
++#if (DBG_LPSPG_INFO_DUMP >= 1)
++	RTW_INFO_DUMP("H2C_LPS_PG_INFO: ", lpspg_info, H2C_LPS_PG_INFO_LEN);
++#endif
++
++	ret = rtw_hal_fill_h2c_cmd(adapter,
++				   H2C_LPS_PG_INFO,
++				   H2C_LPS_PG_INFO_LEN,
++				   lpspg_info);
++	return ret;
++}
++u8 rtw_hal_set_lps_pg_info(_adapter *adapter)
++{
++	u8 ret = _FAIL;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++
++	if (pwrpriv->lpspg_info.loc == 0) {
++		RTW_ERR("%s lpspg_info.loc = 0\n", __func__);
++		rtw_warn_on(1);
++		return ret;
++	}
++	#ifdef CONFIG_RTL8822C
++	rtw_lps_pg_set_dpk_info_rsvd_page(adapter);
++	rtw_lps_pg_set_iqk_info_rsvd_page(adapter);
++	#endif
++	rtw_hal_set_lps_pg_info_rsvd_page(adapter);
++
++	ret = rtw_hal_set_lps_pg_info_cmd(adapter);
++
++	return ret;
++}
++
++void rtw_hal_lps_pg_rssi_lv_decide(_adapter *adapter, struct sta_info *sta)
++{
++#if 0
++	if (sta->cmn.ra_info.rssi_level >= 4)
++		sta->lps_pg_rssi_lv = 3;	/*RSSI High - 1SS_VHT_MCS7*/
++	else if (sta->cmn.ra_info.rssi_level >=  2)
++		sta->lps_pg_rssi_lv = 2;	/*RSSI Middle - 1SS_VHT_MCS3*/
++	else
++		sta->lps_pg_rssi_lv = 1;	/*RSSI Lower - Lowest_rate*/
++#else
++	sta->lps_pg_rssi_lv = 0;
++#endif
++	RTW_INFO("%s mac-id:%d, rssi:%d, rssi_level:%d, lps_pg_rssi_lv:%d\n",
++		__func__, sta->cmn.mac_id, sta->cmn.rssi_stat.rssi, sta->cmn.ra_info.rssi_level, sta->lps_pg_rssi_lv);
++}
++
++void rtw_hal_lps_pg_handler(_adapter *adapter, enum lps_pg_hdl_id hdl_id)
++{
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct sta_priv *pstapriv = &adapter->stapriv;
++	struct sta_info *sta;
++
++	sta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
++
++	switch (hdl_id) {
++	case LPS_PG_INFO_CFG:
++		rtw_hal_set_lps_pg_info(adapter);
++		break;
++	case LPS_PG_REDLEMEM:
++		if (IS_8822C_SERIES(GET_HAL_DATA(adapter)->version_id))
++			break;
++
++		/*set xmit_block*/
++		rtw_set_xmit_block(adapter, XMIT_BLOCK_REDLMEM);
++		if (_FAIL == rtw_hal_fw_mem_dl(adapter, FW_EMEM))
++			rtw_warn_on(1);
++		/*clearn xmit_block*/
++		rtw_clr_xmit_block(adapter, XMIT_BLOCK_REDLMEM);
++		break;
++	case LPS_PG_PHYDM_DIS:/*Disable RA and PT by H2C*/
++		if (IS_8822C_SERIES(GET_HAL_DATA(adapter)->version_id))
++			break;
++
++		if (sta)
++			rtw_phydm_lps_pg_hdl(adapter, sta, _TRUE);
++		break;
++	case LPS_PG_PHYDM_EN:/*Enable RA and PT by H2C*/
++		if (IS_8822C_SERIES(GET_HAL_DATA(adapter)->version_id))
++			break;
++
++		if (sta) {
++			rtw_hal_lps_pg_rssi_lv_decide(adapter, sta);
++			rtw_phydm_lps_pg_hdl(adapter, sta, _FALSE);
++			sta->lps_pg_rssi_lv = 0;
++		}
++		break;
++
++	default:
++		break;
++	}
++}
++
++#endif /*CONFIG_LPS_PG*/
++
++static u8 _rtw_mi_assoc_if_num(_adapter *adapter)
++{
++	u8 mi_iface_num = 0;
++
++	if (0) {
++		RTW_INFO("[IFS_ASSOC_STATUS] - STA :%d", DEV_STA_LD_NUM(adapter_to_dvobj(adapter)));
++		RTW_INFO("[IFS_ASSOC_STATUS] - AP:%d", DEV_AP_NUM(adapter_to_dvobj(adapter)));
++		RTW_INFO("[IFS_ASSOC_STATUS] - AP starting :%d", DEV_AP_STARTING_NUM(adapter_to_dvobj(adapter)));
++		RTW_INFO("[IFS_ASSOC_STATUS] - MESH :%d", DEV_MESH_NUM(adapter_to_dvobj(adapter)));
++		RTW_INFO("[IFS_ASSOC_STATUS] - ADHOC :%d", DEV_ADHOC_NUM(adapter_to_dvobj(adapter)));
++		/*RTW_INFO("[IFS_ASSOC_STATUS] - P2P-GC :%d", DEV_P2P_GC_NUM(adapter_to_dvobj(adapter)));*/
++		/*RTW_INFO("[IFS_ASSOC_STATUS] - P2P-GO :%d", DEV_P2P_GO_NUM(adapter_to_dvobj(adapter)));*/
++	}
++
++	mi_iface_num = (DEV_STA_LD_NUM(adapter_to_dvobj(adapter)) +
++		DEV_AP_NUM(adapter_to_dvobj(adapter)) +
++		DEV_AP_STARTING_NUM(adapter_to_dvobj(adapter)));
++	return mi_iface_num;
++}
++#ifdef CONFIG_CONCURRENT_MODE
++static _adapter *_rtw_search_sta_iface(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	_adapter *iface = NULL;
++	_adapter *sta_iface = NULL;
++	int i;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) {
++			if (check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++				sta_iface = iface;
++				break;
++			}
++		}
++	}
++	return sta_iface;
++}
++#if defined(CONFIG_AP_MODE) && defined(CONFIG_BT_COEXIST)
++static _adapter *_rtw_search_ap_iface(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	_adapter *iface = NULL;
++	_adapter *ap_iface = NULL;
++	int i;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE ) {
++			ap_iface = iface;
++			break;
++		}
++	}
++	return ap_iface;
++}
++#endif/*CONFIG_AP_MODE*/
++#endif/*CONFIG_CONCURRENT_MODE*/
++
++#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
++void rtw_hal_set_pathb_phase(_adapter *adapter, u8 phase_idx)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(adapter);
++	struct PHY_DM_STRUCT		*pDM_Odm = &pHalData->odmpriv;
++
++	return phydm_pathb_q_matrix_rotate(pDM_Odm, phase_idx);
++}
++#endif
++
++/*
++ * Description: Fill the reserved packets that FW will use to RSVD page.
++ *			Now we just send 4 types packet to rsvd page.
++ *			(1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp.
++ * Input:
++ * finished - FALSE:At the first time we will send all the packets as a large packet to Hw,
++ *		    so we need to set the packet length to total lengh.
++ *	      TRUE: At the second time, we should send the first packet (default:beacon)
++ *		    to Hw again and set the lengh in descriptor to the real beacon lengh.
++ * page_num - The amount of reserved page which driver need.
++ *	      If this is not NULL, this function doesn't real download reserved
++ *	      page, but just count the number of reserved page.
++ *
++ * 2009.10.15 by tynli.
++ * 2017.06.20 modified by Lucas.
++ *
++ * Page Size = 128: 8188e, 8723a/b, 8192c/d,
++ * Page Size = 256: 8192e, 8821a
++ * Page Size = 512: 8812a
++ */
++
++/*#define DBG_DUMP_SET_RSVD_PAGE*/
++static void _rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished, u8 *page_num)
++{
++	PHAL_DATA_TYPE pHalData;
++	struct xmit_frame	*pcmdframe = NULL;
++	struct pkt_attrib	*pattrib;
++	struct xmit_priv	*pxmitpriv;
++	struct pwrctrl_priv *pwrctl;
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	u32	BeaconLength = 0, ProbeRspLength = 0, PSPollLength = 0;
++	u32	NullDataLength = 0, QosNullLength = 0, BTQosNullLength = 0;
++	u32	ProbeReqLength = 0, NullFunctionDataLength = 0;
++	u8	TxDescLen = TXDESC_SIZE, TxDescOffset = TXDESC_OFFSET;
++	u8	TotalPageNum = 0 , CurtPktPageNum = 0 , RsvdPageNum = 0;
++	u8	*ReservedPagePacket;
++	u16	BufIndex = 0;
++	u32	TotalPacketLen = 0, MaxRsvdPageBufSize = 0, PageSize = 0;
++	RSVDPAGE_LOC	RsvdPageLoc;
++	struct registry_priv  *registry_par = &adapter->registrypriv;
++
++#ifdef DBG_FW_DEBUG_MSG_PKT
++	u32	fw_dbg_msg_pkt_len = 0;
++#endif /*DBG_FW_DEBUG_MSG_PKT*/
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++	struct sreset_priv *psrtpriv;
++#endif /* DBG_CONFIG_ERROR_DETECT */
++
++#ifdef CONFIG_MCC_MODE
++	u8 dl_mcc_page = _FAIL;
++#endif /* CONFIG_MCC_MODE */
++	u8 nr_assoc_if;
++
++	_adapter *sta_iface = NULL;
++	_adapter *ap_iface = NULL;
++
++	bool is_wow_mode = _FALSE;
++
++	pHalData = GET_HAL_DATA(adapter);
++#ifdef DBG_CONFIG_ERROR_DETECT
++	psrtpriv = &pHalData->srestpriv;
++#endif
++	pxmitpriv = &adapter->xmitpriv;
++	pwrctl = adapter_to_pwrctl(adapter);
++
++	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&PageSize);
++
++	if (PageSize == 0) {
++		RTW_ERR("[Error]: %s, PageSize is zero!!\n", __func__);
++		return;
++	}
++	nr_assoc_if = _rtw_mi_assoc_if_num(adapter);
++
++	if ((pwrctl->wowlan_mode == _TRUE && pwrctl->wowlan_in_resume == _FALSE) ||
++		pwrctl->wowlan_ap_mode == _TRUE ||
++		pwrctl->wowlan_p2p_mode == _TRUE)
++		is_wow_mode = _TRUE;
++
++	/*page_num for init time to get rsvd page number*/
++	/* Prepare ReservedPagePacket */
++	if (page_num) {
++		ReservedPagePacket = rtw_zmalloc(MAX_CMDBUF_SZ);
++		if (!ReservedPagePacket) {
++			RTW_WARN("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__);
++			*page_num = 0xFF;
++			return;
++		}
++		RTW_INFO(FUNC_ADPT_FMT" Get [ %s ] RsvdPageNUm  ==>\n",
++			FUNC_ADPT_ARG(adapter), (is_wow_mode) ? "WOW" : "NOR");
++
++	} else {
++		if (is_wow_mode)
++			RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE);
++		else
++			RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE);
++
++		RTW_INFO(FUNC_ADPT_FMT" PageSize: %d, [ %s ]-RsvdPageNUm: %d\n",
++			FUNC_ADPT_ARG(adapter), PageSize, (is_wow_mode) ? "WOW" : "NOR", RsvdPageNum);
++
++		MaxRsvdPageBufSize = RsvdPageNum * PageSize;
++		if (MaxRsvdPageBufSize > MAX_CMDBUF_SZ) {
++			RTW_ERR("%s MaxRsvdPageBufSize(%d) is larger than MAX_CMDBUF_SZ(%d)",
++				 __func__, MaxRsvdPageBufSize, MAX_CMDBUF_SZ);
++			rtw_warn_on(1);
++			return;
++		}
++
++		pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv);
++		if (pcmdframe == NULL) {
++			RTW_ERR("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__);
++			return;
++		}
++
++		ReservedPagePacket = pcmdframe->buf_addr;
++	}
++
++	_rtw_memset(&RsvdPageLoc, 0, sizeof(RSVDPAGE_LOC));
++
++	BufIndex = TxDescOffset;
++
++	/*======== beacon content =======*/
++	rtw_hal_construct_beacon(adapter,
++				 &ReservedPagePacket[BufIndex], &BeaconLength);
++
++	/*
++	* When we count the first page size, we need to reserve description size for the RSVD
++	* packet, it will be filled in front of the packet in TXPKTBUF.
++	*/
++	BeaconLength = MAX_BEACON_LEN - TxDescLen;
++	CurtPktPageNum = (u8)PageNum((TxDescLen + BeaconLength), PageSize);
++
++#ifdef CONFIG_FW_HANDLE_TXBCN
++	CurtPktPageNum = CurtPktPageNum * CONFIG_LIMITED_AP_NUM;
++#endif
++	TotalPageNum += CurtPktPageNum;
++
++	BufIndex += (CurtPktPageNum * PageSize);
++
++	RSVD_PAGE_CFG("Beacon", CurtPktPageNum, TotalPageNum, TotalPacketLen);
++
++	/*======== probe response content ========*/
++	if (pwrctl->wowlan_ap_mode == _TRUE) {/*WOW mode*/
++		#ifdef CONFIG_CONCURRENT_MODE
++		if (nr_assoc_if >= 2)
++			RTW_ERR("Not support > 2 net-interface in WOW\n");
++		#endif
++		/* (4) probe response*/
++		RsvdPageLoc.LocProbeRsp = TotalPageNum;
++		rtw_hal_construct_ProbeRsp(
++			adapter, &ReservedPagePacket[BufIndex],
++			&ProbeRspLength,
++			_FALSE);
++		rtw_hal_fill_fake_txdesc(adapter,
++				 &ReservedPagePacket[BufIndex - TxDescLen],
++				 ProbeRspLength, _FALSE, _FALSE, _FALSE);
++
++		CurtPktPageNum = (u8)PageNum(TxDescLen + ProbeRspLength, PageSize);
++		TotalPageNum += CurtPktPageNum;
++		TotalPacketLen = BufIndex + ProbeRspLength;
++		BufIndex += (CurtPktPageNum * PageSize);
++		RSVD_PAGE_CFG("ProbeRsp", CurtPktPageNum, TotalPageNum, TotalPacketLen);
++		goto download_page;
++	}
++
++	/*======== ps-poll content * 1 page ========*/
++	sta_iface = adapter;
++	#ifdef CONFIG_CONCURRENT_MODE
++	if (!MLME_IS_STA(sta_iface) && DEV_STA_LD_NUM(adapter_to_dvobj(sta_iface))) {
++		sta_iface = _rtw_search_sta_iface(adapter);
++		RTW_INFO("get ("ADPT_FMT") to create PS-Poll/Null/QosNull\n", ADPT_ARG(sta_iface));
++	}
++	#endif
++
++	if (MLME_IS_STA(sta_iface) || (nr_assoc_if == 0)) {
++		RsvdPageLoc.LocPsPoll = TotalPageNum;
++		RTW_INFO("LocPsPoll: %d\n", RsvdPageLoc.LocPsPoll);
++		rtw_hal_construct_PSPoll(sta_iface,
++					 &ReservedPagePacket[BufIndex], &PSPollLength);
++		rtw_hal_fill_fake_txdesc(sta_iface,
++					 &ReservedPagePacket[BufIndex - TxDescLen],
++					 PSPollLength, _TRUE, _FALSE, _FALSE);
++
++		CurtPktPageNum = (u8)PageNum((TxDescLen + PSPollLength), PageSize);
++
++		TotalPageNum += CurtPktPageNum;
++
++		BufIndex += (CurtPktPageNum * PageSize);
++		RSVD_PAGE_CFG("PSPoll", CurtPktPageNum, TotalPageNum, TotalPacketLen);
++	}
++
++#ifdef CONFIG_MCC_MODE
++	/*======== MCC * n page ======== */
++	if (MCC_EN(adapter)) {/*Normal mode*/
++		dl_mcc_page = rtw_hal_dl_mcc_fw_rsvd_page(adapter, ReservedPagePacket,
++				&BufIndex, TxDescLen, PageSize, &TotalPageNum, &RsvdPageLoc, page_num);
++	} else {
++		dl_mcc_page = _FAIL;
++	}
++
++	if (dl_mcc_page == _FAIL)
++#endif /* CONFIG_MCC_MODE */
++	{	/*======== null data * 1 page ======== */
++		if (MLME_IS_STA(sta_iface) || (nr_assoc_if == 0)) {
++			RsvdPageLoc.LocNullData = TotalPageNum;
++			RTW_INFO("LocNullData: %d\n", RsvdPageLoc.LocNullData);
++			rtw_hal_construct_NullFunctionData(
++				sta_iface,
++				&ReservedPagePacket[BufIndex],
++				&NullDataLength,
++				_FALSE, 0, 0, _FALSE);
++			rtw_hal_fill_fake_txdesc(sta_iface,
++				 &ReservedPagePacket[BufIndex - TxDescLen],
++				 NullDataLength, _FALSE, _FALSE, _FALSE);
++
++			CurtPktPageNum = (u8)PageNum(TxDescLen + NullDataLength, PageSize);
++
++			TotalPageNum += CurtPktPageNum;
++
++			BufIndex += (CurtPktPageNum * PageSize);
++			RSVD_PAGE_CFG("NullData", CurtPktPageNum, TotalPageNum, TotalPacketLen);
++		}
++	}
++
++	/*======== Qos null data * 1 page ======== */
++	if (pwrctl->wowlan_mode == _FALSE ||
++		pwrctl->wowlan_in_resume == _TRUE) {/*Normal mode*/	
++		if (MLME_IS_STA(sta_iface) || (nr_assoc_if == 0)) {
++			RsvdPageLoc.LocQosNull = TotalPageNum;
++			RTW_INFO("LocQosNull: %d\n", RsvdPageLoc.LocQosNull);
++			rtw_hal_construct_NullFunctionData(sta_iface,
++						&ReservedPagePacket[BufIndex],
++						&QosNullLength,
++						_TRUE, 0, 0, _FALSE);
++			rtw_hal_fill_fake_txdesc(sta_iface,
++					 &ReservedPagePacket[BufIndex - TxDescLen],
++					 QosNullLength, _FALSE, _FALSE, _FALSE);
++
++			CurtPktPageNum = (u8)PageNum(TxDescLen + QosNullLength,
++						     PageSize);
++
++			TotalPageNum += CurtPktPageNum;
++
++			BufIndex += (CurtPktPageNum * PageSize);
++			RSVD_PAGE_CFG("QosNull", CurtPktPageNum, TotalPageNum, TotalPacketLen);
++		}
++	}
++
++#ifdef CONFIG_BT_COEXIST
++	/*======== BT Qos null data * 1 page ======== */
++	if (pwrctl->wowlan_mode == _FALSE ||
++		pwrctl->wowlan_in_resume == _TRUE) {/*Normal mode*/
++
++		ap_iface = adapter;
++		#ifdef CONFIG_CONCURRENT_MODE
++		if (!MLME_IS_AP(ap_iface) && DEV_AP_NUM(adapter_to_dvobj(ap_iface))) {	/*DEV_AP_STARTING_NUM*/
++			ap_iface = _rtw_search_ap_iface(adapter);
++			RTW_INFO("get ("ADPT_FMT") to create BTQoSNull\n", ADPT_ARG(ap_iface));
++		}
++		#endif
++
++		if (MLME_IS_AP(ap_iface) || (nr_assoc_if == 0)) {
++			RsvdPageLoc.LocBTQosNull = TotalPageNum;
++
++			RTW_INFO("LocBTQosNull: %d\n", RsvdPageLoc.LocBTQosNull);
++
++			rtw_hal_construct_NullFunctionData(ap_iface,
++						&ReservedPagePacket[BufIndex],
++						&BTQosNullLength,
++						_TRUE, 0, 0, _FALSE);
++
++			rtw_hal_fill_fake_txdesc(ap_iface,
++					&ReservedPagePacket[BufIndex - TxDescLen],
++					BTQosNullLength, _FALSE, _TRUE, _FALSE);
++
++			CurtPktPageNum = (u8)PageNum(TxDescLen + BTQosNullLength,
++							 PageSize);
++
++			TotalPageNum += CurtPktPageNum;
++			BufIndex += (CurtPktPageNum * PageSize);
++
++			RSVD_PAGE_CFG("BTQosNull", CurtPktPageNum, TotalPageNum, TotalPacketLen);
++		}
++	}
++#endif /* CONFIG_BT_COEXIT */
++
++	TotalPacketLen = BufIndex;
++
++#ifdef DBG_FW_DEBUG_MSG_PKT
++		/*======== FW DEBUG MSG * n page ======== */
++		RsvdPageLoc.loc_fw_dbg_msg_pkt = TotalPageNum;
++		RTW_INFO("loc_fw_dbg_msg_pkt: %d\n", RsvdPageLoc.loc_fw_dbg_msg_pkt);
++		rtw_hal_construct_fw_dbg_msg_pkt(
++			adapter,
++			&ReservedPagePacket[BufIndex],
++			&fw_dbg_msg_pkt_len);
++
++		rtw_hal_fill_fake_txdesc(adapter,
++				 &ReservedPagePacket[BufIndex - TxDescLen],
++				 fw_dbg_msg_pkt_len, _FALSE, _FALSE, _FALSE);
++
++		CurtPktPageNum = (u8)PageNum(TxDescLen + fw_dbg_msg_pkt_len, PageSize);
++
++		if (CurtPktPageNum < 2)
++			CurtPktPageNum = 2; /*Need at least 2 rsvd page*/
++		TotalPageNum += CurtPktPageNum;
++
++		TotalPacketLen = BufIndex + fw_dbg_msg_pkt_len;
++		BufIndex += (CurtPktPageNum * PageSize);
++#endif /*DBG_FW_DEBUG_MSG_PKT*/
++
++#ifdef CONFIG_LPS_PG
++	rtw_lps_pg_set_rsvd_page(adapter, ReservedPagePacket, &BufIndex
++		, TxDescLen, PageSize, &TotalPageNum, is_wow_mode
++		, (sta_iface && MLME_IS_STA(sta_iface) && MLME_IS_ASOC(sta_iface)) ? sta_iface : NULL
++		, page_num ? 1 : 0
++	);
++	TotalPacketLen = BufIndex;
++#endif
++
++#ifdef CONFIG_WOWLAN
++	/*======== WOW * n page ======== */
++	if (pwrctl->wowlan_mode == _TRUE &&
++		pwrctl->wowlan_in_resume == _FALSE &&
++		check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {/*WOW mode*/
++		rtw_hal_set_wow_fw_rsvd_page(adapter, ReservedPagePacket,
++					     BufIndex, TxDescLen, PageSize,
++			     &TotalPageNum, &TotalPacketLen, &RsvdPageLoc);
++	}
++#endif /* CONFIG_WOWLAN */
++
++#ifdef CONFIG_P2P_WOWLAN
++	/*======== P2P WOW * n page ======== */
++	if (_TRUE == pwrctl->wowlan_p2p_mode) {/*WOW mode*/
++		rtw_hal_set_p2p_wow_fw_rsvd_page(adapter, ReservedPagePacket,
++						 BufIndex, TxDescLen, PageSize,
++				 &TotalPageNum, &TotalPacketLen, &RsvdPageLoc);
++	}
++#endif /* CONFIG_P2P_WOWLAN */
++
++	/*Note:  BufIndex already add a TxDescOffset offset in first Beacon page
++	* The "TotalPacketLen" is calculate by BufIndex.
++	* We need to decrease TxDescOffset before doing length check. by yiwei
++	*/
++	TotalPacketLen = TotalPacketLen - TxDescOffset;
++
++download_page:
++	if (page_num) {
++		*page_num = TotalPageNum;
++		rtw_mfree(ReservedPagePacket, MAX_CMDBUF_SZ);
++		ReservedPagePacket = NULL;
++		RTW_INFO(FUNC_ADPT_FMT" Get [ %s ] RsvdPageNUm <==\n",
++			FUNC_ADPT_ARG(adapter), (is_wow_mode) ? "WOW" : "NOR");
++		return;
++	}
++
++	/* RTW_INFO("%s BufIndex(%d), TxDescLen(%d), PageSize(%d)\n",__func__, BufIndex, TxDescLen, PageSize);*/
++	RTW_INFO("%s PageNum(%d), pktlen(%d)\n",
++		 __func__, TotalPageNum, TotalPacketLen);
++
++	if (TotalPacketLen > MaxRsvdPageBufSize) {
++		RTW_ERR("%s : rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\n",
++			 __FUNCTION__, TotalPacketLen, MaxRsvdPageBufSize);
++		rtw_warn_on(1);
++		goto error;
++	} else {
++		/* update attribute */
++		pattrib = &pcmdframe->attrib;
++		update_mgntframe_attrib(adapter, pattrib);
++		pattrib->qsel = QSLT_BEACON;
++		pattrib->pktlen = TotalPacketLen;
++		pattrib->last_txcmdsz = TotalPacketLen;
++#ifdef CONFIG_PCI_HCI
++		dump_mgntframe(adapter, pcmdframe);
++#else
++		dump_mgntframe_and_wait(adapter, pcmdframe, 100);
++#endif
++	}
++
++	RTW_INFO("%s: Set RSVD page location to Fw ,TotalPacketLen(%d), TotalPageNum(%d)\n",
++		 __func__, TotalPacketLen, TotalPageNum);
++#ifdef DBG_DUMP_SET_RSVD_PAGE
++	RTW_INFO(" ==================================================\n");
++	RTW_INFO_DUMP("\n", ReservedPagePacket, TotalPacketLen);
++	RTW_INFO(" ==================================================\n");
++#endif
++
++
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE)
++		|| MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)){
++		rtw_hal_set_FwRsvdPage_cmd(adapter, &RsvdPageLoc);
++#ifdef DBG_FW_DEBUG_MSG_PKT
++		rtw_hal_set_fw_dbg_msg_pkt_rsvd_page_cmd(adapter, &RsvdPageLoc);
++#endif /*DBG_FW_DEBUG_MSG_PKT*/
++#ifdef CONFIG_WOWLAN
++		if (pwrctl->wowlan_mode == _TRUE &&
++			pwrctl->wowlan_in_resume == _FALSE)
++			rtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc);
++#endif /* CONFIG_WOWLAN */
++#ifdef CONFIG_AP_WOWLAN
++		if (pwrctl->wowlan_ap_mode == _TRUE)
++			rtw_hal_set_ap_rsvdpage_loc_cmd(adapter, &RsvdPageLoc);
++#endif /* CONFIG_AP_WOWLAN */
++	} else if (pwrctl->wowlan_pno_enable) {
++#ifdef CONFIG_PNO_SUPPORT
++		rtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc);
++		if (pwrctl->wowlan_in_resume)
++			rtw_hal_set_scan_offload_info_cmd(adapter,
++							  &RsvdPageLoc, 0);
++		else
++			rtw_hal_set_scan_offload_info_cmd(adapter,
++							  &RsvdPageLoc, 1);
++#endif /* CONFIG_PNO_SUPPORT */
++	}
++
++#ifdef CONFIG_P2P_WOWLAN
++	if (_TRUE == pwrctl->wowlan_p2p_mode)
++		rtw_hal_set_FwP2PRsvdPage_cmd(adapter, &RsvdPageLoc);
++#endif /* CONFIG_P2P_WOWLAN */
++
++	return;
++error:
++	rtw_free_xmitframe(pxmitpriv, pcmdframe);
++}
++
++void rtw_hal_set_fw_rsvd_page(struct _ADAPTER *adapter, bool finished)
++{
++	if (finished)
++		rtw_mi_tx_beacon_hdl(adapter);
++	else
++		_rtw_hal_set_fw_rsvd_page(adapter, finished, NULL);
++}
++
++/**
++ * rtw_hal_get_rsvd_page_num() - Get needed reserved page number
++ * @adapter:	struct _ADAPTER*
++ *
++ * Caculate needed reserved page number.
++ * In different state would get different number, for example normal mode and
++ * WOW mode would need different reserved page size.
++ *
++ * Return the number of reserved page which driver need.
++ */
++u8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter)
++{
++	u8 num = 0;
++
++
++	_rtw_hal_set_fw_rsvd_page(adapter, _FALSE, &num);
++
++	return num;
++}
++
++#ifndef CONFIG_HAS_HW_VAR_BCN_FUNC
++static void hw_var_set_bcn_func(_adapter *adapter, u8 enable)
++{
++	u32 bcn_ctrl_reg;
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (adapter->hw_port == HW_PORT1)
++		bcn_ctrl_reg = REG_BCN_CTRL_1;
++	else
++#endif
++		bcn_ctrl_reg = REG_BCN_CTRL;
++
++	if (enable)
++		rtw_write8(adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
++	else {
++		u8 val8;
++
++		val8 = rtw_read8(adapter, bcn_ctrl_reg);
++		val8 &= ~(EN_BCN_FUNCTION | EN_TXBCN_RPT);
++
++#ifdef CONFIG_BT_COEXIST
++		if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist == 1) {
++			/* Always enable port0 beacon function for PSTDMA */
++			if (REG_BCN_CTRL == bcn_ctrl_reg)
++				val8 |= EN_BCN_FUNCTION;
++		}
++#endif
++
++		rtw_write8(adapter, bcn_ctrl_reg, val8);
++	}
++
++#ifdef CONFIG_RTL8192F
++	if (IS_HARDWARE_TYPE_8192F(adapter)) {
++		u16 val16, val16_ori;
++
++		val16_ori = val16 = rtw_read16(adapter, REG_WLAN_ACT_MASK_CTRL_1);
++
++		#ifdef CONFIG_CONCURRENT_MODE
++		if (adapter->hw_port == HW_PORT1) {
++			if (enable)
++				val16 |= EN_PORT_1_FUNCTION;
++			else
++				val16 &= ~EN_PORT_1_FUNCTION;
++		} else
++		#endif
++		{
++			if (enable)
++				val16 |= EN_PORT_0_FUNCTION;
++			else
++				val16 &= ~EN_PORT_0_FUNCTION;
++
++			#ifdef CONFIG_BT_COEXIST
++			if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist == 1)
++				val16 |= EN_PORT_0_FUNCTION;
++			#endif
++		}
++
++		if (val16 != val16_ori)
++			rtw_write16(adapter, REG_WLAN_ACT_MASK_CTRL_1,  val16);
++	}
++#endif
++}
++#endif
++
++#ifndef CONFIG_HAS_HW_VAR_MLME_DISCONNECT
++static void hw_var_set_mlme_disconnect(_adapter *adapter)
++{
++	u8 val8;
++
++	/* reject all data frames */
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE)
++#endif
++		rtw_write16(adapter, REG_RXFLTMAP2, 0x0000);
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (adapter->hw_port == HW_PORT1) {
++		/* reset TSF1 */
++		rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(1));
++
++		/* disable update TSF1 */
++		rtw_iface_disable_tsf_update(adapter);
++
++		if (!IS_HARDWARE_TYPE_8723D(adapter)
++			&& !IS_HARDWARE_TYPE_8192F(adapter)
++			&& !IS_HARDWARE_TYPE_8710B(adapter)
++		) {
++			/* disable Port1's beacon function */
++			val8 = rtw_read8(adapter, REG_BCN_CTRL_1);
++			val8 &= ~EN_BCN_FUNCTION;
++			rtw_write8(adapter, REG_BCN_CTRL_1, val8);
++		}
++	} else
++#endif
++	{
++		/* reset TSF */
++		rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(0));
++
++		/* disable update TSF */
++		rtw_iface_disable_tsf_update(adapter);
++	}
++}
++#endif
++
++static void hw_var_set_mlme_sitesurvey(_adapter *adapter, u8 enable)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	u16 value_rxfltmap2;
++
++#ifdef DBG_IFACE_STATUS
++	DBG_IFACE_STATUS_DUMP(adapter);
++#endif
++
++#ifdef CONFIG_FIND_BEST_CHANNEL
++	/* Receive all data frames */
++	value_rxfltmap2 = 0xFFFF;
++#else
++	/* not to receive data frame */
++	value_rxfltmap2 = 0;
++#endif
++
++	if (enable) { /* under sitesurvey */
++		/*
++		* 1. configure REG_RXFLTMAP2
++		* 2. disable TSF update &  buddy TSF update to avoid updating wrong TSF due to clear RCR_CBSSID_BCN
++		* 3. config RCR to receive different BSSID BCN or probe rsp
++		*/
++		rtw_write16(adapter, REG_RXFLTMAP2, value_rxfltmap2);
++
++		rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_ENTER);
++
++		/* Save orignal RRSR setting, only 8812 set RRSR after set ch/bw/band */
++		#if defined (CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
++		hal_data->RegRRSR = rtw_read32(adapter, REG_RRSR);
++		hal_data->RegRRSR &= 0x000FFFFF;
++		#endif
++
++		#if defined(CONFIG_BEAMFORMING) && (defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A))
++		if (IS_8812_SERIES(hal_data->version_id) || IS_8821_SERIES(hal_data->version_id)) {
++			/* set 718[1:0]=2'b00 to avoid BF scan hang */
++			hal_data->backup_snd_ptcl_ctrl = rtw_read8(adapter, REG_SND_PTCL_CTRL_8812A);
++			rtw_write8(adapter, REG_SND_PTCL_CTRL_8812A, (hal_data->backup_snd_ptcl_ctrl & 0xfc));
++		}
++		#endif
++
++		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))
++			StopTxBeacon(adapter);
++	} else { /* sitesurvey done */
++		/*
++		* 1. enable rx data frame
++		* 2. config RCR not to receive different BSSID BCN or probe rsp
++		* 3. doesn't enable TSF update &  buddy TSF right now to avoid HW conflict
++		*	 so, we enable TSF update when rx first BCN after sitesurvey done
++		*/
++		if (rtw_mi_check_fwstate(adapter, WIFI_ASOC_STATE | WIFI_AP_STATE | WIFI_MESH_STATE)) {
++			/* enable to rx data frame */
++			rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);
++		}
++
++		rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_DONE);
++
++		/* Restore orignal RRSR setting,only 8812 set RRSR after set ch/bw/band */
++		#if defined (CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
++			rtw_phydm_set_rrsr(adapter, hal_data->RegRRSR, TRUE);
++		#endif
++
++		#if defined(CONFIG_BEAMFORMING) && (defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A))
++		if (IS_8812_SERIES(hal_data->version_id) || IS_8821_SERIES(hal_data->version_id)) {
++			/* Restore orignal 0x718 setting*/
++			rtw_write8(adapter, REG_SND_PTCL_CTRL_8812A, hal_data->backup_snd_ptcl_ctrl);
++		}
++		#endif
++
++		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {
++			ResumeTxBeacon(adapter);
++			rtw_mi_tx_beacon_hdl(adapter);
++		}
++	}
++}
++
++#ifndef CONFIG_HAS_HW_VAR_MLME_JOIN
++static void hw_var_set_mlme_join(_adapter *adapter, u8 type)
++{
++	u8 val8;
++	u16 val16;
++	u32 val32;
++	u8 RetryLimit = RL_VAL_STA;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (type == 0) {
++		/* prepare to join */
++		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))
++			StopTxBeacon(adapter);
++
++		/* enable to rx data frame.Accept all data frame */
++		rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);
++
++		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
++			RetryLimit = (hal_data->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA;
++		else /* Ad-hoc Mode */
++			RetryLimit = RL_VAL_AP;
++
++		rtw_iface_enable_tsf_update(adapter);
++
++	} else if (type == 1) {
++		/* joinbss_event call back when join res < 0 */
++		if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE)
++			rtw_write16(adapter, REG_RXFLTMAP2, 0x00);
++
++		rtw_iface_disable_tsf_update(adapter);
++
++		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {
++			ResumeTxBeacon(adapter);
++
++			/* reset TSF 1/2 after ResumeTxBeacon */
++			rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(1) | BIT(0));
++		}
++
++	} else if (type == 2) {
++		/* sta add event call back */
++		if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
++			/* fixed beacon issue for 8191su........... */
++			rtw_write8(adapter, 0x542 , 0x02);
++			RetryLimit = RL_VAL_AP;
++		}
++
++		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {
++			ResumeTxBeacon(adapter);
++
++			/* reset TSF 1/2 after ResumeTxBeacon */
++			rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(1) | BIT(0));
++		}
++	}
++
++	val16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit);
++	rtw_write16(adapter, REG_RETRY_LIMIT, val16);
++#else /* !CONFIG_CONCURRENT_MODE */
++	if (type == 0) { /* prepare to join */
++		/* enable to rx data frame.Accept all data frame */
++		rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);
++
++		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
++			RetryLimit = (hal_data->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA;
++		else /* Ad-hoc Mode */
++			RetryLimit = RL_VAL_AP;
++
++		rtw_iface_enable_tsf_update(adapter);
++
++	} else if (type == 1) { /* joinbss_event call back when join res < 0 */
++		rtw_write16(adapter, REG_RXFLTMAP2, 0x00);
++
++		rtw_iface_disable_tsf_update(adapter);
++
++	} else if (type == 2) { /* sta add event call back */
++		if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE))
++			RetryLimit = RL_VAL_AP;
++	}
++
++	val16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit);
++	rtw_write16(adapter, REG_RETRY_LIMIT, val16);
++#endif /* !CONFIG_CONCURRENT_MODE */
++}
++#endif
++
++#ifdef CONFIG_TSF_RESET_OFFLOAD
++static int rtw_hal_h2c_reset_tsf(_adapter *adapter, u8 reset_port)
++{
++	u8 buf[2];
++	int ret;
++
++	if (reset_port == HW_PORT0) {
++		buf[0] = 0x1;
++		buf[1] = 0;
++	} else {
++		buf[0] = 0x0;
++		buf[1] = 0x1;
++	}
++
++	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_RESET_TSF, 2, buf);
++
++	return ret;
++}
++
++int rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port)
++{
++	u8 reset_cnt_before = 0, reset_cnt_after = 0, loop_cnt = 0;
++	u32 reg_reset_tsf_cnt = (reset_port == HW_PORT0) ?
++				REG_FW_RESET_TSF_CNT_0 : REG_FW_RESET_TSF_CNT_1;
++	int ret;
++
++	/* site survey will cause reset tsf fail */
++	rtw_mi_buddy_scan_abort(adapter, _FALSE);
++	reset_cnt_after = reset_cnt_before = rtw_read8(adapter, reg_reset_tsf_cnt);
++	ret = rtw_hal_h2c_reset_tsf(adapter, reset_port);
++	if (ret != _SUCCESS)
++		return ret;
++
++	while ((reset_cnt_after == reset_cnt_before) && (loop_cnt < 10)) {
++		rtw_msleep_os(100);
++		loop_cnt++;
++		reset_cnt_after = rtw_read8(adapter, reg_reset_tsf_cnt);
++	}
++
++	return (loop_cnt >= 10) ? _FAIL : _SUCCESS;
++}
++#endif /* CONFIG_TSF_RESET_OFFLOAD */
++
++#ifndef CONFIG_HAS_HW_VAR_CORRECT_TSF
++#ifdef CONFIG_HW_P0_TSF_SYNC
++#ifdef CONFIG_CONCURRENT_MODE
++static void hw_port0_tsf_sync_sel(_adapter *adapter, u8 benable, u8 hw_port, u16 tr_offset)
++{
++	u8 val8;
++	u8 client_id = 0;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++#ifdef CONFIG_MCC_MODE
++	if (MCC_EN(adapter) && (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))) {
++		RTW_INFO("[MCC] do not set HW TSF sync\n");
++		return;
++	}
++#endif
++	/* check if port0 is already synced */
++	if (benable && dvobj->p0_tsf.sync_port != MAX_HW_PORT && dvobj->p0_tsf.sync_port == hw_port) {
++		RTW_WARN(FUNC_ADPT_FMT ": port0 already enable TSF sync(%d)\n",
++			FUNC_ADPT_ARG(adapter), dvobj->p0_tsf.sync_port);
++		return;
++	}
++
++	/* check if port0 already disable sync */
++	if (!benable && dvobj->p0_tsf.sync_port == MAX_HW_PORT) {
++		RTW_WARN(FUNC_ADPT_FMT ": port0 already disable TSF sync\n", FUNC_ADPT_ARG(adapter));
++		return;
++	}
++
++	/* check if port0 sync to port0 */
++	if (benable && hw_port == HW_PORT0) {
++		RTW_ERR(FUNC_ADPT_FMT ": hw_port is port0 under enable\n", FUNC_ADPT_ARG(adapter));
++		rtw_warn_on(1);
++		return;
++	}
++
++	/*0x5B4 [6:4] :SYNC_CLI_SEL - The selector for the CLINT port of sync tsft source for port 0*/
++	/*	Bit[5:4] : 0 for clint0, 1 for clint1, 2 for clint2, 3 for clint3.
++		Bit6 : 1= enable sync to port 0. 0=disable sync to port 0.*/
++
++	val8 = rtw_read8(adapter, REG_TIMER0_SRC_SEL);
++
++	if (benable) {
++		/*Disable Port0's beacon function*/
++		rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL) & ~BIT_EN_BCN_FUNCTION);
++
++		/*Reg 0x518[15:0]: TSFTR_SYN_OFFSET*/
++		if (tr_offset)
++			rtw_write16(adapter, REG_TSFTR_SYN_OFFSET, tr_offset);
++
++		/*reg 0x577[6]=1*/	/*auto sync by tbtt*/
++		rtw_write8(adapter, REG_MISC_CTRL, rtw_read8(adapter, REG_MISC_CTRL) | BIT_AUTO_SYNC_BY_TBTT);
++
++		if (HW_PORT1 == hw_port)
++			client_id = 0;
++		else if (HW_PORT2 == hw_port)
++			client_id = 1;
++		else if (HW_PORT3 == hw_port)
++			client_id = 2;
++		else if (HW_PORT4 == hw_port)
++			client_id = 3;
++
++		val8 &= 0x8F;
++		val8 |= (BIT(6) | (client_id << 4));
++
++		dvobj->p0_tsf.sync_port = hw_port;
++		dvobj->p0_tsf.offset = tr_offset;
++		rtw_write8(adapter, REG_TIMER0_SRC_SEL, val8);
++
++		/*Enable Port0's beacon function*/
++		rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL)  | BIT_EN_BCN_FUNCTION);
++		RTW_INFO("%s Port_%d TSF sync to P0, timer offset :%d\n", __func__, hw_port, tr_offset);
++	} else {
++		val8 &= ~BIT(6);
++
++		dvobj->p0_tsf.sync_port = MAX_HW_PORT;
++		dvobj->p0_tsf.offset = 0;
++		rtw_write8(adapter, REG_TIMER0_SRC_SEL, val8);
++		RTW_INFO("%s P0 TSF sync disable\n", __func__);
++	}
++}
++static _adapter * _search_ld_sta(_adapter *adapter, u8 include_self)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	u8 i;
++	_adapter *iface = NULL;
++
++	if (rtw_mi_get_assoced_sta_num(adapter) == 0) {
++		RTW_ERR("STA_LD_NUM == 0\n");
++		rtw_warn_on(1);
++	}
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (!iface)
++			continue;
++		if (include_self == _FALSE && adapter == iface)
++			continue;
++		if (is_client_associated_to_ap(iface))
++			break;
++	}
++	if (iface)
++		RTW_INFO("search STA iface -"ADPT_FMT"\n", ADPT_ARG(iface));
++	return iface;
++}
++#endif /*CONFIG_CONCURRENT_MODE*/
++/*Correct port0's TSF*/
++/*#define DBG_P0_TSF_SYNC*/
++void hw_var_set_correct_tsf(PADAPTER adapter, u8 mlme_state)
++{
++#ifdef CONFIG_CONCURRENT_MODE
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++	_adapter *sta_if = NULL;
++	u8 hw_port;
++
++	RTW_INFO(FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(adapter));
++	#ifdef DBG_P0_TSF_SYNC
++	RTW_INFO("[TSF_SYNC] AP_NUM = %d\n", rtw_mi_get_ap_num(adapter));
++	RTW_INFO("[TSF_SYNC] MESH_NUM = %d\n", rtw_mi_get_mesh_num(adapter));
++	RTW_INFO("[TSF_SYNC] LD_STA_NUM = %d\n", rtw_mi_get_assoced_sta_num(adapter));
++	if (dvobj->p0_tsf.sync_port == MAX_HW_PORT)
++		RTW_INFO("[TSF_SYNC] org p0 sync port = N/A\n");
++	else
++		RTW_INFO("[TSF_SYNC] org p0 sync port = %d\n", dvobj->p0_tsf.sync_port);
++	RTW_INFO("[TSF_SYNC] timer offset = %d\n", dvobj->p0_tsf.offset);
++	#endif
++	switch (mlme_state) {
++		case MLME_STA_CONNECTED :
++			{
++				hw_port = rtw_hal_get_port(adapter);
++
++				if (!MLME_IS_STA(adapter)) {
++					RTW_ERR("STA CON state,but iface("ADPT_FMT") is not STA\n", ADPT_ARG(adapter));
++					rtw_warn_on(1);
++				}
++
++				if ((dvobj->p0_tsf.sync_port != MAX_HW_PORT) && (hw_port == HW_PORT0)) {
++					RTW_ERR(ADPT_FMT" is STA with P0 connected => DIS P0_TSF_SYNC\n", ADPT_ARG(adapter));
++					rtw_warn_on(1);
++					hw_port0_tsf_sync_sel(adapter, _FALSE, 0, 0);
++				}
++
++				if ((dvobj->p0_tsf.sync_port == MAX_HW_PORT) &&
++					(rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))) {
++					hw_port0_tsf_sync_sel(adapter, _TRUE, hw_port, 50);/*timer offset 50ms*/
++					#ifdef DBG_P0_TSF_SYNC
++					RTW_INFO("[TSF_SYNC] STA_LINKED => EN P0_TSF_SYNC\n");
++					#endif
++				}
++			}
++			break;
++		case MLME_STA_DISCONNECTED :
++			{
++				hw_port = rtw_hal_get_port(adapter);
++
++				if (!MLME_IS_STA(adapter)) {
++					RTW_ERR("STA DIS_CON state,but iface("ADPT_FMT") is not STA\n", ADPT_ARG(adapter));
++					rtw_warn_on(1);
++				}
++
++				if (dvobj->p0_tsf.sync_port == hw_port) {
++					if (rtw_mi_get_assoced_sta_num(adapter) >= 2) {
++						/* search next appropriate sta*/
++						sta_if = _search_ld_sta(adapter, _FALSE);
++						if (sta_if) {
++							hw_port = rtw_hal_get_port(sta_if);
++							hw_port0_tsf_sync_sel(adapter, _TRUE, hw_port, 50);/*timer offset 50ms*/
++							#ifdef DBG_P0_TSF_SYNC
++							RTW_INFO("[TSF_SYNC] STA_DIS_CON => CHANGE P0_TSF_SYNC\n");
++							#endif
++						}
++					} else if (rtw_mi_get_assoced_sta_num(adapter) == 1) {
++						hw_port0_tsf_sync_sel(adapter, _FALSE, 0, 0);
++						#ifdef DBG_P0_TSF_SYNC
++						RTW_INFO("[TSF_SYNC] STA_DIS_CON => DIS P0_TSF_SYNC\n");
++						#endif
++					}
++				}
++			}
++			break;
++		case MLME_AP_STARTED :
++		case MLME_MESH_STARTED :
++			{
++				if (!(MLME_IS_AP(adapter) || MLME_IS_MESH(adapter))) {
++					RTW_ERR("AP START state,but iface("ADPT_FMT") is not AP\n", ADPT_ARG(adapter));
++					rtw_warn_on(1);
++				}
++
++				if ((dvobj->p0_tsf.sync_port == MAX_HW_PORT) &&
++					rtw_mi_get_assoced_sta_num(adapter)) {
++					/* get port of sta */
++					sta_if = _search_ld_sta(adapter, _FALSE);
++					if (sta_if) {
++						hw_port = rtw_hal_get_port(sta_if);
++						hw_port0_tsf_sync_sel(adapter, _TRUE, hw_port, 50);/*timer offset 50ms*/
++						#ifdef DBG_P0_TSF_SYNC
++						RTW_INFO("[TSF_SYNC] AP_START => EN P0_TSF_SYNC\n");
++						#endif
++					}
++				}
++			}
++			break;
++		case MLME_AP_STOPPED :
++		case MLME_MESH_STOPPED :
++			{
++				if (!(MLME_IS_AP(adapter) || MLME_IS_MESH(adapter))) {
++					RTW_ERR("AP START state,but iface("ADPT_FMT") is not AP\n", ADPT_ARG(adapter));
++					rtw_warn_on(1);
++				}
++				/*stop ap mode*/
++				if ((rtw_mi_get_ap_num(adapter) + rtw_mi_get_mesh_num(adapter) == 1) &&
++					(dvobj->p0_tsf.sync_port != MAX_HW_PORT)) {
++					hw_port0_tsf_sync_sel(adapter, _FALSE, 0, 0);
++					#ifdef DBG_P0_TSF_SYNC
++					RTW_INFO("[TSF_SYNC] AP_STOP => DIS P0_TSF_SYNC\n");
++					#endif
++				}
++			}
++			break;
++		default :
++			RTW_ERR(FUNC_ADPT_FMT" unknow state(0x%02x)\n", FUNC_ADPT_ARG(adapter), mlme_state);
++			break;
++	}
++
++	/*#ifdef DBG_P0_TSF_SYNC*/
++	#if 1
++	if (dvobj->p0_tsf.sync_port == MAX_HW_PORT)
++		RTW_INFO("[TSF_SYNC] p0 sync port = N/A\n");
++	else
++		RTW_INFO("[TSF_SYNC] p0 sync port = %d\n", dvobj->p0_tsf.sync_port);
++	RTW_INFO("[TSF_SYNC] timer offset = %d\n", dvobj->p0_tsf.offset);
++	#endif
++#endif /*CONFIG_CONCURRENT_MODE*/
++}
++
++#else /*! CONFIG_HW_P0_TSF_SYNC*/
++
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++static void hw_var_set_correct_tsf(_adapter *adapter, u8 mlme_state)
++{
++	/*do nothing*/
++}
++#else /* !CONFIG_MI_WITH_MBSSID_CAM*/
++static void rtw_hal_correct_tsf(_adapter *padapter, u8 hw_port, u64 tsf)
++{
++	if (hw_port == HW_PORT0) {
++		/*disable related TSF function*/
++		rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) & (~EN_BCN_FUNCTION));
++#if defined(CONFIG_RTL8192F)
++		rtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter,
++					REG_WLAN_ACT_MASK_CTRL_1) & ~EN_PORT_0_FUNCTION);
++#endif
++
++		rtw_write32(padapter, REG_TSFTR, tsf);
++		rtw_write32(padapter, REG_TSFTR + 4, tsf >> 32);
++
++		/*enable related TSF function*/
++		rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) | EN_BCN_FUNCTION);
++#if defined(CONFIG_RTL8192F)
++		rtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter,
++					REG_WLAN_ACT_MASK_CTRL_1) | EN_PORT_0_FUNCTION);
++#endif
++	} else if (hw_port == HW_PORT1) {
++		/*disable related TSF function*/
++		rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) & (~EN_BCN_FUNCTION));
++#if defined(CONFIG_RTL8192F)
++		rtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter,
++					REG_WLAN_ACT_MASK_CTRL_1) & ~EN_PORT_1_FUNCTION);
++#endif
++
++		rtw_write32(padapter, REG_TSFTR1, tsf);
++		rtw_write32(padapter, REG_TSFTR1 + 4, tsf >> 32);
++
++		/*enable related TSF function*/
++		rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) | EN_BCN_FUNCTION);
++#if defined(CONFIG_RTL8192F)
++		rtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter,
++					REG_WLAN_ACT_MASK_CTRL_1) | EN_PORT_1_FUNCTION);
++#endif
++	} else
++		RTW_INFO("%s-[WARN] "ADPT_FMT" invalid hw_port:%d\n", __func__, ADPT_ARG(padapter), hw_port);
++}
++static void hw_var_set_correct_tsf(_adapter *adapter, u8 mlme_state)
++{
++	u64 tsf;
++	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++	struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info);
++
++	tsf = mlmeext->TSFValue - rtw_modular64(mlmeext->TSFValue, (mlmeinfo->bcn_interval * 1024)) - 1024; /*us*/
++
++	if ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE
++		|| (mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)
++		StopTxBeacon(adapter);
++
++	rtw_hal_correct_tsf(adapter, adapter->hw_port, tsf);
++
++#ifdef CONFIG_CONCURRENT_MODE
++	/* Update buddy port's TSF if it is SoftAP/Mesh for beacon TX issue! */
++	if ((mlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE
++		&& (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))
++	) {
++		struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++		int i;
++		_adapter *iface;
++
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			iface = dvobj->padapters[i];
++			if (!iface)
++				continue;
++			if (iface == adapter)
++				continue;
++
++			if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))
++				&& check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE
++			) {
++				rtw_hal_correct_tsf(iface, iface->hw_port, tsf);
++				#ifdef CONFIG_TSF_RESET_OFFLOAD
++				if (rtw_hal_reset_tsf(iface, iface->hw_port) == _FAIL)
++					RTW_INFO("%s-[ERROR] "ADPT_FMT" Reset port%d TSF fail\n"
++						, __func__, ADPT_ARG(iface), iface->hw_port);
++				#endif	/* CONFIG_TSF_RESET_OFFLOAD*/
++			}
++		}
++	}
++#endif /* CONFIG_CONCURRENT_MODE */
++	if ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE
++		|| (mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)
++		ResumeTxBeacon(adapter);
++}
++#endif /*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/
++#endif /*#ifdef CONFIG_HW_P0_TSF_SYNC*/
++#endif /*#ifndef CONFIG_HAS_HW_VAR_CORRECT_TSF*/
++
++u64 rtw_hal_get_tsftr_by_port(_adapter *adapter, u8 port)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	u64 tsftr = 0;
++
++	if (port >= hal_spec->port_num) {
++		RTW_ERR("%s invalid port(%d) \n", __func__, port);
++		goto exit;
++	}
++
++	switch (rtw_get_chip_type(adapter)) {
++#if defined(CONFIG_RTL8814B)
++	case RTL8814B:
++	{
++		u8 val8;
++
++		/* 0x1500[6:4] - BIT_BCN_TIMER_SEL_FWRD_V1 */
++		val8 = rtw_read8(adapter, REG_PORT_CTRL_SEL);
++		val8 &= ~0x70;
++		val8 |= port << 4;
++		rtw_write8(adapter, REG_PORT_CTRL_SEL, val8);
++
++		tsftr = rtw_read32(adapter, REG_TSFTR_HIGH);
++		tsftr = tsftr << 32;
++		tsftr |= rtw_read32(adapter, REG_TSFTR_LOW);
++
++		break;
++	}
++#endif
++#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
++	case RTL8814A:
++	case RTL8822B:
++	case RTL8821C:
++	case RTL8822C:		
++	{
++		u8 val8;
++
++		/* 0x554[30:28] - BIT_BCN_TIMER_SEL_FWRD */
++		val8 = rtw_read8(adapter, REG_MBSSID_BCN_SPACE + 3);
++		val8 &= 0x8F;
++		val8 |= port << 4;
++		rtw_write8(adapter, REG_MBSSID_BCN_SPACE + 3, val8);
++
++		tsftr = rtw_read32(adapter, REG_TSFTR + 4);
++		tsftr = tsftr << 32;
++		tsftr |= rtw_read32(adapter, REG_TSFTR);
++
++		break;
++	}
++#endif
++#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) \
++		|| defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8192F) \
++		|| defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8723D) \
++		|| defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) \
++		|| defined(CONFIG_RTL8710B)
++	case RTL8188E:
++	case RTL8188F:
++	case RTL8188GTV:
++	case RTL8192E:
++	case RTL8192F:
++	case RTL8723B:
++	case RTL8703B:
++	case RTL8723D:
++	case RTL8812:
++	case RTL8821:
++	case RTL8710B:
++	{
++		u32 addr;
++
++		if (port == HW_PORT0)
++			addr = REG_TSFTR;
++		else if (port == HW_PORT1)
++			addr = REG_TSFTR1;
++		else {
++			RTW_ERR("%s unknown port(%d) \n", __func__, port);
++			goto exit;
++		}
++
++		tsftr = rtw_read32(adapter, addr + 4);
++		tsftr = tsftr << 32;
++		tsftr |= rtw_read32(adapter, addr);
++
++		break;
++	}
++#endif
++	default:
++		RTW_ERR("%s unknow chip type\n", __func__);
++	}
++
++exit:
++	return tsftr;
++}
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_TDLS_CH_SW
++s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode)
++{
++	PHAL_DATA_TYPE	pHalData =  GET_HAL_DATA(padapter);
++	u8 ch_sw_h2c_buf[4] = {0x00, 0x00, 0x00, 0x00};
++
++
++	SET_H2CCMD_CH_SW_OPER_OFFLOAD_CH_NUM(ch_sw_h2c_buf, channel);
++	SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_MODE(ch_sw_h2c_buf, bwmode);
++	switch (bwmode) {
++	case CHANNEL_WIDTH_40:
++		SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_40M_SC(ch_sw_h2c_buf, channel_offset);
++		break;
++	case CHANNEL_WIDTH_80:
++		SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_80M_SC(ch_sw_h2c_buf, channel_offset);
++		break;
++	case CHANNEL_WIDTH_20:
++	default:
++		break;
++	}
++	SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(ch_sw_h2c_buf, pHalData->rfe_type);
++
++	return rtw_hal_fill_h2c_cmd(padapter, H2C_CHNL_SWITCH_OPER_OFFLOAD, sizeof(ch_sw_h2c_buf), ch_sw_h2c_buf);
++}
++#endif
++#endif
++
++#ifdef CONFIG_WMMPS_STA
++void rtw_hal_update_uapsd_tid(_adapter *adapter)
++{
++	struct mlme_priv		*pmlmepriv = &adapter->mlmepriv;
++	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
++
++	/* write complement of pqospriv->uapsd_tid to mac register 0x693 because 
++	    it's designed  for "0" represents "enable" and "1" represents "disable" */
++	rtw_write8(adapter, REG_WMMPS_UAPSD_TID, (u8)(~pqospriv->uapsd_tid));
++}
++#endif /* CONFIG_WMMPS_STA */
++
++#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
++/* For multi-port support, driver needs to inform the port ID to FW for btc operations */
++s32 rtw_hal_set_wifi_btc_port_id_cmd(_adapter *adapter)
++{
++	u8 h2c_buf[H2C_BTC_WL_PORT_ID_LEN] = {0};
++	u8 hw_port = rtw_hal_get_port(adapter);
++
++	SET_H2CCMD_BTC_WL_PORT_ID(h2c_buf, hw_port);
++	RTW_INFO("%s ("ADPT_FMT") - hw_port :%d\n", __func__, ADPT_ARG(adapter), hw_port);
++	return rtw_hal_fill_h2c_cmd(adapter, H2C_BTC_WL_PORT_ID, H2C_BTC_WL_PORT_ID_LEN, h2c_buf);
++}
++#endif
++
++#define LPS_ACTIVE_TIMEOUT	50 /*number of times*/
++void rtw_lps_state_chk(_adapter *adapter, u8 ps_mode)
++{
++	struct pwrctrl_priv 		*pwrpriv = adapter_to_pwrctl(adapter);
++	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct sta_priv		*pstapriv = &adapter->stapriv;
++	struct sta_info		*psta = NULL;
++	u8 ps_ready = _FALSE;
++	s8 leave_wait_count = LPS_ACTIVE_TIMEOUT;
++
++	if (ps_mode == PS_MODE_ACTIVE) {
++#ifdef CONFIG_LPS_ACK
++		if (rtw_sctx_wait(&pwrpriv->lps_ack_sctx, __func__)) {
++			if (pwrpriv->lps_ack_status > 0) {
++				psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
++				if (psta != NULL) {
++					if(issue_nulldata(adapter, psta->cmn.mac_addr, PS_MODE_ACTIVE, 3, 1) == _FAIL)
++						RTW_INFO(FUNC_ADPT_FMT" LPS state sync not yet finished.\n", FUNC_ADPT_ARG(adapter));
++				}
++			}
++		} else {
++			RTW_WARN("LPS sctx query timeout, operation abort!!\n");
++			return;
++		}
++		pwrpriv->lps_ack_status = -1;
++#else
++		do {
++			if ((rtw_read8(adapter, REG_TCR) & BIT_PWRBIT_OW_EN) == 0) {
++				ps_ready = _TRUE;
++				break;
++			}
++			rtw_msleep_os(1);
++		} while (leave_wait_count--);
++
++		if (ps_ready == _FALSE) {
++			RTW_WARN(FUNC_ADPT_FMT" Power Bit Control is still in HW!\n", FUNC_ADPT_ARG(adapter));
++			return;
++		}
++#endif /* CONFIG_LPS_ACK */
++		}
++	}
++
++void rtw_var_set_basic_rate(PADAPTER padapter, u8 *val) {
++
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++	struct mlme_ext_info *mlmext_info = &padapter->mlmeextpriv.mlmext_info;
++	u16 input_b = 0, masked = 0, ioted = 0, BrateCfg = 0;
++	u16 rrsr_2g_force_mask = RRSR_CCK_RATES;
++	u16 rrsr_2g_allow_mask = (RRSR_24M | RRSR_12M | RRSR_6M | RRSR_CCK_RATES);
++	#if CONFIG_IEEE80211_BAND_5GHZ
++	u16 rrsr_5g_force_mask = (RRSR_6M);
++	u16 rrsr_5g_allow_mask = (RRSR_OFDM_RATES);
++	#endif
++	u32 temp_RRSR;
++
++	HalSetBrateCfg(padapter, val, &BrateCfg);
++	input_b = BrateCfg;
++
++	/* apply force and allow mask */
++	#if CONFIG_IEEE80211_BAND_5GHZ
++	if (pHalData->current_band_type != BAND_ON_2_4G) {
++		BrateCfg |= rrsr_5g_force_mask;
++		BrateCfg &= rrsr_5g_allow_mask;
++	} else
++	#endif
++	{ /* 2.4G */
++		BrateCfg |= rrsr_2g_force_mask;
++		BrateCfg &= rrsr_2g_allow_mask;
++	}
++	masked = BrateCfg;
++
++#ifdef CONFIG_CMCC_TEST
++	BrateCfg |= (RRSR_11M | RRSR_5_5M | RRSR_1M); /* use 11M to send ACK */
++	BrateCfg |= (RRSR_24M | RRSR_18M | RRSR_12M); /*CMCC_OFDM_ACK 12/18/24M */
++#endif
++
++	/* IOT consideration */
++	if (mlmext_info->assoc_AP_vendor == HT_IOT_PEER_CISCO) {
++		/* if peer is cisco and didn't use ofdm rate, we enable 6M ack */
++		if ((BrateCfg & (RRSR_24M | RRSR_12M | RRSR_6M)) == 0)
++			BrateCfg |= RRSR_6M;
++	}
++		ioted = BrateCfg;
++
++#ifdef CONFIG_NARROWBAND_SUPPORTING
++	if ((padapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_10)
++		|| (padapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_5)) {
++		BrateCfg &= ~RRSR_CCK_RATES;
++		BrateCfg |= RRSR_6M;
++	}
++#endif
++	pHalData->BasicRateSet = BrateCfg;
++
++	RTW_INFO("HW_VAR_BASIC_RATE: %#x->%#x->%#x\n", input_b, masked, ioted);
++
++	/* Set RRSR rate table. */
++		temp_RRSR = rtw_read32(padapter, REG_RRSR);
++		temp_RRSR &=0xFFFF0000;
++		temp_RRSR |=BrateCfg;
++		rtw_phydm_set_rrsr(padapter, temp_RRSR, TRUE);
++
++	rtw_write8(padapter, REG_RRSR + 2, rtw_read8(padapter, REG_RRSR + 2) & 0xf0);
++
++	#if defined(CONFIG_RTL8188E)
++	rtw_hal_set_hwreg(padapter, HW_VAR_INIT_RTS_RATE, (u8 *)&BrateCfg);
++	#endif
++}
++
++u8 SetHwReg(_adapter *adapter, u8 variable, u8 *val)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	u8 ret = _SUCCESS;
++
++	switch (variable) {
++	case HW_VAR_MEDIA_STATUS: {
++		u8 net_type = *((u8 *)val);
++
++		rtw_hal_set_msr(adapter, net_type);
++	}
++	break;
++	case HW_VAR_DO_IQK:
++		if (*val)
++			hal_data->bNeedIQK = _TRUE;
++		else
++			hal_data->bNeedIQK = _FALSE;
++		break;
++	case HW_VAR_MAC_ADDR:
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++		rtw_hal_set_macaddr_mbid(adapter, val);
++#else
++		rtw_hal_set_macaddr_port(adapter, val);
++#endif
++		break;
++	case HW_VAR_BSSID:
++		rtw_hal_set_bssid(adapter, val);
++		break;
++	case HW_VAR_RCR:
++		ret = hw_var_rcr_config(adapter, *((u32 *)val));
++		break;
++	case HW_VAR_ON_RCR_AM:
++		hw_var_set_rcr_am(adapter, 1);
++		break;
++	case HW_VAR_OFF_RCR_AM:
++		hw_var_set_rcr_am(adapter, 0);
++		break;
++	case HW_VAR_BEACON_INTERVAL:
++		hw_var_set_bcn_interval(adapter, *(u16 *)val);
++		break;
++#ifdef CONFIG_MBSSID_CAM
++	case HW_VAR_MBSSID_CAM_WRITE: {
++		u32	cmd = 0;
++		u32	*cam_val = (u32 *)val;
++
++		rtw_write32(adapter, REG_MBIDCAMCFG_1, cam_val[0]);
++		cmd = BIT_MBIDCAM_POLL | BIT_MBIDCAM_WT_EN | BIT_MBIDCAM_VALID | cam_val[1];
++		rtw_write32(adapter, REG_MBIDCAMCFG_2, cmd);
++	}
++		break;
++	case HW_VAR_MBSSID_CAM_CLEAR: {
++		u32 cmd;
++		u8 entry_id = *(u8 *)val;
++
++		rtw_write32(adapter, REG_MBIDCAMCFG_1, 0);
++
++		cmd = BIT_MBIDCAM_POLL | BIT_MBIDCAM_WT_EN | ((entry_id & MBIDCAM_ADDR_MASK) << MBIDCAM_ADDR_SHIFT);
++		rtw_write32(adapter, REG_MBIDCAMCFG_2, cmd);
++	}
++		break;
++	case HW_VAR_RCR_MBSSID_EN:
++		if (*((u8 *)val))
++			rtw_hal_rcr_add(adapter, RCR_ENMBID);
++		else
++			rtw_hal_rcr_clear(adapter, RCR_ENMBID);
++		break;
++#endif
++	case HW_VAR_PORT_SWITCH:
++		hw_var_port_switch(adapter);
++		break;
++	case HW_VAR_INIT_RTS_RATE: {
++		u16 brate_cfg = *((u16 *)val);
++		u8 rate_index = 0;
++		HAL_VERSION *hal_ver = &hal_data->version_id;
++
++		if (IS_8188E(*hal_ver)) {
++
++			while (brate_cfg > 0x1) {
++				brate_cfg = (brate_cfg >> 1);
++				rate_index++;
++			}
++			rtw_write8(adapter, REG_INIRTS_RATE_SEL, rate_index);
++		} else
++			rtw_warn_on(1);
++	}
++		break;
++	case HW_VAR_SEC_CFG: {
++		u16 reg_scr_ori;
++		u16 reg_scr;
++
++		reg_scr = reg_scr_ori = rtw_read16(adapter, REG_SECCFG);
++		reg_scr |= (SCR_CHK_KEYID | SCR_RxDecEnable | SCR_TxEncEnable);
++
++		if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC))
++			reg_scr |= SCR_CHK_BMC;
++
++		if (_rtw_camctl_chk_flags(adapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH))
++			reg_scr |= SCR_NoSKMC;
++
++		if (reg_scr != reg_scr_ori)
++			rtw_write16(adapter, REG_SECCFG, reg_scr);
++	}
++		break;
++	case HW_VAR_SEC_DK_CFG: {
++		struct security_priv *sec = &adapter->securitypriv;
++		u8 reg_scr = rtw_read8(adapter, REG_SECCFG);
++
++		if (val) { /* Enable default key related setting */
++			reg_scr |= SCR_TXBCUSEDK;
++			if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)
++				reg_scr |= (SCR_RxUseDK | SCR_TxUseDK);
++		} else /* Disable default key related setting */
++			reg_scr &= ~(SCR_RXBCUSEDK | SCR_TXBCUSEDK | SCR_RxUseDK | SCR_TxUseDK);
++
++		rtw_write8(adapter, REG_SECCFG, reg_scr);
++	}
++		break;
++
++	case HW_VAR_ASIX_IOT:
++		/* enable  ASIX IOT function */
++		if (*((u8 *)val) == _TRUE) {
++			/* 0xa2e[0]=0 (disable rake receiver) */
++			rtw_write8(adapter, rCCK0_FalseAlarmReport + 2,
++				rtw_read8(adapter, rCCK0_FalseAlarmReport + 2) & ~(BIT0));
++			/* 0xa1c=0xa0 (reset channel estimation if signal quality is bad) */
++			rtw_write8(adapter, rCCK0_DSPParameter2, 0xa0);
++		} else {
++			/* restore reg:0xa2e,   reg:0xa1c */
++			rtw_write8(adapter, rCCK0_FalseAlarmReport + 2,
++				rtw_read8(adapter, rCCK0_FalseAlarmReport + 2) | (BIT0));
++			rtw_write8(adapter, rCCK0_DSPParameter2, 0x00);
++		}
++		break;
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++	case HW_VAR_WOWLAN: {
++		struct wowlan_ioctl_param *poidparam;
++
++		poidparam = (struct wowlan_ioctl_param *)val;
++		switch (poidparam->subcode) {
++#ifdef CONFIG_WOWLAN
++		case WOWLAN_PATTERN_CLEAN:
++			rtw_hal_dl_pattern(adapter, 2);
++			break;
++		case WOWLAN_ENABLE:
++			rtw_hal_wow_enable(adapter);
++			break;
++		case WOWLAN_DISABLE:
++			rtw_hal_wow_disable(adapter);
++			break;
++#endif /*CONFIG_WOWLAN*/
++#ifdef CONFIG_AP_WOWLAN
++		case WOWLAN_AP_ENABLE:
++			rtw_hal_ap_wow_enable(adapter);
++			break;
++		case WOWLAN_AP_DISABLE:
++			rtw_hal_ap_wow_disable(adapter);
++			break;
++#endif /*CONFIG_AP_WOWLAN*/
++		default:
++			break;
++		}
++	}
++		break;
++#endif /*defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)*/
++
++#ifndef CONFIG_HAS_HW_VAR_BCN_FUNC
++	case HW_VAR_BCN_FUNC:
++		hw_var_set_bcn_func(adapter, *val);
++		break;
++#endif
++
++#ifndef CONFIG_HAS_HW_VAR_MLME_DISCONNECT
++	case HW_VAR_MLME_DISCONNECT:
++		hw_var_set_mlme_disconnect(adapter);
++		break;
++#endif
++
++	case HW_VAR_MLME_SITESURVEY:
++		hw_var_set_mlme_sitesurvey(adapter, *val);
++		#ifdef CONFIG_BT_COEXIST
++		if (hal_data->EEPROMBluetoothCoexist == 1)
++			rtw_btcoex_ScanNotify(adapter, *val ? _TRUE : _FALSE);
++		#endif
++		break;
++
++#ifndef CONFIG_HAS_HW_VAR_MLME_JOIN
++	case HW_VAR_MLME_JOIN:
++		hw_var_set_mlme_join(adapter, *val);
++		break;
++#endif
++
++	case HW_VAR_EN_HW_UPDATE_TSF:
++		rtw_hal_set_hw_update_tsf(adapter);
++		break;
++#ifndef CONFIG_HAS_HW_VAR_CORRECT_TSF
++	case HW_VAR_CORRECT_TSF:
++		hw_var_set_correct_tsf(adapter, *val);
++		break;
++#endif
++
++#if defined(CONFIG_HW_P0_TSF_SYNC) && defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_MCC_MODE)
++	case HW_VAR_TSF_AUTO_SYNC:
++		if (*val == _TRUE)
++			hw_port0_tsf_sync_sel(adapter, _TRUE, adapter->hw_port, 50);
++		else
++			hw_port0_tsf_sync_sel(adapter, _FALSE, adapter->hw_port, 50);
++		break;
++#endif
++	case HW_VAR_APFM_ON_MAC:
++		hal_data->bMacPwrCtrlOn = *val;
++		RTW_INFO("%s: bMacPwrCtrlOn=%d\n", __func__, hal_data->bMacPwrCtrlOn);
++		break;
++#ifdef CONFIG_WMMPS_STA
++	case  HW_VAR_UAPSD_TID:
++		rtw_hal_update_uapsd_tid(adapter);
++		break;
++#endif /* CONFIG_WMMPS_STA */
++#ifdef CONFIG_LPS_PG
++	case HW_VAR_LPS_PG_HANDLE:
++		rtw_hal_lps_pg_handler(adapter, *val);
++		break;
++#endif
++#ifdef CONFIG_LPS_LCLK_WD_TIMER
++	case HW_VAR_DM_IN_LPS_LCLK:
++		rtw_phydm_wd_lps_lclk_hdl(adapter);
++		break;
++#endif
++	case HW_VAR_ENABLE_RX_BAR:
++		if (*val == _TRUE) {
++			/* enable RX BAR */
++			u16 val16 = rtw_read16(adapter, REG_RXFLTMAP1);
++
++			val16 |= BIT(8);
++			rtw_write16(adapter, REG_RXFLTMAP1, val16);
++		} else {
++			/* disable RX BAR */
++			u16 val16 = rtw_read16(adapter, REG_RXFLTMAP1);
++
++			val16 &= (~BIT(8));
++			rtw_write16(adapter, REG_RXFLTMAP1, val16);
++		}
++		RTW_INFO("[HW_VAR_ENABLE_RX_BAR] 0x%02X=0x%02X\n",
++			REG_RXFLTMAP1, rtw_read16(adapter, REG_RXFLTMAP1));
++		break;
++	case HW_VAR_HCI_SUS_STATE:
++		hal_data->hci_sus_state = *(u8 *)val;
++		RTW_INFO("%s: hci_sus_state=%u\n", __func__, hal_data->hci_sus_state);
++		break;
++#if defined(CONFIG_AP_MODE) && defined(CONFIG_FW_HANDLE_TXBCN) && defined(CONFIG_SUPPORT_MULTI_BCN)
++		case HW_VAR_BCN_HEAD_SEL:
++		{
++			u8 vap_id = *(u8 *)val;
++
++			if ((vap_id >= CONFIG_LIMITED_AP_NUM) && (vap_id != 0xFF)) {
++				RTW_ERR(ADPT_FMT " vap_id(%d:%d) is invalid\n", ADPT_ARG(adapter),vap_id, adapter->vap_id);
++				rtw_warn_on(1);
++			}
++			if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
++				u16 drv_pg_bndy = 0, bcn_addr = 0;
++				u32 page_size = 0;
++
++				/*rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_BOUNDARY, &drv_pg_bndy);*/
++				rtw_halmac_get_rsvd_drv_pg_bndy(adapter_to_dvobj(adapter), &drv_pg_bndy);
++				rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&page_size);
++
++				if (vap_id != 0xFF)
++					bcn_addr = drv_pg_bndy + (vap_id * (MAX_BEACON_LEN / page_size));
++				else
++					bcn_addr = drv_pg_bndy;
++				RTW_INFO(ADPT_FMT" vap_id(%d) change BCN HEAD to 0x%04x\n",
++					ADPT_ARG(adapter), vap_id, bcn_addr);
++				rtw_write16(adapter, REG_FIFOPAGE_CTRL_2,
++					(bcn_addr & BIT_MASK_BCN_HEAD_1_V1) | BIT_BCN_VALID_V1);
++			}
++		}
++		break;
++#endif
++	case HW_VAR_LPS_STATE_CHK :
++		rtw_lps_state_chk(adapter, *(u8 *)val);
++		break;
++
++#ifdef CONFIG_RTS_FULL_BW
++	case HW_VAR_SET_RTS_BW:
++	{
++		#ifdef RTW_HALMAC
++			rtw_halmac_set_rts_full_bw(adapter_to_dvobj(adapter), (*val));
++		#else
++			u8 temp;
++			if(*val)
++				temp = (( rtw_read8(adapter, REG_INIRTS_RATE_SEL)) | BIT5 );
++			else
++				temp = (( rtw_read8(adapter, REG_INIRTS_RATE_SEL)) & (~BIT5));
++			rtw_write8(adapter, REG_INIRTS_RATE_SEL, temp);
++			/*RTW_INFO("HW_VAR_SET_RTS_BW	val=%u REG480=0x%x\n", *val, rtw_read8(adapter, REG_INIRTS_RATE_SEL));*/
++		#endif
++	}
++	break;
++#endif/*CONFIG_RTS_FULL_BW*/
++#if defined(CONFIG_PCI_HCI)
++	case HW_VAR_ENSWBCN: 
++	if (*val == _TRUE) {
++		rtw_write8(adapter, REG_CR + 1,
++			   rtw_read8(adapter, REG_CR + 1) | BIT(0));
++	} else
++		rtw_write8(adapter, REG_CR + 1,
++			   rtw_read8(adapter, REG_CR + 1) & ~BIT(0));
++	break;
++#endif
++	default:
++		if (0)
++			RTW_PRINT(FUNC_ADPT_FMT" variable(%d) not defined!\n",
++				  FUNC_ADPT_ARG(adapter), variable);
++		ret = _FAIL;
++		break;
++	}
++
++	return ret;
++}
++
++void GetHwReg(_adapter *adapter, u8 variable, u8 *val)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	u64 val64;
++
++
++	switch (variable) {
++	case HW_VAR_MAC_ADDR:
++		#ifndef CONFIG_MI_WITH_MBSSID_CAM
++		rtw_hal_get_macaddr_port(adapter, val);
++		#endif
++		break;
++	case HW_VAR_BASIC_RATE:
++		*((u16 *)val) = hal_data->BasicRateSet;
++		break;
++	case HW_VAR_MEDIA_STATUS:
++		rtw_hal_get_msr(adapter, val);
++		break;
++	case HW_VAR_DO_IQK:
++		*val = hal_data->bNeedIQK;
++		break;
++	case HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO:
++		if (hal_is_band_support(adapter, BAND_ON_5G))
++			*val = _TRUE;
++		else
++			*val = _FALSE;
++		break;
++	case HW_VAR_APFM_ON_MAC:
++		*val = hal_data->bMacPwrCtrlOn;
++		break;
++	case HW_VAR_RCR:
++		hw_var_rcr_get(adapter, (u32 *)val);
++		break;
++	case HW_VAR_FWLPS_RF_ON:
++		/* When we halt NIC, we should check if FW LPS is leave. */
++		if (rtw_is_surprise_removed(adapter)
++			|| (adapter_to_pwrctl(adapter)->rf_pwrstate == rf_off)
++		) {
++			/*
++			 * If it is in HW/SW Radio OFF or IPS state,
++			 * we do not check Fw LPS Leave,
++			 * because Fw is unload.
++			 */
++			*val = _TRUE;
++		} else {
++			u32 rcr = 0;
++
++			rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
++			if (rcr & (RCR_UC_MD_EN | RCR_BC_MD_EN | RCR_TIM_PARSER_EN))
++				*val = _FALSE;
++			else
++				*val = _TRUE;
++		}
++		break;
++
++	case HW_VAR_HCI_SUS_STATE:
++		*((u8 *)val) = hal_data->hci_sus_state;
++		break;
++
++#ifndef CONFIG_HAS_HW_VAR_BCN_CTRL_ADDR
++	case HW_VAR_BCN_CTRL_ADDR:
++		*((u32 *)val) = hw_bcn_ctrl_addr(adapter, adapter->hw_port);
++		break;
++#endif
++
++#ifdef CONFIG_WAPI_SUPPORT
++	case HW_VAR_CAM_EMPTY_ENTRY: {
++		u8	ucIndex = *((u8 *)val);
++		u8	i;
++		u32	ulCommand = 0;
++		u32	ulContent = 0;
++		u32	ulEncAlgo = CAM_AES;
++
++		for (i = 0; i < CAM_CONTENT_COUNT; i++) {
++			/* filled id in CAM config 2 byte */
++			if (i == 0)
++				ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo) << 2);
++			else
++				ulContent = 0;
++			/* polling bit, and No Write enable, and address */
++			ulCommand = CAM_CONTENT_COUNT * ucIndex + i;
++			ulCommand = ulCommand | CAM_POLLINIG | CAM_WRITE;
++			/* write content 0 is equall to mark invalid */
++			rtw_write32(adapter, REG_CAMWRITE, ulContent);  /* delay_ms(40); */
++			rtw_write32(adapter, REG_CAMCMD, ulCommand);  /* delay_ms(40); */
++		}
++	}
++#endif
++
++	default:
++		if (0)
++			RTW_PRINT(FUNC_ADPT_FMT" variable(%d) not defined!\n",
++				  FUNC_ADPT_ARG(adapter), variable);
++		break;
++	}
++
++}
++
++static u32 _get_page_size(struct _ADAPTER *a)
++{
++#ifdef RTW_HALMAC
++	struct dvobj_priv *d;
++	u32 size = 0;
++	int err = 0;
++
++
++	d = adapter_to_dvobj(a);
++
++	err = rtw_halmac_get_page_size(d, &size);
++	if (!err)
++		return size;
++
++	RTW_WARN(FUNC_ADPT_FMT ": Fail to get Page size!!(err=%d)\n",
++		 FUNC_ADPT_ARG(a), err);
++#endif /* RTW_HALMAC */
++
++	return PAGE_SIZE_128;
++}
++
++u8
++SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	u8 bResult = _SUCCESS;
++
++	switch (variable) {
++
++	case HAL_DEF_DBG_DUMP_RXPKT:
++		hal_data->bDumpRxPkt = *((u8 *)value);
++		break;
++	case HAL_DEF_DBG_DUMP_TXPKT:
++		hal_data->bDumpTxPkt = *((u8 *)value);
++		break;
++	case HAL_DEF_ANT_DETECT:
++		hal_data->AntDetection = *((u8 *)value);
++		break;
++	default:
++		RTW_PRINT("%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
++		bResult = _FAIL;
++		break;
++	}
++
++	return bResult;
++}
++
++#ifdef CONFIG_BEAMFORMING
++u8 rtw_hal_query_txbfer_rf_num(_adapter *adapter)
++{
++	struct registry_priv	*pregistrypriv = &adapter->registrypriv;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++
++	if ((pregistrypriv->beamformer_rf_num) && (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter) || IS_HARDWARE_TYPE_8822BU(adapter) || IS_HARDWARE_TYPE_8821C(adapter)))
++		return pregistrypriv->beamformer_rf_num;
++	else if (IS_HARDWARE_TYPE_8814AE(adapter)
++#if 0
++#if defined(CONFIG_USB_HCI)
++		|| (IS_HARDWARE_TYPE_8814AU(adapter) && (pUsbModeMech->CurUsbMode == 2 || pUsbModeMech->HubUsbMode == 2))  /* for USB3.0 */
++#endif
++#endif
++		) {
++		/*BF cap provided by Yu Chen, Sean, 2015, 01 */
++		if (hal_data->rf_type == RF_3T3R)
++			return 2;
++		else if (hal_data->rf_type == RF_4T4R)
++			return 3;
++		else
++			return 1;
++	} else
++		return 1;
++
++}
++u8 rtw_hal_query_txbfee_rf_num(_adapter *adapter)
++{
++	struct registry_priv		*pregistrypriv = &adapter->registrypriv;
++	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++
++	if ((pregistrypriv->beamformee_rf_num) && (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter) || IS_HARDWARE_TYPE_8822BU(adapter) || IS_HARDWARE_TYPE_8821C(adapter)))
++		return pregistrypriv->beamformee_rf_num;
++	else if (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter)) {
++		if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM)
++			return 2;
++		else
++			return 2;/*TODO: May be 3 in the future, by ChenYu. */
++	} else
++		return 1;
++
++}
++#ifdef RTW_BEAMFORMING_VERSION_2
++void rtw_hal_beamforming_config_csirate(PADAPTER adapter)
++{
++	struct dm_struct *p_dm_odm;
++	struct beamforming_info *bf_info;
++	u8 fix_rate_enable = 0;
++	u8 new_csi_rate_idx;
++	u8 rrsr_54_en;
++	u32 temp_rrsr;
++
++	/* Acting as BFee */
++	if (IS_BEAMFORMEE(adapter)) {
++	#if 0
++		/* Do not enable now because it will affect MU performance and CTS/BA rate. 2016.07.19. by tynli. [PCIE-1660] */
++		if (IS_HARDWARE_TYPE_8821C(Adapter))
++			FixRateEnable = 1;	/* Support after 8821C */
++	#endif
++
++		p_dm_odm = adapter_to_phydm(adapter);
++		bf_info = GET_BEAMFORM_INFO(adapter);
++
++		rtw_halmac_bf_cfg_csi_rate(adapter_to_dvobj(adapter),
++				p_dm_odm->rssi_min,
++				bf_info->cur_csi_rpt_rate,
++				fix_rate_enable, &new_csi_rate_idx, &rrsr_54_en);
++
++		temp_rrsr = rtw_read32(adapter, REG_RRSR);
++		if (rrsr_54_en == 1)
++			temp_rrsr |= RRSR_54M;
++		else if (rrsr_54_en == 0)
++			temp_rrsr &= ~RRSR_54M;
++		rtw_phydm_set_rrsr(adapter, temp_rrsr, FALSE);
++
++		if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)
++			bf_info->cur_csi_rpt_rate = new_csi_rate_idx;
++	}
++}
++#endif
++#endif
++
++u8
++GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	u8 bResult = _SUCCESS;
++
++	switch (variable) {
++	case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB: {
++		struct mlme_priv *pmlmepriv;
++		struct sta_priv *pstapriv;
++		struct sta_info *psta;
++
++		pmlmepriv = &adapter->mlmepriv;
++		pstapriv = &adapter->stapriv;
++		psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
++		if (psta)
++			*((int *)value) = psta->cmn.rssi_stat.rssi;
++	}
++	break;
++	case HAL_DEF_DBG_DUMP_RXPKT:
++		*((u8 *)value) = hal_data->bDumpRxPkt;
++		break;
++	case HAL_DEF_DBG_DUMP_TXPKT:
++		*((u8 *)value) = hal_data->bDumpTxPkt;
++		break;
++	case HAL_DEF_ANT_DETECT:
++		*((u8 *)value) = hal_data->AntDetection;
++		break;
++	case HAL_DEF_TX_PAGE_SIZE:
++		*((u32 *)value) = _get_page_size(adapter);
++		break;
++	case HAL_DEF_TX_STBC:
++		#ifdef CONFIG_ALPHA_SMART_ANTENNA 
++		*(u8 *)value = 0;
++		#else
++		*(u8 *)value = hal_data->max_tx_cnt > 1 ? 1 : 0;
++		#endif
++		break;
++	case HAL_DEF_EXPLICIT_BEAMFORMER:
++	case HAL_DEF_EXPLICIT_BEAMFORMEE:
++	case HAL_DEF_VHT_MU_BEAMFORMER:
++	case HAL_DEF_VHT_MU_BEAMFORMEE:
++		*(u8 *)value = _FALSE;
++		break;
++#ifdef CONFIG_BEAMFORMING
++	case HAL_DEF_BEAMFORMER_CAP:
++		*(u8 *)value = rtw_hal_query_txbfer_rf_num(adapter);
++		break;
++	case HAL_DEF_BEAMFORMEE_CAP:
++		*(u8 *)value = rtw_hal_query_txbfee_rf_num(adapter);
++		break;
++#endif
++	default:
++		RTW_PRINT("%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
++		bResult = _FAIL;
++		break;
++	}
++
++	return bResult;
++}
++
++/*
++ *	Description:
++ *		Translate a character to hex digit.
++ *   */
++u32
++MapCharToHexDigit(
++			char		chTmp
++)
++{
++	if (chTmp >= '0' && chTmp <= '9')
++		return chTmp - '0';
++	else if (chTmp >= 'a' && chTmp <= 'f')
++		return 10 + (chTmp - 'a');
++	else if (chTmp >= 'A' && chTmp <= 'F')
++		return 10 + (chTmp - 'A');
++	else
++		return 0;
++}
++
++
++
++/*
++ *	Description:
++ *		Parse hex number from the string pucStr.
++ *   */
++BOOLEAN
++GetHexValueFromString(
++		char			*szStr,
++		u32			*pu4bVal,
++		u32			*pu4bMove
++)
++{
++	char		*szScan = szStr;
++
++	/* Check input parameter. */
++	if (szStr == NULL || pu4bVal == NULL || pu4bMove == NULL) {
++		RTW_INFO("GetHexValueFromString(): Invalid inpur argumetns! szStr: %p, pu4bVal: %p, pu4bMove: %p\n", szStr, pu4bVal, pu4bMove);
++		return _FALSE;
++	}
++
++	/* Initialize output. */
++	*pu4bMove = 0;
++	*pu4bVal = 0;
++
++	/* Skip leading space. */
++	while (*szScan != '\0' &&
++	       (*szScan == ' ' || *szScan == '\t')) {
++		szScan++;
++		(*pu4bMove)++;
++	}
++
++	/* Skip leading '0x' or '0X'. */
++	if (*szScan == '0' && (*(szScan + 1) == 'x' || *(szScan + 1) == 'X')) {
++		szScan += 2;
++		(*pu4bMove) += 2;
++	}
++
++	/* Check if szScan is now pointer to a character for hex digit, */
++	/* if not, it means this is not a valid hex number. */
++	if (!IsHexDigit(*szScan))
++		return _FALSE;
++
++	/* Parse each digit. */
++	do {
++		(*pu4bVal) <<= 4;
++		*pu4bVal += MapCharToHexDigit(*szScan);
++
++		szScan++;
++		(*pu4bMove)++;
++	} while (IsHexDigit(*szScan));
++
++	return _TRUE;
++}
++
++BOOLEAN
++GetFractionValueFromString(
++		char			*szStr,
++		u8				*pInteger,
++		u8				*pFraction,
++		u32			*pu4bMove
++)
++{
++	char	*szScan = szStr;
++
++	/* Initialize output. */
++	*pu4bMove = 0;
++	*pInteger = 0;
++	*pFraction = 0;
++
++	/* Skip leading space. */
++	while (*szScan != '\0' &&	(*szScan == ' ' || *szScan == '\t')) {
++		++szScan;
++		++(*pu4bMove);
++	}
++
++	if (*szScan < '0' || *szScan > '9')
++		return _FALSE;
++
++	/* Parse each digit. */
++	do {
++		(*pInteger) *= 10;
++		*pInteger += (*szScan - '0');
++
++		++szScan;
++		++(*pu4bMove);
++
++		if (*szScan == '.') {
++			++szScan;
++			++(*pu4bMove);
++
++			if (*szScan < '0' || *szScan > '9')
++				return _FALSE;
++
++			*pFraction += (*szScan - '0') * 10;
++			++szScan;
++			++(*pu4bMove);
++
++			if (*szScan >= '0' && *szScan <= '9') {
++				*pFraction += *szScan - '0';
++				++szScan;
++				++(*pu4bMove);
++			}
++			return _TRUE;
++		}
++	} while (*szScan >= '0' && *szScan <= '9');
++
++	return _TRUE;
++}
++
++/*
++ *	Description:
++ * Return TRUE if szStr is comment out with leading " */ /* ".
++ *   */
++BOOLEAN
++IsCommentString(
++		char			*szStr
++)
++{
++	if (*szStr == '/' && *(szStr + 1) == '/')
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++BOOLEAN
++GetU1ByteIntegerFromStringInDecimal(
++		char	*Str,
++		u8		*pInt
++)
++{
++	u16 i = 0;
++	*pInt = 0;
++
++	while (Str[i] != '\0') {
++		if (Str[i] >= '0' && Str[i] <= '9') {
++			*pInt *= 10;
++			*pInt += (Str[i] - '0');
++		} else
++			return _FALSE;
++		++i;
++	}
++
++	return _TRUE;
++}
++
++/* <20121004, Kordan> For example,
++ * ParseQualifiedString(inString, 0, outString, '[', ']') gets "Kordan" from a string "Hello [Kordan]".
++ * If RightQualifier does not exist, it will hang on in the while loop */
++BOOLEAN
++ParseQualifiedString(
++			char	*In,
++			u32	*Start,
++			char	*Out,
++			char		LeftQualifier,
++			char		RightQualifier
++)
++{
++	u32	i = 0, j = 0;
++	char	c = In[(*Start)++];
++
++	if (c != LeftQualifier)
++		return _FALSE;
++
++	i = (*Start);
++	c = In[(*Start)++];
++	while (c != RightQualifier && c != '\0')
++		c = In[(*Start)++];
++
++	if (c == '\0')
++		return _FALSE;
++
++	j = (*Start) - 2;
++	strncpy((char *)Out, (const char *)(In + i), j - i + 1);
++
++	return _TRUE;
++}
++
++BOOLEAN
++isAllSpaceOrTab(
++	u8	*data,
++	u8	size
++)
++{
++	u8	cnt = 0, NumOfSpaceAndTab = 0;
++
++	while (size > cnt) {
++		if (data[cnt] == ' ' || data[cnt] == '\t' || data[cnt] == '\0')
++			++NumOfSpaceAndTab;
++
++		++cnt;
++	}
++
++	return size == NumOfSpaceAndTab;
++}
++
++
++void rtw_hal_check_rxfifo_full(_adapter *adapter)
++{
++	struct dvobj_priv *psdpriv = adapter->dvobj;
++	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
++	struct registry_priv *regsty = &adapter->registrypriv;
++	int save_cnt = _FALSE;
++
++	if (regsty->check_hw_status == 1) {
++		/* switch counter to RX fifo */
++		if (IS_8188E(pHalData->version_id) ||
++		    IS_8188F(pHalData->version_id) ||
++		    IS_8188GTV(pHalData->version_id) ||
++		    IS_8812_SERIES(pHalData->version_id) ||
++		    IS_8821_SERIES(pHalData->version_id) ||
++		    IS_8723B_SERIES(pHalData->version_id) ||
++		    IS_8192E(pHalData->version_id) ||
++		    IS_8703B_SERIES(pHalData->version_id) ||
++		    IS_8723D_SERIES(pHalData->version_id) ||
++		    IS_8192F_SERIES(pHalData->version_id)) {
++			rtw_write8(adapter, REG_RXERR_RPT + 3, rtw_read8(adapter, REG_RXERR_RPT + 3) | 0xa0);
++			save_cnt = _TRUE;
++		} else {
++			/* todo: other chips */
++		}
++
++
++		if (save_cnt) {
++			pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow;
++			pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT);
++			pdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow - pdbgpriv->dbg_rx_fifo_last_overflow;
++		} else {
++			/* special value to indicate no implementation */
++			pdbgpriv->dbg_rx_fifo_last_overflow = 1;
++			pdbgpriv->dbg_rx_fifo_curr_overflow = 1;
++			pdbgpriv->dbg_rx_fifo_diff_overflow = 1;
++		}
++	}
++}
++
++void linked_info_dump(_adapter *padapter, u8 benable)
++{
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++
++	if (padapter->bLinkInfoDump == benable)
++		return;
++
++	RTW_INFO("%s %s\n", __FUNCTION__, (benable) ? "enable" : "disable");
++
++	if (benable) {
++#ifdef CONFIG_LPS
++		pwrctrlpriv->org_power_mgnt = pwrctrlpriv->power_mgnt;/* keep org value */
++		rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
++#endif
++
++#ifdef CONFIG_IPS
++		pwrctrlpriv->ips_org_mode = pwrctrlpriv->ips_mode;/* keep org value */
++		rtw_pm_set_ips(padapter, IPS_NONE);
++#endif
++	} else {
++#ifdef CONFIG_IPS
++		rtw_pm_set_ips(padapter, pwrctrlpriv->ips_org_mode);
++#endif /* CONFIG_IPS */
++
++#ifdef CONFIG_LPS
++		rtw_pm_set_lps(padapter, pwrctrlpriv->org_power_mgnt);
++#endif /* CONFIG_LPS */
++	}
++	padapter->bLinkInfoDump = benable ;
++}
++
++#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
++void rtw_get_raw_rssi_info(void *sel, _adapter *padapter)
++{
++	u8 isCCKrate, rf_path;
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++	struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
++	RTW_PRINT_SEL(sel, "RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n",
++		HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);
++	isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? TRUE : FALSE;
++
++	if (isCCKrate)
++		psample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball;
++
++	for (rf_path = 0; rf_path < hal_spec->rf_reg_path_num; rf_path++) {
++		if (!(GET_HAL_RX_PATH_BMP(padapter) & BIT(rf_path)))
++			continue;
++		RTW_PRINT_SEL(sel, "RF_PATH_%d=>signal_strength:%d(%%),signal_quality:%d(%%)\n"
++			, rf_path, psample_pkt_rssi->mimo_signal_strength[rf_path], psample_pkt_rssi->mimo_signal_quality[rf_path]);
++
++		if (!isCCKrate) {
++			RTW_PRINT_SEL(sel, "\trx_ofdm_pwr:%d(dBm),rx_ofdm_snr:%d(dB)\n",
++				psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);
++		}
++	}
++}
++
++void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel)
++{
++	u8 isCCKrate, rf_path;
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++	struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
++	_RTW_PRINT_SEL(sel, "============ RAW Rx Info dump ===================\n");
++	_RTW_PRINT_SEL(sel, "RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n", HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);
++
++	isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? TRUE : FALSE;
++
++	if (isCCKrate)
++		psample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball;
++
++	for (rf_path = 0; rf_path < hal_spec->rf_reg_path_num; rf_path++) {
++		if (!(GET_HAL_RX_PATH_BMP(padapter) & BIT(rf_path)))
++			continue;
++		_RTW_PRINT_SEL(sel , "RF_PATH_%d=>signal_strength:%d(%%),signal_quality:%d(%%)"
++			, rf_path, psample_pkt_rssi->mimo_signal_strength[rf_path], psample_pkt_rssi->mimo_signal_quality[rf_path]);
++
++		if (!isCCKrate)
++			_RTW_PRINT_SEL(sel , ",rx_ofdm_pwr:%d(dBm),rx_ofdm_snr:%d(dB)\n", psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);
++		else
++			_RTW_PRINT_SEL(sel , "\n");
++
++	}
++}
++#endif
++
++#ifdef DBG_RX_DFRAME_RAW_DATA
++void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel)
++{
++#define DBG_RX_DFRAME_RAW_DATA_UC		0
++#define DBG_RX_DFRAME_RAW_DATA_BMC		1
++#define DBG_RX_DFRAME_RAW_DATA_TYPES	2
++
++	_irqL irqL;
++	u8 isCCKrate, rf_path;
++	struct recv_priv *precvpriv = &(padapter->recvpriv);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct sta_info *psta;
++	struct sta_recv_dframe_info *psta_dframe_info;
++	int i, j;
++	_list	*plist, *phead;
++	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
++
++	if (precvpriv->store_law_data_flag) {
++
++		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++		for (i = 0; i < NUM_STA; i++) {
++			phead = &(pstapriv->sta_hash[i]);
++			plist = get_next(phead);
++
++			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++
++				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++				plist = get_next(plist);
++
++				if (psta) {
++					if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)  !=   _TRUE)
++					    && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN)  !=  _TRUE)
++					    && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN)  !=  _TRUE)) {
++
++						RTW_PRINT_SEL(sel, "==============================\n");
++						RTW_PRINT_SEL(sel, "macaddr =" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
++
++						for (j = 0; j < DBG_RX_DFRAME_RAW_DATA_TYPES; j++) {
++							if (j == DBG_RX_DFRAME_RAW_DATA_UC) {
++								psta_dframe_info = &psta->sta_dframe_info;
++								RTW_PRINT_SEL(sel, "\n");
++								RTW_PRINT_SEL(sel, "Unicast:\n");
++							} else if (j == DBG_RX_DFRAME_RAW_DATA_BMC) {
++								psta_dframe_info = &psta->sta_dframe_info_bmc;
++								RTW_PRINT_SEL(sel, "\n");
++								RTW_PRINT_SEL(sel, "Broadcast/Multicast:\n");
++							}
++
++							isCCKrate = (psta_dframe_info->sta_data_rate <= DESC_RATE11M) ? TRUE : FALSE;
++
++							RTW_PRINT_SEL(sel, "BW=%s, sgi =%d\n", ch_width_str(psta_dframe_info->sta_bw_mode), psta_dframe_info->sta_sgi);
++							RTW_PRINT_SEL(sel, "Rx_Data_Rate = %s\n", HDATA_RATE(psta_dframe_info->sta_data_rate));
++
++							for (rf_path = 0; rf_path < hal_spec->rf_reg_path_num; rf_path++) {
++								if (!(GET_HAL_RX_PATH_BMP(padapter) & BIT(rf_path)))
++									continue;
++								if (!isCCKrate) {
++									RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)", rf_path, psta_dframe_info->sta_RxPwr[rf_path]);
++									_RTW_PRINT_SEL(sel , ",rx_ofdm_snr:%d(dB)\n", psta_dframe_info->sta_ofdm_snr[rf_path]);
++								} else
++									RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)\n", rf_path, (psta_dframe_info->sta_mimo_signal_strength[rf_path]) - 100);
++							}
++						}
++
++					}
++				}
++			}
++		}
++		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++	}
++}
++#endif
++void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe)
++{
++	u8 isCCKrate, rf_path , dframe_type;
++	u8 *ptr;
++	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++#ifdef DBG_RX_DFRAME_RAW_DATA
++	struct sta_recv_dframe_info *psta_dframe_info;
++#endif
++	struct recv_priv *precvpriv = &(padapter->recvpriv);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
++	struct sta_info *psta = prframe->u.hdr.psta;
++	struct phydm_phyinfo_struct *p_phy_info = &pattrib->phy_info;
++	struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
++	psample_pkt_rssi->data_rate = pattrib->data_rate;
++	ptr = prframe->u.hdr.rx_data;
++	dframe_type = GetFrameType(ptr);
++	/*RTW_INFO("=>%s\n", __FUNCTION__);*/
++
++
++	if (precvpriv->store_law_data_flag) {
++		isCCKrate = (pattrib->data_rate <= DESC_RATE11M) ? TRUE : FALSE;
++
++		psample_pkt_rssi->pwdball = p_phy_info->rx_pwdb_all;
++		psample_pkt_rssi->pwr_all = p_phy_info->recv_signal_power;
++
++		for (rf_path = 0; rf_path < hal_spec->rf_reg_path_num; rf_path++) {
++			psample_pkt_rssi->mimo_signal_strength[rf_path] = p_phy_info->rx_mimo_signal_strength[rf_path];
++			psample_pkt_rssi->mimo_signal_quality[rf_path] = p_phy_info->rx_mimo_signal_quality[rf_path];
++			if (!isCCKrate) {
++				psample_pkt_rssi->ofdm_pwr[rf_path] = p_phy_info->rx_pwr[rf_path];
++				psample_pkt_rssi->ofdm_snr[rf_path] = p_phy_info->rx_snr[rf_path];
++			}
++		}
++#ifdef DBG_RX_DFRAME_RAW_DATA
++		if ((dframe_type == WIFI_DATA_TYPE) || (dframe_type == WIFI_QOS_DATA_TYPE) || (padapter->registrypriv.mp_mode == 1)) {
++
++			/*RTW_INFO("=>%s WIFI_DATA_TYPE or WIFI_QOS_DATA_TYPE\n", __FUNCTION__);*/
++			if (psta) {
++				if (IS_MCAST(get_ra(get_recvframe_data(prframe))))
++					psta_dframe_info = &psta->sta_dframe_info_bmc;
++				else
++					psta_dframe_info = &psta->sta_dframe_info;
++				/*RTW_INFO("=>%s psta->cmn.mac_addr="MAC_FMT" !\n",
++					__FUNCTION__, MAC_ARG(psta->cmn.mac_addr));*/
++				if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) != _TRUE) || (padapter->registrypriv.mp_mode == 1)) {
++					psta_dframe_info->sta_data_rate = pattrib->data_rate;
++					psta_dframe_info->sta_sgi = pattrib->sgi;
++					psta_dframe_info->sta_bw_mode = pattrib->bw;
++					for (rf_path = 0; rf_path < hal_spec->rf_reg_path_num; rf_path++) {
++
++						psta_dframe_info->sta_mimo_signal_strength[rf_path] = (p_phy_info->rx_mimo_signal_strength[rf_path]);/*Percentage to dbm*/
++
++						if (!isCCKrate) {
++							psta_dframe_info->sta_ofdm_snr[rf_path] = p_phy_info->rx_snr[rf_path];
++							psta_dframe_info->sta_RxPwr[rf_path] = p_phy_info->rx_pwr[rf_path];
++						}
++					}
++				}
++			}
++		}
++#endif
++	}
++
++}
++
++int hal_efuse_macaddr_offset(_adapter *adapter)
++{
++	u8 interface_type = 0;
++	int addr_offset = -1;
++
++	interface_type = rtw_get_intf_type(adapter);
++
++	switch (rtw_get_chip_type(adapter)) {
++#ifdef CONFIG_RTL8723B
++	case RTL8723B:
++		if (interface_type == RTW_USB)
++			addr_offset = EEPROM_MAC_ADDR_8723BU;
++		else if (interface_type == RTW_SDIO)
++			addr_offset = EEPROM_MAC_ADDR_8723BS;
++		else if (interface_type == RTW_PCIE)
++			addr_offset = EEPROM_MAC_ADDR_8723BE;
++		break;
++#endif
++#ifdef CONFIG_RTL8703B
++	case RTL8703B:
++		if (interface_type == RTW_USB)
++			addr_offset = EEPROM_MAC_ADDR_8703BU;
++		else if (interface_type == RTW_SDIO)
++			addr_offset = EEPROM_MAC_ADDR_8703BS;
++		break;
++#endif
++#ifdef CONFIG_RTL8723D
++	case RTL8723D:
++		if (interface_type == RTW_USB)
++			addr_offset = EEPROM_MAC_ADDR_8723DU;
++		else if (interface_type == RTW_SDIO)
++			addr_offset = EEPROM_MAC_ADDR_8723DS;
++		else if (interface_type == RTW_PCIE)
++			addr_offset = EEPROM_MAC_ADDR_8723DE;
++		break;
++#endif
++
++#ifdef CONFIG_RTL8188E
++	case RTL8188E:
++		if (interface_type == RTW_USB)
++			addr_offset = EEPROM_MAC_ADDR_88EU;
++		else if (interface_type == RTW_SDIO)
++			addr_offset = EEPROM_MAC_ADDR_88ES;
++		else if (interface_type == RTW_PCIE)
++			addr_offset = EEPROM_MAC_ADDR_88EE;
++		break;
++#endif
++#ifdef CONFIG_RTL8188F
++	case RTL8188F:
++		if (interface_type == RTW_USB)
++			addr_offset = EEPROM_MAC_ADDR_8188FU;
++		else if (interface_type == RTW_SDIO)
++			addr_offset = EEPROM_MAC_ADDR_8188FS;
++		break;
++#endif
++#ifdef CONFIG_RTL8188GTV
++	case RTL8188GTV:
++		if (interface_type == RTW_USB)
++			addr_offset = EEPROM_MAC_ADDR_8188GTVU;
++		else if (interface_type == RTW_SDIO)
++			addr_offset = EEPROM_MAC_ADDR_8188GTVS;
++		break;
++#endif
++#ifdef CONFIG_RTL8812A
++	case RTL8812:
++		if (interface_type == RTW_USB)
++			addr_offset = EEPROM_MAC_ADDR_8812AU;
++		else if (interface_type == RTW_PCIE)
++			addr_offset = EEPROM_MAC_ADDR_8812AE;
++		break;
++#endif
++#ifdef CONFIG_RTL8821A
++	case RTL8821:
++		if (interface_type == RTW_USB)
++			addr_offset = EEPROM_MAC_ADDR_8821AU;
++		else if (interface_type == RTW_SDIO)
++			addr_offset = EEPROM_MAC_ADDR_8821AS;
++		else if (interface_type == RTW_PCIE)
++			addr_offset = EEPROM_MAC_ADDR_8821AE;
++		break;
++#endif
++#ifdef CONFIG_RTL8192E
++	case RTL8192E:
++		if (interface_type == RTW_USB)
++			addr_offset = EEPROM_MAC_ADDR_8192EU;
++		else if (interface_type == RTW_SDIO)
++			addr_offset = EEPROM_MAC_ADDR_8192ES;
++		else if (interface_type == RTW_PCIE)
++			addr_offset = EEPROM_MAC_ADDR_8192EE;
++		break;
++#endif
++#ifdef CONFIG_RTL8814A
++	case RTL8814A:
++		if (interface_type == RTW_USB)
++			addr_offset = EEPROM_MAC_ADDR_8814AU;
++		else if (interface_type == RTW_PCIE)
++			addr_offset = EEPROM_MAC_ADDR_8814AE;
++		break;
++#endif
++
++#ifdef CONFIG_RTL8822B
++	case RTL8822B:
++		if (interface_type == RTW_USB)
++			addr_offset = EEPROM_MAC_ADDR_8822BU;
++		else if (interface_type == RTW_SDIO)
++			addr_offset = EEPROM_MAC_ADDR_8822BS;
++		else if (interface_type == RTW_PCIE)
++			addr_offset = EEPROM_MAC_ADDR_8822BE;
++		break;
++#endif /* CONFIG_RTL8822B */
++
++#ifdef CONFIG_RTL8821C
++	case RTL8821C:
++		if (interface_type == RTW_USB)
++			addr_offset = EEPROM_MAC_ADDR_8821CU;
++		else if (interface_type == RTW_SDIO)
++			addr_offset = EEPROM_MAC_ADDR_8821CS;
++		else if (interface_type == RTW_PCIE)
++			addr_offset = EEPROM_MAC_ADDR_8821CE;
++		break;
++#endif /* CONFIG_RTL8821C */
++
++#ifdef CONFIG_RTL8710B
++	case RTL8710B:
++		if (interface_type == RTW_USB)
++			addr_offset = EEPROM_MAC_ADDR_8710B;
++		break;
++#endif
++
++#ifdef CONFIG_RTL8192F
++	case RTL8192F:
++		if (interface_type == RTW_USB)
++			addr_offset = EEPROM_MAC_ADDR_8192FU;
++		else if (interface_type == RTW_SDIO)
++			addr_offset = EEPROM_MAC_ADDR_8192FS;
++		else if (interface_type == RTW_PCIE)
++			addr_offset = EEPROM_MAC_ADDR_8192FE;
++		break;
++#endif /* CONFIG_RTL8192F */
++
++#ifdef CONFIG_RTL8822C
++	case RTL8822C:
++		if (interface_type == RTW_USB)
++			addr_offset = EEPROM_MAC_ADDR_8822CU;
++		else if (interface_type == RTW_SDIO)
++			addr_offset = EEPROM_MAC_ADDR_8822CS;
++		else if (interface_type == RTW_PCIE)
++			addr_offset = EEPROM_MAC_ADDR_8822CE;
++		break;
++#endif /* CONFIG_RTL8822C */
++
++#ifdef CONFIG_RTL8814B
++	case RTL8814B:
++		if (interface_type == RTW_USB)
++			addr_offset = EEPROM_MAC_ADDR_8814BU;
++		else if (interface_type == RTW_PCIE)
++			addr_offset = EEPROM_MAC_ADDR_8814BE;
++		break;
++#endif /* CONFIG_RTL8814B */
++	}
++
++	if (addr_offset == -1) {
++		RTW_ERR("%s: unknown combination - chip_type:%u, interface:%u\n"
++			, __func__, rtw_get_chip_type(adapter), rtw_get_intf_type(adapter));
++	}
++
++	return addr_offset;
++}
++
++int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr)
++{
++	int ret = _FAIL;
++	int addr_offset;
++
++	addr_offset = hal_efuse_macaddr_offset(padapter);
++	if (addr_offset == -1)
++		goto exit;
++
++	ret = rtw_efuse_map_read(padapter, addr_offset, ETH_ALEN, mac_addr);
++
++exit:
++	return ret;
++}
++
++void rtw_dump_cur_efuse(PADAPTER padapter)
++{
++	int mapsize =0;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
++
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapsize, _FALSE);
++
++	if (mapsize <= 0 || mapsize > EEPROM_MAX_SIZE) {
++		RTW_ERR("wrong map size %d\n", mapsize);
++		return;
++	}
++
++#ifdef CONFIG_RTW_DEBUG
++	if (hal_data->efuse_file_status == EFUSE_FILE_LOADED)
++		RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "EFUSE FILE", hal_data->efuse_eeprom_data, mapsize);
++	else
++		RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "HW EFUSE", hal_data->efuse_eeprom_data, mapsize);
++#endif
++}
++
++
++#ifdef CONFIG_EFUSE_CONFIG_FILE
++u32 Hal_readPGDataFromConfigFile(PADAPTER padapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
++	u32 ret = _FALSE;
++	u32 maplen = 0;
++
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&maplen, _FALSE);
++
++	if (maplen < 256 || maplen > EEPROM_MAX_SIZE) {
++		RTW_ERR("eFuse length error :%d\n", maplen);
++		return _FALSE;
++	}	
++
++	ret = rtw_read_efuse_from_file(EFUSE_MAP_PATH, hal_data->efuse_eeprom_data, maplen);
++
++	hal_data->efuse_file_status = ((ret == _FAIL) ? EFUSE_FILE_FAILED : EFUSE_FILE_LOADED);
++
++	if (hal_data->efuse_file_status == EFUSE_FILE_LOADED)
++		rtw_dump_cur_efuse(padapter);
++
++	return ret;
++}
++
++u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
++	u32 ret = _FAIL;
++
++	if (rtw_read_macaddr_from_file(WIFIMAC_PATH, mac_addr) == _SUCCESS
++		&& rtw_check_invalid_mac_address(mac_addr, _TRUE) == _FALSE
++	) {
++		hal_data->macaddr_file_status = MACADDR_FILE_LOADED;
++		ret = _SUCCESS;
++	} else
++		hal_data->macaddr_file_status = MACADDR_FILE_FAILED;
++
++	return ret;
++}
++#endif /* CONFIG_EFUSE_CONFIG_FILE */
++
++int hal_config_macaddr(_adapter *adapter, bool autoload_fail)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	u8 addr[ETH_ALEN];
++	int addr_offset = hal_efuse_macaddr_offset(adapter);
++	u8 *hw_addr = NULL;
++	int ret = _SUCCESS;
++#if defined(CONFIG_RTL8822B) && defined(CONFIG_USB_HCI)
++	u8 ft_mac_addr[ETH_ALEN] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff}; /* FT USB2 for 8822B */
++#endif
++
++	if (autoload_fail)
++		goto bypass_hw_pg;
++
++	if (addr_offset != -1)
++		hw_addr = &hal_data->efuse_eeprom_data[addr_offset];
++
++#ifdef CONFIG_EFUSE_CONFIG_FILE
++	/* if the hw_addr is written by efuse file, set to NULL */
++	if (hal_data->efuse_file_status == EFUSE_FILE_LOADED)
++		hw_addr = NULL;
++#endif
++
++	if (!hw_addr) {
++		/* try getting hw pg data */
++		if (Hal_GetPhyEfuseMACAddr(adapter, addr) == _SUCCESS)
++			hw_addr = addr;
++	}
++
++#if defined(CONFIG_RTL8822B) && defined(CONFIG_USB_HCI)
++	if (_rtw_memcmp(hw_addr, ft_mac_addr, ETH_ALEN))
++		hw_addr[0] = 0xff;
++#endif
++
++	/* check hw pg data */
++	if (hw_addr && rtw_check_invalid_mac_address(hw_addr, _TRUE) == _FALSE) {
++		_rtw_memcpy(hal_data->EEPROMMACAddr, hw_addr, ETH_ALEN);
++		goto exit;
++	}
++
++bypass_hw_pg:
++
++#ifdef CONFIG_EFUSE_CONFIG_FILE
++	/* check wifi mac file */
++	if (Hal_ReadMACAddrFromFile(adapter, addr) == _SUCCESS) {
++		_rtw_memcpy(hal_data->EEPROMMACAddr, addr, ETH_ALEN);
++		goto exit;
++	}
++#endif
++
++	_rtw_memset(hal_data->EEPROMMACAddr, 0, ETH_ALEN);
++	ret = _FAIL;
++
++exit:
++	return ret;
++}
++
++#ifdef CONFIG_RF_POWER_TRIM
++u32 Array_kfreemap[] = {
++	0x08, 0xe,
++	0x06, 0xc,
++	0x04, 0xa,
++	0x02, 0x8,
++	0x00, 0x6,
++	0x03, 0x4,
++	0x05, 0x2,
++	0x07, 0x0,
++	0x09, 0x0,
++	0x0c, 0x0,
++};
++
++void rtw_bb_rf_gain_offset(_adapter *padapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct registry_priv  *registry_par = &padapter->registrypriv;
++	struct kfree_data_t *kfree_data = &pHalData->kfree_data;
++	u8		value = pHalData->EEPROMRFGainOffset;
++	u8		tmp = 0x3e;
++	u32		res, i = 0;
++	u32		ArrayLen	= sizeof(Array_kfreemap) / sizeof(u32);
++	u32		*Array = Array_kfreemap;
++	u32		v1 = 0, v2 = 0, GainValue = 0, target = 0;
++
++	if (registry_par->RegPwrTrimEnable == 2) {
++		RTW_INFO("Registry kfree default force disable.\n");
++		return;
++	}
++
++#if defined(CONFIG_RTL8723B)
++	if (value & BIT4 && (registry_par->RegPwrTrimEnable == 1)) {
++		RTW_INFO("Offset RF Gain.\n");
++		RTW_INFO("Offset RF Gain.  pHalData->EEPROMRFGainVal=0x%x\n", pHalData->EEPROMRFGainVal);
++
++		if (pHalData->EEPROMRFGainVal != 0xff) {
++
++			if (pHalData->ant_path == RF_PATH_A)
++				GainValue = (pHalData->EEPROMRFGainVal & 0x0f);
++
++			else
++				GainValue = (pHalData->EEPROMRFGainVal & 0xf0) >> 4;
++			RTW_INFO("Ant PATH_%d GainValue Offset = 0x%x\n", (pHalData->ant_path == RF_PATH_A) ? (RF_PATH_A) : (RF_PATH_B), GainValue);
++
++			for (i = 0; i < ArrayLen; i += 2) {
++				/* RTW_INFO("ArrayLen in =%d ,Array 1 =0x%x ,Array2 =0x%x\n",i,Array[i],Array[i]+1); */
++				v1 = Array[i];
++				v2 = Array[i + 1];
++				if (v1 == GainValue) {
++					RTW_INFO("Offset RF Gain. got v1 =0x%x ,v2 =0x%x\n", v1, v2);
++					target = v2;
++					break;
++				}
++			}
++			RTW_INFO("pHalData->EEPROMRFGainVal=0x%x ,Gain offset Target Value=0x%x\n", pHalData->EEPROMRFGainVal, target);
++
++			res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
++			RTW_INFO("Offset RF Gain. before reg 0x7f=0x%08x\n", res);
++			phy_set_rf_reg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18 | BIT17 | BIT16 | BIT15, target);
++			res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
++
++			RTW_INFO("Offset RF Gain. After reg 0x7f=0x%08x\n", res);
++
++		} else
++
++			RTW_INFO("Offset RF Gain.  pHalData->EEPROMRFGainVal=0x%x	!= 0xff, didn't run Kfree\n", pHalData->EEPROMRFGainVal);
++	} else
++		RTW_INFO("Using the default RF gain.\n");
++
++#elif defined(CONFIG_RTL8188E)
++	if (value & BIT4 && (registry_par->RegPwrTrimEnable == 1)) {
++		RTW_INFO("8188ES Offset RF Gain.\n");
++		RTW_INFO("8188ES Offset RF Gain. EEPROMRFGainVal=0x%x\n",
++			 pHalData->EEPROMRFGainVal);
++
++		if (pHalData->EEPROMRFGainVal != 0xff) {
++			res = rtw_hal_read_rfreg(padapter, RF_PATH_A,
++					 REG_RF_BB_GAIN_OFFSET, 0xffffffff);
++
++			RTW_INFO("Offset RF Gain. reg 0x55=0x%x\n", res);
++			res &= 0xfff87fff;
++
++			res |= (pHalData->EEPROMRFGainVal & 0x0f) << 15;
++			RTW_INFO("Offset RF Gain. res=0x%x\n", res);
++
++			rtw_hal_write_rfreg(padapter, RF_PATH_A,
++					    REG_RF_BB_GAIN_OFFSET,
++					    RF_GAIN_OFFSET_MASK, res);
++		} else {
++			RTW_INFO("Offset RF Gain. EEPROMRFGainVal=0x%x == 0xff, didn't run Kfree\n",
++				 pHalData->EEPROMRFGainVal);
++		}
++	} else
++		RTW_INFO("Using the default RF gain.\n");
++#else
++	/* TODO: call this when channel switch */
++	if (kfree_data->flag & KFREE_FLAG_ON)
++		rtw_rf_apply_tx_gain_offset(padapter, 6); /* input ch6 to select BB_GAIN_2G */
++#endif
++
++}
++#endif /*CONFIG_RF_POWER_TRIM */
++
++bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data)
++{
++#ifdef CONFIG_RF_POWER_TRIM
++	int i, j;
++
++	for (i = 0; i < BB_GAIN_NUM; i++)
++		for (j = 0; j < RF_PATH_MAX; j++)
++			if (data->bb_gain[i][j] != 0)
++				return 0;
++#endif
++	return 1;
++}
++
++#ifdef CONFIG_USB_RX_AGGREGATION
++void rtw_set_usb_agg_by_mode_normal(_adapter *padapter, u8 cur_wireless_mode)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	if (cur_wireless_mode < WIRELESS_11_24N
++	    && cur_wireless_mode > 0) { /* ABG mode */
++#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
++		u32 remainder = 0;
++		u8 quotient = 0;
++
++		remainder = MAX_RECVBUF_SZ % (4 * 1024);
++		quotient = (u8)(MAX_RECVBUF_SZ >> 12);
++
++		if (quotient > 5) {
++			pHalData->rxagg_usb_size = 0x6;
++			pHalData->rxagg_usb_timeout = 0x10;
++		} else {
++			if (remainder >= 2048) {
++				pHalData->rxagg_usb_size = quotient;
++				pHalData->rxagg_usb_timeout = 0x10;
++			} else {
++				pHalData->rxagg_usb_size = (quotient - 1);
++				pHalData->rxagg_usb_timeout = 0x10;
++			}
++		}
++#else /* !CONFIG_PREALLOC_RX_SKB_BUFFER */
++		if (0x6 != pHalData->rxagg_usb_size || 0x10 != pHalData->rxagg_usb_timeout) {
++			pHalData->rxagg_usb_size = 0x6;
++			pHalData->rxagg_usb_timeout = 0x10;
++			rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
++				pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
++		}
++#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
++
++	} else if (cur_wireless_mode >= WIRELESS_11_24N
++		   && cur_wireless_mode <= WIRELESS_MODE_MAX) { /* N AC mode */
++#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
++		u32 remainder = 0;
++		u8 quotient = 0;
++
++		remainder = MAX_RECVBUF_SZ % (4 * 1024);
++		quotient = (u8)(MAX_RECVBUF_SZ >> 12);
++
++		if (quotient > 5) {
++			pHalData->rxagg_usb_size = 0x5;
++			pHalData->rxagg_usb_timeout = 0x20;
++		} else {
++			if (remainder >= 2048) {
++				pHalData->rxagg_usb_size = quotient;
++				pHalData->rxagg_usb_timeout = 0x10;
++			} else {
++				pHalData->rxagg_usb_size = (quotient - 1);
++				pHalData->rxagg_usb_timeout = 0x10;
++			}
++		}
++#else /* !CONFIG_PREALLOC_RX_SKB_BUFFER */
++		if ((0x5 != pHalData->rxagg_usb_size) || (0x20 != pHalData->rxagg_usb_timeout)) {
++			pHalData->rxagg_usb_size = 0x5;
++			pHalData->rxagg_usb_timeout = 0x20;
++			rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
++				pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
++		}
++#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
++
++	} else {
++		/* RTW_INFO("%s: Unknow wireless mode(0x%x)\n",__func__,padapter->mlmeextpriv.cur_wireless_mode); */
++	}
++}
++
++void rtw_set_usb_agg_by_mode_customer(_adapter *padapter, u8 cur_wireless_mode, u8 UsbDmaSize, u8 Legacy_UsbDmaSize)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	if (cur_wireless_mode < WIRELESS_11_24N
++	    && cur_wireless_mode > 0) { /* ABG mode */
++		if (Legacy_UsbDmaSize != pHalData->rxagg_usb_size
++		    || 0x10 != pHalData->rxagg_usb_timeout) {
++			pHalData->rxagg_usb_size = Legacy_UsbDmaSize;
++			pHalData->rxagg_usb_timeout = 0x10;
++			rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
++				pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
++		}
++	} else if (cur_wireless_mode >= WIRELESS_11_24N
++		   && cur_wireless_mode <= WIRELESS_MODE_MAX) { /* N AC mode */
++		if (UsbDmaSize != pHalData->rxagg_usb_size
++		    || 0x20 != pHalData->rxagg_usb_timeout) {
++			pHalData->rxagg_usb_size = UsbDmaSize;
++			pHalData->rxagg_usb_timeout = 0x20;
++			rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
++				pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
++		}
++	} else {
++		/* RTW_INFO("%s: Unknown wireless mode(0x%x)\n",__func__,padapter->mlmeextpriv.cur_wireless_mode); */
++	}
++}
++
++void rtw_set_usb_agg_by_mode(_adapter *padapter, u8 cur_wireless_mode)
++{
++#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
++	rtw_set_usb_agg_by_mode_customer(padapter, cur_wireless_mode, 0x3, 0x3);
++	return;
++#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
++
++	rtw_set_usb_agg_by_mode_normal(padapter, cur_wireless_mode);
++}
++#endif /* CONFIG_USB_RX_AGGREGATION */
++
++/* To avoid RX affect TX throughput */
++void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer)
++{
++	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
++	struct mlme_priv		*pmlmepriv = &(padapter->mlmepriv);
++	struct registry_priv *registry_par = &padapter->registrypriv;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	u8 cur_wireless_mode = WIRELESS_INVALID;
++
++#ifdef CONFIG_USB_RX_AGGREGATION
++	if (!registry_par->dynamic_agg_enable)
++		return;
++
++#ifdef RTW_HALMAC
++	if (IS_HARDWARE_TYPE_8822BU(padapter) || IS_HARDWARE_TYPE_8821CU(padapter) 
++		|| IS_HARDWARE_TYPE_8822CU(padapter) || IS_HARDWARE_TYPE_8814BU(padapter))
++		rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, NULL);
++#else /* !RTW_HALMAC */
++	if (IS_HARDWARE_TYPE_8821U(padapter)) { /* || IS_HARDWARE_TYPE_8192EU(padapter)) */
++		/* This AGG_PH_TH only for UsbRxAggMode == USB_RX_AGG_USB */
++		if ((pHalData->rxagg_mode == RX_AGG_USB) && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) {
++			if (pdvobjpriv->traffic_stat.cur_tx_tp > 2 && pdvobjpriv->traffic_stat.cur_rx_tp < 30)
++				rtw_write16(padapter , REG_RXDMA_AGG_PG_TH , 0x1010);
++			else if (pdvobjpriv->traffic_stat.last_tx_bytes > 220000 && pdvobjpriv->traffic_stat.cur_rx_tp < 30)
++				rtw_write16(padapter , REG_RXDMA_AGG_PG_TH , 0x1006);
++			else
++				rtw_write16(padapter, REG_RXDMA_AGG_PG_TH, 0x2005); /* dmc agg th 20K */
++
++			/* RTW_INFO("TX_TP=%u, RX_TP=%u\n", pdvobjpriv->traffic_stat.cur_tx_tp, pdvobjpriv->traffic_stat.cur_rx_tp); */
++		}
++	} else if (IS_HARDWARE_TYPE_8812(padapter)) {
++#ifdef CONFIG_CONCURRENT_MODE
++		u8 i;
++		_adapter *iface;
++		u8 bassocaed = _FALSE;
++		struct mlme_ext_priv *mlmeext;
++
++		for (i = 0; i < pdvobjpriv->iface_nums; i++) {
++			iface = pdvobjpriv->padapters[i];
++			mlmeext = &iface->mlmeextpriv;
++			if (rtw_linked_check(iface) == _TRUE) {
++				if (mlmeext->cur_wireless_mode >= cur_wireless_mode)
++					cur_wireless_mode = mlmeext->cur_wireless_mode;
++				bassocaed = _TRUE;
++			}
++		}
++		if (bassocaed)
++#endif
++			rtw_set_usb_agg_by_mode(padapter, cur_wireless_mode);
++#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
++	} else {
++		rtw_set_usb_agg_by_mode(padapter, cur_wireless_mode);
++#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
++	}
++#endif /* RTW_HALMAC */
++#endif /* CONFIG_USB_RX_AGGREGATION */
++
++}
++
++/* bus-agg check for SoftAP mode */
++inline u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qsel)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	u8 chk_rst = _SUCCESS;
++
++	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
++		return chk_rst;
++
++	/* if((pre_qsel == 0xFF)||(next_qsel== 0xFF)) */
++	/*	return chk_rst; */
++
++	if (((pre_qsel == QSLT_HIGH) || ((next_qsel == QSLT_HIGH)))
++	    && (pre_qsel != next_qsel)) {
++		/* RTW_INFO("### bus-agg break cause of qsel misatch, pre_qsel=0x%02x,next_qsel=0x%02x ###\n", */
++		/*	pre_qsel,next_qsel); */
++		chk_rst = _FAIL;
++	}
++	return chk_rst;
++}
++
++/*
++ * Description:
++ * dump_TX_FIFO: This is only used to dump TX_FIFO for debug WoW mode offload
++ * contant.
++ *
++ * Input:
++ * adapter: adapter pointer.
++ * page_num: The max. page number that user want to dump.
++ * page_size: page size of each page. eg. 128 bytes, 256 bytes, 512byte.
++ */
++void dump_TX_FIFO(_adapter *padapter, u8 page_num, u16 page_size)
++{
++
++	int i;
++	u8 val = 0;
++	u8 base = 0;
++	u32 addr = 0;
++	u32 count = (page_size / 8);
++
++	if (page_num <= 0) {
++		RTW_INFO("!!%s: incorrect input page_num paramter!\n", __func__);
++		return;
++	}
++
++	if (page_size < 128 || page_size > 512) {
++		RTW_INFO("!!%s: incorrect input page_size paramter!\n", __func__);
++		return;
++	}
++
++	RTW_INFO("+%s+\n", __func__);
++	val = rtw_read8(padapter, 0x106);
++	rtw_write8(padapter, 0x106, 0x69);
++	RTW_INFO("0x106: 0x%02x\n", val);
++	base = rtw_read8(padapter, 0x209);
++	RTW_INFO("0x209: 0x%02x\n", base);
++
++	addr = ((base)*page_size) / 8;
++	for (i = 0 ; i < page_num * count ; i += 2) {
++		rtw_write32(padapter, 0x140, addr + i);
++		printk(" %08x %08x ", rtw_read32(padapter, 0x144), rtw_read32(padapter, 0x148));
++		rtw_write32(padapter, 0x140, addr + i + 1);
++		printk(" %08x %08x\n", rtw_read32(padapter, 0x144), rtw_read32(padapter, 0x148));
++	}
++}
++
++#ifdef CONFIG_GPIO_API
++u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num)
++{
++	u8 value = 0;
++	u8 direction = 0;
++	u32 gpio_pin_input_val = REG_GPIO_PIN_CTRL;
++	u32 gpio_pin_output_val = REG_GPIO_PIN_CTRL + 1;
++	u32 gpio_pin_output_en = REG_GPIO_PIN_CTRL + 2;
++	u8 gpio_num_to_set = gpio_num;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++
++	if (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL)
++		return value;
++
++	rtw_ps_deny(adapter, PS_DENY_IOCTL);
++
++	RTW_INFO("rf_pwrstate=0x%02x\n", pwrpriv->rf_pwrstate);
++	LeaveAllPowerSaveModeDirect(adapter);
++
++	if (gpio_num > 7) {
++		gpio_pin_input_val = REG_GPIO_PIN_CTRL_2;
++		gpio_pin_output_val = REG_GPIO_PIN_CTRL_2 + 1;
++		gpio_pin_output_en = REG_GPIO_PIN_CTRL_2 + 2;
++		gpio_num_to_set = gpio_num - 8;
++	}
++
++	/* Read GPIO Direction */
++	direction = (rtw_read8(adapter, gpio_pin_output_en) & BIT(gpio_num_to_set)) >> gpio_num_to_set;
++
++	/* According the direction to read register value */
++	if (direction)
++		value =  (rtw_read8(adapter, gpio_pin_output_val) & BIT(gpio_num_to_set)) >> gpio_num_to_set;
++	else
++		value =  (rtw_read8(adapter, gpio_pin_input_val) & BIT(gpio_num_to_set)) >> gpio_num_to_set;
++
++	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
++	RTW_INFO("%s direction=%d value=%d\n", __FUNCTION__, direction, value);
++
++	return value;
++}
++
++int  rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh)
++{
++	u8 direction = 0;
++	u8 res = -1;
++	u32 gpio_pin_output_val = REG_GPIO_PIN_CTRL + 1;
++	u32 gpio_pin_output_en = REG_GPIO_PIN_CTRL + 2;
++	u8 gpio_num_to_set = gpio_num;
++
++	if (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL)
++		return -1;
++
++	rtw_ps_deny(adapter, PS_DENY_IOCTL);
++
++	LeaveAllPowerSaveModeDirect(adapter);
++
++	if (gpio_num > 7) {
++		gpio_pin_output_val = REG_GPIO_PIN_CTRL_2 + 1;
++		gpio_pin_output_en = REG_GPIO_PIN_CTRL_2 + 2;
++		gpio_num_to_set = gpio_num - 8;
++	}
++
++	/* Read GPIO direction */
++	direction = (rtw_read8(adapter, gpio_pin_output_en) & BIT(gpio_num_to_set)) >> gpio_num_to_set;
++
++	/* If GPIO is output direction, setting value. */
++	if (direction) {
++		if (isHigh)
++			rtw_write8(adapter, gpio_pin_output_val, rtw_read8(adapter, gpio_pin_output_val) | BIT(gpio_num_to_set));
++		else
++			rtw_write8(adapter, gpio_pin_output_val, rtw_read8(adapter, gpio_pin_output_val) & ~BIT(gpio_num_to_set));
++
++		RTW_INFO("%s Set gpio %x[%d]=%d\n", __FUNCTION__, REG_GPIO_PIN_CTRL + 1, gpio_num, isHigh);
++		res = 0;
++	} else {
++		RTW_INFO("%s The gpio is input,not be set!\n", __FUNCTION__);
++		res = -1;
++	}
++
++	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
++	return res;
++}
++
++int rtw_hal_config_gpio(_adapter *adapter, u8 gpio_num, bool isOutput)
++{
++	u32 gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL + 2;
++	u8 gpio_num_to_set = gpio_num;
++
++	if (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL)
++		return -1;
++
++	RTW_INFO("%s gpio_num =%d direction=%d\n", __FUNCTION__, gpio_num, isOutput);
++
++	rtw_ps_deny(adapter, PS_DENY_IOCTL);
++
++	LeaveAllPowerSaveModeDirect(adapter);
++
++	rtw_hal_gpio_multi_func_reset(adapter, gpio_num);
++
++	if (gpio_num > 7) {
++		gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL_2 + 2;
++		gpio_num_to_set = gpio_num - 8;
++	}
++
++	if (isOutput)
++		rtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) | BIT(gpio_num_to_set));
++	else
++		rtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) & ~BIT(gpio_num_to_set));
++
++	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
++
++	return 0;
++}
++int rtw_hal_register_gpio_interrupt(_adapter *adapter, int gpio_num, void(*callback)(u8 level))
++{
++	u8 value;
++	u8 direction;
++	PHAL_DATA_TYPE phal = GET_HAL_DATA(adapter);
++
++	if (IS_HARDWARE_TYPE_8188E(adapter)) {
++		if (gpio_num > 7 || gpio_num < 4) {
++			RTW_PRINT("%s The gpio number does not included 4~7.\n", __FUNCTION__);
++			return -1;
++		}
++	}
++
++	rtw_ps_deny(adapter, PS_DENY_IOCTL);
++
++	LeaveAllPowerSaveModeDirect(adapter);
++
++	/* Read GPIO direction */
++	direction = (rtw_read8(adapter, REG_GPIO_PIN_CTRL + 2) & BIT(gpio_num)) >> gpio_num;
++	if (direction) {
++		RTW_PRINT("%s Can't register output gpio as interrupt.\n", __FUNCTION__);
++		return -1;
++	}
++
++	/* Config GPIO Mode */
++	rtw_write8(adapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 3) | BIT(gpio_num));
++
++	/* Register GPIO interrupt handler*/
++	adapter->gpiointpriv.callback[gpio_num] = callback;
++
++	/* Set GPIO interrupt mode, 0:positive edge, 1:negative edge */
++	value = rtw_read8(adapter, REG_GPIO_PIN_CTRL) & BIT(gpio_num);
++	adapter->gpiointpriv.interrupt_mode = rtw_read8(adapter, REG_HSIMR + 2) ^ value;
++	rtw_write8(adapter, REG_GPIO_INTM, adapter->gpiointpriv.interrupt_mode);
++
++	/* Enable GPIO interrupt */
++	adapter->gpiointpriv.interrupt_enable_mask = rtw_read8(adapter, REG_HSIMR + 2) | BIT(gpio_num);
++	rtw_write8(adapter, REG_HSIMR + 2, adapter->gpiointpriv.interrupt_enable_mask);
++
++	rtw_hal_update_hisr_hsisr_ind(adapter, 1);
++
++	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
++
++	return 0;
++}
++int rtw_hal_disable_gpio_interrupt(_adapter *adapter, int gpio_num)
++{
++	u8 value;
++	u8 direction;
++	PHAL_DATA_TYPE phal = GET_HAL_DATA(adapter);
++
++	if (IS_HARDWARE_TYPE_8188E(adapter)) {
++		if (gpio_num > 7 || gpio_num < 4) {
++			RTW_INFO("%s The gpio number does not included 4~7.\n", __FUNCTION__);
++			return -1;
++		}
++	}
++
++	rtw_ps_deny(adapter, PS_DENY_IOCTL);
++
++	LeaveAllPowerSaveModeDirect(adapter);
++
++	/* Config GPIO Mode */
++	rtw_write8(adapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(gpio_num));
++
++	/* Unregister GPIO interrupt handler*/
++	adapter->gpiointpriv.callback[gpio_num] = NULL;
++
++	/* Reset GPIO interrupt mode, 0:positive edge, 1:negative edge */
++	adapter->gpiointpriv.interrupt_mode = rtw_read8(adapter, REG_GPIO_INTM) & ~BIT(gpio_num);
++	rtw_write8(adapter, REG_GPIO_INTM, 0x00);
++
++	/* Disable GPIO interrupt */
++	adapter->gpiointpriv.interrupt_enable_mask = rtw_read8(adapter, REG_HSIMR + 2) & ~BIT(gpio_num);
++	rtw_write8(adapter, REG_HSIMR + 2, adapter->gpiointpriv.interrupt_enable_mask);
++
++	if (!adapter->gpiointpriv.interrupt_enable_mask)
++		rtw_hal_update_hisr_hsisr_ind(adapter, 0);
++
++	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
++
++	return 0;
++}
++#endif
++
++s8 rtw_hal_ch_sw_iqk_info_search(_adapter *padapter, u8 central_chnl, u8 bw_mode)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++	u8 i;
++
++	for (i = 0; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++) {
++		if ((pHalData->iqk_reg_backup[i].central_chnl != 0)) {
++			if ((pHalData->iqk_reg_backup[i].central_chnl == central_chnl)
++			    && (pHalData->iqk_reg_backup[i].bw_mode == bw_mode))
++				return i;
++		}
++	}
++
++	return -1;
++}
++
++void rtw_hal_ch_sw_iqk_info_backup(_adapter *padapter)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++	s8 res;
++	u8 i;
++
++	/* If it's an existed record, overwrite it */
++	res = rtw_hal_ch_sw_iqk_info_search(padapter, pHalData->current_channel, pHalData->current_channel_bw);
++	if ((res >= 0) && (res < MAX_IQK_INFO_BACKUP_CHNL_NUM)) {
++		rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8 *)&(pHalData->iqk_reg_backup[res]));
++		return;
++	}
++
++	/* Search for the empty record to use */
++	for (i = 0; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++) {
++		if (pHalData->iqk_reg_backup[i].central_chnl == 0) {
++			rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8 *)&(pHalData->iqk_reg_backup[i]));
++			return;
++		}
++	}
++
++	/* Else, overwrite the oldest record */
++	for (i = 1; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++)
++		_rtw_memcpy(&(pHalData->iqk_reg_backup[i - 1]), &(pHalData->iqk_reg_backup[i]), sizeof(struct hal_iqk_reg_backup));
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8 *)&(pHalData->iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM - 1]));
++}
++
++void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case)
++{
++	rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_RESTORE, &ch_sw_use_case);
++}
++
++void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter)
++{
++	u32	mac_cck_ok = 0, mac_ofdm_ok = 0, mac_ht_ok = 0, mac_vht_ok = 0;
++	u32	mac_cck_err = 0, mac_ofdm_err = 0, mac_ht_err = 0, mac_vht_err = 0;
++	u32	mac_cck_fa = 0, mac_ofdm_fa = 0, mac_ht_fa = 0;
++	u32	DropPacket = 0;
++
++	if (!rx_counter) {
++		rtw_warn_on(1);
++		return;
++	}
++	if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter))
++		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
++
++	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x3);
++	mac_cck_ok	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	  */
++	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0);
++	mac_ofdm_ok	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
++	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x6);
++	mac_ht_ok	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
++	mac_vht_ok	= 0;
++	if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
++		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0);
++		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1);
++		mac_vht_ok	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/
++		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
++	}
++
++	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x4);
++	mac_cck_err	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
++	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1);
++	mac_ofdm_err	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
++	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x7);
++	mac_ht_err	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]		 */
++	mac_vht_err	= 0;
++	if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
++		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1);
++		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1);
++		mac_vht_err	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/
++		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
++	}
++
++	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x5);
++	mac_cck_fa	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
++	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x2);
++	mac_ofdm_fa	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
++	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x9);
++	mac_ht_fa	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]		 */
++
++	/* Mac_DropPacket */
++	rtw_write32(padapter, REG_RXERR_RPT, (rtw_read32(padapter, REG_RXERR_RPT) & 0x0FFFFFFF) | Mac_DropPacket);
++	DropPacket = rtw_read32(padapter, REG_RXERR_RPT) & 0x0000FFFF;
++
++	rx_counter->rx_pkt_ok = mac_cck_ok + mac_ofdm_ok + mac_ht_ok + mac_vht_ok;
++	rx_counter->rx_pkt_crc_error = mac_cck_err + mac_ofdm_err + mac_ht_err + mac_vht_err;
++	rx_counter->rx_cck_fa = mac_cck_fa;
++	rx_counter->rx_ofdm_fa = mac_ofdm_fa;
++	rx_counter->rx_ht_fa = mac_ht_fa;
++	rx_counter->rx_pkt_drop = DropPacket;
++}
++void rtw_reset_mac_rx_counters(_adapter *padapter)
++{
++
++	/* If no packet rx, MaxRx clock be gating ,BIT_DISGCLK bit19 set 1 for fix*/
++	if (IS_HARDWARE_TYPE_8703B(padapter) ||
++		IS_HARDWARE_TYPE_8723D(padapter) ||
++		IS_HARDWARE_TYPE_8188F(padapter) ||
++		IS_HARDWARE_TYPE_8188GTV(padapter) ||
++		IS_HARDWARE_TYPE_8192F(padapter) ||
++		IS_HARDWARE_TYPE_8822C(padapter))
++		phy_set_mac_reg(padapter, REG_RCR, BIT19, 0x1);
++
++	/* reset mac counter */
++	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x1);
++	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x0);
++}
++
++void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter)
++{
++	u32 cckok = 0, cckcrc = 0, ofdmok = 0, ofdmcrc = 0, htok = 0, htcrc = 0, OFDM_FA = 0, CCK_FA = 0, vht_ok = 0, vht_err = 0;
++	if (!rx_counter) {
++		rtw_warn_on(1);
++		return;
++	}
++	if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
++		cckok	= phy_query_bb_reg(padapter, 0xF04, 0x3FFF);	     /* [13:0] */
++		ofdmok	= phy_query_bb_reg(padapter, 0xF14, 0x3FFF);	     /* [13:0] */
++		htok		= phy_query_bb_reg(padapter, 0xF10, 0x3FFF);     /* [13:0] */
++		vht_ok	= phy_query_bb_reg(padapter, 0xF0C, 0x3FFF);     /* [13:0] */
++		cckcrc	= phy_query_bb_reg(padapter, 0xF04, 0x3FFF0000); /* [29:16]	 */
++		ofdmcrc	= phy_query_bb_reg(padapter, 0xF14, 0x3FFF0000); /* [29:16] */
++		htcrc	= phy_query_bb_reg(padapter, 0xF10, 0x3FFF0000); /* [29:16] */
++		vht_err	= phy_query_bb_reg(padapter, 0xF0C, 0x3FFF0000); /* [29:16] */
++		CCK_FA	= phy_query_bb_reg(padapter, 0xA5C, bMaskLWord);
++		OFDM_FA	= phy_query_bb_reg(padapter, 0xF48, bMaskLWord);
++	} else if(IS_HARDWARE_TYPE_JAGUAR3(padapter)){
++		cckok = phy_query_bb_reg(padapter, 0x2c04, 0xffff);
++		ofdmok = phy_query_bb_reg(padapter, 0x2c14, 0xffff);
++		htok = phy_query_bb_reg(padapter, 0x2c10, 0xffff);
++		vht_ok = phy_query_bb_reg(padapter, 0x2c0c, 0xffff);
++		cckcrc = phy_query_bb_reg(padapter, 0x2c04, 0xffff0000);
++		ofdmcrc = phy_query_bb_reg(padapter, 0x2c14, 0xffff0000);
++		htcrc = phy_query_bb_reg(padapter, 0x2c10, 0xffff0000);
++		vht_err = phy_query_bb_reg(padapter, 0x2c0c, 0xffff0000);
++		CCK_FA	= phy_query_bb_reg(padapter, 0x1a5c, bMaskLWord);
++		OFDM_FA = phy_query_bb_reg(padapter, 0x2d00, bMaskLWord) - phy_query_bb_reg(padapter, 0x2de0, bMaskLWord);
++
++	} else {
++		cckok	= phy_query_bb_reg(padapter, 0xF88, bMaskDWord);
++		ofdmok	= phy_query_bb_reg(padapter, 0xF94, bMaskLWord);
++		htok		= phy_query_bb_reg(padapter, 0xF90, bMaskLWord);
++		vht_ok	= 0;
++		cckcrc	= phy_query_bb_reg(padapter, 0xF84, bMaskDWord);
++		ofdmcrc	= phy_query_bb_reg(padapter, 0xF94, bMaskHWord);
++		htcrc	= phy_query_bb_reg(padapter, 0xF90, bMaskHWord);
++		vht_err	= 0;
++		OFDM_FA = phy_query_bb_reg(padapter, 0xCF0, bMaskLWord) + phy_query_bb_reg(padapter, 0xCF2, bMaskLWord) +
++			phy_query_bb_reg(padapter, 0xDA2, bMaskLWord) + phy_query_bb_reg(padapter, 0xDA4, bMaskLWord) +
++			phy_query_bb_reg(padapter, 0xDA6, bMaskLWord) + phy_query_bb_reg(padapter, 0xDA8, bMaskLWord);
++
++		CCK_FA = (rtw_read8(padapter, 0xA5B) << 8) | (rtw_read8(padapter, 0xA5C));
++	}
++
++	rx_counter->rx_pkt_ok = cckok + ofdmok + htok + vht_ok;
++	rx_counter->rx_pkt_crc_error = cckcrc + ofdmcrc + htcrc + vht_err;
++	rx_counter->rx_ofdm_fa = OFDM_FA;
++	rx_counter->rx_cck_fa = CCK_FA;
++
++}
++
++void rtw_reset_phy_trx_ok_counters(_adapter *padapter)
++{
++	if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
++		phy_set_bb_reg(padapter, 0xB58, BIT0, 0x1);
++		phy_set_bb_reg(padapter, 0xB58, BIT0, 0x0);
++	} else if(IS_HARDWARE_TYPE_JAGUAR3(padapter)) {
++		phy_set_bb_reg(padapter, 0x1EB4, BIT25, 0x1);
++		phy_set_bb_reg(padapter, 0x1EB4, BIT25, 0x0);
++	} else {
++		phy_set_bb_reg(padapter, 0xF14, BIT16, 0x1);
++		phy_set_bb_reg(padapter, 0xF14, BIT16, 0x0);
++	}
++}
++
++void rtw_reset_phy_rx_counters(_adapter *padapter)
++{
++	/* reset phy counter */
++	if (IS_HARDWARE_TYPE_JAGUAR3(padapter)) {
++		/* reset CCK FA counter */
++		phy_set_bb_reg(padapter, 0x1a2c, BIT(15) | BIT(14), 0);
++		phy_set_bb_reg(padapter, 0x1a2c, BIT(15) | BIT(14), 2);
++
++		/* reset CCK CCA counter */
++		phy_set_bb_reg(padapter, 0x1a2c, BIT(13) | BIT(12), 0);
++		phy_set_bb_reg(padapter, 0x1a2c, BIT(13) | BIT(12), 2);
++		rtw_reset_phy_trx_ok_counters(padapter);
++
++	} else if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
++		rtw_reset_phy_trx_ok_counters(padapter);
++
++		phy_set_bb_reg(padapter, 0x9A4, BIT17, 0x1);/* reset  OFDA FA counter */
++		phy_set_bb_reg(padapter, 0x9A4, BIT17, 0x0);
++
++		phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset  CCK FA counter */
++		phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1);
++	} else {
++		phy_set_bb_reg(padapter, 0xF14, BIT16, 0x1);
++		rtw_msleep_os(10);
++		phy_set_bb_reg(padapter, 0xF14, BIT16, 0x0);
++
++		phy_set_bb_reg(padapter, 0xD00, BIT27, 0x1);/* reset  OFDA FA counter */
++		phy_set_bb_reg(padapter, 0xC0C, BIT31, 0x1);/* reset  OFDA FA counter */
++		phy_set_bb_reg(padapter, 0xD00, BIT27, 0x0);
++		phy_set_bb_reg(padapter, 0xC0C, BIT31, 0x0);
++
++		phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset  CCK FA counter */
++		phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1);
++	}
++}
++#ifdef DBG_RX_COUNTER_DUMP
++void rtw_dump_drv_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter)
++{
++	struct recv_priv *precvpriv = &padapter->recvpriv;
++	if (!rx_counter) {
++		rtw_warn_on(1);
++		return;
++	}
++	rx_counter->rx_pkt_ok = padapter->drv_rx_cnt_ok;
++	rx_counter->rx_pkt_crc_error = padapter->drv_rx_cnt_crcerror;
++	rx_counter->rx_pkt_drop = precvpriv->rx_drop - padapter->drv_rx_cnt_drop;
++}
++void rtw_reset_drv_rx_counters(_adapter *padapter)
++{
++	struct recv_priv *precvpriv = &padapter->recvpriv;
++	padapter->drv_rx_cnt_ok = 0;
++	padapter->drv_rx_cnt_crcerror = 0;
++	padapter->drv_rx_cnt_drop = precvpriv->rx_drop;
++}
++void rtw_dump_phy_rxcnts_preprocess(_adapter *padapter, u8 rx_cnt_mode)
++{
++	u8 initialgain;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
++
++	if ((!(padapter->dump_rx_cnt_mode & DUMP_PHY_RX_COUNTER)) && (rx_cnt_mode & DUMP_PHY_RX_COUNTER)) {
++		rtw_hal_get_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, NULL);
++		RTW_INFO("%s CurIGValue:0x%02x\n", __FUNCTION__, initialgain);
++		rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);
++		/*disable dynamic functions, such as high power, DIG*/
++		rtw_phydm_ability_backup(padapter);
++		rtw_phydm_func_clr(padapter, (ODM_BB_DIG | ODM_BB_FA_CNT));
++	} else if ((padapter->dump_rx_cnt_mode & DUMP_PHY_RX_COUNTER) && (!(rx_cnt_mode & DUMP_PHY_RX_COUNTER))) {
++		/* turn on phy-dynamic functions */
++		rtw_phydm_ability_restore(padapter);
++		initialgain = 0xff; /* restore RX GAIN */
++		rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);
++
++	}
++}
++
++void rtw_dump_rx_counters(_adapter *padapter)
++{
++	struct dbg_rx_counter rx_counter;
++
++	if (padapter->dump_rx_cnt_mode & DUMP_DRV_RX_COUNTER) {
++		_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
++		rtw_dump_drv_rx_counters(padapter, &rx_counter);
++		RTW_INFO("Drv Received packet OK:%d CRC error:%d Drop Packets: %d\n",
++			rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_pkt_drop);
++		rtw_reset_drv_rx_counters(padapter);
++	}
++
++	if (padapter->dump_rx_cnt_mode & DUMP_MAC_RX_COUNTER) {
++		_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
++		rtw_dump_mac_rx_counters(padapter, &rx_counter);
++		RTW_INFO("Mac Received packet OK:%d CRC error:%d FA Counter: %d Drop Packets: %d\n",
++			 rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error,
++			rx_counter.rx_cck_fa + rx_counter.rx_ofdm_fa + rx_counter.rx_ht_fa,
++			 rx_counter.rx_pkt_drop);
++		rtw_reset_mac_rx_counters(padapter);
++	}
++
++	if (padapter->dump_rx_cnt_mode & DUMP_PHY_RX_COUNTER) {
++		_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
++		rtw_dump_phy_rx_counters(padapter, &rx_counter);
++		/* RTW_INFO("%s: OFDM_FA =%d\n", __FUNCTION__, rx_counter.rx_ofdm_fa); */
++		/* RTW_INFO("%s: CCK_FA =%d\n", __FUNCTION__, rx_counter.rx_cck_fa); */
++		RTW_INFO("Phy Received packet OK:%d CRC error:%d FA Counter: %d\n", rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error,
++			 rx_counter.rx_ofdm_fa + rx_counter.rx_cck_fa);
++		rtw_reset_phy_rx_counters(padapter);
++	}
++}
++#endif
++u8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
++	u8 curr_tx_sgi = 0;
++	struct ra_sta_info *ra_info;
++
++	if (!psta)
++		return curr_tx_sgi;
++
++	if (padapter->fix_rate == 0xff) {
++#if defined(CONFIG_RTL8188E)
++#if (RATE_ADAPTIVE_SUPPORT == 1)
++		curr_tx_sgi = hal_data->odmpriv.ra_info[psta->cmn.mac_id].rate_sgi;
++#endif /* (RATE_ADAPTIVE_SUPPORT == 1)*/
++#else
++		ra_info = &psta->cmn.ra_info;
++		curr_tx_sgi = ((ra_info->curr_tx_rate) & 0x80) >> 7;
++#endif
++	} else {
++		curr_tx_sgi = ((padapter->fix_rate) & 0x80) >> 7;
++	}
++
++	return curr_tx_sgi;
++}
++
++u8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
++	u8 rate_id = 0;
++	struct ra_sta_info *ra_info;
++
++	if (!psta)
++		return rate_id;
++
++	if (padapter->fix_rate == 0xff) {
++#if defined(CONFIG_RTL8188E)
++#if (RATE_ADAPTIVE_SUPPORT == 1)
++		rate_id = hal_data->odmpriv.ra_info[psta->cmn.mac_id].decision_rate;
++#endif /* (RATE_ADAPTIVE_SUPPORT == 1)*/
++#else
++		ra_info = &psta->cmn.ra_info;
++		rate_id = ra_info->curr_tx_rate & 0x7f;
++#endif
++	} else {
++		rate_id = padapter->fix_rate & 0x7f;
++	}
++
++	return rate_id;
++}
++
++void update_IOT_info(_adapter *padapter)
++{
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	switch (pmlmeinfo->assoc_AP_vendor) {
++	case HT_IOT_PEER_MARVELL:
++		pmlmeinfo->turboMode_cts2self = 1;
++		pmlmeinfo->turboMode_rtsen = 0;
++		break;
++
++	case HT_IOT_PEER_RALINK:
++		pmlmeinfo->turboMode_cts2self = 0;
++		pmlmeinfo->turboMode_rtsen = 1;
++		break;
++	case HT_IOT_PEER_REALTEK:
++		/* rtw_write16(padapter, 0x4cc, 0xffff); */
++		/* rtw_write16(padapter, 0x546, 0x01c0); */
++		break;
++	default:
++		pmlmeinfo->turboMode_cts2self = 0;
++		pmlmeinfo->turboMode_rtsen = 1;
++		break;
++	}
++
++}
++#ifdef CONFIG_RTS_FULL_BW 
++/*
++8188E: not support full RTS BW feature(mac REG no define 480[5])
++*/
++void rtw_set_rts_bw(_adapter *padapter) {
++	int i;
++	u8 enable = 1;
++	bool connect_to_8812 = _FALSE;
++	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++	struct sta_info *station = NULL;
++
++	for (i = 0; i < macid_ctl->num; i++) {
++		if (rtw_macid_is_used(macid_ctl, i)) {
++
++			station = NULL;
++			station = macid_ctl->sta[i];
++			if(station) {
++				
++				 _adapter *sta_adapter =station->padapter;
++				struct mlme_ext_priv	*pmlmeext = &(sta_adapter->mlmeextpriv);
++				struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++				
++				if ( pmlmeinfo->state != WIFI_FW_NULL_STATE) {
++					if(_rtw_memcmp(macid_ctl->sta[i]->cmn.mac_addr, bc_addr, ETH_ALEN) !=  _TRUE) {
++						if (  macid_ctl->sta[i]->vendor_8812) {
++							connect_to_8812 = _TRUE;
++							enable = 0;
++						}	
++					}	
++				}
++			}
++		}
++
++		if(connect_to_8812)
++			break;
++	}
++	
++		RTW_INFO("%s connect_to_8812=%d,enable=%u\n", __FUNCTION__,connect_to_8812,enable);
++		rtw_hal_set_hwreg(padapter, HW_VAR_SET_RTS_BW, &enable);
++}
++#endif/*CONFIG_RTS_FULL_BW*/
++
++int hal_spec_init(_adapter *adapter)
++{
++	u8 interface_type = 0;
++	int ret = _SUCCESS;
++
++	interface_type = rtw_get_intf_type(adapter);
++
++	switch (rtw_get_chip_type(adapter)) {
++#ifdef CONFIG_RTL8723B
++	case RTL8723B:
++		init_hal_spec_8723b(adapter);
++		break;
++#endif
++#ifdef CONFIG_RTL8703B
++	case RTL8703B:
++		init_hal_spec_8703b(adapter);
++		break;
++#endif
++#ifdef CONFIG_RTL8723D
++	case RTL8723D:
++		init_hal_spec_8723d(adapter);
++		break;
++#endif
++#ifdef CONFIG_RTL8188E
++	case RTL8188E:
++		init_hal_spec_8188e(adapter);
++		break;
++#endif
++#ifdef CONFIG_RTL8188F
++	case RTL8188F:
++		init_hal_spec_8188f(adapter);
++		break;
++#endif
++#ifdef CONFIG_RTL8188GTV
++	case RTL8188GTV:
++		init_hal_spec_8188gtv(adapter);
++		break;
++#endif
++#ifdef CONFIG_RTL8812A
++	case RTL8812:
++		init_hal_spec_8812a(adapter);
++		break;
++#endif
++#ifdef CONFIG_RTL8821A
++	case RTL8821:
++		init_hal_spec_8821a(adapter);
++		break;
++#endif
++#ifdef CONFIG_RTL8192E
++	case RTL8192E:
++		init_hal_spec_8192e(adapter);
++		break;
++#endif
++#ifdef CONFIG_RTL8814A
++	case RTL8814A:
++		init_hal_spec_8814a(adapter);
++		break;
++#endif
++#ifdef CONFIG_RTL8822B
++	case RTL8822B:
++		rtl8822b_init_hal_spec(adapter);
++		break;
++#endif
++#ifdef CONFIG_RTL8821C
++	case RTL8821C:
++		init_hal_spec_rtl8821c(adapter);
++		break;
++#endif
++#ifdef CONFIG_RTL8710B
++	case RTL8710B:
++		init_hal_spec_8710b(adapter);
++		break;
++#endif
++#ifdef CONFIG_RTL8192F
++	case RTL8192F:
++		init_hal_spec_8192f(adapter);
++		break;
++#endif
++#ifdef CONFIG_RTL8822C
++	case RTL8822C:
++		rtl8822c_init_hal_spec(adapter);
++		break;
++#endif
++#ifdef CONFIG_RTL8814B
++	case RTL8814B:
++		rtl8814b_init_hal_spec(adapter);
++		break;
++#endif
++	default:
++		RTW_ERR("%s: unknown chip_type:%u\n"
++			, __func__, rtw_get_chip_type(adapter));
++		ret = _FAIL;
++		break;
++	}
++
++	return ret;
++}
++
++static const char *const _band_cap_str[] = {
++	/* BIT0 */"2G",
++	/* BIT1 */"5G",
++};
++
++static const char *const _bw_cap_str[] = {
++	/* BIT0 */"5M",
++	/* BIT1 */"10M",
++	/* BIT2 */"20M",
++	/* BIT3 */"40M",
++	/* BIT4 */"80M",
++	/* BIT5 */"160M",
++	/* BIT6 */"80_80M",
++};
++
++static const char *const _proto_cap_str[] = {
++	/* BIT0 */"b",
++	/* BIT1 */"g",
++	/* BIT2 */"n",
++	/* BIT3 */"ac",
++};
++
++static const char *const _wl_func_str[] = {
++	/* BIT0 */"P2P",
++	/* BIT1 */"MIRACAST",
++	/* BIT2 */"TDLS",
++	/* BIT3 */"FTM",
++};
++
++void dump_hal_spec(void *sel, _adapter *adapter)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	int i;
++
++	RTW_PRINT_SEL(sel, "macid_num:%u\n", hal_spec->macid_num);
++	RTW_PRINT_SEL(sel, "macid_cap:%u\n", hal_spec->macid_cap);
++	RTW_PRINT_SEL(sel, "sec_cap:0x%02x\n", hal_spec->sec_cap);
++	RTW_PRINT_SEL(sel, "sec_cam_ent_num:%u\n", hal_spec->sec_cam_ent_num);
++
++	RTW_PRINT_SEL(sel, "rfpath_num_2g:%u\n", hal_spec->rfpath_num_2g);
++	RTW_PRINT_SEL(sel, "rfpath_num_5g:%u\n", hal_spec->rfpath_num_5g);
++	RTW_PRINT_SEL(sel, "rf_reg_path_num:%u\n", hal_spec->rf_reg_path_num);
++	RTW_PRINT_SEL(sel, "rf_reg_path_avail_num:%u\n", hal_spec->rf_reg_path_avail_num);
++	RTW_PRINT_SEL(sel, "rf_reg_trx_path_bmp:0x%02x\n", hal_spec->rf_reg_trx_path_bmp);
++	RTW_PRINT_SEL(sel, "max_tx_cnt:%u\n", hal_spec->max_tx_cnt);
++
++	RTW_PRINT_SEL(sel, "tx_nss_num:%u\n", hal_spec->tx_nss_num);
++	RTW_PRINT_SEL(sel, "rx_nss_num:%u\n", hal_spec->rx_nss_num);
++
++	RTW_PRINT_SEL(sel, "band_cap:");
++	for (i = 0; i < BAND_CAP_BIT_NUM; i++) {
++		if (((hal_spec->band_cap) >> i) & BIT0 && _band_cap_str[i])
++			_RTW_PRINT_SEL(sel, "%s ", _band_cap_str[i]);
++	}
++	_RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "bw_cap:");
++	for (i = 0; i < BW_CAP_BIT_NUM; i++) {
++		if (((hal_spec->bw_cap) >> i) & BIT0 && _bw_cap_str[i])
++			_RTW_PRINT_SEL(sel, "%s ", _bw_cap_str[i]);
++	}
++	_RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "proto_cap:");
++	for (i = 0; i < PROTO_CAP_BIT_NUM; i++) {
++		if (((hal_spec->proto_cap) >> i) & BIT0 && _proto_cap_str[i])
++			_RTW_PRINT_SEL(sel, "%s ", _proto_cap_str[i]);
++	}
++	_RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "txgi_max:%u\n", hal_spec->txgi_max);
++	RTW_PRINT_SEL(sel, "txgi_pdbm:%u\n", hal_spec->txgi_pdbm);
++
++	RTW_PRINT_SEL(sel, "wl_func:");
++	for (i = 0; i < WL_FUNC_BIT_NUM; i++) {
++		if (((hal_spec->wl_func) >> i) & BIT0 && _wl_func_str[i])
++			_RTW_PRINT_SEL(sel, "%s ", _wl_func_str[i]);
++	}
++	_RTW_PRINT_SEL(sel, "\n");
++
++#if CONFIG_TX_AC_LIFETIME
++	RTW_PRINT_SEL(sel, "tx_aclt_unit_factor:%u (unit:%uus)\n"
++		, hal_spec->tx_aclt_unit_factor, hal_spec->tx_aclt_unit_factor * 32);
++#endif
++
++	RTW_PRINT_SEL(sel, "rx_tsf_filter:%u\n", hal_spec->rx_tsf_filter);
++
++	RTW_PRINT_SEL(sel, "pg_txpwr_saddr:0x%X\n", hal_spec->pg_txpwr_saddr);
++	RTW_PRINT_SEL(sel, "pg_txgi_diff_factor:%u\n", hal_spec->pg_txgi_diff_factor);
++}
++
++inline bool hal_chk_band_cap(_adapter *adapter, u8 cap)
++{
++	return GET_HAL_SPEC(adapter)->band_cap & cap;
++}
++
++inline bool hal_chk_bw_cap(_adapter *adapter, u8 cap)
++{
++	return GET_HAL_SPEC(adapter)->bw_cap & cap;
++}
++
++inline bool hal_chk_proto_cap(_adapter *adapter, u8 cap)
++{
++	return GET_HAL_SPEC(adapter)->proto_cap & cap;
++}
++
++inline bool hal_chk_wl_func(_adapter *adapter, u8 func)
++{
++	return GET_HAL_SPEC(adapter)->wl_func & func;
++}
++
++inline bool hal_is_band_support(_adapter *adapter, u8 band)
++{
++	return GET_HAL_SPEC(adapter)->band_cap & band_to_band_cap(band);
++}
++
++inline bool hal_is_bw_support(_adapter *adapter, u8 bw)
++{
++	return GET_HAL_SPEC(adapter)->bw_cap & ch_width_to_bw_cap(bw);
++}
++
++inline bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode)
++{
++	u8 proto_cap = GET_HAL_SPEC(adapter)->proto_cap;
++
++	if (mode == WIRELESS_11B)
++		if ((proto_cap & PROTO_CAP_11B) && hal_chk_band_cap(adapter, BAND_CAP_2G))
++			return 1;
++
++	if (mode == WIRELESS_11G)
++		if ((proto_cap & PROTO_CAP_11G) && hal_chk_band_cap(adapter, BAND_CAP_2G))
++			return 1;
++
++	if (mode == WIRELESS_11A)
++		if ((proto_cap & PROTO_CAP_11G) && hal_chk_band_cap(adapter, BAND_CAP_5G))
++			return 1;
++
++	if (mode == WIRELESS_11_24N)
++		if ((proto_cap & PROTO_CAP_11N) && hal_chk_band_cap(adapter, BAND_CAP_2G))
++			return 1;
++
++	if (mode == WIRELESS_11_5N)
++		if ((proto_cap & PROTO_CAP_11N) && hal_chk_band_cap(adapter, BAND_CAP_5G))
++			return 1;
++
++	if (mode == WIRELESS_11AC)
++		if ((proto_cap & PROTO_CAP_11AC) && hal_chk_band_cap(adapter, BAND_CAP_5G))
++			return 1;
++
++	return 0;
++}
++inline bool hal_is_mimo_support(_adapter *adapter)
++{
++	if ((GET_HAL_TX_NSS(adapter) == 1) &&
++		(GET_HAL_RX_NSS(adapter) == 1))
++		return 0;
++	return 1;
++}
++
++/*
++* hal_largest_bw - starting from in_bw, get largest bw supported by HAL
++* @adapter:
++* @in_bw: starting bw, value of enum channel_width
++*
++* Returns: value of enum channel_width
++*/
++u8 hal_largest_bw(_adapter *adapter, u8 in_bw)
++{
++	for (; in_bw > CHANNEL_WIDTH_20; in_bw--) {
++		if (hal_is_bw_support(adapter, in_bw))
++			break;
++	}
++
++	if (!hal_is_bw_support(adapter, in_bw))
++		rtw_warn_on(1);
++
++	return in_bw;
++}
++
++#ifndef CONFIG_HAS_TX_BEACON_PAUSE
++void ResumeTxBeacon(_adapter *padapter)
++{
++	rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
++		rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2) | BIT(6));
++
++#ifdef RTW_HALMAC
++	/* Add this for driver using HALMAC because driver doesn't have setup time init by self */
++	/* TBTT setup time */
++	rtw_write8(padapter, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME);
++#endif
++
++	/* TBTT hold time: 0x540[19:8] */
++	rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME & 0xFF);
++	rtw_write8(padapter, REG_TBTT_PROHIBIT + 2,
++		(rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME >> 8));
++}
++
++void StopTxBeacon(_adapter *padapter)
++{
++	rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
++		rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2) & (~BIT6));
++
++	/* TBTT hold time: 0x540[19:8] */
++	rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);
++	rtw_write8(padapter, REG_TBTT_PROHIBIT + 2,
++		(rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8));
++}
++#endif /* CONFIG_HAS_TX_BEACON_PAUSE */
++
++#ifdef CONFIG_MI_WITH_MBSSID_CAM /*HW port0 - MBSS*/
++
++#ifdef CONFIG_CLIENT_PORT_CFG
++const u8 _clt_port_id[MAX_CLIENT_PORT_NUM] = {
++	CLT_PORT0,
++	CLT_PORT1,
++	CLT_PORT2,
++	CLT_PORT3
++};
++
++void rtw_clt_port_init(struct clt_port_t  *cltp)
++{
++	cltp->bmp = 0;
++	cltp->num = 0;
++	_rtw_spinlock_init(&cltp->lock);
++}
++void rtw_clt_port_deinit(struct clt_port_t *cltp)
++{
++	_rtw_spinlock_free(&cltp->lock);
++}
++static void _hw_client_port_alloc(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct clt_port_t  *cltp = &dvobj->clt_port;
++	_irqL irql;
++	int i;
++
++	#if 0
++	if (cltp->num > MAX_CLIENT_PORT_NUM) {
++		RTW_ERR(ADPT_FMT" cann't  alloc client (%d)\n", ADPT_ARG(adapter), cltp->num);
++		rtw_warn_on(1);
++		return;
++	}
++	#endif
++
++	if (adapter->client_id !=  MAX_CLIENT_PORT_NUM) {
++		RTW_INFO(ADPT_FMT" client_id %d has allocated port:%d\n",
++			ADPT_ARG(adapter), adapter->client_id, adapter->client_port);
++		return;
++	}
++	_enter_critical_bh(&cltp->lock, &irql);
++	for (i = 0; i < MAX_CLIENT_PORT_NUM; i++) {
++		if (!(cltp->bmp & BIT(i)))
++			break;
++	}
++
++	if (i < MAX_CLIENT_PORT_NUM) {
++		adapter->client_id = i;
++		cltp->bmp |= BIT(i);
++		adapter->client_port = _clt_port_id[i];
++	}
++	cltp->num++;
++	_exit_critical_bh(&cltp->lock, &irql);
++	RTW_INFO("%s("ADPT_FMT")id:%d, port:%d clt_num:%d\n",
++		__func__, ADPT_ARG(adapter), adapter->client_id, adapter->client_port, cltp->num);
++}
++static void _hw_client_port_free(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct clt_port_t  *cltp = &dvobj->clt_port;
++	_irqL irql;
++
++	#if 0
++	if (adapter->client_id >=  MAX_CLIENT_PORT_NUM) {
++		RTW_ERR(ADPT_FMT" client_id %d is invalid\n", ADPT_ARG(adapter), adapter->client_id);
++		/*rtw_warn_on(1);*/
++	}
++	#endif
++
++	RTW_INFO("%s ("ADPT_FMT") id:%d, port:%d clt_num:%d\n",
++		__func__, ADPT_ARG(adapter), adapter->client_id, adapter->client_port, cltp->num);
++
++	_enter_critical_bh(&cltp->lock, &irql);
++	if (adapter->client_id !=  MAX_CLIENT_PORT_NUM) {
++		cltp->bmp &= ~ BIT(adapter->client_id);
++		adapter->client_id = MAX_CLIENT_PORT_NUM;
++		adapter->client_port = CLT_PORT_INVALID;
++	}
++	cltp->num--;
++	if (cltp->num < 0)
++		cltp->num = 0;
++	_exit_critical_bh(&cltp->lock, &irql);
++}
++void rtw_hw_client_port_allocate(_adapter *adapter)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++
++	if (hal_spec->port_num != 5)
++		return;
++
++	_hw_client_port_alloc(adapter);
++}
++void rtw_hw_client_port_release(_adapter *adapter)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++
++	if (hal_spec->port_num != 5)
++		return;
++
++	_hw_client_port_free(adapter);
++}
++#endif /*CONFIG_CLIENT_PORT_CFG*/
++
++void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode)
++{
++	RTW_INFO("%s()-"ADPT_FMT" mode = %d\n", __func__, ADPT_ARG(Adapter), mode);
++
++	rtw_hal_rcr_set_chk_bssid(Adapter, MLME_ACTION_NONE);
++
++	/* set net_type */
++	Set_MSR(Adapter, mode);
++
++	if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
++		if (!rtw_mi_get_ap_num(Adapter) && !rtw_mi_get_mesh_num(Adapter))
++			StopTxBeacon(Adapter);
++	} else if (mode == _HW_STATE_ADHOC_)
++		ResumeTxBeacon(Adapter);
++	else if (mode == _HW_STATE_AP_)
++		/* enable rx ps-poll */
++		rtw_write16(Adapter, REG_RXFLTMAP1, rtw_read16(Adapter, REG_RXFLTMAP1) | BIT_CTRLFLT10EN);
++
++	/* enable rx data frame */
++	rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
++
++#ifdef CONFIG_CLIENT_PORT_CFG
++	if (mode == _HW_STATE_STATION_)
++		rtw_hw_client_port_allocate(Adapter);
++	else
++		rtw_hw_client_port_release(Adapter);
++#endif
++#if defined(CONFIG_RTL8192F)
++		rtw_write16(Adapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(Adapter, 
++					REG_WLAN_ACT_MASK_CTRL_1) | EN_PORT_0_FUNCTION);	
++#endif
++}
++#endif
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++u8	rtw_hal_antdiv_before_linked(_adapter *padapter)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++	u8 cur_ant, change_ant;
++
++	if (!pHalData->AntDivCfg)
++		return _FALSE;
++
++	if (pHalData->sw_antdiv_bl_state == 0) {
++		pHalData->sw_antdiv_bl_state = 1;
++
++		rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL);
++		change_ant = (cur_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
++
++		return rtw_antenna_select_cmd(padapter, change_ant, _FALSE);
++	}
++
++	pHalData->sw_antdiv_bl_state = 0;
++	return _FALSE;
++}
++
++void	rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++	if (pHalData->AntDivCfg) {
++		/*RTW_INFO("update_network=> org-RSSI(%d), new-RSSI(%d)\n", dst->Rssi, src->Rssi);*/
++		/*select optimum_antenna for before linked =>For antenna diversity*/
++		if (dst->Rssi >=  src->Rssi) {/*keep org parameter*/
++			src->Rssi = dst->Rssi;
++			src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna;
++		}
++	}
++}
++#endif
++
++#ifdef CONFIG_PHY_CAPABILITY_QUERY
++void rtw_dump_phy_cap_by_phydmapi(void *sel, _adapter *adapter)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
++	struct phy_spec_t *phy_spec = &pHalData->phy_spec;
++
++	RTW_PRINT_SEL(sel, "[PHY SPEC] TRx Capability : 0x%08x\n", phy_spec->trx_cap);
++	RTW_PRINT_SEL(sel, "[PHY SPEC] Tx Stream Num Index : %d\n", (phy_spec->trx_cap >> 24) & 0xFF); /*Tx Stream Num Index [31:24]*/
++	RTW_PRINT_SEL(sel, "[PHY SPEC] Rx Stream Num Index : %d\n", (phy_spec->trx_cap >> 16) & 0xFF); /*Rx Stream Num Index [23:16]*/
++	RTW_PRINT_SEL(sel, "[PHY SPEC] Tx Path Num Index : %d\n", (phy_spec->trx_cap >> 8) & 0xFF);/*Tx Path Num Index	[15:8]*/
++	RTW_PRINT_SEL(sel, "[PHY SPEC] Rx Path Num Index : %d\n\n", (phy_spec->trx_cap & 0xFF));/*Rx Path Num Index	[7:0]*/
++
++	RTW_PRINT_SEL(sel, "[PHY SPEC] STBC Capability : 0x%08x\n", phy_spec->stbc_cap);
++	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT STBC Tx : %s\n", ((phy_spec->stbc_cap >> 24) & 0xFF) ? "Supported" : "N/A"); /*VHT STBC Tx [31:24]*/
++	/*VHT STBC Rx [23:16]
++	0 = not support
++	1 = support for 1 spatial stream
++	2 = support for 1 or 2 spatial streams
++	3 = support for 1 or 2 or 3 spatial streams
++	4 = support for 1 or 2 or 3 or 4 spatial streams*/
++	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT STBC Rx :%d\n", ((phy_spec->stbc_cap >> 16) & 0xFF));
++	RTW_PRINT_SEL(sel, "[PHY SPEC] HT STBC Tx : %s\n", ((phy_spec->stbc_cap >> 8) & 0xFF) ? "Supported" : "N/A"); /*HT STBC Tx [15:8]*/
++	/*HT STBC Rx [7:0]
++	0 = not support
++	1 = support for 1 spatial stream
++	2 = support for 1 or 2 spatial streams
++	3 = support for 1 or 2 or 3 spatial streams*/
++	RTW_PRINT_SEL(sel, "[PHY SPEC] HT STBC Rx : %d\n\n", (phy_spec->stbc_cap & 0xFF));
++
++	RTW_PRINT_SEL(sel, "[PHY SPEC] LDPC Capability : 0x%08x\n", phy_spec->ldpc_cap);
++	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT LDPC Tx : %s\n", ((phy_spec->ldpc_cap >> 24) & 0xFF) ? "Supported" : "N/A"); /*VHT LDPC Tx [31:24]*/
++	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT LDPC Rx : %s\n", ((phy_spec->ldpc_cap >> 16) & 0xFF) ? "Supported" : "N/A"); /*VHT LDPC Rx [23:16]*/
++	RTW_PRINT_SEL(sel, "[PHY SPEC] HT LDPC Tx : %s\n", ((phy_spec->ldpc_cap >> 8) & 0xFF) ? "Supported" : "N/A"); /*HT LDPC Tx [15:8]*/
++	RTW_PRINT_SEL(sel, "[PHY SPEC] HT LDPC Rx : %s\n\n", (phy_spec->ldpc_cap & 0xFF) ? "Supported" : "N/A"); /*HT LDPC Rx [7:0]*/
++	#ifdef CONFIG_BEAMFORMING
++	RTW_PRINT_SEL(sel, "[PHY SPEC] TxBF Capability : 0x%08x\n", phy_spec->txbf_cap);
++	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT MU Bfer : %s\n", ((phy_spec->txbf_cap >> 28) & 0xF) ? "Supported" : "N/A"); /*VHT MU Bfer [31:28]*/
++	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT MU Bfee : %s\n", ((phy_spec->txbf_cap >> 24) & 0xF) ? "Supported" : "N/A"); /*VHT MU Bfee [27:24]*/
++	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT SU Bfer : %s\n", ((phy_spec->txbf_cap >> 20) & 0xF) ? "Supported" : "N/A"); /*VHT SU Bfer [23:20]*/
++	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT SU Bfee : %s\n", ((phy_spec->txbf_cap >> 16) & 0xF) ? "Supported" : "N/A"); /*VHT SU Bfee [19:16]*/
++	RTW_PRINT_SEL(sel, "[PHY SPEC] HT Bfer : %s\n", ((phy_spec->txbf_cap >> 4) & 0xF)  ? "Supported" : "N/A"); /*HT Bfer [7:4]*/
++	RTW_PRINT_SEL(sel, "[PHY SPEC] HT Bfee : %s\n\n", (phy_spec->txbf_cap & 0xF) ? "Supported" : "N/A"); /*HT Bfee [3:0]*/
++
++	RTW_PRINT_SEL(sel, "[PHY SPEC] TxBF parameter : 0x%08x\n", phy_spec->txbf_param);
++	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT Sounding Dim : %d\n", (phy_spec->txbf_param >> 24) & 0xFF); /*VHT Sounding Dim [31:24]*/
++	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT Steering Ant : %d\n", (phy_spec->txbf_param >> 16) & 0xFF); /*VHT Steering Ant [23:16]*/
++	RTW_PRINT_SEL(sel, "[PHY SPEC] HT Sounding Dim : %d\n", (phy_spec->txbf_param >> 8) & 0xFF); /*HT Sounding Dim [15:8]*/
++	RTW_PRINT_SEL(sel, "[PHY SPEC] HT Steering Ant : %d\n", phy_spec->txbf_param & 0xFF); /*HT Steering Ant [7:0]*/
++	#endif
++}
++#else
++void rtw_dump_phy_cap_by_hal(void *sel, _adapter *adapter)
++{
++	u8 phy_cap = _FALSE;
++
++	/* STBC */
++	rtw_hal_get_def_var(adapter, HAL_DEF_TX_STBC, (u8 *)&phy_cap);
++	RTW_PRINT_SEL(sel, "[HAL] STBC Tx : %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
++
++	phy_cap = _FALSE;
++	rtw_hal_get_def_var(adapter, HAL_DEF_RX_STBC, (u8 *)&phy_cap);
++	RTW_PRINT_SEL(sel, "[HAL] STBC Rx : %s\n\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
++
++	/* LDPC support */
++	phy_cap = _FALSE;
++	rtw_hal_get_def_var(adapter, HAL_DEF_TX_LDPC, (u8 *)&phy_cap);
++	RTW_PRINT_SEL(sel, "[HAL] LDPC Tx : %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
++
++	phy_cap = _FALSE;
++	rtw_hal_get_def_var(adapter, HAL_DEF_RX_LDPC, (u8 *)&phy_cap);
++	RTW_PRINT_SEL(sel, "[HAL] LDPC Rx : %s\n\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
++	
++	#ifdef CONFIG_BEAMFORMING
++	phy_cap = _FALSE;
++	rtw_hal_get_def_var(adapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&phy_cap);
++	RTW_PRINT_SEL(sel, "[HAL] Beamformer: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
++
++	phy_cap = _FALSE;
++	rtw_hal_get_def_var(adapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&phy_cap);
++	RTW_PRINT_SEL(sel, "[HAL] Beamformee: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
++
++	phy_cap = _FALSE;
++	rtw_hal_get_def_var(adapter, HAL_DEF_VHT_MU_BEAMFORMER, &phy_cap);
++	RTW_PRINT_SEL(sel, "[HAL] VHT MU Beamformer: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
++
++	phy_cap = _FALSE;
++	rtw_hal_get_def_var(adapter, HAL_DEF_VHT_MU_BEAMFORMEE, &phy_cap);
++	RTW_PRINT_SEL(sel, "[HAL] VHT MU Beamformee: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
++	#endif
++}
++#endif
++void rtw_dump_phy_cap(void *sel, _adapter *adapter)
++{
++	RTW_PRINT_SEL(sel, "\n ======== PHY Capability ========\n");
++#ifdef CONFIG_PHY_CAPABILITY_QUERY
++	rtw_dump_phy_cap_by_phydmapi(sel, adapter);
++#else
++	rtw_dump_phy_cap_by_hal(sel, adapter);
++#endif
++}
++
++inline s16 translate_dbm_to_percentage(s16 signal)
++{
++	if ((signal <= -100) || (signal >= 20))
++		return	0;
++	else if (signal >= 0)
++		return	100;
++	else
++		return 100 + signal;
++}
++
++#ifdef CONFIG_SWTIMER_BASED_TXBCN
++#ifdef CONFIG_BCN_RECOVERY
++#define REG_CPU_MGQ_INFO	0x041C
++#define BIT_BCN_POLL			BIT(28)
++u8 rtw_ap_bcn_recovery(_adapter *padapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
++
++	if (hal_data->issue_bcn_fail >= 2) {
++		RTW_ERR("%s ISSUE BCN Fail\n", __func__);
++		rtw_write8(padapter, REG_CPU_MGQ_INFO + 3, 0x10);
++		hal_data->issue_bcn_fail = 0;
++	}
++	return _SUCCESS;
++}
++#endif /*CONFIG_BCN_RECOVERY*/
++
++#ifdef CONFIG_BCN_XMIT_PROTECT
++u8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms)
++{
++	u32 start_time = rtw_get_current_time();
++	u8 bcn_queue_empty = _FALSE;
++
++	do {
++		if (rtw_read16(padapter, REG_TXPKT_EMPTY) & BIT(11)) {
++			bcn_queue_empty = _TRUE;
++			break;
++		}
++	} while (rtw_get_passing_time_ms(start_time) <= (txbcn_timer_ms + 10));
++
++	if (bcn_queue_empty == _FALSE)
++		RTW_ERR("%s BCN queue not empty\n", __func__);
++
++	return bcn_queue_empty;
++}
++#endif /*CONFIG_BCN_XMIT_PROTECT*/
++#endif /*CONFIG_SWTIMER_BASED_TXBCN*/
++
++/**
++ * rtw_hal_get_trx_path() - Get RF path related information
++ * @d:		struct dvobj_priv*
++ * @type:	RF type, nTnR
++ * @tx:		Tx path
++ * @rx:		Rx path
++ *
++ * Get RF type, TX path and RX path information.
++ */
++void rtw_hal_get_trx_path(struct dvobj_priv *d, enum rf_type *type,
++			 enum bb_path *tx, enum bb_path *rx)
++{
++	struct _ADAPTER *a = dvobj_get_primary_adapter(d);
++	enum rf_type t = GET_HAL_RFPATH(a);
++
++	if (type)
++		*type = t;
++
++	if (tx || rx) {
++		u8 tx_bmp = GET_HAL_TX_PATH_BMP(a);
++		u8 rx_bmp = GET_HAL_RX_PATH_BMP(a);
++
++		if (!tx_bmp && !rx_bmp)
++			rf_type_to_default_trx_bmp(t, tx, rx);
++		else {
++			if (tx)
++				*tx = GET_HAL_TX_PATH_BMP(a);
++			if (rx)
++				*rx = GET_HAL_RX_PATH_BMP(a);
++		}
++	}
++}
++
++#ifdef RTW_CHANNEL_SWITCH_OFFLOAD
++void rtw_hal_switch_chnl_and_set_bw_offload(_adapter *adapter, u8 central_ch, u8 pri_ch_idx, u8 bw)
++{
++	u8 h2c[H2C_SINGLE_CHANNELSWITCH_V2_LEN] = {0};
++	PHAL_DATA_TYPE hal;
++	struct submit_ctx *chsw_sctx;
++
++	hal = GET_HAL_DATA(adapter);
++	chsw_sctx = &hal->chsw_sctx;
++
++	SET_H2CCMD_SINGLE_CH_SWITCH_V2_CENTRAL_CH_NUM(h2c, central_ch);
++	SET_H2CCMD_SINGLE_CH_SWITCH_V2_PRIMARY_CH_IDX(h2c, pri_ch_idx);
++	SET_H2CCMD_SINGLE_CH_SWITCH_V2_BW(h2c, bw);
++
++	rtw_sctx_init(chsw_sctx, 10);
++	rtw_hal_fill_h2c_cmd(adapter, H2C_SINGLE_CHANNELSWITCH_V2, H2C_SINGLE_CHANNELSWITCH_V2_LEN, h2c);
++	rtw_sctx_wait(chsw_sctx, __func__);
++}
++#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
++
++u8 phy_get_current_tx_num(
++		PADAPTER		pAdapter,
++		u8				Rate
++)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(pAdapter);
++	u8	tx_num = 0;
++
++	if (IS_1T_RATE(Rate))
++		tx_num = hal_data->txpath_num_nss[0];
++	else if (IS_2T_RATE(Rate))
++		tx_num = hal_data->txpath_num_nss[1];
++	else if (IS_3T_RATE(Rate))
++		tx_num = hal_data->txpath_num_nss[2];
++	else if (IS_4T_RATE(Rate))
++		tx_num = hal_data->txpath_num_nss[3];
++	else
++		rtw_warn_on(1);
++
++	return tx_num == 0 ? RF_1TX : tx_num - 1;
++}
++
++#ifdef CONFIG_RTL8812A
++u8 * rtw_hal_set_8812a_vendor_ie(_adapter *padapter , u8 *pframe ,uint *frlen ) {
++	int vender_len = 7;
++	unsigned char	vendor_info[vender_len];
++	unsigned char REALTEK_OUI[] = {0x00, 0xe0, 0x4c};
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	if( !IS_HARDWARE_TYPE_8812(padapter) )
++		return pframe;
++
++	_rtw_memset(vendor_info,0,vender_len);
++	_rtw_memcpy(vendor_info, REALTEK_OUI, 3);
++	vendor_info[4] =2;
++	if(pHalData->version_id.CUTVersion > B_CUT_VERSION )
++		vendor_info[6] = RT_HT_CAP_USE_JAGUAR_CCUT;
++	else
++		vendor_info[6] = RT_HT_CAP_USE_JAGUAR_BCUT;
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_,vender_len,vendor_info , frlen);
++	
++	return pframe;
++}
++#endif /*CONFIG_RTL8812A*/
++
++static inline void rtw_enter_protsel(struct protsel *protsel, u32 sel)
++{
++	int refcnt;
++
++	_enter_critical_mutex(&protsel->mutex, NULL);
++
++	refcnt = ATOMIC_INC_RETURN(&protsel->refcnt);
++
++	WARN_ON(refcnt > 1 && protsel->sel != sel);
++
++	protsel->sel = sel;
++
++	_exit_critical_mutex(&protsel->mutex, NULL);
++}
++
++static inline void rtw_leave_protsel(struct protsel *protsel)
++{
++	int refcnt;
++
++	_enter_critical_mutex(&protsel->mutex, NULL);
++
++	refcnt = ATOMIC_DEC_RETURN(&protsel->refcnt);
++
++	_exit_critical_mutex(&protsel->mutex, NULL);
++
++	WARN_ON(refcnt < 0);
++}
++
++static inline bool rtw_assert_protsel(struct protsel *protsel)
++{
++	int refcnt = ATOMIC_READ(&protsel->refcnt);
++
++	if (refcnt > 0)
++		return true;
++
++	return false;
++}
++
++#ifdef CONFIG_PROTSEL_PORT
++void rtw_enter_protsel_port(_adapter *padapter, u8 port_sel)
++{
++	u8 val8;
++
++	rtw_enter_protsel(&padapter->dvobj->protsel_port, port_sel);
++
++	val8 = rtw_read8(padapter, REG_PORT_CTRL_SEL);
++	val8 &= ~BIT_MASK_PORT_CTRL_SEL;
++	val8 |= BIT_PORT_CTRL_SEL(port_sel);
++	rtw_write8(padapter, REG_PORT_CTRL_SEL, val8);
++}
++
++bool rtw_assert_protsel_port(_adapter *padapter, u32 addr, u8 len)
++{
++	if (!padapter->bup)	/* don't assert before IF up */
++		return true;
++
++	return rtw_assert_protsel(&padapter->dvobj->protsel_port);
++}
++
++void rtw_leave_protsel_port(_adapter *padapter)
++{
++	rtw_leave_protsel(&padapter->dvobj->protsel_port);
++}
++#endif
++
++#ifdef CONFIG_PROTSEL_ATIMDTIM
++void rtw_enter_protsel_atimdtim(_adapter *padapter, u8 port_sel)
++{
++	/* 0~15 is for port 0 MBSSID setting
++	 * 16 is for port 1 setting
++	 * 17 is for port 2 setting
++	 * 18 is for port 3 setting
++	 * 19 is for port 4 setting
++	 */
++	u8 val8;
++
++	if (port_sel >= 1 && port_sel <= 4)
++		port_sel += 15;
++
++	rtw_enter_protsel(&padapter->dvobj->protsel_atimdtim, port_sel);
++
++	val8 = rtw_read8(padapter, REG_ATIM_DTIM_CTRL_SEL);
++	val8 &= ~BIT_MASK_ATIM_DTIM_SEL;
++	val8 |= BIT_ATIM_DTIM_SEL(port_sel);
++	rtw_write8(padapter, REG_ATIM_DTIM_CTRL_SEL, val8);
++}
++
++bool rtw_assert_protsel_atimdtim(_adapter *padapter, u32 addr, u8 len)
++{
++	return rtw_assert_protsel(&padapter->dvobj->protsel_atimdtim);
++}
++
++void rtw_leave_protsel_atimdtim(_adapter *padapter)
++{
++	rtw_leave_protsel(&padapter->dvobj->protsel_atimdtim);
++}
++#endif
++
++#ifdef CONFIG_PROTSEL_MACSLEEP
++void rtw_enter_protsel_macsleep(_adapter *padapter, u8 sel)
++{
++	u32 val32;
++
++	rtw_enter_protsel(&padapter->dvobj->protsel_macsleep, sel);
++
++	val32 = rtw_read32(padapter, REG_MACID_SLEEP_CTRL);
++	val32 &= ~BIT_MASK_MACID_SLEEP_SEL;
++	val32 |= BIT_MACID_SLEEP_SEL(sel);
++	rtw_write32(padapter, REG_MACID_SLEEP_CTRL, val32);
++}
++
++bool rtw_assert_protsel_macsleep(_adapter *padapter, u32 addr, u8 len)
++{
++	return rtw_assert_protsel(&padapter->dvobj->protsel_macsleep);
++}
++
++void rtw_leave_protsel_macsleep(_adapter *padapter)
++{
++	rtw_leave_protsel(&padapter->dvobj->protsel_macsleep);
++}
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_com_c2h.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_com_c2h.h
+new file mode 100644
+index 000000000..54f2d0686
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_com_c2h.h
+@@ -0,0 +1,140 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __COMMON_C2H_H__
++#define __COMMON_C2H_H__
++
++#define C2H_TYPE_REG 0
++#define C2H_TYPE_PKT 1
++
++/* 
++* C2H event format:
++* Fields    TRIGGER    PAYLOAD    SEQ    PLEN    ID
++* BITS     [127:120]    [119:16]   [15:8]  [7:4]  [3:0]
++*/
++#define C2H_ID(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)), 0, 4)
++#define C2H_PLEN(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)), 4, 4)
++#define C2H_SEQ(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 1, 0, 8)
++#define C2H_PAYLOAD(_c2h)	(((u8*)(_c2h)) + 2)
++
++#define SET_C2H_ID(_c2h, _val)		SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 0, 4, _val)
++#define SET_C2H_PLEN(_c2h, _val)	SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 4, 4, _val)
++#define SET_C2H_SEQ(_c2h, _val)		SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 1 , 0, 8, _val)
++
++/* 
++* C2H event format:
++* Fields    TRIGGER     PLEN      PAYLOAD    SEQ      ID
++* BITS    [127:120]  [119:112]  [111:16]   [15:8]   [7:0]
++*/
++#define C2H_ID_88XX(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)), 0, 8)
++#define C2H_SEQ_88XX(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 1, 0, 8)
++#define C2H_PAYLOAD_88XX(_c2h)	(((u8*)(_c2h)) + 2)
++#define C2H_PLEN_88XX(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 14, 0, 8)
++#define C2H_TRIGGER_88XX(_c2h)	LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 15, 0, 8)
++
++#define SET_C2H_ID_88XX(_c2h, _val)		SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 0, 8, _val)
++#define SET_C2H_SEQ_88XX(_c2h, _val)	SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 1, 0, 8, _val)
++#define SET_C2H_PLEN_88XX(_c2h, _val)	SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 14, 0, 8, _val)
++
++typedef enum _C2H_EVT {
++	C2H_DBG = 0x00,
++	C2H_LB = 0x01,
++	C2H_TXBF = 0x02,
++	C2H_CCX_TX_RPT = 0x03,
++	C2H_AP_REQ_TXRPT = 0x04,
++	C2H_FW_SCAN_COMPLETE = 0x7,
++	C2H_BT_INFO = 0x09,
++	C2H_BT_MP_INFO = 0x0B,
++	C2H_RA_RPT = 0x0C,
++	C2H_SPC_STAT = 0x0D,
++	C2H_RA_PARA_RPT = 0x0E,
++	C2H_FW_CHNL_SWITCH_COMPLETE = 0x10,
++	C2H_IQK_FINISH = 0x11,
++	C2H_MAILBOX_STATUS = 0x15,
++	C2H_P2P_RPORT = 0x16,
++	C2H_MCC = 0x17,
++	C2H_MAC_HIDDEN_RPT = 0x19,
++	C2H_MAC_HIDDEN_RPT_2 = 0x1A,
++	C2H_BCN_EARLY_RPT = 0x1E,
++	C2H_DEFEATURE_DBG = 0x22,
++	C2H_CUSTOMER_STR_RPT = 0x24,
++	C2H_CUSTOMER_STR_RPT_2 = 0x25,
++	C2H_WLAN_INFO = 0x27,
++#ifdef RTW_PER_CMD_SUPPORT_FW
++	C2H_PER_RATE_RPT = 0x2c,
++#endif
++	C2H_LPS_STATUS_RPT = 0x32,
++	C2H_SET_TXPWR_FINISH = 0x70,
++	C2H_DEFEATURE_RSVD = 0xFD,
++	C2H_EXTEND = 0xff,
++} C2H_EVT;
++
++typedef enum _EXTEND_C2H_EVT {
++	EXTEND_C2H_DBG_PRINT = 0
++} EXTEND_C2H_EVT;
++
++#define C2H_REG_LEN 16
++
++/* C2H_IQK_FINISH, 0x11 */
++#define IQK_OFFLOAD_LEN 1
++void c2h_iqk_offload(_adapter *adapter, u8 *data, u8 len);
++int	c2h_iqk_offload_wait(_adapter *adapter, u32 timeout_ms);
++#define rtl8812_iqk_wait c2h_iqk_offload_wait /* TODO: remove this after phydm call c2h_iqk_offload_wait instead */
++
++#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
++/* C2H_MAC_HIDDEN_RPT, 0x19 */
++#define MAC_HIDDEN_RPT_LEN 8
++int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len);
++
++/* C2H_MAC_HIDDEN_RPT_2, 0x1A */
++#define MAC_HIDDEN_RPT_2_LEN 5
++int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len);
++int hal_read_mac_hidden_rpt(_adapter *adapter);
++#else
++#define hal_read_mac_hidden_rpt(adapter) _SUCCESS
++#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */
++
++/* C2H_DEFEATURE_DBG, 0x22 */
++#define DEFEATURE_DBG_LEN 1
++int c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len);
++
++#ifdef CONFIG_RTW_CUSTOMER_STR
++/* C2H_CUSTOMER_STR_RPT, 0x24 */
++#define CUSTOMER_STR_RPT_LEN 8
++int c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len);
++
++/* C2H_CUSTOMER_STR_RPT_2, 0x25 */
++#define CUSTOMER_STR_RPT_2_LEN 8
++int c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len);
++#endif /* CONFIG_RTW_CUSTOMER_STR */
++
++#ifdef RTW_PER_CMD_SUPPORT_FW
++/* C2H_PER_RATE_RPT, 0x2c */
++int c2h_per_rate_rpt_hdl(_adapter *adapter, u8 *data, u8 len);
++#endif
++
++#ifdef CONFIG_LPS_ACK
++/* C2H_LPS_STATUS_RPT, 0x32 */
++#define LPS_STATUS_RPT_LEN 2
++int c2h_lps_status_rpt(PADAPTER adapter, u8 *data, u8 len);
++#endif /* CONFIG_LPS_ACK */
++
++#ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
++/* C2H_SET_TXPWR_FINISH, 0x70 */
++#define SET_TXPWR_FINISH_LEN 1
++void c2h_txpwr_idx_offload_done(_adapter *adapter, u8 *data, u8 len);
++int c2h_txpwr_idx_offload_wait(_adapter *adapter);
++#endif
++
++#endif /* __COMMON_C2H_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_com_phycfg.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_com_phycfg.c
+new file mode 100644
+index 000000000..a15a6f0c3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_com_phycfg.c
+@@ -0,0 +1,6197 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _HAL_COM_PHYCFG_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++#define PG_TXPWR_1PATH_BYTE_NUM_2G 18
++#define PG_TXPWR_BASE_BYTE_NUM_2G 11
++
++#define PG_TXPWR_1PATH_BYTE_NUM_5G 24
++#define PG_TXPWR_BASE_BYTE_NUM_5G 14
++
++#define PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) (((_pg_v) & 0xf0) >> 4)
++#define PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) ((_pg_v) & 0x0f)
++#define PG_TXPWR_MSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_MSB_DIFF_S4BIT(_pg_v))
++#define PG_TXPWR_LSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_LSB_DIFF_S4BIT(_pg_v))
++#define IS_PG_TXPWR_BASE_INVALID(hal_spec, _base) ((_base) > hal_spec->txgi_max)
++#define IS_PG_TXPWR_DIFF_INVALID(_diff) ((_diff) > 7 || (_diff) < -8)
++#define PG_TXPWR_INVALID_BASE 255
++#define PG_TXPWR_INVALID_DIFF 8
++
++#if !IS_PG_TXPWR_DIFF_INVALID(PG_TXPWR_INVALID_DIFF)
++#error "PG_TXPWR_DIFF definition has problem"
++#endif
++
++#define PG_TXPWR_SRC_PG_DATA	0
++#define PG_TXPWR_SRC_IC_DEF		1
++#define PG_TXPWR_SRC_DEF		2
++#define PG_TXPWR_SRC_NUM		3
++
++const char *const _pg_txpwr_src_str[] = {
++	"PG_DATA",
++	"IC_DEF",
++	"DEF",
++	"UNKNOWN"
++};
++
++#define pg_txpwr_src_str(src) (((src) >= PG_TXPWR_SRC_NUM) ? _pg_txpwr_src_str[PG_TXPWR_SRC_NUM] : _pg_txpwr_src_str[(src)])
++
++const char *const _txpwr_pg_mode_str[] = {
++	"PWR_IDX",
++	"TSSI_OFFSET",
++	"UNKNOWN",
++};
++
++static const u8 rate_sec_base[RATE_SECTION_NUM] = {
++	MGN_11M,
++	MGN_54M,
++	MGN_MCS7,
++	MGN_MCS15,
++	MGN_MCS23,
++	MGN_MCS31,
++	MGN_VHT1SS_MCS7,
++	MGN_VHT2SS_MCS7,
++	MGN_VHT3SS_MCS7,
++	MGN_VHT4SS_MCS7,
++};
++
++#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
++typedef struct _TxPowerInfo24G {
++	u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
++	u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
++	/* If only one tx, only BW20 and OFDM are used. */
++	s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
++	s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
++	s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
++	s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
++} TxPowerInfo24G;
++
++typedef struct _TxPowerInfo5G {
++	u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
++	/* If only one tx, only BW20, OFDM, BW80 and BW160 are used. */
++	s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
++	s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
++	s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
++	s8 BW80_Diff[MAX_RF_PATH][MAX_TX_COUNT];
++	s8 BW160_Diff[MAX_RF_PATH][MAX_TX_COUNT];
++} TxPowerInfo5G;
++
++#ifndef DBG_PG_TXPWR_READ
++#define DBG_PG_TXPWR_READ 0
++#endif
++
++#if DBG_PG_TXPWR_READ
++static void dump_pg_txpwr_info_2g(void *sel, TxPowerInfo24G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt)
++{
++	int path, group, tx_idx;
++
++	RTW_PRINT_SEL(sel, "2.4G\n");
++	RTW_PRINT_SEL(sel, "CCK-1T base:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (group = 0; group < MAX_CHNL_GROUP_24G; group++)
++		_RTW_PRINT_SEL(sel, "G%02d ", group);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (group = 0; group < MAX_CHNL_GROUP_24G; group++)
++			_RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexCCK_Base[path][group]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "CCK diff:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
++		_RTW_PRINT_SEL(sel, "%dT ", path + 1);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->CCK_Diff[path][tx_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "BW40-1S base:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++)
++		_RTW_PRINT_SEL(sel, "G%02d ", group);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++)
++			_RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexBW40_Base[path][group]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "OFDM diff:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
++		_RTW_PRINT_SEL(sel, "%dT ", path + 1);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->OFDM_Diff[path][tx_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "BW20 diff:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
++		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW20_Diff[path][tx_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "BW40 diff:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
++		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW40_Diff[path][tx_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++}
++
++static void dump_pg_txpwr_info_5g(void *sel, TxPowerInfo5G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt)
++{
++	int path, group, tx_idx;
++
++	RTW_PRINT_SEL(sel, "5G\n");
++	RTW_PRINT_SEL(sel, "BW40-1S base:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
++		_RTW_PRINT_SEL(sel, "G%02d ", group);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
++			_RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexBW40_Base[path][group]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "OFDM diff:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
++		_RTW_PRINT_SEL(sel, "%dT ", path + 1);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->OFDM_Diff[path][tx_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "BW20 diff:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
++		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW20_Diff[path][tx_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "BW40 diff:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
++		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW40_Diff[path][tx_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "BW80 diff:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
++		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW80_Diff[path][tx_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "BW160 diff:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
++		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW160_Diff[path][tx_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++}
++#endif /* DBG_PG_TXPWR_READ */
++
++const struct map_t pg_txpwr_def_info =
++	MAP_ENT(0xB8, 1, 0xFF
++		, MAPSEG_ARRAY_ENT(0x10, 168,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE,
++			0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
++			0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A,
++			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
++			0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24,
++			0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
++			0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
++			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE,
++			0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE)
++	);
++
++#ifdef CONFIG_RTL8188E
++static const struct map_t rtl8188e_pg_txpwr_def_info =
++	MAP_ENT(0xB8, 1, 0xFF
++		, MAPSEG_ARRAY_ENT(0x10, 12,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24)
++	);
++#endif
++
++#ifdef CONFIG_RTL8188F
++static const struct map_t rtl8188f_pg_txpwr_def_info =
++	MAP_ENT(0xB8, 1, 0xFF
++		, MAPSEG_ARRAY_ENT(0x10, 12,
++			0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x27, 0x27, 0x27, 0x27, 0x24)
++	);
++#endif
++
++#ifdef CONFIG_RTL8188GTV
++static const struct map_t rtl8188gtv_pg_txpwr_def_info =
++	MAP_ENT(0xB8, 1, 0xFF
++		, MAPSEG_ARRAY_ENT(0x10, 12,
++			0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x27, 0x27, 0x27, 0x27, 0x24)
++	);
++#endif
++
++#ifdef CONFIG_RTL8723B
++static const struct map_t rtl8723b_pg_txpwr_def_info =
++	MAP_ENT(0xB8, 2, 0xFF
++		, MAPSEG_ARRAY_ENT(0x10, 12,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0xE0)
++		, MAPSEG_ARRAY_ENT(0x3A, 12,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0xE0)
++	);
++#endif
++
++#ifdef CONFIG_RTL8703B
++static const struct map_t rtl8703b_pg_txpwr_def_info =
++	MAP_ENT(0xB8, 1, 0xFF
++		, MAPSEG_ARRAY_ENT(0x10, 12,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
++	);
++#endif
++
++#ifdef CONFIG_RTL8723D
++static const struct map_t rtl8723d_pg_txpwr_def_info =
++	MAP_ENT(0xB8, 2, 0xFF
++		, MAPSEG_ARRAY_ENT(0x10, 12,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
++		, MAPSEG_ARRAY_ENT(0x3A, 12,
++			0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x21, 0x21, 0x21, 0x21, 0x21, 0x02)
++	);
++#endif
++
++#ifdef CONFIG_RTL8192E
++static const struct map_t rtl8192e_pg_txpwr_def_info =
++	MAP_ENT(0xB8, 2, 0xFF
++		, MAPSEG_ARRAY_ENT(0x10, 14,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
++		, MAPSEG_ARRAY_ENT(0x3A, 14,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
++	);
++#endif
++
++#ifdef CONFIG_RTL8821A
++static const struct map_t rtl8821a_pg_txpwr_def_info =
++	MAP_ENT(0xB8, 1, 0xFF
++		, MAPSEG_ARRAY_ENT(0x10, 39,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xFF, 0xFF, 0xFF, 0xFF,
++			0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
++			0x04, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00)
++	);
++#endif
++
++#ifdef CONFIG_RTL8821C
++static const struct map_t rtl8821c_pg_txpwr_def_info =
++	MAP_ENT(0xB8, 1, 0xFF
++		, MAPSEG_ARRAY_ENT(0x10, 54,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xFF, 0xFF, 0xFF, 0xFF,
++			0xFF, 0xFF, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
++			0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xEC, 0xFF, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
++	);
++#endif
++
++#ifdef CONFIG_RTL8710B
++static const struct map_t rtl8710b_pg_txpwr_def_info =
++	MAP_ENT(0xC8, 1, 0xFF
++		, MAPSEG_ARRAY_ENT(0x20, 12,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x20)
++	);
++#endif
++
++#ifdef CONFIG_RTL8812A
++static const struct map_t rtl8812a_pg_txpwr_def_info =
++	MAP_ENT(0xB8, 1, 0xFF
++		, MAPSEG_ARRAY_ENT(0x10, 82,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF,
++			0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
++			0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, 0x00, 0xEE, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A,
++			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF,
++			0x00, 0xEE)
++	);
++#endif
++
++#ifdef CONFIG_RTL8822B
++static const struct map_t rtl8822b_pg_txpwr_def_info =
++	MAP_ENT(0xB8, 1, 0xFF
++		, MAPSEG_ARRAY_ENT(0x10, 82,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF,
++			0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
++			0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, 0xEC, 0xEC, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A,
++			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF,
++			0xEC, 0xEC)
++	);
++#endif
++
++#ifdef CONFIG_RTL8822C
++static const struct map_t rtl8822c_pg_txpwr_def_info =
++	MAP_ENT(0xB8, 1, 0xFF
++		, MAPSEG_ARRAY_ENT(0x10, 82,
++			0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x02, 0x00, 0x00, 0xFF, 0xFF,
++			0xFF, 0xFF, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33,
++			0x02, 0x00, 0xFF, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0xFF, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33,
++			0x33, 0x33, 0x33, 0x33, 0x33, 0x02, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x33, 0x33, 0x33, 0x33,
++			0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x02, 0x00, 0xFF, 0xFF, 0x00, 0xFF,
++			0x00, 0x00)
++	);
++#endif
++
++#ifdef CONFIG_RTL8814A
++static const struct map_t rtl8814a_pg_txpwr_def_info =
++	MAP_ENT(0xB8, 1, 0xFF
++		, MAPSEG_ARRAY_ENT(0x10, 168,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE,
++			0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
++			0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A,
++			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
++			0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02,
++			0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
++			0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
++			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE,
++			0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE)
++	);
++#endif
++
++#ifdef CONFIG_RTL8192F/*use 8192F default,no document*/
++static const struct map_t rtl8192f_pg_txpwr_def_info =
++	MAP_ENT(0xB8, 2, 0xFF
++		, MAPSEG_ARRAY_ENT(0x10, 14,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
++		, MAPSEG_ARRAY_ENT(0x3A, 14,
++			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
++	);
++#endif
++
++#ifdef CONFIG_RTL8814B
++static const struct map_t rtl8814b_pg_txpwr_def_info =
++	MAP_ENT(0xB8, 1, 0xFF
++		, MAPSEG_ARRAY_ENT(0x10, 168,
++			0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x02, 0xFF, 0xFF, 0xFF, 0xFF,
++			0xFF, 0xFF, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
++			0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xEC, 0xFF, 0xFF, 0xFF, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
++			0x28, 0x28, 0x28, 0x28, 0x28, 0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++			0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++			0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++			0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++			0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++			0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++			0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++			0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF)
++	);
++#endif
++
++const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter)
++{
++	u8 interface_type = 0;
++	const struct map_t *map = NULL;
++
++	interface_type = rtw_get_intf_type(adapter);
++
++	switch (rtw_get_chip_type(adapter)) {
++#ifdef CONFIG_RTL8723B
++	case RTL8723B:
++		map = &rtl8723b_pg_txpwr_def_info;
++		break;
++#endif
++#ifdef CONFIG_RTL8703B
++	case RTL8703B:
++		map = &rtl8703b_pg_txpwr_def_info;
++		break;
++#endif
++#ifdef CONFIG_RTL8723D
++	case RTL8723D:
++		map = &rtl8723d_pg_txpwr_def_info;
++		break;
++#endif
++#ifdef CONFIG_RTL8188E
++	case RTL8188E:
++		map = &rtl8188e_pg_txpwr_def_info;
++		break;
++#endif
++#ifdef CONFIG_RTL8188F
++	case RTL8188F:
++		map = &rtl8188f_pg_txpwr_def_info;
++		break;
++#endif
++#ifdef CONFIG_RTL8188GTV
++	case RTL8188GTV:
++		map = &rtl8188gtv_pg_txpwr_def_info;
++		break;
++#endif
++#ifdef CONFIG_RTL8812A
++	case RTL8812:
++		map = &rtl8812a_pg_txpwr_def_info;
++		break;
++#endif
++#ifdef CONFIG_RTL8821A
++	case RTL8821:
++		map = &rtl8821a_pg_txpwr_def_info;
++		break;
++#endif
++#ifdef CONFIG_RTL8192E
++	case RTL8192E:
++		map = &rtl8192e_pg_txpwr_def_info;
++		break;
++#endif
++#ifdef CONFIG_RTL8814A
++	case RTL8814A:
++		map = &rtl8814a_pg_txpwr_def_info;
++		break;
++#endif
++#ifdef CONFIG_RTL8822B
++	case RTL8822B:
++		map = &rtl8822b_pg_txpwr_def_info;
++		break;
++#endif
++#ifdef CONFIG_RTL8821C
++	case RTL8821C:
++		map = &rtl8821c_pg_txpwr_def_info;
++		break;
++#endif
++#ifdef CONFIG_RTL8710B
++	case RTL8710B:
++		map = &rtl8710b_pg_txpwr_def_info;
++		break;
++#endif
++#ifdef CONFIG_RTL8192F
++	case RTL8192F:
++		map = &rtl8192f_pg_txpwr_def_info;
++		break;
++#endif
++#ifdef CONFIG_RTL8822C
++	case RTL8822C:
++		map = &rtl8822c_pg_txpwr_def_info;
++		break;
++#endif
++#ifdef CONFIG_RTL8814B
++	case RTL8814B:
++		map = &rtl8814b_pg_txpwr_def_info;
++		break;
++#endif
++	}
++
++	if (map == NULL) {
++		RTW_ERR("%s: unknown chip_type:%u\n"
++			, __func__, rtw_get_chip_type(adapter));
++		rtw_warn_on(1);
++	}
++
++	return map;
++}
++
++static u8 hal_chk_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	u8 path, group, tx_idx;
++
++	if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G))
++		return _SUCCESS;
++
++	for (path = 0; path < MAX_RF_PATH; path++) {
++		if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path))
++			continue;
++		for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
++			if (IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexCCK_Base[path][group])
++				|| IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group]))
++				return _FAIL;
++		}
++		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
++			if (tx_idx + 1 > hal_data->max_tx_cnt)
++				continue;
++			if (IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx])
++				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
++				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
++				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx]))
++				return _FAIL;
++		}
++	}
++
++	return _SUCCESS;
++}
++
++static u8 hal_chk_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info)
++{
++#if CONFIG_IEEE80211_BAND_5GHZ
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	u8 path, group, tx_idx;
++
++	if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G))
++		return _SUCCESS;
++
++	for (path = 0; path < MAX_RF_PATH; path++) {
++		if (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
++			continue;
++		for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
++			if (IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group]))
++				return _FAIL;
++		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
++			if (tx_idx + 1 > hal_data->max_tx_cnt)
++				continue;
++			if (IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
++				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
++				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
++				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx])
++				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx]))
++				return _FAIL;
++		}
++	}
++#endif /* CONFIG_IEEE80211_BAND_5GHZ */
++	return _SUCCESS;
++}
++
++static inline void hal_init_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	u8 path, group, tx_idx;
++
++	if (pwr_info == NULL)
++		return;
++
++	_rtw_memset(pwr_info, 0, sizeof(TxPowerInfo24G));
++
++	/* init with invalid value */
++	for (path = 0; path < MAX_RF_PATH; path++) {
++		for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
++			pwr_info->IndexCCK_Base[path][group] = PG_TXPWR_INVALID_BASE;
++			pwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE;
++		}
++		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
++			pwr_info->CCK_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
++			pwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
++			pwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
++			pwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
++		}
++	}
++
++	/* init for dummy base and diff */
++	for (path = 0; path < MAX_RF_PATH; path++) {
++		if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path))
++			break;
++		/* 2.4G BW40 base has 1 less group than CCK base*/
++		pwr_info->IndexBW40_Base[path][MAX_CHNL_GROUP_24G - 1] = 0;
++
++		/* dummy diff */
++		pwr_info->CCK_Diff[path][0] = 0; /* 2.4G CCK-1TX */
++		pwr_info->BW40_Diff[path][0] = 0; /* 2.4G BW40-1S */
++	}
++}
++
++static inline void hal_init_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info)
++{
++#if CONFIG_IEEE80211_BAND_5GHZ
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	u8 path, group, tx_idx;
++
++	if (pwr_info == NULL)
++		return;
++
++	_rtw_memset(pwr_info, 0, sizeof(TxPowerInfo5G));
++
++	/* init with invalid value */
++	for (path = 0; path < MAX_RF_PATH; path++) {
++		for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
++			pwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE;
++		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
++			pwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
++			pwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
++			pwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
++			pwr_info->BW80_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
++			pwr_info->BW160_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
++		}
++	}
++
++	for (path = 0; path < MAX_RF_PATH; path++) {
++		if (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
++			break;
++		/* dummy diff */
++		pwr_info->BW40_Diff[path][0] = 0; /* 5G BW40-1S */
++	}
++#endif /* CONFIG_IEEE80211_BAND_5GHZ */
++}
++
++#if DBG_PG_TXPWR_READ
++#define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) 1
++#else
++#define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) (_txpwr_src > PG_TXPWR_SRC_PG_DATA)
++#endif
++
++u16 hal_load_pg_txpwr_info_path_2g(
++	_adapter *adapter,
++	TxPowerInfo24G	*pwr_info,
++	u32 path,
++	u8 txpwr_src,
++	const struct map_t *txpwr_map,
++	u16 pg_offset)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	u16 offset = pg_offset;
++	u8 group, tx_idx;
++	u8 val;
++	u8 tmp_base;
++	s8 tmp_diff;
++
++	if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G)) {
++		offset += PG_TXPWR_1PATH_BYTE_NUM_2G;
++		goto exit;
++	}
++
++	if (DBG_PG_TXPWR_READ)
++		RTW_INFO("%s [%c] offset:0x%03x\n", __func__, rf_path_char(path), offset);
++
++	for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
++		if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
++			tmp_base = map_read8(txpwr_map, offset);
++			if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)
++				&& IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexCCK_Base[path][group])
++			) {
++				pwr_info->IndexCCK_Base[path][group] = tmp_base;
++				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++					RTW_INFO("[%c] 2G G%02d CCK-1T base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
++			}
++		}
++		offset++;
++	}
++
++	for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
++		if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
++			tmp_base = map_read8(txpwr_map, offset);
++			if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)
++				&& IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group])
++			) {
++				pwr_info->IndexBW40_Base[path][group] =	tmp_base;
++				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++					RTW_INFO("[%c] 2G G%02d BW40-1S base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
++			}
++		}
++		offset++;
++	}
++
++	for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
++		if (tx_idx == 0) {
++			if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
++				val = map_read8(txpwr_map, offset);
++				tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
++				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
++					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
++				) {
++					pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
++					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++						RTW_INFO("[%c] 2G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
++				}
++				tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
++				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
++					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
++				) {
++					pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
++					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++						RTW_INFO("[%c] 2G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
++				}
++			}
++			offset++;
++		} else {
++			if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && tx_idx + 1 <= hal_data->max_tx_cnt) {
++				val = map_read8(txpwr_map, offset);
++				tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
++				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
++					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
++				) {
++					pwr_info->BW40_Diff[path][tx_idx] = tmp_diff;
++					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++						RTW_INFO("[%c] 2G BW40-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
++
++				}
++				tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
++				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
++					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
++				) {
++					pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
++					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++						RTW_INFO("[%c] 2G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
++				}
++			}
++			offset++;
++
++			if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && tx_idx + 1 <= hal_data->max_tx_cnt) {
++				val = map_read8(txpwr_map, offset);
++				tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
++				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
++					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
++				) {
++					pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
++					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++						RTW_INFO("[%c] 2G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
++				}
++				tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
++				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
++					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx])
++				) {
++					pwr_info->CCK_Diff[path][tx_idx] =	tmp_diff;
++					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++						RTW_INFO("[%c] 2G CCK-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
++				}
++			}
++			offset++;
++		}
++	}
++
++	if (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_2G) {
++		RTW_ERR("%s parse %d bytes != %d\n", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_2G);
++		rtw_warn_on(1);
++	}
++
++exit:
++	return offset;
++}
++
++u16 hal_load_pg_txpwr_info_path_5g(
++	_adapter *adapter,
++	TxPowerInfo5G	*pwr_info,
++	u32 path,
++	u8 txpwr_src,
++	const struct map_t *txpwr_map,
++	u16 pg_offset)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	u16 offset = pg_offset;
++	u8 group, tx_idx;
++	u8 val;
++	u8 tmp_base;
++	s8 tmp_diff;
++
++#if CONFIG_IEEE80211_BAND_5GHZ
++	if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G))
++#endif
++	{
++		offset += PG_TXPWR_1PATH_BYTE_NUM_5G;
++		goto exit;
++	}
++
++#if CONFIG_IEEE80211_BAND_5GHZ
++	if (DBG_PG_TXPWR_READ)
++		RTW_INFO("%s[%c] eaddr:0x%03x\n", __func__, rf_path_char(path), offset);
++
++	for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
++		if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) {
++			tmp_base = map_read8(txpwr_map, offset);
++			if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)
++				&& IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group])
++			) {
++				pwr_info->IndexBW40_Base[path][group] = tmp_base;
++				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++					RTW_INFO("[%c] 5G G%02d BW40-1S base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
++			}
++		}
++		offset++;
++	}
++
++	for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
++		if (tx_idx == 0) {
++			if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) {
++				val = map_read8(txpwr_map, offset);
++				tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
++				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
++					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
++				) {
++					pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
++					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++						RTW_INFO("[%c] 5G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
++				}
++				tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
++				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
++					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
++				) {
++					pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
++					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++						RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
++				}
++			}
++			offset++;
++		} else {
++			if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && tx_idx + 1 <= hal_data->max_tx_cnt) {
++				val = map_read8(txpwr_map, offset);
++				tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
++				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
++					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
++				) {
++					pwr_info->BW40_Diff[path][tx_idx] = tmp_diff;
++					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++						RTW_INFO("[%c] 5G BW40-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
++				}
++				tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
++				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
++					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
++				) {
++					pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
++					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++						RTW_INFO("[%c] 5G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
++				}
++			}
++			offset++;
++		}
++	}
++
++	/* OFDM diff 2T ~ 3T */
++	if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && hal_data->max_tx_cnt > 1) {
++		val = map_read8(txpwr_map, offset);
++		tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
++		if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
++			&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][1])
++		) {
++			pwr_info->OFDM_Diff[path][1] = tmp_diff;
++			if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++				RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 2, tmp_diff, pg_txpwr_src_str(txpwr_src));
++		}
++		if (hal_data->max_tx_cnt > 2) {
++			tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
++			if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
++				&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][2])
++			) {
++				pwr_info->OFDM_Diff[path][2] = tmp_diff;
++				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++					RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 3, tmp_diff, pg_txpwr_src_str(txpwr_src));
++			}
++		}
++	}
++	offset++;
++
++	/* OFDM diff 4T */
++	if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && hal_data->max_tx_cnt > 3) {
++		val = map_read8(txpwr_map, offset);
++		tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
++		if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
++			&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][3])
++		) {
++			pwr_info->OFDM_Diff[path][3] = tmp_diff;
++			if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++				RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 4, tmp_diff, pg_txpwr_src_str(txpwr_src));
++		}
++	}
++	offset++;
++
++	for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
++		if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && tx_idx + 1 <= hal_data->max_tx_cnt) {
++			val = map_read8(txpwr_map, offset);
++			tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
++			if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
++				&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx])
++			) {
++				pwr_info->BW80_Diff[path][tx_idx] = tmp_diff;
++				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++					RTW_INFO("[%c] 5G BW80-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
++			}
++			tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
++			if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
++				&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx])
++			) {
++				pwr_info->BW160_Diff[path][tx_idx] = tmp_diff;
++				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
++					RTW_INFO("[%c] 5G BW160-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
++			}
++		}
++		offset++;
++	}
++
++	if (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_5G) {
++		RTW_ERR("%s parse %d bytes != %d\n", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_5G);
++		rtw_warn_on(1);
++	}
++
++#endif /* CONFIG_IEEE80211_BAND_5GHZ */
++
++exit:
++	return offset;
++}
++
++void hal_load_pg_txpwr_info(
++	_adapter *adapter,
++	TxPowerInfo24G *pwr_info_2g,
++	TxPowerInfo5G *pwr_info_5g,
++	u8 *pg_data,
++	BOOLEAN AutoLoadFail
++)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	u8 path;
++	u16 pg_offset;
++	u8 txpwr_src = PG_TXPWR_SRC_PG_DATA;
++	struct map_t pg_data_map = MAP_ENT(184, 1, 0xFF, MAPSEG_PTR_ENT(0x00, 184, pg_data));
++	const struct map_t *txpwr_map = NULL;
++
++	/* init with invalid value and some dummy base and diff */
++	hal_init_pg_txpwr_info_2g(adapter, pwr_info_2g);
++	hal_init_pg_txpwr_info_5g(adapter, pwr_info_5g);
++
++select_src:
++	pg_offset = hal_spec->pg_txpwr_saddr;
++
++	switch (txpwr_src) {
++	case PG_TXPWR_SRC_PG_DATA:
++		txpwr_map = &pg_data_map;
++		break;
++	case PG_TXPWR_SRC_IC_DEF:
++		txpwr_map = hal_pg_txpwr_def_info(adapter);
++		break;
++	case PG_TXPWR_SRC_DEF:
++	default:
++		txpwr_map = &pg_txpwr_def_info;
++		break;
++	};
++
++	if (txpwr_map == NULL)
++		goto end_parse;
++
++	for (path = 0; path < MAX_RF_PATH ; path++) {
++		if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
++			break;
++		pg_offset = hal_load_pg_txpwr_info_path_2g(adapter, pwr_info_2g, path, txpwr_src, txpwr_map, pg_offset);
++		pg_offset = hal_load_pg_txpwr_info_path_5g(adapter, pwr_info_5g, path, txpwr_src, txpwr_map, pg_offset);
++	}
++
++	if (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) == _SUCCESS
++		&& hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) == _SUCCESS)
++		goto exit;
++
++end_parse:
++	txpwr_src++;
++	if (txpwr_src < PG_TXPWR_SRC_NUM)
++		goto select_src;
++
++	if (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) != _SUCCESS
++		|| hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) != _SUCCESS)
++		rtw_warn_on(1);
++
++exit:
++	#if DBG_PG_TXPWR_READ
++	if (pwr_info_2g)
++		dump_pg_txpwr_info_2g(RTW_DBGDUMP, pwr_info_2g, 4, 4);
++	if (pwr_info_5g)
++		dump_pg_txpwr_info_5g(RTW_DBGDUMP, pwr_info_5g, 4, 4);
++	#endif
++
++	return;
++}
++#endif /* CONFIG_TXPWR_PG_WITH_PWR_IDX */
++
++#ifdef CONFIG_EFUSE_CONFIG_FILE
++
++#define EFUSE_POWER_INDEX_INVALID 0xFF
++
++static u8 _check_phy_efuse_tx_power_info_valid(u8 *pg_data, int chk_len, u16 pg_offset)
++{
++	int ff_cnt = 0;
++	int i;
++
++	for (i = 0; i < chk_len; i++) {
++		if (*(pg_data + pg_offset + i) == 0xFF)
++			ff_cnt++;
++	}
++
++	if (ff_cnt == 0)
++		return _TRUE;
++	else if (ff_cnt == chk_len)
++		return _FALSE;
++	else
++		return EFUSE_POWER_INDEX_INVALID;
++}
++
++int check_phy_efuse_tx_power_info_valid(_adapter *adapter)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	u8 *pg_data = hal_data->efuse_eeprom_data;
++	u16 pg_offset = hal_spec->pg_txpwr_saddr;
++	u8 path;
++	u8 valid_2g_path_bmp = 0;
++#if CONFIG_IEEE80211_BAND_5GHZ
++	u8 valid_5g_path_bmp = 0;
++#endif
++
++	/* NOTE: TSSI offset use the same layout as TXPWR base */
++
++	for (path = 0; path < MAX_RF_PATH; path++) {
++		u8 ret = _FALSE;
++
++		if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
++			break;
++
++		if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
++			ret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_2G, pg_offset);
++			if (ret == _TRUE)
++				valid_2g_path_bmp |= BIT(path);
++			else if (ret == EFUSE_POWER_INDEX_INVALID)
++				return _FALSE;
++		}
++		pg_offset += PG_TXPWR_1PATH_BYTE_NUM_2G;
++
++		#if CONFIG_IEEE80211_BAND_5GHZ
++		if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) {
++			ret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_5G, pg_offset);
++			if (ret == _TRUE)
++				valid_5g_path_bmp |= BIT(path);
++			else if (ret == EFUSE_POWER_INDEX_INVALID)
++				return _FALSE;
++		}
++		#endif
++		pg_offset += PG_TXPWR_1PATH_BYTE_NUM_5G;
++	}
++
++	if ((hal_chk_band_cap(adapter, BAND_CAP_2G) && valid_2g_path_bmp)
++		#if CONFIG_IEEE80211_BAND_5GHZ
++		|| (hal_chk_band_cap(adapter, BAND_CAP_5G) && valid_5g_path_bmp)
++		#endif
++	)
++		return _TRUE;
++
++	return _FALSE;
++}
++#endif /* CONFIG_EFUSE_CONFIG_FILE */
++
++#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
++void hal_load_txpwr_info(_adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	u8 max_tx_cnt = hal_data->max_tx_cnt;
++	u8 *pg_data = hal_data->efuse_eeprom_data;
++	TxPowerInfo24G *pwr_info_2g = NULL;
++	TxPowerInfo5G *pwr_info_5g = NULL;
++	u8 rfpath, ch_idx, group, tx_idx;
++
++	if (hal_chk_band_cap(adapter, BAND_CAP_2G))
++		pwr_info_2g = rtw_vmalloc(sizeof(TxPowerInfo24G));
++#if CONFIG_IEEE80211_BAND_5GHZ
++	if (hal_chk_band_cap(adapter, BAND_CAP_5G))
++		pwr_info_5g = rtw_vmalloc(sizeof(TxPowerInfo5G));
++#endif
++
++	/* load from pg data (or default value) */
++	hal_load_pg_txpwr_info(adapter, pwr_info_2g, pwr_info_5g, pg_data, _FALSE);
++
++	/* transform to hal_data */
++	for (rfpath = 0; rfpath < MAX_RF_PATH; rfpath++) {
++
++		if (!pwr_info_2g || !HAL_SPEC_CHK_RF_PATH_2G(hal_spec, rfpath))
++			goto bypass_2g;
++
++		/* 2.4G base */
++		for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++) {
++			u8 cck_group;
++
++			if (rtw_get_ch_group(ch_idx + 1, &group, &cck_group) != BAND_ON_2_4G)
++				continue;
++
++			hal_data->Index24G_CCK_Base[rfpath][ch_idx] = pwr_info_2g->IndexCCK_Base[rfpath][cck_group];
++			hal_data->Index24G_BW40_Base[rfpath][ch_idx] = pwr_info_2g->IndexBW40_Base[rfpath][group];
++		}
++
++		/* 2.4G diff */
++		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
++			if (tx_idx + 1 > max_tx_cnt)
++				break;
++
++			hal_data->CCK_24G_Diff[rfpath][tx_idx] = pwr_info_2g->CCK_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
++			hal_data->OFDM_24G_Diff[rfpath][tx_idx] = pwr_info_2g->OFDM_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
++			hal_data->BW20_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW20_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
++			hal_data->BW40_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW40_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
++		}
++bypass_2g:
++		;
++
++#if CONFIG_IEEE80211_BAND_5GHZ
++		if (!pwr_info_5g || !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, rfpath))
++			goto bypass_5g;
++
++		/* 5G base */
++		for (ch_idx = 0; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
++			if (rtw_get_ch_group(center_ch_5g_all[ch_idx], &group, NULL) != BAND_ON_5G)
++				continue;
++			hal_data->Index5G_BW40_Base[rfpath][ch_idx] = pwr_info_5g->IndexBW40_Base[rfpath][group];
++		}
++
++		for (ch_idx = 0 ; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++) {
++			u8 upper, lower;
++
++			if (rtw_get_ch_group(center_ch_5g_80m[ch_idx], &group, NULL) != BAND_ON_5G)
++				continue;
++
++			upper = pwr_info_5g->IndexBW40_Base[rfpath][group];
++			lower = pwr_info_5g->IndexBW40_Base[rfpath][group + 1];
++			hal_data->Index5G_BW80_Base[rfpath][ch_idx] = (upper + lower) / 2;
++		}
++
++		/* 5G diff */
++		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
++			if (tx_idx + 1 > max_tx_cnt)
++				break;
++
++			hal_data->OFDM_5G_Diff[rfpath][tx_idx] = pwr_info_5g->OFDM_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
++			hal_data->BW20_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW20_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
++			hal_data->BW40_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW40_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
++			hal_data->BW80_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW80_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
++		}
++bypass_5g:
++		;
++#endif /* CONFIG_IEEE80211_BAND_5GHZ */
++	}
++
++	if (pwr_info_2g)
++		rtw_vmfree(pwr_info_2g, sizeof(TxPowerInfo24G));
++	if (pwr_info_5g)
++		rtw_vmfree(pwr_info_5g, sizeof(TxPowerInfo5G));
++}
++
++void dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	int path, ch_idx, tx_idx;
++
++	RTW_PRINT_SEL(sel, "2.4G\n");
++	RTW_PRINT_SEL(sel, "CCK-1T base:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
++		_RTW_PRINT_SEL(sel, "%3d ", center_ch_2g[ch_idx]);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
++			_RTW_PRINT_SEL(sel, "%3u ", hal_data->Index24G_CCK_Base[path][ch_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "CCK diff:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++		_RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++			_RTW_PRINT_SEL(sel, "%2d ", hal_data->CCK_24G_Diff[path][tx_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "BW40-1S base:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
++		_RTW_PRINT_SEL(sel, "%3d ", center_ch_2g[ch_idx]);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
++			_RTW_PRINT_SEL(sel, "%3u ", hal_data->Index24G_BW40_Base[path][ch_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "OFDM diff:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++		_RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++			_RTW_PRINT_SEL(sel, "%2d ", hal_data->OFDM_24G_Diff[path][tx_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "BW20 diff:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++		_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++			_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW20_24G_Diff[path][tx_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "BW40 diff:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++		_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++			_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW40_24G_Diff[path][tx_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++}
++
++void dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt)
++{
++#if CONFIG_IEEE80211_BAND_5GHZ
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	int path, ch_idx, tx_idx;
++	u8 dump_section = 0;
++	u8 ch_idx_s = 0;
++
++	RTW_PRINT_SEL(sel, "5G\n");
++	RTW_PRINT_SEL(sel, "BW40-1S base:\n");
++	do {
++		#define DUMP_5G_BW40_BASE_SECTION_NUM 3
++		u8 end[DUMP_5G_BW40_BASE_SECTION_NUM] = {64, 144, 177};
++
++		RTW_PRINT_SEL(sel, "%4s ", "");
++		for (ch_idx = ch_idx_s; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
++			_RTW_PRINT_SEL(sel, "%3d ", center_ch_5g_all[ch_idx]);
++			if (end[dump_section] == center_ch_5g_all[ch_idx])
++				break;
++		}
++		_RTW_PRINT_SEL(sel, "\n");
++		for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++			RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++			for (ch_idx = ch_idx_s; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
++				_RTW_PRINT_SEL(sel, "%3u ", hal_data->Index5G_BW40_Base[path][ch_idx]);
++				if (end[dump_section] == center_ch_5g_all[ch_idx])
++					break;
++			}
++			_RTW_PRINT_SEL(sel, "\n");
++		}
++		RTW_PRINT_SEL(sel, "\n");
++
++		ch_idx_s = ch_idx + 1;
++		dump_section++;
++		if (dump_section >= DUMP_5G_BW40_BASE_SECTION_NUM)
++			break;
++	} while (1);
++
++	RTW_PRINT_SEL(sel, "BW80-1S base:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (ch_idx = 0; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++)
++		_RTW_PRINT_SEL(sel, "%3d ", center_ch_5g_80m[ch_idx]);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (ch_idx = 0; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++)
++			_RTW_PRINT_SEL(sel, "%3u ", hal_data->Index5G_BW80_Base[path][ch_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "OFDM diff:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++		_RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++			_RTW_PRINT_SEL(sel, "%2d ", hal_data->OFDM_5G_Diff[path][tx_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "BW20 diff:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++		_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++			_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW20_5G_Diff[path][tx_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "BW40 diff:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++		_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++			_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW40_5G_Diff[path][tx_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "BW80 diff:\n");
++	RTW_PRINT_SEL(sel, "%4s ", "");
++	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++		_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
++	_RTW_PRINT_SEL(sel, "\n");
++	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
++		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
++		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
++			_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW80_5G_Diff[path][tx_idx]);
++		_RTW_PRINT_SEL(sel, "\n");
++	}
++	RTW_PRINT_SEL(sel, "\n");
++#endif /* CONFIG_IEEE80211_BAND_5GHZ */
++}
++#endif /* CONFIG_TXPWR_PG_WITH_PWR_IDX */
++
++/*
++* rtw_regsty_get_target_tx_power -
++*
++* Return dBm or -1 for undefined
++*/
++s8 rtw_regsty_get_target_tx_power(
++		PADAPTER		Adapter,
++		u8				Band,
++		u8				RfPath,
++		RATE_SECTION	RateSection
++)
++{
++	struct registry_priv *regsty = adapter_to_regsty(Adapter);
++	s8 value = 0;
++
++	if (RfPath > RF_PATH_D) {
++		RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
++		return -1;
++	}
++
++	if (Band != BAND_ON_2_4G
++		#if CONFIG_IEEE80211_BAND_5GHZ
++		&& Band != BAND_ON_5G
++		#endif
++	) {
++		RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
++		return -1;
++	}
++
++	if (RateSection >= RATE_SECTION_NUM
++		#if CONFIG_IEEE80211_BAND_5GHZ
++		|| (Band == BAND_ON_5G && RateSection == CCK)
++		#endif
++	) {
++		RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d\n", __func__
++			, RateSection, Band, RfPath);
++		return -1;
++	}
++
++	if (Band == BAND_ON_2_4G)
++		value = regsty->target_tx_pwr_2g[RfPath][RateSection];
++#if CONFIG_IEEE80211_BAND_5GHZ
++	else /* BAND_ON_5G */
++		value = regsty->target_tx_pwr_5g[RfPath][RateSection - 1];
++#endif
++
++	return value;
++}
++
++bool rtw_regsty_chk_target_tx_power_valid(_adapter *adapter)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	int path, tx_num, band, rs;
++	s8 target;
++
++	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
++		if (!hal_is_band_support(adapter, band))
++			continue;
++
++		for (path = 0; path < RF_PATH_MAX; path++) {
++			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
++				break;
++
++			for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
++				tx_num = rate_section_to_tx_num(rs);
++				if (tx_num + 1 > GET_HAL_TX_NSS(adapter))
++					continue;
++
++				if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
++					continue;
++
++				if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
++					continue;
++
++				target = rtw_regsty_get_target_tx_power(adapter, band, path, rs);
++				if (target == -1) {
++					RTW_PRINT("%s return _FALSE for band:%d, path:%d, rs:%d, t:%d\n", __func__, band, path, rs, target);
++					return _FALSE;
++				}
++			}
++		}
++	}
++
++	return _TRUE;
++}
++
++/*
++* phy_get_target_txpwr -
++*
++* Return value in unit of TX Gain Index
++*/
++u8 phy_get_target_txpwr(
++		PADAPTER		Adapter,
++		u8				Band,
++		u8				RfPath,
++		RATE_SECTION	RateSection
++)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++	u8 value = 0;
++
++	if (RfPath > RF_PATH_D) {
++		RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
++		return 0;
++	}
++
++	if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
++		RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
++		return 0;
++	}
++
++	if (RateSection >= RATE_SECTION_NUM
++		|| (Band == BAND_ON_5G && RateSection == CCK)
++	) {
++		RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d\n", __func__
++			, RateSection, Band, RfPath);
++		return 0;
++	}
++
++	if (Band == BAND_ON_2_4G)
++		value = pHalData->target_txpwr_2g[RfPath][RateSection];
++	else if (Band == BAND_ON_5G)
++		value = pHalData->target_txpwr_5g[RfPath][RateSection - 1];
++
++	return value;
++}
++
++static void phy_set_target_txpwr(
++		PADAPTER		Adapter,
++		u8				Band,
++		u8				RfPath,
++		RATE_SECTION	RateSection,
++		u8				Value
++)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++
++	if (RfPath > RF_PATH_D) {
++		RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
++		return;
++	}
++
++	if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
++		RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
++		return;
++	}
++
++	if (RateSection >= RATE_SECTION_NUM
++		|| (Band == BAND_ON_5G && RateSection == CCK)
++	) {
++		RTW_PRINT("%s invalid RateSection:%d in %sG, RfPath:%d\n", __func__
++			, RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath);
++		return;
++	}
++
++	if (Band == BAND_ON_2_4G)
++		pHalData->target_txpwr_2g[RfPath][RateSection] = Value;
++	else /* BAND_ON_5G */
++		pHalData->target_txpwr_5g[RfPath][RateSection - 1] = Value;
++}
++
++static inline BOOLEAN phy_is_txpwr_by_rate_undefined_of_band_path(_adapter *adapter, u8 band, u8 path)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	u8 rate_idx = 0;
++
++	for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++) {
++		if (hal_data->TxPwrByRate[band][path][rate_idx] != hal_spec->txgi_max)
++			goto exit;
++	}
++
++exit:
++	return rate_idx >= TX_PWR_BY_RATE_NUM_RATE ? _TRUE : _FALSE;
++}
++
++static inline void phy_txpwr_by_rate_duplicate_band_path(_adapter *adapter, u8 band, u8 s_path, u8 t_path)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	u8 rate_idx = 0;
++
++	for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++)
++		hal_data->TxPwrByRate[band][t_path][rate_idx] = hal_data->TxPwrByRate[band][s_path][rate_idx];
++}
++
++static void phy_txpwr_by_rate_chk_for_path_dup(_adapter *adapter)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	u8 band, path;
++	s8 src_path;
++
++	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++)
++		for (path = RF_PATH_A; path < RF_PATH_MAX; path++)
++			hal_data->txpwr_by_rate_undefined_band_path[band][path] = 0;
++
++	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
++		if (!hal_is_band_support(adapter, band))
++			continue;
++
++		for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
++			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
++				continue;
++
++			if (phy_is_txpwr_by_rate_undefined_of_band_path(adapter, band, path))
++				hal_data->txpwr_by_rate_undefined_band_path[band][path] = 1;
++		}
++	}
++
++	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
++		if (!hal_is_band_support(adapter, band))
++			continue;
++
++		src_path = -1;
++		for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
++			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
++				continue;
++
++			/* find src */
++			if (src_path == -1 && hal_data->txpwr_by_rate_undefined_band_path[band][path] == 0)
++				src_path = path;
++		}
++
++		if (src_path == -1) {
++			RTW_ERR("%s all power by rate undefined\n", __func__);
++			continue;
++		}
++
++		for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
++			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
++				continue;
++
++			/* duplicate src to undefined one */
++			if (hal_data->txpwr_by_rate_undefined_band_path[band][path] == 1) {
++				RTW_INFO("%s duplicate %s [%c] to [%c]\n", __func__
++					, band_str(band), rf_path_char(src_path), rf_path_char(path));
++				phy_txpwr_by_rate_duplicate_band_path(adapter, band, src_path, path);
++			}
++		}
++	}
++}
++
++void phy_store_target_tx_power(PADAPTER	pAdapter)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);
++	struct registry_priv *regsty = adapter_to_regsty(pAdapter);
++
++	u8 band, path, rs, tx_num, base;
++
++	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
++		if (!hal_is_band_support(pAdapter, band))
++			continue;
++
++		for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
++			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
++				break;
++
++			for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
++				tx_num = rate_section_to_tx_num(rs);
++				if (tx_num + 1 > GET_HAL_TX_NSS(pAdapter))
++					continue;
++
++				if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
++					continue;
++
++				if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
++					continue;
++
++				if (regsty->target_tx_pwr_valid == _TRUE)
++					base = hal_spec->txgi_pdbm * rtw_regsty_get_target_tx_power(pAdapter, band, path, rs);
++				else
++					base = _PHY_GetTxPowerByRate(pAdapter, band, path, rate_sec_base[rs]);
++				phy_set_target_txpwr(pAdapter, band, path, rs, base);
++			}
++		}
++	}
++}
++
++static u8 get_val_from_dhex(u32 dhex, u8 i)
++{
++	return (((dhex >> (i * 8 + 4)) & 0xF)) * 10 + ((dhex >> (i * 8)) & 0xF);
++}
++
++static u8 get_val_from_hex(u32 hex, u8 i)
++{
++	return (hex >> (i * 8)) & 0xFF;
++}
++
++void
++PHY_GetRateValuesOfTxPowerByRate(
++		PADAPTER pAdapter,
++		u32 RegAddr,
++		u32 BitMask,
++		u32 Value,
++		u8 *Rate,
++		s8 *PwrByRateVal,
++		u8 *RateNum
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
++	u8 i = 0;
++	u8 (*get_val)(u32, u8);
++
++	if (pDM_Odm->phy_reg_pg_version == 1)
++		get_val = get_val_from_dhex;
++	else
++		get_val = get_val_from_hex;
++
++	switch (RegAddr) {
++	case rTxAGC_A_Rate18_06:
++	case rTxAGC_B_Rate18_06:
++		Rate[0] = MGN_6M;
++		Rate[1] = MGN_9M;
++		Rate[2] = MGN_12M;
++		Rate[3] = MGN_18M;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case rTxAGC_A_Rate54_24:
++	case rTxAGC_B_Rate54_24:
++		Rate[0] = MGN_24M;
++		Rate[1] = MGN_36M;
++		Rate[2] = MGN_48M;
++		Rate[3] = MGN_54M;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case rTxAGC_A_CCK1_Mcs32:
++		Rate[0] = MGN_1M;
++		PwrByRateVal[0] = (s8)get_val(Value, 1);
++		*RateNum = 1;
++		break;
++
++	case rTxAGC_B_CCK11_A_CCK2_11:
++		if (BitMask == 0xffffff00) {
++			Rate[0] = MGN_2M;
++			Rate[1] = MGN_5_5M;
++			Rate[2] = MGN_11M;
++			for (i = 1; i < 4; ++i)
++				PwrByRateVal[i - 1] = (s8)get_val(Value, i);
++			*RateNum = 3;
++		} else if (BitMask == 0x000000ff) {
++			Rate[0] = MGN_11M;
++			PwrByRateVal[0] = (s8)get_val(Value, 0);
++			*RateNum = 1;
++		}
++		break;
++
++	case rTxAGC_A_Mcs03_Mcs00:
++	case rTxAGC_B_Mcs03_Mcs00:
++		Rate[0] = MGN_MCS0;
++		Rate[1] = MGN_MCS1;
++		Rate[2] = MGN_MCS2;
++		Rate[3] = MGN_MCS3;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case rTxAGC_A_Mcs07_Mcs04:
++	case rTxAGC_B_Mcs07_Mcs04:
++		Rate[0] = MGN_MCS4;
++		Rate[1] = MGN_MCS5;
++		Rate[2] = MGN_MCS6;
++		Rate[3] = MGN_MCS7;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case rTxAGC_A_Mcs11_Mcs08:
++	case rTxAGC_B_Mcs11_Mcs08:
++		Rate[0] = MGN_MCS8;
++		Rate[1] = MGN_MCS9;
++		Rate[2] = MGN_MCS10;
++		Rate[3] = MGN_MCS11;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case rTxAGC_A_Mcs15_Mcs12:
++	case rTxAGC_B_Mcs15_Mcs12:
++		Rate[0] = MGN_MCS12;
++		Rate[1] = MGN_MCS13;
++		Rate[2] = MGN_MCS14;
++		Rate[3] = MGN_MCS15;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case rTxAGC_B_CCK1_55_Mcs32:
++		Rate[0] = MGN_1M;
++		Rate[1] = MGN_2M;
++		Rate[2] = MGN_5_5M;
++		for (i = 1; i < 4; ++i)
++			PwrByRateVal[i - 1] = (s8)get_val(Value, i);
++		*RateNum = 3;
++		break;
++
++	case 0xC20:
++	case 0xE20:
++	case 0x1820:
++	case 0x1a20:
++		Rate[0] = MGN_1M;
++		Rate[1] = MGN_2M;
++		Rate[2] = MGN_5_5M;
++		Rate[3] = MGN_11M;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0xC24:
++	case 0xE24:
++	case 0x1824:
++	case 0x1a24:
++		Rate[0] = MGN_6M;
++		Rate[1] = MGN_9M;
++		Rate[2] = MGN_12M;
++		Rate[3] = MGN_18M;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0xC28:
++	case 0xE28:
++	case 0x1828:
++	case 0x1a28:
++		Rate[0] = MGN_24M;
++		Rate[1] = MGN_36M;
++		Rate[2] = MGN_48M;
++		Rate[3] = MGN_54M;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0xC2C:
++	case 0xE2C:
++	case 0x182C:
++	case 0x1a2C:
++		Rate[0] = MGN_MCS0;
++		Rate[1] = MGN_MCS1;
++		Rate[2] = MGN_MCS2;
++		Rate[3] = MGN_MCS3;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0xC30:
++	case 0xE30:
++	case 0x1830:
++	case 0x1a30:
++		Rate[0] = MGN_MCS4;
++		Rate[1] = MGN_MCS5;
++		Rate[2] = MGN_MCS6;
++		Rate[3] = MGN_MCS7;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0xC34:
++	case 0xE34:
++	case 0x1834:
++	case 0x1a34:
++		Rate[0] = MGN_MCS8;
++		Rate[1] = MGN_MCS9;
++		Rate[2] = MGN_MCS10;
++		Rate[3] = MGN_MCS11;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0xC38:
++	case 0xE38:
++	case 0x1838:
++	case 0x1a38:
++		Rate[0] = MGN_MCS12;
++		Rate[1] = MGN_MCS13;
++		Rate[2] = MGN_MCS14;
++		Rate[3] = MGN_MCS15;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0xC3C:
++	case 0xE3C:
++	case 0x183C:
++	case 0x1a3C:
++		Rate[0] = MGN_VHT1SS_MCS0;
++		Rate[1] = MGN_VHT1SS_MCS1;
++		Rate[2] = MGN_VHT1SS_MCS2;
++		Rate[3] = MGN_VHT1SS_MCS3;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0xC40:
++	case 0xE40:
++	case 0x1840:
++	case 0x1a40:
++		Rate[0] = MGN_VHT1SS_MCS4;
++		Rate[1] = MGN_VHT1SS_MCS5;
++		Rate[2] = MGN_VHT1SS_MCS6;
++		Rate[3] = MGN_VHT1SS_MCS7;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0xC44:
++	case 0xE44:
++	case 0x1844:
++	case 0x1a44:
++		Rate[0] = MGN_VHT1SS_MCS8;
++		Rate[1] = MGN_VHT1SS_MCS9;
++		Rate[2] = MGN_VHT2SS_MCS0;
++		Rate[3] = MGN_VHT2SS_MCS1;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0xC48:
++	case 0xE48:
++	case 0x1848:
++	case 0x1a48:
++		Rate[0] = MGN_VHT2SS_MCS2;
++		Rate[1] = MGN_VHT2SS_MCS3;
++		Rate[2] = MGN_VHT2SS_MCS4;
++		Rate[3] = MGN_VHT2SS_MCS5;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0xC4C:
++	case 0xE4C:
++	case 0x184C:
++	case 0x1a4C:
++		Rate[0] = MGN_VHT2SS_MCS6;
++		Rate[1] = MGN_VHT2SS_MCS7;
++		Rate[2] = MGN_VHT2SS_MCS8;
++		Rate[3] = MGN_VHT2SS_MCS9;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0xCD8:
++	case 0xED8:
++	case 0x18D8:
++	case 0x1aD8:
++		Rate[0] = MGN_MCS16;
++		Rate[1] = MGN_MCS17;
++		Rate[2] = MGN_MCS18;
++		Rate[3] = MGN_MCS19;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0xCDC:
++	case 0xEDC:
++	case 0x18DC:
++	case 0x1aDC:
++		Rate[0] = MGN_MCS20;
++		Rate[1] = MGN_MCS21;
++		Rate[2] = MGN_MCS22;
++		Rate[3] = MGN_MCS23;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0x3a24: /* HT MCS24-27 */
++		Rate[0] = MGN_MCS24;
++		Rate[1] = MGN_MCS25;
++		Rate[2] = MGN_MCS26;
++		Rate[3] = MGN_MCS27;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0x3a28: /* HT MCS28-31 */
++		Rate[0] = MGN_MCS28;
++		Rate[1] = MGN_MCS29;
++		Rate[2] = MGN_MCS30;
++		Rate[3] = MGN_MCS31;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0xCE0:
++	case 0xEE0:
++	case 0x18E0:
++	case 0x1aE0:
++		Rate[0] = MGN_VHT3SS_MCS0;
++		Rate[1] = MGN_VHT3SS_MCS1;
++		Rate[2] = MGN_VHT3SS_MCS2;
++		Rate[3] = MGN_VHT3SS_MCS3;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0xCE4:
++	case 0xEE4:
++	case 0x18E4:
++	case 0x1aE4:
++		Rate[0] = MGN_VHT3SS_MCS4;
++		Rate[1] = MGN_VHT3SS_MCS5;
++		Rate[2] = MGN_VHT3SS_MCS6;
++		Rate[3] = MGN_VHT3SS_MCS7;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0xCE8:
++	case 0xEE8:
++	case 0x18E8:
++	case 0x1aE8:
++	case 0x3a48:
++		Rate[0] = MGN_VHT3SS_MCS8;
++		Rate[1] = MGN_VHT3SS_MCS9;
++		Rate[2] = MGN_VHT4SS_MCS0;
++		Rate[3] = MGN_VHT4SS_MCS1;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0x3a4c:
++		Rate[0] = MGN_VHT4SS_MCS2;
++		Rate[1] = MGN_VHT4SS_MCS3;
++		Rate[2] = MGN_VHT4SS_MCS4;
++		Rate[3] = MGN_VHT4SS_MCS5;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	case 0x3a50:
++		Rate[0] = MGN_VHT4SS_MCS6;
++		Rate[1] = MGN_VHT4SS_MCS7;
++		Rate[2] = MGN_VHT4SS_MCS8;
++		Rate[3] = MGN_VHT4SS_MCS9;
++		for (i = 0; i < 4; ++i)
++			PwrByRateVal[i] = (s8)get_val(Value, i);
++		*RateNum = 4;
++		break;
++
++	default:
++		RTW_PRINT("Invalid RegAddr 0x%x in %s()\n", RegAddr, __func__);
++		break;
++	};
++}
++
++void
++PHY_StoreTxPowerByRateNew(
++		PADAPTER	pAdapter,
++		u32			Band,
++		u32			RfPath,
++		u32			RegAddr,
++		u32			BitMask,
++		u32			Data
++)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++	u8	i = 0, rates[4] = {0}, rateNum = 0;
++	s8	PwrByRateVal[4] = {0};
++
++	PHY_GetRateValuesOfTxPowerByRate(pAdapter, RegAddr, BitMask, Data, rates, PwrByRateVal, &rateNum);
++
++	if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
++		RTW_PRINT("Invalid Band %d\n", Band);
++		return;
++	}
++
++	if (RfPath > RF_PATH_D) {
++		RTW_PRINT("Invalid RfPath %d\n", RfPath);
++		return;
++	}
++
++	for (i = 0; i < rateNum; ++i) {
++		u8 rate_idx = PHY_GetRateIndexOfTxPowerByRate(rates[i]);
++
++		pHalData->TxPwrByRate[Band][RfPath][rate_idx] = PwrByRateVal[i];
++	}
++}
++
++void
++PHY_InitTxPowerByRate(
++		PADAPTER	pAdapter
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);
++	u8	band = 0, rfPath = 0, rate = 0;
++
++	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band)
++		for (rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath)
++				for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate)
++					pHalData->TxPwrByRate[band][rfPath][rate] = hal_spec->txgi_max;
++}
++
++void
++phy_store_tx_power_by_rate(
++		PADAPTER	pAdapter,
++		u32			Band,
++		u32			RfPath,
++		u32			TxNum,
++		u32			RegAddr,
++		u32			BitMask,
++		u32			Data
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
++
++	if (pDM_Odm->phy_reg_pg_version > 0)
++		PHY_StoreTxPowerByRateNew(pAdapter, Band, RfPath, RegAddr, BitMask, Data);
++	else
++		RTW_INFO("Invalid PHY_REG_PG.txt version %d\n",  pDM_Odm->phy_reg_pg_version);
++
++}
++
++/*
++  * This function must be called if the value in the PHY_REG_PG.txt(or header)
++  * is exact dBm values
++  */
++void
++PHY_TxPowerByRateConfiguration(
++		PADAPTER			pAdapter
++)
++{
++	phy_txpwr_by_rate_chk_for_path_dup(pAdapter);
++	phy_store_target_tx_power(pAdapter);
++}
++
++#ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
++extern bool phy_set_txpwr_idx_offload(_adapter *adapter);
++#endif
++
++void
++phy_set_tx_power_index_by_rate_section(
++		PADAPTER		pAdapter,
++		enum rf_path		RFPath,
++		u8				Channel,
++		u8				rs
++)
++{
++	PHAL_DATA_TYPE	hal_data = GET_HAL_DATA(pAdapter);
++	u8 band = hal_data->current_band_type;
++	u8 bw = hal_data->current_channel_bw;
++	u32	powerIndex = 0;
++	int	i = 0;
++
++	if (rs >= RATE_SECTION_NUM) {
++		RTW_INFO("Invalid RateSection %d in %s", rs, __func__);
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (rs == CCK && bw != BAND_ON_2_4G)
++		goto exit;
++
++	for (i = 0; i < rates_by_sections[rs].rate_num; ++i) {
++#if DBG_TX_POWER_IDX
++		struct txpwr_idx_comp tic;
++
++		powerIndex = rtw_hal_get_tx_power_index(pAdapter, RFPath
++			, rs, rates_by_sections[rs].rates[i], bw, band, Channel, 0, &tic);
++		dump_tx_power_index_inline(RTW_DBGDUMP, pAdapter, RFPath, bw, Channel
++			, rates_by_sections[rs].rates[i], powerIndex, &tic);
++#else
++		powerIndex = phy_get_tx_power_index_ex(pAdapter, RFPath
++			, rs, rates_by_sections[rs].rates[i], bw, band, Channel, 0);
++#endif
++		PHY_SetTxPowerIndex(pAdapter, powerIndex, RFPath, rates_by_sections[rs].rates[i]);
++	}
++
++#ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
++	if (!hal_data->set_entire_txpwr
++		&& phy_set_txpwr_idx_offload(pAdapter))
++		rtw_hal_set_txpwr_done(pAdapter);
++#endif
++
++exit:
++	return;
++}
++
++bool phy_get_ch_idx(u8 ch, u8 *ch_idx)
++{
++	u8  i = 0;
++	BOOLEAN bIn24G = _TRUE;
++
++	if (ch > 0 && ch <= 14) {
++		bIn24G = _TRUE;
++		*ch_idx = ch - 1;
++	} else {
++		bIn24G = _FALSE;
++
++		for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) {
++			if (center_ch_5g_all[i] == ch) {
++				*ch_idx = i;
++				break;
++			}
++		}
++	}
++
++	return bIn24G;
++}
++
++bool phy_chk_ch_setting_consistency(_adapter *adapter, u8 ch)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	u8 ch_idx = 0xFF;
++	u8 ret = _FAIL;
++
++	phy_get_ch_idx(ch, &ch_idx);
++	if (ch_idx == 0xFF) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (ch != hal_data->current_channel) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (ch <= 14) {
++		if (hal_data->current_band_type != BAND_ON_2_4G) {
++			rtw_warn_on(1);
++			goto exit;
++		}
++		if (hal_data->current_channel_bw > CHANNEL_WIDTH_40) {
++			rtw_warn_on(1);
++			goto exit;
++		}
++	}
++	if (ch > 14) {
++		if (hal_data->current_band_type != BAND_ON_5G) {
++			rtw_warn_on(1);
++			goto exit;
++		}
++		if (hal_data->current_channel_bw > CHANNEL_WIDTH_160) {
++			rtw_warn_on(1);
++			goto exit;
++		}
++	}
++
++	ret = _SUCCESS;
++
++exit:
++	if (ret != _SUCCESS)
++		RTW_WARN("ch:%u, hal band:%u, ch:%u, bw:%u\n", ch
++			, hal_data->current_band_type, hal_data->current_channel, hal_data->current_channel_bw);
++
++	return ret;
++}
++
++#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
++u8 phy_get_pg_txpwr_idx(_adapter *pAdapter
++	, enum rf_path RFPath, RATE_SECTION rs, u8 ntx_idx
++	, enum channel_width BandWidth, u8 band, u8 Channel)
++{
++	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(pAdapter);
++	u8					i;
++	u8					txPower = 0;
++	u8					chnlIdx = (Channel - 1);
++
++	if (HAL_IsLegalChannel(pAdapter, Channel) == _FALSE) {
++		chnlIdx = 0;
++		RTW_INFO("Illegal channel!!\n");
++	}
++
++	phy_get_ch_idx(Channel, &chnlIdx);
++
++	if (0)
++		RTW_INFO("[%s] Channel Index: %d\n", band_str(band), chnlIdx);
++
++	if (band == BAND_ON_2_4G) {
++		if (IS_CCK_RATE_SECTION(rs)) {
++			/* CCK-nTX */
++			txPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx];
++			txPower += pHalData->CCK_24G_Diff[RFPath][RF_1TX];
++			if (ntx_idx >= RF_2TX)
++				txPower += pHalData->CCK_24G_Diff[RFPath][RF_2TX];
++			if (ntx_idx >= RF_3TX)
++				txPower += pHalData->CCK_24G_Diff[RFPath][RF_3TX];
++			if (ntx_idx >= RF_4TX)
++				txPower += pHalData->CCK_24G_Diff[RFPath][RF_4TX];
++			goto exit;
++		}
++
++		txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx];
++
++		/* OFDM-nTX */
++		if (IS_OFDM_RATE_SECTION(rs)) {
++			txPower += pHalData->OFDM_24G_Diff[RFPath][RF_1TX];
++			if (ntx_idx >= RF_2TX)
++				txPower += pHalData->OFDM_24G_Diff[RFPath][RF_2TX];
++			if (ntx_idx >= RF_3TX)
++				txPower += pHalData->OFDM_24G_Diff[RFPath][RF_3TX];
++			if (ntx_idx >= RF_4TX)
++				txPower += pHalData->OFDM_24G_Diff[RFPath][RF_4TX];
++			goto exit;
++		}
++
++		/* BW20-nS */
++		if (BandWidth == CHANNEL_WIDTH_20) {
++			txPower += pHalData->BW20_24G_Diff[RFPath][RF_1TX];
++			if (rate_section_to_tx_num(rs) >= RF_2TX)
++				txPower += pHalData->BW20_24G_Diff[RFPath][RF_2TX];
++			if (rate_section_to_tx_num(rs) >= RF_3TX)
++				txPower += pHalData->BW20_24G_Diff[RFPath][RF_3TX];
++			if (rate_section_to_tx_num(rs) >= RF_4TX)
++				txPower += pHalData->BW20_24G_Diff[RFPath][RF_4TX];
++			goto exit;
++		}
++
++		/* BW40-nS */
++		if (BandWidth == CHANNEL_WIDTH_40
++			/* Willis suggest adopt BW 40M power index while in BW 80 mode */
++			|| BandWidth == CHANNEL_WIDTH_80
++		) {
++			txPower += pHalData->BW40_24G_Diff[RFPath][RF_1TX];
++			if (rate_section_to_tx_num(rs) >= RF_2TX)
++				txPower += pHalData->BW40_24G_Diff[RFPath][RF_2TX];
++			if (rate_section_to_tx_num(rs) >= RF_3TX)
++				txPower += pHalData->BW40_24G_Diff[RFPath][RF_3TX];
++			if (rate_section_to_tx_num(rs) >= RF_4TX)
++				txPower += pHalData->BW40_24G_Diff[RFPath][RF_4TX];
++			goto exit;
++		}
++	}
++#if CONFIG_IEEE80211_BAND_5GHZ
++	else if (band == BAND_ON_5G) {
++		if (IS_CCK_RATE_SECTION(rs)) {
++			RTW_WARN("===>%s: INVALID, CCK on 5G\n", __func__);
++			goto exit;
++		}
++
++		txPower = pHalData->Index5G_BW40_Base[RFPath][chnlIdx];
++
++		/* OFDM-nTX */
++		if (IS_OFDM_RATE_SECTION(rs)) {
++			txPower += pHalData->OFDM_5G_Diff[RFPath][RF_1TX];
++			if (ntx_idx >= RF_2TX)
++				txPower += pHalData->OFDM_5G_Diff[RFPath][RF_2TX];
++			if (ntx_idx >= RF_3TX)
++				txPower += pHalData->OFDM_5G_Diff[RFPath][RF_3TX];
++			if (ntx_idx >= RF_4TX)
++				txPower += pHalData->OFDM_5G_Diff[RFPath][RF_4TX];
++			goto exit;
++		}
++
++		/* BW20-nS */
++		if (BandWidth == CHANNEL_WIDTH_20) {
++			txPower += pHalData->BW20_5G_Diff[RFPath][RF_1TX];
++			if (rate_section_to_tx_num(rs) >= RF_2TX)
++				txPower += pHalData->BW20_5G_Diff[RFPath][RF_2TX];
++			if (rate_section_to_tx_num(rs) >= RF_3TX)
++				txPower += pHalData->BW20_5G_Diff[RFPath][RF_3TX];
++			if (rate_section_to_tx_num(rs) >= RF_4TX)
++				txPower += pHalData->BW20_5G_Diff[RFPath][RF_4TX];
++			goto exit;
++		}
++
++		/* BW40-nS */
++		if (BandWidth == CHANNEL_WIDTH_40) {
++			txPower += pHalData->BW40_5G_Diff[RFPath][RF_1TX];
++			if (rate_section_to_tx_num(rs) >= RF_2TX)
++				txPower += pHalData->BW40_5G_Diff[RFPath][RF_2TX];
++			if (rate_section_to_tx_num(rs) >= RF_3TX)
++				txPower += pHalData->BW40_5G_Diff[RFPath][RF_3TX];
++			if (rate_section_to_tx_num(rs) >= RF_4TX)
++				txPower += pHalData->BW40_5G_Diff[RFPath][RF_4TX];
++			goto exit;
++		}
++
++		/* BW80-nS */
++		if (BandWidth == CHANNEL_WIDTH_80) {
++			/* get 80MHz cch index */
++			for (i = 0; i < CENTER_CH_5G_80M_NUM; ++i) {
++				if (center_ch_5g_80m[i] == Channel) {
++					chnlIdx = i;
++					break;
++				}
++			}
++			if (i >= CENTER_CH_5G_80M_NUM) {
++			#ifdef CONFIG_MP_INCLUDED
++				if (rtw_mp_mode_check(pAdapter) == _FALSE)
++			#endif
++					rtw_warn_on(1);
++				txPower = 0;
++				goto exit;
++			}
++
++			txPower = pHalData->Index5G_BW80_Base[RFPath][chnlIdx];
++
++			txPower += + pHalData->BW80_5G_Diff[RFPath][RF_1TX];
++			if (rate_section_to_tx_num(rs) >= RF_2TX)
++				txPower += pHalData->BW80_5G_Diff[RFPath][RF_2TX];
++			if (rate_section_to_tx_num(rs) >= RF_3TX)
++				txPower += pHalData->BW80_5G_Diff[RFPath][RF_3TX];
++			if (rate_section_to_tx_num(rs) >= RF_4TX)
++				txPower += pHalData->BW80_5G_Diff[RFPath][RF_4TX];
++			goto exit;
++		}
++
++		/* TODO: BW160-nS */
++		rtw_warn_on(1);
++	}
++#endif /* CONFIG_IEEE80211_BAND_5GHZ */
++
++exit:
++	return txPower;
++}
++#endif /* CONFIG_TXPWR_PG_WITH_PWR_IDX */
++
++s8
++PHY_GetTxPowerTrackingOffset(
++	PADAPTER	pAdapter,
++	enum rf_path	RFPath,
++	u8			Rate
++)
++{
++	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(pAdapter);
++	struct dm_struct			*pDM_Odm = &pHalData->odmpriv;
++	s8	offset = 0;
++
++	if (pDM_Odm->rf_calibrate_info.txpowertrack_control  == _FALSE)
++		return offset;
++
++	if ((Rate == MGN_1M) || (Rate == MGN_2M) || (Rate == MGN_5_5M) || (Rate == MGN_11M)) {
++		offset = pDM_Odm->rf_calibrate_info.remnant_cck_swing_idx;
++		/*RTW_INFO("+Remnant_CCKSwingIdx = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_CCKSwingIdx);*/
++	} else {
++		offset = pDM_Odm->rf_calibrate_info.remnant_ofdm_swing_idx[RFPath];
++		/*RTW_INFO("+Remanant_OFDMSwingIdx[RFPath %u][Rate 0x%x] = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]);	*/
++
++	}
++
++	return offset;
++}
++
++/*The same as MRateToHwRate in hal_com.c*/
++u8
++PHY_GetRateIndexOfTxPowerByRate(
++		u8		Rate
++)
++{
++	u8	index = 0;
++	switch (Rate) {
++	case MGN_1M:
++		index = 0;
++		break;
++	case MGN_2M:
++		index = 1;
++		break;
++	case MGN_5_5M:
++		index = 2;
++		break;
++	case MGN_11M:
++		index = 3;
++		break;
++	case MGN_6M:
++		index = 4;
++		break;
++	case MGN_9M:
++		index = 5;
++		break;
++	case MGN_12M:
++		index = 6;
++		break;
++	case MGN_18M:
++		index = 7;
++		break;
++	case MGN_24M:
++		index = 8;
++		break;
++	case MGN_36M:
++		index = 9;
++		break;
++	case MGN_48M:
++		index = 10;
++		break;
++	case MGN_54M:
++		index = 11;
++		break;
++	case MGN_MCS0:
++		index = 12;
++		break;
++	case MGN_MCS1:
++		index = 13;
++		break;
++	case MGN_MCS2:
++		index = 14;
++		break;
++	case MGN_MCS3:
++		index = 15;
++		break;
++	case MGN_MCS4:
++		index = 16;
++		break;
++	case MGN_MCS5:
++		index = 17;
++		break;
++	case MGN_MCS6:
++		index = 18;
++		break;
++	case MGN_MCS7:
++		index = 19;
++		break;
++	case MGN_MCS8:
++		index = 20;
++		break;
++	case MGN_MCS9:
++		index = 21;
++		break;
++	case MGN_MCS10:
++		index = 22;
++		break;
++	case MGN_MCS11:
++		index = 23;
++		break;
++	case MGN_MCS12:
++		index = 24;
++		break;
++	case MGN_MCS13:
++		index = 25;
++		break;
++	case MGN_MCS14:
++		index = 26;
++		break;
++	case MGN_MCS15:
++		index = 27;
++		break;
++	case MGN_MCS16:
++		index = 28;
++		break;
++	case MGN_MCS17:
++		index = 29;
++		break;
++	case MGN_MCS18:
++		index = 30;
++		break;
++	case MGN_MCS19:
++		index = 31;
++		break;
++	case MGN_MCS20:
++		index = 32;
++		break;
++	case MGN_MCS21:
++		index = 33;
++		break;
++	case MGN_MCS22:
++		index = 34;
++		break;
++	case MGN_MCS23:
++		index = 35;
++		break;
++	case MGN_MCS24:
++		index = 36;
++		break;
++	case MGN_MCS25:
++		index = 37;
++		break;
++	case MGN_MCS26:
++		index = 38;
++		break;
++	case MGN_MCS27:
++		index = 39;
++		break;
++	case MGN_MCS28:
++		index = 40;
++		break;
++	case MGN_MCS29:
++		index = 41;
++		break;
++	case MGN_MCS30:
++		index = 42;
++		break;
++	case MGN_MCS31:
++		index = 43;
++		break;
++	case MGN_VHT1SS_MCS0:
++		index = 44;
++		break;
++	case MGN_VHT1SS_MCS1:
++		index = 45;
++		break;
++	case MGN_VHT1SS_MCS2:
++		index = 46;
++		break;
++	case MGN_VHT1SS_MCS3:
++		index = 47;
++		break;
++	case MGN_VHT1SS_MCS4:
++		index = 48;
++		break;
++	case MGN_VHT1SS_MCS5:
++		index = 49;
++		break;
++	case MGN_VHT1SS_MCS6:
++		index = 50;
++		break;
++	case MGN_VHT1SS_MCS7:
++		index = 51;
++		break;
++	case MGN_VHT1SS_MCS8:
++		index = 52;
++		break;
++	case MGN_VHT1SS_MCS9:
++		index = 53;
++		break;
++	case MGN_VHT2SS_MCS0:
++		index = 54;
++		break;
++	case MGN_VHT2SS_MCS1:
++		index = 55;
++		break;
++	case MGN_VHT2SS_MCS2:
++		index = 56;
++		break;
++	case MGN_VHT2SS_MCS3:
++		index = 57;
++		break;
++	case MGN_VHT2SS_MCS4:
++		index = 58;
++		break;
++	case MGN_VHT2SS_MCS5:
++		index = 59;
++		break;
++	case MGN_VHT2SS_MCS6:
++		index = 60;
++		break;
++	case MGN_VHT2SS_MCS7:
++		index = 61;
++		break;
++	case MGN_VHT2SS_MCS8:
++		index = 62;
++		break;
++	case MGN_VHT2SS_MCS9:
++		index = 63;
++		break;
++	case MGN_VHT3SS_MCS0:
++		index = 64;
++		break;
++	case MGN_VHT3SS_MCS1:
++		index = 65;
++		break;
++	case MGN_VHT3SS_MCS2:
++		index = 66;
++		break;
++	case MGN_VHT3SS_MCS3:
++		index = 67;
++		break;
++	case MGN_VHT3SS_MCS4:
++		index = 68;
++		break;
++	case MGN_VHT3SS_MCS5:
++		index = 69;
++		break;
++	case MGN_VHT3SS_MCS6:
++		index = 70;
++		break;
++	case MGN_VHT3SS_MCS7:
++		index = 71;
++		break;
++	case MGN_VHT3SS_MCS8:
++		index = 72;
++		break;
++	case MGN_VHT3SS_MCS9:
++		index = 73;
++		break;
++	case MGN_VHT4SS_MCS0:
++		index = 74;
++		break;
++	case MGN_VHT4SS_MCS1:
++		index = 75;
++		break;
++	case MGN_VHT4SS_MCS2:
++		index = 76;
++		break;
++	case MGN_VHT4SS_MCS3:
++		index = 77;
++		break;
++	case MGN_VHT4SS_MCS4:
++		index = 78;
++		break;
++	case MGN_VHT4SS_MCS5:
++		index = 79;
++		break;
++	case MGN_VHT4SS_MCS6:
++		index = 80;
++		break;
++	case MGN_VHT4SS_MCS7:
++		index = 81;
++		break;
++	case MGN_VHT4SS_MCS8:
++		index = 82;
++		break;
++	case MGN_VHT4SS_MCS9:
++		index = 83;
++		break;
++	default:
++		RTW_INFO("Invalid rate 0x%x in %s\n", Rate, __FUNCTION__);
++		break;
++	};
++
++	return index;
++}
++
++s8
++_PHY_GetTxPowerByRate(
++		PADAPTER	pAdapter,
++		u8			Band,
++		enum rf_path	RFPath,
++		u8			Rate
++)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++	s8 value = 0;
++	u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
++
++	if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
++		RTW_INFO("Invalid band %d in %s\n", Band, __func__);
++		goto exit;
++	}
++	if (RFPath > RF_PATH_D) {
++		RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __func__);
++		goto exit;
++	}
++	if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) {
++		RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __func__);
++		goto exit;
++	}
++
++	value = pHalData->TxPwrByRate[Band][RFPath][rateIndex];
++
++exit:
++	return value;
++}
++
++
++s8
++PHY_GetTxPowerByRate(
++		PADAPTER	pAdapter,
++		u8			Band,
++		enum rf_path	RFPath,
++		RATE_SECTION rs,
++		enum MGN_RATE rate
++)
++{
++	if (phy_is_tx_power_by_rate_needed(pAdapter))
++		return _PHY_GetTxPowerByRate(pAdapter, Band, RFPath, rate);
++	return phy_get_target_txpwr(pAdapter, Band, RFPath, rs);
++}
++
++void
++PHY_SetTxPowerByRate(
++		PADAPTER	pAdapter,
++		u8			Band,
++		enum rf_path	RFPath,
++		u8			Rate,
++		s8			Value
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++	u8	rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
++
++	if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
++		RTW_INFO("Invalid band %d in %s\n", Band, __FUNCTION__);
++		return;
++	}
++	if (RFPath > RF_PATH_D) {
++		RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __FUNCTION__);
++		return;
++	}
++	if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) {
++		RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __FUNCTION__);
++		return;
++	}
++
++	pHalData->TxPwrByRate[Band][RFPath][rateIndex] = Value;
++}
++
++u8 phy_check_under_survey_ch(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	_adapter *iface;
++	struct mlme_ext_priv *mlmeext;
++	u8 ret = _FALSE;
++	int i;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (!iface)
++			continue;
++		mlmeext = &iface->mlmeextpriv;
++
++		/* check scan state */
++		if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE
++			&& mlmeext_scan_state(mlmeext) != SCAN_COMPLETE
++				&& mlmeext_scan_state(mlmeext) != SCAN_BACKING_OP) {
++			ret = _TRUE;
++		} else if (mlmeext_scan_state(mlmeext) == SCAN_BACKING_OP
++			&& !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME)) {
++			ret = _TRUE;
++		}
++	}
++
++	return ret;
++}
++
++void
++phy_set_tx_power_level_by_path(
++		PADAPTER	Adapter,
++		u8			channel,
++		u8			path
++)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
++	BOOLEAN bIsIn24G = (pHalData->current_band_type == BAND_ON_2_4G);
++	u8 under_survey_ch = phy_check_under_survey_ch(Adapter);
++
++
++	/* if ( pMgntInfo->RegNByteAccess == 0 ) */
++	{
++		if (bIsIn24G)
++			phy_set_tx_power_index_by_rate_section(Adapter, path, channel, CCK);
++
++		phy_set_tx_power_index_by_rate_section(Adapter, path, channel, OFDM);
++
++		if (!under_survey_ch) {
++			phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS0_MCS7);
++
++			if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))
++				phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_1SSMCS0_1SSMCS9);
++
++			if (pHalData->tx_nss >= 2) {
++				phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS8_MCS15);
++
++				if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))
++					phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_2SSMCS0_2SSMCS9);
++
++				if (IS_HARDWARE_TYPE_8814A(Adapter)) {
++					phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS16_MCS23);
++					phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_3SSMCS0_3SSMCS9);
++				}
++			}
++		}
++	}
++}
++
++#if CONFIG_TXPWR_LIMIT
++const char *const _txpwr_lmt_rs_str[] = {
++	"CCK",
++	"OFDM",
++	"HT",
++	"VHT",
++	"UNKNOWN",
++};
++
++static s8
++phy_GetChannelIndexOfTxPowerLimit(
++		u8			Band,
++		u8			Channel
++)
++{
++	s8	channelIndex = -1;
++	u8	i = 0;
++
++	if (Band == BAND_ON_2_4G)
++		channelIndex = Channel - 1;
++	else if (Band == BAND_ON_5G) {
++		for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) {
++			if (center_ch_5g_all[i] == Channel)
++				channelIndex = i;
++		}
++	} else
++		RTW_PRINT("Invalid Band %d in %s\n", Band, __func__);
++
++	if (channelIndex == -1)
++		RTW_PRINT("Invalid Channel %d of Band %d in %s\n", Channel, Band, __func__);
++
++	return channelIndex;
++}
++
++static s8 phy_txpwr_ww_lmt_value(_adapter *adapter)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++
++	if (hal_spec->txgi_max == 63)
++		return -63;
++	else if (hal_spec->txgi_max == 127)
++		return -128;
++
++	rtw_warn_on(1);
++	return -128;
++}
++
++/*
++* return txpwr limit in unit of TX Gain Index
++* hsl_spec->txgi_max is returned when NO limit
++*/
++s8 phy_get_txpwr_lmt(
++		PADAPTER			Adapter,
++		const char			*regd_name,
++		BAND_TYPE			Band,
++		enum channel_width		bw,
++	u8 tlrs,
++	u8 ntx_idx,
++	u8 cch,
++	u8 lock
++)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(Adapter);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(Adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
++	struct txpwr_lmt_ent *ent = NULL;
++	_irqL irqL;
++	_list *cur, *head;
++	s8 ch_idx;
++	u8 is_ww_regd = 0;
++	s8 ww_lmt_val = phy_txpwr_ww_lmt_value(Adapter);
++	s8 lmt = hal_spec->txgi_max;
++
++	if ((Adapter->registrypriv.RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory != 1) ||
++		Adapter->registrypriv.RegEnableTxPowerLimit == 0)
++		goto exit;
++
++	if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
++		RTW_ERR("%s invalid band:%u\n", __func__, Band);
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (Band == BAND_ON_5G  && tlrs == TXPWR_LMT_RS_CCK) {
++		RTW_ERR("5G has no CCK\n");
++		goto exit;
++	}
++
++	if (lock)
++		_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++
++	if (!regd_name) /* no regd_name specified, use currnet */
++		regd_name = rfctl->regd_name;
++
++	if (rfctl->txpwr_regd_num == 0
++		|| strcmp(regd_name, regd_str(TXPWR_LMT_NONE)) == 0)
++		goto release_lock;
++
++	if (strcmp(regd_name, regd_str(TXPWR_LMT_WW)) == 0)
++		is_ww_regd = 1;
++
++	if (!is_ww_regd) {
++		ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name);
++		if (!ent)
++			goto release_lock;
++	}
++
++	ch_idx = phy_GetChannelIndexOfTxPowerLimit(Band, cch);
++	if (ch_idx == -1)
++		goto release_lock;
++
++	if (Band == BAND_ON_2_4G) {
++		if (!is_ww_regd) {
++			lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx];
++			if (lmt != ww_lmt_val)
++				goto release_lock;
++		}
++
++		/* search for min value for WW regd or WW limit */
++		lmt = hal_spec->txgi_max;
++		head = &rfctl->txpwr_lmt_list;
++		cur = get_next(head);
++		while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
++			ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
++			cur = get_next(cur);
++			if (ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] != ww_lmt_val)
++				lmt = rtw_min(lmt, ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx]);
++		}
++	}
++	#if CONFIG_IEEE80211_BAND_5GHZ
++	else if (Band == BAND_ON_5G) {
++		if (!is_ww_regd) {
++			lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx];
++			if (lmt != ww_lmt_val)
++				goto release_lock;
++		}
++
++		/* search for min value for WW regd or WW limit */
++		lmt = hal_spec->txgi_max;
++		head = &rfctl->txpwr_lmt_list;
++		cur = get_next(head);
++		while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
++			ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
++			cur = get_next(cur);
++			if (ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] != ww_lmt_val)
++				lmt = rtw_min(lmt, ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx]);
++		}
++	}
++	#endif
++
++release_lock:
++	if (lock)
++		_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++
++exit:
++	return lmt;
++}
++
++/*
++* return txpwr limit diff value to target of its rate section in unit of TX Gain Index
++* hal_spec->txgi_max is returned when NO limit
++*/
++inline s8 phy_get_txpwr_lmt_diff(_adapter *adapter
++	, const char *regd_name
++	, BAND_TYPE band, enum channel_width bw
++	, u8 rfpath, u8 rs, u8 tlrs, u8 ntx_idx, u8 cch, u8 lock
++)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	s8 lmt = phy_get_txpwr_lmt(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock);
++
++	if (lmt != hal_spec->txgi_max) {
++		/* return diff value */
++		lmt = lmt - phy_get_target_txpwr(adapter, band, rfpath, rs);
++	}
++
++	return lmt;
++}
++
++/*
++* May search for secondary channels for min limit
++* @opch: used to specify operating channel position to get
++* cch of every bandwidths which differ from current hal_data.cch20, 40, 80...
++*
++* return txpwr limit in unit of TX Gain Index
++* hsl_spec->txgi_max is returned when NO limit
++*/
++s8 phy_get_txpwr_lmt_sub_chs(_adapter *adapter
++	, const char *regd_name
++	, BAND_TYPE band, enum channel_width bw
++	, u8 rfpath, u8 rate, u8 ntx_idx, u8 cch, u8 opch)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	BOOLEAN no_sc = _FALSE;
++	u8 cch_20 = hal_data->cch_20, cch_40 = hal_data->cch_40, cch_80 = hal_data->cch_80;
++	s8 tlrs = -1;
++	s8 lmt = hal_spec->txgi_max;
++	u8 tmp_cch = 0;
++	u8 tmp_bw;
++	u8 bw_bmp = 0;
++	s8 min_lmt = hal_spec->txgi_max;
++	u8 final_bw = bw, final_cch = cch;
++	_irqL irqL;
++
++#ifdef CONFIG_MP_INCLUDED
++	/* MP mode channel don't use secondary channel */
++	if (rtw_mp_mode_check(adapter) == _TRUE)
++		no_sc = _TRUE;
++#endif
++	if (IS_CCK_RATE(rate))
++		tlrs = TXPWR_LMT_RS_CCK;
++	else if (IS_OFDM_RATE(rate))
++		tlrs = TXPWR_LMT_RS_OFDM;
++	else if (IS_HT_RATE(rate))
++		tlrs = TXPWR_LMT_RS_HT;
++	else if (IS_VHT_RATE(rate))
++		tlrs = TXPWR_LMT_RS_VHT;
++	else {
++		RTW_ERR("%s invalid rate 0x%x\n", __func__, rate);
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (no_sc == _TRUE) {
++		/* use the input center channel and bandwidth directly */
++		tmp_cch = cch;
++		bw_bmp = ch_width_to_bw_cap(bw);
++	} else {
++		/* decide center channel of each bandwidth */
++		if (opch != 0) {
++			cch_80 = bw == CHANNEL_WIDTH_80 ? cch : 0;
++			cch_40 = bw == CHANNEL_WIDTH_40 ? cch : 0;
++			cch_20 = bw == CHANNEL_WIDTH_20 ? cch : 0;
++			if (cch_80 != 0)
++				cch_40 = rtw_get_scch_by_cch_opch(cch_80, CHANNEL_WIDTH_80, opch);
++			if (cch_40 != 0)
++				cch_20 = rtw_get_scch_by_cch_opch(cch_40, CHANNEL_WIDTH_40, opch);
++		}
++
++		/*
++		* find the possible tx bandwidth bmp for this rate, and then will get center channel for each bandwidth
++		* if no possible tx bandwidth bmp, select valid bandwidth up to current RF bandwidth into bmp
++		*/
++		if (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM)
++			bw_bmp = BW_CAP_20M; /* CCK, OFDM only BW 20M */
++		else if (tlrs == TXPWR_LMT_RS_HT) {
++			bw_bmp = rtw_get_tx_bw_bmp_of_ht_rate(dvobj, rate, bw);
++			if (bw_bmp == 0)
++				bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_40 ? CHANNEL_WIDTH_40 : bw);
++		} else if (tlrs == TXPWR_LMT_RS_VHT) {
++			bw_bmp = rtw_get_tx_bw_bmp_of_vht_rate(dvobj, rate, bw);
++			if (bw_bmp == 0)
++				bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_160 ? CHANNEL_WIDTH_160 : bw);
++		} else
++			rtw_warn_on(1);
++	}
++
++	if (bw_bmp == 0)
++		goto exit;
++
++	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++
++	/* loop for each possible tx bandwidth to find minimum limit */
++	for (tmp_bw = CHANNEL_WIDTH_20; tmp_bw <= bw; tmp_bw++) {
++		if (!(ch_width_to_bw_cap(tmp_bw) & bw_bmp))
++			continue;
++
++		if (no_sc == _FALSE) {
++			if (tmp_bw == CHANNEL_WIDTH_20)
++				tmp_cch = cch_20;
++			else if (tmp_bw == CHANNEL_WIDTH_40)
++				tmp_cch = cch_40;
++			else if (tmp_bw == CHANNEL_WIDTH_80)
++				tmp_cch = cch_80;
++			else {
++				tmp_cch = 0;
++				rtw_warn_on(1);
++			}
++		}
++
++		lmt = phy_get_txpwr_lmt(adapter, regd_name, band, tmp_bw, tlrs, ntx_idx, tmp_cch, 0);
++
++		if (min_lmt >= lmt) {
++			min_lmt = lmt;
++			final_cch = tmp_cch;
++			final_bw = tmp_bw;
++		}
++
++	}
++
++	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++
++exit:
++
++	if (0) {
++		if (final_bw != bw && (IS_HT_RATE(rate) || IS_VHT_RATE(rate)))
++			RTW_INFO("%s min_lmt: %s ch%u -> %s ch%u\n"
++				, MGN_RATE_STR(rate)
++				, ch_width_str(bw), cch
++				, ch_width_str(final_bw), final_cch);
++	}
++
++	return min_lmt;
++}
++
++static void phy_txpwr_lmt_cck_ofdm_mt_chk(_adapter *adapter)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	struct txpwr_lmt_ent *ent;
++	_list *cur, *head;
++	u8 channel, tlrs, ntx_idx;
++
++	rfctl->txpwr_lmt_2g_cck_ofdm_state = 0;
++#if CONFIG_IEEE80211_BAND_5GHZ
++	rfctl->txpwr_lmt_5g_cck_ofdm_state = 0;
++#endif
++
++	head = &rfctl->txpwr_lmt_list;
++	cur = get_next(head);
++
++	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
++		ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
++		cur = get_next(cur);
++
++		/* check 2G CCK, OFDM state*/
++		for (tlrs = TXPWR_LMT_RS_CCK; tlrs <= TXPWR_LMT_RS_OFDM; tlrs++) {
++			for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
++				for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) {
++					if (ent->lmt_2g[CHANNEL_WIDTH_20][tlrs][channel][ntx_idx] != hal_spec->txgi_max) {
++						if (tlrs == TXPWR_LMT_RS_CCK)
++							rfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_CCK_1T << ntx_idx;
++						else
++							rfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx;
++						break;
++					}
++				}
++			}
++		}
++
++		/* if 2G OFDM multi-TX is not defined, reference HT20 */
++		for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) {
++			for (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
++				if (rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))
++					continue;
++				ent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM][channel][ntx_idx] =
++					ent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT][channel][ntx_idx];
++			}
++		}
++
++#if CONFIG_IEEE80211_BAND_5GHZ
++		/* check 5G OFDM state*/
++		for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
++			for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
++				if (ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] != hal_spec->txgi_max) {
++					rfctl->txpwr_lmt_5g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx;
++					break;
++				}
++			}
++		}
++
++		for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
++			for (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
++				if (rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))
++					continue;
++				/* if 5G OFDM multi-TX is not defined, reference HT20 */
++				ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] =
++					ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT - 1][channel][ntx_idx];
++			}
++		}
++#endif /* CONFIG_IEEE80211_BAND_5GHZ */
++	}
++}
++
++#if CONFIG_IEEE80211_BAND_5GHZ
++static void phy_txpwr_lmt_cross_ref_ht_vht(_adapter *adapter)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	struct txpwr_lmt_ent *ent;
++	_list *cur, *head;
++	u8 bw, channel, tlrs, ref_tlrs, ntx_idx;
++	int ht_ref_vht_5g_20_40 = 0;
++	int vht_ref_ht_5g_20_40 = 0;
++	int ht_has_ref_5g_20_40 = 0;
++	int vht_has_ref_5g_20_40 = 0;
++
++	rfctl->txpwr_lmt_5g_20_40_ref = 0;
++
++	head = &rfctl->txpwr_lmt_list;
++	cur = get_next(head);
++
++	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
++		ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
++		cur = get_next(cur);
++
++		for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {
++
++			for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
++
++				for (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; ++tlrs) {
++
++					/* 5G 20M 40M VHT and HT can cross reference */
++					if (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40) {
++						if (tlrs == TXPWR_LMT_RS_HT)
++							ref_tlrs = TXPWR_LMT_RS_VHT;
++						else if (tlrs == TXPWR_LMT_RS_VHT)
++							ref_tlrs = TXPWR_LMT_RS_HT;
++						else
++							continue;
++
++						for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
++
++							if (ent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx] == hal_spec->txgi_max)
++								continue;
++
++							if (tlrs == TXPWR_LMT_RS_HT)
++								ht_has_ref_5g_20_40++;
++							else if (tlrs == TXPWR_LMT_RS_VHT)
++								vht_has_ref_5g_20_40++;
++							else
++								continue;
++
++							if (ent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] != hal_spec->txgi_max)
++								continue;
++
++							if (tlrs == TXPWR_LMT_RS_HT && ref_tlrs == TXPWR_LMT_RS_VHT)
++								ht_ref_vht_5g_20_40++;
++							else if (tlrs == TXPWR_LMT_RS_VHT && ref_tlrs == TXPWR_LMT_RS_HT)
++								vht_ref_ht_5g_20_40++;
++
++							if (0)
++								RTW_INFO("reg:%s, bw:%u, ch:%u, %s-%uT ref %s-%uT\n"
++									, ent->regd_name, bw, channel
++									, txpwr_lmt_rs_str(tlrs), ntx_idx + 1
++									, txpwr_lmt_rs_str(ref_tlrs), ntx_idx + 1);
++
++							ent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] =
++								ent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx];
++						}
++					}
++
++				}
++			}
++		}
++	}
++
++	if (0) {
++		RTW_INFO("ht_ref_vht_5g_20_40:%d, ht_has_ref_5g_20_40:%d\n", ht_ref_vht_5g_20_40, ht_has_ref_5g_20_40);
++		RTW_INFO("vht_ref_ht_5g_20_40:%d, vht_has_ref_5g_20_40:%d\n", vht_ref_ht_5g_20_40, vht_has_ref_5g_20_40);
++	}
++
++	/* 5G 20M&40M HT all come from VHT*/
++	if (ht_ref_vht_5g_20_40 && ht_has_ref_5g_20_40 == ht_ref_vht_5g_20_40)
++		rfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_HT_FROM_VHT;
++
++	/* 5G 20M&40M VHT all come from HT*/
++	if (vht_ref_ht_5g_20_40 && vht_has_ref_5g_20_40 == vht_ref_ht_5g_20_40)
++		rfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_VHT_FROM_HT;
++}
++#endif /* CONFIG_IEEE80211_BAND_5GHZ */
++
++#ifndef DBG_TXPWR_LMT_BAND_CHK
++#define DBG_TXPWR_LMT_BAND_CHK 0
++#endif
++
++#if DBG_TXPWR_LMT_BAND_CHK
++/* check if larger bandwidth limit is less than smaller bandwidth for HT & VHT rate */
++void phy_txpwr_limit_bandwidth_chk(_adapter *adapter)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	u8 band, bw, path, tlrs, ntx_idx, cch, offset, scch;
++	u8 ch_num, n, i;
++
++	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
++		if (!hal_is_band_support(adapter, band))
++			continue;
++
++		for (bw = CHANNEL_WIDTH_40; bw <= CHANNEL_WIDTH_80; bw++) {
++			if (bw >= CHANNEL_WIDTH_160)
++				continue;
++			if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80)
++				continue;
++
++			if (band == BAND_ON_2_4G)
++				ch_num = center_chs_2g_num(bw);
++			else
++				ch_num = center_chs_5g_num(bw);
++
++			if (ch_num == 0) {
++				rtw_warn_on(1);
++				break;
++			}
++
++			for (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; tlrs++) {
++
++				if (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT)
++					continue;
++				if (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK)
++					continue;
++				if (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM))
++					continue;
++				if (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT)
++					continue;
++				if (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
++					continue;
++
++				for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
++					struct txpwr_lmt_ent *ent;
++					_list *cur, *head;
++
++					if (ntx_idx + 1 > hal_data->max_tx_cnt)
++						continue;
++
++					/* bypass CCK multi-TX is not defined */
++					if (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) {
++						if (band == BAND_ON_2_4G
++							&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx)))
++							continue;
++					}
++
++					/* bypass OFDM multi-TX is not defined */
++					if (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) {
++						if (band == BAND_ON_2_4G
++							&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
++							continue;
++						#if CONFIG_IEEE80211_BAND_5GHZ
++						if (band == BAND_ON_5G
++							&& !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
++							continue;
++						#endif
++					}
++
++					/* bypass 5G 20M, 40M pure reference */
++					#if CONFIG_IEEE80211_BAND_5GHZ
++					if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) {
++						if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) {
++							if (tlrs == TXPWR_LMT_RS_HT)
++								continue;
++						} else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) {
++							if (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40)
++								continue;
++						}
++					}
++					#endif
++
++					for (n = 0; n < ch_num; n++) {
++						u8 cch_by_bw[3];
++						u8 offset_by_bw; /* bitmap, 0 for lower, 1 for upper */
++						u8 bw_pos;
++						s8 lmt[3];
++
++						if (band == BAND_ON_2_4G)
++							cch = center_chs_2g(bw, n);
++						else
++							cch = center_chs_5g(bw, n);
++
++						if (cch == 0) {
++							rtw_warn_on(1);
++							break;
++						}
++
++						_rtw_memset(cch_by_bw, 0, 3);
++						cch_by_bw[bw] = cch;
++						offset_by_bw = 0x01;
++
++						do {
++							for (bw_pos = bw; bw_pos >= CHANNEL_WIDTH_40; bw_pos--)
++								cch_by_bw[bw_pos - 1] = rtw_get_scch_by_cch_offset(cch_by_bw[bw_pos], bw_pos, offset_by_bw & BIT(bw_pos) ? HAL_PRIME_CHNL_OFFSET_UPPER : HAL_PRIME_CHNL_OFFSET_LOWER);
++
++							head = &rfctl->txpwr_lmt_list;
++							cur = get_next(head);
++							while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
++								ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
++								cur = get_next(cur);
++
++								for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
++									lmt[bw_pos] = phy_get_txpwr_lmt(adapter, ent->regd_name, band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0);
++
++								for (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--)
++									if (lmt[bw_pos] > lmt[bw_pos - 1])
++										break;
++								if (bw_pos == CHANNEL_WIDTH_20)
++									continue;
++
++								RTW_PRINT_SEL(RTW_DBGDUMP, "[%s][%s][%s][%uT][%-4s] cch:"
++									, band_str(band)
++									, ch_width_str(bw)
++									, txpwr_lmt_rs_str(tlrs)
++									, ntx_idx + 1
++									, ent->regd_name
++								);
++								for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
++									_RTW_PRINT_SEL(RTW_DBGDUMP, "%03u ", cch_by_bw[bw_pos]);
++								_RTW_PRINT_SEL(RTW_DBGDUMP, "limit:");
++								for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) {
++									if (lmt[bw_pos] == hal_spec->txgi_max)
++										_RTW_PRINT_SEL(RTW_DBGDUMP, "N/A ");
++									else if (lmt[bw_pos] > -hal_spec->txgi_pdbm && lmt[bw_pos] < 0) /* -1 < value < 0 */
++										_RTW_PRINT_SEL(RTW_DBGDUMP, "-0.%d", (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
++									else if (lmt[bw_pos] % hal_spec->txgi_pdbm)
++										_RTW_PRINT_SEL(RTW_DBGDUMP, "%2d.%d ", lmt[bw_pos] / hal_spec->txgi_pdbm, (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
++									else
++										_RTW_PRINT_SEL(RTW_DBGDUMP, "%2d ", lmt[bw_pos] / hal_spec->txgi_pdbm);
++								}
++								_RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
++							}
++							for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
++								lmt[bw_pos] = phy_get_txpwr_lmt(adapter, regd_str(TXPWR_LMT_WW), band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0);
++
++							for (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--)
++								if (lmt[bw_pos] > lmt[bw_pos - 1])
++									break;
++							if (bw_pos != CHANNEL_WIDTH_20) {
++								RTW_PRINT_SEL(RTW_DBGDUMP, "[%s][%s][%s][%uT][%-4s] cch:"
++									, band_str(band)
++									, ch_width_str(bw)
++									, txpwr_lmt_rs_str(tlrs)
++									, ntx_idx + 1
++									, regd_str(TXPWR_LMT_WW)
++								);
++								for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
++									_RTW_PRINT_SEL(RTW_DBGDUMP, "%03u ", cch_by_bw[bw_pos]);
++								_RTW_PRINT_SEL(RTW_DBGDUMP, "limit:");
++								for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) {
++									if (lmt[bw_pos] == hal_spec->txgi_max)
++										_RTW_PRINT_SEL(RTW_DBGDUMP, "N/A ");
++									else if (lmt[bw_pos] > -hal_spec->txgi_pdbm && lmt[bw_pos] < 0) /* -1 < value < 0 */
++										_RTW_PRINT_SEL(RTW_DBGDUMP, "-0.%d", (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
++									else if (lmt[bw_pos] % hal_spec->txgi_pdbm)
++										_RTW_PRINT_SEL(RTW_DBGDUMP, "%2d.%d ", lmt[bw_pos] / hal_spec->txgi_pdbm, (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
++									else
++										_RTW_PRINT_SEL(RTW_DBGDUMP, "%2d ", lmt[bw_pos] / hal_spec->txgi_pdbm);
++								}
++								_RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
++							}
++
++							offset_by_bw += 2;
++							if (offset_by_bw & BIT(bw + 1))
++								break;
++						} while (1); /* loop for all ch combinations */
++					} /* loop for center channels */
++				} /* loop fo each ntx_idx */
++			} /* loop for tlrs */
++		} /* loop for bandwidth */
++	} /* loop for band */
++}
++#endif /* DBG_TXPWR_LMT_BAND_CHK */
++
++static void phy_txpwr_lmt_post_hdl(_adapter *adapter)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	_irqL irqL;
++
++	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++
++#if CONFIG_IEEE80211_BAND_5GHZ
++	if (IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
++		phy_txpwr_lmt_cross_ref_ht_vht(adapter);
++#endif
++	phy_txpwr_lmt_cck_ofdm_mt_chk(adapter);
++
++#if DBG_TXPWR_LMT_BAND_CHK
++	phy_txpwr_limit_bandwidth_chk(adapter);
++#endif
++
++	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
++}
++
++BOOLEAN
++GetS1ByteIntegerFromStringInDecimal(
++			char	*str,
++			s8		*val
++)
++{
++	u8 negative = 0;
++	u16 i = 0;
++
++	*val = 0;
++
++	while (str[i] != '\0') {
++		if (i == 0 && (str[i] == '+' || str[i] == '-')) {
++			if (str[i] == '-')
++				negative = 1;
++		} else if (str[i] >= '0' && str[i] <= '9') {
++			*val *= 10;
++			*val += (str[i] - '0');
++		} else
++			return _FALSE;
++		++i;
++	}
++
++	if (negative)
++		*val = -*val;
++
++	return _TRUE;
++}
++#endif /* CONFIG_TXPWR_LIMIT */
++
++/*
++* phy_set_tx_power_limit - Parsing TX power limit from phydm array, called by odm_ConfigBB_TXPWR_LMT_XXX in phydm
++*/
++void
++phy_set_tx_power_limit(
++		struct dm_struct		*pDM_Odm,
++		u8				*Regulation,
++		u8				*Band,
++		u8				*Bandwidth,
++		u8				*RateSection,
++		u8				*ntx,
++		u8				*Channel,
++		u8				*PowerLimit
++)
++{
++#if CONFIG_TXPWR_LIMIT
++	PADAPTER Adapter = pDM_Odm->adapter;
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
++	u8 band = 0, bandwidth = 0, tlrs = 0, channel;
++	u8 ntx_idx;
++	s8 powerLimit = 0, prevPowerLimit, channelIndex;
++	s8 ww_lmt_val = phy_txpwr_ww_lmt_value(Adapter);
++
++	if (0)
++		RTW_INFO("Index of power limit table [regulation %s][band %s][bw %s][rate section %s][ntx %s][chnl %s][val %s]\n"
++			, Regulation, Band, Bandwidth, RateSection, ntx, Channel, PowerLimit);
++
++	if (GetU1ByteIntegerFromStringInDecimal((char *)Channel, &channel) == _FALSE
++		|| GetS1ByteIntegerFromStringInDecimal((char *)PowerLimit, &powerLimit) == _FALSE
++	) {
++		RTW_PRINT("Illegal index of power limit table [ch %s][val %s]\n", Channel, PowerLimit);
++		return;
++	}
++
++	if (powerLimit != ww_lmt_val) {
++		if (powerLimit < -hal_spec->txgi_max || powerLimit > hal_spec->txgi_max)
++			RTW_PRINT("Illegal power limit value [ch %s][val %s]\n", Channel, PowerLimit);
++
++		if (powerLimit > hal_spec->txgi_max)
++			powerLimit = hal_spec->txgi_max;
++		else if (powerLimit < -hal_spec->txgi_max)
++			powerLimit =  ww_lmt_val + 1;
++	}
++
++	if (strncmp(RateSection, "CCK", 3) == 0)
++		tlrs = TXPWR_LMT_RS_CCK;
++	else if (strncmp(RateSection, "OFDM", 4) == 0)
++		tlrs = TXPWR_LMT_RS_OFDM;
++	else if (strncmp(RateSection, "HT", 2) == 0)
++		tlrs = TXPWR_LMT_RS_HT;
++	else if (strncmp(RateSection, "VHT", 3) == 0)
++		tlrs = TXPWR_LMT_RS_VHT;
++	else {
++		RTW_PRINT("Wrong rate section:%s\n", RateSection);
++		return;
++	}
++
++	if (strncmp(ntx, "1T", 2) == 0)
++		ntx_idx = RF_1TX;
++	else if (strncmp(ntx, "2T", 2) == 0)
++		ntx_idx = RF_2TX;
++	else if (strncmp(ntx, "3T", 2) == 0)
++		ntx_idx = RF_3TX;
++	else if (strncmp(ntx, "4T", 2) == 0)
++		ntx_idx = RF_4TX;
++	else {
++		RTW_PRINT("Wrong tx num:%s\n", ntx);
++		return;
++	}
++
++	if (strncmp(Bandwidth, "20M", 3) == 0)
++		bandwidth = CHANNEL_WIDTH_20;
++	else if (strncmp(Bandwidth, "40M", 3) == 0)
++		bandwidth = CHANNEL_WIDTH_40;
++	else if (strncmp(Bandwidth, "80M", 3) == 0)
++		bandwidth = CHANNEL_WIDTH_80;
++	else if (strncmp(Bandwidth, "160M", 4) == 0)
++		bandwidth = CHANNEL_WIDTH_160;
++	else {
++		RTW_PRINT("unknown bandwidth: %s\n", Bandwidth);
++		return;
++	}
++
++	if (strncmp(Band, "2.4G", 4) == 0) {
++		band = BAND_ON_2_4G;
++		channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, channel);
++
++		if (channelIndex == -1) {
++			RTW_PRINT("unsupported channel: %d at 2.4G\n", channel);
++			return;
++		}
++
++		if (bandwidth >= MAX_2_4G_BANDWIDTH_NUM) {
++			RTW_PRINT("unsupported bandwidth: %s at 2.4G\n", Bandwidth);
++			return;
++		}
++
++		rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);
++	}
++#if CONFIG_IEEE80211_BAND_5GHZ
++	else if (strncmp(Band, "5G", 2) == 0) {
++		band = BAND_ON_5G;
++		channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, channel);
++
++		if (channelIndex == -1) {
++			RTW_PRINT("unsupported channel: %d at 5G\n", channel);
++			return;
++		}
++
++		rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);
++	}
++#endif
++	else {
++		RTW_PRINT("unknown/unsupported band:%s\n", Band);
++		return;
++	}
++#endif
++}
++
++void
++phy_set_tx_power_limit_ex(
++		struct dm_struct		*pDM_Odm,
++		u8				Regulation,
++		u8				Band,
++		u8				Bandwidth,
++		u8				RateSection,
++		u8				ntx,
++		u8				channel,
++		s8				powerLimit
++)
++{
++#if CONFIG_TXPWR_LIMIT
++	PADAPTER Adapter = pDM_Odm->adapter;
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
++	u8 regd;
++	u8 band = 0, bandwidth = 0, tlrs = 0;
++	u8 ntx_idx;
++	s8 prevPowerLimit, channelIndex;
++	s8 ww_lmt_val = phy_txpwr_ww_lmt_value(Adapter);
++
++	if (0)
++		RTW_INFO("Index of power limit table [regulation %d][band %d][bw %d][rate section %d][ntx %d][chnl %d][val %d]\n"
++			, Regulation, Band, Bandwidth, RateSection, ntx, channel, powerLimit);
++
++	if (powerLimit != ww_lmt_val) {
++		if (powerLimit < -hal_spec->txgi_max || powerLimit > hal_spec->txgi_max)
++			RTW_PRINT("Illegal power limit value [ch %d][val %d]\n", channel, powerLimit);
++
++		if (powerLimit > hal_spec->txgi_max)
++			powerLimit = hal_spec->txgi_max;
++		else if (powerLimit < -hal_spec->txgi_max)
++			powerLimit =  ww_lmt_val + 1;
++	}
++
++	switch (Regulation) {
++	case PW_LMT_REGU_FCC:
++		regd = TXPWR_LMT_FCC;
++		break;
++	case PW_LMT_REGU_ETSI:
++		regd = TXPWR_LMT_ETSI;
++		break;
++	case PW_LMT_REGU_MKK:
++		regd = TXPWR_LMT_MKK;
++		break;
++	case PW_LMT_REGU_IC:
++		regd = TXPWR_LMT_IC;
++		break;
++	case PW_LMT_REGU_KCC:
++		regd = TXPWR_LMT_KCC;
++		break;
++	case PW_LMT_REGU_ACMA:
++		regd = TXPWR_LMT_ACMA;
++		break;
++	case PW_LMT_REGU_CHILE:
++		regd = TXPWR_LMT_CHILE;
++		break;
++	case PW_LMT_REGU_UKRAINE:
++		regd = TXPWR_LMT_UKRAINE;
++		break;
++	case PW_LMT_REGU_MEXICO:
++		regd = TXPWR_LMT_MEXICO;
++		break;
++	case PW_LMT_REGU_CN:
++		regd = TXPWR_LMT_CN;
++		break;
++	case PW_LMT_REGU_WW13:
++	default:	
++		RTW_PRINT("Wrong regulation:%d\n", Regulation);
++		return;		
++	}
++
++	switch (RateSection) {
++	case PW_LMT_RS_CCK:
++		tlrs = TXPWR_LMT_RS_CCK;
++		break;
++	case PW_LMT_RS_OFDM:
++		tlrs = TXPWR_LMT_RS_OFDM;
++		break;
++	case PW_LMT_RS_HT:
++		tlrs = TXPWR_LMT_RS_HT;
++		break;
++	case PW_LMT_RS_VHT:
++		tlrs = TXPWR_LMT_RS_VHT;
++		break;
++	default:
++		RTW_PRINT("Wrong rate section:%d\n", RateSection);
++		return;
++	}
++
++	switch (ntx) {
++	case PW_LMT_PH_1T:
++		ntx_idx = RF_1TX;
++		break;
++	case PW_LMT_PH_2T:
++		ntx_idx = RF_2TX;
++		break;
++	case PW_LMT_PH_3T:
++		ntx_idx = RF_3TX;
++		break;
++	case PW_LMT_PH_4T:
++		ntx_idx = RF_4TX;
++		break;
++	default:
++		RTW_PRINT("Wrong tx num:%d\n", ntx);
++		return;
++	}
++
++	switch (Bandwidth) {
++	case PW_LMT_BW_20M:
++		bandwidth = CHANNEL_WIDTH_20;
++		break;
++	case PW_LMT_BW_40M:
++		bandwidth = CHANNEL_WIDTH_40;
++		break;
++	case PW_LMT_BW_80M:
++		bandwidth = CHANNEL_WIDTH_80;
++		break;
++	case PW_LMT_BW_160M:
++		bandwidth = CHANNEL_WIDTH_160;
++		break;
++	default:
++		RTW_PRINT("unknown bandwidth: %d\n", Bandwidth);
++		return;
++	}
++
++	if (Band == PW_LMT_BAND_2_4G) {
++		band = BAND_ON_2_4G;
++		channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, channel);
++
++		if (channelIndex == -1) {
++			RTW_PRINT("unsupported channel: %d at 2.4G\n", channel);
++			return;
++		}
++
++		if (bandwidth >= MAX_2_4G_BANDWIDTH_NUM) {
++			RTW_PRINT("unsupported bandwidth: %s at 2.4G\n", ch_width_str(bandwidth));
++			return;
++		}
++
++		rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), regd_str(regd), band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);
++	}
++#if CONFIG_IEEE80211_BAND_5GHZ
++	else if (Band == PW_LMT_BAND_5G) {
++		band = BAND_ON_5G;
++		channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, channel);
++
++		if (channelIndex == -1) {
++			RTW_PRINT("unsupported channel: %d at 5G\n", channel);
++			return;
++		}
++
++		rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), regd_str(regd), band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);
++	}
++#endif
++	else {
++		RTW_PRINT("unknown/unsupported band:%d\n", Band);
++		return;
++	}
++#endif
++}
++
++u8 phy_get_tx_power_index_ex(_adapter *adapter
++	, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate
++	, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch)
++{
++	return rtw_hal_get_tx_power_index(adapter, rfpath, rs, rate, bw, band, cch, opch, NULL);
++}
++
++u8 phy_get_tx_power_index(
++		PADAPTER			pAdapter,
++		enum rf_path		RFPath,
++		u8					Rate,
++		enum channel_width	BandWidth,
++		u8					Channel
++)
++{
++	RATE_SECTION rs = mgn_rate_to_rs(Rate);
++	BAND_TYPE band = Channel <= 14 ? BAND_ON_2_4G : BAND_ON_5G;
++
++	return rtw_hal_get_tx_power_index(pAdapter, RFPath, rs, Rate, BandWidth, band, Channel, 0, NULL);
++}
++
++void
++PHY_SetTxPowerIndex(
++		PADAPTER		pAdapter,
++		u32				PowerIndex,
++		enum rf_path		RFPath,
++		u8				Rate
++)
++{
++	rtw_hal_set_tx_power_index(pAdapter, PowerIndex, RFPath, Rate);
++}
++
++void dump_tx_power_index_inline(void *sel, _adapter *adapter, u8 rfpath, enum channel_width bw, u8 cch, enum MGN_RATE rate, u8 pwr_idx, struct txpwr_idx_comp *tic)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++
++	if (tic->utarget == hal_spec->txgi_max) {
++		RTW_PRINT_SEL(sel, "TXPWR: [%c][%s]cch:%u, %s %uT, idx:%u(0x%02x) = base(%d) + min((byr(%d) + btc(%d) + extra(%d)), lmt(%d), ulmt(%d)) + tpt(%d) + dpd(%d)\n"
++			, rf_path_char(rfpath), ch_width_str(bw), cch
++			, MGN_RATE_STR(rate), tic->ntx_idx + 1
++			, pwr_idx, pwr_idx, tic->base
++			, tic->by_rate, tic->btc, tic->extra, tic->limit, tic->ulimit
++			, tic->tpt, tic->dpd);
++	} else {
++		RTW_PRINT_SEL(sel, "TXPWR: [%c][%s]cch:%u, %s %uT, idx:%u(0x%02x) = base(%d) + min(utgt(%d), lmt(%d), ulmt(%d)) + tpt(%d) + dpd(%d)\n"
++			, rf_path_char(rfpath), ch_width_str(bw), cch
++			, MGN_RATE_STR(rate), tic->ntx_idx + 1
++			, pwr_idx, pwr_idx, tic->base
++			, tic->utarget, tic->limit, tic->ulimit
++			, tic->tpt, tic->dpd);
++	}
++}
++
++void dump_tx_power_idx_value(void *sel, _adapter *adapter, u8 rfpath, enum MGN_RATE rate, u8 pwr_idx, struct txpwr_idx_comp *tic)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	char tmp_str[8];
++
++	txpwr_idx_get_dbm_str(tic->target, hal_spec->txgi_max, hal_spec->txgi_pdbm, 0, tmp_str, 8);
++
++	if (tic->utarget == hal_spec->txgi_max) {
++		RTW_PRINT_SEL(sel, "%4c %9s %uT %s %3u(0x%02x)"
++			"   %4d      ((%4d   %3d   %5d)  %4d  %4d)   %3d   %3d\n"
++			, rf_path_char(rfpath), MGN_RATE_STR(rate), tic->ntx_idx + 1
++			, tmp_str, pwr_idx, pwr_idx
++			, tic->base, tic->by_rate, tic->btc, tic->extra, tic->limit, tic->ulimit
++			, tic->tpt, tic->dpd);
++	} else {
++		RTW_PRINT_SEL(sel, "%4c %9s %uT %s %3u(0x%02x)"
++			"   %4d      (%4d  %4d  %4d)   %3d   %3d\n"
++			, rf_path_char(rfpath), MGN_RATE_STR(rate), tic->ntx_idx + 1
++			, tmp_str, pwr_idx, pwr_idx
++			, tic->base, tic->utarget, tic->limit, tic->ulimit
++			, tic->tpt, tic->dpd);
++	}
++}
++
++void dump_tx_power_idx_title(void *sel, _adapter *adapter, enum channel_width bw, u8 cch, u8 opch)
++{
++	u8 cch_20, cch_40, cch_80;
++
++	cch_80 = bw == CHANNEL_WIDTH_80 ? cch : 0;
++	cch_40 = bw == CHANNEL_WIDTH_40 ? cch : 0;
++	cch_20 = bw == CHANNEL_WIDTH_20 ? cch : 0;
++	if (cch_80 != 0)
++		cch_40 = rtw_get_scch_by_cch_opch(cch_80, CHANNEL_WIDTH_80, opch);
++	if (cch_40 != 0)
++		cch_20 = rtw_get_scch_by_cch_opch(cch_40, CHANNEL_WIDTH_40, opch);
++
++	RTW_PRINT_SEL(sel, "%s", ch_width_str(bw));
++	if (bw >= CHANNEL_WIDTH_80)
++		_RTW_PRINT_SEL(sel, ", cch80:%u", cch_80);
++	if (bw >= CHANNEL_WIDTH_40)
++		_RTW_PRINT_SEL(sel, ", cch40:%u", cch_40);
++	_RTW_PRINT_SEL(sel, ", cch20:%u\n", cch_20);
++
++	if (!phy_is_txpwr_user_target_specified(adapter)) {
++		RTW_PRINT_SEL(sel, "%-4s %-9s %2s %-6s %-3s%6s"
++			" = %-4s + min((%-4s + %-3s + %-5s), %-4s, %-4s) + %-3s + %-3s\n"
++			, "path", "rate", "", "dBm", "idx", ""
++			, "base", "byr", "btc", "extra", "lmt", "ulmt"
++			, "tpt", "dpd");
++	} else {
++		RTW_PRINT_SEL(sel, "%-4s %-9s %2s %-6s %-3s%6s"
++			" = %-4s + min(%-4s, %-4s, %-4s) + %-3s + %-3s\n"
++			, "path", "rate", "", "dBm", "idx", ""
++			, "base", "utgt", "lmt", "ulmt"
++			, "tpt", "dpd");
++	}
++}
++
++void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath
++	, RATE_SECTION rs, enum channel_width bw, u8 cch, u8 opch)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	u8 power_idx;
++	struct txpwr_idx_comp tic;
++	u8 tx_num, i;
++	u8 band = cch > 14 ? BAND_ON_5G : BAND_ON_2_4G;
++
++	if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, rfpath))
++		return;
++
++	if (rs >= RATE_SECTION_NUM)
++		return;
++
++	tx_num = rate_section_to_tx_num(rs);
++	if (tx_num + 1 > hal_data->tx_nss)
++		return;
++
++	if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
++		return;
++
++	if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
++		return;
++
++	for (i = 0; i < rates_by_sections[rs].rate_num; i++) {
++		power_idx = rtw_hal_get_tx_power_index(adapter, rfpath, rs, rates_by_sections[rs].rates[i], bw, band, cch, opch, &tic);
++		dump_tx_power_idx_value(sel, adapter, rfpath, rates_by_sections[rs].rates[i], power_idx, &tic);
++	}
++}
++
++void dump_tx_power_idx(void *sel, _adapter *adapter, enum channel_width bw, u8 cch, u8 opch)
++{
++	u8 rfpath, rs;
++
++	dump_tx_power_idx_title(sel, adapter, bw, cch, opch);
++	for (rfpath = RF_PATH_A; rfpath < RF_PATH_MAX; rfpath++)
++		for (rs = CCK; rs < RATE_SECTION_NUM; rs++)
++			dump_tx_power_idx_by_path_rs(sel, adapter, rfpath, rs, bw, cch, opch);
++}
++
++void dump_txpwr_total_dbm_value(void *sel, _adapter *adapter, enum MGN_RATE rate, u8 ntx_idx
++	, s16 target, s16 byr, s16 btc, s16 extra, s16 lmt, s16 ulmt)
++{
++	char target_str[8];
++	char byr_str[8];
++	char btc_str[8];
++	char extra_str[8];
++	char lmt_str[8];
++	char ulmt_str[8];
++
++	txpwr_mbm_get_dbm_str(target, 0, target_str, 8);
++	txpwr_mbm_get_dbm_str(byr, 0, byr_str, 8);
++	txpwr_mbm_get_dbm_str(btc, 0, btc_str, 8);
++	txpwr_mbm_get_dbm_str(extra, 0, extra_str, 8);
++	txpwr_mbm_get_dbm_str(lmt, 0, lmt_str, 8);
++	txpwr_mbm_get_dbm_str(ulmt, 0, ulmt_str, 8);
++
++	RTW_PRINT_SEL(sel, "%9s %uT %s =    ((%s   %s   %s), %s, %s)\n"
++		, MGN_RATE_STR(rate), ntx_idx + 1
++		, target_str, byr_str, btc_str, extra_str, lmt_str, ulmt_str);
++}
++
++void dump_txpwr_total_dbm_value_utgt(void *sel, _adapter *adapter, enum MGN_RATE rate, u8 ntx_idx
++	, s16 target, s16 utgt, s16 lmt, s16 ulmt)
++{
++	char target_str[8];
++	char utgt_str[8];
++	char lmt_str[8];
++	char ulmt_str[8];
++
++	txpwr_mbm_get_dbm_str(target, 0, target_str, 8);
++	txpwr_mbm_get_dbm_str(utgt, 0, utgt_str, 8);
++	txpwr_mbm_get_dbm_str(lmt, 0, lmt_str, 8);
++	txpwr_mbm_get_dbm_str(ulmt, 0, ulmt_str, 8);
++
++	RTW_PRINT_SEL(sel, "%9s %uT %s =    (%s, %s, %s)\n"
++		, MGN_RATE_STR(rate), ntx_idx + 1
++		, target_str, utgt_str, lmt_str, ulmt_str);
++}
++
++void dump_txpwr_total_dbm_title(void *sel, _adapter *adapter, enum channel_width bw, u8 cch, u8 opch)
++{
++	u8 cch_20, cch_40, cch_80;
++
++	cch_80 = bw == CHANNEL_WIDTH_80 ? cch : 0;
++	cch_40 = bw == CHANNEL_WIDTH_40 ? cch : 0;
++	cch_20 = bw == CHANNEL_WIDTH_20 ? cch : 0;
++	if (cch_80 != 0)
++		cch_40 = rtw_get_scch_by_cch_opch(cch_80, CHANNEL_WIDTH_80, opch);
++	if (cch_40 != 0)
++		cch_20 = rtw_get_scch_by_cch_opch(cch_40, CHANNEL_WIDTH_40, opch);
++
++	RTW_PRINT_SEL(sel, "%s", ch_width_str(bw));
++	if (bw >= CHANNEL_WIDTH_80)
++		_RTW_PRINT_SEL(sel, ", cch80:%u", cch_80);
++	if (bw >= CHANNEL_WIDTH_40)
++		_RTW_PRINT_SEL(sel, ", cch40:%u", cch_40);
++	_RTW_PRINT_SEL(sel, ", cch20:%u\n", cch_20);
++
++	if (!phy_is_txpwr_user_target_specified(adapter)) {
++		RTW_PRINT_SEL(sel, "%-9s %2s %-6s = min((%-6s + %-6s + %-6s), %-6s, %-6s)\n"
++			, "rate", "", "target", "byr", "btc", "extra", "lmt", "ulmt");
++	} else {
++		RTW_PRINT_SEL(sel, "%-9s %2s %-6s = min(%-6s, %-6s, %-6s)\n"
++			, "rate", "", "target", "utgt", "lmt", "ulmt");
++	}
++}
++
++void dump_txpwr_total_dbm_by_rs(void *sel, _adapter *adapter, u8 rs, enum channel_width bw, u8 cch, u8 opch)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	u8 i;
++	u8 band = cch > 14 ? BAND_ON_5G : BAND_ON_2_4G;
++
++	if (rs >= RATE_SECTION_NUM)
++		return;
++
++	if (rate_section_to_tx_num(rs) + 1 > hal_data->tx_nss)
++		return;
++
++	if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
++		return;
++
++	if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
++		return;
++
++	for (i = 0; i < rates_by_sections[rs].rate_num; i++) {
++		struct txpwr_idx_comp tic;
++		s16 target, byr, btc, extra, utgt, lmt, ulmt;
++		u8 tx_num;
++
++		target = phy_get_txpwr_total_mbm(adapter, rs, rates_by_sections[rs].rates[i], bw, cch, opch, &tic);
++		tx_num = tic.ntx_idx + 1;
++		if (tic.limit == hal_spec->txgi_max)
++			lmt = UNSPECIFIED_MBM;
++		else
++			lmt = ((tic.limit * MBM_PDBM) / hal_spec->txgi_pdbm) + mb_of_ntx(tx_num);
++		if (tic.ulimit == hal_spec->txgi_max)
++			ulmt = UNSPECIFIED_MBM;
++		else
++			ulmt = ((tic.ulimit * MBM_PDBM) / hal_spec->txgi_pdbm) + mb_of_ntx(tx_num);
++
++		if (tic.utarget == hal_spec->txgi_max) {
++			byr = ((tic.by_rate * MBM_PDBM) / hal_spec->txgi_pdbm) + mb_of_ntx(tx_num);
++			btc = (tic.btc * MBM_PDBM) / hal_spec->txgi_pdbm;
++			extra = (tic.extra * MBM_PDBM) / hal_spec->txgi_pdbm;
++			dump_txpwr_total_dbm_value(sel, adapter, rates_by_sections[rs].rates[i], tic.ntx_idx
++				, target, byr, btc, extra, lmt, ulmt);
++		} else {
++			utgt = ((tic.utarget * MBM_PDBM) / hal_spec->txgi_pdbm) + mb_of_ntx(tx_num);
++			dump_txpwr_total_dbm_value_utgt(sel, adapter, rates_by_sections[rs].rates[i], tic.ntx_idx
++				, target, utgt, lmt, ulmt);
++		}
++	}
++}
++
++/* dump txpowr in dBm with effect of N-TX */
++void dump_txpwr_total_dbm(void *sel, _adapter *adapter, enum channel_width bw, u8 cch, u8 opch)
++{
++	u8 rs;
++
++	dump_txpwr_total_dbm_title(sel, adapter, bw, cch, opch);
++	for (rs = CCK; rs < RATE_SECTION_NUM; rs++)
++		dump_txpwr_total_dbm_by_rs(sel, adapter, rs, bw, cch, opch);
++}
++
++bool phy_is_tx_power_limit_needed(_adapter *adapter)
++{
++#if CONFIG_TXPWR_LIMIT
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
++
++	if (regsty->RegEnableTxPowerLimit == 1
++		|| (regsty->RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory == 1))
++		return _TRUE;
++#endif
++
++	return _FALSE;
++}
++
++bool phy_is_tx_power_by_rate_needed(_adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
++
++	if (regsty->RegEnableTxPowerByRate == 1
++		|| (regsty->RegEnableTxPowerByRate == 2 && hal_data->EEPROMRegulatory != 2))
++		return _TRUE;
++
++	return _FALSE;
++}
++
++int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	int ret = _FAIL;
++
++	hal_data->txpwr_by_rate_loaded = 0;
++	PHY_InitTxPowerByRate(adapter);
++
++	/* tx power limit is based on tx power by rate */
++	hal_data->txpwr_limit_loaded = 0;
++
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++	if (chk_file
++		&& phy_ConfigBBWithPgParaFile(adapter, PHY_FILE_PHY_REG_PG) == _SUCCESS
++	) {
++		hal_data->txpwr_by_rate_from_file = 1;
++		goto post_hdl;
++	}
++#endif
++
++#ifdef CONFIG_EMBEDDED_FWIMG
++	if (HAL_STATUS_SUCCESS == odm_config_bb_with_header_file(&hal_data->odmpriv, CONFIG_BB_PHY_REG_PG)) {
++		RTW_INFO("default power by rate loaded\n");
++		hal_data->txpwr_by_rate_from_file = 0;
++		goto post_hdl;
++	}
++#endif
++
++	RTW_ERR("%s():Read Tx power by rate fail\n", __func__);
++	goto exit;
++
++post_hdl:
++	if (hal_data->odmpriv.phy_reg_pg_value_type != PHY_REG_PG_EXACT_VALUE) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	PHY_TxPowerByRateConfiguration(adapter);
++	hal_data->txpwr_by_rate_loaded = 1;
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++
++#if CONFIG_TXPWR_LIMIT
++int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	int ret = _FAIL;
++
++	hal_data->txpwr_limit_loaded = 0;
++	rtw_regd_exc_list_free(rfctl);
++	rtw_txpwr_lmt_list_free(rfctl);
++
++	if (!hal_data->txpwr_by_rate_loaded && regsty->target_tx_pwr_valid != _TRUE) {
++		RTW_ERR("%s():Read Tx power limit before target tx power is specify\n", __func__);
++		goto exit;
++	}
++
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++	if (chk_file
++		&& PHY_ConfigRFWithPowerLimitTableParaFile(adapter, PHY_FILE_TXPWR_LMT) == _SUCCESS
++	) {
++		hal_data->txpwr_limit_from_file = 1;
++		goto post_hdl;
++	}
++#endif
++
++#ifdef CONFIG_EMBEDDED_FWIMG
++	if (odm_config_rf_with_header_file(&hal_data->odmpriv, CONFIG_RF_TXPWR_LMT, RF_PATH_A) == HAL_STATUS_SUCCESS) {
++		RTW_INFO("default power limit loaded\n");
++		hal_data->txpwr_limit_from_file = 0;
++		goto post_hdl;
++	}
++#endif
++
++	RTW_ERR("%s():Read Tx power limit fail\n", __func__);
++	goto exit;
++
++post_hdl:
++	phy_txpwr_lmt_post_hdl(adapter);
++	rtw_txpwr_init_regd(rfctl);
++	hal_data->txpwr_limit_loaded = 1;
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++#endif /* CONFIG_TXPWR_LIMIT */
++
++void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file)
++{
++	struct registry_priv *regsty = adapter_to_regsty(adapter);
++
++	/* check registy target tx power */
++	regsty->target_tx_pwr_valid = rtw_regsty_chk_target_tx_power_valid(adapter);
++
++	/* power by rate */
++	if (phy_is_tx_power_by_rate_needed(adapter)
++		|| regsty->target_tx_pwr_valid != _TRUE /* need target tx power from by rate table */
++	)
++		phy_load_tx_power_by_rate(adapter, chk_file);
++
++	/* power limit */
++#if CONFIG_TXPWR_LIMIT
++	if (phy_is_tx_power_limit_needed(adapter))
++		phy_load_tx_power_limit(adapter, chk_file);
++#endif
++}
++
++inline void phy_reload_tx_power_ext_info(_adapter *adapter)
++{
++	phy_load_tx_power_ext_info(adapter, 1);
++}
++
++inline void phy_reload_default_tx_power_ext_info(_adapter *adapter)
++{
++	phy_load_tx_power_ext_info(adapter, 0);
++}
++
++void dump_tx_power_ext_info(void *sel, _adapter *adapter)
++{
++	struct registry_priv *regsty = adapter_to_regsty(adapter);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++
++	RTW_PRINT_SEL(sel, "txpwr_pg_mode: %s\n", txpwr_pg_mode_str(hal_data->txpwr_pg_mode));
++
++	if (regsty->target_tx_pwr_valid == _TRUE)
++		RTW_PRINT_SEL(sel, "target_tx_power: from registry\n");
++	else if (hal_data->txpwr_by_rate_loaded)
++		RTW_PRINT_SEL(sel, "target_tx_power: from power by rate\n");
++	else
++		RTW_PRINT_SEL(sel, "target_tx_power: unavailable\n");
++
++	RTW_PRINT_SEL(sel, "tx_power_by_rate: %s, %s, %s\n"
++		, phy_is_tx_power_by_rate_needed(adapter) ? "enabled" : "disabled"
++		, hal_data->txpwr_by_rate_loaded ? "loaded" : "unloaded"
++		, hal_data->txpwr_by_rate_from_file ? "file" : "default"
++	);
++
++	RTW_PRINT_SEL(sel, "tx_power_limit: %s, %s, %s\n"
++		, phy_is_tx_power_limit_needed(adapter) ? "enabled" : "disabled"
++		, hal_data->txpwr_limit_loaded ? "loaded" : "unloaded"
++		, hal_data->txpwr_limit_from_file ? "file" : "default"
++	);
++}
++
++void dump_target_tx_power(void *sel, _adapter *adapter)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct registry_priv *regsty = adapter_to_regsty(adapter);
++	int path, tx_num, band, rs;
++	u8 target;
++
++	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
++		if (!hal_is_band_support(adapter, band))
++			continue;
++
++		for (path = 0; path < RF_PATH_MAX; path++) {
++			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
++				break;
++
++			RTW_PRINT_SEL(sel, "[%s][%c]%s\n", band_str(band), rf_path_char(path)
++				, (regsty->target_tx_pwr_valid == _FALSE && hal_data->txpwr_by_rate_undefined_band_path[band][path]) ? "(dup)" : "");
++
++			for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
++				tx_num = rate_section_to_tx_num(rs);
++				if (tx_num + 1 > hal_data->tx_nss)
++					continue;
++
++				if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
++					continue;
++
++				if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
++					continue;
++
++				target = phy_get_target_txpwr(adapter, band, path, rs);
++
++				if (target % hal_spec->txgi_pdbm) {
++					_RTW_PRINT_SEL(sel, "%7s: %2d.%d\n", rate_section_str(rs)
++						, target / hal_spec->txgi_pdbm, (target % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
++				} else {
++					_RTW_PRINT_SEL(sel, "%7s: %5d\n", rate_section_str(rs)
++						, target / hal_spec->txgi_pdbm);
++				}
++			}
++		}
++	}
++
++	return;
++}
++
++void dump_tx_power_by_rate(void *sel, _adapter *adapter)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	int path, tx_num, band, n, rs;
++	u8 rate_num, max_rate_num, base;
++	s8 by_rate;
++
++	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
++		if (!hal_is_band_support(adapter, band))
++			continue;
++
++		for (path = 0; path < RF_PATH_MAX; path++) {
++			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
++				break;
++
++			RTW_PRINT_SEL(sel, "[%s][%c]%s\n", band_str(band), rf_path_char(path)
++				, hal_data->txpwr_by_rate_undefined_band_path[band][path] ? "(dup)" : "");
++
++			for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
++				tx_num = rate_section_to_tx_num(rs);
++				if (tx_num + 1 > hal_data->tx_nss)
++					continue;
++
++				if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
++					continue;
++
++				if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
++					continue;
++
++				if (IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
++					max_rate_num = 10;
++				else
++					max_rate_num = 8;
++				rate_num = rate_section_rate_num(rs);
++
++				RTW_PRINT_SEL(sel, "%7s: ", rate_section_str(rs));
++
++				/* dump power by rate in db */
++				for (n = rate_num - 1; n >= 0; n--) {
++					by_rate = PHY_GetTxPowerByRate(adapter, band, path, rs, rates_by_sections[rs].rates[n]);
++					if (by_rate % hal_spec->txgi_pdbm) {
++						_RTW_PRINT_SEL(sel, "%2d.%d ", by_rate / hal_spec->txgi_pdbm
++							, (by_rate % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
++					} else
++						_RTW_PRINT_SEL(sel, "%5d ", by_rate / hal_spec->txgi_pdbm);
++				}
++				for (n = 0; n < max_rate_num - rate_num; n++)
++					_RTW_PRINT_SEL(sel, "%5s ", "");
++
++				_RTW_PRINT_SEL(sel, "|");
++
++				/* dump power by rate in offset */
++				for (n = rate_num - 1; n >= 0; n--) {
++					by_rate = PHY_GetTxPowerByRate(adapter, band, path, rs, rates_by_sections[rs].rates[n]);
++					base = phy_get_target_txpwr(adapter, band, path, rs);
++					_RTW_PRINT_SEL(sel, "%3d ", by_rate - base);
++				}
++				RTW_PRINT_SEL(sel, "\n");
++
++			}
++		}
++	}
++}
++
++/*
++ * phy file path is stored in global char array rtw_phy_para_file_path
++ * need to care about racing
++ */
++int rtw_get_phy_file_path(_adapter *adapter, const char *file_name)
++{
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	int len = 0;
++
++	if (file_name) {
++		len += snprintf(rtw_phy_para_file_path, PATH_LENGTH_MAX, "%s", rtw_phy_file_path);
++		#if defined(CONFIG_MULTIDRV) || defined(REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER)
++		len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s/", hal_spec->ic_name);
++		#endif
++		len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s", file_name);
++
++		return _TRUE;
++	}
++#endif
++	return _FALSE;
++}
++
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++int
++phy_ConfigMACWithParaFile(
++		PADAPTER	Adapter,
++		char		*pFileName
++)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
++	int	rlen = 0, rtStatus = _FAIL;
++	char	*szLine, *ptmp;
++	u32	u4bRegOffset, u4bRegValue, u4bMove;
++
++	if (!(Adapter->registrypriv.load_phy_file & LOAD_MAC_PARA_FILE))
++		return rtStatus;
++
++	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
++
++	if ((pHalData->mac_reg_len == 0) && (pHalData->mac_reg == NULL)) {
++		rtw_get_phy_file_path(Adapter, pFileName);
++		if (rtw_readable_file_sz_chk(rtw_phy_para_file_path, 
++			MAX_PARA_FILE_BUF_LEN) == _TRUE) {
++			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
++			if (rlen > 0) {
++				rtStatus = _SUCCESS;
++				pHalData->mac_reg = rtw_zvmalloc(rlen);
++				if (pHalData->mac_reg) {
++					_rtw_memcpy(pHalData->mac_reg, pHalData->para_file_buf, rlen);
++					pHalData->mac_reg_len = rlen;
++				} else
++					RTW_INFO("%s mac_reg alloc fail !\n", __FUNCTION__);
++			}
++		}
++	} else {
++		if ((pHalData->mac_reg_len != 0) && (pHalData->mac_reg != NULL)) {
++			_rtw_memcpy(pHalData->para_file_buf, pHalData->mac_reg, pHalData->mac_reg_len);
++			rtStatus = _SUCCESS;
++		} else
++			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
++	}
++
++	if (rtStatus == _SUCCESS) {
++		ptmp = pHalData->para_file_buf;
++		for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
++			if (!IsCommentString(szLine)) {
++				/* Get 1st hex value as register offset */
++				if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
++					if (u4bRegOffset == 0xffff) {
++						/* Ending. */
++						break;
++					}
++
++					/* Get 2nd hex value as register value. */
++					szLine += u4bMove;
++					if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove))
++						rtw_write8(Adapter, u4bRegOffset, (u8)u4bRegValue);
++				}
++			}
++		}
++	} else
++		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
++
++	return rtStatus;
++}
++
++int
++phy_ConfigBBWithParaFile(
++		PADAPTER	Adapter,
++		char		*pFileName,
++		u32			ConfigType
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++	int	rlen = 0, rtStatus = _FAIL;
++	char	*szLine, *ptmp;
++	u32	u4bRegOffset, u4bRegValue, u4bMove;
++	char	*pBuf = NULL;
++	u32	*pBufLen = NULL;
++
++	if (!(Adapter->registrypriv.load_phy_file & LOAD_BB_PARA_FILE))
++		return rtStatus;
++
++	switch (ConfigType) {
++	case CONFIG_BB_PHY_REG:
++		pBuf = pHalData->bb_phy_reg;
++		pBufLen = &pHalData->bb_phy_reg_len;
++		break;
++	case CONFIG_BB_AGC_TAB:
++		pBuf = pHalData->bb_agc_tab;
++		pBufLen = &pHalData->bb_agc_tab_len;
++		break;
++	default:
++		RTW_INFO("Unknown ConfigType!! %d\r\n", ConfigType);
++		break;
++	}
++
++	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
++
++	if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) {
++		rtw_get_phy_file_path(Adapter, pFileName);
++		if (rtw_readable_file_sz_chk(rtw_phy_para_file_path, 
++			MAX_PARA_FILE_BUF_LEN) == _TRUE) {
++			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
++			if (rlen > 0) {
++				rtStatus = _SUCCESS;
++				pBuf = rtw_zvmalloc(rlen);
++				if (pBuf) {
++					_rtw_memcpy(pBuf, pHalData->para_file_buf, rlen);
++					*pBufLen = rlen;
++
++					switch (ConfigType) {
++					case CONFIG_BB_PHY_REG:
++						pHalData->bb_phy_reg = pBuf;
++						break;
++					case CONFIG_BB_AGC_TAB:
++						pHalData->bb_agc_tab = pBuf;
++						break;
++					}
++				} else
++					RTW_INFO("%s(): ConfigType %d  alloc fail !\n", __FUNCTION__, ConfigType);
++			}
++		}
++	} else {
++		if ((pBufLen != NULL) && (*pBufLen != 0) && (pBuf != NULL)) {
++			_rtw_memcpy(pHalData->para_file_buf, pBuf, *pBufLen);
++			rtStatus = _SUCCESS;
++		} else
++			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
++	}
++
++	if (rtStatus == _SUCCESS) {
++		ptmp = pHalData->para_file_buf;
++		for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
++			if (!IsCommentString(szLine)) {
++				/* Get 1st hex value as register offset. */
++				if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
++					if (u4bRegOffset == 0xffff) {
++						/* Ending. */
++						break;
++					} else if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {
++#ifdef CONFIG_LONG_DELAY_ISSUE
++						rtw_msleep_os(50);
++#else
++						rtw_mdelay_os(50);
++#endif
++					} else if (u4bRegOffset == 0xfd)
++						rtw_mdelay_os(5);
++					else if (u4bRegOffset == 0xfc)
++						rtw_mdelay_os(1);
++					else if (u4bRegOffset == 0xfb)
++						rtw_udelay_os(50);
++					else if (u4bRegOffset == 0xfa)
++						rtw_udelay_os(5);
++					else if (u4bRegOffset == 0xf9)
++						rtw_udelay_os(1);
++
++					/* Get 2nd hex value as register value. */
++					szLine += u4bMove;
++					if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
++						/* RTW_INFO("[BB-ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue); */
++						phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
++
++						if (u4bRegOffset == 0xa24)
++							pHalData->odmpriv.rf_calibrate_info.rega24 = u4bRegValue;
++
++						/* Add 1us delay between BB/RF register setting. */
++						rtw_udelay_os(1);
++					}
++				}
++			}
++		}
++	} else
++		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
++
++	return rtStatus;
++}
++
++void
++phy_DecryptBBPgParaFile(
++	PADAPTER		Adapter,
++	char			*buffer
++)
++{
++	u32	i = 0, j = 0;
++	u8	map[95] = {0};
++	u8	currentChar;
++	char	*BufOfLines, *ptmp;
++
++	/* RTW_INFO("=====>phy_DecryptBBPgParaFile()\n"); */
++	/* 32 the ascii code of the first visable char, 126 the last one */
++	for (i = 0; i < 95; ++i)
++		map[i] = (u8)(94 - i);
++
++	ptmp = buffer;
++	i = 0;
++	for (BufOfLines = GetLineFromBuffer(ptmp); BufOfLines != NULL; BufOfLines = GetLineFromBuffer(ptmp)) {
++		/* RTW_INFO("Encrypted Line: %s\n", BufOfLines); */
++
++		for (j = 0; j < strlen(BufOfLines); ++j) {
++			currentChar = BufOfLines[j];
++
++			if (currentChar == '\0')
++				break;
++
++			currentChar -= (u8)((((i + j) * 3) % 128));
++
++			BufOfLines[j] = map[currentChar - 32] + 32;
++		}
++		/* RTW_INFO("Decrypted Line: %s\n", BufOfLines ); */
++		if (strlen(BufOfLines) != 0)
++			i++;
++		BufOfLines[strlen(BufOfLines)] = '\n';
++	}
++}
++
++#ifndef DBG_TXPWR_BY_RATE_FILE_PARSE
++#define DBG_TXPWR_BY_RATE_FILE_PARSE 0
++#endif
++
++int
++phy_ParseBBPgParaFile(
++	PADAPTER		Adapter,
++	char			*buffer
++)
++{
++	int	rtStatus = _FAIL;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
++	char	*szLine, *ptmp;
++	u32	u4bRegOffset, u4bRegMask;
++	u32	u4bMove;
++	BOOLEAN firstLine = _TRUE;
++	u8	tx_num = 0;
++	u8	band = 0, rf_path = 0;
++
++	if (Adapter->registrypriv.RegDecryptCustomFile == 1)
++		phy_DecryptBBPgParaFile(Adapter, buffer);
++
++	ptmp = buffer;
++	for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
++		if (isAllSpaceOrTab(szLine, sizeof(*szLine)))
++			continue;
++
++		if (!IsCommentString(szLine)) {
++			/* Get header info (relative value or exact value) */
++			if (firstLine) {
++				if (strncmp(szLine, "#[v1]", 5) == 0
++					|| strncmp(szLine, "#[v2]", 5) == 0)
++					pHalData->odmpriv.phy_reg_pg_version = szLine[3] - '0';
++				else {
++					RTW_ERR("The format in PHY_REG_PG are invalid %s\n", szLine);
++					goto exit;
++				}
++
++				if (strncmp(szLine + 5, "[Exact]#", 8) == 0) {
++					pHalData->odmpriv.phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
++					firstLine = _FALSE;
++					continue;
++				} else {
++					RTW_ERR("The values in PHY_REG_PG are invalid %s\n", szLine);
++					goto exit;
++				}
++			}
++
++			if (pHalData->odmpriv.phy_reg_pg_version > 0) {
++				u32	index = 0;
++
++				if (strncmp(szLine, "0xffff", 6) == 0)
++					break;
++
++				if (strncmp(szLine, "#[END]#", 7)) {
++					/* load the table label info */
++					if (szLine[0] == '#') {
++						index = 0;
++						if (strncmp(szLine, "#[2.4G]", 7) == 0) {
++							band = BAND_ON_2_4G;
++							index += 8;
++						} else if (strncmp(szLine, "#[5G]", 5) == 0) {
++							band = BAND_ON_5G;
++							index += 6;
++						} else {
++							RTW_ERR("Invalid band %s in PHY_REG_PG.txt\n", szLine);
++							goto exit;
++						}
++
++						rf_path = szLine[index] - 'A';
++						if (DBG_TXPWR_BY_RATE_FILE_PARSE)
++							RTW_INFO(" Table label Band %d, RfPath %d\n", band, rf_path );
++					} else { /* load rows of tables */
++						if (szLine[1] == '1')
++							tx_num = RF_1TX;
++						else if (szLine[1] == '2')
++							tx_num = RF_2TX;
++						else if (szLine[1] == '3')
++							tx_num = RF_3TX;
++						else if (szLine[1] == '4')
++							tx_num = RF_4TX;
++						else {
++							RTW_ERR("Invalid row in PHY_REG_PG.txt '%c'(%d)\n", szLine[1], szLine[1]);
++							goto exit;
++						}
++
++						while (szLine[index] != ']')
++							++index;
++						++index;/* skip ] */
++
++						/* Get 2nd hex value as register offset. */
++						szLine += index;
++						if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove))
++							szLine += u4bMove;
++						else
++							goto exit;
++
++						/* Get 2nd hex value as register mask. */
++						if (GetHexValueFromString(szLine, &u4bRegMask, &u4bMove))
++							szLine += u4bMove;
++						else
++							goto exit;
++
++						if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_EXACT_VALUE) {
++							u32	combineValue = 0;
++							u8	integer = 0, fraction = 0;
++
++							if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
++								szLine += u4bMove;
++							else
++								goto exit;
++
++							integer *= hal_spec->txgi_pdbm;
++							integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
++							if (pHalData->odmpriv.phy_reg_pg_version == 1)
++								combineValue |= (((integer / 10) << 4) + (integer % 10));
++							else
++								combineValue |= integer;
++
++							if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
++								szLine += u4bMove;
++							else
++								goto exit;
++
++							integer *= hal_spec->txgi_pdbm;
++							integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
++							combineValue <<= 8;
++							if (pHalData->odmpriv.phy_reg_pg_version == 1)
++								combineValue |= (((integer / 10) << 4) + (integer % 10));
++							else
++								combineValue |= integer;
++
++							if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
++								szLine += u4bMove;
++							else
++								goto exit;
++
++							integer *= hal_spec->txgi_pdbm;
++							integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
++							combineValue <<= 8;
++							if (pHalData->odmpriv.phy_reg_pg_version == 1)
++								combineValue |= (((integer / 10) << 4) + (integer % 10));
++							else
++								combineValue |= integer;
++
++							if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
++								szLine += u4bMove;
++							else
++								goto exit;
++
++							integer *= hal_spec->txgi_pdbm;
++							integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
++							combineValue <<= 8;
++							if (pHalData->odmpriv.phy_reg_pg_version == 1)
++								combineValue |= (((integer / 10) << 4) + (integer % 10));
++							else
++								combineValue |= integer;
++
++							phy_store_tx_power_by_rate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, combineValue);
++
++							if (DBG_TXPWR_BY_RATE_FILE_PARSE)
++								RTW_INFO("addr:0x%3x mask:0x%08x %dTx = 0x%08x\n", u4bRegOffset, u4bRegMask, tx_num + 1, combineValue);
++						}
++					}
++				}
++			}
++		}
++	}
++
++	rtStatus = _SUCCESS;
++
++exit:
++	RTW_INFO("%s return %d\n", __func__, rtStatus);
++	return rtStatus;
++}
++
++int
++phy_ConfigBBWithPgParaFile(
++		PADAPTER	Adapter,
++		const char	*pFileName)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++	int	rlen = 0, rtStatus = _FAIL;
++
++	if (!(Adapter->registrypriv.load_phy_file & LOAD_BB_PG_PARA_FILE))
++		return rtStatus;
++
++	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
++
++	if (pHalData->bb_phy_reg_pg == NULL) {
++		rtw_get_phy_file_path(Adapter, pFileName);
++		if (rtw_readable_file_sz_chk(rtw_phy_para_file_path, 
++			MAX_PARA_FILE_BUF_LEN) == _TRUE) {
++			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
++			if (rlen > 0) {
++				rtStatus = _SUCCESS;
++				pHalData->bb_phy_reg_pg = rtw_zvmalloc(rlen);
++				if (pHalData->bb_phy_reg_pg) {
++					_rtw_memcpy(pHalData->bb_phy_reg_pg, pHalData->para_file_buf, rlen);
++					pHalData->bb_phy_reg_pg_len = rlen;
++				} else
++					RTW_INFO("%s bb_phy_reg_pg alloc fail !\n", __FUNCTION__);
++			}
++		}
++	} else {
++		if ((pHalData->bb_phy_reg_pg_len != 0) && (pHalData->bb_phy_reg_pg != NULL)) {
++			_rtw_memcpy(pHalData->para_file_buf, pHalData->bb_phy_reg_pg, pHalData->bb_phy_reg_pg_len);
++			rtStatus = _SUCCESS;
++		} else
++			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
++	}
++
++	if (rtStatus == _SUCCESS) {
++		/* RTW_INFO("phy_ConfigBBWithPgParaFile(): read %s ok\n", pFileName); */
++		rtStatus = phy_ParseBBPgParaFile(Adapter, pHalData->para_file_buf);
++	} else
++		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
++
++	return rtStatus;
++}
++
++#if (MP_DRIVER == 1)
++
++int
++phy_ConfigBBWithMpParaFile(
++		PADAPTER	Adapter,
++		char		*pFileName
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++	int	rlen = 0, rtStatus = _FAIL;
++	char	*szLine, *ptmp;
++	u32	u4bRegOffset, u4bRegValue, u4bMove;
++
++	if (!(Adapter->registrypriv.load_phy_file & LOAD_BB_MP_PARA_FILE))
++		return rtStatus;
++
++	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
++
++	if ((pHalData->bb_phy_reg_mp_len == 0) && (pHalData->bb_phy_reg_mp == NULL)) {
++		rtw_get_phy_file_path(Adapter, pFileName);
++		if (rtw_readable_file_sz_chk(rtw_phy_para_file_path, 
++			MAX_PARA_FILE_BUF_LEN) == _TRUE) {
++			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
++			if (rlen > 0) {
++				rtStatus = _SUCCESS;
++				pHalData->bb_phy_reg_mp = rtw_zvmalloc(rlen);
++				if (pHalData->bb_phy_reg_mp) {
++					_rtw_memcpy(pHalData->bb_phy_reg_mp, pHalData->para_file_buf, rlen);
++					pHalData->bb_phy_reg_mp_len = rlen;
++				} else
++					RTW_INFO("%s bb_phy_reg_mp alloc fail !\n", __FUNCTION__);
++			}
++		}
++	} else {
++		if ((pHalData->bb_phy_reg_mp_len != 0) && (pHalData->bb_phy_reg_mp != NULL)) {
++			_rtw_memcpy(pHalData->para_file_buf, pHalData->bb_phy_reg_mp, pHalData->bb_phy_reg_mp_len);
++			rtStatus = _SUCCESS;
++		} else
++			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
++	}
++
++	if (rtStatus == _SUCCESS) {
++		/* RTW_INFO("phy_ConfigBBWithMpParaFile(): read %s ok\n", pFileName); */
++
++		ptmp = pHalData->para_file_buf;
++		for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
++			if (!IsCommentString(szLine)) {
++				/* Get 1st hex value as register offset. */
++				if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
++					if (u4bRegOffset == 0xffff) {
++						/* Ending. */
++						break;
++					} else if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {
++#ifdef CONFIG_LONG_DELAY_ISSUE
++						rtw_msleep_os(50);
++#else
++						rtw_mdelay_os(50);
++#endif
++					} else if (u4bRegOffset == 0xfd)
++						rtw_mdelay_os(5);
++					else if (u4bRegOffset == 0xfc)
++						rtw_mdelay_os(1);
++					else if (u4bRegOffset == 0xfb)
++						rtw_udelay_os(50);
++					else if (u4bRegOffset == 0xfa)
++						rtw_udelay_os(5);
++					else if (u4bRegOffset == 0xf9)
++						rtw_udelay_os(1);
++
++					/* Get 2nd hex value as register value. */
++					szLine += u4bMove;
++					if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
++						/* RTW_INFO("[ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue); */
++						phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
++
++						/* Add 1us delay between BB/RF register setting. */
++						rtw_udelay_os(1);
++					}
++				}
++			}
++		}
++	} else
++		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
++
++	return rtStatus;
++}
++
++#endif
++
++int
++PHY_ConfigRFWithParaFile(
++		PADAPTER	Adapter,
++		char		*pFileName,
++		enum rf_path		eRFPath
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++	int	rlen = 0, rtStatus = _FAIL;
++	char	*szLine, *ptmp;
++	u32	u4bRegOffset, u4bRegValue, u4bMove;
++	u16	i;
++	char	*pBuf = NULL;
++	u32	*pBufLen = NULL;
++
++	if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_PARA_FILE))
++		return rtStatus;
++
++	switch (eRFPath) {
++	case RF_PATH_A:
++		pBuf = pHalData->rf_radio_a;
++		pBufLen = &pHalData->rf_radio_a_len;
++		break;
++	case RF_PATH_B:
++		pBuf = pHalData->rf_radio_b;
++		pBufLen = &pHalData->rf_radio_b_len;
++		break;
++	default:
++		RTW_INFO("Unknown RF path!! %d\r\n", eRFPath);
++		break;
++	}
++
++	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
++
++	if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) {
++		rtw_get_phy_file_path(Adapter, pFileName);
++		if (rtw_readable_file_sz_chk(rtw_phy_para_file_path, 
++			MAX_PARA_FILE_BUF_LEN) == _TRUE) {
++			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
++			if (rlen > 0) {
++				rtStatus = _SUCCESS;
++				pBuf = rtw_zvmalloc(rlen);
++				if (pBuf) {
++					_rtw_memcpy(pBuf, pHalData->para_file_buf, rlen);
++					*pBufLen = rlen;
++
++					switch (eRFPath) {
++					case RF_PATH_A:
++						pHalData->rf_radio_a = pBuf;
++						break;
++					case RF_PATH_B:
++						pHalData->rf_radio_b = pBuf;
++						break;
++					default:
++						RTW_INFO("Unknown RF path!! %d\r\n", eRFPath);
++						break;
++					}
++				} else
++					RTW_INFO("%s(): eRFPath=%d  alloc fail !\n", __FUNCTION__, eRFPath);
++			}
++		}
++	} else {
++		if ((pBufLen != NULL) && (*pBufLen != 0) && (pBuf != NULL)) {
++			_rtw_memcpy(pHalData->para_file_buf, pBuf, *pBufLen);
++			rtStatus = _SUCCESS;
++		} else
++			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
++	}
++
++	if (rtStatus == _SUCCESS) {
++		/* RTW_INFO("%s(): read %s successfully\n", __FUNCTION__, pFileName); */
++
++		ptmp = pHalData->para_file_buf;
++		for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
++			if (!IsCommentString(szLine)) {
++				/* Get 1st hex value as register offset. */
++				if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
++					if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {
++						/* Deay specific ms. Only RF configuration require delay.												 */
++#ifdef CONFIG_LONG_DELAY_ISSUE
++						rtw_msleep_os(50);
++#else
++						rtw_mdelay_os(50);
++#endif
++					} else if (u4bRegOffset == 0xfd) {
++						/* delay_ms(5); */
++						for (i = 0; i < 100; i++)
++							rtw_udelay_os(MAX_STALL_TIME);
++					} else if (u4bRegOffset == 0xfc) {
++						/* delay_ms(1); */
++						for (i = 0; i < 20; i++)
++							rtw_udelay_os(MAX_STALL_TIME);
++					} else if (u4bRegOffset == 0xfb)
++						rtw_udelay_os(50);
++					else if (u4bRegOffset == 0xfa)
++						rtw_udelay_os(5);
++					else if (u4bRegOffset == 0xf9)
++						rtw_udelay_os(1);
++					else if (u4bRegOffset == 0xffff)
++						break;
++
++					/* Get 2nd hex value as register value. */
++					szLine += u4bMove;
++					if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
++						phy_set_rf_reg(Adapter, eRFPath, u4bRegOffset, bRFRegOffsetMask, u4bRegValue);
++
++						/* Temp add, for frequency lock, if no delay, that may cause */
++						/* frequency shift, ex: 2412MHz => 2417MHz */
++						/* If frequency shift, the following action may works. */
++						/* Fractional-N table in radio_a.txt */
++						/* 0x2a 0x00001		 */ /* channel 1 */
++						/* 0x2b 0x00808		frequency divider. */
++						/* 0x2b 0x53333 */
++						/* 0x2c 0x0000c */
++						rtw_udelay_os(1);
++					}
++				}
++			}
++		}
++	} else
++		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
++
++	return rtStatus;
++}
++
++void
++initDeltaSwingIndexTables(
++	PADAPTER	Adapter,
++	char		*Band,
++	char		*Path,
++	char		*Sign,
++	char		*Channel,
++	char		*Rate,
++	char		*Data
++)
++{
++#define STR_EQUAL_5G(_band, _path, _sign, _rate, _chnl) \
++	((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\
++	 (strcmp(Rate, _rate) == 0) && (strcmp(Channel, _chnl) == 0)\
++	)
++#define STR_EQUAL_2G(_band, _path, _sign, _rate) \
++	((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\
++	 (strcmp(Rate, _rate) == 0)\
++	)
++
++#define STORE_SWING_TABLE(_array, _iteratedIdx) \
++	do {	\
++	for (token = strsep(&Data, delim); token != NULL; token = strsep(&Data, delim)) {\
++		sscanf(token, "%d", &idx);\
++		_array[_iteratedIdx++] = (u8)idx;\
++	} } while (0)\
++
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
++	struct dm_rf_calibration_struct	*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
++	u32	j = 0;
++	char	*token;
++	char	delim[] = ",";
++	u32	idx = 0;
++
++	/* RTW_INFO("===>initDeltaSwingIndexTables(): Band: %s;\nPath: %s;\nSign: %s;\nChannel: %s;\nRate: %s;\n, Data: %s;\n",  */
++	/*	Band, Path, Sign, Channel, Rate, Data); */
++
++	if (STR_EQUAL_2G("2G", "A", "+", "CCK"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p, j);
++	else if (STR_EQUAL_2G("2G", "A", "-", "CCK"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n, j);
++	else if (STR_EQUAL_2G("2G", "B", "+", "CCK"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p, j);
++	else if (STR_EQUAL_2G("2G", "B", "-", "CCK"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n, j);
++	else if (STR_EQUAL_2G("2G", "A", "+", "ALL"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_p, j);
++	else if (STR_EQUAL_2G("2G", "A", "-", "ALL"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_n, j);
++	else if (STR_EQUAL_2G("2G", "B", "+", "ALL"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_p, j);
++	else if (STR_EQUAL_2G("2G", "B", "-", "ALL"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_n, j);
++	else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "0"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[0], j);
++	else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "0"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[0], j);
++	else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "0"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[0], j);
++	else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "0"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[0], j);
++	else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "1"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[1], j);
++	else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "1"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[1], j);
++	else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "1"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[1], j);
++	else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "1"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[1], j);
++	else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "2"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[2], j);
++	else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "2"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[2], j);
++	else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "2"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[2], j);
++	else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "2"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[2], j);
++	else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "3"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[3], j);
++	else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "3"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[3], j);
++	else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "3"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[3], j);
++	else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "3"))
++		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[3], j);
++	else
++		RTW_INFO("===>initDeltaSwingIndexTables(): The input is invalid!!\n");
++}
++
++int
++PHY_ConfigRFWithTxPwrTrackParaFile(
++		PADAPTER		Adapter,
++		char			*pFileName
++)
++{
++	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
++	struct dm_struct			*pDM_Odm = &pHalData->odmpriv;
++	int	rlen = 0, rtStatus = _FAIL;
++	char	*szLine, *ptmp;
++	u32	i = 0;
++
++	if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_TXPWR_TRACK_PARA_FILE))
++		return rtStatus;
++
++	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
++
++	if ((pHalData->rf_tx_pwr_track_len == 0) && (pHalData->rf_tx_pwr_track == NULL)) {
++		rtw_get_phy_file_path(Adapter, pFileName);
++		if (rtw_readable_file_sz_chk(rtw_phy_para_file_path, 
++			MAX_PARA_FILE_BUF_LEN) == _TRUE) {
++			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
++			if (rlen > 0) {
++				rtStatus = _SUCCESS;
++				pHalData->rf_tx_pwr_track = rtw_zvmalloc(rlen);
++				if (pHalData->rf_tx_pwr_track) {
++					_rtw_memcpy(pHalData->rf_tx_pwr_track, pHalData->para_file_buf, rlen);
++					pHalData->rf_tx_pwr_track_len = rlen;
++				} else
++					RTW_INFO("%s rf_tx_pwr_track alloc fail !\n", __FUNCTION__);
++			}
++		}
++	} else {
++		if ((pHalData->rf_tx_pwr_track_len != 0) && (pHalData->rf_tx_pwr_track != NULL)) {
++			_rtw_memcpy(pHalData->para_file_buf, pHalData->rf_tx_pwr_track, pHalData->rf_tx_pwr_track_len);
++			rtStatus = _SUCCESS;
++		} else
++			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
++	}
++
++	if (rtStatus == _SUCCESS) {
++		/* RTW_INFO("%s(): read %s successfully\n", __FUNCTION__, pFileName); */
++
++		ptmp = pHalData->para_file_buf;
++		for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
++			if (!IsCommentString(szLine)) {
++				char	band[5] = "", path[5] = "", sign[5]  = "";
++				char	chnl[5] = "", rate[10] = "";
++				char	data[300] = ""; /* 100 is too small */
++
++				if (strlen(szLine) < 10 || szLine[0] != '[')
++					continue;
++
++				strncpy(band, szLine + 1, 2);
++				strncpy(path, szLine + 5, 1);
++				strncpy(sign, szLine + 8, 1);
++
++				i = 10; /* szLine+10 */
++				if (!ParseQualifiedString(szLine, &i, rate, '[', ']')) {
++					/* RTW_INFO("Fail to parse rate!\n"); */
++				}
++				if (!ParseQualifiedString(szLine, &i, chnl, '[', ']')) {
++					/* RTW_INFO("Fail to parse channel group!\n"); */
++				}
++				while (szLine[i] != '{' && i < strlen(szLine))
++					i++;
++				if (!ParseQualifiedString(szLine, &i, data, '{', '}')) {
++					/* RTW_INFO("Fail to parse data!\n"); */
++				}
++
++				initDeltaSwingIndexTables(Adapter, band, path, sign, chnl, rate, data);
++			}
++		}
++	} else
++		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
++#if 0
++	for (i = 0; i < DELTA_SWINGIDX_SIZE; ++i) {
++		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2ga_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2ga_p[i]);
++		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2ga_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2ga_n[i]);
++		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2gb_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2gb_p[i]);
++		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2gb_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2gb_n[i]);
++		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p[i]);
++		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n[i]);
++		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p[i]);
++		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n[i]);
++
++		for (j = 0; j < 3; ++j) {
++			RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5ga_p[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5ga_p[j][i]);
++			RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5ga_n[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5ga_n[j][i]);
++			RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5gb_p[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5gb_p[j][i]);
++			RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5gb_n[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5gb_n[j][i]);
++		}
++	}
++#endif
++	return rtStatus;
++}
++
++#if CONFIG_TXPWR_LIMIT
++
++#ifndef DBG_TXPWR_LMT_FILE_PARSE
++#define DBG_TXPWR_LMT_FILE_PARSE 0
++#endif
++
++#define PARSE_RET_NO_HDL	0
++#define PARSE_RET_SUCCESS	1
++#define PARSE_RET_FAIL		2
++
++/*
++* @@Ver=2.0
++* or
++* @@DomainCode=0x28, Regulation=C6
++* or
++* @@CountryCode=GB, Regulation=C7
++*/
++static u8 parse_reg_exc_config(_adapter *adapter, char *szLine)
++{
++#define VER_PREFIX "Ver="
++#define DOMAIN_PREFIX "DomainCode=0x"
++#define COUNTRY_PREFIX "CountryCode="
++#define REG_PREFIX "Regulation="
++
++	const u8 ver_prefix_len = strlen(VER_PREFIX);
++	const u8 domain_prefix_len = strlen(DOMAIN_PREFIX);
++	const u8 country_prefix_len = strlen(COUNTRY_PREFIX);
++	const u8 reg_prefix_len = strlen(REG_PREFIX);
++	u32 i, i_val_s, i_val_e;
++	u32 j;
++	u8 domain = 0xFF;
++	char *country = NULL;
++	u8 parse_reg = 0;
++
++	if (szLine[0] != '@' || szLine[1] != '@')
++		return PARSE_RET_NO_HDL;
++
++	i = 2;
++	if (strncmp(szLine + i, VER_PREFIX, ver_prefix_len) == 0)
++		; /* nothing to do */
++	else if (strncmp(szLine + i, DOMAIN_PREFIX, domain_prefix_len) == 0) {
++		/* get string after domain prefix to ',' */
++		i += domain_prefix_len;
++		i_val_s = i;
++		while (szLine[i] != ',') {
++			if (szLine[i] == '\0')
++				return PARSE_RET_FAIL;
++			i++;
++		}
++		i_val_e = i;
++
++		/* check if all hex */
++		for (j = i_val_s; j < i_val_e; j++)
++			if (IsHexDigit(szLine[j]) == _FALSE)
++				return PARSE_RET_FAIL;
++
++		/* get value from hex string */
++		if (sscanf(szLine + i_val_s, "%hhx", &domain) != 1)
++			return PARSE_RET_FAIL;
++
++		parse_reg = 1;
++	} else if (strncmp(szLine + i, COUNTRY_PREFIX, country_prefix_len) == 0) {
++		/* get string after country prefix to ',' */
++		i += country_prefix_len;
++		i_val_s = i;
++		while (szLine[i] != ',') {
++			if (szLine[i] == '\0')
++				return PARSE_RET_FAIL;
++			i++;
++		}
++		i_val_e = i;
++
++		if (i_val_e - i_val_s != 2)
++			return PARSE_RET_FAIL;
++
++		/* check if all alpha */
++		for (j = i_val_s; j < i_val_e; j++)
++			if (is_alpha(szLine[j]) == _FALSE)
++				return PARSE_RET_FAIL;
++
++		country = szLine + i_val_s;
++
++		parse_reg = 1;
++
++	} else
++		return PARSE_RET_FAIL;
++
++	if (parse_reg) {
++		/* move to 'R' */
++		while (szLine[i] != 'R') {
++			if (szLine[i] == '\0')
++				return PARSE_RET_FAIL;
++			i++;
++		}
++
++		/* check if matching regulation prefix */
++		if (strncmp(szLine + i, REG_PREFIX, reg_prefix_len) != 0)
++			return PARSE_RET_FAIL;
++
++		/* get string after regulation prefix ending with space */
++		i += reg_prefix_len;
++		i_val_s = i;
++		while (szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0')
++			i++;
++
++		if (i == i_val_s)
++			return PARSE_RET_FAIL;
++
++		rtw_regd_exc_add_with_nlen(adapter_to_rfctl(adapter), country, domain, szLine + i_val_s, i - i_val_s);
++	}
++
++	return PARSE_RET_SUCCESS;
++}
++
++static int
++phy_ParsePowerLimitTableFile(
++	PADAPTER		Adapter,
++	char			*buffer
++)
++{
++#define LD_STAGE_EXC_MAPPING	0
++#define LD_STAGE_TAB_DEFINE		1
++#define LD_STAGE_TAB_START		2
++#define LD_STAGE_COLUMN_DEFINE	3
++#define LD_STAGE_CH_ROW			4
++
++	int	rtStatus = _FAIL;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
++	struct dm_struct	*pDM_Odm = &(pHalData->odmpriv);
++	u8	loadingStage = LD_STAGE_EXC_MAPPING;
++	u32	i = 0, forCnt = 0;
++	char	*szLine, *ptmp;
++	char band[10], bandwidth[10], rateSection[10], ntx[10], colNumBuf[10];
++	char **regulation = NULL;
++	u8	colNum = 0;
++
++	if (Adapter->registrypriv.RegDecryptCustomFile == 1)
++		phy_DecryptBBPgParaFile(Adapter, buffer);
++
++	ptmp = buffer;
++	for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
++		if (isAllSpaceOrTab(szLine, sizeof(*szLine)))
++			continue;
++		if (IsCommentString(szLine))
++			continue;
++
++		if (loadingStage == LD_STAGE_EXC_MAPPING) {
++			if (szLine[0] == '#' || szLine[1] == '#') {
++				loadingStage = LD_STAGE_TAB_DEFINE;
++				if (DBG_TXPWR_LMT_FILE_PARSE)
++					dump_regd_exc_list(RTW_DBGDUMP, adapter_to_rfctl(Adapter));
++			} else {
++				if (parse_reg_exc_config(Adapter, szLine) == PARSE_RET_FAIL) {
++					RTW_ERR("Fail to parse regulation exception ruls!\n");
++					goto exit;
++				}
++				continue;
++			}
++		}
++
++		if (loadingStage == LD_STAGE_TAB_DEFINE) {
++			/* read "##	2.4G, 20M, 1T, CCK" */
++			if (szLine[0] != '#' || szLine[1] != '#')
++				continue;
++
++			/* skip the space */
++			i = 2;
++			while (szLine[i] == ' ' || szLine[i] == '\t')
++				++i;
++
++			szLine[--i] = ' '; /* return the space in front of the regulation info */
++
++			/* Parse the label of the table */
++			_rtw_memset((void *) band, 0, 10);
++			_rtw_memset((void *) bandwidth, 0, 10);
++			_rtw_memset((void *) ntx, 0, 10);
++			_rtw_memset((void *) rateSection, 0, 10);
++			if (!ParseQualifiedString(szLine, &i, band, ' ', ',')) {
++				RTW_ERR("Fail to parse band!\n");
++				goto exit;
++			}
++			if (!ParseQualifiedString(szLine, &i, bandwidth, ' ', ',')) {
++				RTW_ERR("Fail to parse bandwidth!\n");
++				goto exit;
++			}
++			if (!ParseQualifiedString(szLine, &i, ntx, ' ', ',')) {
++				RTW_ERR("Fail to parse ntx!\n");
++				goto exit;
++			}
++			if (!ParseQualifiedString(szLine, &i, rateSection, ' ', ',')) {
++				RTW_ERR("Fail to parse rate!\n");
++				goto exit;
++			}
++
++			loadingStage = LD_STAGE_TAB_START;
++		} else if (loadingStage == LD_STAGE_TAB_START) {
++			/* read "##	START" */
++			if (szLine[0] != '#' || szLine[1] != '#')
++				continue;
++
++			/* skip the space */
++			i = 2;
++			while (szLine[i] == ' ' || szLine[i] == '\t')
++				++i;
++
++			if (strncmp((u8 *)(szLine + i), "START", 5)) {
++				RTW_ERR("Missing \"##   START\" label\n");
++				goto exit;
++			}
++
++			loadingStage = LD_STAGE_COLUMN_DEFINE;
++		} else if (loadingStage == LD_STAGE_COLUMN_DEFINE) {
++			/* read "##	#5#	FCC	ETSI	MKK	IC	KCC" */
++			if (szLine[0] != '#' || szLine[1] != '#')
++				continue;
++
++			/* skip the space */
++			i = 2;
++			while (szLine[i] == ' ' || szLine[i] == '\t')
++				++i;
++
++			_rtw_memset((void *) colNumBuf, 0, 10);
++			if (!ParseQualifiedString(szLine, &i, colNumBuf, '#', '#')) {
++				RTW_ERR("Fail to parse column number!\n");
++				goto exit;
++			}
++			if (!GetU1ByteIntegerFromStringInDecimal(colNumBuf, &colNum)) {
++				RTW_ERR("Column number \"%s\" is not unsigned decimal\n", colNumBuf);
++				goto exit;
++			}
++			if (colNum == 0) {
++				RTW_ERR("Column number is 0\n");
++				goto exit;
++			}
++
++			if (DBG_TXPWR_LMT_FILE_PARSE)
++				RTW_PRINT("[%s][%s][%s][%s] column num:%d\n", band, bandwidth, rateSection, ntx, colNum);
++
++			regulation = (char **)rtw_zmalloc(sizeof(char *) * colNum);
++			if (!regulation) {
++				RTW_ERR("Regulation alloc fail\n");
++				goto exit;
++			}
++
++			for (forCnt = 0; forCnt < colNum; ++forCnt) {
++				u32 i_ns;
++
++				/* skip the space */
++				while (szLine[i] == ' ' || szLine[i] == '\t')
++					i++;
++				i_ns = i;
++
++				while (szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0')
++					i++;
++
++				regulation[forCnt] = (char *)rtw_malloc(i - i_ns + 1);
++				if (!regulation[forCnt]) {
++					RTW_ERR("Regulation alloc fail\n");
++					goto exit;
++				}
++
++				_rtw_memcpy(regulation[forCnt], szLine + i_ns, i - i_ns);
++				regulation[forCnt][i - i_ns] = '\0';
++			}
++
++			if (DBG_TXPWR_LMT_FILE_PARSE) {
++				RTW_PRINT("column name:");
++				for (forCnt = 0; forCnt < colNum; ++forCnt)
++					_RTW_PRINT(" %s", regulation[forCnt]);
++				_RTW_PRINT("\n");
++			}
++
++			loadingStage = LD_STAGE_CH_ROW;
++		} else if (loadingStage == LD_STAGE_CH_ROW) {
++			char	channel[10] = {0}, powerLimit[10] = {0};
++			u8	cnt = 0;
++
++			/* the table ends */
++			if (szLine[0] == '#' && szLine[1] == '#') {
++				i = 2;
++				while (szLine[i] == ' ' || szLine[i] == '\t')
++					++i;
++
++				if (strncmp((u8 *)(szLine + i), "END", 3) == 0) {
++					loadingStage = LD_STAGE_TAB_DEFINE;
++					if (regulation) {
++						for (forCnt = 0; forCnt < colNum; ++forCnt) {
++							if (regulation[forCnt]) {
++								rtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1);
++								regulation[forCnt] = NULL;
++							}
++						}
++						rtw_mfree((u8 *)regulation, sizeof(char *) * colNum);
++						regulation = NULL;
++					}
++					colNum = 0;
++					continue;
++				} else {
++					RTW_ERR("Missing \"##   END\" label\n");
++					goto exit;
++				}
++			}
++
++			if ((szLine[0] != 'c' && szLine[0] != 'C') ||
++				(szLine[1] != 'h' && szLine[1] != 'H')
++			) {
++				RTW_WARN("Wrong channel prefix: '%c','%c'(%d,%d)\n", szLine[0], szLine[1], szLine[0], szLine[1]);
++				continue;
++			}
++			i = 2;/* move to the  location behind 'h' */
++
++			/* load the channel number */
++			cnt = 0;
++			while (szLine[i] >= '0' && szLine[i] <= '9') {
++				channel[cnt] = szLine[i];
++				++cnt;
++				++i;
++			}
++			/* RTW_INFO("chnl %s!\n", channel); */
++
++			for (forCnt = 0; forCnt < colNum; ++forCnt) {
++				/* skip the space between channel number and the power limit value */
++				while (szLine[i] == ' ' || szLine[i] == '\t')
++					++i;
++
++				/* load the power limit value */
++				_rtw_memset((void *) powerLimit, 0, 10);
++
++				if (szLine[i] == 'W' && szLine[i + 1] == 'W') {
++					/*
++					* case "WW" assign special ww value
++					* means to get minimal limit in other regulations at same channel
++					*/
++					s8 ww_value = phy_txpwr_ww_lmt_value(Adapter);
++
++					sprintf(powerLimit, "%d", ww_value);
++					i += 2;
++
++				} else if (szLine[i] == 'N' && szLine[i + 1] == 'A') {
++					/*
++					* case "NA" assign max txgi value
++					* means no limitation
++					*/
++					sprintf(powerLimit, "%d", hal_spec->txgi_max);
++					i += 2;
++
++				} else if ((szLine[i] >= '0' && szLine[i] <= '9') || szLine[i] == '.'
++					|| szLine[i] == '+' || szLine[i] == '-'
++				){
++					/* case of dBm value */
++					u8 integer = 0, fraction = 0, negative = 0;
++					u32 u4bMove;
++					s8 lmt = 0;
++
++					if (szLine[i] == '+' || szLine[i] == '-') {
++						if (szLine[i] == '-')
++							negative = 1;
++						i++;
++					}
++
++					if (GetFractionValueFromString(&szLine[i], &integer, &fraction, &u4bMove))
++						i += u4bMove;
++					else {
++						RTW_ERR("Limit \"%s\" is not valid decimal\n", &szLine[i]);
++						goto exit;
++					}
++
++					/* transform to string of value in unit of txgi */
++					lmt = integer * hal_spec->txgi_pdbm + ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
++					if (negative)
++						lmt = -lmt;
++					sprintf(powerLimit, "%d", lmt);
++
++				} else {
++					RTW_ERR("Wrong limit expression \"%c%c\"(%d, %d)\n"
++						, szLine[i], szLine[i + 1], szLine[i], szLine[i + 1]);
++					goto exit;
++				}
++
++				/* store the power limit value */
++				phy_set_tx_power_limit(pDM_Odm, (u8 *)regulation[forCnt], (u8 *)band,
++					(u8 *)bandwidth, (u8 *)rateSection, (u8 *)ntx, (u8 *)channel, (u8 *)powerLimit);
++
++			}
++		}
++	}
++
++	rtStatus = _SUCCESS;
++
++exit:
++	if (regulation) {
++		for (forCnt = 0; forCnt < colNum; ++forCnt) {
++			if (regulation[forCnt]) {
++				rtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1);
++				regulation[forCnt] = NULL;
++			}
++		}
++		rtw_mfree((u8 *)regulation, sizeof(char *) * colNum);
++		regulation = NULL;
++	}
++
++	RTW_INFO("%s return %d\n", __func__, rtStatus);
++	return rtStatus;
++}
++
++int
++PHY_ConfigRFWithPowerLimitTableParaFile(
++		PADAPTER	Adapter,
++		const char	*pFileName
++)
++{
++	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
++	int	rlen = 0, rtStatus = _FAIL;
++
++	if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_TXPWR_LMT_PARA_FILE))
++		return rtStatus;
++
++	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
++
++	if (pHalData->rf_tx_pwr_lmt == NULL) {
++		rtw_get_phy_file_path(Adapter, pFileName);
++		if (rtw_readable_file_sz_chk(rtw_phy_para_file_path, 
++			MAX_PARA_FILE_BUF_LEN) == _TRUE) {
++			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
++			if (rlen > 0) {
++				rtStatus = _SUCCESS;
++				pHalData->rf_tx_pwr_lmt = rtw_zvmalloc(rlen);
++				if (pHalData->rf_tx_pwr_lmt) {
++					_rtw_memcpy(pHalData->rf_tx_pwr_lmt, pHalData->para_file_buf, rlen);
++					pHalData->rf_tx_pwr_lmt_len = rlen;
++				} else
++					RTW_INFO("%s rf_tx_pwr_lmt alloc fail !\n", __FUNCTION__);
++			}
++		}
++	} else {
++		if ((pHalData->rf_tx_pwr_lmt_len != 0) && (pHalData->rf_tx_pwr_lmt != NULL)) {
++			_rtw_memcpy(pHalData->para_file_buf, pHalData->rf_tx_pwr_lmt, pHalData->rf_tx_pwr_lmt_len);
++			rtStatus = _SUCCESS;
++		} else
++			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
++	}
++
++	if (rtStatus == _SUCCESS) {
++		/* RTW_INFO("%s(): read %s ok\n", __FUNCTION__, pFileName); */
++		rtStatus = phy_ParsePowerLimitTableFile(Adapter, pHalData->para_file_buf);
++	} else
++		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
++
++	return rtStatus;
++}
++#endif /* CONFIG_TXPWR_LIMIT */
++
++void phy_free_filebuf_mask(_adapter *padapter, u8 mask)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++	if (pHalData->mac_reg && (mask & LOAD_MAC_PARA_FILE)) {
++		rtw_vmfree(pHalData->mac_reg, pHalData->mac_reg_len);
++		pHalData->mac_reg = NULL;
++	}
++	if (mask & LOAD_BB_PARA_FILE) {
++		if (pHalData->bb_phy_reg) {
++			rtw_vmfree(pHalData->bb_phy_reg, pHalData->bb_phy_reg_len);
++			pHalData->bb_phy_reg = NULL;
++		}
++		if (pHalData->bb_agc_tab) {
++			rtw_vmfree(pHalData->bb_agc_tab, pHalData->bb_agc_tab_len);
++			pHalData->bb_agc_tab = NULL;
++		}
++	}
++	if (pHalData->bb_phy_reg_pg && (mask & LOAD_BB_PG_PARA_FILE)) {
++		rtw_vmfree(pHalData->bb_phy_reg_pg, pHalData->bb_phy_reg_pg_len);
++		pHalData->bb_phy_reg_pg = NULL;
++	}
++	if (pHalData->bb_phy_reg_mp && (mask & LOAD_BB_MP_PARA_FILE)) {
++		rtw_vmfree(pHalData->bb_phy_reg_mp, pHalData->bb_phy_reg_mp_len);
++		pHalData->bb_phy_reg_mp = NULL;
++	}
++	if (mask & LOAD_RF_PARA_FILE) {
++		if (pHalData->rf_radio_a) {
++			rtw_vmfree(pHalData->rf_radio_a, pHalData->rf_radio_a_len);
++			pHalData->rf_radio_a = NULL;
++		}
++		if (pHalData->rf_radio_b) {
++			rtw_vmfree(pHalData->rf_radio_b, pHalData->rf_radio_b_len);
++			pHalData->rf_radio_b = NULL;
++		}
++	}
++	if (pHalData->rf_tx_pwr_track && (mask & LOAD_RF_TXPWR_TRACK_PARA_FILE)) {
++		rtw_vmfree(pHalData->rf_tx_pwr_track, pHalData->rf_tx_pwr_track_len);
++		pHalData->rf_tx_pwr_track = NULL;
++	}
++	if (pHalData->rf_tx_pwr_lmt && (mask & LOAD_RF_TXPWR_LMT_PARA_FILE)) {
++		rtw_vmfree(pHalData->rf_tx_pwr_lmt, pHalData->rf_tx_pwr_lmt_len);
++		pHalData->rf_tx_pwr_lmt = NULL;
++	}
++}
++
++inline void phy_free_filebuf(_adapter *padapter)
++{
++	phy_free_filebuf_mask(padapter, 0xFF);
++}
++
++#endif
++
++/*
++* check if user specified mbm is valid
++*/
++bool phy_is_txpwr_user_mbm_valid(_adapter *adapter, s16 mbm)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++
++	/* 1T upper bound check */
++	if (hal_spec->txgi_max <= mbm * hal_spec->txgi_pdbm / MBM_PDBM)
++		return 0;
++
++	return 1;
++}
++
++bool phy_is_txpwr_user_target_specified(_adapter *adapter)
++{
++	s16 total_mbm = UNSPECIFIED_MBM;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	total_mbm = rtw_cfg80211_dev_get_total_txpwr_target_mbm(adapter_to_dvobj(adapter));
++#endif
++
++	return total_mbm != UNSPECIFIED_MBM;
++}
++
++/*
++* Return value in unit of TX Gain Index
++* hal_spec.txgi_max means unspecified
++*/
++s8 phy_get_txpwr_user_target(_adapter *adapter, struct hal_spec_t *hal_spec, u8 ntx_idx)
++{
++	s16 total_mbm = UNSPECIFIED_MBM;
++	s8 target;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	total_mbm = rtw_cfg80211_dev_get_total_txpwr_target_mbm(adapter_to_dvobj(adapter));
++#endif
++	if (total_mbm != UNSPECIFIED_MBM)
++		target = (total_mbm - mb_of_ntx(ntx_idx + 1)) * hal_spec->txgi_pdbm / MBM_PDBM;
++	else
++		target = hal_spec->txgi_max;
++
++	return target;
++}
++
++/*
++* Return value in unit of TX Gain Index
++* hal_spec.txgi_max means unspecified
++*/
++s8 phy_get_txpwr_user_lmt(_adapter *adapter, struct hal_spec_t *hal_spec, u8 ntx_idx)
++{
++	s16 total_mbm = UNSPECIFIED_MBM;
++	s8 lmt;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	total_mbm = rtw_cfg80211_dev_get_total_txpwr_lmt_mbm(adapter_to_dvobj(adapter));
++#endif
++	if (total_mbm != UNSPECIFIED_MBM)
++		lmt = (total_mbm - mb_of_ntx(ntx_idx + 1)) * hal_spec->txgi_pdbm / MBM_PDBM;
++	else
++		lmt = hal_spec->txgi_max;
++
++	return lmt;
++}
++
++/*
++* Return value in unit of TX Gain Index
++*/
++s8 phy_get_txpwr_target(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate, u8 ntx_idx
++	, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch, struct txpwr_idx_comp *tic)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	s8 target, by_rate = 0, btc_diff = 0, extra = 0;
++	s8 lmt, utgt, ulmt;
++
++	lmt = utgt = ulmt = hal_spec->txgi_max;
++
++	if (band != BAND_ON_2_4G && IS_CCK_RATE(rate))
++		goto exit;
++
++	utgt = phy_get_txpwr_user_target(adapter, hal_spec, ntx_idx);
++	if (utgt != hal_spec->txgi_max)
++		goto get_lmt;
++
++#ifdef CONFIG_RTL8812A
++	if (IS_HARDWARE_TYPE_8812(adapter)
++		&& phy_get_txpwr_target_skip_by_rate_8812a(adapter, rate))
++		by_rate = phy_get_target_txpwr(adapter, band, rfpath, rs);
++	else
++#endif
++		by_rate = PHY_GetTxPowerByRate(adapter, band, rfpath, rs, rate);
++	if (by_rate == hal_spec->txgi_max)
++		by_rate = 0;
++
++#ifdef CONFIG_BT_COEXIST
++	if (hal_data->EEPROMBluetoothCoexist == _TRUE)
++		btc_diff = -(rtw_btcoex_query_reduced_wl_pwr_lvl(adapter) * hal_spec->txgi_pdbm);
++#endif
++
++	extra = rtw_hal_get_txpwr_target_extra_bias(adapter, rfpath, rs, rate, bw, band, cch);
++
++get_lmt:
++	lmt = phy_get_txpwr_lmt_sub_chs(adapter, NULL, band, bw, rfpath, rate, ntx_idx, cch, opch);
++	ulmt = phy_get_txpwr_user_lmt(adapter, hal_spec, ntx_idx);
++	/* TODO: limit from outer source, ex: 11d */
++
++exit:
++	if (utgt != hal_spec->txgi_max)
++		target = utgt;
++	else
++		target = by_rate + btc_diff + extra;
++
++	if (target > lmt)
++		target = lmt;
++	if (target > ulmt)
++		target = ulmt;
++
++	if (tic) {
++		tic->target = target;
++		if (utgt == hal_spec->txgi_max) {
++			tic->by_rate = by_rate;
++			tic->btc = btc_diff;
++			tic->extra = extra;
++		}
++		tic->utarget = utgt;
++		tic->limit = lmt;
++		tic->ulimit = ulmt;
++	}
++
++	return target;
++}
++
++/* TODO: common dpd_diff getting API from phydm */
++#ifdef CONFIG_RTL8822C
++#include "./rtl8822c/rtl8822c.h"
++#endif
++
++/*
++* Return in unit of TX Gain Index
++*/
++s8 phy_get_txpwr_amends(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate, u8 ntx_idx
++	, enum channel_width bw, BAND_TYPE band, u8 cch, struct txpwr_idx_comp *tic)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	s8 tpt_diff = 0, dpd_diff = 0, val = 0;
++
++	if (band != BAND_ON_2_4G && IS_CCK_RATE(rate))
++		goto exit;
++
++	if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8188GTV(adapter)
++		|| IS_HARDWARE_TYPE_8192E(adapter) || IS_HARDWARE_TYPE_8192F(adapter)
++		|| IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8703B(adapter) || IS_HARDWARE_TYPE_8723D(adapter)
++		|| IS_HARDWARE_TYPE_8710B(adapter)
++		|| IS_HARDWARE_TYPE_8821(adapter) || IS_HARDWARE_TYPE_8812(adapter)
++	)
++		tpt_diff = PHY_GetTxPowerTrackingOffset(adapter, rfpath, rate);
++
++#ifdef CONFIG_RTL8822C
++	if (IS_HARDWARE_TYPE_8822C(adapter))
++		dpd_diff = -(rtl8822c_get_dis_dpd_by_rate_diff(adapter, rate) * hal_spec->txgi_pdbm);
++#endif
++
++exit:
++	if (tic) {
++		tic->tpt = tpt_diff;
++		tic->dpd = dpd_diff;
++	}
++
++	return tpt_diff + dpd_diff;
++}
++
++#ifdef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
++s8 phy_get_tssi_txpwr_by_rate_ref(_adapter *adapter, enum rf_path path
++	, enum channel_width bw, u8 cch, u8 opch)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	u8 ntx_idx = phy_get_current_tx_num(adapter, MGN_MCS7);
++	BAND_TYPE band = cch > 14 ? BAND_ON_5G : BAND_ON_2_4G;
++	s8 pwr_idx;
++
++	pwr_idx = phy_get_txpwr_target(adapter, path, HT_1SS, MGN_MCS7
++		, ntx_idx, bw, band, cch, opch, NULL);
++	pwr_idx += phy_get_txpwr_amends(adapter, path, HT_1SS, MGN_MCS7
++		, ntx_idx, bw, band, cch, NULL);
++
++	return pwr_idx;
++}
++#endif
++
++/*
++ * Rteurn tx power index for rate
++ */
++u8 hal_com_get_txpwr_idx(_adapter *adapter, enum rf_path rfpath
++	, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch
++	, struct txpwr_idx_comp *tic)
++{
++	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	s16 power_idx = 0;
++	s8 base = 0;
++	s8 rate_target, rate_amends;
++	u8 ntx_idx = phy_get_current_tx_num(adapter, rate);
++
++	/* target */
++	rate_target = phy_get_txpwr_target(adapter, rfpath, rs, rate, ntx_idx, bw, band, cch, opch, tic);
++
++	/* amends */
++	rate_amends = phy_get_txpwr_amends(adapter, rfpath, rs, rate, ntx_idx, bw, band, cch, tic);
++
++	switch (hal->txpwr_pg_mode) {
++#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	case TXPWR_PG_WITH_PWR_IDX: {
++		/*
++		* power index = 
++		* 1. pg base (per rate section) +
++		* 2. target diff (per rate) to target of its rate section +
++		* 3. amends diff (per rate)
++		*/
++		u8 rs_target;
++
++		base = phy_get_pg_txpwr_idx(adapter, rfpath, rs, ntx_idx, bw, band, cch);
++		rs_target = phy_get_target_txpwr(adapter, band, rfpath, rs);
++		power_idx = base + (rate_target - rs_target) + (rate_amends);
++
++		if (tic) {
++			if (tic->utarget == hal_spec->txgi_max)
++				tic->by_rate -= rs_target;
++			else
++				tic->utarget -= rs_target;
++			if (tic->limit != hal_spec->txgi_max)
++				tic->limit -= rs_target;
++			if (tic->ulimit != hal_spec->txgi_max)
++				tic->ulimit -= rs_target;
++		}
++	}
++		break;
++#endif
++#ifdef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
++	case TXPWR_PG_WITH_TSSI_OFFSET: {
++		/*
++		* power index = 
++		* 1. base (fixed) +
++		* 2. target (per rate) +
++		* 3. amends diff (per rate)
++		* base is selected that power index of MCS7 ==  halrf_get_tssi_codeword_for_txindex()
++		*/
++		s8 mcs7_idx;
++
++		mcs7_idx = phy_get_tssi_txpwr_by_rate_ref(adapter, rfpath, bw, cch, opch);
++		base = halrf_get_tssi_codeword_for_txindex(adapter_to_phydm(adapter)) - mcs7_idx;
++		power_idx = base + rate_target + rate_amends;
++	}
++		break;
++#endif
++	}
++
++	if (tic) {
++		tic->ntx_idx = ntx_idx;
++		tic->base = base;
++	}
++
++	if (power_idx < 0)
++		power_idx = 0;
++	else if (power_idx > hal_spec->txgi_max)
++		power_idx = hal_spec->txgi_max;
++
++#if defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8812A)
++	if ((IS_HARDWARE_TYPE_8821(adapter) || IS_HARDWARE_TYPE_8812(adapter))
++		&& power_idx % 2 == 1 && !IS_NORMAL_CHIP(hal->version_id))
++		--power_idx;
++#endif
++
++	return power_idx;
++}
++
++/* get txpowr in mBm for single path */
++s16 phy_get_txpwr_single_mbm(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate
++	, enum channel_width bw, u8 cch, u8 opch, struct txpwr_idx_comp *tic)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	BAND_TYPE band = cch <= 14 ? BAND_ON_2_4G : BAND_ON_5G;
++	u8 ntx_idx = phy_get_current_tx_num(adapter, rate);
++	s16 val;
++
++	val = phy_get_txpwr_target(adapter, rfpath, rs, rate, ntx_idx, bw, band, cch, opch, tic);
++	val = (val * MBM_PDBM) / hal_spec->txgi_pdbm;
++	if (tic)
++		tic->ntx_idx = ntx_idx;
++
++	return val;
++}
++
++/* get txpowr in mBm with effect of N-TX */
++s16 phy_get_txpwr_total_mbm(_adapter *adapter, RATE_SECTION rs, u8 rate
++	, enum channel_width bw, u8 cch, u8 opch, struct txpwr_idx_comp *tic)
++{
++	s16 val;
++	u8 tx_num = phy_get_current_tx_num(adapter, rate) + 1;
++
++	/* assume all path have same txpower target */
++	val = phy_get_txpwr_single_mbm(adapter, RF_PATH_A, rs, rate, bw, cch, opch, tic);
++	val += mb_of_ntx(tx_num);
++
++	return val;
++}
++
++static s16 _phy_get_txpwr_max_mbm(_adapter *adapter, s8 rfpath
++	, enum channel_width bw, u8 cch, u8 opch, u16 bmp_cck_ofdm, u32 bmp_ht, u64 bmp_vht)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	BAND_TYPE band = cch <= 14 ? BAND_ON_2_4G : BAND_ON_5G;
++	u8 tx_num;
++	RATE_SECTION rs;
++	u8 hw_rate;
++	int i;
++	s16 max = UNSPECIFIED_MBM, mbm;
++
++	if (0)
++		RTW_INFO("cck_ofdm:0x%04x, ht:0x%08x, vht:0x%016llx\n", bmp_cck_ofdm, bmp_ht, bmp_vht);
++
++	for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
++		tx_num = rate_section_to_tx_num(rs);
++		if (tx_num + 1 > hal_data->tx_nss)
++			continue;
++		
++		if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
++			continue;
++		
++		if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
++			continue;
++		
++		for (i = 0; i < rates_by_sections[rs].rate_num; i++) {
++			hw_rate = MRateToHwRate(rates_by_sections[rs].rates[i]);
++			if (IS_LEGACY_HRATE(hw_rate)) {
++				if (!(bmp_cck_ofdm & BIT(hw_rate)))
++					continue;
++			} else if (IS_HT_HRATE(hw_rate)) {
++				if (!(bmp_ht & BIT(hw_rate - DESC_RATEMCS0)))
++					continue;
++			} else if (IS_VHT_HRATE(hw_rate)) {
++				if (!(bmp_vht & BIT(hw_rate - DESC_RATEVHTSS1MCS0)))
++					continue;
++			}
++
++			if (rfpath < 0) /* total */
++				mbm = phy_get_txpwr_total_mbm(adapter, rs, rates_by_sections[rs].rates[i], bw, cch, opch, NULL);
++			else
++				mbm = phy_get_txpwr_single_mbm(adapter, rfpath, rs, rates_by_sections[rs].rates[i], bw, cch, opch, NULL);
++
++			if (max == UNSPECIFIED_MBM || mbm > max)
++				max = mbm;
++		}
++	}
++
++	return max;
++}
++
++s16 phy_get_txpwr_single_max_mbm(_adapter *adapter, u8 rfpath
++	, enum channel_width bw, u8 cch, u8 opch, u16 bmp_cck_ofdm, u32 bmp_ht, u64 bmp_vht)
++{
++	return _phy_get_txpwr_max_mbm(adapter, rfpath, bw, cch, opch, bmp_cck_ofdm, bmp_ht, bmp_vht);
++}
++
++s16 phy_get_txpwr_total_max_mbm(_adapter *adapter
++	, enum channel_width bw, u8 cch, u8 opch, u16 bmp_cck_ofdm, u32 bmp_ht, u64 bmp_vht)
++{
++	return _phy_get_txpwr_max_mbm(adapter, -1, bw, cch, opch, bmp_cck_ofdm, bmp_ht, bmp_vht);
++}
++
++s8
++phy_get_tx_power_final_absolute_value(_adapter *adapter, u8 rfpath, u8 rate,
++				      enum channel_width bw, u8 cch)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	RATE_SECTION rs = mgn_rate_to_rs(rate);
++	BAND_TYPE band = cch <= 14 ? BAND_ON_2_4G : BAND_ON_5G;
++	s8 val;
++
++	val = phy_get_txpwr_target(adapter, rfpath
++		, rs, rate, phy_get_current_tx_num(adapter, rate), bw, band, cch, 0, NULL);
++
++	val /= hal_spec->txgi_pdbm;
++
++	return val;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_dm.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_dm.c
+new file mode 100644
+index 000000000..3f9e2d4b2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_dm.c
+@@ -0,0 +1,1855 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2014 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++/* A mapping from HalData to ODM. */
++enum odm_board_type boardType(u8 InterfaceSel)
++{
++	enum odm_board_type        board	= ODM_BOARD_DEFAULT;
++
++#ifdef CONFIG_PCI_HCI
++	INTERFACE_SELECT_PCIE   pcie	= (INTERFACE_SELECT_PCIE)InterfaceSel;
++	switch (pcie) {
++	case INTF_SEL0_SOLO_MINICARD:
++		board |= ODM_BOARD_MINICARD;
++		break;
++	case INTF_SEL1_BT_COMBO_MINICARD:
++		board |= ODM_BOARD_BT;
++		board |= ODM_BOARD_MINICARD;
++		break;
++	default:
++		board = ODM_BOARD_DEFAULT;
++		break;
++	}
++
++#elif defined(CONFIG_USB_HCI)
++	INTERFACE_SELECT_USB    usb	= (INTERFACE_SELECT_USB)InterfaceSel;
++	switch (usb) {
++	case INTF_SEL1_USB_High_Power:
++		board |= ODM_BOARD_EXT_LNA;
++		board |= ODM_BOARD_EXT_PA;
++		break;
++	case INTF_SEL2_MINICARD:
++		board |= ODM_BOARD_MINICARD;
++		break;
++	case INTF_SEL4_USB_Combo:
++		board |= ODM_BOARD_BT;
++		break;
++	case INTF_SEL5_USB_Combo_MF:
++		board |= ODM_BOARD_BT;
++		break;
++	case INTF_SEL0_USB:
++	case INTF_SEL3_USB_Solo:
++	default:
++		board = ODM_BOARD_DEFAULT;
++		break;
++	}
++
++#endif
++	/* RTW_INFO("===> boardType(): (pHalData->InterfaceSel, pDM_Odm->BoardType) = (%d, %d)\n", InterfaceSel, board); */
++
++	return board;
++}
++
++void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter)
++{
++	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
++	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
++
++	if (hal->RegIQKFWOffload) {
++		rtw_sctx_init(&hal->iqk_sctx, 0);
++		phydm_fwoffload_ability_init(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
++	} else
++		phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
++
++	RTW_INFO("IQK FW offload:%s\n", hal->RegIQKFWOffload ? "enable" : "disable");
++
++	if (rtw_mi_check_status(adapter, MI_LINKED)) {
++		#ifdef CONFIG_LPS
++		LPS_Leave(adapter, "SWITCH_IQK_OFFLOAD");
++		#endif
++		halrf_iqk_trigger(p_dm_odm, _FALSE);
++	}
++}
++
++#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
++void rtw_phydm_iqk_trigger(_adapter *adapter)
++{
++	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
++	u8 clear = _TRUE;
++	u8 segment = _FALSE;
++	u8 rfk_forbidden = _FALSE;
++
++	halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
++#if (RTL8822C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1)
++	/* halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment); to do */
++	halrf_rf_k_connect_trigger(p_dm_odm, _TRUE, SEGMENT_FREE);
++#else
++	/*segment = _rtw_phydm_iqk_segment_chk(adapter);*/
++	halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment);
++	halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
++#endif
++}
++#endif
++
++void rtw_phydm_iqk_trigger_dbg(_adapter *adapter, bool recovery, bool clear, bool segment)
++{
++	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
++
++#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
++		halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
++#else
++		halrf_iqk_trigger(p_dm_odm, recovery);
++#endif
++}
++void rtw_phydm_lck_trigger(_adapter *adapter)
++{
++	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
++
++	halrf_lck_trigger(p_dm_odm);
++}
++#ifdef CONFIG_DBG_RF_CAL
++void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment)
++{
++	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
++
++	rtw_ps_deny(adapter, PS_DENY_IOCTL);
++	LeaveAllPowerSaveModeDirect(adapter);
++
++	rtw_phydm_ability_backup(adapter);
++	rtw_phydm_func_disable_all(adapter);
++
++	halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_IQK);
++
++	rtw_phydm_iqk_trigger_dbg(adapter, recovery, clear, segment);
++	rtw_phydm_ability_restore(adapter);
++
++	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
++}
++
++void rtw_hal_lck_test(_adapter *adapter)
++{
++	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
++
++	rtw_ps_deny(adapter, PS_DENY_IOCTL);
++	LeaveAllPowerSaveModeDirect(adapter);
++
++	rtw_phydm_ability_backup(adapter);
++	rtw_phydm_func_disable_all(adapter);
++
++	halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_LCK);
++
++	rtw_phydm_lck_trigger(adapter);
++
++	rtw_phydm_ability_restore(adapter);
++	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
++}
++#endif
++
++#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
++void rtw_hal_update_param_init_fw_offload_cap(_adapter *adapter)
++{
++	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
++
++	if (adapter->registrypriv.fw_param_init)
++		phydm_fwoffload_ability_init(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
++	else
++		phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
++
++	RTW_INFO("Init-Parameter FW offload:%s\n", adapter->registrypriv.fw_param_init ? "enable" : "disable");
++}
++#endif
++
++void record_ra_info(void *p_dm_void, u8 macid, struct cmn_sta_info *p_sta, u64 ra_mask)
++{
++	struct dm_struct *p_dm = (struct dm_struct *)p_dm_void;
++	_adapter *adapter = p_dm->adapter;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++
++	if (p_sta) {
++		rtw_macid_ctl_set_bw(macid_ctl, macid, p_sta->ra_info.ra_bw_mode);
++		rtw_macid_ctl_set_vht_en(macid_ctl, macid, p_sta->ra_info.is_vht_enable);
++		rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, ra_mask);
++		rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, ra_mask >> 32);
++
++		rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
++	}
++}
++
++#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
++void rtw_phydm_fill_desc_dpt(void *dm, u8 *desc, u8 dpt_lv)
++{
++	struct dm_struct *p_dm = (struct dm_struct *)dm;
++	_adapter *adapter = p_dm->adapter;
++
++	switch (rtw_get_chip_type(adapter)) {
++/*
++	#ifdef CONFIG_RTL8188F
++	case RTL8188F:
++		break;
++	#endif
++
++	#ifdef CONFIG_RTL8723B
++	case RTL8723B :
++		break;
++	#endif
++
++	#ifdef CONFIG_RTL8703B
++	case RTL8703B :
++		break;
++	#endif
++
++	#ifdef CONFIG_RTL8812A
++	case RTL8812 :
++		break;
++	#endif
++
++	#ifdef CONFIG_RTL8821A
++	case RTL8821:
++		break;
++	#endif
++
++	#ifdef CONFIG_RTL8814A
++	case RTL8814A :
++		break;
++	#endif
++
++	#ifdef CONFIG_RTL8192F
++	case RTL8192F :
++		break;
++	#endif
++*/
++/*
++	#ifdef CONFIG_RTL8192E
++	case RTL8192E :
++		SET_TX_DESC_TX_POWER_0_PSET_92E(desc, dpt_lv);
++		break;
++	#endif
++*/
++	#ifdef CONFIG_RTL8822B
++	case RTL8822B :
++		SET_TX_DESC_TXPWR_OFSET_8822B(desc, dpt_lv);
++	break;
++	#endif
++
++	#ifdef CONFIG_RTL8821C
++	case RTL8821C :
++		SET_TX_DESC_TXPWR_OFSET_8821C(desc, dpt_lv);
++	break;
++	#endif
++
++	default :
++		RTW_ERR("%s IC not support dynamic tx power\n", __func__);
++		break;
++	}
++}
++void rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id)
++{
++	struct dm_struct *dm = adapter_to_phydm(adapter);
++
++	odm_set_dyntxpwr(dm, desc, mac_id);
++}
++#endif
++
++#ifdef CONFIG_TDMADIG
++void rtw_phydm_tdmadig(_adapter *adapter, u8 state)
++{
++	struct registry_priv	*pregistrypriv = &adapter->registrypriv;
++	struct mlme_priv		*pmlmepriv = &(adapter->mlmepriv);
++	struct dm_struct *dm = adapter_to_phydm(adapter);
++	u8 tdma_dig_en;
++
++	switch (state) {
++	case TDMADIG_INIT:
++		phydm_tdma_dig_para_upd(dm, ENABLE_TDMA, pregistrypriv->tdmadig_en);
++		phydm_tdma_dig_para_upd(dm, MODE_DECISION, pregistrypriv->tdmadig_mode);
++		break;
++	case TDMADIG_NON_INIT:
++		if(pregistrypriv->tdmadig_dynamic) {
++			if(pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)
++				tdma_dig_en = 0;
++			else
++				tdma_dig_en = pregistrypriv->tdmadig_en;
++			phydm_tdma_dig_para_upd(dm, ENABLE_TDMA, tdma_dig_en);
++		}
++		break;
++	default:
++		break;
++
++	}
++}
++#endif/*CONFIG_TDMADIG*/
++void rtw_phydm_ops_func_init(struct dm_struct *p_phydm)
++{
++	struct ra_table *p_ra_t = &p_phydm->dm_ra_table;
++
++	p_ra_t->record_ra_info = record_ra_info;
++	#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
++	p_phydm->fill_desc_dyntxpwr = rtw_phydm_fill_desc_dpt;
++	#endif
++}
++void rtw_phydm_priv_init(_adapter *adapter)
++{
++	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
++	struct dm_struct *phydm = &(hal->odmpriv);
++
++	phydm->adapter = adapter;
++	odm_cmn_info_init(phydm, ODM_CMNINFO_PLATFORM, ODM_CE);
++}
++
++void Init_ODM_ComInfo(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(adapter);
++	struct dm_struct	*pDM_Odm = &(pHalData->odmpriv);
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
++	int i;
++
++	/*phydm_op_mode could be change for different scenarios: ex: SoftAP - PHYDM_BALANCE_MODE*/
++	pHalData->phydm_op_mode = PHYDM_PERFORMANCE_MODE;/*Service one device*/
++	rtw_odm_init_ic_type(adapter);
++
++	if (rtw_get_intf_type(adapter) == RTW_GSPI)
++		odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, ODM_ITRF_SDIO);
++	else
++		odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, rtw_get_intf_type(adapter));
++
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->version_id));
++
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID);
++
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec);
++
++#ifdef CONFIG_ADVANCE_OTA
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ADVANCE_OTA, adapter->registrypriv.adv_ota);
++#endif
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, pHalData->rf_type);
++
++	{
++		/* 1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= */
++		u8 odm_board_type = ODM_BOARD_DEFAULT;
++
++		if (pHalData->ExternalLNA_2G != 0) {
++			odm_board_type |= ODM_BOARD_EXT_LNA;
++			odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1);
++		}
++		if (pHalData->external_lna_5g != 0) {
++			odm_board_type |= ODM_BOARD_EXT_LNA_5G;
++			odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, 1);
++		}
++		if (pHalData->ExternalPA_2G != 0) {
++			odm_board_type |= ODM_BOARD_EXT_PA;
++			odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_PA, 1);
++		}
++		if (pHalData->external_pa_5g != 0) {
++			odm_board_type |= ODM_BOARD_EXT_PA_5G;
++			odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, 1);
++		}
++		if (pHalData->EEPROMBluetoothCoexist)
++			odm_board_type |= ODM_BOARD_BT;
++
++		odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, odm_board_type);
++		/* 1 ============== End of BoardType ============== */
++	}
++
++	rtw_hal_set_odm_var(adapter, HAL_ODM_REGULATION, NULL, _TRUE);
++
++#ifdef CONFIG_DFS_MASTER
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_DFS_REGION_DOMAIN, adapter_to_rfctl(adapter)->dfs_region_domain);
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->radar_detect_enabled));
++#endif
++
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA);
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_APA, pHalData->TypeAPA);
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GLNA, pHalData->TypeGLNA);
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA);
++
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->rfe_type);
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_X_CAP_SETTING, pHalData->crystal_cap);
++
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0);
++
++	/*Add by YuChen for kfree init*/
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_REGRFKFREEENABLE, adapter->registrypriv.RegPwrTrimEnable);
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFKFREEENABLE, pHalData->RfKFreeEnable);
++
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BE_FIX_TX_ANT, pHalData->b_fix_tx_ant);
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, pHalData->with_extenal_ant_switch);
++
++	/* (8822B) efuse 0x3D7 & 0x3D8 for TX PA bias */
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D7, pHalData->efuse0x3d7);
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D8, pHalData->efuse0x3d8);
++
++	/* waiting for PhyDMV034 support*/
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MANUAL_SUPPORTABILITY, &(adapter->registrypriv.phydm_ability)); 
++	/*Add by YuChen for adaptivity init*/
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVITY, &(adapter->registrypriv.adaptivity_en));
++	phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE);
++	phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini);
++	phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff);
++
++	/*halrf info init*/
++	halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_EEPROM_THERMAL_VALUE, pHalData->eeprom_thermal_meter);
++	halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_PWT_TYPE, 0);
++	halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_MP_POWER_TRACKING_TYPE, pHalData->txpwr_pg_mode);
++
++	if (rtw_odm_adaptivity_needed(adapter) == _TRUE)
++		rtw_odm_adaptivity_config_msg(RTW_DBGDUMP, adapter);
++
++#ifdef CONFIG_IQK_PA_OFF
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKPAOFF, 1);
++#endif
++	rtw_hal_update_iqk_fw_offload_cap(adapter);
++	#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
++	rtw_hal_update_param_init_fw_offload_cap(adapter);
++	#endif
++
++	/* Pointer reference */
++	/*Antenna diversity relative parameters*/
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_DIV, &(pHalData->AntDivCfg));
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MP_MODE, &(adapter->registrypriv.mp_mode));
++
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BB_OPERATION_MODE, &(pHalData->phydm_op_mode));
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes));
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes));
++
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->current_band_type));
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate));
++
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC));
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm));
++#ifdef CONFIG_NARROWBAND_SUPPORTING
++	if ((adapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_10)
++		|| (adapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_5)) {
++		odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(adapter->registrypriv.rtw_nb_config));
++	}
++	else
++#endif
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->current_channel_bw));
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->current_channel));
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed));
++
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SCAN, &(pHalData->bScanInProcess));
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving));
++	/*Add by Yuchen for phydm beamforming*/
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp));
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp));
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_TEST, &(pHalData->antenna_test));
++#ifdef CONFIG_RTL8723B
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_IS1ANTENNA, &pHalData->EEPROMBluetoothAntNum);
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RFDEFAULTPATH, &pHalData->ant_path);
++#endif /*CONFIG_RTL8723B*/
++#ifdef CONFIG_USB_HCI
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_HUBUSBMODE, &(dvobj->usb_speed));
++#endif
++
++#ifdef CONFIG_DYNAMIC_SOML
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVE_SOML, &(adapter->registrypriv.dyn_soml_en));
++#endif
++#ifdef CONFIG_RTW_PATH_DIV
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_PATH_DIV, &(adapter->registrypriv.path_div));
++#endif
++	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FCS_MODE, &(pHalData->multi_ch_switch_mode));
++
++	/*halrf info hook*/
++	/* waiting for PhyDMV034 support*/
++	halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY, &(adapter->registrypriv.halrf_ability));
++#ifdef CONFIG_MP_INCLUDED
++	halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CON_TX, &(adapter->mppriv.mpt_ctx.is_start_cont_tx));
++	halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_SINGLE_TONE, &(adapter->mppriv.mpt_ctx.is_single_tone));
++	halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CARRIER_SUPPRESSION, &(adapter->mppriv.mpt_ctx.is_carrier_suppression));
++	halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MP_RATE_INDEX, &(adapter->mppriv.mpt_ctx.mpt_rate_index));
++#endif/*CONFIG_MP_INCLUDED*/
++	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
++		phydm_cmn_sta_info_hook(pDM_Odm, i, NULL);
++
++	rtw_phydm_ops_func_init(pDM_Odm);
++	phydm_dm_early_init(pDM_Odm);
++	/* TODO */
++	/* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */
++	/* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */
++}
++
++
++static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
++/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
++/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(DownLink/Tx) */
++{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
++
++static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
++/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
++/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(UpLink/Rx)*/
++{ 0xa44f, 0x5ea44f,	 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
++
++static u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] =
++/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
++/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP */
++{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322,	 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
++
++
++struct turbo_edca_setting{
++	u32 edca_ul; /* uplink, tx */
++	u32 edca_dl; /* downlink, rx */
++};
++
++#define TURBO_EDCA_ENT(UL, DL) {UL, DL}
++
++#if 0
++#define TURBO_EDCA_MODE_NUM 18
++static struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {
++	TURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 0 */
++	TURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */
++	TURBO_EDCA_ENT(0x4319, 0x4319), /* mode 2 */	
++	
++	TURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */
++	TURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 4 */
++	TURBO_EDCA_ENT(0x5e4319, 0x5e4319), /* mode 5 */	
++	
++	TURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 6 */
++	TURBO_EDCA_ENT(0x6e431c, 0x6e431c), /* mode 7 */
++	TURBO_EDCA_ENT(0x6e4319, 0x6e4319), /* mode 8 */
++	
++	TURBO_EDCA_ENT(0x5ea42b, 0xa42b), /* mode 9 */
++	TURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 10 */
++	TURBO_EDCA_ENT(0x5e4319, 0x4319), /* mode 11 */
++	
++	TURBO_EDCA_ENT(0x6ea42b, 0xa42b), /* mode 12 */
++	TURBO_EDCA_ENT(0x6e431c, 0x431c), /* mode 13 */
++	TURBO_EDCA_ENT(0x6e4319, 0x4319), /* mode 14 */
++
++	TURBO_EDCA_ENT(0x431c, 0x5e431c), /* mode 15 */
++
++	TURBO_EDCA_ENT(0xa42b, 0x5ea42b), /* mode 16 */
++
++	TURBO_EDCA_ENT(0x138642b, 0x431c), /* mode 17 */
++};
++#else
++#define TURBO_EDCA_MODE_NUM 8
++static struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {
++	/* { UL, DL } */
++	TURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 0 */
++
++	TURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */	
++	
++	TURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 2 */
++
++	TURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */
++	
++	TURBO_EDCA_ENT(0x5ea42b, 0x431c), /* mode 4 */
++	
++	TURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 5 */
++
++	TURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 6 */
++	
++	TURBO_EDCA_ENT(0x5e431c, 0xa42b), /* mode 7 */
++};
++#endif
++
++void rtw_hal_turbo_edca(_adapter *adapter)
++{
++	HAL_DATA_TYPE		*hal_data = GET_HAL_DATA(adapter);
++	struct dvobj_priv		*dvobj = adapter_to_dvobj(adapter);
++	struct recv_priv		*precvpriv = &(adapter->recvpriv);
++	struct registry_priv		*pregpriv = &adapter->registrypriv;
++	struct mlme_ext_priv	*pmlmeext = &(adapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	/* Parameter suggested by Scott  */
++#if 0
++	u32	EDCA_BE_UL = edca_setting_UL[p_mgnt_info->iot_peer];
++	u32	EDCA_BE_DL = edca_setting_DL[p_mgnt_info->iot_peer];
++#endif
++	u32	EDCA_BE_UL = 0x5ea42b;
++	u32	EDCA_BE_DL = 0x00a42b;
++	u8	ic_type = rtw_get_chip_type(adapter);
++
++	u8	iot_peer = 0;
++	u8	wireless_mode = 0xFF;                 /* invalid value */
++	u8	traffic_index;
++	u32	edca_param;
++	u64	cur_tx_bytes = 0;
++	u64	cur_rx_bytes = 0;
++	u8	bbtchange = _TRUE;
++	u8	is_bias_on_rx = _FALSE;
++	u8	is_linked = _FALSE;
++	u8	interface_type;
++
++	if (hal_data->dis_turboedca == 1)
++		return;
++
++	if (rtw_mi_check_status(adapter, MI_ASSOC))
++		is_linked = _TRUE;
++
++	if (is_linked != _TRUE) {
++		precvpriv->is_any_non_be_pkts = _FALSE;
++		return;
++	}
++
++	if ((pregpriv->wifi_spec == 1)) { /* || (pmlmeinfo->HT_enable == 0)) */
++		precvpriv->is_any_non_be_pkts = _FALSE;
++		return;
++	}
++
++	interface_type = rtw_get_intf_type(adapter);
++	wireless_mode = pmlmeext->cur_wireless_mode;
++
++	iot_peer = pmlmeinfo->assoc_AP_vendor;
++
++	if (iot_peer >=  HT_IOT_PEER_MAX) {
++		precvpriv->is_any_non_be_pkts = _FALSE;
++		return;
++	}
++
++	if (ic_type == RTL8188E) {
++		if ((iot_peer == HT_IOT_PEER_RALINK) || (iot_peer == HT_IOT_PEER_ATHEROS))
++			is_bias_on_rx = _TRUE;
++	}
++
++	/* Check if the status needs to be changed. */
++	if ((bbtchange) || (!precvpriv->is_any_non_be_pkts)) {
++		cur_tx_bytes = dvobj->traffic_stat.cur_tx_bytes;
++		cur_rx_bytes = dvobj->traffic_stat.cur_rx_bytes;
++
++		/* traffic, TX or RX */
++		if (is_bias_on_rx) {
++			if (cur_tx_bytes > (cur_rx_bytes << 2)) {
++				/* Uplink TP is present. */
++				traffic_index = UP_LINK;
++			} else {
++				/* Balance TP is present. */
++				traffic_index = DOWN_LINK;
++			}
++		} else {
++			if (cur_rx_bytes > (cur_tx_bytes << 2)) {
++				/* Downlink TP is present. */
++				traffic_index = DOWN_LINK;
++			} else {
++				/* Balance TP is present. */
++				traffic_index = UP_LINK;
++			}
++		}
++#if 0
++		if ((p_dm_odm->dm_edca_table.prv_traffic_idx != traffic_index)
++			|| (!p_dm_odm->dm_edca_table.is_current_turbo_edca))
++#endif
++		{
++			if (interface_type == RTW_PCIE) {
++				EDCA_BE_UL = 0x6ea42b;
++				EDCA_BE_DL = 0x6ea42b;
++			}
++
++			/* 92D txop can't be set to 0x3e for cisco1250 */
++			if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
++				EDCA_BE_DL = edca_setting_DL[iot_peer];
++				EDCA_BE_UL = edca_setting_UL[iot_peer];
++			}
++			/* merge from 92s_92c_merge temp*/
++			else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
++				EDCA_BE_DL = edca_setting_dl_g_mode[iot_peer];
++			else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
++				EDCA_BE_DL = 0xa630;
++			else if (iot_peer == HT_IOT_PEER_MARVELL) {
++				EDCA_BE_DL = edca_setting_DL[iot_peer];
++				EDCA_BE_UL = edca_setting_UL[iot_peer];
++			} else if (iot_peer == HT_IOT_PEER_ATHEROS) {
++				/* Set DL EDCA for Atheros peer to 0x3ea42b.*/
++				/* Suggested by SD3 Wilson for ASUS TP issue.*/
++				EDCA_BE_DL = edca_setting_DL[iot_peer];
++			}
++
++			if ((ic_type == RTL8812) || (ic_type == RTL8821) || (ic_type == RTL8192E) || (ic_type == RTL8192F)) { /* add 8812AU/8812AE */
++				EDCA_BE_UL = 0x5ea42b;
++				EDCA_BE_DL = 0x5ea42b;
++
++				RTW_DBG("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x\n", EDCA_BE_UL, EDCA_BE_DL);
++			}
++
++			if (interface_type == RTW_PCIE &&
++				((ic_type == RTL8822B)
++				|| (ic_type == RTL8822C)
++				|| (ic_type == RTL8814A) || (ic_type == RTL8814B))) {
++				EDCA_BE_UL = 0x6ea42b;
++				EDCA_BE_DL = 0x6ea42b;
++			}
++
++			if ((ic_type == RTL8822B)
++			    && (interface_type == RTW_SDIO))
++				EDCA_BE_DL = 0x00431c;
++
++#ifdef CONFIG_RTW_TPT_MODE
++			if ( dvobj->tpt_mode > 0 ) {				
++				EDCA_BE_UL = dvobj->edca_be_ul;
++				EDCA_BE_DL = dvobj->edca_be_dl;
++			}
++#endif /* CONFIG_RTW_TPT_MODE */
++
++			/* keep this condition at last check */
++			if (hal_data->dis_turboedca == 2) {					
++				
++					if (hal_data->edca_param_mode < TURBO_EDCA_MODE_NUM) {
++
++						struct turbo_edca_setting param;
++
++						param = rtw_turbo_edca[hal_data->edca_param_mode];
++
++						EDCA_BE_UL = param.edca_ul;
++						EDCA_BE_DL = param.edca_dl;
++						
++					} else {
++					
++						EDCA_BE_UL = hal_data->edca_param_mode;
++						EDCA_BE_DL = hal_data->edca_param_mode;
++					}				
++			}
++
++			if (traffic_index == DOWN_LINK)
++				edca_param = EDCA_BE_DL;
++			else
++				edca_param = EDCA_BE_UL;
++
++#ifdef CONFIG_EXTEND_LOWRATE_TXOP
++#define TXOP_CCK1M			0x01A6
++#define TXOP_CCK2M			0x00E6
++#define TXOP_CCK5M			0x006B
++#define TXOP_OFD6M			0x0066
++#define TXOP_MCS6M			0x0061
++{
++			struct sta_info *psta;
++			struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++			u8 mac_id, role, current_rate_id;
++			
++			/*	search all used & connect2AP macid	*/
++			for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) {
++				if (rtw_macid_is_used(macid_ctl, mac_id))  {
++					role = GET_H2CCMD_MSRRPT_PARM_ROLE(&(macid_ctl->h2c_msr[mac_id]));
++					if (role != H2C_MSR_ROLE_AP)
++						continue;
++
++					psta = macid_ctl->sta[mac_id];
++					current_rate_id = rtw_get_current_tx_rate(adapter, psta);
++					/*  Check init tx_rate==1M and set 0x508[31:16]==0x019B(unit 32us) if it is 	*/
++					switch (current_rate_id) {
++						case DESC_RATE1M:
++							edca_param &= 0x0000FFFF;
++							edca_param |= (TXOP_CCK1M<<16);
++							break;
++						case DESC_RATE2M:
++							edca_param &= 0x0000FFFF;
++							edca_param |= (TXOP_CCK2M<<16);
++							break;
++						case DESC_RATE5_5M:
++							edca_param &= 0x0000FFFF;
++							edca_param |= (TXOP_CCK5M<<16);
++							break;
++						case DESC_RATE6M:
++							edca_param &= 0x0000FFFF;
++							edca_param |= (TXOP_OFD6M<<16);
++							break;
++						case DESC_RATEMCS0:
++							edca_param &= 0x0000FFFF;
++							edca_param |= (TXOP_MCS6M<<16);
++							break;
++						default:
++							break;
++					}
++				}
++			}
++}
++#endif /* CONFIG_EXTEND_LOWRATE_TXOP */
++
++#ifdef 	CONFIG_RTW_CUSTOMIZE_BEEDCA
++			edca_param = CONFIG_RTW_CUSTOMIZE_BEEDCA;
++#endif
++
++			if ( edca_param != hal_data->ac_param_be) {
++				
++				rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
++
++				RTW_INFO("Turbo EDCA =0x%x\n", edca_param);
++			}
++
++			hal_data->prv_traffic_idx = traffic_index;
++		}
++
++		hal_data->is_turbo_edca = _TRUE;
++	} else {
++		/*  */
++		/* Turn Off EDCA turbo here. */
++		/* Restore original EDCA according to the declaration of AP. */
++		/*  */
++		if (hal_data->is_turbo_edca) {
++			edca_param = hal_data->ac_param_be;
++			rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
++			hal_data->is_turbo_edca = _FALSE;
++		}
++	}
++
++}
++
++s8 rtw_dm_get_min_rssi(_adapter *adapter)
++{
++	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
++	struct sta_info *sta;
++	s8 min_rssi = 127, rssi;
++	int i;
++
++	for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
++		sta = macid_ctl->sta[i];
++		if (!sta || !GET_H2CCMD_MSRRPT_PARM_OPMODE(macid_ctl->h2c_msr + i)
++			|| is_broadcast_mac_addr(sta->cmn.mac_addr))
++			continue;
++		rssi = sta->cmn.rssi_stat.rssi;
++		if (rssi >= 0 && min_rssi > rssi)
++			min_rssi = rssi;
++	}
++
++	return min_rssi == 127 ? 0 : min_rssi;
++}
++
++s8 rtw_phydm_get_min_rssi(_adapter *adapter)
++{
++	struct dm_struct *phydm = adapter_to_phydm(adapter);
++	s8 rssi_min = 0;
++
++	rssi_min = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_RSSI_MIN);
++	return rssi_min;
++}
++
++u8 rtw_phydm_get_cur_igi(_adapter *adapter)
++{
++	struct dm_struct *phydm = adapter_to_phydm(adapter);
++	u8 cur_igi = 0;
++
++	cur_igi = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CURR_IGI);
++	return cur_igi;
++}
++
++bool rtw_phydm_get_edcca_flag(_adapter *adapter)
++{
++	struct dm_struct *phydm = adapter_to_phydm(adapter);
++	bool cur_edcca_flag = 0;
++
++	cur_edcca_flag = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_EDCCA_FLAG);
++	return cur_edcca_flag;
++}
++
++u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt)
++{
++	struct dm_struct *phydm = adapter_to_phydm(adapter);
++
++	if (cnt == FA_OFDM)
++		return  phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_OFDM);
++	else if (cnt == FA_CCK)
++		return  phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_CCK);
++	else if (cnt == FA_TOTAL)
++		return  phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_TOTAL);
++	else if (cnt == CCA_OFDM)
++		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_OFDM);
++	else if (cnt == CCA_CCK)
++		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_CCK);
++	else if (cnt == CCA_ALL)
++		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_ALL);
++	else if (cnt == CRC32_OK_VHT)
++		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_VHT);
++	else if (cnt == CRC32_OK_HT)
++		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_HT);
++	else if (cnt == CRC32_OK_LEGACY)
++		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_LEGACY);
++	else if (cnt == CRC32_OK_CCK)
++		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_CCK);
++	else if (cnt == CRC32_ERROR_VHT)
++		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_VHT);
++	else if (cnt == CRC32_ERROR_HT)
++		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_HT);
++	else if (cnt == CRC32_ERROR_LEGACY)
++		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_LEGACY);
++	else if (cnt == CRC32_ERROR_CCK)
++		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_CCK);
++	else
++		return 0;
++}
++
++u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter)
++{
++	u8 rts = _FALSE;
++	struct dm_struct *podmpriv = adapter_to_phydm(adapter);
++
++	odm_acquire_spin_lock(podmpriv, RT_IQK_SPINLOCK);
++	if (podmpriv->rf_calibrate_info.is_iqk_in_progress == _TRUE) {
++		RTW_ERR("IQK InProgress\n");
++		rts = _TRUE;
++	}
++	odm_release_spin_lock(podmpriv, RT_IQK_SPINLOCK);
++
++	return rts;
++}
++
++void SetHalODMVar(
++	PADAPTER				Adapter,
++	HAL_ODM_VARIABLE		eVariable,
++	void						*pValue1,
++	BOOLEAN					bSet)
++{
++	struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
++	/* _irqL irqL; */
++	switch (eVariable) {
++	case HAL_ODM_STA_INFO: {
++		struct sta_info *psta = (struct sta_info *)pValue1;
++
++		if (bSet) {
++			RTW_INFO("### Set STA_(%d) info ###\n", psta->cmn.mac_id);
++			psta->cmn.dm_ctrl = STA_DM_CTRL_ACTIVE;
++			phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, &(psta->cmn));
++		} else {
++			RTW_INFO("### Clean STA_(%d) info ###\n", psta->cmn.mac_id);
++			/* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
++			psta->cmn.dm_ctrl = 0;
++			phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, NULL);
++
++			/* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
++		}
++	}
++		break;
++	case HAL_ODM_P2P_STATE:
++		odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
++		break;
++	case HAL_ODM_WIFI_DISPLAY_STATE:
++		odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
++		break;
++	case HAL_ODM_REGULATION:
++		/* used to auto enable/disable adaptivity by SD7 */
++		phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_2G, 0);
++		phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_5G, 0);
++		break;
++	case HAL_ODM_INITIAL_GAIN: {
++		u8 rx_gain = *((u8 *)(pValue1));
++		/*printk("rx_gain:%x\n",rx_gain);*/
++		if (rx_gain == 0xff) {/*restore rx gain*/
++			/*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/
++			odm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain);
++		} else {
++			/*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/
++			/*odm_write_dig(podmpriv,rx_gain);*/
++			odm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain);
++		}
++	}
++	break;
++	case HAL_ODM_RX_INFO_DUMP: {
++		u8 cur_igi = 0;
++		s8 rssi_min;
++		void *sel;
++
++		sel = pValue1;
++		cur_igi = rtw_phydm_get_cur_igi(Adapter);
++		rssi_min = rtw_phydm_get_min_rssi(Adapter);
++
++		_RTW_PRINT_SEL(sel, "============ Rx Info dump ===================\n");
++		_RTW_PRINT_SEL(sel, "is_linked = %d, rssi_min = %d(%%)(%d(%%)), current_igi = 0x%x\n"
++			, podmpriv->is_linked, rssi_min, rtw_dm_get_min_rssi(Adapter), cur_igi);
++		_RTW_PRINT_SEL(sel, "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n",
++			rtw_phydm_get_phy_cnt(Adapter, FA_CCK),
++			rtw_phydm_get_phy_cnt(Adapter, FA_OFDM),
++			rtw_phydm_get_phy_cnt(Adapter, FA_TOTAL));
++
++		if (podmpriv->is_linked) {
++			_RTW_PRINT_SEL(sel, "rx_rate = %s", HDATA_RATE(podmpriv->rx_rate));
++			if (IS_HARDWARE_TYPE_8814A(Adapter))
++				_RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%), rssi_c = %d(%%), rssi_d = %d(%%)\n",
++					podmpriv->rssi_a, podmpriv->rssi_b, podmpriv->rssi_c, podmpriv->rssi_d);
++			else
++				_RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%)\n", podmpriv->rssi_a, podmpriv->rssi_b);
++#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
++			rtw_dump_raw_rssi_info(Adapter, sel);
++#endif
++		}
++	}
++		break;
++	case HAL_ODM_RX_Dframe_INFO: {
++		void *sel;
++
++		sel = pValue1;
++
++		/*_RTW_PRINT_SEL(sel , "HAL_ODM_RX_Dframe_INFO\n");*/
++#ifdef DBG_RX_DFRAME_RAW_DATA
++		rtw_dump_rx_dframe_info(Adapter, sel);
++#endif
++	}
++		break;
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	case HAL_ODM_ANTDIV_SELECT: {
++		u8	antenna = (*(u8 *)pValue1);
++		HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++		/*switch antenna*/
++		odm_update_rx_idle_ant(&pHalData->odmpriv, antenna);
++		/*RTW_INFO("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/
++
++	}
++		break;
++#endif
++
++	default:
++		break;
++	}
++}
++
++void GetHalODMVar(
++	PADAPTER				Adapter,
++	HAL_ODM_VARIABLE		eVariable,
++	void						*pValue1,
++	void						*pValue2)
++{
++	struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
++
++	switch (eVariable) {
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	case HAL_ODM_ANTDIV_SELECT: {
++		struct phydm_fat_struct	*pDM_FatTable = &podmpriv->dm_fat_table;
++		*((u8 *)pValue1) = pDM_FatTable->rx_idle_ant;
++	}
++		break;
++#endif
++	case HAL_ODM_INITIAL_GAIN:
++		*((u8 *)pValue1) = rtw_phydm_get_cur_igi(Adapter);
++		break;
++	default:
++		break;
++	}
++}
++
++#ifdef RTW_HALMAC
++#include "../hal_halmac.h"
++#endif
++
++enum hal_status
++rtw_phydm_fw_iqk(
++	struct dm_struct	*p_dm_odm,
++	u8 clear,
++	u8 segment
++)
++{
++	#ifdef RTW_HALMAC
++	struct _ADAPTER *adapter = p_dm_odm->adapter;
++
++	if (rtw_halmac_iqk(adapter_to_dvobj(adapter), clear, segment) == 0)
++		return HAL_STATUS_SUCCESS;
++	#endif
++	return HAL_STATUS_FAILURE;
++}
++
++enum hal_status
++rtw_phydm_cfg_phy_para(
++	struct dm_struct	*p_dm_odm,
++	enum phydm_halmac_param config_type,
++	u32 offset,
++	u32 data,
++	u32 mask,
++	enum rf_path e_rf_path,
++	u32 delay_time)
++{
++	#ifdef RTW_HALMAC
++	struct _ADAPTER *adapter = p_dm_odm->adapter;
++	struct rtw_phy_parameter para;
++
++	switch (config_type) {
++	case PHYDM_HALMAC_CMD_MAC_W8:
++		para.cmd = 0; /* MAC register */
++		para.data.mac.offset = offset;
++		para.data.mac.value = data;
++		para.data.mac.msk = mask;
++		para.data.mac.msk_en = (mask) ? 1 : 0;
++		para.data.mac.size = 1;
++	break;
++	case PHYDM_HALMAC_CMD_MAC_W16:
++		para.cmd = 0; /* MAC register */
++		para.data.mac.offset = offset;
++		para.data.mac.value = data;
++		para.data.mac.msk = mask;
++		para.data.mac.msk_en = (mask) ? 1 : 0;
++		para.data.mac.size = 2;
++	break;
++	case PHYDM_HALMAC_CMD_MAC_W32:
++		para.cmd = 0; /* MAC register */
++		para.data.mac.offset = offset;
++		para.data.mac.value = data;
++		para.data.mac.msk = mask;
++		para.data.mac.msk_en = (mask) ? 1 : 0;
++		para.data.mac.size = 4;
++	break;
++	case PHYDM_HALMAC_CMD_BB_W8:
++		para.cmd = 1; /* BB register */
++		para.data.bb.offset = offset;
++		para.data.bb.value = data;
++		para.data.bb.msk = mask;
++		para.data.bb.msk_en = (mask) ? 1 : 0;
++		para.data.bb.size = 1;
++	break;
++	case PHYDM_HALMAC_CMD_BB_W16:
++		para.cmd = 1; /* BB register */
++		para.data.bb.offset = offset;
++		para.data.bb.value = data;
++		para.data.bb.msk = mask;
++		para.data.bb.msk_en = (mask) ? 1 : 0;
++		para.data.bb.size = 2;
++	break;
++	case PHYDM_HALMAC_CMD_BB_W32:
++		para.cmd = 1; /* BB register */
++		para.data.bb.offset = offset;
++		para.data.bb.value = data;
++		para.data.bb.msk = mask;
++		para.data.bb.msk_en = (mask) ? 1 : 0;
++		para.data.bb.size = 4;
++	break;
++	case PHYDM_HALMAC_CMD_RF_W:
++		para.cmd = 2; /* RF register */
++		para.data.rf.offset = offset;
++		para.data.rf.value = data;
++		para.data.rf.msk = mask;
++		para.data.rf.msk_en = (mask) ? 1 : 0;
++		if (e_rf_path == RF_PATH_A)
++			para.data.rf.path = 0;
++		else if (e_rf_path == RF_PATH_B)
++			para.data.rf.path = 1;
++		else if (e_rf_path == RF_PATH_C)
++			para.data.rf.path = 2;
++		else if (e_rf_path == RF_PATH_D)
++			para.data.rf.path = 3;
++		else
++			para.data.rf.path = 0;
++	break;
++	case PHYDM_HALMAC_CMD_DELAY_US:
++		para.cmd = 3; /* Delay */
++		para.data.delay.unit = 0; /* microsecond */
++		para.data.delay.value = delay_time;
++	break;
++	case PHYDM_HALMAC_CMD_DELAY_MS:
++		para.cmd = 3; /* Delay */
++		para.data.delay.unit = 1; /* millisecond */
++		para.data.delay.value = delay_time;
++	break;
++	case PHYDM_HALMAC_CMD_END:
++		para.cmd = 0xFF; /* End command */
++	break;
++	default:
++		return HAL_STATUS_FAILURE;
++	}
++
++	if (rtw_halmac_cfg_phy_para(adapter_to_dvobj(adapter), &para))
++		return HAL_STATUS_FAILURE;
++	#endif /*RTW_HALMAC*/
++	return HAL_STATUS_SUCCESS;
++}
++
++
++#ifdef CONFIG_LPS_LCLK_WD_TIMER
++void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter)
++{
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
++	struct sta_priv *pstapriv = &adapter->stapriv;
++	struct sta_info *psta = NULL;
++	bool is_linked = _FALSE;
++
++	if (!rtw_is_hw_init_completed(adapter))
++		return;
++
++	if (rtw_mi_check_status(adapter, MI_ASSOC))
++		is_linked = _TRUE;
++
++	if (is_linked == _FALSE)
++		return;
++
++	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
++	if (psta == NULL)
++		return;
++
++	odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, is_linked);
++
++	phydm_watchdog_lps_32k(&pHalData->odmpriv);
++
++#ifdef CONFIG_LPS_PG
++	if (pwrpriv->lps_level == LPS_PG) {
++		 if (rtw_hal_set_lps_pg_info_cmd(adapter) == _FAIL)
++		 	RTW_INFO(FUNC_ADPT_FMT": Send PG H2C command Fail! \n", 
++		 			 FUNC_ADPT_ARG(adapter));
++	}
++#endif /* CONFIG_LPS_PG */
++}
++
++void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter)
++{
++	struct mlme_priv	*pmlmepriv = &adapter->mlmepriv;
++	struct sta_priv *pstapriv = &adapter->stapriv;
++	u8 cur_igi = 0;
++	s8 min_rssi = 0;
++
++	if (!rtw_is_hw_init_completed(adapter))
++		return;
++
++	cur_igi = rtw_phydm_get_cur_igi(adapter);
++	min_rssi = rtw_dm_get_min_rssi(adapter);
++	/*RTW_INFO("%s "ADPT_FMT" cur_ig_value=%d, min_rssi = %d\n", __func__,  ADPT_ARG(adapter), cur_igi, min_rssi);*/
++
++	if (min_rssi <= 0)
++		return;
++
++	if ((cur_igi > min_rssi + 5) ||
++		(cur_igi < min_rssi - 5)) {
++#ifdef CONFIG_LPS
++		rtw_dm_in_lps_wk_cmd(adapter);
++#endif
++	}
++}
++#endif /*CONFIG_LPS_LCLK_WD_TIMER*/
++
++void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta)
++{
++	struct ra_sta_info *ra_info;
++	u8 curr_sgi = _FALSE;
++	u32 tx_tp_mbips, rx_tp_mbips, bi_tp_mbips;
++
++	if (!psta)
++		return;
++	RTW_PRINT_SEL(sel, "\n");
++	RTW_PRINT_SEL(sel, "====== mac_id : %d [" MAC_FMT "] ======\n",
++		psta->cmn.mac_id, MAC_ARG(psta->cmn.mac_addr));
++
++	if (is_client_associated_to_ap(psta->padapter))
++		RTW_PRINT_SEL(sel, "BCN counts : %d (per-%d second), DTIM Period:%d\n",
++		rtw_get_bcn_cnt(psta->padapter) / 2, 1, rtw_get_bcn_dtim_period(psta->padapter));
++
++	ra_info = &psta->cmn.ra_info;
++	curr_sgi = rtw_get_current_tx_sgi(adapter, psta);
++	RTW_PRINT_SEL(sel, "tx_rate : %s(%s)  rx_rate : %s, rx_rate_bmc : %s, rssi : %d %%\n"
++		, HDATA_RATE(rtw_get_current_tx_rate(adapter, psta)), (curr_sgi) ? "S" : "L"
++		, HDATA_RATE((psta->curr_rx_rate & 0x7F)), HDATA_RATE((psta->curr_rx_rate_bmc & 0x7F)), psta->cmn.rssi_stat.rssi
++	);
++
++	if (0) {
++		RTW_PRINT_SEL(sel, "tx_bytes:%llu(%llu - %llu)\n"
++			, psta->sta_stats.tx_bytes - psta->sta_stats.last_tx_bytes
++			, psta->sta_stats.tx_bytes, psta->sta_stats.last_tx_bytes
++		);
++		RTW_PRINT_SEL(sel, "rx_uc_bytes:%llu(%llu - %llu)\n"
++			, sta_rx_uc_bytes(psta) - sta_last_rx_uc_bytes(psta)
++			, sta_rx_uc_bytes(psta), sta_last_rx_uc_bytes(psta)
++		);
++		RTW_PRINT_SEL(sel, "rx_mc_bytes:%llu(%llu - %llu)\n"
++			, psta->sta_stats.rx_mc_bytes - psta->sta_stats.last_rx_mc_bytes
++			, psta->sta_stats.rx_mc_bytes, psta->sta_stats.last_rx_mc_bytes
++		);
++		RTW_PRINT_SEL(sel, "rx_bc_bytes:%llu(%llu - %llu)\n"
++			, psta->sta_stats.rx_bc_bytes - psta->sta_stats.last_rx_bc_bytes
++			, psta->sta_stats.rx_bc_bytes, psta->sta_stats.last_rx_bc_bytes
++		);
++	}
++
++	_RTW_PRINT_SEL(sel, "RTW: [TP] ");
++	tx_tp_mbips = psta->sta_stats.tx_tp_kbits >> 10;
++	rx_tp_mbips = psta->sta_stats.rx_tp_kbits >> 10;
++	bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
++
++	if (tx_tp_mbips)
++		_RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
++	else
++		_RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.tx_tp_kbits);
++
++	if (rx_tp_mbips) 
++		_RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
++	else
++		_RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.rx_tp_kbits);
++
++	if (bi_tp_mbips)
++		_RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
++	else
++		_RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
++
++
++	_RTW_PRINT_SEL(sel, "RTW: [Smooth TP] ");
++	tx_tp_mbips = psta->sta_stats.smooth_tx_tp_kbits >> 10;
++	rx_tp_mbips = psta->sta_stats.smooth_rx_tp_kbits >> 10;
++	bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
++	if (tx_tp_mbips)
++		_RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
++	else
++		_RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.smooth_tx_tp_kbits);
++
++	if (rx_tp_mbips) 
++		_RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
++	else
++		_RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.smooth_rx_tp_kbits);
++
++	if (bi_tp_mbips)
++		_RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
++	else
++		_RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.smooth_tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
++
++	#if 0
++	RTW_PRINT_SEL(sel, "Moving-AVG TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\n\n",
++		(psta->cmn.tx_moving_average_tp << 3), (psta->cmn.rx_moving_average_tp << 3),
++		(psta->cmn.tx_moving_average_tp + psta->cmn.rx_moving_average_tp) << 3);
++	#endif
++}
++
++void dump_sta_info(void *sel, struct sta_info *psta)
++{
++	struct ra_sta_info *ra_info;
++	u8 curr_tx_sgi = _FALSE;
++	u8 curr_tx_rate = 0;
++
++	if (!psta)
++		return;
++
++	ra_info = &psta->cmn.ra_info;
++
++	RTW_PRINT_SEL(sel, "============ STA [" MAC_FMT "]  ===================\n",
++		MAC_ARG(psta->cmn.mac_addr));
++	RTW_PRINT_SEL(sel, "mac_id : %d\n", psta->cmn.mac_id);
++	RTW_PRINT_SEL(sel, "wireless_mode : 0x%02x\n", psta->wireless_mode);
++	RTW_PRINT_SEL(sel, "mimo_type : %d\n", psta->cmn.mimo_type);
++	RTW_PRINT_SEL(sel, "static smps : %s\n", (psta->cmn.sm_ps == SM_PS_STATIC) ? "Y" : "N");
++	RTW_PRINT_SEL(sel, "bw_mode : %s, ra_bw_mode : %s\n",
++			ch_width_str(psta->cmn.bw_mode), ch_width_str(ra_info->ra_bw_mode));
++	RTW_PRINT_SEL(sel, "rate_id : %d\n", ra_info->rate_id);
++	RTW_PRINT_SEL(sel, "rssi : %d (%%), rssi_level : %d\n", psta->cmn.rssi_stat.rssi, ra_info->rssi_level);
++	RTW_PRINT_SEL(sel, "is_support_sgi : %s, is_vht_enable : %s\n",
++			(ra_info->is_support_sgi) ? "Y" : "N", (ra_info->is_vht_enable) ? "Y" : "N");
++	RTW_PRINT_SEL(sel, "disable_ra : %s, disable_pt : %s\n",
++				(ra_info->disable_ra) ? "Y" : "N", (ra_info->disable_pt) ? "Y" : "N");
++	RTW_PRINT_SEL(sel, "is_noisy : %s\n", (ra_info->is_noisy) ? "Y" : "N");
++	RTW_PRINT_SEL(sel, "txrx_state : %d\n", ra_info->txrx_state);/*0: uplink, 1:downlink, 2:bi-direction*/
++
++	curr_tx_sgi = rtw_get_current_tx_sgi(psta->padapter, psta);
++	curr_tx_rate = rtw_get_current_tx_rate(psta->padapter, psta);
++	RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n",
++			HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L");
++	RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw));
++	RTW_PRINT_SEL(sel, "curr_retry_ratio : %d\n", ra_info->curr_retry_ratio);
++	RTW_PRINT_SEL(sel, "ra_mask : 0x%016llx\n\n", ra_info->ramask);
++}
++
++void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++
++	if (psta == NULL) {
++		RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(adapter));
++		rtw_warn_on(1);
++		return;
++	}
++
++	if (psta->cmn.mac_id >= macid_ctl->num)
++		return;
++
++	phydm_ra_registed(&hal_data->odmpriv, psta->cmn.mac_id, psta->cmn.rssi_stat.rssi);
++	dump_sta_info(RTW_DBGDUMP, psta);
++}
++
++static void init_phydm_info(_adapter *adapter)
++{
++	PHAL_DATA_TYPE	hal_data = GET_HAL_DATA(adapter);
++	struct dm_struct *phydm = &(hal_data->odmpriv);
++
++	odm_cmn_info_init(phydm, ODM_CMNINFO_FW_VER, hal_data->firmware_version);
++	odm_cmn_info_init(phydm, ODM_CMNINFO_FW_SUB_VER, hal_data->firmware_sub_version);
++}
++
++#ifdef CONFIG_CTRL_TXSS_BY_TP
++void rtw_phydm_trx_cfg(_adapter *adapter, bool tx_1ss)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	enum bb_path txpath = BB_PATH_AB;
++	enum bb_path rxpath = BB_PATH_AB;
++	/*is_2tx = _FALSE for 8822B, or BB_PATH_AUTO for PATH_DIVERSITY for 8822B*/
++	enum bb_path txpath_1ss = BB_PATH_A;
++
++	rtw_hal_get_trx_path(adapter_to_dvobj(adapter), NULL, &txpath, &rxpath);
++	txpath = (tx_1ss) ? BB_PATH_A : txpath;
++
++	if (phydm_api_trx_mode(adapter_to_phydm(adapter), txpath, rxpath, txpath_1ss) == FALSE)
++		RTW_ERR("%s failed\n", __func__);
++}
++#endif
++
++
++/*
++* trx_mode init - 8822B / 8822C / 8192F
++* 1ssNTx - 8192E / 8812A / 8822B / 8822C / 8192F
++* Path-diversity - 8822B / 8822C / 8192F
++* PHYDM API - phydm_api_trx_mode
++*/
++static u8 rtw_phydm_config_trx_path(_adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	enum bb_path txpath;
++	enum bb_path rxpath;
++	int i;
++	u8 rst = _FAIL;
++
++	rtw_hal_get_trx_path(adapter_to_dvobj(adapter), NULL, &txpath, &rxpath);
++	if (!txpath) {
++		RTW_ERR("%s tx_path_bmp is empty\n", __func__);
++		rtw_warn_on(1);
++		goto exit;
++	}
++	if (!rxpath) {
++		RTW_ERR("%s rx_path_bmp is empty\n", __func__);
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	tx_path_nss_set_default(hal_data->txpath_nss, hal_data->txpath_num_nss
++		, GET_HAL_TX_PATH_BMP(adapter));
++
++#if defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B) ||defined(CONFIG_RTL8822C)
++{
++	enum bb_path txpath_1ss;
++
++	if (txpath == BB_PATH_AB) {
++		switch (hal_data->max_tx_cnt) {
++		case 2:
++			#ifdef CONFIG_RTW_TX_NPATH_EN
++			if (adapter->registrypriv.tx_npath == 1)
++				txpath_1ss = BB_PATH_AB;
++			else
++			#endif
++			#ifdef CONFIG_RTW_PATH_DIV
++			if (adapter->registrypriv.path_div == 1) /* path diversity, support 2sts TX */
++				txpath_1ss = BB_PATH_AUTO;
++			else
++			#endif
++				txpath_1ss = BB_PATH_A;
++			break;
++		case 1:
++			#ifdef CONFIG_RTW_PATH_DIV
++			if (adapter->registrypriv.path_div == 1) /* path diversity, no support 2sts TX */
++				txpath = txpath_1ss = BB_PATH_AUTO;
++			else
++			#endif
++				txpath = txpath_1ss = BB_PATH_A;
++			break;
++		default:
++			RTW_ERR("%s invalid max_tx_cnt:%u\n", __func__
++				, hal_data->max_tx_cnt);
++			rtw_warn_on(1);
++			goto exit;
++		}
++	} else 
++		txpath_1ss = txpath;
++
++	if (phydm_api_trx_mode(adapter_to_phydm(adapter), txpath, rxpath, txpath_1ss) == FALSE) {
++		RTW_ERR("%s txpath=0x%x, rxpath=0x%x, txpath_1ss=0x%x fail\n", __func__
++			, txpath, rxpath, txpath_1ss);
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (hal_data->txpath_nss[0] != txpath_1ss) {
++		hal_data->txpath_nss[0] = txpath_1ss;
++		if (txpath_1ss == BB_PATH_AUTO)
++			hal_data->txpath_num_nss[0] = 1;
++		else {
++			hal_data->txpath_num_nss[0] = 0;
++			for (i = 0; i < RF_PATH_MAX; i++) {
++				if (txpath_1ss & BIT(i))
++					hal_data->txpath_num_nss[0]++;
++			}
++		}
++	}
++}
++#elif defined(CONFIG_RTL8814B)
++{
++	if (config_phydm_trx_mode_8814b(adapter_to_phydm(adapter), txpath, rxpath) == FALSE) {
++		RTW_ERR("%s txpath=0x%x, rxpath=0x%x fail\n", __func__
++			, txpath, rxpath);
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	/* 8814B is always full-TX */
++	tx_path_nss_set_full_tx(hal_data->txpath_nss, hal_data->txpath_num_nss, txpath);
++}
++#elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8192E)
++{
++	#ifdef CONFIG_RTW_TX_NPATH_EN
++	if (adapter->registrypriv.tx_npath == 1) {
++		phydm_tx_2path(adapter_to_phydm(adapter));
++		tx_path_nss_set_full_tx(hal_data->txpath_nss, hal_data->txpath_num_nss, txpath);
++	}
++	#endif
++}
++#endif
++
++	hal_data->txpath = txpath;
++	hal_data->rxpath = rxpath;
++	dump_hal_runtime_trx_mode(RTW_DBGDUMP, adapter);
++	rst = _SUCCESS;
++
++exit:
++	return rst;
++}
++
++void rtw_phydm_init(_adapter *adapter)
++{
++	PHAL_DATA_TYPE	hal_data = GET_HAL_DATA(adapter);
++	struct dm_struct	*phydm = &(hal_data->odmpriv);
++
++	rtw_phydm_config_trx_path(adapter);
++	init_phydm_info(adapter);
++	hal_data->phydm_init_result = odm_dm_init(phydm);
++
++#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
++	phydm_pathb_q_matrix_rotate_en(phydm);
++#endif
++}
++
++bool rtw_phydm_set_crystal_cap(_adapter *adapter, u8 crystal_cap)
++{
++	PHAL_DATA_TYPE	hal_data = GET_HAL_DATA(adapter);
++	struct dm_struct	*phydm = &(hal_data->odmpriv);
++
++	return phydm_set_crystal_cap_reg(phydm, crystal_cap);
++}
++
++#ifdef CONFIG_LPS_PG
++/*
++static void _lps_pg_state_update(_adapter *adapter)
++{
++	u8	is_in_lpspg = _FALSE;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(adapter);
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	struct sta_priv *pstapriv = &adapter->stapriv;
++	struct sta_info *psta = NULL;
++
++	if ((pwrpriv->lps_level == LPS_PG) && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) && (pwrpriv->rpwm <= PS_STATE_S2))
++		is_in_lpspg = _TRUE;
++	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
++
++	if (psta)
++		psta->cmn.ra_info.disable_ra = (is_in_lpspg) ? _TRUE : _FALSE;
++}
++*/
++void rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg)
++{
++	struct dm_struct *phydm = adapter_to_phydm(adapter);
++	/*u8 rate_id;*/
++
++	if(sta == NULL) {
++		RTW_ERR("%s sta is null\n", __func__);
++		rtw_warn_on(1);
++		return;
++	}
++
++	if (in_lpspg) {
++		sta->cmn.ra_info.disable_ra = _TRUE;
++		sta->cmn.ra_info.disable_pt = _TRUE;
++		/*TODO : DRV fix tx rate*/
++		/*rate_id = phydm_get_rate_from_rssi_lv(phydm, sta->cmn.mac_id);*/
++	} else {
++		sta->cmn.ra_info.disable_ra = _FALSE;
++		sta->cmn.ra_info.disable_pt = _FALSE;
++	}
++
++	rtw_phydm_ra_registed(adapter, sta);
++}
++#endif
++
++/*#define DBG_PHYDM_STATE_CHK*/
++
++
++static u8 _rtw_phydm_rfk_condition_check(_adapter *adapter, u8 is_scaning, u8 ifs_linked)
++{
++	u8 rfk_allowed = _TRUE;
++
++	#ifdef CONFIG_SKIP_RFK_IN_DM
++	rfk_allowed = _FALSE;
++	if (0)
++		RTW_ERR("[RFK-CHK] RF-K not allowed due to CONFIG_SKIP_RFK_IN_DM\n");
++	return rfk_allowed;
++	#endif
++
++	#ifdef CONFIG_MCC_MODE
++	/*not in MCC State*/
++	if (MCC_EN(adapter) && 
++		rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
++		rfk_allowed = _FALSE;
++		if (0)
++			RTW_INFO("[RFK-CHK] RF-K not allowed due to doing MCC\n");
++		return rfk_allowed;
++	}
++	#endif
++
++	#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
++
++	#endif
++
++	if (ifs_linked) {
++		if (is_scaning) {
++			rfk_allowed = _FALSE;
++			RTW_DBG("[RFK-CHK] RF-K not allowed due to ifaces under site-survey\n");
++		}
++		else {
++			rfk_allowed = rtw_mi_stayin_union_ch_chk(adapter) ? _TRUE : _FALSE;
++			if (rfk_allowed == _FALSE)
++				RTW_ERR("[RFK-CHK] RF-K not allowed due to ld_iface not stayin union ch\n");
++		}
++	}
++
++	return rfk_allowed;
++}
++
++#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
++static u8 _rtw_phydm_iqk_segment_chk(_adapter *adapter, u8 ifs_linked)
++{
++	u8 iqk_sgt = _FALSE;
++
++#if 0
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	if (ifs_linked && (dvobj->traffic_stat.cur_tx_tp > 2 || dvobj->traffic_stat.cur_rx_tp > 2))
++		rst = _TRUE;
++#else
++	if (ifs_linked)
++		iqk_sgt = _TRUE;
++#endif
++	return iqk_sgt;
++}
++#endif
++
++/*check the tx low rate while unlinked to any AP;for pwr tracking */
++static u8 _rtw_phydm_pwr_tracking_rate_check(_adapter *adapter)
++{
++	int i;
++	_adapter *iface;
++	u8		if_tx_rate = 0xFF;
++	u8		tx_rate = 0xFF;
++	struct mlme_ext_priv	*pmlmeext = NULL;
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		pmlmeext = &(iface->mlmeextpriv);
++		if ((iface) && rtw_is_adapter_up(iface)) {
++#ifdef CONFIG_P2P
++			if (!rtw_p2p_chk_role(&(iface)->wdinfo, P2P_ROLE_DISABLE))
++				if_tx_rate = IEEE80211_OFDM_RATE_6MB;
++			else
++#endif
++				if_tx_rate = pmlmeext->tx_rate;
++
++			if (if_tx_rate < tx_rate) {
++				/*5G limit ofdm rate*/
++				if (pHalData->current_channel > 14) {
++					if (!IS_CCK_RATE(if_tx_rate))
++						tx_rate = if_tx_rate;
++				} else {
++					tx_rate = if_tx_rate;
++				}
++			}
++			RTW_DBG("%s i=%d if_tx_rate =0x%x\n", __func__, i, if_tx_rate);
++		}
++	}
++
++	/*suggest by RF James,unlinked setting ofdm rate*/
++	if (tx_rate == 0xFF)
++		tx_rate = IEEE80211_OFDM_RATE_6MB;
++
++	RTW_DBG("%s tx_low_rate (unlinked to any AP)=0x%x\n", __func__, tx_rate);
++	return tx_rate;
++}
++
++#ifdef CONFIG_DYNAMIC_SOML
++void rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size)
++{
++	struct dm_struct *phydm = adapter_to_phydm(adapter);
++
++	phydm_soml_bytes_acq(phydm, data_rate, size);
++}
++
++void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl,
++			u8 period, u8 delay)
++{
++	struct dm_struct *phydm = adapter_to_phydm(adapter);
++
++	phydm_adaptive_soml_para_set(phydm, train_num, intvl, period, delay);
++	RTW_INFO("%s.\n", __func__);
++}
++
++void rtw_dyn_soml_config(_adapter *adapter)
++{
++	RTW_INFO("%s.\n", __func__);
++
++	if (adapter->registrypriv.dyn_soml_en == 1) {
++		/* Must after phydm_adaptive_soml_init() */
++		rtw_hal_set_hwreg(adapter , HW_VAR_SET_SOML_PARAM , NULL);
++		RTW_INFO("dyn_soml_en = 1\n");
++	} else {
++		if (adapter->registrypriv.dyn_soml_en == 2) {
++			rtw_dyn_soml_para_set(adapter, 
++				adapter->registrypriv.dyn_soml_train_num, 
++				adapter->registrypriv.dyn_soml_interval, 
++				adapter->registrypriv.dyn_soml_period,
++				adapter->registrypriv.dyn_soml_delay);
++			RTW_INFO("dyn_soml_en = 2\n");
++			RTW_INFO("dyn_soml_en, param = %d, %d, %d, %d\n",
++				adapter->registrypriv.dyn_soml_train_num,
++				adapter->registrypriv.dyn_soml_interval, 
++				adapter->registrypriv.dyn_soml_period,
++				adapter->registrypriv.dyn_soml_delay);
++		} else if (adapter->registrypriv.dyn_soml_en == 0) {
++			RTW_INFO("dyn_soml_en = 0\n");
++		} else
++			RTW_ERR("%s, wrong setting: dyn_soml_en = %d\n", __func__,
++				adapter->registrypriv.dyn_soml_en);
++	}
++}
++#endif
++
++void rtw_phydm_set_rrsr(_adapter *adapter, u32 rrsr_value, bool write_rrsr)
++{
++	struct dm_struct *phydm = adapter_to_phydm(adapter);
++	u32 temp_rrsr =0xFFFFFFFF;
++
++	if (adapter->registrypriv.set_rrsr_value != 0xFFFFFFFF)
++		temp_rrsr = adapter->registrypriv.set_rrsr_value;
++	else
++		temp_rrsr = rrsr_value;
++
++	odm_cmn_info_update(phydm, ODM_CMNINFO_RRSR_VAL, temp_rrsr);
++	if(write_rrsr)
++		phydm_rrsr_set_register(phydm, temp_rrsr);
++}
++void rtw_phydm_dyn_rrsr_en(_adapter *adapter, bool en_rrsr)
++{
++	struct dm_struct *phydm = adapter_to_phydm(adapter);
++
++	phydm_rrsr_en(phydm, en_rrsr);
++}
++void rtw_phydm_read_efuse(_adapter *adapter)
++{
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
++	struct dm_struct *phydm = &(hal_data->odmpriv);
++
++	/*PHYDM API - thermal trim*/
++	phydm_get_thermal_trim_offset(phydm);
++	/*PHYDM API - power trim*/
++	phydm_get_power_trim_offset(phydm);
++}
++
++#ifdef CONFIG_LPS_PWR_TRACKING
++void rtw_phydm_pwr_tracking_directly(_adapter *adapter)
++{
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
++	u8 rfk_forbidden = _TRUE;
++	u8 is_linked = _FALSE;
++
++	if (rtw_mi_check_status(adapter, MI_ASSOC))
++		is_linked = _TRUE;
++
++	rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, hal_data->bScanInProcess, is_linked) == _TRUE) ? _FALSE : _TRUE;
++	halrf_cmn_info_set(&hal_data->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
++
++	odm_txpowertracking_direct_ce(&hal_data->odmpriv);
++}
++#endif
++
++void rtw_phydm_watchdog(_adapter *adapter, bool in_lps)
++{
++	u8	bLinked = _FALSE;
++	u8	bsta_state = _FALSE;
++	u8	bBtDisabled = _TRUE;
++	u8	rfk_forbidden = _FALSE;
++	#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
++	u8	segment_iqk = _FALSE;
++	#endif
++	u8	tx_unlinked_low_rate = 0xFF;
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(adapter);
++
++	if (!rtw_is_hw_init_completed(adapter)) {
++		RTW_DBG("%s skip due to hw_init_completed == FALSE\n", __func__);
++		return;
++	}
++	if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_SURVEY))
++		pHalData->bScanInProcess = _TRUE;
++	else
++		pHalData->bScanInProcess = _FALSE;
++
++	if (rtw_mi_check_status(adapter, MI_ASSOC)) {
++		bLinked = _TRUE;
++		if (rtw_mi_check_status(adapter, MI_STA_LINKED))
++		bsta_state = _TRUE;
++	}
++
++	odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked);
++	odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state);
++
++	#ifdef CONFIG_BT_COEXIST
++	bBtDisabled = rtw_btcoex_IsBtDisabled(adapter);
++	odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED,
++				(bBtDisabled == _TRUE) ? _FALSE : _TRUE);
++	#else
++	odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED, _FALSE);
++	#endif /* CONFIG_BT_COEXIST */
++
++	rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, pHalData->bScanInProcess, bLinked) == _TRUE) ? _FALSE : _TRUE;
++	halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
++
++	#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
++	segment_iqk = _rtw_phydm_iqk_segment_chk(adapter, bLinked);
++	halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_IQK_SEGMENT, segment_iqk);
++	#endif
++	#ifdef DBG_PHYDM_STATE_CHK
++	RTW_INFO("%s rfk_forbidden = %s, segment_iqk = %s\n",
++			__func__, (rfk_forbidden) ? "Y" : "N", (segment_iqk) ? "Y" : "N");
++	#endif
++
++	if (bLinked == _FALSE) {
++		tx_unlinked_low_rate = _rtw_phydm_pwr_tracking_rate_check(adapter);
++		halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RATE_INDEX, tx_unlinked_low_rate);
++	}
++
++	/*if (!rtw_mi_stayin_union_band_chk(adapter)) {
++		#ifdef DBG_PHYDM_STATE_CHK
++		RTW_ERR("Not stay in union band, skip phydm\n");
++		#endif
++		goto _exit;
++	}*/
++
++	#ifdef CONFIG_TDMADIG
++	rtw_phydm_tdmadig(adapter, TDMADIG_NON_INIT);
++	#endif/*CONFIG_TDMADIG*/
++
++	if (in_lps)
++		phydm_watchdog_lps(&pHalData->odmpriv);
++	else
++		phydm_watchdog(&pHalData->odmpriv);
++
++	#ifdef CONFIG_RTW_ACS
++	rtw_acs_update_current_info(adapter);
++	#endif
++
++	return;
++}
++
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_dm.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_dm.h
+new file mode 100644
+index 000000000..53a2aedbd
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_dm.h
+@@ -0,0 +1,118 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL_DM_H__
++#define __HAL_DM_H__
++
++#define adapter_to_phydm(adapter) (&(GET_HAL_DATA(adapter)->odmpriv))
++#define dvobj_to_phydm(dvobj) adapter_to_phydm(dvobj_get_primary_adapter(dvobj))
++#ifdef CONFIG_TDMADIG
++void rtw_phydm_tdmadig(_adapter *adapter, u8 state);
++#endif
++void rtw_phydm_priv_init(_adapter *adapter);
++void Init_ODM_ComInfo(_adapter *adapter);
++void rtw_phydm_init(_adapter *adapter);
++
++void rtw_hal_turbo_edca(_adapter *adapter);
++u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter);
++
++void GetHalODMVar(
++	PADAPTER				Adapter,
++	HAL_ODM_VARIABLE		eVariable,
++	void						*pValue1,
++	void						*pValue2);
++void SetHalODMVar(
++	PADAPTER				Adapter,
++	HAL_ODM_VARIABLE		eVariable,
++	void						*pValue1,
++	BOOLEAN					bSet);
++
++void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta);
++
++#ifdef CONFIG_DYNAMIC_SOML
++void rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size);
++void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl,
++			u8 period, u8 delay);
++void rtw_dyn_soml_config(_adapter *adapter);
++#endif
++void rtw_phydm_set_rrsr(_adapter *adapter, u32 rrsr_value, bool write_rrsr);
++void rtw_phydm_dyn_rrsr_en(_adapter *adapter, bool en_rrsr);
++void rtw_phydm_watchdog(_adapter *adapter, bool in_lps);
++
++void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter);
++void dump_sta_info(void *sel, struct sta_info *psta);
++void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta);
++
++#ifdef CONFIG_DBG_RF_CAL
++void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment);
++void rtw_hal_lck_test(_adapter *adapter);
++#endif
++
++s8 rtw_dm_get_min_rssi(_adapter *adapter);
++s8 rtw_phydm_get_min_rssi(_adapter *adapter);
++u8 rtw_phydm_get_cur_igi(_adapter *adapter);
++bool rtw_phydm_get_edcca_flag(_adapter *adapter);
++
++
++#ifdef CONFIG_LPS_LCLK_WD_TIMER
++extern void phydm_rssi_monitor_check(void *p_dm_void);
++
++void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter);
++void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter);
++#endif
++#ifdef CONFIG_TDMADIG
++enum rtw_tdmadig_state{
++	TDMADIG_INIT,
++	TDMADIG_NON_INIT,
++};
++#endif
++enum phy_cnt {
++	FA_OFDM,
++	FA_CCK,
++	FA_TOTAL,
++	CCA_OFDM,
++	CCA_CCK,
++	CCA_ALL,
++	CRC32_OK_VHT,
++	CRC32_OK_HT,
++	CRC32_OK_LEGACY,
++	CRC32_OK_CCK,
++	CRC32_ERROR_VHT,
++	CRC32_ERROR_HT,
++	CRC32_ERROR_LEGACY,
++	CRC32_ERROR_CCK,
++};
++u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt);
++#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
++void rtw_phydm_iqk_trigger(_adapter *adapter);
++#endif
++void rtw_phydm_read_efuse(_adapter *adapter);
++bool rtw_phydm_set_crystal_cap(_adapter *adapter, u8 crystal_cap);
++
++#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
++void rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id);
++#endif
++
++#ifdef CONFIG_LPS_PG
++void rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg);
++#endif
++#ifdef CONFIG_LPS_PWR_TRACKING
++void rtw_phydm_pwr_tracking_directly(_adapter *adapter);
++#endif
++
++#ifdef CONFIG_CTRL_TXSS_BY_TP
++void rtw_phydm_trx_cfg(_adapter *adapter, bool tx_1ss);
++#endif
++
++#endif /* __HAL_DM_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_dm_acs.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_dm_acs.c
+new file mode 100644
+index 000000000..f29ccf1e8
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_dm_acs.c
+@@ -0,0 +1,554 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2014 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#include <drv_types.h>
++#include <hal_data.h>
++
++
++#if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)
++static void _rtw_bss_nums_count(_adapter *adapter, u8 *pbss_nums)
++{
++	struct mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
++	_queue *queue = &(pmlmepriv->scanned_queue);
++	struct wlan_network *pnetwork = NULL;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++
++	_list	*plist, *phead;
++	_irqL irqL;
++	int chan_idx = -1;
++
++	if (pbss_nums == NULL) {
++		RTW_ERR("%s pbss_nums is null pointer\n", __func__);
++		return;
++	}
++	_rtw_memset(pbss_nums, 0, MAX_CHANNEL_NUM);
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++	while (1) {
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++		if (!pnetwork)
++			break;
++		chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), pnetwork->network.Configuration.DSConfig);
++		if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
++			RTW_ERR("%s can't get chan_idx(CH:%d)\n",
++				__func__, pnetwork->network.Configuration.DSConfig);
++			chan_idx = 0;
++		}
++		/*if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ)*/
++
++		pbss_nums[chan_idx]++;
++
++		plist = get_next(plist);
++	}
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++}
++
++u8 rtw_get_ch_num_by_idx(_adapter *adapter, u8 idx)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	RT_CHANNEL_INFO *pch_set = rfctl->channel_set;
++	u8 max_chan_nums = rfctl->max_chan_nums;
++
++	if (idx >= max_chan_nums)
++		return 0;
++	return pch_set[idx].ChannelNum;
++}
++#endif /*defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)*/
++
++
++#ifdef CONFIG_RTW_ACS
++void rtw_acs_version_dump(void *sel, _adapter *adapter)
++{
++	_RTW_PRINT_SEL(sel, "RTK_ACS VER_%d\n", RTK_ACS_VERSION);
++}
++u8 rtw_phydm_clm_ratio(_adapter *adapter)
++{
++	struct dm_struct *phydm = adapter_to_phydm(adapter);
++
++	return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CLM_RATIO);
++}
++u8 rtw_phydm_nhm_ratio(_adapter *adapter)
++{
++	struct dm_struct *phydm = adapter_to_phydm(adapter);
++
++	return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_NHM_RATIO);
++}
++void rtw_acs_reset(_adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct auto_chan_sel *pacs = &hal_data->acs;
++
++	_rtw_memset(pacs, 0, sizeof(struct auto_chan_sel));
++	#ifdef CONFIG_RTW_ACS_DBG
++	rtw_acs_adv_reset(adapter);
++	#endif /*CONFIG_RTW_ACS_DBG*/
++}
++
++#ifdef CONFIG_RTW_ACS_DBG
++u8 rtw_is_acs_igi_valid(_adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct auto_chan_sel *pacs = &hal_data->acs;
++
++	if ((pacs->igi) && ((pacs->igi >= 0x1E) || (pacs->igi < 0x60)))
++		return _TRUE;
++
++	return _FALSE;
++}
++void rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct auto_chan_sel *pacs = &hal_data->acs;
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
++
++	pacs->scan_type = scan_type;
++	pacs->scan_time = scan_time;
++	pacs->igi = igi;
++	pacs->bw = bw;
++	RTW_INFO("[ACS] ADV setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\n",
++		pacs->scan_type ? 'A' : 'P', pacs->scan_time, pacs->igi, pacs->bw);
++}
++void rtw_acs_adv_reset(_adapter *adapter)
++{
++	rtw_acs_adv_setting(adapter, SCAN_ACTIVE, 0, 0, 0);
++}
++#endif /*CONFIG_RTW_ACS_DBG*/
++
++void rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct dm_struct *phydm = adapter_to_phydm(adapter);
++#if (RTK_ACS_VERSION == 3)
++	struct clm_para_info clm_para;
++	struct nhm_para_info nhm_para;
++	struct env_trig_rpt trig_rpt;
++
++	scan_time_ms -= 10;
++
++	init_acs_clm(clm_para, scan_time_ms);
++
++	if (pid == NHM_PID_IEEE_11K_HIGH)
++		init_11K_high_nhm(nhm_para, scan_time_ms);
++	else if (pid == NHM_PID_IEEE_11K_LOW)
++		init_11K_low_nhm(nhm_para, scan_time_ms);
++	else
++		init_acs_nhm(nhm_para, scan_time_ms);
++
++	hal_data->acs.trig_rst = phydm_env_mntr_trigger(phydm, &nhm_para, &clm_para, &trig_rpt);
++	if (hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS)) {
++		hal_data->acs.trig_rpt.clm_rpt_stamp = trig_rpt.clm_rpt_stamp;
++		hal_data->acs.trig_rpt.nhm_rpt_stamp = trig_rpt.nhm_rpt_stamp;
++		/*RTW_INFO("[ACS] trigger success (rst = 0x%02x, clm_stamp:%d, nhm_stamp:%d)\n",
++			hal_data->acs.trig_rst, hal_data->acs.trig_rpt.clm_rpt_stamp, hal_data->acs.trig_rpt.nhm_rpt_stamp);*/
++	} else
++		RTW_ERR("[ACS] trigger failed (rst = 0x%02x)\n", hal_data->acs.trig_rst);
++#else
++	phydm_ccx_monitor_trigger(phydm, scan_time_ms);
++#endif
++
++	hal_data->acs.trigger_ch = scan_chan;
++	hal_data->acs.triggered = _TRUE;
++
++	#ifdef CONFIG_RTW_ACS_DBG
++	RTW_INFO("[ACS] Trigger CH:%d, Times:%d\n", hal_data->acs.trigger_ch, scan_time_ms);
++	#endif
++}
++void rtw_acs_get_rst(_adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct dm_struct *phydm = adapter_to_phydm(adapter);
++	int chan_idx = -1;
++	u8 cur_chan = hal_data->acs.trigger_ch;
++
++	if (cur_chan == 0)
++		return;
++
++	if (!hal_data->acs.triggered)
++		return;
++
++	chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), cur_chan);
++	if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
++		RTW_ERR("[ACS] %s can't get chan_idx(CH:%d)\n", __func__, cur_chan);
++		return;
++	}
++#if (RTK_ACS_VERSION == 3)
++	if (!(hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS))) {
++		RTW_ERR("[ACS] get_rst return, due to acs trigger failed\n");
++		return;
++	}
++
++	{
++		struct env_mntr_rpt rpt = {0};
++		u8 rst;
++
++		rst = phydm_env_mntr_result(phydm, &rpt);
++		if ((rst == (NHM_SUCCESS | CLM_SUCCESS)) &&
++			(rpt.clm_rpt_stamp == hal_data->acs.trig_rpt.clm_rpt_stamp) &&
++			(rpt.nhm_rpt_stamp == hal_data->acs.trig_rpt.nhm_rpt_stamp)){
++			hal_data->acs.clm_ratio[chan_idx] = rpt.clm_ratio;
++			hal_data->acs.nhm_ratio[chan_idx] = rpt.nhm_ratio;
++			_rtw_memcpy(&hal_data->acs.nhm[chan_idx][0], rpt.nhm_result, NHM_RPT_NUM);
++
++			/*RTW_INFO("[ACS] get_rst success (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\n",
++			rst,
++			hal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp,
++			hal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp);*/
++		} else {
++			RTW_ERR("[ACS] get_rst failed (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\n",
++			rst,
++			hal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp,
++			hal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp);
++		}
++	}
++
++#else
++	phydm_ccx_monitor_result(phydm);
++
++	hal_data->acs.clm_ratio[chan_idx] = rtw_phydm_clm_ratio(adapter);
++	hal_data->acs.nhm_ratio[chan_idx] = rtw_phydm_nhm_ratio(adapter);
++#endif
++	hal_data->acs.triggered = _FALSE;
++	#ifdef CONFIG_RTW_ACS_DBG
++	RTW_INFO("[ACS] Result CH:%d, CLM:%d NHM:%d\n",
++		cur_chan, hal_data->acs.clm_ratio[chan_idx], hal_data->acs.nhm_ratio[chan_idx]);
++	#endif
++}
++
++void _rtw_phydm_acs_select_best_chan(_adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	u8 ch_idx;
++	u8 ch_idx_24g = 0xFF, ch_idx_5g = 0xFF;
++	u8 min_itf_24g = 0xFF,  min_itf_5g = 0xFF;
++	u8 *pbss_nums = hal_data->acs.bss_nums;
++	u8 *pclm_ratio = hal_data->acs.clm_ratio;
++	u8 *pnhm_ratio = hal_data->acs.nhm_ratio;
++	u8 *pinterference_time = hal_data->acs.interference_time;
++	u8 max_chan_nums = rfctl->max_chan_nums;
++
++	for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
++		if (pbss_nums[ch_idx])
++			pinterference_time[ch_idx] = (pclm_ratio[ch_idx] / 2) + (pnhm_ratio[ch_idx] / 2);
++		else
++			pinterference_time[ch_idx] = (pclm_ratio[ch_idx] / 3) + ((pnhm_ratio[ch_idx] * 2) / 3);
++
++		if (rtw_get_ch_num_by_idx(adapter, ch_idx) < 14) {
++			if (pinterference_time[ch_idx] < min_itf_24g) {
++				min_itf_24g = pinterference_time[ch_idx];
++				ch_idx_24g = ch_idx;
++			}
++		} else {
++			if (pinterference_time[ch_idx] < min_itf_5g) {
++				min_itf_5g = pinterference_time[ch_idx];
++				ch_idx_5g = ch_idx;
++			}
++		}
++	}
++	if (ch_idx_24g != 0xFF)
++		hal_data->acs.best_chan_24g = rtw_get_ch_num_by_idx(adapter, ch_idx_24g);
++
++	if (ch_idx_5g != 0xFF)
++		hal_data->acs.best_chan_5g = rtw_get_ch_num_by_idx(adapter, ch_idx_5g);
++
++	hal_data->acs.trigger_ch = 0;
++}
++
++void rtw_acs_info_dump(void *sel, _adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	u8 max_chan_nums = rfctl->max_chan_nums;
++	u8 ch_idx, ch_num;
++
++	_RTW_PRINT_SEL(sel, "========== ACS (VER-%d) ==========\n", RTK_ACS_VERSION);
++	_RTW_PRINT_SEL(sel, "Best 24G Channel:%d\n", hal_data->acs.best_chan_24g);
++	_RTW_PRINT_SEL(sel, "Best 5G Channel:%d\n\n", hal_data->acs.best_chan_5g);
++
++	#ifdef CONFIG_RTW_ACS_DBG
++	_RTW_PRINT_SEL(sel, "Advanced setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\n",
++		hal_data->acs.scan_type ? 'A' : 'P', hal_data->acs.scan_time, hal_data->acs.igi, hal_data->acs.bw);
++
++	_RTW_PRINT_SEL(sel, "BW  20MHz\n");
++	_RTW_PRINT_SEL(sel, "%5s  %3s  %3s  %3s(%%)  %3s(%%)  %3s\n",
++						"Index", "CH", "BSS", "CLM", "NHM", "ITF");
++
++	for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
++		ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
++		_RTW_PRINT_SEL(sel, "%5d  %3d  %3d  %6d  %6d  %3d\n",
++						ch_idx, ch_num, hal_data->acs.bss_nums[ch_idx],
++						hal_data->acs.clm_ratio[ch_idx],
++						hal_data->acs.nhm_ratio[ch_idx],
++						hal_data->acs.interference_time[ch_idx]);
++	}
++	#endif
++}
++void rtw_acs_select_best_chan(_adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++
++	_rtw_bss_nums_count(adapter, hal_data->acs.bss_nums);
++	_rtw_phydm_acs_select_best_chan(adapter);
++	rtw_acs_info_dump(RTW_DBGDUMP, adapter);
++}
++
++void rtw_acs_start(_adapter *adapter)
++{
++	rtw_acs_reset(adapter);
++	if (GET_ACS_STATE(adapter) != ACS_ENABLE)
++		SET_ACS_STATE(adapter, ACS_ENABLE);
++}
++void rtw_acs_stop(_adapter *adapter)
++{
++	SET_ACS_STATE(adapter, ACS_DISABLE);
++}
++
++
++u8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	int chan_idx = -1;
++
++	chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
++	if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
++		RTW_ERR("[ACS] Get CLM fail, can't get chan_idx(CH:%d)\n", chan);
++		return 0;
++	}
++
++	return hal_data->acs.clm_ratio[chan_idx];
++}
++u8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++
++	if (ch_idx >= MAX_CHANNEL_NUM) {
++		RTW_ERR("%s [ACS] ch_idx(%d) is invalid\n", __func__, ch_idx);
++		return 0;
++	}
++
++	return hal_data->acs.clm_ratio[ch_idx];
++}
++u8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	int chan_idx = -1;
++
++	chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
++	if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
++		RTW_ERR("[ACS] Get NHM fail, can't get chan_idx(CH:%d)\n", chan);
++		return 0;
++	}
++
++	return hal_data->acs.nhm_ratio[chan_idx];
++}
++u8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++
++	if (ch_idx >= MAX_CHANNEL_NUM) {
++		RTW_ERR("%s [ACS] ch_idx(%d) is invalid\n", __func__, ch_idx);
++		return 0;
++	}
++
++	return hal_data->acs.nhm_ratio[ch_idx];
++}
++void rtw_acs_chan_info_dump(void *sel, _adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	u8 max_chan_nums = rfctl->max_chan_nums;
++	u8 ch_idx, ch_num;
++	u8 utilization;
++
++	_RTW_PRINT_SEL(sel, "BW  20MHz\n");
++	_RTW_PRINT_SEL(sel, "%5s  %3s  %7s(%%)  %12s(%%)  %11s(%%)  %9s(%%)  %8s(%%)\n",
++						"Index", "CH", "Quality", "Availability", "Utilization",
++						"WIFI Util", "Interference Util");
++
++	for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
++		ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
++		utilization = hal_data->acs.clm_ratio[ch_idx] + hal_data->acs.nhm_ratio[ch_idx];
++		_RTW_PRINT_SEL(sel, "%5d  %3d  %7d   %12d   %12d   %12d   %12d\n",
++						ch_idx, ch_num,
++						(100-hal_data->acs.interference_time[ch_idx]),
++						(100-utilization),
++						utilization,
++						hal_data->acs.clm_ratio[ch_idx],
++						hal_data->acs.nhm_ratio[ch_idx]);
++	}
++}
++void rtw_acs_current_info_dump(void *sel, _adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	u8 ch, cen_ch, bw, offset;
++
++	_RTW_PRINT_SEL(sel, "========== ACS (VER-%d) ==========\n", RTK_ACS_VERSION);
++
++	ch = rtw_get_oper_ch(adapter);
++	bw = rtw_get_oper_bw(adapter);
++	offset = rtw_get_oper_choffset(adapter);
++
++	_RTW_PRINT_SEL(sel, "Current Channel:%d\n", ch);
++	if ((bw == CHANNEL_WIDTH_80) ||(bw == CHANNEL_WIDTH_40)) {
++		cen_ch = rtw_get_center_ch(ch, bw, offset);
++		_RTW_PRINT_SEL(sel, "Center Channel:%d\n", cen_ch);
++	}
++
++	_RTW_PRINT_SEL(sel, "Current BW %s\n", ch_width_str(bw));
++	if (0)
++		_RTW_PRINT_SEL(sel, "Current IGI 0x%02x\n", rtw_phydm_get_cur_igi(adapter));
++	_RTW_PRINT_SEL(sel, "CLM:%d, NHM:%d\n\n",
++		hal_data->acs.cur_ch_clm_ratio, hal_data->acs.cur_ch_nhm_ratio);
++}
++
++void rtw_acs_update_current_info(_adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++
++	hal_data->acs.cur_ch_clm_ratio = rtw_phydm_clm_ratio(adapter);
++	hal_data->acs.cur_ch_nhm_ratio = rtw_phydm_nhm_ratio(adapter);
++
++	#ifdef CONFIG_RTW_ACS_DBG
++	rtw_acs_current_info_dump(RTW_DBGDUMP, adapter);
++	#endif
++}
++#endif /*CONFIG_RTW_ACS*/
++
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++void rtw_noise_monitor_version_dump(void *sel, _adapter *adapter)
++{
++	_RTW_PRINT_SEL(sel, "RTK_NOISE_MONITOR VER_%d\n", RTK_NOISE_MONITOR_VERSION);
++}
++void rtw_nm_enable(_adapter *adapter)
++{
++	SET_NM_STATE(adapter, NM_ENABLE);
++}
++void rtw_nm_disable(_adapter *adapter)
++{
++	SET_NM_STATE(adapter, NM_DISABLE);
++}
++void rtw_noise_info_dump(void *sel, _adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	u8 max_chan_nums = rfctl->max_chan_nums;
++	u8 ch_idx, ch_num;
++
++	_RTW_PRINT_SEL(sel, "========== NM (VER-%d) ==========\n", RTK_NOISE_MONITOR_VERSION);
++
++	_RTW_PRINT_SEL(sel, "%5s  %3s  %3s  %10s", "Index", "CH", "BSS", "Noise(dBm)\n");
++
++	_rtw_bss_nums_count(adapter, hal_data->nm.bss_nums);
++
++	for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
++		ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
++		_RTW_PRINT_SEL(sel, "%5d  %3d  %3d  %10d\n",
++						ch_idx, ch_num, hal_data->nm.bss_nums[ch_idx],
++						hal_data->nm.noise[ch_idx]);
++	}
++}
++
++void rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct dm_struct *phydm = &hal_data->odmpriv;
++	int chan_idx = -1;
++	s16 noise = 0;
++
++	#ifdef DBG_NOISE_MONITOR
++	RTW_INFO("[NM] chan(%d)-PauseDIG:%s,  IGIValue:0x%02x, max_time:%d (ms)\n",
++		chan, (is_pause_dig) ? "Y" : "N", igi_value, max_time);
++	#endif
++
++	chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
++	if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
++		RTW_ERR("[NM] Get noise fail, can't get chan_idx(CH:%d)\n", chan);
++		return;
++	}
++	noise = odm_inband_noise_monitor(phydm, is_pause_dig, igi_value, max_time); /*dBm*/
++
++	hal_data->nm.noise[chan_idx] = noise;
++
++	#ifdef DBG_NOISE_MONITOR
++	RTW_INFO("[NM] %s chan_%d, noise = %d (dBm)\n", __func__, chan, hal_data->nm.noise[chan_idx]);
++
++	RTW_INFO("[NM] noise_a = %d, noise_b = %d  noise_all:%d\n",
++			 phydm->noise_level.noise[RF_PATH_A],
++			 phydm->noise_level.noise[RF_PATH_B],
++			 phydm->noise_level.noise_all);
++	#endif /*DBG_NOISE_MONITOR*/
++}
++
++s16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	s16 noise = 0;
++	int chan_idx = -1;
++
++	chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
++	if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
++		RTW_ERR("[NM] Get noise fail, can't get chan_idx(CH:%d)\n", chan);
++		return noise;
++	}
++	noise = hal_data->nm.noise[chan_idx];
++
++	#ifdef DBG_NOISE_MONITOR
++	RTW_INFO("[NM] %s chan_%d, noise = %d (dBm)\n", __func__, chan, noise);
++	#endif/*DBG_NOISE_MONITOR*/
++	return noise;
++}
++s16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	s16 noise = 0;
++
++	if (ch_idx >= MAX_CHANNEL_NUM) {
++		RTW_ERR("[NM] %s ch_idx(%d) is invalid\n", __func__, ch_idx);
++		return noise;
++	}
++	noise = hal_data->nm.noise[ch_idx];
++
++	#ifdef DBG_NOISE_MONITOR
++	RTW_INFO("[NM] %s ch_idx %d, noise = %d (dBm)\n", __func__, ch_idx, noise);
++	#endif/*DBG_NOISE_MONITOR*/
++	return noise;
++}
++
++s16 rtw_noise_measure_curchan(_adapter *padapter)
++{
++	s16 noise = 0;
++	u8 igi_value = 0x1E;
++	u32 max_time = 100;/* ms */
++	u8 is_pause_dig = _TRUE;
++	u8 cur_chan = rtw_get_oper_ch(padapter);
++
++	if (rtw_linked_check(padapter) == _FALSE)
++		return noise;
++
++	rtw_ps_deny(padapter, PS_DENY_IOCTL);
++	LeaveAllPowerSaveModeDirect(padapter);
++	rtw_noise_measure(padapter, cur_chan, is_pause_dig, igi_value, max_time);
++	noise = rtw_noise_query_by_chan_num(padapter, cur_chan);
++	rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
++
++	return noise;
++}
++#endif /*CONFIG_BACKGROUND_NOISE_MONITOR*/
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_dm_acs.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_dm_acs.h
+new file mode 100644
+index 000000000..871c14487
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_dm_acs.h
+@@ -0,0 +1,167 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL_DM_ACS_H__
++#define __HAL_DM_ACS_H__
++#ifdef CONFIG_RTW_ACS
++#define RTK_ACS_VERSION	3
++
++#if (RTK_ACS_VERSION == 3)
++enum NHM_PID {
++	NHM_PID_ACS,
++	NHM_PID_IEEE_11K_HIGH,
++	NHM_PID_IEEE_11K_LOW,
++};
++
++#define init_clm_param(clm, app, lv, time) \
++	do {\
++		clm.clm_app = app;\
++		clm.clm_lv = lv;\
++		clm.mntr_time = time;\
++	} while (0)
++
++#define init_nhm_param(nhm, txon, cca, cnt_opt, app, lv, time) \
++	do {\
++		nhm.incld_txon = txon;\
++		nhm.incld_cca = cca;\
++		nhm.div_opt = cnt_opt;\
++		nhm.nhm_app = app;\
++		nhm.nhm_lv = lv;\
++		nhm.mntr_time = time;\
++	} while (0)
++
++	
++#define init_acs_clm(clm, time) \
++	init_clm_param(clm, CLM_ACS, CLM_LV_2, time)
++
++#define init_acs_nhm(nhm, time) \
++	init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, NHM_ACS, NHM_LV_2, time)
++
++#define init_11K_high_nhm(nhm, time) \
++	init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_HIGH, NHM_LV_2, time)
++	
++#define init_11K_low_nhm(nhm, time) \
++		init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_LOW, NHM_LV_2, time)
++
++
++#endif /*(RTK_ACS_VERSION == 3)*/
++void rtw_acs_version_dump(void *sel, _adapter *adapter);
++extern void phydm_ccx_monitor_trigger(void *p_dm_void, u16 monitor_time);
++extern void phydm_ccx_monitor_result(void *p_dm_void);
++
++#define GET_ACS_STATE(padapter)					(ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state))
++#define SET_ACS_STATE(padapter, set_state)			(ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state))
++#define IS_ACS_ENABLE(padapter)					((GET_ACS_STATE(padapter) == ACS_ENABLE) ? _TRUE : _FALSE)
++
++enum ACS_STATE {
++	ACS_DISABLE,
++	ACS_ENABLE,
++};
++
++#define ACS_BW_20M	BIT(0)
++#define ACS_BW_40M	BIT(1)
++#define ACS_BW_80M	BIT(2)
++#define ACS_BW_160M	BIT(3)
++
++struct auto_chan_sel {
++	ATOMIC_T state;
++	u8 trigger_ch;
++	bool triggered;
++	u8 clm_ratio[MAX_CHANNEL_NUM];
++	u8 nhm_ratio[MAX_CHANNEL_NUM];
++	#if (RTK_ACS_VERSION == 3)
++	u8 nhm[MAX_CHANNEL_NUM][NHM_RPT_NUM];
++	#endif
++	u8 bss_nums[MAX_CHANNEL_NUM];
++	u8 interference_time[MAX_CHANNEL_NUM];
++	u8 cur_ch_clm_ratio;
++	u8 cur_ch_nhm_ratio;
++	u8 best_chan_5g;
++	u8 best_chan_24g;
++
++	#if (RTK_ACS_VERSION == 3)
++	u8 trig_rst;
++	struct env_trig_rpt	trig_rpt;
++	#endif
++
++	#ifdef CONFIG_RTW_ACS_DBG
++	RT_SCAN_TYPE scan_type;
++	u16 scan_time;
++	u8 igi;
++	u8 bw;
++	#endif
++};
++
++#define rtw_acs_get_best_chan_24g(adapter)		(GET_HAL_DATA(adapter)->acs.best_chan_24g)
++#define rtw_acs_get_best_chan_5g(adapter)		(GET_HAL_DATA(adapter)->acs.best_chan_5g)
++
++#ifdef CONFIG_RTW_ACS_DBG
++#define rtw_is_acs_passiv_scan(adapter)	(((GET_HAL_DATA(adapter)->acs.scan_type) == SCAN_PASSIVE) ? _TRUE : _FALSE)
++
++#define rtw_acs_get_adv_st(adapter)	(GET_HAL_DATA(adapter)->acs.scan_time)
++#define rtw_is_acs_st_valid(adapter)	((GET_HAL_DATA(adapter)->acs.scan_time) ? _TRUE : _FALSE)
++
++#define rtw_acs_get_adv_igi(adapter)	(GET_HAL_DATA(adapter)->acs.igi)
++u8 rtw_is_acs_igi_valid(_adapter *adapter);
++
++#define rtw_acs_get_adv_bw(adapter)	(GET_HAL_DATA(adapter)->acs.bw)
++
++void rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw);
++void rtw_acs_adv_reset(_adapter *adapter);
++#endif
++
++u8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan);
++u8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx);
++u8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan);
++u8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx);
++
++void rtw_acs_reset(_adapter *adapter);
++void rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid);
++void rtw_acs_get_rst(_adapter *adapter);
++void rtw_acs_select_best_chan(_adapter *adapter);
++void rtw_acs_info_dump(void *sel, _adapter *adapter);
++void rtw_acs_update_current_info(_adapter *adapter);
++void rtw_acs_chan_info_dump(void *sel, _adapter *adapter);
++void rtw_acs_current_info_dump(void *sel, _adapter *adapter);
++
++void rtw_acs_start(_adapter *adapter);
++void rtw_acs_stop(_adapter *adapter);
++
++#endif /*CONFIG_RTW_ACS*/
++
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++#define RTK_NOISE_MONITOR_VERSION	3
++#define GET_NM_STATE(padapter)					(ATOMIC_READ(&GET_HAL_DATA(padapter)->nm.state))
++#define SET_NM_STATE(padapter, set_state)			(ATOMIC_SET(&GET_HAL_DATA(padapter)->nm.state, set_state))
++#define IS_NM_ENABLE(padapter)					((GET_NM_STATE(padapter) == NM_ENABLE) ? _TRUE : _FALSE)
++
++enum NM_STATE {
++	NM_DISABLE,
++	NM_ENABLE,
++};
++
++struct noise_monitor {
++	ATOMIC_T state;
++	s16 noise[MAX_CHANNEL_NUM];
++	u8 bss_nums[MAX_CHANNEL_NUM];
++};
++void rtw_nm_enable(_adapter *adapter);
++void rtw_nm_disable(_adapter *adapter);
++void rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time);
++s16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan);
++s16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx);
++s16 rtw_noise_measure_curchan(_adapter *padapter);
++void rtw_noise_info_dump(void *sel, _adapter *adapter);
++#endif
++#endif /* __HAL_DM_ACS_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_halmac.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_halmac.c
+new file mode 100644
+index 000000000..ac9c030fe
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_halmac.c
+@@ -0,0 +1,5868 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2015 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _HAL_HALMAC_C_
++
++#include <drv_types.h>		/* PADAPTER, struct dvobj_priv, SDIO_ERR_VAL8 and etc. */
++#include <hal_data.h>		/* efuse, PHAL_DATA_TYPE and etc. */
++#include "hal_halmac.h"		/* dvobj_to_halmac() and ect. */
++
++/*
++ * HALMAC take return value 0 for fail and 1 for success to replace
++ * _FALSE/_TRUE after V1_04_09
++ */
++#define RTW_HALMAC_FAIL			0
++#define RTW_HALMAC_SUCCESS		1
++
++#define DEFAULT_INDICATOR_TIMELMT	1000	/* ms */
++#define MSG_PREFIX			"[HALMAC]"
++
++#define RTW_HALMAC_DLFW_MEM_NO_STOP_TX
++#define RTW_HALMAC_FILTER_DRV_C2H	/* Block C2H owner=driver */
++
++/*
++ * Driver API for HALMAC operations
++ */
++
++#ifdef CONFIG_SDIO_HCI
++#include <rtw_sdio.h>
++
++static u8 _halmac_mac_reg_page0_chk(const char *func, struct dvobj_priv *dvobj, u32 offset)
++{
++#if defined(CONFIG_IO_CHECK_IN_ANA_LOW_CLK) && defined(CONFIG_LPS_LCLK)
++	struct pwrctrl_priv *pwrpriv = &dvobj->pwrctl_priv;
++	u32 mac_reg_offset = 0;
++
++	if (pwrpriv->pwr_mode == PS_MODE_ACTIVE)
++		return _TRUE;
++
++	if (pwrpriv->lps_level == LPS_NORMAL)
++		return _TRUE;
++
++	if (pwrpriv->rpwm >= PS_STATE_S2)
++		return _TRUE;
++
++	if (offset & (WLAN_IOREG_DEVICE_ID << 13))  { /*WLAN_IOREG_OFFSET*/
++		mac_reg_offset = offset & HALMAC_WLAN_MAC_REG_MSK;
++		if (mac_reg_offset < 0x100) {
++			RTW_ERR(FUNC_ADPT_FMT
++				"access MAC REG -0x%04x in PS-mode:0x%02x (rpwm:0x%02x, lps_level:0x%02x)\n",
++				FUNC_ADPT_ARG(dvobj_get_primary_adapter(dvobj)), mac_reg_offset,
++				pwrpriv->pwr_mode, pwrpriv->rpwm, pwrpriv->lps_level);
++			rtw_warn_on(1);
++			return _FALSE;
++		}
++	}
++#endif
++	return _TRUE;
++}
++
++static u8 _halmac_sdio_cmd52_read(void *p, u32 offset)
++{
++	struct dvobj_priv *d;
++	u8 val;
++	u8 ret;
++
++
++	d = (struct dvobj_priv *)p;
++	_halmac_mac_reg_page0_chk(__func__, d, offset);
++	ret = rtw_sdio_read_cmd52(d, offset, &val, 1);
++	if (_FAIL == ret) {
++		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
++		return SDIO_ERR_VAL8;
++	}
++
++	return val;
++}
++
++static void _halmac_sdio_cmd52_write(void *p, u32 offset, u8 val)
++{
++	struct dvobj_priv *d;
++	u8 ret;
++
++
++	d = (struct dvobj_priv *)p;
++	_halmac_mac_reg_page0_chk(__func__, d, offset);
++	ret = rtw_sdio_write_cmd52(d, offset, &val, 1);
++	if (_FAIL == ret)
++		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
++}
++
++static u8 _halmac_sdio_reg_read_8(void *p, u32 offset)
++{
++	struct dvobj_priv *d;
++	u8 *pbuf;
++	u8 val;
++	u8 ret;
++
++
++	d = (struct dvobj_priv *)p;
++	val = SDIO_ERR_VAL8;
++	_halmac_mac_reg_page0_chk(__func__, d, offset);
++	pbuf = rtw_zmalloc(1);
++	if (!pbuf)
++		return val;
++
++	ret = rtw_sdio_read_cmd53(d, offset, pbuf, 1);
++	if (ret == _FAIL) {
++		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
++		goto exit;
++	}
++
++	val = *pbuf;
++
++exit:
++	rtw_mfree(pbuf, 1);
++
++	return val;
++}
++
++static u16 _halmac_sdio_reg_read_16(void *p, u32 offset)
++{
++	struct dvobj_priv *d;
++	u8 *pbuf;
++	u16 val;
++	u8 ret;
++
++
++	d = (struct dvobj_priv *)p;
++	val = SDIO_ERR_VAL16;
++	_halmac_mac_reg_page0_chk(__func__, d, offset);
++	pbuf = rtw_zmalloc(2);
++	if (!pbuf)
++		return val;
++
++	ret = rtw_sdio_read_cmd53(d, offset, pbuf, 2);
++	if (ret == _FAIL) {
++		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
++		goto exit;
++	}
++
++	val = le16_to_cpu(*(u16 *)pbuf);
++
++exit:
++	rtw_mfree(pbuf, 2);
++
++	return val;
++}
++
++static u32 _halmac_sdio_reg_read_32(void *p, u32 offset)
++{
++	struct dvobj_priv *d;
++	u8 *pbuf;
++	u32 val;
++	u8 ret;
++
++
++	d = (struct dvobj_priv *)p;
++	val = SDIO_ERR_VAL32;
++	_halmac_mac_reg_page0_chk(__func__, d, offset);
++	pbuf = rtw_zmalloc(4);
++	if (!pbuf)
++		return val;
++
++	ret = rtw_sdio_read_cmd53(d, offset, pbuf, 4);
++	if (ret == _FAIL) {
++		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
++		goto exit;
++	}
++
++	val = le32_to_cpu(*(u32 *)pbuf);
++
++exit:
++	rtw_mfree(pbuf, 4);
++
++	return val;
++}
++
++static u8 _halmac_sdio_reg_read_n(void *p, u32 offset, u32 size, u8 *data)
++{
++	struct dvobj_priv *d = (struct dvobj_priv *)p;
++	u8 *pbuf;
++	u8 ret;
++	u8 rst = RTW_HALMAC_FAIL;
++	u32 sdio_read_size;
++
++
++	if (!data)
++		return rst;
++
++	sdio_read_size = RND4(size);
++	sdio_read_size = rtw_sdio_cmd53_align_size(d, sdio_read_size);
++
++	pbuf = rtw_zmalloc(sdio_read_size);
++	if (!pbuf)
++		return rst;
++
++	ret = rtw_sdio_read_cmd53(d, offset, pbuf, sdio_read_size);
++	if (ret == _FAIL) {
++		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
++		goto exit;
++	}
++
++	_rtw_memcpy(data, pbuf, size);
++	rst = RTW_HALMAC_SUCCESS;
++exit:
++	rtw_mfree(pbuf, sdio_read_size);
++
++	return rst;
++}
++
++static void _halmac_sdio_reg_write_8(void *p, u32 offset, u8 val)
++{
++	struct dvobj_priv *d;
++	u8 *pbuf;
++	u8 ret;
++
++
++	d = (struct dvobj_priv *)p;
++	_halmac_mac_reg_page0_chk(__func__, d, offset);
++	pbuf = rtw_zmalloc(1);
++	if (!pbuf)
++		return;
++	_rtw_memcpy(pbuf, &val, 1);
++
++	ret = rtw_sdio_write_cmd53(d, offset, pbuf, 1);
++	if (ret == _FAIL)
++		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
++
++	rtw_mfree(pbuf, 1);
++}
++
++static void _halmac_sdio_reg_write_16(void *p, u32 offset, u16 val)
++{
++	struct dvobj_priv *d;
++	u8 *pbuf;
++	u8 ret;
++
++
++	d = (struct dvobj_priv *)p;
++	_halmac_mac_reg_page0_chk(__func__, d, offset);
++	val = cpu_to_le16(val);
++	pbuf = rtw_zmalloc(2);
++	if (!pbuf)
++		return;
++	_rtw_memcpy(pbuf, &val, 2);
++
++	ret = rtw_sdio_write_cmd53(d, offset, pbuf, 2);
++	if (ret == _FAIL)
++		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
++
++	rtw_mfree(pbuf, 2);
++}
++
++static void _halmac_sdio_reg_write_32(void *p, u32 offset, u32 val)
++{
++	struct dvobj_priv *d;
++	u8 *pbuf;
++	u8 ret;
++
++
++	d = (struct dvobj_priv *)p;
++	_halmac_mac_reg_page0_chk(__func__, d, offset);
++	val = cpu_to_le32(val);
++	pbuf = rtw_zmalloc(4);
++	if (!pbuf)
++		return;
++	_rtw_memcpy(pbuf, &val, 4);
++
++	ret = rtw_sdio_write_cmd53(d, offset, pbuf, 4);
++	if (ret == _FAIL)
++		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
++
++	rtw_mfree(pbuf, 4);
++}
++
++static u8 _halmac_sdio_read_cia(void *p, u32 offset)
++{
++	struct dvobj_priv *d;
++	u8 data = 0;
++	u8 ret;
++
++
++	d = (struct dvobj_priv *)p;
++
++	ret = rtw_sdio_f0_read(d, offset, &data, 1);
++	if (ret == _FAIL)
++		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
++
++	return data;
++}
++
++#else /* !CONFIG_SDIO_HCI */
++
++static u8 _halmac_reg_read_8(void *p, u32 offset)
++{
++	struct dvobj_priv *d;
++	PADAPTER adapter;
++
++
++	d = (struct dvobj_priv *)p;
++	adapter = dvobj_get_primary_adapter(d);
++
++	return _rtw_read8(adapter, offset);
++}
++
++static u16 _halmac_reg_read_16(void *p, u32 offset)
++{
++	struct dvobj_priv *d;
++	PADAPTER adapter;
++
++
++	d = (struct dvobj_priv *)p;
++	adapter = dvobj_get_primary_adapter(d);
++
++	return _rtw_read16(adapter, offset);
++}
++
++static u32 _halmac_reg_read_32(void *p, u32 offset)
++{
++	struct dvobj_priv *d;
++	PADAPTER adapter;
++
++
++	d = (struct dvobj_priv *)p;
++	adapter = dvobj_get_primary_adapter(d);
++
++	return _rtw_read32(adapter, offset);
++}
++
++static void _halmac_reg_write_8(void *p, u32 offset, u8 val)
++{
++	struct dvobj_priv *d;
++	PADAPTER adapter;
++	int err;
++
++
++	d = (struct dvobj_priv *)p;
++	adapter = dvobj_get_primary_adapter(d);
++
++	err = _rtw_write8(adapter, offset, val);
++	if (err == _FAIL)
++		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
++}
++
++static void _halmac_reg_write_16(void *p, u32 offset, u16 val)
++{
++	struct dvobj_priv *d;
++	PADAPTER adapter;
++	int err;
++
++
++	d = (struct dvobj_priv *)p;
++	adapter = dvobj_get_primary_adapter(d);
++
++	err = _rtw_write16(adapter, offset, val);
++	if (err == _FAIL)
++		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
++}
++
++static void _halmac_reg_write_32(void *p, u32 offset, u32 val)
++{
++	struct dvobj_priv *d;
++	PADAPTER adapter;
++	int err;
++
++
++	d = (struct dvobj_priv *)p;
++	adapter = dvobj_get_primary_adapter(d);
++
++	err = _rtw_write32(adapter, offset, val);
++	if (err == _FAIL)
++		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
++}
++#endif /* !CONFIG_SDIO_HCI */
++
++#ifdef DBG_IO
++static void _halmac_reg_read_monitor(void *p, u32 addr, u32 len, u32 val
++	, const char *caller, const u32 line)
++{
++	struct dvobj_priv *d = (struct dvobj_priv *)p;
++	_adapter *adapter = dvobj_get_primary_adapter(d);
++
++	dbg_rtw_reg_read_monitor(adapter, addr, len, val, caller, line);
++}
++
++static void _halmac_reg_write_monitor(void *p, u32 addr, u32 len, u32 val
++	, const char *caller, const u32 line)
++{
++	struct dvobj_priv *d = (struct dvobj_priv *)p;
++	_adapter *adapter = dvobj_get_primary_adapter(d);
++
++	dbg_rtw_reg_write_monitor(adapter, addr, len, val, caller, line);
++}
++#endif
++
++static u8 _halmac_mfree(void *p, void *buffer, u32 size)
++{
++	rtw_mfree(buffer, size);
++	return RTW_HALMAC_SUCCESS;
++}
++
++static void *_halmac_malloc(void *p, u32 size)
++{
++	return rtw_zmalloc(size);
++}
++
++static u8 _halmac_memcpy(void *p, void *dest, void *src, u32 size)
++{
++	_rtw_memcpy(dest, src, size);
++	return RTW_HALMAC_SUCCESS;
++}
++
++static u8 _halmac_memset(void *p, void *addr, u8 value, u32 size)
++{
++	_rtw_memset(addr, value, size);
++	return RTW_HALMAC_SUCCESS;
++}
++
++static void _halmac_udelay(void *p, u32 us)
++{
++	/* Most hardware polling wait time < 50us) */
++	if (us <= 50)
++		rtw_udelay_os(us);
++	else if (us <= 1000)
++		rtw_usleep_os(us);
++	else
++		rtw_msleep_os(RTW_DIV_ROUND_UP(us, 1000));
++}
++
++static u8 _halmac_mutex_init(void *p, HALMAC_MUTEX *pMutex)
++{
++	_rtw_mutex_init(pMutex);
++	return RTW_HALMAC_SUCCESS;
++}
++
++static u8 _halmac_mutex_deinit(void *p, HALMAC_MUTEX *pMutex)
++{
++	_rtw_mutex_free(pMutex);
++	return RTW_HALMAC_SUCCESS;
++}
++
++static u8 _halmac_mutex_lock(void *p, HALMAC_MUTEX *pMutex)
++{
++	int err;
++
++	err = _enter_critical_mutex(pMutex, NULL);
++	if (err)
++		return RTW_HALMAC_FAIL;
++
++	return RTW_HALMAC_SUCCESS;
++}
++
++static u8 _halmac_mutex_unlock(void *p, HALMAC_MUTEX *pMutex)
++{
++	_exit_critical_mutex(pMutex, NULL);
++	return RTW_HALMAC_SUCCESS;
++}
++
++#ifndef CONFIG_SDIO_HCI
++#define DBG_MSG_FILTER
++#endif
++
++#ifdef DBG_MSG_FILTER
++static u8 is_msg_allowed(uint drv_lv, u8 msg_lv)
++{
++	switch (drv_lv) {
++	case _DRV_NONE_:
++		return _FALSE;
++
++	case _DRV_ALWAYS_:
++		if (msg_lv > HALMAC_DBG_ALWAYS)
++			return _FALSE;
++		break;
++	case _DRV_ERR_:
++		if (msg_lv > HALMAC_DBG_ERR)
++			return _FALSE;
++		break;
++	case _DRV_WARNING_:
++		if (msg_lv > HALMAC_DBG_WARN)
++			return _FALSE;
++		break;
++	case _DRV_INFO_:
++		if (msg_lv >= HALMAC_DBG_TRACE)
++			return _FALSE;
++		break;
++	}
++
++	return _TRUE;
++}
++#endif /* DBG_MSG_FILTER */
++
++static u8 _halmac_msg_print(void *p, u32 msg_type, u8 msg_level, s8 *fmt, ...)
++{
++#define MSG_LEN		100
++	va_list args;
++	u8 str[MSG_LEN] = {0};
++#ifdef DBG_MSG_FILTER
++	uint drv_level = _DRV_NONE_;
++#endif
++	int err;
++	u8 ret = RTW_HALMAC_SUCCESS;
++
++
++#ifdef DBG_MSG_FILTER
++#ifdef CONFIG_RTW_DEBUG
++	drv_level = rtw_drv_log_level;
++#endif
++	if (is_msg_allowed(drv_level, msg_level) == _FALSE)
++		return ret;
++#endif
++
++	str[0] = '\n';
++	va_start(args, fmt);
++	err = vsnprintf(str, MSG_LEN, fmt, args);
++	va_end(args);
++
++	/* An output error is encountered */
++	if (err < 0)
++		return RTW_HALMAC_FAIL;
++	/* Output may be truncated due to size limit */
++	if ((err == (MSG_LEN - 1)) && (str[MSG_LEN - 2] != '\n'))
++		ret = RTW_HALMAC_FAIL;
++
++	if (msg_level == HALMAC_DBG_ALWAYS)
++		RTW_PRINT(MSG_PREFIX "%s", str);
++	else if (msg_level <= HALMAC_DBG_ERR)
++		RTW_ERR(MSG_PREFIX "%s", str);
++	else if (msg_level <= HALMAC_DBG_WARN)
++		RTW_WARN(MSG_PREFIX "%s", str);
++	else
++		RTW_DBG(MSG_PREFIX "%s", str);
++
++	return ret;
++}
++
++static u8 _halmac_buff_print(void *p, u32 msg_type, u8 msg_level, s8 *buf, u32 size)
++{
++	if (msg_level <= HALMAC_DBG_WARN)
++		RTW_INFO_DUMP(MSG_PREFIX, buf, size);
++	else
++		RTW_DBG_DUMP(MSG_PREFIX, buf, size);
++
++	return RTW_HALMAC_SUCCESS;
++}
++
++
++const char *const RTW_HALMAC_FEATURE_NAME[] = {
++	"HALMAC_FEATURE_CFG_PARA",
++	"HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE",
++	"HALMAC_FEATURE_DUMP_LOGICAL_EFUSE",
++	"HALMAC_FEATURE_DUMP_LOGICAL_EFUSE_MASK",
++	"HALMAC_FEATURE_UPDATE_PACKET",
++	"HALMAC_FEATURE_SEND_SCAN_PACKET",
++	"HALMAC_FEATURE_DROP_SCAN_PACKET",
++	"HALMAC_FEATURE_UPDATE_DATAPACK",
++	"HALMAC_FEATURE_RUN_DATAPACK",
++	"HALMAC_FEATURE_CHANNEL_SWITCH",
++	"HALMAC_FEATURE_IQK",
++	"HALMAC_FEATURE_POWER_TRACKING",
++	"HALMAC_FEATURE_PSD",
++	"HALMAC_FEATURE_FW_SNDING",
++	"HALMAC_FEATURE_DPK",
++	"HALMAC_FEATURE_ALL"
++};
++
++static inline u8 is_valid_id_status(enum halmac_feature_id id, enum halmac_cmd_process_status status)
++{
++	switch (id) {
++	case HALMAC_FEATURE_CFG_PARA:
++		RTW_DBG("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
++		break;
++	case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
++		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
++		if (HALMAC_CMD_PROCESS_DONE != status)
++			RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
++				 __FUNCTION__, id, status);
++		break;
++	case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
++		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
++		if (HALMAC_CMD_PROCESS_DONE != status)
++			RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
++				 __FUNCTION__, id, status);
++		break;
++	case HALMAC_FEATURE_UPDATE_PACKET:
++		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
++		if (status != HALMAC_CMD_PROCESS_DONE)
++			RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
++				 __FUNCTION__, id, status);
++		break;
++	case HALMAC_FEATURE_UPDATE_DATAPACK:
++		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
++		break;
++	case HALMAC_FEATURE_RUN_DATAPACK:
++		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
++		break;
++	case HALMAC_FEATURE_CHANNEL_SWITCH:
++		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
++		if ((status != HALMAC_CMD_PROCESS_DONE) && (status != HALMAC_CMD_PROCESS_RCVD))
++			RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
++				 __FUNCTION__, id, status);
++		if (status == HALMAC_CMD_PROCESS_DONE)
++			return _FALSE;
++		break;
++	case HALMAC_FEATURE_IQK:
++		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
++		break;
++	case HALMAC_FEATURE_POWER_TRACKING:
++		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
++		break;
++	case HALMAC_FEATURE_PSD:
++		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
++		break;
++	case HALMAC_FEATURE_FW_SNDING:
++		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
++		break;
++	case HALMAC_FEATURE_DPK:
++		if (status == HALMAC_CMD_PROCESS_RCVD)
++			return _FALSE;
++		if ((status != HALMAC_CMD_PROCESS_DONE)
++		    || (status != HALMAC_CMD_PROCESS_ERROR))
++			RTW_WARN("%s: %s unexpected status(0x%x)!\n",
++				 __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id],
++				 status);
++		break;
++	case HALMAC_FEATURE_ALL:
++		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
++		break;
++	default:
++		RTW_ERR("%s: unknown feature id(%d)\n", __FUNCTION__, id);
++		return _FALSE;
++	}
++
++	return _TRUE;
++}
++
++static int init_halmac_event_with_waittime(struct dvobj_priv *d, enum halmac_feature_id id, u8 *buf, u32 size, u32 time)
++{
++	struct submit_ctx *sctx;
++
++
++	if (!d->hmpriv.indicator[id].sctx) {
++		sctx = (struct submit_ctx *)rtw_zmalloc(sizeof(*sctx));
++		if (!sctx)
++			return -1;
++	} else {
++		RTW_WARN("%s: id(%d) sctx is not NULL!!\n", __FUNCTION__, id);
++		sctx = d->hmpriv.indicator[id].sctx;
++		d->hmpriv.indicator[id].sctx = NULL;
++	}
++
++	rtw_sctx_init(sctx, time);
++	d->hmpriv.indicator[id].buffer = buf;
++	d->hmpriv.indicator[id].buf_size = size;
++	d->hmpriv.indicator[id].ret_size = 0;
++	d->hmpriv.indicator[id].status = 0;
++	/* fill sctx at least to sure other variables are all ready! */
++	d->hmpriv.indicator[id].sctx = sctx;
++
++	return 0;
++}
++
++static inline int init_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id, u8 *buf, u32 size)
++{
++	return init_halmac_event_with_waittime(d, id, buf, size, DEFAULT_INDICATOR_TIMELMT);
++}
++
++static void free_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id)
++{
++	struct submit_ctx *sctx;
++
++
++	if (!d->hmpriv.indicator[id].sctx)
++		return;
++
++	sctx = d->hmpriv.indicator[id].sctx;
++	d->hmpriv.indicator[id].sctx = NULL;
++	rtw_mfree((u8 *)sctx, sizeof(*sctx));
++}
++
++static int wait_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	struct submit_ctx *sctx;
++	int status;
++	int ret;
++
++
++	sctx = d->hmpriv.indicator[id].sctx;
++	if (!sctx)
++		return -1;
++
++	ret = rtw_sctx_wait(sctx, RTW_HALMAC_FEATURE_NAME[id]);
++	status = sctx->status;
++	free_halmac_event(d, id);
++	if (_SUCCESS == ret)
++		return 0;
++
++	/* If no one change sctx->status, it is timeout case */
++	if (status == 0)
++		status = RTW_SCTX_DONE_TIMEOUT;
++	RTW_ERR("%s: id(%d, %s) status=0x%x ! Reset HALMAC state!\n",
++		__FUNCTION__, id, RTW_HALMAC_FEATURE_NAME[id], status);
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++	api->halmac_reset_feature(mac, id);
++
++	return -1;
++}
++
++/*
++ * Return:
++ *	Always return RTW_HALMAC_SUCCESS, HALMAC don't care the return value.
++ */
++static u8 _halmac_event_indication(void *p, enum halmac_feature_id feature_id,
++				enum halmac_cmd_process_status process_status,
++				u8 *buf, u32 size)
++{
++	struct dvobj_priv *d;
++	PADAPTER adapter;
++	PHAL_DATA_TYPE hal;
++	struct halmac_indicator *tbl, *indicator;
++	struct submit_ctx *sctx;
++	u32 cpsz;
++	u8 ret;
++
++
++	d = (struct dvobj_priv *)p;
++	adapter = dvobj_get_primary_adapter(d);
++	hal = GET_HAL_DATA(adapter);
++	tbl = d->hmpriv.indicator;
++
++	/* Filter(Skip) middle status indication */
++	ret = is_valid_id_status(feature_id, process_status);
++	if (_FALSE == ret)
++		goto exit;
++
++	indicator = &tbl[feature_id];
++	indicator->status = process_status;
++	indicator->ret_size = size;
++	if (!indicator->sctx) {
++		RTW_WARN("%s: id(%d, %s) is not waiting!!\n", __FUNCTION__,
++			 feature_id, RTW_HALMAC_FEATURE_NAME[feature_id]);
++		goto exit;
++	}
++	sctx = indicator->sctx;
++
++	if (HALMAC_CMD_PROCESS_ERROR == process_status) {
++		RTW_ERR("%s: id(%d, %s) Something wrong!!\n", __FUNCTION__,
++			feature_id, RTW_HALMAC_FEATURE_NAME[feature_id]);
++		if ((size == 1) && buf)
++			RTW_ERR("%s: error code=0x%x\n", __FUNCTION__, *buf);
++		rtw_sctx_done_err(&sctx, RTW_SCTX_DONE_UNKNOWN);
++		goto exit;
++	}
++
++	if (size > indicator->buf_size) {
++		RTW_WARN("%s: id(%d, %s) buffer is not enough(%d<%d), "
++			 "and data will be truncated!\n",
++			 __FUNCTION__,
++			 feature_id, RTW_HALMAC_FEATURE_NAME[feature_id],
++			 indicator->buf_size, size);
++		cpsz = indicator->buf_size;
++	} else {
++		cpsz = size;
++	}
++	if (cpsz && indicator->buffer)
++		_rtw_memcpy(indicator->buffer, buf, cpsz);
++
++	rtw_sctx_done(&sctx);
++
++exit:
++	return RTW_HALMAC_SUCCESS;
++}
++
++struct halmac_platform_api rtw_halmac_platform_api = {
++	/* R/W register */
++#ifdef CONFIG_SDIO_HCI
++	.SDIO_CMD52_READ = _halmac_sdio_cmd52_read,
++	.SDIO_CMD53_READ_8 = _halmac_sdio_reg_read_8,
++	.SDIO_CMD53_READ_16 = _halmac_sdio_reg_read_16,
++	.SDIO_CMD53_READ_32 = _halmac_sdio_reg_read_32,
++	.SDIO_CMD53_READ_N = _halmac_sdio_reg_read_n,
++	.SDIO_CMD52_WRITE = _halmac_sdio_cmd52_write,
++	.SDIO_CMD53_WRITE_8 = _halmac_sdio_reg_write_8,
++	.SDIO_CMD53_WRITE_16 = _halmac_sdio_reg_write_16,
++	.SDIO_CMD53_WRITE_32 = _halmac_sdio_reg_write_32,
++	.SDIO_CMD52_CIA_READ = _halmac_sdio_read_cia,
++#endif /* CONFIG_SDIO_HCI */
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
++	.REG_READ_8 = _halmac_reg_read_8,
++	.REG_READ_16 = _halmac_reg_read_16,
++	.REG_READ_32 = _halmac_reg_read_32,
++	.REG_WRITE_8 = _halmac_reg_write_8,
++	.REG_WRITE_16 = _halmac_reg_write_16,
++	.REG_WRITE_32 = _halmac_reg_write_32,
++#endif /* CONFIG_USB_HCI || CONFIG_PCI_HCI */
++
++#ifdef DBG_IO
++	.READ_MONITOR = _halmac_reg_read_monitor,
++	.WRITE_MONITOR = _halmac_reg_write_monitor,
++#endif
++
++	/* Write data */
++#if 0
++	/* impletement in HAL-IC level */
++	.SEND_RSVD_PAGE = sdio_write_data_rsvd_page,
++	.SEND_H2C_PKT = sdio_write_data_h2c,
++#endif
++	/* Memory allocate */
++	.RTL_FREE = _halmac_mfree,
++	.RTL_MALLOC = _halmac_malloc,
++	.RTL_MEMCPY = _halmac_memcpy,
++	.RTL_MEMSET = _halmac_memset,
++
++	/* Sleep */
++	.RTL_DELAY_US = _halmac_udelay,
++
++	/* Process Synchronization */
++	.MUTEX_INIT = _halmac_mutex_init,
++	.MUTEX_DEINIT = _halmac_mutex_deinit,
++	.MUTEX_LOCK = _halmac_mutex_lock,
++	.MUTEX_UNLOCK = _halmac_mutex_unlock,
++
++	.MSG_PRINT = _halmac_msg_print,
++	.BUFF_PRINT = _halmac_buff_print,
++	.EVENT_INDICATION = _halmac_event_indication,
++};
++
++u8 rtw_halmac_read8(struct intf_hdl *pintfhdl, u32 addr)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++
++
++	/* WARNING: pintf_dev should not be null! */
++	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
++	api = HALMAC_GET_API(mac);
++
++	return api->halmac_reg_read_8(mac, addr);
++}
++
++u16 rtw_halmac_read16(struct intf_hdl *pintfhdl, u32 addr)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++
++
++	/* WARNING: pintf_dev should not be null! */
++	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
++	api = HALMAC_GET_API(mac);
++
++	return api->halmac_reg_read_16(mac, addr);
++}
++
++u32 rtw_halmac_read32(struct intf_hdl *pintfhdl, u32 addr)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++
++
++	/* WARNING: pintf_dev should not be null! */
++	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
++	api = HALMAC_GET_API(mac);
++
++	return api->halmac_reg_read_32(mac, addr);
++}
++
++static void _read_register(struct dvobj_priv *d, u32 addr, u32 cnt, u8 *buf)
++{
++#if 1
++	struct _ADAPTER *a;
++	u32 i, n;
++	u16 val16;
++	u32 val32;
++
++
++	a = dvobj_get_primary_adapter(d);
++
++	i = addr & 0x3;
++	/* Handle address not start from 4 bytes alignment case */
++	if (i) {
++		val32 = cpu_to_le32(rtw_read32(a, addr & ~0x3));
++		n = 4 - i;
++		_rtw_memcpy(buf, ((u8 *)&val32) + i, n);
++		i = n;
++		cnt -= n;
++	}
++
++	while (cnt) {
++		if (cnt >= 4)
++			n = 4;
++		else if (cnt >= 2)
++			n = 2;
++		else
++			n = 1;
++		cnt -= n;
++
++		switch (n) {
++		case 1:
++			buf[i] = rtw_read8(a, addr+i);
++			i++;
++			break;
++		case 2:
++			val16 = cpu_to_le16(rtw_read16(a, addr+i));
++			_rtw_memcpy(&buf[i], &val16, 2);
++			i += 2;
++			break;
++		case 4:
++			val32 = cpu_to_le32(rtw_read32(a, addr+i));
++			_rtw_memcpy(&buf[i], &val32, 4);
++			i += 4;
++			break;
++		}
++	}
++#else
++	struct _ADAPTER *a;
++	u32 i;
++
++
++	a = dvobj_get_primary_adapter(d);
++	for (i = 0; i < cnt; i++)
++		buf[i] = rtw_read8(a, addr + i);
++#endif
++}
++
++#ifdef CONFIG_SDIO_HCI
++static int _sdio_read_local(struct dvobj_priv *d, u32 addr, u32 cnt, u8 *buf)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++
++
++	if (buf == NULL)
++		return -1;
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_reg_sdio_cmd53_read_n(mac, addr, cnt, buf);
++	if (status != HALMAC_RET_SUCCESS) {
++		RTW_ERR("%s: addr=0x%08x cnt=%d err=%d\n",
++			__FUNCTION__, addr, cnt, status);
++		return -1;
++	}
++
++	return 0;
++}
++#endif /* CONFIG_SDIO_HCI */
++
++void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem)
++{
++	struct dvobj_priv *d;
++
++
++	if (pmem == NULL) {
++		RTW_ERR("pmem is NULL\n");
++		return;
++	}
++
++	d = pintfhdl->pintf_dev;
++
++#ifdef CONFIG_SDIO_HCI
++	if (addr & 0xFFFF0000) {
++		int err = 0;
++
++		err = _sdio_read_local(d, addr, cnt, pmem);
++		if (!err)
++			return;
++	}
++#endif /* CONFIG_SDIO_HCI */
++
++	_read_register(d, addr, cnt, pmem);
++}
++
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++
++	/* WARNING: pintf_dev should not be null! */
++	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
++	api = HALMAC_GET_API(mac);
++
++	/*return api->halmac_reg_read_indirect_8(mac, addr);*/
++	return api->halmac_reg_read_8(mac, addr);
++}
++
++u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	u16 val16 = 0;
++
++	/* WARNING: pintf_dev should not be null! */
++	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
++	api = HALMAC_GET_API(mac);
++
++	/*return api->halmac_reg_read_indirect_16(mac, addr);*/
++	return api->halmac_reg_read_16(mac, addr);
++}
++
++u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++
++
++	/* WARNING: pintf_dev should not be null! */
++	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
++	api = HALMAC_GET_API(mac);
++
++	return api->halmac_reg_read_indirect_32(mac, addr);
++}
++#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
++
++int rtw_halmac_write8(struct intf_hdl *pintfhdl, u32 addr, u8 value)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++
++
++	/* WARNING: pintf_dev should not be null! */
++	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_reg_write_8(mac, addr, value);
++
++	if (status == HALMAC_RET_SUCCESS)
++		return 0;
++
++	return -1;
++}
++
++int rtw_halmac_write16(struct intf_hdl *pintfhdl, u32 addr, u16 value)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++
++
++	/* WARNING: pintf_dev should not be null! */
++	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_reg_write_16(mac, addr, value);
++
++	if (status == HALMAC_RET_SUCCESS)
++		return 0;
++
++	return -1;
++}
++
++int rtw_halmac_write32(struct intf_hdl *pintfhdl, u32 addr, u32 value)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++
++
++	/* WARNING: pintf_dev should not be null! */
++	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_reg_write_32(mac, addr, value);
++
++	if (status == HALMAC_RET_SUCCESS)
++		return 0;
++
++	return -1;
++}
++
++static int init_write_rsvd_page_size(struct dvobj_priv *d)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	u32 size = 0;
++	struct halmac_ofld_func_info ofld_info;
++	enum halmac_ret_status status;
++	int err = 0;
++
++
++#ifdef CONFIG_USB_HCI
++	/* for USB do not exceed MAX_CMDBUF_SZ */
++	size = 0x1000;
++#elif defined(CONFIG_PCI_HCI)
++	size = MAX_CMDBUF_SZ - TXDESC_OFFSET;
++#elif defined(CONFIG_SDIO_HCI)
++	size = 0x7000; /* 28KB */
++#else
++	/* Use HALMAC default setting and don't call any function */
++	return 0;
++#endif
++#if 0	/* Fail to pass coverity DEADCODE check */
++	/* If size==0, use HALMAC default setting and don't call any function */
++	if (!size)
++		return 0;
++#endif
++	err = rtw_halmac_set_max_dl_fw_size(d, size);
++	if (err) {
++		RTW_ERR("%s: Fail to set max download fw size!\n", __FUNCTION__);
++		return -1;
++	}
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	_rtw_memset(&ofld_info, 0, sizeof(ofld_info));
++	ofld_info.halmac_malloc_max_sz = 0xFFFFFFFF;
++	ofld_info.rsvd_pg_drv_buf_max_sz = size;
++	status = api->halmac_ofld_func_cfg(mac, &ofld_info);
++	if (status != HALMAC_RET_SUCCESS) {
++		RTW_ERR("%s: Fail to config offload parameters!\n", __FUNCTION__);
++		return -1;
++	}
++
++	return 0;
++}
++
++static int init_priv(struct halmacpriv *priv)
++{
++	struct halmac_indicator *indicator;
++	u32 count, size;
++
++
++	if (priv->indicator)
++		RTW_WARN("%s: HALMAC private data is not CLEAR!\n", __FUNCTION__);
++	count = HALMAC_FEATURE_ALL + 1;
++	size = sizeof(*indicator) * count;
++	indicator = (struct halmac_indicator *)rtw_zmalloc(size);
++	if (!indicator)
++		return -1;
++	priv->indicator = indicator;
++
++	return 0;
++}
++
++static void deinit_priv(struct halmacpriv *priv)
++{
++	struct halmac_indicator *indicator;
++
++
++	indicator = priv->indicator;
++	priv->indicator = NULL;
++	if (indicator) {
++		u32 count, size;
++
++		count = HALMAC_FEATURE_ALL + 1;
++#ifdef CONFIG_RTW_DEBUG
++		{
++			struct submit_ctx *sctx;
++			u32 i;
++
++			for (i = 0; i < count; i++) {
++				if (!indicator[i].sctx)
++					continue;
++
++				RTW_WARN("%s: %s id(%d) sctx still exist!!\n",
++					__FUNCTION__, RTW_HALMAC_FEATURE_NAME[i], i);
++				sctx = indicator[i].sctx;
++				indicator[i].sctx = NULL;
++				rtw_mfree((u8 *)sctx, sizeof(*sctx));
++			}
++		}
++#endif /* !CONFIG_RTW_DEBUG */
++		size = sizeof(*indicator) * count;
++		rtw_mfree((u8 *)indicator, size);
++	}
++}
++
++#ifdef CONFIG_SDIO_HCI
++static enum halmac_sdio_spec_ver _sdio_ver_drv2halmac(struct dvobj_priv *d)
++{
++	bool v3;
++	enum halmac_sdio_spec_ver ver;
++
++
++	v3 = rtw_is_sdio30(dvobj_get_primary_adapter(d));
++	if (v3)
++		ver = HALMAC_SDIO_SPEC_VER_3_00;
++	else
++		ver = HALMAC_SDIO_SPEC_VER_2_00;
++
++	return ver;
++}
++#endif /* CONFIG_SDIO_HCI */
++
++void rtw_halmac_get_version(char *str, u32 len)
++{
++	enum halmac_ret_status status;
++	struct halmac_ver ver;
++
++
++	status = halmac_get_version(&ver);
++	if (status != HALMAC_RET_SUCCESS)
++		return;
++
++	rtw_sprintf(str, len, "V%d_%02d_%02d",
++		    ver.major_ver, ver.prototype_ver, ver.minor_ver);
++}
++
++int rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf_api)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_interface intf;
++	enum halmac_ret_status status;
++	int err = 0;
++#ifdef CONFIG_SDIO_HCI
++	struct halmac_sdio_hw_info info;
++#endif /* CONFIG_SDIO_HCI */
++
++
++	halmac = dvobj_to_halmac(d);
++	if (halmac) {
++		RTW_WARN("%s: initialize already completed!\n", __FUNCTION__);
++		goto error;
++	}
++
++	err = init_priv(&d->hmpriv);
++	if (err)
++		goto error;
++
++#ifdef CONFIG_SDIO_HCI
++	intf = HALMAC_INTERFACE_SDIO;
++#elif defined(CONFIG_USB_HCI)
++	intf = HALMAC_INTERFACE_USB;
++#elif defined(CONFIG_PCI_HCI)
++	intf = HALMAC_INTERFACE_PCIE;
++#else
++#warning "INTERFACE(CONFIG_XXX_HCI) not be defined!!"
++	intf = HALMAC_INTERFACE_UNDEFINE;
++#endif
++	status = halmac_init_adapter(d, pf_api, intf, &halmac, &api);
++	if (HALMAC_RET_SUCCESS != status) {
++		RTW_ERR("%s: halmac_init_adapter fail!(status=%d)\n", __FUNCTION__, status);
++		err = -1;
++		if (halmac)
++			goto deinit;
++		goto free;
++	}
++
++	dvobj_set_halmac(d, halmac);
++
++	status = api->halmac_interface_integration_tuning(halmac);
++	if (status != HALMAC_RET_SUCCESS) {
++		RTW_ERR("%s: halmac_interface_integration_tuning fail!(status=%d)\n", __FUNCTION__, status);
++		err = -1;
++		goto deinit;
++	}
++
++	status = api->halmac_phy_cfg(halmac, HALMAC_INTF_PHY_PLATFORM_ALL);
++	if (status != HALMAC_RET_SUCCESS) {
++		RTW_ERR("%s: halmac_phy_cfg fail!(status=%d)\n", __FUNCTION__, status);
++		err = -1;
++		goto deinit;
++	}
++
++	init_write_rsvd_page_size(d);
++
++#ifdef CONFIG_SDIO_HCI
++	_rtw_memset(&info, 0, sizeof(info));
++	info.spec_ver = _sdio_ver_drv2halmac(d);
++	/* Convert clock speed unit to MHz from Hz */
++	info.clock_speed = RTW_DIV_ROUND_UP(rtw_sdio_get_clock(d), 1000000);
++	info.block_size = rtw_sdio_get_block_size(d);
++	if (d->hmpriv.sdio_io_indir == 2)
++		info.io_indir_flag = 0;
++	else
++		info.io_indir_flag = 1; /* Default enable indirect I/O */
++	RTW_DBG("%s: SDIO ver=%u clock=%uMHz blk_size=%u bytes, io_indir=%u\n",
++		__FUNCTION__, info.spec_ver+2, info.clock_speed,
++		info.block_size, info.io_indir_flag);
++	status = api->halmac_sdio_hw_info(halmac, &info);
++	if (status != HALMAC_RET_SUCCESS) {
++		RTW_ERR("%s: halmac_sdio_hw_info fail!(status=%d)\n",
++			__FUNCTION__, status);
++		err = -1;
++		goto deinit;
++	}
++#endif /* CONFIG_SDIO_HCI */
++
++	return 0;
++
++deinit:
++	status = halmac_deinit_adapter(halmac);
++	dvobj_set_halmac(d, NULL);
++	if (status != HALMAC_RET_SUCCESS)
++		RTW_ERR("%s: halmac_deinit_adapter fail!(status=%d)\n",
++			__FUNCTION__, status);
++
++free:
++	deinit_priv(&d->hmpriv);
++
++error:
++	return err;
++}
++
++int rtw_halmac_deinit_adapter(struct dvobj_priv *d)
++{
++	struct halmac_adapter *halmac;
++	enum halmac_ret_status status;
++	int err = 0;
++
++
++	halmac = dvobj_to_halmac(d);
++	if (halmac) {
++		status = halmac_deinit_adapter(halmac);
++		dvobj_set_halmac(d, NULL);
++		if (status != HALMAC_RET_SUCCESS)
++			err = -1;
++	}
++
++	deinit_priv(&d->hmpriv);
++
++	return err;
++}
++
++static inline enum halmac_portid _hw_port_drv2halmac(enum _hw_port hwport)
++{
++	enum halmac_portid port = HALMAC_PORTID_NUM;
++
++
++	switch (hwport) {
++	case HW_PORT0:
++		port = HALMAC_PORTID0;
++		break;
++	case HW_PORT1:
++		port = HALMAC_PORTID1;
++		break;
++	case HW_PORT2:
++		port = HALMAC_PORTID2;
++		break;
++	case HW_PORT3:
++		port = HALMAC_PORTID3;
++		break;
++	case HW_PORT4:
++		port = HALMAC_PORTID4;
++		break;
++	default:
++		break;
++	}
++
++	return port;
++}
++
++static enum halmac_network_type_select _network_type_drv2halmac(u8 type)
++{
++	enum halmac_network_type_select network = HALMAC_NETWORK_UNDEFINE;
++
++
++	switch (type) {
++	case _HW_STATE_NOLINK_:
++	case _HW_STATE_MONITOR_:
++		network = HALMAC_NETWORK_NO_LINK;
++		break;
++
++	case _HW_STATE_ADHOC_:
++		network = HALMAC_NETWORK_ADHOC;
++		break;
++
++	case _HW_STATE_STATION_:
++		network = HALMAC_NETWORK_INFRASTRUCTURE;
++		break;
++
++	case _HW_STATE_AP_:
++		network = HALMAC_NETWORK_AP;
++		break;
++	}
++
++	return network;
++}
++
++static u8 _network_type_halmac2drv(enum halmac_network_type_select network)
++{
++	u8 type = _HW_STATE_NOLINK_;
++
++
++	switch (network) {
++	case HALMAC_NETWORK_NO_LINK:
++	case HALMAC_NETWORK_UNDEFINE:
++		type = _HW_STATE_NOLINK_;
++		break;
++
++	case HALMAC_NETWORK_ADHOC:
++		type = _HW_STATE_ADHOC_;
++		break;
++
++	case HALMAC_NETWORK_INFRASTRUCTURE:
++		type = _HW_STATE_STATION_;
++		break;
++
++	case HALMAC_NETWORK_AP:
++		type = _HW_STATE_AP_;
++		break;
++	}
++
++	return type;
++}
++
++static void _beacon_ctrl_halmac2drv(struct halmac_bcn_ctrl *ctrl,
++				struct rtw_halmac_bcn_ctrl *drv_ctrl)
++{
++	drv_ctrl->rx_bssid_fit = ctrl->dis_rx_bssid_fit ? 0 : 1;
++	drv_ctrl->txbcn_rpt = ctrl->en_txbcn_rpt ? 1 : 0;
++	drv_ctrl->tsf_update = ctrl->dis_tsf_udt ? 0 : 1;
++	drv_ctrl->enable_bcn = ctrl->en_bcn ? 1 : 0;
++	drv_ctrl->rxbcn_rpt = ctrl->en_rxbcn_rpt ? 1 : 0;
++	drv_ctrl->p2p_ctwin = ctrl->en_p2p_ctwin ? 1 : 0;
++	drv_ctrl->p2p_bcn_area = ctrl->en_p2p_bcn_area ? 1 : 0;
++}
++
++static void _beacon_ctrl_drv2halmac(struct rtw_halmac_bcn_ctrl *drv_ctrl,
++				struct halmac_bcn_ctrl *ctrl)
++{
++	ctrl->dis_rx_bssid_fit = drv_ctrl->rx_bssid_fit ? 0 : 1;
++	ctrl->en_txbcn_rpt = drv_ctrl->txbcn_rpt ? 1 : 0;
++	ctrl->dis_tsf_udt = drv_ctrl->tsf_update ? 0 : 1;
++	ctrl->en_bcn = drv_ctrl->enable_bcn ? 1 : 0;
++	ctrl->en_rxbcn_rpt = drv_ctrl->rxbcn_rpt ? 1 : 0;
++	ctrl->en_p2p_ctwin = drv_ctrl->p2p_ctwin ? 1 : 0;
++	ctrl->en_p2p_bcn_area = drv_ctrl->p2p_bcn_area ? 1 : 0;
++}
++
++int rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void *pvalue)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_get_hw_value(mac, hw_id, pvalue);
++	if (HALMAC_RET_SUCCESS != status)
++		return -1;
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_get_tx_fifo_size() - TX FIFO size
++ * @d:		struct dvobj_priv*
++ * @size:	TX FIFO size, unit is byte.
++ *
++ * Get TX FIFO size(byte) from HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u32 val = 0;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_TXFIFO_SIZE, &val);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	*size = val;
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_get_rx_fifo_size() - RX FIFO size
++ * @d:		struct dvobj_priv*
++ * @size:	RX FIFO size, unit is byte
++ *
++ * Get RX FIFO size(byte) from HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u32 val = 0;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_RXFIFO_SIZE, &val);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	*size = val;
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_get_rsvd_drv_pg_bndy() - Reserve page boundary of driver
++ * @d:		struct dvobj_priv*
++ * @size:	Page size, unit is byte
++ *
++ * Get reserve page boundary of driver from HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u16 val = 0;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_RSVD_PG_BNDY, &val);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	*bndy = val;
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_get_page_size() - Page size
++ * @d:		struct dvobj_priv*
++ * @size:	Page size, unit is byte
++ *
++ * Get TX/RX page size(byte) from HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u32 val = 0;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_PAGE_SIZE, &val);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	*size = val;
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_get_tx_agg_align_size() - TX aggregation align size
++ * @d:		struct dvobj_priv*
++ * @size:	TX aggregation align size, unit is byte
++ *
++ * Get TX aggregation align size(byte) from HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u16 val = 0;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_TX_AGG_ALIGN_SIZE, &val);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	*size = val;
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_get_rx_agg_align_size() - RX aggregation align size
++ * @d:		struct dvobj_priv*
++ * @size:	RX aggregation align size, unit is byte
++ *
++ * Get RX aggregation align size(byte) from HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u8 val = 0;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_RX_AGG_ALIGN_SIZE, &val);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	*size = val;
++
++	return 0;
++}
++
++/*
++ * Description:
++ *	Get RX driver info size. RX driver info is a small memory space between
++ *	scriptor and RX payload.
++ *
++ *	+-------------------------+
++ *	| RX descriptor           |
++ *	| usually 24 bytes        |
++ *	+-------------------------+
++ *	| RX driver info          |
++ *	| depends on driver cfg   |
++ *	+-------------------------+
++ *	| RX paylad               |
++ *	|                         |
++ *	+-------------------------+
++ *
++ * Parameter:
++ *	d	pointer to struct dvobj_priv of driver
++ *	sz	rx driver info size in bytes.
++ *
++ * Return:
++ *	0	Success
++ *	other	Fail
++ */
++int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *d, u8 *sz)
++{
++	enum halmac_ret_status status;
++	struct halmac_adapter *halmac = dvobj_to_halmac(d);
++	struct halmac_api *api = HALMAC_GET_API(halmac);
++	u8 dw = 0;
++
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_DRV_INFO_SIZE, &dw);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	*sz = dw * 8;
++	return 0;
++}
++
++/**
++ * rtw_halmac_get_tx_desc_size() - TX descriptor size
++ * @d:		struct dvobj_priv*
++ * @size:	TX descriptor size, unit is byte.
++ *
++ * Get TX descriptor size(byte) from HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u32 val = 0;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_TX_DESC_SIZE, &val);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	*size = val;
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_get_rx_desc_size() - RX descriptor size
++ * @d:		struct dvobj_priv*
++ * @size:	RX descriptor size, unit is byte.
++ *
++ * Get RX descriptor size(byte) from HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u32 val = 0;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_RX_DESC_SIZE, &val);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	*size = val;
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_get_tx_dma_ch_map() - Get TX DMA channel Map for tx desc
++ * @d:		struct dvobj_priv*
++ * @dma_ch_map:	return map of QSEL to DMA channel
++ * @map_size:	size of dma_ch_map
++ *		Suggest size to be last valid QSEL(QSLT_CMD)+1 or full QSLT
++ *		size(0x20)
++ *
++ * 8814B would need this to get mapping of QSEL to DMA channel for TX desc.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_get_tx_dma_ch_map(struct dvobj_priv *d, u8 *dma_ch_map, u8 map_size)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	struct halmac_rqpn_ch_map map;
++	enum halmac_dma_ch channel = HALMAC_DMA_CH_UNDEFINE;
++	u8 qsel;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_RQPN_CH_MAPPING, &map);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	for (qsel = 0; qsel < map_size; qsel++) {
++		switch (qsel) {
++		/*case QSLT_VO:*/
++		case 0x06:
++		case 0x07:
++			channel = map.dma_map_vo;
++			break;
++		/*case QSLT_VI:*/
++		case 0x04:
++		case 0x05:
++			channel = map.dma_map_vi;
++			break;
++		/*case QSLT_BE:*/
++		case 0x00:
++		case 0x03:
++			channel = map.dma_map_be;
++			break;
++		/*case QSLT_BK:*/
++		case 0x01:
++		case 0x02:
++			channel = map.dma_map_bk;
++			break;
++		/*case QSLT_BEACON:*/
++		case 0x10:
++			channel = HALMAC_DMA_CH_BCN;
++			break;
++		/*case QSLT_HIGH:*/
++		case 0x11:
++			channel = map.dma_map_hi;
++			break;
++		/*case QSLT_MGNT:*/
++		case 0x12:
++			channel = map.dma_map_mg;
++			break;
++		/*case QSLT_CMD:*/
++		case 0x13:
++			channel = HALMAC_DMA_CH_H2C;
++			break;
++		default:
++			/*RTW_ERR("%s: invalid qsel=0x%x\n", __FUNCTION__, qsel);*/
++			channel = HALMAC_DMA_CH_UNDEFINE;
++			break;
++		}
++		dma_ch_map[qsel] = (u8)channel;
++	}
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_get_fw_max_size() - Firmware MAX size
++ * @d:		struct dvobj_priv*
++ * @size:	MAX Firmware size, unit is byte.
++ *
++ * Get Firmware MAX size(byte) from HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++static int rtw_halmac_get_fw_max_size(struct dvobj_priv *d, u32 *size)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u32 val = 0;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_FW_MAX_SIZE, &val);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	*size = val;
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_get_ori_h2c_size() - Original H2C MAX size
++ * @d:		struct dvobj_priv*
++ * @size:	H2C MAX size, unit is byte.
++ *
++ * Get original H2C MAX size(byte) from HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u32 val = 0;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_ORI_H2C_SIZE, &val);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	*size = val;
++
++	return 0;
++}
++
++int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size)
++{
++	enum halmac_ret_status status;
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	u8 val;
++
++
++	if (!size)
++		return -1;
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_OQT_SIZE, &val);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	*size = val;
++	return 0;
++}
++
++int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num)
++{
++	enum halmac_ret_status status;
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	u8 val;
++
++
++	if (!num)
++		return -1;
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_QUEUE_NUM, &val);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	*num = val;
++	return 0;
++}
++
++/**
++ * rtw_halmac_get_mac_address() - Get MAC address of specific port
++ * @d:		struct dvobj_priv*
++ * @hwport:	port
++ * @addr:	buffer for storing MAC address
++ *
++ * Get MAC address of specific port from HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_portid port;
++	union halmac_wlan_addr hwa;
++	enum halmac_ret_status status;
++	int err = -1;
++
++
++	if (!addr)
++		goto out;
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++	port = _hw_port_drv2halmac(hwport);
++	_rtw_memset(&hwa, 0, sizeof(hwa));
++
++	status = api->halmac_get_mac_addr(halmac, port, &hwa);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++	_rtw_memcpy(addr, hwa.addr, 6);
++
++	err = 0;
++out:
++	return err;
++}
++
++/**
++ * rtw_halmac_get_network_type() - Get network type of specific port
++ * @d:		struct dvobj_priv*
++ * @hwport:	port
++ * @type:	buffer to put network type (_HW_STATE_*)
++ *
++ * Get network type of specific port from HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type)
++{
++#if 0
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_portid port;
++	enum halmac_network_type_select network;
++	enum halmac_ret_status status;
++	int err = -1;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++	port = _hw_port_drv2halmac(hwport);
++	network = HALMAC_NETWORK_UNDEFINE;
++
++	status = api->halmac_get_net_type(halmac, port, &network);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++	*type = _network_type_halmac2drv(network);
++
++	err = 0;
++out:
++	return err;
++#else
++	struct _ADAPTER *a;
++	enum halmac_portid port;
++	enum halmac_network_type_select network;
++	u32 val;
++	int err = -1;
++
++
++	a = dvobj_get_primary_adapter(d);
++	port = _hw_port_drv2halmac(hwport);
++	network = HALMAC_NETWORK_UNDEFINE;
++
++	switch (port) {
++	case HALMAC_PORTID0:
++		val = rtw_read32(a, REG_CR);
++		network = BIT_GET_NETYPE0(val);
++		break;
++
++	case HALMAC_PORTID1:
++		val = rtw_read32(a, REG_CR);
++		network = BIT_GET_NETYPE1(val);
++		break;
++
++	case HALMAC_PORTID2:
++		val = rtw_read32(a, REG_CR_EXT);
++		network = BIT_GET_NETYPE2(val);
++		break;
++
++	case HALMAC_PORTID3:
++		val = rtw_read32(a, REG_CR_EXT);
++		network = BIT_GET_NETYPE3(val);
++		break;
++
++	case HALMAC_PORTID4:
++		val = rtw_read32(a, REG_CR_EXT);
++		network = BIT_GET_NETYPE4(val);
++		break;
++
++	default:
++		goto out;
++	}
++
++	*type = _network_type_halmac2drv(network);
++
++	err = 0;
++out:
++	return err;
++#endif
++}
++
++/**
++ * rtw_halmac_get_bcn_ctrl() - Get beacon control setting of specific port
++ * @d:		struct dvobj_priv*
++ * @hwport:	port
++ * @bcn_ctrl:	setting of beacon control
++ *
++ * Get beacon control setting of specific port from HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport,
++			struct rtw_halmac_bcn_ctrl *bcn_ctrl)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_portid port;
++	struct halmac_bcn_ctrl ctrl;
++	enum halmac_ret_status status;
++	int err = -1;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++	port = _hw_port_drv2halmac(hwport);
++	_rtw_memset(&ctrl, 0, sizeof(ctrl));
++
++	status = api->halmac_rw_bcn_ctrl(halmac, port, 0, &ctrl);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++	_beacon_ctrl_halmac2drv(&ctrl, bcn_ctrl);
++
++	err = 0;
++out:
++	return err;
++}
++
++/*
++ * Note:
++ *	When this function return, the register REG_RCR may be changed.
++ */
++int rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	int err = -1;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_cfg_drv_info(halmac, info);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++	err = 0;
++out:
++	/* Sync driver RCR cache with register setting */
++	rtw_hal_get_hwreg(dvobj_get_primary_adapter(d), HW_VAR_RCR, NULL);
++
++	return err;
++}
++
++/**
++ * rtw_halmac_set_max_dl_fw_size() - Set the MAX download firmware size
++ * @d:		struct dvobj_priv*
++ * @size:	the max download firmware size in one I/O
++ *
++ * Set the max download firmware size in one I/O.
++ * Please also consider the max size of the callback function "SEND_RSVD_PAGE"
++ * could accept, because download firmware would call "SEND_RSVD_PAGE" to send
++ * firmware to IC.
++ *
++ * If the value of "size" is not even, it would be rounded down to nearest
++ * even, and 0 and 1 are both invalid value.
++ *
++ * Return 0 for setting OK, otherwise fail.
++ */
++int rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++
++
++	if (!size || (size == 1))
++		return -1;
++
++	mac = dvobj_to_halmac(d);
++	if (!mac) {
++		RTW_ERR("%s: HALMAC is not ready!!\n", __FUNCTION__);
++		return -1;
++	}
++	api = HALMAC_GET_API(mac);
++
++	size &= ~1; /* round down to even */
++	status = api->halmac_cfg_max_dl_size(mac, size);
++	if (status != HALMAC_RET_SUCCESS) {
++		RTW_WARN("%s: Fail to cfg_max_dl_size(%d), err=%d!!\n",
++			 __FUNCTION__, size, status);
++		return -1;
++	}
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_set_mac_address() - Set mac address of specific port
++ * @d:		struct dvobj_priv*
++ * @hwport:	port
++ * @addr:	mac address
++ *
++ * Set self mac address of specific port to HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_portid port;
++	union halmac_wlan_addr hwa;
++	enum halmac_ret_status status;
++	int err = -1;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	port = _hw_port_drv2halmac(hwport);
++	_rtw_memset(&hwa, 0, sizeof(hwa));
++	_rtw_memcpy(hwa.addr, addr, 6);
++
++	status = api->halmac_cfg_mac_addr(halmac, port, &hwa);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++	err = 0;
++out:
++	return err;
++}
++
++/**
++ * rtw_halmac_set_bssid() - Set BSSID of specific port
++ * @d:		struct dvobj_priv*
++ * @hwport:	port
++ * @addr:	BSSID, mac address of AP
++ *
++ * Set BSSID of specific port to HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_portid port;
++	union halmac_wlan_addr hwa;
++	enum halmac_ret_status status;
++	int err = -1;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++	port = _hw_port_drv2halmac(hwport);
++
++	_rtw_memset(&hwa, 0, sizeof(hwa));
++	_rtw_memcpy(hwa.addr, addr, 6);
++	status = api->halmac_cfg_bssid(halmac, port, &hwa);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++	err = 0;
++out:
++	return err;
++}
++
++/**
++ * rtw_halmac_set_tx_address() - Set transmitter address of specific port
++ * @d:		struct dvobj_priv*
++ * @hwport:	port
++ * @addr:	transmitter address
++ *
++ * Set transmitter address of specific port to HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_portid port;
++	union halmac_wlan_addr hwa;
++	enum halmac_ret_status status;
++	int err = -1;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++	port = _hw_port_drv2halmac(hwport);
++	_rtw_memset(&hwa, 0, sizeof(hwa));
++	_rtw_memcpy(hwa.addr, addr, 6);
++
++	status = api->halmac_cfg_transmitter_addr(halmac, port, &hwa);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++	err = 0;
++out:
++	return err;
++}
++
++/**
++ * rtw_halmac_set_network_type() - Set network type of specific port
++ * @d:		struct dvobj_priv*
++ * @hwport:	port
++ * @type:	network type (_HW_STATE_*)
++ *
++ * Set network type of specific port to HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_portid port;
++	enum halmac_network_type_select network;
++	enum halmac_ret_status status;
++	int err = -1;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++	port = _hw_port_drv2halmac(hwport);
++	network = _network_type_drv2halmac(type);
++
++	status = api->halmac_cfg_net_type(halmac, port, network);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++	err = 0;
++out:
++	return err;
++}
++
++/**
++ * rtw_halmac_reset_tsf() - Reset TSF timer of specific port
++ * @d:		struct dvobj_priv*
++ * @hwport:	port
++ *
++ * Notice HALMAC to reset timing synchronization function(TSF) timer of
++ * specific port.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_portid port;
++	enum halmac_ret_status status;
++	int err = -1;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++	port = _hw_port_drv2halmac(hwport);
++
++	status = api->halmac_cfg_tsf_rst(halmac, port);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++	err = 0;
++out:
++	return err;
++}
++
++/**
++ * rtw_halmac_set_bcn_interval() - Set beacon interval of each port
++ * @d:		struct dvobj_priv*
++ * @hwport:	port
++ * @space:	beacon interval, unit is ms
++ *
++ * Set beacon interval of specific port to HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport,
++				u32 interval)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_portid port;
++	enum halmac_ret_status status;
++	int err = -1;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++	port = _hw_port_drv2halmac(hwport);
++
++	status = api->halmac_cfg_bcn_space(halmac, port, interval);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++	err = 0;
++out:
++	return err;
++}
++
++/**
++ * rtw_halmac_set_bcn_ctrl() - Set beacon control setting of each port
++ * @d:		struct dvobj_priv*
++ * @hwport:	port
++ * @bcn_ctrl:	setting of beacon control
++ *
++ * Set beacon control setting of specific port to HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport,
++			struct rtw_halmac_bcn_ctrl *bcn_ctrl)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_portid port;
++	struct halmac_bcn_ctrl ctrl;
++	enum halmac_ret_status status;
++	int err = -1;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++	port = _hw_port_drv2halmac(hwport);
++	_rtw_memset(&ctrl, 0, sizeof(ctrl));
++	_beacon_ctrl_drv2halmac(bcn_ctrl, &ctrl);
++
++	status = api->halmac_rw_bcn_ctrl(halmac, port, 1, &ctrl);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++	err = 0;
++out:
++	return err;
++}
++
++/**
++ * rtw_halmac_set_aid() - Set association identifier(AID) of specific port
++ * @d:		struct dvobj_priv*
++ * @hwport:	port
++ * @aid:	Association identifier
++ *
++ * Set association identifier(AID) of specific port to HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_portid port;
++	enum halmac_ret_status status;
++	int err = -1;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++	port = _hw_port_drv2halmac(hwport);
++
++#if 0
++	status = api->halmac_cfg_aid(halmac, port, aid);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++#else
++{
++	struct _ADAPTER *a;
++	u32 addr;
++	u16 val;
++
++	a = dvobj_get_primary_adapter(d);
++
++	switch (port) {
++	case 0:
++		addr = REG_BCN_PSR_RPT;
++		val = rtw_read16(a, addr);
++		val = BIT_SET_PS_AID_0(val, aid);
++		rtw_write16(a, addr, val);
++		break;
++
++	case 1:
++		addr = REG_BCN_PSR_RPT1;
++		val = rtw_read16(a, addr);
++		val = BIT_SET_PS_AID_1(val, aid);
++		rtw_write16(a, addr, val);
++		break;
++
++	case 2:
++		addr = REG_BCN_PSR_RPT2;
++		val = rtw_read16(a, addr);
++		val = BIT_SET_PS_AID_2(val, aid);
++		rtw_write16(a, addr, val);
++		break;
++
++	case 3:
++		addr = REG_BCN_PSR_RPT3;
++		val = rtw_read16(a, addr);
++		val = BIT_SET_PS_AID_3(val, aid);
++		rtw_write16(a, addr, val);
++		break;
++
++	case 4:
++		addr = REG_BCN_PSR_RPT4;
++		val = rtw_read16(a, addr);
++		val = BIT_SET_PS_AID_4(val, aid);
++		rtw_write16(a, addr, val);
++		break;
++
++	default:
++		goto out;
++	}
++}
++#endif
++
++	err = 0;
++out:
++	return err;
++}
++
++int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_cfg_ch_bw(mac, channel, pri_ch_idx, bw);
++	if (HALMAC_RET_SUCCESS != status)
++		return -1;
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_set_edca() - config edca parameter
++ * @d:		struct dvobj_priv*
++ * @queue:	XMIT_[VO/VI/BE/BK]_QUEUE
++ * @aifs:	Arbitration inter-frame space(AIFS)
++ * @cw:		Contention window(CW)
++ * @txop:	MAX Transmit Opportunity(TXOP)
++ *
++ * Return: 0 if process OK, otherwise -1.
++ */
++int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_acq_id ac;
++	struct halmac_edca_para edca;
++	enum halmac_ret_status status;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	switch (queue) {
++	case XMIT_VO_QUEUE:
++		ac = HALMAC_ACQ_ID_VO;
++		break;
++	case XMIT_VI_QUEUE:
++		ac = HALMAC_ACQ_ID_VI;
++		break;
++	case XMIT_BE_QUEUE:
++		ac = HALMAC_ACQ_ID_BE;
++		break;
++	case XMIT_BK_QUEUE:
++		ac = HALMAC_ACQ_ID_BK;
++		break;
++	default:
++		return -1;
++	}
++
++	edca.aifs = aifs;
++	edca.cw = cw;
++	edca.txop_limit = txop;
++
++	status = api->halmac_cfg_edca_para(mac, ac, &edca);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_set_rts_full_bw() - Send RTS to all covered channels
++ * @d:		struct dvobj_priv*
++ * @enable:	_TRUE(enable), _FALSE(disable)
++ *
++ * Hradware will duplicate RTS packet to all channels which are covered in used
++ * bandwidth.
++ *
++ * Return 0 if process OK, otherwise -1.
++ */
++int rtw_halmac_set_rts_full_bw(struct dvobj_priv *d, u8 enable)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u8 full;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++	full = (enable == _TRUE) ? 1 : 0;
++
++	status = api->halmac_set_hw_value(mac, HALMAC_HW_RTS_FULL_BW, &full);
++	if (HALMAC_RET_SUCCESS != status)
++		return -1;
++
++	return 0;
++}
++
++#ifdef RTW_HALMAC_DBG_POWER_SWITCH
++static void _dump_mac_reg(struct dvobj_priv *d, u32 start, u32 end)
++{
++	struct _ADAPTER *adapter;
++	int i, j = 1;
++
++
++	adapter = dvobj_get_primary_adapter(d);
++	for (i = start; i < end; i += 4) {
++		if (j % 4 == 1)
++			RTW_PRINT("0x%04x", i);
++		_RTW_PRINT(" 0x%08x ", rtw_read32(adapter, i));
++		if ((j++) % 4 == 0)
++			_RTW_PRINT("\n");
++	}
++}
++
++void dump_dbg_val(struct _ADAPTER *a, u32 reg)
++{
++	u32 v32;
++
++
++	rtw_write8(a, 0x3A, reg);
++	v32 = rtw_read32(a, 0xC0);
++	RTW_PRINT("0x3A = %02x, 0xC0 = 0x%08x\n",reg, v32);
++}
++
++#ifdef CONFIG_PCI_HCI
++static void _dump_pcie_cfg_space(struct dvobj_priv *d)
++{
++	struct _ADAPTER *padapter = dvobj_get_primary_adapter(d);
++	struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
++	struct pci_dev  *pdev = pdvobjpriv->ppcidev;
++	struct pci_dev  *bridge_pdev = pdev->bus->self;
++
++        u32 tmp[4] = { 0 };
++        u32 i, j;
++
++	RTW_PRINT("\n*****  PCI Device Configuration Space *****\n\n");
++
++        for(i = 0; i < 0x100; i += 0x10)
++        {
++                for (j = 0 ; j < 4 ; j++)
++                        pci_read_config_dword(pdev, i + j * 4, tmp+j);
++
++        	RTW_PRINT("%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
++                        i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,
++                        tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,
++                        tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,
++                        tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);
++        }
++
++	RTW_PRINT("\n*****  PCI Host Device Configuration Space*****\n\n");
++
++        for(i = 0; i < 0x100; i += 0x10)
++        {
++                for (j = 0 ; j < 4 ; j++)
++                        pci_read_config_dword(bridge_pdev, i + j * 4, tmp+j);
++
++        	RTW_PRINT("%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
++                        i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,
++                        tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,
++                        tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,
++                        tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);
++        }
++}
++#endif
++
++static void _dump_mac_reg_for_power_switch(struct dvobj_priv *d,
++					   const char* caller, char* desc)
++{
++	struct _ADAPTER *a;
++	u8 v8;
++
++
++	RTW_PRINT("%s: %s\n", caller, desc);
++	RTW_PRINT("======= MAC REG =======\n");
++	/* page 0/1 */
++	_dump_mac_reg(d, 0x0, 0x200);
++	_dump_mac_reg(d, 0x300, 0x400); /* also dump page 3 */
++
++	/* dump debug register */
++	a = dvobj_get_primary_adapter(d);
++
++#ifdef CONFIG_PCI_HCI
++	_dump_pcie_cfg_space(d);
++
++	v8 = rtw_read8(a, 0xF6) | 0x01;
++	rtw_write8(a, 0xF6, v8);
++	RTW_PRINT("0xF6 = %02x\n", v8);
++
++	dump_dbg_val(a, 0x63);
++	dump_dbg_val(a, 0x64);
++	dump_dbg_val(a, 0x68);
++	dump_dbg_val(a, 0x69);
++	dump_dbg_val(a, 0x6a);
++	dump_dbg_val(a, 0x6b);
++	dump_dbg_val(a, 0x71);
++	dump_dbg_val(a, 0x72);
++#endif
++}
++
++static enum halmac_ret_status _power_switch(struct halmac_adapter *halmac,
++					    struct halmac_api *api,
++					    enum halmac_mac_power pwr)
++{
++	enum halmac_ret_status status;
++	char desc[80] = {0};
++
++
++	rtw_sprintf(desc, 80, "before calling power %s",
++				(pwr==HALMAC_MAC_POWER_ON)?"on":"off");
++	_dump_mac_reg_for_power_switch((struct dvobj_priv *)halmac->drv_adapter,
++			__FUNCTION__, desc);
++
++	status = api->halmac_mac_power_switch(halmac, pwr);
++	RTW_PRINT("%s: status=%d\n", __FUNCTION__, status);
++
++	rtw_sprintf(desc, 80, "after calling power %s",
++				(pwr==HALMAC_MAC_POWER_ON)?"on":"off");
++	_dump_mac_reg_for_power_switch((struct dvobj_priv *)halmac->drv_adapter,
++			__FUNCTION__, desc);
++
++	return status;
++}
++#else /* !RTW_HALMAC_DBG_POWER_SWITCH */
++#define _power_switch(mac, api, pwr)	(api)->halmac_mac_power_switch(mac, pwr)
++#endif /* !RTW_HALMAC_DBG_POWER_SWITCH */
++
++/*
++ * Description:
++ *	Power on device hardware.
++ *	[Notice!] If device's power state is on before,
++ *	it would be power off first and turn on power again.
++ *
++ * Return:
++ *	0	power on success
++ *	-1	power on fail
++ *	-2	power state unchange
++ */
++int rtw_halmac_poweron(struct dvobj_priv *d)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	int err = -1;
++#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B)
++	struct _ADAPTER *a;
++	u8 v8;
++	u32 addr;
++
++	a = dvobj_get_primary_adapter(d);
++#endif
++
++	halmac = dvobj_to_halmac(d);
++	if (!halmac)
++		goto out;
++
++	api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_pre_init_system_cfg(halmac);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++#ifdef CONFIG_SDIO_HCI
++	status = api->halmac_sdio_cmd53_4byte(halmac, HALMAC_SDIO_CMD53_4BYTE_MODE_RW);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++#endif /* CONFIG_SDIO_HCI */
++
++#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B)
++	addr = 0x3F3;
++	v8 = rtw_read8(a, addr);
++	RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8);
++	/* are we in pcie debug mode? */
++	if (!(v8 & BIT(2))) {
++		RTW_PRINT("%s: Enable pcie debug mode\n", __FUNCTION__);
++		v8 |= BIT(2);
++		v8 = rtw_write8(a, addr, v8);
++	}
++#endif
++
++	status = _power_switch(halmac, api, HALMAC_MAC_POWER_ON);
++	if (HALMAC_RET_PWR_UNCHANGE == status) {
++
++#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B)
++		addr = 0x3F3;
++		v8 = rtw_read8(a, addr);
++		RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8);
++		
++		/* are we in pcie debug mode? */
++		if (!(v8 & BIT(2))) {
++			RTW_PRINT("%s: Enable pcie debug mode\n", __FUNCTION__);
++			v8 |= BIT(2);
++			v8 = rtw_write8(a, addr, v8);
++		} else if (v8 & BIT(0)) {
++			/* DMA stuck */
++			addr = 0x1350;
++			v8 = rtw_read8(a, addr);
++			RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8);
++			RTW_PRINT("%s: recover DMA stuck\n", __FUNCTION__);
++			v8 |= BIT(6);
++			v8 = rtw_write8(a, addr, v8);
++			RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8);
++		}
++#endif
++		/*
++		 * Work around for warm reboot but device not power off,
++		 * but it would also fall into this case when auto power on is enabled.
++		 */
++		_power_switch(halmac, api, HALMAC_MAC_POWER_OFF);
++		status = _power_switch(halmac, api, HALMAC_MAC_POWER_ON);
++		RTW_WARN("%s: Power state abnormal, try to recover...%s\n",
++			 __FUNCTION__, (HALMAC_RET_SUCCESS == status)?"OK":"FAIL!");
++	}
++	if (HALMAC_RET_SUCCESS != status) {
++		if (HALMAC_RET_PWR_UNCHANGE == status)
++			err = -2;
++		goto out;
++	}
++
++	status = api->halmac_init_system_cfg(halmac);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++	err = 0;
++out:
++	return err;
++}
++
++/*
++ * Description:
++ *	Power off device hardware.
++ *
++ * Return:
++ *	0	Power off success
++ *	-1	Power off fail
++ */
++int rtw_halmac_poweroff(struct dvobj_priv *d)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	int err = -1;
++
++
++	halmac = dvobj_to_halmac(d);
++	if (!halmac)
++		goto out;
++
++	api = HALMAC_GET_API(halmac);
++
++	status = _power_switch(halmac, api, HALMAC_MAC_POWER_OFF);
++	if ((HALMAC_RET_SUCCESS != status)
++	    && (HALMAC_RET_PWR_UNCHANGE != status))
++		goto out;
++
++	err = 0;
++out:
++	return err;
++}
++
++#ifdef CONFIG_SUPPORT_TRX_SHARED
++static inline enum halmac_rx_fifo_expanding_mode _trx_share_mode_drv2halmac(u8 trx_share_mode)
++{
++	if (0 == trx_share_mode)
++		return HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE;
++	else if (1 == trx_share_mode)
++		return HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK;
++	else if (2 == trx_share_mode)
++		return HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK;
++	else if (3 == trx_share_mode)
++		return HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK;
++	else
++		return HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE;
++}
++
++static enum halmac_rx_fifo_expanding_mode _rtw_get_trx_share_mode(struct _ADAPTER *adapter)
++{
++	struct registry_priv *registry_par = &adapter->registrypriv;
++
++	return _trx_share_mode_drv2halmac(registry_par->trx_share_mode);
++}
++
++void dump_trx_share_mode(void *sel, struct _ADAPTER *adapter)
++{
++	struct registry_priv  *registry_par = &adapter->registrypriv;
++	u8 mode = _trx_share_mode_drv2halmac(registry_par->trx_share_mode);
++
++	if (HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK == mode)
++		RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_1");
++	else if (HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK == mode)
++		RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_2");
++	else if (HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK == mode)
++		RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_3");
++	else
++		RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "DISABLE");
++}
++#endif
++
++static enum halmac_drv_rsvd_pg_num _rsvd_page_num_drv2halmac(u16 num)
++{
++	if (num <= 8)
++		return HALMAC_RSVD_PG_NUM8;
++	if (num <= 16)
++		return HALMAC_RSVD_PG_NUM16;
++	if (num <= 24)
++		return HALMAC_RSVD_PG_NUM24;
++	if (num <= 32)
++		return HALMAC_RSVD_PG_NUM32;
++	if (num <= 64)
++		return HALMAC_RSVD_PG_NUM64;
++	if (num <= 128)
++		return HALMAC_RSVD_PG_NUM128;
++
++	if (num > 256)
++		RTW_WARN("%s: Fail to allocate RSVD page(%d)!!"
++			 " The MAX RSVD page number is 256...\n",
++			 __FUNCTION__, num);
++
++	return HALMAC_RSVD_PG_NUM256;
++}
++
++static u16 _rsvd_page_num_halmac2drv(enum halmac_drv_rsvd_pg_num rsvd_page_number)
++{
++	u16 num = 0;
++
++
++	switch (rsvd_page_number) {
++	case HALMAC_RSVD_PG_NUM8:
++		num = 8;
++		break;
++
++	case HALMAC_RSVD_PG_NUM16:
++		num = 16;
++		break;
++
++	case HALMAC_RSVD_PG_NUM24:
++		num = 24;
++		break;
++
++	case HALMAC_RSVD_PG_NUM32:
++		num = 32;
++		break;
++
++	case HALMAC_RSVD_PG_NUM64:
++		num = 64;
++		break;
++
++	case HALMAC_RSVD_PG_NUM128:
++		num = 128;
++		break;
++
++	case HALMAC_RSVD_PG_NUM256:
++		num = 256;
++		break;
++	}
++
++	return num;
++}
++
++static enum halmac_trx_mode _choose_trx_mode(struct dvobj_priv *d)
++{
++	PADAPTER p;
++
++
++	p = dvobj_get_primary_adapter(d);
++
++	if (p->registrypriv.wifi_spec)
++		return HALMAC_TRX_MODE_WMM;
++
++#ifdef CONFIG_SUPPORT_TRX_SHARED
++	if (_rtw_get_trx_share_mode(p))
++		return HALMAC_TRX_MODE_TRXSHARE;
++#endif
++
++	return HALMAC_TRX_MODE_NORMAL;
++}
++
++static inline enum halmac_rf_type _rf_type_drv2halmac(enum rf_type rf_drv)
++{
++	enum halmac_rf_type rf_mac;
++
++
++	switch (rf_drv) {
++	case RF_1T1R:
++		rf_mac = HALMAC_RF_1T1R;
++		break;
++	case RF_1T2R:
++		rf_mac = HALMAC_RF_1T2R;
++		break;
++	case RF_2T2R:
++		rf_mac = HALMAC_RF_2T2R;
++		break;
++	case RF_2T3R:
++		rf_mac = HALMAC_RF_2T3R;
++		break;
++	case RF_2T4R:
++		rf_mac = HALMAC_RF_2T4R;
++		break;
++	case RF_3T3R:
++		rf_mac = HALMAC_RF_3T3R;
++		break;
++	case RF_3T4R:
++		rf_mac = HALMAC_RF_3T4R;
++		break;
++	case RF_4T4R:
++		rf_mac = HALMAC_RF_4T4R;
++		break;
++	default:
++		rf_mac = HALMAC_RF_MAX_TYPE;
++		RTW_ERR("%s: Invalid RF type(0x%x)!\n", __FUNCTION__, rf_drv);
++		break;
++	}
++
++	return rf_mac;
++}
++
++static inline enum rf_type _rf_type_halmac2drv(enum halmac_rf_type rf_mac)
++{
++	enum rf_type rf_drv;
++
++
++	switch (rf_mac) {
++	case HALMAC_RF_1T2R:
++		rf_drv = RF_1T2R;
++		break;
++	case HALMAC_RF_2T4R:
++		rf_drv = RF_2T4R;
++		break;
++	case HALMAC_RF_2T2R:
++	case HALMAC_RF_2T2R_GREEN:
++		rf_drv = RF_2T2R;
++		break;
++	case HALMAC_RF_2T3R:
++		rf_drv = RF_2T3R;
++		break;
++	case HALMAC_RF_1T1R:
++		rf_drv = RF_1T1R;
++		break;
++	case HALMAC_RF_3T3R:
++		rf_drv = RF_3T3R;
++		break;
++	case HALMAC_RF_3T4R:
++		rf_drv = RF_3T4R;
++		break;
++	case HALMAC_RF_4T4R:
++		rf_drv = RF_4T4R;
++		break;
++	default:
++		rf_drv = RF_TYPE_MAX;
++		RTW_ERR("%s: Invalid RF type(0x%x)!\n", __FUNCTION__, rf_mac);
++		break;
++	}
++
++	return rf_drv;
++}
++
++static enum odm_cut_version _cut_version_drv2phydm(
++				enum tag_HAL_Cut_Version_Definition cut_drv)
++{
++	enum odm_cut_version cut_phydm = ODM_CUT_A;
++	u32 diff;
++
++
++	if (cut_drv > K_CUT_VERSION)
++		RTW_WARN("%s: unknown cut_ver=%d !!\n", __FUNCTION__, cut_drv);
++
++	diff = cut_drv - A_CUT_VERSION;
++	cut_phydm += diff;
++
++	return cut_phydm;
++}
++
++static int _send_general_info_by_reg(struct dvobj_priv *d,
++				     struct halmac_general_info *info)
++{
++	struct _ADAPTER *a;
++	struct hal_com_data *hal;
++	enum tag_HAL_Cut_Version_Definition cut_drv;
++	enum rf_type rftype;
++	enum odm_cut_version cut_phydm;
++	u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0};
++
++
++	a = dvobj_get_primary_adapter(d);
++	hal = GET_HAL_DATA(a);
++	rftype = _rf_type_halmac2drv(info->rf_type);
++	cut_drv = GET_CVID_CUT_VERSION(hal->version_id);
++	cut_phydm = _cut_version_drv2phydm(cut_drv);
++
++#define CLASS_GENERAL_INFO_REG				0x02
++#define CMD_ID_GENERAL_INFO_REG				0x0C
++#define GENERAL_INFO_REG_SET_CMD_ID(buf, v)		SET_BITS_TO_LE_4BYTE(buf, 0, 5, v)
++#define GENERAL_INFO_REG_SET_CLASS(buf, v)		SET_BITS_TO_LE_4BYTE(buf, 5, 3, v)
++#define GENERAL_INFO_REG_SET_RFE_TYPE(buf, v)		SET_BITS_TO_LE_4BYTE(buf, 8, 8, v)
++#define GENERAL_INFO_REG_SET_RF_TYPE(buf, v)		SET_BITS_TO_LE_4BYTE(buf, 16, 8, v)
++#define GENERAL_INFO_REG_SET_CUT_VERSION(buf, v)	SET_BITS_TO_LE_4BYTE(buf, 24, 8, v)
++#define GENERAL_INFO_REG_SET_RX_ANT_STATUS(buf, v)	SET_BITS_TO_LE_1BYTE(buf+4, 0, 4, v)
++#define GENERAL_INFO_REG_SET_TX_ANT_STATUS(buf, v)	SET_BITS_TO_LE_1BYTE(buf+4, 4, 4, v)
++
++	GENERAL_INFO_REG_SET_CMD_ID(h2c, CMD_ID_GENERAL_INFO_REG);
++	GENERAL_INFO_REG_SET_CLASS(h2c, CLASS_GENERAL_INFO_REG);
++	GENERAL_INFO_REG_SET_RFE_TYPE(h2c, info->rfe_type);
++	GENERAL_INFO_REG_SET_RF_TYPE(h2c, rftype);
++	GENERAL_INFO_REG_SET_CUT_VERSION(h2c, cut_phydm);
++	GENERAL_INFO_REG_SET_RX_ANT_STATUS(h2c, info->rx_ant_status);
++	GENERAL_INFO_REG_SET_TX_ANT_STATUS(h2c, info->tx_ant_status);
++
++	return rtw_halmac_send_h2c(d, h2c);
++}
++
++static int _send_general_info(struct dvobj_priv *d)
++{
++	struct _ADAPTER *adapter;
++	struct hal_com_data *hal;
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	struct halmac_general_info info;
++	enum halmac_ret_status status;
++	enum rf_type rf = RF_1T1R;
++	enum bb_path txpath = BB_PATH_A;
++	enum bb_path rxpath = BB_PATH_A;
++	int err;
++
++
++	adapter = dvobj_get_primary_adapter(d);
++	hal = GET_HAL_DATA(adapter);
++	halmac = dvobj_to_halmac(d);
++	if (!halmac)
++		return -1;
++	api = HALMAC_GET_API(halmac);
++
++	_rtw_memset(&info, 0, sizeof(info));
++	info.rfe_type = (u8)hal->rfe_type;
++	rtw_hal_get_trx_path(d, &rf, &txpath, &rxpath);
++	info.rf_type = _rf_type_drv2halmac(rf);
++	info.tx_ant_status = (u8)txpath;
++	info.rx_ant_status = (u8)rxpath;
++	info.ext_pa = 0;	/* 2.4G or 5G? format not known */
++	info.package_type = hal->PackageType;
++	info.mp_mode = adapter->registrypriv.mp_mode;
++
++	status = api->halmac_send_general_info(halmac, &info);
++	switch (status) {
++	case HALMAC_RET_SUCCESS:
++		break;
++	case HALMAC_RET_NO_DLFW:
++		RTW_WARN("%s: halmac_send_general_info() fail because fw not dl!\n",
++			 __FUNCTION__);
++		/* go through */
++	default:
++		return -1;
++	}
++
++	err = _send_general_info_by_reg(d, &info);
++	if (err) {
++		RTW_ERR("%s: Fail to send general info by register!\n",
++			 __FUNCTION__);
++		return -1;
++	}
++
++	return 0;
++}
++
++static int _cfg_drv_rsvd_pg_num(struct dvobj_priv *d)
++{
++	struct _ADAPTER *a;
++	struct hal_com_data *hal;
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_drv_rsvd_pg_num rsvd_page_number;
++	enum halmac_ret_status status;
++	u16 drv_rsvd_num;
++	int ret = 0;
++
++
++	a = dvobj_get_primary_adapter(d);
++	hal = GET_HAL_DATA(a);
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	drv_rsvd_num = rtw_hal_get_rsvd_page_num(a);
++	rsvd_page_number = _rsvd_page_num_drv2halmac(drv_rsvd_num);
++	status = api->halmac_cfg_drv_rsvd_pg_num(halmac, rsvd_page_number);
++	if (status != HALMAC_RET_SUCCESS) {
++		ret = -1;
++		goto exit;
++	}
++	hal->drv_rsvd_page_number = _rsvd_page_num_halmac2drv(rsvd_page_number);
++
++exit:
++#ifndef DBG_RSVD_PAGE_CFG
++	if (drv_rsvd_num != _rsvd_page_num_halmac2drv(rsvd_page_number))
++#endif
++		RTW_INFO("%s: request %d pages => halmac %d pages %s\n"
++			, __FUNCTION__, drv_rsvd_num, _rsvd_page_num_halmac2drv(rsvd_page_number)
++			, ret ? "fail" : "success");
++
++	return ret;
++}
++
++static void _debug_dlfw_fail(struct dvobj_priv *d)
++{
++	struct _ADAPTER *a;
++	u32 addr;
++	u32 v32, i, n;
++
++
++	a = dvobj_get_primary_adapter(d);
++
++	/* read 0x80[15:0], 0x10F8[31:0] once */
++	addr = 0x80;
++	v32 = rtw_read16(a, addr);
++	RTW_PRINT("%s: 0x%X = 0x%04x\n", __FUNCTION__, addr, v32);
++
++	addr = 0x10F8;
++	v32 = rtw_read32(a, addr);
++	RTW_PRINT("%s: 0x%X = 0x%08x\n", __FUNCTION__, addr, v32);
++
++	/* read 0x10FC[31:0], 5 times */
++	addr = 0x10FC;
++	n = 5;
++	for (i = 0; i < n; i++) {
++		v32 = rtw_read32(a, addr);
++		RTW_PRINT("%s: 0x%X = 0x%08x (%u/%u)\n",
++			  __FUNCTION__, addr, v32, i, n);
++	}
++
++	/*
++	 * write 0x3A[7:0]=0x28 and 0xF6[7:0]=0x01
++	 * and then read 0xC0[31:0] 5 times
++	 */
++	addr = 0x3A;
++	v32 = 0x28;
++	rtw_write8(a, addr, (u8)v32);
++	v32 = rtw_read8(a, addr);
++	RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v32);
++
++	addr = 0xF6;
++	v32 = 0x1;
++	rtw_write8(a, addr, (u8)v32);
++	v32 = rtw_read8(a, addr);
++	RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v32);
++
++	addr = 0xC0;
++	n = 5;
++	for (i = 0; i < n; i++) {
++		v32 = rtw_read32(a, addr);
++		RTW_PRINT("%s: 0x%X = 0x%08x (%u/%u)\n",
++			  __FUNCTION__, addr, v32, i, n);
++	}
++
++	mac_reg_dump(NULL, a);
++#ifdef CONFIG_SDIO_HCI
++	RTW_PRINT("======= SDIO Local REG =======\n");
++	sdio_local_reg_dump(NULL, a);
++	RTW_PRINT("======= SDIO CCCR REG =======\n");
++	sd_f0_reg_dump(NULL, a);
++#endif /* CONFIG_SDIO_HCI */
++
++	/* read 0x80 after 10 secs */
++	rtw_msleep_os(10000);
++	addr = 0x80;
++	v32 = rtw_read16(a, addr);
++	RTW_PRINT("%s: 0x%X = 0x%04x (after 10 secs)\n",
++		  __FUNCTION__, addr, v32);
++}
++
++static enum halmac_ret_status _enter_cpu_sleep_mode(struct dvobj_priv *d)
++{
++	struct hal_com_data *hal;
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++
++
++	hal = GET_HAL_DATA(dvobj_get_primary_adapter(d));
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++#ifdef CONFIG_RTL8822B
++	/* Support after firmware version 21 */
++	if (hal->firmware_version < 21)
++		return HALMAC_RET_NOT_SUPPORT;
++#elif defined(CONFIG_RTL8821C)
++	/* Support after firmware version 13.6 or 16 */
++	if (hal->firmware_version == 13) {
++		if (hal->firmware_sub_version < 6)
++			return HALMAC_RET_NOT_SUPPORT;
++	} else if (hal->firmware_version < 16) {
++		return HALMAC_RET_NOT_SUPPORT;
++	}
++#endif
++
++	return api->halmac_enter_cpu_sleep_mode(mac);
++}
++
++/*
++ * _cpu_sleep() - Let IC CPU enter sleep mode
++ * @d:		struct dvobj_priv*
++ * @timeout:	time limit of wait, unit is ms
++ *		0 for no limit
++ *
++ * Return 0 for CPU in sleep mode, otherwise fail to enter sleep mode.
++ * Error codes definition are as follow:
++ * 	-1	HALMAC enter sleep return fail
++ *	-2	HALMAC get CPU mode return fail
++ *	-110	timeout
++ */
++static int _cpu_sleep(struct dvobj_priv *d, u32 timeout)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	enum halmac_wlcpu_mode mode = HALMAC_WLCPU_UNDEFINE;
++	systime start_t;
++	s32 period = 0;
++	u32 cnt = 0;
++	int err = 0;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	start_t = rtw_get_current_time();
++
++	status = _enter_cpu_sleep_mode(d);
++	if (status != HALMAC_RET_SUCCESS) {
++		if (status != HALMAC_RET_NOT_SUPPORT)
++			err = -1;
++		goto exit;
++	}
++
++	do {
++		cnt++;
++
++		mode = HALMAC_WLCPU_UNDEFINE;
++		status = api->halmac_get_cpu_mode(mac, &mode);
++
++		period = rtw_get_passing_time_ms(start_t);
++
++		if (status != HALMAC_RET_SUCCESS) {
++			err = -2;
++			break;
++		}
++		if (mode == HALMAC_WLCPU_SLEEP)
++			break;
++		if (period > timeout) {
++			err = -110;
++			break;
++		}
++
++		rtw_msleep_os(1);
++	} while (1);
++
++exit:
++	if (err)
++		RTW_ERR("%s: Fail to enter sleep mode! (%d, %d)\n",
++			__FUNCTION__, status, mode);
++
++	RTW_INFO("%s: Cost %dms to polling %u times. (err=%d)\n",
++		__FUNCTION__, period, cnt, err);
++
++	return err;
++}
++
++static void _init_trx_cfg_drv(struct dvobj_priv *d)
++{
++#ifdef CONFIG_PCI_HCI
++	rtw_hal_irp_reset(dvobj_get_primary_adapter(d));
++#endif
++}
++
++/*
++ * Description:
++ *	Downlaod Firmware Flow
++ *
++ * Parameters:
++ *	d	pointer of struct dvobj_priv
++ *	fw	firmware array
++ *	fwsize	firmware size
++ *	re_dl	re-download firmware or not
++ *		0: run in init hal flow, not re-download
++ *		1: it is a stand alone operation, not in init hal flow
++ *
++ * Return:
++ *	0	Success
++ *	others	Fail
++ */
++static int download_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize, u8 re_dl)
++{
++	PHAL_DATA_TYPE hal;
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	struct halmac_fw_version fw_vesion;
++	enum halmac_ret_status status;
++	int err = 0;
++
++
++	hal = GET_HAL_DATA(dvobj_get_primary_adapter(d));
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	if ((!fw) || (!fwsize))
++		return -1;
++
++	/* 1. Driver Stop Tx */
++	/* ToDo */
++
++	/* 2. Driver Check Tx FIFO is empty */
++	err = rtw_halmac_txfifo_wait_empty(d, 2000); /* wait 2s */
++	if (err) {
++		err = -1;
++		goto resume_tx;
++	}
++
++	/* 3. Config MAX download size */
++	/*
++	 * Already done in rtw_halmac_init_adapter() or
++	 * somewhere calling rtw_halmac_set_max_dl_fw_size().
++	 */
++
++	if (re_dl) {
++		/* 4. Enter IC CPU sleep mode */
++		err = _cpu_sleep(d, 2000);
++		if (err) {
++			RTW_ERR("%s: IC CPU fail to enter sleep mode!(%d)\n",
++				__FUNCTION__, err);
++			/* skip this error */
++			err = 0;
++		}
++	}
++
++	/* 5. Download Firmware */
++	status = api->halmac_download_firmware(mac, fw, fwsize);
++	if (status != HALMAC_RET_SUCCESS) {
++		RTW_ERR("%s: download firmware FAIL! status=0x%02x\n",
++			__FUNCTION__, status);
++		_debug_dlfw_fail(d);
++		err = -1;
++		goto resume_tx;
++	}
++
++	/* 5.1. (Driver) Reset driver variables if needed */
++	hal->LastHMEBoxNum = 0;
++
++	/* 5.2. (Driver) Get FW version */
++	status = api->halmac_get_fw_version(mac, &fw_vesion);
++	if (status == HALMAC_RET_SUCCESS) {
++		hal->firmware_version = fw_vesion.version;
++		hal->firmware_sub_version = fw_vesion.sub_version;
++		hal->firmware_size = fwsize;
++	}
++
++resume_tx:
++	/* 6. Driver resume TX if needed */
++	/* ToDo */
++
++	if (err)
++		goto exit;
++
++	if (re_dl) {
++		enum halmac_trx_mode mode;
++
++		/* 7. Change reserved page size */
++		err = _cfg_drv_rsvd_pg_num(d);
++		if (err)
++			return -1;
++
++		/* 8. Init TRX Configuration */
++		mode = _choose_trx_mode(d);
++		status = api->halmac_init_trx_cfg(mac, mode);
++		if (HALMAC_RET_SUCCESS != status)
++			return -1;
++		_init_trx_cfg_drv(d);
++
++		/* 9. Config RX Aggregation */
++		err = rtw_halmac_rx_agg_switch(d, _TRUE);
++		if (err)
++			return -1;
++
++		/* 10. Send General Info */
++		err = _send_general_info(d);
++		if (err)
++			return -1;
++	}
++
++exit:
++	return err;
++}
++
++static int init_mac_flow(struct dvobj_priv *d)
++{
++	PADAPTER p;
++	struct hal_com_data *hal;
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_drv_rsvd_pg_num rsvd_page_number;
++	union halmac_wlan_addr hwa;
++	enum halmac_trx_mode trx_mode;
++	enum halmac_ret_status status;
++	u8 drv_rsvd_num;
++	u8 nettype;
++	int err, err_ret = -1;
++
++
++	p = dvobj_get_primary_adapter(d);
++	hal = GET_HAL_DATA(p);
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++#ifdef CONFIG_SUPPORT_TRX_SHARED
++	status = api->halmac_cfg_rxff_expand_mode(halmac,
++						  _rtw_get_trx_share_mode(p));
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++#endif
++
++#ifdef DBG_LA_MODE
++	if (dvobj_to_regsty(d)->la_mode_en) {
++		status = api->halmac_cfg_la_mode(halmac, HALMAC_LA_MODE_PARTIAL);
++		if (status != HALMAC_RET_SUCCESS) {
++			RTW_ERR("%s: Fail to enable LA mode!\n", __FUNCTION__);
++			goto out;
++		}
++		RTW_PRINT("%s: Enable LA mode OK.\n", __FUNCTION__);
++	}
++#endif
++
++	err = _cfg_drv_rsvd_pg_num(d);
++	if (err)
++		goto out;
++
++#ifdef CONFIG_USB_HCI
++	status = api->halmac_set_bulkout_num(halmac, d->RtNumOutPipes);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++#endif /* CONFIG_USB_HCI */
++
++	trx_mode = _choose_trx_mode(d);
++	status = api->halmac_init_mac_cfg(halmac, trx_mode);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++	/* Driver insert flow: Sync driver setting with register */
++	/* Sync driver RCR cache with register setting */
++	rtw_hal_get_hwreg(dvobj_get_primary_adapter(d), HW_VAR_RCR, NULL);
++
++#ifdef CONFIG_RTS_FULL_BW
++	err = rtw_halmac_set_rts_full_bw(d, _TRUE);
++	if (err)
++		RTW_WARN("%s: Fail to set RTS FULL BW mode\n", __FUNCTION__);
++#else
++	err = rtw_halmac_set_rts_full_bw(d, _FALSE);
++	if (err)
++		RTW_WARN("%s: Fail to disable RTS FULL BW mode\n", __FUNCTION__);
++#endif /* CONFIG_RTS_FULL_BW */
++
++	_init_trx_cfg_drv(d);
++	/* Driver inser flow end */
++
++	err = rtw_halmac_rx_agg_switch(d, _TRUE);
++	if (err)
++		goto out;
++
++	nettype = dvobj_to_regsty(d)->wireless_mode;
++	if (is_supported_vht(nettype) == _TRUE)
++		status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_AC);
++	else if (is_supported_ht(nettype) == _TRUE)
++		status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_N);
++	else if (IsSupportedTxOFDM(nettype) == _TRUE)
++		status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_G);
++	else
++		status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_B);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++	err_ret = 0;
++out:
++	return err_ret;
++}
++
++static int _drv_enable_trx(struct dvobj_priv *d)
++{
++	struct _ADAPTER *adapter;
++	u32 status;
++
++
++	adapter = dvobj_get_primary_adapter(d);
++	if (adapter->bup == _FALSE) {
++#ifdef CONFIG_NEW_NETDEV_HDL
++		status = rtw_mi_start_drv_threads(adapter);
++#else
++		status = rtw_start_drv_threads(adapter);
++#endif
++		if (status == _FAIL) {
++			RTW_ERR("%s: Start threads Failed!\n", __FUNCTION__);
++			return -1;
++		}
++	}
++
++	rtw_intf_start(adapter);
++
++	return 0;
++}
++
++/*
++ * Notices:
++ *	Make sure following information
++ *	1. GET_HAL_RFPATH
++ *	2. GET_HAL_DATA(dvobj_get_primary_adapter(d))->rfe_type
++ *	3. GET_HAL_DATA(dvobj_get_primary_adapter(d))->PackageType
++ *	4. dvobj_get_primary_adapter(d)->registrypriv.mp_mode
++ *	are all ready before calling this function.
++ */
++static int _halmac_init_hal(struct dvobj_priv *d, u8 *fw, u32 fwsize)
++{
++	PADAPTER adapter;
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u32 ok;
++	u8 fw_ok = _FALSE;
++	int err, err_ret = -1;
++
++
++	adapter = dvobj_get_primary_adapter(d);
++	halmac = dvobj_to_halmac(d);
++	if (!halmac)
++		goto out;
++	api = HALMAC_GET_API(halmac);
++
++	/* StatePowerOff */
++
++	/* SKIP: halmac_init_adapter (Already done before) */
++
++	/* halmac_pre_Init_system_cfg */
++	/* halmac_mac_power_switch(on) */
++	/* halmac_Init_system_cfg */
++	ok = rtw_hal_power_on(adapter);
++	if (_FAIL == ok)
++		goto out;
++
++	/* StatePowerOn */
++
++	/* DownloadFW */
++	if (fw && fwsize) {
++		err = download_fw(d, fw, fwsize, 0);
++		if (err)
++			goto out;
++		fw_ok = _TRUE;
++	}
++
++	/* InitMACFlow */
++	err = init_mac_flow(d);
++	if (err)
++		goto out;
++
++	/* Driver insert flow: Enable TR/RX */
++	err = _drv_enable_trx(d);
++	if (err)
++		goto out;
++
++	/* halmac_send_general_info */
++	if (_TRUE == fw_ok) {
++		err = _send_general_info(d);
++		if (err)
++			goto out;
++	}
++
++	/* Init Phy parameter-MAC */
++	ok = rtw_hal_init_mac_register(adapter);
++	if (_FALSE == ok)
++		goto out;
++
++	/* StateMacInitialized */
++
++	/* halmac_cfg_drv_info */
++	err = rtw_halmac_config_rx_info(d, HALMAC_DRV_INFO_PHY_STATUS);
++	if (err)
++		goto out;
++
++	/* halmac_set_hw_value(HALMAC_HW_EN_BB_RF) */
++	/* Init BB, RF */
++	ok = rtw_hal_init_phy(adapter);
++	if (_FALSE == ok)
++		goto out;
++
++	status = api->halmac_init_interface_cfg(halmac);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++	/* SKIP: halmac_verify_platform_api */
++	/* SKIP: halmac_h2c_lb */
++
++	/* StateRxIdle */
++
++	err_ret = 0;
++out:
++	return err_ret;
++}
++
++int rtw_halmac_init_hal(struct dvobj_priv *d)
++{
++	return _halmac_init_hal(d, NULL, 0);
++}
++
++/*
++ * Notices:
++ *	Make sure following information
++ *	1. GET_HAL_RFPATH
++ *	2. GET_HAL_DATA(dvobj_get_primary_adapter(d))->rfe_type
++ *	3. GET_HAL_DATA(dvobj_get_primary_adapter(d))->PackageType
++ *	4. dvobj_get_primary_adapter(d)->registrypriv.mp_mode
++ *	are all ready before calling this function.
++ */
++int rtw_halmac_init_hal_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize)
++{
++	return _halmac_init_hal(d, fw, fwsize);
++}
++
++/*
++ * Notices:
++ *	Make sure following information
++ *	1. GET_HAL_RFPATH
++ *	2. GET_HAL_DATA(dvobj_get_primary_adapter(d))->rfe_type
++ *	3. GET_HAL_DATA(dvobj_get_primary_adapter(d))->PackageType
++ *	4. dvobj_get_primary_adapter(d)->registrypriv.mp_mode
++ *	are all ready before calling this function.
++ */
++int rtw_halmac_init_hal_fw_file(struct dvobj_priv *d, u8 *fwpath)
++{
++	u8 *fw = NULL;
++	u32 fwmaxsize = 0, size = 0;
++	int err = 0;
++
++
++	err = rtw_halmac_get_fw_max_size(d, &fwmaxsize);
++	if (err) {
++		RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err);
++		return -1;
++	}
++
++	fw = rtw_zmalloc(fwmaxsize);
++	if (!fw)
++		return -1;
++
++	size = rtw_retrieve_from_file(fwpath, fw, fwmaxsize);
++	if (!size) {
++		err = -1;
++		goto exit;
++	}
++
++	err = _halmac_init_hal(d, fw, size);
++
++exit:
++	rtw_mfree(fw, fwmaxsize);
++	/*fw = NULL;*/
++
++	return err;
++}
++
++int rtw_halmac_deinit_hal(struct dvobj_priv *d)
++{
++	PADAPTER adapter;
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	int err = -1;
++
++
++	adapter = dvobj_get_primary_adapter(d);
++	halmac = dvobj_to_halmac(d);
++	if (!halmac)
++		goto out;
++	api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_deinit_interface_cfg(halmac);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++	rtw_hal_power_off(adapter);
++
++	err = 0;
++out:
++	return err;
++}
++
++int rtw_halmac_self_verify(struct dvobj_priv *d)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	int err = -1;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_verify_platform_api(mac);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++	status = api->halmac_h2c_lb(mac);
++	if (status != HALMAC_RET_SUCCESS)
++		goto out;
++
++	err = 0;
++out:
++	return err;
++}
++
++static u8 rtw_halmac_txfifo_is_empty(struct dvobj_priv *d)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u32 chk_num = 10;
++	u8 rst = _FALSE;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_txfifo_is_empty(mac, chk_num);
++	if (status == HALMAC_RET_SUCCESS)
++		rst = _TRUE;
++
++	return rst;
++}
++
++/**
++ * rtw_halmac_txfifo_wait_empty() - Wait TX FIFO to be emtpy
++ * @d:		struct dvobj_priv*
++ * @timeout:	time limit of wait, unit is ms
++ *		0 for no limit
++ *
++ * Wait TX FIFO to be emtpy.
++ *
++ * Return 0 for TX FIFO is empty, otherwise not empty.
++ */
++int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout)
++{
++	struct _ADAPTER *a;
++	u8 empty = _FALSE;
++	u32 cnt = 0;
++	systime start_time = 0;
++	u32 pass_time; /* ms */
++
++
++	a = dvobj_get_primary_adapter(d);
++	start_time = rtw_get_current_time();
++
++	do {
++		cnt++;
++		empty = rtw_halmac_txfifo_is_empty(d);
++		if (empty == _TRUE)
++			break;
++
++		if (timeout) {
++			pass_time = rtw_get_passing_time_ms(start_time);
++			if (pass_time > timeout)
++				break;
++		}
++		if (RTW_CANNOT_IO(a)) {
++			RTW_WARN("%s: Interrupted by I/O forbiden!\n", __FUNCTION__);
++			break;
++		}
++
++		rtw_msleep_os(2);
++	} while (1);
++
++	if (empty == _FALSE) {
++#ifdef CONFIG_RTW_DEBUG
++		u16 dbg_reg[] = {0x210, 0x230, 0x234, 0x238, 0x23C, 0x240,
++				 0x418, 0x10FC, 0x10F8, 0x11F4, 0x11F8};
++		u8 i;
++		u32 val;
++
++		if (!RTW_CANNOT_IO(a)) {
++			for (i = 0; i < ARRAY_SIZE(dbg_reg); i++) {
++				val = rtw_read32(a, dbg_reg[i]);
++				RTW_ERR("REG_%X:0x%08x\n", dbg_reg[i], val);
++			}
++		}
++#endif /* CONFIG_RTW_DEBUG */
++
++		RTW_ERR("%s: Fail to wait txfifo empty!(cnt=%d)\n",
++			__FUNCTION__, cnt);
++		return -1;
++	}
++
++	return 0;
++}
++
++static enum halmac_dlfw_mem _fw_mem_drv2halmac(enum fw_mem mem, u8 tx_stop)
++{
++	enum halmac_dlfw_mem mem_halmac = HALMAC_DLFW_MEM_UNDEFINE;
++
++
++	switch (mem) {
++	case FW_EMEM:
++		if (tx_stop == _FALSE)
++			mem_halmac = HALMAC_DLFW_MEM_EMEM_RSVD_PG;
++		else
++			mem_halmac = HALMAC_DLFW_MEM_EMEM;
++		break;
++
++	case FW_IMEM:
++	case FW_DMEM:
++		mem_halmac = HALMAC_DLFW_MEM_UNDEFINE;
++		break;
++	}
++
++	return mem_halmac;
++}
++
++int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	enum halmac_dlfw_mem dlfw_mem;
++	u8 tx_stop = _FALSE;
++	u32 chk_timeout = 2000; /* unit: ms */
++	int err = 0;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	if ((!fw) || (!fwsize))
++		return -1;
++
++#ifndef RTW_HALMAC_DLFW_MEM_NO_STOP_TX
++	/* 1. Driver Stop Tx */
++	/* ToDo */
++
++	/* 2. Driver Check Tx FIFO is empty */
++	err = rtw_halmac_txfifo_wait_empty(d, chk_timeout);
++	if (err)
++		tx_stop = _FALSE;
++	else
++		tx_stop = _TRUE;
++#endif /* !RTW_HALMAC_DLFW_MEM_NO_STOP_TX */
++
++	/* 3. Download Firmware MEM */
++	dlfw_mem = _fw_mem_drv2halmac(mem, tx_stop);
++	if (dlfw_mem == HALMAC_DLFW_MEM_UNDEFINE) {
++		err = -1;
++		goto resume_tx;
++	}
++	status = api->halmac_free_download_firmware(mac, dlfw_mem, fw, fwsize);
++	if (status != HALMAC_RET_SUCCESS) {
++		RTW_ERR("%s: halmac_free_download_firmware fail(err=0x%x)\n",
++			__FUNCTION__, status);
++		err = -1;
++		goto resume_tx;
++	}
++
++resume_tx:
++#ifndef RTW_HALMAC_DLFW_MEM_NO_STOP_TX
++	/* 4. Driver resume TX if needed */
++	/* ToDo */
++#endif /* !RTW_HALMAC_DLFW_MEM_NO_STOP_TX */
++
++	return err;
++}
++
++int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem)
++{
++	u8 *fw = NULL;
++	u32 fwmaxsize = 0, size = 0;
++	int err = 0;
++
++
++	err = rtw_halmac_get_fw_max_size(d, &fwmaxsize);
++	if (err) {
++		RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err);
++		return -1;
++	}
++
++	fw = rtw_zmalloc(fwmaxsize);
++	if (!fw)
++		return -1;
++
++	size = rtw_retrieve_from_file(fwpath, fw, fwmaxsize);
++	if (size)
++		err = rtw_halmac_dlfw_mem(d, fw, size, mem);
++	else
++		err = -1;
++
++	rtw_mfree(fw, fwmaxsize);
++	/*fw = NULL;*/
++
++	return err;
++}
++
++/*
++ * Return:
++ *	0	Success
++ *	-22	Invalid arguemnt
++ */
++int rtw_halmac_dlfw(struct dvobj_priv *d, u8 *fw, u32 fwsize)
++{
++	PADAPTER adapter;
++	enum halmac_ret_status status;
++	u32 ok;
++	int err, err_ret = -1;
++
++
++	if (!fw || !fwsize)
++		return -22;
++
++	adapter = dvobj_get_primary_adapter(d);
++
++	/* re-download firmware */
++	if (rtw_is_hw_init_completed(adapter))
++		return download_fw(d, fw, fwsize, 1);
++
++	/* Download firmware before hal init */
++	/* Power on, download firmware and init mac */
++	ok = rtw_hal_power_on(adapter);
++	if (_FAIL == ok)
++		goto out;
++
++	err = download_fw(d, fw, fwsize, 0);
++	if (err) {
++		err_ret = err;
++		goto out;
++	}
++
++	err = init_mac_flow(d);
++	if (err)
++		goto out;
++
++	err = _send_general_info(d);
++	if (err)
++		goto out;
++
++	err_ret = 0;
++
++out:
++	return err_ret;
++}
++
++int rtw_halmac_dlfw_from_file(struct dvobj_priv *d, u8 *fwpath)
++{
++	u8 *fw = NULL;
++	u32 fwmaxsize = 0, size = 0;
++	int err = 0;
++
++
++	err = rtw_halmac_get_fw_max_size(d, &fwmaxsize);
++	if (err) {
++		RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err);
++		return -1;
++	}
++
++	fw = rtw_zmalloc(fwmaxsize);
++	if (!fw)
++		return -1;
++
++	size = rtw_retrieve_from_file(fwpath, fw, fwmaxsize);
++	if (size)
++		err = rtw_halmac_dlfw(d, fw, size);
++	else
++		err = -1;
++
++	rtw_mfree(fw, fwmaxsize);
++	/*fw = NULL;*/
++
++	return err;
++}
++
++/*
++ * Description:
++ *	Power on/off BB/RF domain.
++ *
++ * Parameters:
++ *	enable	_TRUE/_FALSE for power on/off
++ *
++ * Return:
++ *	0	Success
++ *	others	Fail
++ */
++int rtw_halmac_phy_power_switch(struct dvobj_priv *d, u8 enable)
++{
++	PADAPTER adapter;
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u8 on;
++
++
++	adapter = dvobj_get_primary_adapter(d);
++	halmac = dvobj_to_halmac(d);
++	if (!halmac)
++		return -1;
++	api = HALMAC_GET_API(halmac);
++	on = (enable == _TRUE) ? 1 : 0;
++
++	status = api->halmac_set_hw_value(halmac, HALMAC_HW_EN_BB_RF, &on);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	return 0;
++}
++
++static u8 _is_fw_read_cmd_down(PADAPTER adapter, u8 msgbox_num)
++{
++	u8 read_down = _FALSE;
++	int retry_cnts = 100;
++	u8 valid;
++
++	do {
++		valid = rtw_read8(adapter, REG_HMETFR) & BIT(msgbox_num);
++		if (0 == valid)
++			read_down = _TRUE;
++		else
++			rtw_msleep_os(1);
++	} while ((!read_down) && (retry_cnts--));
++
++	if (_FALSE == read_down)
++		RTW_WARN("%s, reg_1cc(%x), msg_box(%d)...\n", __func__, rtw_read8(adapter, REG_HMETFR), msgbox_num);
++
++	return read_down;
++}
++
++/**
++ * rtw_halmac_send_h2c() - Send H2C to firmware
++ * @d:		struct dvobj_priv*
++ * @h2c:	H2C data buffer, suppose to be 8 bytes
++ *
++ * Send H2C to firmware by message box register(0x1D0~0x1D3 & 0x1F0~0x1F3).
++ *
++ * Assume firmware be ready to accept H2C here, please check
++ * (hal->bFWReady == _TRUE) before call this function or make sure firmware is
++ * ready.
++ *
++ * Return: 0 if process OK, otherwise fail to send this H2C.
++ */
++int rtw_halmac_send_h2c(struct dvobj_priv *d, u8 *h2c)
++{
++	PADAPTER adapter = dvobj_get_primary_adapter(d);
++	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
++	u8 h2c_box_num = 0;
++	u32 msgbox_addr = 0;
++	u32 msgbox_ex_addr = 0;
++	u32 h2c_cmd = 0;
++	u32 h2c_cmd_ex = 0;
++	int err = -1;
++
++
++	if (!h2c) {
++		RTW_WARN("%s: pbuf is NULL\n", __FUNCTION__);
++		return err;
++	}
++
++	if (rtw_is_surprise_removed(adapter)) {
++		RTW_WARN("%s: surprise removed\n", __FUNCTION__);
++		return err;
++	}
++
++	_enter_critical_mutex(&d->h2c_fwcmd_mutex, NULL);
++
++	/* pay attention to if race condition happened in H2C cmd setting */
++	h2c_box_num = hal->LastHMEBoxNum;
++
++	if (!_is_fw_read_cmd_down(adapter, h2c_box_num)) {
++		RTW_WARN(" fw read cmd failed...\n");
++#ifdef DBG_CONFIG_ERROR_DETECT
++		hal->srestpriv.self_dect_fw = _TRUE;
++		hal->srestpriv.self_dect_fw_cnt++;
++#endif /* DBG_CONFIG_ERROR_DETECT */
++		goto exit;
++	}
++
++	/* Write Ext command (byte 4~7) */
++	msgbox_ex_addr = REG_HMEBOX_E0 + (h2c_box_num * EX_MESSAGE_BOX_SIZE);
++	_rtw_memcpy((u8 *)(&h2c_cmd_ex), h2c + 4, EX_MESSAGE_BOX_SIZE);
++	h2c_cmd_ex = le32_to_cpu(h2c_cmd_ex);
++	rtw_write32(adapter, msgbox_ex_addr, h2c_cmd_ex);
++
++	/* Write command (byte 0~3) */
++	msgbox_addr = REG_HMEBOX0 + (h2c_box_num * MESSAGE_BOX_SIZE);
++	_rtw_memcpy((u8 *)(&h2c_cmd), h2c, 4);
++	h2c_cmd = le32_to_cpu(h2c_cmd);
++	rtw_write32(adapter, msgbox_addr, h2c_cmd);
++
++	/* update last msg box number */
++	hal->LastHMEBoxNum = (h2c_box_num + 1) % MAX_H2C_BOX_NUMS;
++	err = 0;
++
++#ifdef DBG_H2C_CONTENT
++	RTW_INFO_DUMP("[H2C] - ", h2c, RTW_HALMAC_H2C_MAX_SIZE);
++#endif
++exit:
++	_exit_critical_mutex(&d->h2c_fwcmd_mutex, NULL);
++	return err;
++}
++
++/**
++ * rtw_halmac_c2h_handle() - Handle C2H for HALMAC
++ * @d:		struct dvobj_priv*
++ * @c2h:	Full C2H packet, including RX description and payload
++ * @size:	Size(byte) of c2h
++ *
++ * Send C2H packet to HALMAC to process C2H packets, and the expected C2H ID is
++ * 0xFF. This function won't have any I/O, so caller doesn't have to call it in
++ * I/O safe place(ex. command thread).
++ *
++ * Please sure doesn't call this function in the same thread as someone is
++ * waiting HALMAC C2H ack, otherwise there is a deadlock happen.
++ *
++ * Return: 0 if process OK, otherwise no action for this C2H.
++ */
++int rtw_halmac_c2h_handle(struct dvobj_priv *d, u8 *c2h, u32 size)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++#ifdef RTW_HALMAC_FILTER_DRV_C2H
++	u32 desc_size = 0;
++	u8 *c2h_data;
++	u8 sub;
++#endif /* RTW_HALMAC_FILTER_DRV_C2H */
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++#ifdef RTW_HALMAC_FILTER_DRV_C2H
++	status = api->halmac_get_hw_value(mac, HALMAC_HW_RX_DESC_SIZE,
++					  &desc_size);
++	if (status != HALMAC_RET_SUCCESS) {
++		RTW_ERR("%s: fail to get rx desc size!\n", __FUNCTION__);
++		goto skip_filter;
++	}
++
++	c2h_data = c2h + desc_size;
++	sub = C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_data);
++	switch (sub) {
++	case C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG:
++	case C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG:
++	case C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG:
++	case C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG:
++	case C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG:
++	case C2H_SUB_CMD_ID_FTMC2H_RPT:
++	case C2H_SUB_CMD_ID_DRVFTMC2H_RPT:
++	case C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG:
++	case C2H_SUB_CMD_ID_CCX_RPT:
++	case C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT:
++	case C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT:
++	case C2H_SUB_CMD_ID_C2H_PKT_SCC_CSA_RPT:
++	case C2H_SUB_CMD_ID_C2H_PKT_FW_STATUS_NOTIFY:
++	case C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END:
++	case C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL:
++	case C2H_SUB_CMD_ID_FW_FWCTRL_RPT:
++	case C2H_SUB_CMD_ID_SCAN_CH_NOTIFY:
++	case C2H_SUB_CMD_ID_FW_TBTT_RPT:
++	case C2H_SUB_CMD_ID_BCN_OFFLOAD:
++	case C2H_SUB_CMD_ID_FW_DBG_MSG:
++		RTW_PRINT("%s: unhandled C2H, id=0xFF subid=0x%x len=%u\n",
++			  __FUNCTION__, sub, C2H_HDR_GET_LEN(c2h_data));
++		RTW_PRINT_DUMP("C2H: ", c2h_data, size - desc_size);
++		return 0;
++	}
++
++skip_filter:
++#endif /* RTW_HALMAC_FILTER_DRV_C2H */
++
++	status = api->halmac_get_c2h_info(mac, c2h, size);
++	if (HALMAC_RET_SUCCESS != status)
++		return -1;
++
++	return 0;
++}
++
++int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u32 val;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_get_efuse_available_size(mac, &val);
++	if (HALMAC_RET_SUCCESS != status)
++		return -1;
++
++	*size = val;
++	return 0;
++}
++
++int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *d, u32 *size)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u32 val;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_get_efuse_size(mac, &val);
++	if (HALMAC_RET_SUCCESS != status)
++		return -1;
++
++	*size = val;
++	return 0;
++}
++
++int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	enum halmac_feature_id id;
++	int ret;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++	id = HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE;
++
++	ret = init_halmac_event(d, id, map, size);
++	if (ret)
++		return -1;
++
++	status = api->halmac_dump_efuse_map(mac, HALMAC_EFUSE_R_DRV);
++	if (HALMAC_RET_SUCCESS != status) {
++		free_halmac_event(d, id);
++		return -1;
++	}
++
++	ret = wait_halmac_event(d, id);
++	if (ret)
++		return -1;
++
++	return 0;
++}
++
++int rtw_halmac_read_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u8 v;
++	u32 i;
++	u8 *efuse = NULL;
++	u32 size = 0;
++	int err = 0;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	if (api->halmac_read_efuse) {
++		for (i = 0; i < cnt; i++) {
++			status = api->halmac_read_efuse(mac, offset + i, &v);
++			if (HALMAC_RET_SUCCESS != status)
++				return -1;
++			data[i] = v;
++		}
++	} else {
++		err = rtw_halmac_get_physical_efuse_size(d, &size);
++		if (err)
++			return -1;
++
++		efuse = rtw_zmalloc(size);
++		if (!efuse)
++			return -1;
++
++		err = rtw_halmac_read_physical_efuse_map(d, efuse, size);
++		if (err)
++			err = -1;
++		else
++			_rtw_memcpy(data, efuse + offset, cnt);
++
++		rtw_mfree(efuse, size);
++	}
++
++	return err;
++}
++
++int rtw_halmac_write_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u32 i;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	if (api->halmac_write_efuse == NULL)
++		return -1;
++
++	for (i = 0; i < cnt; i++) {
++		status = api->halmac_write_efuse(mac, offset + i, data[i]);
++		if (HALMAC_RET_SUCCESS != status)
++			return -1;
++	}
++
++	return 0;
++}
++
++int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *d, u32 *size)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u32 val;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_get_logical_efuse_size(mac, &val);
++	if (HALMAC_RET_SUCCESS != status)
++		return -1;
++
++	*size = val;
++	return 0;
++}
++
++int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, u8 *maskmap, u32 masksize)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	enum halmac_feature_id id;
++	int ret;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++	id = HALMAC_FEATURE_DUMP_LOGICAL_EFUSE;
++
++	ret = init_halmac_event(d, id, map, size);
++	if (ret)
++		return -1;
++
++	status = api->halmac_dump_logical_efuse_map(mac, HALMAC_EFUSE_R_DRV);
++	if (HALMAC_RET_SUCCESS != status) {
++		free_halmac_event(d, id);
++		return -1;
++	}
++
++	ret = wait_halmac_event(d, id);
++	if (ret)
++		return -1;
++
++	if (maskmap && masksize) {
++		struct halmac_pg_efuse_info pginfo;
++
++		pginfo.efuse_map = map;
++		pginfo.efuse_map_size = size;
++		pginfo.efuse_mask = maskmap;
++		pginfo.efuse_mask_size = masksize;
++
++		status = api->halmac_mask_logical_efuse(mac, &pginfo);
++		if (status != HALMAC_RET_SUCCESS)
++			RTW_WARN("%s: mask logical efuse FAIL!\n", __FUNCTION__);
++	}
++
++	return 0;
++}
++
++int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, u8 *maskmap, u32 masksize)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	struct halmac_pg_efuse_info pginfo;
++	enum halmac_ret_status status;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	pginfo.efuse_map = map;
++	pginfo.efuse_map_size = size;
++	pginfo.efuse_mask = maskmap;
++	pginfo.efuse_mask_size = masksize;
++
++	status = api->halmac_pg_efuse_by_map(mac, &pginfo, HALMAC_EFUSE_R_AUTO);
++	if (HALMAC_RET_SUCCESS != status)
++		return -1;
++
++	return 0;
++}
++
++int rtw_halmac_read_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u8 v;
++	u32 i;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	for (i = 0; i < cnt; i++) {
++		status = api->halmac_read_logical_efuse(mac, offset + i, &v);
++		if (HALMAC_RET_SUCCESS != status)
++			return -1;
++		data[i] = v;
++	}
++
++	return 0;
++}
++
++int rtw_halmac_write_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u32 i;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	for (i = 0; i < cnt; i++) {
++		status = api->halmac_write_logical_efuse(mac, offset + i, data[i]);
++		if (HALMAC_RET_SUCCESS != status)
++			return -1;
++	}
++
++	return 0;
++}
++
++int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u32 i;
++	u8 bank = 1;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	for (i = 0; i < cnt; i++) {
++		status = api->halmac_write_efuse_bt(mac, offset + i, data[i], bank);
++		if (HALMAC_RET_SUCCESS != status) {
++			printk("%s: halmac_write_efuse_bt status = %d\n", __FUNCTION__, status);
++			return -1;
++		}
++	}
++	printk("%s: halmac_write_efuse_bt status = HALMAC_RET_SUCCESS %d\n", __FUNCTION__, status);
++	return 0;
++}
++
++
++int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	int bank = 1;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_dump_efuse_map_bt(mac, bank, size, map);
++	if (HALMAC_RET_SUCCESS != status) {
++		printk("%s: halmac_dump_efuse_map_bt fail!\n", __FUNCTION__);
++		return -1;
++	}
++
++	printk("%s: OK!\n", __FUNCTION__);
++
++	return 0;
++}
++
++static enum hal_fifo_sel _fifo_sel_drv2halmac(u8 fifo_sel)
++{
++	switch (fifo_sel) {
++	case 0:
++		return HAL_FIFO_SEL_TX;
++	case 1:
++		return HAL_FIFO_SEL_RX;
++	case 2:
++		return HAL_FIFO_SEL_RSVD_PAGE;
++	case 3:
++		return HAL_FIFO_SEL_REPORT;
++	case 4:
++		return HAL_FIFO_SEL_LLT;
++	case 5:
++		return HAL_FIFO_SEL_RXBUF_FW;
++	}
++
++	return HAL_FIFO_SEL_RSVD_PAGE;
++}
++
++/*#define CONFIG_HALMAC_FIFO_DUMP*/
++int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum hal_fifo_sel halmac_fifo_sel;
++	enum halmac_ret_status status;
++	u8 *pfifo_map = NULL;
++	u32 fifo_size = 0;
++	s8 ret = 0;/* 0:success, -1:error */
++	u8 mem_created = _FALSE;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	if ((size != 0) && (buffer == NULL))
++		return -1;
++
++	halmac_fifo_sel = _fifo_sel_drv2halmac(fifo_sel);
++
++	if ((size) && (buffer)) {
++		pfifo_map = buffer;
++		fifo_size = size;
++	} else {
++		fifo_size = api->halmac_get_fifo_size(mac, halmac_fifo_sel);
++
++		if (fifo_size)
++			pfifo_map = rtw_zvmalloc(fifo_size);
++		if (pfifo_map == NULL)
++			return -1;
++		mem_created = _TRUE;
++	}
++
++	status = api->halmac_dump_fifo(mac, halmac_fifo_sel, addr, fifo_size, pfifo_map);
++	if (HALMAC_RET_SUCCESS != status) {
++		ret = -1;
++		goto _exit;
++	}
++
++#ifdef CONFIG_HALMAC_FIFO_DUMP
++	{
++		static const char * const fifo_sel_str[] = {
++			"TX", "RX", "RSVD_PAGE", "REPORT", "LLT", "RXBUF_FW"
++		};
++
++		RTW_INFO("%s FIFO DUMP [start_addr:0x%04x , size:%d]\n", fifo_sel_str[halmac_fifo_sel], addr, fifo_size);
++		RTW_INFO_DUMP("\n", pfifo_map, fifo_size);
++		RTW_INFO(" ==================================================\n");
++	}
++#endif /* CONFIG_HALMAC_FIFO_DUMP */
++
++_exit:
++	if ((mem_created == _TRUE) && pfifo_map)
++		rtw_vmfree(pfifo_map, fifo_size);
++
++	return ret;
++}
++
++/*
++ * rtw_halmac_rx_agg_switch() - Switch RX aggregation function and setting
++ * @d		struct dvobj_priv *
++ * @enable	_FALSE/_TRUE for disable/enable RX aggregation function
++ *
++ * This function could help to on/off bus RX aggregation function, and is only
++ * useful for SDIO and USB interface. Although only "enable" flag is brough in,
++ * some setting would be taken from other places, and they are from:
++ * [DMA aggregation]
++ *	struct hal_com_data.rxagg_dma_size
++ *	struct hal_com_data.rxagg_dma_timeout
++ * [USB aggregation] (only use for USB interface)
++ *	struct hal_com_data.rxagg_usb_size
++ *	struct hal_com_data.rxagg_usb_timeout
++ * If above values of size and timeout are both 0 means driver would not
++ * control the threshold setting and leave it to HALMAC handle.
++ *
++ * From HALMAC V1_04_04, driver force the size threshold be hard limit, and the
++ * rx size can not exceed the setting.
++ *
++ * Return 0 for success, otherwise fail.
++ */
++int rtw_halmac_rx_agg_switch(struct dvobj_priv *d, u8 enable)
++{
++	struct _ADAPTER *adapter;
++	struct hal_com_data *hal;
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	struct halmac_rxagg_cfg rxaggcfg;
++	enum halmac_ret_status status;
++
++
++	adapter = dvobj_get_primary_adapter(d);
++	hal = GET_HAL_DATA(adapter);
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++	_rtw_memset((void *)&rxaggcfg, 0, sizeof(rxaggcfg));
++	rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE;
++	/*
++	 * Always enable size limit to avoid rx size exceed
++	 * driver defined size.
++	 */
++	rxaggcfg.threshold.size_limit_en = 1;
++
++#ifdef RTW_RX_AGGREGATION
++	if (_TRUE == enable) {
++#ifdef CONFIG_SDIO_HCI
++		rxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA;
++		rxaggcfg.threshold.drv_define = 0;
++		if (hal->rxagg_dma_size || hal->rxagg_dma_timeout) {
++			rxaggcfg.threshold.drv_define = 1;
++			rxaggcfg.threshold.timeout = hal->rxagg_dma_timeout;
++			rxaggcfg.threshold.size = hal->rxagg_dma_size;
++			RTW_INFO("%s: RX aggregation threshold: "
++				 "timeout=%u size=%u\n",
++				 __FUNCTION__,
++				 hal->rxagg_dma_timeout,
++				 hal->rxagg_dma_size);
++		}
++#elif defined(CONFIG_USB_HCI)
++		switch (hal->rxagg_mode) {
++		case RX_AGG_DISABLE:
++			rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE;
++			break;
++
++		case RX_AGG_DMA:
++			rxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA;
++			if (hal->rxagg_dma_size || hal->rxagg_dma_timeout) {
++				rxaggcfg.threshold.drv_define = 1;
++				rxaggcfg.threshold.timeout = hal->rxagg_dma_timeout;
++				rxaggcfg.threshold.size = hal->rxagg_dma_size;
++			}
++			break;
++
++		case RX_AGG_USB:
++		case RX_AGG_MIX:
++			rxaggcfg.mode = HALMAC_RX_AGG_MODE_USB;
++			if (hal->rxagg_usb_size || hal->rxagg_usb_timeout) {
++				rxaggcfg.threshold.drv_define = 1;
++				rxaggcfg.threshold.timeout = hal->rxagg_usb_timeout;
++				rxaggcfg.threshold.size = hal->rxagg_usb_size;
++			}
++			break;
++		}
++#endif /* CONFIG_USB_HCI */
++	}
++#endif /* RTW_RX_AGGREGATION */
++
++	status = api->halmac_cfg_rx_aggregation(halmac, &rxaggcfg);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	return 0;
++}
++
++int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size)
++{
++	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
++	struct halmac_adapter *halmac = dvobj_to_halmac(dvobj);
++	struct halmac_api *api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_dl_drv_rsvd_page(halmac, pg_offset, pbuf, size);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	return 0;
++}
++
++/*
++ * Description
++ *	Fill following spec info from HALMAC API:
++ *	sec_cam_ent_num
++ *
++ * Return
++ *	0	Success
++ *	others	Fail
++ */
++int rtw_halmac_fill_hal_spec(struct dvobj_priv *dvobj, struct hal_spec_t *spec)
++{
++	enum halmac_ret_status status;
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	u8 cam = 0;	/* Security Cam Entry Number */
++
++
++	halmac = dvobj_to_halmac(dvobj);
++	api = HALMAC_GET_API(halmac);
++
++	/* Prepare data from HALMAC */
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_CAM_ENTRY_NUM, &cam);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	/* Fill data to hal_spec_t */
++	spec->sec_cam_ent_num = cam;
++
++	return 0;
++}
++
++int rtw_halmac_p2pps(struct dvobj_priv *dvobj, struct hal_p2p_ps_para *pp2p_ps_para)
++{
++	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
++	struct halmac_adapter *halmac = dvobj_to_halmac(dvobj);
++	struct halmac_api *api = HALMAC_GET_API(halmac);
++	struct halmac_p2pps halmac_p2p_ps;
++
++	(&halmac_p2p_ps)->offload_en = pp2p_ps_para->offload_en;
++	(&halmac_p2p_ps)->role = pp2p_ps_para->role;
++	(&halmac_p2p_ps)->ctwindow_en = pp2p_ps_para->ctwindow_en;
++	(&halmac_p2p_ps)->noa_en = pp2p_ps_para->noa_en;
++	(&halmac_p2p_ps)->noa_sel = pp2p_ps_para->noa_sel;
++	(&halmac_p2p_ps)->all_sta_sleep = pp2p_ps_para->all_sta_sleep;
++	(&halmac_p2p_ps)->discovery = pp2p_ps_para->discovery;
++	(&halmac_p2p_ps)->disable_close_rf = pp2p_ps_para->disable_close_rf;
++	(&halmac_p2p_ps)->p2p_port_id = _hw_port_drv2halmac(pp2p_ps_para->p2p_port_id);
++	(&halmac_p2p_ps)->p2p_group = pp2p_ps_para->p2p_group;
++	(&halmac_p2p_ps)->p2p_macid = pp2p_ps_para->p2p_macid;
++	(&halmac_p2p_ps)->ctwindow_length = pp2p_ps_para->ctwindow_length;
++	(&halmac_p2p_ps)->noa_duration_para = pp2p_ps_para->noa_duration_para;
++	(&halmac_p2p_ps)->noa_interval_para = pp2p_ps_para->noa_interval_para;
++	(&halmac_p2p_ps)->noa_start_time_para = pp2p_ps_para->noa_start_time_para;
++	(&halmac_p2p_ps)->noa_count_para = pp2p_ps_para->noa_count_para;
++
++	status = api->halmac_p2pps(halmac, (&halmac_p2p_ps));
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	return 0;
++
++}
++
++/**
++ * rtw_halmac_iqk() - Run IQ Calibration
++ * @d:		struct dvobj_priv*
++ * @clear:	IQK parameters
++ * @segment:	IQK parameters
++ *
++ * Process IQ Calibration(IQK).
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	enum halmac_feature_id id;
++	struct halmac_iqk_para para;
++	int ret;
++	u8 retry = 3;
++	u8 delay = 1; /* ms */
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++	id = HALMAC_FEATURE_IQK;
++
++	ret = init_halmac_event(d, id, NULL, 0);
++	if (ret)
++		return -1;
++
++	para.clear = clear;
++	para.segment_iqk = segment;
++
++	do {
++		status = api->halmac_start_iqk(mac, &para);
++		if (status != HALMAC_RET_BUSY_STATE)
++			break;
++		RTW_WARN("%s: Fail to start IQK, status is BUSY! retry=%d\n", __FUNCTION__, retry);
++		if (!retry)
++			break;
++		retry--;
++		rtw_msleep_os(delay);
++	} while (1);
++	if (status != HALMAC_RET_SUCCESS) {
++		free_halmac_event(d, id);
++		return -1;
++	}
++
++	ret = wait_halmac_event(d, id);
++	if (ret)
++		return -1;
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_dpk() - Run DP Calibration
++ * @d:		struct dvobj_priv*
++ * @buf:	buffer for store return value
++ * @bufsz:	size of buffer
++ *
++ * Process DP Calibration(DPK).
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_dpk(struct dvobj_priv *d, u8 *buf, u32 bufsz)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	enum halmac_feature_id id;
++	int ret;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++	id = HALMAC_FEATURE_DPK;
++
++	ret = init_halmac_event(d, id, buf, bufsz);
++	if (ret)
++		return -1;
++
++	status = api->halmac_start_dpk(mac);
++	if (status != HALMAC_RET_SUCCESS) {
++		free_halmac_event(d, id);
++		RTW_ERR("%s: Fail to start DPK (0x%x)!\n",
++			__FUNCTION__, status);
++		return -1;
++	}
++
++	ret = wait_halmac_event(d, id);
++	if (ret)
++		return -1;
++
++	return 0;
++}
++
++static inline u32 _phy_parameter_val_drv2halmac(u32 val, u8 msk_en, u32 msk)
++{
++	if (!msk_en)
++		return val;
++
++	return (val << bitshift(msk));
++}
++
++static int _phy_parameter_drv2halmac(struct rtw_phy_parameter *para, struct halmac_phy_parameter_info *info)
++{
++	if (!para || !info)
++		return -1;
++
++	_rtw_memset(info, 0, sizeof(*info));
++
++	switch (para->cmd) {
++	case 0:
++		/* MAC register */
++		switch (para->data.mac.size) {
++		case 1:
++			info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W8;
++			break;
++		case 2:
++			info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W16;
++			break;
++		default:
++			info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W32;
++			break;
++		}
++		info->content.MAC_REG_W.value = _phy_parameter_val_drv2halmac(
++							para->data.mac.value,
++							para->data.mac.msk_en,
++							para->data.mac.msk);
++		info->content.MAC_REG_W.msk = para->data.mac.msk;
++		info->content.MAC_REG_W.offset = para->data.mac.offset;
++		info->content.MAC_REG_W.msk_en = para->data.mac.msk_en;
++		break;
++
++	case 1:
++		/* BB register */
++		switch (para->data.bb.size) {
++		case 1:
++			info->cmd_id = HALMAC_PARAMETER_CMD_BB_W8;
++			break;
++		case 2:
++			info->cmd_id = HALMAC_PARAMETER_CMD_BB_W16;
++			break;
++		default:
++			info->cmd_id = HALMAC_PARAMETER_CMD_BB_W32;
++			break;
++		}
++		info->content.BB_REG_W.value = _phy_parameter_val_drv2halmac(
++							para->data.bb.value,
++							para->data.bb.msk_en,
++							para->data.bb.msk);
++		info->content.BB_REG_W.msk = para->data.bb.msk;
++		info->content.BB_REG_W.offset = para->data.bb.offset;
++		info->content.BB_REG_W.msk_en = para->data.bb.msk_en;
++		break;
++
++	case 2:
++		/* RF register */
++		info->cmd_id = HALMAC_PARAMETER_CMD_RF_W;
++		info->content.RF_REG_W.value = _phy_parameter_val_drv2halmac(
++							para->data.rf.value,
++							para->data.rf.msk_en,
++							para->data.rf.msk);
++		info->content.RF_REG_W.msk = para->data.rf.msk;
++		info->content.RF_REG_W.offset = para->data.rf.offset;
++		info->content.RF_REG_W.msk_en = para->data.rf.msk_en;
++		info->content.RF_REG_W.rf_path = para->data.rf.path;
++		break;
++
++	case 3:
++		/* Delay register */
++		if (para->data.delay.unit == 0)
++			info->cmd_id = HALMAC_PARAMETER_CMD_DELAY_US;
++		else
++			info->cmd_id = HALMAC_PARAMETER_CMD_DELAY_MS;
++		info->content.DELAY_TIME.delay_time = para->data.delay.value;
++		break;
++
++	case 0xFF:
++		/* Latest(End) command */
++		info->cmd_id = HALMAC_PARAMETER_CMD_END;
++		break;
++
++	default:
++		return -1;
++	}
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_cfg_phy_para() - Register(Phy parameter) configuration
++ * @d:		struct dvobj_priv*
++ * @para:	phy parameter
++ *
++ * Configure registers by firmware using H2C/C2H mechanism.
++ * The latest command should be para->cmd==0xFF(End command) to finish all
++ * processes.
++ *
++ * Return: 0 for OK, otherwise fail.
++ */
++int rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	enum halmac_feature_id id;
++	struct halmac_phy_parameter_info info;
++	u8 full_fifo;
++	int err, ret;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++	id = HALMAC_FEATURE_CFG_PARA;
++	full_fifo = 1; /* ToDo: How to deciede? */
++	ret = 0;
++
++	err = _phy_parameter_drv2halmac(para, &info);
++	if (err)
++		return -1;
++
++	err = init_halmac_event(d, id, NULL, 0);
++	if (err)
++		return -1;
++
++	status = api->halmac_cfg_parameter(mac, &info, full_fifo);
++	if (info.cmd_id == HALMAC_PARAMETER_CMD_END) {
++		if (status == HALMAC_RET_SUCCESS) {
++			err = wait_halmac_event(d, id);
++			if (err)
++				ret = -1;
++		} else {
++			free_halmac_event(d, id);
++			ret = -1;
++			RTW_ERR("%s: Fail to send END of cfg parameter, status is 0x%x!\n", __FUNCTION__, status);
++		}
++	} else {
++		if (status == HALMAC_RET_PARA_SENDING) {
++			err = wait_halmac_event(d, id);
++			if (err)
++				ret = -1;
++		} else {
++			free_halmac_event(d, id);
++			if (status != HALMAC_RET_SUCCESS) {
++				ret = -1;
++				RTW_ERR("%s: Fail to cfg parameter, status is 0x%x!\n", __FUNCTION__, status);
++			}
++		}
++	}
++
++	return ret;
++}
++
++static enum halmac_wlled_mode _led_mode_drv2halmac(u8 drv_mode)
++{
++	enum halmac_wlled_mode halmac_mode;
++
++
++	switch (drv_mode) {
++	case 1:
++		halmac_mode = HALMAC_WLLED_MODE_TX;
++		break;
++	case 2:
++		halmac_mode = HALMAC_WLLED_MODE_RX;
++		break;
++	case 3:
++		halmac_mode = HALMAC_WLLED_MODE_SW_CTRL;
++		break;
++	case 0:
++	default:
++		halmac_mode = HALMAC_WLLED_MODE_TRX;
++		break;
++	}
++
++	return halmac_mode;
++}
++
++/**
++ * rtw_halmac_led_cfg() - Configure Hardware LED Mode
++ * @d:		struct dvobj_priv*
++ * @enable:	enable or disable LED function
++ *		0: disable
++ *		1: enable
++ * @mode:	WLan LED mode (valid when enable==1)
++ *		0: Blink when TX(transmit packet) and RX(receive packet)
++ *		1: Blink when TX only
++ *		2: Blink when RX only
++ *		3: Software control
++ *
++ * Configure hardware WLan LED mode.
++ * If want to change LED mode after enabled, need to disable LED first and
++ * enable again to set new mode.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_wlled_mode led_mode;
++	enum halmac_ret_status status;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	if (enable) {
++		status = api->halmac_pinmux_set_func(halmac,
++						     HALMAC_GPIO_FUNC_WL_LED);
++		if (status != HALMAC_RET_SUCCESS) {
++			RTW_ERR("%s: pinmux set fail!(0x%x)\n",
++				__FUNCTION__, status);
++			return -1;
++		}
++
++		led_mode = _led_mode_drv2halmac(mode);
++		status = api->halmac_pinmux_wl_led_mode(halmac, led_mode);
++		if (status != HALMAC_RET_SUCCESS) {
++			RTW_ERR("%s: mode set fail!(0x%x)\n",
++				__FUNCTION__, status);
++			return -1;
++		}
++	} else {
++		/* Change LED to software control and turn off */
++		api->halmac_pinmux_wl_led_mode(halmac,
++					       HALMAC_WLLED_MODE_SW_CTRL);
++		api->halmac_pinmux_wl_led_sw_ctrl(halmac, 0);
++
++		status = api->halmac_pinmux_free_func(halmac,
++						      HALMAC_GPIO_FUNC_WL_LED);
++		if (status != HALMAC_RET_SUCCESS) {
++			RTW_ERR("%s: pinmux free fail!(0x%x)\n",
++				__FUNCTION__, status);
++			return -1;
++		}
++	}
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_led_switch() - Turn Hardware LED on/off
++ * @d:		struct dvobj_priv*
++ * @on:		LED light or not
++ *		0: Off
++ *		1: On(Light)
++ *
++ * Turn Hardware WLan LED On/Off.
++ * Before use this function, user should call rtw_halmac_led_ctrl() to switch
++ * mode to "software control(3)" first, otherwise control would fail.
++ * The interval between on and off must be longer than 1 ms, or the LED would
++ * keep light or dark only.
++ * Ex. Turn off LED at first, turn on after 0.5ms and turn off again after
++ * 0.5ms. The LED during this flow will only keep dark, and miss the turn on
++ * operation between two turn off operations.
++ */
++void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	api->halmac_pinmux_wl_led_sw_ctrl(halmac, on);
++}
++
++/**
++ * rtw_halmac_bt_wake_cfg() - Configure BT wake host function
++ * @d:		struct dvobj_priv*
++ * @enable:	enable or disable BT wake host function
++ *		0: disable
++ *		1: enable
++ *
++ * Configure pinmux to allow BT to control BT wake host pin.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_bt_wake_cfg(struct dvobj_priv *d, u8 enable)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	if (enable) {
++		status = api->halmac_pinmux_set_func(halmac,
++						HALMAC_GPIO_FUNC_BT_HOST_WAKE1);
++		if (status != HALMAC_RET_SUCCESS) {
++			RTW_ERR("%s: pinmux set BT_HOST_WAKE1 fail!(0x%x)\n",
++				__FUNCTION__, status);
++			return -1;
++		}
++	} else {
++		status = api->halmac_pinmux_free_func(halmac,
++						HALMAC_GPIO_FUNC_BT_HOST_WAKE1);
++		if (status != HALMAC_RET_SUCCESS) {
++			RTW_ERR("%s: pinmux free BT_HOST_WAKE1 fail!(0x%x)\n",
++				__FUNCTION__, status);
++			return -1;
++		}
++	}
++
++	return 0;
++}
++
++#ifdef CONFIG_PNO_SUPPORT
++/**
++ * _halmac_scanoffload() - Switch channel by firmware during scanning
++ * @d:		struct dvobj_priv*
++ * @enable:	1: enable, 0: disable
++ * @nlo:	1: nlo mode (no c2h event), 0: normal mode
++ * @ssid:	ssid of probe request
++ * @ssid_len:	ssid length
++ *
++ * Switch Channel and Send Porbe Request Offloaded by FW
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++static int _halmac_scanoffload(struct dvobj_priv *d, u32 enable, u8 nlo,
++			       u8 *ssid, u8 ssid_len)
++{
++	struct _ADAPTER *adapter;
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	struct halmac_ch_info ch_info;
++	struct halmac_ch_switch_option cs_option;
++	struct mlme_ext_priv *pmlmeext;
++	enum halmac_feature_id id_update, id_ch_sw;
++	struct halmac_indicator *indicator, *tbl;
++
++	int err = 0;
++	u8 probereq[64];
++	u32 len = 0;
++	int i = 0;
++	struct pno_ssid pnossid;
++	struct rf_ctl_t *rfctl = NULL;
++	struct _RT_CHANNEL_INFO *ch_set;
++
++
++	tbl = d->hmpriv.indicator;
++	adapter = dvobj_get_primary_adapter(d);
++	mac = dvobj_to_halmac(d);
++	if (!mac)
++		return -1;
++	api = HALMAC_GET_API(mac);
++	id_update = HALMAC_FEATURE_UPDATE_PACKET;
++	id_ch_sw = HALMAC_FEATURE_CHANNEL_SWITCH;
++	pmlmeext = &(adapter->mlmeextpriv);
++	rfctl = adapter_to_rfctl(adapter);
++	ch_set = rfctl->channel_set;
++
++	RTW_INFO("%s: %s scanoffload, mode: %s\n",
++		 __FUNCTION__, enable?"Enable":"Disable",
++		 nlo?"PNO/NLO":"Normal");
++
++	if (enable) {
++		_rtw_memset(probereq, 0, sizeof(probereq));
++
++		_rtw_memset(&pnossid, 0, sizeof(pnossid));
++		if (ssid) {
++			if (ssid_len > sizeof(pnossid.SSID)) {
++				RTW_ERR("%s: SSID length(%d) is too long(>%d)!!\n",
++					__FUNCTION__, ssid_len, sizeof(pnossid.SSID));
++				return -1;
++			}
++
++			pnossid.SSID_len = ssid_len;
++			_rtw_memcpy(pnossid.SSID, ssid, ssid_len);
++		}
++
++		rtw_hal_construct_ProbeReq(adapter, probereq, &len, &pnossid);
++
++		if (!nlo) {
++			err = init_halmac_event(d, id_update, NULL, 0);
++			if (err)
++				return -1;
++		}
++
++		status = api->halmac_update_packet(mac, HALMAC_PACKET_PROBE_REQ,
++						   probereq, len);
++		if (status != HALMAC_RET_SUCCESS) {
++			if (!nlo)
++				free_halmac_event(d, id_update);
++			RTW_ERR("%s: halmac_update_packet FAIL(%d)!!\n",
++				__FUNCTION__, status);
++			return -1;
++		}
++
++		if (!nlo) {
++			err = wait_halmac_event(d, id_update);
++			if (err)
++				RTW_ERR("%s: wait update packet FAIL(%d)!!\n",
++					__FUNCTION__, err);
++		}
++
++		api->halmac_clear_ch_info(mac);
++
++		for (i = 0; i < rfctl->max_chan_nums && ch_set[i].ChannelNum != 0; i++) {
++			_rtw_memset(&ch_info, 0, sizeof(ch_info));
++			ch_info.extra_info = 0;
++			ch_info.channel = ch_set[i].ChannelNum;
++			ch_info.bw = HALMAC_BW_20;
++			ch_info.pri_ch_idx = HALMAC_CH_IDX_1;
++			ch_info.action_id = HALMAC_CS_ACTIVE_SCAN;
++			ch_info.timeout = 1;
++			status = api->halmac_add_ch_info(mac, &ch_info);
++			if (status != HALMAC_RET_SUCCESS) {
++				RTW_ERR("%s: add_ch_info FAIL(%d)!!\n",
++					__FUNCTION__, status);
++				return -1;
++			}
++		}
++
++		/* set channel switch option */
++		_rtw_memset(&cs_option, 0, sizeof(cs_option));
++		cs_option.dest_bw = HALMAC_BW_20;
++		cs_option.periodic_option = HALMAC_CS_PERIODIC_2_PHASE;
++		cs_option.dest_pri_ch_idx = HALMAC_CH_IDX_UNDEFINE;
++		cs_option.tsf_low = 0;
++		cs_option.switch_en = 1;
++		cs_option.dest_ch_en = 1;
++		cs_option.absolute_time_en = 0;
++		cs_option.dest_ch = 1;
++
++		cs_option.normal_period = 5;
++		cs_option.normal_period_sel = 0;
++		cs_option.normal_cycle = 10;
++
++		cs_option.phase_2_period = 1;
++		cs_option.phase_2_period_sel = 1;
++
++		/* nlo is for wow fw,  1: no c2h response */
++		cs_option.nlo_en = nlo;
++
++		if (!nlo) {
++			err = init_halmac_event(d, id_ch_sw, NULL, 0);
++			if (err)
++				return -1;
++		}
++
++		status = api->halmac_ctrl_ch_switch(mac, &cs_option);
++		if (status != HALMAC_RET_SUCCESS) {
++			if (!nlo)
++				free_halmac_event(d, id_ch_sw);
++			RTW_ERR("%s: halmac_ctrl_ch_switch FAIL(%d)!!\n",
++				__FUNCTION__, status);
++			return -1;
++		}
++
++		if (!nlo) {
++			err = wait_halmac_event(d, id_ch_sw);
++			if (err)
++				RTW_ERR("%s: wait ctrl_ch_switch FAIL(%d)!!\n",
++					__FUNCTION__, err);
++		}
++	} else {
++		api->halmac_clear_ch_info(mac);
++
++		_rtw_memset(&cs_option, 0, sizeof(cs_option));
++		cs_option.switch_en = 0;
++
++		if (!nlo) {
++			err = init_halmac_event(d, id_ch_sw, NULL, 0);
++			if (err)
++				return -1;
++		}
++
++		status = api->halmac_ctrl_ch_switch(mac, &cs_option);
++		if (status != HALMAC_RET_SUCCESS) {
++			if (!nlo)
++				free_halmac_event(d, id_ch_sw);
++			RTW_ERR("%s: halmac_ctrl_ch_switch FAIL(%d)!!\n",
++				__FUNCTION__, status);
++			return -1;
++		}
++
++		if (!nlo) {
++			err = wait_halmac_event(d, id_ch_sw);
++			if (err)
++				RTW_ERR("%s: wait ctrl_ch_switch FAIL(%d)!!\n",
++					__FUNCTION__, err);
++		}
++	}
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_pno_scanoffload() - Control firmware scan AP function for PNO
++ * @d:		struct dvobj_priv*
++ * @enable:	1: enable, 0: disable
++ *
++ * Switch firmware scan AP function for PNO(prefer network offload) or
++ * NLO(network list offload).
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_pno_scanoffload(struct dvobj_priv *d, u32 enable)
++{
++	return _halmac_scanoffload(d, enable, 1, NULL, 0);
++}
++#endif /* CONFIG_PNO_SUPPORT */
++
++#ifdef CONFIG_SDIO_HCI
++
++/**
++ * rtw_halmac_preinit_sdio_io_indirect() - Enable indirect I/O or not
++ * @d:		struct dvobj_priv*
++ * @enable:	true: enable, false: disable
++ *
++ * Enable register access using direct I/O or indirect. This function should be
++ * called before rtw_halmac_init_adapter(), and the life cycle is the same as
++ * driver until removing driver.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_preinit_sdio_io_indirect(struct dvobj_priv *d, bool enable)
++{
++	struct halmac_adapter *halmac;
++	struct halmacpriv *priv;
++
++
++	halmac = dvobj_to_halmac(d);
++	if (halmac) {
++		RTW_WARN("%s: illegal operation! "
++			 "preinit function only could be called before init!\n",
++			 __FUNCTION__);
++		return -1;
++	}
++
++	priv = &d->hmpriv;
++	priv->sdio_io_indir = (enable ? 1 : 2);
++
++	return 0;
++}
++
++/*
++ * Description:
++ *	Update queue allocated page number to driver
++ *
++ * Parameter:
++ *	d	pointer to struct dvobj_priv of driver
++ *
++ * Return:
++ *	0	Success, "page" is valid.
++ *	others	Fail, "page" is invalid.
++ */
++int rtw_halmac_query_tx_page_num(struct dvobj_priv *d)
++{
++	PADAPTER adapter;
++	struct halmacpriv *hmpriv;
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	struct halmac_rqpn_map rqpn;
++	enum halmac_dma_mapping dmaqueue;
++	struct halmac_txff_allocation fifosize;
++	enum halmac_ret_status status;
++	u8 i;
++
++
++	adapter = dvobj_get_primary_adapter(d);
++	hmpriv = &d->hmpriv;
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++	_rtw_memset((void *)&rqpn, 0, sizeof(rqpn));
++	_rtw_memset((void *)&fifosize, 0, sizeof(fifosize));
++
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_RQPN_MAPPING, &rqpn);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_TXFF_ALLOCATION, &fifosize);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	for (i = 0; i < HW_QUEUE_ENTRY; i++) {
++		hmpriv->txpage[i] = 0;
++
++		/* Driver index mapping to HALMAC DMA queue */
++		dmaqueue = HALMAC_DMA_MAPPING_UNDEFINE;
++		switch (i) {
++		case VO_QUEUE_INX:
++			dmaqueue = rqpn.dma_map_vo;
++			break;
++		case VI_QUEUE_INX:
++			dmaqueue = rqpn.dma_map_vi;
++			break;
++		case BE_QUEUE_INX:
++			dmaqueue = rqpn.dma_map_be;
++			break;
++		case BK_QUEUE_INX:
++			dmaqueue = rqpn.dma_map_bk;
++			break;
++		case MGT_QUEUE_INX:
++			dmaqueue = rqpn.dma_map_mg;
++			break;
++		case HIGH_QUEUE_INX:
++			dmaqueue = rqpn.dma_map_hi;
++			break;
++		case BCN_QUEUE_INX:
++		case TXCMD_QUEUE_INX:
++			/* Unlimited */
++			hmpriv->txpage[i] = 0xFFFF;
++			continue;
++		}
++
++		switch (dmaqueue) {
++		case HALMAC_DMA_MAPPING_EXTRA:
++			hmpriv->txpage[i] = fifosize.extra_queue_pg_num;
++			break;
++		case HALMAC_DMA_MAPPING_LOW:
++			hmpriv->txpage[i] = fifosize.low_queue_pg_num;
++			break;
++		case HALMAC_DMA_MAPPING_NORMAL:
++			hmpriv->txpage[i] = fifosize.normal_queue_pg_num;
++			break;
++		case HALMAC_DMA_MAPPING_HIGH:
++			hmpriv->txpage[i] = fifosize.high_queue_pg_num;
++			break;
++		case HALMAC_DMA_MAPPING_UNDEFINE:
++			break;
++		}
++		hmpriv->txpage[i] += fifosize.pub_queue_pg_num;
++	}
++
++	return 0;
++}
++
++/*
++ * Description:
++ *	Get specific queue allocated page number
++ *
++ * Parameter:
++ *	d	pointer to struct dvobj_priv of driver
++ *	queue	target queue to query, VO/VI/BE/BK/.../TXCMD_QUEUE_INX
++ *	page	return allocated page number
++ *
++ * Return:
++ *	0	Success, "page" is valid.
++ *	others	Fail, "page" is invalid.
++ */
++int rtw_halmac_get_tx_queue_page_num(struct dvobj_priv *d, u8 queue, u32 *page)
++{
++	*page = 0;
++	if (queue < HW_QUEUE_ENTRY)
++		*page = d->hmpriv.txpage[queue];
++
++	return 0;
++}
++
++/*
++ * Return:
++ *	address for SDIO command
++ */
++u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *d, u8 *desc, u32 size)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u32 addr;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_get_sdio_tx_addr(mac, desc, size, &addr);
++	if (HALMAC_RET_SUCCESS != status)
++		return 0;
++
++	return addr;
++}
++
++int rtw_halmac_sdio_tx_allowed(struct dvobj_priv *d, u8 *buf, u32 size)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_tx_allowed_sdio(mac, buf, size);
++	if (HALMAC_RET_SUCCESS != status)
++		return -1;
++
++	return 0;
++}
++
++u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *d, u8 *seq)
++{
++	u8 id;
++
++#define RTW_SDIO_ADDR_RX_RX0FF_PRFIX	0x0E000
++#define RTW_SDIO_ADDR_RX_RX0FF_GEN(a)	(RTW_SDIO_ADDR_RX_RX0FF_PRFIX|(a&0x3))
++
++	id = *seq;
++	(*seq)++;
++	return RTW_SDIO_ADDR_RX_RX0FF_GEN(id);
++}
++
++int rtw_halmac_sdio_set_tx_format(struct dvobj_priv *d, enum halmac_sdio_tx_format format)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_set_hw_value(mac, HALMAC_HW_SDIO_TX_FORMAT, &format);
++	if (HALMAC_RET_SUCCESS != status)
++		return -1;
++
++	return 0;
++}
++#endif /* CONFIG_SDIO_HCI */
++
++#ifdef CONFIG_USB_HCI
++u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *d, u8 *buf, u32 size)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u8 bulkout_id;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_get_usb_bulkout_id(mac, buf, size, &bulkout_id);
++	if (HALMAC_RET_SUCCESS != status)
++		return 0;
++
++	return bulkout_id;
++}
++
++/**
++ * rtw_halmac_usb_get_txagg_desc_num() - MAX descriptor number in one bulk for TX
++ * @d:		struct dvobj_priv*
++ * @size:	TX FIFO size, unit is byte.
++ *
++ * Get MAX descriptor number in one bulk out from HALMAC.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num)
++{
++	struct halmac_adapter *halmac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	u8 val = 0;
++
++
++	halmac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(halmac);
++
++	status = api->halmac_get_hw_value(halmac, HALMAC_HW_USB_TXAGG_DESC_NUM, &val);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	*num = val;
++
++	return 0;
++}
++
++static inline enum halmac_usb_mode _usb_mode_drv2halmac(enum RTW_USB_SPEED usb_mode)
++{
++	enum halmac_usb_mode halmac_usb_mode = HALMAC_USB_MODE_U2;
++
++	switch (usb_mode) {
++	case RTW_USB_SPEED_2:
++		halmac_usb_mode = HALMAC_USB_MODE_U2;
++		break;
++	case RTW_USB_SPEED_3:
++		halmac_usb_mode = HALMAC_USB_MODE_U3;
++		break;
++	default:
++		halmac_usb_mode = HALMAC_USB_MODE_U2;
++		break;
++	}
++
++	return halmac_usb_mode;
++}
++
++u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode)
++{
++	PADAPTER adapter;
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	enum halmac_usb_mode halmac_usb_mode;
++
++	adapter = dvobj_get_primary_adapter(d);
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++	halmac_usb_mode = _usb_mode_drv2halmac(usb_mode);
++	status = api->halmac_set_hw_value(mac, HALMAC_HW_USB_MODE, (void *)&halmac_usb_mode);
++
++	if (HALMAC_RET_SUCCESS != status)
++		return _FAIL;
++
++	return _SUCCESS;
++}
++#endif /* CONFIG_USB_HCI */
++
++#ifdef CONFIG_BEAMFORMING
++#ifdef RTW_BEAMFORMING_VERSION_2
++int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para,
++		u16 my_aid, enum halmac_csi_seg_len sel, u8 *addr)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	struct halmac_mu_bfer_init_para param;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	_rtw_memset(&param, 0, sizeof(param));
++	param.paid = paid;
++	param.csi_para = csi_para;
++	param.my_aid = my_aid;
++	param.csi_length_sel = sel;
++	_rtw_memcpy(param.bfer_address.addr, addr, 6);
++
++	status = api->halmac_mu_bfer_entry_init(mac, &param);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	return 0;
++}
++
++int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_mu_bfer_entry_del(mac);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	return 0;
++}
++
++
++int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d,
++		enum halmac_snd_role role, enum halmac_data_rate rate)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_cfg_sounding(mac, role, rate);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	return 0;
++}
++
++int rtw_halmac_bf_del_sounding(struct dvobj_priv *d,
++		enum halmac_snd_role role)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_del_sounding(mac, role);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	return 0;
++}
++
++/**
++ * rtw_halmac_bf_cfg_csi_rate() - Config data rate for CSI report frame by RSSI
++ * @d:		struct dvobj_priv*
++ * @rssi:	RSSI vlaue, unit is percentage (0~100).
++ * @current_rate:	Current CSI frame rate
++ *			Valid value example
++ *			0	CCK 1M
++ *			3	CCK 11M
++ *			4	OFDM 6M
++ *			and so on
++ * @fixrate_en:	Enable to fix CSI frame in VHT rate, otherwise legacy OFDM rate.
++ *		The value "0" for disable, otheriwse enable.
++ * @new_rate:	Return new data rate, and value range is the same as
++ *		current_rate
++ * @bmp_ofdm54: Return to suggest enabling OFDM 54M for CSI report frame or not,
++ *		The valid values and meanings are:
++ *		0x00	disable
++ *		0x01	enable
++ *		0xFF	Keep current setting
++ *
++ * According RSSI to config data rate for CSI report frame of Beamforming.
++ *
++ * Return 0 for OK, otherwise fail.
++ */
++int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, u8 rssi,
++			       u8 current_rate, u8 fixrate_en, u8 *new_rate,
++			       u8 *bmp_ofdm54)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	status = api->halmac_cfg_csi_rate(mac,
++			rssi, current_rate, fixrate_en, new_rate,
++			bmp_ofdm54);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	return 0;
++}
++
++int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role,
++		u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en,
++		u32 *given_gid_tab, u32 *given_user_pos)
++{
++	struct halmac_adapter *mac;
++	struct halmac_api *api;
++	enum halmac_ret_status status;
++	struct halmac_cfg_mumimo_para param;
++
++
++	mac = dvobj_to_halmac(d);
++	api = HALMAC_GET_API(mac);
++
++	_rtw_memset(&param, 0, sizeof(param));
++
++	param.role = role;
++	param.grouping_bitmap = grouping_bitmap;
++	param.mu_tx_en = mu_tx_en;
++
++	if (sounding_sts)
++		_rtw_memcpy(param.sounding_sts, sounding_sts, 6);
++
++	if (given_gid_tab)
++		_rtw_memcpy(param.given_gid_tab, given_gid_tab, 8);
++
++	if (given_user_pos)
++		_rtw_memcpy(param.given_user_pos, given_user_pos, 16);
++
++	status = api->halmac_cfg_mumimo(mac, &param);
++	if (status != HALMAC_RET_SUCCESS)
++		return -1;
++
++	return 0;
++}
++
++#endif /* RTW_BEAMFORMING_VERSION_2 */
++#endif /* CONFIG_BEAMFORMING */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_halmac.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_halmac.h
+new file mode 100644
+index 000000000..04e1f73c6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_halmac.h
+@@ -0,0 +1,251 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2015 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _HAL_HALMAC_H_
++#define _HAL_HALMAC_H_
++
++#include <drv_types.h>		/* adapter_to_dvobj(), struct intf_hdl and etc. */
++#include <hal_data.h>		/* struct hal_spec_t */
++#include "halmac/halmac_api.h"	/* struct halmac_adapter* and etc. */
++
++/* HALMAC Definition for Driver */
++#define RTW_HALMAC_H2C_MAX_SIZE		8
++#define RTW_HALMAC_BA_SSN_RPT_SIZE	4
++
++#define dvobj_set_halmac(d, mac)	((d)->halmac = (mac))
++#define dvobj_to_halmac(d)		((struct halmac_adapter *)((d)->halmac))
++#define adapter_to_halmac(p)		dvobj_to_halmac(adapter_to_dvobj(p))
++
++/* for H2C cmd */
++#define MAX_H2C_BOX_NUMS 4
++#define MESSAGE_BOX_SIZE 4
++#define EX_MESSAGE_BOX_SIZE 4
++
++typedef enum _RTW_HALMAC_MODE {
++	RTW_HALMAC_MODE_NORMAL,
++	RTW_HALMAC_MODE_WIFI_TEST,
++} RTW_HALMAC_MODE;
++
++union rtw_phy_para_data {
++	struct _mac {
++		u32	value;	/* value to be set in bit mask(msk) */
++		u32	msk;	/* bit mask */
++		u16	offset; /* address */
++		u8	msk_en;	/* 0/1 for msk invalid/valid */
++		u8	size;	/* Unit is bytes, and value should be 1/2/4 */
++	} mac;
++	struct _bb {
++		u32	value;
++		u32	msk;
++		u16	offset;
++		u8	msk_en;
++		u8	size;
++	} bb;
++	struct _rf {
++		u32	value;
++		u32	msk;
++		u8	offset;
++		u8	msk_en;
++		/*
++		 * 0: path A
++		 * 1: path B
++		 * 2: path C
++		 * 3: path D
++		 */
++		u8	path;
++	} rf;
++	struct _delay {
++		/*
++		 * 0: microsecond (us)
++		 * 1: millisecond (ms)
++		 */
++		u8	unit;
++		u16	value;
++	} delay;
++};
++
++struct rtw_phy_parameter {
++	/*
++	 * 0: MAC register
++	 * 1: BB register
++	 * 2: RF register
++	 * 3: Delay
++	 * 0xFF: Latest(End) command
++	 */
++	u8 cmd;
++	union rtw_phy_para_data data;
++};
++
++struct rtw_halmac_bcn_ctrl {
++	u8 rx_bssid_fit:1;	/* 0:HW handle beacon, 1:ignore */
++	u8 txbcn_rpt:1;		/* Enable TXBCN report in ad hoc and AP mode */
++	u8 tsf_update:1;	/* Update TSF when beacon or probe response */
++	u8 enable_bcn:1;	/* Enable beacon related functions */
++	u8 rxbcn_rpt:1;		/* Enable RXBCNOK report */
++	u8 p2p_ctwin:1;		/* Enable P2P CTN WINDOWS function */
++	u8 p2p_bcn_area:1;	/* Enable P2P BCN area on function */
++};
++
++extern struct halmac_platform_api rtw_halmac_platform_api;
++
++/* HALMAC API for Driver(HAL) */
++u8 rtw_halmac_read8(struct intf_hdl *, u32 addr);
++u16 rtw_halmac_read16(struct intf_hdl *, u32 addr);
++u32 rtw_halmac_read32(struct intf_hdl *, u32 addr);
++void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr);
++u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr);
++u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr);
++#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
++int rtw_halmac_write8(struct intf_hdl *, u32 addr, u8 value);
++int rtw_halmac_write16(struct intf_hdl *, u32 addr, u16 value);
++int rtw_halmac_write32(struct intf_hdl *, u32 addr, u32 value);
++
++/* Software Information */
++void rtw_halmac_get_version(char *str, u32 len);
++
++/* Software setting before Initialization */
++int rtw_halmac_preinit_sdio_io_indirect(struct dvobj_priv *d, bool enable);
++
++/* Software Initialization */
++int rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf_api);
++int rtw_halmac_deinit_adapter(struct dvobj_priv *);
++
++/* Get operations */
++int rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void *pvalue);
++int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size);
++int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size);
++int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy);
++int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size);
++int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size);
++int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size);
++int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *, u8 *sz);
++int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size);
++int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size);
++int rtw_halmac_get_tx_dma_ch_map(struct dvobj_priv *d, u8 *dma_ch_map, u8 map_size);
++int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size);
++int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size);
++int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num);
++int rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
++int rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type);
++int rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl);
++/*int rtw_halmac_get_wow_reason(struct dvobj_priv *, u8 *reason);*/
++
++/* Set operations */
++int rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info);
++int rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size);
++int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
++int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
++int rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
++int rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type);
++int rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport);
++int rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport, u32 space);
++int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl);
++int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid);
++int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw);
++int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop);
++int rtw_halmac_set_rts_full_bw(struct dvobj_priv *d, u8 enable);
++
++/* Functions */
++int rtw_halmac_poweron(struct dvobj_priv *);
++int rtw_halmac_poweroff(struct dvobj_priv *);
++int rtw_halmac_init_hal(struct dvobj_priv *);
++int rtw_halmac_init_hal_fw(struct dvobj_priv *, u8 *fw, u32 fwsize);
++int rtw_halmac_init_hal_fw_file(struct dvobj_priv *, u8 *fwpath);
++int rtw_halmac_deinit_hal(struct dvobj_priv *);
++int rtw_halmac_self_verify(struct dvobj_priv *);
++int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout);
++int rtw_halmac_dlfw(struct dvobj_priv *, u8 *fw, u32 fwsize);
++int rtw_halmac_dlfw_from_file(struct dvobj_priv *, u8 *fwpath);
++int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem);
++int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem);
++int rtw_halmac_phy_power_switch(struct dvobj_priv *, u8 enable);
++int rtw_halmac_send_h2c(struct dvobj_priv *, u8 *h2c);
++int rtw_halmac_c2h_handle(struct dvobj_priv *, u8 *c2h, u32 size);
++
++/* eFuse */
++int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size);
++int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *, u32 *size);
++int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size);
++int rtw_halmac_read_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
++int rtw_halmac_write_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
++int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *, u32 *size);
++int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize);
++int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize);
++int rtw_halmac_read_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
++int rtw_halmac_write_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
++
++int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
++int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size);
++
++int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer);
++int rtw_halmac_rx_agg_switch(struct dvobj_priv *, u8 enable);
++
++/* Specific function APIs*/
++int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size);
++int rtw_halmac_fill_hal_spec(struct dvobj_priv *, struct hal_spec_t *);
++int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para);
++int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment);
++int rtw_halmac_dpk(struct dvobj_priv *d, u8 *buf, u32 bufsz);
++int rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para);
++int rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode);
++void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on);
++int rtw_halmac_bt_wake_cfg(struct dvobj_priv *d, u8 enable);
++#ifdef CONFIG_PNO_SUPPORT
++int rtw_halmac_pno_scanoffload(struct dvobj_priv *d, u32 enable);
++#endif
++
++#ifdef CONFIG_SDIO_HCI
++int rtw_halmac_query_tx_page_num(struct dvobj_priv *);
++int rtw_halmac_get_tx_queue_page_num(struct dvobj_priv *, u8 queue, u32 *page);
++u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *, u8 *desc, u32 size);
++int rtw_halmac_sdio_tx_allowed(struct dvobj_priv *, u8 *buf, u32 size);
++u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *, u8 *seq);
++int rtw_halmac_sdio_set_tx_format(struct dvobj_priv *d, enum halmac_sdio_tx_format format);
++#endif /* CONFIG_SDIO_HCI */
++
++#ifdef CONFIG_USB_HCI
++u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *, u8 *buf, u32 size);
++int rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num);
++u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode);
++#endif /* CONFIG_USB_HCI */
++
++#ifdef CONFIG_SUPPORT_TRX_SHARED
++void dump_trx_share_mode(void *sel, _adapter *adapter);
++#endif
++
++#ifdef CONFIG_BEAMFORMING
++#ifdef RTW_BEAMFORMING_VERSION_2
++int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para,
++		u16 my_aid, enum halmac_csi_seg_len sel, u8 *addr);
++int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d);
++
++int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d, enum halmac_snd_role role,
++		enum halmac_data_rate rate);
++int rtw_halmac_bf_del_sounding(struct dvobj_priv *d, enum halmac_snd_role role);
++
++int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, u8 rssi, u8 current_rate,
++		u8 fixrate_en, u8 *new_rate, u8 *bmp_ofdm54);
++
++int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role,
++		u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en,
++		u32 *given_gid_tab, u32 *given_user_pos);
++#define rtw_halmac_bf_cfg_mu_bfee(d, gid_tab, user_pos) \
++	rtw_halmac_bf_cfg_mu_mimo(d, HAL_BFEE, NULL, 0, 0, gid_tab, user_pos)
++
++#endif /* RTW_BEAMFORMING_VERSION_2 */
++#endif /* CONFIG_BEAMFORMING */
++
++#endif /* _HAL_HALMAC_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_hci/hal_sdio.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_hci/hal_sdio.c
+new file mode 100644
+index 000000000..1e49f713b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_hci/hal_sdio.c
+@@ -0,0 +1,810 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _HAL_SDIO_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++#ifndef RTW_HALMAC
++const char *_sdio_tx_queue_str[] = {
++	"H",
++	"M",
++	"L",
++};
++
++static void dump_mac_page0(PADAPTER padapter)
++{
++	char str_out[128];
++	char str_val[8];
++	char *p = NULL;
++	int index = 0, i = 0;
++	u8 val8 = 0, len = 0;
++
++	RTW_ERR("Dump MAC Page0 register:\n");
++	for (index = 0 ; index < 0x100 ; index += 16) {
++		p = &str_out[0];
++		len = snprintf(str_val, sizeof(str_val),
++			       "0x%02x: ", index);
++		strncpy(str_out, str_val, len);
++		p += len;
++
++		for (i = 0 ; i < 16 ; i++) {
++			len = snprintf(str_val, sizeof(str_val), "%02x ",
++				       rtw_read8(padapter, index + i));
++			strncpy(p, str_val, len);
++			p += len;
++		}
++		RTW_INFO("%s\n", str_out);
++		_rtw_memset(&str_out, '\0', sizeof(str_out));
++	}
++}
++
++/*
++ * Description:
++ *	Call this function to make sure power on successfully
++ *
++ * Return:
++ *	_SUCCESS	enable success
++ *	_FAIL	enable fail
++ */
++bool sdio_power_on_check(PADAPTER padapter) {
++	u32 val_offset0, val_offset1, val_offset2, val_offset3;
++	u32 val_mix = 0;
++	u32 res = 0;
++	bool ret = _FAIL;
++	int index = 0;
++
++	val_offset0 = rtw_read8(padapter, REG_CR);
++	val_offset1 = rtw_read8(padapter, REG_CR + 1);
++	val_offset2 = rtw_read8(padapter, REG_CR + 2);
++	val_offset3 = rtw_read8(padapter, REG_CR + 3);
++
++	if (val_offset0 == 0xEA || val_offset1 == 0xEA ||
++	    val_offset2 == 0xEA || val_offset3 == 0xEA) {
++		RTW_INFO("%s: power on fail, do Power on again\n", __func__);
++		return ret;
++	}
++
++	val_mix = val_offset3 << 24 | val_mix;
++	val_mix = val_offset2 << 16 | val_mix;
++	val_mix = val_offset1 << 8 | val_mix;
++	val_mix = val_offset0 | val_mix;
++
++	res = rtw_read32(padapter, REG_CR);
++
++	RTW_INFO("%s: val_mix:0x%08x, res:0x%08x\n", __func__, val_mix, res);
++
++	while (index < 100) {
++		if (res == val_mix) {
++			RTW_INFO("%s: 0x100 the result of cmd52 and cmd53 is the same.\n", __func__);
++			ret = _SUCCESS;
++			break;
++		} else {
++			RTW_INFO("%s: 0x100 cmd52 and cmd53 is not the same(index:%d).\n", __func__, index);
++			res = rtw_read32(padapter, REG_CR);
++			index++;
++			ret = _FAIL;
++		}
++	}
++
++	if (ret) {
++		index = 0;
++		while (index < 100) {
++			rtw_write32(padapter, 0x1B8, 0x12345678);
++			res = rtw_read32(padapter, 0x1B8);
++			if (res == 0x12345678) {
++				RTW_INFO("%s: 0x1B8 test Pass.\n", __func__);
++				ret = _SUCCESS;
++				break;
++			} else {
++				index++;
++				RTW_INFO("%s: 0x1B8 test Fail(index: %d).\n", __func__, index);
++				ret = _FAIL;
++			}
++		}
++	} else
++		RTW_INFO("%s: fail at cmd52, cmd53.\n", __func__);
++
++	if (ret == _FAIL)
++		dump_mac_page0(padapter);
++
++	return ret;
++}
++
++u8 rtw_hal_sdio_max_txoqt_free_space(_adapter *padapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	if (pHalData->SdioTxOQTMaxFreeSpace < 8)
++		pHalData->SdioTxOQTMaxFreeSpace = 8;
++
++	return pHalData->SdioTxOQTMaxFreeSpace;
++}
++
++u8 rtw_hal_sdio_query_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	if ((pHalData->SdioTxFIFOFreePage[PageIdx] + pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]) >= (RequiredPageNum))
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++void rtw_hal_sdio_update_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	u8	DedicatedPgNum = 0;
++	u8	RequiredPublicFreePgNum = 0;
++	/* _irqL irql; */
++
++	/* _enter_critical_bh(&pHalData->SdioTxFIFOFreePageLock, &irql); */
++
++	DedicatedPgNum = pHalData->SdioTxFIFOFreePage[PageIdx];
++	if (RequiredPageNum <= DedicatedPgNum)
++		pHalData->SdioTxFIFOFreePage[PageIdx] -= RequiredPageNum;
++	else {
++		pHalData->SdioTxFIFOFreePage[PageIdx] = 0;
++		RequiredPublicFreePgNum = RequiredPageNum - DedicatedPgNum;
++		pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] -= RequiredPublicFreePgNum;
++	}
++
++	/* _exit_critical_bh(&pHalData->SdioTxFIFOFreePageLock, &irql); */
++}
++
++void rtw_hal_set_sdio_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ, u8 div_num)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	u32	page_size;
++	u32	lenHQ, lenNQ, lenLQ;
++
++	rtw_hal_get_def_var(padapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
++
++	lenHQ = ((numHQ + numPubQ) / div_num) * page_size;
++	lenNQ = ((numNQ + numPubQ) / div_num) * page_size;
++	lenLQ = ((numLQ + numPubQ) / div_num) * page_size;
++
++	pHalData->sdio_tx_max_len[HI_QUEUE_IDX] = (lenHQ > MAX_XMITBUF_SZ) ? MAX_XMITBUF_SZ : lenHQ;
++	pHalData->sdio_tx_max_len[MID_QUEUE_IDX] = (lenNQ > MAX_XMITBUF_SZ) ? MAX_XMITBUF_SZ : lenNQ;
++	pHalData->sdio_tx_max_len[LOW_QUEUE_IDX] = (lenLQ > MAX_XMITBUF_SZ) ? MAX_XMITBUF_SZ : lenLQ;
++	#ifdef DBG_TX_FREE_PAGE
++	RTW_INFO("rtw_hal_set_sdio_tx_max_length div_num :%u  numHQ=%u numNQ=%u numLQ=%u numPubQ=%u\n",div_num ,numHQ,numNQ,numLQ,numPubQ);
++	RTW_INFO("pHalData->sdio_tx_max_len[HI_QUEUE_IDX] :%u\n",pHalData->sdio_tx_max_len[HI_QUEUE_IDX] );
++	RTW_INFO("pHalData->sdio_tx_max_len[MID_QUEUE_IDX] :%u\n",pHalData->sdio_tx_max_len[MID_QUEUE_IDX] );
++	RTW_INFO("rtw_hal_set_sdio_tx_max_length pHalData->sdio_tx_max_len[LOW_QUEUE_IDX] :%u\n",pHalData->sdio_tx_max_len[LOW_QUEUE_IDX] );
++	#endif
++}
++
++u32 rtw_hal_get_sdio_tx_max_length(PADAPTER padapter, u8 queue_idx)
++{
++	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	u32	deviceId, max_len;
++
++
++	deviceId = ffaddr2deviceId(pdvobjpriv, queue_idx);
++	switch (deviceId) {
++	case WLAN_TX_HIQ_DEVICE_ID:
++		max_len = pHalData->sdio_tx_max_len[HI_QUEUE_IDX];
++		break;
++
++	case WLAN_TX_MIQ_DEVICE_ID:
++		max_len = pHalData->sdio_tx_max_len[MID_QUEUE_IDX];
++		break;
++
++	case WLAN_TX_LOQ_DEVICE_ID:
++		max_len = pHalData->sdio_tx_max_len[LOW_QUEUE_IDX];
++		break;
++
++	default:
++		max_len = pHalData->sdio_tx_max_len[MID_QUEUE_IDX];
++		break;
++	}
++
++	return max_len;
++}
++
++#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
++#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) ||defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8192F)|| defined(CONFIG_RTL8723D)
++void rtw_hal_sdio_avail_page_threshold_init(_adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++
++	hal_data->sdio_avail_int_en_q = 0xFF;
++	rtw_write32(adapter, REG_TQPNT1, 0xFFFFFFFF);
++	rtw_write32(adapter, REG_TQPNT2, 0xFFFFFFFF);
++	#ifdef CONFIG_RTL8192F
++	rtw_write32(adapter, REG_TQPNT3_V1_8192F, 0xFFFFFFFF);
++	#endif
++}
++
++void rtw_hal_sdio_avail_page_threshold_en(_adapter *adapter, u8 qidx, u8 page)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++	if (hal_data->sdio_avail_int_en_q != qidx) {
++		u32 page_size;
++		u32 tx_max_len;
++		u32 threshold_reg[] = {REG_TQPNT1, REG_TQPNT1 + 2, REG_TQPNT2, REG_TQPNT2 + 2}; /* H, M, L, E */
++		u8 dw_shift[] = {0, 16, 0, 16}; /* H, M, L, E */
++		u32 threshold = 0;
++
++		/* use same low-high threshold as page num from tx_max_len */
++		if(dvobj->tx_aval_int_thr_mode == 0) /*default setting by requirement*/
++			threshold = page;
++		else if (dvobj->tx_aval_int_thr_mode == 1 && dvobj->tx_aval_int_thr_value)
++			threshold = dvobj->tx_aval_int_thr_value;
++		else {
++			rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
++			tx_max_len = hal_data->sdio_tx_max_len[qidx];
++			threshold = PageNum(tx_max_len, page_size);
++		}
++		threshold |= (threshold) << 8;
++
++		if (hal_data->sdio_avail_int_en_q == 0xFF)
++			rtw_write16(adapter, threshold_reg[qidx], threshold);
++		else if (hal_data->sdio_avail_int_en_q >> 1 == qidx >> 1) {/* same dword */
++			rtw_write16(adapter, threshold_reg[hal_data->sdio_avail_int_en_q], 0);
++			rtw_write32(adapter, threshold_reg[qidx & 0xFE]
++				, (0xFFFF << dw_shift[hal_data->sdio_avail_int_en_q]) | (threshold << dw_shift[qidx]));
++		} else {
++			rtw_write16(adapter, threshold_reg[hal_data->sdio_avail_int_en_q], 0);
++			rtw_write16(adapter, threshold_reg[hal_data->sdio_avail_int_en_q], 0xFFFF);
++			rtw_write16(adapter, threshold_reg[qidx], threshold);
++		}
++
++		hal_data->sdio_avail_int_en_q = qidx;
++
++		#ifdef DBG_TX_FREE_PAGE
++		RTW_INFO("DWQP enable avail page threshold %s:%u-%u\n", sdio_tx_queue_str(qidx)
++			, threshold & 0xFF, threshold >> 8);
++		#endif
++	}
++}
++#endif
++#endif /* CONFIG_SDIO_TX_ENABLE_AVAL_INT */
++
++#ifdef CONFIG_FW_C2H_REG
++void sd_c2h_hisr_hdl(_adapter *adapter)
++{
++	u8 c2h_evt[C2H_REG_LEN] = {0};
++	u8 id, seq, plen;
++	u8 *payload;
++
++	if (rtw_hal_c2h_evt_read(adapter, c2h_evt) != _SUCCESS)
++		goto exit;
++
++	if (rtw_hal_c2h_reg_hdr_parse(adapter, c2h_evt, &id, &seq, &plen, &payload) != _SUCCESS)
++		goto exit;
++		
++	if (rtw_hal_c2h_id_handle_directly(adapter, id, seq, plen, payload)) {
++		/* Handle directly */
++		rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
++		goto exit;
++	}
++
++	if (rtw_c2h_reg_wk_cmd(adapter, c2h_evt) != _SUCCESS)
++		RTW_ERR("%s rtw_c2h_reg_wk_cmd fail\n", __func__);
++
++exit:
++	return;
++}
++#endif
++
++#ifdef CONFIG_SDIO_CHK_HCI_RESUME
++
++#ifndef SDIO_HCI_RESUME_PWR_RDY_TIMEOUT_MS
++	#define SDIO_HCI_RESUME_PWR_RDY_TIMEOUT_MS 200
++#endif
++#ifndef DBG_SDIO_CHK_HCI_RESUME
++	#define DBG_SDIO_CHK_HCI_RESUME 0
++#endif
++
++bool sdio_chk_hci_resume(struct intf_hdl *pintfhdl)
++{
++	_adapter *adapter = pintfhdl->padapter;
++	u8 hci_sus_state;
++	u8 sus_ctl, sus_ctl_ori = 0xEA;
++	u8 do_leave = 0;
++	systime start = 0, end = 0;
++	u32 poll_cnt = 0;
++	u8 timeout = 0;
++	u8 sr = 0;
++	s32 err = 0;
++
++	rtw_hal_get_hwreg(adapter, HW_VAR_HCI_SUS_STATE, &hci_sus_state);
++	if (hci_sus_state == HCI_SUS_LEAVE || hci_sus_state == HCI_SUS_ERR)
++		goto no_hdl;
++
++	err = sd_cmd52_read(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_HSUS_CTRL), 1, &sus_ctl);
++	if (err)
++		goto exit;
++	sus_ctl_ori = sus_ctl;
++
++	if ((sus_ctl & HCI_RESUME_PWR_RDY) && !(sus_ctl & HCI_SUS_CTRL))
++		goto exit;
++
++	if (sus_ctl & HCI_SUS_CTRL) {
++		sus_ctl &= ~(HCI_SUS_CTRL);
++		err = sd_cmd52_write(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_HSUS_CTRL), 1, &sus_ctl);
++		if (err)
++			goto exit;
++	}
++
++	do_leave = 1;
++
++	/* polling for HCI_RESUME_PWR_RDY && !HCI_SUS_CTRL */
++	start = rtw_get_current_time();
++	while (1) {
++		if (rtw_is_surprise_removed(adapter)) {
++			sr = 1;
++			break;
++		}
++
++		err = sd_cmd52_read(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_HSUS_CTRL), 1, &sus_ctl);
++		poll_cnt++;
++
++		if (!err && (sus_ctl & HCI_RESUME_PWR_RDY) && !(sus_ctl & HCI_SUS_CTRL))
++			break;
++
++		if (rtw_get_passing_time_ms(start) > SDIO_HCI_RESUME_PWR_RDY_TIMEOUT_MS) {
++			timeout = 1;
++			break;
++		}
++	}
++	end = rtw_get_current_time();
++
++exit:
++
++	if (DBG_SDIO_CHK_HCI_RESUME) {
++		RTW_INFO(FUNC_ADPT_FMT" hci_sus_state:%u, sus_ctl:0x%02x(0x%02x), do_leave:%u, to:%u, err:%u\n"
++			, FUNC_ADPT_ARG(adapter), hci_sus_state, sus_ctl, sus_ctl_ori, do_leave, timeout, err);
++		if (start != 0 || end != 0) {
++			RTW_INFO(FUNC_ADPT_FMT" polling %d ms, cnt:%u\n"
++				, FUNC_ADPT_ARG(adapter), rtw_get_time_interval_ms(start, end), poll_cnt);
++		}
++	}
++
++	if (timeout) {
++		RTW_ERR(FUNC_ADPT_FMT" timeout(err:%d) sus_ctl:0x%02x\n"
++			, FUNC_ADPT_ARG(adapter), err, sus_ctl);
++	} else if (err) {
++		RTW_ERR(FUNC_ADPT_FMT" err:%d\n"
++			, FUNC_ADPT_ARG(adapter), err);
++	}
++
++no_hdl:
++	return do_leave ? _TRUE : _FALSE;
++}
++
++void sdio_chk_hci_suspend(struct intf_hdl *pintfhdl)
++{
++#define SDIO_CHK_HCI_SUSPEND_POLLING 0
++
++	_adapter *adapter = pintfhdl->padapter;
++	u8 hci_sus_state;
++	u8 sus_ctl, sus_ctl_ori = 0xEA;
++	systime start = 0, end = 0;
++	u32 poll_cnt = 0;
++	u8 timeout = 0;
++	u8 sr = 0;
++	s32 err = 0;
++	u8 device_id;
++	u16 offset;
++
++	rtw_hal_get_hwreg(adapter, HW_VAR_HCI_SUS_STATE, &hci_sus_state);
++	if (hci_sus_state == HCI_SUS_LEAVE || hci_sus_state == HCI_SUS_LEAVING || hci_sus_state == HCI_SUS_ERR)
++		goto no_hdl;
++
++	err = sd_cmd52_read(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_HSUS_CTRL), 1, &sus_ctl);
++	if (err)
++		goto exit;
++	sus_ctl_ori = sus_ctl;
++
++	if (!(sus_ctl & HCI_RESUME_PWR_RDY))
++		goto exit;
++
++	sus_ctl |= HCI_SUS_CTRL;
++	err = sd_cmd52_write(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_HSUS_CTRL), 1, &sus_ctl);
++	if (err)
++		goto exit;
++
++#if SDIO_CHK_HCI_SUSPEND_POLLING
++	/* polling for HCI_RESUME_PWR_RDY cleared */
++	start = rtw_get_current_time();
++	while (1) {
++		if (rtw_is_surprise_removed(adapter)) {
++			sr = 1;
++			break;
++		}
++
++		err = sd_cmd52_read(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_HSUS_CTRL), 1, &sus_ctl);
++		poll_cnt++;
++
++		if (!err && !(sus_ctl & HCI_RESUME_PWR_RDY))
++			break;
++
++		if (rtw_get_passing_time_ms(start) > SDIO_HCI_RESUME_PWR_RDY_TIMEOUT_MS) {
++			timeout = 1;
++			break;
++		}
++	}
++	end = rtw_get_current_time();
++#endif /* SDIO_CHK_HCI_SUSPEND_POLLING */
++
++exit:
++
++	if (DBG_SDIO_CHK_HCI_RESUME) {
++		RTW_INFO(FUNC_ADPT_FMT" hci_sus_state:%u, sus_ctl:0x%02x(0x%02x), to:%u, err:%u\n"
++			, FUNC_ADPT_ARG(adapter), hci_sus_state, sus_ctl, sus_ctl_ori, timeout, err);
++		if (start != 0 || end != 0) {
++			RTW_INFO(FUNC_ADPT_FMT" polling %d ms, cnt:%u\n"
++				, FUNC_ADPT_ARG(adapter), rtw_get_time_interval_ms(start, end), poll_cnt);
++		}
++	}
++
++#if SDIO_CHK_HCI_SUSPEND_POLLING
++	if (timeout) {
++		RTW_ERR(FUNC_ADPT_FMT" timeout(err:%d) sus_ctl:0x%02x\n"
++			, FUNC_ADPT_ARG(adapter), err, sus_ctl);
++	} else
++#endif
++		if (err) {
++			RTW_ERR(FUNC_ADPT_FMT" err:%d\n"
++				, FUNC_ADPT_ARG(adapter), err);
++		}
++
++no_hdl:
++	return;
++}
++#endif /* CONFIG_SDIO_CHK_HCI_RESUME */
++
++
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++
++/* program indirect access register in sdio local to read/write page0 registers */
++#ifndef INDIRECT_ACCESS_TIMEOUT_MS
++	#define INDIRECT_ACCESS_TIMEOUT_MS 200
++#endif
++#ifndef DBG_SDIO_INDIRECT_ACCESS
++	#define DBG_SDIO_INDIRECT_ACCESS 0
++#endif
++
++s32 sdio_iread(PADAPTER padapter, u32 addr, u8 size, u8 *v)
++{
++	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
++	_mutex *mutex = &adapter_to_dvobj(padapter)->sd_indirect_access_mutex;
++
++	u8 val[4] = {0};
++	u8 cmd[4] = {0}; /* mapping to indirect access register, little endien */
++	systime start = 0, end = 0;
++	u8 timeout = 0;
++	u8 sr = 0;
++	s32 err = 0;
++
++	if (size == 1)
++		SET_INDIRECT_REG_SIZE_1BYTE(cmd);
++	else if (size == 2)
++		SET_INDIRECT_REG_SIZE_2BYTE(cmd);
++	else if (size == 4)
++		SET_INDIRECT_REG_SIZE_4BYTE(cmd);
++
++	SET_INDIRECT_REG_ADDR(cmd, addr);
++
++	/* acquire indirect access lock */
++	_enter_critical_mutex(mutex, NULL);
++
++	if (DBG_SDIO_INDIRECT_ACCESS)
++		RTW_INFO(FUNC_ADPT_FMT" cmd:%02x %02x %02x %02x\n", FUNC_ADPT_ARG(padapter), cmd[0], cmd[1], cmd[2], cmd[3]);
++
++	err = sd_cmd52_write(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_INDIRECT_REG_CFG), 3, cmd);
++	if (err)
++		goto exit;
++
++	/* trigger */
++	SET_INDIRECT_REG_READ(cmd);
++
++	if (DBG_SDIO_INDIRECT_ACCESS)
++		RTW_INFO(FUNC_ADPT_FMT" cmd:%02x %02x %02x %02x\n", FUNC_ADPT_ARG(padapter), cmd[0], cmd[1], cmd[2], cmd[3]);
++
++	err = sd_cmd52_write(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_INDIRECT_REG_CFG + 2), 1, cmd + 2);
++	if (err)
++		goto exit;
++
++	/* polling for indirect access done */
++	start = rtw_get_current_time();
++	while (1) {
++		if (rtw_is_surprise_removed(padapter)) {
++			sr = 1;
++			break;
++		}
++
++		err = sd_cmd52_read(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_INDIRECT_REG_CFG + 2), 1, cmd + 2);
++
++		if (!err && GET_INDIRECT_REG_RDY(cmd))
++			break;
++
++		if (rtw_get_passing_time_ms(start) > INDIRECT_ACCESS_TIMEOUT_MS) {
++			timeout = 1;
++			break;
++		}
++	}
++	end = rtw_get_current_time();
++
++	if (timeout || sr)
++		goto exit;
++
++	/* read result */
++	err = sd_cmd52_read(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_INDIRECT_REG_DATA), size, val);
++	if (size == 2)
++		*((u16 *)(val)) = le16_to_cpu(*((u16 *)(val)));
++	else if (size == 4)
++		*((u32 *)(val)) = le32_to_cpu(*((u32 *)(val)));
++
++	if (DBG_SDIO_INDIRECT_ACCESS) {
++		if (size == 1)
++			RTW_INFO(FUNC_ADPT_FMT" val:0x%02x\n", FUNC_ADPT_ARG(padapter), *((u8 *)(val)));
++		else if (size == 2)
++			RTW_INFO(FUNC_ADPT_FMT" val:0x%04x\n", FUNC_ADPT_ARG(padapter), *((u16 *)(val)));
++		else if (size == 4)
++			RTW_INFO(FUNC_ADPT_FMT" val:0x%08x\n", FUNC_ADPT_ARG(padapter), *((u32 *)(val)));
++	}
++
++exit:
++	/* release indirect access lock */
++	_exit_critical_mutex(mutex, NULL);
++
++	if (DBG_SDIO_INDIRECT_ACCESS) {
++		RTW_INFO(FUNC_ADPT_FMT" addr:0x%0x size:%u, cmd:%02x %02x %02x %02x, to:%u, err:%u\n"
++			, FUNC_ADPT_ARG(padapter), addr, size, cmd[0], cmd[1], cmd[2], cmd[3], timeout, err);
++		if (start != 0 || end != 0) {
++			RTW_INFO(FUNC_ADPT_FMT" polling %d ms\n"
++				, FUNC_ADPT_ARG(padapter), rtw_get_time_interval_ms(start, end));
++		}
++	}
++
++	if (timeout) {
++		RTW_ERR(FUNC_ADPT_FMT" addr:0x%0x timeout(err:%d), cmd\n"
++			, FUNC_ADPT_ARG(padapter), addr, err);
++		if (!err)
++			err = -1; /* just for return value */
++	} else if (err) {
++		RTW_ERR(FUNC_ADPT_FMT" addr:0x%0x err:%d\n"
++			, FUNC_ADPT_ARG(padapter), addr, err);
++	} else if (sr) {
++		/* just for return value */
++		err = -1;
++	}
++
++	if (!err && !timeout && !sr)
++		_rtw_memcpy(v, val, size);
++
++	return err;
++}
++
++s32 sdio_iwrite(PADAPTER padapter, u32 addr, u8 size, u8 *v)
++{
++	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
++	_mutex *mutex = &adapter_to_dvobj(padapter)->sd_indirect_access_mutex;
++
++	u8 val[4] = {0};
++	u8 cmd[4] = {0}; /* mapping to indirect access register, little endien */
++	systime start = 0, end = 0;
++	u8 timeout = 0;
++	u8 sr = 0;
++	s32 err = 0;
++
++	if (size == 1)
++		SET_INDIRECT_REG_SIZE_1BYTE(cmd);
++	else if (size == 2)
++		SET_INDIRECT_REG_SIZE_2BYTE(cmd);
++	else if (size == 4)
++		SET_INDIRECT_REG_SIZE_4BYTE(cmd);
++
++	SET_INDIRECT_REG_ADDR(cmd, addr);
++
++	/* acquire indirect access lock */
++	_enter_critical_mutex(mutex, NULL);
++
++	if (DBG_SDIO_INDIRECT_ACCESS)
++		RTW_INFO(FUNC_ADPT_FMT" cmd:%02x %02x %02x %02x\n", FUNC_ADPT_ARG(padapter), cmd[0], cmd[1], cmd[2], cmd[3]);
++
++	err = sd_cmd52_write(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_INDIRECT_REG_CFG), 3, cmd);
++	if (err)
++		goto exit;
++
++	/* data to write */
++	_rtw_memcpy(val, v, size);
++
++	if (DBG_SDIO_INDIRECT_ACCESS) {
++		if (size == 1)
++			RTW_INFO(FUNC_ADPT_FMT" val:0x%02x\n", FUNC_ADPT_ARG(padapter), *((u8 *)(val)));
++		else if (size == 2)
++			RTW_INFO(FUNC_ADPT_FMT" val:0x%04x\n", FUNC_ADPT_ARG(padapter), *((u16 *)(val)));
++		else if (size == 4)
++			RTW_INFO(FUNC_ADPT_FMT" val:0x%08x\n", FUNC_ADPT_ARG(padapter), *((u32 *)(val)));
++	}
++
++	if (size == 2)
++		*((u16 *)(val)) = cpu_to_le16(*((u16 *)(val)));
++	else if (size == 4)
++		*((u32 *)(val)) = cpu_to_le32(*((u32 *)(val)));
++
++	err = sd_cmd52_write(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_INDIRECT_REG_DATA), size, val);
++	if (err)
++		goto exit;
++
++	/* trigger */
++	SET_INDIRECT_REG_WRITE(cmd);
++
++	if (DBG_SDIO_INDIRECT_ACCESS)
++		RTW_INFO(FUNC_ADPT_FMT" cmd:%02x %02x %02x %02x\n", FUNC_ADPT_ARG(padapter), cmd[0], cmd[1], cmd[2], cmd[3]);
++
++	err = sd_cmd52_write(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_INDIRECT_REG_CFG + 2), 1, cmd + 2);
++	if (err)
++		goto exit;
++
++	/* polling for indirect access done */
++	start = rtw_get_current_time();
++	while (1) {
++		if (rtw_is_surprise_removed(padapter)) {
++			sr = 1;
++			break;
++		}
++
++		err = sd_cmd52_read(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_INDIRECT_REG_CFG + 2), 1, cmd + 2);
++
++		if (!err && GET_INDIRECT_REG_RDY(cmd))
++			break;
++
++		if (rtw_get_passing_time_ms(start) > INDIRECT_ACCESS_TIMEOUT_MS) {
++			timeout = 1;
++			break;
++		}
++	}
++	end = rtw_get_current_time();
++
++	if (timeout || sr)
++		goto exit;
++
++exit:
++	/* release indirect access lock */
++	_exit_critical_mutex(mutex, NULL);
++
++	if (DBG_SDIO_INDIRECT_ACCESS) {
++		RTW_INFO(FUNC_ADPT_FMT" addr:0x%0x size:%u, cmd:%02x %02x %02x %02x, to:%u, err:%u\n"
++			, FUNC_ADPT_ARG(padapter), addr, size, cmd[0], cmd[1], cmd[2], cmd[3], timeout, err);
++		if (start != 0 || end != 0) {
++			RTW_INFO(FUNC_ADPT_FMT" polling %d ms\n"
++				, FUNC_ADPT_ARG(padapter), rtw_get_time_interval_ms(start, end));
++		}
++	}
++
++	if (timeout) {
++		RTW_ERR(FUNC_ADPT_FMT" addr:0x%0x timeout(err:%d), cmd\n"
++			, FUNC_ADPT_ARG(padapter), addr, err);
++		if (!err)
++			err = -1; /* just for return value */
++	} else if (err) {
++		RTW_ERR(FUNC_ADPT_FMT" addr:0x%0x err:%d\n"
++			, FUNC_ADPT_ARG(padapter), addr, err);
++	} else if (sr) {
++		/* just for return value */
++		err = -1;
++	}
++
++	return err;
++}
++
++u8 sdio_iread8(struct intf_hdl *pintfhdl, u32 addr)
++{
++	u8 val;
++
++	if (sdio_iread(pintfhdl->padapter, addr, 1, (u8 *)&val) != 0)
++		val = SDIO_ERR_VAL8;
++
++	return val;
++}
++
++u16 sdio_iread16(struct intf_hdl *pintfhdl, u32 addr)
++{
++	u16 val;
++
++	if (sdio_iread(pintfhdl->padapter, addr, 2, (u8 *)&val) != 0)
++		val = SDIO_ERR_VAL16;
++
++	return val;
++}
++
++u32 sdio_iread32(struct intf_hdl *pintfhdl, u32 addr)
++{
++	u32 val;
++
++	if (sdio_iread(pintfhdl->padapter, addr, 4, (u8 *)&val) != 0)
++		val = SDIO_ERR_VAL32;
++
++	return val;
++}
++
++s32 sdio_iwrite8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
++{
++	return sdio_iwrite(pintfhdl->padapter, addr, 1, (u8 *)&val);
++}
++
++s32 sdio_iwrite16(struct intf_hdl *pintfhdl, u32 addr, u16 val)
++{
++	return sdio_iwrite(pintfhdl->padapter, addr, 2, (u8 *)&val);
++}
++
++s32 sdio_iwrite32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
++{
++	return sdio_iwrite(pintfhdl->padapter, addr, 4, (u8 *)&val);
++}
++#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
++u32 cmd53_4byte_alignment(struct intf_hdl *pintfhdl, u32 addr)
++{
++	u32 addr_rdr;
++	u32 value;
++
++	value = 0;
++	addr_rdr = addr % 4;
++
++	if (addr_rdr) {
++		u8 shift_bit;
++
++		shift_bit = addr_rdr * 8;
++		value = (sd_read32(pintfhdl, (addr - addr_rdr), NULL)) >> shift_bit;
++	} else
++		value = sd_read32(pintfhdl, addr, NULL);
++	
++	return value;
++}
++
++#endif /* !RTW_HALMAC */
++
++#ifndef CONFIG_SDIO_TX_TASKLET
++#ifdef SDIO_FREE_XMIT_BUF_SEMA
++void _rtw_sdio_free_xmitbuf_sema_up(struct xmit_priv *xmit)
++{
++	_rtw_up_sema(&xmit->sdio_free_xmitbuf_sema);
++}
++
++void _rtw_sdio_free_xmitbuf_sema_down(struct xmit_priv *xmit)
++{
++	_rtw_down_sema(&xmit->sdio_free_xmitbuf_sema);
++}
++
++#ifdef DBG_SDIO_FREE_XMIT_BUF_SEMA
++void dbg_rtw_sdio_free_xmitbuf_sema_up(struct xmit_priv *xmit, const char *caller)
++{
++	/* just for debug usage only, pleae take care for the different of count implementaton */
++	RTW_INFO("%s("ADPT_FMT") before up sdio_free_xmitbuf_sema, count:%u\n"
++		, caller, ADPT_ARG(xmit->adapter), xmit->sdio_free_xmitbuf_sema.count);
++	_rtw_sdio_free_xmitbuf_sema_up(xmit);
++}
++
++void dbg_rtw_sdio_free_xmitbuf_sema_down(struct xmit_priv *xmit, const char *caller)
++{
++	/* just for debug usage only, pleae take care for the different of count implementaton */
++	RTW_INFO("%s("ADPT_FMT") before down sdio_free_xmitbuf_sema, count:%u\n"
++		, caller, ADPT_ARG(xmit->adapter), xmit->sdio_free_xmitbuf_sema.count);
++	_rtw_sdio_free_xmitbuf_sema_down(xmit);
++}
++#endif /* DBG_SDIO_FREE_XMIT_BUF_SEMA */
++
++#endif /* SDIO_FREE_XMIT_BUF_SEMA */
++#endif /* !CONFIG_SDIO_TX_TASKLET */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_hci/hal_sdio_coex.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_hci/hal_sdio_coex.c
+new file mode 100644
+index 000000000..564e4089a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_hci/hal_sdio_coex.c
+@@ -0,0 +1,35 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#include <drv_types.h>
++#include <hal_data.h>	/* HAL_DATA_TYPE */
++
++#ifdef CONFIG_SDIO_MULTI_FUNCTION_COEX
++
++int rtw_sdio_multi_state = SDIO_MULTI_WIFI;
++EXPORT_SYMBOL(rtw_sdio_multi_state);
++
++bool ex_hal_sdio_multi_if_bus_available(PADAPTER adapter)
++{
++	return rtw_sdio_multi_state == SDIO_MULTI_WIFI;
++}
++
++#endif  /* CONFIG_SDIO_MULTI_FUNCTION_COEX */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_intf.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_intf.c
+new file mode 100755
+index 000000000..888994297
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_intf.c
+@@ -0,0 +1,2291 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#define _HAL_INTF_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++const u32 _chip_type_to_odm_ic_type[] = {
++	0,
++	ODM_RTL8188E,
++	ODM_RTL8192E,
++	ODM_RTL8812,
++	ODM_RTL8821,
++	ODM_RTL8723B,
++	ODM_RTL8814A,
++	ODM_RTL8703B,
++	ODM_RTL8188F,
++	ODM_RTL8188F,
++	ODM_RTL8822B,
++	ODM_RTL8723D,
++	ODM_RTL8821C,
++	ODM_RTL8710B,
++	ODM_RTL8192F,
++	ODM_RTL8822C,
++	ODM_RTL8814B,
++	0,
++};
++
++void rtw_hal_chip_configure(_adapter *padapter)
++{
++	padapter->hal_func.intf_chip_configure(padapter);
++}
++
++/*
++ * Description:
++ *	Read chip internal ROM data
++ *
++ * Return:
++ *	_SUCCESS success
++ *	_FAIL	 fail
++ */
++u8 rtw_hal_read_chip_info(_adapter *padapter)
++{
++	u8 rtn = _SUCCESS;
++	u8 hci_type = rtw_get_intf_type(padapter);
++	systime start = rtw_get_current_time();
++
++	/*  before access eFuse, make sure card enable has been called */
++	if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
++	    && !rtw_is_hw_init_completed(padapter))
++		rtw_hal_power_on(padapter);
++
++	rtn = padapter->hal_func.read_adapter_info(padapter);
++
++	if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
++	    && !rtw_is_hw_init_completed(padapter))
++		rtw_hal_power_off(padapter);
++
++	RTW_INFO("%s in %d ms\n", __func__, rtw_get_passing_time_ms(start));
++
++	return rtn;
++}
++
++void rtw_hal_read_chip_version(_adapter *padapter)
++{
++	padapter->hal_func.read_chip_version(padapter);
++	rtw_odm_init_ic_type(padapter);
++}
++
++static void rtw_init_wireless_mode(_adapter *padapter)
++{
++	u8 proto_wireless_mode = 0;
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++	if(hal_spec->proto_cap & PROTO_CAP_11B)
++		proto_wireless_mode |= WIRELESS_11B;
++	
++	if(hal_spec->proto_cap & PROTO_CAP_11G)
++		proto_wireless_mode |= WIRELESS_11G;
++#ifdef CONFIG_80211AC_VHT
++	if(hal_spec->band_cap & BAND_CAP_5G)
++		proto_wireless_mode |= WIRELESS_11A;
++#endif
++
++#ifdef CONFIG_80211N_HT
++	if(hal_spec->proto_cap & PROTO_CAP_11N) {
++
++		if(hal_spec->band_cap & BAND_CAP_2G)
++			proto_wireless_mode |= WIRELESS_11_24N;
++		if(hal_spec->band_cap & BAND_CAP_5G)
++			proto_wireless_mode |= WIRELESS_11_5N;
++	}
++#endif
++
++#ifdef CONFIG_80211AC_VHT
++	if(hal_spec->proto_cap & PROTO_CAP_11AC) 
++		proto_wireless_mode |= WIRELESS_11AC;
++#endif
++	padapter->registrypriv.wireless_mode &= proto_wireless_mode;
++}
++
++void rtw_hal_def_value_init(_adapter *padapter)
++{
++	if (is_primary_adapter(padapter)) {
++		/*init fw_psmode_iface_id*/
++		adapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff;
++		/*wireless_mode*/
++		rtw_init_wireless_mode(padapter);
++		padapter->hal_func.init_default_value(padapter);
++
++		rtw_init_hal_com_default_value(padapter);
++		
++		#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++		adapter_to_dvobj(padapter)->dft.port_id = 0xFF;
++		adapter_to_dvobj(padapter)->dft.mac_id = 0xFF;
++		#endif
++		#ifdef CONFIG_HW_P0_TSF_SYNC
++		adapter_to_dvobj(padapter)->p0_tsf.sync_port = MAX_HW_PORT;
++		adapter_to_dvobj(padapter)->p0_tsf.offset = 0;
++		#endif
++
++		GET_HAL_DATA(padapter)->rx_tsf_addr_filter_config = 0;
++	}
++}
++
++u8 rtw_hal_data_init(_adapter *padapter)
++{
++	if (is_primary_adapter(padapter)) {
++		padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
++		padapter->HalData = rtw_zvmalloc(padapter->hal_data_sz);
++		if (padapter->HalData == NULL) {
++			RTW_INFO("cant not alloc memory for HAL DATA\n");
++			return _FAIL;
++		}
++		rtw_phydm_priv_init(padapter);
++	}
++	return _SUCCESS;
++}
++
++void rtw_hal_data_deinit(_adapter *padapter)
++{
++	if (is_primary_adapter(padapter)) {
++		if (padapter->HalData) {
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++			phy_free_filebuf(padapter);
++#endif
++			rtw_vmfree(padapter->HalData, padapter->hal_data_sz);
++			padapter->HalData = NULL;
++			padapter->hal_data_sz = 0;
++		}
++	}
++}
++
++void	rtw_hal_free_data(_adapter *padapter)
++{
++	/* free HAL Data	 */
++	rtw_hal_data_deinit(padapter);
++}
++void rtw_hal_dm_init(_adapter *padapter)
++{
++	if (is_primary_adapter(padapter)) {
++		PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++
++		padapter->hal_func.dm_init(padapter);
++
++		_rtw_spinlock_init(&pHalData->IQKSpinLock);
++
++		#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
++		if (pHalData->txpwr_pg_mode == TXPWR_PG_WITH_PWR_IDX)
++			hal_load_txpwr_info(padapter);
++		#endif
++		phy_load_tx_power_ext_info(padapter, 1);
++	}
++}
++void rtw_hal_dm_deinit(_adapter *padapter)
++{
++	if (is_primary_adapter(padapter)) {
++		PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++
++		padapter->hal_func.dm_deinit(padapter);
++
++		_rtw_spinlock_free(&pHalData->IQKSpinLock);
++	}
++}
++
++enum rf_type rtw_chip_rftype_to_hal_rftype(_adapter *adapter, u8 limit)
++{
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
++	u8 tx_num = 0, rx_num = 0;
++
++	/*get RF PATH from version_id.RF_TYPE */
++	if (IS_1T1R(hal_data->version_id)) {
++		tx_num = 1;
++		rx_num = 1;
++	} else if (IS_1T2R(hal_data->version_id)) {
++		tx_num = 1;
++		rx_num = 2;
++	} else if (IS_2T2R(hal_data->version_id)) {
++		tx_num = 2;
++		rx_num = 2;
++	} else if (IS_2T3R(hal_data->version_id)) {
++		tx_num = 2;
++		rx_num = 3;
++	} else if (IS_2T4R(hal_data->version_id)) {
++		tx_num = 2;
++		rx_num = 4;
++	} else if (IS_3T3R(hal_data->version_id)) {
++		tx_num = 3;
++		rx_num = 3;
++	} else if (IS_3T4R(hal_data->version_id)) {
++		tx_num = 3;
++		rx_num = 4;
++	} else if (IS_4T4R(hal_data->version_id)) {
++		tx_num = 4;
++		rx_num = 4;
++	}
++
++	if (limit) {
++		tx_num = rtw_min(tx_num, limit);
++		rx_num = rtw_min(rx_num, limit);
++	}
++
++	return trx_num_to_rf_type(tx_num, rx_num);
++}
++
++void dump_hal_runtime_trx_mode(void *sel, _adapter *adapter)
++{
++	struct registry_priv *regpriv = &adapter->registrypriv;
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
++	int i;
++
++	RTW_PRINT_SEL(sel, "txpath=0x%x, rxpath=0x%x\n", hal_data->txpath, hal_data->rxpath);
++	for (i = 0; i < hal_data->tx_nss; i++)
++		RTW_PRINT_SEL(sel, "txpath_%uss:0x%x, num:%u\n"
++			, i + 1, hal_data->txpath_nss[i]
++			, hal_data->txpath_num_nss[i]);
++}
++
++void dump_hal_trx_mode(void *sel, _adapter *adapter)
++{
++	struct registry_priv *regpriv = &adapter->registrypriv;
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
++
++	RTW_PRINT_SEL(sel, "trx_path_bmp:0x%02x(%s), NumTotalRFPath:%u, max_tx_cnt:%u\n"
++		, hal_data->trx_path_bmp
++		, rf_type_to_rfpath_str(hal_data->rf_type)
++		, hal_data->NumTotalRFPath
++		, hal_data->max_tx_cnt
++	);
++	RTW_PRINT_SEL(sel, "tx_nss:%u, rx_nss:%u\n"
++		, hal_data->tx_nss, hal_data->rx_nss);
++	RTW_PRINT_SEL(sel, "\n");
++
++	dump_hal_runtime_trx_mode(sel, adapter);
++}
++
++void _dump_rf_path(void *sel, _adapter *adapter)
++{
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	struct registry_priv *regsty = adapter_to_regsty(adapter);
++
++	RTW_PRINT_SEL(sel, "[RF_PATH] ver_id.RF_TYPE:%s\n"
++		, rf_type_to_rfpath_str(rtw_chip_rftype_to_hal_rftype(adapter, 0)));
++	RTW_PRINT_SEL(sel, "[RF_PATH] HALSPEC's rf_reg_trx_path_bmp:0x%02x, rf_reg_path_avail_num:%u, max_tx_cnt:%u\n"
++		, hal_spec->rf_reg_trx_path_bmp, hal_spec->rf_reg_path_avail_num, hal_spec->max_tx_cnt);
++	RTW_PRINT_SEL(sel, "[RF_PATH] PG's trx_path_bmp:0x%02x, max_tx_cnt:%u\n"
++		, hal_data->eeprom_trx_path_bmp, hal_data->eeprom_max_tx_cnt);
++	RTW_PRINT_SEL(sel, "[RF_PATH] Registry's trx_path_bmp:0x%02x, tx_path_lmt:%u, rx_path_lmt:%u\n"
++		, regsty->trx_path_bmp, regsty->tx_path_lmt, regsty->rx_path_lmt);
++	RTW_PRINT_SEL(sel, "[RF_PATH] HALDATA's trx_path_bmp:0x%02x, max_tx_cnt:%u\n"
++		, hal_data->trx_path_bmp, hal_data->max_tx_cnt);
++	RTW_PRINT_SEL(sel, "[RF_PATH] HALDATA's rf_type:%s, NumTotalRFPath:%d\n"
++		, rf_type_to_rfpath_str(hal_data->rf_type), hal_data->NumTotalRFPath);
++}
++
++#ifdef CONFIG_RTL8814A
++extern enum rf_type rtl8814a_rfpath_decision(_adapter *adapter);
++#endif
++
++u8 rtw_hal_rfpath_init(_adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++
++#ifdef CONFIG_RTL8814A
++if (IS_HARDWARE_TYPE_8814A(adapter)) {
++	enum bb_path tx_bmp, rx_bmp;
++	hal_data->rf_type = rtl8814a_rfpath_decision(adapter);
++	rf_type_to_default_trx_bmp(hal_data->rf_type, &tx_bmp, &rx_bmp);
++	hal_data->trx_path_bmp = (tx_bmp << 4) | rx_bmp;
++	hal_data->NumTotalRFPath = 4;
++	hal_data->max_tx_cnt = hal_spec->max_tx_cnt;
++	hal_data->max_tx_cnt = rtw_min(hal_data->max_tx_cnt, rf_type_to_rf_tx_cnt(hal_data->rf_type));
++} else
++#endif
++{
++	struct registry_priv *regsty = adapter_to_regsty(adapter);
++	u8 trx_path_bmp;
++	u8 tx_path_num;
++	u8 rx_path_num;
++	int i;
++
++	trx_path_bmp = hal_spec->rf_reg_trx_path_bmp;
++	
++	if (regsty->trx_path_bmp != 0x00) {
++		/* restrict trx_path_bmp with regsty.trx_path_bmp */
++		trx_path_bmp &= regsty->trx_path_bmp;
++		if (!trx_path_bmp) {
++			RTW_ERR("%s hal_spec.rf_reg_trx_path_bmp:0x%02x, regsty->trx_path_bmp:0x%02x no intersection\n"
++				, __func__, hal_spec->rf_reg_trx_path_bmp, regsty->trx_path_bmp);
++			return _FAIL;
++		}
++	} else if (hal_data->eeprom_trx_path_bmp != 0x00) {
++		/* restrict trx_path_bmp with eeprom_trx_path_bmp */
++		trx_path_bmp &= hal_data->eeprom_trx_path_bmp;
++		if (!trx_path_bmp) {
++			RTW_ERR("%s hal_spec.rf_reg_trx_path_bmp:0x%02x, hal_data->eeprom_trx_path_bmp:0x%02x no intersection\n"
++				, __func__, hal_spec->rf_reg_trx_path_bmp, hal_data->eeprom_trx_path_bmp);
++			return _FAIL;
++		}
++	}
++
++	/* restrict trx_path_bmp with TX and RX num limit */
++	trx_path_bmp = rtw_restrict_trx_path_bmp_by_trx_num_lmt(trx_path_bmp
++		, regsty->tx_path_lmt, regsty->rx_path_lmt, &tx_path_num, &rx_path_num);
++	if (!trx_path_bmp) {
++		RTW_ERR("%s rtw_restrict_trx_path_bmp_by_trx_num_lmt(0x%02x, %u, %u) failed\n"
++			, __func__, trx_path_bmp, regsty->tx_path_lmt, regsty->rx_path_lmt);
++		return _FAIL;
++	}
++	hal_data->trx_path_bmp = trx_path_bmp;
++	hal_data->rf_type = trx_bmp_to_rf_type((trx_path_bmp & 0xF0) >> 4, trx_path_bmp & 0x0F);
++	hal_data->NumTotalRFPath = rtw_max(tx_path_num, rx_path_num);
++
++	hal_data->max_tx_cnt = hal_spec->max_tx_cnt;
++	hal_data->max_tx_cnt = rtw_min(hal_data->max_tx_cnt, tx_path_num);
++	if (hal_data->eeprom_max_tx_cnt)
++		hal_data->max_tx_cnt = rtw_min(hal_data->max_tx_cnt, hal_data->eeprom_max_tx_cnt);
++
++	if (1)
++		_dump_rf_path(RTW_DBGDUMP, adapter);
++}
++
++	RTW_INFO("%s trx_path_bmp:0x%02x(%s), NumTotalRFPath:%u, max_tx_cnt:%u\n"
++		, __func__
++		, hal_data->trx_path_bmp
++		, rf_type_to_rfpath_str(hal_data->rf_type)
++		, hal_data->NumTotalRFPath
++		, hal_data->max_tx_cnt);
++
++	return _SUCCESS;
++}
++
++void _dump_trx_nss(void *sel, _adapter *adapter)
++{
++	struct registry_priv *regpriv = &adapter->registrypriv;
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++
++	RTW_PRINT_SEL(sel, "[TRX_Nss] HALSPEC - tx_nss:%d, rx_nss:%d\n", hal_spec->tx_nss_num, hal_spec->rx_nss_num);
++	RTW_PRINT_SEL(sel, "[TRX_Nss] Registry - tx_nss:%d, rx_nss:%d\n", regpriv->tx_nss, regpriv->rx_nss);
++	RTW_PRINT_SEL(sel, "[TRX_Nss] HALDATA - tx_nss:%d, rx_nss:%d\n", GET_HAL_TX_NSS(adapter), GET_HAL_RX_NSS(adapter));
++
++}
++#define NSS_VALID(nss) (nss > 0)
++
++u8 rtw_hal_trxnss_init(_adapter *adapter)
++{
++	struct registry_priv *regpriv = &adapter->registrypriv;
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
++	enum rf_type rf_path = GET_HAL_RFPATH(adapter);
++
++	hal_data->tx_nss = hal_spec->tx_nss_num;
++	hal_data->rx_nss = hal_spec->rx_nss_num;
++
++	if (NSS_VALID(regpriv->tx_nss))
++		hal_data->tx_nss = rtw_min(hal_data->tx_nss, regpriv->tx_nss);
++	hal_data->tx_nss = rtw_min(hal_data->tx_nss, hal_data->max_tx_cnt);
++	if (NSS_VALID(regpriv->rx_nss))
++		hal_data->rx_nss = rtw_min(hal_data->rx_nss, regpriv->rx_nss);
++	hal_data->rx_nss = rtw_min(hal_data->rx_nss, rf_type_to_rf_rx_cnt(rf_path));
++
++	if (1)
++		_dump_trx_nss(RTW_DBGDUMP, adapter);
++
++	RTW_INFO("%s tx_nss:%u, rx_nss:%u\n", __func__
++		, hal_data->tx_nss, hal_data->rx_nss);
++
++	return _SUCCESS;
++}
++
++#ifdef CONFIG_RTW_SW_LED
++void rtw_hal_sw_led_init(_adapter *padapter)
++{
++	struct led_priv *ledpriv = adapter_to_led(padapter);
++
++	if (ledpriv->bRegUseLed == _FALSE)
++		return;
++
++	if (!is_primary_adapter(padapter))
++		return;
++
++	if (padapter->hal_func.InitSwLeds) {
++		padapter->hal_func.InitSwLeds(padapter);
++		rtw_led_set_ctl_en_mask_primary(padapter);
++		rtw_led_set_iface_en(padapter, 1);
++	}
++}
++
++void rtw_hal_sw_led_deinit(_adapter *padapter)
++{
++	struct led_priv *ledpriv = adapter_to_led(padapter);
++
++	if (ledpriv->bRegUseLed == _FALSE)
++		return;
++
++	if (!is_primary_adapter(padapter))
++		return;
++
++	if (padapter->hal_func.DeInitSwLeds)
++		padapter->hal_func.DeInitSwLeds(padapter);
++}
++#endif
++
++u32 rtw_hal_power_on(_adapter *padapter)
++{
++	u32 ret = 0;
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++
++	ret = padapter->hal_func.hal_power_on(padapter);
++
++#ifdef CONFIG_BT_COEXIST
++	if ((ret == _SUCCESS) && (pHalData->EEPROMBluetoothCoexist == _TRUE))
++		rtw_btcoex_PowerOnSetting(padapter);
++#endif
++
++	return ret;
++}
++void rtw_hal_power_off(_adapter *padapter)
++{
++	struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl;
++
++	_rtw_memset(macid_ctl->h2c_msr, 0, MACID_NUM_SW_LIMIT);
++	_rtw_memset(macid_ctl->op_num, 0, H2C_MSR_ROLE_MAX);
++
++#ifdef CONFIG_LPS_1T1R
++	GET_HAL_DATA(padapter)->lps_1t1r = 0;
++#endif
++
++#ifdef CONFIG_BT_COEXIST
++	rtw_btcoex_PowerOffSetting(padapter);
++#endif
++
++	padapter->hal_func.hal_power_off(padapter);
++}
++
++
++void rtw_hal_init_opmode(_adapter *padapter)
++{
++	NDIS_802_11_NETWORK_INFRASTRUCTURE networkType = Ndis802_11InfrastructureMax;
++	struct  mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	sint fw_state;
++
++	fw_state = get_fwstate(pmlmepriv);
++
++	if (fw_state & WIFI_ADHOC_STATE)
++		networkType = Ndis802_11IBSS;
++	else if (fw_state & WIFI_STATION_STATE)
++		networkType = Ndis802_11Infrastructure;
++#ifdef CONFIG_AP_MODE
++	else if (fw_state & WIFI_AP_STATE)
++		networkType = Ndis802_11APMode;
++#endif
++#ifdef CONFIG_RTW_MESH
++	else if (fw_state & WIFI_MESH_STATE)
++		networkType = Ndis802_11_mesh;
++#endif
++	else
++		return;
++
++	rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_DIRECTLY);
++}
++
++#ifdef CONFIG_NEW_NETDEV_HDL
++uint rtw_hal_iface_init(_adapter *adapter)
++{
++	uint status = _SUCCESS;
++
++	rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(adapter));
++	#ifdef RTW_HALMAC
++	rtw_hal_hw_port_enable(adapter);
++	#endif
++	rtw_sec_restore_wep_key(adapter);
++	rtw_hal_init_opmode(adapter);
++	rtw_hal_start_thread(adapter);
++	return status;
++}
++uint rtw_hal_init(_adapter *padapter)
++{
++	uint status = _SUCCESS;
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++
++	halrf_set_rfsupportability(adapter_to_phydm(padapter));
++
++	status = padapter->hal_func.hal_init(padapter);
++
++	if(pHalData ->phydm_init_result) {
++
++		status = _FAIL;
++		RTW_ERR("%s phydm init fail reason=%u \n",
++			__func__,
++			pHalData ->phydm_init_result);
++	}
++
++	if (status == _SUCCESS) {
++		rtw_set_hw_init_completed(padapter, _TRUE);
++		if (padapter->registrypriv.notch_filter == 1)
++			rtw_hal_notch_filter(padapter, 1);
++		rtw_led_control(padapter, LED_CTL_POWER_ON);
++		init_hw_mlme_ext(padapter);
++		#ifdef CONFIG_RF_POWER_TRIM
++		rtw_bb_rf_gain_offset(padapter);
++		#endif /*CONFIG_RF_POWER_TRIM*/
++		GET_PRIMARY_ADAPTER(padapter)->bup = _TRUE; /*temporary*/
++		#ifdef CONFIG_MI_WITH_MBSSID_CAM
++		rtw_mi_set_mbid_cam(padapter);
++		#endif
++		#ifdef CONFIG_SUPPORT_MULTI_BCN
++		rtw_ap_multi_bcn_cfg(padapter);
++		#endif
++		#if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)
++		#ifdef CONFIG_DYNAMIC_SOML
++		rtw_dyn_soml_config(padapter);
++		#endif
++		#endif
++		#ifdef CONFIG_TDMADIG
++		rtw_phydm_tdmadig(padapter, TDMADIG_INIT);
++		#endif/*CONFIG_TDMADIG*/
++		rtw_phydm_dyn_rrsr_en(padapter,padapter->registrypriv.en_dyn_rrsr);
++		#ifdef RTW_HALMAC
++		RTW_INFO("%s: padapter->registrypriv.set_rrsr_value=0x%x\n", __func__,padapter->registrypriv.set_rrsr_value);
++		if(padapter->registrypriv.set_rrsr_value != 0xFFFFFFFF)
++			rtw_phydm_set_rrsr(padapter, padapter->registrypriv.set_rrsr_value, TRUE);
++		#endif
++	} else {
++		rtw_set_hw_init_completed(padapter, _FALSE);
++		RTW_ERR("%s: hal_init fail\n", __func__);
++	}
++	return status;
++}
++#else
++uint	 rtw_hal_init(_adapter *padapter)
++{
++	uint	status = _SUCCESS;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++	int i;
++
++	halrf_set_rfsupportability(adapter_to_phydm(padapter));
++
++	status = padapter->hal_func.hal_init(padapter);
++
++	if(pHalData ->phydm_init_result) {
++
++		status = _FAIL;
++		RTW_ERR("%s phydm init fail reason=%u \n",
++				__func__,
++				pHalData->phydm_init_result);
++	}
++
++	if (status == _SUCCESS) {
++		rtw_set_hw_init_completed(padapter, _TRUE);
++		rtw_mi_set_mac_addr(padapter);/*set mac addr of all ifaces*/
++		#ifdef RTW_HALMAC
++		rtw_restore_hw_port_cfg(padapter);
++		#endif
++		if (padapter->registrypriv.notch_filter == 1)
++			rtw_hal_notch_filter(padapter, 1);
++
++		for (i = 0; i < dvobj->iface_nums; i++)
++			rtw_sec_restore_wep_key(dvobj->padapters[i]);
++
++		rtw_led_control(padapter, LED_CTL_POWER_ON);
++
++		init_hw_mlme_ext(padapter);
++
++		rtw_hal_init_opmode(padapter);
++
++		#ifdef CONFIG_RF_POWER_TRIM
++		rtw_bb_rf_gain_offset(padapter);
++		#endif /*CONFIG_RF_POWER_TRIM*/
++
++		#ifdef CONFIG_SUPPORT_MULTI_BCN
++		rtw_ap_multi_bcn_cfg(padapter);
++		#endif
++
++#if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)
++#ifdef CONFIG_DYNAMIC_SOML
++		rtw_dyn_soml_config(padapter);
++#endif
++#endif
++		#ifdef CONFIG_TDMADIG
++		rtw_phydm_tdmadig(padapter, TDMADIG_INIT);
++		#endif/*CONFIG_TDMADIG*/
++
++		rtw_phydm_dyn_rrsr_en(padapter,padapter->registrypriv.en_dyn_rrsr);
++		#ifdef RTW_HALMAC
++		RTW_INFO("%s: padapter->registrypriv.set_rrsr_value=0x%x\n", __func__,padapter->registrypriv.set_rrsr_value);
++		if(padapter->registrypriv.set_rrsr_value != 0xFFFFFFFF)
++			rtw_phydm_set_rrsr(padapter, padapter->registrypriv.set_rrsr_value, TRUE);
++		#endif
++
++	} else {
++		rtw_set_hw_init_completed(padapter, _FALSE);
++		RTW_ERR("%s: fail\n", __func__);
++	}
++
++
++	return status;
++
++}
++#endif
++
++uint rtw_hal_deinit(_adapter *padapter)
++{
++	uint	status = _SUCCESS;
++
++	status = padapter->hal_func.hal_deinit(padapter);
++
++	if (status == _SUCCESS) {
++		rtw_led_control(padapter, LED_CTL_POWER_OFF);
++		rtw_set_hw_init_completed(padapter, _FALSE);
++	} else
++		RTW_INFO("\n rtw_hal_deinit: hal_init fail\n");
++
++
++	return status;
++}
++
++u8 rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val)
++{
++	return padapter->hal_func.set_hw_reg_handler(padapter, variable, val);
++}
++
++void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val)
++{
++	padapter->hal_func.GetHwRegHandler(padapter, variable, val);
++}
++
++u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue)
++{
++	return padapter->hal_func.SetHalDefVarHandler(padapter, eVariable, pValue);
++}
++u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue)
++{
++	return padapter->hal_func.get_hal_def_var_handler(padapter, eVariable, pValue);
++}
++
++void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet)
++{
++	padapter->hal_func.SetHalODMVarHandler(padapter, eVariable, pValue1, bSet);
++}
++void	rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2)
++{
++	padapter->hal_func.GetHalODMVarHandler(padapter, eVariable, pValue1, pValue2);
++}
++
++/* FOR SDIO & PCIE */
++void rtw_hal_enable_interrupt(_adapter *padapter)
++{
++#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
++	padapter->hal_func.enable_interrupt(padapter);
++#endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
++}
++
++/* FOR SDIO & PCIE */
++void rtw_hal_disable_interrupt(_adapter *padapter)
++{
++#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
++	padapter->hal_func.disable_interrupt(padapter);
++#endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
++}
++
++
++u8 rtw_hal_check_ips_status(_adapter *padapter)
++{
++	u8 val = _FALSE;
++	if (padapter->hal_func.check_ips_status)
++		val = padapter->hal_func.check_ips_status(padapter);
++	else
++		RTW_INFO("%s: hal_func.check_ips_status is NULL!\n", __FUNCTION__);
++
++	return val;
++}
++
++s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan)
++{
++	s32 ret;
++
++	ret = padapter->hal_func.fw_dl(padapter, wowlan);
++
++#ifdef CONFIG_LPS_1T1R
++	GET_HAL_DATA(padapter)->lps_1t1r = 0;
++#endif
++
++	return ret;
++}
++
++#ifdef RTW_HALMAC
++s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem)
++{
++	systime dlfw_start_time = rtw_get_current_time();
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
++	s32 rst = _FALSE;
++
++	rst = padapter->hal_func.fw_mem_dl(padapter, mem);
++	RTW_INFO("%s in %dms\n", __func__, rtw_get_passing_time_ms(dlfw_start_time));
++
++	if (rst == _FALSE)
++		pdbgpriv->dbg_fw_mem_dl_error_cnt++;
++	if (1)
++		RTW_INFO("%s dbg_fw_mem_dl_error_cnt:%d\n", __func__, pdbgpriv->dbg_fw_mem_dl_error_cnt);
++	return rst;
++}
++#endif
++
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++void rtw_hal_clear_interrupt(_adapter *padapter)
++{
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	padapter->hal_func.clear_interrupt(padapter);
++#endif
++}
++#endif
++
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
++u32	rtw_hal_inirp_init(_adapter *padapter)
++{
++	if (is_primary_adapter(padapter))
++		return padapter->hal_func.inirp_init(padapter);
++	return _SUCCESS;
++}
++u32	rtw_hal_inirp_deinit(_adapter *padapter)
++{
++
++	if (is_primary_adapter(padapter))
++		return padapter->hal_func.inirp_deinit(padapter);
++
++	return _SUCCESS;
++}
++#endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */
++
++#if defined(CONFIG_PCI_HCI)
++void	rtw_hal_irp_reset(_adapter *padapter)
++{
++	padapter->hal_func.irp_reset(GET_PRIMARY_ADAPTER(padapter));
++}
++
++void rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data)
++{
++	u16 cmd[2];
++
++	cmd[0] = addr;
++	cmd[1] = data;
++
++	padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_DBI, (u8 *) cmd);
++}
++
++u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr)
++{
++	padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_DBI, (u8 *)(&addr));
++
++	return (u8)addr;
++}
++
++void rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data)
++{
++	u16 cmd[2];
++
++	cmd[0] = (u16)addr;
++	cmd[1] = data;
++
++	padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_MDIO, (u8 *) cmd);
++}
++
++u16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr)
++{
++	padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_MDIO, &addr);
++
++	return (u8)addr;
++}
++
++u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter)
++{
++	u8 l1off;
++
++	padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_NIC_SUPPORT, &l1off);
++	return l1off;
++}
++
++u8 rtw_hal_pci_l1off_capability(_adapter *padapter)
++{
++	u8 l1off;
++
++	padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_CAPABILITY, &l1off);
++	return l1off;
++}
++
++
++#endif /* #if defined(CONFIG_PCI_HCI) */
++
++/* for USB Auto-suspend */
++u8	rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val)
++{
++	if (padapter->hal_func.interface_ps_func)
++		return padapter->hal_func.interface_ps_func(padapter, efunc_id, val);
++	return _FAIL;
++}
++
++s32	rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++	return padapter->hal_func.hal_xmitframe_enqueue(padapter, pxmitframe);
++}
++
++s32	rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++	return padapter->hal_func.hal_xmit(padapter, pxmitframe);
++}
++
++/*
++ * [IMPORTANT] This function would be run in interrupt context.
++ */
++s32	rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)
++{
++	s32 ret = _FAIL;
++
++	update_mgntframe_attrib_addr(padapter, pmgntframe);
++
++#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
++	if ((!MLME_IS_MESH(padapter) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE)
++		#ifdef CONFIG_RTW_MESH
++		|| (MLME_IS_MESH(padapter) && padapter->mesh_info.mesh_auth_id)
++		#endif
++	)
++		rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe);
++#endif
++
++	ret = padapter->hal_func.mgnt_xmit(padapter, pmgntframe);
++	return ret;
++}
++
++s32	rtw_hal_init_xmit_priv(_adapter *padapter)
++{
++	return padapter->hal_func.init_xmit_priv(padapter);
++}
++void	rtw_hal_free_xmit_priv(_adapter *padapter)
++{
++	padapter->hal_func.free_xmit_priv(padapter);
++}
++
++s32	rtw_hal_init_recv_priv(_adapter *padapter)
++{
++	return padapter->hal_func.init_recv_priv(padapter);
++}
++void	rtw_hal_free_recv_priv(_adapter *padapter)
++{
++	padapter->hal_func.free_recv_priv(padapter);
++}
++
++void rtw_sta_ra_registed(_adapter *padapter, struct sta_info *psta)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
++
++	if (psta == NULL) {
++		RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(padapter));
++		rtw_warn_on(1);
++		return;
++	}
++
++#ifdef CONFIG_AP_MODE
++	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
++		if (psta->cmn.aid > padapter->stapriv.max_aid) {
++			RTW_ERR("station aid %d exceed the max number\n", psta->cmn.aid);
++			rtw_warn_on(1);
++			return;
++		}
++		rtw_ap_update_sta_ra_info(padapter, psta);
++	}
++#endif
++
++	psta->cmn.ra_info.ra_bw_mode = rtw_get_tx_bw_mode(padapter, psta);
++	/*set correct initial date rate for each mac_id */
++	hal_data->INIDATA_RATE[psta->cmn.mac_id] = psta->init_rate;
++
++	rtw_phydm_ra_registed(padapter, psta);
++}
++
++void rtw_hal_update_ra_mask(struct sta_info *psta)
++{
++	_adapter *padapter;
++
++	if (!psta)
++		return;
++
++	padapter = psta->padapter;
++	rtw_sta_ra_registed(padapter, psta);
++}
++
++/*	Start specifical interface thread		*/
++void	rtw_hal_start_thread(_adapter *padapter)
++{
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++#ifndef CONFIG_SDIO_TX_TASKLET
++	padapter->hal_func.run_thread(padapter);
++#endif
++#endif
++}
++/*	Start specifical interface thread		*/
++void	rtw_hal_stop_thread(_adapter *padapter)
++{
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++#ifndef CONFIG_SDIO_TX_TASKLET
++
++	padapter->hal_func.cancel_thread(padapter);
++
++#endif
++#endif
++}
++
++u32	rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask)
++{
++	u32 data = 0;
++	if (padapter->hal_func.read_bbreg)
++		data = padapter->hal_func.read_bbreg(padapter, RegAddr, BitMask);
++	return data;
++}
++void	rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
++{
++	if (padapter->hal_func.write_bbreg)
++		padapter->hal_func.write_bbreg(padapter, RegAddr, BitMask, Data);
++}
++
++u32 rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask)
++{
++	u32 data = 0;
++
++	if (padapter->hal_func.read_rfreg) {
++		data = padapter->hal_func.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
++
++		#ifdef DBG_IO
++		if (match_rf_read_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {
++			RTW_INFO("DBG_IO rtw_hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\n"
++				, eRFPath, RegAddr, BitMask, (data << PHY_CalculateBitShift(BitMask)), data);
++		}
++		#endif
++	}
++
++	return data;
++}
++
++void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
++{
++	if (padapter->hal_func.write_rfreg) {
++
++		#ifdef DBG_IO
++		if (match_rf_write_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {
++			RTW_INFO("DBG_IO rtw_hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\n"
++				, eRFPath, RegAddr, BitMask, (Data << PHY_CalculateBitShift(BitMask)), Data);
++		}
++		#endif
++
++		padapter->hal_func.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);
++
++#ifdef CONFIG_PCI_HCI
++		if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(padapter)) /*For N-Series IC, suggest by Jenyu*/
++			rtw_udelay_os(2);
++#endif
++	}
++}
++
++#ifdef CONFIG_SYSON_INDIRECT_ACCESS
++u32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask)
++{
++	u32 data = 0;
++	if (padapter->hal_func.read_syson_reg)
++		data = padapter->hal_func.read_syson_reg(padapter, RegAddr, BitMask);
++
++	return data;
++}
++
++void rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
++{
++	if (padapter->hal_func.write_syson_reg)
++		padapter->hal_func.write_syson_reg(padapter, RegAddr, BitMask, Data);
++}
++#endif
++
++#if defined(CONFIG_PCI_HCI)
++s32	rtw_hal_interrupt_handler(_adapter *padapter)
++{
++	s32 ret = _FAIL;
++	ret = padapter->hal_func.interrupt_handler(padapter);
++	return ret;
++}
++
++void	rtw_hal_unmap_beacon_icf(_adapter *padapter)
++{
++	padapter->hal_func.unmap_beacon_icf(padapter);
++}
++#endif
++#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
++void	rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf)
++{
++	padapter->hal_func.interrupt_handler(padapter, pkt_len, pbuf);
++}
++#endif
++
++void	rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++	/*u8 cch_160 = Bandwidth == CHANNEL_WIDTH_160 ? channel : 0;*/
++	u8 cch_80 = Bandwidth == CHANNEL_WIDTH_80 ? channel : 0;
++	u8 cch_40 = Bandwidth == CHANNEL_WIDTH_40 ? channel : 0;
++	u8 cch_20 = Bandwidth == CHANNEL_WIDTH_20 ? channel : 0;
++
++	if (rtw_phydm_is_iqk_in_progress(padapter))
++		RTW_ERR("%s, %d, IQK may race condition\n", __func__, __LINE__);
++
++#ifdef CONFIG_MP_INCLUDED
++	/* MP mode channel don't use secondary channel */
++	if (rtw_mp_mode_check(padapter) == _FALSE)
++#endif
++	{
++		#if 0
++		if (cch_160 != 0)
++			cch_80 = rtw_get_scch_by_cch_offset(cch_160, CHANNEL_WIDTH_160, Offset80);
++		#endif
++		if (cch_80 != 0)
++			cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, Offset80);
++		if (cch_40 != 0)
++			cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, Offset40);
++	}
++
++	pHalData->cch_80 = cch_80;
++	pHalData->cch_40 = cch_40;
++	pHalData->cch_20 = cch_20;
++
++	if (0)
++		RTW_INFO("%s cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u)\n", __func__
++			, channel, ch_width_str(Bandwidth), Offset40, Offset80
++			, pHalData->cch_80, pHalData->cch_40, pHalData->cch_20);
++
++	padapter->hal_func.set_chnl_bw_handler(padapter, channel, Bandwidth, Offset40, Offset80);
++}
++
++void	rtw_hal_dm_watchdog(_adapter *padapter)
++{
++
++	rtw_hal_turbo_edca(padapter);
++	padapter->hal_func.hal_dm_watchdog(padapter);
++}
++
++#ifdef CONFIG_LPS_LCLK_WD_TIMER
++void	rtw_hal_dm_watchdog_in_lps(_adapter *padapter)
++{
++#if defined(CONFIG_CONCURRENT_MODE)
++#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
++	if (padapter->hw_port != HW_PORT0)
++		return;
++#endif
++#endif
++
++	if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE)
++		rtw_phydm_watchdog_in_lps_lclk(padapter);/* this function caller is in interrupt context */
++}
++#endif /*CONFIG_LPS_LCLK_WD_TIMER*/
++
++void rtw_hal_bcn_related_reg_setting(_adapter *padapter)
++{
++	padapter->hal_func.SetBeaconRelatedRegistersHandler(padapter);
++}
++
++#ifdef CONFIG_HOSTAPD_MLME
++s32	rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
++{
++	if (padapter->hal_func.hostap_mgnt_xmit_entry)
++		return padapter->hal_func.hostap_mgnt_xmit_entry(padapter, pkt);
++	return _FAIL;
++}
++#endif /* CONFIG_HOSTAPD_MLME */
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++void	rtw_hal_sreset_init(_adapter *padapter)
++{
++	padapter->hal_func.sreset_init_value(padapter);
++}
++void rtw_hal_sreset_reset(_adapter *padapter)
++{
++	padapter = GET_PRIMARY_ADAPTER(padapter);
++	padapter->hal_func.silentreset(padapter);
++}
++
++void rtw_hal_sreset_reset_value(_adapter *padapter)
++{
++	padapter->hal_func.sreset_reset_value(padapter);
++}
++
++void rtw_hal_sreset_xmit_status_check(_adapter *padapter)
++{
++	padapter->hal_func.sreset_xmit_status_check(padapter);
++}
++void rtw_hal_sreset_linked_status_check(_adapter *padapter)
++{
++	padapter->hal_func.sreset_linked_status_check(padapter);
++}
++u8   rtw_hal_sreset_get_wifi_status(_adapter *padapter)
++{
++	return padapter->hal_func.sreset_get_wifi_status(padapter);
++}
++
++bool rtw_hal_sreset_inprogress(_adapter *padapter)
++{
++	padapter = GET_PRIMARY_ADAPTER(padapter);
++	return padapter->hal_func.sreset_inprogress(padapter);
++}
++#endif /* DBG_CONFIG_ERROR_DETECT */
++
++#ifdef CONFIG_IOL
++int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_waiting_ms, u32 bndy_cnt)
++{
++	if (adapter->hal_func.IOL_exec_cmds_sync)
++		return adapter->hal_func.IOL_exec_cmds_sync(adapter, xmit_frame, max_waiting_ms, bndy_cnt);
++	return _FAIL;
++}
++#endif
++
++#ifdef CONFIG_XMIT_THREAD_MODE
++s32 rtw_hal_xmit_thread_handler(_adapter *padapter)
++{
++	return padapter->hal_func.xmit_thread_handler(padapter);
++}
++#endif
++
++#ifdef CONFIG_RECV_THREAD_MODE
++s32 rtw_hal_recv_hdl(_adapter *adapter)
++{
++	return adapter->hal_func.recv_hdl(adapter);
++}
++#endif
++
++void rtw_hal_notch_filter(_adapter *adapter, bool enable)
++{
++	if (adapter->hal_func.hal_notch_filter)
++		adapter->hal_func.hal_notch_filter(adapter, enable);
++}
++
++#ifdef CONFIG_FW_C2H_REG
++inline bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf)
++{
++	HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
++	bool ret = _FAIL;
++
++	ret = C2H_ID_88XX(buf) || C2H_PLEN_88XX(buf);
++
++	return ret;
++}
++
++inline s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf)
++{
++	HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
++	s32 ret = _FAIL;
++
++	ret = c2h_evt_read_88xx(adapter, buf);
++
++	return ret;
++}
++
++bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload)
++{
++	HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
++	bool ret = _FAIL;
++
++	*id = C2H_ID_88XX(buf);
++	*seq = C2H_SEQ_88XX(buf);
++	*plen = C2H_PLEN_88XX(buf);
++	*payload = C2H_PAYLOAD_88XX(buf);
++	ret = _SUCCESS;
++
++	return ret;
++}
++#endif /* CONFIG_FW_C2H_REG */
++
++#ifdef CONFIG_FW_C2H_PKT
++bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload)
++{
++	HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
++	bool ret = _FAIL;
++
++	if (!buf || len > 256 || len < 3)
++		goto exit;
++
++	*id = C2H_ID_88XX(buf);
++	*seq = C2H_SEQ_88XX(buf);
++	*plen = len - 2;
++	*payload = C2H_PAYLOAD_88XX(buf);
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++#endif /* CONFIG_FW_C2H_PKT */
++
++#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
++#include <rtw_bt_mp.h> /* for MPTBT_FwC2hBtMpCtrl */
++#endif
++s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
++{
++	u8 sub_id = 0;
++	s32 ret = _SUCCESS;
++
++	switch (id) {
++	case C2H_FW_SCAN_COMPLETE:
++		RTW_INFO("[C2H], FW Scan Complete\n");
++		break;
++
++#ifdef CONFIG_BT_COEXIST
++	case C2H_BT_INFO:
++		rtw_btcoex_BtInfoNotify(adapter, plen, payload);
++		break;
++	case C2H_BT_MP_INFO:
++		#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
++		MPTBT_FwC2hBtMpCtrl(adapter, payload, plen);
++		#endif
++		rtw_btcoex_BtMpRptNotify(adapter, plen, payload);
++		break;
++	case C2H_MAILBOX_STATUS:
++		RTW_DBG_DUMP("C2H_MAILBOX_STATUS: ", payload, plen);
++		break;
++	case C2H_WLAN_INFO:
++		rtw_btcoex_WlFwDbgInfoNotify(adapter, payload, plen);
++		break;
++#endif /* CONFIG_BT_COEXIST */
++
++	case C2H_IQK_FINISH:
++		c2h_iqk_offload(adapter, payload, plen);
++		break;
++
++#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
++	case C2H_FW_CHNL_SWITCH_COMPLETE:
++		rtw_tdls_chsw_oper_done(adapter);
++		break;
++	case C2H_BCN_EARLY_RPT:
++		rtw_tdls_ch_sw_back_to_base_chnl(adapter);
++		break;
++#endif
++
++#ifdef CONFIG_MCC_MODE
++	case C2H_MCC:
++		rtw_hal_mcc_c2h_handler(adapter, plen, payload);
++		break;
++#endif
++
++#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
++	case C2H_MAC_HIDDEN_RPT:
++		c2h_mac_hidden_rpt_hdl(adapter, payload, plen);
++		break;
++	case C2H_MAC_HIDDEN_RPT_2:
++		c2h_mac_hidden_rpt_2_hdl(adapter, payload, plen);
++		break;
++#endif
++
++	case C2H_DEFEATURE_DBG:
++		c2h_defeature_dbg_hdl(adapter, payload, plen);
++		break;
++
++#ifdef CONFIG_RTW_CUSTOMER_STR
++	case C2H_CUSTOMER_STR_RPT:
++		c2h_customer_str_rpt_hdl(adapter, payload, plen);
++		break;
++	case C2H_CUSTOMER_STR_RPT_2:
++		c2h_customer_str_rpt_2_hdl(adapter, payload, plen);
++		break;
++#endif
++#ifdef RTW_PER_CMD_SUPPORT_FW
++	case C2H_PER_RATE_RPT:
++		c2h_per_rate_rpt_hdl(adapter, payload, plen);
++		break;
++#endif
++#ifdef CONFIG_LPS_ACK
++	case C2H_LPS_STATUS_RPT:
++		c2h_lps_status_rpt(adapter, payload, plen);
++		break;
++#endif	
++#ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
++	case C2H_SET_TXPWR_FINISH:
++		c2h_txpwr_idx_offload_done(adapter, payload, plen);
++		break;
++#endif
++	case C2H_EXTEND:
++		sub_id = payload[0];
++		/* no handle, goto default */
++
++	default:
++		if (phydm_c2H_content_parsing(adapter_to_phydm(adapter), id, plen, payload) != TRUE)
++			ret = _FAIL;
++		break;
++	}
++
++	if (ret != _SUCCESS) {
++		if (id == C2H_EXTEND)
++			RTW_WARN("%s: unknown C2H(0x%02x, 0x%02x)\n", __func__, id, sub_id);
++		else
++			RTW_WARN("%s: unknown C2H(0x%02x)\n", __func__, id);
++	}
++
++	return ret;
++}
++
++#ifndef RTW_HALMAC
++s32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
++{
++	s32 ret = _FAIL;
++
++	ret = adapter->hal_func.c2h_handler(adapter, id, seq, plen, payload);
++	if (ret != _SUCCESS)
++		ret = c2h_handler(adapter, id, seq, plen, payload);
++
++	return ret;
++}
++
++s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
++{
++	switch (id) {
++	case C2H_CCX_TX_RPT:
++	case C2H_BT_MP_INFO:
++	case C2H_FW_CHNL_SWITCH_COMPLETE:
++	case C2H_IQK_FINISH:
++	case C2H_MCC:
++	case C2H_BCN_EARLY_RPT:
++	case C2H_AP_REQ_TXRPT:
++	case C2H_SPC_STAT:
++	case C2H_SET_TXPWR_FINISH:
++		return _TRUE;
++	default:
++		return _FALSE;
++	}
++}
++#endif /* !RTW_HALMAC */
++
++s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter)
++{
++	return GET_HAL_DATA(padapter)->bDisableSWChannelPlan;
++}
++
++#ifdef CONFIG_PROTSEL_MACSLEEP
++static s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep)
++{
++	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
++	u16 reg_sleep_info = macid_ctl->reg_sleep_info;
++	u16 reg_sleep_ctrl = macid_ctl->reg_sleep_ctrl;
++	const u32 sel_mask_sel = BIT(0) | BIT(1) | BIT(2);
++	u8 bit_shift;
++	u32 val32;
++	s32 ret = _FAIL;
++
++	if (macid >= macid_ctl->num) {
++		RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
++			, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" , macid);
++		goto exit;
++	}
++
++	if (macid < 32) {
++		bit_shift = macid;
++	#if (MACID_NUM_SW_LIMIT > 32)
++	} else if (macid < 64) {
++		bit_shift = macid - 32;
++	#endif
++	#if (MACID_NUM_SW_LIMIT > 64)
++	} else if (macid < 96) {
++		bit_shift = macid - 64;
++	#endif
++	#if (MACID_NUM_SW_LIMIT > 96)
++	} else if (macid < 128) {
++		bit_shift = macid - 96;
++	#endif
++	} else {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (!reg_sleep_ctrl || !reg_sleep_info) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	val32 = rtw_read32(adapter, reg_sleep_ctrl);
++	val32 = (val32 &~sel_mask_sel) | ((macid / 32) & sel_mask_sel);
++	rtw_write32(adapter, reg_sleep_ctrl, val32);
++
++	val32 = rtw_read32(adapter, reg_sleep_info);
++	RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
++		, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
++		, macid, reg_sleep_info, val32);
++
++	ret = _SUCCESS;
++
++	if (sleep) {
++		if (val32 & BIT(bit_shift))
++			goto exit;
++		val32 |= BIT(bit_shift);
++	} else {
++		if (!(val32 & BIT(bit_shift)))
++			goto exit;
++		val32 &= ~BIT(bit_shift);
++	}
++
++	rtw_write32(adapter, reg_sleep_info, val32);
++
++exit:
++	return ret;
++}
++#else
++static s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep)
++{
++	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
++	u16 reg_sleep;
++	u8 bit_shift;
++	u32 val32;
++	s32 ret = _FAIL;
++
++	if (macid >= macid_ctl->num) {
++		RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
++			, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" , macid);
++		goto exit;
++	}
++
++	if (macid < 32) {
++		reg_sleep = macid_ctl->reg_sleep_m0;
++		bit_shift = macid;
++	#if (MACID_NUM_SW_LIMIT > 32)
++	} else if (macid < 64) {
++		reg_sleep = macid_ctl->reg_sleep_m1;
++		bit_shift = macid - 32;
++	#endif
++	#if (MACID_NUM_SW_LIMIT > 64)
++	} else if (macid < 96) {
++		reg_sleep = macid_ctl->reg_sleep_m2;
++		bit_shift = macid - 64;
++	#endif
++	#if (MACID_NUM_SW_LIMIT > 96)
++	} else if (macid < 128) {
++		reg_sleep = macid_ctl->reg_sleep_m3;
++		bit_shift = macid - 96;
++	#endif
++	} else {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (!reg_sleep) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	val32 = rtw_read32(adapter, reg_sleep);
++	RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
++		, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
++		, macid, reg_sleep, val32);
++
++	ret = _SUCCESS;
++
++	if (sleep) {
++		if (val32 & BIT(bit_shift))
++			goto exit;
++		val32 |= BIT(bit_shift);
++	} else {
++		if (!(val32 & BIT(bit_shift)))
++			goto exit;
++		val32 &= ~BIT(bit_shift);
++	}
++
++	rtw_write32(adapter, reg_sleep, val32);
++
++exit:
++	return ret;
++}
++#endif
++
++inline s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid)
++{
++	return _rtw_hal_macid_sleep(adapter, macid, 1);
++}
++
++inline s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid)
++{
++	return _rtw_hal_macid_sleep(adapter, macid, 0);
++}
++
++#ifdef CONFIG_PROTSEL_MACSLEEP
++static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8 sleep)
++{
++	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
++	u16 reg_sleep_info = macid_ctl->reg_sleep_info;
++	u16 reg_sleep_ctrl = macid_ctl->reg_sleep_ctrl;
++	const u32 sel_mask_sel = BIT(0) | BIT(1) | BIT(2);
++	u32 m;
++	u8 mid = 0;
++	u32 val32;
++
++	do {
++		if (mid == 0) {
++			m = bmp->m0;
++		#if (MACID_NUM_SW_LIMIT > 32)
++		} else if (mid == 1) {
++			m = bmp->m1;
++		#endif
++		#if (MACID_NUM_SW_LIMIT > 64)
++		} else if (mid == 2) {
++			m = bmp->m2;
++		#endif
++		#if (MACID_NUM_SW_LIMIT > 96)
++		} else if (mid == 3) {
++			m = bmp->m3;
++		#endif
++		} else {
++			rtw_warn_on(1);
++			break;
++		}
++
++		if (m == 0)
++			goto move_next;
++
++		if (!reg_sleep_ctrl || !reg_sleep_info) {
++			rtw_warn_on(1);
++			break;
++		}
++
++		val32 = rtw_read32(adapter, reg_sleep_ctrl);
++		val32 = (val32 &~sel_mask_sel) | (mid & sel_mask_sel);
++		rtw_write32(adapter, reg_sleep_ctrl, val32);
++
++		val32 = rtw_read32(adapter, reg_sleep_info);
++		RTW_INFO(ADPT_FMT" %s m%u=0x%08x, ori reg_0x%03x=0x%08x\n"
++			, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
++			, mid, m, reg_sleep_info, val32);
++
++		if (sleep) {
++			if ((val32 & m) == m)
++				goto move_next;
++			val32 |= m;
++		} else {
++			if ((val32 & m) == 0)
++				goto move_next;
++			val32 &= ~m;
++		}
++
++		rtw_write32(adapter, reg_sleep_info, val32);
++
++move_next:
++		mid++;
++	} while (mid * 32 < MACID_NUM_SW_LIMIT);
++
++	return _SUCCESS;
++}
++#else
++static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8 sleep)
++{
++	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
++	u16 reg_sleep;
++	u32 m;
++	u8 mid = 0;
++	u32 val32;
++
++	do {
++		if (mid == 0) {
++			m = bmp->m0;
++			reg_sleep = macid_ctl->reg_sleep_m0;
++		#if (MACID_NUM_SW_LIMIT > 32)
++		} else if (mid == 1) {
++			m = bmp->m1;
++			reg_sleep = macid_ctl->reg_sleep_m1;
++		#endif
++		#if (MACID_NUM_SW_LIMIT > 64)
++		} else if (mid == 2) {
++			m = bmp->m2;
++			reg_sleep = macid_ctl->reg_sleep_m2;
++		#endif
++		#if (MACID_NUM_SW_LIMIT > 96)
++		} else if (mid == 3) {
++			m = bmp->m3;
++			reg_sleep = macid_ctl->reg_sleep_m3;
++		#endif
++		} else {
++			rtw_warn_on(1);
++			break;
++		}
++
++		if (m == 0)
++			goto move_next;
++
++		if (!reg_sleep) {
++			rtw_warn_on(1);
++			break;
++		}
++
++		val32 = rtw_read32(adapter, reg_sleep);
++		RTW_INFO(ADPT_FMT" %s m%u=0x%08x, ori reg_0x%03x=0x%08x\n"
++			, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
++			, mid, m, reg_sleep, val32);
++
++		if (sleep) {
++			if ((val32 & m) == m)
++				goto move_next;
++			val32 |= m;
++		} else {
++			if ((val32 & m) == 0)
++				goto move_next;
++			val32 &= ~m;
++		}
++
++		rtw_write32(adapter, reg_sleep, val32);
++
++move_next:
++		mid++;
++	} while (mid * 32 < MACID_NUM_SW_LIMIT);
++
++	return _SUCCESS;
++}
++#endif
++
++inline s32 rtw_hal_macid_sleep_all_used(_adapter *adapter)
++{
++	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
++
++	return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 1);
++}
++
++inline s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter)
++{
++	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
++
++	return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 0);
++}
++static s32 _rtw_hal_macid_drop(_adapter *adapter, u8 macid, u8 drop)
++{
++	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
++#ifndef CONFIG_PROTSEL_MACSLEEP
++	u16 reg_drop = 0;
++#else
++	u16 reg_drop_info = macid_ctl->reg_drop_info;
++	u16 reg_drop_ctrl = macid_ctl->reg_drop_ctrl;
++	const u32 sel_mask_sel = BIT(0) | BIT(1) | BIT(2);
++#endif /* CONFIG_PROTSEL_MACSLEEP */
++	u8 bit_shift;
++	u32 val32;
++	s32 ret = _FAIL;
++/* some IC doesn't have this register */
++#ifndef REG_PKT_BUFF_ACCESS_CTRL
++#define REG_PKT_BUFF_ACCESS_CTRL 0
++#endif
++
++	if (macid >= macid_ctl->num) {
++		RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
++			, ADPT_ARG(adapter), drop ? "drop" : "undrop" , macid);
++		goto exit;
++	}
++	
++	if(_rtw_macid_ctl_chk_cap(adapter, MACID_DROP)) {
++		if (macid < 32) {
++#ifndef CONFIG_PROTSEL_MACSLEEP
++			reg_drop = macid_ctl->reg_drop_m0;
++#endif /* CONFIG_PROTSEL_MACSLEEP */
++			bit_shift = macid;
++		#if (MACID_NUM_SW_LIMIT > 32)
++		} else if (macid < 64) {
++#ifndef CONFIG_PROTSEL_MACSLEEP
++			reg_drop = macid_ctl->reg_drop_m1;
++#endif /* CONFIG_PROTSEL_MACSLEEP */
++			bit_shift = macid - 32;
++		#endif
++		#if (MACID_NUM_SW_LIMIT > 64)
++		} else if (macid < 96) {
++#ifndef CONFIG_PROTSEL_MACSLEEP
++			reg_drop = macid_ctl->reg_drop_m2;
++#endif /* CONFIG_PROTSEL_MACSLEEP */
++			bit_shift = macid - 64;
++		#endif
++		#if (MACID_NUM_SW_LIMIT > 96)
++		} else if (macid < 128) {
++#ifndef CONFIG_PROTSEL_MACSLEEP
++			reg_drop = macid_ctl->reg_drop_m3;
++#endif /* CONFIG_PROTSEL_MACSLEEP */
++			bit_shift = macid - 96;
++		#endif
++		} else {
++			rtw_warn_on(1);
++			goto exit;
++		}
++
++#ifndef CONFIG_PROTSEL_MACSLEEP
++		if (!reg_drop) {
++			rtw_warn_on(1);
++			goto exit;
++		}
++		val32 = rtw_read32(adapter, reg_drop);
++		/*RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x \n"
++			, ADPT_ARG(adapter), drop ? "drop" : "undrop"
++			, macid, reg_drop, val32);*/
++#else
++		if (!reg_drop_ctrl || !reg_drop_info) {
++			rtw_warn_on(1);
++			goto exit;
++		}
++
++		val32 = rtw_read32(adapter, reg_drop_ctrl);
++		val32 = (val32 &~sel_mask_sel) | ((macid / 32) & sel_mask_sel);
++		rtw_write32(adapter, reg_drop_ctrl, val32);
++
++		val32 = rtw_read32(adapter, reg_drop_info);
++		/*RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
++			, ADPT_ARG(adapter), drop ? "drop" : "undrop"
++			, macid, reg_drop_info, val32);*/
++#endif /* CONFIG_PROTSEL_MACSLEEP */
++		ret = _SUCCESS;
++
++		if (drop) {
++			if (val32 & BIT(bit_shift))
++				goto exit;
++			val32 |= BIT(bit_shift);
++		} else {
++			if (!(val32 & BIT(bit_shift)))
++				goto exit;
++			val32 &= ~BIT(bit_shift);
++		}
++
++#ifndef CONFIG_PROTSEL_MACSLEEP
++		rtw_write32(adapter, reg_drop, val32);
++		RTW_INFO(ADPT_FMT" %s macid=%d, done reg_0x%03x=0x%08x\n"
++			, ADPT_ARG(adapter), drop ? "drop" : "undrop"
++			, macid, reg_drop, val32);
++#else
++		rtw_write32(adapter, reg_drop_info, val32);
++		RTW_INFO(ADPT_FMT" %s macid=%d, done reg_0x%03x=0x%08x\n"
++			, ADPT_ARG(adapter), drop ? "drop" : "undrop"
++			, macid, reg_drop_info, val32);
++#endif /* CONFIG_PROTSEL_MACSLEEP */
++		
++		
++	} else if(_rtw_macid_ctl_chk_cap(adapter, MACID_DROP_INDIRECT)) {
++		u16 start_addr = macid_ctl->macid_txrpt/8;
++		u32 txrpt_h4b = 0;
++		u8 i;
++		
++		/* each address means 1 byte */
++		start_addr += macid*(macid_ctl->macid_txrpt_pgsz/8);
++		/* select tx report buffer */
++		rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXREPORT_BUF_SELECT);
++		/* set tx report buffer start address for reading */
++		rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, start_addr);
++		txrpt_h4b = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
++		/* OFFSET5 BIT2 is BIT10 of high 4 bytes */
++		if (drop) {
++			if (txrpt_h4b & BIT(10))
++				goto exit;
++			txrpt_h4b |= BIT(10);
++		} else {
++			if (!(txrpt_h4b & BIT(10)))
++				goto exit;
++			txrpt_h4b &= ~BIT(10);
++		}
++		/* set to macid drop field */
++		rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, txrpt_h4b);
++		/* 0x20800000 only write BIT10 of tx report buf */
++		rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, 0x20800000 | start_addr);
++#if 0 /* some ICs doesn't clear the write done bit */
++		/* checking TX queue status */
++		for (i = 0 ; i < 50 ; i++) {
++			txrpt_h4b = rtw_read32(adapter, REG_PKTBUF_DBG_CTRL);
++			if (txrpt_h4b & BIT(23)) {
++				RTW_INFO("%s: wait to write TX RTP buf (%d)!\n", __func__, i);
++				rtw_mdelay_os(10);
++			} else {
++				RTW_INFO("%s: wait to write TX RTP buf done (%d)!\n", __func__, i);
++				break;
++			}
++		}
++#endif
++		rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, start_addr);
++		RTW_INFO("start_addr=%x, data_H:%08x, data_L:%08x, macid=%d, txrpt_h4b=%x\n", start_addr
++		,rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H), rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L), macid, txrpt_h4b);
++	} else {
++		RTW_INFO("There is no definition for camctl cap , please correct it\n");
++	}
++exit:
++	return ret;
++}
++
++inline s32 rtw_hal_macid_drop(_adapter *adapter, u8 macid)
++{
++	return _rtw_hal_macid_drop(adapter, macid, 1);
++}
++
++inline s32 rtw_hal_macid_undrop(_adapter *adapter, u8 macid)
++{
++	return _rtw_hal_macid_drop(adapter, macid, 0);
++}
++
++
++s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
++{
++	_adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter);
++
++	if (GET_HAL_DATA(pri_adapter)->bFWReady == _TRUE)
++		return padapter->hal_func.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer);
++	else if (padapter->registrypriv.mp_mode == 0)
++		RTW_PRINT(FUNC_ADPT_FMT" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\n"
++			  , FUNC_ADPT_ARG(padapter), ElementID);
++	return _FAIL;
++}
++
++void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen,
++			      u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame)
++{
++	padapter->hal_func.fill_fake_txdesc(padapter, pDesc, BufferLen, IsPsPoll, IsBTQosNull, bDataFrame);
++
++}
++
++u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan)
++{
++	u8 num = 0;
++
++
++	if (adapter->hal_func.hal_get_tx_buff_rsvd_page_num) {
++		num = adapter->hal_func.hal_get_tx_buff_rsvd_page_num(adapter, wowlan);
++	} else {
++#ifdef RTW_HALMAC
++		num = GET_HAL_DATA(adapter)->drv_rsvd_page_number;
++#endif /* RTW_HALMAC */
++	}
++
++	return num;
++}
++
++#ifdef CONFIG_GPIO_API
++void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag)
++{
++	if (padapter->hal_func.update_hisr_hsisr_ind)
++		padapter->hal_func.update_hisr_hsisr_ind(padapter, flag);
++}
++
++int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num)
++{
++	int ret = _SUCCESS;
++
++	if (padapter->hal_func.hal_gpio_func_check)
++		ret = padapter->hal_func.hal_gpio_func_check(padapter, gpio_num);
++
++	return ret;
++}
++
++void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num)
++{
++	if (padapter->hal_func.hal_gpio_multi_func_reset)
++		padapter->hal_func.hal_gpio_multi_func_reset(padapter, gpio_num);
++}
++#endif
++
++#ifdef CONFIG_FW_CORRECT_BCN
++void rtw_hal_fw_correct_bcn(_adapter *padapter)
++{
++	if (padapter->hal_func.fw_correct_bcn)
++		padapter->hal_func.fw_correct_bcn(padapter);
++}
++#endif
++
++void rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++
++	if (phy_chk_ch_setting_consistency(adapter, channel) != _SUCCESS)
++		return;
++
++	hal_data->set_entire_txpwr = 1;
++
++	adapter->hal_func.set_tx_power_level_handler(adapter, channel);
++	rtw_hal_set_txpwr_done(adapter);
++
++	hal_data->set_entire_txpwr = 0;
++}
++
++void rtw_hal_update_txpwr_level(_adapter *adapter)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++
++	rtw_hal_set_tx_power_level(adapter, hal_data->current_channel);
++}
++
++void rtw_hal_set_txpwr_done(_adapter *adapter)
++{
++	if (adapter->hal_func.set_txpwr_done)
++		adapter->hal_func.set_txpwr_done(adapter);
++}
++
++void rtw_hal_set_tx_power_index(_adapter *adapter, u32 powerindex
++	, enum rf_path rfpath, u8 rate)
++{
++	adapter->hal_func.set_tx_power_index_handler(adapter, powerindex, rfpath, rate);
++}
++
++u8 rtw_hal_get_tx_power_index(_adapter *adapter, enum rf_path rfpath
++	, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch
++	, struct txpwr_idx_comp *tic)
++{
++	return adapter->hal_func.get_tx_power_index_handler(adapter, rfpath
++		, rs, rate, bw, band, cch, opch, tic);
++}
++
++s8 rtw_hal_get_txpwr_target_extra_bias(_adapter *adapter, enum rf_path rfpath
++	, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch)
++{
++	s8 val = 0;
++
++	if (adapter->hal_func.get_txpwr_target_extra_bias) {
++		val = adapter->hal_func.get_txpwr_target_extra_bias(adapter
++				, rfpath, rs, rate, bw, band, cch);
++	}
++
++	return val;
++}
++
++#ifdef RTW_HALMAC
++/*
++ * Description:
++ *	Initialize MAC registers
++ *
++ * Return:
++ *	_TRUE	success
++ *	_FALSE	fail
++ */
++u8 rtw_hal_init_mac_register(PADAPTER adapter)
++{
++	return adapter->hal_func.init_mac_register(adapter);
++}
++
++/*
++ * Description:
++ *	Initialize PHY(BB/RF) related functions
++ *
++ * Return:
++ *	_TRUE	success
++ *	_FALSE	fail
++ */
++u8 rtw_hal_init_phy(PADAPTER adapter)
++{
++	return adapter->hal_func.init_phy(adapter);
++}
++#endif /* RTW_HALMAC */
++
++#ifdef CONFIG_RFKILL_POLL
++bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid)
++{
++	bool ret;
++
++	if (adapter->hal_func.hal_radio_onoff_check)
++		ret = adapter->hal_func.hal_radio_onoff_check(adapter, valid);
++	else {
++		*valid = 0;
++		ret = _FALSE;
++	}
++	return ret;
++}
++#endif
++
++#define rtw_hal_error_msg(ops_fun)		\
++	RTW_PRINT("### %s - Error : Please hook hal_func.%s ###\n", __FUNCTION__, ops_fun)
++
++u8 rtw_hal_ops_check(_adapter *padapter)
++{
++	u8 ret = _SUCCESS;
++#if 1
++	/*** initialize section ***/
++	if (NULL == padapter->hal_func.read_chip_version) {
++		rtw_hal_error_msg("read_chip_version");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.init_default_value) {
++		rtw_hal_error_msg("init_default_value");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.intf_chip_configure) {
++		rtw_hal_error_msg("intf_chip_configure");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.read_adapter_info) {
++		rtw_hal_error_msg("read_adapter_info");
++		ret = _FAIL;
++	}
++
++	if (NULL == padapter->hal_func.hal_power_on) {
++		rtw_hal_error_msg("hal_power_on");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.hal_power_off) {
++		rtw_hal_error_msg("hal_power_off");
++		ret = _FAIL;
++	}
++
++	if (NULL == padapter->hal_func.hal_init) {
++		rtw_hal_error_msg("hal_init");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.hal_deinit) {
++		rtw_hal_error_msg("hal_deinit");
++		ret = _FAIL;
++	}
++
++	/*** xmit section ***/
++	if (NULL == padapter->hal_func.init_xmit_priv) {
++		rtw_hal_error_msg("init_xmit_priv");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.free_xmit_priv) {
++		rtw_hal_error_msg("free_xmit_priv");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.hal_xmit) {
++		rtw_hal_error_msg("hal_xmit");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.mgnt_xmit) {
++		rtw_hal_error_msg("mgnt_xmit");
++		ret = _FAIL;
++	}
++#ifdef CONFIG_XMIT_THREAD_MODE
++	if (NULL == padapter->hal_func.xmit_thread_handler) {
++		rtw_hal_error_msg("xmit_thread_handler");
++		ret = _FAIL;
++	}
++#endif
++	if (NULL == padapter->hal_func.hal_xmitframe_enqueue) {
++		rtw_hal_error_msg("hal_xmitframe_enqueue");
++		ret = _FAIL;
++	}
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++#ifndef CONFIG_SDIO_TX_TASKLET
++	if (NULL == padapter->hal_func.run_thread) {
++		rtw_hal_error_msg("run_thread");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.cancel_thread) {
++		rtw_hal_error_msg("cancel_thread");
++		ret = _FAIL;
++	}
++#endif
++#endif
++
++	/*** recv section ***/
++	if (NULL == padapter->hal_func.init_recv_priv) {
++		rtw_hal_error_msg("init_recv_priv");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.free_recv_priv) {
++		rtw_hal_error_msg("free_recv_priv");
++		ret = _FAIL;
++	}
++#ifdef CONFIG_RECV_THREAD_MODE
++	if (NULL == padapter->hal_func.recv_hdl) {
++		rtw_hal_error_msg("recv_hdl");
++		ret = _FAIL;
++	}
++#endif
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
++	if (NULL == padapter->hal_func.inirp_init) {
++		rtw_hal_error_msg("inirp_init");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.inirp_deinit) {
++		rtw_hal_error_msg("inirp_deinit");
++		ret = _FAIL;
++	}
++#endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */
++
++
++	/*** interrupt hdl section ***/
++#if defined(CONFIG_PCI_HCI)
++	if (NULL == padapter->hal_func.irp_reset) {
++		rtw_hal_error_msg("irp_reset");
++		ret = _FAIL;
++	}
++#endif/*#if defined(CONFIG_PCI_HCI)*/
++#if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))
++	if (NULL == padapter->hal_func.interrupt_handler) {
++		rtw_hal_error_msg("interrupt_handler");
++		ret = _FAIL;
++	}
++#endif /*#if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))*/
++
++#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
++	if (NULL == padapter->hal_func.enable_interrupt) {
++		rtw_hal_error_msg("enable_interrupt");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.disable_interrupt) {
++		rtw_hal_error_msg("disable_interrupt");
++		ret = _FAIL;
++	}
++#endif /* defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
++
++
++	/*** DM section ***/
++	if (NULL == padapter->hal_func.dm_init) {
++		rtw_hal_error_msg("dm_init");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.dm_deinit) {
++		rtw_hal_error_msg("dm_deinit");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.hal_dm_watchdog) {
++		rtw_hal_error_msg("hal_dm_watchdog");
++		ret = _FAIL;
++	}
++
++	/*** xxx section ***/
++	if (NULL == padapter->hal_func.set_chnl_bw_handler) {
++		rtw_hal_error_msg("set_chnl_bw_handler");
++		ret = _FAIL;
++	}
++
++	if (NULL == padapter->hal_func.set_hw_reg_handler) {
++		rtw_hal_error_msg("set_hw_reg_handler");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.GetHwRegHandler) {
++		rtw_hal_error_msg("GetHwRegHandler");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.get_hal_def_var_handler) {
++		rtw_hal_error_msg("get_hal_def_var_handler");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.SetHalDefVarHandler) {
++		rtw_hal_error_msg("SetHalDefVarHandler");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.GetHalODMVarHandler) {
++		rtw_hal_error_msg("GetHalODMVarHandler");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.SetHalODMVarHandler) {
++		rtw_hal_error_msg("SetHalODMVarHandler");
++		ret = _FAIL;
++	}
++
++	if (NULL == padapter->hal_func.SetBeaconRelatedRegistersHandler) {
++		rtw_hal_error_msg("SetBeaconRelatedRegistersHandler");
++		ret = _FAIL;
++	}
++
++	if (NULL == padapter->hal_func.fill_h2c_cmd) {
++		rtw_hal_error_msg("fill_h2c_cmd");
++		ret = _FAIL;
++	}
++
++#ifdef RTW_HALMAC
++	if (NULL == padapter->hal_func.hal_mac_c2h_handler) {
++		rtw_hal_error_msg("hal_mac_c2h_handler");
++		ret = _FAIL;
++	}
++#elif !defined(CONFIG_RTL8188E)
++	if (NULL == padapter->hal_func.c2h_handler) {
++		rtw_hal_error_msg("c2h_handler");
++		ret = _FAIL;
++	}
++#endif
++
++#if defined(CONFIG_LPS) || defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++	if (NULL == padapter->hal_func.fill_fake_txdesc) {
++		rtw_hal_error_msg("fill_fake_txdesc");
++		ret = _FAIL;
++	}
++#endif
++
++#ifndef RTW_HALMAC
++	if (NULL == padapter->hal_func.hal_get_tx_buff_rsvd_page_num) {
++		rtw_hal_error_msg("hal_get_tx_buff_rsvd_page_num");
++		ret = _FAIL;
++	}
++#endif /* !RTW_HALMAC */
++
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	if (NULL == padapter->hal_func.clear_interrupt) {
++		rtw_hal_error_msg("clear_interrupt");
++		ret = _FAIL;
++	}
++#endif
++#endif /* CONFIG_WOWLAN */
++
++	if (NULL == padapter->hal_func.fw_dl) {
++		rtw_hal_error_msg("fw_dl");
++		ret = _FAIL;
++	}
++
++	#ifdef CONFIG_FW_CORRECT_BCN
++	if (IS_HARDWARE_TYPE_8814A(padapter)
++	    && NULL == padapter->hal_func.fw_correct_bcn) {
++		rtw_hal_error_msg("fw_correct_bcn");
++		ret = _FAIL;
++	}
++	#endif
++
++	if (!padapter->hal_func.set_tx_power_level_handler) {
++		rtw_hal_error_msg("set_tx_power_level_handler");
++		ret = _FAIL;
++	}
++	if (!padapter->hal_func.set_tx_power_index_handler) {
++		rtw_hal_error_msg("set_tx_power_index_handler");
++		ret = _FAIL;
++	}
++	if (!padapter->hal_func.get_tx_power_index_handler) {
++		rtw_hal_error_msg("get_tx_power_index_handler");
++		ret = _FAIL;
++	}
++
++	/*** SReset section ***/
++#ifdef DBG_CONFIG_ERROR_DETECT
++	if (NULL == padapter->hal_func.sreset_init_value) {
++		rtw_hal_error_msg("sreset_init_value");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.sreset_reset_value) {
++		rtw_hal_error_msg("sreset_reset_value");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.silentreset) {
++		rtw_hal_error_msg("silentreset");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.sreset_xmit_status_check) {
++		rtw_hal_error_msg("sreset_xmit_status_check");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.sreset_linked_status_check) {
++		rtw_hal_error_msg("sreset_linked_status_check");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.sreset_get_wifi_status) {
++		rtw_hal_error_msg("sreset_get_wifi_status");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.sreset_inprogress) {
++		rtw_hal_error_msg("sreset_inprogress");
++		ret = _FAIL;
++	}
++#endif  /* #ifdef DBG_CONFIG_ERROR_DETECT */
++
++#ifdef RTW_HALMAC
++	if (NULL == padapter->hal_func.init_mac_register) {
++		rtw_hal_error_msg("init_mac_register");
++		ret = _FAIL;
++	}
++	if (NULL == padapter->hal_func.init_phy) {
++		rtw_hal_error_msg("init_phy");
++		ret = _FAIL;
++	}
++#endif /* RTW_HALMAC */
++
++#ifdef CONFIG_RFKILL_POLL
++	if (padapter->hal_func.hal_radio_onoff_check == NULL) {
++		rtw_hal_error_msg("hal_radio_onoff_check");
++		ret = _FAIL;
++	}
++#endif
++#endif
++	return  ret;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_mcc.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_mcc.c
+new file mode 100644
+index 000000000..6fcdca7d9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_mcc.c
+@@ -0,0 +1,4048 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2015 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifdef CONFIG_MCC_MODE
++#define _HAL_MCC_C_
++
++#include <drv_types.h> /* PADAPTER */
++#include <rtw_mcc.h> /* mcc structure */
++#include <hal_data.h> /* HAL_DATA */
++#include <rtw_pwrctrl.h> /* power control */
++
++/*  use for AP/GO + STA/GC case */
++#define MCC_DURATION_IDX 0 /* druration for station side */
++#define MCC_TSF_SYNC_OFFSET_IDX 1
++#define MCC_START_TIME_OFFSET_IDX 2
++#define MCC_INTERVAL_IDX 3
++#define MCC_GUARD_OFFSET0_IDX 4
++#define MCC_GUARD_OFFSET1_IDX 5
++#define MCC_STOP_THRESHOLD 6
++#define TU 1024 /* 1 TU equals 1024 microseconds */
++/* druration, TSF sync offset, start time offset, interval (unit:TU (1024 microseconds))*/
++u8 mcc_switch_channel_policy_table[][7]={
++	{20, 50, 40, 100, 0, 0, 30},
++	{80, 50, 10, 100, 0, 0, 30},
++	{36, 50, 32, 100, 0, 0, 30},
++	{30, 50, 35, 100, 0, 0, 30},
++};
++
++const int mcc_max_policy_num = sizeof(mcc_switch_channel_policy_table) /sizeof(u8) /7;
++
++static void dump_iqk_val_table(PADAPTER padapter)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++	struct hal_iqk_reg_backup *iqk_reg_backup = pHalData->iqk_reg_backup;
++	u8 total_rf_path = hal_spec->rf_reg_path_num;
++	u8 rf_path_idx = 0;
++	u8 backup_chan_idx = 0;
++	u8 backup_reg_idx = 0;
++
++#ifdef CONFIG_MCC_MODE_V2
++#else
++
++	RTW_INFO("=============dump IQK backup table================\n");
++	for (backup_chan_idx = 0; backup_chan_idx < MAX_IQK_INFO_BACKUP_CHNL_NUM; backup_chan_idx++) {
++		for (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx++) {
++			for(backup_reg_idx = 0; backup_reg_idx < MAX_IQK_INFO_BACKUP_REG_NUM; backup_reg_idx++) {
++				RTW_INFO("ch:%d. bw:%d. rf path:%d. reg[%d] = 0x%02x \n"
++						, iqk_reg_backup[backup_chan_idx].central_chnl
++						, iqk_reg_backup[backup_chan_idx].bw_mode
++						, rf_path_idx
++						, backup_reg_idx
++						, iqk_reg_backup[backup_chan_idx].reg_backup[rf_path_idx][backup_reg_idx]
++						);
++			}
++		}
++	}	
++	RTW_INFO("=============================================\n");
++
++#endif
++}
++
++static void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_len)
++{
++	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
++	u8 p2p_noa_attr_ie[MAX_P2P_IE_LEN] = {0x00};
++	u32 p2p_noa_attr_len = 0;
++	u8 noa_desc_num = 1;
++	u8 opp_ps = 0; /* Disable OppPS */
++	u8 noa_count = 255;
++	u32 noa_duration;
++	u32 noa_interval;
++	u8 noa_index = 0;
++	u8 mcc_policy_idx = 0;
++
++	mcc_policy_idx = pmccobjpriv->policy_index;
++	noa_duration = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX] * TU;
++	noa_interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX] * TU;
++
++	/* P2P OUI(4 bytes) */
++	_rtw_memcpy(p2p_noa_attr_ie, P2P_OUI, 4);
++	p2p_noa_attr_len = p2p_noa_attr_len + 4;
++
++	/* attrute ID(1 byte) */
++	p2p_noa_attr_ie[p2p_noa_attr_len] = P2P_ATTR_NOA;
++	p2p_noa_attr_len = p2p_noa_attr_len + 1;
++	
++	/* attrute length(2 bytes) length = noa_desc_num*13 + 2 */
++	RTW_PUT_LE16(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_desc_num * 13 + 2));
++	p2p_noa_attr_len = p2p_noa_attr_len + 2;
++
++	/* Index (1 byte) */
++	p2p_noa_attr_ie[p2p_noa_attr_len] = noa_index;
++	p2p_noa_attr_len = p2p_noa_attr_len + 1;
++
++	/* CTWindow and OppPS Parameters (1 byte) */
++	p2p_noa_attr_ie[p2p_noa_attr_len] = opp_ps;
++	p2p_noa_attr_len = p2p_noa_attr_len+ 1;
++
++	/* NoA Count (1 byte) */
++	p2p_noa_attr_ie[p2p_noa_attr_len] = noa_count;
++	p2p_noa_attr_len = p2p_noa_attr_len + 1;
++
++	/* NoA Duration (4 bytes) unit: microseconds */
++	RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_duration);
++	p2p_noa_attr_len = p2p_noa_attr_len + 4;
++
++	/* NoA Interval (4 bytes) unit: microseconds */
++	RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_interval);
++	p2p_noa_attr_len = p2p_noa_attr_len + 4;
++
++	/* NoA Start Time (4 bytes) unit: microseconds */
++	RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, pmccadapriv->noa_start_time);
++	if (0)
++		RTW_INFO("indxe:%d, start_time=0x%02x:0x%02x:0x%02x:0x%02x\n"
++		, noa_index
++		, p2p_noa_attr_ie[p2p_noa_attr_len]
++		, p2p_noa_attr_ie[p2p_noa_attr_len + 1]
++		, p2p_noa_attr_ie[p2p_noa_attr_len + 2]
++		, p2p_noa_attr_ie[p2p_noa_attr_len + 3]);
++
++	p2p_noa_attr_len = p2p_noa_attr_len + 4;
++	rtw_set_ie(ie, _VENDOR_SPECIFIC_IE_, p2p_noa_attr_len, (u8 *)p2p_noa_attr_ie, ie_len);
++}
++
++
++/**
++ * rtw_hal_mcc_update_go_p2p_ie - update go p2p ie(add NoA attribute)
++ * @padapter: the adapter to be update go p2p ie
++ */
++static void rtw_hal_mcc_update_go_p2p_ie(PADAPTER padapter)
++{
++	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
++	struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
++	u8 *pos = NULL;
++
++
++	/* no noa attribute, build it */
++	if (pmccadapriv->p2p_go_noa_ie_len == 0)
++		rtw_hal_mcc_build_p2p_noa_attr(padapter, pmccadapriv->p2p_go_noa_ie, &pmccadapriv->p2p_go_noa_ie_len);
++	else {
++		/* has noa attribut, modify it */
++		u32 noa_duration = 0;
++		
++		/* update index */
++		pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 15;
++		/* 0~255 */
++		(*pos) = ((*pos) + 1) % 256;
++		if (0)
++			RTW_INFO("indxe:%d\n", (*pos));
++
++
++		/* update duration */
++		noa_duration = mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX] * TU;
++		pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 12;
++		RTW_PUT_LE32(pos, noa_duration);
++
++		/* update start time */
++		pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 4;
++		RTW_PUT_LE32(pos, pmccadapriv->noa_start_time);
++		if (0)
++			RTW_INFO("start_time=0x%02x:0x%02x:0x%02x:0x%02x\n"
++			, ((u8*)(pos))[0]
++			, ((u8*)(pos))[1]
++			, ((u8*)(pos))[2]
++			, ((u8*)(pos))[3]);
++
++	}
++
++	if (0) {
++		RTW_INFO("p2p_go_noa_ie_len:%d\n", pmccadapriv->p2p_go_noa_ie_len);
++		RTW_INFO_DUMP("\n", pmccadapriv->p2p_go_noa_ie, pmccadapriv->p2p_go_noa_ie_len);
++	}
++	update_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE, 0);
++}
++
++/**
++ * rtw_hal_mcc_remove_go_p2p_ie - remove go p2p ie(add NoA attribute)
++ * @padapter: the adapter to be update go p2p ie
++ */
++static void rtw_hal_mcc_remove_go_p2p_ie(PADAPTER padapter)
++{
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
++
++	/* chech has noa ie or not */
++	if (pmccadapriv->p2p_go_noa_ie_len == 0)
++		return;
++
++	pmccadapriv->p2p_go_noa_ie_len = 0;
++	update_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE, 0);
++}
++
++/* restore IQK value for all interface */
++void rtw_hal_mcc_restore_iqk_val(PADAPTER padapter)
++{
++	u8 take_care_iqk = _FALSE;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	_adapter *iface = NULL;
++	struct mcc_adapter_priv *mccadapriv = NULL;
++	u8 i = 0;
++
++	rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
++	if (take_care_iqk == _TRUE && MCC_EN(padapter)) {
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			iface = dvobj->padapters[i];
++			if (iface == NULL)
++				continue;
++
++			mccadapriv = &iface->mcc_adapterpriv;
++			if (mccadapriv->role == MCC_ROLE_MAX)
++				continue;
++
++			rtw_hal_ch_sw_iqk_info_restore(iface, CH_SW_USE_CASE_MCC);
++		}
++	}
++
++	if (0)
++		dump_iqk_val_table(padapter);
++}
++
++u8 rtw_hal_check_mcc_status(PADAPTER padapter, u8 mcc_status)
++{
++	struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
++
++	if (pmccobjpriv->mcc_status & (mcc_status))
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++void rtw_hal_set_mcc_status(PADAPTER padapter, u8 mcc_status)
++{
++	struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
++
++	pmccobjpriv->mcc_status |= (mcc_status);
++}
++
++void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status)
++{
++	struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
++
++	pmccobjpriv->mcc_status &= (~mcc_status);
++}
++
++static void rtw_hal_mcc_update_policy_table(PADAPTER adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
++	u8 mcc_duration = mccobjpriv->duration;
++	s8 mcc_policy_idx = mccobjpriv->policy_index;
++	u8 interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX];
++	u8 new_mcc_duration_time = 0;
++	u8 new_starttime_offset = 0;
++
++	/* convert % to ms */
++	new_mcc_duration_time = mcc_duration * interval / 100;
++
++	/* start time offset = (interval - duration time)/2 */
++	new_starttime_offset = (interval - new_mcc_duration_time) >> 1;
++
++	/* update modified parameters */
++	mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX]
++		= new_mcc_duration_time;
++
++	mcc_switch_channel_policy_table[mcc_policy_idx][MCC_START_TIME_OFFSET_IDX]
++		= new_starttime_offset;
++	
++
++}
++
++static void rtw_hal_config_mcc_switch_channel_setting(PADAPTER padapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
++	struct registry_priv *registry_par = &padapter->registrypriv;
++	u8 mcc_duration = 0;
++	s8 mcc_policy_idx = 0;
++
++	mcc_policy_idx = registry_par->rtw_mcc_policy_table_idx;
++	mcc_duration = mccobjpriv->duration;
++
++	if (mcc_policy_idx < 0 || mcc_policy_idx >= mcc_max_policy_num) {
++		mccobjpriv->policy_index = 0;
++		RTW_INFO("[MCC] can't find table(%d), use default policy(%d)\n",
++			mcc_policy_idx, mccobjpriv->policy_index);
++	} else
++		mccobjpriv->policy_index = mcc_policy_idx;
++
++	/* convert % to time */
++	if (mcc_duration != 0)
++		rtw_hal_mcc_update_policy_table(padapter);
++
++	RTW_INFO("[MCC] policy(%d): %d,%d,%d,%d,%d,%d\n"
++		, mccobjpriv->policy_index
++		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX]
++		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_TSF_SYNC_OFFSET_IDX]
++		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_START_TIME_OFFSET_IDX]
++		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_INTERVAL_IDX]
++		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX]
++		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX]);
++
++}
++
++static void rtw_hal_mcc_assign_tx_threshold(PADAPTER padapter) 
++{
++	struct registry_priv *preg = &padapter->registrypriv;
++	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++	switch (pmccadapriv->role) {
++	case MCC_ROLE_STA:
++	case MCC_ROLE_GC:
++		switch (pmlmeext->cur_bwmode) {
++		case CHANNEL_WIDTH_20:
++			/*
++			* target tx byte(bytes) = target tx tp(Mbits/sec) * 1024 * 1024 / 8 * (duration(ms) / 1024)
++			*					= target tx tp(Mbits/sec) * 128 * duration(ms)
++			* note:
++			* target tx tp(Mbits/sec) * 1024 * 1024 / 8 ==> Mbits to bytes
++			* duration(ms) / 1024 ==> msec to sec
++			*/
++			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw20_target_tx_tp * 128 * pmccadapriv->mcc_duration;
++			break;
++		case CHANNEL_WIDTH_40:
++			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw40_target_tx_tp * 128 * pmccadapriv->mcc_duration;
++			break;
++		case CHANNEL_WIDTH_80:
++			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw80_target_tx_tp * 128 * pmccadapriv->mcc_duration;
++			break;
++		case CHANNEL_WIDTH_160:
++		case CHANNEL_WIDTH_80_80:
++			RTW_INFO(FUNC_ADPT_FMT": not support bwmode = %d\n"
++				, FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode);
++			break;
++		}
++		break;
++	case MCC_ROLE_AP:
++	case MCC_ROLE_GO:
++		switch (pmlmeext->cur_bwmode) {
++		case CHANNEL_WIDTH_20:
++			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw20_target_tx_tp * 128 * pmccadapriv->mcc_duration;
++			break;
++		case CHANNEL_WIDTH_40:
++			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw40_target_tx_tp * 128 * pmccadapriv->mcc_duration;
++			break;
++		case CHANNEL_WIDTH_80:
++			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw80_target_tx_tp * 128 * pmccadapriv->mcc_duration;
++			break;
++		case CHANNEL_WIDTH_160:
++		case CHANNEL_WIDTH_80_80:
++			RTW_INFO(FUNC_ADPT_FMT": not support bwmode = %d\n"
++				, FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode);
++			break;
++		}
++		break;
++	default:
++		RTW_INFO(FUNC_ADPT_FMT": unknown role = %d\n"
++			, FUNC_ADPT_ARG(padapter), pmccadapriv->role);
++		break;
++	}
++}
++
++#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++static void mcc_cfg_phdym_rf_ch (_adapter *adapter)
++{
++		struct mcc_adapter_priv *mccadapriv = &adapter->mcc_adapterpriv;
++		struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++		HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
++		struct dm_struct *dm = &hal->odmpriv;
++		struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
++		u8 order = 0;
++
++		set_channel_bwmode(adapter, mlmeext->cur_channel, mlmeext->cur_ch_offset, mlmeext->cur_bwmode);
++		order = mccadapriv->order;
++		mcc_dm->mcc_rf_ch[order] = phy_query_rf_reg(adapter, RF_PATH_A, 0x18, 0x03ff);
++}
++
++static void mcc_cfg_phdym_update_macid (_adapter *adapter, u8 add, u8 mac_id)
++{
++		struct mcc_adapter_priv *mccadapriv = &adapter->mcc_adapterpriv;
++		struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++		HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
++		struct dm_struct *dm = &hal->odmpriv;
++		struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
++		u8 order = 0, i = 0;
++
++		order = mccadapriv->order;
++		if (add) {
++			for (i = 0; i < NUM_STA; i++) {
++				if (mcc_dm->sta_macid[order][i] == 0xff) {
++					mcc_dm->sta_macid[order][i] = mac_id;
++					break;
++				}
++			}
++		} else {
++			for (i = 0; i < NUM_STA; i++) {
++				if (mcc_dm->sta_macid[order][i] == mac_id) {
++					mcc_dm->sta_macid[order][i] = 0xff;
++					break;
++				}
++			}
++		}
++
++		
++}
++
++static void mcc_cfg_phdym_start(_adapter *adapter, u8 start)
++{
++	struct dvobj_priv *dvobj;
++	struct mcc_obj_priv *mccobjpriv;
++	HAL_DATA_TYPE *hal;
++	struct dm_struct *dm;
++	struct _phydm_mcc_dm_ *mcc_dm;
++	u8 rfk_forbidden = _TRUE;
++	u8 i = 0, j = 0;
++
++	dvobj = adapter_to_dvobj(adapter);
++	mccobjpriv = adapter_to_mccobjpriv(adapter);
++	hal = GET_HAL_DATA(adapter);
++	dm = &hal->odmpriv;
++	mcc_dm = &dm->mcc_dm;
++
++	if (start) {
++		#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++		mcc_dm->mcc_status = mccobjpriv->mcc_phydm_offload;
++		#endif
++
++		rfk_forbidden = _TRUE;
++		halrf_cmn_info_set(dm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
++	} else {
++		rfk_forbidden = _FALSE;
++		halrf_cmn_info_set(dm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
++
++		#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++		for(i = 0; i < MAX_MCC_NUM; i ++) {
++			for(j = 0; j < NUM_STA; j ++) {
++				if (mcc_dm->sta_macid[i][j] != 0xff)
++					/* clear all used value for mcc stop */
++					/* do nothing for mcc start due to phydm will init to 0xff */
++					mcc_dm->sta_macid[i][j] = 0xff;
++			}
++			mcc_dm->mcc_rf_ch[i] = 0xff;
++		}
++		mcc_dm->mcc_status = 0;
++		#endif
++	}
++}
++
++static void mcc_cfg_phdym_dump(_adapter *adapter, void *sel)
++{
++	HAL_DATA_TYPE *hal;
++	struct dm_struct *dm;
++	struct _phydm_mcc_dm_ *mcc_dm;
++	u8 rfk_forbidden = _TRUE;
++	u8 i = 0, j = 0;
++
++
++	hal = GET_HAL_DATA(adapter);
++	dm = &hal->odmpriv;
++	mcc_dm = &dm->mcc_dm;
++
++	rfk_forbidden = halrf_cmn_info_get(dm, HALRF_CMNINFO_RFK_FORBIDDEN);
++	RTW_PRINT_SEL(sel, "dump mcc dm info\n");
++	RTW_PRINT_SEL(sel, "mcc_status=%d\n", mcc_dm->mcc_status);
++	RTW_PRINT_SEL(sel, "rfk_forbidden=%d\n", rfk_forbidden);
++	for(i = 0; i < MAX_MCC_NUM; i ++) {
++
++		if (mcc_dm->mcc_rf_ch[i] != 0xff)
++			RTW_PRINT_SEL(sel, "mcc_dm->mcc_rf_ch[%d] = 0x%02x\n", i, mcc_dm->mcc_rf_ch[i]);
++		
++		for(j = 0; j < NUM_STA; j ++) {
++			if (mcc_dm->sta_macid[i][j] != 0xff)
++				RTW_PRINT_SEL(sel, "mcc_dm->sta_macid[%d][%d] = %d\n", i, j, mcc_dm->sta_macid[i][j]);
++		}
++	}
++}
++
++static void mcc_cfg_phdym_offload(_adapter *adapter, u8 enable)
++{
++	struct mcc_obj_priv *mccobjpriv = adapter_to_mccobjpriv(adapter);
++	_adapter *iface = NULL;
++	struct mcc_adapter_priv *mccadapriv = NULL;
++	HAL_DATA_TYPE *hal = NULL;
++	struct dm_struct *dm = NULL;
++	struct _phydm_mcc_dm_ *mcc_dm = NULL;
++	struct sta_priv *stapriv = NULL;
++	struct sta_info *sta = NULL;
++	struct wlan_network *cur_network = NULL;
++	_irqL irqL;
++	_list	*head = NULL, *list = NULL;
++	u8 i = 0;
++
++
++	hal = GET_HAL_DATA(adapter);
++	dm = &hal->odmpriv;
++	mcc_dm = &dm->mcc_dm;
++
++	/* due to phydm will rst related date, driver must set related data */
++	if (enable) {
++		for (i = 0; i < MAX_MCC_NUM; i++) {
++			iface = mccobjpriv->iface[i];
++			if (!iface)
++				continue;
++			stapriv = &iface->stapriv;
++			mccadapriv = &iface->mcc_adapterpriv;
++			switch (mccadapriv->role) {
++			case MCC_ROLE_STA:
++			case MCC_ROLE_GC:
++				cur_network = &iface->mlmepriv.cur_network;
++				sta = rtw_get_stainfo(stapriv, cur_network->network.MacAddress);
++				if (sta)
++					mcc_cfg_phdym_update_macid(iface, _TRUE, sta->cmn.mac_id);
++				break;
++			case MCC_ROLE_AP:
++			case MCC_ROLE_GO:
++				_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
++
++				head = &stapriv->asoc_list;
++				list = get_next(head);
++		
++				while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
++					sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
++					list = get_next(list);
++					mcc_cfg_phdym_update_macid(iface, _TRUE, sta->cmn.mac_id);
++				}
++
++				_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
++				break;
++			default:
++				RTW_INFO("Unknown role\n");
++				rtw_warn_on(1);
++				break;
++			}
++			
++		}
++	}
++
++	mcc_dm->mcc_status = enable;
++}
++
++static void rtw_hal_mcc_cfg_phydm (_adapter *adapter, enum mcc_cfg_phydm_ops ops, void *data)
++{
++	switch (ops) {
++	case MCC_CFG_PHYDM_OFFLOAD:
++		mcc_cfg_phdym_offload(adapter, *(u8 *)data);
++		break;
++	case MCC_CFG_PHYDM_RF_CH:
++		mcc_cfg_phdym_rf_ch(adapter);
++		break;
++	case MCC_CFG_PHYDM_ADD_CLIENT:
++		mcc_cfg_phdym_update_macid(adapter, _TRUE, *(u8 *)data);
++		break;
++	case MCC_CFG_PHYDM_REMOVE_CLIENT:
++		mcc_cfg_phdym_update_macid(adapter, _FALSE, *(u8 *)data);
++		break;
++	case MCC_CFG_PHYDM_START:
++		mcc_cfg_phdym_start(adapter, _TRUE);
++		break;
++	case MCC_CFG_PHYDM_STOP:
++		mcc_cfg_phdym_start(adapter, _FALSE);
++		break;
++	case MCC_CFG_PHYDM_DUMP:
++		mcc_cfg_phdym_dump(adapter, data);
++		break;
++	case MCC_CFG_PHYDM_MAX:
++	default:
++		RTW_ERR("[MCC] rtw_hal_mcc_cfg_phydm ops error (%d)\n", ops);
++		break;
++
++	}
++}
++#endif
++
++static void rtw_hal_config_mcc_role_setting(PADAPTER padapter, u8 order)
++{
++	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
++	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct sta_info *psta = NULL;
++	struct registry_priv *preg = &padapter->registrypriv;
++	_irqL irqL;
++	_list	*phead =NULL, *plist = NULL;
++	u8 policy_index = 0;
++	u8 mcc_duration = 0;
++	u8 mcc_interval = 0;
++	u8 starting_ap_num = DEV_AP_STARTING_NUM(pdvobjpriv);
++	u8 ap_num = DEV_AP_NUM(pdvobjpriv);
++
++	policy_index = pmccobjpriv->policy_index;
++	mcc_duration = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_DURATION_IDX]
++		- mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX]
++			- mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX];
++	mcc_interval = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_INTERVAL_IDX];
++
++	if (starting_ap_num == 0 && ap_num == 0) {
++		pmccadapriv->order = order;
++
++		if (pmccadapriv->order == 0) {
++			/* setting is smiliar to GO/AP */
++			/* pmccadapriv->mcc_duration = mcc_interval - mcc_duration;*/
++			pmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID;
++		} else if (pmccadapriv->order == 1) {
++			/* pmccadapriv->mcc_duration = mcc_duration; */
++			pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID;
++		} else {
++			RTW_INFO("[MCC] not support >= 3 interface\n");
++			rtw_warn_on(1);
++		}
++
++		rtw_hal_mcc_assign_tx_threshold(padapter);
++
++		psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
++		if (psta) {
++			/* combine AP/GO macid and mgmt queue macid to bitmap */
++			pmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid);
++			#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++			rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_ADD_CLIENT, &psta->cmn.mac_id);
++			#endif
++		} else {
++			RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter));
++			rtw_warn_on(1);
++		}
++	} else {
++		/* GO/AP is 1nd order  GC/STA is 2nd order */
++		switch (pmccadapriv->role) {
++		case MCC_ROLE_STA:
++		case MCC_ROLE_GC:
++			pmccadapriv->order = 1;
++			pmccadapriv->mcc_duration = mcc_duration;
++
++			rtw_hal_mcc_assign_tx_threshold(padapter);
++			/* assign used mac to avoid affecting RA */
++			pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID;
++
++			psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
++			if (psta) {
++				/* combine AP/GO macid and mgmt queue macid to bitmap */
++				pmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid);
++				#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++				rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_ADD_CLIENT, &psta->cmn.mac_id);
++				#endif
++			} else {
++				RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter));
++				rtw_warn_on(1);
++			}
++			break;
++		case MCC_ROLE_AP:
++		case MCC_ROLE_GO:
++			pmccadapriv->order = 0;
++			/* total druation value equals interval */
++			pmccadapriv->mcc_duration = mcc_interval - mcc_duration;
++			pmccadapriv->p2p_go_noa_ie_len = 0; /* not NoA attribute at init time */
++
++			rtw_hal_mcc_assign_tx_threshold(padapter);
++
++			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++			phead = &pstapriv->asoc_list;
++			plist = get_next(phead);
++			pmccadapriv->mcc_macid_bitmap = 0;
++	
++			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++				psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++				plist = get_next(plist);
++				pmccadapriv->mcc_macid_bitmap |= BIT(psta->cmn.mac_id);
++				#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++				rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_ADD_CLIENT, &psta->cmn.mac_id);
++				#endif
++			}
++
++			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++			psta = rtw_get_bcmc_stainfo(padapter);
++
++			if (psta != NULL)
++				pmccadapriv->mgmt_queue_macid = psta->cmn.mac_id;
++			else {
++				pmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID;
++				RTW_INFO(FUNC_ADPT_FMT":bcmc station is NULL, use macid %d\n"
++					, FUNC_ADPT_ARG(padapter), pmccadapriv->mgmt_queue_macid);
++			}
++
++			/* combine client macid and mgmt queue macid to bitmap */
++			pmccadapriv->mcc_macid_bitmap |= BIT(pmccadapriv->mgmt_queue_macid);
++			break;
++		default:
++			RTW_INFO("Unknown role\n");
++			rtw_warn_on(1);
++			break;
++		}
++
++	}
++
++	/* setting Null data parameters */
++	if (pmccadapriv->role == MCC_ROLE_STA) {
++			pmccadapriv->null_early = 3;
++			pmccadapriv->null_rty_num= 5;
++	} else if (pmccadapriv->role == MCC_ROLE_GC) {
++			pmccadapriv->null_early = 2;
++			pmccadapriv->null_rty_num= 5;
++	} else {
++			pmccadapriv->null_early = 0;
++			pmccadapriv->null_rty_num= 0;
++	}
++
++	RTW_INFO("********* "FUNC_ADPT_FMT" *********\n", FUNC_ADPT_ARG(padapter));
++	RTW_INFO("order:%d\n", pmccadapriv->order);
++	RTW_INFO("role:%d\n", pmccadapriv->role);
++	RTW_INFO("mcc duration:%d\n", pmccadapriv->mcc_duration);
++	RTW_INFO("null_early:%d\n", pmccadapriv->null_early);
++	RTW_INFO("null_rty_num:%d\n", pmccadapriv->null_rty_num);
++	RTW_INFO("mgmt queue macid:%d\n", pmccadapriv->mgmt_queue_macid);
++	RTW_INFO("bitmap:0x%02x\n", pmccadapriv->mcc_macid_bitmap);
++	RTW_INFO("target tx bytes:%d\n", pmccadapriv->mcc_target_tx_bytes_to_port);
++	RTW_INFO("**********************************\n");
++
++	pmccobjpriv->iface[pmccadapriv->order] = padapter;
++	#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++	rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_RF_CH, NULL);
++	#endif
++
++}
++
++static void rtw_hal_mcc_rqt_tsf(PADAPTER padapter, u64 *out_tsf)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
++	PADAPTER order0_iface = NULL;
++	PADAPTER order1_iface = NULL;
++	struct submit_ctx *tsf_req_sctx = NULL;
++	enum _hw_port tsfx = MAX_HW_PORT;
++	enum _hw_port tsfy = MAX_HW_PORT;
++	u8 cmd[H2C_MCC_RQT_TSF_LEN] = {0};
++
++	_enter_critical_mutex(&mccobjpriv->mcc_tsf_req_mutex, NULL);
++
++	order0_iface = mccobjpriv->iface[0];
++	order1_iface = mccobjpriv->iface[1];
++
++	tsf_req_sctx = &mccobjpriv->mcc_tsf_req_sctx;
++	rtw_sctx_init(tsf_req_sctx, MCC_EXPIRE_TIME);
++	mccobjpriv->mcc_tsf_req_sctx_order = 0;
++	tsfx = rtw_hal_get_port(order0_iface);
++	tsfy = rtw_hal_get_port(order1_iface);
++
++	SET_H2CCMD_MCC_RQT_TSFX(cmd, tsfx);
++	SET_H2CCMD_MCC_RQT_TSFY(cmd, tsfy);
++
++	rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_RQT_TSF, H2C_MCC_RQT_TSF_LEN, cmd);
++
++	if (!rtw_sctx_wait(tsf_req_sctx, __func__))
++		RTW_INFO(FUNC_ADPT_FMT": wait for mcc tsf req C2H time out\n", FUNC_ADPT_ARG(padapter));
++
++	if (tsf_req_sctx->status  == RTW_SCTX_DONE_SUCCESS && out_tsf != NULL) {
++		out_tsf[0] = order0_iface->mcc_adapterpriv.tsf;
++		out_tsf[1] = order1_iface->mcc_adapterpriv.tsf;
++	}
++
++
++	_exit_critical_mutex(&mccobjpriv->mcc_tsf_req_mutex, NULL);
++}
++
++static u8 rtw_hal_mcc_check_start_time_is_valid(PADAPTER padapter, u8 case_num,
++	u32 tsfdiff, s8 *upper_bound_0, s8 *lower_bound_0, s8 *upper_bound_1, s8 *lower_bound_1)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
++	u8 duration_0 = 0, duration_1 = 0;
++	s8 final_upper_bound = 0, final_lower_bound = 0;
++	u8 intersection =  _FALSE;
++	u8 min_start_time = 5;
++	u8 max_start_time = 95;
++	
++	duration_0 = mccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration;
++	duration_1 = mccobjpriv->iface[1]->mcc_adapterpriv.mcc_duration;
++
++	switch(case_num) {
++	case 1:
++		*upper_bound_0 = tsfdiff;
++		*lower_bound_0 = tsfdiff - duration_1;
++		*upper_bound_1 = 150 - duration_1;
++		*lower_bound_1= 0;
++		break;
++	case 2:
++		*upper_bound_0 = tsfdiff + 100;
++		*lower_bound_0 = tsfdiff + 100 - duration_1;
++		*upper_bound_1 = 150 - duration_1;
++		*lower_bound_1= 0;
++		break;
++	case 3:
++		*upper_bound_0 = tsfdiff + 50;
++		*lower_bound_0 = tsfdiff + 50 - duration_1;
++		*upper_bound_1 = 150 - duration_1;
++		*lower_bound_1= 0;
++		break;
++	case 4:
++		*upper_bound_0 = tsfdiff;
++		*lower_bound_0 = tsfdiff - duration_1;
++		*upper_bound_1 = 150 - duration_1;
++		*lower_bound_1= 0;
++		break;
++	case 5:
++		*upper_bound_0 = 200 - tsfdiff;
++		*lower_bound_0 = 200 - tsfdiff - duration_1;
++		*upper_bound_1 = 150 - duration_1;
++		*lower_bound_1= 0;
++		break;
++	case 6:
++		*upper_bound_0 = tsfdiff - 50;
++		*lower_bound_0 = tsfdiff - 50 - duration_1;
++		*upper_bound_1 = 150 - duration_1;
++		*lower_bound_1= 0;
++		break;
++	default:
++		RTW_ERR("[MCC] %s: error case number(%d\n)", __func__, case_num);
++	}
++
++
++	/* check Intersection or not */
++	if ((*lower_bound_1 >= *upper_bound_0) ||
++		(*lower_bound_0 >= *upper_bound_1))
++		intersection = _FALSE;
++	else
++		intersection = _TRUE;
++
++	if (intersection) {
++		if (*upper_bound_0 > *upper_bound_1)
++			final_upper_bound = *upper_bound_1;
++		else
++			final_upper_bound = *upper_bound_0;
++
++		if (*lower_bound_0 > *lower_bound_1)
++			final_lower_bound = *lower_bound_0;
++		else
++			final_lower_bound = *lower_bound_1;
++
++		mccobjpriv->start_time = (final_lower_bound + final_upper_bound) / 2;
++
++		/* check start time less than 5ms, request by Pablo@SD1 */
++		if (mccobjpriv->start_time <= min_start_time) {
++			mccobjpriv->start_time = 6;
++			if (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) {
++				intersection = _FALSE;
++				goto exit;
++			}
++		}
++
++		/* check start time less than 95ms */
++		if (mccobjpriv->start_time >= max_start_time) {
++			mccobjpriv->start_time = 90;
++			if (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) {
++				intersection = _FALSE;
++				goto exit;
++			}
++		}
++	}
++
++exit:
++	return intersection;
++}
++
++static void rtw_hal_mcc_decide_duration(PADAPTER padapter)
++{
++	struct registry_priv *registry_par = &padapter->registrypriv;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
++	struct mcc_adapter_priv *mccadapriv = NULL, *mccadapriv_order0 = NULL, *mccadapriv_order1 = NULL;
++	_adapter *iface = NULL, *iface_order0 = NULL,  *iface_order1 = NULL;
++	u8 duration = 0, i = 0, duration_time;
++	u8 mcc_interval = 150;
++
++	iface_order0 = mccobjpriv->iface[0];
++	iface_order1 = mccobjpriv->iface[1];
++	mccadapriv_order0 = &iface_order0->mcc_adapterpriv;
++	mccadapriv_order1 = &iface_order1->mcc_adapterpriv;
++	
++	if (mccobjpriv->duration == 0) {
++		/* default */
++		duration = 30;/*(%)*/
++		RTW_INFO("%s: mccobjpriv->duration=0, use default value(%d)\n",
++			__FUNCTION__, duration);
++	} else {
++		duration = mccobjpriv->duration;/*(%)*/
++		RTW_INFO("%s: mccobjpriv->duration=%d\n",
++			__FUNCTION__, duration);
++	}
++
++	mccobjpriv->interval = mcc_interval;
++	mccobjpriv->mcc_stop_threshold = 2000 * 4 / 300 - 6;
++	/* convert % to ms, for primary adapter */
++	duration_time = mccobjpriv->interval * duration / 100;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++
++		if (!iface)
++			continue;
++
++		mccadapriv = &iface->mcc_adapterpriv;
++		if (mccadapriv->role == MCC_ROLE_MAX)
++			continue;
++
++		if (is_primary_adapter(iface))
++			mccadapriv->mcc_duration = duration_time;
++		else
++			mccadapriv->mcc_duration = mccobjpriv->interval - duration_time;
++	}
++
++	RTW_INFO("[MCC]"  FUNC_ADPT_FMT " order 0 duration=%d\n", FUNC_ADPT_ARG(iface_order0), mccadapriv_order0->mcc_duration);
++	RTW_INFO("[MCC]"  FUNC_ADPT_FMT " order 1 duration=%d\n", FUNC_ADPT_ARG(iface_order1), mccadapriv_order1->mcc_duration);
++}
++
++static u8 rtw_hal_mcc_update_timing_parameters(PADAPTER padapter, u8 force_update)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	u8 need_update = _FALSE;
++	u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);
++	u8 ap_num = DEV_AP_NUM(dvobj);
++
++
++	/* for STA+STA, modify policy table */
++	if (starting_ap_num == 0 && ap_num == 0) {
++		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++		struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
++		struct mcc_adapter_priv *pmccadapriv = NULL;
++		_adapter *iface = NULL;
++		u64 tsf[MAX_MCC_NUM] = {0};
++		u64 tsf0 = 0, tsf1 = 0;
++		u32 beaconperiod_0 = 0, beaconperiod_1 = 0, tsfdiff = 0;
++		s8 upper_bound_0 = 0, lower_bound_0 = 0;
++		s8 upper_bound_1 = 0, lower_bound_1 = 0;
++		u8 valid = _FALSE;
++		u8 case_num = 1;
++		u8 i = 0;
++		
++		/* query TSF */
++		rtw_hal_mcc_rqt_tsf(padapter, tsf);
++
++		/* selecet policy table according TSF diff */
++		tsf0 = tsf[0];
++		beaconperiod_0 = pmccobjpriv->iface[0]->mlmepriv.cur_network.network.Configuration.BeaconPeriod;
++		tsf0 = rtw_modular64(tsf0, (beaconperiod_0 * TU));
++
++		tsf1 = tsf[1];
++		beaconperiod_1 = pmccobjpriv->iface[1]->mlmepriv.cur_network.network.Configuration.BeaconPeriod;
++		tsf1 = rtw_modular64(tsf1, (beaconperiod_1 * TU));
++
++		if (tsf0 > tsf1)
++			tsfdiff = tsf0- tsf1;
++		else
++			tsfdiff = (tsf0 +  beaconperiod_0 * TU) - tsf1;
++
++		/* convert to ms */
++		tsfdiff = (tsfdiff / TU);
++
++		/* force update*/
++		if (force_update) {
++			RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
++				pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
++			RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
++			RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
++				__func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
++			pmccobjpriv->last_tsfdiff = tsfdiff;
++			need_update = _TRUE;
++		} else {
++			if (pmccobjpriv->last_tsfdiff > tsfdiff) {
++				/* last tsfdiff - current tsfdiff > THRESHOLD, update parameters */
++				if (pmccobjpriv->last_tsfdiff > (tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) {
++					RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
++						pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
++					RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
++					RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
++						__func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
++
++					pmccobjpriv->last_tsfdiff = tsfdiff;
++					need_update = _TRUE;
++				} else {
++					need_update = _FALSE;
++				}
++			} else if (tsfdiff > pmccobjpriv->last_tsfdiff){
++				/* current tsfdiff - last tsfdiff > THRESHOLD, update parameters */
++				if (tsfdiff > (pmccobjpriv->last_tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) {
++					RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
++						pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
++					RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
++					RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
++						__func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
++
++					pmccobjpriv->last_tsfdiff = tsfdiff;
++					need_update = _TRUE;
++				} else {
++					need_update = _FALSE;
++				}
++			} else {
++				need_update = _FALSE;
++			}
++		}
++
++		if (need_update == _FALSE)
++			goto exit;
++
++		rtw_hal_mcc_decide_duration(padapter);
++
++		if (tsfdiff <= 50) {
++	
++			/* RX TBTT 0 */
++			case_num = 1;
++			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
++				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
++
++			if (valid)
++				goto valid_result;
++	
++			/* RX TBTT 1 */
++			case_num = 2;
++			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
++				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
++
++			if (valid)
++				goto valid_result;
++			
++			/* RX TBTT 2 */
++			case_num = 3;
++			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
++				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
++
++			if (valid)
++				goto valid_result;
++
++			if (valid == _FALSE) {
++				RTW_INFO("[MCC] do not find fit start time\n");
++				RTW_INFO("[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\n",
++					tsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval);
++
++			}
++
++		} else {
++
++			/* RX TBTT 0 */
++			case_num = 4;
++			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
++				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
++
++			if (valid)
++				goto valid_result;
++			
++			
++			/* RX TBTT 1 */
++			case_num = 5;
++			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
++				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
++
++			if (valid)
++				goto valid_result;
++
++			
++			/* RX TBTT 2 */
++			case_num = 6;
++			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
++				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
++
++			if (valid)
++				goto valid_result;
++
++			if (valid == _FALSE) {
++				RTW_INFO("[MCC] do not find fit start time\n");
++				RTW_INFO("[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\n",
++					tsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval);
++			}
++		}
++
++		
++
++	valid_result:
++		RTW_INFO("********************\n");
++		RTW_INFO("%s: case_num:%d, start time:%d\n",
++				__func__, case_num, pmccobjpriv->start_time);
++		RTW_INFO("%s: upper_bound_0:%d, lower_bound_0:%d\n",
++				__func__, upper_bound_0, lower_bound_0);
++		RTW_INFO("%s: upper_bound_1:%d, lower_bound_1:%d\n",
++				__func__, upper_bound_1, lower_bound_1);
++		
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			iface = dvobj->padapters[i];
++			if (iface == NULL)
++				continue;
++
++			pmccadapriv = &iface->mcc_adapterpriv;
++			pmccadapriv = &iface->mcc_adapterpriv;
++			if (pmccadapriv->role == MCC_ROLE_MAX)
++				continue;
++#if 0
++			if (pmccadapriv->order == 0) {
++				pmccadapriv->mcc_duration = mcc_duration;
++			} else if (pmccadapriv->order == 1) {
++				pmccadapriv->mcc_duration = mcc_interval - mcc_duration;
++			} else {
++				RTW_INFO("[MCC] not support >= 3 interface\n");
++				rtw_warn_on(1);
++			}
++#endif
++			RTW_INFO("********************\n");
++			RTW_INFO(FUNC_ADPT_FMT": order:%d, role:%d\n",
++				FUNC_ADPT_ARG(iface), pmccadapriv->order, pmccadapriv->role);
++			RTW_INFO(FUNC_ADPT_FMT": mcc duration:%d, target tx bytes:%d\n",
++				FUNC_ADPT_ARG(iface), pmccadapriv->mcc_duration, pmccadapriv->mcc_target_tx_bytes_to_port);
++			RTW_INFO(FUNC_ADPT_FMT": mgmt queue macid:%d, bitmap:0x%02x\n",
++				FUNC_ADPT_ARG(iface), pmccadapriv->mgmt_queue_macid, pmccadapriv->mcc_macid_bitmap);
++			RTW_INFO("********************\n");
++		}
++		
++	}
++exit:
++	return need_update;
++}
++
++static u8 rtw_hal_decide_mcc_role(PADAPTER padapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	_adapter *iface = NULL;
++	struct mcc_adapter_priv *pmccadapriv = NULL;
++	struct wifidirect_info *pwdinfo = NULL;
++	struct mlme_priv *pmlmepriv = NULL;
++	u8 ret = _SUCCESS, i = 0;
++	u8 order = 1;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (iface == NULL)
++			continue;
++
++		pmccadapriv = &iface->mcc_adapterpriv;
++		pwdinfo = &iface->wdinfo;
++
++		if (MLME_IS_GO(iface))
++			pmccadapriv->role = MCC_ROLE_GO;
++		else if (MLME_IS_AP(iface))
++			pmccadapriv->role = MCC_ROLE_AP;
++		else if (MLME_IS_GC(iface))
++			pmccadapriv->role = MCC_ROLE_GC;
++		else if (MLME_IS_STA(iface)) {
++			if (MLME_IS_LINKING(iface) || MLME_IS_ASOC(iface))
++				pmccadapriv->role = MCC_ROLE_STA;
++			else {
++				/* bypass non-linked/non-linking interface */
++				RTW_INFO(FUNC_ADPT_FMT" mlme state:0x%2x\n",
++					FUNC_ADPT_ARG(iface), MLME_STATE(iface));
++				continue;
++			}
++		} else {
++			/* bypass non-linked/non-linking interface */
++			RTW_INFO(FUNC_ADPT_FMT" P2P Role:%d, mlme state:0x%2x\n",
++				FUNC_ADPT_ARG(iface), pwdinfo->role, MLME_STATE(iface));
++			continue;
++		}
++
++		if (padapter == iface) {
++			/* current adapter is order 0 */
++			rtw_hal_config_mcc_role_setting(iface, 0);
++		} else {
++			rtw_hal_config_mcc_role_setting(iface, order);
++			order ++;
++		}
++	}
++
++	rtw_hal_mcc_update_timing_parameters(padapter, _TRUE);
++
++	return ret;
++}
++
++static void rtw_hal_construct_CTS(PADAPTER padapter, u8 *pframe, u32 *pLength)
++{
++	u8 broadcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++
++	/* frame type, length = 1*/
++	set_frame_sub_type(pframe, WIFI_RTS);
++
++	/* frame control flag, length = 1 */
++	*(pframe + 1) = 0;
++
++	/* frame duration, length = 2 */
++	*(pframe + 2) = 0x00;
++	*(pframe + 3) = 0x78;
++
++	/* frame recvaddr, length = 6 */
++	_rtw_memcpy((pframe + 4), broadcast_addr, ETH_ALEN);
++	_rtw_memcpy((pframe + 4 + ETH_ALEN), adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy((pframe + 4 + ETH_ALEN*2), adapter_mac_addr(padapter), ETH_ALEN);
++	*pLength = 22;
++}
++
++/* avoid wrong information for power limit */
++void rtw_hal_mcc_upadate_chnl_bw(_adapter *padapter, u8 ch, u8 ch_offset, u8 bw, u8 print)
++{
++
++	u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	PHAL_DATA_TYPE	hal = GET_HAL_DATA(padapter);
++	u8 cch_160, cch_80, cch_40, cch_20;
++
++	center_ch = rtw_get_center_ch(ch, bw, ch_offset);
++
++	if (bw == CHANNEL_WIDTH_80) {
++		if (center_ch > ch)
++			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
++		else if (center_ch < ch)
++			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
++		else
++			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++	}
++
++	/* set Channel */
++	/* saved channel/bw info */
++	rtw_set_oper_ch(padapter, ch);
++	rtw_set_oper_bw(padapter, bw);
++	rtw_set_oper_choffset(padapter, ch_offset);
++
++	cch_80 = bw == CHANNEL_WIDTH_80 ? center_ch : 0;
++	cch_40 = bw == CHANNEL_WIDTH_40 ? center_ch : 0;
++	cch_20 = bw == CHANNEL_WIDTH_20 ? center_ch : 0;
++
++	if (cch_80 != 0)
++		cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, chnl_offset80);
++	if (cch_40 != 0)
++		cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, ch_offset);
++
++
++	hal->cch_80 = cch_80;
++	hal->cch_40 = cch_40;
++	hal->cch_20 = cch_20;
++	hal->current_channel = center_ch;
++	hal->CurrentCenterFrequencyIndex1 = center_ch;
++	hal->current_channel_bw = bw;
++	hal->nCur40MhzPrimeSC = ch_offset;
++	hal->nCur80MhzPrimeSC = chnl_offset80;
++	hal->current_band_type = ch > 14 ? BAND_ON_5G:BAND_ON_2_4G;
++
++	if (print) {
++		RTW_INFO(FUNC_ADPT_FMT" cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u), band:%s\n"
++			, FUNC_ADPT_ARG(padapter), center_ch, ch_width_str(bw)
++			, ch_offset, chnl_offset80
++			, hal->cch_80, hal->cch_40, hal->cch_20
++			, band_str(hal->current_band_type));
++	}
++}
++
++u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index,
++	u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num)
++{
++	u32 len = 0;
++	_adapter *iface = NULL;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
++	struct mlme_ext_info *pmlmeinfo = NULL;
++	struct mlme_ext_priv *pmlmeext = NULL;
++	struct hal_com_data *hal = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	struct mcc_adapter_priv *mccadapriv = NULL;
++#if defined(CONFIG_RTL8822C)
++	struct dm_struct *phydm = adapter_to_phydm(adapter);
++	struct txagc_table_8822c tab;
++	u8 agc_buff[2][NUM_RATE_AC_2SS]; /* tatol 0x40 rate index for PATH A/B */
++#endif
++	
++	u8 ret = _SUCCESS, i = 0, j  =0, order = 0, CurtPktPageNum = 0;
++	u8 *start = NULL;
++	u8 path = RF_PATH_A;
++
++	if (page_num) {
++#ifdef CONFIG_MCC_MODE_V2
++		if (!hal->RegIQKFWOffload)
++			RTW_WARN("[MCC] must enable FW IQK for New IC\n");
++#endif /* CONFIG_MCC_MODE_V2 */
++		*total_page_num += (2 * MAX_MCC_NUM+ 1);
++		RTW_INFO("[MCC] allocate mcc rsvd page num = %d\n", *total_page_num);
++		goto exit;
++	}
++
++	/* check proccess mcc start setting */
++	if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_PROCESS_MCC_START_SETTING)) {
++		ret = _FAIL;
++		goto exit;
++	}
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (iface == NULL)
++			continue;
++
++		mccadapriv = &iface->mcc_adapterpriv;
++		if (mccadapriv->role == MCC_ROLE_MAX)
++			continue;
++
++		order = mccadapriv->order;
++		pmccobjpriv->mcc_loc_rsvd_paga[order] = *total_page_num;
++
++		switch (mccadapriv->role) {
++		case MCC_ROLE_STA:
++		case MCC_ROLE_GC:
++			/* Build NULL DATA */
++			RTW_INFO("LocNull(order:%d): %d\n"
++				, order, pmccobjpriv->mcc_loc_rsvd_paga[order]);
++			len = 0;
++
++			rtw_hal_construct_NullFunctionData(iface
++				, &pframe[*index], &len, _FALSE, 0, 0, _FALSE);
++			rtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc],
++				len, _FALSE, _FALSE, _FALSE);
++
++			CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size);
++			*total_page_num += CurtPktPageNum;
++			*index += (CurtPktPageNum * page_size);
++			RSVD_PAGE_CFG("LocNull", CurtPktPageNum, *total_page_num, *index);
++			break;
++		case MCC_ROLE_AP:
++			/* Bulid CTS */
++			RTW_INFO("LocCTS(order:%d): %d\n"
++				, order, pmccobjpriv->mcc_loc_rsvd_paga[order]);
++
++			len = 0;
++			rtw_hal_construct_CTS(iface, &pframe[*index], &len);
++			rtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc],
++				len, _FALSE, _FALSE, _FALSE);
++
++			CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size);
++			*total_page_num += CurtPktPageNum;
++			*index += (CurtPktPageNum * page_size);
++			RSVD_PAGE_CFG("LocCTS", CurtPktPageNum, *total_page_num, *index);
++			break;
++		case MCC_ROLE_GO:
++		/* To DO */
++			break;
++		default:
++			RTW_INFO(FUNC_ADPT_FMT": unknown role = %d\n"
++				, FUNC_ADPT_ARG(iface), mccadapriv->role);
++			break;
++		}
++	}
++
++	for (i = 0; i < MAX_MCC_NUM; i++) {
++		u8 center_ch = 0, ch = 0, bw = 0, bw_offset = 0;
++		BAND_TYPE band = BAND_MAX;
++		u8 power_index = 0;
++		u8 rate_array_sz = 0;
++		u8 *rates = NULL;
++		u8 rate = 0;
++		u8 shift = 0;
++		u32 power_index_4bytes = 0;
++		u8 total_rate = 0;
++		u8 *total_rate_offset = NULL;
++
++		iface = pmccobjpriv->iface[i];
++		pmlmeext = &iface->mlmeextpriv;
++		ch = pmlmeext->cur_channel;
++		bw = pmlmeext->cur_bwmode;
++		bw_offset = pmlmeext->cur_ch_offset;
++		center_ch = rtw_get_center_ch(ch, bw, bw_offset);
++		band = center_ch <= 14 ? BAND_ON_2_4G : BAND_ON_5G;
++		rtw_hal_mcc_upadate_chnl_bw(iface, ch, bw_offset, bw, _TRUE);
++
++		start = &pframe[*index - tx_desc];
++		_rtw_memset(start, 0, page_size);
++		pmccobjpriv->mcc_pwr_idx_rsvd_page[i] = *total_page_num;
++		RTW_INFO(ADPT_FMT" order:%d, pwr_idx_rsvd_page location[%d]: %d\n",
++			ADPT_ARG(iface), mccadapriv->order,
++			i, pmccobjpriv->mcc_pwr_idx_rsvd_page[i]);
++
++		total_rate_offset = start;
++#if !defined(CONFIG_RTL8822C)			
++		for (path = RF_PATH_A; path < hal_spec->rf_reg_path_num; ++path) {
++			total_rate = 0;
++			/* PATH A for 0~63 byte, PATH B for 64~127 byte*/
++			if (path == RF_PATH_A)
++				start = total_rate_offset + 1;
++			else if (path == RF_PATH_B)
++				start = total_rate_offset + 64;
++			else {
++				RTW_INFO("[MCC] %s: unknow RF PATH(%d)\n", __func__, path);
++				break;
++			}
++
++			/* CCK */
++			if (ch <= 14) {
++				rate_array_sz = rates_by_sections[CCK].rate_num;
++				rates = rates_by_sections[CCK].rates;
++				for (j = 0; j < rate_array_sz; ++j) {
++					power_index = phy_get_tx_power_index_ex(iface, path, CCK, rates[j], bw, band, center_ch, ch);
++					rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
++
++					shift = rate % 4;
++					if (shift == 0) {
++						*start = rate;
++						start++;
++						total_rate++;
++
++						#ifdef DBG_PWR_IDX_RSVD_PAGE
++						RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
++							ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
++							center_ch, MGN_RATE_STR(rates[j]), power_index);
++						#endif
++					}
++
++					*start = power_index;
++					start++;
++
++					#ifdef DBG_PWR_IDX_RSVD_PAGE
++					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
++						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
++						center_ch, MGN_RATE_STR(rates[j]), power_index);
++
++					
++					shift = rate % 4;
++					power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
++					if (shift == 3) {
++						rate = rate - 3;
++						RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
++						power_index_4bytes = 0;
++						total_rate++;
++					}
++					#endif
++						
++				}
++			}
++
++			/* OFDM */
++			rate_array_sz = rates_by_sections[OFDM].rate_num;
++			rates = rates_by_sections[OFDM].rates;
++			for (j = 0; j < rate_array_sz; ++j) {
++				power_index = phy_get_tx_power_index_ex(iface, path, OFDM, rates[j], bw, band, center_ch, ch);
++				rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
++
++				shift = rate % 4;
++				if (shift == 0) {
++					*start = rate;
++					start++;
++					total_rate++;
++
++					#ifdef DBG_PWR_IDX_RSVD_PAGE
++					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
++						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
++						center_ch, MGN_RATE_STR(rates[j]), power_index);
++					#endif
++
++				}
++
++				*start = power_index;
++				start++;
++
++				#ifdef DBG_PWR_IDX_RSVD_PAGE
++				RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
++					ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
++					center_ch, MGN_RATE_STR(rates[j]), power_index);
++
++				shift = rate % 4;
++				power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
++				if (shift == 3) {
++					rate = rate - 3;
++					RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
++					power_index_4bytes = 0;
++					total_rate++;
++				}
++				#endif
++			}
++
++			/* HT_MCS0_MCS7 */
++			rate_array_sz = rates_by_sections[HT_MCS0_MCS7].rate_num;
++			rates = rates_by_sections[HT_MCS0_MCS7].rates;
++			for (j = 0; j < rate_array_sz; ++j) {
++				power_index = phy_get_tx_power_index_ex(iface, path, HT_1SS, rates[j], bw, band, center_ch, ch);
++				rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
++
++				shift = rate % 4;
++				if (shift == 0) {
++					*start = rate;
++					start++;
++					total_rate++;
++
++					#ifdef DBG_PWR_IDX_RSVD_PAGE
++					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
++						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
++						center_ch, MGN_RATE_STR(rates[j]), power_index);
++					#endif
++
++				}
++
++				*start = power_index;
++				start++;
++
++				#ifdef DBG_PWR_IDX_RSVD_PAGE
++				RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
++					ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
++					center_ch, MGN_RATE_STR(rates[j]), power_index);
++
++				shift = rate % 4;
++				power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
++				if (shift == 3) {
++					rate = rate - 3;
++					RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
++					power_index_4bytes = 0;
++					total_rate++;
++				}
++				#endif
++			}
++
++			/* HT_MCS8_MCS15 */
++			rate_array_sz = rates_by_sections[HT_MCS8_MCS15].rate_num;
++			rates = rates_by_sections[HT_MCS8_MCS15].rates;
++			for (j = 0; j < rate_array_sz; ++j) {
++				power_index = phy_get_tx_power_index_ex(iface, path, HT_2SS, rates[j], bw, band, center_ch, ch);
++				rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
++
++				shift = rate % 4;
++				if (shift == 0) {
++					*start = rate;
++					start++;
++					total_rate++;
++
++					#ifdef DBG_PWR_IDX_RSVD_PAGE
++					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
++						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
++						center_ch, MGN_RATE_STR(rates[j]), power_index);
++					#endif
++				}
++
++				*start = power_index;
++				start++;
++
++				#ifdef DBG_PWR_IDX_RSVD_PAGE
++				RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
++					ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
++					center_ch, MGN_RATE_STR(rates[j]), power_index);
++				
++				shift = rate % 4;
++				power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
++				if (shift == 3) {
++					rate = rate - 3;
++					RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
++					power_index_4bytes = 0;
++					total_rate++;
++				}
++				#endif
++			}
++
++			/* VHT_1SSMCS0_1SSMCS9 */
++			rate_array_sz = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rate_num;
++			rates = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rates;
++			for (j = 0; j < rate_array_sz; ++j) {
++				power_index = phy_get_tx_power_index_ex(iface, path, VHT_1SS, rates[j], bw, band, center_ch, ch);
++				rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
++
++				shift = rate % 4;
++				if (shift == 0) {
++					*start = rate;
++					start++;
++					total_rate++;
++					#ifdef DBG_PWR_IDX_RSVD_PAGE
++					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:0x%02x\n",
++						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
++						center_ch, MGN_RATE_STR(rates[j]), power_index);
++					#endif
++				}
++				*start = power_index;
++				start++;
++				#ifdef DBG_PWR_IDX_RSVD_PAGE
++				RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
++					ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
++					center_ch, MGN_RATE_STR(rates[j]), power_index);
++
++				shift = rate % 4;
++				power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
++				if (shift == 3) {
++					rate = rate - 3;
++					RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
++					power_index_4bytes = 0;
++					total_rate++;
++				}
++				#endif
++			}
++
++			/* VHT_2SSMCS0_2SSMCS9 */
++			rate_array_sz = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rate_num;
++			rates = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rates;
++			for (j = 0; j < rate_array_sz; ++j) {
++				power_index = phy_get_tx_power_index_ex(iface, path, VHT_2SS, rates[j], bw, band, center_ch, ch);
++				rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
++
++				shift = rate % 4;
++				if (shift == 0) {
++					*start = rate;
++					start++;
++					total_rate++;
++					#ifdef DBG_PWR_IDX_RSVD_PAGE
++					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
++						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
++						center_ch, MGN_RATE_STR(rates[j]), power_index);
++					#endif
++				}
++				*start = power_index;
++				start++;
++				#ifdef DBG_PWR_IDX_RSVD_PAGE
++				RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
++					ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
++					center_ch, MGN_RATE_STR(rates[j]), power_index);
++
++				shift = rate % 4;
++				power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
++				if (shift == 3) {
++					rate = rate - 3;
++					RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
++					power_index_4bytes = 0;
++						total_rate++;
++				}
++				#endif
++			}
++				
++		}
++		/*  total rate store in offset 0 */
++		*total_rate_offset = total_rate;
++
++#ifdef DBG_PWR_IDX_RSVD_PAGE
++			RTW_INFO("total_rate=%d\n", total_rate);
++			RTW_INFO(" ======================="ADPT_FMT"===========================\n", ADPT_ARG(iface));
++			RTW_INFO_DUMP("\n", total_rate_offset, 128);
++			RTW_INFO(" ==================================================\n");
++#endif
++
++			CurtPktPageNum = 1;
++			*total_page_num += CurtPktPageNum;
++			*index += (CurtPktPageNum * page_size);
++			RSVD_PAGE_CFG("mcc_pwr_idx_rsvd_page", CurtPktPageNum, *total_page_num, *index);
++#else /* 8822C */
++			for (path = RF_PATH_A; path < hal_spec->rf_reg_path_num; ++path) {
++				/* CCK */
++				if (ch <= 14) {
++					rate_array_sz = rates_by_sections[CCK].rate_num;
++					rates = rates_by_sections[CCK].rates;
++					for (j = 0; j < rate_array_sz; ++j) {
++						power_index = phy_get_tx_power_index_ex(iface, path, CCK, rates[j], bw, band, center_ch, ch);
++						rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
++						agc_buff[path][rate] = power_index;
++					}
++				}
++
++				/* OFDM */
++				rate_array_sz = rates_by_sections[OFDM].rate_num;
++				rates = rates_by_sections[OFDM].rates;
++				for (j = 0; j < rate_array_sz; ++j) {
++					power_index = phy_get_tx_power_index_ex(iface, path, OFDM, rates[j], bw, band, center_ch, ch);
++					rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
++					agc_buff[path][rate] = power_index;
++				}
++				/* HT */
++				rate_array_sz = rates_by_sections[HT_MCS0_MCS7].rate_num;
++				rates = rates_by_sections[HT_MCS0_MCS7].rates;
++				for (j = 0; j < rate_array_sz; ++j) {
++					power_index = phy_get_tx_power_index_ex(iface, path, HT_1SS, rates[j], bw, band, center_ch, ch);
++					rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
++					agc_buff[path][rate] = power_index;
++				}
++
++				rate_array_sz = rates_by_sections[HT_MCS8_MCS15].rate_num;
++				rates = rates_by_sections[HT_MCS8_MCS15].rates;
++				for (j = 0; j < rate_array_sz; ++j) {
++					power_index = phy_get_tx_power_index_ex(iface, path, HT_2SS, rates[j], bw, band, center_ch, ch);
++					rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
++					agc_buff[path][rate] = power_index;
++				}
++				/* VHT */
++				rate_array_sz = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rate_num;
++				rates = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rates;
++				for (j = 0; j < rate_array_sz; ++j) {
++					power_index = phy_get_tx_power_index_ex(iface, path, VHT_1SS, rates[j], bw, band, center_ch, ch);
++					rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
++					agc_buff[path][rate] = power_index;
++				}
++
++				rate_array_sz = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rate_num;
++				rates = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rates;
++				for (j = 0; j < rate_array_sz; ++j) {
++					power_index = phy_get_tx_power_index_ex(iface, path, VHT_2SS, rates[j], bw, band, center_ch, ch);
++					rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
++					agc_buff[path][rate] = power_index;
++				}
++			}
++			phydm_get_txagc_ref_and_diff_8822c(phydm, agc_buff, NUM_RATE_AC_2SS, &tab);
++			*start = tab.ref_pow_cck[0];
++			start++;
++			*start = tab.ref_pow_cck[1];
++			start++;
++			*start = tab.ref_pow_ofdm[0];
++			start++;
++			*start = tab.ref_pow_ofdm[1];
++			start++;
++			_rtw_memcpy(start, tab.diff_t, sizeof(tab.diff_t));
++			CurtPktPageNum = 1;
++			*total_page_num += CurtPktPageNum;
++			*index += (CurtPktPageNum * page_size);
++			RSVD_PAGE_CFG("mcc_pwr_idx_rsvd_page", CurtPktPageNum, *total_page_num, *index);
++			#ifdef DBG_PWR_IDX_RSVD_PAGE
++			if (1) {
++				u8 path_idx;
++				for (path_idx = 0; path_idx < 2; path_idx++) {
++					for (j = 0; j < NUM_RATE_AC_2SS; j++) 
++						RTW_INFO("agc_buff[%d][%d]=%x\n", i, j, agc_buff[i][j]);
++				}
++				RTW_INFO("tab->ref_pow_cck[0]=%x\n", tab.ref_pow_cck[0]);
++				RTW_INFO("tab->ref_pow_cck[1]=%x\n", tab.ref_pow_cck[1]);
++				RTW_INFO("tab->ref_pow_ofdm[0]=%x\n", tab.ref_pow_ofdm[0]);
++				RTW_INFO("tab->ref_pow_ofdm[1]=%x\n", tab.ref_pow_ofdm[1]);
++				RTW_INFO_DUMP("diff_t ", tab.diff_t, NUM_RATE_AC_2SS);
++				RTW_INFO_DUMP("tab ", (u8 *)&tab, sizeof(tab));
++			}
++			#endif
++			
++#endif
++		}
++
++exit:
++	return ret;
++}
++
++/*
++* 1. Download MCC rsvd page
++* 2. Re-Download beacon after download rsvd page
++*/
++static void rtw_hal_set_fw_mcc_rsvd_page(PADAPTER padapter)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	PADAPTER port0_iface = dvobj_get_port0_adapter(dvobj);
++	PADAPTER iface = NULL;
++	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
++	u8 mstatus = RT_MEDIA_CONNECT, i = 0;
++
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++	rtw_hal_set_hwreg(port0_iface, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus));
++
++	/* Re-Download beacon */
++	for (i = 0; i < MAX_MCC_NUM; i++) {
++		iface = pmccobjpriv->iface[i];
++		if (iface == NULL)
++			continue;
++
++		pmccadapriv = &iface->mcc_adapterpriv;
++
++		if (pmccadapriv->role == MCC_ROLE_AP
++			|| pmccadapriv->role == MCC_ROLE_GO) {
++			tx_beacon_hdl(iface, NULL);
++		}
++	}
++}
++
++static void rtw_hal_set_mcc_rsvdpage_cmd(_adapter *padapter)
++{
++	u8 cmd[H2C_MCC_LOCATION_LEN] = {0}, i = 0, order = 0;
++	_adapter *iface = NULL;
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
++
++	SET_H2CCMD_MCC_PWRIDX_OFFLOAD_EN(cmd, _TRUE);
++	SET_H2CCMD_MCC_PWRIDX_OFFLOAD_RFNUM(cmd, hal_spec->rf_reg_path_num);
++	for (order = 0; order < MAX_MCC_NUM; order++) {
++		iface = pmccobjpriv->iface[i];
++
++		SET_H2CCMD_MCC_RSVDPAGE_LOC((cmd + order), pmccobjpriv->mcc_loc_rsvd_paga[order]);
++		SET_H2CCMD_MCC_PWRIDX_RSVDPAGE_LOC ((cmd + order), pmccobjpriv->mcc_pwr_idx_rsvd_page[order]);
++	}
++
++#ifdef CONFIG_MCC_MODE_DEBUG
++	RTW_INFO("=========================\n");
++	RTW_INFO("MCC RSVD PAGE LOC:\n");
++	for (i = 0; i < H2C_MCC_LOCATION_LEN; i++)
++		pr_dbg("0x%x ", cmd[i]);
++	pr_dbg("\n");
++	RTW_INFO("=========================\n");
++#endif /* CONFIG_MCC_MODE_DEBUG */
++
++	rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_LOCATION, H2C_MCC_LOCATION_LEN, cmd);
++}
++
++static void rtw_hal_set_mcc_time_setting_cmd(PADAPTER padapter)
++{
++	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
++	u8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0};
++	u8 fw_eable = 1;
++	u8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME;
++	u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);
++	u8 ap_num = DEV_AP_NUM(dvobj);	
++
++	if (starting_ap_num == 0 && ap_num == 0)
++		/* For STA+GC/STA+STA, TSF of GC/STA does not need to sync from TSF of other STA/GC */
++		fw_eable = 0;
++	else
++		/* Only for STA+GO/STA+AP, TSF of AP/GO need to sync from TSF of STA */
++		fw_eable = 1;
++
++	if (fw_eable == 1) {
++		PADAPTER order0_iface = NULL;
++		PADAPTER order1_iface = NULL;
++		u8 policy_idx = mccobjpriv->policy_index;
++		u8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
++		u8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
++		u8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX];
++		u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX];
++		u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX];
++		enum _hw_port tsf_bsae_port = MAX_HW_PORT;
++		enum _hw_port tsf_sync_port = MAX_HW_PORT;
++		order0_iface = mccobjpriv->iface[0];
++		order1_iface = mccobjpriv->iface[1];
++
++		tsf_bsae_port = rtw_hal_get_port(order1_iface);
++		tsf_sync_port = rtw_hal_get_port(order0_iface);
++		
++		/* FW set enable */
++		SET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, fw_eable);
++		/* TSF Sync offset */
++		SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset);
++		/* start time offset */
++		SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0));
++		/* interval */
++		SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
++		/* Early time to inform driver by C2H before switch channel */
++		SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
++		/* Port0 sync from Port1, not support multi-port */
++		SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, tsf_bsae_port);
++		SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, tsf_sync_port);
++	} else {
++		/* start time offset */
++		SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, mccobjpriv->start_time);
++		/* interval */
++		SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, mccobjpriv->interval);
++		/* Early time to inform driver by C2H before switch channel */
++		SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
++	}
++
++#ifdef CONFIG_MCC_MODE_DEBUG
++	{
++		u8 i = 0;
++
++		RTW_INFO("=========================\n");
++		RTW_INFO("NoA:\n");
++		for (i = 0; i < H2C_MCC_TIME_SETTING_LEN; i++)
++			pr_dbg("0x%x ", cmd[i]);
++		pr_dbg("\n");
++		RTW_INFO("=========================\n");
++	}
++#endif /* CONFIG_MCC_MODE_DEBUG */
++
++	rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd);
++}
++
++#ifndef CONFIG_MCC_MODE_V2
++static void rtw_hal_set_mcc_IQK_offload_cmd(PADAPTER padapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
++	struct mcc_adapter_priv *pmccadapriv = NULL;
++	_adapter *iface = NULL;
++	u8 cmd[H2C_MCC_IQK_PARAM_LEN] = {0}, bready = 0, i = 0, order = 0;
++	u16 TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0;
++	u8 total_rf_path = GET_HAL_SPEC(padapter)->rf_reg_path_num;
++	u8 rf_path_idx = 0, last_order = MAX_MCC_NUM - 1, last_rf_path_index = total_rf_path - 1;
++
++	/* by order, last order & last_rf_path_index must set ready bit = 1 */
++	for (i = 0; i < MAX_MCC_NUM; i++) {
++		iface = pmccobjpriv->iface[i];
++		if (iface == NULL)
++			continue;
++
++		pmccadapriv = &iface->mcc_adapterpriv;
++		order = pmccadapriv->order;
++
++		for (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx ++) {
++
++			_rtw_memset(cmd, 0, H2C_MCC_IQK_PARAM_LEN);
++			TX_X = pmccadapriv->mcc_iqk_arr[rf_path_idx].TX_X & 0x7ff;/* [10:0]  */
++			TX_Y = pmccadapriv->mcc_iqk_arr[rf_path_idx].TX_Y & 0x7ff;/* [10:0]  */
++			RX_X = pmccadapriv->mcc_iqk_arr[rf_path_idx].RX_X & 0x3ff;/* [9:0]  */
++			RX_Y = pmccadapriv->mcc_iqk_arr[rf_path_idx].RX_Y & 0x3ff;/* [9:0]  */
++
++			/* ready or not */
++			if (order == last_order && rf_path_idx == last_rf_path_index)
++				bready = 1;
++			else
++				bready = 0;
++
++			SET_H2CCMD_MCC_IQK_READY(cmd, bready);
++			SET_H2CCMD_MCC_IQK_ORDER(cmd, order);
++			SET_H2CCMD_MCC_IQK_PATH(cmd, rf_path_idx);
++
++			/* fill RX_X[7:0] to (cmd+1)[7:0] bitlen=8 */
++			SET_H2CCMD_MCC_IQK_RX_L(cmd, (u8)(RX_X & 0xff));
++			/* fill RX_X[9:8] to (cmd+2)[1:0] bitlen=2 */
++			SET_H2CCMD_MCC_IQK_RX_M1(cmd, (u8)((RX_X >> 8) & 0x03));
++			/* fill RX_Y[5:0] to (cmd+2)[7:2] bitlen=6 */
++			SET_H2CCMD_MCC_IQK_RX_M2(cmd, (u8)(RX_Y & 0x3f));
++			/* fill RX_Y[9:6] to (cmd+3)[3:0] bitlen=4 */
++			SET_H2CCMD_MCC_IQK_RX_H(cmd, (u8)((RX_Y >> 6) & 0x0f));
++
++
++			/* fill TX_X[7:0] to (cmd+4)[7:0] bitlen=8 */
++			SET_H2CCMD_MCC_IQK_TX_L(cmd, (u8)(TX_X & 0xff));
++			/* fill TX_X[10:8] to (cmd+5)[2:0] bitlen=3 */
++			SET_H2CCMD_MCC_IQK_TX_M1(cmd, (u8)((TX_X >> 8) & 0x07));
++			/* fill TX_Y[4:0] to (cmd+5)[7:3] bitlen=5 */
++			SET_H2CCMD_MCC_IQK_TX_M2(cmd, (u8)(TX_Y & 0x1f));
++			/* fill TX_Y[10:5] to (cmd+6)[5:0] bitlen=6 */
++			SET_H2CCMD_MCC_IQK_TX_H(cmd, (u8)((TX_Y >> 5) & 0x3f));
++
++#ifdef CONFIG_MCC_MODE_DEBUG
++			RTW_INFO("=========================\n");
++			RTW_INFO(FUNC_ADPT_FMT" IQK:\n", FUNC_ADPT_ARG(iface));
++			RTW_INFO("TX_X: 0x%02x\n", TX_X);
++			RTW_INFO("TX_Y: 0x%02x\n", TX_Y);
++			RTW_INFO("RX_X: 0x%02x\n", RX_X);
++			RTW_INFO("RX_Y: 0x%02x\n", RX_Y);
++			RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
++			RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
++			RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
++			RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
++			RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
++			RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
++			RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
++			RTW_INFO("=========================\n");
++#endif /* CONFIG_MCC_MODE_DEBUG */
++
++			rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_IQK_PARAM, H2C_MCC_IQK_PARAM_LEN, cmd);
++		}
++	}
++}
++#endif
++
++
++static void rtw_hal_set_mcc_macid_cmd(PADAPTER padapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_adapter_priv *pmccadapriv = NULL;
++	_adapter *iface = NULL;
++	u8 cmd[H2C_MCC_MACID_BITMAP_LEN] = {0}, i = 0, order = 0;
++	u16 bitmap = 0;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (iface == NULL)
++			continue;
++
++		pmccadapriv = &iface->mcc_adapterpriv;
++		if (pmccadapriv->role == MCC_ROLE_MAX)
++			continue;
++		
++		order = pmccadapriv->order;
++		bitmap = pmccadapriv->mcc_macid_bitmap;
++
++		if (order >= (H2C_MCC_MACID_BITMAP_LEN/2)) {
++			RTW_INFO(FUNC_ADPT_FMT" only support 3 interface at most(%d)\n"
++				, FUNC_ADPT_ARG(padapter), order);
++			continue;
++		}
++		SET_H2CCMD_MCC_MACID_BITMAP_L((cmd + order * 2), (u8)(bitmap & 0xff));
++		SET_H2CCMD_MCC_MACID_BITMAP_H((cmd + order * 2), (u8)((bitmap >> 8) & 0xff));
++	}
++
++#ifdef CONFIG_MCC_MODE_DEBUG
++	RTW_INFO("=========================\n");
++	RTW_INFO("MACID BITMAP: ");
++	for (i = 0; i < H2C_MCC_MACID_BITMAP_LEN; i++)
++		printk("0x%x ", cmd[i]);
++	printk("\n");
++	RTW_INFO("=========================\n");
++#endif /* CONFIG_MCC_MODE_DEBUG */
++	rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_MACID_BITMAP, H2C_MCC_MACID_BITMAP_LEN, cmd);
++}
++
++#ifdef CONFIG_MCC_MODE_V2
++static u8 get_pri_ch_idx_by_adapter(u8 center_ch, u8 channel, u8 bw, u8 ch_offset40)
++{
++	u8 pri_ch_idx = 0, chnl_offset80 = 0;
++
++	if (bw == CHANNEL_WIDTH_80) {
++		if (center_ch > channel)
++			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
++		else if (center_ch < channel)
++			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
++		else
++			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++	}
++
++	if (bw == CHANNEL_WIDTH_80) {
++		/* primary channel is at lower subband of 80MHz & 40MHz */
++		if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER))
++			pri_ch_idx = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
++		/* primary channel is at lower subband of 80MHz & upper subband of 40MHz */
++		else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER))
++			pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
++		/* primary channel is at upper subband of 80MHz & lower subband of 40MHz */
++		else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER))
++			pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
++		/* primary channel is at upper subband of 80MHz & upper subband of 40MHz */
++		else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER))
++			pri_ch_idx = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
++		else {
++			if (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER)
++				pri_ch_idx = VHT_DATA_SC_40_LOWER_OF_80MHZ;
++			else if (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER)
++				pri_ch_idx = VHT_DATA_SC_40_UPPER_OF_80MHZ;
++			else
++				RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
++		}
++	} else if (bw == CHANNEL_WIDTH_40) {
++		/* primary channel is at upper subband of 40MHz */
++		if (ch_offset40== HAL_PRIME_CHNL_OFFSET_UPPER)
++			pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
++		/* primary channel is at lower subband of 40MHz */
++		else if (ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER)
++			pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
++		else
++			RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
++	}
++
++	return  pri_ch_idx;
++}
++
++static void rtw_hal_set_mcc_ctrl_cmd_v2(PADAPTER padapter, u8 stop)
++{
++	u8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0;
++	u8 order = 0, totalnum = 0;
++	u8 center_ch = 0, pri_ch_idx = 0, bw = 0;
++	u8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0;
++	u8 dis_sw_retry = 0, null_early_time=2, tsfx = 0, update_parm = 0;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
++	struct mcc_adapter_priv *mccadapriv = NULL;
++	struct mlme_ext_priv *pmlmeext = NULL;
++	struct mlme_ext_info *pmlmeinfo = NULL;
++	_adapter *iface = NULL;
++
++	RTW_INFO(FUNC_ADPT_FMT": stop=%d\n", FUNC_ADPT_ARG(padapter), stop);
++
++	for (i = 0; i < MAX_MCC_NUM; i++) {
++		iface = pmccobjpriv->iface[i];
++		if (iface == NULL)
++			continue;
++
++		if (stop) {
++			if (iface != padapter)
++				continue;
++		}
++
++		mccadapriv = &iface->mcc_adapterpriv;
++		order = mccadapriv->order;
++
++		if (!stop)
++			totalnum = MAX_MCC_NUM;
++		else
++			totalnum = 0xff; /* 0xff means stop */
++
++		pmlmeext = &iface->mlmeextpriv;
++		center_ch = rtw_get_center_ch(pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
++		pri_ch_idx = get_pri_ch_idx_by_adapter(center_ch, pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
++		bw = pmlmeext->cur_bwmode;
++		duration = mccadapriv->mcc_duration;
++		role = mccadapriv->role;
++
++		incurch = _FALSE;
++		dis_sw_retry = _TRUE;
++
++		/* STA/GC TX NULL data to inform AP/GC for ps mode */
++		switch (role) {
++		case MCC_ROLE_GO:
++		case MCC_ROLE_AP:
++			distxnull = MCC_DISABLE_TX_NULL;
++			break;
++		case MCC_ROLE_GC:
++			set_channel_bwmode(iface, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
++			distxnull = MCC_ENABLE_TX_NULL;
++			break;
++		case MCC_ROLE_STA:
++			distxnull = MCC_ENABLE_TX_NULL;
++			break;
++		}
++
++		null_early_time = mccadapriv->null_early;
++
++		c2hrpt = MCC_C2H_REPORT_ALL_STATUS;
++		tsfx = rtw_hal_get_port(iface);
++		update_parm = 0;
++
++		SET_H2CCMD_MCC_CTRL_V2_ORDER(cmd, order);
++		SET_H2CCMD_MCC_CTRL_V2_TOTALNUM(cmd, totalnum);
++		SET_H2CCMD_MCC_CTRL_V2_CENTRAL_CH(cmd, center_ch);
++		SET_H2CCMD_MCC_CTRL_V2_PRIMARY_CH(cmd, pri_ch_idx);
++		SET_H2CCMD_MCC_CTRL_V2_BW(cmd, bw);
++		SET_H2CCMD_MCC_CTRL_V2_DURATION(cmd, duration);
++		SET_H2CCMD_MCC_CTRL_V2_ROLE(cmd, role);
++		SET_H2CCMD_MCC_CTRL_V2_INCURCH(cmd, incurch);
++		SET_H2CCMD_MCC_CTRL_V2_DIS_SW_RETRY(cmd, dis_sw_retry);
++		SET_H2CCMD_MCC_CTRL_V2_DISTXNULL(cmd, distxnull);
++		SET_H2CCMD_MCC_CTRL_V2_C2HRPT(cmd, c2hrpt);
++		SET_H2CCMD_MCC_CTRL_V2_TSFX(cmd, tsfx);
++		SET_H2CCMD_MCC_CTRL_V2_NULL_EARLY(cmd, null_early_time);
++		SET_H2CCMD_MCC_CTRL_V2_UPDATE_PARM(cmd, update_parm);
++
++#ifdef CONFIG_MCC_MODE_DEBUG
++		RTW_INFO("=========================\n");
++		RTW_INFO(FUNC_ADPT_FMT" MCC INFO:\n", FUNC_ADPT_ARG(iface));
++		RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
++		RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
++		RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
++		RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
++		RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
++		RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
++		RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
++		RTW_INFO("=========================\n");
++#endif /* CONFIG_MCC_MODE_DEBUG */
++
++		rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL_V2, H2C_MCC_CTRL_LEN, cmd);
++	}
++}
++
++#else
++static void rtw_hal_set_mcc_ctrl_cmd_v1(PADAPTER padapter, u8 stop)
++{
++	u8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0;
++	u8 order = 0, totalnum = 0, chidx = 0, bw = 0, bw40sc = 0, bw80sc = 0;
++	u8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0, chscan = 0;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
++	struct mcc_adapter_priv *mccadapriv = NULL;
++	struct mlme_ext_priv *pmlmeext = NULL;
++	struct mlme_ext_info *pmlmeinfo = NULL;
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++	_adapter *iface = NULL;
++
++	RTW_INFO(FUNC_ADPT_FMT": stop=%d\n", FUNC_ADPT_ARG(padapter), stop);
++
++	for (i = 0; i < MAX_MCC_NUM; i++) {
++		iface = pmccobjpriv->iface[i];
++		if (iface == NULL)
++			continue;
++
++		if (stop) {
++			if (iface != padapter)
++				continue;
++		}
++
++		mccadapriv = &iface->mcc_adapterpriv;
++		order = mccadapriv->order;
++
++		if (!stop)
++			totalnum = MAX_MCC_NUM;
++		else
++			totalnum = 0xff; /* 0xff means stop */
++
++		pmlmeext = &iface->mlmeextpriv;
++		chidx = pmlmeext->cur_channel;
++		bw = pmlmeext->cur_bwmode;
++		bw40sc = pmlmeext->cur_ch_offset;
++
++		/* decide 80 band width offset */
++		if (bw == CHANNEL_WIDTH_80) {
++			u8 center_ch = rtw_get_center_ch(chidx, bw, bw40sc);
++
++			if (center_ch > chidx)
++				bw80sc = HAL_PRIME_CHNL_OFFSET_LOWER;
++			else if (center_ch < chidx)
++				bw80sc = HAL_PRIME_CHNL_OFFSET_UPPER;
++			else
++				bw80sc = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		} else
++			bw80sc = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++		duration = mccadapriv->mcc_duration;
++		role = mccadapriv->role;
++
++		incurch = _FALSE;
++
++		if (IS_HARDWARE_TYPE_8812(padapter))
++			rfetype = pHalData->rfe_type; /* RFETYPE (only for 8812)*/
++		else
++			rfetype = 0;
++
++		/* STA/GC TX NULL data to inform AP/GC for ps mode */
++		switch (role) {
++		case MCC_ROLE_GO:
++		case MCC_ROLE_AP:
++			distxnull = MCC_DISABLE_TX_NULL;
++			break;
++		case MCC_ROLE_GC:
++		case MCC_ROLE_STA:
++			distxnull = MCC_ENABLE_TX_NULL;
++			break;
++		}
++
++		c2hrpt = MCC_C2H_REPORT_ALL_STATUS;
++		chscan = MCC_CHIDX;
++
++		SET_H2CCMD_MCC_CTRL_ORDER(cmd, order);
++		SET_H2CCMD_MCC_CTRL_TOTALNUM(cmd, totalnum);
++		SET_H2CCMD_MCC_CTRL_CHIDX(cmd, chidx);
++		SET_H2CCMD_MCC_CTRL_BW(cmd, bw);
++		SET_H2CCMD_MCC_CTRL_BW40SC(cmd, bw40sc);
++		SET_H2CCMD_MCC_CTRL_BW80SC(cmd, bw80sc);
++		SET_H2CCMD_MCC_CTRL_DURATION(cmd, duration);
++		SET_H2CCMD_MCC_CTRL_ROLE(cmd, role);
++		SET_H2CCMD_MCC_CTRL_INCURCH(cmd, incurch);
++		SET_H2CCMD_MCC_CTRL_RFETYPE(cmd, rfetype);
++		SET_H2CCMD_MCC_CTRL_DISTXNULL(cmd, distxnull);
++		SET_H2CCMD_MCC_CTRL_C2HRPT(cmd, c2hrpt);
++		SET_H2CCMD_MCC_CTRL_CHSCAN(cmd, chscan);
++
++#ifdef CONFIG_MCC_MODE_DEBUG
++		RTW_INFO("=========================\n");
++		RTW_INFO(FUNC_ADPT_FMT" MCC INFO:\n", FUNC_ADPT_ARG(iface));
++		RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
++		RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
++		RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
++		RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
++		RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
++		RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
++		RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
++		RTW_INFO("=========================\n");
++#endif /* CONFIG_MCC_MODE_DEBUG */
++
++		rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL, H2C_MCC_CTRL_LEN, cmd);
++	}
++}
++#endif
++
++static void rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter, u8 stop)
++{
++	#ifdef CONFIG_MCC_MODE_V2
++		/* new cmd 0x17 */
++		rtw_hal_set_mcc_ctrl_cmd_v2(padapter, stop);
++	#else
++		/* old cmd 0x18 */
++		rtw_hal_set_mcc_ctrl_cmd_v1(padapter, stop);
++	#endif
++}
++
++static u8 check_mcc_support(PADAPTER adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	u8 sta_linked_num = DEV_STA_LD_NUM(dvobj);
++	u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);
++	u8 ap_num = DEV_AP_NUM(dvobj);
++	u8 ret = _FAIL;
++
++	RTW_INFO("[MCC] sta_linked_num=%d, starting_ap_num=%d,ap_num=%d\n",
++		sta_linked_num, starting_ap_num, ap_num);
++
++	/* case for sta + sta case  */
++	if (sta_linked_num == MAX_MCC_NUM) {
++		ret = _SUCCESS;
++		goto exit;
++	}
++
++	/* case for starting AP + linked sta */
++	if ((starting_ap_num + sta_linked_num) == MAX_MCC_NUM) {
++		ret = _SUCCESS;
++		goto exit;
++	}
++
++	/* case for started AP + linked sta */
++	if ((ap_num + sta_linked_num) == MAX_MCC_NUM) {
++		ret = _SUCCESS;
++		goto exit;
++	}
++
++exit:
++		return ret;
++}
++
++static void rtw_hal_mcc_start_prehdl(PADAPTER padapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	_adapter *iface = NULL;
++	struct mcc_adapter_priv *mccadapriv = NULL;
++	u8 i = 1;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (iface == NULL)
++			continue;
++
++		mccadapriv = &iface->mcc_adapterpriv;
++		mccadapriv->role = MCC_ROLE_MAX;
++	}
++
++#ifdef CONFIG_RTL8822C
++	if (IS_HARDWARE_TYPE_8822C(padapter)) {
++		HAL_DATA_TYPE *hal = GET_HAL_DATA(padapter);
++		struct dm_struct *dm = &hal->odmpriv;
++		
++		odm_cmn_info_update(dm, ODM_CMNINFO_IS_DOWNLOAD_FW, hal->bFWReady);
++	}
++#endif
++}
++
++static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status)
++{
++	u8 ret = _SUCCESS, enable_tsf_auto_sync = _FALSE;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
++
++	if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
++		rtw_warn_on(1);
++		RTW_INFO("PS mode is not active before start mcc, force exit ps mode\n");
++		LeaveAllPowerSaveModeDirect(padapter);
++	}
++
++	if (check_mcc_support(padapter) == _FAIL) {
++		ret = _FAIL;
++		goto exit;
++	}
++
++	rtw_hal_mcc_start_prehdl(padapter);
++
++	/* configure mcc switch channel setting */
++	rtw_hal_config_mcc_switch_channel_setting(padapter);
++
++	if (rtw_hal_decide_mcc_role(padapter) == _FAIL) {
++		ret = _FAIL;
++		goto exit;
++	}
++
++	/* set mcc status to indicate process mcc start setting */
++	rtw_hal_set_mcc_status(padapter, MCC_STATUS_PROCESS_MCC_START_SETTING);
++
++	/* only download rsvd page for connect */
++	if (status == MCC_SETCMD_STATUS_START_CONNECT) {
++		/* download mcc rsvd page */
++		rtw_hal_set_fw_mcc_rsvd_page(padapter);
++		rtw_hal_set_mcc_rsvdpage_cmd(padapter);
++	}
++
++	/* configure time setting */
++	rtw_hal_set_mcc_time_setting_cmd(padapter);
++
++#ifndef CONFIG_MCC_MODE_V2
++	/* IQK value offload */
++	rtw_hal_set_mcc_IQK_offload_cmd(padapter);
++#endif
++
++	/* set mac id to fw */
++	rtw_hal_set_mcc_macid_cmd(padapter);
++#ifdef CONFIG_HW_P0_TSF_SYNC
++	if (dvobj->p0_tsf.sync_port != MAX_HW_PORT ) {
++		/* disable tsf auto sync */
++		RTW_INFO("[MCC] disable HW TSF sync\n");
++		rtw_hal_set_hwreg(padapter, HW_VAR_TSF_AUTO_SYNC, &enable_tsf_auto_sync);
++	} else {
++		RTW_INFO("[MCC] already disable HW TSF sync\n");
++	}
++#endif
++	/* set mcc parameter  */
++	rtw_hal_set_mcc_ctrl_cmd(padapter, _FALSE);
++
++exit:
++	return ret;
++}
++
++static void rtw_hal_set_mcc_stop_setting(PADAPTER padapter, u8 status)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *mccobjpriv = &dvobj->mcc_objpriv;
++	_adapter *iface = NULL;
++	struct mcc_adapter_priv *mccadapriv = NULL;
++	u8 i = 0;
++	/*
++	 * when adapter disconnect, stop mcc mod
++	 * total=0xf means stop mcc mode
++	 */
++
++	switch (status) {
++	default:
++		/* let fw switch to other interface channel */
++		for (i = 0; i < MAX_MCC_NUM; i++) {
++			iface = mccobjpriv->iface[i];
++			if (iface == NULL)
++				continue;
++
++			mccadapriv = &iface->mcc_adapterpriv;
++
++			/* use other interface to set cmd */
++			if (iface != padapter) {
++				rtw_hal_set_mcc_ctrl_cmd(iface, _TRUE);
++				break;
++			}
++		}
++		break;
++	}
++}
++
++static void rtw_hal_mcc_status_hdl(PADAPTER padapter, u8 status)
++{
++	switch (status) {
++	case MCC_SETCMD_STATUS_STOP_DISCONNECT:
++		rtw_hal_clear_mcc_status(padapter, MCC_STATUS_NEED_MCC | MCC_STATUS_DOING_MCC);
++		break;
++	case MCC_SETCMD_STATUS_STOP_SCAN_START:
++		rtw_hal_set_mcc_status(padapter, MCC_STATUS_NEED_MCC);
++		rtw_hal_clear_mcc_status(padapter, MCC_STATUS_DOING_MCC);
++		break;
++
++	case MCC_SETCMD_STATUS_START_CONNECT:
++	case MCC_SETCMD_STATUS_START_SCAN_DONE:
++		rtw_hal_set_mcc_status(padapter, MCC_STATUS_NEED_MCC | MCC_STATUS_DOING_MCC);
++		break;
++	default:
++		RTW_INFO(FUNC_ADPT_FMT" error status(%d)\n", FUNC_ADPT_ARG(padapter), status);
++		break;
++	}
++}
++
++static void rtw_hal_mcc_stop_posthdl(PADAPTER padapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
++	struct mcc_adapter_priv *mccadapriv = NULL;
++	_adapter *iface = NULL;
++	PHAL_DATA_TYPE hal;
++	u8 i = 0;
++	u8 enable_rx_bar = _FALSE;
++
++	hal = GET_HAL_DATA(padapter);
++
++	for (i = 0; i < MAX_MCC_NUM; i++) {
++		iface = mccobjpriv->iface[i];
++		if (iface == NULL)
++			continue;
++
++		/* release network queue */
++		rtw_netif_wake_queue(iface->pnetdev);
++		mccadapriv = &iface->mcc_adapterpriv;
++		mccadapriv->mcc_tx_bytes_from_kernel = 0;
++		mccadapriv->mcc_last_tx_bytes_from_kernel = 0;
++		mccadapriv->mcc_tx_bytes_to_port = 0;
++
++		if (mccadapriv->role == MCC_ROLE_GO)
++			rtw_hal_mcc_remove_go_p2p_ie(iface);
++
++#ifdef CONFIG_TDLS
++		if (MLME_IS_STA(iface)) {
++			if (mccadapriv->backup_tdls_en) {
++				rtw_enable_tdls_func(iface);
++				RTW_INFO("%s: Disable MCC, Enable TDLS\n", __func__);
++				mccadapriv->backup_tdls_en = _FALSE;
++			}
++		}
++#endif /* CONFIG_TDLS */
++
++		mccadapriv->role = MCC_ROLE_MAX;
++		mccobjpriv->iface[i] = NULL;
++	}
++
++	/* force switch channel */
++	hal->current_channel = 0;
++	hal->current_channel_bw = CHANNEL_WIDTH_MAX;
++	#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++	rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_STOP, NULL);
++	#endif
++
++#ifdef CONFIG_RTL8822C
++	if (IS_HARDWARE_TYPE_8822C(padapter)) {
++		HAL_DATA_TYPE *hal = GET_HAL_DATA(padapter);
++		struct dm_struct *dm = &hal->odmpriv;
++		
++		odm_cmn_info_update(dm, ODM_CMNINFO_IS_DOWNLOAD_FW, _FALSE);
++	}
++#endif
++}
++
++static void rtw_hal_mcc_start_posthdl(PADAPTER padapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
++	struct mcc_adapter_priv *mccadapriv = NULL;
++	struct pwrctrl_priv	*pwrpriv = adapter_to_pwrctl(padapter);
++	_adapter *iface = NULL;
++	u8 i = 0, order = 0;
++	u8 enable_rx_bar = _TRUE;
++
++	for (i = 0; i < MAX_MCC_NUM; i++) {
++		iface = mccobjpriv->iface[i];
++		if (iface == NULL)
++			continue;
++
++		mccadapriv = &iface->mcc_adapterpriv;
++		if (mccadapriv->role == MCC_ROLE_MAX)
++			continue;
++		
++		mccadapriv->mcc_tx_bytes_from_kernel = 0;
++		mccadapriv->mcc_last_tx_bytes_from_kernel = 0;
++		mccadapriv->mcc_tx_bytes_to_port = 0;
++
++#ifdef CONFIG_TDLS
++		if (MLME_IS_STA(iface)) {
++			if (rtw_is_tdls_enabled(iface)) {
++				mccadapriv->backup_tdls_en = _TRUE;
++				rtw_disable_tdls_func(iface, _TRUE);
++				RTW_INFO("%s: Enable MCC, Disable TDLS\n", __func__);
++			}
++		}
++#endif /* CONFIG_TDLS */
++	}
++	#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++	rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_START, NULL);
++	#endif
++}
++
++/*
++ * rtw_hal_set_mcc_setting - set mcc setting
++ * @padapter: currnet padapter to stop/start MCC
++ * @stop: stop mcc or not
++ * @return val: 1 for SUCCESS, 0 for fail
++ */
++static u8 rtw_hal_set_mcc_setting(PADAPTER padapter, u8 status)
++{
++	u8 ret = _FAIL;
++	struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
++	u8 stop = (status < MCC_SETCMD_STATUS_START_CONNECT) ? _TRUE : _FALSE;
++	systime start_time = rtw_get_current_time();
++
++	RTW_INFO("===> "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++	rtw_sctx_init(&pmccobjpriv->mcc_sctx, MCC_EXPIRE_TIME);
++	pmccobjpriv->mcc_c2h_status = MCC_RPT_MAX;
++
++	if (stop == _FALSE) {
++		/* handle mcc start */
++		if (rtw_hal_set_mcc_start_setting(padapter, status) == _FAIL)
++			goto exit;
++
++		/* wait for C2H */
++		if (!rtw_sctx_wait(&pmccobjpriv->mcc_sctx, __func__))
++			RTW_INFO(FUNC_ADPT_FMT": wait for mcc start C2H time out\n", FUNC_ADPT_ARG(padapter));
++		else
++			ret = _SUCCESS;
++
++		if (ret == _SUCCESS) {
++			RTW_INFO(FUNC_ADPT_FMT": mcc start sucecssfully\n", FUNC_ADPT_ARG(padapter));
++			rtw_hal_mcc_status_hdl(padapter, status);
++			rtw_hal_mcc_start_posthdl(padapter);
++		}
++	} else {
++
++		/* set mcc status to indicate process mcc start setting */
++		rtw_hal_set_mcc_status(padapter, MCC_STATUS_PROCESS_MCC_STOP_SETTING);
++
++		/* handle mcc stop */
++		rtw_hal_set_mcc_stop_setting(padapter, status);
++
++		/* wait for C2H */
++		if (!rtw_sctx_wait(&pmccobjpriv->mcc_sctx, __func__))
++			RTW_INFO(FUNC_ADPT_FMT": wait for mcc stop C2H time out\n", FUNC_ADPT_ARG(padapter));
++		else {
++			ret = _SUCCESS;
++			rtw_hal_mcc_status_hdl(padapter, status);
++			rtw_hal_mcc_stop_posthdl(padapter);
++		}
++	}
++
++exit:
++	/* clear mcc status */
++	rtw_hal_clear_mcc_status(padapter
++		, MCC_STATUS_PROCESS_MCC_START_SETTING | MCC_STATUS_PROCESS_MCC_STOP_SETTING);
++
++	RTW_INFO(FUNC_ADPT_FMT" in %dms <===\n"
++		, FUNC_ADPT_ARG(padapter), rtw_get_passing_time_ms(start_time));
++	return ret;
++}
++
++/**
++ * rtw_hal_mcc_check_case_not_limit_traffic - handler flow ctrl for special case
++ * @cur_iface: fw stay channel setting of this iface
++ * @next_iface: fw will swich channel setting of this iface
++ */
++static void rtw_hal_mcc_check_case_not_limit_traffic(PADAPTER cur_iface, PADAPTER next_iface)
++{
++	u8 cur_bw = cur_iface->mlmeextpriv.cur_bwmode;
++	u8 next_bw = next_iface->mlmeextpriv.cur_bwmode;
++
++	/* for both interface are VHT80, doesn't limit_traffic according to iperf results */
++	if (cur_bw == CHANNEL_WIDTH_80 && next_bw == CHANNEL_WIDTH_80) {
++		cur_iface->mcc_adapterpriv.mcc_tp_limit = _FALSE;
++		next_iface->mcc_adapterpriv.mcc_tp_limit = _FALSE;
++	}
++}
++
++
++/**
++ * rtw_hal_mcc_sw_ch_fw_notify_hdl - handler flow ctrl
++ */
++static void rtw_hal_mcc_sw_ch_fw_notify_hdl(PADAPTER padapter)
++{
++	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
++	struct mcc_adapter_priv *cur_mccadapriv = NULL, *next_mccadapriv = NULL;
++	_adapter *iface = NULL, *cur_iface = NULL, *next_iface = NULL;
++	struct registry_priv *preg = &padapter->registrypriv;
++	u8 cur_op_ch = pdvobjpriv->oper_channel;
++	u8 i = 0, iface_num = pdvobjpriv->iface_nums, cur_order = 0, next_order = 0;
++	static u8 cnt = 1;
++	u32 single_tx_cri = preg->rtw_mcc_single_tx_cri;
++
++	for (i = 0; i < iface_num; i++) {
++		iface = pdvobjpriv->padapters[i];
++		if (iface == NULL)
++			continue;
++
++		if (cur_op_ch == iface->mlmeextpriv.cur_channel) {
++			cur_iface = iface;
++			cur_mccadapriv = &cur_iface->mcc_adapterpriv;
++			cur_order = cur_mccadapriv->order;
++			next_order = (cur_order + 1) % iface_num;
++			next_iface = pmccobjpriv->iface[next_order];
++			next_mccadapriv = &next_iface->mcc_adapterpriv;
++			break;
++		}
++	}
++
++	if (cur_iface == NULL || next_iface == NULL) {
++		RTW_ERR("cur_iface=%p,next_iface=%p\n", cur_iface, next_iface);
++		rtw_warn_on(1);
++		return;
++	}
++
++	/* check other interface tx busy traffic or not under every 2 switch channel notify(Mbits/100ms) */
++	if (cnt == 2) {
++		cur_mccadapriv->mcc_tp = (cur_mccadapriv->mcc_tx_bytes_from_kernel
++			- cur_mccadapriv->mcc_last_tx_bytes_from_kernel) * 10 * 8 / 1024 / 1024;
++		cur_mccadapriv->mcc_last_tx_bytes_from_kernel = cur_mccadapriv->mcc_tx_bytes_from_kernel;
++
++		next_mccadapriv->mcc_tp = (next_mccadapriv->mcc_tx_bytes_from_kernel
++			- next_mccadapriv->mcc_last_tx_bytes_from_kernel) * 10 * 8 / 1024 / 1024;
++		next_mccadapriv->mcc_last_tx_bytes_from_kernel = next_mccadapriv->mcc_tx_bytes_from_kernel;
++
++		cnt = 1;
++	} else
++		cnt = 2;
++
++	/* check single TX or cuncurrnet TX */
++	if (next_mccadapriv->mcc_tp < single_tx_cri) {
++		/* single TX, does not stop */
++		cur_mccadapriv->mcc_tx_stop = _FALSE;
++		cur_mccadapriv->mcc_tp_limit = _FALSE;
++	} else {
++		/* concurrent TX, stop */
++		cur_mccadapriv->mcc_tx_stop = _TRUE;
++		cur_mccadapriv->mcc_tp_limit = _TRUE;
++	}
++
++	if (cur_mccadapriv->mcc_tp < single_tx_cri) {
++		next_mccadapriv->mcc_tx_stop  = _FALSE;
++		next_mccadapriv->mcc_tp_limit = _FALSE;
++	} else {
++		next_mccadapriv->mcc_tx_stop = _FALSE;
++		next_mccadapriv->mcc_tp_limit = _TRUE;
++		next_mccadapriv->mcc_tx_bytes_to_port = 0;
++	}
++
++	/* stop current iface kernel queue or not */
++	if (cur_mccadapriv->mcc_tx_stop)
++		rtw_netif_stop_queue(cur_iface->pnetdev);
++	else
++		rtw_netif_wake_queue(cur_iface->pnetdev);
++
++	/* stop next iface kernel queue or not */
++	if (next_mccadapriv->mcc_tx_stop)
++		rtw_netif_stop_queue(next_iface->pnetdev);
++	else
++		rtw_netif_wake_queue(next_iface->pnetdev);
++
++	/* start xmit tasklet */
++	rtw_os_xmit_schedule(next_iface);
++
++	rtw_hal_mcc_check_case_not_limit_traffic(cur_iface, next_iface);
++
++	if (0) {
++		RTW_INFO("order:%d, mcc_tx_stop:%d, mcc_tp:%d\n",
++			cur_mccadapriv->order, cur_mccadapriv->mcc_tx_stop, cur_mccadapriv->mcc_tp);
++		dump_os_queue(0, cur_iface);
++		RTW_INFO("order:%d, mcc_tx_stop:%d, mcc_tp:%d\n",
++			next_mccadapriv->order, next_mccadapriv->mcc_tx_stop, next_mccadapriv->mcc_tp);
++		dump_os_queue(0, next_iface);
++	}
++}
++
++static void rtw_hal_mcc_update_noa_start_time_hdl(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
++{
++	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
++	struct mcc_adapter_priv *pmccadapriv = NULL;
++	PADAPTER iface = NULL;
++	u8 i = 0;
++	u8 policy_idx = pmccobjpriv->policy_index;
++	u8 noa_tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
++	u8 noa_start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
++	
++	for (i = 0; i < pdvobjpriv->iface_nums; i++) {
++		iface = pdvobjpriv->padapters[i];
++		if (iface == NULL)
++			continue;
++		
++		pmccadapriv = &iface->mcc_adapterpriv;
++		if (pmccadapriv->role == MCC_ROLE_MAX)
++			continue;
++
++		/* GO & channel match */
++		if (pmccadapriv->role == MCC_ROLE_GO) {
++			/* convert GO TBTT from FW to noa_start_time(TU convert to mircosecond) */
++			pmccadapriv->noa_start_time = RTW_GET_LE32(tmpBuf + 2) + noa_start_time_offset * TU;
++
++			if (0) {
++				RTW_INFO("TBTT:0x%02x\n", RTW_GET_LE32(tmpBuf + 2));
++				RTW_INFO("noa_tsf_sync_offset:%d, noa_start_time_offset:%d\n", noa_tsf_sync_offset, noa_start_time_offset);
++				RTW_INFO(FUNC_ADPT_FMT"buf=0x%02x:0x%02x:0x%02x:0x%02x, noa_start_time=0x%02x\n"
++					, FUNC_ADPT_ARG(iface)
++					, tmpBuf[2]
++					, tmpBuf[3]
++					, tmpBuf[4]
++					, tmpBuf[5]
++					,pmccadapriv->noa_start_time);
++				}
++
++			rtw_hal_mcc_update_go_p2p_ie(iface);
++
++			break;
++		}
++	}
++
++}
++
++static u8 mcc_get_reg_hdl(PADAPTER adapter, const u8 *val)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
++	_adapter *cur_iface = NULL;
++	u8 ret = _SUCCESS;
++	u8 cur_order = 0;
++	#ifdef CONFIG_RTL8822C
++	u16 dbg_reg[DBG_MCC_REG_NUM] = {0x4d4,0x522,0x1d70};
++	#else
++	u16 dbg_reg[DBG_MCC_REG_NUM] = {0x4d4,0x522,0xc50,0xe50};
++	#endif
++	u16 dbg_rf_reg[DBG_MCC_RF_REG_NUM] = {0x18};
++	u8 i;
++	u32 reg_val;
++	u8 path = 0, path_nums = 0;
++
++	if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
++		ret = _FAIL;
++		goto exit;
++	}
++
++	if (!val)
++		cur_order = 0xff;
++	else
++		cur_order = *val;
++
++	if (cur_order >= MAX_MCC_NUM && cur_order != 0xff) {
++		RTW_ERR("%s: cur_order=%d\n", __func__, cur_order);
++		ret = _FAIL;
++		goto exit;
++	}
++
++	path_nums = hal_spec->rf_reg_path_num;
++	if (cur_order == 0xff)
++		cur_iface = adapter;
++	else
++		cur_iface = mccobjpriv->iface[cur_order];
++
++	if (!cur_iface) {
++		RTW_ERR("%s: cur_iface = NULL,  cur_order=%d\n", __func__, cur_order);
++		ret = _FAIL;
++		goto exit;
++	}
++
++	_enter_critical_mutex(&mccobjpriv->mcc_dbg_reg_mutex, NULL);
++	if (!RTW_CANNOT_IO(adapter)) {
++		/* RTW_INFO("=================================\n");
++		RTW_INFO(ADPT_FMT": cur_order:%d\n", ADPT_ARG(cur_iface), cur_order); */
++		
++		for (i = 0; i < ARRAY_SIZE(dbg_reg); i++) {
++			reg_val = rtw_read32(adapter, dbg_reg[i]);
++			mccobjpriv->dbg_reg[i] = dbg_reg[i];
++			mccobjpriv->dbg_reg_val[i] = reg_val;
++			/* RTW_PRINT("REG_%X:0x%08x\n", dbg_reg[i], reg_val); */
++		}
++		for (i = 0; i < ARRAY_SIZE(dbg_rf_reg); i++) {
++			for (path = 0; path < path_nums; path++) {
++				reg_val = rtw_hal_read_rfreg(adapter, path, dbg_rf_reg[i], 0xffffffff);
++				/* RTW_PRINT("RF_PATH_%d_REG_%X:0x%08x\n",
++					path, dbg_rf_reg[i], reg_val); */
++				mccobjpriv->dbg_rf_reg[i] = dbg_rf_reg[i];
++				mccobjpriv->dbg_rf_reg_val[i][path] = reg_val;
++			}
++		}
++	}
++	_exit_critical_mutex(&mccobjpriv->mcc_dbg_reg_mutex, NULL);
++
++exit:
++	return ret;
++}
++
++static u8 mcc_get_reg_cmd(_adapter *adapter, u8 cur_order)
++{
++	struct cmd_obj *cmdobj;
++	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++	u8 *mcc_cur_order = NULL;
++	u8 res = _SUCCESS;
++
++	
++	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (cmdobj == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	mcc_cur_order = rtw_zmalloc(sizeof(u8));
++	if (mcc_cur_order == NULL) {
++		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
++		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm->ec_id = MCC_CMD_WK_CID;
++	pdrvextra_cmd_parm->type = MCC_GET_DBG_REG_WK_CID;
++	pdrvextra_cmd_parm->size = 1;
++	pdrvextra_cmd_parm->pbuf = mcc_cur_order;
++
++	_rtw_memcpy(mcc_cur_order, &cur_order, 1);
++
++	init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++	res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
++
++exit:
++	return res;
++}
++
++static void rtw_hal_mcc_rpt_tsf_hdl(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
++{
++	struct dvobj_priv *dvobjpriv = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
++	struct submit_ctx *mcc_tsf_req_sctx = &mccobjpriv->mcc_tsf_req_sctx;
++	struct mcc_adapter_priv *mccadapriv = NULL;
++	_adapter *iface = NULL;
++	u8 order = 0;
++
++	order = mccobjpriv->mcc_tsf_req_sctx_order;
++	iface = mccobjpriv->iface[order];
++	mccadapriv = &iface->mcc_adapterpriv;
++	mccadapriv->tsf = RTW_GET_LE64(tmpBuf + 2);
++
++
++	if (0)
++		RTW_INFO(FUNC_ADPT_FMT" TSF(order:%d):0x%02llx\n", FUNC_ADPT_ARG(iface), mccadapriv->order, mccadapriv->tsf);
++
++	if (mccadapriv->order == (MAX_MCC_NUM - 1))
++		rtw_sctx_done(&mcc_tsf_req_sctx);
++	else
++		mccobjpriv->mcc_tsf_req_sctx_order ++;
++
++}
++
++/**
++ * rtw_hal_mcc_c2h_handler - mcc c2h handler
++ */
++void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
++{
++	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
++	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
++	struct submit_ctx *mcc_sctx = &pmccobjpriv->mcc_sctx;
++	_adapter *cur_adapter = NULL;
++	u8 cur_ch = 0, cur_bw = 0, cur_ch_offset = 0;
++	_irqL irqL;
++
++	/* RTW_INFO("[length]=%d, [C2H data]="MAC_FMT"\n", buflen, MAC_ARG(tmpBuf)); */
++	/* To avoid reg is set, but driver recive c2h to set wrong oper_channel */
++	if (MCC_RPT_STOPMCC == pmccobjpriv->mcc_c2h_status) {
++		RTW_INFO(FUNC_ADPT_FMT" MCC alread stops return\n", FUNC_ADPT_ARG(padapter));
++		return;
++	}
++
++	_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
++	pmccobjpriv->mcc_c2h_status = tmpBuf[0];
++	pmccobjpriv->current_order = tmpBuf[1];
++	cur_adapter = pmccobjpriv->iface[pmccobjpriv->current_order];
++	cur_ch = cur_adapter->mlmeextpriv.cur_channel;
++	cur_bw = cur_adapter->mlmeextpriv.cur_bwmode;
++	cur_ch_offset = cur_adapter->mlmeextpriv.cur_ch_offset;
++	rtw_set_oper_ch(cur_adapter, cur_ch);
++	rtw_set_oper_bw(cur_adapter, cur_bw);
++	rtw_set_oper_choffset(cur_adapter, cur_ch_offset);
++	_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
++
++	if (0)
++		RTW_INFO("%d,order:%d,TSF:0x%llx\n", tmpBuf[0], tmpBuf[1], RTW_GET_LE64(tmpBuf + 2));
++	
++	switch (pmccobjpriv->mcc_c2h_status) {
++	case MCC_RPT_SUCCESS:
++		_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
++		pmccobjpriv->cur_mcc_success_cnt++;
++		rtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _FALSE);
++		mcc_get_reg_cmd(padapter, pmccobjpriv->current_order);
++		_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
++		break;
++	case MCC_RPT_TXNULL_FAIL:
++		RTW_INFO("[MCC] TXNULL FAIL\n");
++		break;
++	case MCC_RPT_STOPMCC:
++		RTW_INFO("[MCC] MCC stop\n");
++		pmccobjpriv->mcc_c2h_status = MCC_RPT_STOPMCC;
++		rtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _TRUE);
++		rtw_sctx_done(&mcc_sctx);
++		break;
++	case MCC_RPT_READY:
++		_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
++		/* initialize counter & time */
++		pmccobjpriv->mcc_launch_time = rtw_get_current_time();
++		pmccobjpriv->mcc_c2h_status = MCC_RPT_READY;
++		pmccobjpriv->cur_mcc_success_cnt = 0;
++		pmccobjpriv->prev_mcc_success_cnt = 0;
++		pmccobjpriv->mcc_tolerance_time = MCC_TOLERANCE_TIME;
++		_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
++
++		RTW_INFO("[MCC] MCC ready\n");
++		rtw_sctx_done(&mcc_sctx);
++		break;
++	case MCC_RPT_SWICH_CHANNEL_NOTIFY:
++		rtw_hal_mcc_sw_ch_fw_notify_hdl(padapter);
++		break;
++	case MCC_RPT_UPDATE_NOA_START_TIME:
++		rtw_hal_mcc_update_noa_start_time_hdl(padapter, buflen, tmpBuf);
++		break;
++	case MCC_RPT_TSF:
++		_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
++		rtw_hal_mcc_rpt_tsf_hdl(padapter, buflen, tmpBuf);
++		_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
++		break;
++	default:
++		/* RTW_INFO("[MCC] Other MCC status(%d)\n", pmccobjpriv->mcc_c2h_status); */
++		break;
++	}
++}
++
++void rtw_hal_mcc_update_parameter(PADAPTER padapter, u8 force_update)
++{	
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
++	u8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0};
++	u8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME;
++	u8 ap_num = DEV_AP_NUM(dvobj);	
++
++	if (ap_num == 0) {
++		u8 need_update = _FALSE;
++		u8 start_time_offset = 0, interval = 0, duration = 0;
++
++		need_update = rtw_hal_mcc_update_timing_parameters(padapter, force_update);
++
++		if (need_update == _FALSE)
++			return;
++		
++		start_time_offset = mccobjpriv->start_time;
++		interval = mccobjpriv->interval;
++		duration = mccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration;
++
++		SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, start_time_offset);
++		SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
++		SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
++		SET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE);
++		SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, duration);
++	} else {
++		PADAPTER order0_iface = NULL;
++		PADAPTER order1_iface = NULL;
++		u8 policy_idx = mccobjpriv->policy_index;
++		u8 duration = mcc_switch_channel_policy_table[policy_idx][MCC_DURATION_IDX];
++		u8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
++		u8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
++		u8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX];
++		u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX];
++		u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX];
++		u8 order0_duration = 0;
++		u8 i = 0;
++		enum _hw_port tsf_bsae_port = MAX_HW_PORT;
++		enum _hw_port tsf_sync_port = MAX_HW_PORT;
++
++		RTW_INFO("%s: policy_idx=%d\n", __func__, policy_idx);
++
++		order0_iface = mccobjpriv->iface[0];
++		order1_iface = mccobjpriv->iface[1];
++
++		/* GO/AP is order 0, GC/STA is order 1 */
++		order0_duration = order0_iface->mcc_adapterpriv.mcc_duration = interval - duration;
++		order0_iface->mcc_adapterpriv.mcc_duration = duration;
++
++		tsf_bsae_port = rtw_hal_get_port(order1_iface);
++		tsf_sync_port = rtw_hal_get_port(order0_iface);
++
++		/* update IE */
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			PADAPTER iface = NULL;
++			struct mcc_adapter_priv *mccadapriv = NULL;
++
++			iface = dvobj->padapters[i];
++			if (iface == NULL)
++				continue;
++		
++			mccadapriv = &iface->mcc_adapterpriv;
++			if (mccadapriv->role == MCC_ROLE_MAX)
++				continue;
++			
++			if (mccadapriv->role == MCC_ROLE_GO)
++				rtw_hal_mcc_update_go_p2p_ie(iface);
++		}
++
++		/* update H2C cmd */
++		/* FW set enable */
++		SET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, _TRUE);
++		/* TSF Sync offset */
++		SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset);
++		/* start time offset */
++		SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0));
++		/* interval */
++		SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
++		/* Early time to inform driver by C2H before switch channel */
++		SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
++		/* Port0 sync from Port1, not support multi-port */
++		SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, tsf_bsae_port);
++		SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, tsf_sync_port);
++		SET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE);
++		SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, order0_duration);
++	}
++
++	rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd);
++}
++
++/**
++ * rtw_hal_mcc_sw_status_check - check mcc swich channel status
++ * @padapter: primary adapter
++ */
++void rtw_hal_mcc_sw_status_check(PADAPTER padapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
++	struct pwrctrl_priv	*pwrpriv = dvobj_to_pwrctl(dvobj);
++	struct mcc_adapter_priv *mccadapriv = NULL;
++	_adapter *iface = NULL;
++	u8 cur_cnt = 0, prev_cnt = 0, diff_cnt = 0, check_ret = _FAIL, threshold = 0;
++	u8 policy_idx = pmccobjpriv->policy_index;
++	u8 noa_enable = _FALSE;
++	u8 i = 0;
++	_irqL irqL;
++	u8 ap_num = DEV_AP_NUM(dvobj);	
++
++/* #define MCC_RESTART 1 */
++
++	if (!MCC_EN(padapter))
++		return;
++
++	_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
++
++	if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
++
++		/* check noa enable or not */
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			iface = dvobj->padapters[i];
++			if (iface == NULL)
++				continue;
++
++			mccadapriv = &iface->mcc_adapterpriv;
++			if (mccadapriv->role == MCC_ROLE_MAX)
++				continue;
++			
++			if (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) {
++				noa_enable = _TRUE;
++				break;
++			}
++		}		
++
++		if (!noa_enable && ap_num == 0)
++			rtw_hal_mcc_update_parameter(padapter, _FALSE);
++
++		threshold = pmccobjpriv->mcc_stop_threshold;
++
++		if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
++			rtw_warn_on(1);
++			RTW_INFO("PS mode is not active under mcc, force exit ps mode\n");
++			LeaveAllPowerSaveModeDirect(padapter);
++		}
++
++		if (rtw_get_passing_time_ms(pmccobjpriv->mcc_launch_time) > 2000) {
++			_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
++
++			cur_cnt = pmccobjpriv->cur_mcc_success_cnt;
++			prev_cnt = pmccobjpriv->prev_mcc_success_cnt;
++			if (cur_cnt < prev_cnt)
++				diff_cnt = (cur_cnt + 255) - prev_cnt;
++			else
++				diff_cnt = cur_cnt - prev_cnt;
++
++			if (diff_cnt < threshold) {
++				pmccobjpriv->mcc_tolerance_time--;
++				RTW_INFO("%s: diff_cnt:%d, tolerance_time:%d\n",
++					__func__, diff_cnt, pmccobjpriv->mcc_tolerance_time);
++			} else
++				pmccobjpriv->mcc_tolerance_time = MCC_TOLERANCE_TIME;
++
++			pmccobjpriv->prev_mcc_success_cnt = pmccobjpriv->cur_mcc_success_cnt;
++
++			if (pmccobjpriv->mcc_tolerance_time != 0)
++				check_ret = _SUCCESS;
++
++			_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
++
++			if (check_ret != _SUCCESS) {
++				RTW_INFO("============ MCC swich channel check fail (%d)=============\n", diff_cnt);
++				/* restart MCC */
++				#ifdef MCC_RESTART
++					rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_STOP_DISCONNECT);
++					rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
++				#endif /* MCC_RESTART */
++			}
++		} else {
++			_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
++			pmccobjpriv->prev_mcc_success_cnt = pmccobjpriv->cur_mcc_success_cnt;
++			_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
++		}
++
++	}
++	_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
++}
++
++/**
++ * rtw_hal_mcc_change_scan_flag - change scan flag under mcc
++ *
++ * MCC mode under sitesurvey goto AP channel to tx bcn & data
++ * MCC mode under sitesurvey doesn't support TX data for station mode (FW not support)
++ *
++ * @padapter: the adapter to be change scan flag
++ * @ch: pointer to rerurn ch
++ * @bw: pointer to rerurn bw
++ * @offset: pointer to rerurn offset
++ */
++u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset)
++{
++	u8 need_ch_setting_union = _TRUE, i = 0, flags = 0, back_op = _FALSE;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_adapter_priv *mccadapriv = NULL;
++	struct mlme_ext_priv *mlmeext = NULL;
++	_adapter *iface = NULL;
++
++	if (!MCC_EN(padapter))
++		goto exit;
++
++	if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC))
++		goto exit;
++
++	/* disable PS_ANNC & TX_RESUME for all interface */
++	/* ToDo: TX_RESUME by interface in SCAN_BACKING_OP */
++	mlmeext = &padapter->mlmeextpriv;
++	
++	flags = mlmeext_scan_backop_flags(mlmeext);
++	if (mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_PS_ANNC))
++		flags &= ~SS_BACKOP_PS_ANNC;
++
++	if (mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME))
++		flags &= ~SS_BACKOP_TX_RESUME;
++
++	mlmeext_assign_scan_backop_flags(mlmeext, flags);
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (!iface)
++			continue;
++
++		mlmeext = &iface->mlmeextpriv;
++
++		if (MLME_IS_GO(iface) || MLME_IS_AP(iface))
++			back_op = _TRUE;
++		else if (MLME_IS_GC(iface) && (iface != padapter))
++			/* switch to another linked interface(GO) to receive beacon to avoid no beacon disconnect */
++			back_op = _TRUE;
++		else if (MLME_IS_STA(iface) && MLME_IS_ASOC(iface) && (iface != padapter))
++			/* switch to another linked interface(STA) to receive beacon to avoid no beacon disconnect  */
++			back_op = _TRUE;
++		else {
++			/* bypass non-linked/non-linking interface/scan interface */
++			continue;
++		}
++		
++		if (back_op) {
++			*ch = mlmeext->cur_channel;
++			*bw = mlmeext->cur_bwmode;
++			*offset = mlmeext->cur_ch_offset;
++			need_ch_setting_union = _FALSE;
++		}
++	}
++exit:
++	return need_ch_setting_union;
++}
++
++/**
++ * rtw_hal_mcc_calc_tx_bytes_from_kernel - calculte tx bytes from kernel to check concurrent tx or not
++ * @padapter: the adapter to be record tx bytes
++ * @len: data len
++ */
++inline void rtw_hal_mcc_calc_tx_bytes_from_kernel(PADAPTER padapter, u32 len)
++{
++	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
++
++	if (MCC_EN(padapter)) {
++		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
++			pmccadapriv->mcc_tx_bytes_from_kernel += len;
++			if (0)
++				RTW_INFO("%s(order:%d): mcc tx bytes from kernel:%lld\n"
++					, __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_from_kernel);
++		}
++	}
++}
++
++/**
++ * rtw_hal_mcc_calc_tx_bytes_to_port - calculte tx bytes to write port in order to flow crtl
++ * @padapter: the adapter to be record tx bytes
++ * @len: data len
++ */
++inline void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len)
++{
++	if (MCC_EN(padapter)) {
++		struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
++		struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
++
++		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
++			pmccadapriv->mcc_tx_bytes_to_port += len;
++			if (0)
++				RTW_INFO("%s(order:%d): mcc tx bytes to port:%d, mcc target tx bytes to port:%d\n"
++					, __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_to_port
++					, pmccadapriv->mcc_target_tx_bytes_to_port);
++		}
++	}
++}
++
++/**
++ * rtw_hal_mcc_stop_tx_bytes_to_port - stop write port to hw or not
++ * @padapter: the adapter to be stopped
++ */
++inline u8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter)
++{
++	if (MCC_EN(padapter)) {
++		struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
++		struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
++
++		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
++			if (pmccadapriv->mcc_tp_limit) {
++				if (pmccadapriv->mcc_tx_bytes_to_port >= pmccadapriv->mcc_target_tx_bytes_to_port) {
++					pmccadapriv->mcc_tx_stop = _TRUE;
++					rtw_netif_stop_queue(padapter->pnetdev);
++					return _TRUE;
++				}
++			}
++		}
++	}
++
++	return _FALSE;
++}
++
++static void rtw_hal_mcc_assign_scan_flag(PADAPTER padapter, u8 scan_done)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_adapter_priv *mccadapriv = NULL;
++	_adapter *iface = NULL;
++	struct mlme_ext_priv *pmlmeext = NULL;
++	u8 i = 0, flags;
++
++	if (!MCC_EN(padapter))
++		return;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (iface == NULL)
++			continue;
++
++		mccadapriv = &iface->mcc_adapterpriv;
++		if (mccadapriv->role == MCC_ROLE_MAX)
++			continue;
++
++		pmlmeext = &iface->mlmeextpriv;
++		if (is_client_associated_to_ap(iface)) {
++			flags = mlmeext_scan_backop_flags_sta(pmlmeext);
++			if (scan_done) {
++				if (mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) {
++					flags &= ~SS_BACKOP_EN;
++					mlmeext_assign_scan_backop_flags_sta(pmlmeext, flags);
++				}
++			} else {
++				if (!mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) {
++					flags |= SS_BACKOP_EN;
++					mlmeext_assign_scan_backop_flags_sta(pmlmeext, flags);
++				}
++			}
++
++		}
++	}
++}
++
++/**
++ * rtw_hal_set_mcc_setting_scan_start - setting mcc under scan start
++ * @padapter: the adapter to be setted
++ * @ch_setting_changed: softap channel setting to be changed or not
++ */
++u8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter)
++{
++	u8 ret = _FAIL;
++
++	if (MCC_EN(padapter)) {
++		struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
++
++		_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
++		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
++			if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
++				ret = rtw_hal_set_mcc_setting(padapter,  MCC_SETCMD_STATUS_STOP_SCAN_START);
++				rtw_hal_mcc_assign_scan_flag(padapter, 0);
++			}
++		}
++		_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
++	}
++
++	return ret;
++}
++
++/**
++ * rtw_hal_set_mcc_setting_scan_complete - setting mcc after scan commplete
++ * @padapter: the adapter to be setted
++ * @ch_setting_changed: softap channel setting to be changed or not
++ */
++u8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter)
++{
++	u8 ret = _FAIL;
++
++	if (MCC_EN(padapter)) {
++		struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
++
++		_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
++
++		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
++				rtw_hal_mcc_assign_scan_flag(padapter, 1);
++				ret = rtw_hal_set_mcc_setting(padapter,  MCC_SETCMD_STATUS_START_SCAN_DONE);	
++		}
++		_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
++	}
++
++	return ret;
++}
++
++
++/**
++ * rtw_hal_set_mcc_setting_start_bss_network - setting mcc under softap start
++ * @padapter: the adapter to be setted
++ * @chbw_grouped: channel bw offset can not be allowed or not
++ */
++u8 rtw_hal_set_mcc_setting_start_bss_network(PADAPTER padapter, u8 chbw_allow)
++{
++	u8 ret = _FAIL;
++
++	if (MCC_EN(padapter)) {
++		/* channel bw offset can not be allowed, start MCC */
++		if (chbw_allow == _FALSE) {
++				struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
++
++				rtw_hal_mcc_restore_iqk_val(padapter);
++				_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
++				ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
++				_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
++			}
++		}
++
++	return ret;
++}
++
++/**
++ * rtw_hal_set_mcc_setting_disconnect - setting mcc under mlme disconnect(stop softap/disconnect from AP)
++ * @padapter: the adapter to be setted
++ */
++u8 rtw_hal_set_mcc_setting_disconnect(PADAPTER padapter)
++{
++	u8 ret = _FAIL;
++
++	if (MCC_EN(padapter)) {
++		struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
++
++		_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
++		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
++			if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
++				ret = rtw_hal_set_mcc_setting(padapter,  MCC_SETCMD_STATUS_STOP_DISCONNECT);
++		}
++		_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
++	}
++
++	return ret;
++}
++
++/**
++ * rtw_hal_set_mcc_setting_join_done_chk_ch - setting mcc under join done
++ * @padapter: the adapter to be checked
++ */
++u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter)
++{
++	u8 ret = _FAIL;
++
++	if (MCC_EN(padapter)) {
++		struct mi_state mstate;
++
++		rtw_mi_status_no_self(padapter, &mstate);
++
++		if (MSTATE_STA_LD_NUM(&mstate) || MSTATE_STA_LG_NUM(&mstate) || MSTATE_AP_NUM(&mstate)) {
++			bool chbw_allow = _TRUE;
++			u8 u_ch, u_offset, u_bw;
++			struct mlme_ext_priv *cur_mlmeext = &padapter->mlmeextpriv;
++			struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++			if (rtw_mi_get_ch_setting_union_no_self(padapter, &u_ch, &u_bw, &u_offset) <= 0) {
++				dump_adapters_status(RTW_DBGDUMP , dvobj);
++				rtw_warn_on(1);
++			}
++
++			RTW_INFO(FUNC_ADPT_FMT" union no self: %u,%u,%u\n"
++				, FUNC_ADPT_ARG(padapter), u_ch, u_bw, u_offset);
++
++			/* chbw_allow? */
++			chbw_allow = rtw_is_chbw_grouped(cur_mlmeext->cur_channel
++				, cur_mlmeext->cur_bwmode, cur_mlmeext->cur_ch_offset
++					, u_ch, u_bw, u_offset);
++
++			RTW_INFO(FUNC_ADPT_FMT" chbw_allow:%d\n"
++				, FUNC_ADPT_ARG(padapter), chbw_allow);
++
++			/* if chbw_allow = false, start MCC setting */
++			if (chbw_allow == _FALSE) {
++				struct mcc_obj_priv *pmccobjpriv = &dvobj->mcc_objpriv;
++
++				rtw_hal_mcc_restore_iqk_val(padapter);
++				_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
++				ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
++				_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
++		}
++	}
++	}
++
++	return ret;
++}
++
++/**
++ * rtw_hal_set_mcc_setting_chk_start_clnt_join - check change channel under start clnt join
++ * @padapter: the adapter to be checked
++ * @ch: pointer to rerurn ch
++ * @bw: pointer to rerurn bw
++ * @offset: pointer to rerurn offset
++ * @chbw_allow: allow to use adapter's channel setting
++ */
++u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset, u8 chbw_allow)
++{
++	u8 ret = _FAIL;
++
++	/* if chbw_allow = false under en_mcc = TRUE, we do not change channel related setting  */
++	if (MCC_EN(padapter)) {
++		/* restore union channel related setting to current channel related setting */
++		if (chbw_allow == _FALSE) {
++			struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++
++			/* issue null data to other interface connected to AP */
++			rtw_hal_mcc_issue_null_data(padapter, chbw_allow, _TRUE);
++
++			*ch = pmlmeext->cur_channel;
++			*bw = pmlmeext->cur_bwmode;
++			*offset = pmlmeext->cur_ch_offset;
++
++			RTW_INFO(FUNC_ADPT_FMT" en_mcc:%d(%d,%d,%d,)\n"
++				, FUNC_ADPT_ARG(padapter), MCC_EN(padapter)
++				, *ch, *bw, *offset);
++			ret = _SUCCESS;
++		}
++	}
++
++	return ret;
++}
++
++static void rtw_hal_mcc_dump_noa_content(void *sel, PADAPTER padapter)
++{
++	struct mcc_adapter_priv *pmccadapriv = NULL;
++	u8 *pos = NULL;
++	pmccadapriv = &padapter->mcc_adapterpriv;
++	/* last position for NoA attribute */
++	pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len;
++
++
++	RTW_PRINT_SEL(sel, "\nStart to dump NoA Content\n");
++	RTW_PRINT_SEL(sel, "NoA Counts:%d\n", *(pos - 13));
++	RTW_PRINT_SEL(sel, "NoA Duration(TU):%d\n", (RTW_GET_LE32(pos - 12))/TU);
++	RTW_PRINT_SEL(sel, "NoA Interval(TU):%d\n", (RTW_GET_LE32(pos - 8))/TU);
++	RTW_PRINT_SEL(sel, "NoA Start time(microseconds):0x%02x\n", RTW_GET_LE32(pos - 4));
++	RTW_PRINT_SEL(sel, "End to dump NoA Content\n");
++}
++
++static void mcc_dump_dbg_reg(void *sel, _adapter *adapter)
++{
++	struct mcc_obj_priv *mccobjpriv = adapter_to_mccobjpriv(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	u8 i,j;
++	_irqL irqL;
++
++	_enter_critical_bh(&mccobjpriv->mcc_lock, &irqL);
++	RTW_PRINT_SEL(sel, "current order=%d\n", mccobjpriv->current_order);
++	_exit_critical_bh(&mccobjpriv->mcc_lock, &irqL);
++
++	_enter_critical_mutex(&mccobjpriv->mcc_dbg_reg_mutex, NULL);
++	for (i = 0; i < ARRAY_SIZE(mccobjpriv->dbg_reg); i++)
++			RTW_PRINT_SEL(sel, "REG_0x%X:0x%08x\n", mccobjpriv->dbg_reg[i], mccobjpriv->dbg_reg_val[i]);
++
++	for (i = 0; i < ARRAY_SIZE(mccobjpriv->dbg_rf_reg); i++) {
++		for (j = 0; j < hal_spec->rf_reg_path_num; j++)
++			RTW_PRINT_SEL(sel, "RF_PATH_%d_REG_0x%X:0x%08x\n",
++				j, mccobjpriv->dbg_rf_reg[i], mccobjpriv->dbg_rf_reg_val[i][j]);
++	}
++	_exit_critical_mutex(&mccobjpriv->mcc_dbg_reg_mutex, NULL);
++}
++
++
++void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj)
++{
++	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
++	struct mcc_adapter_priv *mccadapriv = NULL;
++	_adapter *iface = NULL, *pri_adapter = NULL;
++	struct registry_priv *regpriv = NULL;
++	HAL_DATA_TYPE *hal = NULL;
++	u8 i = 0, j = 0;
++	u64 tsf[MAX_MCC_NUM] = {0};
++
++	/* regpriv is common for all adapter */
++	pri_adapter = dvobj_get_primary_adapter(dvobj);
++	hal = GET_HAL_DATA(pri_adapter);
++
++	RTW_PRINT_SEL(sel, "**********************************************\n");
++	RTW_PRINT_SEL(sel, "en_mcc:%d\n", MCC_EN(pri_adapter));
++	RTW_PRINT_SEL(sel, "primary adapter("ADPT_FMT") duration:%d%c\n",
++		ADPT_ARG(dvobj_get_primary_adapter(dvobj)), mccobjpriv->duration, 37);
++	RTW_PRINT_SEL(sel, "runtime duration:%s\n", mccobjpriv->enable_runtime_duration ? "enable":"disable");
++	RTW_PRINT_SEL(sel, "phydm offload:%s\n", mccobjpriv->mcc_phydm_offload ? "enable":"disable");
++
++	if (rtw_hal_check_mcc_status(pri_adapter, MCC_STATUS_DOING_MCC)) {
++		rtw_hal_mcc_rqt_tsf(pri_adapter, tsf);
++
++		for (i = 0; i < MAX_MCC_NUM; i++) {
++			iface = mccobjpriv->iface[i];
++			if (!iface)
++				continue;
++
++			regpriv = &iface->registrypriv;
++			mccadapriv = &iface->mcc_adapterpriv;
++
++			if (mccadapriv) {
++				u8 p2p_ps_mode = iface->wdinfo.p2p_ps_mode;
++
++				RTW_PRINT_SEL(sel, "adapter mcc info:\n");
++				RTW_PRINT_SEL(sel, "ifname:%s\n", ADPT_ARG(iface));
++				RTW_PRINT_SEL(sel, "order:%d\n", mccadapriv->order);
++				RTW_PRINT_SEL(sel, "duration:%d\n", mccadapriv->mcc_duration);
++				RTW_PRINT_SEL(sel, "target tx bytes:%d\n", mccadapriv->mcc_target_tx_bytes_to_port);
++				RTW_PRINT_SEL(sel, "current TP:%d\n", mccadapriv->mcc_tp);
++				RTW_PRINT_SEL(sel, "mgmt queue macid:%d\n", mccadapriv->mgmt_queue_macid);
++				RTW_PRINT_SEL(sel, "macid bitmap:0x%02x\n", mccadapriv->mcc_macid_bitmap);
++				RTW_PRINT_SEL(sel, "P2P NoA:%s\n\n", p2p_ps_mode == P2P_PS_NOA ? "enable":"disable");
++				RTW_PRINT_SEL(sel, "registry data:\n");
++				RTW_PRINT_SEL(sel, "ap target tx TP(BW:20M):%d Mbps\n", regpriv->rtw_mcc_ap_bw20_target_tx_tp);
++				RTW_PRINT_SEL(sel, "ap target tx TP(BW:40M):%d Mbps\n", regpriv->rtw_mcc_ap_bw40_target_tx_tp);
++				RTW_PRINT_SEL(sel, "ap target tx TP(BW:80M):%d Mbps\n", regpriv->rtw_mcc_ap_bw80_target_tx_tp);
++				RTW_PRINT_SEL(sel, "sta target tx TP(BW:20M):%d Mbps\n", regpriv->rtw_mcc_sta_bw20_target_tx_tp);
++				RTW_PRINT_SEL(sel, "sta target tx TP(BW:40M ):%d Mbps\n", regpriv->rtw_mcc_sta_bw40_target_tx_tp);
++				RTW_PRINT_SEL(sel, "sta target tx TP(BW:80M):%d Mbps\n", regpriv->rtw_mcc_sta_bw80_target_tx_tp);
++				RTW_PRINT_SEL(sel, "single tx criteria:%d Mbps\n", regpriv->rtw_mcc_single_tx_cri);
++				RTW_PRINT_SEL(sel, "HW TSF=0x%llx\n", tsf[mccadapriv->order]);
++				if (MLME_IS_GO(iface))
++					rtw_hal_mcc_dump_noa_content(sel, iface);
++				RTW_PRINT_SEL(sel, "**********************************************\n");
++			}
++		}
++
++		mcc_dump_dbg_reg(sel, pri_adapter);
++	}
++
++	#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++	RTW_PRINT_SEL(sel, "@@@@@@@@@@@@@@@@@@@@\n");
++	rtw_hal_mcc_cfg_phydm(pri_adapter, MCC_CFG_PHYDM_DUMP, sel);
++	RTW_PRINT_SEL(sel, "@@@@@@@@@@@@@@@@@@@@\n");
++	#endif
++	
++	RTW_PRINT_SEL(sel, "------------------------------------------\n");
++	RTW_PRINT_SEL(sel, "policy index:%d\n", mccobjpriv->policy_index);	
++	RTW_PRINT_SEL(sel, "------------------------------------------\n");
++	RTW_PRINT_SEL(sel, "define data:\n");
++	RTW_PRINT_SEL(sel, "ap target tx TP(BW:20M):%d Mbps\n", MCC_AP_BW20_TARGET_TX_TP);
++	RTW_PRINT_SEL(sel, "ap target tx TP(BW:40M):%d Mbps\n", MCC_AP_BW40_TARGET_TX_TP);
++	RTW_PRINT_SEL(sel, "ap target tx TP(BW:80M):%d Mbps\n", MCC_AP_BW80_TARGET_TX_TP);
++	RTW_PRINT_SEL(sel, "sta target tx TP(BW:20M):%d Mbps\n", MCC_STA_BW20_TARGET_TX_TP);
++	RTW_PRINT_SEL(sel, "sta target tx TP(BW:40M):%d Mbps\n", MCC_STA_BW40_TARGET_TX_TP);
++	RTW_PRINT_SEL(sel, "sta target tx TP(BW:80M):%d Mbps\n", MCC_STA_BW80_TARGET_TX_TP);
++	RTW_PRINT_SEL(sel, "single tx criteria:%d Mbps\n", MCC_SINGLE_TX_CRITERIA);
++	RTW_PRINT_SEL(sel, "------------------------------------------\n");
++}
++
++inline void update_mcc_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
++{
++	if (MCC_EN(padapter)) {
++		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
++			/* use QSLT_MGNT to check mgnt queue or bcn queue */
++			if (pattrib->qsel == QSLT_MGNT) {
++				pattrib->mac_id = padapter->mcc_adapterpriv.mgmt_queue_macid;
++				pattrib->qsel = QSLT_VO;
++			}
++		}
++	}
++}
++
++inline u8 rtw_hal_mcc_link_status_chk(_adapter *padapter, const char *msg)
++{
++	u8 ret = _TRUE, i = 0;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	_adapter *iface;
++	struct mlme_ext_priv *mlmeext;
++
++	if (MCC_EN(padapter)) {
++		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
++			for (i = 0; i < dvobj->iface_nums; i++) {
++				iface = dvobj->padapters[i];
++				mlmeext = &iface->mlmeextpriv;
++				if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE) {
++					#ifdef DBG_EXPIRATION_CHK
++						RTW_INFO(FUNC_ADPT_FMT" don't enter %s under scan for MCC mode\n", FUNC_ADPT_ARG(padapter), msg);
++					#endif
++					ret = _FALSE;
++					goto exit;
++				}
++			}
++		}
++	}
++
++exit:
++	return ret;
++}
++
++void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	_adapter *iface = NULL;
++	systime start = rtw_get_current_time();
++	u8 i = 0;
++
++	if (!MCC_EN(padapter))
++		return;
++
++	if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
++		return;
++
++	if (chbw_allow == _TRUE)
++		return;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		/* issue null data to inform ap station will leave */
++		if (is_client_associated_to_ap(iface)) {
++			struct mlme_ext_priv *mlmeext = &iface->mlmeextpriv;
++			struct mlme_ext_info *mlmeextinfo = &mlmeext->mlmext_info;
++			u8 ch = mlmeext->cur_channel;
++			u8 bw = mlmeext->cur_bwmode;
++			u8 offset = mlmeext->cur_ch_offset;
++			struct sta_info *sta = rtw_get_stainfo(&iface->stapriv, get_my_bssid(&(mlmeextinfo->network)));
++
++			if (!sta)
++				continue;
++
++			set_channel_bwmode(iface, ch, offset, bw);
++
++			if (ps_mode)
++				rtw_hal_macid_sleep(iface, sta->cmn.mac_id);
++			else
++				rtw_hal_macid_wakeup(iface, sta->cmn.mac_id);
++
++			issue_nulldata(iface, NULL, ps_mode, 3, 50);
++		}
++	}
++	RTW_INFO("%s(%d ms)\n", __func__, rtw_get_passing_time_ms(start));
++}
++
++u8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len)
++{
++	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
++
++	if (!MCC_EN(padapter))
++		return pframe;
++	
++	if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
++		return pframe;
++
++	if (pmccadapriv->p2p_go_noa_ie_len == 0)
++		return pframe;
++
++	_rtw_memcpy(pframe, pmccadapriv->p2p_go_noa_ie, pmccadapriv->p2p_go_noa_ie_len);
++	*len = *len + pmccadapriv->p2p_go_noa_ie_len;
++
++	return pframe + pmccadapriv->p2p_go_noa_ie_len;
++}
++
++void rtw_hal_dump_mcc_policy_table(void *sel)
++{
++	u8 idx = 0;
++	RTW_PRINT_SEL(sel, "duration\t,tsf sync offset\t,start time offset\t,interval\t,guard offset0\t,guard offset1\n");
++
++	for (idx = 0; idx < mcc_max_policy_num; idx ++) {
++		RTW_PRINT_SEL(sel, "%d\t\t,%d\t\t\t,%d\t\t\t,%d\t\t,%d\t\t,%d\n"
++			, mcc_switch_channel_policy_table[idx][MCC_DURATION_IDX]
++			, mcc_switch_channel_policy_table[idx][MCC_TSF_SYNC_OFFSET_IDX]
++			, mcc_switch_channel_policy_table[idx][MCC_START_TIME_OFFSET_IDX]
++			, mcc_switch_channel_policy_table[idx][MCC_INTERVAL_IDX]
++			, mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET0_IDX]
++			, mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET1_IDX]);
++	}
++}
++
++void rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add)
++{
++	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
++
++	if (!MCC_EN(padapter))
++		return;
++
++	if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
++		return;
++
++	if (pmccadapriv->role == MCC_ROLE_GC || pmccadapriv->role == MCC_ROLE_STA)
++		return;
++
++	if (mac_id < 0) {
++		RTW_WARN("%s: mac_id < 0(%d)\n", __func__, mac_id);
++		return;
++	}
++
++	RTW_INFO(ADPT_FMT" %s macid=%d, ori mcc_macid_bitmap=0x%08x\n"
++		, ADPT_ARG(padapter), add ? "add" : "clear"
++		, mac_id, pmccadapriv->mcc_macid_bitmap);
++
++	if (add) {
++		#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++		rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_ADD_CLIENT, &mac_id);
++		#endif
++		pmccadapriv->mcc_macid_bitmap |= BIT(mac_id);
++	} else {
++		#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++		rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_REMOVE_CLIENT, &mac_id);
++		#endif
++		pmccadapriv->mcc_macid_bitmap &= ~(BIT(mac_id));
++	}
++	rtw_hal_set_mcc_macid_cmd(padapter);
++}
++
++void rtw_hal_mcc_process_noa(PADAPTER padapter)
++{
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
++
++	if (!MCC_EN(padapter))
++		return;
++
++	if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
++		return;
++
++	if (!MLME_IS_GC(padapter))
++		return;
++
++	switch(pwdinfo->p2p_ps_mode) {
++	case P2P_PS_NONE:
++		RTW_INFO("[MCC] Disable NoA under MCC\n");
++		rtw_hal_mcc_update_parameter(padapter, _TRUE);
++		break;
++	case P2P_PS_NOA:
++		RTW_INFO("[MCC] Enable NoA under MCC\n");
++		break;
++	default:
++		break;
++
++	}
++}
++
++void rtw_hal_mcc_parameter_init(PADAPTER padapter)
++{
++	if (!padapter->registrypriv.en_mcc)
++		return;
++
++	if (is_primary_adapter(padapter)) {
++		SET_MCC_EN_FLAG(padapter, padapter->registrypriv.en_mcc);
++		SET_MCC_DURATION(padapter, padapter->registrypriv.rtw_mcc_duration);
++		SET_MCC_RUNTIME_DURATION(padapter, padapter->registrypriv.rtw_mcc_enable_runtime_duration);
++		SET_MCC_PHYDM_OFFLOAD(padapter, padapter->registrypriv.rtw_mcc_phydm_offload);
++	}
++}
++
++
++static u8 set_mcc_duration_hdl(PADAPTER adapter, const u8 *val)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
++	_adapter *iface = NULL;
++	u8 duration = 50;
++	u8 ret = _SUCCESS, noa_enable = _FALSE, i = 0;
++	enum mcc_duration_setting type;
++
++	if (!mccobjpriv->enable_runtime_duration)
++		goto exit;
++
++#ifdef CONFIG_P2P_PS
++	/* check noa enable or not */
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) {
++			noa_enable = _TRUE;
++			break;
++		}
++	}
++#endif /* CONFIG_P2P_PS */
++
++	type = val[0];
++	duration = val[1];
++
++	if (type == MCC_DURATION_MAPPING) {
++		switch (duration) {
++			/* 0 = fair scheduling */
++			case 0:
++				mccobjpriv->duration= 40;
++				mccobjpriv->policy_index = 2;
++				mccobjpriv->mchan_sched_mode = MCC_FAIR_SCHEDULE;
++				break;
++			/* 1 = favor STA */
++			case 1:
++				mccobjpriv->duration= 70;
++				mccobjpriv->policy_index = 1;
++				mccobjpriv->mchan_sched_mode = MCC_FAVOR_STA;
++				break;
++			/* 2 = favor P2P*/
++			case 2:
++			default:
++				mccobjpriv->duration= 30;
++				mccobjpriv->policy_index = 0;
++				mccobjpriv->mchan_sched_mode = MCC_FAVOR_P2P;
++				break;
++		}
++	} else {
++		mccobjpriv->duration = duration;
++		rtw_hal_mcc_update_policy_table(adapter);
++	}
++
++	/* only update sw parameter under MCC 
++	    it will be force update during */
++	if (noa_enable)
++		goto exit;
++
++	if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
++		rtw_hal_mcc_update_parameter(adapter, _TRUE);
++exit:
++	return ret;
++}
++
++u8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val)
++{
++	struct cmd_obj *cmdobj;
++	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++	u8 *buf = NULL;
++	u8 sz = 2;
++	u8 res = _SUCCESS;
++
++	
++	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++	if (cmdobj == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++	if (pdrvextra_cmd_parm == NULL) {
++		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
++		res = _FAIL;
++		goto exit;
++	}
++
++	buf = rtw_zmalloc(sizeof(u8) * sz);
++	if (buf == NULL) {
++		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
++		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
++		res = _FAIL;
++		goto exit;
++	}
++
++	pdrvextra_cmd_parm->ec_id = MCC_CMD_WK_CID;
++	pdrvextra_cmd_parm->type = MCC_SET_DURATION_WK_CID;
++	pdrvextra_cmd_parm->size = sz;
++	pdrvextra_cmd_parm->pbuf = buf;
++
++	_rtw_memcpy(buf, &type, 1);
++	_rtw_memcpy(buf + 1, &val, 1);
++
++	init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++	res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
++
++exit:
++	return res;
++}
++
++#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++static u8 mcc_phydm_offload_enable_hdl(_adapter *adapter, const u8 *val)
++{
++	struct mcc_obj_priv *mccobjpriv =  adapter_to_mccobjpriv(adapter);
++	u8 ret = _SUCCESS;
++	u8 enable = *val;
++
++	/*only modify driver parameter during non-mcc status */
++	if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
++		mccobjpriv->mcc_phydm_offload = enable;
++	} else {
++		/*modify both driver & phydm parameter during mcc status */
++		mccobjpriv->mcc_phydm_offload = enable;
++		rtw_hal_mcc_cfg_phydm(adapter, MCC_CFG_PHYDM_OFFLOAD, &mccobjpriv->mcc_phydm_offload);
++	}
++
++	RTW_INFO("[MCC] phydm offload enable hdl(%d)\n", mccobjpriv->mcc_phydm_offload);
++
++	return ret;
++}
++
++u8 rtw_set_mcc_phydm_offload_enable_cmd(_adapter *adapter, u8 enable, u8 enqueue)
++{
++	u8 res = _SUCCESS;
++
++	if (enqueue) {
++		struct cmd_obj *cmdobj;
++		struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++		struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++		u8 *mcc_phydm_offload_enable = NULL;
++
++		
++		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++		if (cmdobj == NULL) {
++			res = _FAIL;
++			goto exit;
++		}
++
++		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++		if (pdrvextra_cmd_parm == NULL) {
++			rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
++			res = _FAIL;
++			goto exit;
++		}
++
++		mcc_phydm_offload_enable = rtw_zmalloc(sizeof(u8));
++		if (mcc_phydm_offload_enable == NULL) {
++			rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
++			rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
++			res = _FAIL;
++			goto exit;
++		}
++
++		pdrvextra_cmd_parm->ec_id = MCC_CMD_WK_CID;
++		pdrvextra_cmd_parm->type = MCC_SET_PHYDM_OFFLOAD_WK_CID;
++		pdrvextra_cmd_parm->size = 1;
++		pdrvextra_cmd_parm->pbuf = mcc_phydm_offload_enable;
++
++		_rtw_memcpy(mcc_phydm_offload_enable, &enable, 1);
++		init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
++		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
++	} else {
++		mcc_phydm_offload_enable_hdl(adapter, &enable);
++	}
++
++exit:
++	return res;
++}
++#endif
++
++u8 rtw_mcc_cmd_hdl(_adapter *adapter, u8 type, const u8 *val)
++{
++	struct mcc_obj_priv *mccobjpriv =  adapter_to_mccobjpriv(adapter);
++	u8 ret = _SUCCESS;
++
++	switch (type) {
++	case MCC_SET_DURATION_WK_CID:
++		set_mcc_duration_hdl(adapter, val);
++		break;
++	case MCC_GET_DBG_REG_WK_CID:
++		mcc_get_reg_hdl(adapter, val);
++		break;
++	#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++	case MCC_SET_PHYDM_OFFLOAD_WK_CID:
++		mcc_phydm_offload_enable_hdl(adapter, val);
++		break;
++	#endif
++	default:
++		RTW_ERR("[MCC] rtw_mcc_cmd_hdl fail(%d)\n", type);
++		break;
++	}
++
++
++
++	return ret;
++}
++
++#endif /* CONFIG_MCC_MODE */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_mp.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_mp.c
+new file mode 100644
+index 000000000..718bd7d8b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_mp.c
+@@ -0,0 +1,2634 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _HAL_MP_C_
++
++#include <drv_types.h>
++
++#ifdef CONFIG_MP_INCLUDED
++
++#ifdef RTW_HALMAC
++	#include <hal_data.h>		/* struct HAL_DATA_TYPE, RF register definition and etc. */
++#else /* !RTW_HALMAC */
++	#ifdef CONFIG_RTL8188E
++		#include <rtl8188e_hal.h>
++	#endif
++	#ifdef CONFIG_RTL8723B
++		#include <rtl8723b_hal.h>
++	#endif
++	#ifdef CONFIG_RTL8192E
++		#include <rtl8192e_hal.h>
++	#endif
++	#ifdef CONFIG_RTL8814A
++		#include <rtl8814a_hal.h>
++	#endif
++	#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
++		#include <rtl8812a_hal.h>
++	#endif
++	#ifdef CONFIG_RTL8703B
++		#include <rtl8703b_hal.h>
++	#endif
++	#ifdef CONFIG_RTL8723D
++		#include <rtl8723d_hal.h>
++	#endif
++	#ifdef CONFIG_RTL8710B
++		#include <rtl8710b_hal.h>
++	#endif
++	#ifdef CONFIG_RTL8188F
++		#include <rtl8188f_hal.h>
++	#endif
++	#ifdef CONFIG_RTL8188GTV
++		#include <rtl8188gtv_hal.h>
++	#endif
++	#ifdef CONFIG_RTL8192F
++		#include <rtl8192f_hal.h>
++	#endif
++#endif /* !RTW_HALMAC */
++
++
++u8 MgntQuery_NssTxRate(u16 Rate)
++{
++	u8	NssNum = RF_TX_NUM_NONIMPLEMENT;
++
++	if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||
++	    (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))
++		NssNum = RF_2TX;
++	else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||
++		 (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))
++		NssNum = RF_3TX;
++	else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||
++		 (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))
++		NssNum = RF_4TX;
++	else
++		NssNum = RF_1TX;
++
++	return NssNum;
++}
++
++void hal_mpt_SwitchRfSetting(PADAPTER	pAdapter)
++{
++	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
++	u8				ChannelToSw = pMptCtx->MptChannelToSw;
++	u32				ulRateIdx = pMptCtx->mpt_rate_index;
++	u32				ulbandwidth = pMptCtx->MptBandWidth;
++
++	/* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
++	if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
++	    (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
++		pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
++		pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
++
++		if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
++			phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB);
++			phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB);
++		} else {
++			phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
++			phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
++		}
++	} else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
++		if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
++			phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
++			phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
++		} else {
++			phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
++			phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
++		}
++	} else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
++		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
++		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
++	}
++}
++
++s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
++
++
++	if (!netif_running(padapter->pnetdev)) {
++		return _FAIL;
++	}
++
++	if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
++		return _FAIL;
++	}
++	if (enable)
++		pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
++	else
++		pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
++
++	return _SUCCESS;
++}
++
++void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
++
++
++	*enable = pDM_Odm->rf_calibrate_info.txpowertrack_control;
++}
++
++
++void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
++{
++	u32		TempVal = 0, TempVal2 = 0, TempVal3 = 0;
++	u32		CurrCCKSwingVal = 0, CCKSwingIndex = 12;
++	u8		i;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++	PMPT_CONTEXT		pMptCtx = &(Adapter->mppriv.mpt_ctx);
++	u8				u1Channel = pHalData->current_channel;
++	u32				ulRateIdx = pMptCtx->mpt_rate_index;
++	u8				DataRate = 0xFF;
++
++	/* Do not modify CCK TX filter parameters for 8822B*/
++	if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) ||
++		IS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8192F(Adapter) || IS_HARDWARE_TYPE_8822C(Adapter))
++		return;
++
++	DataRate = mpt_to_mgnt_rate(ulRateIdx);
++
++	if (u1Channel == 14 && IS_CCK_RATE(DataRate))
++		pHalData->bCCKinCH14 = TRUE;
++	else
++		pHalData->bCCKinCH14 = FALSE;
++
++	if (IS_HARDWARE_TYPE_8703B(Adapter)) {
++		if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
++			/* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
++			phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
++			phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
++
++		} else {
++			/* Normal setting for 8703B, just recover to the default setting. */
++			/* This hardcore values reference from the parameter which BB team gave. */
++			for (i = 0 ; i < 2 ; ++i)
++				phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
++
++		}
++	} else if (IS_HARDWARE_TYPE_8723D(Adapter)) {
++		/* 2.4G CCK TX DFIR */
++		/* 2016.01.20 Suggest from RS BB mingzhi*/
++		if ((u1Channel == 14)) {
++			phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
++			phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
++			phy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
++		} else {
++			for (i = 0 ; i < 3 ; ++i) {
++				phy_set_bb_reg(Adapter,
++					     pHalData->RegForRecover[i].offset,
++					     bMaskDWord,
++					     pHalData->RegForRecover[i].value);
++			}
++		}
++	} else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
++		/* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
++		CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
++		CCKSwingIndex = 20; /* default index */
++
++		if (!pHalData->bCCKinCH14) {
++			/* Readback the current bb cck swing value and compare with the table to */
++			/* get the current swing index */
++			for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
++				if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) &&
++				    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) {
++					CCKSwingIndex = i;
++					break;
++				}
++			}
++			write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]);
++			write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]);
++			write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]);
++			write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]);
++			write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]);
++			write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]);
++			write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]);
++			write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]);
++			write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]);
++			write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]);
++			write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]);
++			write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]);
++			write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]);
++			write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]);
++			write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]);
++			write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]);
++			RTW_INFO("%s , cck_swing_table_ch1_ch13_88f[%d]\n", __func__, CCKSwingIndex);
++		}  else {
++			for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
++				if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) &&
++				    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) {
++					CCKSwingIndex = i;
++					break;
++				}
++			}
++			write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]);
++			write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]);
++			write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]);
++			write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]);
++			write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]);
++			write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]);
++			write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]);
++			write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]);
++			write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]);
++			write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]);
++			write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]);
++			write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]);
++			write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]);
++			write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]);
++			write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]);
++			write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]);
++			RTW_INFO("%s , cck_swing_table_ch14_88f[%d]\n", __func__, CCKSwingIndex);
++		}
++	} else {
++
++		/* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
++		CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
++
++		if (!pHalData->bCCKinCH14) {
++			/* Readback the current bb cck swing value and compare with the table to */
++			/* get the current swing index */
++			for (i = 0; i < CCK_TABLE_SIZE; i++) {
++				if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13[i][0]) &&
++				    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13[i][1])) {
++					CCKSwingIndex = i;
++					break;
++				}
++			}
++
++			/*Write 0xa22 0xa23*/
++			TempVal = cck_swing_table_ch1_ch13[CCKSwingIndex][0] +
++				(cck_swing_table_ch1_ch13[CCKSwingIndex][1] << 8);
++
++
++			/*Write 0xa24 ~ 0xa27*/
++			TempVal2 = 0;
++			TempVal2 = cck_swing_table_ch1_ch13[CCKSwingIndex][2] +
++				(cck_swing_table_ch1_ch13[CCKSwingIndex][3] << 8) +
++				(cck_swing_table_ch1_ch13[CCKSwingIndex][4] << 16) +
++				(cck_swing_table_ch1_ch13[CCKSwingIndex][5] << 24);
++
++			/*Write 0xa28  0xa29*/
++			TempVal3 = 0;
++			TempVal3 = cck_swing_table_ch1_ch13[CCKSwingIndex][6] +
++				(cck_swing_table_ch1_ch13[CCKSwingIndex][7] << 8);
++		}  else {
++			for (i = 0; i < CCK_TABLE_SIZE; i++) {
++				if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14[i][0]) &&
++				    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14[i][1])) {
++					CCKSwingIndex = i;
++					break;
++				}
++			}
++
++			/*Write 0xa22 0xa23*/
++			TempVal = cck_swing_table_ch14[CCKSwingIndex][0] +
++				  (cck_swing_table_ch14[CCKSwingIndex][1] << 8);
++
++			/*Write 0xa24 ~ 0xa27*/
++			TempVal2 = 0;
++			TempVal2 = cck_swing_table_ch14[CCKSwingIndex][2] +
++				   (cck_swing_table_ch14[CCKSwingIndex][3] << 8) +
++				(cck_swing_table_ch14[CCKSwingIndex][4] << 16) +
++				   (cck_swing_table_ch14[CCKSwingIndex][5] << 24);
++
++			/*Write 0xa28  0xa29*/
++			TempVal3 = 0;
++			TempVal3 = cck_swing_table_ch14[CCKSwingIndex][6] +
++				   (cck_swing_table_ch14[CCKSwingIndex][7] << 8);
++		}
++
++		write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
++		write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
++		write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
++	}
++
++}
++
++void hal_mpt_SetChannel(PADAPTER pAdapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++	struct mp_priv	*pmp = &pAdapter->mppriv;
++	u8		channel = pmp->channel;
++	u8		bandwidth = pmp->bandwidth;
++
++	hal_mpt_SwitchRfSetting(pAdapter);
++
++	pHalData->bSwChnl = _TRUE;
++	pHalData->bSetChnlBW = _TRUE;
++
++	if (bandwidth == 2) {
++		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
++	} else if (bandwidth == 1) {
++		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
++	} else
++		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
++
++	hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
++	rtw_btcoex_wifionly_scan_notify(pAdapter);
++
++}
++
++/*
++ * Notice
++ *	Switch bandwitdth may change center frequency(channel)
++ */
++void hal_mpt_SetBandwidth(PADAPTER pAdapter)
++{
++	struct mp_priv *pmp = &pAdapter->mppriv;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++
++	u8		channel = pmp->channel;
++	u8		bandwidth = pmp->bandwidth;
++
++	pHalData->bSwChnl = _TRUE;
++	pHalData->bSetChnlBW = _TRUE;
++
++	if (bandwidth == 2) {
++		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
++	} else if (bandwidth == 1) {
++		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
++	} else
++		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
++
++	hal_mpt_SwitchRfSetting(pAdapter);
++	rtw_btcoex_wifionly_scan_notify(pAdapter);
++
++}
++
++void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
++{
++	switch (Rate) {
++	case MPT_CCK: {
++		u32	TxAGC = 0, pwr = 0;
++
++		pwr = pTxPower[RF_PATH_A];
++		if (pwr < 0x3f) {
++			TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
++			phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[RF_PATH_A]);
++			phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
++		}
++		pwr = pTxPower[RF_PATH_B];
++		if (pwr < 0x3f) {
++			TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
++			phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[RF_PATH_B]);
++			phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
++		}
++	}
++	break;
++
++	case MPT_OFDM_AND_HT: {
++		u32	TxAGC = 0;
++		u8	pwr = 0;
++
++		pwr = pTxPower[0];
++		if (pwr < 0x3f) {
++			TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
++			RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
++			phy_set_bb_reg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
++			phy_set_bb_reg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
++			phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
++			phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
++			phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
++			phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
++		}
++		TxAGC = 0;
++		pwr = pTxPower[1];
++		if (pwr < 0x3f) {
++			TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
++			RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
++			phy_set_bb_reg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
++			phy_set_bb_reg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
++			phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
++			phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
++			phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
++			phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
++		}
++	}
++	break;
++
++	default:
++		break;
++	}
++	RTW_INFO("<===mpt_SetTxPower_Old()\n");
++}
++
++void
++mpt_SetTxPower(
++	PADAPTER		pAdapter,
++	MPT_TXPWR_DEF	Rate,
++	u8 *pTxPower
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++
++	u8 path = 0 , i = 0, MaxRate = MGN_6M;
++	u8 StartPath = RF_PATH_A, EndPath = RF_PATH_B;
++
++	if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8814B(pAdapter))
++		EndPath = RF_PATH_D;
++	else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)
++		|| IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
++		EndPath = RF_PATH_A;
++
++	switch (Rate) {
++	case MPT_CCK: {
++		u8 rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
++
++		for (path = StartPath; path <= EndPath; path++)
++			for (i = 0; i < sizeof(rate); ++i)
++				PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
++	}
++	break;
++	case MPT_OFDM: {
++		u8 rate[] = {
++			MGN_6M, MGN_9M, MGN_12M, MGN_18M,
++			MGN_24M, MGN_36M, MGN_48M, MGN_54M,
++		};
++
++		for (path = StartPath; path <= EndPath; path++)
++			for (i = 0; i < sizeof(rate); ++i)
++				PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
++	}
++	break;
++	case MPT_HT: {
++		u8 rate[] = {
++			MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
++			MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
++			MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
++			MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,
++			MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,
++			MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,
++			MGN_MCS30, MGN_MCS31,
++		};
++		if (pHalData->rf_type == RF_4T4R)
++			MaxRate = MGN_MCS31;
++		else if (pHalData->rf_type == RF_3T3R)
++			MaxRate = MGN_MCS23;
++		else if (pHalData->rf_type == RF_2T2R)
++			MaxRate = MGN_MCS15;
++		else
++			MaxRate = MGN_MCS7;
++		for (path = StartPath; path <= EndPath; path++) {
++			for (i = 0; i < sizeof(rate); ++i) {
++				if (rate[i] > MaxRate)
++					break;
++				PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
++			}
++		}
++	}
++	break;
++	case MPT_VHT: {
++		u8 rate[] = {
++			MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
++			MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
++			MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
++			MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,
++			MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
++			MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,
++			MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
++			MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,
++		};
++		if (pHalData->rf_type == RF_4T4R)
++			MaxRate = MGN_VHT4SS_MCS9;
++		else if (pHalData->rf_type == RF_3T3R)
++			MaxRate = MGN_VHT3SS_MCS9;
++		else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
++			MaxRate = MGN_VHT2SS_MCS9;
++		else
++			MaxRate = MGN_VHT1SS_MCS9;
++
++		for (path = StartPath; path <= EndPath; path++) {
++			for (i = 0; i < sizeof(rate); ++i) {
++				if (rate[i] > MaxRate)
++					break;
++				PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
++			}
++		}
++	}
++	break;
++	default:
++		RTW_INFO("<===mpt_SetTxPower: Illegal channel!!\n");
++		break;
++	}
++}
++
++void hal_mpt_SetTxPower(PADAPTER pAdapter)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
++	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
++
++	if (pHalData->rf_chip < RF_CHIP_MAX) {
++		if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
++		    IS_HARDWARE_TYPE_8723B(pAdapter) ||
++		    IS_HARDWARE_TYPE_8192E(pAdapter) ||
++		    IS_HARDWARE_TYPE_8703B(pAdapter) ||
++		    IS_HARDWARE_TYPE_8188F(pAdapter) ||
++		    IS_HARDWARE_TYPE_8188GTV(pAdapter)
++		) {
++
++			RTW_INFO("===> MPT_ProSetTxPower: Old\n");
++
++			mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
++			mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
++
++		} else {
++
++			mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
++			mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
++			mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
++			if(IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
++				RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
++				mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
++			}
++		}
++
++		rtw_hal_set_txpwr_done(pAdapter);
++	} else
++		RTW_INFO("RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
++
++	odm_clear_txpowertracking_state(pDM_Odm);
++}
++
++void hal_mpt_SetDataRate(PADAPTER pAdapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
++	u32 DataRate;
++
++	DataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
++
++	hal_mpt_SwitchRfSetting(pAdapter);
++
++	hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
++#ifdef CONFIG_RTL8723B
++	if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
++		if (IS_CCK_RATE(DataRate)) {
++			if (pMptCtx->mpt_rf_path == RF_PATH_A)
++				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0x6);
++			else
++				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0x6);
++		} else {
++			if (pMptCtx->mpt_rf_path == RF_PATH_A)
++				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
++			else
++				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
++		}
++	}
++
++	if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
++	     ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
++		if (pMptCtx->mpt_rf_path == RF_PATH_A)
++			phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
++		else
++			phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
++	}
++#endif
++}
++
++#define RF_PATH_AB	22
++
++#ifdef CONFIG_RTL8814A
++void mpt_ToggleIG_8814A(PADAPTER	pAdapter)
++{
++	u8 Path;
++	u32 IGReg = rA_IGI_Jaguar, IGvalue = 0;
++
++	for (Path = 0; Path <= RF_PATH_D; Path++) {
++		switch (Path) {
++		case RF_PATH_B:
++			IGReg = rB_IGI_Jaguar;
++			break;
++		case RF_PATH_C:
++			IGReg = rC_IGI_Jaguar2;
++			break;
++		case RF_PATH_D:
++			IGReg = rD_IGI_Jaguar2;
++			break;
++		default:
++			IGReg = rA_IGI_Jaguar;
++			break;
++		}
++
++		IGvalue = phy_query_bb_reg(pAdapter, IGReg, bMaskByte0);
++		phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);
++		phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue);
++	}
++}
++
++void mpt_SetRFPath_8814A(PADAPTER	pAdapter)
++{
++
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++	PMPT_CONTEXT	pMptCtx = &pAdapter->mppriv.mpt_ctx;
++	R_ANTENNA_SELECT_OFDM	*p_ofdm_tx;	/* OFDM Tx register */
++	R_ANTENNA_SELECT_CCK	*p_cck_txrx;
++	u8	ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
++	/*/PRT_HIGH_THROUGHPUT		pHTInfo = GET_HT_INFO(pMgntInfo);*/
++	/*/PRT_VERY_HIGH_THROUGHPUT	pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
++
++	u32	ulAntennaTx = pHalData->antenna_tx_path;
++	u32	ulAntennaRx = pHalData->AntennaRxPath;
++	u8	NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
++
++	if (NssforRate == RF_3TX) {
++		RTW_INFO("===> SetAntenna 3T Rate ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
++
++		switch (ulAntennaTx) {
++		case ANTENNA_BCD:
++			pMptCtx->mpt_rf_path = RF_PATH_BCD;
++			/*pHalData->ValidTxPath = 0x0e;*/
++			phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e);	/*/ 0x940[27:16]=12'b0010_0100_0111*/
++			break;
++
++		case ANTENNA_ABC:
++		default:
++			pMptCtx->mpt_rf_path = RF_PATH_ABC;
++			/*pHalData->ValidTxPath = 0x0d;*/
++			phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247);	/*/ 0x940[27:16]=12'b0010_0100_0111*/
++			break;
++		}
++
++	} else { /*/if(NssforRate == RF_1TX)*/
++		RTW_INFO("===> SetAntenna for 1T/2T Rate, ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
++		switch (ulAntennaTx) {
++		case ANTENNA_BCD:
++			pMptCtx->mpt_rf_path = RF_PATH_BCD;
++			/*pHalData->ValidTxPath = 0x0e;*/
++			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
++			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
++			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
++			break;
++
++		case ANTENNA_BC:
++			pMptCtx->mpt_rf_path = RF_PATH_BC;
++			/*pHalData->ValidTxPath = 0x06;*/
++			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
++			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
++			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
++			break;
++		case ANTENNA_B:
++			pMptCtx->mpt_rf_path = RF_PATH_B;
++			/*pHalData->ValidTxPath = 0x02;*/
++			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4);			/*/ 0xa07[7:4] = 4'b0100*/
++			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002);	/*/ 0x93C[31:20]=12'b0000_0000_0010*/
++			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2);					/* 0x80C[7:4] = 4'b0010*/
++			break;
++
++		case ANTENNA_C:
++			pMptCtx->mpt_rf_path = RF_PATH_C;
++			/*pHalData->ValidTxPath = 0x04;*/
++			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2);			/*/ 0xa07[7:4] = 4'b0010*/
++			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004);	/*/ 0x93C[31:20]=12'b0000_0000_0100*/
++			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4);					/*/ 0x80C[7:4] = 4'b0100*/
++			break;
++
++		case ANTENNA_D:
++			pMptCtx->mpt_rf_path = RF_PATH_D;
++			/*pHalData->ValidTxPath = 0x08;*/
++			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1);			/*/ 0xa07[7:4] = 4'b0001*/
++			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008);	/*/ 0x93C[31:20]=12'b0000_0000_1000*/
++			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8);					/*/ 0x80C[7:4] = 4'b1000*/
++			break;
++
++		case ANTENNA_A:
++		default:
++			pMptCtx->mpt_rf_path = RF_PATH_A;
++			/*pHalData->ValidTxPath = 0x01;*/
++			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8);			/*/ 0xa07[7:4] = 4'b1000*/
++			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001);	/*/ 0x93C[31:20]=12'b0000_0000_0001*/
++			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1);					/*/ 0x80C[7:4] = 4'b0001*/
++			break;
++		}
++	}
++
++	switch (ulAntennaRx) {
++	case ANTENNA_A:
++		/*pHalData->ValidRxPath = 0x01;*/
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
++		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
++		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
++		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
++		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
++		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
++		/*/ CCA related PD_delay_th*/
++		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
++		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
++		break;
++
++	case ANTENNA_B:
++		/*pHalData->ValidRxPath = 0x02;*/
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
++		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
++		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
++		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
++		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
++		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
++		/*/ CCA related PD_delay_th*/
++		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
++		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
++		break;
++
++	case ANTENNA_C:
++		/*pHalData->ValidRxPath = 0x04;*/
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
++		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
++		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
++		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
++		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
++		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
++		/*/ CCA related PD_delay_th*/
++		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
++		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
++		break;
++
++	case ANTENNA_D:
++		/*pHalData->ValidRxPath = 0x08;*/
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
++		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
++		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
++		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
++		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
++		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
++		/*/ CCA related PD_delay_th*/
++		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
++		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
++		break;
++
++	case ANTENNA_BC:
++		/*pHalData->ValidRxPath = 0x06;*/
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
++		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
++		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
++		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
++		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
++		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
++		/*/ CCA related PD_delay_th*/
++		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
++		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
++		break;
++
++	case ANTENNA_CD:
++		/*pHalData->ValidRxPath = 0x0C;*/
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
++		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
++		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
++		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
++		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
++		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
++		/*/ CCA related PD_delay_th*/
++		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
++		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
++		break;
++
++	case ANTENNA_BCD:
++		/*pHalData->ValidRxPath = 0x0e;*/
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
++		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
++		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
++		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
++		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
++		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
++		/*/ CCA related PD_delay_th*/
++		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
++		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
++		break;
++
++	case ANTENNA_ABCD:
++		/*pHalData->ValidRxPath = 0x0f;*/
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
++		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
++		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
++		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
++		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
++		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
++		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
++		/*/ CCA related PD_delay_th*/
++		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
++		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
++		break;
++
++	default:
++		break;
++	}
++
++	PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
++
++	mpt_ToggleIG_8814A(pAdapter);
++}
++
++#endif /* CONFIG_RTL8814A */
++#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)  || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
++void
++mpt_SetSingleTone_8814A(
++		PADAPTER	pAdapter,
++		BOOLEAN	bSingleTone,
++		BOOLEAN	bEnPMacTx)
++{
++
++	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
++	u8 StartPath = RF_PATH_A,  EndPath = RF_PATH_A, path;
++	static u32		regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
++
++	if (bSingleTone) {
++		regIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord);		/*/ 0xC1C[31:21]*/
++		regIG1 = phy_query_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord);		/*/ 0xE1C[31:21]*/
++		regIG2 = phy_query_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord);	/*/ 0x181C[31:21]*/
++		regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord);	/*/ 0x1A1C[31:21]*/
++
++		switch (pMptCtx->mpt_rf_path) {
++		case RF_PATH_A:
++		case RF_PATH_B:
++		case RF_PATH_C:
++		case RF_PATH_D:
++			StartPath = pMptCtx->mpt_rf_path;
++			EndPath = pMptCtx->mpt_rf_path;
++			break;
++		case RF_PATH_AB:
++			EndPath = RF_PATH_B;
++			break;
++		case RF_PATH_BC:
++			StartPath = RF_PATH_B;
++			EndPath = RF_PATH_C;
++			break;
++		case RF_PATH_ABC:
++			EndPath = RF_PATH_C;
++			break;
++		case RF_PATH_BCD:
++			StartPath = RF_PATH_B;
++			EndPath = RF_PATH_D;
++			break;
++		case RF_PATH_ABCD:
++			EndPath = RF_PATH_D;
++			break;
++		}
++
++		if (bEnPMacTx == FALSE) {
++			hal_mpt_SetContinuousTx(pAdapter, _TRUE);
++			issue_nulldata(pAdapter, NULL, 1, 3, 500);
++		}
++
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
++
++		for (path = StartPath; path <= EndPath; path++) {
++			phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
++			phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
++
++			phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
++		}
++
++		phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
++		phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
++		phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
++		phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
++	} else {
++		switch (pMptCtx->mpt_rf_path) {
++		case RF_PATH_A:
++		case RF_PATH_B:
++		case RF_PATH_C:
++		case RF_PATH_D:
++			StartPath = pMptCtx->mpt_rf_path;
++			EndPath = pMptCtx->mpt_rf_path;
++			break;
++		case RF_PATH_AB:
++			EndPath = RF_PATH_B;
++			break;
++		case RF_PATH_BC:
++			StartPath = RF_PATH_B;
++			EndPath = RF_PATH_C;
++			break;
++		case RF_PATH_ABC:
++			EndPath = RF_PATH_C;
++			break;
++		case RF_PATH_BCD:
++			StartPath = RF_PATH_B;
++			EndPath = RF_PATH_D;
++			break;
++		case RF_PATH_ABCD:
++			EndPath = RF_PATH_D;
++			break;
++		}
++		for (path = StartPath; path <= EndPath; path++)
++			phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */
++
++		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
++
++		if (bEnPMacTx == FALSE) {
++			if(IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
++#ifdef	PHYDM_MP_SUPPORT
++					phydm_stop_ofdm_cont_tx(pAdapter);
++					pMptCtx->bCckContTx = FALSE;
++					pMptCtx->bOfdmContTx = FALSE;
++#endif
++			} else
++					hal_mpt_SetContinuousTx(pAdapter, _FALSE);
++		}
++
++		phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
++		phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
++		phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
++		phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
++	}
++}
++
++#endif
++
++#if	defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
++void mpt_SetRFPath_8812A(PADAPTER pAdapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++	PMPT_CONTEXT	pMptCtx = &pAdapter->mppriv.mpt_ctx;
++	struct mp_priv *pmp = &pAdapter->mppriv;
++	u8		channel = pmp->channel;
++	u8		bandwidth = pmp->bandwidth;
++	u8		eLNA_2g = pHalData->ExternalLNA_2G;
++	u32		ulAntennaTx, ulAntennaRx;
++	u32 reg0xC50 = 0;
++
++	ulAntennaTx = pHalData->antenna_tx_path;
++	ulAntennaRx = pHalData->AntennaRxPath;
++
++	switch (ulAntennaTx) {
++	case ANTENNA_A:
++		pMptCtx->mpt_rf_path = RF_PATH_A;
++		phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
++		if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
++			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
++		break;
++	case ANTENNA_B:
++		pMptCtx->mpt_rf_path = RF_PATH_B;
++		phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
++		if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
++			phy_set_bb_reg(pAdapter,	r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
++		break;
++	case ANTENNA_AB:
++		pMptCtx->mpt_rf_path = RF_PATH_AB;
++		phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
++		if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
++			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
++		break;
++	default:
++		pMptCtx->mpt_rf_path = RF_PATH_AB;
++		RTW_INFO("Unknown Tx antenna.\n");
++		break;
++	}
++
++	switch (ulAntennaRx) {
++	case ANTENNA_A:
++		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
++		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
++		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
++		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
++
++		/*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
++		reg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
++		phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
++		phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
++
++		/* set PWED_TH for BB Yn user guide R29 */
++		if (IS_HARDWARE_TYPE_8812(pAdapter)) {
++			if (channel <= 14) { /* 2.4G */
++				if (bandwidth == CHANNEL_WIDTH_20
++				    && eLNA_2g == 0) {
++					/* 0x830[3:1]=3'b010 */
++					phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
++				} else
++					/* 0x830[3:1]=3'b100 */
++					phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
++			} else
++				/* 0x830[3:1]=3'b100 for 5G */
++				phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
++		}
++		break;
++	case ANTENNA_B:
++		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
++		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
++		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
++		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
++
++		/*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
++		reg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
++		phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
++		phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
++
++		/* set PWED_TH for BB Yn user guide R29 */
++		if (IS_HARDWARE_TYPE_8812(pAdapter)) {
++			if (channel <= 14) {
++				if (bandwidth == CHANNEL_WIDTH_20
++				    && eLNA_2g == 0) {
++					/* 0x830[3:1]=3'b010 */
++					phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
++				} else
++					/* 0x830[3:1]=3'b100 */
++					phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
++			} else
++				/* 0x830[3:1]=3'b100 for 5G */
++				phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
++		}
++		break;
++	case ANTENNA_AB:
++		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
++		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
++		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
++		/* set PWED_TH for BB Yn user guide R29 */
++		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
++		break;
++	default:
++		RTW_INFO("Unknown Rx antenna.\n");
++		break;
++	}
++
++	if (pHalData->rfe_type == 5 || pHalData->rfe_type == 1) {
++		if (ulAntennaTx == ANTENNA_A || ulAntennaTx == ANTENNA_AB) {
++			/* WiFi */
++			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x2);
++			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
++		} else {
++			/* BT */
++			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x1);
++			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
++		}
++	}
++}
++#endif
++
++#ifdef CONFIG_RTL8723B
++void mpt_SetRFPath_8723B(PADAPTER pAdapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++	u32		ulAntennaTx, ulAntennaRx;
++	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
++	struct dm_struct	*pDM_Odm = &pHalData->odmpriv;
++	struct dm_rf_calibration_struct	*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
++	u8 i;
++
++	ulAntennaTx = pHalData->antenna_tx_path;
++	ulAntennaRx = pHalData->AntennaRxPath;
++
++	if (pHalData->rf_chip >= RF_CHIP_MAX) {
++		RTW_INFO("This RF chip ID is not supported\n");
++		return;
++	}
++
++	switch (pAdapter->mppriv.antenna_tx) {
++	case ANTENNA_A: { /*/ Actually path S1  (Wi-Fi)*/
++		pMptCtx->mpt_rf_path = RF_PATH_A;
++		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
++		phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
++
++		for (i = 0; i < 3; ++i) {
++			u32 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
++			u32 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1];
++
++			if (offset != 0) {
++				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
++				RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
++			}
++		}
++		for (i = 0; i < 2; ++i) {
++			u32 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
++			u32 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1];
++
++			if (offset != 0) {
++				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
++				RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
++			}
++		}
++	}
++	break;
++	case ANTENNA_B: { /*/ Actually path S0 (BT)*/
++		u32 offset;
++		u32 data;
++
++		pMptCtx->mpt_rf_path = RF_PATH_B;
++		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
++		phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
++
++		for (i = 0; i < 3; ++i) {
++			/*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC  to S1 instead of S0.*/
++			offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
++			data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][1];
++			if (pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][0] != 0) {
++				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
++				RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
++			}
++		}
++		/*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
++		for (i = 0; i < 2; ++i) {
++			offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
++			data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][1];
++			if (pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][0] != 0) {
++				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
++				RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
++			}
++		}
++	}
++	break;
++	default:
++		pMptCtx->mpt_rf_path = RF_PATH_AB;
++		break;
++	}
++}
++#endif
++
++#ifdef CONFIG_RTL8703B
++void mpt_SetRFPath_8703B(PADAPTER pAdapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++	u32					ulAntennaTx, ulAntennaRx;
++	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
++	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
++	struct dm_rf_calibration_struct			*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
++	u8 i;
++
++	ulAntennaTx = pHalData->antenna_tx_path;
++	ulAntennaRx = pHalData->AntennaRxPath;
++
++	if (pHalData->rf_chip >= RF_CHIP_MAX) {
++		RTW_INFO("This RF chip ID is not supported\n");
++		return;
++	}
++
++	switch (pAdapter->mppriv.antenna_tx) {
++	case ANTENNA_A: { /* Actually path S1  (Wi-Fi) */
++		pMptCtx->mpt_rf_path = RF_PATH_A;
++		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
++		phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
++
++		for (i = 0; i < 3; ++i) {
++			u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
++			u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
++
++			if (offset != 0) {
++				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
++				RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
++			}
++
++		}
++		for (i = 0; i < 2; ++i) {
++			u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
++			u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
++
++			if (offset != 0) {
++				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
++				RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
++			}
++		}
++	}
++	break;
++	case ANTENNA_B: { /* Actually path S0 (BT)*/
++		pMptCtx->mpt_rf_path = RF_PATH_B;
++		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
++		phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
++
++		for (i = 0; i < 3; ++i) {
++			u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
++			u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
++
++			if (pRFCalibrateInfo->tx_iqc_8703b[i][0] != 0) {
++				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
++				RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
++			}
++		}
++		for (i = 0; i < 2; ++i) {
++			u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
++			u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
++
++			if (pRFCalibrateInfo->rx_iqc_8703b[i][0] != 0) {
++				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
++				RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
++			}
++		}
++	}
++	break;
++	default:
++		pMptCtx->mpt_rf_path = RF_PATH_AB;
++		break;
++	}
++
++}
++#endif
++
++#ifdef CONFIG_RTL8723D
++void mpt_SetRFPath_8723D(PADAPTER pAdapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++	u8	p = 0, i = 0;
++	u32	ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
++	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
++	struct dm_struct	*pDM_Odm = &pHalData->odmpriv;
++	struct dm_rf_calibration_struct	*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
++
++	ulAntennaTx = pHalData->antenna_tx_path;
++	ulAntennaRx = pHalData->AntennaRxPath;
++
++	if (pHalData->rf_chip >= RF_CHIP_MAX) {
++		RTW_INFO("This RF chip ID is not supported\n");
++		return;
++	}
++
++	switch (pAdapter->mppriv.antenna_tx) {
++	/* Actually path S1  (Wi-Fi) */
++	case ANTENNA_A: {
++		pMptCtx->mpt_rf_path = RF_PATH_A;
++		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0);
++	}
++	break;
++	/* Actually path S0 (BT) */
++	case ANTENNA_B: {
++		pMptCtx->mpt_rf_path = RF_PATH_B;
++		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA);
++
++	}
++	break;
++	default:
++		pMptCtx->mpt_rf_path = RF_PATH_AB;
++		break;
++	}
++}
++#endif
++
++void mpt_SetRFPath_819X(PADAPTER	pAdapter)
++{
++	HAL_DATA_TYPE			*pHalData	= GET_HAL_DATA(pAdapter);
++	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
++	u32			ulAntennaTx, ulAntennaRx;
++	R_ANTENNA_SELECT_OFDM	*p_ofdm_tx;	/* OFDM Tx register */
++	R_ANTENNA_SELECT_CCK	*p_cck_txrx;
++	u8		r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
++	u8		chgTx = 0, chgRx = 0;
++	u32		r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
++
++	ulAntennaTx = pHalData->antenna_tx_path;
++	ulAntennaRx = pHalData->AntennaRxPath;
++
++	p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
++	p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
++
++	p_ofdm_tx->r_ant_ht1			= 0x1;
++	p_ofdm_tx->r_ant_ht2			= 0x2;/*Second TX RF path is A*/
++	p_ofdm_tx->r_ant_non_ht			= 0x3;/*/ 0x1+0x2=0x3 */
++
++	switch (ulAntennaTx) {
++	case ANTENNA_A:
++		p_ofdm_tx->r_tx_antenna		= 0x1;
++		r_ofdm_tx_en_val		= 0x1;
++		p_ofdm_tx->r_ant_l		= 0x1;
++		p_ofdm_tx->r_ant_ht_s1		= 0x1;
++		p_ofdm_tx->r_ant_non_ht_s1	= 0x1;
++		p_cck_txrx->r_ccktx_enable	= 0x8;
++		chgTx = 1;
++		/*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
++		/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
++		{
++			phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
++			phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
++			r_ofdm_tx_en_val			= 0x3;
++			/*/ Power save*/
++			/*/cosa r_ant_select_ofdm_val = 0x11111111;*/
++			/*/ We need to close RFB by SW control*/
++			if (pHalData->rf_type == RF_2T2R) {
++				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
++				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
++				phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
++				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
++				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
++			}
++		}
++		pMptCtx->mpt_rf_path = RF_PATH_A;
++		break;
++	case ANTENNA_B:
++		p_ofdm_tx->r_tx_antenna		= 0x2;
++		r_ofdm_tx_en_val		= 0x2;
++		p_ofdm_tx->r_ant_l		= 0x2;
++		p_ofdm_tx->r_ant_ht_s1		= 0x2;
++		p_ofdm_tx->r_ant_non_ht_s1	= 0x2;
++		p_cck_txrx->r_ccktx_enable	= 0x4;
++		chgTx = 1;
++		/*/ From SD3 Willis suggestion !!! Set RF A as standby*/
++		/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
++		{
++			phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
++			phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
++
++			/*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
++			/*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
++			if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
++				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
++				phy_set_bb_reg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
++				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
++				/*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
++				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
++				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
++			}
++		}
++		pMptCtx->mpt_rf_path = RF_PATH_B;
++		break;
++	case ANTENNA_AB:/*/ For 8192S*/
++		p_ofdm_tx->r_tx_antenna		= 0x3;
++		r_ofdm_tx_en_val		= 0x3;
++		p_ofdm_tx->r_ant_l		= 0x3;
++		p_ofdm_tx->r_ant_ht_s1		= 0x3;
++		p_ofdm_tx->r_ant_non_ht_s1	= 0x3;
++		p_cck_txrx->r_ccktx_enable	= 0xC;
++		chgTx = 1;
++		/*/ From SD3Willis suggestion !!! Set RF B as standby*/
++		/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
++		{
++			phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
++			phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
++			/* Disable Power save*/
++			/*cosa r_ant_select_ofdm_val = 0x3321333;*/
++			/* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
++			if (pHalData->rf_type == RF_2T2R) {
++				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
++
++				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
++				/*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
++				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
++				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
++			}
++		}
++		pMptCtx->mpt_rf_path = RF_PATH_AB;
++		break;
++	default:
++		break;
++	}
++#if 0
++	/*  r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
++	/*  r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
++	/* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D	 */
++#endif
++	switch (ulAntennaRx) {
++	case ANTENNA_A:
++		r_rx_antenna_ofdm		= 0x1;	/* A*/
++		p_cck_txrx->r_cckrx_enable	= 0x0;	/* default: A*/
++		p_cck_txrx->r_cckrx_enable_2	= 0x0;	/* option: A*/
++		chgRx = 1;
++		break;
++	case ANTENNA_B:
++		r_rx_antenna_ofdm			= 0x2;	/*/ B*/
++		p_cck_txrx->r_cckrx_enable	= 0x1;	/*/ default: B*/
++		p_cck_txrx->r_cckrx_enable_2	= 0x1;	/*/ option: B*/
++		chgRx = 1;
++		break;
++	case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/
++		r_rx_antenna_ofdm		= 0x3;/*/ AB*/
++		p_cck_txrx->r_cckrx_enable	= 0x0;/*/ default:A*/
++		p_cck_txrx->r_cckrx_enable_2	= 0x1;/*/ option:B*/
++		chgRx = 1;
++		break;
++	default:
++		break;
++	}
++
++
++	if (chgTx && chgRx) {
++		switch (pHalData->rf_chip) {
++		case RF_8225:
++		case RF_8256:
++		case RF_6052:
++			/*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
++			phy_set_bb_reg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val);		/*/OFDM Tx*/
++			phy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val);		/*/OFDM Tx*/
++			phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);	/*/OFDM Rx*/
++			phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);	/*/OFDM Rx*/
++			if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
++				phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm);	/*/OFDM Rx*/
++				phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm);	/*/OFDM Rx*/
++			}
++			phy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
++			break;
++
++		default:
++			RTW_INFO("Unsupported RFChipID for switching antenna.\n");
++			break;
++		}
++	}
++}	/* MPT_ProSetRFPath */
++
++#ifdef CONFIG_RTL8192F
++
++void mpt_set_rfpath_8192f(PADAPTER	pAdapter)
++{
++	HAL_DATA_TYPE			*pHalData	= GET_HAL_DATA(pAdapter);
++	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
++
++	u16		ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
++	u8				NssforRate, odmNssforRate;
++	u32				ulAntennaTx, ulAntennaRx;
++	enum bb_path	RxAntToPhyDm;
++	enum bb_path	TxAntToPhyDm;
++
++	ulAntennaTx = pHalData->antenna_tx_path;
++	ulAntennaRx = pHalData->AntennaRxPath;
++	NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
++
++	if (pHalData->rf_chip >= RF_TYPE_MAX)
++		RTW_INFO("This RF chip ID is not supported\n");
++
++	switch (ulAntennaTx) {
++	case ANTENNA_A:
++			pMptCtx->mpt_rf_path = RF_PATH_A;
++			TxAntToPhyDm = BB_PATH_A;
++			break;
++	case ANTENNA_B:
++			pMptCtx->mpt_rf_path = RF_PATH_B;
++			TxAntToPhyDm = BB_PATH_B;
++			break;
++	case ANTENNA_AB:
++			pMptCtx->mpt_rf_path = RF_PATH_AB;
++			TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
++			break;
++	default:
++			pMptCtx->mpt_rf_path = RF_PATH_AB;
++			TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
++			break;
++	}
++
++	switch (ulAntennaRx) {
++	case ANTENNA_A:
++			RxAntToPhyDm = BB_PATH_A;
++			break;
++	case ANTENNA_B:
++			RxAntToPhyDm = BB_PATH_B;
++			break;
++	case ANTENNA_AB:
++			RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
++			break;
++	default:
++			RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
++			break;
++	}
++
++	phydm_api_trx_mode(GET_PDM_ODM(pAdapter), TxAntToPhyDm, RxAntToPhyDm, TxAntToPhyDm);
++
++}
++
++#endif
++
++void hal_mpt_SetAntenna(PADAPTER	pAdapter)
++{
++	PHAL_DATA_TYPE hal;
++	ANTENNA_PATH anttx;
++	enum bb_path bb_tx = 0;
++
++
++	hal = GET_HAL_DATA(pAdapter);
++	anttx = hal->antenna_tx_path;
++
++	switch (anttx) {
++	case ANTENNA_A:
++		bb_tx = BB_PATH_A;
++		break;
++	case ANTENNA_B:
++		bb_tx = BB_PATH_B;
++		break;
++	case ANTENNA_C:
++		bb_tx = BB_PATH_C;
++		break;
++	case ANTENNA_D:
++		bb_tx = BB_PATH_D;
++		break;
++	case ANTENNA_AB:
++		bb_tx = BB_PATH_AB;
++		break;
++	case ANTENNA_AC:
++		bb_tx = BB_PATH_AC;
++		break;
++	case ANTENNA_AD:
++		bb_tx = BB_PATH_AD;
++		break;
++	case ANTENNA_BC:
++		bb_tx = BB_PATH_BC;
++		break;
++	case ANTENNA_BD:
++		bb_tx = BB_PATH_BD;
++		break;
++	case ANTENNA_CD:
++		bb_tx = BB_PATH_CD;
++		break;
++	case ANTENNA_ABC:
++		bb_tx = BB_PATH_ABC;
++		break;
++	case ANTENNA_BCD:
++		bb_tx = BB_PATH_BCD;
++		break;
++	case ANTENNA_ABD:
++		bb_tx = BB_PATH_ABD;
++		break;
++	case ANTENNA_ACD:
++		bb_tx = BB_PATH_ACD;
++		break;
++	case ANTENNA_ABCD:
++		bb_tx = BB_PATH_ABCD;
++		break;
++	default:
++		bb_tx = BB_PATH_A;
++		break;
++	}
++	tx_path_nss_set_full_tx(hal->txpath_nss, hal->txpath_num_nss, bb_tx);
++	RTW_INFO("%s ,ant idx %d, tx path_num_nss = %d\n", __func__, anttx, hal->txpath_num_nss[0]);
++
++#ifdef CONFIG_RTL8822C
++	if (IS_HARDWARE_TYPE_8822C(pAdapter)) {
++		rtl8822c_mp_config_rfpath(pAdapter);
++		return;
++	}
++#endif
++#ifdef CONFIG_RTL8814A
++	if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
++		mpt_SetRFPath_8814A(pAdapter);
++		return;
++	}
++#endif
++#ifdef CONFIG_RTL8822B
++	if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
++		rtl8822b_mp_config_rfpath(pAdapter);
++		return;
++	}
++#endif
++#ifdef CONFIG_RTL8821C
++	if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
++		rtl8821c_mp_config_rfpath(pAdapter);
++		return;
++	}
++#endif
++#if	defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
++	if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
++		mpt_SetRFPath_8812A(pAdapter);
++		return;
++	}
++#endif
++#ifdef CONFIG_RTL8723B
++	if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
++		mpt_SetRFPath_8723B(pAdapter);
++		return;
++	}
++#endif
++
++#ifdef CONFIG_RTL8703B
++	if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
++		mpt_SetRFPath_8703B(pAdapter);
++		return;
++	}
++#endif
++
++#ifdef CONFIG_RTL8723D
++	if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
++		mpt_SetRFPath_8723D(pAdapter);
++		return;
++	}
++#endif
++
++#ifdef CONFIG_RTL8192F
++		if (IS_HARDWARE_TYPE_8192F(pAdapter)) {
++			mpt_set_rfpath_8192f(pAdapter);
++			return;
++		}
++#endif
++
++#ifdef CONFIG_RTL8814B
++	if (IS_HARDWARE_TYPE_8814B(pAdapter)) {
++		rtl8814b_mp_config_rfpath(pAdapter);
++		return;
++	}
++#endif
++
++	/*	else if (IS_HARDWARE_TYPE_8821B(pAdapter))
++			mpt_SetRFPath_8821B(pAdapter);
++		Prepare for 8822B
++		else if (IS_HARDWARE_TYPE_8822B(Context))
++			mpt_SetRFPath_8822B(Context);
++	*/
++	mpt_SetRFPath_819X(pAdapter);
++	RTW_INFO("mpt_SetRFPath_819X Do %s\n", __func__);
++}
++
++s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++
++	if (!netif_running(pAdapter->pnetdev)) {
++		return _FAIL;
++	}
++
++
++	if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
++		return _FAIL;
++	}
++
++	target_ther &= 0xff;
++
++	pHalData->eeprom_thermal_meter = target_ther;
++
++	return _SUCCESS;
++}
++
++
++void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
++{
++	if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
++		phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
++		phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x0);
++		phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
++	} else
++		phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
++
++}
++
++
++u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path)
++
++{
++	struct dm_struct *p_dm_odm = adapter_to_phydm(pAdapter);
++
++	u32 ThermalValue = 0;
++	s32 thermal_value_temp = 0;
++	s8 thermal_offset = 0;
++	u32 thermal_reg_mask = 0;
++
++	if (IS_8822C_SERIES(GET_HAL_DATA(pAdapter)->version_id))
++			thermal_reg_mask = 0x007e; 	/*0x42: RF Reg[6:1], 35332(themal K  & bias k & power trim) & 35325(tssi )*/
++	else
++			thermal_reg_mask = 0xfc00;	/*0x42: RF Reg[15:10]*/
++
++	ThermalValue = (u8)phy_query_rf_reg(pAdapter, rf_path, 0x42, thermal_reg_mask);
++
++	thermal_offset = phydm_get_thermal_offset(p_dm_odm);
++
++	thermal_value_temp = ThermalValue + thermal_offset;
++
++	if (thermal_value_temp > 63)
++		ThermalValue = 63;
++	else if (thermal_value_temp < 0)
++		ThermalValue = 0;
++	else
++		ThermalValue = thermal_value_temp;
++
++	return (u8)ThermalValue;
++}
++
++
++void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value)
++{
++#if 0
++	fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
++	rtw_msleep_os(1000);
++	fw_cmd_data(pAdapter, value, 1);
++	*value &= 0xFF;
++#else
++	hal_mpt_TriggerRFThermalMeter(pAdapter);
++	rtw_msleep_os(1000);
++	*value = hal_mpt_ReadRFThermalMeter(pAdapter, rfpath);
++#endif
++
++}
++
++
++void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
++
++	pAdapter->mppriv.mpt_ctx.bSingleCarrier = bStart;
++
++	if (bStart) {/*/ Start Single Carrier.*/
++		/*/ Start Single Carrier.*/
++		/*/ 1. if OFDM block on?*/
++		if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
++			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
++
++		/*/ 2. set CCK test mode off, set to CCK normal mode*/
++		phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
++
++		/*/ 3. turn on scramble setting*/
++		phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
++
++		/*/ 4. Turn On Continue Tx and turn off the other test modes.*/
++#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
++		if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
++			phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
++		else
++#endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
++			phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);
++
++	} else {
++		/*/ Stop Single Carrier.*/
++		/*/ Stop Single Carrier.*/
++		/*/ Turn off all test modes.*/
++#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
++		if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
++			phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
++		else
++#endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
++			phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
++
++		rtw_msleep_os(10);
++		/*/BB Reset*/
++		phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
++		phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
++	}
++}
++
++
++void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
++	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
++	u32			ulAntennaTx = pHalData->antenna_tx_path;
++	static u32		regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
++	u8 rfPath;
++
++	if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
++#ifdef	PHYDM_MP_SUPPORT
++#ifdef CONFIG_RTL8814B
++		if(pHalData->current_channel_bw == CHANNEL_WIDTH_80_80)
++		{
++			/* @Tx mode: RF0x00[19:16]=4'b0010 */
++			config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0xF0000, 0x2);
++			/* @Lowest RF gain index: RF_0x0[4:0] = 0*/
++			config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0x1F, 0x0);
++			/* @RF LO enabled */
++			config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x58, BIT(1), 0x1);
++			/* @SYN1 */
++			config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0xF0000, 0x2);
++			config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0x1F, 0x0);
++			config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x58, BIT(1), 0x1);
++		}
++#endif
++		phydm_mp_set_single_tone(pDM_Odm, bStart, pMptCtx->mpt_rf_path);
++#endif
++		return;
++	}
++
++	switch (ulAntennaTx) {
++	case ANTENNA_B:
++		rfPath = RF_PATH_B;
++		break;
++	case ANTENNA_C:
++		rfPath = RF_PATH_C;
++		break;
++	case ANTENNA_D:
++		rfPath = RF_PATH_D;
++		break;
++	case ANTENNA_A:
++	default:
++		rfPath = RF_PATH_A;
++		break;
++	}
++
++	pAdapter->mppriv.mpt_ctx.is_single_tone = bStart;
++	if (bStart) {
++		/*/ Start Single Tone.*/
++		/*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
++		if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
++			regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask);
++			phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
++			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
++			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
++		} else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
++			/*/Set MAC REG 88C: Prevent SingleTone Fail*/
++			phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF);
++			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/
++			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
++		}	else if (IS_HARDWARE_TYPE_8192F(pAdapter)) { /* USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
++ #ifdef CONFIG_RTL8192F
++			phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x1);
++			phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x1);
++			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x1);
++			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x1);
++			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x1);
++			phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x1);
++			phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0xF);
++			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x1); /* RF LO disabled*/
++			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /* Tx mode*/
++#endif
++		} else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
++			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
++				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
++				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
++			} else {
++				/*/ S0/S1 both use PATH A to configure*/
++				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
++				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
++			}
++		} else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
++			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
++				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
++				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
++			}
++		} else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
++			/*Set BB REG 88C: Prevent SingleTone Fail*/
++			phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
++			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1);
++			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2);
++
++		} else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
++			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
++				phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
++				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
++				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x1);
++			} else {/* S0/S1 both use PATH A to configure */
++				phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
++				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
++				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x1);
++			}
++		} else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
++#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
++			u8 p = RF_PATH_A;
++
++			regRF = phy_query_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
++			regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
++			regBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
++			regBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);
++			regBB3 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);
++
++			phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/
++
++			if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
++				for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
++					phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
++					phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
++					phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
++				}
++			} else {
++				phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
++				phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
++#ifdef CONFIG_RTL8821C
++				if (IS_HARDWARE_TYPE_8821C(pAdapter) && pDM_Odm->current_rf_set_8821c == SWITCH_TO_BTG)
++					phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x75, BIT16, 0x1); /* RF LO (for BTG) enabled */
++				else
++#endif
++					phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
++			}
++			if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
++					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777);  /* 0xCB0=0x77777777*/
++					phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777);  /* 0xEB0=0x77777777*/
++					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777);  /* 0xCB4[15:0] = 0x7777*/
++					phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777);  /* 0xEB4[15:0] = 0x7777*/
++					phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xFFF, 0xb); /* 0xCBC[23:16] = 0x12*/
++					phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xFFF, 0x830); /* 0xEBC[23:16] = 0x12*/
++			} else if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
++				phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xF0F0, 0x707);  /* 0xCB0[[15:12, 7:4] = 0x707*/
++
++				if (pHalData->external_pa_5g)
++				{
++					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
++				}
++				else if (pHalData->ExternalPA_2G)
++				{
++					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
++				}
++			} else {
++				phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
++				phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
++
++				if (pHalData->external_pa_5g) {
++					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
++					phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
++				} else if (pHalData->ExternalPA_2G) {
++					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
++					phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
++				}
++			}
++#endif
++		}
++#if defined(CONFIG_RTL8814A)
++				else if (IS_HARDWARE_TYPE_8814A(pAdapter))
++						mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
++#endif
++		else	/*/ Turn On SingleTone and turn off the other test modes.*/
++			phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
++
++		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
++		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
++
++	} else {/*/ Stop Single Ton e.*/
++
++		if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
++			phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF);
++			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
++			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
++		} else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
++			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
++			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */
++			/*/ RESTORE MAC REG 88C: Enable RF Functions*/
++			phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0);
++		} else if (IS_HARDWARE_TYPE_8192F(pAdapter)){
++#ifdef CONFIG_RTL8192F
++			phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x0);
++			phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x0);
++			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x0);
++			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x0);
++			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x0);
++			phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x0);
++			phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0x0);
++			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x0); /* RF LO disabled*/
++			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /* Rx mode*/
++#endif
++		} else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
++			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
++				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
++				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
++			} else {
++				/*/ S0/S1 both use PATH A to configure*/
++				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
++				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
++			}
++		} else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
++			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
++				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
++				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
++			}
++		} else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
++			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/
++			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/
++			/*Set BB REG 88C: Prevent SingleTone Fail*/
++			phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
++		} else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
++			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
++				phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
++				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
++				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x0);
++			} else {	/* S0/S1 both use PATH A to configure */
++				phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
++				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
++				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x0);
++			}
++		} else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
++#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
++			u8 p = RF_PATH_A;
++
++			phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
++
++			if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
++				for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
++					phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
++					phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
++				}
++			} else {
++				p = pMptCtx->mpt_rf_path;
++				phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
++
++				if (IS_HARDWARE_TYPE_8821C(pAdapter))
++					phy_set_rf_reg(pAdapter, p, 0x75, BIT16, 0x0); /* RF LO (for BTG) disabled */
++
++				phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
++			}
++
++			phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
++			phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
++			phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);
++			phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);
++
++			if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
++				RTW_INFO("Restore RFE control Pin cbc\n");
++				phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xfff, 0x0);
++				phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xfff, 0x0);
++			}
++#endif
++		}
++#if defined(CONFIG_RTL8814A)
++		else if (IS_HARDWARE_TYPE_8814A(pAdapter))
++			mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
++
++		else/*/ Turn off all test modes.*/
++			phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
++#endif
++		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
++		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
++
++	}
++}
++
++void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++	struct dm_struct		*pdm_odm = &pHalData->odmpriv;
++	u8 Rate;
++
++	pAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart;
++
++	if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
++#ifdef PHYDM_MP_SUPPORT
++		phydm_mp_set_carrier_supp(pdm_odm, bStart, pAdapter->mppriv.rateidx);
++#endif
++		return;
++	}
++
++	Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
++	if (bStart) {/* Start Carrier Suppression.*/
++		if (Rate <= MPT_RATE_11M) {
++			/*/ 1. if CCK block on?*/
++			if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
++				write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
++
++			/*/Turn Off All Test Mode*/
++			if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
++				phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
++			else
++				phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
++
++			write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);    /*/transmit mode*/
++			write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0);  /*/turn off scramble setting*/
++
++			/*/Set CCK Tx Test Rate*/
++			write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);    /*/Set FTxRate to 1Mbps*/
++		}
++
++		/*Set for dynamic set Power index*/
++		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
++		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
++
++	} else {/* Stop Carrier Suppression.*/
++
++		if (Rate <= MPT_RATE_11M) {
++			write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);    /*normal mode*/
++			write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1);  /*turn on scramble setting*/
++
++			/*BB Reset*/
++			write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
++			write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
++		}
++		/*Stop for dynamic set Power index*/
++		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
++		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
++	}
++	RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n");
++}
++
++u32 hal_mpt_query_phytxok(PADAPTER	pAdapter)
++{
++	PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
++	RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
++	HAL_DATA_TYPE			*pHalData	= GET_HAL_DATA(pAdapter);
++	u16 count = 0;
++
++#ifdef PHYDM_MP_SUPPORT
++	struct dm_struct *dm = (struct dm_struct *)&pHalData->odmpriv;
++	struct phydm_mp *mp = &dm->dm_mp_table;
++
++	if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
++		phydm_mp_get_tx_ok(&pHalData->odmpriv, pAdapter->mppriv.rateidx);
++		count = mp->tx_phy_ok_cnt;
++
++	} else
++#endif
++	{
++
++	if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
++		count = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
++	else
++		count = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
++	}
++
++	if (count > 50000) {
++		rtw_reset_phy_trx_ok_counters(pAdapter);
++		pAdapter->mppriv.tx.sended += count;
++		count = 0;
++	}
++
++	return pAdapter->mppriv.tx.sended + count;
++
++}
++
++static	void mpt_StopCckContTx(
++	PADAPTER	pAdapter
++)
++{
++	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
++	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
++	u8			u1bReg;
++
++	pMptCtx->bCckContTx = FALSE;
++	pMptCtx->bOfdmContTx = FALSE;
++
++	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);	/*normal mode*/
++	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1);	/*turn on scramble setting*/
++
++	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
++		phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0);			/* 0xa15[1:0] = 2b00*/
++		phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);		/* 0xc08[16] = 0*/
++
++		phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
++		phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0);
++		phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0);
++	}
++
++	/*BB Reset*/
++	phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
++	phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
++
++	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
++	phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
++	phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
++	}
++
++	if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
++		IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
++		IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
++		IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
++		phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);/* patch Count CCK adjust Rate*/
++	}
++
++}	/* mpt_StopCckContTx */
++
++
++static	void mpt_StopOfdmContTx(
++	PADAPTER	pAdapter
++)
++{
++	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
++	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
++	u8			u1bReg;
++	u32			data;
++
++	pMptCtx->bCckContTx = FALSE;
++	pMptCtx->bOfdmContTx = FALSE;
++
++	if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
++		phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
++	else
++		phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
++
++	rtw_mdelay_os(10);
++
++	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)){
++		phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0);			/* 0xa15[1:0] = 0*/
++		phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);		/* 0xc08[16] = 0*/
++	}
++
++	/*BB Reset*/
++	phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
++	phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
++
++	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
++	phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
++	phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
++	}
++}	/* mpt_StopOfdmContTx */
++
++
++static	void mpt_StartCckContTx(
++	PADAPTER		pAdapter
++)
++{
++	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
++	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
++	u32			cckrate;
++
++	/* 1. if CCK block on */
++	if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn))
++		phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
++
++	/*Turn Off All Test Mode*/
++	if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
++		phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
++	else
++		phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
++
++	cckrate  = pAdapter->mppriv.rateidx;
++
++	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
++
++	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);	/*transmit mode*/
++	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1);	/*turn on scramble setting*/
++
++	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
++		phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3);			/* 0xa15[1:0] = 11 force cck rxiq = 0*/
++		phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1);		/* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
++		phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
++		phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1);
++		phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1);
++	}
++
++	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
++		phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
++		phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
++	}
++
++	if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
++		IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
++		IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
++		IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
++		if (pAdapter->mppriv.rateidx == MPT_RATE_1M) /* patch Count CCK adjust Rate*/
++			phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);
++		else
++			phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bEnable);
++	}
++
++	pMptCtx->bCckContTx = TRUE;
++	pMptCtx->bOfdmContTx = FALSE;
++
++}	/* mpt_StartCckContTx */
++
++
++static	void mpt_StartOfdmContTx(
++	PADAPTER		pAdapter
++)
++{
++	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
++	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
++
++	/* 1. if OFDM block on?*/
++	if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
++		phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
++
++	/* 2. set CCK test mode off, set to CCK normal mode*/
++	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
++
++	/* 3. turn on scramble setting*/
++	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
++
++	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
++		phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3);			/* 0xa15[1:0] = 2b'11*/
++		phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1);		/* 0xc08[16] = 1*/
++	}
++
++	/* 4. Turn On Continue Tx and turn off the other test modes.*/
++	if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
++		phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
++	else
++		phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
++
++	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
++		phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
++		phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
++	}
++
++	pMptCtx->bCckContTx = FALSE;
++	pMptCtx->bOfdmContTx = TRUE;
++}	/* mpt_StartOfdmContTx */
++
++#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)  || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
++#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
++static void mpt_convert_phydm_txinfo_for_jaguar3(
++	RT_PMAC_TX_INFO	*pMacTxInfo, struct phydm_pmac_info *phydmtxinfo)
++{
++	phydmtxinfo->en_pmac_tx = pMacTxInfo->bEnPMacTx;
++	phydmtxinfo->mode = pMacTxInfo->Mode;
++	phydmtxinfo->tx_rate = MRateToHwRate(mpt_to_mgnt_rate(pMacTxInfo->TX_RATE));
++	phydmtxinfo->tx_sc = pMacTxInfo->TX_SC;
++	phydmtxinfo->is_short_preamble = pMacTxInfo->bSPreamble;
++	phydmtxinfo->ndp_sound = pMacTxInfo->NDP_sound;
++	phydmtxinfo->bw = pMacTxInfo->BandWidth;
++	phydmtxinfo->m_stbc = pMacTxInfo->m_STBC;
++	phydmtxinfo->packet_period = pMacTxInfo->PacketPeriod;
++	phydmtxinfo->packet_count = pMacTxInfo->PacketCount;
++	phydmtxinfo->packet_pattern = pMacTxInfo->PacketPattern;
++	phydmtxinfo->sfd = pMacTxInfo->SFD;
++	phydmtxinfo->signal_field = pMacTxInfo->SignalField;
++	phydmtxinfo->service_field = pMacTxInfo->ServiceField;
++	phydmtxinfo->length = pMacTxInfo->LENGTH;
++	_rtw_memcpy(&phydmtxinfo->crc16,pMacTxInfo->CRC16, 2);
++	_rtw_memcpy(&phydmtxinfo->lsig , pMacTxInfo->LSIG,3);
++	_rtw_memcpy(&phydmtxinfo->ht_sig , pMacTxInfo->HT_SIG,6);
++	_rtw_memcpy(&phydmtxinfo->vht_sig_a , pMacTxInfo->VHT_SIG_A,6);
++	_rtw_memcpy(&phydmtxinfo->vht_sig_b , pMacTxInfo->VHT_SIG_B,4);
++	phydmtxinfo->vht_sig_b_crc = pMacTxInfo->VHT_SIG_B_CRC;
++	_rtw_memcpy(&phydmtxinfo->vht_delimiter,pMacTxInfo->VHT_Delimiter,4);
++}
++#endif
++
++/* for HW TX mode */
++u8 mpt_ProSetPMacTx(PADAPTER	Adapter)
++{
++	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
++	PMPT_CONTEXT	pMptCtx		=	&(Adapter->mppriv.mpt_ctx);
++	struct mp_priv *pmppriv = &Adapter->mppriv;
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
++	RT_PMAC_TX_INFO	PMacTxInfo	=	pMptCtx->PMacTxInfo;
++	struct dm_struct *p_dm_odm;
++	u32			u4bTmp;
++	u8 status = _TRUE;
++
++	p_dm_odm = &pHalData->odmpriv;
++
++#if 0
++	PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
++	PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);
++	PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);
++	PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);
++	dbg_print("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
++	PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
++
++	PRINT_DATA("Src Address", Adapter->mac_addr, ETH_ALEN);
++	PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, ETH_ALEN);
++#endif
++	if (pmppriv->pktInterval != 0)
++		PMacTxInfo.PacketPeriod = pmppriv->pktInterval;
++
++    	if (pmppriv->tx.count != 0)
++        	PMacTxInfo.PacketCount = pmppriv->tx.count;
++
++	RTW_INFO("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
++	RTW_INFO("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
++		 PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
++
++	if (hal_spec->tx_nss_num < 2 && MPT_IS_2SS_RATE(PMacTxInfo.TX_RATE))
++		return _FALSE;
++	if (hal_spec->tx_nss_num < 3 && MPT_IS_3SS_RATE(PMacTxInfo.TX_RATE))
++		return _FALSE;
++	if (hal_spec->tx_nss_num < 4 && MPT_IS_4SS_RATE(PMacTxInfo.TX_RATE))
++		return _FALSE;
++	if (!is_supported_vht(Adapter->registrypriv.wireless_mode) && MPT_IS_VHT_RATE(PMacTxInfo.TX_RATE))
++		return _FALSE;
++	if (!is_supported_ht(Adapter->registrypriv.wireless_mode) && MPT_IS_HT_RATE(PMacTxInfo.TX_RATE))
++		return _FALSE;
++
++	if (PMacTxInfo.BandWidth == 1 && hal_chk_bw_cap(Adapter, BW_CAP_40M))
++		PMacTxInfo.BandWidth = CHANNEL_WIDTH_40;
++	else if (PMacTxInfo.BandWidth == 2 && hal_chk_bw_cap(Adapter, BW_CAP_80M))
++		PMacTxInfo.BandWidth = CHANNEL_WIDTH_80;
++	else
++		PMacTxInfo.BandWidth = CHANNEL_WIDTH_20;
++
++	if (IS_HARDWARE_TYPE_JAGUAR3(Adapter)) {
++#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
++		struct phydm_pmac_info phydm_mactxinfo;
++
++		if (PMacTxInfo.bEnPMacTx == TRUE) {
++			pMptCtx->HWTxmode = PMacTxInfo.Mode;
++			pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
++			if (PMacTxInfo.Mode == CONTINUOUS_TX)
++				hal_mpt_SetTxPower(Adapter);
++		} else {
++			PMacTxInfo.Mode = pMptCtx->HWTxmode;
++			PMacTxInfo.TX_RATE = pMptCtx->mpt_rate_index;
++			pMptCtx->HWTxmode = TEST_NONE;
++		}
++		mpt_convert_phydm_txinfo_for_jaguar3(&PMacTxInfo, &phydm_mactxinfo);
++		phydm_set_pmac_tx(p_dm_odm, &phydm_mactxinfo, pMptCtx->mpt_rf_path);
++#endif
++		return status;
++	}
++
++	if (PMacTxInfo.bEnPMacTx == FALSE) {
++		if (pMptCtx->HWTxmode == CONTINUOUS_TX) {
++			phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);			/*	TX Stop*/
++			if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
++				mpt_StopCckContTx(Adapter);
++			else
++				mpt_StopOfdmContTx(Adapter);
++		} else if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index)) {
++			u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord);
++			phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
++			phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);		/*TX Stop*/
++		} else
++			phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);		/*	TX Stop*/
++
++		if (pMptCtx->HWTxmode == OFDM_Single_Tone_TX) {
++			/* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
++			if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
++				mpt_StopCckContTx(Adapter);
++			else
++				mpt_StopOfdmContTx(Adapter);
++
++			mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);
++		}
++		pMptCtx->HWTxmode = TEST_NONE;
++		return status;
++	}
++
++    	pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
++
++	if (PMacTxInfo.Mode == CONTINUOUS_TX) {
++		pMptCtx->HWTxmode = CONTINUOUS_TX;
++		PMacTxInfo.PacketCount = 1;
++
++        	hal_mpt_SetTxPower(Adapter);
++
++		if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
++			mpt_StartCckContTx(Adapter);
++		else
++			mpt_StartOfdmContTx(Adapter);
++	} else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
++		/* Continuous TX -> HW TX -> RF Setting */
++		pMptCtx->HWTxmode = OFDM_Single_Tone_TX;
++		PMacTxInfo.PacketCount = 1;
++
++		if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
++			mpt_StartCckContTx(Adapter);
++		else
++			mpt_StartOfdmContTx(Adapter);
++	} else if (PMacTxInfo.Mode == PACKETS_TX) {
++		pMptCtx->HWTxmode = PACKETS_TX;
++		if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
++			PMacTxInfo.PacketCount = 0xffff;
++	}
++
++	if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
++		/* 0xb1c[0:15] TX packet count 0xb1C[31:16]	SFD*/
++		u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16);
++		phy_set_bb_reg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
++		/* 0xb40 7:0 SIGNAL	15:8 SERVICE	31:16 LENGTH*/
++		u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16);
++		phy_set_bb_reg(Adapter, 0xb40, bMaskDWord, u4bTmp);
++		u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);
++		phy_set_bb_reg(Adapter, 0xb44, bMaskLWord, u4bTmp);
++
++		if (PMacTxInfo.bSPreamble)
++			phy_set_bb_reg(Adapter, 0xb0c, BIT27, 0);
++		else
++			phy_set_bb_reg(Adapter, 0xb0c, BIT27, 1);
++	} else {
++		phy_set_bb_reg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
++
++		u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24);
++		phy_set_bb_reg(Adapter, 0xb08, bMaskDWord, u4bTmp);	/*	Set 0xb08[23:0] = LSIG, 0xb08[31:24] =  Data init octet*/
++
++		if (PMacTxInfo.PacketPattern == 0x12)
++			u4bTmp = 0x3000000;
++		else
++			u4bTmp = 0;
++	}
++
++	if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {
++		u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16);
++		phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
++		u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16);
++		phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
++	} else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
++		u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16);
++		phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
++		u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16);
++		phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
++
++		_rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);
++		phy_set_bb_reg(Adapter, 0xb14, bMaskDWord, u4bTmp);
++	}
++
++	if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
++		u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod;	/* for TX interval */
++		phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, u4bTmp);
++
++		_rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);
++		phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, u4bTmp);
++
++		/* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/
++		/*& Duration & Frame control*/
++		phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, 0x00000040);
++
++		/* Address1 [0:3]*/
++		u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
++		phy_set_bb_reg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
++
++		/* Address3 [3:0]*/
++		phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
++
++		/* Address2[0:1] & Address1 [5:4]*/
++		u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
++		phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
++
++		/* Address2 [5:2]*/
++		u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
++		phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
++
++		/* Sequence Control & Address3 [5:4]*/
++		/*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/
++		/*phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
++	} else {
++		phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod);	/* for TX interval*/
++		/* & Duration & Frame control */
++		phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, 0x00000040);
++
++		/* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/
++		/* Address1 [0:3]*/
++		u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
++		phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, u4bTmp);
++
++		/* Address3 [3:0]*/
++		phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
++
++		/* Address2[0:1] & Address1 [5:4]*/
++		u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
++		phy_set_bb_reg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
++
++		/* Address2 [5:2] */
++		u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
++		phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
++
++		/* Sequence Control & Address3 [5:4]*/
++		u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);
++		phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
++	}
++
++	phy_set_bb_reg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
++
++	/* 0xb4c 3:0 TXSC	5:4	BW	7:6 m_STBC	8 NDP_Sound*/
++	u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8);
++	phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp);
++
++	if (IS_HARDWARE_TYPE_JAGUAR2(Adapter)) {
++		u32 offset = 0xb44;
++
++		if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
++			phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
++		else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
++			phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
++		else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
++			phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
++
++	} else if(IS_HARDWARE_TYPE_JAGUAR(Adapter)) {
++		u32 offset = 0xb4c;
++
++		if(IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
++			phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
++		else if(IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
++			phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
++		else if(IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
++			phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
++	}
++
++	phy_set_bb_reg(Adapter, 0xb00, BIT8, 1);		/*	Turn on PMAC*/
++	/* phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);				 */ /* TX Stop */
++	if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
++		phy_set_bb_reg(Adapter, 0xb04, 0xf, 8);		/*TX CCK ON*/
++		phy_set_bb_reg(Adapter, 0xA84, BIT31, 0);
++	} else
++		phy_set_bb_reg(Adapter, 0xb04, 0xf, 4);		/*	TX Ofdm ON	*/
++
++	if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)
++		mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);
++
++	return status;
++}
++
++#endif
++
++void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
++{
++	u8 Rate;
++
++	RTW_INFO("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx);
++	Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
++	pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart;
++
++	if (Rate <= MPT_RATE_11M) {
++		if (bStart)
++			mpt_StartCckContTx(pAdapter);
++		else
++			mpt_StopCckContTx(pAdapter);
++
++	} else if (Rate >= MPT_RATE_6M) {
++		if (bStart)
++			mpt_StartOfdmContTx(pAdapter);
++		else
++			mpt_StopOfdmContTx(pAdapter);
++	}
++}
++
++void mpt_trigger_tssi_tracking(PADAPTER pAdapter, u8 rf_path)
++{
++#ifdef CONFIG_RTL8814B
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
++
++	halrf_do_tssi_8814b(pDM_Odm, rf_path);
++#endif
++}
++
++#endif /* CONFIG_MP_INCLUDE*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_phy.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_phy.c
+new file mode 100644
+index 000000000..cf5cb3b54
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/hal_phy.c
+@@ -0,0 +1,257 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _HAL_PHY_C_
++
++#include <drv_types.h>
++
++/**
++* Function:	PHY_CalculateBitShift
++*
++* OverView:	Get shifted position of the BitMask
++*
++* Input:
++*			u32		BitMask,
++*
++* Output:	none
++* Return:		u32		Return the shift bit bit position of the mask
++*/
++u32
++PHY_CalculateBitShift(
++	u32 BitMask
++)
++{
++	u32 i;
++
++	for (i = 0; i <= 31; i++) {
++		if (((BitMask >> i) &  0x1) == 1)
++			break;
++	}
++
++	return i;
++}
++
++
++#ifdef CONFIG_RF_SHADOW_RW
++/* ********************************************************************************
++ *	Constant.
++ * ********************************************************************************
++ * 2008/11/20 MH For Debug only, RF */
++static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
++
++/*
++ * ==> RF shadow Operation API Code Section!!!
++ *
++ *-----------------------------------------------------------------------------
++ * Function:	PHY_RFShadowRead
++ *				PHY_RFShadowWrite
++ *				PHY_RFShadowCompare
++ *				PHY_RFShadowRecorver
++ *				PHY_RFShadowCompareAll
++ *				PHY_RFShadowRecorverAll
++ *				PHY_RFShadowCompareFlagSet
++ *				PHY_RFShadowRecorverFlagSet
++ *
++ * Overview:	When we set RF register, we must write shadow at first.
++ *			When we are running, we must compare shadow abd locate error addr.
++ *			Decide to recorver or not.
++ *
++ * Input:       NONE
++ *
++ * Output:      NONE
++ *
++ * Return:      NONE
++ *
++ * Revised History:
++ * When			Who		Remark
++ * 11/20/2008	MHC		Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++u32
++PHY_RFShadowRead(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				Offset)
++{
++	return	RF_Shadow[eRFPath][Offset].Value;
++
++}	/* PHY_RFShadowRead */
++
++
++void
++PHY_RFShadowWrite(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				Offset,
++		u32				Data)
++{
++	RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask);
++	RF_Shadow[eRFPath][Offset].Driver_Write = _TRUE;
++
++}	/* PHY_RFShadowWrite */
++
++
++BOOLEAN
++PHY_RFShadowCompare(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				Offset)
++{
++	u32	reg;
++	/* Check if we need to check the register */
++	if (RF_Shadow[eRFPath][Offset].Compare == _TRUE) {
++		reg = rtw_hal_read_rfreg(Adapter, eRFPath, Offset, bRFRegOffsetMask);
++		/* Compare shadow and real rf register for 20bits!! */
++		if (RF_Shadow[eRFPath][Offset].Value != reg) {
++			/* Locate error position. */
++			RF_Shadow[eRFPath][Offset].ErrorOrNot = _TRUE;
++		}
++		return RF_Shadow[eRFPath][Offset].ErrorOrNot ;
++	}
++	return _FALSE;
++}	/* PHY_RFShadowCompare */
++
++
++void
++PHY_RFShadowRecorver(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				Offset)
++{
++	/* Check if the address is error */
++	if (RF_Shadow[eRFPath][Offset].ErrorOrNot == _TRUE) {
++		/* Check if we need to recorver the register. */
++		if (RF_Shadow[eRFPath][Offset].Recorver == _TRUE) {
++			rtw_hal_write_rfreg(Adapter, eRFPath, Offset, bRFRegOffsetMask,
++					    RF_Shadow[eRFPath][Offset].Value);
++		}
++	}
++
++}	/* PHY_RFShadowRecorver */
++
++
++void
++PHY_RFShadowCompareAll(
++		PADAPTER			Adapter)
++{
++	enum rf_path	eRFPath = RF_PATH_A;
++	u32		Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
++
++	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
++		for (Offset = 0; Offset < maxReg; Offset++)
++			PHY_RFShadowCompare(Adapter, eRFPath, Offset);
++	}
++
++}	/* PHY_RFShadowCompareAll */
++
++
++void
++PHY_RFShadowRecorverAll(
++		PADAPTER			Adapter)
++{
++	enum rf_path		eRFPath = RF_PATH_A;
++	u32		Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
++
++	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
++		for (Offset = 0; Offset < maxReg; Offset++)
++			PHY_RFShadowRecorver(Adapter, eRFPath, Offset);
++	}
++
++}	/* PHY_RFShadowRecorverAll */
++
++
++void
++PHY_RFShadowCompareFlagSet(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				Offset,
++		u8				Type)
++{
++	/* Set True or False!!! */
++	RF_Shadow[eRFPath][Offset].Compare = Type;
++
++}	/* PHY_RFShadowCompareFlagSet */
++
++
++void
++PHY_RFShadowRecorverFlagSet(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				Offset,
++		u8				Type)
++{
++	/* Set True or False!!! */
++	RF_Shadow[eRFPath][Offset].Recorver = Type;
++
++}	/* PHY_RFShadowRecorverFlagSet */
++
++
++void
++PHY_RFShadowCompareFlagSetAll(
++		PADAPTER			Adapter)
++{
++	enum rf_path	eRFPath = RF_PATH_A;
++	u32		Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
++
++	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
++		for (Offset = 0; Offset < maxReg; Offset++) {
++			/* 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! */
++			if (Offset != 0x26 && Offset != 0x27)
++				PHY_RFShadowCompareFlagSet(Adapter, eRFPath, Offset, _FALSE);
++			else
++				PHY_RFShadowCompareFlagSet(Adapter, eRFPath, Offset, _TRUE);
++		}
++	}
++
++}	/* PHY_RFShadowCompareFlagSetAll */
++
++
++void
++PHY_RFShadowRecorverFlagSetAll(
++		PADAPTER			Adapter)
++{
++	enum rf_path		eRFPath = RF_PATH_A;
++	u32		Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
++
++	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
++		for (Offset = 0; Offset < maxReg; Offset++) {
++			/* 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! */
++			if (Offset != 0x26 && Offset != 0x27)
++				PHY_RFShadowRecorverFlagSet(Adapter, eRFPath, Offset, _FALSE);
++			else
++				PHY_RFShadowRecorverFlagSet(Adapter, eRFPath, Offset, _TRUE);
++		}
++	}
++
++}	/* PHY_RFShadowCompareFlagSetAll */
++
++void
++PHY_RFShadowRefresh(
++		PADAPTER			Adapter)
++{
++	enum rf_path		eRFPath = RF_PATH_A;
++	u32		Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
++
++	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
++		for (Offset = 0; Offset < maxReg; Offset++) {
++			RF_Shadow[eRFPath][Offset].Value = 0;
++			RF_Shadow[eRFPath][Offset].Compare = _FALSE;
++			RF_Shadow[eRFPath][Offset].Recorver  = _FALSE;
++			RF_Shadow[eRFPath][Offset].ErrorOrNot = _FALSE;
++			RF_Shadow[eRFPath][Offset].Driver_Write = _FALSE;
++		}
++	}
++
++}	/* PHY_RFShadowRead */
++#endif /*CONFIG_RF_SHADOW_RW*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/led/hal_led.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/led/hal_led.c
+new file mode 100644
+index 000000000..95d3daa24
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/led/hal_led.c
+@@ -0,0 +1,254 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++#ifdef CONFIG_RTW_LED
++void dump_led_config(void *sel, _adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct led_priv	*ledpriv = adapter_to_led(adapter);
++	int i;
++
++	RTW_PRINT_SEL(sel, "strategy:%u\n", ledpriv->LedStrategy);
++#ifdef CONFIG_RTW_SW_LED
++	RTW_PRINT_SEL(sel, "bRegUseLed:%u\n", ledpriv->bRegUseLed);
++	RTW_PRINT_SEL(sel, "iface_en_mask:0x%02X\n", ledpriv->iface_en_mask);
++	for (i = 0; i < dvobj->iface_nums; i++)
++		RTW_PRINT_SEL(sel, "ctl_en_mask[%d]:0x%08X\n", i, ledpriv->ctl_en_mask[i]);
++#endif
++}
++
++void rtw_led_set_strategy(_adapter *adapter, u8 strategy)
++{
++	struct led_priv *ledpriv = adapter_to_led(adapter);
++	_adapter *pri_adapter = GET_PRIMARY_ADAPTER(adapter);
++
++#ifndef CONFIG_RTW_SW_LED
++	if (IS_SW_LED_STRATEGY(strategy)) {
++		RTW_WARN("CONFIG_RTW_SW_LED is not defined\n");
++		return;
++	}
++#endif
++
++#ifdef CONFIG_RTW_SW_LED
++	if (!ledpriv->bRegUseLed)
++		return;
++#endif
++
++	if (ledpriv->LedStrategy == strategy)
++		return;
++
++	if (IS_HW_LED_STRATEGY(strategy) || IS_HW_LED_STRATEGY(ledpriv->LedStrategy)) {
++		RTW_WARN("switching on/off HW_LED strategy is not supported\n");
++		return;
++	}
++
++	ledpriv->LedStrategy = strategy;
++
++#ifdef CONFIG_RTW_SW_LED
++	rtw_hal_sw_led_deinit(pri_adapter);
++#endif
++
++	rtw_led_control(pri_adapter, RTW_LED_OFF);
++}
++
++#ifdef CONFIG_RTW_SW_LED
++#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
++void rtw_sw_led_blink_uc_trx_only(LED_DATA *led)
++{
++	_adapter *adapter = led->padapter;
++	BOOLEAN bStopBlinking = _FALSE;
++
++	if (led->BlinkingLedState == RTW_LED_ON)
++		SwLedOn(adapter, led);
++	else
++		SwLedOff(adapter, led);
++
++	switch (led->CurrLedState) {
++	case RTW_LED_ON:
++		SwLedOn(adapter, led);
++		break;
++
++	case RTW_LED_OFF:
++		SwLedOff(adapter, led);
++		break;
++
++	case LED_BLINK_TXRX:
++		led->BlinkTimes--;
++		if (led->BlinkTimes == 0)
++			bStopBlinking = _TRUE;
++
++		if (adapter_to_pwrctl(adapter)->rf_pwrstate != rf_on
++			&& adapter_to_pwrctl(adapter)->rfoff_reason > RF_CHANGE_BY_PS
++		) {
++			SwLedOff(adapter, led);
++			led->bLedBlinkInProgress = _FALSE;
++		} else {
++			if (led->bLedOn)
++				led->BlinkingLedState = RTW_LED_OFF;
++			else
++				led->BlinkingLedState = RTW_LED_ON;
++			
++			if (bStopBlinking) {
++				led->CurrLedState = RTW_LED_OFF;
++				led->bLedBlinkInProgress = _FALSE;
++			}
++			_set_timer(&(led->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++		}
++		break;
++
++	default:
++		break;
++	}
++}
++
++void rtw_sw_led_ctl_mode_uc_trx_only(_adapter *adapter, LED_CTL_MODE ctl)
++{
++	struct led_priv	*ledpriv = adapter_to_led(adapter);
++	LED_DATA *led = &(ledpriv->SwLed0);
++	LED_DATA *led1 = &(ledpriv->SwLed1);
++	LED_DATA *led2 = &(ledpriv->SwLed2);
++
++	switch (ctl) {
++	case LED_CTL_UC_TX:
++	case LED_CTL_UC_RX:
++		if (led->bLedBlinkInProgress == _FALSE) {
++			led->bLedBlinkInProgress = _TRUE;
++			led->CurrLedState = LED_BLINK_TXRX;
++			led->BlinkTimes = 2;
++			if (led->bLedOn)
++				led->BlinkingLedState = RTW_LED_OFF;
++			else
++				led->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(led->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++		}
++		break;
++
++	case LED_CTL_POWER_OFF:
++		led->CurrLedState = RTW_LED_OFF;
++		led->BlinkingLedState = RTW_LED_OFF;
++
++		if (led->bLedBlinkInProgress) {
++			_cancel_timer_ex(&(led->BlinkTimer));
++			led->bLedBlinkInProgress = _FALSE;
++		}
++
++		SwLedOff(adapter, led);
++		SwLedOff(adapter, led1);
++		SwLedOff(adapter, led2);
++		break;
++
++	default:
++		break;
++	}
++}
++#endif /* CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY */
++
++void rtw_led_control(_adapter *adapter, LED_CTL_MODE ctl)
++{
++	struct led_priv	*ledpriv = adapter_to_led(adapter);
++
++	if (ledpriv->LedControlHandler) {
++		#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
++		if (ledpriv->LedStrategy != SW_LED_MODE_UC_TRX_ONLY) {
++			if (ctl == LED_CTL_UC_TX || ctl == LED_CTL_BMC_TX) {
++				if (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(LED_CTL_TX))
++					ctl = LED_CTL_TX; /* transform specific TX ctl to general TX ctl */
++			} else if (ctl == LED_CTL_UC_RX || ctl == LED_CTL_BMC_RX) {
++				if (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(LED_CTL_RX))
++					ctl = LED_CTL_RX; /* transform specific RX ctl to general RX ctl */
++			}
++		}
++		#endif
++
++		if ((ledpriv->iface_en_mask & BIT(adapter->iface_id))
++			&& (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(ctl)))
++			ledpriv->LedControlHandler(adapter, ctl);
++	}
++}
++
++void rtw_led_tx_control(_adapter *adapter, const u8 *da)
++{
++#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
++	if (IS_MCAST(da))
++		rtw_led_control(adapter, LED_CTL_BMC_TX);
++	else
++		rtw_led_control(adapter, LED_CTL_UC_TX);
++#else
++	rtw_led_control(adapter, LED_CTL_TX);
++#endif
++}
++
++void rtw_led_rx_control(_adapter *adapter, const u8 *da)
++{
++#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
++	if (IS_MCAST(da))
++		rtw_led_control(adapter, LED_CTL_BMC_RX);
++	else
++		rtw_led_control(adapter, LED_CTL_UC_RX);
++#else
++	rtw_led_control(adapter, LED_CTL_RX);
++#endif
++}
++
++void rtw_led_set_iface_en(_adapter *adapter, u8 en)
++{
++	struct led_priv *ledpriv = adapter_to_led(adapter);
++
++	if (en)
++		ledpriv->iface_en_mask |= BIT(adapter->iface_id);
++	else
++		ledpriv->iface_en_mask &= ~BIT(adapter->iface_id);
++}
++
++void rtw_led_set_iface_en_mask(_adapter *adapter, u8 mask)
++{
++	struct led_priv *ledpriv = adapter_to_led(adapter);
++
++	ledpriv->iface_en_mask = mask;
++}
++
++void rtw_led_set_ctl_en_mask(_adapter *adapter, u32 ctl_mask)
++{
++	struct led_priv *ledpriv = adapter_to_led(adapter);
++	
++#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
++	if (ctl_mask & BIT(LED_CTL_TX))
++		ctl_mask |= BIT(LED_CTL_UC_TX) | BIT(LED_CTL_BMC_TX);
++	if (ctl_mask & BIT(LED_CTL_RX))
++		ctl_mask |= BIT(LED_CTL_UC_RX) | BIT(LED_CTL_BMC_RX);
++#endif
++
++	ledpriv->ctl_en_mask[adapter->iface_id] = ctl_mask;
++}
++
++void rtw_led_set_ctl_en_mask_primary(_adapter *adapter)
++{
++	rtw_led_set_ctl_en_mask(adapter, 0xFFFFFFFF);
++}
++
++void rtw_led_set_ctl_en_mask_virtual(_adapter *adapter)
++{
++	rtw_led_set_ctl_en_mask(adapter
++		, BIT(LED_CTL_POWER_ON) | BIT(LED_CTL_POWER_OFF)
++		| BIT(LED_CTL_TX) | BIT(LED_CTL_RX)
++	);
++}
++#endif /* CONFIG_RTW_SW_LED */
++
++#endif /* CONFIG_RTW_LED */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/led/hal_sdio_led.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/led/hal_sdio_led.c
+new file mode 100644
+index 000000000..506d17d7b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/led/hal_sdio_led.c
+@@ -0,0 +1,2014 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <drv_types.h>
++#include <hal_data.h>
++#ifdef CONFIG_RTW_SW_LED
++
++/*
++ *	Description:
++ *		Implementation of LED blinking behavior.
++ *		It toggle off LED and schedule corresponding timer if necessary.
++ *   */
++void
++SwLedBlink(
++	PLED_SDIO			pLed
++)
++{
++	_adapter			*padapter = pLed->padapter;
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	u8				bStopBlinking = _FALSE;
++
++	/* Change LED according to BlinkingLedState specified. */
++	if (pLed->BlinkingLedState == RTW_LED_ON) {
++		SwLedOn(padapter, pLed);
++	} else {
++		SwLedOff(padapter, pLed);
++	}
++
++	/* Determine if we shall change LED state again. */
++	pLed->BlinkTimes--;
++	switch (pLed->CurrLedState) {
++
++	case LED_BLINK_NORMAL:
++		if (pLed->BlinkTimes == 0)
++			bStopBlinking = _TRUE;
++		break;
++
++	case LED_BLINK_StartToBlink:
++		if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) && check_fwstate(pmlmepriv, WIFI_STATION_STATE))
++			bStopBlinking = _TRUE;
++		if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) &&
++		    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)))
++			bStopBlinking = _TRUE;
++		else if (pLed->BlinkTimes == 0)
++			bStopBlinking = _TRUE;
++		break;
++
++	case LED_BLINK_WPS:
++		if (pLed->BlinkTimes == 0)
++			bStopBlinking = _TRUE;
++		break;
++
++
++	default:
++		bStopBlinking = _TRUE;
++		break;
++
++	}
++
++	if (bStopBlinking) {
++		if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
++			SwLedOff(padapter, pLed);
++		else if ((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) && (pLed->bLedOn == _FALSE))
++			SwLedOn(padapter, pLed);
++		else if ((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) &&  pLed->bLedOn == _TRUE)
++			SwLedOff(padapter, pLed);
++
++		pLed->BlinkTimes = 0;
++		pLed->bLedBlinkInProgress = _FALSE;
++	} else {
++		/* Assign LED state to toggle. */
++		if (pLed->BlinkingLedState == RTW_LED_ON)
++			pLed->BlinkingLedState = RTW_LED_OFF;
++		else
++			pLed->BlinkingLedState = RTW_LED_ON;
++
++		/* Schedule a timer to toggle LED state. */
++		switch (pLed->CurrLedState) {
++		case LED_BLINK_NORMAL:
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++			break;
++
++		case LED_BLINK_SLOWLY:
++		case LED_BLINK_StartToBlink:
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
++			break;
++
++		case LED_BLINK_WPS:
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL);
++		        break;
++
++		default:
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
++			break;
++		}
++	}
++}
++
++void
++SwLedBlink1(
++	PLED_SDIO			pLed
++)
++{
++	_adapter				*padapter = pLed->padapter;
++	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(padapter);
++	struct led_priv		*ledpriv = adapter_to_led(padapter);
++	struct mlme_priv		*pmlmepriv = &(padapter->mlmepriv);
++	PLED_SDIO			pLed1 = &(ledpriv->SwLed1);
++	u8					bStopBlinking = _FALSE;
++
++	if (pHalData->CustomerID == RT_CID_819x_CAMEO)
++		pLed = &(ledpriv->SwLed1);
++
++	/* Change LED according to BlinkingLedState specified. */
++	if (pLed->BlinkingLedState == RTW_LED_ON) {
++		SwLedOn(padapter, pLed);
++	} else {
++		SwLedOff(padapter, pLed);
++	}
++
++
++	if (pHalData->CustomerID == RT_CID_DEFAULT) {
++		if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++			if (!pLed1->bSWLedCtrl) {
++				SwLedOn(padapter, pLed1);
++				pLed1->bSWLedCtrl = _TRUE;
++			} else if (!pLed1->bLedOn)
++				SwLedOn(padapter, pLed1);
++		} else {
++			if (!pLed1->bSWLedCtrl) {
++				SwLedOff(padapter, pLed1);
++				pLed1->bSWLedCtrl = _TRUE;
++			} else if (pLed1->bLedOn)
++				SwLedOff(padapter, pLed1);
++		}
++	}
++
++	switch (pLed->CurrLedState) {
++	case LED_BLINK_SLOWLY:
++		if (pLed->bLedOn)
++			pLed->BlinkingLedState = RTW_LED_OFF;
++		else
++			pLed->BlinkingLedState = RTW_LED_ON;
++		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++		break;
++
++	case LED_BLINK_NORMAL:
++		if (pLed->bLedOn)
++			pLed->BlinkingLedState = RTW_LED_OFF;
++		else
++			pLed->BlinkingLedState = RTW_LED_ON;
++		_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
++		break;
++
++	case LED_BLINK_SCAN:
++		pLed->BlinkTimes--;
++		if (pLed->BlinkTimes == 0)
++			bStopBlinking = _TRUE;
++
++		if (bStopBlinking) {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
++				SwLedOff(padapter, pLed);
++			else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++				pLed->bLedLinkBlinkInProgress = _TRUE;
++				pLed->CurrLedState = LED_BLINK_NORMAL;
++				if (pLed->bLedOn)
++					pLed->BlinkingLedState = RTW_LED_OFF;
++				else
++					pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
++
++			} else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) {
++				pLed->bLedNoLinkBlinkInProgress = _TRUE;
++				pLed->CurrLedState = LED_BLINK_SLOWLY;
++				if (pLed->bLedOn)
++					pLed->BlinkingLedState = RTW_LED_OFF;
++				else
++					pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++			}
++			pLed->bLedScanBlinkInProgress = _FALSE;
++		} else {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
++				SwLedOff(padapter, pLed);
++			else {
++				if (pLed->bLedOn)
++					pLed->BlinkingLedState = RTW_LED_OFF;
++				else
++					pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++			}
++		}
++		break;
++
++	case LED_BLINK_TXRX:
++		pLed->BlinkTimes--;
++		if (pLed->BlinkTimes == 0)
++			bStopBlinking = _TRUE;
++		if (bStopBlinking) {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
++				SwLedOff(padapter, pLed);
++			else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++				pLed->bLedLinkBlinkInProgress = _TRUE;
++				pLed->CurrLedState = LED_BLINK_NORMAL;
++				if (pLed->bLedOn)
++					pLed->BlinkingLedState = RTW_LED_OFF;
++				else
++					pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
++			} else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) {
++				pLed->bLedNoLinkBlinkInProgress = _TRUE;
++				pLed->CurrLedState = LED_BLINK_SLOWLY;
++				if (pLed->bLedOn)
++					pLed->BlinkingLedState = RTW_LED_OFF;
++				else
++					pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++			}
++			pLed->BlinkTimes = 0;
++			pLed->bLedBlinkInProgress = _FALSE;
++		} else {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
++				SwLedOff(padapter, pLed);
++			else {
++				if (pLed->bLedOn)
++					pLed->BlinkingLedState = RTW_LED_OFF;
++				else
++					pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++			}
++		}
++		break;
++
++	case LED_BLINK_WPS:
++		if (pLed->bLedOn)
++			pLed->BlinkingLedState = RTW_LED_OFF;
++		else
++			pLed->BlinkingLedState = RTW_LED_ON;
++		_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++		break;
++
++	case LED_BLINK_WPS_STOP:	/* WPS success */
++		if (pLed->BlinkingLedState == RTW_LED_ON) {
++			pLed->BlinkingLedState = RTW_LED_OFF;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA);
++			bStopBlinking = _FALSE;
++		} else
++			bStopBlinking = _TRUE;
++
++		if (bStopBlinking) {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
++				SwLedOff(padapter, pLed);
++			else {
++				pLed->bLedLinkBlinkInProgress = _TRUE;
++				pLed->CurrLedState = LED_BLINK_NORMAL;
++				if (pLed->bLedOn)
++					pLed->BlinkingLedState = RTW_LED_OFF;
++				else
++					pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
++			}
++			pLed->bLedWPSBlinkInProgress = _FALSE;
++		}
++		break;
++
++	default:
++		break;
++	}
++
++}
++
++void
++SwLedBlink2(
++	PLED_SDIO			pLed
++)
++{
++	_adapter				*padapter = pLed->padapter;
++	struct mlme_priv		*pmlmepriv = &(padapter->mlmepriv);
++	u8					bStopBlinking = _FALSE;
++
++	/* Change LED according to BlinkingLedState specified. */
++	if (pLed->BlinkingLedState == RTW_LED_ON) {
++		SwLedOn(padapter, pLed);
++	} else {
++		SwLedOff(padapter, pLed);
++	}
++
++	switch (pLed->CurrLedState) {
++	case LED_BLINK_SCAN:
++		pLed->BlinkTimes--;
++		if (pLed->BlinkTimes == 0)
++			bStopBlinking = _TRUE;
++
++		if (bStopBlinking) {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
++				SwLedOff(padapter, pLed);
++			else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++				pLed->CurrLedState = RTW_LED_ON;
++				pLed->BlinkingLedState = RTW_LED_ON;
++				SwLedOn(padapter, pLed);
++
++			} else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) {
++				pLed->CurrLedState = RTW_LED_OFF;
++				pLed->BlinkingLedState = RTW_LED_OFF;
++				SwLedOff(padapter, pLed);
++			}
++			pLed->bLedScanBlinkInProgress = _FALSE;
++		} else {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
++				SwLedOff(padapter, pLed);
++			else {
++				if (pLed->bLedOn)
++					pLed->BlinkingLedState = RTW_LED_OFF;
++				else
++					pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++			}
++		}
++		break;
++
++	case LED_BLINK_TXRX:
++		pLed->BlinkTimes--;
++		if (pLed->BlinkTimes == 0)
++			bStopBlinking = _TRUE;
++		if (bStopBlinking) {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
++				SwLedOff(padapter, pLed);
++			else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++				pLed->CurrLedState = RTW_LED_ON;
++				pLed->BlinkingLedState = RTW_LED_ON;
++				SwLedOn(padapter, pLed);
++
++			} else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) {
++				pLed->CurrLedState = RTW_LED_OFF;
++				pLed->BlinkingLedState = RTW_LED_OFF;
++				SwLedOff(padapter, pLed);
++			}
++			pLed->bLedBlinkInProgress = _FALSE;
++		} else {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
++				SwLedOff(padapter, pLed);
++			else {
++				if (pLed->bLedOn)
++					pLed->BlinkingLedState = RTW_LED_OFF;
++				else
++					pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++			}
++		}
++		break;
++
++	default:
++		break;
++	}
++
++}
++
++void
++SwLedBlink3(
++	PLED_SDIO			pLed
++)
++{
++	_adapter			*padapter = pLed->padapter;
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	u8				bStopBlinking = _FALSE;
++
++	/* Change LED according to BlinkingLedState specified. */
++	if (pLed->BlinkingLedState == RTW_LED_ON) {
++		SwLedOn(padapter, pLed);
++	} else {
++		if (pLed->CurrLedState != LED_BLINK_WPS_STOP)
++			SwLedOff(padapter, pLed);
++	}
++
++	switch (pLed->CurrLedState) {
++	case LED_BLINK_SCAN:
++		pLed->BlinkTimes--;
++		if (pLed->BlinkTimes == 0)
++			bStopBlinking = _TRUE;
++
++		if (bStopBlinking) {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
++				SwLedOff(padapter, pLed);
++			else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++				pLed->CurrLedState = RTW_LED_ON;
++				pLed->BlinkingLedState = RTW_LED_ON;
++				if (!pLed->bLedOn)
++					SwLedOn(padapter, pLed);
++
++			} else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) {
++				pLed->CurrLedState = RTW_LED_OFF;
++				pLed->BlinkingLedState = RTW_LED_OFF;
++				if (pLed->bLedOn)
++					SwLedOff(padapter, pLed);
++
++			}
++			pLed->bLedScanBlinkInProgress = _FALSE;
++		} else {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
++				SwLedOff(padapter, pLed);
++			else {
++				if (pLed->bLedOn)
++					pLed->BlinkingLedState = RTW_LED_OFF;
++				else
++					pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++			}
++		}
++		break;
++
++	case LED_BLINK_TXRX:
++		pLed->BlinkTimes--;
++		if (pLed->BlinkTimes == 0)
++			bStopBlinking = _TRUE;
++		if (bStopBlinking) {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
++				SwLedOff(padapter, pLed);
++			else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++				pLed->CurrLedState = RTW_LED_ON;
++				pLed->BlinkingLedState = RTW_LED_ON;
++
++				if (!pLed->bLedOn)
++					SwLedOn(padapter, pLed);
++
++			} else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) {
++				pLed->CurrLedState = RTW_LED_OFF;
++				pLed->BlinkingLedState = RTW_LED_OFF;
++
++				if (pLed->bLedOn)
++					SwLedOff(padapter, pLed);
++
++
++			}
++			pLed->bLedBlinkInProgress = _FALSE;
++		} else {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
++				SwLedOff(padapter, pLed);
++			else {
++				if (pLed->bLedOn)
++					pLed->BlinkingLedState = RTW_LED_OFF;
++				else
++					pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++			}
++		}
++		break;
++
++	case LED_BLINK_WPS:
++		if (pLed->bLedOn)
++			pLed->BlinkingLedState = RTW_LED_OFF;
++		else
++			pLed->BlinkingLedState = RTW_LED_ON;
++		_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++		break;
++
++	case LED_BLINK_WPS_STOP:	/* WPS success */
++		if (pLed->BlinkingLedState == RTW_LED_ON) {
++			pLed->BlinkingLedState = RTW_LED_OFF;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA);
++			bStopBlinking = _FALSE;
++		} else
++			bStopBlinking = _TRUE;
++
++		if (bStopBlinking) {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
++				SwLedOff(padapter, pLed);
++			else {
++				pLed->CurrLedState = RTW_LED_ON;
++				pLed->BlinkingLedState = RTW_LED_ON;
++				SwLedOn(padapter, pLed);
++			}
++			pLed->bLedWPSBlinkInProgress = _FALSE;
++		}
++		break;
++
++
++	default:
++		break;
++	}
++
++}
++
++
++void
++SwLedBlink4(
++	PLED_SDIO			pLed
++)
++{
++	_adapter			*padapter = pLed->padapter;
++	struct led_priv	*ledpriv = adapter_to_led(padapter);
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	PLED_SDIO		pLed1 = &(ledpriv->SwLed1);
++	u8				bStopBlinking = _FALSE;
++
++	/* Change LED according to BlinkingLedState specified. */
++	if (pLed->BlinkingLedState == RTW_LED_ON) {
++		SwLedOn(padapter, pLed);
++	} else {
++		SwLedOff(padapter, pLed);
++	}
++
++	if (!pLed1->bLedWPSBlinkInProgress && pLed1->BlinkingLedState == LED_UNKNOWN) {
++		pLed1->BlinkingLedState = RTW_LED_OFF;
++		pLed1->CurrLedState = RTW_LED_OFF;
++		SwLedOff(padapter, pLed1);
++	}
++
++	switch (pLed->CurrLedState) {
++	case LED_BLINK_SLOWLY:
++		if (pLed->bLedOn)
++			pLed->BlinkingLedState = RTW_LED_OFF;
++		else
++			pLed->BlinkingLedState = RTW_LED_ON;
++		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++		break;
++
++	case LED_BLINK_StartToBlink:
++		if (pLed->bLedOn) {
++			pLed->BlinkingLedState = RTW_LED_OFF;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
++		} else {
++			pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++		}
++		break;
++
++	case LED_BLINK_SCAN:
++		pLed->BlinkTimes--;
++		if (pLed->BlinkTimes == 0)
++			bStopBlinking = _FALSE;
++
++		if (bStopBlinking) {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS)
++				SwLedOff(padapter, pLed);
++			else {
++				pLed->bLedNoLinkBlinkInProgress = _FALSE;
++				pLed->CurrLedState = LED_BLINK_SLOWLY;
++				if (pLed->bLedOn)
++					pLed->BlinkingLedState = RTW_LED_OFF;
++				else
++					pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++			}
++			pLed->bLedScanBlinkInProgress = _FALSE;
++		} else {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS)
++				SwLedOff(padapter, pLed);
++			else {
++				if (pLed->bLedOn)
++					pLed->BlinkingLedState = RTW_LED_OFF;
++				else
++					pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++			}
++		}
++		break;
++
++	case LED_BLINK_TXRX:
++		pLed->BlinkTimes--;
++		if (pLed->BlinkTimes == 0)
++			bStopBlinking = _TRUE;
++		if (bStopBlinking) {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS)
++				SwLedOff(padapter, pLed);
++			else {
++				pLed->bLedNoLinkBlinkInProgress = _TRUE;
++				pLed->CurrLedState = LED_BLINK_SLOWLY;
++				if (pLed->bLedOn)
++					pLed->BlinkingLedState = RTW_LED_OFF;
++				else
++					pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++			}
++			pLed->bLedBlinkInProgress = _FALSE;
++		} else {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS)
++				SwLedOff(padapter, pLed);
++			else {
++				if (pLed->bLedOn)
++					pLed->BlinkingLedState = RTW_LED_OFF;
++				else
++					pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++			}
++		}
++		break;
++
++	case LED_BLINK_WPS:
++		if (pLed->bLedOn) {
++			pLed->BlinkingLedState = RTW_LED_OFF;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
++		} else {
++			pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++		}
++		break;
++
++	case LED_BLINK_WPS_STOP:	/* WPS authentication fail */
++		if (pLed->bLedOn)
++			pLed->BlinkingLedState = RTW_LED_OFF;
++		else
++			pLed->BlinkingLedState = RTW_LED_ON;
++
++		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++		break;
++
++	case LED_BLINK_WPS_STOP_OVERLAP:	/* WPS session overlap */
++		pLed->BlinkTimes--;
++		if (pLed->BlinkTimes == 0) {
++			if (pLed->bLedOn)
++				pLed->BlinkTimes = 1;
++			else
++				bStopBlinking = _TRUE;
++		}
++
++		if (bStopBlinking) {
++			pLed->BlinkTimes = 10;
++			pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
++		} else {
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++		}
++		break;
++
++	default:
++		break;
++	}
++
++
++
++}
++
++void
++SwLedBlink5(
++	PLED_SDIO			pLed
++)
++{
++	_adapter			*padapter = pLed->padapter;
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	u8				bStopBlinking = _FALSE;
++
++	/* Change LED according to BlinkingLedState specified. */
++	if (pLed->BlinkingLedState == RTW_LED_ON) {
++		SwLedOn(padapter, pLed);
++	} else {
++		SwLedOff(padapter, pLed);
++	}
++
++	switch (pLed->CurrLedState) {
++	case LED_BLINK_SCAN:
++		pLed->BlinkTimes--;
++		if (pLed->BlinkTimes == 0)
++			bStopBlinking = _TRUE;
++
++		if (bStopBlinking) {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) {
++				pLed->CurrLedState = RTW_LED_OFF;
++				pLed->BlinkingLedState = RTW_LED_OFF;
++				if (pLed->bLedOn)
++					SwLedOff(padapter, pLed);
++			} else {
++				pLed->CurrLedState = RTW_LED_ON;
++				pLed->BlinkingLedState = RTW_LED_ON;
++				if (!pLed->bLedOn)
++					_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++			}
++
++			pLed->bLedScanBlinkInProgress = _FALSE;
++		} else {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS)
++				SwLedOff(padapter, pLed);
++			else {
++				if (pLed->bLedOn)
++					pLed->BlinkingLedState = RTW_LED_OFF;
++				else
++					pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++			}
++		}
++		break;
++
++
++	case LED_BLINK_TXRX:
++		pLed->BlinkTimes--;
++		if (pLed->BlinkTimes == 0)
++			bStopBlinking = _TRUE;
++
++		if (bStopBlinking) {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) {
++				pLed->CurrLedState = RTW_LED_OFF;
++				pLed->BlinkingLedState = RTW_LED_OFF;
++				if (pLed->bLedOn)
++					SwLedOff(padapter, pLed);
++			} else {
++				pLed->CurrLedState = RTW_LED_ON;
++				pLed->BlinkingLedState = RTW_LED_ON;
++				if (!pLed->bLedOn)
++					_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++			}
++
++			pLed->bLedBlinkInProgress = _FALSE;
++		} else {
++			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS)
++				SwLedOff(padapter, pLed);
++			else {
++				if (pLed->bLedOn)
++					pLed->BlinkingLedState = RTW_LED_OFF;
++				else
++					pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++			}
++		}
++		break;
++
++	default:
++		break;
++	}
++
++
++
++}
++
++void
++SwLedBlink6(
++	PLED_SDIO			pLed
++)
++{
++	_adapter			*padapter = pLed->padapter;
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	u8				bStopBlinking = _FALSE;
++
++	/* Change LED according to BlinkingLedState specified. */
++	if (pLed->BlinkingLedState == RTW_LED_ON) {
++		SwLedOn(padapter, pLed);
++	} else {
++		SwLedOff(padapter, pLed);
++	}
++
++}
++
++/*
++ *	Description:
++ *		Handler function of LED Blinking.
++ *		We dispatch acture LED blink action according to LedStrategy.
++ *   */
++void BlinkHandler(PLED_SDIO	pLed)
++{
++	_adapter		*padapter = pLed->padapter;
++	struct led_priv	*ledpriv = adapter_to_led(padapter);
++
++	/* RTW_INFO("%s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); */
++	if (RTW_CANNOT_RUN(padapter) || (!rtw_is_hw_init_completed(padapter))) {
++		RTW_INFO("%s bDriverStopped:%s, bSurpriseRemoved:%s\n"
++			 , __func__
++			 , rtw_is_drv_stopped(padapter) ? "True" : "False"
++			, rtw_is_surprise_removed(padapter) ? "True" : "False");
++
++		return;
++	}
++
++	switch (ledpriv->LedStrategy) {
++	#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
++	case SW_LED_MODE_UC_TRX_ONLY:
++		rtw_sw_led_blink_uc_trx_only(pLed);
++		break;
++	#endif
++
++	case SW_LED_MODE0:
++		SwLedBlink(pLed);
++		break;
++
++	case SW_LED_MODE1:
++		SwLedBlink1(pLed);
++		break;
++
++	case SW_LED_MODE2:
++		SwLedBlink2(pLed);
++		break;
++
++	case SW_LED_MODE3:
++		SwLedBlink3(pLed);
++		break;
++
++	case SW_LED_MODE4:
++		SwLedBlink4(pLed);
++		break;
++
++	case SW_LED_MODE5:
++		SwLedBlink5(pLed);
++		break;
++
++	case SW_LED_MODE6:
++		SwLedBlink6(pLed);
++		break;
++
++	default:
++		/* SwLedBlink(pLed); */
++		break;
++	}
++}
++
++/*
++ *	Description:
++ *		Callback function of LED BlinkTimer,
++ *		it just schedules to corresponding BlinkWorkItem/led_blink_hdl
++ *   */
++void BlinkTimerCallback(void *data)
++{
++	PLED_SDIO	 pLed = (PLED_SDIO)data;
++	_adapter		*padapter = pLed->padapter;
++
++	/* RTW_INFO("%s\n", __FUNCTION__); */
++
++	if (RTW_CANNOT_RUN(padapter) || (!rtw_is_hw_init_completed(padapter))) {
++		/*RTW_INFO("%s bDriverStopped:%s, bSurpriseRemoved:%s\n"
++			, __func__
++			, rtw_is_drv_stopped(padapter)?"True":"False"
++			, rtw_is_surprise_removed(padapter)?"True":"False" );*/
++		return;
++	}
++
++#ifdef CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD
++	rtw_led_blink_cmd(padapter, pLed);
++#else
++	_set_workitem(&(pLed->BlinkWorkItem));
++#endif
++}
++
++/*
++ *	Description:
++ *		Callback function of LED BlinkWorkItem.
++ *		We dispatch acture LED blink action according to LedStrategy.
++ *   */
++void BlinkWorkItemCallback(_workitem *work)
++{
++	PLED_SDIO	 pLed = container_of(work, LED_SDIO, BlinkWorkItem);
++	BlinkHandler(pLed);
++}
++
++static void
++SwLedControlMode0(
++	_adapter		*padapter,
++	LED_CTL_MODE		LedAction
++)
++{
++	struct led_priv	*ledpriv = adapter_to_led(padapter);
++	PLED_SDIO	pLed = &(ledpriv->SwLed1);
++
++	/* Decide led state */
++	switch (LedAction) {
++	case LED_CTL_TX:
++	case LED_CTL_RX:
++		if (pLed->bLedBlinkInProgress == _FALSE) {
++			pLed->bLedBlinkInProgress = _TRUE;
++
++			pLed->CurrLedState = LED_BLINK_NORMAL;
++			pLed->BlinkTimes = 2;
++
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++		}
++		break;
++
++	case LED_CTL_START_TO_LINK:
++		if (pLed->bLedBlinkInProgress == _FALSE) {
++			pLed->bLedBlinkInProgress = _TRUE;
++
++			pLed->CurrLedState = LED_BLINK_StartToBlink;
++			pLed->BlinkTimes = 24;
++
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
++		} else
++			pLed->CurrLedState = LED_BLINK_StartToBlink;
++		break;
++
++	case LED_CTL_LINK:
++		pLed->CurrLedState = RTW_LED_ON;
++		if (pLed->bLedBlinkInProgress == _FALSE) {
++			pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), 0);
++		}
++		break;
++
++	case LED_CTL_NO_LINK:
++		pLed->CurrLedState = RTW_LED_OFF;
++		if (pLed->bLedBlinkInProgress == _FALSE) {
++			pLed->BlinkingLedState = RTW_LED_OFF;
++			_set_timer(&(pLed->BlinkTimer), 0);
++		}
++		break;
++
++	case LED_CTL_POWER_OFF:
++		pLed->CurrLedState = RTW_LED_OFF;
++		if (pLed->bLedBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedBlinkInProgress = _FALSE;
++		}
++		SwLedOff(padapter, pLed);
++		break;
++
++	case LED_CTL_START_WPS:
++		if (pLed->bLedBlinkInProgress == _FALSE || pLed->CurrLedState == RTW_LED_ON) {
++			pLed->bLedBlinkInProgress = _TRUE;
++
++			pLed->CurrLedState = LED_BLINK_WPS;
++			pLed->BlinkTimes = 20;
++
++			if (pLed->bLedOn) {
++				pLed->BlinkingLedState = RTW_LED_OFF;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL);
++			} else {
++				pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL);
++			}
++		}
++		break;
++
++	case LED_CTL_STOP_WPS:
++		if (pLed->bLedBlinkInProgress) {
++			pLed->CurrLedState = RTW_LED_OFF;
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedBlinkInProgress = _FALSE;
++		}
++		break;
++
++
++	default:
++		break;
++	}
++
++
++}
++
++/* ALPHA, added by chiyoko, 20090106 */
++static void
++SwLedControlMode1(
++	_adapter		*padapter,
++	LED_CTL_MODE		LedAction
++)
++{
++	struct led_priv		*ledpriv = adapter_to_led(padapter);
++	PLED_SDIO			pLed = &(ledpriv->SwLed0);
++	struct mlme_priv		*pmlmepriv = &(padapter->mlmepriv);
++	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(padapter);
++
++	if (pHalData->CustomerID == RT_CID_819x_CAMEO)
++		pLed = &(ledpriv->SwLed1);
++
++	switch (LedAction) {
++	case LED_CTL_POWER_ON:
++	case LED_CTL_START_TO_LINK:
++	case LED_CTL_NO_LINK:
++		if (pLed->bLedNoLinkBlinkInProgress == _FALSE) {
++			if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
++				return;
++			if (pLed->bLedLinkBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedLinkBlinkInProgress = _FALSE;
++			}
++			if (pLed->bLedBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedBlinkInProgress = _FALSE;
++			}
++
++			pLed->bLedNoLinkBlinkInProgress = _TRUE;
++			pLed->CurrLedState = LED_BLINK_SLOWLY;
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++		}
++		break;
++
++	case LED_CTL_LINK:
++		if (pLed->bLedLinkBlinkInProgress == _FALSE) {
++			if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
++				return;
++			if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedNoLinkBlinkInProgress = _FALSE;
++			}
++			if (pLed->bLedBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedBlinkInProgress = _FALSE;
++			}
++			pLed->bLedLinkBlinkInProgress = _TRUE;
++			pLed->CurrLedState = LED_BLINK_NORMAL;
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
++		}
++		break;
++
++	case LED_CTL_SITE_SURVEY:
++		if ((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE))
++			;
++		else if (pLed->bLedScanBlinkInProgress == _FALSE) {
++			if (IS_LED_WPS_BLINKING(pLed))
++				return;
++
++			if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedNoLinkBlinkInProgress = _FALSE;
++			}
++			if (pLed->bLedLinkBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedLinkBlinkInProgress = _FALSE;
++			}
++			if (pLed->bLedBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedBlinkInProgress = _FALSE;
++			}
++			pLed->bLedScanBlinkInProgress = _TRUE;
++			pLed->CurrLedState = LED_BLINK_SCAN;
++			pLed->BlinkTimes = 24;
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++
++		}
++		break;
++
++	case LED_CTL_TX:
++	case LED_CTL_RX:
++		if (pLed->bLedBlinkInProgress == _FALSE) {
++			if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
++				return;
++			if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedNoLinkBlinkInProgress = _FALSE;
++			}
++			if (pLed->bLedLinkBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedLinkBlinkInProgress = _FALSE;
++			}
++			pLed->bLedBlinkInProgress = _TRUE;
++			pLed->CurrLedState = LED_BLINK_TXRX;
++			pLed->BlinkTimes = 2;
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++		}
++		break;
++
++	case LED_CTL_START_WPS: /* wait until xinpin finish */
++	case LED_CTL_START_WPS_BOTTON:
++		if (pLed->bLedWPSBlinkInProgress == _FALSE) {
++			if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedNoLinkBlinkInProgress = _FALSE;
++			}
++			if (pLed->bLedLinkBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedLinkBlinkInProgress = _FALSE;
++			}
++			if (pLed->bLedBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedBlinkInProgress = _FALSE;
++			}
++			if (pLed->bLedScanBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedScanBlinkInProgress = _FALSE;
++			}
++			pLed->bLedWPSBlinkInProgress = _TRUE;
++			pLed->CurrLedState = LED_BLINK_WPS;
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++		}
++		break;
++
++
++	case LED_CTL_STOP_WPS:
++		if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedNoLinkBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedLinkBlinkInProgress == _TRUE) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedLinkBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedBlinkInProgress == _TRUE) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedScanBlinkInProgress == _TRUE) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedScanBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedWPSBlinkInProgress)
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++		else
++			pLed->bLedWPSBlinkInProgress = _TRUE;
++
++		pLed->CurrLedState = LED_BLINK_WPS_STOP;
++		if (pLed->bLedOn) {
++			pLed->BlinkingLedState = RTW_LED_OFF;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA);
++		} else {
++			pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), 0);
++		}
++		break;
++
++	case LED_CTL_STOP_WPS_FAIL:
++		if (pLed->bLedWPSBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedWPSBlinkInProgress = _FALSE;
++		}
++
++		pLed->bLedNoLinkBlinkInProgress = _TRUE;
++		pLed->CurrLedState = LED_BLINK_SLOWLY;
++		if (pLed->bLedOn)
++			pLed->BlinkingLedState = RTW_LED_OFF;
++		else
++			pLed->BlinkingLedState = RTW_LED_ON;
++		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++		break;
++
++	case LED_CTL_POWER_OFF:
++		pLed->CurrLedState = RTW_LED_OFF;
++		pLed->BlinkingLedState = RTW_LED_OFF;
++		if (pLed->bLedNoLinkBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedNoLinkBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedLinkBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedLinkBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedWPSBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedWPSBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedScanBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedScanBlinkInProgress = _FALSE;
++		}
++
++		SwLedOff(padapter, pLed);
++		break;
++
++	default:
++		break;
++
++	}
++
++}
++
++/* Arcadyan/Sitecom , added by chiyoko, 20090216 */
++static void
++SwLedControlMode2(
++	_adapter				*padapter,
++	LED_CTL_MODE		LedAction
++)
++{
++	struct led_priv	*ledpriv = adapter_to_led(padapter);
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	PLED_SDIO		pLed = &(ledpriv->SwLed0);
++
++	switch (LedAction) {
++	case LED_CTL_SITE_SURVEY:
++		if (pmlmepriv->LinkDetectInfo.bBusyTraffic)
++			;
++		else if (pLed->bLedScanBlinkInProgress == _FALSE) {
++			if (IS_LED_WPS_BLINKING(pLed))
++				return;
++
++			if (pLed->bLedBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedBlinkInProgress = _FALSE;
++			}
++			pLed->bLedScanBlinkInProgress = _TRUE;
++			pLed->CurrLedState = LED_BLINK_SCAN;
++			pLed->BlinkTimes = 24;
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++		}
++		break;
++
++	case LED_CTL_TX:
++	case LED_CTL_RX:
++		if ((pLed->bLedBlinkInProgress == _FALSE) && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) {
++			if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
++				return;
++
++			pLed->bLedBlinkInProgress = _TRUE;
++			pLed->CurrLedState = LED_BLINK_TXRX;
++			pLed->BlinkTimes = 2;
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++		}
++		break;
++
++	case LED_CTL_LINK:
++		pLed->CurrLedState = RTW_LED_ON;
++		pLed->BlinkingLedState = RTW_LED_ON;
++		if (pLed->bLedBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedScanBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedScanBlinkInProgress = _FALSE;
++		}
++
++		_set_timer(&(pLed->BlinkTimer), 0);
++		break;
++
++	case LED_CTL_START_WPS: /* wait until xinpin finish */
++	case LED_CTL_START_WPS_BOTTON:
++		if (pLed->bLedWPSBlinkInProgress == _FALSE) {
++			if (pLed->bLedBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedBlinkInProgress = _FALSE;
++			}
++			if (pLed->bLedScanBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedScanBlinkInProgress = _FALSE;
++			}
++			pLed->bLedWPSBlinkInProgress = _TRUE;
++			pLed->CurrLedState = RTW_LED_ON;
++			pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), 0);
++		}
++		break;
++
++	case LED_CTL_STOP_WPS:
++		pLed->bLedWPSBlinkInProgress = _FALSE;
++		if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on) {
++			pLed->CurrLedState = RTW_LED_OFF;
++			pLed->BlinkingLedState = RTW_LED_OFF;
++			_set_timer(&(pLed->BlinkTimer), 0);
++		} else {
++			pLed->CurrLedState = RTW_LED_ON;
++			pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), 0);
++		}
++		break;
++
++	case LED_CTL_STOP_WPS_FAIL:
++		pLed->bLedWPSBlinkInProgress = _FALSE;
++		pLed->CurrLedState = RTW_LED_OFF;
++		pLed->BlinkingLedState = RTW_LED_OFF;
++		_set_timer(&(pLed->BlinkTimer), 0);
++		break;
++
++	case LED_CTL_START_TO_LINK:
++	case LED_CTL_NO_LINK:
++		if (!IS_LED_BLINKING(pLed)) {
++			pLed->CurrLedState = RTW_LED_OFF;
++			pLed->BlinkingLedState = RTW_LED_OFF;
++			_set_timer(&(pLed->BlinkTimer), 0);
++		}
++		break;
++
++	case LED_CTL_POWER_OFF:
++		pLed->CurrLedState = RTW_LED_OFF;
++		pLed->BlinkingLedState = RTW_LED_OFF;
++		if (pLed->bLedBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedScanBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedScanBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedWPSBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedWPSBlinkInProgress = _FALSE;
++		}
++
++		SwLedOff(padapter, pLed);
++		break;
++
++	default:
++		break;
++
++	}
++
++}
++
++/* COREGA, added by chiyoko, 20090316 */
++static void
++SwLedControlMode3(
++	_adapter				*padapter,
++	LED_CTL_MODE		LedAction
++)
++{
++	struct led_priv	*ledpriv = adapter_to_led(padapter);
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	PLED_SDIO		pLed = &(ledpriv->SwLed0);
++
++	switch (LedAction) {
++	case LED_CTL_SITE_SURVEY:
++		if (pmlmepriv->LinkDetectInfo.bBusyTraffic)
++			;
++		else if (pLed->bLedScanBlinkInProgress == _FALSE) {
++			if (IS_LED_WPS_BLINKING(pLed))
++				return;
++
++			if (pLed->bLedBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedBlinkInProgress = _FALSE;
++			}
++			pLed->bLedScanBlinkInProgress = _TRUE;
++			pLed->CurrLedState = LED_BLINK_SCAN;
++			pLed->BlinkTimes = 24;
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++		}
++		break;
++
++	case LED_CTL_TX:
++	case LED_CTL_RX:
++		if ((pLed->bLedBlinkInProgress == _FALSE) && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) {
++			if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
++				return;
++
++			pLed->bLedBlinkInProgress = _TRUE;
++			pLed->CurrLedState = LED_BLINK_TXRX;
++			pLed->BlinkTimes = 2;
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++		}
++		break;
++
++	case LED_CTL_LINK:
++		if (IS_LED_WPS_BLINKING(pLed))
++			return;
++
++		pLed->CurrLedState = RTW_LED_ON;
++		pLed->BlinkingLedState = RTW_LED_ON;
++		if (pLed->bLedBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedScanBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedScanBlinkInProgress = _FALSE;
++		}
++
++		_set_timer(&(pLed->BlinkTimer), 0);
++		break;
++
++	case LED_CTL_START_WPS: /* wait until xinpin finish */
++	case LED_CTL_START_WPS_BOTTON:
++		if (pLed->bLedWPSBlinkInProgress == _FALSE) {
++			if (pLed->bLedBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedBlinkInProgress = _FALSE;
++			}
++			if (pLed->bLedScanBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedScanBlinkInProgress = _FALSE;
++			}
++			pLed->bLedWPSBlinkInProgress = _TRUE;
++			pLed->CurrLedState = LED_BLINK_WPS;
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++		}
++		break;
++
++	case LED_CTL_STOP_WPS:
++		if (pLed->bLedWPSBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedWPSBlinkInProgress = _FALSE;
++		} else
++			pLed->bLedWPSBlinkInProgress = _TRUE;
++
++		pLed->CurrLedState = LED_BLINK_WPS_STOP;
++		if (pLed->bLedOn) {
++			pLed->BlinkingLedState = RTW_LED_OFF;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA);
++		} else {
++			pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), 0);
++		}
++
++		break;
++
++	case LED_CTL_STOP_WPS_FAIL:
++		if (pLed->bLedWPSBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedWPSBlinkInProgress = _FALSE;
++		}
++
++		pLed->CurrLedState = RTW_LED_OFF;
++		pLed->BlinkingLedState = RTW_LED_OFF;
++		_set_timer(&(pLed->BlinkTimer), 0);
++		break;
++
++	case LED_CTL_START_TO_LINK:
++	case LED_CTL_NO_LINK:
++		if (!IS_LED_BLINKING(pLed)) {
++			pLed->CurrLedState = RTW_LED_OFF;
++			pLed->BlinkingLedState = RTW_LED_OFF;
++			_set_timer(&(pLed->BlinkTimer), 0);
++		}
++		break;
++
++	case LED_CTL_POWER_OFF:
++		pLed->CurrLedState = RTW_LED_OFF;
++		pLed->BlinkingLedState = RTW_LED_OFF;
++		if (pLed->bLedBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedScanBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedScanBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedWPSBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedWPSBlinkInProgress = _FALSE;
++		}
++
++		SwLedOff(padapter, pLed);
++		break;
++
++	default:
++		break;
++
++	}
++
++}
++
++
++/* Edimax-Belkin, added by chiyoko, 20090413 */
++static void
++SwLedControlMode4(
++	_adapter				*padapter,
++	LED_CTL_MODE		LedAction
++)
++{
++	struct led_priv	*ledpriv = adapter_to_led(padapter);
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	PLED_SDIO		pLed = &(ledpriv->SwLed0);
++	PLED_SDIO		pLed1 = &(ledpriv->SwLed1);
++
++	switch (LedAction) {
++	case LED_CTL_START_TO_LINK:
++		if (pLed1->bLedWPSBlinkInProgress) {
++			pLed1->bLedWPSBlinkInProgress = _FALSE;
++			_cancel_timer_ex(&(pLed1->BlinkTimer));
++
++			pLed1->BlinkingLedState = RTW_LED_OFF;
++			pLed1->CurrLedState = RTW_LED_OFF;
++
++			if (pLed1->bLedOn)
++				_set_timer(&(pLed->BlinkTimer), 0);
++		}
++
++		if (pLed->bLedStartToLinkBlinkInProgress == _FALSE) {
++			if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
++				return;
++			if (pLed->bLedBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedBlinkInProgress = _FALSE;
++			}
++			if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedNoLinkBlinkInProgress = _FALSE;
++			}
++
++			pLed->bLedStartToLinkBlinkInProgress = _TRUE;
++			pLed->CurrLedState = LED_BLINK_StartToBlink;
++			if (pLed->bLedOn) {
++				pLed->BlinkingLedState = RTW_LED_OFF;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
++			} else {
++				pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++			}
++		}
++		break;
++
++	case LED_CTL_LINK:
++	case LED_CTL_NO_LINK:
++		/* LED1 settings */
++		if (LedAction == LED_CTL_LINK) {
++			if (pLed1->bLedWPSBlinkInProgress) {
++				pLed1->bLedWPSBlinkInProgress = _FALSE;
++				_cancel_timer_ex(&(pLed1->BlinkTimer));
++
++				pLed1->BlinkingLedState = RTW_LED_OFF;
++				pLed1->CurrLedState = RTW_LED_OFF;
++
++				if (pLed1->bLedOn)
++					_set_timer(&(pLed->BlinkTimer), 0);
++			}
++		}
++
++		if (pLed->bLedNoLinkBlinkInProgress == _FALSE) {
++			if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
++				return;
++			if (pLed->bLedBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedBlinkInProgress = _FALSE;
++			}
++
++			pLed->bLedNoLinkBlinkInProgress = _TRUE;
++			pLed->CurrLedState = LED_BLINK_SLOWLY;
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++		}
++		break;
++
++	case LED_CTL_SITE_SURVEY:
++		if ((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE))
++			;
++		else if (pLed->bLedScanBlinkInProgress == _FALSE) {
++			if (IS_LED_WPS_BLINKING(pLed))
++				return;
++
++			if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedNoLinkBlinkInProgress = _FALSE;
++			}
++			if (pLed->bLedBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedBlinkInProgress = _FALSE;
++			}
++			pLed->bLedScanBlinkInProgress = _TRUE;
++			pLed->CurrLedState = LED_BLINK_SCAN;
++			pLed->BlinkTimes = 24;
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++		}
++		break;
++
++	case LED_CTL_TX:
++	case LED_CTL_RX:
++		if (pLed->bLedBlinkInProgress == _FALSE) {
++			if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
++				return;
++			if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedNoLinkBlinkInProgress = _FALSE;
++			}
++			pLed->bLedBlinkInProgress = _TRUE;
++			pLed->CurrLedState = LED_BLINK_TXRX;
++			pLed->BlinkTimes = 2;
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++		}
++		break;
++
++	case LED_CTL_START_WPS: /* wait until xinpin finish */
++	case LED_CTL_START_WPS_BOTTON:
++		if (pLed1->bLedWPSBlinkInProgress) {
++			pLed1->bLedWPSBlinkInProgress = _FALSE;
++			_cancel_timer_ex(&(pLed1->BlinkTimer));
++
++			pLed1->BlinkingLedState = RTW_LED_OFF;
++			pLed1->CurrLedState = RTW_LED_OFF;
++
++			if (pLed1->bLedOn)
++				_set_timer(&(pLed->BlinkTimer), 0);
++		}
++
++		if (pLed->bLedWPSBlinkInProgress == _FALSE) {
++			if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedNoLinkBlinkInProgress = _FALSE;
++			}
++			if (pLed->bLedBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedBlinkInProgress = _FALSE;
++			}
++			if (pLed->bLedScanBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedScanBlinkInProgress = _FALSE;
++			}
++			pLed->bLedWPSBlinkInProgress = _TRUE;
++			pLed->CurrLedState = LED_BLINK_WPS;
++			if (pLed->bLedOn) {
++				pLed->BlinkingLedState = RTW_LED_OFF;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
++			} else {
++				pLed->BlinkingLedState = RTW_LED_ON;
++				_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++			}
++		}
++		break;
++
++	case LED_CTL_STOP_WPS:	/* WPS connect success */
++		if (pLed->bLedWPSBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedWPSBlinkInProgress = _FALSE;
++		}
++
++		pLed->bLedNoLinkBlinkInProgress = _TRUE;
++		pLed->CurrLedState = LED_BLINK_SLOWLY;
++		if (pLed->bLedOn)
++			pLed->BlinkingLedState = RTW_LED_OFF;
++		else
++			pLed->BlinkingLedState = RTW_LED_ON;
++		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++
++		break;
++
++	case LED_CTL_STOP_WPS_FAIL:		/* WPS authentication fail */
++		if (pLed->bLedWPSBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedWPSBlinkInProgress = _FALSE;
++		}
++
++		pLed->bLedNoLinkBlinkInProgress = _TRUE;
++		pLed->CurrLedState = LED_BLINK_SLOWLY;
++		if (pLed->bLedOn)
++			pLed->BlinkingLedState = RTW_LED_OFF;
++		else
++			pLed->BlinkingLedState = RTW_LED_ON;
++		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++
++		/* LED1 settings */
++		if (pLed1->bLedWPSBlinkInProgress)
++			_cancel_timer_ex(&(pLed1->BlinkTimer));
++		else
++			pLed1->bLedWPSBlinkInProgress = _TRUE;
++
++		pLed1->CurrLedState = LED_BLINK_WPS_STOP;
++		if (pLed1->bLedOn)
++			pLed1->BlinkingLedState = RTW_LED_OFF;
++		else
++			pLed1->BlinkingLedState = RTW_LED_ON;
++		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++
++		break;
++
++	case LED_CTL_STOP_WPS_FAIL_OVERLAP:	/* WPS session overlap */
++		if (pLed->bLedWPSBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedWPSBlinkInProgress = _FALSE;
++		}
++
++		pLed->bLedNoLinkBlinkInProgress = _TRUE;
++		pLed->CurrLedState = LED_BLINK_SLOWLY;
++		if (pLed->bLedOn)
++			pLed->BlinkingLedState = RTW_LED_OFF;
++		else
++			pLed->BlinkingLedState = RTW_LED_ON;
++		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
++
++		/* LED1 settings */
++		if (pLed1->bLedWPSBlinkInProgress)
++			_cancel_timer_ex(&(pLed1->BlinkTimer));
++		else
++			pLed1->bLedWPSBlinkInProgress = _TRUE;
++
++		pLed1->CurrLedState = LED_BLINK_WPS_STOP_OVERLAP;
++		pLed1->BlinkTimes = 10;
++		if (pLed1->bLedOn)
++			pLed1->BlinkingLedState = RTW_LED_OFF;
++		else
++			pLed1->BlinkingLedState = RTW_LED_ON;
++		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
++
++		break;
++
++	case LED_CTL_POWER_OFF:
++		pLed->CurrLedState = RTW_LED_OFF;
++		pLed->BlinkingLedState = RTW_LED_OFF;
++
++		if (pLed->bLedNoLinkBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedNoLinkBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedLinkBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedLinkBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedWPSBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedWPSBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedScanBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedScanBlinkInProgress = _FALSE;
++		}
++		if (pLed->bLedStartToLinkBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedStartToLinkBlinkInProgress = _FALSE;
++		}
++
++		if (pLed1->bLedWPSBlinkInProgress) {
++			_cancel_timer_ex(&(pLed1->BlinkTimer));
++			pLed1->bLedWPSBlinkInProgress = _FALSE;
++		}
++
++		pLed1->BlinkingLedState = LED_UNKNOWN;
++		SwLedOff(padapter, pLed);
++		SwLedOff(padapter, pLed1);
++		break;
++
++	default:
++		break;
++
++	}
++
++}
++
++
++
++/* Sercomm-Belkin, added by chiyoko, 20090415 */
++static void
++SwLedControlMode5(
++	_adapter				*padapter,
++	LED_CTL_MODE		LedAction
++)
++{
++	struct led_priv	*ledpriv = adapter_to_led(padapter);
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++	PLED_SDIO		pLed = &(ledpriv->SwLed0);
++
++	if (pHalData->CustomerID == RT_CID_819x_CAMEO)
++		pLed = &(ledpriv->SwLed1);
++
++	switch (LedAction) {
++	case LED_CTL_POWER_ON:
++	case LED_CTL_NO_LINK:
++	case LED_CTL_LINK:	/* solid blue */
++		pLed->CurrLedState = RTW_LED_ON;
++		pLed->BlinkingLedState = RTW_LED_ON;
++
++		_set_timer(&(pLed->BlinkTimer), 0);
++		break;
++
++	case LED_CTL_SITE_SURVEY:
++		if ((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE))
++			;
++		else if (pLed->bLedScanBlinkInProgress == _FALSE) {
++			if (pLed->bLedBlinkInProgress == _TRUE) {
++				_cancel_timer_ex(&(pLed->BlinkTimer));
++				pLed->bLedBlinkInProgress = _FALSE;
++			}
++			pLed->bLedScanBlinkInProgress = _TRUE;
++			pLed->CurrLedState = LED_BLINK_SCAN;
++			pLed->BlinkTimes = 24;
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
++		}
++		break;
++
++	case LED_CTL_TX:
++	case LED_CTL_RX:
++		if (pLed->bLedBlinkInProgress == _FALSE) {
++			if (pLed->CurrLedState == LED_BLINK_SCAN)
++				return;
++			pLed->bLedBlinkInProgress = _TRUE;
++			pLed->CurrLedState = LED_BLINK_TXRX;
++			pLed->BlinkTimes = 2;
++			if (pLed->bLedOn)
++				pLed->BlinkingLedState = RTW_LED_OFF;
++			else
++				pLed->BlinkingLedState = RTW_LED_ON;
++			_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
++		}
++		break;
++
++	case LED_CTL_POWER_OFF:
++		pLed->CurrLedState = RTW_LED_OFF;
++		pLed->BlinkingLedState = RTW_LED_OFF;
++
++		if (pLed->bLedBlinkInProgress) {
++			_cancel_timer_ex(&(pLed->BlinkTimer));
++			pLed->bLedBlinkInProgress = _FALSE;
++		}
++
++		SwLedOff(padapter, pLed);
++		break;
++
++	default:
++		break;
++
++	}
++
++}
++
++/* WNC-Corega, added by chiyoko, 20090902 */
++static void
++SwLedControlMode6(
++	_adapter				*padapter,
++	LED_CTL_MODE		LedAction
++)
++{
++	struct led_priv	*ledpriv = adapter_to_led(padapter);
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	PLED_SDIO pLed0 = &(ledpriv->SwLed0);
++
++	switch (LedAction) {
++	case LED_CTL_POWER_ON:
++	case LED_CTL_LINK:
++	case LED_CTL_NO_LINK:
++		_cancel_timer_ex(&(pLed0->BlinkTimer));
++		pLed0->CurrLedState = RTW_LED_ON;
++		pLed0->BlinkingLedState = RTW_LED_ON;
++		_set_timer(&(pLed0->BlinkTimer), 0);
++		break;
++
++	case LED_CTL_POWER_OFF:
++		SwLedOff(padapter, pLed0);
++		break;
++
++	default:
++		break;
++	}
++
++}
++
++void
++LedControlSDIO(
++	_adapter				*padapter,
++	LED_CTL_MODE		LedAction
++)
++{
++	struct led_priv	*ledpriv = adapter_to_led(padapter);
++
++#if (MP_DRIVER == 1)
++	if (padapter->registrypriv.mp_mode == 1)
++		return;
++#endif
++
++	if (RTW_CANNOT_RUN(padapter) || (!rtw_is_hw_init_completed(padapter))) {
++		/*RTW_INFO("%s bDriverStopped:%s, bSurpriseRemoved:%s\n"
++		, __func__
++		, rtw_is_drv_stopped(padapter)?"True":"False"
++		, rtw_is_surprise_removed(padapter)?"True":"False");*/
++		return;
++	}
++
++	if (ledpriv->bRegUseLed == _FALSE)
++		return;
++
++	/* if(priv->bInHctTest) */
++	/*	return; */
++
++	if ((adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on &&
++	     adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) &&
++	    (LedAction == LED_CTL_TX || LedAction == LED_CTL_RX ||
++	     LedAction == LED_CTL_SITE_SURVEY ||
++	     LedAction == LED_CTL_LINK ||
++	     LedAction == LED_CTL_NO_LINK ||
++	     LedAction == LED_CTL_POWER_ON))
++		return;
++
++	switch (ledpriv->LedStrategy) {
++	#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
++	case SW_LED_MODE_UC_TRX_ONLY:
++		rtw_sw_led_ctl_mode_uc_trx_only(padapter, LedAction);
++		break;
++	#endif
++
++	case SW_LED_MODE0:
++		SwLedControlMode0(padapter, LedAction);
++		break;
++
++	case SW_LED_MODE1:
++		SwLedControlMode1(padapter, LedAction);
++		break;
++	case SW_LED_MODE2:
++		SwLedControlMode2(padapter, LedAction);
++		break;
++
++	case SW_LED_MODE3:
++		SwLedControlMode3(padapter, LedAction);
++		break;
++
++	case SW_LED_MODE4:
++		SwLedControlMode4(padapter, LedAction);
++		break;
++
++	case SW_LED_MODE5:
++		SwLedControlMode5(padapter, LedAction);
++		break;
++
++	case SW_LED_MODE6:
++		SwLedControlMode6(padapter, LedAction);
++		break;
++
++	default:
++		break;
++	}
++
++}
++
++/*
++ *	Description:
++ *		Reset status of LED_871x object.
++ *   */
++void ResetLedStatus(PLED_SDIO pLed)
++{
++
++	pLed->CurrLedState = RTW_LED_OFF; /* Current LED state. */
++	pLed->bLedOn = _FALSE; /* true if LED is ON, false if LED is OFF. */
++
++	pLed->bLedBlinkInProgress = _FALSE; /* true if it is blinking, false o.w.. */
++	pLed->bLedWPSBlinkInProgress = _FALSE;
++
++	pLed->BlinkTimes = 0; /* Number of times to toggle led state for blinking. */
++	pLed->BlinkingLedState = LED_UNKNOWN; /* Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are. */
++
++	pLed->bLedNoLinkBlinkInProgress = _FALSE;
++	pLed->bLedLinkBlinkInProgress = _FALSE;
++	pLed->bLedStartToLinkBlinkInProgress = _FALSE;
++	pLed->bLedScanBlinkInProgress = _FALSE;
++}
++
++/*
++*	Description:
++*		Initialize an LED_871x object.
++*   */
++void
++InitLed(
++	_adapter			*padapter,
++	PLED_SDIO		pLed,
++	LED_PIN			LedPin
++)
++{
++	pLed->padapter = padapter;
++	pLed->LedPin = LedPin;
++
++	ResetLedStatus(pLed);
++
++	rtw_init_timer(&(pLed->BlinkTimer), padapter, BlinkTimerCallback, pLed);
++
++	_init_workitem(&(pLed->BlinkWorkItem), BlinkWorkItemCallback, pLed);
++}
++
++
++/*
++ *	Description:
++ *		DeInitialize an LED_871x object.
++ *   */
++void
++DeInitLed(
++	PLED_SDIO		pLed
++)
++{
++	_cancel_workitem_sync(&(pLed->BlinkWorkItem));
++	_cancel_timer_ex(&(pLed->BlinkTimer));
++	ResetLedStatus(pLed);
++}
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/ap_makefile.mk b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/ap_makefile.mk
+new file mode 100644
+index 000000000..84cefef8e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/ap_makefile.mk
+@@ -0,0 +1,222 @@
++
++_PHYDM_FILES :=\
++	phydm/phydm.o \
++	phydm/phydm_dig.o\
++	phydm/phydm_antdiv.o\
++	phydm/phydm_soml.o\
++	phydm/phydm_smt_ant.o\
++	phydm/phydm_pathdiv.o\
++	phydm/phydm_rainfo.o\
++	phydm/phydm_dynamictxpower.o\
++	phydm/phydm_adaptivity.o\
++	phydm/phydm_debug.o\
++	phydm/phydm_interface.o\
++	phydm/phydm_phystatus.o\
++	phydm/phydm_hwconfig.o\
++	phydm/phydm_dfs.o\
++	phydm/phydm_cfotracking.o\
++	phydm/phydm_adc_sampling.o\
++	phydm/phydm_ccx.o\
++	phydm/phydm_primary_cca.o\
++	phydm/phydm_cck_pd.o\
++	phydm/phydm_rssi_monitor.o\
++	phydm/phydm_auto_dbg.o\
++	phydm/phydm_math_lib.o\
++	phydm/phydm_noisemonitor.o\
++	phydm/phydm_api.o\
++	phydm/phydm_pow_train.o\
++	phydm/phydm_lna_sat.o\
++	phydm/phydm_pmac_tx_setting.o\
++	phydm/phydm_mp.o\
++	phydm/phydm_cck_rx_pathdiv.o\
++	phydm/phydm_direct_bf.o\
++	phydm/txbf/phydm_hal_txbf_api.o\
++	EdcaTurboCheck.o\
++	phydm/halrf/halrf.o\
++	phydm/halrf/halrf_debug.o\
++	phydm/halrf/halphyrf_ap.o\
++	phydm/halrf/halrf_powertracking_ap.o\
++	phydm/halrf/halrf_powertracking.o\
++	phydm/halrf/halrf_kfree.o\
++	phydm/halrf/halrf_psd.o
++
++ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
++	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
++		_PHYDM_FILES += \
++		phydm/rtl8188e/halhwimg8188e_bb.o\
++		phydm/rtl8188e/halhwimg8188e_mac.o\
++		phydm/rtl8188e/halhwimg8188e_rf.o\
++		phydm/rtl8188e/phydm_regconfig8188e.o\
++		phydm/rtl8188e/hal8188erateadaptive.o\
++		phydm/rtl8188e/phydm_rtl8188e.o\
++		phydm/halrf/rtl8188e/halrf_8188e_ap.o
++	endif
++endif
++
++ifeq ($(CONFIG_RTL_8812_SUPPORT),y)
++	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
++		_PHYDM_FILES += ./phydm/halrf/rtl8812a/halrf_8812a_ap.o
++	endif
++	_PHYDM_FILES += phydm/rtl8812a/phydm_rtl8812a.o
++endif
++
++ifeq ($(CONFIG_WLAN_HAL_8881A),y)
++	_PHYDM_FILES += phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.o
++endif
++
++ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
++	_PHYDM_FILES += \
++	phydm/halrf/rtl8192e/halrf_8192e_ap.o\
++	phydm/rtl8192e/phydm_rtl8192e.o
++endif
++
++ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
++	rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_8814a_ap.o
++	rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_iqk_8814a.o
++	rtl8192cd-objs += phydm/halrf/rtl8814a/halhwimg8814a_rf.o
++	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
++		rtl8192cd-objs += \
++		phydm/rtl8814a/halhwimg8814a_bb.o\
++		phydm/rtl8814a/halhwimg8814a_mac.o\
++		phydm/rtl8814a/phydm_regconfig8814a.o\
++		phydm/rtl8814a/phydm_rtl8814a.o
++	endif
++endif
++
++ifeq ($(CONFIG_WLAN_HAL_8822BE),y)
++	_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_8822b.o
++	_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_iqk_8822b.o
++	_PHYDM_FILES += phydm/halrf/rtl8822b/halhwimg8822b_rf.o
++	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
++		_PHYDM_FILES += \
++		phydm/rtl8822b/halhwimg8822b_bb.o\
++		phydm/rtl8822b/halhwimg8822b_mac.o\
++		phydm/rtl8822b/phydm_regconfig8822b.o\
++		phydm/rtl8822b/phydm_hal_api8822b.o\
++		phydm/rtl8822b/phydm_rtl8822b.o
++	endif
++endif
++
++ifeq ($(CONFIG_WLAN_HAL_8822CE),y)
++	_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_8822c.o
++	_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_iqk_8822c.o
++	_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_dpk_8822c.o
++	_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_rfk_init_8822c.o
++	_PHYDM_FILES += phydm/halrf/rtl8822c/halhwimg8822c_rf.o
++	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
++		_PHYDM_FILES += \
++		phydm/rtl8822c/halhwimg8822c_bb.o\
++		phydm/rtl8822c/phydm_regconfig8822c.o\
++		phydm/rtl8822c/phydm_hal_api8822c.o
++	endif
++endif
++
++ifeq ($(CONFIG_WLAN_HAL_8812FE),y)
++	_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_8812f.o
++	_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_iqk_8812f.o
++	_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_dpk_8812f.o
++	_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_tssi_8812f.o
++	_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_rfk_init_8812f.o
++	_PHYDM_FILES += phydm/halrf/rtl8812f/halhwimg8812f_rf.o
++	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
++		_PHYDM_FILES += \
++		phydm/rtl8812f/halhwimg8812f_bb.o\
++		phydm/rtl8812f/phydm_regconfig8812f.o\
++		phydm/rtl8812f/phydm_hal_api8812f.o
++	endif
++endif
++
++ifeq ($(CONFIG_WLAN_HAL_8821CE),y)
++	_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_8821c.o
++	_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_iqk_8821c.o
++	_PHYDM_FILES += phydm/halrf/rtl8821c/halhwimg8821c_rf.o
++	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
++		_PHYDM_FILES += \
++		phydm/rtl8821c/halhwimg8821c_bb.o\
++		phydm/rtl8821c/halhwimg8821c_mac.o\
++		phydm/rtl8821c/phydm_regconfig8821c.o\
++		phydm/rtl8821c/phydm_hal_api8821c.o
++	endif
++endif
++
++ifeq ($(CONFIG_WLAN_HAL_8197F),y)
++		_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_8197f.o
++		_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_iqk_8197f.o
++		_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_dpk_8197f.o
++		_PHYDM_FILES += phydm/halrf/rtl8197f/halhwimg8197f_rf.o
++		_PHYDM_FILES += efuse_97f/efuse.o
++	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
++		_PHYDM_FILES += \
++		phydm/rtl8197f/halhwimg8197f_bb.o\
++		phydm/rtl8197f/halhwimg8197f_mac.o\
++		phydm/rtl8197f/phydm_hal_api8197f.o\
++		phydm/rtl8197f/phydm_regconfig8197f.o\
++		phydm/rtl8197f/phydm_rtl8197f.o
++	endif
++endif
++
++
++ifeq ($(CONFIG_WLAN_HAL_8192FE),y)
++		_PHYDM_FILES += phydm/halrf/rtl8192f/halrf_8192f.o
++		_PHYDM_FILES += phydm/halrf/rtl8192f/halrf_dpk_8192f.o
++		_PHYDM_FILES += phydm/halrf/rtl8192f/halhwimg8192f_rf.o
++	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
++		_PHYDM_FILES += \
++		phydm/rtl8192f/halhwimg8192f_bb.o\
++		phydm/rtl8192f/halhwimg8192f_mac.o\
++		phydm/rtl8192f/phydm_hal_api8192f.o\
++		phydm/rtl8192f/phydm_regconfig8192f.o\
++		phydm/rtl8192f/phydm_rtl8192f.o
++	endif
++endif
++
++ifeq ($(CONFIG_WLAN_HAL_8198F),y)
++		_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_8198f.o
++		_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_iqk_8198f.o
++		_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_dpk_8198f.o
++		_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_rfk_init_8198f.o
++		_PHYDM_FILES += phydm/halrf/rtl8198f/halhwimg8198f_rf.o
++	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
++		_PHYDM_FILES += \
++		phydm/rtl8198f/phydm_hal_api8198f.o\
++		phydm/rtl8198f/halhwimg8198f_bb.o\
++		phydm/rtl8198f/halhwimg8198f_mac.o\
++		phydm/rtl8198f/phydm_regconfig8198f.o \
++		phydm/halrf/rtl8198f/halrf_8198f.o
++	endif
++endif
++
++ifeq ($(CONFIG_WLAN_HAL_8814BE),y)
++		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_8814b.o
++		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_iqk_8814b.o
++		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_dpk_8814b.o
++		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_txgapk_8814b.o
++		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_rfk_init_8814b.o
++		_PHYDM_FILES += phydm/halrf/rtl8814b/halhwimg8814b_rf.o
++	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
++		_PHYDM_FILES += \
++		phydm/rtl8814b/phydm_hal_api8814b.o\
++		phydm/rtl8814b/halhwimg8814b_bb.o\
++		phydm/rtl8814b/phydm_regconfig8814b.o \
++		phydm/halrf/rtl8814b/halrf_8814b.o
++	endif
++endif
++
++ifeq ($(CONFIG_WLAN_HAL_8197G),y)
++		_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_8197g.o
++		_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_iqk_8197g.o
++		_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_dpk_8197g.o
++		_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_tssi_8197g.o
++		_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_rfk_init_8197g.o
++		_PHYDM_FILES += phydm/halrf/rtl8197g/halhwimg8197g_rf.o
++	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
++		_PHYDM_FILES += \
++		phydm/rtl8197g/phydm_hal_api8197g.o\
++		phydm/rtl8197g/halhwimg8197g_bb.o\
++		phydm/rtl8197g/halhwimg8197g_mac.o\
++		phydm/rtl8197g/phydm_regconfig8197g.o \
++		phydm/rtl8197g/phydm_rtl8197g.o \
++		phydm/halrf/rtl8197g/halrf_8197g.o
++	endif
++endif
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halhwimg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halhwimg.h
+new file mode 100644
+index 000000000..6d658b393
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halhwimg.h
+@@ -0,0 +1,137 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#pragma once
++#ifndef __INC_HW_IMG_H
++#define __INC_HW_IMG_H
++
++/*@
++ * 2011/03/15 MH Add for different IC HW image file selection. code size consideration.
++ *   */
++#if RT_PLATFORM == PLATFORM_LINUX
++
++	#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
++		/* @For 92C */
++		#define		RTL8192CE_HWIMG_SUPPORT					1
++		#define		RTL8192CE_TEST_HWIMG_SUPPORT			0
++		#define		RTL8192CU_HWIMG_SUPPORT					0
++		#define		RTL8192CU_TEST_HWIMG_SUPPORT			0
++
++		/* @For 92D */
++		#define		RTL8192DE_HWIMG_SUPPORT					1
++		#define		RTL8192DE_TEST_HWIMG_SUPPORT			0
++		#define		RTL8192DU_HWIMG_SUPPORT					0
++		#define		RTL8192DU_TEST_HWIMG_SUPPORT			0
++
++		/* @For 8723 */
++		#define		RTL8723E_HWIMG_SUPPORT					1
++		#define		RTL8723U_HWIMG_SUPPORT					0
++		#define		RTL8723S_HWIMG_SUPPORT					0
++
++		/* @For 88E */
++		#define		RTL8188EE_HWIMG_SUPPORT					0
++		#define		RTL8188EU_HWIMG_SUPPORT					0
++		#define		RTL8188ES_HWIMG_SUPPORT					0
++
++	#elif (DEV_BUS_TYPE == RT_USB_INTERFACE)
++		/* @For 92C */
++		#define	RTL8192CE_HWIMG_SUPPORT				0
++		#define	RTL8192CE_TEST_HWIMG_SUPPORT			0
++		#define	RTL8192CU_HWIMG_SUPPORT				1
++		#define	RTL8192CU_TEST_HWIMG_SUPPORT			0
++
++		/* @For 92D */
++		#define	RTL8192DE_HWIMG_SUPPORT				0
++		#define	RTL8192DE_TEST_HWIMG_SUPPORT			0
++		#define	RTL8192DU_HWIMG_SUPPORT				1
++		#define	RTL8192DU_TEST_HWIMG_SUPPORT			0
++
++		/* @For 8723 */
++		#define	RTL8723E_HWIMG_SUPPORT					0
++		#define	RTL8723U_HWIMG_SUPPORT					1
++		#define	RTL8723S_HWIMG_SUPPORT					0
++
++		/* @For 88E */
++		#define		RTL8188EE_HWIMG_SUPPORT					0
++		#define		RTL8188EU_HWIMG_SUPPORT					0
++		#define		RTL8188ES_HWIMG_SUPPORT					0
++
++	#elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
++		/* @For 92C */
++		#define	RTL8192CE_HWIMG_SUPPORT				0
++		#define	RTL8192CE_TEST_HWIMG_SUPPORT			0
++		#define	RTL8192CU_HWIMG_SUPPORT				1
++		#define	RTL8192CU_TEST_HWIMG_SUPPORT			0
++
++		/* @For 92D */
++		#define	RTL8192DE_HWIMG_SUPPORT				0
++		#define	RTL8192DE_TEST_HWIMG_SUPPORT			0
++		#define	RTL8192DU_HWIMG_SUPPORT				1
++		#define	RTL8192DU_TEST_HWIMG_SUPPORT			0
++
++		/* @For 8723 */
++		#define	RTL8723E_HWIMG_SUPPORT					0
++		#define	RTL8723U_HWIMG_SUPPORT					0
++		#define	RTL8723S_HWIMG_SUPPORT					1
++
++		/* @For 88E */
++		#define		RTL8188EE_HWIMG_SUPPORT					0
++		#define		RTL8188EU_HWIMG_SUPPORT					0
++		#define		RTL8188ES_HWIMG_SUPPORT					0
++	#endif
++
++#else	/* PLATFORM_WINDOWS & MacOSX */
++
++	/* @For 92C */
++	#define		RTL8192CE_HWIMG_SUPPORT						1
++	#define		RTL8192CE_TEST_HWIMG_SUPPORT				1
++	#define		RTL8192CU_HWIMG_SUPPORT						1
++	#define		RTL8192CU_TEST_HWIMG_SUPPORT				1
++
++	/* @For 92D */
++	#define		RTL8192DE_HWIMG_SUPPORT					1
++	#define		RTL8192DE_TEST_HWIMG_SUPPORT				1
++	#define		RTL8192DU_HWIMG_SUPPORT					1
++	#define		RTL8192DU_TEST_HWIMG_SUPPORT				1
++
++	#if defined(UNDER_CE)
++		/* @For 8723 */
++		#define		RTL8723E_HWIMG_SUPPORT					0
++		#define		RTL8723U_HWIMG_SUPPORT					0
++		#define		RTL8723S_HWIMG_SUPPORT					1
++
++		/* @For 88E */
++		#define		RTL8188EE_HWIMG_SUPPORT					0
++		#define		RTL8188EU_HWIMG_SUPPORT					0
++		#define		RTL8188ES_HWIMG_SUPPORT					0
++
++	#else
++
++		/* @For 8723 */
++		#define		RTL8723E_HWIMG_SUPPORT					1
++		/* @#define		RTL_8723E_TEST_HWIMG_SUPPORT			1 */
++		#define		RTL8723U_HWIMG_SUPPORT					1
++		/* @#define		RTL_8723U_TEST_HWIMG_SUPPORT			1 */
++		#define		RTL8723S_HWIMG_SUPPORT					1
++		/* @#define		RTL_8723S_TEST_HWIMG_SUPPORT			1 */
++
++		/* @For 88E */
++		#define		RTL8188EE_HWIMG_SUPPORT					1
++		#define		RTL8188EU_HWIMG_SUPPORT					1
++		#define		RTL8188ES_HWIMG_SUPPORT					1
++	#endif
++
++#endif
++
++#endif /* @__INC_HW_IMG_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_ap.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_ap.c
+new file mode 100644
+index 000000000..857f01946
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_ap.c
+@@ -0,0 +1,1674 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#ifndef index_mapping_NUM_88E
++	#define	index_mapping_NUM_88E	15
++#endif
++
++/* #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) */
++
++#define	CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
++	do {\
++		for (_offset = 0; _offset < _size; _offset++) { \
++			\
++			if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
++				\
++				if (_offset != 0)\
++					_offset--;\
++				break;\
++			} \
++		}			\
++		if (_offset >= _size)\
++			_offset = _size-1;\
++	} while (0)
++
++void odm_clear_txpowertracking_state(	
++	void *dm_void
++)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
++	struct rtl8192cd_priv *priv = dm->priv;
++
++	u8 i;
++	
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===>%s\n", __func__);
++
++	for (i = 0; i < MAX_RF_PATH; i++) {
++		cali_info->absolute_ofdm_swing_idx[i] = 0;
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "cali_info->absolute_ofdm_swing_idx[%d]=%d\n",
++			i, cali_info->absolute_ofdm_swing_idx[i]);
++	}
++
++ 	dm->rf_calibrate_info.thermal_value = 0;
++	dm->rf_calibrate_info.thermal_value_lck = 0;
++	dm->rf_calibrate_info.thermal_value_iqk = 0;
++}
++
++void configure_txpower_track(
++	void		*dm_void,
++	struct txpwrtrack_cfg	*config
++)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++#if RTL8812A_SUPPORT
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	/* if (IS_HARDWARE_TYPE_8812(dm->adapter)) */
++	if (dm->support_ic_type == ODM_RTL8812)
++		configure_txpower_track_8812a(config);
++	/* else */
++#endif
++#endif
++
++#if RTL8814A_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8814A)
++		configure_txpower_track_8814a(config);
++#endif
++
++
++#if RTL8188E_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8188E)
++		configure_txpower_track_8188e(config);
++#endif
++
++#if RTL8197F_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8197F)
++		configure_txpower_track_8197f(config);
++#endif
++
++#if RTL8822B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8822B)
++		configure_txpower_track_8822b(config);
++#endif
++
++#if RTL8192F_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8192F)
++		configure_txpower_track_8192f(config);
++#endif
++
++#if RTL8198F_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8198F)
++		configure_txpower_track_8198f(config);
++#endif
++
++#if RTL8814B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8814B)
++		configure_txpower_track_8814b(config);
++#endif
++
++#if RTL8812F_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8812F)
++		configure_txpower_track_8812f(config);
++#endif
++
++#if RTL8197G_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8197G)
++		configure_txpower_track_8197g(config);
++#endif
++
++}
++
++#if (RTL8192E_SUPPORT == 1)
++void
++odm_txpowertracking_callback_thermal_meter_92e(
++	void		*dm_void
++)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
++	u8	thermal_value = 0, delta, delta_IQK, delta_LCK, channel, is_decrease, rf_mimo_mode;
++	u8	thermal_value_avg_count = 0;
++	u8     OFDM_min_index = 10; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur */
++	s8	OFDM_index[2], index ;
++	u32	thermal_value_avg = 0, reg0x18;
++	u32	i = 0, j = 0, rf;
++	s32	value32, CCK_index = 0, ele_A, ele_D, ele_C, X, Y;
++	struct rtl8192cd_priv	*priv = dm->priv;
++
++	rf_mimo_mode = dm->rf_type;
++	/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode); */
++
++#ifdef MP_TEST
++	if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
++		channel = priv->pshare->working_channel;
++		if (priv->pshare->mp_txpwr_tracking == false)
++			return;
++	} else
++#endif
++	{
++		channel = (priv->pmib->dot11RFEntry.dot11channel);
++	}
++
++	thermal_value = (unsigned char)odm_get_rf_reg(dm, RF_PATH_A, ODM_RF_T_METER_92E, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
++
++
++	switch (rf_mimo_mode) {
++	case RF_1T1R:
++		rf = 1;
++		break;
++	case RF_2T2R:
++		rf = 2;
++		break;
++	default:
++		rf = 2;
++		break;
++	}
++
++	/* Query OFDM path A default setting 	Bit[31:21] */
++	ele_D = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D);
++	for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {
++		if (ele_D == (ofdm_swing_table_92e[i] >> 22)) {
++			OFDM_index[0] = (unsigned char)i;
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0]);
++			break;
++		}
++	}
++
++	/* Query OFDM path B default setting */
++	if (rf_mimo_mode == RF_2T2R) {
++		ele_D = phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKOFDM_D);
++		for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {
++			if (ele_D == (ofdm_swing_table_92e[i] >> 22)) {
++				OFDM_index[1] = (unsigned char)i;
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1]);
++				break;
++			}
++		}
++	}
++
++	/* calculate average thermal meter */
++	{
++		priv->pshare->thermal_value_avg_88xx[priv->pshare->thermal_value_avg_index_88xx] = thermal_value;
++		priv->pshare->thermal_value_avg_index_88xx++;
++		if (priv->pshare->thermal_value_avg_index_88xx == AVG_THERMAL_NUM_88XX)
++			priv->pshare->thermal_value_avg_index_88xx = 0;
++
++		for (i = 0; i < AVG_THERMAL_NUM_88XX; i++) {
++			if (priv->pshare->thermal_value_avg_88xx[i]) {
++				thermal_value_avg += priv->pshare->thermal_value_avg_88xx[i];
++				thermal_value_avg_count++;
++			}
++		}
++
++		if (thermal_value_avg_count) {
++			thermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count);
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value);
++		}
++	}
++
++	/* Initialize */
++	if (!priv->pshare->thermal_value) {
++		priv->pshare->thermal_value = priv->pmib->dot11RFEntry.ther;
++		priv->pshare->thermal_value_iqk = thermal_value;
++		priv->pshare->thermal_value_lck = thermal_value;
++	}
++
++	if (thermal_value != priv->pshare->thermal_value) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n");
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
++
++		delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
++		delta_IQK = RTL_ABS(thermal_value, priv->pshare->thermal_value_iqk);
++		delta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck);
++		is_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0);
++
++#ifdef _TRACKING_TABLE_FILE
++		if (priv->pshare->rf_ft_var.pwr_track_file) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
++
++			if (is_decrease) {
++				for (i = 0; i < rf; i++) {
++					OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);
++					OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E- 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]);
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
++					CCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);
++					CCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index);
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n",  CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));
++				}
++			} else {
++				for (i = 0; i < rf; i++) {
++					OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);
++					OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ?  OFDM_min_index : OFDM_index[i]);
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
++					CCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);
++					CCK_index = ((CCK_index < 0) ? 0 : CCK_index);
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));
++				}
++			}
++		}
++#endif /* CFG_TRACKING_TABLE_FILE */
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]);
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]);
++
++		/* Adujst OFDM Ant_A according to IQK result */
++		ele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22;
++		X = priv->pshare->rege94;
++		Y = priv->pshare->rege9c;
++
++		if (X != 0) {
++			if ((X & 0x00000200) != 0)
++				X = X | 0xFFFFFC00;
++			ele_A = ((X * ele_D) >> 8) & 0x000003FF;
++
++			/* new element C = element D x Y */
++			if ((Y & 0x00000200) != 0)
++				Y = Y | 0xFFFFFC00;
++			ele_C = ((Y * ele_D) >> 8) & 0x000003FF;
++
++			/* wirte new elements A, C, D to regC80 and regC94, element B is always 0 */
++			value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
++			phy_set_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, value32);
++
++			value32 = (ele_C & 0x000003C0) >> 6;
++			phy_set_bb_reg(priv, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, value32);
++
++			value32 = ((X * ele_D) >> 7) & 0x01;
++			phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), value32);
++		} else {
++			phy_set_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]);
++			phy_set_bb_reg(priv, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, 0x00);
++			phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), 0x00);
++		}
++
++		set_CCK_swing_index(priv, CCK_index);
++
++		if (rf == 2) {
++			ele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] & 0xFFC00000) >> 22;
++			X = priv->pshare->regeb4;
++			Y = priv->pshare->regebc;
++
++			if (X != 0) {
++				if ((X & 0x00000200) != 0)	/* consider minus */
++					X = X | 0xFFFFFC00;
++				ele_A = ((X * ele_D) >> 8) & 0x000003FF;
++
++				/* new element C = element D x Y */
++				if ((Y & 0x00000200) != 0)
++					Y = Y | 0xFFFFFC00;
++				ele_C = ((Y * ele_D) >> 8) & 0x00003FF;
++
++				/* wirte new elements A, C, D to regC88 and regC9C, element B is always 0 */
++				value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
++				phy_set_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, value32);
++
++				value32 = (ele_C & 0x000003C0) >> 6;
++				phy_set_bb_reg(priv, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, value32);
++
++				value32 = ((X * ele_D) >> 7) & 0x01;
++				phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), value32);
++			} else {
++				phy_set_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]);
++				phy_set_bb_reg(priv, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, 0x00);
++				phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), 0x00);
++			}
++
++		}
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc80 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD));
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc88 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD));
++
++		if ((delta_IQK > 3) && (!iqk_info->rfk_forbidden)) {
++			priv->pshare->thermal_value_iqk = thermal_value;
++#ifdef MP_TEST
++#endif			if (!(*(dm->mp_mode) && (OPMODE & (WIFI_MP_CTX_BACKGROUND | WIFI_MP_CTX_PACKET))))
++
++				halrf_iqk_trigger(dm, false);
++		}
++
++		if ((delta_LCK > 8)  && (!iqk_info->rfk_forbidden)) {
++			RTL_W8(0x522, 0xff);
++			reg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1);
++			phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1);
++			phy_set_rf_reg(priv, RF_PATH_A, 0x18, BIT(15), 1);
++			delay_ms(1);
++			phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 0);
++			phy_set_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, reg0x18);
++			RTL_W8(0x522, 0x0);
++			priv->pshare->thermal_value_lck = thermal_value;
++		}
++	}
++
++	/* update thermal meter value */
++	priv->pshare->thermal_value = thermal_value;
++	for (i = 0 ; i < rf ; i++)
++		priv->pshare->OFDM_index[i] = OFDM_index[i];
++	priv->pshare->CCK_index = CCK_index;
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
++}
++#endif
++
++#if (RTL8814B_SUPPORT == 1 || RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8197G_SUPPORT == 1)
++void
++odm_txpowertracking_callback_thermal_meter_jaguar_series4(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
++ 	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
++	struct rtl8192cd_priv *priv = dm->priv;
++	struct txpwrtrack_cfg c;
++
++	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
++		return;
++
++	u8 thermal_value[MAX_RF_PATH] = {0}, delta[MAX_RF_PATH] = {0};
++	u8 delta_swing_table_idx_tup[DELTA_SWINGIDX_SIZE] = {0};
++	u8 delta_swing_table_idx_tdown[DELTA_SWINGIDX_SIZE] = {0};
++	u8 delta_LCK = 0, delta_IQK = 0, i = 0, j = 0, p;
++	u8 thermal_value_avg_count[MAX_RF_PATH] = {0};
++	u32 thermal_value_avg[MAX_RF_PATH] = {0};
++	s8 thermal_value_temp[MAX_RF_PATH] = {0};
++
++	u8 *pwrtrk_tab_up_a = NULL;
++	u8 *pwrtrk_tab_down_a = NULL;
++	u8 *pwrtrk_tab_up_b = NULL;
++	u8 *pwrtrk_tab_down_b = NULL;
++	u8 *pwrtrk_tab_up_c = NULL;
++	u8 *pwrtrk_tab_down_c = NULL;
++	u8 *pwrtrk_tab_up_d = NULL;
++	u8 *pwrtrk_tab_down_d = NULL;
++	u8 tracking_method = MIX_MODE;
++
++	configure_txpower_track(dm, &c);
++
++	(*c.get_delta_swing_table)(dm,
++		(u8 **)&pwrtrk_tab_up_a, (u8 **)&pwrtrk_tab_down_a,
++		(u8 **)&pwrtrk_tab_up_b, (u8 **)&pwrtrk_tab_down_b);
++
++	if (GET_CHIP_VER(priv) == VERSION_8814B) {
++		(*c.get_delta_swing_table8814only)(dm,
++			(u8 **)&pwrtrk_tab_up_c, (u8 **)&pwrtrk_tab_down_c,
++			(u8 **)&pwrtrk_tab_up_d, (u8 **)&pwrtrk_tab_down_d);
++	}
++
++	cali_info->txpowertracking_callback_cnt++;
++	cali_info->is_txpowertracking_init = true;
++
++	/* Initialize */
++	if (!dm->rf_calibrate_info.thermal_value)
++		dm->rf_calibrate_info.thermal_value =
++			priv->pmib->dot11RFEntry.thermal[RF_PATH_A];
++
++	if (!dm->rf_calibrate_info.thermal_value_lck)
++		dm->rf_calibrate_info.thermal_value_lck =
++			priv->pmib->dot11RFEntry.thermal[RF_PATH_A];
++
++	if (!dm->rf_calibrate_info.thermal_value_iqk)
++		dm->rf_calibrate_info.thermal_value_iqk =
++			priv->pmib->dot11RFEntry.thermal[RF_PATH_A];
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
++		cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base_path[RF_PATH_A], cali_info->default_ofdm_index);
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		"cali_info->txpowertrack_control=%d\n", cali_info->txpowertrack_control);
++
++	for (i = 0; i < c.rf_path_count; i++) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			"PGthermal[%d]=0x%x(%d)\n", i, 
++			priv->pmib->dot11RFEntry.thermal[i],
++			priv->pmib->dot11RFEntry.thermal[i]);
++
++		if (priv->pmib->dot11RFEntry.thermal[i] == 0xff ||
++			priv->pmib->dot11RFEntry.thermal[i] == 0x0)
++			return;
++	}
++	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {
++		for (i = 0; i < c.rf_path_count; i++)
++			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0x7e); /* 0x42: RF Reg[6:1] Thermal Trim*/
++	} else if (dm->support_ic_type == ODM_RTL8197G) {
++		for (i = 0; i < c.rf_path_count; i++)
++			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, RF_0xf6, 0x7E000);
++	} else {
++		for (i = 0; i < c.rf_path_count; i++) {
++			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
++
++			if (dm->support_ic_type == ODM_RTL8814B) {
++				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_multi_thermal_offset(dm, i);
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + multi_thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_multi_thermal_offset(dm, i));
++			} else {
++				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));
++			}
++
++			if (thermal_value_temp[i] > 63)
++				thermal_value[i] = 63;
++			else if (thermal_value_temp[i] < 0)
++				thermal_value[i] = 0;
++			else
++				thermal_value[i] = thermal_value_temp[i];
++		}
++	}
++
++	for (j = 0; j < c.rf_path_count; j++) {
++		cali_info->thermal_value_avg_path[j][cali_info->thermal_value_avg_index_path[j]] = thermal_value[j];
++		cali_info->thermal_value_avg_index_path[j]++;
++		if (cali_info->thermal_value_avg_index_path[j] == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
++			cali_info->thermal_value_avg_index_path[j] = 0;
++
++
++		for (i = 0; i < c.average_thermal_num; i++) {
++			if (cali_info->thermal_value_avg_path[j][i]) {
++				thermal_value_avg[j] += cali_info->thermal_value_avg_path[j][i];
++				thermal_value_avg_count[j]++;
++			}
++		}
++
++		if (thermal_value_avg_count[j]) {            /* Calculate Average thermal_value after average enough times */
++			thermal_value[j] = (u8)(thermal_value_avg[j] / thermal_value_avg_count[j]);
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"PGthermal[%d] = 0x%x(%d),   AVG Thermal Meter = 0x%x(%d)\n", j,
++				priv->pmib->dot11RFEntry.thermal[j],
++				priv->pmib->dot11RFEntry.thermal[j],
++				thermal_value[j],
++				thermal_value[j]);
++		}
++		/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
++
++		/* "delta" here is used to determine whether thermal value changes or not. */
++		delta[j] = RTL_ABS(thermal_value[j], priv->pmib->dot11RFEntry.thermal[j]);
++		delta_LCK = RTL_ABS(thermal_value[RF_PATH_A], dm->rf_calibrate_info.thermal_value_lck);
++		delta_IQK = RTL_ABS(thermal_value[RF_PATH_A], dm->rf_calibrate_info.thermal_value_iqk);
++	}
++
++	/*4 6. If necessary, do LCK.*/
++	for (i = 0; i < c.rf_path_count; i++)
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta[%d], delta_LCK, delta_IQK) = (%d, %d, %d)\n", i, delta[i], delta_LCK, delta_IQK);
++
++	/* Wait sacn to do LCK by RF Jenyu*/
++	if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
++		/* Delta temperature is equal to or larger than 20 centigrade.*/
++		if (delta_LCK >= c.threshold_iqk) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
++			cali_info->thermal_value_lck = thermal_value[RF_PATH_A];
++
++			/*Use RTLCK, so close power tracking driver LCK*/
++			if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
++				if (c.phy_lc_calibrate)
++					(*c.phy_lc_calibrate)(dm);
++			} else
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do not do LCK\n");
++		}
++	}
++
++	/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
++#ifdef _TRACKING_TABLE_FILE
++	for (i = 0; i < c.rf_path_count; i++) {
++		if (i == RF_PATH_B) {
++			odm_move_memory(dm, delta_swing_table_idx_tup, pwrtrk_tab_up_b, DELTA_SWINGIDX_SIZE);
++			odm_move_memory(dm, delta_swing_table_idx_tdown, pwrtrk_tab_down_b, DELTA_SWINGIDX_SIZE);
++		} else if (i == RF_PATH_C) {
++			odm_move_memory(dm, delta_swing_table_idx_tup, pwrtrk_tab_up_c, DELTA_SWINGIDX_SIZE);
++			odm_move_memory(dm, delta_swing_table_idx_tdown, pwrtrk_tab_down_c, DELTA_SWINGIDX_SIZE);
++		} else if (i == RF_PATH_D) {
++			odm_move_memory(dm, delta_swing_table_idx_tup, pwrtrk_tab_up_d, DELTA_SWINGIDX_SIZE);
++			odm_move_memory(dm, delta_swing_table_idx_tdown, pwrtrk_tab_down_d, DELTA_SWINGIDX_SIZE);
++		} else {
++			odm_move_memory(dm, delta_swing_table_idx_tup, pwrtrk_tab_up_a, DELTA_SWINGIDX_SIZE);
++			odm_move_memory(dm, delta_swing_table_idx_tdown, pwrtrk_tab_down_a, DELTA_SWINGIDX_SIZE);
++		}
++
++		cali_info->delta_power_index_last_path[i] = cali_info->delta_power_index_path[i];	/*recording poer index offset*/
++		delta[i] = thermal_value[i] > priv->pmib->dot11RFEntry.thermal[i] ? (thermal_value[i] - priv->pmib->dot11RFEntry.thermal[i]) : (priv->pmib->dot11RFEntry.thermal[i] - thermal_value[i]);
++				
++		if (delta[i] >= TXPWR_TRACK_TABLE_SIZE)
++			delta[i] = TXPWR_TRACK_TABLE_SIZE - 1;
++
++		if (thermal_value[i] > priv->pmib->dot11RFEntry.thermal[i]) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"delta_swing_table_idx_tup[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tup[delta[i]], i);
++				
++			cali_info->delta_power_index_path[i] = delta_swing_table_idx_tup[delta[i]];
++			cali_info->absolute_ofdm_swing_idx[i] =  delta_swing_table_idx_tup[delta[i]];	    /*Record delta swing for mix mode power tracking*/
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"******Temp is higher and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
++		} else {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"delta_swing_table_idx_tdown[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tdown[delta[i]], i);
++			cali_info->delta_power_index_path[i] = -1 * delta_swing_table_idx_tdown[delta[i]];
++			cali_info->absolute_ofdm_swing_idx[i] = -1 * delta_swing_table_idx_tdown[delta[i]];        /*Record delta swing for mix mode power tracking*/
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"******Temp is lower and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
++		}
++	}
++
++#endif
++
++	for (p = RF_PATH_A; p < c.rf_path_count; p++) {	
++		if (cali_info->delta_power_index_path[p] == cali_info->delta_power_index_last_path[p])	     /*If Thermal value changes but lookup table value still the same*/
++			cali_info->power_index_offset_path[p] = 0;
++		else
++			cali_info->power_index_offset_path[p] = cali_info->delta_power_index_path[p] - cali_info->delta_power_index_last_path[p];	/*Power index diff between 2 times Power Tracking*/
++	}
++
++#if 0
++	if (dm->support_ic_type == ODM_RTL8814B) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++	} else {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
++	}
++#else
++	if (*dm->mp_mode == 1) {
++		if (cali_info->txpowertrack_control == 1) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
++			tracking_method = MIX_MODE;
++		} else if (cali_info->txpowertrack_control == 3) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
++			tracking_method = TSSI_MODE;
++		}
++	} else {
++		if (dm->priv->pmib->dot11RFEntry.tssi_enable == 0) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
++			tracking_method = MIX_MODE;
++		} else if (dm->priv->pmib->dot11RFEntry.tssi_enable == 1) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
++			tracking_method = TSSI_MODE;
++		}
++	}
++
++	if (dm->support_ic_type == ODM_RTL8822C || dm->support_ic_type == ODM_RTL8812F ||
++		dm->support_ic_type == ODM_RTL8814B || dm->support_ic_type == ODM_RTL8197G)
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			(*c.odm_tx_pwr_track_set_pwr)(dm, tracking_method, p, 0);
++
++#endif
++	/* Wait sacn to do IQK by RF Jenyu*/
++	if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden) && (dm->is_linked || *dm->mp_mode)) {
++		/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
++		if (delta_IQK >= c.threshold_iqk) {
++			cali_info->thermal_value_iqk = thermal_value[RF_PATH_A];
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
++
++			/*if (!cali_info->is_iqk_in_progress)*/
++			/* 	(*c.do_iqk)(dm, delta_IQK, thermal_value[RF_PATH_A], 8);*/
++			/*RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do IQK\n");*/
++
++			/*if (!cali_info->is_iqk_in_progress)*/
++			/*	(*c.do_tssi_dck)(dm, true);*/
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do TSSI DCK\n");
++		}
++	}
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===%s\n", __func__);
++
++	cali_info->tx_powercount = 0;
++}
++#endif
++
++#if (RTL8197F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
++	RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
++void
++odm_txpowertracking_callback_thermal_meter_jaguar_series3(
++	void		*dm_void
++)
++{
++#if 1
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase;
++	u8 thermal_value_avg_count = 0, p = 0, i = 0;
++	u32 thermal_value_avg = 0;
++	struct rtl8192cd_priv *priv = dm->priv;
++	struct txpwrtrack_cfg c;
++	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	/*The following tables decide the final index of OFDM/CCK swing table.*/
++	u8 *pwrtrk_tab_up_a = NULL, *pwrtrk_tab_down_a = NULL;
++	u8 *pwrtrk_tab_up_b = NULL, *pwrtrk_tab_down_b = NULL;
++	u8 *pwrtrk_tab_up_cck_a = NULL, *pwrtrk_tab_down_cck_a = NULL;
++	u8 *pwrtrk_tab_up_cck_b = NULL, *pwrtrk_tab_down_cck_b = NULL;
++	/*for 8814 add by Yu Chen*/
++	u8 *pwrtrk_tab_up_c = NULL, *pwrtrk_tab_down_c = NULL;
++	u8 *pwrtrk_tab_up_d = NULL, *pwrtrk_tab_down_d = NULL;
++	u8 *pwrtrk_tab_up_cck_c = NULL, *pwrtrk_tab_down_cck_c = NULL;
++	u8 *pwrtrk_tab_up_cck_d = NULL, *pwrtrk_tab_down_cck_d = NULL;
++	s8 thermal_value_temp = 0;
++
++#ifdef MP_TEST
++	if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
++		channel = priv->pshare->working_channel;
++		if (priv->pshare->mp_txpwr_tracking == false)
++			return;
++	} else
++#endif
++	{
++		channel = (priv->pmib->dot11RFEntry.dot11channel);
++	}
++
++	configure_txpower_track(dm, &c);
++
++	(*c.get_delta_all_swing_table)(dm,
++		(u8 **)&pwrtrk_tab_up_a, (u8 **)&pwrtrk_tab_down_a,
++		(u8 **)&pwrtrk_tab_up_b, (u8 **)&pwrtrk_tab_down_b,
++		(u8 **)&pwrtrk_tab_up_cck_a, (u8 **)&pwrtrk_tab_down_cck_a,
++		(u8 **)&pwrtrk_tab_up_cck_b, (u8 **)&pwrtrk_tab_down_cck_b);
++
++	if (GET_CHIP_VER(priv) == VERSION_8198F) {
++		(*c.get_delta_all_swing_table_ex)(dm,
++			(u8 **)&pwrtrk_tab_up_c, (u8 **)&pwrtrk_tab_down_c,
++			(u8 **)&pwrtrk_tab_up_d, (u8 **)&pwrtrk_tab_down_d,
++			(u8 **)&pwrtrk_tab_up_cck_c, (u8 **)&pwrtrk_tab_down_cck_c,
++			(u8 **)&pwrtrk_tab_up_cck_d, (u8 **)&pwrtrk_tab_down_cck_d);
++	}
++	/*0x42: RF Reg[15:10] 88E*/
++	thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);
++#ifdef THER_TRIM
++	if (GET_CHIP_VER(priv) == VERSION_8197F) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"orig thermal_value=%d, ther_trim_val=%d\n", thermal_value, priv->pshare->rf_ft_var.ther_trim_val);
++
++		thermal_value += priv->pshare->rf_ft_var.ther_trim_val;
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"after thermal trim, thermal_value=%d\n", thermal_value);
++	}
++
++	if (GET_CHIP_VER(priv) == VERSION_8198F) {
++		thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "thermal_value_temp(%d) = ther_value(%d) + ther_trim_ther(%d)\n",
++		       thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
++
++		if (thermal_value_temp > 63)
++			thermal_value = 63;
++		else if (thermal_value_temp < 0)
++			thermal_value = 0;
++		else
++			thermal_value = thermal_value_temp;
++	}
++#endif
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\n\n\nCurrent Thermal = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\n"
++		, thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther);
++
++	/* Initialize */
++	if (!dm->rf_calibrate_info.thermal_value)
++		dm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther;
++
++	if (!dm->rf_calibrate_info.thermal_value_lck)
++		dm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther;
++
++	if (!dm->rf_calibrate_info.thermal_value_iqk)
++		dm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther;
++
++	/* calculate average thermal meter */
++	dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
++	dm->rf_calibrate_info.thermal_value_avg_index++;
++
++	if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
++		dm->rf_calibrate_info.thermal_value_avg_index = 0;
++
++	for (i = 0; i < c.average_thermal_num; i++) {
++		if (dm->rf_calibrate_info.thermal_value_avg[i]) {
++			thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i];
++			thermal_value_avg_count++;
++		}
++	}
++
++	if (thermal_value_avg_count) {/*Calculate Average thermal_value after average enough times*/
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"thermal_value_avg=0x%x(%d)  thermal_value_avg_count = %d\n"
++			, thermal_value_avg, thermal_value_avg, thermal_value_avg_count);
++
++		thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\n", thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther);
++	}
++
++	/*4 Calculate delta, delta_LCK, delta_IQK.*/
++	delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
++	delta_LCK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_lck);
++	delta_IQK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_iqk);
++	is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1);
++
++	if (delta > 29) { /* power track table index(thermal diff.) upper bound*/
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta(%d) > 29, set delta to 29\n", delta);
++		delta = 29;
++	}
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
++
++	/*4 if necessary, do LCK.*/
++	if ((delta_LCK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
++		dm->rf_calibrate_info.thermal_value_lck = thermal_value;
++#if (RTL8822B_SUPPORT != 1)
++		if (!(dm->support_ic_type & ODM_RTL8822B)) {
++			if (c.phy_lc_calibrate)
++				(*c.phy_lc_calibrate)(dm);
++		}
++#endif
++	}
++
++	if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/
++		return;
++
++	/*4 Do Power Tracking*/
++
++	if (thermal_value != dm->rf_calibrate_info.thermal_value) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******** START POWER TRACKING ********\n");
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n",
++		       thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
++
++#ifdef _TRACKING_TABLE_FILE
++		if (priv->pshare->rf_ft_var.pwr_track_file) {
++			if (is_increase) { /*thermal is higher than base*/
++				for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++					switch (p) {
++					case RF_PATH_B:
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_b[%d] = %d pwrtrk_tab_up_cck_b[%d] = %d\n", delta, pwrtrk_tab_up_b[delta], delta, pwrtrk_tab_up_cck_b[delta]);
++						cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_b[delta];
++						cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_b[delta];
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
++						break;
++
++					case RF_PATH_C:
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_c[%d] = %d pwrtrk_tab_up_cck_c[%d] = %d\n", delta, pwrtrk_tab_up_c[delta], delta, pwrtrk_tab_up_cck_c[delta]);
++						cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_c[delta];
++						cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_c[delta];
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
++						break;
++
++					case RF_PATH_D:
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_d[%d] = %d pwrtrk_tab_up_cck_d[%d] = %d\n", delta, pwrtrk_tab_up_d[delta], delta, pwrtrk_tab_up_cck_d[delta]);
++						cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_d[delta];
++						cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_d[delta];
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
++						break;
++					default:
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_a[%d] = %d pwrtrk_tab_up_cck_a[%d] = %d\n", delta, pwrtrk_tab_up_a[delta], delta, pwrtrk_tab_up_cck_a[delta]);
++						cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_a[delta];
++						cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_a[delta];
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
++						break;
++					}
++				}
++			} else { /* thermal is lower than base*/
++				for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++					switch (p) {
++					case RF_PATH_B:
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_b[%d] = %d   pwrtrk_tab_down_cck_b[%d] = %d\n", delta, pwrtrk_tab_down_b[delta], delta, pwrtrk_tab_down_cck_b[delta]);
++						cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_b[delta];
++						cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_b[delta];
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d   pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
++						break;
++
++					case RF_PATH_C:
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_c[%d] = %d   pwrtrk_tab_down_cck_c[%d] = %d\n", delta, pwrtrk_tab_down_c[delta], delta, pwrtrk_tab_down_cck_c[delta]);
++						cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_c[delta];
++						cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_c[delta];
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d   pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
++						break;
++
++					case RF_PATH_D:
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_d[%d] = %d   pwrtrk_tab_down_cck_d[%d] = %d\n", delta, pwrtrk_tab_down_d[delta], delta, pwrtrk_tab_down_cck_d[delta]);
++						cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_d[delta];
++						cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_d[delta];
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d   pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
++						break;
++
++					default:
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_a[%d] = %d   pwrtrk_tab_down_cck_a[%d] = %d\n", delta, pwrtrk_tab_down_a[delta], delta, pwrtrk_tab_down_cck_a[delta]);
++						cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_a[delta];
++						cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_a[delta];
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d   pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
++						break;
++					}
++				}
++			}
++
++			if (is_increase) {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power --->\n");
++				if (GET_CHIP_VER(priv) == VERSION_8197F) {
++					for (p = RF_PATH_A; p < c.rf_path_count; p++)
++						(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
++				} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
++					for (p = RF_PATH_A; p < c.rf_path_count; p++)
++						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++				} else if (GET_CHIP_VER(priv) == VERSION_8822B) {
++					for (p = RF_PATH_A; p < c.rf_path_count; p++)
++						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++				} else if (GET_CHIP_VER(priv) == VERSION_8821C) {
++					for (p = RF_PATH_A; p < c.rf_path_count; p++)
++						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++				}  else if (GET_CHIP_VER(priv) == VERSION_8198F) {
++					for (p = RF_PATH_A; p < c.rf_path_count; p++)
++						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++				} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
++					for (p = RF_PATH_A; p < c.rf_path_count; p++)
++						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++				}
++			} else {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power --->\n");
++				if (GET_CHIP_VER(priv) == VERSION_8197F) {
++					for (p = RF_PATH_A; p < c.rf_path_count; p++)
++						(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
++				} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
++					for (p = RF_PATH_A; p < c.rf_path_count; p++)
++						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++				} else if (GET_CHIP_VER(priv) == VERSION_8822B) {
++					for (p = RF_PATH_A; p < c.rf_path_count; p++)
++						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++				} else if (GET_CHIP_VER(priv) == VERSION_8821C) {
++					for (p = RF_PATH_A; p < c.rf_path_count; p++)
++						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++				} else if (GET_CHIP_VER(priv) == VERSION_8198F) {
++					for (p = RF_PATH_A; p < c.rf_path_count; p++)
++						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++				} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
++					for (p = RF_PATH_A; p < c.rf_path_count; p++)
++						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++				}
++			}
++		}
++#endif
++
++		if (GET_CHIP_VER(priv) != VERSION_8198F) {
++			if ((delta_IQK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden) && dm->is_linked) {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
++				dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
++				if (!(dm->support_ic_type & ODM_RTL8197F)) {
++					if (c.do_iqk)
++						(*c.do_iqk)(dm, false, thermal_value, 0);
++				}
++			}
++		}
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n\n", __func__);
++		/*update thermal meter value*/
++		dm->rf_calibrate_info.thermal_value =  thermal_value;
++
++	}
++
++#endif
++}
++#endif
++
++/*#if (RTL8814A_SUPPORT == 1)*/
++#if (RTL8814A_SUPPORT == 1)
++
++void
++odm_txpowertracking_callback_thermal_meter_jaguar_series2(
++	void		*dm_void
++)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	u8			thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase;
++	u8			thermal_value_avg_count = 0, p = 0, i = 0;
++	u32			thermal_value_avg = 0, reg0x18;
++	u32			bb_swing_reg[4] = {REG_A_TX_SCALE_JAGUAR, REG_B_TX_SCALE_JAGUAR, REG_C_TX_SCALE_JAGUAR2, REG_D_TX_SCALE_JAGUAR2};
++	s32			ele_D;
++	u32			bb_swing_idx;
++	struct rtl8192cd_priv	*priv = dm->priv;
++	struct txpwrtrack_cfg	c;
++	boolean			is_tssi_enable = false;
++	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
++	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
++
++	/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
++	u8			*delta_swing_table_idx_tup_a = NULL, *delta_swing_table_idx_tdown_a = NULL;
++	u8			*delta_swing_table_idx_tup_b = NULL, *delta_swing_table_idx_tdown_b = NULL;
++	/* for 8814 add by Yu Chen */
++	u8			*delta_swing_table_idx_tup_c = NULL, *delta_swing_table_idx_tdown_c = NULL;
++	u8			*delta_swing_table_idx_tup_d = NULL, *delta_swing_table_idx_tdown_d = NULL;
++
++#ifdef MP_TEST
++	if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
++		channel = priv->pshare->working_channel;
++		if (priv->pshare->mp_txpwr_tracking == false)
++			return;
++	} else
++#endif
++	{
++		channel = (priv->pmib->dot11RFEntry.dot11channel);
++	}
++
++	configure_txpower_track(dm, &c);
++	cali_info->default_ofdm_index = priv->pshare->OFDM_index0[RF_PATH_A];
++
++	(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
++		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
++
++	if (dm->support_ic_type & ODM_RTL8814A)	/* for 8814 path C & D */
++		(*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
++			(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
++
++	thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
++
++	/* Initialize */
++	if (!dm->rf_calibrate_info.thermal_value)
++		dm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther;
++
++	if (!dm->rf_calibrate_info.thermal_value_lck)
++		dm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther;
++
++	if (!dm->rf_calibrate_info.thermal_value_iqk)
++		dm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther;
++
++	is_tssi_enable = (boolean)odm_get_rf_reg(dm, RF_PATH_A, REG_RF_TX_GAIN_OFFSET, BIT(7));	/* check TSSI enable */
++
++	/* 4 Query OFDM BB swing default setting 	Bit[31:21] */
++	for (p = RF_PATH_A ; p < c.rf_path_count ; p++) {
++		ele_D = odm_get_bb_reg(dm, bb_swing_reg[p], 0xffe00000);
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[p], odm_get_bb_reg(dm, bb_swing_reg[p], MASKDWORD), ele_D);
++
++		for (bb_swing_idx = 0; bb_swing_idx < TXSCALE_TABLE_SIZE; bb_swing_idx++) {/* 4 */
++			if (ele_D == tx_scaling_table_jaguar[bb_swing_idx]) {
++				dm->rf_calibrate_info.OFDM_index[p] = (u8)bb_swing_idx;
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"OFDM_index[%d]=%d\n", p, dm->rf_calibrate_info.OFDM_index[p]);
++				break;
++			}
++		}
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "kfree_offset[%d]=%d\n", p, cali_info->kfree_offset[p]);
++
++	}
++
++	/* calculate average thermal meter */
++	dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
++	dm->rf_calibrate_info.thermal_value_avg_index++;
++	if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num)  /* Average times =  c.average_thermal_num */
++		dm->rf_calibrate_info.thermal_value_avg_index = 0;
++
++	for (i = 0; i < c.average_thermal_num; i++) {
++		if (dm->rf_calibrate_info.thermal_value_avg[i]) {
++			thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i];
++			thermal_value_avg_count++;
++		}
++	}
++
++	if (thermal_value_avg_count) {            /* Calculate Average thermal_value after average enough times */
++		thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", thermal_value, priv->pmib->dot11RFEntry.ther);
++	}
++
++	/* 4 Calculate delta, delta_LCK, delta_IQK. */
++	delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
++	delta_LCK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_lck);
++	delta_IQK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_iqk);
++	is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1);
++
++	/* 4 if necessary, do LCK. */
++	if (!(dm->support_ic_type & ODM_RTL8821)) {
++		if ((delta_LCK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
++			dm->rf_calibrate_info.thermal_value_lck = thermal_value;
++
++			/*Use RTLCK, so close power tracking driver LCK*/
++#if (RTL8814A_SUPPORT != 1)
++			if (!(dm->support_ic_type & ODM_RTL8814A)) {
++				if (c.phy_lc_calibrate)
++					(*c.phy_lc_calibrate)(dm);
++			}
++#endif
++		}
++	}
++
++	if ((delta_IQK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
++		panic_printk("%s(%d)\n", __FUNCTION__, __LINE__);
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
++		dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
++		if (c.do_iqk)
++			(*c.do_iqk)(dm, true, 0, 0);
++	}
++
++	if (!priv->pmib->dot11RFEntry.ther)	/*Don't do power tracking since no calibrated thermal value*/
++		return;
++
++	/* 4 Do Power Tracking */
++
++	if (is_tssi_enable == true) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter PURE TSSI MODE**********\n");
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			(*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0);
++	} else if (thermal_value != dm->rf_calibrate_info.thermal_value) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\n******** START POWER TRACKING ********\n");
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
++
++#ifdef _TRACKING_TABLE_FILE
++		if (priv->pshare->rf_ft_var.pwr_track_file) {
++			if (is_increase) {		/* thermal is higher than base */
++				for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++					switch (p) {
++					case RF_PATH_B:
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
++						cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta];       /* Record delta swing for mix mode power tracking */
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++						break;
++
++					case RF_PATH_C:
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]);
++						cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta];       /* Record delta swing for mix mode power tracking */
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++						break;
++
++					case RF_PATH_D:
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]);
++						cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta];       /* Record delta swing for mix mode power tracking */
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++						break;
++
++					default:
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
++						cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta];        /* Record delta swing for mix mode power tracking */
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++						break;
++					}
++				}
++			} else {				/* thermal is lower than base */
++				for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++					switch (p) {
++					case RF_PATH_B:
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
++						cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta];        /* Record delta swing for mix mode power tracking */
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++						break;
++
++					case RF_PATH_C:
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]);
++						cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta];        /* Record delta swing for mix mode power tracking */
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++						break;
++
++					case RF_PATH_D:
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]);
++						cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta];        /* Record delta swing for mix mode power tracking */
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++						break;
++
++					default:
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
++						cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta];        /* Record delta swing for mix mode power tracking */
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++						break;
++					}
++				}
++			}
++
++			if (is_increase) {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power --->\n");
++				for (p = RF_PATH_A; p < c.rf_path_count; p++)
++					(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++			} else {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power --->\n");
++				for (p = RF_PATH_A; p < c.rf_path_count; p++)
++					(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++			}
++		}
++#endif
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
++		/* update thermal meter value */
++		dm->rf_calibrate_info.thermal_value =  thermal_value;
++
++	}
++}
++#endif
++
++#if (RTL8812A_SUPPORT == 1 || RTL8881A_SUPPORT == 1)
++void
++odm_txpowertracking_callback_thermal_meter_jaguar_series(
++	void		*dm_void
++)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	unsigned char			thermal_value = 0, delta, delta_LCK, channel, is_decrease;
++	unsigned char			thermal_value_avg_count = 0;
++	unsigned int			thermal_value_avg = 0, reg0x18;
++	unsigned int			bb_swing_reg[4] = {0xc1c, 0xe1c, 0x181c, 0x1a1c};
++	int					ele_D, value32;
++	char					OFDM_index[2], index;
++	unsigned int			i = 0, j = 0, rf_path, max_rf_path = 2, rf;
++	struct rtl8192cd_priv		*priv = dm->priv;
++	unsigned char			OFDM_min_index = 7; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur and Mimic */
++	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
++
++
++#ifdef MP_TEST
++	if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
++		channel = priv->pshare->working_channel;
++		if (priv->pshare->mp_txpwr_tracking == false)
++			return;
++	} else
++#endif
++	{
++		channel = (priv->pmib->dot11RFEntry.dot11channel);
++	}
++
++#if RTL8881A_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8881A) {
++		max_rf_path = 1;
++		if ((get_bonding_type_8881A() == BOND_8881AM || get_bonding_type_8881A() == BOND_8881AN)
++		    && priv->pshare->rf_ft_var.use_intpa8881A && (*dm->band_type == ODM_BAND_2_4G))
++			OFDM_min_index = 6;		/* intPA - upper bond set to +3 dB (base: -2 dB)ot11RFEntry.phy_band_select == PHY_BAND_2G)) */
++		else
++			OFDM_min_index = 10;		/* OFDM BB Swing should be less than +1dB, which is required by Arthur and Mimic */
++	}
++#endif
++
++
++	thermal_value = (unsigned char)phy_query_rf_reg(priv, RF_PATH_A, 0x42, 0xfc00, 1); /* 0x42: RF Reg[15:10] 88E */
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
++
++
++	/* 4 Query OFDM BB swing default setting 	Bit[31:21] */
++	for (rf_path = 0 ; rf_path < max_rf_path ; rf_path++) {
++		ele_D = phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000);
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], MASKDWORD), ele_D);
++		for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */
++			if (ele_D == ofdm_swing_table_8812[i]) {
++				OFDM_index[rf_path] = (unsigned char)i;
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[%d]=%d\n", rf_path, OFDM_index[rf_path]);
++				break;
++			}
++		}
++	}
++#if 0
++	/* Query OFDM path A default setting 	Bit[31:21] */
++	ele_D = phy_query_bb_reg(priv, 0xc1c, 0xffe00000);
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc1c:0x%x ([31:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xc1c, MASKDWORD), ele_D);
++	for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */
++		if (ele_D == ofdm_swing_table_8812[i]) {
++			OFDM_index[0] = (unsigned char)i;
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[0]=%d\n", OFDM_index[0]);
++			break;
++		}
++	}
++	/* Query OFDM path B default setting */
++	if (rf == 2) {
++		ele_D = phy_query_bb_reg(priv, 0xe1c, 0xffe00000);
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xe1c:0x%x ([32:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xe1c, MASKDWORD), ele_D);
++		for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {
++			if (ele_D == ofdm_swing_table_8812[i]) {
++				OFDM_index[1] = (unsigned char)i;
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[1]=%d\n", OFDM_index[1]);
++				break;
++			}
++		}
++	}
++#endif
++	/* Initialize */
++	if (!priv->pshare->thermal_value) {
++		priv->pshare->thermal_value = priv->pmib->dot11RFEntry.ther;
++		priv->pshare->thermal_value_lck = thermal_value;
++	}
++
++	/* calculate average thermal meter */
++	{
++		priv->pshare->thermal_value_avg_8812[priv->pshare->thermal_value_avg_index_8812] = thermal_value;
++		priv->pshare->thermal_value_avg_index_8812++;
++		if (priv->pshare->thermal_value_avg_index_8812 == AVG_THERMAL_NUM_8812)
++			priv->pshare->thermal_value_avg_index_8812 = 0;
++
++		for (i = 0; i < AVG_THERMAL_NUM_8812; i++) {
++			if (priv->pshare->thermal_value_avg_8812[i]) {
++				thermal_value_avg += priv->pshare->thermal_value_avg_8812[i];
++				thermal_value_avg_count++;
++			}
++		}
++
++		if (thermal_value_avg_count) {
++			thermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count);
++			/* printk("AVG Thermal Meter = 0x%x\n", thermal_value); */
++		}
++	}
++
++
++	/* 4 If necessary,  do power tracking */
++
++	if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/
++		return;
++
++	if (thermal_value != priv->pshare->thermal_value) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n");
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
++		delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
++		delta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck);
++		is_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0);
++		/* if (*dm->band_type == ODM_BAND_5G) */
++		{
++#ifdef _TRACKING_TABLE_FILE
++			if (priv->pshare->rf_ft_var.pwr_track_file) {
++				for (rf_path = 0; rf_path < max_rf_path; rf_path++) {
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
++					if (is_decrease) {
++						OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] + get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0);
++						OFDM_index[rf_path] = ((OFDM_index[rf_path] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[rf_path]);
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
++#if 0/* RTL8881A_SUPPORT */
++						if (dm->support_ic_type == ODM_RTL8881A) {
++							if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) {
++								if (priv->pshare->add_tx_agc) { /* tx_agc has been added */
++									add_tx_power88xx_ac(priv, 0);
++									priv->pshare->add_tx_agc = 0;
++									priv->pshare->add_tx_agc_index = 0;
++								}
++							}
++						}
++#endif
++					} else {
++
++						OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] - get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0);
++#if 0/* RTL8881A_SUPPORT */
++						if (dm->support_ic_type == ODM_RTL8881A) {
++							if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) {
++								if (OFDM_index[i] < OFDM_min_index) {
++									priv->pshare->add_tx_agc_index = (OFDM_min_index - OFDM_index[i]) / 2; /* Calculate Remnant tx_agc value,  2 index for 1 tx_agc */
++									add_tx_power88xx_ac(priv, priv->pshare->add_tx_agc_index);
++									priv->pshare->add_tx_agc = 1;     /* add_tx_agc Flag = 1 */
++									OFDM_index[i] = OFDM_min_index;
++								} else {
++									if (priv->pshare->add_tx_agc) { /* tx_agc been added */
++										priv->pshare->add_tx_agc = 0;
++										priv->pshare->add_tx_agc_index = 0;
++										add_tx_power88xx_ac(priv, 0); /* minus the added TPI */
++									}
++								}
++							}
++						}
++#else
++						OFDM_index[rf_path] = ((OFDM_index[rf_path] < OFDM_min_index) ?  OFDM_min_index : OFDM_index[rf_path]);
++#endif
++						RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
++					}
++				}
++			}
++#endif
++			/* 4 Set new BB swing index */
++			for (rf_path = 0; rf_path < max_rf_path; rf_path++) {
++				phy_set_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000, ofdm_swing_table_8812[(unsigned int)OFDM_index[rf_path]]);
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000), OFDM_index[rf_path]);
++			}
++
++		}
++		if ((delta_LCK > 8) && (!iqk_info->rfk_forbidden)) {
++			RTL_W8(0x522, 0xff);
++			reg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1);
++			phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1);
++			phy_set_rf_reg(priv, RF_PATH_A, 0x18, BIT(15), 1);
++			delay_ms(200); /* frequency deviation */
++			phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 0);
++			phy_set_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, reg0x18);
++#ifdef CONFIG_RTL_8812_SUPPORT
++			if (GET_CHIP_VER(priv) == VERSION_8812E)
++				update_bbrf_val8812(priv, priv->pmib->dot11RFEntry.dot11channel);
++#endif
++			RTL_W8(0x522, 0x0);
++			priv->pshare->thermal_value_lck = thermal_value;
++		}
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
++
++		/* update thermal meter value */
++		priv->pshare->thermal_value = thermal_value;
++		for (rf_path = 0; rf_path < max_rf_path; rf_path++)
++			priv->pshare->OFDM_index[rf_path] = OFDM_index[rf_path];
++	}
++}
++
++#endif
++
++
++void
++odm_txpowertracking_callback_thermal_meter(
++	void		*dm_void
++)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
++	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
++
++	
++#if (RTL8814B_SUPPORT == 1 || RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8197G_SUPPORT == 1)
++	if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8822C | ODM_RTL8197G)) {
++		odm_txpowertracking_callback_thermal_meter_jaguar_series4(dm);
++		return;
++	}
++#endif
++#if (RTL8197F_SUPPORT == 1 ||RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8197F || dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8822B
++		|| dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8198F) {
++		odm_txpowertracking_callback_thermal_meter_jaguar_series3(dm);
++		return;
++	}
++#endif
++#if (RTL8814A_SUPPORT == 1)		/*use this function to do power tracking after 8814 by YuChen*/
++	if (dm->support_ic_type & ODM_RTL8814A) {
++		odm_txpowertracking_callback_thermal_meter_jaguar_series2(dm);
++		return;
++	}
++#endif
++#if (RTL8881A_SUPPORT || RTL8812A_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8812 || dm->support_ic_type & ODM_RTL8881A) {
++		odm_txpowertracking_callback_thermal_meter_jaguar_series(dm);
++		return;
++	}
++#endif
++
++#if (RTL8192E_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8192E) {
++		odm_txpowertracking_callback_thermal_meter_92e(dm);
++		return;
++	}
++#endif
++
++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
++	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	/* PMGNT_INFO      		mgnt_info = &adapter->mgnt_info; */
++#endif
++
++
++	u8			thermal_value = 0, delta, delta_LCK, delta_IQK, offset;
++	u8			thermal_value_avg_count = 0;
++	u32			thermal_value_avg = 0;
++	/*	s32			ele_A=0, ele_D, TempCCk, X, value32;
++	 *	s32			Y, ele_C=0;
++	 *	s8			OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index;
++	 *	s8			deltaPowerIndex = 0; */
++	u32			i = 0;/* , j = 0; */
++	boolean		is2T = false;
++	/*	bool 		bInteralPA = false; */
++
++	u8			OFDM_max_index = 34, rf = (is2T) ? 2 : 1; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
++	u8			indexforchannel = 0;/*get_right_chnl_place_for_iqk(hal_data->current_channel)*/
++	enum            _POWER_DEC_INC { POWER_DEC, POWER_INC };
++
++	struct txpwrtrack_cfg	c;
++
++
++	/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
++	s8			delta_swing_table_idx[2][index_mapping_NUM_88E] = {
++		/* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */
++		{0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11}, {0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 7, 8, 9, 9, 10}
++	};
++	u8			thermal_threshold[2][index_mapping_NUM_88E] = {
++		/* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */
++		{0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 27}, {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 25, 25}
++	};
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	struct rtl8192cd_priv	*priv = dm->priv;
++#endif
++
++	/* 4 2. Initilization ( 7 steps in total ) */
++
++	configure_txpower_track(dm, &c);
++
++	dm->rf_calibrate_info.txpowertracking_callback_cnt++; /* cosa add for debug */
++	dm->rf_calibrate_info.is_txpowertracking_init = true;
++
++#if (MP_DRIVER == 1)
++	dm->rf_calibrate_info.txpowertrack_control = hal_data->txpowertrack_control; /* <Kordan> We should keep updating the control variable according to HalData.
++     * <Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
++	dm->rf_calibrate_info.rega24 = 0x090e1317;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(MP_TEST)
++	if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
++		if (dm->priv->pshare->mp_txpwr_tracking == false)
++			return;
++	}
++#endif
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===>odm_txpowertracking_callback_thermal_meter_8188e, dm->bb_swing_idx_cck_base: %d, dm->bb_swing_idx_ofdm_base: %d\n", cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base);
++	/*
++		if (!dm->rf_calibrate_info.tm_trigger) {
++			odm_set_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, BIT(17) | BIT(16), 0x3);
++			dm->rf_calibrate_info.tm_trigger = 1;
++			return;
++		}
++	*/
++	thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
++	if (!thermal_value || !dm->rf_calibrate_info.txpowertrack_control)
++#else
++	if (!dm->rf_calibrate_info.txpowertrack_control)
++#endif
++		return;
++
++	/* 4 3. Initialize ThermalValues of rf_calibrate_info */
++
++	if (!dm->rf_calibrate_info.thermal_value) {
++		dm->rf_calibrate_info.thermal_value_lck = thermal_value;
++		dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
++	}
++
++	if (dm->rf_calibrate_info.is_reloadtxpowerindex)
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n");
++
++	/* 4 4. Calculate average thermal meter */
++
++	dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
++	dm->rf_calibrate_info.thermal_value_avg_index++;
++	if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num)
++		dm->rf_calibrate_info.thermal_value_avg_index = 0;
++
++	for (i = 0; i < c.average_thermal_num; i++) {
++		if (dm->rf_calibrate_info.thermal_value_avg[i]) {
++			thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i];
++			thermal_value_avg_count++;
++		}
++	}
++
++	if (thermal_value_avg_count) {
++		/* Give the new thermo value a weighting */
++		thermal_value_avg += (thermal_value * 4);
++
++		thermal_value = (u8)(thermal_value_avg / (thermal_value_avg_count + 4));
++		cali_info->thermal_value_delta = thermal_value - priv->pmib->dot11RFEntry.ther;
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value);
++	}
++
++	/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
++
++	delta	  = (thermal_value > dm->rf_calibrate_info.thermal_value) ? (thermal_value - dm->rf_calibrate_info.thermal_value) : (dm->rf_calibrate_info.thermal_value - thermal_value);
++	delta_LCK = (thermal_value > dm->rf_calibrate_info.thermal_value_lck) ? (thermal_value - dm->rf_calibrate_info.thermal_value_lck) : (dm->rf_calibrate_info.thermal_value_lck - thermal_value);
++	delta_IQK = (thermal_value > dm->rf_calibrate_info.thermal_value_iqk) ? (thermal_value - dm->rf_calibrate_info.thermal_value_iqk) : (dm->rf_calibrate_info.thermal_value_iqk - thermal_value);
++
++	/* 4 6. If necessary, do LCK. */
++	if (!(dm->support_ic_type & ODM_RTL8821)) {
++		/*if((delta_LCK > hal_data->delta_lck) && (hal_data->delta_lck != 0))*/
++		if ((delta_LCK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
++			/*Delta temperature is equal to or larger than 20 centigrade.*/
++			dm->rf_calibrate_info.thermal_value_lck = thermal_value;
++			(*c.phy_lc_calibrate)(dm);
++		}
++	}
++
++	/* 3 7. If necessary, move the index of swing table to adjust Tx power. */
++
++	if (delta > 0 && dm->rf_calibrate_info.txpowertrack_control) {
++
++		delta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value);
++
++		/* 4 7.1 The Final Power index = BaseIndex + power_index_offset */
++
++		if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
++			CALCULATE_SWINGTALBE_OFFSET(offset, POWER_INC, index_mapping_NUM_88E, delta);
++			dm->rf_calibrate_info.delta_power_index_last = dm->rf_calibrate_info.delta_power_index;
++			dm->rf_calibrate_info.delta_power_index =  delta_swing_table_idx[POWER_INC][offset];
++
++		} else {
++
++			CALCULATE_SWINGTALBE_OFFSET(offset, POWER_DEC, index_mapping_NUM_88E, delta);
++			dm->rf_calibrate_info.delta_power_index_last = dm->rf_calibrate_info.delta_power_index;
++			dm->rf_calibrate_info.delta_power_index = (-1) * delta_swing_table_idx[POWER_DEC][offset];
++		}
++
++		if (dm->rf_calibrate_info.delta_power_index == dm->rf_calibrate_info.delta_power_index_last)
++			dm->rf_calibrate_info.power_index_offset = 0;
++		else
++			dm->rf_calibrate_info.power_index_offset = dm->rf_calibrate_info.delta_power_index - dm->rf_calibrate_info.delta_power_index_last;
++
++		for (i = 0; i < rf; i++)
++			dm->rf_calibrate_info.OFDM_index[i] = cali_info->bb_swing_idx_ofdm_base + dm->rf_calibrate_info.power_index_offset;
++		dm->rf_calibrate_info.CCK_index = cali_info->bb_swing_idx_cck_base + dm->rf_calibrate_info.power_index_offset;
++
++		cali_info->bb_swing_idx_cck = dm->rf_calibrate_info.CCK_index;
++		cali_info->bb_swing_idx_ofdm[RF_PATH_A] = dm->rf_calibrate_info.OFDM_index[RF_PATH_A];
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, dm->rf_calibrate_info.power_index_offset);
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "The 'OFDM' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base, dm->rf_calibrate_info.power_index_offset);
++
++		/* 4 7.1 Handle boundary conditions of index. */
++
++
++		for (i = 0; i < rf; i++) {
++			if (dm->rf_calibrate_info.OFDM_index[i] > OFDM_max_index)
++				dm->rf_calibrate_info.OFDM_index[i] = OFDM_max_index;
++			else if (dm->rf_calibrate_info.OFDM_index[i] < 0)
++				dm->rf_calibrate_info.OFDM_index[i] = 0;
++		}
++
++		if (dm->rf_calibrate_info.CCK_index > c.swing_table_size_cck - 1)
++			dm->rf_calibrate_info.CCK_index = c.swing_table_size_cck - 1;
++		else if (dm->rf_calibrate_info.CCK_index < 0)
++			dm->rf_calibrate_info.CCK_index = 0;
++	} else {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"The thermal meter is unchanged or TxPowerTracking OFF: thermal_value: %d, dm->rf_calibrate_info.thermal_value: %d)\n", thermal_value, dm->rf_calibrate_info.thermal_value);
++		dm->rf_calibrate_info.power_index_offset = 0;
++	}
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.CCK_index, cali_info->bb_swing_idx_cck_base);
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.OFDM_index[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base);
++
++	if (dm->rf_calibrate_info.power_index_offset != 0 && dm->rf_calibrate_info.txpowertrack_control) {
++		/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
++
++		dm->rf_calibrate_info.is_tx_power_changed = true; /* Always true after Tx Power is adjusted by power tracking. */
++		/*  */
++		/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
++		/* to increase TX power. Otherwise, EVM will be bad. */
++		/*  */
++		/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
++		if (thermal_value > dm->rf_calibrate_info.thermal_value) {
++			/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK, */
++			/*	"Temperature Increasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */
++			/*	dm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */
++		} else if (thermal_value < dm->rf_calibrate_info.thermal_value) { /* Low temperature */
++			/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK, */
++			/*	"Temperature Decreasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */
++			/*		dm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */
++		}
++		if (thermal_value > dm->priv->pmib->dot11RFEntry.ther)
++		{
++			/*				RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"Temperature(%d) hugher than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */
++			(*c.odm_tx_pwr_track_set_pwr)(dm, TXAGC, 0, 0);
++		} else {
++			/*			RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"Temperature(%d) lower than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */
++			(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_A, indexforchannel);
++			if (is2T)
++				(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_B, indexforchannel);
++		}
++
++		cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;
++		cali_info->bb_swing_idx_ofdm_base = cali_info->bb_swing_idx_ofdm[RF_PATH_A];
++		dm->rf_calibrate_info.thermal_value = thermal_value;
++
++	}
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n");
++
++	dm->rf_calibrate_info.tx_powercount = 0;
++}
++
++/* 3============================================================
++ * 3 IQ Calibration
++ * 3============================================================ */
++
++void
++odm_reset_iqk_result(
++	void		*dm_void
++)
++{
++	return;
++}
++#if 1/* !(DM_ODM_SUPPORT_TYPE & ODM_AP) */
++u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
++{
++	u8	channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
++		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
++	};
++	u8	place = chnl;
++
++
++	if (chnl > 14) {
++		for (place = 14; place < sizeof(channel_all); place++) {
++			if (channel_all[place] == chnl)
++				return place - 13;
++		}
++	}
++	return 0;
++
++}
++#endif
++
++void
++odm_iq_calibrate(
++	struct dm_struct	*dm
++)
++{
++	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
++
++	if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) {
++		if ((*dm->channel != dm->pre_channel) && (!*dm->is_scan_in_process)) {
++			dm->pre_channel = *dm->channel;
++			dm->linked_interval = 0;
++		}
++
++		if (dm->linked_interval < 3)
++			dm->linked_interval++;
++
++		if (dm->linked_interval == 2)
++			halrf_iqk_trigger(dm, false);
++	} else
++		dm->linked_interval = 0;
++
++}
++
++void phydm_rf_init(void		*dm_void)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	odm_txpowertracking_init(dm);
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++#if (RTL8814A_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814A)
++		phy_iq_calibrate_8814a_init(dm);
++#endif
++#endif
++
++}
++
++void phydm_rf_watchdog(void		*dm_void)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++
++	odm_txpowertracking_check(dm);
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
++		odm_iq_calibrate(dm);
++#endif
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_ap.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_ap.h
+new file mode 100644
+index 000000000..8cc2797bc
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_ap.h
+@@ -0,0 +1,170 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __HALPHYRF_H__
++#define __HALPHYRF_H__
++
++#include "halrf/halrf_powertracking_ap.h"
++#include "halrf/halrf_kfree.h"
++
++#if (RTL8814A_SUPPORT == 1)
++	#include "halrf/rtl8814a/halrf_iqk_8814a.h"
++#endif
++
++#if (RTL8822B_SUPPORT == 1)
++	#include "halrf/rtl8822b/halrf_iqk_8822b.h"
++#endif
++
++#if (RTL8821C_SUPPORT == 1)
++	#include "halrf/rtl8821c/halrf_iqk_8821c.h"
++#endif
++
++#if (RTL8195B_SUPPORT == 1)
++//	#include "halrf/rtl8195b/halrf.h"
++	#include "halrf/rtl8195b/halrf_iqk_8195b.h"
++	#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
++	#include "halrf/rtl8195b/halrf_dpk_8195b.h"
++#endif
++
++#if (RTL8198F_SUPPORT == 1)
++	#include "halrf/rtl8198f/halrf_iqk_8198f.h"
++	#include "halrf/rtl8198f/halrf_dpk_8198f.h"
++#endif
++
++#if (RTL8812F_SUPPORT == 1)
++	#include "halrf/rtl8812f/halrf_iqk_8812f.h"
++	#include "halrf/rtl8812f/halrf_dpk_8812f.h"
++	#include "halrf/rtl8812f/halrf_tssi_8812f.h"
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++	#include "halrf/rtl8814b/halrf_iqk_8814b.h"
++	#include "halrf/rtl8814b/halrf_dpk_8814b.h"
++	#include "halrf/rtl8814b/halrf_txgapk_8814b.h"
++#endif
++
++#if (RTL8197G_SUPPORT == 1)
++	#include "halrf/rtl8197g/halrf_iqk_8197g.h"
++	#include "halrf/rtl8197g/halrf_dpk_8197g.h"
++	#include "halrf/rtl8197g/halrf_tssi_8197g.h"
++#endif
++
++enum pwrtrack_method {
++	BBSWING,
++	TXAGC,
++	MIX_MODE,
++	TSSI_MODE,
++	MIX_2G_TSSI_5G_MODE,
++	MIX_5G_TSSI_2G_MODE,
++	CLEAN_MODE
++};
++
++typedef void	(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
++typedef void(*func_iqk)(void *, u8, u8, u8);
++typedef void	(*func_lck)(void *);
++typedef void	(*func_tssi_dck)(void *, u8);
++/* refine by YuChen for 8814A */
++typedef void	(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
++typedef void	(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
++typedef void	(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
++typedef void	(*func_all_swing_ex)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
++
++struct txpwrtrack_cfg {
++	u8		swing_table_size_cck;
++	u8		swing_table_size_ofdm;
++	u8		threshold_iqk;
++	u8		threshold_dpk;
++	u8		average_thermal_num;
++	u8		rf_path_count;
++	u32		thermal_reg_addr;
++	func_set_pwr	odm_tx_pwr_track_set_pwr;
++	func_iqk	do_iqk;
++	func_lck		phy_lc_calibrate;
++	func_tssi_dck	do_tssi_dck;
++	func_swing	get_delta_swing_table;
++	func_swing8814only	get_delta_swing_table8814only;
++	func_all_swing		get_delta_all_swing_table;
++	func_all_swing_ex	get_delta_all_swing_table_ex;
++};
++
++void
++odm_clear_txpowertracking_state(
++	void *dm_void
++);
++
++void
++configure_txpower_track(
++	void		*dm_void,
++	struct txpwrtrack_cfg	*config
++);
++
++
++void
++odm_txpowertracking_callback_thermal_meter(
++	void		*dm_void
++);
++
++#if (RTL8192E_SUPPORT == 1)
++void
++odm_txpowertracking_callback_thermal_meter_92e(
++	void		*dm_void
++);
++#endif
++
++#if (RTL8814A_SUPPORT == 1)
++void
++odm_txpowertracking_callback_thermal_meter_jaguar_series2(
++	void		*dm_void
++);
++
++#elif ODM_IC_11AC_SERIES_SUPPORT
++void
++odm_txpowertracking_callback_thermal_meter_jaguar_series(
++	void		*dm_void
++);
++
++#elif (RTL8197F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
++	RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
++void
++odm_txpowertracking_callback_thermal_meter_jaguar_series3(
++	void		*dm_void
++);
++
++#elif (RTL8814B_SUPPORT == 1 || RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8197G_SUPPORT == 1)
++void
++odm_txpowertracking_callback_thermal_meter_jaguar_series4(
++	void		*dm_void
++);
++
++#endif
++
++#define IS_CCK_RATE(_rate)				(ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M)
++
++#define ODM_TARGET_CHNL_NUM_2G_5G	59
++
++
++void
++odm_reset_iqk_result(
++	void		*dm_void
++);
++u8
++odm_get_right_chnl_place_for_iqk(
++	u8 chnl
++);
++
++void phydm_rf_init(void		*dm_void);
++void phydm_rf_watchdog(void		*dm_void);
++
++#endif	/*#ifndef __HALPHYRF_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_ce.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_ce.c
+new file mode 100644
+index 000000000..9b21e4944
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_ce.c
+@@ -0,0 +1,1176 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal)\
++	do {                                                                   \
++		u32 __offset = (u32)_offset;                                   \
++		u32 __size = (u32)_size;                                       \
++		for (__offset = 0; __offset < __size; __offset++) {            \
++			if (_delta_thermal <                                   \
++				thermal_threshold[_direction][__offset]) {     \
++				if (__offset != 0)                             \
++					__offset--;                            \
++				break;                                         \
++			}                                                      \
++		}                                                              \
++		if (__offset >= __size)                                        \
++			__offset = __size - 1;                                 \
++	} while (0)
++
++void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if RTL8192E_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8192E)
++		configure_txpower_track_8192e(config);
++#endif
++#if RTL8821A_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8821)
++		configure_txpower_track_8821a(config);
++#endif
++#if RTL8812A_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8812)
++		configure_txpower_track_8812a(config);
++#endif
++#if RTL8188E_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8188E)
++		configure_txpower_track_8188e(config);
++#endif
++
++#if RTL8723B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8723B)
++		configure_txpower_track_8723b(config);
++#endif
++
++#if RTL8814A_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8814A)
++		configure_txpower_track_8814a(config);
++#endif
++
++#if RTL8703B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8703B)
++		configure_txpower_track_8703b(config);
++#endif
++
++#if RTL8188F_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8188F)
++		configure_txpower_track_8188f(config);
++#endif
++#if RTL8723D_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8723D)
++		configure_txpower_track_8723d(config);
++#endif
++/*@ JJ ADD 20161014 */
++#if RTL8710B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8710B)
++		configure_txpower_track_8710b(config);
++#endif
++#if RTL8822B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8822B)
++		configure_txpower_track_8822b(config);
++#endif
++#if RTL8821C_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8821C)
++		configure_txpower_track_8821c(config);
++#endif
++
++#if RTL8192F_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8192F)
++		configure_txpower_track_8192f(config);
++#endif
++
++#if RTL8822C_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8822C)
++		configure_txpower_track_8822c(config);
++#endif
++
++#if RTL8814B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8814B)
++		configure_txpower_track_8814b(config);
++#endif
++
++
++}
++
++/*@ **********************************************************************
++ * <20121113, Kordan> This function should be called when tx_agc changed.
++ * Otherwise the previous compensation is gone, because we record the
++ * delta of temperature between two TxPowerTracking watch dogs.
++ *
++ * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
++ * need to call this function.
++ * **********************************************************************
++ */
++void odm_clear_txpowertracking_state(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	u8 p = 0;
++	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
++
++	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
++	cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
++	dm->rf_calibrate_info.CCK_index = 0;
++
++	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
++		cali_info->bb_swing_idx_ofdm_base[p]
++						= cali_info->default_ofdm_index;
++		cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
++		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
++
++		cali_info->power_index_offset[p] = 0;
++		cali_info->delta_power_index[p] = 0;
++		cali_info->delta_power_index_last[p] = 0;
++
++		/* Initial Mix mode power tracking*/
++		cali_info->absolute_ofdm_swing_idx[p] = 0;
++		cali_info->remnant_ofdm_swing_idx[p] = 0;
++		cali_info->kfree_offset[p] = 0;
++	}
++	/* Initial Mix mode power tracking*/
++	cali_info->modify_tx_agc_flag_path_a = false;
++	cali_info->modify_tx_agc_flag_path_b = false;
++	cali_info->modify_tx_agc_flag_path_c = false;
++	cali_info->modify_tx_agc_flag_path_d = false;
++	cali_info->remnant_cck_swing_idx = 0;
++	cali_info->thermal_value = rf->eeprom_thermal;
++	cali_info->modify_tx_agc_value_cck = 0;
++	cali_info->modify_tx_agc_value_ofdm = 0;
++}
++
++void odm_get_tracking_table(void *dm_void, u8 thermal_value, u8 delta)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	struct txpwrtrack_cfg c = {0};
++
++	u8 p;
++	/* 4 1. TWO tables decide the final index of OFDM/CCK swing table. */
++	u8 *pwrtrk_tab_up_a = NULL;
++	u8 *pwrtrk_tab_down_a = NULL;
++	u8 *pwrtrk_tab_up_b = NULL;
++	u8 *pwrtrk_tab_down_b = NULL;
++	/*for 8814 add by Yu Chen*/
++	u8 *pwrtrk_tab_up_c = NULL;
++	u8 *pwrtrk_tab_down_c = NULL;
++	u8 *pwrtrk_tab_up_d = NULL;
++	u8 *pwrtrk_tab_down_d = NULL;
++	/*for Xtal Offset by James.Tung*/
++	s8 *xtal_tab_up = NULL;
++	s8 *xtal_tab_down = NULL;
++
++	configure_txpower_track(dm, &c);
++
++	(*c.get_delta_swing_table)(dm,
++				   (u8 **)&pwrtrk_tab_up_a,
++				   (u8 **)&pwrtrk_tab_down_a,
++				   (u8 **)&pwrtrk_tab_up_b,
++				   (u8 **)&pwrtrk_tab_down_b);
++
++	if (dm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/
++		(*c.get_delta_swing_table8814only)(dm,
++						   (u8 **)&pwrtrk_tab_up_c,
++						   (u8 **)&pwrtrk_tab_down_c,
++						   (u8 **)&pwrtrk_tab_up_d,
++						   (u8 **)&pwrtrk_tab_down_d);
++	/*for Xtal Offset*/
++	if (dm->support_ic_type &
++	    (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F))
++		(*c.get_delta_swing_xtal_table)(dm,
++						(s8 **)&xtal_tab_up,
++						(s8 **)&xtal_tab_down);
++
++	if (thermal_value > rf->eeprom_thermal) {
++		for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++			/*recording power index offset*/
++			cali_info->delta_power_index_last[p] =
++					cali_info->delta_power_index[p];
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "******Temp is higher******\n");
++			switch (p) {
++			case RF_PATH_B:
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "pwrtrk_tab_up_b[%d] = %d\n", delta,
++				       pwrtrk_tab_up_b[delta]);
++
++				cali_info->delta_power_index[p] =
++							pwrtrk_tab_up_b[delta];
++				cali_info->absolute_ofdm_swing_idx[p] =
++							pwrtrk_tab_up_b[delta];
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "absolute_ofdm_swing_idx[PATH_B] = %d\n",
++				       cali_info->absolute_ofdm_swing_idx[p]);
++				break;
++
++			case RF_PATH_C:
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "pwrtrk_tab_up_c[%d] = %d\n", delta,
++				       pwrtrk_tab_up_c[delta]);
++
++				cali_info->delta_power_index[p] =
++							pwrtrk_tab_up_c[delta];
++				cali_info->absolute_ofdm_swing_idx[p] =
++							pwrtrk_tab_up_c[delta];
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "absolute_ofdm_swing_idx[PATH_C] = %d\n",
++				       cali_info->absolute_ofdm_swing_idx[p]);
++				break;
++
++			case RF_PATH_D:
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "pwrtrk_tab_up_d[%d] = %d\n", delta,
++				       pwrtrk_tab_up_d[delta]);
++
++				cali_info->delta_power_index[p] =
++							pwrtrk_tab_up_d[delta];
++				cali_info->absolute_ofdm_swing_idx[p] =
++							pwrtrk_tab_up_d[delta];
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "absolute_ofdm_swing_idx[PATH_D] = %d\n",
++				       cali_info->absolute_ofdm_swing_idx[p]);
++				break;
++
++			default:
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "pwrtrk_tab_up_a[%d] = %d\n", delta,
++				       pwrtrk_tab_up_a[delta]);
++
++				cali_info->delta_power_index[p] =
++							pwrtrk_tab_up_a[delta];
++				cali_info->absolute_ofdm_swing_idx[p] =
++							pwrtrk_tab_up_a[delta];
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "absolute_ofdm_swing_idx[PATH_A] = %d\n",
++				       cali_info->absolute_ofdm_swing_idx[p]);
++				break;
++			}
++		}
++		/* @JJ ADD 20161014 */
++		/*Save xtal_offset from Xtal table*/
++		if (dm->support_ic_type &
++		    (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B |
++		    ODM_RTL8192F)) {
++			/*recording last Xtal offset*/
++			cali_info->xtal_offset_last = cali_info->xtal_offset;
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "[Xtal] xtal_tab_up[%d] = %d\n",
++			       delta, xtal_tab_up[delta]);
++			cali_info->xtal_offset = xtal_tab_up[delta];
++			if (cali_info->xtal_offset_last != xtal_tab_up[delta])
++				cali_info->xtal_offset_eanble = 1;
++		}
++	} else {
++		for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++			/*recording power index offset*/
++			cali_info->delta_power_index_last[p] =
++						cali_info->delta_power_index[p];
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "******Temp is lower******\n");
++			switch (p) {
++			case RF_PATH_B:
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "pwrtrk_tab_down_b[%d] = %d\n", delta,
++				       pwrtrk_tab_down_b[delta]);
++				cali_info->delta_power_index[p] =
++						-1 * pwrtrk_tab_down_b[delta];
++				cali_info->absolute_ofdm_swing_idx[p] =
++						-1 * pwrtrk_tab_down_b[delta];
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "absolute_ofdm_swing_idx[PATH_B] = %d\n",
++				       cali_info->absolute_ofdm_swing_idx[p]);
++				break;
++
++			case RF_PATH_C:
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "pwrtrk_tab_down_c[%d] = %d\n", delta,
++				       pwrtrk_tab_down_c[delta]);
++				cali_info->delta_power_index[p] =
++						-1 * pwrtrk_tab_down_c[delta];
++				cali_info->absolute_ofdm_swing_idx[p] =
++						-1 * pwrtrk_tab_down_c[delta];
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "absolute_ofdm_swing_idx[PATH_C] = %d\n",
++				       cali_info->absolute_ofdm_swing_idx[p]);
++				break;
++
++			case RF_PATH_D:
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "pwrtrk_tab_down_d[%d] = %d\n", delta,
++				       pwrtrk_tab_down_d[delta]);
++				cali_info->delta_power_index[p] =
++						-1 * pwrtrk_tab_down_d[delta];
++				cali_info->absolute_ofdm_swing_idx[p] =
++						-1 * pwrtrk_tab_down_d[delta];
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "absolute_ofdm_swing_idx[PATH_D] = %d\n",
++				       cali_info->absolute_ofdm_swing_idx[p]);
++				break;
++
++			default:
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "pwrtrk_tab_down_a[%d] = %d\n", delta,
++				       pwrtrk_tab_down_a[delta]);
++				cali_info->delta_power_index[p] =
++						-1 * pwrtrk_tab_down_a[delta];
++				cali_info->absolute_ofdm_swing_idx[p] =
++						-1 * pwrtrk_tab_down_a[delta];
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "absolute_ofdm_swing_idx[PATH_A] = %d\n",
++				       cali_info->absolute_ofdm_swing_idx[p]);
++				break;
++			}
++		}
++		/* @JJ ADD 20161014 */
++		if (dm->support_ic_type &
++		    (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B |
++		    ODM_RTL8192F)) {
++			/*recording last Xtal offset*/
++			cali_info->xtal_offset_last = cali_info->xtal_offset;
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "[Xtal] xtal_tab_down[%d] = %d\n", delta,
++			       xtal_tab_down[delta]);
++			/*Save xtal_offset from Xtal table*/
++			cali_info->xtal_offset = xtal_tab_down[delta];
++			if (cali_info->xtal_offset_last != xtal_tab_down[delta])
++				cali_info->xtal_offset_eanble = 1;
++		}
++	}
++}
++
++void odm_pwrtrk_method(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 p, idxforchnl = 0;
++
++	struct txpwrtrack_cfg c = {0};
++
++	configure_txpower_track(dm, &c);
++
++	if (dm->support_ic_type &
++		(ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8821 | ODM_RTL8812 |
++		ODM_RTL8723B | ODM_RTL8814A | ODM_RTL8703B | ODM_RTL8188F |
++		ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8710B |
++		ODM_RTL8192F)) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "***Enter PwrTrk MIX_MODE***\n");
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++	} else if (dm->support_ic_type & ODM_RTL8723D) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "***Enter PwrTrk MIX_MODE***\n");
++		p = (u8)odm_get_bb_reg(dm, R_0x948, 0x00000080);
++		(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++		/*if open ant_div 0x948=140,do 2 path pwr_track*/
++		if (odm_get_bb_reg(dm, R_0x948, 0x00000040))
++			(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, 1, 0);
++	} else {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "***Enter PwrTrk BBSWING_MODE***\n");
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			(*c.odm_tx_pwr_track_set_pwr)
++				(dm, BBSWING, p, idxforchnl);
++	}
++}
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++void odm_txpowertracking_callback_thermal_meter(struct dm_struct *dm)
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++void odm_txpowertracking_callback_thermal_meter(void *dm_void)
++#else
++void odm_txpowertracking_callback_thermal_meter(void *adapter)
++#endif
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#endif
++
++	struct _hal_rf_ *rf = &dm->rf_table;
++	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++
++	u8 thermal_value = 0, delta, delta_lck, delta_iqk, p = 0, i = 0;
++	u8 thermal_value_avg_count = 0;
++	u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
++
++	/* OFDM BB Swing should be less than +3.0dB, required by Arthur */
++#if 0
++	u8 OFDM_min_index = 0;
++#endif
++#if 0
++	/* get_right_chnl_place_for_iqk(hal_data->current_channel) */
++#endif
++	u8 power_tracking_type = rf->pwt_type;
++	s8 thermal_value_temp = 0;
++
++	struct txpwrtrack_cfg c = {0};
++
++	/* @4 2. Initialization ( 7 steps in total ) */
++
++	configure_txpower_track(dm, &c);
++
++	cali_info->txpowertracking_callback_cnt++;
++	cali_info->is_txpowertracking_init = true;
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++	       "\n\n\n===>%s bbsw_idx_cck_base=%d\n",
++	       __func__, cali_info->bb_swing_idx_cck_base);
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++	       "bbsw_idx_ofdm_base[A]=%d default_ofdm_idx=%d\n",
++	       cali_info->bb_swing_idx_ofdm_base[RF_PATH_A],
++	       cali_info->default_ofdm_index);
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++	       "cali_info->txpowertrack_control=%d, rf->eeprom_thermal %d\n",
++	       cali_info->txpowertrack_control, rf->eeprom_thermal);
++
++	 /* 0x42: RF Reg[15:10] 88E */
++	thermal_value =
++		(u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);
++
++	thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++	       "thermal_value_temp(%d) = ther_value(%d) + pwr_trim_ther(%d)\n",
++	       thermal_value_temp, thermal_value,
++	       phydm_get_thermal_offset(dm));
++
++	if (thermal_value_temp > 63)
++		thermal_value = 63;
++	else if (thermal_value_temp < 0)
++		thermal_value = 0;
++	else
++		thermal_value = thermal_value_temp;
++
++	/*@add log by zhao he, check c80/c94/c14/ca0 value*/
++	if (dm->support_ic_type &
++	    (ODM_RTL8723D | ODM_RTL8710B)) {
++		regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
++		regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);
++		regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);
++		regab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF);
++		RF_DBG(dm, DBG_RF_IQK,
++		       "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n",
++		       regc80, regcd0, regcd4, regab4);
++	}
++
++	if (!cali_info->txpowertrack_control)
++		return;
++
++	if (rf->eeprom_thermal == 0xff) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "no pg, hal_data->eeprom_thermal_meter = 0x%x\n",
++		       rf->eeprom_thermal);
++		return;
++	}
++
++	/*@4 3. Initialize ThermalValues of rf_calibrate_info*/
++
++	if (cali_info->is_reloadtxpowerindex)
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "reload ofdm index for band switch\n");
++
++	/*@4 4. Calculate average thermal meter*/
++
++	cali_info->thermal_value_avg[cali_info->thermal_value_avg_index]
++		= thermal_value;
++
++	cali_info->thermal_value_avg_index++;
++	/*Average times =  c.average_thermal_num*/
++	if (cali_info->thermal_value_avg_index == c.average_thermal_num)
++		cali_info->thermal_value_avg_index = 0;
++
++	for (i = 0; i < c.average_thermal_num; i++) {
++		if (cali_info->thermal_value_avg[i]) {
++			thermal_value_avg += cali_info->thermal_value_avg[i];
++			thermal_value_avg_count++;
++		}
++	}
++
++	/* Calculate Average thermal_value after average enough times */
++	if (thermal_value_avg_count) {
++		thermal_value =
++			(u8)(thermal_value_avg / thermal_value_avg_count);
++		cali_info->thermal_value_delta
++			= thermal_value - rf->eeprom_thermal;
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n",
++		       thermal_value, rf->eeprom_thermal);
++	}
++
++	/* @4 5. Calculate delta, delta_lck, delta_iqk. */
++	/* "delta" here is used to determine thermal value changes or not. */
++	if (thermal_value > cali_info->thermal_value)
++		delta = thermal_value - cali_info->thermal_value;
++	else
++		delta = cali_info->thermal_value - thermal_value;
++
++	if (thermal_value > cali_info->thermal_value_lck)
++		delta_lck = thermal_value - cali_info->thermal_value_lck;
++	else
++		delta_lck = cali_info->thermal_value_lck - thermal_value;
++
++	if (thermal_value > cali_info->thermal_value_iqk)
++		delta_iqk = thermal_value - cali_info->thermal_value_iqk;
++	else
++		delta_iqk = cali_info->thermal_value_iqk - thermal_value;
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++	       "(delta, delta_lck, delta_iqk) = (%d, %d, %d)\n", delta,
++	       delta_lck, delta_iqk);
++
++	/*@4 6. If necessary, do LCK.*/
++	/* Wait sacn to do LCK by RF Jenyu*/
++	if (!(*dm->is_scan_in_process) && !iqk_info->rfk_forbidden) {
++		/* Delta temperature is equal to or larger than 20 centigrade.*/
++		if (delta_lck >= c.threshold_iqk) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "delta_lck(%d) >= threshold_iqk(%d)\n",
++			       delta_lck, c.threshold_iqk);
++			cali_info->thermal_value_lck = thermal_value;
++
++			/*Use RTLCK, close power tracking driver LCK*/
++			/*8821 don't do LCK*/
++			if (!(dm->support_ic_type &
++				(ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B)) &&
++				c.phy_lc_calibrate) {
++				(*c.phy_lc_calibrate)(dm);
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "do pwrtrk lck\n");
++			}
++		}
++	}
++
++	/*@3 7. If necessary, move the index of swing table to adjust Tx power.*/
++	/* "delta" here is used to record the absolute value of difference. */
++	if (delta > 0 && cali_info->txpowertrack_control) {
++		if (thermal_value > rf->eeprom_thermal)
++			delta = thermal_value - rf->eeprom_thermal;
++		else
++			delta = rf->eeprom_thermal - thermal_value;
++
++		if (delta >= TXPWR_TRACK_TABLE_SIZE)
++			delta = TXPWR_TRACK_TABLE_SIZE - 1;
++
++		odm_get_tracking_table(dm, thermal_value, delta);
++
++		for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "\n[path-%d] Calculate pwr_idx_offset\n", p);
++
++			/*If Thermal value changes but table value is the same*/
++			if (cali_info->delta_power_index[p] ==
++				cali_info->delta_power_index_last[p])
++				cali_info->power_index_offset[p] = 0;
++			else
++				cali_info->power_index_offset[p] =
++				cali_info->delta_power_index[p] -
++				cali_info->delta_power_index_last[p];
++
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "path-%d pwridx_diff%d=pwr_idx%d - last_idx%d\n",
++			       p, cali_info->power_index_offset[p],
++			       cali_info->delta_power_index[p],
++			       cali_info->delta_power_index_last[p]);
++#if 0
++
++			cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];
++			cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];
++
++			cali_info->bb_swing_idx_cck = cali_info->CCK_index;
++			cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];
++
++			/*************Print BB Swing base and index Offset*************/
++
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n",
++			       cali_info->bb_swing_idx_cck,
++			       cali_info->bb_swing_idx_cck_base,
++			       cali_info->power_index_offset[p]);
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n",
++			       cali_info->bb_swing_idx_ofdm[p], p,
++			       cali_info->bb_swing_idx_ofdm_base[p],
++			       cali_info->power_index_offset[p]);
++
++			/*4 7.1 Handle boundary conditions of index.*/
++
++			if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
++				cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
++			else if (cali_info->OFDM_index[p] <= OFDM_min_index)
++				cali_info->OFDM_index[p] = OFDM_min_index;
++#endif
++		}
++#if 0
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "\n\n========================================================================================================\n");
++
++		if (cali_info->CCK_index > c.swing_table_size_cck - 1)
++			cali_info->CCK_index = c.swing_table_size_cck - 1;
++		else if (cali_info->CCK_index <= 0)
++			cali_info->CCK_index = 0;
++#endif
++	} else {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "Thermal is unchanged thermal=%d last_thermal=%d\n",
++		       thermal_value,
++		       cali_info->thermal_value);
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			cali_info->power_index_offset[p] = 0;
++	}
++
++#if 0
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++	       "TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
++	       cali_info->CCK_index,
++	       cali_info->bb_swing_idx_cck_base); /*Print Swing base & current*/
++
++	for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
++		       cali_info->OFDM_index[p], p,
++		       cali_info->bb_swing_idx_ofdm_base[p]);
++	}
++#endif
++
++	if ((dm->support_ic_type & ODM_RTL8814A)) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "power_tracking_type=%d\n",
++		       power_tracking_type);
++
++		if (power_tracking_type == 0) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "***Enter PwrTrk MIX_MODE***\n");
++			for (p = RF_PATH_A; p < c.rf_path_count; p++)
++				(*c.odm_tx_pwr_track_set_pwr)
++					(dm, MIX_MODE, p, 0);
++		} else if (power_tracking_type == 1) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "***Enter PwrTrk MIX(2G) TSSI(5G) MODE***\n");
++			for (p = RF_PATH_A; p < c.rf_path_count; p++)
++				(*c.odm_tx_pwr_track_set_pwr)
++					(dm, MIX_2G_TSSI_5G_MODE, p, 0);
++		} else if (power_tracking_type == 2) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "***Enter PwrTrk MIX(5G) TSSI(2G)MODE***\n");
++			for (p = RF_PATH_A; p < c.rf_path_count; p++)
++				(*c.odm_tx_pwr_track_set_pwr)
++					(dm, MIX_5G_TSSI_2G_MODE, p, 0);
++		} else if (power_tracking_type == 3) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "***Enter PwrTrk TSSI MODE***\n");
++			for (p = RF_PATH_A; p < c.rf_path_count; p++)
++				(*c.odm_tx_pwr_track_set_pwr)
++					(dm, TSSI_MODE, p, 0);
++		}
++	} else if ((cali_info->power_index_offset[RF_PATH_A] != 0 ||
++		    cali_info->power_index_offset[RF_PATH_B] != 0 ||
++		    cali_info->power_index_offset[RF_PATH_C] != 0 ||
++		    cali_info->power_index_offset[RF_PATH_D] != 0)) {
++#if 0
++		/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
++		/*Always true after Tx Power is adjusted by power tracking.*/
++
++		cali_info->is_tx_power_changed = true;
++		/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
++		 * to increase TX power. Otherwise, EVM will be bad.
++		 *
++		 * 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E.
++		 */
++		if (thermal_value > cali_info->thermal_value) {
++			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
++				       p, cali_info->power_index_offset[p],
++				       delta, thermal_value, rf->eeprom_thermal,
++				       cali_info->thermal_value);
++			}
++		} else if (thermal_value < cali_info->thermal_value) { /*Low temperature*/
++			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
++				       p, cali_info->power_index_offset[p],
++				       delta, thermal_value, rf->eeprom_thermal,
++				       cali_info->thermal_value);
++			}
++		}
++#endif
++
++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
++		if (thermal_value > rf->eeprom_thermal) {
++#else
++		if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
++#endif
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "Temperature(%d) higher than PG value(%d)\n",
++			       thermal_value, rf->eeprom_thermal);
++
++			odm_pwrtrk_method(dm);
++		} else {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "Temperature(%d) lower than PG value(%d)\n",
++			       thermal_value, rf->eeprom_thermal);
++
++			odm_pwrtrk_method(dm);
++		}
++
++#if 0
++		/*Record last time Power Tracking result as base.*/
++		cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];
++#endif
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "cali_info->thermal_value = %d thermal_value= %d\n",
++		       cali_info->thermal_value, thermal_value);
++	}
++	/*Record last Power Tracking Thermal value*/
++	cali_info->thermal_value = thermal_value;
++
++	if (dm->support_ic_type &
++		(ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8192F | ODM_RTL8710B)) {
++		if (cali_info->xtal_offset_eanble != 0 &&
++		    cali_info->txpowertrack_control &&
++		    rf->eeprom_thermal != 0xff) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "**********Enter Xtal Tracking**********\n");
++
++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
++			if (thermal_value > rf->eeprom_thermal) {
++#else
++			if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
++#endif
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "Temperature(%d) higher than PG (%d)\n",
++				       thermal_value, rf->eeprom_thermal);
++				(*c.odm_txxtaltrack_set_xtal)(dm);
++			} else {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "Temperature(%d) lower than PG (%d)\n",
++				       thermal_value, rf->eeprom_thermal);
++				(*c.odm_txxtaltrack_set_xtal)(dm);
++			}
++		}
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "**********End Xtal Tracking**********\n");
++	}
++
++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
++
++	/* Wait sacn to do IQK by RF Jenyu*/
++	if (!(*dm->is_scan_in_process) && !iqk_info->rfk_forbidden &&
++	    !cali_info->is_iqk_in_progress && dm->is_linked) {
++		if (!(dm->support_ic_type & ODM_RTL8723B)) {
++			/*Delta temperature is equal or larger than 20 Celsius*/
++			/*When threshold is 8*/
++			if (delta_iqk >= c.threshold_iqk) {
++				cali_info->thermal_value_iqk = thermal_value;
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "delta_iqk(%d) >= threshold_iqk(%d)\n",
++				       delta_iqk, c.threshold_iqk);
++				(*c.do_iqk)(dm, delta_iqk, thermal_value, 8);
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "do pwrtrk iqk\n");
++			}
++		}
++	}
++
++#if 0
++	if (cali_info->dpk_thermal[RF_PATH_A] != 0) {
++		if (diff_DPK[RF_PATH_A] >= c.threshold_dpk) {
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
++			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk));
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
++		} else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) {
++			s32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk);
++
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
++			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
++		} else {
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
++			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
++		}
++	}
++	if (cali_info->dpk_thermal[RF_PATH_B] != 0) {
++		if (diff_DPK[RF_PATH_B] >= c.threshold_dpk) {
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
++			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk));
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
++		} else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) {
++			s32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk);
++
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
++			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
++		} else {
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
++			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
++		}
++	}
++#endif
++
++#endif
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===%s\n", __func__);
++
++	cali_info->tx_powercount = 0;
++}
++
++#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
++void
++odm_txpowertracking_new_callback_thermal_meter(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
++ 	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
++	u8 thermal_value[MAX_RF_PATH] = {0}, delta[MAX_RF_PATH] = {0};
++	u8 delta_swing_table_idx_tup[DELTA_SWINGIDX_SIZE] = {0};
++	u8 delta_swing_table_idx_tdown[DELTA_SWINGIDX_SIZE] = {0};
++	u8 delta_LCK = 0, delta_IQK = 0, i = 0, j = 0, p;
++	u8 thermal_value_avg_count[MAX_RF_PATH] = {0};
++	u32 thermal_value_avg[MAX_RF_PATH] = {0};
++	s8 thermal_value_temp[MAX_RF_PATH] = {0};
++	u8 tracking_method = MIX_MODE;
++
++	struct txpwrtrack_cfg c;
++
++	u8 *delta_swing_table_idx_tup_a = NULL;
++	u8 *delta_swing_table_idx_tdown_a = NULL;
++	u8 *delta_swing_table_idx_tup_b = NULL;
++	u8 *delta_swing_table_idx_tdown_b = NULL;
++	u8 *delta_swing_table_idx_tup_c = NULL;
++	u8 *delta_swing_table_idx_tdown_c = NULL;
++	u8 *delta_swing_table_idx_tup_d = NULL;
++	u8 *delta_swing_table_idx_tdown_d = NULL;
++
++	configure_txpower_track(dm, &c);
++
++	(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
++		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
++
++	if (dm->support_ic_type == ODM_RTL8814B) {
++		(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
++			(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
++	}
++
++	cali_info->txpowertracking_callback_cnt++;
++	cali_info->is_txpowertracking_init = true;
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
++		cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		"cali_info->txpowertrack_control=%d, tssi->thermal[RF_PATH_A]=%d tssi->thermal[RF_PATH_B]=%d\n",
++		cali_info->txpowertrack_control,  tssi->thermal[RF_PATH_A], tssi->thermal[RF_PATH_B]);
++
++	if (dm->support_ic_type == ODM_RTL8822C) {
++		for (i = 0; i < c.rf_path_count; i++)
++			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0x7e); /* 0x42: RF Reg[6:1] Thermal Trim*/
++	} else {
++		for (i = 0; i < c.rf_path_count; i++) {
++			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
++
++			if (dm->support_ic_type == ODM_RTL8814B) {
++				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_multi_thermal_offset(dm, i);
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + multi_thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_multi_thermal_offset(dm, i));
++			} else {
++				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));
++			}
++
++			if (thermal_value_temp[i] > 63)
++				thermal_value[i] = 63;
++			else if (thermal_value_temp[i] < 0)
++				thermal_value[i] = 0;
++			else
++				thermal_value[i] = thermal_value_temp[i];
++		}
++	}
++
++	if ((tssi->thermal[RF_PATH_A] == 0xff || tssi->thermal[RF_PATH_B] == 0xff) &&
++		cali_info->txpowertrack_control != 3) {
++		for (i = 0; i < c.rf_path_count; i++)
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, tssi->thermal[%d] = 0x%x\n",
++				i, tssi->thermal[i]);
++		return;
++	}
++
++	for (j = 0; j < c.rf_path_count; j++) {
++		cali_info->thermal_value_avg_path[j][cali_info->thermal_value_avg_index_path[j]] = thermal_value[j];
++		cali_info->thermal_value_avg_index_path[j]++;
++		if (cali_info->thermal_value_avg_index_path[j] == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
++			cali_info->thermal_value_avg_index_path[j] = 0;
++
++
++		for (i = 0; i < c.average_thermal_num; i++) {
++			if (cali_info->thermal_value_avg_path[j][i]) {
++				thermal_value_avg[j] += cali_info->thermal_value_avg_path[j][i];
++				thermal_value_avg_count[j]++;
++			}
++		}
++
++		if (thermal_value_avg_count[j]) {            /* Calculate Average thermal_value after average enough times */
++			thermal_value[j] = (u8)(thermal_value_avg[j] / thermal_value_avg_count[j]);
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"AVG Thermal Meter = 0x%X, tssi->thermal[%d] = 0x%x\n",
++				thermal_value[j], j, tssi->thermal[j]);
++		}
++		/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
++
++		/* "delta" here is used to determine whether thermal value changes or not. */
++		delta[j] = (thermal_value[j] > cali_info->thermal_value_path[j]) ? (thermal_value[j] - cali_info->thermal_value_path[j]) : (cali_info->thermal_value_path[j] - thermal_value[j]);
++		delta_LCK = (thermal_value[0] > cali_info->thermal_value_lck) ? (thermal_value[0] - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value[0]);
++		delta_IQK = (thermal_value[0] > cali_info->thermal_value_iqk) ? (thermal_value[0] - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value[0]);
++	}
++
++	/*4 6. If necessary, do LCK.*/
++
++	for (i = 0; i < c.rf_path_count; i++)
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta[%d], delta_LCK, delta_IQK) = (%d, %d, %d)\n", i, delta[i], delta_LCK, delta_IQK);
++
++	/* Wait sacn to do LCK by RF Jenyu*/
++	if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
++		/* Delta temperature is equal to or larger than 20 centigrade.*/
++		if (delta_LCK >= c.threshold_iqk) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
++			cali_info->thermal_value_lck = thermal_value[RF_PATH_A];
++
++			/*Use RTLCK, so close power tracking driver LCK*/
++			if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
++				if (c.phy_lc_calibrate)
++					(*c.phy_lc_calibrate)(dm);
++			} else
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do not do LCK\n");
++		}
++	}
++
++	/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
++	for (i = 0; i < c.rf_path_count; i++) {
++		if (i == RF_PATH_B) {
++			odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_b, DELTA_SWINGIDX_SIZE);
++			odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_b, DELTA_SWINGIDX_SIZE);
++		} else if (i == RF_PATH_C) {
++			odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_c, DELTA_SWINGIDX_SIZE);
++			odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_c, DELTA_SWINGIDX_SIZE);
++		} else if (i == RF_PATH_D) {
++			odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_d, DELTA_SWINGIDX_SIZE);
++			odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_d, DELTA_SWINGIDX_SIZE);
++		} else {
++			odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_a, DELTA_SWINGIDX_SIZE);
++			odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_a, DELTA_SWINGIDX_SIZE);
++		}
++
++		cali_info->delta_power_index_last[i] = cali_info->delta_power_index[i];	/*recording poer index offset*/
++		delta[i] = thermal_value[i] > tssi->thermal[i] ? (thermal_value[i] - tssi->thermal[i]) : (tssi->thermal[i] - thermal_value[i]);
++				
++		if (delta[i] >= TXPWR_TRACK_TABLE_SIZE)
++			delta[i] = TXPWR_TRACK_TABLE_SIZE - 1;
++
++		if (thermal_value[i] > tssi->thermal[i]) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"delta_swing_table_idx_tup[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tup[delta[i]], i);
++				
++			cali_info->delta_power_index[i] = delta_swing_table_idx_tup[delta[i]];
++			cali_info->absolute_ofdm_swing_idx[i] =  delta_swing_table_idx_tup[delta[i]];	    /*Record delta swing for mix mode power tracking*/
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"******Temp is higher and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
++		} else {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"delta_swing_table_idx_tdown[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tdown[delta[i]], i);
++			cali_info->delta_power_index[i] = -1 * delta_swing_table_idx_tdown[delta[i]];
++			cali_info->absolute_ofdm_swing_idx[i] = -1 * delta_swing_table_idx_tdown[delta[i]];        /*Record delta swing for mix mode power tracking*/
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"******Temp is lower and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
++		}
++	}
++
++	for (p = RF_PATH_A; p < c.rf_path_count; p++) {	
++		if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p])	     /*If Thermal value changes but lookup table value still the same*/
++			cali_info->power_index_offset[p] = 0;
++		else
++			cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p];	/*Power index diff between 2 times Power Tracking*/
++	}
++
++#if 0
++	if (dm->support_ic_type == ODM_RTL8822C) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++	} else {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
++	}
++#endif
++	if (*dm->mp_mode == 1) {
++		if (cali_info->txpowertrack_control == 1) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
++			tracking_method = MIX_MODE;
++		} else if (cali_info->txpowertrack_control == 3) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
++			tracking_method = TSSI_MODE;
++		}
++	} else {
++		if (rf->power_track_type >= 0 && rf->power_track_type <= 3) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
++			tracking_method = MIX_MODE;
++		} else if (rf->power_track_type >= 4 && rf->power_track_type <= 7) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
++			tracking_method = TSSI_MODE;
++		}
++	}
++
++	if (dm->support_ic_type == ODM_RTL8822C || dm->support_ic_type == ODM_RTL8814B)
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			(*c.odm_tx_pwr_track_set_pwr)(dm, tracking_method, p, 0);
++
++	/* Wait sacn to do IQK by RF Jenyu*/
++	if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden) && (dm->is_linked || *dm->mp_mode)) {
++		/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
++		if (delta_IQK >= c.threshold_iqk) {
++			cali_info->thermal_value_iqk = thermal_value[RF_PATH_A];
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
++			/*if (!cali_info->is_iqk_in_progress)*/
++			/*	(*c.do_iqk)(dm, delta_IQK, thermal_value[RF_PATH_A], 8);*/
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do IQK\n");
++
++			/*if (!cali_info->is_iqk_in_progress)*/
++			/*	(*c.do_tssi_dck)(dm, true);*/
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do TSSI DCK\n");
++		}
++	}
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===%s\n", __func__);
++
++	cali_info->tx_powercount = 0;
++}
++#endif
++
++/*@3============================================================
++ * 3 IQ Calibration
++ * 3============================================================
++ */
++
++void odm_reset_iqk_result(void *dm_void)
++{
++}
++
++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
++u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
++{
++	u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
++		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
++		36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64,
++		100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122,
++		124, 126, 128, 130, 132, 134, 136, 138, 140,
++		149, 151, 153, 155, 157, 159, 161, 163, 165};
++	u8 place = chnl;
++
++	if (chnl > 14) {
++		for (place = 14; place < sizeof(channel_all); place++) {
++			if (channel_all[place] == chnl)
++				return place - 13;
++		}
++	}
++	return 0;
++}
++#endif
++
++void odm_iq_calibrate(struct dm_struct *dm)
++{
++	void *adapter = dm->adapter;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	if (*dm->is_fcs_mode_enable)
++		return;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
++	if (IS_HARDWARE_TYPE_8812AU(adapter))
++		return;
++#endif
++
++	if (dm->is_linked && !iqk_info->rfk_forbidden) {
++		if ((*dm->channel != dm->pre_channel) &&
++		    (!*dm->is_scan_in_process)) {
++			dm->pre_channel = *dm->channel;
++			dm->linked_interval = 0;
++		}
++
++		if (dm->linked_interval < 3)
++			dm->linked_interval++;
++
++		if (dm->linked_interval == 2)
++			halrf_iqk_trigger(dm, false);
++	} else {
++		dm->linked_interval = 0;
++	}
++}
++
++void phydm_rf_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	odm_txpowertracking_init(dm);
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	odm_clear_txpowertracking_state(dm);
++#endif
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++#if (RTL8814A_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814A)
++		phy_iq_calibrate_8814a_init(dm);
++#endif
++#endif
++}
++
++void phydm_rf_watchdog(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	odm_txpowertracking_check(dm);
++#if 0
++/*if (dm->support_ic_type & ODM_IC_11AC_SERIES)*/
++/*odm_iq_calibrate(dm);*/
++#endif
++#endif
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_ce.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_ce.h
+new file mode 100644
+index 000000000..dcded1e0a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_ce.h
+@@ -0,0 +1,123 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __HALPHYRF_H__
++#define __HALPHYRF_H__
++
++#include "halrf/halrf_kfree.h"
++#if (RTL8814A_SUPPORT == 1)
++#include "halrf/rtl8814a/halrf_iqk_8814a.h"
++#endif
++
++#if (RTL8822B_SUPPORT == 1)
++#include "halrf/rtl8822b/halrf_iqk_8822b.h"
++#endif
++
++#if (RTL8821C_SUPPORT == 1)
++#include "halrf/rtl8821c/halrf_iqk_8821c.h"
++#endif
++
++#if (RTL8195B_SUPPORT == 1)
++/* #include "halrf/rtl8195b/halrf.h" */
++#include "halrf/rtl8195b/halrf_iqk_8195b.h"
++#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
++#include "halrf/rtl8195b/halrf_dpk_8195b.h"
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++	#include "halrf/rtl8814b/halrf_iqk_8814b.h"	
++	#include "halrf/rtl8814b/halrf_dpk_8814b.h"
++	#include "halrf/rtl8814b/halrf_txgapk_8814b.h"
++#endif
++
++#include "halrf/halrf_powertracking_ce.h"
++
++enum spur_cal_method {
++	PLL_RESET,
++	AFE_PHASE_SEL
++};
++
++enum pwrtrack_method {
++	BBSWING,
++	TXAGC,
++	MIX_MODE,
++	TSSI_MODE,
++	MIX_2G_TSSI_5G_MODE,
++	MIX_5G_TSSI_2G_MODE,
++	CLEAN_MODE
++};
++
++typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
++typedef void (*func_iqk)(void *, u8, u8, u8);
++typedef void (*func_lck)(void *);
++typedef void (*func_tssi_dck)(void *, u8);
++typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
++typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
++typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
++typedef void (*func_set_xtal)(void *);
++
++struct txpwrtrack_cfg {
++	u8 swing_table_size_cck;
++	u8 swing_table_size_ofdm;
++	u8 threshold_iqk;
++	u8 threshold_dpk;
++	u8 average_thermal_num;
++	u8 rf_path_count;
++	u32 thermal_reg_addr;
++	func_set_pwr odm_tx_pwr_track_set_pwr;
++	func_iqk do_iqk;
++	func_lck phy_lc_calibrate;
++	func_tssi_dck do_tssi_dck;
++	func_swing get_delta_swing_table;
++	func_swing8814only get_delta_swing_table8814only;
++	func_swing_xtal get_delta_swing_xtal_table;
++	func_set_xtal odm_txxtaltrack_set_xtal;
++};
++
++void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config);
++
++void odm_clear_txpowertracking_state(void *dm_void);
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++void odm_txpowertracking_callback_thermal_meter(void *dm_void);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++void odm_txpowertracking_callback_thermal_meter(void *dm);
++#else
++void odm_txpowertracking_callback_thermal_meter(void *adapter);
++#endif
++
++#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
++void odm_txpowertracking_new_callback_thermal_meter(void *dm_void);
++#endif
++
++#define ODM_TARGET_CHNL_NUM_2G_5G 59
++
++void odm_reset_iqk_result(void *dm_void);
++u8 odm_get_right_chnl_place_for_iqk(u8 chnl);
++
++void phydm_rf_init(void *dm_void);
++void phydm_rf_watchdog(void *dm_void);
++
++#endif /*__HALPHYRF_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_iot.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_iot.c
+new file mode 100644
+index 000000000..441a28868
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_iot.c
+@@ -0,0 +1,652 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#define	CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
++	do {\
++		for (_offset = 0; _offset < _size; _offset++) { \
++			if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
++				if (_offset != 0)\
++					_offset--;\
++				break;\
++			} \
++		}			\
++		if (_offset >= _size)\
++			_offset = _size-1;\
++	} while (0)
++
++void configure_txpower_track(
++	void					*dm_void,
++	struct txpwrtrack_cfg	*config
++)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if RTL8195B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8195B)
++		configure_txpower_track_8195b(config);
++#endif
++#if RTL8710C_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8710C)
++		configure_txpower_track_8710c(config);
++#endif
++#if RTL8721D_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8721D)
++		configure_txpower_track_8721d(config);
++#endif
++
++}
++
++/* **********************************************************************
++ * <20121113, Kordan> This function should be called when tx_agc changed.
++ * Otherwise the previous compensation is gone, because we record the
++ * delta of temperature between two TxPowerTracking watch dogs.
++ *
++ * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
++ * need to call this function.
++ * ********************************************************************** */
++void
++odm_clear_txpowertracking_state(
++	void					*dm_void
++)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	u8			p = 0;
++	struct dm_rf_calibration_struct	*cali_info = &dm->rf_calibrate_info;
++
++	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
++	cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
++	dm->rf_calibrate_info.CCK_index = 0;
++
++	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
++		cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
++		cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
++		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
++
++		cali_info->power_index_offset[p] = 0;
++		cali_info->delta_power_index[p] = 0;
++		cali_info->delta_power_index_last[p] = 0;
++
++		cali_info->absolute_ofdm_swing_idx[p] = 0;
++		cali_info->remnant_ofdm_swing_idx[p] = 0;
++		cali_info->kfree_offset[p] = 0;
++	}
++
++	cali_info->modify_tx_agc_flag_path_a = false;
++	cali_info->modify_tx_agc_flag_path_b = false;
++	cali_info->modify_tx_agc_flag_path_c = false;
++	cali_info->modify_tx_agc_flag_path_d = false;
++	cali_info->remnant_cck_swing_idx = 0;
++	cali_info->thermal_value = rf->eeprom_thermal;
++	cali_info->modify_tx_agc_value_cck = 0;
++	cali_info->modify_tx_agc_value_ofdm = 0;
++}
++
++void
++odm_txpowertracking_callback_thermal_meter(
++	void	*dm_void
++)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
++	struct	dm_iqk_info *iqk_info = &dm->IQK_info;
++
++	u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
++	u8 thermal_value_avg_count = 0;
++	u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
++
++	u8 OFDM_min_index = 0;  /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
++	u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */
++	u8 power_tracking_type = rf->pwt_type;
++	u8 xtal_offset_eanble = 0;
++	s8 thermal_value_temp = 0;
++
++	struct txpwrtrack_cfg	c = {0};
++
++	/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
++	u8 *delta_swing_table_idx_tup_a = NULL;
++	u8 *delta_swing_table_idx_tdown_a = NULL;
++	u8 *delta_swing_table_idx_tup_b = NULL;
++	u8 *delta_swing_table_idx_tdown_b = NULL;
++#if (RTL8721D_SUPPORT == 1)
++	u8 *delta_swing_table_idx_tup_a_cck = NULL;
++	u8 *delta_swing_table_idx_tdown_a_cck = NULL;
++	u8 *delta_swing_table_idx_tup_b_cck = NULL;
++	u8 *delta_swing_table_idx_tdown_b_cck = NULL;
++#endif
++	/*for Xtal Offset by James.Tung*/
++	s8 *delta_swing_table_xtal_up = NULL;
++	s8 *delta_swing_table_xtal_down = NULL;
++
++	/* 4 2. Initialization ( 7 steps in total ) */
++	indexforchannel = odm_get_right_chnl_place_for_iqk(*dm->channel);
++	configure_txpower_track(dm, &c);
++#if (RTL8721D_SUPPORT == 1)
++	(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
++		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b,
++		(u8 **)&delta_swing_table_idx_tup_a_cck, (u8 **)&delta_swing_table_idx_tdown_a_cck,
++		(u8 **)&delta_swing_table_idx_tup_b_cck, (u8 **)&delta_swing_table_idx_tdown_b_cck);
++#else
++	(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
++		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
++#endif
++
++	/*for Xtal Offset*/
++	if (dm->support_ic_type == ODM_RTL8195B ||
++	    dm->support_ic_type == ODM_RTL8721D ||
++	    dm->support_ic_type == ODM_RTL8710C)
++		(*c.get_delta_swing_xtal_table)(dm,
++		 (s8 **)&delta_swing_table_xtal_up,
++		 (s8 **)&delta_swing_table_xtal_down);
++
++	cali_info->txpowertracking_callback_cnt++;	/*cosa add for debug*/
++	cali_info->is_txpowertracking_init = true;
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++	       "===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
++	       cali_info->bb_swing_idx_cck_base,
++	       cali_info->bb_swing_idx_ofdm_base[RF_PATH_A],
++	       cali_info->default_ofdm_index);
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++	       "cali_info->txpowertrack_control = %d, hal_data->eeprom_thermal_meter %d\n",
++	       cali_info->txpowertrack_control, rf->eeprom_thermal);
++
++	if (dm->support_ic_type == ODM_RTL8721D
++		|| dm->support_ic_type == ODM_RTL8710C)
++		thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A,
++						   c.thermal_reg_addr, 0x7e0);
++		/* 0x42: RF Reg[10:5] 8721D */
++	else
++		thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A,
++						   c.thermal_reg_addr, 0xfc00);
++		/* 0x42: RF Reg[15:10] 88E */
++
++	thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++	       "thermal_value_temp(%d) = thermal_value(%d) + power_trim_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
++
++	if (thermal_value_temp > 63)
++		thermal_value = 63;
++	else if (thermal_value_temp < 0)
++		thermal_value = 0;
++	else
++		thermal_value = thermal_value_temp;
++
++	if (!cali_info->txpowertrack_control)
++		return;
++
++	if (rf->eeprom_thermal == 0xff) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", rf->eeprom_thermal);
++		return;
++	}
++#if 0
++	/*4 3. Initialize ThermalValues of rf_calibrate_info*/
++	//if (cali_info->is_reloadtxpowerindex)
++	//	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n");
++#endif
++	/*4 4. Calculate average thermal meter*/
++
++	cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value;
++	cali_info->thermal_value_avg_index++;
++	if (cali_info->thermal_value_avg_index == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
++		cali_info->thermal_value_avg_index = 0;
++
++	for (i = 0; i < c.average_thermal_num; i++) {
++		if (cali_info->thermal_value_avg[i]) {
++			thermal_value_avg += cali_info->thermal_value_avg[i];
++			thermal_value_avg_count++;
++		}
++	}
++
++	if (thermal_value_avg_count) {			  /* Calculate Average thermal_value after average enough times */
++		thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
++		cali_info->thermal_value_delta = thermal_value - rf->eeprom_thermal;
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, rf->eeprom_thermal);
++	}
++
++	/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
++	/* "delta" here is used to determine whether thermal value changes or not. */
++	delta	= (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value);
++	delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
++	delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
++
++	/*4 6. If necessary, do LCK.*/
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
++
++	/* Wait sacn to do LCK by RF Jenyu*/
++	if ((!*dm->is_scan_in_process) && !iqk_info->rfk_forbidden &&
++	    (!*dm->is_tdma)) {
++		/* Delta temperature is equal to or larger than 20 centigrade.*/
++		if (delta_LCK >= c.threshold_iqk) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
++			cali_info->thermal_value_lck = thermal_value;
++
++			/*Use RTLCK, so close power tracking driver LCK*/
++			(*c.phy_lc_calibrate)(dm);
++		}
++	}
++
++	/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
++	if (delta > 0 && cali_info->txpowertrack_control) {
++		/* "delta" here is used to record the absolute value of difference. */
++		delta = thermal_value > rf->eeprom_thermal ? (thermal_value - rf->eeprom_thermal) : (rf->eeprom_thermal - thermal_value);
++
++		if (delta >= TXPWR_TRACK_TABLE_SIZE)
++			delta = TXPWR_TRACK_TABLE_SIZE - 1;
++
++		/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
++		if (thermal_value > rf->eeprom_thermal) {
++			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++				cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
++				switch (p) {
++				case RF_PATH_B:
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					       "delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
++#if (RTL8721D_SUPPORT == 1)
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					       "delta_swing_table_idx_tup_b_cck[%d] = %d\n", delta, delta_swing_table_idx_tup_b_cck[delta]);
++
++					cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_b_cck[delta];
++
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					       "******Temp is higher and cali_info->absolute_cck_swing_idx[RF_PATH_B] = %d\n",
++					       cali_info->absolute_cck_swing_idx[p]);
++#endif
++					cali_info->delta_power_index[p] =
++						delta_swing_table_idx_tup_b
++						[delta];
++					cali_info->absolute_ofdm_swing_idx[p] =
++						delta_swing_table_idx_tup_b
++						[delta];
++					/*Record delta swing for mix mode*/
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					       "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++					break;
++
++				default:
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					       "delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
++#if (RTL8721D_SUPPORT == 1)
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					       "delta_swing_table_idx_tup_a_cck[%d] = %d\n", delta, delta_swing_table_idx_tup_a_cck[delta]);
++
++					cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_a_cck[delta];
++
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					       "******Temp is higher and cali_info->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_cck_swing_idx[p]);
++#endif
++					cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
++					cali_info->absolute_ofdm_swing_idx[p] =
++					delta_swing_table_idx_tup_a[delta];
++					/*Record delta swing*/
++					/*for mix mode power tracking*/
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					       "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++					break;
++				}
++			}
++			/* JJ ADD 20161014 */
++			if (dm->support_ic_type == ODM_RTL8195B ||
++			    dm->support_ic_type == ODM_RTL8721D ||
++			    dm->support_ic_type == ODM_RTL8710C) {
++				/*Save xtal_offset from Xtal table*/
++				cali_info->xtal_offset_last = cali_info->xtal_offset;	/*recording last Xtal offset*/
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]);
++				cali_info->xtal_offset = delta_swing_table_xtal_up[delta];
++				xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset);
++			}
++
++		} else {
++			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++				cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
++
++				switch (p) {
++				case RF_PATH_B:
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					       "delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
++#if (RTL8721D_SUPPORT == 1)
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					       "delta_swing_table_idx_tdown_b_cck[%d] = %d\n", delta, delta_swing_table_idx_tdown_b_cck[delta]);
++
++					cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b_cck[delta];
++
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					       "******Temp is lower and cali_info->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_cck_swing_idx[p]);
++#endif
++					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
++					cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					       "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++					break;
++
++				default:
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					       "delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
++#if (RTL8721D_SUPPORT == 1)
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					       "delta_swing_table_idx_tdown_a_cck[%d] = %d\n", delta, delta_swing_table_idx_tdown_a_cck[delta]);
++
++					cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a_cck[delta];
++
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					       "******Temp is lower and cali_info->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_cck_swing_idx[p]);
++#endif
++					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
++					cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					       "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++					break;
++				}
++			}
++			/* JJ ADD 20161014 */
++
++			if (dm->support_ic_type == ODM_RTL8195B ||
++			    dm->support_ic_type == ODM_RTL8721D ||
++			    dm->support_ic_type == ODM_RTL8710C) {
++				/*Save xtal_offset from Xtal table*/
++				cali_info->xtal_offset_last = cali_info->xtal_offset;	/*recording last Xtal offset*/
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]);
++				cali_info->xtal_offset = delta_swing_table_xtal_down[delta];
++				xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset);
++			}
++		}
++#if 0
++		for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p);
++
++			if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p])		 /*If Thermal value changes but lookup table value still the same*/
++				cali_info->power_index_offset[p] = 0;
++			else
++				cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p];		/*Power index diff between 2 times Power Tracking*/
++
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]);
++
++			cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];
++			cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];
++
++			cali_info->bb_swing_idx_cck = cali_info->CCK_index;
++			cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];
++
++			/*************Print BB Swing base and index Offset*************/
++
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]);
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]);
++
++			/*4 7.1 Handle boundary conditions of index.*/
++
++			if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
++				cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
++			else if (cali_info->OFDM_index[p] <= OFDM_min_index)
++				cali_info->OFDM_index[p] = OFDM_min_index;
++		}
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "\n\n========================================================================================================\n");
++
++		if (cali_info->CCK_index > c.swing_table_size_cck - 1)
++			cali_info->CCK_index = c.swing_table_size_cck - 1;
++		else if (cali_info->CCK_index <= 0)
++			cali_info->CCK_index = 0;
++#endif
++	} else {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n",
++		       cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value);
++
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			cali_info->power_index_offset[p] = 0;
++	}
++#if 0
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++	       "TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
++	       cali_info->CCK_index, cali_info->bb_swing_idx_cck_base);	   /*Print Swing base & current*/
++
++	for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
++		       cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);
++	}
++#endif
++
++#if (RTL8721D_SUPPORT == 1)
++	if (thermal_value != cali_info->thermal_value) {
++		if (thermal_value > rf->eeprom_thermal)
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "Temperature(%d) higher than PG value(%d)\n",
++			       thermal_value, rf->eeprom_thermal);
++		else if (thermal_value < rf->eeprom_thermal)
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			       "Temperature(%d) lower than PG value(%d)\n",
++			       thermal_value, rf->eeprom_thermal);
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "**********Enter POWER Tracking MIX_MODE**********\n");
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p,
++						      indexforchannel);
++
++		/*Record last time Power Tracking result as base.*/
++		cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			cali_info->bb_swing_idx_ofdm_base[p] =
++			cali_info->bb_swing_idx_ofdm[p];
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "cali_info->thermal_value = %d thermal_value= %d\n",
++		       cali_info->thermal_value, thermal_value);
++		/*Record last Power Tracking Thermal value*/
++		cali_info->thermal_value = thermal_value;
++	}
++
++#else
++	if (thermal_value > rf->eeprom_thermal) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "Temperature(%d) higher than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
++
++		if (dm->support_ic_type == ODM_RTL8188E ||
++		    dm->support_ic_type == ODM_RTL8192E ||
++		    dm->support_ic_type == ODM_RTL8821 ||
++		    dm->support_ic_type == ODM_RTL8812 ||
++		    dm->support_ic_type == ODM_RTL8723B ||
++		    dm->support_ic_type == ODM_RTL8814A ||
++		    dm->support_ic_type == ODM_RTL8703B ||
++		    dm->support_ic_type == ODM_RTL8188F ||
++		    dm->support_ic_type == ODM_RTL8822B ||
++		    dm->support_ic_type == ODM_RTL8723D ||
++		    dm->support_ic_type == ODM_RTL8821C ||
++		    dm->support_ic_type == ODM_RTL8710B ||
++		    dm->support_ic_type == ODM_RTL8192F ||
++		    dm->support_ic_type == ODM_RTL8195B ||
++		    dm->support_ic_type == ODM_RTL8710C){
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
++			for (p = RF_PATH_A; p < c.rf_path_count; p++)
++				(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++		} else {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
++			for (p = RF_PATH_A; p < c.rf_path_count; p++)
++				(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
++		}
++	} else {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "Temperature(%d) lower than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
++
++		if (dm->support_ic_type == ODM_RTL8188E ||
++		    dm->support_ic_type == ODM_RTL8192E ||
++		    dm->support_ic_type == ODM_RTL8821 ||
++		    dm->support_ic_type == ODM_RTL8812 ||
++		    dm->support_ic_type == ODM_RTL8723B ||
++		    dm->support_ic_type == ODM_RTL8814A ||
++		    dm->support_ic_type == ODM_RTL8703B ||
++		    dm->support_ic_type == ODM_RTL8188F ||
++		    dm->support_ic_type == ODM_RTL8822B ||
++		    dm->support_ic_type == ODM_RTL8723D ||
++		    dm->support_ic_type == ODM_RTL8821C ||
++		    dm->support_ic_type == ODM_RTL8710B ||
++		    dm->support_ic_type == ODM_RTL8192F ||
++		    dm->support_ic_type == ODM_RTL8195B ||
++		    dm->support_ic_type == ODM_RTL8710C) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
++			for (p = RF_PATH_A; p < c.rf_path_count; p++)
++				(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel);
++		} else {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
++			for (p = RF_PATH_A; p < c.rf_path_count; p++)
++				(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
++		}
++
++		cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;    /*Record last time Power Tracking result as base.*/
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value);
++
++		cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
++	}
++#endif
++	/* JJ ADD 20161014 */
++	if (dm->support_ic_type == ODM_RTL8195B ||
++	    dm->support_ic_type == ODM_RTL8721D ||
++	    dm->support_ic_type == ODM_RTL8710C) {
++		if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (rf->eeprom_thermal != 0xff)) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
++
++			if (thermal_value > rf->eeprom_thermal) {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "Temperature(%d) higher than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
++				(*c.odm_txxtaltrack_set_xtal)(dm);
++			} else {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "Temperature(%d) lower than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
++				(*c.odm_txxtaltrack_set_xtal)(dm);
++			}
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
++		}
++	}
++#if (!RTL8721D_SUPPORT)
++	/* Wait sacn to do IQK by RF Jenyu*/
++	if ((!*dm->is_scan_in_process) && (!iqk_info->rfk_forbidden) && (dm->is_linked || *dm->mp_mode)) {
++		/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
++		if (delta_IQK >= c.threshold_iqk) {
++			cali_info->thermal_value_iqk = thermal_value;
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
++			if (!cali_info->is_iqk_in_progress)
++				(*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
++		}
++	}
++#endif
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n");
++
++	cali_info->tx_powercount = 0;
++}
++
++/* 3============================================================
++ * 3 IQ Calibration
++ * 3============================================================
++ */
++
++void
++odm_reset_iqk_result(
++	void					*dm_void
++)
++{
++	return;
++}
++
++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
++u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
++{
++	u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
++		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
++		36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64,
++		100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122,
++		124, 126, 128, 130, 132, 134, 136, 138, 140,
++		149, 151, 153, 155, 157, 159, 161, 163, 165};
++	u8 place = chnl;
++
++	if (chnl > 14) {
++		for (place = 14; place < sizeof(channel_all); place++) {
++			if (channel_all[place] == chnl)
++				return place - 13;
++		}
++	}
++	return 0;
++}
++#endif
++
++void
++odm_rf_calibrate(struct dm_struct *dm)
++{
++#if (RTL8721D_SUPPORT == 1)
++	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
++
++	if (dm->is_linked && !iqk_info->rfk_forbidden) {
++		if ((*dm->channel != dm->pre_channel) &&
++		    (!*dm->is_scan_in_process)) {
++			dm->pre_channel = *dm->channel;
++			dm->linked_interval = 0;
++		}
++
++		if (dm->linked_interval < 3)
++			dm->linked_interval++;
++
++		if (dm->linked_interval == 2)
++			halrf_rf_k_connect_trigger(dm, 0, SEGMENT_FREE);
++	} else {
++		dm->linked_interval = 0;
++	}
++#endif
++}
++
++void phydm_rf_init(void		*dm_void)
++{
++	struct dm_struct	*dm = (struct dm_struct *)dm_void;
++
++	odm_txpowertracking_init(dm);
++	
++	odm_clear_txpowertracking_state(dm);
++}
++
++void phydm_rf_watchdog(void		*dm_void)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++
++	odm_txpowertracking_check(dm);
++#if (RTL8721D_SUPPORT == 1)
++	odm_rf_calibrate(dm);
++#endif
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_iot.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_iot.h
+new file mode 100644
+index 000000000..8d4395a1f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_iot.h
+@@ -0,0 +1,137 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __HALPHYRF_H__
++#define __HALPHYRF_H__
++
++#include "halrf/halrf_kfree.h"
++
++#if (RTL8821C_SUPPORT == 1)
++	#include "halrf/rtl8821c/halrf_iqk_8821c.h"
++#endif
++
++#if (RTL8195B_SUPPORT == 1)
++//	#include "halrf/rtl8195b/halrf.h"
++	#include "halrf/rtl8195b/halrf_iqk_8195b.h"
++	#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
++	#include "halrf/rtl8195b/halrf_dpk_8195b.h"
++#endif
++
++#if (RTL8710C_SUPPORT == 1)
++//	#include "halrf/rtl8710c/halrf.h"
++	#include "halrf/rtl8710c/halrf_iqk_8710c.h"
++//	#include "halrf/rtl8710c/halrf_txgapk_8710c.h"
++//	#include "halrf/rtl8710c/halrf_dpk_8710c.h"
++#endif
++
++#include "halrf/halrf_powertracking_iot.h"
++
++
++enum spur_cal_method {
++	PLL_RESET,
++	AFE_PHASE_SEL
++};
++
++enum pwrtrack_method {
++	BBSWING,
++	TXAGC,
++	MIX_MODE,
++	TSSI_MODE,
++	MIX_2G_TSSI_5G_MODE,
++	MIX_5G_TSSI_2G_MODE,
++	CLEAN_MODE
++};
++
++typedef void	(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
++typedef void(*func_iqk)(void *, u8, u8, u8);
++typedef void	(*func_lck)(void *);
++#if (RTL8721D_SUPPORT == 1)
++	typedef void	(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **,
++				      u8 **, u8 **, u8 **, u8 **);
++#else
++	typedef void	(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
++#endif
++typedef void	(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
++typedef void(*func_swing_xtal)(void *, s8 **, s8 **);
++typedef void(*func_set_xtal)(void *);
++
++struct txpwrtrack_cfg {
++	u8		swing_table_size_cck;
++	u8		swing_table_size_ofdm;
++	u8		threshold_iqk;
++	u8		threshold_dpk;
++	u8		average_thermal_num;
++	u8		rf_path_count;
++	u32		thermal_reg_addr;
++	func_set_pwr	odm_tx_pwr_track_set_pwr;
++	func_iqk	do_iqk;
++	func_lck		phy_lc_calibrate;
++	func_swing	get_delta_swing_table;
++	func_swing8814only	get_delta_swing_table8814only;
++	func_swing_xtal			get_delta_swing_xtal_table;
++	func_set_xtal			odm_txxtaltrack_set_xtal;
++};
++
++void
++configure_txpower_track(
++	void					*dm_void,
++	struct txpwrtrack_cfg	*config
++);
++
++
++void
++odm_clear_txpowertracking_state(
++	void					*dm_void
++);
++
++void
++odm_txpowertracking_callback_thermal_meter(
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	void					*dm_void
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	void	*dm
++#else
++	void	*adapter
++#endif
++);
++
++
++
++#define ODM_TARGET_CHNL_NUM_2G_5G	59
++
++
++void
++odm_reset_iqk_result(
++	void					*dm_void
++);
++u8
++odm_get_right_chnl_place_for_iqk(
++	u8 chnl
++);
++
++void phydm_rf_init(void					*dm_void);
++void phydm_rf_watchdog(void					*dm_void);
++
++#endif	/*#ifndef __HALPHYRF_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_win.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_win.c
+new file mode 100644
+index 000000000..e6e5d7bea
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_win.c
+@@ -0,0 +1,1091 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#define	CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
++	do {\
++		for (_offset = 0; _offset < _size; _offset++) { \
++			\
++			if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
++				\
++				if (_offset != 0)\
++					_offset--;\
++				break;\
++			} \
++		}			\
++		if (_offset >= _size)\
++			_offset = _size-1;\
++	} while (0)
++
++void configure_txpower_track(
++	struct dm_struct		*dm,
++	struct txpwrtrack_cfg	*config
++)
++{
++#if RTL8192E_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8192E)
++		configure_txpower_track_8192e(config);
++#endif
++#if RTL8821A_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8821)
++		configure_txpower_track_8821a(config);
++#endif
++#if RTL8812A_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8812)
++		configure_txpower_track_8812a(config);
++#endif
++#if RTL8188E_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8188E)
++		configure_txpower_track_8188e(config);
++#endif
++
++#if RTL8188F_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8188F)
++		configure_txpower_track_8188f(config);
++#endif
++
++#if RTL8723B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8723B)
++		configure_txpower_track_8723b(config);
++#endif
++
++#if RTL8814A_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8814A)
++		configure_txpower_track_8814a(config);
++#endif
++
++#if RTL8703B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8703B)
++		configure_txpower_track_8703b(config);
++#endif
++
++#if RTL8822B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8822B)
++		configure_txpower_track_8822b(config);
++#endif
++
++#if RTL8723D_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8723D)
++		configure_txpower_track_8723d(config);
++#endif
++
++/* JJ ADD 20161014 */
++#if RTL8710B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8710B)
++		configure_txpower_track_8710b(config);
++#endif
++
++#if RTL8821C_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8821C)
++		configure_txpower_track_8821c(config);
++#endif
++
++#if RTL8192F_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8192F)
++		configure_txpower_track_8192f(config);
++#endif
++
++#if RTL8822C_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8822C)
++		configure_txpower_track_8822c(config);
++#endif
++
++#if RTL8814B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8814B)
++		configure_txpower_track_8814b(config);
++#endif
++
++
++}
++
++/* **********************************************************************
++ * <20121113, Kordan> This function should be called when tx_agc changed.
++ * Otherwise the previous compensation is gone, because we record the
++ * delta of temperature between two TxPowerTracking watch dogs.
++ *
++ * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
++ * need to call this function.
++ * ********************************************************************** */
++void
++odm_clear_txpowertracking_state(
++	struct dm_struct		*dm
++)
++{
++	PHAL_DATA_TYPE	hal_data = GET_HAL_DATA((PADAPTER)(dm->adapter));
++	u8			p = 0;
++	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
++
++	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
++	cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
++	cali_info->CCK_index = 0;
++
++	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
++		cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
++		cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
++		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
++
++		cali_info->power_index_offset[p] = 0;
++		cali_info->delta_power_index[p] = 0;
++		cali_info->delta_power_index_last[p] = 0;
++
++		cali_info->absolute_ofdm_swing_idx[p] = 0;    /* Initial Mix mode power tracking*/
++		cali_info->remnant_ofdm_swing_idx[p] = 0;
++		cali_info->kfree_offset[p] = 0;
++	}
++
++	cali_info->modify_tx_agc_flag_path_a = false;       /*Initial at Modify Tx Scaling mode*/
++	cali_info->modify_tx_agc_flag_path_b = false;       /*Initial at Modify Tx Scaling mode*/
++	cali_info->modify_tx_agc_flag_path_c = false;       /*Initial at Modify Tx Scaling mode*/
++	cali_info->modify_tx_agc_flag_path_d = false;       /*Initial at Modify Tx Scaling mode*/
++	cali_info->remnant_cck_swing_idx = 0;
++	cali_info->thermal_value = hal_data->eeprom_thermal_meter;
++
++	cali_info->modify_tx_agc_value_cck = 0;			/* modify by Mingzhi.Guo */
++	cali_info->modify_tx_agc_value_ofdm = 0;		/* modify by Mingzhi.Guo */
++
++}
++
++void
++odm_txpowertracking_callback_thermal_meter(
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	struct dm_struct		*dm
++#else
++	void	*adapter
++#endif
++)
++{
++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
++	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct dm_struct		*dm = &hal_data->DM_OutSrc;
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	struct dm_struct		*dm = &hal_data->odmpriv;
++#endif
++#endif
++
++	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
++ 	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++	struct _hal_rf_ *rf = &(dm->rf_table);
++	u8			thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
++	s8			diff_DPK[4] = {0};
++	u8			thermal_value_avg_count = 0;
++	u32			thermal_value_avg = 0, regc80, regcd0, regcd4, regab4, regc88, rege14, reg848,reg838, reg86c;
++
++	u8			OFDM_min_index = 0;  /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
++	u8			indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */
++	u8			power_tracking_type = hal_data->RfPowerTrackingType;
++	u8			xtal_offset_eanble = 0;
++	s8			thermal_value_temp = 0;
++
++	struct txpwrtrack_cfg	c;
++
++	/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
++	u8			*delta_swing_table_idx_tup_a = NULL;
++	u8			*delta_swing_table_idx_tdown_a = NULL;
++	u8			*delta_swing_table_idx_tup_b = NULL;
++	u8			*delta_swing_table_idx_tdown_b = NULL;
++	/*for 8814 add by Yu Chen*/
++	u8			*delta_swing_table_idx_tup_c = NULL;
++	u8			*delta_swing_table_idx_tdown_c = NULL;
++	u8			*delta_swing_table_idx_tup_d = NULL;
++	u8			*delta_swing_table_idx_tdown_d = NULL;
++	/*for Xtal Offset by James.Tung*/
++	s8			*delta_swing_table_xtal_up = NULL;
++	s8			*delta_swing_table_xtal_down = NULL;
++
++	/* 4 2. Initilization ( 7 steps in total ) */
++
++	configure_txpower_track(dm, &c);
++
++	(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
++		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
++
++	if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8814B))	/*for 8814 path C & D*/
++		(*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
++			(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
++	/* JJ ADD 20161014 */
++	if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F))	/*for Xtal Offset*/
++		(*c.get_delta_swing_xtal_table)(dm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down);
++
++
++	cali_info->txpowertracking_callback_cnt++;	/*cosa add for debug*/
++	cali_info->is_txpowertracking_init = true;
++
++	/*cali_info->txpowertrack_control = hal_data->txpowertrack_control;
++	<Kordan> We should keep updating the control variable according to HalData.
++	<Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++#if (MP_DRIVER == 1)
++	cali_info->rega24 = 0x090e1317;
++#endif
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	if (*(dm->mp_mode) == true)
++		cali_info->rega24 = 0x090e1317;
++#endif
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
++		cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		"cali_info->txpowertrack_control=%d,  hal_data->eeprom_thermal_meter %d\n", cali_info->txpowertrack_control,  hal_data->eeprom_thermal_meter);
++	thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
++
++	thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		"thermal_value_temp(%d) = thermal_value(%d) + power_time_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
++
++	if (thermal_value_temp > 63)
++		thermal_value = 63;
++	else if (thermal_value_temp < 0)
++		thermal_value = 0;
++	else
++		thermal_value = thermal_value_temp;
++
++	/*add log by zhao he, check c80/c94/c14/ca0 value*/
++	if (dm->support_ic_type == ODM_RTL8723D) {
++		regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
++		regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);
++		regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);
++		regab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF);
++		RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
++	}
++
++	/* JJ ADD 20161014 */
++	if (dm->support_ic_type == ODM_RTL8710B) {
++		regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
++		regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);
++		regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);
++		regab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF);
++		RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
++	}
++	/* Winnita add 20171205 */
++	if (dm->support_ic_type == ODM_RTL8192F) {
++		regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
++		regc88 = odm_get_bb_reg(dm, R_0xc88, MASKDWORD);
++		regab4 = odm_get_bb_reg(dm, R_0xab4, MASKDWORD);
++		rege14 = odm_get_bb_reg(dm, R_0xe14, MASKDWORD);
++		reg848 = odm_get_bb_reg(dm, R_0x848, MASKDWORD);
++		reg838 = odm_get_bb_reg(dm, R_0x838, MASKDWORD);
++		reg86c = odm_get_bb_reg(dm, R_0x86c, MASKDWORD);
++		RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xc88 = 0x%x 0xab4 = 0x%x 0xe14 = 0x%x\n", regc80, regc88, regab4, rege14);
++		RF_DBG(dm, DBG_RF_IQK, "0x848 = 0x%x 0x838 = 0x%x 0x86c = 0x%x\n", reg848, reg838, reg86c);
++	}
++
++	if (!cali_info->txpowertrack_control)
++		return;
++
++	if (hal_data->eeprom_thermal_meter == 0xff) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", hal_data->eeprom_thermal_meter);
++		return;
++	}
++
++	/*4 3. Initialize ThermalValues of rf_calibrate_info*/
++
++	if (cali_info->is_reloadtxpowerindex)
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n");
++
++	/*4 4. Calculate average thermal meter*/
++
++	cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value;
++	cali_info->thermal_value_avg_index++;
++	if (cali_info->thermal_value_avg_index == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
++		cali_info->thermal_value_avg_index = 0;
++
++	for (i = 0; i < c.average_thermal_num; i++) {
++		if (cali_info->thermal_value_avg[i]) {
++			thermal_value_avg += cali_info->thermal_value_avg[i];
++			thermal_value_avg_count++;
++		}
++	}
++
++	if (thermal_value_avg_count) {            /* Calculate Average thermal_value after average enough times */
++		thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
++		cali_info->thermal_value_delta = thermal_value - hal_data->eeprom_thermal_meter;
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			"AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, hal_data->eeprom_thermal_meter);
++	}
++
++	/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
++
++	/* "delta" here is used to determine whether thermal value changes or not. */
++	delta	= (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value);
++	delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
++	delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
++
++	if (cali_info->thermal_value_iqk == 0xff) {	/*no PG, use thermal value for IQK*/
++		cali_info->thermal_value_iqk = thermal_value;
++		delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no PG, use thermal_value for IQK\n");
++	}
++
++	for (p = RF_PATH_A; p < c.rf_path_count; p++)
++		diff_DPK[p] = (s8)thermal_value - (s8)cali_info->dpk_thermal[p];
++
++	/*4 6. If necessary, do LCK.*/
++
++	if (!(dm->support_ic_type & ODM_RTL8821)) {	/*no PG, do LCK at initial status*/
++		if (cali_info->thermal_value_lck == 0xff) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no PG, do LCK\n");
++			cali_info->thermal_value_lck = thermal_value;
++
++			/*Use RTLCK, so close power tracking driver LCK*/
++			if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
++				if (c.phy_lc_calibrate)
++					(*c.phy_lc_calibrate)(dm);
++			}
++
++			delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
++		}
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
++
++		/* Wait sacn to do LCK by RF Jenyu*/
++		if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
++			/* Delta temperature is equal to or larger than 20 centigrade.*/
++			if (delta_LCK >= c.threshold_iqk) {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
++				cali_info->thermal_value_lck = thermal_value;
++
++				/*Use RTLCK, so close power tracking driver LCK*/
++				if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
++					if (c.phy_lc_calibrate)
++						(*c.phy_lc_calibrate)(dm);
++				}
++			}
++		}
++	}
++
++	/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
++
++	if (delta > 0 && cali_info->txpowertrack_control) {
++		/* "delta" here is used to record the absolute value of differrence. */
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++		delta = thermal_value > hal_data->eeprom_thermal_meter ? (thermal_value - hal_data->eeprom_thermal_meter) : (hal_data->eeprom_thermal_meter - thermal_value);
++#else
++		delta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value);
++#endif
++		if (delta >= TXPWR_TRACK_TABLE_SIZE)
++			delta = TXPWR_TRACK_TABLE_SIZE - 1;
++
++		/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++		if (thermal_value > hal_data->eeprom_thermal_meter) {
++#else
++		if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
++#endif
++
++			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++				cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p];	/*recording poer index offset*/
++				switch (p) {
++				case RF_PATH_B:
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++						"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
++
++					cali_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta];
++					cali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_b[delta];       /*Record delta swing for mix mode power tracking*/
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++						"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++					break;
++
++				case RF_PATH_C:
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++						"delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]);
++
++					cali_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta];
++					cali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_c[delta];       /*Record delta swing for mix mode power tracking*/
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++						"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++					break;
++
++				case RF_PATH_D:
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++						"delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]);
++
++					cali_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta];
++					cali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_d[delta];       /*Record delta swing for mix mode power tracking*/
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++						"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++					break;
++
++				default:
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++						"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
++
++					cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
++					cali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_a[delta];        /*Record delta swing for mix mode power tracking*/
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++						"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++					break;
++				}
++			}
++			/* JJ ADD 20161014 */
++			if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) {
++				/*Save xtal_offset from Xtal table*/
++				cali_info->xtal_offset_last = cali_info->xtal_offset;	/*recording last Xtal offset*/
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					"[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]);
++				cali_info->xtal_offset = delta_swing_table_xtal_up[delta];
++
++				if (cali_info->xtal_offset_last == cali_info->xtal_offset)
++					xtal_offset_eanble = 0;
++				else
++					xtal_offset_eanble = 1;
++			}
++
++		} else {
++			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++				cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p];	/*recording poer index offset*/
++
++				switch (p) {
++				case RF_PATH_B:
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++						"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
++					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
++					cali_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_b[delta];        /*Record delta swing for mix mode power tracking*/
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++						"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++					break;
++
++				case RF_PATH_C:
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++						"delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]);
++					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta];
++					cali_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_c[delta];        /*Record delta swing for mix mode power tracking*/
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++						"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++					break;
++
++				case RF_PATH_D:
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++						"delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]);
++					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta];
++					cali_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_d[delta];        /*Record delta swing for mix mode power tracking*/
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++						"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++					break;
++
++				default:
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++						"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
++					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
++					cali_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_a[delta];        /*Record delta swing for mix mode power tracking*/
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++						"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
++					break;
++				}
++			}
++			/* JJ ADD 20161014 */
++			if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) {
++				/*Save xtal_offset from Xtal table*/
++				cali_info->xtal_offset_last = cali_info->xtal_offset;	/*recording last Xtal offset*/
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					"[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]);
++				cali_info->xtal_offset = delta_swing_table_xtal_down[delta];
++
++				if (cali_info->xtal_offset_last == cali_info->xtal_offset)
++					xtal_offset_eanble = 0;
++				else
++					xtal_offset_eanble = 1;
++			}
++
++		}
++
++		for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p);
++
++			if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p])         /*If Thermal value changes but lookup table value still the same*/
++				cali_info->power_index_offset[p] = 0;
++			else
++				cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p];      /*Power index diff between 2 times Power Tracking*/
++
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]);
++
++			cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];
++			cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];
++
++			cali_info->bb_swing_idx_cck = cali_info->CCK_index;
++			cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];
++
++			/*************Print BB Swing base and index Offset*************/
++
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]);
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]);
++
++			/*4 7.1 Handle boundary conditions of index.*/
++
++			if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
++				cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
++			else if (cali_info->OFDM_index[p] <= OFDM_min_index)
++				cali_info->OFDM_index[p] = OFDM_min_index;
++		}
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			"\n\n========================================================================================================\n");
++
++		if (cali_info->CCK_index > c.swing_table_size_cck - 1)
++			cali_info->CCK_index = c.swing_table_size_cck - 1;
++		else if (cali_info->CCK_index <= 0)
++			cali_info->CCK_index = 0;
++	} else {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			"The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n",
++			cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value);
++
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			cali_info->power_index_offset[p] = 0;
++	}
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
++		cali_info->CCK_index, cali_info->bb_swing_idx_cck_base);       /*Print Swing base & current*/
++
++	for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
++			cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);
++	}
++
++	if (dm->support_ic_type & ODM_RTL8814B)
++		power_tracking_type = TSSI_MODE;
++
++	if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8814B)) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "power_tracking_type=%d\n", power_tracking_type);
++
++		if (power_tracking_type == 0) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
++			for (p = RF_PATH_A; p < c.rf_path_count; p++)
++				(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++		} else if (power_tracking_type == 1) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n");
++			for (p = RF_PATH_A; p < c.rf_path_count; p++)
++				(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_2G_TSSI_5G_MODE, p, 0);
++		} else if (power_tracking_type == 2) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n");
++			for (p = RF_PATH_A; p < c.rf_path_count; p++)
++				(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_5G_TSSI_2G_MODE, p, 0);
++		} else if (power_tracking_type == 3) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI MODE**********\n");
++			for (p = RF_PATH_A; p < c.rf_path_count; p++)
++				(*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0);
++		}
++		cali_info->thermal_value = thermal_value;         /*Record last Power Tracking Thermal value*/
++
++	} else if ((cali_info->power_index_offset[RF_PATH_A] != 0 ||
++		cali_info->power_index_offset[RF_PATH_B] != 0 ||
++		cali_info->power_index_offset[RF_PATH_C] != 0 ||
++		cali_info->power_index_offset[RF_PATH_D] != 0) &&
++		cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {
++		/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
++
++		cali_info->is_tx_power_changed = true;	/*Always true after Tx Power is adjusted by power tracking.*/
++		/*  */
++		/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
++		/* to increase TX power. Otherwise, EVM will be bad. */
++		/*  */
++		/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
++		if (thermal_value > cali_info->thermal_value) {
++			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					"Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
++					p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
++			}
++		} else if (thermal_value < cali_info->thermal_value) {	/*Low temperature*/
++			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					"Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
++					p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
++			}
++		}
++
++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
++		if (thermal_value > hal_data->eeprom_thermal_meter)
++#else
++		if (thermal_value > dm->priv->pmib->dot11RFEntry.ther)
++#endif
++		{
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
++
++			if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
++			    dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
++			    dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
++			    dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B ||
++			    dm->support_ic_type == ODM_RTL8192F) {
++
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
++				for (p = RF_PATH_A; p < c.rf_path_count; p++)
++					(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++			} else {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
++				for (p = RF_PATH_A; p < c.rf_path_count; p++)
++					(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
++			}
++		} else {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
++
++			if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
++			    dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
++			    dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
++			    dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B ||
++				dm->support_ic_type == ODM_RTL8192F) {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
++				for (p = RF_PATH_A; p < c.rf_path_count; p++)
++					(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel);
++			} else {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
++				for (p = RF_PATH_A; p < c.rf_path_count; p++)
++					(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
++			}
++
++		}
++
++		cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;    /*Record last time Power Tracking result as base.*/
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++			"cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value);
++
++		cali_info->thermal_value = thermal_value;         /*Record last Power Tracking Thermal value*/
++
++	}
++
++
++	if (dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D ||
++		dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
++
++		if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {
++
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
++
++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
++			if (thermal_value > hal_data->eeprom_thermal_meter) {
++#else
++			if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
++#endif
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					"Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
++				(*c.odm_txxtaltrack_set_xtal)(dm);
++			} else {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					"Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
++				(*c.odm_txxtaltrack_set_xtal)(dm);
++			}
++		}
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
++	}
++
++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
++
++	/* Wait sacn to do IQK by RF Jenyu*/
++	if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden) && dm->is_linked) {
++		if (!IS_HARDWARE_TYPE_8723B(adapter)) {
++			/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
++			if (delta_IQK >= c.threshold_iqk) {
++				cali_info->thermal_value_iqk = thermal_value;
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
++				if (!cali_info->is_iqk_in_progress)
++					(*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
++			}
++		}
++	}
++	if (cali_info->dpk_thermal[RF_PATH_A] != 0) {
++		if (diff_DPK[RF_PATH_A] >= c.threshold_dpk) {
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
++			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk));
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
++		} else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) {
++			s32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk);
++
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
++			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
++		} else {
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
++			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
++		}
++	}
++	if (cali_info->dpk_thermal[RF_PATH_B] != 0) {
++		if (diff_DPK[RF_PATH_B] >= c.threshold_dpk) {
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
++			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk));
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
++		} else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) {
++			s32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk);
++
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
++			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
++		} else {
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
++			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
++			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
++		}
++	}
++
++#endif
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n");
++
++	cali_info->tx_powercount = 0;
++}
++
++#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
++void
++odm_txpowertracking_new_callback_thermal_meter(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
++ 	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
++	u8 thermal_value[MAX_RF_PATH] = {0}, delta[MAX_RF_PATH] = {0};
++	u8 delta_swing_table_idx_tup[DELTA_SWINGIDX_SIZE] = {0};
++	u8 delta_swing_table_idx_tdown[DELTA_SWINGIDX_SIZE] = {0};
++	u8 delta_LCK = 0, delta_IQK = 0, i = 0, j = 0, p;
++	u8 thermal_value_avg_count[MAX_RF_PATH] = {0};
++	u32 thermal_value_avg[MAX_RF_PATH] = {0};
++	s8 thermal_value_temp[MAX_RF_PATH] = {0};
++	u8 tracking_method = MIX_MODE;
++
++	struct txpwrtrack_cfg c;
++
++	u8 *delta_swing_table_idx_tup_a = NULL;
++	u8 *delta_swing_table_idx_tdown_a = NULL;
++	u8 *delta_swing_table_idx_tup_b = NULL;
++	u8 *delta_swing_table_idx_tdown_b = NULL;
++	u8 *delta_swing_table_idx_tup_c = NULL;
++	u8 *delta_swing_table_idx_tdown_c = NULL;
++	u8 *delta_swing_table_idx_tup_d = NULL;
++	u8 *delta_swing_table_idx_tdown_d = NULL;
++
++	configure_txpower_track(dm, &c);
++
++	(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
++		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
++
++	if (dm->support_ic_type == ODM_RTL8814B) {
++		(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
++			(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
++	}
++
++	cali_info->txpowertracking_callback_cnt++;
++	cali_info->is_txpowertracking_init = true;
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
++		cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		"cali_info->txpowertrack_control=%d, tssi->thermal[RF_PATH_A]=%d tssi->thermal[RF_PATH_B]=%d\n",
++		cali_info->txpowertrack_control,  tssi->thermal[RF_PATH_A], tssi->thermal[RF_PATH_B]);
++
++	if (dm->support_ic_type == ODM_RTL8822C) {
++		for (i = 0; i < c.rf_path_count; i++)
++			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0x7e);	/* 0x42: RF Reg[6:1] Thermal Trim*/
++	} else {
++		for (i = 0; i < c.rf_path_count; i++) {
++			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
++
++			if (dm->support_ic_type == ODM_RTL8814B) {
++				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_multi_thermal_offset(dm, i);
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + multi_thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_multi_thermal_offset(dm, i));
++			} else {
++				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));
++			}
++
++			if (thermal_value_temp[i] > 63)
++				thermal_value[i] = 63;
++			else if (thermal_value_temp[i] < 0)
++				thermal_value[i] = 0;
++			else
++				thermal_value[i] = thermal_value_temp[i];
++		}
++	}
++
++	if ((tssi->thermal[RF_PATH_A] == 0xff || tssi->thermal[RF_PATH_B] == 0xff)) {
++		for (i = 0; i < c.rf_path_count; i++)
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, tssi->thermal[%d] = 0x%x\n",
++				i, tssi->thermal[i]);
++		return;
++	}
++
++	for (j = 0; j < c.rf_path_count; j++) {
++		cali_info->thermal_value_avg_path[j][cali_info->thermal_value_avg_index_path[j]] = thermal_value[j];
++		cali_info->thermal_value_avg_index_path[j]++;
++		if (cali_info->thermal_value_avg_index_path[j] == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
++			cali_info->thermal_value_avg_index_path[j] = 0;
++
++
++		for (i = 0; i < c.average_thermal_num; i++) {
++			if (cali_info->thermal_value_avg_path[j][i]) {
++				thermal_value_avg[j] += cali_info->thermal_value_avg_path[j][i];
++				thermal_value_avg_count[j]++;
++			}
++		}
++
++		if (thermal_value_avg_count[j]) {            /* Calculate Average thermal_value after average enough times */
++			thermal_value[j] = (u8)(thermal_value_avg[j] / thermal_value_avg_count[j]);
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"AVG Thermal Meter = 0x%X, tssi->thermal[%d] = 0x%x\n",
++				thermal_value[j], j, tssi->thermal[j]);
++		}
++		/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
++
++		/* "delta" here is used to determine whether thermal value changes or not. */
++		delta[j] = (thermal_value[j] > cali_info->thermal_value_path[j]) ? (thermal_value[j] - cali_info->thermal_value_path[j]) : (cali_info->thermal_value_path[j] - thermal_value[j]);
++		delta_LCK = (thermal_value[0] > cali_info->thermal_value_lck) ? (thermal_value[0] - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value[0]);
++		delta_IQK = (thermal_value[0] > cali_info->thermal_value_iqk) ? (thermal_value[0] - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value[0]);
++	}
++
++	/*4 6. If necessary, do LCK.*/
++
++	for (i = 0; i < c.rf_path_count; i++)
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta[%d], delta_LCK, delta_IQK) = (%d, %d, %d)\n", i, delta[i], delta_LCK, delta_IQK);
++
++	/* Wait sacn to do LCK by RF Jenyu*/
++	if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
++		/* Delta temperature is equal to or larger than 20 centigrade.*/
++		if (delta_LCK >= c.threshold_iqk) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
++			cali_info->thermal_value_lck = thermal_value[RF_PATH_A];
++
++			/*Use RTLCK, so close power tracking driver LCK*/
++			if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
++				if (c.phy_lc_calibrate)
++					(*c.phy_lc_calibrate)(dm);
++			} else
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do not do LCK\n");
++		}
++	}
++
++	/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
++	for (i = 0; i < c.rf_path_count; i++) {
++		if (i == RF_PATH_B) {
++			odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_b, DELTA_SWINGIDX_SIZE);
++			odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_b, DELTA_SWINGIDX_SIZE);
++		} else if (i == RF_PATH_C) {
++			odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_c, DELTA_SWINGIDX_SIZE);
++			odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_c, DELTA_SWINGIDX_SIZE);
++		} else if (i == RF_PATH_D) {
++			odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_d, DELTA_SWINGIDX_SIZE);
++			odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_d, DELTA_SWINGIDX_SIZE);
++		} else {
++			odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_a, DELTA_SWINGIDX_SIZE);
++			odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_a, DELTA_SWINGIDX_SIZE);
++		}
++
++		cali_info->delta_power_index_last[i] = cali_info->delta_power_index[i];	/*recording poer index offset*/
++		delta[i] = thermal_value[i] > tssi->thermal[i] ? (thermal_value[i] - tssi->thermal[i]) : (tssi->thermal[i] - thermal_value[i]);
++				
++		if (delta[i] >= TXPWR_TRACK_TABLE_SIZE)
++			delta[i] = TXPWR_TRACK_TABLE_SIZE - 1;
++
++		if (thermal_value[i] > tssi->thermal[i]) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"delta_swing_table_idx_tup[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tup[delta[i]], i);
++				
++			cali_info->delta_power_index[i] = delta_swing_table_idx_tup[delta[i]];
++			cali_info->absolute_ofdm_swing_idx[i] =  delta_swing_table_idx_tup[delta[i]];	    /*Record delta swing for mix mode power tracking*/
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"******Temp is higher and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
++		} else {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"delta_swing_table_idx_tdown[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tdown[delta[i]], i);
++			cali_info->delta_power_index[i] = -1 * delta_swing_table_idx_tdown[delta[i]];
++			cali_info->absolute_ofdm_swing_idx[i] = -1 * delta_swing_table_idx_tdown[delta[i]];        /*Record delta swing for mix mode power tracking*/
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"******Temp is lower and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
++		}
++	}
++
++	for (p = RF_PATH_A; p < c.rf_path_count; p++) {	
++		if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p])	     /*If Thermal value changes but lookup table value still the same*/
++			cali_info->power_index_offset[p] = 0;
++		else
++			cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p];	/*Power index diff between 2 times Power Tracking*/
++	}
++
++#if 0
++	if (dm->support_ic_type == ODM_RTL8822C) {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
++	} else {
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
++	}
++#endif
++	if (*dm->mp_mode == 1) {
++		if (cali_info->txpowertrack_control == 1) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
++			tracking_method = MIX_MODE;
++		} else if (cali_info->txpowertrack_control == 3) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
++			tracking_method = TSSI_MODE;
++		}	
++	} else {
++		if (rf->power_track_type >= 0 && rf->power_track_type <= 3) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
++			tracking_method = MIX_MODE;
++		} else if (rf->power_track_type >= 4 && rf->power_track_type <= 7) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
++			tracking_method = TSSI_MODE;
++		}	
++	}
++
++	if (dm->support_ic_type == ODM_RTL8822C || dm->support_ic_type == ODM_RTL8814B)
++		for (p = RF_PATH_A; p < c.rf_path_count; p++)
++			(*c.odm_tx_pwr_track_set_pwr)(dm, tracking_method, p, 0);
++
++	/* Wait sacn to do IQK by RF Jenyu*/
++	if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden) && (dm->is_linked || *dm->mp_mode)) {
++		/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
++		if (delta_IQK >= c.threshold_iqk) {
++			cali_info->thermal_value_iqk = thermal_value[RF_PATH_A];
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
++			/*if (!cali_info->is_iqk_in_progress)*/
++			/*	(*c.do_iqk)(dm, delta_IQK, thermal_value[RF_PATH_A], 8);*/
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do IQK\n");
++
++			/*if (!cali_info->is_iqk_in_progress)*/
++			/*	(*c.do_tssi_dck)(dm, true);*/
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do TSSI DCK\n");
++		}
++	}
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===%s\n", __func__);
++
++	cali_info->tx_powercount = 0;
++}
++#endif
++
++/* 3============================================================
++ * 3 IQ Calibration
++ * 3============================================================ */
++
++void
++odm_reset_iqk_result(
++	struct dm_struct	*dm
++)
++{
++	return;
++}
++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
++u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
++{
++	u8	channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
++		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
++	};
++	u8	place = chnl;
++
++
++	if (chnl > 14) {
++		for (place = 14; place < sizeof(channel_all); place++) {
++			if (channel_all[place] == chnl)
++				return place - 13;
++		}
++	}
++	return 0;
++
++}
++#endif
++
++void
++odm_iq_calibrate(
++	struct dm_struct	*dm
++)
++{
++	void	*adapter = dm->adapter;
++	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
++	
++	RF_DBG(dm, DBG_RF_IQK, "=>%s\n",__FUNCTION__);
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	if (*dm->is_fcs_mode_enable)
++		return;
++#endif
++
++	if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) {
++		RF_DBG(dm, DBG_RF_IQK, "interval=%d ch=%d prech=%d scan=%s\n", dm->linked_interval,
++		       *dm->channel,  dm->pre_channel, *dm->is_scan_in_process == TRUE ? "TRUE":"FALSE");
++
++		if (*dm->channel != dm->pre_channel) {
++			dm->pre_channel = *dm->channel;
++			dm->linked_interval = 0;
++		}
++
++		if ((dm->linked_interval < 3) && (!*dm->is_scan_in_process))
++			dm->linked_interval++;
++
++		if (dm->linked_interval == 2)
++			PHY_IQCalibrate(adapter, false);
++	} else
++		dm->linked_interval = 0;
++
++		RF_DBG(dm, DBG_RF_IQK, "<=%s interval=%d ch=%d prech=%d scan=%s\n", __FUNCTION__, dm->linked_interval,
++			*dm->channel,  dm->pre_channel, *dm->is_scan_in_process == TRUE?"TRUE":"FALSE");
++}
++
++void phydm_rf_init(struct dm_struct		*dm)
++{
++
++	odm_txpowertracking_init(dm);
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	odm_clear_txpowertracking_state(dm);
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++#if (RTL8814A_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814A)
++		phy_iq_calibrate_8814a_init(dm);
++#endif
++#endif
++
++}
++
++void phydm_rf_watchdog(struct dm_struct *dm)
++{
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	FunctionIn(COMP_MLME);
++
++	if (*dm->mp_mode == 1) {
++#if (MP_DRIVER == 1)
++		odm_txpowertracking_check(dm);
++#endif
++	} else {
++		odm_txpowertracking_check(dm);
++
++		if (dm->support_ic_type & (ODM_IC_11AC_SERIES |  ODM_IC_JGR3_SERIES))
++			odm_iq_calibrate(dm);
++	}
++#endif
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_win.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_win.h
+new file mode 100644
+index 000000000..3769d60a9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halphyrf_win.h
+@@ -0,0 +1,132 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __HALPHYRF_H__
++#define __HALPHYRF_H__
++
++#if (RTL8814A_SUPPORT == 1)
++	#include "halrf/rtl8814a/halrf_iqk_8814a.h"
++#endif
++
++#if (RTL8822B_SUPPORT == 1)
++	#include "halrf/rtl8822b/halrf_iqk_8822b.h"
++	#include "../mac/Halmac_type.h"
++#endif
++#include "halrf/halrf_powertracking_win.h"
++#include "halrf/halrf_kfree.h"
++#include "halrf/halrf_txgapcal.h"
++#if (RTL8821C_SUPPORT == 1)
++	#include "halrf/rtl8821c/halrf_iqk_8821c.h"
++#endif
++
++#if (RTL8195B_SUPPORT == 1)
++//	#include "halrf/rtl8195b/halrf.h"
++	#include "halrf/rtl8195b/halrf_iqk_8195b.h"
++	#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
++	#include "halrf/rtl8195b/halrf_dpk_8195b.h"
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++	#include "halrf/rtl8814b/halrf_iqk_8814b.h"
++	#include "halrf/rtl8814b/halrf_txgapk_8814b.h"
++#endif
++
++enum spur_cal_method {
++	PLL_RESET,
++	AFE_PHASE_SEL
++};
++
++enum pwrtrack_method {
++	BBSWING,
++	TXAGC,
++	MIX_MODE,
++	TSSI_MODE,
++	MIX_2G_TSSI_5G_MODE,
++	MIX_5G_TSSI_2G_MODE,
++	CLEAN_MODE
++};
++
++typedef void(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
++typedef void(*func_iqk)(void *, u8, u8, u8);
++typedef void(*func_lck)(void *);
++typedef void(*func_tssi_dck)(void *, u8);
++typedef void(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
++typedef void(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
++typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
++typedef void (*func_set_xtal)(void *);
++typedef void(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
++
++struct txpwrtrack_cfg {
++	u8		swing_table_size_cck;
++	u8		swing_table_size_ofdm;
++	u8		threshold_iqk;
++	u8		threshold_dpk;
++	u8		average_thermal_num;
++	u8		rf_path_count;
++	u32		thermal_reg_addr;
++	func_set_pwr	odm_tx_pwr_track_set_pwr;
++	func_iqk	do_iqk;
++	func_lck	phy_lc_calibrate;
++	func_tssi_dck	do_tssi_dck;
++	func_swing	get_delta_swing_table;
++	func_swing8814only	get_delta_swing_table8814only;
++	func_swing_xtal			get_delta_swing_xtal_table;
++	func_set_xtal			odm_txxtaltrack_set_xtal;
++	func_all_swing	get_delta_all_swing_table;
++};
++
++void
++configure_txpower_track(
++	struct dm_struct		*dm,
++	struct txpwrtrack_cfg	*config
++);
++
++
++void
++odm_clear_txpowertracking_state(
++	struct dm_struct		*dm
++);
++
++void
++odm_txpowertracking_callback_thermal_meter(
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	struct dm_struct		*dm
++#else
++	void	*adapter
++#endif
++);
++
++#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
++void
++odm_txpowertracking_new_callback_thermal_meter(void *dm_void);
++#endif
++
++#define ODM_TARGET_CHNL_NUM_2G_5G	59
++
++
++void
++odm_reset_iqk_result(
++	struct dm_struct	*dm
++);
++u8
++odm_get_right_chnl_place_for_iqk(
++	u8 chnl
++);
++
++void odm_iq_calibrate(struct dm_struct	*dm);
++void phydm_rf_init(struct dm_struct		*dm);
++void phydm_rf_watchdog(struct dm_struct		*dm);
++
++#endif	/*#ifndef __HALPHYRF_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf.c
+new file mode 100644
+index 000000000..e851c492a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf.c
+@@ -0,0 +1,4065 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ * ************************************************************
++ */
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
++	RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
++	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
++	RTL8812F_SUPPORT == 1 || RTL8710C_SUPPORT == 1 ||\
++	RTL8197G_SUPPORT == 1)
++
++void _iqk_check_if_reload(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++
++	iqk_info->is_reload = (boolean)odm_get_bb_reg(dm, R_0x1bf0, BIT(16));
++}
++
++void _iqk_page_switch(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type == ODM_RTL8821C)
++		odm_write_4byte(dm, 0x1b00, 0xf8000008);
++	else
++		odm_write_4byte(dm, 0x1b00, 0xf800000a);
++}
++
++u32 halrf_psd_log2base(u32 val)
++{
++	u8 j;
++	u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
++	u32 result, val_fractiond_b = 0;
++	u32 table_fraction[21] = {
++		0, 432, 332, 274, 232, 200, 174, 151, 132, 115,
++		100, 86, 74, 62, 51, 42, 32, 23, 15, 7, 0};
++
++	if (val == 0)
++		return 0;
++
++	tmp = val;
++
++	while (1) {
++		if (tmp == 1)
++			break;
++
++		tmp = (tmp >> 1);
++		shiftcount++;
++	}
++
++	val_integerd_b = shiftcount + 1;
++
++	tmp2 = 1;
++	for (j = 1; j <= val_integerd_b; j++)
++		tmp2 = tmp2 * 2;
++
++	tmp = (val * 100) / tmp2;
++	tindex = tmp / 5;
++
++	if (tindex > 20)
++		tindex = 20;
++
++	val_fractiond_b = table_fraction[tindex];
++
++	result = val_integerd_b * 100 - val_fractiond_b;
++
++	return result;
++}
++#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
++	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
++void halrf_iqk_xym_enable(struct dm_struct *dm, u8 xym_enable)
++{
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++
++	if (xym_enable == 0)
++		iqk_info->xym_read = false;
++	else
++		iqk_info->xym_read = true;
++
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s %s\n", "xym_read = ",
++	       (iqk_info->xym_read ? "true" : "false"));
++}
++
++/*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/
++void halrf_iqk_xym_read(void *dm_void, u8 path, u8 xym_type)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++	u8 i, start, num;
++	u32 tmp1, tmp2;
++
++	if (!iqk_info->xym_read)
++		return;
++
++	if (*dm->band_width == 0) {
++		start = 3;
++		num = 4;
++	} else if (*dm->band_width == 1) {
++		start = 2;
++		num = 6;
++	} else {
++		start = 0;
++		num = 10;
++	}
++
++	odm_write_4byte(dm, 0x1b00, 0xf8000008);
++	tmp1 = odm_read_4byte(dm, 0x1b1c);
++	odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
++
++	odm_write_4byte(dm, 0x1b00, 0xf800000a);
++	tmp2 = odm_read_4byte(dm, 0x1b1c);
++	odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
++
++	for (path = 0; path < 2; path++) {
++		odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
++		switch (xym_type) {
++		case 0:
++			for (i = 0; i < num; i++) {
++				odm_write_4byte(dm, 0x1b14, 0xe6 + start + i);
++				odm_write_4byte(dm, 0x1b14, 0x0);
++				iqk_info->rx_xym[path][i] =
++						odm_read_4byte(dm, 0x1b38);
++			}
++			break;
++		case 1:
++			for (i = 0; i < num; i++) {
++				odm_write_4byte(dm, 0x1b14, 0xe6 + start + i);
++				odm_write_4byte(dm, 0x1b14, 0x0);
++				iqk_info->tx_xym[path][i] =
++						odm_read_4byte(dm, 0x1b38);
++			}
++			break;
++		case 2:
++			for (i = 0; i < 6; i++) {
++				odm_write_4byte(dm, 0x1b14, 0xe0 + i);
++				odm_write_4byte(dm, 0x1b14, 0x0);
++				iqk_info->gs1_xym[path][i] =
++						odm_read_4byte(dm, 0x1b38);
++			}
++			break;
++		case 3:
++			for (i = 0; i < 6; i++) {
++				odm_write_4byte(dm, 0x1b14, 0xe0 + i);
++				odm_write_4byte(dm, 0x1b14, 0x0);
++				iqk_info->gs2_xym[path][i] =
++						odm_read_4byte(dm, 0x1b38);
++			}
++			break;
++		case 4:
++			for (i = 0; i < 6; i++) {
++				odm_write_4byte(dm, 0x1b14, 0xe0 + i);
++				odm_write_4byte(dm, 0x1b14, 0x0);
++				iqk_info->rxk1_xym[path][i] =
++						odm_read_4byte(dm, 0x1b38);
++			}
++			break;
++		}
++		odm_write_4byte(dm, 0x1b38, 0x20000000);
++		odm_write_4byte(dm, 0x1b00, 0xf8000008);
++		odm_write_4byte(dm, 0x1b1c, tmp1);
++		odm_write_4byte(dm, 0x1b00, 0xf800000a);
++		odm_write_4byte(dm, 0x1b1c, tmp2);
++		_iqk_page_switch(dm);
++	}
++}
++
++/*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/
++void halrf_iqk_xym_show(struct dm_struct *dm, u8 xym_type)
++{
++	u8 num, path, path_num, i;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++
++	if (dm->rf_type == RF_1T1R)
++		path_num = 0x1;
++	else if (dm->rf_type == RF_2T2R)
++		path_num = 0x2;
++	else
++		path_num = 0x4;
++
++	if (*dm->band_width == CHANNEL_WIDTH_20)
++		num = 4;
++	else if (*dm->band_width == CHANNEL_WIDTH_40)
++		num = 6;
++	else
++		num = 10;
++
++	for (path = 0; path < path_num; path++) {
++		switch (xym_type) {
++		case 0:
++			for (i = 0; i < num; i++)
++				RF_DBG(dm, DBG_RF_IQK,
++				       "[IQK]%-20s %-2d: 0x%x\n",
++				       (path == 0) ? "PATH A RX-XYM " :
++				       "PATH B RX-XYM", i,
++				       iqk_info->rx_xym[path][i]);
++			break;
++		case 1:
++			for (i = 0; i < num; i++)
++				RF_DBG(dm, DBG_RF_IQK,
++				       "[IQK]%-20s %-2d: 0x%x\n",
++				       (path == 0) ? "PATH A TX-XYM " :
++				       "PATH B TX-XYM", i,
++				       iqk_info->tx_xym[path][i]);
++			break;
++		case 2:
++			for (i = 0; i < 6; i++)
++				RF_DBG(dm, DBG_RF_IQK,
++				       "[IQK]%-20s %-2d: 0x%x\n",
++				       (path == 0) ? "PATH A GS1-XYM " :
++				       "PATH B GS1-XYM", i,
++				       iqk_info->gs1_xym[path][i]);
++			break;
++		case 3:
++			for (i = 0; i < 6; i++)
++				RF_DBG(dm, DBG_RF_IQK,
++				       "[IQK]%-20s %-2d: 0x%x\n",
++				       (path == 0) ? "PATH A GS2-XYM " :
++				       "PATH B GS2-XYM", i,
++				       iqk_info->gs2_xym[path][i]);
++			break;
++		case 4:
++			for (i = 0; i < 6; i++)
++				RF_DBG(dm, DBG_RF_IQK,
++				       "[IQK]%-20s %-2d: 0x%x\n",
++				       (path == 0) ? "PATH A RXK1-XYM " :
++				       "PATH B RXK1-XYM", i,
++				       iqk_info->rxk1_xym[path][i]);
++			break;
++		}
++	}
++}
++
++void halrf_iqk_xym_dump(void *dm_void)
++{
++	u32 tmp1, tmp2;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	odm_write_4byte(dm, 0x1b00, 0xf8000008);
++	tmp1 = odm_read_4byte(dm, 0x1b1c);
++	odm_write_4byte(dm, 0x1b00, 0xf800000a);
++	tmp2 = odm_read_4byte(dm, 0x1b1c);
++#if 0
++	/*halrf_iqk_xym_read(dm, xym_type);*/
++#endif
++	odm_write_4byte(dm, 0x1b00, 0xf8000008);
++	odm_write_4byte(dm, 0x1b1c, tmp1);
++	odm_write_4byte(dm, 0x1b00, 0xf800000a);
++	odm_write_4byte(dm, 0x1b1c, tmp2);
++	_iqk_page_switch(dm);
++}
++#endif
++void halrf_iqk_info_dump(void *dm_void, u32 *_used, char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 rf_path, j, reload_iqk = 0;
++	u32 tmp;
++	/*two channel, PATH, TX/RX, 0:pass 1 :fail*/
++	boolean iqk_result[2][NUM][2];
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++
++	if (!(dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)))
++		return;
++
++	/* IQK INFO */
++	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s\n",
++		 "% IQK Info %");
++	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s\n",
++		 (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" :
++		 "Driver-IQK");
++
++	reload_iqk = (u8)odm_get_bb_reg(dm, R_0x1bf0, BIT(16));
++	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
++		 "reload", (reload_iqk) ? "True" : "False");
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
++		 "rfk_forbidden", (iqk_info->rfk_forbidden) ? "True" : "False");
++#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
++	RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
++	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
++	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
++		 "segment_iqk", (iqk_info->segment_iqk) ? "True" : "False");
++#endif
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s:%d %d\n",
++		 "iqk count / fail count", dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %d\n",
++		 "channel", *dm->channel);
++
++	if (*dm->band_width == CHANNEL_WIDTH_20)
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "%-20s: %s\n", "bandwidth", "BW_20");
++	else if (*dm->band_width == CHANNEL_WIDTH_40)
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "%-20s: %s\n", "bandwidth", "BW_40");
++	else if (*dm->band_width == CHANNEL_WIDTH_80)
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "%-20s: %s\n", "bandwidth", "BW_80");
++	else if (*dm->band_width == CHANNEL_WIDTH_160)
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "%-20s: %s\n", "bandwidth", "BW_160");
++	else if (*dm->band_width == CHANNEL_WIDTH_80_80)
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "%-20s: %s\n", "bandwidth", "BW_80_80");
++	else
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "%-20s: %s\n", "bandwidth", "BW_UNKNOWN");
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "%-20s: %llu %s\n", "progressing_time",
++		 dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)");
++
++	tmp = odm_read_4byte(dm, 0x1bf0);
++	for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)
++		for (j = 0; j < 2; j++)
++			iqk_result[0][rf_path][j] = (boolean)
++			(tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))));
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "%-20s: 0x%08x\n", "Reg0x1bf0", tmp);
++	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
++		 "PATH_A-Tx result",
++		 (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass");
++	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
++		 "PATH_A-Rx result",
++		 (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass");
++#if (RTL8822B_SUPPORT == 1)
++	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
++		 "PATH_B-Tx result",
++		 (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass");
++	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
++		 "PATH_B-Rx result",
++		 (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass");
++#endif
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void halrf_get_fw_version(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	rf->fw_ver = (dm->fw_version << 16) | dm->fw_sub_version;
++}
++
++void halrf_iqk_dbg(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 rf_path, j;
++	u32 tmp;
++	/*two channel, PATH, TX/RX, 0:pass 1 :fail*/
++	boolean iqk_result[2][NUM][2];
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	/* IQK INFO */
++	RF_DBG(dm, DBG_RF_IQK, "%-20s\n", "====== IQK Info ======");
++
++	RF_DBG(dm, DBG_RF_IQK, "%-20s\n",
++	       (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" :
++	       "Driver-IQK");
++
++	if (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) {
++		halrf_get_fw_version(dm);
++		RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%x\n", "FW_VER", rf->fw_ver);
++	} else {
++		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "IQK_VER", HALRF_IQK_VER);
++	}
++
++	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "reload",
++	       (iqk_info->is_reload) ? "True" : "False");
++
++	RF_DBG(dm, DBG_RF_IQK, "%-20s: %d %d\n", "iqk count / fail count",
++	       dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
++
++	RF_DBG(dm, DBG_RF_IQK, "%-20s: %d\n", "channel", *dm->channel);
++
++	if (*dm->band_width == CHANNEL_WIDTH_20)
++		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_20");
++	else if (*dm->band_width == CHANNEL_WIDTH_40)
++		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_40");
++	else if (*dm->band_width == CHANNEL_WIDTH_80)
++		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_80");
++	else if (*dm->band_width == CHANNEL_WIDTH_160)
++		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_160");
++	else if (*dm->band_width == CHANNEL_WIDTH_80_80)
++		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_80_80");
++	else
++		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth",
++		       "BW_UNKNOWN");
++#if 0
++/*
++ *	RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n",
++ *	       "progressing_time",
++ *	       dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)");
++ */
++#endif
++	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "rfk_forbidden",
++	       (iqk_info->rfk_forbidden) ? "True" : "False");
++#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
++	RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
++	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
++	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "segment_iqk",
++	       (iqk_info->segment_iqk) ? "True" : "False");
++#endif
++
++	RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n", "progressing_time",
++	       dm->rf_calibrate_info.iqk_progressing_time, "(ms)");
++
++	tmp = odm_read_4byte(dm, 0x1bf0);
++	for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)
++		for (j = 0; j < 2; j++)
++			iqk_result[0][rf_path][j] = (boolean)
++			(tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))));
++
++	RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%08x\n", "Reg0x1bf0", tmp);
++	RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%08x\n", "Reg0x1be8",
++	       odm_read_4byte(dm, 0x1be8));
++	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_A-Tx result",
++	       (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass");
++	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_A-Rx result",
++	       (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass");
++#if (RTL8822B_SUPPORT == 1)
++	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_B-Tx result",
++	       (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass");
++	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_B-Rx result",
++	       (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass");
++#endif
++}
++
++void halrf_lck_dbg(struct dm_struct *dm)
++{
++	RF_DBG(dm, DBG_RF_IQK, "%-20s\n", "====== LCK Info ======");
++#if 0
++	/*RF_DBG(dm, DBG_RF_IQK, "%-20s\n",
++	 *	 (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "LCK" : "RTK"));
++	 */
++#endif
++	RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n", "progressing_time",
++	       dm->rf_calibrate_info.lck_progressing_time, "(ms)");
++}
++void phydm_get_iqk_cfir(void *dm_void, u8 idx, u8 path, boolean debug)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	switch (dm->support_ic_type) {
++#if (RTL8822B_SUPPORT == 1)
++	case ODM_RTL8822B:
++		phy_get_iqk_cfir_8822b(dm, idx, path, debug);
++	break;
++#endif
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:		
++		phy_get_iqk_cfir_8822c(dm, idx, path, debug);
++	break;
++#endif
++#if (RTL8814B_SUPPORT == 1)
++	case ODM_RTL8814B:		
++		phy_get_iqk_cfir_8814b(dm, idx, path, debug);
++	break;
++#endif
++	default:
++	break;
++	}
++}
++
++
++void halrf_iqk_dbg_cfir_backup(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++	u8 path, idx, i;
++
++	switch (dm->support_ic_type) {
++#if (RTL8822B_SUPPORT == 1)
++		case ODM_RTL8822B:
++			phy_iqk_dbg_cfir_backup_8822b(dm);
++				break;
++#endif
++#if (RTL8822C_SUPPORT == 1)
++		case ODM_RTL8822C:			
++			phy_iqk_dbg_cfir_backup_8822c(dm);
++				break;
++#endif
++#if (RTL8814B_SUPPORT == 1)
++		case ODM_RTL8814B:			
++			phy_iqk_dbg_cfir_backup_8814b(dm);
++				break;
++#endif
++	default:
++	break;
++	}
++
++}
++
++void halrf_iqk_dbg_cfir_backup_update(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_iqk_info *iqk = &dm->IQK_info;
++	u8 i, path, idx;
++	u32 bmask13_12 = BIT(13) | BIT(12);
++	u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
++	u32 data;
++
++	switch (dm->support_ic_type) {
++#if (RTL8822B_SUPPORT == 1)
++	case ODM_RTL8822B:
++		phy_iqk_dbg_cfir_backup_update_8822b(dm);
++		break;
++#endif
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:		
++		phy_iqk_dbg_cfir_backup_update_8822c(dm);
++		break;
++#endif
++	default:
++	break;
++	}
++}
++
++void halrf_iqk_dbg_cfir_reload(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_iqk_info *iqk = &dm->IQK_info;
++	u8 i, path, idx;
++	u32 bmask13_12 = BIT(13) | BIT(12);
++	u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
++	u32 data;
++	
++	switch (dm->support_ic_type) {
++#if (RTL8822B_SUPPORT == 1)
++	case ODM_RTL8822B:
++		phy_iqk_dbg_cfir_reload_8822b(dm);
++	break;
++#endif
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:		
++		phy_iqk_dbg_cfir_reload_8822c(dm);
++		break;
++#endif
++	default:
++	break;
++	}
++}
++
++void halrf_iqk_dbg_cfir_write(void *dm_void, u8 type, u32 path, u32 idx,
++			      u32 i, u32 data)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++
++	switch (dm->support_ic_type) {
++#if (RTL8822B_SUPPORT == 1)
++	case ODM_RTL8822B:
++		phy_iqk_dbg_cfir_write_8822b(dm, type, path, idx, i, data);
++	break;
++#endif
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:		
++		phy_iqk_dbg_cfir_write_8822c(dm, type, path, idx, i, data);
++		break;
++#endif
++	default:
++	break;
++	}
++}
++
++void halrf_iqk_dbg_cfir_backup_show(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++	u8 path, idx, i;
++
++	switch (dm->support_ic_type) {
++#if (RTL8822B_SUPPORT == 1)
++	case ODM_RTL8822B:
++		phy_iqk_dbg_cfir_backup_8822b(dm);
++	break;
++#endif
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:		
++		phy_iqk_dbg_cfir_backup_8822c(dm);
++		break;
++#endif
++	default:
++	break;
++	}
++}
++
++void halrf_do_imr_test(void *dm_void, u8 flag_imr_test)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (flag_imr_test != 0x0)
++		switch (dm->support_ic_type) {
++#if (RTL8822B_SUPPORT == 1)
++		case ODM_RTL8822B:
++			do_imr_test_8822b(dm);
++			break;
++#endif
++#if (RTL8821C_SUPPORT == 1)
++		case ODM_RTL8821C:
++			do_imr_test_8821c(dm);
++			break;
++#endif
++		default:
++			break;
++		}
++}
++
++#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
++void halrf_iqk_debug(void *dm_void, u32 *const dm_value, u32 *_used,
++		     char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if 0
++	/*dm_value[0]=0x0: backup from SRAM & show*/
++	/*dm_value[0]=0x1: write backup CFIR to SRAM*/
++	/*dm_value[0]=0x2: reload default CFIR to SRAM*/
++	/*dm_value[0]=0x3: show backup*/
++	/*dm_value[0]=0x10: write backup CFIR real part*/
++	/*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/
++	/*dm_value[0]=0x11: write backup CFIR imag*/
++	/*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/
++	/*dm_value[0]=0x20 :xym_read enable*/
++	/*--> dm_value[1]:0:disable, 1:enable*/
++	/*if dm_value[0]=0x20 = enable, */
++	/*0x1:show rx_sym; 0x2: tx_xym; 0x3:gs1_xym; 0x4:gs2_sym; 0x5:rxk1_xym*/
++#endif
++	if (dm_value[0] == 0x0)
++		halrf_iqk_dbg_cfir_backup(dm);
++	else if (dm_value[0] == 0x1)
++		halrf_iqk_dbg_cfir_backup_update(dm);
++	else if (dm_value[0] == 0x2)
++		halrf_iqk_dbg_cfir_reload(dm);
++	else if (dm_value[0] == 0x3)
++		halrf_iqk_dbg_cfir_backup_show(dm);
++	else if (dm_value[0] == 0x10)
++		halrf_iqk_dbg_cfir_write(dm, 0, dm_value[1], dm_value[2],
++					 dm_value[3], dm_value[4]);
++	else if (dm_value[0] == 0x11)
++		halrf_iqk_dbg_cfir_write(dm, 1, dm_value[1], dm_value[2],
++					 dm_value[3], dm_value[4]);
++	else if (dm_value[0] == 0x20)
++		halrf_iqk_xym_enable(dm, (u8)dm_value[1]);
++	else if (dm_value[0] == 0x21)
++		halrf_iqk_xym_show(dm, (u8)dm_value[1]);
++	else if (dm_value[0] == 0x30)
++		halrf_do_imr_test(dm, (u8)dm_value[1]);
++}
++#endif
++
++void halrf_iqk_hwtx_check(void *dm_void, boolean is_check)
++{
++#if 0
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++	u32 tmp_b04;
++
++	if (is_check) {
++		iqk_info->is_hwtx = (boolean)odm_get_bb_reg(dm, R_0xb00, BIT(8));
++	} else {
++		if (iqk_info->is_hwtx) {
++			tmp_b04 = odm_read_4byte(dm, 0xb04);
++			odm_set_bb_reg(dm, R_0xb04, BIT(3) | BIT(2), 0x0);
++			odm_write_4byte(dm, 0xb04, tmp_b04);
++		}
++	}
++#endif
++}
++#endif
++
++u8 halrf_match_iqk_version(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	u32 iqk_version = 0;
++	char temp[10] = {0};
++
++	odm_move_memory(dm, temp, HALRF_IQK_VER, sizeof(temp));
++	PHYDM_SSCANF(temp + 2, DCMD_HEX, &iqk_version);
++
++	if (dm->support_ic_type == ODM_RTL8822B) {
++		if (iqk_version >= 0x24 && (odm_get_hw_img_version(dm) >= 72))
++			return 1;
++		else if ((iqk_version <= 0x23) &&
++			 (odm_get_hw_img_version(dm) <= 71))
++			return 1;
++		else
++			return 0;
++	}
++
++	if (dm->support_ic_type == ODM_RTL8821C) {
++		if (iqk_version >= 0x18 && (odm_get_hw_img_version(dm) >= 37))
++			return 1;
++		else
++			return 0;
++	}
++
++	return 1;
++}
++
++void halrf_rf_lna_setting(void *dm_void, enum halrf_lna_set type)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	switch (dm->support_ic_type) {
++#if (RTL8188E_SUPPORT == 1)
++	case ODM_RTL8188E:
++		halrf_rf_lna_setting_8188e(dm, type);
++		break;
++#endif
++#if (RTL8192E_SUPPORT == 1)
++	case ODM_RTL8192E:
++		halrf_rf_lna_setting_8192e(dm, type);
++		break;
++#endif
++#if (RTL8192F_SUPPORT == 1)
++	case ODM_RTL8192F:
++		halrf_rf_lna_setting_8192f(dm, type);
++		break;
++#endif
++
++#if (RTL8723B_SUPPORT == 1)
++	case ODM_RTL8723B:
++		halrf_rf_lna_setting_8723b(dm, type);
++		break;
++#endif
++#if (RTL8812A_SUPPORT == 1)
++	case ODM_RTL8812:
++		halrf_rf_lna_setting_8812a(dm, type);
++		break;
++#endif
++#if ((RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1))
++	case ODM_RTL8881A:
++	case ODM_RTL8821:
++		halrf_rf_lna_setting_8821a(dm, type);
++		break;
++#endif
++#if (RTL8822B_SUPPORT == 1)
++	case ODM_RTL8822B:
++		halrf_rf_lna_setting_8822b(dm_void, type);
++		break;
++#endif
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:
++		halrf_rf_lna_setting_8822c(dm_void, type);
++		break;
++#endif
++#if (RTL8812F_SUPPORT == 1)
++	case ODM_RTL8812F:
++		halrf_rf_lna_setting_8812f(dm_void, type);
++		break;
++#endif
++#if (RTL8821C_SUPPORT == 1)
++	case ODM_RTL8821C:
++		halrf_rf_lna_setting_8821c(dm_void, type);
++		break;
++#endif
++#if (RTL8814B_SUPPORT == 1)
++		case ODM_RTL8814B:
++			break;
++#endif
++	default:
++		break;
++	}
++}
++
++void halrf_support_ability_debug(void *dm_void, char input[][16], u32 *_used,
++				 char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	u32 dm_value[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 i;
++
++	for (i = 0; i < 5; i++)
++		if (input[i + 1])
++			PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]);
++
++	if (dm_value[0] == 100) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\n[RF Supportability]\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "00. (( %s ))Power Tracking\n",
++			 ((rf->rf_supportability & HAL_RF_TX_PWR_TRACK) ?
++			 ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "01. (( %s ))IQK\n",
++			 ((rf->rf_supportability & HAL_RF_IQK) ? ("V") :
++			 (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "02. (( %s ))LCK\n",
++			 ((rf->rf_supportability & HAL_RF_LCK) ? ("V") :
++			 (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "03. (( %s ))DPK\n",
++			 ((rf->rf_supportability & HAL_RF_DPK) ? ("V") :
++			 (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "04. (( %s ))HAL_RF_TXGAPK\n",
++			 ((rf->rf_supportability & HAL_RF_TXGAPK) ? ("V") :
++			 (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "05. (( %s ))HAL_RF_DACK\n",
++			 ((rf->rf_supportability & HAL_RF_DACK) ? ("V") :
++			 (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "06. (( %s ))DPK_TRACK\n",
++			 ((rf->rf_supportability & HAL_RF_DPK_TRACK) ? ("V") :
++			 (".")));
++#ifdef CONFIG_2G_BAND_SHIFT
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "07. (( %s ))HAL_2GBAND_SHIFT\n",
++			 ((rf->rf_supportability & HAL_2GBAND_SHIFT) ? ("V") :
++			 (".")));
++#endif
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "08. (( %s ))HAL_RF_RXDCK\n",
++			 ((rf->rf_supportability & HAL_RF_RXDCK) ? ("V") :
++			 (".")));
++
++	} else {
++		if (dm_value[1] == 1) /* enable */
++			rf->rf_supportability |= BIT(dm_value[0]);
++		else if (dm_value[1] == 2) /* disable */
++			rf->rf_supportability &= ~(BIT(dm_value[0]));
++		else
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[Warning!!!]  1:enable,  2:disable\n");
++	}
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\nCurr-RF_supportability =  0x%x\n\n", rf->rf_supportability);
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++#ifdef CONFIG_2G_BAND_SHIFT
++void halrf_support_band_shift_debug(void *dm_void, char input[][16], u32 *_used,
++				    char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	//u32 band_value[2] = {00};
++	u32 dm_value[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 i;
++
++#if (RTL8192F_SUPPORT == 1)
++	for (i = 0; i < 7; i++)
++		if (input[i + 1])
++			PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]);
++
++	if (!(rf->rf_supportability & HAL_2GBAND_SHIFT)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\nCurr-RF_supportability[07. (( . ))HAL_2GBAND_SHIFT]\nNo RF Band Shift,default: 2.4G!\n");
++	} else {
++		if (dm_value[0] == 01) {
++			rf->rf_shift_band = HAL_RF_2P3;
++			halrf_lck_trigger(dm);
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\n[rf_shift_band] = %d\nRF Band Shift to 2.3G!\n",
++				 rf->rf_shift_band);
++		} else if (dm_value[0] == 02) {
++			rf->rf_shift_band = HAL_RF_2P5;
++			halrf_lck_trigger(dm);
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\n[rf_shift_band] = %d\nRF Band Shift to 2.5G!\n",
++				 rf->rf_shift_band);
++		} else {
++			rf->rf_shift_band = HAL_RF_2P4;
++			halrf_lck_trigger(dm);
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\n[rf_shift_band] = %d\nNo RF Band Shift,default: 2.4G!\n",
++				 rf->rf_shift_band);
++		}
++	}
++	*_used = used;
++	*_out_len = out_len;
++#endif
++}
++#endif
++
++void halrf_cmn_info_init(void *dm_void, enum halrf_cmninfo_init cmn_info,
++			 u32 value)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	switch (cmn_info) {
++	case HALRF_CMNINFO_EEPROM_THERMAL_VALUE:
++		rf->eeprom_thermal = (u8)value;
++		break;
++	case HALRF_CMNINFO_PWT_TYPE:
++		rf->pwt_type = (u8)value;
++		break;
++	case HALRF_CMNINFO_MP_POWER_TRACKING_TYPE:
++		rf->mp_pwt_type = (u8)value;
++		break;
++	default:
++		break;
++	}
++}
++
++void halrf_cmn_info_hook(void *dm_void, enum halrf_cmninfo_hook cmn_info,
++			 void *value)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	switch (cmn_info) {
++	case HALRF_CMNINFO_CON_TX:
++		rf->is_con_tx = (boolean *)value;
++		break;
++	case HALRF_CMNINFO_SINGLE_TONE:
++		rf->is_single_tone = (boolean *)value;
++		break;
++	case HALRF_CMNINFO_CARRIER_SUPPRESSION:
++		rf->is_carrier_suppresion = (boolean *)value;
++		break;
++	case HALRF_CMNINFO_MP_RATE_INDEX:
++		rf->mp_rate_index = (u8 *)value;
++		break;
++	case HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY:
++		rf->manual_rf_supportability = (u32 *)value;
++		break;
++	default:
++		/*do nothing*/
++		break;
++	}
++}
++
++void halrf_cmn_info_set(void *dm_void, u32 cmn_info, u64 value)
++{
++	/* This init variable may be changed in run time. */
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	switch (cmn_info) {
++	case HALRF_CMNINFO_ABILITY:
++		rf->rf_supportability = (u32)value;
++		break;
++
++	case HALRF_CMNINFO_DPK_EN:
++		rf->dpk_en = (u8)value;
++		break;
++	case HALRF_CMNINFO_RFK_FORBIDDEN:
++		dm->IQK_info.rfk_forbidden = (boolean)value;
++		break;
++#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
++	RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
++	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
++	case HALRF_CMNINFO_IQK_SEGMENT:
++		dm->IQK_info.segment_iqk = (boolean)value;
++		break;
++#endif
++	case HALRF_CMNINFO_RATE_INDEX:
++		rf->p_rate_index = (u32)value;
++		break;
++#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	case HALRF_CMNINFO_MP_PSD_POINT:
++		rf->halrf_psd_data.point = (u32)value;
++		break;
++	case HALRF_CMNINFO_MP_PSD_START_POINT:
++		rf->halrf_psd_data.start_point = (u32)value;
++		break;
++	case HALRF_CMNINFO_MP_PSD_STOP_POINT:
++		rf->halrf_psd_data.stop_point = (u32)value;
++		break;
++	case HALRF_CMNINFO_MP_PSD_AVERAGE:
++		rf->halrf_psd_data.average = (u32)value;
++		break;
++#endif
++	case HALRF_CMNINFO_POWER_TRACK_CONTROL:
++		cali_info->txpowertrack_control = (u8)value;
++		break;
++	default:
++		/* do nothing */
++		break;
++	}
++}
++
++u64 halrf_cmn_info_get(void *dm_void, u32 cmn_info)
++{
++	/* This init variable may be changed in run time. */
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	u64 return_value = 0;
++
++	switch (cmn_info) {
++	case HALRF_CMNINFO_ABILITY:
++		return_value = (u32)rf->rf_supportability;
++		break;
++	case HALRF_CMNINFO_RFK_FORBIDDEN:
++		return_value = dm->IQK_info.rfk_forbidden;
++		break;
++#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
++	RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
++	RTL8814B_SUPPORT == 1  || RTL8822C_SUPPORT == 1)
++	case HALRF_CMNINFO_IQK_SEGMENT:
++		return_value = dm->IQK_info.segment_iqk;
++		break;
++#endif
++	default:
++		/* do nothing */
++		break;
++	}
++
++	return return_value;
++}
++
++void halrf_supportability_init_mp(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	switch (dm->support_ic_type) {
++	case ODM_RTL8814B:
++#if (RTL8814B_SUPPORT == 1)
++		rf->rf_supportability =
++			/*HAL_RF_TX_PWR_TRACK |*/
++			HAL_RF_IQK |
++			HAL_RF_LCK |
++			HAL_RF_DPK |
++			HAL_RF_DACK |
++			/*HAL_RF_TXGAPK |*/
++			HAL_RF_DPK_TRACK |
++			0;
++#endif
++		break;
++#if (RTL8822B_SUPPORT == 1)
++	case ODM_RTL8822B:
++		rf->rf_supportability =
++			/*HAL_RF_TX_PWR_TRACK |*/
++			HAL_RF_IQK |
++			HAL_RF_LCK |
++			/*@HAL_RF_DPK |*/
++			0;
++		break;
++#endif
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:
++		rf->rf_supportability =
++			/*HAL_RF_TX_PWR_TRACK |*/
++			HAL_RF_IQK |
++			HAL_RF_LCK |
++			HAL_RF_DPK |
++			HAL_RF_DACK |
++			HAL_RF_DPK_TRACK |
++			HAL_RF_RXDCK |
++			HAL_RF_TXGAPK |
++			0;
++		break;
++#endif
++#if (RTL8821C_SUPPORT == 1)
++	case ODM_RTL8821C:
++		rf->rf_supportability =
++			/*HAL_RF_TX_PWR_TRACK |*/
++			HAL_RF_IQK |
++			HAL_RF_LCK |
++			/*@HAL_RF_DPK |*/
++			/*@HAL_RF_TXGAPK |*/
++			0;
++		break;
++#endif
++#if (RTL8195B_SUPPORT == 1)
++	case ODM_RTL8195B:
++		rf->rf_supportability =
++			HAL_RF_TX_PWR_TRACK |
++			HAL_RF_IQK |
++			HAL_RF_LCK |
++			HAL_RF_DPK |
++			/*HAL_RF_TXGAPK |*/
++			HAL_RF_DPK_TRACK |
++			0;
++		break;
++#endif
++#if (RTL8812F_SUPPORT == 1)
++	case ODM_RTL8812F:
++		rf->rf_supportability =
++			/*HAL_RF_TX_PWR_TRACK |*/
++			HAL_RF_IQK |
++			HAL_RF_LCK |
++			HAL_RF_DPK |
++			HAL_RF_DACK |
++			HAL_RF_DPK_TRACK |
++			0;
++		break;
++#endif
++
++#if (RTL8198F_SUPPORT == 1)
++	case ODM_RTL8198F:
++		rf->rf_supportability =
++			/*HAL_RF_TX_PWR_TRACK |*/
++			HAL_RF_IQK |
++			HAL_RF_LCK |
++			HAL_RF_DPK |
++			/*@HAL_RF_TXGAPK |*/
++			0;
++		break;
++#endif
++
++#if (RTL8192F_SUPPORT == 1)
++	case ODM_RTL8192F:
++		rf->rf_supportability =
++			/*HAL_RF_TX_PWR_TRACK |*/
++			HAL_RF_IQK |
++			HAL_RF_LCK |
++			HAL_RF_DPK |
++			/*@HAL_RF_TXGAPK |*/
++#ifdef CONFIG_2G_BAND_SHIFT
++			/*@HAL_2GBAND_SHIFT |*/
++#endif
++			0;
++		break;
++#endif
++
++#if (RTL8197F_SUPPORT == 1)
++	case ODM_RTL8197F:
++		rf->rf_supportability =
++			/*HAL_RF_TX_PWR_TRACK |*/
++			HAL_RF_IQK |
++			HAL_RF_LCK |
++			HAL_RF_DPK |
++			/*@HAL_RF_TXGAPK |*/
++			0;
++		break;
++#endif
++#if (RTL8197G_SUPPORT == 1)
++	case ODM_RTL8197G:
++		rf->rf_supportability =
++			/*HAL_RF_TX_PWR_TRACK |*/
++			HAL_RF_IQK |
++			/*HAL_RF_LCK |*/
++			HAL_RF_DPK |
++			/*@HAL_RF_TXGAPK |*/
++			HAL_RF_DPK_TRACK |
++			0;
++		break;
++#endif
++#if (RTL8721D_SUPPORT == 1)
++	case ODM_RTL8721D:
++		rf->rf_supportability =
++			HAL_RF_TX_PWR_TRACK |
++			HAL_RF_IQK |
++			HAL_RF_LCK |
++			HAL_RF_DPK |
++			HAL_RF_DPK_TRACK |
++			/*@HAL_RF_TXGAPK |*/
++			0;
++		break;
++#endif
++
++	default:
++		rf->rf_supportability =
++			/*HAL_RF_TX_PWR_TRACK |*/
++			HAL_RF_IQK |
++			HAL_RF_LCK |
++			/*@HAL_RF_DPK |*/
++			/*@HAL_RF_TXGAPK |*/
++			0;
++		break;
++	}
++
++	RF_DBG(dm, DBG_RF_INIT,
++	       "IC = ((0x%x)), RF_Supportability Init MP = ((0x%x))\n",
++	       dm->support_ic_type, rf->rf_supportability);
++}
++
++void halrf_supportability_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	switch (dm->support_ic_type) {
++	case ODM_RTL8814B:
++#if (RTL8814B_SUPPORT == 1)
++		rf->rf_supportability =
++			HAL_RF_TX_PWR_TRACK |
++			HAL_RF_IQK |
++			HAL_RF_LCK |
++			HAL_RF_DPK |
++			HAL_RF_DACK |
++			HAL_RF_DPK_TRACK |
++			0;
++#endif
++		break;
++#if (RTL8822B_SUPPORT == 1)
++	case ODM_RTL8822B:
++		rf->rf_supportability =
++			HAL_RF_TX_PWR_TRACK |
++			HAL_RF_IQK |
++			HAL_RF_LCK |
++			/*@HAL_RF_DPK |*/
++			0;
++		break;
++#endif
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:
++		rf->rf_supportability =
++			HAL_RF_TX_PWR_TRACK |
++			HAL_RF_IQK |
++			HAL_RF_LCK |
++			HAL_RF_DPK |
++			HAL_RF_DACK |
++			HAL_RF_DPK_TRACK |
++			HAL_RF_RXDCK |
++			HAL_RF_TXGAPK |
++			0;
++		break;
++#endif
++#if (RTL8821C_SUPPORT == 1)
++	case ODM_RTL8821C:
++		rf->rf_supportability =
++			HAL_RF_TX_PWR_TRACK |
++			HAL_RF_IQK |
++			HAL_RF_LCK |
++			/*@HAL_RF_DPK |*/
++			/*@HAL_RF_TXGAPK |*/
++			0;
++		break;
++#endif
++#if (RTL8195B_SUPPORT == 1)
++	case ODM_RTL8195B:
++		rf->rf_supportability =
++			HAL_RF_TX_PWR_TRACK |
++			HAL_RF_IQK |
++			HAL_RF_LCK |
++			HAL_RF_DPK |
++			/*HAL_RF_TXGAPK |*/
++			HAL_RF_DPK_TRACK |
++			0;
++		break;
++#endif
++#if (RTL8812F_SUPPORT == 1)
++		case ODM_RTL8812F:
++			rf->rf_supportability =
++				HAL_RF_TX_PWR_TRACK |
++				HAL_RF_IQK |
++				HAL_RF_LCK |
++				HAL_RF_DPK |
++				HAL_RF_DACK |
++				HAL_RF_DPK_TRACK |
++				0;
++			break;
++#endif
++
++#if (RTL8198F_SUPPORT == 1)
++		case ODM_RTL8198F:
++			rf->rf_supportability =
++				HAL_RF_TX_PWR_TRACK |
++				HAL_RF_IQK |
++				HAL_RF_LCK |
++				HAL_RF_DPK |
++				/*@HAL_RF_TXGAPK |*/
++				0;
++			break;
++#endif
++
++#if (RTL8192F_SUPPORT == 1)
++		case ODM_RTL8192F:
++			rf->rf_supportability =
++				HAL_RF_TX_PWR_TRACK |
++				HAL_RF_IQK |
++				HAL_RF_LCK |
++				HAL_RF_DPK |
++				/*@HAL_RF_TXGAPK |*/
++#ifdef CONFIG_2G_BAND_SHIFT
++				/*@HAL_2GBAND_SHIFT |*/
++#endif
++				0;
++			break;
++#endif
++
++#if (RTL8197F_SUPPORT == 1)
++		case ODM_RTL8197F:
++			rf->rf_supportability =
++				HAL_RF_TX_PWR_TRACK |
++				HAL_RF_IQK |
++				HAL_RF_LCK |
++				HAL_RF_DPK |
++				/*@HAL_RF_TXGAPK |*/
++				0;
++			break;
++#endif
++#if (RTL8197G_SUPPORT == 1)
++		case ODM_RTL8197G:
++			rf->rf_supportability =
++				HAL_RF_TX_PWR_TRACK |
++				HAL_RF_IQK |
++				/*HAL_RF_LCK |*/
++				HAL_RF_DPK |
++				/*@HAL_RF_TXGAPK |*/
++				HAL_RF_DPK_TRACK |
++#ifdef CONFIG_2G_BAND_SHIFT
++				HAL_2GBAND_SHIFT |
++#endif
++			0;
++		break;
++#endif
++#if (RTL8721D_SUPPORT == 1)
++		case ODM_RTL8721D:
++			rf->rf_supportability =
++				HAL_RF_TX_PWR_TRACK |
++				HAL_RF_IQK |
++				HAL_RF_LCK |
++				HAL_RF_DPK |
++				HAL_RF_DPK_TRACK |
++				/*@HAL_RF_TXGAPK |*/
++				0;
++			break;
++#endif
++
++	default:
++		rf->rf_supportability =
++			HAL_RF_TX_PWR_TRACK |
++			HAL_RF_IQK |
++			HAL_RF_LCK |
++			/*@HAL_RF_DPK |*/
++			0;
++		break;
++	}
++
++	RF_DBG(dm, DBG_RF_INIT,
++	       "IC = ((0x%x)), RF_Supportability Init = ((0x%x))\n",
++	       dm->support_ic_type, rf->rf_supportability);
++}
++
++void halrf_watchdog(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++#if 0
++	/*RF_DBG(dm, DBG_RF_TMP, "%s\n", __func__);*/
++#endif
++
++	if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
++		rf->is_tssi_in_progress)
++		return;
++
++	phydm_rf_watchdog(dm);
++	halrf_dpk_track(dm);
++}
++
++#if 0
++void
++halrf_iqk_init(
++	void			*dm_void
++)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	switch (dm->support_ic_type) {
++#if (RTL8814B_SUPPORT == 1)
++	case ODM_RTL8814B:
++		break;
++#endif
++#if (RTL8822B_SUPPORT == 1)
++	case ODM_RTL8822B:
++		_iq_calibrate_8822b_init(dm);
++		break;
++#endif
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:
++		_iq_calibrate_8822c_init(dm);
++		break;
++#endif
++#if (RTL8821C_SUPPORT == 1)
++	case ODM_RTL8821C:
++		break;
++#endif
++
++	default:
++		break;
++	}
++}
++#endif
++
++void halrf_reload_iqk(void *dm_void, boolean reset)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++	u8 i, ch;
++	u32 tmp;
++	u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
++
++	switch (dm->support_ic_type) {
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:		
++		iqk_reload_iqk_8822c(dm, reset);
++	break;
++#endif
++#if (RTL8195B_SUPPORT == 1)
++	case ODM_RTL8195B:
++		iqk_reload_iqk_8195b(dm, reset);
++	break;
++#endif
++
++	default:
++	break;
++	}
++}
++
++void halrf_rfk_handshake(void *dm_void, boolean is_before_k)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (!dm->mp_mode)
++		return;
++
++	if (*dm->mp_mode)
++		return;
++
++	switch (dm->support_ic_type) {
++#if (RTL8822C_SUPPORT == 1)
++		case ODM_RTL8822C:
++			halrf_rfk_handshake_8822c(dm, is_before_k);
++			break;
++#endif
++		default:
++			break;
++	}
++}
++
++void halrf_bbreset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++
++	switch (dm->support_ic_type) {
++#if (RTL8814B_SUPPORT == 1)
++		case ODM_RTL8814B:
++			phydm_bb_reset_8814b(dm);
++			break;
++#endif
++		default:
++			break;
++	}
++}
++
++void halrf_rf_k_connect_trigger(void *dm_void, boolean is_recovery,
++				enum halrf_k_segment_time seg_time)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;	
++	struct dm_dpk_info *dpk_info = &dm->dpk_info;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	if (!dm->mp_mode)
++		return;
++
++	if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
++		rf->is_carrier_suppresion) {
++		if (*dm->mp_mode & 
++			(*rf->is_con_tx || *rf->is_single_tone ||
++			*rf->is_carrier_suppresion))
++			return;
++	}
++
++	/*[TX GAP K]*/
++	halrf_txgapk_trigger(dm);
++
++	/*[LOK, IQK]*/
++	halrf_segment_iqk_trigger(dm, true, seg_time);
++
++	/*[TSSI Trk]*/
++	halrf_tssi_trigger(dm);
++
++	/*[DPK]*/
++	if(dpk_info->is_dpk_by_channel == true)
++		halrf_dpk_trigger(dm);
++	else
++		halrf_dpk_reload(dm);
++
++	//ADDA restore to MP_UI setting;
++	config_halrf_path_adda_setting_trigger(dm);
++
++	halrf_bbreset(dm);
++}
++
++void config_halrf_path_adda_setting_trigger(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	
++#if (RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814B)
++		config_phydm_path_adda_setting_8814b(dm);
++#endif
++	
++}
++
++void halrf_dack_restore(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	if (!(rf->rf_supportability & HAL_RF_DACK))
++		return;
++	switch (dm->support_ic_type) {
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:
++		halrf_dack_restore_8822c(dm);
++		break;
++#endif
++	default:
++		break;
++	}
++}
++void halrf_dack_trigger(void *dm_void, boolean force)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	u64 start_time;
++
++	if (!(rf->rf_supportability & HAL_RF_DACK))
++		return;
++
++	start_time = odm_get_current_time(dm);
++
++	switch (dm->support_ic_type) {
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:
++		halrf_dac_cal_8822c(dm, force);
++		break;
++#endif
++#if (RTL8812F_SUPPORT == 1)
++	case ODM_RTL8812F:
++		halrf_dac_cal_8812f(dm);
++		break;
++#endif
++#if (RTL8814B_SUPPORT == 1)
++	case ODM_RTL8814B:
++		halrf_dac_cal_8814b(dm);
++		break;
++#endif
++	default:
++		break;
++	}
++	rf->dpk_progressing_time = odm_get_progressing_time(dm, start_time);
++	RF_DBG(dm, DBG_RF_DACK, "[DACK]DACK progressing_time = %lld ms\n",
++	       rf->dpk_progressing_time);
++}
++
++
++void halrf_dack_dbg(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	u64 start_time;
++
++	if (!(rf->rf_supportability & HAL_RF_DACK))
++		return;
++
++	switch (dm->support_ic_type) {
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:
++		halrf_dack_dbg_8822c(dm);
++		break;
++#endif
++	default:
++		break;
++	}
++}
++
++
++void halrf_segment_iqk_trigger(void *dm_void, boolean clear,
++			       boolean segment_iqk)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	u64 start_time;
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++	if (odm_check_power_status(dm) == false)
++		return;
++#endif
++
++	if (!dm->mp_mode)
++		return;
++
++	if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
++		rf->is_carrier_suppresion) {
++		if (*dm->mp_mode & 
++			(*rf->is_con_tx || *rf->is_single_tone ||
++			*rf->is_carrier_suppresion))
++			return;
++	}
++
++	if (!(rf->rf_supportability & HAL_RF_IQK))
++		return;
++
++#if DISABLE_BB_RF
++	return;
++#endif
++	if (iqk_info->rfk_forbidden)
++		return;
++
++	halrf_rfk_handshake(dm, true);
++
++	if (!dm->rf_calibrate_info.is_iqk_in_progress) {
++		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
++		dm->rf_calibrate_info.is_iqk_in_progress = true;
++		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
++		start_time = odm_get_current_time(dm);
++		dm->IQK_info.segment_iqk = segment_iqk;
++
++		switch (dm->support_ic_type) {
++#if (RTL8822B_SUPPORT == 1)
++		case ODM_RTL8822B:
++			phy_iq_calibrate_8822b(dm, clear, segment_iqk);
++			break;
++#endif
++#if (RTL8822C_SUPPORT == 1)
++		case ODM_RTL8822C:
++			phy_iq_calibrate_8822c(dm, clear, segment_iqk);
++			break;
++#endif
++#if (RTL8821C_SUPPORT == 1)
++		case ODM_RTL8821C:
++			phy_iq_calibrate_8821c(dm, clear, segment_iqk);
++			break;
++#endif
++#if (RTL8814B_SUPPORT == 1)
++		case ODM_RTL8814B:
++			phy_iq_calibrate_8814b(dm, clear, segment_iqk);
++			break;
++#endif
++#if (RTL8195B_SUPPORT == 1)
++		case ODM_RTL8195B:
++			phy_iq_calibrate_8195b(dm, clear, segment_iqk);
++			break;
++#endif
++#if (RTL8710C_SUPPORT == 1)
++		case ODM_RTL8710C:
++			phy_iq_calibrate_8710c(dm, clear, segment_iqk);
++			break;
++#endif
++#if (RTL8198F_SUPPORT == 1)
++		case ODM_RTL8198F:
++			phy_iq_calibrate_8198f(dm, clear, segment_iqk);
++			break;
++#endif
++#if (RTL8812F_SUPPORT == 1)
++		case ODM_RTL8812F:
++			phy_iq_calibrate_8812f(dm, clear, segment_iqk);
++			break;
++#endif
++#if (RTL8197G_SUPPORT == 1)
++		case ODM_RTL8197G:
++			phy_iq_calibrate_8197g(dm, clear, segment_iqk);
++			break;
++#endif
++#if (RTL8188E_SUPPORT == 1)
++		case ODM_RTL8188E:
++			phy_iq_calibrate_8188e(dm, false);
++			break;
++#endif
++#if (RTL8188F_SUPPORT == 1)
++		case ODM_RTL8188F:
++			phy_iq_calibrate_8188f(dm, false);
++			break;
++#endif
++#if (RTL8192E_SUPPORT == 1)
++		case ODM_RTL8192E:
++			phy_iq_calibrate_8192e(dm, false);
++			break;
++#endif
++#if (RTL8197F_SUPPORT == 1)
++		case ODM_RTL8197F:
++			phy_iq_calibrate_8197f(dm, false);
++			break;
++#endif
++#if (RTL8192F_SUPPORT == 1)
++		case ODM_RTL8192F:
++			phy_iq_calibrate_8192f(dm, false);
++			break;
++#endif
++#if (RTL8703B_SUPPORT == 1)
++		case ODM_RTL8703B:
++			phy_iq_calibrate_8703b(dm, false);
++			break;
++#endif
++#if (RTL8710B_SUPPORT == 1)
++		case ODM_RTL8710B:
++			phy_iq_calibrate_8710b(dm, false);
++			break;
++#endif
++#if (RTL8723B_SUPPORT == 1)
++		case ODM_RTL8723B:
++			phy_iq_calibrate_8723b(dm, false);
++			break;
++#endif
++#if (RTL8723D_SUPPORT == 1)
++		case ODM_RTL8723D:
++			phy_iq_calibrate_8723d(dm, false);
++			break;
++#endif
++#if (RTL8721D_SUPPORT == 1)
++		case ODM_RTL8721D:
++			phy_iq_calibrate_8721d(dm, false);
++			break;
++#endif
++#if (RTL8812A_SUPPORT == 1)
++		case ODM_RTL8812:
++			phy_iq_calibrate_8812a(dm, false);
++			break;
++#endif
++#if (RTL8821A_SUPPORT == 1)
++		case ODM_RTL8821:
++			phy_iq_calibrate_8821a(dm, false);
++			break;
++#endif
++#if (RTL8814A_SUPPORT == 1)
++		case ODM_RTL8814A:
++			phy_iq_calibrate_8814a(dm, false);
++			break;
++#endif
++		default:
++			break;
++		}
++		dm->rf_calibrate_info.iqk_progressing_time =
++				odm_get_progressing_time(dm, start_time);
++		RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK progressing_time = %lld ms\n",
++		       dm->rf_calibrate_info.iqk_progressing_time);
++
++		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
++		dm->rf_calibrate_info.is_iqk_in_progress = false;
++		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
++
++		halrf_rfk_handshake(dm, false);
++	} else {
++		RF_DBG(dm, DBG_RF_IQK,
++		       "== Return the IQK CMD, because RFKs in Progress ==\n");
++	}
++}
++
++
++void halrf_iqk_trigger(void *dm_void, boolean is_recovery)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++	struct dm_dpk_info *dpk_info = &dm->dpk_info;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	u64 start_time;
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++	if (odm_check_power_status(dm) == false)
++		return;
++#endif
++
++	if (!dm->mp_mode)
++		return;
++
++	if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
++		rf->is_carrier_suppresion) {
++		if (*dm->mp_mode & 
++			(*rf->is_con_tx || *rf->is_single_tone ||
++			*rf->is_carrier_suppresion))
++			return;
++	}
++
++	if (!(rf->rf_supportability & HAL_RF_IQK))
++		return;
++
++#if DISABLE_BB_RF
++	return;
++#endif
++
++	if (iqk_info->rfk_forbidden)
++		return;
++
++	halrf_rfk_handshake(dm, true);
++
++	if (!dm->rf_calibrate_info.is_iqk_in_progress) {
++		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
++		dm->rf_calibrate_info.is_iqk_in_progress = true;
++		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
++		start_time = odm_get_current_time(dm);
++		switch (dm->support_ic_type) {
++#if (RTL8188E_SUPPORT == 1)
++		case ODM_RTL8188E:
++			phy_iq_calibrate_8188e(dm, is_recovery);
++			break;
++#endif
++#if (RTL8188F_SUPPORT == 1)
++		case ODM_RTL8188F:
++			phy_iq_calibrate_8188f(dm, is_recovery);
++			break;
++#endif
++#if (RTL8192E_SUPPORT == 1)
++		case ODM_RTL8192E:
++			phy_iq_calibrate_8192e(dm, is_recovery);
++			break;
++#endif
++#if (RTL8197F_SUPPORT == 1)
++		case ODM_RTL8197F:
++			phy_iq_calibrate_8197f(dm, is_recovery);
++			break;
++#endif
++#if (RTL8192F_SUPPORT == 1)
++		case ODM_RTL8192F:
++			phy_iq_calibrate_8192f(dm, is_recovery);
++			break;
++#endif
++#if (RTL8703B_SUPPORT == 1)
++		case ODM_RTL8703B:
++			phy_iq_calibrate_8703b(dm, is_recovery);
++			break;
++#endif
++#if (RTL8710B_SUPPORT == 1)
++		case ODM_RTL8710B:
++			phy_iq_calibrate_8710b(dm, is_recovery);
++			break;
++#endif
++#if (RTL8723B_SUPPORT == 1)
++		case ODM_RTL8723B:
++			phy_iq_calibrate_8723b(dm, is_recovery);
++			break;
++#endif
++#if (RTL8723D_SUPPORT == 1)
++		case ODM_RTL8723D:
++			phy_iq_calibrate_8723d(dm, is_recovery);
++			break;
++#endif
++#if (RTL8721D_SUPPORT == 1)
++		case ODM_RTL8721D:
++			phy_iq_calibrate_8721d(dm, is_recovery);
++			break;
++#endif
++#if (RTL8812A_SUPPORT == 1)
++		case ODM_RTL8812:
++			phy_iq_calibrate_8812a(dm, is_recovery);
++			break;
++#endif
++#if (RTL8821A_SUPPORT == 1)
++		case ODM_RTL8821:
++			phy_iq_calibrate_8821a(dm, is_recovery);
++			break;
++#endif
++#if (RTL8814A_SUPPORT == 1)
++		case ODM_RTL8814A:
++			phy_iq_calibrate_8814a(dm, is_recovery);
++			break;
++#endif
++#if (RTL8822B_SUPPORT == 1)
++		case ODM_RTL8822B:
++			phy_iq_calibrate_8822b(dm, false, false);
++			break;
++#endif
++#if (RTL8822C_SUPPORT == 1)
++		case ODM_RTL8822C:
++			phy_iq_calibrate_8822c(dm, false, false);
++			break;
++#endif
++#if (RTL8821C_SUPPORT == 1)
++		case ODM_RTL8821C:
++			phy_iq_calibrate_8821c(dm, false, false);
++			break;
++#endif
++#if (RTL8814B_SUPPORT == 1)
++		case ODM_RTL8814B:
++			phy_iq_calibrate_8814b(dm, false, false);
++			break;
++#endif
++#if (RTL8195B_SUPPORT == 1)
++		case ODM_RTL8195B:
++			phy_iq_calibrate_8195b(dm, false, false);
++			break;
++#endif
++#if (RTL8710C_SUPPORT == 1)
++		case ODM_RTL8710C:
++			phy_iq_calibrate_8710c(dm, false, false);
++			break;
++#endif
++#if (RTL8198F_SUPPORT == 1)
++		case ODM_RTL8198F:
++			phy_iq_calibrate_8198f(dm, false, false);
++			break;
++#endif
++#if (RTL8812F_SUPPORT == 1)
++		case ODM_RTL8812F:
++			phy_iq_calibrate_8812f(dm, false, false);
++			break;
++#endif
++#if (RTL8197G_SUPPORT == 1)
++		case ODM_RTL8197G:
++			phy_iq_calibrate_8197g(dm, false, false);
++			break;
++#endif
++		default:
++			break;
++		}
++	rf->iqk_progressing_time = odm_get_progressing_time(dm, start_time);
++	RF_DBG(dm, DBG_RF_LCK, "[IQK]Trigger IQK progressing_time = %lld ms\n",
++	       rf->iqk_progressing_time);
++		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
++		dm->rf_calibrate_info.is_iqk_in_progress = false;
++		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
++
++		halrf_rfk_handshake(dm, false);
++	} else {
++		RF_DBG(dm, DBG_RF_IQK,
++		       "== Return the IQK CMD, because RFKs in Progress ==\n");
++	}
++}
++
++void halrf_lck_trigger(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	u64 start_time;
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++	if (odm_check_power_status(dm) == false)
++		return;
++#endif
++
++	if (!dm->mp_mode)
++		return;
++
++	if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
++		rf->is_carrier_suppresion) {
++		if (*dm->mp_mode & 
++			(*rf->is_con_tx || *rf->is_single_tone ||
++			*rf->is_carrier_suppresion))
++			return;
++	}
++
++	if (!(rf->rf_supportability & HAL_RF_LCK))
++		return;
++
++#if DISABLE_BB_RF
++	return;
++#endif
++	if (iqk_info->rfk_forbidden)
++		return;
++	while (*dm->is_scan_in_process) {
++		RF_DBG(dm, DBG_RF_IQK, "[LCK]scan is in process, bypass LCK\n");
++		return;
++	}
++
++	if (!dm->rf_calibrate_info.is_lck_in_progress) {
++		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
++		dm->rf_calibrate_info.is_lck_in_progress = true;
++		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
++		start_time = odm_get_current_time(dm);
++		switch (dm->support_ic_type) {
++#if (RTL8188E_SUPPORT == 1)
++		case ODM_RTL8188E:
++			phy_lc_calibrate_8188e(dm);
++			break;
++#endif
++#if (RTL8188F_SUPPORT == 1)
++		case ODM_RTL8188F:
++			phy_lc_calibrate_8188f(dm);
++			break;
++#endif
++#if (RTL8192E_SUPPORT == 1)
++		case ODM_RTL8192E:
++			phy_lc_calibrate_8192e(dm);
++			break;
++#endif
++#if (RTL8197F_SUPPORT == 1)
++		case ODM_RTL8197F:
++			phy_lc_calibrate_8197f(dm);
++			break;
++#endif
++#if (RTL8192F_SUPPORT == 1)
++		case ODM_RTL8192F:
++			phy_lc_calibrate_8192f(dm);
++			break;
++#endif
++#if (RTL8703B_SUPPORT == 1)
++		case ODM_RTL8703B:
++			phy_lc_calibrate_8703b(dm);
++			break;
++#endif
++#if (RTL8710B_SUPPORT == 1)
++		case ODM_RTL8710B:
++			phy_lc_calibrate_8710b(dm);
++			break;
++#endif
++#if (RTL8721D_SUPPORT == 1)
++		case ODM_RTL8721D:
++			phy_lc_calibrate_8721d(dm);
++			break;
++#endif
++#if (RTL8723B_SUPPORT == 1)
++		case ODM_RTL8723B:
++			phy_lc_calibrate_8723b(dm);
++			break;
++#endif
++#if (RTL8723D_SUPPORT == 1)
++		case ODM_RTL8723D:
++			phy_lc_calibrate_8723d(dm);
++			break;
++#endif
++#if (RTL8812A_SUPPORT == 1)
++		case ODM_RTL8812:
++			phy_lc_calibrate_8812a(dm);
++			break;
++#endif
++#if (RTL8821A_SUPPORT == 1)
++		case ODM_RTL8821:
++			phy_lc_calibrate_8821a(dm);
++			break;
++#endif
++#if (RTL8814A_SUPPORT == 1)
++		case ODM_RTL8814A:
++			phy_lc_calibrate_8814a(dm);
++			break;
++#endif
++#if (RTL8822B_SUPPORT == 1)
++		case ODM_RTL8822B:
++			phy_lc_calibrate_8822b(dm);
++			break;
++#endif
++#if (RTL8822C_SUPPORT == 1)
++		case ODM_RTL8822C:
++			phy_lc_calibrate_8822c(dm);
++			break;
++#endif
++#if (RTL8812F_SUPPORT == 1)
++		case ODM_RTL8812F:
++			phy_lc_calibrate_8812f(dm);
++			break;
++#endif
++#if (RTL8821C_SUPPORT == 1)
++		case ODM_RTL8821C:
++			phy_lc_calibrate_8821c(dm);
++			break;
++#endif
++#if (RTL8814B_SUPPORT == 1)
++		case ODM_RTL8814B:
++			break;
++#endif
++#if (RTL8710C_SUPPORT == 1)
++		case ODM_RTL8710C:
++			phy_lc_calibrate_8710c(dm);
++			break;
++#endif
++		default:
++			break;
++		}
++		dm->rf_calibrate_info.lck_progressing_time =
++				odm_get_progressing_time(dm, start_time);
++		RF_DBG(dm, DBG_RF_IQK, "[IQK]LCK progressing_time = %lld ms\n",
++		       dm->rf_calibrate_info.lck_progressing_time);
++#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
++		halrf_lck_dbg(dm);
++#endif
++		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
++		dm->rf_calibrate_info.is_lck_in_progress = false;
++		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
++	} else {
++		RF_DBG(dm, DBG_RF_IQK,
++		       "= Return the LCK CMD, because RFK is in Progress =\n");
++	}
++}
++
++void halrf_aac_check(struct dm_struct *dm)
++{
++	switch (dm->support_ic_type) {
++#if (RTL8821C_SUPPORT == 1)
++	case ODM_RTL8821C:
++#if 0
++		aac_check_8821c(dm);
++#endif
++		break;
++#endif
++#if (RTL8822B_SUPPORT == 1)
++	case ODM_RTL8822B:
++#if 1
++		aac_check_8822b(dm);
++#endif
++		break;
++#endif
++	default:
++		break;
++	}
++}
++
++void halrf_rxdck(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	if (!(rf->rf_supportability & HAL_RF_RXDCK))
++		return;
++
++	switch (dm->support_ic_type) {
++	case ODM_RTL8822C:
++#if (RTL8822C_SUPPORT == 1)
++		halrf_rxdck_8822c(dm);
++		break;
++#endif
++	default:
++		break;
++	}
++}
++
++void halrf_x2k_check(struct dm_struct *dm)
++{
++
++	switch (dm->support_ic_type) {
++	case ODM_RTL8821C:
++#if (RTL8821C_SUPPORT == 1)
++#endif
++		break;
++	case ODM_RTL8822C:
++#if (RTL8822C_SUPPORT == 1)
++		phy_x2_check_8822c(dm);
++		break;
++#endif
++	case ODM_RTL8812F:
++#if (RTL8812F_SUPPORT == 1)
++		phy_x2_check_8812f(dm);
++		break;
++#endif
++	default:
++		break;
++	}
++}
++
++void halrf_set_rfsupportability(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	if (!dm->mp_mode)
++		return;
++
++	if (rf->manual_rf_supportability &&
++	    *rf->manual_rf_supportability != 0xffffffff) {
++		rf->rf_supportability = *rf->manual_rf_supportability;
++	} else if (*dm->mp_mode) {
++		halrf_supportability_init_mp(dm);
++	} else {
++		halrf_supportability_init(dm);
++	}
++}
++
++void halrf_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	RF_DBG(dm, DBG_RF_INIT, "HALRF_Init\n");
++	rf->aac_checked = false;
++	halrf_init_debug_setting(dm);
++	halrf_set_rfsupportability(dm);
++#if 1
++	/*Init all RF funciton*/
++	halrf_aac_check(dm);
++	halrf_dack_trigger(dm, false);
++	halrf_x2k_check(dm);
++#endif
++
++	/*power trim, thrmal trim, pa bias*/
++	phydm_config_new_kfree(dm);
++
++	/*TSSI Init*/
++	halrf_tssi_dck(dm, true);
++	halrf_tssi_get_efuse(dm);
++	halrf_tssi_set_de(dm);
++
++	/*TX Gap K*/
++	halrf_txgapk_write_gain_table(dm);
++}
++
++void halrf_dpk_trigger(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	struct dm_dpk_info *dpk_info = &dm->dpk_info;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++
++	u64 start_time;
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++	if (odm_check_power_status(dm) == false)
++		return;
++#endif
++
++	if (!dm->mp_mode)
++		return;
++
++	if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
++		rf->is_carrier_suppresion) {
++		if (*dm->mp_mode &
++			(*rf->is_con_tx || *rf->is_single_tone ||
++			*rf->is_carrier_suppresion))
++			return;
++	}
++
++	if (!(rf->rf_supportability & HAL_RF_DPK))
++		return;
++
++#if DISABLE_BB_RF
++	return;
++#endif
++
++	if (iqk_info->rfk_forbidden)
++		return;
++
++	halrf_rfk_handshake(dm, true);
++
++	if (!rf->is_dpk_in_progress) {
++		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
++		rf->is_dpk_in_progress = true;
++		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
++		start_time = odm_get_current_time(dm);
++
++		switch (dm->support_ic_type) {
++#if (RTL8822C_SUPPORT == 1)
++		case ODM_RTL8822C:
++			do_dpk_8822c(dm);
++			break;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++#if (RTL8197F_SUPPORT == 1)
++		case ODM_RTL8197F:
++			do_dpk_8197f(dm);
++			break;
++#endif
++#if (RTL8192F_SUPPORT == 1)
++		case ODM_RTL8192F:
++			do_dpk_8192f(dm);
++			break;
++#endif
++
++#if (RTL8198F_SUPPORT == 1)
++		case ODM_RTL8198F:
++			do_dpk_8198f(dm);
++			break;
++#endif
++#if (RTL8812F_SUPPORT == 1)
++		case ODM_RTL8812F:
++			do_dpk_8812f(dm);
++			break;
++#endif
++#if (RTL8197G_SUPPORT == 1)
++		case ODM_RTL8197G:
++			do_dpk_8197g(dm);
++			break;
++#endif
++
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++		case ODM_RTL8814B:
++			do_dpk_8814b(dm);
++			break;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
++#if (RTL8195B_SUPPORT == 1)
++		case ODM_RTL8195B:
++			do_dpk_8195b(dm);
++		break;
++#endif
++#if (RTL8721D_SUPPORT == 1)
++		case ODM_RTL8721D:
++			do_dpk_8721d(dm);
++			break;
++#endif
++#endif
++		default:
++			break;
++	}
++	rf->dpk_progressing_time = odm_get_progressing_time(dm, start_time);
++	RF_DBG(dm, DBG_RF_DPK, "[DPK]DPK progressing_time = %lld ms\n",
++	       rf->dpk_progressing_time);
++
++		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
++		rf->is_dpk_in_progress = false;
++		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
++
++		halrf_rfk_handshake(dm, false);
++	} else {
++		RF_DBG(dm, DBG_RF_DPK,
++		       "== Return the DPK CMD, because RFKs in Progress ==\n");
++	}
++}
++
++void halrf_set_dpkbychannel(void *dm_void, boolean dpk_by_ch)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	struct dm_dpk_info *dpk_info = &dm->dpk_info;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++
++	
++	switch (dm->support_ic_type) {
++#if (RTL8814B_SUPPORT == 1)
++		case ODM_RTL8814B:
++			dpk_set_dpkbychannel_8814b(dm, dpk_by_ch);
++		break;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
++#if (RTL8195B_SUPPORT == 1)
++		case ODM_RTL8195B:
++			dpk_set_dpkbychannel_8195b(dm,dpk_by_ch);
++		break;
++#endif
++#endif
++		default:
++			if (dpk_by_ch)
++				dpk_info->is_dpk_by_channel = 1;
++			else
++				dpk_info->is_dpk_by_channel = 0;
++		break;
++	}
++
++}
++
++void halrf_set_dpkenable(void *dm_void, boolean is_dpk_enable)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	struct dm_dpk_info *dpk_info = &dm->dpk_info;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++
++	
++	switch (dm->support_ic_type) {
++#if (RTL8814B_SUPPORT == 1)
++		case ODM_RTL8814B:
++			dpk_set_is_dpk_enable_8814b(dm, is_dpk_enable);
++		break;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
++#if (RTL8195B_SUPPORT == 1)
++		case ODM_RTL8195B:
++			dpk_set_is_dpk_enable_8195b(dm, is_dpk_enable);
++	break;
++#endif
++
++#if (RTL8721D_SUPPORT == 1)
++	case ODM_RTL8721D:
++		dpk_set_is_dpk_enable_8721d(dm, is_dpk_enable);
++	break;
++#endif
++
++#endif
++	default:
++	break;
++	}
++
++}
++boolean halrf_get_dpkbychannel(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	struct dm_dpk_info *dpk_info = &dm->dpk_info;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++	boolean is_dpk_by_channel = true;
++	
++	switch (dm->support_ic_type) {
++#if (RTL8814B_SUPPORT == 1)
++		case ODM_RTL8814B:
++			is_dpk_by_channel = dpk_get_dpkbychannel_8814b(dm);
++		break;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
++#if (RTL8195B_SUPPORT == 1)
++		case ODM_RTL8195B:
++			is_dpk_by_channel = dpk_get_dpkbychannel_8195b(dm);
++		break;
++#endif
++#endif
++
++	default:
++	break;
++	}
++	return is_dpk_by_channel;
++
++}
++
++
++boolean halrf_get_dpkenable(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	struct dm_dpk_info *dpk_info = &dm->dpk_info;
++	struct dm_iqk_info *iqk_info = &dm->IQK_info;
++	boolean is_dpk_enable = true;
++
++	
++	switch (dm->support_ic_type) {
++#if (RTL8814B_SUPPORT == 1)
++		case ODM_RTL8814B:
++			is_dpk_enable = dpk_get_is_dpk_enable_8814b(dm);
++		break;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
++#if (RTL8195B_SUPPORT == 1)
++		case ODM_RTL8195B:
++			is_dpk_enable = dpk_get_is_dpk_enable_8195b(dm);
++		break;
++#endif
++#endif
++		default:
++		break;
++	}
++	return is_dpk_enable;
++
++}
++
++u8 halrf_dpk_result_check(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_dpk_info *dpk_info = &dm->dpk_info;
++
++	u8 result = 0;
++
++	switch (dm->support_ic_type) {
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:
++		if (dpk_info->dpk_path_ok == 0x3)
++			result = 1;
++		else
++			result = 0;
++		break;
++#endif
++
++#if (RTL8195B_SUPPORT == 1)
++	case ODM_RTL8195B:
++		if (dpk_info->dpk_path_ok == 0x1)
++			result = 1;
++		else
++			result = 0;
++		break;
++#endif
++
++#if (RTL8721D_SUPPORT == 1)
++	case ODM_RTL8721D:
++		if (dpk_info->dpk_path_ok == 0x1)
++			result = 1;
++		else
++			result = 0;
++		break;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++
++#if (RTL8197F_SUPPORT == 1)
++	case ODM_RTL8197F:
++		if (dpk_info->dpk_path_ok == 0x3)
++			result = 1;
++		else
++			result = 0;
++		break;
++#endif
++
++#if (RTL8192F_SUPPORT == 1)
++	case ODM_RTL8192F:
++		if (dpk_info->dpk_path_ok == 0x3)
++			result = 1;
++		else
++			result = 0;
++		break;
++#endif
++
++#if (RTL8198F_SUPPORT == 1)
++	case ODM_RTL8198F:
++		if (dpk_info->dpk_path_ok == 0xf)
++			result = 1;
++		else
++			result = 0;
++		break;
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++	case ODM_RTL8814B:
++		if (dpk_info->dpk_path_ok == 0xf)
++			result = 1;
++		else
++			result = 0;
++		break;
++#endif
++
++#if (RTL8812F_SUPPORT == 1)
++	case ODM_RTL8812F:
++		if (dpk_info->dpk_path_ok == 0x3)
++			result = 1;
++		else
++			result = 0;
++		break;
++#endif
++
++#if (RTL8197G_SUPPORT == 1)
++	case ODM_RTL8197G:
++		if (dpk_info->dpk_path_ok == 0x3)
++			result = 1;
++		else
++			result = 0;
++		break;
++#endif
++
++#endif
++	default:
++		break;
++	}
++	return result;
++}
++
++void halrf_dpk_sram_read(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	u8 path, group;
++
++	switch (dm->support_ic_type) {
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:
++		dpk_coef_read_8822c(dm);
++		break;
++#endif
++
++#if (RTL8195B_SUPPORT == 1)
++	case ODM_RTL8195B:
++		dpk_sram_read_8195b(dm);
++		break;
++#endif
++
++#if (RTL8721D_SUPPORT == 1)
++	case ODM_RTL8721D:
++		dpk_sram_read_8721d(dm);
++		break;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++
++#if (RTL8197F_SUPPORT == 1)
++	case ODM_RTL8197F:
++		dpk_sram_read_8197f(dm);
++		break;
++#endif
++
++#if (RTL8192F_SUPPORT == 1)
++	case ODM_RTL8192F:
++		dpk_sram_read_8192f(dm);
++		break;
++#endif
++
++#if (RTL8198F_SUPPORT == 1)
++	case ODM_RTL8198F:
++		dpk_sram_read_8198f(dm);
++		break;
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++	case ODM_RTL8814B:
++		dpk_sram_read_8814b(dm);
++		break;
++#endif
++
++#if (RTL8812F_SUPPORT == 1)
++	case ODM_RTL8812F:
++		dpk_coef_read_8812f(dm);
++		break;
++#endif
++
++#if (RTL8197G_SUPPORT == 1)
++	case ODM_RTL8197G:
++		dpk_sram_read_8197g(dm);
++		break;
++#endif
++
++#endif
++	default:
++		break;
++	}
++}
++
++void halrf_dpk_enable_disable(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	if (!(rf->rf_supportability & HAL_RF_DPK))
++		return;
++
++	if (!rf->is_dpk_in_progress) {
++		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
++		rf->is_dpk_in_progress = true;
++		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
++
++	switch (dm->support_ic_type) {
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:
++		dpk_enable_disable_8822c(dm);
++		break;
++#endif
++#if (RTL8195B_SUPPORT == 1)
++	case ODM_RTL8195B:
++		dpk_enable_disable_8195b(dm);
++		break;
++#endif
++#if (RTL8721D_SUPPORT == 1)
++		case ODM_RTL8721D:
++			phy_dpk_enable_disable_8721d(dm);
++		break;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++
++#if (RTL8197F_SUPPORT == 1)
++	case ODM_RTL8197F:
++		phy_dpk_enable_disable_8197f(dm);
++		break;
++#endif
++#if (RTL8192F_SUPPORT == 1)
++	case ODM_RTL8192F:
++		phy_dpk_enable_disable_8192f(dm);
++		break;
++#endif
++
++#if (RTL8198F_SUPPORT == 1)
++	case ODM_RTL8198F:
++		dpk_enable_disable_8198f(dm);
++		break;
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++	case ODM_RTL8814B:
++		dpk_enable_disable_8814b(dm);
++		break;
++#endif
++
++#if (RTL8812F_SUPPORT == 1)
++	case ODM_RTL8812F:
++		dpk_enable_disable_8812f(dm);
++		break;
++#endif
++
++#if (RTL8197G_SUPPORT == 1)
++	case ODM_RTL8197G:
++		dpk_enable_disable_8197g(dm);
++		break;
++#endif
++
++#endif
++	default:
++		break;
++	}
++
++		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
++		rf->is_dpk_in_progress = false;
++		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
++	} else {
++		RF_DBG(dm, DBG_RF_DPK,
++		       "== Return the DPK CMD, because RFKs in Progress ==\n");
++	}
++}
++
++void halrf_dpk_track(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_dpk_info *dpk_info = &dm->dpk_info;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
++	    dm->is_psd_in_process || (dpk_info->dpk_path_ok == 0) ||
++	    !(rf->rf_supportability & HAL_RF_DPK_TRACK) || rf->is_tssi_in_progress
++	    || rf->is_txgapk_in_progress || *dm->is_fcs_mode_enable)
++		return;
++
++	switch (dm->support_ic_type) {
++#if (RTL8814B_SUPPORT == 1)
++	case ODM_RTL8814B:
++		dpk_track_8814b(dm);
++		break;
++#endif
++
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:
++		dpk_track_8822c(dm);
++		break;
++#endif
++
++#if (RTL8195B_SUPPORT == 1)
++	case ODM_RTL8195B:
++		dpk_track_8195b(dm);
++		break;
++#endif
++
++#if (RTL8721D_SUPPORT == 1)
++	case ODM_RTL8721D:
++		phy_dpk_track_8721d(dm);
++		break;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++
++#if (RTL8197F_SUPPORT == 1)
++	case ODM_RTL8197F:
++		phy_dpk_track_8197f(dm);
++		break;
++#endif
++
++#if (RTL8192F_SUPPORT == 1)
++	case ODM_RTL8192F:
++		phy_dpk_track_8192f(dm);
++		break;
++#endif
++
++#if (RTL8198F_SUPPORT == 1)
++	case ODM_RTL8198F:
++		dpk_track_8198f(dm);
++		break;
++#endif
++
++#if (RTL8812F_SUPPORT == 1)
++	case ODM_RTL8812F:
++		dpk_track_8812f(dm);
++		break;
++#endif
++
++#if (RTL8197G_SUPPORT == 1)
++	case ODM_RTL8197G:
++		dpk_track_8197g(dm);
++		break;
++#endif
++
++#endif
++	default:
++		break;
++	}
++}
++
++void halrf_set_dpk_track(void *dm_void, u8 enable)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &(dm->rf_table);
++
++	if (enable)
++		rf->rf_supportability = rf->rf_supportability | HAL_RF_DPK_TRACK;
++	else
++		rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK_TRACK;
++}
++
++void halrf_dpk_reload(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_dpk_info *dpk_info = &dm->dpk_info;
++
++	switch (dm->support_ic_type) {
++#if (RTL8195B_SUPPORT == 1)
++	case ODM_RTL8195B:
++		if (dpk_info->dpk_path_ok > 0)
++			dpk_reload_8195b(dm);
++		break;
++#endif
++#if (RTL8721D_SUPPORT == 1)
++	case ODM_RTL8721D:
++		if (dpk_info->dpk_path_ok > 0)
++			dpk_reload_8721d(dm);
++		break;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++
++#if (RTL8197F_SUPPORT == 1)
++	case ODM_RTL8197F:
++		if (dpk_info->dpk_path_ok > 0)
++			dpk_reload_8197f(dm);
++		break;
++#endif
++
++#if (RTL8192F_SUPPORT == 1)
++	case ODM_RTL8192F:
++		if (dpk_info->dpk_path_ok > 0)
++			dpk_reload_8192f(dm);
++
++		break;
++#endif
++
++#if (RTL8198F_SUPPORT == 1)
++	case ODM_RTL8198F:
++		if (dpk_info->dpk_path_ok > 0)
++			dpk_reload_8198f(dm);
++		break;		
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++	case ODM_RTL8814B:
++		if (dpk_info->dpk_path_ok > 0)
++			dpk_reload_8814b(dm);
++		break;		
++#endif
++
++#endif
++	default:
++		break;
++	}
++}
++
++void halrf_dpk_switch(void *dm_void, u8 enable)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_dpk_info *dpk_info = &dm->dpk_info;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	if (enable) {
++		rf->rf_supportability = rf->rf_supportability | HAL_RF_DPK;
++		dpk_info->is_dpk_enable = true;
++		halrf_dpk_enable_disable(dm);
++		halrf_dpk_trigger(dm);
++		halrf_set_dpk_track(dm, 1);
++	} else {
++		halrf_set_dpk_track(dm, 0);
++		dpk_info->is_dpk_enable = false;
++		halrf_dpk_enable_disable(dm);
++		rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK;
++	}
++}
++
++void _halrf_dpk_info_by_chip(void *dm_void, u32 *_used, char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	switch (dm->support_ic_type) {
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:
++		dpk_info_by_8822c(dm, &used, output, &out_len);
++		break;
++#endif
++
++#if (RTL8812F_SUPPORT == 1)
++	case ODM_RTL8812F:
++		dpk_info_by_8812f(dm, &used, output, &out_len);
++		break;
++#endif
++
++#if (RTL8197G_SUPPORT == 1)
++	case ODM_RTL8197G:
++		dpk_info_by_8197g(dm, &used, output, &out_len);
++		break;
++#endif
++
++	default:
++		break;
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void _halrf_display_dpk_info(void *dm_void, u32 *_used, char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_dpk_info *dpk_info = &dm->dpk_info;
++	struct _hal_rf_ *rf = &(dm->rf_table);
++
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	char *ic_name = NULL;
++
++	switch (dm->support_ic_type) {
++
++#if (RTL8822C_SUPPORT)
++	case ODM_RTL8822C:
++		ic_name = "8822C";
++		break;
++#endif
++
++#if (RTL8814B_SUPPORT)
++	case ODM_RTL8814B:
++		ic_name = "8814B";
++		break;
++#endif
++
++#if (RTL8812F_SUPPORT)
++	case ODM_RTL8812F:
++		ic_name = "8812F";
++		break;
++#endif
++
++#if (RTL8198F_SUPPORT)
++	case ODM_RTL8198F:
++		ic_name = "8198F";
++		break;
++#endif
++
++#if (RTL8197F_SUPPORT)
++	case ODM_RTL8197F:
++		ic_name = "8197F";
++		break;
++#endif
++
++#if (RTL8192F_SUPPORT)
++	case ODM_RTL8192F:
++		ic_name = "8192F";
++		break;
++#endif
++
++#if (RTL8197G_SUPPORT)
++	case ODM_RTL8197G:
++		ic_name = "8197G";
++		break;
++#endif
++
++#if (RTL8710B_SUPPORT)
++	case ODM_RTL8721D:
++		ic_name = "8721D";
++		break;
++#endif
++
++#if (RTL8195B_SUPPORT)
++	case ODM_RTL8195B:
++		ic_name = "8195B";
++		break;
++#endif
++	}
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\n===============[ DPK info %s ]===============\n", ic_name);
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s %s\n",
++		 "DPK type", (dm->fw_offload_ability & PHYDM_RF_DPK_OFFLOAD) ? "FW" : "Driver",
++		 (dpk_info->is_dpk_by_channel) ? "(By channel)" : "(By group)");
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d (%d)\n",
++		 "FW Ver (Sub Ver)", dm->fw_version, dm->fw_sub_version);
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
++		 "DPK Ver", HALRF_DPK_VER);
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
++		 "RFK init ver", HALRF_RFK_INIT_VER);
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d (RFE type:%d)\n",
++		 "Ext_PA 2G / 5G", dm->ext_pa, dm->ext_pa_5g, dm->rfe_type);
++
++	if ((dpk_info->dpk_ch == 0) && (dpk_info->thermal_dpk[0] == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used, "\n %-25s\n",
++			 "No DPK had been done before!!!");
++		return;
++	}
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d\n",
++		 "DPK Cal / OK / Reload", dpk_info->dpk_cal_cnt, dpk_info->dpk_ok_cnt,
++		 dpk_info->dpk_reload_cnt);
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
++		 "RFK H2C timeout", (rf->is_rfk_h2c_timeout) ? "Yes" : "No");
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
++		 "DPD Reload", (dpk_info->dpk_status & BIT(0)) ? "Yes" : "No");
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
++		 "DPD status", dpk_info->is_dpk_enable ? "Enable" : "Disable");
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
++		 "DPD track status", (rf->rf_supportability & HAL_RF_DPK_TRACK) ? "Enable" : "Disable");
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s / %s / %d / %s\n",
++		 "TSSI / Band / CH / BW", dpk_info->is_tssi_mode == 1 ? "On" : "Off",
++		 dpk_info->dpk_band == 0 ? "2G" : "5G", dpk_info->dpk_ch,
++		 dpk_info->dpk_bw == 3 ? "20M" : (dpk_info->dpk_bw == 2 ? "40M" : "80M"));
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s / %s / %s / %s\n",
++		 "DPK result (path)", dpk_info->dpk_path_ok & BIT(0) ? "OK" : "Fail",
++		 (dm->support_ic_type & ODM_IC_2SS) ? ((dpk_info->dpk_path_ok & BIT(1)) >> 1 ? "OK" : "Fail") : "NA",
++		 (dm->support_ic_type & ODM_IC_3SS) ? ((dpk_info->dpk_path_ok & BIT(2)) >> 2 ? "OK" : "Fail") : "NA",
++		 (dm->support_ic_type & ODM_IC_4SS) ? ((dpk_info->dpk_path_ok & BIT(3)) >> 3 ? "OK" : "Fail") : "NA");
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d / %d\n",
++		 "DPK thermal (path)", dpk_info->thermal_dpk[0], dpk_info->thermal_dpk[1],
++		 dpk_info->thermal_dpk[2], dpk_info->thermal_dpk[3]);
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
++		 "DPK bkup GNT control", dpk_info->gnt_control);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
++		 "DPK bkup GNT value", dpk_info->gnt_value);
++
++	_halrf_dpk_info_by_chip(dm, &used, output, &out_len);
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void halrf_dpk_debug_cmd(void *dm_void, char input[][16], u32 *_used,
++				char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_dpk_info *dpk_info = &dm->dpk_info;
++	struct _hal_rf_ *rf = &(dm->rf_table);
++
++	char *cmd[5] = {"-h", "on", "off", "info", "switch"};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 i;
++
++	if ((strcmp(input[2], cmd[4]) != 0)) {
++		if (!(rf->rf_supportability & HAL_RF_DPK)) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "DPK is Unsupported!!!\n");
++			return;
++		}
++	}
++
++	if ((strcmp(input[2], cmd[0]) == 0)) {
++		for (i = 1; i < 4; i++) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "  %s\n", cmd[i]);
++		}
++	} else if ((strcmp(input[2], cmd[1]) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "DPK is Enabled!!\n");
++		dpk_info->is_dpk_enable = true;
++		halrf_dpk_enable_disable(dm);
++	} else if ((strcmp(input[2], cmd[2]) == 0)){
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "DPK is Disabled!!\n");
++		dpk_info->is_dpk_enable = false;
++		halrf_dpk_enable_disable(dm);
++	} else if ((strcmp(input[2], cmd[3]) == 0))
++		_halrf_display_dpk_info(dm, &used, output, &out_len);
++	else if ((strcmp(input[2], cmd[4]) == 0) && (strcmp(input[3], cmd[1]) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "DPK Switch on!!\n");
++		halrf_dpk_switch(dm, 1);
++	} else if ((strcmp(input[2], cmd[4]) == 0) && (strcmp(input[3], cmd[2]) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "DPK Switch off!!\n");
++		halrf_dpk_switch(dm, 0);
++	} else {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "DPK Trigger!!\n");
++		halrf_dpk_trigger(dm);
++	}
++}
++
++void halrf_dpk_c2h_report_transfer(void	*dm_void, boolean is_ok, u8 *buf, u8 buf_size)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	struct dm_dpk_info *dpk_info = &dm->dpk_info;
++
++	if (!(rf->rf_supportability & HAL_RF_DPK))
++		return;
++
++	switch (dm->support_ic_type) {
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:
++		dpk_c2h_report_transfer_8822c(dm, is_ok, buf, buf_size);
++		break;
++#endif
++	default:
++		break;
++	}
++}
++
++void halrf_dpk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	struct dm_dpk_info *dpk_info = &dm->dpk_info;
++
++	if (!(rf->rf_supportability & HAL_RF_DPK) || rf->is_dpk_in_progress)
++		return;
++
++	switch (dm->support_ic_type) {
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:
++		dpk_info_rsvd_page_8822c(dm, buf, buf_size);
++		break;
++#endif
++	default:
++		break;
++	}
++}
++
++void halrf_iqk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	if (!(rf->rf_supportability & HAL_RF_IQK))
++		return;
++
++	if (dm->rf_calibrate_info.is_iqk_in_progress)
++		return;
++
++	switch (dm->support_ic_type) {
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:
++		iqk_info_rsvd_page_8822c(dm, buf, buf_size);
++		break;
++#endif
++#if (RTL8195B_SUPPORT == 1)
++	case ODM_RTL8195B:
++		iqk_info_rsvd_page_8195b(dm, buf, buf_size);
++		break;
++#endif
++
++	default:
++		break;
++	}
++}
++
++enum hal_status
++halrf_config_rfk_with_header_file(void *dm_void, u32 config_type)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	enum hal_status result = HAL_STATUS_SUCCESS;
++#if 0
++#if (RTL8822B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8822B) {
++		if (config_type == CONFIG_BB_RF_CAL_INIT)
++			odm_read_and_config_mp_8822b_cal_init(dm);
++	}
++#endif
++#endif
++#if (RTL8197G_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8197G) {
++		if (config_type == CONFIG_BB_RF_CAL_INIT)
++			odm_read_and_config_mp_8197g_cal_init(dm);
++	}
++#endif
++#if (RTL8198F_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8198F) {
++		if (config_type == CONFIG_BB_RF_CAL_INIT)
++			odm_read_and_config_mp_8198f_cal_init(dm);
++	}
++#endif
++#if (RTL8812F_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8812F) {
++		if (config_type == CONFIG_BB_RF_CAL_INIT)
++			odm_read_and_config_mp_8812f_cal_init(dm);
++	}
++#endif
++#if (RTL8822C_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8822C) {
++		if (config_type == CONFIG_BB_RF_CAL_INIT)
++			odm_read_and_config_mp_8822c_cal_init(dm);
++	}
++#endif
++#if (RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8814B) {
++		if (config_type == CONFIG_BB_RF_CAL_INIT)
++			odm_read_and_config_mp_8814b_cal_init(dm);
++	}
++#endif
++#if (RTL8195B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8195B) {
++		if (config_type == CONFIG_BB_RF_CAL_INIT)
++			odm_read_and_config_mp_8195b_cal_init(dm);
++	}
++#endif
++#if (RTL8721D_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8721D) {
++		if (config_type == CONFIG_BB_RF_CAL_INIT)
++			odm_read_and_config_mp_8721d_cal_init(dm);
++	}
++#endif
++
++	return result;
++}
++
++void halrf_txgapk_trigger(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	u64 start_time = 0x0;
++
++	if (!(rf->rf_supportability & HAL_RF_TXGAPK))
++		return;
++
++	halrf_rfk_handshake(dm, true);
++
++	start_time = odm_get_current_time(dm);
++	rf->is_txgapk_in_progress = true;
++
++	switch (dm->support_ic_type) {
++#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
++#if (RTL8195B_SUPPORT == 1)
++	case ODM_RTL8195B:
++		/*phy_txgap_calibrate_8195b(dm, false);*/
++	break;
++#endif
++#if (RTL8721D_SUPPORT == 1)
++	case ODM_RTL8721D:
++		/*phy_txgap_calibrate_8721d(dm, false);*/
++	break;
++#endif
++
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++	case ODM_RTL8814B:
++		/*phy_txgap_calibrate_8814b(dm, false);*/
++	break;
++#endif
++
++#if (RTL8822C_SUPPORT == 1)
++	case ODM_RTL8822C:
++		halrf_txgapk_8822c(dm);
++	break;
++#endif
++
++	default:
++		break;
++	}
++	rf->is_txgapk_in_progress = false;
++
++	halrf_rfk_handshake(dm, false);
++
++	rf->dpk_progressing_time =
++		odm_get_progressing_time(dm_void, start_time);
++	RF_DBG(dm, DBG_RF_TXGAPK, "[TGGC]TXGAPK progressing_time = %lld ms\n",
++	       rf->dpk_progressing_time);
++}
++
++void halrf_tssi_get_efuse(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	
++#if (RTL8822C_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8822C) {
++		halrf_tssi_get_efuse_8822c(dm);
++		halrf_get_efuse_thermal_pwrtype_8822c(dm);
++	}
++#endif
++
++#if (RTL8812F_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8812F) {
++		halrf_tssi_get_efuse_8812f(dm);
++	}
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814B) {
++		halrf_tssi_get_efuse_8814b(dm);
++		halrf_get_efuse_thermal_pwrtype_8814b(dm);
++	}
++#endif
++
++#if (RTL8197G_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8197G) {
++		halrf_tssi_get_efuse_8197g(dm);
++	}
++#endif
++
++}
++
++void halrf_do_rxbb_dck(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++
++#if (RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8814B)
++		halrf_do_rxbb_dck_8814b(dm);
++#endif
++
++}
++
++void halrf_do_tssi(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (RTL8822C_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8822C)
++		halrf_do_tssi_8822c(dm);
++#endif
++
++#if (RTL8812F_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8812F)
++		halrf_do_tssi_8812f(dm);
++#endif
++
++#if (RTL8197G_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8197G)
++		halrf_do_tssi_8197g(dm);
++#endif
++
++}
++
++void halrf_set_tssi_enable(void *dm_void, boolean enable)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &(dm->rf_table);
++
++	if (enable == 1) {
++		rf->power_track_type = 4;
++		odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);
++	} else {
++		rf->power_track_type = 0;
++		odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
++	}
++}
++
++
++void halrf_do_thermal(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (RTL8822C_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8822C)
++		halrf_do_thermal_8822c(dm);
++#endif
++}
++
++
++
++u32 halrf_set_tssi_value(void *dm_void, u32 tssi_value)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (RTL8822C_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8822C)
++		return halrf_set_tssi_value_8822c(dm, tssi_value);
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814B)
++		return halrf_set_tssi_value_8814b(dm, tssi_value);
++#endif
++
++	return 0;
++}
++
++void halrf_set_tssi_power(void *dm_void, s8 power)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (RTL8822C_SUPPORT == 1)
++	/*halrf_set_tssi_poewr_8822c(dm, power);*/
++#endif
++}
++
++void halrf_tssi_set_de_for_tx_verify(void *dm_void, u32 tssi_de, u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (RTL8822C_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8822C)
++		halrf_tssi_set_de_for_tx_verify_8822c(dm, tssi_de, path);
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814B)
++		halrf_tssi_set_de_for_tx_verify_8814b(dm, tssi_de, path);
++#endif
++
++#if (RTL8812F_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8812F)
++		halrf_tssi_set_de_for_tx_verify_8812f(dm, tssi_de, path);
++#endif
++
++#if (RTL8197G_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8197G)
++		halrf_tssi_set_de_for_tx_verify_8197g(dm, tssi_de, path);
++#endif
++
++}
++
++u32 halrf_query_tssi_value(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (RTL8822C_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8822C)
++		return halrf_query_tssi_value_8822c(dm);
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814B)
++		return halrf_query_tssi_value_8814b(dm);
++#endif
++	return 0;
++}
++
++void halrf_tssi_cck(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (RTL8822C_SUPPORT == 1)
++	/*halrf_tssi_cck_8822c(dm);*/
++	if (dm->support_ic_type & ODM_RTL8822C)
++		halrf_thermal_cck_8822c(dm);
++#endif
++
++}
++
++void halrf_thermal_cck(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (RTL8822C_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8822C)
++		halrf_thermal_cck_8822c(dm);
++#endif
++
++}
++
++void halrf_tssi_set_de(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	
++#if (RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814B)
++		halrf_tssi_set_de_8814b(dm);
++#endif
++}
++
++void halrf_tssi_dck(void *dm_void, u8 direct_do)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	
++	halrf_rfk_handshake(dm, true);
++
++#if (RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814B) {
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++		if (dm->rfe_type == 1 || dm->rfe_type == 4 || dm->rfe_type == 5)
++			return;
++#else
++		if (dm->rfe_type == 1 || dm->rfe_type == 6)
++			return;
++#endif
++		halrf_tssi_dck_8814b(dm, direct_do);
++	}
++#endif
++
++#if (RTL8822C_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8822C)
++		halrf_tssi_dck_8822c(dm);
++#endif
++
++#if (RTL8812F_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8812F)
++		halrf_tssi_dck_8812f(dm);
++#endif
++
++#if (RTL8197G_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8197G)
++		halrf_tssi_dck_8197g(dm);
++#endif
++
++	halrf_rfk_handshake(dm, false);
++
++}
++
++void halrf_calculate_tssi_codeword(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	
++#if (RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814B)
++		halrf_calculate_tssi_codeword_8814b(dm, RF_PATH_A);
++#endif
++
++#if (RTL8822C_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8822C)
++		halrf_calculate_tssi_codeword_8822c(dm);
++#endif	
++}
++
++void halrf_set_tssi_codeword(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
++#endif
++	
++#if (RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814B)
++		halrf_set_tssi_codeword_8814b(dm, tssi->tssi_codeword);
++#endif
++
++#if (RTL8822C_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8822C)
++		halrf_set_tssi_codeword_8822c(dm, tssi->tssi_codeword);
++#endif	
++
++}
++
++u8 halrf_get_tssi_codeword_for_txindex(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814B) {
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++		return 100;
++#else
++		return 60;
++#endif
++	}
++#endif
++
++#if (RTL8822C_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8822C)
++		return 64;
++#endif
++
++#if (RTL8812F_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8812F)
++		return 100;
++#endif
++
++#if (RTL8197G_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8197G)
++		return 100;
++#endif
++
++	return 60;
++}
++
++void halrf_tssi_clean_de(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (RTL8812F_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8812F)
++		halrf_tssi_clean_de_8812f(dm);
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814B)
++		halrf_tssi_clean_de_8814b(dm);
++#endif
++
++#if (RTL8197G_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8197G)
++		halrf_tssi_clean_de_8197g(dm);
++#endif
++
++}
++
++u32 halrf_tssi_trigger_de(void *dm_void, u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (RTL8812F_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8812F)
++		return halrf_tssi_trigger_de_8812f(dm, path);
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814B)
++		return halrf_tssi_trigger_de_8814b(dm, path);
++#endif
++
++#if (RTL8197G_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8197G)
++		return halrf_tssi_trigger_de_8197g(dm, path);
++#endif
++	return 0;
++}
++
++u32 halrf_tssi_get_de(void *dm_void, u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (RTL8822C_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8822C)
++		return halrf_tssi_get_de_8822c(dm, path);
++#endif
++	
++#if (RTL8812F_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8812F)
++		return halrf_tssi_get_de_8812f(dm, path);
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814B)
++		return halrf_tssi_get_de_8814b(dm, path);
++#endif
++
++#if (RTL8197G_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8197G)
++		return halrf_tssi_get_de_8197g(dm, path);
++#endif
++	return 0;
++}
++
++void halrf_tssi_trigger(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
++	struct _hal_rf_ *rf = &(dm->rf_table);
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	if (*dm->mp_mode == 1) {
++		if (cali_info->txpowertrack_control == 0 ||
++			cali_info->txpowertrack_control == 1) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"[TSSI]======>%s MP Mode UI chose thermal tracking. return !!!\n", __func__);
++			return;
++		}
++	} else {
++		if (rf->power_track_type >= 0 && rf->power_track_type <= 3) {
++			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				"[TSSI]======>%s Normal Mode efues is thermal tracking. return !!!\n", __func__);
++			return;
++		}	
++	}
++#endif
++
++	halrf_calculate_tssi_codeword(dm);
++	halrf_set_tssi_codeword(dm);
++	halrf_tssi_dck(dm, false);
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	halrf_tssi_get_efuse(dm);
++#endif
++	halrf_tssi_set_de(dm);
++	halrf_do_tssi(dm);
++}
++
++void halrf_txgapk_write_gain_table(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (RTL8822C_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8822C)
++		halrf_txgapk_save_all_tx_gain_table_8822c(dm);
++#endif
++}
++
++void halrf_txgapk_reload_tx_gain(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (RTL8822C_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8822C)
++		halrf_txgapk_reload_tx_gain_8822c(dm);
++#endif
++}
++
++void halrf_txgap_enable_disable(void *dm_void, u8 enable)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &(dm->rf_table);
++
++	if (enable) {
++		rf->rf_supportability = rf->rf_supportability | HAL_RF_TXGAPK;
++		halrf_txgapk_trigger(dm);
++	} else {
++		rf->rf_supportability = rf->rf_supportability & ~HAL_RF_TXGAPK;
++		halrf_txgapk_reload_tx_gain(dm);
++	}
++}
++
++void _halrf_dump_subpage(void *dm_void, u32 *_used, char *output, u32 *_out_len, u8 page)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 addr;
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\n===============[ Subpage_%d start]===============\n", page);
++
++	odm_set_bb_reg(dm, R_0x1b00, BIT(2) | BIT(1), page);
++
++	for (addr = 0x1b00; addr < 0x1c00; addr += 0x10) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 " 0x%x : 0x%08x  0x%08x  0x%08x  0x%08x\n", addr,
++			odm_get_bb_reg(dm, addr, MASKDWORD),
++		 	odm_get_bb_reg(dm, addr + 0x4, MASKDWORD),
++		 	odm_get_bb_reg(dm, addr + 0x8, MASKDWORD),
++		 	odm_get_bb_reg(dm, addr + 0xc, MASKDWORD));
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void halrf_dump_rfk_reg(void *dm_void, char input[][16], u32 *_used,
++			      char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 reg_1b00, supportability;
++	u8 page;
++
++	if (!(dm->support_ic_type & (ODM_IC_11AC_SERIES |  ODM_IC_JGR3_SERIES))) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "CMD is Unsupported due to IC type!!!\n");
++		return;
++	} else if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
++	    dm->is_psd_in_process || rf->is_tssi_in_progress || rf->is_txgapk_in_progress) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Bypass CMD due to RFK is doing!!!\n");
++		return;
++	}
++
++	supportability = rf->rf_supportability;
++
++	/*to avoid DPK track interruption*/
++	rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK_TRACK;
++
++	reg_1b00 = odm_get_bb_reg(dm, R_0x1b00, MASKDWORD);
++
++	if (input[2])
++		PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[0]);
++
++	if ((strcmp(input[2], help) == 0))
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "dump subpage {0:Page0, 1:Page1, 2:Page2, 3:Page3, 4:all}\n");
++	else if (var1[0] > 4)
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Wrong subpage number!!\n");
++	else if (var1[0] == 4) {
++		for (page = 0; page < 4; page++)
++			_halrf_dump_subpage(dm, &used, output, &out_len, page);
++	} else
++		_halrf_dump_subpage(dm, &used, output, &out_len, (u8)var1[0]);
++
++	odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, reg_1b00);
++
++	rf->rf_supportability = supportability;
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++/*Golbal function*/
++void halrf_reload_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 i;
++
++	for (i = 0; i < num; i++)
++		odm_write_4byte(dm, bp_reg[i], bp[i]);
++}
++
++void halrf_reload_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num,
++		       u8 ss)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 i, path;
++
++	for (i = 0; i < num; i++) {
++		for (path = 0; path < ss; path++)
++			odm_set_rf_reg(dm, (enum rf_path)path, bp_reg[i],
++				       MASK20BITS, bp[i][path]);
++	}
++}
++
++void halrf_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 i;
++
++	for (i = 0; i < num; i++)
++		bp[i] = odm_read_4byte(dm, bp_reg[i]);
++}
++
++void halrf_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num, u8 ss)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 i, path;
++
++	for (i = 0; i < num; i++) {
++		for (path = 0; path < ss; path++) {
++			bp[i][path] =
++				odm_get_rf_reg(dm, (enum rf_path)path,
++					       bp_reg[i], MASK20BITS);
++		}
++	}
++}
++
++void halrf_swap(void *dm_void, u32 *v1, u32 *v2)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 temp;
++
++	temp = *v1;
++	*v1 = *v2;
++	*v2 = temp;
++}
++
++void halrf_bubble(void *dm_void, u32 *v1, u32 *v2)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 temp;
++
++	if (*v1 >= 0x200 && *v2 >= 0x200) {
++		if (*v1 > *v2)
++			halrf_swap(dm, v1, v2);
++	} else if (*v1 < 0x200 && *v2 < 0x200) {
++		if (*v1 > *v2)
++			halrf_swap(dm, v1, v2);
++	} else if (*v1 < 0x200 && *v2 >= 0x200) {
++		halrf_swap(dm, v1, v2);
++	}
++}
++
++void halrf_b_sort(void *dm_void, u32 *iv, u32 *qv)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 temp;
++	u32 i, j;
++
++	RF_DBG(dm, DBG_RF_DACK, "[DACK]bubble!!!!!!!!!!!!");
++	for (i = 0; i < SN - 1; i++) {
++		for (j = 0; j < (SN - 1 - i) ; j++) {
++			halrf_bubble(dm, &iv[j], &iv[j + 1]);
++			halrf_bubble(dm, &qv[j], &qv[j + 1]);
++		}
++	}
++}
++
++void halrf_minmax_compare(void *dm_void, u32 value, u32 *min,
++			  u32 *max)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (value >= 0x200) {
++		if (*min >= 0x200) {
++			if (*min > value)
++				*min = value;
++		} else {
++			*min = value;
++		}
++		if (*max >= 0x200) {
++			if (*max < value)
++				*max = value;
++		}
++	} else {
++		if (*min < 0x200) {
++			if (*min > value)
++				*min = value;
++		}
++
++		if (*max  >= 0x200) {
++			*max = value;
++		} else {
++			if (*max < value)
++				*max = value;
++		}
++	}
++}
++
++u32 halrf_delta(void *dm_void, u32 v1, u32 v2)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (v1 >= 0x200 && v2 >= 0x200) {
++		if (v1 > v2)
++			return v1 - v2;
++		else
++			return v2 - v1;
++	} else if (v1 >= 0x200 && v2 < 0x200) {
++		return v2 + (0x400 - v1);
++	} else if (v1 < 0x200 && v2 >= 0x200) {
++		return v1 + (0x400 - v2);
++	}
++
++	if (v1 > v2)
++		return v1 - v2;
++	else
++		return v2 - v1;
++}
++
++boolean halrf_compare(void *dm_void, u32 value)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	boolean fail = false;
++
++	if (value >= 0x200 && (0x400 - value) > 0x64)
++		fail = true;
++	else if (value < 0x200 && value > 0x64)
++		fail = true;
++
++	if (fail)
++		RF_DBG(dm, DBG_RF_DACK, "[DACK]overflow!!!!!!!!!!!!!!!");
++	return fail;
++}
++
++void halrf_mode(void *dm_void, u32 *i_value, u32 *q_value)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 iv[SN], qv[SN], im[SN], qm[SN], temp, temp1, temp2;
++	u32 p, m, t;
++	u32 i_max = 0, q_max = 0, i_min = 0x0, q_min = 0x0, c = 0x0;
++	u32 i_delta, q_delta;
++	u8 i, j, ii = 0, qi = 0;
++	boolean fail = false;
++
++	ODM_delay_ms(10);
++	for (i = 0; i < SN; i++) {
++		im[i] = 0;
++		qm[i] = 0;
++	}
++	i = 0;
++	c = 0;
++	while (i < SN && c < 1000) {
++		c++;
++		temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
++		iv[i] = (temp & 0x3ff000) >> 12;
++		qv[i] = temp & 0x3ff;
++
++		fail = false;
++		if (halrf_compare(dm, iv[i]))
++			fail = true;
++		if (halrf_compare(dm, qv[i]))
++			fail = true;
++		if (!fail)
++			i++;
++	}
++	c = 0;
++	do {
++		c++;
++		i_min = iv[0];
++		i_max = iv[0];
++		q_min = qv[0];
++		q_max = qv[0];
++		for (i = 0; i < SN; i++) {
++			halrf_minmax_compare(dm, iv[i], &i_min, &i_max);
++			halrf_minmax_compare(dm, qv[i], &q_min, &q_max);
++		}
++		RF_DBG(dm, DBG_RF_DACK, "[DACK]i_min=0x%x, i_max=0x%x",
++		       i_min, i_max);
++		RF_DBG(dm, DBG_RF_DACK, "[DACK]q_min=0x%x, q_max=0x%x",
++		       q_min, q_max);
++		if (i_max < 0x200 && i_min < 0x200)
++			i_delta = i_max - i_min;
++		else if (i_max >= 0x200 && i_min >= 0x200)
++			i_delta = i_max - i_min;
++		else
++			i_delta = i_max + (0x400 - i_min);
++
++		if (q_max < 0x200 && q_min < 0x200)
++			q_delta = q_max - q_min;
++		else if (q_max >= 0x200 && q_min >= 0x200)
++			q_delta = q_max - q_min;
++		else
++			q_delta = q_max + (0x400 - q_min);
++		RF_DBG(dm, DBG_RF_DACK, "[DACK]i_delta=0x%x, q_delta=0x%x",
++		       i_delta, q_delta);
++		halrf_b_sort(dm, iv, qv);
++		if (i_delta > 5 || q_delta > 5) {
++			temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
++			iv[0] = (temp & 0x3ff000) >> 12;
++			qv[0] = temp & 0x3ff;
++			temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
++			iv[SN - 1] = (temp & 0x3ff000) >> 12;
++			qv[SN - 1] = temp & 0x3ff;
++		} else {
++			break;
++		}
++	} while (c < 100);
++#if 1
++#if 0
++	for (i = 0; i < SN; i++)
++		RF_DBG(dm, DBG_RF_DACK, "[DACK]iv[%d] = 0x%x\n", i, iv[i]);
++	for (i = 0; i < SN; i++)
++		RF_DBG(dm, DBG_RF_DACK, "[DACK]qv[%d] = 0x%x\n", i, qv[i]);
++#endif
++	/*i*/
++	m = 0;
++	p = 0;
++	for (i = 10; i < SN - 10; i++) {
++		if (iv[i] > 0x200)
++			m = (0x400 - iv[i]) + m;
++		else
++			p = iv[i] + p;
++	}
++
++	if (p > m) {
++		t = p - m;
++		t = t / (SN - 20);
++	} else {
++		t = m - p;
++		t = t / (SN - 20);
++		if (t != 0x0)
++			t = 0x400 - t;
++	}
++	*i_value = t;
++	/*q*/
++	m = 0;
++	p = 0;
++	for (i = 10; i < SN - 10; i++) {
++		if (qv[i] > 0x200)
++			m = (0x400 - qv[i]) + m;
++		else
++			p = qv[i] + p;
++	}
++	if (p > m) {
++		t = p - m;
++		t = t / (SN - 20);
++	} else {
++		t = m - p;
++		t = t / (SN - 20);
++		if (t != 0x0)
++			t = 0x400 - t;
++	}
++	*q_value = t;
++#endif
++}
++void halrf_delay_10us(u16 v1)
++{	
++	u16 i = 0;
++	
++	for (i = 0; i < v1; i++)
++		ODM_delay_us(10);
++}
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf.h
+new file mode 100644
+index 000000000..5d327cede
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf.h
+@@ -0,0 +1,787 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_H__
++#define __HALRF_H__
++
++/*@============================================================*/
++/*@include files*/
++/*@============================================================*/
++#include "halrf/halrf_psd.h"
++#if (RTL8822B_SUPPORT == 1)
++#include "halrf/rtl8822b/halrf_rfk_init_8822b.h"
++#endif
++#if (RTL8822C_SUPPORT == 1)
++#include "halrf/rtl8822c/halrf_rfk_init_8822c.h"
++#include "halrf/rtl8822c/halrf_iqk_8822c.h"
++#include "halrf/rtl8822c/halrf_tssi_8822c.h"
++#include "halrf/rtl8822c/halrf_dpk_8822c.h"
++#include "halrf/rtl8822c/halrf_txgapk_8822c.h"
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++#if (RTL8197G_SUPPORT == 1)
++#include "halrf/rtl8197g/halrf_rfk_init_8197g.h"
++#endif
++#if (RTL8198F_SUPPORT == 1)
++#include "halrf/rtl8198f/halrf_rfk_init_8198f.h"
++#endif
++#if (RTL8812F_SUPPORT == 1)
++#include "halrf/rtl8812f/halrf_rfk_init_8812f.h"
++#endif
++
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++#include "halrf/rtl8814b/halrf_rfk_init_8814b.h"
++#include "halrf/rtl8814b/halrf_iqk_8814b.h"
++#include "halrf/rtl8814b/halrf_dpk_8814b.h"
++#include "halrf/rtl8814b/halrf_txgapk_8814b.h"
++#endif
++
++/*@============================================================*/
++/*@Definition */
++/*@============================================================*/
++/*IQK version*/
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++#define IQK_VER_8188E "0x14"
++#define IQK_VER_8192E "0x01"
++#define IQK_VER_8192F "0x01"
++#define IQK_VER_8723B "0x1e"
++#define IQK_VER_8812A "0x02"
++#define IQK_VER_8821A "0x02"
++#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
++#define IQK_VER_8188E "0x01"
++#define IQK_VER_8192E "0x01"
++#define IQK_VER_8192F "0x01"
++#define IQK_VER_8723B "0x1e"
++#define IQK_VER_8812A "0x01"
++#define IQK_VER_8821A "0x01"
++#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++#define IQK_VER_8188E "0x01"
++#define IQK_VER_8192E "0x01"
++#define IQK_VER_8192F "0x01"
++#define IQK_VER_8723B "0x1e"
++#define IQK_VER_8812A "0x01"
++#define IQK_VER_8821A "0x01"
++#elif (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
++#define IQK_VER_8188E "0x01"
++#define IQK_VER_8192E "0x01"
++#define IQK_VER_8192F "0x01"
++#define IQK_VER_8723B "0x1e"
++#define IQK_VER_8812A "0x01"
++#define IQK_VER_8821A "0x01"
++#endif
++#define IQK_VER_8814A "0x0f"
++#define IQK_VER_8188F "0x01"
++#define IQK_VER_8197F "0x1d"
++#define IQK_VER_8703B "0x05"
++#define IQK_VER_8710B "0x01"
++#define IQK_VER_8723D "0x02"
++#define IQK_VER_8822B "0x32"
++#define IQK_VER_8822C "0x10"
++#define IQK_VER_8821C "0x23"
++#define IQK_VER_8198F "0x0b"
++#define IQK_VER_8814B "0x13"
++#define IQK_VER_8812F "0x0b"
++#define IQK_VER_8710C "0x06"
++#define IQK_VER_8197G "0x03"
++
++/*LCK version*/
++#define LCK_VER_8188E "0x02"
++#define LCK_VER_8192E "0x02"
++#define LCK_VER_8192F "0x01"
++#define LCK_VER_8723B "0x02"
++#define LCK_VER_8812A "0x01"
++#define LCK_VER_8821A "0x01"
++#define LCK_VER_8814A "0x01"
++#define LCK_VER_8188F "0x01"
++#define LCK_VER_8197F "0x01"
++#define LCK_VER_8703B "0x01"
++#define LCK_VER_8710B "0x01"
++#define LCK_VER_8723D "0x01"
++#define LCK_VER_8822B "0x02"
++#define LCK_VER_8822C "0x00"
++#define LCK_VER_8821C "0x02"
++#define LCK_VER_8814B "0x01"
++#define LCK_VER_8195B "0x02"
++#define LCK_VER_8710C "0x01"
++#define LCK_VER_8197G "0x00"
++
++/*power tracking version*/
++#define PWRTRK_VER_8188E "0x01"
++#define PWRTRK_VER_8192E "0x01"
++#define PWRTRK_VER_8192F "0x01"
++#define PWRTRK_VER_8723B "0x01"
++#define PWRTRK_VER_8812A "0x01"
++#define PWRTRK_VER_8821A "0x01"
++#define PWRTRK_VER_8814A "0x01"
++#define PWRTRK_VER_8188F "0x01"
++#define PWRTRK_VER_8197F "0x01"
++#define PWRTRK_VER_8703B "0x01"
++#define PWRTRK_VER_8710B "0x01"
++#define PWRTRK_VER_8723D "0x01"
++#define PWRTRK_VER_8822B "0x01"
++#define PWRTRK_VER_8822C "0x00"
++#define PWRTRK_VER_8821C "0x01"
++#define PWRTRK_VER_8814B "0x00"
++#define PWRTRK_VER_8197G "0x00"
++
++/*DPK version*/
++#define DPK_VER_8188E "NONE"
++#define DPK_VER_8192E "NONE"
++#define DPK_VER_8723B "NONE"
++#define DPK_VER_8812A "NONE"
++#define DPK_VER_8821A "NONE"
++#define DPK_VER_8814A "NONE"
++#define DPK_VER_8188F "NONE"
++#define DPK_VER_8197F "0x08"
++#define DPK_VER_8703B "NONE"
++#define DPK_VER_8710B "NONE"
++#define DPK_VER_8723D "NONE"
++#define DPK_VER_8822B "NONE"
++#define DPK_VER_8822C "0x1e"
++#define DPK_VER_8821C "NONE"
++#define DPK_VER_8192F "0x0d"
++#define DPK_VER_8198F "0x0e"
++#define DPK_VER_8814B "0x0e"
++#define DPK_VER_8195B "0x0c"
++#define DPK_VER_8812F "0x07"
++#define DPK_VER_8197G "0x09"
++
++/*RFK_INIT version*/
++#define RFK_INIT_VER_8822B "0x8"
++#define RFK_INIT_VER_8822C "0x8"
++#define RFK_INIT_VER_8195B "0x1"
++#define RFK_INIT_VER_8198F "0x8"
++#define RFK_INIT_VER_8814B "0xa"
++#define RFK_INIT_VER_8812F "0x3"
++#define RFK_INIT_VER_8197G "0x4"
++
++/*DACK version*/
++#define DACK_VER_8822C "0xa"
++#define DACK_VER_8814B "0x3"
++
++/*TXGAPK version*/
++#define TXGAPK_VER_8814B "0x1"
++#define TXGAPK_VER_8195B "0x2"
++
++/*Kfree tracking version*/
++#define KFREE_VER_8188E \
++		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
++#define KFREE_VER_8192E \
++		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
++#define KFREE_VER_8192F \
++		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
++#define KFREE_VER_8723B \
++		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
++#define KFREE_VER_8812A \
++		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
++#define KFREE_VER_8821A \
++		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
++#define KFREE_VER_8814A \
++		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
++#define KFREE_VER_8188F \
++		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
++#define KFREE_VER_8197F \
++		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
++#define KFREE_VER_8703B \
++		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
++#define KFREE_VER_8710B \
++		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
++#define KFREE_VER_8723D \
++		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
++#define KFREE_VER_8822B \
++		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
++#define KFREE_VER_8822C \
++		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
++#define KFREE_VER_8821C \
++		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
++#define KFREE_VER_8814B \
++		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
++#define KFREE_VER_8197G \
++		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
++
++#define TSSI_VER_8812F "0x1"
++#define TSSI_VER_8822C "0x1"
++#define TSSI_VER_8821C "0x1"
++#define TSSI_VER_8814B "0x1"
++#define TSSI_VER_8197G "0x1"
++
++/*PA Bias Calibration version*/
++#define PABIASK_VER_8188E \
++	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
++#define PABIASK_VER_8192E \
++	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
++#define PABIASK_VER_8192F \
++	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
++#define PABIASK_VER_8723B \
++	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
++#define PABIASK_VER_8812A \
++	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
++#define PABIASK_VER_8821A \
++	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
++#define PABIASK_VER_8814A \
++	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
++#define PABIASK_VER_8188F \
++	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
++#define PABIASK_VER_8197F \
++	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
++#define PABIASK_VER_8703B \
++	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
++#define PABIASK_VER_8710B \
++	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
++#define PABIASK_VER_8723D \
++	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
++#define PABIASK_VER_8822B \
++	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
++#define PABIASK_VER_8822C \
++	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
++#define PABIASK_VER_8821C \
++	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
++#define PABIASK_VER_8814B \
++	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
++#define PABIASK_VER_8197G \
++	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
++
++#define HALRF_IQK_VER \
++	(dm->support_ic_type == ODM_RTL8188E) ? IQK_VER_8188E : \
++	(dm->support_ic_type == ODM_RTL8192E) ? IQK_VER_8192E : \
++	(dm->support_ic_type == ODM_RTL8192F) ? IQK_VER_8192F : \
++	(dm->support_ic_type == ODM_RTL8723B) ? IQK_VER_8723B : \
++	(dm->support_ic_type == ODM_RTL8812) ? IQK_VER_8812A : \
++	(dm->support_ic_type == ODM_RTL8821) ? IQK_VER_8821A : \
++	(dm->support_ic_type == ODM_RTL8814A) ? IQK_VER_8814A : \
++	(dm->support_ic_type == ODM_RTL8188F) ? IQK_VER_8188F : \
++	(dm->support_ic_type == ODM_RTL8197F) ? IQK_VER_8197F : \
++	(dm->support_ic_type == ODM_RTL8703B) ? IQK_VER_8703B : \
++	(dm->support_ic_type == ODM_RTL8710B) ? IQK_VER_8710B : \
++	(dm->support_ic_type == ODM_RTL8723D) ? IQK_VER_8723D : \
++	(dm->support_ic_type == ODM_RTL8822B) ? IQK_VER_8822B : \
++	(dm->support_ic_type == ODM_RTL8822C) ? IQK_VER_8822C : \
++	(dm->support_ic_type == ODM_RTL8821C) ? IQK_VER_8821C : \
++	(dm->support_ic_type == ODM_RTL8814B) ? IQK_VER_8814B : \
++	(dm->support_ic_type == ODM_RTL8710C) ? IQK_VER_8710C : \
++	(dm->support_ic_type == ODM_RTL8197G) ? IQK_VER_8197G : "unknown"
++
++#define HALRF_LCK_VER \
++	(dm->support_ic_type == ODM_RTL8188E) ? LCK_VER_8188E : \
++	(dm->support_ic_type == ODM_RTL8192E) ? LCK_VER_8192E : \
++	(dm->support_ic_type == ODM_RTL8192F) ? LCK_VER_8192F : \
++	(dm->support_ic_type == ODM_RTL8723B) ? LCK_VER_8723B : \
++	(dm->support_ic_type == ODM_RTL8812) ? LCK_VER_8812A : \
++	(dm->support_ic_type == ODM_RTL8821) ? LCK_VER_8821A : \
++	(dm->support_ic_type == ODM_RTL8814A) ? LCK_VER_8814A : \
++	(dm->support_ic_type == ODM_RTL8188F) ? LCK_VER_8188F : \
++	(dm->support_ic_type == ODM_RTL8197F) ? LCK_VER_8197F : \
++	(dm->support_ic_type == ODM_RTL8703B) ? LCK_VER_8703B : \
++	(dm->support_ic_type == ODM_RTL8710B) ? LCK_VER_8710B : \
++	(dm->support_ic_type == ODM_RTL8723D) ? LCK_VER_8723D : \
++	(dm->support_ic_type == ODM_RTL8822B) ? LCK_VER_8822B : \
++	(dm->support_ic_type == ODM_RTL8822C) ? LCK_VER_8822C : \
++	(dm->support_ic_type == ODM_RTL8821C) ? LCK_VER_8821C : \
++	(dm->support_ic_type == ODM_RTL8814B) ? LCK_VER_8814B : \
++	(dm->support_ic_type == ODM_RTL8710C) ? LCK_VER_8710C : \
++	(dm->support_ic_type == ODM_RTL8710C) ? LCK_VER_8710C : "unknown"
++#define HALRF_POWRTRACKING_VER \
++	(dm->support_ic_type == ODM_RTL8188E) ? PWRTRK_VER_8188E : \
++	(dm->support_ic_type == ODM_RTL8192E) ? PWRTRK_VER_8192E : \
++	(dm->support_ic_type == ODM_RTL8192F) ? PWRTRK_VER_8192F : \
++	(dm->support_ic_type == ODM_RTL8723B) ? PWRTRK_VER_8723B : \
++	(dm->support_ic_type == ODM_RTL8812) ? PWRTRK_VER_8812A : \
++	(dm->support_ic_type == ODM_RTL8821) ? PWRTRK_VER_8821A : \
++	(dm->support_ic_type == ODM_RTL8814A) ? PWRTRK_VER_8814A : \
++	(dm->support_ic_type == ODM_RTL8188F) ? PWRTRK_VER_8188F : \
++	(dm->support_ic_type == ODM_RTL8197F) ? PWRTRK_VER_8197F : \
++	(dm->support_ic_type == ODM_RTL8703B) ? PWRTRK_VER_8703B : \
++	(dm->support_ic_type == ODM_RTL8710B) ? PWRTRK_VER_8710B : \
++	(dm->support_ic_type == ODM_RTL8723D) ? PWRTRK_VER_8723D : \
++	(dm->support_ic_type == ODM_RTL8822B) ? PWRTRK_VER_8822B : \
++	(dm->support_ic_type == ODM_RTL8822C) ? PWRTRK_VER_8822C : \
++	(dm->support_ic_type == ODM_RTL8821C) ? PWRTRK_VER_8821C : \
++	(dm->support_ic_type == ODM_RTL8197G) ? PWRTRK_VER_8197G : "unknown"
++
++#define HALRF_DPK_VER \
++	(dm->support_ic_type == ODM_RTL8188E) ? DPK_VER_8188E : \
++	(dm->support_ic_type == ODM_RTL8192E) ? DPK_VER_8192E : \
++	(dm->support_ic_type == ODM_RTL8192F) ? DPK_VER_8192F : \
++	(dm->support_ic_type == ODM_RTL8723B) ? DPK_VER_8723B : \
++	(dm->support_ic_type == ODM_RTL8812) ? DPK_VER_8812A : \
++	(dm->support_ic_type == ODM_RTL8821) ? DPK_VER_8821A : \
++	(dm->support_ic_type == ODM_RTL8814A) ? DPK_VER_8814A : \
++	(dm->support_ic_type == ODM_RTL8188F) ? DPK_VER_8188F : \
++	(dm->support_ic_type == ODM_RTL8197F) ? DPK_VER_8197F : \
++	(dm->support_ic_type == ODM_RTL8198F) ? DPK_VER_8198F : \
++	(dm->support_ic_type == ODM_RTL8703B) ? DPK_VER_8703B : \
++	(dm->support_ic_type == ODM_RTL8710B) ? DPK_VER_8710B : \
++	(dm->support_ic_type == ODM_RTL8723D) ? DPK_VER_8723D : \
++	(dm->support_ic_type == ODM_RTL8822B) ? DPK_VER_8822B : \
++	(dm->support_ic_type == ODM_RTL8822C) ? DPK_VER_8822C : \
++	(dm->support_ic_type == ODM_RTL8812F) ? DPK_VER_8812F : \
++	(dm->support_ic_type == ODM_RTL8821C) ? DPK_VER_8821C : \
++	(dm->support_ic_type == ODM_RTL8814B) ? DPK_VER_8814B : \
++	(dm->support_ic_type == ODM_RTL8197G) ? DPK_VER_8197G : "unknown"
++
++#define HALRF_KFREE_VER \
++	(dm->support_ic_type == ODM_RTL8188E) ? KFREE_VER_8188E : \
++	(dm->support_ic_type == ODM_RTL8192E) ? KFREE_VER_8192E : \
++	(dm->support_ic_type == ODM_RTL8192F) ? KFREE_VER_8192F : \
++	(dm->support_ic_type == ODM_RTL8723B) ? KFREE_VER_8723B : \
++	(dm->support_ic_type == ODM_RTL8812) ? KFREE_VER_8812A : \
++	(dm->support_ic_type == ODM_RTL8821) ? KFREE_VER_8821A : \
++	(dm->support_ic_type == ODM_RTL8814A) ? KFREE_VER_8814A : \
++	(dm->support_ic_type == ODM_RTL8188F) ? KFREE_VER_8188F : \
++	(dm->support_ic_type == ODM_RTL8197F) ? KFREE_VER_8197F : \
++	(dm->support_ic_type == ODM_RTL8703B) ? KFREE_VER_8703B : \
++	(dm->support_ic_type == ODM_RTL8710B) ? KFREE_VER_8710B : \
++	(dm->support_ic_type == ODM_RTL8723D) ? KFREE_VER_8723D : \
++	(dm->support_ic_type == ODM_RTL8822B) ? KFREE_VER_8822B : \
++	(dm->support_ic_type == ODM_RTL8822C) ? KFREE_VER_8822C : \
++	(dm->support_ic_type == ODM_RTL8821C) ? KFREE_VER_8821C : \
++	(dm->support_ic_type == ODM_RTL8814B) ? KFREE_VER_8814B : \
++	(dm->support_ic_type == ODM_RTL8197G) ? KFREE_VER_8197G : "unknown"
++
++#define HALRF_TSSI_VER \
++	(dm->support_ic_type == ODM_RTL8812F) ? TSSI_VER_8812F : \
++	(dm->support_ic_type == ODM_RTL8822C) ? TSSI_VER_8822C : \
++	(dm->support_ic_type == ODM_RTL8821C) ? TSSI_VER_8821C : \
++	(dm->support_ic_type == ODM_RTL8814B) ? TSSI_VER_8814B : \
++	(dm->support_ic_type == ODM_RTL8197G) ? TSSI_VER_8197G : "unknown"
++
++#define HALRF_PABIASK_VER \
++	(dm->support_ic_type == ODM_RTL8188E) ? PABIASK_VER_8188E : \
++	(dm->support_ic_type == ODM_RTL8192E) ? PABIASK_VER_8192E : \
++	(dm->support_ic_type == ODM_RTL8192F) ? PABIASK_VER_8192F : \
++	(dm->support_ic_type == ODM_RTL8723B) ? PABIASK_VER_8723B : \
++	(dm->support_ic_type == ODM_RTL8812) ? PABIASK_VER_8812A : \
++	(dm->support_ic_type == ODM_RTL8821) ? PABIASK_VER_8821A : \
++	(dm->support_ic_type == ODM_RTL8814A) ? PABIASK_VER_8814A : \
++	(dm->support_ic_type == ODM_RTL8188F) ? PABIASK_VER_8188F : \
++	(dm->support_ic_type == ODM_RTL8197F) ? PABIASK_VER_8197F : \
++	(dm->support_ic_type == ODM_RTL8703B) ? PABIASK_VER_8703B : \
++	(dm->support_ic_type == ODM_RTL8710B) ? PABIASK_VER_8710B : \
++	(dm->support_ic_type == ODM_RTL8723D) ? PABIASK_VER_8723D : \
++	(dm->support_ic_type == ODM_RTL8822B) ? PABIASK_VER_8822B : \
++	(dm->support_ic_type == ODM_RTL8822C) ? PABIASK_VER_8822C : \
++	(dm->support_ic_type == ODM_RTL8821C) ? PABIASK_VER_8821C : \
++	(dm->support_ic_type == ODM_RTL8814B) ? PABIASK_VER_8814B : \
++	(dm->support_ic_type == ODM_RTL8197G) ? PABIASK_VER_8197G : "unknown"
++
++#define HALRF_RFK_INIT_VER \
++	(dm->support_ic_type == ODM_RTL8822B) ? RFK_INIT_VER_8822B : \
++	(dm->support_ic_type == ODM_RTL8822C) ? RFK_INIT_VER_8822C : \
++	(dm->support_ic_type == ODM_RTL8812F) ? RFK_INIT_VER_8812F : \
++	(dm->support_ic_type == ODM_RTL8198F) ? RFK_INIT_VER_8198F : \
++	(dm->support_ic_type == ODM_RTL8814B) ? RFK_INIT_VER_8814B : \
++	(dm->support_ic_type == ODM_RTL8197G) ? RFK_INIT_VER_8197G : "unknown"
++
++#define HALRF_DACK_VER \
++	(dm->support_ic_type == ODM_RTL8822C) ? DACK_VER_8822C : \
++	(dm->support_ic_type == ODM_RTL8814B) ? DACK_VER_8814B : "unknown"
++
++#define IQK_THRESHOLD 8
++#define DPK_THRESHOLD 4
++#define HALRF_ABS(a,b) ((a>b) ? (a-b) : (b-a))
++#define SN 100
++
++#define CCK_TSSI_NUM 6
++#define OFDM_2G_TSSI_NUM 5
++#define OFDM_5G_TSSI_NUM 14
++
++
++
++/*@===========================================================*/
++/*AGC RX High Power mode*/
++/*@===========================================================*/
++#define lna_low_gain_1 0x64
++#define lna_low_gain_2 0x5A
++#define lna_low_gain_3 0x58
++
++/*@============================================================*/
++/*@ enumeration */
++/*@============================================================*/
++
++enum halrf_func_idx { /*F_XXX = PHYDM XXX function*/
++	RF00_PWR_TRK = 0, /*Pow_trk, TSSI_trk*/
++	RF01_IQK = 1,	  /*LOK, IQK*/
++	RF02_LCK = 2,
++	RF03_DPK = 3,
++	RF04_TXGAPK = 4,
++	RF05_DACK = 5,
++	RF06_DPK_TRK = 6,
++	RF07_2GBAND_SHIFT = 7,
++	RF08_RXDCK = 8
++};
++
++enum halrf_ability {
++	HAL_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),
++	HAL_RF_IQK = BIT(RF01_IQK),
++	HAL_RF_LCK = BIT(RF02_LCK),
++	HAL_RF_DPK = BIT(RF03_DPK),
++	HAL_RF_TXGAPK = BIT(RF04_TXGAPK),
++	HAL_RF_DACK = BIT(RF05_DACK),
++	HAL_RF_DPK_TRACK = BIT(RF06_DPK_TRK),
++	HAL_2GBAND_SHIFT = BIT(RF07_2GBAND_SHIFT),
++	HAL_RF_RXDCK = BIT(RF08_RXDCK)
++};
++
++enum halrf_shift_band {
++	HAL_RF_2P4 = 0,
++	HAL_RF_2P3 = 1,
++	HAL_RF_2P5 = 2
++};
++
++enum halrf_dbg_comp {
++	DBG_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),
++	DBG_RF_IQK = BIT(RF01_IQK),
++	DBG_RF_LCK = BIT(RF02_LCK),
++	DBG_RF_DPK = BIT(RF03_DPK),
++	DBG_RF_TXGAPK = BIT(RF04_TXGAPK),
++	DBG_RF_DACK = BIT(RF05_DACK),
++	DBG_RF_MP = BIT(29),
++	DBG_RF_TMP = BIT(30),
++	DBG_RF_INIT = BIT(31)
++};
++
++enum halrf_cmninfo_init {
++	HALRF_CMNINFO_ABILITY = 0,
++	HALRF_CMNINFO_DPK_EN = 1,
++	HALRF_CMNINFO_EEPROM_THERMAL_VALUE,
++	HALRF_CMNINFO_RFK_FORBIDDEN,
++	HALRF_CMNINFO_IQK_SEGMENT,
++	HALRF_CMNINFO_RATE_INDEX,
++	HALRF_CMNINFO_PWT_TYPE,
++	HALRF_CMNINFO_MP_PSD_POINT,
++	HALRF_CMNINFO_MP_PSD_START_POINT,
++	HALRF_CMNINFO_MP_PSD_STOP_POINT,
++	HALRF_CMNINFO_MP_PSD_AVERAGE,
++	HALRF_CMNINFO_IQK_TIMES,
++	HALRF_CMNINFO_MP_POWER_TRACKING_TYPE,
++	HALRF_CMNINFO_POWER_TRACK_CONTROL
++};
++
++enum halrf_cmninfo_hook {
++	HALRF_CMNINFO_CON_TX,
++	HALRF_CMNINFO_SINGLE_TONE,
++	HALRF_CMNINFO_CARRIER_SUPPRESSION,
++	HALRF_CMNINFO_MP_RATE_INDEX,
++	HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY
++};
++
++enum halrf_lna_set {
++	HALRF_LNA_DISABLE = 0,
++	HALRF_LNA_ENABLE = 1,
++};
++
++enum halrf_k_segment_time {
++	SEGMENT_FREE = 0,
++	SEGMENT_10MS = 10, /*10ms*/
++	SEGMENT_30MS = 30, /*30ms*/
++	SEGMENT_50MS = 50, /*50ms*/
++};
++
++#define POWER_INDEX_DIFF 4
++#define TSSI_TXAGC_DIFF 2
++
++#define TSSI_CODE_NUM 84
++
++#define TSSI_SLOPE_2G 8
++#define TSSI_SLOPE_5G 5
++
++#define TSSI_EFUSE_NUM 25
++#define TSSI_EFUSE_KFREE_NUM 4
++
++struct _halrf_tssi_data {
++	s32 cck_offset_patha;
++	s32 cck_offset_pathb;
++	s32 tssi_trk_txagc_offset[PHYDM_MAX_RF_PATH];
++	s32 delta_tssi_txagc_offset[PHYDM_MAX_RF_PATH];
++	s16 txagc_codeword[TSSI_CODE_NUM];
++	u16 tssi_codeword[TSSI_CODE_NUM];
++	s8 tssi_efuse[PHYDM_MAX_RF_PATH][TSSI_EFUSE_NUM];
++	s8 tssi_kfree_efuse[PHYDM_MAX_RF_PATH][TSSI_EFUSE_KFREE_NUM];
++	u8 thermal[PHYDM_MAX_RF_PATH];
++	u32 index[PHYDM_MAX_RF_PATH][14];
++	u8 do_tssi;
++	u8 get_thermal;
++	u8 tssi_finish_bit[PHYDM_MAX_RF_PATH];
++	u8 thermal_trigger;
++};
++
++struct _halrf_txgapk_info {
++	u32 txgapk_rf3f_bp[5][12][PHYDM_MAX_RF_PATH]; /* band(2Gcck/2GOFDM/5GL/5GM/5GH)/idx/path */
++	boolean txgapk_bp_done;
++	s8 offset[12][PHYDM_MAX_RF_PATH];
++	s8 fianl_offset[12][PHYDM_MAX_RF_PATH];
++	u8 read_txgain;
++};
++
++
++/*@============================================================*/
++/*@ structure */
++/*@============================================================*/
++
++struct _hal_rf_ {
++	/*hook*/
++	u8 *test1;
++
++	/*update*/
++	u32 rf_supportability;
++	u8 rf_shift_band;
++	/*u32 halrf_tssi_data;*/
++
++	u8 eeprom_thermal;
++	u8 dpk_en; /*Enable Function DPK OFF/ON = 0/1*/
++	boolean dpk_done;
++	u64 dpk_progressing_time;
++	u64 iqk_progressing_time;
++	u32 fw_ver;
++
++	boolean *is_con_tx;
++	boolean *is_single_tone;
++	boolean *is_carrier_suppresion;
++	boolean is_dpk_in_progress;
++	boolean is_tssi_in_progress;
++	boolean is_bt_iqk_timeout;
++	boolean is_rfk_h2c_timeout;
++	boolean aac_checked;
++	boolean is_txgapk_in_progress;
++
++	u8 *mp_rate_index;
++	u32 *manual_rf_supportability;
++	u32 p_rate_index;
++	u8 pwt_type;
++	u32 rf_dbg_comp;
++#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	struct _halrf_psd_data halrf_psd_data;
++	struct _halrf_tssi_data halrf_tssi_data;
++#endif
++	struct _halrf_txgapk_info halrf_txgapk_info;
++	u8 power_track_type;
++	u8 mp_pwt_type;
++	u8 pre_band_type;
++};
++
++/*@============================================================*/
++/*@ function prototype */
++/*@============================================================*/
++
++#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
++	RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
++	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
++	RTL8812F_SUPPORT == 1 || RTL8710C_SUPPORT == 1 ||\
++	RTL8197G_SUPPORT == 1)
++void halrf_iqk_info_dump(void *dm_void, u32 *_used, char *output,
++			 u32 *_out_len);
++
++void halrf_iqk_hwtx_check(void *dm_void, boolean is_check);
++#endif
++
++u8 halrf_match_iqk_version(void *dm_void);
++
++void halrf_support_ability_debug(void *dm_void, char input[][16], u32 *_used,
++				 char *output, u32 *_out_len);
++#ifdef CONFIG_2G_BAND_SHIFT
++void halrf_support_band_shift_debug(void *dm_void, char input[][16], u32 *_used,
++				    char *output, u32 *_out_len);
++#endif
++void halrf_cmn_info_init(void *dm_void, enum halrf_cmninfo_init cmn_info,
++			 u32 value);
++
++void halrf_cmn_info_hook(void *dm_void, enum halrf_cmninfo_hook cmn_info,
++			 void *value);
++
++void halrf_cmn_info_set(void *dm_void, u32 cmn_info, u64 value);
++
++u64 halrf_cmn_info_get(void *dm_void, u32 cmn_info);
++
++void halrf_watchdog(void *dm_void);
++
++void halrf_supportability_init(void *dm_void);
++
++void halrf_init(void *dm_void);
++
++void halrf_iqk_trigger(void *dm_void, boolean is_recovery);
++
++void halrf_rfk_handshake(void *dm_void, boolean is_before_k);
++
++void halrf_rf_k_connect_trigger(void *dm_void, boolean is_recovery,
++				enum halrf_k_segment_time seg_time);
++
++void halrf_segment_iqk_trigger(void *dm_void, boolean clear,
++			       boolean segment_iqk);
++
++void halrf_lck_trigger(void *dm_void);
++
++void halrf_iqk_debug(void *dm_void, u32 *const dm_value, u32 *_used,
++		     char *output, u32 *_out_len);
++
++void phydm_get_iqk_cfir(void *dm_void, u8 idx, u8 path, boolean debug);
++
++void halrf_iqk_xym_read(void *dm_void, u8 path, u8 xym_type);
++
++void halrf_rf_lna_setting(void *dm_void, enum halrf_lna_set type);
++
++void halrf_do_imr_test(void *dm_void, u8 data);
++
++u32 halrf_psd_log2base(u32 val);
++
++void halrf_dpk_trigger(void *dm_void);
++
++void halrf_txgapk_trigger(void *dm_void);
++
++u8 halrf_dpk_result_check(void *dm_void);
++
++void halrf_dpk_sram_read(void *dm_void);
++
++void halrf_dpk_enable_disable(void *dm_void);
++
++void halrf_dpk_track(void *dm_void);
++
++void halrf_dpk_reload(void *dm_void);
++
++void halrf_dpk_debug_cmd(void *dm_void, char input[][16], u32 *_used,
++			 char *output, u32 *_out_len);
++
++void halrf_dpk_c2h_report_transfer(void	*dm_void, boolean is_ok, u8 *buf, u8 buf_size);
++
++void halrf_dpk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size);
++
++/*Global function*/
++
++void halrf_reload_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num);
++
++void halrf_reload_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num,
++		       u8 ss);
++
++void halrf_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num);
++
++void halrf_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num, u8 ss);
++
++void halrf_mode(void *dm_void, u32 *i_value, u32 *q_value);
++
++boolean halrf_compare(void *dm_void, u32 value);
++
++u32 halrf_delta(void *dm_void, u32 v1, u32 v2);
++
++void halrf_minmax_compare(void *dm_void, u32 value, u32 *min, u32 *max);
++
++void halrf_b_sort(void *dm_void, u32 *iv, u32 *qv);
++
++void halrf_bubble(void *dm_void, u32 *v1, u32 *v2);
++
++void halrf_swap(void *dm_void, u32 *v1, u32 *v2);
++
++enum hal_status
++halrf_config_rfk_with_header_file(void *dm_void, u32 config_type);
++
++#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
++	RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
++	RTL8814B_SUPPORT == 1  || RTL8822C_SUPPORT == 1 ||\
++	RTL8812F_SUPPORT == 1 || RTL8710C_SUPPORT == 1 ||\
++	RTL8197G_SUPPORT == 1)
++void halrf_iqk_dbg(void *dm_void);
++#endif
++
++void halrf_tssi_get_efuse(void *dm_void);
++
++void halrf_do_tssi(void *dm_void);
++
++void halrf_set_tssi_enable(void *dm_void, boolean enable);
++
++void halrf_do_thermal(void *dm_void);
++
++u32 halrf_set_tssi_value(void *dm_void, u32 tssi_value);
++
++void halrf_set_tssi_power(void *dm_void, s8 power);
++
++void halrf_tssi_set_de_for_tx_verify(void *dm_void, u32 tssi_de, u8 path);
++
++u32 halrf_query_tssi_value(void *dm_void);
++
++void halrf_tssi_cck(void *dm_void);
++
++void halrf_thermal_cck(void *dm_void);
++
++void halrf_tssi_set_de(void *dm_void);
++
++void halrf_tssi_dck(void *dm_void, u8 direct_do);
++
++void halrf_calculate_tssi_codeword(void *dm_void);
++
++void halrf_set_tssi_codeword(void *dm_void);
++
++u8 halrf_get_tssi_codeword_for_txindex(void *dm_void);
++
++void halrf_tssi_clean_de(void *dm_void);
++
++u32 halrf_tssi_trigger_de(void *dm_void, u8 path);
++
++u32 halrf_tssi_get_de(void *dm_void, u8 path);
++
++void halrf_tssi_trigger(void *dm_void);
++
++void halrf_txgapk_write_gain_table(void *dm_void);
++
++void halrf_txgapk_reload_tx_gain(void *dm_void);
++
++void halrf_txgap_enable_disable(void *dm_void, u8 enable);
++
++void halrf_set_dpk_track(void *dm_void, u8 enable);
++
++void halrf_set_dpkbychannel(void *dm_void, boolean dpk_by_ch);
++
++void halrf_set_dpkenable(void *dm_void, boolean is_dpk_enable);
++
++boolean halrf_get_dpkbychannel(void *dm_void);
++
++boolean halrf_get_dpkenable(void *dm_void);
++
++void _iqk_check_if_reload(void *dm_void);
++
++void halrf_do_rxbb_dck(void *dm_void);
++
++void config_halrf_path_adda_setting_trigger(void *dm_void);
++
++void halrf_reload_iqk(void *dm_void, boolean reset);
++
++void halrf_dack_dbg(void *dm_void);
++
++void halrf_dack_trigger(void *dm_void, boolean force);
++
++void halrf_dack_restore(void *dm_void);
++
++void halrf_iqk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size);
++
++void halrf_set_rfsupportability(void *dm_void);
++
++void halrf_rxdck(void *dm_void);
++
++void halrf_delay_10us(u16 v1);
++
++void halrf_dump_rfk_reg(void *dm_void, char input[][16], u32 *_used,
++			      char *output, u32 *_out_len);
++
++#endif /*__HALRF_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_debug.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_debug.c
+new file mode 100644
+index 000000000..b0b8fffb2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_debug.c
+@@ -0,0 +1,390 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ * ************************************************************
++ */
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++void halrf_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len)
++{
++#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 rf_release_ver = 0;
++
++	switch (dm->support_ic_type) {
++#if (RTL8814A_SUPPORT)
++	case ODM_RTL8814A:
++		rf_release_ver = RF_RELEASE_VERSION_8814A;
++		break;
++#endif
++
++#if (RTL8821C_SUPPORT)
++	case ODM_RTL8821C:
++		rf_release_ver = RF_RELEASE_VERSION_8821C;
++		break;
++#endif
++
++#if (RTL8822B_SUPPORT)
++	case ODM_RTL8822B:
++		rf_release_ver = RF_RELEASE_VERSION_8822B;
++		break;
++#endif
++
++#if (RTL8822C_SUPPORT)
++	case ODM_RTL8822C:
++		rf_release_ver = RF_RELEASE_VERSION_8822C;
++		break;
++#endif
++
++#if (RTL8814B_SUPPORT)
++	case ODM_RTL8814B:
++		rf_release_ver = RF_RELEASE_VERSION_8814B;
++		break;
++#endif
++
++#if (RTL8812F_SUPPORT)
++	case ODM_RTL8812F:
++		rf_release_ver = RF_RELEASE_VERSION_8812F;
++		break;
++#endif
++
++#if (RTL8198F_SUPPORT)
++	case ODM_RTL8198F:
++		rf_release_ver = RF_RELEASE_VERSION_8198F;
++		break;
++#endif
++
++#if (RTL8197F_SUPPORT)
++	case ODM_RTL8197F:
++		rf_release_ver = RF_RELEASE_VERSION_8197F;
++		break;
++#endif
++
++#if (RTL8192F_SUPPORT)
++	case ODM_RTL8192F:
++		rf_release_ver = RF_RELEASE_VERSION_8192F;
++		break;
++#endif
++
++#if (RTL8710B_SUPPORT)
++	case ODM_RTL8710B:
++		rf_release_ver = RF_RELEASE_VERSION_8710B;
++		break;
++#endif
++
++#if (RTL8195B_SUPPORT)
++	case ODM_RTL8195B:
++		rf_release_ver = RF_RELEASE_VERSION_8195B;
++		break;
++#endif
++	}
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %d\n",
++		 "RF Para Release Ver", rf_release_ver);
++
++	/* HAL RF version List */
++	PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n",
++		 "% HAL RF version %");
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "Power Tracking", HALRF_POWRTRACKING_VER);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "  %-35s: %s %s\n", "IQK",
++		 (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW" :
++		 HALRF_IQK_VER,
++		 (halrf_match_iqk_version(dm_void)) ? "(match)" : "(mismatch)");
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "LCK", HALRF_LCK_VER);
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "DPK", HALRF_DPK_VER);
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "TSSI", HALRF_TSSI_VER);
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "KFREE", HALRF_KFREE_VER);
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "TX 2G Current Calibration", HALRF_PABIASK_VER);
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "RFK Init. Parameter", HALRF_RFK_INIT_VER);
++
++	*_used = used;
++	*_out_len = out_len;
++#endif
++}
++
++void halrf_debug_trace(void *dm_void, char input[][16], u32 *_used,
++		       char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	u32 one = 1;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 rf_var[10] = {0};
++	u8 i;
++
++	for (i = 0; i < 5; i++)
++		if (input[i + 1])
++			PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &rf_var[i]);
++
++	if (rf_var[0] == 100) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\n[DBG MSG] RF Selection\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "00. (( %s ))TX_PWR_TRACK\n",
++			 ((rf->rf_dbg_comp & DBG_RF_TX_PWR_TRACK) ? ("V") :
++			 (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "01. (( %s ))IQK\n",
++			 ((rf->rf_dbg_comp & DBG_RF_IQK) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "02. (( %s ))LCK\n",
++			 ((rf->rf_dbg_comp & DBG_RF_LCK) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "03. (( %s ))DPK\n",
++			 ((rf->rf_dbg_comp & DBG_RF_DPK) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "04. (( %s ))TXGAPK\n",
++			 ((rf->rf_dbg_comp & DBG_RF_TXGAPK) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "29. (( %s ))MP\n",
++			 ((rf->rf_dbg_comp & DBG_RF_MP) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "30. (( %s ))TMP\n",
++			 ((rf->rf_dbg_comp & DBG_RF_TMP) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "31. (( %s ))INIT\n",
++			 ((rf->rf_dbg_comp & DBG_RF_INIT) ? ("V") : (".")));
++
++	} else if (rf_var[0] == 101) {
++		rf->rf_dbg_comp = 0;
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Disable all DBG COMP\n");
++	} else {
++		if (rf_var[1] == 1) /*enable*/
++			rf->rf_dbg_comp |= (one << rf_var[0]);
++		else if (rf_var[1] == 2) /*disable*/
++			rf->rf_dbg_comp &= ~(one << rf_var[0]);
++	}
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\nCurr-RF_Dbg_Comp = 0x%x\n", rf->rf_dbg_comp);
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void halrf_dack_debug_cmd(void *dm_void, char input[][16])
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	u32 dm_value[10] = {0};
++	u8 i;
++
++	for (i = 0; i < 7; i++)
++		if (input[i + 1])
++			PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]);
++
++	if (dm_value[0] == 1)
++		halrf_dack_trigger(dm, true);
++	else			
++		halrf_dack_trigger(dm, false);	
++}
++
++struct halrf_command {
++	char name[16];
++	u8 id;
++};
++
++enum halrf_CMD_ID {
++	HALRF_HELP,
++	HALRF_SUPPORTABILITY,
++	HALRF_DBG_COMP,
++	HALRF_PROFILE,
++	HALRF_IQK_INFO,
++	HALRF_IQK,
++	HALRF_IQK_DEBUG,
++	HALRF_DPK,
++	HALRF_DACK,
++	HALRF_DACK_DEBUG,
++	HALRF_DUMP_RFK_REG,
++#ifdef CONFIG_2G_BAND_SHIFT
++	HAL_BAND_SHIFT,
++#endif
++};
++
++struct halrf_command halrf_cmd_ary[] = {
++	{"-h", HALRF_HELP},
++	{"ability", HALRF_SUPPORTABILITY},
++	{"dbg", HALRF_DBG_COMP},
++	{"profile", HALRF_PROFILE},
++	{"iqk_info", HALRF_IQK_INFO},
++	{"iqk", HALRF_IQK},
++	{"iqk_dbg", HALRF_IQK_DEBUG},
++	{"dpk", HALRF_DPK},
++	{"dack", HALRF_DACK},
++	{"dack_dbg", HALRF_DACK_DEBUG},
++	{"dump_rfk_reg", HALRF_DUMP_RFK_REG},
++#ifdef CONFIG_2G_BAND_SHIFT
++	{"band_shift", HAL_BAND_SHIFT},
++#endif
++};
++
++void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
++		      u32 *_out_len, u32 input_num)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
++	u8 id = 0;
++	u32 rf_var[10] = {0};
++	u32 i, input_idx = 0;
++	u32 halrf_ary_size =
++			sizeof(halrf_cmd_ary) / sizeof(struct halrf_command);
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	/* Parsing Cmd ID */
++	for (i = 0; i < halrf_ary_size; i++) {
++		if (strcmp(halrf_cmd_ary[i].name, input[1]) == 0) {
++			id = halrf_cmd_ary[i].id;
++			break;
++		}
++	}
++
++	if (i == halrf_ary_size) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "RF Cmd not found\n");
++		return;
++	}
++
++	switch (id) {
++	case HALRF_HELP:
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "RF cmd ==>\n");
++
++		for (i = 0; i < halrf_ary_size - 1; i++) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "  %-5d: %s\n", i, halrf_cmd_ary[i + 1].name);
++		}
++		break;
++	case HALRF_SUPPORTABILITY:
++		halrf_support_ability_debug(dm, &input[0], &used, output,
++					    &out_len);
++		break;
++#ifdef CONFIG_2G_BAND_SHIFT
++	case HAL_BAND_SHIFT:
++		halrf_support_band_shift_debug(dm, &input[0], &used, output,
++					       &out_len);
++		break;
++#endif
++	case HALRF_DBG_COMP:
++		halrf_debug_trace(dm, &input[0], &used, output, &out_len);
++		break;
++	case HALRF_PROFILE:
++		halrf_basic_profile(dm, &used, output, &out_len);
++		break;
++	case HALRF_IQK_INFO:
++#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
++		halrf_iqk_info_dump(dm, &used, output, &out_len);
++#endif
++		break;
++	case HALRF_IQK:
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "TRX IQK Trigger\n");
++		halrf_iqk_trigger(dm, false);
++#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
++		halrf_iqk_info_dump(dm, &used, output, &out_len);
++#endif
++		break;
++	case HALRF_IQK_DEBUG:
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "IQK DEBUG!!!!!\n");
++		for (i = 0; i < 5; i++) {
++			if (input[i + 1]) {
++				PHYDM_SSCANF(input[i + 2], DCMD_HEX,
++					     &rf_var[i]);
++				input_idx++;
++			}
++		}
++
++		if (input_idx >= 1) {
++#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
++			if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8822C | ODM_RTL8814B))
++				halrf_iqk_debug(dm, (u32 *)rf_var, &used,
++						output, &out_len);
++#endif
++		}
++		break;
++	case HALRF_DPK:
++		halrf_dpk_debug_cmd(dm, input, &used, output, &out_len);
++		break;
++	case HALRF_DACK:
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "DACK Trigger\n");
++		halrf_dack_debug_cmd(dm, &input[0]);
++		break;
++	case HALRF_DACK_DEBUG:
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "DACK DEBUG\n");
++		halrf_dack_dbg(dm);
++		break;
++	case HALRF_DUMP_RFK_REG:
++		halrf_dump_rfk_reg(dm, input, &used, output, &out_len);
++		break;
++	default:
++		break;
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++#endif
++}
++
++void halrf_init_debug_setting(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	rf->rf_dbg_comp =
++
++#if DBG
++#if 0
++	/*DBG_RF_TX_PWR_TRACK	|*/
++	/*DBG_RF_IQK		| */
++	/*DBG_RF_LCK		| */
++	/*DBG_RF_DPK		| */
++	/*DBG_RF_DACK		| */
++	/*DBG_RF_TXGAPK		| */
++	/*DBG_RF_MP			| */
++	/*DBG_RF_TMP		| */
++	/*DBG_RF_INIT		| */
++#endif
++#endif
++	0;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_debug.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_debug.h
+new file mode 100644
+index 000000000..ff1ff96d2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_debug.h
+@@ -0,0 +1,123 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_DEBUG_H__
++#define __HALRF_DEBUG_H__
++
++/*@============================================================*/
++/*@include files*/
++/*@============================================================*/
++
++/*@============================================================*/
++/*@Definition */
++/*@============================================================*/
++
++#if DBG
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++#define RF_DBG(dm, comp, fmt, args...)                     \
++	do {                                               \
++		if ((comp) & dm->rf_table.rf_dbg_comp) { \
++			pr_debug("[RF] ");                 \
++			RT_PRINTK(fmt, ##args);            \
++		}                                          \
++	} while (0)
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++
++static __inline void RF_DBG(PDM_ODM_T dm, int comp, char *fmt, ...)
++{
++	RT_STATUS rt_status;
++	va_list args;
++	char buf[PRINT_MAX_SIZE] = {0};
++
++	if ((comp & dm->rf_table.rf_dbg_comp) == 0)
++		return;
++
++	if (fmt == NULL)
++		return;
++
++	va_start(args, fmt);
++	rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
++	va_end(args);
++
++	if (rt_status != RT_STATUS_SUCCESS) {
++		DbgPrint("Failed (%d) to print message to buffer\n", rt_status);
++		return;
++	}
++
++	DbgPrint("[RF] %s", buf);
++}
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
++
++#define RF_DBG(dm, comp, fmt, args...)                     \
++	do {                                               \
++		if ((comp) & dm->rf_table.rf_dbg_comp) { \
++			RT_DEBUG(COMP_PHYDM, DBG_DMESG, "[RF] " fmt, ##args);  \
++		}                                          \
++	} while (0)
++
++#else
++#define RF_DBG(dm, comp, fmt, args...)                                         \
++	do {                                                                   \
++		struct dm_struct *__dm = dm;                                   \
++		if ((comp) & __dm->rf_table.rf_dbg_comp) {                     \
++			RT_TRACE(((struct rtl_priv *)__dm->adapter),           \
++				 COMP_PHYDM, DBG_DMESG, "[RF] " fmt, ##args);  \
++		}                                                              \
++	} while (0)
++#endif
++
++#else /*#if DBG*/
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++static __inline void RF_DBG(struct dm_struct *dm, int comp, char *fmt, ...)
++{
++}
++#else
++#define RF_DBG(dm, comp, fmt, args...)
++#endif
++
++#endif /*#if DBG*/
++
++/*@============================================================*/
++/*@ enumeration */
++/*@============================================================*/
++
++/*@============================================================*/
++/*@ structure */
++/*@============================================================*/
++
++/*@============================================================*/
++/*@ function prototype */
++/*@============================================================*/
++
++void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
++		      u32 *_out_len, u32 input_num);
++
++void halrf_init_debug_setting(void *dm_void);
++
++#endif /*__HALRF_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_dpk.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_dpk.h
+new file mode 100644
+index 000000000..daac1ea84
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_dpk.h
+@@ -0,0 +1,150 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_DPK_H__
++#define __HALRF_DPK_H__
++
++/*@--------------------------Define Parameters-------------------------------*/
++#define GAIN_LOSS 1
++#define DO_DPK 2
++#define DPK_ON 3
++#define GAIN_LOSS_PULSE 4
++#define DPK_PAS 5
++#define DPK_LMS 6
++#define DPK_LOK 4
++#define DPK_TXK 5
++#define DAGC 4
++#define LOSS_CHK 0
++#define GAIN_CHK 1
++#define PAS_READ 2
++#define AVG_THERMAL_NUM 8
++#define AVG_THERMAL_NUM_DPK 8
++#define THERMAL_DPK_AVG_NUM 4
++
++/*define RF path numer*/
++#if (RTL8198F_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
++#define KPATH 4
++#elif (RTL8192F_SUPPORT == 1 || RTL8197F_SUPPORT == 1 ||RTL8197G_SUPPORT == 1 ||\
++	RTL8822C_SUPPORT == 1 || RTL8812F_SUPPORT == 1)
++#define KPATH 2
++#else
++#define KPATH 1
++#endif
++
++#if (RTL8814B_SUPPORT == 1 || RTL8721D_SUPPORT == 1)
++#define GROUP_5G 6
++#elif (RTL8195B_SUPPORT == 1)
++#define GROUP_5G 13
++#endif
++
++/*@---------------------------End Define Parameters---------------------------*/
++
++struct dm_dpk_info {
++
++	boolean	is_dpk_enable;
++	boolean	is_dpk_pwr_on;
++	boolean	is_dpk_by_channel;
++	boolean is_tssi_mode;
++	u8	dpk_status;			/*bit[0]:reload;bit[1]:cal;bit[2]:cal_ok*/
++	u16	dpk_path_ok;
++	/*@BIT(15)~BIT(12) : 5G reserved, BIT(11)~BIT(8) 5G_S3~5G_S0*/
++	/*@BIT(7)~BIT(4) : 2G reserved, BIT(3)~BIT(0) 2G_S3~2G_S0*/
++	u8	thermal_dpk[KPATH];					/*path*/	
++	u8	thermal_dpk_avg[KPATH][AVG_THERMAL_NUM_DPK];	/*path*/
++	u8	pre_pwsf[KPATH];
++	u8	thermal_dpk_avg_index;
++	u32	gnt_control;
++	u32	gnt_value;
++	u8	dpk_ch;
++	u8	dpk_band;
++	u8	dpk_bw;
++	u32	dpk_rf18[2];
++	u32	dpk_cal_cnt;
++	u32	dpk_ok_cnt;
++	u32	dpk_reload_cnt;
++
++#if (RTL8822C_SUPPORT == 1 || RTL8812F_SUPPORT == 1 || RTL8197G_SUPPORT == 1)
++	u16	dc_i[2];			/*MDPD DC I path*/
++	u16	dc_q[2];			/*MDPD DC Q path*/
++	u8	corr_val[2];			/*Corr value path*/
++	u8	corr_idx[2];			/*Corr index path*/
++#endif
++
++#if (RTL8822C_SUPPORT == 1 || RTL8812F_SUPPORT == 1)
++	u8	result[2];			/*path*/
++	u8	dpk_txagc[2];			/*path*/
++	u32	coef[2][20];			/*path/MDPD coefficient*/
++	u16	dpk_gs[2];			/*MDPD coef gs*/
++	u8	thermal_dpk_delta[2];		/*path*/
++#endif
++
++#if (RTL8198F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8197F_SUPPORT == 1 ||\
++	RTL8814B_SUPPORT == 1 || RTL8197G_SUPPORT == 1)
++	/*2G DPK data*/
++	u8 	dpk_result[KPATH][3];			/*path/group*/
++	u8 	pwsf_2g[KPATH][3];			/*path/group*/	
++	u32	lut_2g_even[KPATH][3][64];		/*path/group/LUT data*/
++	u32	lut_2g_odd[KPATH][3][64];		/*path/group/LUT data*/
++	s16	tmp_pas_i[32];			/*PAScan I data*/
++	s16	tmp_pas_q[32];			/*PAScan Q data*/
++#endif
++
++#if (RTL8814B_SUPPORT == 1)
++	/*5G DPK data*/
++	u8	dpk_5g_result[KPATH][GROUP_5G];			/*path/group*/
++	u8	pwsf_5g[KPATH][GROUP_5G];			/*path/group*/
++	u32	lut_5g[KPATH][GROUP_5G][64];			/*path/group/LUT data*/
++	u32	lut_2g[KPATH][GROUP_5G][64];			/*path/group/LUT data*/
++	u8	rxbb[4];			/*path/group*/
++	u8	txbb[4];			/*path/group*/
++	u8	tx_gain;
++#endif
++
++#if (RTL8195B_SUPPORT == 1 || RTL8721D_SUPPORT == 1)
++		u8	dpk_txagc;
++		/*2G DPK data*/
++	u8	dpk_2g_result[KPATH][3];			/*path/group*/
++	u8	pwsf_2g[KPATH][3];			/*path/group*/
++	u32	lut_2g_even[KPATH][3][16];		/*path/group/LUT data*/
++	u32	lut_2g_odd[KPATH][3][16];		/*path/group/LUT data*/
++		/*5G DPK data*/
++	u8	dpk_5g_result[KPATH][GROUP_5G];			/*path/group*/
++	u8	pwsf_5g[KPATH][GROUP_5G];			/*path/group*/
++	u32	lut_5g_even[KPATH][GROUP_5G][16];		/*path/group/LUT data*/
++	u32	lut_5g_odd[KPATH][GROUP_5G][16];		/*path/group/LUT data*/
++#endif
++};
++
++#if (RTL8822C_SUPPORT == 1)
++struct dm_dpk_c2h_report {
++	u8	result[2];		/*ch0_result/ch1_result*/
++	u8	therm[2][2];		/*therm0_s0/therm0_s1/therm1_s0/therm1_s1*/
++	u8	therm_delta[2][2];	/*therm_delta0_s0/therm_delta0_s1/therm_delta1_s0/therm_delta1_s1*/
++	u32	dpk_rf18[2];		/*dpk_ch0/dpk_ch1*/
++	u8	dpk_status;		/*dpk_status*/
++};
++#endif
++
++#endif /*__HALRF_DPK_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_features.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_features.h
+new file mode 100644
+index 000000000..da97614be
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_features.h
+@@ -0,0 +1,43 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_FEATURES_H__
++#define __HALRF_FEATURES_H__
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++
++#define CONFIG_HALRF_POWERTRACKING 1
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++
++#define CONFIG_HALRF_POWERTRACKING 1
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++
++#define CONFIG_HALRF_POWERTRACKING 1
++
++#endif
++
++#endif /*#ifndef __HALRF_FEATURES_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_iqk.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_iqk.h
+new file mode 100644
+index 000000000..e97637b80
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_iqk.h
+@@ -0,0 +1,149 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_IQK_H__
++#define __HALRF_IQK_H__
++
++/*@--------------------------Define Parameters-------------------------------*/
++#define LOK_delay 1
++#define WBIQK_delay 10
++#define TX_IQK 0
++#define RX_IQK 1
++#define TXIQK 0
++#define RXIQK1 1
++#define RXIQK2 2
++#define kcount_limit_80m 2
++#define kcount_limit_others 4
++#define rxiqk_gs_limit 6
++#define TXWBIQK_EN 1
++#define RXWBIQK_EN 1
++#if (RTL8814A_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
++	RTL8814B_SUPPORT)
++#define NUM 4
++#elif (RTL8822B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
++	RTL8812F_SUPPORT == 1 ||	RTL8197G_SUPPORT == 1)
++#define NUM 2
++#else
++#define NUM 1
++#endif
++
++/*@-----------------------End Define Parameters-----------------------*/
++
++struct dm_dack_info {
++	boolean dack_en;
++	u16 msbk_d[2][2][15];
++	u8 dck_d[2][2][2];
++	u16 biask_d[2][2];
++};
++
++struct dm_iqk_info {
++	boolean lok_fail[NUM];
++	boolean iqk_fail[2][NUM];
++	u32 iqc_matrix[2][NUM];
++	u8 iqk_times;
++	u32 rf_reg18;
++	u32 rf_reg08;
++	u32 lna_idx;
++	u8 iqk_step;
++	u8 rxiqk_step;
++	u8 tmp1bcc;
++	u8 txgain;
++	u32 txgain56;
++	u8 kcount;
++	u8 rfk_ing; /*bit0:IQKing, bit1:LCKing, bit2:DPKing*/
++	boolean rfk_forbidden;
++	u8 rxbb;
++	u32 rf_reg58;
++	boolean segment_iqk;
++	boolean is_tssi_mode;
++	u8 iqk_band;
++	u8 iqk_ch;
++	u8 iqk_bw;
++#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
++	RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
++	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
++	RTL8812F_SUPPORT == 1 || RTL8197G_SUPPORT == 1 ||\
++	RTL8710C_SUPPORT == 1)
++	u32 iqk_channel[2];
++	boolean iqk_fail_report[2][NUM][2]; /*channel/path/TRX(TX:0, RX:1) */
++	/*channel / path / TRX(TX:0, RX:1) / CFIR_real*/
++	/*channel index = 2 is just for debug*/
++#if (RTL8814B_SUPPORT == 1)
++	u16 iqk_cfir_real[3][NUM][2][19];
++	u16 iqk_cfir_imag[3][NUM][2][19];
++#elif (RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 )
++	u16 iqk_cfir_real[3][2][2][17];
++	/*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
++	/*channel index = 2 is just for debug*/
++	u16 iqk_cfir_imag[3][2][2][17];
++	/*times/path*/
++#elif (RTL8195B_SUPPORT == 1)
++	u32 iqk_cfir_real[3][NUM][2][9];
++	u32 iqk_cfir_imag[3][NUM][2][9];
++	/*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
++	/*channel index = 2 is just for debug*/
++#else
++	u32 iqk_cfir_real[3][NUM][2][8];
++	/*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
++	/*channel index = 2 is just for debug*/
++	u32 iqk_cfir_imag[3][NUM][2][8];
++#endif
++
++#if (RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 )
++	u32 rx_cfir_real[2][2][17];
++	u32 rx_cfir_imag[2][2][17];
++	u32 rx_cfir[2][2];
++#endif
++	u8 retry_count[2][NUM][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */
++	u8 gs_retry_count[2][NUM][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */
++	/* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */
++	u8 rxiqk_fail_code[2][NUM];
++	u32 lok_idac[2][NUM]; /*channel / path*/
++	u16 rxiqk_agc[2][NUM]; /*channel / path*/
++	u32 bypass_iqk[2][NUM]; /*channel / 0xc94/0xe94*/
++	u32 txgap_result[8]; /*txagpK result  */
++	u32 tmp_gntwl;
++	boolean is_btg;
++	boolean isbnd;
++	boolean is_reload;
++	boolean is_hwtx;
++	boolean xym_read;
++	boolean trximr_enable;
++#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
++	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
++	u32 rx_xym[2][10];
++	u32 tx_xym[2][10];
++	u32 gs1_xym[2][6];
++	u32 gs2_xym[2][6];
++	u32 rxk1_xym[2][6];
++#endif
++#if (RTL8710C_SUPPORT == 1 || RTL8197G_SUPPORT == 1 )
++	u32 txxy[2][2];
++	u32 rxxy[2][2];
++#endif
++#endif
++};
++
++#endif /*__HALRF_IQK_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_kfree.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_kfree.c
+new file mode 100644
+index 000000000..d1f51a7ec
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_kfree.c
+@@ -0,0 +1,2940 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@============================================================*/
++/*@include files*/
++/*@============================================================*/
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++/*@<YuChen, 150720> Add for KFree Feature Requested by RF David.*/
++/*@This is a phydm API*/
++
++void phydm_set_kfree_to_rf_8814a(void *dm_void, u8 e_rf_path, u8 data)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
++	boolean is_odd;
++	u32 tx_gain_bitmask = (BIT(17) | BIT(16) | BIT(15));
++
++	if ((data % 2) != 0) { /*odd->positive*/
++		data = data - 1;
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), 1);
++		is_odd = true;
++	} else { /*even->negative*/
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), 0);
++		is_odd = false;
++	}
++	RF_DBG(dm, DBG_RF_MP, "phy_ConfigKFree8814A(): RF_0x55[19]= %d\n",
++	       is_odd);
++	switch (data) {
++	case 0:
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 0);
++		cali_info->kfree_offset[e_rf_path] = 0;
++		break;
++	case 2:
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 0);
++		cali_info->kfree_offset[e_rf_path] = 0;
++		break;
++	case 4:
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 1);
++		cali_info->kfree_offset[e_rf_path] = 1;
++		break;
++	case 6:
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 1);
++		cali_info->kfree_offset[e_rf_path] = 1;
++		break;
++	case 8:
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 2);
++		cali_info->kfree_offset[e_rf_path] = 2;
++		break;
++	case 10:
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 2);
++		cali_info->kfree_offset[e_rf_path] = 2;
++		break;
++	case 12:
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 3);
++		cali_info->kfree_offset[e_rf_path] = 3;
++		break;
++	case 14:
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 3);
++		cali_info->kfree_offset[e_rf_path] = 3;
++		break;
++	case 16:
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 4);
++		cali_info->kfree_offset[e_rf_path] = 4;
++		break;
++	case 18:
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 4);
++		cali_info->kfree_offset[e_rf_path] = 4;
++		break;
++	case 20:
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 5);
++		cali_info->kfree_offset[e_rf_path] = 5;
++		break;
++
++	default:
++		break;
++	}
++
++	if (!is_odd) {
++		/*that means Kfree offset is negative, we need to record it.*/
++		cali_info->kfree_offset[e_rf_path] =
++				(-1) * cali_info->kfree_offset[e_rf_path];
++		RF_DBG(dm, DBG_RF_MP,
++		       "phy_ConfigKFree8814A(): kfree_offset = %d\n",
++		       cali_info->kfree_offset[e_rf_path]);
++	} else {
++		RF_DBG(dm, DBG_RF_MP,
++		       "phy_ConfigKFree8814A(): kfree_offset = %d\n",
++		       cali_info->kfree_offset[e_rf_path]);
++	}
++}
++
++void phydm_get_thermal_trim_offset_8821c(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_therm = 0xff;
++
++	odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_21C, &pg_therm, false);
++
++	if (pg_therm != 0xff) {
++		pg_therm = pg_therm & 0x1f;
++		if ((pg_therm & BIT(0)) == 0)
++			power_trim_info->thermal = (-1 * (pg_therm >> 1));
++		else
++			power_trim_info->thermal = (pg_therm >> 1);
++
++		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8821c thermal trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8821c thermal:%d\n",
++		       power_trim_info->thermal);
++}
++
++void phydm_get_power_trim_offset_8821c(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_power = 0xff, i;
++
++	odm_efuse_one_byte_read(dm, PPG_2G_TXAB_21C, &pg_power, false);
++
++	if (pg_power != 0xff) {
++		power_trim_info->bb_gain[0][0] = pg_power;
++		odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_21C, &pg_power, false);
++		power_trim_info->bb_gain[1][0] = pg_power;
++		odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_21C, &pg_power, false);
++		power_trim_info->bb_gain[2][0] = pg_power;
++		odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_21C, &pg_power, false);
++		power_trim_info->bb_gain[3][0] = pg_power;
++		odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_21C, &pg_power, false);
++		power_trim_info->bb_gain[4][0] = pg_power;
++		odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_21C, &pg_power, false);
++		power_trim_info->bb_gain[5][0] = pg_power;
++		power_trim_info->flag =
++			power_trim_info->flag | KFREE_FLAG_ON |
++			KFREE_FLAG_ON_2G | KFREE_FLAG_ON_5G;
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8821c power trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_ON) {
++		for (i = 0; i < KFREE_BAND_NUM; i++)
++			RF_DBG(dm, DBG_RF_MP,
++			       "[kfree] 8821c pwr_trim->bb_gain[%d][0]=0x%X\n",
++			       i, power_trim_info->bb_gain[i][0]);
++	}
++}
++
++void phydm_set_kfree_to_rf_8821c(void *dm_void, u8 e_rf_path, boolean wlg_btg,
++				 u8 data)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 wlg, btg;
++	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
++	u32 s_gain_bmask = (BIT(19) | BIT(18) | BIT(17) |
++			    BIT(16) | BIT(15) | BIT(14));
++
++	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);
++	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 1);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 1);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 1);
++
++	if (wlg_btg) {
++		wlg = data & 0xf;
++		btg = (data & 0xf0) >> 4;
++
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (wlg & BIT(0)));
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, (wlg >> 1));
++
++		odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(19), (btg & BIT(0)));
++		odm_set_rf_reg(dm, e_rf_path, RF_0x65, gain_bmask, (btg >> 1));
++	} else {
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), data & BIT(0));
++		odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,
++			       ((data & 0x1f) >> 1));
++	}
++
++	RF_DBG(dm, DBG_RF_MP,
++	       "[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n",
++	       odm_get_rf_reg(dm, e_rf_path, RF_0x55, s_gain_bmask),
++	       odm_get_rf_reg(dm, e_rf_path, RF_0x65, s_gain_bmask));
++}
++
++void phydm_clear_kfree_to_rf_8821c(void *dm_void, u8 e_rf_path, u8 data)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
++	u32 s_gain_bmask = (BIT(19) | BIT(18) | BIT(17) |
++			    BIT(16) | BIT(15) | BIT(14));
++
++	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);
++	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 1);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 1);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 1);
++
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, (data >> 1));
++
++	odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(19), (data & BIT(0)));
++	odm_set_rf_reg(dm, e_rf_path, RF_0x65, gain_bmask, (data >> 1));
++
++	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 0);
++	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 0);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 0);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 0);
++
++	RF_DBG(dm, DBG_RF_MP,
++	       "[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n",
++	       odm_get_rf_reg(dm, e_rf_path, RF_0x55, s_gain_bmask),
++	       odm_get_rf_reg(dm, e_rf_path, RF_0x65, s_gain_bmask));
++}
++
++void phydm_get_thermal_trim_offset_8822b(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_therm = 0xff;
++
++	odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_22B, &pg_therm, false);
++
++	if (pg_therm != 0xff) {
++		pg_therm = pg_therm & 0x1f;
++		if ((pg_therm & BIT(0)) == 0)
++			power_trim_info->thermal = (-1 * (pg_therm >> 1));
++		else
++			power_trim_info->thermal = (pg_therm >> 1);
++
++		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b thermal trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b thermal:%d\n",
++		       power_trim_info->thermal);
++}
++
++void phydm_get_power_trim_offset_8822b(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_power = 0xff, i, j;
++
++	odm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false);
++
++	if (pg_power != 0xff) {
++		/*Path A*/
++		odm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false);
++		power_trim_info->bb_gain[0][0] = (pg_power & 0xf);
++
++		/*Path B*/
++		odm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false);
++		power_trim_info->bb_gain[0][1] = ((pg_power & 0xf0) >> 4);
++
++		power_trim_info->flag |= KFREE_FLAG_ON_2G;
++		power_trim_info->flag |= KFREE_FLAG_ON;
++	}
++
++	odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22B, &pg_power, false);
++
++	if (pg_power != 0xff) {
++		/*Path A*/
++		odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22B, &pg_power, false);
++		power_trim_info->bb_gain[1][0] = pg_power;
++		odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_22B, &pg_power, false);
++		power_trim_info->bb_gain[2][0] = pg_power;
++		odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_22B, &pg_power, false);
++		power_trim_info->bb_gain[3][0] = pg_power;
++		odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_22B, &pg_power, false);
++		power_trim_info->bb_gain[4][0] = pg_power;
++		odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_22B, &pg_power, false);
++		power_trim_info->bb_gain[5][0] = pg_power;
++
++		/*Path B*/
++		odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22B, &pg_power, false);
++		power_trim_info->bb_gain[1][1] = pg_power;
++		odm_efuse_one_byte_read(dm, PPG_5GL2_TXB_22B, &pg_power, false);
++		power_trim_info->bb_gain[2][1] = pg_power;
++		odm_efuse_one_byte_read(dm, PPG_5GM1_TXB_22B, &pg_power, false);
++		power_trim_info->bb_gain[3][1] = pg_power;
++		odm_efuse_one_byte_read(dm, PPG_5GM2_TXB_22B, &pg_power, false);
++		power_trim_info->bb_gain[4][1] = pg_power;
++		odm_efuse_one_byte_read(dm, PPG_5GH1_TXB_22B, &pg_power, false);
++		power_trim_info->bb_gain[5][1] = pg_power;
++
++		power_trim_info->flag |= KFREE_FLAG_ON_5G;
++		power_trim_info->flag |= KFREE_FLAG_ON;
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b power trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (!(power_trim_info->flag & KFREE_FLAG_ON))
++		return;
++
++	for (i = 0; i < KFREE_BAND_NUM; i++) {
++		for (j = 0; j < 2; j++)
++			RF_DBG(dm, DBG_RF_MP,
++			       "[kfree] 8822b PwrTrim->bb_gain[%d][%d]=0x%X\n",
++			       i, j, power_trim_info->bb_gain[i][j]);
++	}
++}
++
++void phydm_set_pa_bias_to_rf_8822b(void *dm_void, u8 e_rf_path, s8 tx_pa_bias)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 rf_reg_51 = 0, rf_reg_52 = 0, rf_reg_3f = 0;
++	u32 tx_pa_bias_bmask = (BIT(12) | BIT(11) | BIT(10) | BIT(9));
++
++	rf_reg_51 = odm_get_rf_reg(dm, e_rf_path, RF_0x51, RFREGOFFSETMASK);
++	rf_reg_52 = odm_get_rf_reg(dm, e_rf_path, RF_0x52, RFREGOFFSETMASK);
++
++	RF_DBG(dm, DBG_RF_MP,
++	       "[kfree] 8822b 2g rf(0x51)=0x%X rf(0x52)=0x%X path=%d\n",
++	       rf_reg_51, rf_reg_52, e_rf_path);
++
++#if 0
++	/*rf3f => rf52[19:17] = rf3f[2:0] rf52[16:15] = rf3f[4:3] rf52[3:0] = rf3f[8:5]*/
++	/*rf3f => rf51[6:3] = rf3f[12:9] rf52[13] = rf3f[13]*/
++#endif
++	rf_reg_3f = ((rf_reg_52 & 0xe0000) >> 17) |
++		    (((rf_reg_52 & 0x18000) >> 15) << 3) |
++		    ((rf_reg_52 & 0xf) << 5) |
++		    (((rf_reg_51 & 0x78) >> 3) << 9) |
++		    (((rf_reg_52 & 0x2000) >> 13) << 13);
++
++	RF_DBG(dm, DBG_RF_MP,
++	       "[kfree] 8822b 2g original pa_bias=%d rf_reg_3f=0x%X path=%d\n",
++	       tx_pa_bias, rf_reg_3f, e_rf_path);
++
++	tx_pa_bias = (s8)((rf_reg_3f & tx_pa_bias_bmask) >> 9) + tx_pa_bias;
++
++	if (tx_pa_bias < 0)
++		tx_pa_bias = 0;
++	else if (tx_pa_bias > 7)
++		tx_pa_bias = 7;
++
++	rf_reg_3f = ((rf_reg_3f & 0xfe1ff) | (tx_pa_bias << 9));
++
++	RF_DBG(dm, DBG_RF_MP,
++	       "[kfree] 8822b 2g 0x%X 0x%X pa_bias=%d rfreg_3f=0x%X path=%d\n",
++	       PPG_PABIAS_2GA_22B, PPG_PABIAS_2GB_22B,
++	       tx_pa_bias, rf_reg_3f, e_rf_path);
++
++	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(10), 0x1);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x0);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, BIT(0), 0x1);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, BIT(1), 0x1);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, (BIT(1) | BIT(0)), 0x3);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
++	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(10), 0x0);
++
++	RF_DBG(dm, DBG_RF_MP,
++	       "[kfree] 8822b 2g tx pa bias rf_0x3f(0x%X) path=%d\n",
++	       odm_get_rf_reg(dm, e_rf_path, RF_0x3f,
++			      (BIT(12) | BIT(11) | BIT(10) | BIT(9))),
++			      e_rf_path);
++}
++
++void phydm_get_pa_bias_offset_8822b(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_pa_bias = 0xff, e_rf_path = 0;
++	s8 tx_pa_bias[2] = {0};
++
++	odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22B, &pg_pa_bias, false);
++
++	if (pg_pa_bias != 0xff) {
++		/*paht a*/
++		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22B,
++					&pg_pa_bias, false);
++		pg_pa_bias = pg_pa_bias & 0xf;
++
++		if ((pg_pa_bias & BIT(0)) == 0)
++			tx_pa_bias[0] = (-1 * (pg_pa_bias >> 1));
++		else
++			tx_pa_bias[0] = (pg_pa_bias >> 1);
++
++		/*paht b*/
++		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GB_22B,
++					&pg_pa_bias, false);
++		pg_pa_bias = pg_pa_bias & 0xf;
++
++		if ((pg_pa_bias & BIT(0)) == 0)
++			tx_pa_bias[1] = (-1 * (pg_pa_bias >> 1));
++		else
++			tx_pa_bias[1] = (pg_pa_bias >> 1);
++
++		RF_DBG(dm, DBG_RF_MP,
++		       "[kfree] 8822b 2g PathA_pa_bias:%d PathB_pa_bias:%d\n",
++		       tx_pa_bias[0], tx_pa_bias[1]);
++
++		for (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++)
++			phydm_set_pa_bias_to_rf_8822b(dm, e_rf_path,
++						      tx_pa_bias[e_rf_path]);
++
++		power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
++	} else {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b 2g tx pa bias no pg\n");
++	}
++}
++
++void phydm_set_kfree_to_rf_8822b(void *dm_void, u8 e_rf_path, u8 data)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
++
++	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);
++	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
++
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,
++		       ((data & 0x1f) >> 1));
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b 0x55[19:14]=0x%X path=%d\n",
++	       odm_get_rf_reg(dm, e_rf_path, RF_0x55,
++			      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
++			      BIT(15) | BIT(14))), e_rf_path);
++}
++
++void phydm_clear_kfree_to_rf_8822b(void *dm_void, u8 e_rf_path, u8 data)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
++
++	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);
++	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
++
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,
++		       ((data & 0x1f) >> 1));
++
++	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 0);
++	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 0);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(7), 0);
++
++	RF_DBG(dm, DBG_RF_MP,
++	       "[kfree] 8822b clear power trim 0x55[19:14]=0x%X path=%d\n",
++	       odm_get_rf_reg(dm, e_rf_path, RF_0x55,
++			      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
++			      BIT(15) | BIT(14))), e_rf_path);
++}
++
++void phydm_get_thermal_trim_offset_8710b(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_therm = 0xff;
++
++	odm_efuse_one_byte_read(dm, 0x0EF, &pg_therm, false);
++
++	if (pg_therm != 0xff) {
++		pg_therm = pg_therm & 0x1f;
++		if ((pg_therm & BIT(0)) == 0)
++			power_trim_info->thermal = (-1 * (pg_therm >> 1));
++		else
++			power_trim_info->thermal = (pg_therm >> 1);
++
++		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b thermal trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b thermal:%d\n",
++		       power_trim_info->thermal);
++}
++
++void phydm_get_power_trim_offset_8710b(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_power = 0xff;
++
++	odm_efuse_one_byte_read(dm, 0xEE, &pg_power, false);
++
++	if (pg_power != 0xff) {
++		/*Path A*/
++		odm_efuse_one_byte_read(dm, 0xEE, &pg_power, false);
++		power_trim_info->bb_gain[0][0] = (pg_power & 0xf);
++
++		power_trim_info->flag |= KFREE_FLAG_ON_2G;
++		power_trim_info->flag |= KFREE_FLAG_ON;
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b power trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_ON)
++		RF_DBG(dm, DBG_RF_MP,
++		       "[kfree] 8710b power_trim_data->bb_gain[0][0]=0x%X\n",
++		       power_trim_info->bb_gain[0][0]);
++}
++
++void phydm_set_kfree_to_rf_8710b(void *dm_void, u8 e_rf_path, u8 data)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15));
++
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, ((data & 0xf) >> 1));
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b 0x55[19:14]=0x%X path=%d\n",
++	       odm_get_rf_reg(dm, e_rf_path, RF_0x55,
++			      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
++			      BIT(15) | BIT(14))), e_rf_path);
++}
++
++void phydm_clear_kfree_to_rf_8710b(void *dm_void, u8 e_rf_path, u8 data)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
++
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,
++		       ((data & 0x1f) >> 1));
++
++	RF_DBG(dm, DBG_RF_MP,
++	       "[kfree] 8710b clear power trim 0x55[19:14]=0x%X path=%d\n",
++	       odm_get_rf_reg(dm, e_rf_path, RF_0x55,
++			      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
++			      BIT(15) | BIT(14))), e_rf_path);
++}
++
++void phydm_get_thermal_trim_offset_8192f(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_therm = 0xff;
++
++	odm_efuse_one_byte_read(dm, 0x1EF, &pg_therm, false);
++
++	if (pg_therm != 0xff) {
++		pg_therm = pg_therm & 0x1f;
++		if ((pg_therm & BIT(0)) == 0)
++			power_trim_info->thermal = (-1 * (pg_therm >> 1));
++		else
++			power_trim_info->thermal = (pg_therm >> 1);
++
++		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8192f thermal trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8192f thermal:%d\n",
++		       power_trim_info->thermal);
++}
++
++void phydm_get_power_trim_offset_8192f(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_power1 = 0xff, pg_power2 = 0xff, pg_power3 = 0xff, i, j;
++
++	odm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false); /*CH4-9*/
++
++	if (pg_power1 != 0xff) {
++		/*Path A*/
++		odm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false);
++		power_trim_info->bb_gain[1][0] = (pg_power1 & 0xf);
++		/*Path B*/
++		odm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false);
++		power_trim_info->bb_gain[1][1] = ((pg_power1 & 0xf0) >> 4);
++
++		power_trim_info->flag |= KFREE_FLAG_ON_2G;
++		power_trim_info->flag |= KFREE_FLAG_ON;
++	}
++
++	odm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false); /*CH1-3*/
++
++	if (pg_power2 != 0xff) {
++		/*Path A*/
++		odm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false);
++		power_trim_info->bb_gain[0][0] = (pg_power2 & 0xf);
++		/*Path B*/
++		odm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false);
++		power_trim_info->bb_gain[0][1] = ((pg_power2 & 0xf0) >> 4);
++
++		power_trim_info->flag |= KFREE_FLAG_ON_2G;
++		power_trim_info->flag |= KFREE_FLAG_ON;
++	} else {
++		power_trim_info->bb_gain[0][0] = (pg_power1 & 0xf);
++		power_trim_info->bb_gain[0][1] = ((pg_power1 & 0xf0) >> 4);
++	}
++
++	odm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false); /*CH10-14*/
++
++	if (pg_power3 != 0xff) {
++		/*Path A*/
++		odm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false);
++		power_trim_info->bb_gain[2][0] = (pg_power3 & 0xf);
++		/*Path B*/
++		odm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false);
++		power_trim_info->bb_gain[2][1] = ((pg_power3 & 0xf0) >> 4);
++
++		power_trim_info->flag |= KFREE_FLAG_ON_2G;
++		power_trim_info->flag |= KFREE_FLAG_ON;
++	} else {
++		power_trim_info->bb_gain[2][0] = (pg_power1 & 0xf);
++		power_trim_info->bb_gain[2][1] = ((pg_power1 & 0xf0) >> 4);
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8192F power trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (!(power_trim_info->flag & KFREE_FLAG_ON))
++		return;
++
++	for (i = 0; i < KFREE_CH_NUM; i++) {
++		for (j = 0; j < 2; j++)
++			RF_DBG(dm, DBG_RF_MP,
++			       "[kfree] 8192F PwrTrim->bb_gain[%d][%d]=0x%X\n",
++			       i, j, power_trim_info->bb_gain[i][j]);
++	}
++}
++
++void phydm_set_kfree_to_rf_8192f(void *dm_void, u8 e_rf_path, u8 channel_idx,
++				 u8 data)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	/*power_trim based on 55[19:14]*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
++	/*enable 55[14] for 0.5db step*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 1);
++	/*enter power_trim debug mode*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 1);
++	/*write enable*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 1);
++
++	if (e_rf_path == 0) {
++		if (channel_idx == 0) {
++			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);
++			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
++
++			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);
++			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
++
++		} else if (channel_idx == 1) {
++			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);
++			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
++
++			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);
++			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
++		} else if (channel_idx == 2) {
++			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);
++			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
++
++			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);
++			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
++		}
++	} else if (e_rf_path == 1) {
++		if (channel_idx == 0) {
++			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);
++			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
++
++			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);
++			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
++		} else if (channel_idx == 1) {
++			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);
++			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
++
++			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);
++			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
++		} else if (channel_idx == 2) {
++			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);
++			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
++
++			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);
++			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
++		}
++	}
++
++	/*leave power_trim debug mode*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);
++	/*write disable*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 0);
++
++	RF_DBG(dm, DBG_RF_MP,
++	       "[kfree] 8192F 0x55[19:14]=0x%X path=%d channel=%d\n",
++	       odm_get_rf_reg(dm, e_rf_path, RF_0x55,
++			      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
++			      BIT(15) | BIT(14))), e_rf_path, channel_idx);
++}
++
++#if 0
++/*
++void phydm_clear_kfree_to_rf_8192f(void *dm_void, u8 e_rf_path, u8 data)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	struct dm_rf_calibration_struct	*cali_info = &dm->rf_calibrate_info;
++
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1));
++
++	RF_DBG(dm, DBG_RF_MP,
++		"[kfree] 8192F clear power trim 0x55[19:14]=0x%X path=%d\n",
++		odm_get_rf_reg(dm, e_rf_path, RF_0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),
++		e_rf_path
++		);
++}
++*/
++#endif
++
++void phydm_get_thermal_trim_offset_8198f(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_therm = 0;
++
++	odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_98F, &pg_therm, false);
++
++	if (pg_therm != 0) {
++		pg_therm = pg_therm & 0x1f;
++		if ((pg_therm & BIT(0)) == 0)
++			power_trim_info->thermal = (-1 * (pg_therm >> 1));
++		else
++			power_trim_info->thermal = (pg_therm >> 1);
++
++		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f thermal trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f thermal:%d\n",
++		       power_trim_info->thermal);
++}
++
++void phydm_get_power_trim_offset_8198f(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_power = 0, i, j;
++
++	odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_98F, &pg_power, false);
++
++	if (pg_power != 0) {
++		power_trim_info->bb_gain[0][0] = pg_power & 0xf;
++		power_trim_info->bb_gain[0][1] = (pg_power & 0xf0) >> 4;
++
++		odm_efuse_one_byte_read(dm, PPG_2GL_TXCD_98F, &pg_power, false);
++		power_trim_info->bb_gain[0][2] = pg_power & 0xf;
++		power_trim_info->bb_gain[0][3] = (pg_power & 0xf0) >> 4;
++
++		odm_efuse_one_byte_read(dm, PPG_2GM_TXAB_98F, &pg_power, false);
++		power_trim_info->bb_gain[1][0] = pg_power & 0xf;
++		power_trim_info->bb_gain[1][1] = (pg_power & 0xf0) >> 4;
++
++		odm_efuse_one_byte_read(dm, PPG_2GM_TXCD_98F, &pg_power, false);
++		power_trim_info->bb_gain[1][2] = pg_power & 0xf;
++		power_trim_info->bb_gain[1][3] = (pg_power & 0xf0) >> 4;
++
++		odm_efuse_one_byte_read(dm, PPG_2GH_TXAB_98F, &pg_power, false);
++		power_trim_info->bb_gain[2][0] = pg_power & 0xf;
++		power_trim_info->bb_gain[2][1] = (pg_power & 0xf0) >> 4;
++
++		odm_efuse_one_byte_read(dm, PPG_2GH_TXCD_98F, &pg_power, false);
++		power_trim_info->bb_gain[2][2] = pg_power & 0xf;
++		power_trim_info->bb_gain[2][3] = (pg_power & 0xf0) >> 4;
++
++		power_trim_info->flag =
++			power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G;
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f power trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_ON) {
++		for (i = 0; i < KFREE_BAND_NUM; i++) {
++			for (j = 0; j < MAX_RF_PATH; j++) {
++				RF_DBG(dm, DBG_RF_MP,
++				       "[kfree] 8198f pwr_trim->bb_gain[%d][%d]=0x%X\n",
++				       i, j, power_trim_info->bb_gain[i][j]);
++			}
++		}
++	}
++}
++
++void phydm_get_pa_bias_offset_8198f(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_pa_bias = 0, i;
++	u8 tx_pa_bias[4] = {0};
++
++	odm_efuse_one_byte_read(dm, PPG_PABIAS_2GAB_98F, &pg_pa_bias, false);
++
++	if (pg_pa_bias != 0) {
++		/*paht ab*/
++		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GAB_98F,
++					&pg_pa_bias, false);
++		tx_pa_bias[0] = pg_pa_bias & 0xf;
++		tx_pa_bias[1] = ((pg_pa_bias & 0xf0) >> 4);
++
++		/*paht cd*/
++		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GCD_98F,
++					&pg_pa_bias, false);
++		tx_pa_bias[2] = pg_pa_bias & 0xf;
++		tx_pa_bias[3] = ((pg_pa_bias & 0xf0) >> 4);
++
++		for (i = RF_PATH_A; i < 4; i++) {
++			if ((tx_pa_bias[i] & 0x1) == 1)
++				tx_pa_bias[i] = tx_pa_bias[i] & 0xe;
++			else
++				tx_pa_bias[i] = tx_pa_bias[i] | 0x1;
++		}
++
++		RF_DBG(dm, DBG_RF_MP,
++		       "[kfree] 8198f PathA_pa_bias:0x%x PathB_pa_bias:0x%x\n",
++		       tx_pa_bias[0], tx_pa_bias[1]);
++
++		RF_DBG(dm, DBG_RF_MP,
++		       "[kfree] 8198f PathC_pa_bias:0x%x PathD_pa_bias:0x%x\n",
++		       tx_pa_bias[2], tx_pa_bias[3]);
++
++		for (i = RF_PATH_A; i < 4; i++)
++			odm_set_rf_reg(dm, i, 0x60, 0x0000f000, tx_pa_bias[i]);
++
++		power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
++	} else {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f tx pa bias no pg\n");
++	}
++}
++
++void phydm_get_set_lna_offset_8198f(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_pa_bias = 0, i;
++	u8 cg[4] = {0}, cs[4] = {0};
++	u32 rf_reg;
++
++	odm_efuse_one_byte_read(dm, PPG_LNA_2GA_98F, &pg_pa_bias, false);
++
++	if (pg_pa_bias != 0) {
++		odm_efuse_one_byte_read(dm, PPG_LNA_2GA_98F,
++					&pg_pa_bias, false);
++		cg[0] = (pg_pa_bias & 0xc) >> 2;
++		cs[0] = pg_pa_bias & 0x3;
++
++		odm_efuse_one_byte_read(dm, PPG_LNA_2GB_98F,
++					&pg_pa_bias, false);
++		cg[1] = (pg_pa_bias & 0xc) >> 2;
++		cs[1] = pg_pa_bias & 0x3;
++
++		odm_efuse_one_byte_read(dm, PPG_LNA_2GC_98F,
++					&pg_pa_bias, false);
++		cg[2] = (pg_pa_bias & 0xc) >> 2;
++		cs[2] = pg_pa_bias & 0x3;
++
++		odm_efuse_one_byte_read(dm, PPG_LNA_2GD_98F,
++					&pg_pa_bias, false);
++		cg[3] = (pg_pa_bias & 0xc) >> 2;
++		cs[3] = pg_pa_bias & 0x3;
++
++		for (i = RF_PATH_A; i < 4; i++) {
++			RF_DBG(dm, DBG_RF_MP,
++				"[kfree] 8198f lna cg[%d]=0x%x cs[%d]=0x%x\n",
++				i, cg[i], i, cs[i]);
++			odm_set_rf_reg(dm, i, 0xdf, RFREGOFFSETMASK, 0x2);
++
++			if (cg[i] == 0x3) {
++				rf_reg = odm_get_rf_reg(dm, i, 0x86, (BIT(19) | BIT(18)));
++				rf_reg = rf_reg + 1;
++				if (rf_reg >= 0x3)
++					rf_reg = 0x3;
++				odm_set_rf_reg(dm, i, 0x86, (BIT(19) | BIT(18)), rf_reg);
++				RF_DBG(dm, DBG_RF_MP,
++					"[kfree] 8198f lna CG set rf 0x86 [19:18]=0x%x path=%d\n", rf_reg, i);
++			}
++			if (cs[i] == 0x3) {
++				rf_reg = odm_get_rf_reg(dm, i, 0x86, (BIT(17) | BIT(16)));
++				rf_reg = rf_reg + 1;
++				if (rf_reg >= 0x3)
++					rf_reg = 0x3;
++				odm_set_rf_reg(dm, i, 0x86, (BIT(17) | BIT(16)), rf_reg);
++				RF_DBG(dm, DBG_RF_MP,
++					"[kfree] 8198f lna CS set rf 0x86 [17:16]=0x%x path=%d\n", rf_reg, i);
++			}	
++		}
++
++		power_trim_info->lna_flag |= LNA_FLAG_ON;
++	} else {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f lna no pg\n");
++	}
++}
++
++
++void phydm_set_kfree_to_rf_8198f(void *dm_void, u8 e_rf_path, u8 data)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++	u32 i;
++	s8 pwr_offset[3];
++
++	RF_DBG(dm, DBG_RF_MP,
++		   "[kfree] %s:Set kfree to rf 0x33\n", __func__);
++
++	/*power_trim based on 55[19:14]*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
++	/*enable 55[14] for 0.5db step*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 1);
++	/*enter power_trim debug mode*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);
++	/*write enable*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 1);
++
++	for (i =0; i < 3; i++)
++		pwr_offset[i] = power_trim_info->bb_gain[i][e_rf_path];
++
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[0]);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[0]);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[1]);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[1]);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[2]);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[2]);
++
++	/*leave power_trim debug mode*/
++	/*odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);*/
++	/*write disable*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 0);
++
++}
++
++void phydm_clear_kfree_to_rf_8198f(void *dm_void, u8 e_rf_path, u8 data)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	RF_DBG(dm, DBG_RF_MP,
++		   "[kfree] %s:Clear kfree to rf 0x55\n", __func__);
++#if 0
++	/*power_trim based on 55[19:14]*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
++	/*enable 55[14] for 0.5db step*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 1);
++	/*enter power_trim debug mode*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);
++	/*write enable*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 1);
++
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);
++	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
++
++	/*leave power_trim debug mode*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);
++	/*enable 55[14] for 0.5db step*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 0);
++	/*write disable*/
++	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 0);
++#else
++
++	odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 1);
++	/*odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 0);*/
++
++#endif
++
++}
++
++void phydm_get_set_thermal_trim_offset_8822c(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_therm = 0xff, thermal[2] = {0};
++
++	odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_22C, &pg_therm, false);
++
++	if (pg_therm != 0xff) {
++		/*s0*/
++		pg_therm = pg_therm & 0x1f;
++
++		thermal[RF_PATH_A] =
++			((pg_therm & 0x1) << 3) | ((pg_therm >> 1) & 0x7);
++
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x43, 0x000f0000, thermal[RF_PATH_A]);
++
++		/*s1*/
++		odm_efuse_one_byte_read(dm, PPG_THERMAL_B_OFFSET_22C, &pg_therm, false);
++
++		pg_therm = pg_therm & 0x1f;
++
++		thermal[RF_PATH_B] = ((pg_therm & 0x1) << 3) | ((pg_therm >> 1) & 0x7);
++
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x43, 0x000f0000, thermal[RF_PATH_B]);
++
++		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
++
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8822c thermal trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8822c thermalA:%d thermalB:%d\n",
++			thermal[RF_PATH_A],
++			thermal[RF_PATH_B]);	
++}
++
++void phydm_set_power_trim_offset_8822c(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++	u8 e_rf_path;
++
++	for (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++)
++	{
++		odm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 1);
++
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x0);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[0][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x1);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[1][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x2);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[2][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x3);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[2][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x4);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[3][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x5);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[4][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x6);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[5][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x7);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[6][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x8);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[7][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x9);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[3][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xa);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[4][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xb);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[5][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xc);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[6][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xd);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[7][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xe);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[7][e_rf_path]);
++
++		odm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 0);
++	}
++}
++
++void phydm_get_set_power_trim_offset_8822c(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_power = 0xff, i, j;
++	u8 pg_power1, pg_power2 , pg_power3, pg_power4, pg_power5;
++
++	odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_22C, &pg_power1, false);
++	odm_efuse_one_byte_read(dm, PPG_2GM_TXAB_22C, &pg_power2, false);
++	odm_efuse_one_byte_read(dm, PPG_2GH_TXAB_22C, &pg_power3, false);
++	odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22C, &pg_power4, false);
++	odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22C, &pg_power5, false);
++
++	if (pg_power1 != 0xff || pg_power2 != 0xff || pg_power3 != 0xff ||
++		pg_power4 != 0xff || pg_power5 != 0xff) {
++		odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[0][0] = pg_power & 0xf;
++		power_trim_info->bb_gain[0][1] = (pg_power & 0xf0) >> 4;
++
++		odm_efuse_one_byte_read(dm, PPG_2GM_TXAB_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[1][0] = pg_power & 0xf;
++		power_trim_info->bb_gain[1][1] = (pg_power & 0xf0) >> 4;
++
++		odm_efuse_one_byte_read(dm, PPG_2GH_TXAB_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[2][0] = pg_power & 0xf;
++		power_trim_info->bb_gain[2][1] = (pg_power & 0xf0) >> 4;
++
++		odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[3][0] = pg_power & 0x1f;
++		odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[3][1] = pg_power & 0x1f;
++
++		odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[4][0] = pg_power & 0x1f;
++		odm_efuse_one_byte_read(dm, PPG_5GL2_TXB_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[4][1] = pg_power & 0x1f;
++
++		odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[5][0] = pg_power & 0x1f;
++		odm_efuse_one_byte_read(dm, PPG_5GM1_TXB_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[5][1] = pg_power & 0x1f;
++
++		odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[6][0] = pg_power & 0x1f;
++		odm_efuse_one_byte_read(dm, PPG_5GM2_TXB_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[6][1] = pg_power & 0x1f;
++
++		odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[7][0] = pg_power & 0x1f;
++		odm_efuse_one_byte_read(dm, PPG_5GH1_TXB_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[7][1] = pg_power & 0x1f;
++
++		power_trim_info->flag =
++			power_trim_info->flag | KFREE_FLAG_ON |
++						KFREE_FLAG_ON_2G |
++						KFREE_FLAG_ON_5G;
++
++		phydm_set_power_trim_offset_8822c(dm);
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8822c power trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_ON) {
++		for (i = 0; i < KFREE_BAND_NUM; i++) {
++			for (j = 0; j < 2; j++) {
++				RF_DBG(dm, DBG_RF_MP,
++				       "[kfree] 8822c pwr_trim->bb_gain[%d][%d]=0x%X\n",
++				       i, j, power_trim_info->bb_gain[i][j]);
++			}
++		}
++	}
++}
++
++void phydm_get_tssi_trim_offset_8822c(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 i, j = 0;
++	u8 pg_power[16] = {0};
++
++	odm_efuse_one_byte_read(dm, TSSI_2GM_TXA_22C, &pg_power[0], false);
++	odm_efuse_one_byte_read(dm, TSSI_2GM_TXB_22C, &pg_power[1], false);
++	odm_efuse_one_byte_read(dm, TSSI_2GH_TXA_22C, &pg_power[2], false);
++	odm_efuse_one_byte_read(dm, TSSI_2GH_TXB_22C, &pg_power[3], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GL1_TXA_22C, &pg_power[4], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GL1_TXB_22C, &pg_power[5], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GL2_TXA_22C, &pg_power[6], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GL2_TXB_22C, &pg_power[7], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GM1_TXA_22C, &pg_power[8], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GM1_TXB_22C, &pg_power[9], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GM2_TXA_22C, &pg_power[10], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GM2_TXB_22C, &pg_power[11], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GH1_TXA_22C, &pg_power[12], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GH1_TXB_22C, &pg_power[13], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GH2_TXA_22C, &pg_power[14], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GH2_TXB_22C, &pg_power[15], false);
++
++	for (i = 0; i < 16; i++) {
++		if (pg_power[i] == 0xff)
++			j++;
++	}
++
++	if (j == 15) {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8822c tssi trim no PG\n");
++		return;
++	} else {
++		power_trim_info->tssi_trim[0][0] = (s8)pg_power[0];
++		power_trim_info->tssi_trim[0][1] = (s8)pg_power[1];
++		power_trim_info->tssi_trim[1][0] = (s8)pg_power[0];
++		power_trim_info->tssi_trim[1][1] = (s8)pg_power[1];
++		power_trim_info->tssi_trim[2][0] = (s8)pg_power[2];
++		power_trim_info->tssi_trim[2][1] = (s8)pg_power[3];
++		power_trim_info->tssi_trim[3][0] = (s8)pg_power[4];
++		power_trim_info->tssi_trim[3][1] = (s8)pg_power[5];
++		power_trim_info->tssi_trim[4][0] = (s8)pg_power[6];
++		power_trim_info->tssi_trim[4][1] = (s8)pg_power[7];
++		power_trim_info->tssi_trim[5][0] = (s8)pg_power[8];
++		power_trim_info->tssi_trim[5][1] = (s8)pg_power[9];
++		power_trim_info->tssi_trim[6][0] = (s8)pg_power[10];
++		power_trim_info->tssi_trim[6][1] = (s8)pg_power[11];
++		power_trim_info->tssi_trim[7][0] = (s8)pg_power[12];
++		power_trim_info->tssi_trim[7][1] = (s8)pg_power[13];
++		power_trim_info->tssi_trim[8][0] = (s8)pg_power[14];
++		power_trim_info->tssi_trim[8][1] = (s8)pg_power[15];
++
++		power_trim_info->flag =
++			power_trim_info->flag | TSSI_TRIM_FLAG_ON;
++
++		if (power_trim_info->flag & TSSI_TRIM_FLAG_ON) {
++			for (i = 0; i < KFREE_BAND_NUM; i++) {
++				for (j = 0; j < 2; j++) {
++					RF_DBG(dm, DBG_RF_MP,
++					       "[kfree] 8822c tssi_trim[%d][%d]=0x%X\n",
++					       i, j, power_trim_info->tssi_trim[i][j]);
++				}
++			}
++		}
++	}
++}
++
++s8 phydm_get_tssi_trim_de_8822c(void *dm_void, u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 channel = *dm->channel, group = 0;
++
++	if (channel >= 1 && channel <= 3)
++		group = 0;
++	else if (channel >= 4 && channel <= 9)
++		group = 1;
++	else if (channel >= 10 && channel <= 14)
++		group = 2;
++	else if (channel >= 36 && channel <= 50)
++		group = 3;
++	else if (channel >= 52 && channel <= 64)
++		group = 4;
++	else if (channel >= 100 && channel <= 118)
++		group = 5;
++	else if (channel >= 120 && channel <= 144)
++		group = 6;
++	else if (channel >= 149 && channel <= 165)
++		group = 7;
++	else if (channel >= 167 && channel <= 177)
++		group = 8;
++	else {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] Channel(%d) is not exist in Group\n",
++			channel);
++		return 0;
++	}
++
++	return power_trim_info->tssi_trim[group][path];
++}
++
++
++
++void phydm_get_set_pa_bias_offset_8822c(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_pa_bias = 0xff;
++
++	RF_DBG(dm, DBG_RF_MP, "======>%s\n", __func__);
++
++	odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22C, &pg_pa_bias, false);
++
++	if (pg_pa_bias != 0xff) {
++		/*2G s0*/
++		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22C,
++					&pg_pa_bias, false);
++		pg_pa_bias = pg_pa_bias & 0xf;
++
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 2G s0 pa_bias=0x%x\n", pg_pa_bias);
++
++		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x0000f000, pg_pa_bias);
++
++		/*2G s1*/
++		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GB_22C,
++					&pg_pa_bias, false);
++		pg_pa_bias = pg_pa_bias & 0xf;
++
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 2G s1 pa_bias=0x%x\n", pg_pa_bias);
++
++		odm_set_rf_reg(dm, RF_PATH_B, 0x60, 0x0000f000, pg_pa_bias);
++
++		/*5G s0*/
++		odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_22C,
++					&pg_pa_bias, false);
++		pg_pa_bias = pg_pa_bias & 0xf;
++
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 5G s0 pa_bias=0x%x\n", pg_pa_bias);
++
++		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x000f0000, pg_pa_bias);
++
++		/*5G s1*/
++		odm_efuse_one_byte_read(dm, PPG_PABIAS_5GB_22C,
++					&pg_pa_bias, false);
++		pg_pa_bias = pg_pa_bias & 0xf;
++
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 5G s1 pa_bias=0x%x\n", pg_pa_bias);
++
++		odm_set_rf_reg(dm, RF_PATH_B, 0x60, 0x000f0000, pg_pa_bias);
++
++		power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
++	} else {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8822c tx pa bias no pg\n");
++	}
++
++}
++
++void phydm_get_set_thermal_trim_offset_8812f(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_therm = 0xff, thermal[2] = {0};
++
++	odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_22C, &pg_therm, false);
++
++	if (pg_therm != 0xff) {
++		/*s0*/
++		pg_therm = pg_therm & 0x1f;
++
++		thermal[RF_PATH_A] =
++			((pg_therm & 0x1) << 3) | ((pg_therm >> 1) & 0x7);
++
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x43, 0x000f0000, thermal[RF_PATH_A]);
++
++		/*s1*/
++		odm_efuse_one_byte_read(dm, PPG_THERMAL_B_OFFSET_22C, &pg_therm, false);
++
++		pg_therm = pg_therm & 0x1f;
++
++		thermal[RF_PATH_B] = ((pg_therm & 0x1) << 3) | ((pg_therm >> 1) & 0x7);
++
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x43, 0x000f0000, thermal[RF_PATH_B]);
++
++		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
++
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8812f thermal trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8812f thermalA:%d thermalB:%d\n",
++			thermal[RF_PATH_A],
++			thermal[RF_PATH_B]);	
++}
++
++void phydm_set_power_trim_offset_8812f(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++	u8 e_rf_path;
++
++	for (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++)
++	{
++		odm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 1);
++
++#if 0
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x0);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[0][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x1);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[1][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x2);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[2][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x3);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[2][e_rf_path]);
++#endif
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x4);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[3][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x5);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[4][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x6);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[5][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x7);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[6][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x8);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[7][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x9);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[3][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xa);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[4][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xb);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[5][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xc);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[6][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xd);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[7][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xe);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
++			power_trim_info->bb_gain[7][e_rf_path]);
++
++		odm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 0);
++	}
++}
++
++void phydm_get_set_power_trim_offset_8812f(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_power = 0xff, i, j;
++	u8 pg_power1 = 0, pg_power2 = 0, pg_power3 = 0;
++	u8 pg_power4 = 0, pg_power5 = 0;
++
++	odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22C, &pg_power1, false);
++	odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22C, &pg_power2, false);
++	odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_22C, &pg_power3, false);
++	odm_efuse_one_byte_read(dm, PPG_5GL2_TXB_22C, &pg_power4, false);
++	odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_22C, &pg_power5, false);
++
++	if (pg_power1 != 0xff || pg_power2 != 0xff || pg_power3 != 0xff ||
++		pg_power4 != 0xff || pg_power5 != 0xff) {
++#if 0
++		odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[0][0] = pg_power & 0xf;
++		power_trim_info->bb_gain[0][1] = (pg_power & 0xf0) >> 4;
++
++		odm_efuse_one_byte_read(dm, PPG_2GM_TXAB_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[1][0] = pg_power & 0xf;
++		power_trim_info->bb_gain[1][1] = (pg_power & 0xf0) >> 4;
++
++		odm_efuse_one_byte_read(dm, PPG_2GH_TXAB_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[2][0] = pg_power & 0xf;
++		power_trim_info->bb_gain[2][1] = (pg_power & 0xf0) >> 4;
++#endif
++		odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[3][0] = pg_power & 0x1f;
++		odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[3][1] = pg_power & 0x1f;
++
++		odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[4][0] = pg_power & 0x1f;
++		odm_efuse_one_byte_read(dm, PPG_5GL2_TXB_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[4][1] = pg_power & 0x1f;
++
++		odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[5][0] = pg_power & 0x1f;
++		odm_efuse_one_byte_read(dm, PPG_5GM1_TXB_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[5][1] = pg_power & 0x1f;
++
++		odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[6][0] = pg_power & 0x1f;
++		odm_efuse_one_byte_read(dm, PPG_5GM2_TXB_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[6][1] = pg_power & 0x1f;
++
++		odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[7][0] = pg_power & 0x1f;
++		odm_efuse_one_byte_read(dm, PPG_5GH1_TXB_22C, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[7][1] = pg_power & 0x1f;
++
++		power_trim_info->flag =
++			power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_5G;
++
++		phydm_set_power_trim_offset_8812f(dm);
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8812f power trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_ON) {
++		for (i = 0; i < KFREE_BAND_NUM; i++) {
++			for (j = 0; j < 2; j++) {
++				RF_DBG(dm, DBG_RF_MP,
++				       "[kfree] 8812f pwr_trim->bb_gain[%d][%d]=0x%X\n",
++				       i, j, power_trim_info->bb_gain[i][j]);
++			}
++		}
++	}
++}
++
++void phydm_get_tssi_trim_offset_8812f(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 i, j = 0;
++	u8 pg_power[16] = {0};
++
++#if 0
++	odm_efuse_one_byte_read(dm, TSSI_2GM_TXA_22C, &pg_power[0], false);
++	odm_efuse_one_byte_read(dm, TSSI_2GM_TXB_22C, &pg_power[1], false);
++	odm_efuse_one_byte_read(dm, TSSI_2GH_TXA_22C, &pg_power[2], false);
++	odm_efuse_one_byte_read(dm, TSSI_2GH_TXB_22C, &pg_power[3], false);
++#endif
++	odm_efuse_one_byte_read(dm, TSSI_5GL1_TXA_22C, &pg_power[4], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GL1_TXB_22C, &pg_power[5], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GL2_TXA_22C, &pg_power[6], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GL2_TXB_22C, &pg_power[7], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GM1_TXA_22C, &pg_power[8], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GM1_TXB_22C, &pg_power[9], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GM2_TXA_22C, &pg_power[10], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GM2_TXB_22C, &pg_power[11], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GH1_TXA_22C, &pg_power[12], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GH1_TXB_22C, &pg_power[13], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GH2_TXA_22C, &pg_power[14], false);
++	odm_efuse_one_byte_read(dm, TSSI_5GH2_TXB_22C, &pg_power[15], false);
++
++	for (i = 4; i < 16; i++) {
++		if (pg_power[i] == 0xff)
++			j++;
++	}
++
++	if (j == 12) {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8812f tssi trim no PG\n");
++		return;
++	} else {
++#if 0
++		power_trim_info->tssi_trim[0][0] = (s8)pg_power[0];
++		power_trim_info->tssi_trim[0][1] = (s8)pg_power[1];
++		power_trim_info->tssi_trim[1][0] = (s8)pg_power[0];
++		power_trim_info->tssi_trim[1][1] = (s8)pg_power[1];
++		power_trim_info->tssi_trim[2][0] = (s8)pg_power[2];
++		power_trim_info->tssi_trim[2][1] = (s8)pg_power[3];
++#endif
++		power_trim_info->tssi_trim[3][0] = (s8)pg_power[4];
++		power_trim_info->tssi_trim[3][1] = (s8)pg_power[5];
++		power_trim_info->tssi_trim[4][0] = (s8)pg_power[6];
++		power_trim_info->tssi_trim[4][1] = (s8)pg_power[7];
++		power_trim_info->tssi_trim[5][0] = (s8)pg_power[8];
++		power_trim_info->tssi_trim[5][1] = (s8)pg_power[9];
++		power_trim_info->tssi_trim[6][0] = (s8)pg_power[10];
++		power_trim_info->tssi_trim[6][1] = (s8)pg_power[11];
++		power_trim_info->tssi_trim[7][0] = (s8)pg_power[12];
++		power_trim_info->tssi_trim[7][1] = (s8)pg_power[13];
++		power_trim_info->tssi_trim[8][0] = (s8)pg_power[14];
++		power_trim_info->tssi_trim[8][1] = (s8)pg_power[15];
++
++		power_trim_info->flag =
++			power_trim_info->flag | TSSI_TRIM_FLAG_ON;
++
++		if (power_trim_info->flag & TSSI_TRIM_FLAG_ON) {
++			for (i = 0; i < KFREE_BAND_NUM; i++) {
++				for (j = 0; j < 2; j++) {
++					RF_DBG(dm, DBG_RF_MP,
++					       "[kfree] 8812f tssi_trim[%d][%d]=0x%X\n",
++					       i, j, power_trim_info->tssi_trim[i][j]);
++				}
++			}
++		}
++	}
++}
++
++s8 phydm_get_tssi_trim_de_8812f(void *dm_void, u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 channel = *dm->channel, group = 0;
++
++	if (channel >= 1 && channel <= 3)
++		group = 0;
++	else if (channel >= 4 && channel <= 9)
++		group = 1;
++	else if (channel >= 10 && channel <= 14)
++		group = 2;
++	else if (channel >= 36 && channel <= 50)
++		group = 3;
++	else if (channel >= 52 && channel <= 64)
++		group = 4;
++	else if (channel >= 100 && channel <= 118)
++		group = 5;
++	else if (channel >= 120 && channel <= 144)
++		group = 6;
++	else if (channel >= 149 && channel <= 165)
++		group = 7;
++	else if (channel >= 167 && channel <= 177)
++		group = 8;
++	else {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] Channel(%d) is not exist in Group\n",
++			channel);
++		return 0;
++	}
++
++	return power_trim_info->tssi_trim[group][path];
++}
++
++void phydm_get_set_pa_bias_offset_8812f(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_pa_bias = 0xff;
++
++	RF_DBG(dm, DBG_RF_MP, "======>%s\n", __func__);
++
++	odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_22C, &pg_pa_bias, false);
++
++	if (pg_pa_bias != 0xff) {
++#if 0
++		/*2G s0*/
++		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22C,
++					&pg_pa_bias, false);
++		pg_pa_bias = pg_pa_bias & 0xf;
++
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 2G s0 pa_bias=0x%x\n", pg_pa_bias);
++
++		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x0000f000, pg_pa_bias);
++
++		/*2G s1*/
++		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GB_22C,
++					&pg_pa_bias, false);
++		pg_pa_bias = pg_pa_bias & 0xf;
++
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 2G s1 pa_bias=0x%x\n", pg_pa_bias);
++
++		odm_set_rf_reg(dm, RF_PATH_B, 0x60, 0x0000f000, pg_pa_bias);
++#endif
++
++		/*5G s0*/
++		odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_22C,
++					&pg_pa_bias, false);
++		pg_pa_bias = pg_pa_bias & 0xf;
++
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 5G s0 pa_bias=0x%x\n", pg_pa_bias);
++
++		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x000f0000, pg_pa_bias);
++
++		/*5G s1*/
++		odm_efuse_one_byte_read(dm, PPG_PABIAS_5GB_22C,
++					&pg_pa_bias, false);
++		pg_pa_bias = pg_pa_bias & 0xf;
++
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 5G s1 pa_bias=0x%x\n", pg_pa_bias);
++
++		odm_set_rf_reg(dm, RF_PATH_B, 0x60, 0x000f0000, pg_pa_bias);
++
++		power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
++	} else {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8812f tx pa bias no pg\n");
++	}
++
++}
++
++void phydm_get_thermal_trim_offset_8195b(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_therm = 0xff;
++
++	odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_95B, &pg_therm, false);
++
++	if (pg_therm != 0xff) {
++		pg_therm = pg_therm & 0x1f;
++		if ((pg_therm & BIT(0)) == 0)
++			power_trim_info->thermal = (-1 * (pg_therm >> 1));
++		else
++			power_trim_info->thermal = (pg_therm >> 1);
++
++		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8195b thermal trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8195b thermal:%d\n",
++		       power_trim_info->thermal);
++}
++
++void phydm_set_power_trim_rf_8195b(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	RF_DBG(dm, DBG_RF_MP,
++		   "[kfree] %s:Set kfree to rf 0x33\n", __func__);
++
++	if (power_trim_info->flag & KFREE_FLAG_ON) { 
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, BIT(19), 1);
++
++		if (power_trim_info->flag & KFREE_FLAG_ON_2G) {
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x0);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++				power_trim_info->bb_gain[0][RF_PATH_A]);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x1);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++				power_trim_info->bb_gain[1][RF_PATH_A]);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x2);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++				power_trim_info->bb_gain[2][RF_PATH_A]);
++		}
++
++		if (power_trim_info->flag & KFREE_FLAG_ON_5G) {
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x4);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++				power_trim_info->bb_gain[3][RF_PATH_A]);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x5);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++				power_trim_info->bb_gain[4][RF_PATH_A]);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x6);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++				power_trim_info->bb_gain[5][RF_PATH_A]);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x7);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++				power_trim_info->bb_gain[6][RF_PATH_A]);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x8);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++				power_trim_info->bb_gain[7][RF_PATH_A]);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xe);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++				power_trim_info->bb_gain[7][RF_PATH_A]);
++		}
++
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, BIT(19), 0);
++	}
++
++}
++
++void phydm_get_set_power_trim_offset_8195b(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_power = 0xff, i, j;
++
++	odm_efuse_one_byte_read(dm, PPG_2GL_TXA_95B, &pg_power, false);
++
++	if (pg_power != 0xff) {
++		odm_efuse_one_byte_read(dm, PPG_2GL_TXA_95B, &pg_power, false);
++		power_trim_info->bb_gain[0][0] = pg_power & 0xf;
++
++		odm_efuse_one_byte_read(dm, PPG_2GM_TXA_95B, &pg_power, false);
++		power_trim_info->bb_gain[1][0] = pg_power & 0xf;
++
++		odm_efuse_one_byte_read(dm, PPG_2GH_TXA_95B, &pg_power, false);
++		power_trim_info->bb_gain[2][0] = pg_power & 0xf;
++
++		power_trim_info->flag =
++			power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G;
++	}
++
++	pg_power = 0xff;
++
++	odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_95B, &pg_power, false);
++
++	if (pg_power != 0xff) {
++		odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_95B, &pg_power, false);
++		power_trim_info->bb_gain[3][0] = pg_power & 0x1f;
++
++		odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_95B, &pg_power, false);
++		power_trim_info->bb_gain[4][0] = pg_power & 0x1f;
++
++		odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_95B, &pg_power, false);
++		power_trim_info->bb_gain[5][0] = pg_power & 0x1f;
++
++		odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_95B, &pg_power, false);
++		power_trim_info->bb_gain[6][0] = pg_power & 0x1f;
++
++		odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_95B, &pg_power, false);
++		power_trim_info->bb_gain[7][0] = pg_power & 0x1f;
++
++		power_trim_info->flag =
++			power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_5G;
++	}
++
++	phydm_set_power_trim_rf_8195b(dm);
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8195b power trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_ON) {
++		for (i = 0; i < KFREE_BAND_NUM; i++) {
++			for (j = 0; j < 1; j++) {
++				RF_DBG(dm, DBG_RF_MP,
++				       "[kfree] 8195b pwr_trim->bb_gain[%d][%d]=0x%X\n",
++				       i, j, power_trim_info->bb_gain[i][j]);
++			}
++		}
++	}
++}
++
++void phydm_get_set_pa_bias_offset_8195b(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_pa_bias = 0xff;
++
++	RF_DBG(dm, DBG_RF_MP, "======>%s\n", __func__);
++
++	/*2G*/
++	odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_95B, &pg_pa_bias, false);
++
++	if (pg_pa_bias != 0xff) {
++		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_95B,
++					&pg_pa_bias, false);
++		pg_pa_bias = pg_pa_bias & 0xf;
++
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 2G pa_bias=0x%x\n", pg_pa_bias);
++
++		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x0000f000, pg_pa_bias);
++	} else {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8195b 2G tx pa bias no pg\n");
++	}
++
++	/*5G*/
++	pg_pa_bias = 0xff;
++
++	odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_95B, &pg_pa_bias, false);
++
++	if (pg_pa_bias != 0xff) {
++		odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_95B,
++					&pg_pa_bias, false);
++		pg_pa_bias = pg_pa_bias & 0xf;
++
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 5G pa_bias=0x%x\n", pg_pa_bias);
++
++		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x000f0000, pg_pa_bias);
++
++		power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
++	} else {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8195b 5G tx pa bias no pg\n");
++	}
++}
++
++void phydm_get_thermal_trim_offset_8721d(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_therm = 0xff;
++
++	odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_8721D, &pg_therm, false);
++
++	if (pg_therm != 0xff) {
++		pg_therm = pg_therm & 0x1f;
++		if ((pg_therm & BIT(0)) == 0)
++			power_trim_info->thermal = (-1 * (pg_therm >> 1));
++		else
++			power_trim_info->thermal = (pg_therm >> 1);
++
++		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8721d thermal trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8721d thermal:%d\n",
++		       power_trim_info->thermal);
++}
++
++void phydm_set_power_trim_rf_8721d(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] %s:Set kfree to rf 0x33\n", __func__);
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, BIT(19), 1);
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x0);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++		       power_trim_info->bb_gain[0][RF_PATH_A]);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x1);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++		       power_trim_info->bb_gain[1][RF_PATH_A]);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x2);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++		       power_trim_info->bb_gain[2][RF_PATH_A]);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x3);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++		       power_trim_info->bb_gain[2][RF_PATH_A]);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x4);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++		       power_trim_info->bb_gain[3][RF_PATH_A]);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x5);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++		       power_trim_info->bb_gain[4][RF_PATH_A]);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x6);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++		       power_trim_info->bb_gain[5][RF_PATH_A]);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x7);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++		       power_trim_info->bb_gain[6][RF_PATH_A]);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x8);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
++		       power_trim_info->bb_gain[7][RF_PATH_A]);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x9);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
++		       power_trim_info->bb_gain[3][RF_PATH_A]);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xa);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
++		       power_trim_info->bb_gain[4][RF_PATH_A]);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xb);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
++		       power_trim_info->bb_gain[5][RF_PATH_A]);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xc);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
++		       power_trim_info->bb_gain[6][RF_PATH_A]);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xd);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
++		       power_trim_info->bb_gain[7][RF_PATH_A]);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xe);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
++		       power_trim_info->bb_gain[7][RF_PATH_A]);
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, BIT(19), 0);
++}
++
++void phydm_get_set_power_trim_offset_8721d(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_power = 0xff, i, j;
++	u8 pg_power1, pg_power2, pg_power3, pg_power4, pg_power5, pg_power6;
++
++	odm_efuse_one_byte_read(dm, PPG_2G_TXA_8721D, &pg_power1, false);
++	odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_8721D, &pg_power2, false);
++	odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_8721D, &pg_power3, false);
++	odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_8721D, &pg_power4, false);
++	odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_8721D, &pg_power5, false);
++	odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_8721D, &pg_power6, false);
++
++	if (pg_power1 != 0xff || pg_power2 != 0xff || pg_power3 != 0xff ||
++	    pg_power4 != 0xff || pg_power5 != 0xff || pg_power6 != 0xff) {
++		odm_efuse_one_byte_read(dm, PPG_2G_TXA_8721D, &pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[0][0] = pg_power & 0xf;
++		power_trim_info->bb_gain[1][0] = pg_power & 0xf;
++		power_trim_info->bb_gain[2][0] = pg_power & 0xf;
++
++		odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_8721D,
++					&pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[3][0] = pg_power & 0x1f;
++
++		odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_8721D,
++					&pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[4][0] = pg_power & 0x1f;
++
++		odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_8721D,
++					&pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[5][0] = pg_power & 0x1f;
++
++		odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_8721D,
++					&pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[6][0] = pg_power & 0x1f;
++
++		odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_8721D,
++					&pg_power, false);
++		if (pg_power == 0xff)
++			pg_power = 0;
++		power_trim_info->bb_gain[7][0] = pg_power & 0x1f;
++
++		power_trim_info->flag =
++			power_trim_info->flag | KFREE_FLAG_ON |
++						KFREE_FLAG_ON_2G |
++						KFREE_FLAG_ON_5G;
++
++		phydm_set_power_trim_rf_8721d(dm);
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8721d power trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_ON) {
++		for (i = 0; i < KFREE_BAND_NUM; i++) {
++			for (j = 0; j < 1; j++) {
++				RF_DBG(dm, DBG_RF_MP,
++				       "[kfree] 8721d pwr_trim->bb_gain[%d][%d]=0x%X\n",
++				       i, j, power_trim_info->bb_gain[i][j]);
++			}
++		}
++	}
++}
++
++void phydm_get_set_pa_bias_offset_8721d(void *dm_void)
++{
++#if 0
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_pa_bias = 0xff;
++
++	RF_DBG(dm, DBG_RF_MP, "======>%s\n", __func__);
++
++	odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_95B, &pg_pa_bias, false);
++
++	if (pg_pa_bias != 0xff) {
++		/*2G*/
++		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_95B,
++					&pg_pa_bias, false);
++		pg_pa_bias = pg_pa_bias & 0xf;
++
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 2G pa_bias=0x%x\n", pg_pa_bias);
++
++		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x0000f000, pg_pa_bias);
++
++		/*5G*/
++		odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_95B,
++					&pg_pa_bias, false);
++		pg_pa_bias = pg_pa_bias & 0xf;
++
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 5G pa_bias=0x%x\n", pg_pa_bias);
++
++		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x000f0000, pg_pa_bias);
++
++		power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
++	} else {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8721d tx pa bias no pg\n");
++	}
++#endif
++}
++
++void phydm_get_thermal_trim_offset_8197g(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_therm = 0xff, i;
++
++	odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_97G, &pg_therm, false);
++
++	if (pg_therm != 0xff) {
++		for (i = 0; i < 2; i++) {
++			if (i == 0)
++				odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_97G, &pg_therm, false);
++			else if (i == 1)
++				odm_efuse_one_byte_read(dm, PPG_THERMAL_B_OFFSET_97G, &pg_therm, false);
++
++			RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g Efuse thermal S%d:0x%x\n", i, pg_therm);
++
++			pg_therm = pg_therm & 0x1f;
++			if ((pg_therm & BIT(0)) == 0)
++				power_trim_info->multi_thermal[i] = (-1 * (pg_therm >> 1));
++			else
++				power_trim_info->multi_thermal[i] = (pg_therm >> 1);
++		}
++
++		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g thermal trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	for (i = 0; i < 2; i++) {
++		if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
++			RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g thermal S%d:%d\n",
++			       i ,power_trim_info->multi_thermal[i]);
++	}
++}
++
++void phydm_set_power_trim_offset_8197g(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++	u8 e_rf_path;
++
++	for (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++)
++	{
++		odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 1);
++
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 0);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F,
++			power_trim_info->bb_gain[0][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 1);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F,
++			power_trim_info->bb_gain[0][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 2);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, 
++			power_trim_info->bb_gain[1][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 3);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, 
++			power_trim_info->bb_gain[1][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 4);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, 
++			power_trim_info->bb_gain[2][e_rf_path]);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 5);
++		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, 
++			power_trim_info->bb_gain[2][e_rf_path]);
++
++		odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 0);
++	}
++
++}
++
++void phydm_get_set_power_trim_offset_8197g(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_power = 0, i, j;
++
++	odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_97G, &pg_power, false);
++
++	if (pg_power != 0) {
++		power_trim_info->bb_gain[0][0] = pg_power & 0xf;
++		power_trim_info->bb_gain[0][1] = (pg_power & 0xf0) >> 4;
++
++		odm_efuse_one_byte_read(dm, PPG_2GM_TXAB_97G, &pg_power, false);
++		power_trim_info->bb_gain[1][0] = pg_power & 0xf;
++		power_trim_info->bb_gain[1][1] = (pg_power & 0xf0) >> 4;
++
++		odm_efuse_one_byte_read(dm, PPG_2GH_TXAB_97G, &pg_power, false);
++		power_trim_info->bb_gain[2][0] = pg_power & 0xf;
++		power_trim_info->bb_gain[2][1] = (pg_power & 0xf0) >> 4;
++
++		phydm_set_power_trim_offset_8197g(dm);
++
++		power_trim_info->flag =
++			power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G;
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g power trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_ON) {
++		for (i = 0; i < KFREE_BAND_NUM; i++) {
++			for (j = 0; j < MAX_RF_PATH; j++) {
++				RF_DBG(dm, DBG_RF_MP,
++				       "[kfree] 8197g pwr_trim->bb_gain[%d][%d]=0x%X\n",
++				       i, j, power_trim_info->bb_gain[i][j]);
++			}
++		}
++	}
++}
++
++void phydm_get_tssi_trim_offset_8197g(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 i, j = 0;
++	u8 pg_power[4] = {0};
++
++	odm_efuse_one_byte_read(dm, TSSI_2GL_TXA_97G, &pg_power[0], false);
++	odm_efuse_one_byte_read(dm, TSSI_2GL_TXB_97G, &pg_power[1], false);
++	odm_efuse_one_byte_read(dm, TSSI_2GH_TXA_97G, &pg_power[2], false);
++	odm_efuse_one_byte_read(dm, TSSI_2GH_TXB_97G, &pg_power[3], false);
++
++	for (i = 0; i < 4; i++) {
++		if (pg_power[i] == 0xff)
++			j++;
++	}
++
++	if (j == 3) {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g tssi trim no PG\n");
++		return;
++	} else {
++		power_trim_info->tssi_trim[0][0] = (s8)pg_power[0];
++		power_trim_info->tssi_trim[0][1] = (s8)pg_power[1];
++		power_trim_info->tssi_trim[1][0] = (s8)pg_power[0];
++		power_trim_info->tssi_trim[1][1] = (s8)pg_power[1];
++		power_trim_info->tssi_trim[2][0] = (s8)pg_power[2];
++		power_trim_info->tssi_trim[2][1] = (s8)pg_power[3];
++
++		power_trim_info->flag =
++			power_trim_info->flag | TSSI_TRIM_FLAG_ON;
++
++		for (i = 0; i < KFREE_BAND_NUM; i++) {
++			for (j = 0; j < MAX_PATH_NUM_8197G; j++) {
++				RF_DBG(dm, DBG_RF_MP,
++				       "[kfree] 8197g tssi_trim[%d][%d]=0x%X\n",
++				       i, j, power_trim_info->tssi_trim[i][j]);
++			}
++		}
++	}
++}
++
++s8 phydm_get_tssi_trim_de_8197g(void *dm_void, u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 channel = *dm->channel, group = 0;
++
++	if (channel >= 1 && channel <= 3)
++		group = 0;
++	else if (channel >= 4 && channel <= 9)
++		group = 1;
++	else if (channel >= 10 && channel <= 14)
++		group = 2;
++	else {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] Channel(%d) is not exist in Group\n",
++			channel);
++		return 0;
++	}
++
++	return power_trim_info->tssi_trim[group][path];
++}
++
++void phydm_get_set_pa_bias_offset_8197g(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_pa_bias = 0xff, i;
++	u8 tx_pa_bias[4] = {0};
++
++	odm_efuse_one_byte_read(dm, PPG_PABIAS_2GAB_97G, &pg_pa_bias, false);
++
++	if (pg_pa_bias != 0xff) {
++		/*paht ab*/
++		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GAB_97G,
++					&pg_pa_bias, false);
++		tx_pa_bias[0] = pg_pa_bias & 0xf;
++		tx_pa_bias[1] = ((pg_pa_bias & 0xf0) >> 4);
++
++		RF_DBG(dm, DBG_RF_MP,
++		       "[kfree] 8197g PathA_pa_bias:0x%x PathB_pa_bias:0x%x\n",
++		       tx_pa_bias[0], tx_pa_bias[1]);
++
++		for (i = RF_PATH_A; i < 2; i++)
++			odm_set_rf_reg(dm, i, 0x60, 0x0000f000, tx_pa_bias[i]);
++
++		power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
++	} else {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g tx pa bias no pg\n");
++	}
++}
++
++void phydm_get_set_lna_offset_8197g(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_lna[2] = {0}, i, pg_lna_tmp = 0;
++	u32 lna_trim_addr[2] = {0x1884, 0x4184};
++
++	odm_efuse_one_byte_read(dm, PPG_LNA_2GA_97G, &pg_lna_tmp, false);
++
++	if (pg_lna_tmp != 0) {
++		odm_efuse_one_byte_read(dm, PPG_LNA_2GA_97G,
++					&pg_lna[RF_PATH_A], false);
++		power_trim_info->lna_trim[RF_PATH_A] = (s8)pg_lna[RF_PATH_A];
++
++		odm_efuse_one_byte_read(dm, PPG_LNA_2GB_97G,
++					&pg_lna[RF_PATH_B], false);
++		power_trim_info->lna_trim[RF_PATH_B] = (s8)pg_lna[RF_PATH_B];
++
++		for (i = RF_PATH_A; i < 2; i++) {
++			if (odm_get_bb_reg(dm, lna_trim_addr[i], 0x00c00000) == 0x2) {
++				odm_set_rf_reg(dm, i, 0x88, 0x00000f00, (pg_lna[i] & 0xf));
++				RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g lna trim CG 0x%x path=%d\n", (pg_lna[i] & 0xf), i);
++			} else if (odm_get_bb_reg(dm, lna_trim_addr[i], 0x00c00000) == 0x3) {
++				odm_set_rf_reg(dm, i, 0x88, 0x00000f00, ((pg_lna[i] & 0xf0) >> 4));
++				RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g lna trim CS 0x%x path=%d\n", ((pg_lna[i] & 0xf0) >> 4), i);
++			}
++		}
++
++		power_trim_info->lna_flag |= LNA_FLAG_ON;
++	} else {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g lna trim no pg\n");
++	}
++}
++
++void phydm_set_lna_trim_offset_8197g(void *dm_void, u8 path, u8 cg_cs, u8 enable)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *trim = &dm->power_trim_data;
++
++	u8 i;
++
++	if (enable == 0) {
++		for (i = RF_PATH_A; i < 2; i++) {
++			odm_set_rf_reg(dm, i, 0x88, 0x00000f00, 0x0);
++			RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g diversity lna trim disable\n");
++		}
++		return;
++	}
++
++	/*cg*/
++	if (cg_cs == 0) {
++		odm_set_rf_reg(dm, path, 0x88, 0x00000f00, (trim->lna_trim[path] & 0xf));
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g diversity lna trim CG 0x%x path=%d\n",
++			(trim->lna_trim[path] & 0xf), path);
++	} else if (cg_cs == 1) {	/*cs*/
++		odm_set_rf_reg(dm, path, 0x88, 0x00000f00, ((trim->lna_trim[path] & 0xf0) >> 4));
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g diversity lna trim CS 0x%x path=%d\n",
++			((trim->lna_trim[path] & 0xf0) >> 4), path);
++	}
++}
++
++
++void phydm_get_thermal_trim_offset_8710c(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_therm = 0;
++
++	odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_10C, &pg_therm, false);
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8710c Efuse thermal:0x%x\n", pg_therm);
++
++	if (pg_therm != 0xff) {
++		pg_therm = pg_therm & 0x1f;
++		if ((pg_therm & BIT(0)) == 0)
++			power_trim_info->thermal = (-1 * (pg_therm >> 1));
++		else
++			power_trim_info->thermal = (pg_therm >> 1);
++
++		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8710c thermal trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8710c thermal:%d\n",
++		       power_trim_info->thermal);
++}
++
++void phydm_set_power_trim_offset_8710c(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(18), 1);
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x3f,
++		power_trim_info->bb_gain[0][RF_PATH_A]);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 1);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x3f,
++		power_trim_info->bb_gain[1][RF_PATH_A]);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 2);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x3f, 
++		power_trim_info->bb_gain[2][RF_PATH_A]);
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(18), 0);
++}
++
++void phydm_get_set_power_trim_offset_8710c(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_power = 0, i, j;
++
++	odm_efuse_one_byte_read(dm, PPG_2GL_TX_10C, &pg_power, false);
++
++	if (pg_power != 0xff) {
++		power_trim_info->bb_gain[0][RF_PATH_A] = pg_power & 0xf;
++
++		odm_efuse_one_byte_read(dm, PPG_2GM_TX_10C, &pg_power, false);
++		power_trim_info->bb_gain[1][RF_PATH_A] = pg_power & 0xf;
++
++		odm_efuse_one_byte_read(dm, PPG_2GH_TX_10C, &pg_power, false);
++		power_trim_info->bb_gain[2][RF_PATH_A] = pg_power & 0xf;
++
++		phydm_set_power_trim_offset_8710c(dm);
++
++		power_trim_info->flag =
++			power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G;
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8710c power trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	if (power_trim_info->flag & KFREE_FLAG_ON) {
++		for (i = 0; i < KFREE_BAND_NUM; i++) {
++			for (j = 0; j < MAX_RF_PATH; j++) {
++				RF_DBG(dm, DBG_RF_MP,
++				       "[kfree] 8710c pwr_trim->bb_gain[%d][%d]=0x%X\n",
++				       i, j, power_trim_info->bb_gain[i][j]);
++			}
++		}
++	}
++}
++
++void phydm_get_set_pa_bias_offset_8710c(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_pa_bias = 0xff;
++	u8 tx_pa_bias = 0;
++
++	odm_efuse_one_byte_read(dm, PPG_PABIAS_10C, &pg_pa_bias, false);
++
++	if (pg_pa_bias != 0xff) {
++		tx_pa_bias = pg_pa_bias & 0xf;
++
++		RF_DBG(dm, DBG_RF_MP,
++		       "[kfree] 8710c PathA_pa_bias:0x%x\n", tx_pa_bias);
++
++		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x0000f000, tx_pa_bias);
++
++		power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
++	} else {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] 8710c tx pa bias no pg\n");
++	}
++}
++
++void phydm_get_thermal_trim_offset_8814b(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	u8 pg_therm = 0xff, i;
++
++	odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_14B, &pg_therm, false);
++
++	if (pg_therm != 0xff) {
++		for (i = 0; i < MAX_RF_PATH; i++) {
++			if (i == 0)
++				odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_14B, &pg_therm, false);
++			else if (i == 1)
++				odm_efuse_one_byte_read(dm, PPG_THERMAL_B_OFFSET_14B, &pg_therm, false);
++			else if (i == 2)
++				odm_efuse_one_byte_read(dm, PPG_THERMAL_C_OFFSET_14B, &pg_therm, false);
++			else if (i == 3)
++				odm_efuse_one_byte_read(dm, PPG_THERMAL_D_OFFSET_14B, &pg_therm, false);
++
++			RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b Efuse thermal S%d:0x%x\n", i, pg_therm);
++			pg_therm = pg_therm & 0x1f;
++			if ((pg_therm & BIT(0)) == 0)
++				power_trim_info->multi_thermal[i] = (-1 * (pg_therm >> 1));
++			else
++				power_trim_info->multi_thermal[i] = (pg_therm >> 1);
++		}
++
++		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
++	}
++
++	RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b thermal trim flag:0x%02x\n",
++	       power_trim_info->flag);
++
++	for (i = 0; i < MAX_RF_PATH; i++) {
++		if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
++			RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b thermal S%d:%d\n",
++			       i ,power_trim_info->multi_thermal[i]);
++	}
++}
++
++s8 phydm_get_tssi_trim_de(void *dm_void, u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & ODM_RTL8822C)
++		return phydm_get_tssi_trim_de_8822c(dm, path);
++	else if (dm->support_ic_type & ODM_RTL8812F)
++		return phydm_get_tssi_trim_de_8812f(dm, path);
++	else if (dm->support_ic_type & ODM_RTL8197G)
++		return phydm_get_tssi_trim_de_8197g(dm, path);
++	else
++		return 0;	
++}
++
++void phydm_do_new_kfree(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & ODM_RTL8822C) {
++		phydm_get_set_thermal_trim_offset_8822c(dm);
++		phydm_get_set_power_trim_offset_8822c(dm);
++		phydm_get_set_pa_bias_offset_8822c(dm);
++		phydm_get_tssi_trim_offset_8822c(dm);
++	}
++
++	if (dm->support_ic_type & ODM_RTL8812F) {
++		phydm_get_set_thermal_trim_offset_8812f(dm);
++		phydm_get_set_power_trim_offset_8812f(dm);
++		phydm_get_set_pa_bias_offset_8812f(dm);
++		phydm_get_tssi_trim_offset_8812f(dm);
++	}
++
++	if (dm->support_ic_type & ODM_RTL8195B) {
++		phydm_get_thermal_trim_offset_8195b(dm);
++		phydm_get_set_power_trim_offset_8195b(dm);
++		phydm_get_set_pa_bias_offset_8195b(dm);
++	}
++
++	if (dm->support_ic_type & ODM_RTL8721D) {
++		phydm_get_thermal_trim_offset_8721d(dm);
++		phydm_get_set_power_trim_offset_8721d(dm);
++		/*phydm_get_set_pa_bias_offset_8721d(dm);*/
++	}
++
++	if (dm->support_ic_type & ODM_RTL8198F) {
++		phydm_get_pa_bias_offset_8198f(dm);
++		phydm_get_set_lna_offset_8198f(dm);
++	}
++
++	if (dm->support_ic_type & ODM_RTL8197G) {
++		phydm_get_thermal_trim_offset_8197g(dm);
++		phydm_get_set_power_trim_offset_8197g(dm);
++		phydm_get_set_pa_bias_offset_8197g(dm);
++		phydm_get_tssi_trim_offset_8197g(dm);
++		phydm_get_set_lna_offset_8197g(dm);
++	}
++
++	if (dm->support_ic_type & ODM_RTL8710C) {
++		phydm_get_thermal_trim_offset_8710c(dm);
++		phydm_get_set_power_trim_offset_8710c(dm);
++		phydm_get_set_pa_bias_offset_8710c(dm);
++	}
++
++	if (dm->support_ic_type & ODM_RTL8814B) {
++		phydm_get_thermal_trim_offset_8814b(dm);
++		/*phydm_get_set_power_trim_offset_8814b(dm);*/
++		/*phydm_get_set_pa_bias_offset_8814b(dm);*/
++	}
++}
++
++void phydm_set_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & ODM_RTL8814A)
++		phydm_set_kfree_to_rf_8814a(dm, e_rf_path, data);
++
++	if ((dm->support_ic_type & ODM_RTL8821C) &&
++	    (*dm->band_type == ODM_BAND_2_4G))
++		phydm_set_kfree_to_rf_8821c(dm, e_rf_path, true, data);
++	else if (dm->support_ic_type & ODM_RTL8821C)
++		phydm_set_kfree_to_rf_8821c(dm, e_rf_path, false, data);
++
++	if (dm->support_ic_type & ODM_RTL8822B)
++		phydm_set_kfree_to_rf_8822b(dm, e_rf_path, data);
++
++	if (dm->support_ic_type & ODM_RTL8710B)
++		phydm_set_kfree_to_rf_8710b(dm, e_rf_path, data);
++
++	if (dm->support_ic_type & ODM_RTL8198F)
++		phydm_set_kfree_to_rf_8198f(dm, e_rf_path, data);
++}
++
++void phydm_clear_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & ODM_RTL8822B)
++		phydm_clear_kfree_to_rf_8822b(dm, e_rf_path, 1);
++
++	if (dm->support_ic_type & ODM_RTL8821C)
++		phydm_clear_kfree_to_rf_8821c(dm, e_rf_path, 1);
++
++	if (dm->support_ic_type & ODM_RTL8198F)
++		phydm_clear_kfree_to_rf_8198f(dm, e_rf_path, 0);
++}
++
++void phydm_get_thermal_trim_offset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal;
++	u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
++
++	if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
++		RF_DBG(dm, DBG_RF_MP, "[kfree] dump efuse fail !!!\n");
++#endif
++
++	if (dm->support_ic_type & ODM_RTL8821C)
++		phydm_get_thermal_trim_offset_8821c(dm_void);
++	else if (dm->support_ic_type & ODM_RTL8822B)
++		phydm_get_thermal_trim_offset_8822b(dm_void);
++	else if (dm->support_ic_type & ODM_RTL8710B)
++		phydm_get_thermal_trim_offset_8710b(dm_void);
++	else if (dm->support_ic_type & ODM_RTL8192F)
++		phydm_get_thermal_trim_offset_8192f(dm_void);
++	else if (dm->support_ic_type & ODM_RTL8198F)
++		phydm_get_thermal_trim_offset_8198f(dm_void);
++}
++
++void phydm_get_power_trim_offset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if 0 //(DM_ODM_SUPPORT_TYPE & ODM_WIN)	// 2017 MH DM Should use the same code.s
++	void		*adapter = dm->adapter;
++	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	PEFUSE_HAL		pEfuseHal = &hal_data->EfuseHal;
++	u1Byte			eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
++
++	if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO(adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
++		RF_DBG(dm, DBG_RF_MP, "[kfree] dump efuse fail !!!\n");
++#endif
++
++	if (dm->support_ic_type & ODM_RTL8821C)
++		phydm_get_power_trim_offset_8821c(dm_void);
++	else if (dm->support_ic_type & ODM_RTL8822B)
++		phydm_get_power_trim_offset_8822b(dm_void);
++	else if (dm->support_ic_type & ODM_RTL8710B)
++		phydm_get_power_trim_offset_8710b(dm_void);
++	else if (dm->support_ic_type & ODM_RTL8192F)
++		phydm_get_power_trim_offset_8192f(dm_void);
++	else if (dm->support_ic_type & ODM_RTL8198F)
++		phydm_get_power_trim_offset_8198f(dm_void);
++}
++
++void phydm_get_pa_bias_offset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal;
++	u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
++
++	if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
++		RF_DBG(dm, DBG_RF_MP, "[kfree] dump efuse fail !!!\n");
++#endif
++
++	if (dm->support_ic_type & ODM_RTL8822B)
++		phydm_get_pa_bias_offset_8822b(dm_void);
++}
++
++s8 phydm_get_thermal_offset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
++		return power_trim_info->thermal;
++	else
++		return 0;
++}
++
++s8 phydm_get_multi_thermal_offset(void *dm_void, u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
++
++	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
++		return power_trim_info->multi_thermal[path];
++	else
++		return 0;
++}
++
++void phydm_do_kfree(void *dm_void, u8 channel_to_sw)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_power_trim_data *pwrtrim = &dm->power_trim_data;
++	u8 channel_idx = 0, rfpath = 0, max_path = 0, kfree_band_num = 0;
++	u8 i, j;
++	s8 bb_gain;
++
++	if (dm->support_ic_type & ODM_RTL8814A)
++		max_path = 4; /*0~3*/
++	else if (dm->support_ic_type &
++		 (ODM_RTL8812 | ODM_RTL8822B | ODM_RTL8192F)) {
++		max_path = 2; /*0~1*/
++		kfree_band_num = KFREE_BAND_NUM;
++	} else if (dm->support_ic_type & ODM_RTL8821C) {
++		max_path = 1;
++		kfree_band_num = KFREE_BAND_NUM;
++	} else if (dm->support_ic_type & ODM_RTL8710B) {
++		max_path = 1;
++		kfree_band_num = 1;
++	} else if (dm->support_ic_type & ODM_RTL8198F) {
++		max_path = 4;
++		kfree_band_num = 3;
++	}
++
++	if (dm->support_ic_type &
++	    (ODM_RTL8192F | ODM_RTL8822B | ODM_RTL8821C |
++	    ODM_RTL8814A | ODM_RTL8710B)) {
++		for (i = 0; i < kfree_band_num; i++) {
++			for (j = 0; j < max_path; j++)
++				RF_DBG(dm, DBG_RF_MP,
++				       "[kfree] PwrTrim->gain[%d][%d]=0x%X\n",
++				       i, j, pwrtrim->bb_gain[i][j]);
++		}
++	}
++	if (*dm->band_type == ODM_BAND_2_4G &&
++	    pwrtrim->flag & KFREE_FLAG_ON_2G) {
++		if (!(dm->support_ic_type & ODM_RTL8192F)) {
++			if (channel_to_sw >= 1 && channel_to_sw <= 14)
++				channel_idx = PHYDM_2G;
++			for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {
++				RF_DBG(dm, DBG_RF_MP,
++				       "[kfree] %s:chnl=%d PATH=%d gain:0x%X\n",
++				       __func__, channel_to_sw, rfpath,
++				       pwrtrim->bb_gain[channel_idx][rfpath]);
++				bb_gain = pwrtrim->bb_gain[channel_idx][rfpath];
++				phydm_set_kfree_to_rf(dm, rfpath, bb_gain);
++			}
++		} else if (dm->support_ic_type & ODM_RTL8192F) {
++			if (channel_to_sw >= 1 && channel_to_sw <= 3)
++				channel_idx = 0;
++			if (channel_to_sw >= 4 && channel_to_sw <= 9)
++				channel_idx = 1;
++			if (channel_to_sw >= 10 && channel_to_sw <= 14)
++				channel_idx = 2;
++			for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {
++				RF_DBG(dm, DBG_RF_MP,
++				       "[kfree] %s:chnl=%d PATH=%d gain:0x%X\n",
++				       __func__, channel_to_sw, rfpath,
++				       pwrtrim->bb_gain[channel_idx][rfpath]);
++				bb_gain = pwrtrim->bb_gain[channel_idx][rfpath];
++				phydm_set_kfree_to_rf_8192f(dm, rfpath,
++							    channel_idx,
++							    bb_gain);
++			}
++		}
++	} else if (*dm->band_type == ODM_BAND_5G &&
++		   pwrtrim->flag & KFREE_FLAG_ON_5G) {
++		if (channel_to_sw >= 36 && channel_to_sw <= 48)
++			channel_idx = PHYDM_5GLB1;
++		if (channel_to_sw >= 52 && channel_to_sw <= 64)
++			channel_idx = PHYDM_5GLB2;
++		if (channel_to_sw >= 100 && channel_to_sw <= 120)
++			channel_idx = PHYDM_5GMB1;
++		if (channel_to_sw >= 122 && channel_to_sw <= 144)
++			channel_idx = PHYDM_5GMB2;
++		if (channel_to_sw >= 149 && channel_to_sw <= 177)
++			channel_idx = PHYDM_5GHB;
++
++		for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {
++			RF_DBG(dm, DBG_RF_MP,
++			       "[kfree] %s: channel=%d PATH=%d bb_gain:0x%X\n",
++			       __func__, channel_to_sw, rfpath,
++			       pwrtrim->bb_gain[channel_idx][rfpath]);
++			bb_gain = pwrtrim->bb_gain[channel_idx][rfpath];
++			phydm_set_kfree_to_rf(dm, rfpath, bb_gain);
++		}
++	} else {
++		RF_DBG(dm, DBG_RF_MP, "[kfree] Set default Register\n");
++		if (!(dm->support_ic_type & ODM_RTL8192F)) {
++			for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {
++				bb_gain = pwrtrim->bb_gain[channel_idx][rfpath];
++				phydm_clear_kfree_to_rf(dm, rfpath, bb_gain);
++			}
++		}
++#if 0
++		/*else if(dm->support_ic_type & ODM_RTL8192F){
++			if (channel_to_sw >= 1 && channel_to_sw <= 3)
++				channel_idx = 0;
++			if (channel_to_sw >= 4 && channel_to_sw <= 9)
++				channel_idx = 1;
++			if (channel_to_sw >= 9 && channel_to_sw <= 14)
++				channel_idx = 2;
++			for (rfpath = RF_PATH_A;  rfpath < max_path; rfpath++)
++				phydm_clear_kfree_to_rf_8192f(dm, rfpath, pwrtrim->bb_gain[channel_idx][rfpath]);
++		}*/
++#endif
++	}
++}
++
++void phydm_config_new_kfree(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
++
++	if (cali_info->reg_rf_kfree_enable == 2) {
++		RF_DBG(dm, DBG_RF_MP,
++		       "[kfree] %s: reg_rf_kfree_enable == 2, Disable\n",
++		       __func__);
++		return;
++	} else if (cali_info->reg_rf_kfree_enable == 1 ||
++			cali_info->reg_rf_kfree_enable == 0) {
++		RF_DBG(dm, DBG_RF_MP,
++		       "[kfree] %s: reg_rf_kfree_enable == true\n", __func__);
++	
++		phydm_do_new_kfree(dm);
++	}
++}
++
++void phydm_config_kfree(void *dm_void, u8 channel_to_sw)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
++	struct odm_power_trim_data *pwrtrim = &dm->power_trim_data;
++
++	RF_DBG(dm, DBG_RF_MP, "===>[kfree] phy_ConfigKFree()\n");
++
++	if (cali_info->reg_rf_kfree_enable == 2) {
++		RF_DBG(dm, DBG_RF_MP,
++		       "[kfree] %s: reg_rf_kfree_enable == 2, Disable\n",
++		       __func__);
++		return;
++	} else if (cali_info->reg_rf_kfree_enable == 1 ||
++			cali_info->reg_rf_kfree_enable == 0) {
++		RF_DBG(dm, DBG_RF_MP,
++		       "[kfree] %s: reg_rf_kfree_enable == true\n", __func__);
++		/*Make sure the targetval is defined*/
++		if (!(pwrtrim->flag & KFREE_FLAG_ON)) {
++			RF_DBG(dm, DBG_RF_MP,
++			       "[kfree] %s: efuse is 0xff, KFree not work\n",
++			       __func__);
++			return;
++		}
++#if 0
++		/*if kfree_table[0] == 0xff, means no Kfree*/
++#endif
++		phydm_do_kfree(dm, channel_to_sw);
++	}
++	RF_DBG(dm, DBG_RF_MP, "<===[kfree] phy_ConfigKFree()\n");
++}
++
++void phydm_set_lna_trim_offset (void *dm_void, u8 path, u8 cg_cs, u8 enable)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & ODM_RTL8197G)
++		phydm_set_lna_trim_offset_8197g(dm, path, cg_cs, enable);
++}
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_kfree.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_kfree.h
+new file mode 100644
+index 000000000..ac5fe0161
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_kfree.h
+@@ -0,0 +1,234 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_KFREE_H__
++#define __HALRF_KFREE_H__
++
++#define KFREE_VERSION "1.0"
++
++#define KFREE_BAND_NUM 9
++#define KFREE_CH_NUM 3
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
++
++#define BB_GAIN_NUM 6
++
++#endif
++
++#define KFREE_FLAG_ON BIT(0)
++#define KFREE_FLAG_THERMAL_K_ON BIT(1)
++
++#define KFREE_FLAG_ON_2G BIT(2)
++#define KFREE_FLAG_ON_5G BIT(3)
++
++#define PA_BIAS_FLAG_ON BIT(4)
++
++#define TSSI_TRIM_FLAG_ON BIT(5)
++
++#define LNA_FLAG_ON BIT(6)
++
++
++#define PPG_THERMAL_OFFSET_98F 0x50
++#define PPG_2GM_TXAB_98F 0x51
++#define PPG_2GM_TXCD_98F 0x52
++#define PPG_2GL_TXAB_98F 0x53
++#define PPG_2GL_TXCD_98F 0x54
++#define PPG_2GH_TXAB_98F 0x55
++#define PPG_2GH_TXCD_98F 0x56
++
++#define PPG_PABIAS_2GAB_98F 0x57
++#define PPG_PABIAS_2GCD_98F 0x58
++
++#define PPG_LNA_2GA_98F 0x59
++#define PPG_LNA_2GB_98F 0x5a
++#define PPG_LNA_2GC_98F 0x5b
++#define PPG_LNA_2GD_98F 0x5c
++
++#define PPG_THERMAL_OFFSET_21C 0x1EF
++#define PPG_2G_TXAB_21C 0x1EE
++#define PPG_5GL1_TXA_21C 0x1EC
++#define PPG_5GL2_TXA_21C 0x1E8
++#define PPG_5GM1_TXA_21C 0x1E4
++#define PPG_5GM2_TXA_21C 0x1E0
++#define PPG_5GH1_TXA_21C 0x1DC
++
++#define PPG_THERMAL_OFFSET_22B 0x3EF
++#define PPG_2G_TXAB_22B 0x3EE
++#define PPG_2G_TXCD_22B 0x3ED
++#define PPG_5GL1_TXA_22B 0x3EC
++#define PPG_5GL1_TXB_22B 0x3EB
++#define PPG_5GL1_TXC_22B 0x3EA
++#define PPG_5GL1_TXD_22B 0x3E9
++#define PPG_5GL2_TXA_22B 0x3E8
++#define PPG_5GL2_TXB_22B 0x3E7
++#define PPG_5GL2_TXC_22B 0x3E6
++#define PPG_5GL2_TXD_22B 0x3E5
++#define PPG_5GM1_TXA_22B 0x3E4
++#define PPG_5GM1_TXB_22B 0x3E3
++#define PPG_5GM1_TXC_22B 0x3E2
++#define PPG_5GM1_TXD_22B 0x3E1
++#define PPG_5GM2_TXA_22B 0x3E0
++#define PPG_5GM2_TXB_22B 0x3DF
++#define PPG_5GM2_TXC_22B 0x3DE
++#define PPG_5GM2_TXD_22B 0x3DD
++#define PPG_5GH1_TXA_22B 0x3DC
++#define PPG_5GH1_TXB_22B 0x3DB
++#define PPG_5GH1_TXC_22B 0x3DA
++#define PPG_5GH1_TXD_22B 0x3D9
++
++#define PPG_PABIAS_2GA_22B 0x3D5
++#define PPG_PABIAS_2GB_22B 0x3D6
++
++#define PPG_THERMAL_A_OFFSET_22C 0x1ef
++#define PPG_THERMAL_B_OFFSET_22C 0x1b0
++#define PPG_2GL_TXAB_22C 0x1d4
++#define PPG_2GM_TXAB_22C 0x1ee
++#define PPG_2GH_TXAB_22C 0x1d2
++#define PPG_5GL1_TXA_22C 0x1ec
++#define PPG_5GL1_TXB_22C 0x1eb
++#define PPG_5GL2_TXA_22C 0x1e8
++#define PPG_5GL2_TXB_22C 0x1e7
++#define PPG_5GM1_TXA_22C 0x1e4
++#define PPG_5GM1_TXB_22C 0x1e3
++#define PPG_5GM2_TXA_22C 0x1e0
++#define PPG_5GM2_TXB_22C 0x1df
++#define PPG_5GH1_TXA_22C 0x1dc
++#define PPG_5GH1_TXB_22C 0x1db
++
++#define PPG_PABIAS_2GA_22C 0x1d6
++#define PPG_PABIAS_2GB_22C 0x1d5
++#define PPG_PABIAS_5GA_22C 0x1d8
++#define PPG_PABIAS_5GB_22C 0x1d7
++
++#define TSSI_2GM_TXA_22C 0x1c0
++#define TSSI_2GM_TXB_22C 0x1bf
++#define TSSI_2GH_TXA_22C 0x1be
++#define TSSI_2GH_TXB_22C 0x1bd
++#define TSSI_5GL1_TXA_22C 0x1bc
++#define TSSI_5GL1_TXB_22C 0x1bb
++#define TSSI_5GL2_TXA_22C 0x1ba
++#define TSSI_5GL2_TXB_22C 0x1b9
++#define TSSI_5GM1_TXA_22C 0x1b8
++#define TSSI_5GM1_TXB_22C 0x1b7
++#define TSSI_5GM2_TXA_22C 0x1b6
++#define TSSI_5GM2_TXB_22C 0x1b5
++#define TSSI_5GH1_TXA_22C 0x1b4
++#define TSSI_5GH1_TXB_22C 0x1b3
++#define TSSI_5GH2_TXA_22C 0x1b2
++#define TSSI_5GH2_TXB_22C 0x1b1
++ 
++/*8195B*/
++#define PPG_THERMAL_OFFSET_95B 0x1ef
++#define PPG_2GL_TXA_95B 0x1d4
++#define PPG_2GM_TXA_95B 0x1ee
++#define PPG_2GH_TXA_95B 0x1d2
++#define PPG_5GL1_TXA_95B 0x1ec
++#define PPG_5GL2_TXA_95B 0x1e8
++#define PPG_5GM1_TXA_95B 0x1e4
++#define PPG_5GM2_TXA_95B 0x1e0
++#define PPG_5GH1_TXA_95B 0x1dc
++
++#define PPG_PABIAS_2GA_95B 0x1d6
++#define PPG_PABIAS_5GA_95B 0x1d8
++
++/*8721D*/
++/*#define KFREE_BAND_NUM_8721D 6*/
++#define PPG_THERMAL_OFFSET_8721D 0x1EF
++#define PPG_2G_TXA_8721D 0x1EE
++#define PPG_5GL1_TXA_8721D 0x1ED
++#define PPG_5GL2_TXA_8721D 0x1EC
++#define PPG_5GM1_TXA_8721D 0x1EB
++#define PPG_5GM2_TXA_8721D 0x1EA
++#define PPG_5GH1_TXA_8721D 0x1E9
++
++/*8197G*/
++#define PPG_THERMAL_A_OFFSET_97G 0x50
++#define PPG_THERMAL_B_OFFSET_97G 0x27
++#define PPG_2GM_TXAB_97G 0x51
++#define PPG_2GL_TXAB_97G 0x53
++#define PPG_2GH_TXAB_97G 0x55
++#define TSSI_2GL_TXA_97G 0x1c
++#define TSSI_2GL_TXB_97G 0x1d
++#define TSSI_2GH_TXA_97G 0x1e
++#define TSSI_2GH_TXB_97G 0x1f
++#define PPG_PABIAS_2GAB_97G 0x57
++#define PPG_LNA_2GA_97G 0x21
++#define PPG_LNA_2GB_97G 0x22
++
++/*8710C Ameba Z2*/
++#define PPG_THERMAL_OFFSET_10C 0x1EF
++#define PPG_2GL_TX_10C 0x1D4
++#define PPG_2GM_TX_10C 0x1EE
++#define PPG_2GH_TX_10C 0x1D2
++#define PPG_PABIAS_10C 0x1D6
++#define PPG_LNA_10C 0x1D0
++
++/*8814B*/
++#define PPG_THERMAL_A_OFFSET_14B 0x3D4
++#define PPG_THERMAL_B_OFFSET_14B 0x3D3
++#define PPG_THERMAL_C_OFFSET_14B 0x3D2
++#define PPG_THERMAL_D_OFFSET_14B 0x3D1
++
++struct odm_power_trim_data {
++	u8 flag;
++	u8 pa_bias_flag;
++	u8 lna_flag;
++	s8 bb_gain[KFREE_BAND_NUM][MAX_RF_PATH];
++	s8 tssi_trim[KFREE_BAND_NUM][MAX_RF_PATH];
++	s8 lna_trim[MAX_RF_PATH];
++	s8 thermal;
++	s8 multi_thermal[MAX_RF_PATH];
++};
++
++enum phydm_kfree_channeltosw {
++	PHYDM_2G = 0,
++	PHYDM_5GLB1 = 1,
++	PHYDM_5GLB2 = 2,
++	PHYDM_5GMB1 = 3,
++	PHYDM_5GMB2 = 4,
++	PHYDM_5GHB = 5,
++};
++
++void phydm_get_thermal_trim_offset(void *dm_void);
++
++void phydm_get_power_trim_offset(void *dm_void);
++
++void phydm_get_pa_bias_offset(void *dm_void);
++
++s8 phydm_get_thermal_offset(void *dm_void);
++
++s8 phydm_get_multi_thermal_offset(void *dm_void, u8 path);
++
++void phydm_clear_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data);
++
++void phydm_config_new_kfree(void *dm_void);
++
++s8 phydm_get_tssi_trim_de(void *dm_void, u8 path);
++
++void phydm_config_kfree(void *dm_void, u8 channel_to_sw);
++
++void phydm_set_lna_trim_offset (void *dm_void, u8 path, u8 cg_cs, u8 enable);
++
++#endif /*__HALRF_KFREE_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking.c
+new file mode 100644
+index 000000000..b77de6626
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking.c
+@@ -0,0 +1,183 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ * ************************************************************
++ */
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++boolean
++odm_check_power_status(void *dm_void)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	PADAPTER *adapter = dm->adapter;
++
++	RT_RF_POWER_STATE rt_state;
++	MGNT_INFO *mgnt_info = &((PADAPTER)adapter)->MgntInfo;
++
++	/* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */
++	if (mgnt_info->init_adpt_in_progress == true) {
++		RF_DBG(dm, DBG_RF_INIT,
++		       "check_pow_status Return true, due to initadapter\n");
++		return true;
++	}
++
++	/*
++	 *	2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.
++	 */
++	((PADAPTER)adapter)->HalFunc.GetHwRegHandler((PADAPTER)adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state));
++	if (((PADAPTER)adapter)->bDriverStopped || ((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) {
++		RF_DBG(dm, DBG_RF_INIT,
++		       "check_pow_status Return false, due to %d/%d/%d\n",
++		       ((PADAPTER)adapter)->bDriverStopped,
++		       ((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep,
++		       rt_state);
++		return false;
++	}
++#endif
++	return true;
++}
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++void halrf_update_pwr_track(void *dm_void, u8 rate)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	u8 path_idx = 0;
++#endif
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Pwr Track Get rate=0x%x\n", rate);
++
++	dm->tx_rate = rate;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++#if USE_WORKITEM
++	odm_schedule_work_item(&dm->ra_rpt_workitem);
++#else
++	if (dm->support_ic_type == ODM_RTL8821) {
++#if (RTL8821A_SUPPORT == 1)
++		odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);
++#endif
++	} else if (dm->support_ic_type == ODM_RTL8812) {
++		for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8812A; path_idx++) {
++#if (RTL8812A_SUPPORT == 1)
++			odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, path_idx, 0);
++#endif
++		}
++	} else if (dm->support_ic_type == ODM_RTL8723B) {
++#if (RTL8723B_SUPPORT == 1)
++		odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);
++#endif
++	} else if (dm->support_ic_type == ODM_RTL8192E) {
++		for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8192E; path_idx++) {
++#if (RTL8192E_SUPPORT == 1)
++			odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, path_idx, 0);
++#endif
++		}
++	} else if (dm->support_ic_type == ODM_RTL8188E) {
++#if (RTL8188E_SUPPORT == 1)
++		odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);
++#endif
++	}
++#endif
++#else
++	odm_schedule_work_item(&dm->ra_rpt_workitem);
++#endif
++#endif
++}
++
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void halrf_update_init_rate_work_item_callback(
++	void *context)
++{
++	void *adapter = (void *)context;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++	u8 p = 0;
++
++	if (dm->support_ic_type == ODM_RTL8821) {
++#if (RTL8821A_SUPPORT == 1)
++		odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);
++#endif
++	} else if (dm->support_ic_type == ODM_RTL8812) {
++#if (RTL8812A_SUPPORT == 1)
++		/*Don't know how to include &c*/
++		for (p = RF_PATH_A; p < MAX_PATH_NUM_8812A; p++)
++			odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, p, 0);
++#endif
++	} else if (dm->support_ic_type == ODM_RTL8723B) {
++#if (RTL8723B_SUPPORT == 1)
++		odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);
++#endif
++	} else if (dm->support_ic_type == ODM_RTL8192E) {
++#if (RTL8192E_SUPPORT == 1)
++		/*Don't know how to include &c*/
++		for (p = RF_PATH_A; p < MAX_PATH_NUM_8192E; p++)
++			odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, p, 0);
++#endif
++	} else if (dm->support_ic_type == ODM_RTL8188E) {
++#if (RTL8188E_SUPPORT == 1)
++		odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);
++#endif
++	}
++}
++#endif
++
++void halrf_set_pwr_track(void *dm_void, u8 enable)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
++	struct _hal_rf_ *rf = &(dm->rf_table);
++	struct txpwrtrack_cfg c;
++	u8 i;
++
++	configure_txpower_track(dm, &c);
++	if (enable) {
++		rf->rf_supportability = rf->rf_supportability | HAL_RF_TX_PWR_TRACK;
++		if (cali_info->txpowertrack_control == 1 || cali_info->txpowertrack_control == 3)
++			halrf_do_tssi(dm);
++	} else {
++		rf->rf_supportability = rf->rf_supportability & ~HAL_RF_TX_PWR_TRACK;
++		odm_clear_txpowertracking_state(dm);
++		halrf_do_tssi(dm);
++		halrf_calculate_tssi_codeword(dm);
++		halrf_set_tssi_codeword(dm);
++		for (i = 0; i < c.rf_path_count; i++)
++			(*c.odm_tx_pwr_track_set_pwr)(dm, CLEAN_MODE, i, 0);
++	}
++
++	if (cali_info->txpowertrack_control == 2 ||
++		cali_info->txpowertrack_control == 3 ||
++		cali_info->txpowertrack_control == 4 ||
++		cali_info->txpowertrack_control == 5)
++		halrf_txgapk_reload_tx_gain(dm);
++}
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking.h
+new file mode 100644
+index 000000000..c81f25225
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking.h
+@@ -0,0 +1,43 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_POWER_TRACKING_H__
++#define __HALRF_POWER_TRACKING_H__
++
++boolean
++odm_check_power_status(void *dm_void);
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++void halrf_update_pwr_track(void *dm_void, u8 rate);
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void halrf_update_init_rate_work_item_callback(
++	void *context);
++#endif
++
++void halrf_set_pwr_track(void *dm_void, u8 enable);
++
++#endif /*#ifndef __HALRF_POWERTRACKING_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_ap.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_ap.c
+new file mode 100644
+index 000000000..bf331b1a7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_ap.c
+@@ -0,0 +1,1252 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/* ************************************************************
++ * include files
++ * ************************************************************ */
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#if !defined(_OUTSRC_COEXIST)
++/* ************************************************************
++ * Global var
++ * ************************************************************ */
++
++
++u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D] = {
++	0x0b40002d, /* 0,  -15.0dB */
++	0x0c000030, /* 1,  -14.5dB */
++	0x0cc00033, /* 2,  -14.0dB */
++	0x0d800036, /* 3,  -13.5dB */
++	0x0e400039, /* 4,  -13.0dB */
++	0x0f00003c, /* 5,  -12.5dB */
++	0x10000040, /* 6,  -12.0dB */
++	0x11000044, /* 7,  -11.5dB */
++	0x12000048, /* 8,  -11.0dB */
++	0x1300004c, /* 9,  -10.5dB */
++	0x14400051, /* 10, -10.0dB */
++	0x15800056, /* 11, -9.5dB */
++	0x16c0005b, /* 12, -9.0dB */
++	0x18000060, /* 13, -8.5dB */
++	0x19800066, /* 14, -8.0dB */
++	0x1b00006c, /* 15, -7.5dB */
++	0x1c800072, /* 16, -7.0dB */
++	0x1e400079, /* 17, -6.5dB */
++	0x20000080, /* 18, -6.0dB */
++	0x22000088, /* 19, -5.5dB */
++	0x24000090, /* 20, -5.0dB */
++	0x26000098, /* 21, -4.5dB */
++	0x288000a2, /* 22, -4.0dB */
++	0x2ac000ab, /* 23, -3.5dB */
++	0x2d4000b5, /* 24, -3.0dB */
++	0x300000c0, /* 25, -2.5dB */
++	0x32c000cb, /* 26, -2.0dB */
++	0x35c000d7, /* 27, -1.5dB */
++	0x390000e4, /* 28, -1.0dB */
++	0x3c8000f2, /* 29, -0.5dB */
++	0x40000100, /* 30, +0dB */
++	0x43c0010f, /* 31, +0.5dB */
++	0x47c0011f, /* 32, +1.0dB */
++	0x4c000130, /* 33, +1.5dB */
++	0x50800142, /* 34, +2.0dB */
++	0x55400155, /* 35, +2.5dB */
++	0x5a400169, /* 36, +3.0dB */
++	0x5fc0017f, /* 37, +3.5dB */
++	0x65400195, /* 38, +4.0dB */
++	0x6b8001ae, /* 39, +4.5dB */
++	0x71c001c7, /* 40, +5.0dB */
++	0x788001e2, /* 41, +5.5dB */
++	0x7f8001fe  /* 42, +6.0dB */
++};
++
++u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
++	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},	/* 0, -16.0dB */
++	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 1, -15.5dB */
++	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 2, -15.0dB */
++	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 3, -14.5dB */
++	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 4, -14.0dB */
++	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 5, -13.5dB */
++	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 6, -13.0dB */
++	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 7, -12.5dB */
++	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 8, -12.0dB */
++	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 9, -11.5dB */
++	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 10, -11.0dB */
++	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 11, -10.5dB */
++	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 12, -10.0dB */
++	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 13, -9.5dB */
++	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 14, -9.0dB */
++	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 15, -8.5dB */
++	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
++	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 17, -7.5dB */
++	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 18, -7.0dB */
++	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 19, -6.5dB */
++	{0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02},	/* 20, -6.0dB */
++	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 21, -5.5dB */
++	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 22, -5.0dB */
++	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 23, -4.5dB */
++	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 24, -4.0dB */
++	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 25, -3.5dB */
++	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 26, -3.0dB */
++	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 27, -2.5dB */
++	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 28, -2.0dB */
++	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 29, -1.5dB */
++	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 30, -1.0dB */
++	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 31, -0.5dB */
++	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}	/* 32, +0dB */
++};
++
++
++u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
++	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},	/* 0, -16.0dB */
++	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 1, -15.5dB */
++	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 2, -15.0dB */
++	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 3, -14.5dB */
++	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 4, -14.0dB */
++	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 5, -13.5dB */
++	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 6, -13.0dB */
++	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 7, -12.5dB */
++	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 8, -12.0dB */
++	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 9, -11.5dB */
++	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 10, -11.0dB */
++	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 11, -10.5dB */
++	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 12, -10.0dB */
++	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 13, -9.5dB */
++	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 14, -9.0dB */
++	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 15, -8.5dB */
++	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
++	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 17, -7.5dB */
++	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 18, -7.0dB */
++	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 19, -6.5dB */
++	{0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 20, -6.0dB */
++	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 21, -5.5dB */
++	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 22, -5.0dB */
++	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 23, -4.5dB */
++	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 24, -4.0dB */
++	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 25, -3.5dB */
++	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 26, -3.0dB */
++	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 27, -2.5dB */
++	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 28, -2.0dB */
++	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 29, -1.5dB */
++	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 30, -1.0dB */
++	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 31, -0.5dB */
++	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}	/* 32, +0dB */
++};
++
++u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D] = {
++	0x0b40002d, /* 0,  -15.0dB */
++	0x0c000030, /* 1,  -14.5dB */
++	0x0cc00033, /* 2,  -14.0dB */
++	0x0d800036, /* 3,  -13.5dB */
++	0x0e400039, /* 4,  -13.0dB */
++	0x0f00003c, /* 5,  -12.5dB */
++	0x10000040, /* 6,  -12.0dB */
++	0x11000044, /* 7,  -11.5dB */
++	0x12000048, /* 8,  -11.0dB */
++	0x1300004c, /* 9,  -10.5dB */
++	0x14400051, /* 10, -10.0dB */
++	0x15800056, /* 11, -9.5dB */
++	0x16c0005b, /* 12, -9.0dB */
++	0x18000060, /* 13, -8.5dB */
++	0x19800066, /* 14, -8.0dB */
++	0x1b00006c, /* 15, -7.5dB */
++	0x1c800072, /* 16, -7.0dB */
++	0x1e400079, /* 17, -6.5dB */
++	0x20000080, /* 18, -6.0dB */
++	0x22000088, /* 19, -5.5dB */
++	0x24000090, /* 20, -5.0dB */
++	0x26000098, /* 21, -4.5dB */
++	0x288000a2, /* 22, -4.0dB */
++	0x2ac000ab, /* 23, -3.5dB */
++	0x2d4000b5, /* 24, -3.0dB */
++	0x300000c0, /* 25, -2.5dB */
++	0x32c000cb, /* 26, -2.0dB */
++	0x35c000d7, /* 27, -1.5dB */
++	0x390000e4, /* 28, -1.0dB */
++	0x3c8000f2, /* 29, -0.5dB */
++	0x40000100, /* 30, +0dB */
++	0x43c0010f, /* 31, +0.5dB */
++	0x47c0011f, /* 32, +1.0dB */
++	0x4c000130, /* 33, +1.5dB */
++	0x50800142, /* 34, +2.0dB */
++	0x55400155, /* 35, +2.5dB */
++	0x5a400169, /* 36, +3.0dB */
++	0x5fc0017f, /* 37, +3.5dB */
++	0x65400195, /* 38, +4.0dB */
++	0x6b8001ae, /* 39, +4.5dB */
++	0x71c001c7, /* 40, +5.0dB */
++	0x788001e2, /* 41, +5.5dB */
++	0x7f8001fe  /* 42, +6.0dB */
++};
++
++
++u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
++	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},	/* 0, -16.0dB */
++	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 1, -15.5dB */
++	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 2, -15.0dB */
++	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 3, -14.5dB */
++	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 4, -14.0dB */
++	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 5, -13.5dB */
++	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 6, -13.0dB */
++	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 7, -12.5dB */
++	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 8, -12.0dB */
++	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 9, -11.5dB */
++	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 10, -11.0dB */
++	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 11, -10.5dB */
++	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 12, -10.0dB */
++	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 13, -9.5dB */
++	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 14, -9.0dB */
++	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 15, -8.5dB */
++	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
++	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 17, -7.5dB */
++	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 18, -7.0dB */
++	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 19, -6.5dB */
++	{0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02},	/* 20, -6.0dB */
++	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 21, -5.5dB */
++	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 22, -5.0dB */
++	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 23, -4.5dB */
++	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 24, -4.0dB */
++	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 25, -3.5dB */
++	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 26, -3.0dB */
++	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 27, -2.5dB */
++	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 28, -2.0dB */
++	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 29, -1.5dB */
++	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 30, -1.0dB */
++	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 31, -0.5dB */
++	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}	/* 32, +0dB */
++};
++
++
++u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
++	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},	/* 0, -16.0dB */
++	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 1, -15.5dB */
++	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 2, -15.0dB */
++	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 3, -14.5dB */
++	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 4, -14.0dB */
++	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 5, -13.5dB */
++	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 6, -13.0dB */
++	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 7, -12.5dB */
++	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 8, -12.0dB */
++	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 9, -11.5dB */
++	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 10, -11.0dB */
++	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 11, -10.5dB */
++	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 12, -10.0dB */
++	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 13, -9.5dB */
++	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 14, -9.0dB */
++	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 15, -8.5dB */
++	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
++	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 17, -7.5dB */
++	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 18, -7.0dB */
++	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 19, -6.5dB */
++	{0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 20, -6.0dB */
++	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 21, -5.5dB */
++	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 22, -5.0dB */
++	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 23, -4.5dB */
++	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 24, -4.0dB */
++	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 25, -3.5dB */
++	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 26, -3.0dB */
++	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 27, -2.5dB */
++	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 28, -2.0dB */
++	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 29, -1.5dB */
++	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 30, -1.0dB */
++	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 31, -0.5dB */
++	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}	/* 32, +0dB */
++};
++
++u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
++	{0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 0  -16dB */
++	{0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 1  -15.5dB */
++	{0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 2  -15dB */
++	{0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 3  -14.5dB */
++	{0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 4  -14dB */
++	{0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 5  -13.5dB */
++	{0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 6  -13dB */
++	{0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 7  -12.5dB */
++	{0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 8  -12dB */
++	{0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 9  -11.5dB */
++	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 10  -11dB */
++	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 11  -10.5dB */
++	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 12  -10dB */
++	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 13  -9.5dB */
++	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 14  -9dB */
++	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 15  -8.5dB */
++	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 16  -8dB */
++	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 17  -7.5dB */
++	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 18  -7dB */
++	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 19  -6.5dB */
++	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}      /* 20  -6dB */
++};
++
++
++u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
++	{0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 0  -16dB */
++	{0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 1  -15.5dB */
++	{0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 2  -15dB */
++	{0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 3  -14.5dB */
++	{0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 4  -14dB */
++	{0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 5  -13.5dB */
++	{0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 6  -13dB */
++	{0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 7  -12.5dB */
++	{0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 8  -12dB */
++	{0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 9  -11.5dB */
++	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 10  -11dB */
++	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 11  -10.5dB */
++	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 12  -10dB */
++	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 13  -9.5dB */
++	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 14  -9dB */
++	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 15  -8.5dB */
++	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 16  -8dB */
++	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 17  -7.5dB */
++	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 18  -7dB */
++	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 19  -6.5dB */
++	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}      /* 20  -6dB */
++};
++
++
++u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
++	{0x44,	 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
++	{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
++	{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
++	{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	    /*-14.5dB*/
++	{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
++	{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
++	{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
++	{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
++	{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
++	{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
++	{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
++	{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
++	{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
++	{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
++	{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
++	{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
++	{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
++	{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
++	{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
++	{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
++	{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
++};
++
++/* Winnita ADD 20171113 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/
++u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
++	0x0CD,			 /*0 ,    -20dB*/
++	0x0D9,
++	0x0E6,
++	0x0F3,
++	0x102,
++	0x111,
++	0x121,
++	0x132,
++	0x144,
++	0x158,
++	0x16C,
++	0x182,
++	0x198,
++	0x1B1,
++	0x1CA,
++	0x1E5,
++	0x202,
++	0x221,
++	0x241,
++	0x263,		/*19*/
++	0x287,		/*20*/
++	0x2AE,		/*21*/
++	0x2D6,		/*22*/
++	0x301,		/*23*/
++	0x32F,		/*24*/
++	0x35F,		/*25*/
++	0x392,		/*26*/
++	0x3C9,		/*27*/
++	0x402,		/*28*/
++	0x43F,		/*29*/
++	0x47F,		/*30*/
++	0x4C3,		/*31*/
++	0x50C,		/*32*/
++	0x558,		/*33*/
++	0x5A9,		/*34*/
++	0x5FF,		/*35*/
++	0x65A,		/*36*/
++	0x6BA,
++	0x720,
++	0x78C,
++	0x7FF,
++};
++
++
++#if 0
++u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E] = {
++	/* Index0   6  dB */ 0x7fc001ff,
++	/* Index1   5.7dB */ 0x7b4001ed,
++	/* Index2   5.4dB */ 0x774001dd,
++	/* Index3   5.1dB */ 0x734001cd,
++	/* Index4   4.8dB */ 0x6f4001bd,
++	/* Index5   4.5dB */ 0x6b8001ae,
++	/* Index6   4.2dB */ 0x67c0019f,
++	/* Index7   3.9dB */ 0x64400191,
++	/* Index8   3.6dB */ 0x60c00183,
++	/* Index9   3.3dB */ 0x5d800176,
++	/* Index10  3  dB */ 0x5a80016a,
++	/* Index11  2.7dB */ 0x5740015d,
++	/* Index12  2.4dB */ 0x54400151,
++	/* Index13  2.1dB */ 0x51800146,
++	/* Index14  1.8dB */ 0x4ec0013b,
++	/* Index15  1.5dB */ 0x4c000130,
++	/* Index16  1.2dB */ 0x49800126,
++	/* Index17  0.9dB */ 0x4700011c,
++	/* Index18  0.6dB */ 0x44800112,
++	/* Index19  0.3dB */ 0x42000108,
++	/* Index20  0  dB */ 0x40000100, /* 20 This is OFDM base index */
++	/* Index21 -0.3dB */ 0x3dc000f7,
++	/* Index22 -0.6dB */ 0x3bc000ef,
++	/* Index23 -0.9dB */ 0x39c000e7,
++	/* Index24 -1.2dB */ 0x37c000df,
++	/* Index25 -1.5dB */ 0x35c000d7,
++	/* Index26 -1.8dB */ 0x340000d0,
++	/* Index27 -2.1dB */ 0x324000c9,
++	/* Index28 -2.4dB */ 0x308000c2,
++	/* Index29 -2.7dB */ 0x2f0000bc,
++	/* Index30 -3  dB */ 0x2d4000b5,
++	/* Index31 -3.3dB */ 0x2bc000af,
++	/* Index32 -3.6dB */ 0x2a4000a9,
++	/* Index33 -3.9dB */ 0x28c000a3,
++	/* Index34 -4.2dB */ 0x2780009e,
++	/* Index35 -4.5dB */ 0x26000098,
++	/* Index36 -4.8dB */ 0x24c00093,
++	/* Index37 -5.1dB */ 0x2380008e,
++	/* Index38 -5.4dB */ 0x22400089,
++	/* Index39 -5.7dB */ 0x21400085,
++	/* Index40 -6  dB */ 0x20000080,
++	/* Index41 -6.3dB */ 0x1f00007c,
++	/* Index42 -6.6dB */ 0x1e000078,
++	/* Index43 -6.9dB */ 0x1d000074,
++	/* Index44 -7.2dB */ 0x1c000070,
++	/* Index45 -7.5dB */ 0x1b00006c,
++	/* Index46 -7.8dB */ 0x1a000068,
++	/* Index47 -8.1dB */ 0x19400065,
++	/* Index48 -8.4dB */ 0x18400061,
++	/* Index49 -8.7dB */ 0x1780005e,
++	/* Index50 -9  dB */ 0x16c0005b,
++	/* Index51 -9.3dB */ 0x16000058,
++	/* Index52 -9.6dB */ 0x15400055,
++	/* Index53 -9.9dB */ 0x14800052
++};
++u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8] = {
++	/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x1C, 0x12, 0x08, 0x04},
++	/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x1B, 0x11, 0x08, 0x04},
++	/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x1A, 0x11, 0x07, 0x04},
++	/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x19, 0x10, 0x07, 0x04},
++	/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x18, 0x10, 0x07, 0x03},
++	/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x18, 0x0F, 0x07, 0x03},
++	/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x17, 0x0F, 0x06, 0x03},
++	/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x16, 0x0E, 0x06, 0x03},
++	/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x15, 0x0E, 0x06, 0x03},
++	/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x14, 0x0D, 0x06, 0x03},
++	/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x14, 0x0D, 0x06, 0x03},
++	/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x13, 0x0C, 0x05, 0x03},
++	/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x12, 0x0C, 0x05, 0x03},
++	/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x12, 0x0B, 0x05, 0x03},
++	/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x11, 0x0B, 0x05, 0x02},
++	/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x11, 0x0B, 0x05, 0x02},
++	/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x10, 0x0A, 0x05, 0x02},
++	/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x10, 0x0A, 0x04, 0x02},
++	/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x0F, 0x0A, 0x04, 0x02},
++	/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x0E, 0x09, 0x04, 0x02},
++	/* Index20  -6.0dB */    {0x1B, 0x1A, 0x17, 0x13, 0x0E, 0x09, 0x04, 0x02}, /* 20 This is CCK base index */
++	/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x0E, 0x09, 0x04, 0x02},
++	/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x0D, 0x08, 0x04, 0x02},
++	/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x0D, 0x08, 0x04, 0x02},
++	/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x0C, 0x08, 0x03, 0x02},
++	/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x0C, 0x08, 0x03, 0x02},
++	/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x0B, 0x07, 0x03, 0x02},
++	/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x0B, 0x07, 0x03, 0x02},
++	/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x0B, 0x07, 0x03, 0x02},
++	/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x0A, 0x07, 0x03, 0x01},
++	/* Index30  -9.0dB */    {0x13, 0x12, 0x10, 0x0D, 0x0A, 0x06, 0x03, 0x01}, /* 30 This is hp CCK base index */
++	/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x0A, 0x06, 0x03, 0x01},
++	/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x09, 0x06, 0x03, 0x01},
++	/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x09, 0x06, 0x03, 0x01},
++	/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x09, 0x06, 0x02, 0x01},
++	/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x08, 0x05, 0x02, 0x01},
++	/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x08, 0x05, 0x02, 0x01},
++	/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x08, 0x05, 0x02, 0x01},
++	/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
++	/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
++	/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
++	/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
++	/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
++	/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x06, 0x04, 0x02, 0x01},
++	/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
++	/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
++	/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
++	/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x06, 0x04, 0x02, 0x01},
++	/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
++	/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
++	/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
++	/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
++	/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
++	/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
++};
++u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = {
++	/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x00, 0x00, 0x00, 0x00},
++	/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x00, 0x00, 0x00, 0x00},
++	/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x00, 0x00, 0x00, 0x00},
++	/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x00, 0x00, 0x00, 0x00},
++	/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x00, 0x00, 0x00, 0x00},
++	/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x00, 0x00, 0x00, 0x00},
++	/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x00, 0x00, 0x00, 0x00},
++	/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x00, 0x00, 0x00, 0x00},
++	/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x00, 0x00, 0x00, 0x00},
++	/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x00, 0x00, 0x00, 0x00},
++	/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x00, 0x00, 0x00, 0x00},
++	/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x00, 0x00, 0x00, 0x00},
++	/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x00, 0x00, 0x00, 0x00},
++	/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x00, 0x00, 0x00, 0x00},
++	/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x00},
++	/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x00, 0x00, 0x00, 0x00},
++	/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x00, 0x00, 0x00, 0x00},
++	/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x00, 0x00, 0x00, 0x00},
++	/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x00, 0x00, 0x00, 0x00},
++	/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x00, 0x00, 0x00, 0x00},
++	/* Index20  -6  dB */     {0x1B, 0x1A, 0x17, 0x13, 0x00, 0x00, 0x00, 0x00},
++	/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00},
++	/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x00, 0x00, 0x00, 0x00},
++	/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x00, 0x00, 0x00, 0x00},
++	/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x00, 0x00, 0x00, 0x00},
++	/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x00, 0x00, 0x00, 0x00},
++	/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x00, 0x00, 0x00, 0x00},
++	/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x00, 0x00, 0x00, 0x00},
++	/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
++	/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
++	/* Index30  -9  dB */    {0x13, 0x12, 0x10, 0x0D, 0x00, 0x00, 0x00, 0x00},
++	/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
++	/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
++	/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x00, 0x00, 0x00, 0x00},
++	/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00},
++	/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x00, 0x00, 0x00, 0x00},
++	/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x00, 0x00, 0x00, 0x00},
++	/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x00, 0x00, 0x00, 0x00},
++	/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
++	/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
++	/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
++	/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
++	/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
++	/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x00, 0x00, 0x00, 0x00},
++	/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
++	/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
++	/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x00, 0x00, 0x00, 0x00},
++	/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
++	/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
++	/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
++	/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
++	/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
++	/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
++	/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00}
++};
++#endif
++#endif
++
++
++u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3
++	, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9
++							      };
++u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4
++	, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11
++							      };
++
++
++#ifdef CONFIG_WLAN_HAL_8192EE
++u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E] = {
++	/* Index0   6  dB */ 0x7fc001ff,
++	/* Index1   5.7dB */ 0x7b4001ed,
++	/* Index2   5.4dB */ 0x774001dd,
++	/* Index3   5.1dB */ 0x734001cd,
++	/* Index4   4.8dB */ 0x6f4001bd,
++	/* Index5   4.5dB */ 0x6b8001ae,
++	/* Index6   4.2dB */ 0x67c0019f,
++	/* Index7   3.9dB */ 0x64400191,
++	/* Index8   3.6dB */ 0x60c00183,
++	/* Index9   3.3dB */ 0x5d800176,
++	/* Index10  3  dB */ 0x5a80016a,
++	/* Index11  2.7dB */ 0x5740015d,
++	/* Index12  2.4dB */ 0x54400151,
++	/* Index13  2.1dB */ 0x51800146,
++	/* Index14  1.8dB */ 0x4ec0013b,
++	/* Index15  1.5dB */ 0x4c000130,
++	/* Index16  1.2dB */ 0x49800126,
++	/* Index17  0.9dB */ 0x4700011c,
++	/* Index18  0.6dB */ 0x44800112,
++	/* Index19  0.3dB */ 0x42000108,
++	/* Index20  0  dB */ 0x40000100, /* 20 This is OFDM base index */
++	/* Index21 -0.3dB */ 0x3dc000f7,
++	/* Index22 -0.6dB */ 0x3bc000ef,
++	/* Index23 -0.9dB */ 0x39c000e7,
++	/* Index24 -1.2dB */ 0x37c000df,
++	/* Index25 -1.5dB */ 0x35c000d7,
++	/* Index26 -1.8dB */ 0x340000d0,
++	/* Index27 -2.1dB */ 0x324000c9,
++	/* Index28 -2.4dB */ 0x308000c2,
++	/* Index29 -2.7dB */ 0x2f0000bc,
++	/* Index30 -3  dB */ 0x2d4000b5,
++	/* Index31 -3.3dB */ 0x2bc000af,
++	/* Index32 -3.6dB */ 0x2a4000a9,
++	/* Index33 -3.9dB */ 0x28c000a3,
++	/* Index34 -4.2dB */ 0x2780009e,
++	/* Index35 -4.5dB */ 0x26000098,
++	/* Index36 -4.8dB */ 0x24c00093,
++	/* Index37 -5.1dB */ 0x2380008e,
++	/* Index38 -5.4dB */ 0x22400089,
++	/* Index39 -5.7dB */ 0x21400085,
++	/* Index40 -6  dB */ 0x20000080,
++	/* Index41 -6.3dB */ 0x1f00007c,
++	/* Index42 -6.6dB */ 0x1e000078,
++	/* Index43 -6.9dB */ 0x1d000074,
++	/* Index44 -7.2dB */ 0x1c000070,
++	/* Index45 -7.5dB */ 0x1b00006c,
++	/* Index46 -7.8dB */ 0x1a000068,
++	/* Index47 -8.1dB */ 0x19400065,
++	/* Index48 -8.4dB */ 0x18400061,
++	/* Index49 -8.7dB */ 0x1780005e,
++	/* Index50 -9  dB */ 0x16c0005b,
++	/* Index51 -9.3dB */ 0x16000058,
++	/* Index52 -9.6dB */ 0x15400055,
++	/* Index53 -9.9dB */ 0x14800052
++};
++u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8] = {
++	/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x1C, 0x12, 0x08, 0x04},
++	/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x1B, 0x11, 0x08, 0x04},
++	/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x1A, 0x11, 0x07, 0x04},
++	/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x19, 0x10, 0x07, 0x04},
++	/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x18, 0x10, 0x07, 0x03},
++	/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x18, 0x0F, 0x07, 0x03},
++	/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x17, 0x0F, 0x06, 0x03},
++	/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x16, 0x0E, 0x06, 0x03},
++	/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x15, 0x0E, 0x06, 0x03},
++	/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x14, 0x0D, 0x06, 0x03},
++	/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x14, 0x0D, 0x06, 0x03},
++	/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x13, 0x0C, 0x05, 0x03},
++	/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x12, 0x0C, 0x05, 0x03},
++	/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x12, 0x0B, 0x05, 0x03},
++	/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x11, 0x0B, 0x05, 0x02},
++	/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x11, 0x0B, 0x05, 0x02},
++	/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x10, 0x0A, 0x05, 0x02},
++	/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x10, 0x0A, 0x04, 0x02},
++	/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x0F, 0x0A, 0x04, 0x02},
++	/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x0E, 0x09, 0x04, 0x02},
++	/* Index20  -6.0dB */    {0x1B, 0x1A, 0x17, 0x13, 0x0E, 0x09, 0x04, 0x02}, /* 20 This is CCK base index */
++	/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x0E, 0x09, 0x04, 0x02},
++	/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x0D, 0x08, 0x04, 0x02},
++	/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x0D, 0x08, 0x04, 0x02},
++	/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x0C, 0x08, 0x03, 0x02},
++	/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x0C, 0x08, 0x03, 0x02},
++	/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x0B, 0x07, 0x03, 0x02},
++	/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x0B, 0x07, 0x03, 0x02},
++	/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x0B, 0x07, 0x03, 0x02},
++	/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x0A, 0x07, 0x03, 0x01},
++	/* Index30  -9.0dB */    {0x13, 0x12, 0x10, 0x0D, 0x0A, 0x06, 0x03, 0x01}, /* 30 This is hp CCK base index */
++	/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x0A, 0x06, 0x03, 0x01},
++	/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x09, 0x06, 0x03, 0x01},
++	/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x09, 0x06, 0x03, 0x01},
++	/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x09, 0x06, 0x02, 0x01},
++	/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x08, 0x05, 0x02, 0x01},
++	/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x08, 0x05, 0x02, 0x01},
++	/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x08, 0x05, 0x02, 0x01},
++	/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
++	/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
++	/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
++	/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
++	/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
++	/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x06, 0x04, 0x02, 0x01},
++	/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
++	/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
++	/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
++	/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x06, 0x04, 0x02, 0x01},
++	/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
++	/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
++	/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
++	/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
++	/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
++	/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
++};
++u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = {
++	/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x00, 0x00, 0x00, 0x00},
++	/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x00, 0x00, 0x00, 0x00},
++	/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x00, 0x00, 0x00, 0x00},
++	/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x00, 0x00, 0x00, 0x00},
++	/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x00, 0x00, 0x00, 0x00},
++	/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x00, 0x00, 0x00, 0x00},
++	/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x00, 0x00, 0x00, 0x00},
++	/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x00, 0x00, 0x00, 0x00},
++	/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x00, 0x00, 0x00, 0x00},
++	/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x00, 0x00, 0x00, 0x00},
++	/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x00, 0x00, 0x00, 0x00},
++	/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x00, 0x00, 0x00, 0x00},
++	/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x00, 0x00, 0x00, 0x00},
++	/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x00, 0x00, 0x00, 0x00},
++	/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x00},
++	/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x00, 0x00, 0x00, 0x00},
++	/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x00, 0x00, 0x00, 0x00},
++	/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x00, 0x00, 0x00, 0x00},
++	/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x00, 0x00, 0x00, 0x00},
++	/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x00, 0x00, 0x00, 0x00},
++	/* Index20  -6  dB */     {0x1B, 0x1A, 0x17, 0x13, 0x00, 0x00, 0x00, 0x00},
++	/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00},
++	/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x00, 0x00, 0x00, 0x00},
++	/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x00, 0x00, 0x00, 0x00},
++	/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x00, 0x00, 0x00, 0x00},
++	/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x00, 0x00, 0x00, 0x00},
++	/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x00, 0x00, 0x00, 0x00},
++	/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x00, 0x00, 0x00, 0x00},
++	/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
++	/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
++	/* Index30  -9  dB */    {0x13, 0x12, 0x10, 0x0D, 0x00, 0x00, 0x00, 0x00},
++	/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
++	/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
++	/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x00, 0x00, 0x00, 0x00},
++	/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00},
++	/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x00, 0x00, 0x00, 0x00},
++	/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x00, 0x00, 0x00, 0x00},
++	/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x00, 0x00, 0x00, 0x00},
++	/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
++	/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
++	/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
++	/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
++	/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
++	/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x00, 0x00, 0x00, 0x00},
++	/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
++	/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
++	/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x00, 0x00, 0x00, 0x00},
++	/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
++	/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
++	/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
++	/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
++	/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
++	/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
++	/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00}
++};
++#endif
++
++#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
++	RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
++	RTL8814B_SUPPORT == 1)
++u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
++	0x081, /* 0,  -12.0dB */
++	0x088, /* 1,  -11.5dB */
++	0x090, /* 2,  -11.0dB */
++	0x099, /* 3,  -10.5dB */
++	0x0A2, /* 4,  -10.0dB */
++	0x0AC, /* 5,  -9.5dB */
++	0x0B6, /* 6,  -9.0dB */
++	0x0C0, /* 7,  -8.5dB */
++	0x0CC, /* 8,  -8.0dB */
++	0x0D8, /* 9,  -7.5dB */
++	0x0E5, /* 10, -7.0dB */
++	0x0F2, /* 11, -6.5dB */
++	0x101, /* 12, -6.0dB */
++	0x110, /* 13, -5.5dB */
++	0x120, /* 14, -5.0dB */
++	0x131, /* 15, -4.5dB */
++	0x143, /* 16, -4.0dB */
++	0x156, /* 17, -3.5dB */
++	0x16A, /* 18, -3.0dB */
++	0x180, /* 19, -2.5dB */
++	0x197, /* 20, -2.0dB */
++	0x1AF, /* 21, -1.5dB */
++	0x1C8, /* 22, -1.0dB */
++	0x1E3, /* 23, -0.5dB */
++	0x200, /* 24, +0  dB */
++	0x21E, /* 25, +0.5dB */
++	0x23E, /* 26, +1.0dB */
++	0x261, /* 27, +1.5dB */
++	0x285, /* 28, +2.0dB */
++	0x2AB, /* 29, +2.5dB */
++	0x2D3, /* 30, +3.0dB */
++	0x2FE, /* 31, +3.5dB */
++	0x32B, /* 32, +4.0dB */
++	0x35C, /* 33, +4.5dB */
++	0x38E, /* 34, +5.0dB */
++	0x3C4, /* 35, +5.5dB */
++	0x3FE  /* 36, +6.0dB */
++};
++#elif(ODM_IC_11AC_SERIES_SUPPORT)
++u32 ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812] = {
++	0x3FE, /* 0,  (6dB) */
++	0x3C4, /* 1,  (5.5dB) */
++	0x38E, /* 2,  (5dB) */
++	0x35C, /* 3,  (4.5dB) */
++	0x32B, /* 4,  (4dB) */
++	0x2FE, /* 5,  (3.5dB) */
++	0x2D3, /* 6,  (3dB) */
++	0x2AB, /* 7,  (2.5dB) */
++	0x285, /* 8,  (2dB) */
++	0x261, /* 9,  (1.5dB */
++	0x23E, /* 10, (1dB) */
++	0x21E, /* 11, (0.5dB) */
++	0x200, /* 12, (0dB)		8814 int PA 2G default */
++	0x1E3, /* 13, (-0.5dB) */
++	0x1C8, /* 14, (-1dB) */
++	0x1AF, /* 15, (-1.5dB) */
++	0x197, /* 16, (-2dB) */
++	0x180, /* 17, (-2.5dB) */
++	0x16A, /* 18, (-3dB)		8812 / 8814 int PA 5G / 8814 ext PA 2G5G default */
++	0x156, /* 19, (-3.5dB) */
++	0x143, /* 20, (-4dB)		8812 HP default */
++	0x131, /* 21, (-4.5dB) */
++	0x120, /* 22, (-5dB) */
++	0x110, /* 23, (-5.5dB) */
++	0x101, /* 24, (-6dB) */
++	0x0F2, /* 25, (-6.5dB) */
++	0x0E5, /* 26, (-7dB) */
++	0x0D8, /* 27, (-7.5dB) */
++	0x0CC, /* 28, (-8dB) */
++	0x0C0, /* 29, (-8.5dB) */
++	0x0B6, /* 30, (-9dB) */
++	0x0AC, /* 31, (-9.5dB) */
++	0x0A2, /* 32, (-10dB) */
++	0x099, /* 33, (-10.5dB) */
++	0x090, /* 34, (-11dB) */
++	0x088, /* 35, (-11.5dB) */
++	0x081, /* 36, (-12dB) */
++	0x079, /* 37, (-12.5dB) */
++	0x072, /* 38, (-13dB) */
++	0x06c, /* 39, (-13.5dB) */
++	0x066, /* 40, (-14dB) */
++	0x060, /* 41, (-14.5dB) */
++	0x05B  /* 42, (-15dB) */
++};
++#endif
++
++u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
++	0x0CD,
++	0x0D9,
++	0x0E6,
++	0x0F3,
++	0x102,
++	0x111,
++	0x121,
++	0x132,
++	0x144,
++	0x158,
++	0x16C,
++	0x182,
++	0x198,
++	0x1B1,
++	0x1CA,
++	0x1E5,
++	0x202,
++	0x221,
++	0x241,
++	0x263,
++	0x287,
++	0x2AE,
++	0x2D6,
++	0x301,
++	0x32F,
++	0x35F,
++	0x392,
++	0x3C9,
++	0x402,
++	0x43F,
++	0x47F,
++	0x4C3,
++	0x50C,
++	0x558,
++	0x5A9,
++	0x5FF,
++	0x65A,
++	0x6BA,
++	0x720,
++	0x78C,
++	0x7FF,
++};
++/* JJ ADD 20161014 */
++u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
++	0x0CD,
++	0x0D9,
++	0x0E6,
++	0x0F3,
++	0x102,
++	0x111,
++	0x121,
++	0x132,
++	0x144,
++	0x158,
++	0x16C,
++	0x182,
++	0x198,
++	0x1B1,
++	0x1CA,
++	0x1E5,
++	0x202,
++	0x221,
++	0x241,
++	0x263,
++	0x287,
++	0x2AE,
++	0x2D6,
++	0x301,
++	0x32F,
++	0x35F,
++	0x392,
++	0x3C9,
++	0x402,
++	0x43F,
++	0x47F,
++	0x4C3,
++	0x50C,
++	0x558,
++	0x5A9,
++	0x5FF,
++	0x65A,
++	0x6BA,
++	0x720,
++	0x78C,
++	0x7FF,
++};
++
++
++/* #endif */
++/* 3============================================================
++ * 3 Tx Power Tracking
++ * 3============================================================ */
++
++void
++odm_txpowertracking_init(
++	void		*dm_void
++)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_IC_11N_SERIES)))
++		return;
++#endif
++
++	odm_txpowertracking_thermal_meter_init(dm);
++}
++
++
++u8
++get_swing_index(
++	void		*dm_void
++)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	u8			i = 0, bb_swing_mask = 0;
++	u32			bb_swing = 0;
++	u32			swing_table_size = 0;
++	u32			*swing_table = 0;
++	struct rtl8192cd_priv	*priv = dm->priv;
++
++#if (RTL8197F_SUPPORT == 1)
++	if (GET_CHIP_VER(priv) == VERSION_8197F) {
++		bb_swing = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D);
++		swing_table = ofdm_swing_table_new;
++		swing_table_size = OFDM_TABLE_SIZE_92D;
++		bb_swing_mask = 22;
++	}
++#endif
++
++#if (RTL8192F_SUPPORT == 1)
++	if (GET_CHIP_VER(priv) == VERSION_8192F) {
++		bb_swing = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D);
++		swing_table = ofdm_swing_table_new;
++		swing_table_size = OFDM_TABLE_SIZE_92D;
++		bb_swing_mask = 22;
++	}
++#endif
++
++#if (RTL8822B_SUPPORT == 1)
++	if (GET_CHIP_VER(priv) == VERSION_8822B) {
++		bb_swing = phy_query_bb_reg(priv, REG_A_TX_SCALE_JAGUAR, 0xFFE00000);
++		swing_table = tx_scaling_table_jaguar;
++		swing_table_size = TXSCALE_TABLE_SIZE;
++		bb_swing_mask = 0;
++	}
++#endif
++
++	for (i = 0; i < swing_table_size - 1; i++) {
++		u32 table_value = swing_table[i] >> bb_swing_mask;
++
++		if (bb_swing == table_value)
++			break;
++	}
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "bb_swing=0x%x bbswing_index=%d\n", bb_swing, i);
++
++
++	return i;
++}
++
++
++void
++odm_txpowertracking_thermal_meter_init(
++	void		*dm_void
++)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
++	struct rtl8192cd_priv		*priv = dm->priv;
++	u8 p;
++	u8 default_swing_index;
++#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1)
++	if ((GET_CHIP_VER(priv) == VERSION_8197F) || (GET_CHIP_VER(priv) == VERSION_8822B) ||(GET_CHIP_VER(priv) == VERSION_8192F))
++		default_swing_index = get_swing_index(dm);
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void		*adapter = dm->adapter;
++	PMGNT_INFO	mgnt_info = &adapter->MgntInfo;
++	HAL_DATA_TYPE		*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++
++	mgnt_info->is_txpowertracking = true;
++	hal_data->tx_powercount       = 0;
++	hal_data->is_txpowertracking_init = false;
++
++	if (*(dm->mp_mode) == false)
++		hal_data->txpowertrack_control = true;
++	RF_DBG(dm, COMP_POWER_TRACKING, "mgnt_info->is_txpowertracking = %d\n", mgnt_info->is_txpowertracking);
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++#ifdef CONFIG_RTL8188E
++	{
++		dm->rf_calibrate_info.is_txpowertracking = true;
++		dm->rf_calibrate_info.tx_powercount = 0;
++		dm->rf_calibrate_info.is_txpowertracking_init = false;
++
++		if (*(dm->mp_mode) == false)
++			dm->rf_calibrate_info.txpowertrack_control = true;
++
++		MSG_8192C("dm txpowertrack_control = %d\n", dm->rf_calibrate_info.txpowertrack_control);
++	}
++#else
++	{
++		void		*adapter = dm->adapter;
++		HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++		struct dm_priv	*pdmpriv = &hal_data->dmpriv;
++		
++		pdmpriv->is_txpowertracking = true;
++		pdmpriv->tx_powercount = 0;
++		pdmpriv->is_txpowertracking_init = false;
++
++		if (*(dm->mp_mode) == false)		/* for mp driver, turn off txpwrtracking as default */
++			pdmpriv->txpowertrack_control = true;
++
++		MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control);
++
++	}
++#endif/* endif (CONFIG_RTL8188E==1) */
++#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++
++#ifdef RTL8188E_SUPPORT
++	{
++		dm->rf_calibrate_info.is_txpowertracking = true;
++		dm->rf_calibrate_info.tx_powercount = 0;
++		dm->rf_calibrate_info.is_txpowertracking_init = false;
++		dm->rf_calibrate_info.txpowertrack_control = true;
++		dm->rf_calibrate_info.tm_trigger = 0;
++	}
++#endif
++#endif
++
++	dm->rf_calibrate_info.txpowertrack_control = true;
++	dm->rf_calibrate_info.delta_power_index = 0;
++	dm->rf_calibrate_info.delta_power_index_last = 0;
++	dm->rf_calibrate_info.power_index_offset = 0;
++	dm->rf_calibrate_info.thermal_value = 0;
++	cali_info->default_ofdm_index = 28;
++
++#if (RTL8197F_SUPPORT == 1)
++	if (GET_CHIP_VER(priv) == VERSION_8197F) {
++		cali_info->default_ofdm_index = (default_swing_index >= (OFDM_TABLE_SIZE_92D - 1)) ? 30 : default_swing_index;
++		cali_info->default_cck_index = 28;
++	}
++#endif
++
++#if (RTL8192F_SUPPORT == 1)
++	if (GET_CHIP_VER(priv) == VERSION_8192F) {
++		cali_info->default_ofdm_index = (default_swing_index >= (OFDM_TABLE_SIZE_92D - 1)) ? 30 : default_swing_index;
++		cali_info->default_cck_index = 28;
++	}
++#endif
++
++#if (RTL8822B_SUPPORT == 1)
++	if (GET_CHIP_VER(priv) == VERSION_8822B) {
++		cali_info->default_ofdm_index = (default_swing_index >= (TXSCALE_TABLE_SIZE - 1)) ? 24 : default_swing_index;
++		cali_info->default_cck_index = 20;
++	}
++#endif
++
++
++#if RTL8188E_SUPPORT
++	cali_info->default_cck_index = 20;	/* -6 dB */
++#elif RTL8192E_SUPPORT
++	cali_info->default_cck_index = 8;	/* -12 dB */
++#endif
++	cali_info->bb_swing_idx_ofdm_base = cali_info->default_ofdm_index;
++	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
++	dm->rf_calibrate_info.CCK_index = cali_info->default_cck_index;
++
++	for (p = 0; p < MAX_RF_PATH; p++) {
++		dm->rf_calibrate_info.OFDM_index[p] = cali_info->default_ofdm_index;
++		cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
++		cali_info->kfree_offset[p] = 0;	/* for 8814 kfree*/
++	}
++	cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "cali_info->default_ofdm_index=%d cali_info->default_cck_index=%d\n", cali_info->default_ofdm_index, cali_info->default_cck_index);
++
++	cali_info->tm_trigger = 0;
++}
++
++
++void
++odm_txpowertracking_check(
++	void		*dm_void
++)
++{
++	/*  */
++	/* For AP/ADSL use struct rtl8192cd_priv* */
++	/* For CE/NIC use struct void* */
++	/*  */
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_				*rf = &(dm->rf_table);
++
++	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
++		return;
++
++	/*  */
++	/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
++	/* at the same time. In the stage2/3, we need to prive universal interface and merge all */
++	/* HW dynamic mechanism. */
++	/*  */
++	switch	(dm->support_platform) {
++	case	ODM_WIN:
++		odm_txpowertracking_check_mp(dm);
++		break;
++
++	case	ODM_CE:
++		odm_txpowertracking_check_ce(dm);
++		break;
++
++	case	ODM_AP:
++		odm_txpowertracking_check_ap(dm);
++		break;
++	}
++
++}
++
++void
++odm_txpowertracking_check_ce(
++	void		*dm_void
++)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	void	*adapter = dm->adapter;
++	struct _hal_rf_				*rf = &(dm->rf_table);
++
++#if (RTL8188E_SUPPORT == 1)
++
++	/* if(!mgnt_info->is_txpowertracking || (!pdmpriv->txpowertrack_control && pdmpriv->is_ap_kdone)) */
++
++	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
++		return;
++
++	if (!dm->rf_calibrate_info.tm_trigger) {	/* at least delay 1 sec */
++		/* hal_data->TxPowerCheckCnt++;	 */ /* cosa add for debug */
++		odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
++		/* DBG_8192C("Trigger 92C Thermal Meter!!\n"); */
++
++		dm->rf_calibrate_info.tm_trigger = 1;
++		return;
++
++	} else {
++		/* DBG_8192C("Schedule TxPowerTracking direct call!!\n"); */
++		odm_txpowertracking_callback_thermal_meter_8188e(adapter);
++		dm->rf_calibrate_info.tm_trigger = 0;
++	}
++#endif
++
++#endif
++}
++
++void
++odm_txpowertracking_check_mp(
++	void		*dm_void
++)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	void	*adapter = dm->adapter;
++
++	if (odm_check_power_status(adapter) == false)
++		return;
++
++	if (!adapter->is_slave_of_dmsp || adapter->dual_mac_smart_concurrent == false)
++		odm_txpowertracking_thermal_meter_check(adapter);
++#endif
++
++}
++
++
++void
++odm_txpowertracking_check_ap(
++	void		*dm_void
++)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
++
++#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1) || (RTL8198F_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8812F_SUPPORT == 1) || (RTL8197G_SUPPORT == 1))
++	if (!dm->rf_calibrate_info.tm_trigger) {
++		if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8192F | ODM_RTL8198F)) {
++			odm_set_rf_reg(dm, RF_PATH_A, 0x42, (BIT(17) | BIT(16)), 0x3);
++		} else if (dm->support_ic_type & ODM_RTL8812F) {
++			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
++			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);
++			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
++			
++			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
++			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);
++			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
++		} else if (dm->support_ic_type & ODM_RTL8814B) {
++			odm_set_rf_reg(dm, RF_PATH_A, 0x42, BIT(17), 0x1);
++			odm_set_rf_reg(dm, RF_PATH_B, 0x42, BIT(17), 0x1);
++			odm_set_rf_reg(dm, RF_PATH_C, 0x42, BIT(17), 0x1);
++			odm_set_rf_reg(dm, RF_PATH_D, 0x42, BIT(17), 0x1);
++		} else if (dm->support_ic_type & ODM_RTL8197G) {
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x42, BIT(17), 0x1);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x42, BIT(17), 0x0);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x42, BIT(17), 0x1);
++
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0x42, BIT(17), 0x1);
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0x42, BIT(17), 0x0);
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0x42, BIT(17), 0x1);
++		}
++
++		if (dm->support_ic_type & ODM_RTL8814B) {
++			ODM_delay_us(300);
++			odm_txpowertracking_callback_thermal_meter(dm);
++			tssi->thermal_trigger = 1;
++		}
++
++		dm->rf_calibrate_info.tm_trigger = 1;
++	} else {
++		odm_txpowertracking_callback_thermal_meter(dm);
++		if (dm->support_ic_type & ODM_RTL8814B)
++			tssi->thermal_trigger = 0;
++		dm->rf_calibrate_info.tm_trigger = 0;
++	}
++#endif
++
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_ap.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_ap.h
+new file mode 100644
+index 000000000..dfeb3233b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_ap.h
+@@ -0,0 +1,406 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_POWERTRACKING_H__
++#define __HALRF_POWERTRACKING_H__
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	#ifdef RTK_AC_SUPPORT
++		#define ODM_IC_11AC_SERIES_SUPPORT		1
++	#else
++		#define ODM_IC_11AC_SERIES_SUPPORT		0
++	#endif
++#else
++	#define ODM_IC_11AC_SERIES_SUPPORT		1
++#endif
++
++#define		DPK_DELTA_MAPPING_NUM	13
++#define		index_mapping_HP_NUM	15
++#define		DELTA_SWINGIDX_SIZE     30
++#define		DELTA_SWINTSSI_SIZE     61
++#define		BAND_NUM				3
++#define		MAX_RF_PATH	4
++#define		TXSCALE_TABLE_SIZE		37
++#define		CCK_TABLE_SIZE_8723D		41
++/* JJ ADD 20161014 */
++#define		CCK_TABLE_SIZE_8710B		41
++
++#define IQK_MAC_REG_NUM		4
++#define IQK_ADDA_REG_NUM		16
++#define IQK_BB_REG_NUM_MAX	10
++
++#define IQK_BB_REG_NUM		9
++
++#define AVG_THERMAL_NUM		8
++#define AVG_THERMAL_NUM_DPK		8
++#define THERMAL_DPK_AVG_NUM		4
++
++#define iqk_matrix_reg_num	8
++/* #define IQK_MATRIX_SETTINGS_NUM	1+24+21 */
++#define IQK_MATRIX_SETTINGS_NUM	(14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
++
++#if !defined(_OUTSRC_COEXIST)
++	#define	OFDM_TABLE_SIZE_92D	43
++	#define	OFDM_TABLE_SIZE	37
++	#define	CCK_TABLE_SIZE		33
++	#define	CCK_TABLE_SIZE_88F	21
++	#define	CCK_TABLE_SIZE_8192F	41
++
++
++
++	/* #define	OFDM_TABLE_SIZE_92E	54 */
++	/* #define	CCK_TABLE_SIZE_92E	54 */
++	extern	u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D];
++	extern	u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
++	extern	u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
++
++
++	extern	u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D];
++	extern	u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
++	extern	u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
++	extern	u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
++	extern	u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
++	extern	u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
++	extern	u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
++
++#endif
++
++#define	ODM_OFDM_TABLE_SIZE	37
++#define	ODM_CCK_TABLE_SIZE		33
++#define TXPWR_TRACK_TABLE_SIZE 30
++/* <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
++extern u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE];
++extern u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE];
++
++static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};
++static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11};
++
++/* extern	u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];
++ * extern	u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];
++ * extern	u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8]; */
++
++#ifdef CONFIG_WLAN_HAL_8192EE
++	#define	OFDM_TABLE_SIZE_92E	54
++	#define	CCK_TABLE_SIZE_92E	54
++	extern	u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];
++	extern	u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];
++	extern	u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8];
++#endif
++
++#define	OFDM_TABLE_SIZE_8812	43
++#define	AVG_THERMAL_NUM_8812	4
++
++#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
++	RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
++	RTL8814B_SUPPORT == 1)
++	extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
++	#elif(ODM_IC_11AC_SERIES_SUPPORT)
++	extern unsigned int ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812];
++#endif
++
++extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
++/* JJ ADD 20161014 */
++extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
++
++#define dm_check_txpowertracking	odm_txpowertracking_check
++
++struct iqk_matrix_regs_setting {
++	boolean	is_iqk_done;
++	s32		value[1][iqk_matrix_reg_num];
++};
++
++struct dm_rf_calibration_struct {
++	/* for tx power tracking */
++
++	u32	rega24; /* for TempCCK */
++	s32	rege94;
++	s32	rege9c;
++	s32	regeb4;
++	s32	regebc;
++
++	/* u8 is_txpowertracking; */
++	u8	tx_powercount;
++	boolean is_txpowertracking_init;
++	boolean is_txpowertracking;
++	u8  	txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
++	u8	tm_trigger;
++	u8  	internal_pa_5g[2];	/* pathA / pathB */
++
++	u8  	thermal_meter[2];    /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
++	u8	thermal_value;
++	u8	thermal_value_path[MAX_RF_PATH];
++	u8	thermal_value_lck;
++	u8	thermal_value_iqk;
++	s8  	thermal_value_delta; /* delta of thermal_value and efuse thermal */
++	u8	thermal_value_avg[AVG_THERMAL_NUM];
++	u8	thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM];
++	u8	thermal_value_avg_index;
++	u8	thermal_value_avg_index_path[MAX_RF_PATH];
++	s8	power_index_offset_path[MAX_RF_PATH];
++
++	u8	thermal_value_rx_gain;
++	u8	thermal_value_crystal;
++	u8	thermal_value_dpk_store;
++	u8	thermal_value_dpk_track;
++	boolean	txpowertracking_in_progress;
++
++
++	boolean	is_reloadtxpowerindex;
++	u8	is_rf_pi_enable;
++	u32 	txpowertracking_callback_cnt; /* cosa add for debug */
++
++	u8	is_cck_in_ch14;
++	u8	CCK_index;
++	u8	OFDM_index[MAX_RF_PATH];
++	s8	power_index_offset;
++	s8	delta_power_index;
++	s8	delta_power_index_path[MAX_RF_PATH];
++	s8	delta_power_index_last;
++	s8	delta_power_index_last_path[MAX_RF_PATH];
++	boolean is_tx_power_changed;
++
++	struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
++	u8	delta_lck;
++	u8  delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
++	s8  delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
++	s8  delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
++
++	u8			bb_swing_idx_ofdm[MAX_RF_PATH];
++	u8			bb_swing_idx_ofdm_current;
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	u8			bb_swing_idx_ofdm_base[MAX_RF_PATH];
++#else
++	u8			bb_swing_idx_ofdm_base;
++	u8			bb_swing_idx_ofdm_base_path[MAX_RF_PATH];
++#endif
++	boolean			bb_swing_flag_ofdm;
++	u8			bb_swing_idx_cck;
++	u8			bb_swing_idx_cck_current;
++	u8			bb_swing_idx_cck_base;
++	u8			default_ofdm_index;
++	u8			default_cck_index;
++	boolean			bb_swing_flag_cck;
++
++	s8			absolute_ofdm_swing_idx[MAX_RF_PATH];
++	s8			remnant_ofdm_swing_idx[MAX_RF_PATH];
++	s8			absolute_cck_swing_idx[MAX_RF_PATH];
++	s8			remnant_cck_swing_idx;
++	s8			modify_tx_agc_value;       /*Remnat compensate value at tx_agc */
++	boolean			modify_tx_agc_flag_path_a;
++	boolean			modify_tx_agc_flag_path_b;
++	boolean			modify_tx_agc_flag_path_c;
++	boolean			modify_tx_agc_flag_path_d;
++	boolean			modify_tx_agc_flag_path_a_cck;
++	boolean			modify_tx_agc_flag_path_b_cck;
++
++	s8			kfree_offset[MAX_RF_PATH];
++
++	/* -------------------------------------------------------------------- */
++
++	/* for IQK */
++	u32	regc04;
++	u32	reg874;
++	u32	regc08;
++	u32	regb68;
++	u32	regb6c;
++	u32	reg870;
++	u32	reg860;
++	u32	reg864;
++
++	boolean	is_iqk_initialized;
++	boolean is_lck_in_progress;
++	boolean	is_antenna_detected;
++	boolean	is_need_iqk;
++	boolean	is_iqk_in_progress;
++	boolean	is_iqk_pa_off;
++	u8	delta_iqk;
++	u32	ADDA_backup[IQK_ADDA_REG_NUM];
++	u32	IQK_MAC_backup[IQK_MAC_REG_NUM];
++	u32	IQK_BB_backup_recover[9];
++	u32	IQK_BB_backup[IQK_BB_REG_NUM];
++	u32	tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
++	u32	rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */
++	u32	tx_iqc_8703b[3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
++	u32	rx_iqc_8703b[2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
++
++	u64	iqk_start_time;
++	u64	iqk_total_progressing_time;
++	u64	iqk_progressing_time;
++	u64	lck_progressing_time;
++	u32  lok_result;
++	u8	iqk_step;
++	u8	kcount;
++	u8	retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
++	boolean	is_mp_mode;
++
++	/* for APK */
++	u32 	ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
++	u8	is_ap_kdone;
++	u8	is_apk_thermal_meter_ignore;
++	u8	is_dp_done;
++#if 0 /*move below members to halrf_dpk.h*/
++	u8	is_dp_path_aok;
++	u8	is_dp_path_bok;
++	u8	is_dp_path_cok;
++	u8	is_dp_path_dok;
++	u8 	dp_path_a_result[3];
++	u8 	dp_path_b_result[3];
++	u8 	dp_path_c_result[3];
++	u8 	dp_path_d_result[3];
++	boolean	is_dpk_enable;
++	u32	txrate[11];
++	u8 	pwsf_2g_a[3];
++	u8 	pwsf_2g_b[3];
++	u8 	pwsf_2g_c[3];
++	u8 	pwsf_2g_d[3];
++	u32	lut_2g_even_a[3][64];
++	u32	lut_2g_odd_a[3][64];
++	u32	lut_2g_even_b[3][64];
++	u32	lut_2g_odd_b[3][64];
++	u32	lut_2g_even_c[3][64];
++	u32	lut_2g_odd_c[3][64];
++	u32	lut_2g_even_d[3][64];
++	u32	lut_2g_odd_d[3][64];
++	u1Byte 	is_5g_pdk_a_ok;
++	u1Byte 	is_5g_pdk_b_ok;
++	u1Byte 	is_5g_pdk_c_ok;
++	u1Byte 	is_5g_pdk_d_ok;
++	u1Byte 	pwsf_5g_a[9];
++	u1Byte 	pwsf_5g_b[9];
++	u1Byte 	pwsf_5g_c[9];
++	u1Byte 	pwsf_5g_d[9];
++	u4Byte	lut_5g_even_a[9][16];
++	u4Byte	lut_5g_odd_a[9][16];
++	u4Byte	lut_5g_even_b[9][16];
++	u4Byte	lut_5g_odd_b[9][16];
++	u4Byte	lut_5g_even_c[9][16];
++	u4Byte	lut_5g_odd_c[9][16];
++	u4Byte	lut_5g_even_d[9][16];
++	u4Byte	lut_5g_odd_d[9][16];
++	u8	thermal_value_dpk;
++	u8	thermal_value_dpk_avg[AVG_THERMAL_NUM_DPK];
++	u8	thermal_value_dpk_avg_index;
++#endif
++	s8  modify_tx_agc_value_ofdm;
++	s8  modify_tx_agc_value_cck;
++
++	/*Add by Yuchen for Kfree Phydm*/
++	u8			reg_rf_kfree_enable;	/*for registry*/
++	u8			rf_kfree_enable;		/*for efuse enable check*/
++	u32	tx_lok[2];
++};
++
++void
++odm_txpowertracking_check_ap(
++	void		*dm_void
++);
++
++void
++odm_txpowertracking_check(
++	void		*dm_void
++);
++
++
++void
++odm_txpowertracking_thermal_meter_init(
++	void		*dm_void
++);
++
++void
++odm_txpowertracking_init(
++	void		*dm_void
++);
++
++void
++odm_txpowertracking_check_mp(
++	void		*dm_void
++);
++
++
++void
++odm_txpowertracking_check_ce(
++	void		*dm_void
++);
++
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++
++void
++odm_txpowertracking_callback_thermal_meter92c(
++	void	*adapter
++);
++
++void
++odm_txpowertracking_callback_rx_gain_thermal_meter92d(
++	void	*adapter
++);
++
++void
++odm_txpowertracking_callback_thermal_meter92d(
++	void	*adapter
++);
++
++void
++odm_txpowertracking_direct_call92c(
++	void		*adapter
++);
++
++void
++odm_txpowertracking_thermal_meter_check(
++	void		*adapter
++);
++
++#endif
++
++
++
++#endif	/*#ifndef __HALRF_POWER_TRACKING_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_ce.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_ce.c
+new file mode 100644
+index 000000000..1ae098bff
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_ce.c
+@@ -0,0 +1,936 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@===========================================================
++ * include files
++ *============================================================
++ */
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++/*@************************************************************
++ * Global var
++ * ************************************************************
++ */
++
++u32 ofdm_swing_table[OFDM_TABLE_SIZE] = {
++	0x7f8001fe, /* 0, +6.0dB */
++	0x788001e2, /* 1, +5.5dB */
++	0x71c001c7, /* 2, +5.0dB*/
++	0x6b8001ae, /* 3, +4.5dB*/
++	0x65400195, /* 4, +4.0dB*/
++	0x5fc0017f, /* 5, +3.5dB*/
++	0x5a400169, /* 6, +3.0dB*/
++	0x55400155, /* 7, +2.5dB*/
++	0x50800142, /* 8, +2.0dB*/
++	0x4c000130, /* 9, +1.5dB*/
++	0x47c0011f, /* 10, +1.0dB*/
++	0x43c0010f, /* 11, +0.5dB*/
++	0x40000100, /* 12, +0dB*/
++	0x3c8000f2, /* 13, -0.5dB*/
++	0x390000e4, /* 14, -1.0dB*/
++	0x35c000d7, /* 15, -1.5dB*/
++	0x32c000cb, /* 16, -2.0dB*/
++	0x300000c0, /* 17, -2.5dB*/
++	0x2d4000b5, /* 18, -3.0dB*/
++	0x2ac000ab, /* 19, -3.5dB*/
++	0x288000a2, /* 20, -4.0dB*/
++	0x26000098, /* 21, -4.5dB*/
++	0x24000090, /* 22, -5.0dB*/
++	0x22000088, /* 23, -5.5dB*/
++	0x20000080, /* 24, -6.0dB*/
++	0x1e400079, /* 25, -6.5dB*/
++	0x1c800072, /* 26, -7.0dB*/
++	0x1b00006c, /* 27. -7.5dB*/
++	0x19800066, /* 28, -8.0dB*/
++	0x18000060, /* 29, -8.5dB*/
++	0x16c0005b, /* 30, -9.0dB*/
++	0x15800056, /* 31, -9.5dB*/
++	0x14400051, /* 32, -10.0dB*/
++	0x1300004c, /* 33, -10.5dB*/
++	0x12000048, /* 34, -11.0dB*/
++	0x11000044, /* 35, -11.5dB*/
++	0x10000040, /* 36, -12.0dB*/
++};
++
++u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
++	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
++	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
++	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
++	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
++	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
++	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
++	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
++	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
++	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
++	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
++	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
++	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
++	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0 default*/
++	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
++	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
++	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
++	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
++	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
++	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
++	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
++	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
++	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
++	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
++	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
++	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
++	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
++	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
++	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
++	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
++	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
++	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
++	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
++	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
++};
++
++u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
++	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
++	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
++	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
++	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
++	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
++	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
++	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
++	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
++	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
++	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
++	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
++	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
++	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0 default*/
++	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
++	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
++	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
++	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
++	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
++	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
++	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
++	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
++	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
++	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
++	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
++	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
++	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
++	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
++	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
++	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
++	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
++	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
++	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
++	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
++};
++
++u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
++	0x0b40002d, /* 0,  -15.0dB */
++	0x0c000030, /* 1,  -14.5dB */
++	0x0cc00033, /* 2,  -14.0dB */
++	0x0d800036, /* 3,  -13.5dB */
++	0x0e400039, /* 4,  -13.0dB */
++	0x0f00003c, /* 5,  -12.5dB */
++	0x10000040, /* 6,  -12.0dB */
++	0x11000044, /* 7,  -11.5dB */
++	0x12000048, /* 8,  -11.0dB */
++	0x1300004c, /* 9,  -10.5dB */
++	0x14400051, /* 10, -10.0dB */
++	0x15800056, /* 11, -9.5dB */
++	0x16c0005b, /* 12, -9.0dB */
++	0x18000060, /* 13, -8.5dB */
++	0x19800066, /* 14, -8.0dB */
++	0x1b00006c, /* 15, -7.5dB */
++	0x1c800072, /* 16, -7.0dB */
++	0x1e400079, /* 17, -6.5dB */
++	0x20000080, /* 18, -6.0dB */
++	0x22000088, /* 19, -5.5dB */
++	0x24000090, /* 20, -5.0dB */
++	0x26000098, /* 21, -4.5dB */
++	0x288000a2, /* 22, -4.0dB */
++	0x2ac000ab, /* 23, -3.5dB */
++	0x2d4000b5, /* 24, -3.0dB */
++	0x300000c0, /* 25, -2.5dB */
++	0x32c000cb, /* 26, -2.0dB */
++	0x35c000d7, /* 27, -1.5dB */
++	0x390000e4, /* 28, -1.0dB */
++	0x3c8000f2, /* 29, -0.5dB */
++	0x40000100, /* 30, +0dB */
++	0x43c0010f, /* 31, +0.5dB */
++	0x47c0011f, /* 32, +1.0dB */
++	0x4c000130, /* 33, +1.5dB */
++	0x50800142, /* 34, +2.0dB */
++	0x55400155, /* 35, +2.5dB */
++	0x5a400169, /* 36, +3.0dB */
++	0x5fc0017f, /* 37, +3.5dB */
++	0x65400195, /* 38, +4.0dB */
++	0x6b8001ae, /* 39, +4.5dB */
++	0x71c001c7, /* 40, +5.0dB */
++	0x788001e2, /* 41, +5.5dB */
++	0x7f8001fe /* 42, +6.0dB */
++};
++
++u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
++	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
++	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
++	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
++	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
++	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
++	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
++	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
++	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
++	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
++	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
++	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
++	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
++	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
++	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
++	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
++	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
++	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
++	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
++	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
++	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
++	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
++};
++
++u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
++	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
++	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
++	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
++	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
++	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
++	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
++	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
++	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
++	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
++	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
++	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
++	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
++	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
++	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
++	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
++	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
++	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
++	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
++	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
++	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
++	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
++};
++
++u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
++	{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
++	{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
++	{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
++	{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
++	{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
++	{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
++	{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
++	{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
++	{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
++	{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
++	{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
++	{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
++	{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
++	{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
++	{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
++	{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
++	{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
++	{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
++	{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
++	{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
++	{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++		0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
++};
++
++u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
++	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /*   0, -16.0dB*/
++	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /*   1, -15.5dB*/
++	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /*   2, -15.0dB*/
++	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /*   3, -14.5dB*/
++	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /*   4, -14.0dB*/
++	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /*   5, -13.5dB*/
++	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /*   6, -13.0dB*/
++	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /*   7, -12.5dB*/
++	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /*   8, -12.0dB*/
++	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /*   9, -11.5dB*/
++	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  10, -11.0dB*/
++	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  11, -10.5dB*/
++	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  12, -10.0dB*/
++	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  13, -9.5dB*/
++	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /*  14, -9.0dB */
++	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /*  15, -8.5dB*/
++	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /*  16, -8.0dB */
++	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /*  17, -7.5dB*/
++	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /*  18, -7.0dB */
++	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /*  19, -6.5dB*/
++	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*  20, -6.0dB */
++	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /*  21, -5.5dB*/
++	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /*  22, -5.0dB */
++	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /*  23, -4.5dB*/
++	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /*  24, -4.0dB */
++	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /*  25, -3.5dB*/
++	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /*  26, -3.0dB*/
++	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /*  27, -2.5dB*/
++	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /*  28, -2.0dB */
++	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /*  29, -1.5dB*/
++	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /*  30, -1.0dB*/
++	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /*  31, -0.5dB*/
++	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /*   32, +0dB*/
++};
++
++u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
++	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /*  0, -16.0dB*/
++	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/
++	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  2, -15.0dB*/
++	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/
++	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  4, -14.0dB*/
++	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/
++	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/
++	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  7, -12.5dB*/
++	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/
++	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/
++	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/
++	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/
++	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/
++	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/
++	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */
++	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/
++	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
++	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/
++	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */
++	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */
++	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */
++	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/
++	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */
++	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/
++	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */
++	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */
++	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */
++	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/
++	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */
++	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/
++	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */
++	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */
++	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB	*/
++};
++
++u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
++	0x0CD, /*0 ,    -20dB*/
++	0x0D9,
++	0x0E6,
++	0x0F3,
++	0x102,
++	0x111,
++	0x121,
++	0x132,
++	0x144,
++	0x158,
++	0x16C,
++	0x182,
++	0x198,
++	0x1B1,
++	0x1CA,
++	0x1E5,
++	0x202,
++	0x221,
++	0x241,
++	0x263,
++	0x287,
++	0x2AE,
++	0x2D6,
++	0x301,
++	0x32F,
++	0x35F,
++	0x392,
++	0x3C9,
++	0x402,
++	0x43F,
++	0x47F,
++	0x4C3,
++	0x50C,
++	0x558,
++	0x5A9,
++	0x5FF,
++	0x65A,
++	0x6BA,
++	0x720,
++	0x78C,
++	0x7FF,
++};
++
++/*@JJ ADD 20161014 */
++u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
++	0x0CD, /*0 ,    -20dB*/
++	0x0D9,
++	0x0E6,
++	0x0F3,
++	0x102,
++	0x111,
++	0x121,
++	0x132,
++	0x144,
++	0x158,
++	0x16C,
++	0x182,
++	0x198,
++	0x1B1,
++	0x1CA,
++	0x1E5,
++	0x202,
++	0x221,
++	0x241,
++	0x263,
++	0x287,
++	0x2AE,
++	0x2D6,
++	0x301,
++	0x32F,
++	0x35F,
++	0x392,
++	0x3C9,
++	0x402,
++	0x43F,
++	0x47F,
++	0x4C3,
++	0x50C,
++	0x558,
++	0x5A9,
++	0x5FF,
++	0x65A,
++	0x6BA,
++	0x720,
++	0x78C,
++	0x7FF,
++};
++
++/*@Winnita ADD 20171116 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/
++u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
++	0x0CD, /*0 ,    -20dB*/
++	0x0D9,
++	0x0E6,
++	0x0F3,
++	0x102,
++	0x111,
++	0x121,
++	0x132,
++	0x144,
++	0x158,
++	0x16C,
++	0x182,
++	0x198,
++	0x1B1,
++	0x1CA,
++	0x1E5,
++	0x202,
++	0x221,
++	0x241,
++	0x263, /*19*/
++	0x287, /*20*/
++	0x2AE, /*21*/
++	0x2D6, /*22*/
++	0x301, /*23*/
++	0x32F, /*24*/
++	0x35F, /*25*/
++	0x392, /*26*/
++	0x3C9, /*27*/
++	0x402, /*28*/
++	0x43F, /*29*/
++	0x47F, /*30*/
++	0x4C3, /*31*/
++	0x50C, /*32*/
++	0x558, /*33*/
++	0x5A9, /*34*/
++	0x5FF, /*35*/
++	0x65A, /*36*/
++	0x6BA,
++	0x720,
++	0x78C,
++	0x7FF,
++};
++
++u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
++	0x081, /* 0,  -12.0dB*/
++	0x088, /* 1,  -11.5dB*/
++	0x090, /* 2,  -11.0dB*/
++	0x099, /* 3,  -10.5dB*/
++	0x0A2, /* 4,  -10.0dB*/
++	0x0AC, /* 5,  -9.5dB*/
++	0x0B6, /* 6,  -9.0dB*/
++	0x0C0, /*7,  -8.5dB*/
++	0x0CC, /* 8,  -8.0dB*/
++	0x0D8, /* 9,  -7.5dB*/
++	0x0E5, /* 10, -7.0dB*/
++	0x0F2, /* 11, -6.5dB*/
++	0x101, /* 12, -6.0dB*/
++	0x110, /* 13, -5.5dB*/
++	0x120, /* 14, -5.0dB*/
++	0x131, /* 15, -4.5dB*/
++	0x143, /* 16, -4.0dB*/
++	0x156, /* 17, -3.5dB*/
++	0x16A, /* 18, -3.0dB*/
++	0x180, /* 19, -2.5dB*/
++	0x197, /* 20, -2.0dB*/
++	0x1AF, /* 21, -1.5dB*/
++	0x1C8, /* 22, -1.0dB*/
++	0x1E3, /* 23, -0.5dB*/
++	0x200, /* 24, +0  dB*/
++	0x21E, /* 25, +0.5dB*/
++	0x23E, /* 26, +1.0dB*/
++	0x261, /* 27, +1.5dB*/
++	0x285, /* 28, +2.0dB*/
++	0x2AB, /* 29, +2.5dB*/
++	0x2D3, /*30, +3.0dB*/
++	0x2FE, /* 31, +3.5dB*/
++	0x32B, /* 32, +4.0dB*/
++	0x35C, /* 33, +4.5dB*/
++	0x38E, /* 34, +5.0dB*/
++	0x3C4, /* 35, +5.5dB*/
++	0x3FE /* 36, +6.0dB	*/
++};
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
++#else
++u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3,
++					  4, 4, 4, 4, 4, 4, 4, 4, 5, 5,
++					  7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
++u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4,
++					  4, 5, 5, 6, 6, 7, 7, 7, 7, 8,
++					  8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
++#endif
++
++void odm_txpowertracking_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	odm_txpowertracking_thermal_meter_init(dm);
++}
++
++u8 get_swing_index(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
++	void *adapter = dm->adapter;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++#endif
++	u8 i = 0;
++	u32 bb_swing, table_value;
++
++	if (dm->support_ic_type &
++		(ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |
++		ODM_RTL8188F | ODM_RTL8703B | ODM_RTL8723D |
++		ODM_RTL8710B)) {
++
++		bb_swing = odm_get_bb_reg(dm, R_0xc80, 0xFFC00000);
++
++		for (i = 0; i < OFDM_TABLE_SIZE; i++) {
++			table_value = ofdm_swing_table_new[i];
++
++			if (table_value >= 0x100000)
++				table_value >>= 22;
++			if (bb_swing == table_value)
++				break;
++		}
++	} else {
++#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
++		bb_swing =
++		phy_get_tx_bb_swing_8812a(adapter,
++					  hal_data->current_band_type,
++					  RF_PATH_A);
++#else
++		bb_swing = odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000);
++#endif
++		for (i = 0; i < TXSCALE_TABLE_SIZE; i++) {
++			table_value = tx_scaling_table_jaguar[i];
++
++			if (bb_swing == table_value)
++				break;
++		}
++	}
++
++	return i;
++}
++
++u8 get_cck_swing_index(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	u8 i = 0;
++	u32 bb_cck_swing;
++
++	if (dm->support_ic_type &
++		(ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E)) {
++		bb_cck_swing = odm_read_1byte(dm, 0xa22);
++
++		for (i = 0; i < CCK_TABLE_SIZE; i++) {
++			if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
++				break;
++		}
++	} else if (dm->support_ic_type & ODM_RTL8703B) {
++		bb_cck_swing = odm_read_1byte(dm, 0xa22);
++
++		for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
++			if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
++				break;
++		}
++	}
++
++	return i;
++}
++
++void odm_txpowertracking_thermal_meter_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
++
++	u8 swing_idx = get_swing_index(dm);
++	u8 cckswing_idx = get_cck_swing_index(dm);
++	u8 p = 0;
++
++	cali_info->is_txpowertracking = true;
++	cali_info->tx_powercount = 0;
++	cali_info->is_txpowertracking_init = false;
++
++	if (!(*dm->mp_mode))
++		cali_info->txpowertrack_control = true;
++	else
++		cali_info->txpowertrack_control = false;
++
++	if (!(*dm->mp_mode))
++		cali_info->txpowertrack_control = true;
++
++	RF_DBG(dm, DBG_RF_IQK, "dm txpowertrack_control = %d\n",
++	       cali_info->txpowertrack_control);
++#if 0
++	/* dm->rf_calibrate_info.txpowertrack_control = true; */
++#endif
++	cali_info->thermal_value = rf->eeprom_thermal;
++	cali_info->thermal_value_iqk = rf->eeprom_thermal;
++	cali_info->thermal_value_lck = rf->eeprom_thermal;
++
++#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8822C) {
++		cali_info->thermal_value_path[RF_PATH_A] = tssi->thermal[RF_PATH_A];
++		cali_info->thermal_value_path[RF_PATH_B] = tssi->thermal[RF_PATH_B];
++		cali_info->thermal_value_iqk = tssi->thermal[RF_PATH_A];
++		cali_info->thermal_value_lck = tssi->thermal[RF_PATH_A];
++	}
++	
++	if (dm->support_ic_type == ODM_RTL8814B) {
++		cali_info->thermal_value_path[RF_PATH_A] = tssi->thermal[RF_PATH_A];
++		cali_info->thermal_value_path[RF_PATH_B] = tssi->thermal[RF_PATH_B];
++		cali_info->thermal_value_path[RF_PATH_C] = tssi->thermal[RF_PATH_C];
++		cali_info->thermal_value_path[RF_PATH_D] = tssi->thermal[RF_PATH_D];
++		cali_info->thermal_value_iqk = tssi->thermal[RF_PATH_A];
++		cali_info->thermal_value_lck = tssi->thermal[RF_PATH_A];
++	}
++#endif
++
++	if (!cali_info->default_bb_swing_index_flag) {
++		if (dm->support_ic_type &
++			(ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |
++			ODM_RTL8703B | ODM_RTL8821)) {
++			if (swing_idx >= OFDM_TABLE_SIZE)
++				cali_info->default_ofdm_index = 30;
++			else
++				cali_info->default_ofdm_index = swing_idx;
++
++			if (cckswing_idx >= CCK_TABLE_SIZE)
++				cali_info->default_cck_index = 20;
++			else
++				cali_info->default_cck_index = cckswing_idx;
++		/*@add by Mingzhi.Guo  2015-03-23*/
++		} else if (dm->support_ic_type == ODM_RTL8188F) {
++			cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
++			cali_info->default_cck_index = 20; /*CCK:-6dB*/
++		/*@add by zhaohe  2015-10-27*/
++		} else if (dm->support_ic_type == ODM_RTL8723D) {
++			cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
++			cali_info->default_cck_index = 28; /*CCK:   -6dB*/
++		/*@JJ ADD 20161014 */
++		} else if (dm->support_ic_type == ODM_RTL8710B) {
++			cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
++			cali_info->default_cck_index = 28; /*CCK:   -6dB*/
++		} else if (dm->support_ic_type == ODM_RTL8192F) {
++			cali_info->default_ofdm_index = 30;/*OFDM: 0dB*/
++			cali_info->default_cck_index = 28; /*CCK:   -6dB*/
++		} else {
++			if (swing_idx >= TXSCALE_TABLE_SIZE)
++				cali_info->default_ofdm_index = 24;
++			else
++				cali_info->default_ofdm_index = swing_idx;
++
++			cali_info->default_cck_index = 24;
++		}
++		cali_info->default_bb_swing_index_flag = true;
++	}
++
++	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
++	cali_info->CCK_index = cali_info->default_cck_index;
++
++	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
++		cali_info->bb_swing_idx_ofdm_base[p] =
++						cali_info->default_ofdm_index;
++		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
++		cali_info->delta_power_index[p] = 0;
++		cali_info->delta_power_index_last[p] = 0;
++		cali_info->power_index_offset[p] = 0;
++	}
++	cali_info->modify_tx_agc_value_ofdm = 0;
++	cali_info->modify_tx_agc_value_cck = 0;
++	cali_info->tm_trigger = 0;
++}
++
++void odm_txpowertracking_check(void *dm_void)
++{
++	/*@2011/09/29 MH In HW integration first stage
++	 * we provide 4 different handle to operate at the same time.
++	 * In the stage2/3, we need to prive universal interface and merge all
++	 * HW dynamic mechanism.
++	 */
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	switch (dm->support_platform) {
++	case ODM_WIN:
++		odm_txpowertracking_check_mp(dm);
++		break;
++
++	case ODM_CE:
++		odm_txpowertracking_check_ce(dm);
++		break;
++
++	case ODM_AP:
++		odm_txpowertracking_check_ap(dm);
++		break;
++
++	default:
++		break;
++	}
++}
++
++void odm_txpowertracking_check_ce(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
++		return;
++
++	if ((rf->power_track_type & 0xf0) >> 4 != 0) {
++		if (dm->support_ic_type & ODM_RTL8822C) {
++			/*halrf_tssi_cck(dm);*/
++			/*halrf_thermal_cck(dm);*/
++			return;
++		}
++	}
++
++	if (!dm->rf_calibrate_info.tm_trigger) {
++		if (dm->support_ic_type &
++			(ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8192E |
++			ODM_RTL8723B | ODM_RTL8812 | ODM_RTL8821 |
++			ODM_RTL8814A | ODM_RTL8703B | ODM_RTL8723D |
++			ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8710B |
++			ODM_RTL8192F))
++			odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW,
++				       (BIT(17) | BIT(16)), 0x03);
++		else if (dm->support_ic_type & ODM_RTL8822C) {
++			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
++			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);
++			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
++			
++			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
++			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);
++			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
++		} else if (dm->support_ic_type & ODM_RTL8814B) {
++			odm_set_rf_reg(dm, RF_PATH_A, 0x42, BIT(17), 0x1);
++			odm_set_rf_reg(dm, RF_PATH_B, 0x42, BIT(17), 0x1);
++			odm_set_rf_reg(dm, RF_PATH_C, 0x42, BIT(17), 0x1);
++			odm_set_rf_reg(dm, RF_PATH_D, 0x42, BIT(17), 0x1);
++		} else
++			odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_OLD,
++				       RFREGOFFSETMASK, 0x60);
++
++#if (RTL8814B_SUPPORT == 1)
++		if (dm->support_ic_type & ODM_RTL8814B) {
++			ODM_delay_us(300);
++			odm_txpowertracking_new_callback_thermal_meter(dm);
++			tssi->thermal_trigger = 1;
++		}
++#endif
++		dm->rf_calibrate_info.tm_trigger = 1;
++		return;
++	}
++	
++	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B)) {
++#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
++		odm_txpowertracking_new_callback_thermal_meter(dm);
++		if (dm->support_ic_type & ODM_RTL8814B)
++			tssi->thermal_trigger = 0;
++#endif
++	} else
++		odm_txpowertracking_callback_thermal_meter(dm);
++	dm->rf_calibrate_info.tm_trigger = 0;
++#endif
++}
++
++void
++odm_txpowertracking_direct_ce(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &dm->rf_table;
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++
++	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
++		return;
++
++	if (dm->support_ic_type & ODM_RTL8822C) {
++		/*halrf_tssi_cck(dm);*/
++		/*halrf_thermal_cck(dm);*/
++		return;
++	}
++
++	if (dm->support_ic_type &
++		(ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8192E |
++		ODM_RTL8723B | ODM_RTL8812 | ODM_RTL8821 |
++		ODM_RTL8814A | ODM_RTL8703B | ODM_RTL8723D |
++		ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8710B |
++		ODM_RTL8192F | ODM_RTL8814B))
++		odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03);
++	else if (dm->support_ic_type & ODM_RTL8822C) {
++		odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
++		odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);
++		odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
++			
++		odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
++		odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);
++		odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
++	} else
++		odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_OLD, RFREGOFFSETMASK, 0x60);
++
++	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B)) {
++#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
++		odm_txpowertracking_new_callback_thermal_meter(dm);
++#endif
++	} else
++		odm_txpowertracking_callback_thermal_meter(dm);
++#endif
++
++}
++
++
++void odm_txpowertracking_check_mp(void *dm_void)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	void *adapter = dm->adapter;
++
++	if (odm_check_power_status(adapter) == false) {
++		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
++			 ("check_pow_status, return false\n"));
++		return;
++	}
++
++	odm_txpowertracking_thermal_meter_check(adapter);
++#endif
++}
++
++void odm_txpowertracking_check_ap(void *dm_void)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rtl8192cd_priv *priv = dm->priv;
++
++	return;
++
++#endif
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_ce.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_ce.h
+new file mode 100644
+index 000000000..2f3067acb
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_ce.h
+@@ -0,0 +1,330 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_POWERTRACKING_H__
++#define __HALRF_POWERTRACKING_H__
++
++#define DPK_DELTA_MAPPING_NUM 13
++#define index_mapping_HP_NUM 15
++#define OFDM_TABLE_SIZE 43
++#define CCK_TABLE_SIZE 33
++#define CCK_TABLE_SIZE_88F 21
++#define TXSCALE_TABLE_SIZE 37
++#define CCK_TABLE_SIZE_8723D 41
++/*@JJ ADD 20161014 */
++#define CCK_TABLE_SIZE_8710B 41
++#define CCK_TABLE_SIZE_8192F 41
++
++#define TXPWR_TRACK_TABLE_SIZE 30
++#define DELTA_SWINGIDX_SIZE 30
++#define DELTA_SWINTSSI_SIZE 61
++#define BAND_NUM 4
++
++#define AVG_THERMAL_NUM 8
++#define IQK_MAC_REG_NUM 4
++#define IQK_ADDA_REG_NUM 16
++#define IQK_BB_REG_NUM_MAX 10
++
++#define IQK_BB_REG_NUM 9
++
++#define iqk_matrix_reg_num 8
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
++#else
++/* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
++#define IQK_MATRIX_SETTINGS_NUM (14 + 24 + 21)
++#endif
++
++extern u32 ofdm_swing_table[OFDM_TABLE_SIZE];
++extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
++extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
++
++extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
++extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
++extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
++extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
++extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
++extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
++extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
++/*@JJ ADD 20161014 */
++extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
++extern u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
++
++extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
++
++/*@<20121018, Kordan> In case fail to read TxPowerTrack.txt */
++/* we use the table of 88E as the default table. */
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
++#else
++extern u8 delta_swing_table_idx_2ga_p_8188e[];
++extern u8 delta_swing_table_idx_2ga_n_8188e[];
++#endif
++
++#define dm_check_txpowertracking odm_txpowertracking_check
++
++struct iqk_matrix_regs_setting {
++	boolean is_iqk_done;
++	s32 value[3][iqk_matrix_reg_num];
++	boolean is_bw_iqk_result_saved[3];
++};
++
++struct dm_rf_calibration_struct {
++	/* for tx power tracking */
++
++	u32 rega24; /* for TempCCK */
++	s32 rege94;
++	s32 rege9c;
++	s32 regeb4;
++	s32 regebc;
++
++	u8 tx_powercount;
++	boolean is_txpowertracking_init;
++	boolean is_txpowertracking;
++	/* for mp mode, turn off txpwrtracking as default */
++	u8 txpowertrack_control;
++	u8 tm_trigger;
++	u8 internal_pa_5g[2]; /* pathA / pathB */
++
++	/* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
++	u8 thermal_meter[2];
++	u8 thermal_value;
++	u8 thermal_value_path[MAX_RF_PATH];
++	u8 thermal_value_lck;
++	u8 thermal_value_iqk;
++	s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
++	u8 thermal_value_dpk;
++	u8 thermal_value_avg[AVG_THERMAL_NUM];
++	u8 thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM];
++	u8 thermal_value_avg_index;
++	u8 thermal_value_avg_index_path[MAX_RF_PATH];
++	u8 thermal_value_rx_gain;
++	u8 thermal_value_crystal;
++	u8 thermal_value_dpk_store;
++	u8 thermal_value_dpk_track;
++	boolean txpowertracking_in_progress;
++
++	boolean is_reloadtxpowerindex;
++	u8 is_rf_pi_enable;
++	u32 txpowertracking_callback_cnt; /* cosa add for debug */
++
++	/*@---------------------- Tx power Tracking ---------------------- */
++	u8 is_cck_in_ch14;
++	u8 CCK_index;
++	u8 OFDM_index[MAX_RF_PATH];
++	s8 power_index_offset[MAX_RF_PATH];
++	s8 delta_power_index[MAX_RF_PATH];
++	s8 delta_power_index_last[MAX_RF_PATH];
++	boolean is_tx_power_changed;
++	s8 xtal_offset;
++	s8 xtal_offset_last;
++	u8 xtal_offset_eanble;
++
++	struct iqk_matrix_regs_setting
++				iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
++	u8 delta_lck;
++	s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
++	u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
++	u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
++	u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
++	u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
++	u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
++	u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
++	u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
++	u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
++	u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
++	u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
++	u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
++	u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
++	s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
++	s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
++	u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
++
++	u8 bb_swing_idx_ofdm[MAX_RF_PATH];
++	u8 bb_swing_idx_ofdm_current;
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
++#else
++	u8 bb_swing_idx_ofdm_base;
++#endif
++	boolean default_bb_swing_index_flag;
++	boolean bb_swing_flag_ofdm;
++	u8 bb_swing_idx_cck;
++	u8 bb_swing_idx_cck_current;
++	u8 bb_swing_idx_cck_base;
++	u8 default_ofdm_index;
++	u8 default_cck_index;
++	boolean bb_swing_flag_cck;
++
++	s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
++	s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
++	s8 absolute_cck_swing_idx[MAX_RF_PATH];
++	s8 remnant_cck_swing_idx;
++	s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
++	boolean modify_tx_agc_flag_path_a;
++	boolean modify_tx_agc_flag_path_b;
++	boolean modify_tx_agc_flag_path_c;
++	boolean modify_tx_agc_flag_path_d;
++	boolean modify_tx_agc_flag_path_a_cck;
++	boolean modify_tx_agc_flag_path_b_cck;
++
++	s8 kfree_offset[MAX_RF_PATH];
++
++	/*@----------------------------------------------------------------- */
++
++	/* for IQK */
++	u32 regc04;
++	u32 reg874;
++	u32 regc08;
++	u32 regb68;
++	u32 regb6c;
++	u32 reg870;
++	u32 reg860;
++	u32 reg864;
++
++	boolean is_iqk_initialized;
++	boolean is_lck_in_progress;
++	boolean is_antenna_detected;
++	boolean is_need_iqk;
++	boolean is_iqk_in_progress;
++	boolean is_iqk_pa_off;
++	u8 delta_iqk;
++	u32 ADDA_backup[IQK_ADDA_REG_NUM];
++	u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
++	u32 IQK_BB_backup_recover[9];
++	u32 IQK_BB_backup[IQK_BB_REG_NUM];
++	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
++	u32 tx_iqc_8723b[2][3][2];
++	/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
++	u32 rx_iqc_8723b[2][2][2];
++	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
++	u32 tx_iqc_8703b[3][2];
++	/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
++	u32 rx_iqc_8703b[2][2];
++	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
++	u32 tx_iqc_8723d[2][3][2];
++	/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
++	u32 rx_iqc_8723d[2][2][2];
++	/* JJ ADD 20161014 */
++	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
++	u32 tx_iqc_8710b[2][3][2];
++	/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
++	u32 rx_iqc_8710b[2][2][2];
++
++	u8 iqk_step;
++	u8 kcount;
++	u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
++	boolean is_mp_mode;
++
++	/*@<James> IQK time measurement */
++	u64 iqk_start_time;
++	u64 iqk_progressing_time;
++	u64 iqk_total_progressing_time;
++	u64 lck_progressing_time;
++
++	u32 lok_result;
++
++	/* for APK */
++	u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
++	u8 is_ap_kdone;
++	u8 is_apk_thermal_meter_ignore;
++
++	/* DPK */
++	boolean is_dpk_fail;
++	u8 is_dp_done;
++	u8 is_dp_path_aok;
++	u8 is_dp_path_bok;
++
++	u32 tx_lok[2];
++	u32 dpk_tx_agc;
++	s32 dpk_gain;
++	u32 dpk_thermal[4];
++	s8 modify_tx_agc_value_ofdm;
++	s8 modify_tx_agc_value_cck;
++
++	/*@Add by Yuchen for Kfree Phydm*/
++	u8 reg_rf_kfree_enable; /*for registry*/
++	u8 rf_kfree_enable; /*for efuse enable check*/
++};
++
++void odm_txpowertracking_check(void *dm_void);
++
++void odm_txpowertracking_init(void *dm_void);
++
++void odm_txpowertracking_check_ap(void *dm_void);
++
++void odm_txpowertracking_thermal_meter_init(void *dm_void);
++
++void odm_txpowertracking_init(void *dm_void);
++
++void odm_txpowertracking_check_mp(void *dm_void);
++
++void odm_txpowertracking_check_ce(void *dm_void);
++
++void odm_txpowertracking_direct_ce(void *dm_void);
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++
++void odm_txpowertracking_callback_thermal_meter92c(
++	void *adapter);
++
++void odm_txpowertracking_callback_rx_gain_thermal_meter92d(
++	void *adapter);
++
++void odm_txpowertracking_callback_thermal_meter92d(
++	void *adapter);
++
++void odm_txpowertracking_direct_call92c(
++	void *adapter);
++
++void odm_txpowertracking_thermal_meter_check(
++	void *adapter);
++
++#endif
++
++#endif /*__HALRF_POWER_TRACKING_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_iot.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_iot.c
+new file mode 100644
+index 000000000..dd6e02b3f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_iot.c
+@@ -0,0 +1,980 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*============================================================	*/
++/* include files												*/
++/*============================================================	*/
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++/* ************************************************************
++ * Global var
++ * ************************************************************
++ */
++
++u32	ofdm_swing_table[OFDM_TABLE_SIZE] = {
++	0x7f8001fe,	/* 0, +6.0dB */
++	0x788001e2,	/* 1, +5.5dB */
++	0x71c001c7,	/* 2, +5.0dB*/
++	0x6b8001ae,	/* 3, +4.5dB*/
++	0x65400195,	/* 4, +4.0dB*/
++	0x5fc0017f,	/* 5, +3.5dB*/
++	0x5a400169,	/* 6, +3.0dB*/
++	0x55400155,	/* 7, +2.5dB*/
++	0x50800142,	/* 8, +2.0dB*/
++	0x4c000130,	/* 9, +1.5dB*/
++	0x47c0011f,	/* 10, +1.0dB*/
++	0x43c0010f,	/* 11, +0.5dB*/
++	0x40000100,	/* 12, +0dB*/
++	0x3c8000f2,	/* 13, -0.5dB*/
++	0x390000e4,	/* 14, -1.0dB*/
++	0x35c000d7,	/* 15, -1.5dB*/
++	0x32c000cb,	/* 16, -2.0dB*/
++	0x300000c0,	/* 17, -2.5dB*/
++	0x2d4000b5,	/* 18, -3.0dB*/
++	0x2ac000ab,	/* 19, -3.5dB*/
++	0x288000a2,	/* 20, -4.0dB*/
++	0x26000098,	/* 21, -4.5dB*/
++	0x24000090,	/* 22, -5.0dB*/
++	0x22000088,	/* 23, -5.5dB*/
++	0x20000080,	/* 24, -6.0dB*/
++	0x1e400079,	/* 25, -6.5dB*/
++	0x1c800072,	/* 26, -7.0dB*/
++	0x1b00006c,	/* 27. -7.5dB*/
++	0x19800066,	/* 28, -8.0dB*/
++	0x18000060,	/* 29, -8.5dB*/
++	0x16c0005b,	/* 30, -9.0dB*/
++	0x15800056,	/* 31, -9.5dB*/
++	0x14400051,	/* 32, -10.0dB*/
++	0x1300004c,	/* 33, -10.5dB*/
++	0x12000048,	/* 34, -11.0dB*/
++	0x11000044,	/* 35, -11.5dB*/
++	0x10000040,	/* 36, -12.0dB*/
++};
++
++u8	cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
++	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},	/* 0, +0dB */
++	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 1, -0.5dB */
++	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 2, -1.0dB*/
++	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 3, -1.5dB*/
++	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 4, -2.0dB */
++	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 5, -2.5dB*/
++	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 6, -3.0dB*/
++	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 7, -3.5dB*/
++	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 8, -4.0dB */
++	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 9, -4.5dB*/
++	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 10, -5.0dB */
++	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 11, -5.5dB*/
++	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},	/* 12, -6.0dB <== default */
++	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 13, -6.5dB*/
++	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 14, -7.0dB */
++	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 15, -7.5dB*/
++	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
++	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 17, -8.5dB*/
++	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 18, -9.0dB */
++	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 19, -9.5dB*/
++	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 20, -10.0dB*/
++	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 21, -10.5dB*/
++	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 22, -11.0dB*/
++	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 23, -11.5dB*/
++	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 24, -12.0dB*/
++	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 25, -12.5dB*/
++	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 26, -13.0dB*/
++	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 27, -13.5dB*/
++	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 28, -14.0dB*/
++	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 29, -14.5dB*/
++	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 30, -15.0dB*/
++	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 31, -15.5dB*/
++	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}	/* 32, -16.0dB*/
++};
++
++u8	cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
++	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},	/* 0, +0dB */
++	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 1, -0.5dB */
++	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 2, -1.0dB */
++	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 3, -1.5dB*/
++	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 4, -2.0dB */
++	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 5, -2.5dB*/
++	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 6, -3.0dB */
++	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 7, -3.5dB */
++	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 8, -4.0dB */
++	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 9, -4.5dB*/
++	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 10, -5.0dB */
++	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 11, -5.5dB*/
++	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 12, -6.0dB  <== default*/
++	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 13, -6.5dB */
++	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 14, -7.0dB */
++	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 15, -7.5dB*/
++	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
++	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 17, -8.5dB*/
++	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 18, -9.0dB */
++	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 19, -9.5dB*/
++	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 20, -10.0dB*/
++	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 21, -10.5dB*/
++	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 22, -11.0dB*/
++	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 23, -11.5dB*/
++	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 24, -12.0dB*/
++	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 25, -12.5dB*/
++	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 26, -13.0dB*/
++	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 27, -13.5dB*/
++	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 28, -14.0dB*/
++	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 29, -14.5dB*/
++	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 30, -15.0dB*/
++	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 31, -15.5dB*/
++	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}	/* 32, -16.0dB*/
++};
++
++u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
++	0x0b40002d, /* 0,  -15.0dB	*/
++	0x0c000030, /* 1,  -14.5dB*/
++	0x0cc00033, /* 2,  -14.0dB*/
++	0x0d800036, /* 3,  -13.5dB*/
++	0x0e400039, /* 4,  -13.0dB */
++	0x0f00003c, /* 5,  -12.5dB*/
++	0x10000040, /* 6,  -12.0dB*/
++	0x11000044, /* 7,  -11.5dB*/
++	0x12000048, /* 8,  -11.0dB*/
++	0x1300004c, /* 9,  -10.5dB*/
++	0x14400051, /* 10, -10.0dB*/
++	0x15800056, /* 11, -9.5dB*/
++	0x16c0005b, /* 12, -9.0dB*/
++	0x18000060, /* 13, -8.5dB*/
++	0x19800066, /* 14, -8.0dB*/
++	0x1b00006c, /* 15, -7.5dB*/
++	0x1c800072, /* 16, -7.0dB*/
++	0x1e400079, /* 17, -6.5dB*/
++	0x20000080, /* 18, -6.0dB*/
++	0x22000088, /* 19, -5.5dB*/
++	0x24000090, /* 20, -5.0dB*/
++	0x26000098, /* 21, -4.5dB*/
++	0x288000a2, /* 22, -4.0dB*/
++	0x2ac000ab, /* 23, -3.5dB*/
++	0x2d4000b5, /* 24, -3.0dB*/
++	0x300000c0, /* 25, -2.5dB*/
++	0x32c000cb, /* 26, -2.0dB*/
++	0x35c000d7, /* 27, -1.5dB*/
++	0x390000e4, /* 28, -1.0dB*/
++	0x3c8000f2, /* 29, -0.5dB*/
++	0x40000100, /* 30, +0dB*/
++	0x43c0010f, /* 31, +0.5dB*/
++	0x47c0011f, /* 32, +1.0dB*/
++	0x4c000130, /* 33, +1.5dB*/
++	0x50800142, /* 34, +2.0dB*/
++	0x55400155, /* 35, +2.5dB*/
++	0x5a400169, /* 36, +3.0dB*/
++	0x5fc0017f, /* 37, +3.5dB*/
++	0x65400195, /* 38, +4.0dB*/
++	0x6b8001ae, /* 39, +4.5dB*/
++	0x71c001c7, /* 40, +5.0dB*/
++	0x788001e2, /* 41, +5.5dB*/
++	0x7f8001fe  /* 42, +6.0dB*/
++};
++
++u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
++	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
++	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
++	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
++	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/
++	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
++	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
++	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
++	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
++	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
++	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
++	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
++	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
++	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
++	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
++	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
++	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
++	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
++	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
++	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
++	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
++	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
++};
++
++u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
++	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
++	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
++	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
++	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/
++	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
++	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
++	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
++	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
++	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
++	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
++	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
++	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
++	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
++	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
++	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
++	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
++	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
++	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
++	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
++	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
++	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
++};
++
++u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
++	{0x44,	 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
++	{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
++	{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
++	{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	    /*-14.5dB*/
++	{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
++	{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
++	{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
++	{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
++	{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
++	{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
++	{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
++	{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
++	{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
++	{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
++	{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
++	{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
++	{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
++	{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
++	{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
++	{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
++	{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
++};
++
++u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
++	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},	/*  0, -16.0dB*/
++	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/*   1, -15.5dB*/
++	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/*  2, -15.0dB*/
++	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/*   3, -14.5dB*/
++	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/*   4, -14.0dB*/
++	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/*   5, -13.5dB*/
++	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/*   6, -13.0dB*/
++	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/*   7, -12.5dB*/
++	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/*  8, -12.0dB*/
++	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/*   9, -11.5dB*/
++	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/*  10, -11.0dB*/
++	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/*  11, -10.5dB*/
++	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/*  12, -10.0dB*/
++	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/*  13, -9.5dB*/
++	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/*  14, -9.0dB */
++	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/*  15, -8.5dB*/
++	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/*  16, -8.0dB */
++	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/*  17, -7.5dB*/
++	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/*  18, -7.0dB */
++	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/*  19, -6.5dB*/
++	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},	/*20, -6.0dB */
++	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/*  21, -5.5dB*/
++	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 22, -5.0dB */
++	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/*  23, -4.5dB*/
++	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/*  24, -4.0dB */
++	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/*  25, -3.5dB*/
++	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/*  26, -3.0dB*/
++	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/*  27, -2.5dB*/
++	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/*  28, -2.0dB */
++	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/*  29, -1.5dB*/
++	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/*  30, -1.0dB*/
++	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/*  31, -0.5dB*/
++	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}	/*  32, +0dB*/
++};
++
++u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
++	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},	/*  0, -16.0dB*/
++	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 1, -15.5dB*/
++	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/*  2, -15.0dB*/
++	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 3, -14.5dB*/
++	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/*  4, -14.0dB*/
++	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/*5, -13.5dB*/
++	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 6, -13.0dB*/
++	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/*  7, -12.5dB*/
++	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 8, -12.0dB*/
++	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 9, -11.5dB*/
++	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 10, -11.0dB*/
++	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/*11, -10.5dB*/
++	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 12, -10.0dB*/
++	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 13, -9.5dB*/
++	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/*14, -9.0dB */
++	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 15, -8.5dB*/
++	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
++	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 17, -7.5dB*/
++	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 18, -7.0dB */
++	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 19, -6.5dB */
++	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 20, -6.0dB */
++	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 21, -5.5dB*/
++	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 22, -5.0dB */
++	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/*23, -4.5dB*/
++	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 24, -4.0dB */
++	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 25, -3.5dB */
++	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 26, -3.0dB */
++	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/*27, -2.5dB*/
++	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 28, -2.0dB */
++	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/*29, -1.5dB*/
++	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 30, -1.0dB */
++	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 31, -0.5dB */
++	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}	/* 32, +0dB	*/
++};
++
++u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
++	0x0CD,          /*0 ,    -20dB*/
++	0x0D9,
++	0x0E6,
++	0x0F3,
++	0x102,
++	0x111,
++	0x121,
++	0x132,
++	0x144,
++	0x158,
++	0x16C,
++	0x182,
++	0x198,
++	0x1B1,
++	0x1CA,
++	0x1E5,
++	0x202,
++	0x221,
++	0x241,
++	0x263,
++	0x287,
++	0x2AE,
++	0x2D6,
++	0x301,
++	0x32F,
++	0x35F,
++	0x392,
++	0x3C9,
++	0x402,
++	0x43F,
++	0x47F,
++	0x4C3,
++	0x50C,
++	0x558,
++	0x5A9,
++	0x5FF,
++	0x65A,
++	0x6BA,
++	0x720,
++	0x78C,
++	0x7FF,
++};
++
++/* JJ ADD 20161014 */
++u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
++	0x0CD,          /*0 ,    -20dB*/
++	0x0D9,
++	0x0E6,
++	0x0F3,
++	0x102,
++	0x111,
++	0x121,
++	0x132,
++	0x144,
++	0x158,
++	0x16C,
++	0x182,
++	0x198,
++	0x1B1,
++	0x1CA,
++	0x1E5,
++	0x202,
++	0x221,
++	0x241,
++	0x263,
++	0x287,
++	0x2AE,
++	0x2D6,
++	0x301,
++	0x32F,
++	0x35F,
++	0x392,
++	0x3C9,
++	0x402,
++	0x43F,
++	0x47F,
++	0x4C3,
++	0x50C,
++	0x558,
++	0x5A9,
++	0x5FF,
++	0x65A,
++	0x6BA,
++	0x720,
++	0x78C,
++	0x7FF,
++};
++
++/* Winnita ADD 20171116 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/
++u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
++	0x0CD,			 /*0 ,    -20dB*/
++	0x0D9,
++	0x0E6,
++	0x0F3,
++	0x102,
++	0x111,
++	0x121,
++	0x132,
++	0x144,
++	0x158,
++	0x16C,
++	0x182,
++	0x198,
++	0x1B1,
++	0x1CA,
++	0x1E5,
++	0x202,
++	0x221,
++	0x241,
++	0x263,		/*19*/
++	0x287,		/*20*/
++	0x2AE,		/*21*/
++	0x2D6,		/*22*/
++	0x301,		/*23*/
++	0x32F,		/*24*/
++	0x35F,		/*25*/
++	0x392,		/*26*/
++	0x3C9,		/*27*/
++	0x402,		/*28*/
++	0x43F,		/*29*/
++	0x47F,		/*30*/
++	0x4C3,		/*31*/
++	0x50C,		/*32*/
++	0x558,		/*33*/
++	0x5A9,		/*34*/
++	0x5FF,		/*35*/
++	0x65A,		/*36*/
++	0x6BA,
++	0x720,
++	0x78C,
++	0x7FF,
++};
++
++/* Winnita ADD 201805 PathA 0xAB4[10:0]*/
++u32 cck_swing_table_ch1_ch14_8721d[CCK_TABLE_SIZE_8721D] = {
++	0x0CD,			 /*0 ,    -20dB*/
++	0x0D9,
++	0x0E6,
++	0x0F3,
++	0x102,
++	0x111,
++	0x121,
++	0x132,
++	0x144,
++	0x158,
++	0x16C,
++	0x182,
++	0x198,
++	0x1B1,
++	0x1CA,
++	0x1E5,
++	0x202,
++	0x221,
++	0x241,
++	0x263,		/*19*/
++	0x287,		/*20*/
++	0x2AE,		/*21*/
++	0x2D6,		/*22*/
++	0x301,		/*23*/
++	0x32F,		/*24*/
++	0x35F,		/*25*/
++	0x392,		/*26*/
++	0x3C9,		/*27*/
++	0x402,		/*28*/
++	0x43F,		/*29*/
++	0x47F,		/*30*/
++	0x4C3,		/*31*/
++	0x50C,		/*32*/
++	0x558,		/*33*/
++	0x5A9,		/*34*/
++	0x5FF,		/*35*/
++	0x65A,		/*36*/
++	0x6BA,
++	0x720,
++	0x78C,
++	0x7FF,
++};
++
++u32 cck_swing_table_ch1_ch14_8710c[CCK_TABLE_SIZE_8710C] = {
++	0x0CD,          /*0 ,    -20dB*/
++	0x0D9,
++	0x0E6,
++	0x0F3,
++	0x102,
++	0x111,
++	0x121,
++	0x132,
++	0x144,
++	0x158,
++	0x16C,
++	0x182,
++	0x198,
++	0x1B1,
++	0x1CA,
++	0x1E5,
++	0x202,
++	0x221,
++	0x241,
++	0x263,
++	0x287,
++	0x2AE,
++	0x2D6,
++	0x301,
++	0x32F,
++	0x35F,
++	0x392,
++	0x3C9,
++	0x402,
++	0x43F,
++	0x47F,
++	0x4C3,
++	0x50C,
++	0x558,
++	0x5A9,
++	0x5FF,
++	0x65A,
++	0x6BA,
++	0x720,
++	0x78C,
++	0x7FF,
++};
++
++u32 cck_swing_table_03db_ch1_ch14_8710c[CCK_03DB_TABLE_SIZE_8710C] = {
++	0x143,		/*0 ,    -4dB*/
++	0x14C,		/*1 ,    -3.75dB*/
++	0x156,		/*2 ,    -3.5dB*/
++	0x160,
++	0x16A,
++	0x175,
++	0x17F,
++	0x18B,
++	0x196,
++	0x1A2,
++	0x1AE,
++	0x1BB,
++	0x1C8,
++	0x1D5,
++	0x1E3,
++	0x1F1,
++	0x200,
++	0x20F,
++	0x21E,
++	0x22F,
++	0x23F,
++	0x250,
++	0x261,
++	0x273,
++	0x285,
++	0x298,
++	0x2AB,
++	0x2BF,
++	0x2D6,
++	0x2E9,
++	0x2FF,
++	0x315,
++	0x32C,
++	0x344,
++	0x35C,
++	0x375,
++	0x390,
++	0x3AA,
++	0x3C5,
++	0x3E1,
++	0x402,		/*40 ,    +6dB	default*/
++	0x41C,
++	0x43B,
++	0x45A,
++	0x47C,
++	0x49C,
++	0x4BF,
++	0x4E2,
++	0x510,
++	0x52C,
++	0x553,
++	0x57B,
++	0x5A5,
++	0x5CE,
++	0x5F9,
++	0x626,
++	0x655,
++	0x683,
++	0x6B5,
++	0x6E6,
++	0x71E,
++	0x74E,
++	0x786,
++	0x7BD,
++	0x7F9,
++	0x832,
++	0x871,
++	0x8AF,
++	0x8F2,
++	0x932,
++	0x977,
++	0x9BE,
++	0xA0E,
++	0xA52,
++	0xAA1,
++	0xAEE,
++	0xB54,
++	0xB95,
++	0xBEB,
++	0xC43,
++	0xCA3		/*80 ,    +16dB*/
++};
++
++u32 ofdm_swing_table_03DB_8710c[OFDM_03DB_TABLE_SIZE_8710C] = {
++	0xE4,		/*0 ,    -7dB*/
++	0xEB,		/*1 ,    -6.75dB*/
++	0xF2,		/*2 ,    -6.5dB*/
++	0xF9,
++	0x100,
++	0x108,
++	0x110,
++	0x118,
++	0x11F,
++	0x128,
++	0x131,
++	0x13A,
++	0x143,
++	0x14C,
++	0x156,
++	0x160,
++	0x16A,
++	0x175,
++	0x180,
++	0x18B,
++	0x196,
++	0x1A2,
++	0x1AE,
++	0x1BB,
++	0x1C8,
++	0x1D5,
++	0x1E3,
++	0x1F1,
++	0x200,
++	0x20F,
++	0x21F,
++	0x22F,
++	0x23F,
++	0x250,
++	0x261,
++	0x273,
++	0x286,
++	0x298,
++	0x2AB,
++	0x2BF,
++	0x2D6,		/*40 ,    +3dB default*/
++	0x2E9,
++	0x2FF,
++	0x315,
++	0x32C,
++	0x344,
++	0x35C,
++	0x375,
++	0x390,
++	0x3AA,
++	0x3C5,
++	0x3E1,
++	0x3FF,
++	0x41C,
++	0x43B,
++	0x45A,
++	0x47B,
++	0x49C,
++	0x4BF,
++	0x4E2,
++	0x507,
++	0x52C,
++	0x553,
++	0x57B,
++	0x5A4,
++	0x5CE,
++	0x5F9,
++	0x626,
++	0x654,
++	0x683,
++	0x6B4,
++	0x6E6,
++	0x71B,
++	0x74E,
++	0x785,
++	0x7BD,
++	0x7F7,
++	0x832,
++	0x870,
++	0x8AF,
++	0x8F0		/*80 ,    +13dB*/
++};
++
++
++
++u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
++	0x081, /* 0,  -12.0dB*/
++	0x088, /* 1,  -11.5dB*/
++	0x090, /* 2,  -11.0dB*/
++	0x099, /* 3,  -10.5dB*/
++	0x0A2, /* 4,  -10.0dB*/
++	0x0AC, /* 5,  -9.5dB*/
++	0x0B6, /* 6,  -9.0dB*/
++	0x0C0, /*7,  -8.5dB*/
++	0x0CC, /* 8,  -8.0dB*/
++	0x0D8, /* 9,  -7.5dB*/
++	0x0E5, /* 10, -7.0dB*/
++	0x0F2, /* 11, -6.5dB*/
++	0x101, /* 12, -6.0dB*/
++	0x110, /* 13, -5.5dB*/
++	0x120, /* 14, -5.0dB*/
++	0x131, /* 15, -4.5dB*/
++	0x143, /* 16, -4.0dB*/
++	0x156, /* 17, -3.5dB*/
++	0x16A, /* 18, -3.0dB*/
++	0x180, /* 19, -2.5dB*/
++	0x197, /* 20, -2.0dB*/
++	0x1AF, /* 21, -1.5dB*/
++	0x1C8, /* 22, -1.0dB*/
++	0x1E3, /* 23, -0.5dB*/
++	0x200, /* 24, +0  dB*/
++	0x21E, /* 25, +0.5dB*/
++	0x23E, /* 26, +1.0dB*/
++	0x261, /* 27, +1.5dB*/
++	0x285,/* 28, +2.0dB*/
++	0x2AB, /* 29, +2.5dB*/
++	0x2D3, /*30, +3.0dB*/
++	0x2FE, /* 31, +3.5dB*/
++	0x32B, /* 32, +4.0dB*/
++	0x35C, /* 33, +4.5dB*/
++	0x38E, /* 34, +5.0dB*/
++	0x3C4, /* 35, +5.5dB*/
++	0x3FE  /* 36, +6.0dB	*/
++};
++
++void
++odm_txpowertracking_init(
++	void	*dm_void
++)
++{
++	struct dm_struct	*dm = (struct dm_struct *)dm_void;
++
++	odm_txpowertracking_thermal_meter_init(dm);
++}
++
++u8
++get_swing_index(
++	void	*dm_void
++)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	u8 i = 0;
++	u32 bb_swing;
++	u32 swing_table_size;
++	u32 *swing_table;
++	u32 table_value;
++
++	if (dm->support_ic_type == ODM_RTL8710C) {
++		bb_swing = odm_get_bb_reg(dm, R_0xcc8, 0x000007ff);
++
++		for (i = 0; i < OFDM_03DB_TABLE_SIZE_8710C; i++) {
++			if (bb_swing == ofdm_swing_table_03DB_8710c[i])
++				break;
++		}
++	}
++
++	if (dm->support_ic_type == ODM_RTL8195B) {
++		bb_swing = odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000);
++		swing_table = tx_scaling_table_jaguar;
++		swing_table_size = TXSCALE_TABLE_SIZE;
++
++		for (i = 0; i < swing_table_size; i++) {
++			table_value = swing_table[i];
++
++			table_value = table_value;
++			if (bb_swing == table_value)
++				break;
++		}
++	}
++
++	return i;
++}
++
++u8
++get_cck_swing_index(
++	void		*dm_void
++)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	u8 i = 0;
++	u32 bb_cck_swing;
++
++	if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
++	    dm->support_ic_type == ODM_RTL8192E) {
++		bb_cck_swing = odm_read_1byte(dm, 0xa22);
++
++		for (i = 0; i < CCK_TABLE_SIZE; i++) {
++			if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
++				break;
++		}
++	} else if (dm->support_ic_type == ODM_RTL8703B) {
++		bb_cck_swing = odm_read_1byte(dm, 0xa22);
++
++		for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
++			if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
++				break;
++		}
++	} else if (dm->support_ic_type == ODM_RTL8710C) {
++		bb_cck_swing = odm_get_bb_reg(dm, R_0xab4, 0x7ff);
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "bb_cck_swing = 0x%x\n", bb_cck_swing);
++
++		for (i = 0; i < CCK_03DB_TABLE_SIZE_8710C; i++) {
++			if (bb_cck_swing == cck_swing_table_03db_ch1_ch14_8710c[i])
++				break;
++		}
++	}
++
++	return i;
++}
++
++void
++odm_txpowertracking_thermal_meter_init(
++	void	*dm_void
++)
++{
++	struct dm_struct	*dm = (struct dm_struct *)dm_void;
++	u8 default_swing_index;
++	u8 p = 0;
++	struct dm_rf_calibration_struct	*cali_info = &dm->rf_calibrate_info;
++	struct _hal_rf_ *rf = &dm->rf_table;
++
++	if (!(*dm->mp_mode))
++		cali_info->txpowertrack_control = true;
++	else
++		cali_info->txpowertrack_control = false;
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "dm txpowertrack_control = %d\n", cali_info->txpowertrack_control);
++
++	/* dm->rf_calibrate_info.txpowertrack_control = true; */
++	cali_info->thermal_value = rf->eeprom_thermal;
++	cali_info->thermal_value_iqk = rf->eeprom_thermal;
++	cali_info->thermal_value_lck = rf->eeprom_thermal;
++
++	if (!cali_info->default_bb_swing_index_flag) {
++		if (dm->support_ic_type == ODM_RTL8195B) {
++			default_swing_index = get_swing_index(dm);
++			cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
++			cali_info->default_cck_index = 24;
++		} else if (dm->support_ic_type == ODM_RTL8721D) {
++			cali_info->default_ofdm_index = 28;	/*OFDM: -1dB*/
++			cali_info->default_cck_index = 28;	/*CCK: -6dB*/
++		} else if (dm->support_ic_type == ODM_RTL8710C) {
++			cali_info->default_ofdm_index = get_swing_index(dm);
++			cali_info->default_cck_index = get_cck_swing_index(dm);
++		}
++		cali_info->default_bb_swing_index_flag = true;
++	}
++
++	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
++	cali_info->CCK_index = cali_info->default_cck_index;
++
++	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
++		cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
++		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
++		cali_info->delta_power_index[p] = 0;
++		cali_info->delta_power_index_last[p] = 0;
++		cali_info->power_index_offset[p] = 0;
++	}
++	cali_info->modify_tx_agc_value_ofdm = 0;
++	cali_info->modify_tx_agc_value_cck = 0;
++	cali_info->tm_trigger = 0;
++}
++
++void
++odm_txpowertracking_check(
++	void	*dm_void
++)
++{
++	struct dm_struct	*dm = (struct dm_struct *)dm_void;
++
++	odm_txpowertracking_check_iot(dm);
++}
++
++void
++odm_txpowertracking_check_iot(
++	void	*dm_void
++)
++{
++	struct dm_struct	*dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_		*rf = &dm->rf_table;
++
++	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
++		return;
++
++	if (!dm->rf_calibrate_info.tm_trigger) {
++		if (dm->support_ic_type == ODM_RTL8195B)
++			odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03);
++		else if (dm->support_ic_type == ODM_RTL8721D ||
++			dm->support_ic_type == ODM_RTL8710C)
++			odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW,
++				       (BIT(12) | BIT(11)), 0x03);
++
++		dm->rf_calibrate_info.tm_trigger = 1;
++		return;
++	}
++	odm_txpowertracking_callback_thermal_meter(dm);
++	dm->rf_calibrate_info.tm_trigger = 0;
++}
++
++void
++odm_txpowertracking_check_mp(
++	void	*dm_void
++)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	void	*adapter = dm->adapter;
++
++	if (odm_check_power_status(adapter) == false) {
++		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("check_pow_status, return false\n"));
++		return;
++	}
++
++	odm_txpowertracking_thermal_meter_check(adapter);
++#endif
++}
++
++void
++odm_txpowertracking_check_ap(
++	void	*dm_void
++)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	struct rtl8192cd_priv	*priv		= dm->priv;
++
++	return;
++
++#endif
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_iot.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_iot.h
+new file mode 100644
+index 000000000..81ddde2da
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_iot.h
+@@ -0,0 +1,371 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_POWERTRACKING_H__
++#define __HALRF_POWERTRACKING_H__
++
++#define		DPK_DELTA_MAPPING_NUM	13
++#define		index_mapping_HP_NUM	15
++#define	OFDM_TABLE_SIZE	43
++#define	CCK_TABLE_SIZE			33
++#define	CCK_TABLE_SIZE_88F	21
++#define TXSCALE_TABLE_SIZE		37
++#define CCK_TABLE_SIZE_8723D	41
++/* JJ ADD 20161014 */
++#define CCK_TABLE_SIZE_8710B	41
++#define	CCK_TABLE_SIZE_8192F   41
++#define	CCK_TABLE_SIZE_8721D   41
++#define	CCK_TABLE_SIZE_8710C   41
++#define	CCK_03DB_TABLE_SIZE_8710C   81
++#define	OFDM_03DB_TABLE_SIZE_8710C	81
++
++
++#define TXPWR_TRACK_TABLE_SIZE	30
++#define DELTA_SWINGIDX_SIZE     30
++#define DELTA_SWINTSSI_SIZE     61
++#define BAND_NUM				4
++
++#define AVG_THERMAL_NUM		8
++#define IQK_MAC_REG_NUM		4
++#define IQK_ADDA_REG_NUM		16
++#define IQK_BB_REG_NUM_MAX	10
++
++#define IQK_BB_REG_NUM		9
++
++
++
++#define iqk_matrix_reg_num	8
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
++#else
++#define IQK_MATRIX_SETTINGS_NUM	(14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
++#endif
++
++extern	u32 ofdm_swing_table[OFDM_TABLE_SIZE];
++extern	u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
++extern	u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
++
++extern	u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
++extern	u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
++extern	u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
++extern	u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
++extern	u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
++extern	u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
++extern	u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
++/* JJ ADD 20161014 */
++extern	u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
++extern	u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
++extern	u32 cck_swing_table_ch1_ch14_8721d[CCK_TABLE_SIZE_8721D];
++extern  u32 cck_swing_table_ch1_ch14_8710c[CCK_TABLE_SIZE_8710C];
++extern  u32 cck_swing_table_03db_ch1_ch14_8710c[CCK_03DB_TABLE_SIZE_8710C];
++extern  u32 ofdm_swing_table_03DB_8710c[OFDM_03DB_TABLE_SIZE_8710C];
++
++extern  u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
++
++/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
++#else
++static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};
++static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11};
++#endif
++
++void
++odm_txpowertracking_init(
++	void		*dm_void
++);
++
++#define dm_check_txpowertracking	odm_txpowertracking_check
++
++struct iqk_matrix_regs_setting {
++	boolean	is_iqk_done;
++	s32		value[3][iqk_matrix_reg_num];
++	boolean	is_bw_iqk_result_saved[3];
++};
++
++struct dm_rf_calibration_struct {
++	/* for tx power tracking */
++
++	u32	rega24; /* for TempCCK */
++	s32	rege94;
++	s32	rege9c;
++	s32	regeb4;
++	s32	regebc;
++
++	u8	tx_powercount;
++	boolean is_txpowertracking_init;
++	boolean is_txpowertracking;
++	u8  	txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
++	u8	tm_trigger;
++	u8  	internal_pa_5g[2];	/* pathA / pathB */
++
++	u8  	thermal_meter[2];    /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
++	u8	thermal_value;
++	u8	thermal_value_lck;
++	u8	thermal_value_iqk;
++	s8  	thermal_value_delta; /* delta of thermal_value and efuse thermal */
++	u8	thermal_value_dpk;
++	u8	thermal_value_avg[AVG_THERMAL_NUM];
++	u8	thermal_value_avg_index;
++	u8	thermal_value_rx_gain;
++	u8	thermal_value_crystal;
++	u8	thermal_value_dpk_store;
++	u8	thermal_value_dpk_track;
++	boolean	txpowertracking_in_progress;
++
++	boolean	is_reloadtxpowerindex;
++	u8	is_rf_pi_enable;
++	u32 	txpowertracking_callback_cnt; /* cosa add for debug */
++
++
++	/* ------------------------- Tx power Tracking ------------------------- */
++	u8	is_cck_in_ch14;
++	u8	CCK_index;
++	u8	OFDM_index[MAX_RF_PATH];
++	s8	power_index_offset[MAX_RF_PATH];
++	s8	delta_power_index[MAX_RF_PATH];
++	s8	delta_power_index_last[MAX_RF_PATH];
++	boolean is_tx_power_changed;
++	s8	xtal_offset;
++	s8	xtal_offset_last;
++
++#if (RTL8710B_SUPPORT == 1 || RTL8721D_SUPPORT == 1)
++	struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
++#endif
++	u8	delta_lck;
++	s8  bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
++	u8  delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
++#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	u8  delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
++#endif
++	u8  delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
++#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	u8  delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
++#endif
++
++#if (RTL8195B_SUPPORT == 1)
++	u8  delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
++#endif
++
++#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	u8  delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
++#endif
++#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	u8  delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
++#endif
++	s8  delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
++	s8  delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
++
++	u8			bb_swing_idx_ofdm[MAX_RF_PATH];
++	u8			bb_swing_idx_ofdm_current;
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
++	u8			bb_swing_idx_ofdm_base[MAX_RF_PATH];
++#else
++	u8			bb_swing_idx_ofdm_base;
++#endif
++	boolean		default_bb_swing_index_flag;
++	boolean			bb_swing_flag_ofdm;
++	u8			bb_swing_idx_cck;
++	u8			bb_swing_idx_cck_current;
++	u8			bb_swing_idx_cck_base;
++	u8			default_ofdm_index;
++	u8			default_cck_index;
++	boolean			bb_swing_flag_cck;
++
++	s8			absolute_ofdm_swing_idx[MAX_RF_PATH];
++	s8			remnant_ofdm_swing_idx[MAX_RF_PATH];
++	s8			absolute_cck_swing_idx[MAX_RF_PATH];
++	s8			remnant_cck_swing_idx;
++	s8			modify_tx_agc_value;       /*Remnat compensate value at tx_agc */
++	boolean			modify_tx_agc_flag_path_a;
++	boolean			modify_tx_agc_flag_path_b;
++	boolean			modify_tx_agc_flag_path_c;
++	boolean			modify_tx_agc_flag_path_d;
++	boolean			modify_tx_agc_flag_path_a_cck;
++	boolean			modify_tx_agc_flag_path_b_cck;
++
++	s8			kfree_offset[MAX_RF_PATH];
++
++	/* -------------------------------------------------------------------- */
++
++	/* for IQK */
++	u32	regc04;
++	u32	reg874;
++	u32	regc08;
++	u32	regb68;
++	u32	regb6c;
++	u32	reg870;
++	u32	reg860;
++	u32	reg864;
++
++	boolean	is_iqk_initialized;
++	boolean is_lck_in_progress;
++	boolean	is_antenna_detected;
++	boolean	is_need_iqk;
++	boolean	is_iqk_in_progress;
++	boolean is_iqk_pa_off;
++	u8	delta_iqk;
++	u32	ADDA_backup[IQK_ADDA_REG_NUM];
++	u32	IQK_MAC_backup[IQK_MAC_REG_NUM];
++	u32	IQK_BB_backup_recover[9];
++	u32	IQK_BB_backup[IQK_BB_REG_NUM];
++#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	u32 	tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
++	u32 	rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */
++	u32	tx_iqc_8703b[3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
++	u32	rx_iqc_8703b[2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
++	u32	tx_iqc_8723d[2][3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
++	u32	rx_iqc_8723d[2][2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
++#endif
++	/* JJ ADD 20161014 */
++	u32	tx_iqc_8710b[2][3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
++	u32	rx_iqc_8710b[2][2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
++
++	u8	iqk_step;
++	u8	kcount;
++	u8	retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
++	boolean	is_mp_mode;
++
++
++
++	/* <James> IQK time measurement */
++	u32	iqk_start_time;
++	u32	iqk_progressing_time;
++	u32	iqk_total_progressing_time;
++	u32	lck_progressing_time;
++
++	u32  lok_result;
++
++	/* for APK */
++	u32 	ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
++	u8	is_ap_kdone;
++	u8	is_apk_thermal_meter_ignore;
++
++	/* DPK */
++	boolean is_dpk_fail;
++	u8	is_dp_done;
++	u8	is_dp_path_aok;
++	u8	is_dp_path_bok;
++
++	u32	tx_lok[2];
++	u32  dpk_tx_agc;
++	s32  dpk_gain;
++	u32  dpk_thermal[4];
++	s8 modify_tx_agc_value_ofdm;
++	s8 modify_tx_agc_value_cck;
++
++	/*Add by Yuchen for Kfree Phydm*/
++	u8			reg_rf_kfree_enable;	/*for registry*/
++	u8			rf_kfree_enable;		/*for efuse enable check*/
++
++};
++
++
++void
++odm_txpowertracking_check(
++	void		*dm_void
++);
++
++void
++odm_txpowertracking_check_ap(
++	void		*dm_void
++);
++
++void
++odm_txpowertracking_thermal_meter_init(
++	void		*dm_void
++);
++
++
++void
++odm_txpowertracking_check_mp(
++	void		*dm_void
++);
++
++
++void
++odm_txpowertracking_check_iot(
++	void		*dm_void
++);
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++
++void
++odm_txpowertracking_callback_thermal_meter92c(
++	void	*adapter
++);
++
++void
++odm_txpowertracking_callback_rx_gain_thermal_meter92d(
++	void	*adapter
++);
++
++void
++odm_txpowertracking_callback_thermal_meter92d(
++	void	*adapter
++);
++
++void
++odm_txpowertracking_direct_call92c(
++	void		*adapter
++);
++
++void
++odm_txpowertracking_thermal_meter_check(
++	void		*adapter
++);
++
++#endif
++
++#endif	/*#ifndef __HALRF_POWER_TRACKING_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_win.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_win.c
+new file mode 100644
+index 000000000..c22e9d894
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_win.c
+@@ -0,0 +1,909 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/*============================================================	*/
++/* include files												*/
++/*============================================================	*/
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++/* ************************************************************
++ * Global var
++ * ************************************************************ */
++
++u32	ofdm_swing_table[OFDM_TABLE_SIZE] = {
++	0x7f8001fe,	/* 0, +6.0dB */
++	0x788001e2,	/* 1, +5.5dB */
++	0x71c001c7,	/* 2, +5.0dB */
++	0x6b8001ae,	/* 3, +4.5dB */
++	0x65400195,	/* 4, +4.0dB */
++	0x5fc0017f,	/* 5, +3.5dB */
++	0x5a400169,	/* 6, +3.0dB */
++	0x55400155,	/* 7, +2.5dB */
++	0x50800142,	/* 8, +2.0dB */
++	0x4c000130,	/* 9, +1.5dB */
++	0x47c0011f,	/* 10, +1.0dB */
++	0x43c0010f,	/* 11, +0.5dB */
++	0x40000100,	/* 12, +0dB */
++	0x3c8000f2,	/* 13, -0.5dB */
++	0x390000e4,	/* 14, -1.0dB */
++	0x35c000d7,	/* 15, -1.5dB */
++	0x32c000cb,	/* 16, -2.0dB */
++	0x300000c0,	/* 17, -2.5dB */
++	0x2d4000b5,	/* 18, -3.0dB */
++	0x2ac000ab,	/* 19, -3.5dB */
++	0x288000a2,	/* 20, -4.0dB */
++	0x26000098,	/* 21, -4.5dB */
++	0x24000090,	/* 22, -5.0dB */
++	0x22000088,	/* 23, -5.5dB */
++	0x20000080,	/* 24, -6.0dB */
++	0x1e400079,	/* 25, -6.5dB */
++	0x1c800072,	/* 26, -7.0dB */
++	0x1b00006c,	/* 27. -7.5dB */
++	0x19800066,	/* 28, -8.0dB */
++	0x18000060,	/* 29, -8.5dB */
++	0x16c0005b,	/* 30, -9.0dB */
++	0x15800056,	/* 31, -9.5dB */
++	0x14400051,	/* 32, -10.0dB */
++	0x1300004c,	/* 33, -10.5dB */
++	0x12000048,	/* 34, -11.0dB */
++	0x11000044,	/* 35, -11.5dB */
++	0x10000040,	/* 36, -12.0dB */
++};
++
++u8	cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
++	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},	/* 0, +0dB */
++	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 1, -0.5dB */
++	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 2, -1.0dB */
++	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 3, -1.5dB */
++	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 4, -2.0dB */
++	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 5, -2.5dB */
++	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 6, -3.0dB */
++	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 7, -3.5dB */
++	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 8, -4.0dB */
++	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 9, -4.5dB */
++	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 10, -5.0dB */
++	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 11, -5.5dB */
++	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},	/* 12, -6.0dB <== default */
++	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 13, -6.5dB */
++	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 14, -7.0dB */
++	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 15, -7.5dB */
++	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
++	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 17, -8.5dB */
++	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 18, -9.0dB */
++	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 19, -9.5dB */
++	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 20, -10.0dB */
++	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 21, -10.5dB */
++	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 22, -11.0dB */
++	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 23, -11.5dB */
++	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 24, -12.0dB */
++	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 25, -12.5dB */
++	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 26, -13.0dB */
++	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 27, -13.5dB */
++	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 28, -14.0dB */
++	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 29, -14.5dB */
++	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 30, -15.0dB */
++	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 31, -15.5dB */
++	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}	/* 32, -16.0dB */
++};
++
++
++u8	cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
++	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},	/* 0, +0dB */
++	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 1, -0.5dB */
++	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 2, -1.0dB */
++	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 3, -1.5dB */
++	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 4, -2.0dB */
++	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 5, -2.5dB */
++	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 6, -3.0dB */
++	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 7, -3.5dB */
++	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 8, -4.0dB */
++	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 9, -4.5dB */
++	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 10, -5.0dB */
++	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 11, -5.5dB */
++	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 12, -6.0dB  <== default */
++	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 13, -6.5dB */
++	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 14, -7.0dB */
++	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 15, -7.5dB */
++	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
++	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 17, -8.5dB */
++	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 18, -9.0dB */
++	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 19, -9.5dB */
++	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 20, -10.0dB */
++	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 21, -10.5dB */
++	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 22, -11.0dB */
++	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 23, -11.5dB */
++	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 24, -12.0dB */
++	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 25, -12.5dB */
++	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 26, -13.0dB */
++	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 27, -13.5dB */
++	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 28, -14.0dB */
++	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 29, -14.5dB */
++	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 30, -15.0dB */
++	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 31, -15.5dB */
++	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}	/* 32, -16.0dB */
++};
++
++
++u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
++	0x0b40002d, /* 0,  -15.0dB */
++	0x0c000030, /* 1,  -14.5dB */
++	0x0cc00033, /* 2,  -14.0dB */
++	0x0d800036, /* 3,  -13.5dB */
++	0x0e400039, /* 4,  -13.0dB */
++	0x0f00003c, /* 5,  -12.5dB */
++	0x10000040, /* 6,  -12.0dB */
++	0x11000044, /* 7,  -11.5dB */
++	0x12000048, /* 8,  -11.0dB */
++	0x1300004c, /* 9,  -10.5dB */
++	0x14400051, /* 10, -10.0dB */
++	0x15800056, /* 11, -9.5dB */
++	0x16c0005b, /* 12, -9.0dB */
++	0x18000060, /* 13, -8.5dB */
++	0x19800066, /* 14, -8.0dB */
++	0x1b00006c, /* 15, -7.5dB */
++	0x1c800072, /* 16, -7.0dB */
++	0x1e400079, /* 17, -6.5dB */
++	0x20000080, /* 18, -6.0dB */
++	0x22000088, /* 19, -5.5dB */
++	0x24000090, /* 20, -5.0dB */
++	0x26000098, /* 21, -4.5dB */
++	0x288000a2, /* 22, -4.0dB */
++	0x2ac000ab, /* 23, -3.5dB */
++	0x2d4000b5, /* 24, -3.0dB */
++	0x300000c0, /* 25, -2.5dB */
++	0x32c000cb, /* 26, -2.0dB */
++	0x35c000d7, /* 27, -1.5dB */
++	0x390000e4, /* 28, -1.0dB */
++	0x3c8000f2, /* 29, -0.5dB */
++	0x40000100, /* 30, +0dB */
++	0x43c0010f, /* 31, +0.5dB */
++	0x47c0011f, /* 32, +1.0dB */
++	0x4c000130, /* 33, +1.5dB */
++	0x50800142, /* 34, +2.0dB */
++	0x55400155, /* 35, +2.5dB */
++	0x5a400169, /* 36, +3.0dB */
++	0x5fc0017f, /* 37, +3.5dB */
++	0x65400195, /* 38, +4.0dB */
++	0x6b8001ae, /* 39, +4.5dB */
++	0x71c001c7, /* 40, +5.0dB */
++	0x788001e2, /* 41, +5.5dB */
++	0x7f8001fe  /* 42, +6.0dB */
++};
++
++
++u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
++	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
++	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
++	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
++	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/
++	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
++	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
++	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
++	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
++	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
++	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
++	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
++	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
++	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
++	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
++	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
++	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
++	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
++	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
++	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
++	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
++	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
++};
++
++
++u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
++	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
++	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
++	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
++	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/
++	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
++	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
++	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
++	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
++	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
++	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
++	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
++	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
++	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
++	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
++	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
++	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
++	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
++	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
++	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
++	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
++	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
++};
++
++
++u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
++	{0x44,	 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
++	{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
++	{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
++	{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	    /*-14.5dB*/
++	{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
++	{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
++	{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
++	{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
++	{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
++	{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
++	{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
++	{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
++	{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
++	{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
++	{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
++	{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
++	{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
++	{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
++	{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
++	{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
++	{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
++};
++
++
++u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
++	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},	/* 0, -16.0dB */
++	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 1, -15.5dB */
++	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 2, -15.0dB */
++	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 3, -14.5dB */
++	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 4, -14.0dB */
++	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 5, -13.5dB */
++	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 6, -13.0dB */
++	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 7, -12.5dB */
++	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 8, -12.0dB */
++	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 9, -11.5dB */
++	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 10, -11.0dB */
++	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 11, -10.5dB */
++	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 12, -10.0dB */
++	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 13, -9.5dB */
++	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 14, -9.0dB */
++	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 15, -8.5dB */
++	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
++	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 17, -7.5dB */
++	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 18, -7.0dB */
++	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 19, -6.5dB */
++	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},	/* 20, -6.0dB */
++	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 21, -5.5dB */
++	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 22, -5.0dB */
++	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 23, -4.5dB */
++	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 24, -4.0dB */
++	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 25, -3.5dB */
++	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 26, -3.0dB */
++	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 27, -2.5dB */
++	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 28, -2.0dB */
++	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 29, -1.5dB */
++	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 30, -1.0dB */
++	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 31, -0.5dB */
++	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}	/* 32, +0dB */
++};
++
++
++u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
++	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},	/* 0, -16.0dB */
++	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 1, -15.5dB */
++	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 2, -15.0dB */
++	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 3, -14.5dB */
++	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 4, -14.0dB */
++	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 5, -13.5dB */
++	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 6, -13.0dB */
++	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 7, -12.5dB */
++	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 8, -12.0dB */
++	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 9, -11.5dB */
++	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 10, -11.0dB */
++	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 11, -10.5dB */
++	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 12, -10.0dB */
++	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 13, -9.5dB */
++	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 14, -9.0dB */
++	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 15, -8.5dB */
++	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
++	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 17, -7.5dB */
++	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 18, -7.0dB */
++	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 19, -6.5dB */
++	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 20, -6.0dB */
++	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 21, -5.5dB */
++	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 22, -5.0dB */
++	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 23, -4.5dB */
++	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 24, -4.0dB */
++	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 25, -3.5dB */
++	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 26, -3.0dB */
++	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 27, -2.5dB */
++	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 28, -2.0dB */
++	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 29, -1.5dB */
++	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 30, -1.0dB */
++	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 31, -0.5dB */
++	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}	/* 32, +0dB */
++};
++u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
++	0x0CD,
++	0x0D9,
++	0x0E6,
++	0x0F3,
++	0x102,
++	0x111,
++	0x121,
++	0x132,
++	0x144,
++	0x158,
++	0x16C,
++	0x182,
++	0x198,
++	0x1B1,
++	0x1CA,
++	0x1E5,
++	0x202,
++	0x221,
++	0x241,
++	0x263,
++	0x287,
++	0x2AE,
++	0x2D6,
++	0x301,
++	0x32F,
++	0x35F,
++	0x392,
++	0x3C9,
++	0x402,
++	0x43F,
++	0x47F,
++	0x4C3,
++	0x50C,
++	0x558,
++	0x5A9,
++	0x5FF,
++	0x65A,
++	0x6BA,
++	0x720,
++	0x78C,
++	0x7FF,
++};
++/* JJ ADD 20161014 */
++u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
++	0x0CD,			 /*0 ,    -20dB*/
++	0x0D9,
++	0x0E6,
++	0x0F3,
++	0x102,
++	0x111,
++	0x121,
++	0x132,
++	0x144,
++	0x158,
++	0x16C,
++	0x182,
++	0x198,
++	0x1B1,
++	0x1CA,
++	0x1E5,
++	0x202,
++	0x221,
++	0x241,
++	0x263,		/*19*/
++	0x287,		/*20*/
++	0x2AE,		/*21*/
++	0x2D6,		/*22*/
++	0x301,		/*23*/
++	0x32F,		/*24*/
++	0x35F,		/*25*/
++	0x392,		/*26*/
++	0x3C9,		/*27*/
++	0x402,		/*28*/
++	0x43F,		/*29*/
++	0x47F,		/*30*/
++	0x4C3,		/*31*/
++	0x50C,		/*32*/
++	0x558,		/*33*/
++	0x5A9,		/*34*/
++	0x5FF,		/*35*/
++	0x65A,		/*36*/
++	0x6BA,
++	0x720,
++	0x78C,
++	0x7FF,
++};
++
++/* Winnita ADD 20170828 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/
++u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
++	0x0CD,			 /*0 ,    -20dB*/
++	0x0D9,
++	0x0E6,
++	0x0F3,
++	0x102,
++	0x111,
++	0x121,
++	0x132,
++	0x144,
++	0x158,
++	0x16C,
++	0x182,
++	0x198,
++	0x1B1,
++	0x1CA,
++	0x1E5,
++	0x202,
++	0x221,
++	0x241,
++	0x263,		/*19*/
++	0x287,		/*20*/
++	0x2AE,		/*21*/
++	0x2D6,		/*22*/
++	0x301,		/*23*/
++	0x32F,		/*24*/
++	0x35F,		/*25*/
++	0x392,		/*26*/
++	0x3C9,		/*27*/
++	0x402,		/*28*/
++	0x43F,		/*29*/
++	0x47F,		/*30*/
++	0x4C3,		/*31*/
++	0x50C,		/*32*/
++	0x558,		/*33*/
++	0x5A9,		/*34*/
++	0x5FF,		/*35*/
++	0x65A,		/*36*/
++	0x6BA,
++	0x720,
++	0x78C,
++	0x7FF,
++};
++
++u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
++	0x081, /* 0,  -12.0dB */
++	0x088, /* 1,  -11.5dB */
++	0x090, /* 2,  -11.0dB */
++	0x099, /* 3,  -10.5dB */
++	0x0A2, /* 4,  -10.0dB */
++	0x0AC, /* 5,  -9.5dB */
++	0x0B6, /* 6,  -9.0dB */
++	0x0C0, /* 7,  -8.5dB */
++	0x0CC, /* 8,  -8.0dB */
++	0x0D8, /* 9,  -7.5dB */
++	0x0E5, /* 10, -7.0dB */
++	0x0F2, /* 11, -6.5dB */
++	0x101, /* 12, -6.0dB */
++	0x110, /* 13, -5.5dB */
++	0x120, /* 14, -5.0dB */
++	0x131, /* 15, -4.5dB */
++	0x143, /* 16, -4.0dB */
++	0x156, /* 17, -3.5dB */
++	0x16A, /* 18, -3.0dB */
++	0x180, /* 19, -2.5dB */
++	0x197, /* 20, -2.0dB */
++	0x1AF, /* 21, -1.5dB */
++	0x1C8, /* 22, -1.0dB */
++	0x1E3, /* 23, -0.5dB */
++	0x200, /* 24, +0  dB */
++	0x21E, /* 25, +0.5dB */
++	0x23E, /* 26, +1.0dB */
++	0x261, /* 27, +1.5dB */
++	0x285, /* 28, +2.0dB */
++	0x2AB, /* 29, +2.5dB */
++	0x2D3, /* 30, +3.0dB */
++	0x2FE, /* 31, +3.5dB */
++	0x32B, /* 32, +4.0dB */
++	0x35C, /* 33, +4.5dB */
++	0x38E, /* 34, +5.0dB */
++	0x3C4, /* 35, +5.5dB */
++	0x3FE  /* 36, +6.0dB */
++};
++
++void
++odm_txpowertracking_init(
++	void		*dm_void
++)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B)))
++		return;
++#endif
++
++	odm_txpowertracking_thermal_meter_init(dm);
++}
++
++u8
++get_swing_index(
++	void		*dm_void
++)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	void		*adapter = dm->adapter;
++	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	u8			i = 0;
++	u32			bb_swing, table_value;
++
++	if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
++	    dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8188F || 
++	    dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || 
++	    dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8710B ||
++	    dm->support_ic_type == ODM_RTL8821) {
++		bb_swing = odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000);
++
++		for (i = 0; i < OFDM_TABLE_SIZE; i++) {
++			table_value = ofdm_swing_table_new[i];
++
++			if (table_value >= 0x100000)
++				table_value >>= 22;
++			if (bb_swing == table_value)
++				break;
++		}
++	} else {
++		bb_swing = PHY_GetTxBBSwing_8812A(adapter, hal_data->CurrentBandType, RF_PATH_A);
++
++		for (i = 0; i < TXSCALE_TABLE_SIZE; i++) {
++			table_value = tx_scaling_table_jaguar[i];
++
++			if (bb_swing == table_value)
++				break;
++		}
++	}
++
++	return i;
++}
++
++u8
++get_cck_swing_index(
++	void		*dm_void
++)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++
++	u8			i = 0;
++	u32			bb_cck_swing;
++
++	if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
++	    dm->support_ic_type == ODM_RTL8192E) {
++		bb_cck_swing = odm_read_1byte(dm, 0xa22);
++
++		for (i = 0; i < CCK_TABLE_SIZE; i++) {
++			if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
++				break;
++		}
++	} else if (dm->support_ic_type == ODM_RTL8703B) {
++		bb_cck_swing = odm_read_1byte(dm, 0xa22);
++
++		for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
++			if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
++				break;
++		}
++	}
++
++	return i;
++}
++
++
++void
++odm_txpowertracking_thermal_meter_init(
++	void		*dm_void
++)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	u8 default_swing_index = get_swing_index(dm);
++	u8 default_cck_swing_index = get_cck_swing_index(dm);
++	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
++	struct _hal_rf_ *rf = &dm->rf_table;
++	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void		*adapter = dm->adapter;
++	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	u8			p = 0;
++
++	if (*(dm->mp_mode) == false)
++		cali_info->txpowertrack_control = true;
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++#ifdef CONFIG_RTL8188E
++	{
++		cali_info->is_txpowertracking = true;
++		cali_info->tx_powercount = 0;
++		cali_info->is_txpowertracking_init = false;
++
++		if (*(dm->mp_mode) == false)
++			cali_info->txpowertrack_control = true;
++
++		MSG_8192C("dm txpowertrack_control = %d\n", cali_info->txpowertrack_control);
++	}
++#else
++	{
++		void		*adapter = dm->adapter;
++		HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++		struct dm_priv	*pdmpriv = &hal_data->dmpriv;
++
++		pdmpriv->is_txpowertracking = true;
++		pdmpriv->tx_powercount = 0;
++		pdmpriv->is_txpowertracking_init = false;
++
++		if (*(dm->mp_mode) == false)
++			pdmpriv->txpowertrack_control = true;
++
++		MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control);
++
++	}
++#endif
++#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++#ifdef RTL8188E_SUPPORT
++	{
++		cali_info->is_txpowertracking = true;
++		cali_info->tx_powercount = 0;
++		cali_info->is_txpowertracking_init = false;
++		cali_info->txpowertrack_control = true;
++	}
++#endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++#if (MP_DRIVER == 1)
++	cali_info->txpowertrack_control = false;
++#else
++	cali_info->txpowertrack_control = true;
++#endif
++#else
++	cali_info->txpowertrack_control = true;
++#endif
++
++	cali_info->thermal_value	= hal_data->eeprom_thermal_meter;
++	cali_info->thermal_value_iqk	= hal_data->eeprom_thermal_meter;
++	cali_info->thermal_value_lck	= hal_data->eeprom_thermal_meter;
++
++#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8822C) {
++		cali_info->thermal_value_path[RF_PATH_A] = tssi->thermal[RF_PATH_A];
++		cali_info->thermal_value_path[RF_PATH_B] = tssi->thermal[RF_PATH_B];
++		cali_info->thermal_value_iqk = tssi->thermal[RF_PATH_A];
++		cali_info->thermal_value_lck = tssi->thermal[RF_PATH_A];
++	}
++
++	if (dm->support_ic_type == ODM_RTL8814B) {
++		cali_info->thermal_value_path[RF_PATH_A] = tssi->thermal[RF_PATH_A];
++		cali_info->thermal_value_path[RF_PATH_B] = tssi->thermal[RF_PATH_B];
++		cali_info->thermal_value_path[RF_PATH_C] = tssi->thermal[RF_PATH_C];
++		cali_info->thermal_value_path[RF_PATH_D] = tssi->thermal[RF_PATH_D];
++		cali_info->thermal_value_iqk = tssi->thermal[RF_PATH_A];
++		cali_info->thermal_value_lck = tssi->thermal[RF_PATH_A];
++	}
++#endif
++
++	if (cali_info->default_bb_swing_index_flag != true) {
++		/*The index of "0 dB" in SwingTable.*/
++		if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
++		    dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8703B ||
++		    dm->support_ic_type == ODM_RTL8821) {
++			cali_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index;
++			cali_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index;
++		} else if (dm->support_ic_type == ODM_RTL8188F) {          /*add by Mingzhi.Guo  2015-03-23*/
++			cali_info->default_ofdm_index = 28;							/*OFDM: -1dB*/
++			cali_info->default_cck_index = 20;							/*CCK:-6dB*/
++		} else if (dm->support_ic_type == ODM_RTL8723D) {			 /*add by zhaohe  2015-10-27*/
++			cali_info->default_ofdm_index = 28;						 	   /*OFDM: -1dB*/
++			cali_info->default_cck_index = 28;							/*CCK:   -6dB*/
++			/* JJ ADD 20161014 */
++		} else if (dm->support_ic_type == ODM_RTL8710B) {			
++			cali_info->default_ofdm_index = 28;					/*OFDM: -1dB*/
++			cali_info->default_cck_index = 28;					/*CCK:   -6dB*/
++		/*Winnita add 20170828*/
++		} else if (dm->support_ic_type == ODM_RTL8192F) {			
++			cali_info->default_ofdm_index = 30;					/*OFDM: 0dB*/
++			cali_info->default_cck_index = 28;					/*CCK:   -6dB*/
++		} else {
++			cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
++			cali_info->default_cck_index = 24;
++		}
++		cali_info->default_bb_swing_index_flag = true;
++	}
++
++	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
++	cali_info->CCK_index = cali_info->default_cck_index;
++
++	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
++		cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
++		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
++		cali_info->delta_power_index[p] = 0;
++		cali_info->delta_power_index_last[p] = 0;
++		cali_info->power_index_offset[p] = 0;
++		cali_info->kfree_offset[p] = 0;
++	}
++	cali_info->modify_tx_agc_value_ofdm = 0;
++	cali_info->modify_tx_agc_value_cck = 0;
++	cali_info->tm_trigger = 0;
++}
++
++
++void
++odm_txpowertracking_check(
++	void		*dm_void
++)
++{
++
++#if 0
++	/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
++	/*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
++	/* HW dynamic mechanism. */
++#endif
++
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	switch	(dm->support_platform) {
++	case	ODM_WIN:
++		odm_txpowertracking_check_mp(dm);
++		break;
++
++	case	ODM_CE:
++		odm_txpowertracking_check_ce(dm);
++		break;
++
++	case	ODM_AP:
++		odm_txpowertracking_check_ap(dm);
++		break;
++
++	default:
++		break;
++	}
++
++}
++
++void
++odm_txpowertracking_check_ce(
++	void		*dm_void
++)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_				*rf = &(dm->rf_table);
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	void	*adapter = dm->adapter;
++#if ((RTL8188F_SUPPORT == 1))
++	rtl8192c_odm_check_txpowertracking(adapter);
++#endif
++
++#if (RTL8188E_SUPPORT == 1)
++
++	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
++		return;
++
++	if (!cali_info->tm_trigger) {
++		odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
++		/*DBG_8192C("Trigger 92C Thermal Meter!!\n");*/
++
++		cali_info->tm_trigger = 1;
++		return;
++
++	} else {
++		/*DBG_8192C("Schedule TxPowerTracking direct call!!\n");*/
++		odm_txpowertracking_callback_thermal_meter_8188e(adapter);
++		cali_info->tm_trigger = 0;
++	}
++#endif
++#endif
++}
++
++void
++odm_txpowertracking_check_mp(
++	void		*dm_void
++)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void	*adapter = dm->adapter;
++
++	if (*dm->is_fcs_mode_enable)
++		return;
++
++	if (odm_check_power_status(dm) == false) {
++		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("check_pow_status return false\n"));
++		return;
++	}
++
++	if (IS_HARDWARE_TYPE_8821B(adapter)) /* TODO: Don't Do PowerTracking*/
++		return;
++
++	odm_txpowertracking_thermal_meter_check(adapter);
++
++
++#endif
++
++}
++
++
++void
++odm_txpowertracking_check_ap(
++	void		*dm_void
++)
++{
++	return;
++
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++
++void
++odm_txpowertracking_direct_call(
++	void		*adapter
++)
++{
++	HAL_DATA_TYPE		*hal_data	= GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct			*dm = &hal_data->DM_OutSrc;
++
++	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B)) {
++#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
++		odm_txpowertracking_new_callback_thermal_meter(dm);
++#endif
++	} else
++		odm_txpowertracking_callback_thermal_meter(adapter);
++}
++
++void
++odm_txpowertracking_thermal_meter_check(
++	void		*adapter
++)
++{
++	static u8			tm_trigger = 0;
++	HAL_DATA_TYPE			*pHalData = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct	*dm = &(pHalData->DM_OutSrc);
++	struct _hal_rf_			*rf = &(dm->rf_table);
++	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
++
++	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) {
++		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
++			("===>odm_txpowertracking_thermal_meter_check(),mgnt_info->is_txpowertracking is false, return!!\n"));
++		return;
++	}
++
++	if (!tm_trigger) {
++		if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8192E(adapter) || IS_HARDWARE_TYPE_8192F(adapter)
++		    ||IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8703B(adapter)
++		    || IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8821C(adapter) || IS_HARDWARE_TYPE_8710B(adapter)
++		    )/* JJ ADD 20161014 */
++			PHY_SetRFReg(adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
++		else if (IS_HARDWARE_TYPE_8822C(adapter)) {
++			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
++			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);
++			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
++			
++			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
++			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);
++			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
++		} else if (IS_HARDWARE_TYPE_8814B(adapter)) {
++			odm_set_rf_reg(dm, RF_PATH_A, 0x42, BIT(17), 0x1);
++			odm_set_rf_reg(dm, RF_PATH_B, 0x42, BIT(17), 0x1);
++			odm_set_rf_reg(dm, RF_PATH_C, 0x42, BIT(17), 0x1);
++			odm_set_rf_reg(dm, RF_PATH_D, 0x42, BIT(17), 0x1);
++		} else
++			PHY_SetRFReg(adapter, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
++
++		if (dm->support_ic_type & ODM_RTL8814B) {
++			ODM_delay_us(300);
++			odm_txpowertracking_direct_call(adapter);
++			tssi->thermal_trigger = 1;
++		}
++
++		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Trigger Thermal Meter!!\n"));
++
++		tm_trigger = 1;
++		return;
++	} else {
++		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Schedule TxPowerTracking direct call!!\n"));
++		odm_txpowertracking_direct_call(adapter);
++
++		if (dm->support_ic_type & ODM_RTL8814B)
++			tssi->thermal_trigger = 0;
++
++		tm_trigger = 0;
++	}
++}
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_win.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_win.h
+new file mode 100644
+index 000000000..240254884
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_powertracking_win.h
+@@ -0,0 +1,305 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_POWERTRACKING_H__
++#define __HALRF_POWERTRACKING_H__
++
++#define	DPK_DELTA_MAPPING_NUM	13
++#define	index_mapping_HP_NUM	15
++#define	TXSCALE_TABLE_SIZE		37
++#define	OFDM_TABLE_SIZE			43
++#define	CCK_TABLE_SIZE			33
++#define	CCK_TABLE_SIZE_8723D    41
++#define	TXPWR_TRACK_TABLE_SIZE	30
++#define	DELTA_SWINGIDX_SIZE     30
++#define	DELTA_SWINTSSI_SIZE     61
++#define	BAND_NUM				3
++#define	MAX_RF_PATH	4
++#define	CCK_TABLE_SIZE_88F	21
++/* JJ ADD 20161014 */
++#define	CCK_TABLE_SIZE_8710B   41
++#define	CCK_TABLE_SIZE_8192F   41
++
++
++#define	dm_check_txpowertracking	odm_txpowertracking_check
++
++#define IQK_MATRIX_SETTINGS_NUM	(14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
++#define	AVG_THERMAL_NUM		8
++#define	iqk_matrix_reg_num	8
++#define	IQK_MAC_REG_NUM		4
++#define	IQK_ADDA_REG_NUM		16
++
++#define	IQK_BB_REG_NUM		9
++
++
++extern	u32 ofdm_swing_table[OFDM_TABLE_SIZE];
++extern	u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
++extern	u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
++
++extern	u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
++extern	u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
++extern	u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
++extern	u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
++extern	u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
++extern	u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
++extern	u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
++/* JJ ADD 20161014 */
++extern	u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
++extern	u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
++
++extern  u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
++
++/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
++static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};
++static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11};
++
++void
++odm_txpowertracking_check(
++	void		*dm_void
++);
++
++void
++odm_txpowertracking_check_ap(
++	void		*dm_void
++);
++
++void
++odm_txpowertracking_thermal_meter_init(
++	void		*dm_void
++);
++
++void
++odm_txpowertracking_init(
++	void		*dm_void
++);
++
++void
++odm_txpowertracking_check_mp(
++	void		*dm_void
++);
++
++
++void
++odm_txpowertracking_check_ce(
++	void		*dm_void
++);
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++
++
++void
++odm_txpowertracking_thermal_meter_check(
++	void		*adapter
++);
++
++#endif
++
++struct iqk_matrix_regs_setting {
++	boolean	is_iqk_done;
++	s32		value[3][iqk_matrix_reg_num];
++	boolean	is_bw_iqk_result_saved[3];
++};
++
++struct dm_rf_calibration_struct {
++	/* for tx power tracking */
++
++	u32	rega24; /* for TempCCK */
++	s32	rege94;
++	s32	rege9c;
++	s32	regeb4;
++	s32	regebc;
++	/* u8 is_txpowertracking; */
++	u8	tx_powercount;
++	boolean is_txpowertracking_init;
++	boolean is_txpowertracking;
++	u8  	txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
++	u8	tm_trigger;
++	u8  	internal_pa_5g[2];	/* pathA / pathB */
++
++	u8  	thermal_meter[2];    /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
++	u8	thermal_value;
++	u8	thermal_value_path[MAX_RF_PATH];
++	u8	thermal_value_lck;
++	u8	thermal_value_iqk;
++	u8	thermal_value_dpk;
++	s8	thermal_value_delta; /* delta of thermal_value and efuse thermal */
++	u8	thermal_value_avg[AVG_THERMAL_NUM];
++	u8	thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM];
++	u8	thermal_value_avg_index;
++	u8	thermal_value_avg_index_path[MAX_RF_PATH];
++	u8	thermal_value_rx_gain;
++
++
++	boolean	is_reloadtxpowerindex;
++	u8	is_rf_pi_enable;
++	u32 	txpowertracking_callback_cnt; /* cosa add for debug */
++
++
++	/* ------------------------- Tx power Tracking ------------------------- */
++	u8	is_cck_in_ch14;
++	u8	CCK_index;
++	u8	OFDM_index[MAX_RF_PATH];
++	s8	power_index_offset[MAX_RF_PATH];
++	s8	delta_power_index[MAX_RF_PATH];
++	s8	delta_power_index_last[MAX_RF_PATH];
++	boolean is_tx_power_changed;
++	s8	xtal_offset;
++	s8	xtal_offset_last;
++
++	struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
++	u8	delta_lck;
++	s8  bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
++	u8  delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
++	u8  delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
++	s8  delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
++	s8  delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
++	u8  delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
++
++	u8			bb_swing_idx_ofdm[MAX_RF_PATH];
++	u8			bb_swing_idx_ofdm_current;
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	u8			bb_swing_idx_ofdm_base[MAX_RF_PATH];
++#else
++	u8			bb_swing_idx_ofdm_base;
++#endif
++	boolean		default_bb_swing_index_flag;
++	boolean			bb_swing_flag_ofdm;
++	u8			bb_swing_idx_cck;
++	u8			bb_swing_idx_cck_current;
++	u8			bb_swing_idx_cck_base;
++	u8			default_ofdm_index;
++	u8			default_cck_index;
++	boolean			bb_swing_flag_cck;
++
++	s8			absolute_ofdm_swing_idx[MAX_RF_PATH];
++	s8			remnant_ofdm_swing_idx[MAX_RF_PATH];
++	s8			absolute_cck_swing_idx[MAX_RF_PATH];
++	s8			remnant_cck_swing_idx;
++	s8			modify_tx_agc_value;       /*Remnat compensate value at tx_agc */
++	boolean			modify_tx_agc_flag_path_a;
++	boolean			modify_tx_agc_flag_path_b;
++	boolean			modify_tx_agc_flag_path_c;
++	boolean			modify_tx_agc_flag_path_d;
++	boolean			modify_tx_agc_flag_path_a_cck;
++	boolean			modify_tx_agc_flag_path_b_cck;
++
++	s8			kfree_offset[MAX_RF_PATH];
++
++	/* -------------------------------------------------------------------- */
++
++	/* for IQK */
++	u32	regc04;
++	u32	reg874;
++	u32	regc08;
++	u32	regb68;
++	u32	regb6c;
++	u32	reg870;
++	u32	reg860;
++	u32	reg864;
++
++	boolean	is_iqk_initialized;
++	boolean is_lck_in_progress;
++	boolean	is_antenna_detected;
++	boolean	is_need_iqk;
++	boolean	is_iqk_in_progress;
++	boolean	is_iqk_pa_off;
++	u8	delta_iqk;
++	u32	ADDA_backup[IQK_ADDA_REG_NUM];
++	u32	IQK_MAC_backup[IQK_MAC_REG_NUM];
++	u32	IQK_BB_backup_recover[9];
++	u32	IQK_BB_backup[IQK_BB_REG_NUM];
++	u32	tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
++	u32	rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */
++	u32	tx_iqc_8703b[3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
++	u32	rx_iqc_8703b[2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
++	u32	tx_iqc_8723d[2][3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
++	u32	rx_iqc_8723d[2][2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
++	/* JJ ADD 20161014 */
++	u32	tx_iqc_8710b[2][3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
++	u32	rx_iqc_8710b[2][2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
++
++	u64	iqk_start_time;
++	u64	iqk_total_progressing_time;
++	u64	iqk_progressing_time;
++	u64	lck_progressing_time;
++	u32  lok_result;
++	u8	iqk_step;
++	u8	kcount;
++	u8	retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
++	boolean	is_mp_mode;
++
++	/* for APK */
++	u32 	ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
++	u8	is_ap_kdone;
++	u8	is_apk_thermal_meter_ignore;
++
++	/* DPK */
++	boolean is_dpk_fail;
++	u8	is_dp_done;
++	u8	is_dp_path_aok;
++	u8	is_dp_path_bok;
++
++	u32	tx_lok[2];
++	u32  dpk_tx_agc;
++	s32  dpk_gain;
++	u32  dpk_thermal[4];
++
++	s8 modify_tx_agc_value_ofdm;
++	s8 modify_tx_agc_value_cck;
++
++	/*Add by Yuchen for Kfree Phydm*/
++	u8			reg_rf_kfree_enable;	/*for registry*/
++	u8			rf_kfree_enable;		/*for efuse enable check*/
++};
++
++
++
++
++#endif	/*#ifndef __HALRF_POWER_TRACKING_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_psd.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_psd.c
+new file mode 100644
+index 000000000..bab7d09ac
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_psd.c
+@@ -0,0 +1,531 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/*@===========================================================
++ * include files
++ *============================================================
++ */
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++u64 _sqrt(u64 x)
++{
++	u64 i = 0;
++	u64 j = (x >> 1) + 1;
++
++	while (i <= j) {
++		u64 mid = (i + j) >> 1;
++
++		u64 sq = mid * mid;
++
++		if (sq == x)
++			return mid;
++		else if (sq < x)
++			i = mid + 1;
++		else
++			j = mid - 1;
++	}
++
++	return j;
++}
++
++u32 halrf_get_psd_data(
++	struct dm_struct *dm,
++	u32 point)
++{
++	struct _hal_rf_ *rf = &(dm->rf_table);
++	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
++	u32 psd_val = 0, psd_reg, psd_report, psd_point, psd_start, i, delay_time = 0;
++
++#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
++	if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) {
++		if (psd->average == 0)
++			delay_time = 100;
++		else
++			delay_time = 0;
++	}
++#endif
++#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
++	if (dm->support_interface == ODM_ITRF_PCIE) {
++		if (psd->average == 0)
++			delay_time = 1000;
++		else
++			delay_time = 100;
++	}
++#endif
++
++	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
++		psd_reg = R_0x910;
++		psd_report = R_0xf44;
++	} else {
++		psd_reg = R_0x808;
++		psd_report = R_0x8b4;
++	}
++
++	if (dm->support_ic_type & ODM_RTL8710B) {
++		psd_point = 0xeffffc00;
++		psd_start = 0x10000000;
++	} else {
++		psd_point = 0xffbffc00;
++		psd_start = 0x00400000;
++	}
++
++	psd_val = odm_get_bb_reg(dm, psd_reg, MASKDWORD);
++
++	psd_val &= psd_point;
++	psd_val |= point;
++
++	odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);
++
++	psd_val |= psd_start;
++
++	odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);
++
++	for (i = 0; i < delay_time; i++)
++		ODM_delay_us(1);
++
++	psd_val = odm_get_bb_reg(dm, psd_report, MASKDWORD);
++
++	if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8710B)) {
++		psd_val &= MASKL3BYTES;
++		psd_val = psd_val / 32;
++	} else {
++		psd_val &= MASKLWORD;
++	}
++
++	return psd_val;
++}
++
++void halrf_psd(
++	struct dm_struct *dm,
++	u32 point,
++	u32 start_point,
++	u32 stop_point,
++	u32 average)
++{
++	struct _hal_rf_ *rf = &(dm->rf_table);
++	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
++
++	u32 i = 0, j = 0, k = 0;
++	u32 psd_reg, avg_org, point_temp, average_tmp, mode;
++	u64 data_tatal = 0, data_temp[64] = {0};
++
++	psd->buf_size = 256;
++
++	mode = average >> 16;
++	
++	if (mode == 2)
++		average_tmp = 1;
++	else
++		average_tmp = average & 0xffff;
++
++	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
++		psd_reg = R_0x910;
++	else
++		psd_reg = R_0x808;
++
++#if 0
++	dbg_print("[PSD]point=%d, start_point=%d, stop_point=%d, average=%d, average_tmp=%d, buf_size=%d\n",
++		point, start_point, stop_point, average, average_tmp, psd->buf_size);
++#endif
++
++	for (i = 0; i < psd->buf_size; i++)
++		psd->psd_data[i] = 0;
++
++	if (dm->support_ic_type & ODM_RTL8710B)
++		avg_org = odm_get_bb_reg(dm, psd_reg, 0x30000);
++	else
++		avg_org = odm_get_bb_reg(dm, psd_reg, 0x3000);
++
++	if (mode == 1) {
++		if (dm->support_ic_type & ODM_RTL8710B)
++			odm_set_bb_reg(dm, psd_reg, 0x30000, 0x1);
++		else
++			odm_set_bb_reg(dm, psd_reg, 0x3000, 0x1);
++	}
++
++#if 0
++	if (avg_temp == 0)
++		avg = 1;
++	else if (avg_temp == 1)
++		avg = 8;
++	else if (avg_temp == 2)
++		avg = 16;
++	else if (avg_temp == 3)
++		avg = 32;
++#endif
++
++	i = start_point;
++	while (i < stop_point) {
++		data_tatal = 0;
++
++		if (i >= point)
++			point_temp = i - point;
++		else
++			point_temp = i;
++
++		for (k = 0; k < average_tmp; k++) {
++			data_temp[k] = halrf_get_psd_data(dm, point_temp);
++			data_tatal = data_tatal + (data_temp[k] * data_temp[k]);
++
++#if 0
++			if ((k % 20) == 0)
++				dbg_print("\n ");
++
++			dbg_print("0x%x ", data_temp[k]);
++#endif
++		}
++#if 0
++		/*dbg_print("\n");*/
++#endif
++
++		data_tatal = phydm_division64((data_tatal * 100), average_tmp);
++		psd->psd_data[j] = (u32)_sqrt(data_tatal);
++
++		i++;
++		j++;
++	}
++
++#if 0
++	for (i = 0; i < psd->buf_size; i++) {
++		if ((i % 20) == 0)
++			dbg_print("\n ");
++
++		dbg_print("0x%x ", psd->psd_data[i]);
++	}
++	dbg_print("\n\n");
++#endif
++
++	if (dm->support_ic_type & ODM_RTL8710B)
++		odm_set_bb_reg(dm, psd_reg, 0x30000, avg_org);
++	else
++		odm_set_bb_reg(dm, psd_reg, 0x3000, avg_org);
++}
++
++void backup_bb_register(struct dm_struct *dm, u32 *bb_backup, u32 *backup_bb_reg, u32 counter)
++{
++	u32 i ;
++
++	for (i = 0; i < counter; i++)
++		bb_backup[i] = odm_get_bb_reg(dm, backup_bb_reg[i], MASKDWORD);
++}
++
++void restore_bb_register(struct dm_struct *dm, u32 *bb_backup, u32 *backup_bb_reg, u32 counter)
++{
++	u32 i ;
++
++	for (i = 0; i < counter; i++)
++		odm_set_bb_reg(dm, backup_bb_reg[i], MASKDWORD, bb_backup[i]);
++}
++
++
++
++void _halrf_psd_iqk_init(struct dm_struct *dm)
++{
++	odm_set_bb_reg(dm, 0x1b04, MASKDWORD, 0x0);
++	odm_set_bb_reg(dm, 0x1b08, MASKDWORD, 0x80);
++	odm_set_bb_reg(dm, 0x1b0c, 0xc00, 0x3);
++	odm_set_bb_reg(dm, 0x1b14, MASKDWORD, 0x0);
++	odm_set_bb_reg(dm, 0x1b18, BIT(0), 0x1);
++
++	if (dm->support_ic_type & ODM_RTL8197G)
++		odm_set_bb_reg(dm, 0x1b20, MASKDWORD, 0x00040008);
++	if (dm->support_ic_type & ODM_RTL8198F)
++		odm_set_bb_reg(dm, 0x1b20, MASKDWORD, 0x00000000);
++
++	if (dm->support_ic_type & (ODM_RTL8197G | ODM_RTL8198F)) {
++		odm_set_bb_reg(dm, 0x1b24, MASKDWORD, 0x00030000);
++		odm_set_bb_reg(dm, 0x1b28, MASKDWORD, 0x00000000);
++		odm_set_bb_reg(dm, 0x1b2c, MASKDWORD, 0x00180018);
++		odm_set_bb_reg(dm, 0x1b30, MASKDWORD, 0x20000000);
++		/*odm_set_bb_reg(dm, 0x1b38, MASKDWORD, 0x20000000);*/
++		/*odm_set_bb_reg(dm, 0x1b3c, MASKDWORD, 0x20000000);*/
++	}
++
++	odm_set_bb_reg(dm, 0x1b1c, 0xfff, 0xd21);
++	odm_set_bb_reg(dm, 0x1b1c, 0xfff00000, 0x821);
++	odm_set_bb_reg(dm, 0x1b28, MASKDWORD, 0x0);
++	odm_set_bb_reg(dm, 0x1bcc, 0x3f, 0x3f);	
++}
++
++
++u32 halrf_get_iqk_psd_data(
++	struct dm_struct *dm,
++	u32 point)
++{
++	struct _hal_rf_ *rf = &(dm->rf_table);
++	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
++	u32 psd_val, psd_val1, psd_val2, psd_point, i, delay_time = 0;
++
++#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
++	if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) {
++		if (dm->support_ic_type & ODM_RTL8822C)
++			delay_time = 1000;
++		else
++			delay_time = 0;
++	}
++#endif
++#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
++	if (dm->support_interface == ODM_ITRF_PCIE) {
++		if (dm->support_ic_type & ODM_RTL8822C)
++			delay_time = 1000;
++		else
++			delay_time = 150;
++	}
++#endif
++	psd_point = odm_get_bb_reg(dm, R_0x1b2c, MASKDWORD);
++
++	psd_point &= 0xF000FFFF;
++
++	point &= 0xFFF;
++
++	psd_point = psd_point | (point << 16);
++
++	odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, psd_point);
++
++	odm_set_bb_reg(dm, R_0x1b34, BIT(0), 0x1);
++
++	odm_set_bb_reg(dm, R_0x1b34, BIT(0), 0x0);
++
++	for (i = 0; i < delay_time; i++)
++		ODM_delay_us(1);
++
++	if (dm->support_ic_type & (ODM_RTL8197G | ODM_RTL8198F)) {
++		if (dm->support_ic_type & ODM_RTL8197G)
++			odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x001a0001);
++		else
++			odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001);
++
++		psd_val1 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
++
++		psd_val1 = (psd_val1 & 0x001f0000) >> 16;
++
++		if (dm->support_ic_type & ODM_RTL8197G)
++			odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x001b0001);
++		else
++			odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x002e0001);
++
++		psd_val2 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
++
++		psd_val = (psd_val1 << 27) + (psd_val2 >> 5);
++	} else {
++		odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001);
++
++		psd_val1 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
++
++		psd_val1 = (psd_val1 & 0x07FF0000) >> 16;
++
++		odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x002e0001);
++
++		psd_val2 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
++
++		psd_val = (psd_val1 << 21) + (psd_val2 >> 11);
++	}
++
++	return psd_val;
++}
++
++void halrf_iqk_psd(
++	struct dm_struct *dm,
++	u32 point,
++	u32 start_point,
++	u32 stop_point,
++	u32 average)
++{
++	struct _hal_rf_ *rf = &(dm->rf_table);
++	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
++
++	u32 i = 0, j = 0, k = 0;
++	u32 psd_reg, avg_org, point_temp, average_tmp = 32, mode, reg_tmp = 5;
++	u64 data_tatal = 0, data_temp[64] = {0};
++	s32 s_point_tmp;
++
++	psd->buf_size = 256;
++
++	mode = average >> 16;
++
++	if (mode == 2) {
++		if (dm->support_ic_type & ODM_RTL8822C)
++			average_tmp = 1;
++		else {
++			reg_tmp = odm_get_bb_reg(dm, R_0x1b1c, 0x000e0000);
++			if (reg_tmp == 0)
++				average_tmp = 1;
++			else if (reg_tmp == 3)
++				average_tmp = 8;
++			else if (reg_tmp == 4)
++				average_tmp = 16;
++			else if (reg_tmp == 5)
++				average_tmp = 32;
++			odm_set_bb_reg(dm, R_0x1b1c, 0x000e0000, 0x0);
++		}
++	} else {
++		reg_tmp = odm_get_bb_reg(dm, R_0x1b1c, 0x000e0000);
++		if (reg_tmp == 0)
++			average_tmp = 1;
++		else if (reg_tmp == 3)
++			average_tmp = 8;
++		else if (reg_tmp == 4)
++			average_tmp = 16;
++		else if (reg_tmp == 5)
++			average_tmp = 32;
++		odm_set_bb_reg(dm, R_0x1b1c, 0x000e0000, 0x0);
++	}
++
++#if 0
++	DbgPrint("[PSD]point=%d, start_point=%d, stop_point=%d, average=0x%x, average_tmp=%d, buf_size=%d, mode=%d\n",
++		point, start_point, stop_point, average, average_tmp, psd->buf_size, mode);
++#endif
++
++	for (i = 0; i < psd->buf_size; i++)
++		psd->psd_data[i] = 0;
++
++	i = start_point;
++	while (i < stop_point) {
++		data_tatal = 0;
++
++		if (i >= point)
++			point_temp = i - point;
++		else
++		{
++			if (dm->support_ic_type & ODM_RTL8814B)
++			{
++				s_point_tmp = i - point - 1;
++				point_temp = s_point_tmp & 0xfff;
++			}
++			else
++				point_temp = i;
++		}
++
++		for (k = 0; k < average_tmp; k++) {
++			data_temp[k] = halrf_get_iqk_psd_data(dm, point_temp);
++			/*data_tatal = data_tatal + (data_temp[k] * data_temp[k]);*/
++			data_tatal = data_tatal + data_temp[k];
++
++#if 0
++			if ((k % 20) == 0)
++				DbgPrint("\n ");
++
++			DbgPrint("0x%x ", data_temp[k]);
++#endif
++		}
++
++		data_tatal = phydm_division64((data_tatal * 10), average_tmp);
++		psd->psd_data[j] = (u32)data_tatal;
++
++		i++;
++		j++;
++	}
++
++	if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8198F | ODM_RTL8197G))
++		odm_set_bb_reg(dm, R_0x1b1c, 0x000e0000, reg_tmp);
++
++#if 0
++	DbgPrint("\n [iqk psd]psd result:\n");
++
++	for (i = 0; i < psd->buf_size; i++) {
++		if ((i % 20) == 0)
++			DbgPrint("\n ");
++
++		DbgPrint("0x%x ", psd->psd_data[i]);
++	}
++	DbgPrint("\n\n");
++#endif
++}
++
++
++u32
++halrf_psd_init(
++	void *dm_void)
++{
++	enum rt_status ret_status = RT_STATUS_SUCCESS;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &(dm->rf_table);
++	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
++
++#if 0
++	u32 bb_backup[12];
++	u32 backup_bb_reg[12] = {0x1b04, 0x1b08, 0x1b0c, 0x1b14, 0x1b18,
++				0x1b1c, 0x1b28, 0x1bcc, 0x1b2c, 0x1b34,
++				0x1bd4, 0x1bfc};
++#endif
++
++	if (psd->psd_progress) {
++		ret_status = RT_STATUS_PENDING;
++	} else {
++		psd->psd_progress = 1;
++		if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8198F | ODM_RTL8197G)) {
++			/*backup_bb_register(dm, bb_backup, backup_bb_reg, 12);*/
++			_halrf_psd_iqk_init(dm);
++			halrf_iqk_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
++			/*restore_bb_register(dm, bb_backup, backup_bb_reg, 12);*/
++		} else
++			halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
++		psd->psd_progress = 0;
++	}
++	return ret_status;
++}
++
++u32
++halrf_psd_query(
++	void *dm_void,
++	u32 *outbuf,
++	u32 buf_size)
++{
++	enum rt_status ret_status = RT_STATUS_SUCCESS;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &(dm->rf_table);
++	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
++
++	if (psd->psd_progress)
++		ret_status = RT_STATUS_PENDING;
++	else
++		odm_move_memory(dm, outbuf, psd->psd_data,
++				sizeof(u32) * psd->buf_size);
++
++	return ret_status;
++}
++
++u32
++halrf_psd_init_query(
++	void *dm_void,
++	u32 *outbuf,
++	u32 point,
++	u32 start_point,
++	u32 stop_point,
++	u32 average,
++	u32 buf_size)
++{
++	enum rt_status ret_status = RT_STATUS_SUCCESS;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _hal_rf_ *rf = &(dm->rf_table);
++	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
++
++	psd->point = point;
++	psd->start_point = start_point;
++	psd->stop_point = stop_point;
++	psd->average = average;
++
++	if (psd->psd_progress) {
++		ret_status = RT_STATUS_PENDING;
++	} else {
++		psd->psd_progress = 1;
++		halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
++		odm_move_memory(dm, outbuf, psd->psd_data, 0x400);
++		psd->psd_progress = 0;
++	}
++
++	return ret_status;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_psd.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_psd.h
+new file mode 100644
+index 000000000..f4a76746d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_psd.h
+@@ -0,0 +1,50 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_PSD_H__
++#define __HALRF_PSD_H__
++
++
++struct _halrf_psd_data {
++	u32 point;
++	u32 start_point;
++	u32 stop_point;
++	u32 average;
++	u32 buf_size;
++	u32 psd_data[256];
++	u32 psd_progress;
++};
++
++u32
++halrf_psd_init(
++	void *dm_void);
++
++u32
++halrf_psd_query(
++	void *dm_void,
++	u32 *outbuf,
++	u32 buf_size);
++
++u32
++halrf_psd_init_query(
++	void *dm_void,
++	u32 *outbuf,
++	u32 point,
++	u32 start_point,
++	u32 stop_point,
++	u32 average,
++	u32 buf_size);
++
++#endif /*#__HALRF_PSD_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_txgapcal.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_txgapcal.c
+new file mode 100644
+index 000000000..0cc44974b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_txgapcal.c
+@@ -0,0 +1,300 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++void odm_bub_sort(u32 *data, u32 n)
++{
++	int i, j, temp, sp;
++
++	for (i = n - 1; i >= 0; i--) {
++		sp = 1;
++		for (j = 0; j < i; j++) {
++			if (data[j] < data[j + 1]) {
++				temp = data[j];
++				data[j] = data[j + 1];
++				data[j + 1] = temp;
++				sp = 0;
++			}
++		}
++		if (sp == 1)
++			break;
++	}
++}
++
++#if (RTL8197F_SUPPORT == 1)
++
++u4Byte
++odm_tx_gain_gap_psd_8197f(
++	void *dm_void,
++	u1Byte rf_path,
++	u4Byte rf56)
++{
++	PDM_ODM_T dm = (PDM_ODM_T)dm_void;
++
++	u1Byte i, j;
++	u4Byte psd_vaule[5], psd_avg_time = 5, psd_vaule_temp;
++
++	u4Byte iqk_ctl_addr[2][6] = {{0xe30, 0xe34, 0xe50, 0xe54, 0xe38, 0xe3c},
++				     {0xe50, 0xe54, 0xe30, 0xe34, 0xe58, 0xe5c}};
++
++	u4Byte psd_finish_bit[2] = {0x04000000, 0x20000000};
++	u4Byte psd_fail_bit[2] = {0x08000000, 0x40000000};
++
++	u4Byte psd_cntl_value[2][2] = {{0x38008c1c, 0x10008c1c},
++				       {0x38008c2c, 0x10008c2c}};
++
++	u4Byte psd_report_addr[2] = {0xea0, 0xec0};
++
++	odm_set_rf_reg(dm, rf_path, RF_0xdf, bRFRegOffsetMask, 0x00e02);
++
++	ODM_delay_us(100);
++
++	odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x0);
++
++	odm_set_rf_reg(dm, rf_path, RF_0x56, 0xfff, rf56);
++	while (rf56 != (odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff)))
++		odm_set_rf_reg(dm, rf_path, RF_0x56, 0xfff, rf56);
++
++	odm_set_bb_reg(dm, R_0xd94, 0xffffffff, 0x44FFBB44);
++	odm_set_bb_reg(dm, R_0xe70, 0xffffffff, 0x00400040);
++	odm_set_bb_reg(dm, R_0xc04, 0xffffffff, 0x6f005403);
++	odm_set_bb_reg(dm, R_0xc08, 0xffffffff, 0x000804e4);
++	odm_set_bb_reg(dm, R_0x874, 0xffffffff, 0x04203400);
++	odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x80800000);
++
++	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][0], 0xffffffff, psd_cntl_value[rf_path][0]);
++	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][1], 0xffffffff, psd_cntl_value[rf_path][1]);
++	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][2], 0xffffffff, psd_cntl_value[rf_path][0]);
++	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][3], 0xffffffff, psd_cntl_value[rf_path][0]);
++	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][4], 0xffffffff, 0x8215001F);
++	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][5], 0xffffffff, 0x2805001F);
++
++	odm_set_bb_reg(dm, R_0xe40, 0xffffffff, 0x81007C00);
++	odm_set_bb_reg(dm, R_0xe44, 0xffffffff, 0x81004800);
++	odm_set_bb_reg(dm, R_0xe4c, 0xffffffff, 0x0046a8d0);
++
++	for (i = 0; i < psd_avg_time; i++) {
++		for (j = 0; j < 1000; j++) {
++			odm_set_bb_reg(dm, R_0xe48, 0xffffffff, 0xfa005800);
++			odm_set_bb_reg(dm, R_0xe48, 0xffffffff, 0xf8005800);
++
++			while (!odm_get_bb_reg(dm, R_0xeac, psd_finish_bit[rf_path]))
++				; /*wait finish bit*/
++
++			if (!odm_get_bb_reg(dm, R_0xeac, psd_fail_bit[rf_path])) { /*check fail bit*/
++
++				psd_vaule[i] = odm_get_bb_reg(dm, psd_report_addr[rf_path], 0xffffffff);
++
++				if (psd_vaule[i] > 0xffff)
++					break;
++			}
++		}
++
++		RF_DBG(dm, DBG_RF_IQK,
++		       "[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x time=%d psd_vaule=0x%x\n",
++		       odm_get_rf_reg(dm, rf_path, RF_0x0, 0xff), rf56,
++		       odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff), j,
++		       psd_vaule[i]);
++	}
++
++	odm_bub_sort(psd_vaule, psd_avg_time);
++
++	psd_vaule_temp = psd_vaule[(UINT)(psd_avg_time / 2)];
++
++	odm_set_bb_reg(dm, R_0xd94, 0xffffffff, 0x44BBBB44);
++	odm_set_bb_reg(dm, R_0xe70, 0xffffffff, 0x80408040);
++	odm_set_bb_reg(dm, R_0xc04, 0xffffffff, 0x6f005433);
++	odm_set_bb_reg(dm, R_0xc08, 0xffffffff, 0x000004e4);
++	odm_set_bb_reg(dm, R_0x874, 0xffffffff, 0x04003400);
++	odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x00000000);
++
++	RF_DBG(dm, DBG_RF_IQK,
++	       "[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x psd_vaule_temp=0x%x\n",
++	       odm_get_rf_reg(dm, rf_path, RF_0x0, 0xff), rf56,
++	       odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff), psd_vaule_temp);
++
++	odm_set_rf_reg(dm, rf_path, RF_0xdf, bRFRegOffsetMask, 0x00602);
++
++	return psd_vaule_temp;
++}
++
++void odm_tx_gain_gap_calibration_8197f(
++	void *dm_void)
++{
++	PDM_ODM_T dm = (PDM_ODM_T)dm_void;
++
++	u1Byte rf_path, rf0_idx, rf0_idx_current, rf0_idx_next, i, delta_gain_retry = 3;
++
++	s1Byte delta_gain_gap_pre, delta_gain_gap[2][11];
++	u4Byte rf56_current, rf56_next, psd_value_current, psd_value_next;
++	u4Byte psd_gap, rf56_current_temp[2][11];
++	s4Byte rf33[2][11];
++
++	memset(rf33, 0x0, sizeof(rf33));
++
++	for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
++		if (rf_path == RF_PATH_A)
++			odm_set_bb_reg(dm, R_0x88c, (BIT(21) | BIT(20)), 0x3); /*disable 3-wire*/
++		else if (rf_path == RF_PATH_B)
++			odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22)), 0x3); /*disable 3-wire*/
++
++		ODM_delay_us(100);
++
++		for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
++			rf0_idx_current = 3 * (rf0_idx - 1) + 1;
++			odm_set_rf_reg(dm, rf_path, RF_0x0, 0xff, rf0_idx_current);
++			ODM_delay_us(100);
++			rf56_current_temp[rf_path][rf0_idx] = odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff);
++			rf56_current = rf56_current_temp[rf_path][rf0_idx];
++
++			rf0_idx_next = 3 * rf0_idx + 1;
++			odm_set_rf_reg(dm, rf_path, RF_0x0, 0xff, rf0_idx_next);
++			ODM_delay_us(100);
++			rf56_next = odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff);
++
++			RF_DBG(dm, DBG_RF_IQK,
++			       "[TGGC] rf56_current[%d][%d]=0x%x rf56_next[%d][%d]=0x%x\n",
++			       rf_path, rf0_idx, rf56_current, rf_path, rf0_idx,
++			       rf56_next);
++
++			if ((rf56_current >> 5) == (rf56_next >> 5)) {
++				delta_gain_gap[rf_path][rf0_idx] = 0;
++
++				RF_DBG(dm, DBG_RF_IQK,
++				       "[TGGC] rf56_current[11:5] == rf56_next[%d][%d][11:5]=0x%x delta_gain_gap[%d][%d]=%d\n",
++				       rf_path, rf0_idx, (rf56_next >> 5),
++				       rf_path, rf0_idx,
++				       delta_gain_gap[rf_path][rf0_idx]);
++
++				continue;
++			}
++
++			RF_DBG(dm, DBG_RF_IQK,
++			       "[TGGC] rf56_current[%d][%d][11:5]=0x%x != rf56_next[%d][%d][11:5]=0x%x\n",
++			       rf_path, rf0_idx, (rf56_current >> 5), rf_path,
++			       rf0_idx, (rf56_next >> 5));
++
++			for (i = 0; i < delta_gain_retry; i++) {
++				psd_value_current = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_current);
++
++				psd_value_next = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_next - 2);
++
++				psd_gap = psd_value_next / (psd_value_current / 1000);
++
++#if 0
++				if (psd_gap > 1413)
++					delta_gain_gap[rf_path][rf0_idx] = 1;
++				else if (psd_gap > 1122)
++					delta_gain_gap[rf_path][rf0_idx] = 0;
++				else
++					delta_gain_gap[rf_path][rf0_idx] = -1;
++#endif
++
++				if (psd_gap > 1445)
++					delta_gain_gap[rf_path][rf0_idx] = 1;
++				else if (psd_gap > 1096)
++					delta_gain_gap[rf_path][rf0_idx] = 0;
++				else
++					delta_gain_gap[rf_path][rf0_idx] = -1;
++
++				if (i == 0)
++					delta_gain_gap_pre = delta_gain_gap[rf_path][rf0_idx];
++
++				RF_DBG(dm, DBG_RF_IQK,
++				       "[TGGC] psd_value_current=0x%x psd_value_next=0x%x psd_value_next/psd_value_current=%d delta_gain_gap[%d][%d]=%d\n",
++				       psd_value_current, psd_value_next,
++				       psd_gap, rf_path, rf0_idx,
++				       delta_gain_gap[rf_path][rf0_idx]);
++
++				if (i == 0 && delta_gain_gap[rf_path][rf0_idx] == 0)
++					break;
++
++				if (delta_gain_gap_pre != delta_gain_gap[rf_path][rf0_idx]) {
++					delta_gain_gap[rf_path][rf0_idx] = 0;
++
++					RF_DBG(dm, DBG_RF_IQK, "[TGGC] delta_gain_gap_pre(%d) != delta_gain_gap[%d][%d](%d) time=%d\n",
++					       delta_gain_gap_pre, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx], i);
++
++					break;
++				}
++
++				RF_DBG(dm, DBG_RF_IQK,
++				       "[TGGC] delta_gain_gap_pre(%d) == delta_gain_gap[%d][%d](%d) time=%d\n",
++				       delta_gain_gap_pre, rf_path, rf0_idx,
++				       delta_gain_gap[rf_path][rf0_idx], i);
++			}
++		}
++
++		if (rf_path == RF_PATH_A)
++			odm_set_bb_reg(dm, R_0x88c, (BIT(21) | BIT(20)), 0x0); /*enable 3-wire*/
++		else if (rf_path == RF_PATH_B)
++			odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22)), 0x0); /*enable 3-wire*/
++
++		ODM_delay_us(100);
++	}
++
++#if 0
++	/*odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22) | BIT(21) | BIT(20)), 0x0);*/ /*enable 3-wire*/
++#endif
++
++	for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
++		odm_set_rf_reg(dm, rf_path, RF_0xef, bRFRegOffsetMask, 0x00100);
++
++		for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
++			rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + (rf56_current_temp[rf_path][rf0_idx] & 0x1f);
++
++			for (i = rf0_idx; i <= 10; i++)
++				rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + delta_gain_gap[rf_path][i];
++
++			if (rf33[rf_path][rf0_idx] >= 0x1d)
++				rf33[rf_path][rf0_idx] = 0x1d;
++			else if (rf33[rf_path][rf0_idx] <= 0x2)
++				rf33[rf_path][rf0_idx] = 0x2;
++
++			rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + ((rf0_idx - 1) * 0x4000) + (rf56_current_temp[rf_path][rf0_idx] & 0xfffe0);
++
++			RF_DBG(dm, DBG_RF_IQK,
++			       "[TGGC] rf56[%d][%d]=0x%05x rf33[%d][%d]=0x%05x\n",
++			       rf_path, rf0_idx,
++			       rf56_current_temp[rf_path][rf0_idx], rf_path,
++			       rf0_idx, rf33[rf_path][rf0_idx]);
++
++			odm_set_rf_reg(dm, rf_path, RF_0x33, bRFRegOffsetMask, rf33[rf_path][rf0_idx]);
++		}
++
++		odm_set_rf_reg(dm, rf_path, RF_0xef, bRFRegOffsetMask, 0x00000);
++	}
++}
++#endif
++
++void odm_tx_gain_gap_calibration(void *dm_void)
++{
++	PDM_ODM_T dm = (PDM_ODM_T)dm_void;
++#if (RTL8197F_SUPPORT == 1)
++	if (dm->SupportICType & ODM_RTL8197F)
++		odm_tx_gain_gap_calibration_8197f(dm_void);
++#endif
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_txgapcal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_txgapcal.h
+new file mode 100644
+index 000000000..09651cbee
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/halrf_txgapcal.h
+@@ -0,0 +1,31 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_TXGAPCAL_H__
++#define __HALRF_TXGAPCAL_H__
++
++void odm_tx_gain_gap_calibration(void *dm_void);
++
++#endif /*__HALRF_TXGAPCAL_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/rtl8723d/halrf_8723d.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/rtl8723d/halrf_8723d.c
+new file mode 100644
+index 000000000..2ee7a9b76
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/rtl8723d/halrf_8723d.c
+@@ -0,0 +1,2637 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include "mp_precomp.h"
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++#if RT_PLATFORM == PLATFORM_MACOSX
++#include "phydm_precomp.h"
++#else
++#include "../phydm_precomp.h"
++#endif
++#else
++#include "../../phydm_precomp.h"
++#endif
++
++#if (RTL8723D_SUPPORT == 1)
++
++/*---------------------------Define Local Constant---------------------------*/
++/*IQK*/
++#define IQK_DELAY_TIME_8723D 10
++
++/* 2010/04/25 MH Define the max tx power tracking tx agc power.*/
++#define ODM_TXPWRTRACK_MAX_IDX_8723D 6
++
++#define PATH_S1 0
++#define idx_0xc94 0
++#define idx_0xc80 1
++#define idx_0xc4c 2
++
++#define idx_0xc14 0
++#define idx_0xca0 1
++
++#define PATH_S0 1
++#define idx_0xcd0 0
++#define idx_0xcd4 1
++
++#define idx_0xcd8 0
++#define idx_0xcdc 1
++
++#define KEY 0
++#define VAL 1
++
++/*---------------------------Define Local Constant---------------------------*/
++
++/* Tx Power Tracking*/
++
++void set_iqk_matrix_8723d(struct dm_struct *dm, u8 OFDM_index, u8 rf_path,
++			  s32 iqk_result_x, s32 iqk_result_y)
++{
++	s32 ele_A = 0, ele_D = 0, ele_C = 0, value32;
++	s32 ele_A_ext = 0, ele_C_ext = 0, ele_D_ext = 0;
++
++	if (OFDM_index >= OFDM_TABLE_SIZE)
++		OFDM_index = OFDM_TABLE_SIZE - 1;
++	else if (OFDM_index < 0)
++		OFDM_index = 0;
++
++	if (iqk_result_x != 0 && (*dm->band_type == ODM_BAND_2_4G)) {
++		/* new element D */
++		ele_D = (ofdm_swing_table_new[OFDM_index] & 0xFFC00000) >> 22;
++		ele_D_ext = (((iqk_result_x * ele_D) >> 7) & 0x01);
++		/* new element A */
++		if ((iqk_result_x & 0x00000200) != 0) /* consider minus */
++			iqk_result_x = iqk_result_x | 0xFFFFFC00;
++		ele_A = ((iqk_result_x * ele_D) >> 8) & 0x000003FF;
++		ele_A_ext = ((iqk_result_x * ele_D) >> 7) & 0x1;
++		/* new element C */
++		if ((iqk_result_y & 0x00000200) != 0)
++			iqk_result_y = iqk_result_y | 0xFFFFFC00;
++		ele_C = ((iqk_result_y * ele_D) >> 8) & 0x000003FF;
++		ele_C_ext = ((iqk_result_y * ele_D) >> 7) & 0x1;
++
++		switch (rf_path) {
++		case RF_PATH_A:
++			/* write new elements A, C, D to regC80, regC94, reg0xc4c, and element B is always 0 */
++			/* write 0xc80 */
++			value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
++			odm_set_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, value32);
++			/* write 0xc94 */
++			value32 = (ele_C & 0x000003C0) >> 6;
++			odm_set_bb_reg(dm, R_0xc94, MASKH4BITS, value32);
++			/* write 0xc4c */
++			value32 = (ele_D_ext << 28) | (ele_A_ext << 31) | (ele_C_ext << 29);
++			value32 = (odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & (~(BIT(31) | BIT(29) | BIT(28)))) | value32;
++			odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD, value32);
++			break;
++
++		case RF_PATH_B:
++			/*write new elements A, C, D to regCd0 and regCd4, element B is always 0*/
++			value32 = ele_D;
++			odm_set_bb_reg(dm, R_0xcd4, 0x007FE000, value32);
++
++			value32 = ele_C;
++			odm_set_bb_reg(dm, R_0xcd4, 0x000007FE, value32);
++
++			value32 = ele_A;
++			odm_set_bb_reg(dm, R_0xcd0, 0x000007FE, value32);
++
++			odm_set_bb_reg(dm, R_0xcd4, BIT(12), ele_D_ext);
++			odm_set_bb_reg(dm, R_0xcd0, BIT(0), ele_A_ext);
++			odm_set_bb_reg(dm, R_0xcd4, BIT(0), ele_C_ext);
++			break;
++		default:
++			break;
++		}
++	} else {
++		switch (rf_path) {
++		case RF_PATH_A:
++			odm_set_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_new[OFDM_index]);
++			odm_set_bb_reg(dm, R_0xc94, MASKH4BITS, 0x00);
++			value32 = odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & (~(BIT(31) | BIT(29) | BIT(28)));
++			odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD, value32);
++			break;
++
++		case RF_PATH_B:
++			/*image S1:c80 to S0:Cd0 and Cd4*/
++			odm_set_bb_reg(dm, R_0xcd0, 0x000007FE, ofdm_swing_table_new[OFDM_index] & 0x000003FF);
++			odm_set_bb_reg(dm, R_0xcd0, 0x0007E000, (ofdm_swing_table_new[OFDM_index] & 0x0000FC00) >> 10);
++			odm_set_bb_reg(dm, R_0xcd4, 0x0000007E, (ofdm_swing_table_new[OFDM_index] & 0x003F0000) >> 16);
++			odm_set_bb_reg(dm, R_0xcd4, 0x007FE000, (ofdm_swing_table_new[OFDM_index] & 0xFFC00000) >> 22);
++
++			odm_set_bb_reg(dm, R_0xcd4, 0x00000780, 0x00);
++
++			odm_set_bb_reg(dm, R_0xcd4, BIT(12), 0x0);
++			odm_set_bb_reg(dm, R_0xcd4, BIT(0), 0x0);
++			odm_set_bb_reg(dm, R_0xcd0, BIT(0), 0x0);
++			break;
++		default:
++			break;
++		}
++	}
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++	       "TxPwrTracking path %c: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x ele_A_ext = 0x%x ele_C_ext = 0x%x ele_D_ext = 0x%x\n",
++	       (rf_path == RF_PATH_A ? 'A' : 'B'), (u32)iqk_result_x,
++	       (u32)iqk_result_y, (u32)ele_A, (u32)ele_C, (u32)ele_D,
++	       (u32)ele_A_ext, (u32)ele_C_ext, (u32)ele_D_ext);
++}
++
++void set_cck_filter_coefficient_8723d(struct dm_struct *dm, u8 cck_swing_index)
++{
++	odm_set_bb_reg(dm, R_0xab4, 0x000007FF, cck_swing_table_ch1_ch14_8723d[cck_swing_index]);
++}
++
++void do_iqk_8723d(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
++		  u8 threshold)
++{
++	u32 is_bt_enable = 0;
++
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (!(*dm->mp_mode))
++		is_bt_enable = odm_get_mac_reg(dm, R_0xa8, MASKDWORD) & BIT(17);
++
++	if (is_bt_enable) {
++		RF_DBG(dm, DBG_RF_IQK, "[IQK]Skip IQK because BT is enable\n");
++		return;
++	}
++
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]Do IQK because BT is disable\n");
++
++	odm_reset_iqk_result(dm);
++
++	dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
++
++	halrf_iqk_trigger(dm, false);
++}
++
++/*-----------------------------------------------------------------------------
++ * Function:	odm_tx_pwr_track_set_pwr_8723d()
++ *
++ * Overview:	8723D change all channel tx power according to flag.
++ *				OFDM & CCK are all different.
++ *
++ * Input:		NONE
++ *
++ * Output:		NONE
++ *
++ * Return:		NONE
++ *
++ * Revised History:
++ *	When		Who		Remark
++ *	04/23/2012	MHC		Create version 0.
++ *
++ *---------------------------------------------------------------------------
++ */
++void odm_tx_pwr_track_set_pwr_8723d(void *dm_void, enum pwrtrack_method method,
++				    u8 rf_path, u8 channel_mapped_index)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if !((DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211))
++	struct _ADAPTER *adapter = dm->adapter;
++#endif
++#if 0
++	//PHAL_DATA_TYPE			hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++#endif
++	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	u8 pwr_tracking_limit_ofdm = 30;
++	u8 pwr_tracking_limit_cck = 40;
++	u8 tx_rate = 0xFF;
++	u8 final_ofdm_swing_index = 0;
++	u8 final_cck_swing_index = 0;
++
++	if (*dm->mp_mode) {
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++#if (MP_DRIVER == 1)
++		PMPT_CONTEXT p_mpt_ctx = &adapter->MptCtx;
++
++		tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
++#endif
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++#ifdef CONFIG_MP_INCLUDED
++		PMPT_CONTEXT p_mpt_ctx = &adapter->mppriv.mpt_ctx;
++
++		tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
++#endif
++#endif
++#endif
++	} else {
++		u16 rate = *dm->forced_data_rate;
++
++		if (!rate) { /*auto rate*/
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++			tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++			tx_rate = dm->tx_rate;
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++			if (dm->number_linked_client != 0)
++				tx_rate = hw_rate_to_m_rate(dm->tx_rate);
++			else
++				tx_rate = rf->p_rate_index;
++#endif
++		} else { /*force rate*/
++			tx_rate = (u8)rate;
++		}
++	}
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===>ODM_TxPwrTrackSetPwr8723DA\n");
++
++	if (tx_rate != 0xFF) {
++		/*CCK*/
++		if ((tx_rate >= MGN_1M && tx_rate <= MGN_5_5M) || tx_rate == MGN_11M)
++			pwr_tracking_limit_cck = 40;
++		/*OFDM*/
++		else if ((tx_rate >= MGN_6M) && (tx_rate <= MGN_48M))
++			pwr_tracking_limit_ofdm = 36;
++		else if (tx_rate == MGN_54M)
++			pwr_tracking_limit_ofdm = 34;
++
++		/* HT*/
++		else if ((tx_rate >= MGN_MCS0) && (tx_rate <= MGN_MCS2))
++			pwr_tracking_limit_ofdm = 38;
++		else if ((tx_rate >= MGN_MCS3) && (tx_rate <= MGN_MCS4))
++			pwr_tracking_limit_ofdm = 36;
++		else if ((tx_rate >= MGN_MCS5) && (tx_rate <= MGN_MCS7))
++			pwr_tracking_limit_ofdm = 34;
++
++		else if ((tx_rate >= MGN_MCS8) && (tx_rate <= MGN_MCS10))
++			pwr_tracking_limit_ofdm = 38;
++		else if ((tx_rate >= MGN_MCS11) && (tx_rate <= MGN_MCS12))
++			pwr_tracking_limit_ofdm = 36;
++		else if ((tx_rate >= MGN_MCS13) && (tx_rate <= MGN_MCS15))
++			pwr_tracking_limit_ofdm = 34;
++
++		else
++			pwr_tracking_limit_ofdm = cali_info->default_ofdm_index; /*Default OFDM index = 30 */
++	}
++
++	if (method == TXAGC) {
++		u32 pwr = 0, tx_agc = 0;
++		/*void *adapter = dm->adapter;*/
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "odm_TxPwrTrackSetPwr_8723D CH=%d\n", *dm->channel);
++
++		cali_info->remnant_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path]; /* Remnant index equal to aboslute compensate value. */
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++
++#if (MP_DRIVER != 1)
++#if 0
++		PHY_SetTxPowerLevelByPath8723D(adapter, *dm->channel, rf_path);   /* Using new set power function */
++		/* PHY_SetTxPowerLevel8723D(dm->adapter, *dm->channel); */
++#endif
++		cali_info->modify_tx_agc_flag_path_a = true;
++		cali_info->modify_tx_agc_flag_path_b = true;
++		cali_info->modify_tx_agc_flag_path_a_cck = true;
++		if (rf_path == RF_PATH_A) {
++			odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, CCK);
++			odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, OFDM);
++			odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, HT_MCS0_MCS7);
++			odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, HT_MCS8_MCS15);
++		} else {
++			odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, *dm->channel, CCK);
++			odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, *dm->channel, OFDM);
++			odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, *dm->channel, HT_MCS0_MCS7);
++			odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, *dm->channel, HT_MCS8_MCS15);
++		}
++#else
++
++		if (rf_path == RF_PATH_A) {
++			/*CCK path S1*/
++			pwr = odm_get_bb_reg(dm, REG_TX_AGC_A_RATE18_06, 0xFF);
++			pwr += cali_info->power_index_offset[RF_PATH_A];
++			odm_set_bb_reg(dm, REG_TX_AGC_A_CCK_1_MCS32, MASKBYTE1, pwr);
++			tx_agc = (pwr << 16) | (pwr << 8) | (pwr);
++			odm_set_bb_reg(dm, REG_TX_AGC_B_CCK_11_A_CCK_2_11, 0x00ffffff, tx_agc);
++			RT_DISP(FPHY, PHY_TXPWR, ("%s: CCK Tx-rf(A) Power = 0x%x\n", __func__, tx_agc));
++
++			/*OFDM path S1*/
++			pwr = odm_get_bb_reg(dm, REG_TX_AGC_A_RATE18_06, 0xFF);
++			pwr += (cali_info->bb_swing_idx_ofdm[RF_PATH_A] - cali_info->bb_swing_idx_ofdm_base[RF_PATH_A]);
++			tx_agc = ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
++			odm_set_bb_reg(dm, REG_TX_AGC_A_RATE18_06, MASKDWORD, tx_agc);
++			odm_set_bb_reg(dm, REG_TX_AGC_A_RATE54_24, MASKDWORD, tx_agc);
++			odm_set_bb_reg(dm, REG_TX_AGC_A_MCS03_MCS00, MASKDWORD, tx_agc);
++			odm_set_bb_reg(dm, REG_TX_AGC_A_MCS07_MCS04, MASKDWORD, tx_agc);
++			odm_set_bb_reg(dm, REG_TX_AGC_A_MCS11_MCS08, MASKDWORD, tx_agc);
++			odm_set_bb_reg(dm, REG_TX_AGC_A_MCS15_MCS12, MASKDWORD, tx_agc);
++			RT_DISP(FPHY, PHY_TXPWR, ("%s: OFDM Tx-rf(A) Power = 0x%x\n", __func__, tx_agc));
++		} else if (rf_path == RF_PATH_B) {
++			pwr = odm_get_bb_reg(dm, REG_TX_AGC_B_RATE18_06, 0xFF);
++			pwr += cali_info->power_index_offset[RF_PATH_B];
++			odm_set_bb_reg(dm, REG_TX_AGC_B_CCK_1_55_MCS32, MASKBYTE3, pwr);
++			odm_set_bb_reg(dm, REG_TX_AGC_B_CCK_11_A_CCK_2_11, 0xff000000, pwr);
++			RT_DISP(FPHY, PHY_TXPWR, ("%s: CCK Tx-rf(B) Power = 0x%x\n", __func__, pwr));
++
++			pwr = odm_get_bb_reg(dm, REG_TX_AGC_B_RATE18_06, 0xFF);
++			pwr += (cali_info->bb_swing_idx_ofdm[RF_PATH_B] - cali_info->bb_swing_idx_ofdm_base[RF_PATH_B]);
++			tx_agc = ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
++			odm_set_bb_reg(dm, REG_TX_AGC_B_RATE18_06, MASKDWORD, tx_agc);
++			odm_set_bb_reg(dm, REG_TX_AGC_B_RATE54_24, MASKDWORD, tx_agc);
++			odm_set_bb_reg(dm, REG_TX_AGC_B_MCS03_MCS00, MASKDWORD, tx_agc);
++			odm_set_bb_reg(dm, REG_TX_AGC_B_MCS07_MCS04, MASKDWORD, tx_agc);
++			odm_set_bb_reg(dm, REG_TX_AGC_B_MCS11_MCS08, MASKDWORD, tx_agc);
++			odm_set_bb_reg(dm, REG_TX_AGC_B_MCS15_MCS12, MASKDWORD, tx_agc);
++			RT_DISP(FPHY, PHY_TXPWR, ("%s: OFDM Tx-rf(B) Power = 0x%x\n", __func__, tx_agc));
++		}
++#endif
++
++#endif
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++/*phy_rf6052_set_cck_tx_power(dm->priv, *(dm->channel));
++		  phy_rf6052_set_ofdm_tx_power(dm->priv, *(dm->channel));*/
++#endif
++
++	} else if (method == BBSWING) {
++		final_ofdm_swing_index = cali_info->default_ofdm_index + cali_info->absolute_ofdm_swing_idx[rf_path];
++		final_cck_swing_index = cali_info->default_cck_index + cali_info->absolute_ofdm_swing_idx[rf_path];
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       " cali_info->default_ofdm_index=%d,  cali_info->DefaultCCKIndex=%d, cali_info->absolute_ofdm_swing_idx[rf_path]=%d, cali_info->remnant_cck_swing_idx=%d   rf_path = %d\n",
++		       cali_info->default_ofdm_index,
++		       cali_info->default_cck_index,
++		       cali_info->absolute_ofdm_swing_idx[rf_path],
++		       cali_info->remnant_cck_swing_idx, rf_path);
++
++		/* Adjust BB swing by OFDM IQ matrix */
++		if (final_ofdm_swing_index >= pwr_tracking_limit_ofdm)
++			final_ofdm_swing_index = pwr_tracking_limit_ofdm;
++		else if (final_ofdm_swing_index < 0)
++			final_ofdm_swing_index = 0;
++
++		if (final_cck_swing_index >= CCK_TABLE_SIZE_8723D)
++			final_cck_swing_index = CCK_TABLE_SIZE_8723D - 1;
++		else if (cali_info->bb_swing_idx_cck < 0)
++			final_cck_swing_index = 0;
++
++		set_iqk_matrix_8723d(dm, final_ofdm_swing_index, RF_PATH_A,
++				     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
++				     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
++
++		set_iqk_matrix_8723d(dm, final_ofdm_swing_index, RF_PATH_B,
++				     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][4],
++				     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][5]);
++
++		set_cck_filter_coefficient_8723d(dm, final_cck_swing_index);
++
++		cali_info->modify_tx_agc_flag_path_a = true;
++
++		odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, CCK);
++		odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, OFDM);
++		odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, HT_MCS0_MCS7);
++
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "final_cck_swing_index=%d\n",
++		       final_cck_swing_index);
++
++	} else if (method == MIX_MODE) {
++#if (0)  /*MP_DRIVER == 1*/
++		u32 tx_agc = 0; /*add by Mingzhi.Guo 2015-04-10*/
++		s32 pwr = 0;
++#endif
++		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++		       "dm->default_ofdm_index=%d,  dm->DefaultCCKIndex=%d, dm->absolute_ofdm_swing_idx[rf_path]=%d, rf_path = %d\n",
++		       cali_info->default_ofdm_index,
++		       cali_info->default_cck_index,
++		       cali_info->absolute_ofdm_swing_idx[rf_path], rf_path);
++
++		final_ofdm_swing_index = cali_info->default_ofdm_index + cali_info->absolute_ofdm_swing_idx[rf_path];
++
++		if (rf_path == RF_PATH_A) {
++			final_cck_swing_index = cali_info->default_cck_index + cali_info->absolute_ofdm_swing_idx[rf_path]; /*CCK Follow path-A and lower CCK index means higher power.*/
++
++			if (final_ofdm_swing_index > pwr_tracking_limit_ofdm) {
++				cali_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index - pwr_tracking_limit_ofdm;
++
++				set_iqk_matrix_8723d(dm, pwr_tracking_limit_ofdm, RF_PATH_A,
++						     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
++						     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
++				set_iqk_matrix_8723d(dm, pwr_tracking_limit_ofdm, RF_PATH_B,
++						     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][4],
++						     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][5]);
++
++				cali_info->modify_tx_agc_flag_path_a = true;
++				/*Set tx_agc Page C{};*/
++#if 0
++				/*odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, OFDM);*/
++				/*	odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, HT_MCS0_MCS7);*/
++#endif
++
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "******Path_A Over BBSwing Limit, pwr_tracking_limit = %d, Remnant tx_agc value = %d\n",
++				       pwr_tracking_limit_ofdm,
++				       cali_info->remnant_ofdm_swing_idx[rf_path]);
++			} else if (final_ofdm_swing_index < 0) {
++				cali_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index;
++
++				set_iqk_matrix_8723d(dm, 0, RF_PATH_A,
++						     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
++						     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
++				set_iqk_matrix_8723d(dm, 0, RF_PATH_B,
++						     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][4],
++						     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][5]);
++
++				cali_info->modify_tx_agc_flag_path_a = true;
++
++				/*Set tx_agc Page C{};*/
++#if 0
++				/*odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, OFDM);*/
++				/*	odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, HT_MCS0_MCS7);*/
++#endif
++
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "******Path_A Lower then BBSwing lower bound  0, Remnant tx_agc value = %d\n",
++				       cali_info->remnant_ofdm_swing_idx[rf_path]);
++			} else {
++				set_iqk_matrix_8723d(dm, final_ofdm_swing_index, RF_PATH_A,
++						     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
++						     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
++				set_iqk_matrix_8723d(dm, final_ofdm_swing_index, RF_PATH_B,
++						     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][4],
++						     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][5]);
++
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "******Path_A Compensate with BBSwing, final_ofdm_swing_index = %d\n",
++				       final_ofdm_swing_index);
++
++				if (cali_info->modify_tx_agc_flag_path_a) {
++					cali_info->remnant_ofdm_swing_idx[rf_path] = 0;
++
++					/*Set tx_agc Page C{};*/
++#if 0
++					/*	odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, OFDM );
++						odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, HT_MCS0_MCS7 );
++						odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, HT_MCS8_MCS15 );*/
++#endif
++
++					cali_info->modify_tx_agc_flag_path_a = false;
++
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "******Path_A dm->Modify_TxAGC_Flag = false\n");
++				}
++			}
++#if (0) /*MP_DRIVER == 1*/
++			if ((*dm->mp_mode) == 1) {
++				pwr = odm_get_bb_reg(dm, REG_TX_AGC_A_RATE18_06, 0xFF);
++				pwr += (cali_info->remnant_ofdm_swing_idx[RF_PATH_A] - cali_info->modify_tx_agc_value_ofdm);
++
++				if (pwr > 0x3F)
++					pwr = 0x3F;
++				else if (pwr < 0)
++					pwr = 0;
++
++				tx_agc |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
++				odm_set_bb_reg(dm, REG_TX_AGC_A_RATE18_06, MASKDWORD, tx_agc);
++				odm_set_bb_reg(dm, REG_TX_AGC_A_RATE54_24, MASKDWORD, tx_agc);
++				odm_set_bb_reg(dm, REG_TX_AGC_A_MCS03_MCS00, MASKDWORD, tx_agc);
++				odm_set_bb_reg(dm, REG_TX_AGC_A_MCS07_MCS04, MASKDWORD, tx_agc);
++
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "ODM_TxPwrTrackSetPwr8188F: OFDM Tx-rf(A) Power = 0x%x\n",
++				       tx_agc);
++			}
++#endif
++
++			odm_set_tx_power_index_by_rate_section(dm, rf_path,
++							       *dm->channel,
++							       OFDM);
++			odm_set_tx_power_index_by_rate_section(dm, rf_path,
++							       *dm->channel,
++							       HT_MCS0_MCS7);
++			cali_info->modify_tx_agc_value_ofdm = cali_info->remnant_ofdm_swing_idx[RF_PATH_A];
++
++			if (final_cck_swing_index > pwr_tracking_limit_cck) {
++				cali_info->remnant_cck_swing_idx = final_cck_swing_index - pwr_tracking_limit_cck;
++
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "******Path_A CCK Over Limit, pwr_tracking_limit_cck = %d, dm->remnant_cck_swing_idx  = %d\n",
++				       pwr_tracking_limit_cck,
++				       cali_info->remnant_cck_swing_idx);
++
++				/* Adjust BB swing by CCK filter coefficient*/
++				odm_set_bb_reg(dm, R_0xab4, 0x000007FF, cck_swing_table_ch1_ch14_8723d[pwr_tracking_limit_cck]);
++
++				cali_info->modify_tx_agc_flag_path_a_cck = true;
++
++				/*Set tx_agc Page C{};*/
++#if 0
++				/*	odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, CCK);
++					odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, CCK);*/
++#endif
++
++			} else if (final_cck_swing_index < 0) {
++				cali_info->remnant_cck_swing_idx = final_cck_swing_index;
++
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "******Path_A CCK Under Limit, pwr_tracking_limit_cck = %d, dm->remnant_cck_swing_idx  = %d\n",
++				       0, cali_info->remnant_cck_swing_idx);
++
++				odm_set_bb_reg(dm, R_0xab4, 0x000007FF, cck_swing_table_ch1_ch14_8723d[0]);
++
++				cali_info->modify_tx_agc_flag_path_a_cck = true;
++
++#if 0
++				/*odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, CCK);
++				odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, CCK);*/
++#endif
++
++			} else {
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "******Path_A CCK Compensate with BBSwing, final_cck_swing_index = %d\n",
++				       final_cck_swing_index);
++
++				odm_set_bb_reg(dm, R_0xab4, 0x000007FF, cck_swing_table_ch1_ch14_8723d[final_cck_swing_index]);
++
++#if 0
++				/*	if (cali_info->modify_tx_agc_flag_path_a_cck) {*/
++#endif
++				cali_info->remnant_cck_swing_idx = 0;
++
++#if 0
++				/*odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, CCK );
++				odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, CCK );*/
++#endif
++
++				cali_info->modify_tx_agc_flag_path_a_cck = false;
++
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "******Path_A dm->Modify_TxAGC_Flag_CCK = false\n");
++			}
++#if (0) /*MP_DRIVER == 1*/
++			if ((*dm->mp_mode)) {
++				pwr = odm_get_bb_reg(dm, REG_TX_AGC_B_CCK_11_A_CCK_2_11, MASKBYTE1);
++				pwr += cali_info->remnant_cck_swing_idx - cali_info->modify_tx_agc_value_cck;
++
++				if (pwr > 0x3F)
++					pwr = 0x3F;
++				else if (pwr < 0)
++					pwr = 0;
++
++				odm_set_bb_reg(dm, REG_TX_AGC_A_CCK_1_MCS32, MASKBYTE1, pwr);
++				tx_agc = (pwr << 16) | (pwr << 8) | (pwr);
++				odm_set_bb_reg(dm, REG_TX_AGC_B_CCK_11_A_CCK_2_11, 0xffffff00, tx_agc);
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "ODM_TxPwrTrackSetPwr8723D: CCK Tx-rf(A) Power = 0x%x\n",
++				       tx_agc);
++			} else
++#endif
++
++				odm_set_tx_power_index_by_rate_section(dm, rf_path, *dm->channel, CCK);
++
++			cali_info->modify_tx_agc_value_cck = cali_info->remnant_cck_swing_idx;
++		}
++#if 0
++		if (rf_path == RF_PATH_B) {
++			if (final_ofdm_swing_index > pwr_tracking_limit_ofdm) {
++				cali_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index - pwr_tracking_limit_ofdm;
++
++				set_iqk_matrix_8723d(dm, pwr_tracking_limit_ofdm, RF_PATH_B,
++					cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][4],
++					cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][5]);
++
++				cali_info->modify_tx_agc_flag_path_a = true;
++
++
++				/*odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, OFDM);
++				odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, HT_MCS0_MCS7);*/
++
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "******Path_B Over BBSwing Limit, pwr_tracking_limit = %d, Remnant tx_agc value = %d\n",
++				       pwr_tracking_limit_ofdm,
++				       cali_info->remnant_ofdm_swing_idx[rf_path
++				       ]);
++			} else if (final_ofdm_swing_index < 0) {
++				cali_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index ;
++
++				set_iqk_matrix_8723d(dm, 0, RF_PATH_B,
++					cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][4],
++					cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][5]);
++
++				cali_info->modify_tx_agc_flag_path_a = true;
++
++
++				/*odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, OFDM);
++				odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, HT_MCS0_MCS7);*/
++
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "******Path_B Lower then BBSwing lower bound  0, Remnant tx_agc value = %d\n",
++				       cali_info->remnant_ofdm_swing_idx[rf_path
++				       ]);
++			} else {
++				set_iqk_matrix_8723d(dm, final_ofdm_swing_index, RF_PATH_B,
++					cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][4],
++					cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][5]);
++
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "******Path_B Compensate with BBSwing, final_ofdm_swing_index = %d\n",
++				       final_ofdm_swing_index);
++
++				if (cali_info->modify_tx_agc_flag_path_b) {
++					cali_info->remnant_ofdm_swing_idx[rf_path] = 0;
++
++					/*odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, OFDM);
++					odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, HT_MCS0_MCS7);*/
++
++					cali_info->modify_tx_agc_flag_path_a = false;
++
++					RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "******Path_B dm->Modify_TxAGC_Flag = false\n");
++				}
++			}
++#if (MP_DRIVER == 1)
++			if ((*dm->mp_mode) == 1) {
++				pwr = odm_get_bb_reg(dm, REG_TX_AGC_A_RATE18_06, 0xFF);
++				pwr += (cali_info->remnant_ofdm_swing_idx[RF_PATH_B] - cali_info->modify_tx_agc_value_ofdm);
++
++				if (pwr > 0x3F)
++					pwr = 0x3F;
++				else if (pwr < 0)
++					pwr = 0;
++
++				tx_agc |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
++				odm_set_bb_reg(dm, REG_TX_AGC_A_RATE18_06, MASKDWORD, tx_agc);
++				odm_set_bb_reg(dm, REG_TX_AGC_A_RATE54_24, MASKDWORD, tx_agc);
++				odm_set_bb_reg(dm, REG_TX_AGC_A_MCS03_MCS00, MASKDWORD, tx_agc);
++				odm_set_bb_reg(dm, REG_TX_AGC_A_MCS07_MCS04, MASKDWORD, tx_agc);
++
++				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++				       "ODM_TxPwrTrackSetPwr8723D: OFDM Tx-rf(A) Power = 0x%x\n",
++				       tx_agc);
++
++			} else
++#endif
++			{
++				odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, *dm->channel, OFDM);
++				odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, *dm->channel, HT_MCS0_MCS7);
++			}
++			cali_info->modify_tx_agc_value_ofdm = cali_info->remnant_ofdm_swing_idx[RF_PATH_B] ;
++		}
++#endif
++	} else {
++		return;
++	}
++}
++
++void get_delta_swing_table_8723d(void *dm_void, u8 **temperature_up_a,
++				 u8 **temperature_down_a, u8 **temperature_up_b,
++				 u8 **temperature_down_b)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if !((DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211))
++	struct _ADAPTER *adapter = dm->adapter;
++#endif
++	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
++	struct _hal_rf_ *rf = &dm->rf_table;
++	u8 tx_rate = 0xFF;
++	u8 channel = *dm->channel;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};
++	static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11};
++#endif
++
++	if (*dm->mp_mode) {
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++#if (MP_DRIVER == 1)
++		PMPT_CONTEXT p_mpt_ctx = &adapter->MptCtx;
++
++		tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
++#endif
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++#ifdef CONFIG_MP_INCLUDED
++		PMPT_CONTEXT p_mpt_ctx = &adapter->mppriv.mpt_ctx;
++
++		tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
++#endif
++#endif
++#endif
++	} else {
++		u16 rate = *dm->forced_data_rate;
++
++		if (!rate) { /*auto rate*/
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++			tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++			tx_rate = dm->tx_rate;
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++			if (dm->number_linked_client != 0)
++				tx_rate = hw_rate_to_m_rate(dm->tx_rate);
++			else
++				tx_rate = rf->p_rate_index;
++#endif
++		} else { /*force rate*/
++			tx_rate = (u8)rate;
++		}
++	}
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Power Tracking tx_rate=0x%X\n",
++	       tx_rate);
++
++	if (channel >= 1 && channel <= 14) {
++#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++		if (RX_HAL_IS_CCK_RATE(tx_rate)) {
++#else
++		if (IS_CCK_RATE(tx_rate)) {
++#endif
++			*temperature_up_a = cali_info->delta_swing_table_idx_2g_cck_a_p;
++			*temperature_down_a = cali_info->delta_swing_table_idx_2g_cck_a_n;
++			*temperature_up_b = cali_info->delta_swing_table_idx_2g_cck_b_p;
++			*temperature_down_b = cali_info->delta_swing_table_idx_2g_cck_b_n;
++		} else {
++			*temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;
++			*temperature_down_a = cali_info->delta_swing_table_idx_2ga_n;
++			*temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;
++			*temperature_down_b = cali_info->delta_swing_table_idx_2gb_n;
++		}
++	} else {
++		*temperature_up_a = (u8 *)delta_swing_table_idx_2ga_p_8188e;
++		*temperature_down_a = (u8 *)delta_swing_table_idx_2ga_n_8188e;
++		*temperature_up_b = (u8 *)delta_swing_table_idx_2ga_p_8188e;
++		*temperature_down_b = (u8 *)delta_swing_table_idx_2ga_n_8188e;
++	}
++}
++
++void get_delta_swing_xtal_table_8723d(void *dm_void, s8 **temperature_up_xtal,
++				      s8 **temperature_down_xtal)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
++
++	*temperature_up_xtal = cali_info->delta_swing_table_xtal_p;
++	*temperature_down_xtal = cali_info->delta_swing_table_xtal_n;
++}
++
++void odm_txxtaltrack_set_xtal_8723d(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
++	s8 crystal_cap;
++
++	crystal_cap = dm->dm_cfo_track.crystal_cap_default & 0x3F;
++	crystal_cap = crystal_cap + cali_info->xtal_offset;
++
++	if (crystal_cap < 0)
++		crystal_cap = 0;
++	else if (crystal_cap > 63)
++		crystal_cap = 63;
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
++	       "crystal_cap(%d)= dm->dm_cfo_track.crystal_cap_default(%d) + cali_info->xtal_offset(%d)\n",
++	       crystal_cap, dm->dm_cfo_track.crystal_cap_default, cali_info->xtal_offset);
++
++	odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0xFFF000, (crystal_cap | (crystal_cap << 6)));
++
++	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "crystal_cap(0x2c)  0x%X\n",
++	       odm_get_bb_reg(dm, REG_MAC_PHY_CTRL, 0xFFF000));
++}
++
++void configure_txpower_track_8723d(struct txpwrtrack_cfg *config)
++{
++	config->swing_table_size_cck = CCK_TABLE_SIZE_8723D;
++	config->swing_table_size_ofdm = OFDM_TABLE_SIZE;
++	config->threshold_iqk = IQK_THRESHOLD;
++	config->average_thermal_num = AVG_THERMAL_NUM_8723D;
++	config->rf_path_count = MAX_PATH_NUM_8723D;
++	config->thermal_reg_addr = RF_0x42;
++
++	config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr_8723d;
++	config->do_iqk = do_iqk_8723d;
++	config->phy_lc_calibrate = halrf_lck_trigger;
++	config->get_delta_swing_table = get_delta_swing_table_8723d;
++	config->get_delta_swing_xtal_table = get_delta_swing_xtal_table_8723d;
++	config->odm_txxtaltrack_set_xtal = odm_txxtaltrack_set_xtal_8723d;
++}
++
++#define MAX_TOLERANCE 5
++#define IQK_DELAY_TIME 1
++
++u8 phy_path_s1_iqk_8723d(struct dm_struct *dm, boolean config_path_s0)
++{
++	u32 reg_eac, reg_e94, reg_e9c, path_sel_bb;
++	u8 result = 0x00, cnt;
++	u32 original_path, original_gnt;
++	u16 ktime;
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]path S1 TXIQK!!\n");
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0x67 @S1 TXIQK = 0x%x\n",
++	       odm_get_mac_reg(dm, R_0x64, MASKBYTE3));
++	/*save RF path*/
++	path_sel_bb = odm_get_bb_reg(dm, R_0x948, MASKDWORD);
++#if 0
++	/*RF_DBG(dm,DBG_RF_IQK, "[IQK]0x1e6@S1 TXIQK = 0x%x\n", platform_efio_read_1byte(adapter, 0x1e6));*/
++#endif
++	odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x99000000);
++
++	/*IQK setting*/
++	/*leave IQK mode*/
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	/* --- \A7\EF\BCgTXIQK mode table ---*/
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x80000);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00004);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0005d);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xBFFE0);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00000);
++
++	/*path-A IQK setting*/
++	odm_set_bb_reg(dm, R_0xe30, MASKDWORD, 0x08008c0c);
++	odm_set_bb_reg(dm, R_0xe34, MASKDWORD, 0x38008c1c);
++	odm_set_bb_reg(dm, R_0xe38, MASKDWORD, 0x8214019f);
++	odm_set_bb_reg(dm, R_0xe3c, MASKDWORD, 0x28160200);
++	odm_set_bb_reg(dm, R_0xe40, MASKDWORD, 0x01007c00);
++	odm_set_bb_reg(dm, R_0xe44, MASKDWORD, 0x01004800);
++
++	/*LO calibration setting*/
++	odm_set_bb_reg(dm, R_0xe4c, MASKDWORD, 0x00462911);
++
++	/*PA, PAD setting*/
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x1);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x56, 0x600, 0x0);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x56, 0x1E0, 0x3);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x8d, 0x1F, 0xf);
++
++	/*LOK setting  added for 8723D*/
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x10, 0x1);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x54, 0x1, 0x1);
++#if 1
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK, 0xe0d);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK, 0x60d);
++#endif
++
++	RF_DBG(dm, DBG_RF_IQK, "RF0x1 @S1 TXIQK = 0x%x\n",
++	       odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK));
++	RF_DBG(dm, DBG_RF_IQK, "RF0x2 @S1 TXIQK = 0x%x\n",
++	       odm_get_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK));
++
++	/*enter IQK mode*/
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
++
++#if 1
++	/*backup path & GNT value */
++	original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]OriginalGNT = 0x%x\n", original_gnt);
++
++	/*set GNT_WL=1/GNT_BT=1  and path owner to WiFi for pause BT traffic*/
++	odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x0000ff00);
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
++	odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1);
++#endif
++
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0054);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]GNT_BT @S1 TXIQK = 0x%x\n",
++	       odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD));
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0x948 @S1 TXIQK = 0x%x\n",
++	       odm_get_bb_reg(dm, R_0x948, MASKDWORD));
++
++	/*One shot, path S1 LOK & IQK*/
++	odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xfa000000);
++	odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf8000000);
++
++	/* delay x ms */
++#if 0
++	/*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/
++#endif
++
++	ktime = 0;
++	while ((!odm_get_bb_reg(dm, R_0xeac, BIT(26))) && ktime < 1000) {
++		ODM_delay_us(10);
++		ktime++;
++	}
++
++#if 1
++	/*Restore GNT_WL/GNT_BT  and path owner*/
++	odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
++	odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
++#endif
++
++	/*reload RF path*/
++	odm_set_bb_reg(dm, R_0x948, MASKDWORD, path_sel_bb);
++
++	/*leave IQK mode*/
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	/*PA/PAD controlled by 0x0*/
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x0);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, BIT(0), 0x0);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, BIT(0), 0x0);
++
++	/* Check failed*/
++	reg_eac = odm_get_bb_reg(dm, R_0xeac, MASKDWORD);
++	reg_e94 = odm_get_bb_reg(dm, R_0xe94, MASKDWORD);
++	reg_e9c = odm_get_bb_reg(dm, R_0xe9c, MASKDWORD);
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac = 0x%x\n", reg_eac);
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", reg_e94,
++	       reg_e9c);
++	/*monitor image power before & after IQK*/
++	RF_DBG(dm, DBG_RF_IQK,
++	       "[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
++	       odm_get_bb_reg(dm, R_0xe90, MASKDWORD),
++	       odm_get_bb_reg(dm, R_0xe98, MASKDWORD));
++
++	if (!(reg_eac & BIT(28)) &&
++	    (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
++	    (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
++
++		result |= 0x01;
++	else
++		RF_DBG(dm, DBG_RF_IQK, "S1 TXIQK FAIL\n");
++	return result;
++}
++
++u8 phy_path_s1_rx_iqk_8723d(struct dm_struct *dm, boolean config_path_s0)
++{
++	u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u4tmp, tmp, path_sel_bb;
++	u8 result = 0x00, cnt;
++	u16 ktime;
++	u32 original_path, original_gnt;
++
++	path_sel_bb = odm_get_bb_reg(dm, R_0x948, MASKDWORD);
++
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]path S1 RXIQK Step1!!\n");
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0x67 @S1 RXIQK1 = 0x%x\n",
++	       odm_get_mac_reg(dm, R_0x64, MASKBYTE3));
++	odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x99000000);
++#if 0
++	/*RF_DBG(dm,DBG_RF_INIT, "[IQK]0x1e6@S1 RXIQK1 = 0x%x\n", platform_efio_read_1byte(adapter, 0x1e6));	*/
++#endif
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
++
++	/*IQK setting*/
++	odm_set_bb_reg(dm, R_0xe40, MASKDWORD, 0x01007c00);
++	odm_set_bb_reg(dm, R_0xe44, MASKDWORD, 0x01004800);
++
++	/*path-A IQK setting*/
++	odm_set_bb_reg(dm, R_0xe30, MASKDWORD, 0x18008c1c);
++	odm_set_bb_reg(dm, R_0xe34, MASKDWORD, 0x38008c1c);
++	odm_set_bb_reg(dm, R_0xe50, MASKDWORD, 0x38008c1c);
++	odm_set_bb_reg(dm, R_0xe54, MASKDWORD, 0x38008c1c);
++
++	odm_set_bb_reg(dm, R_0xe38, MASKDWORD, 0x82160000);
++	odm_set_bb_reg(dm, R_0xe3c, MASKDWORD, 0x28160000);
++
++	/*LO calibration setting*/
++	odm_set_bb_reg(dm, R_0xe4c, MASKDWORD, 0x0046a911);
++
++	/*modify RXIQK mode table*/
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x80000);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00006);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0005f);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xa7ffb);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00000);
++
++	/*---------PA/PAD=0----------*/
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x1);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x56, 0x600, 0x0);
++#if 1
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK, 0xe0d);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK, 0x60d);
++#endif
++	RF_DBG(dm, DBG_RF_IQK, "RF0x1@ path S1 RXIQK1 = 0x%x\n",
++	       odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK));
++	RF_DBG(dm, DBG_RF_IQK, "RF0x2@ path S1 RXIQK1 = 0x%x\n",
++	       odm_get_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK));
++
++	/*enter IQK mode*/
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
++#if 1
++	/*backup path & GNT value */
++	original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]OriginalGNT = 0x%x\n", original_gnt);
++
++	/*set GNT_WL=1/GNT_BT=1  and path owner to WiFi for pause BT traffic*/
++	odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x0000ff00);
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
++	odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1);
++#endif
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0054);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]GNT_BT @S1 RXIQK1 = 0x%x\n",
++	       odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD));
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0x948 @S1 RXIQK1 = 0x%x\n",
++	       odm_get_bb_reg(dm, R_0x948, MASKDWORD));
++
++	/*One shot, path S1 LOK & IQK*/
++	odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf9000000);
++	odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf8000000);
++
++	/*delay x ms*/
++#if 0
++	/*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/
++#endif
++
++	ktime = 0;
++	while ((!odm_get_bb_reg(dm, R_0xeac, BIT(26))) && ktime < 1000) {
++		ODM_delay_us(10);
++		ktime++;
++	}
++	reg_eac = odm_get_bb_reg(dm, R_0xeac, MASKDWORD);
++	reg_e94 = odm_get_bb_reg(dm, R_0xe94, MASKDWORD);
++	reg_e9c = odm_get_bb_reg(dm, R_0xe9c, MASKDWORD);
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac = 0x%x\n", reg_eac);
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", reg_e94,
++	       reg_e9c);
++	/*monitor image power before & after IQK*/
++	RF_DBG(dm, DBG_RF_IQK,
++	       "[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
++	       odm_get_bb_reg(dm, R_0xe90, MASKDWORD),
++	       odm_get_bb_reg(dm, R_0xe98, MASKDWORD));
++	tmp = (reg_e9c & 0x03FF0000) >> 16;
++	if ((tmp & 0x200) > 0)
++		tmp = 0x400 - tmp;
++
++	if (!(reg_eac & BIT(28)) &&
++	    (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
++	    (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) {
++		result |= 0x01;
++	} else {
++		RF_DBG(dm, DBG_RF_IQK, "S1 RXIQK STEP1 FAIL\n");
++#if 1
++		/*Restore GNT_WL/GNT_BT  and path owner*/
++		odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
++		odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
++		odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
++#endif
++		/*reload RF path*/
++		odm_set_bb_reg(dm, R_0x948, MASKDWORD, path_sel_bb);
++		odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
++
++		for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++			ODM_delay_us(10);
++
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x0);
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, BIT(0), 0x0);
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, BIT(0), 0x0);
++		return result;
++	}
++
++	u4tmp = 0x80007C00 | (reg_e94 & 0x3FF0000) | ((reg_e9c & 0x3FF0000) >> 16);
++	odm_set_bb_reg(dm, R_0xe40, MASKDWORD, u4tmp);
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe40 = 0x%x u4tmp = 0x%x\n",
++	       odm_get_bb_reg(dm, R_0xe40, MASKDWORD), u4tmp);
++
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]path S1 RXIQK STEP2!!\n");
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0x67 @S1 RXIQK2 = 0x%x\n",
++	       odm_get_mac_reg(dm, R_0x64, MASKBYTE3));
++#if 0
++	/*RF_DBG(dm,DBG_RF_INIT, "[IQK]0x1e6@S1 RXIQK2 = 0x%x\n", platform_efio_read_1byte(adapter, 0x1e6));	*/
++#endif
++	odm_set_bb_reg(dm, R_0xe44, MASKDWORD, 0x01004800);
++
++	odm_set_bb_reg(dm, R_0xe30, MASKDWORD, 0x38008c1c);
++	odm_set_bb_reg(dm, R_0xe34, MASKDWORD, 0x18008c1c);
++	odm_set_bb_reg(dm, R_0xe50, MASKDWORD, 0x38008c1c);
++	odm_set_bb_reg(dm, R_0xe54, MASKDWORD, 0x38008c1c);
++
++	odm_set_bb_reg(dm, R_0xe38, MASKDWORD, 0x82170000);
++	odm_set_bb_reg(dm, R_0xe3c, MASKDWORD, 0x28171400);
++
++	/*LO calibration setting*/
++	odm_set_bb_reg(dm, R_0xe4c, MASKDWORD, 0x0046a8d1);
++
++	/*modify RXIQK mode table*/
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00007);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0005f);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xb3fdb);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00000);
++
++	RF_DBG(dm, DBG_RF_IQK, "RF0x1 @S1 RXIQK2 = 0x%x\n",
++	       odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK));
++	RF_DBG(dm, DBG_RF_IQK, "RF0x2 @S1 RXIQK2 = 0x%x\n",
++	       odm_get_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK));
++
++	/*enter IQK mode*/
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
++
++#if 1
++	/*backup path & GNT value */
++	original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]OriginalGNT = 0x%x\n", original_gnt);
++
++	/*set GNT_WL=1/GNT_BT=1  and path owner to WiFi for pause BT traffic*/
++	odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x0000ff00);
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
++	odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1);
++#endif
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0054);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]GNT_BT @S1 RXIQK2 = 0x%x\n",
++	       odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD));
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0x948 @S1 RXIQK2 = 0x%x\n",
++	       odm_get_bb_reg(dm, R_0x948, MASKDWORD));
++
++	odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf9000000);
++	odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf8000000);
++
++	/*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/
++
++	ktime = 0;
++	while ((!odm_get_bb_reg(dm, R_0xeac, BIT(26))) && ktime < 1000) {
++		ODM_delay_us(10);
++		ktime++;
++	}
++
++#if 1
++	/*Restore GNT_WL/GNT_BT  and path owner*/
++	odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
++	odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
++#endif
++	/*reload RF path*/
++	odm_set_bb_reg(dm, R_0x948, MASKDWORD, path_sel_bb);
++
++	/*leave IQK mode*/
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	/*	PA/PAD controlled by 0x0*/
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x0);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, BIT(0), 0x0);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, BIT(0), 0x0);
++
++	reg_eac = odm_get_bb_reg(dm, R_0xeac, MASKDWORD);
++	reg_ea4 = odm_get_bb_reg(dm, R_0xea4, MASKDWORD);
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac = 0x%x\n", reg_eac);
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xea4 = 0x%x, 0xeac = 0x%x\n", reg_ea4,
++	       reg_eac);
++
++	RF_DBG(dm, DBG_RF_IQK,
++	       "[IQK]0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n",
++	       odm_get_bb_reg(dm, R_0xea0, MASKDWORD),
++	       odm_get_bb_reg(dm, R_0xea8, MASKDWORD));
++
++	tmp = (reg_eac & 0x03FF0000) >> 16;
++	if ((tmp & 0x200) > 0)
++		tmp = 0x400 - tmp;
++
++	if (!(reg_eac & BIT(27)) && /*if Tx is OK, check whether Rx is OK*/
++	    (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
++	    (((reg_eac & 0x03FF0000) >> 16) != 0x36) &&
++	    (((reg_ea4 & 0x03FF0000) >> 16) < 0x11a) &&
++	    (((reg_ea4 & 0x03FF0000) >> 16) > 0xe6) &&
++	    tmp < 0x1a)
++		result |= 0x02;
++	else
++		RF_DBG(dm, DBG_RF_IQK, "S1 RXIQK STEP2 FAIL\n");
++	return result;
++}
++
++u8 phy_path_s0_iqk_8723d(struct dm_struct *dm)
++{
++	u32 reg_e94_s0, reg_e9c_s0, reg_eac_s0, path_sel_bb;
++	u8 result = 0x00, cnt;
++	u16 ktime;
++	u32 original_path, original_gnt;
++
++	RF_DBG(dm, DBG_RF_IQK, "path S0 TXIQK!\n");
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0x67 @S0 TXIQK = 0x%x\n",
++	       odm_get_mac_reg(dm, R_0x64, MASKBYTE3));
++	path_sel_bb = odm_get_bb_reg(dm, R_0x948, MASKDWORD);
++
++	odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x99000280); /*10 od 0x948 0x1 [7] ; WL:S1 to S0;BT:S0 to S1;*/
++#if 0
++	/*RF_DBG(dm,DBG_RF_INIT, "[IQK]0x1e6@S0 TXIQK = 0x%x\n", platform_efio_read_1byte(adapter, 0x1e6));*/
++#endif
++
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	/*modify TXIQK mode table*/
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, RFREGOFFSETMASK, 0x80000);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00004);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0005d);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xBFFE0);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, RFREGOFFSETMASK, 0x00000);
++
++	/*path-A IQK setting*/
++	odm_set_bb_reg(dm, R_0xe30, MASKDWORD, 0x08008c0c);
++	odm_set_bb_reg(dm, R_0xe34, MASKDWORD, 0x38008c1c);
++	odm_set_bb_reg(dm, R_0xe38, MASKDWORD, 0x8214018a);
++	odm_set_bb_reg(dm, R_0xe3c, MASKDWORD, 0x28160200);
++	odm_set_bb_reg(dm, R_0xe40, MASKDWORD, 0x01007c00);
++	odm_set_bb_reg(dm, R_0xe44, MASKDWORD, 0x01004800);
++
++	/*LO calibration setting*/
++	odm_set_bb_reg(dm, R_0xe4c, MASKDWORD, 0x00462911);
++
++	/*PA, PAD setting*/
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, 0x800, 0x1);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x66, 0x600, 0x0);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x66, 0x1E0, 0x3);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x8d, 0x1F, 0xf);
++
++	/*LOK setting	added for 8723D*/
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, 0x10, 0x1);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x64, 0x1, 0x1);
++
++#if 1
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK, 0xe6d);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK, 0x66d);
++#endif
++
++	RF_DBG(dm, DBG_RF_IQK, "RF0x1 @S0 TXIQK = 0x%x\n",
++	       odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK));
++	RF_DBG(dm, DBG_RF_IQK, "RF0x2 @S0 TXIQK = 0x%x\n",
++	       odm_get_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK));
++	/*enter IQK mode*/
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
++#if 1
++	/*backup path & GNT value */
++	original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]OriginalGNT = 0x%x\n", original_gnt);
++
++	/*set GNT_WL=1/GNT_BT=1  and path owner to WiFi for pause BT traffic*/
++	odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x0000ff00);
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
++	odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1);
++#endif
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0054);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]GNT_BT @S0 TXIQK = 0x%x\n",
++	       odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD));
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0x948 @S0 TXIQK = 0x%x\n",
++	       odm_get_bb_reg(dm, R_0x948, MASKDWORD));
++
++	/*One shot, path S1 LOK & IQK*/
++	odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf9000000);
++	odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf8000000);
++
++	/*delay x ms*/
++#if 0
++	/*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/
++#endif
++
++	ktime = 0;
++	while ((!odm_get_bb_reg(dm, R_0xeac, BIT(26))) && ktime < 1000) {
++		ODM_delay_us(10);
++		ktime++;
++	}
++#if 1
++	/*Restore GNT_WL/GNT_BT  and path owner*/
++	odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
++	odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
++#endif
++	/*reload RF path*/
++	odm_set_bb_reg(dm, R_0x948, MASKDWORD, path_sel_bb);
++	/*leave IQK mode*/
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	/*PA/PAD controlled by 0x0*/
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, 0x800, 0x0);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, BIT(0), 0x0);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, BIT(0), 0x0);
++	/* Check failed*/
++	reg_eac_s0 = odm_get_bb_reg(dm, R_0xeac, MASKDWORD);
++	reg_e94_s0 = odm_get_bb_reg(dm, R_0xe94, MASKDWORD);
++	reg_e9c_s0 = odm_get_bb_reg(dm, R_0xe9c, MASKDWORD);
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac_s0 = 0x%x\n", reg_eac_s0);
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe94_s0 = 0x%x, 0xe9c_s0 = 0x%x\n",
++	       reg_e94_s0, reg_e9c_s0);
++	/*monitor image power before & after IQK*/
++	RF_DBG(dm, DBG_RF_IQK,
++	       "[IQK]0xe90_s0(before IQK)= 0x%x, 0xe98_s0(afer IQK) = 0x%x\n",
++	       odm_get_bb_reg(dm, R_0xe90, MASKDWORD),
++	       odm_get_bb_reg(dm, R_0xe98, MASKDWORD));
++	if (!(reg_eac_s0 & BIT(28)) &&
++	    (((reg_e94_s0 & 0x03FF0000) >> 16) != 0x142) &&
++	    (((reg_e9c_s0 & 0x03FF0000) >> 16) != 0x42))
++
++		result |= 0x01;
++	else
++		RF_DBG(dm, DBG_RF_IQK, "S0 TXIQK FAIL\n");
++
++	return result;
++}
++
++u8 phy_path_s0_rx_iqk_8723d(struct dm_struct *dm, boolean config_path_s0)
++{
++	u32 reg_e94_s0, reg_e9c_s0, reg_ea4_s0, reg_eac_s0, tmp, u4tmp;
++	u32 path_sel_bb;
++	u8 result = 0x00, cnt;
++	u16 ktime;
++	u32 original_path, original_gnt;
++
++	path_sel_bb = odm_get_bb_reg(dm, R_0x948, MASKDWORD);
++	RF_DBG(dm, DBG_RF_IQK, "path S0 RxIQK Step1!!\n");
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0x67 @S0 RXIQK1 = 0x%x\n",
++	       odm_get_mac_reg(dm, R_0x64, MASKBYTE3));
++	odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x99000280);
++#if 0
++	/*RF_DBG(dm,DBG_RF_INIT, "[IQK]0x1e6@S0 RXIQK1 = 0x%x\n", platform_efio_read_1byte(adapter, 0x1e6));*/
++#endif
++
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
++
++	odm_set_bb_reg(dm, R_0xe40, MASKDWORD, 0x01007c00);
++	odm_set_bb_reg(dm, R_0xe44, MASKDWORD, 0x01004800);
++
++	odm_set_bb_reg(dm, R_0xe30, MASKDWORD, 0x18008c1c);
++	odm_set_bb_reg(dm, R_0xe34, MASKDWORD, 0x38008c1c);
++	odm_set_bb_reg(dm, R_0xe50, MASKDWORD, 0x38008c1c);
++	odm_set_bb_reg(dm, R_0xe54, MASKDWORD, 0x38008c1c);
++
++	odm_set_bb_reg(dm, R_0xe38, MASKDWORD, 0x82160000);
++	odm_set_bb_reg(dm, R_0xe3c, MASKDWORD, 0x28160000);
++
++	odm_set_bb_reg(dm, R_0xe4c, MASKDWORD, 0x0046a911);
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, RFREGOFFSETMASK, 0x80000);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00006);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0005f);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xa7ffb);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, RFREGOFFSETMASK, 0x00000);
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, 0x800, 0x1);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x66, 0x600, 0x0);
++
++#if 1
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK, 0xe6d);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK, 0x66d);
++#endif
++
++	RF_DBG(dm, DBG_RF_IQK, "RF0x1 @S0 RXIQK1 = 0x%x\n",
++	       odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK));
++	RF_DBG(dm, DBG_RF_IQK, "RF0x2 @S0 RXIQK1 = 0x%x\n",
++	       odm_get_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK));
++
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
++
++#if 1
++	/*backup path & GNT value */
++	original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]OriginalGNT = 0x%x\n", original_gnt);
++
++	/*set GNT_WL=1/GNT_BT=1  and path owner to WiFi for pause BT traffic*/
++	odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x0000ff00);
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
++	odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1);
++#endif
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0054);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]GNT_BT @S0 RXIQK1 = 0x%x\n",
++	       odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD));
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0x948 @S0 RXIQK1 = 0x%x\n",
++	       odm_get_bb_reg(dm, R_0x948, MASKDWORD));
++
++	odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf9000000);
++	odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf8000000);
++
++#if 0
++	/*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/
++#endif
++	ktime = 0;
++	while ((!odm_get_bb_reg(dm, R_0xeac, BIT(26))) && ktime < 1000) {
++		ODM_delay_us(10);
++		ktime++;
++	}
++	reg_eac_s0 = odm_get_bb_reg(dm, R_0xeac, MASKDWORD);
++	reg_e94_s0 = odm_get_bb_reg(dm, R_0xe94, MASKDWORD);
++	reg_e9c_s0 = odm_get_bb_reg(dm, R_0xe9c, MASKDWORD);
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac_s0 = 0x%x\n", reg_eac_s0);
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe94_s0 = 0x%x, 0xe9c_s0 = 0x%x\n",
++	       reg_e94_s0, reg_e9c_s0);
++	/*monitor image power before & after IQK*/
++	RF_DBG(dm, DBG_RF_IQK,
++	       "[IQK]0xe90_s0(before IQK)= 0x%x, 0xe98_s0(afer IQK) = 0x%x\n",
++	       odm_get_bb_reg(dm, R_0xe90, MASKDWORD),
++	       odm_get_bb_reg(dm, R_0xe98, MASKDWORD));
++
++	tmp = (reg_e9c_s0 & 0x03FF0000) >> 16;
++	if ((tmp & 0x200) > 0)
++		tmp = 0x400 - tmp;
++
++	if (!(reg_eac_s0 & BIT(28)) &&
++	    (((reg_e94_s0 & 0x03FF0000) >> 16) != 0x142) &&
++	    (((reg_e9c_s0 & 0x03FF0000) >> 16) != 0x42)) {
++		result |= 0x01;
++	} else {
++		RF_DBG(dm, DBG_RF_IQK, "S0 RXIQK STEP1 FAIL\n");
++#if 1
++		/*Restore GNT_WL/GNT_BT  and path owner*/
++		odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
++		odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
++		odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
++#endif
++		/*reload RF path*/
++		odm_set_bb_reg(dm, R_0x948, MASKDWORD, path_sel_bb);
++		odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
++
++		for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++			ODM_delay_us(10);
++
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, 0x800, 0x0);
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, BIT(0), 0x0);
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, BIT(0), 0x0);
++		return result;
++	}
++
++	u4tmp = 0x80007C00 | (reg_e94_s0 & 0x3FF0000) | ((reg_e9c_s0 & 0x3FF0000) >> 16);
++	odm_set_bb_reg(dm, R_0xe40, MASKDWORD, u4tmp);
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe40_s0 = 0x%x u4tmp = 0x%x\n",
++	       odm_get_bb_reg(dm, R_0xe40, MASKDWORD), u4tmp);
++
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]path S0 RXIQK STEP2!!\n\n");
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0x67 @S0 RXIQK2 = 0x%x\n",
++	       odm_get_mac_reg(dm, R_0x64, MASKBYTE3));
++#if 0
++	/*RF_DBG(dm,DBG_RF_INIT, "[IQK]0x1e6@S0 RXIQK2 = 0x%x\n", platform_efio_read_1byte(adapter, 0x1e6));*/
++#endif
++	odm_set_bb_reg(dm, R_0xe44, MASKDWORD, 0x01004800);
++
++	odm_set_bb_reg(dm, R_0xe30, MASKDWORD, 0x38008c1c);
++	odm_set_bb_reg(dm, R_0xe34, MASKDWORD, 0x18008c1c);
++	odm_set_bb_reg(dm, R_0xe50, MASKDWORD, 0x38008c1c);
++	odm_set_bb_reg(dm, R_0xe54, MASKDWORD, 0x38008c1c);
++
++	odm_set_bb_reg(dm, R_0xe38, MASKDWORD, 0x82170000);
++	odm_set_bb_reg(dm, R_0xe3c, MASKDWORD, 0x28171400);
++
++	odm_set_bb_reg(dm, R_0xe4c, MASKDWORD, 0x0046a8d1);
++
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, 0x80000, 0x1);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00007);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0005f);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xb3fdb);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, RFREGOFFSETMASK, 0x00000);
++
++	RF_DBG(dm, DBG_RF_IQK, "RF0x1 @S0 RXIQK2 = 0x%x\n",
++	       odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK));
++	RF_DBG(dm, DBG_RF_IQK, "RF0x2 @S0 RXIQK2 = 0x%x\n",
++	       odm_get_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK));
++	/*enter IQK mode*/
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
++#if 1
++	/*backup path & GNT value */
++	original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]OriginalGNT = 0x%x\n", original_gnt);
++
++	/*set GNT_WL=1/GNT_BT=1  and path owner to WiFi for pause BT traffic*/
++	odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x0000ff00);
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
++	odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1);
++#endif
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0054);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]GNT_BT @S0 RXIQK2 = 0x%x\n",
++	       odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD));
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0x948 @S0 RXIQK2 = 0x%x\n",
++	       odm_get_bb_reg(dm, R_0x948, MASKDWORD));
++
++	odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf9000000);
++	odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf8000000);
++
++#if 0
++	/*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/
++#endif
++	ktime = 0;
++	while ((!odm_get_bb_reg(dm, R_0xeac, BIT(26))) && ktime < 1000) {
++		ODM_delay_us(1);
++		ktime++;
++	}
++#if 1
++	/*Restore GNT_WL/GNT_BT  and path owner*/
++	odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
++	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
++	odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
++#endif
++	/*reload RF path*/
++	odm_set_bb_reg(dm, R_0x948, MASKDWORD, path_sel_bb);
++
++	/*leave IQK mode*/
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, 0x800, 0x0);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, BIT(0), 0x0);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, BIT(0), 0x0);
++
++	reg_eac_s0 = odm_get_bb_reg(dm, R_0xeac, MASKDWORD);
++	reg_ea4_s0 = odm_get_bb_reg(dm, R_0xea4, MASKDWORD);
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac_s0 = 0x%x\n", reg_eac_s0);
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xea4_s0 = 0x%x, 0xeac_s0 = 0x%x\n",
++	       reg_ea4_s0, reg_eac_s0);
++
++	RF_DBG(dm, DBG_RF_IQK,
++	       "[IQK]0xea0_s0(before IQK)= 0x%x, 0xea8_s0(afer IQK) = 0x%x\n",
++	       odm_get_bb_reg(dm, R_0xea0, MASKDWORD),
++	       odm_get_bb_reg(dm, R_0xea8, MASKDWORD));
++
++	tmp = (reg_eac_s0 & 0x03FF0000) >> 16;
++	if ((tmp & 0x200) > 0)
++		tmp = 0x400 - tmp;
++
++	if (!(reg_eac_s0 & BIT(27)) && /*if Tx is OK, check whether Rx is OK*/
++	    (((reg_ea4_s0 & 0x03FF0000) >> 16) != 0x132) &&
++	    (((reg_eac_s0 & 0x03FF0000) >> 16) != 0x36) &&
++	    (((reg_ea4_s0 & 0x03FF0000) >> 16) < 0x11a) &&
++	    (((reg_ea4_s0 & 0x03FF0000) >> 16) > 0xe6) &&
++	    tmp < 0x1a)
++		result |= 0x02;
++	else
++		RF_DBG(dm, DBG_RF_IQK, "S0 RXIQK STEP2 FAIL\n");
++	return result;
++}
++
++void _phy_path_s1_fill_iqk_matrix_8723d(struct dm_struct *dm, boolean is_iqk_ok,
++					s32 result[][8], u8 final_candidate,
++					boolean is_tx_only)
++{
++	u32 oldval_1, X, TX1_A, reg;
++	s32 Y, TX1_C;
++	RF_DBG(dm, DBG_RF_IQK, "path S1 IQ Calibration %s !\n",
++	       (is_iqk_ok) ? "Success" : "Failed");
++
++	if (final_candidate == 0xFF)
++		return;
++
++	if (is_iqk_ok) {
++		oldval_1 = (odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD) >> 22) & 0x3FF;
++
++		X = result[final_candidate][0];
++
++		if ((X & 0x00000200) != 0)
++			X = X | 0xFFFFFC00;
++		TX1_A = (X * oldval_1) >> 8;
++		RF_DBG(dm, DBG_RF_IQK,
++		       "X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n", X, TX1_A,
++		       oldval_1);
++		odm_set_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0x3FF, TX1_A);
++
++		odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, BIT(31), ((X * oldval_1 >> 7) & 0x1));
++
++		Y = result[final_candidate][1];
++		if ((Y & 0x00000200) != 0)
++			Y = Y | 0xFFFFFC00;
++
++		TX1_C = (Y * oldval_1) >> 8;
++		RF_DBG(dm, DBG_RF_IQK, "Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C);
++		odm_set_bb_reg(dm, R_0xc94, 0xF0000000, ((TX1_C & 0x3C0) >> 6));
++		odm_set_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0x003F0000, (TX1_C & 0x3F));
++
++		odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, BIT(29), ((Y * oldval_1 >> 7) & 0x1));
++
++		if (is_tx_only) {
++			RF_DBG(dm, DBG_RF_IQK, "%s only Tx OK\n", __func__);
++			return;
++		}
++		reg = result[final_candidate][2];
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++		if (RTL_ABS(reg, 0x100) >= 16)
++			reg = 0x100;
++#endif
++		odm_set_bb_reg(dm, R_0xc14, 0x3FF, reg);
++
++		reg = result[final_candidate][3] & 0x3F;
++		odm_set_bb_reg(dm, R_0xc14, 0xFC00, reg);
++
++		reg = (result[final_candidate][3] >> 6) & 0xF;
++		odm_set_bb_reg(dm, R_0xca0, 0xF0000000, reg);
++
++		/* 10 os 7201 10
++		 * 10 id ea4 [25:16] p
++		 * 10 os 7202 10
++		 * 10 od c14 VarFromTmp [9:0] p
++		 *
++		 * 10 os 7201 11
++		 * 10 id eac [25:22] p
++		 * 10 os 7202 11
++		 * 10 od ca0 VarFromTmp [31:28] p
++		 *
++		 * 10 os 7201 12
++		 * 10 id eac [21:16] p
++		 * 10 os 7202 12
++		 * 10 od c14 VarFromTmp [15:10] p
++		 */
++	}
++}
++
++void _phy_path_s0_fill_iqk_matrix_8723d(struct dm_struct *dm, boolean is_iqk_ok,
++					s32 result[][8], u8 final_candidate,
++					boolean is_tx_only)
++{
++	u32 oldval_0, X, TX0_A, reg;
++	s32 Y, TX0_C;
++	RF_DBG(dm, DBG_RF_IQK, "path S0 IQ Calibration %s !\n",
++	       (is_iqk_ok) ? "Success" : "Failed");
++
++	if (final_candidate == 0xFF)
++		return;
++
++	if (is_iqk_ok) {
++		oldval_0 = (odm_get_bb_reg(dm, R_0xcd4, MASKDWORD) >> 13) & 0x3FF;
++
++		X = result[final_candidate][4];
++		if ((X & 0x00000200) != 0)
++			X = X | 0xFFFFFC00;
++		TX0_A = (X * oldval_0) >> 8;
++		RF_DBG(dm, DBG_RF_IQK,
++		       "X = 0x%x, TX0_A = 0x%x, oldval_0 0x%x\n", X, TX0_A,
++		       oldval_0);
++		odm_set_bb_reg(dm, R_0xcd0, 0x7FE, TX0_A);
++
++		odm_set_bb_reg(dm, R_0xcd0, BIT(0), ((X * oldval_0 >> 7) & 0x1));
++
++		Y = result[final_candidate][5];
++		if ((Y & 0x00000200) != 0)
++			Y = Y | 0xFFFFFC00;
++
++		TX0_C = (Y * oldval_0) >> 8;
++		RF_DBG(dm, DBG_RF_IQK, "Y = 0x%x, TX0_C = 0x%x\n", Y, TX0_C);
++		odm_set_bb_reg(dm, R_0xcd4, 0x7FE, (TX0_C & 0x3FF));
++
++		odm_set_bb_reg(dm, R_0xcd4, BIT(0), ((Y * oldval_0 >> 7) & 0x1));
++
++		if (is_tx_only)
++			return;
++
++		reg = result[final_candidate][6];
++		odm_set_bb_reg(dm, R_0xcd8, 0x3FF, reg);
++
++		reg = result[final_candidate][7];
++		odm_set_bb_reg(dm, R_0xcd8, 0x003FF000, reg);
++
++		/*10 os 7201 10
++		 *10 id ea4 [25:16] p
++		 *10 os 7202 10
++		 *10 od cd8 VarFromTmp [9:0] p
++		 *
++		 *10 os 7201 11
++		 *10 id eac [25:16] p
++		 *10 os 7202 11
++		 *10 od cd8 VarFromTmp [21:12] p
++		 *		rege94_s1 = result[i][0];
++		 *		rege9c_s1 = result[i][1];
++		 *		regea4_s1 = result[i][2];
++		 *		regeac_s1 = result[i][3];
++		 *		rege94_s0 = result[i][4];
++		 *		rege9c_s0 = result[i][5];
++		 *		regea4_s0 = result[i][6];
++		 *		regeac_s0 = result[i][7];
++		 */
++	}
++}
++
++void _phy_save_adda_registers_8723d(struct dm_struct *dm, u32 *adda_reg,
++				    u32 *adda_backup, u32 register_num)
++{
++	u32 i;
++
++	for (i = 0; i < register_num; i++)
++		adda_backup[i] = odm_get_bb_reg(dm, adda_reg[i], MASKDWORD);
++}
++
++void _phy_save_mac_registers_8723d(struct dm_struct *dm, u32 *mac_reg,
++				   u32 *mac_backup)
++{
++	u32 i;
++
++	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
++		mac_backup[i] = odm_read_1byte(dm, mac_reg[i]);
++	mac_backup[i] = odm_read_4byte(dm, mac_reg[i]);
++}
++
++void _phy_reload_adda_registers_8723d(struct dm_struct *dm, u32 *adda_reg,
++				      u32 *adda_backup, u32 regiester_num)
++{
++	u32 i;
++
++	RF_DBG(dm, DBG_RF_IQK, "Reload ADDA power saving parameters !\n");
++	for (i = 0; i < regiester_num; i++)
++		odm_set_bb_reg(dm, adda_reg[i], MASKDWORD, adda_backup[i]);
++}
++
++void _phy_reload_mac_registers_8723d(struct dm_struct *dm, u32 *mac_reg,
++				     u32 *mac_backup)
++{
++	u32 i;
++
++	RF_DBG(dm, DBG_RF_IQK, "Reload MAC parameters !\n");
++	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
++		odm_write_1byte(dm, mac_reg[i], (u8)mac_backup[i]);
++	odm_write_4byte(dm, mac_reg[i], mac_backup[i]);
++}
++
++void _phy_path_adda_on_8723d(struct dm_struct *dm, u32 *adda_reg,
++			     boolean is_path_a_on, boolean is2T)
++{
++	u32 path_on;
++	u32 i;
++
++	path_on = is_path_a_on ? 0x03c00016 : 0x03c00016;
++
++	if (!is2T) {
++		path_on = 0x03c00016;
++		odm_set_bb_reg(dm, adda_reg[0], MASKDWORD, 0x03c00016);
++	} else {
++		odm_set_bb_reg(dm, adda_reg[0], MASKDWORD, path_on);
++	}
++
++	for (i = 1; i < IQK_ADDA_REG_NUM; i++)
++		odm_set_bb_reg(dm, adda_reg[i], MASKDWORD, path_on);
++}
++
++void _phy_mac_setting_calibration_8723d(struct dm_struct *dm, u32 *mac_reg,
++					u32 *mac_backup)
++{
++#if 0
++	/*
++		odm_write_1byte(dm, mac_reg[i], 0x3F);
++
++		for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){
++			odm_write_1byte(dm, mac_reg[i], (u8)(mac_backup[i]&(~BIT(3))));
++		}
++		odm_write_1byte(dm, mac_reg[i], (u8)(mac_backup[i]&(~BIT(5))));
++	*/
++
++	/*odm_set_bb_reg(dm, R_0x522, MASKBYTE0, 0x7f);*/
++	/*odm_set_bb_reg(dm, R_0x550, MASKBYTE0, 0x15);*/
++	/*odm_set_bb_reg(dm, R_0x551, MASKBYTE0, 0x00);*/
++#endif
++	odm_set_bb_reg(dm, R_0x520, 0x00ff0000, 0xff);
++}
++
++void _phy_path_a_stand_by_8723d(struct dm_struct *dm)
++{
++	u8 cnt;
++
++	RF_DBG(dm, DBG_RF_IQK, "path-S1 standby mode!\n");
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
++#if 0
++	/*	odm_set_bb_reg(dm, R_0x840, MASKDWORD, 0x00010000);*/
++#endif
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	odm_set_rf_reg(dm, (enum rf_path)0x0, RF_0x0, RFREGOFFSETMASK, 0x10000);
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
++}
++
++void _phy_path_b_stand_by_8723d(struct dm_struct *dm)
++{
++	u8 cnt;
++
++	RF_DBG(dm, DBG_RF_IQK, "path-S0 standby mode!\n");
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
++
++	for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++		ODM_delay_us(10);
++
++	odm_set_rf_reg(dm, (enum rf_path)0x1, RF_0x0, RFREGOFFSETMASK, 0x10000);
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
++}
++
++void _phy_pi_mode_switch_8723d(struct dm_struct *dm, boolean pi_mode)
++{
++	u32 mode;
++
++	mode = pi_mode ? 0x01000100 : 0x01000000;
++	odm_set_bb_reg(dm, R_0x820, MASKDWORD, mode);
++	odm_set_bb_reg(dm, R_0x828, MASKDWORD, mode);
++}
++
++boolean
++phy_simularity_compare_8723d(struct dm_struct *dm, s32 result[][8], u8 c1,
++			     u8 c2, boolean is2t)
++{
++	u32 i, j, diff, simularity_bit_map, bound = 0;
++	u8 final_candidate[2] = {0xFF, 0xFF};
++	boolean is_result = true;
++#if 0
++	/*#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)*/
++	/*	bool		is2T = IS_92C_SERIAL( hal_data->version_id);*/
++	/*#else*/
++#endif
++#if 0
++	/*#endif*/
++#endif
++
++	s32 tmp1 = 0, tmp2 = 0;
++
++	if (is2t)
++		bound = 8;
++	else
++		bound = 4;
++
++	RF_DBG(dm, DBG_RF_IQK, "===> IQK:%s c1 %d c2 %d!!!\n", __func__, c1,
++	       c2);
++
++	simularity_bit_map = 0;
++
++	for (i = 0; i < bound; i++) {
++		if (i == 1 || i == 3 || i == 5 || i == 7) {
++			if ((result[c1][i] & 0x00000200) != 0)
++				tmp1 = result[c1][i] | 0xFFFFFC00;
++			else
++				tmp1 = result[c1][i];
++
++			if ((result[c2][i] & 0x00000200) != 0)
++				tmp2 = result[c2][i] | 0xFFFFFC00;
++			else
++				tmp2 = result[c2][i];
++		} else {
++			tmp1 = result[c1][i];
++			tmp2 = result[c2][i];
++		}
++
++		diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
++
++		if (diff > MAX_TOLERANCE) {
++			RF_DBG(dm, DBG_RF_IQK,
++			       "IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n",
++			       diff, i, result[c1][i], result[c2][i]);
++
++			if ((i == 2 || i == 6) && !simularity_bit_map) {
++				if (result[c1][i] + result[c1][i + 1] == 0)
++					final_candidate[(i / 4)] = c2;
++				else if (result[c2][i] + result[c2][i + 1] == 0)
++					final_candidate[(i / 4)] = c1;
++				else
++					simularity_bit_map = simularity_bit_map | (1 << i);
++			} else {
++				simularity_bit_map = simularity_bit_map | (1 << i);
++			}
++		}
++	}
++
++	RF_DBG(dm, DBG_RF_IQK, "IQK:%s simularity_bit_map   %x !!!\n", __func__,
++	       simularity_bit_map);
++
++	if (simularity_bit_map == 0) {
++		for (i = 0; i < (bound / 4); i++) {
++			if (final_candidate[i] != 0xFF) {
++				for (j = i * 4; j < (i + 1) * 4 - 2; j++)
++					result[3][j] = result[final_candidate[i]][j];
++				is_result = false;
++			}
++		}
++		return is_result;
++	}
++
++	if (!(simularity_bit_map & 0x03)) {
++		for (i = 0; i < 2; i++)
++			result[3][i] = result[c1][i];
++	}
++
++	if (!(simularity_bit_map & 0x0c)) {
++		for (i = 2; i < 4; i++)
++			result[3][i] = result[c1][i];
++	}
++
++	if (!(simularity_bit_map & 0x30)) {
++		for (i = 4; i < 6; i++)
++			result[3][i] = result[c1][i];
++	}
++
++	if (!(simularity_bit_map & 0xc0)) {
++		for (i = 6; i < 8; i++)
++			result[3][i] = result[c1][i];
++	}
++
++	return false;
++}
++
++void _phy_check_coex_status_8723d(struct dm_struct *dm, boolean beforek)
++{
++#if MP_DRIVER != 1
++	u8 u1b_tmp;
++	u16 count = 0;
++	u8 h2c_parameter;
++
++	if (beforek) {
++		/* Set H2C cmd to inform FW (enable). */
++		h2c_parameter = 1;
++		odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
++		/* Check 0x1e6 or 100ms timeout*/
++		count = 0;
++		u1b_tmp = odm_read_1byte(dm, 0x1e6);
++		while (u1b_tmp != 0x1 && count < 5000) {
++			ODM_delay_us(20);
++			u1b_tmp = odm_read_1byte(dm, 0x1e6);
++			count++;
++		}
++
++		if (count >= 5000)
++			RF_DBG(dm, DBG_RF_INIT,
++			       "[IQK]Polling 0x1e6 to 1 for WiFi calibration H2C cmd FAIL! count(%d)",
++			       count);
++
++		/* Wait BT IQK finished. */
++		/* polling 0x1e7[0]=1 or 600ms timeout */
++		count = 0;
++		u1b_tmp = odm_read_1byte(dm, 0x1e7);
++		while ((!(u1b_tmp & BIT(0))) && count < 30000) {
++			ODM_delay_us(20);
++			u1b_tmp = odm_read_1byte(dm, 0x1e7);
++			count++;
++		}
++
++		if (count >= 30000)
++			RF_DBG(dm, DBG_RF_INIT,
++			       "[IQK]Waiting BT IQK finish time out! count(%d)",
++			       count);
++	} else {
++		/* Set H2C cmd to inform FW (disable). */
++		h2c_parameter = 0;
++		odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
++		/* Check 0x1e6 or 100ms timeout*/
++		count = 0;
++		u1b_tmp = odm_read_1byte(dm, 0x1e6);
++		while (u1b_tmp != 0 && count < 5000) {
++			ODM_delay_us(20);
++			u1b_tmp = odm_read_1byte(dm, 0x1e6);
++			count++;
++		}
++
++		if (count >= 1000)
++			RF_DBG(dm, DBG_RF_INIT,
++			       "[IQK]Polling 0x1e6 to 0 for WiFi calibration H2C cmd FAIL! count(%d)",
++			       count);
++	}
++#endif
++}
++
++void _phy_iq_calibrate_8723d(struct dm_struct *dm, s32 result[][8], u8 t,
++			     boolean is2T)
++{
++	u32 i;
++	u8 path_s1_ok = 0x0, path_s0_ok = 0x0, cnt;
++	u8 tmp0xc50 = (u8)odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
++	u8 tmp0xc58 = (u8)odm_get_bb_reg(dm, R_0xc58, MASKBYTE0);
++	u32 ADDA_REG[IQK_ADDA_REG_NUM] = {
++		R_0x85c, R_0xe6c,
++		R_0xe70, R_0xe74,
++		R_0xe78, R_0xe7c,
++		R_0xe80, R_0xe84,
++		R_0xe88, R_0xe8c,
++		R_0xed0, R_0xed4,
++		R_0xed8, R_0xedc,
++		R_0xee0, R_0xeec};
++	u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = {
++		R_0x522, R_0x550,
++		R_0x551, R_0x40};
++
++	u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
++		R_0xc04, R_0xc08,
++		R_0x874, R_0xb68, R_0xb6c,
++		R_0x870, R_0x860,
++		R_0x864, R_0xa04};
++	u32 cnt_iqk_fail = 0;
++	u32 retry_count;
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	retry_count = 2;
++#elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++#if MP_DRIVER
++	retry_count = 9;
++#else
++	retry_count = 2;
++#endif
++#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
++	if (*dm->mp_mode)
++		retry_count = 9;
++	else
++		retry_count = 2;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++#ifdef MP_TEST
++	if (*dm->mp_mode)
++		retry_count = 9;
++#endif
++#endif
++
++	if (t == 0) {
++		_phy_save_adda_registers_8723d(dm, ADDA_REG, dm->rf_calibrate_info.ADDA_backup, IQK_ADDA_REG_NUM);
++		_phy_save_mac_registers_8723d(dm, IQK_MAC_REG, dm->rf_calibrate_info.IQK_MAC_backup);
++		_phy_save_adda_registers_8723d(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup, IQK_BB_REG_NUM);
++	}
++	RF_DBG(dm, DBG_RF_IQK, "IQ Calibration for 1T1R_S0/S1 for %d times\n",
++	       t);
++
++	_phy_path_adda_on_8723d(dm, ADDA_REG, true, is2T);
++#if 0
++	if (t == 0)
++		dm->rf_calibrate_info.is_rf_pi_enable = (u8)odm_get_bb_reg(dm, R_0x820, BIT(8));
++
++	if (!dm->rf_calibrate_info.is_rf_pi_enable) {
++		/*  Switch BB to PI mode to do IQ Calibration. */
++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
++		_phy_pi_mode_switch_8723d(adapter, true);
++#else
++		_phy_pi_mode_switch_8723d(dm, true);
++#endif
++	}
++#endif
++	_phy_mac_setting_calibration_8723d(dm, IQK_MAC_REG, dm->rf_calibrate_info.IQK_MAC_backup);
++	/*BB setting*/
++#if 0
++	/*odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT24, 0x00);*/
++#endif
++	odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0xf);
++	odm_set_bb_reg(dm, R_0xc04, MASKDWORD, 0x03a05611);
++	odm_set_bb_reg(dm, R_0xc08, MASKDWORD, 0x000800e4);
++	odm_set_bb_reg(dm, R_0x874, MASKDWORD, 0x25204200);
++
++	/*IQ calibration setting*/
++#if 0
++	/*RF_DBG(dm,DBG_RF_IQK, "IQK setting!\n");	*/
++#endif
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
++	odm_set_bb_reg(dm, R_0xe40, MASKDWORD, 0x01007c00);
++	odm_set_bb_reg(dm, R_0xe44, MASKDWORD, 0x01004800);
++
++	if (is2T) {
++		_phy_path_b_stand_by_8723d(dm);
++		_phy_path_adda_on_8723d(dm, ADDA_REG, false, is2T);
++	}
++
++#if 1
++	for (i = 0; i < retry_count; i++) {
++		path_s1_ok = phy_path_s1_iqk_8723d(dm, is2T);
++		if (path_s1_ok == 0x01) {
++			RF_DBG(dm, DBG_RF_IQK, "path S1 Tx IQK Success!!\n");
++			result[t][0] = (odm_get_bb_reg(dm, R_0xe94, MASKDWORD) & 0x3FF0000) >> 16;
++			result[t][1] = (odm_get_bb_reg(dm, R_0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
++			break;
++		}
++
++		RF_DBG(dm, DBG_RF_IQK, "path S1 Tx IQK Fail!!\n");
++		result[t][0] = 0x100;
++		result[t][1] = 0x0;
++		cnt_iqk_fail++;
++#if 0
++		else if (i == (retry_count - 1) && path_s1_ok == 0x01) {
++			RT_DISP(FINIT, INIT_IQK, ("path S1 IQK Only  Tx Success!!\n"));
++
++			result[t][0] = (odm_get_bb_reg(dm, R_0xe94, MASKDWORD) & 0x3FF0000) >> 16;
++			result[t][1] = (odm_get_bb_reg(dm, R_0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
++		}
++#endif
++	}
++#endif
++#if 1
++	for (i = 0; i < retry_count; i++) {
++		path_s1_ok = phy_path_s1_rx_iqk_8723d(dm, is2T);
++		if (path_s1_ok == 0x03) {
++			RF_DBG(dm, DBG_RF_IQK, "path S1 Rx IQK Success!!\n");
++			result[t][2] = (odm_get_bb_reg(dm, R_0xea4, MASKDWORD) & 0x3FF0000) >> 16;
++			result[t][3] = (odm_get_bb_reg(dm, R_0xeac, MASKDWORD) & 0x3FF0000) >> 16;
++			break;
++		}
++
++		RF_DBG(dm, DBG_RF_IQK, "path S1 Rx IQK Fail!!\n");
++		result[t][2] = 0x100;
++		result[t][3] = 0x0;
++		cnt_iqk_fail++;
++	}
++
++	if (path_s1_ok == 0x00)
++		RF_DBG(dm, DBG_RF_IQK, "path S1 IQK failed!!\n");
++#endif
++	if (is2T) {
++		_phy_path_a_stand_by_8723d(dm);
++		_phy_path_adda_on_8723d(dm, ADDA_REG, false, is2T);
++
++		odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
++		odm_set_bb_reg(dm, R_0xe40, MASKDWORD, 0x01007c00);
++		odm_set_bb_reg(dm, R_0xe44, MASKDWORD, 0x01004800);
++
++#if 1
++		for (i = 0; i < retry_count; i++) {
++			path_s0_ok = phy_path_s0_iqk_8723d(dm);
++			if (path_s0_ok == 0x01) {
++				RF_DBG(dm, DBG_RF_IQK,
++				       "path S0 Tx IQK Success!!\n");
++				result[t][4] = (odm_get_bb_reg(dm, R_0xe94, MASKDWORD) & 0x3FF0000) >> 16;
++				result[t][5] = (odm_get_bb_reg(dm, R_0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
++				break;
++			}
++
++			RF_DBG(dm, DBG_RF_IQK, "path S0 Tx IQK Fail!!\n");
++			result[t][4] = 0x100;
++			result[t][5] = 0x0;
++			cnt_iqk_fail++;
++#if 0
++			else if (i == (retry_count - 1) && path_s1_ok == 0x01) {
++				RT_DISP(FINIT, INIT_IQK, ("path S0 IQK Only  Tx Success!!\n"));
++
++				result[t][0] = (odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_B, MASKDWORD) & 0x3FF0000) >> 16;
++				result[t][1] = (odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_B, MASKDWORD) & 0x3FF0000) >> 16;
++			}
++#endif
++		}
++#endif
++
++#if 1
++		for (i = 0; i < retry_count; i++) {
++			path_s0_ok = phy_path_s0_rx_iqk_8723d(dm, is2T);
++			if (path_s0_ok == 0x03) {
++				RF_DBG(dm, DBG_RF_IQK,
++				       "path S0 Rx IQK Success!!\n");
++#if 0
++				/*				result[t][0] = (odm_get_bb_reg(dm, R_0xe94, MASKDWORD)&0x3FF0000)>>16;*/
++				/*				result[t][1] = (odm_get_bb_reg(dm, R_0xe9c, MASKDWORD)&0x3FF0000)>>16;*/
++#endif
++				result[t][6] = (odm_get_bb_reg(dm, R_0xea4, MASKDWORD) & 0x3FF0000) >> 16;
++				result[t][7] = (odm_get_bb_reg(dm, R_0xeac, MASKDWORD) & 0x3FF0000) >> 16;
++				break;
++			}
++
++			RF_DBG(dm, DBG_RF_IQK, "path S0 Rx IQK Fail!!\n");
++			result[t][6] = 0x100;
++			result[t][7] = 0x0;
++			cnt_iqk_fail++;
++		}
++
++		if (path_s0_ok == 0x00)
++			RF_DBG(dm, DBG_RF_IQK, "path S0 IQK failed!!\n");
++#endif
++	}
++	RF_DBG(dm, DBG_RF_IQK, "IQK:Back to BB mode, load original value!\n");
++	odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
++
++		for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++			ODM_delay_us(10);
++
++	if (t != 0) {
++		_phy_reload_adda_registers_8723d(dm, ADDA_REG, dm->rf_calibrate_info.ADDA_backup, IQK_ADDA_REG_NUM);
++		/* Reload MAC parameters*/
++		_phy_reload_mac_registers_8723d(dm, IQK_MAC_REG, dm->rf_calibrate_info.IQK_MAC_backup);
++		_phy_reload_adda_registers_8723d(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup, IQK_BB_REG_NUM);
++
++		odm_set_bb_reg(dm, R_0xc50, MASKBYTE0, 0x50);
++		odm_set_bb_reg(dm, R_0xc50, MASKBYTE0, tmp0xc50);
++		if (is2T) {
++			odm_set_bb_reg(dm, R_0xc58, MASKBYTE0, 0x50);
++			odm_set_bb_reg(dm, R_0xc58, MASKBYTE0, tmp0xc58);
++		}
++		odm_set_bb_reg(dm, R_0xe30, MASKDWORD, 0x01008c00);
++		odm_set_bb_reg(dm, R_0xe34, MASKDWORD, 0x01008c00);
++	}
++	dm->n_iqk_cnt++;
++	if (cnt_iqk_fail == 0)
++		dm->n_iqk_ok_cnt++;
++	else
++		dm->n_iqk_fail_cnt = dm->n_iqk_fail_cnt + cnt_iqk_fail;
++	RF_DBG(dm, DBG_RF_IQK, "%s <==\n", __func__);
++}
++
++void _phy_lc_calibrate_8723d(struct dm_struct *dm, boolean is2T)
++{
++	u8 tmp_reg;
++	u32 lc_cal, cnt;
++	u16 i;
++
++	tmp_reg = odm_read_1byte(dm, 0xd03);
++	if ((tmp_reg & 0x70) != 0)
++		odm_write_1byte(dm, 0xd03, tmp_reg & 0x8F);
++	else
++		odm_write_1byte(dm, REG_TXPAUSE, 0xFF);
++	/*backup RF0x18*/
++	lc_cal = odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK);
++	/*Start LCK*/
++	odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000);
++	for (cnt = 0; cnt < 100; cnt++) {
++		if (odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
++			break;
++		for (i = 0; i < 1000; i++) /*delay 10ms*/
++			ODM_delay_us(10);
++	}
++	if (cnt == 100)
++		RF_DBG(dm, DBG_RF_LCK, "LCK time out\n");
++	/* Recover channel number*/
++	odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal);
++	/*Restore original situation*/
++	if ((tmp_reg & 0x70) != 0)
++		odm_write_1byte(dm, 0xd03, tmp_reg);
++	else
++		odm_write_1byte(dm, REG_TXPAUSE, 0x00);
++}
++
++/* IQK version:0x2    20171109*/
++
++void phy_iq_calibrate_8723d(void *dm_void, boolean is_recovery)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	s32 result[4][8];
++	u8 i, final_candidate, indexforchannel, cnt;
++	boolean is_path_s1_ok, is_path_s0_ok;
++	s32 rege94_s1, rege9c_s1, regea4_s1, regeac_s1, rege94_s0, rege9c_s0, regea4_s0, regeac_s0, reg_tmp = 0;
++	s32 regc80, regc94, regc14, regca0, regcd0, regcd4, regcd8;
++	boolean is12simular, is13simular, is23simular;
++	u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
++		R_0xc14, R_0xc1c,
++		R_0xc4c, R_0xc78,
++		R_0xc80, R_0xc88,
++		R_0xc94, R_0xc9c,
++		R_0xca0};
++	u32 path_sel_bb_phy_iqk;
++	u32 original_path, original_gnt, ori_path_ctrl;
++	u32 iqk_fail_b, iqk_fail_a;
++
++#if 1
++	RF_DBG(dm, DBG_RF_IQK,
++	       "================ IQK Start ===================\n");
++
++	iqk_fail_b = dm->n_iqk_fail_cnt;
++
++	RF_DBG(dm, DBG_RF_INIT, "=====>%s\n", __func__);
++
++	path_sel_bb_phy_iqk = odm_get_bb_reg(dm, R_0x948, MASKDWORD);
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
++	if (is_recovery) {
++#else
++	if (is_recovery && !dm->is_in_hct_test) {
++#endif
++		RF_DBG(dm, DBG_RF_INIT, "%s: Return due to is_recovery!\n",
++		       __func__);
++		_phy_reload_adda_registers_8723d(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup_recover, 9);
++		return;
++	}
++	/*Check & wait if BT is doing IQK*/
++	if (!(*dm->mp_mode))
++		_phy_check_coex_status_8723d(dm, true);
++
++	RF_DBG(dm, DBG_RF_IQK, "IQK:Start!!!\n");
++	odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
++	dm->rf_calibrate_info.is_iqk_in_progress = true;
++	odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
++
++	for (i = 0; i < 8; i++) {
++		result[0][i] = 0;
++		result[1][i] = 0;
++		result[2][i] = 0;
++		result[3][i] = 0;
++	}
++
++	final_candidate = 0xff;
++	is_path_s1_ok = false;
++	is_path_s0_ok = false;
++	is12simular = false;
++	is23simular = false;
++	is13simular = false;
++
++	for (i = 0; i < 3; i++) {
++#if 1
++		/*set path control to WL*/
++		ori_path_ctrl = odm_get_mac_reg(dm, R_0x64, MASKBYTE3); /*save 0x67*/
++		RF_DBG(dm, DBG_RF_IQK, "[IQK]original 0x67 = 0x%x\n",
++		       ori_path_ctrl);
++		odm_set_mac_reg(dm, R_0x64, BIT(31), 0x1);
++		RF_DBG(dm, DBG_RF_IQK, "[IQK]set 0x67 = 0x%x\n",
++		       odm_get_mac_reg(dm, R_0x64, MASKBYTE3));
++		/*backup path & GNT value */
++		original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
++		odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
++
++		for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
++			ODM_delay_us(10);
++
++		original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
++		RF_DBG(dm, DBG_RF_IQK, "[IQK]OriginalGNT = 0x%x\n",
++		       original_gnt);
++		/*set GNT_WL=1/GNT_BT=1  and path owner to WiFi for pause BT traffic*/
++		odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x0000ff00);
++		odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
++		odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1);
++#endif
++		_phy_iq_calibrate_8723d(dm, result, i, true);
++#if 1
++		/*Restore GNT_WL/GNT_BT  and path owner*/
++		odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
++		odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
++		odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
++		/*Restore path control owner*/
++		odm_set_mac_reg(dm, R_0x64, MASKBYTE3, ori_path_ctrl);
++		RF_DBG(dm, DBG_RF_IQK, "[IQK]restore 0x67 = 0x%x\n",
++		       odm_get_mac_reg(dm, R_0x64, MASKBYTE3));
++#endif
++		if (i == 1) {
++			is12simular = phy_simularity_compare_8723d(dm, result, 0, 1, true);
++			if (is12simular) {
++				final_candidate = 0;
++				RF_DBG(dm, DBG_RF_IQK,
++				       "IQK: is12simular final_candidate is %x\n",
++				       final_candidate);
++				break;
++			}
++		}
++
++		if (i == 2) {
++			is13simular = phy_simularity_compare_8723d(dm, result, 0, 2, true);
++			if (is13simular) {
++				final_candidate = 0;
++				RF_DBG(dm, DBG_RF_IQK,
++				       "IQK: is13simular final_candidate is %x\n",
++				       final_candidate);
++
++				break;
++			}
++			is23simular = phy_simularity_compare_8723d(dm, result, 1, 2, true);
++			if (is23simular) {
++				final_candidate = 1;
++				RF_DBG(dm, DBG_RF_IQK,
++				       "IQK: is23simular final_candidate is %x\n",
++				       final_candidate);
++			} else {
++				for (i = 0; i < 8; i++)
++					reg_tmp += result[3][i];
++
++				if (reg_tmp != 0)
++					final_candidate = 3;
++				else
++					final_candidate = 0xFF;
++			}
++		}
++	}
++
++	for (i = 0; i < 4; i++) {
++		rege94_s1 = result[i][0];
++		rege9c_s1 = result[i][1];
++		regea4_s1 = result[i][2];
++		regeac_s1 = result[i][3];
++		rege94_s0 = result[i][4];
++		rege9c_s0 = result[i][5];
++		regea4_s0 = result[i][6];
++		regeac_s0 = result[i][7];
++		RF_DBG(dm, DBG_RF_IQK,
++		       "[IQK] rege94_s1=%x rege9c_s1=%x regea4_s1=%x regeac_s1=%x rege94_s0=%x rege9c_s0=%x regea4_s0=%x regeac_s0=%x\n ",
++		       rege94_s1, rege9c_s1, regea4_s1, regeac_s1, rege94_s0,
++		       rege9c_s0, regea4_s0, regeac_s0);
++	}
++
++	if (final_candidate != 0xff) {
++		dm->rf_calibrate_info.rege94 = result[final_candidate][0];
++		rege94_s1 = result[final_candidate][0];
++		dm->rf_calibrate_info.rege9c = result[final_candidate][1];
++		rege9c_s1 = result[final_candidate][1];
++		regea4_s1 = result[final_candidate][2];
++		regeac_s1 = result[final_candidate][3];
++		dm->rf_calibrate_info.regeb4 = result[final_candidate][4];
++		rege94_s0 = result[final_candidate][4];
++		dm->rf_calibrate_info.regebc = result[final_candidate][5];
++		rege9c_s0 = result[final_candidate][5];
++		regea4_s0 = result[final_candidate][6];
++		regeac_s0 = result[final_candidate][7];
++		RF_DBG(dm, DBG_RF_IQK, "[IQK] final_candidate is %x\n",
++		       final_candidate);
++		RF_DBG(dm, DBG_RF_IQK,
++		       "[IQK] TX1_X=%x TX1_Y=%x RX1_X=%x RX1_Y=%x TX0_X=%x TX0_Y=%x RX0_X=%x RX0_Y=%x\n ",
++		       rege94_s1, rege9c_s1, regea4_s1, regeac_s1, rege94_s0,
++		       rege9c_s0, regea4_s0, regeac_s0);
++		is_path_s1_ok = true;
++		is_path_s0_ok = true;
++	} else {
++		RF_DBG(dm, DBG_RF_IQK, "[IQK] FAIL use default value\n");
++		dm->rf_calibrate_info.rege94 = 0x100;
++		dm->rf_calibrate_info.regeb4 = 0x100;
++		dm->rf_calibrate_info.rege9c = 0x0;
++		dm->rf_calibrate_info.regebc = 0x0;
++	}
++
++	if (rege94_s1 != 0)
++		_phy_path_s1_fill_iqk_matrix_8723d(dm, is_path_s1_ok, result, final_candidate, (regea4_s1 == 0));
++	if (rege94_s0 != 0)
++		_phy_path_s0_fill_iqk_matrix_8723d(dm, is_path_s0_ok, result, final_candidate, (regea4_s0 == 0));
++
++	iqk_fail_a = dm->n_iqk_fail_cnt;
++	if (iqk_fail_a - iqk_fail_b > 0)
++		RF_DBG(dm, DBG_RF_IQK,
++		       "[8723dIQK]n_iqk_fail_cnt+,IQK restore to default value !\n");
++
++	regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
++	regc94 = odm_get_bb_reg(dm, R_0xc94, MASKDWORD);
++	regc14 = odm_get_bb_reg(dm, R_0xc14, MASKDWORD);
++	regca0 = odm_get_bb_reg(dm, R_0xca0, MASKDWORD);
++	RF_DBG(dm, DBG_RF_IQK,
++	       "[IQK]0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n",
++	       regc80, regc94, regc14, regca0);
++
++	regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);
++	regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);
++	regcd8 = odm_get_bb_reg(dm, R_0xcd8, MASKDWORD);
++	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n",
++	       regcd0, regcd4, regcd8);
++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
++	indexforchannel = odm_get_right_chnl_place_for_iqk(*dm->channel);
++#else
++	indexforchannel = 0;
++#endif
++
++	if (final_candidate < 4) {
++		for (i = 0; i < iqk_matrix_reg_num; i++)
++			dm->rf_calibrate_info.iqk_matrix_reg_setting[indexforchannel].value[0][i] = result[final_candidate][i];
++		dm->rf_calibrate_info.iqk_matrix_reg_setting[indexforchannel].is_iqk_done = true;
++	}
++	RF_DBG(dm, DBG_RF_IQK, "\nIQK OK indexforchannel %d.\n",
++	       indexforchannel);
++	_phy_save_adda_registers_8723d(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup_recover, IQK_BB_REG_NUM);
++
++	if (!(*dm->mp_mode))
++		_phy_check_coex_status_8723d(dm, false);
++
++	odm_set_bb_reg(dm, R_0x948, MASKDWORD, path_sel_bb_phy_iqk);
++	RF_DBG(dm, DBG_RF_IQK, "IQK finished\n");
++#endif
++}
++
++void phy_lc_calibrate_8723d(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	_phy_lc_calibrate_8723d(dm, false);
++}
++
++#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
++void _phy_set_rf_path_switch_8723d(struct dm_struct *dm,
++#else
++void _phy_set_rf_path_switch_8723d(void *adapter,
++#endif
++				   boolean is_main, boolean is2T)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++#endif
++
++	if (is_main)
++		odm_set_mac_reg(dm, R_0x7c4, MASKLWORD, 0x7700);
++	else
++		odm_set_mac_reg(dm, R_0x7c4, MASKLWORD, 0xDD00);
++
++	odm_set_mac_reg(dm, R_0x7c0, MASKDWORD, 0xC00F0038);
++	odm_set_mac_reg(dm, R_0x70, BIT(26), 1);
++	odm_set_mac_reg(dm, R_0x64, BIT(31), 1);
++}
++
++
++#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
++void phy_set_rf_path_switch_8723d(struct dm_struct *dm,
++#else
++void phy_set_rf_path_switch_8723d(void *adapter,
++#endif
++				  boolean is_main)
++{
++#if DISABLE_BB_RF
++	return;
++#endif
++
++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	_phy_set_rf_path_switch_8723d(dm, is_main, true);
++#else
++	_phy_set_rf_path_switch_8723d(adapter, is_main, true);
++#endif
++#endif
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++boolean _phy_query_rf_path_switch_8723d(
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	struct dm_struct *dm,
++#else
++	ADAPTER *adapter,
++#endif
++	boolean is2T)
++{
++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	struct dm_struct *dm = &hal_data->odmpriv;
++#endif
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++#endif
++#endif
++
++	if (odm_get_bb_reg(dm, R_0x7c4, MASKLWORD) == 0x7700)
++		return true;
++	else
++		return false;
++}
++
++boolean phy_query_rf_path_switch_8723d(
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	struct dm_struct *dm
++#else
++	void *adapter
++#endif
++	)
++{
++#if DISABLE_BB_RF
++	return true;
++#endif
++
++#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
++	return _phy_query_rf_path_switch_8723d(adapter, false);
++#else
++	return _phy_query_rf_path_switch_8723d(dm, false);
++#endif
++}
++#endif
++
++#else
++
++void phy_iq_calibrate_8723d(void *dm_void, boolean is_recovery) {}
++void phy_lc_calibrate_8723d(void *dm_void) {}
++
++void odm_tx_pwr_track_set_pwr_8723d(struct dm_struct *dm,
++				    enum pwrtrack_method method, u8 rf_path,
++				    u8 channel_mapped_index) {}
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/rtl8723d/halrf_8723d.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/rtl8723d/halrf_8723d.h
+new file mode 100644
+index 000000000..1221094ad
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/halrf/rtl8723d/halrf_8723d.h
+@@ -0,0 +1,83 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_8723D_H__
++#define __HALRF_8723D_H__
++
++/*--------------------------Define Parameters-------------------------------*/
++#define IQK_DELAY_TIME_8723D 10 /* ms */
++#define index_mapping_NUM_8723D 15
++#define AVG_THERMAL_NUM_8723D 4
++#define RF_T_METER_8723D 0x42
++
++void configure_txpower_track_8723d(struct txpwrtrack_cfg *config);
++
++void get_delta_swing_table_8723d(void *dm_void, u8 **temperature_up_a,
++				 u8 **temperature_down_a, u8 **temperature_up_b,
++				 u8 **temperature_down_b);
++
++void set_cck_filter_coefficient_8723d(struct dm_struct *dm, u8 cck_swing_index);
++
++void do_iqk_8723d(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
++		  u8 threshold);
++
++void odm_tx_pwr_track_set_pwr_8723d(void *dm_void, enum pwrtrack_method method,
++				    u8 rf_path, u8 channel_mapped_index);
++
++void odm_txxtaltrack_set_xtal_8723d(void *dm_void);
++
++/* 1 7.	IQK */
++
++void phy_iq_calibrate_8723d(void *dm_void, boolean is_recovery);
++
++/*
++ * LC calibrate
++ */
++void phy_lc_calibrate_8723d(void *dm_void);
++
++
++#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
++void phy_set_rf_path_switch_8723d(struct dm_struct *dm,
++#else
++void phy_set_rf_path_switch_8723d(void *adapter,
++#endif
++				  boolean is_main);
++
++#if 0
++/*
++ * AP calibrate
++ */
++void
++phy_ap_calibrate_8723d(
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	struct dm_struct		*dm,
++#else
++	void	*adapter,
++#endif
++	s8		delta);
++void
++phy_digital_predistortion_8723d(void	*adapter);
++#endif
++
++void _phy_save_adda_registers_8723d(struct dm_struct *dm, u32 *adda_reg,
++				    u32 *adda_backup, u32 register_num);
++
++void _phy_path_adda_on_8723d(struct dm_struct *dm, u32 *adda_reg,
++			     boolean is_path_a_on, boolean is2T);
++
++void _phy_mac_setting_calibration_8723d(struct dm_struct *dm, u32 *mac_reg,
++					u32 *mac_backup);
++
++#endif /*#ifndef __HALRF_8723D_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/mp_precomp.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/mp_precomp.h
+new file mode 100644
+index 000000000..897adc13f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/mp_precomp.h
+@@ -0,0 +1,24 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm.c
+new file mode 100644
+index 000000000..b1c879be2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm.c
+@@ -0,0 +1,3684 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ ************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++const u16 phy_rate_table[] = {
++	/*@20M*/
++	1, 2, 5, 11,
++	6, 9, 12, 18, 24, 36, 48, 54,
++	6, 13, 19, 26, 39, 52, 58, 65, /*@MCS0~7*/
++	13, 26, 39, 52, 78, 104, 117, 130, /*@MCS8~15*/
++	19, 39, 58, 78, 117, 156, 175, 195, /*@MCS16~23*/
++	26, 52, 78, 104, 156, 208, 234, 260, /*@MCS24~31*/
++	6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1ss MCS0~9*/
++	13, 26, 39, 52, 78, 104, 117, 130, 156, 180, /*@2ss MCS0~9*/
++	19, 39, 58, 78, 117, 156, 175, 195, 234, 260, /*@3ss MCS0~9*/
++	26, 52, 78, 104, 156, 208, 234, 260, 312, 360 /*@4ss MCS0~9*/
++};
++
++void phydm_traffic_load_decision(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 shift = 0;
++
++	/*@---TP & Trafic-load calculation---*/
++
++	if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)
++		dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
++
++	if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)
++		dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
++
++	dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;
++	dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;
++	dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
++	dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
++
++	/*@AP:  <<3(8bit), >>20(10^6,M), >>0(1sec)*/
++	shift = 17 + (PHYDM_WATCH_DOG_PERIOD - 1);
++	/*@WIN&CE:  <<3(8bit), >>20(10^6,M), >>1(2sec)*/
++
++	dm->tx_tp = (dm->tx_tp >> 1) + (u32)((dm->cur_tx_ok_cnt >> shift) >> 1);
++	dm->rx_tp = (dm->rx_tp >> 1) + (u32)((dm->cur_rx_ok_cnt >> shift) >> 1);
++
++	dm->total_tp = dm->tx_tp + dm->rx_tp;
++
++	/*@[Calculate TX/RX state]*/
++	if (dm->tx_tp > (dm->rx_tp << 1))
++		dm->txrx_state_all = TX_STATE;
++	else if (dm->rx_tp > (dm->tx_tp << 1))
++		dm->txrx_state_all = RX_STATE;
++	else
++		dm->txrx_state_all = BI_DIRECTION_STATE;
++
++	/*@[Traffic load decision]*/
++	dm->pre_traffic_load = dm->traffic_load;
++
++	if (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) {
++		/* @( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
++		dm->traffic_load = TRAFFIC_HIGH;
++	} else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) {
++		/*@( 0.5M * 8bit ) / 2sec =  2M bits /sec )*/
++		dm->traffic_load = TRAFFIC_MID;
++	} else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) {
++		/*@( 0.1M * 8bit ) / 2sec =  0.4M bits /sec )*/
++		dm->traffic_load = TRAFFIC_LOW;
++	} else if (dm->cur_tx_ok_cnt > 25000 || dm->cur_rx_ok_cnt > 25000) {
++		/*@( 0.025M * 8bit ) / 2sec =  0.1M bits /sec )*/
++		dm->traffic_load = TRAFFIC_ULTRA_LOW;
++	} else {
++		dm->traffic_load = TRAFFIC_NO_TP;
++	}
++
++	/*@[Calculate consecutive idlel time]*/
++	if (dm->traffic_load == 0)
++		dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD;
++	else
++		dm->consecutive_idlel_time = 0;
++
++	#if 0
++	PHYDM_DBG(dm, DBG_COMMON_FLOW,
++		  "cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
++		  dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt,
++		  dm->last_rx_ok_cnt);
++
++	PHYDM_DBG(dm, DBG_COMMON_FLOW, "tx_tp = %d, rx_tp = %d\n", dm->tx_tp,
++		  dm->rx_tp);
++	#endif
++}
++
++void phydm_cck_new_agc_chk(struct dm_struct *dm)
++{
++	u32 new_agc_addr = 0x0;
++
++	dm->cck_new_agc = false;
++#if (RTL8723D_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT ||\
++	RTL8197F_SUPPORT || RTL8710B_SUPPORT || RTL8192F_SUPPORT ||\
++	RTL8195B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
++	RTL8721D_SUPPORT || RTL8710C_SUPPORT)
++	if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8821C |
++	    ODM_RTL8197F | ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8195B |
++	    ODM_RTL8721D | ODM_RTL8710C)) {
++		new_agc_addr = R_0xa9c;
++	} else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C |
++		   ODM_RTL8814B | ODM_RTL8197G)) {
++		new_agc_addr = R_0x1a9c;
++	}
++
++		/*@1: new agc  0: old agc*/
++	dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, new_agc_addr, BIT(17));
++#endif
++}
++
++/*select 3 or 4 bit LNA */
++void phydm_cck_lna_bit_num_chk(struct dm_struct *dm)
++{
++	boolean report_type = 0;
++	#if (RTL8192E_SUPPORT)
++	u32 value_824, value_82c;
++	#endif
++
++	#if (RTL8192E_SUPPORT)
++	if (dm->support_ic_type & (ODM_RTL8192E)) {
++	/* @0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
++	 * should be equal or CCK RSSI report may be incorrect
++	 */
++		value_824 = odm_get_bb_reg(dm, R_0x824, BIT(9));
++		value_82c = odm_get_bb_reg(dm, R_0x82c, BIT(9));
++
++		if (value_824 != value_82c)
++			odm_set_bb_reg(dm, R_0x82c, BIT(9), value_824);
++		odm_set_bb_reg(dm, R_0xa80, BIT(7), value_824);
++		report_type = (boolean)value_824;
++	}
++	#endif
++
++	#if (RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8710B_SUPPORT)
++	if (dm->support_ic_type &
++	    (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
++		report_type = (boolean)odm_get_bb_reg(dm, R_0x950, BIT(11));
++
++		if (report_type != 1)
++			pr_debug("[Warning] CCK should be 4bit LNA\n");
++	}
++	#endif
++
++	#if (RTL8821C_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8821C) {
++		if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
++			report_type = 1;
++	}
++	#endif
++
++	dm->cck_agc_report_type = report_type;
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "cck_agc_report_type=((%d))\n",
++		  dm->cck_agc_report_type);
++}
++
++void phydm_init_cck_setting(struct dm_struct *dm)
++{
++	u32 reg_tmp = 0;
++	u32 mask_tmp = 0;
++
++	phydm_cck_new_agc_chk(dm);
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		return;
++
++	reg_tmp = ODM_REG(CCK_RPT_FORMAT, dm);
++	mask_tmp = ODM_BIT(CCK_RPT_FORMAT, dm);
++	dm->is_cck_high_power = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "ext_lna_gain=((%d))\n", dm->ext_lna_gain);
++
++	phydm_config_cck_rx_antenna_init(dm);
++
++	if (dm->support_ic_type & ODM_RTL8192F)
++		phydm_config_cck_rx_path(dm, BB_PATH_AB);
++	else if (dm->valid_path_set == BB_PATH_A)
++		phydm_config_cck_rx_path(dm, BB_PATH_A);
++	else if (dm->valid_path_set == BB_PATH_B)
++		phydm_config_cck_rx_path(dm, BB_PATH_B);
++
++	phydm_cck_lna_bit_num_chk(dm);
++	phydm_get_cck_rssi_table_from_reg(dm);
++}
++
++#ifdef CONFIG_RFE_BY_HW_INFO
++void phydm_init_hw_info_by_rfe(struct dm_struct *dm)
++{
++	#if (RTL8821C_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8821C)
++		phydm_init_hw_info_by_rfe_type_8821c(dm);
++	#endif
++	#if (RTL8197F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8197F)
++		phydm_init_hw_info_by_rfe_type_8197f(dm);
++	#endif
++	#if (RTL8197G_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8197G)
++		phydm_init_hw_info_by_rfe_type_8197g(dm);
++	#endif
++}
++#endif
++
++void phydm_common_info_self_init(struct dm_struct *dm)
++{
++	u32 reg_tmp = 0;
++	u32 mask_tmp = 0;
++
++	dm->run_in_drv_fw = RUN_IN_DRIVER;
++
++	/*@BB IP Generation*/
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		dm->ic_ip_series = PHYDM_IC_JGR3;
++	else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
++		dm->ic_ip_series = PHYDM_IC_AC;
++	else if (dm->support_ic_type & ODM_IC_11N_SERIES)
++		dm->ic_ip_series = PHYDM_IC_N;
++
++	/*@BB phy-status Generation*/
++	if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC)
++		dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_3;
++	else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)
++		dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_2;
++	else
++		dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_1;
++
++	phydm_init_cck_setting(dm);
++
++	reg_tmp = ODM_REG(BB_RX_PATH, dm);
++	mask_tmp = ODM_BIT(BB_RX_PATH, dm);
++	dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
++#if (DM_ODM_SUPPORT_TYPE != ODM_CE)
++	dm->is_net_closed = &dm->BOOLEAN_temp;
++
++	phydm_init_debug_setting(dm);
++#endif
++	phydm_init_soft_ml_setting(dm);
++
++	dm->phydm_sys_up_time = 0;
++
++	if (dm->support_ic_type & ODM_IC_1SS)
++		dm->num_rf_path = 1;
++	else if (dm->support_ic_type & ODM_IC_2SS)
++		dm->num_rf_path = 2;
++	#if 0
++	/* @RTK do not has IC which is equipped with 3 RF paths,
++	 * so ODM_IC_3SS is an enpty macro and result in coverity check errors
++	 */
++	else if (dm->support_ic_type & ODM_IC_3SS)
++		dm->num_rf_path = 3;
++	#endif
++	else if (dm->support_ic_type & ODM_IC_4SS)
++		dm->num_rf_path = 4;
++	else
++		dm->num_rf_path = 1;
++
++	phydm_trx_antenna_setting_init(dm, dm->num_rf_path);
++
++	dm->tx_rate = 0xFF;
++	dm->rssi_min_by_path = 0xFF;
++
++	dm->number_linked_client = 0;
++	dm->pre_number_linked_client = 0;
++	dm->number_active_client = 0;
++	dm->pre_number_active_client = 0;
++
++	dm->last_tx_ok_cnt = 0;
++	dm->last_rx_ok_cnt = 0;
++	dm->tx_tp = 0;
++	dm->rx_tp = 0;
++	dm->total_tp = 0;
++	dm->traffic_load = TRAFFIC_LOW;
++
++	dm->nbi_set_result = 0;
++	dm->is_init_hw_info_by_rfe = false;
++	dm->pre_dbg_priority = DBGPORT_RELEASE;
++	dm->tp_active_th = 5;
++	dm->disable_phydm_watchdog = 0;
++
++	dm->u8_dummy = 0xf;
++	dm->u16_dummy = 0xffff;
++	dm->u32_dummy = 0xffffffff;
++#if (RTL8814B_SUPPORT)
++/*@------------For spur detection Default Mode------------@*/
++	dm->dsde_sel = DET_CSI;
++	dm->csi_wgt = 4;
++/*@-------------------------------------------------------@*/
++#endif
++	dm->pre_is_linked = false;
++	dm->is_linked = false;
++/*dym bw thre and it can config by registry*/
++	if (dm->en_auto_bw_th == 0)
++		dm->en_auto_bw_th = 20;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	if (!(dm->is_fcs_mode_enable)) {
++		dm->is_fcs_mode_enable = &dm->boolean_dummy;
++		pr_debug("[Warning] is_fcs_mode_enable=NULL\n");
++	}
++#endif
++	/*init IOT table*/
++	odm_memory_set(dm, &dm->iot_table, 0, sizeof(struct phydm_iot_center));
++}
++
++void phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_iot_center	*iot_table = &dm->iot_table;
++
++	PHYDM_DBG(dm, DBG_CMN, "[IOT] 0x%x = %d\n", iot_idx, en);
++	switch (iot_idx) {
++	case 0x100f0401:
++		iot_table->patch_id_100f0401 = en;
++		PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_100f0401 = %d\n",
++			  iot_table->patch_id_100f0401);
++		break;
++	case 0x10120200:
++		iot_table->patch_id_10120200 = en;
++		PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_10120200 = %d\n",
++			  iot_table->patch_id_10120200);
++		break;
++	case 0x40010700:
++		iot_table->patch_id_40010700 = en;
++		PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_40010700 = %d\n",
++			  iot_table->patch_id_40010700);
++		break;
++	case 0x021f0800:
++		iot_table->patch_id_021f0800 = en;
++		PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_021f0800 = %d\n",
++			  iot_table->patch_id_021f0800);
++		break;
++	default:
++		pr_debug("[%s] warning!\n", __func__);
++		break;
++	}
++}
++
++void phydm_cmn_sta_info_update(void *dm_void, u8 macid)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
++	struct ra_sta_info *ra = NULL;
++
++	if (is_sta_active(sta)) {
++		ra = &sta->ra_info;
++	} else {
++		PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n",
++			  __func__);
++		return;
++	}
++
++	PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
++	PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", sta->mac_id);
++
++	/*@[Calculate TX/RX state]*/
++	if (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1))
++		ra->txrx_state = TX_STATE;
++	else if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1))
++		ra->txrx_state = RX_STATE;
++	else
++		ra->txrx_state = BI_DIRECTION_STATE;
++
++	ra->is_noisy = dm->noisy_decision;
++}
++
++void phydm_common_info_self_update(struct dm_struct *dm)
++{
++	u8 sta_cnt = 0, num_active_client = 0;
++	u32 i, one_entry_macid = 0;
++	u32 ma_rx_tp = 0;
++	u32 tp_diff = 0;
++	struct cmn_sta_info *sta;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	PADAPTER adapter = (PADAPTER)dm->adapter;
++	PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
++
++	sta = dm->phydm_sta_info[0];
++
++	/* STA mode is linked to AP */
++	if (is_sta_active(sta) && !ACTING_AS_AP(adapter))
++		dm->bsta_state = true;
++	else
++		dm->bsta_state = false;
++#endif
++
++	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
++		sta = dm->phydm_sta_info[i];
++		if (is_sta_active(sta)) {
++			sta_cnt++;
++
++			if (sta_cnt == 1)
++				one_entry_macid = i;
++
++			phydm_cmn_sta_info_update(dm, (u8)i);
++			#ifdef PHYDM_BEAMFORMING_SUPPORT
++			/*@phydm_get_txbf_device_num(dm, (u8)i);*/
++			#endif
++
++			ma_rx_tp = sta->rx_moving_average_tp +
++				   sta->tx_moving_average_tp;
++
++			PHYDM_DBG(dm, DBG_COMMON_FLOW,
++				  "TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp);
++
++			if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
++				num_active_client++;
++		}
++	}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	dm->is_linked = (sta_cnt != 0) ? true : false;
++#endif
++
++	if (sta_cnt == 1) {
++		dm->is_one_entry_only = true;
++		dm->one_entry_macid = one_entry_macid;
++		dm->one_entry_tp = ma_rx_tp;
++
++		dm->tp_active_occur = 0;
++
++		PHYDM_DBG(dm, DBG_COMMON_FLOW,
++			  "one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n",
++			  dm->one_entry_tp, dm->pre_one_entry_tp);
++
++		if (dm->one_entry_tp > dm->pre_one_entry_tp &&
++		    dm->pre_one_entry_tp <= 2) {
++			tp_diff = dm->one_entry_tp - dm->pre_one_entry_tp;
++
++			if (tp_diff > dm->tp_active_th)
++				dm->tp_active_occur = 1;
++		}
++		dm->pre_one_entry_tp = dm->one_entry_tp;
++	} else {
++		dm->is_one_entry_only = false;
++	}
++
++	dm->pre_number_linked_client = dm->number_linked_client;
++	dm->pre_number_active_client = dm->number_active_client;
++
++	dm->number_linked_client = sta_cnt;
++	dm->number_active_client = num_active_client;
++
++	/*Traffic load information update*/
++	phydm_traffic_load_decision(dm);
++
++	dm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD;
++
++	dm->is_dfs_band = phydm_is_dfs_band(dm);
++	dm->phy_dbg_info.show_phy_sts_cnt = 0;
++
++	/*[Link Status Check]*/
++	dm->first_connect = dm->is_linked && !dm->pre_is_linked;
++	dm->first_disconnect = !dm->is_linked && dm->pre_is_linked;
++	dm->pre_is_linked = dm->is_linked;
++}
++
++void phydm_common_info_self_reset(struct dm_struct *dm)
++{
++	struct odm_phy_dbg_info		*dbg_t = &dm->phy_dbg_info;
++
++	dbg_t->beacon_cnt_in_period = dbg_t->num_qry_beacon_pkt;
++	dbg_t->num_qry_beacon_pkt = 0;
++
++	dm->rxsc_l = 0xff;
++	dm->rxsc_20 = 0xff;
++	dm->rxsc_40 = 0xff;
++	dm->rxsc_80 = 0xff;
++}
++
++void *
++phydm_get_structure(struct dm_struct *dm, u8 structure_type)
++
++{
++	void *structure = NULL;
++
++	switch (structure_type) {
++	case PHYDM_FALSEALMCNT:
++		structure = &dm->false_alm_cnt;
++		break;
++
++	case PHYDM_CFOTRACK:
++		structure = &dm->dm_cfo_track;
++		break;
++
++	case PHYDM_ADAPTIVITY:
++		structure = &dm->adaptivity;
++		break;
++#ifdef CONFIG_PHYDM_DFS_MASTER
++	case PHYDM_DFS:
++		structure = &dm->dfs;
++		break;
++#endif
++	default:
++		break;
++	}
++
++	return structure;
++}
++
++void phydm_phy_info_update(struct dm_struct *dm)
++{
++#if (RTL8822B_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8822B)
++		dm->phy_dbg_info.condi_num = phydm_get_condi_num_8822b(dm);
++#endif
++}
++
++void phydm_hw_setting(struct dm_struct *dm)
++{
++#if (RTL8821A_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8821)
++		odm_hw_setting_8821a(dm);
++#endif
++
++#if (RTL8814A_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8814A)
++		phydm_hwsetting_8814a(dm);
++#endif
++
++#if (RTL8822B_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8822B)
++		phydm_hwsetting_8822b(dm);
++#endif
++
++#if (RTL8812A_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8812)
++		phydm_hwsetting_8812a(dm);
++#endif
++
++#if (RTL8197F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8197F)
++		phydm_hwsetting_8197f(dm);
++#endif
++
++#if (RTL8192F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8192F)
++		phydm_hwsetting_8192f(dm);
++#endif
++
++#if (RTL8822C_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8822C)
++		phydm_hwsetting_8822c(dm);
++#endif
++
++#if (RTL8197G_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8197G)
++		phydm_hwsetting_8197g(dm);
++#endif
++
++#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
++	phydm_cck_rx_pathdiv_watchdog(dm);
++#endif
++}
++
++__odm_func__
++boolean phydm_chk_bb_rf_pkg_set_valid(struct dm_struct *dm)
++{
++	boolean valid = true;
++
++	if (dm->support_ic_type == ODM_RTL8822C) {
++		#if (RTL8822C_SUPPORT)
++		valid = phydm_chk_pkg_set_valid_8822c(dm,
++						      RELEASE_VERSION_8822C,
++						      RF_RELEASE_VERSION_8822C);
++		#else
++		valid = true; /*@Just for preventing compile warnings*/
++		#endif
++	#if (RTL8812F_SUPPORT)
++	} else if (dm->support_ic_type == ODM_RTL8812F) {
++		valid = phydm_chk_pkg_set_valid_8812f(dm,
++						      RELEASE_VERSION_8812F,
++						      RF_RELEASE_VERSION_8812F);
++	#endif
++	#if (RTL8197G_SUPPORT)
++	} else if (dm->support_ic_type == ODM_RTL8197G) {
++		valid = phydm_chk_pkg_set_valid_8197g(dm,
++						      RELEASE_VERSION_8197G,
++						      RF_RELEASE_VERSION_8197G);
++	#endif
++	#if (RTL8812F_SUPPORT)
++	} else if (dm->support_ic_type == ODM_RTL8812F) {
++		valid = phydm_chk_pkg_set_valid_8812f(dm,
++						      RELEASE_VERSION_8812F,
++						      RF_RELEASE_VERSION_8812F);
++	#endif
++	#if (RTL8198F_SUPPORT)
++	} else if (dm->support_ic_type == ODM_RTL8198F) {
++		valid = phydm_chk_pkg_set_valid_8198f(dm,
++						      RELEASE_VERSION_8198F,
++						      RF_RELEASE_VERSION_8198F);
++	#endif
++	#if (RTL8814B_SUPPORT)
++	} else if (dm->support_ic_type == ODM_RTL8814B) {
++		valid = phydm_chk_pkg_set_valid_8814b(dm,
++						      RELEASE_VERSION_8814B,
++						      RF_RELEASE_VERSION_8814B);
++	#endif
++	}
++
++	return valid;
++}
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++u64 phydm_supportability_init_win(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u64 support_ability = 0;
++
++	switch (dm->support_ic_type) {
++/*@---------------N Series--------------------*/
++#if (RTL8188E_SUPPORT)
++	case ODM_RTL8188E:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*ODM_BB_DYNAMIC_TXPWR |*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR |
++			ODM_BB_PRIMARY_CCA;
++		break;
++#endif
++
++#if (RTL8192E_SUPPORT)
++	case ODM_RTL8192E:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*ODM_BB_DYNAMIC_TXPWR |*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR |
++			ODM_BB_PRIMARY_CCA;
++		break;
++#endif
++
++#if (RTL8723B_SUPPORT)
++	case ODM_RTL8723B:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*ODM_BB_DYNAMIC_TXPWR |*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR |
++			ODM_BB_PRIMARY_CCA;
++		break;
++#endif
++
++#if (RTL8703B_SUPPORT)
++	case ODM_RTL8703B:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*ODM_BB_DYNAMIC_TXPWR |*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8723D_SUPPORT)
++	case ODM_RTL8723D:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*ODM_BB_DYNAMIC_TXPWR |*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			ODM_BB_PWR_TRAIN |
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8710B_SUPPORT)
++	case ODM_RTL8710B:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*ODM_BB_DYNAMIC_TXPWR |*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			ODM_BB_PWR_TRAIN |
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8188F_SUPPORT)
++	case ODM_RTL8188F:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*ODM_BB_DYNAMIC_TXPWR |*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8192F_SUPPORT)
++	case ODM_RTL8192F:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			ODM_BB_PWR_TRAIN	|
++			ODM_BB_RATE_ADAPTIVE |
++			/*ODM_BB_PATH_DIV |*/
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ADAPTIVE_SOML |
++			ODM_BB_ENV_MONITOR;
++			/*ODM_BB_LNA_SAT_CHK |*/
++			/*ODM_BB_PRIMARY_CCA*/
++
++		break;
++#endif
++
++/*@---------------AC Series-------------------*/
++
++#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
++	case ODM_RTL8812:
++	case ODM_RTL8821:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_DYNAMIC_TXPWR |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8814A_SUPPORT)
++	case ODM_RTL8814A:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_DYNAMIC_TXPWR |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8822B_SUPPORT)
++	case ODM_RTL8822B:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*ODM_BB_DYNAMIC_TXPWR	|*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			/*ODM_BB_ADAPTIVE_SOML |*/
++			ODM_BB_RATE_ADAPTIVE |
++			/*ODM_BB_PATH_DIV |*/
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8821C_SUPPORT)
++	case ODM_RTL8821C:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*ODM_BB_DYNAMIC_TXPWR	|*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++/*@---------------JGR3 Series-------------------*/
++
++#if (RTL8822C_SUPPORT)
++	case ODM_RTL8822C:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_DYNAMIC_TXPWR |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_PATH_DIV |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8814B_SUPPORT)
++	case ODM_RTL8814B:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*ODM_BB_DYNAMIC_TXPWR |*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING;
++			/*ODM_BB_ENV_MONITOR;*/
++		break;
++#endif
++
++	default:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*ODM_BB_DYNAMIC_TXPWR |*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++
++		pr_debug("[Warning] Supportability Init Warning !!!\n");
++		break;
++	}
++
++	return support_ability;
++}
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
++u64 phydm_supportability_init_ce(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u64 support_ability = 0;
++
++	switch (dm->support_ic_type) {
++/*@---------------N Series--------------------*/
++#if (RTL8188E_SUPPORT)
++	case ODM_RTL8188E:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*@ODM_BB_DYNAMIC_TXPWR	|*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*@ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR |
++			ODM_BB_PRIMARY_CCA;
++		break;
++#endif
++
++#if (RTL8192E_SUPPORT)
++	case ODM_RTL8192E:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*@ODM_BB_DYNAMIC_TXPWR	|*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*@ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR |
++			ODM_BB_PRIMARY_CCA;
++		break;
++#endif
++
++#if (RTL8723B_SUPPORT)
++	case ODM_RTL8723B:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*@ODM_BB_DYNAMIC_TXPWR	|*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*@ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR |
++			ODM_BB_PRIMARY_CCA;
++		break;
++#endif
++
++#if (RTL8703B_SUPPORT)
++	case ODM_RTL8703B:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*@ODM_BB_DYNAMIC_TXPWR	|*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*@ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8723D_SUPPORT)
++	case ODM_RTL8723D:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*@ODM_BB_DYNAMIC_TXPWR	|*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			ODM_BB_PWR_TRAIN	|
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8710B_SUPPORT)
++	case ODM_RTL8710B:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*@ODM_BB_DYNAMIC_TXPWR	|*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*@ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8188F_SUPPORT)
++	case ODM_RTL8188F:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*@ODM_BB_DYNAMIC_TXPWR	|*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*@ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8192F_SUPPORT)
++	case ODM_RTL8192F:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			ODM_BB_PWR_TRAIN |
++			ODM_BB_RATE_ADAPTIVE |
++			/*ODM_BB_PATH_DIV |*/
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			/*@ODM_BB_ADAPTIVE_SOML |*/
++			ODM_BB_ENV_MONITOR;
++			/*@ODM_BB_LNA_SAT_CHK |*/
++			/*@ODM_BB_PRIMARY_CCA*/
++			break;
++#endif
++/*@---------------AC Series-------------------*/
++
++#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
++	case ODM_RTL8812:
++	case ODM_RTL8821:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*@ODM_BB_DYNAMIC_TXPWR	|*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*@ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8814A_SUPPORT)
++	case ODM_RTL8814A:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*@ODM_BB_DYNAMIC_TXPWR	|*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*@ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8822B_SUPPORT)
++	case ODM_RTL8822B:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_DYNAMIC_TXPWR	|
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*@ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			/*ODM_BB_PATH_DIV |*/
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8821C_SUPPORT)
++	case ODM_RTL8821C:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*@ODM_BB_DYNAMIC_TXPWR	|*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*@ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++/*@---------------JGR3 Series-------------------*/
++
++#if (RTL8822C_SUPPORT)
++	case ODM_RTL8822C:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_DYNAMIC_TXPWR	|
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			ODM_BB_RATE_ADAPTIVE |
++			/* ODM_BB_PATH_DIV | */
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8814B_SUPPORT)
++	case ODM_RTL8814B:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*@ODM_BB_DYNAMIC_TXPWR	|*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*@ODM_BB_PWR_TRAIN |*/
++			/*ODM_BB_RATE_ADAPTIVE |*/
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING;
++			/*ODM_BB_ENV_MONITOR;*/
++		break;
++#endif
++
++	default:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*@ODM_BB_DYNAMIC_TXPWR	|*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*@ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++
++		pr_debug("[Warning] Supportability Init Warning !!!\n");
++		break;
++	}
++
++	return support_ability;
++}
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++u64 phydm_supportability_init_ap(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u64 support_ability = 0;
++
++	switch (dm->support_ic_type) {
++/*@---------------N Series--------------------*/
++#if (RTL8188E_SUPPORT)
++	case ODM_RTL8188E:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR |
++			ODM_BB_PRIMARY_CCA;
++		break;
++#endif
++
++#if (RTL8192E_SUPPORT)
++	case ODM_RTL8192E:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR |
++			ODM_BB_PRIMARY_CCA;
++		break;
++#endif
++
++#if (RTL8723B_SUPPORT)
++	case ODM_RTL8723B:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN		|*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8198F_SUPPORT || RTL8197F_SUPPORT)
++	case ODM_RTL8198F:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			/*ODM_BB_RATE_ADAPTIVE |*/
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING;
++			/*ODM_BB_ADAPTIVE_SOML |*/
++			/*ODM_BB_ENV_MONITOR |*/
++			/*ODM_BB_LNA_SAT_CHK |*/
++			/*ODM_BB_PRIMARY_CCA;*/
++		break;
++	case ODM_RTL8197F:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ADAPTIVE_SOML |
++			ODM_BB_ENV_MONITOR |
++			ODM_BB_LNA_SAT_CHK |
++			ODM_BB_PRIMARY_CCA;
++		break;
++#endif
++
++#if (RTL8192F_SUPPORT)
++	case ODM_RTL8192F:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			/*ODM_BB_CFO_TRACKING |*/
++			ODM_BB_ADAPTIVE_SOML |
++			/*ODM_BB_PATH_DIV |*/
++			ODM_BB_ENV_MONITOR |
++			/*ODM_BB_LNA_SAT_CHK |*/
++			/*ODM_BB_PRIMARY_CCA |*/
++			0;
++		break;
++#endif
++
++/*@---------------AC Series-------------------*/
++
++#if (RTL8881A_SUPPORT)
++	case ODM_RTL8881A:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8814A_SUPPORT)
++	case ODM_RTL8814A:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8822B_SUPPORT)
++	case ODM_RTL8822B:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			/*ODM_BB_ADAPTIVE_SOML |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8821C_SUPPORT)
++	case ODM_RTL8821C:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++
++		break;
++#endif
++
++/*@---------------JGR3 Series-------------------*/
++
++#if (RTL8814B_SUPPORT)
++	case ODM_RTL8814B:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			/*ODM_BB_RATE_ADAPTIVE |*/
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8197G_SUPPORT)
++	case ODM_RTL8197G:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8812F_SUPPORT)
++	case ODM_RTL8812F:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_DYNAMIC_TXPWR	|
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			/*ODM_BB_CCK_PD |*/
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++	default:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++
++		pr_debug("[Warning] Supportability Init Warning !!!\n");
++		break;
++	}
++
++	return support_ability;
++}
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
++u64 phydm_supportability_init_iot(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u64 support_ability = 0;
++
++	switch (dm->support_ic_type) {
++#if (RTL8710B_SUPPORT)
++	case ODM_RTL8710B:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*ODM_BB_DYNAMIC_TXPWR |*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8195A_SUPPORT)
++	case ODM_RTL8195A:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*ODM_BB_DYNAMIC_TXPWR |*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8195B_SUPPORT)
++	case ODM_RTL8195B:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*ODM_BB_DYNAMIC_TXPWR |*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING;
++			/*ODM_BB_ENV_MONITOR*/
++		break;
++#endif
++
++#if (RTL8721D_SUPPORT)
++	case ODM_RTL8721D:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*ODM_BB_DYNAMIC_TXPWR |*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++
++#if (RTL8710C_SUPPORT)
++	case ODM_RTL8710C:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*ODM_BB_DYNAMIC_TXPWR |*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_ADAPTIVITY |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++		break;
++#endif
++	default:
++		support_ability |=
++			ODM_BB_DIG |
++			ODM_BB_RA_MASK |
++			/*ODM_BB_DYNAMIC_TXPWR |*/
++			ODM_BB_FA_CNT |
++			ODM_BB_RSSI_MONITOR |
++			ODM_BB_CCK_PD |
++			/*ODM_BB_PWR_TRAIN |*/
++			ODM_BB_RATE_ADAPTIVE |
++			ODM_BB_CFO_TRACKING |
++			ODM_BB_ENV_MONITOR;
++
++		pr_debug("[Warning] Supportability Init Warning !!!\n");
++		break;
++	}
++
++	return support_ability;
++}
++#endif
++
++void phydm_fwoffload_ability_init(struct dm_struct *dm,
++				  enum phydm_offload_ability offload_ability)
++{
++	switch (offload_ability) {
++	case PHYDM_PHY_PARAM_OFFLOAD:
++		if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
++			dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;
++		break;
++
++	case PHYDM_RF_IQK_OFFLOAD:
++		dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;
++		break;
++
++	case PHYDM_RF_DPK_OFFLOAD:
++		dm->fw_offload_ability |= PHYDM_RF_DPK_OFFLOAD;
++		break;
++
++	default:
++		PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
++		break;
++	}
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
++		  dm->fw_offload_ability);
++}
++
++void phydm_fwoffload_ability_clear(struct dm_struct *dm,
++				   enum phydm_offload_ability offload_ability)
++{
++	switch (offload_ability) {
++	case PHYDM_PHY_PARAM_OFFLOAD:
++		if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
++			dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);
++		break;
++
++	case PHYDM_RF_IQK_OFFLOAD:
++		dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);
++		break;
++
++	case PHYDM_RF_DPK_OFFLOAD:
++		dm->fw_offload_ability &= (~PHYDM_RF_DPK_OFFLOAD);
++		break;	
++
++	default:
++		PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
++		break;
++	}
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
++		  dm->fw_offload_ability);
++}
++
++void phydm_supportability_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u64 support_ability;
++
++	if (dm->manual_supportability &&
++	    *dm->manual_supportability != 0xffffffff) {
++		support_ability = *dm->manual_supportability;
++	} else if (*dm->mp_mode) {
++		support_ability = 0;
++	} else {
++		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++		support_ability = phydm_supportability_init_win(dm);
++		#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++		support_ability = phydm_supportability_init_ap(dm);
++		#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
++		support_ability = phydm_supportability_init_ce(dm);
++		#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
++		support_ability = phydm_supportability_init_iot(dm);
++		#endif
++
++		/*@[Config Antenna Diversity]*/
++		if (IS_FUNC_EN(dm->enable_antdiv))
++			support_ability |= ODM_BB_ANT_DIV;
++
++		/*@[Config TXpath Diversity]*/
++		if (IS_FUNC_EN(dm->enable_pathdiv))
++			support_ability |= ODM_BB_PATH_DIV;
++
++		/*@[Config Adaptive SOML]*/
++		if (IS_FUNC_EN(dm->en_adap_soml))
++			support_ability |= ODM_BB_ADAPTIVE_SOML;
++
++	}
++	dm->support_ability = support_ability;
++	PHYDM_DBG(dm, ODM_COMP_INIT, "IC=0x%x, mp=%d, Supportability=0x%llx\n",
++		  dm->support_ic_type, *dm->mp_mode, dm->support_ability);
++}
++
++void phydm_rfe_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "RFE_Init\n");
++#if (RTL8822B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8822B)
++		phydm_rfe_8822b_init(dm);
++#endif
++}
++
++void phydm_dm_early_init(struct dm_struct *dm)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	phydm_init_debug_setting(dm);
++#endif
++}
++
++enum phydm_init_result odm_dm_init(struct dm_struct *dm)
++{
++	enum phydm_init_result result = PHYDM_INIT_SUCCESS;
++
++	if (!phydm_chk_bb_rf_pkg_set_valid(dm)) {
++		pr_debug("[Warning][%s] Init fail\n", __func__);
++		return PHYDM_INIT_FAIL_BBRF_REG_INVALID;
++	}
++
++	halrf_init(dm);
++	phydm_supportability_init(dm);
++	phydm_pause_func_init(dm);
++	phydm_rfe_init(dm);
++	phydm_common_info_self_init(dm);
++	phydm_rx_phy_status_init(dm);
++#ifdef PHYDM_AUTO_DEGBUG
++	phydm_auto_dbg_engine_init(dm);
++#endif
++	phydm_dig_init(dm);
++#ifdef PHYDM_SUPPORT_CCKPD
++#ifdef PHYDM_DCC_ENHANCE
++	phydm_dig_cckpd_coex_init(dm);
++#endif
++	phydm_cck_pd_init(dm);
++#endif
++	phydm_env_monitor_init(dm);
++	phydm_adaptivity_init(dm);
++	phydm_ra_info_init(dm);
++	phydm_rssi_monitor_init(dm);
++	phydm_cfo_tracking_init(dm);
++	phydm_rf_init(dm);
++	phydm_dc_cancellation(dm);
++#ifdef PHYDM_TXA_CALIBRATION
++	phydm_txcurrentcalibration(dm);
++	phydm_get_pa_bias_offset(dm);
++#endif
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	odm_antenna_diversity_init(dm);
++#endif
++#ifdef CONFIG_ADAPTIVE_SOML
++	phydm_adaptive_soml_init(dm);
++#endif
++#ifdef CONFIG_PATH_DIVERSITY
++	phydm_tx_path_diversity_init(dm);
++#endif
++#ifdef CONFIG_DYNAMIC_TX_TWR
++	phydm_dynamic_tx_power_init(dm);
++#endif
++#if (PHYDM_LA_MODE_SUPPORT)
++	phydm_la_init(dm);
++#endif
++
++#ifdef PHYDM_BEAMFORMING_VERSION1
++	phydm_beamforming_init(dm);
++#endif
++
++#if (RTL8188E_SUPPORT)
++	odm_ra_info_init_all(dm);
++#endif
++#ifdef PHYDM_PRIMARY_CCA
++	phydm_primary_cca_init(dm);
++#endif
++#ifdef CONFIG_PSD_TOOL
++	phydm_psd_init(dm);
++#endif
++
++#ifdef CONFIG_SMART_ANTENNA
++	phydm_smt_ant_init(dm);
++#endif
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++	phydm_lna_sat_check_init(dm);
++#endif
++#ifdef CONFIG_MCC_DM
++	phydm_mcc_init(dm);
++#endif
++
++#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
++	phydm_cck_rx_pathdiv_init(dm);
++#endif
++
++#ifdef CONFIG_MU_RSOML
++	phydm_mu_rsoml_init(dm);
++#endif
++
++#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
++	phydm_tx_collsion_th_init(dm);
++#endif
++
++	return result;
++}
++
++void odm_dm_reset(struct dm_struct *dm)
++{
++	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	odm_ant_div_reset(dm);
++	#endif
++	phydm_set_edcca_threshold_api(dm);
++}
++
++void phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
++			     char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 dm_value[10] = {0};
++	u64 pre_support_ability, one = 1;
++	u64 comp = 0;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 i;
++
++	for (i = 0; i < 5; i++) {
++		if (input[i + 1])
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
++	}
++
++	pre_support_ability = dm->support_ability;
++	comp = dm->support_ability;
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\n================================\n");
++
++	if (dm_value[0] == 100) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[Supportability] PhyDM Selection\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "================================\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "00. (( %s ))DIG\n",
++			 ((comp & ODM_BB_DIG) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "01. (( %s ))RA_MASK\n",
++			 ((comp & ODM_BB_RA_MASK) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "02. (( %s ))DYN_TXPWR\n",
++			 ((comp & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "03. (( %s ))FA_CNT\n",
++			 ((comp & ODM_BB_FA_CNT) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "04. (( %s ))RSSI_MNTR\n",
++			 ((comp & ODM_BB_RSSI_MONITOR) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "05. (( %s ))CCK_PD\n",
++			 ((comp & ODM_BB_CCK_PD) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "06. (( %s ))ANT_DIV\n",
++			 ((comp & ODM_BB_ANT_DIV) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "07. (( %s ))SMT_ANT\n",
++			 ((comp & ODM_BB_SMT_ANT) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "08. (( %s ))PWR_TRAIN\n",
++			 ((comp & ODM_BB_PWR_TRAIN) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "09. (( %s ))RA\n",
++			 ((comp & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "10. (( %s ))PATH_DIV\n",
++			 ((comp & ODM_BB_PATH_DIV) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "11. (( %s ))DFS\n",
++			 ((comp & ODM_BB_DFS) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "12. (( %s ))DYN_ARFR\n",
++			 ((comp & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "13. (( %s ))ADAPTIVITY\n",
++			 ((comp & ODM_BB_ADAPTIVITY) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "14. (( %s ))CFO_TRACK\n",
++			 ((comp & ODM_BB_CFO_TRACKING) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "15. (( %s ))ENV_MONITOR\n",
++			 ((comp & ODM_BB_ENV_MONITOR) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "16. (( %s ))PRI_CCA\n",
++			 ((comp & ODM_BB_PRIMARY_CCA) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "17. (( %s ))ADPTV_SOML\n",
++			 ((comp & ODM_BB_ADAPTIVE_SOML) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "18. (( %s ))LNA_SAT_CHK\n",
++			 ((comp & ODM_BB_LNA_SAT_CHK) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "================================\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[Supportability] PhyDM offload ability\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "================================\n");
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "00. (( %s ))PHY PARAM OFFLOAD\n",
++			 ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ?
++			 ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "01. (( %s ))RF IQK OFFLOAD\n",
++			 ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ?
++			 ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "================================\n");
++
++	} else if (dm_value[0] == 101) {
++		dm->support_ability = 0;
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Disable all support_ability components\n");
++	} else {
++		if (dm_value[1] == 1) { /* @enable */
++			dm->support_ability |= (one << dm_value[0]);
++		} else if (dm_value[1] == 2) {/* @disable */
++			dm->support_ability &= ~(one << dm_value[0]);
++		} else {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[Warning!!!]  1:enable,  2:disable\n");
++		}
++	}
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "pre-supportability = 0x%llx\n", pre_support_ability);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "Cur-supportability = 0x%llx\n", dm->support_ability);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "================================\n");
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_watchdog_lps_32k(struct dm_struct *dm)
++{
++	PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
++
++	phydm_common_info_self_update(dm);
++	phydm_rssi_monitor_check(dm);
++	phydm_dig_lps_32k(dm);
++	phydm_common_info_self_reset(dm);
++}
++
++void phydm_watchdog_lps(struct dm_struct *dm)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
++	PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
++
++	phydm_common_info_self_update(dm);
++	phydm_rssi_monitor_check(dm);
++	phydm_basic_dbg_message(dm);
++	phydm_receiver_blocking(dm);
++	phydm_false_alarm_counter_statistics(dm);
++	phydm_dig_by_rssi_lps(dm);
++	#ifdef PHYDM_SUPPORT_CCKPD
++	phydm_cck_pd_th(dm);
++	#endif
++	phydm_adaptivity(dm);
++	#ifdef CONFIG_BW_INDICATION
++	phydm_dyn_bw_indication(dm);
++	#endif
++	#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
++	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	/*@enable AntDiv in PS mode, request from SD4 Jeff*/
++	odm_antenna_diversity(dm);
++	#endif
++	#endif
++	phydm_common_info_self_reset(dm);
++#endif
++}
++
++void phydm_watchdog_mp(struct dm_struct *dm)
++{
++}
++
++void phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (pause_type == PHYDM_PAUSE) {
++		dm->disable_phydm_watchdog = 1;
++		PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Stop\n");
++	} else {
++		dm->disable_phydm_watchdog = 0;
++		PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Start\n");
++	}
++}
++
++void phydm_pause_func_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;
++	dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
++	dm->pause_lv_table.lv_antdiv = PHYDM_PAUSE_RELEASE;
++	dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
++	dm->pause_lv_table.lv_adapt = PHYDM_PAUSE_RELEASE;
++	dm->pause_lv_table.lv_adsl = PHYDM_PAUSE_RELEASE;
++}
++
++u8 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
++		    enum phydm_pause_type pause_type,
++		    enum phydm_pause_level pause_lv, u8 val_lehgth,
++		    u32 *val_buf)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_func_poiner *func_t = &dm->phydm_func_handler;
++	s8 *pause_lv_pre = &dm->s8_dummy;
++	u32 *bkp_val = &dm->u32_dummy;
++	u32 ori_val[5] = {0};
++	u64 pause_func_bitmap = (u64)BIT(pause_func);
++	u8 i = 0;
++	u8 en_2rcca = 0;
++	u8 en_bw40m = 0;
++	u8 pause_result = PAUSE_FAIL;
++
++	PHYDM_DBG(dm, ODM_COMP_API, "\n");
++	PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] LV=%d, Len=%d\n", __func__,
++		  ((pause_type == PHYDM_PAUSE) ? "Pause" :
++		  ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
++		  pause_lv, val_lehgth);
++
++	if (pause_lv >= PHYDM_PAUSE_MAX_NUM) {
++		PHYDM_DBG(dm, ODM_COMP_API, "[WARNING]Wrong LV=%d\n", pause_lv);
++		return PAUSE_FAIL;
++	}
++
++	if (pause_func == F00_DIG) {
++		PHYDM_DBG(dm, ODM_COMP_API, "[DIG]\n");
++
++		if (val_lehgth != 1) {
++			PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
++			return PAUSE_FAIL;
++		}
++
++		ori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value);
++		pause_lv_pre = &dm->pause_lv_table.lv_dig;
++		bkp_val = (u32 *)(&dm->dm_dig_table.rvrt_val);
++		/*@function pointer hook*/
++		func_t->pause_phydm_handler = phydm_set_dig_val;
++
++#ifdef PHYDM_SUPPORT_CCKPD
++	} else if (pause_func == F05_CCK_PD) {
++		PHYDM_DBG(dm, ODM_COMP_API, "[CCK_PD]\n");
++
++		if (val_lehgth != 1) {
++			PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
++			return PAUSE_FAIL;
++		}
++
++		ori_val[0] = (u32)dm->dm_cckpd_table.cck_pd_lv;
++		pause_lv_pre = &dm->pause_lv_table.lv_cckpd;
++		bkp_val = (u32 *)(&dm->dm_cckpd_table.rvrt_val);
++		/*@function pointer hook*/
++		func_t->pause_phydm_handler = phydm_set_cckpd_val;
++#endif
++
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	} else if (pause_func == F06_ANT_DIV) {
++		PHYDM_DBG(dm, ODM_COMP_API, "[AntDiv]\n");
++
++		if (val_lehgth != 1) {
++			PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
++			return PAUSE_FAIL;
++		}
++		/*@default antenna*/
++		ori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant);
++		pause_lv_pre = &dm->pause_lv_table.lv_antdiv;
++		bkp_val = (u32 *)(&dm->dm_fat_table.rvrt_val);
++		/*@function pointer hook*/
++		func_t->pause_phydm_handler = phydm_set_antdiv_val;
++
++#endif
++#ifdef PHYDM_SUPPORT_ADAPTIVITY
++	} else if (pause_func == F13_ADPTVTY) {
++		PHYDM_DBG(dm, ODM_COMP_API, "[Adaptivity]\n");
++
++		if (val_lehgth != 2) {
++			PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 2\n");
++			return PAUSE_FAIL;
++		}
++
++		ori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/
++		ori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/
++		pause_lv_pre = &dm->pause_lv_table.lv_adapt;
++		bkp_val = (u32 *)(&dm->adaptivity.rvrt_val);
++		/*@function pointer hook*/
++		func_t->pause_phydm_handler = phydm_set_edcca_val;
++
++#endif
++#ifdef CONFIG_ADAPTIVE_SOML
++	} else if (pause_func == F17_ADPTV_SOML) {
++		PHYDM_DBG(dm, ODM_COMP_API, "[AD-SOML]\n");
++
++		if (val_lehgth != 1) {
++			PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
++			return PAUSE_FAIL;
++		}
++		/*SOML_ON/OFF*/
++		ori_val[0] = (u32)(dm->dm_soml_table.soml_on_off);
++
++		pause_lv_pre = &dm->pause_lv_table.lv_adsl;
++		bkp_val = (u32 *)(&dm->dm_soml_table.rvrt_val);
++		 /*@function pointer hook*/
++		func_t->pause_phydm_handler = phydm_set_adsl_val;
++
++#endif
++	} else {
++		PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error func idx\n");
++		return PAUSE_FAIL;
++	}
++
++	PHYDM_DBG(dm, ODM_COMP_API, "Pause_LV{new , pre} = {%d ,%d}\n",
++		  pause_lv, *pause_lv_pre);
++
++	if (pause_type == PHYDM_PAUSE || pause_type == PHYDM_PAUSE_NO_SET) {
++		if (pause_lv <= *pause_lv_pre) {
++			PHYDM_DBG(dm, ODM_COMP_API,
++				  "[PAUSE FAIL] Pre_LV >= Curr_LV\n");
++			return PAUSE_FAIL;
++		}
++
++		if (!(dm->pause_ability & pause_func_bitmap)) {
++			for (i = 0; i < val_lehgth; i++)
++				bkp_val[i] = ori_val[i];
++		}
++
++		dm->pause_ability |= pause_func_bitmap;
++		PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
++			  dm->pause_ability);
++
++		if (pause_type == PHYDM_PAUSE) {
++			for (i = 0; i < val_lehgth; i++)
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n",
++					  i, val_buf[i], bkp_val[i]);
++			func_t->pause_phydm_handler(dm, val_buf, val_lehgth);
++		} else {
++			for (i = 0; i < val_lehgth; i++)
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n",
++					  i, bkp_val[i]);
++		}
++
++		*pause_lv_pre = pause_lv;
++		pause_result = PAUSE_SUCCESS;
++
++	} else if (pause_type == PHYDM_RESUME) {
++		if (pause_lv < *pause_lv_pre) {
++			PHYDM_DBG(dm, ODM_COMP_API,
++				  "[Resume FAIL] Pre_LV >= Curr_LV\n");
++			return PAUSE_FAIL;
++		}
++
++		if ((dm->pause_ability & pause_func_bitmap) == 0) {
++			PHYDM_DBG(dm, ODM_COMP_API,
++				  "[RESUME] No Need to Revert\n");
++			return PAUSE_SUCCESS;
++		}
++
++		dm->pause_ability &= ~pause_func_bitmap;
++		PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
++			  dm->pause_ability);
++
++		*pause_lv_pre = PHYDM_PAUSE_RELEASE;
++
++		for (i = 0; i < val_lehgth; i++) {
++			PHYDM_DBG(dm, ODM_COMP_API,
++				  "[RESUME] val_idx[%d]={0x%x}\n", i,
++				  bkp_val[i]);
++		}
++
++		func_t->pause_phydm_handler(dm, bkp_val, val_lehgth);
++
++		pause_result = PAUSE_SUCCESS;
++	} else {
++		PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error pause_type\n");
++		pause_result = PAUSE_FAIL;
++	}
++	return pause_result;
++}
++
++void phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
++			      char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 i;
++	u8 length = 0;
++	u32 buf[5] = {0};
++	u8 set_result = 0;
++	enum phydm_func_idx func = 0;
++	enum phydm_pause_type type = 0;
++	enum phydm_pause_level lv = 0;
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{Func} {1:pause,2:pause no set 3:Resume} {lv:0~3} Val[5:0]\n");
++
++		goto out;
++	}
++
++	for (i = 0; i < 10; i++) {
++		if (input[i + 1])
++			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
++	}
++
++	func = (enum phydm_func_idx)var1[0];
++	type = (enum phydm_pause_type)var1[1];
++	lv = (enum phydm_pause_level)var1[2];
++
++	for (i = 0; i < 5; i++)
++		buf[i] = var1[3 + i];
++
++	if (func == F00_DIG) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[DIG]\n");
++		length = 1;
++
++	} else if (func == F05_CCK_PD) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[CCK_PD]\n");
++		length = 1;
++	} else if (func == F06_ANT_DIV) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[Ant_Div]\n");
++		length = 1;
++	} else if (func == F13_ADPTVTY) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[Adaptivity]\n");
++		length = 2;
++	} else if (func == F17_ADPTV_SOML) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[ADSL]\n");
++		length = 1;
++	} else {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[Set Function Error]\n");
++		length = 0;
++	}
++
++	if (length != 0) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{%s, lv=%d} val = %d, %d}\n",
++			 ((type == PHYDM_PAUSE) ? "Pause" :
++			 ((type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
++			 lv, var1[3], var1[4]);
++
++		set_result = phydm_pause_func(dm, func, type, lv, length, buf);
++	}
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "set_result = %d\n", set_result);
++
++out:
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm,
++				enum phydm_pause_type pause_type, u8 rssi)
++{
++	u32 igi_val = rssi + 10;
++	u32 th_buf[2];
++
++	PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] rssi=%d\n", __func__,
++		  ((pause_type == PHYDM_PAUSE) ? "Pause" :
++		  ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
++		  rssi);
++
++	if (pause_type == PHYDM_RESUME) {
++		phydm_pause_func(dm, F00_DIG, PHYDM_RESUME,
++				 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
++
++		phydm_pause_func(dm, F13_ADPTVTY, PHYDM_RESUME,
++				 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
++	} else {
++		odm_write_dig(dm, (u8)igi_val);
++		phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE,
++				 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
++
++		th_buf[0] = 0xff;
++		th_buf[1] = 0xff;
++
++		phydm_pause_func(dm, F13_ADPTVTY, PHYDM_PAUSE,
++				 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
++	}
++}
++
++u8 phydm_stop_dm_watchdog_check(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->disable_phydm_watchdog == 1) {
++		PHYDM_DBG(dm, DBG_COMMON_FLOW, "Disable phydm\n");
++		return true;
++	} else {
++		return false;
++	}
++}
++
++void phydm_watchdog(struct dm_struct *dm)
++{
++	PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
++
++	phydm_common_info_self_update(dm);
++	phydm_phy_info_update(dm);
++	phydm_rssi_monitor_check(dm);
++	phydm_basic_dbg_message(dm);
++	phydm_dm_summary(dm, FIRST_MACID);
++#ifdef PHYDM_AUTO_DEGBUG
++	phydm_auto_dbg_engine(dm);
++#endif
++	phydm_receiver_blocking(dm);
++
++	if (phydm_stop_dm_watchdog_check(dm) == true)
++		return;
++
++	phydm_hw_setting(dm);
++
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++	if (dm->original_dig_restore == 0) {
++		phydm_tdma_dig_timer_check(dm);
++	} else
++#endif
++	{
++		phydm_false_alarm_counter_statistics(dm);
++		phydm_noisy_detection(dm);
++
++	#if defined(PHYDM_DCC_ENHANCE) && defined(PHYDM_SUPPORT_CCKPD)
++		phydm_dig_cckpd_coex(dm);
++	#else
++		phydm_dig(dm);
++		#ifdef PHYDM_SUPPORT_CCKPD
++		phydm_cck_pd_th(dm);
++		#endif
++	#endif
++	}
++
++#ifdef PHYDM_HW_IGI
++	phydm_hwigi(dm);
++#endif
++#ifdef PHYDM_POWER_TRAINING_SUPPORT
++	phydm_update_power_training_state(dm);
++#endif
++	phydm_adaptivity(dm);
++	phydm_ra_info_watchdog(dm);
++#ifdef CONFIG_PATH_DIVERSITY
++	phydm_tx_path_diversity(dm);
++#endif
++	phydm_cfo_tracking(dm);
++#ifdef CONFIG_DYNAMIC_TX_TWR
++	phydm_dynamic_tx_power(dm);
++#endif
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	odm_antenna_diversity(dm);
++#endif
++#ifdef CONFIG_ADAPTIVE_SOML
++	phydm_adaptive_soml(dm);
++#endif
++
++#ifdef PHYDM_BEAMFORMING_VERSION1
++	phydm_beamforming_watchdog(dm);
++#endif
++
++	halrf_watchdog(dm);
++#ifdef PHYDM_PRIMARY_CCA
++	phydm_primary_cca(dm);
++#endif
++#ifdef CONFIG_BW_INDICATION
++	phydm_dyn_bw_indication(dm);
++#endif
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	odm_dtc(dm);
++#endif
++
++	phydm_env_mntr_watchdog(dm);
++
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++	phydm_lna_sat_chk_watchdog(dm);
++#endif
++
++#ifdef CONFIG_MCC_DM
++	phydm_mcc_switch(dm);
++#endif
++
++#ifdef CONFIG_MU_RSOML
++	phydm_mu_rsoml_decision(dm);
++#endif
++
++	phydm_common_info_self_reset(dm);
++}
++
++void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx,
++			 boolean enable)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 h2c_val[H2C_MAX_LENGTH] = {0};
++	u8 para4[4]; /*4 bit*/
++	u8 para8[4]; /*8 bit*/
++	u8 i = 0;
++
++	for (i = 0; i < 4; i++) {
++		para4[i] = 0;
++		para8[i] = 0;
++	}
++
++	switch (fun_idx) {
++	case F00_DIG:
++		phydm_fill_fw_dig_info(dm, &enable, para4, para8);
++		break;
++	default:
++		pr_debug("[Warning] %s\n", __func__);
++		return;
++	}
++
++	h2c_val[0] = (u8)((fun_idx & 0x3f) | (enable << 6));
++	h2c_val[1] = para8[0];
++	h2c_val[2] = para8[1];
++	h2c_val[3] = para8[2];
++	h2c_val[4] = para8[3];
++	h2c_val[5] = (para4[0] & 0xf) | ((para4[1] & 0xf) << 3);
++	h2c_val[6] = (para4[2] & 0xf) | ((para4[3] & 0xf) << 3);
++
++	PHYDM_DBG(dm, DBG_FW_DM,
++		  "H2C[0x59] fun_idx=%d,en=%d,para8={%x %x %x %x},para4={%x %x %x %x}\n",
++		  fun_idx, enable,
++		  para8[0], para8[1], para8[2], para8[3],
++		  para4[0], para4[1], para4[2], para4[3]);
++
++	odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_DM_CTRL, H2C_MAX_LENGTH, h2c_val);
++}
++
++/*@
++ * Init /.. Fixed HW value. Only init time.
++ */
++void odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info,
++		       u64 value)
++{
++	/* This section is used for init value */
++	switch (cmn_info) {
++	/* @Fixed ODM value. */
++	case ODM_CMNINFO_ABILITY:
++		dm->support_ability = (u64)value;
++		break;
++
++	case ODM_CMNINFO_RF_TYPE:
++		dm->rf_type = (u8)value;
++		break;
++
++	case ODM_CMNINFO_PLATFORM:
++		dm->support_platform = (u8)value;
++		break;
++
++	case ODM_CMNINFO_INTERFACE:
++		dm->support_interface = (u8)value;
++		break;
++
++	case ODM_CMNINFO_MP_TEST_CHIP:
++		dm->is_mp_chip = (u8)value;
++		break;
++
++	case ODM_CMNINFO_IC_TYPE:
++		dm->support_ic_type = (u32)value;
++		break;
++
++	case ODM_CMNINFO_CUT_VER:
++		dm->cut_version = (u8)value;
++		break;
++
++	case ODM_CMNINFO_FAB_VER:
++		dm->fab_version = (u8)value;
++		break;
++	case ODM_CMNINFO_FW_VER:
++		dm->fw_version = (u8)value;
++		break;
++	case ODM_CMNINFO_FW_SUB_VER:
++		dm->fw_sub_version = (u8)value;
++		break;
++	case ODM_CMNINFO_RFE_TYPE:
++#if (RTL8821C_SUPPORT)
++		if (dm->support_ic_type & ODM_RTL8821C)
++			dm->rfe_type_expand = (u8)value;
++		else
++#endif
++			dm->rfe_type = (u8)value;
++
++#ifdef CONFIG_RFE_BY_HW_INFO
++		phydm_init_hw_info_by_rfe(dm);
++#endif
++		break;
++
++	case ODM_CMNINFO_RF_ANTENNA_TYPE:
++		dm->ant_div_type = (u8)value;
++		break;
++
++	case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
++		dm->with_extenal_ant_switch = (u8)value;
++		break;
++
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	case ODM_CMNINFO_BE_FIX_TX_ANT:
++		dm->dm_fat_table.b_fix_tx_ant = (u8)value;
++		break;
++#endif
++
++	case ODM_CMNINFO_BOARD_TYPE:
++		if (!dm->is_init_hw_info_by_rfe)
++			dm->board_type = (u8)value;
++		break;
++
++	case ODM_CMNINFO_PACKAGE_TYPE:
++		if (!dm->is_init_hw_info_by_rfe)
++			dm->package_type = (u8)value;
++		break;
++
++	case ODM_CMNINFO_EXT_LNA:
++		if (!dm->is_init_hw_info_by_rfe)
++			dm->ext_lna = (u8)value;
++		break;
++
++	case ODM_CMNINFO_5G_EXT_LNA:
++		if (!dm->is_init_hw_info_by_rfe)
++			dm->ext_lna_5g = (u8)value;
++		break;
++
++	case ODM_CMNINFO_EXT_PA:
++		if (!dm->is_init_hw_info_by_rfe)
++			dm->ext_pa = (u8)value;
++		break;
++
++	case ODM_CMNINFO_5G_EXT_PA:
++		if (!dm->is_init_hw_info_by_rfe)
++			dm->ext_pa_5g = (u8)value;
++		break;
++
++	case ODM_CMNINFO_GPA:
++		if (!dm->is_init_hw_info_by_rfe)
++			dm->type_gpa = (u16)value;
++		break;
++
++	case ODM_CMNINFO_APA:
++		if (!dm->is_init_hw_info_by_rfe)
++			dm->type_apa = (u16)value;
++		break;
++
++	case ODM_CMNINFO_GLNA:
++		if (!dm->is_init_hw_info_by_rfe)
++			dm->type_glna = (u16)value;
++		break;
++
++	case ODM_CMNINFO_ALNA:
++		if (!dm->is_init_hw_info_by_rfe)
++			dm->type_alna = (u16)value;
++		break;
++
++	case ODM_CMNINFO_EXT_TRSW:
++		if (!dm->is_init_hw_info_by_rfe)
++			dm->ext_trsw = (u8)value;
++		break;
++	case ODM_CMNINFO_EXT_LNA_GAIN:
++		dm->ext_lna_gain = (u8)value;
++		break;
++	case ODM_CMNINFO_PATCH_ID:
++		dm->iot_table.win_patch_id = (u8)value;
++		break;
++	case ODM_CMNINFO_BINHCT_TEST:
++		dm->is_in_hct_test = (boolean)value;
++		break;
++	case ODM_CMNINFO_BWIFI_TEST:
++		dm->wifi_test = (u8)value;
++		break;
++	case ODM_CMNINFO_SMART_CONCURRENT:
++		dm->is_dual_mac_smart_concurrent = (boolean)value;
++		break;
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	case ODM_CMNINFO_CONFIG_BB_RF:
++		dm->config_bbrf = (boolean)value;
++		break;
++#endif
++	case ODM_CMNINFO_IQKPAOFF:
++		dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;
++		break;
++	case ODM_CMNINFO_REGRFKFREEENABLE:
++		dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
++		break;
++	case ODM_CMNINFO_RFKFREEENABLE:
++		dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
++		break;
++	case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
++		dm->normal_rx_path = (u8)value;
++		break;
++	case ODM_CMNINFO_VALID_PATH_SET:
++		dm->valid_path_set = (u8)value;
++		break;
++	case ODM_CMNINFO_EFUSE0X3D8:
++		dm->efuse0x3d8 = (u8)value;
++		break;
++	case ODM_CMNINFO_EFUSE0X3D7:
++		dm->efuse0x3d7 = (u8)value;
++		break;
++	case ODM_CMNINFO_ADVANCE_OTA:
++		dm->p_advance_ota = (u8)value;
++		break;
++
++#ifdef CONFIG_PHYDM_DFS_MASTER
++	case ODM_CMNINFO_DFS_REGION_DOMAIN:
++		dm->dfs_region_domain = (u8)value;
++		break;
++#endif
++	case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING:
++		dm->soft_ap_special_setting = (u32)value;
++		break;
++
++	case ODM_CMNINFO_X_CAP_SETTING:
++		dm->dm_cfo_track.crystal_cap_default = (u8)value;
++		break;
++
++	case ODM_CMNINFO_DPK_EN:
++		/*@dm->dpk_en = (u1Byte)value;*/
++		halrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value);
++		break;
++
++	case ODM_CMNINFO_HP_HWID:
++		dm->hp_hw_id = (boolean)value;
++		break;
++	case ODM_CMNINFO_TSSI_ENABLE:
++		dm->en_tssi_mode = (u8)value;
++		break;
++	case ODM_CMNINFO_DIS_DPD:
++		dm->en_dis_dpd = (boolean)value;
++		break;
++	case ODM_CMNINFO_EN_AUTO_BW_TH:
++		dm->en_auto_bw_th = (u8)value;
++		break;
++#if (RTL8721D_SUPPORT)
++	case ODM_CMNINFO_POWER_VOLTAGE:
++		dm->power_voltage = (u8)value;
++		break;
++	case ODM_CMNINFO_ANTDIV_GPIO:
++		dm->antdiv_gpio = (u8)value;
++		break;
++	case ODM_CMNINFO_PEAK_DETECT_MODE:
++		dm->peak_detect_mode = (u8)value;
++		break;
++#endif
++	default:
++		break;
++	}
++}
++
++void odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info,
++		       void *value)
++{
++	/* @Hook call by reference pointer. */
++	switch (cmn_info) {
++	/* @Dynamic call by reference pointer. */
++	case ODM_CMNINFO_TX_UNI:
++		dm->num_tx_bytes_unicast = (u64 *)value;
++		break;
++
++	case ODM_CMNINFO_RX_UNI:
++		dm->num_rx_bytes_unicast = (u64 *)value;
++		break;
++
++	case ODM_CMNINFO_BAND:
++		dm->band_type = (u8 *)value;
++		break;
++
++	case ODM_CMNINFO_SEC_CHNL_OFFSET:
++		dm->sec_ch_offset = (u8 *)value;
++		break;
++
++	case ODM_CMNINFO_SEC_MODE:
++		dm->security = (u8 *)value;
++		break;
++
++	case ODM_CMNINFO_BW:
++		dm->band_width = (u8 *)value;
++		break;
++
++	case ODM_CMNINFO_CHNL:
++		dm->channel = (u8 *)value;
++		break;
++
++	case ODM_CMNINFO_SCAN:
++		dm->is_scan_in_process = (boolean *)value;
++		break;
++
++	case ODM_CMNINFO_POWER_SAVING:
++		dm->is_power_saving = (boolean *)value;
++		break;
++
++	case ODM_CMNINFO_TDMA:
++		dm->is_tdma = (boolean *)value;
++		break;
++
++	case ODM_CMNINFO_ONE_PATH_CCA:
++		dm->one_path_cca = (u8 *)value;
++		break;
++
++	case ODM_CMNINFO_DRV_STOP:
++		dm->is_driver_stopped = (boolean *)value;
++		break;
++	case ODM_CMNINFO_INIT_ON:
++		dm->pinit_adpt_in_progress = (boolean *)value;
++		break;
++
++	case ODM_CMNINFO_ANT_TEST:
++		dm->antenna_test = (u8 *)value;
++		break;
++
++	case ODM_CMNINFO_NET_CLOSED:
++		dm->is_net_closed = (boolean *)value;
++		break;
++
++	case ODM_CMNINFO_FORCED_RATE:
++		dm->forced_data_rate = (u16 *)value;
++		break;
++	case ODM_CMNINFO_ANT_DIV:
++		dm->enable_antdiv = (u8 *)value;
++		break;
++	case ODM_CMNINFO_PATH_DIV:
++		dm->enable_pathdiv = (u8 *)value;
++		break;
++	case ODM_CMNINFO_ADAPTIVE_SOML:
++		dm->en_adap_soml = (u8 *)value;
++		break;
++	case ODM_CMNINFO_ADAPTIVITY:
++		dm->edcca_mode = (u8 *)value;
++		break;
++
++	case ODM_CMNINFO_P2P_LINK:
++		dm->dm_dig_table.is_p2p_in_process = (u8 *)value;
++		break;
++
++	case ODM_CMNINFO_IS1ANTENNA:
++		dm->is_1_antenna = (boolean *)value;
++		break;
++
++	case ODM_CMNINFO_RFDEFAULTPATH:
++		dm->rf_default_path = (u8 *)value;
++		break;
++
++	case ODM_CMNINFO_FCS_MODE: /* @fast channel switch (= MCC mode)*/
++		dm->is_fcs_mode_enable = (boolean *)value;
++		break;
++
++	case ODM_CMNINFO_HUBUSBMODE:
++		dm->hub_usb_mode = (u8 *)value;
++		break;
++	case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
++		dm->is_fw_dw_rsvd_page_in_progress = (boolean *)value;
++		break;
++	case ODM_CMNINFO_TX_TP:
++		dm->current_tx_tp = (u32 *)value;
++		break;
++	case ODM_CMNINFO_RX_TP:
++		dm->current_rx_tp = (u32 *)value;
++		break;
++	case ODM_CMNINFO_SOUNDING_SEQ:
++		dm->sounding_seq = (u8 *)value;
++		break;
++#ifdef CONFIG_PHYDM_DFS_MASTER
++	case ODM_CMNINFO_DFS_MASTER_ENABLE:
++		dm->dfs_master_enabled = (u8 *)value;
++		break;
++#endif
++
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
++		dm->dm_fat_table.p_force_tx_by_desc = (u8 *)value;
++		break;
++	case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
++		dm->dm_fat_table.p_default_s0_s1 = (u8 *)value;
++		break;
++	case ODM_CMNINFO_BF_ANTDIV_DECISION:
++		dm->dm_fat_table.is_no_csi_feedback = (boolean *)value;
++		break;
++#endif
++
++	case ODM_CMNINFO_SOFT_AP_MODE:
++		dm->soft_ap_mode = (u32 *)value;
++		break;
++	case ODM_CMNINFO_MP_MODE:
++		dm->mp_mode = (u8 *)value;
++		break;
++	case ODM_CMNINFO_INTERRUPT_MASK:
++		dm->interrupt_mask = (u32 *)value;
++		break;
++	case ODM_CMNINFO_BB_OPERATION_MODE:
++		dm->bb_op_mode = (u8 *)value;
++		break;
++	case ODM_CMNINFO_MANUAL_SUPPORTABILITY:
++		dm->manual_supportability = (u32 *)value;
++		break;
++	case ODM_CMNINFO_EN_DYM_BW_INDICATION:
++		dm->dis_dym_bw_indication = (u8 *)value;
++	default:
++		/*do nothing*/
++		break;
++	}
++}
++
++/*@
++ * Update band/CHannel/.. The values are dynamic but non-per-packet.
++ */
++void odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value)
++{
++	/* This init variable may be changed in run time. */
++	switch (cmn_info) {
++	case ODM_CMNINFO_LINK_IN_PROGRESS:
++		dm->is_link_in_process = (boolean)value;
++		break;
++
++	case ODM_CMNINFO_ABILITY:
++		dm->support_ability = (u64)value;
++		break;
++
++	case ODM_CMNINFO_RF_TYPE:
++		dm->rf_type = (u8)value;
++		break;
++
++	case ODM_CMNINFO_WIFI_DIRECT:
++		dm->is_wifi_direct = (boolean)value;
++		break;
++
++	case ODM_CMNINFO_WIFI_DISPLAY:
++		dm->is_wifi_display = (boolean)value;
++		break;
++
++	case ODM_CMNINFO_LINK:
++		dm->is_linked = (boolean)value;
++		break;
++
++	case ODM_CMNINFO_CMW500LINK:
++		dm->iot_table.is_linked_cmw500 = (boolean)value;
++		break;
++
++	case ODM_CMNINFO_STATION_STATE:
++		dm->bsta_state = (boolean)value;
++		break;
++
++	case ODM_CMNINFO_RSSI_MIN:
++#if 0
++		dm->rssi_min = (u8)value;
++#endif
++		break;
++
++	case ODM_CMNINFO_RSSI_MIN_BY_PATH:
++		dm->rssi_min_by_path = (u8)value;
++		break;
++
++	case ODM_CMNINFO_DBG_COMP:
++		dm->debug_components = (u64)value;
++		break;
++
++#ifdef ODM_CONFIG_BT_COEXIST
++	/* The following is for BT HS mode and BT coexist mechanism. */
++	case ODM_CMNINFO_BT_ENABLED:
++		dm->bt_info_table.is_bt_enabled = (boolean)value;
++		break;
++
++	case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
++		dm->bt_info_table.is_bt_connect_process = (boolean)value;
++		break;
++
++	case ODM_CMNINFO_BT_HS_RSSI:
++		dm->bt_info_table.bt_hs_rssi = (u8)value;
++		break;
++
++	case ODM_CMNINFO_BT_OPERATION:
++		dm->bt_info_table.is_bt_hs_operation = (boolean)value;
++		break;
++
++	case ODM_CMNINFO_BT_LIMITED_DIG:
++		dm->bt_info_table.is_bt_limited_dig = (boolean)value;
++		break;
++#endif
++
++	case ODM_CMNINFO_AP_TOTAL_NUM:
++		dm->ap_total_num = (u8)value;
++		break;
++
++#ifdef CONFIG_PHYDM_DFS_MASTER
++	case ODM_CMNINFO_DFS_REGION_DOMAIN:
++		dm->dfs_region_domain = (u8)value;
++		break;
++#endif
++
++	case ODM_CMNINFO_BT_CONTINUOUS_TURN:
++		dm->is_bt_continuous_turn = (boolean)value;
++		break;
++	case ODM_CMNINFO_IS_DOWNLOAD_FW:
++		dm->is_download_fw = (boolean)value;
++		break;
++	case ODM_CMNINFO_PHYDM_PATCH_ID:
++		dm->iot_table.phydm_patch_id = (u32)value;
++		break;
++	case ODM_CMNINFO_RRSR_VAL:
++		dm->dm_ra_table.rrsr_val_init = (u32)value;
++		break;
++	case ODM_CMNINFO_LINKED_BF_SUPPORT:
++		dm->linked_bf_support = (u8)value;
++		break;
++	case ODM_CMNINFO_FLATNESS_TYPE:
++		dm->flatness_type = (u8)value;
++		break;
++	default:
++		break;
++	}
++}
++
++u32 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type)
++{
++	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct ccx_info *ccx_info = &dm->dm_ccx_info;
++
++	switch (info_type) {
++	/*@=== [FA Relative] ===========================================*/
++	case PHYDM_INFO_FA_OFDM:
++		return fa_t->cnt_ofdm_fail;
++
++	case PHYDM_INFO_FA_CCK:
++		return fa_t->cnt_cck_fail;
++
++	case PHYDM_INFO_FA_TOTAL:
++		return fa_t->cnt_all;
++
++	case PHYDM_INFO_CCA_OFDM:
++		return fa_t->cnt_ofdm_cca;
++
++	case PHYDM_INFO_CCA_CCK:
++		return fa_t->cnt_cck_cca;
++
++	case PHYDM_INFO_CCA_ALL:
++		return fa_t->cnt_cca_all;
++
++	case PHYDM_INFO_CRC32_OK_VHT:
++		return fa_t->cnt_vht_crc32_ok;
++
++	case PHYDM_INFO_CRC32_OK_HT:
++		return fa_t->cnt_ht_crc32_ok;
++
++	case PHYDM_INFO_CRC32_OK_LEGACY:
++		return fa_t->cnt_ofdm_crc32_ok;
++
++	case PHYDM_INFO_CRC32_OK_CCK:
++		return fa_t->cnt_cck_crc32_ok;
++
++	case PHYDM_INFO_CRC32_ERROR_VHT:
++		return fa_t->cnt_vht_crc32_error;
++
++	case PHYDM_INFO_CRC32_ERROR_HT:
++		return fa_t->cnt_ht_crc32_error;
++
++	case PHYDM_INFO_CRC32_ERROR_LEGACY:
++		return fa_t->cnt_ofdm_crc32_error;
++
++	case PHYDM_INFO_CRC32_ERROR_CCK:
++		return fa_t->cnt_cck_crc32_error;
++
++	case PHYDM_INFO_EDCCA_FLAG:
++		return fa_t->edcca_flag;
++
++	case PHYDM_INFO_OFDM_ENABLE:
++		return fa_t->ofdm_block_enable;
++
++	case PHYDM_INFO_CCK_ENABLE:
++		return fa_t->cck_block_enable;
++
++	case PHYDM_INFO_DBG_PORT_0:
++		return fa_t->dbg_port0;
++
++	case PHYDM_INFO_CRC32_OK_HT_AGG:
++		return fa_t->cnt_ht_crc32_ok_agg;
++
++	case PHYDM_INFO_CRC32_ERROR_HT_AGG:
++		return fa_t->cnt_ht_crc32_error_agg;
++
++	/*@=== [DIG] ================================================*/
++
++	case PHYDM_INFO_CURR_IGI:
++		return dig_t->cur_ig_value;
++
++	/*@=== [RSSI] ===============================================*/
++	case PHYDM_INFO_RSSI_MIN:
++		return (u32)dm->rssi_min;
++
++	case PHYDM_INFO_RSSI_MAX:
++		return (u32)dm->rssi_max;
++
++	case PHYDM_INFO_CLM_RATIO:
++		return (u32)ccx_info->clm_ratio;
++	case PHYDM_INFO_NHM_RATIO:
++		return (u32)ccx_info->nhm_ratio;
++	case PHYDM_INFO_NHM_NOISE_PWR:
++		return (u32)ccx_info->nhm_level;
++	default:
++		return 0xffffffff;
++	}
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void odm_init_all_work_items(struct dm_struct *dm)
++{
++	void *adapter = dm->adapter;
++#if USE_WORKITEM
++
++#ifdef CONFIG_ADAPTIVE_SOML
++	odm_initialize_work_item(dm,
++				 &dm->dm_soml_table.phydm_adaptive_soml_workitem,
++				 (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback,
++				 (void *)adapter,
++				 "AdaptiveSOMLWorkitem");
++#endif
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++	odm_initialize_work_item(dm,
++				 &dm->phydm_evm_antdiv_workitem,
++				 (RT_WORKITEM_CALL_BACK)phydm_evm_antdiv_workitem_callback,
++				 (void *)adapter,
++				 "EvmAntdivWorkitem");
++#endif
++
++#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++	odm_initialize_work_item(dm,
++				 &dm->dm_swat_table.phydm_sw_antenna_switch_workitem,
++				 (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,
++				 (void *)adapter,
++				 "AntennaSwitchWorkitem");
++#endif
++#if (defined(CONFIG_HL_SMART_ANTENNA))
++	odm_initialize_work_item(dm,
++				 &dm->dm_sat_table.hl_smart_antenna_workitem,
++				 (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
++				 (void *)adapter,
++				 "hl_smart_ant_workitem");
++
++	odm_initialize_work_item(dm,
++				 &dm->dm_sat_table.hl_smart_antenna_decision_workitem,
++				 (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
++				 (void *)adapter,
++				 "hl_smart_ant_decision_workitem");
++#endif
++
++	odm_initialize_work_item(
++		dm,
++		&dm->ra_rpt_workitem,
++		(RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback,
++		(void *)adapter,
++		"ra_rpt_workitem");
++
++#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++	odm_initialize_work_item(
++		dm,
++		&dm->fast_ant_training_workitem,
++		(RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,
++		(void *)adapter,
++		"fast_ant_training_workitem");
++#endif
++
++#endif /*#if USE_WORKITEM*/
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++	odm_initialize_work_item(
++		dm,
++		&dm->beamforming_info.txbf_info.txbf_enter_work_item,
++		(RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,
++		(void *)adapter,
++		"txbf_enter_work_item");
++
++	odm_initialize_work_item(
++		dm,
++		&dm->beamforming_info.txbf_info.txbf_leave_work_item,
++		(RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,
++		(void *)adapter,
++		"txbf_leave_work_item");
++
++	odm_initialize_work_item(
++		dm,
++		&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item,
++		(RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,
++		(void *)adapter,
++		"txbf_fw_ndpa_work_item");
++
++	odm_initialize_work_item(
++		dm,
++		&dm->beamforming_info.txbf_info.txbf_clk_work_item,
++		(RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,
++		(void *)adapter,
++		"txbf_clk_work_item");
++
++	odm_initialize_work_item(
++		dm,
++		&dm->beamforming_info.txbf_info.txbf_rate_work_item,
++		(RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,
++		(void *)adapter,
++		"txbf_rate_work_item");
++
++	odm_initialize_work_item(
++		dm,
++		&dm->beamforming_info.txbf_info.txbf_status_work_item,
++		(RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,
++		(void *)adapter,
++		"txbf_status_work_item");
++
++	odm_initialize_work_item(
++		dm,
++		&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item,
++		(RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,
++		(void *)adapter,
++		"txbf_reset_tx_path_work_item");
++
++	odm_initialize_work_item(
++		dm,
++		&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item,
++		(RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,
++		(void *)adapter,
++		"txbf_get_tx_rate_work_item");
++#endif
++
++#if (PHYDM_LA_MODE_SUPPORT == 1)
++	odm_initialize_work_item(
++		dm,
++		&dm->adcsmp.adc_smp_work_item,
++		(RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
++		(void *)adapter,
++		"adc_smp_work_item");
++
++	odm_initialize_work_item(
++		dm,
++		&dm->adcsmp.adc_smp_work_item_1,
++		(RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
++		(void *)adapter,
++		"adc_smp_work_item_1");
++#endif
++}
++
++void odm_free_all_work_items(struct dm_struct *dm)
++{
++#if USE_WORKITEM
++
++#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++	odm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem);
++#endif
++
++#ifdef CONFIG_ADAPTIVE_SOML
++	odm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem);
++#endif
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++	odm_free_work_item(&dm->phydm_evm_antdiv_workitem);
++#endif
++
++#if (defined(CONFIG_HL_SMART_ANTENNA))
++	odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem);
++	odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem);
++#endif
++
++#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++	odm_free_work_item(&dm->fast_ant_training_workitem);
++#endif
++	odm_free_work_item(&dm->ra_rpt_workitem);
++/*odm_free_work_item((&dm->sbdcnt_workitem));*/
++#endif
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item));
++	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item));
++	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));
++	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item));
++	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item));
++	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item));
++	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));
++	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));
++#endif
++
++#if (PHYDM_LA_MODE_SUPPORT == 1)
++	odm_free_work_item((&dm->adcsmp.adc_smp_work_item));
++	odm_free_work_item((&dm->adcsmp.adc_smp_work_item_1));
++#endif
++}
++#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
++
++void odm_init_all_timers(struct dm_struct *dm)
++{
++#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++	odm_ant_div_timers(dm, INIT_ANTDIV_TIMMER);
++#endif
++#if (defined(PHYDM_TDMA_DIG_SUPPORT))
++#ifdef IS_USE_NEW_TDMA
++	phydm_tdma_dig_timers(dm, INIT_TDMA_DIG_TIMMER);
++#endif
++#endif
++#ifdef CONFIG_ADAPTIVE_SOML
++	phydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER);
++#endif
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++#ifdef PHYDM_LNA_SAT_CHK_TYPE1
++	phydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER);
++#endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	odm_initialize_timer(dm, &dm->sbdcnt_timer,
++			     (void *)phydm_sbd_callback, NULL, "SbdTimer");
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++	odm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,
++			     (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL,
++			     "txbf_fw_ndpa_timer");
++#endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++	odm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer,
++			     (void *)beamforming_sw_timer_callback, NULL,
++			     "beamforming_timer");
++#endif
++#endif
++}
++
++void odm_cancel_all_timers(struct dm_struct *dm)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	/* @2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/
++	if (dm->adapter == NULL)
++		return;
++#endif
++
++#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++	odm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER);
++#endif
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++#ifdef IS_USE_NEW_TDMA
++	phydm_tdma_dig_timers(dm, CANCEL_TDMA_DIG_TIMMER);
++#endif
++#endif
++#ifdef CONFIG_ADAPTIVE_SOML
++	phydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER);
++#endif
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++#ifdef PHYDM_LNA_SAT_CHK_TYPE1
++	phydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER);
++#endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	odm_cancel_timer(dm, &dm->sbdcnt_timer);
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++	odm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
++#endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++	odm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer);
++#endif
++#endif
++}
++
++void odm_release_all_timers(struct dm_struct *dm)
++{
++#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++	odm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER);
++#endif
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++#ifdef IS_USE_NEW_TDMA
++	phydm_tdma_dig_timers(dm, RELEASE_TDMA_DIG_TIMMER);
++#endif
++#endif
++#ifdef CONFIG_ADAPTIVE_SOML
++	phydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER);
++#endif
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++#ifdef PHYDM_LNA_SAT_CHK_TYPE1
++	phydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER);
++#endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	odm_release_timer(dm, &dm->sbdcnt_timer);
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++	odm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
++#endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++	odm_release_timer(dm, &dm->beamforming_info.beamforming_timer);
++#endif
++#endif
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++void odm_init_all_threads(
++	struct dm_struct *dm)
++{
++#ifdef TPT_THREAD
++	k_tpt_task_init(dm->priv);
++#endif
++}
++
++void odm_stop_all_threads(
++	struct dm_struct *dm)
++{
++#ifdef TPT_THREAD
++	k_tpt_task_stop(dm->priv);
++#endif
++}
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++/* @Justin: According to the current RRSI to adjust Response Frame TX power,
++ * 2012/11/05
++ */
++void odm_dtc(struct dm_struct *dm)
++{
++#ifdef CONFIG_DM_RESP_TXAGC
++/* RSSI higher than this value, start to decade TX power */
++#define DTC_BASE 35
++
++/* RSSI lower than this value, start to increase TX power */
++#define DTC_DWN_BASE (DTC_BASE - 5)
++
++	/* RSSI vs TX power step mapping: decade TX power */
++	static const u8 dtc_table_down[] = {
++		DTC_BASE,
++		(DTC_BASE + 5),
++		(DTC_BASE + 10),
++		(DTC_BASE + 15),
++		(DTC_BASE + 20),
++		(DTC_BASE + 25)};
++
++	/* RSSI vs TX power step mapping: increase TX power */
++	static const u8 dtc_table_up[] = {
++		DTC_DWN_BASE,
++		(DTC_DWN_BASE - 5),
++		(DTC_DWN_BASE - 10),
++		(DTC_DWN_BASE - 15),
++		(DTC_DWN_BASE - 15),
++		(DTC_DWN_BASE - 20),
++		(DTC_DWN_BASE - 20),
++		(DTC_DWN_BASE - 25),
++		(DTC_DWN_BASE - 25),
++		(DTC_DWN_BASE - 30),
++		(DTC_DWN_BASE - 35)};
++
++	u8 i;
++	u8 dtc_steps = 0;
++	u8 sign;
++	u8 resp_txagc = 0;
++
++	if (dm->rssi_min > DTC_BASE) {
++		/* need to decade the CTS TX power */
++		sign = 1;
++		for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {
++			if (dtc_table_down[i] >= dm->rssi_min || dtc_steps >= 6)
++				break;
++			else
++				dtc_steps++;
++		}
++	}
++#if 0
++	else if (dm->rssi_min > DTC_DWN_BASE) {
++		/* needs to increase the CTS TX power */
++		sign = 0;
++		dtc_steps = 1;
++		for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {
++			if (dtc_table_up[i] <= dm->rssi_min || dtc_steps >= 10)
++				break;
++			else
++				dtc_steps++;
++		}
++	}
++#endif
++	else {
++		sign = 0;
++		dtc_steps = 0;
++	}
++
++	resp_txagc = dtc_steps | (sign << 4);
++	resp_txagc = resp_txagc | (resp_txagc << 5);
++	odm_write_1byte(dm, 0x06d9, resp_txagc);
++
++	PHYDM_DBG(dm, ODM_COMP_PWR_TRAIN,
++		  "%s rssi_min:%u, set RESP_TXAGC to %s %u\n", __func__,
++		  dm->rssi_min, sign ? "minus" : "plus", dtc_steps);
++#endif /* @CONFIG_RESP_TXAGC_ADJUST */
++}
++
++#endif /* @#if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
++
++/*@<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/
++void phydm_dc_cancellation(struct dm_struct *dm)
++{
++#ifdef PHYDM_DC_CANCELLATION
++	u32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0};
++	u32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0};
++	u32 reg_value32[PHYDM_MAX_RF_PATH] = {0};
++	u8 path = RF_PATH_A;
++	u8 set_result;
++
++	if (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT))
++		return;
++	if ((dm->support_ic_type & ODM_RTL8188F) &&
++	    dm->cut_version < ODM_CUT_D)
++		return;
++	if ((dm->support_ic_type & ODM_RTL8192F) &&
++	    dm->cut_version == ODM_CUT_A)
++		return;
++	if (*dm->band_width == CHANNEL_WIDTH_5)
++		return;
++	if (*dm->band_width == CHANNEL_WIDTH_10)
++		return;
++
++	PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
++
++	/*@DC_Estimation (only for 2x2 ic now) */
++
++	for (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) {
++		if (path > RF_PATH_A &&
++		    dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8188F |
++					  ODM_RTL8710B | ODM_RTL8721D |
++					  ODM_RTL8710C | ODM_RTL8723D))
++			break;
++		else if (path > RF_PATH_B &&
++			 dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8192F))
++			break;
++		if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
++			PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
++			return;
++		}
++		odm_write_dig(dm, 0x7e);
++		/*@Disable LNA*/
++		if (dm->support_ic_type & ODM_RTL8821C)
++			halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
++		/*Turn off 3-wire*/
++		phydm_stop_3_wire(dm, PHYDM_SET);
++		if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
++			ODM_RTL8710B)) {
++			/*set debug port to 0x235*/
++			if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "Set Debug port Fail\n");
++				return;
++			}
++		} else if (dm->support_ic_type & (ODM_RTL8721D |
++			ODM_RTL8710C)) {
++			/*set debug port to 0x200*/
++			if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) {
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "Set Debug port Fail\n");
++				return;
++			}
++		} else if (dm->support_ic_type & ODM_RTL8821C) {
++			if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
++				/*set debug port to 0x200*/
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "Set Debug port Fail\n");
++				return;
++			}
++			phydm_bb_dbg_port_header_sel(dm, 0x0);
++		} else if (dm->support_ic_type & ODM_RTL8822B) {
++			if (path == RF_PATH_A &&
++			    !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
++				/*set debug port to 0x200*/
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "Set Debug port Fail\n");
++				return;
++			}
++			if (path == RF_PATH_B &&
++			    !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x202)) {
++				/*set debug port to 0x200*/
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "Set Debug port Fail\n");
++				return;
++			}
++			phydm_bb_dbg_port_header_sel(dm, 0x0);
++		} else if (dm->support_ic_type & ODM_RTL8192F) {
++			if (path == RF_PATH_A &&
++			    !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
++				/*set debug port to 0x235*/
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "Set Debug port Fail\n");
++				return;
++			}
++			if (path == RF_PATH_B &&
++			    !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x23d)) {
++				/*set debug port to 0x23d*/
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "Set Debug port Fail\n");
++				return;
++			}
++		}
++
++		/*@disable CCK DCNF*/
++		odm_set_bb_reg(dm, R_0xa78, MASKBYTE1, 0x0);
++
++		PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation Begin!!!\n");
++
++		phydm_stop_ck320(dm, true); /*stop ck320*/
++
++		/* the same debug port both for path-a and path-b*/
++		reg_value32[path] = phydm_get_bb_dbg_port_val(dm);
++
++		phydm_stop_ck320(dm, false); /*start ck320*/
++
++		phydm_release_bb_dbg_port(dm);
++		/* @Turn on 3-wire*/
++		phydm_stop_3_wire(dm, PHYDM_REVERT);
++		/* @Enable LNA*/
++		if (dm->support_ic_type & ODM_RTL8821C)
++			halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
++
++		odm_write_dig(dm, 0x20);
++
++		set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
++
++		PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation OK!!!\n");
++	}
++
++	/*@DC_Cancellation*/
++	/*@DC compensation to CCK data path*/
++	odm_set_bb_reg(dm, R_0xa9c, BIT(20), 0x1);
++	if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
++		ODM_RTL8710B)) {
++		offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
++		offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
++
++		/*@Before filling into registers,
++		 *offset should be multiplexed (-1)
++		 */
++		offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
++				  (0x400 - offset_i_hex[0]) :
++				  (0x1ff - offset_i_hex[0]);
++		offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
++				  (0x400 - offset_q_hex[0]) :
++				  (0x1ff - offset_q_hex[0]);
++
++		odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
++		odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
++	} else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {
++		/* Path-a */
++		offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10;
++		offset_q_hex[0] = reg_value32[0] & 0x3ff;
++
++		/*@Before filling into registers,
++		 *offset should be multiplexed (-1)
++		 */
++		offset_i_hex[0] = 0x400 - offset_i_hex[0];
++		offset_q_hex[0] = 0x400 - offset_q_hex[0];
++
++		odm_set_bb_reg(dm, R_0xc10, 0x3c000000,
++			       (0x3c0 & offset_i_hex[0]) >> 6);
++		odm_set_bb_reg(dm, R_0xc10, 0xfc00, 0x3f & offset_i_hex[0]);
++		odm_set_bb_reg(dm, R_0xc14, 0x3c000000,
++			       (0x3c0 & offset_q_hex[0]) >> 6);
++		odm_set_bb_reg(dm, R_0xc14, 0xfc00, 0x3f & offset_q_hex[0]);
++
++		/* Path-b */
++		if (dm->rf_type > RF_1T1R) {
++			offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10;
++			offset_q_hex[1] = reg_value32[1] & 0x3ff;
++
++			/*@Before filling into registers,
++			 *offset should be multiplexed (-1)
++			 */
++			offset_i_hex[1] = 0x400 - offset_i_hex[1];
++			offset_q_hex[1] = 0x400 - offset_q_hex[1];
++
++			odm_set_bb_reg(dm, R_0xe10, 0x3c000000,
++				       (0x3c0 & offset_i_hex[1]) >> 6);
++			odm_set_bb_reg(dm, R_0xe10, 0xfc00,
++				       0x3f & offset_i_hex[1]);
++			odm_set_bb_reg(dm, R_0xe14, 0x3c000000,
++				       (0x3c0 & offset_q_hex[1]) >> 6);
++			odm_set_bb_reg(dm, R_0xe14, 0xfc00,
++				       0x3f & offset_q_hex[1]);
++		}
++	} else if (dm->support_ic_type & (ODM_RTL8192F)) {
++		/* Path-a I:df4[27:18],Q:df4[17:8]*/
++		offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
++		offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
++
++		/*@Before filling into registers,
++		 *offset should be multiplexed (-1)
++		 */
++		offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
++				  (0x400 - offset_i_hex[0]) :
++				  (0xff - offset_i_hex[0]);
++		offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
++				  (0x400 - offset_q_hex[0]) :
++				  (0xff - offset_q_hex[0]);
++		/*Path-a I:c10[7:0],Q:c10[15:8]*/
++		odm_set_bb_reg(dm, R_0xc10, 0xff, offset_i_hex[0]);
++		odm_set_bb_reg(dm, R_0xc10, 0xff00, offset_q_hex[0]);
++
++		/* Path-b */
++		if (dm->rf_type > RF_1T1R) {
++			/* @I:df4[27:18],Q:df4[17:8]*/
++			offset_i_hex[1] = (reg_value32[1] & 0xffc0000) >> 18;
++			offset_q_hex[1] = (reg_value32[1] & 0x3ff00) >> 8;
++
++			/*@Before filling into registers,
++			 *offset should be multiplexed (-1)
++			 */
++			offset_i_hex[1] = (offset_i_hex[1] >= 0x200) ?
++					  (0x400 - offset_i_hex[1]) :
++					  (0xff - offset_i_hex[1]);
++			offset_q_hex[1] = (offset_q_hex[1] >= 0x200) ?
++					  (0x400 - offset_q_hex[1]) :
++					  (0xff - offset_q_hex[1]);
++			/*Path-b I:c18[7:0],Q:c18[15:8]*/
++			odm_set_bb_reg(dm, R_0xc18, 0xff, offset_i_hex[1]);
++			odm_set_bb_reg(dm, R_0xc18, 0xff00, offset_q_hex[1]);
++		}
++	} else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
++	 /*judy modified 20180517*/
++		offset_i_hex[0] = (reg_value32[0] & 0xff80000) >> 19;
++		offset_q_hex[0] = (reg_value32[0] & 0x3fe00) >> 9;
++
++		/*@Before filling into registers,
++		 *offset should be multiplexed (-1)
++		 */
++		offset_i_hex[0] = 0x200 - offset_i_hex[0];
++		offset_q_hex[0] = 0x200 - offset_q_hex[0];
++
++		odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
++		odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
++	}
++#endif
++}
++
++void phydm_receiver_blocking(void *dm_void)
++{
++#ifdef CONFIG_RECEIVER_BLOCKING
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 chnl = *dm->channel;
++	u8 bw = *dm->band_width;
++	u32 bb_regf0 = odm_get_bb_reg(dm, R_0xf0, 0xf000);
++
++	if (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT) ||
++	    *dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
++		return;
++
++	if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 < 8) ||
++	    dm->support_ic_type & ODM_RTL8192E) {
++	    /*@8188E_T version*/
++		if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
++			goto end;
++
++		if (bw == CHANNEL_WIDTH_20 && chnl == 1) {
++			phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2410,
++					  PHYDM_DONT_CARE);
++			dm->is_rx_blocking_en = true;
++		} else if ((bw == CHANNEL_WIDTH_20) && (chnl == 13)) {
++			phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
++					  PHYDM_DONT_CARE);
++			dm->is_rx_blocking_en = true;
++		} else if (dm->is_rx_blocking_en && chnl != 1 && chnl != 13) {
++			phydm_nbi_enable(dm, FUNC_DISABLE);
++			odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
++			dm->is_rx_blocking_en = false;
++		}
++		return;
++	} else if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 >= 8)) {
++	/*@8188E_S version*/
++		if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
++			goto end;
++
++		if (bw == CHANNEL_WIDTH_20 && chnl == 13) {
++			phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
++					  PHYDM_DONT_CARE);
++			dm->is_rx_blocking_en = true;
++		} else if (dm->is_rx_blocking_en && chnl != 13) {
++			phydm_nbi_enable(dm, FUNC_DISABLE);
++			odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
++			dm->is_rx_blocking_en = false;
++		}
++		return;
++	}
++
++end:
++	if (dm->is_rx_blocking_en) {
++		phydm_nbi_enable(dm, FUNC_DISABLE);
++		odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
++		dm->is_rx_blocking_en = false;
++	}
++#endif
++}
++
++void phydm_dyn_bw_indication(void *dm_void)
++{
++#ifdef CONFIG_BW_INDICATION
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 en_auto_bw_th = dm->en_auto_bw_th;
++
++	if (!(dm->support_ic_type & ODM_DYM_BW_INDICATION_SUPPORT))
++		return;
++
++	/*driver decide bw cobime timing*/
++	if (dm->dis_dym_bw_indication) {
++		if (*dm->dis_dym_bw_indication)
++			return;
++	}
++
++	/*check for auto bw*/
++	if (dm->rssi_min <= en_auto_bw_th && dm->is_linked) {
++		phydm_bw_fixed_enable(dm, FUNC_DISABLE);
++		return;
++	}
++
++	phydm_bw_fixed_setting(dm);
++#endif
++}
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm.h
+new file mode 100644
+index 000000000..f124a63fd
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm.h
+@@ -0,0 +1,1541 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __HALDMOUTSRC_H__
++#define __HALDMOUTSRC_H__
++
++/*@============================================================*/
++/*@include files*/
++/*@============================================================*/
++/*PHYDM header*/
++#include "phydm_pre_define.h"
++#include "phydm_features.h"
++#include "phydm_dig.h"
++#ifdef CONFIG_PATH_DIVERSITY
++#include "phydm_pathdiv.h"
++#endif
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++#include "phydm_antdiv.h"
++#endif
++
++#include "phydm_soml.h"
++
++#ifdef CONFIG_SMART_ANTENNA
++#include "phydm_smt_ant.h"
++#endif
++#ifdef CONFIG_ANT_DETECTION
++#include "phydm_antdect.h"
++#endif
++#include "phydm_rainfo.h"
++#ifdef CONFIG_DYNAMIC_TX_TWR
++#include "phydm_dynamictxpower.h"
++#endif
++#include "phydm_cfotracking.h"
++#include "phydm_adaptivity.h"
++#include "phydm_dfs.h"
++#include "phydm_ccx.h"
++#include "txbf/phydm_hal_txbf_api.h"
++#if (PHYDM_LA_MODE_SUPPORT)
++#include "phydm_adc_sampling.h"
++#endif
++#ifdef CONFIG_PSD_TOOL
++#include "phydm_psd.h"
++#endif
++#ifdef PHYDM_PRIMARY_CCA
++#include "phydm_primary_cca.h"
++#endif
++#include "phydm_cck_pd.h"
++#include "phydm_rssi_monitor.h"
++#ifdef PHYDM_AUTO_DEGBUG
++#include "phydm_auto_dbg.h"
++#endif
++#include "phydm_math_lib.h"
++#include "phydm_noisemonitor.h"
++#include "phydm_api.h"
++#ifdef PHYDM_POWER_TRAINING_SUPPORT
++#include "phydm_pow_train.h"
++#endif
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++#include "phydm_lna_sat.h"
++#endif
++#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
++#include "phydm_pmac_tx_setting.h"
++#endif
++#ifdef PHYDM_MP_SUPPORT
++#include "phydm_mp.h"
++#endif
++
++#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
++#include "phydm_cck_rx_pathdiv.h"
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	#include "phydm_beamforming.h"
++#endif
++
++#ifdef CONFIG_DIRECTIONAL_BF
++#include "phydm_direct_bf.h"
++#endif
++
++#include "phydm_regtable.h"
++
++/*@HALRF header*/
++#include "halrf/halrf_iqk.h"
++#include "halrf/halrf_dpk.h"
++#include "halrf/halrf.h"
++#include "halrf/halrf_powertracking.h"
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	#include "halrf/halphyrf_ap.h"
++#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
++	#include "halrf/halphyrf_ce.h"
++#elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++	#include "halrf/halphyrf_win.h"
++#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
++	#include "halrf/halphyrf_iot.h"
++#endif
++
++extern const u16	phy_rate_table[84];
++
++/*@============================================================*/
++/*@Definition */
++/*@============================================================*/
++
++/* Traffic load decision */
++#define TRAFFIC_NO_TP			0
++#define	TRAFFIC_ULTRA_LOW		1
++#define	TRAFFIC_LOW			2
++#define	TRAFFIC_MID			3
++#define	TRAFFIC_HIGH			4
++
++#define	NONE				0
++
++#if defined(DM_ODM_CE_MAC80211)
++#define MAX_2(x, y)					\
++	__max2(typeof(x), typeof(y),			\
++	      x, y)
++#define __max2(t1, t2, x, y) ({		\
++	t1 m80211_max1 = (x);					\
++	t2 m80211_max2 = (y);					\
++	m80211_max1 > m80211_max2 ? m80211_max1 : m80211_max2; })
++
++#define MIN_2(x, y)					\
++	__min2(typeof(x), typeof(y),			\
++	      x, y)
++#define __min2(t1, t2, x, y) ({		\
++	t1 m80211_min1 = (x);					\
++	t2 m80211_min2 = (y);					\
++	m80211_min1 < m80211_min2 ? m80211_min1 : m80211_min2; })
++
++#define DIFF_2(x, y)					\
++	__diff2(typeof(x), typeof(y),			\
++	      x, y)
++#define __diff2(t1, t2, x, y) ({		\
++	t1 __d1 = (x);					\
++	t2 __d2 = (y);					\
++	(__d1 >= __d2) ? (__d1 - __d2) : (__d2 - __d1); })
++#else
++#define MAX_2(_x_, _y_)	(((_x_) > (_y_)) ? (_x_) : (_y_))
++#define MIN_2(_x_, _y_)	(((_x_) < (_y_)) ? (_x_) : (_y_))
++#define DIFF_2(_x_, _y_)	((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_))
++#endif
++
++#define IS_GREATER(_x_, _y_)	(((_x_) >= (_y_)) ? true : false)
++#define IS_LESS(_x_, _y_)	(((_x_) < (_y_)) ? true : false)
++
++#if defined(DM_ODM_CE_MAC80211)
++#define BYTE_DUPLICATE_2_DWORD(B0) ({	\
++	u32 __b_dup = (B0);\
++	(((__b_dup) << 24) | ((__b_dup) << 16) | ((__b_dup) << 8) | (__b_dup));\
++	})
++#else
++#define BYTE_DUPLICATE_2_DWORD(B0)	\
++	(((B0) << 24) | ((B0) << 16) | ((B0) << 8) | (B0))
++#endif
++#define BYTE_2_DWORD(B3, B2, B1, B0)	\
++	(((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0))
++#define BIT_2_BYTE(B3, B2, B1, B0)	\
++	(((B3) << 3) | ((B2) << 2) | ((B1) << 1) | (B0))
++
++/*@For cmn sta info*/
++#if defined(DM_ODM_CE_MAC80211)
++#define is_sta_active(sta) ({	\
++	struct cmn_sta_info *__sta = (sta);	\
++	((__sta) && (__sta->dm_ctrl & STA_DM_CTRL_ACTIVE));	\
++	})
++
++#define IS_FUNC_EN(name) ({	\
++	u8 *__is_func_name = (name);	\
++	(__is_func_name) && (*__is_func_name);	\
++	})
++#else
++#define is_sta_active(sta)	((sta) && (sta->dm_ctrl & STA_DM_CTRL_ACTIVE))
++
++#define IS_FUNC_EN(name)	((name) && (*name))
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	#define PHYDM_WATCH_DOG_PERIOD	1 /*second*/
++#else
++	#define PHYDM_WATCH_DOG_PERIOD	2 /*second*/
++#endif
++
++#define PHY_HIST_SIZE		12
++#define PHY_HIST_TH_SIZE	(PHY_HIST_SIZE - 1)
++
++/*@============================================================*/
++/*structure and define*/
++/*@============================================================*/
++
++#define		dm_type_by_fw		0
++#define		dm_type_by_driver	1
++
++#ifdef BB_RAM_SUPPORT
++
++struct phydm_bb_ram_per_sta {
++	/* @Reg0x1E84 for RAM I/O*/
++	boolean			hw_igi_en;
++	boolean			tx_pwr_offset0_en;
++	boolean			tx_pwr_offset1_en;
++	/* @ macid from 0 to 63, above 63 => mapping to 63*/
++	u8			macid_addr;
++	/* @hw_igi value for paths after packet Tx in a period of time*/
++	u8			hw_igi;
++	/* @tx_pwr_offset0 offset for Tx power index*/
++	s8			tx_pwr_offset0;
++	s8			tx_pwr_offset1;
++
++};
++
++struct phydm_bb_ram_ctrl {
++	/*@ For 98F/14B/22C/12F, each tx_pwr_ofst step will be 1dB*/
++	struct phydm_bb_ram_per_sta pram_sta_ctrl[64];
++	/*------------ For table2 do not set power offset by macid --------*/
++	/* For type == 2'b10, 0x1e70[22:16] = tx_pwr_offset_reg0, 0x1e70[23] = enable */
++	boolean			tx_pwr_ofst_reg0_en;
++	u8			tx_pwr_ofst_reg0;
++	/* For type == 2'b11, 0x1e70[30:24] = tx_pwr_offset_reg1, 0x1e70[31] = enable */
++	boolean			tx_pwr_ofst_reg1_en;
++	u8			tx_pwr_ofst_reg1;
++	boolean			hwigi_watchdog_en;
++};
++
++#endif
++
++struct phydm_phystatus_statistic {
++	/*@[CCK]*/
++	u32			rssi_cck_sum;
++	u32			rssi_cck_cnt;
++	u32			rssi_beacon_sum[RF_PATH_MEM_SIZE];
++	u32			rssi_beacon_cnt;
++	#ifdef PHYSTS_3RD_TYPE_SUPPORT
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	u32			rssi_cck_sum_abv_2ss[RF_PATH_MEM_SIZE - 1];
++	#endif
++	#endif
++	/*@[OFDM]*/
++	u32			rssi_ofdm_sum[RF_PATH_MEM_SIZE];
++	u32			rssi_ofdm_cnt;
++	u32			evm_ofdm_sum;
++	u32			snr_ofdm_sum[RF_PATH_MEM_SIZE];
++	u16			evm_ofdm_hist[PHY_HIST_SIZE];
++	u16			snr_ofdm_hist[PHY_HIST_SIZE];
++	/*@[1SS]*/
++	u32			rssi_1ss_cnt;
++	u32			rssi_1ss_sum[RF_PATH_MEM_SIZE];
++	u32			evm_1ss_sum;
++	u32			snr_1ss_sum[RF_PATH_MEM_SIZE];
++	u16			evm_1ss_hist[PHY_HIST_SIZE];
++	u16			snr_1ss_hist[PHY_HIST_SIZE];
++	/*@[2SS]*/
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	u32			rssi_2ss_cnt;
++	u32			rssi_2ss_sum[RF_PATH_MEM_SIZE];
++	u32			evm_2ss_sum[2];
++	u32			snr_2ss_sum[RF_PATH_MEM_SIZE];
++	u16			evm_2ss_hist[2][PHY_HIST_SIZE];
++	u16			snr_2ss_hist[2][PHY_HIST_SIZE];
++	#endif
++	/*@[3SS]*/
++	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++	u32			rssi_3ss_cnt;
++	u32			rssi_3ss_sum[RF_PATH_MEM_SIZE];
++	u32			evm_3ss_sum[3];
++	u32			snr_3ss_sum[RF_PATH_MEM_SIZE];
++	u16			evm_3ss_hist[3][PHY_HIST_SIZE];
++	u16			snr_3ss_hist[3][PHY_HIST_SIZE];
++	#endif
++	/*@[4SS]*/
++	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	u32			rssi_4ss_cnt;
++	u32			rssi_4ss_sum[RF_PATH_MEM_SIZE];
++	u32			evm_4ss_sum[4];
++	u32			snr_4ss_sum[RF_PATH_MEM_SIZE];
++	u16			evm_4ss_hist[4][PHY_HIST_SIZE];
++	u16			snr_4ss_hist[4][PHY_HIST_SIZE];
++	#endif
++#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
++	u16			p4_cnt[RF_PATH_MEM_SIZE]; /*phy-sts page4 cnt*/
++	u16			cn_sum[RF_PATH_MEM_SIZE]; /*condition number*/
++	u16			cn_hist[RF_PATH_MEM_SIZE][PHY_HIST_SIZE];
++#endif
++};
++
++struct phydm_phystatus_avg {
++	/*@[CCK]*/
++	u8			rssi_cck_avg;
++	u8			rssi_beacon_avg[RF_PATH_MEM_SIZE];
++	#ifdef PHYSTS_3RD_TYPE_SUPPORT
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	u8			rssi_cck_avg_abv_2ss[RF_PATH_MEM_SIZE - 1];
++	#endif
++	#endif
++	/*@[OFDM]*/
++	u8			rssi_ofdm_avg[RF_PATH_MEM_SIZE];
++	u8			evm_ofdm_avg;
++	u8			snr_ofdm_avg[RF_PATH_MEM_SIZE];
++	/*@[1SS]*/
++	u8			rssi_1ss_avg[RF_PATH_MEM_SIZE];
++	u8			evm_1ss_avg;
++	u8			snr_1ss_avg[RF_PATH_MEM_SIZE];
++	/*@[2SS]*/
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	u8			rssi_2ss_avg[RF_PATH_MEM_SIZE];
++	u8			evm_2ss_avg[2];
++	u8			snr_2ss_avg[RF_PATH_MEM_SIZE];
++	#endif
++	/*@[3SS]*/
++	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++	u8			rssi_3ss_avg[RF_PATH_MEM_SIZE];
++	u8			evm_3ss_avg[3];
++	u8			snr_3ss_avg[RF_PATH_MEM_SIZE];
++	#endif
++	/*@[4SS]*/
++	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	u8			rssi_4ss_avg[RF_PATH_MEM_SIZE];
++	u8			evm_4ss_avg[4];
++	u8			snr_4ss_avg[RF_PATH_MEM_SIZE];
++	#endif
++};
++
++struct odm_phy_dbg_info {
++	/*@ODM Write,debug info*/
++	u32			num_qry_phy_status_cck;
++	u32			num_qry_phy_status_ofdm;
++#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) || (defined(PHYSTS_3RD_TYPE_SUPPORT))
++	u32			num_qry_mu_pkt;
++	u32			num_qry_bf_pkt;
++	u16			num_mu_vht_pkt[VHT_RATE_NUM];
++	boolean			is_ldpc_pkt;
++	boolean			is_stbc_pkt;
++	u8			num_of_ppdu[4];
++	u8			gid_num[4];
++#endif
++	u32			condi_num; /*@condition number U(18,4)*/
++	u8			condi_num_cdf[CN_CNT_MAX];
++	u8			num_qry_beacon_pkt;
++	u8			beacon_cnt_in_period; /*@beacon cnt within watchdog period*/
++	u8			beacon_phy_rate;
++	u8			show_phy_sts_all_pkt;	/*@Show phy status witch not match BSSID*/
++	u16			show_phy_sts_max_cnt;	/*@show number of phy-status row data per PHYDM watchdog*/
++	u16			show_phy_sts_cnt;
++	u16			num_qry_legacy_pkt[LEGACY_RATE_NUM];
++	u16			num_qry_ht_pkt[HT_RATE_NUM];
++	u16			num_qry_pkt_sc_20m[LOW_BW_RATE_NUM]; /*@20M SC*/
++	boolean			ht_pkt_not_zero;
++	boolean			low_bw_20_occur;
++	#if ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT)
++	u16			num_qry_vht_pkt[VHT_RATE_NUM];
++	u16			num_qry_pkt_sc_40m[LOW_BW_RATE_NUM]; /*@40M SC*/
++	boolean			vht_pkt_not_zero;
++	boolean			low_bw_40_occur;
++	#endif
++	u16			snr_hist_th[PHY_HIST_TH_SIZE];
++	u16			evm_hist_th[PHY_HIST_TH_SIZE];
++	#ifdef PHYSTS_3RD_TYPE_SUPPORT
++	u16			cn_hist_th[PHY_HIST_TH_SIZE]; /*U(16,1)*/
++	u8			condition_num_seg0;
++	u8			eigen_val[4];
++	s16			cfo_tail[4]; /*per-path's cfo_tail */
++	#endif
++	struct phydm_phystatus_statistic	physts_statistic_info;
++	struct phydm_phystatus_avg		phystatus_statistic_avg;
++};
++
++enum odm_cmninfo {
++	/*@Fixed value*/
++	/*@-----------HOOK BEFORE REG INIT-----------*/
++	ODM_CMNINFO_PLATFORM = 0,
++	ODM_CMNINFO_ABILITY,
++	ODM_CMNINFO_INTERFACE,
++	ODM_CMNINFO_MP_TEST_CHIP,
++	ODM_CMNINFO_IC_TYPE,
++	ODM_CMNINFO_CUT_VER,
++	ODM_CMNINFO_FAB_VER,
++	ODM_CMNINFO_FW_VER,
++	ODM_CMNINFO_FW_SUB_VER,
++	ODM_CMNINFO_RF_TYPE,
++	ODM_CMNINFO_RFE_TYPE,
++	ODM_CMNINFO_DPK_EN,
++	ODM_CMNINFO_BOARD_TYPE,
++	ODM_CMNINFO_PACKAGE_TYPE,
++	ODM_CMNINFO_EXT_LNA,
++	ODM_CMNINFO_5G_EXT_LNA,
++	ODM_CMNINFO_EXT_PA,
++	ODM_CMNINFO_5G_EXT_PA,
++	ODM_CMNINFO_GPA,
++	ODM_CMNINFO_APA,
++	ODM_CMNINFO_GLNA,
++	ODM_CMNINFO_ALNA,
++	ODM_CMNINFO_TDMA,
++	ODM_CMNINFO_EXT_TRSW,
++	ODM_CMNINFO_EXT_LNA_GAIN,
++	ODM_CMNINFO_PATCH_ID,
++	ODM_CMNINFO_BINHCT_TEST,
++	ODM_CMNINFO_BWIFI_TEST,
++	ODM_CMNINFO_SMART_CONCURRENT,
++	ODM_CMNINFO_CONFIG_BB_RF,
++	ODM_CMNINFO_IQKPAOFF,
++	ODM_CMNINFO_HUBUSBMODE,
++	ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,
++	ODM_CMNINFO_TX_TP,
++	ODM_CMNINFO_RX_TP,
++	ODM_CMNINFO_SOUNDING_SEQ,
++	ODM_CMNINFO_REGRFKFREEENABLE,
++	ODM_CMNINFO_RFKFREEENABLE,
++	ODM_CMNINFO_NORMAL_RX_PATH_CHANGE,
++	ODM_CMNINFO_VALID_PATH_SET,
++	ODM_CMNINFO_EFUSE0X3D8,
++	ODM_CMNINFO_EFUSE0X3D7,
++	ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING,
++	ODM_CMNINFO_X_CAP_SETTING,
++	ODM_CMNINFO_ADVANCE_OTA,
++	ODM_CMNINFO_HP_HWID,
++	ODM_CMNINFO_TSSI_ENABLE,
++	ODM_CMNINFO_DIS_DPD,
++	ODM_CMNINFO_POWER_VOLTAGE,
++	ODM_CMNINFO_ANTDIV_GPIO,
++	ODM_CMNINFO_EN_AUTO_BW_TH,
++	ODM_CMNINFO_PEAK_DETECT_MODE,
++	/*@-----------HOOK BEFORE REG INIT-----------*/
++
++	/*@Dynamic value:*/
++
++	/*@--------- POINTER REFERENCE-----------*/
++	ODM_CMNINFO_TX_UNI,
++	ODM_CMNINFO_RX_UNI,
++	ODM_CMNINFO_BAND,
++	ODM_CMNINFO_SEC_CHNL_OFFSET,
++	ODM_CMNINFO_SEC_MODE,
++	ODM_CMNINFO_BW,
++	ODM_CMNINFO_CHNL,
++	ODM_CMNINFO_FORCED_RATE,
++	ODM_CMNINFO_ANT_DIV,
++	ODM_CMNINFO_PATH_DIV,
++	ODM_CMNINFO_ADAPTIVE_SOML,
++	ODM_CMNINFO_ADAPTIVITY,
++	ODM_CMNINFO_SCAN,
++	ODM_CMNINFO_POWER_SAVING,
++	ODM_CMNINFO_ONE_PATH_CCA,
++	ODM_CMNINFO_DRV_STOP,
++	ODM_CMNINFO_PNP_IN,
++	ODM_CMNINFO_INIT_ON,
++	ODM_CMNINFO_ANT_TEST,
++	ODM_CMNINFO_NET_CLOSED,
++	ODM_CMNINFO_P2P_LINK,
++	ODM_CMNINFO_FCS_MODE,
++	ODM_CMNINFO_IS1ANTENNA,
++	ODM_CMNINFO_RFDEFAULTPATH,
++	ODM_CMNINFO_DFS_MASTER_ENABLE,
++	ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC,
++	ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA,
++	ODM_CMNINFO_SOFT_AP_MODE,
++	ODM_CMNINFO_MP_MODE,
++	ODM_CMNINFO_INTERRUPT_MASK,
++	ODM_CMNINFO_BB_OPERATION_MODE,
++	ODM_CMNINFO_BF_ANTDIV_DECISION,
++	ODM_CMNINFO_MANUAL_SUPPORTABILITY,
++	ODM_CMNINFO_EN_DYM_BW_INDICATION,
++	/*@--------- POINTER REFERENCE-----------*/
++
++	/*@------------CALL BY VALUE-------------*/
++	ODM_CMNINFO_WIFI_DIRECT,
++	ODM_CMNINFO_WIFI_DISPLAY,
++	ODM_CMNINFO_LINK_IN_PROGRESS,
++	ODM_CMNINFO_LINK,
++	ODM_CMNINFO_CMW500LINK,
++	ODM_CMNINFO_STATION_STATE,
++	ODM_CMNINFO_RSSI_MIN,
++	ODM_CMNINFO_RSSI_MIN_BY_PATH,
++	ODM_CMNINFO_DBG_COMP,
++	ODM_CMNINFO_RA_THRESHOLD_HIGH,	/*to be removed*/
++	ODM_CMNINFO_RA_THRESHOLD_LOW,	/*to be removed*/
++	ODM_CMNINFO_RF_ANTENNA_TYPE,
++	ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH,
++	ODM_CMNINFO_BE_FIX_TX_ANT,
++	ODM_CMNINFO_BT_ENABLED,
++	ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
++	ODM_CMNINFO_BT_HS_RSSI,
++	ODM_CMNINFO_BT_OPERATION,
++	ODM_CMNINFO_BT_LIMITED_DIG,
++	ODM_CMNINFO_AP_TOTAL_NUM,
++	ODM_CMNINFO_POWER_TRAINING,
++	ODM_CMNINFO_DFS_REGION_DOMAIN,
++	ODM_CMNINFO_BT_CONTINUOUS_TURN,
++	ODM_CMNINFO_IS_DOWNLOAD_FW,
++	ODM_CMNINFO_PHYDM_PATCH_ID,
++	ODM_CMNINFO_RRSR_VAL,
++	ODM_CMNINFO_LINKED_BF_SUPPORT,
++	ODM_CMNINFO_FLATNESS_TYPE,
++	/*@------------CALL BY VALUE-------------*/
++
++	/*@Dynamic ptr array hook itms.*/
++	ODM_CMNINFO_STA_STATUS,
++	ODM_CMNINFO_MAX,
++
++};
++
++enum phydm_rfe_bb_source_sel {
++	PAPE_2G			= 0,
++	PAPE_5G			= 1,
++	LNA0N_2G		= 2,
++	LNAON_5G		= 3,
++	TRSW			= 4,
++	TRSW_B			= 5,
++	GNT_BT			= 6,
++	ZERO			= 7,
++	ANTSEL_0		= 8,
++	ANTSEL_1		= 9,
++	ANTSEL_2		= 0xa,
++	ANTSEL_3		= 0xb,
++	ANTSEL_4		= 0xc,
++	ANTSEL_5		= 0xd,
++	ANTSEL_6		= 0xe,
++	ANTSEL_7		= 0xf
++};
++
++enum phydm_info_query {
++	PHYDM_INFO_FA_OFDM,
++	PHYDM_INFO_FA_CCK,
++	PHYDM_INFO_FA_TOTAL,
++	PHYDM_INFO_CCA_OFDM,
++	PHYDM_INFO_CCA_CCK,
++	PHYDM_INFO_CCA_ALL,
++	PHYDM_INFO_CRC32_OK_VHT,
++	PHYDM_INFO_CRC32_OK_HT,
++	PHYDM_INFO_CRC32_OK_LEGACY,
++	PHYDM_INFO_CRC32_OK_CCK,
++	PHYDM_INFO_CRC32_ERROR_VHT,
++	PHYDM_INFO_CRC32_ERROR_HT,
++	PHYDM_INFO_CRC32_ERROR_LEGACY,
++	PHYDM_INFO_CRC32_ERROR_CCK,
++	PHYDM_INFO_EDCCA_FLAG,
++	PHYDM_INFO_OFDM_ENABLE,
++	PHYDM_INFO_CCK_ENABLE,
++	PHYDM_INFO_CRC32_OK_HT_AGG,
++	PHYDM_INFO_CRC32_ERROR_HT_AGG,
++	PHYDM_INFO_DBG_PORT_0,
++	PHYDM_INFO_CURR_IGI,
++	PHYDM_INFO_RSSI_MIN,
++	PHYDM_INFO_RSSI_MAX,
++	PHYDM_INFO_CLM_RATIO,
++	PHYDM_INFO_NHM_RATIO,
++	PHYDM_INFO_NHM_NOISE_PWR,
++};
++
++enum phydm_api {
++	PHYDM_API_NBI		= 1,
++	PHYDM_API_CSI_MASK	= 2,
++};
++
++enum phydm_func_idx { /*@F_XXX = PHYDM XXX function*/
++
++	F00_DIG			= 0,
++	F01_RA_MASK		= 1,
++	F02_DYN_TXPWR		= 2,
++	F03_FA_CNT		= 3,
++	F04_RSSI_MNTR		= 4,
++	F05_CCK_PD		= 5,
++	F06_ANT_DIV		= 6,
++	F07_SMT_ANT		= 7,
++	F08_PWR_TRAIN		= 8,
++	F09_RA			= 9,
++	F10_PATH_DIV		= 10,
++	F11_DFS			= 11,
++	F12_DYN_ARFR		= 12,
++	F13_ADPTVTY		= 13,
++	F14_CFO_TRK		= 14,
++	F15_ENV_MNTR		= 15,
++	F16_PRI_CCA		= 16,
++	F17_ADPTV_SOML		= 17,
++	F18_LNA_SAT_CHK		= 18,
++};
++
++/*@=[PHYDM supportability]==========================================*/
++enum odm_ability {
++	ODM_BB_DIG		= BIT(F00_DIG),
++	ODM_BB_RA_MASK		= BIT(F01_RA_MASK),
++	ODM_BB_DYNAMIC_TXPWR	= BIT(F02_DYN_TXPWR),
++	ODM_BB_FA_CNT		= BIT(F03_FA_CNT),
++	ODM_BB_RSSI_MONITOR	= BIT(F04_RSSI_MNTR),
++	ODM_BB_CCK_PD		= BIT(F05_CCK_PD),
++	ODM_BB_ANT_DIV		= BIT(F06_ANT_DIV),
++	ODM_BB_SMT_ANT		= BIT(F07_SMT_ANT),
++	ODM_BB_PWR_TRAIN	= BIT(F08_PWR_TRAIN),
++	ODM_BB_RATE_ADAPTIVE	= BIT(F09_RA),
++	ODM_BB_PATH_DIV		= BIT(F10_PATH_DIV),
++	ODM_BB_DFS		= BIT(F11_DFS),
++	ODM_BB_DYNAMIC_ARFR	= BIT(F12_DYN_ARFR),
++	ODM_BB_ADAPTIVITY	= BIT(F13_ADPTVTY),
++	ODM_BB_CFO_TRACKING	= BIT(F14_CFO_TRK),
++	ODM_BB_ENV_MONITOR	= BIT(F15_ENV_MNTR),
++	ODM_BB_PRIMARY_CCA	= BIT(F16_PRI_CCA),
++	ODM_BB_ADAPTIVE_SOML	= BIT(F17_ADPTV_SOML),
++	ODM_BB_LNA_SAT_CHK	= BIT(F18_LNA_SAT_CHK),
++};
++
++/*@=[PHYDM Debug Component]=====================================*/
++enum phydm_dbg_comp {
++	/*@BB Driver Functions*/
++	DBG_DIG			= BIT(F00_DIG),
++	DBG_RA_MASK		= BIT(F01_RA_MASK),
++	DBG_DYN_TXPWR		= BIT(F02_DYN_TXPWR),
++	DBG_FA_CNT		= BIT(F03_FA_CNT),
++	DBG_RSSI_MNTR		= BIT(F04_RSSI_MNTR),
++	DBG_CCKPD		= BIT(F05_CCK_PD),
++	DBG_ANT_DIV		= BIT(F06_ANT_DIV),
++	DBG_SMT_ANT		= BIT(F07_SMT_ANT),
++	DBG_PWR_TRAIN		= BIT(F08_PWR_TRAIN),
++	DBG_RA			= BIT(F09_RA),
++	DBG_PATH_DIV		= BIT(F10_PATH_DIV),
++	DBG_DFS			= BIT(F11_DFS),
++	DBG_DYN_ARFR		= BIT(F12_DYN_ARFR),
++	DBG_ADPTVTY		= BIT(F13_ADPTVTY),
++	DBG_CFO_TRK		= BIT(F14_CFO_TRK),
++	DBG_ENV_MNTR		= BIT(F15_ENV_MNTR),
++	DBG_PRI_CCA		= BIT(F16_PRI_CCA),
++	DBG_ADPTV_SOML		= BIT(F17_ADPTV_SOML),
++	DBG_LNA_SAT_CHK		= BIT(F18_LNA_SAT_CHK),
++	/*Neet to re-arrange*/
++	DBG_PHY_STATUS		= BIT(20),
++	DBG_TMP			= BIT(21),
++	DBG_FW_TRACE		= BIT(22),
++	DBG_TXBF		= BIT(23),
++	DBG_COMMON_FLOW		= BIT(24),
++	DBG_COMP_MCC		= BIT(25),
++	DBG_FW_DM		= BIT(26),
++	DBG_DM_SUMMARY		= BIT(27),
++	ODM_PHY_CONFIG		= BIT(28),
++	ODM_COMP_INIT		= BIT(29),
++	DBG_CMN			= BIT(30),/*@common*/
++	ODM_COMP_API		= BIT(31)
++};
++
++/*@=========================================================*/
++
++/*@ODM_CMNINFO_ONE_PATH_CCA*/
++enum odm_cca_path {
++	ODM_CCA_2R		= 0,
++	ODM_CCA_1R_A		= 1,
++	ODM_CCA_1R_B		= 2,
++};
++
++enum phy_reg_pg_type {
++	PHY_REG_PG_RELATIVE_VALUE = 0,
++	PHY_REG_PG_EXACT_VALUE	= 1
++};
++
++enum phydm_offload_ability {
++	PHYDM_PHY_PARAM_OFFLOAD = BIT(0),
++	PHYDM_RF_IQK_OFFLOAD	= BIT(1),
++	PHYDM_RF_DPK_OFFLOAD	= BIT(2),
++};
++
++enum phydm_init_result {
++	PHYDM_INIT_SUCCESS = 0,
++	PHYDM_INIT_FAIL_BBRF_REG_INVALID = 1
++};
++
++struct phydm_pause_lv {
++	s8			lv_dig;
++	s8			lv_cckpd;
++	s8			lv_antdiv;
++	s8			lv_adapt;
++	s8			lv_adsl;
++};
++
++struct phydm_func_poiner {
++	void (*pause_phydm_handler)(void *dm_void, u32 *val_buf, u8 val_len);
++};
++
++struct pkt_process_info {
++	#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
++	/*@send phystatus in each sampling time*/
++	boolean			physts_auto_swch_en;
++	u8			mac_ppdu_cnt;
++	u8			phy_ppdu_cnt; /*change with phy cca cnt*/
++	u8			page_bitmap_target;
++	u8			page_bitmap_record;
++	u8			ppdu_phy_rate;
++	u8			ppdu_macid;
++	boolean			is_1st_mpdu;
++	#endif
++	u8			lna_idx;
++	u8			vga_idx;
++};
++
++#ifdef ODM_CONFIG_BT_COEXIST
++struct	phydm_bt_info {
++	boolean			is_bt_enabled;		/*@BT is enabled*/
++	boolean			is_bt_connect_process;	/*@BT HS is under connection progress.*/
++	u8			bt_hs_rssi;		/*@BT HS mode wifi rssi value.*/
++	boolean			is_bt_hs_operation;	/*@BT HS mode is under progress*/
++	boolean			is_bt_limited_dig;	/*@BT is busy.*/
++};
++#endif
++
++struct	phydm_iot_center {
++	boolean			is_linked_cmw500;
++	u8			win_patch_id;		/*Customer ID*/
++	boolean			patch_id_100f0401;
++	boolean			patch_id_10120200;
++	boolean			patch_id_40010700;
++	boolean			patch_id_021f0800;
++	u32			phydm_patch_id;		/*temp for CCX IOT */
++};
++
++#if (RTL8822B_SUPPORT)
++struct drp_rtl8822b_struct {
++	enum bb_path path_judge;
++	u16 path_a_cck_fa;
++	u16 path_b_cck_fa;
++};
++#endif
++
++#ifdef CONFIG_MCC_DM
++#define MCC_DM_REG_NUM	32
++struct _phydm_mcc_dm_ {
++	u8		mcc_pre_status;
++	u8		mcc_reg_id[MCC_DM_REG_NUM];
++	u16		mcc_dm_reg[MCC_DM_REG_NUM];
++	u8		mcc_dm_val[MCC_DM_REG_NUM][2];
++	/*mcc DIG*/
++	u8		mcc_rssi[2];
++	/*u8		mcc_igi[2];*/
++
++	/* need to be config by driver*/
++	u8		mcc_status;
++	u8		sta_macid[2][NUM_STA];
++	u16		mcc_rf_ch[2];
++
++};
++#endif
++
++#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
++struct phydm_physts {
++	u8			cck_gi_u_bnd;
++	u8			cck_gi_l_bnd;
++};
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	#if (RT_PLATFORM != PLATFORM_LINUX)
++		typedef
++	#endif
++
++struct dm_struct {
++#else/*for AP, CE Team*/
++struct dm_struct {
++#endif
++	/*@Add for different team use temporarily*/
++	void			*adapter;		/*@For CE/NIC team*/
++	struct rtl8192cd_priv	*priv;			/*@For AP team*/
++	boolean			odm_ready;
++	enum phy_reg_pg_type	phy_reg_pg_value_type;
++	u8			phy_reg_pg_version;
++	u64			support_ability;	/*@PHYDM function Supportability*/
++	u64			pause_ability;		/*@PHYDM function pause Supportability*/
++	u64			debug_components;
++	u8			cmn_dbg_msg_period;
++	u8			cmn_dbg_msg_cnt;
++	u32			fw_debug_components;
++	u32			num_qry_phy_status_all;	/*@CCK + OFDM*/
++	u32			last_num_qry_phy_status_all;
++	u32			rx_pwdb_ave;
++	boolean		is_init_hw_info_by_rfe;
++
++	//TSSI
++	u8			en_tssi_mode;
++
++	/*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
++	boolean			is_cck_high_power;
++	u8			rf_path_rx_enable;
++	/*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
++
++	/* @COMMON INFORMATION */
++
++	/*@Init value*/
++	/*@-----------HOOK BEFORE REG INIT-----------*/
++
++	u8			support_platform;	/*@PHYDM Platform info WIN/AP/CE = 1/2/3 */
++	u8			normal_rx_path;
++	u8			valid_path_set;	/*@use for single rx path only*/
++	boolean			brxagcswitch;		/* @for rx AGC table switch in Microsoft case */
++	u8			support_interface;	/*@PHYDM PCIE/USB/SDIO = 1/2/3*/
++	u32			support_ic_type;	/*@PHYDM supported IC*/
++	enum phydm_api_host	run_in_drv_fw;		/*@PHYDM API is using in FW or Driver*/
++	u8			ic_ip_series;		/*N/AC/JGR3*/
++	enum phydm_phy_sts_type	ic_phy_sts_type;	/*@Type1/type2/type3*/
++	u8			cut_version;		/*@cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/
++	u8			fab_version;		/*@Fab version TSMC/UMC = 0/1*/
++	u8			fw_version;
++	u8			fw_sub_version;
++	u8			rf_type;		/*@RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/
++	u8			rfe_type;
++	u8			board_type;
++	u8			package_type;
++	u16			type_glna;
++	u16			type_gpa;
++	u16			type_alna;
++	u16			type_apa;
++	u8			ext_lna;		/*@with 2G external LNA  NO/Yes = 0/1*/
++	u8			ext_lna_5g;		/*@with 5G external LNA  NO/Yes = 0/1*/
++	u8			ext_pa;			/*@with 2G external PNA  NO/Yes = 0/1*/
++	u8			ext_pa_5g;		/*@with 5G external PNA  NO/Yes = 0/1*/
++	u8			efuse0x3d7;		/*@with Efuse number*/
++	u8			efuse0x3d8;
++	u8			ext_trsw;		/*@with external TRSW  NO/Yes = 0/1*/
++	u8			ext_lna_gain;		/*@gain of external lna*/
++	boolean			is_in_hct_test;
++	u8			wifi_test;
++	boolean			is_dual_mac_smart_concurrent;
++	u32			bk_support_ability;	/*SD4 only*/
++	u8			with_extenal_ant_switch;
++	/*@cck agc relative*/
++	boolean			cck_new_agc;
++	s8			cck_lna_gain_table[8];
++	u8			cck_sat_cnt_th_init;
++	/*@-------------------------------------*/
++	u32			phydm_sys_up_time;
++	u8			num_rf_path;		/*@ex: 8821C=1, 8192E=2, 8814B=4*/
++	u32			soft_ap_special_setting;
++	boolean			boolean_dummy;
++	s8			s8_dummy;
++	u8			u8_dummy;
++	u16			u16_dummy;
++	u32			u32_dummy;
++	u8			rfe_hwsetting_band;
++	u8			p_advance_ota;
++	boolean			hp_hw_id;
++	boolean			BOOLEAN_temp;
++	boolean			is_dfs_band;
++	u8			is_rx_blocking_en;
++	u16			fw_offload_ability;
++	boolean			is_download_fw;
++	boolean			en_dis_dpd;
++	u16			dis_dpd_rate;
++	u8			en_auto_bw_th;
++	#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8197G_SUPPORT)
++	u8			txagc_buff[RF_PATH_MEM_SIZE][PHY_NUM_RATE_IDX];
++	u32			bp_0x9b0;
++	#endif
++	#if (RTL8822C_SUPPORT)
++	u8			ofdm_rxagc_l_bnd[16];
++	boolean			l_bnd_detect[16];
++	#endif
++	boolean			rf_write_no_protection;
++/*@-----------HOOK BEFORE REG INIT-----------*/
++/*@===========================================================*/
++/*@====[ CALL BY Reference ]=========================================*/
++/*@===========================================================*/
++
++	u64			*num_tx_bytes_unicast;	/*@TX Unicast byte cnt*/
++	u64			*num_rx_bytes_unicast;	/*@RX Unicast byte cnt*/
++	u8			*band_type;		/*@2.4G/5G = 0/1*/
++	u8			*sec_ch_offset;		/*@Secondary channel offset don't_care/below/above = 0/1/2*/
++	u8			*security;		/*@security mode Open/WEP/AES/TKIP = 0/1/2/3*/
++	u8			*band_width;		/*@20M/40M/80M = 0/1/2*/
++	u8			*channel;		/*@central CH number*/
++	boolean			*is_scan_in_process;
++	boolean			*is_power_saving;
++	boolean			*is_tdma;
++	u8			*one_path_cca;		/*@CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/
++	u8			*antenna_test;
++	boolean			*is_net_closed;
++	boolean			*is_fcs_mode_enable;	/*@fast channel switch (= MCC mode)*/
++	/*@--------- For 8723B IQK-------------------------------------*/
++	boolean			*is_1_antenna;
++	u8			*rf_default_path;	/* @0:S1, 1:S0 */
++	/*@-----------------------------------------------------------*/
++
++	u16			*forced_data_rate;
++	u8			*enable_antdiv;
++	u8			*enable_pathdiv;
++	u8			*en_adap_soml;
++	u8			*edcca_mode;
++	u8			*hub_usb_mode;		/*@1:USB2.0, 2:USB3.0*/
++	boolean			*is_fw_dw_rsvd_page_in_progress;
++	u32			*current_tx_tp;
++	u32			*current_rx_tp;
++	u8			*sounding_seq;
++	u32			*soft_ap_mode;
++	u8			*mp_mode;
++	u32			*interrupt_mask;
++	u8			*bb_op_mode;
++	u32			*manual_supportability;
++	u8			*dis_dym_bw_indication;
++/*@===========================================================*/
++/*@====[ CALL BY VALUE ]===========================================*/
++/*@===========================================================*/
++
++	u8			disable_phydm_watchdog;
++	boolean			is_link_in_process;
++	boolean			is_wifi_direct;
++	boolean			is_wifi_display;
++	boolean			is_linked;
++	boolean			pre_is_linked;
++	boolean			first_connect;
++	boolean			first_disconnect;
++	boolean			bsta_state;
++	u8			rssi_min;
++	u8			rssi_min_macid;
++	u8			pre_rssi_min;
++	u8			rssi_max;
++	u8			rssi_max_macid;
++	u8			rssi_min_by_path;
++	boolean			is_mp_chip;
++	boolean			is_one_entry_only;
++	u32			one_entry_macid;
++	u32			one_entry_tp;
++	u32			pre_one_entry_tp;
++	u8			pre_number_linked_client;
++	u8			number_linked_client;
++	u8			pre_number_active_client;
++	u8			number_active_client;
++	boolean			is_disable_phy_api;
++	u8			rssi_a;
++	u8			rssi_b;
++	u8			rssi_c;
++	u8			rssi_d;
++	s8			rxsc_80;
++	s8			rxsc_40;
++	s8			rxsc_20;
++	s8			rxsc_l;
++	u64			rssi_trsw;
++	u64			rssi_trsw_h;
++	u64			rssi_trsw_l;
++	u64			rssi_trsw_iso;
++	u8			tx_ant_status; /*TX path enable*/
++	u8			rx_ant_status; /*RX path enable*/
++	#ifdef PHYDM_COMPILE_ABOVE_4SS
++	enum bb_path		tx_4ss_status; /*@Use N-X for 4STS rate*/
++	#endif
++	#ifdef PHYDM_COMPILE_ABOVE_3SS
++	enum bb_path		tx_3ss_status; /*@Use N-X for 3STS rate*/
++	#endif
++	#ifdef PHYDM_COMPILE_ABOVE_2SS
++	enum bb_path		tx_2ss_status; /*@Use N-X for 2STS rate*/
++	#endif
++	enum bb_path		tx_1ss_status; /*@Use N-X for 1STS rate*/
++	u8			cck_lna_idx;
++	u8			cck_vga_idx;
++	u8			curr_station_id;
++	u8			ofdm_agc_idx[4];
++	u8			rx_rate;
++	u8			rate_ss;
++	u8			tx_rate;
++	u8			linked_interval;
++	u8			pre_channel;
++	u32			txagc_offset_value_a;
++	boolean			is_txagc_offset_positive_a;
++	u32			txagc_offset_value_b;
++	boolean			is_txagc_offset_positive_b;
++	u8			ap_total_num;
++	boolean			flatness_type;
++	/*@[traffic]*/
++	u8			traffic_load;
++	u8			pre_traffic_load;
++	u32			tx_tp;			/*@Mbps*/
++	u32			rx_tp;			/*@Mbps*/
++	u32			total_tp;		/*@Mbps*/
++	u8			txrx_state_all;		/*@0:tx, 1:rx, 2:bi-dir*/
++	u64			cur_tx_ok_cnt;
++	u64			cur_rx_ok_cnt;
++	u64			last_tx_ok_cnt;
++	u64			last_rx_ok_cnt;
++	u16			consecutive_idlel_time;	/*@unit: second*/
++	/*@---------------------------*/
++	boolean			is_bb_swing_offset_positive_a;
++	boolean			is_bb_swing_offset_positive_b;
++
++	/*@[DIG]*/
++	boolean			MPDIG_2G;		/*off MPDIG*/
++	u8			times_2g;		/*@for MP DIG*/
++	u8			force_igi;		/*@for debug*/
++
++	/*@[TDMA-DIG]*/
++	u8			tdma_dig_timer_ms;
++	u8			tdma_dig_state_number;
++	u8			tdma_dig_low_upper_bond;
++	u8			force_tdma_low_igi;
++	u8			force_tdma_high_igi;
++	u8			fix_expire_to_zero;
++	boolean			original_dig_restore;
++	/*@---------------------------*/
++
++	/*@[AntDiv]*/
++	u8			ant_div_type;
++	u8			antdiv_rssi;
++	u8			fat_comb_a;
++	u8			fat_comb_b;
++	u8			antdiv_intvl;
++	u8			antdiv_delay;
++	u8			ant_type;
++	u8			ant_type2;
++	u8			pre_ant_type;
++	u8			pre_ant_type2;
++	u8			antdiv_period;
++	u8			evm_antdiv_period;
++	u8			antdiv_select;
++	u8			antdiv_train_num; /*@training time for each antenna in EVM method*/
++	u8			stop_antdiv_rssi_th;
++	u16			stop_antdiv_tp_diff_th;
++	u16			stop_antdiv_tp_th;
++	u8			antdiv_tp_period;
++	u16			tp_active_th;
++	u8			tp_active_occur;
++	u8			path_select;
++	u8			antdiv_evm_en;
++	u8			bdc_holdstate;
++	u8			antdiv_counter;
++	/*@---------------------------*/
++
++	u8			ndpa_period;
++	boolean			h2c_rarpt_connect;
++	boolean			cck_agc_report_type; /*@1:4bit LNA, 0:3bit LNA */
++	u8			print_agc;
++	u8			la_mode;
++	/*@---8821C Antenna and RF Set BTG/WLG/WLA Select---------------*/
++	u8			current_rf_set_8821c;
++	u8			default_rf_set_8821c;
++	u8			current_ant_num_8821c;
++	u8			default_ant_num_8821c;
++	u8			rfe_type_expand;
++	/*@-----------------------------------------------------------*/
++	/*@---For Adaptivtiy---------------------------------------------*/
++	s8			TH_L2H_default;
++	s8			th_edcca_hl_diff_default;
++	s8			th_l2h_ini;
++	s8			th_edcca_hl_diff;
++	boolean			carrier_sense_enable;
++	/*@-----------------------------------------------------------*/
++	u8			pre_dbg_priority;
++	u8			nbi_set_result;
++	u8			c2h_cmd_start;
++	u8			fw_debug_trace[60];
++	u8			pre_c2h_seq;
++	boolean			fw_buff_is_enpty;
++	u32			data_frame_num;
++	/*@--- for spur detection ---------------------------------------*/
++	boolean			en_reg_mntr_bb;
++	boolean			en_reg_mntr_rf;
++	boolean			en_reg_mntr_mac;
++	boolean			en_reg_mntr_byte;
++	/*@--------------------------------------------------------------*/
++#if (RTL8814B_SUPPORT || RTL8812F_SUPPORT)
++	/*@--- for spur detection ---------------------------------------*/
++	u8			dsde_sel;
++	u8			nbi_path_sel;
++	u8			csi_wgt;
++	/*@------------------------------------------*/
++#endif
++	/*@--- for noise detection ---------------------------------------*/
++	boolean			is_noisy_state;
++	boolean			noisy_decision; /*@b_noisy*/
++	boolean			pre_b_noisy;
++	u32			noisy_decision_smooth;
++	/*@-----------------------------------------------------------*/
++
++	/*@--- for MCC ant weighting ------------------------------------*/
++	boolean			is_stop_dym_ant_weighting;
++	/*@-----------------------------------------------------------*/
++
++	boolean			is_disable_dym_ecs;
++	boolean			is_disable_dym_ant_weighting;
++	struct cmn_sta_info	*phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];
++	u8			phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];/*@sta_idx = phydm_macid_table[HW_macid]*/
++
++#if (RATE_ADAPTIVE_SUPPORT)
++	u16			currmin_rpt_time;
++	struct _phydm_txstatistic_ hw_stats;
++	struct _odm_ra_info_	ra_info[ODM_ASSOCIATE_ENTRY_NUM];
++/*Use mac_id as array index. STA mac_id=0*/
++/*VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/
++#endif
++	/*@2012/02/14 MH Add to share 88E ra with other SW team*/
++	/*We need to colelct all support abilit to a proper area.*/
++	boolean			ra_support88e;
++	boolean			*is_driver_stopped;
++	boolean			*is_driver_is_going_to_pnp_set_power_sleep;
++	boolean			*pinit_adpt_in_progress;
++	boolean			is_user_assign_level;
++	u8			RSSI_BT;		/*@come from BT*/
++
++	/*@---PSD Relative ---------------------------------------------*/
++	boolean			is_psd_in_process;
++	boolean			is_psd_active;
++	/*@-----------------------------------------------------------*/
++
++	boolean			bsomlenabled;	/* @D-SoML control */
++	u8			no_ndp_cnts;
++	u8			ndp_cnt_pre;
++	boolean			is_beamformed;
++	u8			linked_bf_support;
++	boolean			bhtstfdisabled;	/* @dynamic HTSTF gain control*/
++	u32			n_iqk_cnt;
++	u32			n_iqk_ok_cnt;
++	u32			n_iqk_fail_cnt;
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	boolean			config_bbrf;
++#endif
++	boolean			is_disable_power_training;
++	boolean			is_bt_continuous_turn;
++	u8			enhance_pwr_th[3];
++	u8			set_pwr_th[3];
++	/*@----------Dyn Tx Pwr ---------------------------------------*/
++#ifdef BB_RAM_SUPPORT
++	struct phydm_bb_ram_ctrl p_bb_ram_ctrl;
++#endif
++	u8			dynamic_tx_high_power_lvl;
++	void	(*fill_desc_dyntxpwr)(void *dm, u8 *desc, u8 dyn_tx_power);
++	u8			last_dtp_lvl;
++	u8			min_power_index;
++	u32			tx_agc_ofdm_18_6;
++	/*-------------------------------------------------------------*/
++	u8			rx_pkt_type;
++
++#ifdef CONFIG_PHYDM_DFS_MASTER
++	u8			dfs_region_domain;
++	u8			*dfs_master_enabled;
++	/*@---phydm_radar_detect_with_dbg_parm start --------------------*/
++	u8			radar_detect_dbg_parm_en;
++	u32			radar_detect_reg_918;
++	u32			radar_detect_reg_91c;
++	u32			radar_detect_reg_920;
++	u32			radar_detect_reg_924;
++
++	u32			radar_detect_reg_a40;
++	u32			radar_detect_reg_a44;
++	u32			radar_detect_reg_a48;
++	u32			radar_detect_reg_a4c;
++	u32			radar_detect_reg_a50;
++	u32			radar_detect_reg_a54;
++
++	u32			radar_detect_reg_f54;
++	u32			radar_detect_reg_f58;
++	u32			radar_detect_reg_f5c;
++	u32			radar_detect_reg_f70;
++	u32			radar_detect_reg_f74;
++	/*@---For zero-wait DFS---------------------------------------*/
++	boolean			seg1_dfs_flag;
++	/*@-----------------------------------------------------------*/
++/*@-----------------------------------------------------------*/
++#endif
++
++/*@=== RTL8721D ===*/
++#if (RTL8721D_SUPPORT)
++	boolean			cbw20_adc80;
++	boolean			invalid_mode;
++	u8			power_voltage;
++	u8			cca_cbw20_lev;
++	u8			cca_cbw40_lev;
++	u8			antdiv_gpio;
++	u8			peak_detect_mode;
++#endif
++
++/*@=== PHYDM Timer ========================================== (start)*/
++
++	struct phydm_timer_list	mpt_dig_timer;
++	struct phydm_timer_list	fast_ant_training_timer;
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++	struct phydm_timer_list	evm_fast_ant_training_timer;
++#endif
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++	struct phydm_timer_list tdma_dig_timer;
++#endif
++	struct phydm_timer_list	sbdcnt_timer;
++
++/*@=== PHYDM Workitem ======================================= (start)*/
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++#if USE_WORKITEM
++	RT_WORK_ITEM		fast_ant_training_workitem;
++	RT_WORK_ITEM		ra_rpt_workitem;
++	RT_WORK_ITEM		sbdcnt_workitem;
++	RT_WORK_ITEM		phydm_evm_antdiv_workitem;
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++	RT_WORK_ITEM		phydm_tdma_dig_workitem;
++#endif
++#endif
++#endif
++
++/*@=== PHYDM Structure ======================================== (start)*/
++	struct	phydm_func_poiner	phydm_func_handler;
++	struct	phydm_iot_center	iot_table;
++
++#ifdef ODM_CONFIG_BT_COEXIST
++	struct	phydm_bt_info		bt_info_table;
++#endif
++
++	struct	pkt_process_info	pkt_proc_struct;
++	struct phydm_adaptivity_struct	adaptivity;
++#ifdef CONFIG_PHYDM_DFS_MASTER
++	struct _DFS_STATISTICS		dfs;
++#endif
++	struct odm_noise_monitor	noise_level;
++	struct odm_phy_dbg_info		phy_dbg_info;
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	struct odm_phy_dbg_info		phy_dbg_info_win_bkp;
++#endif
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	struct phydm_bf_rate_info_jgr3 bf_rate_info_jgr3;
++#endif
++
++#ifdef CONFIG_ADAPTIVE_SOML
++	struct adaptive_soml		dm_soml_table;
++#endif
++
++#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++	#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	struct _BF_DIV_COEX_		dm_bdc_table;
++	#endif
++
++	#if (defined(CONFIG_HL_SMART_ANTENNA))
++	struct smt_ant_honbo		dm_sat_table;
++	#endif
++#endif
++
++#if (defined(CONFIG_SMART_ANTENNA))
++	struct smt_ant			smtant_table;
++#endif
++
++	struct _hal_rf_			rf_table;	/*@for HALRF function*/
++	struct dm_rf_calibration_struct	rf_calibrate_info;
++	struct dm_iqk_info		IQK_info;
++	struct dm_dpk_info		dpk_info;
++	struct dm_dack_info		dack_info;
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	struct phydm_fat_struct		dm_fat_table;
++	struct sw_antenna_switch	dm_swat_table;
++#endif
++	struct phydm_dig_struct		dm_dig_table;
++
++#ifdef PHYDM_SUPPORT_CCKPD
++	struct phydm_cckpd_struct	dm_cckpd_table;
++
++	#ifdef PHYDM_DCC_ENHANCE
++	struct phydm_dcc_struct		dm_dcc_info; /*dig cckpd coex*/
++	#endif
++#endif
++
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++	struct phydm_lna_sat_t		dm_lna_sat_info;
++#endif
++
++#ifdef CONFIG_MCC_DM
++	struct _phydm_mcc_dm_ mcc_dm;
++#endif
++
++#ifdef PHYDM_PRIMARY_CCA
++	struct phydm_pricca_struct	dm_pri_cca;
++#endif
++
++	struct ra_table			dm_ra_table;
++	struct phydm_fa_struct		false_alm_cnt;
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++	struct phydm_fa_acc_struct	false_alm_cnt_acc;
++#ifdef IS_USE_NEW_TDMA
++	struct phydm_fa_acc_struct	false_alm_cnt_acc_low;
++#endif
++#endif
++	struct phydm_cfo_track_struct	dm_cfo_track;
++	struct ccx_info			dm_ccx_info;
++
++	struct odm_power_trim_data	power_trim_data;
++#if (RTL8822B_SUPPORT)
++	struct drp_rtl8822b_struct	phydm_rtl8822b;
++#endif
++
++#ifdef CONFIG_PSD_TOOL
++	struct psd_info			dm_psd_table;
++#endif
++
++#if (PHYDM_LA_MODE_SUPPORT)
++	struct rt_adcsmp		adcsmp;
++#endif
++
++#if (defined(CONFIG_PATH_DIVERSITY))
++	struct _ODM_PATH_DIVERSITY_	dm_path_div;
++#endif
++
++#if (defined(CONFIG_ANT_DETECTION))
++	struct _ANT_DETECTED_INFO	ant_detected_info;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++	struct _RT_BEAMFORMING_INFO 	beamforming_info;
++#endif
++#endif
++#ifdef PHYDM_AUTO_DEGBUG
++	struct	phydm_auto_dbg_struct	auto_dbg_table;
++#endif
++
++	struct	phydm_pause_lv		pause_lv_table;
++	struct	phydm_api_stuc		api_table;
++#ifdef PHYDM_POWER_TRAINING_SUPPORT
++	struct	phydm_pow_train_stuc	pow_train_table;
++#endif
++
++#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
++	struct phydm_pmac_tx dm_pmac_tx_table;
++#endif
++
++#ifdef PHYDM_MP_SUPPORT
++	struct phydm_mp dm_mp_table;
++#endif
++
++#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
++	struct phydm_cck_rx_pathdiv dm_cck_rx_pathdiv_table;
++#endif
++/*@==========================================================*/
++
++#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
++	/*@-------------------phydm_phystatus report --------------------*/
++	struct phydm_physts dm_physts_table;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++
++#if (RT_PLATFORM != PLATFORM_LINUX)
++} dm_struct;	/*@DM_Dynamic_Mechanism_Structure*/
++#else
++};
++#endif
++
++#else	/*@for AP,CE Team*/
++};
++#endif
++
++enum phydm_adv_ota {
++	PHYDM_PATHB_1RCCA		= BIT(0),
++	PHYDM_HP_OTA_SETTING_A		= BIT(1),
++	PHYDM_HP_OTA_SETTING_B		= BIT(2),
++	PHYDM_ASUS_OTA_SETTING		= BIT(3),
++	PHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4),
++	PHYDM_HP_OTA_SETTING_CCK_PATH	= BIT(5),
++	PHYDM_LENOVO_OTA_SETTING_NBI_CSI = BIT(6),
++
++};
++
++enum phydm_bb_op_mode {
++	PHYDM_PERFORMANCE_MODE	= 0,		/*Service one device*/
++	PHYDM_BALANCE_MODE	= 1,		/*@Service more than one device*/
++};
++
++enum phydm_structure_type {
++	PHYDM_FALSEALMCNT,
++	PHYDM_CFOTRACK,
++	PHYDM_ADAPTIVITY,
++	PHYDM_DFS,
++	PHYDM_ROMINFO,
++
++};
++
++enum odm_bb_config_type {
++	CONFIG_BB_PHY_REG,
++	CONFIG_BB_AGC_TAB,
++	CONFIG_BB_AGC_TAB_2G,
++	CONFIG_BB_AGC_TAB_5G,
++	CONFIG_BB_PHY_REG_PG,
++	CONFIG_BB_PHY_REG_MP,
++	CONFIG_BB_AGC_TAB_DIFF,
++	CONFIG_BB_RF_CAL_INIT,
++};
++
++enum odm_rf_config_type {
++	CONFIG_RF_RADIO,
++	CONFIG_RF_TXPWR_LMT,
++	CONFIG_RF_SYN_RADIO,
++};
++
++enum odm_fw_config_type {
++	CONFIG_FW_NIC,
++	CONFIG_FW_NIC_2,
++	CONFIG_FW_AP,
++	CONFIG_FW_AP_2,
++	CONFIG_FW_MP,
++	CONFIG_FW_WOWLAN,
++	CONFIG_FW_WOWLAN_2,
++	CONFIG_FW_AP_WOWLAN,
++	CONFIG_FW_BT,
++};
++
++/*status code*/
++#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
++enum rt_status {
++	RT_STATUS_SUCCESS,
++	RT_STATUS_FAILURE,
++	RT_STATUS_PENDING,
++	RT_STATUS_RESOURCE,
++	RT_STATUS_INVALID_CONTEXT,
++	RT_STATUS_INVALID_PARAMETER,
++	RT_STATUS_NOT_SUPPORT,
++	RT_STATUS_OS_API_FAILED,
++};
++#endif	/*@end of enum rt_status definition*/
++
++void
++phydm_watchdog_lps(struct dm_struct *dm);
++
++void
++phydm_watchdog_lps_32k(struct dm_struct *dm);
++
++void
++phydm_txcurrentcalibration(struct dm_struct *dm);
++
++void
++phydm_dm_early_init(struct dm_struct *dm);
++
++enum phydm_init_result
++odm_dm_init(struct dm_struct *dm);
++
++void
++odm_dm_reset(struct dm_struct *dm);
++
++void
++phydm_fwoffload_ability_init(struct dm_struct *dm,
++			     enum phydm_offload_ability offload_ability);
++
++void
++phydm_fwoffload_ability_clear(struct dm_struct *dm,
++			      enum phydm_offload_ability offload_ability);
++
++void
++phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
++			char *output, u32 *_out_len);
++
++void
++phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type);
++
++void
++phydm_watchdog(struct dm_struct *dm);
++
++void
++phydm_watchdog_mp(struct dm_struct *dm);
++
++void
++phydm_pause_func_init(void *dm_void);
++
++u8
++phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
++		 enum phydm_pause_type pause_type,
++		 enum phydm_pause_level pause_lv, u8 val_lehgth, u32 *val_buf);
++
++void
++phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
++			 char *output, u32 *_out_len);
++
++void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm,
++				enum phydm_pause_type pause_type, u8 rssi);
++
++void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx,
++			 boolean enable);
++
++void
++odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, u64 value);
++
++void
++odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info, void *value);
++
++void
++odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value);
++
++u32
++phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type);
++
++void
++odm_init_all_timers(struct dm_struct *dm);
++
++void
++odm_cancel_all_timers(struct dm_struct *dm);
++
++void
++odm_release_all_timers(struct dm_struct *dm);
++
++void *
++phydm_get_structure(struct dm_struct *dm, u8 structure_type);
++
++void
++phydm_dc_cancellation(struct dm_struct *dm);
++
++void
++phydm_receiver_blocking(void *dm_void);
++
++void
++phydm_dyn_bw_indication(void *dm_void);
++
++void
++phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en);
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void
++odm_init_all_work_items(
++	struct dm_struct	*dm
++);
++void
++odm_free_all_work_items(
++	struct dm_struct	*dm
++);
++#endif	/*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++void
++odm_dtc(struct dm_struct *dm);
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++void
++odm_init_all_threads(
++	struct dm_struct	*dm
++);
++
++void
++odm_stop_all_threads(
++	struct dm_struct	*dm
++);
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm.mk b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm.mk
+new file mode 100644
+index 000000000..305200b87
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm.mk
+@@ -0,0 +1,233 @@
++EXTRA_CFLAGS += -I$(src)/hal/phydm
++
++_PHYDM_FILES := hal/phydm/phydm_debug.o	\
++								hal/phydm/phydm_antdiv.o\
++								hal/phydm/phydm_soml.o\
++								hal/phydm/phydm_smt_ant.o\
++								hal/phydm/phydm_antdect.o\
++								hal/phydm/phydm_interface.o\
++								hal/phydm/phydm_phystatus.o\
++								hal/phydm/phydm_hwconfig.o\
++								hal/phydm/phydm.o\
++								hal/phydm/phydm_dig.o\
++								hal/phydm/phydm_pathdiv.o\
++								hal/phydm/phydm_rainfo.o\
++								hal/phydm/phydm_dynamictxpower.o\
++								hal/phydm/phydm_adaptivity.o\
++								hal/phydm/phydm_cfotracking.o\
++								hal/phydm/phydm_noisemonitor.o\
++								hal/phydm/phydm_beamforming.o\
++								hal/phydm/phydm_direct_bf.o\
++								hal/phydm/phydm_dfs.o\
++								hal/phydm/txbf/halcomtxbf.o\
++								hal/phydm/txbf/haltxbfinterface.o\
++								hal/phydm/txbf/phydm_hal_txbf_api.o\
++								hal/phydm/phydm_adc_sampling.o\
++								hal/phydm/phydm_ccx.o\
++								hal/phydm/phydm_psd.o\
++								hal/phydm/phydm_primary_cca.o\
++								hal/phydm/phydm_cck_pd.o\
++								hal/phydm/phydm_rssi_monitor.o\
++								hal/phydm/phydm_auto_dbg.o\
++								hal/phydm/phydm_math_lib.o\
++								hal/phydm/phydm_api.o\
++								hal/phydm/phydm_pow_train.o\
++								hal/phydm/phydm_lna_sat.o\
++								hal/phydm/phydm_pmac_tx_setting.o\
++								hal/phydm/phydm_mp.o\
++								hal/phydm/phydm_cck_rx_pathdiv.o\
++								hal/phydm/halrf/halrf.o\
++								hal/phydm/halrf/halrf_debug.o\
++								hal/phydm/halrf/halphyrf_ce.o\
++								hal/phydm/halrf/halrf_powertracking_ce.o\
++								hal/phydm/halrf/halrf_powertracking.o\
++								hal/phydm/halrf/halrf_kfree.o\
++								hal/phydm/halrf/halrf_psd.o
++		
++ifeq ($(CONFIG_RTL8188E), y)
++RTL871X = rtl8188e
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\
++								hal/phydm/$(RTL871X)/hal8188erateadaptive.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8188e.o
++endif
++
++ifeq ($(CONFIG_RTL8192E), y)
++RTL871X = rtl8192e
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8192e.o
++endif
++
++
++ifeq ($(CONFIG_RTL8812A), y)
++RTL871X = rtl8812a
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8812a.o\
++								hal/phydm/txbf/haltxbfjaguar.o
++endif
++
++ifeq ($(CONFIG_RTL8821A), y)
++RTL871X = rtl8821a
++_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\
++								hal/phydm/rtl8821a/halhwimg8821a_bb.o\
++								hal/phydm/rtl8821a/halhwimg8821a_rf.o\
++								hal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\
++								hal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\
++								hal/phydm/rtl8821a/phydm_regconfig8821a.o\
++								hal/phydm/rtl8821a/phydm_rtl8821a.o\
++								hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\
++								hal/phydm/txbf/haltxbfjaguar.o
++endif
++
++
++ifeq ($(CONFIG_RTL8723B), y)
++RTL871X = rtl8723b
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\
++								hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8723b.o
++endif
++
++
++ifeq ($(CONFIG_RTL8814A), y)
++RTL871X = rtl8814a
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\
++								hal/phydm/halrf/$(RTL871X)/halhwimg8814a_rf.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8814a.o\
++								hal/phydm/txbf/haltxbf8814a.o
++endif
++
++
++ifeq ($(CONFIG_RTL8723C), y)
++RTL871X = rtl8703b
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8703b.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8703b.o
++endif
++
++ifeq ($(CONFIG_RTL8723D), y)
++RTL871X = rtl8723d
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8723d.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8723d.o
++endif
++
++
++ifeq ($(CONFIG_RTL8710B), y)
++RTL871X = rtl8710b
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8710b_mac.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8710b.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8710b.o\
++								hal/phydm/halrf/$(RTL871X)/halhwimg8710b_rf.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8710b.o
++endif
++
++
++ifeq ($(CONFIG_RTL8188F), y)
++RTL871X = rtl8188f
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8188f.o \
++								hal/phydm/$(RTL871X)/phydm_rtl8188f.o
++endif
++
++ifeq ($(CONFIG_RTL8822B), y)
++RTL871X = rtl8822b
++_PHYDM_FILES +=	hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \
++								hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \
++								hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \
++								hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \
++								hal/phydm/halrf/$(RTL871X)/halhwimg8822b_rf.o \
++								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \
++								hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \
++								hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \
++								hal/phydm/$(RTL871X)/phydm_rtl8822b.o
++
++_PHYDM_FILES +=	hal/phydm/txbf/haltxbf8822b.o
++endif
++
++
++ifeq ($(CONFIG_RTL8821C), y)
++RTL871X = rtl8821c
++_PHYDM_FILES +=	hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \
++								hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \
++								hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \
++								hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\
++								hal/phydm/halrf/$(RTL871X)/halhwimg8821c_rf.o \
++								hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o
++endif
++ifeq ($(CONFIG_RTL8192F), y)
++RTL871X = rtl8192f
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8192f_mac.o\
++								hal/phydm/$(RTL871X)/phydm_hal_api8192f.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8192f.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8192f.o\
++								hal/phydm/halrf/$(RTL871X)/halhwimg8192f_rf.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8192f.o	
++endif
++
++ifeq ($(CONFIG_RTL8198F), y)
++RTL871X = rtl8198f
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8198f_mac.o\
++								hal/phydm/$(RTL871X)/phydm_hal_api8198f.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8198f.o\
++								hal/phydm/halrf/$(RTL871X)/halhwimg8198f_rf.o
++endif
++
++ifeq ($(CONFIG_RTL8822C), y)
++RTL871X = rtl8822c
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822c_bb.o\
++								hal/phydm/$(RTL871X)/phydm_hal_api8822c.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8822c.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8822c.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8822c.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822c.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_tssi_8822c.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_dpk_8822c.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_txgapk_8822c.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822c.o\
++								hal/phydm/halrf/$(RTL871X)/halhwimg8822c_rf.o
++endif
++
++ifeq ($(CONFIG_RTL8814B), y)
++RTL871X = rtl8814b
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814b_bb.o\
++								hal/phydm/$(RTL871X)/phydm_hal_api8814b.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8814b.o\
++								hal/phydm/halrf/$(RTL871X)/halhwimg8814b_rf.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8814b.o \
++								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814b.o \
++								hal/phydm/halrf/$(RTL871X)/halrf_dpk_8814b.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8814b.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_txgapk_8814b.o
++endif
+\ No newline at end of file
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_adaptivity.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_adaptivity.c
+new file mode 100644
+index 000000000..96b134c19
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_adaptivity.c
+@@ -0,0 +1,847 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ ************************************************************/
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	#if WPP_SOFTWARE_TRACE
++		#include "PhyDM_Adaptivity.tmh"
++	#endif
++#endif
++#ifdef PHYDM_SUPPORT_ADAPTIVITY
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++boolean
++phydm_check_channel_plan(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
++	void *adapter = dm->adapter;
++	PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
++
++	if (mgnt_info->RegEnableAdaptivity != 2)
++		return false;
++
++	if (!dm->carrier_sense_enable) { /*@check domain Code for adaptivity or CarrierSense*/
++		if ((*dm->band_type == ODM_BAND_5G) &&
++		    !(adapt->regulation_5g == REGULATION_ETSI || adapt->regulation_5g == REGULATION_WW)) {
++			PHYDM_DBG(dm, DBG_ADPTVTY,
++				  "adaptivity skip 5G domain code : %d\n",
++				  adapt->regulation_5g);
++			return true;
++		} else if ((*dm->band_type == ODM_BAND_2_4G) &&
++			   !(adapt->regulation_2g == REGULATION_ETSI || adapt->regulation_2g == REGULATION_WW)) {
++			PHYDM_DBG(dm, DBG_ADPTVTY,
++				  "adaptivity skip 2.4G domain code : %d\n",
++				  adapt->regulation_2g);
++			return true;
++		} else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) {
++			PHYDM_DBG(dm, DBG_ADPTVTY,
++				  "adaptivity neither 2G nor 5G band, return\n");
++			return true;
++		}
++	} else {
++		if ((*dm->band_type == ODM_BAND_5G) &&
++		    !(adapt->regulation_5g == REGULATION_MKK || adapt->regulation_5g == REGULATION_WW)) {
++			PHYDM_DBG(dm, DBG_ADPTVTY,
++				  "CarrierSense skip 5G domain code : %d\n",
++				  adapt->regulation_5g);
++			return true;
++		} else if ((*dm->band_type == ODM_BAND_2_4G) &&
++			   !(adapt->regulation_2g == REGULATION_MKK || adapt->regulation_2g == REGULATION_WW)) {
++			PHYDM_DBG(dm, DBG_ADPTVTY,
++				  "CarrierSense skip 2.4G domain code : %d\n",
++				  adapt->regulation_2g);
++			return true;
++		} else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) {
++			PHYDM_DBG(dm, DBG_ADPTVTY,
++				  "CarrierSense neither 2G nor 5G band, return\n");
++			return true;
++		}
++	}
++
++	return false;
++}
++
++boolean
++phydm_soft_ap_special_set(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
++	boolean disable_ap_adapt_setting = false;
++
++	if (dm->soft_ap_mode != NULL) {
++		if (*dm->soft_ap_mode != 0 &&
++		    (dm->soft_ap_special_setting & BIT(0)))
++			disable_ap_adapt_setting = true;
++		else
++			disable_ap_adapt_setting = false;
++		PHYDM_DBG(dm, DBG_ADPTVTY,
++			  "soft_ap_setting = %x, soft_ap = %d, dis_ap_adapt = %d\n",
++			  dm->soft_ap_special_setting, *dm->soft_ap_mode,
++			  disable_ap_adapt_setting);
++	}
++
++	return disable_ap_adapt_setting;
++}
++
++boolean
++phydm_ap_num_check(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
++	boolean dis_adapt = false;
++
++	if  (dm->ap_total_num > adapt->ap_num_th)
++		dis_adapt = true;
++	else
++		dis_adapt = false;
++
++	PHYDM_DBG(dm, DBG_ADPTVTY, "AP total num = %d, AP num threshold = %d\n",
++		  dm->ap_total_num, adapt->ap_num_th);
++	return dis_adapt;
++}
++
++void phydm_check_adaptivity(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
++	boolean disable_adapt = false;
++
++	if (!adapt->mode_cvrt_en)
++		return;
++
++	if (phydm_check_channel_plan(dm) || phydm_ap_num_check(dm) ||
++	    phydm_soft_ap_special_set(dm))
++		disable_adapt = true;
++
++	if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE && disable_adapt)
++		*dm->edcca_mode = PHYDM_EDCCA_NORMAL_MODE;
++	else if (*dm->edcca_mode == PHYDM_EDCCA_NORMAL_MODE && !disable_adapt)
++		*dm->edcca_mode = PHYDM_EDCCA_ADAPT_MODE;
++}
++
++void phydm_set_l2h_th_ini_win(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	 /*@ [New Format: JGR3]IGI-idx:45 = RSSI:35 = -65dBm*/
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		if (dm->support_ic_type & ODM_RTL8822C)
++			dm->th_l2h_ini = 45;
++		else if (dm->support_ic_type & ODM_RTL8814B)
++			dm->th_l2h_ini = 49;
++	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++	 /*@ [Old Format] -11+base(50) = IGI_idx:39 = RSSI:29 = -71dBm*/
++		if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812)) {
++			dm->th_l2h_ini = -17;
++		} else {
++			if (*dm->band_type == ODM_BAND_5G)
++				dm->th_l2h_ini = -14;
++			else if (*dm->band_type == ODM_BAND_2_4G)
++				dm->th_l2h_ini = -9;
++		}
++	} else { /*ODM_IC_11N_SERIES*/
++		dm->th_l2h_ini = -9;
++	}
++}
++#endif
++
++void phydm_dig_up_bound_lmt_en(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
++
++	if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE ||
++	    !dm->is_linked) {
++		adapt->igi_up_bound_lmt_cnt = 0;
++		adapt->igi_lmt_en = false;
++		return;
++	}
++
++	if (dm->total_tp > 1) {
++		adapt->igi_lmt_en = true;
++		adapt->igi_up_bound_lmt_cnt = adapt->igi_up_bound_lmt_val;
++		PHYDM_DBG(dm, DBG_ADPTVTY,
++			  "TP >1, Start limit IGI upper bound\n");
++	} else {
++		if (adapt->igi_up_bound_lmt_cnt == 0)
++			adapt->igi_lmt_en = false;
++		else
++			adapt->igi_up_bound_lmt_cnt--;
++	}
++
++	PHYDM_DBG(dm, DBG_ADPTVTY, "IGI_lmt_cnt = %d\n",
++		  adapt->igi_up_bound_lmt_cnt);
++}
++
++void phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		odm_set_bb_reg(dm, R_0x84c, MASKBYTE2, (u8)L2H + 0x80);
++		odm_set_bb_reg(dm, R_0x84c, MASKBYTE3, (u8)H2L + 0x80);
++	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		odm_set_bb_reg(dm, R_0xc4c, MASKBYTE0, (u8)L2H);
++		odm_set_bb_reg(dm, R_0xc4c, MASKBYTE2, (u8)H2L);
++	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		odm_set_bb_reg(dm, R_0x8a4, MASKBYTE0, (u8)L2H);
++		odm_set_bb_reg(dm, R_0x8a4, MASKBYTE1, (u8)H2L);
++	}
++}
++
++void phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (state == PHYDM_IGNORE_EDCCA) {
++		/*@ignore EDCCA*/
++		odm_set_mac_reg(dm, R_0x520, BIT(15), 1);
++		/*@enable EDCCA count down*/
++		odm_set_mac_reg(dm, R_0x524, BIT(11), 0);
++	} else { /*@don't set MAC ignore EDCCA signal*/
++		/*@don't ignore EDCCA*/
++		odm_set_mac_reg(dm, R_0x520, BIT(15), 0);
++		/*@disable EDCCA count down*/
++		odm_set_mac_reg(dm, R_0x524, BIT(11), 1);
++	}
++	PHYDM_DBG(dm, DBG_ADPTVTY, "EDCCA enable state = %d\n", state);
++}
++
++void phydm_search_pwdb_lower_bound(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
++	u32 value32 = 0, reg_value32 = 0;
++	u8 cnt = 0, try_count = 0;
++	u8 tx_edcca1 = 0;
++	boolean is_adjust = true;
++	s8 th_l2h, th_h2l, igi_target_dc = 0x32;
++	s8 diff = 0;
++	s8 IGI = adapt->igi_base + 30 + dm->th_l2h_ini - dm->th_edcca_hl_diff;
++
++	halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
++	diff = igi_target_dc - IGI;
++	th_l2h = dm->th_l2h_ini + diff;
++	if (th_l2h > 10)
++		th_l2h = 10;
++
++	th_h2l = th_l2h - dm->th_edcca_hl_diff;
++	phydm_set_edcca_threshold(dm, th_h2l, th_l2h);
++	ODM_delay_ms(30);
++
++	while (is_adjust) {
++		/*@check CCA status*/
++		/*set debug port to 0x0*/
++		if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) {
++			reg_value32 = phydm_get_bb_dbg_port_val(dm);
++
++			while (reg_value32 & BIT(3) && try_count < 3) {
++				ODM_delay_ms(3);
++				try_count = try_count + 1;
++				reg_value32 = phydm_get_bb_dbg_port_val(dm);
++			}
++			phydm_release_bb_dbg_port(dm);
++			try_count = 0;
++		}
++
++		/*@count EDCCA signal = 1 times*/
++		for (cnt = 0; cnt < 20; cnt++) {
++			if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1,
++						  adapt->adaptivity_dbg_port)) {
++				value32 = phydm_get_bb_dbg_port_val(dm);
++				phydm_release_bb_dbg_port(dm);
++			}
++
++			if (value32 & BIT(30) && dm->support_ic_type &
++						 (ODM_RTL8723B | ODM_RTL8188E))
++				tx_edcca1 = tx_edcca1 + 1;
++			else if (value32 & BIT(29))
++				tx_edcca1 = tx_edcca1 + 1;
++		}
++
++		if (tx_edcca1 > 1) {
++			IGI = IGI - 1;
++			th_l2h = th_l2h + 1;
++			if (th_l2h > 10)
++				th_l2h = 10;
++
++			th_h2l = th_l2h - dm->th_edcca_hl_diff;
++			phydm_set_edcca_threshold(dm, th_h2l, th_l2h);
++			tx_edcca1 = 0;
++			if (th_l2h == 10)
++				is_adjust = false;
++
++		} else {
++			is_adjust = false;
++		}
++	}
++
++	adapt->adapt_igi_up = IGI - ADAPT_DC_BACKOFF;
++	adapt->h2l_lb = th_h2l + ADAPT_DC_BACKOFF;
++	adapt->l2h_lb = th_l2h + ADAPT_DC_BACKOFF;
++
++	halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
++	phydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/
++}
++
++boolean phydm_re_search_condition(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
++	u8 adaptivity_igi_upper = adaptivity->adapt_igi_up + ADAPT_DC_BACKOFF;
++
++	if (adaptivity_igi_upper <= 0x26)
++		return true;
++	else
++		return false;
++}
++
++void phydm_set_l2h_th_ini(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	 /*@ [New Format: JGR3]IGI-idx:45 = RSSI:35 = -65dBm*/
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		if (dm->support_ic_type & ODM_RTL8822C)
++			dm->th_l2h_ini = 45;
++		else if (dm->support_ic_type & ODM_RTL8814B)
++			dm->th_l2h_ini = 49;
++	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++	 /*@ [Old Format] -11+base(50) = IGI_idx:39 = RSSI:29 = -71dBm*/
++		if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812))
++			dm->th_l2h_ini = -17;
++		else
++			dm->th_l2h_ini = -14;
++	} else { /*ODM_IC_11N_SERIES*/
++		if (dm->support_ic_type & ODM_RTL8721D)
++			dm->th_l2h_ini = -14;
++		else
++			dm->th_l2h_ini = -11;
++	}
++}
++
++void phydm_set_l2h_th_ini_carrier_sense(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		dm->th_l2h_ini = 60; /*@ -50dBm*/
++	else
++		dm->th_l2h_ini = 10; /*@ -50dBm*/
++}
++
++void phydm_set_forgetting_factor(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
++		return;
++
++	if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A |
++				  ODM_RTL8195B))
++		odm_set_bb_reg(dm, R_0x8a0, BIT(1) | BIT(0), 0);
++}
++
++void phydm_edcca_decision_opt(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
++		return;
++
++	if (dm->support_ic_type & ODM_RTL8822B)
++		odm_set_bb_reg(dm, R_0x8dc, BIT(5), 0x1);
++	else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
++		odm_set_bb_reg(dm, R_0xce8, BIT(13), 0x1);
++	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		odm_set_bb_reg(dm, R_0x844, BIT(30) | BIT(29), 0x0);
++}
++
++void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,
++			    char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	char help[] = "-h";
++	u32 dm_value[10] = {0};
++	u8 i = 0, input_idx = 0;
++	u32 reg_value32 = 0;
++	s8 h2l_diff = 0;
++
++	for (i = 0; i < 5; i++) {
++		if (input[i + 1]) {
++			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
++			input_idx++;
++		}
++	}
++	if (strcmp(input[1], help) == 0) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Show adaptivity message: {0}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Enter debug mode: {1} {th_l2h_ini} {th_edcca_hl_diff}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Leave debug mode: {2}\n");
++		goto out;
++	}
++
++	if (input_idx == 0)
++		return;
++
++	if (dm_value[0] == PHYDM_ADAPT_DEBUG) {
++		adaptivity->debug_mode = true;
++		if (dm_value[1] != 0)
++			dm->th_l2h_ini = (s8)dm_value[1];
++		if (dm_value[2] != 0)
++			dm->th_edcca_hl_diff = (s8)dm_value[2];
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
++			 dm->th_l2h_ini, dm->th_edcca_hl_diff);
++	} else if (dm_value[0] == PHYDM_ADAPT_RESUME) {
++		adaptivity->debug_mode = false;
++		dm->th_l2h_ini = adaptivity->th_l2h_ini_backup;
++		dm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup;
++	} else if (dm_value[0] == PHYDM_ADAPT_MSG) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "debug_mode = %s, th_l2h_ini = %d\n",
++			 (adaptivity->debug_mode ? "TRUE" : "FALSE"),
++			 dm->th_l2h_ini);
++		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++			reg_value32 = odm_get_bb_reg(dm, R_0x84c, MASKDWORD);
++			h2l_diff = (s8)((0x00ff0000 & reg_value32) >> 16) -
++				   (s8)((0xff000000 & reg_value32) >> 24);
++		} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++			reg_value32 = odm_get_bb_reg(dm, R_0xc4c, MASKDWORD);
++			h2l_diff = (s8)(0x000000ff & reg_value32) -
++				   (s8)((0x00ff0000 & reg_value32) >> 16);
++		} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++			reg_value32 = odm_get_bb_reg(dm, R_0x8a4, MASKDWORD);
++			h2l_diff = (s8)(0x000000ff & reg_value32) -
++				   (s8)((0x0000ff00 & reg_value32) >> 8);
++		}
++
++		if (h2l_diff == 7)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "adaptivity enable\n");
++		else
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "adaptivity disable\n");
++	}
++
++out:
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (val_len != 2) {
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "[Error][adaptivity]Need val_len = 2\n");
++		return;
++	}
++	phydm_set_edcca_threshold(dm, (s8)val_buf[1], (s8)val_buf[0]);
++}
++
++boolean phydm_edcca_abort(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter = dm->adapter;
++	u32 is_fw_in_psmode = false;
++#endif
++
++	if (!(dm->support_ability & ODM_BB_ADAPTIVITY)) {
++		PHYDM_DBG(dm, DBG_ADPTVTY, "adaptivity disable\n");
++		return true;
++	}
++
++	if (dm->pause_ability & ODM_BB_ADAPTIVITY) {
++		PHYDM_DBG(dm, DBG_ADPTVTY, "Return: Pause ADPTVTY in LV=%d\n",
++			  dm->pause_lv_table.lv_adapt);
++		return true;
++	}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	((PADAPTER)adapter)->HalFunc.GetHwRegHandler(adapter,
++						      HW_VAR_FW_PSMODE_STATUS,
++						      (u8 *)(&is_fw_in_psmode));
++
++	/*@Disable EDCCA while under LPS mode, added by Roger, 2012.09.14.*/
++	if (is_fw_in_psmode)
++		return true;
++#endif
++
++	return false;
++}
++
++void phydm_edcca_thre_calc_jgr3(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
++	u8 igi = dig_t->cur_ig_value;
++	s8 th_l2h = 0, th_h2l = 0;
++
++	if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
++		/*prevent pwdB clipping and result in Miss Detection*/
++		adapt->l2h_dyn_min = (u8)(dm->th_l2h_ini - ADC_BACKOFF);
++
++		if (igi < adapt->l2h_dyn_min)
++			th_l2h = igi + ADC_BACKOFF;
++		else
++			th_l2h = dm->th_l2h_ini;
++
++		th_h2l = th_l2h - dm->th_edcca_hl_diff;
++	} else {
++		th_l2h = MAX_2(igi + TH_L2H_DIFF_IGI, EDCCA_TH_L2H_LB);
++		th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
++	}
++	adapt->th_l2h = th_l2h;
++	adapt->th_h2l = th_h2l;
++
++	phydm_set_edcca_threshold(dm, adapt->th_h2l, adapt->th_l2h);
++}
++
++void phydm_edcca_thre_calc(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
++	u8 igi = dig_t->cur_ig_value;
++	s8 th_l2h = 0, th_h2l = 0;
++	s8 diff = 0, igi_target = adapt->igi_base;
++
++	if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) {
++		/*@fix EDCCA hang issue*/
++		if (dm->support_ic_type & ODM_RTL8812) {
++			/*@ADC_mask disable*/
++			odm_set_bb_reg(dm, R_0x800, BIT(10), 1);
++			/*@ADC_mask enable*/
++			odm_set_bb_reg(dm, R_0x800, BIT(10), 0);
++		}
++
++		if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
++			/*@Limit IGI upper bound for adaptivity*/
++			phydm_dig_up_bound_lmt_en(dm);
++			diff = igi_target - (s8)igi;
++			th_l2h = dm->th_l2h_ini + diff;
++			if (th_l2h > 10)
++				th_l2h = 10;
++
++			th_h2l = th_l2h - dm->th_edcca_hl_diff;
++		} else {
++			th_l2h = 70 - igi;
++			th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
++		}
++		/*replace lower bound to prevent EDCCA always equal 1*/
++		if (th_h2l < adapt->h2l_lb)
++			th_h2l = adapt->h2l_lb;
++		if (th_l2h < adapt->l2h_lb)
++			th_l2h = adapt->l2h_lb;
++		PHYDM_DBG(dm, DBG_ADPTVTY,
++			  "adapt_igi_up=0x%x, l2h_lb = %d dBm, h2l_lb = %d dBm\n",
++			  adapt->adapt_igi_up,
++			  IGI_2_DBM(adapt->l2h_lb + adapt->adapt_igi_up),
++			  IGI_2_DBM(adapt->h2l_lb + adapt->adapt_igi_up));
++	} else { /* < JGR2 & N*/
++		if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
++			/*need to consider PwdB upper bound for 8814 later IC*/
++			adapt->l2h_dyn_min = (u8)(dm->th_l2h_ini + igi_target);
++
++			if (igi < adapt->l2h_dyn_min)
++				th_l2h = igi;
++			else
++				th_l2h = adapt->l2h_dyn_min;
++
++			th_h2l = th_l2h - dm->th_edcca_hl_diff;
++		} else {
++			th_l2h = MAX_2(igi + TH_L2H_DIFF_IGI, EDCCA_TH_L2H_LB);
++			th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
++		}
++	}
++
++	adapt->th_l2h = th_l2h;
++	adapt->th_h2l = th_h2l;
++
++	phydm_set_edcca_threshold(dm, adapt->th_h2l, adapt->th_l2h);
++}
++#endif
++
++void phydm_set_edcca_threshold_api(void *dm_void)
++{
++#ifdef PHYDM_SUPPORT_ADAPTIVITY
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
++
++	if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
++		return;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		phydm_edcca_thre_calc_jgr3(dm);
++	else
++		phydm_edcca_thre_calc(dm);
++
++	PHYDM_DBG(dm, DBG_ADPTVTY,
++		  "API :IGI = 0x%x, th_l2h = %d, th_h2l = %d\n",
++		  dm->dm_dig_table.cur_ig_value, adapt->th_l2h, adapt->th_h2l);
++#endif
++}
++
++void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
++				u32 value)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
++
++	switch (cmn_info) {
++	case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:
++		dm->carrier_sense_enable = (boolean)value;
++		break;
++	case PHYDM_ADAPINFO_TH_L2H_INI:
++		dm->th_l2h_ini = (s8)value;
++		break;
++	case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:
++		dm->th_edcca_hl_diff = (s8)value;
++		break;
++	case PHYDM_ADAPINFO_AP_NUM_TH:
++		adaptivity->ap_num_th = (u8)value;
++		break;
++	case PHYDM_ADAPINFO_SWITCH_TH_L2H_INI_IN_BAND:
++		adaptivity->switch_th_l2h_ini_in_band = (u8)value;
++		break;
++	default:
++		break;
++	}
++}
++
++void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info,
++				  u32 value)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
++
++	/*This init variable may be changed in run time.*/
++	switch (cmn_info) {
++	case PHYDM_ADAPINFO_DOMAIN_CODE_2G:
++		adapt->regulation_2g = (u8)value;
++		break;
++	case PHYDM_ADAPINFO_DOMAIN_CODE_5G:
++		adapt->regulation_5g = (u8)value;
++		break;
++	default:
++		break;
++	}
++}
++
++void phydm_adaptivity_init(void *dm_void)
++{
++#ifdef PHYDM_SUPPORT_ADAPTIVITY
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
++
++	/* @[Config Adaptivity]*/
++	if (!dm->edcca_mode) {
++		pr_debug("[%s] warning!\n", __func__);
++		dm->edcca_mode = &dm->u8_dummy;
++		dm->support_ability &= ~ODM_BB_ADAPTIVITY;
++		return;
++	}
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	if (!dm->carrier_sense_enable) {
++		if (dm->th_l2h_ini == 0 &&
++		    !adaptivity->switch_th_l2h_ini_in_band)
++			phydm_set_l2h_th_ini(dm);
++	} else {
++		phydm_set_l2h_th_ini_carrier_sense(dm);
++	}
++
++	if (dm->th_edcca_hl_diff == 0)
++		dm->th_edcca_hl_diff = 7;
++
++	if (dm->wifi_test & RT_WIFI_LOGO)
++		dm->support_ability &= ~ODM_BB_ADAPTIVITY;
++
++	if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE)
++		adaptivity->mode_cvrt_en = true;
++	else
++		adaptivity->mode_cvrt_en = false;
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	if (!dm->carrier_sense_enable) {
++		if (dm->th_l2h_ini == 0)
++			phydm_set_l2h_th_ini(dm);
++	} else {
++		phydm_set_l2h_th_ini_carrier_sense(dm);
++	}
++
++	if (dm->th_edcca_hl_diff == 0)
++		dm->th_edcca_hl_diff = 7;
++
++	if (dm->wifi_test || *dm->mp_mode)
++		dm->support_ability &= ~ODM_BB_ADAPTIVITY;
++#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	if (dm->carrier_sense_enable) {
++		phydm_set_l2h_th_ini_carrier_sense(dm);
++		dm->th_edcca_hl_diff = 7;
++	} else {
++		dm->th_l2h_ini = dm->TH_L2H_default; /*set by mib*/
++		dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_default;
++	}
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	if (!dm->carrier_sense_enable) {
++		if (dm->th_l2h_ini == 0)
++			phydm_set_l2h_th_ini(dm);
++	} else {
++		phydm_set_l2h_th_ini_carrier_sense(dm);
++	}
++
++	if (dm->th_edcca_hl_diff == 0)
++		dm->th_edcca_hl_diff = 7;
++#endif
++
++	adaptivity->debug_mode = false;
++	adaptivity->th_l2h_ini_backup = dm->th_l2h_ini;
++	adaptivity->th_edcca_hl_diff_backup = dm->th_edcca_hl_diff;
++	adaptivity->igi_base = 0x32;
++	adaptivity->adapt_igi_up = 0;
++	adaptivity->h2l_lb = 0;
++	adaptivity->l2h_lb = 0;
++	adaptivity->l2h_dyn_min = 0;
++	adaptivity->th_l2h = 0x7f;
++	adaptivity->th_h2l = 0x7f;
++
++	if (dm->support_ic_type & ODM_IC_11N_SERIES)
++		adaptivity->adaptivity_dbg_port = 0x208;
++	else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
++		adaptivity->adaptivity_dbg_port = 0x209;
++
++	if (dm->support_ic_type & ODM_IC_11N_SERIES &&
++	    !(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
++		if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) {
++			/*set to page B1*/
++			odm_set_bb_reg(dm, R_0xe28, BIT(30), 0x1);
++			/*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
++			odm_set_bb_reg(dm, R_0xbc0, BIT(27) | BIT(26), 0x1);
++			odm_set_bb_reg(dm, R_0xe28, BIT(30), 0x0);
++		} else {
++			/*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
++			odm_set_bb_reg(dm, R_0xe24, BIT(21) | BIT(20), 0x1);
++		}
++	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES &&
++		   !(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
++		/*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
++		odm_set_bb_reg(dm, R_0x944, BIT(29) | BIT(28), 0x1);
++	}
++
++	if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) {
++		phydm_search_pwdb_lower_bound(dm);
++		if (phydm_re_search_condition(dm))
++			phydm_search_pwdb_lower_bound(dm);
++	} else {
++		/*resume to no link state*/
++		phydm_set_edcca_threshold(dm, 0x7f, 0x7f);
++	}
++
++	/*@whether to ignore EDCCA*/
++	phydm_mac_edcca_state(dm, PHYDM_DONT_IGNORE_EDCCA);
++
++	/*@forgetting factor setting*/
++	phydm_set_forgetting_factor(dm);
++
++	/*@EDCCA behavior based on maximum or mean power*/
++	phydm_edcca_decision_opt(dm);
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	adaptivity->igi_up_bound_lmt_val = 180;
++#else
++	adaptivity->igi_up_bound_lmt_val = 90;
++#endif
++	adaptivity->igi_up_bound_lmt_cnt = 0;
++	adaptivity->igi_lmt_en = false;
++#endif
++}
++
++void phydm_adaptivity(void *dm_void)
++{
++#ifdef PHYDM_SUPPORT_ADAPTIVITY
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++
++	if (phydm_edcca_abort(dm))
++		return;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	phydm_check_adaptivity(dm); /*@Check adaptivity enable*/
++
++	if (!dm->carrier_sense_enable &&
++	    !adapt->debug_mode &&
++	    adapt->switch_th_l2h_ini_in_band)
++		phydm_set_l2h_th_ini_win(dm);
++#endif
++
++	PHYDM_DBG(dm, DBG_ADPTVTY, "%s ====>\n", __func__);
++	PHYDM_DBG(dm, DBG_ADPTVTY, "mode = %s, debug_mode = %d\n",
++		  (*dm->edcca_mode ?
++		  (dm->carrier_sense_enable ?
++		  "CARRIER SENSE" :
++		  "ADAPTIVITY") :
++		  "NORMAL"),
++		  adapt->debug_mode);
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		phydm_edcca_thre_calc_jgr3(dm);
++	else
++		phydm_edcca_thre_calc(dm);
++
++	if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE)
++		PHYDM_DBG(dm, DBG_ADPTVTY,
++			  "th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
++			  dm->th_l2h_ini, dm->th_edcca_hl_diff);
++	if (dm->support_ic_type & ODM_IC_PWDB_EDCCA)
++		PHYDM_DBG(dm, DBG_ADPTVTY,
++			  "IGI = 0x%x, th_l2h = %d dBm, th_h2l = %d dBm\n",
++			  dig_t->cur_ig_value,
++			  IGI_2_DBM(adapt->th_l2h + dig_t->cur_ig_value),
++			  IGI_2_DBM(adapt->th_h2l + dig_t->cur_ig_value));
++	else
++		PHYDM_DBG(dm, DBG_ADPTVTY,
++			  "IGI = 0x%x, th_l2h = %d dBm, th_h2l = %d dBm\n",
++			  dig_t->cur_ig_value,
++			  IGI_2_DBM(adapt->th_l2h),
++			  IGI_2_DBM(adapt->th_h2l));
++#endif
++}
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_adaptivity.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_adaptivity.h
+new file mode 100644
+index 000000000..f125fb1f7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_adaptivity.h
+@@ -0,0 +1,126 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDMADAPTIVITY_H__
++#define __PHYDMADAPTIVITY_H__
++
++#define ADAPTIVITY_VERSION "9.7.07" /*@20190321 changed by Kevin,
++				     *add 8721D threshold l2h init
++				     */
++#define ADC_BACKOFF 12
++#define EDCCA_TH_L2H_LB 48
++#define TH_L2H_DIFF_IGI 8
++#define EDCCA_HL_DIFF_NORMAL 8
++#define IGI_2_DBM(igi) (igi - 110)
++/*@ [PHYDM-337][Old IC] EDCCA TH = IGI + REG setting*/
++#define ODM_IC_PWDB_EDCCA (ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |\
++			   ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8812)
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
++	#define ADAPT_DC_BACKOFF 2
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	#define ADAPT_DC_BACKOFF 4
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	#define ADAPT_DC_BACKOFF 0
++#endif
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++enum phydm_regulation_type {
++	REGULATION_FCC		= 0,
++	REGULATION_MKK		= 1,
++	REGULATION_ETSI		= 2,
++	REGULATION_WW		= 3,
++	MAX_REGULATION_NUM	= 4
++};
++#endif
++
++enum phydm_edcca_mode {
++	PHYDM_EDCCA_NORMAL_MODE = 0,
++	PHYDM_EDCCA_ADAPT_MODE = 1
++};
++
++enum phydm_adapinfo {
++	PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
++	PHYDM_ADAPINFO_TH_L2H_INI,
++	PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
++	PHYDM_ADAPINFO_AP_NUM_TH,
++	PHYDM_ADAPINFO_DOMAIN_CODE_2G,
++	PHYDM_ADAPINFO_DOMAIN_CODE_5G,
++	PHYDM_ADAPINFO_SWITCH_TH_L2H_INI_IN_BAND
++};
++
++enum phydm_mac_edcca_type {
++	PHYDM_IGNORE_EDCCA		= 0,
++	PHYDM_DONT_IGNORE_EDCCA		= 1
++};
++
++enum phydm_adaptivity_debug_mode {
++	PHYDM_ADAPT_MSG			= 0,
++	PHYDM_ADAPT_DEBUG		= 1,
++	PHYDM_ADAPT_RESUME		= 2,
++};
++
++struct phydm_adaptivity_struct {
++	boolean			mode_cvrt_en;
++	s8			th_l2h_ini_backup;
++	s8			th_edcca_hl_diff_backup;
++	s8			igi_base;
++	s8			h2l_lb;
++	s8			l2h_lb;
++	u8			ap_num_th;
++	u8			l2h_dyn_min;
++	u32			adaptivity_dbg_port; /*N:0x208, AC:0x209*/
++	u8			debug_mode;
++	u16			igi_up_bound_lmt_cnt;	/*@When igi_up_bound_lmt_cnt !=0, limit IGI upper bound to "adapt_igi_up"*/
++	u16			igi_up_bound_lmt_val;	/*@max value of igi_up_bound_lmt_cnt*/
++	boolean			igi_lmt_en;
++	u8			adapt_igi_up;
++	u32			rvrt_val[2]; /*@all rvrt_val for pause API must set to u32*/
++	s8			th_l2h;
++	s8			th_h2l;
++	u8			regulation_2g;
++	u8			regulation_5g;
++	u8			switch_th_l2h_ini_in_band;
++};
++
++#ifdef PHYDM_SUPPORT_ADAPTIVITY
++void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,
++			    char *output, u32 *_out_len);
++
++void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len);
++#endif
++
++void phydm_set_edcca_threshold_api(void *dm_void);
++
++void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
++				u32 value);
++
++void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info,
++				  u32 value);
++
++void phydm_adaptivity_init(void *dm_void);
++
++void phydm_adaptivity(void *dm_void);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_adc_sampling.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_adc_sampling.c
+new file mode 100644
+index 000000000..186e0e455
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_adc_sampling.c
+@@ -0,0 +1,1597 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#if (PHYDM_LA_MODE_SUPPORT)
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8192F_SUPPORT)
++	#include "rtl8197f/Hal8197FPhyReg.h"
++	#include "WlanHAL/HalMac88XX/halmac_reg2.h"
++	#else
++	#include "WlanHAL/HalHeader/HalComReg.h"
++	#endif
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	#if WPP_SOFTWARE_TRACE
++	#include "phydm_adc_sampling.tmh"
++	#endif
++#endif
++
++#if RTL8814B_SUPPORT
++boolean phydm_la_finish_addr_recover_8814B(void *dm_void, u32 *finish_addr)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	boolean recover_success;
++
++	if (dm->support_ic_type != ODM_RTL8814B)
++		return false;
++
++	if (smp->la_buff_mode == ADCSMP_BUFF_HALF) {
++		if (*finish_addr < 0x4000) /*0~0x4000*/
++			*finish_addr += 0x8000;
++
++		recover_success = true;
++	} else {
++		if (*finish_addr >= 0x4000 && *finish_addr < 0x8000)
++			recover_success = true;
++		else
++			recover_success = false;
++	}
++	pr_debug("[8814B] recover_success=(%d)\n", recover_success);
++
++	return recover_success;
++}
++#endif
++
++#if RTL8198F_SUPPORT
++void phydm_la_pre_run(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
++	u8 i = 0;
++	u8 tmp = 0;
++	u8 target_polling_bit = BIT(1);
++
++	if (!(dm->support_ic_type & ODM_RTL8198F))
++		return;
++
++	if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG)
++		return;
++
++	/*pre run */
++	/*force to bb trigger*/
++	odm_set_mac_reg(dm, R_0x7c0, BIT(3), 0);
++	/*dma_trig_and(AND1) output 1*/
++	odm_set_bb_reg(dm, R_0x1ce4, 0xf0000000, 0x0);
++	/*r_dma_trigger_AND1_inv = 1*/
++	odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/
++	/* polling bit for BB ADC mode */
++	odm_set_mac_reg(dm, R_0x7c0, BIT(1), 1);
++
++	pr_debug("buf[end:start]=(0x%x~0x%x)\n", buf->end_pos, buf->start_pos);
++
++	do {
++		tmp = odm_read_1byte(dm, R_0x7c0);
++		if ((tmp & target_polling_bit) == false) {
++			pr_debug("LA pre-run fail.\n");
++			phydm_la_stop(dm);
++			phydm_release_bb_dbg_port(dm);
++		} else {
++			ODM_delay_ms(100);
++			pr_debug("LA pre-run while_cnt = %d.\n", i);
++			i++;
++		}
++	} while (i < 3);
++
++	/*r_dma_trigger_AND1_inv = 0*/
++	odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/
++
++	if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG)
++		odm_set_mac_reg(dm, R_0x7c0, BIT(3), 1);
++}
++#endif
++
++#if (RTL8821C_SUPPORT || RTL8195B_SUPPORT)
++void
++phydm_la_clk_en(void *dm_void, boolean enable)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 val = (enable) ? 1 : 0;
++
++	if (!(dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)))
++		return;
++
++	if (dm->support_ic_type == ODM_RTL8821C &&
++	    dm->cut_version == ODM_CUT_A)
++		return;
++
++	odm_set_bb_reg(dm, R_0x95c, BIT(23), val);
++}
++#endif
++
++#if (RTL8197F_SUPPORT)
++void
++phydm_la_stop_dma_8197f(void *dm_void, enum phydm_backup_type opt)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++
++	if (dm->support_ic_type != ODM_RTL8197F)
++		return;
++
++	if (opt == PHYDM_BACKUP) {
++		/*Stop DMA*/
++		smp->backup_dma = odm_get_mac_reg(dm, R_0x300, 0xffff);
++		odm_set_mac_reg(dm, R_0x300, 0x7fff, 0x7fff);
++	} else { /*restore*/
++		/*Resume DMA*/
++		odm_set_mac_reg(dm, R_0x300, 0x7fff, smp->backup_dma);
++	}
++}
++#endif
++
++#ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM
++void
++phydm_la_mv_data_2_tx_buffer(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
++
++	if (!(dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC))
++		return;
++
++	pr_debug("GetTxPktBuf from iMEM\n");
++	odm_set_mac_reg(dm, R_0x7c0, BIT(0), 0x0); /*Disable LA mode HW block*/
++
++	/* 98F LA memory loccation is separate from normal
++	 * driver use, DMA is no longer required to stop
++	 */
++	#if (RTL8197F_SUPPORT)
++	phydm_la_stop_dma_8197f(dm, PHYDM_BACKUP);
++	#endif
++
++	/* @move LA mode content from IMEM to TxPktBuffer
++	 * Source : OCPBASE_IMEM 0x00000000
++	 * Destination : OCPBASE_TXBUF 0x18780000
++	 * Length : 64K
++	 */
++	GET_HAL_INTERFACE(dm->priv)->init_ddma_handler(dm->priv,
++						       OCPBASE_IMEM,
++						       OCPBASE_TXBUF
++						       + buf->start_pos,
++						       0x10000);
++}
++#endif
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++
++void phydm_la_bb_adv_reset_jgr3(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	struct la_adv_trig *adv = &smp->adv_trig_table;
++
++	odm_memory_set(dm, adv, 0, sizeof(struct la_adv_trig));
++
++}
++
++void phydm_la_bb_adv_trig_setting_jgr3(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	struct la_adv_trig *adv = &smp->adv_trig_table;
++
++	pr_debug(" *ADV BB-trig = %d\n", adv->la_adv_bbtrigger_en);
++
++	if (!adv->la_adv_bbtrigger_en) { /*normal LA mode & back to default*/
++		/*@AND0*/
++		odm_set_bb_reg(dm, R_0x1ce4, BIT(27), 0);
++
++		/*@AND1*/
++		odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, 0);
++		odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/
++		/*@AND2*/
++		odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0);
++		odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/
++		/*@AND3*/
++		odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0);
++		odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/
++		/*@AND4*/
++		odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, 0); /*@AND 4 mask en*/
++		odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/
++	} else {
++		/*@AND0 */
++		/*path 1 default: enable ori. BB trigger*/
++		odm_set_bb_reg(dm, R_0x1ce4, BIT(27),
++			       (adv->la_ori_bb_dis ? 1 : 0));
++
++		/* @AND1 */
++		odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv);
++		odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, adv->la_and1_sel);
++		odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val);
++
++		/*@AND2 */
++		odm_set_bb_reg(dm, R_0x1ce8, BIT(15), adv->la_and2_inv);
++		odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, adv->la_and2_sel);
++		odm_set_bb_reg(dm, R_0x1ce8, 0x7c00, adv->la_and2_val);
++
++		/*@AND3 */
++		odm_set_bb_reg(dm, R_0x1ce8, BIT(25), adv->la_and3_inv);
++		odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, adv->la_and3_sel);
++		odm_set_bb_reg(dm, R_0x1ce8, 0x1f00000, adv->la_and3_val);
++
++		/*@AND4 */
++		odm_set_bb_reg(dm, R_0x1ce8, BIT(26), adv->la_and4_inv);
++		odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, adv->la_and4_mask);
++		odm_set_bb_reg(dm, R_0x1cec, MASKDWORD, adv->la_and4_bitmap);
++	}
++}
++
++void phydm_la_bb_adv_cmd_show_jgr3(void *dm_void, u32 *_used,
++				   char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	struct la_adv_trig *adv = &smp->adv_trig_table;
++
++	PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++		 "  *And0 Disable=%d\n", adv->la_ori_bb_dis);
++	PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++		 "  *And1{sel,val,inv}={0x%x,0x%x,%d}\n  *And2{sel,val,inv}={0x%x,0x%x,%d}\n  *And3{sel,val,inv}={0x%x,0x%x,%d}\n",
++		 adv->la_and1_sel, adv->la_and1_val, adv->la_and1_inv,
++		 adv->la_and2_sel, adv->la_and2_val, adv->la_and2_inv,
++		 adv->la_and3_sel, adv->la_and3_val, adv->la_and3_inv);
++	PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++		 "  *And4{mask,bitmap,inv}={0x%x,0x%x,%d}\n",
++		 adv->la_and4_mask, adv->la_and4_bitmap, adv->la_and4_inv);
++}
++
++void phydm_la_bb_adv_cmd_jgr3(void *dm_void, char input[][16], u32 *_used,
++			      char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	struct la_adv_trig *adv = &smp->adv_trig_table;
++	u32 var1[10] = {0};
++	u32 adv_trig_en;
++
++	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
++		return;
++
++	if ((strcmp(input[2], "show") == 0)) {
++		phydm_la_bb_adv_cmd_show_jgr3(dm, _used, output, _out_len);
++		return;
++	}
++
++	PHYDM_SSCANF(input[2], DCMD_HEX, &var1[0]);
++	PHYDM_SSCANF(input[3], DCMD_HEX, &var1[1]);
++	PHYDM_SSCANF(input[4], DCMD_HEX, &var1[2]);
++	PHYDM_SSCANF(input[5], DCMD_HEX, &var1[3]);
++	PHYDM_SSCANF(input[6], DCMD_HEX, &var1[4]);
++
++	adv_trig_en = var1[0];
++
++	if (adv_trig_en != 1) {
++		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++			 "Back to Ori-BB-trig\n");
++		phydm_la_bb_adv_reset_jgr3(dm);
++		return;
++	}
++
++	adv->la_adv_bbtrigger_en = true;
++
++	if (var1[1] == 0) {
++		adv->la_ori_bb_dis = (boolean)var1[2];
++	} else if (var1[1] == 1) {
++		adv->la_and1_sel = (u8)var1[2];
++		adv->la_and1_val = (u8)var1[3];
++		adv->la_and1_inv = (boolean)var1[4];
++	} else if (var1[1] == 2) {
++		adv->la_and2_sel = (u8)var1[2];
++		adv->la_and2_val = (u8)var1[3];
++		adv->la_and2_inv = (boolean)var1[4];
++	} else if (var1[1] == 3) {
++		adv->la_and3_sel = (u8)var1[2];
++		adv->la_and3_val = (u8)var1[3];
++		adv->la_and2_inv = (boolean)var1[4];
++	}  else if (var1[1] == 4) {
++		adv->la_and4_mask = var1[2];
++		adv->la_and4_bitmap = var1[3];
++		adv->la_and4_inv = (boolean)var1[4];
++	}
++
++	PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++		 "[Adv_trig_en=%d]\n\n", adv_trig_en);
++
++	phydm_la_bb_adv_cmd_show_jgr3(dm, _used, output, _out_len);
++}
++
++void phydm_la_cmd_fast_jgr3(void *dm_void, char input[][16], u32 *_used,
++			    char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	struct la_adv_trig *adv = &smp->adv_trig_table;
++	enum auto_detection_state ad_mode;
++	const u8 ofdm_codeword[8] = {0xb, 0xf, 0xa, 0xe, 0x9, 0xd, 0x8, 0xc};
++	u32 codeword;
++	u8 rate_idx;
++	u32 trig_time_cca = 0;
++	s32 val_sign32_tmp = 0;
++	u32 var[10] = {0};
++	u8 bw = *dm->band_width;
++
++	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) {
++		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++			 "Only Support for JGR-3 ICs\n");
++		return;
++	}
++
++	if (bw > 2) {
++		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++			 "Not Support for BW > %dM\n", 20 << bw);
++		return;
++	}
++
++	PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var[0]);
++	PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var[1]);
++	PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var[2]);
++
++	trig_time_cca = ((smp->smp_number_max >> (bw + 1)) / 10)
++			- (2 << (2 - bw)) - (2 - bw);
++
++	if (var[0] < 10) {
++	/*=== [Type: 0 ~ 10] : CCA P-edge trigger ==========================*/
++		/*--- Basic Trigger Setting --------------------------------*/
++		smp->la_trig_mode = 1;
++		smp->la_trig_sig_sel = 2;
++		smp->la_trigger_time = trig_time_cca;
++		smp->la_mac_mask_or_hdr_sel = 0;
++		smp->la_trigger_edge = 0;
++		smp->la_smp_rate = 2 - bw;
++		smp->la_count = 0;
++		if (var[0] == 0) { /*AGC*/
++			smp->la_dma_type = 5;
++			smp->la_dbg_port = 0x870;
++		} else if (var[0] == 1) { /*EVM*/
++			smp->la_dma_type = 4;
++			smp->la_dbg_port = 0x392;
++		} else if (var[0] == 2) { /*SNR*/
++			smp->la_dma_type = 4;
++			if (var[1] == 0)
++				smp->la_dbg_port = 0x89e;
++			else
++				smp->la_dbg_port = 0xa9e;
++		} else if (var[0] == 3) { /*CFO*/
++			smp->la_dma_type = 4;
++			if (var[1] == 0)
++				smp->la_dbg_port = 0x88c;
++			else
++				smp->la_dbg_port = 0xa8c;
++		}  else if (var[0] == 4) { /*ADC*/
++			if (var[1] == 0) {
++				smp->la_dma_type = 0;
++				smp->la_dbg_port = 0x880;
++			} else {
++				smp->la_dma_type = 1;
++				smp->la_dbg_port = 0xa80;
++			}
++		}
++		/*--- Adv-Trigger Setting------------------------------------*/
++		adv->la_adv_bbtrigger_en = false;
++	} else if (var[0] < 20) {
++	/*=== [Type: 10 ~ 19]: RX-EVM Trigger ===============================*/
++		/*--- Basic Trigger Setting ---------------------------------*/
++		smp->la_trig_mode = 0;
++		smp->la_trig_sig_sel = 0;
++		smp->la_mac_mask_or_hdr_sel = 0;
++		smp->la_trigger_edge = 0;
++		smp->la_smp_rate = 2 - bw;
++		smp->la_count = 0;
++		smp->la_dma_type = 4;
++		smp->la_dbg_port = 0x392;
++
++		/*--- Adv-Trigger Setting -----------------------------------*/
++		phydm_la_bb_adv_reset_jgr3(dm);
++		adv->la_adv_bbtrigger_en = true;
++
++		/*And[0]*/
++		adv->la_ori_bb_dis = true;
++
++		/*And[1]*/
++		adv->la_and1_inv = 0;
++		adv->la_and1_sel = 4; /*RX-state*/
++		if (var[2] == 0) {
++			/*L-preamble 8+8+4 = 20*/
++			smp->la_trigger_time = trig_time_cca - 20;
++			/*Legacy Data*/
++			adv->la_and1_val = 5;
++		} else if (var[2] == 1) {
++			/*HT-preamble (8+8+4) + (8+4+4*Nrx) = 32 + Nrx * 4*/
++			smp->la_trigger_time = trig_time_cca - 32 -
++					       (dm->num_rf_path * 4);
++			/*HT Data*/
++			adv->la_and1_val = 18;
++		} else {
++			/*VHT-preamble (8+8+4) + (8+4+4*Nrx) +4 = 36 + Nrx * 4*/
++			smp->la_trigger_time = trig_time_cca - 36 -
++					       (dm->num_rf_path * 4);
++			/*VHT Data*/
++			adv->la_and1_val = 18;
++		}
++
++		/*And[2]*/
++		adv->la_and2_inv = 0;
++		adv->la_and2_sel = 0; /*Disable*/
++
++		/*And[3]*/
++		adv->la_and2_inv = 0;
++		adv->la_and3_sel = 0; /*Disable*/
++
++		/*And[4]*/
++		adv->la_and4_inv = 0;
++
++		if (var[0] == 11) {
++			/*[>= -X dB]*/
++			if (var[1] == 2) {
++				adv->la_and4_bitmap = 0;
++				adv->la_and4_mask = 0x1;
++			} else if (var[1] == 4) {
++				adv->la_and4_bitmap = 0;
++				adv->la_and4_mask = 0x3;
++			} else if (var[1] == 8) {
++				adv->la_and4_bitmap = 0;
++				adv->la_and4_mask = 0x7;
++			} else if (var[1] == 16) {
++				adv->la_and4_bitmap = 0;
++				adv->la_and4_mask = 0xf;
++			} else if (var[1] == 32) {
++				adv->la_and4_bitmap = 0;
++				adv->la_and4_mask = 0x1f;
++			} else if (var[1] == 64) {
++				adv->la_and4_bitmap = 0;
++				adv->la_and4_mask = 0x3f;
++			} else {
++				PDM_SNPF(*_out_len, *_used, output + *_used,
++					 *_out_len - *_used,
++					 "Not Support >= -%d dB\n", var[1]);
++				return;
++			}
++		} else if (var[0] == 10) {
++			/*[<= -X dB]*/
++			if (var[1] == 2) {
++				adv->la_and4_bitmap = 0x7e;
++				adv->la_and4_mask = 0x7e;
++			} else if (var[1] == 4) {
++				adv->la_and4_bitmap = 0x7c;
++				adv->la_and4_mask = 0x7c;
++			} else if (var[1] == 8) {
++				adv->la_and4_bitmap = 0x78;
++				adv->la_and4_mask = 0x78;
++			} else if (var[1] == 16) {
++				adv->la_and4_bitmap = 0x70;
++				adv->la_and4_mask = 0x70;
++			} else if (var[1] == 32) {
++				adv->la_and4_bitmap = 0x60;
++				adv->la_and4_mask = 0x60;
++			} else if (var[1] == 64) {
++				adv->la_and4_bitmap = 0x40;
++				adv->la_and4_mask = 0x40;
++			} else {
++				PDM_SNPF(*_out_len, *_used, output + *_used,
++					 *_out_len - *_used,
++					 "Not Support <= -%d dB\n", var[1]);
++				return;
++			}
++		} else if (var[0] == 12) {
++			/*[= -X dB]*/
++			val_sign32_tmp = 0 - (s32)var[1];
++			adv->la_and4_bitmap = (u32)(val_sign32_tmp & 0x7f);
++			adv->la_and4_mask = 0x7f;
++		}
++	} else if (var[0] < 30) {
++	/*=== [Type: 20 ~ 29]: RX-Rate Trigger ==============================*/
++		/*--- Basic Trigger Setting ---------------------------------*/
++		smp->la_trig_mode = 0;
++		smp->la_trig_sig_sel = 0;
++		smp->la_mac_mask_or_hdr_sel = 0;
++		smp->la_trigger_edge = 0;
++		smp->la_smp_rate = 2 - bw;
++		smp->la_count = 0;
++		smp->la_dma_type = 4;
++
++		rate_idx = (u8)var[1];
++
++		/*--- Adv-Trigger Setting -----------------------------------*/
++		phydm_la_bb_adv_reset_jgr3(dm);
++		adv->la_adv_bbtrigger_en = true;
++
++		/*And[0]*/
++		adv->la_ori_bb_dis = true;
++
++		/*And[1]*/
++		adv->la_and1_inv = 0;
++		adv->la_and1_sel = 4; /*RX-state*/
++
++		if (rate_idx <= ODM_RATE54M && rate_idx >= ODM_RATE6M) {
++			ad_mode = AD_LEGACY_MODE;
++			codeword = (u32)ofdm_codeword[rate_idx - ODM_RATE6M];
++			smp->la_dbg_port = 0x3a9;
++			/*L-preamble 8+8 = 16*/
++			smp->la_trigger_time = trig_time_cca - 20;
++			/*Legacy Data*/
++			adv->la_and1_val = 5;
++		} else if (rate_idx <= ODM_RATEMCS31) {
++			ad_mode = AD_HT_MODE;
++			codeword = (u32)(rate_idx - ODM_RATEMCS0);
++			smp->la_dbg_port = 0x3aa;
++			/*HT-preamble (8+8+4) + (8+4+4*Nrx) = 32 + Nrx * 4*/
++			smp->la_trigger_time = trig_time_cca - 32 -
++					       (dm->num_rf_path * 4);
++			/*HT,VHT Data*/
++			adv->la_and1_val = 18;
++		} else if (rate_idx <= ODM_RATEVHTSS4MCS9) {
++			ad_mode = AD_VHT_MODE;
++			codeword = (u32)phydm_rate_order_compute(dm, rate_idx);
++			codeword--;
++			smp->la_dbg_port = 0x3ab;
++			/*VHT-preamble (8+8+4) + (8+4+4*Nrx) = 36 + Nrx * 4*/
++			smp->la_trigger_time = trig_time_cca - 36 -
++					       (dm->num_rf_path * 4);
++			/*HT,VHT Data*/
++			adv->la_and1_val = 18;
++		} else {
++			PDM_SNPF(*_out_len, *_used, output + *_used,
++				 *_out_len - *_used,
++				 "Not Support\n");
++			return;
++		}
++
++		/*And[2]*/
++		adv->la_and2_inv = 0;
++		adv->la_and2_sel = 0; /*Disable*/
++
++		/*And[3]*/
++		adv->la_and2_inv = 0;
++		adv->la_and3_sel = 0; /*Disable*/
++
++		/*And[4]*/
++		adv->la_and4_inv = 0;
++
++		if (var[0] == 20) {
++			if (ad_mode == AD_LEGACY_MODE) {
++				adv->la_and4_bitmap = codeword;
++				adv->la_and4_mask = 0x3000000f;
++			} else if (ad_mode == AD_HT_MODE) {
++				adv->la_and4_bitmap = (2 << 28) | codeword;
++				adv->la_and4_mask = 0x3000003f;
++			}  else { /* AD_VHT_MODE*/
++				adv->la_and4_bitmap = (1 << 28) |
++						      (codeword << 4);
++				adv->la_and4_mask = 0x300000f0;
++			}
++		} else {
++			PDM_SNPF(*_out_len, *_used, output + *_used,
++				 *_out_len - *_used,
++				 "Not Support\n");
++			return;
++		}
++	} else {
++		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++			 "Not Support\n");
++		return;
++	}
++	PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++		 "[Basic-Trigger]\n");
++	PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++		 "  *echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n",
++		 smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type,
++		 smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel,
++		 smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate,
++		 smp->la_count);
++	pr_debug("echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n",
++		 smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type,
++		 smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel,
++		 smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate,
++		 smp->la_count);
++
++	if (adv->la_adv_bbtrigger_en) {
++		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++			 "[Adv-Trigger]\n");
++		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++			 "  *And0 Disable=%d\n", adv->la_ori_bb_dis);
++		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++			 "  *And1{sel,val,inv}={0x%x,0x%x,%d}\n  *And2{sel,val,inv}={0x%x,0x%x,%d}\n  *And3{sel,val,inv}={0x%x,0x%x,%d}\n",
++			 adv->la_and1_sel, adv->la_and1_val, adv->la_and1_inv,
++			 adv->la_and2_sel, adv->la_and2_val, adv->la_and2_inv,
++			 adv->la_and3_sel, adv->la_and3_val, adv->la_and3_inv);
++		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++			 "  *And4{mask,bitmap,inv}={0x%x,0x%x,%d}\n",
++			 adv->la_and4_mask, adv->la_and4_bitmap,
++			 adv->la_and4_inv);
++	}
++	phydm_la_set(dm);
++}
++
++#endif
++
++void
++phydm_la_buffer_print(void *dm_void, char input[][16], u32 *_used,
++		      char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
++	u64 la_pattern_msb, la_pattern_lsb;
++	u64 la_pattern, la_pattern_part;
++	s64 tmp_s64;
++	u64 mask = 0xffffffff;
++	u8 mask_length = 0;
++	u32 i;
++	u32 idx;
++	u32 var[10] = {0};
++
++	if (!buf->octet || buf->length == 0 || buf->length < smp->smp_number)
++		return;
++
++	PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var[0]);
++	PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var[1]);
++	PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var[2]);
++	PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var[3]);
++
++	pr_debug("echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n",
++		 smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type,
++		 smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel,
++		 smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate,
++		 smp->la_count);
++	pr_debug("[LA Data Dump] smp_number = %d\n", smp->smp_number);
++	pr_debug("Dump_Start\n");
++
++	if (var[0] == 0) {
++		for (i = 0; i < smp->smp_number; i++) {
++			idx = i << 1;
++			pr_debug("%08x%08x\n", buf->octet[idx],
++				 buf->octet[idx + 1]);
++		}
++	} else if (var[0] == 1) {
++		/*------------------------*/
++		if (var[1] == 0)
++			pr_debug("[Hex]\n");
++		else if (var[1] == 1)
++			pr_debug("[Dec unsigned]\n");
++		else if (var[1] == 2)
++			pr_debug("[Dec signed]\n");
++
++		pr_debug("BIT[%d:%d]\n", var[3], var[2]);
++
++		if (var[2] > var[3]) {
++			pr_debug("[Warning] BIT_L > BIT_H\n");
++			return;
++		}
++
++		mask_length = (u8)(var[3] - var[2] + 1);
++		mask = phydm_gen_bitmask(mask_length) << var[2];
++		/*------------------------*/
++		for (i = 0; i < smp->smp_number; i++) {
++			idx = i << 1;
++			la_pattern_msb = (u64)buf->octet[idx];
++			la_pattern_lsb = (u64)buf->octet[idx + 1];
++			la_pattern = (la_pattern_msb << 32) | la_pattern_lsb;
++			la_pattern_part = (la_pattern & mask) >> var[2];
++
++			if (var[1] == 0) {
++				pr_debug("0x%llx\n", la_pattern_part);
++			} else if (var[1] == 1) {
++				pr_debug("%llu\n", la_pattern_part);
++			} else if (var[1] == 2) {
++				tmp_s64 = phydm_cnvrt_2_sign_64(la_pattern_part,
++								mask_length);
++				pr_debug("%lld\n", tmp_s64);
++			}
++		}
++	}
++	pr_debug("Dump_End\n\n");
++}
++
++void
++phydm_la_buffer_release(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
++
++	if (buf->length != 0x0) {
++		odm_free_memory(dm, buf->octet, buf->length);
++		buf->length = 0x0;
++	}
++}
++
++boolean
++phydm_la_buffer_allocate(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	#endif
++	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
++	boolean ret = true;
++
++	pr_debug("[LA mode BufferAllocate]\n");
++
++	if (buf->length == 0) {
++	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++		if (PlatformAllocateMemoryWithZero(adapter, (void **)&
++						   buf->octet,
++						   buf->buffer_size) !=
++						   RT_STATUS_SUCCESS)
++			ret = false;
++	#else
++		odm_allocate_memory(dm, (void **)&buf->octet, buf->buffer_size);
++
++		if (!buf->octet)
++			ret = false;
++	#endif
++
++		if (ret)
++			buf->length = buf->buffer_size;
++	}
++
++	return ret;
++}
++
++void phydm_la_access_tx_pkt_buf(void *dm_void, u32 addr, u32 buff_idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
++	u32 page;
++	u32 data_l = 0, data_h = 0;
++
++	#if (RTL8192F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8192F) {
++		#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++		indirect_access_sdram_8192f(dm->adapter, TX_PACKET_BUFFER,
++					    TRUE, (u16)addr >> 3, 0,
++					    &data_h, &data_l);
++		#else
++		odm_write_1byte(dm, R_0x0106, 0x69);
++		odm_set_mac_reg(dm, R_0x0140, MASKDWORD, addr >> 3);
++		data_l = odm_get_mac_reg(dm, R_0x0144, MASKDWORD);
++		data_h = odm_get_mac_reg(dm, R_0x0148, MASKDWORD);
++		odm_write_1byte(dm, R_0x0106, 0x0);
++		#endif
++	} else
++	#endif
++	{
++		/* Reg140=0x780+(addr>>12),
++		 * addr=0x30~0x3F, total 16 pages
++		 */
++		page = addr >> 12;
++
++		if (page != smp->txff_page) {
++			smp->txff_page = page;
++			odm_set_mac_reg(dm, R_0x0140, MASKLWORD, 0x780 + page);
++		}
++		data_l = odm_read_4byte(dm, R_0x8000 + (addr & 0xfff));
++		data_h = odm_read_4byte(dm, R_0x8000 + (addr & 0xfff) + 4);
++	}
++
++	buf->octet[buff_idx] = data_h;
++	buf->octet[buff_idx + 1] = data_l;
++
++	/*@==== [Print LA Patterns] ==========================================*/
++	if (smp->is_la_print)
++		pr_debug("%08x%08x\n", data_h, data_l);
++}
++
++void phydm_la_get_tx_pkt_buf(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
++	u32 i = 0, value32 = 0;
++	u32 addr = 0, finish_addr = 0; /* @(unit: 8Byte)*/
++	boolean is_round_up = false;
++	u32 addr_8byte = 0;
++	u32 round_up_point = 0;
++	#if (RTL8814B_SUPPORT)
++	boolean recover_success = true;
++	#endif
++
++	odm_memory_set(dm, buf->octet, 0, buf->length);
++	pr_debug("GetTxPktBuf\n");
++
++	/*@==== [Get LA Report] ==============================================*/
++	if (dm->support_ic_type & ODM_RTL8192F) {
++		value32 = odm_read_4byte(dm, R_0x7f0);
++		is_round_up = (boolean)((value32 & BIT(31)) >> 31);
++		finish_addr = (value32 & 0x7FFF8000) >> 15; /*@16 bit (unit: 8Byte)*/
++	} else {
++		odm_write_1byte(dm, R_0x0106, 0x69);
++		value32 = odm_read_4byte(dm, R_0x7c0);
++		is_round_up = (boolean)((value32 & BIT(31)) >> 31);
++
++		if (dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC)
++			finish_addr = (value32 & 0x7FFF8000) >> 15; /*@16 bit (unit: 8Byte)*/
++		else
++			finish_addr = (value32 & 0x7FFF0000) >> 16; /*@15bit (unit: 8Byte)*/
++	}
++
++	#if (RTL8814B_SUPPORT)
++	recover_success = phydm_la_finish_addr_recover_8814B(dm, &finish_addr);
++	#endif
++
++	pr_debug("start_addr = ((0x%x)), end_addr = ((0x%x)), buffer_size = ((0x%x))\n",
++		 buf->start_pos, buf->end_pos, buf->buffer_size);
++	if (is_round_up) {
++		pr_debug("buf_start(0x%x)|----2---->|finish_addr(0x%x)|----1---->|buf_end(0x%x)\n",
++			 buf->start_pos, finish_addr << 3, buf->end_pos);
++		addr = (finish_addr + 2) << 3; /*+1 or +2 ??*/
++		round_up_point = (buf->end_pos - addr) >> 3; /*@Byte to 8Byte*/
++		smp->smp_number = smp->smp_number_max;
++		pr_debug("is_round_up=(%d), round_up_point=(%d), 0x7c0/0x7F0=(0x%x), smp_number=(%d)\n",
++			 is_round_up, round_up_point, value32, smp->smp_number);
++	} else {
++		pr_debug("buf_start(0x%x)|------->|finish_addr(0x%x)             |buf_end(0x%x)\n",
++			 buf->start_pos, finish_addr << 3, buf->end_pos);
++		addr = buf->start_pos;
++		addr_8byte = addr >> 3;
++		smp->smp_number = DIFF_2(addr_8byte, finish_addr);
++
++		pr_debug("is_round_up=(%d), smp_number=(%d)\n",
++			 is_round_up, smp->smp_number);
++	}
++
++	/*@==== [Get LA Patterns in TXFF] ====================================*/
++	pr_debug("Dump_Start\n");
++	#ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM
++	phydm_la_mv_data_2_tx_buffer(dm);
++	#endif
++
++	#if (RTL8814B_SUPPORT)
++	if ((dm->support_ic_type & ODM_RTL8814B) && !recover_success) {
++		addr = buf->start_pos;
++		smp->smp_number = smp->smp_number_max;
++	}
++	#endif
++
++	for (i = 0; i < smp->smp_number; i++) {
++		phydm_la_access_tx_pkt_buf(dm, addr, i << 1);
++		addr += 8;
++
++		if (addr >= buf->end_pos)
++			addr = buf->start_pos; /*Ring buffer*/
++	}
++
++	#if (RTL8197F_SUPPORT)
++	phydm_la_stop_dma_8197f(dm, PHYDM_RESTORE);
++	#endif
++	pr_debug("Dump_End\n");
++}
++
++void phydm_la_set_trig_src(void *dm_void, u8 la_trig_mode)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 reg = (dm->support_ic_type == ODM_RTL8192F) ? R_0x7f0 : R_0x7c0;
++
++	if (la_trig_mode == PHYDM_ADC_MAC_TRIG)
++		odm_set_mac_reg(dm, reg, BIT(3), 1);
++	else
++		odm_set_mac_reg(dm, reg, BIT(3), 0);
++}
++
++void phydm_la_set_mac_iq_dump(void *dm_void, boolean impossible_trig_condi)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	u32 reg_value = 0;
++	u32 reg1 = 0, reg2 = 0, reg3 = 0;
++
++	if (dm->support_ic_type & ODM_RTL8192F) {
++		reg1 = R_0x7f0;
++		reg2 = R_0x7f4;
++		reg3 = R_0x7f8;
++	} else {
++		reg1 = R_0x7c0;
++		reg2 = R_0x7c4;
++		reg3 = R_0x7c8;
++	}
++
++	odm_write_1byte(dm, reg1, 0); /*@clear all reg1*/
++	/*@Enable LA mode HW block*/
++	odm_set_mac_reg(dm, reg1, BIT(0), 1);
++
++	if (smp->la_trig_mode == PHYDM_MAC_TRIG) {
++		smp->la_dump_mode = LA_MAC_DBG_DUMP;
++		/*polling bit for MAC mode*/
++		odm_set_mac_reg(dm, reg1, BIT(2), 1);
++		/*trigger mode for MAC*/
++		odm_set_mac_reg(dm, reg1, 0x18,	smp->la_trigger_edge);
++		pr_debug("[MAC_trig] ref_mask=(0x%x), ref_value=(0x%x), dbg_port =(0x%x)\n",
++			 smp->la_mac_mask_or_hdr_sel, smp->la_trig_sig_sel,
++			 smp->la_dbg_port);
++		/*@[Set MAC Debug Port]*/
++		odm_set_mac_reg(dm, R_0xf4, BIT(16), 1);
++		odm_set_mac_reg(dm, R_0x38, 0xff0000, smp->la_dbg_port);
++		odm_set_mac_reg(dm, reg2, MASKDWORD,
++				smp->la_mac_mask_or_hdr_sel);
++		odm_set_mac_reg(dm, reg3, MASKDWORD, smp->la_trig_sig_sel);
++	} else {
++		smp->la_dump_mode = LA_BB_ADC_DUMP;
++
++		if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
++			/*polling bit for MAC trigger event*/
++			if (impossible_trig_condi)
++				phydm_la_set_trig_src(dm, PHYDM_ADC_BB_TRIG);
++			else
++				phydm_la_set_trig_src(dm, PHYDM_ADC_MAC_TRIG);
++
++			odm_set_mac_reg(dm, reg1, 0xc0,	smp->la_trig_sig_sel);
++
++			if (smp->la_trig_sig_sel == ADCSMP_TRIG_REG) {
++				/* @manual trigger reg1[5] = 0->1*/
++				odm_set_mac_reg(dm, reg1, BIT(5), 1);
++			}
++		}
++		/*polling bit for BB ADC mode*/
++		odm_set_mac_reg(dm, reg1, BIT(1), 1);
++	}
++
++	reg_value = odm_get_mac_reg(dm, reg1, 0xff);
++	pr_debug("4. [Set MAC IQ dump] 0x%x[7:0]=(0x%x)\n", reg1, reg_value);
++
++	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
++		    ("4. [Set MAC IQ dump] 0x%x[7:0]=(0x%x)\n", reg1,
++		    reg_value));
++	#endif
++}
++
++void phydm_la_set_bb_dbg_port(void *dm_void, boolean impossible_trig_condi)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++
++	u8	trig_mode = smp->la_trig_mode;
++	u32	trig_sel = smp->la_trig_sig_sel;
++	u32	dbg_port = smp->la_dbg_port;
++
++	if (trig_mode == PHYDM_MAC_TRIG)
++		trig_sel = 0; /*@ignore this setting*/
++
++	/*set BB debug port*/
++	if (impossible_trig_condi) {
++		dbg_port = 0xf;
++		trig_sel = 0;
++		pr_debug("[BB Setting] fake-trigger!\n");
++	}
++
++	if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port)) {
++		pr_debug(" *Set dbg_port=(0x%x)\n", dbg_port);
++	} else {
++		dbg_port = phydm_get_bb_dbg_port_idx(dm);
++		pr_debug("[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port);
++	}
++
++	/*@debug port bit*/
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		odm_set_bb_reg(dm, R_0x95c, 0x1f, trig_sel);
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, trig_sel);
++	#endif
++	} else {
++		odm_set_bb_reg(dm, R_0x9a0, 0x1f, trig_sel);
++	}
++
++	if (smp->la_trig_mode == PHYDM_ADC_BB_TRIG) {
++		pr_debug(" *Set dbg_port[BIT] = %d\n", trig_sel);
++
++		#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++		RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
++			    (" *Set dbg_port[BIT] = %d\n", trig_sel));
++		#endif
++	}
++}
++
++void phydm_la_set_bb(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++
++	u8	trig_mode = smp->la_trig_mode;
++	u8	edge = smp->la_trigger_edge;
++	u8	smp_rate = smp->la_smp_rate;
++	u8	dma_type = smp->la_dma_type;
++	u32	dbg_port_hdr_sel = 0;
++	char	*trig_mode_word = NULL;
++
++	pr_debug("3. [BB Setting] mode=(%d), Edge=(%s), smp_rate=(%dM), Dma_type=(%d)\n",
++		 trig_mode,
++		 (edge == 0) ? "P" : "N", 80 >> smp_rate, dma_type);
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		if (trig_mode == PHYDM_ADC_RF0_TRIG)
++			dbg_port_hdr_sel = 9; /*@DBGOUT_RFC_a[31:0]*/
++		else if (trig_mode == PHYDM_ADC_RF1_TRIG)
++			dbg_port_hdr_sel = 8; /*@DBGOUT_RFC_b[31:0]*/
++		else if ((trig_mode == PHYDM_ADC_BB_TRIG) ||
++			 (trig_mode == PHYDM_ADC_MAC_TRIG)) {
++			if (smp->la_mac_mask_or_hdr_sel <= 0xf)
++				dbg_port_hdr_sel = smp->la_mac_mask_or_hdr_sel;
++			else
++				dbg_port_hdr_sel = 0;
++		}
++
++		phydm_bb_dbg_port_header_sel(dm, dbg_port_hdr_sel);
++
++		odm_set_bb_reg(dm, R_0x8b4, BIT(7), 1);/*@update rpt every pkt*/
++		odm_set_bb_reg(dm, R_0x95c, 0xf00, dma_type);
++		/*@0: posedge, 1: negedge*/
++		odm_set_bb_reg(dm, R_0x95c, BIT(31), edge);
++		odm_set_bb_reg(dm, R_0x95c, 0xe0, smp_rate);
++		/*	@(0:) '80MHz'
++		 *	(1:) '40MHz'
++		 *	(2:) '20MHz'
++		 *	(3:) '10MHz'
++		 *	(4:) '5MHz'
++		 *	(5:) '2.5MHz'
++		 *	(6:) '1.25MHz'
++		 *	(7:) '160MHz (for BW160 ic)'
++		 */
++		#if (RTL8821C_SUPPORT || RTL8195B_SUPPORT)
++		phydm_la_clk_en(dm, true);
++		#endif
++
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		odm_set_bb_reg(dm, R_0x1eb4, BIT(23), 0x1);/*@update rpt every pkt*/
++		/*@MAC-PHY timing*/
++		odm_set_bb_reg(dm, R_0x1ce4, BIT(7) | BIT(6), 0);
++		odm_set_bb_reg(dm, R_0x1cf4, BIT(23), 1); /*@LA mode on*/
++		odm_set_bb_reg(dm, R_0x1ce4, 0x3f, dma_type);
++		/*@0: posedge, 1: negedge ??*/
++		odm_set_bb_reg(dm, R_0x1ce4, BIT(26), edge);
++		odm_set_bb_reg(dm, R_0x1ce4, 0x700, smp_rate);
++
++		phydm_la_bb_adv_trig_setting_jgr3(dm);
++	#endif
++	} else {
++		if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
++			odm_set_bb_reg(dm, R_0xd00, BIT(26), 0x1); /*@update rpt every pkt*/
++
++		#if (RTL8192F_SUPPORT)
++		if ((dm->support_ic_type & ODM_RTL8192F))
++			/*@LA reset HW block enable for true-mac asic*/
++			odm_set_bb_reg(dm, R_0x9a0, BIT(15), 1);
++		#endif
++
++		odm_set_bb_reg(dm, R_0x9a0, 0xf00, dma_type);
++		/*@0: posedge, 1: negedge*/
++		odm_set_bb_reg(dm, R_0x9a0, BIT(31), edge);
++		odm_set_bb_reg(dm, R_0x9a0, 0xe0, smp_rate);
++		/*	@(0:) '80MHz'
++		 *	(1:) '40MHz'
++		 *	(2:) '20MHz'
++		 *	(3:) '10MHz'
++		 *	(4:) '5MHz'
++		 *	(5:) '2.5MHz'
++		 *	(6:) '1.25MHz'
++		 *	(7:) '160MHz (for BW160 ic)'
++		 */
++	}
++}
++
++void phydm_la_set_mac_trigger_time(void *dm_void, u32 trigger_time_mu_sec)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 time_unit_num = 0;
++	u32 unit = 0;
++
++	if (trigger_time_mu_sec < 128)
++		unit = 0; /*unit: 1mu sec*/
++	else if (trigger_time_mu_sec < 256)
++		unit = 1; /*unit: 2mu sec*/
++	else if (trigger_time_mu_sec < 512)
++		unit = 2; /*unit: 4mu sec*/
++	else if (trigger_time_mu_sec < 1024)
++		unit = 3; /*unit: 8mu sec*/
++	else if (trigger_time_mu_sec < 2048)
++		unit = 4; /*unit: 16mu sec*/
++	else if (trigger_time_mu_sec < 4096)
++		unit = 5; /*unit: 32mu sec*/
++	else if (trigger_time_mu_sec < 8192)
++		unit = 6; /*unit: 64mu sec*/
++
++	time_unit_num = (u8)(trigger_time_mu_sec >> unit);
++
++	pr_debug("2. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
++		 time_unit_num, unit);
++	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, (
++		    "3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
++		    time_unit_num, unit));
++	#endif
++
++	if (dm->support_ic_type & ODM_RTL8192F) {
++		odm_set_mac_reg(dm, R_0x7fc, BIT(2) | BIT(1) | BIT(0), unit);
++		odm_set_mac_reg(dm, R_0x7f0, 0x7f00, (time_unit_num & 0x7f));
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		odm_set_mac_reg(dm, R_0x7cc, BIT(18) | BIT(17) | BIT(16), unit);
++		odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
++	#endif
++	} else {
++		odm_set_mac_reg(dm, R_0x7cc, BIT(20) | BIT(19) | BIT(18), unit);
++		odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
++	}
++}
++
++void phydm_la_set_buff_mode(void *dm_void, enum la_buff_mode mode)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	struct rtl8192cd_priv		*priv = dm->priv;
++	u8 normal_LA_on = priv->pmib->miscEntry.normal_LA_on;
++#endif
++	u32 buff_size_base = 0;
++	u32 end_pos_tmp = 0;
++
++	smp->la_buff_mode = mode;
++	switch (dm->support_ic_type) {
++	case ODM_RTL8814A:
++		buff_size_base = 0x10000;
++		end_pos_tmp = 0x40000;
++		break;
++	case ODM_RTL8822B:
++	case ODM_RTL8822C:
++	case ODM_RTL8812F:
++		buff_size_base = 0x20000; /*@WIN: TX_FIFO_SIZE_LA_8822C*/
++		end_pos_tmp = 0x40000;
++		break;
++	case ODM_RTL8814B:
++		buff_size_base = 0x30000;
++		end_pos_tmp = 0x60000;
++		break;
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	case ODM_RTL8197F:
++	case ODM_RTL8198F:
++	case ODM_RTL8197G:
++		buff_size_base = 0x10000;
++		end_pos_tmp = (normal_LA_on == 1) ? 0x20000 : 0x10000;
++		break;
++#endif
++	case ODM_RTL8192F:
++		buff_size_base = 0xE000;
++		end_pos_tmp = 0x10000;
++		break;
++	case ODM_RTL8821C:
++		buff_size_base = 0x8000;
++		end_pos_tmp = 0x10000;
++		break;
++	case ODM_RTL8195B:
++		buff_size_base = 0x4000;
++		end_pos_tmp = 0x8000;
++		break;
++	default:
++		pr_debug("[%s] Warning!", __func__);
++		break;
++	}
++
++	buf->buffer_size = buff_size_base;
++
++	if (dm->support_ic_type & FULL_BUFF_MODE_SUPPORT) {
++		if (mode == ADCSMP_BUFF_HALF) {
++			odm_set_mac_reg(dm, R_0x7cc, BIT(30), 0);
++		} else {
++			buf->buffer_size = buf->buffer_size << 1;
++			odm_set_mac_reg(dm, R_0x7cc, BIT(30), 1);
++		}
++	}
++
++	buf->end_pos = end_pos_tmp;
++	buf->start_pos = end_pos_tmp - buf->buffer_size;
++	smp->smp_number_max = buf->buffer_size >> 3;
++
++	pr_debug("start_addr=(0x%x), end_addr=(0x%x), buffer_size=(0x%x), smp_number_max=(%d)\n",
++		 buf->start_pos, buf->end_pos, buf->buffer_size,
++		 smp->smp_number_max);
++}
++
++void phydm_la_adc_smp_start(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	u8 tmp_u1b = 0;
++	u8 i = 0;
++	u8 polling_bit = 0;
++	boolean polling_ok = false;
++	boolean impossible_trig_condi = (smp->en_fake_trig) ? true : false;
++
++	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
++		    ("1. [BB Setting] Mode=(%d), DbgPort=(0x%x), Edge=(%d), SmpRate=(%d), Trig_Sel=(0x%x), Dma_type=(%d)\n",
++		    smp->la_trig_mode, smp->la_dbg_port, smp->la_trigger_edge,
++		    smp->la_smp_rate, smp->la_trig_sig_sel, smp->la_dma_type));
++	#endif
++	pr_debug("1. [BB Setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n",
++		 smp->la_trig_mode, smp->la_dbg_port, smp->la_trigger_edge,
++		 smp->la_smp_rate, smp->la_trig_sig_sel, smp->la_dma_type);
++
++	phydm_la_set_mac_trigger_time(dm, smp->la_trigger_time);
++	phydm_la_set_bb(dm);
++	phydm_la_set_bb_dbg_port(dm, impossible_trig_condi);
++	phydm_la_set_mac_iq_dump(dm, impossible_trig_condi);
++
++	#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	watchdog_stop(dm->priv);
++	#endif
++
++	if (impossible_trig_condi) {
++		ODM_delay_ms(100);
++		phydm_la_set_bb_dbg_port(dm, false);
++
++		if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
++			phydm_la_set_trig_src(dm, PHYDM_ADC_MAC_TRIG);
++		}
++	}
++#if RTL8198F_SUPPORT
++	phydm_la_pre_run(dm);
++#endif
++	polling_bit = (smp->la_dump_mode == LA_BB_ADC_DUMP) ? BIT(1) : BIT(2);
++	do { /*Polling time always use 100ms, when it exceed 2s, break loop*/
++		if (dm->support_ic_type & ODM_RTL8192F)
++			tmp_u1b = odm_read_1byte(dm, R_0x7f0);
++		else
++			tmp_u1b = odm_read_1byte(dm, R_0x7c0);
++
++		pr_debug("[%d] polling rpt=((0x%x))\n", i, tmp_u1b);
++
++		if (smp->adc_smp_state != ADCSMP_STATE_SET) {
++			pr_debug("[state Error] state != ADCSMP_STATE_SET\n");
++			break;
++
++		} else if (tmp_u1b & polling_bit) {
++			ODM_delay_ms(100);
++			i++;
++			continue;
++		} else {
++			pr_debug("[LA Query OK] polling_bit=%d\n", polling_bit);
++			polling_ok = true;
++			break;
++		}
++	} while (i < 20);
++
++	if (smp->adc_smp_state == ADCSMP_STATE_SET) {
++		if (polling_ok)
++			phydm_la_get_tx_pkt_buf(dm);
++		else
++			pr_debug("[Polling timeout]\n");
++	}
++
++	#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	watchdog_resume(dm->priv);
++	#endif
++
++	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	if (smp->adc_smp_state == ADCSMP_STATE_SET)
++		smp->adc_smp_state = ADCSMP_STATE_QUERY;
++	#endif
++
++	pr_debug("[LA mode] la_count = ((%d))\n", smp->la_count);
++	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
++		    ("[LA mode] la_count = ((%d))\n", smp->la_count));
++	#endif
++
++	phydm_la_stop(dm);
++
++	if (smp->la_count == 0) {
++		pr_debug("LA Dump finished ---------->\n\n\n");
++		phydm_release_bb_dbg_port(dm);
++
++		#if (RTL8821C_SUPPORT || RTL8195B_SUPPORT)
++		phydm_la_clk_en(dm, false);
++		#endif
++	} else {
++		smp->la_count--;
++		pr_debug("LA Dump more ---------->\n\n\n");
++		phydm_la_set(dm);
++	}
++}
++
++void phydm_la_set(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	boolean is_set_success = true;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++
++	if (smp->adc_smp_state != ADCSMP_STATE_IDLE)
++		is_set_success = false;
++	else if (smp->adc_smp_buf.length == 0)
++		is_set_success = phydm_la_buffer_allocate(dm);
++
++	if (!is_set_success) {
++		pr_debug("[LA Set Fail] LA_State=(%d)\n", smp->adc_smp_state);
++		return;
++	}
++
++	smp->adc_smp_state = ADCSMP_STATE_SET;
++
++	pr_debug("[LA Set Success] LA_State=(%d)\n", smp->adc_smp_state);
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++
++	pr_debug("ADCSmp_work_item_index=(%d)\n", smp->la_work_item_index);
++
++	if (smp->la_work_item_index != 0) {
++		odm_schedule_work_item(&smp->adc_smp_work_item_1);
++		smp->la_work_item_index = 0;
++	} else {
++		odm_schedule_work_item(&smp->adc_smp_work_item);
++		smp->la_work_item_index = 1;
++	}
++#else
++	phydm_la_adc_smp_start(dm);
++#endif
++}
++
++void phydm_la_cmd(void *dm_void, char input[][16], u32 *_used, char *output,
++		  u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE))
++		return;
++
++#ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM
++	if (dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC) {
++		if (dm->is_download_fw)
++			return;
++	}
++	#if RTL8198F_SUPPORT
++	if (dm->support_ic_type & ODM_RTL8198F) {
++		if (!*dm->mp_mode && !dm->priv->pmib->miscEntry.normal_LA_on) {
++			pr_debug("plz re-set normal_LA_on = 1 & DnUp.\n");
++			return;
++		}
++	}
++	#endif
++#endif
++
++	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
++
++	/*@dbg_print("echo cmd input_num = %d\n", input_num);*/
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "=====[LA Mode Help] =============================\n");
++		/*Trigger*/
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "BB_trig:  1 0 {DbgPort Bit} {DMA#} {TrigTime} {DbgPort_head(Jgr2)}\n\t{DbgPort} {Edge: 0(P),1(N)} {f_smp:80 >> N} {Capture num}\n\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "MAC_trig: 1 1 {0-ok/1-fail/2-cca} {DMA#} {TrigTime} {DbgPort_head(Jgr2)}\n\t{DbgPort} {N/A} {f_smp:80 >> N} {Cpture num}\n\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "All: {En} {0:ADC_BB_trig,1:ADC MAC_trig,2:RF0,3:RF1,4:MAC}\n\t{BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA#} {TrigTime}\n\t{DbgPort_head/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n\n");
++		/*Adv-Trig*/
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "adv show\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "adv {adv_trig_en} {0:And[0]_disable} {en}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "adv {adv_trig_en} {1~3: And[3:0]} {Sel} {Val} {Inv}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "adv {adv_trig_en} {4: And[4]} {BitMask} {BitVal} {Inv}\n\n");
++		#endif
++		/*Setting*/
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "set {1:tx_buff_size} {0: half, 1:full}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "set {2:Fake Trigger} {en}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "set {3:Auto Print} {en}\n\n");
++		/*Print*/
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "print {0: all(Hex)}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "print {1: partial} {0:hex 1:dec 2: s-dec} {bit_L} {bit_H}\n\n");
++
++		/*Fast Trigger*/
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "fast {0: CCA trig & AGC Dbg Port}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "fast {1: CCA trig & EVM Dbg Port}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "fast {2: CCA trig & SNR Dbg Port}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "fast {3: CCA trig & CFO Dbg Port}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "fast {4: CCA trig & ADC output Dbg Port}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "fast {10: EVM>=-X dB, 11: EVM<=-X dB} {X=2/4/8/16/32/64} {0:Lgcy, 1:HT}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "fast {12: EVM=-X dB} {X} {0:Lgcy, 1:HT}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "fast {20: RX-rate-idx=X} {X}\n");
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "=================================================\n");
++	} else if ((strcmp(input[1], "print") == 0)) {
++		phydm_la_buffer_print(dm, input, &used, output, &out_len);
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	} else if ((strcmp(input[1], "fast") == 0)) {
++		phydm_la_cmd_fast_jgr3(dm, input, &used, output, &out_len);
++
++	} else if ((strcmp(input[1], "adv") == 0)) {
++		phydm_la_bb_adv_cmd_jgr3(dm, input, &used, output, &out_len);
++#endif
++	} else if ((strcmp(input[1], "set") == 0)) {
++		PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
++
++		if (var1[1] == 1) {
++			PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
++			phydm_la_set_buff_mode(dm, (enum la_buff_mode)var1[2]);
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "Buff_mode=(%d/2)\n", smp->la_buff_mode + 1);
++		} else if (var1[1] == 2) {
++			PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
++			smp->en_fake_trig = (boolean)var1[2];
++
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "en_fake_trig=(%d)\n", smp->en_fake_trig);
++		} else if (var1[1] == 3) {
++			PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
++			smp->is_la_print = (boolean)var1[2];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "Auto print=(%d)\n", smp->is_la_print);
++		}
++	} else if (var1[0] == 1) {
++		PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
++
++		smp->la_trig_mode = (u8)var1[1];
++
++		if (smp->la_trig_mode == PHYDM_MAC_TRIG)
++			PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
++		else
++			PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
++		smp->la_trig_sig_sel = var1[2];
++
++		PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
++		PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
++		PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
++		PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]);
++		PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]);
++		PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]);
++		PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]);
++
++		smp->la_dma_type = (u8)var1[3];
++		smp->la_trigger_time = var1[4]; /*unit: us*/
++		smp->la_mac_mask_or_hdr_sel = var1[5];
++		smp->la_dbg_port = var1[6];
++		smp->la_trigger_edge = (u8)var1[7];
++		smp->la_smp_rate = (u8)(var1[8] & 0x7);
++		smp->la_count = var1[9];
++
++		pr_debug("echo lamode %d %d %d %d %d %d %x %d %d %d\n",
++			 var1[0], var1[1], var1[2], var1[3], var1[4],
++			 var1[5], var1[6], var1[7], var1[8], var1[9]);
++		#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++		RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
++			    ("echo lamode %d %d %d %d %d %d %x %d %d %d\n",
++			    var1[0], var1[1], var1[2], var1[3],
++			    var1[4], var1[5], var1[6], var1[7],
++			    var1[8], var1[9]));
++		#endif
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "a.En= ((1)),  b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n",
++			 smp->la_trig_mode, smp->la_trig_sig_sel,
++			 smp->la_dma_type);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "e.Trig_Time = ((%dus)), f.Dbg_head/mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n",
++			 smp->la_trigger_time,
++			 smp->la_mac_mask_or_hdr_sel, smp->la_dbg_port);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n",
++			 smp->la_trigger_edge, (80 >> smp->la_smp_rate),
++			 smp->la_count);
++
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "k.en_new_bbtrigger = ((%d))\n",
++			 smp->adv_trig_table.la_adv_bbtrigger_en);
++		#endif
++
++		phydm_la_set(dm);
++	} else {
++		phydm_la_stop(dm);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Disable LA mode\n");
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_la_stop(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++
++	smp->adc_smp_state = ADCSMP_STATE_IDLE;
++}
++
++void phydm_la_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
++
++	smp->adc_smp_state = ADCSMP_STATE_IDLE;
++	smp->is_la_print = true;
++	smp->en_fake_trig = false;
++	smp->txff_page = 0xffffffff;
++	phydm_la_set_buff_mode(dm, ADCSMP_BUFF_HALF);
++
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	phydm_la_bb_adv_reset_jgr3(dm);
++	#endif
++}
++
++void adc_smp_de_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	phydm_la_stop(dm);
++	phydm_la_buffer_release(dm);
++}
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++void adc_smp_work_item_callback(void *context)
++{
++	void *adapter = (void *)context;
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++	struct rt_adcsmp *smp = &dm->adcsmp;
++
++	pr_debug("[WorkItem Call back] LA_State=(%d)\n", smp->adc_smp_state);
++	phydm_la_adc_smp_start(dm);
++}
++#endif
++#endif /*@endif PHYDM_LA_MODE_SUPPORT*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_adc_sampling.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_adc_sampling.h
+new file mode 100644
+index 000000000..1f978098c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_adc_sampling.h
+@@ -0,0 +1,172 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __INC_ADCSMP_H
++#define __INC_ADCSMP_H
++
++#if (PHYDM_LA_MODE_SUPPORT)
++
++/* fix compile time flag*/
++#define DYNAMIC_LA_MODE "4.1"
++
++/* @1 ============================================================
++ * 1  Definition
++ * 1 ============================================================
++ */
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++#if (RTL8197F_SUPPORT || RTL8198F_SUPPORT || RTL8197G_SUPPORT)
++	#define PHYDM_COMPILE_LA_STORE_IN_IMEM
++#endif
++#endif
++
++#define PHYDM_LA_STORE_IN_IMEM_IC (ODM_RTL8197F | ODM_RTL8198F | ODM_RTL8197G)
++
++#define FULL_BUFF_MODE_SUPPORT (ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\
++				ODM_RTL8812F | ODM_RTL8814B)
++
++/* @ ============================================================
++ *  enumrate
++ *  ============================================================
++ */
++enum la_dump_mode {
++	LA_BB_ADC_DUMP		= 0,
++	LA_MAC_DBG_DUMP		= 1
++};
++
++enum rt_adcsmp_trig_sel {
++	PHYDM_ADC_BB_TRIG	= 0,
++	PHYDM_ADC_MAC_TRIG	= 1,
++	PHYDM_ADC_RF0_TRIG	= 2,
++	PHYDM_ADC_RF1_TRIG	= 3,
++	PHYDM_MAC_TRIG		= 4
++};
++
++enum rt_adcsmp_trig_sig_sel {
++	ADCSMP_TRIG_CRCOK	= 0,
++	ADCSMP_TRIG_CRCFAIL	= 1,
++	ADCSMP_TRIG_CCA		= 2,
++	ADCSMP_TRIG_REG		= 3
++};
++
++enum rt_adcsmp_state {
++	ADCSMP_STATE_IDLE	= 0,
++	ADCSMP_STATE_SET	= 1,
++	ADCSMP_STATE_QUERY	= 2
++};
++
++enum la_buff_mode {
++	ADCSMP_BUFF_HALF	= 0,
++	ADCSMP_BUFF_ALL		= 1	/*Only use in MP Driver*/
++};
++
++/* @ ============================================================
++ *   structure
++ *  ============================================================
++ */
++
++struct rt_adcsmp_string {
++	u32			*octet;
++	u32			length;
++	u32			buffer_size;
++	u32			start_pos;
++	u32			end_pos;	/*@buf addr*/
++};
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++struct la_adv_trig {
++	boolean			la_adv_bbtrigger_en;
++	boolean			la_ori_bb_dis;
++	u8			la_and1_sel;
++	u8			la_and1_val;
++	boolean			la_and1_inv;
++	u8			la_and2_sel;
++	u8			la_and2_val;
++	boolean			la_and2_inv;
++	u8			la_and3_sel;
++	u8			la_and3_val;
++	boolean			la_and3_inv;
++	u32			la_and4_mask;
++	u32			la_and4_bitmap;
++	boolean			la_and4_inv;
++};
++#endif
++
++struct rt_adcsmp {
++	struct rt_adcsmp_string	adc_smp_buf;
++	enum rt_adcsmp_state	adc_smp_state;
++	enum la_buff_mode	la_buff_mode;
++	enum la_dump_mode	la_dump_mode;
++	u8			la_trig_mode;
++	u32			la_trig_sig_sel;
++	u8			la_dma_type;
++	u32			la_trigger_time;
++	/*@1.BB mode: Dbg port header sel, 2.MAC mode: for reference mask*/
++	u32			la_mac_mask_or_hdr_sel;
++	u32			la_dbg_port;
++	u8			la_trigger_edge;
++	u8			la_smp_rate;
++	u32			la_count;
++	u32			smp_number;
++	u32			smp_number_max;
++	u32			txff_page;
++	boolean			is_la_print;
++	boolean			en_fake_trig;
++#if (RTL8197F_SUPPORT)
++	u32			backup_dma;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	u8			la_work_item_index;
++	RT_WORK_ITEM		adc_smp_work_item;
++	RT_WORK_ITEM		adc_smp_work_item_1;
++#endif
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	struct la_adv_trig	adv_trig_table;
++#endif
++};
++
++/* @ ============================================================
++ *  Function Prototype
++ *  ============================================================
++ */
++
++void phydm_la_set(void *dm_void);
++
++void phydm_la_cmd(void *dm_void, char input[][16], u32 *_used, char *output,
++		  u32 *_out_len);
++
++void phydm_la_stop(void *dm_void);
++
++void phydm_la_init(void *dm_void);
++
++void adc_smp_de_init(void *dm_void);
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++void adc_smp_work_item_callback(void *context);
++#endif
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_antdect.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_antdect.c
+new file mode 100644
+index 000000000..a3213896c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_antdect.c
+@@ -0,0 +1,888 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/* ************************************************************
++ * include files
++ * ************************************************************ */
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#ifdef CONFIG_ANT_DETECTION
++
++/* @IS_ANT_DETECT_SUPPORT_SINGLE_TONE(adapter)
++ * IS_ANT_DETECT_SUPPORT_RSSI(adapter)
++ * IS_ANT_DETECT_SUPPORT_PSD(adapter) */
++
++/* @1 [1. Single Tone method] =================================================== */
++
++/*@
++ * Description:
++ *	Set Single/Dual Antenna default setting for products that do not do detection in advance.
++ *
++ * Added by Joseph, 2012.03.22
++ *   */
++void odm_sw_ant_div_construct_scan_chnl(
++	void *adapter,
++	u8 scan_chnl)
++{
++}
++
++u8 odm_sw_ant_div_select_scan_chnl(
++	void *adapter)
++{
++	return 0;
++}
++
++void odm_single_dual_antenna_default_setting(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
++	void *adapter = dm->adapter;
++
++	u8 bt_ant_num = BT_GetPgAntNum(adapter);
++	/* Set default antenna A and B status */
++	if (bt_ant_num == 2) {
++		dm_swat_table->ANTA_ON = true;
++		dm_swat_table->ANTB_ON = true;
++
++	} else if (bt_ant_num == 1) {
++		/* Set antenna A as default */
++		dm_swat_table->ANTA_ON = true;
++		dm_swat_table->ANTB_ON = false;
++
++	} else
++		RT_ASSERT(false, ("Incorrect antenna number!!\n"));
++}
++
++/* @2 8723A ANT DETECT
++ *
++ * Description:
++ *	Implement IQK single tone for RF DPK loopback and BB PSD scanning.
++ *	This function is cooperated with BB team Neil.
++ *
++ * Added by Roger, 2011.12.15
++ *   */
++boolean
++odm_single_dual_antenna_detection(
++	void *dm_void,
++	u8 mode)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	void *adapter = dm->adapter;
++	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
++	u32 current_channel, rf_loop_reg;
++	u8 n;
++	u32 reg88c, regc08, reg874, regc50, reg948, regb2c, reg92c, reg930, reg064, afe_rrx_wait_cca;
++	u8 initial_gain = 0x5a;
++	u32 PSD_report_tmp;
++	u32 ant_a_report = 0x0, ant_b_report = 0x0, ant_0_report = 0x0;
++	boolean is_result = true;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "%s============>\n", __func__);
++
++	if (!(dm->support_ic_type & ODM_RTL8723B))
++		return is_result;
++
++	/* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
++	if (!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(((PADAPTER)adapter)))
++		return is_result;
++
++	/* @1 Backup Current RF/BB Settings */
++
++	current_channel = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
++	rf_loop_reg = odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK);
++	if (dm->support_ic_type & ODM_RTL8723B) {
++		reg92c = odm_get_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD);
++		reg930 = odm_get_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD);
++		reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
++		regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);
++		reg064 = odm_get_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29));
++		odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x1);
++		odm_set_bb_reg(dm, rfe_ctrl_anta_src, 0xff, 0x77);
++		odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* @dbg 7 */
++		odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0); /* @dbg 8 */
++		odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x0);
++	}
++
++	ODM_delay_us(10);
++
++	/* Store A path Register 88c, c08, 874, c50 */
++	reg88c = odm_get_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD);
++	regc08 = odm_get_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD);
++	reg874 = odm_get_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD);
++	regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
++
++	/* Store AFE Registers */
++	if (dm->support_ic_type & ODM_RTL8723B)
++		afe_rrx_wait_cca = odm_get_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD);
++
++	/* Set PSD 128 pts */
++	odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* @128 pts */
++
++	/* To SET CH1 to do */
++	odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* @channel 1 */
++
++	/* @AFE all on step */
++	if (dm->support_ic_type & ODM_RTL8723B)
++		odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, 0x01c00016);
++
++	/* @3 wire Disable */
++	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, 0xCCF000C0);
++
++	/* @BB IQK setting */
++	odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800E4);
++	odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22208000);
++
++	/* @IQK setting tone@ 4.34Mhz */
++	odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008C1C);
++	odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00);
++
++	/* Page B init */
++	odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x00080000);
++	odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x0f600000);
++	odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
++	odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1f);
++	if (dm->support_ic_type & ODM_RTL8723B) {
++		odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82150016);
++		odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28150016);
++	}
++	odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d0);
++	odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7f, initial_gain);
++
++	/* @IQK Single tone start */
++	odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
++	odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
++	odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
++
++	ODM_delay_us(10000);
++
++	/* PSD report of antenna A */
++	PSD_report_tmp = 0x0;
++	for (n = 0; n < 2; n++) {
++		PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain);
++		if (PSD_report_tmp > ant_a_report)
++			ant_a_report = PSD_report_tmp;
++	}
++
++	/* @change to Antenna B */
++	if (dm->support_ic_type & ODM_RTL8723B) {
++		odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
++		odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
++	}
++
++	ODM_delay_us(10);
++
++	/* PSD report of antenna B */
++	PSD_report_tmp = 0x0;
++	for (n = 0; n < 2; n++) {
++		PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain);
++		if (PSD_report_tmp > ant_b_report)
++			ant_b_report = PSD_report_tmp;
++	}
++
++	/* @Close IQK Single Tone function */
++	odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
++
++	/* @1 Return to antanna A */
++	if (dm->support_ic_type & ODM_RTL8723B) {
++		/* @external DPDT */
++		odm_set_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD, reg92c);
++
++		/* @internal S0/S1 */
++		odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
++		odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
++		odm_set_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD, reg930);
++		odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), reg064);
++	}
++
++	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, reg88c);
++	odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, regc08);
++	odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, reg874);
++	odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7F, 0x40);
++	odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD, regc50);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, current_channel);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_loop_reg);
++
++	/* Reload AFE Registers */
++	if (dm->support_ic_type & ODM_RTL8723B)
++		odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, afe_rrx_wait_cca);
++
++	if (dm->support_ic_type & ODM_RTL8723B) {
++		PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_A[%d]= %d\n", 2416,
++			  ant_a_report);
++		PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_B[%d]= %d\n", 2416,
++			  ant_b_report);
++
++		/* @2 Test ant B based on ant A is ON */
++		if (ant_a_report >= 100 && ant_b_report >= 100 && ant_a_report <= 135 && ant_b_report <= 135) {
++			u8 TH1 = 2, TH2 = 6;
++
++			if ((ant_a_report - ant_b_report < TH1) || (ant_b_report - ant_a_report < TH1)) {
++				dm_swat_table->ANTA_ON = true;
++				dm_swat_table->ANTB_ON = true;
++				PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Dual Antenna\n",
++					  __func__);
++			} else if (((ant_a_report - ant_b_report >= TH1) && (ant_a_report - ant_b_report <= TH2)) ||
++				   ((ant_b_report - ant_a_report >= TH1) && (ant_b_report - ant_a_report <= TH2))) {
++				dm_swat_table->ANTA_ON = false;
++				dm_swat_table->ANTB_ON = false;
++				is_result = false;
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "%s: Need to check again\n",
++					  __func__);
++			} else {
++				dm_swat_table->ANTA_ON = true;
++				dm_swat_table->ANTB_ON = false;
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "%s: Single Antenna\n", __func__);
++			}
++			dm->ant_detected_info.is_ant_detected = true;
++			dm->ant_detected_info.db_for_ant_a = ant_a_report;
++			dm->ant_detected_info.db_for_ant_b = ant_b_report;
++			dm->ant_detected_info.db_for_ant_o = ant_0_report;
++
++		} else {
++			PHYDM_DBG(dm, DBG_ANT_DIV, "return false!!\n");
++			is_result = false;
++		}
++	}
++	return is_result;
++}
++
++/* @1 [2. Scan AP RSSI method] ================================================== */
++
++boolean
++odm_sw_ant_div_check_before_link(
++	void *dm_void)
++{
++#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
++
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	void *adapter = dm->adapter;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	//PMGNT_INFO		mgnt_info = &adapter->MgntInfo;
++	PMGNT_INFO mgnt_info = &(((PADAPTER)(adapter))->MgntInfo);
++	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	s8 score = 0;
++	PRT_WLAN_BSS p_tmp_bss_desc, p_test_bss_desc;
++	u8 power_target_L = 9, power_target_H = 16;
++	u8 tmp_power_diff = 0, power_diff = 0, avg_power_diff = 0, max_power_diff = 0, min_power_diff = 0xff;
++	u16 index, counter = 0;
++	static u8 scan_channel;
++	u32 tmp_swas_no_link_bk_reg948;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n",
++		  dm->dm_swat_table.ANTA_ON, dm->dm_swat_table.ANTB_ON);
++
++	/* @if(HP id) */
++	{
++		if (dm->dm_swat_table.rssi_ant_dect_result == true && dm->support_ic_type == ODM_RTL8723B) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "8723B RSSI-based Antenna Detection is done\n");
++			return false;
++		}
++
++		if (dm->support_ic_type == ODM_RTL8723B) {
++			if (dm_swat_table->swas_no_link_bk_reg948 == 0xff)
++				dm_swat_table->swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH);
++		}
++	}
++
++	if (dm->adapter == NULL) { /* @For BSOD when plug/unplug fast.  //By YJ,120413 */
++		/* The ODM structure is not initialized. */
++		return false;
++	}
++
++	/* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
++	if (!IS_ANT_DETECT_SUPPORT_RSSI(((PADAPTER)adapter)))
++		return false;
++	else
++		PHYDM_DBG(dm, DBG_ANT_DIV, "Antenna Detection: RSSI method\n");
++
++	/* Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. */
++	odm_acquire_spin_lock(dm, RT_RF_STATE_SPINLOCK);
++	if (hal_data->eRFPowerState != eRfOn || mgnt_info->RFChangeInProgress || mgnt_info->bMediaConnect) {
++		odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);
++
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "%s: rf_change_in_progress(%x), e_rf_power_state(%x)\n",
++			  __func__, mgnt_info->RFChangeInProgress,
++			  hal_data->eRFPowerState);
++
++		dm_swat_table->swas_no_link_state = 0;
++
++		return false;
++	} else
++		odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);
++	PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->swas_no_link_state = %d\n",
++		  dm_swat_table->swas_no_link_state);
++	/* @1 Run AntDiv mechanism "Before Link" part. */
++	if (dm_swat_table->swas_no_link_state == 0) {
++		/* @1 Prepare to do Scan again to check current antenna state. */
++
++		/* Set check state to next step. */
++		dm_swat_table->swas_no_link_state = 1;
++
++		/* @Copy Current Scan list. */
++		mgnt_info->tmpNumBssDesc = mgnt_info->NumBssDesc;
++		PlatformMoveMemory((void *)mgnt_info->tmpbssDesc, (void *)mgnt_info->bssDesc, sizeof(RT_WLAN_BSS) * MAX_BSS_DESC);
++
++		/* @Go back to scan function again. */
++		PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Scan one more time\n",
++			  __func__);
++		mgnt_info->ScanStep = 0;
++		mgnt_info->bScanAntDetect = true;
++		scan_channel = odm_sw_ant_div_select_scan_chnl(adapter);
++
++		if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
++			if (fat_tab->rx_idle_ant == MAIN_ANT)
++				odm_update_rx_idle_ant(dm, AUX_ANT);
++			else
++				odm_update_rx_idle_ant(dm, MAIN_ANT);
++			if (scan_channel == 0) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "%s: No AP List Avaiable, Using ant(%s)\n",
++					  __func__,
++					  (fat_tab->rx_idle_ant == MAIN_ANT) ?
++					  "AUX_ANT" : "MAIN_ANT");
++
++				if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {
++					dm_swat_table->ant_5g = fat_tab->rx_idle_ant;
++					PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_5g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
++				} else {
++					dm_swat_table->ant_2g = fat_tab->rx_idle_ant;
++					PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_2g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
++				}
++				return false;
++			}
++
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "%s: Change to %s for testing.\n", __func__,
++				  ((fat_tab->rx_idle_ant == MAIN_ANT) ?
++				  "MAIN_ANT" : "AUX_ANT"));
++		} else if (dm->support_ic_type & (ODM_RTL8723B)) {
++			/*Switch Antenna to another one.*/
++
++			tmp_swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH);
++
++			if (dm_swat_table->cur_antenna == MAIN_ANT && tmp_swas_no_link_bk_reg948 == 0x200) {
++				odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
++				odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
++				dm_swat_table->cur_antenna = AUX_ANT;
++			} else {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "Reg[948]= (( %x )) was in wrong state\n",
++					  tmp_swas_no_link_bk_reg948);
++				return false;
++			}
++			ODM_delay_us(10);
++
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "%s: Change to (( %s-ant))  for testing.\n",
++				  __func__,
++				  (dm_swat_table->cur_antenna == MAIN_ANT) ?
++				  "MAIN" : "AUX");
++		}
++
++		odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
++		PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
++
++		return true;
++	} else { /* @dm_swat_table->swas_no_link_state == 1 */
++		/* @1 ScanComple() is called after antenna swiched. */
++		/* @1 Check scan result and determine which antenna is going */
++		/* @1 to be used. */
++
++		PHYDM_DBG(dm, DBG_ANT_DIV, " tmp_num_bss_desc= (( %d ))\n",
++			  mgnt_info->tmpNumBssDesc); /* @debug for Dino */
++
++		for (index = 0; index < mgnt_info->tmpNumBssDesc; index++) {
++			p_tmp_bss_desc = &mgnt_info->tmpbssDesc[index]; /* @Antenna 1 */
++			p_test_bss_desc = &mgnt_info->bssDesc[index]; /* @Antenna 2 */
++
++			if (PlatformCompareMemory(p_test_bss_desc->bdBssIdBuf, p_tmp_bss_desc->bdBssIdBuf, 6) != 0) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "%s: ERROR!! This shall not happen.\n",
++					  __func__);
++				continue;
++			}
++
++			if (dm->support_ic_type != ODM_RTL8723B) {
++				if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
++					if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) {
++						PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Compare scan entry: score++\n", __func__);
++						RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
++						PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
++
++						score++;
++						PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
++					} else if (p_tmp_bss_desc->RecvSignalPower < p_test_bss_desc->RecvSignalPower) {
++						PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Compare scan entry: score--\n", __func__);
++						RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
++						PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
++						score--;
++					} else {
++						if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp < 5000) {
++							RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
++							PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
++							PHYDM_DBG(dm, DBG_ANT_DIV, "The 2nd Antenna didn't get this AP\n\n");
++						}
++					}
++				}
++			} else { /* @8723B */
++				if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
++					PHYDM_DBG(dm, DBG_ANT_DIV, "channel_number == scan_channel->(( %d ))\n", p_tmp_bss_desc->ChannelNumber);
++
++					if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { /* Pow(Ant1) > Pow(Ant2) */
++						counter++;
++						tmp_power_diff = (u8)(p_tmp_bss_desc->RecvSignalPower - p_test_bss_desc->RecvSignalPower);
++						power_diff = power_diff + tmp_power_diff;
++
++						PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
++						PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
++						PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
++
++#if 0
++						/* PHYDM_DBG(dm,DBG_ANT_DIV, "tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d))\n", tmp_power_diff,max_power_diff,min_power_diff); */
++#endif
++						if (tmp_power_diff > max_power_diff)
++							max_power_diff = tmp_power_diff;
++						if (tmp_power_diff < min_power_diff)
++							min_power_diff = tmp_power_diff;
++#if 0
++						/* PHYDM_DBG(dm,DBG_ANT_DIV, "max_power_diff: (( %d)),min_power_diff: (( %d))\n",max_power_diff,min_power_diff); */
++#endif
++
++						PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
++					} else if (p_test_bss_desc->RecvSignalPower > p_tmp_bss_desc->RecvSignalPower) { /* Pow(Ant1) < Pow(Ant2) */
++						counter++;
++						tmp_power_diff = (u8)(p_test_bss_desc->RecvSignalPower - p_tmp_bss_desc->RecvSignalPower);
++						power_diff = power_diff + tmp_power_diff;
++						PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
++						PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
++						PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
++						if (tmp_power_diff > max_power_diff)
++							max_power_diff = tmp_power_diff;
++						if (tmp_power_diff < min_power_diff)
++							min_power_diff = tmp_power_diff;
++					} else { /* Pow(Ant1) = Pow(Ant2) */
++						if (p_test_bss_desc->bdTstamp > p_tmp_bss_desc->bdTstamp) { /* Stamp(Ant1) < Stamp(Ant2) */
++							PHYDM_DBG(dm, DBG_ANT_DIV, "time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000);
++							if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp > 5000) {
++								counter++;
++								PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
++								PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
++								PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
++								min_power_diff = 0;
++							}
++						} else
++							PHYDM_DBG(dm, DBG_ANT_DIV, "[Error !!!]: Time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000);
++					}
++				}
++			}
++		}
++
++		if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
++			if (mgnt_info->NumBssDesc != 0 && score < 0) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "%s: Using ant(%s)\n", __func__,
++					  (fat_tab->rx_idle_ant == MAIN_ANT) ?
++					  "MAIN_ANT" : "AUX_ANT");
++			} else {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "%s: Remain ant(%s)\n", __func__,
++					  (fat_tab->rx_idle_ant == MAIN_ANT) ?
++					  "AUX_ANT" : "MAIN_ANT");
++
++				if (fat_tab->rx_idle_ant == MAIN_ANT)
++					odm_update_rx_idle_ant(dm, AUX_ANT);
++				else
++					odm_update_rx_idle_ant(dm, MAIN_ANT);
++			}
++
++			if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {
++				dm_swat_table->ant_5g = fat_tab->rx_idle_ant;
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "dm_swat_table->ant_5g=%s\n",
++					  (fat_tab->rx_idle_ant == MAIN_ANT) ?
++					  "MAIN_ANT" : "AUX_ANT");
++			} else {
++				dm_swat_table->ant_2g = fat_tab->rx_idle_ant;
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "dm_swat_table->ant_2g=%s\n",
++					  (fat_tab->rx_idle_ant == MAIN_ANT) ?
++					  "MAIN_ANT" : "AUX_ANT");
++			}
++		} else if (dm->support_ic_type == ODM_RTL8723B) {
++			if (counter == 0) {
++				if (dm->dm_swat_table.pre_aux_fail_detec == false) {
++					dm->dm_swat_table.pre_aux_fail_detec = true;
++					dm->dm_swat_table.rssi_ant_dect_result = false;
++					PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] ->  Scan Target-channel again\n");
++
++					/* @3 [ Scan again ] */
++					odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
++					PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
++					return true;
++				} else { /* pre_aux_fail_detec == true */
++					/* @2 [ Single Antenna ] */
++					dm->dm_swat_table.pre_aux_fail_detec = false;
++					dm->dm_swat_table.rssi_ant_dect_result = true;
++					PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[  Still cannot find any AP ]]\n");
++					PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
++				}
++				dm->dm_swat_table.aux_fail_detec_counter++;
++			} else {
++				dm->dm_swat_table.pre_aux_fail_detec = false;
++
++				if (counter == 3) {
++					avg_power_diff = ((power_diff - max_power_diff - min_power_diff) >> 1) + ((max_power_diff + min_power_diff) >> 2);
++					PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) ,  power_diff: (( %d ))\n", counter, power_diff);
++					PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) ,  min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff);
++				} else if (counter >= 4) {
++					avg_power_diff = (power_diff - max_power_diff - min_power_diff) / (counter - 2);
++					PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) ,  power_diff: (( %d ))\n", counter, power_diff);
++					PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) ,  min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff);
++
++				} else { /* @counter==1,2 */
++					avg_power_diff = power_diff / counter;
++					PHYDM_DBG(dm, DBG_ANT_DIV, "avg_power_diff: (( %d )) , counter: (( %d )) ,  power_diff: (( %d ))\n", avg_power_diff, counter, power_diff);
++				}
++
++				/* @2 [ Retry ] */
++				if (avg_power_diff >= power_target_L && avg_power_diff <= power_target_H) {
++					dm->dm_swat_table.retry_counter++;
++
++					if (dm->dm_swat_table.retry_counter <= 3) {
++						dm->dm_swat_table.rssi_ant_dect_result = false;
++						PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Low confidence result ]] avg_power_diff= (( %d ))  ->  Scan Target-channel again ]]\n", avg_power_diff);
++
++						/* @3 [ Scan again ] */
++						odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
++						PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
++						return true;
++					} else {
++						dm->dm_swat_table.rssi_ant_dect_result = true;
++						PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Still Low confidence result ]]  (( retry_counter > 3 ))\n");
++						PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
++					}
++				}
++				/* @2 [ Dual Antenna ] */
++				else if ((mgnt_info->NumBssDesc != 0) && (avg_power_diff < power_target_L)) {
++					dm->dm_swat_table.rssi_ant_dect_result = true;
++					if (dm->dm_swat_table.ANTB_ON == false) {
++						dm->dm_swat_table.ANTA_ON = true;
++						dm->dm_swat_table.ANTB_ON = true;
++					}
++					PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Dual antenna\n", __func__);
++					dm->dm_swat_table.dual_ant_counter++;
++
++					/* set bt coexDM from 1ant coexDM to 2ant coexDM */
++					BT_SetBtCoexAntNum(adapter, BT_COEX_ANT_TYPE_DETECTED, 2);
++
++					/* @3 [ Init antenna diversity ] */
++					dm->support_ability |= ODM_BB_ANT_DIV;
++					odm_ant_div_init(dm);
++				}
++				/* @2 [ Single Antenna ] */
++				else if (avg_power_diff > power_target_H) {
++					dm->dm_swat_table.rssi_ant_dect_result = true;
++					if (dm->dm_swat_table.ANTB_ON == true) {
++						dm->dm_swat_table.ANTA_ON = true;
++						dm->dm_swat_table.ANTB_ON = false;
++#if 0
++						/* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 1); */
++#endif
++					}
++					PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
++					dm->dm_swat_table.single_ant_counter++;
++				}
++			}
++#if 0
++			/* PHYDM_DBG(dm,DBG_ANT_DIV, "is_result=(( %d ))\n",dm->dm_swat_table.rssi_ant_dect_result); */
++#endif
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\n\n\n",
++				  dm->dm_swat_table.dual_ant_counter,
++				  dm->dm_swat_table.single_ant_counter,
++				  dm->dm_swat_table.retry_counter,
++				  dm->dm_swat_table.aux_fail_detec_counter);
++
++			/* @2 recover the antenna setting */
++
++			if (dm->dm_swat_table.ANTB_ON == false)
++				odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, (dm_swat_table->swas_no_link_bk_reg948));
++
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "is_result=(( %d )), Recover  Reg[948]= (( %x ))\n\n",
++				  dm->dm_swat_table.rssi_ant_dect_result,
++				  dm_swat_table->swas_no_link_bk_reg948);
++		}
++
++		/* @Check state reset to default and wait for next time. */
++		dm_swat_table->swas_no_link_state = 0;
++		mgnt_info->bScanAntDetect = false;
++
++		return false;
++	}
++
++#else
++	return false;
++#endif
++
++	return false;
++}
++
++/* @1 [3. PSD method] ========================================================== */
++void odm_single_dual_antenna_detection_psd(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 channel_ori;
++	u8 initial_gain = 0x36;
++	u8 tone_idx;
++	u8 tone_lenth_1 = 7, tone_lenth_2 = 4;
++	u16 tone_idx_1[7] = {88, 104, 120, 8, 24, 40, 56};
++	u16 tone_idx_2[4] = {8, 24, 40, 56};
++	u32 psd_report_main[11] = {0}, psd_report_aux[11] = {0};
++	/* u8	tone_lenth_1=4, tone_lenth_2=2; */
++	/* u16	tone_idx_1[4]={88, 120, 24, 56}; */
++	/* u16	tone_idx_2[2]={ 24,  56}; */
++	/* u32	psd_report_main[6]={0}, psd_report_aux[6]={0}; */
++
++	u32 PSD_report_temp, max_psd_report_main = 0, max_psd_report_aux = 0;
++	u32 PSD_power_threshold;
++	u32 main_psd_result = 0, aux_psd_result = 0;
++	u32 regc50, reg948, regb2c, regc14, reg908;
++	u32 i = 0, test_num = 8;
++
++	if (dm->support_ic_type != ODM_RTL8723B)
++		return;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "%s============>\n", __func__);
++
++	/* @2 [ Backup Current RF/BB Settings ] */
++
++	channel_ori = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
++	reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
++	regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);
++	regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
++	regc14 = odm_get_bb_reg(dm, R_0xc14, MASKDWORD);
++	reg908 = odm_get_bb_reg(dm, R_0x908, MASKDWORD);
++
++	/* @2 [ setting for doing PSD function (CH4)] */
++	odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 0); /* @disable whole CCK block */
++	odm_write_1byte(dm, REG_TXPAUSE, 0xFF); /* Turn off TX  ->  Pause TX Queue */
++	odm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */
++
++	/* PHYTXON while loop */
++	odm_set_bb_reg(dm, R_0x908, MASKDWORD, 0x803);
++	while (odm_get_bb_reg(dm, R_0xdf4, BIT(6))) {
++		i++;
++		if (i > 1000000) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "Wait in %s() more than %d times!\n",
++				  __FUNCTION__, i);
++			break;
++		}
++	}
++
++	odm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain);
++	odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */
++	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable    88c[23:20]=0xf */
++	odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt	 */ /* Set PSD 128 ptss */
++	ODM_delay_us(3000);
++
++	/* @2 [ Doing PSD Function in (CH4)] */
++
++	/* @Antenna A */
++	PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant   (CH4)\n");
++	odm_set_bb_reg(dm, R_0x948, 0xfff, 0x200);
++	ODM_delay_us(10);
++	PHYDM_DBG(dm, DBG_ANT_DIV, "dbg\n");
++	for (i = 0; i < test_num; i++) {
++		for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
++			PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);
++			/* @if(  PSD_report_temp>psd_report_main[tone_idx]  ) */
++			psd_report_main[tone_idx] += PSD_report_temp;
++		}
++	}
++	/* @Antenna B */
++	PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant   (CH4)\n");
++	odm_set_bb_reg(dm, R_0x948, 0xfff, 0x280);
++	ODM_delay_us(10);
++	for (i = 0; i < test_num; i++) {
++		for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
++			PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);
++			/* @if(  PSD_report_temp>psd_report_aux[tone_idx]  ) */
++			psd_report_aux[tone_idx] += PSD_report_temp;
++		}
++	}
++	/* @2 [ Doing PSD Function in (CH8)] */
++
++	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable    88c[23:20]=0x0 */
++	ODM_delay_us(3000);
++
++	odm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain);
++	odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */
++
++	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable    88c[23:20]=0xf */
++	ODM_delay_us(3000);
++
++	/* @Antenna A */
++	PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant   (CH8)\n");
++	odm_set_bb_reg(dm, R_0x948, 0xfff, 0x200);
++	ODM_delay_us(10);
++
++	for (i = 0; i < test_num; i++) {
++		for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
++			PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);
++			/* @if(  PSD_report_temp>psd_report_main[tone_idx]  ) */
++			psd_report_main[tone_lenth_1 + tone_idx] += PSD_report_temp;
++		}
++	}
++
++	/* @Antenna B */
++	PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant   (CH8)\n");
++	odm_set_bb_reg(dm, R_0x948, 0xfff, 0x280);
++	ODM_delay_us(10);
++
++	for (i = 0; i < test_num; i++) {
++		for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
++			PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);
++			/* @if(  PSD_report_temp>psd_report_aux[tone_idx]  ) */
++			psd_report_aux[tone_lenth_1 + tone_idx] += PSD_report_temp;
++		}
++	}
++
++	/* @2 [ Calculate Result ] */
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "\nMain PSD Result: (ALL)\n");
++	for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
++		PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1),
++			  psd_report_main[tone_idx]);
++		main_psd_result += psd_report_main[tone_idx];
++		if (psd_report_main[tone_idx] > max_psd_report_main)
++			max_psd_report_main = psd_report_main[tone_idx];
++	}
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "--------------------------- \nTotal_Main= (( %d ))\n",
++		  main_psd_result);
++	PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Main = (( %d ))\n",
++		  max_psd_report_main);
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "\nAux PSD Result: (ALL)\n");
++	for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
++		PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1),
++			  psd_report_aux[tone_idx]);
++		aux_psd_result += psd_report_aux[tone_idx];
++		if (psd_report_aux[tone_idx] > max_psd_report_aux)
++			max_psd_report_aux = psd_report_aux[tone_idx];
++	}
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "--------------------------- \nTotal_Aux= (( %d ))\n",
++		  aux_psd_result);
++	PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Aux = (( %d ))\n\n",
++		  max_psd_report_aux);
++
++	/* @main_psd_result=main_psd_result-max_psd_report_main; */
++	/* @aux_psd_result=aux_psd_result-max_psd_report_aux; */
++	PSD_power_threshold = (main_psd_result * 7) >> 3;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n",
++		  main_psd_result, aux_psd_result, PSD_power_threshold);
++
++	/* @3 [ Dual Antenna ] */
++	if (aux_psd_result >= PSD_power_threshold) {
++		if (dm->dm_swat_table.ANTB_ON == false) {
++			dm->dm_swat_table.ANTA_ON = true;
++			dm->dm_swat_table.ANTB_ON = true;
++		}
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "odm_sw_ant_div_check_before_link(): Dual antenna\n");
++
++#if 0
++		/* set bt coexDM from 1ant coexDM to 2ant coexDM */
++		/* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */
++#endif
++
++		/* @Init antenna diversity */
++		dm->support_ability |= ODM_BB_ANT_DIV;
++		odm_ant_div_init(dm);
++	}
++	/* @3 [ Single Antenna ] */
++	else {
++		if (dm->dm_swat_table.ANTB_ON == true) {
++			dm->dm_swat_table.ANTA_ON = true;
++			dm->dm_swat_table.ANTB_ON = false;
++		}
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "odm_sw_ant_div_check_before_link(): Single antenna\n");
++	}
++
++	/* @2 [ Recover all parameters ] */
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, channel_ori);
++	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable    88c[23:20]=0x0 */
++	odm_set_bb_reg(dm, R_0xc50, 0x7f, regc50);
++
++	odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
++	odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
++
++	odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 1); /* @enable whole CCK block */
++	odm_write_1byte(dm, REG_TXPAUSE, 0x0); /* Turn on TX	 */ /* Resume TX Queue */
++	odm_set_bb_reg(dm, R_0xc14, MASKDWORD, regc14); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */
++	odm_set_bb_reg(dm, R_0x908, MASKDWORD, reg908);
++
++	return;
++}
++
++void odm_sw_ant_detect_init(void *dm_void)
++{
++#if (RTL8723B_SUPPORT == 1)
++
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
++
++	if (dm->support_ic_type != ODM_RTL8723B)
++		return;
++
++	/* @dm_swat_table->pre_antenna = MAIN_ANT; */
++	/* @dm_swat_table->cur_antenna = MAIN_ANT; */
++	dm_swat_table->swas_no_link_state = 0;
++	dm_swat_table->pre_aux_fail_detec = false;
++	dm_swat_table->swas_no_link_bk_reg948 = 0xff;
++
++#ifdef CONFIG_PSD_TOOL
++	phydm_psd_init(dm);
++#endif
++#endif
++}
++#endif
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_antdect.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_antdect.h
+new file mode 100644
+index 000000000..f7fc75f18
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_antdect.h
+@@ -0,0 +1,78 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDMANTDECT_H__
++#define __PHYDMANTDECT_H__
++
++#define ANTDECT_VERSION "2.1"
++
++#if (defined(CONFIG_ANT_DETECTION))
++/* @#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */
++/* @ANT Test */
++#define ANTTESTALL 0x00 /*@ant A or B will be Testing*/
++#define ANTTESTA 0x01 /*@ant A will be Testing*/
++#define ANTTESTB 0x02 /*@ant B will be testing*/
++
++#define MAX_ANTENNA_DETECTION_CNT 10
++
++struct _ANT_DETECTED_INFO {
++	boolean is_ant_detected;
++	u32 db_for_ant_a;
++	u32 db_for_ant_b;
++	u32 db_for_ant_o;
++};
++
++enum dm_swas {
++	antenna_a = 1,
++	antenna_b = 2,
++	antenna_max = 3,
++};
++
++/* @1 [1. Single Tone method] =================================================== */
++
++void odm_single_dual_antenna_default_setting(
++	void *dm_void);
++
++boolean
++odm_single_dual_antenna_detection(
++	void *dm_void,
++	u8 mode);
++
++/* @1 [2. Scan AP RSSI method] ================================================== */
++
++#define sw_ant_div_check_before_link odm_sw_ant_div_check_before_link
++
++boolean
++odm_sw_ant_div_check_before_link(
++	void *dm_void);
++
++/* @1 [3. PSD method] ========================================================== */
++
++void odm_single_dual_antenna_detection_psd(
++	void *dm_void);
++
++void odm_sw_ant_detect_init(void *dm_void);
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_antdiv.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_antdiv.c
+new file mode 100644
+index 000000000..e563d3f62
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_antdiv.c
+@@ -0,0 +1,6143 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*************************************************************
++ * include files
++ ************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++/*******************************************************
++ * when antenna test utility is on or some testing need to disable antenna
++ * diversity call this function to disable all ODM related mechanisms which
++ * will switch antenna.
++ *****************************************************
++ */
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++
++#if (RTL8721D_SUPPORT == 1)
++
++void odm_update_rx_idle_ant_8721d(void *dm_void, u8 ant, u32 default_ant,
++				  u32 optional_ant)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);
++	/*@Default RX*/
++	odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);
++	/*@Optional RX*/
++	odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);
++	/*@Default TX*/
++	fat_tab->rx_idle_ant = ant;
++}
++
++void odm_trx_hw_ant_div_init_8721d(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[8721D] AntDiv_Init =>  ant_div_type=[CG_TRX_HW_ANTDIV]\n");
++
++	/*@BT Coexistence*/
++	/*@keep antsel_map when GNT_BT = 1*/
++	odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
++	/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
++	odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
++	/* @Disable hw antsw & fast_train.antsw when BT TX/RX */
++	odm_set_bb_reg(dm, R_0xe64, 0xFFFF0000, 0x000c);
++
++	switch (dm->antdiv_gpio) {
++	case ANTDIV_GPIO_PA2PA4: {
++		PAD_CMD(_PA_2, ENABLE);
++		Pinmux_Config(_PA_2, PINMUX_FUNCTION_RFE);
++		PAD_CMD(_PA_4, ENABLE);
++		Pinmux_Config(_PA_4, PINMUX_FUNCTION_RFE);
++		break;
++	}
++	case ANTDIV_GPIO_PA5PA6: {
++		PAD_CMD(_PA_5, ENABLE);
++		Pinmux_Config(_PA_5, PINMUX_FUNCTION_RFE);
++		PAD_CMD(_PA_6, ENABLE);
++		Pinmux_Config(_PA_6, PINMUX_FUNCTION_RFE);
++		break;
++	}
++	case ANTDIV_GPIO_PA12PA13: {
++		PAD_CMD(_PA_12, ENABLE);
++		Pinmux_Config(_PA_12, PINMUX_FUNCTION_RFE);
++		PAD_CMD(_PA_13, ENABLE);
++		Pinmux_Config(_PA_13, PINMUX_FUNCTION_RFE);
++		break;
++	}
++	case ANTDIV_GPIO_PA14PA15: {
++		PAD_CMD(_PA_14, ENABLE);
++		Pinmux_Config(_PA_14, PINMUX_FUNCTION_RFE);
++		PAD_CMD(_PA_15, ENABLE);
++		Pinmux_Config(_PA_15, PINMUX_FUNCTION_RFE);
++		break;
++	}
++	case ANTDIV_GPIO_PA16PA17: {
++		PAD_CMD(_PA_16, ENABLE);
++		Pinmux_Config(_PA_16, PINMUX_FUNCTION_RFE);
++		PAD_CMD(_PA_17, ENABLE);
++		Pinmux_Config(_PA_17, PINMUX_FUNCTION_RFE);
++		break;
++	}
++	case ANTDIV_GPIO_PB1PB2: {
++		PAD_CMD(_PB_1, ENABLE);
++		Pinmux_Config(_PB_1, PINMUX_FUNCTION_RFE);
++		PAD_CMD(_PB_2, ENABLE);
++		Pinmux_Config(_PB_2, PINMUX_FUNCTION_RFE);
++		break;
++	}
++	case ANTDIV_GPIO_PB26PB29: {
++		PAD_CMD(_PB_26, ENABLE);
++		Pinmux_Config(_PB_26, PINMUX_FUNCTION_RFE);
++		PAD_CMD(_PB_29, ENABLE);
++		Pinmux_Config(_PB_29, PINMUX_FUNCTION_RFE);
++		break;
++	}
++	default: {
++	}
++	}
++
++	if (dm->antdiv_gpio == ANTDIV_GPIO_PA12PA13 ||
++	    dm->antdiv_gpio == ANTDIV_GPIO_PA14PA15 ||
++	    dm->antdiv_gpio == ANTDIV_GPIO_PA16PA17 ||
++	    dm->antdiv_gpio == ANTDIV_GPIO_PB1PB2) {
++		/* ANT_SEL_P, ANT_SEL_N */
++		odm_set_bb_reg(dm, R_0x930, 0xF, 8);
++		odm_set_bb_reg(dm, R_0x930, 0xF0, 8);
++		odm_set_bb_reg(dm, R_0x92c, BIT(1) | BIT(0), 2);
++		odm_set_bb_reg(dm, R_0x944, 0x00000003, 0x3);
++	} else if (dm->antdiv_gpio == ANTDIV_GPIO_PA2PA4 ||
++		   dm->antdiv_gpio == ANTDIV_GPIO_PA5PA6 ||
++		   dm->antdiv_gpio == ANTDIV_GPIO_PB26PB29) {
++		/* TRSW_P, TRSW_N */
++		odm_set_bb_reg(dm, R_0x930, 0xF00, 8);
++		odm_set_bb_reg(dm, R_0x930, 0xF000, 8);
++		odm_set_bb_reg(dm, R_0x92c, BIT(3) | BIT(2), 2);
++		odm_set_bb_reg(dm, R_0x944, 0x0000000C, 0x3);
++	}
++
++	u32 sysreg208 = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0);
++
++	sysreg208 |= BIT(28);
++	HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0, sysreg208);
++
++	u32 sysreg344 =
++		      HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL);
++
++	sysreg344 |= BIT(9);
++	HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344);
++
++	u32 sysreg280 = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0);
++
++	sysreg280 |= 0x7;
++	HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0, sysreg280);
++
++	sysreg344 |= BIT(8);
++	HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344);
++
++	sysreg344 |= BIT(0);
++	HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344);
++
++	odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
++	odm_set_bb_reg(dm, R_0x804, 0xF00, 1); /* r_keep_rfpin */
++
++	/*PTA setting: WL_BB_SEL_BTG_TRXG_anta,  (1: HW CTRL  0: SW CTRL)*/
++	/*odm_set_bb_reg(dm, R_0x948, BIT6, 0);*/
++	/*odm_set_bb_reg(dm, R_0x948, BIT8, 0);*/
++	/*@GNT_WL tx*/
++	odm_set_bb_reg(dm, R_0x950, BIT(29), 0);
++
++	/*@Mapping Table*/
++	odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
++	odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
++	/* odm_set_bb_reg(dm, R_0x864, BIT5|BIT4|BIT3, 0); */
++	/* odm_set_bb_reg(dm, R_0x864, BIT8|BIT7|BIT6, 1); */
++
++	/* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */
++	odm_set_bb_reg(dm, R_0xccc, BIT(12), 0);
++	/* @Low-to-High threshold for WLBB_SEL_RF_ON */
++	/*when OFDM enable */
++	odm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01);
++	/* @High-to-Low threshold for WLBB_SEL_RF_ON */
++	/* when OFDM enable */
++	odm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0);
++	/* @b Low-to-High threshold for WLBB_SEL_RF_ON*/
++	/*when OFDM disable ( only CCK ) */
++	odm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06);
++	/* @High-to-Low threshold for WLBB_SEL_RF_ON*/
++	/* when OFDM disable ( only CCK ) */
++	odm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00);
++
++	/*OFDM HW AntDiv Parameters*/
++	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0);
++	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00);
++	odm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04);
++
++	/*@CCK HW AntDiv Parameters*/
++	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
++	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 0);
++	odm_set_bb_reg(dm, R_0xaa8, BIT(8), 0);
++
++	odm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf);
++	odm_set_bb_reg(dm, R_0xa14, 0x1F, 0x8);
++	odm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1);
++	odm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0);
++	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1);
++
++	/*@disable antenna training	*/
++	odm_set_bb_reg(dm, R_0xe08, BIT(16), 0);
++	odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
++}
++#endif
++
++void odm_stop_antenna_switch_dm(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	/* @disable ODM antenna diversity */
++	dm->support_ability &= ~ODM_BB_ANT_DIV;
++	if (fat_tab->div_path_type == ANT_PATH_A)
++		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
++	else if (fat_tab->div_path_type == ANT_PATH_B)
++		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
++	else if (fat_tab->div_path_type == ANT_PATH_AB)
++		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
++	odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
++	PHYDM_DBG(dm, DBG_ANT_DIV, "STOP Antenna Diversity\n");
++}
++
++void phydm_enable_antenna_diversity(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	dm->support_ability |= ODM_BB_ANT_DIV;
++	dm->antdiv_select = 0;
++	PHYDM_DBG(dm, DBG_ANT_DIV, "AntDiv is enabled & Re-Init AntDiv\n");
++	odm_antenna_diversity_init(dm);
++}
++
++void odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C,...*/)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type == ODM_RTL8723B) {
++		if (ant_setting == 0) /* @ant A*/
++			odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000000);
++		else if (ant_setting == 1)
++			odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000280);
++	} else if (dm->support_ic_type == ODM_RTL8723D) {
++		if (ant_setting == 0) /* @ant A*/
++			odm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0000);
++		else if (ant_setting == 1)
++			odm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0280);
++	}
++}
++
++/* ****************************************************** */
++
++void odm_sw_ant_div_rest_after_link(void *dm_void)
++{
++#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	u32 i;
++
++	if (dm->ant_div_type == S0S1_SW_ANTDIV) {
++		swat_tab->try_flag = SWAW_STEP_INIT;
++		swat_tab->rssi_trying = 0;
++		swat_tab->double_chk_flag = 0;
++		fat_tab->rx_idle_ant = MAIN_ANT;
++
++		for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
++			phydm_antdiv_reset_statistic(dm, i);
++	}
++
++#endif
++}
++
++void phydm_n_on_off(void *dm_void, u8 swch, u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	if (path == ANT_PATH_A) {
++		odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
++	} else if (path == ANT_PATH_B) {
++		odm_set_bb_reg(dm, R_0xc58, BIT(7), swch);
++	} else if (path == ANT_PATH_AB) {
++		odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
++		odm_set_bb_reg(dm, R_0xc58, BIT(7), swch);
++	}
++	odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
++#if (RTL8723D_SUPPORT == 1)
++	/*@Mingzhi 2017-05-08*/
++	if (dm->support_ic_type == ODM_RTL8723D) {
++		if (swch == ANTDIV_ON) {
++			odm_set_bb_reg(dm, R_0xce0, BIT(1), 1);
++			odm_set_bb_reg(dm, R_0x948, BIT(6), 1);
++			/*@1:HW ctrl  0:SW ctrl*/
++		} else {
++			odm_set_bb_reg(dm, R_0xce0, BIT(1), 0);
++			odm_set_bb_reg(dm, R_0x948, BIT(6), 0);
++			/*@1:HW ctrl  0:SW ctrl*/
++		}
++	}
++#endif
++}
++
++void phydm_ac_on_off(void *dm_void, u8 swch, u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	if (dm->support_ic_type & ODM_RTL8812) {
++		odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
++		/* OFDM AntDiv function block enable */
++		odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
++		/* @CCK AntDiv function block enable */
++	} else if (dm->support_ic_type & ODM_RTL8822B) {
++		odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
++		odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
++		if (path == ANT_PATH_A) {
++			odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
++		} else if (path == ANT_PATH_B) {
++			odm_set_bb_reg(dm, R_0xe50, BIT(7), swch);
++		} else if (path == ANT_PATH_AB) {
++			odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
++			odm_set_bb_reg(dm, R_0xe50, BIT(7), swch);
++		}
++	} else {
++		odm_set_bb_reg(dm, R_0x8d4, BIT(24), swch);
++		/* OFDM AntDiv function block enable */
++
++		if (dm->cut_version >= ODM_CUT_C &&
++		    dm->support_ic_type == ODM_RTL8821 &&
++		    dm->ant_div_type != S0S1_SW_ANTDIV) {
++			PHYDM_DBG(dm, DBG_ANT_DIV, "(Turn %s) CCK HW-AntDiv\n",
++				  (swch == ANTDIV_ON) ? "ON" : "OFF");
++			odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
++			odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
++			/* @CCK AntDiv function block enable */
++		} else if (dm->support_ic_type == ODM_RTL8821C) {
++			PHYDM_DBG(dm, DBG_ANT_DIV, "(Turn %s) CCK HW-AntDiv\n",
++				  (swch == ANTDIV_ON) ? "ON" : "OFF");
++			odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
++			odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
++			/* @CCK AntDiv function block enable */
++		}
++	}
++}
++
++void phydm_jgr3_on_off(void *dm_void, u8 swch, u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	odm_set_bb_reg(dm, R_0x8a0, BIT(17), swch);
++	/* OFDM AntDiv function block enable */
++	odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
++	/* @CCK AntDiv function block enable */
++}
++
++void odm_ant_div_on_off(void *dm_void, u8 swch, u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	if (fat_tab->ant_div_on_off != swch) {
++		if (dm->ant_div_type == S0S1_SW_ANTDIV)
++			return;
++
++		if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "(( Turn %s )) N-Series HW-AntDiv block\n",
++				  (swch == ANTDIV_ON) ? "ON" : "OFF");
++			phydm_n_on_off(dm, swch, path);
++
++		} else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "(( Turn %s )) AC-Series HW-AntDiv block\n",
++				  (swch == ANTDIV_ON) ? "ON" : "OFF");
++			phydm_ac_on_off(dm, swch, path);
++		} else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "(( Turn %s )) JGR3 HW-AntDiv block\n",
++				  (swch == ANTDIV_ON) ? "ON" : "OFF");
++			phydm_jgr3_on_off(dm, swch, path);
++		}
++	}
++	fat_tab->ant_div_on_off = swch;
++}
++
++void odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	u8 enable;
++
++	if (fat_tab->b_fix_tx_ant == NO_FIX_TX_ANT)
++		enable = (swch == TX_BY_DESC) ? 1 : 0;
++	else
++		enable = 0; /*@Force TX by Reg*/
++
++	if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
++		if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
++			odm_set_bb_reg(dm, R_0x80c, BIT(21), enable);
++		else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT)
++			odm_set_bb_reg(dm, R_0x900, BIT(18), enable);
++		else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT)
++			odm_set_bb_reg(dm, R_0x186c, BIT(1), enable);
++
++		PHYDM_DBG(dm, DBG_ANT_DIV, "[AntDiv] TX_Ant_BY (( %s ))\n",
++			  (enable == TX_BY_DESC) ? "DESC" : "REG");
++	}
++}
++
++void phydm_antdiv_reset_statistic(void *dm_void, u32 macid)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	fat_tab->main_sum[macid] = 0;
++	fat_tab->aux_sum[macid] = 0;
++	fat_tab->main_cnt[macid] = 0;
++	fat_tab->aux_cnt[macid] = 0;
++	fat_tab->main_sum_cck[macid] = 0;
++	fat_tab->aux_sum_cck[macid] = 0;
++	fat_tab->main_cnt_cck[macid] = 0;
++	fat_tab->aux_cnt_cck[macid] = 0;
++}
++
++void phydm_fast_training_enable(void *dm_void, u8 swch)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 enable;
++
++	if (swch == FAT_ON)
++		enable = 1;
++	else
++		enable = 0;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "Fast ant Training_en = ((%d))\n", enable);
++
++	if (dm->support_ic_type == ODM_RTL8188E) {
++		odm_set_bb_reg(dm, R_0xe08, BIT(16), enable);
++			/*@enable fast training*/
++	} else if (dm->support_ic_type == ODM_RTL8192E) {
++		odm_set_bb_reg(dm, R_0xb34, BIT(28), enable);
++			/*@enable fast training (path-A)*/
++#if 0
++		odm_set_bb_reg(dm, R_0xb34, BIT(29), enable);
++			/*enable fast training (path-B)*/
++#endif
++	} else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8822B)) {
++		odm_set_bb_reg(dm, R_0x900, BIT(19), enable);
++			/*@enable fast training */
++	}
++}
++
++void phydm_keep_rx_ack_ant_by_tx_ant_time(void *dm_void, u32 time)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	/* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/
++	if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
++		odm_set_bb_reg(dm, R_0xe20, 0xf00000, time);
++	else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT)
++		odm_set_bb_reg(dm, R_0x818, 0xf00000, time);
++}
++
++void phydm_update_rx_idle_ac(void *dm_void, u8 ant, u32 default_ant,
++			     u32 optional_ant, u32 default_tx_ant)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	u16 value16 = odm_read_2byte(dm, ODM_REG_TRMUX_11AC + 2);
++	/* @2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to  */
++	/* @prevnt incorrect 0xc08 bit0-15.We still not know why it is changed*/
++	value16 &= ~(BIT(11) | BIT(10) | BIT(9) | BIT(8) | BIT(7) | BIT(6) |
++		   BIT(5) | BIT(4) | BIT(3));
++	value16 |= ((u16)default_ant << 3);
++	value16 |= ((u16)optional_ant << 6);
++	value16 |= ((u16)default_tx_ant << 9);
++	odm_write_2byte(dm, ODM_REG_TRMUX_11AC + 2, value16);
++#if 0
++	odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0x380000, default_ant);
++		/* @Default RX */
++	odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0x1c00000, optional_ant);
++		/* Optional RX */
++	odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0xe000000, default_ant);
++		/* @Default TX */
++#endif
++}
++
++void phydm_update_rx_idle_n(void *dm_void, u8 ant, u32 default_ant,
++			    u32 optional_ant, u32 default_tx_ant)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 value32;
++
++	if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F)) {
++		odm_set_bb_reg(dm, R_0xb38, 0x38, default_ant);
++			/* @Default RX */
++		odm_set_bb_reg(dm, R_0xb38, 0x1c0, optional_ant);
++			/* Optional RX */
++		odm_set_bb_reg(dm, R_0x860, 0x7000, default_ant);
++			/* @Default TX */
++#if (RTL8723B_SUPPORT == 1)
++	} else if (dm->support_ic_type == ODM_RTL8723B) {
++		value32 = odm_get_bb_reg(dm, R_0x948, 0xFFF);
++
++		if (value32 != 0x280)
++			odm_update_rx_idle_ant_8723b(dm, ant, default_ant,
++						     optional_ant);
++		else
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n");
++#endif
++
++#if (RTL8723D_SUPPORT == 1) /*@Mingzhi 2017-05-08*/
++	} else if (dm->support_ic_type == ODM_RTL8723D) {
++		phydm_set_tx_ant_pwr_8723d(dm, ant);
++		odm_update_rx_idle_ant_8723d(dm, ant, default_ant,
++					     optional_ant);
++#endif
++
++#if (RTL8721D_SUPPORT == 1)
++	} else if (dm->support_ic_type == ODM_RTL8721D) {
++		odm_update_rx_idle_ant_8721d(dm, ant, default_ant,
++					     optional_ant);
++#endif
++	} else {
++/*@8188E & 8188F*/
++/*@		if (dm->support_ic_type == ODM_RTL8723D) {*/
++/*#if (RTL8723D_SUPPORT == 1)*/
++/*			phydm_set_tx_ant_pwr_8723d(dm, ant);*/
++/*#endif*/
++/*		}*/
++#if (RTL8188F_SUPPORT == 1)
++		if (dm->support_ic_type == ODM_RTL8188F)
++			phydm_update_rx_idle_antenna_8188F(dm, default_ant);
++#endif
++
++		odm_set_bb_reg(dm, R_0x864, 0x38, default_ant);/*@Default RX*/
++		odm_set_bb_reg(dm, R_0x864, 0x1c0, optional_ant);
++			/*Optional RX*/
++		odm_set_bb_reg(dm, R_0x860, 0x7000, default_tx_ant);
++			/*@Default TX*/
++	}
++}
++
++void phydm_update_rx_idle_jgr3(void *dm_void, u8 ant, u32 default_ant,
++			       u32 optional_ant, u32 default_tx_ant)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 value32;
++
++	odm_set_bb_reg(dm, R_0x1884, 0xf0, default_ant);/*@Default RX*/
++	odm_set_bb_reg(dm, R_0x1884, 0xf00, optional_ant);
++		/*Optional RX*/
++	odm_set_bb_reg(dm, R_0x1884, 0xf000, default_tx_ant);
++		/*@Default TX*/
++}
++void odm_update_rx_idle_ant(void *dm_void, u8 ant)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	u32 default_ant, optional_ant, value32, default_tx_ant;
++
++	if (fat_tab->rx_idle_ant != ant) {
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ Update Rx-Idle-ant ] rx_idle_ant =%s\n",
++			  (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
++
++		if (!(dm->support_ic_type & ODM_RTL8723B))
++			fat_tab->rx_idle_ant = ant;
++
++		if (ant == MAIN_ANT) {
++			default_ant = ANT1_2G;
++			optional_ant = ANT2_2G;
++		} else {
++			default_ant = ANT2_2G;
++			optional_ant = ANT1_2G;
++		}
++
++		if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
++			default_tx_ant = (fat_tab->b_fix_tx_ant ==
++					 FIX_TX_AT_MAIN) ? 0 : 1;
++		else
++			default_tx_ant = default_ant;
++
++		if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
++			phydm_update_rx_idle_n(dm, ant, default_ant,
++					       optional_ant, default_tx_ant);
++		} else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
++			phydm_update_rx_idle_ac(dm, ant, default_ant,
++						optional_ant, default_tx_ant);
++		} else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT) {
++			phydm_update_rx_idle_jgr3(dm, ant, default_ant,
++						  optional_ant, default_tx_ant);
++		}
++		/*PathA Resp Tx*/
++		if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B |
++		    ODM_RTL8814A))
++			odm_set_mac_reg(dm, R_0x6d8, 0x7, default_tx_ant);
++		else if (dm->support_ic_type == ODM_RTL8188E)
++			odm_set_mac_reg(dm, R_0x6d8, 0xc0, default_tx_ant);
++		else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT)
++			odm_set_mac_reg(dm, R_0x6f8, 0xf, default_tx_ant);
++		else
++			odm_set_mac_reg(dm, R_0x6d8, 0x700, default_tx_ant);
++
++	} else { /* @fat_tab->rx_idle_ant == ant */
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ Stay in Ori-ant ]  rx_idle_ant =%s\n",
++			  (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
++		fat_tab->rx_idle_ant = ant;
++	}
++}
++
++void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	u32 default_ant, optional_ant, value32, default_tx_ant;
++
++	if (fat_tab->rx_idle_ant2 != ant) {
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ Update Rx-Idle-ant2 ] rx_idle_ant2 =%s\n",
++			  (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
++		if (ant == MAIN_ANT) {
++			default_ant = ANT1_2G;
++			optional_ant = ANT2_2G;
++		} else {
++			default_ant = ANT2_2G;
++			optional_ant = ANT1_2G;
++		}
++
++		if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
++			default_tx_ant = (fat_tab->b_fix_tx_ant ==
++					  FIX_TX_AT_MAIN) ? 0 : 1;
++		else
++			default_tx_ant = default_ant;
++		if (dm->support_ic_type & ODM_RTL8822B) {
++			u16 v16 = odm_read_2byte(dm, ODM_REG_ANT_11AC_B + 2);
++
++			v16 &= ~(0xff8);/*0xE08[11:3]*/
++			v16 |= ((u16)default_ant << 3);
++			v16 |= ((u16)optional_ant << 6);
++			v16 |= ((u16)default_tx_ant << 9);
++			odm_write_2byte(dm, ODM_REG_ANT_11AC_B + 2, v16);
++			odm_set_mac_reg(dm, R_0x6d8, 0x38, default_tx_ant);
++			/*PathB Resp Tx*/
++		}
++	} else {
++		/* fat_tab->rx_idle_ant2 == ant */
++		PHYDM_DBG(dm, DBG_ANT_DIV, "[Stay Ori Ant] rx_idle_ant2 = %s\n",
++			  (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
++		fat_tab->rx_idle_ant2 = ant;
++	}
++}
++
++void phydm_set_antdiv_val(void *dm_void, u32 *val_buf,	u8 val_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (val_len != 1) {
++		PHYDM_DBG(dm, ODM_COMP_API, "[Error][antdiv]Need val_len=1\n");
++		return;
++	}
++
++	odm_update_rx_idle_ant(dm, (u8)(*val_buf));
++}
++
++void odm_update_tx_ant(void *dm_void, u8 ant, u32 mac_id)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	u8 tx_ant;
++
++	if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
++		ant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ?
++		       MAIN_ANT : AUX_ANT;
++
++	if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
++		tx_ant = ant;
++	else {
++		if (ant == MAIN_ANT)
++			tx_ant = ANT1_2G;
++		else
++			tx_ant = ANT2_2G;
++	}
++
++	fat_tab->antsel_a[mac_id] = tx_ant & BIT(0);
++	fat_tab->antsel_b[mac_id] = (tx_ant & BIT(1)) >> 1;
++	fat_tab->antsel_c[mac_id] = (tx_ant & BIT(2)) >> 2;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[Set TX-DESC value]: mac_id:(( %d )),  tx_ant = (( %s ))\n",
++		  mac_id, (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
++#if 0
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "antsel_tr_mux=(( 3'b%d%d%d ))\n",
++		  fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
++		  fat_tab->antsel_a[mac_id]);
++#endif
++}
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++
++void odm_bdc_init(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "\n[ BDC Initialization......]\n");
++	dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
++	dm_bdc_table->bdc_mode = BDC_MODE_NULL;
++	dm_bdc_table->bdc_try_flag = 0;
++	dm_bdc_table->bd_ccoex_type_wbfer = 0;
++	dm->bdc_holdstate = 0xff;
++
++	if (dm->support_ic_type == ODM_RTL8192E) {
++		odm_set_bb_reg(dm, R_0xd7c, 0x0FFFFFFF, 0x1081008);
++		odm_set_bb_reg(dm, R_0xd80, 0x0FFFFFFF, 0);
++	} else if (dm->support_ic_type == ODM_RTL8812) {
++		odm_set_bb_reg(dm, R_0x9b0, 0x0FFFFFFF, 0x1081008);
++			/* @0x9b0[30:0] = 01081008 */
++		odm_set_bb_reg(dm, R_0x9b4, 0x0FFFFFFF, 0);
++			/* @0x9b4[31:0] = 00000000 */
++	}
++}
++
++void odm_CSI_on_off(
++	void *dm_void,
++	u8 CSI_en)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	if (CSI_en == CSI_ON) {
++		if (dm->support_ic_type == ODM_RTL8192E)
++			odm_set_mac_reg(dm, R_0xd84, BIT(11), 1);
++				/* @0xd84[11]=1 */
++		else if (dm->support_ic_type == ODM_RTL8812)
++			odm_set_mac_reg(dm, R_0x9b0, BIT(31), 1);
++				/* @0x9b0[31]=1 */
++
++	} else if (CSI_en == CSI_OFF) {
++		if (dm->support_ic_type == ODM_RTL8192E)
++			odm_set_mac_reg(dm, R_0xd84, BIT(11), 0);
++				/* @0xd84[11]=0 */
++		else if (dm->support_ic_type == ODM_RTL8812)
++			odm_set_mac_reg(dm, R_0x9b0, BIT(31), 0);
++				/* @0x9b0[31]=0 */
++	}
++}
++
++void odm_bd_ccoex_type_with_bfer_client(
++	void *dm_void,
++	u8 swch)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
++	u8 bd_ccoex_type_wbfer;
++
++	if (swch == DIVON_CSIOFF) {
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[BDCcoexType: 1] {DIV,CSI} ={1,0}\n");
++		bd_ccoex_type_wbfer = 1;
++
++		if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {
++			odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
++			odm_CSI_on_off(dm, CSI_OFF);
++			dm_bdc_table->bd_ccoex_type_wbfer = 1;
++		}
++	} else if (swch == DIVOFF_CSION) {
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[BDCcoexType: 2] {DIV,CSI} ={0,1}\n");
++		bd_ccoex_type_wbfer = 2;
++
++		if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {
++			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
++			odm_CSI_on_off(dm, CSI_ON);
++			dm_bdc_table->bd_ccoex_type_wbfer = 2;
++		}
++	}
++}
++
++void odm_bf_ant_div_mode_arbitration(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
++	u8 current_bdc_mode;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	PHYDM_DBG(dm, DBG_ANT_DIV, "\n");
++
++	/* @2 mode 1 */
++	if (dm_bdc_table->num_txbfee_client != 0 &&
++	    dm_bdc_table->num_txbfer_client == 0) {
++		current_bdc_mode = BDC_MODE_1;
++
++		if (current_bdc_mode != dm_bdc_table->bdc_mode) {
++			dm_bdc_table->bdc_mode = BDC_MODE_1;
++			odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
++			dm_bdc_table->bdc_rx_idle_update_counter = 1;
++			PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode1 ))\n");
++		}
++
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[Antdiv + BF coextance mode] : (( Mode1 ))\n");
++	}
++	/* @2 mode 2 */
++	else if ((dm_bdc_table->num_txbfee_client == 0) &&
++		 (dm_bdc_table->num_txbfer_client != 0)) {
++		current_bdc_mode = BDC_MODE_2;
++
++		if (current_bdc_mode != dm_bdc_table->bdc_mode) {
++			dm_bdc_table->bdc_mode = BDC_MODE_2;
++			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
++			dm_bdc_table->bdc_try_flag = 0;
++			PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode2 ))\n");
++		}
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[Antdiv + BF coextance mode] : (( Mode2 ))\n");
++	}
++	/* @2 mode 3 */
++	else if ((dm_bdc_table->num_txbfee_client != 0) &&
++		 (dm_bdc_table->num_txbfer_client != 0)) {
++		current_bdc_mode = BDC_MODE_3;
++
++		if (current_bdc_mode != dm_bdc_table->bdc_mode) {
++			dm_bdc_table->bdc_mode = BDC_MODE_3;
++			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
++			dm_bdc_table->bdc_try_flag = 0;
++			dm_bdc_table->bdc_rx_idle_update_counter = 1;
++			PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode3 ))\n");
++		}
++
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[Antdiv + BF coextance mode] : (( Mode3 ))\n");
++	}
++	/* @2 mode 4 */
++	else if ((dm_bdc_table->num_txbfee_client == 0) &&
++		 (dm_bdc_table->num_txbfer_client == 0)) {
++		current_bdc_mode = BDC_MODE_4;
++
++		if (current_bdc_mode != dm_bdc_table->bdc_mode) {
++			dm_bdc_table->bdc_mode = BDC_MODE_4;
++			odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
++			PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode4 ))\n");
++		}
++
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[Antdiv + BF coextance mode] : (( Mode4 ))\n");
++	}
++#endif
++}
++
++void odm_div_train_state_setting(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "\n*****[S T A R T ]*****  [2-0. DIV_TRAIN_STATE]\n");
++	dm_bdc_table->bdc_try_counter = 2;
++	dm_bdc_table->bdc_try_flag = 1;
++	dm_bdc_table->BDC_state = bdc_bfer_train_state;
++	odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
++}
++
++void odm_bd_ccoex_bfee_rx_div_arbitration(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
++	boolean stop_bf_flag;
++	u8 bdc_active_mode;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "***{ num_BFee,  num_BFer, num_client}  = (( %d  ,  %d  ,  %d))\n",
++		  dm_bdc_table->num_txbfee_client,
++		  dm_bdc_table->num_txbfer_client, dm_bdc_table->num_client);
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "***{ num_BF_tars,  num_DIV_tars }  = ((  %d  ,  %d ))\n",
++		  dm_bdc_table->num_bf_tar, dm_bdc_table->num_div_tar);
++
++	/* @2 [ MIB control ] */
++	if (dm->bdc_holdstate == 2) {
++		odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
++		dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
++		PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ BF STATE]\n");
++		return;
++	} else if (dm->bdc_holdstate == 1) {
++		dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
++		odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
++		PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n");
++		return;
++	}
++
++	/* @------------------------------------------------------------ */
++
++	/* @2 mode 2 & 3 */
++	if (dm_bdc_table->bdc_mode == BDC_MODE_2 ||
++	    dm_bdc_table->bdc_mode == BDC_MODE_3) {
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "\n{ Try_flag,  Try_counter } = {  %d , %d  }\n",
++			  dm_bdc_table->bdc_try_flag,
++			  dm_bdc_table->bdc_try_counter);
++		PHYDM_DBG(dm, DBG_ANT_DIV, "BDCcoexType = (( %d ))\n\n",
++			  dm_bdc_table->bd_ccoex_type_wbfer);
++
++		/* @All Client have Bfer-Cap------------------------------- */
++		if (dm_bdc_table->num_txbfer_client == dm_bdc_table->num_client) {
++			/* @BFer STA Only?: yes */
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "BFer STA only?  (( Yes ))\n");
++			dm_bdc_table->bdc_try_flag = 0;
++			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
++			odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
++			return;
++		} else
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "BFer STA only?  (( No ))\n");
++		if (dm_bdc_table->is_all_bf_sta_idle == false && dm_bdc_table->is_all_div_sta_idle == true) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "All DIV-STA are idle, but BF-STA not\n");
++			dm_bdc_table->bdc_try_flag = 0;
++			dm_bdc_table->BDC_state = bdc_bfer_train_state;
++			odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
++			return;
++		} else if (dm_bdc_table->is_all_bf_sta_idle == true && dm_bdc_table->is_all_div_sta_idle == false) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "All BF-STA are idle, but DIV-STA not\n");
++			dm_bdc_table->bdc_try_flag = 0;
++			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
++			odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
++			return;
++		}
++
++		/* Select active mode-------------------------------------- */
++		if (dm_bdc_table->num_bf_tar == 0) { /* Selsect_1,  Selsect_2 */
++			if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "Select active mode (( 1 ))\n");
++				dm_bdc_table->bdc_active_mode = 1;
++			} else {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "Select active mode  (( 2 ))\n");
++				dm_bdc_table->bdc_active_mode = 2;
++			}
++			dm_bdc_table->bdc_try_flag = 0;
++			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
++			odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
++			return;
++		} else { /* num_bf_tar > 0 */
++			if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "Select active mode (( 3 ))\n");
++				dm_bdc_table->bdc_active_mode = 3;
++				dm_bdc_table->bdc_try_flag = 0;
++				dm_bdc_table->BDC_state = bdc_bfer_train_state;
++				odm_bd_ccoex_type_with_bfer_client(dm,
++								   DIVOFF_CSION)
++								   ;
++				return;
++			} else { /* Selsect_4 */
++				bdc_active_mode = 4;
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "Select active mode (( 4 ))\n");
++
++				if (bdc_active_mode != dm_bdc_table->bdc_active_mode) {
++					dm_bdc_table->bdc_active_mode = 4;
++					PHYDM_DBG(dm, DBG_ANT_DIV, "Change to active mode (( 4 ))  &  return!!!\n");
++					return;
++				}
++			}
++		}
++
++#if 1
++		if (dm->bdc_holdstate == 0xff) {
++			dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
++			odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
++			PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n");
++			return;
++		}
++#endif
++
++		/* @Does Client number changed ? ------------------------------- */
++		if (dm_bdc_table->num_client != dm_bdc_table->pre_num_client) {
++			dm_bdc_table->bdc_try_flag = 0;
++			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[  The number of client has been changed !!!]   return to (( BDC_DIV_TRAIN_STATE ))\n");
++		}
++		dm_bdc_table->pre_num_client = dm_bdc_table->num_client;
++
++		if (dm_bdc_table->bdc_try_flag == 0) {
++			/* @2 DIV_TRAIN_STATE (mode 2-0) */
++			if (dm_bdc_table->BDC_state == BDC_DIV_TRAIN_STATE)
++				odm_div_train_state_setting(dm);
++			/* @2 BFer_TRAIN_STATE (mode 2-1) */
++			else if (dm_bdc_table->BDC_state == bdc_bfer_train_state) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "*****[2-1. BFer_TRAIN_STATE ]*****\n");
++
++#if 0
++				/* @if(dm_bdc_table->num_bf_tar==0) */
++				/* @{ */
++				/*	PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist?  : (( No )),   [ bdc_bfer_train_state ] >> [BDC_DIV_TRAIN_STATE]\n"); */
++				/*	odm_div_train_state_setting( dm); */
++				/* @} */
++				/* else */ /* num_bf_tar != 0 */
++				/* @{ */
++#endif
++				dm_bdc_table->bdc_try_counter = 2;
++				dm_bdc_table->bdc_try_flag = 1;
++				dm_bdc_table->BDC_state = BDC_DECISION_STATE;
++				odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "BF_tars exist?  : (( Yes )),   [ bdc_bfer_train_state ] >> [BDC_DECISION_STATE]\n");
++				/* @} */
++			}
++			/* @2 DECISION_STATE (mode 2-2) */
++			else if (dm_bdc_table->BDC_state == BDC_DECISION_STATE) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "*****[2-2. DECISION_STATE]*****\n");
++#if 0
++				/* @if(dm_bdc_table->num_bf_tar==0) */
++				/* @{ */
++				/*	ODM_AntDiv_Printk(("BF_tars exist?  : (( No )),   [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); */
++				/*	odm_div_train_state_setting( dm); */
++				/* @} */
++				/* else */ /* num_bf_tar != 0 */
++				/* @{ */
++#endif
++				if (dm_bdc_table->BF_pass == false || dm_bdc_table->DIV_pass == false)
++					stop_bf_flag = true;
++				else
++					stop_bf_flag = false;
++
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "BF_tars exist?  : (( Yes )),  {BF_pass, DIV_pass, stop_bf_flag }  = { %d, %d, %d }\n",
++					  dm_bdc_table->BF_pass,
++					  dm_bdc_table->DIV_pass, stop_bf_flag);
++
++				if (stop_bf_flag == true) { /* @DIV_en */
++					dm_bdc_table->bdc_hold_counter = 10; /* @20 */
++					odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
++					dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
++					PHYDM_DBG(dm, DBG_ANT_DIV, "[ stop_bf_flag= ((true)),   BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE]\n");
++				} else { /* @BF_en */
++					dm_bdc_table->bdc_hold_counter = 10; /* @20 */
++					odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
++					dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
++					PHYDM_DBG(dm, DBG_ANT_DIV, "[stop_bf_flag= ((false)),   BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE]\n");
++				}
++				/* @} */
++			}
++			/* @2 BF-HOLD_STATE (mode 2-3) */
++			else if (dm_bdc_table->BDC_state == BDC_BF_HOLD_STATE) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "*****[2-3. BF_HOLD_STATE ]*****\n");
++
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "bdc_hold_counter = (( %d ))\n",
++					  dm_bdc_table->bdc_hold_counter);
++
++				if (dm_bdc_table->bdc_hold_counter == 1) {
++					PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n");
++					odm_div_train_state_setting(dm);
++				} else {
++					dm_bdc_table->bdc_hold_counter--;
++
++#if 0
++					/* @if(dm_bdc_table->num_bf_tar==0) */
++					/* @{ */
++					/*	PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist?  : (( No )),   [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"); */
++					/*	odm_div_train_state_setting( dm); */
++					/* @} */
++					/* else */ /* num_bf_tar != 0 */
++					/* @{ */
++					/* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist?  : (( Yes ))\n"); */
++#endif
++					dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
++					odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
++					PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE]\n");
++					/* @} */
++				}
++			}
++			/* @2 DIV-HOLD_STATE (mode 2-4) */
++			else if (dm_bdc_table->BDC_state == BDC_DIV_HOLD_STATE) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "*****[2-4. DIV_HOLD_STATE ]*****\n");
++
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "bdc_hold_counter = (( %d ))\n",
++					  dm_bdc_table->bdc_hold_counter);
++
++				if (dm_bdc_table->bdc_hold_counter == 1) {
++					PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n");
++					odm_div_train_state_setting(dm);
++				} else {
++					dm_bdc_table->bdc_hold_counter--;
++					dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
++					odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
++					PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE]\n");
++				}
++			}
++
++		} else if (dm_bdc_table->bdc_try_flag == 1) {
++			/* @2 Set Training counter */
++			if (dm_bdc_table->bdc_try_counter > 1) {
++				dm_bdc_table->bdc_try_counter--;
++				if (dm_bdc_table->bdc_try_counter == 1)
++					dm_bdc_table->bdc_try_flag = 0;
++
++				PHYDM_DBG(dm, DBG_ANT_DIV, "Training !!\n");
++				/* return ; */
++			}
++		}
++	}
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "\n[end]\n");
++
++#endif /* @#if(DM_ODM_SUPPORT_TYPE  == ODM_AP) */
++}
++
++#endif
++#endif /* @#ifdef PHYDM_BEAMFORMING_SUPPORT*/
++
++#if (RTL8188E_SUPPORT == 1)
++
++void odm_rx_hw_ant_div_init_88e(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 value32;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
++
++	/* @MAC setting */
++	value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
++	odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD,
++			value32 | (BIT(23) | BIT(25)));
++			/* Reg4C[25]=1, Reg4C[23]=1 for pin output */
++	/* Pin Settings */
++	odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
++			/* reg870[8]=1'b0, reg870[9]=1'b0 */
++			/* antsel antselb by HW */
++	odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
++			/* reg864[10]=1'b0 */ /* antsel2 by HW */
++	odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1);
++			/* regb2c[22]=1'b0 */ /* disable CS/CG switch */
++	odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
++			/* regb2c[31]=1'b1 */ /* output at CG only */
++	/* OFDM Settings */
++	odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
++	/* @CCK Settings */
++	odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
++			/* @Fix CCK PHY status report issue */
++	odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
++			/* @CCK complete HW AntDiv within 64 samples */
++
++	odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0001);
++			/* @antenna mapping table */
++
++	fat_tab->enable_ctrl_frame_antdiv = 1;
++}
++
++void odm_trx_hw_ant_div_init_88e(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 value32;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
++
++	/* @MAC setting */
++	value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
++	odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD,
++			value32 | (BIT(23) | BIT(25)));
++			/* Reg4C[25]=1, Reg4C[23]=1 for pin output */
++	/* Pin Settings */
++	odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
++			/* reg870[8]=1'b0, reg870[9]=1'b0 */
++			/* antsel antselb by HW */
++	odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
++			/* reg864[10]=1'b0 */ /* antsel2 by HW */
++	odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0);
++			/* regb2c[22]=1'b0 */ /* disable CS/CG switch */
++	odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
++			/* regb2c[31]=1'b1 */ /* output at CG only */
++	/* OFDM Settings */
++	odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
++	/* @CCK Settings */
++	odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
++			/* @Fix CCK PHY status report issue */
++	odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
++			/* @CCK complete HW AntDiv within 64 samples */
++
++	/* @antenna mapping table */
++	if (!dm->is_mp_chip) { /* testchip */
++		odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, 0x700, 1);
++				/* Reg858[10:8]=3'b001 */
++		odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, 0x3800, 2);
++				/* Reg858[13:11]=3'b010 */
++	} else /* @MPchip */
++		odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, MASKDWORD, 0x0201);
++				/*Reg914=3'b010, Reg915=3'b001*/
++
++	fat_tab->enable_ctrl_frame_antdiv = 1;
++}
++
++#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++void odm_smart_hw_ant_div_init_88e(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 value32, i;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "***8188E AntDiv_Init =>  ant_div_type=[CG_TRX_SMART_ANTDIV]\n");
++
++#if 0
++	if (*dm->mp_mode == true) {
++		PHYDM_DBG(dm, ODM_COMP_INIT, "dm->ant_div_type: %d\n",
++			  dm->ant_div_type);
++		return;
++	}
++#endif
++
++	fat_tab->train_idx = 0;
++	fat_tab->fat_state = FAT_PREPARE_STATE;
++
++	dm->fat_comb_a = 5;
++	dm->antdiv_intvl = 0x64; /* @100ms */
++
++	for (i = 0; i < 6; i++)
++		fat_tab->bssid[i] = 0;
++	for (i = 0; i < (dm->fat_comb_a); i++) {
++		fat_tab->ant_sum_rssi[i] = 0;
++		fat_tab->ant_rssi_cnt[i] = 0;
++		fat_tab->ant_ave_rssi[i] = 0;
++	}
++
++	/* @MAC setting */
++	value32 = odm_get_mac_reg(dm, R_0x4c, MASKDWORD);
++	odm_set_mac_reg(dm, R_0x4c, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
++	value32 = odm_get_mac_reg(dm, R_0x7b4, MASKDWORD);
++	odm_set_mac_reg(dm, R_0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
++	/* value32 = platform_efio_read_4byte(adapter, 0x7B4); */
++	/* platform_efio_write_4byte(adapter, 0x7b4, value32|BIT(18));	 */ /* append MACID in reponse packet */
++
++	/* @Match MAC ADDR */
++	odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, 0);
++	odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, 0);
++
++	odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); /* reg870[8]=1'b0, reg870[9]=1'b0		 */ /* antsel antselb by HW */
++	odm_set_bb_reg(dm, R_0x864, BIT(10), 0); /* reg864[10]=1'b0	 */ /* antsel2 by HW */
++	odm_set_bb_reg(dm, R_0xb2c, BIT(22), 0); /* regb2c[22]=1'b0	 */ /* disable CS/CG switch */
++	odm_set_bb_reg(dm, R_0xb2c, BIT(31), 0); /* regb2c[31]=1'b1	 */ /* output at CS only */
++	odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x000000a0);
++
++	/* @antenna mapping table */
++	if (dm->fat_comb_a == 2) {
++		if (!dm->is_mp_chip) { /* testchip */
++			odm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
++			odm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
++		} else { /* @MPchip */
++			odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 1);
++			odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2);
++		}
++	} else {
++		if (!dm->is_mp_chip) { /* testchip */
++			odm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 0); /* Reg858[10:8]=3'b000 */
++			odm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 1); /* Reg858[13:11]=3'b001 */
++			odm_set_bb_reg(dm, R_0x878, BIT(16), 0);
++			odm_set_bb_reg(dm, R_0x858, BIT(15) | BIT(14), 2); /* @(Reg878[0],Reg858[14:15])=3'b010 */
++			odm_set_bb_reg(dm, R_0x878, BIT(19) | BIT(18) | BIT(17), 3); /* Reg878[3:1]=3b'011 */
++			odm_set_bb_reg(dm, R_0x878, BIT(22) | BIT(21) | BIT(20), 4); /* Reg878[6:4]=3b'100 */
++			odm_set_bb_reg(dm, R_0x878, BIT(25) | BIT(24) | BIT(23), 5); /* Reg878[9:7]=3b'101 */
++			odm_set_bb_reg(dm, R_0x878, BIT(28) | BIT(27) | BIT(26), 6); /* Reg878[12:10]=3b'110 */
++			odm_set_bb_reg(dm, R_0x878, BIT(31) | BIT(30) | BIT(29), 7); /* Reg878[15:13]=3b'111 */
++		} else { /* @MPchip */
++			odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 4); /* @0: 3b'000 */
++			odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2); /* @1: 3b'001 */
++			odm_set_bb_reg(dm, R_0x914, MASKBYTE2, 0); /* @2: 3b'010 */
++			odm_set_bb_reg(dm, R_0x914, MASKBYTE3, 1); /* @3: 3b'011 */
++			odm_set_bb_reg(dm, R_0x918, MASKBYTE0, 3); /* @4: 3b'100 */
++			odm_set_bb_reg(dm, R_0x918, MASKBYTE1, 5); /* @5: 3b'101 */
++			odm_set_bb_reg(dm, R_0x918, MASKBYTE2, 6); /* @6: 3b'110 */
++			odm_set_bb_reg(dm, R_0x918, MASKBYTE3, 255); /* @7: 3b'111 */
++		}
++	}
++
++	/* @Default ant setting when no fast training */
++	odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), 0); /* @Default RX */
++	odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */
++	odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), 0); /* @Default TX */
++
++	/* @Enter Traing state */
++	odm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), (dm->fat_comb_a - 1)); /* reg864[2:0]=3'd6	 */ /* ant combination=reg864[2:0]+1 */
++
++#if 0
++	/* SW Control */
++	/* phy_set_bb_reg(adapter, 0x864, BIT10, 1); */
++	/* phy_set_bb_reg(adapter, 0x870, BIT9, 1); */
++	/* phy_set_bb_reg(adapter, 0x870, BIT8, 1); */
++	/* phy_set_bb_reg(adapter, 0x864, BIT11, 1); */
++	/* phy_set_bb_reg(adapter, 0x860, BIT9, 0); */
++	/* phy_set_bb_reg(adapter, 0x860, BIT8, 0); */
++#endif
++}
++#endif
++
++#endif /* @#if (RTL8188E_SUPPORT == 1) */
++
++#if (RTL8192E_SUPPORT == 1)
++void odm_rx_hw_ant_div_init_92e(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++#if 0
++	if (*dm->mp_mode == true) {
++		odm_ant_div_on_off(dm, ANTDIV_OFF);
++		odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
++		/* r_rxdiv_enable_anta  regc50[8]=1'b0  0: control by c50[9] */
++		odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);
++		/* @1:CG, 0:CS */
++		return;
++	}
++#endif
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
++
++	/* Pin Settings */
++	odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
++		/* reg870[8]=1'b0,   antsel is controled by HWs */
++	odm_set_bb_reg(dm, R_0xc50, BIT(8), 1);
++		/* regc50[8]=1'b1    CS/CG switching is controled by HWs*/
++
++	/* @Mapping table */
++	odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
++		/* @antenna mapping table */
++
++	/* OFDM Settings */
++	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
++	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
++
++	/* @CCK Settings */
++	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
++		/* Select which path to receive for CCK_1 & CCK_2 */
++	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
++		/* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
++	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
++		/* @Fix CCK PHY status report issue */
++	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
++		/* @CCK complete HW AntDiv within 64 samples */
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++	phydm_evm_sw_antdiv_init(dm);
++#endif
++}
++
++void odm_trx_hw_ant_div_init_92e(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if 0
++	if (*dm->mp_mode == true) {
++		odm_ant_div_on_off(dm, ANTDIV_OFF);
++		odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* r_rxdiv_enable_anta  regc50[8]=1'b0  0: control by c50[9] */
++		odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);  /* @1:CG, 0:CS */
++		return;
++	}
++#endif
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
++
++	/* @3 --RFE pin setting--------- */
++	/* @[MAC] */
++	odm_set_mac_reg(dm, R_0x38, BIT(11), 1);
++		/* @DBG PAD Driving control (GPIO 8) */
++	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* path-A, RFE_CTRL_3 */
++	odm_set_mac_reg(dm, R_0x4c, BIT(29), 1); /* path-A, RFE_CTRL_8 */
++	/* @[BB] */
++	odm_set_bb_reg(dm, R_0x944, BIT(3), 1); /* RFE_buffer */
++	odm_set_bb_reg(dm, R_0x944, BIT(8), 1);
++	odm_set_bb_reg(dm, R_0x940, BIT(7) | BIT(6), 0x0);
++		/* r_rfe_path_sel_   (RFE_CTRL_3) */
++	odm_set_bb_reg(dm, R_0x940, BIT(17) | BIT(16), 0x0);
++		/* r_rfe_path_sel_   (RFE_CTRL_8) */
++	odm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer */
++	odm_set_bb_reg(dm, R_0x92c, BIT(3), 0); /* rfe_inv  (RFE_CTRL_3) */
++	odm_set_bb_reg(dm, R_0x92c, BIT(8), 1); /* rfe_inv  (RFE_CTRL_8) */
++	odm_set_bb_reg(dm, R_0x930, 0xF000, 0x8); /* path-A, RFE_CTRL_3 */
++	odm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */
++	/* @3 ------------------------- */
++
++	/* Pin Settings */
++	odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
++		/* path-A  */ /* disable CS/CG switch */
++
++#if 0
++	/* @Let it follows PHY_REG for bit9 setting */
++	if (dm->priv->pshare->rf_ft_var.use_ext_pa ||
++	    dm->priv->pshare->rf_ft_var.use_ext_lna)
++		odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);/* path-A output at CS */
++	else
++		odm_set_bb_reg(dm, R_0xc50, BIT(9), 0);
++			/* path-A output at CG ->normal power */
++#endif
++
++	odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
++		/* path-A*/ /* antsel antselb by HW */
++	odm_set_bb_reg(dm, R_0xb38, BIT(10), 0);/* path-A*/ /* antsel2 by HW */
++
++	/* @Mapping table */
++	odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
++		/* @antenna mapping table */
++
++	/* OFDM Settings */
++	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
++	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
++
++	/* @CCK Settings */
++	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
++		/* Select which path to receive for CCK_1 & CCK_2 */
++	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
++		/* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
++	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
++		/* @Fix CCK PHY status report issue */
++	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
++		/* @CCK complete HW AntDiv within 64 samples */
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++	phydm_evm_sw_antdiv_init(dm);
++#endif
++}
++
++#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++void odm_smart_hw_ant_div_init_92e(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "***8192E AntDiv_Init =>  ant_div_type=[CG_TRX_SMART_ANTDIV]\n");
++}
++#endif
++
++#endif /* @#if (RTL8192E_SUPPORT == 1) */
++
++#if (RTL8192F_SUPPORT == 1)
++void odm_rx_hw_ant_div_init_92f(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
++
++	/* Pin Settings */
++	odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
++		/* reg870[8]=1'b0, "antsel" is controlled by HWs */
++	odm_set_bb_reg(dm, R_0xc50, BIT(8), 1);
++		/* regc50[8]=1'b1, " CS/CG switching" is controlled by HWs */
++
++	/* @Mapping table */
++	odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
++		/* @antenna mapping table */
++
++	/* OFDM Settings */
++	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
++	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
++
++	/* @CCK Settings */
++	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
++		/* Select which path to receive for CCK_1 & CCK_2 */
++	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
++		/* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
++	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
++		/* @Fix CCK PHY status report issue */
++	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
++		/* @CCK complete HW AntDiv within 64 samples */
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++	phydm_evm_sw_antdiv_init(dm);
++#endif
++}
++
++void odm_trx_hw_ant_div_init_92f(void *dm_void)
++
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
++	/* @3 --RFE pin setting--------- */
++	/* @[MAC] */
++	odm_set_mac_reg(dm, R_0x1048, BIT(0), 1);
++		/* @DBG PAD Driving control (gpioA_0) */
++	odm_set_mac_reg(dm, R_0x1048, BIT(1), 1);
++		/* @DBG PAD Driving control (gpioA_1) */
++	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1);
++	odm_set_mac_reg(dm, R_0x1038, BIT(25) | BIT(24) | BIT(23), 0);
++		/* @gpioA_0,gpioA_1*/
++	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
++	/* @[BB] */
++	odm_set_bb_reg(dm, R_0x944, BIT(8), 1); /* output enable */
++	odm_set_bb_reg(dm, R_0x944, BIT(9), 1);
++	odm_set_bb_reg(dm, R_0x940, BIT(16) | BIT(17), 0x0);
++		/* r_rfe_path_sel_   (RFE_CTRL_8) */
++	odm_set_bb_reg(dm, R_0x940, BIT(18) | BIT(19), 0x0);
++		/* r_rfe_path_sel_   (RFE_CTRL_9) */
++	odm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer_en */
++	odm_set_bb_reg(dm, R_0x92c, BIT(8), 0); /* rfe_inv  (RFE_CTRL_8) */
++	odm_set_bb_reg(dm, R_0x92c, BIT(9), 1); /* rfe_inv  (RFE_CTRL_9) */
++	odm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */
++	odm_set_bb_reg(dm, R_0x934, 0xF0, 0x8); /* path-A, RFE_CTRL_9 */
++	/* @3 ------------------------- */
++
++	/* Pin Settings */
++	odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
++		/* path-A,disable CS/CG switch */
++	odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
++		/* path-A*, antsel antselb by HW */
++	odm_set_bb_reg(dm, R_0xb38, BIT(10), 0); /* path-A ,antsel2 by HW */
++
++	/* @Mapping table */
++	odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
++		/* @antenna mapping table */
++
++	/* OFDM Settings */
++	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
++	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
++
++	/* @CCK Settings */
++	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
++		/* Select which path to receive for CCK_1 & CCK_2 */
++	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
++		/* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
++	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
++		/* @Fix CCK PHY status report issue */
++	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
++		/* @CCK complete HW AntDiv within 64 samples */
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++	phydm_evm_sw_antdiv_init(dm);
++#endif
++}
++
++#endif /* @#if (RTL8192F_SUPPORT == 1) */
++
++#if (RTL8822B_SUPPORT == 1)
++void phydm_trx_hw_ant_div_init_22b(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
++
++	/* Pin Settings */
++	odm_set_bb_reg(dm, R_0xcb8, BIT(21) | BIT(20), 0x1);
++	odm_set_bb_reg(dm, R_0xcb8, BIT(23) | BIT(22), 0x1);
++	odm_set_bb_reg(dm, R_0xc1c, BIT(7) | BIT(6), 0x0);
++	/* @------------------------- */
++
++	/* @Mapping table */
++	/* @antenna mapping table */
++	odm_set_bb_reg(dm, R_0xca4, 0xFFFF, 0x0100);
++
++	/* OFDM Settings */
++	/* thershold */
++	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0);
++	/* @bias */
++	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0);
++	odm_set_bb_reg(dm, R_0x668, BIT(3), 0x1);
++
++	/* @CCK Settings */
++	/* Select which path to receive for CCK_1 & CCK_2 */
++	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
++	/* @Fix CCK PHY status report issue */
++	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
++	/* @CCK complete HW AntDiv within 64 samples */
++	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
++	/* @BT Coexistence */
++	/* @keep antsel_map when GNT_BT = 1 */
++	odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
++	/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
++	odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
++	/* response TX ant by RX ant */
++	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
++#if (defined(CONFIG_2T4R_ANTENNA))
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "***8822B AntDiv_Init =>  2T4R case\n");
++	/* Pin Settings */
++	odm_set_bb_reg(dm, R_0xeb8, BIT(21) | BIT(20), 0x1);
++	odm_set_bb_reg(dm, R_0xeb8, BIT(23) | BIT(22), 0x1);
++	odm_set_bb_reg(dm, R_0xe1c, BIT(7) | BIT(6), 0x0);
++	/* @BT Coexistence */
++	odm_set_bb_reg(dm, R_0xeac, BIT(9), 1);
++	/* @keep antsel_map when GNT_BT = 1 */
++	/* Mapping table */
++	/* antenna mapping table */
++	odm_set_bb_reg(dm, R_0xea4, 0xFFFF, 0x0100);
++	/*odm_set_bb_reg(dm, R_0x900, 0x30000, 0x3);*/
++#endif
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++	phydm_evm_sw_antdiv_init(dm);
++#endif
++}
++#endif /* @#if (RTL8822B_SUPPORT == 1) */
++
++#if (RTL8197F_SUPPORT == 1)
++void phydm_rx_hw_ant_div_init_97f(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++#if 0
++	if (*dm->mp_mode == true) {
++		odm_ant_div_on_off(dm, ANTDIV_OFF);
++		odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
++		/* r_rxdiv_enable_anta  regc50[8]=1'b0  0: control by c50[9] */
++		odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);  /* @1:CG, 0:CS */
++		return;
++	}
++#endif
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
++
++	/* Pin Settings */
++	odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
++		/* reg870[8]=1'b0, */ /* "antsel" is controlled by HWs */
++	odm_set_bb_reg(dm, R_0xc50, BIT(8), 1);
++		/* regc50[8]=1'b1 *//*"CS/CG switching" is controlled by HWs */
++
++	/* @Mapping table */
++	odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
++		/* @antenna mapping table */
++
++	/* OFDM Settings */
++	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
++	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
++
++	/* @CCK Settings */
++	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
++		/* Select which path to receive for CCK_1 & CCK_2 */
++	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
++		/* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
++	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
++		/* @Fix CCK PHY status report issue */
++	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
++		/* @CCK complete HW AntDiv within 64 samples */
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++	phydm_evm_sw_antdiv_init(dm);
++#endif
++}
++#endif //#if (RTL8197F_SUPPORT == 1)
++
++#if (RTL8197G_SUPPORT == 1)
++void phydm_rx_hw_ant_div_init_97g(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
++
++	/* Pin Settings */
++	odm_set_bb_reg(dm, R_0x1884, BIT(23), 0);
++		/* reg1844[23]=1'b0 *//*"CS/CG switching" is controlled by HWs*/
++	odm_set_bb_reg(dm, R_0x1884, BIT(16), 1);
++		/* reg1844[16]=1'b1 *//*"antsel" is controlled by HWs*/
++
++	/* @Mapping table */
++	odm_set_bb_reg(dm, R_0x1870, 0xFFFF, 0x0100);
++		/* @antenna mapping table */
++
++	/* OFDM Settings */
++	odm_set_bb_reg(dm, R_0x1938, 0xFFE0, 0xA0); /* thershold */
++	odm_set_bb_reg(dm, R_0x1938, 0x7FF0000, 0x0); /* @bias */
++
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++	phydm_evm_sw_antdiv_init(dm);
++#endif
++}
++#endif //#if (RTL8197F_SUPPORT == 1)
++
++#if (RTL8723D_SUPPORT == 1)
++void odm_trx_hw_ant_div_init_8723d(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
++
++	/*@BT Coexistence*/
++	/*@keep antsel_map when GNT_BT = 1*/
++	odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
++	/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
++	odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
++	/* @Disable hw antsw & fast_train.antsw when BT TX/RX */
++	odm_set_bb_reg(dm, R_0xe64, 0xFFFF0000, 0x000c);
++
++	odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
++#if 0
++	/*PTA setting: WL_BB_SEL_BTG_TRXG_anta,  (1: HW CTRL  0: SW CTRL)*/
++	/*odm_set_bb_reg(dm, R_0x948, BIT6, 0);*/
++	/*odm_set_bb_reg(dm, R_0x948, BIT8, 0);*/
++#endif
++	/*@GNT_WL tx*/
++	odm_set_bb_reg(dm, R_0x950, BIT(29), 0);
++
++	/*@Mapping Table*/
++	odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
++	odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 3);
++#if 0
++	/* odm_set_bb_reg(dm, R_0x864, BIT5|BIT4|BIT3, 0); */
++	/* odm_set_bb_reg(dm, R_0x864, BIT8|BIT7|BIT6, 1); */
++#endif
++
++	/* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */
++	odm_set_bb_reg(dm, R_0xccc, BIT(12), 0);
++	/* @Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable */
++	odm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01);
++	/* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable */
++	odm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0);
++	/* @b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable (CCK)*/
++	odm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06);
++	/* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable (CCK) */
++	odm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00);
++
++	/*OFDM HW AntDiv Parameters*/
++	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0);
++	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00);
++	odm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04);
++
++	/*@CCK HW AntDiv Parameters*/
++	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
++	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
++	odm_set_bb_reg(dm, R_0xaa8, BIT(8), 0);
++
++	odm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf);
++	odm_set_bb_reg(dm, R_0xa14, 0x1F, 0x8);
++	odm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1);
++	odm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0);
++	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1);
++
++	/*@disable antenna training	*/
++	odm_set_bb_reg(dm, R_0xe08, BIT(16), 0);
++	odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
++}
++/*@Mingzhi 2017-05-08*/
++
++void odm_s0s1_sw_ant_div_init_8723d(void *dm_void)
++{
++	struct dm_struct		*dm = (struct dm_struct *)dm_void;
++	struct sw_antenna_switch	*swat_tab = &dm->dm_swat_table;
++	struct phydm_fat_struct		*fat_tab = &dm->dm_fat_table;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "***8723D AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
++
++	/*@keep antsel_map when GNT_BT = 1*/
++	odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
++
++	/* @Disable antsw when GNT_BT=1 */
++	odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
++
++	/* @Mapping Table */
++	odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
++	odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
++
++	/* Output Pin Settings */
++#if 0
++	/* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */
++#endif
++	odm_set_bb_reg(dm, R_0x870, BIT(8), 1);
++	odm_set_bb_reg(dm, R_0x870, BIT(9), 1);
++
++	/* Status init */
++	fat_tab->is_become_linked  = false;
++	swat_tab->try_flag = SWAW_STEP_INIT;
++	swat_tab->double_chk_flag = 0;
++	swat_tab->cur_antenna = MAIN_ANT;
++	swat_tab->pre_ant = MAIN_ANT;
++	dm->antdiv_counter = CONFIG_ANTDIV_PERIOD;
++
++	/* @2 [--For HW Bug setting] */
++	odm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant  by Reg */
++}
++
++void odm_update_rx_idle_ant_8723d(void *dm_void, u8 ant, u32 default_ant,
++				  u32 optional_ant)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	void *adapter = dm->adapter;
++	u8 count = 0;
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
++	/*score board to BT ,a002:WL to do ant-div*/
++	odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa002);
++	ODM_delay_us(50);
++#endif
++#if 0
++	/*	odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);	*/
++#endif
++	if (dm->ant_div_type == S0S1_SW_ANTDIV) {
++	odm_set_bb_reg(dm, R_0x860, BIT(8), default_ant);
++	odm_set_bb_reg(dm, R_0x860, BIT(9), default_ant);
++	}
++	odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);
++		/*@Default RX*/
++	odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);
++		/*Optional RX*/
++	odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);
++		/*@Default TX*/
++	fat_tab->rx_idle_ant = ant;
++#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
++	/*score board to BT ,a000:WL@S1 a001:WL@S0*/
++	if (default_ant == ANT1_2G)
++		odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa000);
++	else
++		odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa001);
++#endif
++}
++
++void phydm_set_tx_ant_pwr_8723d(void *dm_void, u8 ant)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	void *adapter = dm->adapter;
++
++	fat_tab->rx_idle_ant = ant;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel);
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	rtw_hal_set_tx_power_level(adapter, *dm->channel);
++#endif
++}
++#endif
++
++#if (RTL8723B_SUPPORT == 1)
++void odm_trx_hw_ant_div_init_8723b(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "***8723B AntDiv_Init =>  ant_div_type=[CG_TRX_HW_ANTDIV(DPDT)]\n");
++
++	/* @Mapping Table */
++	odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
++	odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
++
++	/* OFDM HW AntDiv Parameters */
++	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0); /* thershold */
++	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00); /* @bias */
++
++	/* @CCK HW AntDiv Parameters */
++	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
++		/* patch for clk from 88M to 80M */
++	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
++		/* @do 64 samples */
++
++	/* @BT Coexistence */
++	odm_set_bb_reg(dm, R_0x864, BIT(12), 0);
++		/* @keep antsel_map when GNT_BT = 1 */
++	odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
++		/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
++
++	/* Output Pin Settings */
++	odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
++
++	odm_set_bb_reg(dm, R_0x948, BIT(6), 0);
++		/* WL_BB_SEL_BTG_TRXG_anta,  (1: HW CTRL  0: SW CTRL) */
++	odm_set_bb_reg(dm, R_0x948, BIT(7), 0);
++
++	odm_set_mac_reg(dm, R_0x40, BIT(3), 1);
++	odm_set_mac_reg(dm, R_0x38, BIT(11), 1);
++	odm_set_mac_reg(dm, R_0x4c, BIT(24) | BIT(23), 2);
++		/* select DPDT_P and DPDT_N as output pin */
++
++	odm_set_bb_reg(dm, R_0x944, BIT(0) | BIT(1), 3); /* @in/out */
++	odm_set_bb_reg(dm, R_0x944, BIT(31), 0);
++
++	odm_set_bb_reg(dm, R_0x92c, BIT(1), 0); /* @DPDT_P non-inverse */
++	odm_set_bb_reg(dm, R_0x92c, BIT(0), 1); /* @DPDT_N inverse */
++
++	odm_set_bb_reg(dm, R_0x930, 0xF0, 8); /* @DPDT_P = ANTSEL[0] */
++	odm_set_bb_reg(dm, R_0x930, 0xF, 8); /* @DPDT_N = ANTSEL[0] */
++
++	/* @2 [--For HW Bug setting] */
++	if (dm->ant_type == ODM_AUTO_ANT)
++		odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
++			/* @CCK AntDiv function block enable */
++}
++
++void odm_s0s1_sw_ant_div_init_8723b(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "***8723B AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
++
++	/* @Mapping Table */
++	odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
++	odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
++
++#if 0
++	/* Output Pin Settings */
++	/* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */
++#endif
++	odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
++
++	fat_tab->is_become_linked = false;
++	swat_tab->try_flag = SWAW_STEP_INIT;
++	swat_tab->double_chk_flag = 0;
++
++	/* @2 [--For HW Bug setting] */
++	odm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant  by Reg */
++}
++
++void odm_update_rx_idle_ant_8723b(
++	void *dm_void,
++	u8 ant,
++	u32 default_ant,
++	u32 optional_ant)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	void *adapter = dm->adapter;
++	u8 count = 0;
++	/*u8			u1_temp;*/
++	/*u8			h2c_parameter;*/
++
++	if (!dm->is_linked && dm->ant_type == ODM_AUTO_ANT) {
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to no link\n");
++		return;
++	}
++
++#if 0
++	/* Send H2C command to FW */
++	/* @Enable wifi calibration */
++	h2c_parameter = true;
++	odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
++
++	/* @Check if H2C command sucess or not (0x1e6) */
++	u1_temp = odm_read_1byte(dm, 0x1e6);
++	while ((u1_temp != 0x1) && (count < 100)) {
++		ODM_delay_us(10);
++		u1_temp = odm_read_1byte(dm, 0x1e6);
++		count++;
++	}
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[ Update Rx-Idle-ant ] 8723B: H2C command status = %d, count = %d\n",
++		  u1_temp, count);
++
++	if (u1_temp == 0x1) {
++		/* @Check if BT is doing IQK (0x1e7) */
++		count = 0;
++		u1_temp = odm_read_1byte(dm, 0x1e7);
++		while ((!(u1_temp & BIT(0)))  && (count < 100)) {
++			ODM_delay_us(50);
++			u1_temp = odm_read_1byte(dm, 0x1e7);
++			count++;
++		}
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ Update Rx-Idle-ant ] 8723B: BT IQK status = %d, count = %d\n",
++			  u1_temp, count);
++
++		if (u1_temp & BIT(0)) {
++			odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);
++			odm_set_bb_reg(dm, R_0x948, BIT(9), default_ant);
++			odm_set_bb_reg(dm, R_0x864, 0x38, default_ant);
++					/* @Default RX */
++			odm_set_bb_reg(dm, R_0x864, 0x1c0, optional_ant);
++					/* @Optional RX */
++			odm_set_bb_reg(dm, R_0x860, 0x7000, default_ant);
++					/* @Default TX */
++			fat_tab->rx_idle_ant = ant;
++
++			/* Set TX AGC by S0/S1 */
++			/* Need to consider Linux driver */
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++			adapter->hal_func.set_tx_power_level_handler(adapter, *dm->channel);
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++			rtw_hal_set_tx_power_level(adapter, *dm->channel);
++#endif
++
++			/* Set IQC by S0/S1 */
++			odm_set_iqc_by_rfpath(dm, default_ant);
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n");
++		} else
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to BT IQK\n");
++	} else
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to H2C command fail\n");
++
++	/* Send H2C command to FW */
++	/* @Disable wifi calibration */
++	h2c_parameter = false;
++	odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
++#else
++
++	odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);
++	odm_set_bb_reg(dm, R_0x948, BIT(9), default_ant);
++	odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);
++			/*@Default RX*/
++	odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);
++			/*Optional RX*/
++	odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);
++			/*@Default TX*/
++	fat_tab->rx_idle_ant = ant;
++
++/* Set TX AGC by S0/S1 */
++/* Need to consider Linux driver */
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel);
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	rtw_hal_set_tx_power_level(adapter, *dm->channel);
++#endif
++
++	/* Set IQC by S0/S1 */
++	odm_set_iqc_by_rfpath(dm, default_ant);
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n");
++
++#endif
++}
++
++boolean
++phydm_is_bt_enable_8723b(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 bt_state;
++#if 0
++	/*u32			reg75;*/
++
++	/*reg75 = odm_get_bb_reg(dm, R_0x74, BIT8);*/
++	/*odm_set_bb_reg(dm, R_0x74, BIT8, 0x0);*/
++#endif
++	odm_set_bb_reg(dm, R_0xa0, BIT(24) | BIT(25) | BIT(26), 0x5);
++	bt_state = odm_get_bb_reg(dm, R_0xa0, 0xf);
++#if 0
++	/*odm_set_bb_reg(dm, R_0x74, BIT8, reg75);*/
++#endif
++
++	if (bt_state == 4 || bt_state == 7 || bt_state == 9 || bt_state == 13)
++		return true;
++	else
++		return false;
++}
++#endif /* @#if (RTL8723B_SUPPORT == 1) */
++
++#if (RTL8821A_SUPPORT == 1)
++
++void odm_trx_hw_ant_div_init_8821a(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
++
++	/* Output Pin Settings */
++	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
++
++	odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
++	odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
++
++	odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
++
++	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
++			/* select DPDT_P and DPDT_N as output pin */
++	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
++	odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
++	odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
++	odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
++	odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
++
++	/* @Mapping Table */
++	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
++	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
++
++	/* OFDM HW AntDiv Parameters */
++	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
++	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
++
++	/* @CCK HW AntDiv Parameters */
++	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
++		/* patch for clk from 88M to 80M */
++	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
++
++	odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
++		/* @ANTSEL_CCK sent to the smart_antenna circuit */
++	odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
++		/* @CCK AntDiv function block enable */
++
++	/* @BT Coexistence */
++	odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
++		/* @keep antsel_map when GNT_BT = 1 */
++	odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
++		/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
++
++	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
++		/* settling time of antdiv by RF LNA = 100ns */
++
++	/* response TX ant by RX ant */
++	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
++}
++
++void odm_s0s1_sw_ant_div_init_8821a(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
++
++	/* Output Pin Settings */
++	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
++
++	odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
++	odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
++
++	odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
++
++	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
++		/* select DPDT_P and DPDT_N as output pin */
++	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
++	odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
++	odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
++	odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
++	odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
++
++	/* @Mapping Table */
++	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
++	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
++
++	/* OFDM HW AntDiv Parameters */
++	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
++	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
++
++	/* @CCK HW AntDiv Parameters */
++	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
++		/* patch for clk from 88M to 80M */
++	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
++
++	odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
++		/* @ANTSEL_CCK sent to the smart_antenna circuit */
++	odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
++		/* @CCK AntDiv function block enable */
++
++	/* @BT Coexistence */
++	odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
++		/* @keep antsel_map when GNT_BT = 1 */
++	odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
++		/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
++
++	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
++		/* settling time of antdiv by RF LNA = 100ns */
++
++	/* response TX ant by RX ant */
++	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
++
++	odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
++
++	swat_tab->try_flag = SWAW_STEP_INIT;
++	swat_tab->double_chk_flag = 0;
++	swat_tab->cur_antenna = MAIN_ANT;
++	swat_tab->pre_ant = MAIN_ANT;
++	swat_tab->swas_no_link_state = 0;
++}
++#endif /* @#if (RTL8821A_SUPPORT == 1) */
++
++#if (RTL8821C_SUPPORT == 1)
++void odm_trx_hw_ant_div_init_8821c(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
++	/* Output Pin Settings */
++	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
++
++	odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
++	odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
++
++	odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
++
++	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
++		/* select DPDT_P and DPDT_N as output pin */
++	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
++	odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
++	odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
++	odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
++	odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
++
++	/* @Mapping Table */
++	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
++	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
++
++	/* OFDM HW AntDiv Parameters */
++	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
++	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
++
++	/* @CCK HW AntDiv Parameters */
++	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
++		/* patch for clk from 88M to 80M */
++	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
++
++	odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
++		/* @ANTSEL_CCK sent to the smart_antenna circuit */
++	odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
++		/* @CCK AntDiv function block enable */
++
++	/* @BT Coexistence */
++	odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
++		/* @keep antsel_map when GNT_BT = 1 */
++	odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
++		/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
++
++	/* Timming issue */
++	odm_set_bb_reg(dm, R_0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), 0);
++		/*@keep antidx after tx for ACK ( unit x 3.2 mu sec)*/
++	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
++		/* settling time of antdiv by RF LNA = 100ns */
++
++	/* response TX ant by RX ant */
++	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
++}
++
++void phydm_s0s1_sw_ant_div_init_8821c(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
++
++	/* Output Pin Settings */
++	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
++
++	odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
++	odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
++
++	odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
++
++	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
++		/* select DPDT_P and DPDT_N as output pin */
++	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
++	odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
++	odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
++	odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
++	odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
++
++	/* @Mapping Table */
++	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
++	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
++
++	/* OFDM HW AntDiv Parameters */
++	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
++	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x00); /* @bias */
++
++	/* @CCK HW AntDiv Parameters */
++	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
++		/* patch for clk from 88M to 80M */
++	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
++
++	odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
++		/* @ANTSEL_CCK sent to the smart_antenna circuit */
++	odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
++		/* @CCK AntDiv function block enable */
++
++	/* @BT Coexistence */
++	odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
++		/* @keep antsel_map when GNT_BT = 1 */
++	odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
++		/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
++
++	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
++		/* settling time of antdiv by RF LNA = 100ns */
++
++	/* response TX ant by RX ant */
++	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
++
++	odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
++
++	swat_tab->try_flag = SWAW_STEP_INIT;
++	swat_tab->double_chk_flag = 0;
++	swat_tab->cur_antenna = MAIN_ANT;
++	swat_tab->pre_ant = MAIN_ANT;
++	swat_tab->swas_no_link_state = 0;
++}
++#endif /* @#if (RTL8821C_SUPPORT == 1) */
++
++#if (RTL8881A_SUPPORT == 1)
++void odm_trx_hw_ant_div_init_8881a(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
++
++	/* Output Pin Settings */
++	/* @[SPDT related] */
++	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
++	odm_set_mac_reg(dm, R_0x4c, BIT(26), 0);
++	odm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */
++	odm_set_bb_reg(dm, R_0xcb4, BIT(22), 0);
++	odm_set_bb_reg(dm, R_0xcb4, BIT(24), 1);
++	odm_set_bb_reg(dm, R_0xcb0, 0xF00, 8); /* @DPDT_P = ANTSEL[0] */
++	odm_set_bb_reg(dm, R_0xcb0, 0xF0000, 8); /* @DPDT_N = ANTSEL[0] */
++
++	/* @Mapping Table */
++	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
++	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
++
++	/* OFDM HW AntDiv Parameters */
++	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
++	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */
++	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
++		/* settling time of antdiv by RF LNA = 100ns */
++
++	/* @CCK HW AntDiv Parameters */
++	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
++		/* patch for clk from 88M to 80M */
++	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
++
++	/* @2 [--For HW Bug setting] */
++
++	odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
++		/* TX ant  by Reg *//* A-cut bug */
++}
++
++#endif /* @#if (RTL8881A_SUPPORT == 1) */
++
++#if (RTL8812A_SUPPORT == 1)
++void odm_trx_hw_ant_div_init_8812a(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
++
++	/* @3 */ /* @3 --RFE pin setting--------- */
++	/* @[BB] */
++	odm_set_bb_reg(dm, R_0x900, BIT(10) | BIT(9) | BIT(8), 0x0);
++		/* @disable SW switch */
++	odm_set_bb_reg(dm, R_0x900, BIT(17) | BIT(16), 0x0);
++	odm_set_bb_reg(dm, R_0x974, BIT(7) | BIT(6), 0x3); /* @in/out */
++	odm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */
++	odm_set_bb_reg(dm, R_0xcb4, BIT(26), 0);
++	odm_set_bb_reg(dm, R_0xcb4, BIT(27), 1);
++	odm_set_bb_reg(dm, R_0xcb0, 0xF000000, 8); /* @DPDT_P = ANTSEL[0] */
++	odm_set_bb_reg(dm, R_0xcb0, 0xF0000000, 8); /* @DPDT_N = ANTSEL[0] */
++	/* @3 ------------------------- */
++
++	/* @Mapping Table */
++	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
++	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
++
++	/* OFDM HW AntDiv Parameters */
++	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
++	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */
++	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
++		/* settling time of antdiv by RF LNA = 100ns */
++
++	/* @CCK HW AntDiv Parameters */
++	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
++		/* patch for clk from 88M to 80M */
++	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
++
++	/* @2 [--For HW Bug setting] */
++
++	odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
++		/* TX ant  by Reg */ /* A-cut bug */
++}
++
++#endif /* @#if (RTL8812A_SUPPORT == 1) */
++
++#if (RTL8188F_SUPPORT == 1)
++void odm_s0s1_sw_ant_div_init_8188f(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
++
++#if 0
++	/*@GPIO setting*/
++	/*odm_set_mac_reg(dm, R_0x64, BIT(18), 0); */
++	/*odm_set_mac_reg(dm, R_0x44, BIT(28)|BIT(27), 0);*/
++	/*odm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3);*/
++		/*enable_output for P_GPIO[4:3]*/
++	/*odm_set_mac_reg(dm, R_0x44, BIT(12)|BIT(11), 0);*/ /*output value*/
++	/*odm_set_mac_reg(dm, R_0x40, BIT(1)|BIT(0), 0);*/ /*GPIO function*/
++#endif
++
++	if (dm->support_ic_type == ODM_RTL8188F) {
++		if (dm->support_interface == ODM_ITRF_USB)
++			odm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3);
++				/*@enable_output for P_GPIO[4:3]*/
++		else if (dm->support_interface == ODM_ITRF_SDIO)
++			odm_set_mac_reg(dm, R_0x44, BIT(18), 0x1);
++				/*@enable_output for P_GPIO[2]*/
++	}
++
++	fat_tab->is_become_linked = false;
++	swat_tab->try_flag = SWAW_STEP_INIT;
++	swat_tab->double_chk_flag = 0;
++}
++
++void phydm_update_rx_idle_antenna_8188F(void *dm_void, u32 default_ant)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 codeword;
++
++	if (dm->support_ic_type == ODM_RTL8188F) {
++		if (dm->support_interface == ODM_ITRF_USB) {
++			if (default_ant == ANT1_2G)
++				codeword = 1; /*@2'b01*/
++			else
++				codeword = 2; /*@2'b10*/
++			odm_set_mac_reg(dm, R_0x44, 0x1800, codeword);
++				/*@GPIO[4:3] output value*/
++		} else if (dm->support_interface == ODM_ITRF_SDIO) {
++			if (default_ant == ANT1_2G) {
++				codeword = 0; /*@1'b0*/
++				odm_set_bb_reg(dm, R_0x870, 0x300, 0x3);
++				odm_set_bb_reg(dm, R_0x860, 0x300, 0x1);
++			} else {
++				codeword = 1; /*@1'b1*/
++				odm_set_bb_reg(dm, R_0x870, 0x300, 0x3);
++				odm_set_bb_reg(dm, R_0x860, 0x300, 0x2);
++			}
++			odm_set_mac_reg(dm, R_0x44, BIT(10), codeword);
++				/*@GPIO[2] output value*/
++		}
++	}
++}
++#endif
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++void phydm_rx_rate_for_antdiv(void *dm_void, void *pkt_info_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	struct phydm_perpkt_info_struct *pktinfo = NULL;
++	u8 data_rate = 0;
++
++	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
++	data_rate = pktinfo->data_rate & 0x7f;
++
++	if (!fat_tab->get_stats)
++		return;
++
++	if (fat_tab->antsel_rx_keep_0 == ANT1_2G) {
++		if (data_rate >= ODM_RATEMCS0 &&
++		    data_rate <= ODM_RATEMCS15)
++			fat_tab->main_ht_cnt[data_rate - ODM_RATEMCS0]++;
++		else if (data_rate >= ODM_RATEVHTSS1MCS0 &&
++			 data_rate <= ODM_RATEVHTSS2MCS9)
++			fat_tab->main_vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++;
++	} else { /*ANT2_2G*/
++		if (data_rate >= ODM_RATEMCS0 &&
++		    data_rate <= ODM_RATEMCS15)
++			fat_tab->aux_ht_cnt[data_rate - ODM_RATEMCS0]++;
++		else if (data_rate >= ODM_RATEVHTSS1MCS0 &&
++			 data_rate <= ODM_RATEVHTSS2MCS9)
++			fat_tab->aux_vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++;
++	}
++}
++
++void phydm_antdiv_reset_rx_rate(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	odm_memory_set(dm, &fat_tab->main_ht_cnt[0], 0, HT_IDX * 2);
++	odm_memory_set(dm, &fat_tab->aux_ht_cnt[0], 0, HT_IDX * 2);
++	odm_memory_set(dm, &fat_tab->main_vht_cnt[0], 0, VHT_IDX * 2);
++	odm_memory_set(dm, &fat_tab->aux_vht_cnt[0], 0, VHT_IDX * 2);
++}
++
++void phydm_statistics_evm_1ss(void *dm_void,	void *phy_info_void,
++			      u8 antsel_tr_mux, u32 id, u32 utility)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	struct phydm_phyinfo_struct *phy_info = NULL;
++
++	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
++	if (antsel_tr_mux == ANT1_2G) {
++		fat_tab->main_evm_sum[id] += ((phy_info->rx_mimo_evm_dbm[0])
++					     << 5);
++		fat_tab->main_evm_cnt[id]++;
++	} else {
++		fat_tab->aux_evm_sum[id] += ((phy_info->rx_mimo_evm_dbm[0])
++					    << 5);
++		fat_tab->aux_evm_cnt[id]++;
++	}
++}
++
++void phydm_statistics_evm_2ss(void *dm_void,	void *phy_info_void,
++			      u8 antsel_tr_mux, u32 id, u32 utility)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	struct phydm_phyinfo_struct *phy_info = NULL;
++
++	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
++	if (antsel_tr_mux == ANT1_2G) {
++		fat_tab->main_evm_2ss_sum[id][0] += phy_info->rx_mimo_evm_dbm[0]
++						    << 5;
++		fat_tab->main_evm_2ss_sum[id][1] += phy_info->rx_mimo_evm_dbm[1]
++						    << 5;
++		fat_tab->main_evm_2ss_cnt[id]++;
++
++	} else {
++		fat_tab->aux_evm_2ss_sum[id][0] += (phy_info->rx_mimo_evm_dbm[0]
++						   << 5);
++		fat_tab->aux_evm_2ss_sum[id][1] += (phy_info->rx_mimo_evm_dbm[1]
++						   << 5);
++		fat_tab->aux_evm_2ss_cnt[id]++;
++	}
++}
++
++void phydm_evm_sw_antdiv_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	/*@EVM enhance AntDiv method init----------------*/
++	fat_tab->evm_method_enable = 0;
++	fat_tab->fat_state = NORMAL_STATE_MIAN;
++	fat_tab->fat_state_cnt = 0;
++	fat_tab->pre_antdiv_rssi = 0;
++
++	dm->antdiv_intvl = 30;
++	dm->antdiv_delay = 20;
++	dm->antdiv_train_num = 4;
++	if (dm->support_ic_type & ODM_RTL8192E)
++		odm_set_bb_reg(dm, R_0x910, 0x3f, 0xf);
++	dm->antdiv_evm_en = 1;
++	/*@dm->antdiv_period=1;*/
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	dm->evm_antdiv_period = 1;
++#else
++	dm->evm_antdiv_period = 3;
++#endif
++	dm->stop_antdiv_rssi_th = 3;
++	dm->stop_antdiv_tp_th = 80;
++	dm->antdiv_tp_period = 3;
++	dm->stop_antdiv_tp_diff_th = 5;
++}
++
++void odm_evm_fast_ant_reset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	fat_tab->evm_method_enable = 0;
++	if (fat_tab->div_path_type == ANT_PATH_A)
++		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
++	else if (fat_tab->div_path_type == ANT_PATH_B)
++		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
++	else if (fat_tab->div_path_type == ANT_PATH_AB)
++		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
++	fat_tab->fat_state = NORMAL_STATE_MIAN;
++	fat_tab->fat_state_cnt = 0;
++	dm->antdiv_period = 0;
++	odm_set_mac_reg(dm, R_0x608, BIT(8), 0);
++}
++
++void odm_evm_enhance_ant_div(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 main_rssi, aux_rssi;
++	u32 main_crc_utility = 0, aux_crc_utility = 0, utility_ratio = 1;
++	u32 main_evm, aux_evm, diff_rssi = 0, diff_EVM = 0;
++	u32 main_2ss_evm[2], aux_2ss_evm[2];
++	u32 main_1ss_evm, aux_1ss_evm;
++	u32 main_2ss_evm_sum, aux_2ss_evm_sum;
++	u8 score_EVM = 0, score_CRC = 0;
++	u8 rssi_larger_ant = 0;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	u32 value32, i, mac_id;
++	boolean main_above1 = false, aux_above1 = false;
++	boolean force_antenna = false;
++	struct cmn_sta_info *sta;
++	u32 main_tp_avg, aux_tp_avg;
++	u8 curr_rssi, rssi_diff;
++	u32 tp_diff, tp_diff_avg;
++	u16 main_max_cnt = 0, aux_max_cnt = 0;
++	u16 main_max_idx = 0, aux_max_idx = 0;
++	u16 main_cnt_all = 0, aux_cnt_all = 0;
++	u8 rate_num = dm->num_rf_path;
++	u8 rate_ss_shift = 0;
++	u8 tp_diff_return = 0, tp_return = 0, rssi_return = 0;
++	u8 target_ant_evm_1ss, target_ant_evm_2ss;
++	u8 decision_evm_ss;
++	u8 next_ant;
++
++	fat_tab->target_ant_enhance = 0xFF;
++
++	if ((dm->support_ic_type & ODM_EVM_ANTDIV_IC)) {
++		if (dm->is_one_entry_only) {
++#if 0
++			/* PHYDM_DBG(dm,DBG_ANT_DIV, "[One Client only]\n"); */
++#endif
++			mac_id = dm->one_entry_macid;
++			sta = dm->phydm_sta_info[mac_id];
++
++			main_rssi = (fat_tab->main_cnt[mac_id] != 0) ? (fat_tab->main_sum[mac_id] / fat_tab->main_cnt[mac_id]) : 0;
++			aux_rssi = (fat_tab->aux_cnt[mac_id] != 0) ? (fat_tab->aux_sum[mac_id] / fat_tab->aux_cnt[mac_id]) : 0;
++
++			if ((main_rssi == 0 && aux_rssi != 0 && aux_rssi >= FORCE_RSSI_DIFF) || (main_rssi != 0 && aux_rssi == 0 && main_rssi >= FORCE_RSSI_DIFF))
++				diff_rssi = FORCE_RSSI_DIFF;
++			else if (main_rssi != 0 && aux_rssi != 0)
++				diff_rssi = (main_rssi >= aux_rssi) ? (main_rssi - aux_rssi) : (aux_rssi - main_rssi);
++
++			if (main_rssi >= aux_rssi)
++				rssi_larger_ant = MAIN_ANT;
++			else
++				rssi_larger_ant = AUX_ANT;
++
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "Main_Cnt=(( %d )), main_rssi=(( %d ))\n",
++				  fat_tab->main_cnt[mac_id], main_rssi);
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "Aux_Cnt=(( %d )), aux_rssi=(( %d ))\n",
++				  fat_tab->aux_cnt[mac_id], aux_rssi);
++
++			if (((main_rssi >= evm_rssi_th_high || aux_rssi >= evm_rssi_th_high) || fat_tab->evm_method_enable == 1)
++			    /* @&& (diff_rssi <= FORCE_RSSI_DIFF + 1) */
++			    ) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "> TH_H || evm_method_enable==1\n");
++
++				if ((main_rssi >= evm_rssi_th_low || aux_rssi >= evm_rssi_th_low)) {
++					PHYDM_DBG(dm, DBG_ANT_DIV, "> TH_L, fat_state_cnt =((%d))\n", fat_tab->fat_state_cnt);
++
++					/*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)============================================================*/
++					if (fat_tab->fat_state_cnt < (dm->antdiv_train_num << 1)) {
++						if (fat_tab->fat_state_cnt == 0) {
++							/*Reset EVM 1SS Method */
++							fat_tab->main_evm_sum[mac_id] = 0;
++							fat_tab->aux_evm_sum[mac_id] = 0;
++							fat_tab->main_evm_cnt[mac_id] = 0;
++							fat_tab->aux_evm_cnt[mac_id] = 0;
++							/*Reset EVM 2SS Method */
++							fat_tab->main_evm_2ss_sum[mac_id][0] = 0;
++							fat_tab->main_evm_2ss_sum[mac_id][1] = 0;
++							fat_tab->aux_evm_2ss_sum[mac_id][0] = 0;
++							fat_tab->aux_evm_2ss_sum[mac_id][1] = 0;
++							fat_tab->main_evm_2ss_cnt[mac_id] = 0;
++							fat_tab->aux_evm_2ss_cnt[mac_id] = 0;
++
++							/*Reset TP Method */
++							fat_tab->main_tp = 0;
++							fat_tab->aux_tp = 0;
++							fat_tab->main_tp_cnt = 0;
++							fat_tab->aux_tp_cnt = 0;
++							phydm_antdiv_reset_rx_rate(dm);
++
++							/*Reset CRC Method */
++							fat_tab->main_crc32_ok_cnt = 0;
++							fat_tab->main_crc32_fail_cnt = 0;
++							fat_tab->aux_crc32_ok_cnt = 0;
++							fat_tab->aux_crc32_fail_cnt = 0;
++
++#ifdef SKIP_EVM_ANTDIV_TRAINING_PATCH
++							if ((*dm->band_width == CHANNEL_WIDTH_20) && sta->mimo_type == RF_2T2R) {
++								/*@1. Skip training: RSSI*/
++#if 0
++								/*PHYDM_DBG(pDM_Odm,DBG_ANT_DIV, "TargetAnt_enhance=((%d)), RxIdleAnt=((%d))\n", pDM_FatTable->TargetAnt_enhance, pDM_FatTable->RxIdleAnt);*/
++#endif
++								curr_rssi = (u8)((fat_tab->rx_idle_ant == MAIN_ANT) ? main_rssi : aux_rssi);
++								rssi_diff = (curr_rssi > fat_tab->pre_antdiv_rssi) ? (curr_rssi - fat_tab->pre_antdiv_rssi) : (fat_tab->pre_antdiv_rssi - curr_rssi);
++
++								PHYDM_DBG(dm, DBG_ANT_DIV, "[1] rssi_return, curr_rssi=((%d)), pre_rssi=((%d))\n", curr_rssi, fat_tab->pre_antdiv_rssi);
++
++								fat_tab->pre_antdiv_rssi = curr_rssi;
++								if (rssi_diff < dm->stop_antdiv_rssi_th && curr_rssi != 0)
++									rssi_return = 1;
++
++								/*@2. Skip training: TP Diff*/
++								tp_diff = (dm->rx_tp > fat_tab->pre_antdiv_tp) ? (dm->rx_tp - fat_tab->pre_antdiv_tp) : (fat_tab->pre_antdiv_tp - dm->rx_tp);
++
++								PHYDM_DBG(dm, DBG_ANT_DIV, "[2] tp_diff_return, curr_tp=((%d)), pre_tp=((%d))\n", dm->rx_tp, fat_tab->pre_antdiv_tp);
++								fat_tab->pre_antdiv_tp = dm->rx_tp;
++								if ((tp_diff < (u32)(dm->stop_antdiv_tp_diff_th) && dm->rx_tp != 0))
++									tp_diff_return = 1;
++
++								PHYDM_DBG(dm, DBG_ANT_DIV, "[3] tp_return, curr_rx_tp=((%d))\n", dm->rx_tp);
++								/*@3. Skip training: TP*/
++								if (dm->rx_tp >= (u32)(dm->stop_antdiv_tp_th))
++									tp_return = 1;
++
++								PHYDM_DBG(dm, DBG_ANT_DIV, "[4] Return {rssi, tp_diff, tp} = {%d, %d, %d}\n", rssi_return, tp_diff_return, tp_return);
++								/*@4. Joint Return Decision*/
++								if (tp_return) {
++									if (tp_diff_return || rssi_diff) {
++										PHYDM_DBG(dm, DBG_ANT_DIV, "***Return EVM SW AntDiv\n");
++										return;
++									}
++								}
++							}
++#endif
++
++							fat_tab->evm_method_enable = 1;
++							if (fat_tab->div_path_type == ANT_PATH_A)
++								odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
++							else if (fat_tab->div_path_type == ANT_PATH_B)
++								odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
++							else if (fat_tab->div_path_type == ANT_PATH_AB)
++								odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
++							dm->antdiv_period = dm->evm_antdiv_period;
++							odm_set_mac_reg(dm, R_0x608, BIT(8), 1); /*RCR accepts CRC32-Error packets*/
++							fat_tab->fat_state_cnt++;
++							fat_tab->get_stats = false;
++							next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? MAIN_ANT : AUX_ANT;
++							odm_update_rx_idle_ant(dm, next_ant);
++							PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv Delay ]\n");
++							odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_delay); //ms
++						} else if ((fat_tab->fat_state_cnt % 2) != 0) {
++							fat_tab->fat_state_cnt++;
++							fat_tab->get_stats = true;
++							odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_intvl); //ms
++						} else if ((fat_tab->fat_state_cnt % 2) == 0) {
++							fat_tab->fat_state_cnt++;
++							fat_tab->get_stats = false;
++							next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
++							odm_update_rx_idle_ant(dm, next_ant);
++							PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv Delay ]\n");
++							odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_delay); //ms
++						}
++					}
++					/*@Decision state: 4==============================================================*/
++					else {
++						fat_tab->get_stats = false;
++						fat_tab->fat_state_cnt = 0;
++						PHYDM_DBG(dm, DBG_ANT_DIV, "[Decisoin state ]\n");
++
++/* @3 [CRC32 statistic] */
++#if 0
++						if ((fat_tab->main_crc32_ok_cnt > (fat_tab->aux_crc32_ok_cnt << 1)) || (diff_rssi >= 40 && rssi_larger_ant == MAIN_ANT)) {
++							fat_tab->target_ant_crc32 = MAIN_ANT;
++							force_antenna = true;
++							PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Main\n");
++						} else if ((fat_tab->aux_crc32_ok_cnt > ((fat_tab->main_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == AUX_ANT))) {
++							fat_tab->target_ant_crc32 = AUX_ANT;
++							force_antenna = true;
++							PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Aux\n");
++						} else
++#endif
++						{
++							if (fat_tab->main_crc32_fail_cnt <= 5)
++								fat_tab->main_crc32_fail_cnt = 5;
++
++							if (fat_tab->aux_crc32_fail_cnt <= 5)
++								fat_tab->aux_crc32_fail_cnt = 5;
++
++							if (fat_tab->main_crc32_ok_cnt > fat_tab->main_crc32_fail_cnt)
++								main_above1 = true;
++
++							if (fat_tab->aux_crc32_ok_cnt > fat_tab->aux_crc32_fail_cnt)
++								aux_above1 = true;
++
++							if (main_above1 == true && aux_above1 == false) {
++								force_antenna = true;
++								fat_tab->target_ant_crc32 = MAIN_ANT;
++							} else if (main_above1 == false && aux_above1 == true) {
++								force_antenna = true;
++								fat_tab->target_ant_crc32 = AUX_ANT;
++							} else if (main_above1 == true && aux_above1 == true) {
++								main_crc_utility = ((fat_tab->main_crc32_ok_cnt) << 7) / fat_tab->main_crc32_fail_cnt;
++								aux_crc_utility = ((fat_tab->aux_crc32_ok_cnt) << 7) / fat_tab->aux_crc32_fail_cnt;
++								fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility >= aux_crc_utility) ? MAIN_ANT : AUX_ANT);
++
++								if (main_crc_utility != 0 && aux_crc_utility != 0) {
++									if (main_crc_utility >= aux_crc_utility)
++										utility_ratio = (main_crc_utility << 1) / aux_crc_utility;
++									else
++										utility_ratio = (aux_crc_utility << 1) / main_crc_utility;
++								}
++							} else if (main_above1 == false && aux_above1 == false) {
++								if (fat_tab->main_crc32_ok_cnt == 0)
++									fat_tab->main_crc32_ok_cnt = 1;
++								if (fat_tab->aux_crc32_ok_cnt == 0)
++									fat_tab->aux_crc32_ok_cnt = 1;
++
++								main_crc_utility = ((fat_tab->main_crc32_fail_cnt) << 7) / fat_tab->main_crc32_ok_cnt;
++								aux_crc_utility = ((fat_tab->aux_crc32_fail_cnt) << 7) / fat_tab->aux_crc32_ok_cnt;
++								fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility <= aux_crc_utility) ? MAIN_ANT : AUX_ANT);
++
++								if (main_crc_utility != 0 && aux_crc_utility != 0) {
++									if (main_crc_utility >= aux_crc_utility)
++										utility_ratio = (main_crc_utility << 1) / (aux_crc_utility);
++									else
++										utility_ratio = (aux_crc_utility << 1) / (main_crc_utility);
++								}
++							}
++						}
++						odm_set_mac_reg(dm, R_0x608, BIT(8), 0); /* NOT Accept CRC32 Error packets. */
++						PHYDM_DBG(dm, DBG_ANT_DIV, "MAIN_CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->main_crc32_ok_cnt, fat_tab->main_crc32_fail_cnt, main_crc_utility);
++						PHYDM_DBG(dm, DBG_ANT_DIV, "AUX__CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->aux_crc32_ok_cnt, fat_tab->aux_crc32_fail_cnt, aux_crc_utility);
++						PHYDM_DBG(dm, DBG_ANT_DIV, "***1.TargetAnt_CRC32 = ((%s))\n", (fat_tab->target_ant_crc32 == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
++
++						for (i = 0; i < HT_IDX; i++) {
++							main_cnt_all += fat_tab->main_ht_cnt[i];
++							aux_cnt_all += fat_tab->aux_ht_cnt[i];
++
++							if (fat_tab->main_ht_cnt[i] > main_max_cnt) {
++								main_max_cnt = fat_tab->main_ht_cnt[i];
++								main_max_idx = i;
++							}
++
++							if (fat_tab->aux_ht_cnt[i] > aux_max_cnt) {
++								aux_max_cnt = fat_tab->aux_ht_cnt[i];
++								aux_max_idx = i;
++							}
++						}
++
++						for (i = 0; i < rate_num; i++) {
++							rate_ss_shift = (i << 3);
++							PHYDM_DBG(dm, DBG_ANT_DIV, "*main_ht_cnt  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
++							(rate_ss_shift), (rate_ss_shift + 7),
++							fat_tab->main_ht_cnt[rate_ss_shift + 0], fat_tab->main_ht_cnt[rate_ss_shift + 1],
++							fat_tab->main_ht_cnt[rate_ss_shift + 2], fat_tab->main_ht_cnt[rate_ss_shift + 3],
++							fat_tab->main_ht_cnt[rate_ss_shift + 4], fat_tab->main_ht_cnt[rate_ss_shift + 5],
++							fat_tab->main_ht_cnt[rate_ss_shift + 6], fat_tab->main_ht_cnt[rate_ss_shift + 7]);
++						}
++
++						for (i = 0; i < rate_num; i++) {
++							rate_ss_shift = (i << 3);
++							PHYDM_DBG(dm, DBG_ANT_DIV, "*aux_ht_cnt  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
++							(rate_ss_shift), (rate_ss_shift + 7),
++							fat_tab->aux_ht_cnt[rate_ss_shift + 0], fat_tab->aux_ht_cnt[rate_ss_shift + 1],
++							fat_tab->aux_ht_cnt[rate_ss_shift + 2], fat_tab->aux_ht_cnt[rate_ss_shift + 3],
++							fat_tab->aux_ht_cnt[rate_ss_shift + 4], fat_tab->aux_ht_cnt[rate_ss_shift + 5],
++							fat_tab->aux_ht_cnt[rate_ss_shift + 6], fat_tab->aux_ht_cnt[rate_ss_shift + 7]);
++						}
++
++						/* @3 [EVM statistic] */
++						/*@1SS EVM*/
++						main_1ss_evm = (fat_tab->main_evm_cnt[mac_id] != 0) ? (fat_tab->main_evm_sum[mac_id] / fat_tab->main_evm_cnt[mac_id]) : 0;
++						aux_1ss_evm = (fat_tab->aux_evm_cnt[mac_id] != 0) ? (fat_tab->aux_evm_sum[mac_id] / fat_tab->aux_evm_cnt[mac_id]) : 0;
++						target_ant_evm_1ss = (main_1ss_evm == aux_1ss_evm) ? (fat_tab->pre_target_ant_enhance) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT);
++
++						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main1ss_EVM= ((  %d ))\n", fat_tab->main_evm_cnt[mac_id], main_1ss_evm);
++						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_1ss_EVM = ((  %d ))\n", fat_tab->aux_evm_cnt[mac_id], aux_1ss_evm);
++
++						/*@2SS EVM*/
++						main_2ss_evm[0] = (fat_tab->main_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->main_evm_2ss_sum[mac_id][0] / fat_tab->main_evm_2ss_cnt[mac_id]) : 0;
++						main_2ss_evm[1] = (fat_tab->main_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->main_evm_2ss_sum[mac_id][1] / fat_tab->main_evm_2ss_cnt[mac_id]) : 0;
++						main_2ss_evm_sum = main_2ss_evm[0] + main_2ss_evm[1];
++
++						aux_2ss_evm[0] = (fat_tab->aux_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->aux_evm_2ss_sum[mac_id][0] / fat_tab->aux_evm_2ss_cnt[mac_id]) : 0;
++						aux_2ss_evm[1] = (fat_tab->aux_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->aux_evm_2ss_sum[mac_id][1] / fat_tab->aux_evm_2ss_cnt[mac_id]) : 0;
++						aux_2ss_evm_sum = aux_2ss_evm[0] + aux_2ss_evm[1];
++
++						target_ant_evm_2ss = (main_2ss_evm_sum == aux_2ss_evm_sum) ? (fat_tab->pre_target_ant_enhance) : ((main_2ss_evm_sum >= aux_2ss_evm_sum) ? MAIN_ANT : AUX_ANT);
++
++						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main2ss_EVM{A,B,Sum} = {%d, %d, %d}\n",
++							  fat_tab->main_evm_2ss_cnt[mac_id], main_2ss_evm[0], main_2ss_evm[1], main_2ss_evm_sum);
++						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_2ss_EVM{A,B,Sum} = {%d, %d, %d}\n",
++							  fat_tab->aux_evm_2ss_cnt[mac_id], aux_2ss_evm[0], aux_2ss_evm[1], aux_2ss_evm_sum);
++
++						if ((main_2ss_evm_sum + aux_2ss_evm_sum) != 0) {
++							decision_evm_ss = 2;
++							main_evm = main_2ss_evm_sum;
++							aux_evm = aux_2ss_evm_sum;
++							fat_tab->target_ant_evm = target_ant_evm_2ss;
++						} else {
++							decision_evm_ss = 1;
++							main_evm = main_1ss_evm;
++							aux_evm = aux_1ss_evm;
++							fat_tab->target_ant_evm = target_ant_evm_1ss;
++						}
++
++						if ((main_evm == 0 || aux_evm == 0))
++							diff_EVM = 100;
++						else if (main_evm >= aux_evm)
++							diff_EVM = main_evm - aux_evm;
++						else
++							diff_EVM = aux_evm - main_evm;
++
++						PHYDM_DBG(dm, DBG_ANT_DIV, "***2.TargetAnt_EVM((%d-ss)) = ((%s))\n", decision_evm_ss, (fat_tab->target_ant_evm == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
++
++						//3 [TP statistic]
++						main_tp_avg = (fat_tab->main_tp_cnt != 0) ? (fat_tab->main_tp / fat_tab->main_tp_cnt) : 0;
++						aux_tp_avg = (fat_tab->aux_tp_cnt != 0) ? (fat_tab->aux_tp / fat_tab->aux_tp_cnt) : 0;
++						tp_diff_avg = DIFF_2(main_tp_avg, aux_tp_avg);
++						fat_tab->target_ant_tp = (tp_diff_avg < 100) ? (fat_tab->pre_target_ant_enhance) : ((main_tp_avg >= aux_tp_avg) ? MAIN_ANT : AUX_ANT);
++
++						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main_TP = ((%d))\n", fat_tab->main_tp_cnt, main_tp_avg);
++						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_TP = ((%d))\n", fat_tab->aux_tp_cnt, aux_tp_avg);
++						PHYDM_DBG(dm, DBG_ANT_DIV, "***3.TargetAnt_TP = ((%s))\n", (fat_tab->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
++
++						/*Reset TP Method */
++						fat_tab->main_tp = 0;
++						fat_tab->aux_tp = 0;
++						fat_tab->main_tp_cnt = 0;
++						fat_tab->aux_tp_cnt = 0;
++
++						/* @2 [ Decision state ] */
++						#if 1
++						if (main_max_idx == aux_max_idx && ((main_cnt_all + aux_cnt_all) != 0)) {
++							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision EVM, main_max_idx = ((MCS%d)), aux_max_idx = ((MCS%d))\n", main_max_idx, aux_max_idx);
++							fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
++						} else {
++							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision TP, main_max_idx = ((MCS%d)), aux_max_idx = ((MCS%d))\n", main_max_idx, aux_max_idx);
++							fat_tab->target_ant_enhance = fat_tab->target_ant_tp;
++						}
++						#else
++						if (fat_tab->target_ant_evm == fat_tab->target_ant_crc32) {
++							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
++
++							if ((utility_ratio < 2 && force_antenna == false) && diff_EVM <= 30)
++								fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance;
++							else
++								fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
++						}
++						#if 0
++						else if ((diff_EVM <= 50 && (utility_ratio > 4 && force_antenna == false)) || (force_antenna == true)) {
++							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
++							fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
++						}
++						#endif
++						else if (diff_EVM >= 20) {
++							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
++							fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
++						} else if (utility_ratio >= 6 && force_antenna == false) {
++							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
++							fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
++						} else {
++							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
++
++							if (force_antenna == true)
++								score_CRC = 2;
++							else if (utility_ratio >= 5) /*@>2.5*/
++								score_CRC = 2;
++							else if (utility_ratio >= 4) /*@>2*/
++								score_CRC = 1;
++							else
++								score_CRC = 0;
++
++							if (diff_EVM >= 15)
++								score_EVM = 3;
++							else if (diff_EVM >= 10)
++								score_EVM = 2;
++							else if (diff_EVM >= 5)
++								score_EVM = 1;
++							else
++								score_EVM = 0;
++
++							if (score_CRC > score_EVM)
++								fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
++							else if (score_CRC < score_EVM)
++								fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
++							else
++								fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance;
++						}
++						#endif
++						fat_tab->pre_target_ant_enhance = fat_tab->target_ant_enhance;
++
++						PHYDM_DBG(dm, DBG_ANT_DIV, "*** 4.TargetAnt_enhance = (( %s ))******\n", (fat_tab->target_ant_enhance == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
++					}
++				} else { /* RSSI< = evm_rssi_th_low */
++					PHYDM_DBG(dm, DBG_ANT_DIV, "[ <TH_L: escape from > TH_L ]\n");
++					odm_evm_fast_ant_reset(dm);
++				}
++			} else {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "[escape from> TH_H || evm_method_enable==1]\n");
++				odm_evm_fast_ant_reset(dm);
++			}
++		} else {
++			PHYDM_DBG(dm, DBG_ANT_DIV, "[multi-Client]\n");
++			odm_evm_fast_ant_reset(dm);
++		}
++	}
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void phydm_evm_antdiv_callback(
++	struct phydm_timer_list *timer)
++{
++	void *adapter = (void *)timer->Adapter;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++
++	#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++	#if USE_WORKITEM
++	odm_schedule_work_item(&dm->phydm_evm_antdiv_workitem);
++	#else
++	{
++		odm_hw_ant_div(dm);
++	}
++	#endif
++	#else
++	odm_schedule_work_item(&dm->phydm_evm_antdiv_workitem);
++	#endif
++}
++
++void phydm_evm_antdiv_workitem_callback(
++	void *context)
++{
++	void *adapter = (void *)context;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++
++	odm_hw_ant_div(dm);
++}
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++void phydm_evm_antdiv_callback(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	void *padapter = dm->adapter;
++
++	if (*dm->is_net_closed)
++		return;
++	if (dm->support_interface == ODM_ITRF_PCIE) {
++		odm_hw_ant_div(dm);
++	} else {
++		/* @Can't do I/O in timer callback*/
++		phydm_run_in_thread_cmd(dm,
++					phydm_evm_antdiv_workitem_callback,
++					padapter);
++	}
++}
++
++void phydm_evm_antdiv_workitem_callback(void *context)
++{
++	void *adapter = (void *)context;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->odmpriv;
++
++	odm_hw_ant_div(dm);
++}
++
++#else
++void phydm_evm_antdiv_callback(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "******AntDiv_Callback******\n");
++	odm_hw_ant_div(dm);
++}
++#endif
++
++#endif
++
++void odm_hw_ant_div(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 i, min_max_rssi = 0xFF, ant_div_max_rssi = 0, max_rssi = 0;
++	u32 main_rssi, aux_rssi, mian_cnt, aux_cnt, local_max_rssi;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	u8 rx_idle_ant = fat_tab->rx_idle_ant, target_ant = 7;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct cmn_sta_info *sta;
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
++	u32 TH1 = 500000;
++	u32 TH2 = 10000000;
++	u32 ma_rx_temp, degrade_TP_temp, improve_TP_temp;
++	u8 monitor_rssi_threshold = 30;
++
++	dm_bdc_table->BF_pass = true;
++	dm_bdc_table->DIV_pass = true;
++	dm_bdc_table->is_all_div_sta_idle = true;
++	dm_bdc_table->is_all_bf_sta_idle = true;
++	dm_bdc_table->num_bf_tar = 0;
++	dm_bdc_table->num_div_tar = 0;
++	dm_bdc_table->num_client = 0;
++#endif
++#endif
++
++	if (!dm->is_linked) { /* @is_linked==False */
++		PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
++
++		if (fat_tab->is_become_linked) {
++			if (fat_tab->div_path_type == ANT_PATH_A)
++				odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
++			else if (fat_tab->div_path_type == ANT_PATH_B)
++				odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
++			else if (fat_tab->div_path_type == ANT_PATH_AB)
++				odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
++			odm_update_rx_idle_ant(dm, MAIN_ANT);
++			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
++			dm->antdiv_period = 0;
++
++			fat_tab->is_become_linked = dm->is_linked;
++		}
++		return;
++	} else {
++		if (!fat_tab->is_become_linked) {
++			PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
++			if (fat_tab->div_path_type == ANT_PATH_A)
++				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
++			else if (fat_tab->div_path_type == ANT_PATH_B)
++				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
++			else if (fat_tab->div_path_type == ANT_PATH_AB)
++				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
++			#if 0
++			/*odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);*/
++
++			/* @if(dm->support_ic_type == ODM_RTL8821 ) */
++			/* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */
++			/* CCK AntDiv function disable */
++
++			/* @#if(DM_ODM_SUPPORT_TYPE  == ODM_AP) */
++			/* @else if(dm->support_ic_type == ODM_RTL8881A) */
++			/* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */
++			/* CCK AntDiv function disable */
++			/* @#endif */
++
++			/* @else if(dm->support_ic_type == ODM_RTL8723B ||*/
++			/* @dm->support_ic_type == ODM_RTL8812) */
++			/* odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); */
++			/* CCK AntDiv function disable */
++			#endif
++
++			fat_tab->is_become_linked = dm->is_linked;
++
++			if (dm->support_ic_type == ODM_RTL8723B &&
++			    dm->ant_div_type == CG_TRX_HW_ANTDIV) {
++				odm_set_bb_reg(dm, R_0x930, 0xF0, 8);
++				/* @DPDT_P = ANTSEL[0] for 8723B AntDiv */
++				odm_set_bb_reg(dm, R_0x930, 0xF, 8);
++				/* @DPDT_N = ANTSEL[0] */
++			}
++
++			/* @ BDC Init */
++			#ifdef PHYDM_BEAMFORMING_SUPPORT
++			#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++			odm_bdc_init(dm);
++			#endif
++			#endif
++
++			#ifdef ODM_EVM_ENHANCE_ANTDIV
++			odm_evm_fast_ant_reset(dm);
++			#endif
++		}
++	}
++
++	if (!(*fat_tab->p_force_tx_by_desc)) {
++		if (dm->is_one_entry_only)
++			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
++		else
++			odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
++	}
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++	if (dm->antdiv_evm_en == 1) {
++		odm_evm_enhance_ant_div(dm);
++		if (fat_tab->fat_state_cnt != 0)
++			return;
++	} else
++		odm_evm_fast_ant_reset(dm);
++#endif
++
++/* @2 BDC mode Arbitration */
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0)
++		odm_bf_ant_div_mode_arbitration(dm);
++#endif
++#endif
++
++	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
++		sta = dm->phydm_sta_info[i];
++		if (!is_sta_active(sta)) {
++			phydm_antdiv_reset_statistic(dm, i);
++			continue;
++		}
++
++		/* @2 Caculate RSSI per Antenna */
++		if (fat_tab->main_cnt[i] != 0 || fat_tab->aux_cnt[i] != 0) {
++			mian_cnt = fat_tab->main_cnt[i];
++			aux_cnt = fat_tab->aux_cnt[i];
++			main_rssi = (mian_cnt != 0) ?
++				    (fat_tab->main_sum[i] / mian_cnt) : 0;
++			aux_rssi = (aux_cnt != 0) ?
++				   (fat_tab->aux_sum[i] / aux_cnt) : 0;
++			target_ant = (mian_cnt == aux_cnt) ?
++				     fat_tab->rx_idle_ant :
++				     ((mian_cnt >= aux_cnt) ?
++				     MAIN_ANT : AUX_ANT);
++				     /*Use counter number for OFDM*/
++
++		} else { /*@CCK only case*/
++			mian_cnt = fat_tab->main_cnt_cck[i];
++			aux_cnt = fat_tab->aux_cnt_cck[i];
++			main_rssi = (mian_cnt != 0) ?
++				    (fat_tab->main_sum_cck[i] / mian_cnt) : 0;
++			aux_rssi = (aux_cnt != 0) ?
++				   (fat_tab->aux_sum_cck[i] / aux_cnt) : 0;
++			target_ant = (main_rssi == aux_rssi) ?
++				     fat_tab->rx_idle_ant :
++				     ((main_rssi >= aux_rssi) ?
++				     MAIN_ANT : AUX_ANT);
++				     /*Use RSSI for CCK only case*/
++		}
++
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "*** Client[ %d ] : Main_Cnt = (( %d ))  ,  CCK_Main_Cnt = (( %d )) ,  main_rssi= ((  %d ))\n",
++			  i, fat_tab->main_cnt[i],
++			  fat_tab->main_cnt_cck[i], main_rssi);
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "*** Client[ %d ] : Aux_Cnt   = (( %d ))  , CCK_Aux_Cnt   = (( %d )) ,  aux_rssi = ((  %d ))\n",
++			  i, fat_tab->aux_cnt[i],
++			  fat_tab->aux_cnt_cck[i], aux_rssi);
++
++		local_max_rssi = (main_rssi > aux_rssi) ? main_rssi : aux_rssi;
++		/* @ Select max_rssi for DIG */
++		if (local_max_rssi > ant_div_max_rssi && local_max_rssi < 40)
++			ant_div_max_rssi = local_max_rssi;
++		if (local_max_rssi > max_rssi)
++			max_rssi = local_max_rssi;
++
++		/* @ Select RX Idle Antenna */
++		if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) {
++			rx_idle_ant = target_ant;
++			min_max_rssi = local_max_rssi;
++		}
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++		if (dm->antdiv_evm_en == 1) {
++			if (fat_tab->target_ant_enhance != 0xFF) {
++				target_ant = fat_tab->target_ant_enhance;
++				rx_idle_ant = fat_tab->target_ant_enhance;
++			}
++		}
++#endif
++
++		/* @2 Select TX Antenna */
++		if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
++			#ifdef PHYDM_BEAMFORMING_SUPPORT
++			#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++			if (dm_bdc_table->w_bfee_client[i] == 0)
++			#endif
++			#endif
++			{
++				odm_update_tx_ant(dm, target_ant, i);
++			}
++		}
++
++/* @------------------------------------------------------------ */
++
++		#ifdef PHYDM_BEAMFORMING_SUPPORT
++		#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++
++		dm_bdc_table->num_client++;
++
++		if (dm_bdc_table->bdc_mode == BDC_MODE_2 || dm_bdc_table->bdc_mode == BDC_MODE_3) {
++			/* @2 Byte counter */
++
++			ma_rx_temp = sta->rx_moving_average_tp; /* RX  TP   ( bit /sec) */
++
++			if (dm_bdc_table->BDC_state == bdc_bfer_train_state)
++				dm_bdc_table->MA_rx_TP_DIV[i] = ma_rx_temp;
++			else
++				dm_bdc_table->MA_rx_TP[i] = ma_rx_temp;
++
++			if (ma_rx_temp < TH2 && ma_rx_temp > TH1 && local_max_rssi <= monitor_rssi_threshold) {
++				if (dm_bdc_table->w_bfer_client[i] == 1) { /* @Bfer_Target */
++					dm_bdc_table->num_bf_tar++;
++
++					if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) {
++						improve_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 9) >> 3; /* @* 1.125 */
++						dm_bdc_table->BF_pass = (dm_bdc_table->MA_rx_TP[i] > improve_TP_temp) ? true : false;
++						PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] :  { MA_rx_TP,improve_TP_temp, MA_rx_TP_DIV,  BF_pass}={ %d,  %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], improve_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->BF_pass);
++					}
++				} else { /* @DIV_Target */
++					dm_bdc_table->num_div_tar++;
++
++					if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) {
++						degrade_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 5) >> 3; /* @* 0.625 */
++						dm_bdc_table->DIV_pass = (dm_bdc_table->MA_rx_TP[i] > degrade_TP_temp) ? true : false;
++						PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] :  { MA_rx_TP, degrade_TP_temp, MA_rx_TP_DIV,  DIV_pass}=\n{ %d,  %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], degrade_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->DIV_pass);
++					}
++				}
++			}
++
++			if (ma_rx_temp > TH1) {
++				if (dm_bdc_table->w_bfer_client[i] == 1) /* @Bfer_Target */
++					dm_bdc_table->is_all_bf_sta_idle = false;
++				else /* @DIV_Target */
++					dm_bdc_table->is_all_div_sta_idle = false;
++			}
++
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "*** Client[ %d ] :  { BFmeeCap, BFmerCap}  = { %d , %d }\n",
++				  i, dm_bdc_table->w_bfee_client[i],
++				  dm_bdc_table->w_bfer_client[i]);
++
++			if (dm_bdc_table->BDC_state == bdc_bfer_train_state)
++				PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] :    MA_rx_TP_DIV = (( %d ))\n", i, dm_bdc_table->MA_rx_TP_DIV[i]);
++
++			else
++				PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] :    MA_rx_TP = (( %d ))\n", i, dm_bdc_table->MA_rx_TP[i]);
++		}
++		#endif
++		#endif
++
++		#ifdef PHYDM_BEAMFORMING_SUPPORT
++		#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++		if (dm_bdc_table->bdc_try_flag == 0)
++		#endif
++		#endif
++		{
++			phydm_antdiv_reset_statistic(dm, i);
++		}
++	}
++
++/* @2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) */
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	PHYDM_DBG(dm, DBG_ANT_DIV, "*** rx_idle_ant = (( %s ))\n",
++		  (rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	if (dm_bdc_table->bdc_mode == BDC_MODE_1 || dm_bdc_table->bdc_mode == BDC_MODE_3) {
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "*** bdc_rx_idle_update_counter = (( %d ))\n",
++			  dm_bdc_table->bdc_rx_idle_update_counter);
++
++		if (dm_bdc_table->bdc_rx_idle_update_counter == 1) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "***Update RxIdle Antenna!!!\n");
++			dm_bdc_table->bdc_rx_idle_update_counter = 30;
++			odm_update_rx_idle_ant(dm, rx_idle_ant);
++		} else {
++			dm_bdc_table->bdc_rx_idle_update_counter--;
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "***NOT update RxIdle Antenna because of BF  ( need to fix TX-ant)\n");
++		}
++	} else
++#endif
++#endif
++		odm_update_rx_idle_ant(dm, rx_idle_ant);
++#else
++
++	odm_update_rx_idle_ant(dm, rx_idle_ant);
++
++#endif /* @#if(DM_ODM_SUPPORT_TYPE  == ODM_AP) */
++
++/* @2 BDC Main Algorithm */
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0)
++		odm_bd_ccoex_bfee_rx_div_arbitration(dm);
++
++	dm_bdc_table->num_txbfee_client = 0;
++	dm_bdc_table->num_txbfer_client = 0;
++#endif
++#endif
++
++	if (ant_div_max_rssi == 0)
++		dig_t->ant_div_rssi_max = dm->rssi_min;
++	else
++		dig_t->ant_div_rssi_max = ant_div_max_rssi;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "***AntDiv End***\n\n");
++}
++
++#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++
++void odm_s0s1_sw_ant_div_reset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	fat_tab->is_become_linked = false;
++	swat_tab->try_flag = SWAW_STEP_INIT;
++	swat_tab->double_chk_flag = 0;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "%s: fat_tab->is_become_linked = %d\n",
++		  __func__, fat_tab->is_become_linked);
++}
++
++void phydm_sw_antdiv_train_time(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
++	u8 high_traffic_train_time_u = 0x32, high_traffic_train_time_l = 0;
++	u8 low_traffic_train_time_u = 200, low_traffic_train_time_l = 0;
++	u8 train_time_temp;
++
++	if (dm->traffic_load == TRAFFIC_HIGH) {
++		train_time_temp = swat_tab->train_time;
++
++		if (swat_tab->train_time_flag == 3) {
++			high_traffic_train_time_l = 0xa;
++
++			if (train_time_temp <= 16)
++				train_time_temp = high_traffic_train_time_l;
++			else
++				train_time_temp -= 16;
++
++		} else if (swat_tab->train_time_flag == 2) {
++			train_time_temp -= 8;
++			high_traffic_train_time_l = 0xf;
++		} else if (swat_tab->train_time_flag == 1) {
++			train_time_temp -= 4;
++			high_traffic_train_time_l = 0x1e;
++		} else if (swat_tab->train_time_flag == 0) {
++			train_time_temp += 8;
++			high_traffic_train_time_l = 0x28;
++		}
++
++		if (dm->support_ic_type == ODM_RTL8188F) {
++			if (dm->support_interface == ODM_ITRF_SDIO)
++				high_traffic_train_time_l += 0xa;
++		}
++
++		/* @-- */
++		if (train_time_temp > high_traffic_train_time_u)
++			train_time_temp = high_traffic_train_time_u;
++
++		else if (train_time_temp < high_traffic_train_time_l)
++			train_time_temp = high_traffic_train_time_l;
++
++		swat_tab->train_time = train_time_temp; /*@10ms~200ms*/
++
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "train_time_flag=((%d)), train_time=((%d))\n",
++			  swat_tab->train_time_flag,
++			  swat_tab->train_time);
++
++	} else if ((dm->traffic_load == TRAFFIC_MID) ||
++		   (dm->traffic_load == TRAFFIC_LOW)) {
++		train_time_temp = swat_tab->train_time;
++
++		if (swat_tab->train_time_flag == 3) {
++			low_traffic_train_time_l = 10;
++			if (train_time_temp < 50)
++				train_time_temp = low_traffic_train_time_l;
++			else
++				train_time_temp -= 50;
++		} else if (swat_tab->train_time_flag == 2) {
++			train_time_temp -= 30;
++			low_traffic_train_time_l = 36;
++		} else if (swat_tab->train_time_flag == 1) {
++			train_time_temp -= 10;
++			low_traffic_train_time_l = 40;
++		} else {
++			train_time_temp += 10;
++			low_traffic_train_time_l = 50;
++		}
++
++		if (dm->support_ic_type == ODM_RTL8188F) {
++			if (dm->support_interface == ODM_ITRF_SDIO)
++				low_traffic_train_time_l += 10;
++		}
++
++		/* @-- */
++		if (train_time_temp >= low_traffic_train_time_u)
++			train_time_temp = low_traffic_train_time_u;
++
++		else if (train_time_temp <= low_traffic_train_time_l)
++			train_time_temp = low_traffic_train_time_l;
++
++		swat_tab->train_time = train_time_temp; /*@10ms~200ms*/
++
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "train_time_flag=((%d)) , train_time=((%d))\n",
++			  swat_tab->train_time_flag, swat_tab->train_time);
++
++	} else {
++		swat_tab->train_time = 0xc8; /*@200ms*/
++	}
++}
++
++void phydm_sw_antdiv_decision(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	u32 i, min_max_rssi = 0xFF, local_max_rssi, local_min_rssi;
++	u32 main_rssi, aux_rssi;
++	u8 rx_idle_ant = swat_tab->pre_ant;
++	u8 target_ant = swat_tab->pre_ant, next_ant = 0;
++	struct cmn_sta_info *entry = NULL;
++	u32 main_cnt = 0, aux_cnt = 0, main_sum = 0, aux_sum = 0;
++	u32 main_ctrl_cnt = 0, aux_ctrl_cnt = 0;
++	boolean is_by_ctrl_frame = false;
++	boolean cond_23d_main, cond_23d_aux;
++	u64 pkt_cnt_total = 0;
++
++	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
++		entry = dm->phydm_sta_info[i];
++		if (!is_sta_active(entry)) {
++			phydm_antdiv_reset_statistic(dm, i);
++			continue;
++		}
++
++		/* @2 Caculate RSSI per Antenna */
++		if (fat_tab->main_cnt[i] != 0 || fat_tab->aux_cnt[i] != 0) {
++			main_cnt = (u32)fat_tab->main_cnt[i];
++			aux_cnt = (u32)fat_tab->aux_cnt[i];
++			main_rssi = (main_cnt != 0) ?
++				    (fat_tab->main_sum[i] / main_cnt) : 0;
++			aux_rssi = (aux_cnt != 0) ?
++				   (fat_tab->aux_sum[i] / aux_cnt) : 0;
++			if (dm->support_ic_type == ODM_RTL8723D) {
++				cond_23d_main = (aux_cnt > main_cnt) &&
++						((main_rssi - aux_rssi < 5) ||
++						(aux_rssi > main_rssi));
++				cond_23d_aux = (main_cnt > aux_cnt) &&
++					       ((aux_rssi - main_rssi < 5) ||
++					       (main_rssi > aux_rssi));
++				if (swat_tab->pre_ant == MAIN_ANT) {
++					if (main_cnt == 0)
++						target_ant = (aux_cnt != 0) ?
++							     AUX_ANT :
++							     swat_tab->pre_ant;
++					else
++						target_ant = cond_23d_main ?
++							     AUX_ANT :
++							     swat_tab->pre_ant;
++				} else {
++					if (aux_cnt == 0)
++						target_ant = (main_cnt != 0) ?
++							     MAIN_ANT :
++							     swat_tab->pre_ant;
++					else
++						target_ant = cond_23d_aux ?
++							     MAIN_ANT :
++							     swat_tab->pre_ant;
++				}
++			} else {
++				if (swat_tab->pre_ant == MAIN_ANT) {
++					target_ant = (aux_rssi > main_rssi) ?
++						     AUX_ANT :
++						     swat_tab->pre_ant;
++				} else if (swat_tab->pre_ant == AUX_ANT) {
++					target_ant = (main_rssi > aux_rssi) ?
++						     MAIN_ANT :
++						     swat_tab->pre_ant;
++				}
++			}
++		} else { /*@CCK only case*/
++			main_cnt = fat_tab->main_cnt_cck[i];
++			aux_cnt = fat_tab->aux_cnt_cck[i];
++			main_rssi = (main_cnt != 0) ?
++				    (fat_tab->main_sum_cck[i] / main_cnt) : 0;
++			aux_rssi = (aux_cnt != 0) ?
++				   (fat_tab->aux_sum_cck[i] / aux_cnt) : 0;
++			target_ant = (main_rssi == aux_rssi) ?
++				     swat_tab->pre_ant :
++				     ((main_rssi >= aux_rssi) ?
++				     MAIN_ANT : AUX_ANT);
++				     /*Use RSSI for CCK only case*/
++		}
++		local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi;
++		local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi;
++
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "***  CCK_counter_main = (( %d ))  , CCK_counter_aux= ((  %d ))\n",
++			  fat_tab->main_cnt_cck[i], fat_tab->aux_cnt_cck[i]);
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "***  OFDM_counter_main = (( %d ))  , OFDM_counter_aux= ((  %d ))\n",
++			  fat_tab->main_cnt[i], fat_tab->aux_cnt[i]);
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "***  main_Cnt = (( %d ))  , aux_Cnt   = (( %d ))\n",
++			  main_cnt, aux_cnt);
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "***  main_rssi= ((  %d )) , aux_rssi = ((  %d ))\n",
++			  main_rssi, aux_rssi);
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i,
++			  (target_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
++
++		/* @2 Select RX Idle Antenna */
++
++		if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) {
++			rx_idle_ant = target_ant;
++			min_max_rssi = local_max_rssi;
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "*** local_max_rssi-local_min_rssi = ((%d))\n",
++				  (local_max_rssi - local_min_rssi));
++
++			if ((local_max_rssi - local_min_rssi) > 8) {
++				if (local_min_rssi != 0) {
++					swat_tab->train_time_flag = 3;
++				} else {
++					if (min_max_rssi > RSSI_CHECK_THRESHOLD)
++						swat_tab->train_time_flag = 0;
++					else
++						swat_tab->train_time_flag = 3;
++				}
++			} else if ((local_max_rssi - local_min_rssi) > 5) {
++				swat_tab->train_time_flag = 2;
++			} else if ((local_max_rssi - local_min_rssi) > 2) {
++				swat_tab->train_time_flag = 1;
++			} else {
++				swat_tab->train_time_flag = 0;
++			}
++		}
++
++		/* @2 Select TX Antenna */
++		if (target_ant == MAIN_ANT)
++			fat_tab->antsel_a[i] = ANT1_2G;
++		else
++			fat_tab->antsel_a[i] = ANT2_2G;
++
++		phydm_antdiv_reset_statistic(dm, i);
++		pkt_cnt_total += (main_cnt + aux_cnt);
++	}
++
++	if (swat_tab->is_sw_ant_div_by_ctrl_frame) {
++		odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_DETERMINE);
++		is_by_ctrl_frame = true;
++	}
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "Control frame packet counter = %d, data frame packet counter = %llu\n",
++		  swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame, pkt_cnt_total);
++
++	if (min_max_rssi == 0xff || ((pkt_cnt_total <
++	    (swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame >> 1)) &&
++	    dm->phy_dbg_info.num_qry_beacon_pkt < 2)) {
++		min_max_rssi = 0;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "Check RSSI of control frame because min_max_rssi == 0xff\n");
++		PHYDM_DBG(dm, DBG_ANT_DIV, "is_by_ctrl_frame = %d\n",
++			  is_by_ctrl_frame);
++
++		if (is_by_ctrl_frame) {
++			main_ctrl_cnt = fat_tab->main_ctrl_cnt;
++			aux_ctrl_cnt = fat_tab->aux_ctrl_cnt;
++			main_rssi = (main_ctrl_cnt != 0) ?
++				    (fat_tab->main_ctrl_sum / main_ctrl_cnt) :
++				    0;
++			aux_rssi = (aux_ctrl_cnt != 0) ?
++				   (fat_tab->aux_ctrl_sum / aux_ctrl_cnt) : 0;
++
++			if (main_ctrl_cnt <= 1 &&
++			    fat_tab->cck_ctrl_frame_cnt_main >= 1)
++				main_rssi = 0;
++
++			if (aux_ctrl_cnt <= 1 &&
++			    fat_tab->cck_ctrl_frame_cnt_aux >= 1)
++				aux_rssi = 0;
++
++			if (main_rssi != 0 || aux_rssi != 0) {
++				rx_idle_ant = (main_rssi == aux_rssi) ?
++					      swat_tab->pre_ant :
++					      ((main_rssi >= aux_rssi) ?
++					      MAIN_ANT : AUX_ANT);
++				local_max_rssi = (main_rssi >= aux_rssi) ?
++						 main_rssi : aux_rssi;
++				local_min_rssi = (main_rssi >= aux_rssi) ?
++						 aux_rssi : main_rssi;
++
++				if ((local_max_rssi - local_min_rssi) > 8)
++					swat_tab->train_time_flag = 3;
++				else if ((local_max_rssi - local_min_rssi) > 5)
++					swat_tab->train_time_flag = 2;
++				else if ((local_max_rssi - local_min_rssi) > 2)
++					swat_tab->train_time_flag = 1;
++				else
++					swat_tab->train_time_flag = 0;
++
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "Control frame: main_rssi = %d, aux_rssi = %d\n",
++					  main_rssi, aux_rssi);
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "rx_idle_ant decided by control frame = %s\n",
++					  (rx_idle_ant == MAIN_ANT ?
++					  "MAIN" : "AUX"));
++			}
++		}
++	}
++
++	fat_tab->min_max_rssi = min_max_rssi;
++	swat_tab->try_flag = SWAW_STEP_PEEK;
++
++	if (swat_tab->double_chk_flag == 1) {
++		swat_tab->double_chk_flag = 0;
++
++		if (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  " [Double check] min_max_rssi ((%d)) > %d again!!\n",
++				  fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD);
++
++			odm_update_rx_idle_ant(dm, rx_idle_ant);
++
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[reset try_flag = 0] Training accomplished !!!]\n\n\n");
++		} else {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  " [Double check] min_max_rssi ((%d)) <= %d !!\n",
++				  fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD);
++
++			next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ?
++				   AUX_ANT : MAIN_ANT;
++			swat_tab->try_flag = SWAW_STEP_PEEK;
++			swat_tab->reset_idx = RSSI_CHECK_RESET_PERIOD;
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[set try_flag=0]  Normal state:  Need to tryg again!!\n\n\n");
++		}
++	} else {
++		if (fat_tab->min_max_rssi < RSSI_CHECK_THRESHOLD)
++			swat_tab->reset_idx = RSSI_CHECK_RESET_PERIOD;
++
++		swat_tab->pre_ant = rx_idle_ant;
++		odm_update_rx_idle_ant(dm, rx_idle_ant);
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[reset try_flag = 0] Training accomplished !!!]\n\n\n");
++	}
++}
++
++void odm_s0s1_sw_ant_div(void *dm_void, u8 step)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	u32 value32;
++	u8 next_ant = 0;
++
++	if (!dm->is_linked) { /* @is_linked==False */
++		PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
++		if (fat_tab->is_become_linked == true) {
++			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
++			if (dm->support_ic_type == ODM_RTL8723B) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "Set REG 948[9:6]=0x0\n");
++				odm_set_bb_reg(dm, R_0x948, 0x3c0, 0x0);
++			}
++			fat_tab->is_become_linked = dm->is_linked;
++		}
++		return;
++	} else {
++		if (fat_tab->is_become_linked == false) {
++			PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
++
++			if (dm->support_ic_type == ODM_RTL8723B) {
++				value32 = odm_get_bb_reg(dm, R_0x864, 0x38);
++
++#if (RTL8723B_SUPPORT == 1)
++				if (value32 == 0x0)
++					odm_update_rx_idle_ant_8723b(dm,
++								     MAIN_ANT,
++								     ANT1_2G,
++								     ANT2_2G);
++				else if (value32 == 0x1)
++					odm_update_rx_idle_ant_8723b(dm,
++								     AUX_ANT,
++								     ANT2_2G,
++								     ANT1_2G);
++#endif
++
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "8723B: First link! Force antenna to  %s\n",
++					  (value32 == 0x0 ? "MAIN" : "AUX"));
++			}
++
++			if (dm->support_ic_type == ODM_RTL8723D) {
++				value32 = odm_get_bb_reg(dm, R_0x864, 0x38);
++#if (RTL8723D_SUPPORT == 1)
++				if (value32 == 0x0)
++					odm_update_rx_idle_ant_8723d(dm,
++								     MAIN_ANT,
++								     ANT1_2G,
++								     ANT2_2G);
++				else if (value32 == 0x1)
++					odm_update_rx_idle_ant_8723d(dm,
++								     AUX_ANT,
++								     ANT2_2G,
++								     ANT1_2G);
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "8723D: First link! Force antenna to  %s\n",
++					  (value32 == 0x0 ? "MAIN" : "AUX"));
++#endif
++			}
++			fat_tab->is_become_linked = dm->is_linked;
++		}
++	}
++
++	if (!(*fat_tab->p_force_tx_by_desc)) {
++		if (dm->is_one_entry_only == true)
++			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
++		else
++			odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
++	}
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[%d] { try_flag=(( %d )), step=(( %d )), double_chk_flag = (( %d )) }\n",
++		  __LINE__, swat_tab->try_flag, step,
++		  swat_tab->double_chk_flag);
++
++	/* @ Handling step mismatch condition. */
++	/* @ Peak step is not finished at last time. */
++	/* @ Recover the variable and check again. */
++	if (step != swat_tab->try_flag) {
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[step != try_flag]    Need to Reset After Link\n");
++		odm_sw_ant_div_rest_after_link(dm);
++	}
++
++	if (swat_tab->try_flag == SWAW_STEP_INIT) {
++		swat_tab->try_flag = SWAW_STEP_PEEK;
++		swat_tab->train_time_flag = 0;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[set try_flag = 0]  Prepare for peek!\n\n");
++		return;
++
++	} else {
++		/* @1 Normal state (Begin Trying) */
++		if (swat_tab->try_flag == SWAW_STEP_PEEK) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), traffic_load = (%d))\n",
++				  dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt,
++				  dm->traffic_load);
++			phydm_sw_antdiv_train_time(dm);
++
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "Current min_max_rssi is ((%d))\n",
++				  fat_tab->min_max_rssi);
++
++			/* @---reset index--- */
++			if (swat_tab->reset_idx >= RSSI_CHECK_RESET_PERIOD) {
++				fat_tab->min_max_rssi = 0;
++				swat_tab->reset_idx = 0;
++			}
++			PHYDM_DBG(dm, DBG_ANT_DIV, "reset_idx = (( %d ))\n",
++				  swat_tab->reset_idx);
++
++			swat_tab->reset_idx++;
++
++			/* @---double check flag--- */
++			if (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD &&
++			    swat_tab->double_chk_flag == 0) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  " min_max_rssi is ((%d)), and > %d\n",
++					  fat_tab->min_max_rssi,
++					  RSSI_CHECK_THRESHOLD);
++
++				swat_tab->double_chk_flag = 1;
++				swat_tab->try_flag = SWAW_STEP_DETERMINE;
++				swat_tab->rssi_trying = 0;
++
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "Test the current ant for (( %d )) ms again\n",
++					  swat_tab->train_time);
++				odm_update_rx_idle_ant(dm,
++						       fat_tab->rx_idle_ant);
++				odm_set_timer(dm, &swat_tab->sw_antdiv_timer,
++					      swat_tab->train_time); /*@ms*/
++				return;
++			}
++
++			next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ?
++				   AUX_ANT : MAIN_ANT;
++
++			swat_tab->try_flag = SWAW_STEP_DETERMINE;
++
++			if (swat_tab->reset_idx <= 1)
++				swat_tab->rssi_trying = 2;
++			else
++				swat_tab->rssi_trying = 1;
++
++			odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_PEEK);
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[set try_flag=1]  Normal state:  Begin Trying!!\n");
++
++		} else if ((swat_tab->try_flag == SWAW_STEP_DETERMINE) &&
++			   (swat_tab->double_chk_flag == 0)) {
++			next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ?
++				   AUX_ANT : MAIN_ANT;
++			swat_tab->rssi_trying--;
++		}
++
++		/* @1 Decision state */
++		if (swat_tab->try_flag == SWAW_STEP_DETERMINE &&
++		    swat_tab->rssi_trying == 0) {
++			phydm_sw_antdiv_decision(dm);
++			return;
++		}
++	}
++
++	/* @1 4.Change TRX antenna */
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "rssi_trying = (( %d )),    ant: (( %s )) >>> (( %s ))\n",
++		  swat_tab->rssi_trying,
++		  (fat_tab->rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"),
++		  (next_ant == MAIN_ANT ? "MAIN" : "AUX"));
++
++	odm_update_rx_idle_ant(dm, next_ant);
++
++	/* @1 5.Reset Statistics */
++
++	fat_tab->rx_idle_ant = next_ant;
++
++	if (dm->support_ic_type == ODM_RTL8723D) {
++		if (fat_tab->rx_idle_ant == MAIN_ANT) {
++			fat_tab->main_sum[0] = 0;
++			fat_tab->main_cnt[0] = 0;
++			fat_tab->main_sum_cck[0] = 0;
++			fat_tab->main_cnt_cck[0] = 0;
++		} else {
++			fat_tab->aux_sum[0] = 0;
++			fat_tab->aux_cnt[0] = 0;
++			fat_tab->aux_sum_cck[0] = 0;
++			fat_tab->aux_cnt_cck[0] = 0;
++		}
++	}
++
++	if (dm->support_ic_type == ODM_RTL8188F) {
++		if (dm->support_interface == ODM_ITRF_SDIO) {
++			ODM_delay_us(200);
++
++			if (fat_tab->rx_idle_ant == MAIN_ANT) {
++				fat_tab->main_sum[0] = 0;
++				fat_tab->main_cnt[0] = 0;
++				fat_tab->main_sum_cck[0] = 0;
++				fat_tab->main_cnt_cck[0] = 0;
++			} else {
++				fat_tab->aux_sum[0] = 0;
++				fat_tab->aux_cnt[0] = 0;
++				fat_tab->aux_sum_cck[0] = 0;
++				fat_tab->aux_cnt_cck[0] = 0;
++			}
++		}
++	}
++	/* @1 6.Set next timer   (Trying state) */
++	PHYDM_DBG(dm, DBG_ANT_DIV, " Test ((%s)) ant for (( %d )) ms\n",
++		  (next_ant == MAIN_ANT ? "MAIN" : "AUX"),
++		  swat_tab->train_time);
++	odm_set_timer(dm, &swat_tab->sw_antdiv_timer, swat_tab->train_time);
++								/*@ms*/
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void odm_sw_antdiv_callback(struct phydm_timer_list *timer)
++{
++	void *adapter = (void *)timer->Adapter;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct sw_antenna_switch *swat_tab = &hal_data->DM_OutSrc.dm_swat_table;
++
++#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++#if USE_WORKITEM
++	odm_schedule_work_item(&swat_tab->phydm_sw_antenna_switch_workitem);
++#else
++	{
++#if 0
++		/* @dbg_print("SW_antdiv_Callback"); */
++#endif
++		odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE);
++	}
++#endif
++#else
++	odm_schedule_work_item(&swat_tab->phydm_sw_antenna_switch_workitem);
++#endif
++}
++
++void odm_sw_antdiv_workitem_callback(void *context)
++{
++	void *adapter = (void *)context;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++
++#if 0
++	/* @dbg_print("SW_antdiv_Workitem_Callback"); */
++#endif
++	odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE);
++}
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++
++void odm_sw_antdiv_workitem_callback(void *context)
++{
++	void *
++		adapter = (void *)context;
++	HAL_DATA_TYPE
++	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++
++#if 0
++	/*@dbg_print("SW_antdiv_Workitem_Callback");*/
++#endif
++	odm_s0s1_sw_ant_div(&hal_data->odmpriv, SWAW_STEP_DETERMINE);
++}
++
++void odm_sw_antdiv_callback(void *function_context)
++{
++	struct dm_struct *dm = (struct dm_struct *)function_context;
++	void *padapter = dm->adapter;
++	if (*dm->is_net_closed == true)
++		return;
++
++#if 0 /* @Can't do I/O in timer callback*/
++	odm_s0s1_sw_ant_div(dm, SWAW_STEP_DETERMINE);
++#else
++	rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback,
++			      padapter);
++#endif
++}
++
++#endif
++
++void odm_s0s1_sw_ant_div_by_ctrl_frame(void *dm_void, u8 step)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	switch (step) {
++	case SWAW_STEP_PEEK:
++		swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame = 0;
++		swat_tab->is_sw_ant_div_by_ctrl_frame = true;
++		fat_tab->main_ctrl_cnt = 0;
++		fat_tab->aux_ctrl_cnt = 0;
++		fat_tab->main_ctrl_sum = 0;
++		fat_tab->aux_ctrl_sum = 0;
++		fat_tab->cck_ctrl_frame_cnt_main = 0;
++		fat_tab->cck_ctrl_frame_cnt_aux = 0;
++		fat_tab->ofdm_ctrl_frame_cnt_main = 0;
++		fat_tab->ofdm_ctrl_frame_cnt_aux = 0;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\n");
++		break;
++	case SWAW_STEP_DETERMINE:
++		swat_tab->is_sw_ant_div_by_ctrl_frame = false;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "odm_S0S1_SwAntDivForAPMode(): Stop peek\n");
++		break;
++	default:
++		swat_tab->is_sw_ant_div_by_ctrl_frame = false;
++		break;
++	}
++}
++
++void odm_antsel_statistics_ctrl(void *dm_void, u8 antsel_tr_mux,
++				u32 rx_pwdb_all)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	if (antsel_tr_mux == ANT1_2G) {
++		fat_tab->main_ctrl_sum += rx_pwdb_all;
++		fat_tab->main_ctrl_cnt++;
++	} else {
++		fat_tab->aux_ctrl_sum += rx_pwdb_all;
++		fat_tab->aux_ctrl_cnt++;
++	}
++}
++
++void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void *dm_void,
++						    void *phy_info_void,
++						    void *pkt_info_void
++	/*	struct phydm_phyinfo_struct*		phy_info, */
++	/*	struct phydm_perpkt_info_struct*		pktinfo */
++	)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_phyinfo_struct *phy_info = NULL;
++	struct phydm_perpkt_info_struct *pktinfo = NULL;
++	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	u8 rssi_cck;
++
++	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
++	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
++
++	if (!(dm->support_ability & ODM_BB_ANT_DIV))
++		return;
++
++	if (dm->ant_div_type != S0S1_SW_ANTDIV)
++		return;
++
++	/* @In try state */
++	if (!swat_tab->is_sw_ant_div_by_ctrl_frame)
++		return;
++
++	/* No HW error and match receiver address */
++	if (!pktinfo->is_to_self)
++		return;
++
++	swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame++;
++
++	if (pktinfo->is_cck_rate) {
++		rssi_cck = phy_info->rx_mimo_signal_strength[RF_PATH_A];
++		fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ?
++					    ANT1_2G : ANT2_2G;
++
++		if (fat_tab->antsel_rx_keep_0 == ANT1_2G)
++			fat_tab->cck_ctrl_frame_cnt_main++;
++		else
++			fat_tab->cck_ctrl_frame_cnt_aux++;
++
++		odm_antsel_statistics_ctrl(dm, fat_tab->antsel_rx_keep_0,
++					   rssi_cck);
++	} else {
++		fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ?
++					    ANT1_2G : ANT2_2G;
++
++		if (fat_tab->antsel_rx_keep_0 == ANT1_2G)
++			fat_tab->ofdm_ctrl_frame_cnt_main++;
++		else
++			fat_tab->ofdm_ctrl_frame_cnt_aux++;
++
++		odm_antsel_statistics_ctrl(dm, fat_tab->antsel_rx_keep_0,
++					   phy_info->rx_pwdb_all);
++	}
++}
++
++#endif /* @#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) */
++
++void odm_set_next_mac_addr_target(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	struct cmn_sta_info *entry;
++	u32 value32, i;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "%s ==>\n", __func__);
++
++	if (dm->is_linked) {
++		for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
++			if ((fat_tab->train_idx + 1) == ODM_ASSOCIATE_ENTRY_NUM)
++				fat_tab->train_idx = 0;
++			else
++				fat_tab->train_idx++;
++
++			entry = dm->phydm_sta_info[fat_tab->train_idx];
++
++			if (is_sta_active(entry)) {
++				/*@Match MAC ADDR*/
++				value32 = (entry->mac_addr[5] << 8) | entry->mac_addr[4];
++
++				odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, value32); /*@0x7b4~0x7b5*/
++
++				value32 = (entry->mac_addr[3] << 24) | (entry->mac_addr[2] << 16) | (entry->mac_addr[1] << 8) | entry->mac_addr[0];
++
++				odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, value32); /*@0x7b0~0x7b3*/
++
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "fat_tab->train_idx=%d\n",
++					  fat_tab->train_idx);
++
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "Training MAC addr = %x:%x:%x:%x:%x:%x\n",
++					  entry->mac_addr[5],
++					  entry->mac_addr[4],
++					  entry->mac_addr[3],
++					  entry->mac_addr[2],
++					  entry->mac_addr[1],
++					  entry->mac_addr[0]);
++
++				break;
++			}
++		}
++	}
++}
++
++#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++
++void odm_fast_ant_training(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	u32 max_rssi_path_a = 0, pckcnt_path_a = 0;
++	u8 i, target_ant_path_a = 0;
++	boolean is_pkt_filter_macth_path_a = false;
++#if (RTL8192E_SUPPORT == 1)
++	u32 max_rssi_path_b = 0, pckcnt_path_b = 0;
++	u8 target_ant_path_b = 0;
++	boolean is_pkt_filter_macth_path_b = false;
++#endif
++
++	if (!dm->is_linked) { /* @is_linked==False */
++		PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
++
++		if (fat_tab->is_become_linked == true) {
++			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
++			phydm_fast_training_enable(dm, FAT_OFF);
++			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
++			fat_tab->is_become_linked = dm->is_linked;
++		}
++		return;
++	} else {
++		if (fat_tab->is_become_linked == false) {
++			PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked!!!]\n");
++			fat_tab->is_become_linked = dm->is_linked;
++		}
++	}
++
++	if (!(*fat_tab->p_force_tx_by_desc)) {
++		if (dm->is_one_entry_only == true)
++			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
++		else
++			odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
++	}
++
++	if (dm->support_ic_type == ODM_RTL8188E)
++		odm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1));
++#if (RTL8192E_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8192E) {
++		odm_set_bb_reg(dm, R_0xb38, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1)); /* path-A  */ /* ant combination=regB38[2:0]+1 */
++		odm_set_bb_reg(dm, R_0xb38, BIT(18) | BIT(17) | BIT(16), ((dm->fat_comb_b) - 1)); /* path-B  */ /* ant combination=regB38[18:16]+1 */
++	}
++#endif
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "==>%s\n", __func__);
++
++	/* @1 TRAINING STATE */
++	if (fat_tab->fat_state == FAT_TRAINING_STATE) {
++		/* @2 Caculate RSSI per Antenna */
++
++		/* @3 [path-A]--------------------------- */
++		for (i = 0; i < (dm->fat_comb_a); i++) { /* @i : antenna index */
++			if (fat_tab->ant_rssi_cnt[i] == 0)
++				fat_tab->ant_ave_rssi[i] = 0;
++			else {
++				fat_tab->ant_ave_rssi[i] = fat_tab->ant_sum_rssi[i] / fat_tab->ant_rssi_cnt[i];
++				is_pkt_filter_macth_path_a = true;
++			}
++
++			if (fat_tab->ant_ave_rssi[i] > max_rssi_path_a) {
++				max_rssi_path_a = fat_tab->ant_ave_rssi[i];
++				pckcnt_path_a = fat_tab->ant_rssi_cnt[i];
++				target_ant_path_a = i;
++			} else if (fat_tab->ant_ave_rssi[i] == max_rssi_path_a) {
++				if (fat_tab->ant_rssi_cnt[i] > pckcnt_path_a) {
++					max_rssi_path_a = fat_tab->ant_ave_rssi[i];
++					pckcnt_path_a = fat_tab->ant_rssi_cnt[i];
++					target_ant_path_a = i;
++				}
++			}
++
++			PHYDM_DBG(
++				  "*** ant-index : [ %d ],      counter = (( %d )),     Avg RSSI = (( %d ))\n",
++				  i, fat_tab->ant_rssi_cnt[i],
++				  fat_tab->ant_ave_rssi[i]);
++		}
++
++#if 0
++#if (RTL8192E_SUPPORT == 1)
++		/* @3 [path-B]--------------------------- */
++		for (i = 0; i < (dm->fat_comb_b); i++) {
++			if (fat_tab->antRSSIcnt_pathB[i] == 0)
++				fat_tab->antAveRSSI_pathB[i] = 0;
++			else { /*  @(ant_rssi_cnt[i] != 0) */
++				fat_tab->antAveRSSI_pathB[i] = fat_tab->antSumRSSI_pathB[i] / fat_tab->antRSSIcnt_pathB[i];
++				is_pkt_filter_macth_path_b = true;
++			}
++			if (fat_tab->antAveRSSI_pathB[i] > max_rssi_path_b) {
++				max_rssi_path_b = fat_tab->antAveRSSI_pathB[i];
++				pckcnt_path_b = fat_tab->antRSSIcnt_pathB[i];
++				target_ant_path_b = (u8)i;
++			}
++			if (fat_tab->antAveRSSI_pathB[i] == max_rssi_path_b) {
++				if (fat_tab->antRSSIcnt_pathB > pckcnt_path_b) {
++					max_rssi_path_b = fat_tab->antAveRSSI_pathB[i];
++					target_ant_path_b = (u8)i;
++				}
++			}
++			if (dm->fat_print_rssi == 1) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "***{path-B}: Sum RSSI[%d] = (( %d )),      cnt RSSI [%d] = (( %d )),     Avg RSSI[%d] = (( %d ))\n",
++					  i, fat_tab->antSumRSSI_pathB[i], i,
++					  fat_tab->antRSSIcnt_pathB[i], i,
++					  fat_tab->antAveRSSI_pathB[i]);
++			}
++		}
++#endif
++#endif
++
++		/* @1 DECISION STATE */
++
++		/* @2 Select TRX Antenna */
++
++		phydm_fast_training_enable(dm, FAT_OFF);
++
++		/* @3 [path-A]--------------------------- */
++		if (is_pkt_filter_macth_path_a == false) {
++#if 0
++			/* PHYDM_DBG(dm,DBG_ANT_DIV, "{path-A}: None Packet is matched\n"); */
++#endif
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "{path-A}: None Packet is matched\n");
++			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
++		} else {
++			PHYDM_DBG(
++				  "target_ant_path_a = (( %d )) , max_rssi_path_a = (( %d ))\n",
++				  target_ant_path_a, max_rssi_path_a);
++
++			/* @3 [ update RX-optional ant ]        Default RX is Omni, Optional RX is the best decision by FAT */
++			if (dm->support_ic_type == ODM_RTL8188E)
++				odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), target_ant_path_a);
++			else if (dm->support_ic_type == ODM_RTL8192E)
++				odm_set_bb_reg(dm, R_0xb38, BIT(8) | BIT(7) | BIT(6), target_ant_path_a); /* Optional RX [pth-A] */
++
++			/* @3 [ update TX ant ] */
++			odm_update_tx_ant(dm, target_ant_path_a, (fat_tab->train_idx));
++
++			if (target_ant_path_a == 0)
++				odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
++		}
++#if 0
++#if (RTL8192E_SUPPORT == 1)
++		/* @3 [path-B]--------------------------- */
++		if (is_pkt_filter_macth_path_b == false) {
++			if (dm->fat_print_rssi == 1)
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "***[%d]{path-B}: None Packet is matched\n\n\n",
++					  __LINE__);
++		} else {
++			if (dm->fat_print_rssi == 1) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  " ***target_ant_path_b = (( %d )) *** max_rssi = (( %d ))***\n\n\n",
++					  target_ant_path_b, max_rssi_path_b);
++			}
++			odm_set_bb_reg(dm, R_0xb38, BIT(21) | BIT20 | BIT19, target_ant_path_b);	/* @Default RX is Omni, Optional RX is the best decision by FAT */
++			odm_set_bb_reg(dm, R_0x80c, BIT(21), 1); /* Reg80c[21]=1'b1		//from TX Info */
++
++			fat_tab->antsel_pathB[fat_tab->train_idx] = target_ant_path_b;
++		}
++#endif
++#endif
++
++		/* @2 Reset counter */
++		for (i = 0; i < (dm->fat_comb_a); i++) {
++			fat_tab->ant_sum_rssi[i] = 0;
++			fat_tab->ant_rssi_cnt[i] = 0;
++		}
++		/*@
++		#if (RTL8192E_SUPPORT == 1)
++		for(i=0; i<=(dm->fat_comb_b); i++)
++		{
++			fat_tab->antSumRSSI_pathB[i] = 0;
++			fat_tab->antRSSIcnt_pathB[i] = 0;
++		}
++		#endif
++		*/
++
++		fat_tab->fat_state = FAT_PREPARE_STATE;
++		return;
++	}
++
++	/* @1 NORMAL STATE */
++	if (fat_tab->fat_state == FAT_PREPARE_STATE) {
++		PHYDM_DBG(dm, DBG_ANT_DIV, "[ Start Prepare state ]\n");
++
++		odm_set_next_mac_addr_target(dm);
++
++		/* @2 Prepare Training */
++		fat_tab->fat_state = FAT_TRAINING_STATE;
++		phydm_fast_training_enable(dm, FAT_ON);
++		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
++		/* @enable HW AntDiv */
++		PHYDM_DBG(dm, DBG_ANT_DIV, "[Start Training state]\n");
++
++		odm_set_timer(dm, &dm->fast_ant_training_timer, dm->antdiv_intvl); /* @ms */
++	}
++}
++
++void odm_fast_ant_training_callback(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	if (*(dm->is_net_closed) == true)
++		return;
++#endif
++
++#if USE_WORKITEM
++	odm_schedule_work_item(&dm->fast_ant_training_workitem);
++#else
++	PHYDM_DBG(dm, DBG_ANT_DIV, "******%s******\n", __func__);
++	odm_fast_ant_training(dm);
++#endif
++}
++
++void odm_fast_ant_training_work_item_callback(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "******%s******\n", __func__);
++	odm_fast_ant_training(dm);
++}
++
++#endif
++
++void odm_ant_div_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
++
++	if (!(dm->support_ability & ODM_BB_ANT_DIV)) {
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[Return!!!]   Not Support Antenna Diversity Function\n");
++		return;
++	}
++/* @--- */
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) {
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n");
++		if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC))
++			return;
++	} else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) {
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n");
++		if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC))
++			return;
++	} else if (fat_tab->ant_div_2g_5g == (ODM_ANTDIV_2G | ODM_ANTDIV_5G))
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n");
++
++#endif
++	/* @--- */
++
++	/* @2 [--General---] */
++	dm->antdiv_period = 0;
++
++	fat_tab->is_become_linked = false;
++	fat_tab->ant_div_on_off = 0xff;
++
++/* @3       -   AP   - */
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	odm_bdc_init(dm);
++#endif
++#endif
++
++/* @3     -   WIN   - */
++#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	swat_tab->ant_5g = MAIN_ANT;
++	swat_tab->ant_2g = MAIN_ANT;
++#endif
++
++	/* @2 [---Set MAIN_ANT as default antenna if Auto-ant enable---] */
++	if (fat_tab->div_path_type == ANT_PATH_A)
++		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
++	else if (fat_tab->div_path_type == ANT_PATH_B)
++		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
++	else if (fat_tab->div_path_type == ANT_PATH_AB)
++		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
++
++	dm->ant_type = ODM_AUTO_ANT;
++
++	fat_tab->rx_idle_ant = 0xff;
++		/*to make RX-idle-antenna will be updated absolutly*/
++	odm_update_rx_idle_ant(dm, MAIN_ANT);
++	phydm_keep_rx_ack_ant_by_tx_ant_time(dm, 0);
++	/* Timming issue: keep Rx ant after tx for ACK(5 x 3.2 mu = 16mu sec)*/
++
++	/* @2 [---Set TX Antenna---] */
++	if (!fat_tab->p_force_tx_by_desc) {
++		fat_tab->force_tx_by_desc = 0;
++		fat_tab->p_force_tx_by_desc = &fat_tab->force_tx_by_desc;
++	}
++	PHYDM_DBG(dm, DBG_ANT_DIV, "p_force_tx_by_desc = %d\n",
++		  *fat_tab->p_force_tx_by_desc);
++
++	if (*fat_tab->p_force_tx_by_desc)
++		odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
++	else
++		odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
++
++	/* @2 [--88E---] */
++	if (dm->support_ic_type == ODM_RTL8188E) {
++#if (RTL8188E_SUPPORT == 1)
++		/* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
++		/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
++		/* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
++
++		if (dm->ant_div_type != CGCS_RX_HW_ANTDIV &&
++		    dm->ant_div_type != CG_TRX_HW_ANTDIV &&
++		    dm->ant_div_type != CG_TRX_SMART_ANTDIV) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[Return!!!]  88E Not Supprrt This AntDiv type\n");
++			dm->support_ability &= ~(ODM_BB_ANT_DIV);
++			return;
++		}
++
++		if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
++			odm_rx_hw_ant_div_init_88e(dm);
++		else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
++			odm_trx_hw_ant_div_init_88e(dm);
++#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++		else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
++			odm_smart_hw_ant_div_init_88e(dm);
++#endif
++#endif
++	}
++
++/* @2 [--92E---] */
++#if (RTL8192E_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8192E) {
++		/* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
++		/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
++		/* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
++
++		if (dm->ant_div_type != CGCS_RX_HW_ANTDIV &&
++		    dm->ant_div_type != CG_TRX_HW_ANTDIV &&
++		    dm->ant_div_type != CG_TRX_SMART_ANTDIV) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[Return!!!]  8192E Not Supprrt This AntDiv type\n");
++			dm->support_ability &= ~(ODM_BB_ANT_DIV);
++			return;
++		}
++
++		if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
++			odm_rx_hw_ant_div_init_92e(dm);
++		else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
++			odm_trx_hw_ant_div_init_92e(dm);
++#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++		else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
++			odm_smart_hw_ant_div_init_92e(dm);
++#endif
++	}
++#endif
++
++	/* @2 [--92F---] */
++#if (RTL8192F_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8192F) {
++	/* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
++	/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
++	/* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
++
++	if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
++		if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[Return!!!]  8192F Not Supprrt This AntDiv type\n");
++			dm->support_ability &= ~(ODM_BB_ANT_DIV);
++			return;
++		}
++	}
++	if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
++		odm_rx_hw_ant_div_init_92f(dm);
++	else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
++	odm_trx_hw_ant_div_init_92f(dm);
++	}
++#endif
++
++#if (RTL8197F_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8197F) {
++		dm->ant_div_type = CGCS_RX_HW_ANTDIV;
++
++		if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[Return!!!]  8197F Not Supprrt This AntDiv type\n");
++			dm->support_ability &= ~(ODM_BB_ANT_DIV);
++			return;
++		}
++		phydm_rx_hw_ant_div_init_97f(dm);
++	}
++#endif
++
++#if (RTL8197G_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8197G) {
++		dm->ant_div_type = CGCS_RX_HW_ANTDIV;
++
++		if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[Return!!!]  8197F Not Supprrt This AntDiv type\n");
++			dm->support_ability &= ~(ODM_BB_ANT_DIV);
++			return;
++		}
++		phydm_rx_hw_ant_div_init_97g(dm);
++	}
++#endif
++/* @2 [--8723B---] */
++#if (RTL8723B_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8723B) {
++		dm->ant_div_type = S0S1_SW_ANTDIV;
++		/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
++
++		if (dm->ant_div_type != S0S1_SW_ANTDIV &&
++		    dm->ant_div_type != CG_TRX_HW_ANTDIV) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[Return!!!] 8723B  Not Supprrt This AntDiv type\n");
++			dm->support_ability &= ~(ODM_BB_ANT_DIV);
++			return;
++		}
++
++		if (dm->ant_div_type == S0S1_SW_ANTDIV)
++			odm_s0s1_sw_ant_div_init_8723b(dm);
++		else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
++			odm_trx_hw_ant_div_init_8723b(dm);
++	}
++#endif
++/*@2 [--8723D---]*/
++#if (RTL8723D_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8723D) {
++		if (fat_tab->p_default_s0_s1 == NULL) {
++			fat_tab->default_s0_s1 = 1;
++			fat_tab->p_default_s0_s1 = &fat_tab->default_s0_s1;
++		}
++		PHYDM_DBG(dm, DBG_ANT_DIV, "default_s0_s1 = %d\n",
++			  *fat_tab->p_default_s0_s1);
++
++		if (*fat_tab->p_default_s0_s1 == true)
++			odm_update_rx_idle_ant(dm, MAIN_ANT);
++		else
++			odm_update_rx_idle_ant(dm, AUX_ANT);
++
++		if (dm->ant_div_type == S0S1_TRX_HW_ANTDIV)
++			odm_trx_hw_ant_div_init_8723d(dm);
++		else if (dm->ant_div_type == S0S1_SW_ANTDIV)
++			odm_s0s1_sw_ant_div_init_8723d(dm);
++		else {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				"[Return!!!] 8723D  Not Supprrt This AntDiv type\n");
++			dm->support_ability &= ~(ODM_BB_ANT_DIV);
++			return;
++		}
++	}
++#endif
++#if (RTL8721D_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8721D) {
++		/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
++
++		if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[Return!!!]  8721D Not Supprrt This AntDiv type\n");
++			dm->support_ability &= ~(ODM_BB_ANT_DIV);
++			return;
++		}
++		if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
++			odm_trx_hw_ant_div_init_8721d(dm);
++	}
++#endif
++/* @2 [--8811A 8821A---] */
++#if (RTL8821A_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8821) {
++#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
++		dm->ant_div_type = HL_SW_SMART_ANT_TYPE1;
++
++		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
++			odm_trx_hw_ant_div_init_8821a(dm);
++			phydm_hl_smart_ant_type1_init_8821a(dm);
++		} else
++#endif
++		{
++#ifdef ODM_CONFIG_BT_COEXIST
++			dm->ant_div_type = S0S1_SW_ANTDIV;
++#else
++			dm->ant_div_type = CG_TRX_HW_ANTDIV;
++#endif
++
++			if (dm->ant_div_type != CG_TRX_HW_ANTDIV &&
++			    dm->ant_div_type != S0S1_SW_ANTDIV) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "[Return!!!] 8821A & 8811A  Not Supprrt This AntDiv type\n");
++				dm->support_ability &= ~(ODM_BB_ANT_DIV);
++				return;
++			}
++			if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
++				odm_trx_hw_ant_div_init_8821a(dm);
++			else if (dm->ant_div_type == S0S1_SW_ANTDIV)
++				odm_s0s1_sw_ant_div_init_8821a(dm);
++		}
++	}
++#endif
++
++/* @2 [--8821C---] */
++#if (RTL8821C_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8821C) {
++		dm->ant_div_type = S0S1_SW_ANTDIV;
++		if (dm->ant_div_type != S0S1_SW_ANTDIV) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[Return!!!] 8821C  Not Supprrt This AntDiv type\n");
++			dm->support_ability &= ~(ODM_BB_ANT_DIV);
++			return;
++		}
++		phydm_s0s1_sw_ant_div_init_8821c(dm);
++		odm_trx_hw_ant_div_init_8821c(dm);
++	}
++#endif
++
++/* @2 [--8881A---] */
++#if (RTL8881A_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8881A) {
++		/* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
++		/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
++
++		if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
++			odm_trx_hw_ant_div_init_8881a(dm);
++		} else {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[Return!!!] 8881A  Not Supprrt This AntDiv type\n");
++			dm->support_ability &= ~(ODM_BB_ANT_DIV);
++			return;
++		}
++
++		odm_trx_hw_ant_div_init_8881a(dm);
++	}
++#endif
++
++/* @2 [--8812---] */
++#if (RTL8812A_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8812) {
++		/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
++
++		if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[Return!!!] 8812A  Not Supprrt This AntDiv type\n");
++			dm->support_ability &= ~(ODM_BB_ANT_DIV);
++			return;
++		}
++		odm_trx_hw_ant_div_init_8812a(dm);
++	}
++#endif
++
++/*@[--8188F---]*/
++#if (RTL8188F_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8188F) {
++		dm->ant_div_type = S0S1_SW_ANTDIV;
++		odm_s0s1_sw_ant_div_init_8188f(dm);
++	}
++#endif
++
++/*@[--8822B---]*/
++#if (RTL8822B_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8822B) {
++		dm->ant_div_type = CG_TRX_HW_ANTDIV;
++
++		if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[Return!!!]  8822B Not Supprrt This AntDiv type\n");
++			dm->support_ability &= ~(ODM_BB_ANT_DIV);
++			return;
++		}
++		phydm_trx_hw_ant_div_init_22b(dm);
++#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
++		dm->ant_div_type = HL_SW_SMART_ANT_TYPE2;
++
++		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2)
++			phydm_hl_smart_ant_type2_init_8822b(dm);
++#endif
++	}
++#endif
++
++/*@PHYDM_DBG(dm, DBG_ANT_DIV, "*** support_ic_type=[%lu]\n",*/
++/*dm->support_ic_type);*/
++/*PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv support_ability=[%lu]\n",*/
++/*	  (dm->support_ability & ODM_BB_ANT_DIV)>>6);*/
++/*PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv type=[%d]\n",dm->ant_div_type);*/
++}
++
++void odm_ant_div(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	void *adapter = dm->adapter;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++#if (defined(CONFIG_HL_SMART_ANTENNA))
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++#endif
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++	if (dm->is_linked) {
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "tp_active_occur=((%d)), evm_method_enable=((%d))\n",
++			  dm->tp_active_occur, fat_tab->evm_method_enable);
++
++		if (dm->tp_active_occur == 1 &&
++		    fat_tab->evm_method_enable == 1) {
++			fat_tab->idx_ant_div_counter_5g = dm->antdiv_period;
++			fat_tab->idx_ant_div_counter_2g = dm->antdiv_period;
++		}
++	}
++#endif
++
++	if (*dm->band_type == ODM_BAND_5G) {
++		if (fat_tab->idx_ant_div_counter_5g < dm->antdiv_period) {
++			fat_tab->idx_ant_div_counter_5g++;
++			return;
++		} else
++			fat_tab->idx_ant_div_counter_5g = 0;
++	} else if (*dm->band_type == ODM_BAND_2_4G) {
++		if (fat_tab->idx_ant_div_counter_2g < dm->antdiv_period) {
++			fat_tab->idx_ant_div_counter_2g++;
++			return;
++		} else
++			fat_tab->idx_ant_div_counter_2g = 0;
++	}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN || DM_ODM_SUPPORT_TYPE == ODM_CE)
++
++	if (fat_tab->enable_ctrl_frame_antdiv) {
++		if (dm->data_frame_num <= 10 && dm->is_linked)
++			fat_tab->use_ctrl_frame_antdiv = 1;
++		else
++			fat_tab->use_ctrl_frame_antdiv = 0;
++
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\n",
++			  fat_tab->use_ctrl_frame_antdiv, dm->data_frame_num);
++		dm->data_frame_num = 0;
++	}
++
++	{
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++
++		enum beamforming_cap beamform_cap = phydm_get_beamform_cap(dm);
++		PHYDM_DBG(dm, DBG_ANT_DIV, "is_bt_continuous_turn = ((%d))\n",
++			  dm->is_bt_continuous_turn);
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ AntDiv Beam Cap ]   cap= ((%d))\n", beamform_cap);
++		if (!dm->is_bt_continuous_turn) {
++			if ((beamform_cap & BEAMFORMEE_CAP) &&
++			    (!(*fat_tab->is_no_csi_feedback))) {
++			    /* @BFmee On  &&   Div On->Div Off */
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "[ AntDiv : OFF ]   BFmee ==1; cap= ((%d))\n",
++					  beamform_cap);
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "[ AntDiv BF]   is_no_csi_feedback= ((%d))\n",
++					  *(fat_tab->is_no_csi_feedback));
++				if (fat_tab->fix_ant_bfee == 0) {
++					odm_ant_div_on_off(dm, ANTDIV_OFF,
++							   ANT_PATH_A);
++					fat_tab->fix_ant_bfee = 1;
++				}
++				return;
++			} else { /* @BFmee Off   &&   Div Off->Div On */
++				if (fat_tab->fix_ant_bfee == 1 &&
++				    dm->is_linked) {
++					PHYDM_DBG(dm, DBG_ANT_DIV,
++						  "[ AntDiv : ON ]   BFmee ==0; cap=((%d))\n",
++						  beamform_cap);
++					PHYDM_DBG(dm, DBG_ANT_DIV,
++						  "[ AntDiv BF]   is_no_csi_feedback= ((%d))\n",
++						  *fat_tab->is_no_csi_feedback);
++					if (dm->ant_div_type != S0S1_SW_ANTDIV)
++						odm_ant_div_on_off(dm, ANTDIV_ON
++								   , ANT_PATH_A)
++								   ;
++					fat_tab->fix_ant_bfee = 0;
++				}
++			}
++		} else {
++			if (fat_tab->div_path_type == ANT_PATH_A)
++				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
++			else if (fat_tab->div_path_type == ANT_PATH_B)
++				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
++			else if (fat_tab->div_path_type == ANT_PATH_AB)
++				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
++		}
++#endif
++	}
++#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	/* @----------just for fool proof */
++
++	if (dm->antdiv_rssi)
++		dm->debug_components |= DBG_ANT_DIV;
++	else
++		dm->debug_components &= ~DBG_ANT_DIV;
++
++	if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) {
++		if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC))
++			return;
++	} else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) {
++		if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC))
++			return;
++	}
++#endif
++
++	/* @---------- */
++
++	if (dm->antdiv_select == 1)
++		dm->ant_type = ODM_FIX_MAIN_ANT;
++	else if (dm->antdiv_select == 2)
++		dm->ant_type = ODM_FIX_AUX_ANT;
++	else { /* @if (dm->antdiv_select==0) */
++		dm->ant_type = ODM_AUTO_ANT;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++		/*Stop Antenna diversity for CMW500 testing case*/
++		if (dm->consecutive_idlel_time >= 10) {
++			dm->ant_type = ODM_FIX_MAIN_ANT;
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "[AntDiv: OFF] No TP case, consecutive_idlel_time=((%d))\n",
++				  dm->consecutive_idlel_time);
++		}
++#endif
++	}
++
++	/*PHYDM_DBG(dm, DBG_ANT_DIV,"ant_type= (%d), pre_ant_type= (%d)\n",*/
++	/*dm->ant_type,dm->pre_ant_type); */
++
++	if (dm->ant_type != ODM_AUTO_ANT) {
++		PHYDM_DBG(dm, DBG_ANT_DIV, "Fix Antenna at (( %s ))\n",
++			  (dm->ant_type == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX");
++
++		if (dm->ant_type != dm->pre_ant_type) {
++			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
++			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
++
++			if (dm->ant_type == ODM_FIX_MAIN_ANT)
++				odm_update_rx_idle_ant(dm, MAIN_ANT);
++			else if (dm->ant_type == ODM_FIX_AUX_ANT)
++				odm_update_rx_idle_ant(dm, AUX_ANT);
++		}
++		dm->pre_ant_type = dm->ant_type;
++		return;
++	} else {
++		if (dm->ant_type != dm->pre_ant_type) {
++			odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
++			odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
++		}
++		dm->pre_ant_type = dm->ant_type;
++	}
++#if (defined(CONFIG_2T4R_ANTENNA))
++	if (dm->ant_type2 != ODM_AUTO_ANT) {
++		PHYDM_DBG(dm, DBG_ANT_DIV, "PathB Fix Ant at (( %s ))\n",
++			  (dm->ant_type2 == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX");
++
++		if (dm->ant_type2 != dm->pre_ant_type2) {
++			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
++			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
++
++			if (dm->ant_type2 == ODM_FIX_MAIN_ANT)
++				phydm_update_rx_idle_ant_pathb(dm, MAIN_ANT);
++			else if (dm->ant_type2 == ODM_FIX_AUX_ANT)
++				phydm_update_rx_idle_ant_pathb(dm, AUX_ANT);
++		}
++		dm->pre_ant_type2 = dm->ant_type2;
++		return;
++	}
++	if (dm->ant_type2 != dm->pre_ant_type2) {
++		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
++		odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
++	}
++	dm->pre_ant_type2 = dm->ant_type2;
++
++#endif
++
++/*@ ----------------------------------------------- */
++/*@ [--8188E--] */
++	if (dm->support_ic_type == ODM_RTL8188E) {
++#if (RTL8188E_SUPPORT == 1)
++		if (dm->ant_div_type == CG_TRX_HW_ANTDIV ||
++		    dm->ant_div_type == CGCS_RX_HW_ANTDIV)
++			odm_hw_ant_div(dm);
++
++#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
++	(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++		else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
++			odm_fast_ant_training(dm);
++#endif
++
++#endif
++	}
++/*@ [--8192E--] */
++#if (RTL8192E_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8192E) {
++		if (dm->ant_div_type == CGCS_RX_HW_ANTDIV ||
++		    dm->ant_div_type == CG_TRX_HW_ANTDIV)
++			odm_hw_ant_div(dm);
++
++#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
++	(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++		else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
++			odm_fast_ant_training(dm);
++#endif
++	}
++#endif
++/*@ [--8197F--] */
++#if (RTL8197F_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8197F) {
++		if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
++			odm_hw_ant_div(dm);
++	}
++#endif
++
++/*@ [--8197G--] */
++#if (RTL8197G_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8197G) {
++		if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
++			odm_hw_ant_div(dm);
++	}
++#endif
++
++#if (RTL8723B_SUPPORT == 1)
++/*@ [--8723B---] */
++	else if (dm->support_ic_type == ODM_RTL8723B) {
++		if (phydm_is_bt_enable_8723b(dm)) {
++			PHYDM_DBG(dm, DBG_ANT_DIV, "[BT is enable!!!]\n");
++			if (fat_tab->is_become_linked == true) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "Set REG 948[9:6]=0x0\n");
++				if (dm->support_ic_type == ODM_RTL8723B)
++					odm_set_bb_reg(dm, R_0x948, 0x3c0, 0x0)
++						       ;
++
++				fat_tab->is_become_linked = false;
++			}
++		} else {
++			if (dm->ant_div_type == S0S1_SW_ANTDIV) {
++				#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++				odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
++				#endif
++			} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
++				odm_hw_ant_div(dm);
++		}
++	}
++#endif
++/*@ [--8723D--]*/
++#if (RTL8723D_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8723D) {
++		if (dm->ant_div_type == S0S1_SW_ANTDIV) {
++			#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++			if (dm->antdiv_counter == CONFIG_ANTDIV_PERIOD) {
++				odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
++				dm->antdiv_counter--;
++			} else {
++				dm->antdiv_counter--;
++			}
++			if (dm->antdiv_counter == 0)
++				dm->antdiv_counter = CONFIG_ANTDIV_PERIOD;
++			#endif
++		} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
++			odm_hw_ant_div(dm);
++		}
++	}
++#endif
++#if (RTL8721D_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8721D) {
++		if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
++			odm_hw_ant_div(dm);
++		}
++	}
++#endif
++/*@ [--8821A--] */
++#if (RTL8821A_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8821) {
++		#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
++		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
++			if (sat_tab->fix_beam_pattern_en != 0) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n",
++					  sat_tab->fix_beam_pattern_codeword);
++				/*return;*/
++			} else {
++				odm_fast_ant_training_hl_smart_antenna_type1(dm);
++			}
++
++		} else
++		#endif
++		{
++		#ifdef ODM_CONFIG_BT_COEXIST
++			if (!dm->bt_info_table.is_bt_enabled) { /*@BT disabled*/
++				if (dm->ant_div_type == S0S1_SW_ANTDIV) {
++					dm->ant_div_type = CG_TRX_HW_ANTDIV;
++					PHYDM_DBG(dm, DBG_ANT_DIV,
++						  " [S0S1_SW_ANTDIV]  ->  [CG_TRX_HW_ANTDIV]\n");
++					/*odm_set_bb_reg(dm, 0x8d4, BIT24, 1);*/
++					if (fat_tab->is_become_linked == true)
++						odm_ant_div_on_off(dm,
++								   ANTDIV_ON,
++								   ANT_PATH_A);
++				}
++
++			} else { /*@BT enabled*/
++
++				if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
++					dm->ant_div_type = S0S1_SW_ANTDIV;
++					PHYDM_DBG(dm, DBG_ANT_DIV,
++						  " [CG_TRX_HW_ANTDIV]  ->  [S0S1_SW_ANTDIV]\n");
++					/*odm_set_bb_reg(dm, 0x8d4, BIT24, 0);*/
++					odm_ant_div_on_off(dm, ANTDIV_OFF,
++							   ANT_PATH_A);
++				}
++			}
++		#endif
++
++			if (dm->ant_div_type == S0S1_SW_ANTDIV) {
++				#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++				odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
++				#endif
++			} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
++				odm_hw_ant_div(dm);
++			}
++		}
++	}
++#endif
++
++/*@ [--8821C--] */
++#if (RTL8821C_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8821C) {
++		if (!dm->is_bt_continuous_turn) {
++			dm->ant_div_type = S0S1_SW_ANTDIV;
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "is_bt_continuous_turn = ((%d))   ==> SW AntDiv\n",
++				  dm->is_bt_continuous_turn);
++
++		} else {
++			dm->ant_div_type = CG_TRX_HW_ANTDIV;
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "is_bt_continuous_turn = ((%d))   ==> HW AntDiv\n",
++				  dm->is_bt_continuous_turn);
++			odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
++		}
++
++		if (fat_tab->force_antdiv_type)
++			dm->ant_div_type = fat_tab->antdiv_type_dbg;
++
++		if (dm->ant_div_type == S0S1_SW_ANTDIV) {
++			#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++			odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
++			#endif
++		} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
++			odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
++			odm_hw_ant_div(dm);
++		}
++	}
++#endif
++
++/* @ [--8881A--] */
++#if (RTL8881A_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8881A)
++		odm_hw_ant_div(dm);
++#endif
++
++/*@ [--8812A--] */
++#if (RTL8812A_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8812)
++		odm_hw_ant_div(dm);
++#endif
++
++#if (RTL8188F_SUPPORT == 1)
++/*@ [--8188F--]*/
++	else if (dm->support_ic_type == ODM_RTL8188F) {
++		#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++		odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
++		#endif
++	}
++#endif
++
++/*@ [--8822B--]*/
++#if (RTL8822B_SUPPORT == 1)
++	else if (dm->support_ic_type == ODM_RTL8822B) {
++		if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
++			odm_hw_ant_div(dm);
++		#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
++		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) {
++			if (sat_tab->fix_beam_pattern_en != 0)
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n",
++					  sat_tab->fix_beam_pattern_codeword);
++			else
++				phydm_fast_ant_training_hl_smart_antenna_type2(dm);
++		}
++		#endif
++	}
++#endif
++}
++
++void odm_antsel_statistics(void *dm_void, void *phy_info_void,
++			   u8 antsel_tr_mux, u32 mac_id, u32 utility, u8 method,
++			   u8 is_cck_rate)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	struct phydm_phyinfo_struct *phy_info = NULL;
++
++	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
++
++	if (method == RSSI_METHOD) {
++		if (is_cck_rate) {
++			if (antsel_tr_mux == ANT1_2G) {
++	/*to prevent u16 overflow, max(RSSI)=100, 65435+100 = 65535 (u16)*/
++				if (fat_tab->main_sum_cck[mac_id] > 65435)
++					return;
++
++				fat_tab->main_sum_cck[mac_id] += (u16)utility;
++				fat_tab->main_cnt_cck[mac_id]++;
++			} else {
++				if (fat_tab->aux_sum_cck[mac_id] > 65435)
++					return;
++
++				fat_tab->aux_sum_cck[mac_id] += (u16)utility;
++				fat_tab->aux_cnt_cck[mac_id]++;
++			}
++
++		} else { /*ofdm rate*/
++
++			if (antsel_tr_mux == ANT1_2G) {
++				if (fat_tab->main_sum[mac_id] > 65435)
++					return;
++
++				fat_tab->main_sum[mac_id] += (u16)utility;
++				fat_tab->main_cnt[mac_id]++;
++			} else {
++				if (fat_tab->aux_sum[mac_id] > 65435)
++					return;
++
++				fat_tab->aux_sum[mac_id] += (u16)utility;
++				fat_tab->aux_cnt[mac_id]++;
++			}
++		}
++	}
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++	else if (method == EVM_METHOD) {
++		if (!fat_tab->get_stats)
++			return;
++
++		if (dm->rate_ss == 1) {
++			phydm_statistics_evm_1ss(dm, phy_info, antsel_tr_mux,
++						 mac_id, utility);
++		} else { /*@>= 2SS*/
++			phydm_statistics_evm_2ss(dm, phy_info, antsel_tr_mux,
++						 mac_id, utility);
++		}
++
++	} else if (method == CRC32_METHOD) {
++		if (antsel_tr_mux == ANT1_2G) {
++			fat_tab->main_crc32_ok_cnt += utility;
++			fat_tab->main_crc32_fail_cnt++;
++		} else {
++			fat_tab->aux_crc32_ok_cnt += utility;
++			fat_tab->aux_crc32_fail_cnt++;
++		}
++
++	} else if (method == TP_METHOD) {
++		if (!fat_tab->get_stats)
++			return;
++		if (utility <= ODM_RATEMCS15 && utility >= ODM_RATEMCS0) {
++			if (antsel_tr_mux == ANT1_2G) {
++				fat_tab->main_tp += (phy_rate_table[utility])
++						    << 5;
++				fat_tab->main_tp_cnt++;
++			} else {
++				fat_tab->aux_tp += (phy_rate_table[utility])
++						   << 5;
++				fat_tab->aux_tp_cnt++;
++			}
++		}
++	}
++#endif
++}
++
++void odm_process_rssi_smart(void *dm_void, void *phy_info_void,
++			    void *pkt_info_void, u8 rx_power_ant0)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_phyinfo_struct *phy_info = NULL;
++	struct phydm_perpkt_info_struct *pktinfo = NULL;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
++	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
++
++	if ((dm->support_ic_type & ODM_SMART_ANT_SUPPORT) &&
++	    pktinfo->is_packet_to_self &&
++	    fat_tab->fat_state == FAT_TRAINING_STATE) {
++	/* @(pktinfo->is_packet_match_bssid && (!pktinfo->is_packet_beacon)) */
++		u8 antsel_tr_mux;
++
++		antsel_tr_mux = (fat_tab->antsel_rx_keep_2 << 2) |
++				(fat_tab->antsel_rx_keep_1 << 1) |
++				fat_tab->antsel_rx_keep_0;
++		fat_tab->ant_sum_rssi[antsel_tr_mux] += rx_power_ant0;
++		fat_tab->ant_rssi_cnt[antsel_tr_mux]++;
++	}
++}
++
++void odm_process_rssi_normal(void *dm_void, void *phy_info_void,
++			     void *pkt_info_void, u8 rx_pwr0)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_phyinfo_struct *phy_info = NULL;
++	struct phydm_perpkt_info_struct *pktinfo = NULL;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	u8 rx_evm0, rx_evm1;
++	boolean b_main;
++
++	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
++	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
++	rx_evm0 = phy_info->rx_mimo_signal_quality[0];
++	rx_evm1 = phy_info->rx_mimo_signal_quality[1];
++
++	if (!(pktinfo->is_packet_to_self || fat_tab->use_ctrl_frame_antdiv))
++		return;
++
++	if (dm->ant_div_type == S0S1_SW_ANTDIV) {
++		if (pktinfo->is_cck_rate ||
++		    dm->support_ic_type == ODM_RTL8188F) {
++
++			b_main = (fat_tab->rx_idle_ant == MAIN_ANT);
++			fat_tab->antsel_rx_keep_0 = b_main ? ANT1_2G : ANT2_2G;
++		}
++
++		odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,
++				      pktinfo->station_id, rx_pwr0, RSSI_METHOD,
++				      pktinfo->is_cck_rate);
++	} else {
++		odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,
++				      pktinfo->station_id, rx_pwr0, RSSI_METHOD,
++				      pktinfo->is_cck_rate);
++
++		#ifdef ODM_EVM_ENHANCE_ANTDIV
++		if (!(dm->support_ic_type & ODM_EVM_ANTDIV_IC))
++			return;
++		if (pktinfo->is_cck_rate)
++			return;
++
++		odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,
++				      pktinfo->station_id, rx_evm0, EVM_METHOD,
++				      pktinfo->is_cck_rate);
++		odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,
++				      pktinfo->station_id, pktinfo->data_rate,
++				      TP_METHOD, pktinfo->is_cck_rate);
++		#endif
++	}
++}
++
++void odm_process_rssi_for_ant_div(void *dm_void, void *phy_info_void,
++				  void *pkt_info_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_phyinfo_struct *phy_info = NULL;
++	struct phydm_perpkt_info_struct *pktinfo = NULL;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++#if (defined(CONFIG_HL_SMART_ANTENNA))
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++	u32 beam_tmp;
++	u8 next_ant;
++	u8 train_pkt_number;
++#endif
++	boolean b_main;
++	u8 rx_power_ant0, rx_power_ant1;
++	u8 rx_evm_ant0, rx_evm_ant1;
++	u8 rssi_avg;
++	u64 rssi_linear = 0;
++
++	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
++	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
++	rx_power_ant0 = phy_info->rx_mimo_signal_strength[0];
++	rx_power_ant1 = phy_info->rx_mimo_signal_strength[1];
++	rx_evm_ant0 = phy_info->rx_mimo_signal_quality[0];
++	rx_evm_ant1 = phy_info->rx_mimo_signal_quality[1];
++
++	if ((dm->support_ic_type & ODM_IC_2SS) && !pktinfo->is_cck_rate) {
++		if (rx_power_ant1 < 100) {
++			rssi_linear = phydm_db_2_linear(rx_power_ant0) +
++				      phydm_db_2_linear(rx_power_ant1);
++			/* @Rounding and removing fractional bits */
++			rssi_linear = (rssi_linear +
++				       (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
++			/* @Calculate average RSSI */
++			rssi_linear = DIVIDED_2(rssi_linear);
++			/* @averaged PWDB */
++			rssi_avg = (u8)odm_convert_to_db(rssi_linear);
++		}
++
++	} else {
++		rx_power_ant0 = (u8)phy_info->rx_pwdb_all;
++		rssi_avg = rx_power_ant0;
++	}
++
++#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
++	if ((dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) && (fat_tab->fat_state == FAT_TRAINING_STATE))
++		phydm_process_rssi_for_hb_smtant_type2(dm, phy_info, pktinfo, rssi_avg); /*@for 8822B*/
++	else
++#endif
++
++#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
++#ifdef CONFIG_FAT_PATCH
++		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1 && fat_tab->fat_state == FAT_TRAINING_STATE) {
++		/*@[Beacon]*/
++		if (pktinfo->is_packet_beacon) {
++			sat_tab->beacon_counter++;
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "MatchBSSID_beacon_counter = ((%d))\n",
++				  sat_tab->beacon_counter);
++
++			if (sat_tab->beacon_counter >= sat_tab->pre_beacon_counter + 2) {
++				if (sat_tab->ant_num > 1) {
++					next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
++					odm_update_rx_idle_ant(dm, next_ant);
++				}
++
++				sat_tab->update_beam_idx++;
++
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n",
++					  sat_tab->pre_beacon_counter,
++					  sat_tab->pkt_counter,
++					  sat_tab->update_beam_idx);
++
++				sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
++				sat_tab->pkt_counter = 0;
++			}
++		}
++		/*@[data]*/
++		else if (pktinfo->is_packet_to_self) {
++			if (sat_tab->pkt_skip_statistic_en == 0) {
++				/*@
++				PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]:  antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
++					pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0);
++				*/
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "ID[%d][pkt_cnt = %d]: {ANT, Beam} = {%d, %d}, RSSI = ((%d))\n",
++					  pktinfo->station_id,
++					  sat_tab->pkt_counter,
++					  fat_tab->antsel_rx_keep_0,
++					  sat_tab->fast_training_beam_num,
++					  rx_power_ant0);
++
++				sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0;
++				sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++;
++				sat_tab->pkt_counter++;
++
++#if 1
++				train_pkt_number = sat_tab->beam_train_cnt[fat_tab->rx_idle_ant - 1][sat_tab->fast_training_beam_num];
++#else
++				train_pkt_number = sat_tab->per_beam_training_pkt_num;
++#endif
++
++				/*Swich Antenna erery N pkts*/
++				if (sat_tab->pkt_counter == train_pkt_number) {
++					if (sat_tab->ant_num > 1) {
++						PHYDM_DBG(dm, DBG_ANT_DIV, "packet enugh ((%d ))pkts ---> Switch antenna\n", train_pkt_number);
++						next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
++						odm_update_rx_idle_ant(dm, next_ant);
++					}
++
++					sat_tab->update_beam_idx++;
++					PHYDM_DBG(dm, DBG_ANT_DIV, "pre_beacon_counter = ((%d)), update_beam_idx_counter = ((%d))\n",
++						  sat_tab->pre_beacon_counter, sat_tab->update_beam_idx);
++
++					sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
++					sat_tab->pkt_counter = 0;
++				}
++			}
++		}
++
++		/*Swich Beam after switch "sat_tab->ant_num" antennas*/
++		if (sat_tab->update_beam_idx == sat_tab->ant_num) {
++			sat_tab->update_beam_idx = 0;
++			sat_tab->pkt_counter = 0;
++			beam_tmp = sat_tab->fast_training_beam_num;
++
++			if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {
++				fat_tab->fat_state = FAT_DECISION_STATE;
++
++#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++				if (dm->support_interface == ODM_ITRF_PCIE)
++					odm_fast_ant_training_hl_smart_antenna_type1(dm);
++#endif
++#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
++				if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
++					odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);
++#endif
++
++			} else {
++				sat_tab->fast_training_beam_num++;
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "Update Beam_num (( %d )) -> (( %d ))\n",
++					  beam_tmp,
++					  sat_tab->fast_training_beam_num);
++				phydm_set_all_ant_same_beam_num(dm);
++
++				fat_tab->fat_state = FAT_TRAINING_STATE;
++			}
++		}
++	}
++#else
++
++		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
++		if ((dm->support_ic_type & ODM_HL_SMART_ANT_TYPE1_SUPPORT) &&
++		    pktinfo->is_packet_to_self &&
++		    fat_tab->fat_state == FAT_TRAINING_STATE) {
++			if (sat_tab->pkt_skip_statistic_en == 0) {
++				/*@
++				PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]:  antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
++					pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0);
++				*/
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "StaID[%d]:  antsel_pathA = ((%d)), is_packet_to_self = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
++					  pktinfo->station_id,
++					  fat_tab->antsel_rx_keep_0,
++					  pktinfo->is_packet_to_self,
++					  sat_tab->fast_training_beam_num,
++					  rx_power_ant0);
++
++				sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0;
++				sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++;
++				sat_tab->pkt_counter++;
++
++				/*swich beam every N pkt*/
++				if (sat_tab->pkt_counter >= sat_tab->per_beam_training_pkt_num) {
++					sat_tab->pkt_counter = 0;
++					beam_tmp = sat_tab->fast_training_beam_num;
++
++					if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {
++						fat_tab->fat_state = FAT_DECISION_STATE;
++
++#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++						if (dm->support_interface == ODM_ITRF_PCIE)
++							odm_fast_ant_training_hl_smart_antenna_type1(dm);
++#endif
++#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
++						if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
++							odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);
++#endif
++
++					} else {
++						sat_tab->fast_training_beam_num++;
++						phydm_set_all_ant_same_beam_num(dm);
++
++						fat_tab->fat_state = FAT_TRAINING_STATE;
++						PHYDM_DBG(dm, DBG_ANT_DIV, "Update  Beam_num (( %d )) -> (( %d ))\n", beam_tmp, sat_tab->fast_training_beam_num);
++					}
++				}
++			}
++		}
++	}
++#endif
++	else
++#endif
++		if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) {
++			odm_process_rssi_smart(dm, phy_info, pktinfo,
++					       rx_power_ant0);
++		} else { /* @ant_div_type != CG_TRX_SMART_ANTDIV */
++			odm_process_rssi_normal(dm, phy_info, pktinfo,
++						rx_power_ant0);
++		}
++#if 0
++/* PHYDM_DBG(dm,DBG_ANT_DIV,"is_cck_rate=%d, pwdb_all=%d\n",
++ *	     pktinfo->is_cck_rate, phy_info->rx_pwdb_all);
++ * PHYDM_DBG(dm,DBG_ANT_DIV,"antsel_tr_mux=3'b%d%d%d\n",
++ *	     fat_tab->antsel_rx_keep_2, fat_tab->antsel_rx_keep_1,
++ *	     fat_tab->antsel_rx_keep_0);
++ */
++#endif
++}
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
++void odm_set_tx_ant_by_tx_info(void *dm_void, u8 *desc, u8 mac_id)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	if (!(dm->support_ability & ODM_BB_ANT_DIV))
++		return;
++
++	if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
++		return;
++
++	if (dm->support_ic_type == (ODM_RTL8723B | ODM_RTL8721D)) {
++#if (RTL8723B_SUPPORT == 1 || RTL8721D_SUPPORT == 1)
++		SET_TX_DESC_ANTSEL_A_8723B(desc, fat_tab->antsel_a[mac_id]);
++/*PHYDM_DBG(dm,DBG_ANT_DIV,
++ *	   "[8723B] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
++ *	    mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
++ *	    fat_tab->antsel_a[mac_id]);
++ */
++#endif
++	} else if (dm->support_ic_type == ODM_RTL8821) {
++#if (RTL8821A_SUPPORT == 1)
++		SET_TX_DESC_ANTSEL_A_8812(desc, fat_tab->antsel_a[mac_id]);
++/*PHYDM_DBG(dm,DBG_ANT_DIV,
++ *	   "[8821A] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
++ *	    mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
++ *	    fat_tab->antsel_a[mac_id]);
++ */
++#endif
++	} else if (dm->support_ic_type == ODM_RTL8188E) {
++#if (RTL8188E_SUPPORT == 1)
++		SET_TX_DESC_ANTSEL_A_88E(desc, fat_tab->antsel_a[mac_id]);
++		SET_TX_DESC_ANTSEL_B_88E(desc, fat_tab->antsel_b[mac_id]);
++		SET_TX_DESC_ANTSEL_C_88E(desc, fat_tab->antsel_c[mac_id]);
++/*PHYDM_DBG(dm,DBG_ANT_DIV,
++ *	   "[8188E] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
++ *	    mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
++ *	    fat_tab->antsel_a[mac_id]);
++ */
++#endif
++	} else if (dm->support_ic_type == ODM_RTL8821C) {
++#if (RTL8821C_SUPPORT == 1)
++		SET_TX_DESC_ANTSEL_A_8821C(desc, fat_tab->antsel_a[mac_id]);
++/*PHYDM_DBG(dm,DBG_ANT_DIV,
++ *	   "[8821C] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
++ *	    mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
++ *	    fat_tab->antsel_a[mac_id]);
++ */
++#endif
++	} else if (dm->support_ic_type == ODM_RTL8822B) {
++#if (RTL8822B_SUPPORT == 1)
++		SET_TX_DESC_ANTSEL_A_8822B(desc, fat_tab->antsel_a[mac_id]);
++#endif
++
++	}
++}
++#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++
++void odm_set_tx_ant_by_tx_info(
++	struct rtl8192cd_priv *priv,
++	struct tx_desc *pdesc,
++	unsigned short aid)
++{
++	struct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++
++	if (!(dm->support_ability & ODM_BB_ANT_DIV))
++		return;
++
++	if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
++		return;
++
++	if (dm->support_ic_type == ODM_RTL8881A) {
++#if 0
++		/*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);	*/
++#endif
++		pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16)));
++		pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
++	} else if (dm->support_ic_type == ODM_RTL8192E) {
++#if 0
++		/*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__);	*/
++#endif
++		pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16)));
++		pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
++	} else if (dm->support_ic_type == ODM_RTL8197F) {
++#if 0
++		/*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__);	*/
++#endif
++		pdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16)));
++		pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
++	} else if (dm->support_ic_type == ODM_RTL8822B) {
++		pdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16)));
++		pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
++	} else if (dm->support_ic_type == ODM_RTL8188E) {
++#if 0
++		/*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8188E******\n",__FUNCTION__,__LINE__);*/
++#endif
++		pdesc->Dword2 &= set_desc(~BIT(24));
++		pdesc->Dword2 &= set_desc(~BIT(25));
++		pdesc->Dword7 &= set_desc(~BIT(29));
++
++		pdesc->Dword2 |= set_desc(fat_tab->antsel_a[aid] << 24);
++		pdesc->Dword2 |= set_desc(fat_tab->antsel_b[aid] << 25);
++		pdesc->Dword7 |= set_desc(fat_tab->antsel_c[aid] << 29);
++
++	} else if (dm->support_ic_type == ODM_RTL8812) {
++		/*@[path-A]*/
++#if 0
++		/*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);*/
++#endif
++
++		pdesc->Dword6 &= set_desc(~BIT(16));
++		pdesc->Dword6 &= set_desc(~BIT(17));
++		pdesc->Dword6 &= set_desc(~BIT(18));
++
++		pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
++		pdesc->Dword6 |= set_desc(fat_tab->antsel_b[aid] << 17);
++		pdesc->Dword6 |= set_desc(fat_tab->antsel_c[aid] << 18);
++	}
++}
++
++#if 1 /*@def CONFIG_WLAN_HAL*/
++void odm_set_tx_ant_by_tx_info_hal(
++	struct rtl8192cd_priv *priv,
++	void *pdesc_data,
++	u16 aid)
++{
++	struct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	PTX_DESC_DATA_88XX pdescdata = (PTX_DESC_DATA_88XX)pdesc_data;
++
++	if (!(dm->support_ability & ODM_BB_ANT_DIV))
++		return;
++
++	if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
++		return;
++
++	if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8814A |
++	    ODM_RTL8197F | ODM_RTL8822B)) {
++#if 0
++		/*panic_printk("[%s] [%d] **odm_set_tx_ant_by_tx_info_hal**\n",
++		 *	       __FUNCTION__,__LINE__);
++		 */
++#endif
++		pdescdata->ant_sel = 1;
++		pdescdata->ant_sel_a = fat_tab->antsel_a[aid];
++	}
++}
++#endif /*@#ifdef CONFIG_WLAN_HAL*/
++
++#endif
++
++void odm_ant_div_config(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++	PHYDM_DBG(dm, DBG_ANT_DIV, "WIN Config Antenna Diversity\n");
++	/*@
++	if(dm->support_ic_type==ODM_RTL8723B)
++	{
++		if((!dm->swat_tab.ANTA_ON || !dm->swat_tab.ANTB_ON))
++			dm->support_ability &= ~(ODM_BB_ANT_DIV);
++	}
++	*/
++	#if (defined(CONFIG_2T3R_ANTENNA))
++	#if (RTL8822B_SUPPORT == 1)
++		dm->rfe_type = ANT_2T3R_RFE_TYPE;
++	#endif
++	#endif
++
++	#if (defined(CONFIG_2T4R_ANTENNA))
++	#if (RTL8822B_SUPPORT == 1)
++		dm->rfe_type = ANT_2T4R_RFE_TYPE;
++	#endif
++	#endif
++
++	if (dm->support_ic_type == ODM_RTL8723D)
++		dm->ant_div_type = S0S1_SW_ANTDIV;
++#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "CE Config Antenna Diversity\n");
++
++	if (dm->support_ic_type == ODM_RTL8723B)
++		dm->ant_div_type = S0S1_SW_ANTDIV;
++
++	if (dm->support_ic_type == ODM_RTL8723D)
++		dm->ant_div_type = S0S1_SW_ANTDIV;
++#elif (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "IOT Config Antenna Diversity\n");
++
++	if (dm->support_ic_type == ODM_RTL8721D)
++		dm->ant_div_type = CG_TRX_HW_ANTDIV;
++
++#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "AP Config Antenna Diversity\n");
++
++	/* @2 [ NOT_SUPPORT_ANTDIV ] */
++#if (defined(CONFIG_NOT_SUPPORT_ANTDIV))
++	dm->support_ability &= ~(ODM_BB_ANT_DIV);
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n");
++
++	/* @2 [ 2G&5G_SUPPORT_ANTDIV ] */
++#elif (defined(CONFIG_2G5G_SUPPORT_ANTDIV))
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously\n");
++	fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G | ODM_ANTDIV_5G);
++
++	if (dm->support_ic_type & ODM_ANTDIV_SUPPORT)
++		dm->support_ability |= ODM_BB_ANT_DIV;
++	if (*dm->band_type == ODM_BAND_5G) {
++#if (defined(CONFIG_5G_CGCS_RX_DIVERSITY))
++		dm->ant_div_type = CGCS_RX_HW_ANTDIV;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
++		panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
++#elif (defined(CONFIG_5G_CG_TRX_DIVERSITY) ||\
++	defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))
++		dm->ant_div_type = CG_TRX_HW_ANTDIV;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
++		panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
++#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
++		dm->ant_div_type = CG_TRX_SMART_ANTDIV;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n");
++#elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY))
++		dm->ant_div_type = S0S1_SW_ANTDIV;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n");
++#endif
++	} else if (*dm->band_type == ODM_BAND_2_4G) {
++#if (defined(CONFIG_2G_CGCS_RX_DIVERSITY))
++		dm->ant_div_type = CGCS_RX_HW_ANTDIV;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
++#elif (defined(CONFIG_2G_CG_TRX_DIVERSITY) ||\
++	defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))
++		dm->ant_div_type = CG_TRX_HW_ANTDIV;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
++#elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++		dm->ant_div_type = CG_TRX_SMART_ANTDIV;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n");
++#elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY))
++		dm->ant_div_type = S0S1_SW_ANTDIV;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n");
++#endif
++	}
++
++	/* @2 [ 5G_SUPPORT_ANTDIV ] */
++#elif (defined(CONFIG_5G_SUPPORT_ANTDIV))
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n");
++	panic_printk("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n");
++	fat_tab->ant_div_2g_5g = (ODM_ANTDIV_5G);
++	if (*dm->band_type == ODM_BAND_5G) {
++		if (dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)
++			dm->support_ability |= ODM_BB_ANT_DIV;
++#if (defined(CONFIG_5G_CGCS_RX_DIVERSITY))
++		dm->ant_div_type = CGCS_RX_HW_ANTDIV;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
++		panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
++#elif (defined(CONFIG_5G_CG_TRX_DIVERSITY))
++		dm->ant_div_type = CG_TRX_HW_ANTDIV;
++		panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
++#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
++		dm->ant_div_type = CG_TRX_SMART_ANTDIV;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n");
++#elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY))
++		dm->ant_div_type = S0S1_SW_ANTDIV;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n");
++#endif
++	} else if (*dm->band_type == ODM_BAND_2_4G) {
++		PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 2G ant_div_type\n");
++		dm->support_ability &= ~(ODM_BB_ANT_DIV);
++	}
++
++	/* @2 [ 2G_SUPPORT_ANTDIV ] */
++#elif (defined(CONFIG_2G_SUPPORT_ANTDIV))
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n");
++	fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G);
++	if (*dm->band_type == ODM_BAND_2_4G) {
++		if (dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)
++			dm->support_ability |= ODM_BB_ANT_DIV;
++#if (defined(CONFIG_2G_CGCS_RX_DIVERSITY))
++		dm->ant_div_type = CGCS_RX_HW_ANTDIV;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
++#elif (defined(CONFIG_2G_CG_TRX_DIVERSITY))
++		dm->ant_div_type = CG_TRX_HW_ANTDIV;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
++#elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++		dm->ant_div_type = CG_TRX_SMART_ANTDIV;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n");
++#elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY))
++		dm->ant_div_type = S0S1_SW_ANTDIV;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n");
++#endif
++	} else if (*dm->band_type == ODM_BAND_5G) {
++		PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 5G ant_div_type\n");
++		dm->support_ability &= ~(ODM_BB_ANT_DIV);
++	}
++#endif
++#endif
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[AntDiv Config Info] AntDiv_SupportAbility = (( %x ))\n",
++		  ((dm->support_ability & ODM_BB_ANT_DIV) ? 1 : 0));
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[AntDiv Config Info] be_fix_tx_ant = ((%d))\n",
++		  dm->dm_fat_table.b_fix_tx_ant);
++}
++
++void odm_ant_div_timers(void *dm_void, u8 state)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	if (state == INIT_ANTDIV_TIMMER) {
++#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++		odm_initialize_timer(dm,
++				     &dm->dm_swat_table.sw_antdiv_timer,
++				     (void *)odm_sw_antdiv_callback, NULL,
++				     "sw_antdiv_timer");
++#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
++	(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++		odm_initialize_timer(dm, &dm->fast_ant_training_timer,
++				     (void *)odm_fast_ant_training_callback,
++				     NULL, "fast_ant_training_timer");
++#endif
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++		odm_initialize_timer(dm, &dm->evm_fast_ant_training_timer,
++				     (void *)phydm_evm_antdiv_callback, NULL,
++				     "evm_fast_ant_training_timer");
++#endif
++	} else if (state == CANCEL_ANTDIV_TIMMER) {
++#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++		odm_cancel_timer(dm,
++				 &dm->dm_swat_table.sw_antdiv_timer);
++#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
++	(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++		odm_cancel_timer(dm, &dm->fast_ant_training_timer);
++#endif
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++		odm_cancel_timer(dm, &dm->evm_fast_ant_training_timer);
++#endif
++	} else if (state == RELEASE_ANTDIV_TIMMER) {
++#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++		odm_release_timer(dm,
++				  &dm->dm_swat_table.sw_antdiv_timer);
++#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
++	(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++		odm_release_timer(dm, &dm->fast_ant_training_timer);
++#endif
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++		odm_release_timer(dm, &dm->evm_fast_ant_training_timer);
++#endif
++	}
++}
++
++void phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used,
++			char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct	*fat_tab = &dm->dm_fat_table;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 dm_value[10] = {0};
++	char help[] = "-h";
++	u8 i, input_idx = 0;
++
++	for (i = 0; i < 5; i++) {
++		if (input[i + 1]) {
++			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
++			input_idx++;
++		}
++	}
++
++	if (input_idx == 0)
++		return;
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{1} {0:auto, 1:fix main, 2:fix auto}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{2} {antdiv_period}\n");
++		#if (RTL8821C_SUPPORT == 1)
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{3} {en} {0:Default, 1:HW_Div, 2:SW_Div}\n");
++		#endif
++
++	} else if (dm_value[0] == 1) {
++	/*@fixed or auto antenna*/
++		if (dm_value[1] == 0) {
++			dm->ant_type = ODM_AUTO_ANT;
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "AntDiv: Auto\n");
++		} else if (dm_value[1] == 1) {
++			dm->ant_type = ODM_FIX_MAIN_ANT;
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "AntDiv: Fix Main\n");
++		} else if (dm_value[1] == 2) {
++			dm->ant_type = ODM_FIX_AUX_ANT;
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "AntDiv: Fix Aux\n");
++		}
++
++		if (dm->ant_type != ODM_AUTO_ANT) {
++			odm_stop_antenna_switch_dm(dm);
++			if (dm->ant_type == ODM_FIX_MAIN_ANT)
++				odm_update_rx_idle_ant(dm, MAIN_ANT);
++			else if (dm->ant_type == ODM_FIX_AUX_ANT)
++				odm_update_rx_idle_ant(dm, AUX_ANT);
++		} else {
++			phydm_enable_antenna_diversity(dm);
++		}
++		dm->pre_ant_type = dm->ant_type;
++	} else if (dm_value[0] == 2) {
++	/*@dynamic period for AntDiv*/
++		dm->antdiv_period = (u8)dm_value[1];
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "AntDiv_period=((%d))\n", dm->antdiv_period);
++	}
++	#if (RTL8821C_SUPPORT == 1)
++	else if (dm_value[0] == 3 &&
++		 dm->support_ic_type == ODM_RTL8821C) {
++		/*Only for 8821C*/
++		if (dm_value[1] == 0) {
++			fat_tab->force_antdiv_type = false;
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[8821C] AntDiv: Default\n");
++		} else if (dm_value[1] == 1) {
++			fat_tab->force_antdiv_type = true;
++			fat_tab->antdiv_type_dbg = CG_TRX_HW_ANTDIV;
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[8821C] AntDiv: HW diversity\n");
++		} else if (dm_value[1] == 2) {
++			fat_tab->force_antdiv_type = true;
++			fat_tab->antdiv_type_dbg = S0S1_SW_ANTDIV;
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[8821C] AntDiv: SW diversity\n");
++		}
++	}
++	#endif
++	#ifdef ODM_EVM_ENHANCE_ANTDIV
++	else if (dm_value[0] == 4) {
++		if (dm_value[1] == 0) {
++			/*@init parameters for EVM AntDiv*/
++			phydm_evm_sw_antdiv_init(dm);
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "init evm antdiv parameters\n");
++		} else if (dm_value[1] == 1) {
++			/*training number for EVM AntDiv*/
++			dm->antdiv_train_num = (u8)dm_value[2];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "antdiv_train_num = ((%d))\n",
++				 dm->antdiv_train_num);
++		} else if (dm_value[1] == 2) {
++			/*training interval for EVM AntDiv*/
++			dm->antdiv_intvl = (u8)dm_value[2];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "antdiv_intvl = ((%d))\n",
++				 dm->antdiv_intvl);
++		} else if (dm_value[1] == 3) {
++			/*@function period for EVM AntDiv*/
++			dm->evm_antdiv_period = (u8)dm_value[2];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "evm_antdiv_period = ((%d))\n",
++				 dm->evm_antdiv_period);
++		} else if (dm_value[1] == 100) {/*show parameters*/
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "ant_type = ((%d))\n", dm->ant_type);
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "antdiv_train_num = ((%d))\n",
++				 dm->antdiv_train_num);
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "antdiv_intvl = ((%d))\n",
++				 dm->antdiv_intvl);
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "evm_antdiv_period = ((%d))\n",
++				 dm->evm_antdiv_period);
++		}
++	}
++	#ifdef CONFIG_2T4R_ANTENNA
++	else if (dm_value[0] == 5) { /*Only for 8822B 2T4R case*/
++
++		if (dm_value[1] == 0) {
++			dm->ant_type2 = ODM_AUTO_ANT;
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "AntDiv: PathB Auto\n");
++		} else if (dm_value[1] == 1) {
++			dm->ant_type2 = ODM_FIX_MAIN_ANT;
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "AntDiv: PathB Fix Main\n");
++		} else if (dm_value[1] == 2) {
++			dm->ant_type2 = ODM_FIX_AUX_ANT;
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "AntDiv: PathB Fix Aux\n");
++		}
++
++		if (dm->ant_type2 != ODM_AUTO_ANT) {
++			odm_stop_antenna_switch_dm(dm);
++			if (dm->ant_type2 == ODM_FIX_MAIN_ANT)
++				phydm_update_rx_idle_ant_pathb(dm, MAIN_ANT);
++			else if (dm->ant_type2 == ODM_FIX_AUX_ANT)
++				phydm_update_rx_idle_ant_pathb(dm, AUX_ANT);
++		} else {
++			phydm_enable_antenna_diversity(dm);
++		}
++		dm->pre_ant_type2 = dm->ant_type2;
++	}
++	#endif
++	#endif
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void odm_ant_div_reset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++	if (dm->ant_div_type == S0S1_SW_ANTDIV)
++		odm_s0s1_sw_ant_div_reset(dm);
++	#endif
++}
++
++void odm_antenna_diversity_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	odm_ant_div_config(dm);
++	odm_ant_div_init(dm);
++}
++
++void odm_antenna_diversity(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (*dm->mp_mode)
++		return;
++
++	if (!(dm->support_ability & ODM_BB_ANT_DIV)) {
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[Return!!!]   Not Support Antenna Diversity Function\n");
++		return;
++	}
++
++	if (dm->pause_ability & ODM_BB_ANT_DIV) {
++		PHYDM_DBG(dm, DBG_ANT_DIV, "Return: Pause AntDIv in LV=%d\n",
++			  dm->pause_lv_table.lv_antdiv);
++		return;
++	}
++
++	odm_ant_div(dm);
++}
++#endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_antdiv.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_antdiv.h
+new file mode 100644
+index 000000000..9bba14393
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_antdiv.h
+@@ -0,0 +1,534 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDMANTDIV_H__
++#define __PHYDMANTDIV_H__
++
++/*@#define ANTDIV_VERSION	"2.0"  //2014.11.04*/
++/*@#define ANTDIV_VERSION	"2.1"  //2015.01.13  Dino*/
++/*@#define ANTDIV_VERSION	"2.2"  2015.01.16  Dino*/
++/*@#define ANTDIV_VERSION	"3.1"  2015.07.29  YuChen,remove 92c 92d 8723a*/
++/*@#define ANTDIV_VERSION	"3.2"  2015.08.11  Stanley, disable antenna*/
++				/*@diversity when BT is enable for 8723B*/
++/*@#define ANTDIV_VERSION	"3.3"  2015.08.12  Stanley. 8723B does not*/
++				/*@need to check the antenna is control by BT,*/
++				/*@because antenna diversity only works when */
++				/*@BT is disable or radio off*/
++/*@#define ANTDIV_VERSION	"3.4"  2015.08.28 Dino 1.Add 8821A Smart */
++				/*@Antenna 2. Add 8188F SW S0S1 Antenna*/
++				/*@Diversity*/
++/*@#define ANTDIV_VERSION	"3.5"  2015.10.07 Stanley Always check antenna*/
++				/*@detection result from BT-coex. for 8723B,*/
++				/*@not from PHYDM*/
++/*@#define ANTDIV_VERSION	"3.6"*/ /*@2015.11.16  Stanley  */
++/*@#define ANTDIV_VERSION	"3.7"  2015.11.20 Dino Add SmartAnt FAT Patch */
++/*@#define ANTDIV_VERSION	"3.8"  2015.12.21 Dino, Add SmartAnt dynamic*/
++				/*@training packet num */
++/*@#define ANTDIV_VERSION	"3.9"  2016.01.05 Dino, Add SmartAnt cmd for*/
++				/*@converting single & two smtant, and add cmd*/
++				/*@for adjust truth table */
++#define ANTDIV_VERSION "4.0"	/*@2017.05.25  Mark, Add SW antenna diversity*/
++				/*@for 8821c because HW transient issue */
++
++/* @1 ============================================================
++ * 1  Definition
++ * 1 ============================================================
++ */
++
++#define	ANTDIV_INIT		0xff
++#define	MAIN_ANT	1		/*@ant A or ant Main   or S1*/
++#define	AUX_ANT		2		/*@AntB or ant Aux   or S0*/
++#define	MAX_ANT		3		/* @3 for AP using*/
++
++#define ANT1_2G 0
++/* @= ANT2_5G for 8723D  BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */
++#define ANT2_2G 1
++/* @= ANT1_5G for 8723D  BTG S0  RX S0S1 diversity for 8723D, TX fixed at S1 */
++/*smart antenna*/
++#define SUPPORT_RF_PATH_NUM 4
++#define SUPPORT_BEAM_PATTERN_NUM 4
++#define NUM_ANTENNA_8821A	2
++
++#define SUPPORT_BEAM_SET_PATTERN_NUM		16
++
++#define	NO_FIX_TX_ANT		0
++#define	FIX_TX_AT_MAIN	1
++#define	FIX_AUX_AT_MAIN	2
++
++/* @Antenna Diversty Control type */
++#define	ODM_AUTO_ANT		0
++#define	ODM_FIX_MAIN_ANT	1
++#define	ODM_FIX_AUX_ANT	2
++
++#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\
++			ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A |\
++			ODM_RTL8197F | ODM_RTL8721D)
++#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\
++			ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B)
++#define ODM_JGR3_ANTDIV_SUPPORT ODM_RTL8197G
++#define ODM_ANTDIV_SUPPORT	(ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT |\
++			ODM_JGR3_ANTDIV_SUPPORT)
++#define ODM_SMART_ANT_SUPPORT	(ODM_RTL8188E | ODM_RTL8192E)
++#define ODM_HL_SMART_ANT_TYPE1_SUPPORT		(ODM_RTL8821 | ODM_RTL8822B)
++
++#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\
++			ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D |\
++			ODM_RTL8197F | ODM_RTL8197G)
++#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\
++			ODM_RTL8821C | ODM_RTL8822B)
++
++#define ODM_EVM_ANTDIV_IC (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8822B |\
++			ODM_RTL8197G)
++
++#define ODM_ANTDIV_2G	BIT(0)
++#define ODM_ANTDIV_5G	BIT(1)
++
++#define ANTDIV_ON	1
++#define ANTDIV_OFF	0
++
++#define ANT_PATH_A	0
++#define ANT_PATH_B	1
++#define ANT_PATH_AB	2
++
++#define FAT_ON	1
++#define FAT_OFF	0
++
++#define TX_BY_DESC	1
++#define TX_BY_REG	0
++
++#define RSSI_METHOD	0
++#define EVM_METHOD		1
++#define CRC32_METHOD	2
++#define TP_METHOD		3
++
++#define INIT_ANTDIV_TIMMER		0
++#define CANCEL_ANTDIV_TIMMER	1
++#define RELEASE_ANTDIV_TIMMER	2
++
++#define CRC32_FAIL	1
++#define CRC32_OK	0
++
++#define evm_rssi_th_high	25
++#define evm_rssi_th_low	20
++
++#define NORMAL_STATE_MIAN	1
++#define NORMAL_STATE_AUX	2
++#define TRAINING_STATE		3
++
++#define FORCE_RSSI_DIFF 10
++
++#define HT_IDX 16
++#define VHT_IDX 20
++
++#define CSI_ON	1
++#define CSI_OFF	0
++
++#define DIVON_CSIOFF 1
++#define DIVOFF_CSION 2
++
++#define BDC_DIV_TRAIN_STATE	0
++#define bdc_bfer_train_state	1
++#define BDC_DECISION_STATE		2
++#define BDC_BF_HOLD_STATE		3
++#define BDC_DIV_HOLD_STATE		4
++
++#define BDC_MODE_1 1
++#define BDC_MODE_2 2
++#define BDC_MODE_3 3
++#define BDC_MODE_4 4
++#define BDC_MODE_NULL 0xff
++
++/*SW S0S1 antenna diversity*/
++#define SWAW_STEP_INIT			0xff
++#define SWAW_STEP_PEEK		0
++#define SWAW_STEP_DETERMINE	1
++
++#define RSSI_CHECK_RESET_PERIOD	10
++#define RSSI_CHECK_THRESHOLD		50
++
++/*@Hong Lin Smart antenna*/
++#define HL_SMTANT_2WIRE_DATA_LEN 24
++
++#if (RTL8723D_SUPPORT == 1)
++	#ifndef CONFIG_ANTDIV_PERIOD
++		#define CONFIG_ANTDIV_PERIOD 1
++	#endif
++#endif
++/* @1 ============================================================
++ * 1  structure
++ * 1 ============================================================
++ */
++
++
++struct sw_antenna_switch {
++	u8		double_chk_flag;
++	/*@If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than*/
++	/*@check this antenna again*/
++	u8		try_flag;
++	s32		pre_rssi;
++	u8		cur_antenna;
++	u8		pre_ant;
++	u8		rssi_trying;
++	u8		reset_idx;
++	u8		train_time;
++	u8		train_time_flag;
++	/*@base on RSSI difference between two antennas*/
++	struct phydm_timer_list	sw_antdiv_timer;
++	u32		pkt_cnt_sw_ant_div_by_ctrl_frame;
++	boolean		is_sw_ant_div_by_ctrl_frame;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++#if USE_WORKITEM
++	RT_WORK_ITEM	phydm_sw_antenna_switch_workitem;
++#endif
++#endif
++
++	/* @AntDect (Before link Antenna Switch check) need to be moved*/
++	u16		single_ant_counter;
++	u16		dual_ant_counter;
++	u16		aux_fail_detec_counter;
++	u16		retry_counter;
++	u8		swas_no_link_state;
++	u32		swas_no_link_bk_reg948;
++	boolean		ANTA_ON;	/*To indicate ant A is or not*/
++	boolean		ANTB_ON;	/*@To indicate ant B is on or not*/
++	boolean		pre_aux_fail_detec;
++	boolean		rssi_ant_dect_result;
++	u8		ant_5g;
++	u8		ant_2g;
++};
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++struct _BF_DIV_COEX_ {
++	boolean w_bfer_client[ODM_ASSOCIATE_ENTRY_NUM];
++	boolean w_bfee_client[ODM_ASSOCIATE_ENTRY_NUM];
++	u32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM];
++	u32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM];
++
++	u8 bd_ccoex_type_wbfer;
++	u8 num_txbfee_client;
++	u8 num_txbfer_client;
++	u8 bdc_try_counter;
++	u8 bdc_hold_counter;
++	u8 bdc_mode;
++	u8 bdc_active_mode;
++	u8 BDC_state;
++	u8 bdc_rx_idle_update_counter;
++	u8 num_client;
++	u8 pre_num_client;
++	u8 num_bf_tar;
++	u8 num_div_tar;
++
++	boolean is_all_div_sta_idle;
++	boolean is_all_bf_sta_idle;
++	boolean bdc_try_flag;
++	boolean BF_pass;
++	boolean DIV_pass;
++};
++#endif
++#endif
++
++struct phydm_fat_struct {
++	u8	bssid[6];
++	u8	antsel_rx_keep_0;
++	u8	antsel_rx_keep_1;
++	u8	antsel_rx_keep_2;
++	u8	antsel_rx_keep_3;
++	u32	ant_sum_rssi[7];
++	u32	ant_rssi_cnt[7];
++	u32	ant_ave_rssi[7];
++	u8	fat_state;
++	u8	fat_state_cnt;
++	u32	train_idx;
++	u8	antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
++	u8	antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
++	u8	antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
++	u16	main_ht_cnt[HT_IDX];
++	u16	aux_ht_cnt[HT_IDX];
++	u16	main_vht_cnt[VHT_IDX];
++	u16	aux_vht_cnt[VHT_IDX];
++	u16	main_sum[ODM_ASSOCIATE_ENTRY_NUM];
++	u16	aux_sum[ODM_ASSOCIATE_ENTRY_NUM];
++	u16	main_cnt[ODM_ASSOCIATE_ENTRY_NUM];
++	u16	aux_cnt[ODM_ASSOCIATE_ENTRY_NUM];
++	u16	main_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
++	u16	aux_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
++	u16	main_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
++	u16	aux_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
++	u8	rx_idle_ant;
++	u8	rx_idle_ant2;
++	u32	rvrt_val; /*all rvrt_val for pause API must set to u32*/
++	u8	ant_div_on_off;
++	u8	div_path_type;
++	boolean	is_become_linked;
++	boolean get_stats;
++	u32	min_max_rssi;
++	u8	idx_ant_div_counter_2g;
++	u8	idx_ant_div_counter_5g;
++	u8	ant_div_2g_5g;
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++	/*@For 1SS RX phy rate*/
++	u32	main_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
++	u32	aux_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
++	u32	main_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
++	u32	aux_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
++
++	/*@For 2SS RX phy rate*/
++	u32	main_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];/*@2SS with A1+B*/
++	u32	aux_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];/*@2SS with A2+B*/
++	u32	main_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];
++	u32	aux_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];
++
++	boolean	evm_method_enable;
++	u8	target_ant_evm;
++	u8	target_ant_crc32;
++	u8	target_ant_tp;
++	u8	target_ant_enhance;
++	u8	pre_target_ant_enhance;
++	u16	main_mpdu_ok_cnt;
++	u16	aux_mpdu_ok_cnt;
++
++	u32	crc32_ok_cnt;
++	u32	crc32_fail_cnt;
++	u32	main_crc32_ok_cnt;
++	u32	aux_crc32_ok_cnt;
++	u32	main_crc32_fail_cnt;
++	u32	aux_crc32_fail_cnt;
++
++	u32	main_tp;
++	u32	aux_tp;
++	u32	main_tp_cnt;
++	u32	aux_tp_cnt;
++
++	u8	pre_antdiv_rssi;
++	u8	pre_antdiv_tp;
++#endif
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	u32    cck_ctrl_frame_cnt_main;
++	u32    cck_ctrl_frame_cnt_aux;
++	u32    ofdm_ctrl_frame_cnt_main;
++	u32    ofdm_ctrl_frame_cnt_aux;
++	u32	main_ctrl_sum;
++	u32	aux_ctrl_sum;
++	u32	main_ctrl_cnt;
++	u32	aux_ctrl_cnt;
++#endif
++	u8	b_fix_tx_ant;
++	boolean	fix_ant_bfee;
++	boolean	enable_ctrl_frame_antdiv;
++	boolean	use_ctrl_frame_antdiv;
++	boolean	*is_no_csi_feedback;
++	boolean	force_antdiv_type;
++	u8	antdiv_type_dbg;
++	u8	hw_antsw_occur;
++	u8	*p_force_tx_by_desc;
++	u8	force_tx_by_desc;
++	/*@A temp value, will hook to driver team's outer parameter later*/
++	u8	*p_default_s0_s1;
++	u8	default_s0_s1;
++};
++
++/* @1 ============================================================
++ * 1  enumeration
++ * 1 ============================================================
++ */
++
++enum fat_state /*@Fast antenna training*/
++{
++	FAT_BEFORE_LINK_STATE	= 0,
++	FAT_PREPARE_STATE			= 1,
++	FAT_TRAINING_STATE		= 2,
++	FAT_DECISION_STATE		= 3
++};
++
++enum ant_div_type {
++	NO_ANTDIV			= 0xFF,
++	CG_TRX_HW_ANTDIV			= 0x01,
++	CGCS_RX_HW_ANTDIV		= 0x02,
++	FIXED_HW_ANTDIV		= 0x03,
++	CG_TRX_SMART_ANTDIV	= 0x04,
++	CGCS_RX_SW_ANTDIV	= 0x05,
++	S0S1_SW_ANTDIV	= 0x06, /*@8723B intrnal switch S0 S1*/
++	S0S1_TRX_HW_ANTDIV	= 0x07, /*TRX S0S1 diversity for 8723D*/
++	HL_SW_SMART_ANT_TYPE1	= 0x10,
++	/*@Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys,*/
++	/*@and each ant. is equipped with 4 antenna patterns*/
++	HL_SW_SMART_ANT_TYPE2	= 0x11
++	/*@Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/
++};
++
++/* @1 ============================================================
++ * 1  function prototype
++ * 1 ============================================================
++ */
++
++void odm_stop_antenna_switch_dm(void *dm_void);
++
++void phydm_enable_antenna_diversity(void *dm_void);
++
++void odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C,....*/
++			);
++
++#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link
++
++void odm_sw_ant_div_rest_after_link(void *dm_void);
++
++void odm_ant_div_on_off(void *dm_void, u8 swch, u8 path);
++
++void odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch);
++
++#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++
++void phydm_antdiv_reset_statistic(void *dm_void, u32 macid);
++
++void odm_update_rx_idle_ant(void *dm_void, u8 ant);
++
++void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant);
++
++void phydm_set_antdiv_val(void *dm_void, u32 *val_buf,	u8 val_len);
++
++#if (RTL8723B_SUPPORT == 1)
++void odm_update_rx_idle_ant_8723b(void *dm_void, u8 ant, u32 default_ant,
++				  u32 optional_ant);
++#endif
++
++#if (RTL8188F_SUPPORT == 1)
++void phydm_update_rx_idle_antenna_8188F(void *dm_void,	u32 default_ant);
++#endif
++
++#if (RTL8723D_SUPPORT == 1)
++
++void phydm_set_tx_ant_pwr_8723d(void *dm_void, u8 ant);
++
++void odm_update_rx_idle_ant_8723d(void *dm_void, u8 ant, u32 default_ant,
++				  u32 optional_ant);
++
++#endif
++
++#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void odm_sw_antdiv_callback(struct phydm_timer_list *timer);
++
++void odm_sw_antdiv_workitem_callback(void *context);
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++
++void odm_sw_antdiv_workitem_callback(void *context);
++
++void odm_sw_antdiv_callback(void *function_context);
++
++#endif
++
++void odm_s0s1_sw_ant_div_by_ctrl_frame(void *dm_void, u8 step);
++
++void odm_antsel_statistics_ctrl(void *dm_void,	u8 antsel_tr_mux,
++				u32 rx_pwdb_all);
++
++void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void *dm_void,
++						    void *phy_info_void,
++						    void *pkt_info_void);
++
++#endif
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++void phydm_evm_sw_antdiv_init(void *dm_void);
++
++void phydm_rx_rate_for_antdiv(void *dm_void, void *pkt_info_void);
++
++void phydm_antdiv_reset_rx_rate(void *dm_void);
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void phydm_evm_antdiv_callback(struct phydm_timer_list *timer);
++
++void phydm_evm_antdiv_workitem_callback(void *context);
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++void phydm_evm_antdiv_callback(void *dm_void);
++
++void phydm_evm_antdiv_workitem_callback(void *context);
++
++#else
++void phydm_evm_antdiv_callback(void *dm_void);
++#endif
++
++#endif
++
++void odm_hw_ant_div(void *dm_void);
++
++#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
++	(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++void odm_fast_ant_training(
++	void *dm_void);
++
++void odm_fast_ant_training_callback(void *dm_void);
++
++void odm_fast_ant_training_work_item_callback(void *dm_void);
++#endif
++
++void odm_ant_div_init(void *dm_void);
++
++void odm_ant_div(void *dm_void);
++
++void odm_antsel_statistics(void *dm_void, void *phy_info_void,
++			   u8 antsel_tr_mux, u32 mac_id, u32 utility, u8 method,
++			   u8 is_cck_rate);
++
++void odm_process_rssi_for_ant_div(void *dm_void, void *phy_info_void,
++				  void *pkt_info_void);
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++void odm_set_tx_ant_by_tx_info(void *dm_void,	 u8 *desc, u8 mac_id);
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++
++struct tx_desc;
++/*@declared tx_desc here or compile error happened when enabled 8822B*/
++
++void odm_set_tx_ant_by_tx_info(struct rtl8192cd_priv *priv,
++			       struct tx_desc *pdesc, unsigned short aid);
++
++#if 1 /*@def def CONFIG_WLAN_HAL*/
++void odm_set_tx_ant_by_tx_info_hal(struct rtl8192cd_priv *priv,
++				   void *pdesc_data, u16 aid);
++#endif /*@#ifdef CONFIG_WLAN_HAL*/
++#endif
++
++void odm_ant_div_config(void *dm_void);
++
++void odm_ant_div_timers(void *dm_void, u8 state);
++
++void phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used,
++			char *output, u32 *_out_len);
++
++void odm_ant_div_reset(void *dm_void);
++
++void odm_antenna_diversity_init(void *dm_void);
++
++void odm_antenna_diversity(void *dm_void);
++#endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/
++#endif /*@#ifndef	__ODMANTDIV_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_api.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_api.c
+new file mode 100644
+index 000000000..6e5a8597a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_api.c
+@@ -0,0 +1,3383 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ * ************************************************************
++ */
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++enum channel_width phydm_rxsc_2_bw(void *dm_void, u8 rxsc)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	enum channel_width bw = 0;
++
++	/* @Check RX bandwidth */
++	if (rxsc == 0)
++		bw = *dm->band_width; /*@full bw*/
++	else if (rxsc >= 1 && rxsc <= 8)
++		bw = CHANNEL_WIDTH_20;
++	else if (rxsc >= 9 && rxsc <= 12)
++		bw = CHANNEL_WIDTH_40;
++	else /*if (rxsc >= 13)*/
++		bw = CHANNEL_WIDTH_80;
++
++	return bw;
++}
++
++void phydm_reset_bb_hw_cnt(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	/*@ Reset all counter when 1 */
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 1);
++		odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 0);
++	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		/*@ Reset all counter when 1 (including PMAC and PHY)*/
++		/* Reset Page F counter*/
++		odm_set_bb_reg(dm, R_0xb58, BIT(0), 1);
++		odm_set_bb_reg(dm, R_0xb58, BIT(0), 0);
++	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		odm_set_bb_reg(dm, R_0xf14, BIT(16), 0x1);
++		odm_set_bb_reg(dm, R_0xf14, BIT(16), 0x0);
++	}
++}
++
++void phydm_dynamic_ant_weighting(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#ifdef DYN_ANT_WEIGHTING_SUPPORT
++	#if (RTL8197F_SUPPORT)
++	if (dm->support_ic_type & (ODM_RTL8197F))
++		phydm_dynamic_ant_weighting_8197f(dm);
++	#endif
++
++	#if (RTL8812A_SUPPORT)
++	if (dm->support_ic_type & (ODM_RTL8812)) {
++		phydm_dynamic_ant_weighting_8812a(dm);
++	}
++	#endif
++
++	#if (RTL8822B_SUPPORT)
++	if (dm->support_ic_type & (ODM_RTL8822B))
++		phydm_dynamic_ant_weighting_8822b(dm);
++	#endif
++#endif
++}
++
++#ifdef DYN_ANT_WEIGHTING_SUPPORT
++void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used,
++			  char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "echo dis_dym_ant_weighting {0/1}\n");
++
++	} else {
++		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
++
++		if (var1[0] == 1) {
++			dm->is_disable_dym_ant_weighting = 1;
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "Disable dyn-ant-weighting\n");
++		} else {
++			dm->is_disable_dym_ant_weighting = 0;
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "Enable dyn-ant-weighting\n");
++		}
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++#endif
++
++void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 rx_ant = 0, tx_ant = 0;
++	u8 path_bitmap = 1;
++
++	path_bitmap = (u8)phydm_gen_bitmask(num_rf_path);
++
++	/*PHYDM_DBG(dm, ODM_COMP_INIT, "path_bitmap=0x%x\n", path_bitmap);*/
++
++	dm->tx_ant_status = path_bitmap;
++	dm->rx_ant_status = path_bitmap;
++
++	if (num_rf_path == PDM_1SS)
++		return;
++
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	if (dm->support_ic_type &
++		   (ODM_RTL8192F | ODM_RTL8192E | ODM_RTL8197F)) {
++		dm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0xc04, 0x3);
++		dm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x90c, 0x3);
++	} else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8814A)) {
++		dm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0x808, 0xf);
++		dm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x80c, 0xf);
++	}
++	#endif
++	/* @trx_ant_status are already updated in trx mode API in JGR3 ICs */
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "[%s]ant_status{tx,rx}={0x%x, 0x%x}\n",
++		  __func__, dm->tx_ant_status, dm->rx_ant_status);
++}
++
++void phydm_config_ofdm_tx_path(void *dm_void, enum bb_path path)
++{
++#if (RTL8192E_SUPPORT || RTL8192F_SUPPORT || RTL8812A_SUPPORT)
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 ofdm_tx_path = 0x33;
++
++	if (dm->num_rf_path == PDM_1SS)
++		return;
++
++	switch (dm->support_ic_type) {
++	#if (RTL8192E_SUPPORT || RTL8192F_SUPPORT)
++	case ODM_RTL8192E:
++	case ODM_RTL8192F:
++		if (path == BB_PATH_A)
++			odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121313);
++		else if (path == BB_PATH_B)
++			odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x82221323);
++		else if (path == BB_PATH_AB)
++			odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333);
++
++		break;
++	#endif
++
++	#if (RTL8812A_SUPPORT)
++	case ODM_RTL8812:
++		if (path == BB_PATH_A)
++			ofdm_tx_path = 0x11;
++		else if (path == BB_PATH_B)
++			ofdm_tx_path = 0x22;
++		else if (path == BB_PATH_AB)
++			ofdm_tx_path = 0x33;
++
++		odm_set_bb_reg(dm, R_0x80c, 0xff00, ofdm_tx_path);
++
++		break;
++	#endif
++
++	default:
++		break;
++	}
++#endif
++}
++
++void phydm_config_ofdm_rx_path(void *dm_void, enum bb_path path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 val = 0;
++
++	if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8192F)) {
++#if (RTL8192E_SUPPORT || RTL8192F_SUPPORT)
++		if (path == BB_PATH_A)
++			val = 1;
++		else if (path == BB_PATH_B)
++			val = 2;
++		else if (path == BB_PATH_AB)
++			val = 3;
++
++		odm_set_bb_reg(dm, R_0xc04, 0xff, ((val << 4) | val));
++		odm_set_bb_reg(dm, R_0xd04, 0xf, val);
++#endif
++	}
++#if (RTL8812A_SUPPORT || RTL8822B_SUPPORT)
++	else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) {
++		if (path == BB_PATH_A)
++			val = 1;
++		else if (path == BB_PATH_B)
++			val = 2;
++		else if (path == BB_PATH_AB)
++			val = 3;
++
++		odm_set_bb_reg(dm, R_0x808, MASKBYTE0, ((val << 4) | val));
++	}
++#endif
++}
++
++void phydm_config_cck_rx_antenna_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	if (dm->support_ic_type & ODM_IC_1SS)
++		return;
++
++	/*@CCK 2R CCA parameters*/
++	odm_set_bb_reg(dm, R_0xa00, BIT(15), 0x0); /*@Disable Ant diversity*/
++	odm_set_bb_reg(dm, R_0xa70, BIT(7), 0); /*@Concurrent CCA at LSB & USB*/
++	odm_set_bb_reg(dm, R_0xa74, BIT(8), 0); /*RX path diversity enable*/
++	odm_set_bb_reg(dm, R_0xa14, BIT(7), 0); /*r_en_mrc_antsel*/
++	odm_set_bb_reg(dm, R_0xa20, (BIT(5) | BIT(4)), 1); /*@MBC weighting*/
++
++	if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F))
++		odm_set_bb_reg(dm, R_0xa08, BIT(28), 1); /*r_cck_2nd_sel_eco*/
++	else if (dm->support_ic_type & ODM_RTL8814A)
++		odm_set_bb_reg(dm, R_0xa84, BIT(28), 1); /*@2R CCA only*/
++#endif
++}
++
++void phydm_config_cck_rx_path(void *dm_void, enum bb_path path)
++{
++#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 path_div_select = 0;
++	u8 cck_path[2] = {0};
++	u8 en_2R_path = 0;
++	u8 en_2R_mrc = 0;
++	u8 i = 0, j = 0;
++	u8 num_enable_path = 0;
++	u8 cck_mrc_max_path = 2;
++
++	if (dm->support_ic_type & ODM_IC_1SS)
++		return;
++
++	for (i = 0; i < 4; i++) {
++		if (path & BIT(i)) { /*@ex: PHYDM_ABCD*/
++			num_enable_path++;
++			cck_path[j] = i;
++			j++;
++		}
++		if (num_enable_path >= cck_mrc_max_path)
++			break;
++	}
++
++	if (num_enable_path > 1) {
++		path_div_select = 1;
++		en_2R_path = 1;
++		en_2R_mrc = 1;
++	} else {
++		path_div_select = 0;
++		en_2R_path = 0;
++		en_2R_mrc = 0;
++	}
++	/*@CCK_1 input signal path*/
++	odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), cck_path[0]);
++	/*@CCK_2 input signal path*/
++	odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), cck_path[1]);
++	/*@enable Rx path diversity*/
++	odm_set_bb_reg(dm, R_0xa74, BIT(8), path_div_select);
++	/*@enable 2R Rx path*/
++	odm_set_bb_reg(dm, R_0xa2c, BIT(18), en_2R_path);
++	/*@enable 2R MRC*/
++	odm_set_bb_reg(dm, R_0xa2c, BIT(22), en_2R_mrc);
++	if (dm->support_ic_type & (ODM_RTL8192F | ODM_RTL8197F)) {
++		if (path == BB_PATH_A) {
++			odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);
++			odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 0);
++			odm_set_bb_reg(dm, R_0xa74, BIT(8), 0);
++			odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0);
++			odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0);
++		} else if (path == BB_PATH_B) {/*@for DC cancellation*/
++			odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 1);
++			odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);
++			odm_set_bb_reg(dm, R_0xa74, BIT(8), 0);
++			odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0);
++			odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0);
++		} else if (path == BB_PATH_AB) {
++			odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);
++			odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);
++			odm_set_bb_reg(dm, R_0xa74, BIT(8), 1);
++			odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 1);
++			odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 1);
++		}
++	} else if (dm->support_ic_type & ODM_RTL8822B) {
++		if (path == BB_PATH_A) {
++			odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);
++			odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 0);
++		} else {
++			odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 1);
++			odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);
++		}
++	}
++
++#endif
++}
++
++void phydm_config_cck_tx_path(void *dm_void, enum bb_path path)
++{
++#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (path == BB_PATH_A)
++		odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x8);
++	else if (path == BB_PATH_B)
++		odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x4);
++	else /*if (path == BB_PATH_AB)*/
++		odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0xc);
++#endif
++}
++
++void phydm_config_trx_path_v2(void *dm_void, char input[][16], u32 *_used,
++			      char *output, u32 *_out_len)
++{
++#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\
++	RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8197G_SUPPORT ||\
++	RTL8812F_SUPPORT)
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 val[10] = {0};
++	char help[] = "-h";
++	u8 i = 0, input_idx = 0;
++	enum bb_path tx_path, rx_path, tx_path_ctrl;
++	boolean dbg_mode_en;
++
++	if (!(dm->support_ic_type &
++	    (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8822C |
++	     ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8197G)))
++		return;
++
++	for (i = 0; i < 5; i++) {
++		if (input[i + 1]) {
++			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
++			input_idx++;
++		}
++	}
++
++	if (input_idx == 0)
++		return;
++
++	dbg_mode_en = (boolean)val[0];
++	tx_path = (enum bb_path)val[1];
++	rx_path = (enum bb_path)val[2];
++	tx_path_ctrl = (enum bb_path)val[3];
++
++	if ((strcmp(input[1], help) == 0)) {
++		if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8822B |
++					   ODM_RTL8192F)) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "{en} {tx_path} {rx_path} {ff:auto, else:1ss_tx_path}\n"
++				 );
++		} else {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "{en} {tx_path} {rx_path} {is_tx_2_path}\n");
++		}
++
++	} else if (dbg_mode_en) {
++		dm->is_disable_phy_api = false;
++		phydm_api_trx_mode(dm, tx_path, rx_path, tx_path_ctrl);
++		dm->is_disable_phy_api = true;
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "T/RX path = 0x%x/0x%x, tx_path_ctrl=%d\n",
++			 tx_path, rx_path, tx_path_ctrl);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "T/RX path_en={0x%x, 0x%x}, tx_1ss=%d\n",
++			 dm->tx_ant_status, dm->rx_ant_status,
++			 dm->tx_1ss_status);
++	} else {
++		dm->is_disable_phy_api = false;
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Disable API debug mode\n");
++	}
++#endif
++}
++
++void phydm_config_trx_path_v1(void *dm_void, char input[][16], u32 *_used,
++			      char *output, u32 *_out_len)
++{
++#if (RTL8192E_SUPPORT || RTL8812A_SUPPORT)
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 val[10] = {0};
++	char help[] = "-h";
++	u8 i = 0, input_idx = 0;
++
++	if (!(dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)))
++		return;
++
++	for (i = 0; i < 5; i++) {
++		if (input[i + 1]) {
++			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
++			input_idx++;
++		}
++	}
++
++	if (input_idx == 0)
++		return;
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{0:CCK, 1:OFDM} {1:TX, 2:RX} {1:path_A, 2:path_B, 3:path_AB}\n");
++
++		*_used = used;
++		*_out_len = out_len;
++		return;
++
++	} else if (val[0] == 0) {
++	/* @CCK */
++		if (val[1] == 1) { /*TX*/
++			if (val[2] == 1)
++				phydm_config_cck_tx_path(dm, BB_PATH_A);
++			else if (val[2] == 2)
++				phydm_config_cck_tx_path(dm, BB_PATH_B);
++			else if (val[2] == 3)
++				phydm_config_cck_tx_path(dm, BB_PATH_AB);
++		} else if (val[1] == 2) { /*RX*/
++
++			phydm_config_cck_rx_antenna_init(dm);
++
++			if (val[2] == 1)
++				phydm_config_cck_rx_path(dm, BB_PATH_A);
++			else if (val[2] == 2)
++				phydm_config_cck_rx_path(dm, BB_PATH_B);
++			else if (val[2] == 3)
++				phydm_config_cck_rx_path(dm, BB_PATH_AB);
++			}
++		}
++	/* OFDM */
++	else if (val[0] == 1) {
++		if (val[1] == 1) /*TX*/
++			phydm_config_ofdm_tx_path(dm, val[2]);
++		else if (val[1] == 2) /*RX*/
++			phydm_config_ofdm_rx_path(dm, val[2]);
++	}
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n",
++		 (val[0] == 1) ? "OFDM" : "CCK",
++		 (val[1] == 1) ? "TX" : "RX",
++		 (val[2] & 0x1) ? "A" : "", (val[2] & 0x2) ? "B" : "",
++		 (val[2] & 0x4) ? "C" : "",
++		 (val[2] & 0x8) ? "D" : "");
++
++	*_used = used;
++	*_out_len = out_len;
++#endif
++}
++
++void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used,
++			   char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) {
++		#if (RTL8192E_SUPPORT || RTL8812A_SUPPORT)
++		phydm_config_trx_path_v1(dm, input, _used, output, _out_len);
++		#endif
++	} else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F |
++		   ODM_RTL8192F | ODM_RTL8822C | ODM_RTL8812F |
++		   ODM_RTL8197G | ODM_RTL8814B)) {
++		#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT ||\
++		     RTL8192F_SUPPORT || RTL8822C_SUPPORT ||\
++		     RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\
++		     RTL8197G_SUPPORT)
++		phydm_config_trx_path_v2(dm, input, _used, output, _out_len);
++		#endif
++	}
++}
++
++void phydm_tx_2path(void *dm_void)
++{
++#if (defined(PHYDM_COMPILE_IC_2SS))
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	enum bb_path rx_path = (enum bb_path)dm->rx_ant_status;
++
++	PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
++
++
++	if (!(dm->support_ic_type & ODM_IC_2SS))
++		return;
++
++	#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8197F_SUPPORT ||\
++	     RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
++	if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F |
++	    ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G))
++		phydm_api_trx_mode(dm, BB_PATH_AB, rx_path, BB_PATH_AB);
++	#endif
++
++	#if (RTL8812A_SUPPORT || RTL8192E_SUPPORT)
++	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) {
++		phydm_config_cck_tx_path(dm, BB_PATH_AB);
++		phydm_config_ofdm_tx_path(dm, BB_PATH_AB);
++	}
++	#endif
++#endif
++}
++
++void phydm_stop_3_wire(void *dm_void, u8 set_type)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (set_type == PHYDM_SET) {
++		/*@[Stop 3-wires]*/
++		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++			odm_set_bb_reg(dm, R_0x180c, 0x3, 0x0);
++			odm_set_bb_reg(dm, R_0x180c, BIT(28), 0x1);
++
++			#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++			if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
++				odm_set_bb_reg(dm, R_0x410c, 0x3, 0x0);
++				odm_set_bb_reg(dm, R_0x410c, BIT(28), 0x1);
++			}
++			#endif
++
++			#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++			if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
++				odm_set_bb_reg(dm, R_0x520c, 0x3, 0x0);
++				odm_set_bb_reg(dm, R_0x520c, BIT(28), 0x1);
++				odm_set_bb_reg(dm, R_0x530c, 0x3, 0x0);
++				odm_set_bb_reg(dm, R_0x530c, BIT(28), 0x1);
++			}
++			#endif
++		} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++			odm_set_bb_reg(dm, R_0xc00, 0xf, 0x4);
++			odm_set_bb_reg(dm, R_0xe00, 0xf, 0x4);
++		} else {
++			odm_set_bb_reg(dm, R_0x88c, 0xf00000, 0xf);
++		}
++
++	} else { /*@if (set_type == PHYDM_REVERT)*/
++
++		/*@[Start 3-wires]*/
++		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++			odm_set_bb_reg(dm, R_0x180c, 0x3, 0x3);
++			odm_set_bb_reg(dm, R_0x180c, BIT(28), 0x1);
++
++			#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++			if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
++				odm_set_bb_reg(dm, R_0x410c, 0x3, 0x3);
++				odm_set_bb_reg(dm, R_0x410c, BIT(28), 0x1);
++			}
++			#endif
++
++			#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++			if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
++				odm_set_bb_reg(dm, R_0x520c, 0x3, 0x3);
++				odm_set_bb_reg(dm, R_0x520c, BIT(28), 0x1);
++				odm_set_bb_reg(dm, R_0x530c, 0x3, 0x3);
++				odm_set_bb_reg(dm, R_0x530c, BIT(28), 0x1);
++			}
++			#endif
++		} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++			odm_set_bb_reg(dm, R_0xc00, 0xf, 0x7);
++			odm_set_bb_reg(dm, R_0xe00, 0xf, 0x7);
++		} else {
++			odm_set_bb_reg(dm, R_0x88c, 0xf00000, 0x0);
++		}
++	}
++}
++
++u8 phydm_stop_ic_trx(void *dm_void, u8 set_type)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_api_stuc *api = &dm->api_table;
++	u8 i = 0;
++	boolean trx_idle_success = false;
++	u32 dbg_port_value = 0;
++
++	if (set_type == PHYDM_SET) {
++	/*[Stop TRX]---------------------------------------------------------*/
++		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++			for (i = 0; i < 100; i++) {
++				dbg_port_value = odm_get_bb_reg(dm, R_0x2db4,
++								MASKDWORD);
++				/* BB idle */
++				if ((dbg_port_value & 0x1FFEFF3F) == 0 &&
++				    (dbg_port_value & 0xC0010000) ==
++				    0xC0010000) {
++					PHYDM_DBG(dm, ODM_COMP_API,
++						  "Stop trx wait for (%d) times\n",
++						  i);
++
++					trx_idle_success = true;
++					break;
++				}
++			}
++		} else {
++			/*set debug port to 0x0*/
++			if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0x0))
++				return PHYDM_SET_FAIL;
++			for (i = 0; i < 100; i++) {
++				dbg_port_value = phydm_get_bb_dbg_port_val(dm);
++				/* PHYTXON && CCA_all */
++				if (dm->support_ic_type & (ODM_RTL8721D |
++					ODM_RTL8710B | ODM_RTL8710C |
++					ODM_RTL8188F | ODM_RTL8723D)) {
++					if ((dbg_port_value &
++					    (BIT(20) | BIT(15))) == 0) {
++						PHYDM_DBG(dm, ODM_COMP_API,
++							  "Stop trx wait for (%d) times\n",
++							  i);
++
++						trx_idle_success = true;
++						break;
++					}
++				} else {
++					if ((dbg_port_value &
++					    (BIT(17) | BIT(3))) == 0) {
++						PHYDM_DBG(dm, ODM_COMP_API,
++							  "Stop trx wait for (%d) times\n",
++							  i);
++
++						trx_idle_success = true;
++						break;
++					}
++				}
++				ODM_delay_ms(1);
++			}
++			phydm_release_bb_dbg_port(dm);
++		}
++
++		if (trx_idle_success) {
++			api->tx_queue_bitmap = odm_read_1byte(dm, R_0x522);
++
++			/*pause all TX queue*/
++			odm_set_mac_reg(dm, R_0x520, 0xff0000, 0xff);
++
++			if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++				/*disable OFDM RX CCA*/
++				odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff);
++			} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++				/*disable OFDM RX CCA*/
++				odm_set_bb_reg(dm, R_0x838, BIT(1), 1);
++			} else {
++				api->rxiqc_reg1 = odm_read_4byte(dm, R_0xc14);
++				api->rxiqc_reg2 = odm_read_4byte(dm, R_0xc1c);
++				/* [ Set IQK Matrix = 0 ]
++				 * equivalent to [ Turn off CCA]
++				 */
++				odm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0);
++				odm_set_bb_reg(dm, R_0xc1c, MASKDWORD, 0x0);
++			}
++			phydm_dis_cck_trx(dm, PHYDM_SET);
++		} else {
++			return PHYDM_SET_FAIL;
++		}
++
++		return PHYDM_SET_SUCCESS;
++
++	} else { /*@if (set_type == PHYDM_REVERT)*/
++		/*Release all TX queue*/
++		odm_write_1byte(dm, R_0x522, api->tx_queue_bitmap);
++
++		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++			/*@enable OFDM RX CCA*/
++			odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x0);
++		} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++			/*@enable OFDM RX CCA*/
++			odm_set_bb_reg(dm, R_0x838, BIT(1), 0);
++		} else {
++			/* @[Set IQK Matrix = 0] equivalent to [ Turn off CCA]*/
++			odm_write_4byte(dm, R_0xc14, api->rxiqc_reg1);
++			odm_write_4byte(dm, R_0xc1c, api->rxiqc_reg2);
++		}
++		phydm_dis_cck_trx(dm, PHYDM_REVERT);
++		return PHYDM_SET_SUCCESS;
++	}
++}
++
++void phydm_dis_cck_trx(void *dm_void, u8 set_type)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_api_stuc *api = &dm->api_table;
++
++	if (set_type == PHYDM_SET) {
++		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++			api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0x1a04,
++							     0xf0000000);
++			/* @CCK RxIQ weighting = [0,0] */
++			odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
++			/* @disable CCK Tx */
++			odm_set_bb_reg(dm, R_0x1a04, 0xf0000000, 0x0);
++		} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++			api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0xa04,
++							     0xf0000000);
++			/* @disable CCK block */
++			odm_set_bb_reg(dm, R_0x808, BIT(28), 0);
++			/* @disable CCK Tx */
++			odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x0);
++		} else {
++			api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0xa04,
++							     0xf0000000);
++			/* @disable whole CCK block */
++			odm_set_bb_reg(dm, R_0x800, BIT(24), 0);
++			/* @disable CCK Tx */
++			odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x0);
++		}
++	} else if (set_type == PHYDM_REVERT) {
++		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++			/* @CCK RxIQ weighting = [1,1] */
++			odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
++			/* @enable CCK Tx */
++			odm_set_bb_reg(dm, R_0x1a04, 0xf0000000,
++				       api->ccktx_path);
++		} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++			/* @enable CCK block */
++			odm_set_bb_reg(dm, R_0x808, BIT(28), 1);
++			/* @enable CCK Tx */
++			odm_set_bb_reg(dm, R_0xa04, 0xf0000000,
++				       api->ccktx_path);
++		} else {
++			/* @enable whole CCK block */
++			odm_set_bb_reg(dm, R_0x800, BIT(24), 1);
++			/* @enable CCK Tx */
++			odm_set_bb_reg(dm, R_0xa04, 0xf0000000,
++				       api->ccktx_path);
++		}
++	}
++}
++
++void phydm_bw_fixed_enable(void *dm_void, boolean enable)
++{
++#ifdef CONFIG_BW_INDICATION
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	boolean val = (enable == FUNC_ENABLE) ? 1 : 0;
++
++	if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8195B))
++		odm_set_bb_reg(dm, R_0x840, BIT(4), val);
++	else if (dm->support_ic_type & ODM_RTL8822C)
++		odm_set_bb_reg(dm, R_0x878, BIT(28), val);
++#endif
++}
++
++void phydm_bw_fixed_setting(void *dm_void)
++{
++#ifdef CONFIG_BW_INDICATION
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_api_stuc *api = &dm->api_table;
++	u8 bw = *dm->band_width;
++	u32 reg = 0, reg_mask = 0, reg_value = 0;
++
++	if (!(dm->support_ic_type & ODM_DYM_BW_INDICATION_SUPPORT))
++		return;
++
++	if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B |
++	    ODM_RTL8195B)) {
++		reg = R_0x840;
++		reg_mask = 0xf;
++		reg_value = api->pri_ch_idx;
++	} else if (dm->support_ic_type & ODM_RTL8822C) {
++		reg = R_0x878;
++		reg_mask = 0xc0000000;
++		reg_value = 0x0;
++	}
++
++	switch (bw) {
++	case CHANNEL_WIDTH_80:
++		odm_set_bb_reg(dm, reg, reg_mask, reg_value);
++		break;
++	case CHANNEL_WIDTH_40:
++		odm_set_bb_reg(dm, reg, reg_mask, reg_value);
++		break;
++	default:
++		odm_set_bb_reg(dm, reg, reg_mask, 0x0);
++	}
++
++	phydm_bw_fixed_enable(dm, FUNC_ENABLE);
++#endif
++}
++
++void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch)
++{
++#if (RTL8821A_SUPPORT || RTL8881A_SUPPORT)
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (!(dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)))
++		return;
++
++	/*Output Pin Settings*/
++
++	/*select DPDT_P and DPDT_N as output pin*/
++	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
++
++	/*@by WLAN control*/
++	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1);
++
++	/*@DPDT_N = 1b'0*/ /*@DPDT_P = 1b'0*/
++	odm_set_bb_reg(dm, R_0xcb4, 0xFF, 77);
++
++	if (ext_ant_switch == 1) { /*@2b'01*/
++		odm_set_bb_reg(dm, R_0xcb4, (BIT(29) | BIT(28)), 1);
++		PHYDM_DBG(dm, ODM_COMP_API, "8821A ant swh=2b'01\n");
++	} else if (ext_ant_switch == 2) { /*@2b'10*/
++		odm_set_bb_reg(dm, R_0xcb4, BIT(29) | BIT(28), 2);
++		PHYDM_DBG(dm, ODM_COMP_API, "*8821A ant swh=2b'10\n");
++	}
++#endif
++}
++
++void phydm_csi_mask_enable(void *dm_void, u32 enable)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	boolean en = false;
++
++	en = (enable == FUNC_ENABLE) ? true : false;
++
++	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		odm_set_bb_reg(dm, R_0xd2c, BIT(28), en);
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "Enable CSI Mask:  Reg 0xD2C[28] = ((0x%x))\n", en);
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		odm_set_bb_reg(dm, R_0xc0c, BIT(3), en);
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "Enable CSI Mask:  Reg 0xc0c[3] = ((0x%x))\n", en);
++	#endif
++	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		odm_set_bb_reg(dm, R_0x874, BIT(0), en);
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "Enable CSI Mask:  Reg 0x874[0] = ((0x%x))\n", en);
++	}
++}
++
++void phydm_clean_all_csi_mask(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		odm_set_bb_reg(dm, R_0xd40, MASKDWORD, 0);
++		odm_set_bb_reg(dm, R_0xd44, MASKDWORD, 0);
++		odm_set_bb_reg(dm, R_0xd48, MASKDWORD, 0);
++		odm_set_bb_reg(dm, R_0xd4c, MASKDWORD, 0);
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		u8 i = 0, idx_lmt = 0;
++
++		if (dm->support_ic_type &
++		   (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G))
++			idx_lmt = 127;
++		else /*@for IC supporting 80 + 80*/
++			idx_lmt = 255;
++
++		odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3);
++		odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1);
++		for (i = 0; i < idx_lmt; i++) {
++			odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, i);
++			odm_set_bb_reg(dm, R_0x1d94, MASKBYTE0, 0x0);
++		}
++		odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0);
++	#endif
++	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		odm_set_bb_reg(dm, R_0x880, MASKDWORD, 0);
++		odm_set_bb_reg(dm, R_0x884, MASKDWORD, 0);
++		odm_set_bb_reg(dm, R_0x888, MASKDWORD, 0);
++		odm_set_bb_reg(dm, R_0x88c, MASKDWORD, 0);
++		odm_set_bb_reg(dm, R_0x890, MASKDWORD, 0);
++		odm_set_bb_reg(dm, R_0x894, MASKDWORD, 0);
++		odm_set_bb_reg(dm, R_0x898, MASKDWORD, 0);
++		odm_set_bb_reg(dm, R_0x89c, MASKDWORD, 0);
++	}
++}
++
++void phydm_set_csi_mask(void *dm_void, u32 tone_idx_tmp, u8 tone_direction)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 byte_offset = 0, bit_offset = 0;
++	u32 target_reg = 0;
++	u8 reg_tmp_value = 0;
++	u32 tone_num = 64;
++	u32 tone_num_shift = 0;
++	u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0;
++
++	/* @calculate real tone idx*/
++	if ((tone_idx_tmp % 10) >= 5)
++		tone_idx_tmp += 10;
++
++	tone_idx_tmp = (tone_idx_tmp / 10);
++
++	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		tone_num = 64;
++		csi_mask_reg_p = 0xD40;
++		csi_mask_reg_n = 0xD48;
++
++	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		tone_num = 128;
++		csi_mask_reg_p = 0x880;
++		csi_mask_reg_n = 0x890;
++	}
++
++	if (tone_direction == FREQ_POSITIVE) {
++		if (tone_idx_tmp >= (tone_num - 1))
++			tone_idx_tmp = (tone_num - 1);
++
++		byte_offset = (u8)(tone_idx_tmp >> 3);
++		bit_offset = (u8)(tone_idx_tmp & 0x7);
++		target_reg = csi_mask_reg_p + byte_offset;
++
++	} else {
++		tone_num_shift = tone_num;
++
++		if (tone_idx_tmp >= tone_num)
++			tone_idx_tmp = tone_num;
++
++		tone_idx_tmp = tone_num - tone_idx_tmp;
++
++		byte_offset = (u8)(tone_idx_tmp >> 3);
++		bit_offset = (u8)(tone_idx_tmp & 0x7);
++		target_reg = csi_mask_reg_n + byte_offset;
++	}
++
++	reg_tmp_value = odm_read_1byte(dm, target_reg);
++	PHYDM_DBG(dm, ODM_COMP_API,
++		  "Pre Mask tone idx[%d]:  Reg0x%x = ((0x%x))\n",
++		  (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value);
++	reg_tmp_value |= BIT(bit_offset);
++	odm_write_1byte(dm, target_reg, reg_tmp_value);
++	PHYDM_DBG(dm, ODM_COMP_API,
++		  "New Mask tone idx[%d]:  Reg0x%x = ((0x%x))\n",
++		  (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value);
++}
++
++void phydm_set_nbi_reg(void *dm_void, u32 tone_idx_tmp, u32 bw)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	/*tone_idx X 10*/
++	u32 nbi_128[NBI_128TONE] = {25, 55, 85, 115, 135,
++				    155, 185, 205, 225, 245,
++				    265, 285, 305, 335, 355,
++				    375, 395, 415, 435, 455,
++				    485, 505, 525, 555, 585, 615, 635};
++	/*tone_idx X 10*/
++	u32 nbi_256[NBI_256TONE] = {25, 55, 85, 115, 135,
++				    155, 175, 195, 225, 245,
++				    265, 285, 305, 325, 345,
++				    365, 385, 405, 425, 445,
++				    465, 485, 505, 525, 545,
++				    565, 585, 605, 625, 645,
++				    665, 695, 715, 735, 755,
++				    775, 795, 815, 835, 855,
++				    875, 895, 915, 935, 955,
++				    975, 995, 1015, 1035, 1055,
++				    1085, 1105, 1125, 1145, 1175,
++				    1195, 1225, 1255, 1275};
++	u32 reg_idx = 0;
++	u32 i;
++	u8 nbi_table_idx = FFT_128_TYPE;
++
++	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		nbi_table_idx = FFT_128_TYPE;
++	} else if (dm->support_ic_type & ODM_IC_11AC_1_SERIES) {
++		nbi_table_idx = FFT_256_TYPE;
++	} else if (dm->support_ic_type & ODM_IC_11AC_2_SERIES) {
++		if (bw == 80)
++			nbi_table_idx = FFT_256_TYPE;
++		else /*@20M, 40M*/
++			nbi_table_idx = FFT_128_TYPE;
++	}
++
++	if (nbi_table_idx == FFT_128_TYPE) {
++		for (i = 0; i < NBI_128TONE; i++) {
++			if (tone_idx_tmp < nbi_128[i]) {
++				reg_idx = i + 1;
++				break;
++			}
++		}
++
++	} else if (nbi_table_idx == FFT_256_TYPE) {
++		for (i = 0; i < NBI_256TONE; i++) {
++			if (tone_idx_tmp < nbi_256[i]) {
++				reg_idx = i + 1;
++				break;
++			}
++		}
++	}
++
++	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		odm_set_bb_reg(dm, R_0xc40, 0x1f000000, reg_idx);
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "Set tone idx:  Reg0xC40[28:24] = ((0x%x))\n",
++			  reg_idx);
++	} else {
++		odm_set_bb_reg(dm, R_0x87c, 0xfc000, reg_idx);
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "Set tone idx: Reg0x87C[19:14] = ((0x%x))\n",
++			  reg_idx);
++	}
++}
++
++void phydm_nbi_enable(void *dm_void, u32 enable)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 val = 0;
++
++	val = (enable == FUNC_ENABLE) ? 1 : 0;
++
++	PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI=%d\n", val);
++
++	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		if (dm->support_ic_type & (ODM_RTL8192F | ODM_RTL8197F)) {
++			val = (enable == FUNC_ENABLE) ? 0xf : 0;
++			odm_set_bb_reg(dm, R_0xc50, 0xf000000, val);
++		} else {
++			odm_set_bb_reg(dm, R_0xc40, BIT(9), val);
++		}
++	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C |
++		    ODM_RTL8195B)) {
++			odm_set_bb_reg(dm, R_0x87c, BIT(13), val);
++			odm_set_bb_reg(dm, R_0xc20, BIT(28), val);
++			if (dm->rf_type > RF_1T1R)
++				odm_set_bb_reg(dm, R_0xe20, BIT(28), val);
++		} else {
++			odm_set_bb_reg(dm, R_0x87c, BIT(13), val);
++		}
++	}
++}
++
++u8 phydm_find_fc(void *dm_void, u32 channel, u32 bw, u32 second_ch, u32 *fc_in)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 fc = *fc_in;
++	u32 start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100,
++						  108, 116, 124, 132, 140,
++						  149, 157, 165, 173};
++	u32 start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132,
++						  149, 165};
++	u32 *start_ch = &start_ch_per_40m[0];
++	u32 num_start_channel = NUM_START_CH_40M;
++	u32 channel_offset = 0;
++	u32 i;
++
++	/*@2.4G*/
++	if (channel <= 14 && channel > 0) {
++		if (bw == 80)
++			return PHYDM_SET_FAIL;
++
++		fc = 2412 + (channel - 1) * 5;
++
++		if (bw == 40 && second_ch == PHYDM_ABOVE) {
++			if (channel >= 10) {
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
++					  channel, second_ch);
++				return PHYDM_SET_FAIL;
++			}
++			fc += 10;
++		} else if (bw == 40 && (second_ch == PHYDM_BELOW)) {
++			if (channel <= 2) {
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
++					  channel, second_ch);
++				return PHYDM_SET_FAIL;
++			}
++			fc -= 10;
++		}
++	}
++	/*@5G*/
++	else if (channel >= 36 && channel <= 177) {
++		if (bw != 20) {
++			if (bw == 40) {
++				num_start_channel = NUM_START_CH_40M;
++				start_ch = &start_ch_per_40m[0];
++				channel_offset = CH_OFFSET_40M;
++			} else if (bw == 80) {
++				num_start_channel = NUM_START_CH_80M;
++				start_ch = &start_ch_per_80m[0];
++				channel_offset = CH_OFFSET_80M;
++			}
++
++			for (i = 0; i < (num_start_channel - 1); i++) {
++				if (channel < start_ch[i + 1]) {
++					channel = start_ch[i] + channel_offset;
++					break;
++				}
++			}
++			PHYDM_DBG(dm, ODM_COMP_API, "Mod_CH = ((%d))\n",
++				  channel);
++		}
++
++		fc = 5180 + (channel - 36) * 5;
++
++	} else {
++		PHYDM_DBG(dm, ODM_COMP_API, "CH = ((%d)) Error setting\n",
++			  channel);
++		return PHYDM_SET_FAIL;
++	}
++
++	*fc_in = fc;
++
++	return PHYDM_SET_SUCCESS;
++}
++
++u8 phydm_find_intf_distance(void *dm_void, u32 bw, u32 fc, u32 f_interference,
++			    u32 *tone_idx_tmp_in)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 bw_up = 0, bw_low = 0;
++	u32 int_distance = 0;
++	u32 tone_idx_tmp = 0;
++	u8 set_result = PHYDM_SET_NO_NEED;
++
++	bw_up = fc + bw / 2;
++	bw_low = fc - bw / 2;
++
++	PHYDM_DBG(dm, ODM_COMP_API,
++		  "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low,
++		  fc, bw_up, f_interference);
++
++	if (f_interference >= bw_low && f_interference <= bw_up) {
++		int_distance = DIFF_2(fc, f_interference);
++		/*@10*(int_distance /0.3125)*/
++		tone_idx_tmp = (int_distance << 5);
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n",
++			  int_distance, tone_idx_tmp / 10,
++			  tone_idx_tmp % 10);
++		*tone_idx_tmp_in = tone_idx_tmp;
++		set_result = PHYDM_SET_SUCCESS;
++	}
++
++	return set_result;
++}
++
++u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw,
++			  u32 f_intf, u32 sec_ch)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 fc = 2412;
++	u8 direction = FREQ_POSITIVE;
++	u32 tone_idx = 0;
++	u8 set_result = PHYDM_SET_SUCCESS;
++	u8 rpt = 0;
++
++	if (enable == FUNC_DISABLE) {
++		set_result = PHYDM_SET_SUCCESS;
++		phydm_clean_all_csi_mask(dm);
++
++	} else {
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
++			  ch, bw, f_intf,
++			  (((bw == 20) || (ch > 14)) ? "Don't care" :
++			  (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
++
++		/*@calculate fc*/
++		if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
++			set_result = PHYDM_SET_FAIL;
++		} else {
++			/*@calculate interference distance*/
++			rpt = phydm_find_intf_distance(dm, bw, fc, f_intf,
++						       &tone_idx);
++			if (rpt == PHYDM_SET_SUCCESS) {
++				if (f_intf >= fc)
++					direction = FREQ_POSITIVE;
++				else
++					direction = FREQ_NEGATIVE;
++
++				phydm_set_csi_mask(dm, tone_idx, direction);
++				set_result = PHYDM_SET_SUCCESS;
++			} else {
++				set_result = PHYDM_SET_NO_NEED;
++			}
++		}
++	}
++
++	if (set_result == PHYDM_SET_SUCCESS)
++		phydm_csi_mask_enable(dm, enable);
++	else
++		phydm_csi_mask_enable(dm, FUNC_DISABLE);
++
++	return set_result;
++}
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++u8 phydm_find_intf_distance_jgr3(void *dm_void, u32 bw, u32 fc,
++				 u32 f_interference, u32 *tone_idx_tmp_in)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 bw_up = 0, bw_low = 0;
++	u32 int_distance = 0;
++	u32 tone_idx_tmp = 0;
++	u8 set_result = PHYDM_SET_NO_NEED;
++	u8 channel = *dm->channel;
++
++	bw_up = 1000 * (fc + bw / 2);
++	bw_low = 1000 * (fc - bw / 2);
++	fc = 1000 * fc;
++
++	PHYDM_DBG(dm, ODM_COMP_API,
++		  "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low,
++		  fc, bw_up, f_interference);
++
++	if (f_interference >= bw_low && f_interference <= bw_up) {
++		int_distance = DIFF_2(fc, f_interference);
++		/*@10*(int_distance /0.3125)*/
++		if ((dm->support_ic_type & (ODM_RTL8814B)) && channel < 15)
++			tone_idx_tmp = int_distance / 312;
++		else
++			tone_idx_tmp = ((int_distance + 156) / 312);
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "int_distance = ((%d)) , tone_idx_tmp = ((%d))\n",
++			  int_distance, tone_idx_tmp);
++		*tone_idx_tmp_in = tone_idx_tmp;
++		set_result = PHYDM_SET_SUCCESS;
++	}
++
++	return set_result;
++}
++u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw,
++			       u32 f_intf, u32 sec_ch, u8 wgt)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 fc = 2412;
++	u8 direction = FREQ_POSITIVE;
++	u32 tone_idx = 0;
++	u8 set_result = PHYDM_SET_SUCCESS;
++	u8 rpt = 0;
++
++	if (enable == FUNC_DISABLE) {
++		phydm_csi_mask_enable(dm, FUNC_ENABLE);
++		phydm_clean_all_csi_mask(dm);
++		phydm_csi_mask_enable(dm, FUNC_DISABLE);
++		set_result = PHYDM_SET_SUCCESS;
++	} else {
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "[Set CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s)), wgt = ((%d))\n",
++			  ch, bw, f_intf,
++			  (((bw == 20) || (ch > 14)) ? "Don't care" :
++			  (sec_ch == PHYDM_ABOVE) ? "H" : "L"), wgt);
++
++		/*@calculate fc*/
++		if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
++			set_result = PHYDM_SET_FAIL;
++		} else {
++			/*@calculate interference distance*/
++			rpt = phydm_find_intf_distance_jgr3(dm, bw, fc, f_intf,
++							    &tone_idx);
++			if (rpt == PHYDM_SET_SUCCESS) {
++				if (f_intf >= 1000 * fc)
++					direction = FREQ_POSITIVE;
++				else
++					direction = FREQ_NEGATIVE;
++
++				phydm_csi_mask_enable(dm, FUNC_ENABLE);
++				phydm_set_csi_mask_jgr3(dm, tone_idx, direction,
++							wgt);
++				set_result = PHYDM_SET_SUCCESS;
++			} else {
++				set_result = PHYDM_SET_NO_NEED;
++			}
++		}
++		if (!(set_result == PHYDM_SET_SUCCESS))
++			phydm_csi_mask_enable(dm, FUNC_DISABLE);
++	}
++
++	return set_result;
++}
++
++void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
++			     u8 wgt)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 multi_tone_idx_tmp = 0;
++	u32 reg_tmp_value = 0;
++	u32 tone_num = 64;
++	u32 table_addr = 0;
++	u32 addr = 0;
++	u8 rf_bw = 0;
++	u8 value = 0;
++	u8 channel = *dm->channel;
++
++	rf_bw = odm_read_1byte(dm, R_0x9b0);
++	if (((rf_bw & 0xc) >> 2) == 0x2)
++		tone_num = 128; /* @RF80 : tone(-1) at tone_idx=255 */
++	else
++		tone_num = 64; /* @RF20/40 : tone(-1) at tone_idx=127 */
++
++	if (tone_direction == FREQ_POSITIVE) {
++		if (tone_idx_tmp >= (tone_num - 1))
++			tone_idx_tmp = (tone_num - 1);
++	} else {
++		if (tone_idx_tmp >= tone_num)
++			tone_idx_tmp = tone_num;
++
++		tone_idx_tmp = (tone_num << 1) - tone_idx_tmp;
++	}
++	table_addr = tone_idx_tmp >> 1;
++
++	reg_tmp_value = odm_read_4byte(dm, R_0x1d94);
++	PHYDM_DBG(dm, ODM_COMP_API,
++		  "Pre Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
++		  tone_idx_tmp, reg_tmp_value);
++	odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3);
++	odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1);
++
++	if ((dm->support_ic_type & (ODM_RTL8814B)) && channel < 15) {
++		if (tone_idx_tmp % 2 == 1) {
++			if (tone_direction == FREQ_POSITIVE) {
++				/*===Tone 1===*/
++				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
++					       (table_addr & 0xff));
++				value = (BIT(3) | (wgt & 0x7)) << 4;
++				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
++				reg_tmp_value = odm_read_4byte(dm, R_0x1d94);
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "New Mask tone 1 idx[%d]: Reg0x1d94 = ((0x%x))\n",
++					  tone_idx_tmp, reg_tmp_value);
++				/*===Tone 2===*/
++				value = 0;
++				multi_tone_idx_tmp = tone_idx_tmp + 1;
++				table_addr = multi_tone_idx_tmp >> 1;
++				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
++					       (table_addr & 0xff));
++				value = (BIT(3) | (wgt & 0x7));
++				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
++				reg_tmp_value = odm_read_4byte(dm, R_0x1d94);
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "New Mask tone 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
++					  tone_idx_tmp, reg_tmp_value);
++			} else {
++				/*===Tone 1 & 2===*/
++				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
++					       (table_addr & 0xff));
++				value = ((BIT(3) | (wgt & 0x7)) << 4) |
++					(BIT(3) | (wgt & 0x7));
++				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
++				reg_tmp_value = odm_read_4byte(dm, R_0x1d94);
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "New Mask tone 1 & 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
++					  tone_idx_tmp, reg_tmp_value);
++			}
++		} else {
++			if (tone_direction == FREQ_POSITIVE) {
++				/*===Tone 1 & 2===*/
++				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
++					       (table_addr & 0xff));
++				value = ((BIT(3) | (wgt & 0x7)) << 4) |
++					(BIT(3) | (wgt & 0x7));
++				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
++				reg_tmp_value = odm_read_4byte(dm, R_0x1d94);
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "New Mask tone 1 & 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
++					  tone_idx_tmp, reg_tmp_value);
++			} else {
++				/*===Tone 1===*/
++				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
++					       (table_addr & 0xff));
++				value = (BIT(3) | (wgt & 0x7));
++				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
++				reg_tmp_value = odm_read_4byte(dm, R_0x1d94);
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "New Mask tone 1 idx[%d]: Reg0x1d94 = ((0x%x))\n",
++					  tone_idx_tmp, reg_tmp_value);
++
++				/*===Tone 2===*/
++				value = 0;
++				multi_tone_idx_tmp = tone_idx_tmp - 1;
++				table_addr = multi_tone_idx_tmp >> 1;
++				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
++					       (table_addr & 0xff));
++				value = (BIT(3) | (wgt & 0x7)) << 4;
++				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
++				reg_tmp_value = odm_read_4byte(dm, R_0x1d94);
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "New Mask tone 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
++					  tone_idx_tmp, reg_tmp_value);
++			}
++		}
++	} else {
++		odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, (table_addr & 0xff));
++		if (tone_idx_tmp % 2)
++			value = (BIT(3) | (wgt & 0x7)) << 4;
++		else
++			value = BIT(3) | (wgt & 0x7);
++
++		odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
++		reg_tmp_value = odm_read_4byte(dm, R_0x1d94);
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
++			  tone_idx_tmp, reg_tmp_value);
++	}
++	odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0);
++}
++
++void phydm_nbi_reset_jgr3(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	odm_set_bb_reg(dm, R_0x818, BIT(3), 1);
++	odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0);
++	odm_set_bb_reg(dm, R_0x818, BIT(3), 0);
++	odm_set_bb_reg(dm, R_0x818, BIT(11), 0);
++	#if RTL8814B_SUPPORT
++	if (dm->support_ic_type & ODM_RTL8814B) {
++		odm_set_bb_reg(dm, R_0x1944, 0x300, 0x3);
++		odm_set_bb_reg(dm, R_0x4044, 0x300, 0x3);
++		odm_set_bb_reg(dm, R_0x5044, 0x300, 0x3);
++		odm_set_bb_reg(dm, R_0x5144, 0x300, 0x3);
++		odm_set_bb_reg(dm, R_0x810, 0xf, 0x0);
++		odm_set_bb_reg(dm, R_0x810, 0xf0000, 0x0);
++		odm_set_bb_reg(dm, R_0xc24, MASKDWORD, 0x406000ff);
++	}
++	#endif
++}
++
++u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
++			  u32 sec_ch, u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 fc = 2412;
++	u8 direction = FREQ_POSITIVE;
++	u32 tone_idx = 0;
++	u8 set_result = PHYDM_SET_SUCCESS;
++	u8 rpt = 0;
++
++	if (enable == FUNC_DISABLE) {
++		phydm_nbi_reset_jgr3(dm);
++		set_result = PHYDM_SET_SUCCESS;
++	} else {
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
++			  ch, bw, f_intf,
++			  (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) ||
++			  (ch > 14)) ? "Don't care" :
++			  (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
++
++		/*@calculate fc*/
++		if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
++			set_result = PHYDM_SET_FAIL;
++		} else {
++			/*@calculate interference distance*/
++			rpt = phydm_find_intf_distance_jgr3(dm, bw, fc, f_intf,
++							    &tone_idx);
++			if (rpt == PHYDM_SET_SUCCESS) {
++				if (f_intf >= 1000 * fc)
++					direction = FREQ_POSITIVE;
++				else
++					direction = FREQ_NEGATIVE;
++
++				phydm_set_nbi_reg_jgr3(dm, tone_idx, direction,
++						       path);
++				set_result = PHYDM_SET_SUCCESS;
++			} else {
++				set_result = PHYDM_SET_NO_NEED;
++			}
++		}
++	}
++
++	if (set_result == PHYDM_SET_SUCCESS)
++		phydm_nbi_enable_jgr3(dm, enable, path);
++	else
++		phydm_nbi_enable_jgr3(dm, FUNC_DISABLE, path);
++
++	if (dm->support_ic_type & ODM_RTL8814B)
++		odm_set_bb_reg(dm, R_0x1d3c, BIT(19), 0);
++
++	return set_result;
++}
++
++void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
++			    u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 reg_tmp_value = 0;
++	u32 tone_num = 64;
++	u32 addr = 0;
++	u8 rf_bw = 0;
++
++	rf_bw = odm_read_1byte(dm, R_0x9b0);
++	if (((rf_bw & 0xc) >> 2) == 0x2)
++		tone_num = 128; /* RF80 : tone-1 at tone_idx=255 */
++	else
++		tone_num = 64; /* RF20/40 : tone-1 at tone_idx=127 */
++
++	if (tone_direction == FREQ_POSITIVE) {
++		if (tone_idx_tmp >= (tone_num - 1))
++			tone_idx_tmp = (tone_num - 1);
++	} else {
++		if (tone_idx_tmp >= tone_num)
++			tone_idx_tmp = tone_num;
++
++		tone_idx_tmp = (tone_num << 1) - tone_idx_tmp;
++	}
++	/*Mark the tone idx for Packet detection*/
++	#if RTL8814B_SUPPORT
++	if (dm->support_ic_type & ODM_RTL8814B) {
++		odm_set_bb_reg(dm, R_0xc24, 0xff, 0xff);
++		odm_set_bb_reg(dm, R_0xc24, 0xff00, tone_idx_tmp);
++	}
++	#endif
++	switch (path) {
++	case RF_PATH_A:
++		odm_set_bb_reg(dm, R_0x1944, 0x001FF000, tone_idx_tmp);
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "Set tone idx[%d]:PATH-A = ((0x%x))\n",
++			  tone_idx_tmp, tone_idx_tmp);
++		break;
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	case RF_PATH_B:
++		odm_set_bb_reg(dm, R_0x4044, 0x001FF000, tone_idx_tmp);
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "Set tone idx[%d]:PATH-B = ((0x%x))\n",
++			  tone_idx_tmp, tone_idx_tmp);
++		break;
++	#endif
++	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++	case RF_PATH_C:
++		odm_set_bb_reg(dm, R_0x5044, 0x001FF000, tone_idx_tmp);
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "Set tone idx[%d]:PATH-C = ((0x%x))\n",
++			  tone_idx_tmp, tone_idx_tmp);
++		break;
++	#endif
++	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	case RF_PATH_D:
++		odm_set_bb_reg(dm, R_0x5144, 0x001FF000, tone_idx_tmp);
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "Set tone idx[%d]:PATH-D = ((0x%x))\n",
++			  tone_idx_tmp, tone_idx_tmp);
++		break;
++	#endif
++	default:
++		break;
++	}
++}
++
++void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	boolean val = false;
++
++	val = (enable == FUNC_ENABLE) ? true : false;
++
++	PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI=%d\n", val);
++
++	if (dm->support_ic_type & ODM_RTL8814B) {
++		odm_set_bb_reg(dm, R_0x1d3c, BIT(19), val);
++		odm_set_bb_reg(dm, R_0x818, BIT(3), val);
++	} else if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {
++		odm_set_bb_reg(dm, R_0x818, BIT(3), !val);
++	}
++	odm_set_bb_reg(dm, R_0x818, BIT(11), val);
++	odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0xf);
++
++	if (enable == FUNC_ENABLE) {
++		switch (path) {
++		case RF_PATH_A:
++			odm_set_bb_reg(dm, R_0x1940, BIT(31), val);
++			break;
++		#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++		case RF_PATH_B:
++			odm_set_bb_reg(dm, R_0x4040, BIT(31), val);
++			break;
++		#endif
++		#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++		case RF_PATH_C:
++			odm_set_bb_reg(dm, R_0x5040, BIT(31), val);
++			break;
++		#endif
++		#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++		case RF_PATH_D:
++			odm_set_bb_reg(dm, R_0x5140, BIT(31), val);
++			break;
++		#endif
++		default:
++			break;
++		}
++	} else {
++		odm_set_bb_reg(dm, R_0x1940, BIT(31), val);
++		#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++		odm_set_bb_reg(dm, R_0x4040, BIT(31), val);
++		#endif
++		#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++		odm_set_bb_reg(dm, R_0x5040, BIT(31), val);
++		#endif
++		#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++		odm_set_bb_reg(dm, R_0x5140, BIT(31), val);
++		#endif
++		#if RTL8812F_SUPPORT
++		if (dm->support_ic_type & ODM_RTL8812F) {
++			odm_set_bb_reg(dm, R_0x818, BIT(3), val);
++			odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0x0);
++		}
++		#endif
++	}
++}
++
++u8 phydm_phystat_rpt_jgr3(void *dm_void, enum phystat_rpt info,
++			  enum rf_path ant_path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	s8 evm_org, cfo_org, rxsnr_org;
++	u8 i, return_info = 0, tmp_lsb = 0, tmp_msb = 0, tmp_info = 0;
++
++	/* Update the status for each pkt */
++	odm_set_bb_reg(dm, R_0x8c4, 0xfff000, 0x448);
++	odm_set_bb_reg(dm, R_0x8c0, MASKLWORD, 0x4001);
++	/* PHY status Page1 */
++	odm_set_bb_reg(dm, R_0x8c0, 0x3C00000, 0x1);
++	/*choose debug port for phystatus */
++	odm_set_bb_reg(dm, R_0x1c3c, 0xFFF00, 0x380);
++
++	if (info == PHY_PWDB) {
++		/* Choose the report of the diff path */
++		if (ant_path == RF_PATH_A)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1);
++		else if (ant_path == RF_PATH_B)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x2);
++		else if (ant_path == RF_PATH_C)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x3);
++		else if (ant_path == RF_PATH_D)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x4);
++	} else if (info == PHY_EVM) {
++		/* Choose the report of the diff path */
++		if (ant_path == RF_PATH_A)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x10);
++		else if (ant_path == RF_PATH_B)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x11);
++		else if (ant_path == RF_PATH_C)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x12);
++		else if (ant_path == RF_PATH_D)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x13);
++		return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
++	} else if (info == PHY_CFO) {
++		/* Choose the report of the diff path */
++		if (ant_path == RF_PATH_A)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x14);
++		else if (ant_path == RF_PATH_B)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x15);
++		else if (ant_path == RF_PATH_C)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x16);
++		else if (ant_path == RF_PATH_D)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x17);
++		return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
++	} else if (info == PHY_RXSNR) {
++		/* Choose the report of the diff path */
++		if (ant_path == RF_PATH_A)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x18);
++		else if (ant_path == RF_PATH_B)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x19);
++		else if (ant_path == RF_PATH_C)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1a);
++		else if (ant_path == RF_PATH_D)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1b);
++		return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
++	} else if (info == PHY_LGAIN) {
++		/* choose page */
++		odm_set_bb_reg(dm, R_0x8c0, 0x3c00000, 0x2);
++		/* Choose the report of the diff path */
++		if (ant_path == RF_PATH_A) {
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xd);
++			tmp_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3f);
++			return_info = tmp_info;
++		} else if (ant_path == RF_PATH_B) {
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xd);
++			tmp_lsb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xc0);
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xe);
++			tmp_msb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xf);
++			tmp_info |= (tmp_msb << 2) | tmp_lsb;
++			return_info = tmp_info;
++		} else if (ant_path == RF_PATH_C) {
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xe);
++			tmp_lsb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xf0);
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xf);
++			tmp_msb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3);
++			tmp_info |= (tmp_msb << 4) | tmp_lsb;
++			return_info = tmp_info;
++		} else if (ant_path == RF_PATH_D) {
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x10);
++			tmp_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3f);
++			return_info = tmp_info;
++		}
++	} else if (info == PHY_HT_AAGC_GAIN) {
++		/* choose page */
++		odm_set_bb_reg(dm, R_0x8c0, 0x3c00000, 0x2);
++		/* Choose the report of the diff path */
++		if (ant_path == RF_PATH_A)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x12);
++		else if (ant_path == RF_PATH_B)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x13);
++		else if (ant_path == RF_PATH_C)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x14);
++		else if (ant_path == RF_PATH_D)
++			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x15);
++		return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
++	}
++	return return_info;
++}
++
++void phydm_ex_hal8814b_wifi_only_hw_config(void *dm_void)
++{
++	/*BB control*/
++	/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2);*/
++	/*SW control*/
++	/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0xff, 0x77);*/
++	/*antenna mux switch */
++	/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x974, 0x300, 0x3);*/
++
++	/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1990, 0x300, 0x0);*/
++
++	/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x80000, 0x0);*/
++	/*switch to WL side controller and gnt_wl gnt_bt debug signal */
++	/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x70, 0xff000000, 0x0e);*/
++	/*gnt_wl=1 , gnt_bt=0*/
++	/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff,
++	 *			     0x7700);
++	 */
++	/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff,
++	 *			     0xc00f0038);
++	 */
++}
++
++void phydm_user_position_for_sniffer(void *dm_void, u8 user_position)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	/* user position valid */
++	odm_set_bb_reg(dm, R_0xa68, BIT(17), 1);
++	/* Select user seat from pmac */
++	odm_set_bb_reg(dm, R_0xa68, BIT(16), 1);
++	/*user seat*/
++	odm_set_bb_reg(dm, R_0xa68, (BIT(19) | BIT(18)), user_position);
++}
++
++boolean
++phydm_bb_ctrl_txagc_ofst_jgr3(void *dm_void, s8 pw_offset, /*@(unit: dB)*/
++			      u8 add_half_db /*@(+0.5 dB)*/)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	s8 pw_idx = pw_offset * 4; /*@ 7Bit, 0.25dB unit*/
++
++	if (pw_offset < -16 || pw_offset > 15) {
++		pr_debug("[Warning][%s]Ofst error=%d", __func__, pw_offset);
++		return false;
++	}
++
++	if (add_half_db)
++		pw_idx += 2;
++
++	PHYDM_DBG(dm, ODM_COMP_API, "Pw_ofst=0x%x\n", pw_idx);
++
++	odm_set_bb_reg(dm, R_0x18a0, 0x3f, pw_idx);
++
++	if (dm->num_rf_path >= 2)
++		odm_set_bb_reg(dm, R_0x41a0, 0x3f, pw_idx);
++
++	if (dm->num_rf_path >= 3)
++		odm_set_bb_reg(dm, R_0x52a0, 0x3f, pw_idx);
++
++	if (dm->num_rf_path >= 4)
++		odm_set_bb_reg(dm, R_0x53a0, 0x3f, pw_idx);
++
++	return true;
++}
++
++#endif
++u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
++		     u32 sec_ch)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 fc = 2412;
++	u8 direction = FREQ_POSITIVE;
++	u32 tone_idx = 0;
++	u8 set_result = PHYDM_SET_SUCCESS;
++	u8 rpt = 0;
++
++	if (enable == FUNC_DISABLE) {
++		set_result = PHYDM_SET_SUCCESS;
++	} else {
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
++			  ch, bw, f_intf,
++			  (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) ||
++			  (ch > 14)) ? "Don't care" :
++			  (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
++
++		/*@calculate fc*/
++		if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
++			set_result = PHYDM_SET_FAIL;
++		} else {
++			/*@calculate interference distance*/
++			rpt = phydm_find_intf_distance(dm, bw, fc, f_intf,
++						       &tone_idx);
++			if (rpt == PHYDM_SET_SUCCESS) {
++				if (f_intf >= fc)
++					direction = FREQ_POSITIVE;
++				else
++					direction = FREQ_NEGATIVE;
++
++				phydm_set_nbi_reg(dm, tone_idx, bw);
++
++				set_result = PHYDM_SET_SUCCESS;
++			} else {
++				set_result = PHYDM_SET_NO_NEED;
++		}
++	}
++	}
++
++	if (set_result == PHYDM_SET_SUCCESS)
++		phydm_nbi_enable(dm, enable);
++	else
++		phydm_nbi_enable(dm, FUNC_DISABLE);
++
++	return set_result;
++}
++
++void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used, char *output,
++		     u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 val[10] = {0};
++	char help[] = "-h";
++	u8 i = 0, input_idx = 0, idx_lmt = 0;
++	u32 enable = 0; /*@function enable*/
++	u32 ch = 0;
++	u32 bw = 0;
++	u32 f_int = 0; /*@interference frequency*/
++	u32 sec_ch = 0; /*secondary channel*/
++	u8 rpt = 0;
++	u8 path = 0;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		idx_lmt = 6;
++	else
++		idx_lmt = 5;
++	for (i = 0; i < idx_lmt; i++) {
++		if (input[i + 1]) {
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
++			input_idx++;
++		}
++	}
++
++	if (input_idx == 0)
++		return;
++
++	enable = val[0];
++	ch = val[1];
++	bw = val[2];
++	f_int = val[3];
++	sec_ch = val[4];
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	path = (u8)val[5];
++	#endif
++
++	if ((strcmp(input[1], help) == 0)) {
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(khz)} {Scnd_CH(L=1, H=2)} {Path:A~D(0~3)}\n");
++		else
++		#endif
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(khz)} {Scnd_CH(L=1, H=2)}\n");
++		*_used = used;
++		*_out_len = out_len;
++		return;
++	} else if (val[0] == FUNC_ENABLE) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
++			 ch, bw, f_int,
++			 ((sec_ch == PHYDM_DONT_CARE) ||
++			 (bw == 20) || (ch > 14)) ? "Don't care" :
++			 ((sec_ch == PHYDM_ABOVE) ? "H" : "L"));
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++			rpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int,
++						     sec_ch, path);
++		else
++		#endif
++			rpt = phydm_nbi_setting(dm, enable, ch, bw, f_int,
++						sec_ch);
++	} else if (val[0] == FUNC_DISABLE) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[Disable NBI]\n");
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++			rpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int,
++						     sec_ch, path);
++		else
++		#endif
++			rpt = phydm_nbi_setting(dm, enable, ch, bw, f_int,
++						sec_ch);
++	} else {
++		rpt = PHYDM_SET_FAIL;
++	}
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "[NBI set result: %s]\n",
++		 (rpt == PHYDM_SET_SUCCESS) ? "Success" :
++		 ((rpt == PHYDM_SET_NO_NEED) ? "No need" : "Error"));
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used, char *output,
++		     u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 val[10] = {0};
++	char help[] = "-h";
++	u8 i = 0, input_idx = 0, idx_lmt = 0;
++	u32 enable = 0;  /*@function enable*/
++	u32 ch = 0;
++	u32 bw = 0;
++	u32 f_int = 0; /*@interference frequency*/
++	u32 sec_ch = 0;  /*secondary channel*/
++	u8 rpt = 0;
++	u8 wgt = 0;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		idx_lmt = 6;
++	else
++		idx_lmt = 5;
++
++	for (i = 0; i < idx_lmt; i++) {
++		if (input[i + 1]) {
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
++			input_idx++;
++		}
++	}
++
++	if (input_idx == 0)
++		return;
++
++	enable = val[0];
++	ch = val[1];
++	bw = val[2];
++	f_int = val[3];
++	sec_ch = val[4];
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	wgt = (u8)val[5];
++	#endif
++
++	if ((strcmp(input[1], help) == 0)) {
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(KHz)} {Scnd_CH(L=1, H=2)}\n{wgt:(7:3/4),(6~1: 1/2 ~ 1/64),(0:0)}\n");
++		else
++		#endif
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(Mhz)} {Scnd_CH(L=1, H=2)}\n");
++
++		*_used = used;
++		*_out_len = out_len;
++		return;
++
++	} else if (val[0] == FUNC_ENABLE) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
++			 ch, bw, f_int,
++			 (ch > 14) ? "Don't care" :
++			 (((sec_ch == PHYDM_DONT_CARE) ||
++			 (bw == 20) || (ch > 14)) ? "H" : "L"));
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++			rpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw,
++							  f_int, sec_ch, wgt);
++		else
++		#endif
++			rpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int,
++						     sec_ch);
++	} else if (val[0] == FUNC_DISABLE) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[Disable CSI MASK]\n");
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++			rpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw,
++							  f_int, sec_ch, wgt);
++		else
++		#endif
++			rpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int,
++						     sec_ch);
++	} else {
++		rpt = PHYDM_SET_FAIL;
++	}
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "[CSI MASK set result: %s]\n",
++		 (rpt == PHYDM_SET_SUCCESS) ? "Success" :
++		 ((rpt == PHYDM_SET_NO_NEED) ? "No need" : "Error"));
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_stop_ck320(void *dm_void, u8 enable)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 val = enable ? 1 : 0;
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		odm_set_bb_reg(dm, R_0x8b4, BIT(6), val);
++	} else {
++		if (dm->support_ic_type & ODM_IC_N_2SS) /*N-2SS*/
++			odm_set_bb_reg(dm, R_0x87c, BIT(29), val);
++		else /*N-1SS*/
++			odm_set_bb_reg(dm, R_0x87c, BIT(31), val);
++	}
++}
++
++boolean
++phydm_bb_ctrl_txagc_ofst(void *dm_void, s8 pw_offset, /*@(unit: dB)*/
++			 u8 add_half_db /*@(+0.5 dB)*/)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	s8 pw_idx;
++	u8 offset_bit_num = 0;
++
++	if (dm->support_ic_type & N_IC_TX_OFFEST_5_BIT) {
++		/*@ 5Bit, 0.5dB unit*/
++		if (pw_offset < -8 || pw_offset > 7) {
++			pr_debug("[Warning][%s] Ofst=%d", __func__, pw_offset);
++			return false;
++		}
++		offset_bit_num = 5;
++	} else {
++		if (pw_offset < -16 || pw_offset > 15) {
++			pr_debug("[Warning][%s] Ofst=%d", __func__, pw_offset);
++			return false;
++		}
++		if (dm->support_ic_type & N_IC_TX_OFFEST_7_BIT) {
++		/*@ 7Bit, 0.25dB unit*/
++			offset_bit_num = 7;
++		} else {
++		/*@ 6Bit, 0.5dB unit*/
++			offset_bit_num = 6;
++		}
++	}
++
++	pw_idx = (offset_bit_num == 7) ? pw_offset * 4 : pw_offset * 2;
++
++	if (add_half_db)
++		pw_idx = (offset_bit_num == 7) ? pw_idx + 2 : pw_idx + 1;
++
++	PHYDM_DBG(dm, ODM_COMP_API, "Pw_ofst=0x%x\n", pw_idx);
++
++	switch (dm->ic_ip_series) {
++	case PHYDM_IC_AC:
++		odm_set_bb_reg(dm, R_0x8b4, 0x3f, pw_idx); /*6Bit*/
++		break;
++	case PHYDM_IC_N:
++		if (offset_bit_num == 5) {
++			odm_set_bb_reg(dm, R_0x80c, 0x1f00, pw_idx);
++			if (dm->num_rf_path >= 2)
++				odm_set_bb_reg(dm, R_0x80c, 0x3e000, pw_idx);
++		} else if (offset_bit_num == 6) {
++			odm_set_bb_reg(dm, R_0x80c, 0x3f00, pw_idx);
++			if (dm->num_rf_path >= 2)
++				odm_set_bb_reg(dm, R_0x80c, 0xfc000, pw_idx);
++		}  else { /*7Bit*/
++			odm_set_bb_reg(dm, R_0x80c, 0x7f00, pw_idx);
++			if (dm->num_rf_path >= 2)
++				odm_set_bb_reg(dm, R_0x80c, 0x3f8000, pw_idx);
++		}
++		break;
++	}
++	return true;
++}
++
++boolean
++phydm_set_bb_txagc_offset(void *dm_void, s8 pw_offset, /*@(unit: dB)*/
++			  u8 add_half_db /*@(+0.5 dB)*/)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	boolean rpt = false;
++
++	PHYDM_DBG(dm, ODM_COMP_API, "power_offset=%d, add_half_db =%d\n",
++		  pw_offset, add_half_db);
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		rpt = phydm_bb_ctrl_txagc_ofst_jgr3(dm, pw_offset, add_half_db);
++	} else
++#endif
++	{
++		rpt = phydm_bb_ctrl_txagc_ofst(dm, pw_offset, add_half_db);
++	}
++
++	PHYDM_DBG(dm, ODM_COMP_API, "TX AGC Offset set_success=%d", rpt);
++
++	return rpt;
++}
++
++#ifdef PHYDM_COMMON_API_SUPPORT
++void phydm_reset_txagc(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 r_txagc_cck[4] = {R_0x18a0, R_0x41a0, R_0x52a0, R_0x53a0};
++	u32 r_txagc_ofdm[4] = {R_0x18e8, R_0x41e8, R_0x52e8, R_0x53e8};
++	u32 r_txagc_diff = R_0x3a00;
++	u8 i = 0;
++
++	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) {
++		PHYDM_DBG(dm, ODM_COMP_API, "Only for JGR3 ICs!\n");
++		return;
++	}
++
++	for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
++		odm_set_bb_reg(dm, r_txagc_cck[i], 0x7f0000, 0x0);
++		odm_set_bb_reg(dm, r_txagc_ofdm[i], 0x1fc00, 0x0);
++	}
++
++	for (i = 0; i <= ODM_RATEVHTSS4MCS6; i = i + 4)
++		odm_set_bb_reg(dm, r_txagc_diff + i, MASKDWORD, 0x0);
++}
++boolean
++phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path,
++		      boolean is_positive) {
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	boolean ret = false;
++	u32 txagc_cck = 0;
++	u32 txagc_ofdm = 0;
++	u32 r_txagc_ofdm[4] = {R_0x18e8, R_0x41e8, R_0x52e8, R_0x53e8};
++	u32 r_txagc_cck[4] = {R_0x18a0, R_0x41a0, R_0x52a0, R_0x53a0};
++
++	#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
++	if (dm->support_ic_type &
++	   (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)) {
++		if (path > RF_PATH_B) {
++			PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n",
++				  path);
++			return false;
++		}
++		txagc_cck = (u8)odm_get_bb_reg(dm, r_txagc_cck[path],
++						   0x7F0000);
++		txagc_ofdm = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path],
++						    0x1FC00);
++		if (is_positive) {
++			if (((txagc_cck + pwr_offset) > 127) ||
++			    ((txagc_ofdm + pwr_offset) > 127))
++				return false;
++
++			txagc_cck += pwr_offset;
++			txagc_ofdm += pwr_offset;
++		} else {
++			if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm)
++				return false;
++
++			txagc_cck -= pwr_offset;
++			txagc_ofdm -= pwr_offset;
++		}
++		#if (RTL8822C_SUPPORT)
++		ret = config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_cck,
++							 path, PDM_CCK);
++		ret &= config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_ofdm,
++							 path, PDM_OFDM);
++		#endif
++		#if (RTL8812F_SUPPORT)
++		ret = config_phydm_write_txagc_ref_8812f(dm, (u8)txagc_cck,
++							 path, PDM_CCK);
++		ret &= config_phydm_write_txagc_ref_8812f(dm, (u8)txagc_ofdm,
++							 path, PDM_OFDM);
++		#endif
++		#if (RTL8197G_SUPPORT)
++		ret = config_phydm_write_txagc_ref_8197g(dm, (u8)txagc_cck,
++							 path, PDM_CCK);
++		ret &= config_phydm_write_txagc_ref_8197g(dm, (u8)txagc_ofdm,
++							 path, PDM_OFDM);
++		#endif
++		PHYDM_DBG(dm, ODM_PHY_CONFIG,
++			  "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n",
++			  __func__, path, txagc_cck, txagc_ofdm);
++	}
++	#endif
++
++	#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
++	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) {
++		if (path > RF_PATH_D) {
++			PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n",
++				  path);
++			return false;
++		}
++		txagc_cck = (u8)odm_get_bb_reg(dm, r_txagc_cck[path],
++						   0x7F0000);
++		txagc_ofdm = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path],
++						    0x1FC00);
++		if (is_positive) {
++			if (((txagc_cck + pwr_offset) > 127) ||
++			    ((txagc_ofdm + pwr_offset) > 127))
++				return false;
++
++			txagc_cck += pwr_offset;
++			txagc_ofdm += pwr_offset;
++		} else {
++			if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm)
++				return false;
++
++			txagc_cck -= pwr_offset;
++			txagc_ofdm -= pwr_offset;
++		}
++		#if (RTL8198F_SUPPORT)
++		ret = config_phydm_write_txagc_ref_8198f(dm, (u8)txagc_cck,
++							 path, PDM_CCK);
++		ret &= config_phydm_write_txagc_ref_8198f(dm, (u8)txagc_ofdm,
++							 path, PDM_OFDM);
++		#endif
++		#if (RTL8814B_SUPPORT)
++		ret = config_phydm_write_txagc_ref_8814b(dm, (u8)txagc_cck,
++							 path, PDM_CCK);
++		ret &= config_phydm_write_txagc_ref_8814b(dm, (u8)txagc_ofdm,
++							 path, PDM_OFDM);
++		#endif
++		PHYDM_DBG(dm, ODM_PHY_CONFIG,
++			  "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n",
++			  __func__, path, txagc_cck, txagc_ofdm);
++	}
++	#endif
++
++	return ret;
++}
++
++boolean
++phydm_api_set_txagc(void *dm_void, u32 pwr_idx, enum rf_path path,
++		    u8 rate, boolean is_single_rate)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	boolean ret = false;
++	#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT ||\
++	     RTL8814B_SUPPORT || RTL8197G_SUPPORT)
++	u8 base = 0;
++	u8 txagc_tmp = 0;
++	s8 pw_by_rate_tmp = 0;
++	s8 pw_by_rate_new = 0;
++	#endif
++	#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	u8 i = 0;
++	#endif
++
++#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT)
++	if (dm->support_ic_type &
++	    (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)) {
++		if (is_single_rate) {
++			#if (RTL8822B_SUPPORT)
++			if (dm->support_ic_type == ODM_RTL8822B)
++				ret = phydm_write_txagc_1byte_8822b(dm, pwr_idx,
++								    path, rate);
++			#endif
++
++			#if (RTL8821C_SUPPORT)
++			if (dm->support_ic_type == ODM_RTL8821C)
++				ret = phydm_write_txagc_1byte_8821c(dm, pwr_idx,
++								    path, rate);
++			#endif
++
++			#if (RTL8195B_SUPPORT)
++			if (dm->support_ic_type == ODM_RTL8195B)
++				ret = phydm_write_txagc_1byte_8195b(dm, pwr_idx,
++								    path, rate);
++			#endif
++
++			#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++			set_current_tx_agc(dm->priv, path, rate, (u8)pwr_idx);
++			#endif
++
++		} else {
++			#if (RTL8822B_SUPPORT)
++			if (dm->support_ic_type == ODM_RTL8822B)
++				ret = config_phydm_write_txagc_8822b(dm,
++								     pwr_idx,
++								     path,
++								     rate);
++			#endif
++
++			#if (RTL8821C_SUPPORT)
++			if (dm->support_ic_type == ODM_RTL8821C)
++				ret = config_phydm_write_txagc_8821c(dm,
++								     pwr_idx,
++								     path,
++								     rate);
++			#endif
++
++			#if (RTL8195B_SUPPORT)
++			if (dm->support_ic_type == ODM_RTL8195B)
++				ret = config_phydm_write_txagc_8195b(dm,
++								     pwr_idx,
++								     path,
++								     rate);
++			#endif
++
++			#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++			for (i = 0; i < 4; i++)
++				set_current_tx_agc(dm->priv, path, (rate + i),
++						   (u8)pwr_idx);
++			#endif
++		}
++	}
++#endif
++
++#if (RTL8198F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8198F) {
++		if (rate < 0x4)
++			txagc_tmp = config_phydm_read_txagc_8198f(dm, path,
++								  rate,
++								  PDM_CCK);
++		else
++			txagc_tmp = config_phydm_read_txagc_8198f(dm, path,
++								  rate,
++								  PDM_OFDM);
++
++		pw_by_rate_tmp = config_phydm_read_txagc_diff_8198f(dm, rate);
++		base = txagc_tmp -  pw_by_rate_tmp;
++		base = base & 0x7f;
++		if (DIFF_2((pwr_idx & 0x7f), base) > 64 || pwr_idx > 127)
++			return false;
++
++		pw_by_rate_new = (s8)(pwr_idx - base);
++		ret = phydm_write_txagc_1byte_8198f(dm, pw_by_rate_new, rate);
++		PHYDM_DBG(dm, ODM_PHY_CONFIG,
++			  "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
++			  __func__, path, rate, base, pw_by_rate_new);
++	}
++#endif
++
++#if (RTL8822C_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8822C) {
++		if (rate < 0x4)
++			txagc_tmp = config_phydm_read_txagc_8822c(dm, path,
++								  rate,
++								  PDM_CCK);
++		else
++			txagc_tmp = config_phydm_read_txagc_8822c(dm, path,
++								  rate,
++								  PDM_OFDM);
++
++		pw_by_rate_tmp = config_phydm_read_txagc_diff_8822c(dm, rate);
++		base = txagc_tmp - pw_by_rate_tmp;
++		base = base & 0x7f;
++		if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
++			return false;
++
++		pw_by_rate_new = (s8)(pwr_idx - base);
++		ret = phydm_write_txagc_1byte_8822c(dm, pw_by_rate_new, rate);
++		PHYDM_DBG(dm, ODM_PHY_CONFIG,
++			  "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
++			  __func__, path, rate, base, pw_by_rate_new);
++	}
++#endif
++
++#if (RTL8814B_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8814B) {
++		if (rate < 0x4)
++			txagc_tmp = config_phydm_read_txagc_8814b(dm, path,
++								  rate,
++								  PDM_CCK);
++		else
++			txagc_tmp = config_phydm_read_txagc_8814b(dm, path,
++								  rate,
++								  PDM_OFDM);
++
++		pw_by_rate_tmp = config_phydm_read_txagc_diff_8814b(dm, rate);
++		base = txagc_tmp -  pw_by_rate_tmp;
++		base = base & 0x7f;
++		if (DIFF_2((pwr_idx & 0x7f), base) > 64)
++			return false;
++
++		pw_by_rate_new = (s8)(pwr_idx - base);
++		ret = phydm_write_txagc_1byte_8814b(dm, pw_by_rate_new, rate);
++		PHYDM_DBG(dm, ODM_PHY_CONFIG,
++			  "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
++			  __func__, path, rate, base, pw_by_rate_new);
++	}
++#endif
++
++#if (RTL8812F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8812F) {
++		if (rate < 0x4)
++			txagc_tmp = config_phydm_read_txagc_8812f(dm, path,
++								  rate,
++								  PDM_CCK);
++		else
++			txagc_tmp = config_phydm_read_txagc_8812f(dm, path,
++								  rate,
++								  PDM_OFDM);
++
++		pw_by_rate_tmp = config_phydm_read_txagc_diff_8812f(dm, rate);
++		base = txagc_tmp - pw_by_rate_tmp;
++		base = base & 0x7f;
++		if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
++			return false;
++
++		pw_by_rate_new = (s8)(pwr_idx - base);
++		ret = phydm_write_txagc_1byte_8812f(dm, pw_by_rate_new, rate);
++		PHYDM_DBG(dm, ODM_PHY_CONFIG,
++			  "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
++			  __func__, path, rate, base, pw_by_rate_new);
++	}
++#endif
++
++#if (RTL8197G_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8197G) {
++		if (rate < 0x4)
++			txagc_tmp = config_phydm_read_txagc_8197g(dm, path,
++								  rate,
++								  PDM_CCK);
++		else
++			txagc_tmp = config_phydm_read_txagc_8197g(dm, path,
++								  rate,
++								  PDM_OFDM);
++
++		pw_by_rate_tmp = config_phydm_read_txagc_diff_8197g(dm, rate);
++		base = txagc_tmp - pw_by_rate_tmp;
++		base = base & 0x7f;
++		if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
++			return false;
++
++		pw_by_rate_new = (s8)(pwr_idx - base);
++		ret = phydm_write_txagc_1byte_8197g(dm, pw_by_rate_new, rate);
++		PHYDM_DBG(dm, ODM_PHY_CONFIG,
++			  "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
++			  __func__, path, rate, base, pw_by_rate_new);
++	}
++#endif
++
++#if (RTL8197F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8197F)
++		ret = config_phydm_write_txagc_8197f(dm, pwr_idx, path, rate);
++#endif
++
++#if (RTL8192F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8192F)
++		ret = config_phydm_write_txagc_8192f(dm, pwr_idx, path, rate);
++#endif
++
++#if (RTL8721D_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8721D)
++		ret = config_phydm_write_txagc_8721d(dm, pwr_idx, path, rate);
++#endif
++#if (RTL8710C_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8710C)
++		ret = config_phydm_write_txagc_8710c(dm, pwr_idx, path, rate);
++#endif
++	return ret;
++}
++
++u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 ret = 0;
++
++#if (RTL8822B_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8822B)
++		ret = config_phydm_read_txagc_8822b(dm, path, hw_rate);
++#endif
++
++#if (RTL8197F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8197F)
++		ret = config_phydm_read_txagc_8197f(dm, path, hw_rate);
++#endif
++
++#if (RTL8821C_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8821C)
++		ret = config_phydm_read_txagc_8821c(dm, path, hw_rate);
++#endif
++
++#if (RTL8195B_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8195B)
++		ret = config_phydm_read_txagc_8195b(dm, path, hw_rate);
++#endif
++
++/*@jj add 20170822*/
++#if (RTL8192F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8192F)
++		ret = config_phydm_read_txagc_8192f(dm, path, hw_rate);
++#endif
++
++#if (RTL8198F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8198F) {
++		if (hw_rate < 0x4) {
++			ret = config_phydm_read_txagc_8198f(dm, path, hw_rate,
++							    PDM_CCK);
++		} else {
++			ret = config_phydm_read_txagc_8198f(dm, path, hw_rate,
++							    PDM_OFDM);
++		}
++	}
++#endif
++
++#if (RTL8822C_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8822C) {
++		if (hw_rate < 0x4) {
++			ret = config_phydm_read_txagc_8822c(dm, path, hw_rate,
++							    PDM_CCK);
++		} else {
++			ret = config_phydm_read_txagc_8822c(dm, path, hw_rate,
++							    PDM_OFDM);
++		}
++	}
++#endif
++
++#if (RTL8814B_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8814B) {
++		if (hw_rate < 0x4) {
++			ret = config_phydm_read_txagc_8814b(dm, path, hw_rate,
++							    PDM_CCK);
++		} else {
++			ret = config_phydm_read_txagc_8814b(dm, path, hw_rate,
++							    PDM_OFDM);
++		}
++	}
++#endif
++
++#if (RTL8812F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8812F) {
++		if (hw_rate < 0x4) {
++			ret = config_phydm_read_txagc_8812f(dm, path, hw_rate,
++							    PDM_CCK);
++		} else {
++			ret = config_phydm_read_txagc_8812f(dm, path, hw_rate,
++							    PDM_OFDM);
++		}
++	}
++#endif
++
++#if (RTL8197G_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8197G) {
++		if (hw_rate < 0x4) {
++			ret = config_phydm_read_txagc_8197g(dm, path,
++							    hw_rate,
++							    PDM_CCK);
++		} else {
++			ret = config_phydm_read_txagc_8197g(dm, path,
++							    hw_rate,
++							    PDM_OFDM);
++		}
++	}
++#endif
++
++#if (RTL8721D_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8721D)
++		ret = config_phydm_read_txagc_8721d(dm, path, hw_rate);
++#endif
++#if (RTL8710C_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8710C)
++		ret = config_phydm_read_txagc_8710c(dm, path, hw_rate);
++#endif
++	return ret;
++}
++
++boolean
++phydm_api_switch_bw_channel(void *dm_void, u8 ch, u8 pri_ch,
++			    enum channel_width bw)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	boolean ret = false;
++
++	switch (dm->support_ic_type) {
++#if (RTL8822B_SUPPORT)
++	case ODM_RTL8822B:
++		ret = config_phydm_switch_channel_bw_8822b(dm, ch, pri_ch, bw);
++	break;
++#endif
++
++#if (RTL8197F_SUPPORT)
++	case ODM_RTL8197F:
++		ret = config_phydm_switch_channel_bw_8197f(dm, ch, pri_ch, bw);
++	break;
++#endif
++
++#if (RTL8821C_SUPPORT)
++	case ODM_RTL8821C:
++		ret = config_phydm_switch_channel_bw_8821c(dm, ch, pri_ch, bw);
++	break;
++#endif
++
++#if (RTL8195B_SUPPORT)
++	case ODM_RTL8195B:
++		ret = config_phydm_switch_channel_bw_8195b(dm, ch, pri_ch, bw);
++	break;
++#endif
++
++#if (RTL8192F_SUPPORT)
++	case ODM_RTL8192F:
++		ret = config_phydm_switch_channel_bw_8192f(dm, ch, pri_ch, bw);
++	break;
++#endif
++
++#if (RTL8198F_SUPPORT)
++	case ODM_RTL8198F:
++		ret = config_phydm_switch_channel_bw_8198f(dm, ch, pri_ch, bw);
++	break;
++#endif
++
++#if (RTL8822C_SUPPORT)
++	case ODM_RTL8822C:
++		ret = config_phydm_switch_channel_bw_8822c(dm, ch, pri_ch, bw);
++	break;
++#endif
++
++#if (RTL8814B_SUPPORT)
++	case ODM_RTL8814B:
++		ret = config_phydm_switch_channel_bw_8814b(dm, ch, pri_ch, bw);
++	break;
++#endif
++
++#if (RTL8812F_SUPPORT)
++	case ODM_RTL8812F:
++		ret = config_phydm_switch_channel_bw_8812f(dm, ch, pri_ch, bw);
++	break;
++#endif
++
++#if (RTL8197G_SUPPORT)
++	case ODM_RTL8197G:
++		ret = config_phydm_switch_channel_bw_8197g(dm, ch, pri_ch, bw);
++	break;
++#endif
++
++#if (RTL8721D_SUPPORT)
++	case ODM_RTL8721D:
++		ret = config_phydm_switch_channel_bw_8721d(dm, ch, pri_ch, bw);
++	break;
++#endif
++#if (RTL8710C_SUPPORT)
++	case ODM_RTL8710C:
++		ret = config_phydm_switch_channel_bw_8710c(dm, ch, pri_ch, bw);
++	break;
++#endif
++
++	default:
++		break;
++	}
++	return ret;
++}
++
++boolean
++phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path,
++		   enum bb_path tx_path_ctrl)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	boolean ret = false;
++	boolean is_2tx = false;
++
++	if (tx_path_ctrl == BB_PATH_AB)
++		is_2tx = true;
++
++	switch (dm->support_ic_type) {
++	#if (RTL8822B_SUPPORT)
++	case ODM_RTL8822B:
++		ret = config_phydm_trx_mode_8822b(dm, tx_path, rx_path,
++						  tx_path_ctrl);
++		break;
++	#endif
++
++	#if (RTL8197F_SUPPORT)
++	case ODM_RTL8197F:
++		ret = config_phydm_trx_mode_8197f(dm, tx_path, rx_path, is_2tx);
++		break;
++	#endif
++
++	#if (RTL8192F_SUPPORT)
++	case ODM_RTL8192F:
++		ret = config_phydm_trx_mode_8192f(dm, tx_path, rx_path,
++						  tx_path_ctrl);
++		break;
++	#endif
++
++	#if (RTL8198F_SUPPORT)
++	case ODM_RTL8198F:
++		ret = config_phydm_trx_mode_8198f(dm, tx_path, rx_path, is_2tx);
++		break;
++	#endif
++
++	#if (RTL8814B_SUPPORT)
++	case ODM_RTL8814B:
++		ret = config_phydm_trx_mode_8814b(dm, tx_path, rx_path);
++		break;
++	#endif
++
++	#if (RTL8822C_SUPPORT)
++	case ODM_RTL8822C:
++		ret = config_phydm_trx_mode_8822c(dm, tx_path, rx_path,
++						  tx_path_ctrl);
++		break;
++	#endif
++
++	#if (RTL8812F_SUPPORT)
++	case ODM_RTL8812F:
++		ret = config_phydm_trx_mode_8812f(dm, tx_path, rx_path, is_2tx);
++		break;
++	#endif
++
++	#if (RTL8197G_SUPPORT)
++	case ODM_RTL8197G:
++		ret = config_phydm_trx_mode_8197g(dm, tx_path, rx_path, is_2tx);
++		break;
++	#endif
++
++	#if (RTL8721D_SUPPORT)
++	case ODM_RTL8721D:
++		ret = config_phydm_trx_mode_8721d(dm, tx_path, rx_path, is_2tx);
++		break;
++	#endif
++
++	#if (RTL8710C_SUPPORT)
++	case ODM_RTL8710C:
++		ret = config_phydm_trx_mode_8710c(dm, tx_path, rx_path, is_2tx);
++		break;
++	#endif
++	}
++	return ret;
++}
++#else
++u8 config_phydm_read_txagc_n(void *dm_void, enum rf_path path, u8 hw_rate)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 read_back_data = INVALID_TXAGC_DATA;
++	u32 reg_txagc;
++	u32 reg_mask;
++	/* This function is for 92E/88E etc... */
++	/* @Input need to be HW rate index, not driver rate index!!!! */
++
++	/* @Error handling */
++	if (path > RF_PATH_B || hw_rate > ODM_RATEMCS15) {
++		PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: unsupported path (%d)\n",
++			  __func__, path);
++		return INVALID_TXAGC_DATA;
++	}
++
++	if (path == RF_PATH_A) {
++		switch (hw_rate) {
++		case ODM_RATE1M:
++			reg_txagc = R_0xe08;
++			reg_mask = 0x00007f00;
++			break;
++		case ODM_RATE2M:
++			reg_txagc = R_0x86c;
++			reg_mask = 0x00007f00;
++			break;
++		case ODM_RATE5_5M:
++			reg_txagc = R_0x86c;
++			reg_mask = 0x007f0000;
++			break;
++		case ODM_RATE11M:
++			reg_txagc = R_0x86c;
++			reg_mask = 0x7f000000;
++			break;
++
++		case ODM_RATE6M:
++			reg_txagc = R_0xe00;
++			reg_mask = 0x0000007f;
++			break;
++		case ODM_RATE9M:
++			reg_txagc = R_0xe00;
++			reg_mask = 0x00007f00;
++			break;
++		case ODM_RATE12M:
++			reg_txagc = R_0xe00;
++			reg_mask = 0x007f0000;
++			break;
++		case ODM_RATE18M:
++			reg_txagc = R_0xe00;
++			reg_mask = 0x7f000000;
++			break;
++		case ODM_RATE24M:
++			reg_txagc = R_0xe04;
++			reg_mask = 0x0000007f;
++			break;
++		case ODM_RATE36M:
++			reg_txagc = R_0xe04;
++			reg_mask = 0x00007f00;
++			break;
++		case ODM_RATE48M:
++			reg_txagc = R_0xe04;
++			reg_mask = 0x007f0000;
++			break;
++		case ODM_RATE54M:
++			reg_txagc = R_0xe04;
++			reg_mask = 0x7f000000;
++			break;
++
++		case ODM_RATEMCS0:
++			reg_txagc = R_0xe10;
++			reg_mask = 0x0000007f;
++			break;
++		case ODM_RATEMCS1:
++			reg_txagc = R_0xe10;
++			reg_mask = 0x00007f00;
++			break;
++		case ODM_RATEMCS2:
++			reg_txagc = R_0xe10;
++			reg_mask = 0x007f0000;
++			break;
++		case ODM_RATEMCS3:
++			reg_txagc = R_0xe10;
++			reg_mask = 0x7f000000;
++			break;
++		case ODM_RATEMCS4:
++			reg_txagc = R_0xe14;
++			reg_mask = 0x0000007f;
++			break;
++		case ODM_RATEMCS5:
++			reg_txagc = R_0xe14;
++			reg_mask = 0x00007f00;
++			break;
++		case ODM_RATEMCS6:
++			reg_txagc = R_0xe14;
++			reg_mask = 0x007f0000;
++			break;
++		case ODM_RATEMCS7:
++			reg_txagc = R_0xe14;
++			reg_mask = 0x7f000000;
++			break;
++		case ODM_RATEMCS8:
++			reg_txagc = R_0xe18;
++			reg_mask = 0x0000007f;
++			break;
++		case ODM_RATEMCS9:
++			reg_txagc = R_0xe18;
++			reg_mask = 0x00007f00;
++			break;
++		case ODM_RATEMCS10:
++			reg_txagc = R_0xe18;
++			reg_mask = 0x007f0000;
++			break;
++		case ODM_RATEMCS11:
++			reg_txagc = R_0xe18;
++			reg_mask = 0x7f000000;
++			break;
++		case ODM_RATEMCS12:
++			reg_txagc = R_0xe1c;
++			reg_mask = 0x0000007f;
++			break;
++		case ODM_RATEMCS13:
++			reg_txagc = R_0xe1c;
++			reg_mask = 0x00007f00;
++			break;
++		case ODM_RATEMCS14:
++			reg_txagc = R_0xe1c;
++			reg_mask = 0x007f0000;
++			break;
++		case ODM_RATEMCS15:
++			reg_txagc = R_0xe1c;
++			reg_mask = 0x7f000000;
++			break;
++
++		default:
++			PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid HWrate!\n");
++			break;
++		}
++	} else if (path == RF_PATH_B) {
++		switch (hw_rate) {
++		case ODM_RATE1M:
++			reg_txagc = R_0x838;
++			reg_mask = 0x00007f00;
++			break;
++		case ODM_RATE2M:
++			reg_txagc = R_0x838;
++			reg_mask = 0x007f0000;
++			break;
++		case ODM_RATE5_5M:
++			reg_txagc = R_0x838;
++			reg_mask = 0x7f000000;
++			break;
++		case ODM_RATE11M:
++			reg_txagc = R_0x86c;
++			reg_mask = 0x0000007f;
++			break;
++
++		case ODM_RATE6M:
++			reg_txagc = R_0x830;
++			reg_mask = 0x0000007f;
++			break;
++		case ODM_RATE9M:
++			reg_txagc = R_0x830;
++			reg_mask = 0x00007f00;
++			break;
++		case ODM_RATE12M:
++			reg_txagc = R_0x830;
++			reg_mask = 0x007f0000;
++			break;
++		case ODM_RATE18M:
++			reg_txagc = R_0x830;
++			reg_mask = 0x7f000000;
++			break;
++		case ODM_RATE24M:
++			reg_txagc = R_0x834;
++			reg_mask = 0x0000007f;
++			break;
++		case ODM_RATE36M:
++			reg_txagc = R_0x834;
++			reg_mask = 0x00007f00;
++			break;
++		case ODM_RATE48M:
++			reg_txagc = R_0x834;
++			reg_mask = 0x007f0000;
++			break;
++		case ODM_RATE54M:
++			reg_txagc = R_0x834;
++			reg_mask = 0x7f000000;
++			break;
++
++		case ODM_RATEMCS0:
++			reg_txagc = R_0x83c;
++			reg_mask = 0x0000007f;
++			break;
++		case ODM_RATEMCS1:
++			reg_txagc = R_0x83c;
++			reg_mask = 0x00007f00;
++			break;
++		case ODM_RATEMCS2:
++			reg_txagc = R_0x83c;
++			reg_mask = 0x007f0000;
++			break;
++		case ODM_RATEMCS3:
++			reg_txagc = R_0x83c;
++			reg_mask = 0x7f000000;
++			break;
++		case ODM_RATEMCS4:
++			reg_txagc = R_0x848;
++			reg_mask = 0x0000007f;
++			break;
++		case ODM_RATEMCS5:
++			reg_txagc = R_0x848;
++			reg_mask = 0x00007f00;
++			break;
++		case ODM_RATEMCS6:
++			reg_txagc = R_0x848;
++			reg_mask = 0x007f0000;
++			break;
++		case ODM_RATEMCS7:
++			reg_txagc = R_0x848;
++			reg_mask = 0x7f000000;
++			break;
++
++		case ODM_RATEMCS8:
++			reg_txagc = R_0x84c;
++			reg_mask = 0x0000007f;
++			break;
++		case ODM_RATEMCS9:
++			reg_txagc = R_0x84c;
++			reg_mask = 0x00007f00;
++			break;
++		case ODM_RATEMCS10:
++			reg_txagc = R_0x84c;
++			reg_mask = 0x007f0000;
++			break;
++		case ODM_RATEMCS11:
++			reg_txagc = R_0x84c;
++			reg_mask = 0x7f000000;
++			break;
++		case ODM_RATEMCS12:
++			reg_txagc = R_0x868;
++			reg_mask = 0x0000007f;
++			break;
++		case ODM_RATEMCS13:
++			reg_txagc = R_0x868;
++			reg_mask = 0x00007f00;
++			break;
++		case ODM_RATEMCS14:
++			reg_txagc = R_0x868;
++			reg_mask = 0x007f0000;
++			break;
++		case ODM_RATEMCS15:
++			reg_txagc = R_0x868;
++			reg_mask = 0x7f000000;
++			break;
++
++		default:
++			PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid HWrate!\n");
++			break;
++		}
++	} else {
++		PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid RF path!!\n");
++	}
++	read_back_data = (u8)odm_get_bb_reg(dm, reg_txagc, reg_mask);
++	PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: path-%d rate index 0x%x = 0x%x\n",
++		  __func__, path, hw_rate, read_back_data);
++	return read_back_data;
++}
++#endif
++
++#ifdef CONFIG_MCC_DM
++#ifdef DYN_ANT_WEIGHTING_SUPPORT
++void phydm_set_weighting_cmn(struct dm_struct *dm)
++{
++	PHYDM_DBG(dm, DBG_COMP_MCC, "%s\n", __func__);
++	odm_set_bb_reg(dm, 0xc04, (BIT(18) | BIT(21)), 0x0);
++	odm_set_bb_reg(dm, 0xe04, (BIT(18) | BIT(21)), 0x0);
++}
++
++void phydm_set_weighting_mcc(u8 b_equal_weighting, void *dm_void, u8 port)
++{
++	/*u8 reg_8;*/
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
++	u8	val_0x98e, val_0x98f, val_0x81b;
++	u32 temp_reg;
++
++	PHYDM_DBG(dm, DBG_COMP_MCC, "ant_weighting_mcc, port = %d\n", port);
++	if (b_equal_weighting) {
++		temp_reg = odm_get_bb_reg(dm, 0x98c, 0x00ff0000);
++		val_0x98e = (u8)(temp_reg >> 16) & 0xc0;
++		temp_reg = odm_get_bb_reg(dm, 0x98c, 0xff000000);
++		val_0x98f = (u8)(temp_reg >> 24) & 0x7f;
++		temp_reg = odm_get_bb_reg(dm, 0x818, 0xff000000);
++		val_0x81b = (u8)(temp_reg >> 24) & 0xfd;
++		PHYDM_DBG(dm, DBG_COMP_MCC, "Equal weighting ,rssi_min = %d\n",
++			  dm->rssi_min);
++		/*equal weighting*/
++	} else {
++		val_0x98e = 0x44;
++		val_0x98f = 0x43;
++		temp_reg = odm_get_bb_reg(dm, 0x818, 0xff000000);
++		val_0x81b = (u8)(temp_reg >> 24) | BIT(2);
++		PHYDM_DBG(dm, DBG_COMP_MCC, "AGC weighting ,rssi_min = %d\n",
++			  dm->rssi_min);
++		/*fix sec_min_wgt = 1/2*/
++	}
++	mcc_dm->mcc_reg_id[2] = 0x2;
++	mcc_dm->mcc_dm_reg[2] = 0x98e;
++	mcc_dm->mcc_dm_val[2][port] = val_0x98e;
++
++	mcc_dm->mcc_reg_id[3] = 0x3;
++	mcc_dm->mcc_dm_reg[3] = 0x98f;
++	mcc_dm->mcc_dm_val[3][port] = val_0x98f;
++
++	mcc_dm->mcc_reg_id[4] = 0x4;
++	mcc_dm->mcc_dm_reg[4] = 0x81b;
++	mcc_dm->mcc_dm_val[4][port] = val_0x81b;
++}
++
++void phydm_dyn_ant_dec_mcc(u8 port, u8 rssi_in, void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 rssi_l2h = 43, rssi_h2l = 37;
++
++	if (rssi_in == 0xff)
++		phydm_set_weighting_mcc(FALSE, dm, port);
++	else if (rssi_in >= rssi_l2h)
++		phydm_set_weighting_mcc(TRUE, dm, port);
++	else if (rssi_in <= rssi_h2l)
++		phydm_set_weighting_mcc(FALSE, dm, port);
++}
++
++void phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
++	u8	i;
++
++	phydm_set_weighting_cmn(dm);
++	for (i = 0; i <= 1; i++)
++		phydm_dyn_ant_dec_mcc(i, mcc_dm->mcc_rssi[i], dm);
++}
++#endif /*#ifdef DYN_ANT_WEIGHTING_SUPPORT*/
++
++void phydm_mcc_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
++	u8	i;
++
++	/*PHYDM_DBG(dm, DBG_COMP_MCC, ("MCC init\n"));*/
++	PHYDM_DBG(dm, DBG_COMP_MCC, "MCC init\n");
++	for (i = 0; i < MCC_DM_REG_NUM; i++) {
++		mcc_dm->mcc_reg_id[i] = 0xff;
++		mcc_dm->mcc_dm_reg[i] = 0;
++		mcc_dm->mcc_dm_val[i][0] = 0;
++		mcc_dm->mcc_dm_val[i][1] = 0;
++	}
++	for (i = 0; i < NUM_STA; i++) {
++		mcc_dm->sta_macid[0][i] = 0xff;
++		mcc_dm->sta_macid[1][i] = 0xff;
++	}
++	/* Function init */
++	dm->is_stop_dym_ant_weighting = 0;
++}
++
++u8 phydm_check(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
++	struct cmn_sta_info			*p_entry = NULL;
++	u8	shift = 0;
++	u8	i = 0;
++	u8	j = 0;
++	u8	rssi_min[2] = {0xff, 0xff};
++	u8	sta_num = 8;
++	u8 mcc_macid = 0;
++
++	for (i = 0; i <= 1; i++) {
++		for (j = 0; j < sta_num; j++) {
++			if (mcc_dm->sta_macid[i][j] != 0xff) {
++				mcc_macid = mcc_dm->sta_macid[i][j];
++				p_entry = dm->phydm_sta_info[mcc_macid];
++				if (!p_entry) {
++					PHYDM_DBG(dm, DBG_COMP_MCC,
++						  "PEntry NULL(mac=%d)\n",
++						  mcc_dm->sta_macid[i][j]);
++					return _FAIL;
++				}
++				PHYDM_DBG(dm, DBG_COMP_MCC,
++					  "undec_smoothed_pwdb=%d\n",
++					  p_entry->rssi_stat.rssi);
++				if (p_entry->rssi_stat.rssi < rssi_min[i])
++					rssi_min[i] = p_entry->rssi_stat.rssi;
++			}
++		}
++	}
++	mcc_dm->mcc_rssi[0] = (u8)rssi_min[0];
++	mcc_dm->mcc_rssi[1] = (u8)rssi_min[1];
++	return _SUCCESS;
++}
++
++void phydm_mcc_h2ccmd_rst(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
++	u8 i;
++	u8 regid;
++	u8 h2c_mcc[H2C_MAX_LENGTH];
++
++	/* RST MCC */
++	for (i = 0; i < H2C_MAX_LENGTH; i++)
++		h2c_mcc[i] = 0xff;
++	h2c_mcc[0] = 0x00;
++	odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, h2c_mcc);
++	PHYDM_DBG(dm, DBG_COMP_MCC, "MCC H2C RST\n");
++}
++
++void phydm_mcc_h2ccmd(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
++	u8 i;
++	u8 regid;
++	u8 h2c_mcc[H2C_MAX_LENGTH];
++
++	if (mcc_dm->mcc_rf_ch[0] == 0xff && mcc_dm->mcc_rf_ch[1] == 0xff) {
++		PHYDM_DBG(dm, DBG_COMP_MCC, "MCC channel Error\n");
++		return;
++	}
++	/* Set Channel number */
++	for (i = 0; i < H2C_MAX_LENGTH; i++)
++		h2c_mcc[i] = 0xff;
++	h2c_mcc[0] = 0xe0;
++	h2c_mcc[1] = (u8)(mcc_dm->mcc_rf_ch[0]);
++	h2c_mcc[2] = (u8)(mcc_dm->mcc_rf_ch[0] >> 8);
++	h2c_mcc[3] = (u8)(mcc_dm->mcc_rf_ch[1]);
++	h2c_mcc[4] = (u8)(mcc_dm->mcc_rf_ch[1] >> 8);
++	h2c_mcc[5] = 0xff;
++	h2c_mcc[6] = 0xff;
++	odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, h2c_mcc);
++	PHYDM_DBG(dm, DBG_COMP_MCC,
++		  "MCC H2C SetCH: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
++		  h2c_mcc[0], h2c_mcc[1], h2c_mcc[2], h2c_mcc[3],
++		  h2c_mcc[4], h2c_mcc[5], h2c_mcc[6]);
++
++	/* Set Reg and value*/
++	for (i = 0; i < H2C_MAX_LENGTH; i++)
++		h2c_mcc[i] = 0xff;
++
++	for (i = 0; i < MCC_DM_REG_NUM; i++) {
++		regid = mcc_dm->mcc_reg_id[i];
++		if (regid != 0xff) {
++			h2c_mcc[0] = 0xa0 | (regid & 0x1f);
++			h2c_mcc[1] = (u8)(mcc_dm->mcc_dm_reg[i]);
++			h2c_mcc[2] = (u8)(mcc_dm->mcc_dm_reg[i] >> 8);
++			h2c_mcc[3] = mcc_dm->mcc_dm_val[i][0];
++			h2c_mcc[4] = mcc_dm->mcc_dm_val[i][1];
++			h2c_mcc[5] = 0xff;
++			h2c_mcc[6] = 0xff;
++			odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH,
++					 h2c_mcc);
++			PHYDM_DBG(dm, DBG_COMP_MCC,
++				  "MCC H2C: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
++				  h2c_mcc[0], h2c_mcc[1], h2c_mcc[2],
++				  h2c_mcc[3], h2c_mcc[4],
++				  h2c_mcc[5], h2c_mcc[6]);
++		}
++	}
++}
++
++void phydm_mcc_ctrl(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++
++	PHYDM_DBG(dm, DBG_COMP_MCC, "MCC status: %x\n", mcc_dm->mcc_status);
++	/*MCC stage no change*/
++	if (mcc_dm->mcc_status == mcc_dm->mcc_pre_status)
++		return;
++	/*Not in MCC stage*/
++	if (mcc_dm->mcc_status == 0) {
++		/* Enable normal Ant-weighting */
++		dm->is_stop_dym_ant_weighting = 0;
++		/* Enable normal DIG */
++		odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, 0x20);
++	} else {
++		/* Disable normal Ant-weighting */
++		dm->is_stop_dym_ant_weighting = 1;
++		/* Enable normal DIG */
++		odm_pause_dig(dm, PHYDM_PAUSE_NO_SET, PHYDM_PAUSE_LEVEL_1,
++			      0x20);
++	}
++	if (mcc_dm->mcc_status == 0 && mcc_dm->mcc_pre_status != 0)
++		phydm_mcc_init(dm);
++	mcc_dm->mcc_pre_status = mcc_dm->mcc_status;
++	}
++
++void phydm_fill_mcccmd(void *dm_void, u8 regid, u16 reg_add,
++		       u8 val0, u8 val1)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
++
++	mcc_dm->mcc_reg_id[regid] = regid;
++	mcc_dm->mcc_dm_reg[regid] = reg_add;
++	mcc_dm->mcc_dm_val[regid][0] = val0;
++	mcc_dm->mcc_dm_val[regid][1] = val1;
++}
++
++void phydm_mcc_switch(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
++	s8 ret;
++
++	phydm_mcc_ctrl(dm);
++	if (mcc_dm->mcc_status == 0) {/*Not in MCC stage*/
++		phydm_mcc_h2ccmd_rst(dm);
++		return;
++	}
++	PHYDM_DBG(dm, DBG_COMP_MCC, "MCC switch\n");
++	ret = phydm_check(dm);
++	if (ret == _FAIL) {
++		PHYDM_DBG(dm, DBG_COMP_MCC, "MCC check fail\n");
++		return;
++	}
++	/* Set IGI*/
++	phydm_mcc_igi_cal(dm);
++
++	/* Set Antenna Gain*/
++#if (RTL8822B_SUPPORT == 1)
++	phydm_dynamic_ant_weighting_mcc_8822b(dm);
++#endif
++	/* Set H2C Cmd*/
++	phydm_mcc_h2ccmd(dm);
++}
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void phydm_normal_driver_rx_sniffer(
++	struct dm_struct *dm,
++	u8 *desc,
++	PRT_RFD_STATUS rt_rfd_status,
++	u8 *drv_info,
++	u8 phy_status)
++{
++#if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING))
++	u32 *msg;
++	u16 seq_num;
++
++	if (rt_rfd_status->packet_report_type != NORMAL_RX)
++		return;
++
++	if (!dm->is_linked) {
++		if (rt_rfd_status->is_hw_error)
++			return;
++	}
++
++	if (phy_status == true) {
++		if (dm->rx_pkt_type == type_block_ack ||
++		    dm->rx_pkt_type == type_rts || dm->rx_pkt_type == type_cts)
++			seq_num = 0;
++		else
++			seq_num = rt_rfd_status->seq_num;
++
++		PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
++			    "%04d , %01s, rate=0x%02x, L=%04d , %s , %s",
++			    seq_num,
++			    /*rt_rfd_status->mac_id,*/
++			    (rt_rfd_status->is_crc ? "C" :
++			    rt_rfd_status->is_ampdu ? "A" : "_"),
++			    rt_rfd_status->data_rate,
++			    rt_rfd_status->length,
++			    ((rt_rfd_status->band_width == 0) ? "20M" :
++			    ((rt_rfd_status->band_width == 1) ? "40M" : "80M")),
++			    (rt_rfd_status->is_ldpc ? "LDP" : "BCC"));
++
++		if (dm->rx_pkt_type == type_asoc_req)
++			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_REQ");
++		else if (dm->rx_pkt_type == type_asoc_rsp)
++			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_RSP");
++		else if (dm->rx_pkt_type == type_probe_req)
++			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_REQ");
++		else if (dm->rx_pkt_type == type_probe_rsp)
++			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_RSP");
++		else if (dm->rx_pkt_type == type_deauth)
++			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "DEAUTH");
++		else if (dm->rx_pkt_type == type_beacon)
++			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BEACON");
++		else if (dm->rx_pkt_type == type_block_ack_req)
++			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BA_REQ");
++		else if (dm->rx_pkt_type == type_rts)
++			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__RTS_");
++		else if (dm->rx_pkt_type == type_cts)
++			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__CTS_");
++		else if (dm->rx_pkt_type == type_ack)
++			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__ACK_");
++		else if (dm->rx_pkt_type == type_block_ack)
++			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__BA__");
++		else if (dm->rx_pkt_type == type_data)
++			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "_DATA_");
++		else if (dm->rx_pkt_type == type_data_ack)
++			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "Data_Ack");
++		else if (dm->rx_pkt_type == type_qos_data)
++			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "QoS_Data");
++		else
++			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [0x%x]",
++				    dm->rx_pkt_type);
++
++		PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [RSSI=%d,%d,%d,%d ]",
++			    dm->rssi_a,
++			    dm->rssi_b,
++			    dm->rssi_c,
++			    dm->rssi_d);
++
++		msg = (u32 *)drv_info;
++
++		PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
++			    " , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\n",
++			    msg[6], msg[5], msg[4], msg[3],
++			    msg[2], msg[1], msg[1]);
++	} else {
++		PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
++			    "%04d , %01s, rate=0x%02x, L=%04d , %s , %s\n",
++			    rt_rfd_status->seq_num,
++			    /*rt_rfd_status->mac_id,*/
++			    (rt_rfd_status->is_crc ? "C" :
++			    (rt_rfd_status->is_ampdu) ? "A" : "_"),
++			    rt_rfd_status->data_rate,
++			    rt_rfd_status->length,
++			    ((rt_rfd_status->band_width == 0) ? "20M" :
++			    ((rt_rfd_status->band_width == 1) ? "40M" : "80M")),
++			    (rt_rfd_status->is_ldpc ? "LDP" : "BCC"));
++	}
++
++#endif
++}
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_api.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_api.h
+new file mode 100644
+index 000000000..420cac358
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_api.h
+@@ -0,0 +1,214 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_API_H__
++#define __PHYDM_API_H__
++
++/* 2019.08.02 modify stop trx api for jgr3*/
++#define PHYDM_API_VERSION "2.2"
++
++/* @1 ============================================================
++ * 1  Definition
++ * 1 ============================================================
++ */
++#define N_IC_TX_OFFEST_5_BIT (ODM_RTL8188E | ODM_RTL8192E)
++
++#define N_IC_TX_OFFEST_6_BIT (ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B |\
++			ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8195A |\
++			ODM_RTL8188F)
++
++#define N_IC_TX_OFFEST_7_BIT (ODM_RTL8721D | ODM_RTL8710C)
++
++#define CN_CNT_MAX 10 /*@max condition number threshold*/
++
++#define FUNC_ENABLE 1
++#define FUNC_DISABLE 2
++
++/*@NBI API------------------------------------*/
++#define NBI_128TONE 27 /*register table size*/
++#define NBI_256TONE 59 /*register table size*/
++
++#define NUM_START_CH_80M 7
++#define NUM_START_CH_40M 14
++
++#define CH_OFFSET_40M 2
++#define CH_OFFSET_80M 6
++
++#define FFT_128_TYPE 1
++#define FFT_256_TYPE 2
++
++#define FREQ_POSITIVE 1
++#define FREQ_NEGATIVE 2
++/*@------------------------------------------------*/
++
++enum phystat_rpt {
++	PHY_PWDB = 0,
++	PHY_EVM = 1,
++	PHY_CFO = 2,
++	PHY_RXSNR = 3,
++	PHY_LGAIN = 4,
++	PHY_HT_AAGC_GAIN = 5,
++};
++
++#ifndef PHYDM_COMMON_API_SUPPORT
++#define INVALID_RF_DATA 0xffffffff
++#define INVALID_TXAGC_DATA 0xff
++#endif
++
++/* @1 ============================================================
++ * 1  structure
++ * 1 ============================================================
++ */
++
++struct phydm_api_stuc {
++	u32 rxiqc_reg1; /*N-mode: for pathA REG0xc14*/
++	u32 rxiqc_reg2; /*N-mode: for pathB REG0xc1c*/
++	u8 tx_queue_bitmap; /*REG0x520[23:16]*/
++	u8 ccktx_path;
++	u8 pri_ch_idx;
++};
++
++/* @1 ============================================================
++ * 1  enumeration
++ * 1 ============================================================
++ */
++
++/* @1 ============================================================
++ * 1  function prototype
++ * 1 ============================================================
++ */
++enum channel_width phydm_rxsc_2_bw(void *dm_void, u8 rxsc);
++
++void phydm_reset_bb_hw_cnt(void *dm_void);
++
++void phydm_dynamic_ant_weighting(void *dm_void);
++
++#ifdef DYN_ANT_WEIGHTING_SUPPORT
++void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used,
++			  char *output, u32 *_out_len);
++#endif
++
++void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path);
++
++void phydm_config_ofdm_rx_path(void *dm_void, enum bb_path path);
++
++void phydm_config_cck_rx_path(void *dm_void, enum bb_path path);
++
++void phydm_config_cck_rx_antenna_init(void *dm_void);
++
++void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used,
++			   char *output, u32 *_out_len);
++
++void phydm_config_ofdm_tx_path(void *dm_void, enum bb_path path);
++
++void phydm_config_cck_tx_path(void *dm_void, enum bb_path path);
++
++void phydm_tx_2path(void *dm_void);
++
++void phydm_stop_3_wire(void *dm_void, u8 set_type);
++
++u8 phydm_stop_ic_trx(void *dm_void, u8 set_type);
++
++void phydm_dis_cck_trx(void *dm_void, u8 set_type);
++
++void phydm_bw_fixed_enable(void *dm_void, boolean enable);
++
++void phydm_bw_fixed_setting(void *dm_void);
++
++void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch);
++
++void phydm_nbi_enable(void *dm_void, u32 enable);
++
++u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
++			  u32 sec_ch);
++
++u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
++		     u32 sec_ch);
++
++void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used,
++		     char *output, u32 *_out_len);
++
++void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used,
++		     char *output, u32 *_out_len);
++
++void phydm_stop_ck320(void *dm_void, u8 enable);
++
++boolean
++phydm_set_bb_txagc_offset(void *dm_void, s8 power_offset, u8 add_half_db);
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw,
++			       u32 f_intf, u32 sec_ch, u8 wgt);
++
++void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
++			     u8 wgt);
++
++u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
++			  u32 sec_ch, u8 path);
++
++void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
++			    u8 path);
++
++void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path);
++
++u8 phydm_phystat_rpt_jgr3(void *dm_void, enum phystat_rpt info,
++			  enum rf_path ant_path);
++void phydm_user_position_for_sniffer(void *dm_void, u8 user_position);
++
++#endif
++
++#ifdef PHYDM_COMMON_API_SUPPORT
++void phydm_reset_txagc(void *dm_void);
++
++boolean
++phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path,
++		      boolean is_positive);
++boolean
++phydm_api_set_txagc(void *dm_void, u32 power_index, enum rf_path path,
++		    u8 hw_rate, boolean is_single_rate);
++
++u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate);
++
++boolean
++phydm_api_switch_bw_channel(void *dm_void, u8 central_ch, u8 primary_ch_idx,
++			    enum channel_width bandwidth);
++
++boolean
++phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path,
++		   enum bb_path tx_path_ctrl);
++
++#endif
++
++#ifdef CONFIG_MCC_DM
++#ifdef DYN_ANT_WEIGHTING_SUPPORT
++void phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void);
++#endif /*#ifdef DYN_ANT_WEIGHTING_SUPPORT*/
++void phydm_fill_mcccmd(void *dm_void, u8 regid, u16 reg_add,
++		       u8 val0,	u8 val1);
++u8 phydm_check(void *dm_void);
++void phydm_mcc_init(void *dm_void);
++void phydm_mcc_switch(void *dm_void);
++#endif /*#ifdef CONFIG_MCC_DM*/
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_auto_dbg.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_auto_dbg.c
+new file mode 100644
+index 000000000..203764d7c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_auto_dbg.c
+@@ -0,0 +1,725 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*************************************************************
++ * include files
++ ************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#ifdef PHYDM_AUTO_DEGBUG
++
++void phydm_check_hang_reset(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
++
++	atd_t->dbg_step = 0;
++	atd_t->auto_dbg_type = AUTO_DBG_STOP;
++	phydm_pause_dm_watchdog(dm, PHYDM_RESUME);
++	dm->debug_components &= (~ODM_COMP_API);
++}
++
++void phydm_check_hang_init(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
++
++	atd_t->dbg_step = 0;
++	atd_t->auto_dbg_type = AUTO_DBG_STOP;
++	phydm_pause_dm_watchdog(dm, PHYDM_RESUME);
++}
++
++#if (ODM_IC_11N_SERIES_SUPPORT == 1)
++void phydm_auto_check_hang_engine_n(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
++	struct n_dbgport_803 dbgport_803 = {0};
++	u32 value32_tmp = 0, value32_tmp_2 = 0;
++	u8 i;
++	u32 curr_dbg_port_val[DBGPORT_CHK_NUM] = {0, 0, 0, 0, 0, 0};
++	u16 curr_ofdm_t_cnt;
++	u16 curr_ofdm_r_cnt;
++	u16 curr_cck_t_cnt;
++	u16 curr_cck_r_cnt;
++	u16 curr_ofdm_crc_error_cnt;
++	u16 curr_cck_crc_error_cnt;
++	u16 diff_ofdm_t_cnt;
++	u16 diff_ofdm_r_cnt;
++	u16 diff_cck_t_cnt;
++	u16 diff_cck_r_cnt;
++	u16 diff_ofdm_crc_error_cnt;
++	u16 diff_cck_crc_error_cnt;
++	u8 rf_mode;
++
++	if (atd_t->auto_dbg_type == AUTO_DBG_STOP)
++		return;
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		phydm_check_hang_reset(dm);
++		return;
++	}
++
++	if (atd_t->dbg_step == 0) {
++		pr_debug("dbg_step=0\n\n");
++
++		/*Reset all packet counter*/
++		odm_set_bb_reg(dm, R_0xf14, BIT(16), 1);
++		odm_set_bb_reg(dm, R_0xf14, BIT(16), 0);
++
++	} else if (atd_t->dbg_step == 1) {
++		pr_debug("dbg_step=1\n\n");
++
++		/*Check packet counter Register*/
++		atd_t->ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD);
++		atd_t->ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD);
++		atd_t->ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94,
++								MASKHWORD);
++
++		atd_t->cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD);
++		atd_t->cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD);
++		atd_t->cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84,
++							       0x3fff);
++
++		/*Check Debug Port*/
++		for (i = 0; i < DBGPORT_CHK_NUM; i++) {
++			if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3,
++						  (u32)atd_t->dbg_port_table[i])
++						  ) {
++				atd_t->dbg_port_val[i] =
++					phydm_get_bb_dbg_port_val(dm);
++				phydm_release_bb_dbg_port(dm);
++			}
++		}
++
++	} else if (atd_t->dbg_step == 2) {
++		pr_debug("dbg_step=2\n\n");
++
++		/*Check packet counter Register*/
++		curr_ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD);
++		curr_ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD);
++		curr_ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94,
++							      MASKHWORD);
++
++		curr_cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD);
++		curr_cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD);
++		curr_cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84,
++							     0x3fff);
++
++		/*Check Debug Port*/
++		for (i = 0; i < DBGPORT_CHK_NUM; i++) {
++			if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3,
++						  (u32)atd_t->dbg_port_table[i])
++						  ) {
++				curr_dbg_port_val[i] =
++					phydm_get_bb_dbg_port_val(dm);
++				phydm_release_bb_dbg_port(dm);
++			}
++		}
++
++		/*=== Make check hang decision ===============================*/
++		pr_debug("Check Hang Decision\n\n");
++
++		/* ----- Check RF Register -----------------------------------*/
++		for (i = 0; i < dm->num_rf_path; i++) {
++			rf_mode = (u8)odm_get_rf_reg(dm, i, RF_0x0, 0xf0000);
++			pr_debug("RF0x0[%d] = 0x%x\n", i, rf_mode);
++			if (rf_mode > 3) {
++				pr_debug("Incorrect RF mode\n");
++				pr_debug("ReasonCode:RHN-1\n");
++			}
++		}
++		value32_tmp = odm_get_rf_reg(dm, 0, RF_0xb0, 0xf0000);
++		if (dm->support_ic_type == ODM_RTL8188E) {
++			if (value32_tmp != 0xff8c8) {
++				pr_debug("ReasonCode:RHN-3\n");
++			}
++		}
++		/* ----- Check BB Register ----------------------------------*/
++		/*BB mode table*/
++		value32_tmp = odm_get_bb_reg(dm, R_0x824, 0xe);
++		value32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0xe);
++		pr_debug("BB TX mode table {A, B}= {%d, %d}\n",
++			 value32_tmp, value32_tmp_2);
++
++		if (value32_tmp > 3 || value32_tmp_2 > 3) {
++			pr_debug("ReasonCode:RHN-2\n");
++		}
++
++		value32_tmp = odm_get_bb_reg(dm, R_0x824, 0x700000);
++		value32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0x700000);
++		pr_debug("BB RX mode table {A, B}= {%d, %d}\n", value32_tmp,
++			 value32_tmp_2);
++
++		if (value32_tmp > 3 || value32_tmp_2 > 3) {
++			pr_debug("ReasonCode:RHN-2\n");
++		}
++
++		/*BB HW Block*/
++		value32_tmp = odm_get_bb_reg(dm, R_0x800, MASKDWORD);
++
++		if (!(value32_tmp & BIT(24))) {
++			pr_debug("Reg0x800[24] = 0, CCK BLK is disabled\n");
++			pr_debug("ReasonCode: THN-3\n");
++		}
++
++		if (!(value32_tmp & BIT(25))) {
++			pr_debug("Reg0x800[24] = 0, OFDM BLK is disabled\n");
++			pr_debug("ReasonCode:THN-3\n");
++		}
++
++		/*BB Continue TX*/
++		value32_tmp = odm_get_bb_reg(dm, R_0xd00, 0x70000000);
++		pr_debug("Continue TX=%d\n", value32_tmp);
++		if (value32_tmp != 0) {
++			pr_debug("ReasonCode: THN-4\n");
++		}
++
++		/* ----- Check Packet Counter --------------------------------*/
++		diff_ofdm_t_cnt = curr_ofdm_t_cnt - atd_t->ofdm_t_cnt;
++		diff_ofdm_r_cnt = curr_ofdm_r_cnt - atd_t->ofdm_r_cnt;
++		diff_ofdm_crc_error_cnt = curr_ofdm_crc_error_cnt -
++					  atd_t->ofdm_crc_error_cnt;
++
++		diff_cck_t_cnt = curr_cck_t_cnt - atd_t->cck_t_cnt;
++		diff_cck_r_cnt = curr_cck_r_cnt - atd_t->cck_r_cnt;
++		diff_cck_crc_error_cnt = curr_cck_crc_error_cnt -
++					 atd_t->cck_crc_error_cnt;
++
++		pr_debug("OFDM[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n",
++			 atd_t->ofdm_t_cnt, atd_t->ofdm_r_cnt,
++			 atd_t->ofdm_crc_error_cnt);
++		pr_debug("OFDM[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n",
++			 curr_ofdm_t_cnt, curr_ofdm_r_cnt,
++			 curr_ofdm_crc_error_cnt);
++		pr_debug("OFDM_diff {TX, RX, CRC_error} = {%d, %d, %d}\n",
++			 diff_ofdm_t_cnt, diff_ofdm_r_cnt,
++			 diff_ofdm_crc_error_cnt);
++
++		pr_debug("CCK[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n",
++			 atd_t->cck_t_cnt, atd_t->cck_r_cnt,
++			 atd_t->cck_crc_error_cnt);
++		pr_debug("CCK[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n",
++			 curr_cck_t_cnt, curr_cck_r_cnt,
++			 curr_cck_crc_error_cnt);
++		pr_debug("CCK_diff {TX, RX, CRC_error} = {%d, %d, %d}\n",
++			 diff_cck_t_cnt, diff_cck_r_cnt,
++			 diff_cck_crc_error_cnt);
++
++		/* ----- Check Dbg Port --------------------------------*/
++
++		for (i = 0; i < DBGPORT_CHK_NUM; i++) {
++			pr_debug("Dbg_port=((0x%x))\n",
++				 atd_t->dbg_port_table[i]);
++			pr_debug("Val{pre, curr}={0x%x, 0x%x}\n",
++				 atd_t->dbg_port_val[i], curr_dbg_port_val[i]);
++
++			if (atd_t->dbg_port_table[i] == 0) {
++				if (atd_t->dbg_port_val[i] ==
++				    curr_dbg_port_val[i]) {
++					pr_debug("BB state hang\n");
++					pr_debug("ReasonCode:\n");
++				}
++
++			} else if (atd_t->dbg_port_table[i] == 0x803) {
++				if (atd_t->dbg_port_val[i] ==
++				    curr_dbg_port_val[i]) {
++					/* dbgport_803 =  */
++					/* (struct n_dbgport_803 )   */
++					/* (atd_t->dbg_port_val[i]); */
++					odm_move_memory(dm, &dbgport_803,
++							&atd_t->dbg_port_val[i],
++							sizeof(struct n_dbgport_803));
++					pr_debug("RSTB{BB, GLB, OFDM}={%d, %d,%d}\n",
++						 dbgport_803.bb_rst_b,
++						 dbgport_803.glb_rst_b,
++						 dbgport_803.ofdm_rst_b);
++					pr_debug("{ofdm_tx_en, cck_tx_en, phy_tx_on}={%d, %d, %d}\n",
++						 dbgport_803.ofdm_tx_en,
++						 dbgport_803.cck_tx_en,
++						 dbgport_803.phy_tx_on);
++					pr_debug("CCA_PP{OFDM, CCK}={%d, %d}\n",
++						 dbgport_803.ofdm_cca_pp,
++						 dbgport_803.cck_cca_pp);
++
++					if (dbgport_803.phy_tx_on)
++						pr_debug("Maybe TX Hang\n");
++					else if (dbgport_803.ofdm_cca_pp ||
++						 dbgport_803.cck_cca_pp)
++						pr_debug("Maybe RX Hang\n");
++				}
++
++			} else if (atd_t->dbg_port_table[i] == 0x208) {
++				if ((atd_t->dbg_port_val[i] & BIT(30)) &&
++				    (curr_dbg_port_val[i] & BIT(30))) {
++					pr_debug("EDCCA Pause TX\n");
++					pr_debug("ReasonCode: THN-2\n");
++				}
++
++			} else if (atd_t->dbg_port_table[i] == 0xab0) {
++				/* atd_t->dbg_port_val[i] & 0xffffff == 0 */
++				/* curr_dbg_port_val[i] & 0xffffff == 0 */
++				if (((atd_t->dbg_port_val[i] &
++				      MASK24BITS) == 0) ||
++				    ((curr_dbg_port_val[i] &
++				      MASK24BITS) == 0)) {
++					pr_debug("Wrong L-SIG formate\n");
++					pr_debug("ReasonCode: THN-1\n");
++				}
++			}
++		}
++
++		phydm_check_hang_reset(dm);
++	}
++
++	atd_t->dbg_step++;
++}
++
++void phydm_bb_auto_check_hang_start_n(
++	void *dm_void,
++	u32 *_used,
++	char *output,
++	u32 *_out_len)
++{
++	u32 value32 = 0;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
++		return;
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "PHYDM auto check hang (N-series) is started, Please check the system log\n");
++
++	dm->debug_components |= ODM_COMP_API;
++	atd_t->auto_dbg_type = AUTO_DBG_CHECK_HANG;
++	atd_t->dbg_step = 0;
++
++	phydm_pause_dm_watchdog(dm, PHYDM_PAUSE);
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_dbg_port_dump_n(void *dm_void, u32 *_used, char *output,
++			   u32 *_out_len)
++{
++	u32 value32 = 0;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
++		return;
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "not support now\n");
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++#endif
++
++#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
++void phydm_dbg_port_dump_ac(void *dm_void, u32 *_used, char *output,
++			    u32 *_out_len)
++{
++	u32 value32 = 0;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	if (dm->support_ic_type & ODM_IC_11N_SERIES)
++		return;
++
++	value32 = odm_get_bb_reg(dm, R_0xf80, MASKDWORD);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = 0x%x", "rptreg of sc/bw/ht/...", value32);
++
++	if (dm->support_ic_type & ODM_RTL8822B)
++		odm_set_bb_reg(dm, R_0x198c, BIT(2) | BIT(1) | BIT(0), 7);
++
++	/* dbg_port = basic state machine */
++	{
++		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x000);
++		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "0x8fc", value32);
++
++		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "basic state machine", value32);
++	}
++
++	/* dbg_port = state machine */
++	{
++		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x007);
++		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "0x8fc", value32);
++
++		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "state machine", value32);
++	}
++
++	/* dbg_port = CCA-related*/
++	{
++		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x204);
++		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "0x8fc", value32);
++
++		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "CCA-related", value32);
++	}
++
++	/* dbg_port = edcca/rxd*/
++	{
++		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x278);
++		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "0x8fc", value32);
++
++		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "edcca/rxd", value32);
++	}
++
++	/* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/
++	{
++		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x290);
++		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "0x8fc", value32);
++
++		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x",
++			 "rx_state/mux_state/ADC_MASK_OFDM", value32);
++	}
++
++	/* dbg_port = bf-related*/
++	{
++		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B2);
++		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "0x8fc", value32);
++
++		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "bf-related", value32);
++	}
++
++	/* dbg_port = bf-related*/
++	{
++		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B8);
++		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "0x8fc", value32);
++
++		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "bf-related", value32);
++	}
++
++	/* dbg_port = txon/rxd*/
++	{
++		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA03);
++		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "0x8fc", value32);
++
++		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "txon/rxd", value32);
++	}
++
++	/* dbg_port = l_rate/l_length*/
++	{
++		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0B);
++		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "0x8fc", value32);
++
++		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "l_rate/l_length", value32);
++	}
++
++	/* dbg_port = rxd/rxd_hit*/
++	{
++		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0D);
++		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "0x8fc", value32);
++
++		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "rxd/rxd_hit", value32);
++	}
++
++	/* dbg_port = dis_cca*/
++	{
++		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAA0);
++		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "0x8fc", value32);
++
++		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "dis_cca", value32);
++	}
++
++	/* dbg_port = tx*/
++	{
++		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAB0);
++		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "0x8fc", value32);
++
++		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "tx", value32);
++	}
++
++	/* dbg_port = rx plcp*/
++	{
++		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD0);
++		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "0x8fc", value32);
++
++		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "rx plcp", value32);
++
++		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD1);
++		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "0x8fc", value32);
++
++		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "rx plcp", value32);
++
++		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD2);
++		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "0x8fc", value32);
++
++		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "rx plcp", value32);
++
++		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD3);
++		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "0x8fc", value32);
++
++		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = 0x%x", "rx plcp", value32);
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++#endif
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++void phydm_dbg_port_dump_jgr3(void *dm_void, u32 *_used, char *output,
++			      u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	/*u32 dbg_port_idx_all[3] = {0x000, 0x001, 0x002};*/
++	u32 val = 0;
++	u32 dbg_port_idx = 0;
++	u32 i = 0;
++
++	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
++		return;
++
++	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++		      "%-17s = %s\n", "DbgPort index", "Value");
++
++#if 0
++	/*0x000/0x001/0x002*/
++	for (i = 0; i < 3; i++) {
++		dbg_port_idx = dbg_port_idx_all[i];
++		if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port_idx)) {
++			val = phydm_get_bb_dbg_port_val(dm);
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "0x%-15x = 0x%x\n", dbg_port_idx, val);
++			phydm_release_bb_dbg_port(dm);
++		}
++	}
++#endif
++	for (dbg_port_idx = 0x0; dbg_port_idx <= 0xfff; dbg_port_idx++) {
++		if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port_idx)) {
++			val = phydm_get_bb_dbg_port_val(dm);
++			PDM_VAST_SNPF(out_len, used, output + used,
++				      out_len - used,
++				      "0x%-15x = 0x%x\n", dbg_port_idx, val);
++			phydm_release_bb_dbg_port(dm);
++		}
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++#endif
++
++void phydm_dbg_port_dump(void *dm_void, u32 *_used, char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++		      "------ BB debug port start ------\n");
++
++	switch (dm->ic_ip_series) {
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	case PHYDM_IC_JGR3:
++		phydm_dbg_port_dump_jgr3(dm, &used, output, &out_len);
++		break;
++	#endif
++
++	#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
++	case PHYDM_IC_AC:
++		phydm_dbg_port_dump_ac(dm, &used, output, &out_len);
++		break;
++	#endif
++
++	#if (ODM_IC_11N_SERIES_SUPPORT == 1)
++	case PHYDM_IC_N:
++		phydm_dbg_port_dump_n(dm, &used, output, &out_len);
++		break;
++	#endif
++
++	default:
++		break;
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_auto_dbg_console(
++	void *dm_void,
++	char input[][16],
++	u32 *_used,
++	char *output,
++	u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "hang: {1} {1:Show DbgPort, 2:Auto check hang}\n");
++		return;
++	} else if (var1[0] == 1) {
++		PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
++		if (var1[1] == 1) {
++			phydm_dbg_port_dump(dm, &used, output, &out_len);
++		} else if (var1[1] == 2) {
++			if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++				PDM_SNPF(out_len, used, output + used,
++					 out_len - used, "Not support\n");
++			} else {
++				#if (ODM_IC_11N_SERIES_SUPPORT == 1)
++				phydm_bb_auto_check_hang_start_n(dm, &used,
++								 output,
++								 &out_len);
++				#else
++				PDM_SNPF(out_len, used, output + used,
++					 out_len - used, "Not support\n");
++				#endif
++			}
++		}
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_auto_dbg_engine(void *dm_void)
++{
++	u32 value32 = 0;
++
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
++
++	if (atd_t->auto_dbg_type == AUTO_DBG_STOP)
++		return;
++
++	pr_debug("%s ======>\n", __func__);
++
++	if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_HANG) {
++		if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++			pr_debug("Not Support\n");
++		} else {
++			#if (ODM_IC_11N_SERIES_SUPPORT == 1)
++			phydm_auto_check_hang_engine_n(dm);
++			#else
++			pr_debug("Not Support\n");
++			#endif
++		}
++
++	} else if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_RA) {
++		pr_debug("Not Support\n");
++	}
++}
++
++void phydm_auto_dbg_engine_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
++	u16 dbg_port_table[DBGPORT_CHK_NUM] = {0x0, 0x803, 0x208, 0xab0,
++					       0xab1, 0xab2};
++
++	PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
++
++	odm_move_memory(dm, &atd_t->dbg_port_table[0],
++			&dbg_port_table[0], (DBGPORT_CHK_NUM * 2));
++
++	phydm_check_hang_init(dm);
++}
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_auto_dbg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_auto_dbg.h
+new file mode 100644
+index 000000000..78bde627f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_auto_dbg.h
+@@ -0,0 +1,115 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_AUTO_DBG_H__
++#define __PHYDM_AUTO_DBG_H__
++
++#define AUTO_DBG_VERSION "1.0" /* @2017.05.015  Dino, Add phydm_auto_dbg.h*/
++
++/* @1 ============================================================
++ * 1  Definition
++ * 1 ============================================================
++ */
++
++#define AUTO_CHK_HANG_STEP_MAX 3
++#define DBGPORT_CHK_NUM 6
++
++#ifdef PHYDM_AUTO_DEGBUG
++
++/* @1 ============================================================
++ * 1  enumeration
++ * 1 ============================================================
++ */
++
++enum auto_dbg_type_e {
++	AUTO_DBG_STOP		= 0,
++	AUTO_DBG_CHECK_HANG	= 1,
++	AUTO_DBG_CHECK_RA	= 2,
++	AUTO_DBG_CHECK_DIG	= 3
++};
++
++/* @1 ============================================================
++ * 1  structure
++ * 1 ============================================================
++ */
++
++struct n_dbgport_803 {
++	/*@BYTE 3*/
++	u8 bb_rst_b : 1;
++	u8 glb_rst_b : 1;
++	u8 zero_1bit_1 : 1;
++	u8 ofdm_rst_b : 1;
++	u8 cck_txpe : 1;
++	u8 ofdm_txpe : 1;
++	u8 phy_tx_on : 1;
++	u8 tdrdy : 1;
++	/*@BYTE 2*/
++	u8 txd : 8;
++	/*@BYTE 1*/
++	u8 cck_cca_pp : 1;
++	u8 ofdm_cca_pp : 1;
++	u8 rx_rst : 1;
++	u8 rdrdy : 1;
++	u8 rxd_7_4 : 4;
++	/*@BYTE 0*/
++	u8 rxd_3_0 : 4;
++	u8 ofdm_tx_en : 1;
++	u8 cck_tx_en : 1;
++	u8 zero_1bit_2 : 1;
++	u8 clk_80m : 1;
++};
++
++struct phydm_auto_dbg_struct {
++	enum auto_dbg_type_e auto_dbg_type;
++	u8 dbg_step;
++	u16 dbg_port_table[DBGPORT_CHK_NUM];
++	u32 dbg_port_val[DBGPORT_CHK_NUM];
++	u16 ofdm_t_cnt;
++	u16 ofdm_r_cnt;
++	u16 cck_t_cnt;
++	u16 cck_r_cnt;
++	u16 ofdm_crc_error_cnt;
++	u16 cck_crc_error_cnt;
++};
++
++/* @1 ============================================================
++ * 1  function prototype
++ * 1 ============================================================
++ */
++
++void phydm_dbg_port_dump(void *dm_void, u32 *used, char *output, u32 *out_len);
++
++void phydm_auto_dbg_console(
++	void *dm_void,
++	char input[][16],
++	u32 *_used,
++	char *output,
++	u32 *_out_len);
++
++void phydm_auto_dbg_engine(void *dm_void);
++
++void phydm_auto_dbg_engine_init(void *dm_void);
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_beamforming.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_beamforming.c
+new file mode 100644
+index 000000000..1e21f4020
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_beamforming.c
+@@ -0,0 +1,1986 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	#if WPP_SOFTWARE_TRACE
++		#include "phydm_beamforming.tmh"
++	#endif
++#endif
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++
++void phydm_get_txbf_device_num(
++	void *dm_void,
++	u8 macid)
++{
++#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*@For BDC*/
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
++	struct bf_cmn_info *bf = NULL;
++	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
++	u8 act_as_bfer = 0;
++	u8 act_as_bfee = 0;
++
++	if (is_sta_active(sta)) {
++		bf = &(sta->bf_info);
++	} else {
++		PHYDM_DBG(dm, DBG_TXBF, "[Warning] %s invalid sta_info\n",
++			  __func__);
++		return;
++	}
++
++	if (sta->support_wireless_set & WIRELESS_VHT) {
++		if (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMEE_ENABLE)
++			act_as_bfer = 1;
++
++		if (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMER_ENABLE)
++			act_as_bfee = 1;
++
++	} else if (sta->support_wireless_set & WIRELESS_HT) {
++		if (bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMEE_ENABLE)
++			act_as_bfer = 1;
++
++		if (bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMER_ENABLE)
++			act_as_bfee = 1;
++	}
++
++	if (act_as_bfer))
++		{ /* Our Device act as BFer */
++			dm_bdc_table->w_bfee_client[macid] = true;
++			dm_bdc_table->num_txbfee_client++;
++		}
++	else
++		dm_bdc_table->w_bfee_client[macid] = false;
++
++	if (act_as_bfee))
++		{ /* Our Device act as BFee */
++			dm_bdc_table->w_bfer_client[macid] = true;
++			dm_bdc_table->num_txbfer_client++;
++		}
++	else
++		dm_bdc_table->w_bfer_client[macid] = false;
++
++#endif
++#endif
++}
++
++struct _RT_BEAMFORM_STAINFO *
++phydm_sta_info_init(struct dm_struct *dm, u16 sta_idx, u8 *my_mac_addr)
++{
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	struct _RT_BEAMFORM_STAINFO *entry = &beam_info->beamform_sta_info;
++	struct cmn_sta_info *cmn_sta = dm->phydm_sta_info[sta_idx];
++	//void					*adapter = dm->adapter;
++	ADAPTER * adapter = dm->adapter;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	PMGNT_INFO p_MgntInfo = &((adapter)->MgntInfo);
++	PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_MgntInfo);
++	PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_MgntInfo);
++#endif
++
++	if (!is_sta_active(cmn_sta)) {
++		PHYDM_DBG(dm, DBG_TXBF, "%s => sta_info(mac_id:%d) failed\n",
++			  __func__, sta_idx);
++		#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		rtw_warn_on(1);
++		#endif
++
++		return entry;
++	}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	/*odm_move_memory(dm, (PVOID)(entry->my_mac_addr),*/
++	/*(PVOID)(adapter->CurrentAddress), 6);*/
++	odm_move_memory(dm, entry->my_mac_addr, my_mac_addr, 6);
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	/*odm_move_memory(dm, entry->my_mac_addr,*/
++	/*adapter_mac_addr(sta->padapter), 6);*/
++	odm_move_memory(dm, entry->my_mac_addr, my_mac_addr, 6);
++#endif
++
++	entry->aid = cmn_sta->aid;
++	entry->ra = cmn_sta->mac_addr;
++	entry->mac_id = cmn_sta->mac_id;
++	entry->bw = cmn_sta->bw_mode;
++	entry->cur_beamform = cmn_sta->bf_info.ht_beamform_cap;
++	entry->ht_beamform_cap = cmn_sta->bf_info.ht_beamform_cap;
++
++#if ODM_IC_11AC_SERIES_SUPPORT
++	if (cmn_sta->support_wireless_set & WIRELESS_VHT) {
++		entry->cur_beamform_vht = cmn_sta->bf_info.vht_beamform_cap;
++		entry->vht_beamform_cap = cmn_sta->bf_info.vht_beamform_cap;
++	}
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) /*To Be Removed */
++	entry->ht_beamform_cap = p_ht_info->HtBeamformCap; /*To Be Removed*/
++	entry->vht_beamform_cap = p_vht_info->VhtBeamformCap; /*To Be Removed*/
++
++	if (sta_idx == 0) { /*@client mode*/
++		#if ODM_IC_11AC_SERIES_SUPPORT
++		if (cmn_sta->support_wireless_set & WIRELESS_VHT)
++			entry->cur_beamform_vht = p_vht_info->VhtCurBeamform;
++		#endif
++	}
++#endif
++
++	PHYDM_DBG(dm, DBG_TXBF, "wireless_set = 0x%x, staidx = %d\n",
++		  cmn_sta->support_wireless_set, sta_idx);
++	PHYDM_DBG(dm, DBG_TXBF,
++		  "entry->cur_beamform = 0x%x, entry->cur_beamform_vht = 0x%x\n",
++		  entry->cur_beamform, entry->cur_beamform_vht);
++	return entry;
++}
++void phydm_sta_info_update(
++	struct dm_struct *dm,
++	u16 sta_idx,
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry)
++{
++	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
++
++	if (!is_sta_active(sta))
++		return;
++
++	sta->bf_info.p_aid = beamform_entry->p_aid;
++	sta->bf_info.g_id = beamform_entry->g_id;
++}
++
++struct _RT_BEAMFORMEE_ENTRY *
++phydm_beamforming_get_bfee_entry_by_addr(
++	void *dm_void,
++	u8 *RA,
++	u8 *idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i = 0;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++
++	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
++		if (beam_info->beamformee_entry[i].is_used && (eq_mac_addr(RA, beam_info->beamformee_entry[i].mac_addr))) {
++			*idx = i;
++			return &beam_info->beamformee_entry[i];
++		}
++	}
++
++	return NULL;
++}
++
++struct _RT_BEAMFORMER_ENTRY *
++phydm_beamforming_get_bfer_entry_by_addr(
++	void *dm_void,
++	u8 *TA,
++	u8 *idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i = 0;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++
++	for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) {
++		if (beam_info->beamformer_entry[i].is_used && (eq_mac_addr(TA, beam_info->beamformer_entry[i].mac_addr))) {
++			*idx = i;
++			return &beam_info->beamformer_entry[i];
++		}
++	}
++
++	return NULL;
++}
++
++struct _RT_BEAMFORMEE_ENTRY *
++phydm_beamforming_get_entry_by_mac_id(
++	void *dm_void,
++	u8 mac_id,
++	u8 *idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i = 0;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++
++	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
++		if (beam_info->beamformee_entry[i].is_used && mac_id == beam_info->beamformee_entry[i].mac_id) {
++			*idx = i;
++			return &beam_info->beamformee_entry[i];
++		}
++	}
++
++	return NULL;
++}
++
++enum beamforming_cap
++phydm_beamforming_get_entry_beam_cap_by_mac_id(
++	void *dm_void,
++	u8 mac_id)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i = 0;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	enum beamforming_cap beamform_entry_cap = BEAMFORMING_CAP_NONE;
++
++	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
++		if (beam_info->beamformee_entry[i].is_used && mac_id == beam_info->beamformee_entry[i].mac_id) {
++			beamform_entry_cap = beam_info->beamformee_entry[i].beamform_entry_cap;
++			i = BEAMFORMEE_ENTRY_NUM;
++		}
++	}
++
++	return beamform_entry_cap;
++}
++
++struct _RT_BEAMFORMEE_ENTRY *
++phydm_beamforming_get_free_bfee_entry(
++	void *dm_void,
++	u8 *idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i = 0;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++
++	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
++		if (beam_info->beamformee_entry[i].is_used == false) {
++			*idx = i;
++			return &beam_info->beamformee_entry[i];
++		}
++	}
++	return NULL;
++}
++
++struct _RT_BEAMFORMER_ENTRY *
++phydm_beamforming_get_free_bfer_entry(
++	void *dm_void,
++	u8 *idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i = 0;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s ===>\n", __func__);
++
++	for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) {
++		if (beam_info->beamformer_entry[i].is_used == false) {
++			*idx = i;
++			return &beam_info->beamformer_entry[i];
++		}
++	}
++	return NULL;
++}
++
++/*@
++ * Description: Get the first entry index of MU Beamformee.
++ *
++ * Return value: index of the first MU sta.
++ *
++ * 2015.05.25. Created by tynli.
++ *
++ */
++u8 phydm_beamforming_get_first_mu_bfee_entry_idx(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 idx = 0xFF;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	boolean is_found = false;
++
++	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
++		if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].is_mu_sta) {
++			PHYDM_DBG(dm, DBG_TXBF, "[%s] idx=%d!\n", __func__,
++				  idx);
++			is_found = true;
++			break;
++		}
++	}
++
++	if (!is_found)
++		idx = 0xFF;
++
++	return idx;
++}
++
++/*@Add SU BFee and MU BFee*/
++struct _RT_BEAMFORMEE_ENTRY *
++beamforming_add_bfee_entry(
++	void *dm_void,
++	struct _RT_BEAMFORM_STAINFO *sta,
++	enum beamforming_cap beamform_cap,
++	u8 num_of_sounding_dim,
++	u8 comp_steering_num_of_bfer,
++	u8 *idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMEE_ENTRY *entry = phydm_beamforming_get_free_bfee_entry(dm, idx);
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
++
++	if (entry != NULL) {
++		entry->is_used = true;
++		entry->aid = sta->aid;
++		entry->mac_id = sta->mac_id;
++		entry->sound_bw = sta->bw;
++		odm_move_memory(dm, entry->my_mac_addr, sta->my_mac_addr, 6);
++
++		if (phydm_acting_determine(dm, phydm_acting_as_ap)) {
++			/*@BSSID[44:47] xor BSSID[40:43]*/
++			u16 bssid = ((sta->my_mac_addr[5] & 0xf0) >> 4) ^ (sta->my_mac_addr[5] & 0xf);
++			/*@(dec(A) + dec(B)*32) mod 512*/
++			entry->p_aid = (sta->aid + bssid * 32) & 0x1ff;
++			entry->g_id = 63;
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "%s: BFee P_AID addressed to STA=%d\n",
++				  __func__, entry->p_aid);
++		} else if (phydm_acting_determine(dm, phydm_acting_as_ibss)) {
++			/*@ad hoc mode*/
++			entry->p_aid = 0;
++			entry->g_id = 63;
++			PHYDM_DBG(dm, DBG_TXBF, "%s: BFee P_AID as IBSS=%d\n",
++				  __func__, entry->p_aid);
++		} else {
++			/*@client mode*/
++			entry->p_aid = sta->ra[5];
++			/*@BSSID[39:47]*/
++			entry->p_aid = (entry->p_aid << 1) | (sta->ra[4] >> 7);
++			entry->g_id = 0;
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "%s: BFee P_AID addressed to AP=0x%X\n",
++				  __func__, entry->p_aid);
++		}
++		cp_mac_addr(entry->mac_addr, sta->ra);
++		entry->is_txbf = false;
++		entry->is_sound = false;
++		entry->sound_period = 400;
++		entry->beamform_entry_cap = beamform_cap;
++		entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;
++
++		/*		@entry->log_seq = 0xff;				Move to beamforming_add_bfer_entry*/
++		/*		@entry->log_retry_cnt = 0;			Move to beamforming_add_bfer_entry*/
++		/*		@entry->LogSuccessCnt = 0;		Move to beamforming_add_bfer_entry*/
++
++		entry->log_status_fail_cnt = 0;
++
++		entry->num_of_sounding_dim = num_of_sounding_dim;
++		entry->comp_steering_num_of_bfer = comp_steering_num_of_bfer;
++
++		if (beamform_cap & BEAMFORMER_CAP_VHT_MU) {
++			dm->beamforming_info.beamformee_mu_cnt += 1;
++			entry->is_mu_sta = true;
++			dm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(dm);
++		} else if (beamform_cap & (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) {
++			dm->beamforming_info.beamformee_su_cnt += 1;
++			entry->is_mu_sta = false;
++		}
++
++		return entry;
++	} else
++		return NULL;
++}
++
++/*@Add SU BFee and MU BFer*/
++struct _RT_BEAMFORMER_ENTRY *
++beamforming_add_bfer_entry(
++	void *dm_void,
++	struct _RT_BEAMFORM_STAINFO *sta,
++	enum beamforming_cap beamform_cap,
++	u8 num_of_sounding_dim,
++	u8 *idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMER_ENTRY *entry = phydm_beamforming_get_free_bfer_entry(dm, idx);
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
++
++	if (entry != NULL) {
++		entry->is_used = true;
++		odm_move_memory(dm, entry->my_mac_addr, sta->my_mac_addr, 6);
++		if (phydm_acting_determine(dm, phydm_acting_as_ap)) {
++			/*@BSSID[44:47] xor BSSID[40:43]*/
++			u16 bssid = ((sta->my_mac_addr[5] & 0xf0) >> 4) ^ (sta->my_mac_addr[5] & 0xf);
++
++			entry->p_aid = (sta->aid + bssid * 32) & 0x1ff;
++			entry->g_id = 63;
++			/*@(dec(A) + dec(B)*32) mod 512*/
++		} else if (phydm_acting_determine(dm, phydm_acting_as_ibss)) {
++			entry->p_aid = 0;
++			entry->g_id = 63;
++		} else {
++			entry->p_aid = sta->ra[5];
++			/*@BSSID[39:47]*/
++			entry->p_aid = (entry->p_aid << 1) | (sta->ra[4] >> 7);
++			entry->g_id = 0;
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "%s: P_AID addressed to AP=0x%X\n", __func__,
++				  entry->p_aid);
++		}
++
++		cp_mac_addr(entry->mac_addr, sta->ra);
++		entry->beamform_entry_cap = beamform_cap;
++
++		entry->pre_log_seq = 0; /*@Modified by Jeffery @2015-04-13*/
++		entry->log_seq = 0; /*@Modified by Jeffery @2014-10-29*/
++		entry->log_retry_cnt = 0; /*@Modified by Jeffery @2014-10-29*/
++		entry->log_success = 0; /*@log_success is NOT needed to be accumulated, so  LogSuccessCnt->log_success, 2015-04-13, Jeffery*/
++		entry->clock_reset_times = 0; /*@Modified by Jeffery @2015-04-13*/
++
++		entry->num_of_sounding_dim = num_of_sounding_dim;
++
++		if (beamform_cap & BEAMFORMEE_CAP_VHT_MU) {
++			dm->beamforming_info.beamformer_mu_cnt += 1;
++			entry->is_mu_ap = true;
++			entry->aid = sta->aid;
++		} else if (beamform_cap & (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) {
++			dm->beamforming_info.beamformer_su_cnt += 1;
++			entry->is_mu_ap = false;
++		}
++
++		return entry;
++	} else
++		return NULL;
++}
++
++/* Used for beamforming_start_v1 */
++void phydm_beamforming_ndpa_rate(
++	void *dm_void,
++	enum channel_width BW,
++	u8 rate)
++{
++	u16 ndpa_rate = rate;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
++
++	if (ndpa_rate == 0) {
++		if (dm->rssi_min > 30) /* @link RSSI > 30% */
++			ndpa_rate = ODM_RATE24M;
++		else
++			ndpa_rate = ODM_RATE6M;
++	}
++
++	if (ndpa_rate < ODM_RATEMCS0)
++		BW = (enum channel_width)CHANNEL_WIDTH_20;
++
++	ndpa_rate = (ndpa_rate << 8) | BW;
++	hal_com_txbf_set(dm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate);
++}
++
++/* Used for beamforming_start_sw and  beamforming_start_fw */
++void phydm_beamforming_dym_ndpa_rate(
++	void *dm_void)
++{
++	u16 ndpa_rate = ODM_RATE6M, BW;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	ndpa_rate = ODM_RATE6M;
++	BW = CHANNEL_WIDTH_20;
++
++	ndpa_rate = ndpa_rate << 8 | BW;
++	hal_com_txbf_set(dm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate);
++	PHYDM_DBG(dm, DBG_TXBF, "%s End, NDPA rate = 0x%X\n", __func__,
++		  ndpa_rate);
++}
++
++/*@
++*	SW Sounding : SW Timer unit 1ms
++*				 HW Timer unit (1/32000) s  32k is clock.
++*	FW Sounding : FW Timer unit 10ms
++*/
++void beamforming_dym_period(
++	void *dm_void,
++	u8 status)
++{
++	u8 idx;
++	boolean is_change_period = false;
++	u16 sound_period_sw, sound_period_fw;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;
++
++	struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx];
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	/* @3 TODO  per-client throughput caculation. */
++
++	if ((*dm->current_tx_tp + *dm->current_rx_tp > 2) && (entry->log_status_fail_cnt <= 20 || status)) {
++		sound_period_sw = 40; /* @40ms */
++		sound_period_fw = 40; /* @From  H2C cmd, unit = 10ms */
++	} else {
++		sound_period_sw = 4000; /* @4s */
++		sound_period_fw = 400;
++	}
++	PHYDM_DBG(dm, DBG_TXBF, "[%s]sound_period_sw=%d, sound_period_fw=%d\n",
++		  __func__, sound_period_sw, sound_period_fw);
++
++	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
++		beamform_entry = beam_info->beamformee_entry + idx;
++
++		if (beamform_entry->default_csi_cnt > 20) {
++			/*@Modified by David*/
++			sound_period_sw = 4000;
++			sound_period_fw = 400;
++		}
++
++		PHYDM_DBG(dm, DBG_TXBF, "[%s] period = %d\n", __func__,
++			  sound_period_sw);
++		if ((beamform_entry->beamform_entry_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) == 0)
++			continue;
++
++		if (sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || sound_info->sound_mode == SOUNDING_FW_HT_TIMER) {
++			if (beamform_entry->sound_period != sound_period_fw) {
++				beamform_entry->sound_period = sound_period_fw;
++				is_change_period = true; /*Only FW sounding need to send H2C packet to change sound period. */
++			}
++		} else if (beamform_entry->sound_period != sound_period_sw)
++			beamform_entry->sound_period = sound_period_sw;
++	}
++
++	if (is_change_period)
++		hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx);
++}
++
++boolean
++beamforming_send_ht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	enum channel_width BW,
++	u8 q_idx)
++{
++	boolean ret = true;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (q_idx == BEACON_QUEUE)
++		ret = send_fw_ht_ndpa_packet(dm, RA, BW);
++	else
++		ret = send_sw_ht_ndpa_packet(dm, RA, BW);
++
++	return ret;
++}
++
++boolean
++beamforming_send_vht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	u16 AID,
++	enum channel_width BW,
++	u8 q_idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	boolean ret = true;
++
++	hal_com_txbf_set(dm, TXBF_SET_GET_TX_RATE, NULL);
++
++	if (beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7 && beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9 && !beam_info->snding3ss)
++		PHYDM_DBG(dm, DBG_TXBF, "@%s: 3SS VHT 789 don't sounding\n",
++			  __func__);
++
++	else {
++		if (q_idx == BEACON_QUEUE) /* Send to reserved page => FW NDPA */
++			ret = send_fw_vht_ndpa_packet(dm, RA, AID, BW);
++		else {
++#ifdef SUPPORT_MU_BF
++#if (SUPPORT_MU_BF == 1)
++			beam_info->is_mu_sounding = true;
++			ret = send_sw_vht_mu_ndpa_packet(dm, BW);
++#else
++			beam_info->is_mu_sounding = false;
++			ret = send_sw_vht_ndpa_packet(dm, RA, AID, BW);
++#endif
++#else
++			beam_info->is_mu_sounding = false;
++			ret = send_sw_vht_ndpa_packet(dm, RA, AID, BW);
++#endif
++		}
++	}
++	return ret;
++}
++
++enum beamforming_notify_state
++phydm_beamfomring_is_sounding(
++	void *dm_void,
++	struct _RT_BEAMFORMING_INFO *beam_info,
++	u8 *idx)
++{
++	enum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE;
++	struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i;
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
++
++	/*@if(( Beamforming_GetBeamCap(beam_info) & BEAMFORMER_CAP) == 0)*/
++	/*@is_sounding = BEAMFORMING_NOTIFY_RESET;*/
++	if (beam_oid_info.sound_oid_mode == sounding_stop_all_timer) {
++		is_sounding = BEAMFORMING_NOTIFY_RESET;
++		goto out;
++	}
++
++	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
++		PHYDM_DBG(dm, DBG_TXBF,
++			  "@%s: BFee Entry %d is_used=%d, is_sound=%d\n",
++			  __func__, i, beam_info->beamformee_entry[i].is_used,
++			  beam_info->beamformee_entry[i].is_sound);
++		if (beam_info->beamformee_entry[i].is_used && !beam_info->beamformee_entry[i].is_sound) {
++			PHYDM_DBG(dm, DBG_TXBF, "%s: Add BFee entry %d\n",
++				  __func__, i);
++			*idx = i;
++			if (beam_info->beamformee_entry[i].is_mu_sta)
++				is_sounding = BEAMFORMEE_NOTIFY_ADD_MU;
++			else
++				is_sounding = BEAMFORMEE_NOTIFY_ADD_SU;
++		}
++
++		if (!beam_info->beamformee_entry[i].is_used && beam_info->beamformee_entry[i].is_sound) {
++			PHYDM_DBG(dm, DBG_TXBF, "%s: Delete BFee entry %d\n",
++				  __func__, i);
++			*idx = i;
++			if (beam_info->beamformee_entry[i].is_mu_sta)
++				is_sounding = BEAMFORMEE_NOTIFY_DELETE_MU;
++			else
++				is_sounding = BEAMFORMEE_NOTIFY_DELETE_SU;
++		}
++	}
++
++out:
++	PHYDM_DBG(dm, DBG_TXBF, "%s End, is_sounding = %d\n", __func__,
++		  is_sounding);
++	return is_sounding;
++}
++
++/* This function is unused */
++u8 phydm_beamforming_sounding_idx(
++	void *dm_void,
++	struct _RT_BEAMFORMING_INFO *beam_info)
++{
++	u8 idx = 0;
++	struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
++
++	if (beam_oid_info.sound_oid_mode == SOUNDING_SW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_SW_VHT_TIMER ||
++	    beam_oid_info.sound_oid_mode == SOUNDING_HW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_VHT_TIMER)
++		idx = beam_oid_info.sound_oid_idx;
++	else {
++		u8 i;
++		for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
++			if (beam_info->beamformee_entry[i].is_used && !beam_info->beamformee_entry[i].is_sound) {
++				idx = i;
++				break;
++			}
++		}
++	}
++
++	return idx;
++}
++
++enum sounding_mode
++phydm_beamforming_sounding_mode(
++	void *dm_void,
++	struct _RT_BEAMFORMING_INFO *beam_info,
++	u8 idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 support_interface = dm->support_interface;
++
++	struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx];
++	struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;
++	enum sounding_mode mode = beam_oid_info.sound_oid_mode;
++
++	if (beam_oid_info.sound_oid_mode == SOUNDING_SW_VHT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_VHT_TIMER) {
++		if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
++			mode = beam_oid_info.sound_oid_mode;
++		else
++			mode = sounding_stop_all_timer;
++	} else if (beam_oid_info.sound_oid_mode == SOUNDING_SW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_HT_TIMER) {
++		if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)
++			mode = beam_oid_info.sound_oid_mode;
++		else
++			mode = sounding_stop_all_timer;
++	} else if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) {
++		if (support_interface == ODM_ITRF_USB && !(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)))
++			mode = SOUNDING_FW_VHT_TIMER;
++		else
++			mode = SOUNDING_SW_VHT_TIMER;
++	} else if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) {
++		if (support_interface == ODM_ITRF_USB && !(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)))
++			mode = SOUNDING_FW_HT_TIMER;
++		else
++			mode = SOUNDING_SW_HT_TIMER;
++	} else
++		mode = sounding_stop_all_timer;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] support_interface=%d, mode=%d\n",
++		  __func__, support_interface, mode);
++
++	return mode;
++}
++
++u16 phydm_beamforming_sounding_time(
++	void *dm_void,
++	struct _RT_BEAMFORMING_INFO *beam_info,
++	enum sounding_mode mode,
++	u8 idx)
++{
++	u16 sounding_time = 0xffff;
++	struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx];
++	struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
++
++	if (mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_HW_VHT_TIMER)
++		sounding_time = beam_oid_info.sound_oid_period * 32;
++	else if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_SW_VHT_TIMER)
++		/*@Modified by David*/
++		sounding_time = beam_entry.sound_period; /*@beam_oid_info.sound_oid_period;*/
++	else
++		sounding_time = beam_entry.sound_period;
++
++	return sounding_time;
++}
++
++enum channel_width
++phydm_beamforming_sounding_bw(
++	void *dm_void,
++	struct _RT_BEAMFORMING_INFO *beam_info,
++	enum sounding_mode mode,
++	u8 idx)
++{
++	enum channel_width sounding_bw = CHANNEL_WIDTH_20;
++	struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx];
++	struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_HW_VHT_TIMER)
++		sounding_bw = beam_oid_info.sound_oid_bw;
++	else if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_SW_VHT_TIMER)
++		/*@Modified by David*/
++		sounding_bw = beam_entry.sound_bw; /*@beam_oid_info.sound_oid_bw;*/
++	else
++		sounding_bw = beam_entry.sound_bw;
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s, sounding_bw=0x%X\n", __func__,
++		  sounding_bw);
++
++	return sounding_bw;
++}
++
++boolean
++phydm_beamforming_select_beam_entry(
++	void *dm_void,
++	struct _RT_BEAMFORMING_INFO *beam_info)
++{
++	struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	/*@entry.is_sound is different between first and latter NDPA, and should not be used as BFee entry selection*/
++	/*@BTW, latter modification should sync to the selection mechanism of AP/ADSL instead of the fixed sound_idx.*/
++	sound_info->sound_idx = phydm_beamforming_sounding_idx(dm, beam_info);
++	/*sound_info->sound_idx = 0;*/
++
++	if (sound_info->sound_idx < BEAMFORMEE_ENTRY_NUM)
++		sound_info->sound_mode = phydm_beamforming_sounding_mode(dm, beam_info, sound_info->sound_idx);
++	else
++		sound_info->sound_mode = sounding_stop_all_timer;
++
++	if (sounding_stop_all_timer == sound_info->sound_mode) {
++		PHYDM_DBG(dm, DBG_TXBF,
++			  "[%s] Return because of sounding_stop_all_timer\n",
++			  __func__);
++		return false;
++	} else {
++		sound_info->sound_bw = phydm_beamforming_sounding_bw(dm, beam_info, sound_info->sound_mode, sound_info->sound_idx);
++		sound_info->sound_period = phydm_beamforming_sounding_time(dm, beam_info, sound_info->sound_mode, sound_info->sound_idx);
++		return true;
++	}
++}
++
++/*SU BFee Entry Only*/
++boolean
++phydm_beamforming_start_period(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	boolean ret = true;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;
++
++	phydm_beamforming_dym_ndpa_rate(dm);
++
++	phydm_beamforming_select_beam_entry(dm, beam_info); /* @Modified */
++
++	if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)
++		odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period);
++	else if (sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || sound_info->sound_mode == SOUNDING_HW_HT_TIMER ||
++		 sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER) {
++		HAL_HW_TIMER_TYPE timer_type = HAL_TIMER_TXBF;
++		u32 val = (sound_info->sound_period | (timer_type << 16));
++
++		/* @HW timer stop: All IC has the same setting */
++		phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type));
++		/* odm_write_1byte(dm, 0x15F, 0); */
++		/* @HW timer init: All IC has the same setting, but 92E & 8812A only write 2 bytes */
++		phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_INIT, (u8 *)(&val));
++		/* odm_write_1byte(dm, 0x164, 1); */
++		/* odm_write_4byte(dm, 0x15C, val); */
++		/* @HW timer start: All IC has the same setting */
++		phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_START, (u8 *)(&timer_type));
++		/* odm_write_1byte(dm, 0x15F, 0x5); */
++	} else if (sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || sound_info->sound_mode == SOUNDING_FW_HT_TIMER)
++		ret = beamforming_start_fw(dm, sound_info->sound_idx);
++	else
++		ret = false;
++
++	PHYDM_DBG(dm, DBG_TXBF,
++		  "[%s] sound_idx=%d, sound_mode=%d, sound_bw=%d, sound_period=%d\n",
++		  __func__, sound_info->sound_idx, sound_info->sound_mode,
++		  sound_info->sound_bw, sound_info->sound_period);
++
++	return ret;
++}
++
++/* Used after beamforming_leave, and will clear the setting of the "already deleted" entry
++ *SU BFee Entry Only*/
++void phydm_beamforming_end_period_sw(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	/*void					*adapter = dm->adapter;*/
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;
++
++	HAL_HW_TIMER_TYPE timer_type = HAL_TIMER_TXBF;
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
++
++	if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)
++		odm_cancel_timer(dm, &beam_info->beamforming_timer);
++	else if (sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || sound_info->sound_mode == SOUNDING_HW_HT_TIMER ||
++		 sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER)
++		/*@HW timer stop: All IC has the same setting*/
++		phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type));
++	/*odm_write_1byte(dm, 0x15F, 0);*/
++}
++
++void phydm_beamforming_end_period_fw(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 idx = 0;
++
++	hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx);
++	PHYDM_DBG(dm, DBG_TXBF, "[%s]\n", __func__);
++}
++
++/*SU BFee Entry Only*/
++void phydm_beamforming_clear_entry_sw(
++	void *dm_void,
++	boolean is_delete,
++	u8 delete_idx)
++{
++	u8 idx = 0;
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++
++	if (is_delete) {
++		if (delete_idx < BEAMFORMEE_ENTRY_NUM) {
++			beamform_entry = beam_info->beamformee_entry + delete_idx;
++			if (!(!beamform_entry->is_used && beamform_entry->is_sound)) {
++				PHYDM_DBG(dm, DBG_TXBF,
++					  "[%s] SW delete_idx is wrong!!!!!\n",
++					  __func__);
++				return;
++			}
++		}
++
++		PHYDM_DBG(dm, DBG_TXBF, "[%s] SW delete BFee entry %d\n",
++			  __func__, delete_idx);
++		if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) {
++			beamform_entry->is_beamforming_in_progress = false;
++			beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;
++		} else if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
++			beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;
++			hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&delete_idx);
++		}
++		beamform_entry->is_sound = false;
++		return;
++	}
++
++	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
++		beamform_entry = beam_info->beamformee_entry + idx;
++
++		/*Used after is_sounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/
++		/*This function is mainly used in case "beam_oid_info.sound_oid_mode == sounding_stop_all_timer".*/
++		/*@However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/
++
++		if (!beamform_entry->is_sound)
++			continue;
++
++		PHYDM_DBG(dm, DBG_TXBF, "[%s] SW reset BFee entry %d\n",
++			  __func__, idx);
++		/*@
++		*	If End procedure is
++		*	1. Between (Send NDPA, C2H packet return), reset state to initialized.
++		*	After C2H packet return , status bit will be set to zero.
++		*
++		*	2. After C2H packet, then reset state to initialized and clear status bit.
++		*/
++
++		if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
++			phydm_beamforming_end_sw(dm, 0);
++		else if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
++			beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
++			hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx);
++		}
++
++		beamform_entry->is_sound = false;
++	}
++}
++
++void phydm_beamforming_clear_entry_fw(
++	void *dm_void,
++	boolean is_delete,
++	u8 delete_idx)
++{
++	u8 idx = 0;
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++
++	if (is_delete) {
++		if (delete_idx < BEAMFORMEE_ENTRY_NUM) {
++			beamform_entry = beam_info->beamformee_entry + delete_idx;
++
++			if (!(!beamform_entry->is_used && beamform_entry->is_sound)) {
++				PHYDM_DBG(dm, DBG_TXBF,
++					  "[%s] FW delete_idx is wrong!!!!!\n",
++					  __func__);
++				return;
++			}
++		}
++		PHYDM_DBG(dm, DBG_TXBF, "%s: FW delete BFee entry %d\n",
++			  __func__, delete_idx);
++		beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;
++		beamform_entry->is_sound = false;
++	} else {
++		for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
++			beamform_entry = beam_info->beamformee_entry + idx;
++
++			/*Used after is_sounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/
++			/*This function is mainly used in case "beam_oid_info.sound_oid_mode == sounding_stop_all_timer".*/
++			/*@However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/
++
++			if (beamform_entry->is_sound) {
++				PHYDM_DBG(dm, DBG_TXBF,
++					  "[%s]FW reset BFee entry %d\n",
++					  __func__, idx);
++				/*@
++				*	If End procedure is
++				*	1. Between (Send NDPA, C2H packet return), reset state to initialized.
++				*	After C2H packet return , status bit will be set to zero.
++				*
++				*	2. After C2H packet, then reset state to initialized and clear status bit.
++				*/
++
++				beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
++				beamform_entry->is_sound = false;
++			}
++		}
++	}
++}
++
++/*@
++*	Called :
++*	1. Add and delete entry : beamforming_enter/beamforming_leave
++*	2. FW trigger :  Beamforming_SetTxBFen
++*	3. Set OID_RT_BEAMFORMING_PERIOD : beamforming_control_v2
++*/
++void phydm_beamforming_notify(
++	void *dm_void)
++{
++	u8 idx = BEAMFORMEE_ENTRY_NUM;
++	enum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
++
++	is_sounding = phydm_beamfomring_is_sounding(dm, beam_info, &idx);
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s, Before notify, is_sounding=%d, idx=%d\n",
++		  __func__, is_sounding, idx);
++	PHYDM_DBG(dm, DBG_TXBF, "%s: beam_info->beamformee_su_cnt = %d\n",
++		  __func__, beam_info->beamformee_su_cnt);
++
++	switch (is_sounding) {
++	case BEAMFORMEE_NOTIFY_ADD_SU:
++		PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_ADD_SU\n",
++			  __func__);
++		phydm_beamforming_start_period(dm);
++		break;
++
++	case BEAMFORMEE_NOTIFY_DELETE_SU:
++		PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_DELETE_SU\n",
++			  __func__);
++		if (sound_info->sound_mode == SOUNDING_FW_HT_TIMER || sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) {
++			phydm_beamforming_clear_entry_fw(dm, true, idx);
++			if (beam_info->beamformee_su_cnt == 0) { /* @For 2->1 entry, we should not cancel SW timer */
++				phydm_beamforming_end_period_fw(dm);
++				PHYDM_DBG(dm, DBG_TXBF, "%s: No BFee left\n",
++					  __func__);
++			}
++		} else {
++			phydm_beamforming_clear_entry_sw(dm, true, idx);
++			if (beam_info->beamformee_su_cnt == 0) { /* @For 2->1 entry, we should not cancel SW timer */
++				phydm_beamforming_end_period_sw(dm);
++				PHYDM_DBG(dm, DBG_TXBF, "%s: No BFee left\n",
++					  __func__);
++			}
++		}
++		break;
++
++	case BEAMFORMEE_NOTIFY_ADD_MU:
++		PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_ADD_MU\n",
++			  __func__);
++		if (beam_info->beamformee_mu_cnt == 2) {
++			/*@if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)
++				odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period);*/
++			odm_set_timer(dm, &beam_info->beamforming_timer, 1000); /*@Do MU sounding every 1sec*/
++		} else
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "%s: Less or larger than 2 MU STAs, not to set timer\n",
++				  __func__);
++		break;
++
++	case BEAMFORMEE_NOTIFY_DELETE_MU:
++		PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_DELETE_MU\n",
++			  __func__);
++		if (beam_info->beamformee_mu_cnt == 1) {
++			/*@if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)*/ {
++				odm_cancel_timer(dm, &beam_info->beamforming_timer);
++				PHYDM_DBG(dm, DBG_TXBF,
++					  "%s: Less than 2 MU STAs, stop sounding\n",
++					  __func__);
++			}
++		}
++		break;
++
++	case BEAMFORMING_NOTIFY_RESET:
++		if (sound_info->sound_mode == SOUNDING_FW_HT_TIMER || sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) {
++			phydm_beamforming_clear_entry_fw(dm, false, idx);
++			phydm_beamforming_end_period_fw(dm);
++		} else {
++			phydm_beamforming_clear_entry_sw(dm, false, idx);
++			phydm_beamforming_end_period_sw(dm);
++		}
++
++		break;
++
++	default:
++		break;
++	}
++}
++
++boolean
++beamforming_init_entry(void *dm_void, u16 sta_idx, u8 *bfer_bfee_idx,
++		       u8 *my_mac_addr)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *cmn_sta = dm->phydm_sta_info[sta_idx];
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;
++	struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL;
++	struct _RT_BEAMFORM_STAINFO *sta = NULL;
++	enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE;
++	u8 bfer_idx = 0xF, bfee_idx = 0xF;
++	u8 num_of_sounding_dim = 0, comp_steering_num_of_bfer = 0;
++
++	if (!is_sta_active(cmn_sta)) {
++		PHYDM_DBG(dm, DBG_TXBF, "%s => sta_info(mac_id:%d) failed\n",
++			  __func__, sta_idx);
++		#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		rtw_warn_on(1);
++		#endif
++		return false;
++	}
++
++	sta = phydm_sta_info_init(dm, sta_idx, my_mac_addr);
++	/*The current setting does not support Beaforming*/
++	if (BEAMFORMING_CAP_NONE == sta->ht_beamform_cap && BEAMFORMING_CAP_NONE == sta->vht_beamform_cap) {
++		PHYDM_DBG(dm, DBG_TXBF,
++			  "The configuration disabled Beamforming! Skip...\n");
++		return false;
++	}
++
++	if (!(cmn_sta->support_wireless_set & (WIRELESS_VHT | WIRELESS_HT)))
++		return false;
++	else {
++		if (cmn_sta->support_wireless_set & WIRELESS_HT) { /*@HT*/
++			if (TEST_FLAG(sta->cur_beamform, BEAMFORMING_HT_BEAMFORMER_ENABLE)) { /*We are Beamformee because the STA is Beamformer*/
++				beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_HT_EXPLICIT);
++				num_of_sounding_dim = (sta->cur_beamform & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6;
++			}
++			/*We are Beamformer because the STA is Beamformee*/
++			if (TEST_FLAG(sta->cur_beamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE) ||
++			    TEST_FLAG(sta->ht_beamform_cap, BEAMFORMING_HT_BEAMFORMER_TEST)) {
++				beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_HT_EXPLICIT);
++				comp_steering_num_of_bfer = (sta->cur_beamform & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4;
++			}
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "[%s] HT cur_beamform=0x%X, beamform_cap=0x%X\n",
++				  __func__, sta->cur_beamform, beamform_cap);
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "[%s] HT num_of_sounding_dim=%d, comp_steering_num_of_bfer=%d\n",
++				  __func__, num_of_sounding_dim,
++				  comp_steering_num_of_bfer);
++		}
++#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
++		if (cmn_sta->support_wireless_set & WIRELESS_VHT) { /*VHT*/
++
++			/* We are Beamformee because the STA is SU Beamformer*/
++			if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
++				beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_SU);
++				num_of_sounding_dim = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12;
++			}
++			/* We are Beamformer because the STA is SU Beamformee*/
++			if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) ||
++			    TEST_FLAG(sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) {
++				beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_SU);
++				comp_steering_num_of_bfer = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8;
++			}
++			/* We are Beamformee because the STA is MU Beamformer*/
++			if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) {
++				beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_MU);
++				num_of_sounding_dim = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12;
++			}
++			/* We are Beamformer because the STA is MU Beamformee*/
++			if (phydm_acting_determine(dm, phydm_acting_as_ap)) { /* Only AP mode supports to act an MU beamformer */
++				if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE) ||
++				    TEST_FLAG(sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) {
++					beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_MU);
++					comp_steering_num_of_bfer = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8;
++				}
++			}
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "[%s]VHT cur_beamform_vht=0x%X, beamform_cap=0x%X\n",
++				  __func__, sta->cur_beamform_vht,
++				  beamform_cap);
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "[%s]VHT num_of_sounding_dim=0x%X, comp_steering_num_of_bfer=0x%X\n",
++				  __func__, num_of_sounding_dim,
++				  comp_steering_num_of_bfer);
++		}
++#endif
++	}
++
++	if (beamform_cap == BEAMFORMING_CAP_NONE)
++		return false;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Self BF Entry Cap = 0x%02X\n", __func__,
++		  beamform_cap);
++
++	/*We are BFee, so the entry is BFer*/
++	if (beamform_cap & (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) {
++		beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, sta->ra, &bfer_idx);
++
++		if (beamformer_entry == NULL) {
++			beamformer_entry = beamforming_add_bfer_entry(dm, sta, beamform_cap, num_of_sounding_dim, &bfer_idx);
++			if (beamformer_entry == NULL)
++				PHYDM_DBG(dm, DBG_TXBF,
++					  "[%s]Not enough BFer entry!!!!!\n",
++					  __func__);
++		}
++	}
++
++	/*We are BFer, so the entry is BFee*/
++	if (beamform_cap & (BEAMFORMER_CAP_VHT_MU | BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) {
++		beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, sta->ra, &bfee_idx);
++
++		/*@if BFeeIdx = 0xF, that represent for no matched MACID among all linked entrys */
++		PHYDM_DBG(dm, DBG_TXBF, "[%s] Get BFee entry 0x%X by address\n",
++			  __func__, bfee_idx);
++		if (beamform_entry == NULL) {
++			beamform_entry = beamforming_add_bfee_entry(dm, sta, beamform_cap, num_of_sounding_dim, comp_steering_num_of_bfer, &bfee_idx);
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "[%s]: sta->AID=%d, sta->mac_id=%d\n",
++				  __func__, sta->aid, sta->mac_id);
++
++			PHYDM_DBG(dm, DBG_TXBF, "[%s]: Add BFee entry %d\n",
++				  __func__, bfee_idx);
++
++			if (beamform_entry == NULL)
++				return false;
++			else
++				beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING;
++		} else {
++			/*@Entry has been created. If entry is initialing or progressing then errors occur.*/
++			if (beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED &&
++			    beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED)
++				return false;
++			else
++				beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING;
++		}
++		beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
++		phydm_sta_info_update(dm, sta_idx, beamform_entry);
++	}
++
++	*bfer_bfee_idx = (bfer_idx << 4) | bfee_idx;
++	PHYDM_DBG(dm, DBG_TXBF,
++		  "[%s] End: bfer_idx=0x%X, bfee_idx=0x%X, bfer_bfee_idx=0x%X\n",
++		  __func__, bfer_idx, bfee_idx, *bfer_bfee_idx);
++
++	return true;
++}
++
++void beamforming_deinit_entry(
++	void *dm_void,
++	u8 *RA)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 idx = 0;
++
++	struct _RT_BEAMFORMER_ENTRY *bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, RA, &idx);
++	struct _RT_BEAMFORMEE_ENTRY *bfee_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
++	boolean ret = false;
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
++
++	if (bfee_entry != NULL) {
++		PHYDM_DBG(dm, DBG_TXBF, "%s, bfee_entry\n", __func__);
++		bfee_entry->is_used = false;
++		bfee_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE;
++		bfee_entry->is_beamforming_in_progress = false;
++		if (bfee_entry->is_mu_sta) {
++			dm->beamforming_info.beamformee_mu_cnt -= 1;
++			dm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(dm);
++		} else
++			dm->beamforming_info.beamformee_su_cnt -= 1;
++		ret = true;
++	}
++
++	if (bfer_entry != NULL) {
++		PHYDM_DBG(dm, DBG_TXBF, "%s, bfer_entry\n", __func__);
++		bfer_entry->is_used = false;
++		bfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE;
++		if (bfer_entry->is_mu_ap)
++			dm->beamforming_info.beamformer_mu_cnt -= 1;
++		else
++			dm->beamforming_info.beamformer_su_cnt -= 1;
++		ret = true;
++	}
++
++	if (ret == true)
++		hal_com_txbf_set(dm, TXBF_SET_SOUNDING_LEAVE, (u8 *)&idx);
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s End, idx = 0x%X\n", __func__, idx);
++}
++
++boolean
++beamforming_start_v1(
++	void *dm_void,
++	u8 *RA,
++	boolean mode,
++	enum channel_width BW,
++	u8 rate)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 idx = 0;
++	struct _RT_BEAMFORMEE_ENTRY *entry;
++	boolean ret = true;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++
++	entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
++
++	if (entry->is_used == false) {
++		entry->is_beamforming_in_progress = false;
++		return false;
++	} else {
++		if (entry->is_beamforming_in_progress)
++			return false;
++
++		entry->is_beamforming_in_progress = true;
++
++		if (mode == 1) {
++			if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) {
++				entry->is_beamforming_in_progress = false;
++				return false;
++			}
++		} else if (mode == 0) {
++			if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) {
++				entry->is_beamforming_in_progress = false;
++				return false;
++			}
++		}
++
++		if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) {
++			entry->is_beamforming_in_progress = false;
++			return false;
++		} else {
++			entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING;
++			entry->is_sound = true;
++		}
++	}
++
++	entry->sound_bw = BW;
++	beam_info->beamformee_cur_idx = idx;
++	phydm_beamforming_ndpa_rate(dm, BW, rate);
++	hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx);
++
++	if (mode == 1)
++		ret = beamforming_send_ht_ndpa_packet(dm, RA, BW, NORMAL_QUEUE);
++	else
++		ret = beamforming_send_vht_ndpa_packet(dm, RA, entry->aid, BW, NORMAL_QUEUE);
++
++	if (ret == false) {
++		beamforming_leave(dm, RA);
++		entry->is_beamforming_in_progress = false;
++		return false;
++	}
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s  idx %d\n", __func__, idx);
++	return true;
++}
++
++boolean
++beamforming_start_sw(
++	void *dm_void,
++	u8 idx,
++	u8 mode,
++	enum channel_width BW)
++{
++	u8 *ra = NULL;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMEE_ENTRY *entry;
++	boolean ret = true;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++#ifdef SUPPORT_MU_BF
++#if (SUPPORT_MU_BF == 1)
++	u8 i, poll_sta_cnt = 0;
++	boolean is_get_first_bfee = false;
++#endif
++#endif
++
++	if (beam_info->is_mu_sounding) {
++		beam_info->is_mu_sounding_in_progress = true;
++		entry = &beam_info->beamformee_entry[idx];
++		ra = entry->mac_addr;
++
++	} else {
++		entry = &beam_info->beamformee_entry[idx];
++
++		if (entry->is_used == false) {
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "Skip Beamforming, no entry for idx =%d\n",
++				  idx);
++			entry->is_beamforming_in_progress = false;
++			return false;
++		}
++
++		if (entry->is_beamforming_in_progress) {
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "is_beamforming_in_progress, skip...\n");
++			return false;
++		}
++
++		entry->is_beamforming_in_progress = true;
++		ra = entry->mac_addr;
++
++		if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER) {
++			if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) {
++				entry->is_beamforming_in_progress = false;
++				PHYDM_DBG(dm, DBG_TXBF,
++					  "%s Return by not support BEAMFORMER_CAP_HT_EXPLICIT <==\n",
++					  __func__);
++				return false;
++			}
++		} else if (mode == SOUNDING_SW_VHT_TIMER || mode == SOUNDING_HW_VHT_TIMER || mode == SOUNDING_AUTO_VHT_TIMER) {
++			if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) {
++				entry->is_beamforming_in_progress = false;
++				PHYDM_DBG(dm, DBG_TXBF,
++					  "%s Return by not support BEAMFORMER_CAP_VHT_SU <==\n",
++					  __func__);
++				return false;
++			}
++		}
++		if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) {
++			entry->is_beamforming_in_progress = false;
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "%s Return by incorrect beamform_entry_state(%d) <==\n",
++				  __func__, entry->beamform_entry_state);
++			return false;
++		} else {
++			entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING;
++			entry->is_sound = true;
++		}
++
++		beam_info->beamformee_cur_idx = idx;
++	}
++
++	/*@2014.12.22 Luke: Need to be checked*/
++	/*@GET_TXBF_INFO(adapter)->fTxbfSet(adapter, TXBF_SET_SOUNDING_STATUS, (u8*)&idx);*/
++
++	if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER)
++		ret = beamforming_send_ht_ndpa_packet(dm, ra, BW, NORMAL_QUEUE);
++	else
++		ret = beamforming_send_vht_ndpa_packet(dm, ra, entry->aid, BW, NORMAL_QUEUE);
++
++	if (ret == false) {
++		beamforming_leave(dm, ra);
++		entry->is_beamforming_in_progress = false;
++		return false;
++	}
++
++/*@--------------------------
++	 * Send BF Report Poll for MU BF
++	--------------------------*/
++#ifdef SUPPORT_MU_BF
++#if (SUPPORT_MU_BF == 1)
++	if (beam_info->beamformee_mu_cnt <= 1)
++		goto out;
++
++	/* @More than 1 MU STA*/
++	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
++		entry = &beam_info->beamformee_entry[i];
++		if (!entry->is_mu_sta)
++			continue;
++
++		if (!is_get_first_bfee) {
++			is_get_first_bfee = true;
++			continue;
++		}
++
++		poll_sta_cnt++;
++		if (poll_sta_cnt == (beam_info->beamformee_mu_cnt - 1)) /* The last STA*/
++			send_sw_vht_bf_report_poll(dm, entry->mac_addr, true);
++		else
++			send_sw_vht_bf_report_poll(dm, entry->mac_addr, false);
++	}
++out:
++#endif
++#endif
++	return true;
++}
++
++boolean
++beamforming_start_fw(
++	void *dm_void,
++	u8 idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMEE_ENTRY *entry;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++
++	entry = &beam_info->beamformee_entry[idx];
++	if (entry->is_used == false) {
++		PHYDM_DBG(dm, DBG_TXBF,
++			  "Skip Beamforming, no entry for idx =%d\n", idx);
++		return false;
++	}
++
++	entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING;
++	entry->is_sound = true;
++	hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx);
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] End, idx=0x%X\n", __func__, idx);
++	return true;
++}
++
++void beamforming_check_sounding_success(
++	void *dm_void,
++	boolean status)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx];
++
++	PHYDM_DBG(dm, DBG_TXBF, "[David]@%s Start!\n", __func__);
++
++	if (status == 1) {
++		if (entry->log_status_fail_cnt == 21)
++			beamforming_dym_period(dm, status);
++		entry->log_status_fail_cnt = 0;
++	} else if (entry->log_status_fail_cnt <= 20) {
++		entry->log_status_fail_cnt++;
++		PHYDM_DBG(dm, DBG_TXBF, "%s log_status_fail_cnt %d\n", __func__,
++			  entry->log_status_fail_cnt);
++	}
++	if (entry->log_status_fail_cnt > 20) {
++		entry->log_status_fail_cnt = 21;
++		PHYDM_DBG(dm, DBG_TXBF,
++			  "%s log_status_fail_cnt > 20, Stop SOUNDING\n",
++			  __func__);
++		beamforming_dym_period(dm, status);
++	}
++}
++
++void phydm_beamforming_end_sw(
++	void *dm_void,
++	boolean status)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx];
++
++	if (beam_info->is_mu_sounding) {
++		PHYDM_DBG(dm, DBG_TXBF, "%s: MU sounding done\n", __func__);
++		beam_info->is_mu_sounding_in_progress = false;
++		hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS,
++				 (u8 *)&beam_info->beamformee_cur_idx);
++	} else {
++		if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSING) {
++			PHYDM_DBG(dm, DBG_TXBF, "[%s] BeamformStatus %d\n",
++				  __func__, entry->beamform_entry_state);
++			return;
++		}
++
++		if (beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7 && beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9 && !beam_info->snding3ss) {
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "[%s] VHT3SS 7,8,9, do not apply V matrix.\n",
++				  __func__);
++			entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
++			hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS,
++					 (u8 *)&beam_info->beamformee_cur_idx);
++		} else if (status == 1) {
++			entry->log_status_fail_cnt = 0;
++			entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
++			hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS,
++					 (u8 *)&beam_info->beamformee_cur_idx);
++		} else {
++			entry->log_status_fail_cnt++;
++			entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
++			hal_com_txbf_set(dm, TXBF_SET_TX_PATH_RESET,
++					 (u8 *)&beam_info->beamformee_cur_idx);
++			PHYDM_DBG(dm, DBG_TXBF, "[%s] log_status_fail_cnt %d\n",
++				  __func__, entry->log_status_fail_cnt);
++		}
++
++		if (entry->log_status_fail_cnt > 50) {
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "%s log_status_fail_cnt > 50, Stop SOUNDING\n",
++				  __func__);
++			entry->is_sound = false;
++			beamforming_deinit_entry(dm, entry->mac_addr);
++
++			/*@Modified by David - Every action of deleting entry should follow by Notify*/
++			phydm_beamforming_notify(dm);
++		}
++
++		entry->is_beamforming_in_progress = false;
++	}
++	PHYDM_DBG(dm, DBG_TXBF, "%s: status=%d\n", __func__, status);
++}
++
++void beamforming_timer_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *dm_void
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	void *context
++#endif
++	)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	void *adapter = (void *)context;
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->odmpriv;
++#endif
++	boolean ret = false;
++	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
++	struct _RT_BEAMFORMEE_ENTRY *entry = &(beam_info->beamformee_entry[beam_info->beamformee_cur_idx]);
++	struct _RT_SOUNDING_INFO *sound_info = &(beam_info->sounding_info);
++	boolean is_beamforming_in_progress;
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
++
++	if (beam_info->is_mu_sounding)
++		is_beamforming_in_progress = beam_info->is_mu_sounding_in_progress;
++	else
++		is_beamforming_in_progress = entry->is_beamforming_in_progress;
++
++	if (is_beamforming_in_progress) {
++		PHYDM_DBG(dm, DBG_TXBF,
++			  "is_beamforming_in_progress, reset it\n");
++		phydm_beamforming_end_sw(dm, 0);
++	}
++
++	ret = phydm_beamforming_select_beam_entry(dm, beam_info);
++#if (SUPPORT_MU_BF == 1)
++	if (ret && beam_info->beamformee_mu_cnt > 1)
++		ret = 1;
++	else
++		ret = 0;
++#endif
++	if (ret)
++		ret = beamforming_start_sw(dm, sound_info->sound_idx, sound_info->sound_mode, sound_info->sound_bw);
++	else
++		PHYDM_DBG(dm, DBG_TXBF,
++			  "%s, Error value return from BeamformingStart_V2\n",
++			  __func__);
++
++	if (beam_info->beamformee_su_cnt != 0 || beam_info->beamformee_mu_cnt > 1) {
++		if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)
++			odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period);
++		else {
++			u32 val = (sound_info->sound_period << 16) | HAL_TIMER_TXBF;
++			phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_RESTART, (u8 *)(&val));
++		}
++	}
++}
++
++void beamforming_sw_timer_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct phydm_timer_list *timer
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	void *function_context
++#endif
++	)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter = (void *)timer->Adapter;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++	beamforming_timer_callback(dm);
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	struct dm_struct *dm = (struct dm_struct *)function_context;
++	void *adapter = dm->adapter;
++
++	if (*dm->is_net_closed == true)
++		return;
++	phydm_run_in_thread_cmd(dm, beamforming_timer_callback, adapter);
++#endif
++}
++
++void phydm_beamforming_init(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMING_OID_INFO *beam_oid_info = &beam_info->beamforming_oid_info;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter = dm->adapter;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++
++#ifdef BEAMFORMING_VERSION_1
++	if (hal_data->beamforming_version != BEAMFORMING_VERSION_1) {
++		return;
++	}
++#endif
++#endif
++
++	beam_oid_info->sound_oid_mode = SOUNDING_STOP_OID_TIMER;
++	PHYDM_DBG(dm, DBG_TXBF, "%s mode (%d)\n", __func__,
++		  beam_oid_info->sound_oid_mode);
++
++	beam_info->beamformee_su_cnt = 0;
++	beam_info->beamformer_su_cnt = 0;
++	beam_info->beamformee_mu_cnt = 0;
++	beam_info->beamformer_mu_cnt = 0;
++	beam_info->beamformee_mu_reg_maping = 0;
++	beam_info->mu_ap_index = 0;
++	beam_info->is_mu_sounding = false;
++	beam_info->first_mu_bfee_index = 0xFF;
++	beam_info->apply_v_matrix = true;
++	beam_info->snding3ss = false;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	beam_info->source_adapter = dm->adapter;
++#endif
++	hal_com_txbf_beamform_init(dm);
++}
++
++boolean
++phydm_acting_determine(
++	void *dm_void,
++	enum phydm_acting_type type)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	boolean ret = false;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter = dm->beamforming_info.source_adapter;
++#else
++	struct _ADAPTER *adapter = dm->adapter;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	if (type == phydm_acting_as_ap)
++		ret = ACTING_AS_AP(adapter);
++	else if (type == phydm_acting_as_ibss)
++		ret = ACTING_AS_IBSS(((PADAPTER)(adapter)));
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
++
++	if (type == phydm_acting_as_ap)
++		ret = check_fwstate(pmlmepriv, WIFI_AP_STATE);
++	else if (type == phydm_acting_as_ibss)
++		ret = check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
++#endif
++
++	return ret;
++}
++
++void beamforming_enter(void *dm_void, u16 sta_idx, u8 *my_mac_addr)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 bfer_bfee_idx = 0xff;
++
++	if (beamforming_init_entry(dm, sta_idx, &bfer_bfee_idx, my_mac_addr))
++		hal_com_txbf_set(dm, TXBF_SET_SOUNDING_ENTER, (u8 *)&bfer_bfee_idx);
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] End!\n", __func__);
++}
++
++void beamforming_leave(
++	void *dm_void,
++	u8 *RA)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (RA != NULL) {
++		beamforming_deinit_entry(dm, RA);
++		phydm_beamforming_notify(dm);
++	}
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] End!!\n", __func__);
++}
++
++enum beamforming_cap
++phydm_beamforming_get_beam_cap(
++	void *dm_void,
++	struct _RT_BEAMFORMING_INFO *beam_info)
++{
++	u8 i;
++	boolean is_self_beamformer = false;
++	boolean is_self_beamformee = false;
++	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
++	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
++	enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
++		beamformee_entry = beam_info->beamformee_entry[i];
++
++		if (beamformee_entry.is_used) {
++			is_self_beamformer = true;
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "[%s] BFee entry %d is_used=true\n", __func__,
++				  i);
++			break;
++		}
++	}
++
++	for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) {
++		beamformer_entry = beam_info->beamformer_entry[i];
++
++		if (beamformer_entry.is_used) {
++			is_self_beamformee = true;
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "[%s]: BFer entry %d is_used=true\n",
++				  __func__, i);
++			break;
++		}
++	}
++
++	if (is_self_beamformer)
++		beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP);
++	if (is_self_beamformee)
++		beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP);
++
++	return beamform_cap;
++}
++
++boolean
++beamforming_control_v1(
++	void *dm_void,
++	u8 *RA,
++	u8 AID,
++	u8 mode,
++	enum channel_width BW,
++	u8 rate)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	boolean ret = true;
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
++
++	PHYDM_DBG(dm, DBG_TXBF, "AID (%d), mode (%d), BW (%d)\n", AID, mode,
++		  BW);
++
++	switch (mode) {
++	case 0:
++		ret = beamforming_start_v1(dm, RA, 0, BW, rate);
++		break;
++	case 1:
++		ret = beamforming_start_v1(dm, RA, 1, BW, rate);
++		break;
++	case 2:
++		phydm_beamforming_ndpa_rate(dm, BW, rate);
++		ret = beamforming_send_vht_ndpa_packet(dm, RA, AID, BW, NORMAL_QUEUE);
++		break;
++	case 3:
++		phydm_beamforming_ndpa_rate(dm, BW, rate);
++		ret = beamforming_send_ht_ndpa_packet(dm, RA, BW, NORMAL_QUEUE);
++		break;
++	}
++	return ret;
++}
++
++/*Only OID uses this function*/
++boolean
++phydm_beamforming_control_v2(
++	void *dm_void,
++	u8 idx,
++	u8 mode,
++	enum channel_width BW,
++	u16 period)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMING_OID_INFO *beam_oid_info = &beam_info->beamforming_oid_info;
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
++	PHYDM_DBG(dm, DBG_TXBF, "idx (%d), mode (%d), BW (%d), period (%d)\n",
++		  idx, mode, BW, period);
++
++	beam_oid_info->sound_oid_idx = idx;
++	beam_oid_info->sound_oid_mode = (enum sounding_mode)mode;
++	beam_oid_info->sound_oid_bw = BW;
++	beam_oid_info->sound_oid_period = period;
++
++	phydm_beamforming_notify(dm);
++
++	return true;
++}
++
++void phydm_beamforming_watchdog(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
++
++	if (beam_info->beamformee_su_cnt == 0)
++		return;
++
++	beamforming_dym_period(dm, 0);
++}
++enum beamforming_cap
++phydm_get_beamform_cap(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *sta = NULL;
++	struct bf_cmn_info *bf_info = NULL;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	void *adapter = dm->adapter;
++	enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE;
++	u8 macid;
++	u8 ht_curbeamformcap = 0;
++	u16 vht_curbeamformcap = 0;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	PMGNT_INFO p_MgntInfo = &(((PADAPTER)(adapter))->MgntInfo);
++	PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_MgntInfo);
++	PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_MgntInfo);
++
++	ht_curbeamformcap = p_ht_info->HtCurBeamform;
++	vht_curbeamformcap = p_vht_info->VhtCurBeamform;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[%s] WIN ht_curcap = %d ; vht_curcap = %d\n", __func__,
++		  ht_curbeamformcap, vht_curbeamformcap);
++
++	if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) /*We are Beamformee because the STA is Beamformer*/
++		beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP));
++
++	/*We are Beamformer because the STA is Beamformee*/
++	if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMEE_ENABLE))
++		beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP));
++
++#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
++
++	/* We are Beamformee because the STA is SU Beamformer*/
++	if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMER_ENABLE))
++		beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP));
++
++	/* We are Beamformer because the STA is SU Beamformee*/
++	if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE))
++		beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP));
++
++	/* We are Beamformee because the STA is MU Beamformer*/
++	if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE))
++		beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP));
++#endif
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++
++	for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
++		sta = dm->phydm_sta_info[macid];
++
++		if (!is_sta_active(sta))
++			continue;
++
++		bf_info = &sta->bf_info;
++		vht_curbeamformcap = bf_info->vht_beamform_cap;
++		ht_curbeamformcap = bf_info->ht_beamform_cap;
++
++		if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) /*We are Beamformee because the STA is Beamformer*/
++			beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP));
++
++		/*We are Beamformer because the STA is Beamformee*/
++		if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMEE_ENABLE))
++			beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP));
++
++#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
++		/* We are Beamformee because the STA is SU Beamformer*/
++		if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMER_ENABLE))
++			beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP));
++
++		/* We are Beamformer because the STA is SU Beamformee*/
++		if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE))
++			beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP));
++
++		/* We are Beamformee because the STA is MU Beamformer*/
++		if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE))
++			beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP));
++#endif
++	}
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s] CE ht_curcap = %d ; vht_curcap = %d\n",
++		  __func__, ht_curbeamformcap, vht_curbeamformcap);
++
++#endif
++
++	return beamform_cap;
++}
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_beamforming.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_beamforming.h
+new file mode 100644
+index 000000000..efb53e309
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_beamforming.h
+@@ -0,0 +1,363 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __INC_PHYDM_BEAMFORMING_H
++#define __INC_PHYDM_BEAMFORMING_H
++
++/*@Beamforming Related*/
++#include "txbf/halcomtxbf.h"
++#include "txbf/haltxbfjaguar.h"
++#include "txbf/haltxbf8192e.h"
++#include "txbf/haltxbf8814a.h"
++#include "txbf/haltxbf8822b.h"
++#include "txbf/haltxbfinterface.h"
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++
++#define eq_mac_addr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0)
++#define cp_mac_addr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5])
++
++#endif
++
++#define MAX_BEAMFORMEE_SU 2
++#define MAX_BEAMFORMER_SU 2
++#if ((RTL8822B_SUPPORT == 1) || (RTL8812F_SUPPORT == 1))
++#define MAX_BEAMFORMEE_MU 6
++#define MAX_BEAMFORMER_MU 1
++#else
++#define MAX_BEAMFORMEE_MU 0
++#define MAX_BEAMFORMER_MU 0
++#endif
++
++#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU)
++#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU)
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++/*@for different naming between WIN and CE*/
++#define BEACON_QUEUE BCN_QUEUE_INX
++#define NORMAL_QUEUE MGT_QUEUE_INX
++#define RT_DISABLE_FUNC RTW_DISABLE_FUNC
++#define RT_ENABLE_FUNC RTW_ENABLE_FUNC
++#endif
++
++enum beamforming_entry_state {
++	BEAMFORMING_ENTRY_STATE_UNINITIALIZE,
++	BEAMFORMING_ENTRY_STATE_INITIALIZEING,
++	BEAMFORMING_ENTRY_STATE_INITIALIZED,
++	BEAMFORMING_ENTRY_STATE_PROGRESSING,
++	BEAMFORMING_ENTRY_STATE_PROGRESSED
++};
++
++enum beamforming_notify_state {
++	BEAMFORMING_NOTIFY_NONE,
++	BEAMFORMING_NOTIFY_ADD,
++	BEAMFORMING_NOTIFY_DELETE,
++	BEAMFORMEE_NOTIFY_ADD_SU,
++	BEAMFORMEE_NOTIFY_DELETE_SU,
++	BEAMFORMEE_NOTIFY_ADD_MU,
++	BEAMFORMEE_NOTIFY_DELETE_MU,
++	BEAMFORMING_NOTIFY_RESET
++};
++
++enum beamforming_cap {
++	BEAMFORMING_CAP_NONE = 0x0,
++	BEAMFORMER_CAP_HT_EXPLICIT = BIT(1),
++	BEAMFORMEE_CAP_HT_EXPLICIT = BIT(2),
++	BEAMFORMER_CAP_VHT_SU = BIT(5), /* @Self has er Cap, because Reg er  & peer ee */
++	BEAMFORMEE_CAP_VHT_SU = BIT(6), /* @Self has ee Cap, because Reg ee & peer er */
++	BEAMFORMER_CAP_VHT_MU = BIT(7), /* @Self has er Cap, because Reg er  & peer ee */
++	BEAMFORMEE_CAP_VHT_MU = BIT(8), /* @Self has ee Cap, because Reg ee & peer er */
++	BEAMFORMER_CAP = BIT(9),
++	BEAMFORMEE_CAP = BIT(10),
++};
++
++enum sounding_mode {
++	SOUNDING_SW_VHT_TIMER = 0x0,
++	SOUNDING_SW_HT_TIMER = 0x1,
++	sounding_stop_all_timer = 0x2,
++	SOUNDING_HW_VHT_TIMER = 0x3,
++	SOUNDING_HW_HT_TIMER = 0x4,
++	SOUNDING_STOP_OID_TIMER = 0x5,
++	SOUNDING_AUTO_VHT_TIMER = 0x6,
++	SOUNDING_AUTO_HT_TIMER = 0x7,
++	SOUNDING_FW_VHT_TIMER = 0x8,
++	SOUNDING_FW_HT_TIMER = 0x9,
++};
++
++struct _RT_BEAMFORM_STAINFO {
++	u8 *ra;
++	u16 aid;
++	u16 mac_id;
++	u8 my_mac_addr[6];
++	/*WIRELESS_MODE				wireless_mode;*/
++	enum channel_width bw;
++	enum beamforming_cap beamform_cap;
++	u8 ht_beamform_cap;
++	u16 vht_beamform_cap;
++	u8 cur_beamform;
++	u16 cur_beamform_vht;
++};
++
++struct _RT_BEAMFORMEE_ENTRY {
++	boolean is_used;
++	boolean is_txbf;
++	boolean is_sound;
++	u16 aid; /*Used to construct AID field of NDPA packet.*/
++	u16 mac_id; /*Used to Set Reg42C in IBSS mode. */
++	u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
++	u8 g_id; /*Used to fill Tx DESC*/
++	u8 my_mac_addr[6];
++	u8 mac_addr[6]; /*@Used to fill Reg6E4 to fill Mac address of CSI report frame.*/
++	enum channel_width sound_bw; /*Sounding band_width*/
++	u16 sound_period;
++	enum beamforming_cap beamform_entry_cap;
++	enum beamforming_entry_state beamform_entry_state;
++	boolean is_beamforming_in_progress;
++	/*@u8	log_seq;									// Move to _RT_BEAMFORMER_ENTRY*/
++	/*@u16	log_retry_cnt:3;		// 0~4				// Move to _RT_BEAMFORMER_ENTRY*/
++	/*@u16	LogSuccessCnt:2;		// 0~2				// Move to _RT_BEAMFORMER_ENTRY*/
++	u16 log_status_fail_cnt : 5; /* @0~21 */
++	u16 default_csi_cnt : 5; /* @0~21 */
++	u8 csi_matrix[327];
++	u16 csi_matrix_len;
++	u8 num_of_sounding_dim;
++	u8 comp_steering_num_of_bfer;
++	u8 su_reg_index;
++	/*@For MU-MIMO*/
++	boolean is_mu_sta;
++	u8 mu_reg_index;
++	u8 gid_valid[8];
++	u8 user_position[16];
++};
++
++struct _RT_BEAMFORMER_ENTRY {
++	boolean is_used;
++	/*P_AID of BFer entry is probably not used*/
++	u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
++	u8 g_id;
++	u8 my_mac_addr[6];
++	u8 mac_addr[6];
++	enum beamforming_cap beamform_entry_cap;
++	u8 num_of_sounding_dim;
++	u8 clock_reset_times; /*@Modified by Jeffery @2015-04-10*/
++	u8 pre_log_seq; /*@Modified by Jeffery @2015-03-30*/
++	u8 log_seq; /*@Modified by Jeffery @2014-10-29*/
++	u16 log_retry_cnt : 3; /*@Modified by Jeffery @2014-10-29*/
++	u16 log_success : 2; /*@Modified by Jeffery @2014-10-29*/
++	u8 su_reg_index;
++	/*@For MU-MIMO*/
++	boolean is_mu_ap;
++	u8 gid_valid[8];
++	u8 user_position[16];
++	u16 aid;
++};
++
++struct _RT_SOUNDING_INFO {
++	u8 sound_idx;
++	enum channel_width sound_bw;
++	enum sounding_mode sound_mode;
++	u16 sound_period;
++};
++
++struct _RT_BEAMFORMING_OID_INFO {
++	u8 sound_oid_idx;
++	enum channel_width sound_oid_bw;
++	enum sounding_mode sound_oid_mode;
++	u16 sound_oid_period;
++};
++
++struct _RT_BEAMFORMING_INFO {
++	enum beamforming_cap beamform_cap;
++	struct _RT_BEAMFORMEE_ENTRY beamformee_entry[BEAMFORMEE_ENTRY_NUM];
++	struct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM];
++	struct _RT_BEAMFORM_STAINFO beamform_sta_info;
++	u8 beamformee_cur_idx;
++	struct phydm_timer_list beamforming_timer;
++	struct phydm_timer_list mu_timer;
++	struct _RT_SOUNDING_INFO sounding_info;
++	struct _RT_BEAMFORMING_OID_INFO beamforming_oid_info;
++	struct _HAL_TXBF_INFO txbf_info;
++	u8 sounding_sequence;
++	u8 beamformee_su_cnt;
++	u8 beamformer_su_cnt;
++	u32 beamformee_su_reg_maping;
++	u32 beamformer_su_reg_maping;
++	/*@For MU-MINO*/
++	u8 beamformee_mu_cnt;
++	u8 beamformer_mu_cnt;
++	u32 beamformee_mu_reg_maping;
++	u8 mu_ap_index;
++	boolean is_mu_sounding;
++	u8 first_mu_bfee_index;
++	boolean is_mu_sounding_in_progress;
++	boolean dbg_disable_mu_tx;
++	boolean apply_v_matrix;
++	boolean snding3ss;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *source_adapter;
++#endif
++	/* @Control register */
++	u32 reg_mu_tx_ctrl; /* @For USB/SDIO interfaces aync I/O */
++	u8 tx_bf_data_rate;
++	u8 last_usb_hub;
++};
++
++void phydm_get_txbf_device_num(
++	void *dm_void,
++	u8 macid);
++
++struct _RT_NDPA_STA_INFO {
++	u16 aid : 12;
++	u16 feedback_type : 1;
++	u16 nc_index : 3;
++};
++
++enum phydm_acting_type {
++	phydm_acting_as_ibss = 0,
++	phydm_acting_as_ap = 1
++};
++
++enum beamforming_cap
++phydm_beamforming_get_entry_beam_cap_by_mac_id(
++	void *dm_void,
++	u8 mac_id);
++
++struct _RT_BEAMFORMEE_ENTRY *
++phydm_beamforming_get_bfee_entry_by_addr(
++	void *dm_void,
++	u8 *RA,
++	u8 *idx);
++
++struct _RT_BEAMFORMER_ENTRY *
++phydm_beamforming_get_bfer_entry_by_addr(
++	void *dm_void,
++	u8 *TA,
++	u8 *idx);
++
++void phydm_beamforming_notify(
++	void *dm_void);
++
++boolean
++phydm_acting_determine(
++	void *dm_void,
++	enum phydm_acting_type type);
++
++void beamforming_enter(void *dm_void, u16 sta_idx, u8 *my_mac_addr);
++
++void beamforming_leave(
++	void *dm_void,
++	u8 *RA);
++
++boolean
++beamforming_start_fw(
++	void *dm_void,
++	u8 idx);
++
++void beamforming_check_sounding_success(
++	void *dm_void,
++	boolean status);
++
++void phydm_beamforming_end_sw(
++	void *dm_void,
++	boolean status);
++
++void beamforming_timer_callback(
++	void *dm_void);
++
++void phydm_beamforming_init(
++	void *dm_void);
++
++enum beamforming_cap
++phydm_beamforming_get_beam_cap(
++	void *dm_void,
++	struct _RT_BEAMFORMING_INFO *beam_info);
++
++enum beamforming_cap
++phydm_get_beamform_cap(
++	void *dm_void);
++
++boolean
++beamforming_control_v1(
++	void *dm_void,
++	u8 *RA,
++	u8 AID,
++	u8 mode,
++	enum channel_width BW,
++	u8 rate);
++
++boolean
++phydm_beamforming_control_v2(
++	void *dm_void,
++	u8 idx,
++	u8 mode,
++	enum channel_width BW,
++	u16 period);
++
++void phydm_beamforming_watchdog(
++	void *dm_void);
++
++void beamforming_sw_timer_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct phydm_timer_list *timer
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	void *function_context
++#endif
++	);
++
++boolean
++beamforming_send_ht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	enum channel_width BW,
++	u8 q_idx);
++
++boolean
++beamforming_send_vht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	u16 AID,
++	enum channel_width BW,
++	u8 q_idx);
++
++#else
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
++#define beamforming_gid_paid(adapter, tcb)
++#define phydm_acting_determine(dm, type) false
++#define beamforming_enter(dm, sta_idx, my_mac_addr)
++#define beamforming_leave(dm, RA)
++#define beamforming_end_fw(dm)
++#define beamforming_control_v1(dm, RA, AID, mode, BW, rate) true
++#define beamforming_control_v2(dm, idx, mode, BW, period) true
++#define phydm_beamforming_end_sw(dm, _status)
++#define beamforming_timer_callback(dm)
++#define phydm_beamforming_init(dm)
++#define phydm_beamforming_control_v2(dm, _idx, _mode, _BW, _period) false
++#define beamforming_watchdog(dm)
++#define phydm_beamforming_watchdog(dm)
++#endif /*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/
++#endif /*@#ifdef PHYDM_BEAMFORMING_SUPPORT*/
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cck_pd.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cck_pd.c
+new file mode 100644
+index 000000000..fe9651c18
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cck_pd.c
+@@ -0,0 +1,1359 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ ************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#ifdef PHYDM_SUPPORT_CCKPD
++#ifdef PHYDM_COMPILE_CCKPD_TYPE1
++void phydm_write_cck_pd_type1(void *dm_void, u8 cca_th)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++
++	PHYDM_DBG(dm, DBG_CCKPD, "[%s] cck_cca_th=((0x%x))\n",
++		  __func__, cca_th);
++
++	odm_write_1byte(dm, R_0xa0a, cca_th);
++	cckpd_t->cur_cck_cca_thres = cca_th;
++}
++
++void phydm_set_cckpd_lv_type1(void *dm_void, enum cckpd_lv lv)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++	u8 pd_th = 0;
++
++	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
++	PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
++
++	if (cckpd_t->cck_pd_lv == lv) {
++		PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
++		return;
++	}
++
++	cckpd_t->cck_pd_lv = lv;
++	cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
++
++	if (lv == CCK_PD_LV_4)
++		pd_th = 0xed;
++	else if (lv == CCK_PD_LV_3)
++		pd_th = 0xdd;
++	else if (lv == CCK_PD_LV_2)
++		pd_th = 0xcd;
++	else if (lv == CCK_PD_LV_1)
++		pd_th = 0x83;
++	else if (lv == CCK_PD_LV_0)
++		pd_th = 0x40;
++
++	phydm_write_cck_pd_type1(dm, pd_th);
++}
++
++void phydm_cckpd_type1(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++	enum cckpd_lv lv = CCK_PD_LV_INIT;
++	boolean is_update = true;
++
++	if (dm->is_linked) {
++	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++		if (dm->rssi_min > 60) {
++			lv = CCK_PD_LV_3;
++		} else if (dm->rssi_min > 35) {
++			lv = CCK_PD_LV_2;
++		} else if (dm->rssi_min > 20) {
++			if (cckpd_t->cck_fa_ma > 500)
++				lv = CCK_PD_LV_2;
++			else if (cckpd_t->cck_fa_ma < 250)
++				lv = CCK_PD_LV_1;
++			else
++				is_update = false;
++		} else { /*RSSI < 20*/
++			lv = CCK_PD_LV_1;
++		}
++	#else /*ODM_AP*/
++		if (dig_t->cur_ig_value > 0x32)
++			lv = CCK_PD_LV_4;
++		else if (dig_t->cur_ig_value > 0x2a)
++			lv = CCK_PD_LV_3;
++		else if (dig_t->cur_ig_value > 0x24)
++			lv = CCK_PD_LV_2;
++		else
++			lv = CCK_PD_LV_1;
++	#endif
++	} else {
++		if (cckpd_t->cck_fa_ma > 1000)
++			lv = CCK_PD_LV_1;
++		else if (cckpd_t->cck_fa_ma < 500)
++			lv = CCK_PD_LV_0;
++		else
++			is_update = false;
++	}
++
++	/*[Abnormal case] =================================================*/
++	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	/*@HP 22B LPS power consumption issue & [PCIE-1596]*/
++	if (dm->hp_hw_id && dm->traffic_load == TRAFFIC_ULTRA_LOW) {
++		lv = CCK_PD_LV_0;
++		PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case1\n");
++	} else if ((dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) &&
++	    cckpd_t->cck_fa_ma > 200 && dm->rssi_min <= 20) {
++		lv = CCK_PD_LV_1;
++		cckpd_t->cck_pd_lv = lv;
++		phydm_write_cck_pd_type1(dm, 0xc3); /*@for ASUS OTA test*/
++		is_update = false;
++		PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case2\n");
++	}
++	#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++		#ifdef MCR_WIRELESS_EXTEND
++		lv = CCK_PD_LV_2;
++		cckpd_t->cck_pd_lv = lv;
++		phydm_write_cck_pd_type1(dm, 0x43);
++		is_update = false;
++		PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case3\n");
++		#endif
++	#endif
++	/*=================================================================*/
++
++	if (is_update)
++		phydm_set_cckpd_lv_type1(dm, lv);
++
++	PHYDM_DBG(dm, DBG_CCKPD, "is_linked=%d, lv=%d, pd_th=0x%x\n\n",
++		  dm->is_linked, cckpd_t->cck_pd_lv,
++		  cckpd_t->cur_cck_cca_thres);
++}
++#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE1*/
++
++#ifdef PHYDM_COMPILE_CCKPD_TYPE2
++void phydm_write_cck_pd_type2(void *dm_void, u8 cca_th, u8 cca_th_aaa)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++
++	PHYDM_DBG(dm, DBG_CCKPD, "[%s] pd_th=0x%x, cs_ratio=0x%x\n",
++		  __func__, cca_th, cca_th_aaa);
++
++	odm_set_bb_reg(dm, R_0xa08, 0x3f0000, cca_th);
++	odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, cca_th_aaa);
++	cckpd_t->cur_cck_cca_thres = cca_th;
++	cckpd_t->cck_cca_th_aaa = cca_th_aaa;
++}
++
++void phydm_set_cckpd_lv_type2(void *dm_void, enum cckpd_lv lv)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++	u8 pd_th = 0, cs_ratio = 0, cs_2r_offset = 0;
++	u8 cck_n_rx = 1;
++
++	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
++	PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
++
++	/*@r_mrx & r_cca_mrc*/
++	cck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(18)) &&
++		    odm_get_bb_reg(dm, R_0xa2c, BIT(22))) ? 2 : 1;
++
++	if (cckpd_t->cck_pd_lv == lv && cckpd_t->cck_n_rx == cck_n_rx) {
++		PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
++		return;
++	}
++
++	cckpd_t->cck_n_rx = cck_n_rx;
++	cckpd_t->cck_pd_lv = lv;
++	cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
++
++	if (lv == CCK_PD_LV_4) {
++		cs_ratio = cckpd_t->aaa_default + 8;
++		cs_2r_offset = 5;
++		pd_th = 0xd;
++	} else if (lv == CCK_PD_LV_3) {
++		cs_ratio = cckpd_t->aaa_default + 6;
++		cs_2r_offset = 4;
++		pd_th = 0xd;
++	} else if (lv == CCK_PD_LV_2) {
++		cs_ratio = cckpd_t->aaa_default + 4;
++		cs_2r_offset = 3;
++		pd_th = 0xd;
++	} else if (lv == CCK_PD_LV_1) {
++		cs_ratio = cckpd_t->aaa_default + 2;
++		cs_2r_offset = 1;
++		pd_th = 0x7;
++	} else if (lv == CCK_PD_LV_0) {
++		cs_ratio = cckpd_t->aaa_default;
++		cs_2r_offset = 0;
++		pd_th = 0x3;
++	}
++
++	if (cckpd_t->cck_n_rx == 2) {
++		if (cs_ratio >= cs_2r_offset)
++			cs_ratio = cs_ratio - cs_2r_offset;
++		else
++			cs_ratio = 0;
++	}
++	phydm_write_cck_pd_type2(dm, pd_th, cs_ratio);
++}
++
++void phydm_cckpd_type2(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++	enum cckpd_lv lv = CCK_PD_LV_INIT;
++	u8 igi = dig_t->cur_ig_value;
++	u8 rssi_min = dm->rssi_min;
++	boolean is_update = true;
++
++	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
++
++	if (dm->is_linked) {
++		if (igi > 0x38 && rssi_min > 32) {
++			lv = CCK_PD_LV_4;
++		} else if (igi > 0x2a && rssi_min > 32) {
++			lv = CCK_PD_LV_3;
++		} else if (igi > 0x24 || (rssi_min > 24 && rssi_min <= 30)) {
++			lv = CCK_PD_LV_2;
++		} else if (igi <= 0x24 || rssi_min < 22) {
++			if (cckpd_t->cck_fa_ma > 1000) {
++				lv = CCK_PD_LV_1;
++			} else if (cckpd_t->cck_fa_ma < 500) {
++				lv = CCK_PD_LV_0;
++			} else {
++				is_update = false;
++			}
++		} else {
++			is_update = false;
++		}
++	} else {
++		if (cckpd_t->cck_fa_ma > 1000) {
++			lv = CCK_PD_LV_1;
++		} else if (cckpd_t->cck_fa_ma < 500) {
++			lv = CCK_PD_LV_0;
++		} else {
++			is_update = false;
++		}
++	}
++
++	/*[Abnormal case] =================================================*/
++	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	/*@21C Miracast lag issue & [PCIE-3298]*/
++	if (dm->support_ic_type & ODM_RTL8821C && rssi_min > 60) {
++		lv = CCK_PD_LV_4;
++		cckpd_t->cck_pd_lv = lv;
++		phydm_write_cck_pd_type2(dm, 0x1d, (cckpd_t->aaa_default + 8));
++		is_update = false;
++		PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case1\n");
++	}
++	#endif
++	/*=================================================================*/
++
++	if (is_update) {
++		phydm_set_cckpd_lv_type2(dm, lv);
++	}
++
++	PHYDM_DBG(dm, DBG_CCKPD,
++		  "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x\n\n",
++		  dm->is_linked, cckpd_t->cck_pd_lv, cckpd_t->cck_n_rx,
++		  cckpd_t->cck_cca_th_aaa, cckpd_t->cur_cck_cca_thres);
++}
++#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE2*/
++
++#ifdef PHYDM_COMPILE_CCKPD_TYPE3
++void phydm_write_cck_pd_type3(void *dm_void, u8 pd_th, u8 cs_ratio,
++			      enum cckpd_mode mode)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++
++	PHYDM_DBG(dm, DBG_CCKPD,
++		  "[%s] mode=%d, pd_th=0x%x, cs_ratio=0x%x\n", __func__,
++		  mode, pd_th, cs_ratio);
++
++	switch (mode) {
++	case CCK_BW20_1R: /*RFBW20_1R*/
++	{
++		cckpd_t->cur_cck_pd_20m_1r = pd_th;
++		cckpd_t->cur_cck_cs_ratio_20m_1r = cs_ratio;
++		odm_set_bb_reg(dm, R_0xac8, 0xff, pd_th);
++		odm_set_bb_reg(dm, R_0xad0, 0x1f, cs_ratio);
++	} break;
++	case CCK_BW20_2R: /*RFBW20_2R*/
++	{
++		cckpd_t->cur_cck_pd_20m_2r = pd_th;
++		cckpd_t->cur_cck_cs_ratio_20m_2r = cs_ratio;
++		odm_set_bb_reg(dm, R_0xac8, 0xff00, pd_th);
++		odm_set_bb_reg(dm, R_0xad0, 0x3e0, cs_ratio);
++	} break;
++	case CCK_BW40_1R: /*RFBW40_1R*/
++	{
++		cckpd_t->cur_cck_pd_40m_1r = pd_th;
++		cckpd_t->cur_cck_cs_ratio_40m_1r = cs_ratio;
++		odm_set_bb_reg(dm, R_0xacc, 0xff, pd_th);
++		odm_set_bb_reg(dm, R_0xad0, 0x1f00000, cs_ratio);
++	} break;
++	case CCK_BW40_2R: /*RFBW40_2R*/
++	{
++		cckpd_t->cur_cck_pd_40m_2r = pd_th;
++		cckpd_t->cur_cck_cs_ratio_40m_2r = cs_ratio;
++		odm_set_bb_reg(dm, R_0xacc, 0xff00, pd_th);
++		odm_set_bb_reg(dm, R_0xad0, 0x3e000000, cs_ratio);
++	} break;
++
++	default:
++		/*@pr_debug("[%s] warning!\n", __func__);*/
++		break;
++	}
++}
++
++void phydm_set_cckpd_lv_type3(void *dm_void, enum cckpd_lv lv)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++	enum cckpd_mode cck_mode = CCK_BW20_2R;
++	enum channel_width cck_bw = CHANNEL_WIDTH_20;
++	u8 cck_n_rx = 1;
++	u8 pd_th;
++	u8 cs_ratio;
++
++	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
++	PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
++
++	/*[Check Nrx]*/
++	cck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(17))) ? 2 : 1;
++
++	/*[Check BW]*/
++	if (odm_get_bb_reg(dm, R_0x800, BIT(0)))
++		cck_bw = CHANNEL_WIDTH_40;
++	else
++		cck_bw = CHANNEL_WIDTH_20;
++
++	/*[Check LV]*/
++	if (cckpd_t->cck_pd_lv == lv &&
++	    cckpd_t->cck_n_rx == cck_n_rx &&
++	    cckpd_t->cck_bw == cck_bw) {
++		PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
++		return;
++	}
++
++	cckpd_t->cck_bw = cck_bw;
++	cckpd_t->cck_n_rx = cck_n_rx;
++	cckpd_t->cck_pd_lv = lv;
++	cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
++
++	if (cck_n_rx == 2) {
++		if (cck_bw == CHANNEL_WIDTH_20) {
++			pd_th = cckpd_t->cck_pd_20m_2r;
++			cs_ratio = cckpd_t->cck_cs_ratio_20m_2r;
++			cck_mode = CCK_BW20_2R;
++		} else {
++			pd_th = cckpd_t->cck_pd_40m_2r;
++			cs_ratio = cckpd_t->cck_cs_ratio_40m_2r;
++			cck_mode = CCK_BW40_2R;
++		}
++	} else {
++		if (cck_bw == CHANNEL_WIDTH_20) {
++			pd_th = cckpd_t->cck_pd_20m_1r;
++			cs_ratio = cckpd_t->cck_cs_ratio_20m_1r;
++			cck_mode = CCK_BW20_1R;
++		} else {
++			pd_th = cckpd_t->cck_pd_40m_1r;
++			cs_ratio = cckpd_t->cck_cs_ratio_40m_1r;
++			cck_mode = CCK_BW40_1R;
++		}
++	}
++
++	if (lv == CCK_PD_LV_4) {
++		if (cck_n_rx == 2) {
++			pd_th += 4;
++			cs_ratio += 2;
++		} else {
++			pd_th += 4;
++			cs_ratio += 3;
++		}
++	} else if (lv == CCK_PD_LV_3) {
++		if (cck_n_rx == 2) {
++			pd_th += 3;
++			cs_ratio += 1;
++		} else {
++			pd_th += 3;
++			cs_ratio += 2;
++		}
++	} else if (lv == CCK_PD_LV_2) {
++		pd_th += 2;
++		cs_ratio += 1;
++	} else if (lv == CCK_PD_LV_1) {
++		pd_th += 1;
++		cs_ratio += 1;
++	}
++
++	phydm_write_cck_pd_type3(dm, pd_th, cs_ratio, cck_mode);
++}
++
++void phydm_cckpd_type3(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++	enum cckpd_lv lv = CCK_PD_LV_INIT;
++	u8 igi = dm->dm_dig_table.cur_ig_value;
++	boolean is_update = true;
++	u8 pd_th = 0;
++	u8 cs_ratio = 0;
++
++	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
++
++	if (dm->is_linked) {
++		if (igi > 0x38 && dm->rssi_min > 32) {
++			lv = CCK_PD_LV_4;
++		} else if ((igi > 0x2a) && (dm->rssi_min > 32)) {
++			lv = CCK_PD_LV_3;
++		} else if ((igi > 0x24) ||
++			   (dm->rssi_min > 24 && dm->rssi_min <= 30)) {
++			lv = CCK_PD_LV_2;
++		} else if ((igi <= 0x24) || (dm->rssi_min < 22)) {
++			if (cckpd_t->cck_fa_ma > 1000)
++				lv = CCK_PD_LV_1;
++			else if (cckpd_t->cck_fa_ma < 500)
++				lv = CCK_PD_LV_0;
++			else
++				is_update = false;
++		}
++	} else {
++		if (cckpd_t->cck_fa_ma > 1000)
++			lv = CCK_PD_LV_1;
++		else if (cckpd_t->cck_fa_ma < 500)
++			lv = CCK_PD_LV_0;
++		else
++			is_update = false;
++	}
++
++	if (is_update)
++		phydm_set_cckpd_lv_type3(dm, lv);
++
++	if (cckpd_t->cck_n_rx == 2) {
++		if (cckpd_t->cck_bw == CHANNEL_WIDTH_20) {
++			pd_th = cckpd_t->cur_cck_pd_20m_2r;
++			cs_ratio = cckpd_t->cur_cck_cs_ratio_20m_2r;
++		} else {
++			pd_th = cckpd_t->cur_cck_pd_40m_2r;
++			cs_ratio = cckpd_t->cur_cck_cs_ratio_40m_2r;
++		}
++	} else {
++		if (cckpd_t->cck_bw == CHANNEL_WIDTH_20) {
++			pd_th = cckpd_t->cur_cck_pd_20m_1r;
++			cs_ratio = cckpd_t->cur_cck_cs_ratio_20m_1r;
++		} else {
++			pd_th = cckpd_t->cur_cck_pd_40m_1r;
++			cs_ratio = cckpd_t->cur_cck_cs_ratio_40m_1r;
++		}
++	}
++	PHYDM_DBG(dm, DBG_CCKPD,
++		  "[%dR][%dM] is_linked=%d, lv=%d, cs_ratio=0x%x, pd_th=0x%x\n\n",
++		  cckpd_t->cck_n_rx, 20 << cckpd_t->cck_bw, dm->is_linked,
++		  cckpd_t->cck_pd_lv, cs_ratio, pd_th);
++}
++
++void phydm_cck_pd_init_type3(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++	u32 reg_tmp = 0;
++
++	/*Get Default value*/
++	cckpd_t->cck_pd_20m_1r = (u8)odm_get_bb_reg(dm, R_0xac8, 0xff);
++	cckpd_t->cck_pd_20m_2r = (u8)odm_get_bb_reg(dm, R_0xac8, 0xff00);
++	cckpd_t->cck_pd_40m_1r = (u8)odm_get_bb_reg(dm, R_0xacc, 0xff);
++	cckpd_t->cck_pd_40m_2r = (u8)odm_get_bb_reg(dm, R_0xacc, 0xff00);
++
++	reg_tmp = odm_get_bb_reg(dm, R_0xad0, MASKDWORD);
++	cckpd_t->cck_cs_ratio_20m_1r = (u8)(reg_tmp & 0x1f);
++	cckpd_t->cck_cs_ratio_20m_2r = (u8)((reg_tmp & 0x3e0) >> 5);
++	cckpd_t->cck_cs_ratio_40m_1r = (u8)((reg_tmp & 0x1f00000) >> 20);
++	cckpd_t->cck_cs_ratio_40m_2r = (u8)((reg_tmp & 0x3e000000) >> 25);
++}
++#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE3*/
++
++#ifdef PHYDM_COMPILE_CCKPD_TYPE4
++void phydm_write_cck_pd_type4(void *dm_void, enum cckpd_lv lv,
++			      enum cckpd_mode mode)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++	u32 val = 0;
++
++	PHYDM_DBG(dm, DBG_CCKPD, "write CCK CCA parameters(CS_ratio & PD)\n");
++	switch (mode) {
++	case CCK_BW20_1R: /*RFBW20_1R*/
++	{
++		val = cckpd_t->cckpd_jgr3[0][0][0][lv];
++		odm_set_bb_reg(dm, R_0x1ac8, 0xff, val);
++		val = cckpd_t->cckpd_jgr3[0][0][1][lv];
++		odm_set_bb_reg(dm, R_0x1ad0, 0x1f, val);
++	} break;
++	case CCK_BW40_1R: /*RFBW40_1R*/
++	{
++		val = cckpd_t->cckpd_jgr3[1][0][0][lv];
++		odm_set_bb_reg(dm, R_0x1acc, 0xff, val);
++		val = cckpd_t->cckpd_jgr3[1][0][1][lv];
++		odm_set_bb_reg(dm, R_0x1ad0, 0x01F00000, val);
++	} break;
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	case CCK_BW20_2R: /*RFBW20_2R*/
++	{
++		val = cckpd_t->cckpd_jgr3[0][1][0][lv];
++		odm_set_bb_reg(dm, R_0x1ac8, 0xff00, val);
++		val = cckpd_t->cckpd_jgr3[0][1][1][lv];
++		odm_set_bb_reg(dm, R_0x1ad0, 0x3e0, val);
++	} break;
++	case CCK_BW40_2R: /*RFBW40_2R*/
++	{
++		val = cckpd_t->cckpd_jgr3[1][1][0][lv];
++		odm_set_bb_reg(dm, R_0x1acc, 0xff00, val);
++		val = cckpd_t->cckpd_jgr3[1][1][1][lv];
++		odm_set_bb_reg(dm, R_0x1ad0, 0x3E000000, val);
++	} break;
++	#endif
++	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++	case CCK_BW20_3R: /*RFBW20_3R*/
++	{
++		val = cckpd_t->cckpd_jgr3[0][2][0][lv];
++		odm_set_bb_reg(dm, R_0x1ac8, 0xff0000, val);
++		val = cckpd_t->cckpd_jgr3[0][2][1][lv];
++		odm_set_bb_reg(dm, R_0x1ad0, 0x7c00, val);
++	} break;
++	case CCK_BW40_3R: /*RFBW40_3R*/
++	{
++		val = cckpd_t->cckpd_jgr3[1][2][0][lv];
++		odm_set_bb_reg(dm, R_0x1acc, 0xff0000, val);
++		val = cckpd_t->cckpd_jgr3[1][2][1][lv] & 0x3;
++		odm_set_bb_reg(dm, R_0x1ad0, 0xC0000000, val);
++		val = (cckpd_t->cckpd_jgr3[1][2][1][lv] & 0x1c) >> 2;
++		odm_set_bb_reg(dm, R_0x1ad4, 0x7, val);
++	} break;
++	#endif
++	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	case CCK_BW20_4R: /*RFBW20_4R*/
++	{
++		val = cckpd_t->cckpd_jgr3[0][3][0][lv];
++		odm_set_bb_reg(dm, R_0x1ac8, 0xff000000, val);
++		val = cckpd_t->cckpd_jgr3[0][3][1][lv];
++		odm_set_bb_reg(dm, R_0x1ad0, 0xF8000, val);
++	} break;
++	case CCK_BW40_4R: /*RFBW40_4R*/
++	{
++		val = cckpd_t->cckpd_jgr3[1][3][0][lv];
++		odm_set_bb_reg(dm, R_0x1acc, 0xff000000, val);
++		val = cckpd_t->cckpd_jgr3[1][3][1][lv];
++		odm_set_bb_reg(dm, R_0x1ad4, 0xf8, val);
++	} break;
++	#endif
++	default:
++		/*@pr_debug("[%s] warning!\n", __func__);*/
++		break;
++	}
++}
++
++void phydm_set_cck_pd_lv_type4(void *dm_void, enum cckpd_lv lv)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++	enum cckpd_mode cck_mode = CCK_BW20_2R;
++	enum channel_width cck_bw = CHANNEL_WIDTH_20;
++	u8 cck_n_rx = 0;
++	u32 val = 0;
++	/*u32 val_dbg = 0;*/
++
++	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
++	PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
++
++	/*[Check Nrx]*/
++	cck_n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;
++
++	/*[Check BW]*/
++	val = odm_get_bb_reg(dm, R_0x9b0, 0xc);
++	if (val == 0)
++		cck_bw = CHANNEL_WIDTH_20;
++	else if (val == 1)
++		cck_bw = CHANNEL_WIDTH_40;
++	else
++		cck_bw = CHANNEL_WIDTH_80;
++
++	/*[Check LV]*/
++	if (cckpd_t->cck_pd_lv == lv &&
++	    cckpd_t->cck_n_rx == cck_n_rx &&
++	    cckpd_t->cck_bw == cck_bw) {
++		PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
++		return;
++	}
++
++	cckpd_t->cck_bw = cck_bw;
++	cckpd_t->cck_n_rx = cck_n_rx;
++	cckpd_t->cck_pd_lv = lv;
++	cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
++
++	switch (cck_n_rx) {
++	case 1: /*1R*/
++	{
++		if (cck_bw == CHANNEL_WIDTH_20)
++			cck_mode = CCK_BW20_1R;
++		else if (cck_bw == CHANNEL_WIDTH_40)
++			cck_mode = CCK_BW40_1R;
++	} break;
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	case 2: /*2R*/
++	{
++		if (cck_bw == CHANNEL_WIDTH_20)
++			cck_mode = CCK_BW20_2R;
++		else if (cck_bw == CHANNEL_WIDTH_40)
++			cck_mode = CCK_BW40_2R;
++	} break;
++	#endif
++	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++	case 3: /*3R*/
++	{
++		if (cck_bw == CHANNEL_WIDTH_20)
++			cck_mode = CCK_BW20_3R;
++		else if (cck_bw == CHANNEL_WIDTH_40)
++			cck_mode = CCK_BW40_3R;
++	} break;
++	#endif
++	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	case 4: /*4R*/
++	{
++		if (cck_bw == CHANNEL_WIDTH_20)
++			cck_mode = CCK_BW20_4R;
++		else if (cck_bw == CHANNEL_WIDTH_40)
++			cck_mode = CCK_BW40_4R;
++	} break;
++	#endif
++	default:
++		/*@pr_debug("[%s] warning!\n", __func__);*/
++		break;
++	}
++	phydm_write_cck_pd_type4(dm, lv, cck_mode);
++}
++
++void phydm_read_cckpd_para_type4(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++	u8 bw = 0; /*r_RX_RF_BW*/
++	u8 n_rx = 0;
++	u8 curr_cck_pd_t[2][4][2];
++	u32 reg0 = 0;
++	u32 reg1 = 0;
++	u32 reg2 = 0;
++	u32 reg3 = 0;
++
++	if (!(dm->debug_components & DBG_CCKPD))
++		return;
++
++	bw = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc);
++	n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;
++
++	reg0 = odm_get_bb_reg(dm, R_0x1ac8, MASKDWORD);
++	reg1 = odm_get_bb_reg(dm, R_0x1acc, MASKDWORD);
++	reg2 = odm_get_bb_reg(dm, R_0x1ad0, MASKDWORD);
++	reg3 = odm_get_bb_reg(dm, R_0x1ad4, MASKDWORD);
++	curr_cck_pd_t[0][0][0] = (u8)(reg0 & 0x000000ff);
++	curr_cck_pd_t[1][0][0] = (u8)(reg1 & 0x000000ff);
++	curr_cck_pd_t[0][0][1] = (u8)(reg2 & 0x0000001f);
++	curr_cck_pd_t[1][0][1] = (u8)((reg2 & 0x01f00000) >> 20);
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
++		curr_cck_pd_t[0][1][0] = (u8)((reg0 & 0x0000ff00) >> 8);
++		curr_cck_pd_t[1][1][0] = (u8)((reg1 & 0x0000ff00) >> 8);
++		curr_cck_pd_t[0][1][1] = (u8)((reg2 & 0x000003E0) >> 5);
++		curr_cck_pd_t[1][1][1] = (u8)((reg2 & 0x3E000000) >> 25);
++	}
++	#endif
++	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++	if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) {
++		curr_cck_pd_t[0][2][0] = (u8)((reg0 & 0x00ff0000) >> 16);
++		curr_cck_pd_t[1][2][0] = (u8)((reg1 & 0x00ff0000) >> 16);
++		curr_cck_pd_t[0][2][1] = (u8)((reg2 & 0x00007C00) >> 10);
++		curr_cck_pd_t[1][2][1] = (u8)((reg2 & 0xC0000000) >> 30) |
++					 (u8)((reg3 & 0x00000007) << 3);
++	}
++	#endif
++	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
++		curr_cck_pd_t[0][3][0] = (u8)((reg0 & 0xff000000) >> 24);
++		curr_cck_pd_t[1][3][0] = (u8)((reg1 & 0xff000000) >> 24);
++		curr_cck_pd_t[0][3][1] = (u8)((reg2 & 0x000F8000) >> 15);
++		curr_cck_pd_t[1][3][1] = (u8)((reg3 & 0x000000F8) >> 3);
++	}
++	#endif
++
++	PHYDM_DBG(dm, DBG_CCKPD, "bw=%dM, Nrx=%d\n", 20 << bw, n_rx);
++	PHYDM_DBG(dm, DBG_CCKPD, "lv=%d, readback CS_th=0x%x, PD th=0x%x\n",
++		  cckpd_t->cck_pd_lv,
++		  curr_cck_pd_t[bw][n_rx - 1][1],
++		  curr_cck_pd_t[bw][n_rx - 1][0]);
++}
++
++void phydm_cckpd_type4(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++	u8 igi = dm->dm_dig_table.cur_ig_value;
++	enum cckpd_lv lv = 0;
++	boolean is_update = true;
++
++	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
++
++	if (dm->is_linked) {
++		PHYDM_DBG(dm, DBG_CCKPD, "Linked!!!\n");
++		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++		if (dm->rssi_min > 40) {
++			lv = CCK_PD_LV_4;
++			PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n");
++		} else if (dm->rssi_min > 32) {
++			lv = CCK_PD_LV_3;
++			PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n");
++		} else if (dm->rssi_min > 24) {
++			lv = CCK_PD_LV_2;
++			PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n");
++		} else {
++			if (cckpd_t->cck_fa_ma > 1000) {
++				lv = CCK_PD_LV_1;
++				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-1\n");
++			} else if (cckpd_t->cck_fa_ma < 500) {
++				lv = CCK_PD_LV_0;
++				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-2\n");
++			} else {
++				is_update = false;
++				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-3\n");
++			}
++		}
++		#else /*ODM_AP*/
++		if (igi > 0x38 && dm->rssi_min > 32) {
++			lv = CCK_PD_LV_4;
++			PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n");
++		} else if (igi > 0x2a && dm->rssi_min > 32) {
++			lv = CCK_PD_LV_3;
++			PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n");
++		} else if (igi > 0x24 || dm->rssi_min > 24) {
++			lv = CCK_PD_LV_2;
++			PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n");
++		} else {
++			if (cckpd_t->cck_fa_ma > 1000) {
++				lv = CCK_PD_LV_1;
++				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-1\n");
++			} else if (cckpd_t->cck_fa_ma < 500) {
++				lv = CCK_PD_LV_0;
++				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-2\n");
++			} else {
++				is_update = false;
++				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-3\n");
++			}
++		}
++		#endif
++	} else {
++		PHYDM_DBG(dm, DBG_CCKPD, "UnLinked!!!\n");
++		if (cckpd_t->cck_fa_ma > 1000) {
++			lv = CCK_PD_LV_1;
++			PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n");
++		} else if (cckpd_t->cck_fa_ma < 500) {
++			lv = CCK_PD_LV_0;
++			PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n");
++		} else {
++			is_update = false;
++			PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n");
++		}
++	}
++
++	if (is_update) {
++		phydm_set_cck_pd_lv_type4(dm, lv);
++
++		PHYDM_DBG(dm, DBG_CCKPD, "setting CS_th = 0x%x, PD th = 0x%x\n",
++			  cckpd_t->cckpd_jgr3[cckpd_t->cck_bw]
++			  [cckpd_t->cck_n_rx - 1][1][lv],
++			  cckpd_t->cckpd_jgr3[cckpd_t->cck_bw]
++			  [cckpd_t->cck_n_rx - 1][0][lv]);
++	}
++	phydm_read_cckpd_para_type4(dm);
++}
++
++void phydm_cck_pd_init_type4(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++	u32 reg0 = 0;
++	u32 reg1 = 0;
++	u32 reg2 = 0;
++	u32 reg3 = 0;
++	u8 pw_step = 0;
++	u8 cs_step = 0;
++	u8 cck_bw = 0; /*r_RX_RF_BW*/
++	u8 cck_n_rx = 0;
++	u8 val = 0;
++	u8 i = 0;
++
++	PHYDM_DBG(dm, DBG_CCKPD, "[%s]======>\n", __func__);
++
++	#if 0
++	/*@
++	 *cckpd_t[0][0][0][0] =  1ac8[7:0]	r_PD_lim_RFBW20_1R
++	 *cckpd_t[0][1][0][0] =  1ac8[15:8]	r_PD_lim_RFBW20_2R
++	 *cckpd_t[0][2][0][0] =  1ac8[23:16]	r_PD_lim_RFBW20_3R
++	 *cckpd_t[0][3][0][0] =  1ac8[31:24]	r_PD_lim_RFBW20_4R
++	 *cckpd_t[1][0][0][0] =  1acc[7:0]	r_PD_lim_RFBW40_1R
++	 *cckpd_t[1][1][0][0] =  1acc[15:8]	r_PD_lim_RFBW40_2R
++	 *cckpd_t[1][2][0][0] =  1acc[23:16]	r_PD_lim_RFBW40_3R
++	 *cckpd_t[1][3][0][0] =  1acc[31:24]	r_PD_lim_RFBW40_4R
++	 *
++	 *
++	 *cckpd_t[0][0][1][0] =  1ad0[4:0]	r_CS_ratio_RFBW20_1R[4:0]
++	 *cckpd_t[0][1][1][0] =  1ad0[9:5]	r_CS_ratio_RFBW20_2R[4:0]
++	 *cckpd_t[0][2][1][0] =  1ad0[14:10]	r_CS_ratio_RFBW20_3R[4:0]
++	 *cckpd_t[0][3][1][0] =  1ad0[19:15]	r_CS_ratio_RFBW20_4R[4:0]
++	 *cckpd_t[1][0][1][0] =  1ad0[24:20]	r_CS_ratio_RFBW40_1R[4:0]
++	 *cckpd_t[1][1][1][0] =  1ad0[29:25]	r_CS_ratio_RFBW40_2R[4:0]
++	 *cckpd_t[1][2][1][0] =  1ad0[31:30]	r_CS_ratio_RFBW40_3R[1:0]
++	 *			 1ad4[2:0]	r_CS_ratio_RFBW40_3R[4:2]
++	 *cckpd_t[1][3][1][0] =  1ad4[7:3]	r_CS_ratio_RFBW40_4R[4:0]
++	 */
++	#endif
++	/*[Check Nrx]*/
++	cck_n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;
++
++	/*[Check BW]*/
++	val = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc);
++	if (val == 0)
++		cck_bw = CHANNEL_WIDTH_20;
++	else if (val == 1)
++		cck_bw = CHANNEL_WIDTH_40;
++	else
++		cck_bw = CHANNEL_WIDTH_80;
++
++	cckpd_t->cck_bw = cck_bw;
++	cckpd_t->cck_n_rx = cck_n_rx;
++	reg0 = odm_get_bb_reg(dm, R_0x1ac8, MASKDWORD);
++	reg1 = odm_get_bb_reg(dm, R_0x1acc, MASKDWORD);
++	reg2 = odm_get_bb_reg(dm, R_0x1ad0, MASKDWORD);
++	reg3 = odm_get_bb_reg(dm, R_0x1ad4, MASKDWORD);
++
++	for (i = 0 ; i < CCK_PD_LV_MAX ; i++) {
++		pw_step = i * 2;
++		cs_step = i * 2;
++
++		#if (RTL8197G_SUPPORT)
++		if (dm->support_ic_type & ODM_RTL8197G) {
++			pw_step = i;
++			cs_step = i;
++			if (i > CCK_PD_LV_3) {
++				pw_step = 3;
++				cs_step = 3;
++			}
++		}
++		#endif
++
++		#if (RTL8822C_SUPPORT)
++		if (dm->support_ic_type & ODM_RTL8822C) {
++			if (i == CCK_PD_LV_1) {
++				pw_step = 9; /*IGI-19.2:0x11=d'17*/
++				cs_step = 1;
++			} else if (i == CCK_PD_LV_2) {
++				pw_step = 12; /*IGI-15.5:0x14=d'20*/
++				cs_step = 2;
++			} else if (i == CCK_PD_LV_3) {
++				pw_step = 14; /*IGI-14:0x16=d'22*/
++				cs_step = 3;
++			} else if (i == CCK_PD_LV_4) {
++				pw_step = 17; /*IGI-12:0x19=d'25*/
++				cs_step = 3;
++			}
++		}
++		#endif
++		
++		val = (u8)(reg0 & 0x000000ff) + pw_step;
++		PHYDM_DBG(dm, DBG_CCKPD, "lvl %d val = %x\n\n", i, val);
++		cckpd_t->cckpd_jgr3[0][0][0][i] = val;
++
++		val = (u8)(reg1 & 0x000000ff) + pw_step;
++		cckpd_t->cckpd_jgr3[1][0][0][i] = val;
++
++		val = (u8)(reg2 & 0x0000001f) + cs_step;
++		cckpd_t->cckpd_jgr3[0][0][1][i] = val;
++
++		val = (u8)((reg2 & 0x01f00000) >> 20) + cs_step;
++		cckpd_t->cckpd_jgr3[1][0][1][i] = val;
++
++		#ifdef PHYDM_COMPILE_ABOVE_2SS
++		if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
++			val = (u8)((reg0 & 0x0000ff00) >> 8) + pw_step;
++			cckpd_t->cckpd_jgr3[0][1][0][i] = val;
++
++			val = (u8)((reg1 & 0x0000ff00) >> 8) + pw_step;
++			cckpd_t->cckpd_jgr3[1][1][0][i] = val;
++
++			val = (u8)((reg2 & 0x000003e0) >> 5) + cs_step;
++			cckpd_t->cckpd_jgr3[0][1][1][i] = val;
++
++			val = (u8)((reg2 & 0x3e000000) >> 25) + cs_step;
++			cckpd_t->cckpd_jgr3[1][1][1][i] = val;
++		}
++		#endif
++
++		#ifdef PHYDM_COMPILE_ABOVE_3SS
++		if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) {
++			val = (u8)((reg0 & 0x00ff0000) >> 16) + pw_step;
++			cckpd_t->cckpd_jgr3[0][2][0][i] = val;
++
++			val = (u8)((reg1 & 0x00ff0000) >> 16) + pw_step;
++			cckpd_t->cckpd_jgr3[1][2][0][i] = val;
++			val = (u8)((reg2 & 0x00007c00) >> 10) + cs_step;
++			cckpd_t->cckpd_jgr3[0][2][1][i] = val;
++			val = (u8)(((reg2 & 0xc0000000) >> 30) |
++			      ((reg3 & 0x7) << 3)) + cs_step;
++			cckpd_t->cckpd_jgr3[1][2][1][i] = val;
++		}
++		#endif
++
++		#ifdef PHYDM_COMPILE_ABOVE_4SS
++		if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
++			val = (u8)((reg0 & 0xff000000) >> 24) + pw_step;
++			cckpd_t->cckpd_jgr3[0][3][0][i] = val;
++
++			val = (u8)((reg1 & 0xff000000) >> 24) + pw_step;
++			cckpd_t->cckpd_jgr3[1][3][0][i] = val;
++
++			val = (u8)((reg2 & 0x000f8000) >> 15) + cs_step;
++			cckpd_t->cckpd_jgr3[0][3][1][i] = val;
++
++			val = (u8)((reg3 & 0x000000f8) >> 3) + cs_step;
++			cckpd_t->cckpd_jgr3[1][3][1][i] = val;
++		}
++		#endif
++	}
++}
++
++void phydm_invalid_cckpd_type4(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++	u8 val = 0;
++	u8 i = 0;
++	u8 j = 0;
++	u8 k = 0;
++
++	PHYDM_DBG(dm, DBG_CCKPD, "[%s]======>\n", __func__);
++
++	for (i = 0; i < CCK_PD_LV_MAX; i++) {
++		for (j = 0; j < 2; j++) {
++			for (k = 0; k < dm->num_rf_path; k++) {
++				val = cckpd_t->cckpd_jgr3[j][k][1][i];
++				if (val == INVALID_CS_RATIO_0)
++					cckpd_t->cckpd_jgr3[j][k][1][i] = 0x1c;
++				else if (val == INVALID_CS_RATIO_1)
++					cckpd_t->cckpd_jgr3[j][k][1][i] = 0x1e;
++				else if (val > MAXVALID_CS_RATIO)
++					cckpd_t->cckpd_jgr3[j][k][1][i] =
++					MAXVALID_CS_RATIO;
++			}
++		}
++
++		#if (RTL8198F_SUPPORT)
++		if (dm->support_ic_type & ODM_RTL8198F) {
++			val = cckpd_t->cckpd_jgr3[0][3][1][i];
++			if (i == CCK_PD_LV_1 && val > 0x10)
++				cckpd_t->cckpd_jgr3[0][3][1][i] = 0x10;
++			else if (i == CCK_PD_LV_2 && val > 0x10)
++				cckpd_t->cckpd_jgr3[0][3][1][i] = 0x10;
++			else if (i == CCK_PD_LV_3 && val > 0x10)
++				cckpd_t->cckpd_jgr3[0][3][1][i] = 0x10;
++			else if (i == CCK_PD_LV_4 && val > 0x10)
++				cckpd_t->cckpd_jgr3[0][3][1][i] = 0x10;
++			val = cckpd_t->cckpd_jgr3[1][3][1][i];
++			if (i == CCK_PD_LV_1 && val > 0xF)
++				cckpd_t->cckpd_jgr3[1][3][1][i] = 0xF;
++			else if (i == CCK_PD_LV_2 && val > 0xF)
++				cckpd_t->cckpd_jgr3[1][3][1][i] = 0xF;
++			else if (i == CCK_PD_LV_3 && val > 0xF)
++				cckpd_t->cckpd_jgr3[1][3][1][i] = 0xF;
++			else if (i == CCK_PD_LV_4 && val > 0xF)
++				cckpd_t->cckpd_jgr3[1][3][1][i] = 0xF;
++		}
++		#endif
++	}
++}
++
++#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE4*/
++
++void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++	enum cckpd_lv lv;
++
++	if (val_len != 1) {
++		PHYDM_DBG(dm, ODM_COMP_API, "[Error][CCKPD]Need val_len=1\n");
++		return;
++	}
++
++	lv = (enum cckpd_lv)val_buf[0];
++
++	if (lv > CCK_PD_LV_4) {
++		pr_debug("[%s] warning! lv=%d\n", __func__, lv);
++		return;
++	}
++
++	switch (cckpd_t->cckpd_hw_type) {
++	#ifdef PHYDM_COMPILE_CCKPD_TYPE1
++	case 1:
++		phydm_set_cckpd_lv_type1(dm, lv);
++		break;
++	#endif
++	#ifdef PHYDM_COMPILE_CCKPD_TYPE2
++	case 2:
++		phydm_set_cckpd_lv_type2(dm, lv);
++		break;
++	#endif
++	#ifdef PHYDM_COMPILE_CCKPD_TYPE3
++	case 3:
++		phydm_set_cckpd_lv_type3(dm, lv);
++		break;
++	#endif
++	#ifdef PHYDM_COMPILE_CCKPD_TYPE4
++	case 4:
++		phydm_set_cck_pd_lv_type4(dm, lv);
++		break;
++	#endif
++	default:
++		pr_debug("[%s]warning\n", __func__);
++		break;
++	}
++}
++
++boolean
++phydm_stop_cck_pd_th(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (!(dm->support_ability & ODM_BB_FA_CNT)) {
++		PHYDM_DBG(dm, DBG_CCKPD, "Not Support:ODM_BB_FA_CNT disable\n");
++		return true;
++	}
++
++	if (!(dm->support_ability & ODM_BB_CCK_PD)) {
++		PHYDM_DBG(dm, DBG_CCKPD, "Not Support:ODM_BB_CCK_PD disable\n");
++		return true;
++	}
++
++	if (dm->pause_ability & ODM_BB_CCK_PD) {
++		PHYDM_DBG(dm, DBG_CCKPD, "Return: Pause CCKPD in LV=%d\n",
++			  dm->pause_lv_table.lv_cckpd);
++		return true;
++	}
++
++	if (dm->is_linked && (*dm->channel > 36)) {
++		PHYDM_DBG(dm, DBG_CCKPD, "Return: 5G CH=%d\n", *dm->channel);
++		return true;
++	}
++	return false;
++}
++
++void phydm_cck_pd_th(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++	u32 cck_fa = fa_t->cnt_cck_fail;
++	#ifdef PHYDM_TDMA_DIG_SUPPORT
++	struct phydm_fa_acc_struct *fa_acc_t = &dm->false_alm_cnt_acc;
++	#endif
++
++	PHYDM_DBG(dm, DBG_CCKPD, "[%s] ======>\n", __func__);
++
++	if (phydm_stop_cck_pd_th(dm))
++		return;
++
++	#ifdef PHYDM_TDMA_DIG_SUPPORT
++	if (dm->original_dig_restore)
++		cck_fa = fa_t->cnt_cck_fail;
++	else
++		cck_fa = fa_acc_t->cnt_cck_fail_1sec;
++	#endif
++
++	if (cckpd_t->cck_fa_ma == CCK_FA_MA_RESET)
++		cckpd_t->cck_fa_ma = cck_fa;
++	else
++		cckpd_t->cck_fa_ma = (cckpd_t->cck_fa_ma * 3 + cck_fa) >> 2;
++
++	PHYDM_DBG(dm, DBG_CCKPD,
++		  "IGI=0x%x, rssi_min=%d, cck_fa=%d, cck_fa_ma=%d\n",
++		  dm->dm_dig_table.cur_ig_value, dm->rssi_min,
++		  cck_fa, cckpd_t->cck_fa_ma);
++
++	switch (cckpd_t->cckpd_hw_type) {
++	#ifdef PHYDM_COMPILE_CCKPD_TYPE1
++	case 1:
++		phydm_cckpd_type1(dm);
++		break;
++	#endif
++	#ifdef PHYDM_COMPILE_CCKPD_TYPE2
++	case 2:
++		phydm_cckpd_type2(dm);
++		break;
++	#endif
++	#ifdef PHYDM_COMPILE_CCKPD_TYPE3
++	case 3:
++		phydm_cckpd_type3(dm);
++		break;
++	#endif
++	#ifdef PHYDM_COMPILE_CCKPD_TYPE4
++	case 4:
++		#ifdef PHYDM_DCC_ENHANCE
++		if (dm->dm_dcc_info.dcc_en)
++			phydm_cckpd_type4_dcc(dm);
++		else
++		#endif
++			phydm_cckpd_type4(dm);
++		break;
++	#endif
++	default:
++		pr_debug("[%s]warning\n", __func__);
++		break;
++	}
++}
++
++void phydm_cck_pd_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++
++	if (*dm->mp_mode)
++		return;
++
++	if (dm->support_ic_type & CCK_PD_IC_TYPE1)
++		cckpd_t->cckpd_hw_type = 1;
++	else if (dm->support_ic_type & CCK_PD_IC_TYPE2)
++		cckpd_t->cckpd_hw_type = 2;
++	else if (dm->support_ic_type & CCK_PD_IC_TYPE3)
++		cckpd_t->cckpd_hw_type = 3;
++	else if (dm->support_ic_type & CCK_PD_IC_TYPE4)
++		cckpd_t->cckpd_hw_type = 4;
++
++	PHYDM_DBG(dm, DBG_CCKPD, "[%s] cckpd_hw_type=%d\n",
++		  __func__, cckpd_t->cckpd_hw_type);
++
++	cckpd_t->cck_pd_lv = CCK_PD_LV_INIT;
++	cckpd_t->cck_n_rx = 0xff;
++	cckpd_t->cck_bw = CHANNEL_WIDTH_MAX;
++	cckpd_t->cck_fa_th[1] = 400;
++	cckpd_t->cck_fa_th[0] = 200;
++
++	switch (cckpd_t->cckpd_hw_type) {
++	#ifdef PHYDM_COMPILE_CCKPD_TYPE1
++	case 1:
++		phydm_set_cckpd_lv_type1(dm, CCK_PD_LV_1);
++		break;
++	#endif
++	#ifdef PHYDM_COMPILE_CCKPD_TYPE2
++	case 2:
++		cckpd_t->aaa_default = odm_read_1byte(dm, 0xaaa) & 0x1f;
++		phydm_set_cckpd_lv_type2(dm, CCK_PD_LV_1);
++		break;
++	#endif
++	#ifdef PHYDM_COMPILE_CCKPD_TYPE3
++	case 3:
++		phydm_cck_pd_init_type3(dm);
++		phydm_set_cckpd_lv_type3(dm, CCK_PD_LV_1);
++		break;
++	#endif
++	#ifdef PHYDM_COMPILE_CCKPD_TYPE4
++	case 4:
++		phydm_cck_pd_init_type4(dm);
++		phydm_invalid_cckpd_type4(dm);
++		phydm_set_cck_pd_lv_type4(dm, CCK_PD_LV_1);
++		break;
++	#endif
++	default:
++		pr_debug("[%s]warning\n", __func__);
++		break;
++	}
++}
++
++#ifdef PHYDM_DCC_ENHANCE
++
++void phydm_cckpd_type4_dcc(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++	enum cckpd_lv lv_curr = cckpd_t->cck_pd_lv;
++	enum phydm_cck_pd_trend trend = CCKPD_STABLE;
++	u8 th_ofst = 0;
++	u16 lv_up_th, lv_down_th;
++
++	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
++
++	if (!dm->is_linked)
++		th_ofst = 1;
++
++	lv_up_th = (cckpd_t->cck_fa_th[1]) << th_ofst;
++	lv_down_th = (cckpd_t->cck_fa_th[0]) << th_ofst;
++
++	PHYDM_DBG(dm, DBG_CCKPD, "th{Up, Down}: {%d, %d}\n",
++		  lv_up_th, lv_down_th);
++
++	if (cckpd_t->cck_fa_ma > lv_up_th) {
++		if (lv_curr <= CCK_PD_LV_3) {
++			lv_curr++;
++			trend = CCKPD_INCREASING;
++		} else {
++			lv_curr = CCK_PD_LV_4;
++		}
++	} else if (cckpd_t->cck_fa_ma < lv_down_th) {
++		if (lv_curr >= CCK_PD_LV_1) {
++			lv_curr--;
++			trend = CCKPD_DECREASING;
++		} else {
++			lv_curr = CCK_PD_LV_0;
++		}
++	}
++
++	PHYDM_DBG(dm, DBG_CCKPD, "lv: %d->%d\n", cckpd_t->cck_pd_lv, lv_curr);
++#if 1
++	if (trend != CCKPD_STABLE) {
++		phydm_set_cck_pd_lv_type4(dm, lv_curr);
++
++		PHYDM_DBG(dm, DBG_CCKPD, "setting CS_th = 0x%x, PD th = 0x%x\n",
++			  cckpd_t->cckpd_jgr3[cckpd_t->cck_bw]
++			  [cckpd_t->cck_n_rx - 1][1][lv_curr],
++			  cckpd_t->cckpd_jgr3[cckpd_t->cck_bw]
++			  [cckpd_t->cck_n_rx - 1][0][lv_curr]);
++	}
++	phydm_read_cckpd_para_type4(dm);
++#endif
++}
++
++boolean phydm_do_cckpd(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++
++	if (dig_t->igi_trend == DIG_INCREASING)
++		return false;
++
++	return true;
++}
++
++void phydm_dig_cckpd_coex(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dcc_struct	*dcc = &dm->dm_dcc_info;
++
++	if (*dm->channel > 36) {
++		phydm_dig(dm);
++		return;
++	} else if (!dcc->dcc_en) {
++		phydm_dig(dm);
++		phydm_cck_pd_th(dm);
++		return;
++	}
++
++	dcc->dig_execute_cnt++;
++	PHYDM_DBG(dm, DBG_CCKPD, "DCC_cnt: %d\n", dcc->dig_execute_cnt);
++
++	if (dcc->dig_execute_cnt % dcc->dcc_ratio) {
++		PHYDM_DBG(dm, DBG_CCKPD, "DCC: DIG\n");
++		phydm_dig(dm);
++	} else {
++		if (phydm_do_cckpd(dm)) {
++			PHYDM_DBG(dm, DBG_CCKPD, "DCC: CCKPD\n");
++			dcc->dcc_mode = DCC_CCK_PD;
++			phydm_cck_pd_th(dm);
++		} else {
++			PHYDM_DBG(dm, DBG_CCKPD, "DCC: Boost_DIG\n");
++			dcc->dcc_mode = DCC_DIG;
++			phydm_dig(dm);
++		}
++	}
++}
++
++void phydm_dig_cckpd_coex_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_dcc_struct	*dcc = &dm->dm_dcc_info;
++
++	dcc->dcc_mode = DCC_DIG;
++	dcc->dcc_en = false;
++	dcc->dig_execute_cnt = 0;
++	dcc->dcc_ratio = 2;
++}
++
++void phydm_dig_cckpd_coex_dbg(void *dm_void, char input[][16], u32 *_used,
++			      char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
++	struct phydm_dcc_struct	*dcc = &dm->dm_dcc_info;
++	char help[] = "-h";
++	u32 var[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 i = 0;
++
++	for (i = 0; i < 3; i++) {
++		if (input[i + 1])
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]);
++	}
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Enable: en {0/1}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "DCC_ratio: ratio {x}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "threshold: th {Down_th} {Up_th}\n");
++	} else if ((strcmp(input[1], "en") == 0)) {
++		dcc->dcc_en = (var[1]) ? true : false;
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "en=%d\n", dcc->dcc_en);
++	} else if ((strcmp(input[1], "ratio") == 0)) {
++		dcc->dcc_ratio = (u8)var[1];
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Ratio=%d\n", dcc->dcc_ratio);
++	} else if ((strcmp(input[1], "th") == 0)) {
++		cckpd_t->cck_fa_th[1] = (u16)var[2];
++		cckpd_t->cck_fa_th[0] = (u16)var[1];
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "th{Down, Up}: {%d, %d}\n",
++			 cckpd_t->cck_fa_th[0], cckpd_t->cck_fa_th[1]);
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++#endif
++#endif /*#ifdef PHYDM_SUPPORT_CCKPD*/
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cck_pd.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cck_pd.h
+new file mode 100644
+index 000000000..08a080c9d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cck_pd.h
+@@ -0,0 +1,192 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_CCK_PD_H__
++#define __PHYDM_CCK_PD_H__
++
++/* 2019.10.03 Revert to partIII due to idle test in WQC.*/
++#define CCK_PD_VERSION "3.9"
++
++/*@
++ * 1 ============================================================
++ * 1  Definition
++ * 1 ============================================================
++ */
++#define CCK_FA_MA_RESET 0xffffffff
++
++#define INVALID_CS_RATIO_0 0x1b /* @ only for type4 ICs*/
++#define INVALID_CS_RATIO_1 0x1d /* @ only for type4 ICs*/
++#define MAXVALID_CS_RATIO 0x1f
++/*@Run time flag of CCK_PD HW type*/
++#define CCK_PD_IC_TYPE1 (ODM_RTL8188E | ODM_RTL8812 | ODM_RTL8821 |\
++			ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8814A |\
++			ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8703B |\
++			ODM_RTL8195A | ODM_RTL8188F)
++
++#define CCK_PD_IC_TYPE2 (ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8723D |\
++			ODM_RTL8710B | ODM_RTL8195B) /*extend 0xaaa*/
++
++#define CCK_PD_IC_TYPE3 (ODM_RTL8192F | ODM_RTL8721D | ODM_RTL8710C)
++/*@extend for different bw & path*/
++
++#define CCK_PD_IC_TYPE4 ODM_IC_JGR3_SERIES /*@extend for different bw & path*/
++
++/*@Compile time flag of CCK_PD HW type*/
++#if (RTL8188E_SUPPORT || RTL8812A_SUPPORT || RTL8821A_SUPPORT ||\
++	RTL8192E_SUPPORT || RTL8723B_SUPPORT || RTL8814A_SUPPORT ||\
++	RTL8881A_SUPPORT || RTL8822B_SUPPORT || RTL8703B_SUPPORT ||\
++	RTL8195A_SUPPORT || RTL8188F_SUPPORT)
++	#define PHYDM_COMPILE_CCKPD_TYPE1 /*@only 0xa0a*/
++#endif
++
++#if (RTL8197F_SUPPORT || RTL8821C_SUPPORT || RTL8723D_SUPPORT ||\
++	RTL8710B_SUPPORT || RTL8195B_SUPPORT)
++	#define PHYDM_COMPILE_CCKPD_TYPE2 /*@extend 0xaaa*/
++#endif
++
++#if (RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
++	#define PHYDM_COMPILE_CCKPD_TYPE3 /*@extend for different & path*/
++#endif
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	#define PHYDM_COMPILE_CCKPD_TYPE4 /*@extend for different bw & path*/
++#endif
++/*@
++ * 1 ============================================================
++ * 1  enumeration
++ * 1 ============================================================
++ */
++enum cckpd_lv {
++	CCK_PD_LV_INIT = 0xff,
++	CCK_PD_LV_0 = 0,
++	CCK_PD_LV_1 = 1,
++	CCK_PD_LV_2 = 2,
++	CCK_PD_LV_3 = 3,
++	CCK_PD_LV_4 = 4,
++	CCK_PD_LV_MAX = 5
++};
++
++enum cckpd_mode {
++	CCK_BW20_1R = 0,
++	CCK_BW20_2R = 1,
++	CCK_BW20_3R = 2,
++	CCK_BW20_4R = 3,
++	CCK_BW40_1R = 4,
++	CCK_BW40_2R = 5,
++	CCK_BW40_3R = 6,
++	CCK_BW40_4R = 7
++};
++
++enum dcc_mode {
++	DCC_DIG		= 0,
++	DCC_CCK_PD	= 1
++};
++
++enum phydm_cck_pd_trend {
++	CCKPD_STABLE			= 0,
++	CCKPD_INCREASING		= 1,
++	CCKPD_DECREASING		= 2
++};
++
++/*@
++ * 1 ============================================================
++ * 1  structure
++ * 1 ============================================================
++ */
++
++#ifdef PHYDM_SUPPORT_CCKPD
++
++#ifdef PHYDM_DCC_ENHANCE
++struct phydm_dcc_struct { /*DIG CCK_PD coexistence*/
++	boolean		dcc_en;
++	enum dcc_mode	dcc_mode;
++	u32		dig_execute_cnt;
++	u8		dcc_ratio;
++};
++#endif
++
++struct phydm_cckpd_struct {
++	u8		cckpd_hw_type;
++	u8		cur_cck_cca_thres; /*@current cck_pd value 0xa0a*/
++	u32		cck_fa_ma;
++	u32		rvrt_val; /*all rvrt_val for pause API must set to u32*/
++	u8		pause_lv;
++	u8		cck_n_rx;
++	u16		cck_fa_th[2];
++	enum channel_width cck_bw;
++	enum cckpd_lv	cck_pd_lv;
++	#ifdef PHYDM_COMPILE_CCKPD_TYPE2
++	u8		cck_cca_th_aaa; /*@current cs_ratio value 0xaaa*/
++	u8		aaa_default;	/*@Init cs_ratio value - 0xaaa*/
++	#endif
++	#ifdef PHYDM_COMPILE_CCKPD_TYPE3
++	/*Default value*/
++	u8		cck_pd_20m_1r;
++	u8		cck_pd_20m_2r;
++	u8		cck_pd_40m_1r;
++	u8		cck_pd_40m_2r;
++	u8		cck_cs_ratio_20m_1r;
++	u8		cck_cs_ratio_20m_2r;
++	u8		cck_cs_ratio_40m_1r;
++	u8		cck_cs_ratio_40m_2r;
++	/*Current value*/
++	u8		cur_cck_pd_20m_1r;
++	u8		cur_cck_pd_20m_2r;
++	u8		cur_cck_pd_40m_1r;
++	u8		cur_cck_pd_40m_2r;
++	u8		cur_cck_cs_ratio_20m_1r;
++	u8		cur_cck_cs_ratio_20m_2r;
++	u8		cur_cck_cs_ratio_40m_1r;
++	u8		cur_cck_cs_ratio_40m_2r;
++	#endif
++	#ifdef PHYDM_COMPILE_CCKPD_TYPE4
++	/*@[bw][nrx][0:PD/1:CS][lv]*/
++	u8		cckpd_jgr3[2][4][2][CCK_PD_LV_MAX];
++	#endif
++};
++#endif
++
++/*@
++ * 1 ============================================================
++ * 1  function prototype
++ * 1 ============================================================
++ */
++void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len);
++
++void phydm_cck_pd_th(void *dm_void);
++
++void phydm_cck_pd_init(void *dm_void);
++
++#ifdef PHYDM_DCC_ENHANCE
++void phydm_cckpd_type4_dcc(void *dm_void);
++
++void phydm_dig_cckpd_coex(void *dm_void);
++
++void phydm_dig_cckpd_coex_init(void *dm_void);
++
++void phydm_dig_cckpd_coex_dbg(void *dm_void, char input[][16], u32 *_used,
++			      char *output, u32 *_out_len);
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cck_rx_pathdiv.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cck_rx_pathdiv.c
+new file mode 100644
+index 000000000..bbe05e3a6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cck_rx_pathdiv.c
+@@ -0,0 +1,164 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ ************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT /* @PHYDM-342*/
++void phydm_cck_rx_pathdiv_manaul(void *dm_void, boolean en_cck_rx_pathdiv)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	/* @Can not apply for 98F/14B/97G from DD YC*/
++	if (en_cck_rx_pathdiv) {
++		odm_set_bb_reg(dm, R_0x1a14, BIT(7), 0x0);
++		odm_set_bb_reg(dm, R_0x1a74, BIT(8), 0x1);
++	} else {
++		odm_set_bb_reg(dm, R_0x1a14, BIT(7), 0x1);
++		odm_set_bb_reg(dm, R_0x1a74, BIT(8), 0x0);
++	}
++}
++
++void phydm_cck_rx_pathdiv_watchdog(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
++	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
++	u8 rssi_th = 0;
++	u32 rssi_a = 0, rssi_b = 0, rssi_avg = 0;
++
++	if (!cckrx_t->en_cck_rx_pathdiv)
++		return;
++
++	rssi_a = PHYDM_DIV(cckrx_t->path_a_sum, cckrx_t->path_a_cnt);
++	rssi_b = PHYDM_DIV(cckrx_t->path_b_sum, cckrx_t->path_b_cnt);
++	rssi_avg = (rssi_a + rssi_b) >> 1;
++
++	pr_debug("Rx-A:%d, Rx-B:%d, avg:%d\n", rssi_a, rssi_b, rssi_avg);
++
++	cckrx_t->path_a_cnt = 0;
++	cckrx_t->path_a_sum = 0;
++	cckrx_t->path_b_cnt = 0;
++	cckrx_t->path_b_sum = 0;
++
++	if (fa_t->cnt_all >= 100)
++		rssi_th = cckrx_t->rssi_fa_th;
++	else
++		rssi_th = cckrx_t->rssi_th;
++
++	if (dm->phy_dbg_info.num_qry_beacon_pkt > 14 && rssi_avg <= rssi_th)
++		phydm_cck_rx_pathdiv_manaul(dm, true);
++	else
++		phydm_cck_rx_pathdiv_manaul(dm, false);
++}
++
++void phydm_cck_rx_pathdiv_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
++
++	cckrx_t->en_cck_rx_pathdiv = false;
++	cckrx_t->path_a_cnt = 0;
++	cckrx_t->path_a_sum = 0;
++	cckrx_t->path_b_cnt = 0;
++	cckrx_t->path_b_sum = 0;
++	cckrx_t->rssi_fa_th = 45;
++	cckrx_t->rssi_th = 25;
++}
++
++void phydm_process_rssi_for_cck_rx_pathdiv(void *dm_void, void *phy_info_void,
++					   void *pkt_info_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_phyinfo_struct *phy_info = NULL;
++	struct phydm_perpkt_info_struct *pktinfo = NULL;
++	struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
++
++	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
++	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
++
++	if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid))
++		return;
++
++	if (pktinfo->is_cck_rate)
++		return;
++
++	cckrx_t->path_a_sum += phy_info->rx_mimo_signal_strength[0];
++	cckrx_t->path_a_cnt++;
++
++	cckrx_t->path_b_sum += phy_info->rx_mimo_signal_strength[1];
++	cckrx_t->path_b_cnt++;
++}
++
++void phydm_cck_rx_pathdiv_dbg(void *dm_void, char input[][16], u32 *_used,
++			      char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 i = 0;
++
++	if (!(dm->support_ic_type & ODM_RTL8822C))
++		return;
++
++	for (i = 0; i < 3; i++) {
++		if (input[i + 1])
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
++	}
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "CCK rx pathdiv manual on: {1} {En}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "CCK rx pathdiv watchdog on: {2} {En}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "CCK rx pathdiv rssi_th : {3} {th} {fa_th}\n");
++	} else if (var1[0] == 1) {
++		if (var1[1] == 1)
++			phydm_cck_rx_pathdiv_manaul(dm, true);
++		else
++			phydm_cck_rx_pathdiv_manaul(dm, false);
++	} else if (var1[0] == 2) {
++		if (var1[1] == 1) {
++			cckrx_t->en_cck_rx_pathdiv = true;
++		} else {
++			cckrx_t->en_cck_rx_pathdiv = false;
++			phydm_cck_rx_pathdiv_manaul(dm, false);
++		}
++	} else if (var1[0] == 3) {
++		cckrx_t->rssi_th = (u8)var1[1];
++		cckrx_t->rssi_fa_th = (u8)var1[2];
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cck_rx_pathdiv.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cck_rx_pathdiv.h
+new file mode 100644
+index 000000000..952bcf5f9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cck_rx_pathdiv.h
+@@ -0,0 +1,67 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_CCK_RX_PATHDIV_H__
++#define __PHYDM_CCK_RX_PATHDIV_H__
++
++#define CCK_RX_PATHDIV_VERSION "1.1"
++
++/* @1 ============================================================
++ * 1  Definition
++ * 1 ============================================================
++ */
++/* @1 ============================================================
++ * 1  structure
++ * 1 ============================================================
++ */
++struct phydm_cck_rx_pathdiv {
++	boolean en_cck_rx_pathdiv;
++	u32	path_a_sum;
++	u32	path_b_sum;
++	u16	path_a_cnt;
++	u16	path_b_cnt;
++	u8	rssi_fa_th;
++	u8	rssi_th;
++};
++
++/* @1 ============================================================
++ * 1  enumeration
++ * 1 ============================================================
++ */
++
++/* @1 ============================================================
++ * 1  function prototype
++ * 1 ============================================================
++ */
++void phydm_cck_rx_pathdiv_watchdog(void *dm_void);
++
++void phydm_cck_rx_pathdiv_init(void *dm_void);
++
++void phydm_process_rssi_for_cck_rx_pathdiv(void *dm_void, void *phy_info_void,
++					   void *pkt_info_void);
++
++void phydm_cck_rx_pathdiv_dbg(void *dm_void, char input[][16], u32 *_used,
++			      char *output, u32 *_out_len);
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_ccx.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_ccx.c
+new file mode 100644
+index 000000000..3766e2a1a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_ccx.c
+@@ -0,0 +1,1951 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++void phydm_ccx_hw_restart(void *dm_void)
++			  /*@Will Restart NHM/CLM/FAHM simultaneously*/
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 reg1 = 0;
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
++		reg1 = R_0x994;
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		reg1 = R_0x1e60;
++	#endif
++	else
++		reg1 = R_0x890;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++	/*@disable NHM,CLM, FAHM*/
++	odm_set_bb_reg(dm, reg1, 0x7, 0x0);
++	odm_set_bb_reg(dm, reg1, BIT(8), 0x0);
++	odm_set_bb_reg(dm, reg1, BIT(8), 0x1);
++}
++
++#ifdef FAHM_SUPPORT
++
++u16 phydm_hw_divider(void *dm_void, u16 numerator, u16 denumerator)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u16 result = DEVIDER_ERROR;
++	u32 tmp_u32 = ((numerator << 16) | denumerator);
++	u32 reg_devider_input;
++	u32 reg;
++	u8 i;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		reg_devider_input = 0x1cbc;
++		reg = 0x1f98;
++	} else {
++		reg_devider_input = 0x980;
++		reg = 0x9f0;
++	}
++
++	odm_set_bb_reg(dm, reg_devider_input, MASKDWORD, tmp_u32);
++
++	for (i = 0; i < 10; i++) {
++		ODM_delay_ms(1);
++		if (odm_get_bb_reg(dm, reg, BIT(24))) {
++		/*@Chk HW rpt is ready*/
++
++			result = (u16)odm_get_bb_reg(dm, reg, MASKBYTE2);
++			break;
++		}
++	}
++	return result;
++}
++
++void phydm_fahm_trigger(void *dm_void, u16 tgr_period)
++{ /*@unit (4us)*/
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 fahm_reg1;
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		odm_set_bb_reg(dm, R_0x1cf8, 0xffff00, tgr_period);
++
++		fahm_reg1 = 0x994;
++	} else {
++		odm_set_bb_reg(dm, R_0x978, 0xff000000, (tgr_period & 0xff));
++		odm_set_bb_reg(dm, R_0x97c, 0xff, (tgr_period & 0xff00) >> 8);
++
++		fahm_reg1 = 0x890;
++	}
++
++	odm_set_bb_reg(dm, fahm_reg1, BIT(2), 0);
++	odm_set_bb_reg(dm, fahm_reg1, BIT(2), 1);
++}
++
++void phydm_fahm_set_valid_cnt(void *dm_void, u8 numerator_sel,
++			      u8 denominator_sel)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx_info = &dm->dm_ccx_info;
++	u32 fahm_reg1;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++
++	if (ccx_info->fahm_nume_sel == numerator_sel &&
++	    ccx_info->fahm_denom_sel == denominator_sel) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR, "no need to update\n");
++		return;
++	}
++
++	ccx_info->fahm_nume_sel = numerator_sel;
++	ccx_info->fahm_denom_sel = denominator_sel;
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
++		fahm_reg1 = 0x994;
++	else
++		fahm_reg1 = 0x890;
++
++	odm_set_bb_reg(dm, fahm_reg1, 0xe0, numerator_sel);
++	odm_set_bb_reg(dm, fahm_reg1, 0x7000, denominator_sel);
++}
++
++void phydm_fahm_get_result(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u16 fahm_cnt[12]; /*packet count*/
++	u16 fahm_rpt[12]; /*percentage*/
++	u16 denominator; /*@fahm_denominator packet count*/
++	u32 reg_rpt, reg_rpt_2;
++	u32 reg_tmp;
++	boolean is_ready = false;
++	u8 i;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		reg_rpt = 0x1f80;
++		reg_rpt_2 = 0x1f98;
++	} else {
++		reg_rpt = 0x9d8;
++		reg_rpt_2 = 0x9f0;
++	}
++
++	for (i = 0; i < 3; i++) {
++		if (odm_get_bb_reg(dm, reg_rpt_2, BIT(31))) {
++		/*@Chk HW rpt is ready*/
++			is_ready = true;
++			break;
++		}
++		ODM_delay_ms(1);
++	}
++
++	if (!is_ready)
++		return;
++
++	/*@Get FAHM Denominator*/
++	denominator = (u16)odm_get_bb_reg(dm, reg_rpt_2, MASKLWORD);
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "Reg[0x%x] fahm_denmrtr = %d\n", reg_rpt_2,
++		  denominator);
++
++	/*@Get FAHM nemerator*/
++	for (i = 0; i < 6; i++) {
++		reg_tmp = odm_get_bb_reg(dm, reg_rpt + (i << 2), MASKDWORD);
++
++		PHYDM_DBG(dm, DBG_ENV_MNTR, "Reg[0x%x] fahm_denmrtr = %d\n",
++			  reg_rpt + (i * 4), reg_tmp);
++
++		fahm_cnt[i * 2] = (u16)(reg_tmp & MASKLWORD);
++		fahm_cnt[i * 2 + 1] = (u16)((reg_tmp & MASKHWORD) >> 16);
++	}
++
++	for (i = 0; i < 12; i++)
++		fahm_rpt[i] = phydm_hw_divider(dm, fahm_cnt[i], denominator);
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR,
++		  "FAHM_RPT_cnt[10:0]=[%d, %d, %d, %d, %d(IGI), %d, %d, %d, %d, %d, %d, %d]\n",
++		  fahm_cnt[11], fahm_cnt[10], fahm_cnt[9],
++		  fahm_cnt[8], fahm_cnt[7], fahm_cnt[6],
++		  fahm_cnt[5], fahm_cnt[4], fahm_cnt[3],
++		  fahm_cnt[2], fahm_cnt[1], fahm_cnt[0]);
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR,
++		  "FAHM_RPT[10:0]=[%d, %d, %d, %d, %d(IGI), %d, %d, %d, %d, %d, %d, %d]\n",
++		  fahm_rpt[11], fahm_rpt[10], fahm_rpt[9], fahm_rpt[8],
++		  fahm_rpt[7], fahm_rpt[6], fahm_rpt[5], fahm_rpt[4],
++		  fahm_rpt[3], fahm_rpt[2], fahm_rpt[1], fahm_rpt[0]);
++}
++
++void phydm_fahm_set_th_by_igi(void *dm_void, u8 igi)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx_info = &dm->dm_ccx_info;
++	u32 val = 0;
++	u8 f_th[11]; /*@FAHM Threshold*/
++	u8 rssi_th[11]; /*@in RSSI scale*/
++	u8 th_gap = 2 * IGI_TO_NHM_TH_MULTIPLIER; /*unit is 0.5dB for FAHM*/
++	u8 i;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++
++	if (ccx_info->env_mntr_igi == igi) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR,
++			  "No need to update FAHM_th, IGI=0x%x\n",
++			  ccx_info->env_mntr_igi);
++		return;
++	}
++
++	ccx_info->env_mntr_igi = igi; /*@bkp IGI*/
++
++	if (igi >= CCA_CAP)
++		f_th[0] = (igi - CCA_CAP) * IGI_TO_NHM_TH_MULTIPLIER;
++	else
++		f_th[0] = 0;
++
++	rssi_th[0] = igi - 10 - CCA_CAP;
++
++	for (i = 1; i <= 10; i++) {
++		f_th[i] = f_th[0] + th_gap * i;
++		rssi_th[i] = rssi_th[0] + (i << 1);
++	}
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR,
++		  "FAHM_RSSI_th[10:0]=[%d, %d, %d, (IGI)%d, %d, %d, %d, %d, %d, %d, %d]\n",
++		  rssi_th[10], rssi_th[9], rssi_th[8], rssi_th[7], rssi_th[6],
++		  rssi_th[5], rssi_th[4], rssi_th[3], rssi_th[2], rssi_th[1],
++		  rssi_th[0]);
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		val = BYTE_2_DWORD(0, f_th[2], f_th[1], f_th[0]);
++		odm_set_bb_reg(dm, R_0x1c38, 0xffffff00, val);
++		val = BYTE_2_DWORD(0, f_th[5], f_th[4], f_th[3]);
++		odm_set_bb_reg(dm, R_0x1c78, 0xffffff00, val);
++		val = BYTE_2_DWORD(0, 0, f_th[7], f_th[6]);
++		odm_set_bb_reg(dm, R_0x1c7c, 0xffff0000, val);
++		val = BYTE_2_DWORD(0, f_th[10], f_th[9], f_th[8]);
++		odm_set_bb_reg(dm, R_0x1cb8, 0xffffff00, val);
++	} else {
++		val = BYTE_2_DWORD(f_th[3], f_th[2], f_th[1], f_th[0]);
++		odm_set_bb_reg(dm, R_0x970, MASKDWORD, val);
++		val = BYTE_2_DWORD(f_th[7], f_th[6], f_th[5], f_th[4]);
++		odm_set_bb_reg(dm, R_0x974, MASKDWORD, val);
++		val = BYTE_2_DWORD(0, f_th[10], f_th[9], f_th[8]);
++		odm_set_bb_reg(dm, R_0x978, 0xffffff, val);
++	}
++}
++
++void phydm_fahm_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx_info = &dm->dm_ccx_info;
++	u32 fahm_reg1;
++	u8 denumerator_sel = 0;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "IGI=0x%x\n",
++		  dm->dm_dig_table.cur_ig_value);
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
++		fahm_reg1 = 0x994;
++	else
++		fahm_reg1 = 0x890;
++
++	ccx_info->fahm_period = 65535;
++
++	odm_set_bb_reg(dm, fahm_reg1, 0x6, 3); /*@FAHM HW block enable*/
++
++	denumerator_sel = FAHM_INCLD_FA | FAHM_INCLD_CRC_OK | FAHM_INCLD_CRC_ER;
++	phydm_fahm_set_valid_cnt(dm, FAHM_INCLD_FA, denumerator_sel);
++	phydm_fahm_set_th_by_igi(dm, dm->dm_dig_table.cur_ig_value);
++}
++
++void phydm_fahm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
++		    u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx_info = &dm->dm_ccx_info;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 i;
++
++	for (i = 0; i < 2; i++) {
++		if (input[i + 1])
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
++	}
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{1: trigger, 2:get result}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{3: MNTR mode sel} {1: driver, 2. FW}\n");
++		return;
++	} else if (var1[0] == 1) { /* Set & trigger CLM */
++
++		phydm_fahm_set_th_by_igi(dm, dm->dm_dig_table.cur_ig_value);
++		phydm_fahm_trigger(dm, ccx_info->fahm_period);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Monitor FAHM for %d * 4us\n", ccx_info->fahm_period);
++
++	} else if (var1[0] == 2) { /* @Get CLM results */
++
++		phydm_fahm_get_result(dm);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "FAHM_result=%d us\n", (ccx_info->clm_result << 2));
++
++	} else {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Error\n");
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++#endif /*@#ifdef FAHM_SUPPORT*/
++
++#ifdef NHM_SUPPORT
++
++void phydm_nhm_racing_release(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	u32 value32 = 0;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "lv:(%d)->(0)\n", ccx->nhm_set_lv);
++
++	ccx->nhm_ongoing = false;
++	ccx->nhm_set_lv = NHM_RELEASE;
++
++	if (!(ccx->nhm_app == NHM_BACKGROUND || ccx->nhm_app == NHM_ACS)) {
++		phydm_pause_func(dm, F00_DIG, PHYDM_RESUME,
++				 PHYDM_PAUSE_LEVEL_1, 1, &value32);
++	}
++
++	ccx->nhm_app = NHM_BACKGROUND;
++}
++
++u8 phydm_nhm_racing_ctrl(void *dm_void, enum phydm_nhm_level nhm_lv)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	u8 set_result = PHYDM_SET_SUCCESS;
++	/*@acquire to control NHM API*/
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_ongoing=%d, lv:(%d)->(%d)\n",
++		  ccx->nhm_ongoing, ccx->nhm_set_lv, nhm_lv);
++	if (ccx->nhm_ongoing) {
++		if (nhm_lv <= ccx->nhm_set_lv) {
++			set_result = PHYDM_SET_FAIL;
++		} else {
++			phydm_ccx_hw_restart(dm);
++			ccx->nhm_ongoing = false;
++		}
++	}
++
++	if (set_result)
++		ccx->nhm_set_lv = nhm_lv;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm racing success=%d\n", set_result);
++	return set_result;
++}
++
++void phydm_nhm_trigger(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	u32 nhm_reg1 = 0;
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
++		nhm_reg1 = R_0x994;
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		nhm_reg1 = R_0x1e60;
++	#endif
++	else
++		nhm_reg1 = R_0x890;
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++
++	/* @Trigger NHM*/
++	pdm_set_reg(dm, nhm_reg1, BIT(1), 0);
++	pdm_set_reg(dm, nhm_reg1, BIT(1), 1);
++	ccx->nhm_trigger_time = dm->phydm_sys_up_time;
++	ccx->nhm_rpt_stamp++;
++	ccx->nhm_ongoing = true;
++}
++
++boolean
++phydm_nhm_check_rdy(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	boolean is_ready = false;
++	u32 reg1 = 0, reg1_bit = 0;
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		reg1 = R_0xfb4;
++		reg1_bit = 16;
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		reg1 = R_0x2d4c;
++		reg1_bit = 16;
++	#endif
++	} else {
++		reg1 = R_0x8b4;
++		if (dm->support_ic_type & (ODM_RTL8710B | ODM_RTL8721D |
++					ODM_RTL8710C))
++			reg1_bit = 25;
++		else
++			reg1_bit = 17;
++	}
++	if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit)))
++		is_ready = true;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM rdy=%d\n", is_ready);
++
++	return is_ready;
++}
++
++u8 phydm_nhm_cal_noise(void *dm_void, u8 start_i, u8 end_i, u8 n_sum)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	u8 i = 0;
++	u32 noise_tmp = 0;
++	u8 noise = 0;
++	u32 nhm_valid = 0;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++
++	if (n_sum == 0) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR,
++			  "n_sum = 0, don't need to update noise\n");
++		return 0x0;
++	} else if (end_i > NHM_RPT_NUM - 1) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR,
++			  "[WARNING]end_i is larger than 11!!\n");
++		return 0x0;
++	}
++
++	for (i = start_i; i <= end_i; i++) {
++		if (i == 0)
++			noise_tmp += ccx->nhm_result[0] *
++				     MAX_2(ccx->nhm_th[0] - 2, 0);
++		else if (i == (NHM_RPT_NUM - 1))
++			noise_tmp += ccx->nhm_result[NHM_RPT_NUM - 1] *
++				     (ccx->nhm_th[NHM_TH_NUM - 1] + 2);
++		else
++			noise_tmp += ccx->nhm_result[i] *
++				     (ccx->nhm_th[i - 1] + ccx->nhm_th[i]) >> 1;
++	}
++
++	/* protection for the case of minus noise(RSSI)*/
++	noise = (u8)(NTH_TH_2_RSSI(MAX_2(PHYDM_DIV(noise_tmp, n_sum), 20)));
++	nhm_valid = (n_sum * 100) >> 8;
++	PHYDM_DBG(dm, DBG_ENV_MNTR,
++		  "valid: ((%d)) percent, noise(RSSI)=((%d))\n",
++		  nhm_valid, noise);
++
++	return noise;
++}
++
++void phydm_nhm_get_utility(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	u8 nhm_rpt_non_0 = 0;
++	u8 nhm_rpt_non_11 = 0;
++
++	if (ccx->nhm_rpt_sum >= ccx->nhm_result[0]) {
++		nhm_rpt_non_0 = ccx->nhm_rpt_sum - ccx->nhm_result[0];
++		nhm_rpt_non_11 = ccx->nhm_rpt_sum - ccx->nhm_result[11];
++		ccx->nhm_ratio = (nhm_rpt_non_0 * 100) >> 8;
++		ccx->nhm_level_valid = (nhm_rpt_non_11 * 100) >> 8;
++		ccx->nhm_level = phydm_nhm_cal_noise(dm, 0, NHM_RPT_NUM - 2,
++						     nhm_rpt_non_11);
++	} else {
++		PHYDM_DBG(dm, DBG_ENV_MNTR, "[warning] nhm_rpt_sum invalid\n");
++		ccx->nhm_ratio = 0;
++	}
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_ratio=%d\n", ccx->nhm_ratio);
++}
++
++boolean
++phydm_nhm_get_result(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	u32 value32 = 0;
++	u8 i = 0;
++	u32 nhm_reg1 = 0;
++	u16 nhm_rpt_sum_tmp = 0;
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
++		nhm_reg1 = R_0x994;
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		nhm_reg1 = R_0x1e60;
++	#endif
++	else
++		nhm_reg1 = R_0x890;
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++
++	if (!(dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
++				     ODM_RTL8197G)))
++		pdm_set_reg(dm, nhm_reg1, BIT(1), 0);
++
++	if (!(phydm_nhm_check_rdy(dm))) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM report Fail\n");
++		phydm_nhm_racing_release(dm);
++		return false;
++	}
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		value32 = odm_read_4byte(dm, R_0xfa8);
++		odm_move_memory(dm, &ccx->nhm_result[0], &value32, 4);
++
++		value32 = odm_read_4byte(dm, R_0xfac);
++		odm_move_memory(dm, &ccx->nhm_result[4], &value32, 4);
++
++		value32 = odm_read_4byte(dm, R_0xfb0);
++		odm_move_memory(dm, &ccx->nhm_result[8], &value32, 4);
++
++		/*@Get NHM duration*/
++		value32 = odm_read_4byte(dm, R_0xfb4);
++		ccx->nhm_duration = (u16)(value32 & MASKLWORD);
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		value32 = odm_read_4byte(dm, R_0x2d40);
++		odm_move_memory(dm, &ccx->nhm_result[0], &value32, 4);
++
++		value32 = odm_read_4byte(dm, R_0x2d44);
++		odm_move_memory(dm, &ccx->nhm_result[4], &value32, 4);
++
++		value32 = odm_read_4byte(dm, R_0x2d48);
++		odm_move_memory(dm, &ccx->nhm_result[8], &value32, 4);
++
++		/*@Get NHM duration*/
++		value32 = odm_read_4byte(dm, R_0x2d4c);
++		ccx->nhm_duration = (u16)(value32 & MASKLWORD);
++	#endif
++	} else {
++		value32 = odm_read_4byte(dm, R_0x8d8);
++		odm_move_memory(dm, &ccx->nhm_result[0], &value32, 4);
++
++		value32 = odm_read_4byte(dm, R_0x8dc);
++		odm_move_memory(dm, &ccx->nhm_result[4], &value32, 4);
++
++		value32 = odm_get_bb_reg(dm, R_0x8d0, 0xffff0000);
++		odm_move_memory(dm, &ccx->nhm_result[8], &value32, 2);
++
++		value32 = odm_read_4byte(dm, R_0x8d4);
++
++		ccx->nhm_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
++		ccx->nhm_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
++
++		/*@Get NHM duration*/
++		ccx->nhm_duration = (u16)(value32 & MASKLWORD);
++	}
++
++	/* sum all nhm_result */
++	if (ccx->nhm_period >= 65530) {
++		value32 = (ccx->nhm_duration * 100) >> 16;
++		PHYDM_DBG(dm, DBG_ENV_MNTR,
++			  "NHM valid time = %d, valid: %d percent\n",
++			  ccx->nhm_duration, value32);
++	}
++
++	for (i = 0; i < NHM_RPT_NUM; i++)
++		nhm_rpt_sum_tmp += (u16)ccx->nhm_result[i];
++
++	ccx->nhm_rpt_sum = (u8)nhm_rpt_sum_tmp;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR,
++		  "NHM_Rpt[%d](H->L)[%d %d %d %d %d %d %d %d %d %d %d %d]\n",
++		  ccx->nhm_rpt_stamp, ccx->nhm_result[11], ccx->nhm_result[10],
++		  ccx->nhm_result[9], ccx->nhm_result[8], ccx->nhm_result[7],
++		  ccx->nhm_result[6], ccx->nhm_result[5], ccx->nhm_result[4],
++		  ccx->nhm_result[3], ccx->nhm_result[2], ccx->nhm_result[1],
++		  ccx->nhm_result[0]);
++
++	phydm_nhm_racing_release(dm);
++
++	if (nhm_rpt_sum_tmp > 255) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR,
++			  "[Warning] Invalid NHM RPT, total=%d\n",
++			  nhm_rpt_sum_tmp);
++		return false;
++	}
++
++	return true;
++}
++
++void phydm_nhm_set_th_reg(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	u32 reg1 = 0, reg2 = 0, reg3 = 0, reg4 = 0, reg4_bit = 0;
++	u32 val = 0;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		reg1 = R_0x994;
++		reg2 = R_0x998;
++		reg3 = R_0x99c;
++		reg4 = R_0x9a0;
++		reg4_bit = MASKBYTE0;
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		reg1 = R_0x1e60;
++		reg2 = R_0x1e44;
++		reg3 = R_0x1e48;
++		reg4 = R_0x1e5c;
++		reg4_bit = MASKBYTE2;
++	#endif
++	} else {
++		reg1 = R_0x890;
++		reg2 = R_0x898;
++		reg3 = R_0x89c;
++		reg4 = R_0xe28;
++		reg4_bit = MASKBYTE0;
++	}
++
++	/*Set NHM threshold*/ /*Unit: PWdB U(8,1)*/
++	val = BYTE_2_DWORD(ccx->nhm_th[3], ccx->nhm_th[2],
++			   ccx->nhm_th[1], ccx->nhm_th[0]);
++	pdm_set_reg(dm, reg2, MASKDWORD, val);
++	val = BYTE_2_DWORD(ccx->nhm_th[7], ccx->nhm_th[6],
++			   ccx->nhm_th[5], ccx->nhm_th[4]);
++	pdm_set_reg(dm, reg3, MASKDWORD, val);
++	pdm_set_reg(dm, reg4, reg4_bit, ccx->nhm_th[8]);
++	val = BYTE_2_DWORD(0, 0, ccx->nhm_th[10], ccx->nhm_th[9]);
++	pdm_set_reg(dm, reg1, 0xffff0000, val);
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR,
++		  "Update NHM_th[H->L]=[%d %d %d %d %d %d %d %d %d %d %d]\n",
++		  ccx->nhm_th[10], ccx->nhm_th[9], ccx->nhm_th[8],
++		  ccx->nhm_th[7], ccx->nhm_th[6], ccx->nhm_th[5],
++		  ccx->nhm_th[4], ccx->nhm_th[3], ccx->nhm_th[2],
++		  ccx->nhm_th[1], ccx->nhm_th[0]);
++}
++
++boolean
++phydm_nhm_th_update_chk(void *dm_void, enum nhm_application nhm_app, u8 *nhm_th,
++			u32 *igi_new, boolean en_1db_mode, u8 nhm_th0_manual)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	boolean is_update = false;
++	u8 igi_curr = phydm_get_igi(dm, BB_PATH_A);
++	u8 nhm_igi_th_11k_low[NHM_TH_NUM] = {0x12, 0x15, 0x18, 0x1b, 0x1e,
++					     0x23, 0x28, 0x2c, 0x78,
++					     0x78, 0x78};
++	u8 nhm_igi_th_11k_high[NHM_TH_NUM] = {0x1e, 0x23, 0x28, 0x2d, 0x32,
++					      0x37, 0x78, 0x78, 0x78, 0x78,
++					      0x78};
++	u8 nhm_igi_th_xbox[NHM_TH_NUM] = {0x1a, 0x2c, 0x2e, 0x30, 0x32, 0x34,
++					  0x36, 0x38, 0x3a, 0x3c, 0x3d};
++	u8 i = 0;
++	u8 th_tmp = igi_curr - CCA_CAP;
++	u8 th_step = 2;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "App=%d, nhm_igi=0x%x, igi_curr=0x%x\n",
++		  nhm_app, ccx->nhm_igi, igi_curr);
++
++	if (igi_curr < 0x10) /* Protect for invalid IGI*/
++		return false;
++
++	switch (nhm_app) {
++	case NHM_BACKGROUND: /* @Get IGI form driver parameter(cur_ig_value)*/
++		if (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) {
++			is_update = true;
++			*igi_new = (u32)igi_curr;
++
++			#ifdef NHM_DYM_PW_TH_SUPPORT
++			if (ccx->nhm_dym_pw_th_en) {
++				th_tmp = MAX_2(igi_curr - DYM_PWTH_CCA_CAP, 0);
++				th_step = 3;
++			}
++			#endif
++
++			nhm_th[0] = (u8)IGI_2_NHM_TH(th_tmp);
++
++			for (i = 1; i <= 10; i++)
++				nhm_th[i] = nhm_th[0] +
++					    IGI_2_NHM_TH(th_step * i);
++
++		}
++		break;
++
++	case NHM_ACS:
++		if (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) {
++			is_update = true;
++			*igi_new = (u32)igi_curr;
++			nhm_th[0] = (u8)IGI_2_NHM_TH(igi_curr - CCA_CAP);
++			for (i = 1; i <= 10; i++)
++				nhm_th[i] = nhm_th[0] + IGI_2_NHM_TH(2 * i);
++		}
++		break;
++
++	case IEEE_11K_HIGH:
++		is_update = true;
++		*igi_new = 0x2c;
++		for (i = 0; i < NHM_TH_NUM; i++)
++			nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_11k_high[i]);
++		break;
++
++	case IEEE_11K_LOW:
++		is_update = true;
++		*igi_new = 0x20;
++		for (i = 0; i < NHM_TH_NUM; i++)
++			nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_11k_low[i]);
++		break;
++
++	case INTEL_XBOX:
++		is_update = true;
++		*igi_new = 0x36;
++		for (i = 0; i < NHM_TH_NUM; i++)
++			nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_xbox[i]);
++		break;
++
++	case NHM_DBG: /*@Get IGI form register*/
++		igi_curr = phydm_get_igi(dm, BB_PATH_A);
++		if (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) {
++			is_update = true;
++			*igi_new = (u32)igi_curr;
++			if (en_1db_mode) {
++				nhm_th[0] = (u8)IGI_2_NHM_TH(nhm_th0_manual +
++							     10);
++				th_step = 1;
++			} else {
++				nhm_th[0] = (u8)IGI_2_NHM_TH(igi_curr -
++							     CCA_CAP);
++			}
++
++			for (i = 1; i <= 10; i++)
++				nhm_th[i] = nhm_th[0] + IGI_2_NHM_TH(th_step *
++					    i);
++		}
++		break;
++	}
++
++	if (is_update) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR, "[Update NHM_TH] igi_RSSI=%d\n",
++			  IGI_2_RSSI(*igi_new));
++
++		for (i = 0; i < NHM_TH_NUM; i++) {
++			PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM_th[%d](RSSI) = %d\n",
++				  i, NTH_TH_2_RSSI(nhm_th[i]));
++		}
++	} else {
++		PHYDM_DBG(dm, DBG_ENV_MNTR, "No need to update NHM_TH\n");
++	}
++	return is_update;
++}
++
++void phydm_nhm_set(void *dm_void, enum nhm_option_txon_all include_tx,
++		   enum nhm_option_cca_all include_cca,
++		   enum nhm_divider_opt_all divi_opt,
++		   enum nhm_application nhm_app, u16 period,
++		   boolean en_1db_mode, u8 nhm_th0_manual)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	u8 nhm_th[NHM_TH_NUM] = {0};
++	u32 igi = 0x20;
++	u32 reg1 = 0, reg2 = 0;
++	u32 val_tmp = 0;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR,
++		  "incld{tx, cca}={%d, %d}, divi_opt=%d, period=%d\n",
++		  include_tx, include_cca, divi_opt, period);
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		reg1 = R_0x994;
++		reg2 = R_0x990;
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		reg1 = R_0x1e60;
++		reg2 = R_0x1e40;
++	#endif
++	} else {
++		reg1 = R_0x890;
++		reg2 = R_0x894;
++	}
++
++	/*Set disable_ignore_cca, disable_ignore_txon, ccx_en*/
++	if (include_tx != ccx->nhm_include_txon ||
++	    include_cca != ccx->nhm_include_cca ||
++	    divi_opt != ccx->nhm_divider_opt) {
++	    /* some old ic is not supported on NHM divider option */
++		if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B |
++		    ODM_RTL8195A | ODM_RTL8192E)) {
++			val_tmp = (u32)((include_tx << 2) |
++				  (include_cca << 1) | 1);
++			pdm_set_reg(dm, reg1, 0x700, val_tmp);
++		} else {
++			val_tmp = (u32)BIT_2_BYTE(divi_opt, include_tx,
++				  include_cca, 1);
++			pdm_set_reg(dm, reg1, 0xf00, val_tmp);
++		}
++		ccx->nhm_include_txon = include_tx;
++		ccx->nhm_include_cca = include_cca;
++		ccx->nhm_divider_opt = divi_opt;
++	}
++
++	/*Set NHM period*/
++	if (period != ccx->nhm_period) {
++		pdm_set_reg(dm, reg2, MASKHWORD, period);
++		PHYDM_DBG(dm, DBG_ENV_MNTR,
++			  "Update NHM period ((%d)) -> ((%d))\n",
++			  ccx->nhm_period, period);
++
++		ccx->nhm_period = period;
++	}
++
++	/*Set NHM threshold*/
++	if (phydm_nhm_th_update_chk(dm, nhm_app, &nhm_th[0], &igi,
++				    en_1db_mode, nhm_th0_manual)) {
++		/*Pause IGI*/
++		if (nhm_app == NHM_BACKGROUND || nhm_app == NHM_ACS) {
++			PHYDM_DBG(dm, DBG_ENV_MNTR, "DIG Free Run\n");
++		} else if (phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE,
++					    PHYDM_PAUSE_LEVEL_1, 1, &igi)
++					    == PAUSE_FAIL) {
++			PHYDM_DBG(dm, DBG_ENV_MNTR, "pause DIG Fail\n");
++			return;
++		} else {
++			PHYDM_DBG(dm, DBG_ENV_MNTR, "pause DIG=0x%x\n", igi);
++		}
++		ccx->nhm_app = nhm_app;
++		ccx->nhm_igi = (u8)igi;
++		odm_move_memory(dm, &ccx->nhm_th[0], &nhm_th, NHM_TH_NUM);
++
++		/*Set NHM th*/
++		phydm_nhm_set_th_reg(dm);
++	}
++}
++
++u8 phydm_nhm_mntr_set(void *dm_void, struct nhm_para_info *nhm_para)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u16 nhm_time = 0; /*unit: 4us*/
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++
++	if (nhm_para->mntr_time == 0)
++		return PHYDM_SET_FAIL;
++
++	if (nhm_para->nhm_lv >= NHM_MAX_NUM) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR, "Wrong LV=%d\n", nhm_para->nhm_lv);
++		return PHYDM_SET_FAIL;
++	}
++
++	if (phydm_nhm_racing_ctrl(dm, nhm_para->nhm_lv) == PHYDM_SET_FAIL)
++		return PHYDM_SET_FAIL;
++
++	if (nhm_para->mntr_time >= 262)
++		nhm_time = NHM_PERIOD_MAX;
++	else
++		nhm_time = nhm_para->mntr_time * MS_TO_4US_RATIO;
++
++	phydm_nhm_set(dm, nhm_para->incld_txon, nhm_para->incld_cca,
++		      nhm_para->div_opt, nhm_para->nhm_app, nhm_time,
++		      nhm_para->en_1db_mode, nhm_para->nhm_th0_manual);
++
++	return PHYDM_SET_SUCCESS;
++}
++
++#ifdef NHM_DYM_PW_TH_SUPPORT
++void
++phydm_nhm_restore_pw_th(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++
++	odm_set_bb_reg(dm, R_0x82c, 0x3f, ccx->pw_th_rf20_ori);
++}
++
++void
++phydm_nhm_set_pw_th(void *dm_void, u8 noise, boolean chk_succ)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	boolean not_update = false;
++	u8 pw_th_rf20_new = 0;
++	u8 pw_th_u_bnd = 0;
++	s8 noise_diff = 0;
++	u8 point_mean = 15;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++
++	if (*dm->band_width != CHANNEL_WIDTH_20 ||
++	    *dm->band_type == ODM_BAND_5G) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR,  "bandwidth=((%d)), band=((%d))\n",
++			  *dm->band_width, *dm->band_type);
++		phydm_nhm_restore_pw_th(dm);
++		return;
++	}
++
++	if (chk_succ) {
++		noise_diff = noise - (ccx->nhm_igi - 10);
++		pw_th_u_bnd = (u8)(noise_diff + 32 + point_mean);
++
++		pw_th_u_bnd = MIN_2(pw_th_u_bnd, ccx->nhm_pw_th_max);
++
++		PHYDM_DBG(dm, DBG_ENV_MNTR,
++			  "noise_diff=((%d)), max=((%d)), pw_th_u_bnd=((%d))\n",
++			  noise_diff, ccx->nhm_pw_th_max, pw_th_u_bnd);
++
++		if (pw_th_u_bnd > ccx->pw_th_rf20_cur) {
++			pw_th_rf20_new = ccx->pw_th_rf20_cur + 1;
++		} else if (pw_th_u_bnd < ccx->pw_th_rf20_cur) {
++			if (ccx->pw_th_rf20_cur > ccx->pw_th_rf20_ori)
++				pw_th_rf20_new = ccx->pw_th_rf20_cur - 1;
++			else /*ccx->pw_th_rf20_cur == ccx->pw_th_ori*/
++				not_update = true;
++		} else {/*pw_th_u_bnd == ccx->pw_th_rf20_cur*/
++			not_update = true;
++		}
++	} else {
++		if (ccx->pw_th_rf20_cur > ccx->pw_th_rf20_ori)
++			pw_th_rf20_new = ccx->pw_th_rf20_cur - 1;
++		else /*ccx->pw_th_rf20_cur == ccx->pw_th_ori*/
++			not_update = true;
++	}
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "pw_th_cur=((%d)), pw_th_new=((%d))\n",
++		  ccx->pw_th_rf20_cur, pw_th_rf20_new);
++
++	if (!not_update) {
++		odm_set_bb_reg(dm, R_0x82c, 0x3f, pw_th_rf20_new);
++		ccx->pw_th_rf20_cur = pw_th_rf20_new;
++	}
++}
++
++void
++phydm_nhm_dym_pw_th(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	u8 i = 0;
++	u8 n_sum = 0;
++	u8 noise = 0;
++	boolean chk_succ = false;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++
++	for (i = 0; i < NHM_RPT_NUM - 3; i++) {
++		n_sum = ccx->nhm_result[i] + ccx->nhm_result[i + 1] +
++			ccx->nhm_result[i + 2] + ccx->nhm_result[i + 3];
++		if (n_sum >= ccx->nhm_sl_pw_th) {
++			PHYDM_DBG(dm, DBG_ENV_MNTR, "Do sl[%d:%d]\n", i, i + 3);
++			chk_succ = true;
++			noise = phydm_nhm_cal_noise(dm, i, i + 3, n_sum);
++			break;
++		}
++	}
++
++	if (!chk_succ)
++		PHYDM_DBG(dm, DBG_ENV_MNTR, "SL method failed!\n");
++
++	phydm_nhm_set_pw_th(dm, noise, chk_succ);
++}
++
++boolean
++phydm_nhm_dym_pw_th_en(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	struct phydm_iot_center	*iot_table = &dm->iot_table;
++
++	if (!(dm->support_ic_type & ODM_RTL8822C))
++		return false;
++
++	if (ccx->dym_pwth_manual_ctrl)
++		return true;
++
++	if (dm->iot_table.phydm_patch_id == 0x100f0401 ||
++	    iot_table->patch_id_100f0401) {
++		return true;
++	} else if (ccx->nhm_dym_pw_th_en) {
++		phydm_nhm_restore_pw_th(dm);
++		return false;
++	} else {
++		return false;
++	}
++}
++#endif
++
++/*Environment Monitor*/
++boolean
++phydm_nhm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	struct nhm_para_info nhm_para = {0};
++	boolean nhm_chk_result = false;
++	boolean nhm_polling_result = false;
++	u32 sys_return_time = 0;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++
++	if (ccx->nhm_manual_ctrl) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM in manual ctrl\n");
++		return nhm_chk_result;
++	}
++	sys_return_time = ccx->nhm_trigger_time + MAX_ENV_MNTR_TIME;
++	if (ccx->nhm_app != NHM_BACKGROUND &&
++	    (sys_return_time > dm->phydm_sys_up_time)) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR,
++			  "nhm_app=%d, trigger_time %d, sys_time=%d\n",
++			  ccx->nhm_app, ccx->nhm_trigger_time,
++			  dm->phydm_sys_up_time);
++
++		return nhm_chk_result;
++	}
++
++	/*[NHM get result & calculate Utility----------------------------*/
++	nhm_polling_result = phydm_nhm_get_result(dm);
++	if (nhm_polling_result) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM_rpt success\n");
++		phydm_nhm_get_utility(dm);
++	}
++
++	#ifdef NHM_DYM_PW_TH_SUPPORT
++	ccx->nhm_dym_pw_th_en = phydm_nhm_dym_pw_th_en(dm);
++	if (ccx->nhm_dym_pw_th_en) {
++		if (nhm_polling_result)
++			phydm_nhm_dym_pw_th(dm);
++		else
++			phydm_nhm_set_pw_th(dm, 0x0, false);
++	}
++	#endif
++
++	/*[NHM trigger setting]------------------------------------------*/
++	nhm_para.incld_txon = NHM_EXCLUDE_TXON;
++	nhm_para.incld_cca = NHM_EXCLUDE_CCA;
++	nhm_para.div_opt = NHM_CNT_ALL;
++	nhm_para.nhm_app = NHM_BACKGROUND;
++	nhm_para.nhm_lv = NHM_LV_1;
++	nhm_para.en_1db_mode = false;
++	nhm_para.mntr_time = monitor_time;
++
++	#ifdef NHM_DYM_PW_TH_SUPPORT
++	if (ccx->nhm_dym_pw_th_en) {
++		nhm_para.div_opt = NHM_VALID;
++		nhm_para.mntr_time = monitor_time >> ccx->nhm_period_decre;
++	}
++	#endif
++
++	nhm_chk_result = phydm_nhm_mntr_set(dm, &nhm_para);
++
++	return nhm_chk_result;
++}
++
++void phydm_nhm_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "cur_igi=0x%x\n",
++		  dm->dm_dig_table.cur_ig_value);
++
++	ccx->nhm_app = NHM_BACKGROUND;
++	ccx->nhm_igi = 0xff;
++
++	/*Set NHM threshold*/
++	ccx->nhm_ongoing = false;
++	ccx->nhm_set_lv = NHM_RELEASE;
++
++	if (phydm_nhm_th_update_chk(dm, ccx->nhm_app, &ccx->nhm_th[0],
++				    (u32 *)&ccx->nhm_igi, false, 0))
++		phydm_nhm_set_th_reg(dm);
++
++	ccx->nhm_period = 0;
++
++	ccx->nhm_include_cca = NHM_CCA_INIT;
++	ccx->nhm_include_txon = NHM_TXON_INIT;
++	ccx->nhm_divider_opt = NHM_CNT_INIT;
++
++	ccx->nhm_manual_ctrl = 0;
++	ccx->nhm_rpt_stamp = 0;
++
++	#ifdef NHM_DYM_PW_TH_SUPPORT
++	if (dm->support_ic_type & ODM_RTL8822C) {
++		ccx->nhm_dym_pw_th_en = false;
++		ccx->pw_th_rf20_ori = (u8)odm_get_bb_reg(dm, R_0x82c, 0x3f);
++		ccx->pw_th_rf20_cur = ccx->pw_th_rf20_ori;
++		ccx->nhm_pw_th_max = 63;
++		ccx->nhm_sl_pw_th = 100; /*39%*/
++		ccx->nhm_period_decre = 1;
++		ccx->dym_pwth_manual_ctrl = false;
++	}
++	#endif
++}
++
++void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
++		   u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	struct nhm_para_info nhm_para;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 result_tmp = 0;
++	u8 i = 0;
++
++	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "NHM Basic-Trigger 262ms: {1}\n");
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "NHM Adv-Trigger: {2} {Include TXON} {Include CCA}\n{0:Cnt_all, 1:Cnt valid} {App} {LV:1~4} {0~262ms}, 1dB mode :{en} {t[0](RSSI)}\n");
++		#ifdef NHM_DYM_PW_TH_SUPPORT
++		if (dm->support_ic_type & ODM_RTL8822C) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "NHM dym_pw_th: {3} {0:off}\n");
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "NHM dym_pw_th: {3} {1:on} {max} {period_decre} {sl_th}\n");
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "NHM dym_pw_th: {3} {2:fast on}\n");
++		}
++		#endif
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "NHM Get Result: {100}\n");
++	} else if (var1[0] == 100) { /*Get NHM results*/
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "IGI=0x%x, rpt_stamp=%d\n", ccx->nhm_igi,
++			 ccx->nhm_rpt_stamp);
++
++		if (phydm_nhm_get_result(dm)) {
++			for (i = 0; i <= 11; i++) {
++				result_tmp = ccx->nhm_result[i];
++				PDM_SNPF(out_len, used, output + used,
++					 out_len - used,
++					 "nhm_rpt[%d] = %d (%d percent)\n",
++					 i, result_tmp,
++					 (((result_tmp * 100) + 128) >> 8));
++			}
++			phydm_nhm_get_utility(dm);
++
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[NHM] valid: %d percent, noise(RSSI) = %d\n",
++				 ccx->nhm_level_valid, ccx->nhm_level);
++		} else {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "Get NHM_rpt Fail\n");
++		}
++		ccx->nhm_manual_ctrl = 0;
++	#ifdef NHM_DYM_PW_TH_SUPPORT
++	} else if (var1[0] == 3) { /*NMH dym_pw_th*/
++		if (dm->support_ic_type & ODM_RTL8822C) {
++			for (i = 1; i < 7; i++) {
++				if (input[i + 1]) {
++					PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
++						     &var1[i]);
++				}
++			}
++
++			if (var1[1] == 1) {
++				ccx->nhm_dym_pw_th_en = true;
++				ccx->nhm_pw_th_max = (u8)var1[2];
++				ccx->nhm_period_decre = (u8)var1[3];
++				ccx->nhm_sl_pw_th = (u8)var1[4];
++				ccx->dym_pwth_manual_ctrl = true;
++			} else if (var1[1] == 2) {
++				ccx->nhm_dym_pw_th_en = true;
++				ccx->nhm_pw_th_max = 63;
++				ccx->nhm_period_decre = 1;
++				ccx->nhm_sl_pw_th = 100;
++				ccx->dym_pwth_manual_ctrl = true;
++			} else {
++				ccx->nhm_dym_pw_th_en = false;
++				phydm_nhm_restore_pw_th(dm);
++				ccx->dym_pwth_manual_ctrl = false;
++			}
++		}
++	#endif
++	} else { /*NMH trigger*/
++		ccx->nhm_manual_ctrl = 1;
++
++		for (i = 1; i < 9; i++) {
++			if (input[i + 1]) {
++				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
++					     &var1[i]);
++			}
++		}
++
++		if (var1[0] == 1) {
++			nhm_para.incld_txon = NHM_EXCLUDE_TXON;
++			nhm_para.incld_cca = NHM_EXCLUDE_CCA;
++			nhm_para.div_opt = NHM_CNT_ALL;
++			nhm_para.nhm_app = NHM_DBG;
++			nhm_para.nhm_lv = NHM_LV_4;
++			nhm_para.mntr_time = 262;
++			nhm_para.en_1db_mode = false;
++		} else {
++			nhm_para.incld_txon = (enum nhm_option_txon_all)var1[1];
++			nhm_para.incld_cca = (enum nhm_option_cca_all)var1[2];
++			nhm_para.div_opt = (enum nhm_divider_opt_all)var1[3];
++			nhm_para.nhm_app = (enum nhm_application)var1[4];
++			nhm_para.nhm_lv = (enum phydm_nhm_level)var1[5];
++			nhm_para.mntr_time = (u16)var1[6];
++			nhm_para.en_1db_mode = (boolean)var1[7];
++			nhm_para.nhm_th0_manual = (u8)var1[8];
++
++			/*some old ic is not supported on NHM divider option */
++			if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B |
++			    ODM_RTL8195A | ODM_RTL8192E)) {
++				nhm_para.div_opt = NHM_CNT_ALL;
++			}
++		}
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "txon=%d, cca=%d, dev=%d, app=%d, lv=%d, time=%d ms\n",
++			 nhm_para.incld_txon, nhm_para.incld_cca,
++			 nhm_para.div_opt, nhm_para.nhm_app,
++			 nhm_para.nhm_lv, nhm_para.mntr_time);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "en_1db_mode=%d, th0(for 1db mode)=%d\n",
++			 nhm_para.en_1db_mode, nhm_para.nhm_th0_manual);
++
++		if (phydm_nhm_mntr_set(dm, &nhm_para) == PHYDM_SET_SUCCESS)
++			phydm_nhm_trigger(dm);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "IGI=0x%x, rpt_stamp=%d\n", ccx->nhm_igi,
++			 ccx->nhm_rpt_stamp);
++
++		for (i = 0; i <= 10; i++) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "NHM_th[%d] RSSI = %d\n", i,
++				 NTH_TH_2_RSSI(ccx->nhm_th[i]));
++		}
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++#endif /*@#ifdef NHM_SUPPORT*/
++
++#ifdef CLM_SUPPORT
++
++void phydm_clm_racing_release(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "lv:(%d)->(0)\n", ccx->clm_set_lv);
++
++	ccx->clm_ongoing = false;
++	ccx->clm_set_lv = CLM_RELEASE;
++	ccx->clm_app = CLM_BACKGROUND;
++}
++
++u8 phydm_clm_racing_ctrl(void *dm_void, enum phydm_clm_level clm_lv)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	u8 set_result = PHYDM_SET_SUCCESS;
++	/*@acquire to control CLM API*/
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_ongoing=%d, lv:(%d)->(%d)\n",
++		  ccx->clm_ongoing, ccx->clm_set_lv, clm_lv);
++	if (ccx->clm_ongoing) {
++		if (clm_lv <= ccx->clm_set_lv) {
++			set_result = PHYDM_SET_FAIL;
++		} else {
++			phydm_ccx_hw_restart(dm);
++			ccx->clm_ongoing = false;
++		}
++	}
++
++	if (set_result)
++		ccx->clm_set_lv = clm_lv;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "clm racing success=%d\n", set_result);
++	return set_result;
++}
++
++void phydm_clm_c2h_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx_info = &dm->dm_ccx_info;
++	u8 clm_report = cmd_buf[0];
++	/*@u8 clm_report_idx = cmd_buf[1];*/
++
++	if (cmd_len >= 12)
++		return;
++
++	ccx_info->clm_fw_result_acc += clm_report;
++	ccx_info->clm_fw_result_cnt++;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%d] clm_report= %d\n",
++		  ccx_info->clm_fw_result_cnt, clm_report);
++}
++
++void phydm_clm_h2c(void *dm_void, u16 obs_time, u8 fw_clm_en)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 h2c_val[H2C_MAX_LENGTH] = {0};
++	u8 i = 0;
++	u8 obs_time_idx = 0;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "obs_time_index=%d *4 us\n", obs_time);
++
++	for (i = 1; i <= 16; i++) {
++		if (obs_time & BIT(16 - i)) {
++			obs_time_idx = 16 - i;
++			break;
++		}
++	}
++#if 0
++	obs_time = (2 ^ 16 - 1)~(2 ^ 15)  => obs_time_idx = 15  (65535 ~32768)
++	obs_time = (2 ^ 15 - 1)~(2 ^ 14)  => obs_time_idx = 14
++	...
++	...
++	...
++	obs_time = (2 ^ 1 - 1)~(2 ^ 0)  => obs_time_idx = 0
++
++#endif
++
++	h2c_val[0] = obs_time_idx | (((fw_clm_en) ? 1 : 0) << 7);
++	h2c_val[1] = CLM_MAX_REPORT_TIME;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "PHYDM h2c[0x4d]=0x%x %x %x %x %x %x %x\n",
++		  h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2],
++		  h2c_val[1], h2c_val[0]);
++
++	odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_CLM_MNTR, H2C_MAX_LENGTH, h2c_val);
++}
++
++void phydm_clm_setting(void *dm_void, u16 clm_period /*@4us sample 1 time*/)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++
++	if (ccx->clm_period != clm_period) {
++		if (dm->support_ic_type & ODM_IC_11AC_SERIES)
++			odm_set_bb_reg(dm, R_0x990, MASKLWORD, clm_period);
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++			odm_set_bb_reg(dm, R_0x1e40, MASKLWORD, clm_period);
++		#endif
++		else if (dm->support_ic_type & ODM_IC_11N_SERIES)
++			odm_set_bb_reg(dm, R_0x894, MASKLWORD, clm_period);
++
++		ccx->clm_period = clm_period;
++		PHYDM_DBG(dm, DBG_ENV_MNTR,
++			  "Update CLM period ((%d)) -> ((%d))\n",
++			  ccx->clm_period, clm_period);
++	}
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "Set CLM period=%d * 4us\n",
++		  ccx->clm_period);
++}
++
++void phydm_clm_trigger(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	u32 reg1 = 0;
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
++		reg1 = R_0x994;
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		reg1 = R_0x1e60;
++	#endif
++	else
++		reg1 = R_0x890;
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++
++	odm_set_bb_reg(dm, reg1, BIT(0), 0x0);
++	odm_set_bb_reg(dm, reg1, BIT(0), 0x1);
++
++	ccx->clm_trigger_time = dm->phydm_sys_up_time;
++	ccx->clm_rpt_stamp++;
++	ccx->clm_ongoing = true;
++}
++
++boolean
++phydm_clm_check_rdy(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	boolean is_ready = false;
++	u32 reg1 = 0, reg1_bit = 0;
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		reg1 = R_0xfa4;
++		reg1_bit = 16;
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		reg1 = R_0x2d88;
++		reg1_bit = 16;
++	#endif
++	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		if (dm->support_ic_type & (ODM_RTL8710B | ODM_RTL8721D |
++					ODM_RTL8710C)) {
++			reg1 = R_0x8b4;
++			reg1_bit = 24;
++		} else {
++			reg1 = R_0x8b4;
++			reg1_bit = 16;
++		}
++	}
++	if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit)))
++		is_ready = true;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM rdy=%d\n", is_ready);
++
++	return is_ready;
++}
++
++void phydm_clm_get_utility(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	u32 clm_result_tmp;
++
++	if (ccx->clm_period == 0) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR, "[warning] clm_period = 0\n");
++		ccx->clm_ratio = 0;
++	} else if (ccx->clm_period >= 65530) {
++		clm_result_tmp = (u32)(ccx->clm_result * 100);
++		ccx->clm_ratio = (u8)((clm_result_tmp + (1 << 15)) >> 16);
++	} else {
++		clm_result_tmp = (u32)(ccx->clm_result * 100);
++		ccx->clm_ratio = (u8)(clm_result_tmp / (u32)ccx->clm_period);
++	}
++}
++
++boolean
++phydm_clm_get_result(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx_info = &dm->dm_ccx_info;
++	u32 reg1 = 0;
++	u32 val = 0;
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
++		reg1 = R_0x994;
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		reg1 = R_0x1e60;
++	#endif
++	else
++		reg1 = R_0x890;
++	if (!(dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
++				     ODM_RTL8197G)))
++		odm_set_bb_reg(dm, reg1, BIT(0), 0x0);
++	if (!(phydm_clm_check_rdy(dm))) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM report Fail\n");
++		phydm_clm_racing_release(dm);
++		return false;
++	}
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		val = odm_get_bb_reg(dm, R_0xfa4, MASKLWORD);
++		ccx_info->clm_result = (u16)val;
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		val = odm_get_bb_reg(dm, R_0x2d88, MASKLWORD);
++		ccx_info->clm_result = (u16)val;
++	#endif
++	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		val = odm_get_bb_reg(dm, R_0x8d0, MASKLWORD);
++		ccx_info->clm_result = (u16)val;
++	}
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM result = %d *4 us\n",
++		  ccx_info->clm_result);
++	phydm_clm_racing_release(dm);
++	return true;
++}
++
++void phydm_clm_mntr_fw(void *dm_void, u16 monitor_time /*unit ms*/)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	u32 val = 0;
++
++	/*@[Get CLM report]*/
++	if (ccx->clm_fw_result_cnt != 0) {
++		val = ccx->clm_fw_result_acc / ccx->clm_fw_result_cnt;
++		ccx->clm_ratio = (u8)val;
++	} else {
++		ccx->clm_ratio = 0;
++	}
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR,
++		  "clm_fw_result_acc=%d, clm_fw_result_cnt=%d\n",
++		  ccx->clm_fw_result_acc, ccx->clm_fw_result_cnt);
++
++	ccx->clm_fw_result_acc = 0;
++	ccx->clm_fw_result_cnt = 0;
++
++	/*@[CLM trigger]*/
++	if (monitor_time >= 262)
++		ccx->clm_period = 65535;
++	else
++		ccx->clm_period = monitor_time * MS_TO_4US_RATIO;
++
++	phydm_clm_h2c(dm, ccx->clm_period, true);
++}
++
++u8 phydm_clm_mntr_set(void *dm_void, struct clm_para_info *clm_para)
++{
++	/*@Driver Monitor CLM*/
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	u16 clm_period = 0;
++
++	if (clm_para->mntr_time == 0)
++		return PHYDM_SET_FAIL;
++
++	if (clm_para->clm_lv >= CLM_MAX_NUM) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR, "[WARNING] Wrong LV=%d\n",
++			  clm_para->clm_lv);
++		return PHYDM_SET_FAIL;
++	}
++
++	if (phydm_clm_racing_ctrl(dm, clm_para->clm_lv) == PHYDM_SET_FAIL)
++		return PHYDM_SET_FAIL;
++
++	if (clm_para->mntr_time >= 262)
++		clm_period = CLM_PERIOD_MAX;
++	else
++		clm_period = clm_para->mntr_time * MS_TO_4US_RATIO;
++
++	ccx->clm_app = clm_para->clm_app;
++	phydm_clm_setting(dm, clm_period);
++
++	return PHYDM_SET_SUCCESS;
++}
++
++boolean
++phydm_clm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	struct clm_para_info clm_para = {0};
++	boolean clm_chk_result = false;
++	u32 sys_return_time = 0;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
++	if (ccx->clm_manual_ctrl) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM in manual ctrl\n");
++		return clm_chk_result;
++	}
++
++	sys_return_time = ccx->clm_trigger_time + MAX_ENV_MNTR_TIME;
++
++	if (ccx->clm_app != CLM_BACKGROUND &&
++	    sys_return_time > dm->phydm_sys_up_time) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR, "trigger_time %d, sys_time=%d\n",
++			  ccx->clm_trigger_time, dm->phydm_sys_up_time);
++
++		return clm_chk_result;
++	}
++
++	clm_para.clm_app = CLM_BACKGROUND;
++	clm_para.clm_lv = CLM_LV_1;
++	clm_para.mntr_time = monitor_time;
++	if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) {
++		/*@[Get CLM report]*/
++		if (phydm_clm_get_result(dm)) {
++			PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM_rpt success\n");
++			phydm_clm_get_utility(dm);
++		}
++
++		/*@[CLM trigger]----------------------------------------------*/
++		if (phydm_clm_mntr_set(dm, &clm_para) == PHYDM_SET_SUCCESS)
++			clm_chk_result = true;
++	} else {
++		phydm_clm_mntr_fw(dm, monitor_time);
++	}
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_ratio=%d\n", ccx->clm_ratio);
++
++	/*@PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_chk_result=%d\n",clm_chk_result);*/
++
++	return clm_chk_result;
++}
++
++void phydm_set_clm_mntr_mode(void *dm_void, enum clm_monitor_mode mode)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx_info = &dm->dm_ccx_info;
++
++	if (ccx_info->clm_mntr_mode != mode) {
++		ccx_info->clm_mntr_mode = mode;
++		phydm_ccx_hw_restart(dm);
++
++		if (mode == CLM_DRIVER_MNTR)
++			phydm_clm_h2c(dm, CLM_PERIOD_MAX, 0);
++	}
++}
++
++void phydm_clm_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++	ccx->clm_ongoing = false;
++	ccx->clm_manual_ctrl = 0;
++	ccx->clm_mntr_mode = CLM_DRIVER_MNTR;
++	ccx->clm_period = 0;
++	ccx->clm_rpt_stamp = 0;
++	phydm_clm_setting(dm, 65535);
++}
++
++void phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
++		   u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	struct clm_para_info clm_para = {0};
++	u32 i;
++
++	for (i = 0; i < 4; i++) {
++		if (input[i + 1])
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
++	}
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "CLM Driver Basic-Trigger 262ms: {1}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "CLM Driver Adv-Trigger: {2} {app} {LV} {0~262ms}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "CLM FW Trigger: {3} {1:drv, 2:fw}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "CLM Get Result: {100}\n");
++	} else if (var1[0] == 100) { /* @Get CLM results */
++
++		if (phydm_clm_get_result(dm))
++			phydm_clm_get_utility(dm);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "clm_rpt_stamp=%d\n", ccx->clm_rpt_stamp);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "clm_ratio:((%d percent)) = (%d us/ %d us)\n",
++			 ccx->clm_ratio, ccx->clm_result << 2,
++			 ccx->clm_period << 2);
++
++		ccx->clm_manual_ctrl = 0;
++	} else if (var1[0] == 3) {
++		phydm_set_clm_mntr_mode(dm, (enum clm_monitor_mode)var1[1]);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "CLM mode: %s mode\n",
++			 ((ccx->clm_mntr_mode == CLM_FW_MNTR) ? "FW" : "Drv"));
++	} else { /* Set & trigger CLM */
++		ccx->clm_manual_ctrl = 1;
++
++		if (var1[0] == 1) {
++			clm_para.clm_app = CLM_BACKGROUND;
++			clm_para.clm_lv = CLM_LV_4;
++			clm_para.mntr_time = 262;
++			ccx->clm_mntr_mode = CLM_DRIVER_MNTR;
++		} else if (var1[0] == 2) {
++			clm_para.clm_app = (enum clm_application)var1[1];
++			clm_para.clm_lv = (enum phydm_clm_level)var1[2];
++			ccx->clm_mntr_mode = CLM_DRIVER_MNTR;
++			clm_para.mntr_time = (u16)var1[3];
++		}
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "app=%d, lv=%d, mode=%s, time=%d ms\n",
++			 clm_para.clm_app, clm_para.clm_lv,
++			 ((ccx->clm_mntr_mode == CLM_FW_MNTR) ? "FW" :
++			 "driver"), clm_para.mntr_time);
++
++		if (phydm_clm_mntr_set(dm, &clm_para) == PHYDM_SET_SUCCESS)
++			phydm_clm_trigger(dm);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "clm_rpt_stamp=%d\n", ccx->clm_rpt_stamp);
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++#endif /*@#ifdef CLM_SUPPORT*/
++
++u8 phydm_env_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para,
++			  struct clm_para_info *clm_para,
++			  struct env_trig_rpt *trig_rpt)
++{
++#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT))
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	boolean nhm_set_ok = false;
++	boolean clm_set_ok = false;
++	u8 trigger_result = 0;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
++
++	/*@[NHM]*/
++	nhm_set_ok = phydm_nhm_mntr_set(dm, nhm_para);
++
++	/*@[CLM]*/
++	if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) {
++		clm_set_ok = phydm_clm_mntr_set(dm, clm_para);
++	} else if (ccx->clm_mntr_mode == CLM_FW_MNTR) {
++		phydm_clm_h2c(dm, CLM_PERIOD_MAX, true);
++		trigger_result |= CLM_SUCCESS;
++	}
++
++	if (nhm_set_ok) {
++		phydm_nhm_trigger(dm);
++		trigger_result |= NHM_SUCCESS;
++	}
++
++	if (clm_set_ok) {
++		phydm_clm_trigger(dm);
++		trigger_result |= CLM_SUCCESS;
++	}
++
++	/*@monitor for the test duration*/
++	ccx->start_time = odm_get_current_time(dm);
++
++	trig_rpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp;
++	trig_rpt->clm_rpt_stamp = ccx->clm_rpt_stamp;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_rpt_stamp=%d, clm_rpt_stamp=%d,\n\n",
++		  trig_rpt->nhm_rpt_stamp, trig_rpt->clm_rpt_stamp);
++
++	return trigger_result;
++#endif
++}
++
++u8 phydm_env_mntr_result(void *dm_void, struct env_mntr_rpt *rpt)
++{
++#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT))
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	u8 env_mntr_rpt = 0;
++	u64 progressing_time = 0;
++	u32 val_tmp = 0;
++
++	/*@monitor for the test duration*/
++	progressing_time = odm_get_progressing_time(dm, ccx->start_time);
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "env_time=%lld\n", progressing_time);
++
++	/*@Get NHM result*/
++	if (phydm_nhm_get_result(dm)) {
++		PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM_rpt success\n");
++		phydm_nhm_get_utility(dm);
++		rpt->nhm_ratio = ccx->nhm_ratio;
++		rpt->nhm_noise_pwr = ccx->nhm_level;
++		env_mntr_rpt |= NHM_SUCCESS;
++
++		odm_move_memory(dm, &rpt->nhm_result[0],
++				&ccx->nhm_result[0], NHM_RPT_NUM);
++	} else {
++		rpt->nhm_ratio = ENV_MNTR_FAIL;
++	}
++
++	/*@Get CLM result*/
++	if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) {
++		if (phydm_clm_get_result(dm)) {
++			PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM_rpt success\n");
++			phydm_clm_get_utility(dm);
++			env_mntr_rpt |= CLM_SUCCESS;
++			rpt->clm_ratio = ccx->clm_ratio;
++		} else {
++			rpt->clm_ratio = ENV_MNTR_FAIL;
++		}
++
++	} else {
++		if (ccx->clm_fw_result_cnt != 0) {
++			val_tmp = ccx->clm_fw_result_acc
++			/ ccx->clm_fw_result_cnt;
++			ccx->clm_ratio = (u8)val_tmp;
++		} else {
++			ccx->clm_ratio = 0;
++		}
++
++		rpt->clm_ratio = ccx->clm_ratio;
++		PHYDM_DBG(dm, DBG_ENV_MNTR,
++			  "clm_fw_result_acc=%d, clm_fw_result_cnt=%d\n",
++			  ccx->clm_fw_result_acc, ccx->clm_fw_result_cnt);
++
++		ccx->clm_fw_result_acc = 0;
++		ccx->clm_fw_result_cnt = 0;
++		env_mntr_rpt |= CLM_SUCCESS;
++	}
++
++	rpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp;
++	rpt->clm_rpt_stamp = ccx->clm_rpt_stamp;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR,
++		  "IGI=0x%x, nhm_ratio=%d, clm_ratio=%d, nhm_rpt_stamp=%d, clm_rpt_stamp=%d\n\n",
++		  ccx->nhm_igi, rpt->nhm_ratio, rpt->clm_ratio,
++		  rpt->nhm_rpt_stamp, rpt->clm_rpt_stamp);
++
++	return env_mntr_rpt;
++#endif
++}
++
++/*@Environment Monitor*/
++void phydm_env_mntr_watchdog(void *dm_void)
++{
++#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT))
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	boolean nhm_chk_ok = false;
++	boolean clm_chk_ok = false;
++
++	if (!(dm->support_ability & ODM_BB_ENV_MONITOR))
++		return;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++	nhm_chk_ok = phydm_nhm_mntr_chk(dm, 262); /*@monitor 262ms*/
++	clm_chk_ok = phydm_clm_mntr_chk(dm, 262); /*@monitor 262ms*/
++
++	/*@PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_chk_ok %d\n\n",nhm_chk_ok);*/
++	/*@PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_chk_ok %d\n\n",clm_chk_ok);*/
++
++	if (nhm_chk_ok)
++		phydm_nhm_trigger(dm);
++
++	if (clm_chk_ok)
++		phydm_clm_trigger(dm);
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR,
++		  "Summary: nhm_ratio=((%d)) clm_ratio=((%d))\n\n",
++		  ccx->nhm_ratio, ccx->clm_ratio);
++#endif
++}
++
++void phydm_env_monitor_init(void *dm_void)
++{
++#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT))
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (!(dm->support_ability & ODM_BB_ENV_MONITOR))
++		return;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
++	phydm_ccx_hw_restart(dm);
++	phydm_nhm_init(dm);
++	phydm_clm_init(dm);
++#endif
++}
++
++void phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used,
++			char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	struct clm_para_info clm_para = {0};
++	struct nhm_para_info nhm_para = {0};
++	struct env_mntr_rpt rpt = {0};
++	struct env_trig_rpt trig_rpt = {0};
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	u8 set_result = 0;
++	u8 i = 0;
++
++	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Basic-Trigger 262ms: {1}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Get Result: {100}\n");
++	} else if (var1[0] == 100) { /* Get results */
++		set_result = phydm_env_mntr_result(dm, &rpt);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Set Result=%d\n nhm_ratio=%d clm_ratio=%d\n nhm_rpt_stamp=%d, clm_rpt_stamp=%d,\n",
++			 set_result, rpt.nhm_ratio, rpt.clm_ratio,
++			 rpt.nhm_rpt_stamp, rpt.clm_rpt_stamp);
++
++		for (i = 0; i <= 11; i++) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "nhm_rpt[%d] = %d (%d percent)\n", i,
++				 rpt.nhm_result[i],
++				 (((rpt.nhm_result[i] * 100) + 128) >> 8));
++		}
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[NHM] valid: %d percent, noise(RSSI) = %d\n",
++			 ccx->nhm_level_valid, ccx->nhm_level);
++	} else { /* Set & trigger*/
++		/*nhm para*/
++		nhm_para.incld_txon = NHM_EXCLUDE_TXON;
++		nhm_para.incld_cca = NHM_EXCLUDE_CCA;
++		nhm_para.div_opt = NHM_CNT_ALL;
++		nhm_para.nhm_app = NHM_ACS;
++		nhm_para.nhm_lv = NHM_LV_2;
++		nhm_para.mntr_time = 262;
++		nhm_para.en_1db_mode = false;
++
++		/*clm para*/
++		clm_para.clm_app = CLM_ACS;
++		clm_para.clm_lv = CLM_LV_2;
++		clm_para.mntr_time = 262;
++
++		set_result = phydm_env_mntr_trigger(dm, &nhm_para,
++						    &clm_para, &trig_rpt);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Set Result=%d, nhm_rpt_stamp=%d, clm_rpt_stamp=%d\n",
++			 set_result, trig_rpt.nhm_rpt_stamp,
++			 trig_rpt.clm_rpt_stamp);
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_ccx.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_ccx.h
+new file mode 100644
+index 000000000..f24019d91
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_ccx.h
+@@ -0,0 +1,261 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDMCCX_H__
++#define __PHYDMCCX_H__
++
++/* 2019.07.17 Disable 1db_mode when nhm Basic-Trigger or watchdog*/
++#define CCX_VERSION "3.3"
++
++/* @1 ============================================================
++ * 1  Definition
++ * 1 ============================================================
++ */
++#define CCX_EN 1
++
++#define	MAX_ENV_MNTR_TIME	8	/*second*/
++#define	IGI_TO_NHM_TH_MULTIPLIER 2
++#define	MS_TO_4US_RATIO		250
++#define	CCA_CAP			14
++#define	CLM_MAX_REPORT_TIME	10
++#define	DEVIDER_ERROR		0xffff
++#define CLM_PERIOD_MAX		65535
++#define NHM_PERIOD_MAX		65534
++#define	NHM_TH_NUM		11	/*threshold number of NHM*/
++#define	NHM_RPT_NUM		12
++#ifdef NHM_DYM_PW_TH_SUPPORT
++#define	DYM_PWTH_CCA_CAP	24
++#endif
++
++#define	IGI_2_NHM_TH(igi)	((igi) << 1)/*NHM_threshold = IGI * 2*/
++#define	NTH_TH_2_RSSI(th)	((th >> 1) - 10)
++
++/*@FAHM*/
++#define	FAHM_INCLD_FA		BIT(0)
++#define	FAHM_INCLD_CRC_OK	BIT(1)
++#define	FAHM_INCLD_CRC_ER	BIT(2)
++
++#define NHM_SUCCESS		BIT(0)
++#define CLM_SUCCESS		BIT(1)
++#define FAHM_SUCCESS		BIT(2)
++#define	ENV_MNTR_FAIL		0xff
++
++/* @1 ============================================================
++ * 1 enumrate
++ * 1 ============================================================
++ */
++enum phydm_clm_level {
++	CLM_RELEASE		= 0,
++	CLM_LV_1		= 1,	/* @Low Priority function */
++	CLM_LV_2		= 2,	/* @Middle Priority function */
++	CLM_LV_3		= 3,	/* @High priority function (ex: Check hang function) */
++	CLM_LV_4		= 4,	/* @Debug function (the highest priority) */
++	CLM_MAX_NUM		= 5
++};
++
++enum phydm_nhm_level {
++	NHM_RELEASE		= 0,
++	NHM_LV_1		= 1,	/* @Low Priority function */
++	NHM_LV_2		= 2,	/* @Middle Priority function */
++	NHM_LV_3		= 3,	/* @High priority function (ex: Check hang function) */
++	NHM_LV_4		= 4,	/* @Debug function (the highest priority) */
++	NHM_MAX_NUM		= 5
++};
++
++enum nhm_divider_opt_all {
++	NHM_CNT_ALL		= 0,	/*nhm SUM report <= 255*/
++	NHM_VALID		= 1,	/*nhm SUM report = 255*/
++	NHM_CNT_INIT
++};
++
++enum nhm_setting {
++	SET_NHM_SETTING,
++	STORE_NHM_SETTING,
++	RESTORE_NHM_SETTING
++};
++
++enum nhm_option_cca_all {
++	NHM_EXCLUDE_CCA		= 0,
++	NHM_INCLUDE_CCA		= 1,
++	NHM_CCA_INIT
++};
++
++enum nhm_option_txon_all {
++	NHM_EXCLUDE_TXON	= 0,
++	NHM_INCLUDE_TXON	= 1,
++	NHM_TXON_INIT
++};
++
++enum nhm_application {
++	NHM_BACKGROUND		= 0,/*@default*/
++	NHM_ACS			= 1,
++	IEEE_11K_HIGH		= 2,
++	IEEE_11K_LOW		= 3,
++	INTEL_XBOX		= 4,
++	NHM_DBG			= 5, /*@manual trigger*/
++};
++
++enum clm_application {
++	CLM_BACKGROUND		= 0,/*@default*/
++	CLM_ACS			= 1,
++};
++
++enum clm_monitor_mode {
++	CLM_DRIVER_MNTR		= 1,
++	CLM_FW_MNTR		= 2
++};
++
++/* @1 ============================================================
++ * 1  structure
++ * 1 ============================================================
++ */
++struct env_trig_rpt {
++	u8			nhm_rpt_stamp;
++	u8			clm_rpt_stamp;
++};
++
++
++struct env_mntr_rpt {
++	u8			nhm_ratio;
++	u8			nhm_result[NHM_RPT_NUM];
++	u8			clm_ratio;
++	u8			nhm_rpt_stamp;
++	u8			clm_rpt_stamp;
++	u8			nhm_noise_pwr;
++};
++
++struct nhm_para_info {
++	enum nhm_option_txon_all	incld_txon;	/*@Include TX on*/
++	enum nhm_option_cca_all		incld_cca;	/*@Include CCA*/
++	enum nhm_divider_opt_all	div_opt;	/*@divider option*/
++	enum nhm_application		nhm_app;
++	enum phydm_nhm_level		nhm_lv;
++	u16				mntr_time;	/*@0~262 unit ms*/
++	boolean				en_1db_mode;
++	u8				nhm_th0_manual;	/* for 1-db mode*/
++};
++
++struct clm_para_info {
++	enum clm_application		clm_app;
++	enum phydm_clm_level		clm_lv;
++	u16				mntr_time;	/*@0~262 unit ms*/
++};
++
++struct ccx_info {
++	u32			nhm_trigger_time;
++	u32			clm_trigger_time;
++	u64			start_time;	/*@monitor for the test duration*/
++#ifdef NHM_SUPPORT
++	enum nhm_application		nhm_app;
++	enum nhm_option_txon_all	nhm_include_txon;
++	enum nhm_option_cca_all		nhm_include_cca;
++	enum nhm_divider_opt_all 	nhm_divider_opt;
++	/*Report*/
++	u8			nhm_th[NHM_TH_NUM];
++	u8			nhm_result[NHM_RPT_NUM];
++	u16			nhm_period;	/* @4us per unit */
++	u8			nhm_igi;
++	u8			nhm_manual_ctrl;
++	u8			nhm_ratio;	/*@1% per nuit, it means the interference igi can't overcome.*/
++	u8			nhm_rpt_sum;
++	u16			nhm_duration;	/*@Real time of NHM_VALID */
++	u8			nhm_set_lv;
++	boolean			nhm_ongoing;
++	u8			nhm_rpt_stamp;
++	u8			nhm_level;
++	u8			nhm_level_valid;
++#ifdef NHM_DYM_PW_TH_SUPPORT
++	boolean			nhm_dym_pw_th_en;
++	boolean			dym_pwth_manual_ctrl;
++	u8			pw_th_rf20_ori;
++	u8			pw_th_rf20_cur;
++	u8			nhm_pw_th_max;
++	u8			nhm_period_decre;
++	u8			nhm_sl_pw_th;
++#endif
++#endif
++
++#ifdef CLM_SUPPORT
++	enum clm_application	clm_app;
++	u8			clm_manual_ctrl;
++	u8			clm_set_lv;
++	boolean			clm_ongoing;
++	u16			clm_period;	/* @4us per unit */
++	u16			clm_result;
++	u8			clm_ratio;
++	u32			clm_fw_result_acc;
++	u8			clm_fw_result_cnt;
++	enum clm_monitor_mode	clm_mntr_mode;
++	u8			clm_rpt_stamp;
++#endif
++#ifdef FAHM_SUPPORT
++	boolean			fahm_ongoing;
++	u8			env_mntr_igi;
++	u8			fahm_nume_sel;	/*@fahm_numerator_sel: select {FA, CRCOK, CRC_fail} */
++	u8			fahm_denom_sel;	/*@fahm_denominator_sel: select {FA, CRCOK, CRC_fail} */
++	u16			fahm_period;	/*unit: 4us*/
++#endif
++};
++
++/* @1 ============================================================
++ * 1 Function Prototype
++ * 1 ============================================================
++ */
++
++#ifdef FAHM_SUPPORT
++void phydm_fahm_init(void *dm_void);
++
++void phydm_fahm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
++		    u32 *_out_len);
++#endif
++
++/*@NHM*/
++#ifdef NHM_SUPPORT
++void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
++		   u32 *_out_len);
++u8 phydm_get_igi(void *dm_void, enum bb_path path);
++#endif
++
++/*@CLM*/
++#ifdef CLM_SUPPORT
++void phydm_clm_c2h_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
++
++void phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
++		   u32 *_out_len);
++#endif
++
++u8 phydm_env_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para,
++			  struct clm_para_info *clm_para,
++			  struct env_trig_rpt *rpt);
++
++u8 phydm_env_mntr_result(void *dm_void, struct env_mntr_rpt *rpt);
++
++void phydm_env_mntr_watchdog(void *dm_void);
++
++void phydm_env_monitor_init(void *dm_void);
++
++void phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used,
++			char *output, u32 *_out_len);
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cfotracking.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cfotracking.c
+new file mode 100644
+index 000000000..8532d4e88
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cfotracking.c
+@@ -0,0 +1,618 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++s32 phydm_get_cfo_hz(void *dm_void, u32 val, u8 bit_num, u8 frac_num)
++{
++	s32 val_s = 0;
++
++	val_s = phydm_cnvrt_2_sign(val, bit_num);
++
++	if (frac_num == 10) /*@ (X*312500)/1024 ~= X*305*/
++		val_s *= 305;
++	else if (frac_num == 11) /*@ (X*312500)/2048 ~= X*152*/
++		val_s *= 152;
++	else if (frac_num == 12) /*@ (X*312500)/4096 ~= X*76*/
++		val_s *= 76;
++
++	return val_s;
++}
++
++#if (ODM_IC_11AC_SERIES_SUPPORT)
++void phydm_get_cfo_info_ac(void *dm_void, struct phydm_cfo_rpt *cfo)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i = 0;
++	u32 val[4] = {0};
++	u32 val_1[4] = {0};
++	u32 val_2[4] = {0};
++	u32 val_tmp = 0;
++
++	val[0] = odm_read_4byte(dm, R_0xd0c);
++	val_1[0] = odm_read_4byte(dm, R_0xd10);
++	val_2[0] = odm_get_bb_reg(dm, R_0xd14, 0x1fff0000);
++
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	val[1] = odm_read_4byte(dm, R_0xd4c);
++	val_1[1] = odm_read_4byte(dm, R_0xd50);
++	val_2[1] = odm_get_bb_reg(dm, R_0xd54, 0x1fff0000);
++	#endif
++
++	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++	val[2] = odm_read_4byte(dm, R_0xd8c);
++	val_1[2] = odm_read_4byte(dm, R_0xd90);
++	val_2[2] = odm_get_bb_reg(dm, R_0xd94, 0x1fff0000);
++	#endif
++
++	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	val[3] = odm_read_4byte(dm, R_0xdcc);
++	val_1[3] = odm_read_4byte(dm, R_0xdd0);
++	val_2[3] = odm_get_bb_reg(dm, R_0xdd4, 0x1fff0000);
++	#endif
++
++	for (i = 0; i < dm->num_rf_path; i++) {
++		val_tmp = val[i] & 0xfff;	/*@ Short CFO, S(12,11)*/
++		cfo->cfo_rpt_s[i] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
++
++		val_tmp = val[i] >> 16;		/*@ Long CFO, S(13,12)*/
++		cfo->cfo_rpt_l[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
++
++		val_tmp = val_1[i] & 0x7ff;	/*@ SCFO, S(11,10)*/
++		cfo->cfo_rpt_sec[i] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);
++
++		val_tmp = val_1[i] >> 16;	/*@ Acq CFO, S(13,12)*/
++		cfo->cfo_rpt_acq[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
++
++		val_tmp = val_2[i];		/*@ End CFO, S(13,12)*/
++		cfo->cfo_rpt_end[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
++	}
++}
++#endif
++
++#if (ODM_IC_11N_SERIES_SUPPORT)
++void phydm_get_cfo_info_n(void *dm_void, struct phydm_cfo_rpt *cfo)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 val[5] = {0};
++	u32 val_tmp = 0;
++
++	odm_set_bb_reg(dm, R_0xd00, BIT(26), 1);
++
++	val[0] = odm_read_4byte(dm, R_0xdac); /*@ Short CFO*/
++	val[1] = odm_read_4byte(dm, R_0xdb0); /*@ Long CFO*/
++	val[2] = odm_read_4byte(dm, R_0xdb8); /*@ Sec CFO*/
++	val[3] = odm_read_4byte(dm, R_0xde0); /*@ Acq CFO*/
++	val[4] = odm_read_4byte(dm, R_0xdbc); /*@ End CFO*/
++
++	/*@[path-A]*/
++	if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
++		val_tmp = (val[0] & 0x0fff0000) >> 16; /*@ Short CFO, S(12,11)*/
++		cfo->cfo_rpt_s[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
++		val_tmp = (val[1] & 0x0fff0000) >> 16;	/*@ Long CFO, S(12,11)*/
++		cfo->cfo_rpt_l[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
++		val_tmp = (val[2] & 0x0fff0000) >> 16;	/*@ Sec CFO, S(12,11)*/
++		cfo->cfo_rpt_sec[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
++		val_tmp = (val[3] & 0x0fff0000) >> 16;	/*@ Acq CFO, S(12,11)*/
++		cfo->cfo_rpt_acq[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
++		val_tmp = (val[4] & 0x0fff0000) >> 16;	/*@ Acq CFO, S(12,11)*/
++		cfo->cfo_rpt_end[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
++	} else {
++		val_tmp = (val[0] & 0x0fff0000) >> 16; /*@ Short CFO, S(12,11)*/
++		cfo->cfo_rpt_s[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
++		val_tmp = (val[1] & 0x1fff0000) >> 16;	/*@ Long CFO, S(13,12)*/
++		cfo->cfo_rpt_l[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
++		val_tmp = (val[2] & 0x7ff0000) >> 16;	/*@ Sec CFO, S(11,10)*/
++		cfo->cfo_rpt_sec[0] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);
++		val_tmp = (val[3] & 0x1fff0000) >> 16;	/*@ Acq CFO, S(13,12)*/
++		cfo->cfo_rpt_acq[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
++		val_tmp = (val[4] & 0x1fff0000) >> 16;	/*@ Acq CFO, S(13,12)*/
++		cfo->cfo_rpt_end[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
++	}
++
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	/*@[path-B]*/
++	val_tmp = val[0] & 0xfff;		/*@ Short CFO, S(12,11)*/
++	cfo->cfo_rpt_s[1] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
++	val_tmp = val[1] & 0x1fff;		/*@ Long CFO, S(13,12)*/
++	cfo->cfo_rpt_l[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
++	val_tmp = val[2] & 0x7ff;		/*@ Sec CFO, S(11,10)*/
++	cfo->cfo_rpt_sec[1] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);
++	val_tmp = val[3] & 0x1fff;		/*@ Acq CFO, S(13,12)*/
++	cfo->cfo_rpt_acq[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
++	val_tmp = val[4] & 0x1fff;		/*@ Acq CFO, S(13,12)*/
++	cfo->cfo_rpt_end[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
++	#endif
++}
++
++void phydm_set_atc_status(void *dm_void, boolean atc_status)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
++	u32 reg_tmp = 0;
++	u32 mask_tmp = 0;
++
++	PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]ATC_en=%d\n", __func__, atc_status);
++
++	if (cfo_track->is_atc_status == atc_status)
++		return;
++
++	reg_tmp = ODM_REG(BB_ATC, dm);
++	mask_tmp = ODM_BIT(BB_ATC, dm);
++	odm_set_bb_reg(dm, reg_tmp, mask_tmp, atc_status);
++	cfo_track->is_atc_status = atc_status;
++}
++
++boolean
++phydm_get_atc_status(void *dm_void)
++{
++	boolean atc_status = false;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 reg_tmp = 0;
++	u32 mask_tmp = 0;
++
++	reg_tmp = ODM_REG(BB_ATC, dm);
++	mask_tmp = ODM_BIT(BB_ATC, dm);
++
++	atc_status = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
++
++	PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]atc_status=%d\n", __func__, atc_status);
++	return atc_status;
++}
++#endif
++
++void phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	switch (dm->ic_ip_series) {
++	#if (ODM_IC_11N_SERIES_SUPPORT)
++	case PHYDM_IC_N:
++		phydm_get_cfo_info_n(dm, cfo);
++		break;
++	#endif
++	#if (ODM_IC_11AC_SERIES_SUPPORT)
++	case PHYDM_IC_AC:
++		phydm_get_cfo_info_ac(dm, cfo);
++		break;
++	#endif
++	default:
++		break;
++	}
++}
++
++boolean
++phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
++	u32 reg_val = 0;
++
++	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |
++	    ODM_RTL8195B | ODM_RTL8812F | ODM_RTL8721D | ODM_RTL8710C)) {
++		crystal_cap &= 0x7F;
++		reg_val = crystal_cap | (crystal_cap << 7);
++	} else {
++		crystal_cap &= 0x3F;
++		reg_val = crystal_cap | (crystal_cap << 6);
++	}
++
++	cfo_track->crystal_cap = crystal_cap;
++
++	if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) {
++		#if (RTL8188E_SUPPORT || RTL8188F_SUPPORT)
++		/* write 0x24[22:17] = 0x24[16:11] = crystal_cap */
++		odm_set_mac_reg(dm, R_0x24, 0x7ff800, reg_val);
++		#endif
++	}
++	#if (RTL8812A_SUPPORT)
++	else if (dm->support_ic_type & ODM_RTL8812) {
++		/* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */
++		odm_set_mac_reg(dm, R_0x2c, 0x7FF80000, reg_val);
++	}
++	#endif
++	#if (RTL8703B_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\
++	     RTL8821A_SUPPORT || RTL8723D_SUPPORT)
++	else if ((dm->support_ic_type &
++		 (ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8192E | ODM_RTL8821 |
++		 ODM_RTL8723D))) {
++		/* @0x2C[23:18] = 0x2C[17:12] = crystal_cap */
++		odm_set_mac_reg(dm, R_0x2c, 0x00FFF000, reg_val);
++	}
++	#endif
++	#if (RTL8814A_SUPPORT)
++	else if (dm->support_ic_type & ODM_RTL8814A) {
++		/* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */
++		odm_set_mac_reg(dm, R_0x2c, 0x07FF8000, reg_val);
++	}
++	#endif
++	#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8197F_SUPPORT ||\
++	     RTL8192F_SUPPORT || RTL8197G_SUPPORT)
++	else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C |
++		 ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8197G)) {
++		/* write 0x24[30:25] = 0x28[6:1] = crystal_cap */
++		odm_set_mac_reg(dm, R_0x24, 0x7e000000, crystal_cap);
++		odm_set_mac_reg(dm, R_0x28, 0x7e, crystal_cap);
++	}
++	#endif
++	#if (RTL8710B_SUPPORT)
++	else if (dm->support_ic_type & (ODM_RTL8710B)) {
++		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++		/* write 0x60[29:24] = 0x60[23:18] = crystal_cap */
++		HAL_SetSYSOnReg(dm->adapter, R_0x60, 0x3FFC0000, reg_val);
++		#endif
++	}
++	#endif
++	#if (RTL8195B_SUPPORT)
++	else if (dm->support_ic_type & ODM_RTL8195B) {
++		phydm_set_crystalcap(dm, (u8)(reg_val & 0x7f));
++	}
++	#endif
++	#if (RTL8721D_SUPPORT)
++	else if (dm->support_ic_type & (ODM_RTL8721D)) {
++		/* write 0x4800_0228[30:24] crystal_cap */
++		/*HAL_SetSYSOnReg(dm->adapter, */
++		/*REG_SYS_XTAL_8721d, 0x7F000000, crystal_cap);*/
++		u32 temp_val = HAL_READ32(SYSTEM_CTRL_BASE_LP,
++					   REG_SYS_EFUSE_SYSCFG2);
++		temp_val = ((crystal_cap << 24) & 0x7F000000)
++						| (temp_val & (~0x7F000000));
++		HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_SYS_EFUSE_SYSCFG2,
++			    temp_val);
++	}
++	#endif
++	#if (RTL8710C_SUPPORT)
++	else if (dm->support_ic_type & (ODM_RTL8710C)) {
++		/* write MAC reg 0x28[13:7][6:0] crystal_cap */
++		phydm_set_crystalcap(dm, (u8)(reg_val & 0x7f));
++	}
++	#endif
++
++#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)
++	else if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |
++		 ODM_RTL8812F)) {
++		/* write 0x1040[23:17] = 0x1040[16:10] = crystal_cap */
++		odm_set_mac_reg(dm, R_0x1040, 0x00FFFC00, reg_val);
++	} else {
++		return false;
++	}
++#endif
++	return true;
++}
++
++void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
++
++	if (cfo_track->crystal_cap == crystal_cap)
++		return;
++
++	if (phydm_set_crystal_cap_reg(dm, crystal_cap))
++		PHYDM_DBG(dm, DBG_CFO_TRK, "Set crystal_cap = 0x%x\n",
++			  cfo_track->crystal_cap);
++	else
++		PHYDM_DBG(dm, DBG_CFO_TRK, "Set fail\n");
++}
++
++void phydm_cfo_tracking_reset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
++
++	PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__);
++
++	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8195B |
++	    ODM_RTL8812F))
++		cfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x7f;
++	else
++		cfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x3f;
++
++	cfo_track->is_adjust = true;
++
++	if (cfo_track->crystal_cap > cfo_track->def_x_cap) {
++		phydm_set_crystal_cap(dm, cfo_track->crystal_cap - 1);
++		PHYDM_DBG(dm, DBG_CFO_TRK, "approch to Init-val (0x%x)\n",
++			  cfo_track->crystal_cap);
++
++	} else if (cfo_track->crystal_cap < cfo_track->def_x_cap) {
++		phydm_set_crystal_cap(dm, cfo_track->crystal_cap + 1);
++		PHYDM_DBG(dm, DBG_CFO_TRK, "approch to init-val 0x%x\n",
++			  cfo_track->crystal_cap);
++	}
++
++#if ODM_IC_11N_SERIES_SUPPORT
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	if (dm->support_ic_type & ODM_IC_11N_SERIES)
++		phydm_set_atc_status(dm, true);
++#endif
++#endif
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_AP))
++	if (dm->support_ic_type & ODM_RTL8814B) {
++		/*Disable advance time for CFO residual*/
++		odm_set_bb_reg(dm, R_0xc2c, BIT29, 0x0);
++	}
++#endif
++#endif
++}
++
++void phydm_cfo_tracking_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
++
++	PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]=========>\n", __func__);
++	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8195B |
++	    ODM_RTL8812F))
++		cfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x7f;
++	else
++		cfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x3f;
++
++	cfo_track->def_x_cap = cfo_track->crystal_cap;
++	cfo_track->is_adjust = true;
++	PHYDM_DBG(dm, DBG_CFO_TRK, "crystal_cap=0x%x\n", cfo_track->def_x_cap);
++
++#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
++	/* @Crystal cap. control by WiFi */
++	if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C))
++		odm_set_mac_reg(dm, R_0x10, 0x40, 0x1);
++#endif
++}
++
++void phydm_cfo_tracking(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
++	s32 cfo_avg = 0, cfo_path_sum = 0, cfo_abs = 0;
++	u32 cfo_rpt_sum = 0, cfo_khz_avg[4] = {0};
++	s8 crystal_cap = cfo_track->crystal_cap;
++	u8 i = 0, valid_path_cnt = 0;
++
++	if (!(dm->support_ability & ODM_BB_CFO_TRACKING))
++		return;
++
++	PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__);
++
++	if (!dm->is_linked || !dm->is_one_entry_only) {
++		phydm_cfo_tracking_reset(dm);
++		PHYDM_DBG(dm, DBG_CFO_TRK, "is_linked=%d, one_entry_only=%d\n",
++			  dm->is_linked, dm->is_one_entry_only);
++
++	} else {
++		/* No new packet */
++		if (cfo_track->packet_count == cfo_track->packet_count_pre) {
++			PHYDM_DBG(dm, DBG_CFO_TRK, "Pkt cnt doesn't change\n");
++			return;
++		}
++		cfo_track->packet_count_pre = cfo_track->packet_count;
++
++		/*@Calculate CFO */
++		for (i = 0; i < dm->num_rf_path; i++) {
++			if (!(dm->rx_ant_status & BIT(i)))
++				continue;
++
++			valid_path_cnt++;
++
++			if (cfo_track->CFO_tail[i] < 0)
++				cfo_abs = 0 - cfo_track->CFO_tail[i];
++			else
++				cfo_abs = cfo_track->CFO_tail[i];
++
++			cfo_rpt_sum = (u32)CFO_HW_RPT_2_KHZ(cfo_abs);
++			cfo_khz_avg[i] = PHYDM_DIV(cfo_rpt_sum,
++						   cfo_track->CFO_cnt[i]);
++
++			PHYDM_DBG(dm, DBG_CFO_TRK,
++				  "[Path-%d] CFO_sum=((%d)), cnt=((%d)), CFO_avg=((%s%d))kHz\n",
++				  i, cfo_rpt_sum, cfo_track->CFO_cnt[i],
++				  ((cfo_track->CFO_tail[i] < 0) ? "-" : " "),
++				  cfo_khz_avg[i]);
++
++			if (cfo_track->CFO_tail[i] < 0)
++				cfo_path_sum += (0 - (s32)cfo_khz_avg[i]);
++			else
++				cfo_path_sum += (s32)cfo_khz_avg[i];
++		}
++
++		if (valid_path_cnt >= 2)
++			cfo_avg = cfo_path_sum / valid_path_cnt;
++		else
++			cfo_avg = cfo_path_sum;
++
++		cfo_track->CFO_ave_pre = cfo_avg;
++
++		PHYDM_DBG(dm, DBG_CFO_TRK, "path_cnt=%d, CFO_avg_path=%d kHz\n",
++			  valid_path_cnt, cfo_avg);
++
++		/*reset counter*/
++		for (i = 0; i < dm->num_rf_path; i++) {
++			cfo_track->CFO_tail[i] = 0;
++			cfo_track->CFO_cnt[i] = 0;
++		}
++
++		/* To adjust crystal cap or not */
++		if (!cfo_track->is_adjust) {
++			if (cfo_avg > CFO_TRK_ENABLE_TH ||
++			    cfo_avg < (-CFO_TRK_ENABLE_TH))
++				cfo_track->is_adjust = true;
++		} else {
++			if (cfo_avg <= CFO_TRK_STOP_TH &&
++			    cfo_avg >= (-CFO_TRK_STOP_TH))
++				cfo_track->is_adjust = false;
++		}
++
++		#ifdef ODM_CONFIG_BT_COEXIST
++		/*@BT case: Disable CFO tracking */
++		if (dm->bt_info_table.is_bt_enabled) {
++			cfo_track->is_adjust = false;
++			phydm_set_crystal_cap(dm, cfo_track->def_x_cap);
++			PHYDM_DBG(dm, DBG_CFO_TRK, "[BT]Disable CFO_track\n");
++		}
++		#endif
++
++		/*@Adjust Crystal Cap. */
++		if (cfo_track->is_adjust) {
++			if (cfo_avg > CFO_TRK_STOP_TH)
++				crystal_cap += 1;
++			else if (cfo_avg < (-CFO_TRK_STOP_TH))
++				crystal_cap -= 1;
++
++			if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |
++			    ODM_RTL8195B | ODM_RTL8812F)) {
++				if (crystal_cap > 0x7F)
++					crystal_cap = 0x7F;
++			} else {
++				if (crystal_cap > 0x3F)
++					crystal_cap = 0x3F;
++			}
++			if (crystal_cap < 0)
++				crystal_cap = 0;
++
++			phydm_set_crystal_cap(dm, (u8)crystal_cap);
++		}
++
++		PHYDM_DBG(dm, DBG_CFO_TRK, "X_cap{Curr,Default}={0x%x,0x%x}\n",
++			  cfo_track->crystal_cap, cfo_track->def_x_cap);
++
++		/* @Dynamic ATC switch */
++		#if ODM_IC_11N_SERIES_SUPPORT
++		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++		if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++			if (cfo_avg < CFO_TH_ATC && cfo_avg > -CFO_TH_ATC)
++				phydm_set_atc_status(dm, false);
++			else
++				phydm_set_atc_status(dm, true);
++
++		}
++		#endif
++		#endif
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_AP))
++		if (dm->support_ic_type & ODM_RTL8814B) {
++			//Disable advance time for CFO residual
++			odm_set_bb_reg(dm, R_0xc2c, BIT29, 0x0);
++		}
++		#endif
++		#endif
++	}
++}
++
++void phydm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail,
++		       u8 num_ss)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_perpkt_info_struct *pktinfo = NULL;
++	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
++	boolean valid_info = false;
++	u8 i = 0;
++
++	if (!(dm->support_ability & ODM_BB_CFO_TRACKING))
++		return;
++
++	pktinfo = (struct phydm_perpkt_info_struct *)pktinfo_void;
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
++	if (pktinfo->is_packet_match_bssid)
++		valid_info = true;
++#else
++	if (dm->number_active_client == 1)
++		valid_info = true;
++#endif
++	if (valid_info) {
++		if (num_ss > dm->num_rf_path) /*@For fool proof*/
++			num_ss = dm->num_rf_path;
++		#if 0
++		PHYDM_DBG(dm, DBG_CFO_TRK, "num_ss=%d, num_rf_path=%d\n",
++			  num_ss, dm->num_rf_path);
++		#endif
++
++		/* @ Update CFO report for path-A & path-B */
++		/* Only paht-A and path-B have CFO tail and short CFO */
++		for (i = 0; i < dm->num_rf_path; i++) {
++			if (!(dm->rx_ant_status & BIT(i)))
++				continue;
++			cfo_track->CFO_tail[i] += pcfotail[i];
++			cfo_track->CFO_cnt[i]++;
++			#if 0
++			PHYDM_DBG(dm, DBG_CFO_TRK,
++				  "[ID %d][path %d][rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\n",
++				  pktinfo->station_id, i, pktinfo->data_rate,
++				  pcfotail[i], cfo_track->CFO_tail[i],
++				  cfo_track->CFO_cnt[i]);
++			#endif
++		}
++
++		/* @ Update packet counter */
++		if (cfo_track->packet_count == 0xffffffff)
++			cfo_track->packet_count = 0;
++		else
++			cfo_track->packet_count++;
++	}
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void phy_Init_crystal_capacity(void *dm_void, u8 crystal_cap)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (!phydm_set_crystal_cap_reg(dm, crystal_cap))
++		RT_TRACE_F(COMP_INIT, DBG_SERIOUS,
++			   ("Crystal is not initialized!\n"));
++}
++#endif
++
++void phydm_cfo_tracking_debug(void *dm_void, char input[][16], u32 *_used,
++			      char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "set Xcap: {1}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "show Xcap: {100}\n");
++	} else {
++		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
++
++		if (var1[0] == 1) {
++			PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);
++			phydm_set_crystal_cap(dm, (u8)var1[1]);
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "Set X_cap=0x%x\n", cfo_track->crystal_cap);
++		} else if (var1[0] == 100) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "X_cap=0x%x\n", cfo_track->crystal_cap);
++		}
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cfotracking.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cfotracking.h
+new file mode 100644
+index 000000000..253f3ba3e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_cfotracking.h
+@@ -0,0 +1,74 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDMCFOTRACK_H__
++#define __PHYDMCFOTRACK_H__
++
++/* 2019.03.28 fix 8197G crystal_cap register address*/
++#define CFO_TRACKING_VERSION "2.4"
++
++#define		CFO_TRK_ENABLE_TH	20 /* @kHz enable CFO_Track threshold*/
++#define		CFO_TRK_STOP_TH		10 /* @kHz disable CFO_Track threshold*/
++#define		CFO_TH_ATC		80 /* @kHz */
++
++struct phydm_cfo_track_struct {
++	boolean		is_atc_status;
++	boolean		is_adjust;	/*@already modify crystal cap*/
++	u8		crystal_cap;
++	u8		crystal_cap_default;
++	u8		def_x_cap;
++	s32		CFO_tail[4];
++	u32		CFO_cnt[4];
++	s32		CFO_ave_pre;
++	u32		packet_count;
++	u32		packet_count_pre;
++};
++
++struct phydm_cfo_rpt {
++	s32 cfo_rpt_s[PHYDM_MAX_RF_PATH];
++	s32 cfo_rpt_l[PHYDM_MAX_RF_PATH];
++	s32 cfo_rpt_acq[PHYDM_MAX_RF_PATH];
++	s32 cfo_rpt_sec[PHYDM_MAX_RF_PATH];
++	s32 cfo_rpt_end[PHYDM_MAX_RF_PATH];
++};
++
++void phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo);
++
++boolean phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap);
++
++void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap);
++
++void phydm_cfo_tracking_init(void *dm_void);
++
++void phydm_cfo_tracking(void *dm_void);
++
++void phydm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail,
++		       u8 num_ss);
++void phydm_cfo_tracking_debug(void *dm_void, char input[][16], u32 *_used,
++			      char *output, u32 *_out_len);
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void phy_Init_crystal_capacity(void *dm_void, u8 crystal_cap);
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_debug.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_debug.c
+new file mode 100644
+index 000000000..897d65446
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_debug.c
+@@ -0,0 +1,5864 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ ************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++void phydm_init_debug_setting(struct dm_struct *dm)
++{
++	dm->fw_debug_components = 0;
++	dm->debug_components =
++
++#if DBG
++	/*@BB Functions*/
++	/*@DBG_DIG					|*/
++	/*@DBG_RA_MASK					|*/
++	/*@DBG_DYN_TXPWR				|*/
++	/*@DBG_FA_CNT					|*/
++	/*@DBG_RSSI_MNTR				|*/
++	/*@DBG_CCKPD					|*/
++	/*@DBG_ANT_DIV					|*/
++	/*@DBG_SMT_ANT					|*/
++	/*@DBG_PWR_TRAIN				|*/
++	/*@DBG_RA					|*/
++	/*@DBG_PATH_DIV					|*/
++	/*@DBG_DFS					|*/
++	/*@DBG_DYN_ARFR					|*/
++	/*@DBG_ADPTVTY					|*/
++	/*@DBG_CFO_TRK					|*/
++	/*@DBG_ENV_MNTR					|*/
++	/*@DBG_PRI_CCA					|*/
++	/*@DBG_ADPTV_SOML				|*/
++	/*@DBG_LNA_SAT_CHK				|*/
++	/*@DBG_PHY_STATUS				|*/
++	/*@DBG_TMP					|*/
++	/*@DBG_FW_TRACE					|*/
++	/*@DBG_TXBF					|*/
++	/*@DBG_COMMON_FLOW				|*/
++	/*@ODM_PHY_CONFIG				|*/
++	/*@ODM_COMP_INIT				|*/
++	/*@DBG_CMN					|*/
++	/*@ODM_COMP_API					|*/
++#endif
++	0;
++
++	dm->fw_buff_is_enpty = true;
++	dm->pre_c2h_seq = 0;
++	dm->c2h_cmd_start = 0;
++	dm->cmn_dbg_msg_cnt = PHYDM_WATCH_DOG_PERIOD;
++	dm->cmn_dbg_msg_period = PHYDM_WATCH_DOG_PERIOD;
++	phydm_reset_rx_rate_distribution(dm);
++}
++
++void phydm_bb_dbg_port_header_sel(void *dm_void, u32 header_idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		odm_set_bb_reg(dm, R_0x8f8, 0x3c00000, header_idx);
++
++		/*@
++		 * header_idx:
++		 *	(0:) '{ofdm_dbg[31:0]}'
++		 *	(1:) '{cca,crc32_fail,dbg_ofdm[29:0]}'
++		 *	(2:) '{vbon,crc32_fail,dbg_ofdm[29:0]}'
++		 *	(3:) '{cca,crc32_ok,dbg_ofdm[29:0]}'
++		 *	(4:) '{vbon,crc32_ok,dbg_ofdm[29:0]}'
++		 *	(5:) '{dbg_iqk_anta}'
++		 *	(6:) '{cca,ofdm_crc_ok,dbg_dp_anta[29:0]}'
++		 *	(7:) '{dbg_iqk_antb}'
++		 *	(8:) '{DBGOUT_RFC_b[31:0]}'
++		 *	(9:) '{DBGOUT_RFC_a[31:0]}'
++		 *	(a:) '{dbg_ofdm}'
++		 *	(b:) '{dbg_cck}'
++		 */
++	}
++}
++
++void phydm_bb_dbg_port_clock_en(void *dm_void, u8 enable)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 reg_value = 0;
++
++	if (dm->support_ic_type & ODM_IC_11AC_2_SERIES) {
++		/*@enable/disable debug port clock, for power saving*/
++		reg_value = enable ? 0x7 : 0;
++		odm_set_bb_reg(dm, R_0x198c, 0x7, reg_value);
++	}
++}
++
++u32 phydm_get_bb_dbg_port_idx(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 val = 0;
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		phydm_bb_dbg_port_clock_en(dm, true);
++		val = odm_get_bb_reg(dm, R_0x8fc, MASKDWORD);
++	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		val = odm_get_bb_reg(dm, R_0x1c3c, 0xfff00);
++	} else { /*@if (dm->support_ic_type & ODM_IC_11N_SERIES)*/
++		val = odm_get_bb_reg(dm, R_0x908, MASKDWORD);
++	}
++	return val;
++}
++
++u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 dbg_port_result = false;
++
++	if (curr_dbg_priority > dm->pre_dbg_priority) {
++		if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++			phydm_bb_dbg_port_clock_en(dm, true);
++
++			odm_set_bb_reg(dm, R_0x8fc, MASKDWORD, debug_port);
++		} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++			odm_set_bb_reg(dm, R_0x1c3c, 0xfff00, debug_port);
++
++		} else { /*@if (dm->support_ic_type & ODM_IC_11N_SERIES)*/
++			odm_set_bb_reg(dm, R_0x908, MASKDWORD, debug_port);
++		}
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "DbgPort ((0x%x)) set success, Cur_priority=((%d)), Pre_priority=((%d))\n",
++			  debug_port, curr_dbg_priority, dm->pre_dbg_priority);
++		dm->pre_dbg_priority = curr_dbg_priority;
++		dbg_port_result = true;
++	}
++
++	return dbg_port_result;
++}
++
++void phydm_release_bb_dbg_port(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	phydm_bb_dbg_port_clock_en(dm, false);
++	phydm_bb_dbg_port_header_sel(dm, 0);
++
++	dm->pre_dbg_priority = DBGPORT_RELEASE;
++	PHYDM_DBG(dm, ODM_COMP_API, "Release BB dbg_port\n");
++}
++
++u32 phydm_get_bb_dbg_port_val(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 dbg_port_value = 0;
++
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
++		dbg_port_value = odm_get_bb_reg(dm, R_0xfa0, MASKDWORD);
++	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		dbg_port_value = odm_get_bb_reg(dm, R_0x2dbc, MASKDWORD);
++	else /*@if (dm->support_ic_type & ODM_IC_11N_SERIES)*/
++		dbg_port_value = odm_get_bb_reg(dm, R_0xdf4, MASKDWORD);
++
++	PHYDM_DBG(dm, ODM_COMP_API, "dbg_port_value = 0x%x\n", dbg_port_value);
++	return dbg_port_value;
++}
++
++#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
++#if (ODM_IC_11N_SERIES_SUPPORT)
++void phydm_bb_hw_dbg_info_n(void *dm_void, u32 *_used, char *output,
++			    u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 value32 = 0, value32_1 = 0;
++	u8 rf_gain_a = 0, rf_gain_b = 0, rf_gain_c = 0, rf_gain_d = 0;
++	u8 rx_snr_a = 0, rx_snr_b = 0, rx_snr_c = 0, rx_snr_d = 0;
++	s8 rxevm_0 = 0, rxevm_1 = 0;
++	#if 1
++	struct phydm_cfo_rpt cfo;
++	u8 i = 0;
++	#else
++	s32 short_cfo_a = 0, short_cfo_b = 0, long_cfo_a = 0, long_cfo_b = 0;
++	s32 scfo_a = 0, scfo_b = 0, avg_cfo_a = 0, avg_cfo_b = 0;
++	s32 cfo_end_a = 0, cfo_end_b = 0, acq_cfo_a = 0, acq_cfo_b = 0;
++	#endif
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s\n",
++		 "BB Report Info");
++
++	/*@AGC result*/
++	value32 = odm_get_bb_reg(dm, R_0xdd0, MASKDWORD);
++	rf_gain_a = (u8)(value32 & 0x3f);
++	rf_gain_a = rf_gain_a << 1;
++
++	rf_gain_b = (u8)((value32 >> 8) & 0x3f);
++	rf_gain_b = rf_gain_b << 1;
++
++	rf_gain_c = (u8)((value32 >> 16) & 0x3f);
++	rf_gain_c = rf_gain_c << 1;
++
++	rf_gain_d = (u8)((value32 >> 24) & 0x3f);
++	rf_gain_d = rf_gain_d << 1;
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)",
++		 rf_gain_a, rf_gain_b, rf_gain_c, rf_gain_d);
++
++	/*SNR report*/
++	value32 = odm_get_bb_reg(dm, R_0xdd4, MASKDWORD);
++	rx_snr_a = (u8)(value32 & 0xff);
++	rx_snr_a = rx_snr_a >> 1;
++
++	rx_snr_b = (u8)((value32 >> 8) & 0xff);
++	rx_snr_b = rx_snr_b >> 1;
++
++	rx_snr_c = (u8)((value32 >> 16) & 0xff);
++	rx_snr_c = rx_snr_c >> 1;
++
++	rx_snr_d = (u8)((value32 >> 24) & 0xff);
++	rx_snr_d = rx_snr_d >> 1;
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)",
++		 rx_snr_a, rx_snr_b, rx_snr_c, rx_snr_d);
++
++	/* PostFFT related info*/
++	value32 = odm_get_bb_reg(dm, R_0xdd8, MASKDWORD);
++
++	rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16);
++	rxevm_0 /= 2;
++	if (rxevm_0 < -63)
++		rxevm_0 = 0;
++
++	rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24);
++	rxevm_1 /= 2;
++	if (rxevm_1 < -63)
++		rxevm_1 = 0;
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d", "RXEVM (1ss/2ss)", rxevm_0, rxevm_1);
++
++#if 1
++	phydm_get_cfo_info(dm, &cfo);
++	for (i = 0; i < dm->num_rf_path; i++) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %s[%d] %-28s = {%d, %d, %d, %d, %d}",
++			 "CFO", i, "{S, L, Sec, Acq, End}",
++			 cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i], cfo.cfo_rpt_sec[i],
++			 cfo.cfo_rpt_acq[i], cfo.cfo_rpt_end[i]);
++	}
++#else
++	/*@CFO Report Info*/
++	odm_set_bb_reg(dm, R_0xd00, BIT(26), 1);
++
++	/*Short CFO*/
++	value32 = odm_get_bb_reg(dm, R_0xdac, MASKDWORD);
++	value32_1 = odm_get_bb_reg(dm, R_0xdb0, MASKDWORD);
++
++	short_cfo_b = (s32)(value32 & 0xfff); /*S(12,11)*/
++	short_cfo_a = (s32)((value32 & 0x0fff0000) >> 16);
++
++	long_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/
++	long_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);
++
++	/*SFO 2's to dec*/
++	if (short_cfo_a > 2047)
++		short_cfo_a = short_cfo_a - 4096;
++	if (short_cfo_b > 2047)
++		short_cfo_b = short_cfo_b - 4096;
++
++	short_cfo_a = (short_cfo_a * 312500) / 2048;
++	short_cfo_b = (short_cfo_b * 312500) / 2048;
++
++	/*@LFO 2's to dec*/
++
++	if (long_cfo_a > 4095)
++		long_cfo_a = long_cfo_a - 8192;
++
++	if (long_cfo_b > 4095)
++		long_cfo_b = long_cfo_b - 8192;
++
++	long_cfo_a = long_cfo_a * 312500 / 4096;
++	long_cfo_b = long_cfo_b * 312500 / 4096;
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s",
++		 "CFO Report Info");
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d", "Short CFO(Hz) <A/B>", short_cfo_a,
++		 short_cfo_b);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d", "Long CFO(Hz) <A/B>", long_cfo_a,
++		 long_cfo_b);
++
++	/*SCFO*/
++	value32 = odm_get_bb_reg(dm, R_0xdb8, MASKDWORD);
++	value32_1 = odm_get_bb_reg(dm, R_0xdb4, MASKDWORD);
++
++	scfo_b = (s32)(value32 & 0x7ff); /*S(11,10)*/
++	scfo_a = (s32)((value32 & 0x07ff0000) >> 16);
++
++	if (scfo_a > 1023)
++		scfo_a = scfo_a - 2048;
++
++	if (scfo_b > 1023)
++		scfo_b = scfo_b - 2048;
++
++	scfo_a = scfo_a * 312500 / 1024;
++	scfo_b = scfo_b * 312500 / 1024;
++
++	avg_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/
++	avg_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);
++
++	if (avg_cfo_a > 4095)
++		avg_cfo_a = avg_cfo_a - 8192;
++
++	if (avg_cfo_b > 4095)
++		avg_cfo_b = avg_cfo_b - 8192;
++
++	avg_cfo_a = avg_cfo_a * 312500 / 4096;
++	avg_cfo_b = avg_cfo_b * 312500 / 4096;
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d", "value SCFO(Hz) <A/B>", scfo_a,
++		 scfo_b);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d", "Avg CFO(Hz) <A/B>", avg_cfo_a,
++		 avg_cfo_b);
++
++	value32 = odm_get_bb_reg(dm, R_0xdbc, MASKDWORD);
++	value32_1 = odm_get_bb_reg(dm, R_0xde0, MASKDWORD);
++
++	cfo_end_b = (s32)(value32 & 0x1fff); /*S(13,12)*/
++	cfo_end_a = (s32)((value32 & 0x1fff0000) >> 16);
++
++	if (cfo_end_a > 4095)
++		cfo_end_a = cfo_end_a - 8192;
++
++	if (cfo_end_b > 4095)
++		cfo_end_b = cfo_end_b - 8192;
++
++	cfo_end_a = cfo_end_a * 312500 / 4096;
++	cfo_end_b = cfo_end_b * 312500 / 4096;
++
++	acq_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/
++	acq_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);
++
++	if (acq_cfo_a > 4095)
++		acq_cfo_a = acq_cfo_a - 8192;
++
++	if (acq_cfo_b > 4095)
++		acq_cfo_b = acq_cfo_b - 8192;
++
++	acq_cfo_a = acq_cfo_a * 312500 / 4096;
++	acq_cfo_b = acq_cfo_b * 312500 / 4096;
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d", "End CFO(Hz) <A/B>", cfo_end_a,
++		 cfo_end_b);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d", "ACQ CFO(Hz) <A/B>", acq_cfo_a,
++		 acq_cfo_b);
++#endif
++}
++#endif
++
++#if (ODM_IC_11AC_SERIES_SUPPORT)
++#if (RTL8822B_SUPPORT)
++void phydm_bb_hw_dbg_info_8822b(void *dm_void, u32 *_used, char *output,
++				u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 condi_num = 0;
++	u8 i = 0;
++
++	if (!(dm->support_ic_type == ODM_RTL8822B))
++		return;
++
++	condi_num = phydm_get_condi_num_8822b(dm);
++	phydm_get_condi_num_acc_8822b(dm);
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d.%.4d", "condi_num",
++		 condi_num >> 4, phydm_show_fraction_num(condi_num & 0xf, 4));
++
++	for (i = 0; i < CN_CNT_MAX; i++) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n Tone_num[CN>%d]%-21s = %d",
++			 i, " ", dm->phy_dbg_info.condi_num_cdf[i]);
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++#endif
++
++void phydm_bb_hw_dbg_info_ac(void *dm_void, u32 *_used, char *output,
++			     u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	char *tmp_string = NULL;
++	u8 rx_ht_bw, rx_vht_bw, rxsc, rx_ht, bw_idx = 0;
++	static u8 v_rx_bw;
++	u32 value32, value32_1, value32_2, value32_3;
++	struct phydm_cfo_rpt cfo;
++	u8 i = 0;
++	static u8 tail, parity, rsv, vrsv, smooth, htsound, agg;
++	static u8 stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, v_nsts;
++	static u8 vtxops, vrsv2, vbrsv, bf, vbcrc;
++	static u16 h_length, htcrc8, length;
++	static u16 vpaid;
++	static u16 v_length, vhtcrc8, v_mcss, v_tail, vb_tail;
++	static u8 hmcss, hrx_bw;
++	u8 pwdb;
++	s8 rxevm_0, rxevm_1, rxevm_2;
++	u8 rf_gain[4];
++	u8 rx_snr[4];
++	s32 sig_power;
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s\n",
++		 "BB Report Info");
++
++	/*@ [BW & Mode] =====================================================*/
++
++	value32 = odm_get_bb_reg(dm, R_0xf80, MASKDWORD);
++	rx_ht = (u8)((value32 & 0x180) >> 7);
++
++	if (rx_ht == AD_VHT_MODE) {
++		tmp_string = "VHT";
++		bw_idx = (u8)((value32 >> 1) & 0x3);
++	} else if (rx_ht == AD_HT_MODE) {
++		tmp_string = "HT";
++		bw_idx = (u8)(value32 & 0x1);
++	} else {
++		tmp_string = "Legacy";
++		bw_idx = 0;
++	}
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s %s %dM", "mode", tmp_string, (20 << bw_idx));
++
++	if (rx_ht != AD_LEGACY_MODE) {
++		rxsc = (u8)(value32 & 0x78);
++
++		if (rxsc == 0)
++			tmp_string = "duplicate/full bw";
++		else if (rxsc == 1)
++			tmp_string = "usc20-1";
++		else if (rxsc == 2)
++			tmp_string = "lsc20-1";
++		else if (rxsc == 3)
++			tmp_string = "usc20-2";
++		else if (rxsc == 4)
++			tmp_string = "lsc20-2";
++		else if (rxsc == 9)
++			tmp_string = "usc40";
++		else if (rxsc == 10)
++			tmp_string = "lsc40";
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "  %-35s", tmp_string);
++	}
++
++	/*@ [RX signal power and AGC related info] ==========================*/
++
++	pwdb = (u8)odm_get_bb_reg(dm, R_0xf90, MASKBYTE1);
++	sig_power = -110 + (pwdb >> 1);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d", "OFDM RX Signal Power(dB)", sig_power);
++
++	value32 = odm_get_bb_reg(dm, R_0xd14, MASKDWORD);
++	rx_snr[RF_PATH_A] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/
++	rf_gain[RF_PATH_A] = (s8)(((value32 & MASKBYTE1) >> 8) * 2);
++
++	value32 = odm_get_bb_reg(dm, R_0xd54, MASKDWORD);
++	rx_snr[RF_PATH_B] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/
++	rf_gain[RF_PATH_B] = (s8)(((value32 & MASKBYTE1) >> 8) * 2);
++
++	value32 = odm_get_bb_reg(dm, R_0xd94, MASKDWORD);
++	rx_snr[RF_PATH_C] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/
++	rf_gain[RF_PATH_C] = (s8)(((value32 & MASKBYTE1) >> 8) * 2);
++
++	value32 = odm_get_bb_reg(dm, R_0xdd4, MASKDWORD);
++	rx_snr[RF_PATH_D] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/
++	rf_gain[RF_PATH_D] = (s8)(((value32 & MASKBYTE1) >> 8) * 2);
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)",
++		 rf_gain[RF_PATH_A], rf_gain[RF_PATH_B],
++		 rf_gain[RF_PATH_C], rf_gain[RF_PATH_D]);
++
++	/*@ [RX counter Info] ===============================================*/
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d", "OFDM CCA cnt",
++		 odm_get_bb_reg(dm, R_0xf08, 0xFFFF0000));
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d", "OFDM SBD Fail cnt",
++		 odm_get_bb_reg(dm, R_0xfd0, 0xFFFF));
++
++	value32 = odm_get_bb_reg(dm, R_0xfc4, MASKDWORD);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail cnt",
++		 value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16));
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d", "CCK CCA cnt",
++		 odm_get_bb_reg(dm, R_0xfcc, 0xFFFF));
++
++	value32 = odm_get_bb_reg(dm, R_0xfbc, MASKDWORD);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d",
++		 "LSIG (parity Fail/rate Illegal) cnt", value32 & 0xFFFF,
++		 ((value32 & 0xFFFF0000) >> 16));
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT cnt",
++		 odm_get_bb_reg(dm, R_0xfc0, (0xFFFF0000 >> 16)),
++		 odm_get_bb_reg(dm, R_0xfc8, 0xFFFF));
++
++	/*@ [PostFFT Info] =================================================*/
++	value32 = odm_get_bb_reg(dm, R_0xf8c, MASKDWORD);
++	rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16);
++	rxevm_0 /= 2;
++	if (rxevm_0 < -63)
++		rxevm_0 = 0;
++
++	rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24);
++	rxevm_1 /= 2;
++	value32 = odm_get_bb_reg(dm, R_0xf88, MASKDWORD);
++	rxevm_2 = (s8)((value32 & MASKBYTE2) >> 16);
++	rxevm_2 /= 2;
++
++	if (rxevm_1 < -63)
++		rxevm_1 = 0;
++	if (rxevm_2 < -63)
++		rxevm_2 = 0;
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d / %d", "RXEVM (1ss/2ss/3ss)", rxevm_0,
++		 rxevm_1, rxevm_2);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D dB)",
++		 rx_snr[RF_PATH_A], rx_snr[RF_PATH_B],
++		 rx_snr[RF_PATH_C], rx_snr[RF_PATH_D]);
++
++	value32 = odm_get_bb_reg(dm, R_0xf8c, MASKDWORD);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d", "CSI_1st /CSI_2nd", value32 & 0xFFFF,
++		 ((value32 & 0xFFFF0000) >> 16));
++
++	/*@ [CFO Report Info] ===============================================*/
++	phydm_get_cfo_info(dm, &cfo);
++	for (i = 0; i < dm->num_rf_path; i++) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %s[%d] %-28s = {%d, %d, %d, %d, %d}",
++			 "CFO", i, "{S, L, Sec, Acq, End}",
++			 cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i], cfo.cfo_rpt_sec[i],
++			 cfo.cfo_rpt_acq[i], cfo.cfo_rpt_end[i]);
++	}
++
++	/*@ [L-SIG Content] =================================================*/
++	value32 = odm_get_bb_reg(dm, R_0xf20, MASKDWORD);
++
++	tail = (u8)((value32 & 0xfc0000) >> 18);/*@[23:18]*/
++	parity = (u8)((value32 & 0x20000) >> 17);/*@[17]*/
++	length = (u16)((value32 & 0x1ffe0) >> 5);/*@[16:5]*/
++	rsv = (u8)((value32 & 0x10) >> 4);/*@[4]*/
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s",
++		 "L-SIG");
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d M", "rate",
++		 phydm_get_l_sig_rate(dm, (u8)(value32 & 0x0f)));
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %x / %d / %d", "Rsv/length/parity", rsv, length,
++		 parity);
++
++	if (rx_ht == AD_HT_MODE) {
++	/*@ [HT SIG 1] ======================================================*/
++		value32 = odm_get_bb_reg(dm, R_0xf2c, MASKDWORD);
++
++		hmcss = (u8)(value32 & 0x7F);
++		hrx_bw = (u8)((value32 & 0x80) >> 7);
++		h_length = (u16)((value32 & 0x0fff00) >> 8);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s", "HT-SIG1");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = %d / %d / %d", "MCS/BW/length",
++			 hmcss, hrx_bw, h_length);
++	/*@ [HT SIG 2] ======================================================*/
++		value32 = odm_get_bb_reg(dm, R_0xf30, MASKDWORD);
++		smooth = (u8)(value32 & 0x01);
++		htsound = (u8)((value32 & 0x02) >> 1);
++		rsv = (u8)((value32 & 0x04) >> 2);
++		agg = (u8)((value32 & 0x08) >> 3);
++		stbc = (u8)((value32 & 0x30) >> 4);
++		fec = (u8)((value32 & 0x40) >> 6);
++		sgi = (u8)((value32 & 0x80) >> 7);
++		htltf = (u8)((value32 & 0x300) >> 8);
++		htcrc8 = (u16)((value32 & 0x3fc00) >> 10);
++		tail = (u8)((value32 & 0xfc0000) >> 18);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s",
++			 "HT-SIG2");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = %x / %x / %x / %x / %x / %x",
++			 "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC",
++			 smooth, htsound, rsv, agg, stbc, fec);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = %x / %x / %x / %x",
++			 "SGI/E-HT-LTFs/CRC/tail",
++			 sgi, htltf, htcrc8, tail);
++	} else if (rx_ht == AD_VHT_MODE) {
++	/*@ [VHT SIG A1] ====================================================*/
++		value32 = odm_get_bb_reg(dm, R_0xf2c, MASKDWORD);
++
++		v_rx_bw = (u8)(value32 & 0x03);
++		vrsv = (u8)((value32 & 0x04) >> 2);
++		vstbc = (u8)((value32 & 0x08) >> 3);
++		vgid = (u8)((value32 & 0x3f0) >> 4);
++		v_nsts = (u8)(((value32 & 0x1c00) >> 10) + 1);
++		vpaid = (u16)((value32 & 0x3fe000) >> 13);
++		vtxops = (u8)((value32 & 0x400000) >> 22);
++		vrsv2 = (u8)((value32 & 0x800000) >> 23);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s",
++			 "VHT-SIG-A1");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x",
++			 "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", v_rx_bw,
++			 vrsv, vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2);
++
++	/*@ [VHT SIG A2] ====================================================*/
++		value32 = odm_get_bb_reg(dm, R_0xf30, MASKDWORD);
++
++		/* @sgi=(u8)(value32&0x01); */
++		sgiext = (u8)(value32 & 0x03);
++		/* @fec = (u8)(value32&0x04); */
++		fecext = (u8)((value32 & 0x0C) >> 2);
++
++		v_mcss = (u8)((value32 & 0xf0) >> 4);
++		bf = (u8)((value32 & 0x100) >> 8);
++		vrsv = (u8)((value32 & 0x200) >> 9);
++		vhtcrc8 = (u16)((value32 & 0x3fc00) >> 10);
++		v_tail = (u8)((value32 & 0xfc0000) >> 18);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s", "VHT-SIG-A2");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x",
++			 "SGI/FEC/MCS/BF/Rsv/CRC/tail",
++			 sgiext, fecext, v_mcss, bf, vrsv, vhtcrc8, v_tail);
++
++	/*@ [VHT SIG B] ====================================================*/
++		value32 = odm_get_bb_reg(dm, R_0xf34, MASKDWORD);
++
++		#if 0
++		v_length = (u16)(value32 & 0x1fffff);
++		vbrsv = (u8)((value32 & 0x600000) >> 21);
++		vb_tail = (u16)((value32 & 0x1f800000) >> 23);
++		vbcrc = (u8)((value32 & 0x80000000) >> 31);
++		#endif
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s", "VHT-SIG-B");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = %x",
++			 "Codeword", value32);
++
++		#if 0
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = %x / %x / %x / %x",
++			 "length/Rsv/tail/CRC",
++			 v_length, vbrsv, vb_tail, vbcrc);
++		#endif
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++#endif
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++void phydm_bb_hw_dbg_info_jgr3(void *dm_void, u32 *_used, char *output,
++			       u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	char *tmp_string = NULL;
++	u8 rx_ht_bw = 0, rx_vht_bw = 0, rx_ht = 0;
++	static u8 v_rx_bw;
++	u32 value32 = 0;
++	u8 i = 0;
++	static u8 tail, parity, rsv, vrsv, smooth, htsound, agg;
++	static u8 stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, v_nsts;
++	static u8 vtxops, vrsv2, vbrsv, bf, vbcrc;
++	static u16 h_length, htcrc8, length;
++	static u16 vpaid;
++	static u16 v_length, vhtcrc8, v_mcss, v_tail, vb_tail;
++	static u8 hmcss, hrx_bw;
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s\n",
++		 "BB Report Info");
++
++	/*@ [Mode] =====================================================*/
++
++	value32 = odm_get_bb_reg(dm, R_0x2c20, MASKDWORD);
++	rx_ht = (u8)((value32 & 0xC0000) >> 18);
++	if (rx_ht == AD_VHT_MODE)
++		tmp_string = "VHT";
++	else if (rx_ht == AD_HT_MODE)
++		tmp_string = "HT";
++	else
++		tmp_string = "Legacy";
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s %s", "mode", tmp_string);
++	/*@ [RX counter Info] ===============================================*/
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d", "CCK CCA cnt",
++		 odm_get_bb_reg(dm, R_0x2c08, 0xFFFF));
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d", "OFDM CCA cnt",
++		 odm_get_bb_reg(dm, R_0x2c08, 0xFFFF0000));
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d", "OFDM SBD Fail cnt",
++		 odm_get_bb_reg(dm, R_0x2d20, 0xFFFF0000));
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d",
++		 "LSIG (parity Fail/rate Illegal) cnt",
++		 odm_get_bb_reg(dm, R_0x2d04, 0xFFFF0000),
++		 odm_get_bb_reg(dm, R_0x2d08, 0xFFFF));
++
++	value32 = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT cnt",
++		 value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16));
++
++	value32 = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail cnt",
++		 value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16));
++	/*@ [L-SIG Content] =================================================*/
++	value32 = odm_get_bb_reg(dm, R_0x2c20, MASKDWORD);
++
++	parity = (u8)((value32 & 0x20000) >> 17);/*@[17]*/
++	length = (u16)((value32 & 0x1ffe0) >> 5);/*@[16:5]*/
++	rsv = (u8)((value32 & 0x10) >> 4);/*@[4]*/
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s",
++		 "L-SIG");
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %d M", "rate",
++		 phydm_get_l_sig_rate(dm, (u8)(value32 & 0x0f)));
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\r\n %-35s = %x / %d / %d", "Rsv/length/parity", rsv, length,
++		 parity);
++
++	if (rx_ht == AD_HT_MODE) {
++	/*@ [HT SIG 1] ======================================================*/
++		value32 = odm_get_bb_reg(dm, R_0x2c2c, MASKDWORD);
++
++		hmcss = (u8)(value32 & 0x7F);
++		hrx_bw = (u8)((value32 & 0x80) >> 7);
++		h_length = (u16)((value32 & 0x0fff00) >> 8);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s", "HT-SIG1");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = %d / %d / %d", "MCS/BW/length",
++			 hmcss, hrx_bw, h_length);
++	/*@ [HT SIG 2] ======================================================*/
++		value32 = odm_get_bb_reg(dm, R_0x2c30, MASKDWORD);
++		smooth = (u8)(value32 & 0x01);
++		htsound = (u8)((value32 & 0x02) >> 1);
++		rsv = (u8)((value32 & 0x04) >> 2);
++		agg = (u8)((value32 & 0x08) >> 3);
++		stbc = (u8)((value32 & 0x30) >> 4);
++		fec = (u8)((value32 & 0x40) >> 6);
++		sgi = (u8)((value32 & 0x80) >> 7);
++		htltf = (u8)((value32 & 0x300) >> 8);
++		htcrc8 = (u16)((value32 & 0x3fc00) >> 10);
++		tail = (u8)((value32 & 0xfc0000) >> 18);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s",
++			 "HT-SIG2");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = %x / %x / %x / %x / %x / %x",
++			 "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC",
++			 smooth, htsound, rsv, agg, stbc, fec);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = %x / %x / %x / %x",
++			 "SGI/E-HT-LTFs/CRC/tail",
++			 sgi, htltf, htcrc8, tail);
++	} else if (rx_ht == AD_VHT_MODE) {
++	/*@ [VHT SIG A1] ====================================================*/
++		value32 = odm_get_bb_reg(dm, R_0x2c2c, MASKDWORD);
++
++		v_rx_bw = (u8)(value32 & 0x03);
++		vrsv = (u8)((value32 & 0x04) >> 2);
++		vstbc = (u8)((value32 & 0x08) >> 3);
++		vgid = (u8)((value32 & 0x3f0) >> 4);
++		v_nsts = (u8)(((value32 & 0x1c00) >> 10) + 1);
++		vpaid = (u16)((value32 & 0x3fe000) >> 13);
++		vtxops = (u8)((value32 & 0x400000) >> 22);
++		vrsv2 = (u8)((value32 & 0x800000) >> 23);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s",
++			 "VHT-SIG-A1");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x",
++			 "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", v_rx_bw,
++			 vrsv, vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2);
++
++	/*@ [VHT SIG A2] ====================================================*/
++		value32 = odm_get_bb_reg(dm, R_0x2c30, MASKDWORD);
++
++		/* @sgi=(u8)(value32&0x01); */
++		sgiext = (u8)(value32 & 0x03);
++		/* @fec = (u8)(value32&0x04); */
++		fecext = (u8)((value32 & 0x0C) >> 2);
++
++		v_mcss = (u8)((value32 & 0xf0) >> 4);
++		bf = (u8)((value32 & 0x100) >> 8);
++		vrsv = (u8)((value32 & 0x200) >> 9);
++		vhtcrc8 = (u16)((value32 & 0x3fc00) >> 10);
++		v_tail = (u8)((value32 & 0xfc0000) >> 18);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s", "VHT-SIG-A2");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x",
++			 "SGI/FEC/MCS/BF/Rsv/CRC/tail",
++			 sgiext, fecext, v_mcss, bf, vrsv, vhtcrc8, v_tail);
++
++	/*@ [VHT SIG B] ====================================================*/
++		value32 = odm_get_bb_reg(dm, R_0x2c34, MASKDWORD);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s", "VHT-SIG-B");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = %x",
++			 "Codeword", value32);
++
++		if (v_rx_bw == 0) {
++			v_length = (u16)(value32 & 0x1ffff);
++			vbrsv = (u8)((value32 & 0xE0000) >> 17);
++			vb_tail = (u16)((value32 & 0x03F00000) >> 20);
++		} else if (v_rx_bw == 1) {
++			v_length = (u16)(value32 & 0x7FFFF);
++			vbrsv = (u8)((value32 & 0x180000) >> 19);
++			vb_tail = (u16)((value32 & 0x07E00000) >> 21);
++		} else if (v_rx_bw == 2) {
++			v_length = (u16)(value32 & 0x1fffff);
++			vbrsv = (u8)((value32 & 0x600000) >> 21);
++			vb_tail = (u16)((value32 & 0x1f800000) >> 23);
++		}
++		vbcrc = (u8)((value32 & 0x80000000) >> 31);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "\r\n %-35s = %x / %x / %x / %x",
++			 "length/Rsv/tail/CRC",
++			 v_length, vbrsv, vb_tail, vbcrc);
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++#endif
++
++u8 phydm_get_l_sig_rate(void *dm_void, u8 rate_idx_l_sig)
++{
++	u8 rate_idx = 0xff;
++
++	switch (rate_idx_l_sig) {
++	case 0x0b:
++		rate_idx = 6;
++		break;
++	case 0x0f:
++		rate_idx = 9;
++		break;
++	case 0x0a:
++		rate_idx = 12;
++		break;
++	case 0x0e:
++		rate_idx = 18;
++		break;
++	case 0x09:
++		rate_idx = 24;
++		break;
++	case 0x0d:
++		rate_idx = 36;
++		break;
++	case 0x08:
++		rate_idx = 48;
++		break;
++	case 0x0c:
++		rate_idx = 54;
++		break;
++	default:
++		rate_idx = 0xff;
++		break;
++	}
++
++	return rate_idx;
++}
++
++void phydm_bb_hw_dbg_info(void *dm_void, char input[][16], u32 *_used,
++			  char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	switch (dm->ic_ip_series) {
++	#if (ODM_IC_11N_SERIES_SUPPORT)
++	case PHYDM_IC_N:
++		phydm_bb_hw_dbg_info_n(dm, &used, output, &out_len);
++		break;
++	#endif
++
++	#if (ODM_IC_11AC_SERIES_SUPPORT)
++	case PHYDM_IC_AC:
++		phydm_bb_hw_dbg_info_ac(dm, &used, output, &out_len);
++		phydm_reset_bb_hw_cnt(dm);
++		#if (RTL8822B_SUPPORT)
++		phydm_bb_hw_dbg_info_8822b(dm, &used, output, &out_len);
++		#endif
++		break;
++	#endif
++
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	case PHYDM_IC_JGR3:
++		phydm_bb_hw_dbg_info_jgr3(dm, &used, output, &out_len);
++		phydm_reset_bb_hw_cnt(dm);
++		break;
++	#endif
++	default:
++		break;
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++
++void phydm_dm_summary_cli_win(void *dm_void, char *buf, u8 macid)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track;
++	struct cmn_sta_info *sta = NULL;
++	struct ra_sta_info *ra = NULL;
++	struct dtp_info *dtp = NULL;
++	u64 comp = dm->support_ability;
++	u64 pause_comp = dm->pause_ability;
++
++	if (!dm->is_linked) {
++		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "[%s]No Link !!!\n", __func__);
++		RT_PRINT(buf);
++		return;
++	}
++
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "00.(%s) %-12s: IGI=0x%x, Dyn_Rng=0x%x~0x%x, FA_th={%d,%d,%d}\n",
++		   ((comp & ODM_BB_DIG) ?
++		   ((pause_comp & ODM_BB_DIG) ? "P" : "V") : "."),
++		   "DIG",
++		   dig_t->cur_ig_value,
++		   dig_t->rx_gain_range_min, dig_t->rx_gain_range_max,
++		   dig_t->fa_th[0], dig_t->fa_th[1], dig_t->fa_th[2]);
++        RT_PRINT(buf);
++
++	sta = dm->phydm_sta_info[macid];
++	if (is_sta_active(sta)) {
++		ra = &sta->ra_info;
++		dtp = &sta->dtp_stat;
++
++		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "01.(%s) %-12s: rssi_lv=%d, mask=0x%llx\n",
++			   ((comp & ODM_BB_RA_MASK) ?
++			   ((pause_comp & ODM_BB_RA_MASK) ? "P" : "V") : "."),
++			   "RaMask",
++			   ra->rssi_level, ra->ramask);
++		RT_PRINT(buf);
++
++		#ifdef CONFIG_DYNAMIC_TX_TWR
++		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "02.(%s) %-12s: pwr_lv=%d\n",
++			   ((comp & ODM_BB_DYNAMIC_TXPWR) ?
++			   ((pause_comp & ODM_BB_DYNAMIC_TXPWR) ? "P" : "V") : "."),
++			   "DynTxPwr",
++			   dtp->sta_tx_high_power_lvl);
++		RT_PRINT(buf);
++		#endif
++	}
++
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "05.(%s) %-12s: cck_pd_lv=%d\n",
++		   ((comp & ODM_BB_CCK_PD) ?
++		   ((pause_comp & ODM_BB_CCK_PD) ? "P" : "V") : "."),
++		   "CCK_PD", dm->dm_cckpd_table.cck_pd_lv);
++	RT_PRINT(buf);
++
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "06.(%s) %-12s: div_type=%d, curr_ant=%s\n",
++		   ((comp & ODM_BB_ANT_DIV) ?
++		   ((pause_comp & ODM_BB_ANT_DIV) ? "P" : "V") : "."),
++		   "ANT_DIV",
++		   dm->ant_div_type,
++		   (dm->dm_fat_table.rx_idle_ant == MAIN_ANT) ? "MAIN" : "AUX");
++	RT_PRINT(buf);
++#endif
++
++#ifdef PHYDM_POWER_TRAINING_SUPPORT
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "08.(%s) %-12s: PT_score=%d, disable_PT=%d\n",
++		   ((comp & ODM_BB_PWR_TRAIN) ?
++		   ((pause_comp & ODM_BB_PWR_TRAIN) ? "P" : "V") : "."),
++		   "PwrTrain",
++		   dm->pow_train_table.pow_train_score,
++		   dm->is_disable_power_training);
++	RT_PRINT(buf);
++#endif
++
++#ifdef CONFIG_PHYDM_DFS_MASTER
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "11.(%s) %-12s: dbg_mode=%d, region_domain=%d\n",
++		   ((comp & ODM_BB_DFS) ?
++		   ((pause_comp & ODM_BB_DFS) ? "P" : "V") : "."),
++		   "DFS",
++		   dm->dfs.dbg_mode, dm->dfs_region_domain);
++	RT_PRINT(buf);
++#endif
++#ifdef PHYDM_SUPPORT_ADAPTIVITY
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "13.(%s) %-12s: th{l2h, h2l}={%d, %d}, edcca_flag=%d\n",
++		   ((comp & ODM_BB_ADAPTIVITY) ?
++		   ((pause_comp & ODM_BB_ADAPTIVITY) ? "P" : "V") : "."),
++		   "Adaptivity",
++		   dm->adaptivity.th_l2h, dm->adaptivity.th_h2l,
++		   dm->false_alm_cnt.edcca_flag);
++	RT_PRINT(buf);
++#endif
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "14.(%s) %-12s: CFO_avg=%d kHz, CFO_traking=%s%d\n",
++		   ((comp & ODM_BB_CFO_TRACKING) ?
++		   ((pause_comp & ODM_BB_CFO_TRACKING) ? "P" : "V") : "."),
++		   "CfoTrack",
++		   cfo_t->CFO_ave_pre,
++		   ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"),
++		   DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap));
++	RT_PRINT(buf);
++
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++		   "15.(%s) %-12s: ratio{nhm, clm}={%d, %d}, level{valid, RSSI}={%d, %d}\n",
++		   ((comp & ODM_BB_ENV_MONITOR) ?
++		   ((pause_comp & ODM_BB_ENV_MONITOR) ? "P" : "V") : "."),
++		   "EnvMntr",
++		   dm->dm_ccx_info.nhm_ratio, dm->dm_ccx_info.clm_ratio,
++		   dm->dm_ccx_info.nhm_level_valid, dm->dm_ccx_info.nhm_level);
++	RT_PRINT(buf);
++#ifdef PHYDM_PRIMARY_CCA
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "16.(%s) %-12s: CCA @ (%s SB)\n",
++		   ((comp & ODM_BB_PRIMARY_CCA) ?
++		   ((pause_comp & ODM_BB_PRIMARY_CCA) ? "P" : "V") : "."),
++		   "PriCCA",
++		   ((dm->dm_pri_cca.mf_state == MF_USC_LSC) ? "D" :
++		   ((dm->dm_pri_cca.mf_state == MF_LSC) ? "L" : "U")));
++	RT_PRINT(buf);
++#endif
++#ifdef CONFIG_ADAPTIVE_SOML
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "17.(%s) %-12s: soml_en = %s\n",
++		   ((comp & ODM_BB_ADAPTIVE_SOML) ?
++		   ((pause_comp & ODM_BB_ADAPTIVE_SOML) ? "P" : "V") : "."),
++		   "A-SOML",
++		   (dm->dm_soml_table.soml_last_state == SOML_ON) ?
++		   "ON" : "OFF");
++	RT_PRINT(buf);
++#endif
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "18.(%s) %-12s:\n",
++		   ((comp & ODM_BB_LNA_SAT_CHK) ?
++		   ((pause_comp & ODM_BB_LNA_SAT_CHK) ? "P" : "V") : "."),
++		   "LNA_SAT_CHK");
++	RT_PRINT(buf);
++#endif
++}
++
++void phydm_basic_dbg_msg_cli_win(void *dm_void, char *buf)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
++	struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track;
++	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info_win_bkp;
++	struct phydm_phystatus_statistic *dbg_s = &dbg->physts_statistic_info;
++	struct phydm_phystatus_avg *dbg_avg = &dbg->phystatus_statistic_avg;
++
++	char *rate_type = NULL;
++	u8 tmp_rssi_avg[4];
++	u8 tmp_snr_avg[4];
++	u8 tmp_evm_avg[4];
++	u32 tmp_cnt = 0;
++	u8 macid, target_macid = 0;
++	u8 i = 0;
++	u8 rate_num = dm->num_rf_path;
++	u8 ss_ofst = 0;
++	struct cmn_sta_info *entry = NULL;
++	char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
++
++
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n PHYDM Common Dbg Msg --------->");
++	RT_PRINT(buf);
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n System up time=%d", dm->phydm_sys_up_time);
++	RT_PRINT(buf);
++
++	if (dm->is_linked) {
++		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n ID=((%d)), BW=((%d)), fc=((CH-%d))",
++			   dm->curr_station_id, 20 << *dm->band_width, *dm->channel);
++		RT_PRINT(buf);
++
++		if (((*dm->channel <= 14) && (*dm->band_width == CHANNEL_WIDTH_40)) &&
++		    (dm->support_ic_type & ODM_IC_11N_SERIES)) {
++			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Primary CCA at ((%s SB))",
++				   (*dm->sec_ch_offset == SECOND_CH_AT_LSB) ? "U" : "L");
++			RT_PRINT(buf);
++		}
++
++		if (dm->cck_new_agc || dm->rx_rate > ODM_RATE11M) {
++			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [AGC Idx] {0x%x, 0x%x, 0x%x, 0x%x}",
++				   dm->ofdm_agc_idx[0], dm->ofdm_agc_idx[1],
++				   dm->ofdm_agc_idx[2], dm->ofdm_agc_idx[3]);
++			RT_PRINT(buf);
++		} else {
++			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [CCK AGC Idx] {LNA,VGA}={0x%x, 0x%x}",
++				   dm->cck_lna_idx, dm->cck_vga_idx);
++			RT_PRINT(buf);
++		}
++
++		phydm_print_rate_2_buff(dm, dm->rx_rate, dbg_buf, PHYDM_SNPRINT_SIZE);
++		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n RSSI:{%d, %d, %d, %d}, RxRate:%s (0x%x)",
++			   (dm->rssi_a == 0xff) ? 0 : dm->rssi_a,
++			   (dm->rssi_b == 0xff) ? 0 : dm->rssi_b,
++			   (dm->rssi_c == 0xff) ? 0 : dm->rssi_c,
++			   (dm->rssi_d == 0xff) ? 0 : dm->rssi_d,
++			  dbg_buf, dm->rx_rate);
++		RT_PRINT(buf);
++
++		phydm_print_rate_2_buff(dm, dm->phy_dbg_info.beacon_phy_rate, dbg_buf, PHYDM_SNPRINT_SIZE);
++		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Beacon_cnt=%d, rate_idx:%s (0x%x)",
++			   dm->phy_dbg_info.beacon_cnt_in_period,
++			   dbg_buf,
++			   dm->phy_dbg_info.beacon_phy_rate);
++		RT_PRINT(buf);
++
++		/*Show phydm_rx_rate_distribution;*/
++		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [RxRate Cnt] =============>");
++		RT_PRINT(buf);
++
++		/*@======CCK=================================================*/
++		if (*dm->channel <= 14) {
++			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * CCK = {%d, %d, %d, %d}",
++				   dbg->num_qry_legacy_pkt[0], dbg->num_qry_legacy_pkt[1],
++				   dbg->num_qry_legacy_pkt[2], dbg->num_qry_legacy_pkt[3]);
++			RT_PRINT(buf);
++		}
++		/*@======OFDM================================================*/
++		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * OFDM = {%d, %d, %d, %d, %d, %d, %d, %d}",
++			   dbg->num_qry_legacy_pkt[4], dbg->num_qry_legacy_pkt[5],
++			   dbg->num_qry_legacy_pkt[6], dbg->num_qry_legacy_pkt[7],
++			   dbg->num_qry_legacy_pkt[8], dbg->num_qry_legacy_pkt[9],
++			   dbg->num_qry_legacy_pkt[10], dbg->num_qry_legacy_pkt[11]);
++		RT_PRINT(buf);
++
++		/*@======HT==================================================*/
++		if (dbg->ht_pkt_not_zero) {
++			for (i = 0; i < rate_num; i++) {
++				ss_ofst = (i << 3);
++
++				RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}",
++					   (ss_ofst), (ss_ofst + 7),
++					   dbg->num_qry_ht_pkt[ss_ofst + 0], dbg->num_qry_ht_pkt[ss_ofst + 1],
++					   dbg->num_qry_ht_pkt[ss_ofst + 2], dbg->num_qry_ht_pkt[ss_ofst + 3],
++					   dbg->num_qry_ht_pkt[ss_ofst + 4], dbg->num_qry_ht_pkt[ss_ofst + 5],
++					   dbg->num_qry_ht_pkt[ss_ofst + 6], dbg->num_qry_ht_pkt[ss_ofst + 7]);
++				RT_PRINT(buf);
++			}
++
++			if (dbg->low_bw_20_occur) {
++				for (i = 0; i < rate_num; i++) {
++					ss_ofst = (i << 3);
++
++					RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * [Low BW 20M] HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}",
++						   (ss_ofst), (ss_ofst + 7),
++						   dbg->num_qry_pkt_sc_20m[ss_ofst + 0], dbg->num_qry_pkt_sc_20m[ss_ofst + 1],
++						   dbg->num_qry_pkt_sc_20m[ss_ofst + 2], dbg->num_qry_pkt_sc_20m[ss_ofst + 3],
++						   dbg->num_qry_pkt_sc_20m[ss_ofst + 4], dbg->num_qry_pkt_sc_20m[ss_ofst + 5],
++						   dbg->num_qry_pkt_sc_20m[ss_ofst + 6], dbg->num_qry_pkt_sc_20m[ss_ofst + 7]);
++					RT_PRINT(buf);
++				}
++			}
++		}
++
++#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
++		/*@======VHT=================================================*/
++		if (dbg->vht_pkt_not_zero) {
++			for (i = 0; i < rate_num; i++) {
++				ss_ofst = 10 * i;
++
++				RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}",
++					   (i + 1),
++					   dbg->num_qry_vht_pkt[ss_ofst + 0], dbg->num_qry_vht_pkt[ss_ofst + 1],
++					   dbg->num_qry_vht_pkt[ss_ofst + 2], dbg->num_qry_vht_pkt[ss_ofst + 3],
++					   dbg->num_qry_vht_pkt[ss_ofst + 4], dbg->num_qry_vht_pkt[ss_ofst + 5],
++					   dbg->num_qry_vht_pkt[ss_ofst + 6], dbg->num_qry_vht_pkt[ss_ofst + 7],
++					   dbg->num_qry_vht_pkt[ss_ofst + 8], dbg->num_qry_vht_pkt[ss_ofst + 9]);
++				RT_PRINT(buf);
++			}
++
++			if (dbg->low_bw_20_occur) {
++				for (i = 0; i < rate_num; i++) {
++					ss_ofst = 10 * i;
++
++					RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n *[Low BW 20M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}",
++						   (i + 1),
++						   dbg->num_qry_pkt_sc_20m[ss_ofst + 0], dbg->num_qry_pkt_sc_20m[ss_ofst + 1],
++						   dbg->num_qry_pkt_sc_20m[ss_ofst + 2], dbg->num_qry_pkt_sc_20m[ss_ofst + 3],
++						   dbg->num_qry_pkt_sc_20m[ss_ofst + 4], dbg->num_qry_pkt_sc_20m[ss_ofst + 5],
++						   dbg->num_qry_pkt_sc_20m[ss_ofst + 6], dbg->num_qry_pkt_sc_20m[ss_ofst + 7],
++						   dbg->num_qry_pkt_sc_20m[ss_ofst + 8], dbg->num_qry_pkt_sc_20m[ss_ofst + 9]);
++					RT_PRINT(buf);
++				}
++			}
++
++			if (dbg->low_bw_40_occur) {
++				for (i = 0; i < rate_num; i++) {
++					ss_ofst = 10 * i;
++
++					RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n *[Low BW 40M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}",
++						   (i + 1),
++						   dbg->num_qry_pkt_sc_40m[ss_ofst + 0], dbg->num_qry_pkt_sc_40m[ss_ofst + 1],
++						   dbg->num_qry_pkt_sc_40m[ss_ofst + 2], dbg->num_qry_pkt_sc_40m[ss_ofst + 3],
++						   dbg->num_qry_pkt_sc_40m[ss_ofst + 4], dbg->num_qry_pkt_sc_40m[ss_ofst + 5],
++						   dbg->num_qry_pkt_sc_40m[ss_ofst + 6], dbg->num_qry_pkt_sc_40m[ss_ofst + 7],
++						   dbg->num_qry_pkt_sc_40m[ss_ofst + 8], dbg->num_qry_pkt_sc_40m[ss_ofst + 9]);
++					RT_PRINT(buf);
++				}
++			}
++		}
++#endif
++
++		//1 Show phydm_avg_phystatus_val
++		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++			   "\r\n [Avg PHY Statistic] ==============>\n");
++		RT_PRINT(buf);
++
++		/*===[Beacon]===*/
++		switch (dm->num_rf_path) {
++#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++		case 4:
++			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n",
++				   "[Beacon]", dbg_s->rssi_beacon_cnt,
++				   dbg_avg->rssi_beacon_avg[0],
++				   dbg_avg->rssi_beacon_avg[1],
++				   dbg_avg->rssi_beacon_avg[2],
++				   dbg_avg->rssi_beacon_avg[3]);
++			break;
++#endif
++#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++		case 3:
++			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n",
++				   "[Beacon]", dbg_s->rssi_beacon_cnt,
++				   dbg_avg->rssi_beacon_avg[0],
++				   dbg_avg->rssi_beacon_avg[1],
++				   dbg_avg->rssi_beacon_avg[2]);
++			break;
++#endif
++#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++		case 2:
++			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n",
++				   "[Beacon]", dbg_s->rssi_beacon_cnt,
++				   dbg_avg->rssi_beacon_avg[0],
++				   dbg_avg->rssi_beacon_avg[1]);
++			break;
++#endif
++		default:
++			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n",
++				   "[Beacon]", dbg_s->rssi_beacon_cnt,
++				   dbg_avg->rssi_beacon_avg[0]);
++			break;
++		}
++		RT_PRINT(buf);
++
++		/*===[CCK]===*/
++		switch (dm->num_rf_path) {
++#ifdef PHYSTS_3RD_TYPE_SUPPORT
++	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++		case 4:
++			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n",
++				   "[CCK]", dbg_s->rssi_cck_cnt,
++				   dbg_avg->rssi_cck_avg,
++				   dbg_avg->rssi_cck_avg_abv_2ss[0],
++				   dbg_avg->rssi_cck_avg_abv_2ss[1],
++				   dbg_avg->rssi_cck_avg_abv_2ss[2]);
++			break;
++	#endif
++	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++		case 3:
++			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n",
++				   "[CCK]", dbg_s->rssi_cck_cnt,
++				   dbg_avg->rssi_cck_avg,
++				   dbg_avg->rssi_cck_avg_abv_2ss[0],
++				   dbg_avg->rssi_cck_avg_abv_2ss[1]);
++			break;
++	#endif
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++		case 2:
++			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n",
++				   "[CCK]", dbg_s->rssi_cck_cnt,
++				   dbg_avg->rssi_cck_avg,
++				   dbg_avg->rssi_cck_avg_abv_2ss[0]);
++			break;
++	#endif
++#endif
++		default:
++			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n",
++				   "[CCK]", dbg_s->rssi_cck_cnt,
++				   dbg_avg->rssi_cck_avg);
++			break;
++		}
++		RT_PRINT(buf);
++
++		for (i = 0; i <= 4; i++) {
++			if (i > dm->num_rf_path)
++				break;
++
++			odm_memory_set(dm, tmp_rssi_avg, 0, 4);
++			odm_memory_set(dm, tmp_snr_avg, 0, 4);
++			odm_memory_set(dm, tmp_evm_avg, 0, 4);
++
++			#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++			if (i == 4) {
++				rate_type = "[4-SS]";
++				tmp_cnt = dbg_s->rssi_4ss_cnt;
++				odm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_4ss_avg, dm->num_rf_path);
++				odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_4ss_avg, dm->num_rf_path);
++				odm_move_memory(dm, tmp_evm_avg, dbg_avg->evm_4ss_avg, 4);
++			} else
++			#endif
++			#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++			if (i == 3) {
++				rate_type = "[3-SS]";
++				tmp_cnt = dbg_s->rssi_3ss_cnt;
++				odm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_3ss_avg, dm->num_rf_path);
++				odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_3ss_avg, dm->num_rf_path);
++				odm_move_memory(dm, tmp_evm_avg, dbg_avg->evm_3ss_avg, 3);
++			} else
++			#endif
++			#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++			if (i == 2) {
++				rate_type = "[2-SS]";
++				tmp_cnt = dbg_s->rssi_2ss_cnt;
++				odm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_2ss_avg, dm->num_rf_path);
++				odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_2ss_avg, dm->num_rf_path);
++				odm_move_memory(dm, tmp_evm_avg, dbg_avg->evm_2ss_avg, 2);
++			} else
++			#endif
++			if (i == 1) {
++				rate_type = "[1-SS]";
++				tmp_cnt = dbg_s->rssi_1ss_cnt;
++				odm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_1ss_avg, dm->num_rf_path);
++				odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_1ss_avg, dm->num_rf_path);
++				odm_move_memory(dm, tmp_evm_avg, &dbg_avg->evm_1ss_avg, 1);
++			} else {
++				rate_type = "[L-OFDM]";
++				tmp_cnt = dbg_s->rssi_ofdm_cnt;
++				odm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_ofdm_avg, dm->num_rf_path);
++				odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_ofdm_avg, dm->num_rf_path);
++				odm_move_memory(dm, tmp_evm_avg, &dbg_avg->evm_ofdm_avg, 1);
++			}
++
++			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d} SNR:{%.2d, %.2d, %.2d, %.2d} EVM:{-%.2d, -%.2d, -%.2d, -%.2d}\n",
++				    rate_type, tmp_cnt,
++				    tmp_rssi_avg[0], tmp_rssi_avg[1], tmp_rssi_avg[2], tmp_rssi_avg[3],
++				    tmp_snr_avg[0], tmp_snr_avg[1], tmp_snr_avg[2], tmp_snr_avg[3],
++				    tmp_evm_avg[0], tmp_evm_avg[1], tmp_evm_avg[2], tmp_evm_avg[3]);
++			RT_PRINT(buf);
++		}
++		/*@----------------------------------------------------------*/
++
++		/*Print TX rate*/
++		for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
++			entry = dm->phydm_sta_info[macid];
++
++			if (is_sta_active(entry)) {
++				phydm_print_rate_2_buff(dm, entry->ra_info.curr_tx_rate, dbg_buf, PHYDM_SNPRINT_SIZE);
++				RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n TxRate[%d]=%s (0x%x)", macid, dbg_buf, entry->ra_info.curr_tx_rate);
++				RT_PRINT(buf);
++				target_macid = macid;
++				break;
++			}
++		}
++
++		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++			   "\r\n TP {Tx, Rx, Total} = {%d, %d, %d}Mbps, Traffic_Load=(%d))",
++			   dm->tx_tp, dm->rx_tp, dm->total_tp, dm->traffic_load);
++		RT_PRINT(buf);
++
++		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n CFO_avg=((%d kHz)), CFO_traking = ((%s%d))",
++			   cfo_t->CFO_ave_pre,
++			   ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"),
++			   DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap));
++		RT_PRINT(buf);
++
++		/* @Condition number */
++		#if (RTL8822B_SUPPORT)
++		if (dm->support_ic_type == ODM_RTL8822B) {
++			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Condi_Num=((%d.%.4d))",
++				   dm->phy_dbg_info.condi_num >> 4,
++				   phydm_show_fraction_num(dm->phy_dbg_info.condi_num & 0xf, 4));
++			RT_PRINT(buf);
++		}
++		#endif
++
++#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT))
++		/*STBC or LDPC pkt*/
++		if (dm->support_ic_type & (PHYSTS_2ND_TYPE_IC |
++					   PHYSTS_3RD_TYPE_IC))
++			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Coding: LDPC=((%s)), STBC=((%s))",
++				   (dm->phy_dbg_info.is_ldpc_pkt) ? "Y" : "N",
++				   (dm->phy_dbg_info.is_stbc_pkt) ? "Y" : "N");
++			RT_PRINT(buf);
++#endif
++
++	} else {
++		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n No Link !!!");
++		RT_PRINT(buf);
++	}
++
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}",
++		   fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);
++	RT_PRINT(buf);
++
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}",
++		   fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all);
++	RT_PRINT(buf);
++
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++		   "\r\n [OFDM FA] Parity=%d, Rate=%d, Fast_Fsync=%d, SBD=%d",
++		   fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
++		   fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail);
++	RT_PRINT(buf);
++
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [HT FA] CRC8=%d, MCS=%d",
++		   fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail);
++	RT_PRINT(buf);
++
++#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
++	if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
++		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++			   "\r\n [VHT FA] SIGA_CRC8=%d, SIGB_CRC8=%d, MCS=%d",
++			   fa_t->cnt_crc8_fail_vhta, fa_t->cnt_crc8_fail_vhtb,
++			   fa_t->cnt_mcs_fail_vht);
++		RT_PRINT(buf);
++	}
++#endif
++
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++		   "\r\n [CRC32 OK Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}",
++		   fa_t->cnt_cck_crc32_ok, fa_t->cnt_ofdm_crc32_ok,
++		   fa_t->cnt_ht_crc32_ok, fa_t->cnt_vht_crc32_ok,
++		   fa_t->cnt_crc32_ok_all);
++	RT_PRINT(buf);
++
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++		   "\r\n [CRC32 Err Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}",
++		   fa_t->cnt_cck_crc32_error, fa_t->cnt_ofdm_crc32_error,
++		   fa_t->cnt_ht_crc32_error, fa_t->cnt_vht_crc32_error,
++		   fa_t->cnt_crc32_error_all);
++	RT_PRINT(buf);
++
++	if (fa_t->ofdm2_rate_idx) {
++		phydm_print_rate_2_buff(dm, fa_t->ofdm2_rate_idx,
++					dbg_buf, PHYDM_SNPRINT_SIZE);
++		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++			   "\r\n [OFDM:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)",
++			   dbg_buf, fa_t->cnt_ofdm2_crc32_error,
++			   fa_t->cnt_ofdm2_crc32_ok, fa_t->ofdm2_pcr);
++		RT_PRINT(buf);
++	}
++
++	if (fa_t->ht2_rate_idx) {
++		phydm_print_rate_2_buff(dm, fa_t->ht2_rate_idx, dbg_buf,
++					PHYDM_SNPRINT_SIZE);
++		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++			   "\r\n [HT  :%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)",
++			   dbg_buf, fa_t->cnt_ht2_crc32_error,
++			   fa_t->cnt_ht2_crc32_ok, fa_t->ht2_pcr);
++		RT_PRINT(buf);
++	}
++
++#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
++	if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
++		if (fa_t->vht2_rate_idx) {
++			phydm_print_rate_2_buff(dm, fa_t->vht2_rate_idx,
++						dbg_buf, PHYDM_SNPRINT_SIZE);
++			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++				   "\r\n [VHT :%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)",
++				   dbg_buf, fa_t->cnt_vht2_crc32_error,
++				   fa_t->cnt_vht2_crc32_ok, fa_t->vht2_pcr);
++			RT_PRINT(buf);
++		}
++	}
++#endif
++	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
++		   "\r\n is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x, bNoisy=%d\n",
++		   dm->is_linked, dm->number_linked_client, dm->rssi_min,
++		   dm->dm_dig_table.cur_ig_value, dm->noisy_decision);
++	RT_PRINT(buf);
++
++	phydm_dm_summary_cli_win(dm, buf, target_macid);
++}
++
++#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
++void phydm_sbd_check(
++	struct dm_struct *dm)
++{
++	static u32 pkt_cnt;
++	static boolean sbd_state;
++	u32 sym_count, count, value32;
++
++	if (sbd_state == 0) {
++		pkt_cnt++;
++		/*read SBD conter once every 5 packets*/
++		if (pkt_cnt % 5 == 0) {
++			odm_set_timer(dm, &dm->sbdcnt_timer, 0); /*@ms*/
++			sbd_state = 1;
++		}
++	} else { /*read counter*/
++		value32 = odm_get_bb_reg(dm, R_0xf98, MASKDWORD);
++		sym_count = (value32 & 0x7C000000) >> 26;
++		count = (value32 & 0x3F00000) >> 20;
++		pr_debug("#SBD# sym_count %d count %d\n", sym_count, count);
++		sbd_state = 0;
++	}
++}
++#endif
++
++void phydm_sbd_callback(
++	struct phydm_timer_list *timer)
++{
++#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
++	void *adapter = timer->Adapter;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++
++#if USE_WORKITEM
++	odm_schedule_work_item(&dm->sbdcnt_workitem);
++#else
++	phydm_sbd_check(dm);
++#endif
++#endif
++}
++
++void phydm_sbd_workitem_callback(
++	void *context)
++{
++#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
++	void *adapter = (void *)context;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++
++	phydm_sbd_check(dm);
++#endif
++}
++#endif
++
++void phydm_reset_rx_rate_distribution(struct dm_struct *dm)
++{
++	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
++
++	odm_memory_set(dm, &dbg->num_qry_legacy_pkt[0], 0,
++		       (LEGACY_RATE_NUM * 2));
++	odm_memory_set(dm, &dbg->num_qry_ht_pkt[0], 0,
++		       (HT_RATE_NUM * 2));
++	odm_memory_set(dm, &dbg->num_qry_pkt_sc_20m[0], 0,
++		       (LOW_BW_RATE_NUM * 2));
++
++	dbg->ht_pkt_not_zero = false;
++	dbg->low_bw_20_occur = false;
++
++#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
++	odm_memory_set(dm, &dbg->num_qry_vht_pkt[0], 0, VHT_RATE_NUM * 2);
++	odm_memory_set(dm, &dbg->num_qry_pkt_sc_40m[0], 0, LOW_BW_RATE_NUM * 2);
++	#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) || (defined(PHYSTS_3RD_TYPE_SUPPORT))
++	odm_memory_set(dm, &dbg->num_mu_vht_pkt[0], 0, VHT_RATE_NUM * 2);
++	#endif
++	dbg->vht_pkt_not_zero = false;
++	dbg->low_bw_40_occur = false;
++#endif
++}
++
++void phydm_rx_rate_distribution(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
++	u8 i = 0;
++	u8 rate_num = dm->num_rf_path, ss_ofst = 0;
++
++	PHYDM_DBG(dm, DBG_CMN, "[RxRate Cnt] =============>\n");
++
++	/*@======CCK=========================================================*/
++	if (*dm->channel <= 14) {
++		PHYDM_DBG(dm, DBG_CMN, "* CCK = {%d, %d, %d, %d}\n",
++			  dbg->num_qry_legacy_pkt[0],
++			  dbg->num_qry_legacy_pkt[1],
++			  dbg->num_qry_legacy_pkt[2],
++			  dbg->num_qry_legacy_pkt[3]);
++	}
++	/*@======OFDM========================================================*/
++	PHYDM_DBG(dm, DBG_CMN, "* OFDM = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
++		  dbg->num_qry_legacy_pkt[4], dbg->num_qry_legacy_pkt[5],
++		  dbg->num_qry_legacy_pkt[6], dbg->num_qry_legacy_pkt[7],
++		  dbg->num_qry_legacy_pkt[8], dbg->num_qry_legacy_pkt[9],
++		  dbg->num_qry_legacy_pkt[10], dbg->num_qry_legacy_pkt[11]);
++
++	/*@======HT==========================================================*/
++	if (dbg->ht_pkt_not_zero) {
++		for (i = 0; i < rate_num; i++) {
++			ss_ofst = (i << 3);
++
++			PHYDM_DBG(dm, DBG_CMN,
++				  "* HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
++				  (ss_ofst), (ss_ofst + 7),
++				  dbg->num_qry_ht_pkt[ss_ofst + 0],
++				  dbg->num_qry_ht_pkt[ss_ofst + 1],
++				  dbg->num_qry_ht_pkt[ss_ofst + 2],
++				  dbg->num_qry_ht_pkt[ss_ofst + 3],
++				  dbg->num_qry_ht_pkt[ss_ofst + 4],
++				  dbg->num_qry_ht_pkt[ss_ofst + 5],
++				  dbg->num_qry_ht_pkt[ss_ofst + 6],
++				  dbg->num_qry_ht_pkt[ss_ofst + 7]);
++		}
++
++		if (dbg->low_bw_20_occur) {
++			for (i = 0; i < rate_num; i++) {
++				ss_ofst = (i << 3);
++
++				PHYDM_DBG(dm, DBG_CMN,
++					  "* [Low BW 20M] HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
++					  (ss_ofst), (ss_ofst + 7),
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 0],
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 1],
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 2],
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 3],
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 4],
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 5],
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 6],
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 7]);
++			}
++		}
++	}
++
++#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
++	/*@======VHT==========================================================*/
++	if (dbg->vht_pkt_not_zero) {
++		for (i = 0; i < rate_num; i++) {
++			ss_ofst = 10 * i;
++
++			PHYDM_DBG(dm, DBG_CMN,
++				  "* VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
++				  (i + 1),
++				  dbg->num_qry_vht_pkt[ss_ofst + 0],
++				  dbg->num_qry_vht_pkt[ss_ofst + 1],
++				  dbg->num_qry_vht_pkt[ss_ofst + 2],
++				  dbg->num_qry_vht_pkt[ss_ofst + 3],
++				  dbg->num_qry_vht_pkt[ss_ofst + 4],
++				  dbg->num_qry_vht_pkt[ss_ofst + 5],
++				  dbg->num_qry_vht_pkt[ss_ofst + 6],
++				  dbg->num_qry_vht_pkt[ss_ofst + 7],
++				  dbg->num_qry_vht_pkt[ss_ofst + 8],
++				  dbg->num_qry_vht_pkt[ss_ofst + 9]);
++		}
++
++		if (dbg->low_bw_20_occur) {
++			for (i = 0; i < rate_num; i++) {
++				ss_ofst = 10 * i;
++
++				PHYDM_DBG(dm, DBG_CMN,
++					  "*[Low BW 20M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
++					  (i + 1),
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 0],
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 1],
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 2],
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 3],
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 4],
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 5],
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 6],
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 7],
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 8],
++					  dbg->num_qry_pkt_sc_20m[ss_ofst + 9]);
++			}
++		}
++
++		if (dbg->low_bw_40_occur) {
++			for (i = 0; i < rate_num; i++) {
++				ss_ofst = 10 * i;
++
++				PHYDM_DBG(dm, DBG_CMN,
++					  "*[Low BW 40M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
++					  (i + 1),
++					  dbg->num_qry_pkt_sc_40m[ss_ofst + 0],
++					  dbg->num_qry_pkt_sc_40m[ss_ofst + 1],
++					  dbg->num_qry_pkt_sc_40m[ss_ofst + 2],
++					  dbg->num_qry_pkt_sc_40m[ss_ofst + 3],
++					  dbg->num_qry_pkt_sc_40m[ss_ofst + 4],
++					  dbg->num_qry_pkt_sc_40m[ss_ofst + 5],
++					  dbg->num_qry_pkt_sc_40m[ss_ofst + 6],
++					  dbg->num_qry_pkt_sc_40m[ss_ofst + 7],
++					  dbg->num_qry_pkt_sc_40m[ss_ofst + 8],
++					  dbg->num_qry_pkt_sc_40m[ss_ofst + 9]);
++			}
++		}
++	}
++#endif
++}
++
++u16 phydm_rx_utility(void *dm_void, u16 avg_phy_rate, u8 rx_max_ss,
++		     enum channel_width bw)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
++	u16 utility_primitive = 0, utility = 0;
++
++	if (dbg->ht_pkt_not_zero) {
++	/*@ MCS7 20M: tp = 65, 1000/65 = 15.38, 65*15.5 = 1007*/
++		utility_primitive = avg_phy_rate * 15 + (avg_phy_rate >> 1);
++	}
++#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
++	else if (dbg->vht_pkt_not_zero) {
++	/*@ VHT 1SS MCS9(fake) 20M: tp = 90, 1000/90 = 11.11, 65*11.125 = 1001*/
++		utility_primitive = avg_phy_rate * 11 + (avg_phy_rate >> 3);
++	}
++#endif
++	else {
++	/*@ 54M, 1000/54 = 18.5, 54*18.5 = 999*/
++		utility_primitive = avg_phy_rate * 18 + (avg_phy_rate >> 1);
++	}
++
++	utility = (utility_primitive / rx_max_ss) >> bw;
++
++	if (utility > 1000)
++		utility = 1000;
++
++	return utility;
++}
++
++u16 phydm_rx_avg_phy_rate(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
++	u8 i = 0, rate_num = 0, rate_base = 0;
++	u16 rate = 0, avg_phy_rate = 0;
++	u32 pkt_cnt = 0, phy_rate_sum = 0;
++
++	if (dbg->ht_pkt_not_zero) {
++		rate_num = HT_RATE_NUM;
++		rate_base = ODM_RATEMCS0;
++		for (i = 0; i < rate_num; i++) {
++			rate = phy_rate_table[i + rate_base] << *dm->band_width;
++			phy_rate_sum += dbg->num_qry_ht_pkt[i] * rate;
++			pkt_cnt += dbg->num_qry_ht_pkt[i];
++		}
++	}
++#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
++	else if (dbg->vht_pkt_not_zero) {
++		rate_num = VHT_RATE_NUM;
++		rate_base = ODM_RATEVHTSS1MCS0;
++		for (i = 0; i < rate_num; i++) {
++			rate = phy_rate_table[i + rate_base] << *dm->band_width;
++			phy_rate_sum += dbg->num_qry_vht_pkt[i] * rate;
++			pkt_cnt += dbg->num_qry_vht_pkt[i];
++		}
++	}
++#endif
++	else {
++		for (i = ODM_RATE1M; i <= ODM_RATE54M; i++) {
++			/*SKIP 1M & 6M for beacon case*/
++			if (*dm->channel < 36 && i == ODM_RATE1M)
++				continue;
++
++			if (*dm->channel >= 36 && i == ODM_RATE6M)
++				continue;
++
++			rate = phy_rate_table[i];
++			phy_rate_sum += dbg->num_qry_legacy_pkt[i] * rate;
++			pkt_cnt += dbg->num_qry_legacy_pkt[i];
++		}
++	}
++
++#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
++	if (dbg->low_bw_40_occur) {
++		for (i = 0; i < LOW_BW_RATE_NUM; i++) {
++			rate = phy_rate_table[i + rate_base]
++			       << CHANNEL_WIDTH_40;
++			phy_rate_sum += dbg->num_qry_pkt_sc_40m[i] * rate;
++			pkt_cnt += dbg->num_qry_pkt_sc_40m[i];
++		}
++	}
++#endif
++
++	if (dbg->low_bw_20_occur) {
++		for (i = 0; i < LOW_BW_RATE_NUM; i++) {
++			rate = phy_rate_table[i + rate_base];
++			phy_rate_sum += dbg->num_qry_pkt_sc_20m[i] * rate;
++			pkt_cnt += dbg->num_qry_pkt_sc_20m[i];
++		}
++	}
++
++	avg_phy_rate = (pkt_cnt == 0) ? 0 : (u16)(phy_rate_sum / pkt_cnt);
++
++	return avg_phy_rate;
++}
++
++void phydm_print_hist_2_buf(void *dm_void, u16 *val, u16 len, char *buf,
++			    u16 buf_size)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (len == PHY_HIST_SIZE) {
++		PHYDM_SNPRINTF(buf, buf_size,
++			       "[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]",
++			       val[0], val[1], val[2], val[3], val[4],
++			       val[5], val[6], val[7], val[8], val[9],
++			       val[10], val[11]);
++	} else if (len == (PHY_HIST_SIZE - 1)) {
++		PHYDM_SNPRINTF(buf, buf_size,
++			       "[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]",
++			       val[0], val[1], val[2], val[3], val[4],
++			       val[5], val[6], val[7], val[8], val[9],
++			       val[10]);
++	}
++}
++
++void phydm_nss_hitogram(void *dm_void, enum PDM_RATE_TYPE rate_type)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
++	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
++	char buf[PHYDM_SNPRINT_SIZE] = {0};
++	u16 buf_size = PHYDM_SNPRINT_SIZE;
++	u16 h_size = PHY_HIST_SIZE;
++	u16 *evm_hist = &dbg_s->evm_1ss_hist[0];
++	u16 *snr_hist = &dbg_s->snr_1ss_hist[0];
++	u8 i = 0;
++	u8 ss = phydm_rate_type_2_num_ss(dm, rate_type);
++
++	for (i = 0; i < ss; i++) {
++		if (rate_type == PDM_1SS) {
++			evm_hist = &dbg_s->evm_1ss_hist[0];
++			snr_hist = &dbg_s->snr_1ss_hist[0];
++		} else if (rate_type == PDM_2SS) {
++			#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++			evm_hist = &dbg_s->evm_2ss_hist[i][0];
++			snr_hist = &dbg_s->snr_2ss_hist[i][0];
++			#endif
++		} else if (rate_type == PDM_3SS) {
++			#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++			evm_hist = &dbg_s->evm_3ss_hist[i][0];
++			snr_hist = &dbg_s->snr_3ss_hist[i][0];
++			#endif
++		} else if (rate_type == PDM_4SS) {
++			#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++			evm_hist = &dbg_s->evm_4ss_hist[i][0];
++			snr_hist = &dbg_s->snr_4ss_hist[i][0];
++			#endif
++		}
++
++		phydm_print_hist_2_buf(dm, evm_hist, h_size, buf, buf_size);
++		PHYDM_DBG(dm, DBG_CMN, "[%d-SS][EVM][%d]=%s\n", ss, i, buf);
++		phydm_print_hist_2_buf(dm, snr_hist, h_size, buf, buf_size);
++		PHYDM_DBG(dm, DBG_CMN, "[%d-SS][SNR][%d]=%s\n",  ss, i, buf);
++	}
++}
++
++#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
++void phydm_show_cn_hitogram(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
++	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
++	u16 th_tmp[PHY_HIST_TH_SIZE];
++	char buf[PHYDM_SNPRINT_SIZE] = {0};
++	u8 i = 0;
++	u16 *cn_hist = NULL;
++	u32 cn_avg = 0;
++
++	if (!dm->pkt_proc_struct.physts_auto_swch_en)
++		return;
++
++	if (dm->num_rf_path == 1)
++		return;
++
++	PHYDM_DBG(dm, DBG_CMN, "[Condition number Histogram] ========>\n");
++/*@===[Threshold]=============================================================*/
++	for (i = 0; i < PHY_HIST_TH_SIZE; i++)
++		th_tmp[i] = dbg_i->cn_hist_th[i] >> 1;
++
++	phydm_print_hist_2_buf(dm, th_tmp,
++			       PHY_HIST_TH_SIZE, buf, PHYDM_SNPRINT_SIZE);
++	PHYDM_DBG(dm, DBG_CMN, "%-24s=%s\n", "[CN_TH]", buf);
++
++/*@===[Histogram]=============================================================*/
++
++	for (i = 1; i <= dm->num_rf_path; i++) {
++		if (dbg_s->p4_cnt[i] == 0)
++			continue;
++
++		cn_avg = PHYDM_DIV((dbg_s->cn_sum[i] +
++				   (dbg_s->p4_cnt[i] >> 1)) << 2,
++				   dbg_s->p4_cnt[i]); /*u(8,1)<<2 -> u(10,3)*/
++
++		cn_hist = &dbg_s->cn_hist[i][0];
++		phydm_print_hist_2_buf(dm, cn_hist,
++				       PHY_HIST_SIZE, buf, PHYDM_SNPRINT_SIZE);
++		PHYDM_DBG(dm, DBG_CMN, "[%d-SS]%s=(avg:%d.%4d)%s\n",
++			  i + 1, "[CN]", cn_avg >> 3,
++			  phydm_show_fraction_num(cn_avg & 0x7, 3), buf);
++	}
++}
++#endif
++
++void phydm_show_phy_hitogram(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
++	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
++	char buf[PHYDM_SNPRINT_SIZE] = {0};
++	u16 buf_size = PHYDM_SNPRINT_SIZE;
++	u16 th_size = PHY_HIST_SIZE - 1;
++	u8 i = 0;
++
++	PHYDM_DBG(dm, DBG_CMN, "[PHY Histogram] ==============>\n");
++/*@===[Threshold]=============================================================*/
++	phydm_print_hist_2_buf(dm, dbg_i->evm_hist_th, th_size, buf, buf_size);
++	PHYDM_DBG(dm, DBG_CMN, "%-16s=%s\n", "[EVM_TH]", buf);
++
++	phydm_print_hist_2_buf(dm, dbg_i->snr_hist_th, th_size, buf, buf_size);
++	PHYDM_DBG(dm, DBG_CMN, "%-16s=%s\n", "[SNR_TH]", buf);
++/*@===[OFDM]==================================================================*/
++	if (dbg_s->rssi_ofdm_cnt) {
++		phydm_print_hist_2_buf(dm, dbg_s->evm_ofdm_hist, PHY_HIST_SIZE,
++				       buf, buf_size);
++		PHYDM_DBG(dm, DBG_CMN, "%-14s=%s\n", "[OFDM][EVM]", buf);
++
++		phydm_print_hist_2_buf(dm, dbg_s->snr_ofdm_hist, PHY_HIST_SIZE,
++				       buf, buf_size);
++		PHYDM_DBG(dm, DBG_CMN, "%-14s=%s\n", "[OFDM][SNR]", buf);
++	}
++/*@===[1-SS]==================================================================*/
++	if (dbg_s->rssi_1ss_cnt)
++		phydm_nss_hitogram(dm, PDM_1SS);
++/*@===[2-SS]==================================================================*/
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	if ((dm->support_ic_type & PHYDM_IC_ABOVE_2SS) && dbg_s->rssi_2ss_cnt)
++		phydm_nss_hitogram(dm, PDM_2SS);
++	#endif
++/*@===[3-SS]==================================================================*/
++	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++	if ((dm->support_ic_type & PHYDM_IC_ABOVE_3SS) && dbg_s->rssi_3ss_cnt)
++		phydm_nss_hitogram(dm, PDM_3SS);
++	#endif
++/*@===[4-SS]==================================================================*/
++	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS && dbg_s->rssi_4ss_cnt)
++		phydm_nss_hitogram(dm, PDM_4SS);
++	#endif
++}
++
++void phydm_avg_phy_val_nss(void *dm_void, u8 nss)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
++	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
++	struct phydm_phystatus_avg *dbg_avg = &dbg_i->phystatus_statistic_avg;
++	char *rate_type = NULL;
++	u32 *tmp_cnt = NULL;
++	u8 *tmp_rssi_avg = NULL;
++	u32 *tmp_rssi_sum = NULL;
++	u8 *tmp_snr_avg = NULL;
++	u32 *tmp_snr_sum = NULL;
++	u8 *tmp_evm_avg = NULL;
++	u32 *tmp_evm_sum = NULL;
++	u8 evm_rpt_show[RF_PATH_MEM_SIZE];
++	u8 i = 0;
++
++	odm_memory_set(dm, &evm_rpt_show[0], 0, RF_PATH_MEM_SIZE);
++
++	switch (nss) {
++	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	case 4:
++		rate_type = "[4-SS]";
++		tmp_cnt = &dbg_s->rssi_4ss_cnt;
++		tmp_rssi_avg = &dbg_avg->rssi_4ss_avg[0];
++		tmp_snr_avg = &dbg_avg->snr_4ss_avg[0];
++		tmp_rssi_sum = &dbg_s->rssi_4ss_sum[0];
++		tmp_snr_sum = &dbg_s->snr_4ss_sum[0];
++		tmp_evm_avg = &dbg_avg->evm_4ss_avg[0];
++		tmp_evm_sum = &dbg_s->evm_4ss_sum[0];
++		break;
++	#endif
++	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++	case 3:
++		rate_type = "[3-SS]";
++		tmp_cnt = &dbg_s->rssi_3ss_cnt;
++		tmp_rssi_avg = &dbg_avg->rssi_3ss_avg[0];
++		tmp_snr_avg = &dbg_avg->snr_3ss_avg[0];
++		tmp_rssi_sum = &dbg_s->rssi_3ss_sum[0];
++		tmp_snr_sum = &dbg_s->snr_3ss_sum[0];
++		tmp_evm_avg = &dbg_avg->evm_3ss_avg[0];
++		tmp_evm_sum = &dbg_s->evm_3ss_sum[0];
++		break;
++	#endif
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	case 2:
++		rate_type = "[2-SS]";
++		tmp_cnt = &dbg_s->rssi_2ss_cnt;
++		tmp_rssi_avg = &dbg_avg->rssi_2ss_avg[0];
++		tmp_snr_avg = &dbg_avg->snr_2ss_avg[0];
++		tmp_rssi_sum = &dbg_s->rssi_2ss_sum[0];
++		tmp_snr_sum = &dbg_s->snr_2ss_sum[0];
++		tmp_evm_avg = &dbg_avg->evm_2ss_avg[0];
++		tmp_evm_sum = &dbg_s->evm_2ss_sum[0];
++		break;
++	#endif
++	case 1:
++		rate_type = "[1-SS]";
++		tmp_cnt = &dbg_s->rssi_1ss_cnt;
++		tmp_rssi_avg = &dbg_avg->rssi_1ss_avg[0];
++		tmp_snr_avg = &dbg_avg->snr_1ss_avg[0];
++		tmp_rssi_sum = &dbg_s->rssi_1ss_sum[0];
++		tmp_snr_sum = &dbg_s->snr_1ss_sum[0];
++		tmp_evm_avg = &dbg_avg->evm_1ss_avg;
++		tmp_evm_sum = &dbg_s->evm_1ss_sum;
++		break;
++	case 0:
++		rate_type = "[L-OFDM]";
++		tmp_cnt = &dbg_s->rssi_ofdm_cnt;
++		tmp_rssi_avg = &dbg_avg->rssi_ofdm_avg[0];
++		tmp_snr_avg = &dbg_avg->snr_ofdm_avg[0];
++		tmp_rssi_sum = &dbg_s->rssi_ofdm_sum[0];
++		tmp_snr_sum = &dbg_s->snr_ofdm_sum[0];
++		tmp_evm_avg = &dbg_avg->evm_ofdm_avg;
++		tmp_evm_sum = &dbg_s->evm_ofdm_sum;
++		break;
++	default:
++		PHYDM_DBG(dm, DBG_CMN, "[warning] %s\n", __func__);
++		return;
++	}
++
++	if (*tmp_cnt != 0) {
++		for (i = 0; i < dm->num_rf_path; i++) {
++			tmp_rssi_avg[i] = (u8)(tmp_rssi_sum[i] / *tmp_cnt);
++			tmp_snr_avg[i] = (u8)(tmp_snr_sum[i] / *tmp_cnt);
++		}
++
++		if (nss == 0 || nss == 1) {
++			*tmp_evm_avg = (u8)(*tmp_evm_sum / *tmp_cnt);
++			evm_rpt_show[0] = *tmp_evm_avg;
++		} else {
++			for (i = 0; i < nss; i++) {
++				tmp_evm_avg[i] = (u8)(tmp_evm_sum[i] /
++						      *tmp_cnt);
++				evm_rpt_show[i] = tmp_evm_avg[i];
++			}
++		}
++	}
++
++#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	PHYDM_DBG(dm, DBG_CMN,
++		  "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d} SNR:{%.2d, %.2d, %.2d, %.2d} EVM:{-%.2d, -%.2d, -%.2d, -%.2d}\n",
++		  rate_type, *tmp_cnt,
++		  tmp_rssi_avg[0], tmp_rssi_avg[1], tmp_rssi_avg[2],
++		  tmp_rssi_avg[3], tmp_snr_avg[0], tmp_snr_avg[1],
++		  tmp_snr_avg[2], tmp_snr_avg[3], evm_rpt_show[0],
++		  evm_rpt_show[1], evm_rpt_show[2], evm_rpt_show[3]);
++#elif (defined(PHYDM_COMPILE_ABOVE_3SS))
++	PHYDM_DBG(dm, DBG_CMN,
++		  "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d} SNR:{%.2d, %.2d, %.2d} EVM:{-%.2d, -%.2d, -%.2d}\n",
++		  rate_type, *tmp_cnt,
++		  tmp_rssi_avg[0], tmp_rssi_avg[1], tmp_rssi_avg[2],
++		  tmp_snr_avg[0], tmp_snr_avg[1], tmp_snr_avg[2],
++		  evm_rpt_show[0], evm_rpt_show[1], evm_rpt_show[2]);
++#elif (defined(PHYDM_COMPILE_ABOVE_2SS))
++	PHYDM_DBG(dm, DBG_CMN,
++		  "* %-8s Cnt= ((%.3d)) RSSI:{%.2d, %.2d} SNR:{%.2d, %.2d} EVM:{-%.2d, -%.2d}\n",
++		  rate_type, *tmp_cnt,
++		  tmp_rssi_avg[0], tmp_rssi_avg[1],
++		  tmp_snr_avg[0], tmp_snr_avg[1],
++		  evm_rpt_show[0], evm_rpt_show[1]);
++#else
++	PHYDM_DBG(dm, DBG_CMN,
++		  "* %-8s Cnt= ((%.3d)) RSSI:{%.2d} SNR:{%.2d} EVM:{-%.2d}\n",
++		  rate_type, *tmp_cnt,
++		  tmp_rssi_avg[0], tmp_snr_avg[0], evm_rpt_show[0]);
++#endif
++}
++
++void phydm_get_avg_phystatus_val(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
++	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
++	struct phydm_phystatus_avg *dbg_avg = &dbg_i->phystatus_statistic_avg;
++	u32 avg_tmp = 0;
++	u8 i = 0;
++
++	PHYDM_DBG(dm, DBG_CMN, "[PHY Avg] ==============>\n");
++	phydm_reset_phystatus_avg(dm);
++
++	/*@===[Beacon]===*/
++	if (dbg_s->rssi_beacon_cnt) {
++		for (i = 0; i < dm->num_rf_path; i++) {
++			avg_tmp = dbg_s->rssi_beacon_sum[i] /
++				  dbg_s->rssi_beacon_cnt;
++			dbg_avg->rssi_beacon_avg[i] = (u8)avg_tmp;
++		}
++	}
++
++	switch (dm->num_rf_path) {
++#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	case 4:
++		PHYDM_DBG(dm, DBG_CMN,
++			  "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n",
++			  "[Beacon]", dbg_s->rssi_beacon_cnt,
++			  dbg_avg->rssi_beacon_avg[0],
++			  dbg_avg->rssi_beacon_avg[1],
++			  dbg_avg->rssi_beacon_avg[2],
++			  dbg_avg->rssi_beacon_avg[3]);
++		break;
++#endif
++#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++	case 3:
++		PHYDM_DBG(dm, DBG_CMN,
++			  "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n",
++			  "[Beacon]", dbg_s->rssi_beacon_cnt,
++			  dbg_avg->rssi_beacon_avg[0],
++			  dbg_avg->rssi_beacon_avg[1],
++			  dbg_avg->rssi_beacon_avg[2]);
++		break;
++#endif
++#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	case 2:
++		PHYDM_DBG(dm, DBG_CMN,
++			  "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n",
++			  "[Beacon]", dbg_s->rssi_beacon_cnt,
++			  dbg_avg->rssi_beacon_avg[0],
++			  dbg_avg->rssi_beacon_avg[1]);
++		break;
++#endif
++	default:
++		PHYDM_DBG(dm, DBG_CMN, "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n",
++			  "[Beacon]", dbg_s->rssi_beacon_cnt,
++			  dbg_avg->rssi_beacon_avg[0]);
++		break;
++	}
++
++	/*@===[CCK]===*/
++	if (dbg_s->rssi_cck_cnt) {
++		dbg_avg->rssi_cck_avg = (u8)(dbg_s->rssi_cck_sum /
++					     dbg_s->rssi_cck_cnt);
++		#ifdef PHYSTS_3RD_TYPE_SUPPORT
++		if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) {
++			for (i = 0; i < dm->num_rf_path - 1; i++) {
++				avg_tmp = dbg_s->rssi_cck_sum_abv_2ss[i] /
++					  dbg_s->rssi_cck_cnt;
++				dbg_avg->rssi_cck_avg_abv_2ss[i] = (u8)avg_tmp;
++			}
++		}
++		#endif
++	}
++
++	switch (dm->num_rf_path) {
++#ifdef PHYSTS_3RD_TYPE_SUPPORT
++	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	case 4:
++		PHYDM_DBG(dm, DBG_CMN,
++			  "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n",
++			  "[CCK]", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg,
++			  dbg_avg->rssi_cck_avg_abv_2ss[0],
++			  dbg_avg->rssi_cck_avg_abv_2ss[1],
++			  dbg_avg->rssi_cck_avg_abv_2ss[2]);
++		break;
++	#endif
++	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++	case 3:
++		PHYDM_DBG(dm, DBG_CMN,
++			  "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n",
++			  "[CCK]", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg,
++			  dbg_avg->rssi_cck_avg_abv_2ss[0],
++			  dbg_avg->rssi_cck_avg_abv_2ss[1]);
++		break;
++	#endif
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	case 2:
++		PHYDM_DBG(dm, DBG_CMN,
++			  "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n",
++			  "[CCK]", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg,
++			  dbg_avg->rssi_cck_avg_abv_2ss[0]);
++		break;
++	#endif
++#endif
++	default:
++		PHYDM_DBG(dm, DBG_CMN, "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n",
++			  "[CCK]", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg);
++		break;
++	}
++
++	for (i = 0; i <= dm->num_rf_path; i++)
++		phydm_avg_phy_val_nss(dm, i);
++}
++
++void phydm_get_phy_statistic(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *sta = dm->phydm_sta_info[dm->one_entry_macid];
++	enum channel_width bw;
++	u16 avg_phy_rate = 0;
++	u16 utility = 0;
++	u8 rx_ss = 1;
++
++	avg_phy_rate = phydm_rx_avg_phy_rate(dm);
++
++	if (dm->is_one_entry_only && is_sta_active(sta)) {
++		rx_ss = phydm_get_rx_stream_num(dm, sta->mimo_type);
++		bw = sta->bw_mode;
++		utility = phydm_rx_utility(dm, avg_phy_rate, rx_ss, bw);
++	}
++	PHYDM_DBG(dm, DBG_CMN, "Avg_rx_rate = %d, rx_utility=( %d / 1000 )\n",
++		  avg_phy_rate, utility);
++
++	phydm_rx_rate_distribution(dm);
++	phydm_reset_rx_rate_distribution(dm);
++
++	phydm_show_phy_hitogram(dm);
++	#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
++	phydm_show_cn_hitogram(dm);
++	#endif
++	phydm_get_avg_phystatus_val(dm);
++	phydm_reset_phystatus_statistic(dm);
++};
++
++void phydm_basic_dbg_msg_linked(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track;
++	struct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info;
++	u16 macid, client_cnt = 0;
++	u8 rate = 0;
++	struct cmn_sta_info *entry = NULL;
++	char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
++	struct phydm_cfo_rpt cfo;
++	u8 i = 0;
++
++	PHYDM_DBG(dm, DBG_CMN, "ID=((%d)), BW=((%d)), fc=((CH-%d))\n",
++		  dm->curr_station_id, 20 << *dm->band_width, *dm->channel);
++
++	#ifdef ODM_IC_11N_SERIES_SUPPORT
++	#ifdef PHYDM_PRIMARY_CCA
++	if (((*dm->channel <= 14) && (*dm->band_width == CHANNEL_WIDTH_40)) &&
++	    (dm->support_ic_type & ODM_IC_11N_SERIES)) {
++		PHYDM_DBG(dm, DBG_CMN, "Primary CCA at ((%s SB))\n",
++			  ((*dm->sec_ch_offset == SECOND_CH_AT_LSB) ? "U" :
++			  "L"));
++	}
++	#endif
++	#endif
++
++	if (dm->cck_new_agc || dm->rx_rate > ODM_RATE11M) {
++		PHYDM_DBG(dm, DBG_CMN, "[AGC Idx] {0x%x, 0x%x, 0x%x, 0x%x}\n",
++			  dm->ofdm_agc_idx[0], dm->ofdm_agc_idx[1],
++			  dm->ofdm_agc_idx[2], dm->ofdm_agc_idx[3]);
++	} else {
++		PHYDM_DBG(dm, DBG_CMN, "[CCK AGC Idx] {LNA,VGA}={0x%x, 0x%x}\n",
++			  dm->cck_lna_idx, dm->cck_vga_idx);
++	}
++
++	phydm_print_rate_2_buff(dm, dm->rx_rate, dbg_buf, PHYDM_SNPRINT_SIZE);
++	PHYDM_DBG(dm, DBG_CMN, "RSSI:{%d, %d, %d, %d}, RxRate:%s (0x%x)\n",
++		  (dm->rssi_a == 0xff) ? 0 : dm->rssi_a,
++		  (dm->rssi_b == 0xff) ? 0 : dm->rssi_b,
++		  (dm->rssi_c == 0xff) ? 0 : dm->rssi_c,
++		  (dm->rssi_d == 0xff) ? 0 : dm->rssi_d,
++		  dbg_buf, dm->rx_rate);
++
++	rate = dbg_t->beacon_phy_rate;
++	phydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE);
++
++	PHYDM_DBG(dm, DBG_CMN, "Beacon_cnt=%d, rate_idx=%s (0x%x)\n",
++		  dbg_t->num_qry_beacon_pkt, dbg_buf, dbg_t->beacon_phy_rate);
++
++	phydm_get_phy_statistic(dm);
++
++	PHYDM_DBG(dm, DBG_CMN,
++		  "rxsc_idx {Legacy, 20, 40, 80} = {%d, %d, %d, %d}\n",
++		  dm->rxsc_l, dm->rxsc_20, dm->rxsc_40, dm->rxsc_80);
++
++	/*Print TX rate*/
++	for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
++		entry = dm->phydm_sta_info[macid];
++
++		if (!is_sta_active(entry))
++			continue;
++
++		rate = entry->ra_info.curr_tx_rate;
++		phydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE);
++		PHYDM_DBG(dm, DBG_CMN, "TxRate[%d]=%s (0x%x)\n",
++			  macid, dbg_buf, entry->ra_info.curr_tx_rate);
++
++		client_cnt++;
++
++		if (client_cnt >= dm->number_linked_client)
++			break;
++	}
++
++	PHYDM_DBG(dm, DBG_CMN,
++		  "TP {Tx, Rx, Total} = {%d, %d, %d}Mbps, Traffic_Load=(%d))\n",
++		  dm->tx_tp, dm->rx_tp, dm->total_tp, dm->traffic_load);
++
++	PHYDM_DBG(dm, DBG_CMN, "CFO_avg=((%d kHz)), CFO_traking = ((%s%d))\n",
++		  cfo_t->CFO_ave_pre,
++		  ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"),
++		  DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap));
++
++	/* @CFO report */
++	switch (dm->ic_ip_series) {
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	case PHYDM_IC_JGR3:
++		PHYDM_DBG(dm, DBG_CMN, "cfo_tail = {%d, %d, %d, %d}\n",
++			  dbg_t->cfo_tail[0], dbg_t->cfo_tail[1],
++			  dbg_t->cfo_tail[2], dbg_t->cfo_tail[3]);
++		break;
++	#endif
++	default:
++		phydm_get_cfo_info(dm, &cfo);
++		for (i = 0; i < dm->num_rf_path; i++) {
++			PHYDM_DBG(dm, DBG_CMN,
++				  "CFO[%d] {S, L, Sec, Acq, End} = {%d, %d, %d, %d, %d}\n",
++				  i, cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i],
++				  cfo.cfo_rpt_sec[i], cfo.cfo_rpt_acq[i],
++				  cfo.cfo_rpt_end[i]);
++		}
++		break;
++	}
++
++/* @Condition number */
++#if (RTL8822B_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8822B) {
++		PHYDM_DBG(dm, DBG_CMN, "Condi_Num=((%d.%.4d)), %d\n",
++			  dbg_t->condi_num >> 4,
++			  phydm_show_fraction_num(dbg_t->condi_num & 0xf, 4),
++			  dbg_t->condi_num);
++	}
++#endif
++#ifdef PHYSTS_3RD_TYPE_SUPPORT
++	if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) {
++		PHYDM_DBG(dm, DBG_CMN, "Condi_Num=((%d.%4d dB))\n",
++			  dbg_t->condi_num >> 1,
++			  phydm_show_fraction_num(dbg_t->condi_num & 0x1, 1));
++	}
++#endif
++
++#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT))
++	/*STBC or LDPC pkt*/
++	if (dm->support_ic_type & (PHYSTS_2ND_TYPE_IC | PHYSTS_3RD_TYPE_IC))
++		PHYDM_DBG(dm, DBG_CMN, "Coding: LDPC=((%s)), STBC=((%s))\n",
++			  (dbg_t->is_ldpc_pkt) ? "Y" : "N",
++			  (dbg_t->is_stbc_pkt) ? "Y" : "N");
++#endif
++
++#if (RTL8822C_SUPPORT)
++	/*Beamformed pkt*/
++	if (dm->support_ic_type == ODM_RTL8822C)
++		PHYDM_DBG(dm, DBG_CMN, "Beamformed=((%s))\n",
++			  (dm->is_beamformed) ? "Y" : "N");
++#endif
++}
++
++void phydm_dm_summary(void *dm_void, u8 macid)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track;
++	struct cmn_sta_info *sta = NULL;
++	struct ra_sta_info *ra = NULL;
++	struct dtp_info *dtp = NULL;
++	u64 comp = dm->support_ability;
++	u64 pause_comp = dm->pause_ability;
++
++	if (!(dm->debug_components & DBG_DM_SUMMARY))
++		return;
++
++	if (!dm->is_linked) {
++		pr_debug("[%s]No Link !!!\n", __func__);
++		return;
++	}
++
++	sta = dm->phydm_sta_info[macid];
++
++	if (!is_sta_active(sta)) {
++		pr_debug("[Warning] %s invalid STA, macid=%d\n",
++			 __func__, macid);
++		return;
++	}
++
++	ra = &sta->ra_info;
++	dtp = &sta->dtp_stat;
++	pr_debug("[%s]===========>\n", __func__);
++
++	pr_debug("00.(%s) %-12s: IGI=0x%x, Dyn_Rng=0x%x~0x%x, FA_th={%d,%d,%d}\n",
++		 ((comp & ODM_BB_DIG) ?
++		 ((pause_comp & ODM_BB_DIG) ? "P" : "V") : "."),
++		 "DIG",
++		 dig_t->cur_ig_value,
++		 dig_t->rx_gain_range_min, dig_t->rx_gain_range_max,
++		 dig_t->fa_th[0], dig_t->fa_th[1], dig_t->fa_th[2]);
++
++	pr_debug("01.(%s) %-12s: rssi_lv=%d, mask=0x%llx\n",
++		 ((comp & ODM_BB_RA_MASK) ?
++		 ((pause_comp & ODM_BB_RA_MASK) ? "P" : "V") : "."),
++		 "RaMask",
++		 ra->rssi_level, ra->ramask);
++
++#ifdef CONFIG_DYNAMIC_TX_TWR
++	pr_debug("02.(%s) %-12s: pwr_lv=%d\n",
++		 ((comp & ODM_BB_DYNAMIC_TXPWR) ?
++		 ((pause_comp & ODM_BB_DYNAMIC_TXPWR) ? "P" : "V") : "."),
++		 "DynTxPwr",
++		 dtp->sta_tx_high_power_lvl);
++#endif
++
++	pr_debug("05.(%s) %-12s: cck_pd_lv=%d\n",
++		 ((comp & ODM_BB_CCK_PD) ?
++		 ((pause_comp & ODM_BB_CCK_PD) ? "P" : "V") : "."),
++		 "CCK_PD", dm->dm_cckpd_table.cck_pd_lv);
++
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	pr_debug("06.(%s) %-12s: div_type=%d, curr_ant=%s\n",
++		 ((comp & ODM_BB_ANT_DIV) ?
++		 ((pause_comp & ODM_BB_ANT_DIV) ? "P" : "V") : "."),
++		 "ANT_DIV",
++		 dm->ant_div_type,
++		 (dm->dm_fat_table.rx_idle_ant == MAIN_ANT) ? "MAIN" : "AUX");
++#endif
++
++#ifdef PHYDM_POWER_TRAINING_SUPPORT
++	pr_debug("08.(%s) %-12s: PT_score=%d, disable_PT=%d\n",
++		 ((comp & ODM_BB_PWR_TRAIN) ?
++		 ((pause_comp & ODM_BB_PWR_TRAIN) ? "P" : "V") : "."),
++		 "PwrTrain",
++		 dm->pow_train_table.pow_train_score,
++		 dm->is_disable_power_training);
++#endif
++
++#ifdef CONFIG_PHYDM_DFS_MASTER
++	pr_debug("11.(%s) %-12s: dbg_mode=%d, region_domain=%d\n",
++		 ((comp & ODM_BB_DFS) ?
++		 ((pause_comp & ODM_BB_DFS) ? "P" : "V") : "."),
++		 "DFS",
++		 dm->dfs.dbg_mode, dm->dfs_region_domain);
++#endif
++#ifdef PHYDM_SUPPORT_ADAPTIVITY
++	pr_debug("13.(%s) %-12s: th{l2h, h2l}={%d, %d}, edcca_flag=%d\n",
++		 ((comp & ODM_BB_ADAPTIVITY) ?
++		 ((pause_comp & ODM_BB_ADAPTIVITY) ? "P" : "V") : "."),
++		 "Adaptivity",
++		 dm->adaptivity.th_l2h, dm->adaptivity.th_h2l,
++		 dm->false_alm_cnt.edcca_flag);
++#endif
++	pr_debug("14.(%s) %-12s: CFO_avg=%d kHz, CFO_traking=%s%d\n",
++		 ((comp & ODM_BB_CFO_TRACKING) ?
++		 ((pause_comp & ODM_BB_CFO_TRACKING) ? "P" : "V") : "."),
++		 "CfoTrack",
++		 cfo_t->CFO_ave_pre,
++		 ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"),
++		 DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap));
++
++	pr_debug("15.(%s) %-12s: ratio{nhm, clm}={%d, %d}\n",
++		 ((comp & ODM_BB_ENV_MONITOR) ?
++		 ((pause_comp & ODM_BB_ENV_MONITOR) ? "P" : "V") : "."),
++		 "EnvMntr",
++		 dm->dm_ccx_info.nhm_ratio, dm->dm_ccx_info.clm_ratio);
++
++#ifdef PHYDM_PRIMARY_CCA
++	pr_debug("16.(%s) %-12s: CCA @ (%s SB)\n",
++		 ((comp & ODM_BB_PRIMARY_CCA) ?
++		 ((pause_comp & ODM_BB_PRIMARY_CCA) ? "P" : "V") : "."),
++		 "PriCCA",
++		 ((dm->dm_pri_cca.mf_state == MF_USC_LSC) ? "D" :
++		 ((dm->dm_pri_cca.mf_state == MF_LSC) ? "L" : "U")));
++#endif
++#ifdef CONFIG_ADAPTIVE_SOML
++	pr_debug("17.(%s) %-12s: soml_en = %s\n",
++		 ((comp & ODM_BB_ADAPTIVE_SOML) ?
++		 ((pause_comp & ODM_BB_ADAPTIVE_SOML) ? "P" : "V") : "."),
++		 "A-SOML",
++		 (dm->dm_soml_table.soml_last_state == SOML_ON) ?
++		 "ON" : "OFF");
++#endif
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++	pr_debug("18.(%s) %-12s:\n",
++		 ((comp & ODM_BB_LNA_SAT_CHK) ?
++		 ((pause_comp & ODM_BB_LNA_SAT_CHK) ? "P" : "V") : "."),
++		 "LNA_SAT_CHK");
++#endif
++}
++
++void phydm_basic_dbg_message(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
++	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
++	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct odm_phy_dbg_info *dbg_b = &dm->phy_dbg_info_win_bkp;
++	#endif
++	#ifdef NHM_SUPPORT
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	#endif
++
++	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	/* backup memory*/
++	odm_move_memory(dm, dbg_b, dbg, sizeof(struct odm_phy_dbg_info));
++	#endif
++
++	if (!(dm->debug_components & DBG_CMN)) {
++		#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++		/* reset rx rate distribution*/
++		phydm_reset_rx_rate_distribution(dm);
++		/* cal & reset avg of rssi/snr/evm*/
++		phydm_get_avg_phystatus_val(dm);
++		/* reset sum of rssi/snr/evm*/
++		phydm_reset_phystatus_statistic(dm);
++		#endif
++		return;
++	}
++
++	if (dm->cmn_dbg_msg_cnt >= dm->cmn_dbg_msg_period) {
++		dm->cmn_dbg_msg_cnt = PHYDM_WATCH_DOG_PERIOD;
++	} else {
++		dm->cmn_dbg_msg_cnt += PHYDM_WATCH_DOG_PERIOD;
++		return;
++	}
++
++	PHYDM_DBG(dm, DBG_CMN, "[%s] System up time: ((%d sec))---->\n",
++		  __func__, dm->phydm_sys_up_time);
++
++	if (dm->is_linked)
++		phydm_basic_dbg_msg_linked(dm);
++	else
++		PHYDM_DBG(dm, DBG_CMN, "No Link !!!\n");
++
++	PHYDM_DBG(dm, DBG_CMN, "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
++		  fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);
++	PHYDM_DBG(dm, DBG_CMN, "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
++		  fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all);
++	PHYDM_DBG(dm, DBG_CMN,
++		  "[OFDM FA] Parity=%d, Rate=%d, Fast_Fsync=%d, SBD=%d\n",
++		  fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
++		  fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail);
++	PHYDM_DBG(dm, DBG_CMN, "[HT FA] CRC8=%d, MCS=%d\n",
++		  fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail);
++#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
++	if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
++		PHYDM_DBG(dm, DBG_CMN,
++			  "[VHT FA] SIGA_CRC8=%d, SIGB_CRC8=%d, MCS=%d\n",
++			  fa_t->cnt_crc8_fail_vhta, fa_t->cnt_crc8_fail_vhtb,
++			  fa_t->cnt_mcs_fail_vht);
++	}
++#endif
++	PHYDM_DBG(dm, DBG_CMN,
++		  "[CRC32 OK Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n",
++		  fa_t->cnt_cck_crc32_ok, fa_t->cnt_ofdm_crc32_ok,
++		  fa_t->cnt_ht_crc32_ok, fa_t->cnt_vht_crc32_ok,
++		  fa_t->cnt_crc32_ok_all);
++	PHYDM_DBG(dm, DBG_CMN,
++		  "[CRC32 Err Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n",
++		  fa_t->cnt_cck_crc32_error, fa_t->cnt_ofdm_crc32_error,
++		  fa_t->cnt_ht_crc32_error, fa_t->cnt_vht_crc32_error,
++		  fa_t->cnt_crc32_error_all);
++
++	PHYDM_DBG(dm, DBG_CMN,
++		  "is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x, bNoisy=%d\n",
++		  dm->is_linked, dm->number_linked_client, dm->rssi_min,
++		  dm->dm_dig_table.cur_ig_value, dm->noisy_decision);
++
++#ifdef NHM_SUPPORT
++	if (dm->support_ability & ODM_BB_ENV_MONITOR) {
++		PHYDM_DBG(dm, DBG_CMN,
++			  "[NHM] valid: %d percent, noise(RSSI) = %d\n",
++			  ccx->nhm_level_valid, ccx->nhm_level);
++	}
++#endif
++}
++
++void phydm_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len)
++{
++#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	char *cut = NULL;
++	char *ic_type = NULL;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 date = 0;
++	char *commit_by = NULL;
++	u32 release_ver = 0;
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n",
++		 "% Basic Profile %");
++
++	if (dm->support_ic_type == ODM_RTL8188E) {
++#if (RTL8188E_SUPPORT)
++		ic_type = "RTL8188E";
++		date = RELEASE_DATE_8188E;
++		commit_by = COMMIT_BY_8188E;
++		release_ver = RELEASE_VERSION_8188E;
++#endif
++#if (RTL8812A_SUPPORT)
++	} else if (dm->support_ic_type == ODM_RTL8812) {
++		ic_type = "RTL8812A";
++		date = RELEASE_DATE_8812A;
++		commit_by = COMMIT_BY_8812A;
++		release_ver = RELEASE_VERSION_8812A;
++#endif
++#if (RTL8821A_SUPPORT)
++	} else if (dm->support_ic_type == ODM_RTL8821) {
++		ic_type = "RTL8821A";
++		date = RELEASE_DATE_8821A;
++		commit_by = COMMIT_BY_8821A;
++		release_ver = RELEASE_VERSION_8821A;
++#endif
++#if (RTL8192E_SUPPORT)
++	} else if (dm->support_ic_type == ODM_RTL8192E) {
++		ic_type = "RTL8192E";
++		date = RELEASE_DATE_8192E;
++		commit_by = COMMIT_BY_8192E;
++		release_ver = RELEASE_VERSION_8192E;
++#endif
++#if (RTL8723B_SUPPORT)
++	} else if (dm->support_ic_type == ODM_RTL8723B) {
++		ic_type = "RTL8723B";
++		date = RELEASE_DATE_8723B;
++		commit_by = COMMIT_BY_8723B;
++		release_ver = RELEASE_VERSION_8723B;
++#endif
++#if (RTL8814A_SUPPORT)
++	} else if (dm->support_ic_type == ODM_RTL8814A) {
++		ic_type = "RTL8814A";
++		date = RELEASE_DATE_8814A;
++		commit_by = COMMIT_BY_8814A;
++		release_ver = RELEASE_VERSION_8814A;
++#endif
++#if (RTL8881A_SUPPORT)
++	} else if (dm->support_ic_type == ODM_RTL8881A) {
++		ic_type = "RTL8881A";
++#endif
++#if (RTL8822B_SUPPORT)
++	} else if (dm->support_ic_type == ODM_RTL8822B) {
++		ic_type = "RTL8822B";
++		date = RELEASE_DATE_8822B;
++		commit_by = COMMIT_BY_8822B;
++		release_ver = RELEASE_VERSION_8822B;
++#endif
++#if (RTL8197F_SUPPORT)
++	} else if (dm->support_ic_type == ODM_RTL8197F) {
++		ic_type = "RTL8197F";
++		date = RELEASE_DATE_8197F;
++		commit_by = COMMIT_BY_8197F;
++		release_ver = RELEASE_VERSION_8197F;
++#endif
++#if (RTL8703B_SUPPORT)
++	} else if (dm->support_ic_type == ODM_RTL8703B) {
++		ic_type = "RTL8703B";
++		date = RELEASE_DATE_8703B;
++		commit_by = COMMIT_BY_8703B;
++		release_ver = RELEASE_VERSION_8703B;
++#endif
++#if (RTL8195A_SUPPORT)
++	} else if (dm->support_ic_type == ODM_RTL8195A) {
++		ic_type = "RTL8195A";
++#endif
++#if (RTL8188F_SUPPORT)
++	} else if (dm->support_ic_type == ODM_RTL8188F) {
++		ic_type = "RTL8188F";
++		date = RELEASE_DATE_8188F;
++		commit_by = COMMIT_BY_8188F;
++		release_ver = RELEASE_VERSION_8188F;
++#endif
++#if (RTL8723D_SUPPORT)
++	} else if (dm->support_ic_type == ODM_RTL8723D) {
++		ic_type = "RTL8723D";
++		date = RELEASE_DATE_8723D;
++		commit_by = COMMIT_BY_8723D;
++		release_ver = RELEASE_VERSION_8723D;
++#endif
++	}
++
++/* @JJ ADD 20161014 */
++#if (RTL8710B_SUPPORT)
++	else if (dm->support_ic_type == ODM_RTL8710B) {
++		ic_type = "RTL8710B";
++		date = RELEASE_DATE_8710B;
++		commit_by = COMMIT_BY_8710B;
++		release_ver = RELEASE_VERSION_8710B;
++	}
++#endif
++
++#if (RTL8721D_SUPPORT)
++	else if (dm->support_ic_type == ODM_RTL8721D) {
++		ic_type = "RTL8721D";
++		date = RELEASE_DATE_8721D;
++		commit_by = COMMIT_BY_8721D;
++		release_ver = RELEASE_VERSION_8721D;
++	}
++#endif
++
++#if (RTL8710C_SUPPORT)
++	else if (dm->support_ic_type == ODM_RTL8710C) {
++		ic_type = "RTL8710C";
++		date = RELEASE_DATE_8710C;
++		commit_by = COMMIT_BY_8710C;
++		release_ver = RELEASE_VERSION_8710C;
++	}
++#endif
++
++#if (RTL8821C_SUPPORT)
++	else if (dm->support_ic_type == ODM_RTL8821C) {
++		ic_type = "RTL8821C";
++		date = RELEASE_DATE_8821C;
++		commit_by = COMMIT_BY_8821C;
++		release_ver = RELEASE_VERSION_8821C;
++	}
++#endif
++
++/*@jj add 20170822*/
++#if (RTL8192F_SUPPORT)
++	else if (dm->support_ic_type == ODM_RTL8192F) {
++		ic_type = "RTL8192F";
++		date = RELEASE_DATE_8192F;
++		commit_by = COMMIT_BY_8192F;
++		release_ver = RELEASE_VERSION_8192F;
++	}
++#endif
++
++#if (RTL8198F_SUPPORT)
++	else if (dm->support_ic_type == ODM_RTL8198F) {
++		ic_type = "RTL8198F";
++		date = RELEASE_DATE_8198F;
++		commit_by = COMMIT_BY_8198F;
++		release_ver = RELEASE_VERSION_8198F;
++	}
++#endif
++
++#if (RTL8822C_SUPPORT)
++	else if (dm->support_ic_type == ODM_RTL8822C) {
++		ic_type = "RTL8822C";
++		date = RELEASE_DATE_8822C;
++		commit_by = COMMIT_BY_8822C;
++		release_ver = RELEASE_VERSION_8822C;
++	}
++#endif
++
++#if (RTL8812F_SUPPORT)
++	else if (dm->support_ic_type == ODM_RTL8812F) {
++		ic_type = "RTL8812F";
++		date = RELEASE_DATE_8812F;
++		commit_by = COMMIT_BY_8812F;
++		release_ver = RELEASE_VERSION_8812F;
++	}
++#endif
++
++#if (RTL8197G_SUPPORT)
++	else if (dm->support_ic_type == ODM_RTL8197G) {
++		ic_type = "RTL8197G";
++		date = RELEASE_DATE_8197G;
++		commit_by = COMMIT_BY_8197G;
++		release_ver = RELEASE_VERSION_8197G;
++	}
++#endif
++
++#if (RTL8814B_SUPPORT)
++	else if (dm->support_ic_type == ODM_RTL8814B) {
++		ic_type = "RTL8814B";
++		date = RELEASE_DATE_8814B;
++		commit_by = COMMIT_BY_8814B;
++		release_ver = RELEASE_VERSION_8814B;
++	}
++#endif
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "  %-35s: %s (MP Chip: %s)\n", "IC type", ic_type,
++		 dm->is_mp_chip ? "Yes" : "No");
++
++	if (dm->cut_version == ODM_CUT_A)
++		cut = "A";
++	else if (dm->cut_version == ODM_CUT_B)
++		cut = "B";
++	else if (dm->cut_version == ODM_CUT_C)
++		cut = "C";
++	else if (dm->cut_version == ODM_CUT_D)
++		cut = "D";
++	else if (dm->cut_version == ODM_CUT_E)
++		cut = "E";
++	else if (dm->cut_version == ODM_CUT_F)
++		cut = "F";
++	else if (dm->cut_version == ODM_CUT_G)
++		cut = "G";
++	else if (dm->cut_version == ODM_CUT_H)
++		cut = "H";
++	else if (dm->cut_version == ODM_CUT_I)
++		cut = "I";
++	else if (dm->cut_version == ODM_CUT_J)
++		cut = "J";
++	else if (dm->cut_version == ODM_CUT_K)
++		cut = "K";
++	else if (dm->cut_version == ODM_CUT_L)
++		cut = "L";
++	else if (dm->cut_version == ODM_CUT_M)
++		cut = "M";
++	else if (dm->cut_version == ODM_CUT_N)
++		cut = "N";
++	else if (dm->cut_version == ODM_CUT_O)
++		cut = "O";
++	else if (dm->cut_version == ODM_CUT_TEST)
++		cut = "TEST";
++	else
++		cut = "UNKNOWN";
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %d\n",
++		 "RFE type", dm->rfe_type);
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "CART_Ver", cut);
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %d\n",
++		 "PHY Para Ver", odm_get_hw_img_version(dm));
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %d\n",
++		 "PHY Para Commit date", date);
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "PHY Para Commit by", commit_by);
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %d\n",
++		 "PHY Para Release Ver", release_ver);
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "  %-35s: %d (Subversion: %d)\n", "FW Ver", dm->fw_version,
++		 dm->fw_sub_version);
++
++	/* @1 PHY DM version List */
++	PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n",
++		 "% PHYDM version %");
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "Code base", PHYDM_CODE_BASE);
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "Release Date", PHYDM_RELEASE_DATE);
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "Adaptivity", ADAPTIVITY_VERSION);
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "DIG", DIG_VERSION);
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "CFO Tracking", CFO_TRACKING_VERSION);
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "AntDiv", ANTDIV_VERSION);
++#endif
++#ifdef CONFIG_DYNAMIC_TX_TWR
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "Dynamic TxPower", DYNAMIC_TXPWR_VERSION);
++#endif
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "RA Info", RAINFO_VERSION);
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "AntDetect", ANTDECT_VERSION);
++#endif
++#ifdef CONFIG_PATH_DIVERSITY
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "PathDiv", PATHDIV_VERSION);
++#endif
++#ifdef CONFIG_ADAPTIVE_SOML
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "Adaptive SOML", ADAPTIVE_SOML_VERSION);
++#endif
++#if (PHYDM_LA_MODE_SUPPORT)
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "LA mode", DYNAMIC_LA_MODE);
++#endif
++#ifdef PHYDM_PRIMARY_CCA
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "Primary CCA", PRIMARYCCA_VERSION);
++#endif
++	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
++		 "DFS", DFS_VERSION);
++
++#if (RTL8822B_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8822B)
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "  %-35s: %s\n", "PHY config 8822B",
++			 PHY_CONFIG_VERSION_8822B);
++
++#endif
++#if (RTL8197F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8197F)
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "  %-35s: %s\n", "PHY config 8197F",
++			 PHY_CONFIG_VERSION_8197F);
++#endif
++
++/*@jj add 20170822*/
++#if (RTL8192F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8192F)
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "  %-35s: %s\n", "PHY config 8192F",
++			 PHY_CONFIG_VERSION_8192F);
++#endif
++#if (RTL8721D_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8721D)
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "  %-35s: %s\n", "PHY config 8721D",
++			 PHY_CONFIG_VERSION_8721D);
++#endif
++
++#if (RTL8710C_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8710C)
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "  %-35s: %s\n", "PHY config 8710C",
++			 PHY_CONFIG_VERSION_8710C);
++#endif
++
++	*_used = used;
++	*_out_len = out_len;
++
++#endif /*@#if CONFIG_PHYDM_DEBUG_FUNCTION*/
++}
++
++#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
++void phydm_fw_trace_en_h2c(void *dm_void, boolean enable,
++			   u32 fw_dbg_comp, u32 monitor_mode, u32 macid)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 h2c_parameter[7] = {0};
++	u8 cmd_length;
++
++	if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
++		h2c_parameter[0] = enable;
++		h2c_parameter[1] = (u8)(fw_dbg_comp & MASKBYTE0);
++		h2c_parameter[2] = (u8)((fw_dbg_comp & MASKBYTE1) >> 8);
++		h2c_parameter[3] = (u8)((fw_dbg_comp & MASKBYTE2) >> 16);
++		h2c_parameter[4] = (u8)((fw_dbg_comp & MASKBYTE3) >> 24);
++		h2c_parameter[5] = (u8)monitor_mode;
++		h2c_parameter[6] = (u8)macid;
++		cmd_length = 7;
++
++	} else {
++		h2c_parameter[0] = enable;
++		h2c_parameter[1] = (u8)monitor_mode;
++		h2c_parameter[2] = (u8)macid;
++		cmd_length = 3;
++	}
++
++	PHYDM_DBG(dm, DBG_FW_TRACE,
++		  "[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\n",
++		  enable, monitor_mode, macid);
++
++	odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_TRACE_EN, cmd_length, h2c_parameter);
++}
++
++void phydm_get_per_path_txagc(void *dm_void, u8 path, u32 *_used, char *output,
++			      u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 rate_idx = 0;
++	u8 txagc = 0;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++#ifdef PHYDM_COMMON_API_SUPPORT
++	if (!(dm->support_ic_type & CMN_API_SUPPORT_IC))
++		return;
++
++	if (dm->num_rf_path == 1 && path > RF_PATH_A)
++		return;
++	else if (dm->num_rf_path == 2 && path > RF_PATH_B)
++		return;
++	else if (dm->num_rf_path == 3 && path > RF_PATH_C)
++		return;
++	else if (dm->num_rf_path == 4 && path > RF_PATH_D)
++		return;
++
++	for (rate_idx = 0; rate_idx <= 0x53; rate_idx++) {
++		if (!(dm->support_ic_type & PHYDM_IC_ABOVE_3SS) &&
++		    ((rate_idx >= ODM_RATEMCS16 &&
++		    rate_idx < ODM_RATEVHTSS1MCS0) ||
++		    rate_idx >= ODM_RATEVHTSS3MCS0))
++			continue;
++
++		if (rate_idx == ODM_RATE1M)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "  %-35s\n", "CCK====>");
++		else if (rate_idx == ODM_RATE6M)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\n  %-35s\n", "OFDM====>");
++		else if (rate_idx == ODM_RATEMCS0)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\n  %-35s\n", "HT 1ss====>");
++		else if (rate_idx == ODM_RATEMCS8)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\n  %-35s\n", "HT 2ss====>");
++		else if (rate_idx == ODM_RATEMCS16)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\n  %-35s\n", "HT 3ss====>");
++		else if (rate_idx == ODM_RATEMCS24)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\n  %-35s\n", "HT 4ss====>");
++		else if (rate_idx == ODM_RATEVHTSS1MCS0)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\n  %-35s\n", "VHT 1ss====>");
++		else if (rate_idx == ODM_RATEVHTSS2MCS0)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\n  %-35s\n", "VHT 2ss====>");
++		else if (rate_idx == ODM_RATEVHTSS3MCS0)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\n  %-35s\n", "VHT 3ss====>");
++		else if (rate_idx == ODM_RATEVHTSS4MCS0)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\n  %-35s\n", "VHT 4ss====>");
++
++		txagc = phydm_api_get_txagc(dm, (enum rf_path)path, rate_idx);
++		if (config_phydm_read_txagc_check(txagc))
++			PDM_SNPF(out_len, used, output + used,
++				 out_len - used, "  0x%02x    ", txagc);
++		else
++			PDM_SNPF(out_len, used, output + used,
++				 out_len - used, "  0x%s    ", "xx");
++	}
++#endif
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_get_txagc(void *dm_void, u32 *_used, char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 i = 0;
++
++	#if (RTL8822C_SUPPORT)
++	PDM_SNPF(out_len, used, output + used,
++		 out_len - used, "Disabled DPD rate mask: 0x%x\n",
++		 dm->dis_dpd_rate);
++	#endif
++
++	for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
++		if (i == RF_PATH_A)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "%-35s\n", "path-A====================");
++		else if (i == RF_PATH_B)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\n%-35s\n", "path-B====================");
++		else if (i == RF_PATH_C)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\n%-35s\n", "path-C====================");
++		else if (i == RF_PATH_D)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\n%-35s\n", "path-D====================");
++
++		phydm_get_per_path_txagc(dm, i, &used, output, &out_len);
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_set_txagc(void *dm_void, u32 *const val, u32 *_used,
++		     char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 i = 0;
++	u32 pow = 0; /*power index*/
++	u8 vht_start_rate = ODM_RATEVHTSS1MCS0;
++	boolean rpt = true;
++	enum rf_path path = RF_PATH_A;
++
++/*@val[1] = path*/
++/*@val[2] = hw_rate*/
++/*@val[3] = power_index*/
++
++#ifdef PHYDM_COMMON_API_SUPPORT
++	if (!(dm->support_ic_type & CMN_API_SUPPORT_IC))
++		return;
++
++	path = (enum rf_path)val[1];
++
++	if (val[1] >= dm->num_rf_path) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Write path-%d rate_idx-0x%x fail\n", val[1], val[2]);
++	} else if ((u8)val[2] != 0xff) {
++		if (phydm_api_set_txagc(dm, val[3], path, (u8)val[2], true))
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "Write path-%d rate_idx-0x%x = 0x%x\n",
++				 val[1], val[2], val[3]);
++		else
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "Write path-%d rate index-0x%x fail\n",
++				 val[1], val[2]);
++	} else {
++
++		if (dm->support_ic_type &
++		    (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)) {
++			pow = (val[3] & 0x3f);
++			pow = BYTE_DUPLICATE_2_DWORD(pow);
++
++			for (i = 0; i < ODM_RATEVHTSS2MCS9; i += 4)
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
++		} else if (dm->support_ic_type &
++			   (ODM_RTL8197F | ODM_RTL8192F)) {
++			pow = (val[3] & 0x3f);
++			for (i = 0; i <= ODM_RATEMCS15; i++)
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
++		} else if (dm->support_ic_type & ODM_RTL8198F) {
++			pow = (val[3] & 0x7f);
++			for (i = 0; i <= ODM_RATEVHTSS4MCS9; i++)
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
++		} else if (dm->support_ic_type &
++			   (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)) {
++			pow = (val[3] & 0x7f);
++			for (i = 0; i <= ODM_RATEMCS15; i++)
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
++			for (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++)
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
++		} else if (dm->support_ic_type &
++			   (ODM_RTL8721D | ODM_RTL8710C)) {
++			pow = (val[3] & 0x3f);
++			for (i = 0; i <= ODM_RATEMCS7; i++)
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
++		}
++
++		if (rpt)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "Write all TXAGC of path-%d = 0x%x\n",
++				 val[1], val[3]);
++		else
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "Write all TXAGC of path-%d fail\n", val[1]);
++	}
++
++#endif
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_shift_txagc(void *dm_void, u32 *const val, u32 *_used, char *output,
++		       u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 i = 0;
++	u32 pow = 0; /*Power index*/
++	boolean rpt = true;
++	u8 vht_start_rate = ODM_RATEVHTSS1MCS0;
++	enum rf_path path = RF_PATH_A;
++
++#ifdef PHYDM_COMMON_API_SUPPORT
++	if (!(dm->support_ic_type & CMN_API_SUPPORT_IC))
++		return;
++
++	if (val[1] >= dm->num_rf_path) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Write path-%d fail\n", val[1]);
++		return;
++	}
++
++	path = (enum rf_path)val[1];
++
++	if ((u8)val[2] == 0) {
++	/*@{0:-, 1:+} {Pwr Offset}*/
++		if (dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)) {
++			for (i = 0; i <= ODM_RATEMCS7; i++) {
++				pow = phydm_api_get_txagc(dm, path, i) - val[3];
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
++			}
++			for (i = vht_start_rate; i <= ODM_RATEVHTSS1MCS9; i++) {
++				pow = phydm_api_get_txagc(dm, path, i) - val[3];
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
++			}
++		} else if (dm->support_ic_type & (ODM_RTL8822B)) {
++			for (i = 0; i <= ODM_RATEMCS15; i++) {
++				pow = phydm_api_get_txagc(dm, path, i) - val[3];
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
++			}
++			for (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++) {
++				pow = phydm_api_get_txagc(dm, path, i) - val[3];
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
++			}
++		} else if (dm->support_ic_type &
++			   (ODM_RTL8197F | ODM_RTL8192F)) {
++			for (i = 0; i <= ODM_RATEMCS15; i++) {
++				pow = phydm_api_get_txagc(dm, path, i) - val[3];
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
++			}
++		} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++			rpt &= phydm_api_shift_txagc(dm, val[3], path, 0);
++		} else if (dm->support_ic_type &
++			   (ODM_RTL8721D | ODM_RTL8710C)) {
++			for (i = 0; i <= ODM_RATEMCS7; i++) {
++				pow = phydm_api_get_txagc(dm, path, i) - val[3];
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
++			}
++		}
++	} else if ((u8)val[2] == 1) {
++	/*@{0:-, 1:+} {Pwr Offset}*/
++		if (dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)) {
++			for (i = 0; i <= ODM_RATEMCS7; i++) {
++				pow = phydm_api_get_txagc(dm, path, i) + val[3];
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
++			}
++			for (i = vht_start_rate; i <= ODM_RATEVHTSS1MCS9; i++) {
++				pow = phydm_api_get_txagc(dm, path, i) + val[3];
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
++			}
++		} else if (dm->support_ic_type & (ODM_RTL8822B)) {
++			for (i = 0; i <= ODM_RATEMCS15; i++) {
++				pow = phydm_api_get_txagc(dm, path, i) + val[3];
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
++			}
++			for (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++) {
++				pow = phydm_api_get_txagc(dm, path, i) + val[3];
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
++			}
++		} else if (dm->support_ic_type &
++			   (ODM_RTL8197F | ODM_RTL8192F)) {
++			for (i = 0; i <= ODM_RATEMCS15; i++) {
++				pow = phydm_api_get_txagc(dm, path, i) + val[3];
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
++			}
++		} else if (dm->support_ic_type & (ODM_RTL8721D |
++						  ODM_RTL8710C)) {
++			for (i = 0; i <= ODM_RATEMCS7; i++) {
++				pow = phydm_api_get_txagc(dm, path, i) + val[3];
++				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
++			}
++		} else if (dm->support_ic_type &
++			   (ODM_RTL8822C | ODM_RTL8814B |
++			    ODM_RTL8812F | ODM_RTL8197G)) {
++			rpt &= phydm_api_shift_txagc(dm, val[3], path, 1);
++		}
++	}
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[All rate] Set Path-%d Pow_idx: %s %d\n",
++			 val[1], (val[2] ? "+" : "-"), val[3]);
++	else
++	#endif
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[All rate] Set Path-%d Pow_idx: %s %d(%d.%s dB)\n",
++			 val[1], (val[2] ? "+" : "-"), val[3], val[3] >> 1,
++			 ((val[3] & 1) ? "5" : "0"));
++
++#endif
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_set_txagc_dbg(void *dm_void, char input[][16], u32 *_used,
++			 char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 var1[10] = {0};
++	char help[] = "-h";
++	u8 i = 0, input_idx = 0;
++
++	for (i = 0; i < 5; i++) {
++		if (input[i + 1]) {
++			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
++			input_idx++;
++		}
++	}
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{Dis:0, En:1} {pathA~D(0~3)} {rate_idx(Hex), All_rate:0xff} {txagc_idx (Hex)}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{Pwr Shift(All rate):2} {pathA~D(0~3)} {0:-, 1:+} {Pwr Offset(Hex)}\n");
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{reset all rate ref/diff to 0x0:0xff}\n");
++		#endif
++	} else if (var1[0] == 0) {
++		dm->is_disable_phy_api = false;
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Disable API debug mode\n");
++	} else if (var1[0] == 1) {
++		dm->is_disable_phy_api = false;
++		#ifdef CONFIG_TXAGC_DEBUG_8822C
++		config_phydm_write_txagc_8822c(dm, var1[3],
++					       (enum rf_path)var1[1],
++					       (u8)var1[2]);
++		#elif (defined(CONFIG_TXAGC_DEBUG_8814B))
++		config_phydm_write_txagc_8814b(dm, var1[3],
++					       (enum rf_path)var1[1],
++					       (u8)var1[2]);
++		#else
++		phydm_set_txagc(dm, (u32 *)var1, &used, output, &out_len);
++		#endif
++		dm->is_disable_phy_api = true;
++	} else if (var1[0] == 2) {
++		PHYDM_SSCANF(input[4], DCMD_HEX, &var1[3]);
++		dm->is_disable_phy_api = false;
++		phydm_shift_txagc(dm, (u32 *)var1, &used, output, &out_len);
++		dm->is_disable_phy_api = true;
++	}
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	else if (var1[0] == 0xff) {
++		dm->is_disable_phy_api = false;
++		phydm_reset_txagc(dm);
++		dm->is_disable_phy_api = true;
++	}
++	#endif
++	#ifdef CONFIG_TXAGC_DEBUG_8822C
++	else if (var1[0] == 3) {
++		dm->is_disable_phy_api = false;
++		phydm_txagc_tab_buff_show_8822c(dm);
++		dm->is_disable_phy_api = true;
++	} else if (var1[0] == 4) {
++		dm->is_disable_phy_api = false;
++		config_phydm_set_txagc_to_hw_8822c(dm);
++		dm->is_disable_phy_api = true;
++	}
++	#elif (defined(CONFIG_TXAGC_DEBUG_8814B))
++	else if (var1[0] == 3) {
++		dm->is_disable_phy_api = false;
++		phydm_txagc_tab_buff_show_8814b(dm);
++		dm->is_disable_phy_api = true;
++	} else if (var1[0] == 4) {
++		dm->is_disable_phy_api = false;
++		config_phydm_set_txagc_to_hw_8814b(dm);
++		dm->is_disable_phy_api = true;
++	}
++	#endif
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_cmn_msg_setting(void *dm_void, u32 *val, u32 *_used,
++			   char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	if (val[1] == 1) {
++		dm->cmn_dbg_msg_period = (u8)val[2];
++
++		if (dm->cmn_dbg_msg_period < PHYDM_WATCH_DOG_PERIOD)
++			dm->cmn_dbg_msg_period = PHYDM_WATCH_DOG_PERIOD;
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "cmn_dbg_msg_period=%d\n", dm->cmn_dbg_msg_period);
++	}
++
++#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
++	if (val[1] == 1)
++		phydm_physts_auto_switch_jgr3_set(dm, true, BIT(4) | BIT(1));
++	else
++		phydm_physts_auto_switch_jgr3_set(dm, false, BIT(1));
++#endif
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_debug_trace(void *dm_void, char input[][16], u32 *_used,
++		       char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u64 pre_debug_components, one = 1;
++	u64 comp = 0;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 val[10] = {0};
++	u8 i = 0;
++
++	for (i = 0; i < 5; i++) {
++		if (input[i + 1])
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
++	}
++	comp = dm->debug_components;
++	pre_debug_components = dm->debug_components;
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "\n================================\n");
++	if (val[0] == 100) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[DBG MSG] Component Selection\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "================================\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "00. (( %s ))DIG\n",
++			 ((comp & DBG_DIG) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "01. (( %s ))RA_MASK\n",
++			 ((comp & DBG_RA_MASK) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "02. (( %s ))DYN_TXPWR\n",
++			 ((comp & DBG_DYN_TXPWR) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "03. (( %s ))FA_CNT\n",
++			 ((comp & DBG_FA_CNT) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "04. (( %s ))RSSI_MNTR\n",
++			 ((comp & DBG_RSSI_MNTR) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "05. (( %s ))CCKPD\n",
++			 ((comp & DBG_CCKPD) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "06. (( %s ))ANT_DIV\n",
++			 ((comp & DBG_ANT_DIV) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "07. (( %s ))SMT_ANT\n",
++			 ((comp & DBG_SMT_ANT) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "08. (( %s ))PWR_TRAIN\n",
++			 ((comp & DBG_PWR_TRAIN) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "09. (( %s ))RA\n",
++			 ((comp & DBG_RA) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "10. (( %s ))PATH_DIV\n",
++			 ((comp & DBG_PATH_DIV) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "11. (( %s ))DFS\n",
++			 ((comp & DBG_DFS) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "12. (( %s ))DYN_ARFR\n",
++			 ((comp & DBG_DYN_ARFR) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "13. (( %s ))ADAPTIVITY\n",
++			 ((comp & DBG_ADPTVTY) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "14. (( %s ))CFO_TRK\n",
++			 ((comp & DBG_CFO_TRK) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "15. (( %s ))ENV_MNTR\n",
++			 ((comp & DBG_ENV_MNTR) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "16. (( %s ))PRI_CCA\n",
++			 ((comp & DBG_PRI_CCA) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "17. (( %s ))ADPTV_SOML\n",
++			 ((comp & DBG_ADPTV_SOML) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "18. (( %s ))LNA_SAT_CHK\n",
++			 ((comp & DBG_LNA_SAT_CHK) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "20. (( %s ))PHY_STATUS\n",
++			 ((comp & DBG_PHY_STATUS) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "21. (( %s ))TMP\n",
++			 ((comp & DBG_TMP) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "22. (( %s ))FW_DBG_TRACE\n",
++			 ((comp & DBG_FW_TRACE) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "23. (( %s ))TXBF\n",
++			 ((comp & DBG_TXBF) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "24. (( %s ))COMMON_FLOW\n",
++			 ((comp & DBG_COMMON_FLOW) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "28. (( %s ))PHY_CONFIG\n",
++			 ((comp & ODM_PHY_CONFIG) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "29. (( %s ))INIT\n",
++			 ((comp & ODM_COMP_INIT) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "30. (( %s ))COMMON\n",
++			 ((comp & DBG_CMN) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "31. (( %s ))API\n",
++			 ((comp & ODM_COMP_API) ? ("V") : (".")));
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "================================\n");
++
++	} else if (val[0] == 101) {
++		dm->debug_components = 0;
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Disable all debug components\n");
++	} else {
++		if (val[1] == 1) /*@enable*/
++			dm->debug_components |= (one << val[0]);
++		else if (val[1] == 2) /*@disable*/
++			dm->debug_components &= ~(one << val[0]);
++		else
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[Warning]  1:on,  2:off\n");
++
++		if ((BIT(val[0]) == DBG_PHY_STATUS) && val[1] == 1) {
++			dm->phy_dbg_info.show_phy_sts_all_pkt = (u8)val[2];
++			dm->phy_dbg_info.show_phy_sts_max_cnt = (u16)val[3];
++
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "show_all_pkt=%d, show_max_num=%d\n\n",
++				 dm->phy_dbg_info.show_phy_sts_all_pkt,
++				 dm->phy_dbg_info.show_phy_sts_max_cnt);
++
++		} else if (BIT(val[0]) == DBG_CMN) {
++			phydm_cmn_msg_setting(dm, val, &used, output, &out_len);
++		}
++	}
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "pre-DbgComponents = 0x%llx\n", pre_debug_components);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "Curr-DbgComponents = 0x%llx\n", dm->debug_components);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "================================\n");
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_fw_debug_trace(void *dm_void, char input[][16], u32 *_used,
++			  char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 val[10] = {0};
++	u8 i, input_idx = 0;
++	char help[] = "-h";
++	u32 pre_fw_debug_components = 0, one = 1;
++	u32 comp = 0;
++
++	for (i = 0; i < 5; i++) {
++		if (input[i + 1]) {
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
++			input_idx++;
++		}
++	}
++
++	if (input_idx == 0)
++		return;
++
++	pre_fw_debug_components = dm->fw_debug_components;
++	comp = dm->fw_debug_components;
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "{dbg_comp} {1:en, 2:dis} {mode} {macid}\n");
++	} else {
++		if (val[0] == 101) {
++			dm->fw_debug_components = 0;
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "%s\n", "Clear all fw debug components");
++		} else {
++			if (val[1] == 1) /*@enable*/
++				dm->fw_debug_components |= (one << val[0]);
++			else if (val[1] == 2) /*@disable*/
++				dm->fw_debug_components &= ~(one << val[0]);
++			else
++				PDM_SNPF(out_len, used, output + used,
++					 out_len - used, "%s\n",
++					 "[Warning!!!]  1:enable,  2:disable");
++		}
++
++		comp = dm->fw_debug_components;
++
++		if (comp == 0) {
++			dm->debug_components &= ~DBG_FW_TRACE;
++			/*@H2C to enable C2H Msg*/
++			phydm_fw_trace_en_h2c(dm, false, comp, val[2], val[3]);
++		} else {
++			dm->debug_components |= DBG_FW_TRACE;
++			/*@H2C to enable C2H Msg*/
++			phydm_fw_trace_en_h2c(dm, true, comp, val[2], val[3]);
++		}
++	}
++}
++
++#if (ODM_IC_11N_SERIES_SUPPORT)
++void phydm_dump_bb_reg_n(void *dm_void, u32 *_used, char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 addr = 0;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	/*@For Nseries IC we only need to dump page8 to pageF using 3 digits*/
++	for (addr = 0x800; addr < 0xfff; addr += 4) {
++		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++			      "0x%03x 0x%08x\n",
++			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++#endif
++
++#if (ODM_IC_11AC_SERIES_SUPPORT)
++void phydm_dump_bb_reg_ac(void *dm_void, u32 *_used, char *output,
++			  u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 addr = 0;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	for (addr = 0x800; addr < 0xfff; addr += 4) {
++		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++			      "0x%04x 0x%08x\n",
++			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
++	}
++
++	if (!(dm->support_ic_type &
++	    (ODM_RTL8822B | ODM_RTL8814A | ODM_RTL8821C | ODM_RTL8195B)))
++		goto rpt_reg;
++
++	if (dm->rf_type > RF_2T2R) {
++		for (addr = 0x1800; addr < 0x18ff; addr += 4)
++			PDM_VAST_SNPF(out_len, used, output + used,
++				      out_len - used, "0x%04x 0x%08x\n",
++				      addr,
++				      odm_get_bb_reg(dm, addr, MASKDWORD));
++	}
++
++	if (dm->rf_type > RF_3T3R) {
++		for (addr = 0x1a00; addr < 0x1aff; addr += 4)
++			PDM_VAST_SNPF(out_len, used, output + used,
++				      out_len - used, "0x%04x 0x%08x\n",
++				      addr,
++				      odm_get_bb_reg(dm, addr, MASKDWORD));
++	}
++
++	for (addr = 0x1900; addr < 0x19ff; addr += 4)
++		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++			      "0x%04x 0x%08x\n",
++			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
++
++	for (addr = 0x1c00; addr < 0x1cff; addr += 4)
++		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++			      "0x%04x 0x%08x\n",
++			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
++
++	for (addr = 0x1f00; addr < 0x1fff; addr += 4)
++		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++			      "0x%04x 0x%08x\n",
++			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
++
++rpt_reg:
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++#endif
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++void phydm_dump_bb_reg_jgr3(void *dm_void, u32 *_used, char *output,
++			    u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 addr = 0;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		for (addr = 0x800; addr < 0xdff; addr += 4)
++			PDM_VAST_SNPF(out_len, used, output + used,
++				      out_len - used, "0x%04x 0x%08x\n", addr,
++				      odm_get_bb_reg(dm, addr, MASKDWORD));
++
++		for (addr = 0x1800; addr < 0x1aff; addr += 4)
++			PDM_VAST_SNPF(out_len, used, output + used,
++				      out_len - used, "0x%04x 0x%08x\n", addr,
++				      odm_get_bb_reg(dm, addr, MASKDWORD));
++
++		for (addr = 0x1c00; addr < 0x1eff; addr += 4)
++			PDM_VAST_SNPF(out_len, used, output + used,
++				      out_len - used, "0x%04x 0x%08x\n", addr,
++				      odm_get_bb_reg(dm, addr, MASKDWORD));
++
++		for (addr = 0x4000; addr < 0x41ff; addr += 4)
++			PDM_VAST_SNPF(out_len, used, output + used,
++				      out_len - used, "0x%04x 0x%08x\n", addr,
++				      odm_get_bb_reg(dm, addr, MASKDWORD));
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_dump_bb_reg2_jgr3(void *dm_void, u32 *_used, char *output,
++			     u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 addr = 0;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
++		return;
++
++	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
++		for (addr = 0x5000; addr < 0x53ff; addr += 4) {
++			PDM_VAST_SNPF(out_len, used, output + used,
++				      out_len - used, "0x%04x 0x%08x\n",
++				      addr,
++				      odm_get_bb_reg(dm, addr, MASKDWORD));
++		}
++	}
++	#endif
++	/* @Do not change the order of page-2C/2D*/
++	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++		      "------ BB report-register start ------\n");
++	for (addr = 0x2c00; addr < 0x2dff; addr += 4) {
++		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++			      "0x%04x 0x%08x\n",
++			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_get_per_path_anapar_jgr3(void *dm_void, u8 path, u32 *_used,
++				    char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 state = 0;
++	u8 state_bp = 0;
++	u32 control_bb = 0;
++	u32 control_pow = 0;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 reg_idx = 0;
++	u32 dbgport_idx = 0;
++	u32 dbgport_val = 0;
++
++	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++		      "path-%d:\n", path);
++
++	if (path == RF_PATH_A) {
++		reg_idx = R_0x1830;
++		dbgport_idx = 0x9F0;
++	} else if (path == RF_PATH_B) {
++		reg_idx = R_0x4130;
++		dbgport_idx = 0xBF0;
++	} else if (path == RF_PATH_C) {
++		reg_idx = R_0x5230;
++		dbgport_idx = 0xDF0;
++	} else if (path == RF_PATH_D) {
++		reg_idx = R_0x5330;
++		dbgport_idx = 0xFF0;
++	}
++
++	state_bp = (u8)odm_get_bb_reg(dm, reg_idx, 0xf00000);
++	odm_set_bb_reg(dm, reg_idx, 0x38000000, 0x5); /* @read en*/
++
++	for (state = 0; state <= 0xf; state++) {
++		odm_set_bb_reg(dm, reg_idx, 0xF00000, state);
++		if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbgport_idx)) {
++			dbgport_val = phydm_get_bb_dbg_port_val(dm);
++			phydm_release_bb_dbg_port(dm);
++		} else {
++			PDM_VAST_SNPF(out_len, used, output + used,
++				      out_len - used,
++				      "state:0x%x = read dbg_port error!\n",
++				      state);
++		}
++		control_bb = (dbgport_val & 0xFFFF0) >> 4;
++		control_pow = dbgport_val & 0xF;
++		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++			      "state:0x%x = control_bb:0x%x pow_bb:0x%x\n",
++			      state, control_bb, control_pow);
++	}
++	odm_set_bb_reg(dm, reg_idx, 0xf00000, state_bp);
++	odm_set_bb_reg(dm, reg_idx, 0x38000000, 0x6); /* @write en*/
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++#endif
++
++void phydm_dump_bb_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++		      "BB==========\n");
++	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++		      "------ BB control register start ------\n");
++
++	switch (dm->ic_ip_series) {
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	case PHYDM_IC_JGR3:
++		phydm_dump_bb_reg_jgr3(dm, &used, output, &out_len);
++		break;
++	#endif
++
++	#if (ODM_IC_11AC_SERIES_SUPPORT)
++	case PHYDM_IC_AC:
++		phydm_dump_bb_reg_ac(dm, &used, output, &out_len);
++		break;
++	#endif
++
++	#if (ODM_IC_11N_SERIES_SUPPORT)
++	case PHYDM_IC_N:
++		phydm_dump_bb_reg_n(dm, &used, output, &out_len);
++		break;
++	#endif
++
++	default:
++		break;
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_dump_rf_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 addr = 0;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 reg = 0;
++
++	/* @dump RF register */
++	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++		      "RF-A==========\n");
++
++	for (addr = 0; addr <= 0xFF; addr++) {
++		reg = odm_get_rf_reg(dm, RF_PATH_A, addr, RFREG_MASK);
++		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++			      "0x%02x 0x%05x\n", addr, reg);
++		}
++
++#ifdef PHYDM_COMPILE_ABOVE_2SS
++	if (dm->rf_type > RF_1T1R) {
++		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++			      "RF-B==========\n");
++
++		for (addr = 0; addr <= 0xFF; addr++) {
++			reg = odm_get_rf_reg(dm, RF_PATH_B, addr, RFREG_MASK);
++			PDM_VAST_SNPF(out_len, used, output + used,
++				      out_len - used, "0x%02x 0x%05x\n",
++				      addr, reg);
++		}
++	}
++#endif
++
++#ifdef PHYDM_COMPILE_ABOVE_3SS
++	if (dm->rf_type > RF_2T2R) {
++		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++			      "RF-C==========\n");
++
++		for (addr = 0; addr <= 0xFF; addr++) {
++			reg = odm_get_rf_reg(dm, RF_PATH_C, addr, RFREG_MASK);
++			PDM_VAST_SNPF(out_len, used, output + used,
++				      out_len - used, "0x%02x 0x%05x\n",
++				      addr, reg);
++		}
++	}
++#endif
++
++#ifdef PHYDM_COMPILE_ABOVE_4SS
++	if (dm->rf_type > RF_3T3R) {
++		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++			      "RF-D==========\n");
++
++		for (addr = 0; addr <= 0xFF; addr++) {
++			reg = odm_get_rf_reg(dm, RF_PATH_D, addr, RFREG_MASK);
++			PDM_VAST_SNPF(out_len, used, output + used,
++				      out_len - used, "0x%02x 0x%05x\n",
++				      addr, reg);
++		}
++	}
++#endif
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_dump_mac_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 addr = 0;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	/* @dump MAC register */
++	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++		      "MAC==========\n");
++
++	for (addr = 0; addr < 0x7ff; addr += 4)
++		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++			      "0x%04x 0x%08x\n",
++			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
++
++	for (addr = 0x1000; addr < 0x17ff; addr += 4)
++		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++			      "0x%04x 0x%08x\n",
++			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_dump_reg(void *dm_void, char input[][16], u32 *_used, char *output,
++		    u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 addr = 0;
++
++	if (input[1])
++		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
++
++	if ((strcmp(input[1], help) == 0)) {
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "dumpreg {0:all, 1:BB, 2:RF, 3:MAC 4:BB2 for jgr3}\n");
++		else
++		#endif
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "dumpreg {0:all, 1:BB, 2:RF, 3:MAC}\n");
++	} else if (var1[0] == 0) {
++		phydm_dump_mac_reg(dm, &used, output, &out_len);
++		phydm_dump_bb_reg(dm, &used, output, &out_len);
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		if (dm->ic_ip_series == PHYDM_IC_JGR3)
++			phydm_dump_bb_reg2_jgr3(dm, &used, output, &out_len);
++		#endif
++
++		phydm_dump_rf_reg(dm, &used, output, &out_len);
++	} else if (var1[0] == 1) {
++		phydm_dump_bb_reg(dm, &used, output, &out_len);
++	} else if (var1[0] == 2) {
++		phydm_dump_rf_reg(dm, &used, output, &out_len);
++	} else if (var1[0] == 3) {
++		phydm_dump_mac_reg(dm, &used, output, &out_len);
++	} else if (var1[0] == 4) {
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		if (dm->ic_ip_series == PHYDM_IC_JGR3)
++			phydm_dump_bb_reg2_jgr3(dm, &used, output, &out_len);
++		#endif
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_enable_big_jump(void *dm_void, char input[][16], u32 *_used,
++			   char *output, u32 *_out_len)
++{
++#if (RTL8822B_SUPPORT)
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	u32 dm_value[10] = {0};
++	u8 i, input_idx = 0;
++	u32 val;
++
++	if (!(dm->support_ic_type & ODM_RTL8822B))
++		return;
++
++	for (i = 0; i < 5; i++) {
++		if (input[i + 1]) {
++			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
++			input_idx++;
++		}
++	}
++
++	if (input_idx == 0)
++		return;
++
++	if (dm_value[0] == 0) {
++		dm->dm_dig_table.enable_adjust_big_jump = false;
++
++		val = (dig_t->big_jump_step3 << 5) |
++		      (dig_t->big_jump_step2 << 3) |
++		      dig_t->big_jump_step1;
++
++		odm_set_bb_reg(dm, R_0x8c8, 0xfe, val);
++	} else {
++		dm->dm_dig_table.enable_adjust_big_jump = true;
++	}
++#endif
++}
++
++void phydm_show_rx_rate(void *dm_void, char input[][16], u32 *_used,
++			char *output, u32 *_out_len)
++{
++#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8814B_SUPPORT ||\
++	RTL8195B_SUPPORT || RTL8822C_SUPPORT)
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 var1[10] = {0};
++	char help[] = "-h";
++	u8 i, input_idx = 0;
++
++	for (i = 0; i < 5; i++) {
++		if (input[i + 1]) {
++			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
++			input_idx++;
++		}
++	}
++
++	if (input_idx == 0)
++		return;
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{1: show Rx rate, 0:reset counter}\n");
++		*_used = used;
++		*_out_len = out_len;
++		return;
++
++	} else if (var1[0] == 0) {
++		phydm_reset_rx_rate_distribution(dm);
++		*_used = used;
++		*_out_len = out_len;
++		return;
++	}
++
++	/* @==Show SU Rate====================================================*/
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "=====Rx SU rate Statistics=====\n");
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "[SU][1SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n",
++		 dbg->num_qry_vht_pkt[0], dbg->num_qry_vht_pkt[1],
++		 dbg->num_qry_vht_pkt[2], dbg->num_qry_vht_pkt[3],
++		 dbg->num_qry_vht_pkt[4], dbg->num_qry_vht_pkt[5],
++		 dbg->num_qry_vht_pkt[6], dbg->num_qry_vht_pkt[7],
++		 dbg->num_qry_vht_pkt[8], dbg->num_qry_vht_pkt[9]);
++
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	if (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[SU][2SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n",
++			 dbg->num_qry_vht_pkt[10], dbg->num_qry_vht_pkt[11],
++			 dbg->num_qry_vht_pkt[12], dbg->num_qry_vht_pkt[13],
++			 dbg->num_qry_vht_pkt[14], dbg->num_qry_vht_pkt[15],
++			 dbg->num_qry_vht_pkt[16], dbg->num_qry_vht_pkt[17],
++			 dbg->num_qry_vht_pkt[18], dbg->num_qry_vht_pkt[19]);
++	}
++	#endif
++	/* @==Show MU Rate====================================================*/
++#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) || (defined(PHYSTS_3RD_TYPE_SUPPORT))
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "=====Rx MU rate Statistics=====\n");
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "[MU][1SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n",
++		 dbg->num_mu_vht_pkt[0], dbg->num_mu_vht_pkt[1],
++		 dbg->num_mu_vht_pkt[2], dbg->num_mu_vht_pkt[3],
++		 dbg->num_mu_vht_pkt[4], dbg->num_mu_vht_pkt[5],
++		 dbg->num_mu_vht_pkt[6], dbg->num_mu_vht_pkt[7],
++		 dbg->num_mu_vht_pkt[8], dbg->num_mu_vht_pkt[9]);
++
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	if (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[MU][2SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n",
++			 dbg->num_mu_vht_pkt[10], dbg->num_mu_vht_pkt[11],
++			 dbg->num_mu_vht_pkt[12], dbg->num_mu_vht_pkt[13],
++			 dbg->num_mu_vht_pkt[14], dbg->num_mu_vht_pkt[15],
++			 dbg->num_mu_vht_pkt[16], dbg->num_mu_vht_pkt[17],
++			 dbg->num_mu_vht_pkt[18], dbg->num_mu_vht_pkt[19]);
++	}
++	#endif
++#endif
++	*_used = used;
++	*_out_len = out_len;
++#endif
++}
++
++void phydm_per_tone_evm(void *dm_void, char input[][16], u32 *_used,
++			char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i, j;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 var1[4] = {0};
++	u32 val, tone_num, round;
++	s8 rxevm_0, rxevm_1;
++	s32 avg_num, evm_tone_0[256] = {0}, evm_tone_1[256] = {0};
++	s32 rxevm_sum_0, rxevm_sum_1;
++
++	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		pr_debug("n series not support yet !\n");
++		return;
++	}
++
++	for (i = 0; i < 4; i++) {
++		if (input[i + 1])
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
++	}
++
++	avg_num = var1[0];
++	round = var1[1];
++
++	if (!dm->is_linked) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "No Link !!\n");
++
++		*_used = used;
++		*_out_len = out_len;
++
++		return;
++	}
++
++	pr_debug("ID=((%d)), BW=((%d)), fc=((CH-%d))\n", dm->curr_station_id,
++		 20 << *dm->band_width, *dm->channel);
++	pr_debug("avg_num =((%d)), round =((%d))\n", avg_num, round);
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	watchdog_stop(dm->priv);
++#endif
++	for (j = 0; j < round; j++) {
++		pr_debug("\nround((%d))\n", (j + 1));
++		if (*dm->band_width == CHANNEL_WIDTH_20) {
++			for (tone_num = 228; tone_num <= 255; tone_num++) {
++				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
++				rxevm_sum_0 = 0;
++				rxevm_sum_1 = 0;
++				for (i = 0; i < avg_num; i++) {
++					val = odm_read_4byte(dm, R_0xf8c);
++
++					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
++					rxevm_0 = (rxevm_0 / 2);
++					if (rxevm_0 < -63)
++						rxevm_0 = 0;
++
++					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
++					rxevm_1 = (rxevm_1 / 2);
++					if (rxevm_1 < -63)
++						rxevm_1 = 0;
++					rxevm_sum_0 += rxevm_0;
++					rxevm_sum_1 += rxevm_1;
++					ODM_delay_ms(1);
++				}
++				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
++				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
++				pr_debug("Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\n",
++					 (256 - tone_num), evm_tone_0[tone_num],
++					 evm_tone_1[tone_num]);
++			}
++
++			for (tone_num = 1; tone_num <= 28; tone_num++) {
++				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
++				rxevm_sum_0 = 0;
++				rxevm_sum_1 = 0;
++				for (i = 0; i < avg_num; i++) {
++					val = odm_read_4byte(dm, R_0xf8c);
++
++					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
++					rxevm_0 = (rxevm_0 / 2);
++					if (rxevm_0 < -63)
++						rxevm_0 = 0;
++
++					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
++					rxevm_1 = (rxevm_1 / 2);
++					if (rxevm_1 < -63)
++						rxevm_1 = 0;
++					rxevm_sum_0 += rxevm_0;
++					rxevm_sum_1 += rxevm_1;
++					ODM_delay_ms(1);
++				}
++				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
++				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
++				pr_debug("Tone(%-3d) RXEVM(1ss/2ss)=%d, %d\n",
++					 tone_num, evm_tone_0[tone_num],
++					 evm_tone_1[tone_num]);
++			}
++		} else if (*dm->band_width == CHANNEL_WIDTH_40) {
++			for (tone_num = 198; tone_num <= 254; tone_num++) {
++				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
++				rxevm_sum_0 = 0;
++				rxevm_sum_1 = 0;
++				for (i = 0; i < avg_num; i++) {
++					val = odm_read_4byte(dm, R_0xf8c);
++
++					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
++					rxevm_0 = (rxevm_0 / 2);
++					if (rxevm_0 < -63)
++						rxevm_0 = 0;
++
++					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
++					rxevm_1 = (rxevm_1 / 2);
++					if (rxevm_1 < -63)
++						rxevm_1 = 0;
++
++					rxevm_sum_0 += rxevm_0;
++					rxevm_sum_1 += rxevm_1;
++					ODM_delay_ms(1);
++				}
++				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
++				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
++				pr_debug("Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\n",
++					 (256 - tone_num), evm_tone_0[tone_num],
++					 evm_tone_1[tone_num]);
++			}
++
++			for (tone_num = 2; tone_num <= 58; tone_num++) {
++				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
++				rxevm_sum_0 = 0;
++				rxevm_sum_1 = 0;
++				for (i = 0; i < avg_num; i++) {
++					val = odm_read_4byte(dm, R_0xf8c);
++
++					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
++					rxevm_0 = (rxevm_0 / 2);
++					if (rxevm_0 < -63)
++						rxevm_0 = 0;
++
++					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
++					rxevm_1 = (rxevm_1 / 2);
++					if (rxevm_1 < -63)
++						rxevm_1 = 0;
++					rxevm_sum_0 += rxevm_0;
++					rxevm_sum_1 += rxevm_1;
++					ODM_delay_ms(1);
++				}
++				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
++				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
++				pr_debug("Tone(%-3d) RXEVM(1ss/2ss)=%d, %d\n",
++					 tone_num, evm_tone_0[tone_num],
++					 evm_tone_1[tone_num]);
++			}
++		} else if (*dm->band_width == CHANNEL_WIDTH_80) {
++			for (tone_num = 134; tone_num <= 254; tone_num++) {
++				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
++				rxevm_sum_0 = 0;
++				rxevm_sum_1 = 0;
++				for (i = 0; i < avg_num; i++) {
++					val = odm_read_4byte(dm, R_0xf8c);
++
++					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
++					rxevm_0 = (rxevm_0 / 2);
++					if (rxevm_0 < -63)
++						rxevm_0 = 0;
++
++					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
++					rxevm_1 = (rxevm_1 / 2);
++					if (rxevm_1 < -63)
++						rxevm_1 = 0;
++					rxevm_sum_0 += rxevm_0;
++					rxevm_sum_1 += rxevm_1;
++					ODM_delay_ms(1);
++				}
++				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
++				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
++				pr_debug("Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\n",
++					 (256 - tone_num), evm_tone_0[tone_num],
++					 evm_tone_1[tone_num]);
++			}
++
++			for (tone_num = 2; tone_num <= 122; tone_num++) {
++				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
++				rxevm_sum_0 = 0;
++				rxevm_sum_1 = 0;
++				for (i = 0; i < avg_num; i++) {
++					val = odm_read_4byte(dm, R_0xf8c);
++
++					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
++					rxevm_0 = (rxevm_0 / 2);
++					if (rxevm_0 < -63)
++						rxevm_0 = 0;
++
++					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
++					rxevm_1 = (rxevm_1 / 2);
++					if (rxevm_1 < -63)
++						rxevm_1 = 0;
++					rxevm_sum_0 += rxevm_0;
++					rxevm_sum_1 += rxevm_1;
++					ODM_delay_ms(1);
++				}
++				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
++				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
++				pr_debug("Tone(%-3d) RXEVM (1ss/2ss)=%d, %d\n",
++					 tone_num, evm_tone_0[tone_num],
++					 evm_tone_1[tone_num]);
++			}
++		}
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_bw_ch_adjust(void *dm_void, char input[][16],
++			u32 *_used, char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 i;
++	boolean is_enable_dbg_mode;
++	u8 central_ch, primary_ch_idx;
++	enum channel_width bw;
++
++#ifdef PHYDM_COMMON_API_SUPPORT
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{en} {CH} {pr_ch_idx 1/2/3/4/9/10} {0:20M,1:40M,2:80M}\n");
++		goto out;
++	}
++
++	if (!(dm->support_ic_type & CMN_API_SUPPORT_IC)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Not support this API\n");
++		goto out;
++	}
++
++	for (i = 0; i < 4; i++) {
++		if (input[i + 1])
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
++	}
++
++	is_enable_dbg_mode = (boolean)var1[0];
++	central_ch = (u8)var1[1];
++	primary_ch_idx = (u8)var1[2];
++	bw = (enum channel_width)var1[3];
++
++	if (is_enable_dbg_mode) {
++		dm->is_disable_phy_api = false;
++		phydm_api_switch_bw_channel(dm, central_ch, primary_ch_idx, bw);
++		dm->is_disable_phy_api = true;
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "central_ch = %d, primary_ch_idx = %d, bw = %d\n",
++			 central_ch, primary_ch_idx, bw);
++	}
++out:
++#endif
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_ext_rf_element_ctrl(void *dm_void, char input[][16], u32 *_used,
++			       char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 val[10] = {0};
++	u8 i = 0, input_idx = 0;
++
++	for (i = 0; i < 5; i++) {
++		if (input[i + 1]) {
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
++			input_idx++;
++		}
++	}
++
++	if (input_idx == 0)
++		return;
++
++	if (val[0] == 1) /*@ext switch*/ {
++		phydm_set_ext_switch(dm, val[1]);
++	}
++}
++
++void phydm_print_dbgport(void *dm_void, char input[][16], u32 *_used,
++			 char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 dbg_port_value = 0;
++	u8 val[32];
++	u8 tmp = 0;
++	u8 i;
++
++	if (strcmp(input[1], help) == 0) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{dbg_port_idx}\n");
++		goto out;
++	}
++
++	PHYDM_SSCANF(input[1], DCMD_HEX, &var1[0]);
++
++	dm->debug_components |= ODM_COMP_API;
++	if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, var1[0])) {
++		dbg_port_value = phydm_get_bb_dbg_port_val(dm);
++		phydm_release_bb_dbg_port(dm);
++
++		for (i = 0; i < 32; i++)
++			val[i] = (u8)((dbg_port_value & BIT(i)) >> i);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Dbg Port[0x%x] = ((0x%x))\n", var1[0],
++			 dbg_port_value);
++
++		for (i = 4; i != 0; i--) {
++			tmp = 8 * (i - 1);
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "val[%d:%d] = 8b'%d %d %d %d %d %d %d %d\n",
++				 tmp + 7, tmp, val[tmp + 7], val[tmp + 6],
++				 val[tmp + 5], val[tmp + 4], val[tmp + 3],
++				 val[tmp + 2], val[tmp + 1], val[tmp + 0]);
++		}
++	}
++	dm->debug_components &= (~ODM_COMP_API);
++out:
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_get_anapar_table(void *dm_void, u32 *_used, char *output,
++			    u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	enum rf_path i = RF_PATH_A;
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
++		return;
++
++	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
++		      "------ Analog parameters start ------\n");
++
++	for (i = RF_PATH_A; i < (enum rf_path)dm->num_rf_path; i++)
++		phydm_get_per_path_anapar_jgr3(dm, i, &used, output, &out_len);
++#endif
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_dd_dbg_dump(void *dm_void, char input[][16], u32 *_used,
++		       char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "dump: {1}\n");
++		return;
++	} else if (var1[0] == 1) {
++		/*[Reg]*/
++		phydm_dump_mac_reg(dm, &used, output, &out_len);
++		phydm_dump_bb_reg(dm, &used, output, &out_len);
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		if (dm->ic_ip_series == PHYDM_IC_JGR3)
++			phydm_dump_bb_reg2_jgr3(dm, &used, output, &out_len);
++		#endif
++
++		phydm_dump_rf_reg(dm, &used, output, &out_len);
++		/*[Dbg Port]*/
++		#ifdef PHYDM_AUTO_DEGBUG
++		phydm_dbg_port_dump(dm, &used, output, &out_len);
++		#endif
++		/*[Analog Parameters]*/
++		phydm_get_anapar_table(dm, &used, output, &out_len);
++	}
++}
++
++void phydm_nss_hitogram_mp(void *dm_void, enum PDM_RATE_TYPE rate_type,
++			   u32 *_used, char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
++	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	char buf[PHYDM_SNPRINT_SIZE] = {0};
++	u16 buf_size = PHYDM_SNPRINT_SIZE;
++	u16 h_size = PHY_HIST_SIZE;
++	u16 *evm_hist = &dbg_s->evm_1ss_hist[0];
++	u16 *snr_hist = &dbg_s->snr_1ss_hist[0];
++	u8 i = 0;
++	u8 ss = phydm_rate_type_2_num_ss(dm, rate_type);
++
++	if (rate_type == PDM_OFDM) {
++		phydm_print_hist_2_buf(dm, dbg_s->evm_ofdm_hist, PHY_HIST_SIZE,
++				       buf, buf_size);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "%-14s=%s\n", "[OFDM][EVM]", buf);
++
++		phydm_print_hist_2_buf(dm, dbg_s->snr_ofdm_hist, PHY_HIST_SIZE,
++				       buf, buf_size);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "%-14s=%s\n", "[OFDM][SNR]", buf);
++
++		*_used = used;
++		*_out_len = out_len;
++		return;
++	}
++
++	for (i = 0; i < ss; i++) {
++		if (rate_type == PDM_1SS) {
++			evm_hist = &dbg_s->evm_1ss_hist[0];
++			snr_hist = &dbg_s->snr_1ss_hist[0];
++		} else if (rate_type == PDM_2SS) {
++			#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++			evm_hist = &dbg_s->evm_2ss_hist[i][0];
++			snr_hist = &dbg_s->snr_2ss_hist[i][0];
++			#endif
++		} else if (rate_type == PDM_3SS) {
++			#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++			evm_hist = &dbg_s->evm_3ss_hist[i][0];
++			snr_hist = &dbg_s->snr_3ss_hist[i][0];
++			#endif
++		} else if (rate_type == PDM_4SS) {
++			#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++			evm_hist = &dbg_s->evm_4ss_hist[i][0];
++			snr_hist = &dbg_s->snr_4ss_hist[i][0];
++			#endif
++		}
++
++		phydm_print_hist_2_buf(dm, evm_hist, h_size, buf, buf_size);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[%d-SS][EVM][%d]=%s\n", ss, i, buf);
++		phydm_print_hist_2_buf(dm, snr_hist, h_size, buf, buf_size);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[%d-SS][SNR][%d]=%s\n",  ss, i, buf);
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_mp_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
++		  u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
++	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
++	struct phydm_phystatus_avg *dbg_avg = &dbg_i->phystatus_statistic_avg;
++	char *rate_type = NULL;
++	u8 tmp_rssi_avg[4];
++	u8 tmp_snr_avg[4];
++	u8 tmp_evm_avg[4];
++	u32 tmp_cnt = 0;
++	char buf[PHYDM_SNPRINT_SIZE] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 var1[10] = {0};
++	u16 buf_size = PHYDM_SNPRINT_SIZE;
++	u16 th_size = PHY_HIST_SIZE - 1;
++	u8 i = 0;
++
++	if (!(*dm->mp_mode))
++		return;
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "BW=((%d)), fc=((CH-%d))\n",
++		 20 << *dm->band_width, *dm->channel);
++
++	/*@===[PHY Histogram]================================================*/
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "[PHY Histogram] ==============>\n");
++	/*@===[Threshold]===*/
++	phydm_print_hist_2_buf(dm, dbg_i->evm_hist_th, th_size, buf, buf_size);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "%-16s=%s\n", "[EVM_TH]", buf);
++	phydm_print_hist_2_buf(dm, dbg_i->snr_hist_th, th_size, buf, buf_size);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "%-16s=%s\n", "[SNR_TH]", buf);
++	/*@===[OFDM]===*/
++	phydm_nss_hitogram_mp(dm, PDM_OFDM, &used, output, &out_len);
++	/*@===[1-SS]===*/
++	phydm_nss_hitogram_mp(dm, PDM_1SS, &used, output, &out_len);
++	/*@===[2-SS]===*/
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
++		phydm_nss_hitogram_mp(dm, PDM_2SS, &used, output, &out_len);
++	#endif
++	/*@===[3-SS]===*/
++	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++	if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS)
++		phydm_nss_hitogram_mp(dm, PDM_3SS, &used, output, &out_len);
++	#endif
++	/*@===[4-SS]===*/
++	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS)
++		phydm_nss_hitogram_mp(dm, PDM_4SS, &used, output, &out_len);
++	#endif
++	/*@===[PHY Avg]======================================================*/
++	phydm_get_avg_phystatus_val(dm);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "[PHY Avg] ==============>\n");
++
++	phydm_get_avg_phystatus_val(dm);
++
++	switch (dm->num_rf_path) {
++#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	case 4:
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n",
++			 "[Beacon]", dbg_s->rssi_beacon_cnt,
++			 dbg_avg->rssi_beacon_avg[0],
++			 dbg_avg->rssi_beacon_avg[1],
++			 dbg_avg->rssi_beacon_avg[2],
++			 dbg_avg->rssi_beacon_avg[3]);
++		break;
++#endif
++#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++	case 3:
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n",
++			 "[Beacon]", dbg_s->rssi_beacon_cnt,
++			 dbg_avg->rssi_beacon_avg[0],
++			 dbg_avg->rssi_beacon_avg[1],
++			 dbg_avg->rssi_beacon_avg[2]);
++		break;
++#endif
++#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	case 2:
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n",
++			 "[Beacon]", dbg_s->rssi_beacon_cnt,
++			 dbg_avg->rssi_beacon_avg[0],
++			 dbg_avg->rssi_beacon_avg[1]);
++		break;
++#endif
++	default:
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n",
++			 "[Beacon]", dbg_s->rssi_beacon_cnt,
++			 dbg_avg->rssi_beacon_avg[0]);
++		break;
++	}
++
++	switch (dm->num_rf_path) {
++#ifdef PHYSTS_3RD_TYPE_SUPPORT
++	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	case 4:
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n",
++			 "[CCK]", dbg_s->rssi_cck_cnt,
++			 dbg_avg->rssi_cck_avg,
++			 dbg_avg->rssi_cck_avg_abv_2ss[0],
++			 dbg_avg->rssi_cck_avg_abv_2ss[1],
++			 dbg_avg->rssi_cck_avg_abv_2ss[2]);
++		break;
++	#endif
++	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++	case 3:
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n",
++			 "[CCK]", dbg_s->rssi_cck_cnt,
++			 dbg_avg->rssi_cck_avg,
++			 dbg_avg->rssi_cck_avg_abv_2ss[0],
++			 dbg_avg->rssi_cck_avg_abv_2ss[1]);
++		break;
++	#endif
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	case 2:
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n",
++			 "[CCK]", dbg_s->rssi_cck_cnt,
++			 dbg_avg->rssi_cck_avg,
++			 dbg_avg->rssi_cck_avg_abv_2ss[0]);
++		break;
++	#endif
++#endif
++	default:
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n",
++			 "[CCK]", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg);
++		break;
++	}
++
++	for (i = 0; i <= 4; i++) {
++		if (i > dm->num_rf_path)
++			break;
++
++		odm_memory_set(dm, tmp_rssi_avg, 0, 4);
++		odm_memory_set(dm, tmp_snr_avg, 0, 4);
++		odm_memory_set(dm, tmp_evm_avg, 0, 4);
++
++		switch (i) {
++		#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++		case 4:
++			rate_type = "[4-SS]";
++			tmp_cnt = dbg_s->rssi_4ss_cnt;
++			odm_move_memory(dm, tmp_rssi_avg,
++					dbg_avg->rssi_4ss_avg, dm->num_rf_path);
++			odm_move_memory(dm, tmp_snr_avg,
++					dbg_avg->snr_4ss_avg, dm->num_rf_path);
++			odm_move_memory(dm, tmp_evm_avg, dbg_avg->evm_4ss_avg,
++					4);
++			break;
++		#endif
++		#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++		case 3:
++			rate_type = "[3-SS]";
++			tmp_cnt = dbg_s->rssi_3ss_cnt;
++			odm_move_memory(dm, tmp_rssi_avg,
++					dbg_avg->rssi_3ss_avg, dm->num_rf_path);
++			odm_move_memory(dm, tmp_snr_avg,
++					dbg_avg->snr_3ss_avg, dm->num_rf_path);
++			odm_move_memory(dm, tmp_evm_avg,
++					dbg_avg->evm_3ss_avg, 3);
++			break;
++		#endif
++		#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++		case 2:
++			rate_type = "[2-SS]";
++			tmp_cnt = dbg_s->rssi_2ss_cnt;
++			odm_move_memory(dm, tmp_rssi_avg,
++					dbg_avg->rssi_2ss_avg, dm->num_rf_path);
++			odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_2ss_avg,
++					dm->num_rf_path);
++			odm_move_memory(dm, tmp_evm_avg,
++					dbg_avg->evm_2ss_avg, 2);
++			break;
++		#endif
++		case 1:
++			rate_type = "[1-SS]";
++			tmp_cnt = dbg_s->rssi_1ss_cnt;
++			odm_move_memory(dm, tmp_rssi_avg,
++					dbg_avg->rssi_1ss_avg, dm->num_rf_path);
++			odm_move_memory(dm, tmp_snr_avg,
++					dbg_avg->snr_1ss_avg, dm->num_rf_path);
++			odm_move_memory(dm, tmp_evm_avg,
++					&dbg_avg->evm_1ss_avg, 1);
++			break;
++		default:
++			rate_type = "[L-OFDM]";
++			tmp_cnt = dbg_s->rssi_ofdm_cnt;
++			odm_move_memory(dm, tmp_rssi_avg,
++					dbg_avg->rssi_ofdm_avg,
++					dm->num_rf_path);
++			odm_move_memory(dm, tmp_snr_avg,
++					dbg_avg->snr_ofdm_avg, dm->num_rf_path);
++			odm_move_memory(dm, tmp_evm_avg,
++					&dbg_avg->evm_ofdm_avg, 1);
++			break;
++		}
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			   "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d} SNR:{%.2d, %.2d, %.2d, %.2d} EVM:{-%.2d, -%.2d, -%.2d, -%.2d}\n",
++			    rate_type, tmp_cnt,
++			    tmp_rssi_avg[0], tmp_rssi_avg[1],
++			    tmp_rssi_avg[2], tmp_rssi_avg[3],
++			    tmp_snr_avg[0], tmp_snr_avg[1],
++			    tmp_snr_avg[2], tmp_snr_avg[3],
++			    tmp_evm_avg[0], tmp_evm_avg[1],
++			    tmp_evm_avg[2], tmp_evm_avg[3]);
++	}
++
++	phydm_reset_phystatus_statistic(dm);
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "rxsc_idx {Legacy, 20, 40, 80} = {%d, %d, %d, %d}\n",
++		 dm->rxsc_l, dm->rxsc_20, dm->rxsc_40, dm->rxsc_80);
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_reg_monitor(void *dm_void, char input[][16], u32 *_used,
++		       char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	boolean en_mntr = false;
++	u8 i = 0;
++
++	for (i = 0; i < 7; i++) {
++		if (input[i + 1])
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
++	}
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "reg_mntr {en} {0:all, 1:BB, 2:RF, 3:MAC 4:1/2/4 byte}\n");
++	} else {
++		if (var1[0] == 1)
++			en_mntr = true;
++		else
++			en_mntr = false;
++
++		if (var1[1] == 0) {
++			dm->en_reg_mntr_bb = en_mntr;
++			dm->en_reg_mntr_rf = en_mntr;
++			dm->en_reg_mntr_mac = en_mntr;
++			dm->en_reg_mntr_byte = en_mntr;
++		} else if (var1[1] == 1) {
++			dm->en_reg_mntr_bb = en_mntr;
++		} else if (var1[1] == 2) {
++			dm->en_reg_mntr_rf = en_mntr;
++		} else if (var1[1] == 3) {
++			dm->en_reg_mntr_mac = en_mntr;
++		} else if (var1[1] == 4) {
++			dm->en_reg_mntr_byte = en_mntr;
++		}
++	}
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "en: BB:%d, RF:%d, MAC:%d, byte:%d\n", dm->en_reg_mntr_bb,
++		 dm->en_reg_mntr_rf, dm->en_reg_mntr_mac, dm->en_reg_mntr_byte);
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++#if RTL8814B_SUPPORT
++void phydm_spur_detect_dbg(void *dm_void, char input[][16], u32 *_used,
++			   char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 i;
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{0: Auto spur detect(NBI+CSI), 1:NBI always ON/ CSI Auto,");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "2: CSI always On/ NBI Auto, 3: Disable, 4: CSI & NBI ON}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{If CSI always ON (Mode 2 or 4) -> CSI wgt manual(0~7)}\n");
++	} else {
++		for (i = 0; i < 10; i++) {
++			if (input[i + 1])
++				PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
++		}
++
++		if (var1[0] == 1) {
++			dm->dsde_sel = DET_NBI;
++		} else if (var1[0] == 2) {
++			dm->dsde_sel = DET_CSI;
++		} else if (var1[0] == 3) {
++			dm->dsde_sel = DET_DISABLE;
++		} else if (var1[0] == 4) {
++			dm->dsde_sel = DET_CSI_NBI_EN;
++		} else if (var1[0] == 0) {
++			dm->dsde_sel = DET_AUTO;
++		} else {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "Spur detection mode invalid!\n");
++			return;
++		}
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "spur detect mode = %d\n", dm->dsde_sel);
++
++		if (dm->dsde_sel == DET_CSI_NBI_EN) {
++			if (var1[1] < 8) {
++				dm->csi_wgt = (u8)var1[1];
++				PDM_SNPF(out_len, used, output + used,
++					 out_len - used, "CSI wgt %d\n",
++					 dm->csi_wgt);
++			} else {
++				PDM_SNPF(out_len, used, output + used,
++					 out_len - used,
++					 "CSI wgt setting invalid. Please set the correct wgt!\n");
++				return;
++			}
++		}
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++#endif
++
++struct phydm_command {
++	char name[16];
++	u8 id;
++};
++
++enum PHYDM_CMD_ID {
++	PHYDM_HELP,
++	PHYDM_DEMO,
++	PHYDM_RF_CMD,
++	PHYDM_DIG,
++	PHYDM_RA,
++	PHYDM_PROFILE,
++	PHYDM_ANTDIV,
++	PHYDM_PATHDIV,
++	PHYDM_DEBUG,
++	PHYDM_MP_DEBUG,
++	PHYDM_FW_DEBUG,
++	PHYDM_SUPPORT_ABILITY,
++	PHYDM_GET_TXAGC,
++	PHYDM_SET_TXAGC,
++	PHYDM_SMART_ANT,
++	PHYDM_CH_BW,
++	PHYDM_TRX_PATH,
++	PHYDM_LA_MODE,
++	PHYDM_DUMP_REG,
++	PHYDM_AUTO_DBG,
++	PHYDM_DD_DBG,
++	PHYDM_BIG_JUMP,
++	PHYDM_SHOW_RXRATE,
++	PHYDM_NBI_EN,
++	PHYDM_CSI_MASK_EN,
++	PHYDM_DFS_DEBUG,
++	PHYDM_DFS_HIST,
++	PHYDM_NHM,
++	PHYDM_CLM,
++	PHYDM_FAHM,
++	PHYDM_ENV_MNTR,
++	PHYDM_BB_INFO,
++	//PHYDM_TXBF,
++	PHYDM_H2C,
++	PHYDM_EXT_RF_E_CTRL,
++	PHYDM_ADAPTIVE_SOML,
++	PHYDM_PSD,
++	PHYDM_DEBUG_PORT,
++	PHYDM_DIS_HTSTF_CONTROL,
++	PHYDM_CFO_TRK,
++	PHYDM_ADAPTIVITY_DEBUG,
++	PHYDM_DIS_DYM_ANT_WEIGHTING,
++	PHYDM_FORECE_PT_STATE,
++	PHYDM_STA_INFO,
++	PHYDM_PAUSE_FUNC,
++	PHYDM_PER_TONE_EVM,
++	PHYDM_DYN_TXPWR,
++	PHYDM_LNA_SAT,
++	PHYDM_ANAPAR,
++	PHYDM_CCK_RX_PATHDIV,
++	PHYDM_BEAM_FORMING,
++	PHYDM_REG_MONITOR,
++#if RTL8814B_SUPPORT
++	PHYDM_SPUR_DETECT,
++#endif
++	PHYDM_PHY_STATUS,
++	PHYDM_CRC32_CNT,
++	PHYDM_DCC,
++#ifdef PHYDM_HW_IGI
++	PHYDM_HWIGI,
++#endif
++	PHYDM_PMAC_TX
++};
++
++struct phydm_command phy_dm_ary[] = {
++	{"-h", PHYDM_HELP}, /*@do not move this element to other position*/
++	{"demo", PHYDM_DEMO}, /*@do not move this element to other position*/
++	{"rf", PHYDM_RF_CMD},
++	{"dig", PHYDM_DIG},
++	{"ra", PHYDM_RA},
++	{"profile", PHYDM_PROFILE},
++	{"antdiv", PHYDM_ANTDIV},
++	{"pathdiv", PHYDM_PATHDIV},
++	{"dbg", PHYDM_DEBUG},
++	{"mp_dbg", PHYDM_MP_DEBUG},
++	{"fw_dbg", PHYDM_FW_DEBUG},
++	{"ability", PHYDM_SUPPORT_ABILITY},
++	{"get_txagc", PHYDM_GET_TXAGC},
++	{"set_txagc", PHYDM_SET_TXAGC},
++	{"smtant", PHYDM_SMART_ANT},
++	{"ch_bw", PHYDM_CH_BW},
++	{"trxpath", PHYDM_TRX_PATH},
++	{"lamode", PHYDM_LA_MODE},
++	{"dumpreg", PHYDM_DUMP_REG},
++	{"auto_dbg", PHYDM_AUTO_DBG},
++	{"dd_dbg", PHYDM_DD_DBG},
++	{"bigjump", PHYDM_BIG_JUMP},
++	{"rxrate", PHYDM_SHOW_RXRATE},
++	{"nbi", PHYDM_NBI_EN},
++	{"csi_mask", PHYDM_CSI_MASK_EN},
++	{"dfs", PHYDM_DFS_DEBUG},
++	{"dfs_hist", PHYDM_DFS_HIST},
++	{"nhm", PHYDM_NHM},
++	{"clm", PHYDM_CLM},
++	{"fahm", PHYDM_FAHM},
++	{"env_mntr", PHYDM_ENV_MNTR},
++	{"bbinfo", PHYDM_BB_INFO},
++	/*{"txbf", PHYDM_TXBF},*/
++	{"h2c", PHYDM_H2C},
++	{"ext_rfe", PHYDM_EXT_RF_E_CTRL},
++	{"soml", PHYDM_ADAPTIVE_SOML},
++	{"psd", PHYDM_PSD},
++	{"dbgport", PHYDM_DEBUG_PORT},
++	{"dis_htstf", PHYDM_DIS_HTSTF_CONTROL},
++	{"cfo_trk", PHYDM_CFO_TRK},
++	{"adapt_debug", PHYDM_ADAPTIVITY_DEBUG},
++	{"dis_dym_ant_wgt", PHYDM_DIS_DYM_ANT_WEIGHTING},
++	{"force_pt_state", PHYDM_FORECE_PT_STATE},
++	{"sta_info", PHYDM_STA_INFO},
++	{"pause", PHYDM_PAUSE_FUNC},
++	{"evm", PHYDM_PER_TONE_EVM},
++	{"dyn_txpwr", PHYDM_DYN_TXPWR},
++	{"lna_sat", PHYDM_LNA_SAT},
++	{"anapar", PHYDM_ANAPAR},
++	{"cck_rx_pathdiv", PHYDM_CCK_RX_PATHDIV},
++	{"bf", PHYDM_BEAM_FORMING},
++	{"reg_mntr", PHYDM_REG_MONITOR},
++#if RTL8814B_SUPPORT
++	{"spur_detect", PHYDM_SPUR_DETECT},
++#endif
++	{"physts", PHYDM_PHY_STATUS},
++	{"crc32_cnt", PHYDM_CRC32_CNT},
++#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
++	{"pmac_tx", PHYDM_PMAC_TX},
++#endif
++#ifdef PHYDM_HW_IGI
++	{"hwigi", PHYDM_HWIGI},
++#endif
++	{"dcc", PHYDM_DCC}
++
++	};
++
++#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
++
++void phydm_cmd_parser(struct dm_struct *dm, char input[][MAX_ARGV],
++		      u32 input_num, u8 flag, char *output, u32 out_len)
++{
++#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
++	u32 used = 0;
++	u8 id = 0;
++	u32 var1[10] = {0};
++	u32 i;
++	u32 phydm_ary_size = sizeof(phy_dm_ary) / sizeof(struct phydm_command);
++
++	if (flag == 0) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "GET, nothing to print\n");
++		return;
++	}
++
++	PDM_SNPF(out_len, used, output + used, out_len - used, "\n");
++
++	/* Parsing Cmd ID */
++	if (input_num) {
++		for (i = 0; i < phydm_ary_size; i++) {
++			if (strcmp(phy_dm_ary[i].name, input[0]) == 0) {
++				id = phy_dm_ary[i].id;
++				break;
++			}
++		}
++		if (i == phydm_ary_size) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "PHYDM command not found!\n");
++			return;
++		}
++	}
++
++	switch (id) {
++	case PHYDM_HELP: {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "BB cmd ==>\n");
++
++		for (i = 0; i < phydm_ary_size - 2; i++)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "  %-5d: %s\n", i, phy_dm_ary[i + 2].name);
++	} break;
++
++	case PHYDM_DEMO: { /*@echo demo 10 0x3a z abcde >cmd*/
++		u32 directory = 0;
++
++		#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
++		char char_temp;
++		#else
++		u32 char_temp = ' ';
++		#endif
++
++		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &directory);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Decimal value = %d\n", directory);
++		PHYDM_SSCANF(input[2], DCMD_HEX, &directory);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Hex value = 0x%x\n", directory);
++		PHYDM_SSCANF(input[3], DCMD_CHAR, &char_temp);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Char = %c\n", char_temp);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "String = %s\n", input[4]);
++	} break;
++	case PHYDM_RF_CMD:
++		halrf_cmd_parser(dm, input, &used, output, &out_len, input_num);
++		break;
++
++	case PHYDM_DIG:
++		phydm_dig_debug(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_RA:
++		phydm_ra_debug(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_ANTDIV:
++		#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++		phydm_antdiv_debug(dm, input, &used, output, &out_len);
++		#endif
++		break;
++
++	case PHYDM_PATHDIV:
++		#if (defined(CONFIG_PATH_DIVERSITY))
++		phydm_pathdiv_debug(dm, input, &used, output, &out_len);
++		#endif
++		break;
++
++	case PHYDM_DEBUG:
++		phydm_debug_trace(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_MP_DEBUG:
++		phydm_mp_dbg(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_FW_DEBUG:
++		phydm_fw_debug_trace(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_SUPPORT_ABILITY:
++		phydm_supportability_en(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_SMART_ANT:
++		#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++
++		#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
++		phydm_hl_smt_ant_dbg_type2(dm, input, &used, output, &out_len);
++		#elif (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))
++		phydm_hl_smart_ant_debug(dm, input, &used, output, &out_len);
++		#endif
++
++		#elif (defined(CONFIG_CUMITEK_SMART_ANTENNA))
++		phydm_cumitek_smt_ant_debug(dm, input, &used, output, &out_len);
++		#endif
++
++		break;
++
++	case PHYDM_CH_BW:
++		phydm_bw_ch_adjust(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_PROFILE:
++		phydm_basic_profile(dm, &used, output, &out_len);
++		break;
++
++	case PHYDM_GET_TXAGC:
++		phydm_get_txagc(dm, &used, output, &out_len);
++		break;
++
++	case PHYDM_SET_TXAGC:
++		phydm_set_txagc_dbg(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_TRX_PATH:
++		phydm_config_trx_path(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_LA_MODE:
++		#if (PHYDM_LA_MODE_SUPPORT)
++		phydm_la_cmd(dm, input, &used, output, &out_len);
++		#endif
++		break;
++
++	case PHYDM_DUMP_REG:
++		phydm_dump_reg(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_BIG_JUMP:
++		phydm_enable_big_jump(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_AUTO_DBG:
++		#ifdef PHYDM_AUTO_DEGBUG
++		phydm_auto_dbg_console(dm, input, &used, output, &out_len);
++		#endif
++		break;
++
++	case PHYDM_DD_DBG:
++		phydm_dd_dbg_dump(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_SHOW_RXRATE:
++		phydm_show_rx_rate(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_NBI_EN:
++		phydm_nbi_debug(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_CSI_MASK_EN:
++		phydm_csi_debug(dm, input, &used, output, &out_len);
++		break;
++
++	#ifdef CONFIG_PHYDM_DFS_MASTER
++	case PHYDM_DFS_DEBUG:
++		phydm_dfs_debug(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_DFS_HIST:
++		phydm_dfs_hist_dbg(dm, input, &used, output, &out_len);
++		break;
++	#endif
++
++	case PHYDM_NHM:
++		#ifdef NHM_SUPPORT
++		phydm_nhm_dbg(dm, input, &used, output, &out_len);
++		#endif
++		break;
++
++	case PHYDM_CLM:
++		#ifdef CLM_SUPPORT
++		phydm_clm_dbg(dm, input, &used, output, &out_len);
++		#endif
++		break;
++
++	#ifdef FAHM_SUPPORT
++	case PHYDM_FAHM:
++		phydm_fahm_dbg(dm, input, &used, output, &out_len);
++		break;
++	#endif
++
++	case PHYDM_ENV_MNTR:
++		phydm_env_mntr_dbg(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_BB_INFO:
++		phydm_bb_hw_dbg_info(dm, input, &used, output, &out_len);
++		break;
++	/*
++	case PHYDM_TXBF: {
++	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	#ifdef PHYDM_BEAMFORMING_SUPPORT
++		struct _RT_BEAMFORMING_INFO *beamforming_info = NULL;
++
++		beamforming_info = &dm->beamforming_info;
++
++		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
++		if (var1[0] == 0) {
++			beamforming_info->apply_v_matrix = false;
++			beamforming_info->snding3ss = true;
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\r\n dont apply V matrix and 3SS 789 snding\n");
++		} else if (var1[0] == 1) {
++			beamforming_info->apply_v_matrix = true;
++			beamforming_info->snding3ss = true;
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\r\n apply V matrix and 3SS 789 snding\n");
++		} else if (var1[0] == 2) {
++			beamforming_info->apply_v_matrix = true;
++			beamforming_info->snding3ss = false;
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\r\n default txbf setting\n");
++		} else
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "\r\n unknown cmd!!\n");
++	#endif
++	#endif
++	} break;
++	*/
++	case PHYDM_H2C:
++		phydm_h2C_debug(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_EXT_RF_E_CTRL:
++		phydm_ext_rf_element_ctrl(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_ADAPTIVE_SOML:
++		#ifdef CONFIG_ADAPTIVE_SOML
++		phydm_soml_debug(dm, input, &used, output, &out_len);
++		#endif
++		break;
++
++	case PHYDM_PSD:
++
++		#ifdef CONFIG_PSD_TOOL
++		phydm_psd_debug(dm, input, &used, output, &out_len);
++		#endif
++
++		break;
++
++	case PHYDM_DEBUG_PORT:
++		phydm_print_dbgport(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_DIS_HTSTF_CONTROL: {
++		if (input[1])
++			PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
++
++		if (var1[0] == 1) {
++			/* setting being false is for debug */
++			dm->bhtstfdisabled = true;
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "Dynamic HT-STF Gain Control is Disable\n");
++		} else {
++			/* @default setting should be true,
++			 * always be dynamic control
++			 */
++			dm->bhtstfdisabled = false;
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "Dynamic HT-STF Gain Control is Enable\n");
++		}
++	} break;
++
++	case PHYDM_CFO_TRK:
++		phydm_cfo_tracking_debug(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_ADAPTIVITY_DEBUG:
++		#ifdef PHYDM_SUPPORT_ADAPTIVITY
++		phydm_adaptivity_debug(dm, input, &used, output, &out_len);
++		#endif
++		break;
++
++	case PHYDM_DIS_DYM_ANT_WEIGHTING:
++		#ifdef DYN_ANT_WEIGHTING_SUPPORT
++		phydm_ant_weight_dbg(dm, input, &used, output, &out_len);
++		#endif
++		break;
++
++	case PHYDM_FORECE_PT_STATE:
++		#ifdef PHYDM_POWER_TRAINING_SUPPORT
++		phydm_pow_train_debug(dm, input, &used, output, &out_len);
++		#endif
++		break;
++
++	case PHYDM_STA_INFO:
++		phydm_show_sta_info(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_PAUSE_FUNC:
++		phydm_pause_func_console(dm, input, &used, output, &out_len);
++		break;
++
++	case PHYDM_PER_TONE_EVM:
++		phydm_per_tone_evm(dm, input, &used, output, &out_len);
++		break;
++
++	#ifdef CONFIG_DYNAMIC_TX_TWR
++	case PHYDM_DYN_TXPWR:
++		phydm_dtp_debug(dm, input, &used, output, &out_len);
++		break;
++	#endif
++
++	case PHYDM_LNA_SAT:
++		#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++		phydm_lna_sat_debug(dm, input, &used, output, &out_len);
++		#endif
++		break;
++
++	case PHYDM_ANAPAR:
++		phydm_get_anapar_table(dm, &used, output, &out_len);
++		break;
++	case PHYDM_CCK_RX_PATHDIV:
++		#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
++		phydm_cck_rx_pathdiv_dbg(dm, input, &used, output, &out_len);
++		#endif
++		break;
++
++	case PHYDM_BEAM_FORMING:
++		#ifdef CONFIG_BB_TXBF_API
++		phydm_bf_debug(dm, input, &used, output, &out_len);
++		#endif
++		break;
++	case PHYDM_REG_MONITOR:
++		phydm_reg_monitor(dm, input, &used, output, &out_len);
++		break;
++
++#if RTL8814B_SUPPORT
++	case PHYDM_SPUR_DETECT:
++		phydm_spur_detect_dbg(dm, input, &used, output, &out_len);
++		break;
++#endif
++	case PHYDM_CRC32_CNT:
++		phydm_crc32_cnt_dbg(dm, input, &used, output, &out_len);
++		break;
++	case PHYDM_PHY_STATUS:
++		phydm_physts_dbg(dm, input, &used, output, &out_len);
++		break;
++#ifdef PHYDM_DCC_ENHANCE
++	case PHYDM_DCC:
++		phydm_dig_cckpd_coex_dbg(dm, input, &used, output, &out_len);
++		break;
++#endif
++#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
++	case PHYDM_PMAC_TX:
++		phydm_pmac_tx_dbg(dm, input, &used, output, &out_len);
++		break;
++#endif
++#ifdef PHYDM_HW_IGI
++	case PHYDM_HWIGI:
++		phydm_hwigi_dbg(dm, input, &used, output, &out_len);
++		break;
++#endif
++	default:
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Do not support this command\n");
++		break;
++	}
++#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
++}
++
++#if defined __ECOS || defined __ICCARM__
++#ifndef strsep
++char *strsep(char **s, const char *ct)
++{
++	char *sbegin = *s;
++	char *end;
++
++	if (!sbegin)
++		return NULL;
++
++	end = strpbrk(sbegin, ct);
++	if (end)
++		*end++ = '\0';
++	*s = end;
++	return sbegin;
++}
++#endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP | ODM_IOT))
++s32 phydm_cmd(struct dm_struct *dm, char *input, u32 in_len, u8 flag,
++	      char *output, u32 out_len)
++{
++	char *token;
++	u32 argc = 0;
++	char argv[MAX_ARGC][MAX_ARGV];
++
++	do {
++		token = strsep(&input, ", ");
++		if (token) {
++			if (strlen(token) <= MAX_ARGV)
++				strcpy(argv[argc], token);
++
++			argc++;
++		} else {
++			break;
++		}
++	} while (argc < MAX_ARGC);
++
++	if (argc == 1)
++		argv[0][strlen(argv[0]) - 1] = '\0';
++
++	phydm_cmd_parser(dm, argv, argc, flag, output, out_len);
++
++	return 0;
++}
++#endif
++
++void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
++{
++#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	/*@u8	debug_trace_11byte[60];*/
++	u8 freg_num, c2h_seq, buf_0 = 0;
++
++	if (!(dm->support_ic_type & PHYDM_IC_3081_SERIES))
++		return;
++
++	if (cmd_len > 12 || cmd_len == 0) {
++		pr_debug("[Warning] Error C2H cmd_len=%d\n", cmd_len);
++		return;
++	}
++
++	buf_0 = cmd_buf[0];
++	freg_num = (buf_0 & 0xf);
++	c2h_seq = (buf_0 & 0xf0) >> 4;
++
++	#if 0
++	PHYDM_DBG(dm, DBG_FW_TRACE,
++		  "[FW debug message] freg_num = (( %d )), c2h_seq=(( %d ))\n",
++		  freg_num, c2h_seq);
++
++	strncpy(debug_trace_11byte, &cmd_buf[1], (cmd_len - 1));
++	debug_trace_11byte[cmd_len - 1] = '\0';
++	PHYDM_DBG(dm, DBG_FW_TRACE, "[FW debug message] %s\n",
++		  debug_trace_11byte);
++	PHYDM_DBG(dm, DBG_FW_TRACE, "[FW debug message] cmd_len = (( %d ))\n",
++		  cmd_len);
++	PHYDM_DBG(dm, DBG_FW_TRACE, "[FW debug message] c2h_cmd_start=((%d))\n",
++		  dm->c2h_cmd_start);
++
++	PHYDM_DBG(dm, DBG_FW_TRACE, "pre_seq = (( %d )), current_seq=((%d))\n",
++		  dm->pre_c2h_seq, c2h_seq);
++	PHYDM_DBG(dm, DBG_FW_TRACE, "fw_buff_is_enpty = (( %d ))\n",
++		  dm->fw_buff_is_enpty);
++	#endif
++
++	if (c2h_seq != dm->pre_c2h_seq && dm->fw_buff_is_enpty == false) {
++		dm->fw_debug_trace[dm->c2h_cmd_start] = '\0';
++		PHYDM_DBG(dm, DBG_FW_TRACE, "[FW Dbg Queue Overflow] %s\n",
++			  dm->fw_debug_trace);
++		dm->c2h_cmd_start = 0;
++	}
++
++	if ((cmd_len - 1) > (60 - dm->c2h_cmd_start)) {
++		dm->fw_debug_trace[dm->c2h_cmd_start] = '\0';
++		PHYDM_DBG(dm, DBG_FW_TRACE,
++			  "[FW Dbg Queue error: wrong C2H length] %s\n",
++			  dm->fw_debug_trace);
++		dm->c2h_cmd_start = 0;
++		return;
++	}
++
++	strncpy((char *)&dm->fw_debug_trace[dm->c2h_cmd_start],
++		(char *)&cmd_buf[1], (cmd_len - 1));
++	dm->c2h_cmd_start += (cmd_len - 1);
++	dm->fw_buff_is_enpty = false;
++
++	if (freg_num == 0 || dm->c2h_cmd_start >= 60) {
++		if (dm->c2h_cmd_start < 60)
++			dm->fw_debug_trace[dm->c2h_cmd_start] = '\0';
++		else
++			dm->fw_debug_trace[59] = '\0';
++
++		PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s\n",
++			  dm->fw_debug_trace);
++
++		dm->c2h_cmd_start = 0;
++		dm->fw_buff_is_enpty = true;
++	}
++
++	dm->pre_c2h_seq = c2h_seq;
++#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
++}
++
++void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len)
++{
++#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 function = buffer[0];
++	u8 dbg_num = buffer[1];
++	u16 content_0 = (((u16)buffer[3]) << 8) | ((u16)buffer[2]);
++	u16 content_1 = (((u16)buffer[5]) << 8) | ((u16)buffer[4]);
++	u16 content_2 = (((u16)buffer[7]) << 8) | ((u16)buffer[6]);
++	u16 content_3 = (((u16)buffer[9]) << 8) | ((u16)buffer[8]);
++	u16 content_4 = (((u16)buffer[11]) << 8) | ((u16)buffer[10]);
++
++	if (cmd_len > 12)
++		PHYDM_DBG(dm, DBG_FW_TRACE,
++			  "[FW Msg] Invalid cmd length (( %d )) >12\n",
++			  cmd_len);
++/*@--------------------------------------------*/
++#ifdef CONFIG_RA_FW_DBG_CODE
++	if (function == RATE_DECISION) {
++		if (dbg_num == 0) {
++			if (content_0 == 1)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] RA_CNT=((%d))  Max_device=((%d))--------------------------->\n",
++					  content_1, content_2);
++			else if (content_0 == 2)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] Check RA macid= ((%d)), MediaStatus=((%d)), Dis_RA=((%d)),  try_bit=((0x%x))\n",
++					  content_1, content_2, content_3,
++					  content_4);
++			else if (content_0 == 3)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] Check RA  total=((%d)),  drop=((0x%x)), TXRPT_TRY_bit=((%x)), bNoisy=((%x))\n",
++					  content_1, content_2, content_3,
++					  content_4);
++		} else if (dbg_num == 1) {
++			if (content_0 == 1)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] RTY[0,1,2,3]=[ %d , %d , %d , %d ]\n",
++					  content_1, content_2, content_3,
++					  content_4);
++			else if (content_0 == 2) {
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] RTY[4]=[ %d ], drop=(( %d )), total=(( %d )), current_rate=((0x %x ))",
++					  content_1, content_2, content_3,
++					  content_4);
++				phydm_print_rate(dm, (u8)content_4,
++						 DBG_FW_TRACE);
++			} else if (content_0 == 3)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] penality_idx=(( %d ))\n",
++					  content_1);
++			else if (content_0 == 4)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] RSSI=(( %d )), ra_stage = (( %d ))\n",
++					  content_1, content_2);
++		} else if (dbg_num == 3) {
++			if (content_0 == 1)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] Fast_RA (( DOWN ))  total=((%d)),  total>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n",
++					  content_1, content_2, content_3,
++					  content_4);
++			else if (content_0 == 2)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] Fast_RA (( UP ))  total_acc=((%d)),  total_acc>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n",
++					  content_1, content_2, content_3,
++					  content_4);
++			else if (content_0 == 3)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] Fast_RA (( UP )) ((rate Down Hold))  RA_CNT=((%d))\n",
++					  content_1);
++			else if (content_0 == 4)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] Fast_RA (( UP )) ((tota_accl<5 skip))  RA_CNT=((%d))\n",
++					  content_1);
++			else if (content_0 == 8)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] Fast_RA (( Reset Tx Rpt )) RA_CNT=((%d))\n",
++					  content_1);
++		} else if (dbg_num == 4) {
++			if (content_0 == 3)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] RER_CNT   PCR_ori =(( %d )),  ratio_ori =(( %d )), pcr_updown_bitmap =(( 0x%x )), pcr_var_diff =(( %d ))\n",
++					  content_1, content_2, content_3,
++					  content_4);
++			else if (content_0 == 4)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] pcr_shift_value =(( %s%d )), rate_down_threshold =(( %d )), rate_up_threshold =(( %d ))\n",
++					  ((content_1) ? "+" : "-"), content_2,
++					  content_3, content_4);
++			else if (content_0 == 5)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] pcr_mean =(( %d )), PCR_VAR =(( %d )), offset =(( %d )), decision_offset_p =(( %d ))\n",
++					  content_1, content_2, content_3,
++					  content_4);
++		} else if (dbg_num == 5) {
++			if (content_0 == 1)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] (( UP))  Nsc=(( %d )), N_High=(( %d )), RateUp_Waiting=(( %d )), RateUp_Fail=(( %d ))\n",
++					  content_1, content_2, content_3,
++					  content_4);
++			else if (content_0 == 2)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] ((DOWN))  Nsc=(( %d )), N_Low=(( %d ))\n",
++					  content_1, content_2);
++			else if (content_0 == 3)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] ((HOLD))  Nsc=((%d)), N_High=((%d)), N_Low=((%d)), Reset_CNT=((%d))\n",
++					  content_1, content_2, content_3,
++					  content_4);
++		} else if (dbg_num == 0x60) {
++			if (content_0 == 1)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] ((AP RPT))  macid=((%d)), BUPDATE[macid]=((%d))\n",
++					  content_1, content_2);
++			else if (content_0 == 4)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] ((AP RPT))  pass=((%d)), rty_num=((%d)), drop=((%d)), total=((%d))\n",
++					  content_1, content_2, content_3,
++					  content_4);
++			else if (content_0 == 5)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW] ((AP RPT))  PASS=((%d)), RTY_NUM=((%d)), DROP=((%d)), TOTAL=((%d))\n",
++					  content_1, content_2, content_3,
++					  content_4);
++		}
++	} else if (function == INIT_RA_TABLE) {
++		if (dbg_num == 3)
++			PHYDM_DBG(dm, DBG_FW_TRACE,
++				  "[FW][INIT_RA_INFO] Ra_init, RA_SKIP_CNT = (( %d ))\n",
++				  content_0);
++	} else if (function == RATE_UP) {
++		if (dbg_num == 2) {
++			if (content_0 == 1)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW][RateUp]  ((Highest rate->return)), macid=((%d))  Nsc=((%d))\n",
++					  content_1, content_2);
++		} else if (dbg_num == 5) {
++			if (content_0 == 0)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW][RateUp]  ((rate UP)), up_rate_tmp=((0x%x)), rate_idx=((0x%x)), SGI_en=((%d)),  SGI=((%d))\n",
++					  content_1, content_2, content_3,
++					  content_4);
++			else if (content_0 == 1)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW][RateUp]  ((rate UP)), rate_1=((0x%x)), rate_2=((0x%x)), BW=((%d)), Try_Bit=((%d))\n",
++					  content_1, content_2, content_3,
++					  content_4);
++		}
++	} else if (function == RATE_DOWN) {
++		if (dbg_num == 5) {
++			if (content_0 == 1)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW][RateDownStep]  ((rate Down)), macid=((%d)), rate1=((0x%x)),  rate2=((0x%x)), BW=((%d))\n",
++					  content_1, content_2, content_3,
++					  content_4);
++		}
++	} else if (function == TRY_DONE) {
++		if (dbg_num == 1) {
++			if (content_0 == 1)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW][Try Done]  ((try succsess )) macid=((%d)), Try_Done_cnt=((%d))\n",
++					  content_1, content_2);
++		} else if (dbg_num == 2) {
++			if (content_0 == 1)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW][Try Done]  ((try)) macid=((%d)), Try_Done_cnt=((%d)),  rate_2=((%d)),  try_succes=((%d))\n",
++					  content_1, content_2, content_3,
++					  content_4);
++		}
++	} else if (function == RA_H2C) {
++		if (dbg_num == 1) {
++			if (content_0 == 0)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW][H2C=0x49]  fw_trace_en=((%d)), mode =((%d)),  macid=((%d))\n",
++					  content_1, content_2, content_3);
++		}
++	} else if (function == F_RATE_AP_RPT) {
++		if (dbg_num == 1) {
++			if (content_0 == 1)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW][AP RPT]  ((1)), SPE_STATIS=((0x%x))---------->\n",
++					  content_3);
++		} else if (dbg_num == 2) {
++			if (content_0 == 1)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW][AP RPT]  RTY_all=((%d))\n",
++					  content_1);
++		} else if (dbg_num == 3) {
++			if (content_0 == 1)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW][AP RPT]  MACID1[%d], TOTAL=((%d)),  RTY=((%d))\n",
++					  content_3, content_1, content_2);
++		} else if (dbg_num == 4) {
++			if (content_0 == 1)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW][AP RPT]  MACID2[%d], TOTAL=((%d)),  RTY=((%d))\n",
++					  content_3, content_1, content_2);
++		} else if (dbg_num == 5) {
++			if (content_0 == 1)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW][AP RPT]  MACID1[%d], PASS=((%d)),  DROP=((%d))\n",
++					  content_3, content_1, content_2);
++		} else if (dbg_num == 6) {
++			if (content_0 == 1)
++				PHYDM_DBG(dm, DBG_FW_TRACE,
++					  "[FW][AP RPT]  MACID2[%d],, PASS=((%d)),  DROP=((%d))\n",
++					  content_3, content_1, content_2);
++		}
++	} else if (function == DBC_FW_CLM) {
++		PHYDM_DBG(dm, DBG_FW_TRACE,
++			  "[FW][CLM][%d, %d] = {%d, %d, %d, %d}\n", dbg_num,
++			  content_0, content_1, content_2, content_3,
++			  content_4);
++	} else {
++		PHYDM_DBG(dm, DBG_FW_TRACE,
++			  "[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n",
++			  function, dbg_num, content_0, content_1, content_2,
++			  content_3, content_4);
++	}
++#else
++	PHYDM_DBG(dm, DBG_FW_TRACE,
++		  "[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function,
++		  dbg_num, content_0, content_1, content_2, content_3,
++		  content_4);
++#endif
++/*@--------------------------------------------*/
++
++#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
++}
++
++void phydm_fw_trace_handler_8051(void *dm_void, u8 *buffer, u8 cmd_len)
++{
++#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	int i = 0;
++	u8 extend_c2h_sub_id = 0, extend_c2h_dbg_len = 0;
++	u8 extend_c2h_dbg_seq = 0;
++	u8 fw_debug_trace[128];
++	u8 *extend_c2h_dbg_content = 0;
++
++	if (cmd_len > 127)
++		return;
++
++	extend_c2h_sub_id = buffer[0];
++	extend_c2h_dbg_len = buffer[1];
++	extend_c2h_dbg_content = buffer + 2; /*@DbgSeq+DbgContent for show HEX*/
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	RT_DISP(FC2H, C2H_Summary, ("[Extend C2H packet], Extend_c2hSubId=0x%x, extend_c2h_dbg_len=%d\n",
++				    extend_c2h_sub_id, extend_c2h_dbg_len));
++
++	RT_DISP_DATA(FC2H, C2H_Summary, "[Extend C2H packet], Content Hex:", extend_c2h_dbg_content, cmd_len - 2);
++#endif
++
++go_backfor_aggre_dbg_pkt:
++	i = 0;
++	extend_c2h_dbg_seq = buffer[2];
++	extend_c2h_dbg_content = buffer + 3;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	RT_DISP(FC2H, C2H_Summary, ("[RTKFW, SEQ= %d] :", extend_c2h_dbg_seq));
++#endif
++
++	for (;; i++) {
++		fw_debug_trace[i] = extend_c2h_dbg_content[i];
++		if (extend_c2h_dbg_content[i + 1] == '\0') {
++			fw_debug_trace[i + 1] = '\0';
++			PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s",
++				  &fw_debug_trace[0]);
++			break;
++		} else if (extend_c2h_dbg_content[i] == '\n') {
++			fw_debug_trace[i + 1] = '\0';
++			PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s",
++				  &fw_debug_trace[0]);
++			buffer = extend_c2h_dbg_content + i + 3;
++			goto go_backfor_aggre_dbg_pkt;
++		}
++	}
++#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_debug.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_debug.h
+new file mode 100644
+index 000000000..5b0d283d3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_debug.h
+@@ -0,0 +1,484 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __ODM_DBG_H__
++#define __ODM_DBG_H__
++
++/*#define DEBUG_VERSION	"1.1"*/ /*2015.07.29 YuChen*/
++/*#define DEBUG_VERSION	"1.2"*/ /*2015.08.28 Dino*/
++/*#define DEBUG_VERSION	"1.3"*/ /*2016.04.28 YuChen*/
++/*#define DEBUG_VERSION	"1.4"*/ /*2017.03.13 Dino*/
++/*#define DEBUG_VERSION "2.0"*/ /*2018.01.10 Dino*/
++/*2019.09.17 add hwigi mechanism*/
++#define DEBUG_VERSION "4.2"
++
++/*@
++ * ============================================================
++ *  Definition
++ * ============================================================
++ */
++
++/*@FW DBG MSG*/
++#define	RATE_DECISION		1
++#define	INIT_RA_TABLE		2
++#define	RATE_UP			4
++#define	RATE_DOWN		8
++#define	TRY_DONE		16
++#define	RA_H2C			32
++#define	F_RATE_AP_RPT		64
++#define	DBC_FW_CLM		9
++
++#define PHYDM_SNPRINT_SIZE	64
++/* @----------------------------------------------------------------------------
++ * Define the tracing components
++ *
++ * -----------------------------------------------------------------------------
++ * BB FW Functions
++ */
++#define	PHYDM_FW_COMP_RA	BIT(0)
++#define	PHYDM_FW_COMP_MU	BIT(1)
++#define	PHYDM_FW_COMP_PATH_DIV	BIT(2)
++#define	PHYDM_FW_COMP_PT	BIT(3)
++
++/*@------------------------Export Marco Definition---------------------------*/
++
++#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA)
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	#if (DBG_CMD_SUPPORT == 1)
++		extern	VOID DCMD_Printf(const char *pMsg);
++	#else
++		#define DCMD_Printf(_pMsg)
++	#endif
++
++	#if OS_WIN_FROM_WIN10(OS_VERSION)
++	#define	pr_debug(fmt, ...) DbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, fmt, ##__VA_ARGS__)
++	#else
++	#define	pr_debug		DbgPrint
++	#endif
++
++	#define	dcmd_printf		DCMD_Printf
++	#define	dcmd_scanf		DCMD_Scanf
++	#define	RT_PRINTK		pr_debug
++	#define	PRINT_MAX_SIZE		512
++	#define PHYDM_SNPRINTF		RT_SPRINTF
++	#define	PHYDM_TRACE(_MSG_) 	EXhalPHYDMoutsrc_Print(_MSG_)
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	#define PHYDM_SNPRINTF		snprintf
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	#undef	pr_debug
++	#define pr_debug		printk
++	#define RT_PRINTK(fmt, args...)	pr_debug(fmt, ## args)
++	#define	RT_DISP(dbgtype, dbgflag, printstr)
++	#define RT_TRACE(adapter, comp, drv_level, fmt, args...)	\
++		RTW_INFO(fmt, ## args)
++	#define PHYDM_SNPRINTF		snprintf
++#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
++	#define pr_debug(fmt, args...)		RTW_PRINT_MSG(fmt, ## args)
++	#define RT_DEBUG(comp, drv_level, fmt, args...)	\
++		RTW_PRINT_MSG(fmt, ## args)
++	#define PHYDM_SNPRINTF		snprintf
++#else
++	#define pr_debug	panic_printk
++	/*@#define RT_PRINTK(fmt, args...)	pr_debug("%s(): " fmt, __FUNCTION__, ## args);*/
++	#define RT_PRINTK(fmt, args...)	pr_debug(fmt, ## args)
++	#define PHYDM_SNPRINTF		snprintf
++#endif
++
++#ifndef ASSERT
++	#define ASSERT(expr)
++#endif
++
++#if DBG
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++#define PHYDM_DBG(dm, comp, fmt, args...)			\
++	do {							\
++		if ((comp) & dm->debug_components) {          \
++			pr_debug("[PHYDM] ");			\
++			RT_PRINTK(fmt, ## args);		\
++		}						\
++	} while (0)
++
++#define PHYDM_DBG_F(dm, comp, fmt, args...)			\
++	do {							\
++		if ((comp) & dm->debug_components) {		\
++			RT_PRINTK(fmt, ## args);		\
++		}						\
++	} while (0)
++
++#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)		\
++	do {							\
++		if ((comp) & dm->debug_components) {		\
++			int __i;				\
++			u8 *__ptr = (u8 *)addr;			\
++			pr_debug("[PHYDM] ");			\
++			pr_debug(title_str);			\
++			pr_debug(" ");				\
++			for (__i = 0; __i < 6; __i++)		\
++				pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-");\
++			pr_debug("\n");				\
++		}						\
++	} while (0)
++#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++
++static __inline void PHYDM_DBG(PDM_ODM_T dm, int comp, char *fmt, ...)
++{
++	RT_STATUS rt_status;
++	va_list args;
++	char buf[PRINT_MAX_SIZE] = {0};
++
++	if ((comp & dm->debug_components) == 0)
++		return;
++
++	if (fmt == NULL)
++		return;
++
++	va_start(args, fmt);
++	rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
++	va_end(args);
++
++	if (rt_status != RT_STATUS_SUCCESS) {
++		DbgPrint("Failed (%d) to print message to buffer\n", rt_status);
++		return;
++	}
++
++	#if OS_WIN_FROM_WIN10(OS_VERSION)
++	DbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, "%s", buf);
++	#else
++	DbgPrint("%s", buf);
++	#endif
++}
++
++static __inline void PHYDM_DBG_F(PDM_ODM_T dm, int comp, char *fmt, ...)
++{
++	RT_STATUS rt_status;
++	va_list args;
++	char buf[PRINT_MAX_SIZE] = {0};
++
++	if ((comp & dm->debug_components) == 0)
++		return;
++
++	if (fmt == NULL)
++		return;
++
++	va_start(args, fmt);
++	rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
++	va_end(args);
++
++	if (rt_status != RT_STATUS_SUCCESS) {
++		/*@DbgPrint("DM Print Fail\n");*/
++		return;
++	}
++
++	#if OS_WIN_FROM_WIN10(OS_VERSION)
++	DbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, "%s", buf);
++	#else
++	DbgPrint("%s", buf);
++	#endif
++}
++
++#define PHYDM_PRINT_ADDR(p_dm, comp, title_str, ptr)		\
++	do {							\
++		if ((comp) & p_dm->debug_components) {		\
++								\
++			int __i;				\
++			u8 *__ptr = (u8 *)ptr;			\
++			pr_debug("[PHYDM] ");			\
++			pr_debug(title_str);			\
++			pr_debug(" ");				\
++			for (__i = 0; __i < 6; __i++)		\
++				pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-");	\
++			pr_debug("\n");				\
++		}	\
++	} while (0)
++#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
++
++#define PHYDM_DBG(dm, comp, fmt, args...)			\
++	do {							\
++		if ((comp) & dm->debug_components) {		\
++			RT_DEBUG(COMP_PHYDM, \
++				 DBG_DMESG, "[PHYDM] " fmt, ##args);	\
++		}						\
++	} while (0)
++
++#define PHYDM_DBG_F(dm, comp, fmt, args...)			\
++	do {							\
++		if ((comp) & dm->debug_components) {		\
++			RT_DEBUG(COMP_PHYDM, \
++				 DBG_DMESG, fmt, ##args);	\
++		}	\
++	} while (0)
++
++#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)		\
++	do {							\
++		if ((comp) & dm->debug_components) {		\
++			RT_DEBUG(COMP_PHYDM, \
++				 DBG_DMESG, "[PHYDM] " title_str "%pM\n",	\
++				 addr);				\
++		}						\
++	} while (0)
++
++#elif defined(DM_ODM_CE_MAC80211_V2)
++
++#define PHYDM_DBG(dm, comp, fmt, args...)
++#define PHYDM_DBG_F(dm, comp, fmt, args...)
++#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)
++
++#else
++
++#define PHYDM_DBG(dm, comp, fmt, args...)			\
++	do {							\
++		struct dm_struct *__dm = (dm);			\
++		if ((comp) & __dm->debug_components) {		\
++			RT_TRACE(((struct rtl_priv *)__dm->adapter),\
++				 COMP_PHYDM, DBG_DMESG,		\
++				 "[PHYDM] " fmt, ##args);	\
++		}						\
++	} while (0)
++
++#define PHYDM_DBG_F(dm, comp, fmt, args...)			\
++	do {							\
++		struct dm_struct *__dm = (dm);			\
++		if ((comp) & __dm->debug_components) {		\
++			RT_TRACE(((struct rtl_priv *)__dm->adapter),\
++				 COMP_PHYDM, DBG_DMESG, fmt, ##args);	\
++		}	\
++	} while (0)
++
++#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)		\
++	do {							\
++		struct dm_struct *__dm = (dm);			\
++		if ((comp) & __dm->debug_components) {		\
++			RT_TRACE(((struct rtl_priv *)__dm->adapter),\
++				 COMP_PHYDM, DBG_DMESG,		\
++				 "[PHYDM] " title_str "%pM\n", addr);\
++		}						\
++	} while (0)
++#endif
++
++#else /*@#if DBG*/
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++static __inline void PHYDM_DBG(struct dm_struct *dm, int comp, char *fmt, ...)
++{
++	RT_STATUS rt_status;
++	va_list args;
++	char buf[PRINT_MAX_SIZE] = {0};
++
++	if ((comp & dm->debug_components) == 0)
++		return;
++
++	if (fmt == NULL)
++		return;
++
++	va_start(args, fmt);
++	rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
++	va_end(args);
++
++	if (rt_status != RT_STATUS_SUCCESS) {
++		DbgPrint("Failed (%d) to print message to buffer\n", rt_status);
++		return;
++	}
++
++	PHYDM_TRACE(buf);
++}
++static __inline void PHYDM_DBG_F(struct dm_struct *dm, int comp, char *fmt, ...)
++{
++}
++#else
++#define PHYDM_DBG(dm, comp, fmt, args...)
++#define PHYDM_DBG_F(dm, comp, fmt, args...)
++#endif
++#define PHYDM_PRINT_ADDR(dm, comp, title_str, ptr)
++
++#endif
++
++#define	DBGPORT_PRI_3	3	/*@Debug function (the highest priority)*/
++#define	DBGPORT_PRI_2	2	/*@Check hang function & Strong function*/
++#define	DBGPORT_PRI_1	1	/*Watch dog function*/
++#define	DBGPORT_RELEASE	0	/*@Init value (the lowest priority)*/
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++#define	PHYDM_DBGPRINT		0
++#define	PHYDM_SSCANF(x, y, z)	dcmd_scanf(x, y, z)
++#define	PDM_VAST_SNPF		PDM_SNPF
++#if (PHYDM_DBGPRINT == 1)
++#define	PDM_SNPF(msg)	\
++	do {\
++		rsprintf msg;\
++		pr_debug("%s", output);\
++	} while (0)
++#else
++
++static __inline void PDM_SNPF(u32 out_len, u32 used, char *buff, int len,
++			      char *fmt, ...)
++{
++	RT_STATUS rt_status;
++	va_list args;
++	char buf[PRINT_MAX_SIZE] = {0};
++
++	if (fmt == NULL)
++		return;
++
++	va_start(args, fmt);
++	rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
++	va_end(args);
++
++	if (rt_status != RT_STATUS_SUCCESS) {
++		/*@DbgPrint("DM Print Fail\n");*/
++		return;
++	}
++
++	DCMD_Printf(buf);
++}
++
++
++
++#endif	/*@#if (PHYDM_DBGPRINT == 1)*/
++#else	/*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/
++	#if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__)
++	#define	PHYDM_DBGPRINT	0
++	#else
++	#define	PHYDM_DBGPRINT	1
++	#endif
++#define	MAX_ARGC		20
++#define	MAX_ARGV		16
++#define	DCMD_DECIMAL		"%d"
++#define	DCMD_CHAR		"%c"
++#define	DCMD_HEX		"%x"
++
++#define	PHYDM_SSCANF(x, y, z)	sscanf(x, y, z)
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) RT_PRINTK(fmt, ## args)
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++#define	PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...)	\
++	do {								\
++		RT_DEBUG(COMP_PHYDM, DBG_DMESG, fmt, ##args);		\
++	} while (0)
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++#define	PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...)
++#else
++#define	PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...)	\
++		RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \
++			DBG_DMESG, fmt, ##args)
++#endif
++
++#if (PHYDM_DBGPRINT == 1)
++#define	PDM_SNPF(out_len, used, buff, len, fmt, args...)		\
++	do {								\
++		snprintf(buff, len, fmt, ##args);			\
++		pr_debug("%s", output);					\
++	} while (0)
++#else
++#define	PDM_SNPF(out_len, used, buff, len, fmt, args...)		\
++	do {								\
++		u32 *__pdm_snpf_u = &(used);				\
++		if (out_len > *__pdm_snpf_u)				\
++			*__pdm_snpf_u += snprintf(buff, len, fmt, ##args);\
++	} while (0)
++#endif
++#endif
++/* @1 ============================================================
++ * 1  enumeration
++ * 1 ============================================================
++ */
++
++enum auto_detection_state { /*@Fast antenna training*/
++	AD_LEGACY_MODE	= 0,
++	AD_HT_MODE	= 1,
++	AD_VHT_MODE	= 2
++};
++
++/*@
++ * ============================================================
++ * 1  structure
++ * ============================================================
++ */
++
++#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
++u8 phydm_get_l_sig_rate(void *dm_void, u8 rate_idx_l_sig);
++#endif
++
++void phydm_init_debug_setting(struct dm_struct *dm);
++
++void phydm_bb_dbg_port_header_sel(void *dm_void, u32 header_idx);
++
++u32 phydm_get_bb_dbg_port_idx(void *dm_void);
++
++u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port);
++
++void phydm_release_bb_dbg_port(void *dm_void);
++
++u32 phydm_get_bb_dbg_port_val(void *dm_void);
++
++void phydm_reset_rx_rate_distribution(struct dm_struct *dm);
++
++void phydm_rx_rate_distribution(void *dm_void);
++
++u16 phydm_rx_avg_phy_rate(void *dm_void);
++
++void phydm_show_phy_hitogram(void *dm_void);
++
++void phydm_get_avg_phystatus_val(void *dm_void);
++
++void phydm_get_phy_statistic(void *dm_void);
++
++void phydm_dm_summary(void *dm_void, u8 macid);
++
++void phydm_basic_dbg_message(void *dm_void);
++
++void phydm_basic_profile(void *dm_void, u32 *_used, char *output,
++			 u32 *_out_len);
++#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
++s32 phydm_cmd(struct dm_struct *dm, char *input, u32 in_len, u8 flag,
++	      char *output, u32 out_len);
++#endif
++void phydm_cmd_parser(struct dm_struct *dm, char input[][16], u32 input_num,
++		      u8 flag, char *output, u32 out_len);
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void phydm_basic_dbg_msg_cli_win(void *dm_void, char *buf);
++
++void phydm_sbd_check(
++	struct dm_struct *dm);
++
++void phydm_sbd_callback(
++	struct phydm_timer_list *timer);
++
++void phydm_sbd_workitem_callback(
++	void *context);
++#endif
++
++void phydm_fw_trace_en_h2c(void *dm_void, boolean enable,
++			   u32 fw_debug_component, u32 monitor_mode, u32 macid);
++
++void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
++
++void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len);
++
++void phydm_fw_trace_handler_8051(void *dm_void, u8 *cmd_buf, u8 cmd_len);
++
++#endif /* @__ODM_DBG_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dfs.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dfs.c
+new file mode 100644
+index 000000000..5d7aa229f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dfs.c
+@@ -0,0 +1,2196 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@
++ * ============================================================
++ * include files
++ * ============================================================
++ */
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#if defined(CONFIG_PHYDM_DFS_MASTER)
++
++boolean phydm_dfs_is_meteorology_channel(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	u8 ch = *dm->channel;
++	u8 bw = *dm->band_width;
++
++	return ((bw  == CHANNEL_WIDTH_80 && (ch) >= 116 && (ch) <= 128) ||
++		(bw  == CHANNEL_WIDTH_40 && (ch) >= 116 && (ch) <= 128) ||
++		(bw  == CHANNEL_WIDTH_20 && (ch) >= 120 && (ch) <= 128));
++}
++
++void phydm_dfs_segment_distinguish(void *dm_void, enum rf_syn syn_path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (!(dm->support_ic_type & (ODM_RTL8814B)))
++		return;
++	if (syn_path == RF_SYN1)
++		dm->seg1_dfs_flag = 1;
++	else
++		dm->seg1_dfs_flag = 0;
++}
++
++void phydm_dfs_segment_flag_reset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (!(dm->support_ic_type & (ODM_RTL8814B)))
++		return;
++	if (dm->seg1_dfs_flag)
++		dm->seg1_dfs_flag = 0;
++}
++
++void phydm_radar_detect_reset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
++				   ODM_RTL8197G)) {
++		odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
++		odm_set_bb_reg(dm, R_0xa40, BIT(15), 1);
++	#if (RTL8721D_SUPPORT)
++	} else if (dm->support_ic_type & (ODM_RTL8721D)) {
++		odm_set_bb_reg(dm, R_0xf58, BIT(29), 0);
++		odm_set_bb_reg(dm, R_0xf58, BIT(29), 1);
++	#endif
++	} else if (dm->support_ic_type & (ODM_RTL8814B)) {
++		if (dm->seg1_dfs_flag == 1) {
++			odm_set_bb_reg(dm, R_0xa6c, BIT(0), 0);
++			odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
++			return;
++		}
++		odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
++		odm_set_bb_reg(dm, R_0xa40, BIT(15), 1);
++	} else {
++		odm_set_bb_reg(dm, R_0x924, BIT(15), 0);
++		odm_set_bb_reg(dm, R_0x924, BIT(15), 1);
++	}
++}
++
++void phydm_radar_detect_disable(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
++				   ODM_RTL8197G))
++		odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
++	else if (dm->support_ic_type & (ODM_RTL8814B)) {
++		if (dm->seg1_dfs_flag == 1) {
++			odm_set_bb_reg(dm, R_0xa6c, BIT(0), 0);
++			dm->seg1_dfs_flag = 0;
++			return;
++		}
++		odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
++	}
++	#if (RTL8721D_SUPPORT)
++	else if (dm->support_ic_type & (ODM_RTL8721D))
++		odm_set_bb_reg(dm, R_0xf58, BIT(29), 0);
++	#endif
++	else
++		odm_set_bb_reg(dm, R_0x924, BIT(15), 0);
++
++	PHYDM_DBG(dm, DBG_DFS, "\n");
++}
++
++static void phydm_radar_detect_with_dbg_parm(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & ODM_RTL8721D) {
++		odm_set_bb_reg(dm, R_0xf54, MASKDWORD,
++			       dm->radar_detect_reg_f54);
++		odm_set_bb_reg(dm, R_0xf58, MASKDWORD,
++			       dm->radar_detect_reg_f58);
++		odm_set_bb_reg(dm, R_0xf5c, MASKDWORD,
++			       dm->radar_detect_reg_f5c);
++		odm_set_bb_reg(dm, R_0xf70, MASKDWORD,
++			       dm->radar_detect_reg_f70);
++		odm_set_bb_reg(dm, R_0xf74, MASKDWORD,
++			       dm->radar_detect_reg_f74);
++	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		odm_set_bb_reg(dm, R_0xa40, MASKDWORD,
++			       dm->radar_detect_reg_a40);
++		odm_set_bb_reg(dm, R_0xa44, MASKDWORD,
++			       dm->radar_detect_reg_a44);
++		odm_set_bb_reg(dm, R_0xa48, MASKDWORD,
++			       dm->radar_detect_reg_a48);
++		odm_set_bb_reg(dm, R_0xa4c, MASKDWORD,
++			       dm->radar_detect_reg_a4c);
++		odm_set_bb_reg(dm, R_0xa50, MASKDWORD,
++			       dm->radar_detect_reg_a50);
++		odm_set_bb_reg(dm, R_0xa54, MASKDWORD,
++			       dm->radar_detect_reg_a54);
++	} else {
++		odm_set_bb_reg(dm, R_0x918, MASKDWORD,
++			       dm->radar_detect_reg_918);
++		odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
++			       dm->radar_detect_reg_91c);
++		odm_set_bb_reg(dm, R_0x920, MASKDWORD,
++			       dm->radar_detect_reg_920);
++		odm_set_bb_reg(dm, R_0x924, MASKDWORD,
++			       dm->radar_detect_reg_924);
++	}
++}
++
++/* @Init radar detection parameters, called after ch, bw is set */
++
++void phydm_radar_detect_enable(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _DFS_STATISTICS *dfs = &dm->dfs;
++	u8 region_domain = dm->dfs_region_domain;
++	u8 c_channel = *dm->channel;
++	u8 band_width = *dm->band_width;
++	u8 enable = 0, i;
++	u8 short_pw_upperbound = 0;
++
++	PHYDM_DBG(dm, DBG_DFS, "test, region_domain = %d\n", region_domain);
++	if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) {
++		PHYDM_DBG(dm, DBG_DFS, "PHYDM_DFS_DOMAIN_UNKNOWN\n");
++		goto exit;
++	}
++
++	if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) {
++		odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);
++		odm_set_bb_reg(dm, R_0x834, MASKBYTE0, 0x06);
++
++		if (dm->radar_detect_dbg_parm_en) {
++			phydm_radar_detect_with_dbg_parm(dm);
++			enable = 1;
++			goto exit;
++		}
++
++		if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
++			odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c17ecdf);
++			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);
++			odm_set_bb_reg(dm, R_0x91c, MASKDWORD, 0x0fa21a20);
++			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0f69204);
++
++		} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
++			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);
++			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67234);
++
++			if (c_channel >= 52 && c_channel <= 64) {
++				odm_set_bb_reg(dm, R_0x918, MASKDWORD,
++					       0x1c16ecdf);
++				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
++					       0x0f141a20);
++			} else {
++				odm_set_bb_reg(dm, R_0x918, MASKDWORD,
++					       0x1c16acdf);
++				if (band_width == CHANNEL_WIDTH_20)
++					odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
++						       0x64721a20);
++				else
++					odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
++						       0x68721a20);
++			}
++
++		} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
++			odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c16acdf);
++			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);
++			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67231);
++			if (band_width == CHANNEL_WIDTH_20)
++				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
++					       0x64741a20);
++			else
++				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
++					       0x68741a20);
++
++		} else {
++			/* not supported */
++			PHYDM_DBG(dm, DBG_DFS,
++				  "Unsupported dfs_region_domain:%d\n",
++				  region_domain);
++			goto exit;
++		}
++
++	} else if (dm->support_ic_type &
++		   (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
++
++		odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);
++		odm_set_bb_reg(dm, R_0x834, MASKBYTE0, 0x06);
++
++		/* @8822B only, when BW = 20M, DFIR output is 40Mhz,
++		 * but DFS input is 80MMHz, so it need to upgrade to 80MHz
++		 */
++		if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
++			if (band_width == CHANNEL_WIDTH_20)
++				odm_set_bb_reg(dm, R_0x1984, BIT(26), 1);
++			else
++				odm_set_bb_reg(dm, R_0x1984, BIT(26), 0);
++		}
++
++		if (dm->radar_detect_dbg_parm_en) {
++			phydm_radar_detect_with_dbg_parm(dm);
++			enable = 1;
++			goto exit;
++		}
++
++		if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
++			odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c16acdf);
++			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8500);
++			odm_set_bb_reg(dm, R_0x91c, MASKDWORD, 0x0fc01a1f);
++			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0f57204);
++
++		} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
++			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8500);
++			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67234);
++
++			if (c_channel >= 52 && c_channel <= 64) {
++				odm_set_bb_reg(dm, R_0x918, MASKDWORD,
++					       0x1c16ecdf);
++				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
++					       0x0f141a1f);
++			} else {
++				odm_set_bb_reg(dm, R_0x918, MASKDWORD,
++					       0x1c166cdf);
++				if (band_width == CHANNEL_WIDTH_20)
++					odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
++						       0x64721a1f);
++				else
++					odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
++						       0x68721a1f);
++			}
++
++		} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
++			odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c176cdf);
++			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8400);
++			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe076d231);
++			if (band_width == CHANNEL_WIDTH_20)
++				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
++					       0x64901a1f);
++			else
++				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
++					       0x62901a1f);
++
++		} else {
++			/* not supported */
++			PHYDM_DBG(dm, DBG_DFS,
++				  "Unsupported dfs_region_domain:%d\n",
++				  region_domain);
++			goto exit;
++		}
++		/*RXHP low corner will extend the pulse width,
++		 *so we need to increase the upper bound.
++		 */
++		if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
++			if (odm_get_bb_reg(dm, 0x8d8,
++					   BIT28 | BIT27 | BIT26) == 0) {
++				short_pw_upperbound =
++					(u8)odm_get_bb_reg(dm, 0x91c,
++						       BIT23 | BIT22 |
++						       BIT21 | BIT20);
++				if ((short_pw_upperbound + 4) > 15)
++					odm_set_bb_reg(dm, 0x91c,
++						       BIT23 | BIT22 |
++						       BIT21 | BIT20, 15);
++				else
++					odm_set_bb_reg(dm, 0x91c,
++						       BIT23 | BIT22 |
++						       BIT21 | BIT20,
++						       short_pw_upperbound + 4);
++			}
++			/*@if peak index -1~+1, use original NB method*/
++			odm_set_bb_reg(dm, 0x19e4, 0x003C0000, 13);
++			odm_set_bb_reg(dm, 0x924, 0x70000, 0);
++		}
++
++		if (dm->support_ic_type & (ODM_RTL8881A))
++			odm_set_bb_reg(dm, 0xb00, 0xc0000000, 3);
++
++		/*@for 8814 new dfs mechanism setting*/
++		if (dm->support_ic_type &
++		    (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
++			/*Turn off dfs scaling factor*/
++			odm_set_bb_reg(dm, 0x19e4, 0x1fff, 0x0c00);
++			/*NonDC peak_th = 2times DC peak_th*/
++			odm_set_bb_reg(dm, 0x19e4, 0x30000, 1);
++			/*power for debug and auto test flow latch after ST*/
++			odm_set_bb_reg(dm, 0x9f8, 0xc0000000, 3);
++
++			/*@low pulse width radar pattern will cause wrong drop*/
++			/*@disable peak index should the same
++			 *during the same short pulse (new mechan)
++			 */
++			odm_set_bb_reg(dm, 0x9f4, 0x80000000, 0);
++
++			/*@disable peak index should the same
++			 *during the same short pulse (old mechan)
++			 */
++			odm_set_bb_reg(dm, 0x924, 0x20000000, 0);
++
++			/*@if peak index diff >=2, then drop the result*/
++			odm_set_bb_reg(dm, 0x19e4, 0xe000, 2);
++			if (region_domain == 2) {
++				if ((c_channel >= 52) && (c_channel <= 64)) {
++					/*pulse width hist th setting*/
++					/*th1=2*04us*/
++					odm_set_bb_reg(dm, 0x19e4,
++						       0xff000000, 2);
++					/*th2 = 3*0.4us, th3 = 4*0.4us
++					 *th4 = 7*0.4, th5 = 34*0.4
++					 */
++					odm_set_bb_reg(dm, 0x19e8,
++						       MASKDWORD, 0x22070403);
++
++					/*PRI hist th setting*/
++					/*th1=42*32us*/
++					odm_set_bb_reg(dm, 0x19b8,
++						       0x00007f80, 42);
++					/*th2=47*32us, th3=115*32us,
++					 *th4=123*32us, th5=130*32us
++					 */
++					odm_set_bb_reg(dm, 0x19ec,
++						       MASKDWORD, 0x827b732f);
++				} else {
++					/*pulse width hist th setting*/
++					/*th1=2*04us*/
++					odm_set_bb_reg(dm, 0x19e4,
++						       0xff000000, 1);
++					/*th2 = 13*0.4us, th3 = 26*0.4us
++					 *th4 = 75*0.4us, th5 = 255*0.4us
++					 */
++					odm_set_bb_reg(dm, 0x19e8,
++						       MASKDWORD, 0xff4b1a0d);
++					/*PRI hist th setting*/
++					/*th1=4*32us*/
++
++					odm_set_bb_reg(dm, 0x19b8,
++						       0x00007f80, 4);
++					/*th2=8*32us, th3=16*32us,
++					 *th4=32*32us, th5=128*32=4096us
++					 */
++					odm_set_bb_reg(dm, 0x19ec,
++						       MASKDWORD, 0x80201008);
++				}
++			}
++			/*@ETSI*/
++			else if (region_domain == 3) {
++				/*pulse width hist th setting*/
++				/*th1=2*04us*/
++				odm_set_bb_reg(dm, 0x19e4, 0xff000000, 1);
++				odm_set_bb_reg(dm, 0x19e8,
++					       MASKDWORD, 0x68260d06);
++				/*PRI hist th setting*/
++				/*th1=7*32us*/
++				odm_set_bb_reg(dm, 0x19b8, 0x00007f80, 7);
++				/*th2=40*32us, th3=80*32us,
++				 *th4=110*32us, th5=157*32=5024
++				 */
++				odm_set_bb_reg(dm, 0x19ec,
++					       MASKDWORD, 0xc06e2010);
++			}
++			/*@FCC*/
++			else if (region_domain == 1) {
++				/*pulse width hist th setting*/
++				/*th1=2*04us*/
++				odm_set_bb_reg(dm, 0x19e4, 0xff000000, 2);
++				/*th2 = 13*0.4us, th3 = 26*0.4us,
++				 *th4 = 75*0.4us, th5 = 255*0.4us
++				 */
++				odm_set_bb_reg(dm, 0x19e8,
++					       MASKDWORD, 0xff4b1a0d);
++
++				/*PRI hist th setting*/
++				/*th1=4*32us*/
++				odm_set_bb_reg(dm, 0x19b8, 0x00007f80, 4);
++				/*th2=8*32us, th3=21*32us,
++				 *th4=32*32us, th5=96*32=3072
++				 */
++				if (band_width == CHANNEL_WIDTH_20)
++					odm_set_bb_reg(dm, 0x19ec,
++						       MASKDWORD, 0x60282010);
++				else
++					odm_set_bb_reg(dm, 0x19ec,
++						       MASKDWORD, 0x60282420);
++			} else {
++			}
++		}
++	} else if (dm->support_ic_type &
++		   ODM_IC_JGR3_SERIES) {
++		if (dm->radar_detect_dbg_parm_en) {
++			phydm_radar_detect_with_dbg_parm(dm);
++			enable = 1;
++			goto exit;
++		}
++		if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
++			odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd);
++			if (dm->support_ic_type & (ODM_RTL8814B)) {
++				if (dm->seg1_dfs_flag == 1)
++					odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
++			}
++			odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd);
++			odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);
++			odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345);
++			odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003);
++			odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8);
++		} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
++			odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd);
++			if (dm->support_ic_type & (ODM_RTL8814B)) {
++				if (dm->seg1_dfs_flag == 1)
++					odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
++			}
++			odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd);
++			odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);
++			odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345);
++			odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003);
++			odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8);
++		} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
++			odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd);
++			if (dm->support_ic_type & (ODM_RTL8814B)) {
++				if (dm->seg1_dfs_flag == 1)
++					odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
++			}
++			odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd);
++			odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);
++			odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345);
++			odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003);
++			odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8);
++		} else {
++			/* not supported */
++			PHYDM_DBG(dm, DBG_DFS,
++				  "Unsupported dfs_region_domain:%d\n",
++				  region_domain);
++			goto exit;
++		}
++	#if (RTL8721D_SUPPORT)
++	} else if (dm->support_ic_type & ODM_RTL8721D) {
++		odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);
++		/*CCA MASK*/
++		odm_set_bb_reg(dm, R_0xc38, 0x07c00000, 0x06);
++		/*CCA Threshold*/
++		odm_set_bb_reg(dm, R_0xc3c, 0x00000007, 0x0);
++
++		if (dm->radar_detect_dbg_parm_en) {
++			phydm_radar_detect_with_dbg_parm(dm);
++			enable = 1;
++			goto exit;
++		}
++
++		if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
++			odm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8);
++			odm_set_bb_reg(dm, R_0xf58, MASKDWORD, 0x354cd7dd);
++			odm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab25);
++			odm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fab98);
++			odm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc45029f);
++
++		} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
++			odm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8);
++			odm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab25);
++			odm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fb398);
++			odm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc450e9d);
++
++			if (c_channel >= 52 && c_channel <= 64) {
++				odm_set_bb_reg(dm, R_0xf58, MASKDWORD,
++					       0x354cd7fd);
++			} else {
++				odm_set_bb_reg(dm, R_0xf58, MASKDWORD,
++					       0x354cd7bd);
++			}
++		} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
++			odm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8);
++			odm_set_bb_reg(dm, R_0xf58, MASKDWORD, 0x3558d7bd);
++			odm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab35);
++			odm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fb398);
++			odm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc444e9d);
++		} else {
++			/* not supported */
++			PHYDM_DBG(dm, DBG_DFS,
++				  "Unsupported dfs_region_domain:%d\n",
++				  region_domain);
++			goto exit;
++		}
++
++		/*if peak index -1~+1, use original NB method*/
++		odm_set_bb_reg(dm, R_0xf70, 0x00070000, 0x7);
++		odm_set_bb_reg(dm, R_0xf74, 0x000c0000, 0);
++
++		/*Turn off dfs scaling factor*/
++		odm_set_bb_reg(dm, R_0xf70, 0x00080000, 0x0);
++		/*NonDC peak_th = 2times DC peak_th*/
++		odm_set_bb_reg(dm, R_0xf58, 0x00007800, 1);
++
++		/*low pulse width radar pattern will cause wrong drop*/
++		/*disable peak index should the same*/
++		/*during the same short pulse (new mechan)*/
++		odm_set_bb_reg(dm, R_0xf70, 0x00100000, 0x0);
++		/*if peak index diff >=2, then drop the result*/
++		odm_set_bb_reg(dm, R_0xf70, 0x30000000, 0x2);
++	#endif
++	} else {
++		/*not supported IC type*/
++		PHYDM_DBG(dm, DBG_DFS, "Unsupported IC type:%d\n",
++			  dm->support_ic_type);
++		goto exit;
++	}
++
++	enable = 1;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00007f00);
++		dfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0xa50, 0x000000f0);
++		dfs->peak_th = (u8)odm_get_bb_reg(dm, R_0xa48, 0x00c00000);
++		dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xa50,
++							     0x00f00000);
++		dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xa4c,
++							    0xf0000000);
++		dfs->peak_window = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00030000);
++		dfs->three_peak_opt = (u8)odm_get_bb_reg(dm, R_0xa40,
++							 0x30000000);
++		dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm, R_0xa44,
++							 0x00000007);
++	#if (RTL8721D_SUPPORT)
++	} else if (dm->support_ic_type & (ODM_RTL8721D)) {
++		dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xf54,
++						     0x0000001f) << 2);
++		dfs->st_l2h_cur += (u8)odm_get_bb_reg(dm, R_0xf58, 0xc0000000);
++		dfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0xf70, 0x03c00000);
++		dfs->peak_th = (u8)odm_get_bb_reg(dm, R_0xf5c, 0x00000030);
++		dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xf70,
++							     0x00007800);
++		dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xf74,
++							    0x0000000f);
++		dfs->peak_window = (u8)odm_get_bb_reg(dm, R_0xf58, 0x18000000);
++		dfs->three_peak_opt = (u8)odm_get_bb_reg(dm, R_0xf58,
++							 0x00030000);
++		dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm,
++							 R_0xf58, 0x00007c00);
++	#endif
++	} else {
++		dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0x91c, 0x000000ff);
++		dfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0x918, 0x00001f00);
++		dfs->peak_th = (u8)odm_get_bb_reg(dm, R_0x918, 0x00030000);
++		dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0x920,
++							     0x000f0000);
++		dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0x920,
++							    0x00f00000);
++		dfs->peak_window = (u8)odm_get_bb_reg(dm, R_0x920, 0x00000300);
++		dfs->three_peak_opt = (u8)odm_get_bb_reg(dm, 0x924, 0x00000180);
++		dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm, 0x924, 0x00007000);
++	}
++
++		phydm_dfs_parameter_init(dm);
++
++exit:
++	if (enable) {
++		phydm_radar_detect_reset(dm);
++		PHYDM_DBG(dm, DBG_DFS, "on cch:%u, bw:%u\n", c_channel,
++			  band_width);
++	} else
++		phydm_radar_detect_disable(dm);
++}
++
++void phydm_dfs_parameter_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _DFS_STATISTICS *dfs = &dm->dfs;
++
++	u8 i;
++	for (i = 0; i < 5; i++) {
++		dfs->pulse_flag_hist[i] = 0;
++		dfs->pulse_type_hist[i] = 0;
++		dfs->radar_det_mask_hist[i] = 0;
++		dfs->fa_inc_hist[i] = 0;
++	}
++
++	/*@for dfs mode*/
++	dfs->force_TP_mode = 0;
++	dfs->sw_trigger_mode = 0;
++	dfs->det_print = 0;
++	dfs->det_print2 = 0;
++	dfs->print_hist_rpt = 0;
++	if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
++		dfs->hist_cond_on = 1;
++	else
++		dfs->hist_cond_on = 0;
++
++	/*@for dynamic dfs*/
++	dfs->pwdb_th = 8;
++	dfs->fa_mask_th = 30 * (dfs->dfs_polling_time / 100);
++	dfs->st_l2h_min = 0x20;
++	dfs->st_l2h_max = 0x4e;
++	dfs->pwdb_scalar_factor = 12;
++
++	/*@for dfs histogram*/
++	dfs->pri_hist_th = 5;
++	dfs->pri_sum_g1_th = 9;
++	dfs->pri_sum_g5_th = 5;
++	dfs->pri_sum_g1_fcc_th = 4;		/*@FCC Type6*/
++	dfs->pri_sum_g3_fcc_th = 6;
++	dfs->pri_sum_safe_th = 50;
++	dfs->pri_sum_safe_fcc_th = 110;		/*@30 for AP*/
++	dfs->pri_sum_type4_th = 16;
++	dfs->pri_sum_type6_th = 12;
++	dfs->pri_sum_g5_under_g1_th = 4;
++	dfs->pri_pw_diff_th = 4;
++	dfs->pri_pw_diff_fcc_th = 8;
++	dfs->pri_pw_diff_fcc_idle_th = 2;
++	dfs->pri_pw_diff_w53_th = 10;
++	dfs->pw_std_th = 7;			/*@FCC Type4*/
++	dfs->pw_std_idle_th = 10;
++	dfs->pri_std_th = 6;			/*@FCC Type3,4,6*/
++	dfs->pri_std_idle_th = 10;
++	dfs->pri_type1_upp_fcc_th = 110;
++	dfs->pri_type1_low_fcc_th = 50;
++	dfs->pri_type1_cen_fcc_th = 70;
++	dfs->pw_g0_th = 8;
++	dfs->pw_long_lower_th = 6;		/*@7->6*/
++	dfs->pri_long_upper_th = 30;
++	dfs->pw_long_lower_20m_th = 7;		/*@7 for AP*/
++	dfs->pw_long_sum_upper_th = 60;
++	dfs->type4_pw_max_cnt = 7;
++	dfs->type4_safe_pri_sum_th = 5;
++}
++
++void phydm_dfs_dynamic_setting(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _DFS_STATISTICS *dfs = &dm->dfs;
++
++	u8 peak_th_cur = 0, short_pulse_cnt_th_cur = 0;
++	u8 long_pulse_cnt_th_cur = 0, three_peak_opt_cur = 0;
++	u8 three_peak_th2_cur = 0;
++	u8 peak_window_cur = 0;
++	u8 region_domain = dm->dfs_region_domain;
++	u8 c_channel = *dm->channel;
++
++	if (dm->rx_tp + dm->tx_tp <= 2) {
++		dfs->idle_mode = 1;
++		if (dfs->force_TP_mode)
++			dfs->idle_mode = 0;
++	} else {
++		dfs->idle_mode = 0;
++	}
++
++	if (dfs->idle_mode == 1) { /*@idle (no traffic)*/
++		peak_th_cur = 3;
++		short_pulse_cnt_th_cur = 6;
++		long_pulse_cnt_th_cur = 9;
++		peak_window_cur = 2;
++		three_peak_opt_cur = 0;
++		three_peak_th2_cur = 2;
++		if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
++			if (c_channel >= 52 && c_channel <= 64) {
++				short_pulse_cnt_th_cur = 14;
++				long_pulse_cnt_th_cur = 15;
++				three_peak_th2_cur = 0;
++			} else {
++				short_pulse_cnt_th_cur = 6;
++				three_peak_th2_cur = 0;
++				long_pulse_cnt_th_cur = 10;
++			}
++		} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
++			three_peak_th2_cur = 0;
++		} else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
++			long_pulse_cnt_th_cur = 15;
++			if (phydm_dfs_is_meteorology_channel(dm)) {
++			/*need to add check cac end condition*/
++				peak_th_cur = 2;
++				three_peak_opt_cur = 0;
++				three_peak_th2_cur = 0;
++				short_pulse_cnt_th_cur = 7;
++			} else {
++				three_peak_opt_cur = 0;
++				three_peak_th2_cur = 0;
++				short_pulse_cnt_th_cur = 7;
++			}
++		} else /*@default: FCC*/
++			three_peak_th2_cur = 0;
++
++	} else { /*@in service (with TP)*/
++		peak_th_cur = 2;
++		short_pulse_cnt_th_cur = 6;
++		long_pulse_cnt_th_cur = 7;
++		peak_window_cur = 2;
++		three_peak_opt_cur = 0;
++		three_peak_th2_cur = 2;
++		if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
++			if (c_channel >= 52 && c_channel <= 64) {
++				long_pulse_cnt_th_cur = 15;
++				/*@for high duty cycle*/
++				short_pulse_cnt_th_cur = 5;
++				three_peak_th2_cur = 0;
++			} else {
++				three_peak_opt_cur = 0;
++				three_peak_th2_cur = 0;
++				long_pulse_cnt_th_cur = 8;
++			}
++		} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
++			long_pulse_cnt_th_cur = 5;	/*for 80M FCC*/
++			short_pulse_cnt_th_cur = 5;	/*for 80M FCC*/
++		} else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
++			long_pulse_cnt_th_cur = 15;
++			short_pulse_cnt_th_cur = 5;
++			three_peak_opt_cur = 0;
++		}
++	}
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		if (dfs->peak_th != peak_th_cur)
++			odm_set_bb_reg(dm, R_0xa48, 0x00c00000, peak_th_cur);
++		if (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur)
++			odm_set_bb_reg(dm, R_0xa50, 0x00f00000,
++				       short_pulse_cnt_th_cur);
++		if (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur)
++			odm_set_bb_reg(dm, R_0xa4c, 0xf0000000,
++				       long_pulse_cnt_th_cur);
++		if (dfs->peak_window != peak_window_cur)
++			odm_set_bb_reg(dm, R_0xa40, 0x00030000,
++				       peak_window_cur);
++		if (dfs->three_peak_opt != three_peak_opt_cur)
++			odm_set_bb_reg(dm, R_0xa40, 0x30000000,
++				       three_peak_opt_cur);
++		if (dfs->three_peak_th2 != three_peak_th2_cur)
++			odm_set_bb_reg(dm, R_0xa44, 0x00000007,
++				       three_peak_th2_cur);
++	#if (RTL8721D_SUPPORT)
++	} else if (dm->support_ic_type & (ODM_RTL8721D)) {
++		if (dfs->peak_th != peak_th_cur)
++			odm_set_bb_reg(dm, R_0xf5c, 0x00000030, peak_th_cur);
++		if (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur)
++			odm_set_bb_reg(dm, R_0xf70, 0x00007800,
++				       short_pulse_cnt_th_cur);
++		if (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur)
++			odm_set_bb_reg(dm, R_0xf74, 0x0000000f,
++				       long_pulse_cnt_th_cur);
++		if (dfs->peak_window != peak_window_cur)
++			odm_set_bb_reg(dm, R_0xf58, 0x18000000,
++				       peak_window_cur);
++		if (dfs->three_peak_opt != three_peak_opt_cur)
++			odm_set_bb_reg(dm, R_0xf58, 0x00030000,
++				       three_peak_opt_cur);
++		if (dfs->three_peak_th2 != three_peak_th2_cur)
++			odm_set_bb_reg(dm, R_0xf58, 0x00007c00,
++				       three_peak_th2_cur);
++	#endif
++	} else {
++		if (dfs->peak_th != peak_th_cur)
++			odm_set_bb_reg(dm, R_0x918, 0x00030000, peak_th_cur);
++		if (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur)
++			odm_set_bb_reg(dm, R_0x920, 0x000f0000,
++				       short_pulse_cnt_th_cur);
++		if (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur)
++			odm_set_bb_reg(dm, R_0x920, 0x00f00000,
++				       long_pulse_cnt_th_cur);
++		if (dfs->peak_window != peak_window_cur)
++			odm_set_bb_reg(dm, R_0x920, 0x00000300,
++				       peak_window_cur);
++		if (dfs->three_peak_opt != three_peak_opt_cur)
++			odm_set_bb_reg(dm, R_0x924, 0x00000180,
++				       three_peak_opt_cur);
++		if (dfs->three_peak_th2 != three_peak_th2_cur)
++			odm_set_bb_reg(dm, R_0x924, 0x00007000,
++				       three_peak_th2_cur);
++	}
++
++	dfs->peak_th = peak_th_cur;
++	dfs->short_pulse_cnt_th = short_pulse_cnt_th_cur;
++	dfs->long_pulse_cnt_th = long_pulse_cnt_th_cur;
++	dfs->peak_window = peak_window_cur;
++	dfs->three_peak_opt = three_peak_opt_cur;
++	dfs->three_peak_th2 = three_peak_th2_cur;
++}
++
++boolean
++phydm_radar_detect_dm_check(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _DFS_STATISTICS *dfs = &dm->dfs;
++	u8 region_domain = dm->dfs_region_domain, index = 0;
++
++	u16 i = 0, j = 0, fa_count_cur = 0, fa_count_inc = 0;
++	u16 total_fa_in_hist = 0, total_pulse_count_inc = 0;
++	u16 short_pulse_cnt_inc = 0, short_pulse_cnt_cur = 0;
++	u16 long_pulse_cnt_inc = 0, long_pulse_cnt_cur = 0;
++	u32 regf98_value = 0, reg918_value = 0, reg91c_value = 0;
++	u32 reg920_value = 0, reg924_value = 0, radar_rpt_reg_value = 0;
++	u32 regf54_value = 0, regf58_value = 0, regf5c_value = 0;
++	u32 regdf4_value = 0, regf70_value = 0, regf74_value = 0;
++	#if (RTL8812F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT)
++	u32 rega40_value = 0, rega44_value = 0, rega48_value = 0;
++	u32 rega4c_value = 0, rega50_value = 0, rega54_value = 0;
++	#endif
++	#if (RTL8721D_SUPPORT)
++	u32 reg908_value = 0, regdf4_value = 0;
++	u32 regf54_value = 0, regf58_value = 0, regf5c_value = 0;
++	u32 regf70_value = 0, regf74_value = 0;
++	#endif
++	boolean tri_short_pulse = 0, tri_long_pulse = 0, radar_type = 0;
++	boolean fault_flag_det = 0, fault_flag_psd = 0, fa_flag = 0;
++	boolean radar_detected = 0;
++	u8 st_l2h_new = 0, fa_mask_th = 0, k = 0, sum = 0;
++	u8 c_channel = *dm->channel;
++
++	/*@Get FA count during past 100ms, R_0xf48 for AC series*/
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		fa_count_cur = (u16)odm_get_bb_reg(dm, R_0x2d00, MASKLWORD);
++	#if (RTL8721D_SUPPORT)
++	else if (dm->support_ic_type & (ODM_RTL8721D)) {
++		fa_count_cur = (u16)odm_get_bb_reg(dm,
++						   ODM_REG_OFDM_FA_TYPE2_11N,
++						   MASKHWORD);
++		fa_count_cur += (u16)odm_get_bb_reg(dm,
++						    ODM_REG_OFDM_FA_TYPE3_11N,
++						    MASKLWORD);
++		fa_count_cur += (u16)odm_get_bb_reg(dm,
++						    ODM_REG_OFDM_FA_TYPE3_11N,
++						    MASKHWORD);
++		fa_count_cur += (u16)odm_get_bb_reg(dm,
++						    ODM_REG_OFDM_FA_TYPE4_11N,
++						    MASKLWORD);
++		fa_count_cur += (u16)odm_get_bb_reg(dm,
++						    ODM_REG_OFDM_FA_TYPE1_11N,
++						    MASKLWORD);
++		fa_count_cur += (u16)odm_get_bb_reg(dm,
++						    ODM_REG_OFDM_FA_TYPE1_11N,
++						    MASKHWORD);
++	}
++	#endif
++	else
++		fa_count_cur = (u16)odm_get_bb_reg(dm, R_0xf48, 0x0000ffff);
++
++	if (dfs->fa_count_pre == 0)
++		fa_count_inc = 0;
++	else if (fa_count_cur >= dfs->fa_count_pre)
++		fa_count_inc = fa_count_cur - dfs->fa_count_pre;
++	else
++		fa_count_inc = fa_count_cur;
++	dfs->fa_count_pre = fa_count_cur;
++
++	dfs->fa_inc_hist[dfs->mask_idx] = fa_count_inc;
++
++	for (i = 0; i < 5; i++)
++		total_fa_in_hist = total_fa_in_hist + dfs->fa_inc_hist[i];
++
++	if (dfs->mask_idx >= 2)
++		index = dfs->mask_idx - 2;
++	else
++		index = 5 + dfs->mask_idx - 2;
++
++	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
++				   ODM_RTL8197G)) {
++		radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e00, 0xffffffff);
++		short_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x000ff800)
++					    >> 11);
++		long_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x0fc00000)
++					    >> 22);
++	#if (RTL8721D_SUPPORT)
++	} else if (dm->support_ic_type & (ODM_RTL8721D)) {
++		reg908_value = (u32)odm_get_bb_reg(dm, R_0x908, MASKDWORD);
++		odm_set_bb_reg(dm, R_0x908, MASKDWORD, 0x254);
++		regdf4_value = odm_get_bb_reg(dm, R_0xdf4, MASKDWORD);
++		short_pulse_cnt_cur = (u16)((regdf4_value & 0x000ff000) >> 12);
++		long_pulse_cnt_cur = (u16)((regdf4_value & 0x0fc00000) >> 22);
++
++		tri_short_pulse = (regdf4_value & BIT(20)) ? 1 : 0;
++		tri_long_pulse = (regdf4_value & BIT(28)) ? 1 : 0;
++		if (tri_short_pulse || tri_long_pulse) {
++			odm_set_bb_reg(dm, R_0xf58, BIT(29), 0);
++			odm_set_bb_reg(dm, R_0xf58, BIT(29), 1);
++		}
++	#endif
++	} else if (dm->support_ic_type & (ODM_RTL8814B)) {
++		if (dm->seg1_dfs_flag == 1)
++			radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e20,
++							     0xffffffff);
++		else
++			radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e00,
++							     0xffffffff);
++		short_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x000ff800)
++					    >> 11);
++		long_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x0fc00000)
++					    >> 22);
++	} else {
++		regf98_value = odm_get_bb_reg(dm, R_0xf98, 0xffffffff);
++		short_pulse_cnt_cur = (u16)(regf98_value & 0x000000ff);
++		long_pulse_cnt_cur = (u16)((regf98_value & 0x0000ff00) >> 8);
++	}
++
++	/*@Get short pulse count, need carefully handle the counter overflow*/
++	if (short_pulse_cnt_cur >= dfs->short_pulse_cnt_pre) {
++		short_pulse_cnt_inc = short_pulse_cnt_cur -
++				      dfs->short_pulse_cnt_pre;
++	} else {
++		short_pulse_cnt_inc = short_pulse_cnt_cur;
++	}
++	dfs->short_pulse_cnt_pre = short_pulse_cnt_cur;
++
++	/*@Get long pulse count, need carefully handle the counter overflow*/
++	if (long_pulse_cnt_cur >= dfs->long_pulse_cnt_pre) {
++		long_pulse_cnt_inc = long_pulse_cnt_cur -
++				     dfs->long_pulse_cnt_pre;
++	} else {
++		long_pulse_cnt_inc = long_pulse_cnt_cur;
++	}
++	dfs->long_pulse_cnt_pre = long_pulse_cnt_cur;
++
++	total_pulse_count_inc = short_pulse_cnt_inc + long_pulse_cnt_inc;
++
++	if (dfs->det_print) {
++		PHYDM_DBG(dm, DBG_DFS,
++			  "===============================================\n");
++		PHYDM_DBG(dm, DBG_DFS, "FA_count_inc[%d]\n", fa_count_inc);
++		if (dm->support_ic_type & (ODM_RTL8721D)) {
++			PHYDM_DBG(dm, DBG_DFS,
++				  "Init_Gain[%x] st_l2h_cur[%x] 0xdf4[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
++				  dfs->igi_cur, dfs->st_l2h_cur, regdf4_value,
++				  short_pulse_cnt_inc, long_pulse_cnt_inc);
++			regf54_value = odm_get_bb_reg(dm, R_0xf54, MASKDWORD);
++			regf58_value = odm_get_bb_reg(dm, R_0xf58, MASKDWORD);
++			regf5c_value = odm_get_bb_reg(dm, R_0xf5c, MASKDWORD);
++			regf70_value = odm_get_bb_reg(dm, R_0xf70, MASKDWORD);
++			regf74_value = odm_get_bb_reg(dm, R_0xf74, MASKDWORD);
++			PHYDM_DBG(dm, DBG_DFS,
++				  "0xf54[%08x] 0xf58[%08x] 0xf5c[%08x] 0xf70[%08x] 0xf74[%08x]\n",
++				  regf54_value, regf58_value, regf5c_value,
++				  regf70_value, regf74_value);
++		} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++			PHYDM_DBG(dm, DBG_DFS,
++				  "Init_Gain[%x] st_l2h_cur[%x] 0x2dbc[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
++				  dfs->igi_cur, dfs->st_l2h_cur,
++				  radar_rpt_reg_value, short_pulse_cnt_inc,
++				  long_pulse_cnt_inc);
++		#if (RTL8812F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT)
++			rega40_value = odm_get_bb_reg(dm, R_0xa40, MASKDWORD);
++			rega44_value = odm_get_bb_reg(dm, R_0xa44, MASKDWORD);
++			rega48_value = odm_get_bb_reg(dm, R_0xa48, MASKDWORD);
++			rega4c_value = odm_get_bb_reg(dm, R_0xa4c, MASKDWORD);
++			rega50_value = odm_get_bb_reg(dm, R_0xa50, MASKDWORD);
++			rega54_value = odm_get_bb_reg(dm, R_0xa54, MASKDWORD);
++			PHYDM_DBG(dm, DBG_DFS,
++				  "0xa40[%08x] 0xa44[%08x] 0xa48[%08x] 0xa4c[%08x] 0xa50[%08x] 0xa54[%08x]\n",
++				  rega40_value, rega44_value, rega48_value,
++				  rega4c_value, rega50_value, rega54_value);
++		#endif
++		} else {
++			PHYDM_DBG(dm, DBG_DFS,
++				  "Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
++				  dfs->igi_cur, dfs->st_l2h_cur, regf98_value,
++				  short_pulse_cnt_inc, long_pulse_cnt_inc);
++			reg918_value = odm_get_bb_reg(dm, R_0x918,
++						      0xffffffff);
++			reg91c_value = odm_get_bb_reg(dm, R_0x91c,
++						      0xffffffff);
++			reg920_value = odm_get_bb_reg(dm, R_0x920,
++						      0xffffffff);
++			reg924_value = odm_get_bb_reg(dm, R_0x924,
++						      0xffffffff);
++			PHYDM_DBG(dm, DBG_DFS,
++				  "0x918[%08x] 0x91c[%08x] 0x920[%08x] 0x924[%08x]\n",
++				  reg918_value, reg91c_value,
++				  reg920_value, reg924_value);
++		}
++		PHYDM_DBG(dm, DBG_DFS, "Throughput: %dMbps\n",
++			  (dm->rx_tp + dm->tx_tp));
++
++		PHYDM_DBG(dm, DBG_DFS,
++			  "dfs_regdomain = %d, dbg_mode = %d, idle_mode = %d, print_hist_rpt = %d, hist_cond_on = %d\n",
++			  region_domain, dfs->dbg_mode,
++			  dfs->idle_mode, dfs->print_hist_rpt,
++			  dfs->hist_cond_on);
++	}
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		tri_short_pulse = (radar_rpt_reg_value & BIT(20)) ? 1 : 0;
++		tri_long_pulse = (radar_rpt_reg_value & BIT(28)) ? 1 : 0;
++	} else {
++		tri_short_pulse = (regf98_value & BIT(17)) ? 1 : 0;
++		tri_long_pulse = (regf98_value & BIT(19)) ? 1 : 0;
++	}
++
++	if (tri_short_pulse) {
++		phydm_radar_detect_reset(dm);
++	}
++	if (tri_long_pulse) {
++		phydm_radar_detect_reset(dm);
++		if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
++			if (c_channel >= 52 && c_channel <= 64) {
++				tri_long_pulse = 0;
++			}
++		}
++		if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
++			tri_long_pulse = 0;
++		}
++	}
++
++	st_l2h_new = dfs->st_l2h_cur;
++	dfs->pulse_flag_hist[dfs->mask_idx] = tri_short_pulse | tri_long_pulse;
++	dfs->pulse_type_hist[dfs->mask_idx] = (tri_long_pulse) ? 1 : 0;
++
++	/* PSD(not ready) */
++
++	fault_flag_det = 0;
++	fault_flag_psd = 0;
++	fa_flag = 0;
++	if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
++		fa_mask_th = dfs->fa_mask_th + 20;
++	} else {
++		fa_mask_th = dfs->fa_mask_th;
++	}
++	if (total_fa_in_hist >= fa_mask_th || dfs->igi_cur >= 0x30) {
++		/* st_l2h_new = dfs->st_l2h_max; */
++		dfs->radar_det_mask_hist[index] = 1;
++		if (dfs->pulse_flag_hist[index] == 1) {
++			dfs->pulse_flag_hist[index] = 0;
++			if (dfs->det_print2) {
++				PHYDM_DBG(dm, DBG_DFS,
++					  "Radar is masked : FA mask\n");
++			}
++		}
++		fa_flag = 1;
++	} else {
++		dfs->radar_det_mask_hist[index] = 0;
++	}
++
++	if (dfs->det_print) {
++		PHYDM_DBG(dm, DBG_DFS, "mask_idx: %d\n", dfs->mask_idx);
++		PHYDM_DBG(dm, DBG_DFS, "radar_det_mask_hist: ");
++		for (i = 0; i < 5; i++)
++			PHYDM_DBG(dm, DBG_DFS, "%d ",
++				  dfs->radar_det_mask_hist[i]);
++		PHYDM_DBG(dm, DBG_DFS, "pulse_flag_hist: ");
++		for (i = 0; i < 5; i++)
++			PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->pulse_flag_hist[i]);
++		PHYDM_DBG(dm, DBG_DFS, "fa_inc_hist: ");
++		for (i = 0; i < 5; i++)
++			PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->fa_inc_hist[i]);
++		PHYDM_DBG(dm, DBG_DFS,
++			  "\nfa_mask_th: %d, total_fa_in_hist: %d ",
++			  fa_mask_th, total_fa_in_hist);
++	}
++
++	sum = 0;
++	for (k = 0; k < 5; k++) {
++		if (dfs->radar_det_mask_hist[k] == 1)
++			sum++;
++	}
++
++	if (dfs->mask_hist_checked <= 5)
++		dfs->mask_hist_checked++;
++
++	if (dfs->mask_hist_checked >= 5 && dfs->pulse_flag_hist[index]) {
++		if (sum <= 2) {
++			if (dfs->hist_cond_on) {
++				/*return the value from hist_radar_detected*/
++				radar_detected = phydm_dfs_hist_log(dm, index);
++			} else {
++				if (dfs->pulse_type_hist[index] == 0)
++					dfs->radar_type = 0;
++				else if (dfs->pulse_type_hist[index] == 1)
++					dfs->radar_type = 1;
++				radar_detected = 1;
++				PHYDM_DBG(dm, DBG_DFS,
++					  "Detected type %d radar signal!\n",
++					  dfs->radar_type);
++			}
++		} else {
++			fault_flag_det = 1;
++			if (dfs->det_print2) {
++				PHYDM_DBG(dm, DBG_DFS,
++					  "Radar is masked : mask_hist large than thd\n");
++			}
++		}
++	}
++
++	dfs->mask_idx++;
++	if (dfs->mask_idx == 5)
++		dfs->mask_idx = 0;
++
++	if (fault_flag_det == 0 && fault_flag_psd == 0 && fa_flag == 0) {
++		if (dfs->igi_cur < 0x30) {
++			st_l2h_new = dfs->st_l2h_min;
++		}
++	}
++
++	if (st_l2h_new != dfs->st_l2h_cur) {
++		if (st_l2h_new < dfs->st_l2h_min) {
++			dfs->st_l2h_cur = dfs->st_l2h_min;
++		} else if (st_l2h_new > dfs->st_l2h_max)
++			dfs->st_l2h_cur = dfs->st_l2h_max;
++		else
++			dfs->st_l2h_cur = st_l2h_new;
++		/*odm_set_bb_reg(dm, R_0x91c, 0xff, dfs->st_l2h_cur);*/
++
++		dfs->pwdb_th_cur = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur)
++				    / 2 + dfs->pwdb_scalar_factor;
++
++		/*@limit the pwdb value to absolute lower bound 8*/
++		dfs->pwdb_th_cur = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th);
++
++		/*@limit the pwdb value to absolute upper bound 0x1f*/
++		dfs->pwdb_th_cur = MIN_2(dfs->pwdb_th_cur, 0x1f);
++
++		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++			odm_set_bb_reg(dm, R_0xa50, 0x000000f0,
++				       dfs->pwdb_th_cur);
++		#if (RTL8721D_SUPPORT)
++		else if (dm->support_ic_type & ODM_RTL8721D) {
++			odm_set_bb_reg(dm, R_0xf54, 0x0000001f,
++				       ((dfs->st_l2h_cur & 0x0000007c) >> 2));
++			odm_set_bb_reg(dm, R_0xf58, 0xc0000000,
++				       (dfs->st_l2h_cur & 0x00000003));
++			odm_set_bb_reg(dm, R_0xf70, 0x03c00000,
++				       dfs->pwdb_th_cur);
++		}
++		#endif
++		else
++			odm_set_bb_reg(dm, R_0x918, 0x00001f00,
++				       dfs->pwdb_th_cur);
++	}
++
++	if (dfs->det_print) {
++		PHYDM_DBG(dm, DBG_DFS,
++			  "fault_flag_det[%d], fault_flag_psd[%d], DFS_detected [%d]\n",
++			  fault_flag_det, fault_flag_psd, radar_detected);
++	}
++	#if (RTL8721D_SUPPORT)
++	if (dm->support_ic_type & (ODM_RTL8721D))
++		odm_set_bb_reg(dm, R_0x908, MASKDWORD, reg908_value);
++	#endif
++
++	return radar_detected;
++}
++
++#if (RTL8814A_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT)
++void phydm_dfs_histogram_radar_distinguish(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _DFS_STATISTICS *dfs = &dm->dfs;
++	u8 region_domain = dm->dfs_region_domain;
++	u8 c_channel = *dm->channel;
++	u8 band_width = *dm->band_width;
++
++	u8 dfs_pw_thd1 = 0, dfs_pw_thd2 = 0, dfs_pw_thd3 = 0;
++	u8 dfs_pw_thd4 = 0, dfs_pw_thd5 = 0;
++	u8 dfs_pri_thd1 = 0, dfs_pri_thd2 = 0, dfs_pri_thd3 = 0;
++	u8 dfs_pri_thd4 = 0, dfs_pri_thd5 = 0;
++	u8 pri_th = 0, i = 0;
++	u8 max_pri_idx = 0, max_pw_idx = 0, max_pri_cnt_th = 0;
++	u8 max_pri_cnt_fcc_g1_th = 0, max_pri_cnt_fcc_g3_th = 0;
++	u8 safe_pri_pw_diff_th = 0, safe_pri_pw_diff_fcc_th = 0;
++	u8 safe_pri_pw_diff_w53_th = 0, safe_pri_pw_diff_fcc_idle_th = 0;
++	u8 j = 0;
++	u32 dfs_hist1_pw = 0, dfs_hist2_pw = 0, g_pw[6] = {0};
++	u32 dfs_hist1_pri = 0, dfs_hist2_pri = 0, g_pri[6] = {0};
++	u8 pw_sum_g0g5 = 0, pw_sum_g1g2g3g4 = 0;
++	u8 pri_sum_g0g5 = 0, pri_sum_g1g2g3g4 = 0;
++	u16 pw_sum_ss_g1g2g3g4 = 0, pri_sum_ss_g1g2g3g4 = 0;
++	u8 max_pri_cnt = 0, max_pw_cnt = 0;
++	#if (RTL8721D_SUPPORT)
++	if (dm->support_ic_type & (ODM_RTL8721D))
++		return;
++	#endif
++
++	/*read pulse width hist report*/
++	odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x1);
++	dfs_hist1_pw = odm_get_bb_reg(dm, 0xf5c, 0xffffffff);
++	dfs_hist2_pw = odm_get_bb_reg(dm, 0xf74, 0xffffffff);
++
++	g_pw[0] = (unsigned int)((dfs_hist2_pw & 0xff000000) >> 24);
++	g_pw[1] = (unsigned int)((dfs_hist2_pw & 0x00ff0000) >> 16);
++	g_pw[2] = (unsigned int)((dfs_hist2_pw & 0x0000ff00) >> 8);
++	g_pw[3] = (unsigned int)dfs_hist2_pw & 0x000000ff;
++	g_pw[4] = (unsigned int)((dfs_hist1_pw & 0xff000000) >> 24);
++	g_pw[5] = (unsigned int)((dfs_hist1_pw & 0x00ff0000) >> 16);
++
++	/*read pulse repetition interval hist report*/
++	odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x3);
++	dfs_hist1_pri = odm_get_bb_reg(dm, 0xf5c, 0xffffffff);
++	dfs_hist2_pri = odm_get_bb_reg(dm, 0xf74, 0xffffffff);
++	odm_set_bb_reg(dm, 0x19b4, 0x10000000, 1); /*reset histo report*/
++	odm_set_bb_reg(dm, 0x19b4, 0x10000000, 0); /*@continue histo report*/
++
++	g_pri[0] = (unsigned int)((dfs_hist2_pri & 0xff000000) >> 24);
++	g_pri[1] = (unsigned int)((dfs_hist2_pri & 0x00ff0000) >> 16);
++	g_pri[2] = (unsigned int)((dfs_hist2_pri & 0x0000ff00) >> 8);
++	g_pri[3] = (unsigned int)dfs_hist2_pri & 0x000000ff;
++	g_pri[4] = (unsigned int)((dfs_hist1_pri & 0xff000000) >> 24);
++	g_pri[5] = (unsigned int)((dfs_hist1_pri & 0x00ff0000) >> 16);
++
++	dfs->pri_cond1 = 0;
++	dfs->pri_cond2 = 0;
++	dfs->pri_cond3 = 0;
++	dfs->pri_cond4 = 0;
++	dfs->pri_cond5 = 0;
++	dfs->pw_cond1 = 0;
++	dfs->pw_cond2 = 0;
++	dfs->pw_cond3 = 0;
++	dfs->pri_type3_4_cond1 = 0;	/*@for ETSI*/
++	dfs->pri_type3_4_cond2 = 0;	/*@for ETSI*/
++	dfs->pw_long_cond1 = 0;		/*@for long radar*/
++	dfs->pw_long_cond2 = 0;		/*@for long radar*/
++	dfs->pri_long_cond1 = 0;	/*@for long radar*/
++	dfs->pw_flag = 0;
++	dfs->pri_flag = 0;
++	dfs->pri_type3_4_flag = 0;	/*@for ETSI*/
++	dfs->long_radar_flag = 0;
++	dfs->pw_std = 0;	/*The std(var) of reasonable num of pw group*/
++	dfs->pri_std = 0;	/*The std(var) of reasonable num of pri group*/
++
++	for (i = 0; i < 6; i++) {
++		dfs->pw_hold_sum[i] = 0;
++		dfs->pri_hold_sum[i] = 0;
++	}
++
++	if (dfs->idle_mode == 1)
++		pri_th = dfs->pri_hist_th;
++	else
++		pri_th = dfs->pri_hist_th - 1;
++
++	for (i = 0; i < 6; i++) {
++		dfs->pw_hold[dfs->hist_idx][i] = (u8)g_pw[i];
++		dfs->pri_hold[dfs->hist_idx][i] = (u8)g_pri[i];
++		/*@collect whole histogram report may take some time
++		 *so we add the counter of 2 time slots in FCC and ETSI
++		 */
++		dfs->pw_hold_sum[i] = dfs->pw_hold_sum[i] +
++			dfs->pw_hold[(dfs->hist_idx + 1) % 3][i] +
++			dfs->pw_hold[(dfs->hist_idx + 2) % 3][i];
++		dfs->pri_hold_sum[i] = dfs->pri_hold_sum[i] +
++			dfs->pri_hold[(dfs->hist_idx + 1) % 3][i] +
++			dfs->pri_hold[(dfs->hist_idx + 2) % 3][i];
++	}
++	/*@For long radar type*/
++	for (j = 1; j < 4; j++) {
++		dfs->pw_long_hold_sum[i] = dfs->pw_long_hold_sum[i] +
++			dfs->pw_hold[(dfs->hist_long_idx + j) % 4][i];
++		dfs->pri_long_hold_sum[i] = dfs->pri_long_hold_sum[i] +
++			dfs->pri_hold[(dfs->hist_long_idx + j) % 4][i];
++	}
++
++	dfs->hist_idx++;
++	if (dfs->hist_idx == 3)
++		dfs->hist_idx = 0;
++	dfs->hist_long_idx++;
++	if (dfs->hist_long_idx == 4)
++		dfs->hist_long_idx = 0;
++
++	max_pri_cnt = 0;
++	max_pri_idx = 0;
++	max_pw_cnt = 0;
++	max_pw_idx = 0;
++	max_pri_cnt_th = dfs->pri_sum_g1_th;
++	max_pri_cnt_fcc_g1_th = dfs->pri_sum_g1_fcc_th;
++	max_pri_cnt_fcc_g3_th = dfs->pri_sum_g3_fcc_th;
++	safe_pri_pw_diff_th = dfs->pri_pw_diff_th;
++	safe_pri_pw_diff_fcc_th = dfs->pri_pw_diff_fcc_th;
++	safe_pri_pw_diff_fcc_idle_th = dfs->pri_pw_diff_fcc_idle_th;
++	safe_pri_pw_diff_w53_th = dfs->pri_pw_diff_w53_th;
++
++	/*@g1 to g4 is the reseasonable range of pri and pw*/
++	for (i = 1; i <= 4; i++) {
++		if (dfs->pri_hold_sum[i] > max_pri_cnt) {
++			max_pri_cnt = dfs->pri_hold_sum[i];
++			max_pri_idx = i;
++		}
++		if (dfs->pw_hold_sum[i] > max_pw_cnt) {
++			max_pw_cnt = dfs->pw_hold_sum[i];
++			max_pw_idx = i;
++		}
++		if (dfs->pri_hold_sum[i] >= pri_th)
++			dfs->pri_cond1 = 1;
++	}
++
++	pri_sum_g0g5 = dfs->pri_hold_sum[0];
++	if (pri_sum_g0g5 == 0)
++		pri_sum_g0g5 = 1;
++	pri_sum_g1g2g3g4 = dfs->pri_hold_sum[1] + dfs->pri_hold_sum[2]
++			 + dfs->pri_hold_sum[3] + dfs->pri_hold_sum[4];
++
++	/*pw will reduce because of dc, so we do not treat g0 as illegal group*/
++	pw_sum_g0g5 = dfs->pw_hold_sum[5];
++	if (pw_sum_g0g5 == 0)
++		pw_sum_g0g5 = 1;
++	pw_sum_g1g2g3g4 = dfs->pw_hold_sum[1] + dfs->pw_hold_sum[2] +
++				dfs->pw_hold_sum[3] + dfs->pw_hold_sum[4];
++
++	/*@Calculate the variation from g1 to g4*/
++	for (i = 1; i < 5; i++) {
++		/*Sum of square*/
++		pw_sum_ss_g1g2g3g4 = pw_sum_ss_g1g2g3g4 +
++		(dfs->pw_hold_sum[i] - (pw_sum_g1g2g3g4 / 4)) *
++		(dfs->pw_hold_sum[i] - (pw_sum_g1g2g3g4 / 4));
++		pri_sum_ss_g1g2g3g4 = pri_sum_ss_g1g2g3g4 +
++		(dfs->pri_hold_sum[i] - (pri_sum_g1g2g3g4 / 4)) *
++		(dfs->pri_hold_sum[i] - (pri_sum_g1g2g3g4 / 4));
++	}
++	/*The value may less than the normal variance,
++	 *since the variable type is int (not float)
++	 */
++		dfs->pw_std = (u8)(pw_sum_ss_g1g2g3g4 / 4);
++		dfs->pri_std = (u8)(pri_sum_ss_g1g2g3g4 / 4);
++
++	if (region_domain == 1) {
++		dfs->pri_type3_4_flag = 1;	/*@ETSI flag*/
++
++		/*(OTA) Cancel long PRI case*/
++		dfs->pri_cond2 = 1;
++
++		/*reasonable group shouldn't large*/
++		if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2 &&
++		    pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_fcc_th)
++			dfs->pri_cond3 = 1;
++
++		/*@Cancel the condition that the abs between pri and pw*/
++		if (dfs->pri_std >= dfs->pri_std_th)
++			dfs->pri_cond4 = 1;
++		else if (max_pri_idx == 1 &&
++			 max_pri_cnt >= max_pri_cnt_fcc_g1_th)
++			dfs->pri_cond4 = 1;
++
++		/*(OTA) Cancel the condition (type 3,4 distinction)*/
++		dfs->pri_cond5 = 1;
++
++		if (dfs->pri_cond1 && dfs->pri_cond2 && dfs->pri_cond3 &&
++		    dfs->pri_cond4 && dfs->pri_cond5)
++			dfs->pri_flag = 1;
++
++		/* PW judgment conditions for short radar type */
++		/*ratio of reasonable and illegal group && g5 should be zero*/
++		if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) &&
++		    (dfs->pw_hold_sum[5] <= 1))
++			dfs->pw_cond1 = 1;
++		/*unreasonable group*/
++		if (dfs->pw_hold_sum[4] == 0 && dfs->pw_hold_sum[5] == 0)
++			dfs->pw_cond2 = 1;
++		/*pw's std (short radar) should be large(=7)*/
++		if (dfs->pw_std >= dfs->pw_std_th)
++			dfs->pw_cond3 = 1;
++		if (dfs->pw_cond1 && dfs->pw_cond2 && dfs->pw_cond3)
++			dfs->pw_flag = 1;
++
++		/* @Judgment conditions of long radar type */
++		if (band_width == CHANNEL_WIDTH_20) {
++			if (dfs->pw_long_hold_sum[4] >=
++			    dfs->pw_long_lower_20m_th)
++				dfs->pw_long_cond1 = 1;
++		} else{
++			if (dfs->pw_long_hold_sum[4] >= dfs->pw_long_lower_th)
++				dfs->pw_long_cond1 = 1;
++		}
++		/* @Disable the condition that dfs->pw_long_hold_sum[1] */
++		if (dfs->pw_long_hold_sum[2] + dfs->pw_long_hold_sum[3] +
++		    dfs->pw_long_hold_sum[4] <= dfs->pw_long_sum_upper_th &&
++		    dfs->pw_long_hold_sum[2] <= dfs->pw_long_hold_sum[4] &&
++		    dfs->pw_long_hold_sum[3] <= dfs->pw_long_hold_sum[4])
++			dfs->pw_long_cond2 = 1;
++		/*@g4 should be large for long radar*/
++		if (dfs->pri_long_hold_sum[4] <= dfs->pri_long_upper_th)
++			dfs->pri_long_cond1 = 1;
++		if (dfs->pw_long_cond1 && dfs->pw_long_cond2 &&
++		    dfs->pri_long_cond1)
++			dfs->long_radar_flag = 1;
++	} else if (region_domain == 2) {
++		dfs->pri_type3_4_flag = 1;	/*@ETSI flag*/
++
++		/*PRI judgment conditions for short radar type*/
++		if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2)
++			dfs->pri_cond2 = 1;
++
++		/*reasonable group shouldn't too large*/
++		if (pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_fcc_th)
++			dfs->pri_cond3 = 1;
++
++		/*Cancel the abs diff between pri and pw for idle mode (thr=2)*/
++		dfs->pri_cond4 = 1;
++
++		if (dfs->idle_mode == 1) {
++			if (dfs->pri_std >= dfs->pri_std_idle_th) {
++				if (max_pw_idx == 3 &&
++				    pri_sum_g1g2g3g4 <= dfs->pri_sum_type4_th){
++		/*To distinguish between type 4 radar and false detection*/
++					dfs->pri_cond5 = 1;
++				} else if (max_pw_idx == 1 &&
++					   pri_sum_g1g2g3g4 >=
++					   dfs->pri_sum_type6_th) {
++		/*To distinguish between type 6 radar and false detection*/
++					dfs->pri_cond5 = 1;
++				} else {
++		/*pri variation of short radar should be large (idle mode)*/
++					dfs->pri_cond5 = 1;
++				}
++			}
++		} else {
++		/*pri variation of short radar should be large (TP mode)*/
++			if (dfs->pri_std >= dfs->pri_std_th)
++				dfs->pri_cond5 = 1;
++		}
++
++		if (dfs->pri_cond1 && dfs->pri_cond2 && dfs->pri_cond3 &&
++		    dfs->pri_cond4 && dfs->pri_cond5)
++			dfs->pri_flag = 1;
++
++		/* PW judgment conditions for short radar type */
++		if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) &&
++		    (dfs->pw_hold_sum[5] <= 1))
++		/*ratio of reasonable and illegal group && g5 should be zero*/
++			dfs->pw_cond1 = 1;
++
++		if ((c_channel >= 52) && (c_channel <= 64))
++			dfs->pw_cond2 = 1;
++		/*unreasonable group shouldn't too large*/
++		else if (dfs->pw_hold_sum[0] <= dfs->pw_g0_th)
++			dfs->pw_cond2 = 1;
++
++		if (dfs->idle_mode == 1) {
++		/*pw variation of short radar should be large (idle mode)*/
++			if (dfs->pw_std >= dfs->pw_std_idle_th)
++				dfs->pw_cond3 = 1;
++		} else {
++		/*pw variation of short radar should be large (TP mode)*/
++			if (dfs->pw_std >= dfs->pw_std_th)
++				dfs->pw_cond3 = 1;
++		}
++		if (dfs->pw_cond1 && dfs->pw_cond2 && dfs->pw_cond3)
++			dfs->pw_flag = 1;
++
++		/* @Judgment conditions of long radar type */
++		if (band_width == CHANNEL_WIDTH_20) {
++			if (dfs->pw_long_hold_sum[4] >=
++			    dfs->pw_long_lower_20m_th)
++				dfs->pw_long_cond1 = 1;
++		} else{
++			if (dfs->pw_long_hold_sum[4] >= dfs->pw_long_lower_th)
++				dfs->pw_long_cond1 = 1;
++		}
++		if (dfs->pw_long_hold_sum[1] + dfs->pw_long_hold_sum[2] +
++		    dfs->pw_long_hold_sum[3] + dfs->pw_long_hold_sum[4]
++		    <= dfs->pw_long_sum_upper_th)
++			dfs->pw_long_cond2 = 1;
++		/*@g4 should be large for long radar*/
++		if (dfs->pri_long_hold_sum[4] <= dfs->pri_long_upper_th)
++			dfs->pri_long_cond1 = 1;
++		if (dfs->pw_long_cond1 &&
++		    dfs->pw_long_cond2 && dfs->pri_long_cond1)
++			dfs->long_radar_flag = 1;
++	} else if (region_domain == 3) {
++		/*ratio of reasonable group and illegal group */
++		if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2)
++			dfs->pri_cond2 = 1;
++
++		if (pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_th)
++			dfs->pri_cond3 = 1;
++
++		/*@Cancel the condition that the abs between pri and pw*/
++			dfs->pri_cond4 = 1;
++
++		if (dfs->pri_hold_sum[5] <= dfs->pri_sum_g5_th)
++			dfs->pri_cond5 = 1;
++
++		if (band_width == CHANNEL_WIDTH_40) {
++			if (max_pw_idx == 4) {
++				if (max_pw_cnt >= dfs->type4_pw_max_cnt &&
++				    pri_sum_g1g2g3g4 >=
++				    dfs->type4_safe_pri_sum_th) {
++					dfs->pri_cond1 = 1;
++					dfs->pri_cond4 = 1;
++					dfs->pri_type3_4_cond1 = 1;
++				}
++			}
++		}
++
++		if (dfs->pri_cond1 && dfs->pri_cond2 &&
++		    dfs->pri_cond3 && dfs->pri_cond4 && dfs->pri_cond5)
++			dfs->pri_flag = 1;
++
++		if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2))
++			dfs->pw_flag = 1;
++
++		/*@max num pri group is g1 means radar type3 or type4*/
++		if (max_pri_idx == 1) {
++			if (max_pri_cnt >= max_pri_cnt_th)
++				dfs->pri_type3_4_cond1 = 1;
++			if (dfs->pri_hold_sum[4] <=
++			    dfs->pri_sum_g5_under_g1_th &&
++			    dfs->pri_hold_sum[5] <= dfs->pri_sum_g5_under_g1_th)
++				dfs->pri_type3_4_cond2 = 1;
++		} else {
++			dfs->pri_type3_4_cond1 = 1;
++			dfs->pri_type3_4_cond2 = 1;
++		}
++		if (dfs->pri_type3_4_cond1 && dfs->pri_type3_4_cond2)
++			dfs->pri_type3_4_flag = 1;
++	} else {
++	}
++
++	if (dfs->print_hist_rpt) {
++		dfs_pw_thd1 = (u8)odm_get_bb_reg(dm, 0x19e4, 0xff000000);
++		dfs_pw_thd2 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x000000ff);
++		dfs_pw_thd3 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x0000ff00);
++		dfs_pw_thd4 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x00ff0000);
++		dfs_pw_thd5 = (u8)odm_get_bb_reg(dm, 0x19e8, 0xff000000);
++
++		dfs_pri_thd1 = (u8)odm_get_bb_reg(dm, 0x19b8, 0x7F80);
++		dfs_pri_thd2 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x000000ff);
++		dfs_pri_thd3 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x0000ff00);
++		dfs_pri_thd4 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x00ff0000);
++		dfs_pri_thd5 = (u8)odm_get_bb_reg(dm, 0x19ec, 0xff000000);
++
++		PHYDM_DBG(dm, DBG_DFS, "\ndfs_pw_thd=%d %d %d %d %d\n",
++			  dfs_pw_thd1, dfs_pw_thd2, dfs_pw_thd3,
++			  dfs_pw_thd4, dfs_pw_thd5);
++		PHYDM_DBG(dm, DBG_DFS, "-----pulse width hist-----\n");
++		PHYDM_DBG(dm, DBG_DFS, "dfs_hist_pw=%x %x\n",
++			  dfs_hist1_pw, dfs_hist2_pw);
++		PHYDM_DBG(dm, DBG_DFS, "g_pw_hist = %x %x %x %x %x %x\n",
++			  g_pw[0], g_pw[1], g_pw[2], g_pw[3],
++			  g_pw[4], g_pw[5]);
++		PHYDM_DBG(dm, DBG_DFS, "dfs_pri_thd=%d %d %d %d %d\n",
++			  dfs_pri_thd1, dfs_pri_thd2, dfs_pri_thd3,
++			  dfs_pri_thd4, dfs_pri_thd5);
++		PHYDM_DBG(dm, DBG_DFS, "-----pulse interval hist-----\n");
++		PHYDM_DBG(dm, DBG_DFS, "dfs_hist_pri=%x %x\n",
++			  dfs_hist1_pri, dfs_hist2_pri);
++		PHYDM_DBG(dm, DBG_DFS,
++			  "g_pri_hist = %x %x %x %x %x %x, pw_flag = %d, pri_flag = %d\n",
++			  g_pri[0], g_pri[1], g_pri[2], g_pri[3], g_pri[4],
++			  g_pri[5], dfs->pw_flag, dfs->pri_flag);
++		if (region_domain == 1 || region_domain == 3) {
++			PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n",
++				  (dfs->hist_idx + 2) % 3);
++		} else {
++			PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n",
++				  (dfs->hist_idx + 3) % 4);
++		}
++		PHYDM_DBG(dm, DBG_DFS, "hist_long_idx= %d\n",
++			  (dfs->hist_long_idx + 299) % 300);
++		PHYDM_DBG(dm, DBG_DFS,
++			  "pw_sum_g0g5 = %d, pw_sum_g1g2g3g4 = %d\n",
++			  pw_sum_g0g5, pw_sum_g1g2g3g4);
++		PHYDM_DBG(dm, DBG_DFS,
++			  "pri_sum_g0g5 = %d, pri_sum_g1g2g3g4 = %d\n",
++			  pri_sum_g0g5, pri_sum_g1g2g3g4);
++		PHYDM_DBG(dm, DBG_DFS, "pw_hold_sum = %d %d %d %d %d %d\n",
++			  dfs->pw_hold_sum[0], dfs->pw_hold_sum[1],
++			  dfs->pw_hold_sum[2], dfs->pw_hold_sum[3],
++			  dfs->pw_hold_sum[4], dfs->pw_hold_sum[5]);
++		PHYDM_DBG(dm, DBG_DFS, "pri_hold_sum = %d %d %d %d %d %d\n",
++			  dfs->pri_hold_sum[0], dfs->pri_hold_sum[1],
++			  dfs->pri_hold_sum[2], dfs->pri_hold_sum[3],
++			  dfs->pri_hold_sum[4], dfs->pri_hold_sum[5]);
++		PHYDM_DBG(dm, DBG_DFS, "pw_long_hold_sum = %d %d %d %d %d %d\n",
++			  dfs->pw_long_hold_sum[0], dfs->pw_long_hold_sum[1],
++			  dfs->pw_long_hold_sum[2], dfs->pw_long_hold_sum[3],
++			  dfs->pw_long_hold_sum[4], dfs->pw_long_hold_sum[5]);
++		PHYDM_DBG(dm, DBG_DFS,
++			  "pri_long_hold_sum = %d %d %d %d %d %d\n",
++			  dfs->pri_long_hold_sum[0], dfs->pri_long_hold_sum[1],
++			  dfs->pri_long_hold_sum[2], dfs->pri_long_hold_sum[3],
++			  dfs->pri_long_hold_sum[4], dfs->pri_long_hold_sum[5]);
++		PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n", dfs->idle_mode);
++		PHYDM_DBG(dm, DBG_DFS, "pw_standard = %d\n", dfs->pw_std);
++		PHYDM_DBG(dm, DBG_DFS, "pri_standard = %d\n", dfs->pri_std);
++		PHYDM_DBG(dm, DBG_DFS, "\n");
++		PHYDM_DBG(dm, DBG_DFS,
++			  "pri_cond1 = %d, pri_cond2 = %d, pri_cond3 = %d, pri_cond4 = %d, pri_cond5 = %d\n",
++			  dfs->pri_cond1, dfs->pri_cond2, dfs->pri_cond3,
++			  dfs->pri_cond4, dfs->pri_cond5);
++		PHYDM_DBG(dm, DBG_DFS,
++			  "bandwidth = %d, pri_th = %d, max_pri_cnt_th = %d, safe_pri_pw_diff_th = %d\n",
++			  band_width, pri_th, max_pri_cnt_th,
++			  safe_pri_pw_diff_th);
++	}
++}
++#endif
++boolean phydm_dfs_hist_log(void *dm_void, u8 index)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _DFS_STATISTICS *dfs = &dm->dfs;
++	u8 i = 0, j = 0;
++	boolean hist_radar_detected = 0;
++
++	if (dfs->pulse_type_hist[index] == 0) {
++		dfs->radar_type = 0;
++		if (dfs->pw_flag && dfs->pri_flag &&
++		    dfs->pri_type3_4_flag) {
++			hist_radar_detected = 1;
++			PHYDM_DBG(dm, DBG_DFS,
++				  "Detected type %d radar signal!\n",
++				  dfs->radar_type);
++			if (dfs->det_print2) {
++				PHYDM_DBG(dm, DBG_DFS,
++					  "hist_idx= %d\n",
++					  (dfs->hist_idx + 3) % 4);
++				for (j = 0; j < 4; j++) {
++				for (i = 0; i < 6; i++) {
++					PHYDM_DBG(dm, DBG_DFS,
++						  "pri_hold = %d ",
++						  dfs->pri_hold[j][i]);
++				}
++				PHYDM_DBG(dm, DBG_DFS, "\n");
++				}
++				PHYDM_DBG(dm, DBG_DFS, "\n");
++				for (j = 0; j < 4; j++) {
++				for (i = 0; i < 6; i++) {
++					PHYDM_DBG(dm, DBG_DFS, "pw_hold = %d ",
++						  dfs->pw_hold[j][i]);
++				}
++					PHYDM_DBG(dm, DBG_DFS, "\n");
++				}
++				PHYDM_DBG(dm, DBG_DFS, "\n");
++				PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n",
++					  dfs->idle_mode);
++				PHYDM_DBG(dm, DBG_DFS,
++					  "pw_hold_sum = %d %d %d %d %d %d\n",
++					  dfs->pw_hold_sum[0],
++					  dfs->pw_hold_sum[1],
++					  dfs->pw_hold_sum[2],
++					  dfs->pw_hold_sum[3],
++					  dfs->pw_hold_sum[4],
++					  dfs->pw_hold_sum[5]);
++				PHYDM_DBG(dm, DBG_DFS,
++					  "pri_hold_sum = %d %d %d %d %d %d\n",
++					  dfs->pri_hold_sum[0],
++					  dfs->pri_hold_sum[1],
++					  dfs->pri_hold_sum[2],
++					  dfs->pri_hold_sum[3],
++					  dfs->pri_hold_sum[4],
++					  dfs->pri_hold_sum[5]);
++			}
++		} else {
++		if (dfs->det_print2) {
++			if (dfs->pulse_flag_hist[index] &&
++			    dfs->pri_flag == 0) {
++				PHYDM_DBG(dm, DBG_DFS, "pri_variation = %d\n",
++					  dfs->pri_std);
++				PHYDM_DBG(dm, DBG_DFS,
++					  "PRI criterion is not satisfied!\n");
++				if (dfs->pri_cond1 == 0)
++					PHYDM_DBG(dm, DBG_DFS,
++						  "pri_cond1 is not satisfied!\n");
++				if (dfs->pri_cond2 == 0)
++					PHYDM_DBG(dm, DBG_DFS,
++						  "pri_cond2 is not satisfied!\n");
++				if (dfs->pri_cond3 == 0)
++					PHYDM_DBG(dm, DBG_DFS,
++						  "pri_cond3 is not satisfied!\n");
++				if (dfs->pri_cond4 == 0)
++					PHYDM_DBG(dm, DBG_DFS,
++						  "pri_cond4 is not satisfied!\n");
++				if (dfs->pri_cond5 == 0)
++					PHYDM_DBG(dm, DBG_DFS,
++						  "pri_cond5 is not satisfied!\n");
++			}
++			if (dfs->pulse_flag_hist[index] &&
++			    dfs->pw_flag == 0) {
++				PHYDM_DBG(dm, DBG_DFS, "pw_variation = %d\n",
++					  dfs->pw_std);
++				PHYDM_DBG(dm, DBG_DFS,
++					  "PW criterion is not satisfied!\n");
++				if (dfs->pw_cond1 == 0)
++					PHYDM_DBG(dm, DBG_DFS,
++						  "pw_cond1 is not satisfied!\n");
++				if (dfs->pw_cond2 == 0)
++					PHYDM_DBG(dm, DBG_DFS,
++						  "pw_cond2 is not satisfied!\n");
++				if (dfs->pw_cond3 == 0)
++					PHYDM_DBG(dm, DBG_DFS,
++						  "pw_cond3 is not satisfied!\n");
++			}
++			if (dfs->pulse_flag_hist[index] &&
++			    (dfs->pri_type3_4_flag == 0)) {
++				PHYDM_DBG(dm, DBG_DFS,
++					  "pri_type3_4 criterion is not satisfied!\n");
++				if (dfs->pri_type3_4_cond1 == 0)
++					PHYDM_DBG(dm, DBG_DFS,
++						  "pri_type3_4_cond1 is not satisfied!\n");
++				if (dfs->pri_type3_4_cond2 == 0)
++					PHYDM_DBG(dm, DBG_DFS,
++						  "pri_type3_4_cond2 is not satisfied!\n");
++			}
++			PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n",
++				  (dfs->hist_idx + 3) % 4);
++			for (j = 0; j < 4; j++) {
++				for (i = 0; i < 6; i++) {
++					PHYDM_DBG(dm, DBG_DFS,
++						  "pri_hold = %d ",
++						  dfs->pri_hold[j][i]);
++				}
++				PHYDM_DBG(dm, DBG_DFS, "\n");
++			}
++			PHYDM_DBG(dm, DBG_DFS, "\n");
++			for (j = 0; j < 4; j++) {
++				for (i = 0; i < 6; i++)
++					PHYDM_DBG(dm, DBG_DFS,
++						  "pw_hold = %d ",
++						  dfs->pw_hold[j][i]);
++				PHYDM_DBG(dm, DBG_DFS, "\n");
++			}
++			PHYDM_DBG(dm, DBG_DFS, "\n");
++			PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n",
++				  dfs->idle_mode);
++			PHYDM_DBG(dm, DBG_DFS,
++				  "pw_hold_sum = %d %d %d %d %d %d\n",
++				  dfs->pw_hold_sum[0], dfs->pw_hold_sum[1],
++				  dfs->pw_hold_sum[2], dfs->pw_hold_sum[3],
++				  dfs->pw_hold_sum[4], dfs->pw_hold_sum[5]);
++			PHYDM_DBG(dm, DBG_DFS,
++				  "pri_hold_sum = %d %d %d %d %d %d\n",
++				  dfs->pri_hold_sum[0], dfs->pri_hold_sum[1],
++				  dfs->pri_hold_sum[2], dfs->pri_hold_sum[3],
++				  dfs->pri_hold_sum[4], dfs->pri_hold_sum[5]);
++		}
++		}
++	} else {
++		dfs->radar_type = 1;
++		if (dfs->det_print2) {
++			PHYDM_DBG(dm, DBG_DFS, "\n");
++			PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n",
++				  dfs->idle_mode);
++		}
++		/* @Long radar should satisfy three conditions */
++		if (dfs->long_radar_flag == 1) {
++			hist_radar_detected = 1;
++			PHYDM_DBG(dm, DBG_DFS,
++				  "Detected type %d radar signal!\n",
++				  dfs->radar_type);
++		} else {
++			if (dfs->det_print2) {
++				if (dfs->pw_long_cond1 == 0)
++					PHYDM_DBG(dm, DBG_DFS,
++						  "--pw_long_cond1 is not satisfied!--\n");
++				if (dfs->pw_long_cond2 == 0)
++					PHYDM_DBG(dm, DBG_DFS,
++						  "--pw_long_cond2 is not satisfied!--\n");
++				if (dfs->pri_long_cond1 == 0)
++					PHYDM_DBG(dm, DBG_DFS,
++						  "--pri_long_cond1 is not satisfied!--\n");
++			}
++		}
++	}
++	return hist_radar_detected;
++}
++
++boolean phydm_radar_detect(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _DFS_STATISTICS *dfs = &dm->dfs;
++	boolean radar_detected = false;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		dfs->igi_cur = (u8)odm_get_bb_reg(dm, R_0x1d70, 0x0000007f);
++		dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00007f00);
++	#if (RTL8721D_SUPPORT)
++	} else if (dm->support_ic_type & (ODM_RTL8721D)) {
++		dfs->st_l2h_cur = (u8)(odm_get_bb_reg(dm, R_0xf54,
++						      0x0000001f) << 2);
++		dfs->st_l2h_cur += (u8)odm_get_bb_reg(dm, R_0xf58, 0xc0000000);
++	#endif
++	} else {
++		dfs->igi_cur = (u8)odm_get_bb_reg(dm, R_0xc50, 0x0000007f);
++		dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0x91c, 0x000000ff);
++	}
++
++	/* @dynamic pwdb calibration */
++	if (dfs->igi_pre != dfs->igi_cur) {
++		dfs->pwdb_th_cur = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur)
++				    / 2 + dfs->pwdb_scalar_factor;
++
++		/* @limit the pwdb value to absolute lower bound 0xa */
++		dfs->pwdb_th_cur = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th);
++		/* @limit the pwdb value to absolute upper bound 0x1f */
++		dfs->pwdb_th_cur = MIN_2(dfs->pwdb_th_cur, 0x1f);
++
++		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++			odm_set_bb_reg(dm, R_0xa50, 0x000000f0,
++				       dfs->pwdb_th_cur);
++		#if (RTL8721D_SUPPORT)
++		else if (dm->support_ic_type & (ODM_RTL8721D))
++			odm_set_bb_reg(dm, R_0xf70, 0x03c00000,
++				       dfs->pwdb_th_cur);
++		#endif
++		else
++			odm_set_bb_reg(dm, R_0x918, 0x00001f00,
++				       dfs->pwdb_th_cur);
++	}
++	dfs->igi_pre = dfs->igi_cur;
++
++	phydm_dfs_dynamic_setting(dm);
++	#if (RTL8814A_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT)
++	if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
++		phydm_dfs_histogram_radar_distinguish(dm);
++	#endif
++	radar_detected = phydm_radar_detect_dm_check(dm);
++
++	if (radar_detected) {
++		PHYDM_DBG(dm, DBG_DFS,
++			  "Radar detect: %d\n", radar_detected);
++		phydm_radar_detect_reset(dm);
++		if (dfs->dbg_mode == 1) {
++			PHYDM_DBG(dm, DBG_DFS,
++				  "Radar is detected in DFS dbg mode.\n");
++			radar_detected = 0;
++		}
++	}
++
++	if (dfs->sw_trigger_mode) {
++		radar_detected = 1;
++		PHYDM_DBG(dm, DBG_DFS,
++			  "Radar is detected in DFS SW trigger mode.\n");
++	}
++
++	return radar_detected;
++}
++
++void phydm_dfs_hist_dbg(void *dm_void, char input[][16], u32 *_used,
++			char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _DFS_STATISTICS *dfs = &dm->dfs;
++	char help[] = "-h";
++	u32 argv[5] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 i;
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{0} pri_hist_th = %d\n", dfs->pri_hist_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{1} pri_sum_g1_th = %d\n", dfs->pri_sum_g1_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{2} pri_sum_g5_th = %d\n", dfs->pri_sum_g5_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{3} pri_sum_g1_fcc_th = %d\n",
++			 dfs->pri_sum_g1_fcc_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{4} pri_sum_g3_fcc_th = %d\n",
++			 dfs->pri_sum_g3_fcc_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{5} pri_sum_safe_fcc_th = %d\n",
++			 dfs->pri_sum_safe_fcc_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{6} pri_sum_type4_th = %d\n", dfs->pri_sum_type4_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{7} pri_sum_type6_th = %d\n", dfs->pri_sum_type6_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{8} pri_sum_safe_th = %d\n", dfs->pri_sum_safe_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{9} pri_sum_g5_under_g1_th = %d\n",
++			 dfs->pri_sum_g5_under_g1_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{10} pri_pw_diff_th = %d\n", dfs->pri_pw_diff_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{11} pri_pw_diff_fcc_th = %d\n",
++			 dfs->pri_pw_diff_fcc_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{12} pri_pw_diff_fcc_idle_th = %d\n",
++			 dfs->pri_pw_diff_fcc_idle_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{13} pri_pw_diff_w53_th = %d\n",
++			 dfs->pri_pw_diff_w53_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{14} pri_type1_low_fcc_th = %d\n",
++			 dfs->pri_type1_low_fcc_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{15} pri_type1_upp_fcc_th = %d\n",
++			 dfs->pri_type1_upp_fcc_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{16} pri_type1_cen_fcc_th = %d\n",
++			 dfs->pri_type1_cen_fcc_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{17} pw_g0_th = %d\n", dfs->pw_g0_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{18} pw_long_lower_20m_th = %d\n",
++			 dfs->pw_long_lower_20m_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{19} pw_long_lower_th = %d\n",
++			 dfs->pw_long_lower_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{20} pri_long_upper_th = %d\n",
++			 dfs->pri_long_upper_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{21} pw_long_sum_upper_th = %d\n",
++			 dfs->pw_long_sum_upper_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{22} pw_std_th = %d\n", dfs->pw_std_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{23} pw_std_idle_th = %d\n", dfs->pw_std_idle_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{24} pri_std_th = %d\n", dfs->pri_std_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{25} pri_std_idle_th = %d\n", dfs->pri_std_idle_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{26} type4_pw_max_cnt = %d\n", dfs->type4_pw_max_cnt);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{27} type4_safe_pri_sum_th = %d\n",
++			 dfs->type4_safe_pri_sum_th);
++	} else {
++		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &argv[0]);
++
++		for (i = 1; i < 5; i++) {
++			if (input[i + 1])
++				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
++					     &argv[i]);
++		}
++		if (argv[0] == 0) {
++			dfs->pri_hist_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_hist_th = %d\n",
++				 dfs->pri_hist_th);
++		} else if (argv[0] == 1) {
++			dfs->pri_sum_g1_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_sum_g1_th = %d\n",
++				 dfs->pri_sum_g1_th);
++		} else if (argv[0] == 2) {
++			dfs->pri_sum_g5_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_sum_g5_th = %d\n",
++				 dfs->pri_sum_g5_th);
++		} else if (argv[0] == 3) {
++			dfs->pri_sum_g1_fcc_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_sum_g1_fcc_th = %d\n",
++				 dfs->pri_sum_g1_fcc_th);
++		} else if (argv[0] == 4) {
++			dfs->pri_sum_g3_fcc_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_sum_g3_fcc_th = %d\n",
++				 dfs->pri_sum_g3_fcc_th);
++		} else if (argv[0] == 5) {
++			dfs->pri_sum_safe_fcc_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_sum_safe_fcc_th = %d\n",
++				 dfs->pri_sum_safe_fcc_th);
++		} else if (argv[0] == 6) {
++			dfs->pri_sum_type4_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_sum_type4_th = %d\n",
++				 dfs->pri_sum_type4_th);
++		} else if (argv[0] == 7) {
++			dfs->pri_sum_type6_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_sum_type6_th = %d\n",
++				 dfs->pri_sum_type6_th);
++		} else if (argv[0] == 8) {
++			dfs->pri_sum_safe_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_sum_safe_th = %d\n",
++				 dfs->pri_sum_safe_th);
++		} else if (argv[0] == 9) {
++			dfs->pri_sum_g5_under_g1_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_sum_g5_under_g1_th = %d\n",
++				 dfs->pri_sum_g5_under_g1_th);
++		} else if (argv[0] == 10) {
++			dfs->pri_pw_diff_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_pw_diff_th = %d\n",
++				 dfs->pri_pw_diff_th);
++		} else if (argv[0] == 11) {
++			dfs->pri_pw_diff_fcc_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_pw_diff_fcc_th = %d\n",
++				 dfs->pri_pw_diff_fcc_th);
++		} else if (argv[0] == 12) {
++			dfs->pri_pw_diff_fcc_idle_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_pw_diff_fcc_idle_th = %d\n",
++				 dfs->pri_pw_diff_fcc_idle_th);
++		} else if (argv[0] == 13) {
++			dfs->pri_pw_diff_w53_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_pw_diff_w53_th = %d\n",
++				 dfs->pri_pw_diff_w53_th);
++		} else if (argv[0] == 14) {
++			dfs->pri_type1_low_fcc_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_type1_low_fcc_th = %d\n",
++				 dfs->pri_type1_low_fcc_th);
++		} else if (argv[0] == 15) {
++			dfs->pri_type1_upp_fcc_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_type1_upp_fcc_th = %d\n",
++				 dfs->pri_type1_upp_fcc_th);
++		} else if (argv[0] == 16) {
++			dfs->pri_type1_cen_fcc_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_type1_cen_fcc_th = %d\n",
++				 dfs->pri_type1_cen_fcc_th);
++		} else if (argv[0] == 17) {
++			dfs->pw_g0_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pw_g0_th = %d\n",
++				 dfs->pw_g0_th);
++		} else if (argv[0] == 18) {
++			dfs->pw_long_lower_20m_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pw_long_lower_20m_th = %d\n",
++				 dfs->pw_long_lower_20m_th);
++		} else if (argv[0] == 19) {
++			dfs->pw_long_lower_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pw_long_lower_th = %d\n",
++				 dfs->pw_long_lower_th);
++		} else if (argv[0] == 20) {
++			dfs->pri_long_upper_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_long_upper_th = %d\n",
++				 dfs->pri_long_upper_th);
++		} else if (argv[0] == 21) {
++			dfs->pw_long_sum_upper_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pw_long_sum_upper_th = %d\n",
++				 dfs->pw_long_sum_upper_th);
++		} else if (argv[0] == 22) {
++			dfs->pw_std_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pw_std_th = %d\n",
++				 dfs->pw_std_th);
++		} else if (argv[0] == 23) {
++			dfs->pw_std_idle_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pw_std_idle_th = %d\n",
++				 dfs->pw_std_idle_th);
++		} else if (argv[0] == 24) {
++			dfs->pri_std_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_std_th = %d\n",
++				 dfs->pri_std_th);
++		} else if (argv[0] == 25) {
++			dfs->pri_std_idle_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pri_std_idle_th = %d\n",
++				 dfs->pri_std_idle_th);
++		} else if (argv[0] == 26) {
++			dfs->type4_pw_max_cnt = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "type4_pw_max_cnt = %d\n",
++				 dfs->type4_pw_max_cnt);
++		} else if (argv[0] == 27) {
++			dfs->type4_safe_pri_sum_th = (u8)argv[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "type4_safe_pri_sum_th = %d\n",
++				 dfs->type4_safe_pri_sum_th);
++		}
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used,
++		     char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _DFS_STATISTICS *dfs = &dm->dfs;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 argv[10] = {0};
++	u8 i, input_idx = 0;
++
++	for (i = 0; i < 7; i++) {
++		if (input[i + 1]) {
++			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &argv[i]);
++			input_idx++;
++		}
++	}
++
++	if (input_idx == 0)
++		return;
++
++	dfs->dbg_mode = (boolean)argv[0];
++	dfs->sw_trigger_mode = (boolean)argv[1];
++	dfs->force_TP_mode = (boolean)argv[2];
++	dfs->det_print = (boolean)argv[3];
++	dfs->det_print2 = (boolean)argv[4];
++	dfs->print_hist_rpt = (boolean)argv[5];
++	dfs->hist_cond_on = (boolean)argv[6];
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "dbg_mode: %d, sw_trigger_mode: %d, force_TP_mode: %d, det_print: %d,det_print2: %d, print_hist_rpt: %d, hist_cond_on: %d\n",
++		 dfs->dbg_mode, dfs->sw_trigger_mode, dfs->force_TP_mode,
++		 dfs->det_print, dfs->det_print2, dfs->print_hist_rpt,
++		 dfs->hist_cond_on);
++}
++
++u8 phydm_dfs_polling_time(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _DFS_STATISTICS *dfs = &dm->dfs;
++
++	if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
++		dfs->dfs_polling_time = 40;
++	else
++		dfs->dfs_polling_time = 100;
++
++	return dfs->dfs_polling_time;
++}
++
++#endif /* @defined(CONFIG_PHYDM_DFS_MASTER) */
++
++boolean
++phydm_is_dfs_band(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (((*dm->channel >= 52) && (*dm->channel <= 64)) ||
++	    ((*dm->channel >= 100) && (*dm->channel <= 144)))
++		return true;
++	else
++		return false;
++}
++
++boolean
++phydm_dfs_master_enabled(void *dm_void)
++{
++#ifdef CONFIG_PHYDM_DFS_MASTER
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	boolean ret_val = false;
++
++	if (dm->dfs_master_enabled) /*pointer protection*/
++		ret_val = *dm->dfs_master_enabled ? true : false;
++
++	return ret_val;
++#else
++	return false;
++#endif
++}
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++void phydm_dfs_ap_reset_radar_detect_counter_and_flag(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	/* @Clear Radar Counter and Radar flag */
++	odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
++	odm_set_bb_reg(dm, R_0xa40, BIT(15), 1);
++
++	/* RT_TRACE(COMP_DFS, DBG_LOUD, ("[DFS], After reset radar counter, 0xcf8 = 0x%x, 0xcf4 = 0x%x\n", */
++	/* PHY_QueryBBReg(Adapter, 0xcf8, bMaskDWord), */
++	/* PHY_QueryBBReg(Adapter, 0xcf4, bMaskDWord))); */
++}
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dfs.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dfs.h
+new file mode 100644
+index 000000000..fabc640e7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dfs.h
+@@ -0,0 +1,191 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_DFS_H__
++#define __PHYDM_DFS_H__
++
++#define DFS_VERSION "1.1"
++
++/*@
++ * ============================================================
++ *  Definition
++ * ============================================================
++ */
++
++/*@
++ * ============================================================
++ * 1  structure
++ * ============================================================
++ */
++
++struct _DFS_STATISTICS {
++	u8		mask_idx;
++	u8		igi_cur;
++	u8		igi_pre;
++	u8		st_l2h_cur;
++	u16		fa_count_pre;
++	u16		fa_inc_hist[5];
++	u16		short_pulse_cnt_pre;
++	u16		long_pulse_cnt_pre;
++	u8		pwdb_th;
++	u8		pwdb_th_cur;
++	u8		pwdb_scalar_factor;
++	u8		peak_th;
++	u8		short_pulse_cnt_th;
++	u8		long_pulse_cnt_th;
++	u8		peak_window;
++	u8		three_peak_opt;
++	u8		three_peak_th2;
++	u8		fa_mask_th;
++	u8		st_l2h_max;
++	u8		st_l2h_min;
++	u8		dfs_polling_time;
++	u8		mask_hist_checked : 3;
++	boolean		pulse_flag_hist[5];
++	boolean		pulse_type_hist[5];
++	boolean		radar_det_mask_hist[5];
++	boolean		idle_mode;
++	boolean		force_TP_mode;
++	boolean		dbg_mode;
++	boolean		sw_trigger_mode;
++	boolean		det_print;
++	boolean		det_print2;
++	boolean		radar_type;
++	boolean		print_hist_rpt;
++	boolean		hist_cond_on;
++	/*@dfs histogram*/
++	boolean		pri_cond1;
++	boolean		pri_cond2;
++	boolean		pri_cond3;
++	boolean		pri_cond4;
++	boolean		pri_cond5;
++	boolean		pw_cond1;
++	boolean		pw_cond2;
++	boolean		pw_cond3;
++	boolean		pri_type3_4_cond1;	/*@for ETSI*/
++	boolean		pri_type3_4_cond2;	/*@for ETSI*/
++	boolean		pw_long_cond1;	/*@for long radar*/
++	boolean		pw_long_cond2;	/*@for long radar*/
++	boolean		pri_long_cond1;	/*@for long radar*/
++	boolean		pw_flag;
++	boolean		pri_flag;
++	boolean		pri_type3_4_flag;	/*@for ETSI*/
++	boolean		long_radar_flag;
++	u8		pri_hold_sum[6];
++	u8		pw_hold_sum[6];
++	u8		pri_long_hold_sum[6];
++	u8		pw_long_hold_sum[6];
++	u8		hist_idx;
++	u8		hist_long_idx;
++	u8		pw_hold[4][6];
++	u8		pri_hold[4][6];
++	u8		pw_std;	/*@The std(var) of reasonable num of pw group*/
++	u8		pri_std;/*@The std(var) of reasonable num of pri group*/
++	/*@dfs histogram threshold*/
++	u8		pri_hist_th : 3;
++	u8		pri_sum_g1_th : 4;
++	u8		pri_sum_g5_th : 4;
++	u8		pri_sum_g1_fcc_th : 3;
++	u8		pri_sum_g3_fcc_th : 3;
++	u8		pri_sum_safe_fcc_th : 7;
++	u8		pri_sum_type4_th : 5;
++	u8		pri_sum_type6_th : 5;
++	u8		pri_sum_safe_th : 6;
++	u8		pri_sum_g5_under_g1_th : 3;
++	u8		pri_pw_diff_th : 3;
++	u8		pri_pw_diff_fcc_th : 4;
++	u8		pri_pw_diff_fcc_idle_th : 2;
++	u8		pri_pw_diff_w53_th : 4;
++	u8		pri_type1_low_fcc_th : 7;
++	u8		pri_type1_upp_fcc_th : 7;
++	u8		pri_type1_cen_fcc_th : 7;
++	u8		pw_g0_th : 4;
++	u8		pw_long_lower_20m_th : 4;
++	u8		pw_long_lower_th : 3;
++	u8		pri_long_upper_th : 6;
++	u8		pw_long_sum_upper_th : 7;
++	u8		pw_std_th : 4;
++	u8		pw_std_idle_th : 4;
++	u8		pri_std_th : 4;
++	u8		pri_std_idle_th : 4;
++	u8		type4_pw_max_cnt : 4;
++	u8		type4_safe_pri_sum_th : 3;
++};
++
++/*@
++ * ============================================================
++ * enumeration
++ * ============================================================
++ */
++
++enum phydm_dfs_region_domain {
++	PHYDM_DFS_DOMAIN_UNKNOWN =	0,
++	PHYDM_DFS_DOMAIN_FCC =		1,
++	PHYDM_DFS_DOMAIN_MKK =		2,
++	PHYDM_DFS_DOMAIN_ETSI =		3,
++};
++
++/*@
++ * ============================================================
++ * function prototype
++ * ============================================================
++ */
++#if defined(CONFIG_PHYDM_DFS_MASTER)
++void phydm_radar_detect_reset(void *dm_void);
++void phydm_radar_detect_disable(void *dm_void);
++void phydm_radar_detect_enable(void *dm_void);
++boolean phydm_radar_detect(void *dm_void);
++void phydm_dfs_histogram_radar_distinguish(void *dm_void);
++boolean phydm_dfs_hist_log(void *dm_void, u8 index);
++void phydm_dfs_parameter_init(void *dm_void);
++void phydm_dfs_hist_dbg(void *dm_void, char input[][16], u32 *_used,
++			char *output, u32 *_out_len);
++void phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used,
++		     char *output, u32 *_out_len);
++u8 phydm_dfs_polling_time(void *dm_void);
++#endif /* @defined(CONFIG_PHYDM_DFS_MASTER) */
++
++boolean
++phydm_dfs_is_meteorology_channel(void *dm_void);
++
++void
++phydm_dfs_segment_distinguish(void *dm_void, enum rf_syn syn_path);
++
++void
++phydm_dfs_segment_flag_reset(void *dm_void);
++
++boolean
++phydm_is_dfs_band(void *dm_void);
++
++boolean
++phydm_dfs_master_enabled(void *dm_void);
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++void phydm_dfs_ap_reset_radar_detect_counter_and_flag(void *dm_void);
++#endif
++#endif
++
++#endif /*@#ifndef __PHYDM_DFS_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dig.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dig.c
+new file mode 100644
+index 000000000..fed24e918
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dig.c
+@@ -0,0 +1,3447 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ * ************************************************************
++ */
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#ifdef CFG_DIG_DAMPING_CHK
++void phydm_dig_recorder_reset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
++
++	PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
++
++	odm_memory_set(dm, &dig_rc->igi_bitmap, 0,
++		       sizeof(struct phydm_dig_recorder_strcut));
++}
++
++void phydm_dig_recorder(void *dm_void, u8 igi_curr,
++			u32 fa_cnt)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
++	u8 igi_pre = dig_rc->igi_history[0];
++	u8 igi_up = 0;
++
++	if (!dm->is_linked)
++		return;
++
++	PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
++
++	if (dm->first_connect) {
++		phydm_dig_recorder_reset(dm);
++		dig_rc->igi_history[0] = igi_curr;
++		dig_rc->fa_history[0] = fa_cnt;
++		return;
++	}
++
++	if (igi_curr % 2)
++		igi_curr--;
++
++	igi_pre = dig_rc->igi_history[0];
++	igi_up = (igi_curr > igi_pre) ? 1 : 0;
++	dig_rc->igi_bitmap = ((dig_rc->igi_bitmap << 1) & 0xfe) | igi_up;
++
++	dig_rc->igi_history[3] = dig_rc->igi_history[2];
++	dig_rc->igi_history[2] = dig_rc->igi_history[1];
++	dig_rc->igi_history[1] = dig_rc->igi_history[0];
++	dig_rc->igi_history[0] = igi_curr;
++
++	dig_rc->fa_history[3] = dig_rc->fa_history[2];
++	dig_rc->fa_history[2] = dig_rc->fa_history[1];
++	dig_rc->fa_history[1] = dig_rc->fa_history[0];
++	dig_rc->fa_history[0] = fa_cnt;
++
++	PHYDM_DBG(dm, DBG_DIG, "igi_history[3:0] = {0x%x, 0x%x, 0x%x, 0x%x}\n",
++		  dig_rc->igi_history[3], dig_rc->igi_history[2],
++		  dig_rc->igi_history[1], dig_rc->igi_history[0]);
++	PHYDM_DBG(dm, DBG_DIG, "fa_history[3:0] = {%d, %d, %d, %d}\n",
++		  dig_rc->fa_history[3], dig_rc->fa_history[2],
++		  dig_rc->fa_history[1], dig_rc->fa_history[0]);
++	PHYDM_DBG(dm, DBG_DIG, "igi_bitmap = {%d, %d, %d, %d} = 0x%x\n",
++		  (u8)((dig_rc->igi_bitmap & BIT(3)) >> 3),
++		  (u8)((dig_rc->igi_bitmap & BIT(2)) >> 2),
++		  (u8)((dig_rc->igi_bitmap & BIT(1)) >> 1),
++		  (u8)(dig_rc->igi_bitmap & BIT(0)),
++		  dig_rc->igi_bitmap);
++}
++
++void phydm_dig_damping_chk(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
++	u8 igi_bitmap_4bit = dig_rc->igi_bitmap & 0xf;
++	u8 diff1 = 0, diff2 = 0;
++	u32 fa_low_th = dig_t->fa_th[0];
++	u32 fa_high_th = dig_t->fa_th[1];
++	u32 fa_high_th2 = dig_t->fa_th[2];
++	u8 fa_pattern_match = 0;
++	u32 time_tmp = 0;
++
++	if (!dm->is_linked)
++		return;
++
++	PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
++
++	/*@== Release Damping ================================================*/
++	if (dig_rc->damping_limit_en) {
++		PHYDM_DBG(dm, DBG_DIG,
++			  "[Damping Limit!] limit_time=%d, phydm_sys_up_time=%d\n",
++			  dig_rc->limit_time, dm->phydm_sys_up_time);
++
++		time_tmp = dig_rc->limit_time + DIG_LIMIT_PERIOD;
++
++		if (DIFF_2(dm->rssi_min, dig_rc->limit_rssi) > 3 ||
++		    time_tmp < dm->phydm_sys_up_time) {
++			dig_rc->damping_limit_en = 0;
++			PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, limit_rssi=%d\n",
++				  dm->rssi_min, dig_rc->limit_rssi);
++		}
++		return;
++	}
++
++	/*@== Damping Pattern Check===========================================*/
++	PHYDM_DBG(dm, DBG_DIG, "fa_th{H, L}= {%d,%d}\n", fa_high_th, fa_low_th);
++
++	switch (igi_bitmap_4bit) {
++	case 0x5:
++	/*@ 4b'0101 
++	* IGI:[3]down(0x24)->[2]up(0x26)->[1]down(0x24)->[0]up(0x26)->[new](Lock @ 0x26)
++	* FA: [3] >high1   ->[2] <low   ->[1] >high1   ->[0] <low   ->[new]   <low
++	*
++	* IGI:[3]down(0x24)->[2]up(0x28)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28)
++	* FA: [3] >high2   ->[2] <low   ->[1] >high2   ->[0] <low   ->[new]   <low
++	*/
++		if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
++			diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
++
++		if (dig_rc->igi_history[2] > dig_rc->igi_history[3])
++			diff2 = dig_rc->igi_history[2] - dig_rc->igi_history[3];
++
++		if (dig_rc->fa_history[0] < fa_low_th &&
++		    dig_rc->fa_history[1] > fa_high_th &&
++		    dig_rc->fa_history[2] < fa_low_th &&
++		    dig_rc->fa_history[3] > fa_high_th) {
++		    /*@Check each fa element*/
++			fa_pattern_match = 1;
++		}
++		break;
++	case 0x9:
++	/*@ 4b'1001
++	* IGI:[3]up(0x28)->[2]down(0x26)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28)
++	* FA: [3]  <low  ->[2] <low     ->[1] >high2   ->[0] <low   ->[new]  <low
++	*/
++		if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
++			diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
++
++		if (dig_rc->igi_history[2] < dig_rc->igi_history[3])
++			diff2 = dig_rc->igi_history[3] - dig_rc->igi_history[2];
++
++		if (dig_rc->fa_history[0] < fa_low_th &&
++		    dig_rc->fa_history[1] > fa_high_th2 &&
++		    dig_rc->fa_history[2] < fa_low_th &&
++		    dig_rc->fa_history[3] < fa_low_th) {
++		    /*@Check each fa element*/
++			fa_pattern_match = 1;
++		}
++		break;
++	default:
++		break;
++	}
++
++	if (diff1 >= 2 && diff2 >= 2 && fa_pattern_match) {
++		dig_rc->damping_limit_en = 1;
++		dig_rc->damping_limit_val = dig_rc->igi_history[0];
++		dig_rc->limit_time = dm->phydm_sys_up_time;
++		dig_rc->limit_rssi = dm->rssi_min;
++
++		PHYDM_DBG(dm, DBG_DIG,
++			  "[Start damping_limit!] IGI_dyn_min=0x%x, limit_time=%d, limit_rssi=%d\n",
++			  dig_rc->damping_limit_val,
++			  dig_rc->limit_time, dig_rc->limit_rssi);
++	}
++
++	PHYDM_DBG(dm, DBG_DIG, "damping_limit=%d\n", dig_rc->damping_limit_en);
++}
++#endif
++
++void phydm_fa_threshold_check(void *dm_void, boolean is_dfs_band)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++
++	if (dig_t->is_dbg_fa_th) {
++		PHYDM_DBG(dm, DBG_DIG, "Manual Fix FA_th\n");
++	} else if (dm->is_linked) {
++		if (dm->rssi_min < 20) { /*@[PHYDM-252]*/
++			dig_t->fa_th[0] = 500;
++			dig_t->fa_th[1] = 750;
++			dig_t->fa_th[2] = 1000;
++		} else if (((dm->rx_tp >> 2) > dm->tx_tp) && /*Test RX TP*/
++			   (dm->rx_tp < 10) && (dm->rx_tp > 1)) { /*TP=1~10Mb*/
++			dig_t->fa_th[0] = 125;
++			dig_t->fa_th[1] = 250;
++			dig_t->fa_th[2] = 500;
++		} else {
++			dig_t->fa_th[0] = 250;
++			dig_t->fa_th[1] = 500;
++			dig_t->fa_th[2] = 750;
++		}
++	} else {
++		if (is_dfs_band) { /* @For DFS band and no link */
++
++			dig_t->fa_th[0] = 250;
++			dig_t->fa_th[1] = 1000;
++			dig_t->fa_th[2] = 2000;
++		} else {
++			dig_t->fa_th[0] = 2000;
++			dig_t->fa_th[1] = 4000;
++			dig_t->fa_th[2] = 5000;
++		}
++	}
++
++	PHYDM_DBG(dm, DBG_DIG, "FA_th={%d,%d,%d}\n", dig_t->fa_th[0],
++		  dig_t->fa_th[1], dig_t->fa_th[2]);
++}
++
++void phydm_set_big_jump_step(void *dm_void, u8 curr_igi)
++{
++#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	u8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90};
++	u8 big_jump_lmt = dig_t->big_jump_lmt[dig_t->agc_table_idx];
++	u8 i;
++
++	if (dig_t->enable_adjust_big_jump == 0)
++		return;
++
++	for (i = 0; i <= dig_t->big_jump_step1; i++) {
++		if ((curr_igi + step1[i]) > big_jump_lmt) {
++			if (i != 0)
++				i = i - 1;
++			break;
++		} else if (i == dig_t->big_jump_step1) {
++			break;
++		}
++	}
++	if (dm->support_ic_type & ODM_RTL8822B)
++		odm_set_bb_reg(dm, R_0x8c8, 0xe, i);
++	else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
++		odm_set_bb_reg(dm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i);
++
++	PHYDM_DBG(dm, DBG_DIG, "Bigjump = %d (ori = 0x%x), LMT=0x%x\n", i,
++		  dig_t->big_jump_step1, big_jump_lmt);
++#endif
++}
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++void phydm_write_dig_reg_jgr3(void *dm_void, u8 igi)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++
++	PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
++
++	/* Set IGI value */
++	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
++		return;
++
++	odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC, igi);
++
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
++		odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3, igi);
++	#endif
++
++	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
++		odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3, igi);
++		odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3, igi);
++	}
++	#endif
++}
++
++u8 phydm_get_igi_reg_val_jgr3(void *dm_void, enum bb_path path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 val = 0;
++
++	PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
++
++	/* Set IGI value */
++	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
++		return (u8)val;
++
++	if (path == BB_PATH_A)
++		val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC);
++#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	else if (path == BB_PATH_B)
++		val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3);
++#endif
++
++#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++	else if (path == BB_PATH_C)
++		val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3);
++#endif
++
++#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	else if (path == BB_PATH_D)
++		val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3);
++#endif
++	return (u8)val;
++}
++
++void phydm_fa_cnt_statistics_jgr3(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
++	u32 ret_value = 0;
++	u32 cck_enable = 0;
++
++	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
++		return;
++
++	ret_value = odm_get_bb_reg(dm, R_0x2d20, MASKDWORD);
++	fa_t->cnt_fast_fsync = ret_value & 0xffff;
++	fa_t->cnt_sb_search_fail = (ret_value & 0xffff0000) >> 16;
++
++	ret_value = odm_get_bb_reg(dm, R_0x2d04, MASKDWORD);
++	fa_t->cnt_parity_fail = (ret_value & 0xffff0000) >> 16;
++
++	ret_value = odm_get_bb_reg(dm, R_0x2d08, MASKDWORD);
++	fa_t->cnt_rate_illegal = ret_value & 0xffff;
++	fa_t->cnt_crc8_fail = (ret_value & 0xffff0000) >> 16;
++
++	ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
++	fa_t->cnt_mcs_fail = ret_value & 0xffff;
++
++	/* read CCK CRC32 counter */
++	ret_value = odm_get_bb_reg(dm, R_0x2c04, MASKDWORD);
++	fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
++	fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16;
++
++	/* read OFDM CRC32 counter */
++	ret_value = odm_get_bb_reg(dm, R_0x2c14, MASKDWORD);
++	fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
++	fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;
++
++	/* read OFDM2 CRC32 counter */
++	ret_value = odm_get_bb_reg(dm, R_0x2c1c, MASKDWORD);
++	fa_t->cnt_ofdm2_crc32_ok = ret_value & 0xffff;
++	fa_t->cnt_ofdm2_crc32_error = (ret_value & 0xffff0000) >> 16;
++
++	/* read HT CRC32 counter */
++	ret_value = odm_get_bb_reg(dm, R_0x2c10, MASKDWORD);
++	fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
++	fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;
++
++	/* read HT2 CRC32 counter */
++	ret_value = odm_get_bb_reg(dm, R_0x2c18, MASKDWORD);
++	fa_t->cnt_ht2_crc32_ok = ret_value & 0xffff;
++	fa_t->cnt_ht2_crc32_error = (ret_value & 0xffff0000) >> 16;
++
++	/*for VHT part */
++	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
++	    ODM_RTL8814B)) {
++		/*read VHT CRC32 counter */
++		ret_value = odm_get_bb_reg(dm, R_0x2c0c, MASKDWORD);
++		fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
++		fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16;
++
++		/*read VHT2 CRC32 counter */
++		ret_value = odm_get_bb_reg(dm, R_0x2c54, MASKDWORD);
++		fa_t->cnt_vht2_crc32_ok = ret_value & 0xffff;
++		fa_t->cnt_vht2_crc32_error = (ret_value & 0xffff0000) >> 16;
++
++		ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
++		fa_t->cnt_mcs_fail_vht = (ret_value & 0xffff0000) >> 16;
++
++		ret_value = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD);
++		fa_t->cnt_crc8_fail_vhta = ret_value & 0xffff;
++		fa_t->cnt_crc8_fail_vhtb = (ret_value & 0xffff0000) >> 16;
++	} else {
++		fa_t->cnt_vht_crc32_error = 0;
++		fa_t->cnt_vht_crc32_ok = 0;
++		fa_t->cnt_vht2_crc32_error = 0;
++		fa_t->cnt_vht2_crc32_ok = 0;
++		fa_t->cnt_mcs_fail_vht = 0;
++		fa_t->cnt_crc8_fail_vhta = 0;
++		fa_t->cnt_crc8_fail_vhtb = 0;
++	}
++
++	/* @calculate OFDM FA counter instead of reading brk_cnt*/
++	fa_t->cnt_ofdm_fail = fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal +
++			      fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail +
++			      fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail +
++			      fa_t->cnt_mcs_fail_vht + fa_t->cnt_crc8_fail_vhta;
++
++	/* Read CCK FA counter */
++	fa_t->cnt_cck_fail = odm_get_bb_reg(dm, R_0x1a5c, MASKLWORD);
++
++	/* read CCK/OFDM CCA counter */
++	ret_value = odm_get_bb_reg(dm, R_0x2c08, MASKDWORD);
++	fa_t->cnt_ofdm_cca = ((ret_value & 0xffff0000) >> 16);
++	fa_t->cnt_cck_cca = ret_value & 0xffff;
++
++	/* @CCK RxIQ weighting = 1 => 0x1a14[9:8]=0x0 */
++	cck_enable = odm_get_bb_reg(dm, R_0x1a14, 0x300);
++	if (cck_enable == 0x0) { /* @if(*dm->band_type == ODM_BAND_2_4G) */
++		fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail;
++		fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;
++	} else {
++		fa_t->cnt_all = fa_t->cnt_ofdm_fail;
++		fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;
++	}
++}
++
++#endif
++
++void phydm_write_dig_reg_c50(void *dm_void, u8 igi)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
++
++	odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), igi);
++
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
++		odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), igi);
++	#endif
++
++	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
++		odm_set_bb_reg(dm, ODM_REG(IGI_C, dm), ODM_BIT(IGI, dm), igi);
++		odm_set_bb_reg(dm, ODM_REG(IGI_D, dm), ODM_BIT(IGI, dm), igi);
++	}
++	#endif
++}
++
++void phydm_write_dig_reg(void *dm_void, u8 igi)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	u8 rf_gain = 0;
++
++	PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
++
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		phydm_write_dig_reg_jgr3(dm, igi);
++	else
++	#endif
++		phydm_write_dig_reg_c50(dm, igi);
++
++	#if (RTL8721D_SUPPORT)
++	if (dm->invalid_mode) {
++		if (igi <= 0x10)
++			rf_gain = 0xfa;
++		else if (igi <= 0x40)
++			rf_gain = 0xe3 + 0x20 - (igi >> 1);
++		else if (igi <= 0x50)
++			rf_gain = 0xcb - (igi >> 1);
++		else if (igi <= 0x5e)
++			rf_gain = 0x92 - (igi >> 1);
++		else if (igi <= 0x64)
++			rf_gain = 0x74 - (igi >> 1);
++		else
++			rf_gain = (0x3d > (igi >> 1)) ? (0x3d - (igi >> 1)) : 0;
++		odm_set_bb_reg(dm, R_0x850, 0x1fe0, rf_gain);
++	}
++	#endif
++
++	if (igi == dig_t->cur_ig_value)
++		dig_t->igi_trend = DIG_STABLE;
++	else if (igi > dig_t->cur_ig_value)
++		dig_t->igi_trend = DIG_INCREASING;
++	else
++		dig_t->igi_trend = DIG_DECREASING;
++
++	PHYDM_DBG(dm, DBG_DIG, "Update IGI:0x%x -> 0x%x\n",
++		  dig_t->cur_ig_value, igi);
++
++	dig_t->cur_ig_value = igi;
++}
++
++void odm_write_dig(void *dm_void, u8 new_igi)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
++
++	PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
++
++	/* @1 Check IGI by upper bound */
++	if (adaptivity->igi_lmt_en &&
++	    new_igi > adaptivity->adapt_igi_up && dm->is_linked) {
++		new_igi = adaptivity->adapt_igi_up;
++
++		PHYDM_DBG(dm, DBG_DIG, "Force Adaptivity Up-bound=((0x%x))\n",
++			  new_igi);
++	}
++
++	#if (RTL8192F_SUPPORT)
++	if ((dm->support_ic_type & ODM_RTL8192F) &&
++	    dm->cut_version == ODM_CUT_A &&
++	    new_igi > 0x38) {
++		new_igi = 0x38;
++		PHYDM_DBG(dm, DBG_DIG,
++			  "Force 92F Adaptivity Up-bound=((0x%x))\n", new_igi);
++	}
++	#endif
++
++	if (dig_t->cur_ig_value != new_igi) {
++		#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
++		/* @Modify big jump step for 8822B and 8197F */
++		if (dm->support_ic_type &
++		    (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F))
++			phydm_set_big_jump_step(dm, new_igi);
++		#endif
++
++		#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
++		/* Set IGI value of CCK for new CCK AGC */
++		if (dm->cck_new_agc &&
++		    (dm->support_ic_type & PHYSTS_2ND_TYPE_IC))
++			odm_set_bb_reg(dm, R_0xa0c, 0x3f00, (new_igi >> 1));
++		#endif
++
++		/*@Add by YuChen for USB IO too slow issue*/
++		if (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
++			if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
++			    new_igi < dig_t->cur_ig_value) {
++				dig_t->cur_ig_value = new_igi;
++				phydm_adaptivity(dm);
++			}
++		} else {
++			if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
++			    new_igi > dig_t->cur_ig_value) {
++				dig_t->cur_ig_value = new_igi;
++				phydm_adaptivity(dm);
++			}
++		}
++		phydm_write_dig_reg(dm, new_igi);
++	} else {
++		dig_t->igi_trend = DIG_STABLE;
++	}
++
++	PHYDM_DBG(dm, DBG_DIG, "[%s]New_igi=((0x%x))\n\n",
++		  ((dig_t->igi_trend == DIG_STABLE) ? "=" :
++		  ((dig_t->igi_trend == DIG_INCREASING) ? "+" : "-")),
++		  new_igi);
++}
++
++u8 phydm_get_igi_reg_val(void *dm_void, enum bb_path path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 val = 0;
++	u32 bit_map = ODM_BIT(IGI, dm);
++
++	switch (path) {
++	case BB_PATH_A:
++		val = odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), bit_map);
++		break;
++	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++	case BB_PATH_B:
++		val = odm_get_bb_reg(dm, ODM_REG(IGI_B, dm), bit_map);
++		break;
++	#endif
++
++	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++	case BB_PATH_C:
++		val = odm_get_bb_reg(dm, ODM_REG(IGI_C, dm), bit_map);
++		break;
++	#endif
++
++	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	case BB_PATH_D:
++		val = odm_get_bb_reg(dm, ODM_REG(IGI_D, dm), bit_map);
++		break;
++	#endif
++
++	default:
++		break;
++	}
++
++	return (u8)val;
++}
++
++u8 phydm_get_igi(void *dm_void, enum bb_path path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 val = 0;
++
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		val = phydm_get_igi_reg_val_jgr3(dm, path);
++	else
++	#endif
++		val = phydm_get_igi_reg_val(dm, path);
++
++	return val;
++}
++
++void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (val_len != 1) {
++		PHYDM_DBG(dm, ODM_COMP_API, "[Error][DIG]Need val_len=1\n");
++		return;
++	}
++
++	odm_write_dig(dm, (u8)(*val_buf));
++}
++
++void odm_pause_dig(void *dm_void, enum phydm_pause_type type,
++		   enum phydm_pause_level lv, u8 igi_input)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 rpt = false;
++	u32 igi = (u32)igi_input;
++
++	PHYDM_DBG(dm, DBG_DIG, "[%s]type=%d, LV=%d, igi=0x%x\n", __func__, type,
++		  lv, igi);
++
++	switch (type) {
++	case PHYDM_PAUSE:
++	case PHYDM_PAUSE_NO_SET: {
++		rpt = phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, lv, 1, &igi);
++		break;
++	}
++
++	case PHYDM_RESUME: {
++		rpt = phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, lv, 1, &igi);
++		break;
++	}
++	default:
++		PHYDM_DBG(dm, DBG_DIG, "Wrong type\n");
++		break;
++	}
++
++	PHYDM_DBG(dm, DBG_DIG, "DIG pause_result=%d\n", rpt);
++}
++
++boolean
++phydm_dig_abort(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++#endif
++
++	/* support_ability */
++	if ((!(dm->support_ability & ODM_BB_FA_CNT)) ||
++	    (!(dm->support_ability & ODM_BB_DIG))) {
++		PHYDM_DBG(dm, DBG_DIG, "[DIG] Not Support\n");
++		return true;
++	}
++
++	if (dm->pause_ability & ODM_BB_DIG) {
++		PHYDM_DBG(dm, DBG_DIG, "Return: Pause DIG in LV=%d\n",
++			  dm->pause_lv_table.lv_dig);
++		return true;
++	}
++
++	if (*dm->is_scan_in_process) {
++		PHYDM_DBG(dm, DBG_DIG, "Return: Scan in process\n");
++		return true;
++	}
++
++	if (dm->dm_dig_table.fw_dig_enable) {
++		PHYDM_DBG(dm, DBG_DIG, "Return: FW DIG enable\n");
++		return true;
++	}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++#if OS_WIN_FROM_WIN7(OS_VERSION)
++	if (IsAPModeExist(adapter) && ((PADAPTER)(adapter))->bInHctTest) {
++		PHYDM_DBG(dm, DBG_DIG, " Return: Is AP mode or In HCT Test\n");
++		return true;
++	}
++#endif
++#endif
++
++	return false;
++}
++
++#ifdef PHYDM_HW_IGI
++#ifdef BB_RAM_SUPPORT
++void phydm_rd_hwigi_pre_setting(void *dm_void, u32 *_used, char *output,
++				u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 igi_ofst = 0x0;
++	u32 t1, t2, t3 = 0x0;
++
++	igi_ofst = (u8)odm_get_bb_reg(dm, R_0x1e80, MASKBYTE0);
++	t1 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE1) * 400;
++	t2 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE2) * 400;
++	t3 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE3) * 400;
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "igi_offset:0x%x, t1:%d(ns), t2:%d(ns), t3:%d(ns)\n",
++		 igi_ofst, t1, t2, t3);
++}
++
++void phydm_set_hwigi_pre_setting(void *dm_void, u8 igi_ofst, u8 t1, u8 t2,
++				 u8 t3)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 reg_0x1e80 = 0;
++
++	reg_0x1e80 = igi_ofst + (t1 << 8) + (t2 << 16) + (t3 << 24);
++	odm_set_bb_reg(dm, R_0x1e80, MASKDWORD, reg_0x1e80);
++}
++
++void phydm_rd_hwigi_table(void *dm_void, u8 macid, u32 *_used, char *output,
++			  u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	boolean hwigi_en = false;
++	u8 hwigi = 0x0;
++	u8 hwigi_rx_offset = 0x0;
++	u32 reg_0x1e84 = 0x0;
++
++	reg_0x1e84 |= (macid & 0x3f) << 24; /*macid*/
++	reg_0x1e84 |= BIT(31); /*read_en*/
++	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
++
++	hwigi_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(15));
++	hwigi = (u8)odm_get_bb_reg(dm, R_0x2de8, 0x7f00);
++	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "(macid:%d) hwigi_en:%d, hwigi:0x%x\n", macid, hwigi_en,
++		 hwigi);
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_wt_hwigi_table(void *dm_void, u8 macid, boolean hwigi_en, u8 hwigi)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
++	u32 reg_0x1e84 = 0;
++
++	if (macid > 63)
++		macid = 63;
++
++	dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[macid];
++	dm_ram_per_sta->hw_igi_en = hwigi_en;
++	dm_ram_per_sta->hw_igi = hwigi;
++
++	reg_0x1e84 = (dm_ram_per_sta->tx_pwr_offset0_en << 15) +
++		     ((dm_ram_per_sta->tx_pwr_offset0 & 0x7f) << 8) +
++		     (dm_ram_per_sta->tx_pwr_offset1_en << 23) +
++		     ((dm_ram_per_sta->tx_pwr_offset1 & 0x7f) << 16);
++
++	reg_0x1e84 |= (hwigi_en << 7) + (hwigi & 0x7f);
++	reg_0x1e84 |= (macid & 0x3f) << 24;/*macid*/
++	reg_0x1e84 |= BIT(30); /*write_en*/
++	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
++	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000); /*read_en*/
++	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /*disable rd/wt*/
++}
++
++void phydm_rst_hwigi(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
++	u32 reg_0x1e84 = 0;
++	u8 i = 0;
++
++	PHYDM_DBG(dm, DBG_DIG, "reset hwigi!\n");
++
++	for (i = 0; i < 64; i++) {
++		dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[i];
++		dm_ram_per_sta->hw_igi_en = false;
++		dm_ram_per_sta->hw_igi = 0x0;
++
++		reg_0x1e84 = (dm_ram_per_sta->tx_pwr_offset0_en << 15) +
++			     ((dm_ram_per_sta->tx_pwr_offset0 & 0x7f) << 8) +
++			     (dm_ram_per_sta->tx_pwr_offset1_en << 23) +
++			     ((dm_ram_per_sta->tx_pwr_offset1 & 0x7f) << 16);
++
++		reg_0x1e84 |= (i & 0x3f) << 24;
++		reg_0x1e84 |= BIT(30);
++		odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
++	}
++
++	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000);
++	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0);
++}
++
++void phydm_hwigi_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
++	u8 igi_ofst = 0x0;
++	u8 t1 = 0x0;
++	u8 t2 = 0x0;
++	u8 t3 = 0x0;
++
++	t1 = 0x55; /*34 us*/
++	t3 = 0x55; /*34 us*/
++
++	bb_ctrl->hwigi_watchdog_en = false;
++	phydm_set_hwigi_pre_setting(dm, igi_ofst, t1, t2, t3);
++}
++
++void phydm_hwigi(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *sta = NULL;
++	struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
++	struct rssi_info *rssi = NULL;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
++	u8 sta_cnt = 0;
++	u8 i = 0;
++	u8 hwigi = 0x0;
++	u8 macid = 0;
++
++	if (!(bb_ctrl->hwigi_watchdog_en)) {
++		return;
++	} else if (dm->first_disconnect) {
++		phydm_rst_hwigi(dm);
++		return;
++	}
++
++	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
++		sta = dm->phydm_sta_info[i];
++		if (is_sta_active(sta)) {
++			sta_cnt++;
++
++			if (sta->mac_id > 63)
++				macid = 63;
++			else
++				macid = sta->mac_id;
++
++			dm_ram_per_sta = &bb_ctrl->pram_sta_ctrl[macid];
++			rssi = &sta->rssi_stat;
++			PHYDM_DBG(dm, DBG_DIG,
++				  "STA_id=%d, MACID=%d, RSSI=%d, hwigi_en=%d, hwigi=0x%x\n",
++				  i, sta->mac_id, rssi->rssi,
++				  dm_ram_per_sta->hw_igi_en,
++				  dm_ram_per_sta->hw_igi);
++
++			hwigi = MAX_2((u8)(rssi->rssi + 10),
++				      dig_t->cur_ig_value);
++
++			if (rssi->rssi + 10 > DIG_MAX_PERFORMANCE_MODE)
++				hwigi = DIG_MAX_PERFORMANCE_MODE;
++			else if (rssi->rssi + 10 < DIG_MIN_PERFORMANCE)
++				hwigi = DIG_MIN_PERFORMANCE;
++
++			if (dm_ram_per_sta->hw_igi == hwigi) {
++				PHYDM_DBG(dm, DBG_DIG,
++					  "hwigi not change!\n");
++				return;
++			}
++
++			PHYDM_DBG(dm, DBG_DIG,
++				  "hwigi update: ((0x%x)) -> ((0x%x))\n",
++				  dm_ram_per_sta->hw_igi, hwigi);
++
++			phydm_wt_hwigi_table(dm, sta->mac_id, true, hwigi);
++
++			if (sta_cnt == dm->number_linked_client)
++				break;
++		}
++	}
++}
++
++void phydm_hwigi_dbg(void *dm_void, char input[][16], u32 *_used,
++		     char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
++	char help[] = "-h";
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 var1[7] = {0};
++	u8 i = 0;
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Disable/Enable watchdog : {0/1}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Set hwigi pre-setting: {2} {IGI offset} {T1(after data tx)} {T2(after Rx)} {T3(after rsp tx)}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Set hwigi table: {3} {en} {value} {macid}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Read hwigi : {4} {macid(0~63), 255:all}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Reset all hwigi : {5}\n");
++	} else {
++		for (i = 0; i < 7; i++) {
++			if (input[i + 1])
++				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
++					     &var1[i]);
++		}
++		switch (var1[0]) {
++		case 0:
++		case 1:
++			bb_ctrl->hwigi_watchdog_en = (var1[0]) ? true : false;
++			break;
++		case 2:
++			phydm_set_hwigi_pre_setting(dm, (u8)var1[1],
++						    (u8)var1[2], (u8)var1[3],
++						    (u8)var1[4]);
++			break;
++		case 3:
++			phydm_wt_hwigi_table(dm, (u8)var1[3], (boolean)var1[1],
++					     (boolean)var1[2]);
++			break;
++		case 4:
++			phydm_rd_hwigi_pre_setting(dm, &used, output, &out_len);
++			if ((u8)var1[1] == 0xff)
++				for (i = 0; i < 64; i++)
++					phydm_rd_hwigi_table(dm, i, &used,
++							     output, &out_len);
++			else
++				phydm_rd_hwigi_table(dm, (u8)var1[1], &used,
++						     output, &out_len);
++			break;
++		case 5:
++			phydm_rst_hwigi(dm);
++			break;
++		}
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++#endif
++#endif
++
++void phydm_dig_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	struct phydm_fa_struct *false_alm_cnt = &dm->false_alm_cnt;
++#endif
++	u32 ret_value = 0;
++	u8 i;
++
++	dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
++	dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
++	dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
++
++	dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);
++
++	dig_t->fa_th[0] = 250;
++	dig_t->fa_th[1] = 500;
++	dig_t->fa_th[2] = 750;
++	dig_t->is_dbg_fa_th = false;
++	dig_t->igi_dyn_up_hit = false;
++	dig_t->fw_dig_enable = false;
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	/* @For RTL8881A */
++	false_alm_cnt->cnt_ofdm_fail_pre = 0;
++#endif
++
++	dig_t->rx_gain_range_max = DIG_MAX_BALANCE_MODE;
++	dig_t->rx_gain_range_min = dig_t->cur_ig_value;
++
++#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
++	dig_t->enable_adjust_big_jump = 1;
++	if (dm->support_ic_type & ODM_RTL8822B)
++		ret_value = odm_get_bb_reg(dm, R_0x8c8, MASKLWORD);
++	else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
++		ret_value = odm_get_bb_reg(dm, R_0xc74, MASKLWORD);
++
++	dig_t->big_jump_step1 = (u8)(ret_value & 0xe) >> 1;
++	dig_t->big_jump_step2 = (u8)(ret_value & 0x30) >> 4;
++	dig_t->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6;
++
++	if (dm->support_ic_type &
++	    (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)) {
++		for (i = 0; i < sizeof(dig_t->big_jump_lmt); i++) {
++			if (dig_t->big_jump_lmt[i] == 0)
++				dig_t->big_jump_lmt[i] = 0x64;
++				/* Set -10dBm as default value */
++		}
++	}
++#endif
++
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++		dm->original_dig_restore = true;
++		dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
++		dm->tdma_dig_timer_ms = DIG_TIMER_MS;
++	#endif
++	dig_t->tdma_force_l_igi = 0xff;
++	dig_t->tdma_force_h_igi = 0xff;
++#endif
++#ifdef CFG_DIG_DAMPING_CHK
++	phydm_dig_recorder_reset(dm);
++	dig_t->dig_dl_en = 1;
++#endif
++
++#ifdef PHYDM_HW_IGI
++	phydm_hwigi_init(dm);
++#endif
++}
++void phydm_dig_abs_boundary_decision(struct dm_struct *dm, boolean is_dfs_band)
++{
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
++
++	if (is_dfs_band) {
++		if (*dm->band_width == CHANNEL_WIDTH_20){
++			if (dm->support_ic_type &
++				(ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
++				if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
++					dig_t->dm_dig_min = DIG_MIN_DFS + 2;
++				else
++					dig_t->dm_dig_min = DIG_MIN_DFS;
++			}
++			else
++				dig_t->dm_dig_min = DIG_MIN_DFS;
++		}
++		else
++			dig_t->dm_dig_min = DIG_MIN_DFS;
++
++		dig_t->dig_max_of_min = DIG_MIN_DFS;
++		dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
++	} else if (!dm->is_linked) {
++		dig_t->dm_dig_max = DIG_MAX_COVERAGR;
++		dig_t->dm_dig_min = DIG_MIN_COVERAGE;
++	} else {
++		if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {
++		/*service > 2 devices*/
++			dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
++			#if (DIG_HW == 1)
++			dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
++			#else
++			dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
++			#endif
++		} else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {
++		/*service 1 devices*/
++			if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
++			    dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
++			/*dig_max shouldn't be too high because of adaptivity*/
++				dig_t->dm_dig_max =
++					MIN_2((adapt->th_l2h + 40),
++					      DIG_MAX_PERFORMANCE_MODE);
++			else
++				dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;
++
++			dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
++		}
++
++		if (dm->support_ic_type &
++		    (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
++			dig_t->dm_dig_min = 0x1c;
++		else if (dm->support_ic_type & ODM_RTL8197F)
++			dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
++		else
++			dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
++	}
++
++	PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
++		  dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
++}
++
++void phydm_dig_dym_boundary_decision(struct dm_struct *dm, boolean is_dfs_band)
++{
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++#ifdef CFG_DIG_DAMPING_CHK
++	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
++#endif
++	u8 offset = 15, tmp_max = 0;
++	u8 max_of_rssi_min = 0;
++
++	PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
++
++	if (!dm->is_linked) {
++		/*@if no link, always stay at lower bound*/
++		dig_t->rx_gain_range_max = dig_t->dig_max_of_min;
++		dig_t->rx_gain_range_min = dig_t->dm_dig_min;
++
++		PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
++			  dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
++		return;
++	}
++
++	PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n", dm->rssi_min, offset);
++
++	/* @DIG lower bound */
++	if (is_dfs_band)
++		dig_t->rx_gain_range_min = dig_t->dm_dig_min;
++	else if (dm->rssi_min > dig_t->dig_max_of_min)
++		dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
++	else if (dm->rssi_min < dig_t->dm_dig_min)
++		dig_t->rx_gain_range_min = dig_t->dm_dig_min;
++	else
++		dig_t->rx_gain_range_min = dm->rssi_min;
++
++#ifdef CFG_DIG_DAMPING_CHK
++	/*@Limit Dyn min by damping*/
++	if (dig_t->dig_dl_en &&
++	    dig_rc->damping_limit_en &&
++	    dig_t->rx_gain_range_min < dig_rc->damping_limit_val) {
++		PHYDM_DBG(dm, DBG_DIG,
++			  "[Limit by Damping] Dig_dyn_min=0x%x -> 0x%x\n",
++			  dig_t->rx_gain_range_min, dig_rc->damping_limit_val);
++
++		dig_t->rx_gain_range_min = dig_rc->damping_limit_val;
++	}
++#endif
++
++	/* @DIG upper bound */
++	tmp_max = dig_t->rx_gain_range_min + offset;
++	if (dig_t->rx_gain_range_min != dm->rssi_min) {
++		max_of_rssi_min = dm->rssi_min + offset;
++		if (tmp_max > max_of_rssi_min)
++			tmp_max = max_of_rssi_min;
++	}
++
++	if (tmp_max > dig_t->dm_dig_max)
++		dig_t->rx_gain_range_max = dig_t->dm_dig_max;
++	else if (tmp_max < dig_t->dm_dig_min)
++		dig_t->rx_gain_range_max = dig_t->dm_dig_min;
++	else
++		dig_t->rx_gain_range_max = tmp_max;
++
++	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	/* @1 Force Lower Bound for AntDiv */
++	if (!dm->is_one_entry_only &&
++	    (dm->support_ability & ODM_BB_ANT_DIV) &&
++	    (dm->ant_div_type == CG_TRX_HW_ANTDIV ||
++	     dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
++		if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
++			dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
++		else
++			dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
++
++		PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
++			  dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
++	}
++	#endif
++
++	PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
++		  dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
++}
++
++void phydm_dig_abnormal_case(struct dm_struct *dm)
++{
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++
++	/* @Abnormal lower bound case */
++	if (dig_t->rx_gain_range_min > dig_t->rx_gain_range_max)
++		dig_t->rx_gain_range_min = dig_t->rx_gain_range_max;
++
++	PHYDM_DBG(dm, DBG_DIG, "Abnoraml checked {Max, Min}={0x%x, 0x%x}\n",
++		  dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
++}
++
++u8 phydm_new_igi_by_fa(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *step_size)
++{
++	boolean dig_go_up_check = true;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++
++	if (fa_cnt > dig_t->fa_th[2] && dig_go_up_check)
++		igi = igi + step_size[0];
++	else if ((fa_cnt > dig_t->fa_th[1]) && dig_go_up_check)
++		igi = igi + step_size[1];
++	else if (fa_cnt < dig_t->fa_th[0])
++		igi = igi - step_size[2];
++
++	return igi;
++}
++
++u8 phydm_get_new_igi(struct dm_struct *dm, u8 igi, u32 fa_cnt,
++		     boolean is_dfs_band)
++{
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	u8 step[3] = {0};
++
++	if (dm->is_linked) {
++		if (dm->pre_rssi_min <= dm->rssi_min) {
++			PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n");
++			step[0] = 2;
++			step[1] = 1;
++			step[2] = 2;
++		} else {
++			step[0] = 4;
++			step[1] = 2;
++			step[2] = 2;
++		}
++	} else {
++		step[0] = 2;
++		step[1] = 1;
++		step[2] = 2;
++	}
++
++	PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
++		  step[0]);
++
++	if (dm->first_connect) {
++		if (is_dfs_band) {
++			if (dm->rssi_min > DIG_MAX_DFS)
++				igi = DIG_MAX_DFS;
++			else
++				igi = dm->rssi_min;
++			PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n",
++				  dig_t->rx_gain_range_max);
++		} else {
++			igi = dig_t->rx_gain_range_min;
++		}
++
++		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++		#if (RTL8812A_SUPPORT)
++		if (dm->support_ic_type == ODM_RTL8812)
++			odm_config_bb_with_header_file(dm,
++						       CONFIG_BB_AGC_TAB_DIFF);
++		#endif
++		#endif
++		PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi);
++	} else if (dm->is_linked) {
++		PHYDM_DBG(dm, DBG_DIG, "Adjust IGI @ linked\n");
++		/* @4 Abnormal # beacon case */
++		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++		if (dm->phy_dbg_info.num_qry_beacon_pkt < 5 &&
++		    fa_cnt < DM_DIG_FA_TH1 && dm->bsta_state &&
++		    dm->support_ic_type != ODM_RTL8723D) {
++			dig_t->rx_gain_range_min = 0x1c;
++			igi = dig_t->rx_gain_range_min;
++			PHYDM_DBG(dm, DBG_DIG, "Beacon_num=%d,force igi=0x%x\n",
++				  dm->phy_dbg_info.num_qry_beacon_pkt, igi);
++		} else {
++			igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
++		}
++		#else
++		igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
++		#endif
++	} else {
++		/* @2 Before link */
++		PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
++
++		if (dm->first_disconnect) {
++			igi = dig_t->dm_dig_min;
++			PHYDM_DBG(dm, DBG_DIG,
++				  "First disconnect:foce IGI to lower bound\n");
++		} else {
++			PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n",
++				  igi, fa_cnt);
++
++			igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
++		}
++	}
++
++	/*@Check IGI by dyn-upper/lower bound */
++	if (igi < dig_t->rx_gain_range_min)
++		igi = dig_t->rx_gain_range_min;
++
++	if (igi >= dig_t->rx_gain_range_max) {
++		igi = dig_t->rx_gain_range_max;
++		dig_t->igi_dyn_up_hit = true;
++	} else {
++		dig_t->igi_dyn_up_hit = false;
++	}
++	PHYDM_DBG(dm, DBG_DIG, "igi_dyn_up_hit=%d\n",
++		  dig_t->igi_dyn_up_hit);
++
++	PHYDM_DBG(dm, DBG_DIG, "fa_cnt = %d, IGI: 0x%x -> 0x%x\n",
++		  fa_cnt, dig_t->cur_ig_value, igi);
++
++	return igi;
++}
++
++boolean phydm_dig_dfs_mode_en(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	boolean dfs_mode_en = false;
++
++	/* @Modify lower bound for DFS band */
++	if (dm->is_dfs_band) {
++		#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++		dfs_mode_en = true;
++		#else
++		if (phydm_dfs_master_enabled(dm))
++			dfs_mode_en = true;
++		#endif
++		PHYDM_DBG(dm, DBG_DIG, "In DFS band\n");
++	}
++	return dfs_mode_en;
++}
++
++void phydm_dig(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_fa_struct *fa = &dm->false_alm_cnt;
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++	struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
++#endif
++	u8 igi = dig_t->cur_ig_value;
++	u8 new_igi = 0x20;
++	u32 fa_cnt = fa->cnt_all;
++	boolean dfs_mode_en = false;
++
++#ifdef PHYDM_DCC_ENHANCE
++	if (dm->dm_dcc_info.dcc_en)
++		fa_cnt = fa->cnt_ofdm_fail; /*OFDM FA only*/
++#endif
++
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++	if (!(dm->original_dig_restore)) {
++		if (dig_t->cur_ig_value_tdma == 0)
++			dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
++
++		igi = dig_t->cur_ig_value_tdma;
++		fa_cnt = falm_cnt_acc->cnt_all_1sec;
++	}
++#endif
++
++	if (phydm_dig_abort(dm)) {
++		dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);
++		return;
++	}
++
++	PHYDM_DBG(dm, DBG_DIG, "%s Start===>\n", __func__);
++	PHYDM_DBG(dm, DBG_DIG,
++		  "is_linked=%d, RSSI=%d, 1stConnect=%d, 1stDisconnect=%d\n",
++		  dm->is_linked, dm->rssi_min,
++		  dm->first_connect, dm->first_disconnect);
++
++	PHYDM_DBG(dm, DBG_DIG, "DIG ((%s)) mode\n",
++		  (*dm->bb_op_mode ? "Balance" : "Performance"));
++
++	/*@DFS mode enable check*/
++	dfs_mode_en = phydm_dig_dfs_mode_en(dm);
++
++#ifdef CFG_DIG_DAMPING_CHK
++	/*Record IGI History*/
++	phydm_dig_recorder(dm, igi, fa_cnt);
++
++	/*@DIG Damping Check*/
++	phydm_dig_damping_chk(dm);
++#endif
++
++	/*@Absolute Boundary Decision */
++	phydm_dig_abs_boundary_decision(dm, dfs_mode_en);
++
++	/*@Dynamic Boundary Decision*/
++	phydm_dig_dym_boundary_decision(dm, dfs_mode_en);
++
++	/*@Abnormal case check*/
++	phydm_dig_abnormal_case(dm);
++
++	/*@FA threshold decision */
++	phydm_fa_threshold_check(dm, dfs_mode_en);
++
++	/*Select new IGI by FA */
++	new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
++
++	/* @1 Update status */
++	#ifdef PHYDM_TDMA_DIG_SUPPORT
++	if (!(dm->original_dig_restore)) {
++		dig_t->cur_ig_value_tdma = new_igi;
++		/*@It is possible fa_acc_1sec_tsf >= */
++		/*@1sec while tdma_dig_state == 0*/
++		if (dig_t->tdma_dig_state != 0)
++			odm_write_dig(dm, dig_t->cur_ig_value_tdma);
++	} else
++	#endif
++		odm_write_dig(dm, new_igi);
++}
++
++void phydm_dig_lps_32k(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 current_igi = dm->rssi_min;
++
++	odm_write_dig(dm, current_igi);
++}
++
++void phydm_dig_by_rssi_lps(void *dm_void)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fa_struct *falm_cnt;
++
++	u8 rssi_lower = DIG_MIN_LPS; /* @0x1E or 0x1C */
++	u8 current_igi = dm->rssi_min;
++
++	falm_cnt = &dm->false_alm_cnt;
++	if (phydm_dig_abort(dm))
++		return;
++
++	current_igi = current_igi + RSSI_OFFSET_DIG_LPS;
++	PHYDM_DBG(dm, DBG_DIG, "%s==>\n", __func__);
++
++	/* Using FW PS mode to make IGI */
++	/* @Adjust by  FA in LPS MODE */
++	if (falm_cnt->cnt_all > DM_DIG_FA_TH2_LPS)
++		current_igi = current_igi + 4;
++	else if (falm_cnt->cnt_all > DM_DIG_FA_TH1_LPS)
++		current_igi = current_igi + 2;
++	else if (falm_cnt->cnt_all < DM_DIG_FA_TH0_LPS)
++		current_igi = current_igi - 2;
++
++	/* @Lower bound checking */
++
++	/* RSSI Lower bound check */
++	if ((dm->rssi_min - 10) > DIG_MIN_LPS)
++		rssi_lower = (dm->rssi_min - 10);
++	else
++		rssi_lower = DIG_MIN_LPS;
++
++	/* Upper and Lower Bound checking */
++	if (current_igi > DIG_MAX_LPS)
++		current_igi = DIG_MAX_LPS;
++	else if (current_igi < rssi_lower)
++		current_igi = rssi_lower;
++
++	PHYDM_DBG(dm, DBG_DIG, "fa_cnt_all=%d, rssi_min=%d, curr_igi=0x%x\n",
++		  falm_cnt->cnt_all, dm->rssi_min, current_igi);
++	odm_write_dig(dm, current_igi);
++#endif
++}
++
++/* @3============================================================
++ * 3 FASLE ALARM CHECK
++ * 3============================================================
++ */
++void phydm_false_alarm_counter_reg_reset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
++#endif
++	u32 false_alm_cnt = 0;
++
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++	if (!(dm->original_dig_restore)) {
++		if (dig_t->cur_ig_value_tdma == 0)
++			dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
++
++		false_alm_cnt = falm_cnt_acc->cnt_all_1sec;
++	} else
++#endif
++	{
++		false_alm_cnt = falm_cnt->cnt_all;
++	}
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		/* @reset CCK FA counter */
++		odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 0);
++		odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 2);
++
++		/* @reset CCK CCA counter */
++		odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 0);
++		odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 2);
++
++		/* @Disable common rx clk gating => WLANBB-1106*/
++		odm_set_bb_reg(dm, R_0x1d2c, BIT(31), 0);
++		/* @reset OFDM CCA counter, OFDM FA counter*/
++		phydm_reset_bb_hw_cnt(dm);
++		/* @Enable common rx clk gating => WLANBB-1106*/
++		odm_set_bb_reg(dm, R_0x1d2c, BIT(31), 1);
++	}
++#endif
++#if (ODM_IC_11N_SERIES_SUPPORT)
++	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		/* @reset false alarm counter registers*/
++		odm_set_bb_reg(dm, R_0xc0c, BIT(31), 1);
++		odm_set_bb_reg(dm, R_0xc0c, BIT(31), 0);
++		odm_set_bb_reg(dm, R_0xd00, BIT(27), 1);
++		odm_set_bb_reg(dm, R_0xd00, BIT(27), 0);
++
++		/* @update ofdm counter*/
++		/* @update page C counter*/
++		odm_set_bb_reg(dm, R_0xc00, BIT(31), 0);
++		/* @update page D counter*/
++		odm_set_bb_reg(dm, R_0xd00, BIT(31), 0);
++
++		/* @reset CCK CCA counter*/
++		odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 0);
++		odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 2);
++
++		/* @reset CCK FA counter*/
++		odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 0);
++		odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 2);
++
++		/* @reset CRC32 counter*/
++		odm_set_bb_reg(dm, R_0xf14, BIT(16), 1);
++		odm_set_bb_reg(dm, R_0xf14, BIT(16), 0);
++	}
++#endif /* @#if (ODM_IC_11N_SERIES_SUPPORT) */
++
++#if (ODM_IC_11AC_SERIES_SUPPORT)
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		#if (RTL8881A_SUPPORT)
++		/* @Reset FA counter by enable/disable OFDM */
++		if ((dm->support_ic_type == ODM_RTL8881A) &&
++		    false_alm_cnt->cnt_ofdm_fail_pre >= 0x7fff) {
++			/* reset OFDM */
++			odm_set_bb_reg(dm, R_0x808, BIT(29), 0);
++			odm_set_bb_reg(dm, R_0x808, BIT(29), 1);
++			false_alm_cnt->cnt_ofdm_fail_pre = 0;
++			PHYDM_DBG(dm, DBG_FA_CNT, "Reset FA_cnt\n");
++		}
++		#endif /* @#if (RTL8881A_SUPPORT) */
++
++		/* @reset OFDM FA countner */
++		odm_set_bb_reg(dm, R_0x9a4, BIT(17), 1);
++		odm_set_bb_reg(dm, R_0x9a4, BIT(17), 0);
++
++		/* @reset CCK FA counter */
++		odm_set_bb_reg(dm, R_0xa2c, BIT(15), 0);
++		odm_set_bb_reg(dm, R_0xa2c, BIT(15), 1);
++
++		/* @reset CCA counter */
++		phydm_reset_bb_hw_cnt(dm);
++	}
++#endif /* @#if (ODM_IC_11AC_SERIES_SUPPORT) */
++}
++
++void phydm_false_alarm_counter_reg_hold(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		/* @hold cck counter */
++		odm_set_bb_reg(dm, R_0x1a2c, BIT(12), 1);
++		odm_set_bb_reg(dm, R_0x1a2c, BIT(14), 1);
++	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		/*@hold ofdm counter*/
++		/*@hold page C counter*/
++		odm_set_bb_reg(dm, R_0xc00, BIT(31), 1);
++		/*@hold page D counter*/
++		odm_set_bb_reg(dm, R_0xd00, BIT(31), 1);
++
++		/*@hold cck counter*/
++		odm_set_bb_reg(dm, R_0xa2c, BIT(12), 1);
++		odm_set_bb_reg(dm, R_0xa2c, BIT(14), 1);
++	}
++}
++
++#if (ODM_IC_11N_SERIES_SUPPORT)
++void phydm_fa_cnt_statistics_n(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
++	u32 reg = 0;
++
++	if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
++		return;
++
++	/* @hold ofdm & cck counter */
++	phydm_false_alarm_counter_reg_hold(dm);
++
++	reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11N, MASKDWORD);
++	fa_t->cnt_fast_fsync = (reg & 0xffff);
++	fa_t->cnt_sb_search_fail = ((reg & 0xffff0000) >> 16);
++
++	reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11N, MASKDWORD);
++	fa_t->cnt_ofdm_cca = (reg & 0xffff);
++	fa_t->cnt_parity_fail = ((reg & 0xffff0000) >> 16);
++
++	reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11N, MASKDWORD);
++	fa_t->cnt_rate_illegal = (reg & 0xffff);
++	fa_t->cnt_crc8_fail = ((reg & 0xffff0000) >> 16);
++
++	reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11N, MASKDWORD);
++	fa_t->cnt_mcs_fail = (reg & 0xffff);
++
++	fa_t->cnt_ofdm_fail =
++		fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal +
++		fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail +
++		fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail;
++
++	/* read CCK CRC32 counter */
++	fa_t->cnt_cck_crc32_error = odm_get_bb_reg(dm, R_0xf84, MASKDWORD);
++	fa_t->cnt_cck_crc32_ok = odm_get_bb_reg(dm, R_0xf88, MASKDWORD);
++
++	/* read OFDM CRC32 counter */
++	reg = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11N, MASKDWORD);
++	fa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16;
++	fa_t->cnt_ofdm_crc32_ok = reg & 0xffff;
++
++	/* read OFDM2 CRC32 counter */
++	reg = odm_get_bb_reg(dm, R_0xf9c, MASKDWORD);
++	fa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16;
++	fa_t->cnt_ofdm2_crc32_ok = reg & 0xffff;
++
++	/* read HT CRC32 counter */
++	reg = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD);
++	fa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16;
++	fa_t->cnt_ht_crc32_ok = reg & 0xffff;
++
++	/* read HT2 CRC32 counter */
++	reg = odm_get_bb_reg(dm, R_0xf98, MASKDWORD);
++	fa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16;
++	fa_t->cnt_ht2_crc32_ok = reg & 0xffff;
++
++	/* read VHT CRC32 counter */
++	fa_t->cnt_vht_crc32_error = 0;
++	fa_t->cnt_vht_crc32_ok = 0;
++
++	#if (RTL8723D_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8723D) {
++		/* read HT CRC32 agg counter */
++		reg = odm_get_bb_reg(dm, R_0xfb8, MASKDWORD);
++		fa_t->cnt_ht_crc32_error_agg = (reg & 0xffff0000) >> 16;
++		fa_t->cnt_ht_crc32_ok_agg = reg & 0xffff;
++	}
++	#endif
++
++	#if (RTL8188E_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8188E) {
++		reg = odm_get_bb_reg(dm, ODM_REG_SC_CNT_11N, MASKDWORD);
++		fa_t->cnt_bw_lsc = (reg & 0xffff);
++		fa_t->cnt_bw_usc = ((reg & 0xffff0000) >> 16);
++	}
++	#endif
++
++	reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_LSB_11N, MASKBYTE0);
++	fa_t->cnt_cck_fail = reg;
++
++	reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_MSB_11N, MASKBYTE3);
++	fa_t->cnt_cck_fail += (reg & 0xff) << 8;
++
++	reg = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11N, MASKDWORD);
++	fa_t->cnt_cck_cca = ((reg & 0xFF) << 8) | ((reg & 0xFF00) >> 8);
++
++	fa_t->cnt_all_pre = fa_t->cnt_all;
++
++	fa_t->cnt_all = fa_t->cnt_fast_fsync +
++			fa_t->cnt_sb_search_fail +
++			fa_t->cnt_parity_fail +
++			fa_t->cnt_rate_illegal +
++			fa_t->cnt_crc8_fail +
++			fa_t->cnt_mcs_fail +
++			fa_t->cnt_cck_fail;
++
++	fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca + fa_t->cnt_cck_cca;
++}
++#endif
++
++#if (ODM_IC_11AC_SERIES_SUPPORT)
++void phydm_fa_cnt_statistics_ac(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
++	u32 ret_value = 0;
++	u32 cck_enable = 0;
++
++	if (!(dm->support_ic_type & ODM_IC_11AC_SERIES))
++		return;
++
++	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11AC, MASKDWORD);
++	fa_t->cnt_fast_fsync = (ret_value & 0xffff0000) >> 16;
++
++	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11AC, MASKDWORD);
++	fa_t->cnt_sb_search_fail = ret_value & 0xffff;
++
++	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11AC, MASKDWORD);
++	fa_t->cnt_parity_fail = ret_value & 0xffff;
++	fa_t->cnt_rate_illegal = (ret_value & 0xffff0000) >> 16;
++
++	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11AC, MASKDWORD);
++	fa_t->cnt_crc8_fail = ret_value & 0xffff;
++	fa_t->cnt_mcs_fail = (ret_value & 0xffff0000) >> 16;
++
++	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE5_11AC, MASKDWORD);
++	fa_t->cnt_crc8_fail_vhta = ret_value & 0xffff;
++	fa_t->cnt_crc8_fail_vhtb = ret_value & 0xffff0000 >> 16;
++
++	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE6_11AC, MASKDWORD);
++	fa_t->cnt_mcs_fail_vht = ret_value & 0xffff;
++
++	/* read OFDM FA counter */
++	fa_t->cnt_ofdm_fail = odm_get_bb_reg(dm, R_0xf48, MASKLWORD);
++
++	/* Read CCK FA counter */
++	fa_t->cnt_cck_fail = odm_get_bb_reg(dm, ODM_REG_CCK_FA_11AC, MASKLWORD);
++
++	/* read CCK/OFDM CCA counter */
++	ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD);
++	fa_t->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16;
++	fa_t->cnt_cck_cca = ret_value & 0xffff;
++
++	/* read CCK CRC32 counter */
++	ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CRC32_CNT_11AC, MASKDWORD);
++	fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16;
++	fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
++
++	/* read OFDM CRC32 counter */
++	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11AC, MASKDWORD);
++	fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;
++	fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
++
++	/* read OFDM2 CRC32 counter */
++	ret_value = odm_get_bb_reg(dm, R_0xf1c, MASKDWORD);
++	fa_t->cnt_ofdm2_crc32_ok = ret_value & 0xffff;
++	fa_t->cnt_ofdm2_crc32_error = (ret_value & 0xffff0000) >> 16;
++
++	/* read HT CRC32 counter */
++	ret_value = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11AC, MASKDWORD);
++	fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;
++	fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
++
++	/* read HT2 CRC32 counter */
++	ret_value = odm_get_bb_reg(dm, R_0xf18, MASKDWORD);
++	fa_t->cnt_ht2_crc32_ok = ret_value & 0xffff;
++	fa_t->cnt_ht2_crc32_error = (ret_value & 0xffff0000) >> 16;
++
++	/* read VHT CRC32 counter */
++	ret_value = odm_get_bb_reg(dm, ODM_REG_VHT_CRC32_CNT_11AC, MASKDWORD);
++	fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16;
++	fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
++
++	/*read VHT2 CRC32 counter */
++	ret_value = odm_get_bb_reg(dm, R_0xf54, MASKDWORD);
++	fa_t->cnt_vht2_crc32_ok = ret_value & 0xffff;
++	fa_t->cnt_vht2_crc32_error = (ret_value & 0xffff0000) >> 16;
++
++	#if (RTL8881A_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8881A) {
++		u32 tmp = 0;
++
++		if (fa_t->cnt_ofdm_fail >= fa_t->cnt_ofdm_fail_pre) {
++			tmp = fa_t->cnt_ofdm_fail_pre;
++			fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;
++			fa_t->cnt_ofdm_fail = fa_t->cnt_ofdm_fail - tmp;
++		} else {
++			fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;
++		}
++
++		PHYDM_DBG(dm, DBG_FA_CNT,
++			  "[8881]cnt_ofdm_fail{curr,pre}={%d,%d}\n",
++			  fa_t->cnt_ofdm_fail_pre, tmp);
++	}
++	#endif
++
++	cck_enable = odm_get_bb_reg(dm, ODM_REG_BB_RX_PATH_11AC, BIT(28));
++
++	if (cck_enable) { /* @if(*dm->band_type == ODM_BAND_2_4G) */
++		fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail;
++		fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;
++	} else {
++		fa_t->cnt_all = fa_t->cnt_ofdm_fail;
++		fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;
++	}
++}
++#endif
++
++void phydm_get_dbg_port_info(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
++	u32 dbg_port = dm->adaptivity.adaptivity_dbg_port;
++	u32 val = 0;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		fa_t->dbg_port0 = odm_get_bb_reg(dm, R_0x2db4, MASKDWORD);
++	} else {
++		/*set debug port to 0x0*/
++		if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) {
++			fa_t->dbg_port0 = phydm_get_bb_dbg_port_val(dm);
++			phydm_release_bb_dbg_port(dm);
++		}
++	}
++
++	if (dm->support_ic_type & ODM_RTL8723D) {
++		val = odm_get_bb_reg(dm, R_0x9a0, BIT(29));
++	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		val = odm_get_bb_reg(dm, R_0x2d38, BIT(24));
++	} else if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, dbg_port)) {
++		if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E))
++			val = (phydm_get_bb_dbg_port_val(dm) & BIT(30)) >> 30;
++		else
++			val = (phydm_get_bb_dbg_port_val(dm) & BIT(29)) >> 29;
++		phydm_release_bb_dbg_port(dm);
++	}
++
++	fa_t->edcca_flag = (boolean)val;
++
++	PHYDM_DBG(dm, DBG_FA_CNT, "FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n",
++		  fa_t->dbg_port0, fa_t->edcca_flag);
++}
++
++void phydm_set_crc32_cnt2_rate(void *dm_void, u8 rate_idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
++	boolean is_ofdm_rate = phydm_is_ofdm_rate(dm, rate_idx);
++	boolean is_ht_rate = phydm_is_ht_rate(dm, rate_idx);
++	boolean is_vht_rate = phydm_is_vht_rate(dm, rate_idx);
++	u32 reg_addr = 0x0;
++	u32 ofdm_rate_bitmask = 0x0;
++	u32 ht_mcs_bitmask = 0x0;
++	u32 vht_mcs_bitmask = 0x0;
++	u32 vht_ss_bitmask = 0x0;
++	u8 rate = 0x0;
++	u8 ss = 0x0;
++
++	if (!is_ofdm_rate && !is_ht_rate && !is_vht_rate)
++		PHYDM_DBG(dm, DBG_FA_CNT,
++			  "[FA CNT] rate_idx = (0x%x) is not supported !\n",
++			  rate_idx);
++
++	switch (dm->ic_ip_series) {
++	case PHYDM_IC_N:
++		reg_addr = R_0xf04;
++		ofdm_rate_bitmask = 0x0000f000;
++		ht_mcs_bitmask = 0x007f0000;
++		break;
++	case PHYDM_IC_AC:
++		reg_addr = R_0xb04;
++		ofdm_rate_bitmask = 0x0000f000;
++		ht_mcs_bitmask = 0x007f0000;
++		vht_mcs_bitmask = 0x0f000000;
++		vht_ss_bitmask = 0x30000000;
++		break;
++	case PHYDM_IC_JGR3:
++		reg_addr = R_0x1eb8;
++		ofdm_rate_bitmask = 0x00000f00;
++		ht_mcs_bitmask = 0x007f0000;
++		vht_mcs_bitmask = 0x0000f000;
++		vht_ss_bitmask = 0x000000c0;
++		break;
++	default:
++		break;
++	}
++
++	if (is_ofdm_rate) {
++		rate = phydm_legacy_rate_2_spec_rate(dm, rate_idx);
++
++		odm_set_bb_reg(dm, reg_addr, ofdm_rate_bitmask, rate);
++		fa_t->ofdm2_rate_idx = rate_idx;
++	} else if (is_ht_rate) {
++		rate = phydm_rate_2_rate_digit(dm, rate_idx);
++
++		odm_set_bb_reg(dm, reg_addr, ht_mcs_bitmask, rate);
++		fa_t->ht2_rate_idx = rate_idx;
++	} else if (is_vht_rate) {
++		rate = phydm_rate_2_rate_digit(dm, rate_idx);
++		ss = phydm_rate_to_num_ss(dm, rate_idx);
++
++		odm_set_bb_reg(dm, reg_addr, vht_mcs_bitmask, rate);
++		odm_set_bb_reg(dm, reg_addr, vht_ss_bitmask, ss - 1);
++		fa_t->vht2_rate_idx = rate_idx;
++	}
++}
++
++void phydm_false_alarm_counter_statistics(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
++	char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
++	u32 tmp = 0;
++
++	if (!(dm->support_ability & ODM_BB_FA_CNT))
++		return;
++
++	PHYDM_DBG(dm, DBG_FA_CNT, "%s======>\n", __func__);
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		phydm_fa_cnt_statistics_jgr3(dm);
++		#endif
++	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		#if (ODM_IC_11N_SERIES_SUPPORT)
++		phydm_fa_cnt_statistics_n(dm);
++		#endif
++	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		#if (ODM_IC_11AC_SERIES_SUPPORT)
++		phydm_fa_cnt_statistics_ac(dm);
++		#endif
++	}
++
++	phydm_get_dbg_port_info(dm);
++	phydm_false_alarm_counter_reg_reset(dm_void);
++
++	fa_t->time_fa_all = fa_t->cnt_fast_fsync * 12 +
++			    fa_t->cnt_sb_search_fail * 12 +
++			    fa_t->cnt_parity_fail * 28 +
++			    fa_t->cnt_rate_illegal * 28 +
++			    fa_t->cnt_crc8_fail * 20 +
++			    fa_t->cnt_crc8_fail_vhta * 28 +
++			    fa_t->cnt_mcs_fail_vht * 36 +
++			    fa_t->cnt_mcs_fail * 32 +
++			    fa_t->cnt_cck_fail * 80;
++
++	fa_t->cnt_crc32_error_all = fa_t->cnt_vht_crc32_error +
++				    fa_t->cnt_ht_crc32_error +
++				    fa_t->cnt_ofdm_crc32_error +
++				    fa_t->cnt_cck_crc32_error;
++
++	fa_t->cnt_crc32_ok_all = fa_t->cnt_vht_crc32_ok +
++				 fa_t->cnt_ht_crc32_ok +
++				 fa_t->cnt_ofdm_crc32_ok +
++				 fa_t->cnt_cck_crc32_ok;
++
++	PHYDM_DBG(dm, DBG_FA_CNT,
++		  "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
++		  fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);
++	PHYDM_DBG(dm, DBG_FA_CNT,
++		  "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
++		  fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all);
++	PHYDM_DBG(dm, DBG_FA_CNT,
++		  "[OFDM FA] Parity=%d, Rate=%d, Fast_Fsync=%d, SBD=%d\n",
++		  fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
++		  fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail);
++	PHYDM_DBG(dm, DBG_FA_CNT, "[HT FA] CRC8=%d, MCS=%d\n",
++		  fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail);
++#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
++	if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
++		PHYDM_DBG(dm, DBG_FA_CNT,
++			  "[VHT FA] SIGA_CRC8=%d, SIGB_CRC8=%d, MCS=%d\n",
++			  fa_t->cnt_crc8_fail_vhta, fa_t->cnt_crc8_fail_vhtb,
++			  fa_t->cnt_mcs_fail_vht);
++	}
++#endif
++
++	PHYDM_DBG(dm, DBG_FA_CNT,
++		  "[CRC32 OK Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n",
++		  fa_t->cnt_cck_crc32_ok, fa_t->cnt_ofdm_crc32_ok,
++		  fa_t->cnt_ht_crc32_ok, fa_t->cnt_vht_crc32_ok,
++		  fa_t->cnt_crc32_ok_all);
++	PHYDM_DBG(dm, DBG_FA_CNT,
++		  "[CRC32 Err Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n",
++		  fa_t->cnt_cck_crc32_error, fa_t->cnt_ofdm_crc32_error,
++		  fa_t->cnt_ht_crc32_error, fa_t->cnt_vht_crc32_error,
++		  fa_t->cnt_crc32_error_all);
++
++	if (fa_t->ofdm2_rate_idx) {
++		tmp = fa_t->cnt_ofdm2_crc32_error + fa_t->cnt_ofdm2_crc32_ok;
++		fa_t->ofdm2_pcr = (u8)PHYDM_DIV(fa_t->cnt_ofdm2_crc32_ok * 100,
++						tmp);
++		phydm_print_rate_2_buff(dm, fa_t->ofdm2_rate_idx, dbg_buf,
++					PHYDM_SNPRINT_SIZE);
++		PHYDM_DBG(dm, DBG_FA_CNT,
++			  "[OFDM:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
++			  dbg_buf, fa_t->cnt_ofdm2_crc32_error,
++			  fa_t->cnt_ofdm2_crc32_ok, fa_t->ofdm2_pcr);
++	} else {
++		phydm_set_crc32_cnt2_rate(dm, ODM_RATE6M);
++	}
++
++	if (fa_t->ht2_rate_idx) {
++		tmp = fa_t->cnt_ht2_crc32_error + fa_t->cnt_ht2_crc32_ok;
++		fa_t->ht2_pcr = (u8)PHYDM_DIV(fa_t->cnt_ht2_crc32_ok * 100,
++					      tmp);
++		phydm_print_rate_2_buff(dm, fa_t->ht2_rate_idx, dbg_buf,
++					PHYDM_SNPRINT_SIZE);
++		PHYDM_DBG(dm, DBG_FA_CNT,
++			  "[HT:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
++			  dbg_buf, fa_t->cnt_ht2_crc32_error,
++			  fa_t->cnt_ht2_crc32_ok, fa_t->ht2_pcr);
++	} else {
++		phydm_set_crc32_cnt2_rate(dm, ODM_RATEMCS0);
++	}
++
++#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
++	if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
++		if (fa_t->vht2_rate_idx) {
++			tmp = fa_t->cnt_vht2_crc32_error +
++			      fa_t->cnt_vht2_crc32_ok;
++			fa_t->vht2_pcr = (u8)PHYDM_DIV(fa_t->cnt_vht2_crc32_ok *
++						       100, tmp);
++			phydm_print_rate_2_buff(dm, fa_t->vht2_rate_idx,
++						dbg_buf, PHYDM_SNPRINT_SIZE);
++			PHYDM_DBG(dm, DBG_FA_CNT,
++				  "[VHT:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
++				  dbg_buf, fa_t->cnt_vht2_crc32_error,
++				  fa_t->cnt_vht2_crc32_ok, fa_t->vht2_pcr);
++		} else {
++			phydm_set_crc32_cnt2_rate(dm, ODM_RATEVHTSS1MCS0);
++		}
++	}
++#endif
++}
++
++void phydm_fill_fw_dig_info(void *dm_void, boolean *enable,
++			    u8 *para4, u8 *para8) {
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++
++	dig_t->fw_dig_enable = *enable;
++	para8[0] = dig_t->rx_gain_range_max;
++	para8[1] = dig_t->rx_gain_range_min;
++	para8[2] = dm->number_linked_client;
++	para4[0] = (u8)DIG_LPS_MODE;
++}
++
++void phydm_crc32_cnt_dbg(void *dm_void, char input[][16], u32 *_used,
++			 char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 i = 0;
++	u8 rate = 0x0;
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[CRC32 Cnt] {rate_idx}\n");
++	} else {
++		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
++		rate = (u8)var1[0];
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{rate}={0x%x}", rate);
++
++		phydm_set_crc32_cnt2_rate(dm, rate);
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++void phydm_set_tdma_dig_timer(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 delta_time_us = dm->tdma_dig_timer_ms * 1000;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	u32 timeout = 0;
++	u32 current_time_stamp, diff_time_stamp, regb0 = 0;
++
++	/*some IC has no FREERUN_CUNT register, like 92E*/
++	if (dm->support_ic_type & ODM_RTL8197F)
++		current_time_stamp = odm_get_bb_reg(dm, R_0x568, 0xffffffff);
++	else
++		return;
++
++	timeout = current_time_stamp + delta_time_us;
++
++	diff_time_stamp = current_time_stamp - dig_t->cur_timestamp;
++	dig_t->pre_timestamp = dig_t->cur_timestamp;
++	dig_t->cur_timestamp = current_time_stamp;
++
++	/*@HIMR0, it shows HW interrupt mask*/
++	regb0 = odm_get_bb_reg(dm, R_0xb0, 0xffffffff);
++
++	PHYDM_DBG(dm, DBG_DIG, "Set next timer\n");
++	PHYDM_DBG(dm, DBG_DIG,
++		  "curr_time_stamp=%d, delta_time_us=%d\n",
++		  current_time_stamp, delta_time_us);
++	PHYDM_DBG(dm, DBG_DIG,
++		  "timeout=%d, diff_time_stamp=%d, Reg0xb0 = 0x%x\n",
++		  timeout, diff_time_stamp, regb0);
++
++	if (dm->support_ic_type & ODM_RTL8197F) /*REG_PS_TIMER2*/
++		odm_set_bb_reg(dm, R_0x588, 0xffffffff, timeout);
++	else {
++		PHYDM_DBG(dm, DBG_DIG, "NOT 97F, NOT start\n");
++		return;
++	}
++}
++
++void phydm_tdma_dig_timer_check(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++
++	PHYDM_DBG(dm, DBG_DIG, "tdma_dig_cnt=%d, pre_tdma_dig_cnt=%d\n",
++		  dig_t->tdma_dig_cnt, dig_t->pre_tdma_dig_cnt);
++
++	if (dig_t->tdma_dig_cnt == 0 ||
++	    dig_t->tdma_dig_cnt == dig_t->pre_tdma_dig_cnt) {
++		if (dm->support_ability & ODM_BB_DIG) {
++#ifdef IS_USE_NEW_TDMA
++			if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B |
++			    ODM_RTL8812F | ODM_RTL8822B | ODM_RTL8192F |
++			    ODM_RTL8821C | ODM_RTL8197G | ODM_RTL8822C |
++			    ODM_RTL8723D)) {
++				PHYDM_DBG(dm, DBG_DIG,
++					  "Check fail, Restart timer\n\n");
++				phydm_false_alarm_counter_reset(dm);
++				odm_set_timer(dm, &dm->tdma_dig_timer,
++					      dm->tdma_dig_timer_ms);
++			} else {
++				PHYDM_DBG(dm, DBG_DIG,
++					  "Not support TDMADIG, no SW timer\n");
++			}
++#else
++			/*@if interrupt mask info is got.*/
++			/*Reg0xb0 is no longer needed*/
++#if 0
++			/*regb0 = odm_get_bb_reg(dm, R_0xb0, bMaskDWord);*/
++#endif
++			PHYDM_DBG(dm, DBG_DIG,
++				  "Check fail, Mask[0]=0x%x, restart timer\n",
++				  *dm->interrupt_mask);
++
++			phydm_tdma_dig_add_interrupt_mask_handler(dm);
++			phydm_enable_rx_related_interrupt_handler(dm);
++			phydm_set_tdma_dig_timer(dm);
++#endif
++		}
++	} else {
++		PHYDM_DBG(dm, DBG_DIG, "Check pass, update pre_tdma_dig_cnt\n");
++	}
++
++	dig_t->pre_tdma_dig_cnt = dig_t->tdma_dig_cnt;
++}
++
++/*@different IC/team may use different timer for tdma-dig*/
++void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++#if (DM_ODM_SUPPORT_TYPE == (ODM_AP))
++	if (dm->support_ic_type & ODM_RTL8197F) {
++		/*@HAL_INT_TYPE_PSTIMEOUT2*/
++		phydm_add_interrupt_mask_handler(dm, HAL_INT_TYPE_PSTIMEOUT2);
++	}
++#elif (DM_ODM_SUPPORT_TYPE == (ODM_WIN))
++#elif (DM_ODM_SUPPORT_TYPE == (ODM_CE))
++#endif
++}
++
++/* will be triggered by HW timer*/
++void phydm_tdma_dig(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
++	u32 reg_c50 = 0;
++
++#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\
++	RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8821C_SUPPORT)
++#ifdef IS_USE_NEW_TDMA
++	if (dm->support_ic_type &
++	    (ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8822B |
++	     ODM_RTL8192F | ODM_RTL8821C)) {
++		PHYDM_DBG(dm, DBG_DIG, "98F/14B/12F/22B/92F/21C, new tdma\n");
++		return;
++	}
++#endif
++#endif
++	reg_c50 = odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
++
++	dig_t->tdma_dig_state =
++		dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
++
++	PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, regc50=0x%x\n",
++		  dig_t->tdma_dig_state, reg_c50);
++
++	dig_t->tdma_dig_cnt++;
++
++	if (dig_t->tdma_dig_state == 1) {
++		/* update IGI from tdma_dig_state == 0*/
++		if (dig_t->cur_ig_value_tdma == 0)
++			dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
++
++		odm_write_dig(dm, dig_t->cur_ig_value_tdma);
++		phydm_tdma_false_alarm_counter_check(dm);
++		PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, reset FA counter\n",
++			  dig_t->tdma_dig_state);
++
++	} else if (dig_t->tdma_dig_state == 0) {
++		/* update dig_t->CurIGValue,*/
++		/* @it may different from dig_t->cur_ig_value_tdma */
++		/* TDMA IGI upperbond @ L-state = */
++		/* rf_ft_var.tdma_dig_low_upper_bond = 0x26 */
++
++		if (dig_t->cur_ig_value >= dm->tdma_dig_low_upper_bond)
++			dig_t->low_ig_value = dm->tdma_dig_low_upper_bond;
++		else
++			dig_t->low_ig_value = dig_t->cur_ig_value;
++
++		odm_write_dig(dm, dig_t->low_ig_value);
++		phydm_tdma_false_alarm_counter_check(dm);
++	} else {
++		phydm_tdma_false_alarm_counter_check(dm);
++	}
++}
++
++/*@============================================================*/
++/*@FASLE ALARM CHECK*/
++/*@============================================================*/
++void phydm_tdma_false_alarm_counter_check(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
++	struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	boolean rssi_dump_en = 0;
++	u32 timestamp = 0;
++	u8 tdma_dig_state_number = 0;
++	u32 start_th = 0;
++
++	if (dig_t->tdma_dig_state == 1)
++		phydm_false_alarm_counter_reset(dm);
++	/* Reset FalseAlarmCounterStatistics */
++	/* @fa_acc_1sec_tsf = fa_acc_1sec_tsf, keep */
++	/* @fa_end_tsf = fa_start_tsf = TSF */
++	else {
++		phydm_false_alarm_counter_statistics(dm);
++		if (dm->support_ic_type & ODM_RTL8197F) /*REG_FREERUN_CNT*/
++			timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);
++		else {
++			PHYDM_DBG(dm, DBG_DIG, "NOT 97F! NOT start\n");
++			return;
++		}
++		dig_t->fa_end_timestamp = timestamp;
++		dig_t->fa_acc_1sec_timestamp +=
++			(dig_t->fa_end_timestamp - dig_t->fa_start_timestamp);
++
++		/*prevent dumb*/
++		if (dm->tdma_dig_state_number == 1)
++			dm->tdma_dig_state_number = 2;
++
++		tdma_dig_state_number = dm->tdma_dig_state_number;
++		dig_t->sec_factor =
++			tdma_dig_state_number / (tdma_dig_state_number - 1);
++
++		/*@1sec = 1000000us*/
++		if (dig_t->sec_factor)
++			start_th = (u32)(1000000 / dig_t->sec_factor);
++
++		if (dig_t->fa_acc_1sec_timestamp >= start_th) {
++			rssi_dump_en = 1;
++			phydm_false_alarm_counter_acc(dm, rssi_dump_en);
++			PHYDM_DBG(dm, DBG_DIG,
++				  "sec_factor=%d, total FA=%d, is_linked=%d\n",
++				  dig_t->sec_factor, falm_cnt_acc->cnt_all,
++				  dm->is_linked);
++
++			phydm_noisy_detection(dm);
++			#ifdef PHYDM_SUPPORT_CCKPD
++			phydm_cck_pd_th(dm);
++			#endif
++			phydm_dig(dm);
++			phydm_false_alarm_counter_acc_reset(dm);
++
++			/* Reset FalseAlarmCounterStatistics */
++			/* @fa_end_tsf = fa_start_tsf = TSF, keep */
++			/* @fa_acc_1sec_tsf = 0 */
++			phydm_false_alarm_counter_reset(dm);
++		} else {
++			phydm_false_alarm_counter_acc(dm, rssi_dump_en);
++		}
++	}
++}
++
++void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
++	struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++
++	falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;
++	falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;
++	falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;
++	falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;
++	falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;
++	falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;
++	falm_cnt_acc->cnt_all += falm_cnt->cnt_all;
++	falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;
++	falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;
++	falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;
++	falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;
++	falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;
++	falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;
++	falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;
++	falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;
++	falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;
++	falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;
++	falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;
++	falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;
++	falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;
++	falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;
++	falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;
++
++	if (rssi_dump_en == 1) {
++		falm_cnt_acc->cnt_all_1sec =
++			falm_cnt_acc->cnt_all * dig_t->sec_factor;
++		falm_cnt_acc->cnt_cca_all_1sec =
++			falm_cnt_acc->cnt_cca_all * dig_t->sec_factor;
++		falm_cnt_acc->cnt_cck_fail_1sec =
++			falm_cnt_acc->cnt_cck_fail * dig_t->sec_factor;
++	}
++}
++
++void phydm_false_alarm_counter_acc_reset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fa_acc_struct *falm_cnt_acc = NULL;
++
++#ifdef IS_USE_NEW_TDMA
++	struct phydm_fa_acc_struct *falm_cnt_acc_low = NULL;
++	u32 tmp_cca_1sec = 0;
++	u32 tmp_fa_1sec = 0;
++
++	/*@clear L-fa_acc struct*/
++	falm_cnt_acc_low = &dm->false_alm_cnt_acc_low;
++	tmp_cca_1sec = falm_cnt_acc_low->cnt_cca_all_1sec;
++	tmp_fa_1sec = falm_cnt_acc_low->cnt_all_1sec;
++	odm_memory_set(dm, falm_cnt_acc_low, 0, sizeof(dm->false_alm_cnt_acc));
++	falm_cnt_acc_low->cnt_cca_all_1sec = tmp_cca_1sec;
++	falm_cnt_acc_low->cnt_all_1sec = tmp_fa_1sec;
++
++	/*@clear H-fa_acc struct*/
++	falm_cnt_acc = &dm->false_alm_cnt_acc;
++	tmp_cca_1sec = falm_cnt_acc->cnt_cca_all_1sec;
++	tmp_fa_1sec = falm_cnt_acc->cnt_all_1sec;
++	odm_memory_set(dm, falm_cnt_acc, 0, sizeof(dm->false_alm_cnt_acc));
++	falm_cnt_acc->cnt_cca_all_1sec = tmp_cca_1sec;
++	falm_cnt_acc->cnt_all_1sec = tmp_fa_1sec;
++#else
++	falm_cnt_acc = &dm->false_alm_cnt_acc;
++	/* @Cnt_all_for_rssi_dump & Cnt_CCA_all_for_rssi_dump */
++	/* @do NOT need to be reset */
++	odm_memory_set(dm, falm_cnt_acc, 0, sizeof(falm_cnt_acc));
++#endif
++}
++
++void phydm_false_alarm_counter_reset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fa_struct *falm_cnt;
++	struct phydm_dig_struct *dig_t;
++	u32 timestamp;
++
++	falm_cnt = &dm->false_alm_cnt;
++	dig_t = &dm->dm_dig_table;
++
++	memset(falm_cnt, 0, sizeof(dm->false_alm_cnt));
++	phydm_false_alarm_counter_reg_reset(dm);
++
++#ifdef IS_USE_NEW_TDMA
++	return;
++#endif
++	if (dig_t->tdma_dig_state != 1)
++		dig_t->fa_acc_1sec_timestamp = 0;
++	else
++		dig_t->fa_acc_1sec_timestamp = dig_t->fa_acc_1sec_timestamp;
++
++	/*REG_FREERUN_CNT*/
++	timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);
++	dig_t->fa_start_timestamp = timestamp;
++	dig_t->fa_end_timestamp = timestamp;
++}
++
++void phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	switch (type) {
++	case ENABLE_TDMA:
++		dm->original_dig_restore = !((boolean)input);
++		break;
++	case MODE_DECISION:
++		if (input == (u8)MODE_PERFORMANCE)
++			dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES + 2;
++		else if (input == (u8)MODE_COVERAGE)
++			dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
++		else
++			dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
++		break;
++	}
++}
++
++#ifdef IS_USE_NEW_TDMA
++#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
++static void pre_phydm_tdma_dig_cbk(unsigned long task_dm)
++{
++	struct dm_struct *dm = (struct dm_struct *)task_dm;
++	struct rtl8192cd_priv *priv = dm->priv;
++	struct priv_shared_info *pshare = priv->pshare;
++
++	if (!(priv->drv_state & DRV_STATE_OPEN))
++		return;
++
++	if (pshare->bDriverStopped || pshare->bSurpriseRemoved) {
++		printk("[%s] bDriverStopped(%d) OR bSurpriseRemoved(%d)\n",
++		         __FUNCTION__, pshare->bDriverStopped,
++		         pshare->bSurpriseRemoved);
++		return;
++	}
++
++	rtw_enqueue_timer_event(priv, &pshare->tdma_dig_event,
++			           ENQUEUE_TO_TAIL);
++}
++
++void phydm_tdma_dig_timers_usb(void *dm_void, u8 state)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++
++	if (state == INIT_TDMA_DIG_TIMMER) {
++		struct rtl8192cd_priv *priv = dm->priv;
++
++		init_timer(&dm->tdma_dig_timer);
++		dm->tdma_dig_timer.data = (unsigned long)dm;
++		dm->tdma_dig_timer.function = pre_phydm_tdma_dig_cbk;
++		INIT_TIMER_EVENT_ENTRY(&priv->pshare->tdma_dig_event,
++					    phydm_tdma_dig_cbk,
++					   (unsigned long)dm);
++	} else if (state == CANCEL_TDMA_DIG_TIMMER) {
++		odm_cancel_timer(dm, &dm->tdma_dig_timer);
++	} else if (state == RELEASE_TDMA_DIG_TIMMER) {
++		odm_release_timer(dm, &dm->tdma_dig_timer);
++	}
++}
++#endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
++
++void phydm_tdma_dig_timers(void *dm_void, u8 state)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
++	struct rtl8192cd_priv *priv = dm->priv;
++
++	if (priv->hci_type == RTL_HCI_USB) {
++		phydm_tdma_dig_timers_usb(dm_void, state);
++		return;
++	}
++#endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
++
++	if (state == INIT_TDMA_DIG_TIMMER)
++		odm_initialize_timer(dm, &dm->tdma_dig_timer,
++				     (void *)phydm_tdma_dig_cbk,
++				     NULL, "phydm_tdma_dig_timer");
++	else if (state == CANCEL_TDMA_DIG_TIMMER)
++		odm_cancel_timer(dm, &dm->tdma_dig_timer);
++	else if (state == RELEASE_TDMA_DIG_TIMMER)
++		odm_release_timer(dm, &dm->tdma_dig_timer);
++}
++
++u8 get_new_igi_bound(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *rx_gain_max,
++		     u8 *rx_gain_min, boolean is_dfs_band)
++{
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	u8 step[3] = {0};
++	u8 cur_igi = igi;
++
++	if (dm->is_linked) {
++		if (dm->pre_rssi_min <= dm->rssi_min) {
++			PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n");
++			step[0] = 2;
++			step[1] = 1;
++			step[2] = 2;
++		} else {
++			step[0] = 4;
++			step[1] = 2;
++			step[2] = 2;
++		}
++	} else {
++		step[0] = 2;
++		step[1] = 1;
++		step[2] = 2;
++	}
++
++	PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
++		  step[0]);
++
++	if (dm->first_connect) {
++		if (is_dfs_band) {
++			if (dm->rssi_min > DIG_MAX_DFS)
++				igi = DIG_MAX_DFS;
++			else
++				igi = dm->rssi_min;
++			PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n",
++				  *rx_gain_max);
++		} else {
++			igi = *rx_gain_min;
++		}
++
++		#if 0
++		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++		#if (RTL8812A_SUPPORT)
++		if (dm->support_ic_type == ODM_RTL8812)
++			odm_config_bb_with_header_file(dm,
++						       CONFIG_BB_AGC_TAB_DIFF);
++		#endif
++		#endif
++		#endif
++		PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi);
++	} else {
++		/* @2 Before link */
++		PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
++
++		if (dm->first_disconnect) {
++			igi = dig_t->dm_dig_min;
++			PHYDM_DBG(dm, DBG_DIG,
++				  "First disconnect:foce IGI to lower bound\n");
++		} else {
++			PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n",
++				  igi, fa_cnt);
++
++			igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
++		}
++	}
++	/*@Check IGI by dyn-upper/lower bound */
++	if (igi < *rx_gain_min)
++		igi = *rx_gain_min;
++
++	if (igi > *rx_gain_max)
++		igi = *rx_gain_max;
++
++	PHYDM_DBG(dm, DBG_DIG, "fa_cnt = %d, IGI: 0x%x -> 0x%x\n",
++		  fa_cnt, cur_igi, igi);
++
++	return igi;
++}
++
++void phydm_write_tdma_dig(void *dm_void, u8 new_igi)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
++
++	PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
++#if 0
++	/* @1 Check IGI by upper bound */
++	if (adaptivity->igi_lmt_en &&
++	    new_igi > adaptivity->adapt_igi_up && dm->is_linked) {
++		new_igi = adaptivity->adapt_igi_up;
++
++		PHYDM_DBG(dm, DBG_DIG, "Force Adaptivity Up-bound=((0x%x))\n",
++			  new_igi);
++	}
++#endif
++	phydm_write_dig_reg(dm, new_igi);
++
++	PHYDM_DBG(dm, DBG_DIG, "New %s-IGI=((0x%x))\n",
++		  (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE) ? "L" : "H",
++		  new_igi);
++}
++
++void phydm_tdma_dig_new(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++
++	if (phydm_dig_abort(dm) || dm->original_dig_restore)
++		return;
++	/*@
++	 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
++	 *	  dig_t->tdma_dig_state);
++	 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
++	 *	  dig_t->cur_ig_value_tdma,
++	 *	  dig_t->low_ig_value);
++	 */
++	phydm_tdma_fa_cnt_chk(dm);
++
++	/*@prevent dumb*/
++	if (dm->tdma_dig_state_number < 2)
++		dm->tdma_dig_state_number = 2;
++
++	/*@update state*/
++	dig_t->tdma_dig_cnt++;
++	dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
++
++	/*@
++	 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
++	 *	  dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
++	 */
++
++	if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
++		odm_write_dig(dm, dig_t->low_ig_value);
++	else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
++		odm_write_dig(dm, dig_t->cur_ig_value_tdma);
++
++	odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
++}
++
++/*@callback function triggered by SW timer*/
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void phydm_tdma_dig_cbk(struct phydm_timer_list *timer)
++{
++	void *adapter = (void *)timer->Adapter;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrcs;
++
++	#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++	#if USE_WORKITEM
++	odm_schedule_work_item(&dm->phydm_tdma_dig_workitem);
++	#else
++	phydm_tdma_dig_new(dm);
++	#endif
++	#else
++	odm_schedule_work_item(&dm->phydm_tdma_dig_workitem);
++	#endif
++}
++
++void phydm_tdma_dig_workitem_callback(void *context)
++{
++	void *adapter = (void *)context;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++
++	phydm_tdma_dig_new(dm);
++}
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++void phydm_tdma_dig_cbk(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	void *padapter = dm->adapter;
++
++	if (dm->support_interface == ODM_ITRF_PCIE)
++		phydm_tdma_dig_workitem_callback(dm);
++	/* @Can't do I/O in timer callback*/
++	else
++		phydm_run_in_thread_cmd(dm, phydm_tdma_dig_workitem_callback,
++					dm);
++}
++
++void phydm_tdma_dig_workitem_callback(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++
++	if (phydm_dig_abort(dm) || (dm->original_dig_restore))
++		return;
++	/*@
++	 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
++	 *	  dig_t->tdma_dig_state);
++	 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
++	 *	  dig_t->cur_ig_value_tdma,
++	 *	  dig_t->low_ig_value);
++	 */
++	phydm_tdma_fa_cnt_chk(dm);
++
++	/*@prevent dumb*/
++	if (dm->tdma_dig_state_number < 2)
++		dm->tdma_dig_state_number = 2;
++
++	/*@update state*/
++	dig_t->tdma_dig_cnt++;
++	dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
++
++	/*@
++	 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
++	 *	  dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
++	 */
++
++	if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
++		odm_write_dig(dm, dig_t->low_ig_value);
++	else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
++		odm_write_dig(dm, dig_t->cur_ig_value_tdma);
++
++	odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
++}
++#else
++void phydm_tdma_dig_cbk(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++
++	if (phydm_dig_abort(dm) || dm->original_dig_restore)
++		return;
++	/*@
++	 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
++	 *	  dig_t->tdma_dig_state);
++	 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
++	 *	  dig_t->cur_ig_value_tdma,
++	 *	  dig_t->low_ig_value);
++	 */
++	phydm_tdma_fa_cnt_chk(dm);
++
++	/*@prevent dumb*/
++	if (dm->tdma_dig_state_number < 2)
++		dm->tdma_dig_state_number = 2;
++
++	/*@update state*/
++	dig_t->tdma_dig_cnt++;
++	dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
++
++	/*@
++	 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
++	 *	  dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
++	 */
++
++	if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
++		phydm_write_tdma_dig(dm, dig_t->low_ig_value);
++	else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
++		phydm_write_tdma_dig(dm, dig_t->cur_ig_value_tdma);
++
++	odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
++}
++#endif
++/*@============================================================*/
++/*@FASLE ALARM CHECK*/
++/*@============================================================*/
++void phydm_tdma_fa_cnt_chk(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
++	struct phydm_fa_acc_struct *fa_t_acc = &dm->false_alm_cnt_acc;
++	struct phydm_fa_acc_struct *fa_t_acc_low = &dm->false_alm_cnt_acc_low;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	boolean tdma_dig_block_1sec_flag = false;
++	u32 timestamp = 0;
++	u8 states_per_block = dm->tdma_dig_state_number;
++	u8 cur_tdma_dig_state = 0;
++	u32 start_th = 0;
++	u8 state_diff = 0;
++	u32 tdma_dig_block_period_ms = 0;
++	u32 tdma_dig_block_cnt_thd = 0;
++	u32 timestamp_diff = 0;
++
++	/*@calculate duration of a tdma block*/
++	tdma_dig_block_period_ms = dm->tdma_dig_timer_ms * states_per_block;
++
++	/*@
++	 *caution!ONE_SEC_MS must be divisible by tdma_dig_block_period_ms,
++	 *or FA will be fewer.
++	 */
++	tdma_dig_block_cnt_thd = ONE_SEC_MS / tdma_dig_block_period_ms;
++
++	/*@tdma_dig_state == 0, collect H-state FA, else, collect L-state FA*/
++	if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
++		cur_tdma_dig_state = TDMA_DIG_LOW_STATE;
++	else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
++		cur_tdma_dig_state = TDMA_DIG_HIGH_STATE;
++	/*@
++	 *PHYDM_DBG(dm, DBG_DIG, "in state %d, dig count %d\n",
++	 *	  cur_tdma_dig_state, dig_t->tdma_dig_cnt);
++	 */
++	if (cur_tdma_dig_state == 0) {
++		/*@L-state indicates next block*/
++		dig_t->tdma_dig_block_cnt++;
++
++		/*@1sec dump check*/
++		if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
++			tdma_dig_block_1sec_flag = true;
++
++		/*@
++		 *PHYDM_DBG(dm, DBG_DIG,"[L-state] tdma_dig_block_cnt=%d\n",
++		 *	  dig_t->tdma_dig_block_cnt);
++		 */
++
++		/*@collect FA till this block end*/
++		phydm_false_alarm_counter_statistics(dm);
++		phydm_fa_cnt_acc(dm, tdma_dig_block_1sec_flag,
++				 cur_tdma_dig_state);
++		/*@1s L-FA collect end*/
++
++		/*@1sec dump reached*/
++		if (tdma_dig_block_1sec_flag) {
++			/*@L-DIG*/
++			phydm_noisy_detection(dm);
++			#ifdef PHYDM_SUPPORT_CCKPD
++			phydm_cck_pd_th(dm);
++			#endif
++			PHYDM_DBG(dm, DBG_DIG, "run tdma L-state dig ====>\n");
++			phydm_tdma_low_dig(dm);
++			PHYDM_DBG(dm, DBG_DIG, "\n\n");
++		}
++	} else if (cur_tdma_dig_state == 1) {
++		/*@1sec dump check*/
++		if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
++			tdma_dig_block_1sec_flag = true;
++
++		/*@
++		 *PHYDM_DBG(dm, DBG_DIG,"[H-state] tdma_dig_block_cnt=%d\n",
++		 *	  dig_t->tdma_dig_block_cnt);
++		 */
++
++		/*@collect FA till this block end*/
++		phydm_false_alarm_counter_statistics(dm);
++		phydm_fa_cnt_acc(dm, tdma_dig_block_1sec_flag,
++				 cur_tdma_dig_state);
++		/*@1s H-FA collect end*/
++
++		/*@1sec dump reached*/
++		state_diff = dm->tdma_dig_state_number - dig_t->tdma_dig_state;
++		if (tdma_dig_block_1sec_flag && state_diff == 1) {
++			/*@H-DIG*/
++			phydm_noisy_detection(dm);
++			#ifdef PHYDM_SUPPORT_CCKPD
++			phydm_cck_pd_th(dm);
++			#endif
++			PHYDM_DBG(dm, DBG_DIG, "run tdma H-state dig ====>\n");
++			phydm_tdma_high_dig(dm);
++			PHYDM_DBG(dm, DBG_DIG, "\n\n");
++			PHYDM_DBG(dm, DBG_DIG, "1 sec reached, is_linked=%d\n",
++				  dm->is_linked);
++			PHYDM_DBG(dm, DBG_DIG, "1 sec L-CCA=%d, L-FA=%d\n",
++				  fa_t_acc_low->cnt_cca_all_1sec,
++				  fa_t_acc_low->cnt_all_1sec);
++			PHYDM_DBG(dm, DBG_DIG, "1 sec H-CCA=%d, H-FA=%d\n",
++				  fa_t_acc->cnt_cca_all_1sec,
++				  fa_t_acc->cnt_all_1sec);
++			PHYDM_DBG(dm, DBG_DIG,
++				  "1 sec TOTAL-CCA=%d, TOTAL-FA=%d\n\n",
++				  fa_t_acc->cnt_cca_all +
++				  fa_t_acc_low->cnt_cca_all,
++				  fa_t_acc->cnt_all + fa_t_acc_low->cnt_all);
++
++			/*@Reset AccFalseAlarmCounterStatistics */
++			phydm_false_alarm_counter_acc_reset(dm);
++			dig_t->tdma_dig_block_cnt = 0;
++		}
++	}
++	/*@Reset FalseAlarmCounterStatistics */
++	phydm_false_alarm_counter_reset(dm);
++}
++
++void phydm_tdma_low_dig(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
++	struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc_low;
++#ifdef CFG_DIG_DAMPING_CHK
++	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
++#endif
++	u8 igi = dig_t->cur_ig_value;
++	u8 new_igi = 0x20;
++	u8 tdma_l_igi = dig_t->low_ig_value;
++	u8 tdma_l_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE];
++	u8 tdma_l_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE];
++	u32 fa_cnt = falm_cnt->cnt_all;
++	boolean dfs_mode_en = false, is_performance = true;
++	u8 rssi_min = dm->rssi_min;
++	u8 igi_upper_rssi_min = 0;
++	u8 offset = 15;
++
++	if (!(dm->original_dig_restore)) {
++		if (tdma_l_igi == 0)
++			tdma_l_igi = igi;
++
++		fa_cnt = falm_cnt_acc->cnt_all_1sec;
++	}
++
++	if (phydm_dig_abort(dm)) {
++		dig_t->low_ig_value = phydm_get_igi(dm, BB_PATH_A);
++		return;
++	}
++
++	/*@Mode Decision*/
++	dfs_mode_en = false;
++	is_performance = true;
++
++	/* @Abs Boundary Decision*/
++	dig_t->dm_dig_max = DIG_MAX_COVERAGR; //0x26
++	dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; //0x20
++	dig_t->dig_max_of_min = DIG_MAX_OF_MIN_COVERAGE; //0x22
++
++	if (dm->is_dfs_band) {
++		if (*dm->band_width == CHANNEL_WIDTH_20){
++			if (dm->support_ic_type &
++				(ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
++				if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
++					dig_t->dm_dig_min = DIG_MIN_DFS + 2;
++				else
++					dig_t->dm_dig_min = DIG_MIN_DFS;
++			}
++			else
++				dig_t->dm_dig_min = DIG_MIN_DFS;
++		}
++		else
++			dig_t->dm_dig_min = DIG_MIN_DFS;
++
++	} else {
++		#if 0
++		if (dm->support_ic_type &
++		    (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
++			dig_t->dm_dig_min = 0x1c;
++		else if (dm->support_ic_type & ODM_RTL8197F)
++			dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
++		#endif
++	}
++
++	PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
++		  dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
++
++	/* @Dyn Boundary by RSSI*/
++	if (!dm->is_linked) {
++		/*@if no link, always stay at lower bound*/
++		tdma_l_dym_max = 0x26;
++		tdma_l_dym_min = dig_t->dm_dig_min;
++
++		PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
++			  tdma_l_dym_max, tdma_l_dym_min);
++	} else {
++		PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n",
++			  dm->rssi_min, offset);
++
++		/* @DIG lower bound in L-state*/
++		tdma_l_dym_min = dig_t->dm_dig_min;
++		if (dm->is_dfs_band)
++			tdma_l_dym_min = DIG_MIN_DFS;
++		/*@
++		 *#ifdef CFG_DIG_DAMPING_CHK
++		 *@Limit Dyn min by damping
++		 *if (dig_t->dig_dl_en &&
++		 *   dig_rc->damping_limit_en &&
++		 *   tdma_l_dym_min < dig_rc->damping_limit_val) {
++		 *	PHYDM_DBG(dm, DBG_DIG,
++		 *		  "[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
++		 *		  tdma_l_dym_min, dig_rc->damping_limit_val);
++		 *
++		 *	tdma_l_dym_min = dig_rc->damping_limit_val;
++		 *}
++		 *#endif
++		 */
++
++		/*@DIG upper bound in L-state*/
++		igi_upper_rssi_min = rssi_min + offset;
++		if (igi_upper_rssi_min > dig_t->dm_dig_max)
++			tdma_l_dym_max = dig_t->dm_dig_max;
++		else if (igi_upper_rssi_min < dig_t->dm_dig_min)
++			tdma_l_dym_max = dig_t->dm_dig_min;
++		else
++			tdma_l_dym_max = igi_upper_rssi_min;
++
++		/* @1 Force Lower Bound for AntDiv */
++		/*@
++		 *if (!dm->is_one_entry_only &&
++		 *(dm->support_ability & ODM_BB_ANT_DIV) &&
++		 *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||
++		 *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
++		 *if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
++		 *	dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
++		 *else
++		 *	dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
++		 *
++		 *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
++		 *	  dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
++		 *}
++		 */
++
++		PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
++			  tdma_l_dym_max, tdma_l_dym_min);
++	}
++
++	/*@Abnormal Case Check*/
++	/*@Abnormal lower bound case*/
++	if (tdma_l_dym_min > tdma_l_dym_max)
++		tdma_l_dym_min = tdma_l_dym_max;
++
++	PHYDM_DBG(dm, DBG_DIG,
++		  "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n",
++		  tdma_l_dym_max, tdma_l_dym_min);
++
++	/*@False Alarm Threshold Decision*/
++	phydm_fa_threshold_check(dm, dfs_mode_en);
++
++	/*@Adjust Initial Gain by False Alarm*/
++	/*Select new IGI by FA */
++	if (!(dm->original_dig_restore)) {
++		tdma_l_igi = get_new_igi_bound(dm, tdma_l_igi, fa_cnt,
++					       &tdma_l_dym_max,
++					       &tdma_l_dym_min,
++					       dfs_mode_en);
++	} else {
++		new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
++	}
++
++	/*Update status*/
++	if (!(dm->original_dig_restore)) {
++		if (dig_t->tdma_force_l_igi == 0xff)
++			dig_t->low_ig_value = tdma_l_igi;
++		else
++			dig_t->low_ig_value = dig_t->tdma_force_l_igi;
++		dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] = tdma_l_dym_min;
++		dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = tdma_l_dym_max;
++#if 0
++		/*odm_write_dig(dm, tdma_l_igi);*/
++#endif
++	} else {
++		odm_write_dig(dm, new_igi);
++	}
++}
++
++void phydm_tdma_high_dig(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
++	struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
++#ifdef CFG_DIG_DAMPING_CHK
++	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
++#endif
++	u8 igi = dig_t->cur_ig_value;
++	u8 new_igi = 0x20;
++	u8 tdma_h_igi = dig_t->cur_ig_value_tdma;
++	u8 tdma_h_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE];
++	u8 tdma_h_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE];
++	u32 fa_cnt = falm_cnt->cnt_all;
++	boolean dfs_mode_en = false, is_performance = true;
++	u8 rssi_min = dm->rssi_min;
++	u8 igi_upper_rssi_min = 0;
++	u8 offset = 15;
++
++	if (!(dm->original_dig_restore)) {
++		if (tdma_h_igi == 0)
++			tdma_h_igi = igi;
++
++		fa_cnt = falm_cnt_acc->cnt_all_1sec;
++	}
++
++	if (phydm_dig_abort(dm)) {
++		dig_t->cur_ig_value_tdma = phydm_get_igi(dm, BB_PATH_A);
++		return;
++	}
++
++	/*@Mode Decision*/
++	dfs_mode_en = false;
++	is_performance = true;
++
++	/*@Abs Boundary Decision*/
++	dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; // 0x2a
++
++	if (!dm->is_linked) {
++		dig_t->dm_dig_max = DIG_MAX_COVERAGR;
++		dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; // 0x20
++	} else if (dm->is_dfs_band) {
++		if (*dm->band_width == CHANNEL_WIDTH_20){
++			if (dm->support_ic_type &
++				(ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
++				if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
++					dig_t->dm_dig_min = DIG_MIN_DFS + 2;
++				else
++					dig_t->dm_dig_min = DIG_MIN_DFS;
++			}
++			else
++				dig_t->dm_dig_min = DIG_MIN_DFS;
++		}
++		else
++			dig_t->dm_dig_min = DIG_MIN_DFS;
++
++		dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
++		dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
++	} else {
++		if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {
++		/*service > 2 devices*/
++			dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
++			#if (DIG_HW == 1)
++			dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
++			#else
++			dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
++			#endif
++		} else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {
++		/*service 1 devices*/
++			dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;
++			dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
++		}
++
++		#if 0
++		if (dm->support_ic_type &
++		    (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
++			dig_t->dm_dig_min = 0x1c;
++		else if (dm->support_ic_type & ODM_RTL8197F)
++			dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
++		else
++		#endif
++			dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
++	}
++	PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
++		  dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
++
++	/*@Dyn Boundary by RSSI*/
++	if (!dm->is_linked) {
++		/*@if no link, always stay at lower bound*/
++		tdma_h_dym_max = dig_t->dig_max_of_min;
++		tdma_h_dym_min = dig_t->dm_dig_min;
++
++		PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
++			  tdma_h_dym_max, tdma_h_dym_min);
++	} else {
++		PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n",
++			  dm->rssi_min, offset);
++
++		/* @DIG lower bound in H-state*/
++		if (dm->is_dfs_band)
++			tdma_h_dym_min = DIG_MIN_DFS;
++		else if (rssi_min < dig_t->dm_dig_min)
++			tdma_h_dym_min = dig_t->dm_dig_min;
++		else
++			tdma_h_dym_min = rssi_min; // turbo not considered yet
++
++#ifdef CFG_DIG_DAMPING_CHK
++		/*@Limit Dyn min by damping*/
++		if (dig_t->dig_dl_en &&
++		    dig_rc->damping_limit_en &&
++		    tdma_h_dym_min < dig_rc->damping_limit_val) {
++			PHYDM_DBG(dm, DBG_DIG,
++				  "[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
++				  tdma_h_dym_min, dig_rc->damping_limit_val);
++
++			tdma_h_dym_min = dig_rc->damping_limit_val;
++		}
++#endif
++
++		/*@DIG upper bound in H-state*/
++		igi_upper_rssi_min = rssi_min + offset;
++		if (igi_upper_rssi_min > dig_t->dm_dig_max)
++			tdma_h_dym_max = dig_t->dm_dig_max;
++		else
++			tdma_h_dym_max = igi_upper_rssi_min;
++
++		/* @1 Force Lower Bound for AntDiv */
++		/*@
++		 *if (!dm->is_one_entry_only &&
++		 *(dm->support_ability & ODM_BB_ANT_DIV) &&
++		 *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||
++		 *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
++		 *	if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
++		 *	dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
++		 *	else
++		 *	dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
++		 */
++		/*@
++		 *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
++		 *	  dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
++		 *}
++		 */
++		PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
++			  tdma_h_dym_max, tdma_h_dym_min);
++	}
++
++	/*@Abnormal Case Check*/
++	/*@Abnormal low higher bound case*/
++	if (tdma_h_dym_max < dig_t->dm_dig_min)
++		tdma_h_dym_max = dig_t->dm_dig_min;
++	/*@Abnormal lower bound case*/
++	if (tdma_h_dym_min > tdma_h_dym_max)
++		tdma_h_dym_min = tdma_h_dym_max;
++
++	PHYDM_DBG(dm, DBG_DIG, "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n",
++		  tdma_h_dym_max, tdma_h_dym_min);
++
++	/*@False Alarm Threshold Decision*/
++	phydm_fa_threshold_check(dm, dfs_mode_en);
++
++	/*@Adjust Initial Gain by False Alarm*/
++	/*Select new IGI by FA */
++	if (!(dm->original_dig_restore)) {
++		tdma_h_igi = get_new_igi_bound(dm, tdma_h_igi, fa_cnt,
++					       &tdma_h_dym_max,
++					       &tdma_h_dym_min,
++					       dfs_mode_en);
++	} else {
++		new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
++	}
++
++	/*Update status*/
++	if (!(dm->original_dig_restore)) {
++		if (dig_t->tdma_force_h_igi == 0xff)
++			dig_t->cur_ig_value_tdma = tdma_h_igi;
++		else
++			dig_t->cur_ig_value_tdma = dig_t->tdma_force_h_igi;
++		dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] = tdma_h_dym_min;
++		dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = tdma_h_dym_max;
++#if 0
++		/*odm_write_dig(dm, tdma_h_igi);*/
++#endif
++	} else {
++		odm_write_dig(dm, new_igi);
++	}
++}
++
++void phydm_fa_cnt_acc(void *dm_void, boolean tdma_dig_block_1sec_flag,
++		      u8 cur_tdma_dig_state)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
++	struct phydm_fa_acc_struct *falm_cnt_acc = NULL;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	u8 factor_num = 0;
++	u8 factor_denum = 1;
++	u8 total_state_number = 0;
++
++	if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE)
++		falm_cnt_acc = &dm->false_alm_cnt_acc_low;
++	else if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE)
++
++		falm_cnt_acc = &dm->false_alm_cnt_acc;
++	/*@
++	 *PHYDM_DBG(dm, DBG_DIG,
++	 *	  "[%s] ==> dig_state=%d, one_sec=%d\n", __func__,
++	 *	  cur_tdma_dig_state, tdma_dig_block_1sec_flag);
++	 */
++	falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;
++	falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;
++	falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;
++	falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;
++	falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;
++	falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;
++	falm_cnt_acc->cnt_all += falm_cnt->cnt_all;
++	falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;
++	falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;
++	falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;
++	falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;
++	falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;
++	falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;
++	falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;
++	falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;
++	falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;
++	falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;
++	falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;
++	falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;
++	falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;
++	falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;
++	falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;
++
++	/*@
++	 *PHYDM_DBG(dm, DBG_DIG,
++	 *	"[CCA Cnt]     {CCK, OFDM, Total} = {%d, %d, %d}\n",
++	 *	falm_cnt->cnt_cck_cca,
++	 *	falm_cnt->cnt_ofdm_cca,
++	 *	falm_cnt->cnt_cca_all);
++	 *PHYDM_DBG(dm, DBG_DIG,
++	 *	"[FA Cnt]      {CCK, OFDM, Total} = {%d, %d, %d}\n",
++	 *	falm_cnt->cnt_cck_fail,
++	 *	falm_cnt->cnt_ofdm_fail,
++	 *	falm_cnt->cnt_all);
++	 */
++	if (tdma_dig_block_1sec_flag) {
++		total_state_number = dm->tdma_dig_state_number;
++
++		if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE) {
++			factor_num = total_state_number;
++			factor_denum = total_state_number - 1;
++		} else if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE) {
++			factor_num = total_state_number;
++			factor_denum = 1;
++		}
++
++		falm_cnt_acc->cnt_all_1sec =
++			falm_cnt_acc->cnt_all * factor_num / factor_denum;
++		falm_cnt_acc->cnt_cca_all_1sec =
++			falm_cnt_acc->cnt_cca_all * factor_num / factor_denum;
++		falm_cnt_acc->cnt_cck_fail_1sec =
++			falm_cnt_acc->cnt_cck_fail * factor_num / factor_denum;
++
++		PHYDM_DBG(dm, DBG_DIG,
++			  "[ACC CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
++			  falm_cnt_acc->cnt_cck_cca,
++			  falm_cnt_acc->cnt_ofdm_cca,
++			  falm_cnt_acc->cnt_cca_all);
++		PHYDM_DBG(dm, DBG_DIG,
++			  "[ACC FA Cnt]  {CCK, OFDM, Total} = {%d, %d, %d}\n\n",
++			  falm_cnt_acc->cnt_cck_fail,
++			  falm_cnt_acc->cnt_ofdm_fail,
++			  falm_cnt_acc->cnt_all);
++
++	}
++}
++#endif /*@#ifdef IS_USE_NEW_TDMA*/
++#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
++
++void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,
++		     u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 i = 0;
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{0} {en} fa_th[0] fa_th[1] fa_th[2]\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{1} {Damping Limit en}\n");
++		#ifdef PHYDM_TDMA_DIG_SUPPORT
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{2} {original_dig_restore = %d}\n",
++			 dm->original_dig_restore);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{3} {tdma_dig_timer_ms = %d}\n",
++			 dm->tdma_dig_timer_ms);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{4} {tdma_dig_state_number = %d}\n",
++			 dm->tdma_dig_state_number);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{5} {0:L-state,1:H-state} {force IGI} (L,H)=(%2x,%2x)\n",
++			 dig_t->tdma_force_l_igi, dig_t->tdma_force_h_igi);
++		#endif
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{6} {fw_dig_en}\n");
++	} else {
++		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
++
++		for (i = 1; i < 10; i++)
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
++
++		if (var1[0] == 0) {
++			if (var1[1] == 1) {
++				dig_t->is_dbg_fa_th = true;
++				dig_t->fa_th[0] = (u16)var1[2];
++				dig_t->fa_th[1] = (u16)var1[3];
++				dig_t->fa_th[2] = (u16)var1[4];
++
++				PDM_SNPF(out_len, used, output + used,
++					 out_len - used,
++					 "Set DIG fa_th[0:2]= {%d, %d, %d}\n",
++					 dig_t->fa_th[0], dig_t->fa_th[1],
++					 dig_t->fa_th[2]);
++			} else {
++				dig_t->is_dbg_fa_th = false;
++			}
++		#ifdef PHYDM_TDMA_DIG_SUPPORT
++		} else if (var1[0] == 2) {
++			dm->original_dig_restore = (u8)var1[1];
++			if (dm->original_dig_restore == 1) {
++				PDM_SNPF(out_len, used, output + used,
++					 out_len - used, "Disable TDMA-DIG\n");
++			} else {
++				PDM_SNPF(out_len, used, output + used,
++					 out_len - used, "Enable TDMA-DIG\n");
++			}
++		} else if (var1[0] == 3) {
++			dm->tdma_dig_timer_ms = (u8)var1[1];
++			PDM_SNPF(out_len, used, output + used,
++				 out_len - used, "tdma_dig_timer_ms = %d\n",
++				 dm->tdma_dig_timer_ms);
++		} else if (var1[0] == 4) {
++			dm->tdma_dig_state_number = (u8)var1[1];
++			PDM_SNPF(out_len, used, output + used,
++				 out_len - used, "tdma_dig_state_number = %d\n",
++				 dm->tdma_dig_state_number);
++		} else if (var1[0] == 5) {
++			PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
++			if (var1[1] == 0) {
++				dig_t->tdma_force_l_igi = (u8)var1[2];
++				PDM_SNPF(out_len, used, output + used,
++					 out_len - used,
++					 "force L-state IGI = %2x\n",
++					 dig_t->tdma_force_l_igi);
++			} else if (var1[1] == 1) {
++				dig_t->tdma_force_h_igi = (u8)var1[2];
++				PDM_SNPF(out_len, used, output + used,
++					 out_len - used,
++					 "force H-state IGI = %2x\n",
++					 dig_t->tdma_force_h_igi);
++			}
++		#endif
++		}
++
++		#ifdef CFG_DIG_DAMPING_CHK
++		else if (var1[0] == 1) {
++			dig_t->dig_dl_en = (u8)var1[1];
++			/*@*/
++		}
++		#endif
++		else if (var1[0] == 6) {
++			phydm_fw_dm_ctrl_en(dm, F00_DIG, (boolean)var1[1]);
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "fw_dig_enable = %2x\n", dig_t->fw_dig_enable);
++		}
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++
++#ifdef CONFIG_MCC_DM
++#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT)
++void phydm_mcc_igi_clr(void *dm_void, u8 clr_port)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
++
++	mcc_dm->mcc_rssi[clr_port] = 0xff;
++	mcc_dm->mcc_dm_val[0][clr_port] = 0xff; /* 0xc50 clr */
++	mcc_dm->mcc_dm_val[1][clr_port] = 0xff; /* 0xe50 clr */
++}
++
++void phydm_mcc_igi_chk(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
++
++	if (mcc_dm->mcc_dm_val[0][0] == 0xff &&
++	    mcc_dm->mcc_dm_val[0][1] == 0xff) {
++		mcc_dm->mcc_dm_reg[0] = 0xffff;
++		mcc_dm->mcc_reg_id[0] = 0xff;
++	}
++	if (mcc_dm->mcc_dm_val[1][0] == 0xff &&
++	    mcc_dm->mcc_dm_val[1][1] == 0xff) {
++		mcc_dm->mcc_dm_reg[1] = 0xffff;
++		mcc_dm->mcc_reg_id[1] = 0xff;
++	}
++}
++
++void phydm_mcc_igi_cal(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	u8	shift = 0;
++	u8	igi_val0, igi_val1;
++
++	if (mcc_dm->mcc_rssi[0] == 0xff)
++		phydm_mcc_igi_clr(dm, 0);
++	if (mcc_dm->mcc_rssi[1] == 0xff)
++		phydm_mcc_igi_clr(dm, 1);
++	phydm_mcc_igi_chk(dm);
++	igi_val0 = mcc_dm->mcc_rssi[0] - shift;
++	igi_val1 = mcc_dm->mcc_rssi[1] - shift;
++
++	if (igi_val0 < DIG_MIN_PERFORMANCE)
++		igi_val0 = DIG_MIN_PERFORMANCE;
++
++	if (igi_val1 < DIG_MIN_PERFORMANCE)
++		igi_val1 = DIG_MIN_PERFORMANCE;
++
++	switch (dm->ic_ip_series) {
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	case PHYDM_IC_JGR3:
++		phydm_fill_mcccmd(dm, 0, R_0x1d70, igi_val0, igi_val1);
++		phydm_fill_mcccmd(dm, 1, R_0x1d70 + 1, igi_val0, igi_val1);
++		break;
++	#endif
++	default:
++		phydm_fill_mcccmd(dm, 0, R_0xc50, igi_val0, igi_val1);
++		phydm_fill_mcccmd(dm, 1, R_0xe50, igi_val0, igi_val1);
++		break;
++	}
++
++	PHYDM_DBG(dm, DBG_COMP_MCC, "RSSI_min: %d %d, MCC_igi: %d %d\n",
++		  mcc_dm->mcc_rssi[0], mcc_dm->mcc_rssi[1],
++		  mcc_dm->mcc_dm_val[0][0], mcc_dm->mcc_dm_val[0][1]);
++}
++#endif /*#if (RTL8822B_SUPPORT)*/
++#endif /*#ifdef CONFIG_MCC_DM*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dig.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dig.h
+new file mode 100644
+index 000000000..6f08ef914
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dig.h
+@@ -0,0 +1,373 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDMDIG_H__
++#define __PHYDMDIG_H__
++
++/* 2019.09.25 modify T3 value in init flow*/
++#define DIG_VERSION "3.6"
++
++#define	DIG_HW		0
++#define DIG_LIMIT_PERIOD 60 /*60 sec*/
++
++/*@--------------------Define ---------------------------------------*/
++
++/*@=== [DIG Boundary] ========================================*/
++/*@DIG coverage mode*/
++#define	DIG_MAX_COVERAGR		0x26
++#define	DIG_MIN_COVERAGE		0x1c
++#define	DIG_MAX_OF_MIN_COVERAGE		0x22
++
++/*@[DIG Balance mode]*/
++#if (DIG_HW == 1)
++#define	DIG_MAX_BALANCE_MODE		0x32
++#else
++#define	DIG_MAX_BALANCE_MODE		0x3e
++#endif
++#define	DIG_MAX_OF_MIN_BALANCE_MODE	0x2a
++
++/*@[DIG Performance mode]*/
++#define	DIG_MAX_PERFORMANCE_MODE	0x5a
++#define	DIG_MAX_OF_MIN_PERFORMANCE_MODE	0x40	/*@[WLANBB-871]*/
++#define	DIG_MIN_PERFORMANCE		0x20
++
++/*@DIG DFS function*/
++#define	DIG_MAX_DFS			0x28
++#define	DIG_MIN_DFS			0x20
++
++/*@DIG LPS function*/
++#define	DIG_MAX_LPS			0x3e
++#define	DIG_MIN_LPS			0x20
++
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++#define DIG_NUM_OF_TDMA_STATES	2 /*@L, H state*/
++#define DIG_TIMER_MS			250
++#define	ONE_SEC_MS			1000
++#endif
++
++/*@=== [DIG FA Threshold] ======================================*/
++
++/*Normal*/
++#define	DM_DIG_FA_TH0			500
++#define	DM_DIG_FA_TH1			750
++
++/*@LPS*/
++#define	DM_DIG_FA_TH0_LPS		4	/* @-> 4 lps */
++#define	DM_DIG_FA_TH1_LPS		15	/* @-> 15 lps */
++#define	DM_DIG_FA_TH2_LPS		30	/* @-> 30 lps */
++
++#define	RSSI_OFFSET_DIG_LPS		5
++#define DIG_RECORD_NUM			4
++
++/*@--------------------Enum-----------------------------------*/
++enum phydm_dig_mode {
++	PHYDM_DIG_PERFORAMNCE_MODE	= 0,
++	PHYDM_DIG_COVERAGE_MODE		= 1,
++};
++
++enum phydm_dig_trend {
++	DIG_STABLE			= 0,
++	DIG_INCREASING			= 1,
++	DIG_DECREASING			= 2
++};
++
++enum phydm_fw_dig_mode_e {
++	DIG_PERFORMANCE_MODE	= 0,
++	DIG_COVERAGE_MODE	= 1,
++	DIG_LPS_MODE		= 2
++};
++
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++enum upd_type {
++	ENABLE_TDMA,
++	MODE_DECISION
++};
++
++enum tdma_opmode {
++	MODE_PERFORMANCE = 1,
++	MODE_COVERAGE = 2
++};
++
++#ifdef IS_USE_NEW_TDMA
++enum tdma_dig_timer {
++	INIT_TDMA_DIG_TIMMER,
++	CANCEL_TDMA_DIG_TIMMER,
++	RELEASE_TDMA_DIG_TIMMER
++};
++
++enum tdma_dig_state {
++	TDMA_DIG_LOW_STATE = 0,
++	TDMA_DIG_HIGH_STATE = 1,
++	NORMAL_DIG = 2
++};
++#endif
++#endif
++
++/*@--------------------Define Struct-----------------------------------*/
++#ifdef CFG_DIG_DAMPING_CHK
++struct phydm_dig_recorder_strcut {
++	u8		igi_bitmap; /*@Don't add any new parameter before this*/
++	u8		igi_history[DIG_RECORD_NUM];
++	u32		fa_history[DIG_RECORD_NUM];
++	u8		damping_limit_en;
++	u8		damping_limit_val; /*@Limit IGI_dyn_min*/
++	u32		limit_time;
++	u8		limit_rssi;
++};
++#endif
++
++struct phydm_mcc_dig {
++	u8		mcc_rssi_A;
++	u8		mcc_rssi_B;
++};
++
++struct phydm_dig_struct {
++#ifdef CFG_DIG_DAMPING_CHK
++	struct phydm_dig_recorder_strcut dig_recorder_t;
++	u8		dig_dl_en; /*@damping limit function enable*/
++#endif
++	boolean		fw_dig_enable;
++	boolean		is_dbg_fa_th;
++	u8		cur_ig_value;
++	boolean		igi_dyn_up_hit;
++	u8		igi_trend;
++	u32		rvrt_val; /*all rvrt_val for pause API must set to u32*/
++	u8		igi_backup;
++	u8		rx_gain_range_max;	/*@dig_dynamic_max*/
++	u8		rx_gain_range_min;	/*@dig_dynamic_min*/
++	u8		dm_dig_max;		/*@Absolutly upper bound*/
++	u8		dm_dig_min;		/*@Absolutly lower bound*/
++	u8		dig_max_of_min;		/*@Absolutly max of min*/
++	u32		ant_div_rssi_max;
++	u8		*is_p2p_in_process;
++	u16		fa_th[3];
++#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\
++	RTL8198F_SUPPORT || RTL8192F_SUPPORT || RTL8195B_SUPPORT ||\
++	RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8721D_SUPPORT ||\
++	RTL8710C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
++	u8		rf_gain_idx;
++	u8		agc_table_idx;
++	u8		big_jump_lmt[16];
++	u8		enable_adjust_big_jump:1;
++	u8		big_jump_step1:3;
++	u8		big_jump_step2:2;
++	u8		big_jump_step3:2;
++#endif
++	u8		upcheck_init_val;
++	u8		lv0_ratio_reciprocal;
++	u8		lv1_ratio_reciprocal;
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++	u8		cur_ig_value_tdma;
++	u8		low_ig_value;
++	u8		tdma_dig_state;	/*@To distinguish which state is now.(L-sate or H-state)*/
++	u8		tdma_dig_cnt;	/*@for phydm_tdma_dig_timer_check use*/
++	u8		pre_tdma_dig_cnt;
++	u8		sec_factor;
++	u32		cur_timestamp;
++	u32		pre_timestamp;
++	u32		fa_start_timestamp;
++	u32		fa_end_timestamp;
++	u32		fa_acc_1sec_timestamp;
++#ifdef IS_USE_NEW_TDMA
++	u8		tdma_dig_block_cnt;/*@for 1 second dump indicator use*/
++			/*@dynamic upper bound for L/H state*/
++	u8		tdma_rx_gain_max[DIG_NUM_OF_TDMA_STATES];
++			/*@dynamic lower bound for L/H state*/
++	u8		tdma_rx_gain_min[DIG_NUM_OF_TDMA_STATES];
++			/*To distinguish current state(L-sate or H-state)*/
++#endif
++	u8		tdma_force_l_igi;
++	u8		tdma_force_h_igi;
++#endif
++};
++
++struct phydm_fa_struct {
++	u32		cnt_parity_fail;
++	u32		cnt_rate_illegal;
++	u32		cnt_crc8_fail;
++	u32		cnt_crc8_fail_vhta;
++	u32		cnt_crc8_fail_vhtb;
++	u32		cnt_mcs_fail;
++	u32		cnt_mcs_fail_vht;
++	u32		cnt_ofdm_fail;
++	u32		cnt_ofdm_fail_pre;	/* @For RTL8881A */
++	u32		cnt_cck_fail;
++	u32		cnt_all;
++	u32		cnt_all_accumulated;
++	u32		cnt_all_pre;
++	u32		cnt_fast_fsync;
++	u32		cnt_sb_search_fail;
++	u32		cnt_ofdm_cca;
++	u32		cnt_cck_cca;
++	u32		cnt_cca_all;
++	u32		cnt_bw_usc;
++	u32		cnt_bw_lsc;
++	u32		cnt_cck_crc32_error;
++	u32		cnt_cck_crc32_ok;
++	u32		cnt_ofdm_crc32_error;
++	u32		cnt_ofdm_crc32_ok;
++	u32		cnt_ht_crc32_error;
++	u32		cnt_ht_crc32_ok;
++	u32		cnt_ht_crc32_error_agg;
++	u32		cnt_ht_crc32_ok_agg;
++	u32		cnt_vht_crc32_error;
++	u32		cnt_vht_crc32_ok;
++	u32		cnt_crc32_error_all;
++	u32		cnt_crc32_ok_all;
++	u32		time_fa_all;
++	boolean		cck_block_enable;
++	boolean		ofdm_block_enable;
++	u32		dbg_port0;
++	boolean		edcca_flag;
++	u8		ofdm2_rate_idx;
++	u32		cnt_ofdm2_crc32_error;
++	u32		cnt_ofdm2_crc32_ok;
++	u8		ofdm2_pcr;
++	u8		ht2_rate_idx;
++	u32		cnt_ht2_crc32_error;
++	u32		cnt_ht2_crc32_ok;
++	u8		ht2_pcr;
++	u8		vht2_rate_idx;
++	u32		cnt_vht2_crc32_error;
++	u32		cnt_vht2_crc32_ok;
++	u8		vht2_pcr;
++
++};
++
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++struct phydm_fa_acc_struct {
++	u32		cnt_parity_fail;
++	u32		cnt_rate_illegal;
++	u32		cnt_crc8_fail;
++	u32		cnt_mcs_fail;
++	u32		cnt_ofdm_fail;
++	u32		cnt_ofdm_fail_pre;	/*@For RTL8881A*/
++	u32		cnt_cck_fail;
++	u32		cnt_all;
++	u32		cnt_all_pre;
++	u32		cnt_fast_fsync;
++	u32		cnt_sb_search_fail;
++	u32		cnt_ofdm_cca;
++	u32		cnt_cck_cca;
++	u32		cnt_cca_all;
++	u32		cnt_cck_crc32_error;
++	u32		cnt_cck_crc32_ok;
++	u32		cnt_ofdm_crc32_error;
++	u32		cnt_ofdm_crc32_ok;
++	u32		cnt_ht_crc32_error;
++	u32		cnt_ht_crc32_ok;
++	u32		cnt_vht_crc32_error;
++	u32		cnt_vht_crc32_ok;
++	u32		cnt_crc32_error_all;
++	u32		cnt_crc32_ok_all;
++	u32		cnt_all_1sec;
++	u32		cnt_cca_all_1sec;
++	u32		cnt_cck_fail_1sec;
++};
++
++#endif	/*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
++
++/*@--------------------Function declaration-----------------------------*/
++void phydm_write_dig_reg(void *dm_void, u8 igi);
++
++void odm_write_dig(void *dm_void, u8 current_igi);
++
++u8 phydm_get_igi(void *dm_void, enum bb_path path);
++
++void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len);
++
++void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type,
++		   enum phydm_pause_level pause_level, u8 igi_value);
++
++#ifdef PHYDM_HW_IGI
++void phydm_hwigi(void *dm_void);
++
++void phydm_hwigi_dbg(void *dm_void, char input[][16], u32 *_used,
++		     char *output, u32 *_out_len);
++#endif
++
++void phydm_dig_init(void *dm_void);
++
++void phydm_dig(void *dm_void);
++
++void phydm_dig_lps_32k(void *dm_void);
++
++void phydm_dig_by_rssi_lps(void *dm_void);
++
++void phydm_false_alarm_counter_statistics(void *dm_void);
++
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++void phydm_set_tdma_dig_timer(void *dm_void);
++
++void phydm_tdma_dig_timer_check(void *dm_void);
++
++void phydm_tdma_dig(void *dm_void);
++
++void phydm_tdma_false_alarm_counter_check(void *dm_void);
++
++void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void);
++
++void phydm_false_alarm_counter_reset(void *dm_void);
++
++void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en);
++
++void phydm_false_alarm_counter_acc_reset(void *dm_void);
++
++void phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input);
++
++#ifdef IS_USE_NEW_TDMA
++void phydm_tdma_dig_timers(void *dm_void, u8 state);
++
++void phydm_tdma_dig_cbk(void *dm_void);
++
++void phydm_tdma_dig_workitem_callback(void *dm_void);
++
++void phydm_tdma_fa_cnt_chk(void *dm_void);
++
++void phydm_tdma_low_dig(void *dm_void);
++
++void phydm_tdma_high_dig(void *dm_void);
++
++void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en,
++		      u8 cur_tdma_dig_state);
++#endif /*@#ifdef IS_USE_NEW_TDMA*/
++#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
++
++void phydm_set_ofdm_agc_tab(void *dm_void, u8 tab_sel);
++
++void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,
++		     u32 *_out_len);
++
++void phydm_fill_fw_dig_info(void *dm_void, boolean *enable,
++			    u8 *para4, u8 *para8);
++
++void phydm_crc32_cnt_dbg(void *dm_void, char input[][16], u32 *_used,
++			 char *output, u32 *_out_len);
++
++#ifdef CONFIG_MCC_DM
++void phydm_mcc_igi_cal(void *dm_void);
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_direct_bf.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_direct_bf.c
+new file mode 100644
+index 000000000..55dd2f8da
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_direct_bf.c
+@@ -0,0 +1,366 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ ***************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++#ifdef CONFIG_DIRECTIONAL_BF
++#ifdef PHYDM_COMPILE_IC_2SS
++void phydm_iq_gen_en(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	enum rf_path i = RF_PATH_A;
++	enum rf_path path = RF_PATH_A;
++
++	#if (ODM_IC_11AC_SERIES_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8822B) {
++		for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
++			/*RF mode table write enable*/
++			odm_set_rf_reg(dm, path, RF_0xef, BIT(19), 0x1);
++			/*Select RX mode*/
++			odm_set_rf_reg(dm, path, RF_0x33, 0xF, 3);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, path, RF_0x3e, 0xfffff, 0x00036);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, path, RF_0x3f, 0xfffff, 0x5AFCE);
++			/*RF mode table write disable*/
++			odm_set_rf_reg(dm, path, RF_0xef, BIT(19), 0x0);
++		}
++	}
++	#endif
++
++	#if (ODM_IC_11N_SERIES_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8192F) {
++		/*RF mode table write enable*/
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1);
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1);
++		/* Path A */
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x08000);
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0005f);
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x01042);
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000);
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0004f);
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x71fc2);
++		/* Path B */
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x08000);
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x00050);
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x01042);
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000);
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x00040);
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x71fc2);
++		/*RF mode table write disable*/
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0);
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0);
++	}
++	#endif
++
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	if (dm->support_ic_type & ODM_RTL8197G) {
++		/*RF mode table write enable*/
++		/* Path A */
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1);
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000);
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x000cf);
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x71fc2);
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0);
++
++		/* Path B */
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1);
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000);
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x000cf);
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x71fc2);
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x08000);
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x000ef);
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x01042);
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0);
++	}
++	#endif
++
++}
++
++void phydm_dis_cdd(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	#if (ODM_IC_11AC_SERIES_SUPPORT)
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		odm_set_bb_reg(dm, R_0x808, 0x3ffff00, 0);
++		odm_set_bb_reg(dm, R_0x9ac, 0x1fff, 0);
++		odm_set_bb_reg(dm, R_0x9ac, BIT(13), 1);
++	}
++	#endif
++	#if (ODM_IC_11N_SERIES_SUPPORT)
++	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		odm_set_bb_reg(dm, R_0x90c, 0xffffffff, 0x83321333);
++		/* Set Tx delay setting for CCK pathA,B*/
++		odm_set_bb_reg(dm, R_0xa2c, 0xf0000000, 0);
++		/*Enable Tx CDD for HT part when spatial expansion is applied*/
++		odm_set_bb_reg(dm, R_0xd00, BIT(8), 0);
++		/* Tx CDD for Legacy*/
++		odm_set_bb_reg(dm, R_0xd04, 0xf0000, 0);
++		/* Tx CDD for non-HT*/
++		odm_set_bb_reg(dm, R_0xd0c, 0x3c0, 0);
++		/* Tx CDD for HT SS1*/
++		odm_set_bb_reg(dm, R_0xd0c, 0xf8000, 0);
++	}
++	#endif
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		/* Tx CDD for Legacy Preamble*/
++		odm_set_bb_reg(dm, R_0x1cc0, 0xffffffff, 0x24800000);
++		/* Tx CDD for HT Preamble*/
++		odm_set_bb_reg(dm, R_0x1cb0, 0xffffffff, 0);
++	}
++	#endif
++}
++
++void phydm_pathb_q_matrix_rotate_en(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	phydm_iq_gen_en(dm);
++
++	/*#ifdef PHYDM_COMMON_API_SUPPORT*/
++	/*path selection is controlled by driver*/
++	#if 0
++	if (!phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, BB_PATH_AB))
++		return;
++	#endif
++
++	phydm_dis_cdd(dm);
++	phydm_pathb_q_matrix_rotate(dm, 0);
++
++	#if (ODM_IC_11AC_SERIES_SUPPORT)
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		/*Set Q matrix r_v11 =1*/
++		odm_set_bb_reg(dm, R_0x195c, MASKDWORD, 0x40000);
++		/*Set Q matrix enable*/
++		odm_set_bb_reg(dm, R_0x191c, BIT(7), 1);
++	}
++	#endif
++}
++
++void phydm_pathb_q_matrix_rotate(void *dm_void, u16 idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	#if (ODM_IC_11AC_SERIES_SUPPORT)
++	u32 phase_table_0[ANGLE_NUM] = {0x40000, 0x376CF, 0x20000, 0x00000,
++					0xFE0000, 0xFC8930, 0xFC0000,
++					0xFC8930, 0xFDFFFF, 0x000000,
++					0x020000, 0x0376CF};
++	u32 phase_table_1[ANGLE_NUM] = {0x00000, 0x1FFFF, 0x376CF, 0x40000,
++					0x0376CF, 0x01FFFF, 0x000000,
++					0xFDFFFF, 0xFC8930, 0xFC0000,
++					0xFC8930, 0xFDFFFF};
++	#endif
++	#if (ODM_IC_11N_SERIES_SUPPORT)
++	u32 phase_table_n_0[ANGLE_NUM] = {0x00, 0x0B, 0x02, 0x00, 0x02, 0x02,
++					  0x04, 0x02, 0x0D, 0x09, 0x04, 0x0B};
++	u32 phase_table_n_1[ANGLE_NUM] = {0x40000100, 0x377F00DD, 0x201D8880,
++					  0x00000000, 0xE01D8B80, 0xC8BF0322,
++					  0xC000FF00, 0xC8BF0322, 0xDFE2777F,
++					  0xFFC003FF, 0x20227480, 0x377F00DD};
++	u32 phase_table_n_2[ANGLE_NUM] = {0x00, 0x1E, 0x3C, 0x4C, 0x3C, 0x1E,
++					  0x0F, 0xD2, 0xC3, 0xC4, 0xC3, 0xD2};
++	#endif
++	if (idx >= ANGLE_NUM) {
++		pr_debug("[%s]warning Phase Set Error: %d\n", __func__, idx);
++		return;
++	}
++
++	switch (dm->ic_ip_series) {
++	#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
++	case PHYDM_IC_AC:
++		/*Set Q matrix r_v21*/
++		odm_set_bb_reg(dm, R_0x1954, 0xffffff, phase_table_0[idx]);
++		odm_set_bb_reg(dm, R_0x1950, 0xffffff, phase_table_1[idx]);
++		break;
++	#endif
++
++	#if (ODM_IC_11N_SERIES_SUPPORT == 1)
++	case PHYDM_IC_N:
++		/*Set Q matrix r_v21*/
++		odm_set_bb_reg(dm, R_0xc4c, 0xff000000, phase_table_n_0[idx]);
++		odm_set_bb_reg(dm, R_0xc88, 0xffffffff, phase_table_n_1[idx]);
++		odm_set_bb_reg(dm, R_0xc9c, 0xff000000, phase_table_n_2[idx]);
++		break;
++	#endif
++
++	default:
++		break;
++	}
++}
++
++/*Before use this API, Fill correct Tx Des. and Disable STBC in advance*/
++void phydm_set_direct_bfer(void *dm_void, u16 phs_idx, u8 su_idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if (RTL8822B_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8822B) {
++#if 0
++		u8 phi[13] = {0x0, 0x5, 0xa, 0xf, 0x15, 0x1a, 0x1f, 0x25,
++			      0x2a, 0x2f, 0x35, 0x3a, 0x0};
++		u8 psi[13] = {0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
++			      0x7, 0x7, 0x7, 0x7};
++		u16 psiphi[13] = {0x1c0, 0x1c5, 0x1ca, 0x1cf, 0x1d5, 0x1da,
++				  0x1df, 0x1e5, 0x1ea, 0x1ef, 0x1f5, 0x1fa,
++				  0x1c0}; //{Psi_4bit, Phi_6bit} of 0~360
++#endif
++		u16 ns[3] = {52, 108, 234}; //20/40/80 MHz subcarrier number
++		u16 psiphi[13] = {0x1c0, 0x1c5, 0x1ca, 0x1cf, 0x1d5, 0x1da,
++				  0x1df, 0x1e5, 0x1ea, 0x1ef, 0x1f5, 0x1fa,
++				  0x1c0}; //{Psi_4bit, Phi_6bit} of 0~360
++		u16 psiphiR;
++		u8 i;
++		u8 snr = 0x12; // for 1SS BF
++		u8 nc = 0x0; //bit 2-0
++		u8 nr = 0x1; //bit 5-3
++		u8 ng = 0x0; //bit 7-6
++		u8 cb = 0x1; //bit 9-8; 1 => phi:6, psi:4;
++		u32 bw = odm_get_bb_reg(dm, R_0x8ac, 0x3); //bit 11-10
++		u8 userid = su_idx; //bit 12
++		u32 csi_report = 0x0;
++		u32 ndp_bw = odm_get_bb_reg(dm, R_0x8ac, 0x3); //bit 11-10
++		u8 ndp_sc = 0; //bit 11-10
++		u32 ndp_info = 0x0;
++
++		u16 mem_num = 0;
++		u8 mem_move = 0;
++		u8 mem_sel = 0;
++		u16 mem_addr = 0;
++		u32 dw0, dw1;
++		u64 vm_info = 0;
++		u64 temp = 0;
++		u8 vm_cnt = 0;
++
++		mem_num = ((8 + (6 + 4) * ns[bw]) >> 6) + 1; // SU codebook 1
++
++		/* setting NDP BW/SC info*/
++		ndp_info = (ndp_bw & 0x3)  | (ndp_bw & 0x3) << 6 |
++			   (ndp_bw & 0x3) << 12 | (ndp_sc & 0xf) << 2 |
++			   (ndp_sc & 0xf) << 8 | (ndp_sc & 0xf) << 14;
++		odm_set_bb_reg(dm, R_0xb58, 0x000FFFFC, ndp_info);
++		odm_set_bb_reg(dm, R_0x19f8, 0x00010000, 1);
++		ODM_delay_ms(1); // delay 1ms
++		odm_set_bb_reg(dm, R_0x19f8, 0x00010000, 0);
++
++		/* setting CSI report info*/
++		csi_report = (userid & 0x1) << 12 | (bw & 0x3) << 10 |
++			     (cb & 0x3) << 8 | (ng & 0x3) << 6 |
++			     (nr & 0x7) << 3 | (nc & 0x7);
++		odm_set_bb_reg(dm, R_0x72c, 0x1FFF, csi_report);
++		odm_set_bb_reg(dm, R_0x71c, 0x80000000, 1);
++		PHYDM_DBG(dm, DBG_TXBF, "[%s] direct BF csi report 0x%x\n",
++			  __func__, csi_report);
++		/*========================*/
++
++		odm_set_bb_reg(dm, R_0x19b8, 0x40, 1); //0x19b8[6]:1 to csi_rpt
++		odm_set_bb_reg(dm, R_0x19e0, 0x3FC0, 0xFF); //gated_clk off
++		odm_set_bb_reg(dm, R_0x9e8, 0x2000000, 1); //abnormal txbf
++		odm_set_bb_reg(dm, R_0x9e8, 0x1000000, 0); //read phi psi
++		odm_set_bb_reg(dm, R_0x9e8, 0x70000000, su_idx); //SU user 0
++		odm_set_bb_reg(dm, R_0x1910, 0x8000, 0); //BFer
++
++		dw0 = 0; // for 0x9ec
++		dw1 = 0; // for 0x1900
++		mem_addr = 0;
++		mem_sel = 0;
++		mem_move = 0;
++		vm_info = vm_info | (snr & 0xff); //V matrix info
++		vm_cnt = 8; // V matrix length counter
++		psiphiR = (psiphi[phs_idx] & 0x3ff);
++
++		while (mem_addr < mem_num) {
++			while (vm_cnt <= 32) {
++				// shift only max. 32 bit
++				if (vm_cnt >= 20) {
++					temp = psiphiR << 20;
++					temp = temp << (vm_cnt - 20);
++				} else {
++					temp = psiphiR << vm_cnt;
++				}
++				vm_info |= temp;
++				vm_cnt += 10;
++			}
++			if (mem_sel == 0) {
++				dw0 = vm_info & 0xffffffff;
++				vm_info = vm_info >> 32;
++				vm_cnt -= 32;
++				mem_sel = 1;
++				mem_move = 0;
++			} else {
++				dw1 = vm_info & 0xffffffff;
++				vm_info = vm_info >> 32;
++				vm_cnt -= 32;
++				mem_sel = 0;
++				mem_move = 1;
++			}
++			if (mem_move == 1) {
++				odm_set_bb_reg(dm, 0x9e8, 0x1000000, 0);
++					       //read phi psi
++				odm_set_bb_reg(dm, 0x1910, 0x3FF0000,
++					       mem_addr);
++				odm_set_bb_reg(dm, 0x09ec, 0xFFFFFFFF, dw0);
++				odm_set_bb_reg(dm, 0x1900, 0xFFFFFFFF, dw1);
++				odm_set_bb_reg(dm, 0x9e8, 0x1000000, 1);
++					       //write phi psi
++				mem_move = 0;
++				mem_addr += 1;
++			}
++		}
++		odm_set_bb_reg(dm, 0x9e8, 0x2000000, 0); //normal txbf
++	}
++#endif
++} //end function
++
++/*Before use this API, Disable STBC in advance*/
++/*only 1SS rate can improve performance*/
++void phydm_set_direct_bfer_txdesc_en(void *dm_void, u8 enable)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if (RTL8197G_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8197G) {
++		phydm_iq_gen_en(dm);
++
++		/*#ifdef PHYDM_COMMON_API_SUPPORT*/
++		/*path selection is controlled by driver, use 1ss 2Tx*/
++		#if 0
++		if (!phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, BB_PATH_AB))
++			return;
++		#endif
++
++		phydm_dis_cdd(dm);
++		if (enable)
++			odm_set_bb_reg(dm, R_0x1d90, 0x8000, 1);
++		else
++			odm_set_bb_reg(dm, R_0x1d90, 0x8000, 0);
++	}
++#endif
++} //end function
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_direct_bf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_direct_bf.h
+new file mode 100644
+index 000000000..c9c4c4bed
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_direct_bf.h
+@@ -0,0 +1,44 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_DIR_BF_H__
++#define __PHYDM_DIR_BF_H__
++
++#ifdef CONFIG_DIRECTIONAL_BF
++#define ANGLE_NUM	12
++
++/*@
++ * ============================================================
++ * function prototype
++ * ============================================================
++ */
++void phydm_iq_gen_en(void *dm_void);
++void phydm_dis_cdd(void *dm_void);
++void phydm_pathb_q_matrix_rotate_en(void *dm_void);
++void phydm_pathb_q_matrix_rotate(void *dm_void, u16 idx);
++void phydm_set_direct_bfer(void *dm_void, u16 phs_idx, u8 su_idx);
++void phydm_set_direct_bfer_txdesc_en(void *dm_void, u8 enable);
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dynamictxpower.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dynamictxpower.c
+new file mode 100644
+index 000000000..423ba0504
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dynamictxpower.c
+@@ -0,0 +1,764 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*************************************************************
++ * include files
++ ************************************************************/
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#ifdef CONFIG_DYNAMIC_TX_TWR
++#ifdef BB_RAM_SUPPORT
++void phydm_rd_reg_pwr(void *dm_void, u32 *_used, char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	boolean pwr_ofst0_en = false;
++	boolean pwr_ofst1_en = false;
++	s8 pwr_ofst0 = 0;
++	s8 pwr_ofst1 = 0;
++
++	pwr_ofst0_en = (boolean)odm_get_bb_reg(dm, R_0x1e70, BIT(23));
++	pwr_ofst1_en = (boolean)odm_get_bb_reg(dm, R_0x1e70, BIT(31));
++	pwr_ofst0 = (s8)odm_get_bb_reg(dm, R_0x1e70, 0x7f0000);
++	pwr_ofst1 = (s8)odm_get_bb_reg(dm, R_0x1e70, 0x7f000000);
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "reg0: en:%d, pwr_ofst:0x%x, reg1: en:%d, pwr_ofst:0x%x\n",
++		 pwr_ofst0_en, pwr_ofst0, pwr_ofst1_en, pwr_ofst1);
++
++	*_used = used;
++	*_out_len = out_len;
++};
++
++void phydm_wt_reg_pwr(void *dm_void, boolean is_ofst1, boolean pwr_ofst_en,
++		      s8 pwr_ofst)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
++	u8 reg_0x1e70 = 0;
++
++	if (!is_ofst1) {
++		bb_ctrl->tx_pwr_ofst_reg0_en = pwr_ofst_en;
++		bb_ctrl->tx_pwr_ofst_reg0 = pwr_ofst;
++
++		reg_0x1e70 |= (pwr_ofst_en << 7) + (pwr_ofst & 0x7f);
++		odm_set_bb_reg(dm, R_0x1e70, 0x00ff0000, reg_0x1e70);
++	} else {
++		bb_ctrl->tx_pwr_ofst_reg1_en = pwr_ofst_en;
++		bb_ctrl->tx_pwr_ofst_reg1 = pwr_ofst;
++
++		reg_0x1e70 |= (pwr_ofst_en << 7) + (pwr_ofst & 0x7f);
++		odm_set_bb_reg(dm, R_0x1e70, 0xff000000, reg_0x1e70);
++	}
++};
++
++void phydm_rd_ram_pwr(void *dm_void, u8 macid, u32 *_used, char *output,
++		      u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	boolean pwr_ofst0_en = false;
++	boolean pwr_ofst1_en = false;
++	s8 pwr_ofst0 = 0;
++	s8 pwr_ofst1 = 0;
++	u32 reg_0x1e84 = 0;
++
++	reg_0x1e84 |= (macid & 0x3f) << 24; /* macid*/
++	reg_0x1e84 |= BIT(31); /* read_en*/
++	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
++
++	pwr_ofst0_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(23));
++	pwr_ofst1_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(31));
++	pwr_ofst0 = (s8)odm_get_bb_reg(dm, R_0x2de8, 0x7f0000);
++	pwr_ofst1 = (s8)odm_get_bb_reg(dm, R_0x2de8, 0x7f000000);
++	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "(macid:%d) ram0: en:%d, pwr_ofst:0x%x, ram1: en:%d, pwr_ofst:0x%x\n",
++		 macid, pwr_ofst0_en, pwr_ofst0, pwr_ofst1_en, pwr_ofst1);
++
++	*_used = used;
++	*_out_len = out_len;
++};
++
++void phydm_wt_ram_pwr(void *dm_void, u8 macid, boolean is_ofst1,
++		      boolean pwr_ofst_en, s8 pwr_ofst)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
++	u32 reg_0x1e84 = 0;
++	boolean pwr_ofst_ano_en = false;
++	s8 pwr_ofst_ano = 0;
++
++	if (macid > 63)
++		macid = 63;
++
++	dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[macid];
++	reg_0x1e84 = (dm_ram_per_sta->hw_igi_en << 7) + dm_ram_per_sta->hw_igi;
++	if (!is_ofst1) {
++		dm_ram_per_sta->tx_pwr_offset0_en = pwr_ofst_en;
++		dm_ram_per_sta->tx_pwr_offset0 = pwr_ofst;
++
++		pwr_ofst_ano_en = dm_ram_per_sta->tx_pwr_offset1_en;
++		pwr_ofst_ano = dm_ram_per_sta->tx_pwr_offset1;
++
++		reg_0x1e84 |= (pwr_ofst_en << 15) + ((pwr_ofst & 0x7f) << 8) +
++			      (pwr_ofst_ano_en << 23) +
++			      ((pwr_ofst_ano & 0x7f) << 16);
++	} else {
++		dm_ram_per_sta->tx_pwr_offset1_en = pwr_ofst_en;
++		dm_ram_per_sta->tx_pwr_offset1 = pwr_ofst;
++
++		pwr_ofst_ano_en = dm_ram_per_sta->tx_pwr_offset0_en;
++		pwr_ofst_ano = dm_ram_per_sta->tx_pwr_offset0;
++
++		reg_0x1e84 |= (pwr_ofst_ano_en << 15) +
++			      ((pwr_ofst_ano & 0x7f) << 8) +
++			      (pwr_ofst_en << 23) +  ((pwr_ofst & 0x7f) << 16);
++	}
++	reg_0x1e84 |= (macid & 0x3f) << 24;/* macid*/
++	reg_0x1e84 |= BIT(30); /* write_en*/
++	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
++	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000); /* read_en*/
++	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/
++};
++
++void phydm_rst_ram_pwr(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
++	u32 reg_0x1e84 = 0;
++	u8 i = 0;
++
++	for (i = 0; i < 64; i++) {
++		dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[i];
++		dm_ram_per_sta->tx_pwr_offset0_en = false;
++		dm_ram_per_sta->tx_pwr_offset1_en = false;
++		dm_ram_per_sta->tx_pwr_offset0 = 0x0;
++		dm_ram_per_sta->tx_pwr_offset1 = 0x0;
++		reg_0x1e84 = (dm_ram_per_sta->hw_igi_en << 7) +
++			     dm_ram_per_sta->hw_igi;
++		reg_0x1e84 |= (i & 0x3f) << 24;
++		reg_0x1e84 |= BIT(30);
++		odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
++	}
++
++	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000);
++	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0);
++};
++
++u8 phydm_pwr_lv_mapping_2nd(u8 tx_pwr_lv)
++{
++	if (tx_pwr_lv == tx_high_pwr_level_level3)
++		return PHYDM_2ND_OFFSET_MINUS_11DB;
++	else if (tx_pwr_lv == tx_high_pwr_level_level2)
++		return PHYDM_2ND_OFFSET_MINUS_7DB;
++	else if (tx_pwr_lv == tx_high_pwr_level_level1)
++		return PHYDM_2ND_OFFSET_MINUS_3DB;
++	else
++		return PHYDM_2ND_OFFSET_ZERO;
++}
++
++void phydm_pwr_lv_ctrl(void *dm_void, u8 macid, u8 tx_pwr_lv)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	s8 pwr_offset = 0;
++
++	if (tx_pwr_lv == tx_high_pwr_level_level3)
++		pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_11DB;
++	else if (tx_pwr_lv == tx_high_pwr_level_level2)
++		pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_7DB;
++	else if (tx_pwr_lv == tx_high_pwr_level_level1)
++		pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_3DB;
++	else
++		pwr_offset = PHYDM_BBRAM_OFFSET_ZERO;
++
++	phydm_wt_ram_pwr(dm, macid, RAM_PWR_OFST0, true, pwr_offset);
++}
++
++void phydm_dtp_fill_cmninfo_2nd(void *dm_void, u8 sta_id, u8 dtp_lvl)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id];
++	struct dtp_info *dtp = NULL;
++
++	if (!is_sta_active(sta))
++		return;
++
++	dtp = &dm->phydm_sta_info[sta_id]->dtp_stat;
++	dtp->dyn_tx_power = phydm_pwr_lv_mapping_2nd(dtp_lvl);
++	phydm_pwr_lv_ctrl(dm, sta->mac_id, dtp_lvl);
++
++	PHYDM_DBG(dm, DBG_DYN_TXPWR,
++		  "Fill cmninfo TxPwr: sta_id=(%d), macid=(%d), PwrLv (%d)\n",
++		  sta_id, sta->mac_id, dtp->dyn_tx_power);
++}
++
++void phydm_dtp_init_2nd(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
++		return;
++
++	#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT)
++	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {
++		phydm_rst_ram_pwr(dm);
++		/* rsp tx use type 0*/
++		odm_set_mac_reg(dm, R_0x6d8, BIT(19) | BIT(18), RAM_PWR_OFST0);
++	}
++	#endif
++};
++#endif
++
++boolean
++phydm_check_rates(void *dm_void, u8 rate_idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 check_rate_bitmap0 = 0x08080808; /* @check CCK11M, OFDM54M, MCS7, MCS15*/
++	u32 check_rate_bitmap1 = 0x80200808; /* @check MCS23, MCS31, VHT1SS M9, VHT2SS M9*/
++	u32 check_rate_bitmap2 = 0x00080200; /* @check VHT3SS M9, VHT4SS M9*/
++	u32 bitmap_result;
++
++#if (RTL8822B_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8822B) {
++		check_rate_bitmap2 &= 0;
++		check_rate_bitmap1 &= 0xfffff000;
++		check_rate_bitmap0 &= 0x0fffffff;
++	}
++#endif
++#if (RTL8197F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8197F) {
++		check_rate_bitmap2 &= 0;
++		check_rate_bitmap1 &= 0;
++		check_rate_bitmap0 &= 0x0fffffff;
++	}
++#endif
++#if (RTL8192E_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8192E) {
++		check_rate_bitmap2 &= 0;
++		check_rate_bitmap1 &= 0;
++		check_rate_bitmap0 &= 0x0fffffff;
++	}
++#endif
++#if (RTL8192F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8192F) {
++		check_rate_bitmap2 &= 0;
++		check_rate_bitmap1 &= 0;
++		check_rate_bitmap0 &= 0x0fffffff;
++	}
++#endif
++#if (RTL8721D_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8721D) {
++		check_rate_bitmap2 &= 0;
++		check_rate_bitmap1 &= 0;
++		check_rate_bitmap0 &= 0x000fffff;
++	}
++#endif
++#if (RTL8821C_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8821C) {
++		check_rate_bitmap2 &= 0;
++		check_rate_bitmap1 &= 0x003ff000;
++		check_rate_bitmap0 &= 0x000fffff;
++	}
++#endif
++	if (rate_idx >= 64)
++		bitmap_result = BIT(rate_idx - 64) & check_rate_bitmap2;
++	else if (rate_idx >= 32)
++		bitmap_result = BIT(rate_idx - 32) & check_rate_bitmap1;
++	else if (rate_idx <= 31)
++		bitmap_result = BIT(rate_idx) & check_rate_bitmap0;
++
++	if (bitmap_result != 0)
++		return true;
++	else
++		return false;
++}
++
++enum rf_path
++phydm_check_paths(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	enum rf_path max_path = RF_PATH_A;
++
++	if (dm->num_rf_path == 1)
++		max_path = RF_PATH_A;
++	if (dm->num_rf_path == 2)
++		max_path = RF_PATH_B;
++	if (dm->num_rf_path == 3)
++		max_path = RF_PATH_C;
++	if (dm->num_rf_path == 4)
++		max_path = RF_PATH_D;
++
++	return max_path;
++}
++
++#ifndef PHYDM_COMMON_API_SUPPORT
++u8 phydm_dtp_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 ret = 0xff;
++
++#if (RTL8192E_SUPPORT)
++	ret = config_phydm_read_txagc_n(dm, path, hw_rate);
++#endif
++	return ret;
++}
++#endif
++
++u8 phydm_search_min_power_index(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	enum rf_path path;
++	enum rf_path max_path;
++	u8 min_gain_index = 0x3f;
++	u8 gain_index;
++	u8 rate_idx;
++
++	PHYDM_DBG(dm, DBG_DYN_TXPWR, "%s\n", __func__);
++	max_path = phydm_check_paths(dm);
++	for (path = 0; path <= max_path; path++)
++		for (rate_idx = 0; rate_idx < 84; rate_idx++)
++			if (phydm_check_rates(dm, rate_idx)) {
++#ifdef PHYDM_COMMON_API_SUPPORT
++				/*This is for API support IC : 97F,8822B,92F,8821C*/
++				gain_index = phydm_api_get_txagc(dm, path, rate_idx);
++#else
++				/*This is for API non-support IC : 92E */
++				gain_index = phydm_dtp_get_txagc(dm, path, rate_idx);
++#endif
++				if (gain_index == 0xff) {
++					min_gain_index = 0x20;
++					PHYDM_DBG(dm, DBG_DYN_TXPWR, 
++						  "Error Gain idx!! Rewite to: ((%d))\n",
++						  min_gain_index);
++					break;
++				}
++				PHYDM_DBG(dm, DBG_DYN_TXPWR,
++					  "Support Rate: ((%d)) -> Gain idx: ((%d))\n",
++					  rate_idx, gain_index);
++				if (gain_index < min_gain_index)
++					min_gain_index = gain_index;
++			}
++	return min_gain_index;
++}
++
++void phydm_dynamic_tx_power_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i = 0;
++
++	dm->last_dtp_lvl = tx_high_pwr_level_normal;
++	dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
++
++	switch (dm->ic_ip_series) {
++	#ifdef BB_RAM_SUPPORT
++	case PHYDM_IC_JGR3:
++		dm->set_pwr_th[0] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL1;
++		dm->set_pwr_th[1] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL2;
++		dm->set_pwr_th[2] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL3;
++		phydm_dtp_init_2nd(dm);
++		break;
++	#endif
++	default:
++		for (i = 0; i < 3; i++)
++			dm->enhance_pwr_th[i] = 0xff;
++
++		dm->set_pwr_th[0] = TX_POWER_NEAR_FIELD_THRESH_LVL1;
++		dm->set_pwr_th[1] = TX_POWER_NEAR_FIELD_THRESH_LVL2;
++		dm->set_pwr_th[2] = 0xff;
++		dm->min_power_index = phydm_search_min_power_index(dm);
++		PHYDM_DBG(dm, DBG_DYN_TXPWR, "DTP init: Min Gain idx: ((%d))\n",
++			  dm->min_power_index);
++		break;
++	}
++}
++
++void phydm_noisy_enhance_hp_th(void *dm_void, u8 noisy_state)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (noisy_state == 0) {
++		dm->enhance_pwr_th[0] = dm->set_pwr_th[0];
++		dm->enhance_pwr_th[1] = dm->set_pwr_th[1];
++		dm->enhance_pwr_th[2] = dm->set_pwr_th[2];
++	} else {
++		dm->enhance_pwr_th[0] = dm->set_pwr_th[0] + 8;
++		dm->enhance_pwr_th[1] = dm->set_pwr_th[1] + 5;
++		dm->enhance_pwr_th[2] = dm->set_pwr_th[2];
++	}
++	PHYDM_DBG(dm, DBG_DYN_TXPWR,
++		  "DTP hp_enhance_th: Lv1_th =%d ,Lv2_th = %d ,Lv3_th = %d\n",
++		  dm->enhance_pwr_th[0], dm->enhance_pwr_th[1],
++		  dm->enhance_pwr_th[2]);
++}
++
++u8 phydm_pwr_lvl_check(void *dm_void, u8 input_rssi, u8 last_pwr_lv)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 th[DTP_POWER_LEVEL_SIZE];
++	u8 i;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++)
++			th[i] = dm->set_pwr_th[i];
++
++		PHYDM_DBG(dm, DBG_DYN_TXPWR,
++			  "Ori-DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n",
++			  th[0], th[1], th[2]);
++
++		for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++) {
++			if (i >= (last_pwr_lv))
++				th[i] += DTP_FLOOR_UP_GAP;
++		}
++
++		PHYDM_DBG(dm, DBG_DYN_TXPWR,
++			  "Mod-DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n",
++			  th[0], th[1], th[2]);
++	} else {
++		for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++)
++			th[i] = dm->enhance_pwr_th[i];
++		for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++) {
++			if (i >= (last_pwr_lv))
++				th[i] += DTP_FLOOR_UP_GAP;
++		}
++	}
++
++	if (input_rssi >= th[2])
++		return tx_high_pwr_level_level3;
++	else if (input_rssi < th[2] && input_rssi >= th[1])
++		return tx_high_pwr_level_level2;
++	else if (input_rssi < th[1] && input_rssi >= th[0])
++		return tx_high_pwr_level_level1;
++	else
++		return tx_high_pwr_level_normal;
++}
++
++u8 phydm_pwr_lv_mapping(u8 tx_pwr_lv)
++{
++	if (tx_pwr_lv == tx_high_pwr_level_level3)
++		return PHYDM_OFFSET_MINUS_11DB;
++	else if (tx_pwr_lv == tx_high_pwr_level_level2)
++		return PHYDM_OFFSET_MINUS_7DB;
++	else if (tx_pwr_lv == tx_high_pwr_level_level1)
++		return PHYDM_OFFSET_MINUS_3DB;
++	else
++		return PHYDM_OFFSET_ZERO;
++}
++
++void phydm_dynamic_response_power(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 rpwr = 0;
++
++	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
++		return;
++
++	if (dm->dynamic_tx_high_power_lvl == dm->last_dtp_lvl) {
++		PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr not change\n");
++		return;
++	}
++	PHYDM_DBG(dm, DBG_DYN_TXPWR,
++		  "RespPwr update_DTP_lv: ((%d)) -> ((%d))\n", dm->last_dtp_lvl,
++		  dm->dynamic_tx_high_power_lvl);
++	dm->last_dtp_lvl = dm->dynamic_tx_high_power_lvl;
++	rpwr = phydm_pwr_lv_mapping(dm->dynamic_tx_high_power_lvl);
++	odm_set_mac_reg(dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT(19) | BIT(18),
++			rpwr);
++	PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr Set TxPwr: Lv (%d)\n",
++		  dm->dynamic_tx_high_power_lvl);
++}
++
++void phydm_dtp_fill_cmninfo(void *dm_void, u8 sta_id, u8 dtp_lvl)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id];
++	struct dtp_info *dtp = NULL;
++
++	if (!is_sta_active(sta))
++		return;
++
++	dtp = &sta->dtp_stat;
++	dtp->dyn_tx_power = phydm_pwr_lv_mapping(dtp_lvl);
++	PHYDM_DBG(dm, DBG_DYN_TXPWR,
++		  "Fill cmninfo TxPwr: sta_id=(%d), macid=(%d), PwrLv (%d)\n",
++		  sta_id, sta->mac_id, dtp->dyn_tx_power);
++}
++
++void phydm_dtp_per_sta(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *sta = NULL;
++	struct dtp_info *dtp = NULL;
++	struct rssi_info *rssi = NULL;
++	u8 sta_cnt = 0;
++	u8 i = 0;
++	u8 curr_pwr_lv = 0;
++	u8 last_pwr_lv = 0;
++
++	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
++		sta = dm->phydm_sta_info[i];
++		if (is_sta_active(sta)) {
++			sta_cnt++;
++
++			dtp = &sta->dtp_stat;
++			rssi = &sta->rssi_stat;
++			last_pwr_lv = dtp->sta_last_dtp_lvl;
++			curr_pwr_lv = phydm_pwr_lvl_check(dm, rssi->rssi,
++							  last_pwr_lv);
++			dtp->sta_tx_high_power_lvl = curr_pwr_lv;
++			PHYDM_DBG(dm, DBG_DYN_TXPWR,
++				  "STA_id=%d, MACID=%d , RSSI: %d , GetPwrLv: %d\n",
++				  i, sta->mac_id, rssi->rssi, curr_pwr_lv);
++
++			if (curr_pwr_lv == last_pwr_lv) {
++				dtp->sta_tx_high_power_lvl = last_pwr_lv;
++				PHYDM_DBG(dm, DBG_DYN_TXPWR,
++					  "DTP_lv not change: ((%d))\n",
++					  curr_pwr_lv);
++				return;
++			}
++
++			PHYDM_DBG(dm, DBG_DYN_TXPWR,
++				  "DTP_lv update: ((%d)) -> ((%d))\n",
++				  last_pwr_lv, curr_pwr_lv);
++
++			dtp->sta_last_dtp_lvl = curr_pwr_lv;
++
++			switch (dm->ic_ip_series) {
++			#ifdef BB_RAM_SUPPORT
++			case PHYDM_IC_JGR3:
++				phydm_dtp_fill_cmninfo_2nd(dm, i, curr_pwr_lv);
++				break;
++			#endif
++			default:
++				phydm_dtp_fill_cmninfo(dm, i, curr_pwr_lv);
++				break;
++			}
++
++			if (sta_cnt == dm->number_linked_client)
++				break;
++		}
++	}
++}
++
++void odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 sta_id)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id];
++	struct dtp_info *dtp = NULL;
++
++	if (!is_sta_active(sta))
++		return;
++	dtp = &sta->dtp_stat;
++
++	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
++		return;
++
++	if (dm->fill_desc_dyntxpwr)
++		dm->fill_desc_dyntxpwr(dm, desc, dtp->dyn_tx_power);
++	else
++		PHYDM_DBG(dm, DBG_DYN_TXPWR,
++			  "%s: fill_desc_dyntxpwr is null!\n", __func__);
++
++	if (dtp->last_tx_power != dtp->dyn_tx_power) {
++		PHYDM_DBG(dm, DBG_DYN_TXPWR,
++			  "%s: last_offset=%d, txpwr_offset=%d\n", __func__,
++			  dtp->last_tx_power, dtp->dyn_tx_power);
++		dtp->last_tx_power = dtp->dyn_tx_power;
++	}
++}
++
++void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output,
++			     u32 *_out_len)
++{
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	char help[] = "-h";
++	u32 var1[7] = {0};
++	u8 set_pwr_th1, set_pwr_th2, set_pwr_th3;
++	u8 i = 0;
++	#ifdef BB_RAM_SUPPORT
++	s8 pwr_ofst_tmp = 0x0;
++	#endif
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Set DTP threhosld: {1} {Lv1_th} {Lv2_th} {Lv3_th}\n");
++		#ifdef BB_RAM_SUPPORT
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Set pwr_tx_offset: {2} {0:reg 1:macid} {en} {offset 0/1} {0:-, 1:+} {Pwr Offset} {macid}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Read pwr_tx_offset : {3} {0:reg 1:macid} {macid(0~63), 255:all}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Reset all ram pwr_tx_offset : {4}\n");
++		#endif
++	} else {
++		for (i = 0; i < 7; i++) {
++			if (input[i + 1])
++				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
++					     &var1[i]);
++		}
++		switch (var1[0]) {
++		case 1:
++			for (i = 0; i < 3; i++) {
++				if (var1[i] == 0 || var1[i] > 100)
++					dm->set_pwr_th[i] = 0xff;
++				else
++					dm->set_pwr_th[i] = (u8)var1[1 + i];
++			}
++
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "DTP_TH[0:2] = {%d, %d, %d}\n",
++				 dm->set_pwr_th[0], dm->set_pwr_th[1],
++				 dm->set_pwr_th[2]);
++			break;
++		#ifdef BB_RAM_SUPPORT
++		case 2:
++			if ((boolean)var1[4])
++				pwr_ofst_tmp = (s8)var1[5];
++			else
++				pwr_ofst_tmp = 0x0 - (s8)var1[5];
++
++			if ((boolean)var1[1])
++				phydm_wt_ram_pwr(dm, (u8)var1[6],
++						 (boolean)var1[3],
++						 (boolean)var1[2],
++						 pwr_ofst_tmp);
++			else
++				phydm_wt_reg_pwr(dm, (boolean)var1[3],
++						 (boolean)var1[2],
++						 pwr_ofst_tmp);
++			break;
++		case 3:
++			if ((boolean)var1[1]) {
++				if ((u8)var1[2] == 0xff)
++					for (i = 0; i < 64; i++)
++						phydm_rd_ram_pwr(dm, i, &used,
++								 output,
++								 &out_len);
++				else
++					phydm_rd_ram_pwr(dm, (u8)var1[2], &used,
++							 output, &out_len);
++			} else {
++				phydm_rd_reg_pwr(dm, &used, output, &out_len);
++			}
++			break;
++		case 4:
++			phydm_rst_ram_pwr(dm);
++			break;
++		#endif
++		}
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_dynamic_tx_power(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *sta = NULL;
++	u8 i = 0;
++
++	u8 rssi_min = dm->rssi_min;
++	u8 rssi_tmp = 0;
++
++	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
++		return;
++
++	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) {
++		PHYDM_DBG(dm, DBG_DYN_TXPWR,
++			  "[%s] RSSI_min = %d, Noisy_dec = %d\n", __func__,
++			  rssi_min, dm->noisy_decision);
++		phydm_noisy_enhance_hp_th(dm, dm->noisy_decision);
++		/* Response Power */
++		dm->dynamic_tx_high_power_lvl = phydm_pwr_lvl_check(dm,
++								    rssi_min,
++							    dm->last_dtp_lvl);
++		phydm_dynamic_response_power(dm);
++	}
++	/* Per STA Tx power */
++	phydm_dtp_per_sta(dm);
++}
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++
++void phydm_dynamic_tx_power_init_win(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	void *adapter = dm->adapter;
++	PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
++
++	mgnt_info->bDynamicTxPowerEnable = false;
++	#if DEV_BUS_TYPE == RT_USB_INTERFACE
++	if (RT_GetInterfaceSelection((PADAPTER)adapter) ==
++	    INTF_SEL1_USB_High_Power) {
++		mgnt_info->bDynamicTxPowerEnable = true;
++	}
++	#endif
++
++	hal_data->LastDTPLvl = tx_high_pwr_level_normal;
++	hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
++
++	PHYDM_DBG(dm, DBG_DYN_TXPWR, "[%s] DTP=%d\n", __func__,
++		  mgnt_info->bDynamicTxPowerEnable);
++}
++
++void phydm_dynamic_tx_power_win(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
++		return;
++
++	#if (RTL8814A_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8814A)
++		odm_dynamic_tx_power_8814a(dm);
++	#endif
++
++	#if (RTL8821A_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8821) {
++		void *adapter = dm->adapter;
++		PMGNT_INFO mgnt_info = GetDefaultMgntInfo((PADAPTER)adapter);
++
++		if (mgnt_info->RegRspPwr == 1) {
++			if (dm->rssi_min > 60) {
++				/*Resp TXAGC offset = -3dB*/
++				odm_set_mac_reg(dm, R_0x6d8, 0x1C0000, 1);
++			} else if (dm->rssi_min < 55) {
++				/*Resp TXAGC offset = 0dB*/
++				odm_set_mac_reg(dm, R_0x6d8, 0x1C0000, 0);
++			}
++		}
++	}
++	#endif
++}
++#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
++#endif /* @#ifdef CONFIG_DYNAMIC_TX_TWR */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dynamictxpower.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dynamictxpower.h
+new file mode 100644
+index 000000000..9f0bde01b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_dynamictxpower.h
+@@ -0,0 +1,142 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDMDYNAMICTXPOWER_H__
++#define __PHYDMDYNAMICTXPOWER_H__
++
++#ifdef CONFIG_DYNAMIC_TX_TWR
++/* @============================================================
++ *  Definition
++ * ============================================================
++ */
++
++/* 2019.6.14, Modify per sta API to fix the AP problem of early return*/
++#define DYNAMIC_TXPWR_VERSION "2.1"
++
++#define DTP_POWER_LEVEL_SIZE 3
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
++#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
++#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
++#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
++#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
++#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 80
++#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 63
++#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 55
++#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 90
++#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 85
++#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 80
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 90
++#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 85
++#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 80
++#endif
++
++#define tx_high_pwr_level_normal 0
++#define tx_high_pwr_level_level1 1
++#define tx_high_pwr_level_level2 2
++#define tx_high_pwr_level_level3 3
++#define tx_high_pwr_level_unchange 4
++#define DTP_FLOOR_UP_GAP 3
++
++/* @============================================================
++ * enumrate
++ * ============================================================
++ */
++enum phydm_dtp_power_offset {
++	PHYDM_OFFSET_ZERO = 0,
++	PHYDM_OFFSET_MINUS_3DB = 1,
++	PHYDM_OFFSET_MINUS_7DB = 2,
++	PHYDM_OFFSET_MINUS_11DB = 3,
++	PHYDM_OFFSET_ADD_3DB = 4,
++	PHYDM_OFFSET_ADD_6DB = 5
++};
++
++enum phydm_dtp_power_offset_2nd {
++	PHYDM_2ND_OFFSET_ZERO = 0,
++	PHYDM_2ND_OFFSET_MINUS_3DB = 1,
++	PHYDM_2ND_OFFSET_MINUS_7DB = 2,
++	PHYDM_2ND_OFFSET_MINUS_11DB = 3
++};
++
++enum phydm_dtp_power_offset_bbram {
++	/*@ HW min use 1dB*/
++	PHYDM_BBRAM_OFFSET_ZERO = 0,
++	PHYDM_BBRAM_OFFSET_MINUS_3DB = -3,
++	PHYDM_BBRAM_OFFSET_MINUS_7DB = -7,
++	PHYDM_BBRAM_OFFSET_MINUS_11DB = -11
++};
++
++enum phydm_dtp_power_pkt_type {
++	RAM_PWR_OFST0		= 0,
++	RAM_PWR_OFST1		= 1,
++	REG_PWR_OFST0		= 2,
++	REG_PWR_OFST1		= 3
++};
++
++/* @============================================================
++ *  structure
++ * ============================================================
++ */
++
++/* @============================================================
++ *  Function Prototype
++ * ============================================================
++ */
++
++extern void
++odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 mac_id);
++
++void phydm_dynamic_tx_power(void *dm_void);
++
++void phydm_dynamic_tx_power_init(void *dm_void);
++
++void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output,
++			     u32 *_out_len);
++
++void phydm_rd_reg_pwr(void *dm_void, u32 *_used, char *output, u32 *_out_len);
++
++void phydm_wt_reg_pwr(void *dm_void, boolean is_ofst1, boolean pwr_ofst_en,
++            		     s8 pwr_ofst);
++
++void phydm_wt_ram_pwr(void *dm_void, u8 macid, boolean is_ofst1, 
++		             boolean pwr_ofst_en, s8 pwr_ofst);
++
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void odm_dynamic_tx_power_win(void *dm_void);
++#endif
++
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features.h
+new file mode 100644
+index 000000000..29ffea51e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features.h
+@@ -0,0 +1,80 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_FEATURES_H__
++#define __PHYDM_FEATURES_H__
++
++#define CONFIG_RUN_IN_DRV
++#define ODM_DC_CANCELLATION_SUPPORT		(ODM_RTL8188F | \
++						 ODM_RTL8710B | \
++						 ODM_RTL8192F | \
++						 ODM_RTL8821C | \
++						 ODM_RTL8822B | \
++						 ODM_RTL8721D | \
++						 ODM_RTL8723D | \
++						 ODM_RTL8710C)
++#define ODM_RECEIVER_BLOCKING_SUPPORT	(ODM_RTL8188E | ODM_RTL8192E)
++#define ODM_DYM_BW_INDICATION_SUPPORT	(ODM_RTL8821C | \
++					 ODM_RTL8822B | \
++					 ODM_RTL8822C)
++
++/*@20170103 YuChen add for FW API*/
++#define PHYDM_FW_API_ENABLE_8822B		1
++#define PHYDM_FW_API_FUNC_ENABLE_8822B		1
++#define PHYDM_FW_API_ENABLE_8821C		1
++#define PHYDM_FW_API_FUNC_ENABLE_8821C		1
++#define PHYDM_FW_API_ENABLE_8195B		1
++#define PHYDM_FW_API_FUNC_ENABLE_8195B		1
++#define PHYDM_FW_API_ENABLE_8198F		1
++#define PHYDM_FW_API_FUNC_ENABLE_8198F		1
++#define PHYDM_FW_API_ENABLE_8822C 1
++#define PHYDM_FW_API_FUNC_ENABLE_8822C 1
++#define PHYDM_FW_API_ENABLE_8814B 1
++#define PHYDM_FW_API_FUNC_ENABLE_8814B 1
++#define PHYDM_FW_API_ENABLE_8812F 1
++#define PHYDM_FW_API_FUNC_ENABLE_8812F 1
++#define PHYDM_FW_API_ENABLE_8197G 1
++#define PHYDM_FW_API_FUNC_ENABLE_8197G 1
++
++#define CONFIG_POWERSAVING 0
++
++#ifdef BEAMFORMING_SUPPORT
++#if (BEAMFORMING_SUPPORT)
++	#define PHYDM_BEAMFORMING_SUPPORT
++#endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	#include	"phydm_features_win.h"
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	#include	"phydm_features_ce.h"
++	/*@#include	"phydm_features_ce2_kernel.h"*/
++#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	#include	"phydm_features_ap.h"
++#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
++	#include	"phydm_features_iot.h"
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features_ap.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features_ap.h
+new file mode 100644
+index 000000000..3bd27b0f9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features_ap.h
+@@ -0,0 +1,218 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef	__PHYDM_FEATURES_AP_H__
++#define __PHYDM_FEATURES_AP_H__
++
++#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
++	RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
++	RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\
++	RTL8197G_SUPPORT)
++	#define PHYDM_LA_MODE_SUPPORT			1
++#else
++	#define PHYDM_LA_MODE_SUPPORT			0
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
++	RTL8192F_SUPPORT)
++	#define DYN_ANT_WEIGHTING_SUPPORT
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
++	#define FAHM_SUPPORT
++#endif
++	#define NHM_SUPPORT
++	#define CLM_SUPPORT
++
++#if (RTL8812F_SUPPORT)
++	/*#define PHYDM_PHYSTAUS_AUTO_SWITCH*/
++#endif
++
++#if (RTL8197F_SUPPORT)
++	/*#define PHYDM_TDMA_DIG_SUPPORT*/
++#endif
++
++#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\
++	RTL8197G_SUPPORT)
++	#define PHYDM_TDMA_DIG_SUPPORT 1
++	#ifdef PHYDM_TDMA_DIG_SUPPORT
++	#define IS_USE_NEW_TDMA /*new tdma dig test*/
++	#endif
++#endif
++
++#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT ||\
++	RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)
++	#define PHYDM_LNA_SAT_CHK_SUPPORT
++	#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++
++		#if (RTL8197F_SUPPORT)
++		/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
++		#endif
++
++		#if (RTL8822B_SUPPORT)
++		/*#define PHYDM_LNA_SAT_CHK_TYPE2*/
++		#endif
++
++		#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)
++		#define PHYDM_LNA_SAT_CHK_TYPE1
++		#endif
++	#endif
++#endif
++
++#if (RTL8822B_SUPPORT)
++	/*#define PHYDM_POWER_TRAINING_SUPPORT*/
++#endif
++
++#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
++	RTL8812F_SUPPORT || RTL8197G_SUPPORT)
++	#define PHYDM_PMAC_TX_SETTING_SUPPORT
++#endif
++
++#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
++	RTL8812F_SUPPORT || RTL8197G_SUPPORT)
++	#define PHYDM_MP_SUPPORT
++#endif
++
++#if (RTL8822B_SUPPORT)
++	#define PHYDM_TXA_CALIBRATION
++#endif
++
++#if (RTL8188E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
++	#define	PHYDM_PRIMARY_CCA
++#endif
++
++#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
++	RTL8822B_SUPPORT || RTL8192F_SUPPORT)
++	#define	PHYDM_DC_CANCELLATION
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
++	#define	CONFIG_ADAPTIVE_SOML
++#endif
++
++#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
++	RTL8192E_SUPPORT || RTL8723B_SUPPORT)
++	/*#define	CONFIG_RA_FW_DBG_CODE*/
++#endif
++
++#if (RTL8192F_SUPPORT == 1)
++	/*#define	CONFIG_8912F_SPUR_CALIBRATION*/
++#endif
++
++#if (RTL8822B_SUPPORT == 1)
++	/* #define	CONFIG_8822B_SPUR_CALIBRATION */
++#endif
++
++#if (RTL8197G_SUPPORT)
++	#define CONFIG_DIRECTIONAL_BF
++#endif
++
++#if (RTL8197G_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT)
++	#define CONFIG_DYNAMIC_TX_TWR
++#endif
++
++#if (RTL8197G_SUPPORT)
++	#define CONFIG_DYNAMIC_TXCOLLISION_TH
++#endif
++
++/*#define	CONFIG_PSD_TOOL*/
++#define PHYDM_SUPPORT_CCKPD
++#define PHYDM_SUPPORT_ADAPTIVITY
++/*#define	CONFIG_PATH_DIVERSITY*/
++/*#define	CONFIG_RA_DYNAMIC_RTY_LIMIT*/
++/*#define	CONFIG_RA_DYNAMIC_RATE_ID*/
++#define	CONFIG_BB_TXBF_API
++/*#define	ODM_CONFIG_BT_COEXIST*/
++#define	PHYDM_SUPPORT_RSSI_MONITOR
++#if !defined(CONFIG_DISABLE_PHYDM_DEBUG_FUNCTION)
++	#define CONFIG_PHYDM_DEBUG_FUNCTION
++#endif
++
++/* [ Configure Antenna Diversity ] */
++#if (RTL8188F_SUPPORT)
++	#ifdef CONFIG_ANTENNA_DIVERSITY
++		#define CONFIG_PHYDM_ANTENNA_DIVERSITY
++		#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++	#endif
++#endif
++
++#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) || defined(CONFIG_RTL_8197F_ANT_SWITCH) || defined(CONFIG_RTL_8197G_ANT_SWITCH)
++	#define CONFIG_PHYDM_ANTENNA_DIVERSITY
++	#define ODM_EVM_ENHANCE_ANTDIV
++	/*#define SKIP_EVM_ANTDIV_TRAINING_PATCH*/
++
++	/*----------*/
++	#ifdef CONFIG_NO_2G_DIVERSITY_8197F
++		#define CONFIG_NO_2G_DIVERSITY
++	#elif defined(CONFIG_2G_CGCS_RX_DIVERSITY_8197F)
++		#define CONFIG_2G_CGCS_RX_DIVERSITY
++	#elif defined(CONFIG_2G_CG_TRX_DIVERSITY_8197F)
++		#define CONFIG_2G_CG_TRX_DIVERSITY
++	#endif
++
++	/*----------*/
++	#ifdef CONFIG_NO_2G_DIVERSITY_8197G
++		#define CONFIG_NO_2G_DIVERSITY
++	#elif defined(CONFIG_2G_CGCS_RX_DIVERSITY_8197G)
++		#define CONFIG_2G_CGCS_RX_DIVERSITY
++	#elif defined(CONFIG_2G_CG_TRX_DIVERSITY_8197G)
++		#define CONFIG_2G_CG_TRX_DIVERSITY
++	#endif
++
++	#if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++		#define CONFIG_NO_2G_DIVERSITY
++	#endif
++
++	#ifdef CONFIG_NO_5G_DIVERSITY_8881A
++		#define CONFIG_NO_5G_DIVERSITY
++	#elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A)
++		#define CONFIG_5G_CGCS_RX_DIVERSITY
++	#elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A)
++		#define CONFIG_5G_CG_TRX_DIVERSITY
++	#elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)
++		#define CONFIG_2G5G_CG_TRX_DIVERSITY
++	#endif
++	#if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
++		#define CONFIG_NO_5G_DIVERSITY
++	#endif
++	/*----------*/
++	#if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))
++		#define CONFIG_NOT_SUPPORT_ANTDIV
++	#elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))
++		#define CONFIG_2G_SUPPORT_ANTDIV
++	#elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY))
++		#define CONFIG_5G_SUPPORT_ANTDIV
++	#elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY))
++			#define CONFIG_2G5G_SUPPORT_ANTDIV
++	#endif
++		/*----------*/
++#endif /*Antenna Diveristy*/
++
++/*[SmartAntenna]*/
++/*#define	CONFIG_SMART_ANTENNA*/
++#ifdef CONFIG_SMART_ANTENNA
++	/*#define	CONFIG_CUMITEK_SMART_ANTENNA*/
++#endif
++#define CFG_DIG_DAMPING_CHK
++/* --------------------------------------------------*/
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++	#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
++	     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
++	     RTL8814B_SUPPORT || RTL8812F_SUPPORT)
++		#define	DRIVER_BEAMFORMING_VERSION2
++	#endif
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features_ce.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features_ce.h
+new file mode 100644
+index 000000000..8a2638dca
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features_ce.h
+@@ -0,0 +1,232 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_FEATURES_CE_H__
++#define __PHYDM_FEATURES_CE_H__
++
++#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
++	RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
++	RTL8822C_SUPPORT)
++	#define PHYDM_LA_MODE_SUPPORT			1
++#else
++	#define PHYDM_LA_MODE_SUPPORT			0
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
++	RTL8192F_SUPPORT)
++	#define DYN_ANT_WEIGHTING_SUPPORT
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
++	#define FAHM_SUPPORT
++#endif
++	#define NHM_SUPPORT
++	#define CLM_SUPPORT
++
++#if (RTL8822C_SUPPORT)
++	#define NHM_DYM_PW_TH_SUPPORT
++#endif
++
++#if (RTL8822C_SUPPORT)
++	/*@#define PHYDM_PHYSTAUS_AUTO_SWITCH*/
++#endif
++
++/*@#define PHYDM_TDMA_DIG_SUPPORT*/
++
++#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8821C_SUPPORT ||\
++	RTL8822C_SUPPORT || RTL8723D_SUPPORT)
++	#ifdef CONFIG_TDMADIG
++	#define PHYDM_TDMA_DIG_SUPPORT
++	#ifdef PHYDM_TDMA_DIG_SUPPORT
++	#define IS_USE_NEW_TDMA /*new tdma dig test*/
++	#endif
++	#endif
++#endif
++
++#if (RTL8814B_SUPPORT)
++	/*@#define PHYDM_TDMA_DIG_SUPPORT*/
++	#ifdef PHYDM_TDMA_DIG_SUPPORT
++	/*@#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/
++	#endif
++#endif
++
++#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8814B_SUPPORT)
++	/*@#define PHYDM_LNA_SAT_CHK_SUPPORT*/
++	#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++
++		#if (RTL8197F_SUPPORT)
++		/*@#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
++		#endif
++
++		#if (RTL8822B_SUPPORT)
++		/*@#define PHYDM_LNA_SAT_CHK_TYPE2*/
++		#endif
++
++		#if (RTL8814B_SUPPORT)
++		/*@#define PHYDM_LNA_SAT_CHK_TYPE1*/
++		#endif
++	#endif
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT)
++	#define PHYDM_POWER_TRAINING_SUPPORT
++#endif
++
++#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT)
++	#define PHYDM_PMAC_TX_SETTING_SUPPORT
++#endif
++
++#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT)
++	#define PHYDM_MP_SUPPORT
++#endif
++
++#if (RTL8822C_SUPPORT)
++	#define	PHYDM_CCK_RX_PATHDIV_SUPPORT
++#endif
++
++#if (RTL8822B_SUPPORT)
++	#define PHYDM_TXA_CALIBRATION
++#endif
++
++#if (RTL8188E_SUPPORT)
++	#define	PHYDM_PRIMARY_CCA
++#endif
++
++#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
++	RTL8822B_SUPPORT || RTL8192F_SUPPORT)
++	#define	PHYDM_DC_CANCELLATION
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
++	#define	CONFIG_ADAPTIVE_SOML
++#endif
++
++#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
++	#define	CONFIG_RECEIVER_BLOCKING
++#endif
++
++#if (RTL8192F_SUPPORT)
++	/*#define	CONFIG_8912F_SPUR_CALIBRATION*/
++#endif
++
++#if (RTL8822B_SUPPORT)
++	#define	CONFIG_8822B_SPUR_CALIBRATION
++#endif
++
++#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
++#define CONFIG_DYNAMIC_TX_TWR
++#endif
++#if (RTL8822C_SUPPORT)
++#define PHYDM_HW_IGI
++#endif
++#define PHYDM_SUPPORT_CCKPD
++#define PHYDM_SUPPORT_ADAPTIVITY
++
++/*@Antenna Diversity*/
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	#define CONFIG_PHYDM_ANTENNA_DIVERSITY
++
++	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++
++		#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\
++		     RTL8188F_SUPPORT || RTL8821C_SUPPORT ||\
++		     RTL8723D_SUPPORT)
++			#define	CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++		#endif
++
++		#if (RTL8821A_SUPPORT)
++			/*@#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
++		#endif
++
++		#if (RTL8822B_SUPPORT)
++			/*@#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
++		#endif
++
++	#endif
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT || RTL8192F_SUPPORT)
++	#define CONFIG_PATH_DIVERSITY
++#endif
++
++/*@[SmartAntenna]*/
++/*@#define	CONFIG_SMART_ANTENNA*/
++#ifdef CONFIG_SMART_ANTENNA
++	/*@#define	CONFIG_CUMITEK_SMART_ANTENNA*/
++#endif
++/* @--------------------------------------------------*/
++
++#ifdef CONFIG_DFS_MASTER
++	#define CONFIG_PHYDM_DFS_MASTER
++#endif
++
++#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
++	RTL8192E_SUPPORT || RTL8723B_SUPPORT)
++	/*@#define	CONFIG_RA_FW_DBG_CODE*/
++#endif
++
++#define	CONFIG_PSD_TOOL
++/*@#define	CONFIG_ANT_DETECTION*/
++/*@#define	CONFIG_RA_DYNAMIC_RTY_LIMIT*/
++#define	CONFIG_BB_TXBF_API
++#define	CONFIG_PHYDM_DEBUG_FUNCTION
++
++#ifdef CONFIG_BT_COEXIST
++	#define	ODM_CONFIG_BT_COEXIST
++#endif
++#define	PHYDM_SUPPORT_RSSI_MONITOR
++#define	PHYDM_AUTO_DEGBUG
++#define CFG_DIG_DAMPING_CHK
++
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++	#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8192E_SUPPORT ||\
++	     RTL8814A_SUPPORT || RTL8881A_SUPPORT)
++		#define	PHYDM_BEAMFORMING_VERSION1
++	#endif
++	#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
++	     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
++	     RTL8822C_SUPPORT || RTL8814B_SUPPORT)
++		#define	DRIVER_BEAMFORMING_VERSION2
++	#endif
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT)
++	#ifdef CONFIG_MCC_MODE
++	#define	CONFIG_MCC_DM
++	#endif
++#endif
++
++#if (RTL8822B_SUPPORT)
++	#ifdef CONFIG_DYNAMIC_BYPASS_MODE
++	#define	CONFIG_DYNAMIC_BYPASS
++	#endif
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT)
++	#define CONFIG_DIRECTIONAL_BF
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features_ce2_kernel.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features_ce2_kernel.h
+new file mode 100644
+index 000000000..c206ea605
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features_ce2_kernel.h
+@@ -0,0 +1,84 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_FEATURES_CE_H__
++#define __PHYDM_FEATURES_CE_H__
++
++#define PHYDM_LA_MODE_SUPPORT			0
++
++#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
++	RTL8192F_SUPPORT)
++	#define DYN_ANT_WEIGHTING_SUPPORT
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
++	#define FAHM_SUPPORT
++#endif
++	#define NHM_SUPPORT
++	#define CLM_SUPPORT
++
++#if (RTL8822B_SUPPORT)
++	#define PHYDM_TXA_CALIBRATION
++#endif
++
++#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
++	RTL8822B_SUPPORT || RTL8192F_SUPPORT)
++	#define	PHYDM_DC_CANCELLATION
++#endif
++
++#if (RTL8192F_SUPPORT == 1)
++	/*#define	CONFIG_8912F_SPUR_CALIBRATION*/
++#endif
++
++#if (RTL8822B_SUPPORT == 1)
++	/* #define	CONFIG_8822B_SPUR_CALIBRATION */
++#endif
++
++#define PHYDM_SUPPORT_CCKPD
++#define PHYDM_SUPPORT_ADAPTIVITY
++
++#ifdef CONFIG_DFS_MASTER
++	#define CONFIG_PHYDM_DFS_MASTER
++#endif
++
++#define	CONFIG_BB_TXBF_API
++#define	CONFIG_PHYDM_DEBUG_FUNCTION
++
++#ifdef CONFIG_BT_COEXIST
++	#define	ODM_CONFIG_BT_COEXIST
++#endif
++#define	PHYDM_SUPPORT_RSSI_MONITOR
++#define CFG_DIG_DAMPING_CHK
++
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++	#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
++	     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
++	     RTL8822C_SUPPORT || RTL8814B_SUPPORT)
++		#define	DRIVER_BEAMFORMING_VERSION2
++	#endif
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features_iot.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features_iot.h
+new file mode 100644
+index 000000000..59afe7932
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features_iot.h
+@@ -0,0 +1,171 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef	__PHYDM_FEATURES_IOT_H__
++#define __PHYDM_FEATURES_IOT_H__
++
++#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
++	RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
++	RTL8822C_SUPPORT || RTL8195B_SUPPORT)
++	#define PHYDM_LA_MODE_SUPPORT			1
++#else
++	#define PHYDM_LA_MODE_SUPPORT			0
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
++	RTL8192F_SUPPORT)
++	#define DYN_ANT_WEIGHTING_SUPPORT
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
++	#define FAHM_SUPPORT
++#endif
++	#define NHM_SUPPORT
++	#define CLM_SUPPORT
++
++/*#define PHYDM_TDMA_DIG_SUPPORT*/
++
++#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT)
++	/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/
++	#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++		#if (RTL8197F_SUPPORT)
++		/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
++		#endif
++
++		#if (RTL8822B_SUPPORT)
++		/*#define PHYDM_LNA_SAT_CHK_TYPE2*/
++		#endif
++	#endif
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
++	#define PHYDM_POWER_TRAINING_SUPPORT
++#endif
++
++#if (RTL8822C_SUPPORT)
++	/* #define PHYDM_PMAC_TX_SETTING_SUPPORT */
++#endif
++
++#if (RTL8822C_SUPPORT)
++	/* #define PHYDM_MP_SUPPORT */
++#endif
++
++#if (RTL8822B_SUPPORT)
++	#define PHYDM_TXA_CALIBRATION
++#endif
++
++#if (RTL8188E_SUPPORT)
++	#define	PHYDM_PRIMARY_CCA
++#endif
++
++#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
++	RTL8822B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
++	#define	PHYDM_DC_CANCELLATION
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
++	#define	CONFIG_ADAPTIVE_SOML
++#endif
++
++#if (RTL8822B_SUPPORT)
++	/*#define	CONFIG_DYNAMIC_RX_PATH*/
++#endif
++
++#if (RTL8822B_SUPPORT == 1)
++	/* #define	CONFIG_8822B_SPUR_CALIBRATION */
++#endif
++
++#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
++	#define	CONFIG_RECEIVER_BLOCKING
++#endif
++
++#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
++#define CONFIG_DYNAMIC_TX_TWR
++#endif
++#define PHYDM_SUPPORT_CCKPD
++#define PHYDM_SUPPORT_ADAPTIVITY
++
++/*Antenna Diversity*/
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	#define CONFIG_PHYDM_ANTENNA_DIVERSITY
++
++	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++
++		#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\
++		     RTL8188F_SUPPORT || RTL8821C_SUPPORT)
++			#define	CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++		#endif
++
++		#if (RTL8821A_SUPPORT)
++			/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
++		#endif
++
++		#if (RTL8822B_SUPPORT)
++			/*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
++		#endif
++	#endif
++#endif
++
++/*[SmartAntenna]*/
++/*#define	CONFIG_SMART_ANTENNA*/
++#ifdef CONFIG_SMART_ANTENNA
++	/*#define	CONFIG_CUMITEK_SMART_ANTENNA*/
++#endif
++/* --------------------------------------------------*/
++
++#ifdef CONFIG_DFS_MASTER
++	#define CONFIG_PHYDM_DFS_MASTER
++#endif
++
++#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
++	RTL8192E_SUPPORT || RTL8723B_SUPPORT)
++	/*#define	CONFIG_RA_FW_DBG_CODE*/
++#endif
++
++#define	CONFIG_PSD_TOOL
++/*#define	CONFIG_RA_DBG_CMD*/
++/*#define	CONFIG_ANT_DETECTION*/
++/*#define	CONFIG_PATH_DIVERSITY*/
++/*#define	CONFIG_RA_DYNAMIC_RTY_LIMIT*/
++//#define	CONFIG_BB_TXBF_API
++#define	CONFIG_PHYDM_DEBUG_FUNCTION
++
++#ifdef CONFIG_BT_COEXIST
++	#define	ODM_CONFIG_BT_COEXIST
++#endif
++#define	PHYDM_SUPPORT_RSSI_MONITOR
++/*#define	PHYDM_AUTO_DEGBUG*/
++#define CFG_DIG_DAMPING_CHK
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++	#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
++	     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
++	     RTL8822C_SUPPORT || RTL8814B_SUPPORT)
++		#define	DRIVER_BEAMFORMING_VERSION2
++		#define	CONFIG_BB_TXBF_API
++	#endif
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features_win.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features_win.h
+new file mode 100644
+index 000000000..b6cd15014
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_features_win.h
+@@ -0,0 +1,210 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef	__PHYDM_FEATURES_WIN_H__
++#define __PHYDM_FEATURES_WIN_H__
++
++#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
++	RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
++	RTL8822C_SUPPORT || RTL8814B_SUPPORT)
++	#define PHYDM_LA_MODE_SUPPORT			1
++#else
++	#define PHYDM_LA_MODE_SUPPORT			0
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
++	RTL8192F_SUPPORT)
++	#define DYN_ANT_WEIGHTING_SUPPORT
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
++	#define FAHM_SUPPORT
++#endif
++	#define NHM_SUPPORT
++	#define CLM_SUPPORT
++
++#if (RTL8822C_SUPPORT)
++	#define NHM_DYM_PW_TH_SUPPORT
++#endif
++
++#if (RTL8822C_SUPPORT)
++	#define PHYDM_PHYSTAUS_AUTO_SWITCH
++#endif
++
++/*#define PHYDM_TDMA_DIG_SUPPORT*/
++
++#if (RTL8814B_SUPPORT)
++	/*#define PHYDM_TDMA_DIG_SUPPORT*/
++	#ifdef PHYDM_TDMA_DIG_SUPPORT
++	/*#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/
++	#endif
++#endif
++
++#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8814B_SUPPORT)
++	/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/
++	#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++
++		#if (RTL8197F_SUPPORT)
++		/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
++		#endif
++
++		#if (RTL8822B_SUPPORT)
++		/*#define PHYDM_LNA_SAT_CHK_TYPE2*/
++		#endif
++
++		#if (RTL8814B_SUPPORT)
++		/*#define PHYDM_LNA_SAT_CHK_TYPE1*/
++		#endif
++	#endif
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8710B_SUPPORT || RTL8723D_SUPPORT ||\
++	RTL8192F_SUPPORT)
++	#define	PHYDM_POWER_TRAINING_SUPPORT
++#endif
++
++#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT)
++	#define	PHYDM_PMAC_TX_SETTING_SUPPORT
++#endif
++
++#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT)
++	#define	PHYDM_MP_SUPPORT
++#endif
++
++#if (RTL8822C_SUPPORT)
++	#define	PHYDM_CCK_RX_PATHDIV_SUPPORT
++#endif
++
++#if (RTL8822B_SUPPORT)
++	#define	PHYDM_TXA_CALIBRATION
++#endif
++
++#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
++	#define	PHYDM_PRIMARY_CCA
++#endif
++
++#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
++	RTL8822B_SUPPORT || RTL8192F_SUPPORT)
++	#define	PHYDM_DC_CANCELLATION
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
++	#define	CONFIG_ADAPTIVE_SOML
++#endif
++
++#if (RTL8192F_SUPPORT)
++	#define	CONFIG_8912F_SPUR_CALIBRATION
++#endif
++
++/*Antenna Diversity*/
++#define	CONFIG_PHYDM_ANTENNA_DIVERSITY
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++
++	#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT || RTL8188F_SUPPORT ||\
++	     RTL8821C_SUPPORT || RTL8723D_SUPPORT)
++		#define	CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++	#endif
++
++	#if (RTL8822B_SUPPORT)
++		/*#define	ODM_EVM_ENHANCE_ANTDIV*/
++		/*#define	CONFIG_2T3R_ANTENNA*/
++		/*#define	CONFIG_2T4R_ANTENNA*/
++	#endif
++
++	/* --[SmtAnt]-----------------------------------------*/
++	#if (RTL8821A_SUPPORT)
++		/*#define	CONFIG_HL_SMART_ANTENNA_TYPE1*/
++		#define	CONFIG_FAT_PATCH
++	#endif
++	
++	#if (RTL8822B_SUPPORT)
++		/*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
++	#endif
++	
++	#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1) || defined(CONFIG_HL_SMART_ANTENNA_TYPE2))
++		#define	CONFIG_HL_SMART_ANTENNA
++	#endif
++
++	/* --------------------------------------------------*/
++
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT || RTL8192F_SUPPORT)
++	#define CONFIG_PATH_DIVERSITY
++#endif
++
++/*[SmartAntenna]*/
++#define	CONFIG_SMART_ANTENNA
++#ifdef CONFIG_SMART_ANTENNA
++	/*#define	CONFIG_CUMITEK_SMART_ANTENNA*/
++#endif
++	/* --------------------------------------------------*/
++
++#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
++	#define	CONFIG_RECEIVER_BLOCKING
++#endif
++
++#if (RTL8821C_SUPPORT || RTL8822C_SUPPORT || RTL8822B_SUPPORT)
++	#define CONFIG_BW_INDICATION
++#endif
++
++#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
++	RTL8192E_SUPPORT || RTL8723B_SUPPORT)
++	#define	CONFIG_RA_FW_DBG_CODE
++#endif
++
++/* #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR */
++#define CONFIG_DYNAMIC_TX_TWR
++/* #endif */
++#if (RTL8822C_SUPPORT)
++#define PHYDM_HW_IGI
++#endif
++#define	CONFIG_PSD_TOOL
++#define PHYDM_SUPPORT_ADAPTIVITY
++#define	PHYDM_SUPPORT_CCKPD
++#if (defined(PHYDM_SUPPORT_CCKPD) && RTL8822C_SUPPORT)
++	#define PHYDM_DCC_ENHANCE
++#endif
++/*#define	CONFIG_RA_DYNAMIC_RTY_LIMIT*/
++#define CONFIG_ANT_DETECTION
++#define	CONFIG_BB_TXBF_API
++#define	ODM_CONFIG_BT_COEXIST
++#define	CONFIG_PHYDM_DFS_MASTER
++#define	PHYDM_SUPPORT_RSSI_MONITOR
++#define	PHYDM_AUTO_DEGBUG
++#define CONFIG_PHYDM_DEBUG_FUNCTION
++#define CFG_DIG_DAMPING_CHK
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++	#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT ||  RTL8192E_SUPPORT ||\
++	     RTL8814A_SUPPORT || RTL8881A_SUPPORT)
++		#define	PHYDM_BEAMFORMING_VERSION1
++	#endif
++	#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
++	     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
++	     RTL8822C_SUPPORT || RTL8814B_SUPPORT)
++		#define	DRIVER_BEAMFORMING_VERSION2
++	#endif
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT)
++	/*#define CONFIG_DIRECTIONAL_BF*/
++#endif
++
++#if (RTL8822C_SUPPORT)
++	#define CONFIG_MU_RSOML
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_hwconfig.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_hwconfig.c
+new file mode 100644
+index 000000000..5526df94f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_hwconfig.c
+@@ -0,0 +1,1641 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ ************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#define READ_AND_CONFIG_MP(ic, txt) (odm_read_and_config_mp_##ic##txt(dm))
++#define READ_AND_CONFIG_TC(ic, txt) (odm_read_and_config_tc_##ic##txt(dm))
++
++#if (PHYDM_TESTCHIP_SUPPORT == 1)
++#define READ_AND_CONFIG(ic, txt)                     \
++	do {                                         \
++		if (dm->is_mp_chip)                  \
++			READ_AND_CONFIG_MP(ic, txt); \
++		else                                 \
++			READ_AND_CONFIG_TC(ic, txt); \
++	} while (0)
++#else
++#define READ_AND_CONFIG READ_AND_CONFIG_MP
++#endif
++
++#define GET_VERSION_MP(ic, txt) (odm_get_version_mp_##ic##txt())
++#define GET_VERSION_TC(ic, txt) (odm_get_version_tc_##ic##txt())
++
++#if (PHYDM_TESTCHIP_SUPPORT == 1)
++#define GET_VERSION(ic, txt) (dm->is_mp_chip ? GET_VERSION_MP(ic, txt) : GET_VERSION_TC(ic, txt))
++#else
++#define GET_VERSION(ic, txt) GET_VERSION_MP(ic, txt)
++#endif
++
++enum hal_status
++odm_config_rf_with_header_file(struct dm_struct *dm,
++			       enum odm_rf_config_type config_type,
++			       u8 e_rf_path)
++{
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
++#endif
++	enum hal_status result = HAL_STATUS_SUCCESS;
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "===>%s (%s)\n", __func__,
++		  (dm->is_mp_chip) ? "MPChip" : "TestChip");
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n",
++		  dm->support_platform, dm->support_interface, dm->board_type);
++
++/* @1 AP doesn't use PHYDM power tracking table in these ICs */
++#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
++#if (RTL8812A_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8812) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8812a, _radioa);
++			else if (e_rf_path == RF_PATH_B)
++				READ_AND_CONFIG_MP(8812a, _radiob);
++		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE)
++			HAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++			if ((hal_data->EEPROMSVID == 0x17AA && hal_data->EEPROMSMID == 0xA811) ||
++			    (hal_data->EEPROMSVID == 0x10EC && hal_data->EEPROMSMID == 0xA812) ||
++			    (hal_data->EEPROMSVID == 0x10EC && hal_data->EEPROMSMID == 0x8812))
++				READ_AND_CONFIG_MP(8812a, _txpwr_lmt_hm812a03);
++			else
++#endif
++				READ_AND_CONFIG_MP(8812a, _txpwr_lmt);
++		}
++	}
++#endif
++#if (RTL8821A_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8821) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8821a, _radioa);
++		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
++			if (dm->support_interface == ODM_ITRF_USB) {
++				if (dm->ext_pa_5g || dm->ext_lna_5g)
++					READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_fem);
++				else
++					READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_ipa);
++			} else {
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++				if (mgnt_info->CustomerID == RT_CID_8821AE_ASUS_MB)
++					READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_8mm);
++				else if (mgnt_info->CustomerID == RT_CID_ASUS_NB)
++					READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_5mm);
++				else
++#endif
++					READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a);
++			}
++		}
++	}
++#endif
++#if (RTL8192E_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8192E) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8192e, _radioa);
++			else if (e_rf_path == RF_PATH_B)
++				READ_AND_CONFIG_MP(8192e, _radiob);
++		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) /*Refine by Vincent Lan for 5mm SAR pwr limit*/
++			HAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++
++			if ((hal_data->EEPROMSVID == 0x11AD && hal_data->EEPROMSMID == 0x8192) ||
++			    (hal_data->EEPROMSVID == 0x11AD && hal_data->EEPROMSMID == 0x8193))
++				READ_AND_CONFIG_MP(8192e, _txpwr_lmt_8192e_sar_5mm);
++			else
++#endif
++				READ_AND_CONFIG_MP(8192e, _txpwr_lmt);
++		}
++	}
++#endif
++#if (RTL8723D_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8723D) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8723d, _radioa);
++		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
++			READ_AND_CONFIG_MP(8723d, _txpwr_lmt);
++		}
++	}
++#endif
++/* @JJ ADD 20161014 */
++#if (RTL8710B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8710B) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8710b, _radioa);
++		} else if (config_type == CONFIG_RF_TXPWR_LMT)
++			READ_AND_CONFIG_MP(8710b, _txpwr_lmt);
++	}
++#endif
++
++#endif /* @(DM_ODM_SUPPORT_TYPE !=  ODM_AP) */
++/* @1 All platforms support */
++#if (RTL8188E_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8188E) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8188e, _radioa);
++		} else if (config_type == CONFIG_RF_TXPWR_LMT)
++			READ_AND_CONFIG_MP(8188e, _txpwr_lmt);
++	}
++#endif
++#if (RTL8723B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8723B) {
++		if (config_type == CONFIG_RF_RADIO)
++			READ_AND_CONFIG_MP(8723b, _radioa);
++		else if (config_type == CONFIG_RF_TXPWR_LMT)
++			READ_AND_CONFIG_MP(8723b, _txpwr_lmt);
++	}
++#endif
++#if (RTL8814A_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8814A) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8814a, _radioa);
++			else if (e_rf_path == RF_PATH_B)
++				READ_AND_CONFIG_MP(8814a, _radiob);
++			else if (e_rf_path == RF_PATH_C)
++				READ_AND_CONFIG_MP(8814a, _radioc);
++			else if (e_rf_path == RF_PATH_D)
++				READ_AND_CONFIG_MP(8814a, _radiod);
++		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
++			if (dm->rfe_type == 0)
++				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type0);
++			else if (dm->rfe_type == 1)
++				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type1);
++			else if (dm->rfe_type == 2)
++				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type2);
++			else if (dm->rfe_type == 3)
++				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type3);
++			else if (dm->rfe_type == 5)
++				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type5);
++			else if (dm->rfe_type == 7)
++				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type7);
++			else if (dm->rfe_type == 8)
++				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type8);
++			else
++				READ_AND_CONFIG_MP(8814a, _txpwr_lmt);
++		}
++	}
++#endif
++#if (RTL8703B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8703B) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8703b, _radioa);
++		}
++	}
++#endif
++#if (RTL8188F_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8188F) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8188f, _radioa);
++		} else if (config_type == CONFIG_RF_TXPWR_LMT)
++			READ_AND_CONFIG_MP(8188f, _txpwr_lmt);
++	}
++#endif
++#if (RTL8822B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8822B) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8822b, _radioa);
++			else if (e_rf_path == RF_PATH_B)
++				READ_AND_CONFIG_MP(8822b, _radiob);
++		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
++			if (dm->rfe_type == 5)
++				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type5);
++			else if (dm->rfe_type == 2)
++				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type2);
++			else if (dm->rfe_type == 3)
++				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type3);
++			else if (dm->rfe_type == 4)
++				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type4);
++			else if (dm->rfe_type == 12)
++				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type12);
++			else if (dm->rfe_type == 15)
++				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type15);
++			else if (dm->rfe_type == 16)
++				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type16);
++			else if (dm->rfe_type == 17)
++				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type17);
++			else if (dm->rfe_type == 18)
++				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type18);
++			//else if (dm->rfe_type == 19)
++				//READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type19);
++			else
++				READ_AND_CONFIG_MP(8822b, _txpwr_lmt);
++		}
++	}
++#endif
++
++#if (RTL8197F_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8197F) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8197f, _radioa);
++			else if (e_rf_path == RF_PATH_B)
++				READ_AND_CONFIG_MP(8197f, _radiob);
++		}
++	}
++#endif
++/*@jj add 20170822*/
++#if (RTL8192F_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8192F) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8192f, _radioa);
++			else if (e_rf_path == RF_PATH_B)
++				READ_AND_CONFIG_MP(8192f, _radiob);
++		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
++			if (dm->rfe_type == 0)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type0);
++			else if (dm->rfe_type == 1)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type1);
++			else if (dm->rfe_type == 2)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type2);
++			else if (dm->rfe_type == 3)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type3);
++			else if (dm->rfe_type == 4)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type4);
++			else if (dm->rfe_type == 5)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type5);
++			else if (dm->rfe_type == 6)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type6);
++			else if (dm->rfe_type == 7)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type7);
++			else if (dm->rfe_type == 8)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type8);
++			else if (dm->rfe_type == 9)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type9);
++			else if (dm->rfe_type == 10)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type10);
++			else if (dm->rfe_type == 11)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type11);
++			else if (dm->rfe_type == 12)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type12);
++			else if (dm->rfe_type == 13)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type13);
++			else if (dm->rfe_type == 14)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type14);
++			else if (dm->rfe_type == 15)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type15);
++			else if (dm->rfe_type == 16)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type16);
++			else if (dm->rfe_type == 17)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type17);
++			else if (dm->rfe_type == 18)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type18);
++			else if (dm->rfe_type == 19)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type19);
++			else if (dm->rfe_type == 20)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type20);
++			else if (dm->rfe_type == 21)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type21);
++			else if (dm->rfe_type == 22)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type22);
++			else if (dm->rfe_type == 23)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type23);
++			else if (dm->rfe_type == 24)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type24);
++			else if (dm->rfe_type == 25)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type25);
++			else if (dm->rfe_type == 26)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type26);
++			else if (dm->rfe_type == 27)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type27);
++			else if (dm->rfe_type == 28)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type28);
++			else if (dm->rfe_type == 29)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type29);
++			else if (dm->rfe_type == 30)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type30);
++			else if (dm->rfe_type == 31)
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type31);
++			else
++				READ_AND_CONFIG_MP(8192f, _txpwr_lmt);
++		}
++	}
++#endif
++#if (RTL8721D_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8721D) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8721d, _radioa);
++		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
++			if (dm->power_voltage == ODM_POWER_18V)
++				READ_AND_CONFIG_MP(8721d, _txpwr_lmt_type0);
++			else
++				READ_AND_CONFIG_MP(8721d, _txpwr_lmt_type1);
++		}
++	}
++#endif
++
++#if (RTL8710C_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8710C) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8710c, _radioa);
++		} else if (config_type == CONFIG_RF_TXPWR_LMT)
++			READ_AND_CONFIG_MP(8710c, _txpwr_lmt);
++	}
++#endif
++
++#if (RTL8821C_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8821C) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG(8821c, _radioa);
++		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
++			READ_AND_CONFIG(8821c, _txpwr_lmt);
++		}
++	}
++#endif
++#if (RTL8195B_SUPPORT == 1)
++        if (dm->support_ic_type == ODM_RTL8195B) {
++                if (config_type == CONFIG_RF_RADIO) {
++                        if (e_rf_path == RF_PATH_A)
++                                READ_AND_CONFIG(8195b, _radioa);
++                } else if (config_type == CONFIG_RF_TXPWR_LMT) {
++                        READ_AND_CONFIG(8195b, _txpwr_lmt);
++                }
++        }
++#endif
++#if (RTL8198F_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8198F) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8198f, _radioa);
++			else if (e_rf_path == RF_PATH_B)
++				READ_AND_CONFIG_MP(8198f, _radiob);
++			else if (e_rf_path == RF_PATH_C)
++				READ_AND_CONFIG_MP(8198f, _radioc);
++			else if (e_rf_path == RF_PATH_D)
++				READ_AND_CONFIG_MP(8198f, _radiod);
++		}
++	}
++#endif
++/*#if (RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8814B) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8814b, _radioa);
++			else if (e_rf_path == RF_PATH_B)
++				READ_AND_CONFIG_MP(8814b, _radiob);
++			else if (e_rf_path == RF_PATH_C)
++				READ_AND_CONFIG_MP(8814b, _radioc);
++			else if (e_rf_path == RF_PATH_D)
++				READ_AND_CONFIG_MP(8814b, _radiod);
++		}
++	}
++#endif
++*/
++#if (RTL8822C_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8822C) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8822c, _radioa);
++			else if (e_rf_path == RF_PATH_B)
++				READ_AND_CONFIG_MP(8822c, _radiob);
++		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
++			READ_AND_CONFIG_MP(8822c, _txpwr_lmt);
++		}
++	}
++#endif
++#if (RTL8812F_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8812F) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8812f, _radioa);
++			else if (e_rf_path == RF_PATH_B)
++				READ_AND_CONFIG_MP(8812f, _radiob);
++		}
++	}
++#endif
++#if (RTL8197G_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8197G) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8197g, _radioa);
++			else if (e_rf_path == RF_PATH_B)
++				READ_AND_CONFIG_MP(8197g, _radiob);
++		}
++	}
++#endif
++
++ /*8814B need review, when phydm has related files*/
++ #if (RTL8814B_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8814B) {
++		if (config_type == CONFIG_RF_RADIO) {
++			if (e_rf_path == RF_PATH_A)
++				READ_AND_CONFIG_MP(8814b, _radioa);
++			else if (e_rf_path == RF_PATH_B)
++				READ_AND_CONFIG_MP(8814b, _radiob);
++			else if (e_rf_path == RF_PATH_C)
++				READ_AND_CONFIG_MP(8814b, _radioc);
++			else if (e_rf_path == RF_PATH_D)
++				READ_AND_CONFIG_MP(8814b, _radiod);
++		}
++		if (config_type == CONFIG_RF_SYN_RADIO) {
++			if (e_rf_path == RF_SYN0)
++				READ_AND_CONFIG_MP(8814b, _radiosyn0);
++			else if (e_rf_path == RF_SYN1)
++				READ_AND_CONFIG_MP(8814b, _radiosyn1);
++		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
++			READ_AND_CONFIG_MP(8814b, _txpwr_lmt);
++		}
++	}
++  #endif
++
++	if (config_type == CONFIG_RF_RADIO) {
++		if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
++			result = phydm_set_reg_by_fw(dm,
++						     PHYDM_HALMAC_CMD_END,
++						     0,
++						     0,
++						     0,
++						     (enum rf_path)0,
++						     0);
++			PHYDM_DBG(dm, ODM_COMP_INIT,
++				  "rf param offload end!result = %d", result);
++		}
++	}
++
++	return result;
++}
++
++enum hal_status
++odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm)
++{
++	PHYDM_DBG(dm, ODM_COMP_INIT, "===>%s (%s)\n", __func__,
++		  (dm->is_mp_chip) ? "MPChip" : "TestChip");
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n",
++		  dm->support_platform, dm->support_interface, dm->board_type);
++
++/* @1 AP doesn't use PHYDM power tracking table in these ICs */
++#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
++#if RTL8821A_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8821) {
++		if (dm->support_interface == ODM_ITRF_PCIE)
++			READ_AND_CONFIG_MP(8821a, _txpowertrack_pcie);
++		else if (dm->support_interface == ODM_ITRF_USB)
++			READ_AND_CONFIG_MP(8821a, _txpowertrack_usb);
++		else if (dm->support_interface == ODM_ITRF_SDIO)
++			READ_AND_CONFIG_MP(8821a, _txpowertrack_sdio);
++	}
++#endif
++#if RTL8812A_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8812) {
++		if (dm->support_interface == ODM_ITRF_PCIE)
++			READ_AND_CONFIG_MP(8812a, _txpowertrack_pcie);
++		else if (dm->support_interface == ODM_ITRF_USB) {
++			if (dm->rfe_type == 3 && dm->is_mp_chip)
++				READ_AND_CONFIG_MP(8812a, _txpowertrack_rfe3);
++			else
++				READ_AND_CONFIG_MP(8812a, _txpowertrack_usb);
++		}
++	}
++#endif
++#if RTL8192E_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8192E) {
++		if (dm->support_interface == ODM_ITRF_PCIE)
++			READ_AND_CONFIG_MP(8192e, _txpowertrack_pcie);
++		else if (dm->support_interface == ODM_ITRF_USB)
++			READ_AND_CONFIG_MP(8192e, _txpowertrack_usb);
++		else if (dm->support_interface == ODM_ITRF_SDIO)
++			READ_AND_CONFIG_MP(8192e, _txpowertrack_sdio);
++	}
++#endif
++#if RTL8723D_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8723D) {
++		if (dm->support_interface == ODM_ITRF_PCIE)
++			READ_AND_CONFIG_MP(8723d, _txpowertrack_pcie);
++		else if (dm->support_interface == ODM_ITRF_USB)
++			READ_AND_CONFIG_MP(8723d, _txpowertrack_usb);
++		else if (dm->support_interface == ODM_ITRF_SDIO)
++			READ_AND_CONFIG_MP(8723d, _txpowertrack_sdio);
++
++		READ_AND_CONFIG_MP(8723d, _txxtaltrack);
++	}
++#endif
++/* @JJ ADD 20161014 */
++#if RTL8710B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8710B) {
++		if (dm->package_type == 1)
++			READ_AND_CONFIG_MP(8710b, _txpowertrack_qfn48m_smic);
++		else if (dm->package_type == 5)
++			READ_AND_CONFIG_MP(8710b, _txpowertrack_qfn48m_umc);
++
++		READ_AND_CONFIG_MP(8710b, _txxtaltrack);
++	}
++#endif
++#if RTL8188E_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8188E) {
++		if (odm_get_mac_reg(dm, R_0xf0, 0xF000) >= 8) { /*@if 0xF0[15:12] >= 8, SMIC*/
++			if (dm->support_interface == ODM_ITRF_PCIE)
++				READ_AND_CONFIG_MP(8188e, _txpowertrack_pcie_icut);
++			else if (dm->support_interface == ODM_ITRF_USB)
++				READ_AND_CONFIG_MP(8188e, _txpowertrack_usb_icut);
++			else if (dm->support_interface == ODM_ITRF_SDIO)
++				READ_AND_CONFIG_MP(8188e, _txpowertrack_sdio_icut);
++		} else { /*@else 0xF0[15:12] < 8, TSMC*/
++			if (dm->support_interface == ODM_ITRF_PCIE)
++				READ_AND_CONFIG_MP(8188e, _txpowertrack_pcie);
++			else if (dm->support_interface == ODM_ITRF_USB)
++				READ_AND_CONFIG_MP(8188e, _txpowertrack_usb);
++			else if (dm->support_interface == ODM_ITRF_SDIO)
++				READ_AND_CONFIG_MP(8188e, _txpowertrack_sdio);
++		}
++	}
++#endif
++#endif /* @(DM_ODM_SUPPORT_TYPE !=  ODM_AP) */
++/* @1 All platforms support */
++#if RTL8723B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8723B) {
++		if (dm->support_interface == ODM_ITRF_PCIE)
++			READ_AND_CONFIG_MP(8723b, _txpowertrack_pcie);
++		else if (dm->support_interface == ODM_ITRF_USB)
++			READ_AND_CONFIG_MP(8723b, _txpowertrack_usb);
++		else if (dm->support_interface == ODM_ITRF_SDIO)
++			READ_AND_CONFIG_MP(8723b, _txpowertrack_sdio);
++	}
++#endif
++#if RTL8814A_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8814A) {
++		if (dm->rfe_type == 0)
++			READ_AND_CONFIG_MP(8814a, _txpowertrack_type0);
++		else if (dm->rfe_type == 2)
++			READ_AND_CONFIG_MP(8814a, _txpowertrack_type2);
++		else if (dm->rfe_type == 5)
++			READ_AND_CONFIG_MP(8814a, _txpowertrack_type5);
++		else if (dm->rfe_type == 7)
++			READ_AND_CONFIG_MP(8814a, _txpowertrack_type7);
++		else if (dm->rfe_type == 8)
++			READ_AND_CONFIG_MP(8814a, _txpowertrack_type8);
++		else
++			READ_AND_CONFIG_MP(8814a, _txpowertrack);
++
++		READ_AND_CONFIG_MP(8814a, _txpowertssi);
++	}
++#endif
++#if RTL8703B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8703B) {
++		if (dm->support_interface == ODM_ITRF_USB)
++			READ_AND_CONFIG_MP(8703b, _txpowertrack_usb);
++		else if (dm->support_interface == ODM_ITRF_SDIO)
++			READ_AND_CONFIG_MP(8703b, _txpowertrack_sdio);
++
++		READ_AND_CONFIG_MP(8703b, _txxtaltrack);
++	}
++#endif
++#if RTL8188F_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8188F) {
++		if (dm->support_interface == ODM_ITRF_USB)
++			READ_AND_CONFIG_MP(8188f, _txpowertrack_usb);
++		else if (dm->support_interface == ODM_ITRF_SDIO)
++			READ_AND_CONFIG_MP(8188f, _txpowertrack_sdio);
++	}
++#endif
++#if RTL8822B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8822B) {
++		if (dm->rfe_type == 0)
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type0);
++		else if (dm->rfe_type == 1)
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type1);
++		else if (dm->rfe_type == 2)
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type2);
++		else if ((dm->rfe_type == 3) || (dm->rfe_type == 5))
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type3_type5);
++		else if (dm->rfe_type == 4)
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type4);
++		else if (dm->rfe_type == 6)
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type6);
++		else if (dm->rfe_type == 7)
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type7);
++		else if (dm->rfe_type == 8)
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type8);
++		else if (dm->rfe_type == 9)
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type9);
++		else if (dm->rfe_type == 10)
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type10);
++		else if (dm->rfe_type == 11)
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type11);
++		else if (dm->rfe_type == 12)
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type12);
++		else if (dm->rfe_type == 13)
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type13);
++		else if (dm->rfe_type == 14)
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type14);
++		else if (dm->rfe_type == 15)
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type15);
++		else if (dm->rfe_type == 16)
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type16);
++		else if (dm->rfe_type == 17)
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type17);
++		else if (dm->rfe_type == 18)
++			READ_AND_CONFIG_MP(8822b, _txpowertrack_type18);
++		//else if (dm->rfe_type == 19)
++			//READ_AND_CONFIG_MP(8822b, _txpowertrack_type19);
++		else
++			READ_AND_CONFIG_MP(8822b, _txpowertrack);
++	}
++#endif
++#if RTL8197F_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8197F) {
++		if (dm->rfe_type == 0)
++			READ_AND_CONFIG_MP(8197f, _txpowertrack_type0);
++		else if (dm->rfe_type == 1)
++			READ_AND_CONFIG_MP(8197f, _txpowertrack_type1);
++		else
++			READ_AND_CONFIG_MP(8197f, _txpowertrack);
++	}
++#endif
++/*@jj add 20170822*/
++#if RTL8192F_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8192F) {
++		if (dm->rfe_type == 0)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type0);
++		else if (dm->rfe_type == 1)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type1);
++		else if (dm->rfe_type == 2)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type2);
++		else if (dm->rfe_type == 3)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type3);
++		else if (dm->rfe_type == 4)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type4);
++		else if (dm->rfe_type == 5)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type5);
++		else if (dm->rfe_type == 6)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type6);
++		else if (dm->rfe_type == 7)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type7);
++		else if (dm->rfe_type == 8)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type8);
++		else if (dm->rfe_type == 9)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type9);
++		else if (dm->rfe_type == 10)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type10);
++		else if (dm->rfe_type == 11)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type11);
++		else if (dm->rfe_type == 12)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type12);
++		else if (dm->rfe_type == 13)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type13);
++		else if (dm->rfe_type == 14)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type14);
++		else if (dm->rfe_type == 15)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type15);
++		else if (dm->rfe_type == 16)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type16);
++		else if (dm->rfe_type == 17)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type17);
++		else if (dm->rfe_type == 18)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type18);
++		else if (dm->rfe_type == 19)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type19);
++		else if (dm->rfe_type == 20)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type20);
++		else if (dm->rfe_type == 21)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type21);
++		else if (dm->rfe_type == 22)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type22);
++		else if (dm->rfe_type == 23)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type23);
++		else if (dm->rfe_type == 24)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type24);
++		else if (dm->rfe_type == 25)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type25);
++		else if (dm->rfe_type == 26)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type26);
++		else if (dm->rfe_type == 27)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type27);
++		else if (dm->rfe_type == 28)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type28);
++		else if (dm->rfe_type == 29)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type29);
++		else if (dm->rfe_type == 30)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type30);
++		else if (dm->rfe_type == 31)
++			READ_AND_CONFIG_MP(8192f, _txpowertrack_type31);
++		else
++			READ_AND_CONFIG_MP(8192f, _txpowertrack);
++
++		READ_AND_CONFIG_MP(8192f, _txxtaltrack);
++	}
++#endif
++
++#if RTL8721D_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8721D) {
++		#if 0
++		if (dm->package_type == 1)
++			READ_AND_CONFIG_MP(8721d, _txpowertrack_qfn48m_smic);
++		else if (dm->package_type == 5)
++			READ_AND_CONFIG_MP(8721d, _txpowertrack_qfn48m_umc);
++		#endif
++		READ_AND_CONFIG_MP(8721d, _txpowertrack);
++		READ_AND_CONFIG_MP(8721d, _txxtaltrack);
++	}
++#endif
++
++#if RTL8710C_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8710C) {
++		#if 0
++		if (dm->package_type == 1)
++			READ_AND_CONFIG_MP(8710c, _txpowertrack_qfn48m_smic);
++		else if (dm->package_type == 5)
++			READ_AND_CONFIG_MP(8710c, _txpowertrack_qfn48m_umc);
++		#endif
++		READ_AND_CONFIG_MP(8710c, _txpowertrack);
++		READ_AND_CONFIG_MP(8710c, _txxtaltrack);
++	}
++#endif
++
++#if RTL8821C_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8821C) {
++		if (dm->rfe_type == 0x5)
++			READ_AND_CONFIG(8821c, _txpowertrack_type0x28);
++		else if (dm->rfe_type == 0x4)
++			READ_AND_CONFIG(8821c, _txpowertrack_type0x20);
++		else
++			READ_AND_CONFIG(8821c, _txpowertrack);
++	}
++#endif
++
++#if RTL8198F_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8198F) {
++		if (dm->rfe_type == 0)
++			READ_AND_CONFIG_MP(8198f, _txpowertrack_type0);
++		else if (dm->rfe_type == 1)
++			READ_AND_CONFIG_MP(8198f, _txpowertrack_type1);
++		else if (dm->rfe_type == 3)
++			READ_AND_CONFIG_MP(8198f, _txpowertrack_type3);
++		else
++			READ_AND_CONFIG_MP(8198f, _txpowertrack);
++		}
++#endif
++
++#if RTL8195B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8195B) {
++		if (dm->package_type == 1) {
++			READ_AND_CONFIG_MP(8195b, _txpowertrack_pkg1);
++			READ_AND_CONFIG_MP(8195b, _txxtaltrack_pkg1);
++		} else {
++			READ_AND_CONFIG_MP(8195b, _txpowertrack);
++			READ_AND_CONFIG_MP(8195b, _txxtaltrack);
++		}
++	}
++#endif
++
++#if (RTL8822C_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8822C) {
++		if (dm->en_tssi_mode)
++			READ_AND_CONFIG_MP(8822c, _txpowertracktssi);
++		else
++			READ_AND_CONFIG_MP(8822c, _txpowertrack);
++	}
++#endif
++
++#if (RTL8812F_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8812F) {
++		if (dm->rfe_type == 0)
++			READ_AND_CONFIG_MP(8812f, _txpowertrack_type0);
++		else if (dm->rfe_type == 1)
++			READ_AND_CONFIG_MP(8812f, _txpowertrack_type1);
++		else if (dm->rfe_type == 2)
++			READ_AND_CONFIG_MP(8812f, _txpowertrack_type2);
++		else if (dm->rfe_type == 3)
++			READ_AND_CONFIG_MP(8812f, _txpowertrack_type3);
++		else if (dm->rfe_type == 4)
++			READ_AND_CONFIG_MP(8812f, _txpowertrack_type4);
++		else
++			READ_AND_CONFIG_MP(8812f, _txpowertrack);
++	}
++#endif
++
++#if (RTL8197G_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8197G)
++		READ_AND_CONFIG_MP(8197g, _txpowertrack);
++#endif
++
++#if RTL8814B_SUPPORT
++	if (dm->support_ic_type == ODM_RTL8814B) {
++		if (dm->rfe_type == 0)
++			READ_AND_CONFIG_MP(8814b, _txpowertrack_type0);
++		else if (dm->rfe_type == 1)
++			READ_AND_CONFIG_MP(8814b, _txpowertrack_type1);
++		else if (dm->rfe_type == 2)
++			READ_AND_CONFIG_MP(8814b, _txpowertrack_type2);
++#if 0
++		else if (dm->rfe_type == 3)
++			READ_AND_CONFIG_MP(8814b, _txpowertrack_type3);
++		else if (dm->rfe_type == 6)
++			READ_AND_CONFIG_MP(8814b, _txpowertrack_type6);
++#endif
++		else
++			READ_AND_CONFIG_MP(8814b, _txpowertrack);
++		}
++#endif
++
++	return HAL_STATUS_SUCCESS;
++}
++
++enum hal_status
++odm_config_bb_with_header_file(struct dm_struct *dm,
++			       enum odm_bb_config_type config_type)
++{
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
++#endif
++	enum hal_status result = HAL_STATUS_SUCCESS;
++
++/* @1 AP doesn't use PHYDM initialization in these ICs */
++#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
++#if (RTL8812A_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8812) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG_MP(8812a, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8812a, _agc_tab);
++		else if (config_type == CONFIG_BB_PHY_REG_PG) {
++			if (dm->rfe_type == 3 && dm->is_mp_chip)
++				READ_AND_CONFIG_MP(8812a, _phy_reg_pg_asus);
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++			else if (mgnt_info->CustomerID == RT_CID_WNC_NEC && dm->is_mp_chip)
++				READ_AND_CONFIG_MP(8812a, _phy_reg_pg_nec);
++#if RT_PLATFORM == PLATFORM_MACOSX
++			/*@{1827}{1024} for BUFFALO power by rate table. Isaiah 2013-11-29*/
++			else if (mgnt_info->CustomerID == RT_CID_DNI_BUFFALO)
++				READ_AND_CONFIG_MP(8812a, _phy_reg_pg_dni);
++			/* TP-Link T4UH, Isaiah 2015-03-16*/
++			else if (mgnt_info->CustomerID == RT_CID_TPLINK_HPWR) {
++				pr_debug("RT_CID_TPLINK_HPWR:: _PHY_REG_PG_TPLINK\n");
++				READ_AND_CONFIG_MP(8812a, _phy_reg_pg_tplink);
++			}
++#endif
++#endif
++			else
++				READ_AND_CONFIG_MP(8812a, _phy_reg_pg);
++		} else if (config_type == CONFIG_BB_PHY_REG_MP)
++			READ_AND_CONFIG_MP(8812a, _phy_reg_mp);
++		else if (config_type == CONFIG_BB_AGC_TAB_DIFF) {
++			dm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD;
++			/*@AGC_TAB DIFF dont support FW offload*/
++			if ((*dm->channel >= 36) && (*dm->channel <= 64))
++				AGC_DIFF_CONFIG_MP(8812a, lb);
++			else if (*dm->channel >= 100)
++				AGC_DIFF_CONFIG_MP(8812a, hb);
++		}
++	}
++#endif
++#if (RTL8821A_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8821) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG_MP(8821a, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8821a, _agc_tab);
++		else if (config_type == CONFIG_BB_PHY_REG_PG) {
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
++			HAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++
++			if ((hal_data->EEPROMSVID == 0x1043 && hal_data->EEPROMSMID == 0x207F))
++				READ_AND_CONFIG_MP(8821a, _phy_reg_pg_e202_sa);
++			else
++#endif
++#if (RT_PLATFORM == PLATFORM_MACOSX)
++				/*@  for BUFFALO pwr by rate table */
++				if (mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) {
++				/*@  for BUFFALO pwr by rate table (JP/US)*/
++				if (mgnt_info->ChannelPlan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G)
++					READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_us);
++				else
++					READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_jp);
++			} else
++#endif
++#endif
++				READ_AND_CONFIG_MP(8821a, _phy_reg_pg);
++		}
++	}
++#endif
++#if (RTL8192E_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8192E) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG_MP(8192e, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8192e, _agc_tab);
++		else if (config_type == CONFIG_BB_PHY_REG_PG)
++			READ_AND_CONFIG_MP(8192e, _phy_reg_pg);
++	}
++#endif
++#if (RTL8723D_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8723D) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG_MP(8723d, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8723d, _agc_tab);
++		else if (config_type == CONFIG_BB_PHY_REG_PG)
++			READ_AND_CONFIG_MP(8723d, _phy_reg_pg);
++	}
++#endif
++/* @JJ ADD 20161014 */
++#if (RTL8710B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8710B) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG_MP(8710b, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8710b, _agc_tab);
++		else if (config_type == CONFIG_BB_PHY_REG_PG)
++			READ_AND_CONFIG_MP(8710b, _phy_reg_pg);
++	}
++#endif
++
++#endif /* @(DM_ODM_SUPPORT_TYPE !=  ODM_AP) */
++/* @1 All platforms support */
++#if (RTL8188E_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8188E) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG_MP(8188e, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8188e, _agc_tab);
++		else if (config_type == CONFIG_BB_PHY_REG_PG)
++			READ_AND_CONFIG_MP(8188e, _phy_reg_pg);
++	}
++#endif
++#if (RTL8723B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8723B) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG_MP(8723b, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8723b, _agc_tab);
++		else if (config_type == CONFIG_BB_PHY_REG_PG)
++			READ_AND_CONFIG_MP(8723b, _phy_reg_pg);
++	}
++#endif
++#if (RTL8814A_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8814A) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG_MP(8814a, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8814a, _agc_tab);
++		else if (config_type == CONFIG_BB_PHY_REG_PG) {
++			if (dm->rfe_type == 0)
++				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type0);
++			else if (dm->rfe_type == 2)
++				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type2);
++			else if (dm->rfe_type == 3)
++				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type3);
++			else if (dm->rfe_type == 4)
++				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type4);
++			else if (dm->rfe_type == 5)
++				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type5);
++			else if (dm->rfe_type == 7)
++				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type7);
++			else if (dm->rfe_type == 8)
++				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type8);
++			else
++				READ_AND_CONFIG_MP(8814a, _phy_reg_pg);
++		} else if (config_type == CONFIG_BB_PHY_REG_MP)
++			READ_AND_CONFIG_MP(8814a, _phy_reg_mp);
++	}
++#endif
++#if (RTL8703B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8703B) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG_MP(8703b, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8703b, _agc_tab);
++		else if (config_type == CONFIG_BB_PHY_REG_PG)
++			READ_AND_CONFIG_MP(8703b, _phy_reg_pg);
++	}
++#endif
++#if (RTL8188F_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8188F) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG_MP(8188f, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8188f, _agc_tab);
++		else if (config_type == CONFIG_BB_PHY_REG_PG)
++			READ_AND_CONFIG_MP(8188f, _phy_reg_pg);
++	}
++#endif
++#if (RTL8822B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8822B) {
++		if (config_type == CONFIG_BB_PHY_REG) {
++			READ_AND_CONFIG_MP(8822b, _phy_reg);
++		} else if (config_type == CONFIG_BB_AGC_TAB) {
++			READ_AND_CONFIG_MP(8822b, _agc_tab);
++		} else if (config_type == CONFIG_BB_PHY_REG_PG) {
++			if (dm->rfe_type == 2)
++				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type2);
++			else if (dm->rfe_type == 3)
++				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type3);
++			else if (dm->rfe_type == 4)
++				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type4);
++			else if (dm->rfe_type == 5)
++				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type5);
++			else if (dm->rfe_type == 12)
++				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type12);
++			else if (dm->rfe_type == 15)
++				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type15);
++			else if (dm->rfe_type == 16)
++				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type16);
++			else if (dm->rfe_type == 17)
++				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type17);
++			else if (dm->rfe_type == 18)
++				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type18);
++			//else if (dm->rfe_type == 19)
++				//READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type19);
++			else
++				READ_AND_CONFIG_MP(8822b, _phy_reg_pg);
++		}
++	}
++#endif
++
++#if (RTL8197F_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8197F) {
++		if (config_type == CONFIG_BB_PHY_REG) {
++			READ_AND_CONFIG_MP(8197f, _phy_reg);
++			if (dm->cut_version == ODM_CUT_A)
++				phydm_phypara_a_cut(dm);
++		} else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8197f, _agc_tab);
++	}
++#endif
++/*@jj add 20170822*/
++#if (RTL8192F_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8192F) {
++		if (config_type == CONFIG_BB_PHY_REG) {
++			READ_AND_CONFIG_MP(8192f, _phy_reg);
++		} else if (config_type == CONFIG_BB_AGC_TAB) {
++			READ_AND_CONFIG_MP(8192f, _agc_tab);
++		} else if (config_type == CONFIG_BB_PHY_REG_PG) {
++			if (dm->rfe_type == 0)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type0);
++			else if (dm->rfe_type == 1)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type1);
++			else if (dm->rfe_type == 2)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type2);
++			else if (dm->rfe_type == 3)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type3);
++			else if (dm->rfe_type == 4)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type4);
++			else if (dm->rfe_type == 5)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type5);
++			else if (dm->rfe_type == 6)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type6);
++			else if (dm->rfe_type == 7)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type7);
++			else if (dm->rfe_type == 8)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type8);
++			else if (dm->rfe_type == 9)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type9);
++			else if (dm->rfe_type == 10)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type10);
++			else if (dm->rfe_type == 11)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type11);
++			else if (dm->rfe_type == 12)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type12);
++			else if (dm->rfe_type == 13)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type13);
++			else if (dm->rfe_type == 14)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type14);
++			else if (dm->rfe_type == 15)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type15);
++			else if (dm->rfe_type == 16)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type16);
++			else if (dm->rfe_type == 17)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type17);
++			else if (dm->rfe_type == 18)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type18);
++			else if (dm->rfe_type == 19)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type19);
++			else if (dm->rfe_type == 20)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type20);
++			else if (dm->rfe_type == 21)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type21);
++			else if (dm->rfe_type == 22)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type22);
++			else if (dm->rfe_type == 23)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type23);
++			else if (dm->rfe_type == 24)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type24);
++			else if (dm->rfe_type == 25)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type25);
++			else if (dm->rfe_type == 26)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type26);
++			else if (dm->rfe_type == 27)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type27);
++			else if (dm->rfe_type == 28)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type28);
++			else if (dm->rfe_type == 29)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type29);
++			else if (dm->rfe_type == 30)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type30);
++			else if (dm->rfe_type == 31)
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type31);
++			else
++				READ_AND_CONFIG_MP(8192f, _phy_reg_pg);
++		}
++	}
++#endif
++#if (RTL8721D_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8721D) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG_MP(8721d, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8721d, _agc_tab);
++		else if (config_type == CONFIG_BB_PHY_REG_PG) {
++			if (dm->power_voltage == ODM_POWER_18V)
++				READ_AND_CONFIG_MP(8721d, _phy_reg_pg_type0);
++			else
++				READ_AND_CONFIG_MP(8721d, _phy_reg_pg_type1);
++		}
++	}
++#endif
++
++#if (RTL8710C_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8710C) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG_MP(8710c, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8710c, _agc_tab);
++		else if (config_type == CONFIG_BB_PHY_REG_PG)
++			READ_AND_CONFIG_MP(8710c, _phy_reg_pg);
++	}
++#endif
++
++#if (RTL8821C_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8821C) {
++		if (config_type == CONFIG_BB_PHY_REG) {
++			READ_AND_CONFIG(8821c, _phy_reg);
++		} else if (config_type == CONFIG_BB_AGC_TAB) {
++			READ_AND_CONFIG(8821c, _agc_tab);
++			/* @According to RFEtype, choosing correct AGC table*/
++			if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
++				AGC_DIFF_CONFIG_MP(8821c, btg);
++		} else if (config_type == CONFIG_BB_PHY_REG_PG) {
++			if (dm->rfe_type == 0x5)
++				READ_AND_CONFIG(8821c, _phy_reg_pg_type0x28);
++			else
++				READ_AND_CONFIG(8821c, _phy_reg_pg);
++		} else if (config_type == CONFIG_BB_AGC_TAB_DIFF) {
++			dm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD;
++			/*@AGC_TAB DIFF dont support FW offload*/
++			if (dm->current_rf_set_8821c == SWITCH_TO_BTG)
++				AGC_DIFF_CONFIG_MP(8821c, btg);
++			else if (dm->current_rf_set_8821c == SWITCH_TO_WLG)
++				AGC_DIFF_CONFIG_MP(8821c, wlg);
++		} else if (config_type == CONFIG_BB_PHY_REG_MP) {
++			READ_AND_CONFIG(8821c, _phy_reg_mp);
++		}
++	}
++#endif
++
++#if (RTL8195A_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8195A) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG(8195a, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG(8195a, _agc_tab);
++		else if (config_type == CONFIG_BB_PHY_REG_PG)
++			READ_AND_CONFIG(8195a, _phy_reg_pg);
++	}
++#endif
++#if (RTL8195B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8195B) {
++		if (config_type == CONFIG_BB_PHY_REG) {
++			READ_AND_CONFIG(8195b, _phy_reg);
++		} else if (config_type == CONFIG_BB_AGC_TAB) {
++			READ_AND_CONFIG(8195b, _agc_tab);
++		} else if (config_type == CONFIG_BB_PHY_REG_PG) {
++			READ_AND_CONFIG(8195b, _phy_reg_pg);
++		} else if (config_type == CONFIG_BB_PHY_REG_MP) {
++			if (dm->package_type == 1)
++				odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, 0x10);
++			else
++				odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, 0x12);
++		}
++	}
++#endif
++#if (RTL8198F_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8198F) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG_MP(8198f, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8198f, _agc_tab);
++	}
++#endif
++#if (RTL8814B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8814B) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG_MP(8814b, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8814b, _agc_tab);
++		else if (config_type == CONFIG_BB_PHY_REG_PG) {
++			if (dm->rfe_type == 1)
++				READ_AND_CONFIG(8814b, _phy_reg_pg_type1);
++			else
++				READ_AND_CONFIG(8814b, _phy_reg_pg);
++		}
++	}
++#endif
++#if (RTL8822C_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8822C) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG_MP(8822c, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8822c, _agc_tab);
++		else if (config_type == CONFIG_BB_PHY_REG_PG)
++			READ_AND_CONFIG(8822c, _phy_reg_pg);
++	}
++#endif
++#if (RTL8812F_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8812F) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG_MP(8812f, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8812f, _agc_tab);
++		else if (config_type == CONFIG_BB_PHY_REG_PG)
++			READ_AND_CONFIG(8812f, _phy_reg_pg);
++	}
++#endif
++#if (RTL8197G_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8197G) {
++		if (config_type == CONFIG_BB_PHY_REG)
++			READ_AND_CONFIG_MP(8197g, _phy_reg);
++		else if (config_type == CONFIG_BB_AGC_TAB)
++			READ_AND_CONFIG_MP(8197g, _agc_tab);
++		else if (config_type == CONFIG_BB_PHY_REG_PG)
++			READ_AND_CONFIG(8197g, _phy_reg_pg);
++	}
++#endif
++
++	if (config_type == CONFIG_BB_PHY_REG ||
++	    config_type == CONFIG_BB_AGC_TAB)
++		if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
++			result = phydm_set_reg_by_fw(dm,
++						     PHYDM_HALMAC_CMD_END,
++						     0,
++						     0,
++						     0,
++						     (enum rf_path)0,
++						     0);
++			PHYDM_DBG(dm, ODM_COMP_INIT,
++				  "phy param offload end!result = %d", result);
++		}
++
++	return result;
++}
++
++enum hal_status
++odm_config_mac_with_header_file(struct dm_struct *dm)
++{
++	enum hal_status result = HAL_STATUS_SUCCESS;
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "===>%s (%s)\n", __func__,
++		  (dm->is_mp_chip) ? "MPChip" : "TestChip");
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n",
++		  dm->support_platform, dm->support_interface, dm->board_type);
++
++#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT)
++	if (dm->support_ic_type &
++	    (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8814B)) {
++		PHYDM_DBG(dm, ODM_COMP_INIT, "MAC para-package in HALMAC\n");
++		return result;
++	}
++#endif
++
++/* @1 AP doesn't use PHYDM initialization in these ICs */
++#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
++#if (RTL8812A_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8812)
++		READ_AND_CONFIG_MP(8812a, _mac_reg);
++#endif
++#if (RTL8821A_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8821)
++		READ_AND_CONFIG_MP(8821a, _mac_reg);
++#endif
++#if (RTL8192E_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8192E)
++		READ_AND_CONFIG_MP(8192e, _mac_reg);
++#endif
++#if (RTL8723D_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8723D)
++		READ_AND_CONFIG_MP(8723d, _mac_reg);
++#endif
++#if (RTL8710B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8710B)
++		READ_AND_CONFIG_MP(8710b, _mac_reg);
++#endif
++#endif /* @(DM_ODM_SUPPORT_TYPE !=  ODM_AP) */
++
++/* @1 All platforms support */
++#if (RTL8188E_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8188E)
++		READ_AND_CONFIG_MP(8188e, _mac_reg);
++#endif
++#if (RTL8723B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8723B)
++		READ_AND_CONFIG_MP(8723b, _mac_reg);
++#endif
++#if (RTL8814A_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8814A)
++		READ_AND_CONFIG_MP(8814a, _mac_reg);
++#endif
++#if (RTL8703B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8703B)
++		READ_AND_CONFIG_MP(8703b, _mac_reg);
++#endif
++#if (RTL8188F_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8188F)
++		READ_AND_CONFIG_MP(8188f, _mac_reg);
++#endif
++#if (RTL8822B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8822B)
++		READ_AND_CONFIG_MP(8822b, _mac_reg);
++#endif
++#if (RTL8197F_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8197F)
++		READ_AND_CONFIG_MP(8197f, _mac_reg);
++#endif
++#if (RTL8192F_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8192F)
++		READ_AND_CONFIG_MP(8192f, _mac_reg);
++#endif
++#if (RTL8721D_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8721D)
++		READ_AND_CONFIG_MP(8721d, _mac_reg);
++#endif
++
++#if (RTL8710C_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8710C)
++		READ_AND_CONFIG_MP(8710c, _mac_reg);
++#endif
++
++#if (RTL8821C_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8821C)
++		READ_AND_CONFIG(8821c, _mac_reg);
++#endif
++#if (RTL8195A_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8195A)
++		READ_AND_CONFIG_MP(8195a, _mac_reg);
++#endif
++#if (RTL8195B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8195B)
++		READ_AND_CONFIG_MP(8195b, _mac_reg);
++#endif
++#if (RTL8198F_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8198F)
++		READ_AND_CONFIG_MP(8198f, _mac_reg);
++#endif
++#if (RTL8197G_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8197G)
++		READ_AND_CONFIG_MP(8197g, _mac_reg);
++#endif
++
++	if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
++		result = phydm_set_reg_by_fw(dm,
++					     PHYDM_HALMAC_CMD_END,
++					     0,
++					     0,
++					     0,
++					     (enum rf_path)0,
++					     0);
++		PHYDM_DBG(dm, ODM_COMP_INIT,
++			  "mac param offload end!result = %d", result);
++	}
++
++	return result;
++}
++
++u32 odm_get_hw_img_version(struct dm_struct *dm)
++{
++	u32 version = 0;
++
++	switch (dm->support_ic_type) {
++/* @1 AP doesn't use PHYDM initialization in these ICs */
++#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
++#if (RTL8821A_SUPPORT)
++	case ODM_RTL8821:
++		version = odm_get_version_mp_8821a_phy_reg();
++		break;
++#endif
++#if (RTL8192E_SUPPORT)
++	case ODM_RTL8192E:
++		version = odm_get_version_mp_8192e_phy_reg();
++		break;
++#endif
++#if (RTL8812A_SUPPORT)
++	case ODM_RTL8812:
++		version = odm_get_version_mp_8812a_phy_reg();
++		break;
++#endif
++#endif /* @(DM_ODM_SUPPORT_TYPE != ODM_AP) */
++#if (RTL8723D_SUPPORT)
++	case ODM_RTL8723D:
++		version = odm_get_version_mp_8723d_phy_reg();
++		break;
++#endif
++#if (RTL8710B_SUPPORT)
++	case ODM_RTL8710B:
++		version = odm_get_version_mp_8710b_phy_reg();
++		break;
++#endif
++#if (RTL8188E_SUPPORT)
++	case ODM_RTL8188E:
++		version = odm_get_version_mp_8188e_phy_reg();
++		break;
++#endif
++#if (RTL8723B_SUPPORT)
++	case ODM_RTL8723B:
++		version = odm_get_version_mp_8723b_phy_reg();
++		break;
++#endif
++#if (RTL8814A_SUPPORT)
++	case ODM_RTL8814A:
++		version = odm_get_version_mp_8814a_phy_reg();
++		break;
++#endif
++#if (RTL8703B_SUPPORT)
++	case ODM_RTL8703B:
++		version = odm_get_version_mp_8703b_phy_reg();
++		break;
++#endif
++#if (RTL8188F_SUPPORT)
++	case ODM_RTL8188F:
++		version = odm_get_version_mp_8188f_phy_reg();
++		break;
++#endif
++#if (RTL8822B_SUPPORT)
++	case ODM_RTL8822B:
++		version = odm_get_version_mp_8822b_phy_reg();
++		break;
++#endif
++#if (RTL8197F_SUPPORT)
++	case ODM_RTL8197F:
++		version = odm_get_version_mp_8197f_phy_reg();
++		break;
++#endif
++
++#if (RTL8192F_SUPPORT)
++	case ODM_RTL8192F:
++		version = odm_get_version_mp_8192f_phy_reg();
++		break;
++#endif
++#if (RTL8721D_SUPPORT)
++	case ODM_RTL8721D:
++		version = odm_get_version_mp_8721d_phy_reg();
++		break;
++#endif
++#if (RTL8710C_SUPPORT)
++	case ODM_RTL8710C:
++		version = GET_VERSION_MP(8710c, _mac_reg);
++#endif
++#if (RTL8821C_SUPPORT)
++	case ODM_RTL8821C:
++		version = odm_get_version_mp_8821c_phy_reg();
++		break;
++#endif
++#if (RTL8195B_SUPPORT)
++	case ODM_RTL8195B:
++		version = odm_get_version_mp_8195b_phy_reg();
++		break;
++#endif
++#if (RTL8198F_SUPPORT)
++	case ODM_RTL8198F:
++		version = odm_get_version_mp_8198f_phy_reg();
++		break;
++#endif
++#if (RTL8822C_SUPPORT)
++	case ODM_RTL8822C:
++		version = odm_get_version_mp_8822c_phy_reg();
++		break;
++#endif
++#if (RTL8812F_SUPPORT)
++	case ODM_RTL8812F:
++		version = odm_get_version_mp_8812f_phy_reg();
++		break;
++#endif
++#if (RTL8197G_SUPPORT)
++	case ODM_RTL8197G:
++		version = odm_get_version_mp_8197g_phy_reg();
++		break;
++#endif
++#if (RTL8814B_SUPPORT)
++	case ODM_RTL8814B:
++		version = odm_get_version_mp_8814b_phy_reg();
++		break;
++#endif
++	}
++
++	return version;
++}
++
++u32 query_phydm_trx_capability(struct dm_struct *dm)
++{
++	u32 value32 = 0xFFFFFFFF;
++
++#if (RTL8821C_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8821C)
++		value32 = query_phydm_trx_capability_8821c(dm);
++#endif
++#if (RTL8195B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8195B)
++		value32 = query_phydm_trx_capability_8195b(dm);
++#endif
++	return value32;
++}
++
++u32 query_phydm_stbc_capability(struct dm_struct *dm)
++{
++	u32 value32 = 0xFFFFFFFF;
++
++#if (RTL8821C_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8821C)
++		value32 = query_phydm_stbc_capability_8821c(dm);
++#endif
++#if (RTL8195B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8195B)
++		value32 = query_phydm_stbc_capability_8195b(dm);
++#endif
++
++	return value32;
++}
++
++u32 query_phydm_ldpc_capability(struct dm_struct *dm)
++{
++	u32 value32 = 0xFFFFFFFF;
++
++#if (RTL8821C_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8821C)
++		value32 = query_phydm_ldpc_capability_8821c(dm);
++#endif
++#if (RTL8195B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8195B)
++		value32 = query_phydm_ldpc_capability_8195b(dm);
++#endif
++	return value32;
++}
++
++u32 query_phydm_txbf_parameters(struct dm_struct *dm)
++{
++	u32 value32 = 0xFFFFFFFF;
++
++#if (RTL8821C_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8821C)
++		value32 = query_phydm_txbf_parameters_8821c(dm);
++#endif
++#if (RTL8195B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8195B)
++		value32 = query_phydm_txbf_parameters_8195b(dm);
++#endif
++	return value32;
++}
++
++u32 query_phydm_txbf_capability(struct dm_struct *dm)
++{
++	u32 value32 = 0xFFFFFFFF;
++
++#if (RTL8821C_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8821C)
++		value32 = query_phydm_txbf_capability_8821c(dm);
++#endif
++#if (RTL8195B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8195B)
++		value32 = query_phydm_txbf_capability_8195b(dm);
++#endif
++	return value32;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_hwconfig.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_hwconfig.h
+new file mode 100644
+index 000000000..7c4d1e38c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_hwconfig.h
+@@ -0,0 +1,79 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __HALHWOUTSRC_H__
++#define __HALHWOUTSRC_H__
++
++/*@--------------------------Define -------------------------------------------*/
++#define AGC_DIFF_CONFIG_MP(ic, band)				\
++	(odm_read_and_config_mp_##ic##_agc_tab_diff(dm,		\
++	array_mp_##ic##_agc_tab_diff_##band,			\
++	sizeof(array_mp_##ic##_agc_tab_diff_##band) / sizeof(u32)))
++#define AGC_DIFF_CONFIG_TC(ic, band)				\
++	(odm_read_and_config_tc_##ic##_agc_tab_diff(dm,		\
++	array_tc_##ic##_agc_tab_diff_##band,			\
++	sizeof(array_tc_##ic##_agc_tab_diff_##band) / sizeof(u32)))
++#if defined(DM_ODM_CE_MAC80211)
++#else
++#define AGC_DIFF_CONFIG(ic, band)                     \
++	do {                                          \
++		if (dm->is_mp_chip)                   \
++			AGC_DIFF_CONFIG_MP(ic, band); \
++		else                                  \
++			AGC_DIFF_CONFIG_TC(ic, band); \
++	} while (0)
++#endif
++/*@************************************************************
++ * structure and define
++ ************************************************************/
++
++enum hal_status
++odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm);
++
++enum hal_status
++odm_config_rf_with_header_file(struct dm_struct *dm,
++			       enum odm_rf_config_type config_type,
++			       u8 e_rf_path);
++
++enum hal_status
++odm_config_bb_with_header_file(struct dm_struct *dm,
++			       enum odm_bb_config_type config_type);
++
++enum hal_status
++odm_config_mac_with_header_file(struct dm_struct *dm);
++
++u32 odm_get_hw_img_version(struct dm_struct *dm);
++
++u32 query_phydm_trx_capability(struct dm_struct *dm);
++
++u32 query_phydm_stbc_capability(struct dm_struct *dm);
++
++u32 query_phydm_ldpc_capability(struct dm_struct *dm);
++
++u32 query_phydm_txbf_parameters(struct dm_struct *dm);
++
++u32 query_phydm_txbf_capability(struct dm_struct *dm);
++
++#endif /*@#ifndef	__HALHWOUTSRC_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_interface.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_interface.c
+new file mode 100644
+index 000000000..3bd586b38
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_interface.c
+@@ -0,0 +1,1472 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ ************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++/*@
++ * ODM IO Relative API.
++ */
++
++u8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	struct rtl8192cd_priv *priv = dm->priv;
++	return RTL_R8(reg_addr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
++
++	return rtl_read_byte(rtlpriv, reg_addr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	struct rtw_dev *rtwdev = dm->adapter;
++
++	return rtw_read8(rtwdev, reg_addr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	void *adapter = dm->adapter;
++	return rtw_read8(adapter, reg_addr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	return PlatformEFIORead1Byte(adapter, reg_addr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	void *adapter = dm->adapter;
++
++	return rtw_read8(adapter, reg_addr);
++#endif
++}
++
++u16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	struct rtl8192cd_priv *priv = dm->priv;
++	return RTL_R16(reg_addr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
++
++	return rtl_read_word(rtlpriv, reg_addr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	struct rtw_dev *rtwdev = dm->adapter;
++
++	return rtw_read16(rtwdev, reg_addr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	void *adapter = dm->adapter;
++	return rtw_read16(adapter, reg_addr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	return PlatformEFIORead2Byte(adapter, reg_addr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	void *adapter = dm->adapter;
++
++	return rtw_read16(adapter, reg_addr);
++#endif
++}
++
++u32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	struct rtl8192cd_priv *priv = dm->priv;
++	return RTL_R32(reg_addr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
++
++	return rtl_read_dword(rtlpriv, reg_addr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	struct rtw_dev *rtwdev = dm->adapter;
++
++	return rtw_read32(rtwdev, reg_addr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	void *adapter = dm->adapter;
++	return rtw_read32(adapter, reg_addr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	return PlatformEFIORead4Byte(adapter, reg_addr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	void *adapter = dm->adapter;
++
++	return rtw_read32(adapter, reg_addr);
++#endif
++}
++
++void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	struct rtl8192cd_priv *priv = dm->priv;
++	RTL_W8(reg_addr, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
++
++	rtl_write_byte(rtlpriv, reg_addr, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	struct rtw_dev *rtwdev = dm->adapter;
++
++	rtw_write8(rtwdev, reg_addr, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	void *adapter = dm->adapter;
++	rtw_write8(adapter, reg_addr, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	PlatformEFIOWrite1Byte(adapter, reg_addr, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	void *adapter = dm->adapter;
++
++	rtw_write8(adapter, reg_addr, data);
++#endif
++
++	if (dm->en_reg_mntr_byte)
++		pr_debug("1byte:addr=0x%x, data=0x%x\n", reg_addr, data);
++}
++
++void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	struct rtl8192cd_priv *priv = dm->priv;
++	RTL_W16(reg_addr, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
++
++	rtl_write_word(rtlpriv, reg_addr, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	struct rtw_dev *rtwdev = dm->adapter;
++
++	rtw_write16(rtwdev, reg_addr, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	void *adapter = dm->adapter;
++	rtw_write16(adapter, reg_addr, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	PlatformEFIOWrite2Byte(adapter, reg_addr, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	void *adapter = dm->adapter;
++
++	rtw_write16(adapter, reg_addr, data);
++#endif
++
++	if (dm->en_reg_mntr_byte)
++		pr_debug("2byte:addr=0x%x, data=0x%x\n", reg_addr, data);
++}
++
++void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	struct rtl8192cd_priv *priv = dm->priv;
++	RTL_W32(reg_addr, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
++
++	rtl_write_dword(rtlpriv, reg_addr, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	struct rtw_dev *rtwdev = dm->adapter;
++
++	rtw_write32(rtwdev, reg_addr, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	void *adapter = dm->adapter;
++	rtw_write32(adapter, reg_addr, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	PlatformEFIOWrite4Byte(adapter, reg_addr, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	void *adapter = dm->adapter;
++
++	rtw_write32(adapter, reg_addr, data);
++#endif
++
++	if (dm->en_reg_mntr_byte)
++		pr_debug("4byte:addr=0x%x, data=0x%x\n", reg_addr, data);
++}
++
++void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	phy_set_bb_reg(dm->priv, reg_addr, bit_mask, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	PHY_SetBBReg(adapter, reg_addr, bit_mask, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
++
++	rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	struct rtw_dev *rtwdev = dm->adapter;
++
++	rtw_set_reg_with_mask(rtwdev, reg_addr, bit_mask, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
++#else
++	phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
++#endif
++
++	if (dm->en_reg_mntr_mac)
++		pr_debug("MAC:addr=0x%x, mask=0x%x, data=0x%x\n",
++			 reg_addr, bit_mask, data);
++}
++
++u32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	return phy_query_bb_reg(dm->priv, reg_addr, bit_mask);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	return PHY_QueryMacReg(dm->adapter, reg_addr, bit_mask);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
++
++	return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	struct rtw_dev *rtwdev = dm->adapter;
++
++	return rtw_get_reg_with_mask(rtwdev, reg_addr, bit_mask);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);
++#else
++	return phy_query_mac_reg(dm->adapter, reg_addr, bit_mask);
++#endif
++}
++
++void odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	phy_set_bb_reg(dm->priv, reg_addr, bit_mask, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	PHY_SetBBReg(adapter, reg_addr, bit_mask, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
++
++	rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	struct rtw_dev *rtwdev = dm->adapter;
++
++	rtw_set_reg_with_mask(rtwdev, reg_addr, bit_mask, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
++#else
++	phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
++#endif
++
++	if (dm->en_reg_mntr_bb)
++		pr_debug("BB:addr=0x%x, mask=0x%x, data=0x%x\n",
++			 reg_addr, bit_mask, data);
++}
++
++u32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	return phy_query_bb_reg(dm->priv, reg_addr, bit_mask);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	return PHY_QueryBBReg(adapter, reg_addr, bit_mask);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
++
++	return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	struct rtw_dev *rtwdev = dm->adapter;
++
++	return rtw_get_reg_with_mask(rtwdev, reg_addr, bit_mask);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);
++#else
++	return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);
++#endif
++}
++
++void odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
++		    u32 bit_mask, u32 data)
++{
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	phy_set_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	PHY_SetRFReg(adapter, e_rf_path, reg_addr, bit_mask, data);
++	ODM_delay_us(2);
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
++
++	rtl_set_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	struct rtw_dev *rtwdev = dm->adapter;
++
++	rtw_write_rf(rtwdev, e_rf_path, reg_addr, bit_mask, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	phy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	phy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data);
++	ODM_delay_us(2);
++#endif
++
++	if (dm->en_reg_mntr_rf)
++		pr_debug("RF:path=0x%x, addr=0x%x, mask=0x%x, data=0x%x\n",
++			 e_rf_path, reg_addr, bit_mask, data);
++}
++
++u32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
++		   u32 bit_mask)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	return phy_query_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, 1);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	return PHY_QueryRFReg(adapter, e_rf_path, reg_addr, bit_mask);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
++
++	return rtl_get_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	struct rtw_dev *rtwdev = dm->adapter;
++
++	return rtw_read_rf(rtwdev, e_rf_path, reg_addr, bit_mask);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	return phy_query_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask);
++#else
++	return phy_query_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask);
++#endif
++}
++
++enum hal_status
++phydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type,
++		    u32 offset, u32 data, u32 mask, enum rf_path e_rf_path,
++		    u32 delay_time)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++	return HAL_MAC_Config_PHY_WriteNByte(dm,
++					     config_type,
++					     offset,
++					     data,
++					     mask,
++					     e_rf_path,
++					     delay_time);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	return -ENOTSUPP;
++#else
++	return rtw_phydm_cfg_phy_para(dm,
++				      config_type,
++				      offset,
++				      data,
++				      mask,
++				      e_rf_path,
++				      delay_time);
++#endif
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
++#endif
++}
++
++/*@
++ * ODM Memory relative API.
++ */
++void odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	*ptr = kmalloc(length, GFP_ATOMIC);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	*ptr = kmalloc(length, GFP_ATOMIC);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	*ptr = kmalloc(length, GFP_ATOMIC);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	*ptr = rtw_zvmalloc(length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	PlatformAllocateMemory(adapter, ptr, length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	*ptr = rtw_zvmalloc(length);
++#endif
++}
++
++/* @length could be ignored, used to detect memory leakage. */
++void odm_free_memory(struct dm_struct *dm, void *ptr, u32 length)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	kfree(ptr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	kfree(ptr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	kfree(ptr);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	rtw_vmfree(ptr, length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	/* struct void*    adapter = dm->adapter; */
++	PlatformFreeMemory(ptr, length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	rtw_vmfree(ptr, length);
++#endif
++}
++
++void odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length)
++{
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	memcpy(dest, src, length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	memcpy(dest, src, length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	memcpy(dest, src, length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	_rtw_memcpy(dest, src, length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	PlatformMoveMemory(dest, src, length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	rtw_memcpy(dest, src, length);
++#endif
++}
++
++void odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length)
++{
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	memset(pbuf, value, length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	memset(pbuf, value, length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	memset(pbuf, value, length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	_rtw_memset(pbuf, value, length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	PlatformFillMemory(pbuf, length, value);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	rtw_memset(pbuf, value, length);
++#endif
++}
++
++s32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2, u32 length)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	return memcmp(buf1, buf2, length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	return memcmp(buf1, buf2, length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	return memcmp(buf1, buf2, length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	return _rtw_memcmp(buf1, buf2, length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	return PlatformCompareMemory(buf1, buf2, length);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	return rtw_memcmp(buf1, buf2, length);
++#endif
++}
++
++/*@
++ * ODM MISC relative API.
++ */
++void odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
++
++	rtl_odm_acquirespinlock(rtlpriv, type);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	struct rtw_dev *rtwdev = dm->adapter;
++
++	spin_lock(&rtwdev->hal.dm_lock);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	void *adapter = dm->adapter;
++	rtw_odm_acquirespinlock(adapter, type);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	PlatformAcquireSpinLock(adapter, type);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	void *adapter = dm->adapter;
++
++	rtw_odm_acquirespinlock(adapter, type);
++#endif
++}
++
++void odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
++
++	rtl_odm_releasespinlock(rtlpriv, type);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	struct rtw_dev *rtwdev = dm->adapter;
++
++	spin_unlock(&rtwdev->hal.dm_lock);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	void *adapter = dm->adapter;
++	rtw_odm_releasespinlock(adapter, type);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	PlatformReleaseSpinLock(adapter, type);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	void *adapter = dm->adapter;
++
++	rtw_odm_releasespinlock(adapter, type);
++#endif
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++/*@
++ * Work item relative API. FOr MP driver only~!
++ *   */
++void odm_initialize_work_item(
++	struct dm_struct *dm,
++	PRT_WORK_ITEM work_item,
++	RT_WORKITEM_CALL_BACK callback,
++	void *context,
++	const char *id)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	PlatformInitializeWorkItem(adapter, work_item, callback, context, id);
++#endif
++}
++
++void odm_start_work_item(
++	PRT_WORK_ITEM p_rt_work_item)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	PlatformStartWorkItem(p_rt_work_item);
++#endif
++}
++
++void odm_stop_work_item(
++	PRT_WORK_ITEM p_rt_work_item)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	PlatformStopWorkItem(p_rt_work_item);
++#endif
++}
++
++void odm_free_work_item(
++	PRT_WORK_ITEM p_rt_work_item)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	PlatformFreeWorkItem(p_rt_work_item);
++#endif
++}
++
++void odm_schedule_work_item(
++	PRT_WORK_ITEM p_rt_work_item)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	PlatformScheduleWorkItem(p_rt_work_item);
++#endif
++}
++
++boolean
++odm_is_work_item_scheduled(
++	PRT_WORK_ITEM p_rt_work_item)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	return PlatformIsWorkItemScheduled(p_rt_work_item);
++#endif
++}
++#endif
++
++/*@
++ * ODM Timer relative API.
++ */
++
++void ODM_delay_ms(u32 ms)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	delay_ms(ms);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	mdelay(ms);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	mdelay(ms);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	rtw_mdelay_os(ms);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	delay_ms(ms);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	rtw_mdelay_os(ms);
++#endif
++}
++
++void ODM_delay_us(u32 us)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	delay_us(us);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	udelay(us);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	udelay(us);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	rtw_udelay_os(us);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	PlatformStallExecution(us);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	rtw_udelay_os(us);
++#endif
++}
++
++void ODM_sleep_ms(u32 ms)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	delay_ms(ms);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	msleep(ms);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	msleep(ms);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	rtw_msleep_os(ms);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	delay_ms(ms);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	rtw_msleep_os(ms);
++#endif
++}
++
++void ODM_sleep_us(u32 us)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	delay_us(us);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	usleep_range(us, us + 1);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	usleep_range(us, us + 1);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	rtw_usleep_os(us);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	PlatformStallExecution(us);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	rtw_usleep_os(us);
++#endif
++}
++
++void odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
++		   u32 ms_delay)
++{
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	mod_timer(timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(ms_delay));
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	mod_timer(timer, jiffies + msecs_to_jiffies(ms_delay));
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	mod_timer(&timer->timer, jiffies + msecs_to_jiffies(ms_delay));
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	_set_timer(timer, ms_delay); /* @ms */
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	PlatformSetTimer(adapter, timer, ms_delay);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	rtw_set_timer(timer, ms_delay); /* @ms */
++#endif
++}
++
++void odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
++			  void *call_back_func, void *context,
++			  const char *sz_id)
++{
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	init_timer(timer);
++	timer->function = call_back_func;
++	timer->data = (unsigned long)dm;
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	timer_setup(timer, call_back_func, 0);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	struct _ADAPTER *adapter = dm->adapter;
++
++	_init_timer(timer, adapter->pnetdev, call_back_func, dm);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++
++	PlatformInitializeTimer(adapter, timer, (RT_TIMER_CALL_BACK)call_back_func, context, sz_id);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	struct _ADAPTER *adapter = dm->adapter;
++
++	rtw_init_timer(timer, adapter->pnetdev, (TIMER_FUN)call_back_func, dm, NULL);
++#endif
++}
++
++void odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer)
++{
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	del_timer(timer);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	del_timer(timer);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	del_timer(&timer->timer);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	_cancel_timer_ex(timer);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	PlatformCancelTimer(adapter, timer);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	rtw_cancel_timer(timer);
++#endif
++}
++
++void odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++
++	void *adapter = dm->adapter;
++
++	/* @<20120301, Kordan> If the initilization fails,
++	 * InitializeAdapterXxx will return regardless of InitHalDm.
++	 * Hence, uninitialized timers cause BSOD when the driver
++	 * releases resources since the init fail.
++	 */
++	if (timer == 0) {
++		PHYDM_DBG(dm, ODM_COMP_INIT,
++			  "[%s] Timer is NULL! Please check!\n", __func__);
++		return;
++	}
++
++	PlatformReleaseTimer(adapter, timer);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	rtw_del_timer(timer);
++#endif
++}
++
++u8 phydm_trans_h2c_id(struct dm_struct *dm, u8 phydm_h2c_id)
++{
++	u8 platform_h2c_id = phydm_h2c_id;
++
++	switch (phydm_h2c_id) {
++	/* @1 [0] */
++	case ODM_H2C_RSSI_REPORT:
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++		#if (RTL8188E_SUPPORT == 1)
++		if (dm->support_ic_type == ODM_RTL8188E)
++			platform_h2c_id = H2C_88E_RSSI_REPORT;
++		else
++		#endif
++			platform_h2c_id = H2C_RSSI_REPORT;
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++		platform_h2c_id = H2C_RSSI_SETTING;
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
++#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
++		if (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES)
++			platform_h2c_id = H2C_88XX_RSSI_REPORT;
++		else
++#endif
++#if (RTL8812A_SUPPORT == 1)
++			if (dm->support_ic_type == ODM_RTL8812)
++			platform_h2c_id = H2C_8812_RSSI_REPORT;
++		else
++#endif
++		{
++		}
++#endif
++
++		break;
++
++	/* @1 [3] */
++	case ODM_H2C_WIFI_CALIBRATION:
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++		platform_h2c_id = H2C_WIFI_CALIBRATION;
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++#if (RTL8723B_SUPPORT == 1)
++		platform_h2c_id = H2C_8723B_BT_WLAN_CALIBRATION;
++#endif
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
++#endif
++		break;
++
++	/* @1 [4] */
++	case ODM_H2C_IQ_CALIBRATION:
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++		platform_h2c_id = H2C_IQ_CALIBRATION;
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
++		platform_h2c_id = H2C_8812_IQ_CALIBRATION;
++#endif
++#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
++#endif
++
++		break;
++	/* @1 [5] */
++	case ODM_H2C_RA_PARA_ADJUST:
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++		platform_h2c_id = H2C_RA_PARA_ADJUST;
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
++		platform_h2c_id = H2C_8812_RA_PARA_ADJUST;
++#elif ((RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1))
++		platform_h2c_id = H2C_RA_PARA_ADJUST;
++#elif (RTL8192E_SUPPORT == 1)
++		platform_h2c_id = H2C_8192E_RA_PARA_ADJUST;
++#elif (RTL8723B_SUPPORT == 1)
++		platform_h2c_id = H2C_8723B_RA_PARA_ADJUST;
++#endif
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
++#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
++		if (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES)
++			platform_h2c_id = H2C_88XX_RA_PARA_ADJUST;
++		else
++#endif
++#if (RTL8812A_SUPPORT == 1)
++			if (dm->support_ic_type == ODM_RTL8812)
++			platform_h2c_id = H2C_8812_RA_PARA_ADJUST;
++		else
++#endif
++		{
++		}
++#endif
++
++		break;
++
++	/* @1 [6] */
++	case PHYDM_H2C_DYNAMIC_TX_PATH:
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	#if (RTL8814A_SUPPORT == 1)
++		if (dm->support_ic_type == ODM_RTL8814A)
++			platform_h2c_id = H2C_8814A_DYNAMIC_TX_PATH;
++	#endif
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++#if (RTL8814A_SUPPORT == 1)
++		if (dm->support_ic_type == ODM_RTL8814A)
++			platform_h2c_id = H2C_DYNAMIC_TX_PATH;
++#endif
++#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
++#if (RTL8814A_SUPPORT == 1)
++		if (dm->support_ic_type == ODM_RTL8814A)
++			platform_h2c_id = H2C_88XX_DYNAMIC_TX_PATH;
++#endif
++
++#endif
++
++		break;
++
++	/* @[7]*/
++	case PHYDM_H2C_FW_TRACE_EN:
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++
++		platform_h2c_id = H2C_FW_TRACE_EN;
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++
++		platform_h2c_id = 0x49;
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
++#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
++		if (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES)
++			platform_h2c_id = H2C_88XX_FW_TRACE_EN;
++		else
++#endif
++#if (RTL8812A_SUPPORT == 1)
++		if (dm->support_ic_type == ODM_RTL8812)
++			platform_h2c_id = H2C_8812_FW_TRACE_EN;
++		else
++#endif
++		{
++		}
++
++#endif
++
++		break;
++
++	case PHYDM_H2C_TXBF:
++#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1))
++		platform_h2c_id = 0x41; /*@H2C_TxBF*/
++#endif
++		break;
++
++	case PHYDM_H2C_MU:
++#if (RTL8822B_SUPPORT == 1)
++		platform_h2c_id = 0x4a; /*@H2C_MU*/
++#endif
++		break;
++
++	default:
++		platform_h2c_id = phydm_h2c_id;
++		break;
++	}
++
++	return platform_h2c_id;
++}
++
++/*@ODM FW relative API.*/
++
++void odm_fill_h2c_cmd(struct dm_struct *dm, u8 phydm_h2c_id, u32 cmd_len,
++		      u8 *cmd_buf)
++{
++#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	struct rtw_dev *rtwdev = dm->adapter;
++	u8 cmd_id, cmd_class;
++	u8 h2c_pkt[8];
++#else
++	void *adapter = dm->adapter;
++#endif
++	u8 h2c_id = phydm_trans_h2c_id(dm, phydm_h2c_id);
++
++	PHYDM_DBG(dm, DBG_RA, "[H2C]  h2c_id=((0x%x))\n", h2c_id);
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	if (dm->support_ic_type == ODM_RTL8188E) {
++		if (!dm->ra_support88e)
++			FillH2CCmd88E(adapter, h2c_id, cmd_len, cmd_buf);
++	} else if (dm->support_ic_type == ODM_RTL8814A)
++		FillH2CCmd8814A(adapter, h2c_id, cmd_len, cmd_buf);
++	else if (dm->support_ic_type == ODM_RTL8822B)
++		FillH2CCmd8822B(adapter, h2c_id, cmd_len, cmd_buf);
++	else
++		FillH2CCmd(adapter, h2c_id, cmd_len, cmd_buf);
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++
++	#ifdef DM_ODM_CE_MAC80211
++	rtlpriv->cfg->ops->fill_h2c_cmd(rtlpriv->hw, h2c_id, cmd_len, cmd_buf);
++	#elif defined(DM_ODM_CE_MAC80211_V2)
++	cmd_id = phydm_h2c_id & 0x1f;
++	cmd_class = (phydm_h2c_id >> RTW_H2C_CLASS_OFFSET) & 0x7;
++	memcpy(h2c_pkt + 1, cmd_buf, 7);
++	h2c_pkt[0] = phydm_h2c_id;
++	rtw_fw_send_h2c_packet(rtwdev, h2c_pkt, cmd_id, cmd_class);
++	/* TODO: implement fill h2c command for rtwlan */
++	#else
++	rtw_hal_fill_h2c_cmd(adapter, h2c_id, cmd_len, cmd_buf);
++	#endif
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
++
++	#if (RTL8812A_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8812) {
++		fill_h2c_cmd8812(dm->priv, h2c_id, cmd_len, cmd_buf);
++	} else
++	#endif
++	{
++		GET_HAL_INTERFACE(dm->priv)->fill_h2c_cmd_handler(dm->priv, h2c_id, cmd_len, cmd_buf);
++	}
++
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	rtw_hal_fill_h2c_cmd(adapter, h2c_id, cmd_len, cmd_buf);
++
++#endif
++}
++
++u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,
++			     u8 *tmp_buf)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter = dm->adapter;
++#endif
++	u8 extend_c2h_sub_id = 0;
++	u8 find_c2h_cmd = true;
++
++	if (c2h_cmd_len > 12 || c2h_cmd_len == 0) {
++		pr_debug("[Warning] Error C2H ID=%d, len=%d\n",
++			 c2h_cmd_id, c2h_cmd_len);
++
++		find_c2h_cmd = false;
++		return find_c2h_cmd;
++	}
++
++	switch (c2h_cmd_id) {
++	case PHYDM_C2H_DBG:
++		phydm_fw_trace_handler(dm, tmp_buf, c2h_cmd_len);
++		break;
++
++	case PHYDM_C2H_RA_RPT:
++		phydm_c2h_ra_report_handler(dm, tmp_buf, c2h_cmd_len);
++		break;
++
++	case PHYDM_C2H_RA_PARA_RPT:
++		odm_c2h_ra_para_report_handler(dm, tmp_buf, c2h_cmd_len);
++		break;
++#ifdef CONFIG_PATH_DIVERSITY
++	case PHYDM_C2H_DYNAMIC_TX_PATH_RPT:
++		if (dm->support_ic_type & (ODM_RTL8814A))
++			phydm_c2h_dtp_handler(dm, tmp_buf, c2h_cmd_len);
++		break;
++#endif
++
++	case PHYDM_C2H_IQK_FINISH:
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++
++		if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) {
++			RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Finish ==\n"));
++			odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
++			dm->rf_calibrate_info.is_iqk_in_progress = false;
++			odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
++			dm->rf_calibrate_info.iqk_progressing_time = 0;
++			dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time);
++		}
++
++#endif
++		break;
++
++	case PHYDM_C2H_CLM_MONITOR:
++		phydm_clm_c2h_report_handler(dm, tmp_buf, c2h_cmd_len);
++		break;
++
++	case PHYDM_C2H_DBG_CODE:
++		phydm_fw_trace_handler_code(dm, tmp_buf, c2h_cmd_len);
++		break;
++
++	case PHYDM_C2H_EXTEND:
++		extend_c2h_sub_id = tmp_buf[0];
++		if (extend_c2h_sub_id == PHYDM_EXTEND_C2H_DBG_PRINT)
++			phydm_fw_trace_handler_8051(dm, tmp_buf, c2h_cmd_len);
++
++		break;
++
++	default:
++		find_c2h_cmd = false;
++		break;
++	}
++
++	return find_c2h_cmd;
++}
++
++u64 odm_get_current_time(struct dm_struct *dm)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	return (u64)rtw_get_current_time();
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	return jiffies;
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	return jiffies;
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	return rtw_get_current_time();
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	return PlatformGetCurrentTime();
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	return rtw_get_current_time();
++#endif
++}
++
++u64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	return rtw_get_passing_time_ms((u32)start_time);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	return jiffies_to_msecs(jiffies - start_time);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	return jiffies_to_msecs(jiffies - start_time);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	return rtw_get_passing_time_ms((systime)start_time);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	return ((PlatformGetCurrentTime() - start_time) >> 10);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	return rtw_get_passing_time_ms(start_time);
++#endif
++}
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \
++	(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
++
++void phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 RegName,
++					u8 *val)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	struct _ADAPTER *adapter = dm->adapter;
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	((PADAPTER)adapter)->HalFunc.SetHwRegHandler(adapter, RegName, val);
++#else
++	adapter->hal_func.set_hw_reg_handler(adapter, RegName, val);
++#endif
++
++#endif
++}
++
++void phydm_get_hal_def_var_handler_interface(struct dm_struct *dm,
++					     enum _HAL_DEF_VARIABLE e_variable,
++					     void *value)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	struct _ADAPTER *adapter = dm->adapter;
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	((PADAPTER)adapter)->HalFunc.GetHalDefVarHandler(adapter, e_variable, value);
++#else
++	adapter->hal_func.get_hal_def_var_handler(adapter, e_variable, value);
++#endif
++
++#endif
++}
++
++#endif
++
++void odm_set_tx_power_index_by_rate_section(struct dm_struct *dm,
++					    enum rf_path path, u8 ch,
++					    u8 section)
++{
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++	PHY_SetTxPowerIndexByRateSection(adapter, path, ch, section);
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	void *adapter = dm->adapter;
++
++	phy_set_tx_power_index_by_rs(adapter, ch, path, section);
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	phy_set_tx_power_index_by_rate_section(dm->adapter, path, ch, section);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	void *adapter = dm->adapter;
++
++	PHY_SetTxPowerIndexByRateSection(adapter, path, ch, section);
++#endif
++}
++
++u8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 rate,
++			  u8 bw, u8 ch)
++{
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++
++	return PHY_GetTxPowerIndex(dm->adapter, path, rate, (CHANNEL_WIDTH)bw, ch);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	void *adapter = dm->adapter;
++
++	return phy_get_tx_power_index(adapter, path, rate, bw, ch);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	void *adapter = dm->adapter;
++
++	return phy_get_tx_power_index(adapter, path, rate, bw, ch);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	return phy_get_tx_power_index(dm->adapter, path, rate, bw, ch);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	void *adapter = dm->adapter;
++
++	return PHY_GetTxPowerIndex(dm->adapter, path, rate, bw, ch);
++#endif
++}
++
++u8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data,
++			   boolean b_pseu_do_test)
++{
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++
++	return (u8)EFUSE_OneByteRead(adapter, addr, data, b_pseu_do_test);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	void *adapter = dm->adapter;
++
++	return rtl_efuse_onebyte_read(adapter, addr, data, b_pseu_do_test);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++	return -1;
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	return efuse_onebyte_read(dm->adapter, addr, data, b_pseu_do_test);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
++	return Efuse_OneByteRead(dm, addr, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	void *adapter = dm->adapter;
++
++	return (u8)efuse_OneByteRead(adapter, addr, data, b_pseu_do_test);
++#endif
++}
++
++void odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset,
++				u32 *data)
++{
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	void *adapter = dm->adapter;
++
++	EFUSE_ShadowRead(adapter, type, offset, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	void *adapter = dm->adapter;
++
++	rtl_efuse_logical_map_read(adapter, type, offset, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	efuse_logical_map_read(dm->adapter, type, offset, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	void *adapter = dm->adapter;
++
++	EFUSE_ShadowRead(adapter, type, offset, data);
++#endif
++}
++
++enum hal_status
++odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment)
++{
++	enum hal_status iqk_result = HAL_STATUS_FAILURE;
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	struct _ADAPTER *adapter = dm->adapter;
++
++	if (HAL_MAC_FWIQK_Trigger(&GET_HAL_MAC_INFO(adapter), clear, segment) == 0)
++		iqk_result = HAL_STATUS_SUCCESS;
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	void *adapter = dm->adapter;
++
++	iqk_result = rtl_phydm_fw_iqk(adapter, clear, segment);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++#else
++	iqk_result = rtw_phydm_fw_iqk(dm, clear, segment);
++#endif
++#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
++	iqk_result = rtw_phydm_fw_iqk(dm, clear, segment);
++#endif
++	return iqk_result;
++}
++
++enum hal_status
++odm_dpk_by_fw(struct dm_struct *dm)
++{
++	enum hal_status dpk_result = HAL_STATUS_FAILURE;
++#if 0
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	struct _ADAPTER *adapter = dm->adapter;
++
++	if (hal_mac_fwdpk_trigger(&GET_HAL_MAC_INFO(adapter)) == 0)
++		dpk_result = HAL_STATUS_SUCCESS;
++#else
++	dpk_result = rtw_phydm_fw_dpk(dm);
++#endif
++
++#endif
++	return dpk_result;
++}
++
++void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 mac_id,
++			     struct cmn_sta_info *pcmn_sta_info)
++{
++	dm->phydm_sta_info[mac_id] = pcmn_sta_info;
++
++	if (is_sta_active(pcmn_sta_info))
++		dm->phydm_macid_table[pcmn_sta_info->mac_id] = mac_id;
++}
++
++void phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx,
++			       struct cmn_sta_info *pcmn_sta_info)
++{
++	if (is_sta_active(pcmn_sta_info))
++		dm->phydm_macid_table[pcmn_sta_info->mac_id] = entry_idx;
++}
++
++void phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++
++	struct rtl8192cd_priv *priv = dm->priv;
++
++	#if IS_EXIST_PCI || IS_EXIST_EMBEDDED
++	if (dm->support_interface == ODM_ITRF_PCIE)
++		GET_HAL_INTERFACE(priv)->AddInterruptMaskHandler(priv,
++								 interrupt_type)
++								 ;
++	#endif
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++#endif
++}
++
++void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++
++	struct rtl8192cd_priv *priv = dm->priv;
++
++	#if IS_EXIST_PCI || IS_EXIST_EMBEDDED
++	if (dm->support_interface == ODM_ITRF_PCIE)
++		GET_HAL_INTERFACE(priv)->EnableRxRelatedInterruptHandler(priv);
++	#endif
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++#endif
++}
++
++void phydm_iqk_wait(struct dm_struct *dm, u32 timeout)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++#else
++	void *adapter = dm->adapter;
++
++	rtl8812_iqk_wait(adapter, timeout);
++#endif
++#endif
++}
++
++u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
++	return HwRateToMRate(rate);
++#endif
++	return 0;
++}
++
++void phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
++	ROM_odm_SetCrystalCap(dm, crystal_cap);
++#endif
++}
++
++void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *),
++			     void *context)
++{
++#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++	PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	void *adapter = dm->adapter;
++
++	rtw_run_in_thread_cmd(adapter, func, context);
++#endif
++}
++
++u8 phydm_get_tx_rate(struct dm_struct *dm)
++{
++	struct _hal_rf_ *rf = &dm->rf_table;
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	struct _ADAPTER *adapter = dm->adapter;
++#endif
++	u8 tx_rate = 0xff;
++	u8 mpt_rate_index = 0;
++
++	if (*dm->mp_mode == 1) {
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++#if (MP_DRIVER == 1)
++		PMPT_CONTEXT p_mpt_ctx = &adapter->MptCtx;
++
++		tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
++#endif
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++#ifdef CONFIG_MP_INCLUDED
++		if (rf->mp_rate_index)
++			mpt_rate_index = *rf->mp_rate_index;
++
++		tx_rate = mpt_to_mgnt_rate(mpt_rate_index);
++#endif
++#endif
++#endif
++	} else {
++		u16 rate = *dm->forced_data_rate;
++
++		if (!rate) { /*auto rate*/
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++			struct _ADAPTER *adapter = dm->adapter;
++
++			tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
++			tx_rate = dm->tx_rate;
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++			if (dm->number_linked_client != 0)
++				tx_rate = hw_rate_to_m_rate(dm->tx_rate);
++			else
++				tx_rate = rf->p_rate_index;
++#endif
++		} else { /*force rate*/
++			tx_rate = (u8)rate;
++		}
++	}
++
++	return tx_rate;
++}
++
++u8 phydm_get_tx_power_dbm(struct dm_struct *dm, u8 rf_path,
++					u8 rate, u8 bandwidth, u8 channel)
++{
++	u8 tx_power_dbm = 0;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct _ADAPTER *adapter = dm->adapter;
++	tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValue(adapter, rf_path, rate, bandwidth, channel);
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	tx_power_dbm = phy_get_tx_power_final_absolute_value(dm->adapter, rf_path, rate, bandwidth, channel);
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValue(dm, rf_path, rate, bandwidth, channel);
++#endif
++	return tx_power_dbm;
++}
++
++s16 phydm_get_tx_power_mdbm(struct dm_struct *dm, u8 rf_path,
++					u8 rate, u8 bandwidth, u8 channel)
++{
++	s16 tx_power_dbm = 0;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct _ADAPTER *adapter = dm->adapter;
++	tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValuemdBm(adapter, rf_path, rate, bandwidth, channel);
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	tx_power_dbm = rtw_odm_get_tx_power_mbm(dm, rf_path, rate, bandwidth, channel);
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValuembm(dm, rf_path, rate, bandwidth, channel);
++#endif
++	return tx_power_dbm;
++}
++
++
++u64 phydm_division64(u64 x, u64 y)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	do_div(x, y); 
++	return x;
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	return x / y;
++#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	return rtw_division64(x, y);
++#endif
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_interface.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_interface.h
+new file mode 100644
+index 000000000..6f2b05310
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_interface.h
+@@ -0,0 +1,326 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __ODM_INTERFACE_H__
++#define __ODM_INTERFACE_H__
++
++#define INTERFACE_VERSION "1.2"
++
++#define pdm_set_reg odm_set_bb_reg
++
++/*@=========== Constant/Structure/Enum/... Define*/
++
++enum phydm_h2c_cmd {
++	PHYDM_H2C_RA_MASK		= 0x40,
++	PHYDM_H2C_TXBF			= 0x41,
++	ODM_H2C_RSSI_REPORT		= 0x42,
++	ODM_H2C_IQ_CALIBRATION		= 0x45,
++	PHYDM_RA_MASK_ABOVE_3SS		= 0x46,
++	ODM_H2C_RA_PARA_ADJUST		= 0x47,
++	PHYDM_H2C_DYNAMIC_TX_PATH	= 0x48,
++	PHYDM_H2C_FW_TRACE_EN		= 0x49,
++	ODM_H2C_WIFI_CALIBRATION	= 0x6d,
++	PHYDM_H2C_MU			= 0x4a,
++	PHYDM_H2C_FW_GENERAL_INIT	= 0x4c,
++	PHYDM_H2C_FW_CLM_MNTR		= 0x4d,
++	PHYDM_H2C_MCC			= 0x4f,
++	PHYDM_H2C_RESP_TX_PATH_CTRL	= 0x50,
++	PHYDM_H2C_RESP_TX_ANT_CTRL	= 0x51,
++	PHYDM_H2C_FW_DM_CTRL		= 0x55,
++	ODM_MAX_H2CCMD
++};
++
++enum phydm_c2h_evt {
++	PHYDM_C2H_DBG =		0,
++	PHYDM_C2H_LB =		1,
++	PHYDM_C2H_XBF =		2,
++	PHYDM_C2H_TX_REPORT =	3,
++	PHYDM_C2H_INFO =	9,
++	PHYDM_C2H_BT_MP =	11,
++	PHYDM_C2H_RA_RPT =	12,
++	PHYDM_C2H_RA_PARA_RPT = 14,
++	PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15,
++	PHYDM_C2H_IQK_FINISH =	17, /*@0x11*/
++	PHYDM_C2H_CLM_MONITOR =	0x2a,
++	PHYDM_C2H_DBG_CODE =	0xFE,
++	PHYDM_C2H_EXTEND =	0xFF,
++};
++
++enum phydm_extend_c2h_evt {
++	PHYDM_EXTEND_C2H_DBG_PRINT = 0
++
++};
++
++enum phydm_halmac_param {
++	PHYDM_HALMAC_CMD_MAC_W8 = 0,
++	PHYDM_HALMAC_CMD_MAC_W16 = 1,
++	PHYDM_HALMAC_CMD_MAC_W32 = 2,
++	PHYDM_HALMAC_CMD_BB_W8,
++	PHYDM_HALMAC_CMD_BB_W16,
++	PHYDM_HALMAC_CMD_BB_W32,
++	PHYDM_HALMAC_CMD_RF_W,
++	PHYDM_HALMAC_CMD_DELAY_US,
++	PHYDM_HALMAC_CMD_DELAY_MS,
++	PHYDM_HALMAC_CMD_END = 0XFF,
++};
++
++/*@=========== Macro Define*/
++
++#define _reg_all(_name)			ODM_##_name
++#define _reg_ic(_name, _ic)		ODM_##_name##_ic
++#define _bit_all(_name)			BIT_##_name
++#define _bit_ic(_name, _ic)		BIT_##_name##_ic
++
++#if defined(DM_ODM_CE_MAC80211)
++#define ODM_BIT(name, dm)				\
++	((dm->support_ic_type & ODM_IC_11N_SERIES) ?	\
++	 ODM_BIT_##name##_11N : ODM_BIT_##name##_11AC)
++
++#define ODM_REG(name, dm)				\
++	((dm->support_ic_type & ODM_IC_11N_SERIES) ?	\
++	 ODM_REG_##name##_11N : ODM_REG_##name##_11AC)
++#else
++#define _reg_11N(_name)			ODM_REG_##_name##_11N
++#define _reg_11AC(_name)		ODM_REG_##_name##_11AC
++#define _bit_11N(_name)			ODM_BIT_##_name##_11N
++#define _bit_11AC(_name)		ODM_BIT_##_name##_11AC
++
++#ifdef __ECOS
++#define _rtk_cat(_name, _ic_type, _func)                                \
++	(                                                               \
++		((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
++						   _func##_11AC(_name))
++#else
++
++#define _cat(_name, _ic_type, _func)                                    \
++	(                                                               \
++		((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
++						   _func##_11AC(_name))
++#endif
++/*@
++ * only sample code
++ *#define _cat(_name, _ic_type, _func)					\
++ *	(								\
++ *		((_ic_type) & ODM_RTL8188E) ? _func##_ic(_name, _8188E) :\
++ *		_func##_ic(_name, _8195)				\
++ *	)
++ */
++
++/* @_name: name of register or bit.
++ * Example: "ODM_REG(R_A_AGC_CORE1, dm)"
++ * gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C",
++ * depends on support_ic_type.
++ */
++#ifdef __ECOS
++	#define ODM_REG(_name, _pdm_odm)	\
++		_rtk_cat(_name, _pdm_odm->support_ic_type, _reg)
++	#define ODM_BIT(_name, _pdm_odm)	\
++		_rtk_cat(_name, _pdm_odm->support_ic_type, _bit)
++#else
++	#define ODM_REG(_name, _pdm_odm)	\
++		_cat(_name, _pdm_odm->support_ic_type, _reg)
++	#define ODM_BIT(_name, _pdm_odm)	\
++		_cat(_name, _pdm_odm->support_ic_type, _bit)
++#endif
++
++#endif
++/*@
++ * =========== Extern Variable ??? It should be forbidden.
++ */
++
++/*@
++ * =========== EXtern Function Prototype
++ */
++
++u8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr);
++
++u16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr);
++
++u32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr);
++
++void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data);
++
++void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data);
++
++void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data);
++
++void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask,
++		     u32 data);
++
++u32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask);
++
++void odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data);
++
++u32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask);
++
++void odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
++		    u32 bit_mask, u32 data);
++
++u32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
++		   u32 bit_mask);
++
++/*@
++ * Memory Relative Function.
++ */
++void odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length);
++void odm_free_memory(struct dm_struct *dm, void *ptr, u32 length);
++
++void odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length);
++
++s32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2,
++		       u32 length);
++
++void odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length);
++
++/*@
++ * ODM MISC-spin lock relative API.
++ */
++void odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type);
++
++void odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type);
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++/*@
++ * ODM MISC-workitem relative API.
++ */
++void odm_initialize_work_item(
++	struct dm_struct *dm,
++	PRT_WORK_ITEM p_rt_work_item,
++	RT_WORKITEM_CALL_BACK rt_work_item_callback,
++	void *context,
++	const char *sz_id);
++
++void odm_start_work_item(
++	PRT_WORK_ITEM p_rt_work_item);
++
++void odm_stop_work_item(
++	PRT_WORK_ITEM p_rt_work_item);
++
++void odm_free_work_item(
++	PRT_WORK_ITEM p_rt_work_item);
++
++void odm_schedule_work_item(
++	PRT_WORK_ITEM p_rt_work_item);
++
++boolean
++odm_is_work_item_scheduled(
++	PRT_WORK_ITEM p_rt_work_item);
++#endif
++
++/*@
++ * ODM Timer relative API.
++ */
++void ODM_delay_ms(u32 ms);
++
++void ODM_delay_us(u32 us);
++
++void ODM_sleep_ms(u32 ms);
++
++void ODM_sleep_us(u32 us);
++
++void odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
++		   u32 ms_delay);
++
++void odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
++			  void *call_back_func, void *context,
++			  const char *sz_id);
++
++void odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer);
++
++void odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer);
++
++/*ODM FW relative API.*/
++
++enum hal_status
++phydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type,
++		    u32 offset, u32 data, u32 mask, enum rf_path e_rf_path,
++		    u32 delay_time);
++
++void odm_fill_h2c_cmd(struct dm_struct *dm, u8 element_id, u32 cmd_len,
++		      u8 *cmd_buffer);
++
++u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,
++			     u8 *tmp_buf);
++
++u64 odm_get_current_time(struct dm_struct *dm);
++u64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time);
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \
++	(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
++
++void phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 reg_Name,
++					u8 *val);
++
++void phydm_get_hal_def_var_handler_interface(struct dm_struct *dm,
++					     enum _HAL_DEF_VARIABLE e_variable,
++					     void *value);
++
++#endif
++
++void odm_set_tx_power_index_by_rate_section(struct dm_struct *dm,
++					    enum rf_path path, u8 channel,
++					    u8 rate_section);
++
++u8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 tx_rate,
++			  u8 band_width, u8 channel);
++
++u8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data,
++			   boolean b_pseu_do_test);
++
++void odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset,
++				u32 *data);
++
++enum hal_status
++odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment);
++
++enum hal_status
++odm_dpk_by_fw(struct dm_struct *dm);
++
++void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 index,
++			     struct cmn_sta_info *pcmn_sta_info);
++
++void phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx,
++			       struct cmn_sta_info *pcmn_sta_info);
++
++void phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type);
++
++void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm);
++
++void phydm_iqk_wait(struct dm_struct *dm, u32 timeout);
++u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate);
++
++void phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap);
++void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *),
++			     void *context);
++u8 phydm_get_tx_rate(struct dm_struct *dm);
++u8 phydm_get_tx_power_dbm(struct dm_struct *dm, u8 rf_path,
++					u8 rate, u8 bandwidth, u8 channel);
++
++s16 phydm_get_tx_power_mdbm(struct dm_struct *dm, u8 rf_path,
++					u8 rate, u8 bandwidth, u8 channel);
++
++u64 phydm_division64(u64 x, u64 y);
++
++#endif /* @__ODM_INTERFACE_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_lna_sat.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_lna_sat.c
+new file mode 100644
+index 000000000..d258005ee
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_lna_sat.c
+@@ -0,0 +1,1335 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*************************************************************
++ * include files
++ * *************************************************************/
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++
++#ifdef PHYDM_LNA_SAT_CHK_TYPE1
++void phydm_lna_sat_chk_init(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
++
++	lna_info->check_time = 0;
++	lna_info->sat_cnt_acc_patha = 0;
++	lna_info->sat_cnt_acc_pathb = 0;
++	#ifdef PHYDM_IC_ABOVE_3SS
++	lna_info->sat_cnt_acc_pathc = 0;
++	#endif
++	#ifdef PHYDM_IC_ABOVE_4SS
++	lna_info->sat_cnt_acc_pathd = 0;
++	#endif
++	lna_info->cur_sat_status = 0;
++	lna_info->pre_sat_status = 0;
++	lna_info->cur_timer_check_cnt = 0;
++	lna_info->pre_timer_check_cnt = 0;
++
++	#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
++	if (dm->support_ic_type &
++	    (ODM_RTL8198F | ODM_RTL8814B))
++		phydm_lna_sat_chk_bb_init(dm);
++	#endif
++}
++
++#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
++void phydm_lna_sat_chk_bb_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;
++
++	boolean disable_bb_switch_tab = false;
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
++
++	/*@set table switch mux r_6table_sel_anten*/
++	odm_set_bb_reg(dm, 0x18ac, BIT(8), 0);
++
++	/*@tab decision when idle*/
++	odm_set_bb_reg(dm, 0x18ac, BIT(16), disable_bb_switch_tab);
++	odm_set_bb_reg(dm, 0x41ac, BIT(16), disable_bb_switch_tab);
++	odm_set_bb_reg(dm, 0x52ac, BIT(16), disable_bb_switch_tab);
++	odm_set_bb_reg(dm, 0x53ac, BIT(16), disable_bb_switch_tab);
++	/*@tab decision when ofdmcca*/
++	odm_set_bb_reg(dm, 0x18ac, BIT(17), disable_bb_switch_tab);
++	odm_set_bb_reg(dm, 0x41ac, BIT(17), disable_bb_switch_tab);
++	odm_set_bb_reg(dm, 0x52ac, BIT(17), disable_bb_switch_tab);
++	odm_set_bb_reg(dm, 0x53ac, BIT(17), disable_bb_switch_tab);
++}
++
++void phydm_set_ofdm_agc_tab_path(
++	void *dm_void,
++	u8 tab_sel,
++	enum rf_path path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
++	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) {
++		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "set AGC Tab%d\n", tab_sel);
++		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "r_6table_sel_anten = 0x%x\n",
++			  odm_get_bb_reg(dm, 0x18ac, BIT(8)));
++	}
++
++	if (dm->support_ic_type & ODM_RTL8198F) {
++		/*@table sel:0/2, mapping 2 to 1 */
++		if (tab_sel == OFDM_AGC_TAB_0) {
++			odm_set_bb_reg(dm, 0x18ac, BIT(4), 0);
++			odm_set_bb_reg(dm, 0x41ac, BIT(4), 0);
++			odm_set_bb_reg(dm, 0x52ac, BIT(4), 0);
++			odm_set_bb_reg(dm, 0x53ac, BIT(4), 0);
++		} else if (tab_sel == OFDM_AGC_TAB_2) {
++			odm_set_bb_reg(dm, 0x18ac, BIT(4), 1);
++			odm_set_bb_reg(dm, 0x41ac, BIT(4), 1);
++			odm_set_bb_reg(dm, 0x52ac, BIT(4), 1);
++			odm_set_bb_reg(dm, 0x53ac, BIT(4), 1);
++		} else {
++			odm_set_bb_reg(dm, 0x18ac, BIT(4), 0);
++			odm_set_bb_reg(dm, 0x41ac, BIT(4), 0);
++			odm_set_bb_reg(dm, 0x52ac, BIT(4), 0);
++			odm_set_bb_reg(dm, 0x53ac, BIT(4), 0);
++		}
++	} else if (dm->support_ic_type & ODM_RTL8814B) {
++		if (tab_sel == OFDM_AGC_TAB_0) {
++			odm_set_bb_reg(dm, 0x18ac, 0xf0, 0);
++			odm_set_bb_reg(dm, 0x41ac, 0xf0, 0);
++			odm_set_bb_reg(dm, 0x52ac, 0xf0, 0);
++			odm_set_bb_reg(dm, 0x53ac, 0xf0, 0);
++		} else if (tab_sel == OFDM_AGC_TAB_2) {
++			odm_set_bb_reg(dm, 0x18ac, 0xf0, 2);
++			odm_set_bb_reg(dm, 0x41ac, 0xf0, 2);
++			odm_set_bb_reg(dm, 0x52ac, 0xf0, 2);
++			odm_set_bb_reg(dm, 0x53ac, 0xf0, 2);
++		} else {
++			odm_set_bb_reg(dm, 0x18ac, 0xf0, 0);
++			odm_set_bb_reg(dm, 0x41ac, 0xf0, 0);
++			odm_set_bb_reg(dm, 0x52ac, 0xf0, 0);
++			odm_set_bb_reg(dm, 0x53ac, 0xf0, 0);
++		}
++	}
++}
++
++u8 phydm_get_ofdm_agc_tab_path(
++	void *dm_void,
++	enum rf_path path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 tab_sel = 0;
++
++	if (dm->support_ic_type & ODM_RTL8198F) {
++		tab_sel = (u8)odm_get_bb_reg(dm, R_0x18ac, BIT(4));
++		if (tab_sel == 0)
++			tab_sel = OFDM_AGC_TAB_0;
++		else if (tab_sel == 1)
++			tab_sel = OFDM_AGC_TAB_2;
++	} else if (dm->support_ic_type & ODM_RTL8814B) {
++		tab_sel = (u8)odm_get_bb_reg(dm, R_0x18ac, 0xf0);
++		if (tab_sel == 0)
++			tab_sel = OFDM_AGC_TAB_0;
++		else if (tab_sel == 2)
++			tab_sel = OFDM_AGC_TAB_2;
++	}
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "get path %d AGC Tab %d\n",
++		  path, tab_sel);
++	return tab_sel;
++}
++#endif /*@#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)*/
++
++void phydm_set_ofdm_agc_tab(
++	void *dm_void,
++	u8 tab_sel)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	/*@table sel:0/2, 1 is used for CCK */
++	if (tab_sel == OFDM_AGC_TAB_0)
++		odm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_0);
++	else if (tab_sel == OFDM_AGC_TAB_2)
++		odm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_2);
++	else
++		odm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_0);
++}
++
++u8 phydm_get_ofdm_agc_tab(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	return (u8)odm_get_bb_reg(dm, R_0xc70, 0x1e00);
++}
++
++void phydm_lna_sat_chk(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++	struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;
++	u8 igi_rssi_min;
++	u8 rssi_min = dm->rssi_min;
++	u32 sat_status_a, sat_status_b;
++	#ifdef PHYDM_IC_ABOVE_3SS
++	u32 sat_status_c;
++	#endif
++	#ifdef PHYDM_IC_ABOVE_4SS
++	u32 sat_status_d;
++	#endif
++	u8 igi_restore = dig_t->cur_ig_value;
++	u8 i, chk_cnt = lna_info->chk_cnt;
++	u32 lna_sat_cnt_thd = 0;
++	u8 agc_tab;
++	u32 max_check_time = 0;
++	/*@use rssi_max if rssi_min is not stable;*/
++	/*@rssi_min = dm->rssi_max;*/
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n%s ==>\n", __func__);
++
++	if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) {
++		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "Func disable\n");
++		return;
++	}
++
++	if (lna_info->is_disable_lna_sat_chk) {
++		phydm_lna_sat_chk_init(dm);
++		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "disable_lna_sat_chk\n");
++		return;
++	}
++
++	/*@move igi to target pin of rssi_min */
++	if (rssi_min == 0 || rssi_min == 0xff) {
++		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++			  "rssi_min=%d, set AGC Tab0\n", rssi_min);
++		/*@adapt agc table 0*/
++		phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);
++		phydm_lna_sat_chk_init(dm);
++		return;
++	} else if (rssi_min % 2 != 0) {
++		igi_rssi_min = rssi_min + DIFF_RSSI_TO_IGI - 1;
++	} else {
++		igi_rssi_min = rssi_min + DIFF_RSSI_TO_IGI;
++	}
++
++	if ((lna_info->chk_period > 0) && (lna_info->chk_period <= ONE_SEC_MS))
++		max_check_time = chk_cnt * (ONE_SEC_MS / (lna_info->chk_period)) * 5;
++	else
++		max_check_time = chk_cnt * 5;
++
++	lna_sat_cnt_thd = (max_check_time * lna_info->chk_duty_cycle) / 100;
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++		  "check_time=%d, rssi_min=%d, igi_rssi_min=0x%x\nchk_cnt=%d, chk_period=%d, max_check_time=%d, lna_sat_cnt_thd=%d\n",
++		  lna_info->check_time,
++		  rssi_min,
++		  igi_rssi_min,
++		  chk_cnt,
++		  lna_info->chk_period,
++		  max_check_time,
++		  lna_sat_cnt_thd);
++
++	odm_write_dig(dm, igi_rssi_min);
++
++	/*@adapt agc table 0 check saturation status*/
++	#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
++	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
++		phydm_set_ofdm_agc_tab_path(dm, OFDM_AGC_TAB_0, RF_PATH_A);
++	else
++	#endif
++		phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);
++	/*@open rf power detection ckt & set detection range */
++#if (RTL8198F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8198F) {
++		/*@set rf detection range (threshold)*/
++		config_phydm_write_rf_reg_8198f(dm, RF_PATH_A, 0x85,
++						0x3f, 0x3f);
++		config_phydm_write_rf_reg_8198f(dm, RF_PATH_B, 0x85,
++						0x3f, 0x3f);
++		config_phydm_write_rf_reg_8198f(dm, RF_PATH_C, 0x85,
++						0x3f, 0x3f);
++		config_phydm_write_rf_reg_8198f(dm, RF_PATH_D, 0x85,
++						0x3f, 0x3f);
++		/*@open rf power detection ckt*/
++		config_phydm_write_rf_reg_8198f(dm, RF_PATH_A, 0x86, 0x10, 1);
++		config_phydm_write_rf_reg_8198f(dm, RF_PATH_B, 0x86, 0x10, 1);
++		config_phydm_write_rf_reg_8198f(dm, RF_PATH_C, 0x86, 0x10, 1);
++		config_phydm_write_rf_reg_8198f(dm, RF_PATH_D, 0x86, 0x10, 1);
++	}
++#elif (RTL8814B_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8814B) {
++		/*@set rf detection range (threshold)*/
++		config_phydm_write_rf_reg_8814b(dm, RF_PATH_A, 0x8B, 0x3, 0x3);
++		config_phydm_write_rf_reg_8814b(dm, RF_PATH_B, 0x8B, 0x3, 0x3);
++		config_phydm_write_rf_reg_8814b(dm, RF_PATH_C, 0x8B, 0x3, 0x3);
++		config_phydm_write_rf_reg_8814b(dm, RF_PATH_D, 0x8B, 0x3, 0x3);
++		/*@open rf power detection ckt*/
++		config_phydm_write_rf_reg_8814b(dm, RF_PATH_A, 0x8B, 0x4, 1);
++		config_phydm_write_rf_reg_8814b(dm, RF_PATH_B, 0x8B, 0x4, 1);
++		config_phydm_write_rf_reg_8814b(dm, RF_PATH_C, 0x8B, 0x4, 1);
++		config_phydm_write_rf_reg_8814b(dm, RF_PATH_D, 0x8B, 0x4, 1);
++	}
++#else
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x86, 0x1f, 0x10);
++	odm_set_rf_reg(dm, RF_PATH_B, RF_0x86, 0x1f, 0x10);
++	#ifdef PHYDM_IC_ABOVE_3SS
++	odm_set_rf_reg(dm, RF_PATH_C, RF_0x86, 0x1f, 0x10);
++	#endif
++	#ifdef PHYDM_IC_ABOVE_4SS
++	odm_set_rf_reg(dm, RF_PATH_D, RF_0x86, 0x1f, 0x10);
++	#endif
++#endif
++
++	/*@check saturation status*/
++	for (i = 0; i < chk_cnt; i++) {
++#if (RTL8198F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8198F) {
++		sat_status_a = config_phydm_read_rf_reg_8198f(dm, RF_PATH_A,
++							      RF_0xae,
++							      0xe0000);
++		sat_status_b = config_phydm_read_rf_reg_8198f(dm, RF_PATH_B,
++							      RF_0xae,
++							      0xe0000);
++		sat_status_c = config_phydm_read_rf_reg_8198f(dm, RF_PATH_C,
++							      RF_0xae,
++							      0xe0000);
++		sat_status_d = config_phydm_read_rf_reg_8198f(dm, RF_PATH_D,
++							      RF_0xae,
++							      0xe0000);
++	}
++#elif (RTL8814B_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8814B) {
++	/*@read peak detector info from 8814B rf reg*/
++		sat_status_a = config_phydm_read_rf_reg_8814b(dm, RF_PATH_A,
++							      RF_0xae,
++							      0xc0000);
++		sat_status_b = config_phydm_read_rf_reg_8814b(dm, RF_PATH_B,
++							      RF_0xae,
++							      0xc0000);
++		sat_status_c = config_phydm_read_rf_reg_8814b(dm, RF_PATH_C,
++							      RF_0xae,
++							      0xc0000);
++		sat_status_d = config_phydm_read_rf_reg_8814b(dm, RF_PATH_D,
++							      RF_0xae,
++							      0xc0000);
++	}
++#else
++		sat_status_a = odm_get_rf_reg(dm, RF_PATH_A, RF_0xae, 0xc0000);
++		sat_status_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0xae, 0xc0000);
++		#ifdef PHYDM_IC_ABOVE_3SS
++		sat_status_c = odm_get_rf_reg(dm, RF_PATH_C, RF_0xae, 0xc0000);
++		#endif
++		#ifdef PHYDM_IC_ABOVE_4SS
++		sat_status_d = odm_get_rf_reg(dm, RF_PATH_D, RF_0xae, 0xc0000);
++		#endif
++#endif
++
++		if (sat_status_a != 0)
++			lna_info->sat_cnt_acc_patha++;
++		if (sat_status_b != 0)
++			lna_info->sat_cnt_acc_pathb++;
++		#ifdef PHYDM_IC_ABOVE_3SS
++		if (sat_status_c != 0)
++			lna_info->sat_cnt_acc_pathc++;
++		#endif
++		#ifdef PHYDM_IC_ABOVE_4SS
++		if (sat_status_d != 0)
++			lna_info->sat_cnt_acc_pathd++;
++		#endif
++
++		if (lna_info->sat_cnt_acc_patha >= lna_sat_cnt_thd ||
++		    lna_info->sat_cnt_acc_pathb >= lna_sat_cnt_thd ||
++		    #ifdef PHYDM_IC_ABOVE_3SS
++		    lna_info->sat_cnt_acc_pathc >= lna_sat_cnt_thd ||
++		    #endif
++		    #ifdef PHYDM_IC_ABOVE_4SS
++		    lna_info->sat_cnt_acc_pathd >= lna_sat_cnt_thd ||
++		    #endif
++		    0) {
++			lna_info->cur_sat_status = 1;
++			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++				  "cur_sat_status=%d, check_time=%d\n",
++				  lna_info->cur_sat_status,
++				  lna_info->check_time);
++			break;
++		}
++		lna_info->cur_sat_status = 0;
++	}
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++		  "cur_sat_status=%d, pre_sat_status=%d, sat_cnt_acc_patha=%d, sat_cnt_acc_pathb=%d\n",
++		  lna_info->cur_sat_status,
++		  lna_info->pre_sat_status,
++		  lna_info->sat_cnt_acc_patha,
++		  lna_info->sat_cnt_acc_pathb);
++
++	#ifdef PHYDM_IC_ABOVE_4SS
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++		  "cur_sat_status=%d, pre_sat_status=%d, sat_cnt_acc_pathc=%d, sat_cnt_acc_pathd=%d\n",
++		  lna_info->cur_sat_status,
++		  lna_info->pre_sat_status,
++		  lna_info->sat_cnt_acc_pathc,
++		  lna_info->sat_cnt_acc_pathd);
++	#endif
++	/*@agc table decision*/
++	if (lna_info->cur_sat_status) {
++		if (!lna_info->dis_agc_table_swh)
++			#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
++			if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
++				phydm_set_ofdm_agc_tab_path(dm,
++							    OFDM_AGC_TAB_2,
++							    RF_PATH_A);
++			else
++			#endif
++				phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_2);
++		else
++			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++				  "disable set to AGC Tab%d\n", OFDM_AGC_TAB_2);
++		lna_info->check_time = 0;
++		lna_info->sat_cnt_acc_patha = 0;
++		lna_info->sat_cnt_acc_pathb = 0;
++		#ifdef PHYDM_IC_ABOVE_3SS
++		lna_info->sat_cnt_acc_pathc = 0;
++		#endif
++		#ifdef PHYDM_IC_ABOVE_4SS
++		lna_info->sat_cnt_acc_pathd = 0;
++		#endif
++		lna_info->pre_sat_status = lna_info->cur_sat_status;
++
++	} else if (lna_info->check_time <= (max_check_time - 1)) {
++		if (lna_info->pre_sat_status && !lna_info->dis_agc_table_swh)
++			#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
++			if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
++				phydm_set_ofdm_agc_tab_path(dm,
++							    OFDM_AGC_TAB_2,
++							    RF_PATH_A);
++			else
++			#endif
++				phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_2);
++
++		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ckeck time not reached\n");
++		if (lna_info->dis_agc_table_swh)
++			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++				  "disable set to AGC Tab%d\n", OFDM_AGC_TAB_2);
++		lna_info->check_time++;
++
++	} else if (lna_info->check_time >= max_check_time) {
++		if (!lna_info->dis_agc_table_swh)
++			#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
++			if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
++				phydm_set_ofdm_agc_tab_path(dm,
++							    OFDM_AGC_TAB_0,
++							    RF_PATH_A);
++			else
++			#endif
++				phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);
++
++		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ckeck time reached\n");
++		if (lna_info->dis_agc_table_swh)
++			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++				  "disable set to AGC Tab%d\n", OFDM_AGC_TAB_0);
++		lna_info->check_time = 0;
++		lna_info->sat_cnt_acc_patha = 0;
++		lna_info->sat_cnt_acc_pathb = 0;
++		#ifdef PHYDM_IC_ABOVE_3SS
++		lna_info->sat_cnt_acc_pathc = 0;
++		#endif
++		#ifdef PHYDM_IC_ABOVE_4SS
++		lna_info->sat_cnt_acc_pathd = 0;
++		#endif
++		lna_info->pre_sat_status = lna_info->cur_sat_status;
++	}
++
++	#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
++	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
++		agc_tab = phydm_get_ofdm_agc_tab_path(dm, RF_PATH_A);
++	else
++	#endif
++		agc_tab = phydm_get_ofdm_agc_tab(dm);
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "use AGC tab %d\n", agc_tab);
++
++	/*@restore previous igi*/
++	odm_write_dig(dm, igi_restore);
++	lna_info->cur_timer_check_cnt++;
++	odm_set_timer(dm, &lna_info->phydm_lna_sat_chk_timer,
++		      lna_info->chk_period);
++}
++
++void phydm_lna_sat_chk_callback(
++	void *dm_void
++
++	)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n%s ==>\n", __func__);
++	phydm_lna_sat_chk(dm);
++}
++
++void phydm_lna_sat_chk_timers(
++	void *dm_void,
++	u8 state)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;
++
++	if (state == INIT_LNA_SAT_CHK_TIMMER) {
++		odm_initialize_timer(dm,
++				     &lna_info->phydm_lna_sat_chk_timer,
++				     (void *)phydm_lna_sat_chk_callback, NULL,
++				     "phydm_lna_sat_chk_timer");
++	} else if (state == CANCEL_LNA_SAT_CHK_TIMMER) {
++		odm_cancel_timer(dm, &lna_info->phydm_lna_sat_chk_timer);
++	} else if (state == RELEASE_LNA_SAT_CHK_TIMMER) {
++		odm_release_timer(dm, &lna_info->phydm_lna_sat_chk_timer);
++	}
++}
++
++void phydm_lna_sat_chk_watchdog_type1(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;
++
++	u8 rssi_min = dm->rssi_min;
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n%s ==>\n", __func__);
++
++	if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) {
++		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++			  "func disable\n");
++		return;
++	}
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++		  "pre_timer_check_cnt=%d, cur_timer_check_cnt=%d\n",
++		  lna_info->pre_timer_check_cnt,
++		  lna_info->cur_timer_check_cnt);
++
++	if (lna_info->is_disable_lna_sat_chk) {
++		phydm_lna_sat_chk_init(dm);
++		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++			  "is_disable_lna_sat_chk=%d, return\n",
++			  lna_info->is_disable_lna_sat_chk);
++		return;
++	}
++
++	if (!(dm->support_ic_type &
++	    (ODM_RTL8197F | ODM_RTL8198F | ODM_RTL8814B))) {
++		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++			  "support_ic_type not 97F/98F/14B, return\n");
++		return;
++	}
++
++	if (rssi_min == 0 || rssi_min == 0xff) {
++		/*@adapt agc table 0 */
++		phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);
++		phydm_lna_sat_chk_init(dm);
++		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++			  "rssi_min=%d, return\n", rssi_min);
++		return;
++	}
++
++	if (lna_info->cur_timer_check_cnt == lna_info->pre_timer_check_cnt) {
++		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "fail, restart timer\n");
++		odm_set_timer(dm, &lna_info->phydm_lna_sat_chk_timer,
++			      lna_info->chk_period);
++	} else {
++		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "Timer check pass\n");
++	}
++	lna_info->pre_timer_check_cnt = lna_info->cur_timer_check_cnt;
++}
++
++#endif /*@#ifdef PHYDM_LNA_SAT_CHK_TYPE1*/
++
++#ifdef PHYDM_LNA_SAT_CHK_TYPE2
++
++void phydm_bubble_sort(
++	void *dm_void,
++	u8 *array,
++	u16 array_length)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u16 i, j;
++	u8 temp;
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
++	for (i = 0; i < (array_length - 1); i++) {
++		for (j = (i + 1); j < (array_length); j++) {
++			if (array[i] > array[j]) {
++				temp = array[i];
++				array[i] = array[j];
++				array[j] = temp;
++			}
++		}
++	}
++}
++
++void phydm_lna_sat_chk_type2_init(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
++	u8 real_shift = pinfo->total_bit_shift;
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
++
++	pinfo->total_cnt_snr = 1 << real_shift;
++	pinfo->is_sm_done = TRUE;
++	pinfo->is_snr_done = FALSE;
++	pinfo->cur_snr_mean = 0;
++	pinfo->cur_snr_var = 0;
++	pinfo->cur_lower_snr_mean = 0;
++	pinfo->pre_snr_mean = 0;
++	pinfo->pre_snr_var = 0;
++	pinfo->pre_lower_snr_mean = 0;
++	pinfo->nxt_state = ORI_TABLE_MONITOR;
++	pinfo->pre_state = ORI_TABLE_MONITOR;
++}
++
++void phydm_snr_collect(
++	void *dm_void,
++	u8 rx_snr)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
++
++	if (pinfo->is_sm_done) {
++		/* @adapt only path-A for calculation */
++		pinfo->snr_statistic[pinfo->cnt_snr_statistic] = rx_snr;
++
++		if (pinfo->cnt_snr_statistic == (pinfo->total_cnt_snr - 1)) {
++			pinfo->is_snr_done = TRUE;
++			pinfo->cnt_snr_statistic = 0;
++		} else {
++			pinfo->cnt_snr_statistic++;
++		}
++	} else {
++		return;
++	}
++}
++
++void phydm_parsing_snr(void *dm_void, void *pktinfo_void, s8 *rx_snr)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*lna_t = &dm->dm_lna_sat_info;
++	struct phydm_perpkt_info_struct *pktinfo = NULL;
++	u8 target_macid = dm->rssi_min_macid;
++
++	if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK))
++		return;
++
++	pktinfo = (struct phydm_perpkt_info_struct *)pktinfo_void;
++
++	if (!pktinfo->is_packet_match_bssid)
++		return;
++
++	if (lna_t->force_traget_macid != 0)
++		target_macid = lna_t->force_traget_macid;
++
++	if (target_macid != pktinfo->station_id)
++		return;
++
++	phydm_snr_collect(dm, rx_snr[0]); /*path-A B C D???*/
++}
++
++void phydm_snr_data_processing(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
++	u8 real_shift = pinfo->total_bit_shift;
++	u16 total_snr_cnt = pinfo->total_cnt_snr;
++	u16 total_loop_cnt = (total_snr_cnt - 1), i;
++	u32 temp;
++	u32 sum_snr_statistic = 0;
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++		  "total_loop_cnt=%d\n", total_loop_cnt);
++
++	for (i = 0; (i <= total_loop_cnt); i++) {
++		if (pinfo->is_snr_detail_en) {
++			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++				  "snr[%d]=%d\n", i, pinfo->snr_statistic[i]);
++		}
++
++		sum_snr_statistic += (u32)(pinfo->snr_statistic[i]);
++
++		pinfo->snr_statistic_sqr[i] = (u16)(pinfo->snr_statistic[i] * pinfo->snr_statistic[i]);
++	}
++
++	phydm_bubble_sort(dm, pinfo->snr_statistic, pinfo->total_cnt_snr);
++
++	/*update SNR's cur mean*/
++	pinfo->cur_snr_mean = (sum_snr_statistic >> real_shift);
++
++	for (i = 0; (i <= total_loop_cnt); i++) {
++		if (pinfo->snr_statistic[i] >= pinfo->cur_snr_mean)
++			temp = pinfo->snr_statistic[i] - pinfo->cur_snr_mean;
++		else
++			temp = pinfo->cur_snr_mean - pinfo->snr_statistic[i];
++
++		pinfo->cur_snr_var += (temp * temp);
++	}
++
++	/*update SNR's VAR*/
++	pinfo->cur_snr_var = (pinfo->cur_snr_var >> real_shift);
++
++	/*@acquire lower SNR's statistics*/
++	temp = 0;
++	pinfo->cnt_lower_snr_statistic = (total_snr_cnt >> pinfo->lwr_snr_ratio_bit_shift);
++	pinfo->cnt_lower_snr_statistic = MAX_2(pinfo->cnt_lower_snr_statistic, SNR_RPT_MAX);
++
++	for (i = 0; i < pinfo->cnt_lower_snr_statistic; i++)
++		temp += pinfo->snr_statistic[i];
++
++	pinfo->cur_lower_snr_mean = temp >> (real_shift - pinfo->lwr_snr_ratio_bit_shift);
++}
++
++boolean phydm_is_snr_improve(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
++	boolean is_snr_improve;
++	u8 cur_state = pinfo->nxt_state;
++	u32 cur_mean = pinfo->cur_snr_mean;
++	u32 pre_mean = pinfo->pre_snr_mean;
++	u32 cur_lower_mean = pinfo->cur_lower_snr_mean;
++	u32 pre_lower_mean = pinfo->pre_lower_snr_mean;
++	u32 cur_var = pinfo->cur_snr_var;
++
++	/*special case, zero VAR, interference is gone*/
++	 /*@make sure pre_var is larger enough*/
++	if (cur_state == SAT_TABLE_MONITOR ||
++	    cur_state == ORI_TABLE_TRAINING) {
++		if (cur_mean >= pre_mean) {
++			if (cur_var == 0)
++				return true;
++		}
++	}
++#if 0
++	/*special case, mean degrade less than VAR improvement*/
++	/*@make sure pre_var is larger enough*/
++	if (cur_state == ORI_TABLE_MONITOR &&
++	    cur_mean < pre_mean &&
++	    cur_var < pre_var) {
++		diff_mean = pre_mean - cur_mean;
++		diff_var = pre_var - cur_var;
++		return (diff_var > (2 * diff_mean * diff_mean)) ? true : false;
++	}
++
++#endif
++	if (cur_lower_mean >= (pre_lower_mean + pinfo->delta_snr_mean))
++		is_snr_improve = true;
++	else
++		is_snr_improve = false;
++#if 0
++/* @condition refine, mean is bigger enough or VAR is smaller enough*/
++/* @1. from mean's view, mean improve delta_snr_mean(2), VAR not degrade lot*/
++	if (cur_mean > (pre_mean + pinfo->delta_snr_mean)) {
++		is_mean_improve = TRUE;
++		is_var_improve = (cur_var <= pre_var + dm->delta_snr_var)
++				 ? TRUE : FALSE;
++
++	} else if (cur_var + dm->delta_snr_var <= pre_var) {
++		is_var_improve = TRUE;
++		is_mean_improve = ((cur_mean + 1) >= pre_mean) ? TRUE : FALSE;
++	} else {
++		return false;
++	}
++#endif
++	return is_snr_improve;
++}
++
++boolean phydm_is_snr_degrade(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
++	u32 cur_lower_mean = pinfo->cur_lower_snr_mean;
++	u32 pre_lower_mean = pinfo->pre_lower_snr_mean;
++	boolean is_degrade;
++
++	if (cur_lower_mean <= (pre_lower_mean - pinfo->delta_snr_mean))
++		is_degrade = TRUE;
++	else
++		is_degrade = FALSE;
++#if 0
++	is_mean_dgrade = (pinfo->cur_snr_mean + pinfo->delta_snr_mean <= pinfo->pre_snr_mean) ? TRUE : FALSE;
++	is_var_degrade = (pinfo->cur_snr_var > (pinfo->pre_snr_var + pinfo->delta_snr_mean)) ? TRUE : FALSE;
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d\n",
++		  __func__,
++		  pinfo->cur_snr_mean,
++		  pinfo->pre_snr_mean,
++		  pinfo->cur_snr_var,
++		  pinfo->pre_snr_var);
++
++	return (is_mean_dgrade & is_var_degrade);
++#endif
++	return is_degrade;
++}
++
++boolean phydm_is_large_var(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
++	boolean is_large_var = (pinfo->cur_snr_var >= pinfo->snr_var_thd) ? TRUE : FALSE;
++
++	return is_large_var;
++}
++
++void phydm_update_pre_status(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
++
++	pinfo->pre_lower_snr_mean = pinfo->cur_lower_snr_mean;
++	pinfo->pre_snr_mean = pinfo->cur_snr_mean;
++	pinfo->pre_snr_var = pinfo->cur_snr_var;
++}
++
++void phydm_ori_table_monitor(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
++
++	if (phydm_is_large_var(dm)) {
++		pinfo->nxt_state = SAT_TABLE_TRAINING;
++		config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
++	} else {
++		pinfo->nxt_state = ORI_TABLE_MONITOR;
++		/*switch to anti-sat table*/
++		config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
++	}
++	phydm_update_pre_status(dm);
++	pinfo->pre_state = ORI_TABLE_MONITOR;
++}
++
++void phydm_sat_table_training(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
++
++	#if 0
++	if pre_state = ORI_TABLE_MONITOR || SAT_TABLE_TRY_FAIL,
++	/*@"pre" adapt ori-table, "cur" adapt sat-table*/
++	/*@adapt ori table*/
++	if (pinfo->pre_state == ORI_TABLE_MONITOR) {
++		pinfo->nxt_state = SAT_TABLE_TRAINING;
++		config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
++	} else {
++	#endif
++	if (phydm_is_snr_improve(dm)) {
++		pinfo->nxt_state = SAT_TABLE_MONITOR;
++	} else {
++		pinfo->nxt_state = SAT_TABLE_TRY_FAIL;
++		config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
++	}
++	/*@}*/
++
++	phydm_update_pre_status(dm);
++	pinfo->pre_state = SAT_TABLE_TRAINING;
++}
++
++void phydm_sat_table_try_fail(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
++
++	/* @if pre_state = SAT_TABLE_TRAINING, "pre" adapt sat-table, "cur" adapt ori-table */
++	/* @if pre_state = SAT_TABLE_TRY_FAIL, "pre" adapt ori-table, "cur" adapt ori-table */
++
++	if (phydm_is_large_var(dm)) {
++		if (phydm_is_snr_degrade(dm)) {
++			pinfo->nxt_state = SAT_TABLE_TRAINING;
++			config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
++		} else {
++			pinfo->nxt_state = SAT_TABLE_TRY_FAIL;
++		}
++	} else {
++		pinfo->nxt_state = ORI_TABLE_MONITOR;
++	}
++	phydm_update_pre_status(dm);
++	pinfo->pre_state = SAT_TABLE_TRY_FAIL;
++}
++
++void phydm_sat_table_monitor(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
++
++	if (phydm_is_snr_improve(dm)) {
++		pinfo->sat_table_monitor_times = 0;
++
++		/* @if pre_state = SAT_TABLE_MONITOR, "pre" adapt sat-table, "cur" adapt sat-table */
++		if (pinfo->pre_state == SAT_TABLE_MONITOR) {
++			pinfo->nxt_state = ORI_TABLE_TRAINING;
++			config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
++			//phydm_update_pre_status(dm);
++		} else {
++			pinfo->nxt_state = SAT_TABLE_MONITOR;
++		}
++
++		/* @if pre_state = SAT_TABLE_TRAINING, "pre" adapt sat-table, "cur" adapt sat-table */
++		/* @if pre_state = ORI_TABLE_TRAINING, "pre" adapt ori-table, "cur" adapt sat-table */
++		/*pre_state above is no need to update*/
++	} else {
++		if (pinfo->sat_table_monitor_times == pinfo->force_change_period) {
++			PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s: sat_table_monitor_times=%d\n",
++				  __func__, pinfo->sat_table_monitor_times);
++
++			pinfo->nxt_state = ORI_TABLE_TRAINING;
++			pinfo->sat_table_monitor_times = 0;
++			config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
++		} else {
++			pinfo->nxt_state = SAT_TABLE_MONITOR;
++			pinfo->sat_table_monitor_times++;
++		}
++	}
++	phydm_update_pre_status(dm);
++	pinfo->pre_state = SAT_TABLE_MONITOR;
++}
++
++void phydm_ori_table_training(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
++
++	/* pre_state = SAT_TABLE_MONITOR, "pre" adapt sat-table, "cur" adapt ori-table */
++
++	if (phydm_is_snr_degrade(dm) == FALSE) {
++		pinfo->nxt_state = ORI_TABLE_MONITOR;
++	} else {
++		if (pinfo->pre_snr_var == 0)
++			pinfo->nxt_state = ORI_TABLE_TRY_FAIL;
++		else
++			pinfo->nxt_state = SAT_TABLE_MONITOR;
++
++		config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
++	}
++	phydm_update_pre_status(dm);
++	pinfo->pre_state = ORI_TABLE_TRAINING;
++}
++
++void phydm_ori_table_try_fail(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
++
++	if (pinfo->pre_state == ORI_TABLE_TRY_FAIL) {
++		if (phydm_is_snr_improve(dm)) {
++			pinfo->nxt_state = ORI_TABLE_TRAINING;
++			pinfo->ori_table_try_fail_times = 0;
++			config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
++		} else {
++			if (pinfo->ori_table_try_fail_times == pinfo->force_change_period) {
++				PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++					  "%s: ori_table_try_fail_times=%d\n", __func__, pinfo->ori_table_try_fail_times);
++
++				pinfo->nxt_state = ORI_TABLE_TRY_FAIL;
++				pinfo->ori_table_try_fail_times = 0;
++				phydm_update_pre_status(dm);
++			} else {
++				pinfo->nxt_state = ORI_TABLE_TRY_FAIL;
++				pinfo->ori_table_try_fail_times++;
++				phydm_update_pre_status(dm);
++				//config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
++			}
++		}
++	} else {
++		pinfo->nxt_state = ORI_TABLE_TRY_FAIL;
++		pinfo->ori_table_try_fail_times = 0;
++		phydm_update_pre_status(dm);
++		//config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
++	}
++
++#if 0
++	if (phydm_is_large_var(dm)) {
++		if (phydm_is_snr_degrade(dm)) {
++			pinfo->nxt_state = SAT_TABLE_TRAINING;
++			config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
++		} else {
++			pinfo->nxt_state = SAT_TABLE_TRY_FAIL;
++		}
++	} else {
++		pinfo->nxt_state = ORI_TABLE_MONITOR;
++	}
++
++	phydm_update_pre_status(dm);
++#endif
++	pinfo->pre_state = ORI_TABLE_TRY_FAIL;
++}
++
++char *phydm_lna_sat_state_msg(
++	void *dm_void,
++	IN u8 state)
++{
++	char *dbg_message;
++
++	switch (state) {
++	case ORI_TABLE_MONITOR:
++		dbg_message = "ORI_TABLE_MONITOR";
++		break;
++
++	case SAT_TABLE_TRAINING:
++		dbg_message = "SAT_TABLE_TRAINING";
++		break;
++
++	case SAT_TABLE_TRY_FAIL:
++		dbg_message = "SAT_TABLE_TRY_FAIL";
++		break;
++
++	case SAT_TABLE_MONITOR:
++		dbg_message = "SAT_TABLE_MONITOR";
++		break;
++
++	case ORI_TABLE_TRAINING:
++		dbg_message = "ORI_TABLE_TRAINING";
++		break;
++
++	case ORI_TABLE_TRY_FAIL:
++		dbg_message = "ORI_TABLE_TRY_FAIL";
++		break;
++
++	default:
++		dbg_message = "ORI_TABLE_MONITOR";
++		break;
++	}
++
++	return dbg_message;
++}
++
++void phydm_lna_sat_type2_sm(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
++	u8 state = pinfo->nxt_state;
++	u8 agc_tab = (u8)odm_get_bb_reg(dm, 0x958, 0x1f);
++	char *dbg_message, *nxt_dbg_message;
++	u8 real_shift = pinfo->total_bit_shift;
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n\n%s ==>\n", __func__);
++
++	if ((dm->support_ic_type & ODM_RTL8822B) == FALSE) {
++		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ODM_BB_LNA_SAT_CHK_TYPE2 only support 22B.\n");
++		return;
++	}
++
++	if ((dm->support_ability & ODM_BB_LNA_SAT_CHK) == FALSE) {
++		phydm_lna_sat_chk_type2_init(dm);
++		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ODM_BB_LNA_SAT_CHK_TYPE2 is NOT supported, cur table=%d\n", agc_tab);
++		return;
++	}
++
++	if (pinfo->is_snr_done)
++		phydm_snr_data_processing(dm);
++	else
++		return;
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "cur agc table %d\n", agc_tab);
++
++	if (pinfo->is_force_lna_sat_table != AUTO_AGC_TABLE) {
++		/*reset state machine*/
++		pinfo->nxt_state = ORI_TABLE_MONITOR;
++		if (pinfo->is_snr_done) {
++			if (pinfo->is_force_lna_sat_table == DEFAULT_AGC_TABLE)
++				config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
++			else if (pinfo->is_force_lna_sat_table == LNA_SAT_AGC_TABLE)
++				config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
++			else
++				config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
++
++			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++				  "%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d,cur_lower_mean=%d, pre_lower_mean=%d, cnt_lower_snr=%d\n",
++				  __func__,
++				  pinfo->cur_snr_mean,
++				  pinfo->pre_snr_mean,
++				  pinfo->cur_snr_var,
++				  pinfo->pre_snr_var,
++				  pinfo->cur_lower_snr_mean,
++				  pinfo->pre_lower_snr_mean,
++				  pinfo->cnt_lower_snr_statistic);
++
++			pinfo->is_snr_done = FALSE;
++			pinfo->is_sm_done = TRUE;
++			phydm_update_pre_status(dm);
++		} else {
++			return;
++		}
++	} else if (pinfo->is_snr_done) {
++		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
++			  "%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d,cur_lower_mean=%d, pre_lower_mean=%d, cnt_lower_snr=%d\n",
++			  __func__,
++			  pinfo->cur_snr_mean,
++			  pinfo->pre_snr_mean,
++			  pinfo->cur_snr_var,
++			  pinfo->pre_snr_var,
++			  pinfo->cur_lower_snr_mean,
++			  pinfo->pre_lower_snr_mean,
++			  pinfo->cnt_lower_snr_statistic);
++
++		switch (state) {
++		case ORI_TABLE_MONITOR:
++			dbg_message = "ORI_TABLE_MONITOR";
++			phydm_ori_table_monitor(dm);
++			break;
++
++		case SAT_TABLE_TRAINING:
++			dbg_message = "SAT_TABLE_TRAINING";
++			phydm_sat_table_training(dm);
++			break;
++
++		case SAT_TABLE_TRY_FAIL:
++			dbg_message = "SAT_TABLE_TRY_FAIL";
++			phydm_sat_table_try_fail(dm);
++			break;
++
++		case SAT_TABLE_MONITOR:
++			dbg_message = "SAT_TABLE_MONITOR";
++			phydm_sat_table_monitor(dm);
++			break;
++
++		case ORI_TABLE_TRAINING:
++			dbg_message = "ORI_TABLE_TRAINING";
++			phydm_ori_table_training(dm);
++			break;
++
++		case ORI_TABLE_TRY_FAIL:
++			dbg_message = "ORI_TABLE_TRAINING";
++			phydm_ori_table_try_fail(dm);
++			break;
++
++		default:
++			dbg_message = "ORI_TABLE_MONITOR";
++			phydm_ori_table_monitor(dm);
++			break;
++		}
++
++		dbg_message = phydm_lna_sat_state_msg(dm, state);
++		nxt_dbg_message = phydm_lna_sat_state_msg(dm, pinfo->nxt_state);
++		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "state: [%s]->[%s]\n",
++			  dbg_message, nxt_dbg_message);
++
++		pinfo->is_snr_done = FALSE;
++		pinfo->is_sm_done = TRUE;
++		pinfo->total_cnt_snr = 1 << real_shift;
++
++	} else {
++		return;
++	}
++}
++
++
++#endif /*@#ifdef PHYDM_LNA_SAT_CHK_TYPE2*/
++
++void phydm_lna_sat_debug(
++	void *dm_void,
++	char input[][16],
++	u32 *_used,
++	char *output,
++	u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*lna_t = &dm->dm_lna_sat_info;
++	char help[] = "-h";
++	char monitor[] = "-m";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 i;
++	u8 agc_tab = 0;
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "monitor: -m\n");
++		#ifdef PHYDM_LNA_SAT_CHK_TYPE1
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{0} {lna_sat_chk_en}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{1} {agc_table_switch_en}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{2} {chk_cnt per callback}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{3} {chk_period(ms)}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{4} {chk_duty_cycle(%)}\n");
++		#endif
++	} else if ((strcmp(input[1], monitor) == 0)) {
++#ifdef PHYDM_LNA_SAT_CHK_TYPE1
++		#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
++		if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
++			agc_tab = phydm_get_ofdm_agc_tab_path(dm, RF_PATH_A);
++		else
++		#endif
++			agc_tab = phydm_get_ofdm_agc_tab(dm);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "%s%d, %s%d, %s%d, %s%d\n",
++			 "check_time = ", lna_t->check_time,
++			 "pre_sat_status = ", lna_t->pre_sat_status,
++			 "cur_sat_status = ", lna_t->cur_sat_status,
++			 "current AGC tab = ", agc_tab);
++#endif
++	} else {
++		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
++
++		for (i = 1; i < 10; i++) {
++			if (input[i + 1])
++				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
++					     &var1[i]);
++		}
++		#ifdef PHYDM_LNA_SAT_CHK_TYPE1
++		if (var1[0] == 0) {
++			if (var1[1] == 1)
++				lna_t->is_disable_lna_sat_chk = false;
++			else if (var1[1] == 0)
++				lna_t->is_disable_lna_sat_chk = true;
++
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "dis_lna_sat_chk=%d\n",
++				 lna_t->is_disable_lna_sat_chk);
++		} else if (var1[0] == 1) {
++			if (var1[1] == 1)
++				lna_t->dis_agc_table_swh = false;
++			else if (var1[1] == 0)
++				lna_t->dis_agc_table_swh = true;
++
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "dis_agc_table_swh=%d\n",
++				 lna_t->dis_agc_table_swh);
++
++		} else if (var1[0] == 2) {
++			lna_t->chk_cnt = (u8)var1[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "chk_cnt=%d\n", lna_t->chk_cnt);
++		} else if (var1[0] == 3) {
++			lna_t->chk_period = var1[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "chk_period=%d\n", lna_t->chk_period);
++		} else if (var1[0] == 4) {
++			lna_t->chk_duty_cycle = (u8)var1[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "chk_duty_cycle=%d\n",
++				 lna_t->chk_duty_cycle);
++		}
++		#endif
++		#ifdef PHYDM_LNA_SAT_CHK_TYPE2
++		if (var1[0] == 1)
++			lna_t->force_traget_macid = var1[1];
++		#endif
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_lna_sat_chk_watchdog(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t *lna_sat = &dm->dm_lna_sat_info;
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
++
++	if (lna_sat->lna_sat_type == LNA_SAT_WITH_PEAK_DET) {
++		#ifdef PHYDM_LNA_SAT_CHK_TYPE1
++		phydm_lna_sat_chk_watchdog_type1(dm);
++		#endif
++	} else if (lna_sat->lna_sat_type == LNA_SAT_WITH_TRAIN) {
++		#ifdef PHYDM_LNA_SAT_CHK_TYPE2
++
++		#endif
++	}
++
++}
++
++void phydm_lna_sat_config(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*lna_sat = &dm->dm_lna_sat_info;
++
++	#if (RTL8822B_SUPPORT == 1)
++	if (dm->support_ic_type & (ODM_RTL8822B))
++		lna_sat->lna_sat_type = LNA_SAT_WITH_TRAIN;
++	#endif
++
++	#if (RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\
++	     RTL8198F_SUPPORT || RTL8814B_SUPPORT)
++	if (dm->support_ic_type &
++	    (ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8198F | ODM_RTL8814B))
++		lna_sat->lna_sat_type = LNA_SAT_WITH_PEAK_DET;
++	#endif
++
++	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "[%s] lna_sat_type=%d\n",
++		  __func__, lna_sat->lna_sat_type);
++}
++
++void phydm_lna_sat_check_init(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_lna_sat_t	*lna_sat = &dm->dm_lna_sat_info;
++
++	if ((dm->support_ability & ODM_BB_LNA_SAT_CHK))
++		return;
++
++	/*@2018.04.17 Johnson*/
++	phydm_lna_sat_config(dm);
++	#ifdef PHYDM_LNA_SAT_CHK_TYPE1
++	lna_sat->chk_period = LNA_CHK_PERIOD;
++	lna_sat->chk_cnt = LNA_CHK_CNT;
++	lna_sat->chk_duty_cycle = LNA_CHK_DUTY_CYCLE;
++	lna_sat->dis_agc_table_swh = false;
++	#endif
++	/*@2018.04.17 Johnson end*/
++
++	if (lna_sat->lna_sat_type == LNA_SAT_WITH_PEAK_DET) {
++		#ifdef PHYDM_LNA_SAT_CHK_TYPE1
++		phydm_lna_sat_chk_init(dm);
++		#endif
++	} else if (lna_sat->lna_sat_type == LNA_SAT_WITH_TRAIN) {
++		#ifdef PHYDM_LNA_SAT_CHK_TYPE2
++		phydm_lna_sat_chk_type2_init(dm);
++		#endif
++	}
++}
++
++#endif /*@#ifdef PHYDM_LNA_SAT_CHK_SUPPORT*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_lna_sat.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_lna_sat.h
+new file mode 100644
+index 000000000..c9345b86f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_lna_sat.h
+@@ -0,0 +1,173 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_LNA_SAT_H__
++#define __PHYDM_LNA_SAT_H__
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++/* @1 ============================================================
++ * 1  Definition
++ * 1 ============================================================
++ */
++
++#define LNA_SAT_VERSION "1.0"
++
++/*@LNA saturation check*/
++#define	OFDM_AGC_TAB_0			0
++#define	OFDM_AGC_TAB_2			2
++
++#define	DIFF_RSSI_TO_IGI		10
++#define	ONE_SEC_MS			1000
++
++#define LNA_CHK_PERIOD			100 /*@ms*/
++#define LNA_CHK_CNT			10 /*@checks per callback*/
++#define LNA_CHK_DUTY_CYCLE		5 /*@percentage*/
++
++#define	DELTA_STD	2
++#define	DELTA_MEAN	2
++#define	SNR_STATISTIC_SHIFT	8
++#define	SNR_RPT_MAX	256
++
++/* @1 ============================================================
++ * 1 enumrate
++ * 1 ============================================================
++ */
++
++enum lna_sat_timer_state {
++	INIT_LNA_SAT_CHK_TIMMER,
++	CANCEL_LNA_SAT_CHK_TIMMER,
++	RELEASE_LNA_SAT_CHK_TIMMER
++};
++
++#ifdef PHYDM_LNA_SAT_CHK_TYPE2
++enum lna_sat_chk_type2_status {
++	ORI_TABLE_MONITOR,
++	ORI_TABLE_TRAINING,
++	SAT_TABLE_MONITOR,
++	SAT_TABLE_TRAINING,
++	SAT_TABLE_TRY_FAIL,
++	ORI_TABLE_TRY_FAIL
++};
++
++#endif
++
++enum lna_sat_type {
++	LNA_SAT_WITH_PEAK_DET	= 1,	/*type1*/
++	LNA_SAT_WITH_TRAIN	= 2,	/*type2*/
++};
++
++/* @1 ============================================================
++ * 1  structure
++ * 1 ============================================================
++ */
++
++struct phydm_lna_sat_t {
++#ifdef PHYDM_LNA_SAT_CHK_TYPE1
++	u8			chk_cnt;
++	u8			chk_duty_cycle;
++	u32			chk_period;/*@ms*/
++	boolean			is_disable_lna_sat_chk;
++	boolean			dis_agc_table_swh;
++#endif
++#ifdef PHYDM_LNA_SAT_CHK_TYPE2
++	u8			force_traget_macid;
++	u32			snr_var_thd;
++	u32			delta_snr_mean;
++	u16			ori_table_try_fail_times;
++	u16			cnt_lower_snr_statistic;
++	u16			sat_table_monitor_times;
++	u16			force_change_period;
++	u8			is_snr_detail_en;
++	u8			is_force_lna_sat_table;
++	u8			lwr_snr_ratio_bit_shift;
++	u8			cnt_snr_statistic;
++	u16			snr_statistic_sqr[SNR_RPT_MAX];
++	u8			snr_statistic[SNR_RPT_MAX];
++	u8			is_sm_done;
++	u8			is_snr_done;
++	u32			cur_snr_var;
++	u8			total_bit_shift;
++	u8			total_cnt_snr;
++	u32			cur_snr_mean;
++	u8			cur_snr_var0;
++	u32			cur_lower_snr_mean;
++	u32			pre_snr_mean;
++	u32			pre_snr_var;
++	u32			pre_lower_snr_mean;
++	u8			nxt_state;
++	u8			pre_state;
++#endif
++	enum lna_sat_type	lna_sat_type;
++	u32			sat_cnt_acc_patha;
++	u32			sat_cnt_acc_pathb;
++#ifdef PHYDM_IC_ABOVE_3SS
++	u32			sat_cnt_acc_pathc;
++#endif
++#ifdef PHYDM_IC_ABOVE_4SS
++	u32			sat_cnt_acc_pathd;
++#endif
++	u32			check_time;
++	boolean			pre_sat_status;
++	boolean			cur_sat_status;
++	struct phydm_timer_list	phydm_lna_sat_chk_timer;
++	u32			cur_timer_check_cnt;
++	u32			pre_timer_check_cnt;
++};
++
++/* @1 ============================================================
++ * 1 function prototype
++ * 1 ============================================================
++ */
++void phydm_lna_sat_chk_init(void *dm_void);
++
++u8 phydm_get_ofdm_agc_tab(void *dm_void);
++
++void phydm_lna_sat_chk(void *dm_void);
++
++void phydm_lna_sat_chk_timers(void *dm_void, u8 state);
++
++#ifdef PHYDM_LNA_SAT_CHK_TYPE1
++#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
++void phydm_lna_sat_chk_bb_init(void *dm_void);
++
++void phydm_set_ofdm_agc_tab_path(void *dm_void,
++				 u8 tab_sel, enum rf_path path);
++
++u8 phydm_get_ofdm_agc_tab_path(void *dm_void, enum rf_path path);
++#endif /*@#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)*/
++#endif
++
++#ifdef PHYDM_LNA_SAT_CHK_TYPE2
++void phydm_parsing_snr(void *dm_void, void *pktinfo_void, s8 *rx_snr);
++#endif
++
++void phydm_lna_sat_debug(void *dm_void, char input[][16], u32 *_used,
++			 char *output, u32 *_out_len);
++
++void phydm_lna_sat_chk_watchdog(void *dm_void);
++
++void phydm_lna_sat_check_init(void *dm_void);
++
++#endif /*@#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_math_lib.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_math_lib.c
+new file mode 100644
+index 000000000..550c4a750
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_math_lib.c
+@@ -0,0 +1,285 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ ************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++const u32 db_invert_table[12][8] = {
++	{10, 13, 16, 20, 25, 32, 40, 50}, /* @U(32,3) */
++	{64, 80, 101, 128, 160, 201, 256, 318}, /* @U(32,3) */
++	{401, 505, 635, 800, 1007, 1268, 1596, 2010}, /* @U(32,3) */
++	{316, 398, 501, 631, 794, 1000, 1259, 1585}, /* @U(32,0) */
++	{1995, 2512, 3162, 3981, 5012, 6310, 7943, 10000}, /* @U(32,0) */
++	{12589, 15849, 19953, 25119, 31623, 39811, 50119, 63098}, /* @U(32,0) */
++	{79433, 100000, 125893, 158489, 199526, 251189, 316228,
++	 398107}, /* @U(32,0) */
++	{501187, 630957, 794328, 1000000, 1258925, 1584893, 1995262,
++	 2511886}, /* @U(32,0) */
++	{3162278, 3981072, 5011872, 6309573, 7943282, 1000000, 12589254,
++	 15848932}, /* @U(32,0) */
++	{19952623, 25118864, 31622777, 39810717, 50118723, 63095734,
++	 79432823, 100000000}, /* @U(32,0) */
++	{125892541, 158489319, 199526232, 251188643, 316227766, 398107171,
++	 501187234, 630957345}, /* @U(32,0) */
++	{794328235, 1000000000, 1258925412, 1584893192, 1995262315,
++	 2511886432U, 3162277660U, 3981071706U} }; /* @U(32,0) */
++
++/*Y = 10*log(X)*/
++s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit)
++{
++	s32 Y, integer = 0, decimal = 0;
++	u32 i;
++
++	if (X == 0)
++		X = 1; /* @log2(x), x can't be 0 */
++
++	for (i = (total_bit - 1); i > 0; i--) {
++		if (X & BIT(i)) {
++			integer = i;
++			if (i > 0) {
++				/*decimal is 0.5dB*3=1.5dB~=2dB */
++				decimal = (X & BIT(i - 1)) ? 2 : 0;
++			}
++			break;
++		}
++	}
++
++	Y = 3 * (integer - decimal_bit) + decimal; /* @10*log(x)=3*log2(x), */
++
++	return Y;
++}
++
++s32 odm_sign_conversion(s32 value, u32 total_bit)
++{
++	if (value & BIT(total_bit - 1))
++		value -= BIT(total_bit);
++
++	return value;
++}
++
++/*threshold must form low to high*/
++u16 phydm_find_intrvl(void *dm_void, u16 val, u16 *threshold, u16 th_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u16 i = 0;
++	u16 ret_val = 0;
++	u16 max_th = threshold[th_len - 1];
++
++	for (i = 0; i < th_len; i++) {
++		if (val < threshold[i]) {
++			ret_val = i;
++			break;
++		} else if (val >= max_th) {
++			ret_val = th_len;
++			break;
++		}
++	}
++
++	return ret_val;
++}
++
++void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
++		       u8 seq_length)
++{
++	u8 i = 0, j = 0;
++	u32 tmp_a, tmp_b;
++	u32 tmp_idx_a, tmp_idx_b;
++
++	for (i = 0; i < seq_length; i++)
++		rank_idx[i] = i;
++
++	for (i = 0; i < (seq_length - 1); i++) {
++		for (j = 0; j < (seq_length - 1 - i); j++) {
++			tmp_a = value[j];
++			tmp_b = value[j + 1];
++
++			tmp_idx_a = rank_idx[j];
++			tmp_idx_b = rank_idx[j + 1];
++
++			if (tmp_a < tmp_b) {
++				value[j] = tmp_b;
++				value[j + 1] = tmp_a;
++
++				rank_idx[j] = tmp_idx_b;
++				rank_idx[j + 1] = tmp_idx_a;
++			}
++		}
++	}
++
++	for (i = 0; i < seq_length; i++)
++		idx_out[rank_idx[i]] = i + 1;
++}
++
++u32 odm_convert_to_db(u64 value)
++{
++	u8 i;
++	u8 j;
++	u32 dB;
++
++	if (value >= db_invert_table[11][7])
++		return 96; /* @maximum 96 dB */
++
++	for (i = 0; i < 12; i++) {
++		if (i <= 2 && (value << FRAC_BITS) <= db_invert_table[i][7])
++			break;
++		else if (i > 2 && value <= db_invert_table[i][7])
++			break;
++	}
++
++	for (j = 0; j < 8; j++) {
++		if (i <= 2 && (value << FRAC_BITS) <= db_invert_table[i][j])
++			break;
++		else if (i > 2 && i < 12 && value <= db_invert_table[i][j])
++			break;
++	}
++
++	if (j == 0 && i == 0)
++		goto end;
++
++	if (j == 0) {
++		if (i != 3) {
++			if (db_invert_table[i][0] - value >
++			    value - db_invert_table[i - 1][7]) {
++				i = i - 1;
++				j = 7;
++			}
++		} else {
++			if (db_invert_table[3][0] - value >
++			    value - db_invert_table[2][7]) {
++				i = 2;
++				j = 7;
++			}
++		}
++	} else {
++		if (db_invert_table[i][j] - value >
++		    value - db_invert_table[i][j - 1]) {
++			i = i;
++			j = j - 1;
++		}
++	}
++end:
++	dB = (i << 3) + j + 1;
++
++	return dB;
++}
++
++u64 phydm_db_2_linear(u32 value)
++{
++	u8 i = 0;
++	u8 j = 0;
++	u64 linear = 0;
++
++	value = value & 0xFF;
++
++	/* @1dB~96dB */
++	if (value > 96) {
++		value = 96;
++	} else if (value < 1) {
++		linear = 1;
++		return linear;
++	}
++
++	i = (u8)((value - 1) >> 3);
++	j = (u8)(value - 1) - (i << 3);
++
++	linear = db_invert_table[i][j];
++
++	if (i > 2)
++		linear = linear << FRAC_BITS;
++
++	return linear;
++}
++
++u16 phydm_show_fraction_num(u32 frac_val, u8 bit_num)
++{
++	u8 i = 0;
++	u16 val = 0;
++	u16 base = 5000;
++
++	for (i = bit_num; i > 0; i--) {
++		if (frac_val & BIT(i - 1))
++			val += (base >> (bit_num - i));
++	}
++	return val;
++}
++
++u16 phydm_ones_num_in_bitmap(u64 val, u8 size)
++{
++	u8 i = 0;
++	u8 ones_num = 0;
++
++	for (i = 0; i < size; i++) {
++		if (val & BIT(0))
++			ones_num++;
++
++		val = val >> 1;
++	}
++
++	return ones_num;
++}
++
++u64 phydm_gen_bitmask(u8 mask_num)
++{
++	u8 i = 0;
++	u64 bitmask = 0;
++
++	if (mask_num > 64)
++		return 1;
++
++	for (i = 0; i < mask_num; i++)
++		bitmask = (bitmask << 1) | BIT(0);
++
++	return bitmask;
++}
++
++s32 phydm_cnvrt_2_sign(u32 val, u8 bit_num)
++{
++	if (bit_num >= 32)
++		return (s32)val;
++
++	if (val & BIT(bit_num - 1)) /*Sign BIT*/
++		val -= (1 << bit_num); /*@2's*/
++
++	return val;
++}
++
++s64 phydm_cnvrt_2_sign_64(u64 val, u8 bit_num)
++{
++	u64 one = 1;
++	s64 val_sign = (s64)val;
++
++	if (bit_num >= 64)
++		return (s64)val;
++
++	if (val & (one << (bit_num - 1))) /*Sign BIT*/
++		val_sign = val - (one << bit_num); /*@2's*/
++
++	return val_sign;
++}
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_math_lib.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_math_lib.h
+new file mode 100644
+index 000000000..a96ae5ee4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_math_lib.h
+@@ -0,0 +1,120 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_MATH_LIB_H__
++#define __PHYDM_MATH_LIB_H__
++
++/* @2019.01.24 remove linear2db debug log*/
++#define AUTO_MATH_LIB_VERSION "1.2"
++
++/*@
++ * 1 ============================================================
++ * 1  Definition
++ * 1 ============================================================
++ */
++
++#define PHYDM_DIV(a, b) ((b) ? ((a) / (b)) : 0)
++#define DIVIDED_2(X) ((X) >> 1)
++/*@1/3 ~ 11/32*/
++#if defined(DM_ODM_CE_MAC80211)
++#define DIVIDED_3(X) ({	\
++	u32 div_3_tmp = (X);	\
++	(((div_3_tmp) + ((div_3_tmp) << 1) + ((div_3_tmp) << 3)) >> 5); })
++#else
++#define DIVIDED_3(X) (((X) + ((X) << 1) + ((X) << 3)) >> 5)
++#endif
++#define DIVIDED_4(X) ((X) >> 2)
++
++/*Store Ori Value*/
++#if defined(DM_ODM_CE_MAC80211)
++#define WEIGHTING_AVG(v1, w1, v2, w2)	\
++	__WEIGHTING_AVG(v1, w1, v2, w2, typeof(v1), typeof(w1), typeof(v2), \
++			typeof(w2))
++#define __WEIGHTING_AVG(v1, w1, v2, w2, t1, t2, t3, t4)	({	\
++	t1 __w_a_v1 = (v1);	\
++	t2 __w_a_w1 = (w1);	\
++	t3 __w_a_v2 = (v2);	\
++	t4 __w_a_w2 = (w2);	\
++	((__w_a_v1) * (__w_a_w1) + (__w_a_v2) * (__w_a_w2))	\
++	/ ((__w_a_w2) + (__w_a_w1)); })
++#else
++#define WEIGHTING_AVG(v1, w1, v2, w2) \
++	(((v1) * (w1) + (v2) * (w2)) / ((w2) + (w1)))
++#endif
++
++/*Store 2^ma x Value*/
++#if defined(DM_ODM_CE_MAC80211)
++#define MA_ACC(old, new_val, ma) ({	\
++	s16 __ma_acc_o = (old);		\
++	(__ma_acc_o) - ((__ma_acc_o) >> (ma)) + (new_val); })
++#define GET_MA_VAL(val, ma) ({	\
++	s16 __get_ma_tmp = (ma);\
++	((val) + (1 << ((__get_ma_tmp) - 1))) >> (__get_ma_tmp); })
++#else
++#define MA_ACC(old, new_val, ma) ((old) - ((old) >> (ma)) + (new_val))
++#define GET_MA_VAL(val, ma) (((val) + (1 << ((ma) - 1))) >> (ma))
++#endif
++#define FRAC_BITS 3
++/*@
++ * 1 ============================================================
++ * 1  enumeration
++ * 1 ============================================================
++ */
++
++/*@
++ * 1 ============================================================
++ * 1  structure
++ * 1 ============================================================
++ */
++
++/*@
++ * 1 ============================================================
++ * 1  function prototype
++ * 1 ============================================================
++ */
++
++s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit);
++
++s32 odm_sign_conversion(s32 value, u32 total_bit);
++
++u16 phydm_find_intrvl(void *dm_void, u16 val, u16 *threshold, u16 th_len);
++
++void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
++		       u8 seq_length);
++
++u32 odm_convert_to_db(u64 value);
++
++u64 phydm_db_2_linear(u32 value);
++
++u16 phydm_show_fraction_num(u32 frac_val, u8 bit_num);
++
++u16 phydm_ones_num_in_bitmap(u64 val, u8 size);
++
++u64 phydm_gen_bitmask(u8 mask_num);
++
++s32 phydm_cnvrt_2_sign(u32 val, u8 bit_num);
++
++s64 phydm_cnvrt_2_sign_64(u64 val, u8 bit_num);
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_mp.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_mp.c
+new file mode 100644
+index 000000000..53ff6312c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_mp.c
+@@ -0,0 +1,302 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ ************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#ifdef PHYDM_MP_SUPPORT
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++
++void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
++				   u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_mp *mp = &dm->dm_mp_table;
++	u8 start = RF_PATH_A, end = RF_PATH_A;
++	u8 i = 0;
++
++	switch (path) {
++	case RF_PATH_A:
++	case RF_PATH_B:
++	case RF_PATH_C:
++	case RF_PATH_D:
++		start = path;
++		end = path;
++		break;
++	case RF_PATH_AB:
++		start = RF_PATH_A;
++		end = RF_PATH_B;
++		break;
++#if (defined(PHYDM_COMPILE_IC_4SS))
++	case RF_PATH_AC:
++		start = RF_PATH_A;
++		end = RF_PATH_C;
++		break;
++	case RF_PATH_AD:
++		start = RF_PATH_A;
++		end = RF_PATH_D;
++		break;
++	case RF_PATH_BC:
++		start = RF_PATH_B;
++		end = RF_PATH_C;
++		break;
++	case RF_PATH_BD:
++		start = RF_PATH_B;
++		end = RF_PATH_D;
++		break;
++	case RF_PATH_CD:
++		start = RF_PATH_C;
++		end = RF_PATH_D;
++		break;
++	case RF_PATH_ABC:
++		start = RF_PATH_A;
++		end = RF_PATH_C;
++		break;
++	case RF_PATH_ABD:
++		start = RF_PATH_A;
++		end = RF_PATH_D;
++		break;
++	case RF_PATH_ACD:
++		start = RF_PATH_A;
++		end = RF_PATH_D;
++		break;
++	case RF_PATH_BCD:
++		start = RF_PATH_B;
++		end = RF_PATH_D;
++		break;
++	case RF_PATH_ABCD:
++		start = RF_PATH_A;
++		end = RF_PATH_D;
++		break;
++#endif
++	}
++	if (is_single_tone) {
++		/* Disable CCK and OFDM */
++		odm_set_bb_reg(dm, R_0x1c3c, 0x3, 0x0);
++		for (i = start; i <= end; i++) {
++			/* @Tx mode: RF0x00[19:16]=4'b0010 */
++			odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
++			/*Lowest RF gain index: RF_0x0[4:0] = 0*/
++			odm_set_rf_reg(dm, i, RF_0x0, 0x1f, 0x0);
++			/*RF LO enabled */
++			odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
++		}
++		#if (RTL8814B_SUPPORT)
++		if (dm->support_ic_type & ODM_RTL8814B) {
++			/*Lowest RF gain index: RF_0x0[4:0] = 0x0*/
++			config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
++							0x1f, 0x0);
++			/*RF LO enabled */
++			config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
++							BIT(1), 0x1);
++			if (*dm->band_width == CHANNEL_WIDTH_80_80) {
++				/*SYN1*/
++				config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
++								RF_0x0, 0x1f,
++								0x0);
++				config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
++								RF_0x58, BIT(1),
++								0x1);
++			}
++		}
++		#endif
++	} else {
++		/*Enable CCK and OFDM */
++		odm_set_bb_reg(dm, R_0x1c3c, 0x3, 0x3);
++		/*RF LO disabled */
++		for (i = start; i <= end; i++)
++			odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
++		#if (RTL8814B_SUPPORT)
++		if (dm->support_ic_type & ODM_RTL8814B) {
++			config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
++							BIT(1), 0x1);
++			if (*dm->band_width == CHANNEL_WIDTH_80_80)
++				/*SYN1*/
++				config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
++								RF_0x58, BIT(1),
++								0x1);
++		}
++		#endif
++	}
++}
++
++void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp,
++				    u32 rate_index)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_mp *mp = &dm->dm_mp_table;
++
++	if (is_carrier_supp) {
++		if (phydm_is_cck_rate(dm, (u8)rate_index)) {
++			/*if CCK block on? */
++			if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
++				odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1);
++
++			/*Turn Off All Test mode */
++			odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
++
++			/*transmit mode */
++			odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2);
++			/*turn off scramble setting */
++			odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x0);
++			/*Set CCK Tx Test Rate, set FTxRate to 1Mbps */
++			odm_set_bb_reg(dm, R_0x1a00, 0x3000, 0x0);
++		}
++	} else { /*Stop Carrier Suppression. */
++		if (phydm_is_cck_rate(dm, (u8)rate_index)) {
++			/*normal mode */
++			odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);
++			/*turn on scramble setting */
++			odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1);
++			/*BB Reset */
++			odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
++			odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
++		}
++	}
++}
++
++void phydm_mp_set_single_carrier_jgr3(void *dm_void, boolean is_single_carrier)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_mp *mp = &dm->dm_mp_table;
++
++	if (is_single_carrier) {
++		/*1. if OFDM block on? */
++		if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
++			odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1);
++
++		/*2. set CCK test mode off, set to CCK normal mode */
++		odm_set_bb_reg(dm, R_0x1a00, 0x3, 0);
++
++		/*3. turn on scramble setting */
++		odm_set_bb_reg(dm, R_0x1a00, BIT(3), 1);
++
++		/*4. Turn On single carrier. */
++		odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
++	} else {
++		/*Turn off all test modes. */
++		odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_OFF);
++
++		/*Delay 10 ms */
++		ODM_delay_ms(10);
++
++		/*BB Reset*/
++		odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
++		odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
++	}
++}
++
++void phydm_mp_get_tx_ok_jgr3(void *dm_void, u32 rate_index)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_mp *mp = &dm->dm_mp_table;
++
++	if (phydm_is_cck_rate(dm, (u8)rate_index))
++		mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de4, MASKLWORD);
++	else
++		mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de0, MASKLWORD);
++}
++
++void phydm_mp_get_rx_ok_jgr3(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_mp *mp = &dm->dm_mp_table;
++
++	u32 cck_ok = 0, ofdm_ok = 0, ht_ok = 0, vht_ok = 0;
++	u32 cck_err = 0, ofdm_err = 0, ht_err = 0, vht_err = 0;
++
++	cck_ok = odm_get_bb_reg(dm, R_0x2c04, MASKLWORD);
++	ofdm_ok = odm_get_bb_reg(dm, R_0x2c14, MASKLWORD);
++	ht_ok = odm_get_bb_reg(dm, R_0x2c10, MASKLWORD);
++	vht_ok = odm_get_bb_reg(dm, R_0x2c0c, MASKLWORD);
++
++	cck_err = odm_get_bb_reg(dm, R_0x2c04, MASKHWORD);
++	ofdm_err = odm_get_bb_reg(dm, R_0x2c14, MASKHWORD);
++	ht_err = odm_get_bb_reg(dm, R_0x2c10, MASKHWORD);
++	vht_err = odm_get_bb_reg(dm, R_0x2c0c, MASKHWORD);
++
++	mp->rx_phy_ok_cnt = cck_ok + ofdm_ok + ht_ok + vht_ok;
++	mp->rx_phy_crc_err_cnt = cck_err + ofdm_err + ht_err + vht_err;
++	mp->io_value = (u32)mp->rx_phy_ok_cnt;
++}
++#endif
++void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	phydm_set_crystal_cap(dm, crystal_cap);
++}
++
++void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		phydm_mp_set_single_tone_jgr3(dm, is_single_tone, path);
++}
++
++void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,
++			       u32 rate_index)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		phydm_mp_set_carrier_supp_jgr3(dm, is_carrier_supp, rate_index);
++}
++
++void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		phydm_mp_set_single_carrier_jgr3(dm, is_single_carrier);
++}
++void phydm_mp_reset_rx_counters_phy(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	phydm_reset_bb_hw_cnt(dm);
++}
++
++void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		phydm_mp_get_tx_ok_jgr3(dm, rate_index);
++}
++
++void phydm_mp_get_rx_ok(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		phydm_mp_get_rx_ok_jgr3(dm);
++}
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_mp.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_mp.h
+new file mode 100644
+index 000000000..c09cff1f3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_mp.h
+@@ -0,0 +1,78 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_MP_H__
++#define __PHYDM_MP_H__
++
++/*2019.07.31 Refine code Structure */
++#define MP_VERSION "1.4"
++
++/* @1 ============================================================
++ * 1  Definition
++ * 1 ============================================================
++ */
++/* @1 ============================================================
++ * 1  structure
++ * 1 ============================================================
++ */
++struct phydm_mp {
++	/*Rx OK count, statistics used in Mass Production Test.*/
++	u64 tx_phy_ok_cnt;
++	u64 rx_phy_ok_cnt;
++	/*Rx CRC32 error count, statistics used in Mass Production Test.*/
++	u64 rx_phy_crc_err_cnt;
++	/*The Value of IO operation is depend of MptActType.*/
++	u32 io_value;
++};
++
++/* @1 ============================================================
++ * 1  enumeration
++ * 1 ============================================================
++ */
++enum TX_MODE_OFDM {
++	OFDM_OFF = 0,	
++	OFDM_CONT_TX = 1,
++	OFDM_SINGLE_CARRIER = 2,
++	OFDM_SINGLE_TONE = 4,
++};
++/* @1 ============================================================
++ * 1  function prototype
++ * 1 ============================================================
++ */
++void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap);
++
++void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path);
++
++void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,
++			       u32 rate_index);
++
++void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier);
++
++void phydm_mp_reset_rx_counters_phy(void *dm_void);
++
++void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index);
++
++void phydm_mp_get_rx_ok(void *dm_void);
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_noisemonitor.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_noisemonitor.c
+new file mode 100644
+index 000000000..d2e95cfa0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_noisemonitor.c
+@@ -0,0 +1,467 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*************************************************************
++ * include files
++ ************************************************************/
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++/**************************************************
++ * This function is for inband noise test utility only
++ * To obtain the inband noise level(dbm), do the following.
++ * 1. disable DIG and Power Saving
++ * 2. Set initial gain = 0x1a
++ * 3. Stop updating idle time pwer report (for driver read)
++ *	- 0x80c[25]
++ *
++ *************************************************/
++
++void phydm_set_noise_data_sum(struct noise_level *noise_data, u8 max_rf_path)
++{
++	u8 i = 0;
++
++	for (i = RF_PATH_A; i < max_rf_path; i++) {
++		if (noise_data->valid_cnt[i])
++			noise_data->sum[i] /= noise_data->valid_cnt[i];
++		else
++			noise_data->sum[i] = 0;
++	}
++}
++
++#if (ODM_IC_11N_SERIES_SUPPORT)
++s16 odm_inband_noise_monitor_n(struct dm_struct *dm, u8 is_pause_dig, u8 igi,
++			       u32 max_time)
++{
++	u32 tmp4b;
++	u8 max_rf_path = 0, i = 0;
++	u8 reg_c50, reg_c58, valid_done = 0;
++	struct noise_level noise_data;
++	u64 start = 0, func_start = 0, func_end = 0;
++	s8 val_s8 = 0;
++
++	func_start = odm_get_current_time(dm);
++	dm->noise_level.noise_all = 0;
++
++	if (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R)
++		max_rf_path = 2;
++	else
++		max_rf_path = 1;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR,
++		  "odm_DebugControlInbandNoise_Nseries() ==>\n");
++
++	odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));
++	/* step 1. Disable DIG && Set initial gain. */
++
++	if (is_pause_dig)
++		odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
++
++	/* step 3. Get noise power level */
++	start = odm_get_current_time(dm);
++	while (1) {
++		/* Stop updating idle time pwer report (for driver read) */
++		odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1);
++
++		/* Read Noise Floor Report */
++		tmp4b = odm_get_bb_reg(dm, R_0x8f8, MASKDWORD);
++
++		/* update idle time pwer report per 5us */
++		odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0);
++
++		ODM_delay_us(5);
++
++		noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff);
++		noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
++
++		for (i = RF_PATH_A; i < max_rf_path; i++) {
++			noise_data.sval[i] = (s8)noise_data.value[i];
++			noise_data.sval[i] /= 2;
++		}
++
++		for (i = RF_PATH_A; i < max_rf_path; i++) {
++			if (noise_data.valid_cnt[i] >= VALID_CNT)
++				continue;
++
++			noise_data.valid_cnt[i]++;
++			noise_data.sum[i] += noise_data.sval[i];
++			PHYDM_DBG(dm, DBG_ENV_MNTR,
++				  "rf_path:%d Valid sval=%d\n", i,
++				  noise_data.sval[i]);
++			PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n",
++				  noise_data.sum[i]);
++			if (noise_data.valid_cnt[i] == VALID_CNT)
++				valid_done++;
++		}
++		if (valid_done == max_rf_path ||
++		    (odm_get_progressing_time(dm, start) > max_time)) {
++			phydm_set_noise_data_sum(&noise_data, max_rf_path);
++			break;
++		}
++	}
++	reg_c50 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0);
++	reg_c50 &= ~BIT(7);
++	val_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);
++	dm->noise_level.noise[RF_PATH_A] = val_s8;
++	dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A];
++
++	if (max_rf_path == 2) {
++		reg_c58 = (u8)odm_get_bb_reg(dm, R_0xc58, MASKBYTE0);
++		reg_c58 &= ~BIT(7);
++		val_s8 = (s8)(-110 + reg_c58 + noise_data.sum[RF_PATH_B]);
++		dm->noise_level.noise[RF_PATH_B] = val_s8;
++		dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B];
++	}
++	dm->noise_level.noise_all /= max_rf_path;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR,
++		  "noise_a = %d, noise_b = %d, noise_all = %d\n",
++		  dm->noise_level.noise[RF_PATH_A],
++		  dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all);
++
++	/* step 4. Recover the Dig */
++	if (is_pause_dig)
++		odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
++	func_end = odm_get_progressing_time(dm, func_start);
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n");
++	return dm->noise_level.noise_all;
++}
++#endif
++
++#if (ODM_IC_11AC_SERIES_SUPPORT)
++s16 phydm_idle_noise_measure_ac(struct dm_struct *dm, u8 pause_dig,
++				u8 igi, u32 max_time)
++{
++	u32 tmp4b;
++	u8 max_rf_path = 0, i = 0;
++	u8 reg_c50, reg_e50, valid_done = 0;
++	u64 start = 0, func_start = 0, func_end = 0;
++	struct noise_level noise_data;
++	s8 val_s8 = 0;
++
++	func_start = odm_get_current_time(dm);
++	dm->noise_level.noise_all = 0;
++
++	if (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R)
++		max_rf_path = 2;
++	else
++		max_rf_path = 1;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "%s==>\n", __func__);
++
++	odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));
++
++	/*Step 1. Disable DIG && Set initial gain.*/
++
++	if (pause_dig)
++		odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
++
++	/*Step 2. Get noise power level*/
++	start = odm_get_current_time(dm);
++
++	while (1) {
++		/*Stop updating idle time pwer report (for driver read)*/
++		odm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x1);
++
++		/*Read Noise Floor Report*/
++		tmp4b = odm_get_bb_reg(dm, R_0xff0, MASKDWORD);
++
++		/*update idle time pwer report per 5us*/
++		odm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x0);
++
++		ODM_delay_us(5);
++
++		noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff);
++		noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
++
++		for (i = RF_PATH_A; i < max_rf_path; i++) {
++			noise_data.sval[i] = (s8)noise_data.value[i];
++			noise_data.sval[i] = noise_data.sval[i] >> 1;
++		}
++
++		for (i = RF_PATH_A; i < max_rf_path; i++) {
++			if (noise_data.valid_cnt[i] >= VALID_CNT)
++				continue;
++
++			noise_data.valid_cnt[i]++;
++			noise_data.sum[i] += noise_data.sval[i];
++			PHYDM_DBG(dm, DBG_ENV_MNTR, "Path:%d Valid sval = %d\n",
++				  i, noise_data.sval[i]);
++			PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d\n",
++				  noise_data.sum[i]);
++			if (noise_data.valid_cnt[i] == VALID_CNT)
++				valid_done++;
++		}
++
++		if (valid_done == max_rf_path ||
++		    (odm_get_progressing_time(dm, start) > max_time)) {
++			phydm_set_noise_data_sum(&noise_data, max_rf_path);
++			break;
++		}
++	}
++	reg_c50 = (u8)odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
++	reg_c50 &= ~BIT(7);
++	val_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);
++	dm->noise_level.noise[RF_PATH_A] = val_s8;
++	dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A];
++
++	if (max_rf_path == 2) {
++		reg_e50 = (u8)odm_get_bb_reg(dm, R_0xe50, MASKBYTE0);
++		reg_e50 &= ~BIT(7);
++		val_s8 = (s8)(-110 + reg_e50 + noise_data.sum[RF_PATH_B]);
++		dm->noise_level.noise[RF_PATH_B] = val_s8;
++		dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B];
++	}
++	dm->noise_level.noise_all /= max_rf_path;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR,
++		  "noise_a = %d, noise_b = %d, noise_all = %d\n",
++		  dm->noise_level.noise[RF_PATH_A],
++		  dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all);
++
++	/*Step 3. Recover the Dig*/
++	if (pause_dig)
++		odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
++	func_end = odm_get_progressing_time(dm, func_start);
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n");
++	return dm->noise_level.noise_all;
++}
++
++s16 odm_inband_noise_monitor_ac(struct dm_struct *dm, u8 pause_dig, u8 igi,
++				u32 max_time)
++{
++	s32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/
++	s32 value32, pwdb_A = 0, sval, noise, sum = 0;
++	boolean pd_flag;
++	u8 valid_cnt = 0;
++	u8 invalid_cnt = 0;
++	u64 start = 0, func_start = 0, func_end = 0, proc_time = 0;
++	s32 val_s32 = 0;
++	s16 rpt = 0;
++	u8 val_u8 = 0;
++
++	if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
++		rpt = phydm_idle_noise_measure_ac(dm, pause_dig, igi, max_time);
++		return rpt;
++	}
++
++	if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A)))
++		return 0;
++
++	func_start = odm_get_current_time(dm);
++	dm->noise_level.noise_all = 0;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "%s ==>\n", __func__);
++
++	/* step 1. Disable DIG && Set initial gain. */
++	if (pause_dig)
++		odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
++
++	/* step 3. Get noise power level */
++	start = odm_get_current_time(dm);
++
++	/* step 3. Get noise power level */
++	while (1) {
++		/*Set IGI=0x1C */
++		odm_write_dig(dm, 0x1C);
++		/*stop CK320&CK88 */
++		odm_set_bb_reg(dm, R_0x8b4, BIT(6), 1);
++		/*Read path-A */
++		/*set debug port*/
++		odm_set_bb_reg(dm, R_0x8fc, MASKDWORD, 0x200);
++		/*read debug port*/
++		value32 = odm_get_bb_reg(dm, R_0xfa0, MASKDWORD);
++		/*rxi_buf_anta=RegFA0[19:10]*/
++		rxi_buf_anta = (value32 & 0xFFC00) >> 10;
++		rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/
++
++		pd_flag = (boolean)((value32 & BIT(31)) >> 31);
++
++		/*Not in packet detection period or Tx state */
++		if (!pd_flag || rxi_buf_anta != 0x200) {
++			/*sign conversion*/
++			rxi_buf_anta = odm_sign_conversion(rxi_buf_anta, 10);
++			rxq_buf_anta = odm_sign_conversion(rxq_buf_anta, 10);
++
++			val_s32 = rxi_buf_anta * rxi_buf_anta +
++				  rxq_buf_anta * rxq_buf_anta;
++			/*S(10,9)*S(10,9)=S(20,18)*/
++			pwdb_A = odm_pwdb_conversion(val_s32, 20, 18);
++
++			PHYDM_DBG(dm, DBG_ENV_MNTR,
++				  "pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n",
++				  pwdb_A, rxi_buf_anta & 0x3FF,
++				  rxq_buf_anta & 0x3FF);
++		}
++		/*Start CK320&CK88*/
++		odm_set_bb_reg(dm, R_0x8b4, BIT(6), 0);
++		/*@BB Reset*/
++		val_u8 = odm_read_1byte(dm, 0x02) & (~BIT(0));
++		odm_write_1byte(dm, 0x02, val_u8);
++		val_u8 = odm_read_1byte(dm, 0x02) | BIT(0);
++		odm_write_1byte(dm, 0x02, val_u8);
++		/*PMAC Reset*/
++		val_u8 = odm_read_1byte(dm, 0xB03) & (~BIT(0));
++		odm_write_1byte(dm, 0xB03, val_u8);
++		val_u8 = odm_read_1byte(dm, 0xB03) | BIT(0);
++		odm_write_1byte(dm, 0xB03, val_u8);
++		/*@CCK Reset*/
++		if (odm_read_1byte(dm, 0x80B) & BIT(4)) {
++			val_u8 = odm_read_1byte(dm, 0x80B) & (~BIT(4));
++			odm_write_1byte(dm, 0x80B, val_u8);
++			val_u8 = odm_read_1byte(dm, 0x80B) | BIT(4);
++			odm_write_1byte(dm, 0x80B, val_u8);
++		}
++
++		sval = pwdb_A;
++
++		if ((sval < 0 && sval >= -27) && valid_cnt < VALID_CNT) {
++			valid_cnt++;
++			sum += sval;
++			PHYDM_DBG(dm, DBG_ENV_MNTR, "Valid sval = %d\n", sval);
++			PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n", sum);
++			if (valid_cnt >= VALID_CNT ||
++			    (odm_get_progressing_time(dm, start) > max_time)) {
++				sum /= VALID_CNT;
++				PHYDM_DBG(dm, DBG_ENV_MNTR,
++					  "After divided, sum = %d\n", sum);
++				break;
++			}
++		} else {
++			/*Invalid sval and return -110 dBm*/
++			invalid_cnt++;
++			PHYDM_DBG(dm, DBG_ENV_MNTR, "Invalid sval\n");
++			if (invalid_cnt >= VALID_CNT + 5) {
++				PHYDM_DBG(dm, DBG_ENV_MNTR,
++					  "Invalid count > TH, Return -110, Break!!\n");
++				return -110;
++			}
++		}
++	}
++
++	/*@ADC backoff is 12dB,*/
++	/*Ptarget=0x1C-110=-82dBm*/
++	noise = sum + 12 + 0x1C - 110;
++
++	/*Offset*/
++	noise = noise - 3;
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "noise = %d\n", noise);
++	dm->noise_level.noise_all = (s16)noise;
++
++	/* step 4. Recover the Dig*/
++	if (pause_dig)
++		odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
++
++	func_end = odm_get_progressing_time(dm, func_start);
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR, "%s <==\n", __func__);
++
++	return dm->noise_level.noise_all;
++}
++#endif
++
++s16 odm_inband_noise_monitor(void *dm_void, u8 pause_dig, u8 igi,
++			     u32 max_time)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	s16 val = 0;
++
++	igi = 0x32;
++
++	/* since HW ability is about +15~-35,
++	 * we fix IGI = -60 for maximum coverage
++	 */
++	#if (ODM_IC_11AC_SERIES_SUPPORT)
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
++		val = odm_inband_noise_monitor_ac(dm, pause_dig, igi, max_time);
++	#endif
++
++	#if (ODM_IC_11N_SERIES_SUPPORT)
++	if (dm->support_ic_type & ODM_IC_11N_SERIES)
++		val = odm_inband_noise_monitor_n(dm, pause_dig, igi, max_time);
++	#endif
++
++	return val;
++}
++
++void phydm_noisy_detection(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 total_fa_cnt, total_cca_cnt;
++	u32 score = 0, i, score_smooth;
++
++	total_cca_cnt = dm->false_alm_cnt.cnt_cca_all;
++	total_fa_cnt = dm->false_alm_cnt.cnt_all;
++
++#if 0
++	if (total_fa_cnt * 16 >= total_cca_cnt * 14)    /*  @87.5 */
++		;
++	else if (total_fa_cnt * 16 >= total_cca_cnt * 12) /*  @75 */
++		;
++	else if (total_fa_cnt * 16 >= total_cca_cnt * 10) /*  @56.25 */
++		;
++	else if (total_fa_cnt * 16 >= total_cca_cnt * 8) /*  @50 */
++		;
++	else if (total_fa_cnt * 16 >= total_cca_cnt * 7) /*  @43.75 */
++		;
++	else if (total_fa_cnt * 16 >= total_cca_cnt * 6) /*  @37.5 */
++		;
++	else if (total_fa_cnt * 16 >= total_cca_cnt * 5) /*  @31.25% */
++		;
++	else if (total_fa_cnt * 16 >= total_cca_cnt * 4) /*  @25% */
++		;
++	else if (total_fa_cnt * 16 >= total_cca_cnt * 3) /*  @18.75% */
++		;
++	else if (total_fa_cnt * 16 >= total_cca_cnt * 2) /*  @12.5% */
++		;
++	else if (total_fa_cnt * 16 >= total_cca_cnt * 1) /*  @6.25% */
++		;
++#endif
++	for (i = 0; i <= 16; i++) {
++		if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) {
++			score = 16 - i;
++			break;
++		}
++	}
++
++	/* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */
++	dm->noisy_decision_smooth = (dm->noisy_decision_smooth >> 1) +
++				    (score << 2);
++
++	/* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */
++	if (total_cca_cnt >= 300)
++		score_smooth = (dm->noisy_decision_smooth + 3) >> 3;
++	else
++		score_smooth = 0;
++
++	dm->noisy_decision = (score_smooth >= 3) ? 1 : 0;
++
++	PHYDM_DBG(dm, DBG_ENV_MNTR,
++		  "[NoisyDetection] CCA_cnt=%d,FA_cnt=%d, noisy_dec_smooth=%d, score=%d, score_smooth=%d, noisy_dec=%d\n",
++		  total_cca_cnt, total_fa_cnt, dm->noisy_decision_smooth, score,
++		  score_smooth, dm->noisy_decision);
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_noisemonitor.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_noisemonitor.h
+new file mode 100644
+index 000000000..507285adb
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_noisemonitor.h
+@@ -0,0 +1,48 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++#ifndef __ODMNOISEMONITOR_H__
++#define __ODMNOISEMONITOR_H__
++
++#define VALID_CNT 5
++
++struct noise_level {
++	u8 value[PHYDM_MAX_RF_PATH];
++	s8 sval[PHYDM_MAX_RF_PATH];
++	s32 sum[PHYDM_MAX_RF_PATH];
++	u8 valid[PHYDM_MAX_RF_PATH];
++	u8 valid_cnt[PHYDM_MAX_RF_PATH];
++};
++
++struct odm_noise_monitor {
++	s8 noise[PHYDM_MAX_RF_PATH];
++	s16 noise_all;
++};
++
++s16 odm_inband_noise_monitor(void *dm_void, u8 is_pause_dig, u8 igi_value,
++			     u32 max_time);
++
++void phydm_noisy_detection(void *dm_void);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pathdiv.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pathdiv.c
+new file mode 100644
+index 000000000..8fb85612e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pathdiv.c
+@@ -0,0 +1,1115 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*************************************************************
++ * include files
++ ************************************************************/
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#ifdef CONFIG_PATH_DIVERSITY
++#if RTL8814A_SUPPORT
++void phydm_dtp_fix_tx_path(
++	void *dm_void,
++	u8 path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++	u8 i, num_enable_path = 0;
++
++	if (path == p_div->pre_tx_path)
++		return;
++	else
++		p_div->pre_tx_path = path;
++
++	odm_set_bb_reg(dm, R_0x93c, BIT(18) | BIT(19), 3);
++
++	for (i = 0; i < 4; i++) {
++		if (path & BIT(i))
++			num_enable_path++;
++	}
++	PHYDM_DBG(dm, DBG_PATH_DIV, " number of turn-on path : (( %d ))\n",
++		  num_enable_path);
++
++	if (num_enable_path == 1) {
++		odm_set_bb_reg(dm, R_0x93c, 0xf00000, path);
++
++		if (path == BB_PATH_A) { /* @1-1 */
++			PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A ))\n");
++			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
++		} else if (path == BB_PATH_B) { /* @1-2 */
++			PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( B ))\n");
++			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0);
++		} else if (path == BB_PATH_C) { /* @1-3 */
++			PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( C ))\n");
++			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 0);
++
++		} else if (path == BB_PATH_D) { /* @1-4 */
++			PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( D ))\n");
++			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 0);
++		}
++
++	} else if (num_enable_path == 2) {
++		odm_set_bb_reg(dm, R_0x93c, 0xf00000, path);
++		odm_set_bb_reg(dm, R_0x940, 0xf0, path);
++
++		if (path == (BB_PATH_AB)) { /* @2-1 */
++			PHYDM_DBG(dm, DBG_PATH_DIV,
++				  " Turn on path (( A B ))\n");
++			/* set for 1ss */
++			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
++			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1);
++			/* set for 2ss */
++			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
++			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1);
++		} else if (path == BB_PATH_AC) { /* @2-2 */
++			PHYDM_DBG(dm, DBG_PATH_DIV,
++				  " Turn on path (( A C ))\n");
++			/* set for 1ss */
++			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
++			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1);
++			/* set for 2ss */
++			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
++			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1);
++		} else if (path == BB_PATH_AD) { /* @2-3 */
++			PHYDM_DBG(dm, DBG_PATH_DIV,
++				  " Turn on path (( A D ))\n");
++			/* set for 1ss */
++			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
++			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1);
++			/* set for 2ss */
++			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
++			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1);
++		} else if (path == BB_PATH_BC) { /* @2-4 */
++			PHYDM_DBG(dm, DBG_PATH_DIV,
++				  " Turn on path (( B C ))\n");
++			/* set for 1ss */
++			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0);
++			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1);
++			/* set for 2ss */
++			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0);
++			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1);
++		} else if (path == BB_PATH_BD) { /* @2-5 */
++			PHYDM_DBG(dm, DBG_PATH_DIV,
++				  " Turn on path (( B D ))\n");
++			/* set for 1ss */
++			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0);
++			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1);
++			/* set for 2ss */
++			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0);
++			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1);
++		} else if (path == BB_PATH_CD) { /* @2-6 */
++			PHYDM_DBG(dm, DBG_PATH_DIV,
++				  " Turn on path (( C D ))\n");
++			/* set for 1ss */
++			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 0);
++			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1);
++			/* set for 2ss */
++			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 0);
++			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1);
++		}
++
++	} else if (num_enable_path == 3) {
++		odm_set_bb_reg(dm, R_0x93c, 0xf00000, path);
++		odm_set_bb_reg(dm, R_0x940, 0xf0, path);
++		odm_set_bb_reg(dm, R_0x940, 0xf0000, path);
++
++		if (path == BB_PATH_ABC) { /* @3-1 */
++			PHYDM_DBG(dm, DBG_PATH_DIV,
++				  " Turn on path (( A B C))\n");
++			/* set for 1ss */
++			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
++			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1);
++			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 2);
++			/* set for 2ss */
++			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
++			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1);
++			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 2);
++			/* set for 3ss */
++			odm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0);
++			odm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 1);
++			odm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 2);
++		} else if (path == BB_PATH_ABD) { /* @3-2 */
++			PHYDM_DBG(dm, DBG_PATH_DIV,
++				  " Turn on path (( A B D ))\n");
++			/* set for 1ss */
++			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
++			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1);
++			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2);
++			/* set for 2ss */
++			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
++			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1);
++			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2);
++			/* set for 3ss */
++			odm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0);
++			odm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 1);
++			odm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2);
++
++		} else if (path == BB_PATH_ACD) { /* @3-3 */
++			PHYDM_DBG(dm, DBG_PATH_DIV,
++				  " Turn on path (( A C D ))\n");
++			/* set for 1ss */
++			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
++			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1);
++			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2);
++			/* set for 2ss */
++			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
++			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1);
++			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2);
++			/* set for 3ss */
++			odm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0);
++			odm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 1);
++			odm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2);
++		} else if (path == BB_PATH_BCD) { /* @3-4 */
++			PHYDM_DBG(dm, DBG_PATH_DIV,
++				  " Turn on path (( B C D))\n");
++			/* set for 1ss */
++			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0);
++			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1);
++			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2);
++			/* set for 2ss */
++			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0);
++			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1);
++			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2);
++			/* set for 3ss */
++			odm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 0);
++			odm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 1);
++			odm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2);
++		}
++	} else if (num_enable_path == 4)
++		PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path ((A  B C D))\n");
++}
++
++void phydm_find_default_path(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++	u32 rssi_a = 0, rssi_b = 0, rssi_c = 0, rssi_d = 0, rssi_bcd = 0;
++	u32 rssi_total_a = 0, rssi_total_b = 0;
++	u32 rssi_total_c = 0, rssi_total_d = 0;
++
++	/* @2 Default path Selection By RSSI */
++
++	rssi_a = (p_div->path_a_cnt_all > 0) ?
++		 (p_div->path_a_sum_all / p_div->path_a_cnt_all) : 0;
++	rssi_b = (p_div->path_b_cnt_all > 0) ?
++		 (p_div->path_b_sum_all / p_div->path_b_cnt_all) : 0;
++	rssi_c = (p_div->path_c_cnt_all > 0) ?
++		 (p_div->path_c_sum_all / p_div->path_c_cnt_all) : 0;
++	rssi_d = (p_div->path_d_cnt_all > 0) ?
++		 (p_div->path_d_sum_all / p_div->path_d_cnt_all) : 0;
++
++	p_div->path_a_sum_all = 0;
++	p_div->path_a_cnt_all = 0;
++	p_div->path_b_sum_all = 0;
++	p_div->path_b_cnt_all = 0;
++	p_div->path_c_sum_all = 0;
++	p_div->path_c_cnt_all = 0;
++	p_div->path_d_sum_all = 0;
++	p_div->path_d_cnt_all = 0;
++
++	if (p_div->use_path_a_as_default_ant == 1) {
++		rssi_bcd = (rssi_b + rssi_c + rssi_d) / 3;
++
++		if ((rssi_a + ANT_DECT_RSSI_TH) > rssi_bcd) {
++			p_div->is_path_a_exist = true;
++			p_div->default_path = PATH_A;
++		} else {
++			p_div->is_path_a_exist = false;
++		}
++	} else {
++		if (rssi_a >= rssi_b &&
++		    rssi_a >= rssi_c &&
++		    rssi_a >= rssi_d)
++			p_div->default_path = PATH_A;
++		else if ((rssi_b >= rssi_c) && (rssi_b >= rssi_d))
++			p_div->default_path = PATH_B;
++		else if (rssi_c >= rssi_d)
++			p_div->default_path = PATH_C;
++		else
++			p_div->default_path = PATH_D;
++	}
++}
++
++void phydm_candidate_dtp_update(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++
++	p_div->num_candidate = 3;
++
++	if (p_div->use_path_a_as_default_ant == 1) {
++		if (p_div->num_tx_path == 3) {
++			if (p_div->is_path_a_exist) {
++				p_div->ant_candidate_1 = BB_PATH_ABC;
++				p_div->ant_candidate_2 = BB_PATH_ABD;
++				p_div->ant_candidate_3 = BB_PATH_ACD;
++			} else { /* use path BCD */
++				p_div->num_candidate = 1;
++				phydm_dtp_fix_tx_path(dm, BB_PATH_BCD);
++				return;
++			}
++		} else if (p_div->num_tx_path == 2) {
++			if (p_div->is_path_a_exist) {
++				p_div->ant_candidate_1 = BB_PATH_AB;
++				p_div->ant_candidate_2 = BB_PATH_AC;
++				p_div->ant_candidate_3 = BB_PATH_AD;
++			} else {
++				p_div->ant_candidate_1 = BB_PATH_BC;
++				p_div->ant_candidate_2 = BB_PATH_BD;
++				p_div->ant_candidate_3 = BB_PATH_CD;
++			}
++		}
++	} else {
++		/* @2 3 TX mode */
++		if (p_div->num_tx_path == 3) { /* @choose 3 ant form 4 */
++			if (p_div->default_path == PATH_A) {
++			/* @choose 2 ant form 3 */
++				p_div->ant_candidate_1 = BB_PATH_ABC;
++				p_div->ant_candidate_2 = BB_PATH_ABD;
++				p_div->ant_candidate_3 = BB_PATH_ACD;
++			} else if (p_div->default_path == PATH_B) {
++				p_div->ant_candidate_1 = BB_PATH_ABC;
++				p_div->ant_candidate_2 = BB_PATH_ABD;
++				p_div->ant_candidate_3 = BB_PATH_BCD;
++			} else if (p_div->default_path == PATH_C) {
++				p_div->ant_candidate_1 = BB_PATH_ABC;
++				p_div->ant_candidate_2 = BB_PATH_ACD;
++				p_div->ant_candidate_3 = BB_PATH_BCD;
++			} else if (p_div->default_path == PATH_D) {
++				p_div->ant_candidate_1 = BB_PATH_ABD;
++				p_div->ant_candidate_2 = BB_PATH_ACD;
++				p_div->ant_candidate_3 = BB_PATH_BCD;
++			}
++		}
++
++		/* @2 2 TX mode */
++		else if (p_div->num_tx_path == 2) { /* @choose 2 ant form 4 */
++			if (p_div->default_path == PATH_A) {
++			/* @choose 2 ant form 3 */
++				p_div->ant_candidate_1 = BB_PATH_AB;
++				p_div->ant_candidate_2 = BB_PATH_AC;
++				p_div->ant_candidate_3 = BB_PATH_AD;
++			} else if (p_div->default_path == PATH_B) {
++				p_div->ant_candidate_1 = BB_PATH_AB;
++				p_div->ant_candidate_2 = BB_PATH_BC;
++				p_div->ant_candidate_3 = BB_PATH_BD;
++			} else if (p_div->default_path == PATH_C) {
++				p_div->ant_candidate_1 = BB_PATH_AC;
++				p_div->ant_candidate_2 = BB_PATH_BC;
++				p_div->ant_candidate_3 = BB_PATH_CD;
++			} else if (p_div->default_path == PATH_D) {
++				p_div->ant_candidate_1 = BB_PATH_AD;
++				p_div->ant_candidate_2 = BB_PATH_BD;
++				p_div->ant_candidate_3 = BB_PATH_CD;
++			}
++		}
++	}
++}
++
++void phydm_dynamic_tx_path(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++
++	struct sta_info *entry;
++	u32 i;
++	u8 num_client = 0;
++	u8 h2c_parameter[6] = {0};
++
++	if (!dm->is_linked) { /* @is_linked==False */
++		PHYDM_DBG(dm, DBG_PATH_DIV, "DTP_8814 [No Link!!!]\n");
++
++		if (p_div->is_become_linked) {
++			PHYDM_DBG(dm, DBG_PATH_DIV, "[Be disconnected]---->\n");
++			p_div->is_become_linked = dm->is_linked;
++		}
++		return;
++	} else {
++		if (!p_div->is_become_linked) {
++			PHYDM_DBG(dm, DBG_PATH_DIV, " [Be Linked !!!]----->\n");
++			p_div->is_become_linked = dm->is_linked;
++		}
++	}
++
++	/* @2 [period CTRL] */
++	if (p_div->dtp_period >= 2) {
++		p_div->dtp_period = 0;
++	} else {
++		p_div->dtp_period++;
++		return;
++	}
++
++	/* @2 [Fix path] */
++	if (dm->path_select != PHYDM_AUTO_PATH)
++		return;
++
++/* @2 [Check Bfer] */
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++	{
++		enum beamforming_cap beamform_cap = (dm->beamforming_info.beamform_cap);
++
++		if (beamform_cap & BEAMFORMER_CAP) { /* @BFmer On  &&   Div On->Div Off */
++			if (p_div->fix_path_bfer == 0) {
++				PHYDM_DBG(dm, DBG_PATH_DIV,
++					  "[ PathDiv : OFF ]   BFmer ==1\n");
++				p_div->fix_path_bfer = 1;
++			}
++			return;
++		} else { /* @BFmer Off   &&   Div Off->Div On */
++			if (p_div->fix_path_bfer == 1) {
++				PHYDM_DBG(dm, DBG_PATH_DIV,
++					  "[ PathDiv : ON ]   BFmer ==0\n");
++				p_div->fix_path_bfer = 0;
++			}
++		}
++	}
++#endif
++#endif
++
++	if (p_div->use_path_a_as_default_ant == 1) {
++		phydm_find_default_path(dm);
++		phydm_candidate_dtp_update(dm);
++	} else {
++		if (p_div->phydm_dtp_state == PHYDM_DTP_INIT) {
++			phydm_find_default_path(dm);
++			phydm_candidate_dtp_update(dm);
++			p_div->phydm_dtp_state = PHYDM_DTP_RUNNING_1;
++		}
++
++		else if (p_div->phydm_dtp_state == PHYDM_DTP_RUNNING_1) {
++			p_div->dtp_check_patha_counter++;
++
++			if (p_div->dtp_check_patha_counter >=
++			    NUM_RESET_DTP_PERIOD) {
++				p_div->dtp_check_patha_counter = 0;
++				p_div->phydm_dtp_state = PHYDM_DTP_INIT;
++			}
++#if 0
++			/* @2 Search space update */
++			else {
++				/* @1.  find the worst candidate */
++
++
++				/* @2. repalce the worst candidate */
++			}
++#endif
++		}
++	}
++
++	/* @2 Dynamic path Selection H2C */
++
++	if (p_div->num_candidate == 1) {
++		return;
++	} else {
++		h2c_parameter[0] = p_div->num_candidate;
++		h2c_parameter[1] = p_div->num_tx_path;
++		h2c_parameter[2] = p_div->ant_candidate_1;
++		h2c_parameter[3] = p_div->ant_candidate_2;
++		h2c_parameter[4] = p_div->ant_candidate_3;
++
++		odm_fill_h2c_cmd(dm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, h2c_parameter);
++	}
++}
++
++void phydm_dynamic_tx_path_init(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++	void *adapter = dm->adapter;
++	u8 search_space_2[NUM_CHOOSE2_FROM4] = {BB_PATH_AB, BB_PATH_AC, BB_PATH_AD, BB_PATH_BC, BB_PATH_BD, BB_PATH_CD};
++	u8 search_space_3[NUM_CHOOSE3_FROM4] = {BB_PATH_BCD, BB_PATH_ACD, BB_PATH_ABD, BB_PATH_ABC};
++
++#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT)
++	p_div->is_u3_mode = (*dm->hub_usb_mode == 2) ? 1 : 0;
++	PHYDM_DBG(dm, DBG_PATH_DIV, "[WIN USB] is_u3_mode = (( %d ))\n",
++		  p_div->is_u3_mode);
++#else
++	p_div->is_u3_mode = 1;
++#endif
++	PHYDM_DBG(dm, DBG_PATH_DIV, "Dynamic TX path Init 8814\n");
++
++	memcpy(&p_div->search_space_2[0], &search_space_2[0],
++	       NUM_CHOOSE2_FROM4);
++	memcpy(&p_div->search_space_3[0], &search_space_3[0],
++	       NUM_CHOOSE3_FROM4);
++
++	p_div->use_path_a_as_default_ant = 1;
++	p_div->phydm_dtp_state = PHYDM_DTP_INIT;
++	dm->path_select = PHYDM_AUTO_PATH;
++	p_div->phydm_path_div_type = PHYDM_4R_PATH_DIV;
++
++	if (p_div->is_u3_mode) {
++		p_div->num_tx_path = 3;
++		phydm_dtp_fix_tx_path(dm, BB_PATH_BCD); /* @3TX  Set Init TX path*/
++
++	} else {
++		p_div->num_tx_path = 2;
++		phydm_dtp_fix_tx_path(dm, BB_PATH_BC); /* @2TX // Set Init TX path*/
++	}
++}
++
++void phydm_process_rssi_for_path_div_8814a(void *dm_void, void *phy_info_void,
++					   void *pkt_info_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_phyinfo_struct *phy_info = NULL;
++	struct phydm_perpkt_info_struct *pktinfo = NULL;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++
++	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
++	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
++
++	if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid))
++		return;
++
++	if (pktinfo->data_rate <= ODM_RATE11M)
++		return;
++
++	if (p_div->phydm_path_div_type == PHYDM_4R_PATH_DIV) {
++		p_div->path_a_sum_all += phy_info->rx_mimo_signal_strength[0];
++		p_div->path_a_cnt_all++;
++
++		p_div->path_b_sum_all += phy_info->rx_mimo_signal_strength[1];
++		p_div->path_b_cnt_all++;
++
++		p_div->path_c_sum_all += phy_info->rx_mimo_signal_strength[2];
++		p_div->path_c_cnt_all++;
++
++		p_div->path_d_sum_all += phy_info->rx_mimo_signal_strength[3];
++		p_div->path_d_cnt_all++;
++	}
++}
++
++void phydm_pathdiv_debug_8814a(void *dm_void, char input[][16], u32 *_used,
++			       char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 dm_value[10] = {0};
++	u8 i, input_idx = 0;
++
++	for (i = 0; i < 5; i++) {
++		if (input[i + 1]) {
++			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
++			input_idx++;
++		}
++	}
++
++	if (input_idx == 0)
++		return;
++
++	dm->path_select = (u8)(dm_value[0] & 0xf);
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "Path_select = (( 0x%x ))\n", dm->path_select);
++
++	/* @2 [Fix path] */
++	if (dm->path_select != PHYDM_AUTO_PATH) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Turn on path  [%s%s%s%s]\n",
++			 ((dm->path_select) & 0x1) ? "A" : "",
++			 ((dm->path_select) & 0x2) ? "B" : "",
++			 ((dm->path_select) & 0x4) ? "C" : "",
++			 ((dm->path_select) & 0x8) ? "D" : "");
++
++		phydm_dtp_fix_tx_path(dm, dm->path_select);
++	} else {
++		PDM_SNPF(out_len, used, output + used, out_len - used, "%s\n",
++			 "Auto path");
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++#endif /* @#if RTL8814A_SUPPORT */
++
++#if RTL8812A_SUPPORT
++void phydm_update_tx_path_8812a(void *dm_void, enum bb_path path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++
++	if (p_div->default_tx_path != path) {
++		PHYDM_DBG(dm, DBG_PATH_DIV, "Need to Update Tx path\n");
++
++		if (path == BB_PATH_A) {
++			/*Tx by Reg*/
++			odm_set_bb_reg(dm, R_0x80c, 0xFFF0, 0x111);
++			/*Resp Tx by Txinfo*/
++			odm_set_bb_reg(dm, R_0x6d8, 0xc0, 1);
++		} else {
++			/*Tx by Reg*/
++			odm_set_bb_reg(dm, R_0x80c, 0xFFF0, 0x222);
++			 /*Resp Tx by Txinfo*/
++			odm_set_bb_reg(dm, R_0x6d8, 0xc0, 2);
++		}
++	}
++	p_div->default_tx_path = path;
++
++	PHYDM_DBG(dm, DBG_PATH_DIV, "path=%s\n",
++		  (path == BB_PATH_A) ? "A" : "B");
++}
++
++void phydm_path_diversity_init_8812a(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++	u32 i;
++
++	odm_set_bb_reg(dm, R_0x80c, BIT(29), 1); /* Tx path from Reg */
++	odm_set_bb_reg(dm, R_0x80c, 0xFFF0, 0x111); /* Tx by Reg */
++	odm_set_bb_reg(dm, R_0x6d8, BIT(7) | BIT6, 1); /* Resp Tx by Txinfo */
++	phydm_set_tx_path_by_bb_reg(dm, RF_PATH_A);
++
++	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
++		p_div->path_sel[i] = 1; /* TxInfo default at path-A */
++}
++#endif
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++void phydm_set_resp_tx_path_by_fw_jgr3(void *dm_void, u8 macid,
++				       enum bb_path path, boolean enable)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++	u8 h2c_para[7] = {0};
++	u8 path_map[4] = {0}; /* tx logic map*/
++	u8 num_enable_path = 0;
++	u8 n_tx_path_ctrl_map = 0;
++	u8 i = 0, n_sts = 0;
++
++	/*Response TX is controlled in FW ctrl info*/
++
++	PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] =====>\n", __func__);
++
++	if (enable) {
++		n_tx_path_ctrl_map = path;
++
++		for (i = 0; i < 4; i++) {
++			path_map[i] = 0;
++			if (path & BIT(i))
++				num_enable_path++;
++		}
++
++		for (i = 0; i < 4; i++) {
++			if (path & BIT(i)) {
++				path_map[i] = n_sts;
++				n_sts++;
++
++				if (n_sts == num_enable_path)
++					break;
++			}
++		}
++	}
++
++	PHYDM_DBG(dm, DBG_PATH_DIV, "ctrl_map=0x%x Map[D:A]={%d, %d, %d, %d}\n",
++		  n_tx_path_ctrl_map,
++		  path_map[3], path_map[2], path_map[1], path_map[0]);
++
++	h2c_para[0] = macid;
++	h2c_para[1] = n_tx_path_ctrl_map;
++	h2c_para[2] = (path_map[3] << 6) | (path_map[2] << 4) |
++		      (path_map[1] << 2) | path_map[0];
++
++	odm_fill_h2c_cmd(dm, PHYDM_H2C_DYNAMIC_TX_PATH, 7, h2c_para);
++}
++
++void phydm_get_tx_path_txdesc_jgr3(void *dm_void, u8 macid,
++				   struct path_txdesc_ctrl *desc)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++	u8 ant_map_a = 0, ant_map_b = 0;
++	u8 ntx_map = 0;
++
++	if (p_div->path_sel[macid] == BB_PATH_A) {
++		desc->ant_map_a = 0; /*offest24[23:22]*/
++		desc->ant_map_b = 0; /*offest24[25:24]*/
++		desc->ntx_map = BB_PATH_A; /*offest28[23:20]*/
++	} else if (p_div->path_sel[macid] == BB_PATH_B) {
++		desc->ant_map_a = 0; /*offest24[23:22]*/
++		desc->ant_map_b = 0; /*offest24[25:24]*/
++		desc->ntx_map = BB_PATH_B; /*offest28[23:20]*/
++	} else {
++		desc->ant_map_a = 0; /*offest24[23:22]*/
++		desc->ant_map_b = 1; /*offest24[25:24]*/
++		desc->ntx_map = BB_PATH_AB; /*offest28[23:20]*/
++	}
++}
++#endif
++
++void phydm_tx_path_by_mac_or_reg(void *dm_void, enum phydm_path_ctrl ctrl)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++
++	PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] ctrl=%s\n",
++		  __func__, (ctrl == TX_PATH_BY_REG) ? "REG" : "DESC");
++
++	if (ctrl == p_div->tx_path_ctrl)
++		return;
++
++	p_div->tx_path_ctrl = ctrl;
++
++	switch (dm->support_ic_type) {
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	case ODM_RTL8822B:
++	case ODM_RTL8822C:
++	case ODM_RTL8812F:
++	case ODM_RTL8197G:
++		if (ctrl == TX_PATH_BY_REG) {
++			odm_set_bb_reg(dm, R_0x1e24, BIT(16), 0); /*OFDM*/
++			odm_set_bb_reg(dm, R_0x1a84, 0xe0, 0); /*CCK*/
++		} else {
++			odm_set_bb_reg(dm, R_0x1e24, BIT(16), 1); /*OFDM*/
++			odm_set_bb_reg(dm, R_0x1a84, 0xe0, 7); /*CCK*/
++		}
++
++		break;
++	#endif
++	#if 0 /*(RTL8822B_SUPPORT)*/ /*@ HW Bug*/
++	case ODM_RTL8822B:
++		if (ctrl == TX_PATH_BY_REG) {
++			odm_set_bb_reg(dm, R_0x93c, BIT(18), 0);
++			odm_set_bb_reg(dm, R_0xa84, 0xe0, 0); /*CCK*/
++		} else {
++			odm_set_bb_reg(dm, R_0x93c, BIT(18), 1);
++			odm_set_bb_reg(dm, R_0xa84, 0xe0, 7); /*CCK*/
++		}
++
++		break;
++	#endif
++	default:
++		break;
++	}
++}
++
++void phydm_fix_1ss_tx_path_by_bb_reg(void *dm_void,
++				     enum bb_path tx_path_sel_1ss,
++				     enum bb_path tx_path_sel_cck)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++
++	if (tx_path_sel_1ss != BB_PATH_AUTO) {
++		p_div->ofdm_fix_path_en = true;
++		p_div->ofdm_fix_path_sel = tx_path_sel_1ss;
++	} else {
++		p_div->ofdm_fix_path_en = false;
++		p_div->ofdm_fix_path_sel = dm->tx_1ss_status;
++	}
++
++	if (tx_path_sel_cck != BB_PATH_AUTO) {
++		p_div->cck_fix_path_en = true;
++		p_div->cck_fix_path_sel = tx_path_sel_cck;
++	} else {
++		p_div->cck_fix_path_en = false;
++		p_div->cck_fix_path_sel = dm->tx_1ss_status;
++	}
++
++	p_div->force_update = true;
++
++	PHYDM_DBG(dm, DBG_PATH_DIV,
++		  "{OFDM_fix_en=%d, path=%d} {CCK_fix_en=%d, path=%d}\n",
++		  p_div->ofdm_fix_path_en, p_div->ofdm_fix_path_sel,
++		  p_div->cck_fix_path_en, p_div->cck_fix_path_sel);
++}
++
++void phydm_set_tx_path_by_bb_reg(void *dm_void, enum bb_path tx_path_sel_1ss)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++	enum bb_path tx_path_sel_cck = tx_path_sel_1ss;
++
++	if (!p_div->force_update) {
++		if (tx_path_sel_1ss == p_div->default_tx_path) {
++			PHYDM_DBG(dm, DBG_PATH_DIV, "Stay in TX path=%s\n",
++				  (tx_path_sel_1ss == BB_PATH_A) ? "A" : "B");
++			return;
++		}
++	}
++	p_div->force_update = false;
++
++	p_div->default_tx_path = tx_path_sel_1ss;
++
++	PHYDM_DBG(dm, DBG_PATH_DIV, "Switch TX path=%s\n",
++		  (tx_path_sel_1ss == BB_PATH_A) ? "A" : "B");
++
++	/*Adv-ctrl mode*/
++	if (p_div->cck_fix_path_en) {
++		PHYDM_DBG(dm, DBG_PATH_DIV, "Fix CCK TX path=%d\n",
++			  p_div->cck_fix_path_sel);
++		tx_path_sel_cck = p_div->cck_fix_path_sel;
++	}
++
++	if (p_div->ofdm_fix_path_en) {
++		PHYDM_DBG(dm, DBG_PATH_DIV, "Fix OFDM TX path=%d\n",
++			  p_div->ofdm_fix_path_sel);
++		tx_path_sel_1ss = p_div->ofdm_fix_path_sel;
++	}
++
++	switch (dm->support_ic_type) {
++	#if RTL8822C_SUPPORT
++	case ODM_RTL8822C:
++		phydm_config_tx_path_8822c(dm, dm->tx_2ss_status,
++					   tx_path_sel_1ss, tx_path_sel_cck);
++		break;
++	#endif
++
++	#if RTL8822B_SUPPORT
++	case ODM_RTL8822B:
++		if (dm->tx_ant_status != BB_PATH_AB)
++			return;
++
++		phydm_config_tx_path_8822b(dm, BB_PATH_AB,
++					   tx_path_sel_1ss, tx_path_sel_cck);
++		break;
++	#endif
++
++	#if RTL8192F_SUPPORT
++	case ODM_RTL8192F:
++		if (dm->tx_ant_status != BB_PATH_AB)
++			return;
++
++		phydm_config_tx_path_8192f(dm, BB_PATH_AB,
++					   tx_path_sel_1ss, tx_path_sel_cck);
++		break;
++	#endif
++
++	#if RTL8812A_SUPPORT
++	case ODM_RTL8812:
++		phydm_update_tx_path_8812a(dm, tx_path_sel_1ss);
++		break;
++	#endif
++	default:
++		break;
++	}
++}
++
++void phydm_tx_path_diversity_2ss(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++	struct cmn_sta_info *sta;
++	enum bb_path default_tx_path = BB_PATH_A, path = BB_PATH_A;
++	u32 rssi_a = 0, rssi_b = 0;
++	u32 local_max_rssi, glb_min_rssi = 0xff;
++	u8 i = 0;
++
++	PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] =======>\n", __func__);
++
++	if (!dm->is_linked) {
++		if (dm->first_disconnect)
++			phydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_REG);
++
++		PHYDM_DBG(dm, DBG_PATH_DIV, "No Link\n");
++		return;
++	}
++
++	#if 0/*def PHYDM_IC_JGR3_SERIES_SUPPORT*/
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		if (dm->is_one_entry_only || p_div->cck_fix_path_en ||
++		    p_div->ofdm_fix_path_en)
++			phydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_REG);
++		else
++			phydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_DESC);
++	}
++	#endif
++
++	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
++		sta = dm->phydm_sta_info[i];
++		if (!is_sta_active(sta))
++			continue;
++
++		/* 2 Caculate RSSI per path */
++		rssi_a = PHYDM_DIV(p_div->path_a_sum[i], p_div->path_a_cnt[i]);
++		rssi_b = PHYDM_DIV(p_div->path_b_sum[i], p_div->path_b_cnt[i]);
++
++		if (rssi_a == rssi_b)
++			path =  p_div->default_tx_path;
++		else
++			path = (rssi_a > rssi_b) ? BB_PATH_A : BB_PATH_B;
++
++		local_max_rssi = (rssi_a > rssi_b) ? rssi_a : rssi_b;
++
++		PHYDM_DBG(dm, DBG_PATH_DIV,
++			  "[%d]PathA sum=%d, cnt=%d, avg_rssi=%d\n",
++			  i, p_div->path_a_sum[i],
++			  p_div->path_a_cnt[i], rssi_a);
++		PHYDM_DBG(dm, DBG_PATH_DIV,
++			  "[%d]PathB sum=%d, cnt=%d, avg_rssi=%d\n",
++			  i, p_div->path_b_sum[i],
++			  p_div->path_b_cnt[i], rssi_b);
++
++		/*Select default Tx path */
++		if (local_max_rssi < glb_min_rssi) {
++			glb_min_rssi = local_max_rssi;
++			default_tx_path = path;
++		}
++
++		if (p_div->path_sel[i] != path) {
++			p_div->path_sel[i] = path;
++			#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++			if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++				phydm_set_resp_tx_path_by_fw_jgr3(dm, i,
++								  path, true);
++			#endif
++		}
++
++		p_div->path_a_cnt[i] = 0;
++		p_div->path_a_sum[i] = 0;
++		p_div->path_b_cnt[i] = 0;
++		p_div->path_b_sum[i] = 0;
++	}
++
++	/* 2 Update default Tx path */
++	phydm_set_tx_path_by_bb_reg(dm, default_tx_path);
++	PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] end\n\n", __func__);
++}
++
++void phydm_tx_path_diversity(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++
++	p_div->path_div_in_progress = false;
++
++	if (!(dm->support_ability & ODM_BB_PATH_DIV))
++		return;
++
++	if (p_div->stop_path_div) {
++		PHYDM_DBG(dm, DBG_PATH_DIV,
++			  "stop_path_div=1, tx_1ss_status=%d\n",
++			  dm->tx_1ss_status);
++		return;
++	}
++
++	switch (dm->support_ic_type) {
++	#ifdef PHYDM_CONFIG_PATH_DIV_V2
++	case ODM_RTL8822B:
++	case ODM_RTL8822C:
++	case ODM_RTL8192F:
++	case ODM_RTL8812F:
++	case ODM_RTL8197G:
++		if (dm->rx_ant_status != BB_PATH_AB) {
++			PHYDM_DBG(dm, DBG_PATH_DIV,
++				  "[Return] tx_Path_en=%d, rx_Path_en=%d\n",
++				  dm->tx_ant_status, dm->rx_ant_status);
++			return;
++		}
++
++		p_div->path_div_in_progress = true;
++		phydm_tx_path_diversity_2ss(dm);
++		break;
++	#endif
++
++	#if (RTL8812A_SUPPORT)
++	case ODM_RTL8812:
++		phydm_tx_path_diversity_2ss(dm);
++		break;
++	#endif
++
++	#if RTL8814A_SUPPORT
++	case ODM_RTL8814A:
++		phydm_dynamic_tx_path(dm);
++		break;
++	#endif
++	}
++}
++
++void phydm_tx_path_diversity_init_v2(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++	u32 i = 0;
++
++	PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] ====>\n", __func__);
++
++	/*BB_PATH_AB is a invalid value used for init state*/
++	p_div->default_tx_path = BB_PATH_A;
++	p_div->tx_path_ctrl = TX_PATH_CTRL_INIT;
++	p_div->path_div_in_progress = false;
++
++	p_div->cck_fix_path_en = false;
++	p_div->ofdm_fix_path_en = false;
++	p_div->force_update = false;
++
++	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
++		p_div->path_sel[i] = BB_PATH_A; /* TxInfo default at path-A */
++
++	phydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_REG);
++}
++
++void phydm_tx_path_diversity_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (!(dm->support_ability & ODM_BB_PATH_DIV))
++		return;
++
++	switch (dm->support_ic_type) {
++	#ifdef PHYDM_CONFIG_PATH_DIV_V2
++	case ODM_RTL8822C:
++	case ODM_RTL8822B:
++	case ODM_RTL8192F:
++	case ODM_RTL8812F:
++	case ODM_RTL8197G:
++	phydm_tx_path_diversity_init_v2(dm); /*@ After 8822B*/
++	break;
++	#endif
++
++	#if RTL8812A_SUPPORT
++	case ODM_RTL8812:
++	phydm_path_diversity_init_8812a(dm);
++	break;
++	#endif
++
++	#if RTL8814A_SUPPORT
++	case ODM_RTL8814A:
++	phydm_dynamic_tx_path_init(dm);
++	break;
++	#endif
++	}
++}
++
++void phydm_process_rssi_for_path_div(void *dm_void, void *phy_info_void,
++				     void *pkt_info_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_phyinfo_struct *phy_info = NULL;
++	struct phydm_perpkt_info_struct *pktinfo = NULL;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++	u8 id = 0;
++
++	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
++	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
++
++	if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid))
++		return;
++
++	if (pktinfo->is_cck_rate)
++		return;
++
++	id = pktinfo->station_id;
++	p_div->path_a_sum[id] += phy_info->rx_mimo_signal_strength[0];
++	p_div->path_a_cnt[id]++;
++
++	p_div->path_b_sum[id] += phy_info->rx_mimo_signal_strength[1];
++	p_div->path_b_cnt[id]++;
++}
++
++void phydm_pathdiv_debug(void *dm_void, char input[][16], u32 *_used,
++			 char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++	char help[] = "-h";
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 val[10] = {0};
++	u8 i, input_idx = 0;
++
++	for (i = 0; i < 5; i++) {
++		if (input[i + 1]) {
++			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
++			input_idx++;
++		}
++	}
++
++	if (input_idx == 0)
++		return;
++
++	PHYDM_SSCANF(input[1], DCMD_HEX, &val[0]);
++	PHYDM_SSCANF(input[2], DCMD_HEX, &val[1]);
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{1:TX Ctrl Sig} {0:BB, 1:MAC}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{2:BB Default TX REG} {path}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{3:MAC DESC TX} {path} {macid}\n");
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{4:MAC Resp TX} {path} {macid}\n");
++		#endif
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{5:Fix 1ss path} {ofdm path} {cck path}\n");
++	} else if (val[0] == 1) {
++		phydm_tx_path_by_mac_or_reg(dm, (enum phydm_path_ctrl)val[1]);
++	} else if (val[0] == 2) {
++		phydm_set_tx_path_by_bb_reg(dm, (enum bb_path)val[1]);
++	} else if (val[0] == 3) {
++		p_div->path_sel[val[2]] = (enum bb_path)val[1];
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	} else if (val[0] == 4) {
++		phydm_set_resp_tx_path_by_fw_jgr3(dm, (u8)val[2],
++						  (enum bb_path)val[1], true);
++	#endif
++	} else if (val[0] == 5) {
++		phydm_fix_1ss_tx_path_by_bb_reg(dm, (enum bb_path)val[1],
++						(enum bb_path)val[2]);
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_c2h_dtp_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
++
++	u8 macid = cmd_buf[0];
++	u8 target = cmd_buf[1];
++	u8 nsc_1 = cmd_buf[2];
++	u8 nsc_2 = cmd_buf[3];
++	u8 nsc_3 = cmd_buf[4];
++
++	PHYDM_DBG(dm, DBG_PATH_DIV, "Target_candidate = (( %d ))\n", target);
++/*@
++	if( (nsc_1 >= nsc_2) &&  (nsc_1 >= nsc_3))
++	{
++		phydm_dtp_fix_tx_path(dm, p_div->ant_candidate_1);
++	}
++	else	if( nsc_2 >= nsc_3)
++	{
++		phydm_dtp_fix_tx_path(dm, p_div->ant_candidate_2);
++	}
++	else
++	{
++		phydm_dtp_fix_tx_path(dm, p_div->ant_candidate_3);
++	}
++	*/
++}
++
++#endif /*  @#ifdef CONFIG_PATH_DIVERSITY */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pathdiv.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pathdiv.h
+new file mode 100644
+index 000000000..ee3438252
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pathdiv.h
+@@ -0,0 +1,145 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDMPATHDIV_H__
++#define __PHYDMPATHDIV_H__
++
++#ifdef CONFIG_PATH_DIVERSITY
++/* @2019.03.07 open resp tx path h2c only for 1ss status*/
++#define PATHDIV_VERSION "4.4"
++
++#if (RTL8192F_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\
++	RTL8812F_SUPPORT || RTL8197G_SUPPORT)
++	#define PHYDM_CONFIG_PATH_DIV_V2
++#endif
++
++#define USE_PATH_A_AS_DEFAULT_ANT /* @for 8814 dynamic TX path selection */
++
++#define NUM_RESET_DTP_PERIOD 5
++#define ANT_DECT_RSSI_TH 3
++
++#define PATH_A 1
++#define PATH_B 2
++#define PATH_C 3
++#define PATH_D 4
++
++#define PHYDM_AUTO_PATH 0
++#define PHYDM_FIX_PATH 1
++
++#define NUM_CHOOSE2_FROM4 6
++#define NUM_CHOOSE3_FROM4 4
++
++enum phydm_dtp_state {
++	PHYDM_DTP_INIT = 1,
++	PHYDM_DTP_RUNNING_1
++};
++
++enum phydm_path_div_type {
++	PHYDM_2R_PATH_DIV = 1,
++	PHYDM_4R_PATH_DIV = 2
++};
++
++enum phydm_path_ctrl {
++	TX_PATH_BY_REG = 0,
++	TX_PATH_BY_DESC = 1,
++	TX_PATH_CTRL_INIT
++};
++
++struct path_txdesc_ctrl {
++	u8 ant_map_a : 2;
++	u8 ant_map_b : 2;
++	u8 ntx_map : 4;
++};
++
++struct _ODM_PATH_DIVERSITY_ {
++	boolean stop_path_div; /*@Limit by enabled path number*/
++	boolean path_div_in_progress;
++	boolean	cck_fix_path_en; /*@ BB Reg for Adv-Ctrl (or debug mode)*/
++	boolean	ofdm_fix_path_en; /*@ BB Reg for Adv-Ctrl (or debug mode)*/
++	enum bb_path cck_fix_path_sel; /*@ BB Reg for Adv-Ctrl (or debug mode)*/
++	enum bb_path ofdm_fix_path_sel;/*@ BB Reg for Adv-Ctrl (or debug mode)*/
++	enum phydm_path_ctrl tx_path_ctrl;
++	enum bb_path default_tx_path;
++	enum bb_path path_sel[ODM_ASSOCIATE_ENTRY_NUM];
++	u32	path_a_sum[ODM_ASSOCIATE_ENTRY_NUM];
++	u32	path_b_sum[ODM_ASSOCIATE_ENTRY_NUM];
++	u16	path_a_cnt[ODM_ASSOCIATE_ENTRY_NUM];
++	u16	path_b_cnt[ODM_ASSOCIATE_ENTRY_NUM];
++	u8	phydm_path_div_type;
++	boolean force_update;
++#if RTL8814A_SUPPORT
++
++	u32	path_a_sum_all;
++	u32	path_b_sum_all;
++	u32	path_c_sum_all;
++	u32	path_d_sum_all;
++
++	u32	path_a_cnt_all;
++	u32	path_b_cnt_all;
++	u32	path_c_cnt_all;
++	u32	path_d_cnt_all;
++
++	u8	dtp_period;
++	boolean	is_become_linked;
++	boolean	is_u3_mode;
++	u8	num_tx_path;
++	u8	default_path;
++	u8	num_candidate;
++	u8	ant_candidate_1;
++	u8	ant_candidate_2;
++	u8	ant_candidate_3;
++	u8     phydm_dtp_state;
++	u8	dtp_check_patha_counter;
++	boolean	fix_path_bfer;
++	u8	search_space_2[NUM_CHOOSE2_FROM4];
++	u8	search_space_3[NUM_CHOOSE3_FROM4];
++
++	u8	pre_tx_path;
++	u8	use_path_a_as_default_ant;
++	boolean	is_path_a_exist;
++
++#endif
++};
++
++void phydm_set_tx_path_by_bb_reg(void *dm_void, enum bb_path tx_path_sel_1ss);
++
++void phydm_get_tx_path_txdesc_jgr3(void *dm_void, u8 macid,
++				   struct path_txdesc_ctrl *desc);
++
++void phydm_c2h_dtp_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
++
++void phydm_tx_path_diversity_init(void *dm_void);
++
++void phydm_tx_path_diversity(void *dm_void);
++
++void phydm_process_rssi_for_path_div(void *dm_void, void *phy_info_void,
++				     void *pkt_info_void);
++
++void phydm_pathdiv_debug(void *dm_void, char input[][16], u32 *_used,
++			 char *output, u32 *_out_len);
++
++#endif /* @#ifdef CONFIG_PATH_DIVERSITY */
++#endif /* @#ifndef  __PHYDMPATHDIV_H__ */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_phystatus.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_phystatus.c
+new file mode 100644
+index 000000000..0769a9ffa
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_phystatus.c
+@@ -0,0 +1,3134 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ ************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#ifdef PHYDM_COMPILE_MU
++u8 phydm_get_gid(struct dm_struct *dm, u8 *phy_status_inf)
++{
++#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
++	struct phy_sts_rpt_jgr2_type1 *rpt_jgr2 = NULL;
++#endif
++#ifdef PHYSTS_3RD_TYPE_SUPPORT
++	struct phy_sts_rpt_jgr3_type1 *rpt_jgr3 = NULL;
++#endif
++	u8 gid = 0;
++
++	if (dm->ic_phy_sts_type == PHYDM_PHYSTS_TYPE_1)
++		return 0;
++
++	if ((*phy_status_inf & 0xf) != 1)
++		return 0;
++
++	switch (dm->ic_phy_sts_type) {
++	#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
++	case PHYDM_PHYSTS_TYPE_2:
++		rpt_jgr2 = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf;
++		gid = rpt_jgr2->gid;
++		break;
++	#endif
++	#ifdef PHYSTS_3RD_TYPE_SUPPORT
++	case PHYDM_PHYSTS_TYPE_3:
++		rpt_jgr3 = (struct phy_sts_rpt_jgr3_type1 *)phy_status_inf;
++		gid = rpt_jgr3->gid;
++		break;
++	#endif
++	default:
++		break;
++	}
++
++	return gid;
++}
++#endif
++
++void phydm_rx_statistic_cal(struct dm_struct *dm,
++			    struct phydm_phyinfo_struct *phy_info,
++			    u8 *phy_status_inf,
++			    struct phydm_perpkt_info_struct *pktinfo)
++{
++	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	struct phydm_bf_rate_info_jgr3 *bfrateinfo = &dm->bf_rate_info_jgr3;
++#endif
++
++	u8 rate = (pktinfo->data_rate & 0x7f);
++	u8 bw_idx = phy_info->band_width;
++	u8 offset = 0;
++	u8 gid = 0;
++#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT))
++	u8 val = 0;
++#endif
++	#ifdef PHYDM_COMPILE_MU
++	u8 is_mu_pkt = 0;
++	#endif
++
++	if (rate <= ODM_RATE54M) {
++		dbg_i->num_qry_legacy_pkt[rate]++;
++	} else if (rate <= ODM_RATEMCS31) {
++		dbg_i->ht_pkt_not_zero = true;
++		offset = rate - ODM_RATEMCS0;
++
++		if (offset > (HT_RATE_NUM - 1))
++			offset = HT_RATE_NUM - 1;
++
++		if (dm->support_ic_type &
++		    (PHYSTS_2ND_TYPE_IC | PHYSTS_3RD_TYPE_IC)) {
++			if (bw_idx == *dm->band_width) {
++				dbg_i->num_qry_ht_pkt[offset]++;
++
++			} else if (bw_idx == CHANNEL_WIDTH_20) {
++				dbg_i->num_qry_pkt_sc_20m[offset]++;
++				dbg_i->low_bw_20_occur = true;
++			}
++		} else {
++			dbg_i->num_qry_ht_pkt[offset]++;
++		}
++	}
++#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT))
++	else if (rate <= ODM_RATEVHTSS4MCS9) {
++		offset = rate - ODM_RATEVHTSS1MCS0;
++
++		if (offset > (VHT_RATE_NUM - 1))
++			offset = VHT_RATE_NUM - 1;
++
++		#ifdef PHYDM_COMPILE_MU
++		gid = phydm_get_gid(dm, phy_status_inf);
++
++		if (gid != 0 && gid != 63)
++			is_mu_pkt = true;
++
++		if (is_mu_pkt) {
++		#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT ||\
++		     (defined(PHYSTS_3RD_TYPE_SUPPORT)))
++			dbg_i->num_mu_vht_pkt[offset]++;
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++			bfrateinfo->num_mu_vht_pkt[offset]++;
++		#endif
++		#else
++			dbg_i->num_qry_vht_pkt[offset]++; /*@for debug*/
++		#endif
++		} else
++		#endif
++		{
++			dbg_i->vht_pkt_not_zero = true;
++
++			if (dm->support_ic_type &
++			    (PHYSTS_2ND_TYPE_IC | PHYSTS_3RD_TYPE_IC)) {
++				if (bw_idx == *dm->band_width) {
++					dbg_i->num_qry_vht_pkt[offset]++;
++				#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++					bfrateinfo->num_qry_vht_pkt[offset]++;
++				#endif
++
++				} else if (bw_idx == CHANNEL_WIDTH_20) {
++					dbg_i->num_qry_pkt_sc_20m[offset]++;
++					dbg_i->low_bw_20_occur = true;
++				} else {/*@if (bw_idx == CHANNEL_WIDTH_40)*/
++					dbg_i->num_qry_pkt_sc_40m[offset]++;
++					dbg_i->low_bw_40_occur = true;
++				}
++			} else {
++				dbg_i->num_qry_vht_pkt[offset]++;
++			}
++		}
++
++		#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT ||\
++		     (defined(PHYSTS_3RD_TYPE_SUPPORT)))
++		if (pktinfo->ppdu_cnt < 4) {
++			val = rate;
++
++			#ifdef PHYDM_COMPILE_MU
++			if (is_mu_pkt)
++				val |= BIT(7);
++			#endif
++
++			dbg_i->num_of_ppdu[pktinfo->ppdu_cnt] = val;
++			dbg_i->gid_num[pktinfo->ppdu_cnt] = gid;
++		}
++		#endif
++	}
++#endif
++}
++
++void phydm_reset_phystatus_avg(struct dm_struct *dm)
++{
++	struct phydm_phystatus_avg *dbg_avg = NULL;
++
++	dbg_avg = &dm->phy_dbg_info.phystatus_statistic_avg;
++	odm_memory_set(dm, &dbg_avg->rssi_cck_avg, 0,
++		       sizeof(struct phydm_phystatus_avg));
++}
++
++void phydm_reset_phystatus_statistic(struct dm_struct *dm)
++{
++	struct phydm_phystatus_statistic *dbg_s = NULL;
++
++	dbg_s = &dm->phy_dbg_info.physts_statistic_info;
++
++	odm_memory_set(dm, &dbg_s->rssi_cck_sum, 0,
++		       sizeof(struct phydm_phystatus_statistic));
++}
++
++void phydm_reset_phy_info(struct dm_struct *dm,
++			  struct phydm_phyinfo_struct *phy_info)
++{
++	u8 i = 0;
++
++	odm_memory_set(dm, &phy_info->physts_rpt_valid, 0,
++		       sizeof(struct phydm_phyinfo_struct));
++
++	phy_info->rx_power = -110;
++	phy_info->recv_signal_power = -110;
++
++	for (i = 0; i < dm->num_rf_path; i++)
++		phy_info->rx_pwr[i] = -110;
++}
++
++void phydm_avg_rssi_evm_snr(void *dm_void,
++			    struct phydm_phyinfo_struct *phy_info,
++			    struct phydm_perpkt_info_struct *pktinfo)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
++	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
++	u8 *rssi = phy_info->rx_mimo_signal_strength;
++	u8 *evm = phy_info->rx_mimo_evm_dbm;
++	s8 *snr = phy_info->rx_snr;
++	u32 size = PHYSTS_PATH_NUM; /*size of path=4*/
++	u16 size_th = PHY_HIST_SIZE - 1; /*size of threshold*/
++	u16 val = 0, intvl = 0;
++	u8 i = 0;
++
++	if (pktinfo->is_packet_beacon) {
++		for (i = 0; i < dm->num_rf_path; i++)
++			dbg_s->rssi_beacon_sum[i] += rssi[i];
++
++		dbg_s->rssi_beacon_cnt++;
++	}
++
++	if (pktinfo->data_rate <= ODM_RATE11M) {
++		/*RSSI*/
++		dbg_s->rssi_cck_sum += rssi[0];
++		#ifdef PHYSTS_3RD_TYPE_SUPPORT
++		if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) {
++			for (i = 1; i < dm->num_rf_path; i++)
++				dbg_s->rssi_cck_sum_abv_2ss[i - 1] += rssi[i];
++		}
++		#endif
++		dbg_s->rssi_cck_cnt++;
++	} else if (pktinfo->data_rate <= ODM_RATE54M) {
++		for (i = 0; i < dm->num_rf_path; i++) {
++			/*SNR & RSSI*/
++			dbg_s->snr_ofdm_sum[i] += snr[i];
++			dbg_s->rssi_ofdm_sum[i] += rssi[i];
++		}
++		/*@evm*/
++		dbg_s->evm_ofdm_sum += evm[0];
++		dbg_s->rssi_ofdm_cnt++;
++
++		val = (u16)evm[0];
++		intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, size_th);
++		dbg_s->evm_ofdm_hist[intvl]++;
++
++		val = (u16)snr[0];
++		intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, size_th);
++		dbg_s->snr_ofdm_hist[intvl]++;
++
++	} else if (pktinfo->rate_ss == 1) {
++/*@===[1-SS]==================================================================*/
++		for (i = 0; i < dm->num_rf_path; i++) {
++			/*SNR & RSSI*/
++			dbg_s->snr_1ss_sum[i] += snr[i];
++			dbg_s->rssi_1ss_sum[i] += rssi[i];
++		}
++
++		/*@evm*/
++		dbg_s->evm_1ss_sum += evm[0];
++		/*@EVM Histogram*/
++		val = (u16)evm[0];
++		intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, size_th);
++		dbg_s->evm_1ss_hist[intvl]++;
++
++		/*SNR Histogram*/
++		val = (u16)snr[0];
++		intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, size_th);
++		dbg_s->snr_1ss_hist[intvl]++;
++
++		dbg_s->rssi_1ss_cnt++;
++	} else if (pktinfo->rate_ss == 2) {
++/*@===[2-SS]==================================================================*/
++		#if (defined(PHYDM_COMPILE_ABOVE_2SS))
++		for (i = 0; i < dm->num_rf_path; i++) {
++			/*SNR & RSSI*/
++			dbg_s->snr_2ss_sum[i] += snr[i];
++			dbg_s->rssi_2ss_sum[i] += rssi[i];
++		}
++
++		for (i = 0; i < pktinfo->rate_ss; i++) {
++			/*@evm*/
++			dbg_s->evm_2ss_sum[i] += evm[i];
++			/*@EVM Histogram*/
++			val = (u16)evm[i];
++			intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,
++						  size_th);
++			dbg_s->evm_2ss_hist[i][intvl]++;
++
++			/*SNR Histogram*/
++			val = (u16)snr[i];
++			intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,
++						  size_th);
++			dbg_s->snr_2ss_hist[i][intvl]++;
++		}
++		dbg_s->rssi_2ss_cnt++;
++		#endif
++	} else if (pktinfo->rate_ss == 3) {
++/*@===[3-SS]==================================================================*/
++		#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++		for (i = 0; i < dm->num_rf_path; i++) {
++			/*SNR & RSSI*/
++			dbg_s->snr_3ss_sum[i] += snr[i];
++			dbg_s->rssi_3ss_sum[i] += rssi[i];
++		}
++
++		for (i = 0; i < pktinfo->rate_ss; i++) {
++			/*@evm*/
++			dbg_s->evm_3ss_sum[i] += evm[i];
++			/*@EVM Histogram*/
++			val = (u16)evm[i];
++			intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,
++						  size_th);
++			dbg_s->evm_3ss_hist[i][intvl]++;
++
++			/*SNR Histogram*/
++			val = (u16)snr[i];
++			intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,
++						  size_th);
++			dbg_s->snr_3ss_hist[i][intvl]++;
++		}
++		dbg_s->rssi_3ss_cnt++;
++		#endif
++	} else if (pktinfo->rate_ss == 4) {
++/*@===[4-SS]==================================================================*/
++		#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++		for (i = 0; i < dm->num_rf_path; i++) {
++			/*SNR & RSSI*/
++			dbg_s->snr_4ss_sum[i] += snr[i];
++			dbg_s->rssi_4ss_sum[i] += rssi[i];
++		}
++
++		for (i = 0; i < pktinfo->rate_ss; i++) {
++			/*@evm*/
++			dbg_s->evm_4ss_sum[i] += evm[i];
++
++			/*@EVM Histogram*/
++			val = (u16)evm[i];
++			intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,
++						  size_th);
++			dbg_s->evm_4ss_hist[i][intvl]++;
++
++			/*SNR Histogram*/
++			val = (u16)snr[i];
++			intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,
++						  size_th);
++			dbg_s->snr_4ss_hist[i][intvl]++;
++		}
++		dbg_s->rssi_4ss_cnt++;
++		#endif
++	}
++}
++
++void phydm_avg_phystatus_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
++	u16 snr_hist_th[PHY_HIST_TH_SIZE] = {5, 8, 11, 14, 17, 20, 23, 26,
++					      29, 32, 35};
++	u16 evm_hist_th[PHY_HIST_TH_SIZE] = {5, 8, 11, 14, 17, 20, 23, 26,
++					      29, 32, 35};
++	#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
++	u16 cn_hist_th[PHY_HIST_TH_SIZE] = {2, 3, 4, 5, 6, 8, 10,
++					    12, 14, 16, 18};
++	#endif
++	u32 size = PHY_HIST_TH_SIZE * 2;
++	u8 i = 0;
++
++	odm_move_memory(dm, dbg_i->snr_hist_th, snr_hist_th, size);
++	odm_move_memory(dm, dbg_i->evm_hist_th, evm_hist_th, size);
++	#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
++	dm->pkt_proc_struct.physts_auto_swch_en = false;
++	for (i = 0; i < PHY_HIST_TH_SIZE; i++)
++		dbg_i->cn_hist_th[i] = cn_hist_th[i] << 1;
++	#endif
++}
++
++u8 phydm_get_signal_quality(struct phydm_phyinfo_struct *phy_info,
++			    struct dm_struct *dm,
++			    struct phy_status_rpt_8192cd *phy_sts)
++{
++	u8 sq_rpt;
++	u8 result = 0;
++
++	if (phy_info->rx_pwdb_all > 40 && !dm->is_in_hct_test) {
++		result = 100;
++	} else {
++		sq_rpt = phy_sts->cck_sig_qual_ofdm_pwdb_all;
++
++		if (sq_rpt > 64)
++			result = 0;
++		else if (sq_rpt < 20)
++			result = 100;
++		else
++			result = ((64 - sq_rpt) * 100) / 44;
++	}
++
++	return result;
++}
++
++u8 phydm_pw_2_percent(s8 ant_power)
++{
++	if ((ant_power <= -100) || ant_power >= 20)
++		return 0;
++	else if (ant_power >= 0)
++		return 100;
++	else
++		return 100 + ant_power;
++}
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++void phydm_process_signal_strength(struct dm_struct *dm,
++				   struct phydm_phyinfo_struct *phy_info,
++				   struct phydm_perpkt_info_struct *pktinfo)
++{
++	boolean is_cck_rate = 0;
++	u8 avg_rssi = 0, tmp_rssi = 0, best_rssi = 0, second_rssi = 0;
++	u8 ss = 0; /*signal strenth after scale mapping*/
++	u8 pwdb = phy_info->rx_pwdb_all;
++	u8 i;
++
++	is_cck_rate = (pktinfo->data_rate <= ODM_RATE11M) ? true : false;
++
++	/*use the best two RSSI only*/
++	for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
++		tmp_rssi = phy_info->rx_mimo_signal_strength[i];
++
++		/*@Get the best two RSSI*/
++		if (tmp_rssi > best_rssi && tmp_rssi > second_rssi) {
++			second_rssi = best_rssi;
++			best_rssi = tmp_rssi;
++		} else if (tmp_rssi > second_rssi && tmp_rssi <= best_rssi) {
++			second_rssi = tmp_rssi;
++		}
++	}
++
++	if (best_rssi == 0)
++		return;
++
++	if (pktinfo->rate_ss == 1)
++		avg_rssi = best_rssi;
++	else
++		avg_rssi = (best_rssi + second_rssi) >> 1;
++
++	/* Update signal strength to UI,
++	 * and phy_info->rx_pwdb_all is the maximum RSSI of all path
++	 */
++	if (dm->support_ic_type & (PHYSTS_3RD_TYPE_IC | PHYSTS_2ND_TYPE_IC))
++		ss = SignalScaleProc(dm->adapter, pwdb, false, false);
++	else
++		ss = SignalScaleProc(dm->adapter, pwdb, true, is_cck_rate);
++
++	phy_info->signal_strength = ss;
++}
++
++static u8 phydm_sq_patch_lenovo(
++	struct dm_struct *dm,
++	u8 is_cck_rate,
++	u8 pwdb_all,
++	u8 path,
++	u8 RSSI)
++{
++	u8 sq = 0;
++
++	if (is_cck_rate) {
++		if (dm->support_ic_type & ODM_RTL8192E) {
++/*@
++ * <Roger_Notes>
++ * Expected signal strength and bars indication at Lenovo lab. 2013.04.11
++ * 802.11n, 802.11b, 802.11g only at channel 6
++ *
++ *	Attenuation (dB)	OS Signal Bars	RSSI by Xirrus (dBm)
++ *		50				5			-49
++ *		55				5			-49
++ *		60				5			-50
++ *		65				5			-51
++ *		70				5			-52
++ *		75				5			-54
++ *		80				5			-55
++ *		85				4			-60
++ *		90				3			-63
++ *		95				3			-65
++ *		100				2			-67
++ *		102				2			-67
++ *		104				1			-70
++ */
++			if (pwdb_all >= 50)
++				sq = 100;
++			else if (pwdb_all >= 35 && pwdb_all < 50)
++				sq = 80;
++			else if (pwdb_all >= 31 && pwdb_all < 35)
++				sq = 60;
++			else if (pwdb_all >= 22 && pwdb_all < 31)
++				sq = 40;
++			else if (pwdb_all >= 18 && pwdb_all < 22)
++				sq = 20;
++			else
++				sq = 10;
++		} else {
++			if (pwdb_all >= 50)
++				sq = 100;
++			else if (pwdb_all >= 35 && pwdb_all < 50)
++				sq = 80;
++			else if (pwdb_all >= 22 && pwdb_all < 35)
++				sq = 60;
++			else if (pwdb_all >= 18 && pwdb_all < 22)
++				sq = 40;
++			else
++				sq = 10;
++		}
++
++	} else {
++		/* OFDM rate */
++
++		if (dm->support_ic_type & ODM_RTL8192E) {
++			if (RSSI >= 45)
++				sq = 100;
++			else if (RSSI >= 22 && RSSI < 45)
++				sq = 80;
++			else if (RSSI >= 18 && RSSI < 22)
++				sq = 40;
++			else
++				sq = 20;
++		} else {
++			if (RSSI >= 45)
++				sq = 100;
++			else if (RSSI >= 22 && RSSI < 45)
++				sq = 80;
++			else if (RSSI >= 18 && RSSI < 22)
++				sq = 40;
++			else
++				sq = 20;
++		}
++	}
++	return sq;
++}
++
++static u8 phydm_sq_patch_rt_cid_819x_acer(
++	struct dm_struct *dm,
++	u8 is_cck_rate,
++	u8 pwdb_all,
++	u8 path,
++	u8 RSSI)
++{
++	u8 sq = 0;
++
++	if (is_cck_rate) {
++#if OS_WIN_FROM_WIN8(OS_VERSION)
++		if (pwdb_all >= 50)
++			sq = 100;
++		else if (pwdb_all >= 35 && pwdb_all < 50)
++			sq = 80;
++		else if (pwdb_all >= 30 && pwdb_all < 35)
++			sq = 60;
++		else if (pwdb_all >= 25 && pwdb_all < 30)
++			sq = 40;
++		else if (pwdb_all >= 20 && pwdb_all < 25)
++			sq = 20;
++		else
++			sq = 10;
++#else
++		if (pwdb_all >= 50)
++			sq = 100;
++		else if (pwdb_all >= 35 && pwdb_all < 50)
++			sq = 80;
++		else if (pwdb_all >= 30 && pwdb_all < 35)
++			sq = 60;
++		else if (pwdb_all >= 25 && pwdb_all < 30)
++			sq = 40;
++		else if (pwdb_all >= 20 && pwdb_all < 25)
++			sq = 20;
++		else
++			sq = 10;
++
++		/* @Abnormal case, do not indicate the value above 20 on Win7 */
++		if (pwdb_all == 0)
++			sq = 20;
++#endif
++
++	} else {
++		/* OFDM rate */
++		if (dm->support_ic_type & ODM_RTL8192E) {
++			if (RSSI >= 45)
++				sq = 100;
++			else if (RSSI >= 22 && RSSI < 45)
++				sq = 80;
++			else if (RSSI >= 18 && RSSI < 22)
++				sq = 40;
++			else
++				sq = 20;
++		} else {
++			if (RSSI >= 35)
++				sq = 100;
++			else if (RSSI >= 30 && RSSI < 35)
++				sq = 80;
++			else if (RSSI >= 25 && RSSI < 30)
++				sq = 40;
++			else
++				sq = 20;
++		}
++	}
++	return sq;
++}
++#endif
++
++static u8
++phydm_evm_2_percent(s8 value)
++{
++	/* @-33dB~0dB to 0%~99% */
++	s8 ret_val;
++
++	ret_val = value;
++	ret_val /= 2;
++
++/*@dbg_print("value=%d\n", value);*/
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++	if (ret_val >= 0)
++		ret_val = 0;
++
++	if (ret_val <= -40)
++		ret_val = -40;
++
++	ret_val = 0 - ret_val;
++	ret_val *= 3;
++#else
++	if (ret_val >= 0)
++		ret_val = 0;
++
++	if (ret_val <= -33)
++		ret_val = -33;
++
++	ret_val = 0 - ret_val;
++	ret_val *= 3;
++
++	if (ret_val == 99)
++		ret_val = 100;
++#endif
++
++	return (u8)ret_val;
++}
++
++s8 phydm_cck_rssi_convert(struct dm_struct *dm, u16 lna_idx, u8 vga_idx)
++{
++	/*@phydm_get_cck_rssi_table_from_reg*/
++	return (dm->cck_lna_gain_table[lna_idx] - (vga_idx << 1));
++}
++
++void phydm_get_cck_rssi_table_from_reg(struct dm_struct *dm)
++{
++	u8 used_lna_idx_tmp;
++	u32 reg_0xa80 = 0x7431, reg_0xabc = 0xcbe5edfd;
++	u32 val = 0;
++	u8 i;
++
++	/*@example: {-53, -43, -33, -27, -19, -13, -3, 1}*/
++	/*@{0xCB, 0xD5, 0xDF, 0xE5, 0xED, 0xF3, 0xFD, 0x2}*/
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "CCK LNA Gain table init\n");
++
++	if (!(dm->support_ic_type & ODM_RTL8197F))
++		return;
++
++	reg_0xa80 = odm_get_bb_reg(dm, R_0xa80, 0xFFFF);
++	reg_0xabc = odm_get_bb_reg(dm, R_0xabc, MASKDWORD);
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "reg_0xa80 = 0x%x\n", reg_0xa80);
++	PHYDM_DBG(dm, ODM_COMP_INIT, "reg_0xabc = 0x%x\n", reg_0xabc);
++
++	for (i = 0; i <= 3; i++) {
++		used_lna_idx_tmp = (u8)((reg_0xa80 >> (4 * i)) & 0x7);
++		val = (reg_0xabc >> (8 * i)) & 0xff;
++		dm->cck_lna_gain_table[used_lna_idx_tmp] = (s8)val;
++	}
++
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "cck_lna_gain_table = {%d,%d,%d,%d,%d,%d,%d,%d}\n",
++		  dm->cck_lna_gain_table[0], dm->cck_lna_gain_table[1],
++		  dm->cck_lna_gain_table[2], dm->cck_lna_gain_table[3],
++		  dm->cck_lna_gain_table[4], dm->cck_lna_gain_table[5],
++		  dm->cck_lna_gain_table[6], dm->cck_lna_gain_table[7]);
++}
++
++s8 phydm_get_cck_rssi(void *dm_void, u8 lna_idx, u8 vga_idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	s8 rx_pow = 0;
++
++	switch (dm->support_ic_type) {
++	#if (RTL8197F_SUPPORT)
++	case ODM_RTL8197F:
++		rx_pow = phydm_cck_rssi_convert(dm, lna_idx, vga_idx);
++		break;
++	#endif
++
++	#if (RTL8723D_SUPPORT)
++	case ODM_RTL8723D:
++		rx_pow = phydm_cckrssi_8723d(dm, lna_idx, vga_idx);
++		break;
++	#endif
++
++	#if (RTL8710B_SUPPORT)
++	case ODM_RTL8710B:
++		rx_pow = phydm_cckrssi_8710b(dm, lna_idx, vga_idx);
++		break;
++	#endif
++
++	#if (RTL8721D_SUPPORT)
++	case ODM_RTL8721D:
++		rx_pow = phydm_cckrssi_8721d(dm, lna_idx, vga_idx);
++		break;
++	#endif
++
++	#if (RTL8710C_SUPPORT)
++	case ODM_RTL8710C:
++		rx_pow = phydm_cckrssi_8710c(dm, lna_idx, vga_idx);
++		break;
++	#endif
++
++	#if (RTL8192F_SUPPORT)
++	case ODM_RTL8192F:
++		rx_pow = phydm_cckrssi_8192f(dm, lna_idx, vga_idx);
++		break;
++	#endif
++
++	#if (RTL8821C_SUPPORT)
++	case ODM_RTL8821C:
++		rx_pow = phydm_cck_rssi_8821c(dm, lna_idx, vga_idx);
++		break;
++	#endif
++
++	#if (RTL8195B_SUPPORT)
++	case ODM_RTL8195B:
++		rx_pow = phydm_cck_rssi_8195B(dm, lna_idx, vga_idx);
++		break;
++	#endif
++
++	#if (RTL8188E_SUPPORT)
++	case ODM_RTL8188E:
++		rx_pow = phydm_cck_rssi_8188e(dm, lna_idx, vga_idx);
++		break;
++	#endif
++
++	#if (RTL8192E_SUPPORT)
++	case ODM_RTL8192E:
++		rx_pow = phydm_cck_rssi_8192e(dm, lna_idx, vga_idx);
++		break;
++	#endif
++
++	#if (RTL8723B_SUPPORT)
++	case ODM_RTL8723B:
++		rx_pow = phydm_cck_rssi_8723b(dm, lna_idx, vga_idx);
++		break;
++	#endif
++
++	#if (RTL8703B_SUPPORT)
++	case ODM_RTL8703B:
++		rx_pow = phydm_cck_rssi_8703b(dm, lna_idx, vga_idx);
++		break;
++	#endif
++
++	#if (RTL8188F_SUPPORT)
++	case ODM_RTL8188F:
++		rx_pow = phydm_cck_rssi_8188f(dm, lna_idx, vga_idx);
++		break;
++	#endif
++
++	#if (RTL8195A_SUPPORT)
++	case ODM_RTL8195A:
++		rx_pow = phydm_cck_rssi_8195a(dm, lna_idx, vga_idx);
++		break;
++	#endif
++
++	#if (RTL8812A_SUPPORT)
++	case ODM_RTL8812:
++		rx_pow = phydm_cck_rssi_8812a(dm, lna_idx, vga_idx);
++		break;
++	#endif
++
++	#if (RTL8821A_SUPPORT || RTL8881A_SUPPORT)
++	case ODM_RTL8821:
++	case ODM_RTL8881A:
++		rx_pow = phydm_cck_rssi_8821a(dm, lna_idx, vga_idx);
++		break;
++	#endif
++
++	#if (RTL8814A_SUPPORT)
++	case ODM_RTL8814A:
++		rx_pow = phydm_cck_rssi_8814a(dm, lna_idx, vga_idx);
++		break;
++	#endif
++
++	default:
++		break;
++	}
++
++	return rx_pow;
++}
++
++#if (ODM_IC_11N_SERIES_SUPPORT)
++void phydm_phy_sts_n_parsing(struct dm_struct *dm,
++			     struct phydm_phyinfo_struct *phy_info,
++			     u8 *phy_status_inf,
++			     struct phydm_perpkt_info_struct *pktinfo)
++{
++	u8 i = 0;
++	s8 rx_pwr[4], rx_pwr_all = 0;
++	u8 EVM, pwdb_all = 0, pwdb_all_bt = 0;
++	u8 RSSI, total_rssi = 0;
++	u8 rf_rx_num = 0;
++	u8 lna_idx = 0;
++	u8 vga_idx = 0;
++	u8 cck_agc_rpt;
++	s8 evm_tmp = 0;
++	u8 sq = 0;
++	u8 val_tmp = 0;
++	s8 val_s8 = 0;
++	struct phy_status_rpt_8192cd *phy_sts = NULL;
++
++	phy_sts = (struct phy_status_rpt_8192cd *)phy_status_inf;
++
++	if (pktinfo->is_cck_rate) {
++		cck_agc_rpt = phy_sts->cck_agc_rpt_ofdm_cfosho_a;
++
++		/*@3 bit LNA*/
++		lna_idx = ((cck_agc_rpt & 0xE0) >> 5);
++		vga_idx = (cck_agc_rpt & 0x1F);
++
++		#if (RTL8703B_SUPPORT)
++		if (dm->support_ic_type & (ODM_RTL8703B) &&
++		    dm->cck_agc_report_type == 1) {
++			/*@4 bit LNA*/
++			if (phy_sts->cck_rpt_b_ofdm_cfosho_b & BIT(7))
++				val_tmp = 1;
++			else
++				val_tmp = 0;
++			lna_idx = (val_tmp << 3) | lna_idx;
++		}
++		#endif
++
++		rx_pwr_all = phydm_get_cck_rssi(dm, lna_idx, vga_idx);
++
++		PHYDM_DBG(dm, DBG_RSSI_MNTR,
++			  "ext_lna_gain (( %d )), lna_idx: (( 0x%x )), vga_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n",
++			  dm->ext_lna_gain, lna_idx, vga_idx, rx_pwr_all);
++
++		if (dm->board_type & ODM_BOARD_EXT_LNA)
++			rx_pwr_all -= dm->ext_lna_gain;
++
++		pwdb_all = phydm_pw_2_percent(rx_pwr_all);
++
++		if (pktinfo->is_to_self) {
++			dm->cck_lna_idx = lna_idx;
++			dm->cck_vga_idx = vga_idx;
++		}
++
++		phy_info->rx_pwdb_all = pwdb_all;
++		phy_info->bt_rx_rssi_percentage = pwdb_all;
++		phy_info->recv_signal_power = rx_pwr_all;
++
++		/* @(3) Get Signal Quality (EVM) */
++		#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++		if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO)
++			sq = phydm_sq_patch_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0);
++		else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER)
++			sq = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0);
++		else
++		#endif
++			sq = phydm_get_signal_quality(phy_info, dm, phy_sts);
++
++		/* @dbg_print("cck sq = %d\n", sq); */
++
++		phy_info->signal_quality = sq;
++		phy_info->rx_mimo_signal_quality[RF_PATH_A] = sq;
++		phy_info->rx_mimo_signal_quality[RF_PATH_B] = -1;
++
++		for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
++			if (i == 0)
++				phy_info->rx_mimo_signal_strength[0] = pwdb_all;
++			else
++				phy_info->rx_mimo_signal_strength[i] = 0;
++		}
++	} else { /* @2 is OFDM rate */
++
++		/* @(1)Get RSSI for HT rate */
++
++		for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
++			if (dm->rf_path_rx_enable & BIT(i))
++				rf_rx_num++;
++
++			val_s8 = phy_sts->path_agc[i].gain & 0x3F;
++			rx_pwr[i] = (val_s8 * 2) - 110;
++
++			if (pktinfo->is_to_self)
++				dm->ofdm_agc_idx[i] = val_s8;
++
++			phy_info->rx_pwr[i] = rx_pwr[i];
++			RSSI = phydm_pw_2_percent(rx_pwr[i]);
++			total_rssi += RSSI;
++
++			phy_info->rx_mimo_signal_strength[i] = (u8)RSSI;
++
++			/* @Get Rx snr value in DB */
++			val_s8 = (s8)(phy_sts->path_rxsnr[i] / 2);
++			phy_info->rx_snr[i] = val_s8;
++
++			/* Record Signal Strength for next packet */
++
++			#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++			if (i == RF_PATH_A) {
++				if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) {
++					phy_info->signal_quality = phydm_sq_patch_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, i, RSSI);
++				} else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER)
++					phy_info->signal_quality = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, RSSI);
++			}
++			#endif
++		}
++
++		/* @(2)PWDB, Average PWDB calculated by hardware (for RA) */
++		val_s8 = phy_sts->cck_sig_qual_ofdm_pwdb_all >> 1;
++		rx_pwr_all = (val_s8  & 0x7f) - 110;
++
++		pwdb_all = phydm_pw_2_percent(rx_pwr_all);
++		pwdb_all_bt = pwdb_all;
++
++		phy_info->rx_pwdb_all = pwdb_all;
++		phy_info->bt_rx_rssi_percentage = pwdb_all_bt;
++		phy_info->rx_power = rx_pwr_all;
++		phy_info->recv_signal_power = rx_pwr_all;
++
++		/* @(3)EVM of HT rate */
++		for (i = 0; i < pktinfo->rate_ss; i++) {
++		/* @Do not use shift operation like "rx_evmX >>= 1"
++		 * because the compilor of free build environment
++		 * fill most significant bit to "zero" when doing shifting
++		 * operation which may change a negative
++		 * value to positive one, then the dbm value
++		 * (which is supposed to be negative) is not correct anymore.
++		 */
++			EVM = phydm_evm_2_percent(phy_sts->stream_rxevm[i]);
++
++			/*@Fill value in RFD, Get the 1st spatial stream only*/
++			if (i == RF_PATH_A)
++				phy_info->signal_quality = (u8)(EVM & 0xff);
++
++			phy_info->rx_mimo_signal_quality[i] = (u8)(EVM & 0xff);
++
++			if (phy_sts->stream_rxevm[i] < 0)
++				evm_tmp = 0 - phy_sts->stream_rxevm[i];
++
++			if (evm_tmp == 64)
++				evm_tmp = 0;
++
++			phy_info->rx_mimo_evm_dbm[i] = (u8)evm_tmp;
++		}
++		phydm_parsing_cfo(dm, pktinfo,
++				  phy_sts->path_cfotail, pktinfo->rate_ss);
++	}
++
++	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->ant_sel;
++	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->ant_sel_b;
++	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antsel_rx_keep_2;
++	#endif
++}
++#endif
++
++#if ODM_IC_11AC_SERIES_SUPPORT
++static s16
++phydm_cfo(s8 value)
++{
++	s16 ret_val;
++
++	if (value < 0) {
++		ret_val = 0 - value;
++		ret_val = (ret_val << 1) + (ret_val >> 1); /*@2.5~=312.5/2^7 */
++		ret_val = ret_val | BIT(12); /*set bit12 as 1 for negative cfo*/
++	} else {
++		ret_val = value;
++		ret_val = (ret_val << 1) + (ret_val >> 1); /* @*2.5~=312.5/2^7*/
++	}
++	return ret_val;
++}
++
++static u8
++phydm_evm_dbm(s8 value)
++{
++	s8 ret_val = value;
++
++	/* @-33dB~0dB to 33dB ~ 0dB */
++	if (ret_val == -128)
++		ret_val = 127;
++	else if (ret_val < 0)
++		ret_val = 0 - ret_val;
++
++	ret_val = ret_val >> 1;
++	return (u8)ret_val;
++}
++
++void phydm_rx_physts_bw_parsing(struct phydm_phyinfo_struct *phy_info,
++				struct phydm_perpkt_info_struct *
++				pktinfo,
++				struct phy_status_rpt_8812 *
++				phy_sts)
++{
++	if (pktinfo->data_rate > ODM_RATE54M) {
++		switch (phy_sts->r_RFMOD) {
++		case 1:
++			if (phy_sts->sub_chnl == 0)
++				phy_info->band_width = 1;
++			else
++				phy_info->band_width = 0;
++			break;
++
++		case 2:
++			if (phy_sts->sub_chnl == 0)
++				phy_info->band_width = 2;
++			else if (phy_sts->sub_chnl == 9 ||
++				 phy_sts->sub_chnl == 10)
++				phy_info->band_width = 1;
++			else
++				phy_info->band_width = 0;
++			break;
++
++		default:
++		case 0:
++			phy_info->band_width = 0;
++			break;
++		}
++	}
++}
++
++void phydm_get_sq(struct dm_struct *dm, struct phydm_phyinfo_struct *phy_info,
++		  u8 is_cck_rate)
++{
++	u8 sq = 0;
++	u8 pwdb_all = phy_info->rx_pwdb_all; /*precentage*/
++	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	u8 rssi = phy_info->rx_mimo_signal_strength[0];
++	#endif
++
++	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) {
++		if (is_cck_rate)
++			sq = phydm_sq_patch_lenovo(dm, 1, pwdb_all, 0, 0);
++		else
++			sq = phydm_sq_patch_lenovo(dm, 0, pwdb_all, 0, rssi);
++	} else
++	#endif
++	{
++		if (is_cck_rate) {
++			if (pwdb_all > 40 && !dm->is_in_hct_test) {
++				sq = 100;
++			} else {
++				if (pwdb_all > 64)
++					sq = 0;
++				else if (pwdb_all < 20)
++					sq = 100;
++				else
++					sq = ((64 - pwdb_all) * 100) / 44;
++			}
++		} else {
++			sq = phy_info->rx_mimo_signal_quality[0];
++		}
++	}
++
++#if 0
++	/* @dbg_print("cck sq = %d\n", sq); */
++#endif
++	phy_info->signal_quality = sq;
++}
++
++void phydm_rx_physts_1st_type(struct dm_struct *dm,
++			      struct phydm_phyinfo_struct *phy_info,
++			      u8 *phy_status_inf,
++			      struct phydm_perpkt_info_struct *pktinfo)
++{
++	u8 i = 0;
++	s8 rx_pwr_db = 0;
++	u8 val = 0; /*tmp value*/
++	s8 val_s8 = 0; /*tmp value*/
++	u8 rssi = 0; /*pre path RSSI*/
++	u8 rf_rx_num = 0;
++	u8 lna_idx = 0, vga_idx = 0;
++	u8 cck_agc_rpt = 0;
++	struct phy_status_rpt_8812 *phy_sts = NULL;
++	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	#endif
++
++	phy_sts = (struct phy_status_rpt_8812 *)phy_status_inf;
++	phydm_rx_physts_bw_parsing(phy_info, pktinfo, phy_sts);
++
++	/* @== [CCK rate] ====================================================*/
++	if (pktinfo->is_cck_rate) {
++		cck_agc_rpt = phy_sts->cfosho[0];
++		lna_idx = (cck_agc_rpt & 0xE0) >> 5;
++		vga_idx = cck_agc_rpt & 0x1F;
++
++		rx_pwr_db = phydm_get_cck_rssi(dm, lna_idx, vga_idx);
++		rssi = phydm_pw_2_percent(rx_pwr_db);
++
++		if (dm->support_ic_type == ODM_RTL8812 &&
++		    !dm->is_cck_high_power) {
++			if (rssi >= 80) {
++				rssi = ((rssi - 80) << 1) +
++					   ((rssi - 80) >> 1) + 80;
++			} else if ((rssi <= 78) && (rssi >= 20)) {
++				rssi += 3;
++			}
++		}
++		dm->cck_lna_idx = lna_idx;
++		dm->cck_vga_idx = vga_idx;
++
++		phy_info->rx_pwdb_all = rssi;
++		phy_info->rx_mimo_signal_strength[0] = rssi;
++	} else {
++	/* @== [OFDM rate] ===================================================*/
++		for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
++			/*@[RSSI]*/
++			if (dm->rf_path_rx_enable & BIT(i))
++				rf_rx_num++;
++
++			if (i < RF_PATH_C)
++				val = phy_sts->gain_trsw[i];
++			else
++				val = phy_sts->gain_trsw_cd[i - 2];
++
++			phy_info->rx_pwr[i] = (val & 0x7F) - 110;
++			rssi = phydm_pw_2_percent(phy_info->rx_pwr[i]);
++			phy_info->rx_mimo_signal_strength[i] = rssi;
++
++			/*@[SNR]*/
++			if (i < RF_PATH_C)
++				val_s8 = phy_sts->rxsnr[i];
++			else if (dm->support_ic_type & (ODM_RTL8814A))
++				val_s8 = (s8)phy_sts->csi_current[i - 2];
++
++			phy_info->rx_snr[i] = val_s8 >> 1;
++
++			/*@[CFO_short  & CFO_tail]*/
++			if (i < RF_PATH_C) {
++				val_s8 = phy_sts->cfosho[i];
++				phy_info->cfo_short[i] = phydm_cfo(val_s8);
++				val_s8 = phy_sts->cfotail[i];
++				phy_info->cfo_tail[i] = phydm_cfo(val_s8);
++			}
++
++			if (i < RF_PATH_C && pktinfo->is_to_self)
++				dm->ofdm_agc_idx[i] = phy_sts->gain_trsw[i];
++		}
++
++	/* @== [PWDB] ========================================================*/
++
++		/*@(Avg PWDB calculated by hardware*/
++		if (!dm->is_mp_chip) /*@8812, 8821*/
++			val = phy_sts->pwdb_all;
++		else
++			val = phy_sts->pwdb_all >> 1; /*old fomula*/
++
++		rx_pwr_db = (val & 0x7f) - 110;
++		phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db);
++
++		/*@(4)EVM of OFDM rate*/
++		for (i = 0; i < pktinfo->rate_ss; i++) {
++			if (!pktinfo->is_cck_rate &&
++			    pktinfo->data_rate <= ODM_RATE54M) {
++				val_s8 = phy_sts->sigevm;
++			} else if (i < RF_PATH_C) {
++				if (phy_sts->rxevm[i] == -128)
++					phy_sts->rxevm[i] = -25;
++
++				val_s8 = phy_sts->rxevm[i];
++			} else {
++				if (phy_sts->rxevm_cd[i - 2] == -128)
++					phy_sts->rxevm_cd[i - 2] = -25;
++
++				val_s8 = phy_sts->rxevm_cd[i - 2];
++			}
++			/*@[EVM to 0~100%]*/
++			val = phydm_evm_2_percent(val_s8);
++			phy_info->rx_mimo_signal_quality[i] = val;
++			/*@[EVM dBm]*/
++			phy_info->rx_mimo_evm_dbm[i] = phydm_evm_dbm(val_s8);
++		}
++		phydm_parsing_cfo(dm, pktinfo,
++				  phy_sts->cfotail, pktinfo->rate_ss);
++	}
++
++	/* @== [General Info] ================================================*/
++
++	phy_info->rx_power = rx_pwr_db;
++	phy_info->bt_rx_rssi_percentage = phy_info->rx_pwdb_all;
++	phy_info->recv_signal_power = phy_info->rx_power;
++	phydm_get_sq(dm, phy_info, pktinfo->is_cck_rate);
++
++	dm->rx_pwdb_ave = dm->rx_pwdb_ave + phy_info->rx_pwdb_all;
++
++	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	fat_tab->hw_antsw_occur = phy_sts->hw_antsw_occur;
++	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_anta;
++	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_antb;
++	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_antc;
++	dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_antd;
++	#endif
++}
++
++#endif
++
++void phydm_reset_rssi_for_dm(struct dm_struct *dm, u8 station_id)
++{
++	struct cmn_sta_info *sta;
++
++	sta = dm->phydm_sta_info[station_id];
++
++	if (!is_sta_active(sta))
++		return;
++	PHYDM_DBG(dm, DBG_RSSI_MNTR, "Reset RSSI for macid = (( %d ))\n",
++		  station_id);
++
++	sta->rssi_stat.rssi_cck = -1;
++	sta->rssi_stat.rssi_ofdm = -1;
++	sta->rssi_stat.rssi = -1;
++	sta->rssi_stat.ofdm_pkt_cnt = 0;
++	sta->rssi_stat.cck_pkt_cnt = 0;
++	sta->rssi_stat.cck_sum_power = 0;
++	sta->rssi_stat.is_send_rssi = RA_RSSI_STATE_INIT;
++	sta->rssi_stat.packet_map = 0;
++	sta->rssi_stat.valid_bit = 0;
++}
++
++#if (ODM_IC_11N_SERIES_SUPPORT || ODM_IC_11AC_SERIES_SUPPORT)
++
++s32 phydm_get_rssi_8814_ofdm(struct dm_struct *dm, u8 *rssi_in)
++{
++	s32 rssi_avg;
++	u8 rx_count = 0;
++	u64 rssi_linear = 0;
++
++	if (dm->rx_ant_status & BB_PATH_A) {
++		rx_count++;
++		rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_A]);
++	}
++
++	if (dm->rx_ant_status & BB_PATH_B) {
++		rx_count++;
++		rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_B]);
++	}
++
++	if (dm->rx_ant_status & BB_PATH_C) {
++		rx_count++;
++		rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_C]);
++	}
++
++	if (dm->rx_ant_status & BB_PATH_D) {
++		rx_count++;
++		rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_D]);
++	}
++
++	/* @Rounding and removing fractional bits */
++	rssi_linear = (rssi_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
++
++	/* @Calculate average RSSI */
++	switch (rx_count) {
++	case 2:
++		rssi_linear = DIVIDED_2(rssi_linear);
++		break;
++	case 3:
++		rssi_linear = DIVIDED_3(rssi_linear);
++		break;
++	case 4:
++		rssi_linear = DIVIDED_4(rssi_linear);
++		break;
++	}
++	rssi_avg = odm_convert_to_db(rssi_linear);
++
++	return rssi_avg;
++}
++
++void phydm_process_rssi_for_dm(struct dm_struct *dm,
++			       struct phydm_phyinfo_struct *phy_info,
++			       struct phydm_perpkt_info_struct *pktinfo)
++{
++	s32 rssi_ave = 0; /*@average among all paths*/
++	s8 rssi_all = 0; /*@average value of CCK & OFDM*/
++	s8 rssi_cck_tmp = 0, rssi_ofdm_tmp = 0;
++	u8 i = 0;
++	u8 rssi_max = 0, rssi_min = 0;
++	u32 w1 = 0, w2 = 0; /*weighting*/
++	u8 send_rssi_2_fw = 0;
++	u8 *rssi_tmp = NULL;
++	struct cmn_sta_info *sta = NULL;
++	struct rssi_info *rssi_t = NULL;
++	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	#endif
++	#endif
++
++	if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
++		return;
++
++	#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++	odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(dm, phy_info, pktinfo);
++	#endif
++
++	sta = dm->phydm_sta_info[pktinfo->station_id];
++
++	if (!is_sta_active(sta))
++		return;
++
++	rssi_t = &sta->rssi_stat;
++
++	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++	if ((dm->support_ability & ODM_BB_ANT_DIV) &&
++	    fat_tab->enable_ctrl_frame_antdiv) {
++		if (pktinfo->is_packet_match_bssid)
++			dm->data_frame_num++;
++
++		if (fat_tab->use_ctrl_frame_antdiv) {
++			if (!pktinfo->is_to_self) /*@data frame + CTRL frame*/
++				return;
++		} else {
++			/*@data frame only*/
++			if (!pktinfo->is_packet_match_bssid)
++				return;
++		}
++	} else
++	#endif
++	#endif
++	{
++		if (!pktinfo->is_packet_match_bssid) /*@data frame only*/
++			return;
++	}
++
++	if (pktinfo->is_packet_beacon) {
++		dm->phy_dbg_info.num_qry_beacon_pkt++;
++		dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;
++	}
++
++	/* @--------------Statistic for antenna/path diversity--------------- */
++	#ifdef ODM_EVM_ENHANCE_ANTDIV
++	phydm_rx_rate_for_antdiv(dm, pktinfo);
++	#endif
++
++	#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++	if (dm->support_ability & ODM_BB_ANT_DIV)
++		odm_process_rssi_for_ant_div(dm, phy_info, pktinfo);
++	#endif
++
++	#if (defined(CONFIG_PATH_DIVERSITY))
++	if (dm->support_ability & ODM_BB_PATH_DIV)
++		phydm_process_rssi_for_path_div(dm, phy_info, pktinfo);
++	#endif
++	/* @----------------------------------------------------------------- */
++
++	rssi_cck_tmp = rssi_t->rssi_cck;
++	rssi_ofdm_tmp = rssi_t->rssi_ofdm;
++	rssi_all = rssi_t->rssi;
++
++	if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_beacon))
++		return;
++
++	if (!pktinfo->is_cck_rate) {
++/* @=== [ofdm RSSI] ======================================================== */
++		rssi_tmp = phy_info->rx_mimo_signal_strength;
++
++		#if (RTL8814A_SUPPORT == 1)
++		if (dm->support_ic_type & (ODM_RTL8814A)) {
++			rssi_ave = phydm_get_rssi_8814_ofdm(dm, rssi_tmp);
++		} else
++		#endif
++		{
++			if (rssi_tmp[RF_PATH_B] == 0) {
++				rssi_ave = rssi_tmp[RF_PATH_A];
++			} else {
++				if (rssi_tmp[RF_PATH_A] > rssi_tmp[RF_PATH_B]) {
++					rssi_max = rssi_tmp[RF_PATH_A];
++					rssi_min = rssi_tmp[RF_PATH_B];
++				} else {
++					rssi_max = rssi_tmp[RF_PATH_B];
++					rssi_min = rssi_tmp[RF_PATH_A];
++				}
++				if ((rssi_max - rssi_min) < 3)
++					rssi_ave = rssi_max;
++				else if ((rssi_max - rssi_min) < 6)
++					rssi_ave = rssi_max - 1;
++				else if ((rssi_max - rssi_min) < 10)
++					rssi_ave = rssi_max - 2;
++				else
++					rssi_ave = rssi_max - 3;
++			}
++		}
++
++		/* OFDM MA RSSI */
++		if (rssi_ofdm_tmp <= 0) { /* @initialize */
++			rssi_ofdm_tmp = (s8)phy_info->rx_pwdb_all;
++		} else {
++			rssi_ofdm_tmp = (s8)WEIGHTING_AVG(rssi_ofdm_tmp,
++							  (1 << RSSI_MA) - 1,
++							  rssi_ave, 1);
++			if (phy_info->rx_pwdb_all > (u32)rssi_ofdm_tmp)
++				rssi_ofdm_tmp++;
++		}
++
++		PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi_ofdm=%d\n", rssi_ofdm_tmp);
++	} else {
++/* @=== [cck RSSI] ========================================================= */
++		rssi_ave = phy_info->rx_pwdb_all;
++
++		if (rssi_t->cck_pkt_cnt <= 63)
++			rssi_t->cck_pkt_cnt++;
++
++		/* @1 Process CCK RSSI */
++		if (rssi_cck_tmp <= 0) { /* @initialize */
++			rssi_cck_tmp = (s8)phy_info->rx_pwdb_all;
++			rssi_t->cck_sum_power = (u16)phy_info->rx_pwdb_all;
++			rssi_t->cck_pkt_cnt = 1; /*reset*/
++			PHYDM_DBG(dm, DBG_RSSI_MNTR, "[1]CCK_INIT\n");
++		} else if (rssi_t->cck_pkt_cnt <= CCK_RSSI_INIT_COUNT) {
++			rssi_t->cck_sum_power = rssi_t->cck_sum_power +
++						(u16)phy_info->rx_pwdb_all;
++
++			rssi_cck_tmp = rssi_t->cck_sum_power /
++				       rssi_t->cck_pkt_cnt;
++
++			PHYDM_DBG(dm, DBG_RSSI_MNTR,
++				  "[2]SumPow=%d, cck_pkt=%d\n",
++				  rssi_t->cck_sum_power, rssi_t->cck_pkt_cnt);
++		} else {
++			rssi_cck_tmp = (s8)WEIGHTING_AVG(rssi_cck_tmp,
++							 (1 << RSSI_MA) - 1,
++							 phy_info->rx_pwdb_all,
++							 1);
++			if (phy_info->rx_pwdb_all > (u32)rssi_cck_tmp)
++				rssi_cck_tmp++;
++		}
++		PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi_cck=%d\n", rssi_cck_tmp);
++	}
++
++/* @=== [ofdm + cck weighting RSSI] ========================================= */
++	if (!pktinfo->is_cck_rate) {
++		if (rssi_t->ofdm_pkt_cnt < 8 && !(rssi_t->packet_map & BIT(7)))
++			rssi_t->ofdm_pkt_cnt++; /*OFDM packet cnt in bitmap*/
++
++		rssi_t->packet_map = (rssi_t->packet_map << 1) | BIT(0);
++	} else {
++		if (rssi_t->ofdm_pkt_cnt > 0 && rssi_t->packet_map & BIT(7))
++			rssi_t->ofdm_pkt_cnt--;
++
++		rssi_t->packet_map = rssi_t->packet_map << 1;
++	}
++
++	if (rssi_t->ofdm_pkt_cnt == 8) {
++		rssi_all = rssi_ofdm_tmp;
++	} else {
++		if (rssi_t->valid_bit < 8)
++			rssi_t->valid_bit++;
++
++		if (rssi_t->valid_bit == 8) {
++			if (rssi_t->ofdm_pkt_cnt > 4)
++				w1 = 64;
++			else
++				w1 = (u32)(rssi_t->ofdm_pkt_cnt << 4);
++
++			w2 = 64 - w1;
++
++			rssi_all = (s8)((w1 * (u32)rssi_ofdm_tmp +
++					 w2 * (u32)rssi_cck_tmp) >> 6);
++		} else if (rssi_t->valid_bit != 0) { /*@(valid_bit > 8)*/
++			w1 = (u32)rssi_t->ofdm_pkt_cnt;
++			w2 = (u32)(rssi_t->valid_bit - rssi_t->ofdm_pkt_cnt);
++			rssi_all = (s8)WEIGHTING_AVG((u32)rssi_ofdm_tmp, w1,
++						     (u32)rssi_cck_tmp, w2);
++		} else {
++			rssi_all = 0;
++		}
++	}
++	PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi=%d,w1=%d,w2=%d\n", rssi_all, w1, w2);
++
++	if ((rssi_t->ofdm_pkt_cnt >= 1 || rssi_t->cck_pkt_cnt >= 5) &&
++	    rssi_t->is_send_rssi == RA_RSSI_STATE_INIT) {
++		send_rssi_2_fw = 1;
++		rssi_t->is_send_rssi = RA_RSSI_STATE_SEND;
++	}
++
++	rssi_t->rssi_cck = rssi_cck_tmp;
++	rssi_t->rssi_ofdm = rssi_ofdm_tmp;
++	rssi_t->rssi = rssi_all;
++
++	if (send_rssi_2_fw) { /* Trigger init rate by RSSI */
++		if (rssi_t->ofdm_pkt_cnt != 0)
++			rssi_t->rssi = rssi_ofdm_tmp;
++
++		PHYDM_DBG(dm, DBG_RSSI_MNTR,
++			  "[Send to FW] PWDB=%d, ofdm_pkt=%d, cck_pkt=%d\n",
++			  rssi_all, rssi_t->ofdm_pkt_cnt, rssi_t->cck_pkt_cnt);
++	}
++
++#if 0
++	/* @dbg_print("ofdm_pkt=%d, weighting=%d\n", ofdm_pkt_cnt, weighting);*/
++	/* @dbg_print("rssi_ofdm_tmp=%d, rssi_all=%d, rssi_cck_tmp=%d\n", */
++	/*	rssi_ofdm_tmp, rssi_all, rssi_cck_tmp); */
++#endif
++}
++#endif
++
++#ifdef PHYSTS_3RD_TYPE_SUPPORT
++#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
++void phydm_physts_auto_switch_jgr3_reset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct;
++
++	pkt_proc->phy_ppdu_cnt = 0xff;
++	pkt_proc->mac_ppdu_cnt = 0xff;
++	pkt_proc->page_bitmap_record = 0;
++}
++
++boolean phydm_physts_auto_switch_jgr3(void *dm_void, u8 *phy_sts,
++				      struct phydm_perpkt_info_struct *pktinfo)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct;
++	boolean is_skip_physts_parsing = false;
++	u8 phy_sts_byte0 = (*phy_sts & 0xff);
++	u8 phy_ppdu_cnt_pre = 0, mac_ppdu_cnt_pre = 0;
++	u8 ppdu_phy_rate_pre = 0, ppdu_macid_pre = 0;
++	u8 page = phy_sts_byte0 & 0xf;
++
++	if (!pkt_proc->physts_auto_swch_en)
++		return is_skip_physts_parsing;
++
++	phy_ppdu_cnt_pre = pkt_proc->phy_ppdu_cnt;
++	mac_ppdu_cnt_pre = pkt_proc->mac_ppdu_cnt;
++	ppdu_phy_rate_pre = pkt_proc->ppdu_phy_rate;
++	ppdu_macid_pre = pkt_proc->ppdu_macid;
++
++	pkt_proc->phy_ppdu_cnt = (phy_sts_byte0 & 0x30) >> 4;
++	pkt_proc->mac_ppdu_cnt = pktinfo->ppdu_cnt;
++	pkt_proc->ppdu_phy_rate = pktinfo->data_rate;
++	pkt_proc->ppdu_macid = pktinfo->station_id;
++
++	PHYDM_DBG(dm, DBG_PHY_STATUS,
++		  "[rate:0x%x] PPDU mac{pre, curr}= {%d, %d}, phy{pre, curr}= {%d, %d}\n",
++		  pktinfo->data_rate, mac_ppdu_cnt_pre, pkt_proc->mac_ppdu_cnt,
++		  phy_ppdu_cnt_pre, pkt_proc->phy_ppdu_cnt);
++
++	if (pktinfo->data_rate < ODM_RATEMCS0) {
++		pkt_proc->page_bitmap_record = 0;
++		return is_skip_physts_parsing;
++	}
++
++	if (ppdu_macid_pre == pkt_proc->ppdu_macid &&
++	    ppdu_phy_rate_pre == pkt_proc->ppdu_phy_rate &&
++	    phy_ppdu_cnt_pre == pkt_proc->phy_ppdu_cnt &&
++	    mac_ppdu_cnt_pre == pkt_proc->mac_ppdu_cnt) {
++		if (pkt_proc->page_bitmap_record & BIT(page)) {
++			/*@PHYDM_DBG(dm, DBG_PHY_STATUS, "collect page-%d enough\n", page);*/
++			is_skip_physts_parsing = true;
++		} else if (pkt_proc->page_bitmap_record ==
++			   pkt_proc->page_bitmap_target) {
++			/*@PHYDM_DBG(dm, DBG_PHY_STATUS, "collect all enough\n");*/
++			is_skip_physts_parsing = true;
++		} else {
++			/*@PHYDM_DBG(dm, DBG_PHY_STATUS, "update page-%d\n", page);*/
++			pkt_proc->page_bitmap_record |= BIT(page);
++		}
++		pkt_proc->is_1st_mpdu = false;
++	} else {
++		/*@PHYDM_DBG(dm, DBG_PHY_STATUS, "[New Pkt] update page-%d\n", page);*/
++		pkt_proc->page_bitmap_record = BIT(page);
++		pkt_proc->is_1st_mpdu = true;
++	}
++
++	PHYDM_DBG(dm, DBG_PHY_STATUS,
++		  "bitmap{record, target}= {0x%x, 0x%x}\n",
++		  pkt_proc->page_bitmap_record,
++		  pkt_proc->page_bitmap_target);
++
++	return is_skip_physts_parsing;
++}
++
++void phydm_physts_auto_switch_jgr3_set(void *dm_void, boolean enable,
++				       u8 bitmap_en)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct;
++	u16 en_page_num = 1;
++
++	if (!(dm->support_ic_type & PHYSTS_AUTO_SWITCH_IC))
++		return;
++#if 0
++	if (!(dm->support_ic_type & PHYSTS_3RD_TYPE_IC))
++		return;
++#endif
++	pkt_proc->physts_auto_swch_en = enable;
++	pkt_proc->page_bitmap_target = bitmap_en;
++	phydm_physts_auto_switch_jgr3_reset(dm);
++	en_page_num = phydm_ones_num_in_bitmap((u64)bitmap_en, 8);
++
++	PHYDM_DBG(dm, DBG_CMN, "[%s]en=%d, bitmap_en=%d, en_page_num=%d\n",
++		  __func__, enable, bitmap_en, en_page_num);
++
++	if (enable) {
++		/*@per MPDU latch & update phy-staatus*/
++		odm_set_mac_reg(dm, R_0x60c, BIT(31), 1);
++		/*@Update Period (OFDM Symbol)*/
++		odm_set_bb_reg(dm, R_0x8c0, 0xfc000, 3);
++		/*@switchin bitmap*/
++		odm_set_bb_reg(dm, R_0x8c4, 0x7f80000, bitmap_en);
++		/*@mode 3*/
++		odm_set_bb_reg(dm, R_0x8c4, (BIT(28) | BIT(27)), 3);
++	} else {
++		odm_set_mac_reg(dm, R_0x60c, BIT(31), 0);
++		odm_set_bb_reg(dm, R_0x8c0, 0xfc000, 0x1);
++		odm_set_bb_reg(dm, R_0x8c4, 0x7f80000, 0x2);
++		odm_set_bb_reg(dm, R_0x8c4, (BIT(28) | BIT(27)), 0);
++	}
++}
++
++void phydm_avg_condi_num(void *dm_void,
++			 struct phydm_phyinfo_struct *phy_info,
++			 struct phydm_perpkt_info_struct *pktinfo)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
++	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
++	u16 size_th = PHY_HIST_SIZE - 1; /*size of threshold*/
++	u16 val = 0, intvl = 0;
++	u8 arry_idx = 0;
++
++	if (pktinfo->rate_ss == 1)
++		return;
++
++	arry_idx = pktinfo->rate_ss - 1;
++
++	dbg_s->p4_cnt[arry_idx]++;
++	dbg_s->cn_sum[arry_idx] += dbg_i->condition_num_seg0;
++
++	/*CN Histogram*/
++	val = (u16)dbg_i->condition_num_seg0;
++	intvl = phydm_find_intrvl(dm, val, dbg_i->cn_hist_th, size_th);
++	dbg_s->cn_hist[arry_idx][intvl]++;
++
++	dbg_i->condi_num = (u32)dbg_i->condition_num_seg0; /*will remove*/
++}
++#endif
++
++void phydm_print_phystat_jgr3(struct dm_struct *dm, u8 *phy_sts,
++			      struct phydm_perpkt_info_struct *pktinfo,
++			      struct phydm_phyinfo_struct *phy_info)
++{
++	struct phy_sts_rpt_jgr3_type0 *rpt0 = NULL;
++	struct phy_sts_rpt_jgr3_type1 *rpt1 = NULL;
++	struct phy_sts_rpt_jgr3_type2_3 *rpt2 = NULL;
++	struct phy_sts_rpt_jgr3_type4 *rpt3 = NULL;
++	struct phy_sts_rpt_jgr3_type5 *rpt4 = NULL;
++	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
++	u8 phy_status_page_num = (*phy_sts & 0xf);
++	u32 *phy_status_tmp = NULL;
++	u8 i = 0;
++	/*u32 size = PHY_STATUS_JRGUAR3_DW_LEN << 2;*/
++
++	if (!(dm->debug_components & DBG_PHY_STATUS))
++		return;
++
++	rpt0 = (struct phy_sts_rpt_jgr3_type0 *)phy_sts;
++	rpt1 = (struct phy_sts_rpt_jgr3_type1 *)phy_sts;
++	rpt2 = (struct phy_sts_rpt_jgr3_type2_3 *)phy_sts;
++	rpt3 = (struct phy_sts_rpt_jgr3_type4 *)phy_sts;
++	rpt4 = (struct phy_sts_rpt_jgr3_type5 *)phy_sts;
++
++	phy_status_tmp = (u32 *)phy_sts;
++
++	if (dbg->show_phy_sts_all_pkt == 0) {
++		if (!pktinfo->is_packet_match_bssid)
++			return;
++	}
++
++	dbg->show_phy_sts_cnt++;
++
++	if (dbg->show_phy_sts_max_cnt != SHOW_PHY_STATUS_UNLIMITED) {
++		if (dbg->show_phy_sts_cnt > dbg->show_phy_sts_max_cnt)
++			return;
++	}
++
++	if (phy_status_page_num == 0)
++		pr_debug("Phy Status Rpt: CCK\n");
++	else
++		pr_debug("Phy Status Rpt: OFDM_%d\n", phy_status_page_num);
++
++	pr_debug("StaID=%d, RxRate = 0x%x match_bssid=%d, ppdu_cnt=%d\n",
++		 pktinfo->station_id, pktinfo->data_rate,
++		 pktinfo->is_packet_match_bssid, pktinfo->ppdu_cnt);
++
++	for (i = 0; i < PHY_STATUS_JRGUAR3_DW_LEN; i++)
++		pr_debug("Offset[%d:%d] = 0x%x\n",
++			 ((4 * i) + 3), (4 * i), phy_status_tmp[i]);
++
++	if (phy_status_page_num == 0) { /* @CCK(default) */
++		pr_debug("[0] Pkt_cnt=%d, Channel_msb=%d, Pwdb_a=%d, Gain_a=%d, TRSW=%d, AGC_table_b=%d, AGC_table_c=%d,\n",
++			 rpt0->pkt_cnt, rpt0->channel_msb, rpt0->pwdb_a,
++			 rpt0->gain_a, rpt0->trsw, rpt0->agc_table_b,
++			 rpt0->agc_table_c);
++		pr_debug("[4] Path_Sel_o=%d, Gnt_BT_keep_cnt=%d, HW_AntSW_occur_keep_cck=%d,\n Band=%d, Channel=%d, AGC_table_a=%d, l_RXSC=%d, AGC_table_d=%d\n",
++			 rpt0->path_sel_o, rpt0->gnt_bt_keep_cck,
++			 rpt0->hw_antsw_occur_keep_cck, rpt0->band,
++			 rpt0->channel, rpt0->agc_table_a, rpt0->l_rxsc,
++			 rpt0->agc_table_d);
++		pr_debug("[8] AntIdx={%d, %d, %d, %d}, Length=%d\n",
++			 rpt0->antidx_d, rpt0->antidx_c, rpt0->antidx_b,
++			 rpt0->antidx_a, rpt0->length);
++		pr_debug("[12] MF_off=%d, SQloss=%d, lockbit=%d, raterr=%d, rxrate=%d, lna_h_a=%d, CCK_BB_power_a=%d, lna_l_a=%d, vga_a=%d, sq=%d\n",
++			 rpt0->mf_off, rpt0->sqloss, rpt0->lockbit,
++			 rpt0->raterr, rpt0->rxrate, rpt0->lna_h_a,
++			 rpt0->bb_power_a, rpt0->lna_l_a, rpt0->vga_a,
++			 rpt0->signal_quality);
++		pr_debug("[16] Gain_b=%d, lna_h_b=%d, CCK_BB_power_b=%d, lna_l_b=%d, vga_b=%d, Pwdb_b=%d\n",
++			 rpt0->gain_b, rpt0->lna_h_b, rpt0->bb_power_b,
++			 rpt0->lna_l_b, rpt0->vga_b, rpt0->pwdb_b);
++		pr_debug("[20] Gain_c=%d, lna_h_c=%d, CCK_BB_power_c=%d, lna_l_c=%d, vga_c=%d, Pwdb_c=%d\n",
++			 rpt0->gain_c, rpt0->lna_h_c, rpt0->bb_power_c,
++			 rpt0->lna_l_c, rpt0->vga_c, rpt0->pwdb_c);
++		pr_debug("[24] Gain_d=%d, lna_h_d=%d, CCK_BB_power_d=%d, lna_l_d=%d, vga_d=%d, Pwdb_d=%d\n",
++			 rpt0->gain_c, rpt0->lna_h_c, rpt0->bb_power_c,
++			 rpt0->lna_l_c, rpt0->vga_c, rpt0->pwdb_c);
++	} else if (phy_status_page_num == 1) {
++		pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_pri_msb=%d, Pkt_cnt=%d,\n",
++			 rpt1->pwdb_c, rpt1->pwdb_b, rpt1->pwdb_a,
++			 rpt1->channel_pri_msb, rpt1->pkt_cnt);
++		pr_debug("[4] BF: %d, stbc=%d, ldpc=%d, gnt_bt=%d, band=%d, Ch_pri_lsb=%d, rxsc[ht, l]={%d, %d}, pwdb[D]=%d\n",
++			 rpt1->beamformed, rpt1->stbc, rpt1->ldpc, rpt1->gnt_bt,
++			 rpt1->band, rpt1->channel_pri_lsb, rpt1->ht_rxsc,
++			 rpt1->l_rxsc, rpt1->pwdb_d);
++		pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}, Channel_sec[msb,lsb]={%d, %d}\n",
++			 rpt1->antidx_d, rpt1->antidx_c,
++			 rpt1->antidx_b, rpt1->antidx_a,
++			 rpt1->hw_antsw_occur_d, rpt1->hw_antsw_occur_c,
++			 rpt1->hw_antsw_occur_b, rpt1->hw_antsw_occur_a,
++			 rpt1->channel_sec_msb, rpt1->channel_sec_lsb);
++		pr_debug("[12] GID=%d, PAID[msb,lsb]={%d,%d}\n",
++			 rpt1->gid, rpt1->paid_msb, rpt1->paid);
++		pr_debug("[16] RX_EVM[D:A]={%d, %d, %d, %d}\n",
++			 rpt1->rxevm[3], rpt1->rxevm[2],
++			 rpt1->rxevm[1], rpt1->rxevm[0]);
++		pr_debug("[20] CFO_tail[D:A]={%d, %d, %d, %d}\n",
++			 rpt1->cfo_tail[3], rpt1->cfo_tail[2],
++			 rpt1->cfo_tail[1], rpt1->cfo_tail[0]);
++		pr_debug("[24] RX_SNR[D:A]={%d, %d, %d, %d}\n\n",
++			 rpt1->rxsnr[3], rpt1->rxsnr[2],
++			 rpt1->rxsnr[1], rpt1->rxsnr[0]);
++	} else if (phy_status_page_num == 2 || phy_status_page_num == 3) {
++		pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n",
++			 rpt2->pwdb[2], rpt2->pwdb[1], rpt2->pwdb[0],
++			 rpt2->channel_msb, rpt2->pkt_cnt);
++		pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, Gnt_BT=%d, band=%d, CH_lsb=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n",
++			 rpt2->beamformed, rpt2->stbc, rpt2->ldpc, rpt2->gnt_bt,
++			 rpt2->band, rpt2->channel_lsb,
++			 rpt2->ht_rxsc, rpt2->l_rxsc, rpt2->pwdb[3]);
++		pr_debug("[8] AgcTab[D:A]={%d, %d, %d, %d}, pwed_th=%d, shift_l_map=%d\n",
++			 rpt2->agc_table_d, rpt2->agc_table_c,
++			 rpt2->agc_table_b, rpt2->agc_table_a,
++			 rpt2->pwed_th, rpt2->shift_l_map);
++		pr_debug("[12] AvgNoisePowerdB=%d, mp_gain_c[msb, lsb]={%d, %d}, mp_gain_b[msb, lsb]={%d, %d}, mp_gain_a=%d, cnt_cca2agc_rdy=%d\n",
++			 rpt2->avg_noise_pwr_lsb, rpt2->mp_gain_c_msb,
++			 rpt2->mp_gain_c_lsb, rpt2->mp_gain_b_msb,
++			 rpt2->mp_gain_b_lsb, rpt2->mp_gain_a,
++			 rpt2->cnt_cca2agc_rdy);
++		pr_debug("[16] HT AAGC gain[B:A]={%d, %d}, AAGC step[D:A]={%d, %d, %d, %d}, IsFreqSelectFadimg=%d, mp_gain_d=%d\n",
++			 rpt2->ht_aagc_gain[1], rpt2->ht_aagc_gain[0],
++			 rpt2->aagc_step_d, rpt2->aagc_step_c,
++			 rpt2->aagc_step_b, rpt2->aagc_step_a,
++			 rpt2->is_freq_select_fading, rpt2->mp_gain_d);
++		pr_debug("[20] DAGC gain ant[B:A]={%d, %d}, HT AAGC gain[D:C]={%d, %d}\n",
++			 rpt2->dagc_gain[1], rpt2->dagc_gain[0],
++			 rpt2->ht_aagc_gain[3], rpt2->ht_aagc_gain[2]);
++		pr_debug("[24] AvgNoisePwerdB=%d, syn_count[msb, lsb]={%d, %d}, counter=%d, DAGC gain ant[D:C]={%d, %d}\n",
++			 rpt2->avg_noise_pwr_msb, rpt2->syn_count_msb,
++			 rpt2->syn_count_lsb, rpt2->counter,
++			 rpt2->dagc_gain[3], rpt2->dagc_gain[2]);
++	} else if (phy_status_page_num == 4) { /*type 4*/
++		pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n",
++			 rpt3->pwdb[2], rpt3->pwdb[1], rpt3->pwdb[0],
++			 rpt3->channel_msb, rpt3->pkt_cnt);
++		pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, GNT_BT=%d, band=%d, CH_pri=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n",
++			 rpt3->beamformed, rpt3->stbc, rpt3->ldpc, rpt3->gnt_bt,
++			 rpt3->band, rpt3->channel_lsb, rpt3->ht_rxsc,
++			 rpt3->l_rxsc, rpt3->pwdb[3]);
++		pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}, Training_done[D:A]={%d, %d, %d, %d},\n    BadToneCnt_CN_excess_0=%d, BadToneCnt_min_eign_0=%d\n",
++			 rpt3->antidx_d, rpt3->antidx_c,
++			 rpt3->antidx_b, rpt3->antidx_a,
++			 rpt3->hw_antsw_occur_d, rpt3->hw_antsw_occur_c,
++			 rpt3->hw_antsw_occur_b, rpt3->hw_antsw_occur_a,
++			 rpt3->training_done_d, rpt3->training_done_c,
++			 rpt3->training_done_b, rpt3->training_done_a,
++			 rpt3->bad_tone_cnt_cn_excess_0,
++			 rpt3->bad_tone_cnt_min_eign_0);
++		pr_debug("[12] avg_cond_num_1=%d, avg_cond_num_0=%d, bad_tone_cnt_cn_excess_1=%d,\n     bad_tone_cnt_min_eign_1=%d, Tx_pkt_cnt=%d\n",
++			 ((rpt3->avg_cond_num_1_msb << 1) |
++			 rpt3->avg_cond_num_1_lsb),
++			 rpt3->avg_cond_num_0, rpt3->bad_tone_cnt_cn_excess_1,
++			 rpt3->bad_tone_cnt_min_eign_1, rpt3->tx_pkt_cnt);
++		pr_debug("[16] Stream RXEVM[D:A]={%d, %d, %d, %d}\n",
++			 rpt3->rxevm[3], rpt3->rxevm[2],
++			 rpt3->rxevm[1], rpt3->rxevm[0]);
++		pr_debug("[20] Eigenvalue[D:A]={%d, %d, %d, %d}\n",
++			 rpt3->eigenvalue[3], rpt3->eigenvalue[2],
++			 rpt3->eigenvalue[1], rpt3->eigenvalue[0]);
++		pr_debug("[24] RX SNR[D:A]={%d, %d, %d, %d}\n",
++			 rpt3->rxsnr[3], rpt3->rxsnr[2],
++			 rpt3->rxsnr[1], rpt3->rxsnr[0]);
++	} else if (phy_status_page_num == 5) { /*type 5*/
++		pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n",
++			 rpt4->pwdb[2], rpt4->pwdb[1], rpt4->pwdb[0],
++			 rpt4->channel_msb, rpt4->pkt_cnt);
++		pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, GNT_BT=%d, band=%d, CH_pri=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n",
++			 rpt4->beamformed, rpt4->stbc, rpt4->ldpc, rpt4->gnt_bt,
++			 rpt4->band, rpt4->channel_lsb, rpt4->ht_rxsc,
++			 rpt4->l_rxsc, rpt4->pwdb[3]);
++		pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}\n",
++			 rpt4->antidx_d, rpt4->antidx_c,
++			 rpt4->antidx_b, rpt4->antidx_a,
++			 rpt4->hw_antsw_occur_d, rpt4->hw_antsw_occur_c,
++			 rpt4->hw_antsw_occur_b, rpt4->hw_antsw_occur_a);
++		pr_debug("[12] Inf_posD[1,0]={%d, %d}, Inf_posC[1,0]={%d, %d}, Inf_posB[1,0]={%d, %d}, Inf_posA[1,0]={%d, %d}, Tx_pkt_cnt=%d\n",
++			 rpt4->inf_pos_1_D_flg, rpt4->inf_pos_0_D_flg,
++			 rpt4->inf_pos_1_C_flg, rpt4->inf_pos_0_C_flg,
++			 rpt4->inf_pos_1_B_flg, rpt4->inf_pos_0_B_flg,
++			 rpt4->inf_pos_1_A_flg, rpt4->inf_pos_0_A_flg,
++			 rpt4->tx_pkt_cnt);
++		pr_debug("[16] Inf_pos_B[1,0]={%d, %d}, Inf_pos_A[1,0]={%d, %d}\n",
++			 rpt4->inf_pos_1_b, rpt4->inf_pos_0_b,
++			 rpt4->inf_pos_1_a, rpt4->inf_pos_0_a);
++		pr_debug("[20] Inf_pos_D[1,0]={%d, %d}, Inf_pos_C[1,0]={%d, %d}\n",
++			 rpt4->inf_pos_1_d, rpt4->inf_pos_0_d,
++			 rpt4->inf_pos_1_c, rpt4->inf_pos_0_c);
++	}
++}
++
++void phydm_reset_phy_info_jgr3(struct dm_struct *phydm,
++			       struct phydm_phyinfo_struct *phy_info)
++{
++	u8 i;
++
++	phy_info->rx_pwdb_all = 0;
++	phy_info->signal_quality = 0;
++	phy_info->band_width = 0;
++	phy_info->rx_count = 0;
++	phy_info->rx_power = -110;
++	phy_info->recv_signal_power = -110;
++	phy_info->bt_rx_rssi_percentage = 0;
++	phy_info->signal_strength = 0;
++	phy_info->channel = 0;
++	phy_info->is_mu_packet = 0;
++	phy_info->is_beamformed = 0;
++	phy_info->rxsc = 0;
++
++	for (i = 0; i < 4; i++) {
++		phy_info->rx_mimo_signal_strength[i] = 0;
++		phy_info->rx_mimo_signal_quality[i] = 0;
++		phy_info->rx_mimo_evm_dbm[i] = 0;
++		phy_info->cfo_short[i] = 0;
++		phy_info->cfo_tail[i] = 0;
++		phy_info->rx_pwr[i] = -110;
++		phy_info->rx_snr[i] = 0;
++	}
++}
++
++#if 0
++void phydm_per_path_info_3rd(u8 rx_path, s8 pwr, s8 rx_evm, s8 cfo_tail,
++			     s8 rx_snr, struct phydm_phyinfo_struct *phy_info)
++{
++	u8 evm_dbm = 0;
++	u8 evm_percentage = 0;
++
++	/* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */
++
++	evm_dbm = (rx_evm == -128) ? 0 : ((u8)(0 - rx_evm) >> 1);
++	evm_percentage = (evm_dbm >= 34) ? 100 : evm_dbm * 3;
++
++	phy_info->rx_pwr[rx_path] = pwr;
++
++	/*@CFO(kHz) = CFO_tail * 312.5(kHz) / 2^7 ~= CFO tail * 5/2 (kHz)*/
++	phy_info->cfo_tail[rx_path] = (cfo_tail * 5) >> 1;
++	phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;
++	phy_info->rx_mimo_signal_strength[rx_path] = phydm_pw_2_percent(pwr);
++	phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;
++	phy_info->rx_snr[rx_path] = rx_snr >> 1;
++}
++
++void phydm_common_phy_info_jgr3(s8 rx_power, u8 channel, boolean is_beamformed,
++				boolean is_mu_packet, u8 bandwidth,
++				u8 signal_quality, u8 rxsc,
++				struct phydm_phyinfo_struct *phy_info)
++{
++	phy_info->rx_power = rx_power; /* RSSI in dB */
++	phy_info->recv_signal_power = rx_power; /* RSSI in dB */
++	phy_info->channel = channel; /* @channel number */
++	phy_info->is_beamformed = is_beamformed; /* @apply BF */
++	phy_info->is_mu_packet = is_mu_packet; /* @MU packet */
++	phy_info->rxsc = rxsc;
++
++	phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_power); /*percentage */
++	phy_info->signal_quality = signal_quality; /* signal quality */
++	phy_info->band_width = bandwidth; /* @bandwidth */
++}
++#endif
++
++void phydm_get_physts_0_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
++			     struct phydm_perpkt_info_struct *pktinfo,
++			     struct phydm_phyinfo_struct *phy_info)
++{
++	/* type 0 is used for cck packet */
++	struct phy_sts_rpt_jgr3_type0 *phy_sts = NULL;
++	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
++	u8 sq = 0, i, rx_cnt = 0;
++	s8 rx_power[4], pwdb;
++	s8 rx_pwr_db_max = -120;
++
++	phy_sts = (struct phy_sts_rpt_jgr3_type0 *)phy_status_inf;
++
++	#if (RTL8197G_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8197G) {
++		if (dm->rx_ant_status == BB_PATH_B) {
++			phy_sts->pwdb_b = phy_sts->pwdb_a;
++			phy_sts->gain_b = phy_sts->gain_a;
++			phy_sts->pwdb_a = 0;
++			phy_sts->gain_a = 0;
++		}
++	}
++	#endif
++
++	rx_power[0] = phy_sts->pwdb_a;
++	rx_power[1] = phy_sts->pwdb_b;
++	rx_power[2] = phy_sts->pwdb_c;
++	rx_power[3] = phy_sts->pwdb_d;
++
++	#if (RTL8822C_SUPPORT || RTL8197G_SUPPORT)
++	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8197G)) {
++		struct phydm_physts *physts_table = &dm->dm_physts_table;
++		if (phy_sts->gain_a < physts_table->cck_gi_l_bnd)
++			rx_power[0] += ((physts_table->cck_gi_l_bnd -
++					phy_sts->gain_a) << 1);
++		else if (phy_sts->gain_a > physts_table->cck_gi_u_bnd)
++			rx_power[0] -= ((phy_sts->gain_a -
++					physts_table->cck_gi_u_bnd) << 1);
++
++		if (phy_sts->gain_b < physts_table->cck_gi_l_bnd)
++			rx_power[1] += ((physts_table->cck_gi_l_bnd -
++					phy_sts->gain_b) << 1);
++		else if (phy_sts->gain_b > physts_table->cck_gi_u_bnd)
++			rx_power[1] -= ((phy_sts->gain_b -
++					physts_table->cck_gi_u_bnd) << 1);
++	}
++	#endif
++
++	/* @Update per-path information */
++	for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
++		if ((dm->rx_ant_status & BIT(i)) == 0)
++			continue;
++
++		rx_cnt++; /* @check the number of the ant */
++
++		if (rx_cnt > dm->num_rf_path)
++			break;
++
++		if (pktinfo->is_to_self)
++			dm->ofdm_agc_idx[i] = rx_power[i];
++
++		/* @Setting the RX power: agc_idx -110 dBm*/
++		pwdb = rx_power[i] - 110;
++
++		phy_info->rx_pwr[i] = pwdb;
++		phy_info->rx_mimo_signal_strength[i] = phydm_pw_2_percent(pwdb);
++
++		/* search maximum pwdb */
++		if (pwdb > rx_pwr_db_max)
++			rx_pwr_db_max = pwdb;
++	}
++
++	/* @Calculate Signal Quality*/
++	if (phy_sts->signal_quality >= 64) {
++		sq = 0;
++	} else if (phy_sts->signal_quality <= 20) {
++		sq = 100;
++	} else {
++		/* @mapping to 2~99% */
++		sq = 64 - phy_sts->signal_quality;
++		sq = ((sq << 3) + sq) >> 2;
++	}
++
++	/* @Modify CCK PWDB if old AGC */
++	if (!dm->cck_new_agc) {
++		u8 lna_idx[4], vga_idx[4];
++
++		lna_idx[0] = ((phy_sts->lna_h_a << 3) | phy_sts->lna_l_a);
++		vga_idx[0] = phy_sts->vga_a;
++		lna_idx[1] = ((phy_sts->lna_h_b << 3) | phy_sts->lna_l_b);
++		vga_idx[1] = phy_sts->vga_b;
++		lna_idx[2] = ((phy_sts->lna_h_c << 3) | phy_sts->lna_l_c);
++		vga_idx[2] = phy_sts->vga_c;
++		lna_idx[3] = ((phy_sts->lna_h_d << 3) | phy_sts->lna_l_d);
++		vga_idx[3] = phy_sts->vga_d;
++	}
++
++	/*@CCK no STBC and LDPC*/
++	dbg_i->is_ldpc_pkt = false;
++	dbg_i->is_stbc_pkt = false;
++
++	/*cck channel has hw bug, [WLANBB-1429]*/
++	phy_info->channel = 0;
++	phy_info->rx_power = rx_pwr_db_max;
++	phy_info->recv_signal_power = rx_pwr_db_max;
++	phy_info->is_beamformed = false;
++	phy_info->is_mu_packet = false;
++	phy_info->rxsc = phy_sts->l_rxsc;
++	phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db_max);
++	phy_info->signal_quality = sq;
++	phy_info->band_width = CHANNEL_WIDTH_20;
++
++	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
++	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
++	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
++	dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
++	#endif
++}
++
++void phydm_get_physts_1_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
++				    struct phydm_perpkt_info_struct *pktinfo,
++				    struct phydm_phyinfo_struct *phy_info)
++{
++	struct phy_sts_rpt_jgr3_type1 *phy_sts = NULL;
++	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
++	s8 evm = 0;
++	u8 i;
++	s8 sq = 0;
++
++	phy_sts = (struct phy_sts_rpt_jgr3_type1 *)phy_status_inf;
++
++	/* SNR: S(8,1), EVM: S(8,1), CFO: S(8,7) */
++
++	for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
++		if ((dm->rx_ant_status & BIT(i)) == 0)
++			continue;
++
++		evm = phy_sts->rxevm[i];
++		evm = (evm == -128) ? 0 : ((0 - evm) >> 1);
++		sq = (evm >= 34) ? 100 : evm * 3; /* @Convert EVM to 0~100%*/
++
++		phy_info->rx_mimo_evm_dbm[i] = (u8)evm;
++		phy_info->rx_mimo_signal_quality[i] = sq;
++		phy_info->rx_snr[i] = phy_sts->rxsnr[i] >> 1;
++		/*@CFO(kHz) = CFO_tail*312.5(kHz)/2^7 ~= CFO tail * 5/2 (kHz)*/
++		phy_info->cfo_tail[i] = (phy_sts->cfo_tail[i] * 5) >> 1;
++		dbg_i->cfo_tail[i] = (phy_sts->cfo_tail[i] * 5) >> 1;
++	}
++	phy_info->signal_quality = phy_info->rx_mimo_signal_quality[0];
++
++	if (phy_sts->gid != 0 && phy_sts->gid != 63) {
++		phy_info->is_mu_packet = true;
++		dbg_i->num_qry_mu_pkt++;
++	} else {
++		phy_info->is_mu_packet = false;
++	}
++
++	phydm_parsing_cfo(dm, pktinfo, phy_sts->cfo_tail, pktinfo->rate_ss);
++
++#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
++	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
++	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
++	dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
++#endif
++}
++
++void phydm_get_physts_2_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
++				    struct phydm_perpkt_info_struct *pktinfo,
++				    struct phydm_phyinfo_struct *phy_info)
++{
++	/* type 2 & 3 is used for ofdm packet */
++	struct phy_sts_rpt_jgr3_type2_3 *phy_sts = NULL;
++}
++
++void phydm_get_physts_4_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
++				    struct phydm_perpkt_info_struct *pktinfo,
++				    struct phydm_phyinfo_struct *phy_info)
++{
++	struct phy_sts_rpt_jgr3_type4 *phy_sts = NULL;
++	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
++	s8 evm = 0;
++	u8 i;
++	s8 sq = 0;
++
++	phy_sts = (struct phy_sts_rpt_jgr3_type4 *)phy_status_inf;
++
++	/* SNR: S(8,1), EVM: S(8,1), CFO: S(8,7) */
++
++	for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
++		if ((dm->rx_ant_status & BIT(i)) == 0)
++			continue;
++
++		evm = phy_sts->rxevm[i];
++		evm = (evm == -128) ? 0 : ((0 - evm) >> 1);
++		sq = (evm >= 34) ? 100 : evm * 3; /* @Convert EVM to 0~100%*/
++
++		phy_info->rx_mimo_evm_dbm[i] = (u8)evm;
++		phy_info->rx_mimo_signal_quality[i] = sq;
++		phy_info->rx_snr[i] = phy_sts->rxsnr[i] >> 1;
++	}
++	phy_info->signal_quality = phy_info->rx_mimo_signal_quality[0];
++#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
++	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
++	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
++	dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
++#endif
++	odm_move_memory(dm, dbg_i->eigen_val, phy_sts->eigenvalue, 4);
++	dbg_i->condition_num_seg0 = phy_sts->avg_cond_num_0;
++}
++
++void phydm_get_physts_5_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
++				    struct phydm_perpkt_info_struct *pktinfo,
++				    struct phydm_phyinfo_struct *phy_info)
++{
++	struct phy_sts_rpt_jgr3_type5 *phy_sts = NULL;
++
++}
++
++void phydm_get_physts_ofdm_cmn_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
++				    struct phydm_perpkt_info_struct *pktinfo,
++				    struct phydm_phyinfo_struct *phy_info)
++{
++	struct phy_sts_rpt_jgr3_ofdm_cmn *phy_sts = NULL;
++	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
++	s8 rx_pwr_db_max = -120;
++	s8 pwdb = 0;
++	u8 i, rx_cnt = 0;
++
++	phy_sts = (struct phy_sts_rpt_jgr3_ofdm_cmn *)phy_status_inf;
++
++	/* Parsing Offset0 & 4*/
++	for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
++		if ((dm->rx_ant_status & BIT(i)) == 0)
++			continue;
++
++		rx_cnt++; /* @check the number of the ant */
++
++		pwdb = (s8)phy_sts->pwdb[i] - 110; /*@dB*/
++
++		if (pktinfo->is_to_self)
++			dm->ofdm_agc_idx[i] = phy_sts->pwdb[i];
++
++		/* search maximum pwdb */
++		if (pwdb > rx_pwr_db_max)
++			rx_pwr_db_max = pwdb;
++
++		phy_info->rx_pwr[i] = pwdb;
++		phy_info->rx_mimo_signal_strength[i] = phydm_pw_2_percent(pwdb);
++	}
++
++	phy_info->rx_count = (rx_cnt > 0) ? rx_cnt - 1 : 0; /*from 1~4 to 0~3 */
++	phy_info->rx_power = rx_pwr_db_max;
++	phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db_max);
++	phy_info->recv_signal_power = rx_pwr_db_max;
++	phy_info->channel = phy_sts->channel_lsb;
++	phy_info->is_beamformed = (boolean)phy_sts->beamformed;
++	phy_info->rxsc = (PHYDM_IS_LEGACY_RATE(pktinfo->data_rate)) ?
++			  phy_sts->l_rxsc : phy_sts->ht_rxsc;
++	phy_info->band_width = phydm_rxsc_2_bw(dm, phy_info->rxsc);
++
++	dbg_i->is_ldpc_pkt = phy_sts->ldpc;
++	dbg_i->is_stbc_pkt = phy_sts->stbc;
++	dbg_i->num_qry_bf_pkt += phy_sts->beamformed;
++}
++
++void phydm_process_dm_rssi_jgr3(struct dm_struct *dm,
++				struct phydm_phyinfo_struct *phy_info,
++				struct phydm_perpkt_info_struct *pktinfo)
++{
++	struct cmn_sta_info *sta = NULL;
++	struct rssi_info *rssi_t = NULL;
++	u8 rssi_tmp = 0;
++	u64 rssi_linear = 0;
++	s16 rssi_db = 0;
++	u8 i = 0;
++	u8 rx_count = 0;
++
++	#if (defined(PHYDM_CCK_RX_PATHDIV_SUPPORT))
++	struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
++	#endif
++
++	/*@[Step4]*/
++	if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
++		return;
++
++	sta = dm->phydm_sta_info[pktinfo->station_id];
++
++	if (!is_sta_active(sta))
++		return;
++
++	if (!pktinfo->is_packet_match_bssid) /*@data frame only*/
++		return;
++
++	if (!(pktinfo->is_packet_to_self) && !(pktinfo->is_packet_beacon))
++		return;
++
++	if (pktinfo->is_packet_beacon) {
++		dm->phy_dbg_info.num_qry_beacon_pkt++;
++		dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;
++	}
++
++	#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++	if (dm->support_ability & ODM_BB_ANT_DIV)
++		odm_process_rssi_for_ant_div(dm, phy_info, pktinfo);
++	#endif
++
++	#ifdef ODM_EVM_ENHANCE_ANTDIV
++	phydm_rx_rate_for_antdiv(dm, pktinfo);
++	#endif
++
++	#if (defined(CONFIG_PATH_DIVERSITY))
++	if (dm->support_ability & ODM_BB_PATH_DIV)
++		phydm_process_rssi_for_path_div(dm, phy_info, pktinfo);
++	#endif
++
++	#if (defined(PHYDM_CCK_RX_PATHDIV_SUPPORT))
++	if (cckrx_t->en_cck_rx_pathdiv)
++		phydm_process_rssi_for_cck_rx_pathdiv(dm, phy_info, pktinfo);
++	#endif
++
++	rssi_t = &sta->rssi_stat;
++
++	for (i = 0; i < dm->num_rf_path; i++) {
++		rssi_tmp = phy_info->rx_mimo_signal_strength[i];
++		if (rssi_tmp != 0) {
++			rx_count++;
++			rssi_linear += phydm_db_2_linear(rssi_tmp);
++		}
++	}
++	/* @Rounding and removing fractional bits */
++	rssi_linear = (rssi_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
++
++	switch (rx_count) {
++	case 2:
++		rssi_linear = DIVIDED_2(rssi_linear);
++		break;
++	case 3:
++		rssi_linear = DIVIDED_3(rssi_linear);
++		break;
++	case 4:
++		rssi_linear = DIVIDED_4(rssi_linear);
++		break;
++	}
++
++	rssi_db = (s16)odm_convert_to_db(rssi_linear);
++
++	if (rssi_t->rssi_acc == 0) {
++		rssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA);
++		rssi_t->rssi = (s8)(rssi_db);
++	} else {
++		rssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc, rssi_db, RSSI_MA);
++		rssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc, RSSI_MA);
++	}
++
++	if (pktinfo->is_cck_rate)
++		rssi_t->rssi_cck = (s8)rssi_db;
++	else
++		rssi_t->rssi_ofdm = (s8)rssi_db;
++}
++
++void phydm_rx_physts_jgr3(void *dm_void, u8 *phy_sts,
++			  struct phydm_perpkt_info_struct *pktinfo,
++			  struct phydm_phyinfo_struct *phy_info)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 phy_status_type = (*phy_sts & 0xf);
++
++	/*@[Step 2]*/
++	/*phydm_reset_phy_info_jgr3(dm, phy_info);*/ /* @Memory reset */
++
++	/* Phy status parsing */
++	switch (phy_status_type) {
++	case 0: /*@CCK*/
++		phydm_get_physts_0_jgr3(dm, phy_sts, pktinfo, phy_info);
++		break;
++	case 1:
++		phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info);
++		phydm_get_physts_1_others_jgr3(dm, phy_sts, pktinfo, phy_info);
++		break;
++	case 2:
++	case 3:
++		phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info);
++		phydm_get_physts_2_others_jgr3(dm, phy_sts, pktinfo, phy_info);
++		break;
++	case 4:
++		phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info);
++		phydm_get_physts_4_others_jgr3(dm, phy_sts, pktinfo, phy_info);
++	case 5:
++		phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info);
++		phydm_get_physts_5_others_jgr3(dm, phy_sts, pktinfo, phy_info);
++		break;
++	default:
++		break;
++	}
++
++#if 0
++	PHYDM_DBG(dm, DBG_PHY_STATUS, "RSSI: {%d, %d}\n",
++		  phy_info->rx_mimo_signal_strength[0],
++		  phy_info->rx_mimo_signal_strength[1]);
++	PHYDM_DBG(dm, DBG_PHY_STATUS, "rxdb: {%d, %d}\n",
++		  phy_info->rx_pwr[0], phy_info->rx_pwr[1]);
++	PHYDM_DBG(dm, DBG_PHY_STATUS, "EVM: {%d, %d}\n",
++		  phy_info->rx_mimo_evm_dbm[0], phy_info->rx_mimo_evm_dbm[1]);
++	PHYDM_DBG(dm, DBG_PHY_STATUS, "SQ: {%d, %d}\n",
++		  phy_info->rx_mimo_signal_quality[0],
++		  phy_info->rx_mimo_signal_quality[1]);
++	PHYDM_DBG(dm, DBG_PHY_STATUS, "SNR: {%d, %d}\n",
++		  phy_info->rx_snr[0], phy_info->rx_snr[1]);
++	PHYDM_DBG(dm, DBG_PHY_STATUS, "CFO: {%d, %d}\n",
++		  phy_info->cfo_tail[0], phy_info->cfo_tail[1]);
++	PHYDM_DBG(dm, DBG_PHY_STATUS,
++		  "rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n",
++		  phy_info->rx_pwdb_all, phy_info->rx_power,
++		  phy_info->recv_signal_power);
++	PHYDM_DBG(dm, DBG_PHY_STATUS, "signal_quality = %d\n",
++		  phy_info->signal_quality);
++	PHYDM_DBG(dm, DBG_PHY_STATUS,
++		  "is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n",
++		  phy_info->is_beamformed, phy_info->is_mu_packet,
++		  phy_info->rx_count);
++	PHYDM_DBG(dm, DBG_PHY_STATUS,
++		  "channel = %d, rxsc = %d, band_width = %d\n",
++		  phy_info->channel, phy_info->rxsc, phy_info->band_width);
++#endif
++
++	/*@[Step 1]*/
++	phydm_print_phystat_jgr3(dm, phy_sts, pktinfo, phy_info);
++}
++
++#endif
++
++#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
++/* @For 8822B only!! need to move to FW finally */
++/*@==============================================*/
++
++boolean
++phydm_query_is_mu_api(struct dm_struct *phydm, u8 ppdu_idx, u8 *p_data_rate,
++		      u8 *p_gid)
++{
++	u8 data_rate = 0, gid = 0;
++	boolean is_mu = false;
++
++	data_rate = phydm->phy_dbg_info.num_of_ppdu[ppdu_idx];
++	gid = phydm->phy_dbg_info.gid_num[ppdu_idx];
++
++	if (data_rate & BIT(7)) {
++		is_mu = true;
++		data_rate = data_rate & ~(BIT(7));
++	} else {
++		is_mu = false;
++	}
++
++	*p_data_rate = data_rate;
++	*p_gid = gid;
++
++	return is_mu;
++}
++
++void phydm_print_phy_sts_jgr2(struct dm_struct *dm, u8 *phy_status_inf,
++			      struct phydm_perpkt_info_struct *pktinfo,
++			      struct phydm_phyinfo_struct *phy_info)
++{
++	struct phy_sts_rpt_jgr2_type0 *rpt0 = NULL;
++	struct phy_sts_rpt_jgr2_type1 *rpt = NULL;
++	struct phy_sts_rpt_jgr2_type2 *rpt2 = NULL;
++	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
++	u8 phy_status_page_num = (*phy_status_inf & 0xf);
++	u32 phy_status[PHY_STATUS_JRGUAR2_DW_LEN] = {0};
++	u8 i;
++	u32 size = PHY_STATUS_JRGUAR2_DW_LEN << 2;
++
++	rpt0 = (struct phy_sts_rpt_jgr2_type0 *)phy_status_inf;
++	rpt = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf;
++	rpt2 = (struct phy_sts_rpt_jgr2_type2 *)phy_status_inf;
++
++	odm_move_memory(dm, phy_status, phy_status_inf, size);
++
++	if (!(dm->debug_components & DBG_PHY_STATUS))
++		return;
++
++	if (dbg->show_phy_sts_all_pkt == 0) {
++		if (!pktinfo->is_packet_match_bssid)
++			return;
++	}
++
++	dbg->show_phy_sts_cnt++;
++	#if 0
++	dbg_print("cnt=%d, max=%d\n",
++		  dbg->show_phy_sts_cnt, dbg->show_phy_sts_max_cnt);
++	#endif
++
++	if (dbg->show_phy_sts_max_cnt != SHOW_PHY_STATUS_UNLIMITED) {
++		if (dbg->show_phy_sts_cnt > dbg->show_phy_sts_max_cnt)
++			return;
++	}
++
++	pr_debug("Phy Status Rpt: OFDM_%d\n", phy_status_page_num);
++	pr_debug("StaID=%d, RxRate = 0x%x match_bssid=%d\n",
++		 pktinfo->station_id, pktinfo->data_rate,
++		 pktinfo->is_packet_match_bssid);
++
++	for (i = 0; i < PHY_STATUS_JRGUAR2_DW_LEN; i++)
++		pr_debug("Offset[%d:%d] = 0x%x\n",
++			 ((4 * i) + 3), (4 * i), phy_status[i]);
++
++	if (phy_status_page_num == 0) {
++		pr_debug("[0] TRSW=%d, MP_gain_idx=%d, pwdb=%d\n",
++			 rpt0->trsw, rpt0->gain, rpt0->pwdb);
++		pr_debug("[4] band=%d, CH=%d, agc_table = %d, rxsc = %d\n",
++			 rpt0->band, rpt0->channel,
++			 rpt0->agc_table, rpt0->rxsc);
++		pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\n",
++			 rpt0->antidx_d, rpt0->antidx_c, rpt0->antidx_b,
++			 rpt0->antidx_a, rpt0->length);
++		pr_debug("[12] lna_h=%d, bb_pwr=%d, lna_l=%d, vga=%d, sq=%d\n",
++			 rpt0->lna_h, rpt0->bb_power, rpt0->lna_l,
++			 rpt0->vga, rpt0->signal_quality);
++
++	} else if (phy_status_page_num == 1) {
++		pr_debug("[0] pwdb[D:A]={%d, %d, %d, %d}\n",
++			 rpt->pwdb[3], rpt->pwdb[2],
++			 rpt->pwdb[1], rpt->pwdb[0]);
++		pr_debug("[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht, l]={%d, %d}\n",
++			 rpt->beamformed, rpt->ldpc, rpt->stbc, rpt->gnt_bt,
++			 rpt->hw_antsw_occu, rpt->band, rpt->channel,
++			 rpt->ht_rxsc, rpt->l_rxsc);
++		pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\n",
++			 rpt->antidx_d, rpt->antidx_c, rpt->antidx_b,
++			 rpt->antidx_a, rpt->lsig_length);
++		pr_debug("[12] rf_mode=%d, NBI=%d, Intf_pos=%d, GID=%d, PAID=%d\n",
++			 rpt->rf_mode, rpt->nb_intf_flag,
++			 (rpt->intf_pos + (rpt->intf_pos_msb << 8)), rpt->gid,
++			 (rpt->paid + (rpt->paid_msb << 8)));
++		pr_debug("[16] EVM[D:A]={%d, %d, %d, %d}\n",
++			 rpt->rxevm[3], rpt->rxevm[2],
++			 rpt->rxevm[1], rpt->rxevm[0]);
++		pr_debug("[20] CFO[D:A]={%d, %d, %d, %d}\n",
++			 rpt->cfo_tail[3], rpt->cfo_tail[2], rpt->cfo_tail[1],
++			 rpt->cfo_tail[0]);
++		pr_debug("[24] SNR[D:A]={%d, %d, %d, %d}\n\n",
++			 rpt->rxsnr[3], rpt->rxsnr[2], rpt->rxsnr[1],
++			 rpt->rxsnr[0]);
++
++	} else if (phy_status_page_num == 2) {
++		pr_debug("[0] pwdb[D:A]={%d, %d, %d, %d}\n",
++			 rpt2->pwdb[3], rpt2->pwdb[2], rpt2->pwdb[1],
++			 rpt2->pwdb[0]);
++		pr_debug("[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht,l]={%d, %d}\n",
++			 rpt2->beamformed, rpt2->ldpc, rpt2->stbc, rpt2->gnt_bt,
++			 rpt2->hw_antsw_occu, rpt2->band, rpt2->channel,
++			 rpt2->ht_rxsc, rpt2->l_rxsc);
++		pr_debug("[8] AgcTab[D:A]={%d, %d, %d, %d}, cnt_pw2cca=%d, shift_l_map=%d\n",
++			 rpt2->agc_table_d, rpt2->agc_table_c,
++			 rpt2->agc_table_b, rpt2->agc_table_a,
++			 rpt2->cnt_pw2cca, rpt2->shift_l_map);
++		pr_debug("[12] (TRSW|Gain)[D:A]={%d %d, %d %d, %d %d, %d %d}, cnt_cca2agc_rdy=%d\n",
++			 rpt2->trsw_d, rpt2->gain_d, rpt2->trsw_c, rpt2->gain_c,
++			 rpt2->trsw_b, rpt2->gain_b, rpt2->trsw_a,
++			 rpt2->gain_a, rpt2->cnt_cca2agc_rdy);
++		pr_debug("[16] AAGC step[D:A]={%d, %d, %d, %d} HT AAGC gain[D:A]={%d, %d, %d, %d}\n",
++			 rpt2->aagc_step_d, rpt2->aagc_step_c,
++			 rpt2->aagc_step_b, rpt2->aagc_step_a,
++			 rpt2->ht_aagc_gain[3], rpt2->ht_aagc_gain[2],
++			 rpt2->ht_aagc_gain[1], rpt2->ht_aagc_gain[0]);
++		pr_debug("[20] DAGC gain[D:A]={%d, %d, %d, %d}\n",
++			 rpt2->dagc_gain[3],
++			 rpt2->dagc_gain[2], rpt2->dagc_gain[1],
++			 rpt2->dagc_gain[0]);
++		pr_debug("[24] syn_cnt: %d, Cnt=%d\n\n",
++			 rpt2->syn_count, rpt2->counter);
++	}
++}
++
++void phydm_set_per_path_phy_info(u8 rx_path, s8 pwr, s8 rx_evm, s8 cfo_tail,
++				 s8 rx_snr, u8 ant_idx,
++				 struct phydm_phyinfo_struct *phy_info)
++{
++	u8 evm_dbm = 0;
++	u8 evm_percentage = 0;
++
++	/* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */
++
++	if (rx_evm < 0) {
++		/* @Calculate EVM in dBm */
++		evm_dbm = ((u8)(0 - rx_evm) >> 1);
++
++		if (evm_dbm == 64)
++			evm_dbm = 0; /*@if 1SS rate, evm_dbm [2nd stream] =64*/
++
++		if (evm_dbm != 0) {
++			/* @Convert EVM to 0%~100% percentage */
++			if (evm_dbm >= 34)
++				evm_percentage = 100;
++			else
++				evm_percentage = (evm_dbm << 1) + (evm_dbm);
++		}
++	}
++
++	phy_info->rx_pwr[rx_path] = pwr;
++
++	/*@CFO(kHz) = CFO_tail * 312.5(kHz) / 2^7 ~= CFO tail * 5/2 (kHz)*/
++	phy_info->cfo_tail[rx_path] = (cfo_tail * 5) >> 1;
++	phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;
++	phy_info->rx_mimo_signal_strength[rx_path] = phydm_pw_2_percent(pwr);
++	phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;
++	phy_info->rx_snr[rx_path] = rx_snr >> 1;
++	phy_info->ant_idx[rx_path] = ant_idx;
++
++#if 0
++	if (!pktinfo->is_packet_match_bssid)
++		return;
++
++	dbg_print("path (%d)--------\n", rx_path);
++	dbg_print("rx_pwr = %d, Signal strength = %d\n",
++		  phy_info->rx_pwr[rx_path],
++		  phy_info->rx_mimo_signal_strength[rx_path]);
++	dbg_print("evm_dbm = %d, Signal quality = %d\n",
++		  phy_info->rx_mimo_evm_dbm[rx_path],
++		  phy_info->rx_mimo_signal_quality[rx_path]);
++	dbg_print("CFO = %d, SNR = %d\n",
++		  phy_info->cfo_tail[rx_path], phy_info->rx_snr[rx_path]);
++
++#endif
++}
++
++void phydm_set_common_phy_info(s8 rx_power, u8 channel, boolean is_beamformed,
++			       boolean is_mu_packet, u8 bandwidth,
++			       u8 signal_quality, u8 rxsc,
++			       struct phydm_phyinfo_struct *phy_info)
++{
++	phy_info->rx_power = rx_power; /* RSSI in dB */
++	phy_info->recv_signal_power = rx_power; /* RSSI in dB */
++	phy_info->channel = channel; /* @channel number */
++	phy_info->is_beamformed = is_beamformed; /* @apply BF */
++	phy_info->is_mu_packet = is_mu_packet; /* @MU packet */
++	phy_info->rxsc = rxsc;
++
++	/* RSSI in percentage */
++	phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_power);
++	phy_info->signal_quality = signal_quality; /* signal quality */
++	phy_info->band_width = bandwidth; /* @bandwidth */
++
++#if 0
++	if (!pktinfo->is_packet_match_bssid)
++		return;
++
++	dbg_print("rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n",
++		  phy_info->rx_pwdb_all, phy_info->rx_power,
++		  phy_info->recv_signal_power);
++	dbg_print("signal_quality = %d\n", phy_info->signal_quality);
++	dbg_print("is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n",
++		  phy_info->is_beamformed, phy_info->is_mu_packet,
++		  phy_info->rx_count + 1);
++	dbg_print("channel = %d, rxsc = %d, band_width = %d\n", channel,
++		  rxsc, bandwidth);
++
++#endif
++}
++
++void phydm_get_phy_sts_type0(struct dm_struct *dm, u8 *phy_status_inf,
++			     struct phydm_perpkt_info_struct *pktinfo,
++			     struct phydm_phyinfo_struct *phy_info)
++{
++	/* type 0 is used for cck packet */
++	struct phy_sts_rpt_jgr2_type0 *phy_sts = NULL;
++	u8 sq = 0;
++	s8 rx_pow = 0;
++	u8 lna_idx = 0, vga_idx = 0;
++	u8 ant_idx;
++
++	phy_sts = (struct phy_sts_rpt_jgr2_type0 *)phy_status_inf;
++	rx_pow = phy_sts->pwdb - 110;
++
++	/* Fill in per-path antenna index */
++	ant_idx = phy_sts->antidx_a;
++
++	if (dm->support_ic_type & ODM_RTL8723D) {
++		#if (RTL8723D_SUPPORT)
++		rx_pow = phy_sts->pwdb - 97;
++		#endif
++	}
++	#if (RTL8821C_SUPPORT)
++	else if (dm->support_ic_type & ODM_RTL8821C) {
++		if (phy_sts->pwdb >= -57)
++			rx_pow = phy_sts->pwdb - 100;
++		else
++			rx_pow = phy_sts->pwdb - 102;
++	}
++	#endif
++
++	if (pktinfo->is_to_self) {
++		dm->ofdm_agc_idx[0] = phy_sts->pwdb;
++		dm->ofdm_agc_idx[1] = 0;
++		dm->ofdm_agc_idx[2] = 0;
++		dm->ofdm_agc_idx[3] = 0;
++	}
++
++	/* @Calculate Signal Quality*/
++	if (phy_sts->signal_quality >= 64) {
++		sq = 0;
++	} else if (phy_sts->signal_quality <= 20) {
++		sq = 100;
++	} else {
++		/* @mapping to 2~99% */
++		sq = 64 - phy_sts->signal_quality;
++		sq = ((sq << 3) + sq) >> 2;
++	}
++
++	/* @Get RSSI for old CCK AGC */
++	if (!dm->cck_new_agc) {
++		vga_idx = phy_sts->vga;
++
++		if (dm->support_ic_type & ODM_RTL8197F) {
++			/*@3bit LNA*/
++			lna_idx = phy_sts->lna_l;
++		} else {
++			/*@4bit LNA*/
++			lna_idx = (phy_sts->lna_h << 3) | phy_sts->lna_l;
++		}
++		rx_pow = phydm_get_cck_rssi(dm, lna_idx, vga_idx);
++	}
++
++	/* @Confirm CCK RSSI */
++	#if (RTL8197F_SUPPORT)
++	if (dm->support_ic_type & ODM_RTL8197F) {
++		u8 bb_pwr_th_l = 5; /* round( 31*0.15 ) */
++		u8 bb_pwr_th_h = 27; /* round( 31*0.85 ) */
++
++		if (phy_sts->bb_power < bb_pwr_th_l ||
++		    phy_sts->bb_power > bb_pwr_th_h)
++			rx_pow = 0; /* @Error RSSI for CCK ; set 100*/
++	}
++	#endif
++
++	/*@CCK no STBC and LDPC*/
++	dm->phy_dbg_info.is_ldpc_pkt = false;
++	dm->phy_dbg_info.is_stbc_pkt = false;
++
++	/* Update Common information */
++	phydm_set_common_phy_info(rx_pow, phy_sts->channel, false,
++				  false, CHANNEL_WIDTH_20, sq,
++				  phy_sts->rxsc, phy_info);
++	/* Update CCK pwdb */
++	phydm_set_per_path_phy_info(RF_PATH_A, rx_pow, 0, 0, 0, ant_idx,
++				    phy_info);
++
++	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
++	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
++	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
++	dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
++	#endif
++}
++
++void phydm_get_phy_sts_type1(struct dm_struct *dm, u8 *phy_status_inf,
++			     struct phydm_perpkt_info_struct *pktinfo,
++			     struct phydm_phyinfo_struct *phy_info)
++{
++	/* type 1 is used for ofdm packet */
++	struct phy_sts_rpt_jgr2_type1 *phy_sts = NULL;
++	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
++	s8 rx_pwr_db = -120;
++	s8 rx_pwr = 0;
++	u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;
++	boolean is_mu;
++	u8 ant_idx[4];
++
++	phy_sts = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf;
++
++	/* Fill in per-path antenna index */
++	ant_idx[0] = phy_sts->antidx_a;
++	ant_idx[1] = phy_sts->antidx_b;
++	ant_idx[2] = phy_sts->antidx_c;
++	ant_idx[3] = phy_sts->antidx_d;
++
++	/* Update per-path information */
++	for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
++		if (!(dm->rx_ant_status & BIT(i)))
++			continue;
++		rx_count++;
++
++		if (rx_count > dm->num_rf_path)
++			break;
++
++		/* Update per-path information
++		 * (RSSI_dB RSSI_percentage EVM SNR CFO sq)
++		 */
++		/* @EVM report is reported by stream, not path */
++		rx_pwr = phy_sts->pwdb[i] - 110; /* per-path pwdb(dB)*/
++
++		if (pktinfo->is_to_self)
++			dm->ofdm_agc_idx[i] = phy_sts->pwdb[i];
++
++		phydm_set_per_path_phy_info(i, rx_pwr,
++					    phy_sts->rxevm[rx_count - 1],
++					    phy_sts->cfo_tail[i],
++					    phy_sts->rxsnr[i],
++					    ant_idx[i], phy_info);
++		/* search maximum pwdb */
++		if (rx_pwr > rx_pwr_db)
++			rx_pwr_db = rx_pwr;
++	}
++
++	/* @mapping RX counter from 1~4 to 0~3 */
++	if (rx_count > 0)
++		phy_info->rx_count = rx_count - 1;
++
++	/* @Check if MU packet or not */
++	if (phy_sts->gid != 0 && phy_sts->gid != 63) {
++		is_mu = true;
++		dbg_i->num_qry_mu_pkt++;
++	} else {
++		is_mu = false;
++	}
++
++	/* @count BF packet */
++	dbg_i->num_qry_bf_pkt = dbg_i->num_qry_bf_pkt + phy_sts->beamformed;
++
++	/*STBC or LDPC pkt*/
++	dbg_i->is_ldpc_pkt = phy_sts->ldpc;
++	dbg_i->is_stbc_pkt = phy_sts->stbc;
++
++	/* @Check sub-channel */
++	if (pktinfo->data_rate > ODM_RATE11M &&
++	    pktinfo->data_rate < ODM_RATEMCS0)
++		rxsc = phy_sts->l_rxsc;
++	else
++		rxsc = phy_sts->ht_rxsc;
++
++	/* @Check RX bandwidth */
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		if (rxsc >= 1 && rxsc <= 8)
++			bw = CHANNEL_WIDTH_20;
++		else if ((rxsc >= 9) && (rxsc <= 12))
++			bw = CHANNEL_WIDTH_40;
++		else if (rxsc >= 13)
++			bw = CHANNEL_WIDTH_80;
++		else
++			bw = phy_sts->rf_mode;
++
++	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		if (phy_sts->rf_mode == 0)
++			bw = CHANNEL_WIDTH_20;
++		else if ((rxsc == 1) || (rxsc == 2))
++			bw = CHANNEL_WIDTH_20;
++		else
++			bw = CHANNEL_WIDTH_40;
++	}
++
++	/* Update packet information */
++	phydm_set_common_phy_info(rx_pwr_db, phy_sts->channel,
++				  (boolean)phy_sts->beamformed, is_mu, bw,
++				  phy_info->rx_mimo_signal_quality[0],
++				  rxsc, phy_info);
++
++	phydm_parsing_cfo(dm, pktinfo, phy_sts->cfo_tail, pktinfo->rate_ss);
++	#ifdef PHYDM_LNA_SAT_CHK_TYPE2
++	phydm_parsing_snr(dm, pktinfo, phy_sts->rxsnr);
++	#endif
++
++	#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
++	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
++	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
++	dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
++	#endif
++}
++
++void phydm_get_phy_sts_type2(struct dm_struct *dm, u8 *phy_status_inf,
++			     struct phydm_perpkt_info_struct *pktinfo,
++			     struct phydm_phyinfo_struct *phy_info)
++{
++	struct phy_sts_rpt_jgr2_type2 *phy_sts = NULL;
++	s8 rx_pwr_db_max = -120;
++	s8 rx_pwr = 0;
++	u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;
++
++	phy_sts = (struct phy_sts_rpt_jgr2_type2 *)phy_status_inf;
++
++	for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
++		if (!(dm->rx_ant_status & BIT(i)))
++			continue;
++		rx_count++;
++
++		if (rx_count > dm->num_rf_path)
++			break;
++
++		/* Update per-path information*/
++		/* RSSI_dB, RSSI_percentage, EVM, SNR, CFO, sq */
++		#if (RTL8197F_SUPPORT)
++		if ((dm->support_ic_type & ODM_RTL8197F) &&
++		    phy_sts->pwdb[i] == 0x7f) { /*@97f workaround*/
++
++			if (i == RF_PATH_A) {
++				rx_pwr = (phy_sts->gain_a) << 1;
++				rx_pwr = rx_pwr - 110;
++			} else if (i == RF_PATH_B) {
++				rx_pwr = (phy_sts->gain_b) << 1;
++				rx_pwr = rx_pwr - 110;
++			} else {
++				rx_pwr = 0;
++			}
++		} else
++		#endif
++			rx_pwr = phy_sts->pwdb[i] - 110; /*@dBm*/
++
++		phydm_set_per_path_phy_info(i, rx_pwr, 0, 0, 0, 0, phy_info);
++
++		if (rx_pwr > rx_pwr_db_max) /* search max pwdb */
++			rx_pwr_db_max = rx_pwr;
++	}
++
++	/* @mapping RX counter from 1~4 to 0~3 */
++	if (rx_count > 0)
++		phy_info->rx_count = rx_count - 1;
++
++	/* @Check RX sub-channel */
++	if (pktinfo->data_rate > ODM_RATE11M &&
++	    pktinfo->data_rate < ODM_RATEMCS0)
++		rxsc = phy_sts->l_rxsc;
++	else
++		rxsc = phy_sts->ht_rxsc;
++
++	/*STBC or LDPC pkt*/
++	dm->phy_dbg_info.is_ldpc_pkt = phy_sts->ldpc;
++	dm->phy_dbg_info.is_stbc_pkt = phy_sts->stbc;
++
++	/* @Check RX bandwidth */
++	/* @BW information of sc=0 is useless,
++	 *because there is no information of RF mode
++	 */
++	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		if (rxsc >= 1 && rxsc <= 8)
++			bw = CHANNEL_WIDTH_20;
++		else if ((rxsc >= 9) && (rxsc <= 12))
++			bw = CHANNEL_WIDTH_40;
++		else if (rxsc >= 13)
++			bw = CHANNEL_WIDTH_80;
++
++	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		if (rxsc == 3)
++			bw = CHANNEL_WIDTH_40;
++		else if ((rxsc == 1) || (rxsc == 2))
++			bw = CHANNEL_WIDTH_20;
++	}
++
++	/* Update packet information */
++	phydm_set_common_phy_info(rx_pwr_db_max, phy_sts->channel,
++				  (boolean)phy_sts->beamformed,
++				  false, bw, 0, rxsc, phy_info);
++}
++
++void phydm_process_rssi_for_dm_2nd_type(struct dm_struct *dm,
++					struct phydm_phyinfo_struct *phy_info,
++					struct phydm_perpkt_info_struct *pktinfo
++					)
++{
++	struct cmn_sta_info *sta = NULL;
++	struct rssi_info *rssi_t = NULL;
++	u8 rssi_tmp = 0;
++	u64 rssi_linear = 0;
++	s16 rssi_db = 0;
++	u8 i = 0;
++
++	if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
++		return;
++
++	sta = dm->phydm_sta_info[pktinfo->station_id];
++
++	if (!is_sta_active(sta))
++		return;
++
++	if (!pktinfo->is_packet_match_bssid) /*@data frame only*/
++		return;
++
++#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++	if (dm->support_ability & ODM_BB_ANT_DIV)
++		odm_process_rssi_for_ant_div(dm, phy_info, pktinfo);
++#endif
++
++#if (defined(CONFIG_PATH_DIVERSITY))
++	if (dm->support_ability & ODM_BB_PATH_DIV)
++		phydm_process_rssi_for_path_div(dm, phy_info, pktinfo);
++#endif
++
++#ifdef CONFIG_ADAPTIVE_SOML
++	phydm_rx_qam_for_soml(dm, pktinfo);
++	phydm_rx_rate_for_soml(dm, pktinfo);
++#endif
++
++	if (!(pktinfo->is_packet_to_self) && !(pktinfo->is_packet_beacon))
++		return;
++
++	if (pktinfo->is_packet_beacon) {
++		dm->phy_dbg_info.num_qry_beacon_pkt++;
++		dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;
++	}
++
++	rssi_t = &sta->rssi_stat;
++
++	for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
++		rssi_tmp = phy_info->rx_mimo_signal_strength[i];
++		if (rssi_tmp != 0)
++			rssi_linear += phydm_db_2_linear(rssi_tmp);
++	}
++	/* @Rounding and removing fractional bits */
++	rssi_linear = (rssi_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
++
++	switch (phy_info->rx_count + 1) {
++	case 2:
++		rssi_linear = DIVIDED_2(rssi_linear);
++		break;
++	case 3:
++		rssi_linear = DIVIDED_3(rssi_linear);
++		break;
++	case 4:
++		rssi_linear = DIVIDED_4(rssi_linear);
++		break;
++	}
++
++	rssi_db = (s16)odm_convert_to_db(rssi_linear);
++
++	if (rssi_t->rssi_acc == 0) {
++		rssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA);
++		rssi_t->rssi = (s8)(rssi_db);
++	} else {
++		rssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc, rssi_db, RSSI_MA);
++		rssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc, RSSI_MA);
++	}
++
++	if (pktinfo->is_cck_rate)
++		rssi_t->rssi_cck = (s8)rssi_db;
++	else
++		rssi_t->rssi_ofdm = (s8)rssi_db;
++}
++
++void phydm_rx_physts_2nd_type(void *dm_void, u8 *phy_sts,
++			      struct phydm_perpkt_info_struct *pktinfo,
++			      struct phydm_phyinfo_struct *phy_info)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 page = (*phy_sts & 0xf);
++
++	/* Phy status parsing */
++	switch (page) {
++	case 0: /*@CCK*/
++		phydm_get_phy_sts_type0(dm, phy_sts, pktinfo, phy_info);
++		break;
++	case 1:
++		phydm_get_phy_sts_type1(dm, phy_sts, pktinfo, phy_info);
++		break;
++	case 2:
++		phydm_get_phy_sts_type2(dm, phy_sts, pktinfo, phy_info);
++		break;
++	default:
++		break;
++	}
++
++#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT)
++	if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B))
++		phydm_print_phy_sts_jgr2(dm, phy_sts, pktinfo, phy_info);
++#endif
++}
++
++/*@==============================================*/
++#endif
++
++boolean odm_phy_status_query(struct dm_struct *dm,
++			     struct phydm_phyinfo_struct *phy_info,
++			     u8 *phy_sts,
++			     struct phydm_perpkt_info_struct *pktinfo)
++{
++#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
++	struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct;
++	boolean auto_swch_en = dm->pkt_proc_struct.physts_auto_swch_en;
++#endif
++	u8 rate = pktinfo->data_rate;
++	u8 page = (*phy_sts & 0xf);
++
++	pktinfo->is_cck_rate = PHYDM_IS_CCK_RATE(rate);
++	pktinfo->rate_ss = phydm_rate_to_num_ss(dm, rate);
++	dm->rate_ss = pktinfo->rate_ss; /*@For AP EVM SW antenna diversity use*/
++
++	if (pktinfo->is_cck_rate)
++		dm->phy_dbg_info.num_qry_phy_status_cck++;
++	else
++		dm->phy_dbg_info.num_qry_phy_status_ofdm++;
++
++	/*Reset phy_info*/
++	phydm_reset_phy_info(dm, phy_info);
++
++	if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) {
++		#ifdef PHYSTS_3RD_TYPE_SUPPORT
++		#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
++		if (phydm_physts_auto_switch_jgr3(dm, phy_sts, pktinfo)) {
++			PHYDM_DBG(dm, DBG_PHY_STATUS, "SKIP parsing\n");
++			phy_info->physts_rpt_valid = false;
++			return false;
++		}
++		#endif
++		phydm_rx_physts_jgr3(dm, phy_sts, pktinfo, phy_info);
++		phydm_process_dm_rssi_jgr3(dm, phy_info, pktinfo);
++		#endif
++	} else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) {
++		#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
++		phydm_rx_physts_2nd_type(dm, phy_sts, pktinfo, phy_info);
++		phydm_process_rssi_for_dm_2nd_type(dm, phy_info, pktinfo);
++		#endif
++	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		#if ODM_IC_11AC_SERIES_SUPPORT
++		phydm_rx_physts_1st_type(dm, phy_info, phy_sts, pktinfo);
++		phydm_process_rssi_for_dm(dm, phy_info, pktinfo);
++		#endif
++	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		#if ODM_IC_11N_SERIES_SUPPORT
++		phydm_phy_sts_n_parsing(dm, phy_info, phy_sts, pktinfo);
++		phydm_process_rssi_for_dm(dm, phy_info, pktinfo);
++		#endif
++	}
++	phy_info->signal_strength = phy_info->rx_pwdb_all;
++	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	phydm_process_signal_strength(dm, phy_info, pktinfo);
++	#endif
++
++	/*For basic debug message*/
++	if (pktinfo->is_packet_match_bssid || *dm->mp_mode) {
++		dm->curr_station_id = pktinfo->station_id;
++		dm->rx_rate = rate;
++		dm->rssi_a = phy_info->rx_mimo_signal_strength[RF_PATH_A];
++		dm->rssi_b = phy_info->rx_mimo_signal_strength[RF_PATH_B];
++		dm->rssi_c = phy_info->rx_mimo_signal_strength[RF_PATH_C];
++		dm->rssi_d = phy_info->rx_mimo_signal_strength[RF_PATH_D];
++
++		if (rate >= ODM_RATE6M && rate <= ODM_RATE54M)
++			dm->rxsc_l = (s8)phy_info->rxsc;
++		else if (phy_info->band_width == CHANNEL_WIDTH_20)
++			dm->rxsc_20 = (s8)phy_info->rxsc;
++		else if (phy_info->band_width == CHANNEL_WIDTH_40)
++			dm->rxsc_40 = (s8)phy_info->rxsc;
++		else if (phy_info->band_width == CHANNEL_WIDTH_80)
++			dm->rxsc_80 = (s8)phy_info->rxsc;
++
++		#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
++		if (auto_swch_en && page == 4 && pktinfo->rate_ss > 1)
++			phydm_avg_condi_num(dm, phy_info, pktinfo);
++
++		if (!auto_swch_en ||
++		    (pkt_proc->is_1st_mpdu || PHYDM_IS_LEGACY_RATE(rate)))
++		#endif
++		{
++			phydm_avg_rssi_evm_snr(dm, phy_info, pktinfo);
++			phydm_rx_statistic_cal(dm, phy_info, phy_sts, pktinfo);
++		}
++	}
++
++	phy_info->physts_rpt_valid = true;
++	return true;
++}
++
++void phydm_rx_phy_status_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
++
++	dbg->show_phy_sts_all_pkt = 0;
++	dbg->show_phy_sts_max_cnt = 1;
++	dbg->show_phy_sts_cnt = 0;
++
++	phydm_avg_phystatus_init(dm);
++
++	#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
++	dm->pkt_proc_struct.physts_auto_swch_en = false;
++	#endif
++}
++
++void phydm_physts_dbg(void *dm_void, char input[][16], u32 *_used,
++		      char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	char help[] = "-h";
++	boolean enable;
++	u32 var[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 i = 0;
++
++	for (i = 0; i < 3; i++) {
++		if (input[i + 1])
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]);
++	}
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Page Auto Switching: swh {en} {bitmap(hex)}\n");
++	} else if ((strcmp(input[1], "swh") == 0)) {
++		#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
++		PHYDM_SSCANF(input[3], DCMD_HEX, &var[2]);
++		enable = (boolean)var[1];
++		phydm_physts_auto_switch_jgr3_set(dm, enable, (u8)var[2]);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Page Auto Switching: en=%d, bitmap=0x%x\n",
++			 enable, var[2]);
++		#endif
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_phystatus.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_phystatus.h
+new file mode 100644
+index 000000000..6137084d4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_phystatus.h
+@@ -0,0 +1,1178 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_PHYSTATUS_H__
++#define __PHYDM_PHYSTATUS_H__
++
++/* 2019.09.26 force jgr3 cck channel = 0 due to hw bug*/
++#define PHYSTS_VERSION "1.1"
++
++/*@--------------------------Define ------------------------------------------*/
++#define CCK_RSSI_INIT_COUNT 5
++
++#define RA_RSSI_STATE_INIT 0
++#define RA_RSSI_STATE_SEND 1
++#define RA_RSSI_STATE_HOLD 2
++
++#if defined(DM_ODM_CE_MAC80211)
++#define CFO_HW_RPT_2_KHZ(val) ({		\
++	s32 cfo_hw_rpt_2_khz_tmp = (val);	\
++	(cfo_hw_rpt_2_khz_tmp << 1) + (cfo_hw_rpt_2_khz_tmp >> 1);	\
++	})
++#else
++#define CFO_HW_RPT_2_KHZ(val) ((val << 1) + (val >> 1))
++#endif
++
++/* @(X* 312.5 Khz)>>7 ~=  X*2.5 Khz= (X<<1 + X>>1)Khz  */
++
++#define IGI_2_RSSI(igi) (igi - 10)
++
++#define PHY_STATUS_JRGUAR2_DW_LEN 7 /* @7*4 = 28 Byte */
++#define PHY_STATUS_JRGUAR3_DW_LEN 7 /* @7*4 = 28 Byte */
++#define SHOW_PHY_STATUS_UNLIMITED 0
++#define RSSI_MA 4 /*moving average factor for RSSI: 2^4=16 */
++
++#define PHYSTS_PATH_NUM 4
++
++/*@************************************************************
++ * structure and define
++ ************************************************************/
++
++__PACK struct phy_rx_agc_info {
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 gain : 7, trsw : 1;
++#else
++	u8 trsw : 1, gain : 7;
++#endif
++};
++
++__PACK struct phy_status_rpt_8192cd {
++	struct phy_rx_agc_info path_agc[2];
++	u8	ch_corr[2];
++	u8	cck_sig_qual_ofdm_pwdb_all;
++	u8	cck_agc_rpt_ofdm_cfosho_a;
++	u8	cck_rpt_b_ofdm_cfosho_b;
++	u8	rsvd_1;/*@ch_corr_msb;*/
++	u8	noise_power_db_msb;
++	s8	path_cfotail[2];
++	u8	pcts_mask[2];
++	s8	stream_rxevm[2];
++	u8	path_rxsnr[2];
++	u8	noise_power_db_lsb;
++	u8	rsvd_2[3];
++	u8	stream_csi[2];
++	u8	stream_target_csi[2];
++	s8	sig_evm;
++	u8	rsvd_3;
++
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8	antsel_rx_keep_2: 1;	/*@ex_intf_flg:1;*/
++	u8	sgi_en: 1;
++	u8	rxsc: 2;
++	u8	idle_long: 1;
++	u8	r_ant_train_en: 1;
++	u8	ant_sel_b: 1;
++	u8	ant_sel: 1;
++#else	/*@_BIG_ENDIAN_	*/
++	u8	ant_sel: 1;
++	u8	ant_sel_b: 1;
++	u8	r_ant_train_en: 1;
++	u8	idle_long: 1;
++	u8	rxsc: 2;
++	u8	sgi_en: 1;
++	u8	antsel_rx_keep_2: 1;/*@ex_intf_flg:1;*/
++#endif
++};
++
++struct phy_status_rpt_8812 {
++	/*	@DWORD 0*/
++	u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/
++	u8 chl_num_LSB; /*@channel number[7:0]*/
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 chl_num_MSB : 2; /*@channel number[9:8]*/
++	u8 sub_chnl : 4; /*sub-channel location[3:0]*/
++	u8 r_RFMOD : 2; /*RF mode[1:0]*/
++#else /*@_BIG_ENDIAN_	*/
++	u8 r_RFMOD : 2;
++	u8 sub_chnl : 4;
++	u8 chl_num_MSB : 2;
++#endif
++
++	/*	@DWORD 1*/
++	u8 pwdb_all; /*@CCK signal quality / OFDM pwdb all*/
++	s8 cfosho[2]; /*@CCK AGC report and CCK_BB_Power*/
++		      /*OFDM path-A and path-B short CFO*/
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 resvd_0 : 6;
++	u8 bt_RF_ch_MSB : 2; /*@8812A:2'b0  8814A: bt rf channel keep[7:6]*/
++#else /*@_BIG_ENDIAN_*/
++	u8 bt_RF_ch_MSB : 2;
++	u8 resvd_0 : 6;
++#endif
++
++/*	@DWORD 2*/
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 ant_div_sw_a : 1; /*@8812A: ant_div_sw_a    8814A: 1'b0*/
++	u8 ant_div_sw_b : 1; /*@8812A: ant_div_sw_b    8814A: 1'b0*/
++	u8 bt_RF_ch_LSB : 6; /*@8812A: 6'b0     8814A: bt rf channel keep[5:0]*/
++#else /*@_BIG_ENDIAN_	*/
++	u8 bt_RF_ch_LSB : 6;
++	u8 ant_div_sw_b : 1;
++	u8 ant_div_sw_a : 1;
++#endif
++	s8 cfotail[2]; /*@DW2 byte 1 DW2 byte 2	path-A and path-B CFO tail*/
++	u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/
++	u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/
++
++	/*	@DWORD 3*/
++	s8 rxevm[2]; /*@DW3 byte 1 DW3 byte 2	stream 1 and stream 2 RX EVM*/
++	s8 rxsnr[2]; /*@DW3 byte 3 DW4 byte 0	path-A and path-B RX SNR*/
++
++	/*	@DWORD 4*/
++	u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 PCTS_MSK_RPT_3 : 6; /*PCTS mask report[29:24]*/
++	u8 pcts_rpt_valid : 1; /*pcts_rpt_valid*/
++	u8 resvd_1 : 1; /*@1'b0*/
++#else /*@_BIG_ENDIAN_*/
++	u8 resvd_1 : 1;
++	u8 pcts_rpt_valid : 1;
++	u8 PCTS_MSK_RPT_3 : 6;
++#endif
++	s8 rxevm_cd[2]; /*@8812A: 16'b0*/
++			/*@8814A: stream 3 and stream 4 RX EVM*/
++	/*	@DWORD 5*/
++	u8 csi_current[2]; /*@8812A: stream 1 and 2 CSI*/
++			   /*@8814A:  path-C and path-D RX SNR*/
++	u8 gain_trsw_cd[2]; /*path-C and path-D {TRSW, gain[6:0] }*/
++
++	/*	@DWORD 6*/
++	s8 sigevm; /*signal field EVM*/
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 antidx_antc : 3;	/*@8812A: 3'b0	8814A: antidx_antc[2:0]*/
++	u8 antidx_antd : 3;	/*@8812A: 3'b0	8814A: antidx_antd[2:0]*/
++	u8 dpdt_ctrl_keep : 1;	/*@8812A: 1'b0	8814A: dpdt_ctrl_keep*/
++	u8 GNT_BT_keep : 1;	/*@8812A: 1'b0	8814A: GNT_BT_keep*/
++#else /*@_BIG_ENDIAN_*/
++	u8 GNT_BT_keep : 1;
++	u8 dpdt_ctrl_keep : 1;
++	u8 antidx_antd : 3;
++	u8 antidx_antc : 3;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 antidx_anta : 3; /*@antidx_anta[2:0]*/
++	u8 antidx_antb : 3; /*@antidx_antb[2:0]*/
++	u8 hw_antsw_occur : 2; /*@1'b0*/
++#else /*@_BIG_ENDIAN_*/
++	u8 hw_antsw_occur : 2;
++	u8 antidx_antb : 3;
++	u8 antidx_anta : 3;
++#endif
++};
++
++#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
++
++__PACK struct phy_sts_rpt_jgr2_type0 {
++	/* @DW0 */
++	u8 page_num;
++	u8 pwdb;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 gain : 6;
++	u8 rsvd_0 : 1;
++	u8 trsw : 1;
++#else
++	u8 trsw : 1;
++	u8 rsvd_0 : 1;
++	u8 gain : 6;
++#endif
++	u8 rsvd_1;
++
++	/* @DW1 */
++	u8 rsvd_2;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 rxsc : 4;
++	u8 agc_table : 4;
++#else
++	u8 agc_table : 4;
++	u8 rxsc : 4;
++#endif
++	u8 channel;
++	u8 band;
++
++	/* @DW2 */
++	u16 length;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 antidx_a : 3;
++	u8 antidx_b : 3;
++	u8 rsvd_3 : 2;
++	u8 antidx_c : 3;
++	u8 antidx_d : 3;
++	u8 rsvd_4 : 2;
++#else
++	u8 rsvd_3 : 2;
++	u8 antidx_b : 3;
++	u8 antidx_a : 3;
++	u8 rsvd_4 : 2;
++	u8 antidx_d : 3;
++	u8 antidx_c : 3;
++#endif
++
++	/* @DW3 */
++	u8 signal_quality;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 vga : 5;
++	u8 lna_l : 3;
++	u8 bb_power : 6;
++	u8 rsvd_9 : 1;
++	u8 lna_h : 1;
++#else
++	u8 lna_l : 3;
++	u8 vga : 5;
++	u8 lna_h : 1;
++	u8 rsvd_9 : 1;
++	u8 bb_power : 6;
++#endif
++	u8 rsvd_5;
++
++	/* @DW4 */
++	u32 rsvd_6;
++
++	/* @DW5 */
++	u32 rsvd_7;
++
++	/* @DW6 */
++	u32 rsvd_8;
++};
++
++__PACK struct phy_sts_rpt_jgr2_type1 {
++	/* @DW0 and DW1 */
++	u8 page_num;
++	u8 pwdb[4];
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 l_rxsc : 4;
++	u8 ht_rxsc : 4;
++#else
++	u8 ht_rxsc : 4;
++	u8 l_rxsc : 4;
++#endif
++	u8 channel;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 band : 2;
++	u8 rsvd_0 : 1;
++	u8 hw_antsw_occu : 1;
++	u8 gnt_bt : 1;
++	u8 ldpc : 1;
++	u8 stbc : 1;
++	u8 beamformed : 1;
++#else
++	u8 beamformed : 1;
++	u8 stbc : 1;
++	u8 ldpc : 1;
++	u8 gnt_bt : 1;
++	u8 hw_antsw_occu : 1;
++	u8 rsvd_0 : 1;
++	u8 band : 2;
++#endif
++
++	/* @DW2 */
++	u16 lsig_length;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 antidx_a : 3;
++	u8 antidx_b : 3;
++	u8 rsvd_1 : 2;
++	u8 antidx_c : 3;
++	u8 antidx_d : 3;
++	u8 rsvd_2 : 2;
++#else
++	u8 rsvd_1 : 2;
++	u8 antidx_b : 3;
++	u8 antidx_a : 3;
++	u8 rsvd_2 : 2;
++	u8 antidx_d : 3;
++	u8 antidx_c : 3;
++#endif
++
++	/* @DW3 */
++	u8 paid;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 paid_msb : 1;
++	u8 gid : 6;
++	u8 rsvd_3 : 1;
++#else
++	u8 rsvd_3 : 1;
++	u8 gid : 6;
++	u8 paid_msb : 1;
++#endif
++	u8 intf_pos;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 intf_pos_msb : 1;
++	u8 rsvd_4 : 2;
++	u8 nb_intf_flag : 1;
++	u8 rf_mode : 2;
++	u8 rsvd_5 : 2;
++#else
++	u8 rsvd_5 : 2;
++	u8 rf_mode : 2;
++	u8 nb_intf_flag : 1;
++	u8 rsvd_4 : 2;
++	u8 intf_pos_msb : 1;
++#endif
++
++	/* @DW4 */
++	s8 rxevm[4]; /* s(8,1) */
++
++	/* @DW5 */
++	s8 cfo_tail[4]; /* s(8,7) */
++
++	/* @DW6 */
++	s8 rxsnr[4]; /* s(8,1) */
++};
++
++__PACK struct phy_sts_rpt_jgr2_type2 {
++	/* @DW0 ane DW1 */
++	u8 page_num;
++	u8 pwdb[4];
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 l_rxsc : 4;
++	u8 ht_rxsc : 4;
++#else
++	u8 ht_rxsc : 4;
++	u8 l_rxsc : 4;
++#endif
++	u8 channel;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 band : 2;
++	u8 rsvd_0 : 1;
++	u8 hw_antsw_occu : 1;
++	u8 gnt_bt : 1;
++	u8 ldpc : 1;
++	u8 stbc : 1;
++	u8 beamformed : 1;
++#else
++	u8 beamformed : 1;
++	u8 stbc : 1;
++	u8 ldpc : 1;
++	u8 gnt_bt : 1;
++	u8 hw_antsw_occu : 1;
++	u8 rsvd_0 : 1;
++	u8 band : 2;
++#endif
++
++/* @DW2 */
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 shift_l_map : 6;
++	u8 rsvd_1 : 2;
++#else
++	u8 rsvd_1 : 2;
++	u8 shift_l_map : 6;
++#endif
++	u8 cnt_pw2cca;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 agc_table_a : 4;
++	u8 agc_table_b : 4;
++	u8 agc_table_c : 4;
++	u8 agc_table_d : 4;
++#else
++	u8 agc_table_b : 4;
++	u8 agc_table_a : 4;
++	u8 agc_table_d : 4;
++	u8 agc_table_c : 4;
++#endif
++
++	/* @DW3 ~ DW6*/
++	u8 cnt_cca2agc_rdy;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 gain_a : 6;
++	u8 rsvd_2 : 1;
++	u8 trsw_a : 1;
++	u8 gain_b : 6;
++	u8 rsvd_3 : 1;
++	u8 trsw_b : 1;
++	u8 gain_c : 6;
++	u8 rsvd_4 : 1;
++	u8 trsw_c : 1;
++	u8 gain_d : 6;
++	u8 rsvd_5 : 1;
++	u8 trsw_d : 1;
++	u8 aagc_step_a : 2;
++	u8 aagc_step_b : 2;
++	u8 aagc_step_c : 2;
++	u8 aagc_step_d : 2;
++#else
++	u8 trsw_a : 1;
++	u8 rsvd_2 : 1;
++	u8 gain_a : 6;
++	u8 trsw_b : 1;
++	u8 rsvd_3 : 1;
++	u8 gain_b : 6;
++	u8 trsw_c : 1;
++	u8 rsvd_4 : 1;
++	u8 gain_c : 6;
++	u8 trsw_d : 1;
++	u8 rsvd_5 : 1;
++	u8 gain_d : 6;
++	u8 aagc_step_d : 2;
++	u8 aagc_step_c : 2;
++	u8 aagc_step_b : 2;
++	u8 aagc_step_a : 2;
++#endif
++	u8 ht_aagc_gain[4];
++	u8 dagc_gain[4];
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 counter : 6;
++	u8 rsvd_6 : 2;
++	u8 syn_count : 5;
++	u8 rsvd_7 : 3;
++#else
++	u8 rsvd_6 : 2;
++	u8 counter : 6;
++	u8 rsvd_7 : 3;
++	u8 syn_count : 5;
++#endif
++};
++#endif
++
++/*@==============================================*/
++#ifdef PHYSTS_3RD_TYPE_SUPPORT
++__PACK struct phy_sts_rpt_jgr3_type0 {
++/* @DW0 : Offset 0 */
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 page_num : 4;
++	u8 pkt_cnt : 2;
++	u8 channel_msb : 2;
++#else
++	u8 channel_msb : 2;
++	u8 pkt_cnt : 2;
++	u8 page_num : 4;
++#endif
++	u8 pwdb_a;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 gain_a : 6;
++	u8 rsvd_0 : 1;
++	u8 trsw : 1;
++#else
++	u8 trsw : 1;
++	u8 rsvd_0 : 1;
++	u8 gain_a : 6;
++#endif
++
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 agc_table_b : 4;
++	u8 agc_table_c : 4;
++#else
++	u8 agc_table_c : 4;
++	u8 agc_table_b : 4;
++#endif
++
++/* @DW1 : Offset 4 */
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 rsvd_1 : 4;
++	u8 agc_table_d : 4;
++#else
++	u8 agc_table_d : 4;
++	u8 rsvd_1 : 4;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 l_rxsc : 4;
++	u8 agc_table_a : 4;
++#else
++	u8 agc_table_a : 4;
++	u8 l_rxsc : 4;
++#endif
++	u8 channel;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 band : 2;
++	u8 rsvd_2_1 : 1;
++	u8 hw_antsw_occur_keep_cck : 1;
++	u8 gnt_bt_keep_cck : 1;
++	u8 rsvd_2_2 : 1;
++	u8 path_sel_o : 2;
++#else
++	u8 path_sel_o : 2;
++	u8 rsvd_2_2 : 1;
++	u8 gnt_bt_keep_cck : 1;
++	u8 hw_antsw_occur_keep_cck : 1;
++	u8 rsvd_2_1 : 1;
++	u8 band : 2;
++#endif
++
++	/* @DW2 : Offset 8 */
++	u16 length;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 antidx_a : 4;
++	u8 antidx_b : 4;
++#else
++	u8 antidx_b : 4;
++	u8 antidx_a : 4;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 antidx_c : 4;
++	u8 antidx_d : 4;
++#else
++	u8 antidx_d : 4;
++	u8 antidx_c : 4;
++#endif
++
++	/* @DW3 : Offset 12 */
++	u8 signal_quality;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 vga_a : 5;
++	u8 lna_l_a : 3;
++#else
++	u8 lna_l_a : 3;
++	u8 vga_a : 5;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 bb_power_a : 6;
++	u8 rsvd_3_1 : 1;
++	u8 lna_h_a : 1;
++#else
++
++	u8 lna_h_a : 1;
++	u8 rsvd_3_1 : 1;
++	u8 bb_power_a : 6;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 rxrate : 2;
++	u8 raterr : 1;
++	u8 lockbit : 1;
++	u8 sqloss : 1;
++	u8 mf_off : 1;
++	u8 rsvd_3_2 : 2;
++#else
++	u8 rsvd_3_2 : 2;
++	u8 mf_off : 1;
++	u8 sqloss : 1;
++	u8 lockbit : 1;
++	u8 raterr : 1;
++	u8 rxrate : 2;
++#endif
++
++	/* @DW4 : Offset 16 */
++	u8 pwdb_b;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 vga_b : 5;
++	u8 lna_l_b : 3;
++#else
++	u8 lna_l_b : 3;
++	u8 vga_b : 5;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 bb_power_b : 6;
++	u8 rsvd_4_1 : 1;
++	u8 lna_h_b : 1;
++#else
++	u8 lna_h_b : 1;
++	u8 rsvd_4_1 : 1;
++	u8 bb_power_b : 6;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 gain_b : 6;
++	u8 rsvd_4_2 : 2;
++#else
++	u8 rsvd_4_2 : 2;
++	u8 gain_b : 6;
++#endif
++
++	/* @DW5 : Offset 20 */
++	u8 pwdb_c;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 vga_c : 5;
++	u8 lna_l_c : 3;
++#else
++	u8 lna_l_c : 3;
++	u8 vga_c : 5;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 bb_power_c : 6;
++	u8 rsvd_5_1 : 1;
++	u8 lna_h_c : 1;
++#else
++	u8 lna_h_c : 1;
++	u8 rsvd_5_1 : 1;
++	u8 bb_power_c : 6;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 gain_c : 6;
++	u8 rsvd_5_2 : 2;
++#else
++	u8 rsvd_5_2 : 2;
++	u8 gain_c : 6;
++#endif
++
++	/* @DW6 : Offset 24 */
++	u8 pwdb_d;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 vga_d : 5;
++	u8 lna_l_d : 3;
++#else
++	u8 lna_l_d : 3;
++	u8 vga_d : 5;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 bb_power_d : 6;
++	u8 rsvd_6_1 : 1;
++	u8 lna_h_d : 1;
++#else
++	u8 lna_h_d : 1;
++	u8 rsvd_6_1 : 1;
++	u8 bb_power_d : 6;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 gain_d : 6;
++	u8 rsvd_6_2 : 2;
++#else
++	u8 rsvd_6_2 : 2;
++	u8 gain_d : 6;
++#endif
++};
++
++__PACK struct phy_sts_rpt_jgr3_type1 {
++/* @DW0 : Offset 0 */
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 page_num : 4;
++	u8 pkt_cnt : 2;
++	u8 channel_pri_msb : 2;
++#else
++	u8 channel_pri_msb : 2;
++	u8 pkt_cnt : 2;
++	u8 page_num : 4;
++#endif
++	u8 pwdb_a;
++	u8 pwdb_b;
++	u8 pwdb_c;
++
++	/* @DW1 : Offset 4 */
++	u8 pwdb_d;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 l_rxsc : 4;
++	u8 ht_rxsc : 4;
++#else
++	u8 ht_rxsc : 4;
++	u8 l_rxsc : 4;
++#endif
++	u8 channel_pri_lsb;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 band : 2;
++	u8 rsvd_0 : 2;
++	u8 gnt_bt : 1;
++	u8 ldpc : 1;
++	u8 stbc : 1;
++	u8 beamformed : 1;
++#else
++	u8 beamformed : 1;
++	u8 stbc : 1;
++	u8 ldpc : 1;
++	u8 gnt_bt : 1;
++	u8 rsvd_0 : 2;
++	u8 band : 2;
++#endif
++
++	/* @DW2 : Offset 8 */
++	u8 channel_sec_lsb;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 channel_sec_msb : 2;
++	u8 rsvd_1 : 2;
++	u8 hw_antsw_occur_a : 1;
++	u8 hw_antsw_occur_b : 1;
++	u8 hw_antsw_occur_c : 1;
++	u8 hw_antsw_occur_d : 1;
++#else
++	u8 hw_antsw_occur_d : 1;
++	u8 hw_antsw_occur_c : 1;
++	u8 hw_antsw_occur_b : 1;
++	u8 hw_antsw_occur_a : 1;
++	u8 rsvd_1 : 2;
++	u8 channel_sec_msb : 2;
++
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 antidx_a : 4;
++	u8 antidx_b : 4;
++#else
++	u8 antidx_b : 4;
++	u8 antidx_a : 4;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 antidx_c : 4;
++	u8 antidx_d : 4;
++#else
++	u8 antidx_d : 4;
++	u8 antidx_c : 4;
++#endif
++
++	/* @DW3 : Offset 12 */
++	u8 paid;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 paid_msb : 1;
++	u8 gid : 6;
++	u8 rsvd_3 : 1;
++#else
++	u8 rsvd_3 : 1;
++	u8 gid : 6;
++	u8 paid_msb : 1;
++#endif
++	u16 rsvd_4;
++#if 0
++	/*@
++	u8		rsvd_4;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8		rsvd_5: 6;
++	u8		rf_mode: 2;
++#else
++	u8		rf_mode: 2;
++	u8		rsvd_5: 6;
++#endif
++*/
++#endif
++	/* @DW4 : Offset 16 */
++	s8 rxevm[4]; /* s(8,1) */
++
++	/* @DW5 : Offset 20 */
++	s8 cfo_tail[4]; /* s(8,7) */
++
++	/* @DW6 : Offset 24 */
++	s8 rxsnr[4]; /* s(8,1) */
++};
++
++__PACK struct phy_sts_rpt_jgr3_type2_3 {
++/* Type2 is primary channel & type3 is secondary channel */
++/* @DW0 and DW1: Offest 0 and Offset 4 */
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 page_num : 4;
++	u8 pkt_cnt : 2;
++	u8 channel_msb : 2;
++#else
++	u8 channel_msb : 2;
++	u8 pkt_cnt : 2;
++	u8 page_num : 4;
++#endif
++	u8 pwdb[4];
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 l_rxsc : 4;
++	u8 ht_rxsc : 4;
++#else
++	u8 ht_rxsc : 4;
++	u8 l_rxsc : 4;
++#endif
++	u8 channel_lsb;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 band : 2;
++	u8 rsvd_0 : 2;
++	u8 gnt_bt : 1;
++	u8 ldpc : 1;
++	u8 stbc : 1;
++	u8 beamformed : 1;
++#else
++	u8 beamformed : 1;
++	u8 stbc : 1;
++	u8 ldpc : 1;
++	u8 gnt_bt : 1;
++	u8 rsvd_0 : 2;
++	u8 band : 2;
++#endif
++
++/* @DW2 : Offset 8 */
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 shift_l_map : 6;
++	u8 rsvd_1 : 2;
++#else
++	u8 rsvd_1 : 2;
++	u8 shift_l_map : 6;
++#endif
++	s8 pwed_th; /* @dynamic energy threshold S(8,2) */
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 agc_table_a : 4;
++	u8 agc_table_b : 4;
++#else
++	u8 agc_table_b : 4;
++	u8 agc_table_a : 4;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 agc_table_c : 4;
++	u8 agc_table_d : 4;
++#else
++	u8 agc_table_d : 4;
++	u8 agc_table_c : 4;
++#endif
++
++	/* @DW3 : Offset 12 */
++	u8 cnt_cca2agc_rdy; /* Time(ns) = cnt_cca2agc_ready*25 */
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 mp_gain_a : 6;
++	u8 mp_gain_b_lsb : 2;
++#else
++	u8 mp_gain_b_lsb : 2;
++	u8 mp_gain_a : 6;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 mp_gain_b_msb : 4;
++	u8 mp_gain_c_lsb : 4;
++#else
++	u8 mp_gain_c_lsb : 4;
++	u8 mp_gain_b_msb : 4;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 mp_gain_c_msb : 2;
++	u8 avg_noise_pwr_lsb : 4;
++	u8 rsvd_3 : 2;
++	/* u8		r_rfmod:2; */
++#else
++	/* u8		r_rfmod:2; */
++	u8 rsvd_3 : 2;
++	u8 avg_noise_pwr_lsb : 4;
++	u8 mp_gain_c_msb : 2;
++#endif
++	/* @DW4 ~ 5: offset 16 ~20 */
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 mp_gain_d : 6;
++	u8 is_freq_select_fading : 1;
++	u8 rsvd_2 : 1;
++#else
++	u8 rsvd_2 : 1;
++	u8 is_freq_select_fading : 1;
++	u8 mp_gain_d : 6;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 aagc_step_a : 2;
++	u8 aagc_step_b : 2;
++	u8 aagc_step_c : 2;
++	u8 aagc_step_d : 2;
++#else
++	u8 aagc_step_d : 2;
++	u8 aagc_step_c : 2;
++	u8 aagc_step_b : 2;
++	u8 aagc_step_a : 2;
++#endif
++	u8 ht_aagc_gain[4];
++	u8 dagc_gain[4];
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 counter : 6;
++	u8 syn_count_lsb : 2;
++#else
++	u8 syn_count_lsb : 2;
++	u8 counter : 6;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 syn_count_msb : 3;
++	u8 avg_noise_pwr_msb : 5;
++#else
++	u8 avg_noise_pwr_msb : 5;
++	u8 syn_count_msb : 3;
++#endif
++};
++
++__PACK struct phy_sts_rpt_jgr3_type4 {
++/* smart antenna */
++/* @DW0 and DW1 : offset 0 and 4  */
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 page_num : 4;
++	u8 pkt_cnt : 2;
++	u8 channel_msb : 2;
++#else
++	u8 channel_msb : 2;
++	u8 pkt_cnt : 2;
++	u8 page_num : 4;
++#endif
++	u8 pwdb[4];
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 l_rxsc : 4;
++	u8 ht_rxsc : 4;
++#else
++	u8 ht_rxsc : 4;
++	u8 l_rxsc : 4;
++#endif
++	u8 channel_lsb;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 band : 2;
++	u8 rsvd_0 : 2;
++	u8 gnt_bt : 1;
++	u8 ldpc : 1;
++	u8 stbc : 1;
++	u8 beamformed : 1;
++#else
++	u8 beamformed : 1;
++	u8 stbc : 1;
++	u8 ldpc : 1;
++	u8 gnt_bt : 1;
++	u8 rsvd_0 : 1;
++	u8 band : 2;
++#endif
++
++/* @DW2 : offset 8 */
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 bad_tone_cnt_min_eign_0 : 4;
++	u8 bad_tone_cnt_cn_excess_0 : 4;
++#else
++	u8 bad_tone_cnt_cn_excess_0 : 4;
++	u8 bad_tone_cnt_min_eign_0 : 4;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 training_done_a : 1;
++	u8 training_done_b : 1;
++	u8 training_done_c : 1;
++	u8 training_done_d : 1;
++	u8 hw_antsw_occur_a : 1;
++	u8 hw_antsw_occur_b : 1;
++	u8 hw_antsw_occur_c : 1;
++	u8 hw_antsw_occur_d : 1;
++#else
++	u8 hw_antsw_occur_d : 1;
++	u8 hw_antsw_occur_c : 1;
++	u8 hw_antsw_occur_b : 1;
++	u8 hw_antsw_occur_a : 1;
++	u8 training_done_d : 1;
++	u8 training_done_c : 1;
++	u8 training_done_b : 1;
++	u8 training_done_a : 1;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 antidx_a : 4;
++	u8 antidx_b : 4;
++#else
++	u8 antidx_b : 4;
++	u8 antidx_a : 4;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 antidx_c : 4;
++	u8 antidx_d : 4;
++#else
++	u8 antidx_d : 4;
++	u8 antidx_c : 4;
++#endif
++/* @DW3 : offset 12 */
++	u8 tx_pkt_cnt;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 bad_tone_cnt_min_eign_1 : 4;
++	u8 bad_tone_cnt_cn_excess_1 : 4;
++#else
++	u8 bad_tone_cnt_cn_excess_1 : 4;
++	u8 bad_tone_cnt_min_eign_1 : 4;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 avg_cond_num_0 : 7;
++	u8 avg_cond_num_1_lsb : 1;
++#else
++	u8 avg_cond_num_1_lsb : 1;
++	u8 avg_cond_num_0 : 7;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 avg_cond_num_1_msb : 6;
++	u8 rsvd_1 : 2;
++#else
++	u8 rsvd_1 : 2;
++	u8 avg_cond_num_1_msb : 6;
++#endif
++
++	/* @DW4 : offset 16 */
++	s8 rxevm[4]; /* s(8,1) */
++
++	/* @DW5 : offset 20 */
++	u8 eigenvalue[4]; /* @eigenvalue or eigenvalue of seg0 (in dB) */
++
++	/* @DW6 : ofset 24 */
++	s8 rxsnr[4]; /* s(8,1) */
++};
++
++__PACK struct phy_sts_rpt_jgr3_type5 {
++/* @Debug */
++/* @DW0 ane DW1 : offset 0 and 4 */
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 page_num : 4;
++	u8 pkt_cnt : 2;
++	u8 channel_msb : 2;
++#else
++	u8 channel_msb : 2;
++	u8 pkt_cnt : 2;
++	u8 page_num : 4;
++#endif
++	u8 pwdb[4];
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 l_rxsc : 4;
++	u8 ht_rxsc : 4;
++#else
++	u8 ht_rxsc : 4;
++	u8 l_rxsc : 4;
++#endif
++	u8 channel_lsb;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 band : 2;
++	u8 rsvd_0 : 2;
++	u8 gnt_bt : 1;
++	u8 ldpc : 1;
++	u8 stbc : 1;
++	u8 beamformed : 1;
++#else
++	u8 beamformed : 1;
++	u8 stbc : 1;
++	u8 ldpc : 1;
++	u8 gnt_bt : 1;
++	u8 rsvd_0 : 2;
++	u8 band : 2;
++#endif
++	/* @DW2 : offset 8 */
++	u8 rsvd_1;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 rsvd_2 : 4;
++	u8 hw_antsw_occur_a : 1;
++	u8 hw_antsw_occur_b : 1;
++	u8 hw_antsw_occur_c : 1;
++	u8 hw_antsw_occur_d : 1;
++#else
++	u8 hw_antsw_occur_d : 1;
++	u8 hw_antsw_occur_c : 1;
++	u8 hw_antsw_occur_b : 1;
++	u8 hw_antsw_occur_a : 1;
++	u8 rsvd_2 : 4;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 antidx_a : 4;
++	u8 antidx_b : 4;
++#else
++	u8 antidx_b : 4;
++	u8 antidx_a : 4;
++#endif
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 antidx_c : 4;
++	u8 antidx_d : 4;
++#else
++	u8 antidx_d : 4;
++	u8 antidx_c : 4;
++#endif
++	/* @DW3 : offset 12 */
++	u8 tx_pkt_cnt;
++#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 inf_pos_0_A_flg : 1;
++	u8 inf_pos_1_A_flg : 1;
++	u8 inf_pos_0_B_flg : 1;
++	u8 inf_pos_1_B_flg : 1;
++	u8 inf_pos_0_C_flg : 1;
++	u8 inf_pos_1_C_flg : 1;
++	u8 inf_pos_0_D_flg : 1;
++	u8 inf_pos_1_D_flg : 1;
++#else
++	u8 inf_pos_1_D_flg : 1;
++	u8 inf_pos_0_D_flg : 1;
++	u8 inf_pos_1_C_flg : 1;
++	u8 inf_pos_0_C_flg : 1;
++	u8 inf_pos_1_B_flg : 1;
++	u8 inf_pos_0_B_flg : 1;
++	u8 inf_pos_1_A_flg : 1;
++	u8 inf_pos_0_A_flg : 1;
++#endif
++	u8 rsvd_3;
++	u8 rsvd_4;
++	/* @DW4 : offset 16 */
++	u8 inf_pos_0_a;
++	u8 inf_pos_1_a;
++	u8 inf_pos_0_b;
++	u8 inf_pos_1_b;
++	/* @DW5 : offset 20 */
++	u8 inf_pos_0_c;
++	u8 inf_pos_1_c;
++	u8 inf_pos_0_d;
++	u8 inf_pos_1_d;
++};
++
++__PACK struct phy_sts_rpt_jgr3_ofdm_cmn {
++	#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 page_num : 4;
++	u8 pkt_cnt : 2;
++	u8 channel_msb : 2;
++	#else
++	u8 channel_msb : 2;
++	u8 pkt_cnt : 2;
++	u8 page_num : 4;
++	#endif
++	u8 pwdb[4];
++	#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 l_rxsc : 4;
++	u8 ht_rxsc : 4;
++	#else
++	u8 ht_rxsc : 4;
++	u8 l_rxsc : 4;
++	#endif
++	u8 channel_lsb;
++	#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
++	u8 band : 2;
++	u8 rsvd_0 : 2;
++	u8 gnt_bt : 1;
++	u8 ldpc : 1;
++	u8 stbc : 1;
++	u8 beamformed : 1;
++	#else
++	u8 beamformed : 1;
++	u8 stbc : 1;
++	u8 ldpc : 1;
++	u8 gnt_bt : 1;
++	u8 rsvd_0 : 1;
++	u8 band : 2;
++	#endif
++};
++#endif /*@#ifdef PHYSTS_3RD_TYPE_SUPPORT*/
++
++#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
++void phydm_physts_auto_switch_jgr3_set(void *dm_void, boolean enable,
++				       u8 bitmap_en);
++#endif
++
++#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
++boolean
++phydm_query_is_mu_api(struct dm_struct *phydm, u8 ppdu_idx, u8 *p_data_rate,
++		      u8 *p_gid);
++#endif
++
++void phydm_reset_phystatus_avg(struct dm_struct *dm);
++
++void phydm_reset_phystatus_statistic(struct dm_struct *dm);
++
++void phydm_reset_rssi_for_dm(struct dm_struct *dm, u8 station_id);
++
++void phydm_get_cck_rssi_table_from_reg(struct dm_struct *dm);
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void phydm_normal_driver_rx_sniffer(
++	struct dm_struct *dm,
++	u8 *desc,
++	PRT_RFD_STATUS rt_rfd_status,
++	u8 *drv_info,
++	u8 phy_status);
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++s32 phydm_signal_scale_mapping(struct dm_struct *dm, s32 curr_sig);
++#endif
++
++boolean odm_phy_status_query(struct dm_struct *dm,
++			     struct phydm_phyinfo_struct *phy_info,
++			     u8 *phy_sts,
++			     struct phydm_perpkt_info_struct *pktinfo);
++
++void phydm_rx_phy_status_init(void *dm_void);
++
++void phydm_physts_dbg(void *dm_void, char input[][16], u32 *_used,
++		      char *output, u32 *_out_len);
++
++#endif /*@#ifndef	__HALHWOUTSRC_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pmac_tx_setting.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pmac_tx_setting.c
+new file mode 100644
+index 000000000..81ce34c28
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pmac_tx_setting.c
+@@ -0,0 +1,510 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ ************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++void phydm_start_cck_cont_tx_jgr3(void *dm_void,
++				  struct phydm_pmac_info *tx_info)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
++	u8 rate = tx_info->tx_rate; /* HW rate */
++
++	/* if CCK block on? */
++	if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
++		odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 0x1);
++
++	/* Turn Off All Test mode */
++	odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
++
++	odm_set_bb_reg(dm, R_0x1a00, 0x3000, rate);
++	odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2); /* transmit mode */
++	odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); /* turn on scrambler*/
++
++	/* Fix rate selection issue */
++	odm_set_bb_reg(dm, R_0x1a70, BIT(14), 0x1);
++	/* set RX weighting for path I & Q to 0 */
++	odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
++	/* set loopback mode */
++	odm_set_bb_reg(dm, R_0x1c3c, BIT(4), 0x1);
++
++	pmac_tx->cck_cont_tx = true;
++	pmac_tx->ofdm_cont_tx = false;
++}
++
++void phydm_stop_cck_cont_tx_jgr3(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
++
++	pmac_tx->cck_cont_tx = false;
++	pmac_tx->ofdm_cont_tx = false;
++
++	odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0); /* normal mode */
++	odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); /* turn on scrambler*/
++
++	/* back to default */
++	odm_set_bb_reg(dm, R_0x1a70, BIT(14), 0x0);
++	odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
++	odm_set_bb_reg(dm, R_0x1c3c, BIT(4), 0x0);
++	/* BB Reset */
++	odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
++	odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
++}
++
++void phydm_start_ofdm_cont_tx_jgr3(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
++
++	/* 1. if OFDM block on */
++	if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
++		odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 0x1);
++
++	/* 2. set CCK test mode off, set to CCK normal mode */
++	odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);
++
++	/* 3. turn on scramble setting */
++	odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1);
++
++	/* 4. Turn On Continue Tx and turn off the other test modes. */
++	odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x1);
++
++	pmac_tx->cck_cont_tx = false;
++	pmac_tx->ofdm_cont_tx = true;
++}
++
++void phydm_stop_ofdm_cont_tx_jgr3(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
++
++	pmac_tx->cck_cont_tx = false;
++	pmac_tx->ofdm_cont_tx = false;
++
++	/* Turn Off All Test mode */
++	odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
++
++	/* Delay 10 ms */
++	ODM_delay_ms(10);
++
++	/* BB Reset */
++	odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
++	odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
++}
++
++void phydm_stop_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
++	u32 tmp = 0;
++
++	odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x2); /* TX Stop */
++
++	if (tx_info->mode == CONT_TX) {
++		if (pmac_tx->is_cck_rate)
++			phydm_stop_cck_cont_tx_jgr3(dm);
++		else
++			phydm_stop_ofdm_cont_tx_jgr3(dm);
++	}
++}
++
++void phydm_set_mac_phy_txinfo_jgr3(void *dm_void,
++				   struct phydm_pmac_info *tx_info)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
++	u32 tmp = 0;
++
++	odm_set_bb_reg(dm, R_0xa58, 0x003f8000, tx_info->tx_rate);
++
++	/*0x900[1] ndp_sound */
++	odm_set_bb_reg(dm, R_0x900, BIT(1), tx_info->ndp_sound);
++
++	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	tx_info->m_stbc = tx_info->m_stbc - 1;
++	#endif
++	/*0x900[27:24] txsc [29:28] bw [31:30] m_stbc */
++	tmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) |
++		((tx_info->m_stbc) << 6);
++	odm_set_bb_reg(dm, R_0x900, 0xff000000, tmp);
++
++	if (tx_info->tx_sc == 1) /*upper*/
++		odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x5);
++	else if (tx_info->tx_sc == 2) /*lower*/
++		odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x6);
++	else /* duplicate*/
++		odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x0);
++
++	if (pmac_tx->is_ofdm_rate) {
++		odm_set_bb_reg(dm, R_0x900, BIT(0), 0x0);
++		odm_set_bb_reg(dm, R_0x900, BIT(2), 0x0);
++	} else if (pmac_tx->is_ht_rate) {
++		odm_set_bb_reg(dm, R_0x900, BIT(0), 0x1);
++		odm_set_bb_reg(dm, R_0x900, BIT(2), 0x0);
++	} else if (pmac_tx->is_vht_rate) {
++		odm_set_bb_reg(dm, R_0x900, BIT(0), 0x0);
++		odm_set_bb_reg(dm, R_0x900, BIT(2), 0x1);
++	}
++
++	/* for TX interval */
++	odm_set_bb_reg(dm, R_0x9b8, MASKHWORD, tx_info->packet_period);
++}
++
++void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
++	u32 tmp = 0;
++
++	if (pmac_tx->is_cck_rate)
++		return;
++
++	odm_set_bb_reg(dm, R_0x1eb4, 0xfffff, tx_info->packet_count);
++
++	/* L-SIG */
++	tmp = BYTE_2_DWORD(0, tx_info->lsig[2], tx_info->lsig[1],
++			   tx_info->lsig[0]);
++	odm_set_bb_reg(dm, R_0x908, 0xffffff, tmp);
++	if (pmac_tx->is_ht_rate) {
++	/* HT SIG */
++		tmp = BYTE_2_DWORD(0, tx_info->ht_sig[2], tx_info->ht_sig[1],
++				   tx_info->ht_sig[0]);
++		odm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp);
++		tmp = BYTE_2_DWORD(0, tx_info->ht_sig[5], tx_info->ht_sig[4],
++				   tx_info->ht_sig[3]);
++		odm_set_bb_reg(dm, R_0x910, 0xffffff, tmp);
++	} else if (pmac_tx->is_vht_rate) {
++	/* VHT SIG A/B/serv_field/delimiter */
++		tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[2],
++				   tx_info->vht_sig_a[1],
++				   tx_info->vht_sig_a[0]);
++		odm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp);
++		tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[5],
++				   tx_info->vht_sig_a[4],
++				   tx_info->vht_sig_a[3]);
++		odm_set_bb_reg(dm, R_0x910, 0xffffff, tmp);
++		tmp = BYTE_2_DWORD(tx_info->vht_sig_b[3], tx_info->vht_sig_b[2],
++				   tx_info->vht_sig_b[1],
++				   tx_info->vht_sig_b[0]);
++		odm_set_bb_reg(dm, R_0x914, 0x1fffffff, tmp);
++		odm_set_bb_reg(dm, R_0x938, 0xff00, tx_info->vht_sig_b_crc);
++
++		tmp = BYTE_2_DWORD(tx_info->vht_delimiter[3],
++				   tx_info->vht_delimiter[2],
++				   tx_info->vht_delimiter[1],
++				   tx_info->vht_delimiter[0]);
++		odm_set_bb_reg(dm, R_0x940, MASKDWORD, tmp);
++	}
++}
++
++void phydm_set_cck_preamble_hdr_jgr3(void *dm_void,
++				     struct phydm_pmac_info *tx_info)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
++	u32 tmp = 0;
++
++	if (!pmac_tx->is_cck_rate)
++		return;
++
++	tmp = tx_info->packet_count | (tx_info->sfd << 16);
++	odm_set_bb_reg(dm, R_0x1e64, MASKDWORD, tmp);
++	tmp = tx_info->signal_field | (tx_info->service_field << 8) |
++	      (tx_info->length << 16);
++	odm_set_bb_reg(dm, R_0x1e68, MASKDWORD, tmp);
++	tmp = BYTE_2_DWORD(0, 0, tx_info->crc16[1], tx_info->crc16[0]);
++	odm_set_bb_reg(dm, R_0x1e6c, MASKLWORD, tmp);
++
++	if (tx_info->is_short_preamble)
++		odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0x0);
++	else
++		odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0x1);
++}
++
++void phydm_set_mode_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
++			 enum phydm_pmac_mode mode)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
++
++	if (mode == CONT_TX) {
++		tx_info->packet_count = 1;
++
++		if (pmac_tx->is_cck_rate)
++			phydm_start_cck_cont_tx_jgr3(dm, tx_info);
++		else
++			phydm_start_ofdm_cont_tx_jgr3(dm);
++	}
++}
++
++void phydm_set_pmac_txon_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
++
++	odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0x1); /*Turn on PMAC */
++
++	/*mac scramble seed setting, only in 8198F */
++	#if (RTL8198F_SUPPORT)
++		if (dm->support_ic_type & ODM_RTL8198F)
++			if (!odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
++				odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0x1);
++	#endif
++
++	if (pmac_tx->is_cck_rate) {
++		odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x8); /*TX CCK ON */
++		odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0x0);
++	} else {
++		odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x4); /*TX Ofdm ON */
++	}
++}
++
++void phydm_set_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
++			    enum rf_path mpt_rf_path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
++
++	pmac_tx->is_cck_rate = phydm_is_cck_rate(dm, tx_info->tx_rate);
++	pmac_tx->is_ofdm_rate = phydm_is_ofdm_rate(dm, tx_info->tx_rate);
++	pmac_tx->is_ht_rate = phydm_is_ht_rate(dm, tx_info->tx_rate);
++	pmac_tx->is_vht_rate = phydm_is_vht_rate(dm, tx_info->tx_rate);
++	pmac_tx->path = mpt_rf_path;
++
++	if (!tx_info->en_pmac_tx) {
++		phydm_stop_pmac_tx_jgr3(dm, tx_info);
++		return;
++	}
++
++	phydm_set_mode_jgr3(dm, tx_info, tx_info->mode);
++
++	if (pmac_tx->is_cck_rate)
++		phydm_set_cck_preamble_hdr_jgr3(dm, tx_info);
++	else
++		phydm_set_sig_jgr3(dm, tx_info);
++
++	phydm_set_mac_phy_txinfo_jgr3(dm, tx_info);
++	phydm_set_pmac_txon_jgr3(dm, tx_info);
++}
++
++void phydm_set_tmac_tx_jgr3(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	/* Turn on TMAC */
++	if (odm_get_bb_reg(dm, R_0x1d08, BIT(0)))
++		odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0x0);
++
++	/* mac scramble seed setting, only in 8198F */
++	#if (RTL8198F_SUPPORT)
++		if (dm->support_ic_type & ODM_RTL8198F)
++			if (odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
++				odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0x0);
++	#endif
++
++	/* Turn on TMAC CCK */
++	if (!odm_get_bb_reg(dm, R_0x1a84, BIT(31)))
++		odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0x1);
++}
++#endif
++
++void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		phydm_start_cck_cont_tx_jgr3(dm, tx_info);
++	#endif
++}
++
++void phydm_stop_cck_cont_tx(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		phydm_stop_cck_cont_tx_jgr3(dm);
++	#endif
++}
++
++void phydm_start_ofdm_cont_tx(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		phydm_start_ofdm_cont_tx_jgr3(dm);
++	#endif
++}
++
++void phydm_stop_ofdm_cont_tx(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		phydm_stop_ofdm_cont_tx_jgr3(dm);
++	#endif
++}
++
++void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,
++		       enum rf_path mpt_rf_path)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		phydm_set_pmac_tx_jgr3(dm, tx_info, mpt_rf_path);
++	#endif
++}
++
++void phydm_set_tmac_tx(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		phydm_set_tmac_tx_jgr3(dm);
++	#endif
++}
++
++void phydm_pmac_tx_dbg(void *dm_void, char input[][16], u32 *_used,
++		       char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pmac_info tx_info;
++	char help[] = "-h";
++	char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
++	u32 var[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 i = 0;
++	u32 tx_cnt = 0x0;
++	u8 poll_cnt = 0x0;
++
++	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var[0]);
++
++	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
++		return;
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[pmac_tx] basic : {1} {rate_idx}(only 1M & 6M) {count}\n");
++	} else {
++		for (i = 1; i < 7; i++) {
++			if (input[i + 1]) {
++				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
++					     &var[i]);
++			}
++		}
++
++		tx_info.en_pmac_tx = true;
++		tx_info.mode = PKTS_TX;
++		tx_info.ndp_sound = false;
++		tx_info.bw = CHANNEL_WIDTH_20;
++		tx_info.tx_sc = 0x0; /*duplicate*/
++		tx_info.m_stbc = 0x0; /*disable*/
++		tx_info.packet_period = 2000; /*d'500 us*/
++		tx_info.tx_rate = (u8)var[1];
++		tx_info.packet_count = (u32)var[2];
++
++		if (tx_info.tx_rate == ODM_RATE1M) {
++			tx_info.signal_field = 0xa; /*rate = 1M*/
++			tx_info.service_field = 0x0;
++			tx_info.length = 8000; /*d'8000 us=1000 bytes*/
++			tx_info.crc16[0] = 0x60;
++			tx_info.crc16[1] = 0x8e;
++			/*long preamble*/
++			tx_info.is_short_preamble = false;
++			tx_info.sfd = 0xf3a0;
++		} else if (tx_info.tx_rate == ODM_RATE6M) {
++			/*l-sig[3:0] = rate = 6M = 0xb*/
++			/*l-sig[16:5] = length = 1000 bytes*/
++			/*l-sig[17] = parity = 1*/
++			tx_info.lsig[0] = 0xb;
++			tx_info.lsig[1] = 0x7d;
++			tx_info.lsig[2] = 0x2;
++		}
++		phydm_print_rate_2_buff(dm, tx_info.tx_rate, dbg_buf,
++					PHYDM_SNPRINT_SIZE);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "rate=%s, count=%d, pkt_interval=500(us), length=1000(bytes)\n",
++			 dbg_buf, tx_info.packet_count);
++
++		if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "check trx idle failed, please try again.\n");
++			return;
++		}
++
++		phydm_reset_bb_hw_cnt(dm);
++		phydm_set_pmac_tx_jgr3(dm, &tx_info, RF_PATH_A);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "pmac_tx enabled, please wait for tx_cnt = %d\n",
++			 tx_info.packet_count);
++		while (1) {
++			if (phydm_is_cck_rate(dm, tx_info.tx_rate))
++				tx_cnt = odm_get_bb_reg(dm, R_0x2de4,
++							MASKLWORD);
++			else
++				tx_cnt = odm_get_bb_reg(dm, R_0x2de0,
++							MASKLWORD);
++
++			if (tx_cnt >= tx_info.packet_count || poll_cnt >= 10)
++				break;
++
++			ODM_delay_ms(100);
++			poll_cnt++;
++		}
++
++		if (tx_cnt < tx_info.packet_count)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "polling time out(1s), tx_cnt = %d\n", tx_cnt);
++		else
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "pmac_tx finished, poll_cnt = %d\n", poll_cnt);
++
++		tx_info.en_pmac_tx = false;
++		phydm_set_pmac_tx(dm, &tx_info, RF_PATH_A);
++		phydm_set_tmac_tx(dm);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Stop pmac_tx and turn on true mac mode.\n");
++
++		phydm_stop_ic_trx(dm, PHYDM_REVERT);
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++#endif
+\ No newline at end of file
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pmac_tx_setting.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pmac_tx_setting.h
+new file mode 100644
+index 000000000..689dc429d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pmac_tx_setting.h
+@@ -0,0 +1,109 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_PMAC_TX_SETTING_H__
++#define __PHYDM_PMAC_TX_SETTING_H__
++
++/*2019.08.02 Modify pmac_tx echo cmd to prevent from hang*/
++#define PMAC_TX_SETTING_VERSION "2.0"
++
++/* 1 ============================================================
++ * 1  Definition
++ * 1 ============================================================
++ */
++
++/* 1 ============================================================
++ * 1  structure
++ * 1 ============================================================
++ */
++struct phydm_pmac_info {
++	u8 en_pmac_tx:1; /*0: disable pmac 1: enable pmac */
++	u8 mode:3; /*0: Packet TX 3:Continuous TX */
++	u8 tx_rate; /*should be HW rate*/
++	u8 tx_sc;
++	u8 is_short_preamble:1;
++	u8 ndp_sound:1;
++	u8 bw:3; /* 0:20 1:40 2:80Mhz */
++	u8 m_stbc; /* bSTBC + 1 for WIN/CE, bSTBC for others*/
++	u16 packet_period;
++	u32 packet_count;
++	u8 packet_pattern;
++	u16 sfd;
++	u8 signal_field;
++	u8 service_field;
++	u16 length;
++	u8 crc16[2];
++	u8 lsig[3];
++	u8 ht_sig[6];
++	u8 vht_sig_a[6];
++	u8 vht_sig_b[4];
++	u8 vht_sig_b_crc;
++	u8 vht_delimiter[4];
++};
++
++struct phydm_pmac_tx {
++	boolean is_cck_rate;
++	boolean is_ofdm_rate;
++	boolean is_ht_rate;
++	boolean is_vht_rate;
++	boolean cck_cont_tx;
++	boolean ofdm_cont_tx;
++	u8 path;
++};
++
++/* 1 ============================================================
++ * 1  enumeration
++ * 1 ============================================================
++ */
++
++enum phydm_pmac_mode {
++	NONE_TEST,
++	PKTS_TX,
++	PKTS_RX,
++	CONT_TX,
++	OFDM_SINGLE_TONE_TX,
++	CCK_CARRIER_SIPPRESSION_TX
++};
++
++/* 1 ============================================================
++ * 1  function prototype
++ * 1 ============================================================
++ */
++void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info);
++
++void phydm_stop_cck_cont_tx(void *dm_void);
++
++void phydm_start_ofdm_cont_tx(void *dm_void);
++
++void phydm_stop_ofdm_cont_tx(void *dm_void);
++
++void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,
++		       enum rf_path mpt_rf_path);
++
++void phydm_set_tmac_tx(void *dm_void);
++
++void phydm_pmac_tx_dbg(void *dm_void, char input[][16], u32 *_used,
++		       char *output, u32 *_out_len);
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pow_train.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pow_train.c
+new file mode 100644
+index 000000000..56bc2411d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pow_train.c
+@@ -0,0 +1,171 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*************************************************************
++ * include files
++ ************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#ifdef PHYDM_POWER_TRAINING_SUPPORT
++void phydm_reset_pt_para(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;
++
++	pt_t->pow_train_score = 0;
++}
++
++void phydm_update_power_training_state(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;
++	struct phydm_fa_struct *fa_cnt = &dm->false_alm_cnt;
++	struct ccx_info *ccx = &dm->dm_ccx_info;
++	u32 pt_score_tmp = ENABLE_PT_SCORE;
++	u32 crc_ok_cnt = 0;
++	u32 cca_cnt = 0;
++
++	/*@is_disable_power_training is the key to H2C to disable/enable PT*/
++	/*@if is_disable_power_training == 1, it will use largest power*/
++	if (!(dm->support_ability & ODM_BB_PWR_TRAIN) || !dm->is_linked) {
++		dm->is_disable_power_training = true;
++		phydm_reset_pt_para(dm);
++		return;
++	}
++
++	PHYDM_DBG(dm, DBG_PWR_TRAIN, "%s ======>\n", __func__);
++
++	if (pt_t->pt_state == DISABLE_POW_TRAIN) {
++		dm->is_disable_power_training = true;
++		phydm_reset_pt_para(dm);
++		PHYDM_DBG(dm, DBG_PWR_TRAIN, "Disable PT\n");
++		return;
++
++	} else if (pt_t->pt_state == ENABLE_POW_TRAIN) {
++		dm->is_disable_power_training = false;
++		phydm_reset_pt_para(dm);
++		PHYDM_DBG(dm, DBG_PWR_TRAIN, "Enable PT\n");
++		return;
++
++	} else if (pt_t->pt_state == DYNAMIC_POW_TRAIN) {
++		PHYDM_DBG(dm, DBG_PWR_TRAIN, "Dynamic PT\n");
++
++		/* @Compute score */
++		crc_ok_cnt = dm->phy_dbg_info.num_qry_phy_status_ofdm +
++			     dm->phy_dbg_info.num_qry_phy_status_cck;
++		cca_cnt = fa_cnt->cnt_cca_all;
++#if 0
++		if (crc_ok_cnt > cca_cnt) { /*invalid situation*/
++			pt_score_tmp = KEEP_PRE_PT_SCORE;
++			return;
++		} else if ((crc_ok_cnt + (crc_ok_cnt >> 1)) <= cca_cnt) {
++		/* @???crc_ok <= (2/3)*cca */
++			pt_score_tmp = DISABLE_PT_SCORE;
++			dm->is_disable_power_training = true;
++		} else if ((crc_ok_cnt + (crc_ok_cnt >> 2)) <= cca_cnt) {
++		/* @???crc_ok <= (4/5)*cca */
++			pt_score_tmp = KEEP_PRE_PT_SCORE;
++		} else {
++		/* @???crc_ok > (4/5)*cca */
++			pt_score_tmp = ENABLE_PT_SCORE;
++			dm->is_disable_power_training = false;
++		}
++#endif
++		if (ccx->nhm_ratio > 10) {
++			pt_score_tmp = DISABLE_PT_SCORE;
++			dm->is_disable_power_training = true;
++		} else if (ccx->nhm_ratio < 5) {
++			pt_score_tmp = ENABLE_PT_SCORE;
++			dm->is_disable_power_training = false;
++		} else {
++			pt_score_tmp = KEEP_PRE_PT_SCORE;
++		}
++
++		PHYDM_DBG(dm, DBG_PWR_TRAIN,
++			  "pkt_cnt{ofdm,cck,all} = {%d, %d, %d}, cnt_cca_all=%d\n",
++			  dm->phy_dbg_info.num_qry_phy_status_ofdm,
++			  dm->phy_dbg_info.num_qry_phy_status_cck,
++			  crc_ok_cnt, cca_cnt);
++
++		PHYDM_DBG(dm, DBG_PWR_TRAIN, "pt_score_tmp=%d\n", pt_score_tmp);
++
++		/* smoothing */
++		pt_t->pow_train_score = (pt_score_tmp << 4) +
++					(pt_t->pow_train_score >> 1) +
++					(pt_t->pow_train_score >> 2);
++
++		pt_score_tmp = (pt_t->pow_train_score + 32) >> 6;
++
++		PHYDM_DBG(dm, DBG_PWR_TRAIN,
++			  "pow_train_score = %d, score after smoothing = %d, is_disable_PT = %d\n",
++			  pt_t->pow_train_score, pt_score_tmp,
++			  dm->is_disable_power_training);
++	} else {
++		PHYDM_DBG(dm, DBG_PWR_TRAIN, "[%s]warning\n", __func__);
++	}
++}
++
++void phydm_pow_train_debug(
++	void *dm_void,
++	char input[][16],
++	u32 *_used,
++	char *output,
++	u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 i;
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{0: Auto PT, 1:enable, 2: disable}\n");
++	} else {
++		for (i = 0; i < 10; i++) {
++			if (input[i + 1])
++				PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
++		}
++
++		if (var1[0] == 0)
++			pt_t->pt_state = DYNAMIC_POW_TRAIN;
++		else if (var1[0] == 1)
++			pt_t->pt_state = ENABLE_POW_TRAIN;
++		else if (var1[0] == 2)
++			pt_t->pt_state = DISABLE_POW_TRAIN;
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "PT state = %d\n", pt_t->pt_state);
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pow_train.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pow_train.h
+new file mode 100644
+index 000000000..f966607aa
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pow_train.h
+@@ -0,0 +1,84 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_POW_TRAIN_H__
++#define __PHYDM_POW_TRAIN_H__
++
++#define POW_TRAIN_VERSION "1.0" /* @2017.07.0141  Dino, Add phydm_pow_train.h*/
++
++/****************************************************************
++ * 1 ============================================================
++ * 1  Definition
++ * 1 ============================================================
++ ***************************************************************/
++
++#ifdef PHYDM_POWER_TRAINING_SUPPORT
++/****************************************************************
++ * 1 ============================================================
++ * 1  structure
++ * 1 ============================================================
++ ***************************************************************/
++
++struct phydm_pow_train_stuc {
++	u8 pt_state;
++	u32 pow_train_score;
++};
++
++/****************************************************************
++ * 1 ============================================================
++ * 1  enumeration
++ * 1 ============================================================
++ ***************************************************************/
++
++enum pow_train_state {
++	DYNAMIC_POW_TRAIN = 0,
++	ENABLE_POW_TRAIN = 1,
++	DISABLE_POW_TRAIN = 2
++};
++
++enum power_training_score {
++	DISABLE_PT_SCORE = 0,
++	KEEP_PRE_PT_SCORE = 1,
++	ENABLE_PT_SCORE = 2
++};
++
++/****************************************************************
++ * 1 ============================================================
++ * 1  function prototype
++ * 1 ============================================================
++ ***************************************************************/
++
++void phydm_update_power_training_state(
++	void *dm_void);
++
++void phydm_pow_train_debug(
++	void *dm_void,
++	char input[][16],
++	u32 *_used,
++	char *output,
++	u32 *_out_len);
++
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pre_define.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pre_define.h
+new file mode 100644
+index 000000000..8042731a8
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_pre_define.h
+@@ -0,0 +1,980 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDMPREDEFINE_H__
++#define __PHYDMPREDEFINE_H__
++
++/****************************************************************
++ * 1 ============================================================
++ * 1  Definition
++ * 1 ============================================================
++ ***************************************************************/
++
++#define PHYDM_CODE_BASE			"PHYDM_V045"
++#define PHYDM_RELEASE_DATE		"20191016.0"
++
++/*PHYDM API status*/
++#define	PHYDM_SET_FAIL			0
++#define	PHYDM_SET_SUCCESS		1
++#define	PHYDM_SET_NO_NEED		3
++
++/*PHYDM Set/Revert*/
++#define	PHYDM_SET			1
++#define	PHYDM_REVERT			2
++
++/* @Max path of IC */
++/*N-IC*/
++#define MAX_PATH_NUM_8188E		1
++#define MAX_PATH_NUM_8188F		1
++#define MAX_PATH_NUM_8710B		1
++#define MAX_PATH_NUM_8723B		1
++#define MAX_PATH_NUM_8723D		1
++#define MAX_PATH_NUM_8703B		1
++#define MAX_PATH_NUM_8192E		2
++#define MAX_PATH_NUM_8192F		2
++#define MAX_PATH_NUM_8197F		2
++#define MAX_PATH_NUM_8198F		4
++#define MAX_PATH_NUM_8197G		2
++#define MAX_PATH_NUM_8721D		1
++#define MAX_PATH_NUM_8710C		1
++
++/*@AC-IC*/
++#define MAX_PATH_NUM_8821A		1
++#define MAX_PATH_NUM_8881A		1
++#define MAX_PATH_NUM_8821C		1
++#define MAX_PATH_NUM_8195B		1
++#define MAX_PATH_NUM_8812A		2
++#define MAX_PATH_NUM_8822B		2
++#define MAX_PATH_NUM_8822C		2
++#define MAX_PATH_NUM_8814A		4
++#define MAX_PATH_NUM_8814B		4
++#define MAX_PATH_NUM_8814C		4
++#define MAX_PATH_NUM_8195B		1
++#define MAX_PATH_NUM_8812F		2
++
++/* @Max RF path */
++#define PHYDM_MAX_RF_PATH_N		2	/*@For old N-series IC*/
++#define PHYDM_MAX_RF_PATH		4
++
++/* number of entry */
++#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
++	#ifdef DM_ODM_CE_MAC80211
++		/* @defined in wifi.h (32+1) */
++	#else
++		#define	ASSOCIATE_ENTRY_NUM	MACID_NUM_SW_LIMIT  /* @Max size of asoc_entry[].*/
++	#endif
++	#define	ODM_ASSOCIATE_ENTRY_NUM	ASSOCIATE_ENTRY_NUM
++#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	#define ASSOCIATE_ENTRY_NUM	NUM_STAT
++	#define	ODM_ASSOCIATE_ENTRY_NUM	(ASSOCIATE_ENTRY_NUM + 1)
++#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
++	#ifdef CONFIG_CONCURRENT_MODE
++		#define ASSOCIATE_ENTRY_NUM	NUM_STA + 2 /*@2 is for station mod*/
++	#else
++		#define ASSOCIATE_ENTRY_NUM	NUM_STA /*@8 is for max size of asoc_entry[].*/
++	#endif
++	#define	ODM_ASSOCIATE_ENTRY_NUM	ASSOCIATE_ENTRY_NUM
++#else
++	#define ODM_ASSOCIATE_ENTRY_NUM	(((ASSOCIATE_ENTRY_NUM + 1) * 3) + 1)
++#endif
++
++/* @-----MGN rate--------------------------------- */
++
++enum PDM_RATE_TYPE {
++	PDM_1SS			= 1,	/*VHT/HT 1SS*/
++	PDM_2SS			= 2,	/*VHT/HT 2SS*/
++	PDM_3SS			= 3,	/*VHT/HT 3SS*/
++	PDM_4SS			= 4,	/*VHT/HT 4SS*/
++	PDM_CCK			= 11,	/*@B*/
++	PDM_OFDM		= 12	/*@G*/
++};
++
++enum ODM_MGN_RATE {
++	ODM_MGN_1M		= 0x02,
++	ODM_MGN_2M		= 0x04,
++	ODM_MGN_5_5M		= 0x0B,
++	ODM_MGN_6M		= 0x0C,
++	ODM_MGN_9M		= 0x12,
++	ODM_MGN_11M		= 0x16,
++	ODM_MGN_12M		= 0x18,
++	ODM_MGN_18M		= 0x24,
++	ODM_MGN_24M		= 0x30,
++	ODM_MGN_36M		= 0x48,
++	ODM_MGN_48M		= 0x60,
++	ODM_MGN_54M		= 0x6C,
++	ODM_MGN_MCS32		= 0x7F,
++	ODM_MGN_MCS0		= 0x80,
++	ODM_MGN_MCS1,
++	ODM_MGN_MCS2,
++	ODM_MGN_MCS3,
++	ODM_MGN_MCS4,
++	ODM_MGN_MCS5,
++	ODM_MGN_MCS6,
++	ODM_MGN_MCS7		= 0x87,
++	ODM_MGN_MCS8,
++	ODM_MGN_MCS9,
++	ODM_MGN_MCS10,
++	ODM_MGN_MCS11,
++	ODM_MGN_MCS12,
++	ODM_MGN_MCS13,
++	ODM_MGN_MCS14,
++	ODM_MGN_MCS15,
++	ODM_MGN_MCS16		= 0x90,
++	ODM_MGN_MCS17,
++	ODM_MGN_MCS18,
++	ODM_MGN_MCS19,
++	ODM_MGN_MCS20,
++	ODM_MGN_MCS21,
++	ODM_MGN_MCS22,
++	ODM_MGN_MCS23,
++	ODM_MGN_MCS24		= 0x98,
++	ODM_MGN_MCS25,
++	ODM_MGN_MCS26,
++	ODM_MGN_MCS27,
++	ODM_MGN_MCS28,
++	ODM_MGN_MCS29,
++	ODM_MGN_MCS30,
++	ODM_MGN_MCS31,
++	ODM_MGN_VHT1SS_MCS0	= 0xa0,
++	ODM_MGN_VHT1SS_MCS1,
++	ODM_MGN_VHT1SS_MCS2,
++	ODM_MGN_VHT1SS_MCS3,
++	ODM_MGN_VHT1SS_MCS4,
++	ODM_MGN_VHT1SS_MCS5,
++	ODM_MGN_VHT1SS_MCS6,
++	ODM_MGN_VHT1SS_MCS7,
++	ODM_MGN_VHT1SS_MCS8,
++	ODM_MGN_VHT1SS_MCS9,
++	ODM_MGN_VHT2SS_MCS0	= 0xaa,
++	ODM_MGN_VHT2SS_MCS1	= 0xab,
++	ODM_MGN_VHT2SS_MCS2,
++	ODM_MGN_VHT2SS_MCS3,
++	ODM_MGN_VHT2SS_MCS4,
++	ODM_MGN_VHT2SS_MCS5	= 0xaf,
++	ODM_MGN_VHT2SS_MCS6	= 0xb0,
++	ODM_MGN_VHT2SS_MCS7,
++	ODM_MGN_VHT2SS_MCS8,
++	ODM_MGN_VHT2SS_MCS9	= 0xb3,
++	ODM_MGN_VHT3SS_MCS0	= 0xb4,
++	ODM_MGN_VHT3SS_MCS1,
++	ODM_MGN_VHT3SS_MCS2,
++	ODM_MGN_VHT3SS_MCS3,
++	ODM_MGN_VHT3SS_MCS4,
++	ODM_MGN_VHT3SS_MCS5,
++	ODM_MGN_VHT3SS_MCS6,
++	ODM_MGN_VHT3SS_MCS7	= 0xbb,
++	ODM_MGN_VHT3SS_MCS8	= 0xbc,
++	ODM_MGN_VHT3SS_MCS9	= 0xbd,
++	ODM_MGN_VHT4SS_MCS0	= 0xbe,
++	ODM_MGN_VHT4SS_MCS1,
++	ODM_MGN_VHT4SS_MCS2,
++	ODM_MGN_VHT4SS_MCS3,
++	ODM_MGN_VHT4SS_MCS4,
++	ODM_MGN_VHT4SS_MCS5,
++	ODM_MGN_VHT4SS_MCS6,
++	ODM_MGN_VHT4SS_MCS7,
++	ODM_MGN_VHT4SS_MCS8,
++	ODM_MGN_VHT4SS_MCS9	= 0xc7,
++	ODM_MGN_UNKNOWN
++};
++
++#define	ODM_MGN_MCS0_SG		0xc0
++#define	ODM_MGN_MCS1_SG		0xc1
++#define	ODM_MGN_MCS2_SG		0xc2
++#define	ODM_MGN_MCS3_SG		0xc3
++#define	ODM_MGN_MCS4_SG		0xc4
++#define	ODM_MGN_MCS5_SG		0xc5
++#define	ODM_MGN_MCS6_SG		0xc6
++#define	ODM_MGN_MCS7_SG		0xc7
++#define	ODM_MGN_MCS8_SG		0xc8
++#define	ODM_MGN_MCS9_SG		0xc9
++#define	ODM_MGN_MCS10_SG	0xca
++#define	ODM_MGN_MCS11_SG	0xcb
++#define	ODM_MGN_MCS12_SG	0xcc
++#define	ODM_MGN_MCS13_SG	0xcd
++#define	ODM_MGN_MCS14_SG	0xce
++#define	ODM_MGN_MCS15_SG	0xcf
++
++/* @-----DESC rate--------------------------------- */
++
++#define ODM_RATEMCS15_SG	0x1c
++#define ODM_RATEMCS32		0x20
++
++enum phydm_ctrl_info_rate {
++	ODM_RATE1M		= 0x00,
++	ODM_RATE2M		= 0x01,
++	ODM_RATE5_5M		= 0x02,
++	ODM_RATE11M		= 0x03,
++/* OFDM Rates, TxHT = 0 */
++	ODM_RATE6M		= 0x04,
++	ODM_RATE9M		= 0x05,
++	ODM_RATE12M		= 0x06,
++	ODM_RATE18M		= 0x07,
++	ODM_RATE24M		= 0x08,
++	ODM_RATE36M		= 0x09,
++	ODM_RATE48M		= 0x0A,
++	ODM_RATE54M		= 0x0B,
++/* @MCS Rates, TxHT = 1 */
++	ODM_RATEMCS0		= 0x0C,
++	ODM_RATEMCS1		= 0x0D,
++	ODM_RATEMCS2		= 0x0E,
++	ODM_RATEMCS3		= 0x0F,
++	ODM_RATEMCS4		= 0x10,
++	ODM_RATEMCS5		= 0x11,
++	ODM_RATEMCS6		= 0x12,
++	ODM_RATEMCS7		= 0x13,
++	ODM_RATEMCS8		= 0x14,
++	ODM_RATEMCS9		= 0x15,
++	ODM_RATEMCS10		= 0x16,
++	ODM_RATEMCS11		= 0x17,
++	ODM_RATEMCS12		= 0x18,
++	ODM_RATEMCS13		= 0x19,
++	ODM_RATEMCS14		= 0x1A,
++	ODM_RATEMCS15		= 0x1B,
++	ODM_RATEMCS16		= 0x1C,
++	ODM_RATEMCS17		= 0x1D,
++	ODM_RATEMCS18		= 0x1E,
++	ODM_RATEMCS19		= 0x1F,
++	ODM_RATEMCS20		= 0x20,
++	ODM_RATEMCS21		= 0x21,
++	ODM_RATEMCS22		= 0x22,
++	ODM_RATEMCS23		= 0x23,
++	ODM_RATEMCS24		= 0x24,
++	ODM_RATEMCS25		= 0x25,
++	ODM_RATEMCS26		= 0x26,
++	ODM_RATEMCS27		= 0x27,
++	ODM_RATEMCS28		= 0x28,
++	ODM_RATEMCS29		= 0x29,
++	ODM_RATEMCS30		= 0x2A,
++	ODM_RATEMCS31		= 0x2B,
++	ODM_RATEVHTSS1MCS0	= 0x2C,
++	ODM_RATEVHTSS1MCS1	= 0x2D,
++	ODM_RATEVHTSS1MCS2	= 0x2E,
++	ODM_RATEVHTSS1MCS3	= 0x2F,
++	ODM_RATEVHTSS1MCS4	= 0x30,
++	ODM_RATEVHTSS1MCS5	= 0x31,
++	ODM_RATEVHTSS1MCS6	= 0x32,
++	ODM_RATEVHTSS1MCS7	= 0x33,
++	ODM_RATEVHTSS1MCS8	= 0x34,
++	ODM_RATEVHTSS1MCS9	= 0x35,
++	ODM_RATEVHTSS2MCS0	= 0x36,
++	ODM_RATEVHTSS2MCS1	= 0x37,
++	ODM_RATEVHTSS2MCS2	= 0x38,
++	ODM_RATEVHTSS2MCS3	= 0x39,
++	ODM_RATEVHTSS2MCS4	= 0x3A,
++	ODM_RATEVHTSS2MCS5	= 0x3B,
++	ODM_RATEVHTSS2MCS6	= 0x3C,
++	ODM_RATEVHTSS2MCS7	= 0x3D,
++	ODM_RATEVHTSS2MCS8	= 0x3E,
++	ODM_RATEVHTSS2MCS9	= 0x3F,
++	ODM_RATEVHTSS3MCS0	= 0x40,
++	ODM_RATEVHTSS3MCS1	= 0x41,
++	ODM_RATEVHTSS3MCS2	= 0x42,
++	ODM_RATEVHTSS3MCS3	= 0x43,
++	ODM_RATEVHTSS3MCS4	= 0x44,
++	ODM_RATEVHTSS3MCS5	= 0x45,
++	ODM_RATEVHTSS3MCS6	= 0x46,
++	ODM_RATEVHTSS3MCS7	= 0x47,
++	ODM_RATEVHTSS3MCS8	= 0x48,
++	ODM_RATEVHTSS3MCS9	= 0x49,
++	ODM_RATEVHTSS4MCS0	= 0x4A,
++	ODM_RATEVHTSS4MCS1	= 0x4B,
++	ODM_RATEVHTSS4MCS2	= 0x4C,
++	ODM_RATEVHTSS4MCS3	= 0x4D,
++	ODM_RATEVHTSS4MCS4	= 0x4E,
++	ODM_RATEVHTSS4MCS5	= 0x4F,
++	ODM_RATEVHTSS4MCS6	= 0x50,
++	ODM_RATEVHTSS4MCS7	= 0x51,
++	ODM_RATEVHTSS4MCS8	= 0x52,
++	ODM_RATEVHTSS4MCS9	= 0x53,
++};
++
++enum phydm_legacy_spec_rate {
++	PHYDM_SPEC_RATE_6M	= 0xb,
++	PHYDM_SPEC_RATE_9M	= 0xf,
++	PHYDM_SPEC_RATE_12M	= 0xa,
++	PHYDM_SPEC_RATE_18M	= 0xe,
++	PHYDM_SPEC_RATE_24M	= 0x9,
++	PHYDM_SPEC_RATE_36M	= 0xd,
++	PHYDM_SPEC_RATE_48M	= 0x8,
++	PHYDM_SPEC_RATE_54M	= 0xc
++};
++
++#define NUM_RATE_AC_4SS (ODM_RATEVHTSS4MCS9 + 1)
++#define NUM_RATE_AC_3SS (ODM_RATEVHTSS3MCS9 + 1)
++#define NUM_RATE_AC_2SS (ODM_RATEVHTSS2MCS9 + 1)
++#define NUM_RATE_AC_1SS (ODM_RATEVHTSS1MCS9 + 1)
++#define NUM_RATE_N_4SS (ODM_RATEMCS31 + 1)
++#define NUM_RATE_N_3SS (ODM_RATEMCS23 + 1)
++#define NUM_RATE_N_2SS (ODM_RATEMCS15 + 1)
++#define NUM_RATE_N_1SS (ODM_RATEMCS7 + 1)
++
++/*Define from larger rate size to small rate size, DO NOT change the position*/
++/*[AC-4SS]*/
++#if (RTL8814B_SUPPORT)
++	#define PHY_NUM_RATE_IDX NUM_RATE_AC_4SS
++/*[AC-3SS]*/
++#elif (RTL8814A_SUPPORT)
++	#define PHY_NUM_RATE_IDX NUM_RATE_AC_3SS
++/*[AC-2SS]*/
++#elif (RTL8812A_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\
++	RTL8812F_SUPPORT)
++	#define PHY_NUM_RATE_IDX NUM_RATE_AC_2SS
++/*[AC-1SS]*/
++#elif (RTL8881A_SUPPORT || RTL8821A_SUPPORT || RTL8821C_SUPPORT ||\
++	RTL8195B_SUPPORT)
++	#define PHY_NUM_RATE_IDX NUM_RATE_AC_1SS
++/*[N-4SS]*/
++#elif (RTL8198F_SUPPORT)
++	#define PHY_NUM_RATE_IDX NUM_RATE_N_4SS
++/*[N-2SS]*/
++#elif (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\
++	RTL8197G_SUPPORT)
++	#define PHY_NUM_RATE_IDX NUM_RATE_N_2SS
++/*[N-1SS]*/
++#elif (RTL8723B_SUPPORT || RTL8703B_SUPPORT || RTL8188E_SUPPORT || \
++	RTL8188F_SUPPORT || RTL8723D_SUPPORT || RTL8195A_SUPPORT ||\
++	RTL8710B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
++	#define PHY_NUM_RATE_IDX NUM_RATE_N_1SS
++#else
++	#define PHY_NUM_RATE_IDX NUM_RATE_AC_4SS
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	#define CONFIG_SFW_SUPPORTED
++#endif
++
++/****************************************************************
++ * 1 ============================================================
++ * 1  enumeration
++ * 1 ============================================================
++ ***************************************************************/
++
++/*	ODM_CMNINFO_INTERFACE */
++enum odm_interface {
++	ODM_ITRF_PCIE	=	0x1,
++	ODM_ITRF_USB	=	0x2,
++	ODM_ITRF_SDIO	=	0x4,
++	ODM_ITRF_ALL	=	0x7,
++};
++
++enum phydm_api_host {
++	RUN_IN_FW		= 0,
++	RUN_IN_DRIVER		= 1,
++};
++
++/*@========[Run time IC flag] ===================================*/
++
++enum phydm_ic {
++	ODM_RTL8188E	=	BIT(0),
++	ODM_RTL8812	=	BIT(1),
++	ODM_RTL8821	=	BIT(2),
++	ODM_RTL8192E	=	BIT(3),
++	ODM_RTL8723B	=	BIT(4),
++	ODM_RTL8814A	=	BIT(5),
++	ODM_RTL8881A	=	BIT(6),
++	ODM_RTL8822B	=	BIT(7),
++	ODM_RTL8703B	=	BIT(8),
++	ODM_RTL8195A	=	BIT(9),
++	ODM_RTL8188F	=	BIT(10),
++	ODM_RTL8723D	=	BIT(11),
++	ODM_RTL8197F	=	BIT(12),
++	ODM_RTL8821C	=	BIT(13),
++	ODM_RTL8814B	=	BIT(14),
++	ODM_RTL8198F	=	BIT(15),
++	ODM_RTL8710B	=	BIT(16),
++	ODM_RTL8192F	=	BIT(17),
++	ODM_RTL8822C	=	BIT(18),
++	ODM_RTL8195B	=	BIT(19),
++	ODM_RTL8812F	=	BIT(20),
++	ODM_RTL8197G	=	BIT(21),
++	ODM_RTL8721D	=	BIT(22),
++	ODM_RTL8710C	=	BIT(23)	
++};
++
++#define ODM_IC_N_1SS		(ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B |\
++				 ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8195A |\
++				 ODM_RTL8710B | ODM_RTL8721D | ODM_RTL8710C)
++#define ODM_IC_N_2SS		(ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F)
++#define ODM_IC_N_3SS		0
++#define ODM_IC_N_4SS		0
++
++#define ODM_IC_AC_1SS		(ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C |\
++				 ODM_RTL8195B)
++#define ODM_IC_AC_2SS		(ODM_RTL8812 | ODM_RTL8822B)
++#define ODM_IC_AC_3SS		0
++#define ODM_IC_AC_4SS		(ODM_RTL8814A)
++
++#define ODM_IC_JGR3_1SS		0
++#define ODM_IC_JGR3_2SS		(ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)
++#define ODM_IC_JGR3_3SS		0
++#define ODM_IC_JGR3_4SS		(ODM_RTL8198F | ODM_RTL8814B)
++
++/*@====the following macro DO NOT need to update when adding a new IC======= */
++#define ODM_IC_1SS		(ODM_IC_N_1SS | ODM_IC_AC_1SS | ODM_IC_JGR3_1SS)
++#define ODM_IC_2SS		(ODM_IC_N_2SS | ODM_IC_AC_2SS | ODM_IC_JGR3_2SS)
++#define ODM_IC_3SS		(ODM_IC_N_3SS | ODM_IC_AC_3SS | ODM_IC_JGR3_3SS)
++#define ODM_IC_4SS		(ODM_IC_N_4SS | ODM_IC_AC_4SS | ODM_IC_JGR3_4SS)
++
++#define PHYDM_IC_ABOVE_1SS	(ODM_IC_1SS | ODM_IC_2SS | ODM_IC_3SS |\
++				 ODM_IC_4SS)
++#define PHYDM_IC_ABOVE_2SS	(ODM_IC_2SS | ODM_IC_3SS | ODM_IC_4SS)
++#define PHYDM_IC_ABOVE_3SS	(ODM_IC_3SS | ODM_IC_4SS)
++#define PHYDM_IC_ABOVE_4SS	ODM_IC_4SS
++
++#define ODM_IC_11N_SERIES	(ODM_IC_N_1SS | ODM_IC_N_2SS | ODM_IC_N_3SS |\
++				 ODM_IC_N_4SS)
++#define ODM_IC_11AC_SERIES	(ODM_IC_AC_1SS | ODM_IC_AC_2SS |\
++				 ODM_IC_AC_3SS | ODM_IC_AC_4SS)
++#define ODM_IC_JGR3_SERIES	(ODM_IC_JGR3_1SS | ODM_IC_JGR3_2SS |\
++				 ODM_IC_JGR3_3SS | ODM_IC_JGR3_4SS)
++/*@====================================================*/
++
++#define ODM_IC_11AC_1_SERIES	(ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)
++#define ODM_IC_11AC_2_SERIES	(ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C |\
++				 ODM_RTL8195B)
++
++/*@[Phy status type]*/
++#define PHYSTS_2ND_TYPE_IC	(ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D |\
++				 ODM_RTL8821C | ODM_RTL8710B | ODM_RTL8195B |\
++				 ODM_RTL8192F | ODM_RTL8721D | ODM_RTL8710C)
++#define PHYSTS_3RD_TYPE_IC	(ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8822C |\
++				 ODM_RTL8812F | ODM_RTL8197G)
++/*@[FW Type]*/
++#define PHYDM_IC_8051_SERIES	(ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 |\
++				 ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B |\
++				 ODM_RTL8188F | ODM_RTL8192F | ODM_RTL8721D |\
++				 ODM_RTL8710C)
++#define PHYDM_IC_3081_SERIES	(ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\
++				 ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\
++				 ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8814B |\
++				 ODM_RTL8197G)
++/*@[LA mode]*/
++#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\
++				  ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\
++				  ODM_RTL8192F | ODM_RTL8822C | ODM_RTL8812F |\
++				  ODM_RTL8195B | ODM_RTL8814B | ODM_RTL8197G)
++/*@[BF]*/
++#define ODM_IC_TXBF_SUPPORT	(ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 |\
++				 ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B |\
++				 ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8195B |\
++				 ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |\
++				 ODM_RTL8814B | ODM_RTL8197G)
++#define PHYDM_IC_SUPPORT_MU_BFEE (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814B |\
++				  ODM_RTL8195B | ODM_RTL8198F | ODM_RTL8822C |\
++				  ODM_RTL8812F)
++#define PHYDM_IC_SUPPORT_MU_BFER (ODM_RTL8822B | ODM_RTL8814B | ODM_RTL8198F |\
++				  ODM_RTL8822C | ODM_RTL8812F)
++
++#define PHYDM_IC_SUPPORT_MU (PHYDM_IC_SUPPORT_MU_BFEE |\
++				PHYDM_IC_SUPPORT_MU_BFER)
++/*@[PHYDM API]*/
++#define CMN_API_SUPPORT_IC (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F |\
++			    ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\
++			    ODM_RTL8198F | ODM_RTL8812F | ODM_RTL8814B |\
++			    ODM_RTL8197G | ODM_RTL8721D | ODM_RTL8710C)
++
++/* fw offload ability*/
++#define PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD (ODM_RTL8814A | ODM_RTL8822B |\
++					   ODM_RTL8821C | ODM_RTL8822C)
++
++/*@========[Compile time IC flag] ========================*/
++/*@========[AC-3/AC/N Support] ===========================*/
++
++#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
++	RTL8812F_SUPPORT || RTL8197G_SUPPORT)
++	#define PHYDM_IC_JGR3_SERIES_SUPPORT
++	#if (RTL8814B_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT)
++		#define PHYDM_IC_JGR3_80M_SUPPORT
++	#endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++
++	#ifdef RTK_AC_SUPPORT
++	#define ODM_IC_11AC_SERIES_SUPPORT	1
++	#else
++	#define ODM_IC_11AC_SERIES_SUPPORT	0
++	#endif
++
++	#define ODM_IC_11N_SERIES_SUPPORT	1
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++
++	#define ODM_IC_11AC_SERIES_SUPPORT	1
++	#define ODM_IC_11N_SERIES_SUPPORT	1
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
++
++	#define ODM_IC_11AC_SERIES_SUPPORT	1
++	#define ODM_IC_11N_SERIES_SUPPORT	1
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++
++	#define ODM_IC_11AC_SERIES_SUPPORT		1
++	#define ODM_IC_11N_SERIES_SUPPORT			1
++
++#else /*ODM_CE*/
++
++	#if (RTL8188E_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\
++	     RTL8195A_SUPPORT || RTL8703B_SUPPORT || RTL8188F_SUPPORT ||\
++	     RTL8723D_SUPPORT || RTL8197F_SUPPORT || RTL8710B_SUPPORT ||\
++	     RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
++		#define ODM_IC_11N_SERIES_SUPPORT	1
++		#define ODM_IC_11AC_SERIES_SUPPORT	0
++	#else
++		#define ODM_IC_11N_SERIES_SUPPORT	0
++		#define ODM_IC_11AC_SERIES_SUPPORT	1
++	#endif
++#endif
++
++/*@===IC SS Compile Flag, prepare for code size reduction==============*/
++#if (RTL8188E_SUPPORT || RTL8188F_SUPPORT || RTL8723B_SUPPORT ||\
++	RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8881A_SUPPORT ||\
++	RTL8821A_SUPPORT || RTL8821C_SUPPORT || RTL8195A_SUPPORT ||\
++	RTL8710B_SUPPORT || RTL8195B_SUPPORT || RTL8721D_SUPPORT ||\
++	RTL8710C_SUPPORT)
++
++	#define PHYDM_COMPILE_IC_1SS
++#endif
++
++#if (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8812A_SUPPORT ||\
++	RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8822C_SUPPORT ||\
++	RTL8812F_SUPPORT || RTL8197G_SUPPORT)
++	#define PHYDM_COMPILE_IC_2SS
++#endif
++
++/*@#define PHYDM_COMPILE_IC_3SS*/
++
++#if ((RTL8814B_SUPPORT) || (RTL8814A_SUPPORT) || (RTL8198F_SUPPORT))
++	#define PHYDM_COMPILE_IC_4SS
++#endif
++
++/*@==[ABOVE N-SS COMPILE FLAG]=================================================*/
++#if (defined(PHYDM_COMPILE_IC_1SS) || defined(PHYDM_COMPILE_IC_2SS) ||\
++	defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS))
++	#define PHYDM_COMPILE_ABOVE_1SS
++#endif
++
++#if (defined(PHYDM_COMPILE_IC_2SS) || defined(PHYDM_COMPILE_IC_3SS) ||\
++	defined(PHYDM_COMPILE_IC_4SS))
++	#define PHYDM_COMPILE_ABOVE_2SS
++#endif
++
++#if (defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS))
++	#define PHYDM_COMPILE_ABOVE_3SS
++#endif
++
++#if (defined(PHYDM_COMPILE_IC_4SS))
++	#define PHYDM_COMPILE_ABOVE_4SS
++#endif
++
++/*@==[Max RF path number among all compiled ICs]==============================*/
++/*@ ex: support 8814B & 8821C => size=4 */
++/*@ ex: support 8822C & 8821C => size=2 */
++#if (defined(PHYDM_COMPILE_IC_4SS))
++	#define RF_PATH_MEM_SIZE 4
++#elif (defined(PHYDM_COMPILE_IC_3SS))
++	#define RF_PATH_MEM_SIZE 3
++#elif (defined(PHYDM_COMPILE_IC_2SS))
++	#define RF_PATH_MEM_SIZE 2
++#else
++	#define RF_PATH_MEM_SIZE 1
++#endif
++
++/*@========[New Phy-Status Support] ========================*/
++#if (RTL8197F_SUPPORT || RTL8723D_SUPPORT || RTL8822B_SUPPORT ||\
++	RTL8821C_SUPPORT || RTL8710B_SUPPORT || RTL8195B_SUPPORT ||\
++	RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
++	#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT			1
++#else
++	#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT			0
++#endif
++
++#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8822C_SUPPORT ||\
++	RTL8812F_SUPPORT || RTL8197G_SUPPORT)
++	#define PHYSTS_3RD_TYPE_SUPPORT
++#endif
++
++#ifdef PHYSTS_3RD_TYPE_SUPPORT
++	#define PHYSTS_AUTO_SWITCH_IC (ODM_RTL8822C)
++#endif
++
++#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8822C_SUPPORT ||\
++	RTL8812F_SUPPORT || RTL8197G_SUPPORT)
++	#define BB_RAM_SUPPORT
++#endif
++
++#if (RTL8821C_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\
++	RTL8812F_SUPPORT || RTL8814B_SUPPORT || RTL8195B_SUPPORT ||\
++	RTL8198F_SUPPORT)
++	#define PHYDM_COMPILE_MU
++#endif
++
++#if (RTL8822B_SUPPORT)
++	#define CONFIG_MU_JAGUAR_2
++#endif
++
++#if (RTL8814B_SUPPORT || RTL8822C_SUPPORT  || RTL8812F_SUPPORT)
++	#define CONFIG_MU_JAGUAR_3
++#endif
++
++#if (defined(CONFIG_MU_JAGUAR_2) || defined(CONFIG_MU_JAGUAR_3))
++	#if (RTL8814B_SUPPORT)
++		#define MU_EX_MACID		76
++	#elif (RTL8822B_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT)
++		#define MU_EX_MACID		30
++	#endif
++#endif
++/*@============================================================================*/
++
++#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\
++	RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8822C_SUPPORT ||\
++	RTL8198F_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\
++	RTL8197G_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
++#define PHYDM_COMMON_API_SUPPORT
++#endif
++
++#if (RTL8821C_SUPPORT || RTL8197F_SUPPORT || RTL8197G_SUPPORT)
++	#define CONFIG_RFE_BY_HW_INFO
++#endif
++
++#define	CCK_RATE_NUM		4
++#define	OFDM_RATE_NUM		8
++
++#define	LEGACY_RATE_NUM		12
++
++#define	HT_RATE_NUM_4SS		32
++#define	VHT_RATE_NUM_4SS	40
++
++#define	HT_RATE_NUM_3SS		24
++#define	VHT_RATE_NUM_3SS	30
++
++#define	HT_RATE_NUM_2SS		16
++#define	VHT_RATE_NUM_2SS	20
++
++#define	HT_RATE_NUM_1SS		8
++#define	VHT_RATE_NUM_1SS	10
++#if (defined(PHYDM_COMPILE_ABOVE_4SS))
++	#define	HT_RATE_NUM	HT_RATE_NUM_4SS
++	#define	VHT_RATE_NUM	VHT_RATE_NUM_4SS
++#elif (defined(PHYDM_COMPILE_ABOVE_3SS))
++	#define	HT_RATE_NUM	HT_RATE_NUM_3SS
++	#define	VHT_RATE_NUM	VHT_RATE_NUM_3SS
++#elif (defined(PHYDM_COMPILE_ABOVE_2SS))
++	#define	HT_RATE_NUM	HT_RATE_NUM_2SS
++	#define	VHT_RATE_NUM	VHT_RATE_NUM_2SS
++#else
++	#define	HT_RATE_NUM	HT_RATE_NUM_1SS
++	#define	VHT_RATE_NUM	VHT_RATE_NUM_1SS
++#endif
++
++#define	LOW_BW_RATE_NUM		VHT_RATE_NUM
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++#define	SECOND_CH_AT_LSB	2	/*@primary CH @ MSB,  SD4: HAL_PRIME_CHNL_OFFSET_UPPER*/
++#define	SECOND_CH_AT_USB	1	/*@primary CH @ LSB,   SD4: HAL_PRIME_CHNL_OFFSET_LOWER*/
++#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++#define	SECOND_CH_AT_LSB	2	/*@primary CH @ MSB,  SD7: HAL_PRIME_CHNL_OFFSET_UPPER*/
++#define	SECOND_CH_AT_USB	1	/*@primary CH @ LSB,   SD7: HAL_PRIME_CHNL_OFFSET_LOWER*/
++#else /*if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/
++#define	SECOND_CH_AT_LSB	1	/*@primary CH @ MSB,  SD8: HT_2NDCH_OFFSET_BELOW*/
++#define	SECOND_CH_AT_USB	2	/*@primary CH @ LSB,   SD8: HT_2NDCH_OFFSET_ABOVE*/
++#endif
++
++enum phydm_ic_ip {
++	PHYDM_IC_N		= 0,
++	PHYDM_IC_AC		= 1,
++	PHYDM_IC_JGR3		= 2
++};
++
++enum phydm_phy_sts_type {
++	PHYDM_PHYSTS_TYPE_1	= 1,
++	PHYDM_PHYSTS_TYPE_2	= 2,
++	PHYDM_PHYSTS_TYPE_3	= 3
++};
++
++/* ODM_CMNINFO_CUT_VER */
++enum odm_cut_version {
++	ODM_CUT_A		= 0,
++	ODM_CUT_B		= 1,
++	ODM_CUT_C		= 2,
++	ODM_CUT_D		= 3,
++	ODM_CUT_E		= 4,
++	ODM_CUT_F		= 5,
++	ODM_CUT_G		= 6,
++	ODM_CUT_H		= 7,
++	ODM_CUT_I		= 8,
++	ODM_CUT_J		= 9,
++	ODM_CUT_K		= 10,
++	ODM_CUT_L		= 11,
++	ODM_CUT_M		= 12,
++	ODM_CUT_N		= 13,
++	ODM_CUT_O		= 14,
++	ODM_CUT_TEST		= 15,
++};
++
++/* ODM_CMNINFO_FAB_VER */
++enum odm_fab {
++	ODM_TSMC		= 0,
++	ODM_UMC			= 1,
++};
++
++/* ODM_CMNINFO_OP_MODE */
++enum odm_operation_mode {
++	ODM_NO_LINK		= BIT(0),
++	ODM_LINK		= BIT(1),
++	ODM_SCAN		= BIT(2),
++	ODM_POWERSAVE		= BIT(3),
++	ODM_AP_MODE		= BIT(4),
++	ODM_CLIENT_MODE		= BIT(5),
++	ODM_AD_HOC		= BIT(6),
++	ODM_WIFI_DIRECT		= BIT(7),
++	ODM_WIFI_DISPLAY	= BIT(8),
++};
++
++/* ODM_CMNINFO_WM_MODE */
++#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
++enum odm_wireless_mode {
++	ODM_WM_UNKNOW		= 0x0,
++	ODM_WM_B		= BIT(0),
++	ODM_WM_G		= BIT(1),
++	ODM_WM_A		= BIT(2),
++	ODM_WM_N24G		= BIT(3),
++	ODM_WM_N5G		= BIT(4),
++	ODM_WM_AUTO		= BIT(5),
++	ODM_WM_AC		= BIT(6),
++};
++#else
++enum odm_wireless_mode {
++	ODM_WM_UNKNOWN		= 0x00,/*@0x0*/
++	ODM_WM_A		= BIT(0), /* @0x1*/
++	ODM_WM_B		= BIT(1), /* @0x2*/
++	ODM_WM_G		= BIT(2),/* @0x4*/
++	ODM_WM_AUTO		= BIT(3),/* @0x8*/
++	ODM_WM_N24G		= BIT(4),/* @0x10*/
++	ODM_WM_N5G		= BIT(5),/* @0x20*/
++	ODM_WM_AC_5G		= BIT(6),/* @0x40*/
++	ODM_WM_AC_24G		= BIT(7),/* @0x80*/
++	ODM_WM_AC_ONLY		= BIT(8),/* @0x100*/
++	ODM_WM_MAX		= BIT(11)/* @0x800*/
++
++};
++#endif
++
++/* ODM_CMNINFO_BAND */
++enum odm_band_type {
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	ODM_BAND_2_4G		= BIT(0),
++	ODM_BAND_5G		= BIT(1),
++#else
++	ODM_BAND_2_4G		= 0,
++	ODM_BAND_5G,
++	ODM_BAND_ON_BOTH,
++	ODM_BANDMAX
++#endif
++};
++
++/* ODM_CMNINFO_SEC_CHNL_OFFSET */
++enum phydm_sec_chnl_offset {
++	PHYDM_DONT_CARE		= 0,
++	PHYDM_BELOW		= 1,
++	PHYDM_ABOVE		= 2
++};
++
++/* ODM_CMNINFO_SEC_MODE */
++enum odm_security {
++	ODM_SEC_OPEN		= 0,
++	ODM_SEC_WEP40		= 1,
++	ODM_SEC_TKIP		= 2,
++	ODM_SEC_RESERVE		= 3,
++	ODM_SEC_AESCCMP		= 4,
++	ODM_SEC_WEP104		= 5,
++	ODM_WEP_WPA_MIXED	= 6, /* WEP + WPA */
++	ODM_SEC_SMS4		= 7,
++};
++
++/* ODM_CMNINFO_CHNL */
++
++/* ODM_CMNINFO_BOARD_TYPE */
++enum odm_board_type {
++	ODM_BOARD_DEFAULT	= 0,	  /* The DEFAULT case. */
++	ODM_BOARD_MINICARD	= BIT(0), /* @0 = non-mini card, 1= mini card. */
++	ODM_BOARD_SLIM		= BIT(1), /* @0 = non-slim card, 1 = slim card */
++	ODM_BOARD_BT		= BIT(2), /* @0 = without BT card, 1 = with BT */
++	ODM_BOARD_EXT_PA	= BIT(3), /* @0 = no 2G ext-PA, 1 = existing 2G ext-PA */
++	ODM_BOARD_EXT_LNA	= BIT(4), /* @0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */
++	ODM_BOARD_EXT_TRSW	= BIT(5), /* @0 = no ext-TRSW, 1 = existing ext-TRSW */
++	ODM_BOARD_EXT_PA_5G	= BIT(6), /* @0 = no 5G ext-PA, 1 = existing 5G ext-PA */
++	ODM_BOARD_EXT_LNA_5G	= BIT(7), /* @0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */
++};
++
++enum odm_package_type {
++	ODM_PACKAGE_DEFAULT	= 0,
++	ODM_PACKAGE_QFN68	= BIT(0),
++	ODM_PACKAGE_TFBGA90	= BIT(1),
++	ODM_PACKAGE_TFBGA79	= BIT(2),
++};
++
++enum odm_type_gpa {
++	TYPE_GPA0		= 0x0000,
++	TYPE_GPA1		= 0x0055,
++	TYPE_GPA2		= 0x00AA,
++	TYPE_GPA3		= 0x00FF,
++	TYPE_GPA4		= 0x5500,
++	TYPE_GPA5		= 0x5555,
++	TYPE_GPA6		= 0x55AA,
++	TYPE_GPA7		= 0x55FF,
++	TYPE_GPA8		= 0xAA00,
++	TYPE_GPA9		= 0xAA55,
++	TYPE_GPA10		= 0xAAAA,
++	TYPE_GPA11		= 0xAAFF,
++	TYPE_GPA12		= 0xFF00,
++	TYPE_GPA13		= 0xFF55,
++	TYPE_GPA14		= 0xFFAA,
++	TYPE_GPA15		= 0xFFFF,
++};
++
++enum odm_type_apa {
++	TYPE_APA0		= 0x0000,
++	TYPE_APA1		= 0x0055,
++	TYPE_APA2		= 0x00AA,
++	TYPE_APA3		= 0x00FF,
++	TYPE_APA4		= 0x5500,
++	TYPE_APA5		= 0x5555,
++	TYPE_APA6		= 0x55AA,
++	TYPE_APA7		= 0x55FF,
++	TYPE_APA8		= 0xAA00,
++	TYPE_APA9		= 0xAA55,
++	TYPE_APA10		= 0xAAAA,
++	TYPE_APA11		= 0xAAFF,
++	TYPE_APA12		= 0xFF00,
++	TYPE_APA13		= 0xFF55,
++	TYPE_APA14		= 0xFFAA,
++	TYPE_APA15		= 0xFFFF,
++};
++
++enum odm_type_glna {
++	TYPE_GLNA0		= 0x0000,
++	TYPE_GLNA1		= 0x0055,
++	TYPE_GLNA2		= 0x00AA,
++	TYPE_GLNA3		= 0x00FF,
++	TYPE_GLNA4		= 0x5500,
++	TYPE_GLNA5		= 0x5555,
++	TYPE_GLNA6		= 0x55AA,
++	TYPE_GLNA7		= 0x55FF,
++	TYPE_GLNA8		= 0xAA00,
++	TYPE_GLNA9		= 0xAA55,
++	TYPE_GLNA10		= 0xAAAA,
++	TYPE_GLNA11		= 0xAAFF,
++	TYPE_GLNA12		= 0xFF00,
++	TYPE_GLNA13		= 0xFF55,
++	TYPE_GLNA14		= 0xFFAA,
++	TYPE_GLNA15		= 0xFFFF,
++};
++
++enum odm_type_alna {
++	TYPE_ALNA0		= 0x0000,
++	TYPE_ALNA1		= 0x0055,
++	TYPE_ALNA2		= 0x00AA,
++	TYPE_ALNA3		= 0x00FF,
++	TYPE_ALNA4		= 0x5500,
++	TYPE_ALNA5		= 0x5555,
++	TYPE_ALNA6		= 0x55AA,
++	TYPE_ALNA7		= 0x55FF,
++	TYPE_ALNA8		= 0xAA00,
++	TYPE_ALNA9		= 0xAA55,
++	TYPE_ALNA10		= 0xAAAA,
++	TYPE_ALNA11		= 0xAAFF,
++	TYPE_ALNA12		= 0xFF00,
++	TYPE_ALNA13		= 0xFF55,
++	TYPE_ALNA14		= 0xFFAA,
++	TYPE_ALNA15		= 0xFFFF,
++};
++
++#if (RTL8721D_SUPPORT)
++/* ODM_CMNINFO_POWER_VOLTAGE */
++enum odm_power_voltage {
++	ODM_POWER_18V		= 0,
++	ODM_POWER_33V		= 1,
++};
++
++/* ODM_CMNINFO_ANTDIV_GPIO */
++enum odm_antdiv_gpio {
++	ANTDIV_GPIO_PA2PA4	= 0,
++	ANTDIV_GPIO_PA5PA6	= 1,
++	ANTDIV_GPIO_PA12PA13	= 2,
++	ANTDIV_GPIO_PA14PA15	= 3,
++	ANTDIV_GPIO_PA16PA17	= 4,
++	ANTDIV_GPIO_PB1PB2	= 5,
++	ANTDIV_GPIO_PB26PB29	= 6,
++};
++
++/* ODM_CMNINFO_PEAK_DETECT_MODE */
++enum odm_peak_detect_mode {
++	ODM_PD_DIS		= 0,
++	ODM_PD_ENG		= 1,
++	ODM_PD_ENA		= 2,
++	ODM_PD_ENALL		= 3,
++};
++#endif
++
++#define	PAUSE_FAIL		0
++#define	PAUSE_SUCCESS		1
++
++enum odm_parameter_init {
++	ODM_PRE_SETTING		= 0,
++	ODM_POST_SETTING	= 1,
++	ODM_INIT_FW_SETTING	= 2,
++	ODM_PRE_RF_SET		= 3,
++	ODM_POST_RF_SET		= 4
++};
++
++enum phydm_pause_type {
++	PHYDM_PAUSE		= 1,	/*Pause & Set new value*/
++	PHYDM_PAUSE_NO_SET	= 2,	/*Pause & Stay in current value*/
++	PHYDM_RESUME		= 3
++};
++
++enum phydm_backup_type {
++	PHYDM_BACKUP	= 1,
++	PHYDM_RESTORE	= 2
++};
++
++enum phydm_pause_level {
++	PHYDM_PAUSE_RELEASE	= -1,
++	PHYDM_PAUSE_LEVEL_0	= 0,	/* @Low Priority function */
++	PHYDM_PAUSE_LEVEL_1	= 1,	/* @Middle Priority function */
++	PHYDM_PAUSE_LEVEL_2	= 2,	/* @High priority function (ex: Check hang function) */
++	PHYDM_PAUSE_LEVEL_3	= 3,	/* @Debug function (the highest priority) */
++	PHYDM_PAUSE_MAX_NUM	= 4
++};
++
++enum phydm_dis_hw_fun {
++	HW_FUN_DIS		= 0,	/*@Disable a cetain HW function & backup the original value*/
++	HW_FUN_RESUME		= 1	/*Revert */
++};
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_precomp.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_precomp.h
+new file mode 100644
+index 000000000..74b2e160d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_precomp.h
+@@ -0,0 +1,625 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __ODM_PRECOMP_H__
++#define __ODM_PRECOMP_H__
++
++#include "phydm_types.h"
++#include "halrf/halrf_features.h"
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	#include "Precomp.h"		/* @We need to include mp_precomp.h due to batch file setting. */
++#else
++	#define		TEST_FALG___		1
++#endif
++
++/* @2 Config Flags and Structs - defined by each ODM type */
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	#include "../8192cd_cfg.h"
++	#include "../odm_inc.h"
++
++	#include "../8192cd.h"
++	#include "../8192cd_util.h"
++	#include "../8192cd_hw.h"
++	#ifdef _BIG_ENDIAN_
++		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_BIG
++	#else
++		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_LITTLE
++	#endif
++
++	#include "../8192cd_headers.h"
++	#include "../8192cd_debug.h"
++
++	#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
++		#define INIT_TIMER_EVENT_ENTRY(_entry, _func, _data) \
++		do { \
++			_rtw_init_listhead(&(_entry)->list); \
++			(_entry)->data = (_data); \
++			(_entry)->function = (_func); \
++		} while (0)
++	#endif
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	#ifdef DM_ODM_CE_MAC80211
++		#include "../wifi.h"
++		#include "rtl_phydm.h"
++	#elif defined(DM_ODM_CE_MAC80211_V2)
++		#include "../main.h"
++		#include "../hw.h"
++		#include "../fw.h"
++	#endif
++	#define __PACK
++	#define __WLAN_ATTRIB_PACK__
++#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	#include "mp_precomp.h"
++	#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_LITTLE
++	#define __PACK
++	#define __WLAN_ATTRIB_PACK__
++#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
++	#include <drv_types.h>
++	#include <wifi.h>
++	#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_LITTLE
++	#define __PACK
++#endif
++
++/* @2 OutSrc Header Files */
++
++#include "phydm.h"
++#include "phydm_hwconfig.h"
++#include "phydm_phystatus.h"
++#include "phydm_debug.h"
++#include "phydm_regdefine11ac.h"
++#include "phydm_regdefine11n.h"
++#include "phydm_interface.h"
++#include "phydm_reg.h"
++#include "halrf/halrf_debug.h"
++
++#ifndef RTL8188E_SUPPORT
++	#define	RTL8188E_SUPPORT	0
++#endif
++#ifndef RTL8812A_SUPPORT
++	#define	RTL8812A_SUPPORT	0
++#endif
++#ifndef RTL8821A_SUPPORT
++	#define	RTL8821A_SUPPORT	0
++#endif
++#ifndef RTL8192E_SUPPORT
++	#define	RTL8192E_SUPPORT	0
++#endif
++#ifndef RTL8723B_SUPPORT
++	#define	RTL8723B_SUPPORT	0
++#endif
++#ifndef RTL8814A_SUPPORT
++	#define	RTL8814A_SUPPORT	0
++#endif
++#ifndef RTL8881A_SUPPORT
++	#define	RTL8881A_SUPPORT	0
++#endif
++#ifndef RTL8822B_SUPPORT
++	#define	RTL8822B_SUPPORT	0
++#endif
++#ifndef RTL8703B_SUPPORT
++	#define	RTL8703B_SUPPORT	0
++#endif
++#ifndef RTL8195A_SUPPORT
++	#define	RTL8195A_SUPPORT	0
++#endif
++#ifndef RTL8188F_SUPPORT
++	#define	RTL8188F_SUPPORT	0
++#endif
++#ifndef RTL8723D_SUPPORT
++	#define	RTL8723D_SUPPORT	0
++#endif
++#ifndef RTL8197F_SUPPORT
++	#define	RTL8197F_SUPPORT	0
++#endif
++#ifndef RTL8821C_SUPPORT
++	#define	RTL8821C_SUPPORT	0
++#endif
++#ifndef RTL8814B_SUPPORT
++	#define	RTL8814B_SUPPORT	0
++#endif
++#ifndef RTL8198F_SUPPORT
++	#define	RTL8198F_SUPPORT	0
++#endif
++#ifndef RTL8710B_SUPPORT
++	#define	RTL8710B_SUPPORT	0
++#endif
++#ifndef RTL8192F_SUPPORT
++	#define	RTL8192F_SUPPORT	0
++#endif
++#ifndef RTL8822C_SUPPORT
++	#define	RTL8822C_SUPPORT	0
++#endif
++#ifndef RTL8195B_SUPPORT
++	#define	RTL8195B_SUPPORT	0
++#endif
++#ifndef RTL8812F_SUPPORT
++	#define	RTL8812F_SUPPORT	0
++#endif
++#ifndef RTL8197G_SUPPORT
++	#define	RTL8197G_SUPPORT	0
++#endif
++#ifndef RTL8721D_SUPPORT
++	#define	RTL8721D_SUPPORT	0
++#endif
++#ifndef RTL8710C_SUPPORT
++	#define	RTL8710C_SUPPORT	0
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && \
++	(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
++
++void phy_set_tx_power_limit(
++	struct dm_struct *dm,
++	u8 *regulation,
++	u8 *band,
++	u8 *bandwidth,
++	u8 *rate_section,
++	u8 *rf_path,
++	u8 *channel,
++	u8 *power_limit);
++
++void phy_set_tx_power_limit_ex(struct dm_struct *dm, u8 regulation, u8 band,
++			       u8 bandwidth, u8 rate_section, u8 rf_path,
++			       u8 channel, s8 power_limit);
++
++enum hal_status
++rtw_phydm_fw_iqk(
++	struct dm_struct *dm,
++	u8 clear,
++	u8 segment);
++
++enum hal_status
++rtw_phydm_fw_dpk(
++	struct dm_struct *dm);
++
++enum hal_status
++rtw_phydm_cfg_phy_para(
++	struct dm_struct *dm,
++	enum phydm_halmac_param config_type,
++	u32 offset,
++	u32 data,
++	u32 mask,
++	enum rf_path e_rf_path,
++	u32 delay_time);
++
++#endif
++
++#if RTL8188E_SUPPORT == 1
++	#define RTL8188E_T_SUPPORT 1
++	#ifdef CONFIG_SFW_SUPPORTED
++		#define RTL8188E_S_SUPPORT 1
++	#else
++		#define RTL8188E_S_SUPPORT 0
++	#endif
++
++	#include "rtl8188e/hal8188erateadaptive.h" /* @for  RA,Power training */
++	#include "rtl8188e/halhwimg8188e_mac.h"
++	#include "rtl8188e/halhwimg8188e_rf.h"
++	#include "rtl8188e/halhwimg8188e_bb.h"
++	#include "rtl8188e/phydm_regconfig8188e.h"
++	#include "rtl8188e/phydm_rtl8188e.h"
++	#include "rtl8188e/hal8188ereg.h"
++	#include "rtl8188e/version_rtl8188e.h"
++	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#include "rtl8188e_hal.h"
++		#include "halrf/rtl8188e/halrf_8188e_ce.h"
++	#endif
++	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++		#include "halrf/rtl8188e/halrf_8188e_win.h"
++	#endif
++	#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++		#include "halrf/rtl8188e/halrf_8188e_ap.h"
++	#endif
++#endif /* @88E END */
++
++#if (RTL8192E_SUPPORT == 1)
++
++	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++		#include "halrf/rtl8192e/halrf_8192e_win.h" /*@FOR_8192E_IQK*/
++	#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++		#include "halrf/rtl8192e/halrf_8192e_ap.h" /*@FOR_8192E_IQK*/
++	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#include "halrf/rtl8192e/halrf_8192e_ce.h" /*@FOR_8192E_IQK*/
++	#endif
++
++	#include "rtl8192e/phydm_rtl8192e.h" /* @FOR_8192E_IQK */
++	#include "rtl8192e/version_rtl8192e.h"
++	#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
++		#include "rtl8192e/halhwimg8192e_bb.h"
++		#include "rtl8192e/halhwimg8192e_mac.h"
++		#include "rtl8192e/halhwimg8192e_rf.h"
++		#include "rtl8192e/phydm_regconfig8192e.h"
++		#include "rtl8192e/hal8192ereg.h"
++	#endif
++	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#include "rtl8192e_hal.h"
++	#endif
++#endif /* @92E END */
++
++#if (RTL8812A_SUPPORT == 1)
++
++	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++		#include "halrf/rtl8812a/halrf_8812a_win.h"
++	#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++		#include "halrf/rtl8812a/halrf_8812a_ap.h"
++	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#include "halrf/rtl8812a/halrf_8812a_ce.h"
++	#endif
++
++	#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
++		#include "rtl8812a/halhwimg8812a_bb.h"
++		#include "rtl8812a/halhwimg8812a_mac.h"
++		#include "rtl8812a/halhwimg8812a_rf.h"
++		#include "rtl8812a/phydm_regconfig8812a.h"
++	#endif
++	#include "rtl8812a/phydm_rtl8812a.h"
++
++	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#include "rtl8812a_hal.h"
++	#endif
++	#include "rtl8812a/version_rtl8812a.h"
++
++#endif /* @8812 END */
++
++#if (RTL8814A_SUPPORT == 1)
++
++	#include "rtl8814a/halhwimg8814a_mac.h"
++	#include "rtl8814a/halhwimg8814a_bb.h"
++	#include "rtl8814a/version_rtl8814a.h"
++	#include "rtl8814a/phydm_rtl8814a.h"
++	#include "halrf/rtl8814a/halhwimg8814a_rf.h"
++	#include "halrf/rtl8814a/version_rtl8814a_rf.h"
++	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++		#include "halrf/rtl8814a/halrf_8814a_win.h"
++	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#include "halrf/rtl8814a/halrf_8814a_ce.h"
++	#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++		#include "halrf/rtl8814a/halrf_8814a_ap.h"
++	#endif
++	#include "rtl8814a/phydm_regconfig8814a.h"
++	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#include "rtl8814a_hal.h"
++		#include "halrf/rtl8814a/halrf_iqk_8814a.h"
++	#endif
++#endif /* @8814 END */
++
++#if (RTL8881A_SUPPORT == 1)/* @FOR_8881_IQK */
++	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++		#include "halrf/rtl8821a/halrf_iqk_8821a_win.h"
++	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#include "halrf/rtl8821a/halrf_iqk_8821a_ce.h"
++	#else
++		#include "halrf/rtl8821a/halrf_iqk_8821a_ap.h"
++	#endif
++#endif
++
++#if (RTL8723B_SUPPORT == 1)
++	#include "rtl8723b/halhwimg8723b_mac.h"
++	#include "rtl8723b/halhwimg8723b_rf.h"
++	#include "rtl8723b/halhwimg8723b_bb.h"
++	#include "rtl8723b/phydm_regconfig8723b.h"
++	#include "rtl8723b/phydm_rtl8723b.h"
++	#include "rtl8723b/hal8723breg.h"
++	#include "rtl8723b/version_rtl8723b.h"
++	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++		#include "halrf/rtl8723b/halrf_8723b_win.h"
++	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#include "halrf/rtl8723b/halrf_8723b_ce.h"
++		#include "rtl8723b/halhwimg8723b_mp.h"
++		#include "rtl8723b_hal.h"
++	#else
++		#include "halrf/rtl8723b/halrf_8723b_ap.h"
++	#endif
++#endif
++
++#if (RTL8821A_SUPPORT == 1)
++	#include "rtl8821a/halhwimg8821a_mac.h"
++	#include "rtl8821a/halhwimg8821a_rf.h"
++	#include "rtl8821a/halhwimg8821a_bb.h"
++	#include "rtl8821a/phydm_regconfig8821a.h"
++	#include "rtl8821a/phydm_rtl8821a.h"
++	#include "rtl8821a/version_rtl8821a.h"
++	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++		#include "halrf/rtl8821a/halrf_8821a_win.h"
++	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#include "halrf/rtl8821a/halrf_8821a_ce.h"
++		#include "halrf/rtl8821a/halrf_iqk_8821a_ce.h"/*@for IQK*/
++		#include "halrf/rtl8812a/halrf_8812a_ce.h"/*@for IQK,LCK,Power-tracking*/
++		#include "rtl8812a_hal.h"
++	#else
++	#endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
++#include "../halmac/halmac_reg2.h"
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++#include "../halmac/halmac_reg2.h"
++#endif
++
++
++#if (RTL8822B_SUPPORT == 1)
++	#include "rtl8822b/halhwimg8822b_mac.h"
++	#include "rtl8822b/halhwimg8822b_bb.h"
++	#include "rtl8822b/phydm_regconfig8822b.h"
++	#include "halrf/rtl8822b/halrf_8822b.h"
++	#include "halrf/rtl8822b/halhwimg8822b_rf.h"
++	#include "halrf/rtl8822b/version_rtl8822b_rf.h"
++	#include "rtl8822b/phydm_rtl8822b.h"
++	#include "rtl8822b/phydm_hal_api8822b.h"
++	#include "rtl8822b/version_rtl8822b.h"
++
++	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#ifdef DM_ODM_CE_MAC80211
++			#include "../halmac/halmac_reg_8822b.h"
++		#elif defined(DM_ODM_CE_MAC80211_V2)
++			#include "../halmac/halmac_reg_8822b.h"
++		#else
++			#include <hal_data.h>		/* @struct HAL_DATA_TYPE */
++			#include <rtl8822b_hal.h>	/* @RX_SMOOTH_FACTOR, reg definition and etc.*/
++		#endif
++	#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	#endif
++
++#endif
++
++#if (RTL8703B_SUPPORT == 1)
++	#include "rtl8703b/phydm_rtl8703b.h"
++	#include "rtl8703b/phydm_regconfig8703b.h"
++	#include "rtl8703b/halhwimg8703b_mac.h"
++	#include "rtl8703b/halhwimg8703b_rf.h"
++	#include "rtl8703b/halhwimg8703b_bb.h"
++	#include "halrf/rtl8703b/halrf_8703b.h"
++	#include "rtl8703b/version_rtl8703b.h"
++	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#include "rtl8703b_hal.h"
++	#endif
++#endif
++
++#if (RTL8188F_SUPPORT == 1)
++	#include "rtl8188f/halhwimg8188f_mac.h"
++	#include "rtl8188f/halhwimg8188f_rf.h"
++	#include "rtl8188f/halhwimg8188f_bb.h"
++	#include "rtl8188f/hal8188freg.h"
++	#include "rtl8188f/phydm_rtl8188f.h"
++	#include "rtl8188f/phydm_regconfig8188f.h"
++	#include "halrf/rtl8188f/halrf_8188f.h" /*@for IQK,LCK,Power-tracking*/
++	#include "rtl8188f/version_rtl8188f.h"
++	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#include "rtl8188f_hal.h"
++	#endif
++#endif
++
++#if (RTL8723D_SUPPORT == 1)
++	#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
++
++		#include "rtl8723d/halhwimg8723d_bb.h"
++		#include "rtl8723d/halhwimg8723d_mac.h"
++		#include "rtl8723d/halhwimg8723d_rf.h"
++		#include "rtl8723d/phydm_regconfig8723d.h"
++		#include "rtl8723d/hal8723dreg.h"
++		#include "rtl8723d/phydm_rtl8723d.h"
++		#include "halrf/rtl8723d/halrf_8723d.h"
++		#include "rtl8723d/version_rtl8723d.h"
++	#endif
++	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#ifdef DM_ODM_CE_MAC80211
++		#else
++		#include "rtl8723d_hal.h"
++		#endif
++	#endif
++#endif /* @8723D End */
++
++#if (RTL8710B_SUPPORT == 1)
++	#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
++
++		#include "rtl8710b/halhwimg8710b_bb.h"
++		#include "rtl8710b/halhwimg8710b_mac.h"
++		#include "rtl8710b/phydm_regconfig8710b.h"
++		#include "rtl8710b/hal8710breg.h"
++		#include "rtl8710b/phydm_rtl8710b.h"
++		#include "halrf/rtl8710b/halrf_8710b.h"
++		#include "halrf/rtl8710b/halhwimg8710b_rf.h"
++		#include "halrf/rtl8710b/version_rtl8710b_rf.h"
++		#include "rtl8710b/version_rtl8710b.h"
++	#endif
++	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#include "rtl8710b_hal.h"
++	#endif
++#endif /* @8710B End */
++
++#if (RTL8197F_SUPPORT == 1)
++	#include "rtl8197f/halhwimg8197f_mac.h"
++	#include "rtl8197f/halhwimg8197f_bb.h"
++	#include "rtl8197f/phydm_hal_api8197f.h"
++	#include "rtl8197f/version_rtl8197f.h"
++	#include "rtl8197f/phydm_rtl8197f.h"
++	#include "rtl8197f/phydm_regconfig8197f.h"
++	#include "halrf/rtl8197f/halrf_8197f.h"
++	#include "halrf/rtl8197f/halrf_iqk_8197f.h"
++	#include "halrf/rtl8197f/halrf_dpk_8197f.h"
++	#include "halrf/rtl8197f/halhwimg8197f_rf.h"
++	#include "halrf/rtl8197f/version_rtl8197f_rf.h"
++#endif
++
++#if (RTL8821C_SUPPORT == 1)
++	#include "rtl8821c/phydm_hal_api8821c.h"
++	#include "rtl8821c/halhwimg8821c_mac.h"
++	#include "rtl8821c/halhwimg8821c_bb.h"
++	#include "rtl8821c/phydm_regconfig8821c.h"
++	#include "halrf/rtl8821c/halrf_8821c.h"
++	#include "halrf/rtl8821c/halhwimg8821c_rf.h"
++	#include "halrf/rtl8821c/version_rtl8821c_rf.h"
++	#include "rtl8821c/version_rtl8821c.h"
++	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#ifdef DM_ODM_CE_MAC80211
++		#include "../halmac/halmac_reg_8821c.h"
++		#else
++		#include "rtl8821c_hal.h"
++		#endif
++	#endif
++#endif
++
++#if (RTL8192F_SUPPORT == 1)
++	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#include "rtl8192f_hal.h"/*need to before rf.h*/
++	#endif
++	#include "rtl8192f/halhwimg8192f_mac.h"
++	#include "rtl8192f/halhwimg8192f_bb.h"
++	#include "rtl8192f/phydm_hal_api8192f.h"
++	#include "rtl8192f/version_rtl8192f.h"
++	#include "rtl8192f/phydm_rtl8192f.h"
++	#include "rtl8192f/phydm_regconfig8192f.h"
++	#include "halrf/rtl8192f/halrf_8192f.h"
++	#include "halrf/rtl8192f/halhwimg8192f_rf.h"
++	#include "halrf/rtl8192f/version_rtl8192f_rf.h"
++	#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++		#include "halrf/rtl8192f/halrf_dpk_8192f.h"
++	#endif
++#endif
++
++#if (RTL8721D_SUPPORT == 1)
++	#include "halrf/rtl8721d/halrf_btiqk_8721d.h"
++	#include "halrf/rtl8721d/halrf_rfk_init_8721d.h"
++	#include "halrf/rtl8721d/halrf_dpk_8721d.h"
++	#include "halrf/rtl8721d/halrf_8721d.h"
++	#include "halrf/rtl8721d/halhwimg8721d_rf.h"
++	#include "halrf/rtl8721d/version_rtl8721d_rf.h"
++	#include "rtl8721d/phydm_hal_api8721d.h"
++	#include "rtl8721d/phydm_regconfig8721d.h"
++	#include "rtl8721d/halhwimg8721d_mac.h"
++	#include "rtl8721d/halhwimg8721d_bb.h"
++	#include "rtl8721d/version_rtl8721d.h"
++	#include "rtl8721d/phydm_rtl8721d.h"
++	#include "rtl8721d/hal8721dreg.h"
++	#include <hal_data.h>
++	#if 0
++	#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	#endif
++	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#include "rtl8721d_hal.h"
++	#endif
++	#endif
++#endif
++
++#if (RTL8710C_SUPPORT == 1)
++	#include "halrf/rtl8710c/halrf_8710c.h"
++	#include "halrf/rtl8710c/halhwimg8710c_rf.h"
++	//#include "halrf/rtl8710c/version_rtl8710c_rf.h"
++	#include "rtl8710c/phydm_hal_api8710c.h"
++	#include "rtl8710c/phydm_regconfig8710c.h"
++	#include "rtl8710c/halhwimg8710c_mac.h"
++	#include "rtl8710c/halhwimg8710c_bb.h"
++	#include "rtl8710c/version_rtl8710c.h"
++	#include "rtl8710c/phydm_rtl8710c.h"
++	//#include "rtl8710c/hal87100creg.h"
++	#include <hal_data.h> /*@HAL_DATA_TYPE*/
++	#if 0
++	#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++		#include "halrf/rtl8710c/halrf_dpk_8710c.h"
++	#endif
++	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#include "rtl8710c_hal.h"
++	#endif
++	#endif
++#endif
++
++#if (RTL8195B_SUPPORT == 1)
++	#include "halrf/rtl8195b/halrf_8195b.h"
++	#include "halrf/rtl8195b/halhwimg8195b_rf.h"
++	#include "halrf/rtl8195b/version_rtl8195b_rf.h"
++	#include "rtl8195b/phydm_hal_api8195b.h"
++	#include "rtl8195b/phydm_regconfig8195b.h"
++	#include "rtl8195b/halhwimg8195b_mac.h"
++	#include "rtl8195b/halhwimg8195b_bb.h"
++	#include "rtl8195b/version_rtl8195b.h"
++	#include <hal_data.h> /*@HAL_DATA_TYPE*/
++#endif
++
++#if (RTL8198F_SUPPORT == 1)
++	#include "rtl8198f/phydm_regconfig8198f.h"
++	#include "rtl8198f/phydm_hal_api8198f.h"
++	#include "rtl8198f/halhwimg8198f_mac.h"
++	#include "rtl8198f/halhwimg8198f_bb.h"
++	#include "rtl8198f/version_rtl8198f.h"
++	#include "halrf/rtl8198f/halrf_8198f.h"
++	#include "halrf/rtl8198f/halrf_iqk_8198f.h"
++	#include "halrf/rtl8198f/halhwimg8198f_rf.h"
++	#include "halrf/rtl8198f/version_rtl8198f_rf.h"
++#endif
++
++#if (RTL8822C_SUPPORT)
++	#include "rtl8822c/halhwimg8822c_bb.h"
++	#include "rtl8822c/phydm_regconfig8822c.h"
++	#include "rtl8822c/phydm_hal_api8822c.h"
++	#include "rtl8822c/version_rtl8822c.h"
++	#include "rtl8822c/phydm_rtl8822c.h"
++	#include "halrf/rtl8822c/halrf_8822c.h"
++	#include "halrf/rtl8822c/halhwimg8822c_rf.h"
++	#include "halrf/rtl8822c/version_rtl8822c_rf.h"
++	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	/* @struct HAL_DATA_TYPE */
++	#include <hal_data.h>
++	/* @RX_SMOOTH_FACTOR, reg definition and etc.*/
++	#include <rtl8822c_hal.h>
++	#endif
++#endif
++#if (RTL8814B_SUPPORT == 1)
++	#include "rtl8814b/halhwimg8814b_bb.h"
++	#include "rtl8814b/phydm_regconfig8814b.h"
++	#include "halrf/rtl8814b/halrf_8814b.h"
++	#include "halrf/rtl8814b/halhwimg8814b_rf.h"
++	#include "halrf/rtl8814b/version_rtl8814b_rf.h"
++	#include "rtl8814b/phydm_hal_api8814b.h"
++	#include "rtl8814b/version_rtl8814b.h"
++	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++		#include <hal_data.h>		/* @struct HAL_DATA_TYPE */
++		#include <rtl8814b_hal.h>	/* @RX_SMOOTH_FACTOR, reg definition and etc.*/
++	#endif
++#endif
++#if (RTL8812F_SUPPORT)
++	#include "rtl8812f/halhwimg8812f_bb.h"
++	#include "rtl8812f/phydm_regconfig8812f.h"
++	#include "halrf/rtl8812f/halrf_8812f.h"
++	#include "halrf/rtl8812f/halhwimg8812f_rf.h"
++	#include "halrf/rtl8812f/version_rtl8812f_rf.h"
++	#include "rtl8812f/phydm_hal_api8812f.h"
++	#include "rtl8812f/version_rtl8812f.h"
++#endif
++#if (RTL8197G_SUPPORT)
++	#include "rtl8197g/halhwimg8197g_bb.h"
++	#include "rtl8197g/halhwimg8197g_mac.h"
++	#include "rtl8197g/phydm_regconfig8197g.h"
++	#include "halrf/rtl8197g/halrf_8197g.h"
++	#include "halrf/rtl8197g/halhwimg8197g_rf.h"
++	#include "halrf/rtl8197g/version_rtl8197g_rf.h"
++	#include "rtl8197g/phydm_hal_api8197g.h"
++	#include "rtl8197g/version_rtl8197g.h"
++	#include "rtl8197g/phydm_rtl8197g.h"
++#endif
++#endif /* @__ODM_PRECOMP_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_primary_cca.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_primary_cca.c
+new file mode 100644
+index 000000000..dec6c5365
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_primary_cca.c
+@@ -0,0 +1,173 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*************************************************************
++ * include files
++ ************************************************************/
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++#ifdef PHYDM_PRIMARY_CCA
++
++void phydm_write_dynamic_cca(
++	void *dm_void,
++	u8 curr_mf_state
++
++	)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
++
++	if (pri_cca->mf_state == curr_mf_state)
++		return;
++
++	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
++		if (curr_mf_state == MF_USC_LSC) {
++			odm_set_bb_reg(dm, R_0xc6c, 0x180, MF_USC_LSC);
++			/*@40M OFDM MF CCA threshold*/
++			odm_set_bb_reg(dm, R_0xc84, 0xf0000000,
++				       pri_cca->cca_th_40m_bkp);
++		} else {
++			odm_set_bb_reg(dm, R_0xc6c, 0x180, curr_mf_state);
++			/*@40M OFDM MF CCA threshold*/
++			odm_set_bb_reg(dm, R_0xc84, 0xf0000000, 0);
++		}
++	}
++
++	pri_cca->mf_state = curr_mf_state;
++	PHYDM_DBG(dm, DBG_PRI_CCA, "Set CCA at ((%s SB)), 0xc6c[8:7]=((%d))\n",
++		  ((curr_mf_state == MF_USC_LSC) ? "D" :
++		  ((curr_mf_state == MF_LSC) ? "L" : "U")), curr_mf_state);
++}
++
++void phydm_primary_cca_reset(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
++
++	PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Reset\n");
++	pri_cca->mf_state = 0xff;
++	pri_cca->pre_bw = (enum channel_width)0xff;
++	phydm_write_dynamic_cca(dm, MF_USC_LSC);
++}
++
++void phydm_primary_cca_11n(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
++	enum channel_width curr_bw = (enum channel_width)*dm->band_width;
++
++	if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
++		return;
++
++	if (!dm->is_linked) {
++		PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][No Link!!!]\n");
++
++		if (pri_cca->pri_cca_is_become_linked) {
++			phydm_primary_cca_reset(dm);
++			pri_cca->pri_cca_is_become_linked = dm->is_linked;
++		}
++		return;
++	} else {
++		if (!pri_cca->pri_cca_is_become_linked) {
++			PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][Linked !!!]\n");
++			pri_cca->pri_cca_is_become_linked = dm->is_linked;
++		}
++	}
++
++	if (curr_bw != pri_cca->pre_bw) {
++		PHYDM_DBG(dm, DBG_PRI_CCA, "[Primary CCA] start ==>\n");
++		pri_cca->pre_bw = curr_bw;
++
++		if (curr_bw == CHANNEL_WIDTH_40) {
++			if (*dm->sec_ch_offset == SECOND_CH_AT_LSB) {
++			/* Primary CH @ upper sideband*/
++				PHYDM_DBG(dm, DBG_PRI_CCA,
++					  "BW40M, Primary CH at USB\n");
++				phydm_write_dynamic_cca(dm, MF_USC);
++			} else {
++			/*Primary CH @ lower sideband*/
++				PHYDM_DBG(dm, DBG_PRI_CCA,
++					  "BW40M, Primary CH at LSB\n");
++				phydm_write_dynamic_cca(dm, MF_LSC);
++			}
++		} else {
++			PHYDM_DBG(dm, DBG_PRI_CCA, "Not BW40M, USB + LSB\n");
++			phydm_primary_cca_reset(dm);
++		}
++	}
++}
++
++boolean
++odm_dynamic_primary_cca_dup_rts(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
++
++	return pri_cca->dup_rts_flag;
++}
++
++void phydm_primary_cca_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
++
++	if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
++		return;
++
++	if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
++		return;
++
++	PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Init ==>\n");
++#if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1)
++	pri_cca->dup_rts_flag = 0;
++	pri_cca->intf_flag = 0;
++	pri_cca->intf_type = 0;
++	pri_cca->monitor_flag = 0;
++	pri_cca->pri_cca_flag = 0;
++	pri_cca->ch_offset = 0;
++#endif
++	pri_cca->mf_state = 0xff;
++	pri_cca->pre_bw = (enum channel_width)0xff;
++	pri_cca->cca_th_40m_bkp = (u8)odm_get_bb_reg(dm, R_0xc84, 0xf0000000);
++}
++
++void phydm_primary_cca(void *dm_void)
++{
++#ifdef PHYDM_PRIMARY_CCA
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
++		return;
++
++	if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
++		return;
++
++	phydm_primary_cca_11n(dm);
++
++#endif
++}
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_primary_cca.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_primary_cca.h
+new file mode 100644
+index 000000000..1978586f2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_primary_cca.h
+@@ -0,0 +1,76 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_PRIMARYCCA_H__
++#define __PHYDM_PRIMARYCCA_H__
++
++#ifdef PHYDM_PRIMARY_CCA
++#define PRIMARYCCA_VERSION "2.0"
++
++/*@============================================================*/
++/*@Definition */
++/*@============================================================*/
++
++#define	OFDMCCA_TH		500
++#define	bw_ind_bias		500
++#define	PRI_CCA_MONITOR_TIME	30
++
++/*@============================================================*/
++/*structure and define*/
++/*@============================================================*/
++enum primary_cca_ch_position { /*N-series REG0xc6c[8:7]*/
++	MF_USC_LSC	= 0,
++	MF_LSC		= 1,
++	MF_USC		= 2
++};
++
++struct phydm_pricca_struct {
++	#if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1)
++	u8	pri_cca_flag;
++	u8	intf_flag;
++	u8	intf_type;
++	u8	monitor_flag;
++	u8	ch_offset;
++	#endif
++	u8	dup_rts_flag;
++	u8	cca_th_40m_bkp; /*@c84[31:28]*/
++	enum channel_width	pre_bw;
++	u8	pri_cca_is_become_linked;
++	u8	mf_state;
++};
++
++/*@============================================================*/
++/*@function prototype*/
++/*@============================================================*/
++void phydm_write_dynamic_cca(void *dm_void, u8 curr_mf_state);
++
++boolean odm_dynamic_primary_cca_dup_rts(void *dm_void);
++
++void phydm_primary_cca_init(void *dm_void);
++
++void phydm_primary_cca(void *dm_void);
++#endif /*@#ifdef PHYDM_PRIMARY_CCA*/
++#endif /*@#ifndef	__PHYDM_PRIMARYCCA_H__*/
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_psd.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_psd.c
+new file mode 100644
+index 000000000..95fc4b734
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_psd.c
+@@ -0,0 +1,486 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/******************************************************************************
++ * include files
++ *****************************************************************************/
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#ifdef CONFIG_PSD_TOOL
++u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct psd_info *dm_psd_table = &dm->dm_psd_table;
++	u32 psd_report = 0;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		#if 0
++		odm_set_bb_reg(dm, R_0x1e8c, 0x3ff, psd_tone_idx & 0x3ff);
++		odm_set_bb_reg(dm, R_0x1e88, BIT(27) | BIT(26),
++			       psd_tone_idx >> 10);
++		/*PSD trigger start*/
++		odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 1);
++		ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
++		/*PSD trigger stop*/
++		odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 0);
++		#endif
++	} else if (dm->support_ic_type & (ODM_RTL8721D |
++				ODM_RTL8710C)) {
++		odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0xfff, psd_tone_idx);
++		odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 1);
++		/*PSD trigger start*/
++		ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
++		odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 0);
++		/*PSD trigger stop*/
++	} else {
++		odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff, psd_tone_idx);
++		/*PSD trigger start*/
++		odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 1);
++		ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
++		/*PSD trigger stop*/
++		odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 0);
++	}
++
++	/*Get PSD Report*/
++	if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
++				ODM_RTL8710C)) {
++		psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
++					    0xffffff);
++		psd_report = psd_report >> 5;
++	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		#if 0
++		psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
++					    0xffffff);
++		#endif
++	} else {
++		psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
++					    0xffff);
++	}
++	psd_report = odm_convert_to_db((u64)psd_report) + igi;
++
++	return psd_report;
++}
++
++u8 psd_result_cali_tone_8821[7] = {21, 28, 33, 93, 98, 105, 127};
++u8 psd_result_cali_val_8821[7] = {67, 69, 71, 72, 71, 69, 67};
++
++u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct psd_info *dm_psd_table = &dm->dm_psd_table;
++	u32 i = 0, mod_tone_idx = 0;
++	u32 t = 0;
++	u16 fft_max_half_bw = 0;
++	u16 psd_fc_channel = dm_psd_table->psd_fc_channel;
++	u8 ag_rf_mode_reg = 0;
++	u8 is_5G = 0;
++	u32 psd_result_tmp = 0;
++	u8 psd_result = 0;
++	u8 psd_result_cali_tone[7] = {0};
++	u8 psd_result_cali_val[7] = {0};
++	u8 noise_idx = 0;
++	u8 set_result = 0;
++	u32 igi_tmp = 0x6e;
++
++	if (dm->support_ic_type == ODM_RTL8821) {
++		odm_move_memory(dm, psd_result_cali_tone,
++				psd_result_cali_tone_8821, 7);
++		odm_move_memory(dm, psd_result_cali_val,
++				psd_result_cali_val_8821, 7);
++	}
++
++	dm_psd_table->psd_in_progress = 1;
++
++	PHYDM_DBG(dm, ODM_COMP_API, "PSD Start =>\n");
++
++	/* @[Stop DIG]*/
++	/* @IGI target at 0dBm & make it can't CCA*/
++	if (phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_3, 1,
++			     &igi_tmp) == PAUSE_FAIL) {
++		return PHYDM_SET_FAIL;
++	}
++
++	ODM_delay_us(10);
++
++	if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
++		phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_3,
++				 1, &igi_tmp);
++		return PHYDM_SET_FAIL;
++	}
++
++	/* @[Set IGI]*/
++	phydm_write_dig_reg(dm, (u8)igi);
++
++	/* @[Backup RF Reg]*/
++	dm_psd_table->rf_0x18_bkp = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18,
++						   RFREG_MASK);
++	dm_psd_table->rf_0x18_bkp_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0x18,
++						     RFREG_MASK);
++
++	if (psd_fc_channel > 14) {
++		is_5G = 1;
++		if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
++					   ODM_RTL8197G)) {
++		#if 0
++			if (psd_fc_channel < 80)
++				ag_rf_mode_reg = 0x1;
++			else if (psd_fc_channel >= 80 && psd_fc_channel <= 140)
++				ag_rf_mode_reg = 0x3;
++			else if (psd_fc_channel > 140)
++				ag_rf_mode_reg = 0x5;
++		#endif
++		} else if (dm->support_ic_type == ODM_RTL8721D) {
++			if (psd_fc_channel >= 36 && psd_fc_channel <= 64)
++				ag_rf_mode_reg = 0x1;
++			else if (psd_fc_channel >= 100 && psd_fc_channel <= 140)
++				ag_rf_mode_reg = 0x5;
++			else if (psd_fc_channel > 140)
++				ag_rf_mode_reg = 0x9;
++		} else {
++			if (psd_fc_channel >= 36 && psd_fc_channel <= 64)
++				ag_rf_mode_reg = 0x1;
++			else if (psd_fc_channel >= 100 && psd_fc_channel <= 140)
++				ag_rf_mode_reg = 0x3;
++			else if (psd_fc_channel > 140)
++				ag_rf_mode_reg = 0x5;
++		}
++	}
++
++	/* Set RF fc*/
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff, psd_fc_channel);
++	odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xff, psd_fc_channel);
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x300, is_5G);
++	odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x300, is_5G);
++	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
++				   ODM_RTL8197G)) {
++		#if 0
++		/* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x3000,
++			       dm_psd_table->psd_bw_rf_reg);
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x3000,
++			       dm_psd_table->psd_bw_rf_reg);
++		/* Set RF ag fc mode*/
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x70000,
++			       ag_rf_mode_reg);
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x70000,
++			       ag_rf_mode_reg);
++		#endif
++	} else {
++		/* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
++		if (dm->support_ic_type == ODM_RTL8721D) {
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x1c00,
++				       dm_psd_table->psd_bw_rf_reg);
++#if (RTL8710C_SUPPORT == 1)
++		} else if (dm->support_ic_type == ODM_RTL8710C) {
++			config_phydm_write_rf_reg_8710c(dm, RF_PATH_A,
++							RF_0x18, 0x1c00,
++						dm_psd_table->psd_bw_rf_reg);
++#endif
++		} else {
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xc00,
++				       dm_psd_table->psd_bw_rf_reg);
++		}
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xc00,
++				       dm_psd_table->psd_bw_rf_reg);
++			/* Set RF ag fc mode*/
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xf0000,
++				       ag_rf_mode_reg);
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xf0000,
++				       ag_rf_mode_reg);
++	}
++
++	#if 0
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++		PHYDM_DBG(dm, ODM_COMP_API, "0x1d70=((0x%x))\n",
++			  odm_get_bb_reg(dm, R_0x1d70, MASKDWORD));
++	else
++	#endif
++		PHYDM_DBG(dm, ODM_COMP_API, "0xc50=((0x%x))\n",
++			  odm_get_bb_reg(dm, R_0xc50, MASKDWORD));
++
++	PHYDM_DBG(dm, ODM_COMP_API, "RF0x18=((0x%x))\n",
++		  odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK));
++
++	/* @[Stop 3-wires]*/
++	phydm_stop_3_wire(dm, PHYDM_SET);
++
++	ODM_delay_us(10);
++
++	if (stop_point > (dm_psd_table->fft_smp_point - 1))
++		stop_point = (dm_psd_table->fft_smp_point - 1);
++
++	if (start_point > (dm_psd_table->fft_smp_point - 1))
++		start_point = (dm_psd_table->fft_smp_point - 1);
++
++	if (start_point > stop_point)
++		stop_point = start_point;
++
++	for (i = start_point; i <= stop_point; i++) {
++		fft_max_half_bw = (dm_psd_table->fft_smp_point) >> 1;
++
++		if (i < fft_max_half_bw)
++			mod_tone_idx = i + fft_max_half_bw;
++		else
++			mod_tone_idx = i - fft_max_half_bw;
++
++		psd_result_tmp = 0;
++		for (t = 0; t < dm_psd_table->sw_avg_time; t++)
++			psd_result_tmp += phydm_get_psd_data(dm, mod_tone_idx,
++							     igi);
++		psd_result =
++			(u8)((psd_result_tmp / dm_psd_table->sw_avg_time)) -
++			dm_psd_table->psd_pwr_common_offset;
++
++		if (dm_psd_table->fft_smp_point == 128 &&
++		    dm_psd_table->noise_k_en) {
++			if (i > psd_result_cali_tone[noise_idx])
++				noise_idx++;
++
++			if (noise_idx > 6)
++				noise_idx = 6;
++
++			if (psd_result >= psd_result_cali_val[noise_idx])
++				psd_result = psd_result -
++					     psd_result_cali_val[noise_idx];
++			else
++				psd_result = 0;
++
++			dm_psd_table->psd_result[i] = psd_result;
++		}
++
++		PHYDM_DBG(dm, ODM_COMP_API, "[%d] N_cali = %d, PSD = %d\n",
++			  mod_tone_idx, psd_result_cali_val[noise_idx],
++			  psd_result);
++	}
++
++	/*@[Start 3-wires]*/
++	phydm_stop_3_wire(dm, PHYDM_REVERT);
++
++	ODM_delay_us(10);
++
++	/*@[Revert Reg]*/
++	set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK,
++		       dm_psd_table->rf_0x18_bkp);
++	odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, RFREG_MASK,
++		       dm_psd_table->rf_0x18_bkp_b);
++
++	PHYDM_DBG(dm, ODM_COMP_API, "PSD finished\n\n");
++
++	phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_3, 1,
++			 &igi_tmp);
++	dm_psd_table->psd_in_progress = 0;
++
++	return PHYDM_SET_SUCCESS;
++}
++
++void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
++			    u8 i_q_setting, u16 fft_smp_point, u8 ant_sel,
++			    u8 psd_input, u8 channel, u8 noise_k_en)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct psd_info *dm_psd_table = &dm->dm_psd_table;
++	u8 fft_smp_point_idx = 0;
++
++	dm_psd_table->fft_smp_point = fft_smp_point;
++
++	if (sw_avg_time == 0)
++		sw_avg_time = 1;
++
++	dm_psd_table->sw_avg_time = sw_avg_time;
++	dm_psd_table->psd_fc_channel = channel;
++	dm_psd_table->noise_k_en = noise_k_en;
++
++	if (fft_smp_point == 128)
++		fft_smp_point_idx = 0;
++	else if (fft_smp_point == 256)
++		fft_smp_point_idx = 1;
++	else if (fft_smp_point == 512)
++		fft_smp_point_idx = 2;
++	else if (fft_smp_point == 1024)
++		fft_smp_point_idx = 3;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		#if 0
++		odm_set_bb_reg(dm, R_0x1e8c, BIT(11) | BIT(10), i_q_setting);
++		odm_set_bb_reg(dm, R_0x1e8c, BIT(13) | BIT(12), hw_avg_time);
++
++		if (fft_smp_point == 4096) {
++			odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x2);
++		} else if (fft_smp_point == 2048) {
++			odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x1);
++		} else {
++			odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x0);
++			odm_set_bb_reg(dm, R_0x1e8c, BIT(15) | BIT(14),
++				       fft_smp_point_idx);
++		}
++		odm_set_bb_reg(dm, R_0x1e8c, BIT(17) | BIT(16), ant_sel);
++		odm_set_bb_reg(dm, R_0x1e8c, BIT(23) | BIT(22), psd_input);
++		#endif
++	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		odm_set_bb_reg(dm, R_0x910, BIT(11) | BIT(10), i_q_setting);
++		odm_set_bb_reg(dm, R_0x910, BIT(13) | BIT(12), hw_avg_time);
++		odm_set_bb_reg(dm, R_0x910, BIT(15) | BIT(14),
++			       fft_smp_point_idx);
++		odm_set_bb_reg(dm, R_0x910, BIT(17) | BIT(16), ant_sel);
++		odm_set_bb_reg(dm, R_0x910, BIT(23), psd_input);
++	} else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
++		odm_set_bb_reg(dm, R_0x808, BIT(19) | BIT(18), i_q_setting);
++		odm_set_bb_reg(dm, R_0x808, BIT(21) | BIT(20), hw_avg_time);
++		odm_set_bb_reg(dm, R_0x808, BIT(23) | BIT(22),
++			       fft_smp_point_idx);
++		odm_set_bb_reg(dm, R_0x804, BIT(5) | BIT(4), ant_sel);
++		odm_set_bb_reg(dm, R_0x80c, BIT(23), psd_input);
++
++#if 0
++	} else {	/*ODM_IC_11N_SERIES*/
++#endif
++	}
++	/*@bw = (*dm->band_width); //ODM_BW20M */
++	/*@channel = *(dm->channel);*/
++}
++
++void phydm_psd_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct psd_info *dm_psd_table = &dm->dm_psd_table;
++
++	PHYDM_DBG(dm, ODM_COMP_API, "PSD para init\n");
++
++	dm_psd_table->psd_in_progress = false;
++
++	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
++		#if 0
++		dm_psd_table->psd_reg = R_0x1e8c;
++		dm_psd_table->psd_report_reg = R_0x2d90;
++
++		/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
++		dm_psd_table->psd_bw_rf_reg = 1;
++		#endif
++
++		return;
++	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
++		dm_psd_table->psd_reg = R_0x910;
++		dm_psd_table->psd_report_reg = R_0xf44;
++
++		/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
++		if (ODM_IC_11AC_2_SERIES)
++			dm_psd_table->psd_bw_rf_reg = 1;
++		else
++			dm_psd_table->psd_bw_rf_reg = 2;
++	} else {
++		dm_psd_table->psd_reg = R_0x808;
++		dm_psd_table->psd_report_reg = R_0x8b4;
++		/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
++		dm_psd_table->psd_bw_rf_reg = 2;
++	}
++
++	dm_psd_table->psd_pwr_common_offset = 0;
++
++	phydm_psd_para_setting(dm, 1, 2, 3, 128, 0, 0, 7, 0);
++#if 0
++	/*phydm_psd(dm, 0x3c, 0, 127);*/ /* target at -50dBm */
++#endif
++}
++
++void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used,
++		     char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	char help[] = "-h";
++	u32 var1[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u8 i = 0;
++
++	if ((strcmp(input[1], help) == 0)) {
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		#if 0
++		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4) 2048 4096}\n{path_sel 0~3} {0:ADC, 1:rxdata_fir_in, 2:rx_nbi_nf_stage2} {CH} {noise_k}\n\n");
++		else
++		#endif
++		#endif
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n");
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{1} {IGI(hex)} {start_point} {stop_point}\n");
++		goto out;
++	}
++
++	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
++
++	if (var1[0] == 0) {
++		for (i = 1; i < 10; i++) {
++			if (input[i + 1])
++				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
++					     &var1[i]);
++		}
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n",
++			 var1[1], var1[2], var1[3], var1[4], var1[5],
++			 var1[6], (u8)var1[7], (u8)var1[8]);
++		phydm_psd_para_setting(dm, (u8)var1[1], (u8)var1[2],
++				       (u8)var1[3], (u16)var1[4],
++				       (u8)var1[5], (u8)var1[6],
++				       (u8)var1[7], (u8)var1[8]);
++
++	} else if (var1[0] == 1) {
++		PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);
++		PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
++		PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n",
++			 var1[1], var1[2], var1[3]);
++		dm->debug_components |= ODM_COMP_API;
++		if (phydm_psd(dm, var1[1], (u16)var1[2], (u16)var1[3]) ==
++		    PHYDM_SET_FAIL)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "PSD_SET_FAIL\n");
++		dm->debug_components &= ~(ODM_COMP_API);
++	}
++
++out:
++	*_used = used;
++	*_out_len = out_len;
++}
++
++u8 phydm_get_psd_result_table(void *dm_void, int index)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct psd_info *dm_psd_table = &dm->dm_psd_table;
++	u8 result = 0;
++
++	if (index < 128)
++		result = dm_psd_table->psd_result[index];
++
++	return result;
++}
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_psd.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_psd.h
+new file mode 100644
+index 000000000..dec384ab2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_psd.h
+@@ -0,0 +1,68 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDMPSD_H__
++#define __PHYDMPSD_H__
++
++/*@#define PSD_VERSION	"1.0"*/ /*@2016.09.22  Dino*/
++/*@2016.10.07  Dino, Add Option for PSD Tone index Selection */
++/*@2019.04.26  Early return & "IF0" for JGR3 ICs */
++#define PSD_VERSION "1.2"
++
++#ifdef CONFIG_PSD_TOOL
++
++
++struct psd_info {
++	u8	psd_in_progress;
++	u32	psd_reg;
++	u32	psd_report_reg;
++	u8	psd_pwr_common_offset;
++	u16	sw_avg_time;
++	u16	fft_smp_point;
++	u32	rf_0x18_bkp;
++	u32	rf_0x18_bkp_b;
++	u16	psd_fc_channel;
++	u32	psd_bw_rf_reg;
++	u8	psd_result[128];
++	u8	noise_k_en;
++};
++
++u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi);
++
++void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used,
++		     char *output, u32 *_out_len);
++
++u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point);
++
++void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
++			    u8 i_q_setting, u16 fft_smp_point, u8 ant_sel,
++			    u8 psd_input, u8 channel, u8 noise_k_en);
++
++void phydm_psd_init(void *dm_void);
++
++u8 phydm_get_psd_result_table(void *dm_void, int index);
++
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_rainfo.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_rainfo.c
+new file mode 100644
+index 000000000..81bfe869b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_rainfo.c
+@@ -0,0 +1,2365 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ ************************************************************/
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++boolean phydm_is_vht_rate(void *dm_void, u8 rate)
++{
++	return ((rate & 0x7f) >= ODM_RATEVHTSS1MCS0) ? true : false;
++}
++
++boolean phydm_is_ht_rate(void *dm_void, u8 rate)
++{
++	return (((rate & 0x7f) >= ODM_RATEMCS0) &&
++		((rate & 0x7f) <= ODM_RATEMCS31)) ? true : false;
++}
++
++boolean phydm_is_ofdm_rate(void *dm_void, u8 rate)
++{
++	return (((rate & 0x7f) >= ODM_RATE6M) &&
++		((rate & 0x7f) <= ODM_RATE54M)) ? true : false;
++}
++
++boolean phydm_is_cck_rate(void *dm_void, u8 rate)
++{
++	return ((rate & 0x7f) <= ODM_RATE11M) ? true : false;
++}
++
++u8 phydm_legacy_rate_2_spec_rate(void *dm_void, u8 rate)
++{
++	u8 rate_idx = 0x0;
++	u8 legacy_spec_rate_t[8] = {PHYDM_SPEC_RATE_6M, PHYDM_SPEC_RATE_9M,
++				    PHYDM_SPEC_RATE_12M, PHYDM_SPEC_RATE_18M,
++				    PHYDM_SPEC_RATE_24M, PHYDM_SPEC_RATE_36M,
++				    PHYDM_SPEC_RATE_48M, PHYDM_SPEC_RATE_54M};
++
++	rate_idx = rate - ODM_RATE6M;
++	return legacy_spec_rate_t[rate_idx];
++}
++
++u8 phydm_rate_2_rate_digit(void *dm_void, u8 rate)
++{
++	u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54};
++	u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
++	u8 rate_digit = 0;
++
++	if (rate_idx >= ODM_RATEVHTSS1MCS0)
++		rate_digit = (rate_idx - ODM_RATEVHTSS1MCS0) % 10;
++	else if (rate_idx >= ODM_RATEMCS0)
++		rate_digit = (rate_idx - ODM_RATEMCS0);
++	else if (rate_idx <= ODM_RATE54M)
++		rate_digit = legacy_table[rate_idx];
++
++	return rate_digit;
++}
++
++u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type)
++{
++	u8 num_ss = 1;
++
++	switch (type) {
++	case PDM_CCK:
++	case PDM_OFDM:
++	case PDM_1SS:
++		num_ss = 1;
++		break;
++	case PDM_2SS:
++		num_ss = 2;
++		break;
++	case PDM_3SS:
++		num_ss = 3;
++		break;
++	case PDM_4SS:
++		num_ss = 4;
++		break;
++	default:
++		break;
++	}
++
++	return num_ss;
++}
++
++u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate)
++{
++	u8 num_ss = 1;
++
++	if (data_rate <= ODM_RATE54M)
++		num_ss = 1;
++	else if (data_rate <= ODM_RATEMCS31)
++		num_ss = ((data_rate - ODM_RATEMCS0) >> 3) + 1;
++	else if (data_rate <= ODM_RATEVHTSS1MCS9)
++		num_ss = 1;
++	else if (data_rate <= ODM_RATEVHTSS2MCS9)
++		num_ss = 2;
++	else if (data_rate <= ODM_RATEVHTSS3MCS9)
++		num_ss = 3;
++	else if (data_rate <= ODM_RATEVHTSS4MCS9)
++		num_ss = 4;
++
++	return num_ss;
++}
++
++void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used,
++		     char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 dm_value[10] = {0};
++	u8 i = 0, input_idx = 0;
++	u8 h2c_parameter[H2C_MAX_LENGTH] = {0};
++	u8 phydm_h2c_id = 0;
++
++	for (i = 0; i < 8; i++) {
++		if (input[i + 1]) {
++			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
++			input_idx++;
++		}
++	}
++
++	if (input_idx == 0)
++		return;
++
++	phydm_h2c_id = (u8)dm_value[0];
++
++	PDM_SNPF(out_len, used, output + used, out_len - used,
++		 "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id);
++
++	for (i = 0; i < H2C_MAX_LENGTH; i++) {
++		h2c_parameter[i] = (u8)dm_value[i + 1];
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "H2C: Byte[%d] = ((0x%x))\n", i, h2c_parameter[i]);
++	}
++
++	odm_fill_h2c_cmd(dm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter);
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_fw_fix_rate(void *dm_void, u8 en, u8 macid, u8 bw, u8 rate)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 reg_u32_tmp;
++
++	if (dm->support_ic_type & PHYDM_IC_8051_SERIES) {
++		reg_u32_tmp = (bw << 24) | (rate << 16) | (macid << 8) | en;
++		odm_set_mac_reg(dm, R_0x4a0, MASKDWORD, reg_u32_tmp);
++
++	} else {
++		if (en == 1)
++			reg_u32_tmp = BYTE_2_DWORD(0x60, macid, bw, rate);
++		else
++			reg_u32_tmp = 0x40000000;
++		if (dm->support_ic_type & ODM_RTL8814B)
++			odm_set_mac_reg(dm, R_0x448, MASKDWORD, reg_u32_tmp);
++		else
++			odm_set_mac_reg(dm, R_0x450, MASKDWORD, reg_u32_tmp);
++	}
++	if (en == 1) {
++		PHYDM_DBG(dm, ODM_COMP_API,
++			  "FW fix TX rate[id =%d], %dM, Rate(%d)=", macid,
++			  (20 << bw), rate);
++		phydm_print_rate(dm, rate, ODM_COMP_API);
++	} else {
++		PHYDM_DBG(dm, ODM_COMP_API, "Auto Rate\n");
++	}
++}
++
++void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
++		    u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_tab = &dm->dm_ra_table;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	char help[] = "-h";
++	u32 var[5] = {0};
++	u8 macid = 0, bw = 0, rate = 0;
++	u8 tx_cls_en = 0, tx_cls_th = 0, tmp = 0;
++	u8 i = 0;
++
++	for (i = 0; i < 5; i++) {
++		if (input[i + 1])
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]);
++	}
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{1} {0:-,1:+} {ofst}: set offset\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{1} {100}: show offset\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{2} {en} {macid} {bw} {rate}: fw fix rate\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{3} {en}: Dynamic RRSR\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{4} {0:pkt RA, 1:TBTT RA}\n");
++#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{5} {0:dis, 1:en}{th; 255:auto, xx:dB}: Tx CLS\n");
++#endif
++	} else if (var[0] == 1) { /*@Adjust PCR offset*/
++
++		if (var[1] == 100) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[Get] RA_ofst=((%s%d))\n",
++				 ((ra_tab->ra_ofst_direc) ? "+" : "-"),
++				 ra_tab->ra_th_ofst);
++
++		} else if (var[1] == 0) {
++			ra_tab->ra_ofst_direc = 0;
++			ra_tab->ra_th_ofst = (u8)var[2];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[Set] RA_ofst=((-%d))\n", ra_tab->ra_th_ofst);
++		} else if (var[1] == 1) {
++			ra_tab->ra_ofst_direc = 1;
++			ra_tab->ra_th_ofst = (u8)var[2];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[Set] RA_ofst=((+%d))\n", ra_tab->ra_th_ofst);
++		}
++
++	} else if (var[0] == 2) { /*@FW fix rate*/
++		macid = (u8)var[2];
++		bw = (u8)var[3];
++		rate = (u8)var[4];
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[FW fix TX Rate] {en, macid,bw,rate}={%d, %d, %d, 0x%x}",
++			 var[1], macid, bw, rate);
++
++		phydm_fw_fix_rate(dm, (u8)var[1], macid, bw, rate);
++	} else if (var[0] == 3) { /*@Dynamic RRSR*/
++		ra_tab->dynamic_rrsr_en = (boolean)var[1];
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[Dynamic RRSR] enable=%d", ra_tab->dynamic_rrsr_en);
++	} else if (var[0] == 4) { /*@RA trigger mode*/
++		ra_tab->ra_trigger_mode = (u8)var[1];
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[RA trigger] mode=%d\n", ra_tab->ra_trigger_mode);
++#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
++	} else if (var[0] == 5) { /*@Tx Collision Detection*/
++		tx_cls_en = (u8)var[1];
++		ra_tab->ra_tx_cls_th = (u8)var[2];
++		tmp = (u8)var[2];
++		tx_cls_th = (tmp < 50) ? 0 : (tmp > 81) ? 31 : tmp - 50;
++		if (tx_cls_en) {
++			odm_set_bb_reg(dm, R_0x8f8, BIT(16), 1);
++			if (ra_tab->ra_tx_cls_th != 255)
++				phydm_tx_collsion_th_set(dm, tx_cls_th,
++							 tx_cls_th);
++
++		} else {
++			odm_set_bb_reg(dm, R_0x8f8, BIT(16), 0);
++		}
++
++		if (tx_cls_en & ra_tab->ra_tx_cls_th != 255) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[Tx Collision Detec] {en, th}={%d, %d}\n",
++				 tx_cls_en, tx_cls_th + 50);
++		} else if (tx_cls_en & ra_tab->ra_tx_cls_th == 255) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[Tx Collision Detec] {en, th}={%d, auto}\n",
++				 tx_cls_en);
++		} else {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[Tx Collision Detec] {en, th}={%d, xx}\n",
++				 tx_cls_en);
++		}
++#endif
++	} else {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[Set] Error\n");
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 mode = cmd_buf[0]; /*Retry Penalty, NH, NL*/
++	u8 i;
++
++	PHYDM_DBG(dm, DBG_FW_TRACE, "[%s] [mode: %d]----------------------->\n",
++		  __func__, mode);
++
++	if (mode == RADBG_DEBUG_MONITOR1) {
++		if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "RSSI =",
++				  cmd_buf[1]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n", "rate =",
++				  cmd_buf[2] & 0x7f);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "SGI =",
++				  (cmd_buf[2] & 0x80) >> 7);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "BW =",
++				  cmd_buf[3]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "BW_max =",
++				  cmd_buf[4]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
++				  "multi_rate0 =", cmd_buf[5]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
++				  "multi_rate1 =", cmd_buf[6]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "DISRA =",
++				  cmd_buf[7]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "VHT_EN =",
++				  cmd_buf[8]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n",
++				  "SGI_support =", cmd_buf[9]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "try_ness =",
++				  cmd_buf[10]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n", "pre_rate =",
++				  cmd_buf[11]);
++		} else {
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "RSSI =",
++				  cmd_buf[1]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %x\n", "BW =",
++				  cmd_buf[2]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "DISRA =",
++				  cmd_buf[3]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "VHT_EN =",
++				  cmd_buf[4]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n",
++				  "Hightest rate =", cmd_buf[5]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
++				  "Lowest rate =", cmd_buf[6]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
++				  "SGI_support =", cmd_buf[7]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "Rate_ID =",
++				  cmd_buf[8]);
++		}
++	} else if (mode == RADBG_DEBUG_MONITOR2) {
++		if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "rate_id =",
++				  cmd_buf[1]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
++				  "highest_rate =", cmd_buf[2]);
++			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
++				  "lowest_rate =", cmd_buf[3]);
++
++			for (i = 4; i <= 11; i++)
++				PHYDM_DBG(dm, DBG_FW_TRACE, "RAMASK =  0x%x\n",
++					  cmd_buf[i]);
++		} else {
++			PHYDM_DBG(dm, DBG_FW_TRACE,
++				  "%5s  %x%x  %x%x  %x%x  %x%x\n", "RA Mask:",
++				  cmd_buf[8], cmd_buf[7], cmd_buf[6],
++				  cmd_buf[5], cmd_buf[4], cmd_buf[3],
++				  cmd_buf[2], cmd_buf[1]);
++		}
++	} else if (mode == RADBG_DEBUG_MONITOR3) {
++		for (i = 0; i < (cmd_len - 1); i++)
++			PHYDM_DBG(dm, DBG_FW_TRACE, "content[%d] = %d\n", i,
++				  cmd_buf[1 + i]);
++	} else if (mode == RADBG_DEBUG_MONITOR4)
++		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  {%d.%d}\n", "RA version =",
++			  cmd_buf[1], cmd_buf[2]);
++	else if (mode == RADBG_DEBUG_MONITOR5) {
++		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n", "Current rate =",
++			  cmd_buf[1]);
++		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "Retry ratio =",
++			  cmd_buf[2]);
++		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "rate down ratio =",
++			  cmd_buf[3]);
++		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n", "highest rate =",
++			  cmd_buf[4]);
++		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  {0x%x 0x%x}\n", "Muti-try =",
++			  cmd_buf[5], cmd_buf[6]);
++		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x%x%x%x%x\n", "RA mask =",
++			  cmd_buf[11], cmd_buf[10], cmd_buf[9], cmd_buf[8],
++			  cmd_buf[7]);
++	}
++	PHYDM_DBG(dm, DBG_FW_TRACE, "-------------------------------\n");
++}
++
++void phydm_ra_dynamic_retry_count(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (!(dm->support_ability & ODM_BB_DYNAMIC_ARFR))
++		return;
++
++	/*PHYDM_DBG(dm, DBG_RA, "dm->pre_b_noisy = %d\n", dm->pre_b_noisy );*/
++
++	if (dm->pre_b_noisy != dm->noisy_decision) {
++		if (dm->noisy_decision) {
++			PHYDM_DBG(dm, DBG_DYN_ARFR, "Noisy Env. RA fallback\n");
++			odm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x0);
++			odm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x04030201);
++		} else {
++			PHYDM_DBG(dm, DBG_DYN_ARFR, "Clean Env. RA fallback\n");
++			odm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x01000000);
++			odm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x06050402);
++		}
++		dm->pre_b_noisy = dm->noisy_decision;
++	}
++}
++
++void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
++	boolean vht_en = phydm_is_vht_rate(dm, rate_idx);
++	u8 b_sgi = (rate & 0x80) >> 7;
++	u8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx);
++	u8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx);
++
++	PHYDM_DBG_F(dm, dbg_component, "( %s%s%s%s%s%d%s%s)\n",
++		    (vht_en && (rate_ss == 1)) ? "VHT 1ss " : "",
++		    (vht_en && (rate_ss == 2)) ? "VHT 2ss " : "",
++		    (vht_en && (rate_ss == 3)) ? "VHT 3ss " : "",
++		    (vht_en && (rate_ss == 4)) ? "VHT 4ss " : "",
++		    (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
++		    rate_digit,
++		    (b_sgi) ? "-S" : " ",
++		    (rate_idx >= ODM_RATEMCS0) ? "" : "M");
++}
++
++void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
++	boolean vht_en = phydm_is_vht_rate(dm, rate_idx);
++	u8 b_sgi = (rate & 0x80) >> 7;
++	u8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx);
++	u8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx);
++
++	PHYDM_SNPRINTF(buf, buf_size, "( %s%s%s%s%s%d%s%s)",
++		       (vht_en && (rate_ss == 1)) ? "VHT 1ss " : "",
++		       (vht_en && (rate_ss == 2)) ? "VHT 2ss " : "",
++		       (vht_en && (rate_ss == 3)) ? "VHT 3ss " : "",
++		       (vht_en && (rate_ss == 4)) ? "VHT 4ss " : "",
++		       (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
++		       rate_digit,
++		       (b_sgi) ? "-S" : " ",
++		       (rate_idx >= ODM_RATEMCS0) ? "" : "M");
++}
++
++void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_tab = &dm->dm_ra_table;
++	struct cmn_sta_info *sta = NULL;
++	u8 macid = cmd_buf[1];
++	u8 rate = cmd_buf[0];
++	u8 ra_ratio = 0xff;
++	u8 curr_bw = 0xff;
++	u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
++	u8 rate_order;
++	u8 gid_index = 0;
++	u8 txcls_rate = 0;
++	char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
++
++	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	sta = dm->phydm_sta_info[dm->phydm_macid_table[macid]];
++	#else
++	sta = dm->phydm_sta_info[macid];
++	#endif
++
++	if (cmd_len == 7) {
++		ra_ratio = cmd_buf[5];
++		curr_bw = cmd_buf[6];
++		PHYDM_DBG(dm, DBG_RA, "[%d] PER=%d\n", macid, ra_ratio);
++	} else if (cmd_len == 8) {
++		ra_ratio = cmd_buf[5];
++		curr_bw = cmd_buf[6];
++		txcls_rate = cmd_buf[7];
++		PHYDM_DBG(dm, DBG_RA, "[%d] PER=%d TxCLS=%d\n", macid, ra_ratio,
++			  txcls_rate);
++	}
++
++	if (cmd_buf[3] != 0) {
++		if (cmd_buf[3] == 0xff)
++			PHYDM_DBG(dm, DBG_RA, "FW Fix Rate\n");
++		else if (cmd_buf[3] == 1)
++			PHYDM_DBG(dm, DBG_RA, "Try Success\n");
++		else if (cmd_buf[3] == 2)
++			PHYDM_DBG(dm, DBG_RA, "Try Fail & Again\n");
++		else if (cmd_buf[3] == 3)
++			PHYDM_DBG(dm, DBG_RA, "Rate Back\n");
++		else if (cmd_buf[3] == 4)
++			PHYDM_DBG(dm, DBG_RA, "Start rate by RSSI\n");
++		else if (cmd_buf[3] == 5)
++			PHYDM_DBG(dm, DBG_RA, "Try rate\n");
++	}
++	phydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE);
++	PHYDM_DBG(dm, DBG_RA, "Tx Rate=%s (%d)\n", dbg_buf, rate);
++
++#ifdef MU_EX_MACID
++	if (macid >= 128 && macid < (128 + MU_EX_MACID)) {
++		gid_index = macid - 128;
++		ra_tab->mu1_rate[gid_index] = rate;
++	}
++	if (macid >= ODM_ASSOCIATE_ENTRY_NUM)
++		return;
++#endif
++	if (is_sta_active(sta)) {
++		sta->ra_info.curr_tx_rate = rate;
++		sta->ra_info.curr_tx_bw = (enum channel_width)curr_bw;
++		sta->ra_info.curr_retry_ratio = ra_ratio;
++	}
++
++	/*trigger power training*/
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++
++	rate_order = phydm_rate_order_compute(dm, rate_idx);
++
++	if (dm->is_one_entry_only ||
++	    (rate_order > ra_tab->highest_client_tx_order &&
++	    ra_tab->power_tracking_flag == 1)) {
++		halrf_update_pwr_track(dm, rate_idx);
++		ra_tab->power_tracking_flag = 0;
++	}
++
++#endif
++
++#if 0
++	/*trigger dynamic rate ID*/
++	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E))
++		phydm_update_rate_id(dm, rate, macid);
++#endif
++}
++
++void odm_ra_post_action_on_assoc(void *dm_void)
++{
++}
++
++void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc,
++				   u8 ra_th_ofst)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_tab = &dm->dm_ra_table;
++
++	ra_tab->ra_ofst_direc = ra_ofst_direc;
++	ra_tab->ra_th_ofst = ra_th_ofst;
++	PHYDM_DBG(dm, DBG_RA_MASK, "Set ra_th_offset=(( %s%d ))\n",
++		  ((ra_ofst_direc) ? "+" : "-"), ra_th_ofst);
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++
++void phydm_gen_ramask_h2c_AP(
++	void *dm_void,
++	struct rtl8192cd_priv *priv,
++	struct sta_info *entry,
++	u8 rssi_level)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type == ODM_RTL8812) {
++		#if (RTL8812A_SUPPORT == 1)
++		UpdateHalRAMask8812(priv, entry, rssi_level);
++		#endif
++	} else if (dm->support_ic_type == ODM_RTL8188E) {
++		#if (RTL8188E_SUPPORT == 1)
++		#ifdef TXREPORT
++		add_RATid(priv, entry);
++		#endif
++		#endif
++	} else {
++		#ifdef CONFIG_WLAN_HAL
++		GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, entry, rssi_level);
++		#endif
++	}
++}
++
++void phydm_update_hal_ra_mask(
++	void *dm_void,
++	u32 wireless_mode,
++	u8 rf_type,
++	u8 bw,
++	u8 mimo_ps_enable,
++	u8 disable_cck_rate,
++	u32 *ratr_bitmap_msb_in,
++	u32 *ratr_bitmap_lsb_in,
++	u8 tx_rate_level)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 ratr_bitmap = *ratr_bitmap_lsb_in;
++	u32 ratr_bitmap_msb = *ratr_bitmap_msb_in;
++
++#if 0
++	/*PHYDM_DBG(dm, DBG_RA_MASK, "phydm_rf_type = (( %x )), rf_type = (( %x ))\n", phydm_rf_type, rf_type);*/
++#endif
++	PHYDM_DBG(dm, DBG_RA_MASK,
++		  "Platfoem original RA Mask = (( 0x %x | %x ))\n",
++		  ratr_bitmap_msb, ratr_bitmap);
++
++	switch (wireless_mode) {
++	case PHYDM_WIRELESS_MODE_B: {
++		ratr_bitmap &= 0x0000000f;
++	} break;
++
++	case PHYDM_WIRELESS_MODE_G: {
++		ratr_bitmap &= 0x00000ff5;
++	} break;
++
++	case PHYDM_WIRELESS_MODE_A: {
++		ratr_bitmap &= 0x00000ff0;
++	} break;
++
++	case PHYDM_WIRELESS_MODE_N_24G:
++	case PHYDM_WIRELESS_MODE_N_5G: {
++		if (mimo_ps_enable)
++			rf_type = RF_1T1R;
++
++		if (rf_type == RF_1T1R) {
++			if (bw == CHANNEL_WIDTH_40)
++				ratr_bitmap &= 0x000ff015;
++			else
++				ratr_bitmap &= 0x000ff005;
++		} else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
++			if (bw == CHANNEL_WIDTH_40)
++				ratr_bitmap &= 0x0ffff015;
++			else
++				ratr_bitmap &= 0x0ffff005;
++		} else { /*@3T*/
++
++			ratr_bitmap &= 0xfffff015;
++			ratr_bitmap_msb &= 0xf;
++		}
++	} break;
++
++	case PHYDM_WIRELESS_MODE_AC_24G: {
++		if (rf_type == RF_1T1R) {
++			ratr_bitmap &= 0x003ff015;
++		} else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
++			ratr_bitmap &= 0xfffff015;
++		} else { /*@3T*/
++
++			ratr_bitmap &= 0xfffff010;
++			ratr_bitmap_msb &= 0x3ff;
++		}
++
++		if (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/
++			ratr_bitmap &= 0x7fdfffff;
++			ratr_bitmap_msb &= 0x1ff;
++		}
++	} break;
++
++	case PHYDM_WIRELESS_MODE_AC_5G: {
++		if (rf_type == RF_1T1R) {
++			ratr_bitmap &= 0x003ff010;
++		} else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
++			ratr_bitmap &= 0xfffff010;
++		} else { /*@3T*/
++
++			ratr_bitmap &= 0xfffff010;
++			ratr_bitmap_msb &= 0x3ff;
++		}
++
++		if (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/
++			ratr_bitmap &= 0x7fdfffff;
++			ratr_bitmap_msb &= 0x1ff;
++		}
++	} break;
++
++	default:
++		break;
++	}
++
++	if (wireless_mode != PHYDM_WIRELESS_MODE_B) {
++		if (tx_rate_level == 0)
++			ratr_bitmap &= 0xffffffff;
++		else if (tx_rate_level == 1)
++			ratr_bitmap &= 0xfffffff0;
++		else if (tx_rate_level == 2)
++			ratr_bitmap &= 0xffffefe0;
++		else if (tx_rate_level == 3)
++			ratr_bitmap &= 0xffffcfc0;
++		else if (tx_rate_level == 4)
++			ratr_bitmap &= 0xffff8f80;
++		else if (tx_rate_level >= 5)
++			ratr_bitmap &= 0xffff0f00;
++	}
++
++	if (disable_cck_rate)
++		ratr_bitmap &= 0xfffffff0;
++
++	PHYDM_DBG(dm, DBG_RA_MASK,
++		  "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n",
++		  wireless_mode, rf_type, bw, mimo_ps_enable, tx_rate_level);
++
++#if 0
++	/*PHYDM_DBG(dm, DBG_RA_MASK, "111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap);*/
++#endif
++
++	*ratr_bitmap_lsb_in = ratr_bitmap;
++	*ratr_bitmap_msb_in = ratr_bitmap_msb;
++	PHYDM_DBG(dm, DBG_RA_MASK,
++		  "Phydm modified RA Mask = (( 0x %x | %x ))\n",
++		  *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in);
++}
++
++#endif
++
++void phydm_rate_adaptive_mask_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_t = &dm->dm_ra_table;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	PADAPTER adapter = dm->adapter;
++	PMGNT_INFO mgnt_info = &(adapter->MgntInfo);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)dm->adapter));
++
++	if (mgnt_info->DM_Type == dm_type_by_driver)
++		hal_data->bUseRAMask = true;
++	else
++		hal_data->bUseRAMask = false;
++
++#endif
++
++	ra_t->ldpc_thres = 35;
++	ra_t->up_ramask_cnt = 0;
++	ra_t->up_ramask_cnt_tmp = 0;
++}
++
++void phydm_refresh_rate_adaptive_mask(void *dm_void)
++{
++/*@Will be removed*/
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	phydm_ra_mask_watchdog(dm);
++}
++
++void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used,
++			 char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *sta = NULL;
++	struct ra_sta_info *ra = NULL;
++#ifdef CONFIG_BEAMFORMING
++	struct bf_cmn_info *bf = NULL;
++#endif
++	char help[] = "-h";
++	u32 var[10] = {0};
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 i, sta_idx_start, sta_idx_end;
++	u8 tatal_sta_num = 0;
++
++	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var[0]);
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "All STA: {1}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "STA[macid]: {2} {macid}\n");
++		return;
++	} else if (var[0] == 1) {
++		sta_idx_start = 0;
++		sta_idx_end = ODM_ASSOCIATE_ENTRY_NUM;
++	} else if (var[0] == 2) {
++		sta_idx_start = var[1];
++		sta_idx_end = var[1];
++	} else {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Warning input value!\n");
++		return;
++	}
++
++	for (i = sta_idx_start; i < sta_idx_end; i++) {
++		sta = dm->phydm_sta_info[i];
++
++		if (!is_sta_active(sta))
++			continue;
++
++		ra = &sta->ra_info;
++		#ifdef CONFIG_BEAMFORMING
++		bf = &sta->bf_info;
++		#endif
++
++		tatal_sta_num++;
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "==[sta_idx: %d][MACID: %d]============>\n", i,
++			 sta->mac_id);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "AID:%d\n", sta->aid);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "ADDR:%x-%x-%x-%x-%x-%x\n", sta->mac_addr[5],
++			 sta->mac_addr[4], sta->mac_addr[3], sta->mac_addr[2],
++			 sta->mac_addr[1], sta->mac_addr[0]);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "DM_ctrl:0x%x\n", sta->dm_ctrl);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "BW:%d, MIMO_Type:0x%x\n", sta->bw_mode,
++			 sta->mimo_type);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "STBC_en:%d, LDPC_en=%d\n", sta->stbc_en,
++			 sta->ldpc_en);
++
++		/*@[RSSI Info]*/
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "RSSI{All, OFDM, CCK}={%d, %d, %d}\n",
++			 sta->rssi_stat.rssi, sta->rssi_stat.rssi_ofdm,
++			 sta->rssi_stat.rssi_cck);
++
++		/*@[RA Info]*/
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Rate_ID:%d, RSSI_LV:%d, ra_bw:%d, SGI_en:%d\n",
++			 ra->rate_id, ra->rssi_level, ra->ra_bw_mode,
++			 ra->is_support_sgi);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "VHT_en:%d, Wireless_set=0x%x, sm_ps=%d\n",
++			 ra->is_vht_enable, sta->support_wireless_set,
++			 sta->sm_ps);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Dis{RA, PT}={%d, %d}, TxRx:%d, Noisy:%d\n",
++			 ra->disable_ra, ra->disable_pt, ra->txrx_state,
++			 ra->is_noisy);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "TX{Rate, BW}={0x%x, %d}, RTY:%d\n", ra->curr_tx_rate,
++			 ra->curr_tx_bw, ra->curr_retry_ratio);
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "RA_Mask:0x%llx\n", ra->ramask);
++
++		/*@[TP]*/
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "TP{TX,RX}={%d, %d}\n", sta->tx_moving_average_tp,
++			 sta->rx_moving_average_tp);
++
++#ifdef CONFIG_BEAMFORMING
++		/*@[Beamforming]*/
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "BF CAP{HT,VHT}={0x%x, 0x%x}\n", bf->ht_beamform_cap,
++			 bf->vht_beamform_cap);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "BF {p_aid,g_id}={0x%x, 0x%x}\n\n", bf->p_aid,
++			 bf->g_id);
++#endif
++	}
++
++	if (tatal_sta_num == 0) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "No Linked STA\n");
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++u8 phydm_get_rx_stream_num(void *dm_void, enum rf_type type)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 rx_num = 1;
++
++	if (type == RF_1T1R)
++		rx_num = 1;
++	else if (type == RF_2T2R || type == RF_1T2R)
++		rx_num = 2;
++	else if (type == RF_3T3R || type == RF_2T3R)
++		rx_num = 3;
++	else if (type == RF_4T4R || type == RF_3T4R || type == RF_2T4R)
++		rx_num = 4;
++	else
++		pr_debug("[Warrning] %s\n", __func__);
++
++	return rx_num;
++}
++
++u8 phydm_get_tx_stream_num(void *dm_void, enum rf_type type)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 tx_num = 1;
++
++	if (type == RF_1T1R || type == RF_1T2R)
++		tx_num = 1;
++	else if (type == RF_2T2R || type == RF_2T3R || type == RF_2T4R)
++		tx_num = 2;
++	else if (type == RF_3T3R || type == RF_3T4R)
++		tx_num = 3;
++	else if (type == RF_4T4R)
++		tx_num = 4;
++	else
++		PHYDM_DBG(dm, DBG_RA, "[Warrning] no mimo_type is found\n");
++
++	return tx_num;
++}
++
++u64 phydm_get_bb_mod_ra_mask(void *dm_void, u8 sta_idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_iot_center	*iot_table = &dm->iot_table;
++	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
++	struct ra_sta_info *ra = NULL;
++	enum channel_width bw = 0;
++	enum wireless_set wrls_mode = 0;
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	struct rtl8192cd_priv *priv = dm->priv;
++#endif
++	u8 tx_stream_num = 1;
++	u8 rssi_lv = 0;
++	u64 ra_mask_bitmap = 0;
++
++	if (is_sta_active(sta)) {
++		ra = &sta->ra_info;
++		bw = ra->ra_bw_mode;
++		wrls_mode = sta->support_wireless_set;
++		tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type);
++		rssi_lv = ra->rssi_level;
++		ra_mask_bitmap = ra->ramask;
++	} else {
++		PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid STA\n", __func__);
++		return 0;
++	}
++
++	PHYDM_DBG(dm, DBG_RA, "macid=%d ori_RA_Mask= 0x%llx\n", sta->mac_id,
++		  ra_mask_bitmap);
++	PHYDM_DBG(dm, DBG_RA,
++		  "wireless_mode=0x%x, tx_ss=%d, BW=%d, MimoPs=%d, rssi_lv=%d\n",
++		  wrls_mode, tx_stream_num, bw, sta->sm_ps, rssi_lv);
++
++	if (sta->sm_ps == SM_PS_STATIC) /*@mimo_ps_enable*/
++		tx_stream_num = 1;
++
++	/*@[Modify RA Mask by Wireless Mode]*/
++
++	if (wrls_mode == WIRELESS_CCK) { /*@B mode*/
++		ra_mask_bitmap &= 0x0000000f;
++	} else if (wrls_mode == WIRELESS_OFDM) { /*@G mode*/
++		ra_mask_bitmap &= 0x00000ff0;
++	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) { /*@BG mode*/
++		ra_mask_bitmap &= 0x00000ff5;
++	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) {
++		/*N_2G*/
++		if (tx_stream_num == 1) {
++			if (bw == CHANNEL_WIDTH_40)
++				ra_mask_bitmap &= 0x000ff015;
++			else
++				ra_mask_bitmap &= 0x000ff005;
++		} else if (tx_stream_num == 2) {
++			if (bw == CHANNEL_WIDTH_40)
++				ra_mask_bitmap &= 0x0ffff015;
++			else
++				ra_mask_bitmap &= 0x0ffff005;
++		} else if (tx_stream_num == 3) {
++			ra_mask_bitmap &= 0xffffff015;
++		} else {
++			ra_mask_bitmap &= 0xffffffff015;
++		}
++	} else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) { /*N_5G*/
++
++		if (tx_stream_num == 1) {
++			if (bw == CHANNEL_WIDTH_40)
++				ra_mask_bitmap &= 0x000ff030;
++			else
++				ra_mask_bitmap &= 0x000ff010;
++		} else if (tx_stream_num == 2) {
++			if (bw == CHANNEL_WIDTH_40)
++				ra_mask_bitmap &= 0x0ffff030;
++			else
++				ra_mask_bitmap &= 0x0ffff010;
++		} else if (tx_stream_num == 3) {
++			ra_mask_bitmap &= 0xffffff010;
++		} else {
++			ra_mask_bitmap &= 0xffffffff010;
++		}
++	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) {
++		/*@AC_2G*/
++		if (tx_stream_num == 1)
++			ra_mask_bitmap &= 0x003ff015;
++		else if (tx_stream_num == 2)
++			ra_mask_bitmap &= 0xfffff015;
++		else if (tx_stream_num == 3)
++			ra_mask_bitmap &= 0x3fffffff015;
++		else /*@AC_4SS 2G*/
++			ra_mask_bitmap &= 0x000ffffffffff015;
++		if (bw == CHANNEL_WIDTH_20) {
++		/* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/
++			ra_mask_bitmap &= 0x0007ffff7fdff015;
++		} else if (bw == CHANNEL_WIDTH_80) {
++		/* @AC 80MHz doesn't support 3SS MCS6*/
++			ra_mask_bitmap &= 0x000fffbffffff015;
++		}
++	} else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) { /*@AC_5G*/
++
++		if (tx_stream_num == 1)
++			ra_mask_bitmap &= 0x003ff010;
++		else if (tx_stream_num == 2)
++			ra_mask_bitmap &= 0xfffff010;
++		else if (tx_stream_num == 3)
++			ra_mask_bitmap &= 0x3fffffff010;
++		else /*@AC_4SS 5G*/
++			ra_mask_bitmap &= 0x000ffffffffff010;
++
++		if (bw == CHANNEL_WIDTH_20) {
++		/* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/
++			ra_mask_bitmap &= 0x0007ffff7fdff010;
++		} else if (bw == CHANNEL_WIDTH_80) {
++		/* @AC 80MHz doesn't support 3SS MCS6*/
++			ra_mask_bitmap &= 0x000fffbffffff010;
++		} else if (bw == CHANNEL_WIDTH_160) {
++		/* @AC 80M+80M doesn't support 3SS & 4SS*/
++			ra_mask_bitmap &= 0xfffff010;
++		}
++	} else {
++		PHYDM_DBG(dm, DBG_RA, "[Warrning] RA mask is Not found\n");
++	}
++
++	PHYDM_DBG(dm, DBG_RA, "Mod by mode=0x%llx\n", ra_mask_bitmap);
++
++#if ((DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
++	if (priv->pshare->veriwave_sta_num > 0) {
++		PHYDM_DBG(dm, DBG_RA, "Mod by RSSI=0x%llx\n", ra_mask_bitmap);
++		return ra_mask_bitmap;
++	}
++#endif
++	/*@[Modify RA Mask by RSSI level]*/
++	if (wrls_mode != WIRELESS_CCK) {
++		if (iot_table->patch_id_40010700) {
++			ra_mask_bitmap &= (rssi_lv == 0 ?
++					  0xffffffffffffffff :
++					  0xfffffffffffffff0);
++			return ra_mask_bitmap;
++		}
++
++		if (rssi_lv == 0)
++			ra_mask_bitmap &= 0xffffffffffffffff;
++		else if (rssi_lv == 1)
++			ra_mask_bitmap &= 0xfffffffffffffff0;
++		else if (rssi_lv == 2)
++			ra_mask_bitmap &= 0xffffffffffffefe0;
++		else if (rssi_lv == 3)
++			ra_mask_bitmap &= 0xffffffffffffcfc0;
++		else if (rssi_lv == 4)
++			ra_mask_bitmap &= 0xffffffffffff8f80;
++		else if (rssi_lv >= 5)
++			ra_mask_bitmap &= 0xffffffffffff0f00;
++	}
++	PHYDM_DBG(dm, DBG_RA, "Mod by RSSI=0x%llx\n", ra_mask_bitmap);
++
++	return ra_mask_bitmap;
++}
++
++u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
++	struct ra_sta_info *ra = NULL;
++	enum wireless_set wrls_set = 0;
++	u8 rssi_lv = 0;
++	u8 rate_idx = 0;
++	u8 rate_ofst = 0;
++
++	if (is_sta_active(sta)) {
++		ra = &sta->ra_info;
++		wrls_set = sta->support_wireless_set;
++		rssi_lv = ra->rssi_level;
++	} else {
++		pr_debug("[Warning] %s: invalid STA\n", __func__);
++		return 0;
++	}
++
++	PHYDM_DBG(dm, DBG_RA, "[%s]macid=%d, wireless_set=0x%x, rssi_lv=%d\n",
++		  __func__, sta->mac_id, wrls_set, rssi_lv);
++
++	rate_ofst = (rssi_lv <= 1) ? 0 : (rssi_lv - 1);
++
++	if (wrls_set & WIRELESS_VHT) {
++		rate_idx = ODM_RATEVHTSS1MCS0 + rate_ofst;
++	} else if (wrls_set & WIRELESS_HT) {
++		rate_idx = ODM_RATEMCS0 + rate_ofst;
++	} else if (wrls_set & WIRELESS_OFDM) {
++		rate_idx = ODM_RATE6M + rate_ofst;
++	} else {
++		rate_idx = ODM_RATE1M + rate_ofst;
++
++		if (rate_idx > ODM_RATE11M)
++			rate_idx = ODM_RATE11M;
++	}
++	return rate_idx;
++}
++
++u8 phydm_get_rate_id(void *dm_void, u8 sta_idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
++	struct ra_sta_info *ra = NULL;
++	enum channel_width bw = 0;
++	enum wireless_set wrls_mode = 0;
++	u8 tx_stream_num = 1;
++	u8 rate_id_idx = PHYDM_BGN_20M_1SS;
++
++	if (is_sta_active(sta)) {
++		ra = &sta->ra_info;
++		bw = ra->ra_bw_mode;
++		wrls_mode = sta->support_wireless_set;
++		tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type);
++
++	} else {
++		PHYDM_DBG(dm, DBG_RA, "[Warning] %s: invalid STA\n", __func__);
++		return 0;
++	}
++
++	PHYDM_DBG(dm, DBG_RA, "macid=%d,wireless_set=0x%x,tx_SS_num=%d,BW=%d\n",
++		  sta->mac_id, wrls_mode, tx_stream_num, bw);
++
++	if (wrls_mode == WIRELESS_CCK) {
++	/*@B mode*/
++		rate_id_idx = PHYDM_B_20M;
++	} else if (wrls_mode == WIRELESS_OFDM) {
++	/*@G mode*/
++		rate_id_idx = PHYDM_G;
++	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) {
++	/*@BG mode*/
++		rate_id_idx = PHYDM_BG;
++	} else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) {
++	/*@GN mode*/
++		if (tx_stream_num == 1)
++			rate_id_idx = PHYDM_GN_N1SS;
++		else if (tx_stream_num == 2)
++			rate_id_idx = PHYDM_GN_N2SS;
++		else if (tx_stream_num == 3)
++			rate_id_idx = PHYDM_ARFR5_N_3SS;
++	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) {
++	 /*@BGN mode*/
++		if (bw == CHANNEL_WIDTH_40) {
++			if (tx_stream_num == 1)
++				rate_id_idx = PHYDM_BGN_40M_1SS;
++			else if (tx_stream_num == 2)
++				rate_id_idx = PHYDM_BGN_40M_2SS;
++			else if (tx_stream_num == 3)
++				rate_id_idx = PHYDM_ARFR5_N_3SS;
++			else if (tx_stream_num == 4)
++				rate_id_idx = PHYDM_ARFR7_N_4SS;
++
++		} else {
++			if (tx_stream_num == 1)
++				rate_id_idx = PHYDM_BGN_20M_1SS;
++			else if (tx_stream_num == 2)
++				rate_id_idx = PHYDM_BGN_20M_2SS;
++			else if (tx_stream_num == 3)
++				rate_id_idx = PHYDM_ARFR5_N_3SS;
++			else if (tx_stream_num == 4)
++				rate_id_idx = PHYDM_ARFR7_N_4SS;
++		}
++	} else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) {
++	/*@AC mode*/
++		if (bw == CHANNEL_WIDTH_160) {
++			if (tx_stream_num == 1)
++				rate_id_idx = PHYDM_ARFR1_AC_1SS;
++			else if (tx_stream_num == 2)
++				rate_id_idx = PHYDM_ARFR0_AC_2SS;
++			else if (tx_stream_num == 3)
++				rate_id_idx = PHYDM_ARFR0_AC_2SS;
++			else if (tx_stream_num == 4)
++				rate_id_idx = PHYDM_ARFR0_AC_2SS;
++		} else {
++			if (tx_stream_num == 1)
++				rate_id_idx = PHYDM_ARFR1_AC_1SS;
++			else if (tx_stream_num == 2)
++				rate_id_idx = PHYDM_ARFR0_AC_2SS;
++			else if (tx_stream_num == 3)
++				rate_id_idx = PHYDM_ARFR4_AC_3SS;
++			else if (tx_stream_num == 4)
++				rate_id_idx = PHYDM_ARFR6_AC_4SS;
++			}
++	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) {
++	/*@AC 2.4G mode*/
++		if (bw >= CHANNEL_WIDTH_80) {
++			if (tx_stream_num == 1)
++				rate_id_idx = PHYDM_ARFR1_AC_1SS;
++			else if (tx_stream_num == 2)
++				rate_id_idx = PHYDM_ARFR0_AC_2SS;
++			else if (tx_stream_num == 3)
++				rate_id_idx = PHYDM_ARFR4_AC_3SS;
++			else if (tx_stream_num == 4)
++				rate_id_idx = PHYDM_ARFR6_AC_4SS;
++		} else {
++			if (tx_stream_num == 1)
++				rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
++			else if (tx_stream_num == 2)
++				rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
++			else if (tx_stream_num == 3)
++				rate_id_idx = PHYDM_ARFR4_AC_3SS;
++			else if (tx_stream_num == 4)
++				rate_id_idx = PHYDM_ARFR6_AC_4SS;
++		}
++	} else {
++		PHYDM_DBG(dm, DBG_RA, "[Warrning] No rate_id is found\n");
++		rate_id_idx = 0;
++	}
++
++	PHYDM_DBG(dm, DBG_RA, "Rate_ID=((0x%x))\n", rate_id_idx);
++
++	return rate_id_idx;
++}
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++void phydm_ra_mode_selection(void *dm_void, u8 mode)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_tab = &dm->dm_ra_table;
++	u8 pre_mode = ra_tab->ra_trigger_mode; /* 0:pkt RA, 1:TBTT RA */
++
++	if (mode >= 2) {
++		PHYDM_DBG(dm, DBG_RA, "RA mode selection Fail\n");
++	} else {
++		ra_tab->ra_trigger_mode = mode;
++		PHYDM_DBG(dm, DBG_RA, "RA mode, 0:pkt RA, 1:TBTT RA\n");
++		PHYDM_DBG(dm, DBG_RA, "PreMode=%d,CurMode=%d\n", pre_mode,
++			  mode);
++	}
++}
++#endif
++
++void phydm_ra_h2c(void *dm_void, u8 sta_idx, u8 dis_ra, u8 dis_pt,
++		  u8 no_update_bw, u8 init_ra_lv, u64 ra_mask)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
++	struct ra_sta_info *ra = NULL;
++	u8 h2c_val[H2C_MAX_LENGTH] = {0};
++
++	if (is_sta_active(sta)) {
++		ra = &sta->ra_info;
++	} else {
++		PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid sta_info\n",
++			  __func__);
++		return;
++	}
++
++	PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__);
++	PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id);
++
++	if (dm->is_disable_power_training)
++		dis_pt = true;
++	else if (!dm->is_disable_power_training)
++		dis_pt = false;
++
++	h2c_val[0] = sta->mac_id;
++	h2c_val[1] = (ra->rate_id & 0x1f) | ((init_ra_lv & 0x3) << 5) |
++		     (ra->is_support_sgi << 7);
++	h2c_val[2] = (u8)((ra->ra_bw_mode) | (((sta->ldpc_en) ? 1 : 0) << 2) |
++			  ((no_update_bw & 0x1) << 3) |
++			  (ra->is_vht_enable << 4) |
++			  ((dis_pt & 0x1) << 6) | ((dis_ra & 0x1) << 7));
++
++	h2c_val[3] = (u8)(ra_mask & 0xff);
++	h2c_val[4] = (u8)((ra_mask & 0xff00) >> 8);
++	h2c_val[5] = (u8)((ra_mask & 0xff0000) >> 16);
++	h2c_val[6] = (u8)((ra_mask & 0xff000000) >> 24);
++
++	PHYDM_DBG(dm, DBG_RA, "PHYDM h2c[0x40]=0x%x %x %x %x %x %x %x\n",
++		  h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2],
++		  h2c_val[1], h2c_val[0]);
++
++	odm_fill_h2c_cmd(dm, PHYDM_H2C_RA_MASK, H2C_MAX_LENGTH, h2c_val);
++
++	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
++	if (dm->support_ic_type & (PHYDM_IC_ABOVE_3SS)) {
++		h2c_val[3] = (u8)((ra_mask >> 32) & 0x000000ff);
++		h2c_val[4] = (u8)(((ra_mask >> 32) & 0x0000ff00) >> 8);
++		h2c_val[5] = (u8)(((ra_mask >> 32) & 0x00ff0000) >> 16);
++		h2c_val[6] = (u8)(((ra_mask >> 32) & 0xff000000) >> 24);
++
++		PHYDM_DBG(dm, DBG_RA, "h2c[0x46]=0x%x %x %x %x %x %x %x\n",
++			  h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3],
++			  h2c_val[2], h2c_val[1], h2c_val[0]);
++
++		odm_fill_h2c_cmd(dm, PHYDM_RA_MASK_ABOVE_3SS,
++				 H2C_MAX_LENGTH, h2c_val);
++	}
++	#endif
++}
++
++void phydm_ra_registed(void *dm_void, u8 sta_idx,
++		       /*@index of sta_info array, not MACID*/
++		       u8 rssi_from_assoc)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_t = &dm->dm_ra_table;
++	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
++	struct ra_sta_info *ra = NULL;
++	u8 init_ra_lv = 0;
++	u64 ra_mask = 0;
++	/*@SD7 STA_idx != macid*/
++	/*@SD4,8 STA_idx == macid, */
++
++	PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
++
++	if (is_sta_active(sta)) {
++		ra = &sta->ra_info;
++		PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d, macid=%d\n", sta_idx,
++			  sta->mac_id);
++	} else {
++		PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid STA\n",
++			  __func__);
++		PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d\n", sta_idx);
++		return;
++	}
++
++	#if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8188E)
++		ra->rate_id = phydm_get_rate_id_88e(dm, sta_idx);
++	else
++	#endif
++	{
++		ra->rate_id = phydm_get_rate_id(dm, sta_idx);
++	}
++
++	ra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx);
++
++	PHYDM_DBG(dm, DBG_RA_MASK, "rssi_assoc=%d\n", rssi_from_assoc);
++
++	if (rssi_from_assoc > 40)
++		init_ra_lv = 1;
++	else if (rssi_from_assoc > 20)
++		init_ra_lv = 2;
++	else if (rssi_from_assoc > 1)
++		init_ra_lv = 3;
++	else
++		init_ra_lv = 0;
++
++	if (ra_t->record_ra_info)
++		ra_t->record_ra_info(dm, sta_idx, sta, ra_mask);
++
++	#if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8188E)
++		/*@Driver RA*/
++		phydm_ra_update_8188e(dm, sta_idx, ra->rate_id,
++				      (u32)ra_mask, ra->is_support_sgi);
++	else
++	#endif
++	{
++		/*@FW RA*/
++		phydm_ra_h2c(dm, sta_idx, ra->disable_ra, ra->disable_pt, 0,
++			     init_ra_lv, ra_mask);
++	}
++}
++
++void phydm_ra_offline(void *dm_void, u8 sta_idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_t = &dm->dm_ra_table;
++	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
++	struct ra_sta_info *ra = NULL;
++
++	if (is_sta_active(sta)) {
++		ra = &sta->ra_info;
++	} else {
++		PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid STA\n", __func__);
++		return;
++	}
++
++	PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__);
++	PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id);
++
++	odm_memory_set(dm, &ra->rate_id, 0, sizeof(struct ra_sta_info));
++	ra->disable_ra = 1;
++	ra->disable_pt = 1;
++
++	if (ra_t->record_ra_info)
++		ra_t->record_ra_info(dm, sta->mac_id, sta, 0);
++
++	if (dm->support_ic_type != ODM_RTL8188E)
++		phydm_ra_h2c(dm, sta->mac_id, 1, 1, 0, 0, 0);
++}
++
++void phydm_ra_mask_watchdog(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_t = &dm->dm_ra_table;
++	struct cmn_sta_info *sta = NULL;
++	struct ra_sta_info *ra = NULL;
++	boolean force_ra_mask_en = false;
++	u8 sta_idx;
++	u64 ra_mask;
++	u8 rssi_lv_new;
++	u8 rssi = 0;
++
++	if (!(dm->support_ability & ODM_BB_RA_MASK))
++		return;
++
++	if (!dm->is_linked || (dm->phydm_sys_up_time % 2) == 1)
++		return;
++
++	PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
++
++	ra_t->up_ramask_cnt++;
++
++	if (ra_t->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD) {
++		ra_t->up_ramask_cnt = 0;
++		force_ra_mask_en = true;
++	}
++
++	for (sta_idx = 0; sta_idx < ODM_ASSOCIATE_ENTRY_NUM; sta_idx++) {
++		sta = dm->phydm_sta_info[sta_idx];
++
++		if (!is_sta_active(sta))
++			continue;
++
++		ra = &sta->ra_info;
++
++		if (ra->disable_ra)
++			continue;
++
++		PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d, macid=%d\n", sta_idx,
++			  sta->mac_id);
++
++		rssi = (u8)(sta->rssi_stat.rssi);
++
++		/*@to be modified*/
++		#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
++		if (dm->support_ic_type == ODM_RTL8812 ||
++			(dm->support_ic_type == ODM_RTL8821 &&
++			 dm->cut_version == ODM_CUT_A)
++			) {
++			if (rssi < ra_t->ldpc_thres) {
++				/*@LDPC TX enable*/
++				#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++				set_ra_ldpc_8812(sta, true);
++				#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++				MgntSet_TX_LDPC(dm->adapter, sta->mac_id, true);
++				#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++				/*to be added*/
++				#endif
++				PHYDM_DBG(dm, DBG_RA_MASK,
++					  "RSSI=%d, ldpc_en =TRUE\n", rssi);
++
++			} else if (rssi > (ra_t->ldpc_thres + 3)) {
++				/*@LDPC TX disable*/
++				#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++				set_ra_ldpc_8812(sta, false);
++				#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++				MgntSet_TX_LDPC(dm->adapter, sta->mac_id, false);
++				#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++				/*to be added*/
++				#endif
++				PHYDM_DBG(dm, DBG_RA_MASK,
++					  "RSSI=%d, ldpc_en =FALSE\n", rssi);
++			}
++		}
++		#endif
++
++		rssi_lv_new = phydm_rssi_lv_dec(dm, (u32)rssi, ra->rssi_level);
++
++		if (ra->rssi_level != rssi_lv_new ||
++		    (force_ra_mask_en && dm->number_linked_client < 10)) {
++			PHYDM_DBG(dm, DBG_RA_MASK, "RSSI LV:((%d))->((%d))\n",
++				  ra->rssi_level, rssi_lv_new);
++
++			ra->rssi_level = rssi_lv_new;
++
++			ra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx);
++
++			if (ra_t->record_ra_info)
++				ra_t->record_ra_info(dm, sta_idx, sta, ra_mask);
++
++			#if (RTL8188E_SUPPORT) && (RATE_ADAPTIVE_SUPPORT)
++			if (dm->support_ic_type == ODM_RTL8188E)
++				/*@Driver RA*/
++				phydm_ra_update_8188e(dm, sta_idx, ra->rate_id,
++						      (u32)ra_mask,
++						      ra->is_support_sgi);
++			else
++			#endif
++			{
++				/*@FW RA*/
++				phydm_ra_h2c(dm, sta_idx, ra->disable_ra,
++					     ra->disable_pt, 1, 0, ra_mask);
++			}
++		}
++	}
++}
++
++u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 vht_en_out = 0;
++
++	if (wireless_mode == PHYDM_WIRELESS_MODE_AC_5G ||
++	    wireless_mode == PHYDM_WIRELESS_MODE_AC_24G ||
++	    wireless_mode == PHYDM_WIRELESS_MODE_AC_ONLY)
++		vht_en_out = 1;
++
++	PHYDM_DBG(dm, DBG_RA, "wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n",
++		  wireless_mode, vht_en_out);
++	return vht_en_out;
++}
++
++u8 phydm_rftype2rateid_2g_n20(void *dm_void, u8 rf_type)
++{
++	u8 rate_id_idx = 0;
++
++	if (rf_type == RF_1T1R)
++		rate_id_idx = PHYDM_BGN_20M_1SS;
++	else if (rf_type == RF_2T2R)
++		rate_id_idx = PHYDM_BGN_20M_2SS;
++	else if (rf_type == RF_3T3R)
++		rate_id_idx = PHYDM_ARFR5_N_3SS;
++	else
++		rate_id_idx = PHYDM_ARFR7_N_4SS;
++	return rate_id_idx;
++}
++
++u8 phydm_rftype2rateid_2g_n40(void *dm_void, u8 rf_type)
++{
++	u8 rate_id_idx = 0;
++
++	if (rf_type == RF_1T1R)
++		rate_id_idx = PHYDM_BGN_40M_1SS;
++	else if (rf_type == RF_2T2R)
++		rate_id_idx = PHYDM_BGN_40M_2SS;
++	else if (rf_type == RF_3T3R)
++		rate_id_idx = PHYDM_ARFR5_N_3SS;
++	else
++		rate_id_idx = PHYDM_ARFR7_N_4SS;
++	return rate_id_idx;
++}
++
++u8 phydm_rftype2rateid_5g_n(void *dm_void, u8 rf_type)
++{
++	u8 rate_id_idx = 0;
++
++	if (rf_type == RF_1T1R)
++		rate_id_idx = PHYDM_GN_N1SS;
++	else if (rf_type == RF_2T2R)
++		rate_id_idx = PHYDM_GN_N2SS;
++	else if (rf_type == RF_3T3R)
++		rate_id_idx = PHYDM_ARFR5_N_3SS;
++	else
++		rate_id_idx = PHYDM_ARFR7_N_4SS;
++	return rate_id_idx;
++}
++
++u8 phydm_rftype2rateid_ac80(void *dm_void, u8 rf_type)
++{
++	u8 rate_id_idx = 0;
++
++	if (rf_type == RF_1T1R)
++		rate_id_idx = PHYDM_ARFR1_AC_1SS;
++	else if (rf_type == RF_2T2R)
++		rate_id_idx = PHYDM_ARFR0_AC_2SS;
++	else if (rf_type == RF_3T3R)
++		rate_id_idx = PHYDM_ARFR4_AC_3SS;
++	else
++		rate_id_idx = PHYDM_ARFR6_AC_4SS;
++	return rate_id_idx;
++}
++
++u8 phydm_rftype2rateid_ac40(void *dm_void, u8 rf_type)
++{
++	u8 rate_id_idx = 0;
++
++	if (rf_type == RF_1T1R)
++		rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
++	else if (rf_type == RF_2T2R)
++		rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
++	else if (rf_type == RF_3T3R)
++		rate_id_idx = PHYDM_ARFR4_AC_3SS;
++	else
++		rate_id_idx = PHYDM_ARFR6_AC_4SS;
++	return rate_id_idx;
++}
++
++u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 rate_id_idx = 0;
++
++	PHYDM_DBG(dm, DBG_RA,
++		  "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n",
++		  wireless_mode, rf_type, bw);
++
++	switch (wireless_mode) {
++	case PHYDM_WIRELESS_MODE_N_24G:
++		if (bw == CHANNEL_WIDTH_40)
++			rate_id_idx = phydm_rftype2rateid_2g_n40(dm, rf_type);
++		else
++			rate_id_idx = phydm_rftype2rateid_2g_n20(dm, rf_type);
++		break;
++
++	case PHYDM_WIRELESS_MODE_N_5G:
++		rate_id_idx = phydm_rftype2rateid_5g_n(dm, rf_type);
++		break;
++
++	case PHYDM_WIRELESS_MODE_G:
++		rate_id_idx = PHYDM_BG;
++		break;
++
++	case PHYDM_WIRELESS_MODE_A:
++		rate_id_idx = PHYDM_G;
++		break;
++
++	case PHYDM_WIRELESS_MODE_B:
++		rate_id_idx = PHYDM_B_20M;
++		break;
++
++	case PHYDM_WIRELESS_MODE_AC_5G:
++	case PHYDM_WIRELESS_MODE_AC_ONLY:
++		rate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type);
++		break;
++
++	case PHYDM_WIRELESS_MODE_AC_24G:
++/*@Becareful to set "Lowest rate" while using PHYDM_ARFR4_AC_3SS in 2.4G/5G*/
++		if (bw >= CHANNEL_WIDTH_80)
++			rate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type);
++		else
++			rate_id_idx = phydm_rftype2rateid_ac40(dm, rf_type);
++		break;
++
++	default:
++		rate_id_idx = 0;
++		break;
++	}
++
++	PHYDM_DBG(dm, DBG_RA, "RA rate ID = (( 0x%x ))\n", rate_id_idx);
++
++	return rate_id_idx;
++}
++
++u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	/*@MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/
++	u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100};
++	u8 new_rssi_lv = 0;
++	u8 i;
++
++	PHYDM_DBG(dm, DBG_RA_MASK,
++		  "curr RA level=(%d), Table_ori=[%d, %d, %d, %d, %d, %d]\n",
++		  ratr_state, rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2],
++		  rssi_lv_t[3], rssi_lv_t[4], rssi_lv_t[5]);
++
++	for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
++		if (i >= (ratr_state))
++			rssi_lv_t[i] += RA_FLOOR_UP_GAP;
++	}
++
++	PHYDM_DBG(dm, DBG_RA_MASK,
++		  "RSSI=(%d), Table_mod=[%d, %d, %d, %d, %d, %d]\n", rssi,
++		  rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2], rssi_lv_t[3],
++		  rssi_lv_t[4], rssi_lv_t[5]);
++
++	for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
++		if (rssi < rssi_lv_t[i]) {
++			new_rssi_lv = i;
++			break;
++		}
++	}
++	return new_rssi_lv;
++}
++
++enum phydm_qam_order phydm_get_ofdm_qam_order(void *dm_void, u8 rate_idx)
++{
++	u8 tmp_idx = rate_idx;
++	enum phydm_qam_order qam_order = PHYDM_QAM_BPSK;
++	enum phydm_qam_order qam[10] = {PHYDM_QAM_BPSK, PHYDM_QAM_QPSK,
++					PHYDM_QAM_QPSK, PHYDM_QAM_16QAM,
++					PHYDM_QAM_16QAM, PHYDM_QAM_64QAM,
++					PHYDM_QAM_64QAM, PHYDM_QAM_64QAM,
++					PHYDM_QAM_256QAM, PHYDM_QAM_256QAM};
++
++	if (rate_idx <= ODM_RATE11M)
++		return PHYDM_QAM_CCK;
++
++	if (rate_idx >= ODM_RATEVHTSS1MCS0) {
++		if (rate_idx >= ODM_RATEVHTSS4MCS0)
++			tmp_idx -= ODM_RATEVHTSS4MCS0;
++		else if (rate_idx >= ODM_RATEVHTSS3MCS0)
++			tmp_idx -= ODM_RATEVHTSS3MCS0;
++		else if (rate_idx >= ODM_RATEVHTSS2MCS0)
++			tmp_idx -= ODM_RATEVHTSS2MCS0;
++		else
++			tmp_idx -= ODM_RATEVHTSS1MCS0;
++
++		qam_order = qam[tmp_idx];
++	} else if (rate_idx >= ODM_RATEMCS0) {
++		if (rate_idx >= ODM_RATEMCS24)
++			tmp_idx -= ODM_RATEMCS24;
++		else if (rate_idx >= ODM_RATEMCS16)
++			tmp_idx -= ODM_RATEMCS16;
++		else if (rate_idx >= ODM_RATEMCS8)
++			tmp_idx -= ODM_RATEMCS8;
++		else
++			tmp_idx -= ODM_RATEMCS0;
++
++		qam_order = qam[tmp_idx];
++	} else {
++		if (rate_idx > ODM_RATE6M) {
++			tmp_idx -= ODM_RATE6M;
++			qam_order = qam[tmp_idx - 1];
++		} else {
++			qam_order = PHYDM_QAM_BPSK;
++		}
++	}
++
++	return qam_order;
++}
++
++u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx)
++{
++	u8 rate_order = rate_idx & 0x7f;
++
++	rate_idx &= 0x7f;
++
++	if (rate_idx >= ODM_RATEVHTSS4MCS0)
++		rate_order -= ODM_RATEVHTSS4MCS0;
++	else if (rate_idx >= ODM_RATEVHTSS3MCS0)
++		rate_order -= ODM_RATEVHTSS3MCS0;
++	else if (rate_idx >= ODM_RATEVHTSS2MCS0)
++		rate_order -= ODM_RATEVHTSS2MCS0;
++	else if (rate_idx >= ODM_RATEVHTSS1MCS0)
++		rate_order -= ODM_RATEVHTSS1MCS0;
++	else if (rate_idx >= ODM_RATEMCS24)
++		rate_order -= ODM_RATEMCS24;
++	else if (rate_idx >= ODM_RATEMCS16)
++		rate_order -= ODM_RATEMCS16;
++	else if (rate_idx >= ODM_RATEMCS8)
++		rate_order -= ODM_RATEMCS8;
++	else if (rate_idx >= ODM_RATEMCS0)
++		rate_order -= ODM_RATEMCS0;
++	else if (rate_idx >= ODM_RATE6M)
++		rate_order -= ODM_RATE6M;
++	else
++		rate_order -= ODM_RATE1M;
++
++	if (rate_idx >= ODM_RATEMCS0)
++		rate_order++;
++
++	return rate_order;
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++u8 phydm_rate2ss(void *dm_void, u8 rate_idx)
++{
++	u8 ret = 0xff;
++	u8 i, j;
++	u8 search_idx;
++	u32 ss_mapping_tab[4][3] = {{0x00000000, 0x003ff000, 0x000ff000},
++				    {0x00000000, 0xffc00000, 0x0ff00000},
++				    {0x000003ff, 0x0000000f, 0xf0000000},
++				    {0x000ffc00, 0x00000ff0, 0x00000000} };
++	if (rate_idx < 32) {
++		search_idx = rate_idx;
++		j = 0;
++	} else if (rate_idx < 64) {
++		search_idx = rate_idx - 32;
++		j = 1;
++	} else {
++		search_idx = rate_idx - 64;
++		j = 2;
++	}
++	for (i = 0; i < 4; i++)
++		if (ss_mapping_tab[i][j] & BIT(search_idx))
++			ret = i;
++	return ret;
++}
++
++u8 phydm_rate2plcp(void *dm_void, u8 rate_idx)
++{
++	u8 rate2ss = 0;
++	u8 ltftime = 0;
++	u8 plcptime = 0xff;
++
++	if (rate_idx < ODM_RATE6M) {
++		plcptime = 192;
++		/* @CCK PLCP = 192us (long preamble) */
++	} else if (rate_idx < ODM_RATEMCS0) {
++		plcptime = 20;
++		/* @LegOFDM PLCP = 20us */
++	} else {
++		if (rate_idx < ODM_RATEVHTSS1MCS0)
++			plcptime = 32;
++		/* @HT mode PLCP = 20us + 12us + 4us x Nss */
++		else
++			plcptime = 36;
++		/* VHT mode PLCP = 20us + 16us + 4us x Nss */
++		rate2ss = phydm_rate2ss(dm_void, rate_idx);
++		if (rate2ss != 0xff)
++			ltftime = (rate2ss + 1) * 4;
++		else
++			return 0xff;
++
++		plcptime += ltftime;
++	}
++	return plcptime;
++}
++
++u8 phydm_get_plcp(void *dm_void, u16 macid)
++{
++	u8 plcp_time = 0;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *sta = NULL;
++	struct ra_sta_info *ra = NULL;
++
++	sta = dm->phydm_sta_info[macid];
++	ra = &sta->ra_info;
++	plcp_time = phydm_rate2plcp(dm, ra->curr_tx_rate);
++	return plcp_time;
++}
++#endif
++
++void phydm_ra_common_info_update(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_tab = &dm->dm_ra_table;
++	struct cmn_sta_info *sta = NULL;
++	u16 macid;
++	u8 rate_order_tmp;
++	u8 rate_idx = 0;
++	u8 cnt = 0;
++
++	ra_tab->highest_client_tx_order = 0;
++	ra_tab->power_tracking_flag = 1;
++
++	if (!dm->number_linked_client)
++		return;
++
++	for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
++		sta = dm->phydm_sta_info[macid];
++
++		if (!is_sta_active(sta))
++			continue;
++
++		rate_idx = sta->ra_info.curr_tx_rate & 0x7f;
++		rate_order_tmp = phydm_rate_order_compute(dm, rate_idx);
++
++		if (rate_order_tmp >= ra_tab->highest_client_tx_order) {
++			ra_tab->highest_client_tx_order = rate_order_tmp;
++			ra_tab->highest_client_tx_rate_order = macid;
++		}
++
++		cnt++;
++
++		if (cnt == dm->number_linked_client)
++			break;
++	}
++	PHYDM_DBG(dm, DBG_RA,
++		  "MACID[%d], Highest Tx order Update for power traking: %d\n",
++		  ra_tab->highest_client_tx_rate_order,
++		  ra_tab->highest_client_tx_order);
++}
++
++void phydm_rrsr_set_register(void *dm_void, u32 rrsr_val)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	odm_set_mac_reg(dm, R_0x440, 0xfffff, rrsr_val);
++}
++
++void phydm_masked_rrsr_set_register(void *dm_void, u32 rrsr_val)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_tab = &dm->dm_ra_table;
++
++	if (ra_tab->rrsr_val_curr == rrsr_val)
++		return;
++
++	ra_tab->rrsr_val_curr = rrsr_val;
++	odm_set_mac_reg(dm, R_0x440, 0xfffff, rrsr_val);
++}
++
++void phydm_rrsr_mask(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra = &dm->dm_ra_table;
++	struct cmn_sta_info *sta = NULL;
++	u8 rate_order = 0;
++	u8 rate_order_min = 0xff;
++	u32 rrsr_mask = 0, rrsr_mask_ofdm = 0;
++	u8 tx_rate_idx = 0;
++	u8 i = 0, sta_cnt = 0;
++
++	if (!ra->dynamic_rrsr_en)
++		return;
++
++	if (!dm->is_linked) {
++		phydm_masked_rrsr_set_register(dm, ra->rrsr_val_init);
++		return;
++	}
++
++#if 1
++	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
++		sta = dm->phydm_sta_info[i];
++		if (!is_sta_active(sta))
++			continue;
++
++		sta_cnt++;
++		tx_rate_idx = sta->ra_info.curr_tx_rate & 0x7f;
++		rate_order = phydm_rate_order_compute(dm, tx_rate_idx);
++		if (rate_order < rate_order_min)
++			rate_order_min = rate_order;
++
++		if (sta_cnt == dm->number_linked_client)
++			break;
++	}
++#else
++	sta = dm->phydm_sta_info[dm->rssi_min_macid];
++
++	if (!is_sta_active(sta)) {
++		PHYDM_DBG(dm, DBG_DYN_ARFR, "[Warning] %s invalid STA\n",
++			  __func__);
++		return;
++	}
++
++	rate_order = phydm_rate_order_compute(dm, sta->ra_info.curr_tx_rate);
++#endif
++	if (rate_order_min == 0) {
++		rrsr_mask = 0x1f;
++	} else {
++		rrsr_mask_ofdm = (u32)phydm_gen_bitmask(rate_order_min);
++		rrsr_mask = (rrsr_mask_ofdm << 4) | 0xf;
++	}
++
++	/*ra->rrsr_val_init = 0x15d;*/
++
++	phydm_masked_rrsr_set_register(dm, ra->rrsr_val_init & rrsr_mask);
++
++	PHYDM_DBG(dm, DBG_DYN_ARFR,
++		  "tx{rate, rate_order_min}={0x%x, %d}, rrsr_init=0x%x, ofdm_rrsr_mask=0x%x, rrsr_val=0x%x\n",
++		  tx_rate_idx, rate_order_min, ra->rrsr_val_init,
++		  rrsr_mask, ra->rrsr_val_curr);
++}
++
++void phydm_ra_info_watchdog(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	phydm_ra_common_info_update(dm);
++	phydm_ra_dynamic_retry_count(dm);
++	phydm_rrsr_mask(dm);
++	phydm_ra_mask_watchdog(dm);
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	odm_refresh_basic_rate_mask(dm);
++#endif
++}
++
++void phydm_rrsr_en(void *dm_void, boolean en_rrsr)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_tab = &dm->dm_ra_table;
++
++	ra_tab->dynamic_rrsr_en = en_rrsr;
++}
++
++void phydm_ra_info_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_tab = &dm->dm_ra_table;
++
++	ra_tab->highest_client_tx_rate_order = 0;
++	ra_tab->highest_client_tx_order = 0;
++	ra_tab->ra_th_ofst = 0;
++	ra_tab->ra_ofst_direc = 0;
++	ra_tab->rrsr_val_init = odm_get_mac_reg(dm, R_0x440, MASKDWORD);
++	ra_tab->ra_trigger_mode = 0;
++	ra_tab->ra_tx_cls_th = 255;
++#if (RTL8822B_SUPPORT == 1)
++	if (dm->support_ic_type == ODM_RTL8822B) {
++		u32 ret_value;
++
++		ret_value = odm_get_mac_reg(dm, R_0x4c8, MASKBYTE2);
++		odm_set_mac_reg(dm, R_0x4cc, MASKBYTE3, (ret_value - 1));
++	}
++#endif
++
++	#if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
++	phydm_ra_dynamic_retry_limit_init(dm);
++	#endif
++
++	#if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/
++	phydm_ra_dynamic_rate_id_init(dm);
++	#endif
++
++	phydm_rate_adaptive_mask_init(dm);
++}
++
++u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 rts_ini_rate = ODM_RATE6M;
++
++	if (is_erp_protect) { /* use CCK rate as RTS*/
++		rts_ini_rate = ODM_RATE1M;
++	} else {
++		switch (tx_rate) {
++		case ODM_RATEVHTSS4MCS9:
++		case ODM_RATEVHTSS4MCS8:
++		case ODM_RATEVHTSS4MCS7:
++		case ODM_RATEVHTSS4MCS6:
++		case ODM_RATEVHTSS4MCS5:
++		case ODM_RATEVHTSS4MCS4:
++		case ODM_RATEVHTSS4MCS3:
++		case ODM_RATEVHTSS3MCS9:
++		case ODM_RATEVHTSS3MCS8:
++		case ODM_RATEVHTSS3MCS7:
++		case ODM_RATEVHTSS3MCS6:
++		case ODM_RATEVHTSS3MCS5:
++		case ODM_RATEVHTSS3MCS4:
++		case ODM_RATEVHTSS3MCS3:
++		case ODM_RATEVHTSS2MCS9:
++		case ODM_RATEVHTSS2MCS8:
++		case ODM_RATEVHTSS2MCS7:
++		case ODM_RATEVHTSS2MCS6:
++		case ODM_RATEVHTSS2MCS5:
++		case ODM_RATEVHTSS2MCS4:
++		case ODM_RATEVHTSS2MCS3:
++		case ODM_RATEVHTSS1MCS9:
++		case ODM_RATEVHTSS1MCS8:
++		case ODM_RATEVHTSS1MCS7:
++		case ODM_RATEVHTSS1MCS6:
++		case ODM_RATEVHTSS1MCS5:
++		case ODM_RATEVHTSS1MCS4:
++		case ODM_RATEVHTSS1MCS3:
++		case ODM_RATEMCS31:
++		case ODM_RATEMCS30:
++		case ODM_RATEMCS29:
++		case ODM_RATEMCS28:
++		case ODM_RATEMCS27:
++		case ODM_RATEMCS23:
++		case ODM_RATEMCS22:
++		case ODM_RATEMCS21:
++		case ODM_RATEMCS20:
++		case ODM_RATEMCS19:
++		case ODM_RATEMCS15:
++		case ODM_RATEMCS14:
++		case ODM_RATEMCS13:
++		case ODM_RATEMCS12:
++		case ODM_RATEMCS11:
++		case ODM_RATEMCS7:
++		case ODM_RATEMCS6:
++		case ODM_RATEMCS5:
++		case ODM_RATEMCS4:
++		case ODM_RATEMCS3:
++		case ODM_RATE54M:
++		case ODM_RATE48M:
++		case ODM_RATE36M:
++		case ODM_RATE24M:
++			rts_ini_rate = ODM_RATE24M;
++			break;
++		case ODM_RATEVHTSS4MCS2:
++		case ODM_RATEVHTSS4MCS1:
++		case ODM_RATEVHTSS3MCS2:
++		case ODM_RATEVHTSS3MCS1:
++		case ODM_RATEVHTSS2MCS2:
++		case ODM_RATEVHTSS2MCS1:
++		case ODM_RATEVHTSS1MCS2:
++		case ODM_RATEVHTSS1MCS1:
++		case ODM_RATEMCS26:
++		case ODM_RATEMCS25:
++		case ODM_RATEMCS18:
++		case ODM_RATEMCS17:
++		case ODM_RATEMCS10:
++		case ODM_RATEMCS9:
++		case ODM_RATEMCS2:
++		case ODM_RATEMCS1:
++		case ODM_RATE18M:
++		case ODM_RATE12M:
++			rts_ini_rate = ODM_RATE12M;
++			break;
++		case ODM_RATEVHTSS4MCS0:
++		case ODM_RATEVHTSS3MCS0:
++		case ODM_RATEVHTSS2MCS0:
++		case ODM_RATEVHTSS1MCS0:
++		case ODM_RATEMCS24:
++		case ODM_RATEMCS16:
++		case ODM_RATEMCS8:
++		case ODM_RATEMCS0:
++		case ODM_RATE9M:
++		case ODM_RATE6M:
++			rts_ini_rate = ODM_RATE6M;
++			break;
++		case ODM_RATE11M:
++		case ODM_RATE5_5M:
++		case ODM_RATE2M:
++		case ODM_RATE1M:
++			rts_ini_rate = ODM_RATE1M;
++			break;
++		default:
++			rts_ini_rate = ODM_RATE6M;
++			break;
++		}
++	}
++
++	if (*dm->band_type == ODM_BAND_5G) {
++		if (rts_ini_rate < ODM_RATE6M)
++			rts_ini_rate = ODM_RATE6M;
++	}
++	return rts_ini_rate;
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++
++void odm_refresh_basic_rate_mask(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	void *adapter = dm->adapter;
++	static u8 stage = 0;
++	u8 cur_stage = 0;
++	OCTET_STRING os_rate_set;
++	PMGNT_INFO mgnt_info = GetDefaultMgntInfo(((PADAPTER)adapter));
++	u8 rate_set[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M};
++
++	if (dm->support_ic_type != ODM_RTL8812 && dm->support_ic_type != ODM_RTL8821)
++		return;
++
++	if (dm->is_linked == false) /* unlink Default port information */
++		cur_stage = 0;
++	else if (dm->rssi_min < 40) /* @link RSSI  < 40% */
++		cur_stage = 1;
++	else if (dm->rssi_min > 45) /* @link RSSI > 45% */
++		cur_stage = 3;
++	else
++		cur_stage = 2; /* @link  25% <= RSSI <= 30% */
++
++	if (cur_stage != stage) {
++		if (cur_stage == 1) {
++			FillOctetString(os_rate_set, rate_set, 5);
++			FilterSupportRate(mgnt_info->mBrates, &os_rate_set, false);
++			phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)&os_rate_set);
++		} else if (cur_stage == 3 && (stage == 1 || stage == 2))
++			phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)(&mgnt_info->mBrates));
++	}
++
++	stage = cur_stage;
++}
++
++#endif
++
++#if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
++
++void phydm_retry_limit_table_bound(
++	void *dm_void,
++	u8 *retry_limit,
++	u8 offset)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_tab = &dm->dm_ra_table;
++
++	if (*retry_limit > offset) {
++		*retry_limit -= offset;
++
++		if (*retry_limit < ra_tab->retrylimit_low)
++			*retry_limit = ra_tab->retrylimit_low;
++		else if (*retry_limit > ra_tab->retrylimit_high)
++			*retry_limit = ra_tab->retrylimit_high;
++	} else
++		*retry_limit = ra_tab->retrylimit_low;
++}
++
++void phydm_reset_retry_limit_table(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_t = &dm->dm_ra_table;
++	u8 i;
++
++	u8 per_rate_retrylimit_table_20M[ODM_RATEMCS15 + 1] = {
++		1, 1, 2, 4, /*@CCK*/
++		2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/
++		2, 4, 6, 8, 12, 18, 20, 22, /*@20M HT-1SS*/
++		2, 4, 6, 8, 12, 18, 20, 22 /*@20M HT-2SS*/
++	};
++	u8 per_rate_retrylimit_table_40M[ODM_RATEMCS15 + 1] = {
++		1, 1, 2, 4, /*@CCK*/
++		2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/
++		4, 8, 12, 16, 24, 32, 32, 32, /*@40M HT-1SS*/
++		4, 8, 12, 16, 24, 32, 32, 32 /*@40M HT-2SS*/
++	};
++
++	memcpy(&ra_t->per_rate_retrylimit_20M[0],
++	       &per_rate_retrylimit_table_20M[0], PHY_NUM_RATE_IDX);
++	memcpy(&ra_t->per_rate_retrylimit_40M[0],
++	       &per_rate_retrylimit_table_40M[0], PHY_NUM_RATE_IDX);
++
++	for (i = 0; i < PHY_NUM_RATE_IDX; i++) {
++		phydm_retry_limit_table_bound(dm,
++					      &ra_t->per_rate_retrylimit_20M[i],
++					      0);
++		phydm_retry_limit_table_bound(dm,
++					      &ra_t->per_rate_retrylimit_40M[i],
++					      0);
++	}
++}
++
++void phydm_ra_dynamic_retry_limit_init(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_tab = &dm->dm_ra_table;
++
++	ra_tab->retry_descend_num = RA_RETRY_DESCEND_NUM;
++	ra_tab->retrylimit_low = RA_RETRY_LIMIT_LOW;
++	ra_tab->retrylimit_high = RA_RETRY_LIMIT_HIGH;
++
++	phydm_reset_retry_limit_table(dm);
++}
++
++void phydm_ra_dynamic_retry_limit(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_tab = &dm->dm_ra_table;
++	u8 i, retry_offset;
++	u32 ma_rx_tp;
++
++	if (dm->pre_number_active_client == dm->number_active_client) {
++		PHYDM_DBG(dm, DBG_RA,
++			  "pre_number_active_client ==  number_active_client\n");
++		return;
++
++	} else {
++		if (dm->number_active_client == 1) {
++			phydm_reset_retry_limit_table(dm);
++			PHYDM_DBG(dm, DBG_RA,
++				  "one client only->reset to default value\n");
++		} else {
++			retry_offset = dm->number_active_client * ra_tab->retry_descend_num;
++
++			for (i = 0; i < PHY_NUM_RATE_IDX; i++) {
++				phydm_retry_limit_table_bound(dm,
++							      &ra_tab->per_rate_retrylimit_20M[i],
++							      retry_offset);
++				phydm_retry_limit_table_bound(dm,
++							      &ra_tab->per_rate_retrylimit_40M[i],
++							      retry_offset);
++			}
++		}
++	}
++}
++#endif
++
++#if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/
++void phydm_ra_dynamic_rate_id_on_assoc(
++	void *dm_void,
++	u8 wireless_mode,
++	u8 init_rate_id)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_RA,
++		  "[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n",
++		  dm->rf_type, wireless_mode, init_rate_id);
++
++	if (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) {
++		if ((dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) &&
++		    (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G))) {
++			PHYDM_DBG(dm, DBG_RA,
++				  "[ON ASSOC] set N-2SS ARFR5 table\n");
++			odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/
++			odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/
++		} else if ((dm->support_ic_type & (ODM_RTL8812)) &&
++			   (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY))) {
++			PHYDM_DBG(dm, DBG_RA,
++				  "[ON ASSOC] set AC-2SS ARFR0 table\n");
++			odm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/
++			odm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/
++		}
++	}
++}
++
++void phydm_ra_dynamic_rate_id_init(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) {
++		odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/
++		odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/
++
++		odm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/
++		odm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/
++	}
++}
++
++void phydm_update_rate_id(
++	void *dm_void,
++	u8 rate,
++	u8 platform_macid)
++{
++#if 0
++
++	struct dm_struct	*dm = (struct dm_struct *)dm_void;
++	struct ra_table		*ra_tab = &dm->dm_ra_table;
++	u8		current_tx_ss;
++	u8		rate_idx = rate & 0x7f; /*remove bit7 SGI*/
++	enum wireless_set wireless_set;
++	u8		phydm_macid;
++	struct cmn_sta_info	*sta;
++
++#if 0
++	if (rate_idx >= ODM_RATEVHTSS2MCS0) {
++		PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT2SS-MCS%d ))\n",
++			  platform_macid, (rate_idx - ODM_RATEVHTSS2MCS0));
++		/*@dummy for SD4 check patch*/
++	} else if (rate_idx >= ODM_RATEVHTSS1MCS0) {
++		PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT1SS-MCS%d ))\n",
++			  platform_macid, (rate_idx - ODM_RATEVHTSS1MCS0));
++		/*@dummy for SD4 check patch*/
++	} else if (rate_idx >= ODM_RATEMCS0) {
++		PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n",
++			  platform_macid, (rate_idx - ODM_RATEMCS0));
++		/*@dummy for SD4 check patch*/
++	} else {
++		PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n",
++			  platform_macid, rate_idx);
++		/*@dummy for SD4 check patch*/
++	}
++#endif
++
++	phydm_macid = dm->phydm_macid_table[platform_macid];
++	sta = dm->phydm_sta_info[phydm_macid];
++
++	if (is_sta_active(sta)) {
++		wireless_set = sta->support_wireless_set;
++
++		if (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) {
++			if (wireless_set & WIRELESS_HT) { /*N mode*/
++				if (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*@2SS mode*/
++
++					sta->ra_info.rate_id  = ARFR_5_RATE_ID;
++					PHYDM_DBG(dm, DBG_RA, "ARFR_5\n");
++				}
++			} else if (wireless_set & WIRELESS_VHT) {/*@AC mode*/
++				if (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*@2SS mode*/
++
++					sta->ra_info.rate_id  = ARFR_0_RATE_ID;
++					PHYDM_DBG(dm, DBG_RA, "ARFR_0\n");
++				}
++			} else
++				sta->ra_info.rate_id  = ARFR_0_RATE_ID;
++
++			PHYDM_DBG(dm, DBG_RA, "UPdate_RateID[%d]: (( 0x%x ))\n",
++				  platform_macid, sta->ra_info.rate_id);
++		}
++	}
++#endif
++}
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_rainfo.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_rainfo.h
+new file mode 100644
+index 000000000..312ae3bf8
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_rainfo.h
+@@ -0,0 +1,306 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDMRAINFO_H__
++#define __PHYDMRAINFO_H__
++
++/* 2019.06.28 Add legacy rate 2 spec rate API*/
++#define RAINFO_VERSION "8.5"
++
++#define	FORCED_UPDATE_RAMASK_PERIOD	5
++
++#define	H2C_MAX_LENGTH		7
++
++#define	RA_FLOOR_UP_GAP		3
++#define	RA_FLOOR_TABLE_SIZE	7
++
++#define	ACTIVE_TP_THRESHOLD	1
++#define	RA_RETRY_DESCEND_NUM	2
++#define	RA_RETRY_LIMIT_LOW	4
++#define	RA_RETRY_LIMIT_HIGH	32
++
++#define PHYDM_IS_LEGACY_RATE(rate) ((rate <= ODM_RATE54M) ? true : false)
++#define PHYDM_IS_CCK_RATE(rate) ((rate <= ODM_RATE11M) ? true : false)
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	#define	FIRST_MACID	1
++#else
++	#define	FIRST_MACID	0
++#endif
++
++/* @1 ============================================================
++ * 1 enumrate
++ * 1 ============================================================
++ */
++
++enum phydm_ra_dbg_para {
++	RADBG_PCR_TH_OFFSET	= 0,
++	RADBG_RTY_PENALTY	= 1,
++	RADBG_N_HIGH		= 2,
++	RADBG_N_LOW		= 3,
++	RADBG_TRATE_UP_TABLE	= 4,
++	RADBG_TRATE_DOWN_TABLE	= 5,
++	RADBG_TRYING_NECESSARY	= 6,
++	RADBG_TDROPING_NECESSARY = 7,
++	RADBG_RATE_UP_RTY_RATIO	= 8,
++	RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */
++
++	RADBG_DEBUG_MONITOR1	= 0xc,
++	RADBG_DEBUG_MONITOR2	= 0xd,
++	RADBG_DEBUG_MONITOR3	= 0xe,
++	RADBG_DEBUG_MONITOR4	= 0xf,
++	RADBG_DEBUG_MONITOR5	= 0x10,
++	NUM_RA_PARA
++};
++
++enum phydm_wireless_mode {
++	PHYDM_WIRELESS_MODE_UNKNOWN	= 0x00,
++	PHYDM_WIRELESS_MODE_A		= 0x01,
++	PHYDM_WIRELESS_MODE_B		= 0x02,
++	PHYDM_WIRELESS_MODE_G		= 0x04,
++	PHYDM_WIRELESS_MODE_AUTO	= 0x08,
++	PHYDM_WIRELESS_MODE_N_24G	= 0x10,
++	PHYDM_WIRELESS_MODE_N_5G	= 0x20,
++	PHYDM_WIRELESS_MODE_AC_5G	= 0x40,
++	PHYDM_WIRELESS_MODE_AC_24G	= 0x80,
++	PHYDM_WIRELESS_MODE_AC_ONLY	= 0x100,
++	PHYDM_WIRELESS_MODE_MAX		= 0x800,
++	PHYDM_WIRELESS_MODE_ALL		= 0xFFFF
++};
++
++enum phydm_rateid_idx {
++	PHYDM_BGN_40M_2SS	= 0,
++	PHYDM_BGN_40M_1SS	= 1,
++	PHYDM_BGN_20M_2SS	= 2,
++	PHYDM_BGN_20M_1SS	= 3,
++	PHYDM_GN_N2SS		= 4,
++	PHYDM_GN_N1SS		= 5,
++	PHYDM_BG		= 6,
++	PHYDM_G			= 7,
++	PHYDM_B_20M		= 8,
++	PHYDM_ARFR0_AC_2SS	= 9,
++	PHYDM_ARFR1_AC_1SS	= 10,
++	PHYDM_ARFR2_AC_2G_1SS	= 11,
++	PHYDM_ARFR3_AC_2G_2SS	= 12,
++	PHYDM_ARFR4_AC_3SS	= 13,
++	PHYDM_ARFR5_N_3SS	= 14,
++	PHYDM_ARFR7_N_4SS	= 15,
++	PHYDM_ARFR6_AC_4SS	= 16
++};
++
++enum phydm_qam_order {
++	PHYDM_QAM_CCK	= 0,
++	PHYDM_QAM_BPSK	= 1,
++	PHYDM_QAM_QPSK	= 2,
++	PHYDM_QAM_16QAM	= 3,
++	PHYDM_QAM_64QAM	= 4,
++	PHYDM_QAM_256QAM = 5
++};
++
++#if (RATE_ADAPTIVE_SUPPORT == 1)/* @88E RA */
++
++struct _phydm_txstatistic_ {
++	u32	hw_total_tx;
++	u32	hw_tx_success;
++	u32	hw_tx_rty;
++	u32	hw_tx_drop;
++};
++
++/* @1 ============================================================
++ * 1  structure
++ * 1 ============================================================
++ */
++struct _odm_ra_info_ {
++	u8	rate_id;
++	u32	rate_mask;
++	u32	ra_use_rate;
++	u8	rate_sgi;
++	u8	rssi_sta_ra;
++	u8	pre_rssi_sta_ra;
++	u8	sgi_enable;
++	u8	decision_rate;
++	u8	pre_rate;
++	u8	highest_rate;
++	u8	lowest_rate;
++	u32	nsc_up;
++	u32	nsc_down;
++	u16	RTY[5];
++	u32	TOTAL;
++	u16	DROP;
++	u8	active;
++	u16	rpt_time;
++	u8	ra_waiting_counter;
++	u8	ra_pending_counter;
++	u8	ra_drop_after_down;
++#if 1 /* POWER_TRAINING_ACTIVE == 1 */ /* For compile  pass only~! */
++	u8	pt_active;	/* on or off */
++	u8	pt_try_state;	/* @0 trying state, 1 for decision state */
++	u8	pt_stage;	/* @0~6 */
++	u8	pt_stop_count;	/* Stop PT counter */
++	u8	pt_pre_rate;	/* @if rate change do PT */
++	u8	pt_pre_rssi;	/* @if RSSI change 5% do PT */
++	u8	pt_mode_ss;	/* @decide whitch rate should do PT */
++	u8	ra_stage;	/* @StageRA, decide how many times RA will be done between PT */
++	u8	pt_smooth_factor;
++#endif
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP) &&	((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
++	u8	rate_down_counter;
++	u8	rate_up_counter;
++	u8	rate_direction;
++	u8	bounding_type;
++	u8	bounding_counter;
++	u8	bounding_learning_time;
++	u8	rate_down_start_time;
++#endif
++};
++#endif
++
++
++struct ra_table {
++	#ifdef MU_EX_MACID
++	u8	mu1_rate[MU_EX_MACID];
++	#endif
++	u8	highest_client_tx_order;
++	u16	highest_client_tx_rate_order;
++	u8	power_tracking_flag;
++	u8	ra_th_ofst; /*RA_threshold_offset*/
++	u8	ra_ofst_direc; /*RA_offset_direction*/
++	u8	up_ramask_cnt; /*@force update_ra_mask counter*/
++	u8	up_ramask_cnt_tmp; /*@Just for debug, should be removed latter*/
++	u32	rrsr_val_init; /*0x440*/
++	u32	rrsr_val_curr; /*0x440*/
++	boolean dynamic_rrsr_en;
++	u8	ra_trigger_mode; /*0: pkt RA, 1: TBTT RA*/
++	u8	ra_tx_cls_th;	 /*255: auto, xx: in dB*/
++#if 0	/*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
++	u8	per_rate_retrylimit_20M[PHY_NUM_RATE_IDX];
++	u8	per_rate_retrylimit_40M[PHY_NUM_RATE_IDX];
++	u8	retry_descend_num;
++	u8	retrylimit_low;
++	u8	retrylimit_high;
++#endif
++	u8	ldpc_thres; /* @if RSSI > ldpc_th => switch from LPDC to BCC */
++	void (*record_ra_info)(void *dm_void, u8 macid,
++			       struct cmn_sta_info *sta, u64 ra_mask);
++};
++
++/* @1 ============================================================
++ * 1  Function Prototype
++ * 1 ============================================================
++ */
++boolean phydm_is_cck_rate(void *dm_void, u8 rate);
++
++boolean phydm_is_ofdm_rate(void *dm_void, u8 rate);
++
++boolean phydm_is_ht_rate(void *dm_void, u8 rate);
++
++boolean phydm_is_vht_rate(void *dm_void, u8 rate);
++
++u8 phydm_legacy_rate_2_spec_rate(void *dm_void, u8 rate);
++
++u8 phydm_rate_2_rate_digit(void *dm_void, u8 rate);
++
++u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type);
++
++u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate);
++
++void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used,
++		     char *output, u32 *_out_len);
++
++void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
++		    u32 *_out_len);
++
++void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
++
++void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component);
++
++void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size);
++
++void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
++
++u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx);
++
++void phydm_rrsr_set_register(void *dm_void, u32 rrsr_val);
++
++void phydm_ra_info_watchdog(void *dm_void);
++
++void phydm_rrsr_en(void *dm_void, boolean en_rrsr);
++
++void phydm_ra_info_init(void *dm_void);
++
++void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc,
++				   u8 ra_th_ofst);
++
++u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode);
++
++u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw);
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++void phydm_update_hal_ra_mask(
++	void *dm_void,
++	u32 wireless_mode,
++	u8 rf_type,
++	u8 BW,
++	u8 mimo_ps_enable,
++	u8 disable_cck_rate,
++	u32 *ratr_bitmap_msb_in,
++	u32 *ratr_bitmap_in,
++	u8 tx_rate_level);
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++u8 phydm_get_plcp(void *dm_void, u16 macid);
++#endif
++
++void phydm_refresh_rate_adaptive_mask(void *dm_void);
++
++u8 phydm_get_rx_stream_num(void *dm_void, enum rf_type type);
++
++u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state);
++
++void odm_ra_post_action_on_assoc(void *dm);
++
++u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect);
++
++void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used,
++			 char *output, u32 *_out_len);
++
++u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx);
++
++void phydm_ra_registed(void *dm_void, u8 macid, u8 rssi_from_assoc);
++
++void phydm_ra_offline(void *dm_void, u8 macid);
++
++void phydm_ra_mask_watchdog(void *dm_void);
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void odm_refresh_basic_rate_mask(
++	void *dm_void);
++#endif
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++void phydm_ra_mode_selection(void *dm_void, u8 mode);
++#endif
++
++#endif /*@#ifndef __PHYDMRAINFO_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_reg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_reg.h
+new file mode 100644
+index 000000000..0835f34bd
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_reg.h
+@@ -0,0 +1,243 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++/*************************************************************
++ * File Name: odm_reg.h
++ *
++ * Description:
++ *
++ * This file is for general register definition.
++ *
++ *
++ ************************************************************/
++#ifndef __HAL_ODM_REG_H__
++#define __HAL_ODM_REG_H__
++
++/*@
++ * Register Definition
++ *
++ */
++
++/* @MAC REG */
++#define	ODM_BB_RESET				0x002
++#define	ODM_DUMMY				0x4fe
++#define	RF_T_METER_OLD				0x24
++#define	RF_T_METER_NEW				0x42
++
++#define	ODM_EDCA_VO_PARAM			0x500
++#define	ODM_EDCA_VI_PARAM			0x504
++#define	ODM_EDCA_BE_PARAM			0x508
++#define	ODM_EDCA_BK_PARAM			0x50C
++#define	ODM_TXPAUSE				0x522
++
++/* @LTE_COEX */
++#define REG_LTECOEX_CTRL			0x07C0
++#define REG_LTECOEX_WRITE_DATA			0x07C4
++#define REG_LTECOEX_READ_DATA			0x07C8
++#define REG_LTECOEX_PATH_CONTROL		0x70
++
++/* @BB REG */
++#define	ODM_FPGA_PHY0_PAGE8			0x800
++#define	ODM_PSD_SETTING				0x808
++#define	ODM_AFE_SETTING				0x818
++#define	ODM_TXAGC_B_6_18			0x830
++#define	ODM_TXAGC_B_24_54			0x834
++#define	ODM_TXAGC_B_MCS32_5			0x838
++#define	ODM_TXAGC_B_MCS0_MCS3			0x83c
++#define	ODM_TXAGC_B_MCS4_MCS7			0x848
++#define	ODM_TXAGC_B_MCS8_MCS11			0x84c
++#define	ODM_ANALOG_REGISTER			0x85c
++#define	ODM_RF_INTERFACE_OUTPUT			0x860
++#define	ODM_TXAGC_B_MCS12_MCS15			0x868
++#define	ODM_TXAGC_B_11_A_2_11			0x86c
++#define	ODM_AD_DA_LSB_MASK			0x874
++#define	ODM_ENABLE_3_WIRE			0x88c
++#define	ODM_PSD_REPORT				0x8b4
++#define	ODM_R_ANT_SELECT			0x90c
++#define	ODM_CCK_ANT_SELECT			0xa07
++#define	ODM_CCK_PD_THRESH			0xa0a
++#define	ODM_CCK_RF_REG1				0xa11
++#define	ODM_CCK_MATCH_FILTER			0xa20
++#define	ODM_CCK_RAKE_MAC			0xa2e
++#define	ODM_CCK_CNT_RESET			0xa2d
++#define	ODM_CCK_TX_DIVERSITY			0xa2f
++#define	ODM_CCK_FA_CNT_MSB			0xa5b
++#define	ODM_CCK_FA_CNT_LSB			0xa5c
++#define	ODM_CCK_NEW_FUNCTION			0xa75
++#define	ODM_OFDM_PHY0_PAGE_C			0xc00
++#define	ODM_OFDM_RX_ANT				0xc04
++#define	ODM_R_A_RXIQI				0xc14
++#define	ODM_R_A_AGC_CORE1			0xc50
++#define	ODM_R_A_AGC_CORE2			0xc54
++#define	ODM_R_B_AGC_CORE1			0xc58
++#define	ODM_R_AGC_PAR				0xc70
++#define	ODM_R_HTSTF_AGC_PAR			0xc7c
++#define	ODM_TX_PWR_TRAINING_A			0xc90
++#define	ODM_TX_PWR_TRAINING_B			0xc98
++#define	ODM_OFDM_FA_CNT1			0xcf0
++#define	ODM_OFDM_PHY0_PAGE_D			0xd00
++#define	ODM_OFDM_FA_CNT2			0xda0
++#define	ODM_OFDM_FA_CNT3			0xda4
++#define	ODM_OFDM_FA_CNT4			0xda8
++#define	ODM_TXAGC_A_6_18			0xe00
++#define	ODM_TXAGC_A_24_54			0xe04
++#define	ODM_TXAGC_A_1_MCS32			0xe08
++#define	ODM_TXAGC_A_MCS0_MCS3			0xe10
++#define	ODM_TXAGC_A_MCS4_MCS7			0xe14
++#define	ODM_TXAGC_A_MCS8_MCS11			0xe18
++#define	ODM_TXAGC_A_MCS12_MCS15			0xe1c
++
++/* RF REG */
++#define	ODM_GAIN_SETTING			0x00
++#define	ODM_CHANNEL				0x18
++#define	ODM_RF_T_METER				0x24
++#define	ODM_RF_T_METER_92D			0x42
++#define	ODM_RF_T_METER_88E			0x42
++#define	ODM_RF_T_METER_92E			0x42
++#define	ODM_RF_T_METER_8812			0x42
++#define	REG_RF_TX_GAIN_OFFSET			0x55
++
++/* @ant Detect Reg */
++#define	ODM_DPDT				0x300
++
++/* PSD Init */
++#define	ODM_PSDREG				0x808
++
++/* @92D path Div */
++#define	PATHDIV_REG				0xB30
++#define	PATHDIV_TRI				0xBA0
++
++
++/*@
++ * Bitmap Definition
++ */
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++	/* TX AGC */
++	#define		REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR		0xc20
++	#define		REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR		0xc24
++	#define		REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR		0xc28
++	#define		REG_TX_AGC_A_MCS3_MCS0_JAGUAR			0xc2c
++	#define		REG_TX_AGC_A_MCS7_MCS4_JAGUAR			0xc30
++	#define		REG_TX_AGC_A_MCS11_MCS8_JAGUAR			0xc34
++	#define		REG_TX_AGC_A_MCS15_MCS12_JAGUAR			0xc38
++	#define		REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	0xc3c
++	#define		REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	0xc40
++	#define		REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	0xc44
++	#define		REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	0xc48
++	#define		REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	0xc4c
++	#if defined(CONFIG_WLAN_HAL_8814AE)
++		#define		REG_TX_AGC_A_MCS19_MCS16_JAGUAR		0xcd8
++		#define		REG_TX_AGC_A_MCS23_MCS20_JAGUAR		0xcdc
++		#define		REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	0xce0
++		#define		REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	0xce4
++		#define		REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	0xce8
++	#endif
++	#define		REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR		0xe20
++	#define		REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR		0xe24
++	#define		REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR		0xe28
++	#define		REG_TX_AGC_B_MCS3_MCS0_JAGUAR			0xe2c
++	#define		REG_TX_AGC_B_MCS7_MCS4_JAGUAR			0xe30
++	#define		REG_TX_AGC_B_MCS11_MCS8_JAGUAR			0xe34
++	#define		REG_TX_AGC_B_MCS15_MCS12_JAGUAR			0xe38
++	#define		REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	0xe3c
++	#define		REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	0xe40
++	#define		REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	0xe44
++	#define		REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	0xe48
++	#define		REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	0xe4c
++	#if defined(CONFIG_WLAN_HAL_8814AE)
++		#define		REG_TX_AGC_B_MCS19_MCS16_JAGUAR		0xed8
++		#define		REG_TX_AGC_B_MCS23_MCS20_JAGUAR		0xedc
++		#define		REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	0xee0
++		#define		REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	0xee4
++		#define		REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	0xee8
++		#define		REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR	0x1820
++		#define		REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR	0x1824
++		#define		REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR	0x1828
++		#define		REG_TX_AGC_C_MCS3_MCS0_JAGUAR		0x182c
++		#define		REG_TX_AGC_C_MCS7_MCS4_JAGUAR		0x1830
++		#define		REG_TX_AGC_C_MCS11_MCS8_JAGUAR		0x1834
++		#define		REG_TX_AGC_C_MCS15_MCS12_JAGUAR		0x1838
++		#define		REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	0x183c
++		#define		REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	0x1840
++		#define		REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	0x1844
++		#define		REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	0x1848
++		#define		REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	0x184c
++		#define		REG_TX_AGC_C_MCS19_MCS16_JAGUAR		0x18d8
++		#define		REG_TX_AGC_C_MCS23_MCS20_JAGUAR		0x18dc
++		#define		REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	0x18e0
++		#define		REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	0x18e4
++		#define		REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	0x18e8
++		#define		REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR	0x1a20
++		#define		REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR	0x1a24
++		#define		REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR	0x1a28
++		#define		REG_TX_AGC_D_MCS3_MCS0_JAGUAR		0x1a2c
++		#define		REG_TX_AGC_D_MCS7_MCS4_JAGUAR		0x1a30
++		#define		REG_TX_AGC_D_MCS11_MCS8_JAGUAR		0x1a34
++		#define		REG_TX_AGC_D_MCS15_MCS12_JAGUAR		0x1a38
++		#define		REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	0x1a3c
++		#define		REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	0x1a40
++		#define		REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	0x1a44
++		#define		REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	0x1a48
++		#define		REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	0x1a4c
++		#define		REG_TX_AGC_D_MCS19_MCS16_JAGUAR		0x1ad8
++		#define		REG_TX_AGC_D_MCS23_MCS20_JAGUAR		0x1adc
++		#define		REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	0x1ae0
++		#define		REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	0x1ae4
++		#define		REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	0x1ae8
++	#endif
++
++	#define		is_tx_agc_byte0_jaguar	0xff
++	#define		is_tx_agc_byte1_jaguar	0xff00
++	#define		is_tx_agc_byte2_jaguar	0xff0000
++	#define		is_tx_agc_byte3_jaguar	0xff000000
++#if defined(CONFIG_WLAN_HAL_8198F) || defined(CONFIG_WLAN_HAL_8822CE) ||\
++defined(CONFIG_WLAN_HAL_8814BE) || defined(CONFIG_WLAN_HAL_8812FE) ||\
++defined(CONFIG_WLAN_HAL_8197G)
++		#define REG_TX_AGC_CCK_11_CCK_1_JAGUAR3		0x3a00
++		#define REG_TX_AGC_OFDM_18_CCK_6_JAGUAR3	0x3a04
++		#define	REG_TX_AGC_OFDM_54_CCK_24_JAGUAR3	0x3a08
++		#define	REG_TX_AGC_MCS3_0_JAGUAR3		0x3a0c
++		#define	REG_TX_AGC_MCS7_4_JAGUAR3		0x3a10
++		#define	REG_TX_AGC_MCS11_8_JAGUAR3		0x3a14
++		#define	REG_TX_AGC_MCS15_12_JAGUAR3		0x3a18
++		#define	REG_TX_AGC_MCS19_16_JAGUAR3		0x3a1c
++		#define	REG_TX_AGC_MCS23_20_JAGUAR3		0x3a20
++		#define	REG_TX_AGC_MCS27_24_JAGUAR3		0x3a24
++		#define	REG_TX_AGC_MCS31_28_JAGUAR3		0x3a28
++		#define	REG_TX_AGC_VHT_Nss1_MCS3_0_JAGUAR3	0x3a2c
++		#define	REG_TX_AGC_VHT_Nss1_MCS7_4_JAGUAR3	0x3a30
++		#define	REG_TX_AGC_VHT_NSS2_MCS1_NSS1_MCS8_JAGUAR3	0x3a34
++		#define	REG_TX_AGC_VHT_Nss2_MCS5_2_JAGUAR3	0x3a38
++		#define	REG_TX_AGC_VHT_Nss2_MCS9_6_JAGUAR3	0x3a3c
++		#define	REG_TX_AGC_VHT_Nss3_MCS3_0_JAGUAR3	0x3a40
++		#define	REG_TX_AGC_VHT_Nss3_MCS7_4_JAGUAR3	0x3a44
++		#define	REG_TX_AGC_VHT_Nss4_MCS1_Nss3_MCS8_JAGUAR3	0x3a48
++		#define	REG_TX_AGC_VHT_Nss4_MCS5_2_JAGUAR3	0x3a4c
++		#define	REG_TX_AGC_VHT_Nss4_MCS9_6_JAGUAR3	0x3a50
++#endif
++#endif
++
++#define	BIT_FA_RESET					BIT(0)
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_regdefine11ac.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_regdefine11ac.h
+new file mode 100644
+index 000000000..7824ac22c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_regdefine11ac.h
+@@ -0,0 +1,109 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __ODM_REGDEFINE11AC_H__
++#define __ODM_REGDEFINE11AC_H__
++
++/* @2 RF REG LIST */
++
++
++
++/* @2 BB REG LIST */
++/* PAGE 8 */
++#define	ODM_REG_CCK_RPT_FORMAT_11AC		0x804
++#define	ODM_REG_BB_RX_PATH_11AC			0x808
++#define	ODM_REG_BB_TX_PATH_11AC			0x80c
++#define	ODM_REG_BB_ATC_11AC			0x860
++#define	ODM_REG_EDCCA_POWER_CAL			0x8dc
++#define	ODM_REG_DBG_RPT_11AC			0x8fc
++/* PAGE 9 */
++#define	ODM_REG_EDCCA_DOWN_OPT			0x900
++#define	ODM_REG_ACBB_EDCCA_ENHANCE		0x944
++#define	odm_adc_trigger_jaguar2			0x95C	/*@ADC sample mode*/
++#define	ODM_REG_OFDM_FA_RST_11AC		0x9A4
++#define	ODM_REG_CCX_PERIOD_11AC			0x990
++#define	ODM_REG_NHM_TH9_TH10_11AC		0x994
++#define	ODM_REG_CLM_11AC			0x994
++#define	ODM_REG_NHM_TH3_TO_TH0_11AC		0x998
++#define	ODM_REG_NHM_TH7_TO_TH4_11AC		0x99c
++#define	ODM_REG_NHM_TH8_11AC			0x9a0
++#define	ODM_REG_NHM_9E8_11AC			0x9e8
++#define	ODM_REG_CSI_CONTENT_VALUE		0x9b4
++/* PAGE A */
++#define	ODM_REG_CCK_CCA_11AC			0xA0A
++#define	ODM_REG_CCK_FA_RST_11AC			0xA2C
++#define	ODM_REG_CCK_FA_11AC			0xA5C
++/* PAGE B */
++#define	ODM_REG_RST_RPT_11AC			0xB58
++/* PAGE C */
++#define	ODM_REG_TRMUX_11AC			0xC08
++#define	ODM_REG_IGI_A_11AC			0xC50
++/* PAGE E */
++#define	ODM_REG_IGI_B_11AC			0xE50
++#define	ODM_REG_ANT_11AC_B			0xE08
++/* PAGE F */
++#define	ODM_REG_CCK_CRC32_CNT_11AC		0xF04
++#define	ODM_REG_CCK_CCA_CNT_11AC		0xF08
++#define	ODM_REG_VHT_CRC32_CNT_11AC		0xF0c
++#define	ODM_REG_HT_CRC32_CNT_11AC		0xF10
++#define	ODM_REG_OFDM_CRC32_CNT_11AC		0xF14
++#define	ODM_REG_OFDM_FA_11AC			0xF48
++#define	ODM_REG_OFDM_FA_TYPE1_11AC		0xFCC
++#define	ODM_REG_OFDM_FA_TYPE2_11AC		0xFD0
++#define	ODM_REG_OFDM_FA_TYPE3_11AC		0xFBC
++#define	ODM_REG_OFDM_FA_TYPE4_11AC		0xFC0
++#define	ODM_REG_OFDM_FA_TYPE5_11AC		0xFC4
++#define	ODM_REG_OFDM_FA_TYPE6_11AC		0xFC8
++#define	ODM_REG_RPT_11AC			0xfa0
++#define	ODM_REG_CLM_RESULT_11AC			0xfa4
++#define	ODM_REG_NHM_CNT_11AC			0xfa8
++#define ODM_REG_NHM_DUR_READY_11AC		0xfb4
++
++#define	ODM_REG_NHM_CNT7_TO_CNT4_11AC		0xfac
++#define	ODM_REG_NHM_CNT11_TO_CNT8_11AC		0xfb0
++/* PAGE 18 */
++#define	ODM_REG_IGI_C_11AC			0x1850
++/* PAGE 1A */
++#define	ODM_REG_IGI_D_11AC			0x1A50
++
++/* PAGE 1D */
++#define	ODM_REG_IGI_11AC3			0x1D70
++
++/* @2 MAC REG LIST */
++#define	ODM_REG_RESP_TX_11AC			0x6D8
++
++
++
++/* @DIG Related */
++#define	ODM_BIT_IGI_11AC			0x0000007F
++#define	ODM_BIT_IGI_B_11AC3			0x00007F00
++#define	ODM_BIT_IGI_C_11AC3			0x007F0000
++#define	ODM_BIT_IGI_D_11AC3			0x7F000000
++#define	ODM_BIT_CCK_RPT_FORMAT_11AC		BIT(16)
++#define	ODM_BIT_BB_RX_PATH_11AC			0xF
++#define	ODM_BIT_BB_TX_PATH_11AC			0xF
++#define	ODM_BIT_BB_ATC_11AC			BIT(14)
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_regdefine11n.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_regdefine11n.h
+new file mode 100644
+index 000000000..aa162327a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_regdefine11n.h
+@@ -0,0 +1,220 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __ODM_REGDEFINE11N_H__
++#define __ODM_REGDEFINE11N_H__
++
++/* @2 RF REG LIST */
++#define	ODM_REG_RF_MODE_11N			0x00
++#define	ODM_REG_RF_0B_11N			0x0B
++#define	ODM_REG_CHNBW_11N			0x18
++#define	ODM_REG_T_METER_11N			0x24
++#define	ODM_REG_RF_25_11N			0x25
++#define	ODM_REG_RF_26_11N			0x26
++#define	ODM_REG_RF_27_11N			0x27
++#define	ODM_REG_RF_2B_11N			0x2B
++#define	ODM_REG_RF_2C_11N			0x2C
++#define	ODM_REG_RXRF_A3_11N			0x3C
++#define	ODM_REG_T_METER_92D_11N			0x42
++#define	ODM_REG_T_METER_88E_11N			0x42
++#define	ODM_REF_RF_DF_11N			0xDF
++
++
++
++/* @2 BB REG LIST
++ * PAGE 8
++ */
++#define	ODM_REG_BB_CTRL_11N			0x800
++#define	ODM_REG_RF_PIN_11N			0x804
++#define	ODM_REG_PSD_CTRL_11N			0x808
++#define	ODM_REG_TX_ANT_CTRL_11N			0x80C
++#define	ODM_REG_BB_PWR_SAV5_11N			0x818
++#define	ODM_REG_CCK_RPT_FORMAT_11N		0x824
++#define	ODM_REG_CCK_RPT_FORMAT_11N_B		0x82C
++#define	ODM_REG_RX_DEFAULT_A_11N		0x858
++#define	ODM_REG_RX_DEFAULT_B_11N		0x85A
++#define	ODM_REG_BB_PWR_SAV3_11N			0x85C
++#define	ODM_REG_ANTSEL_CTRL_11N			0x860
++#define	ODM_REG_RX_ANT_CTRL_11N			0x864
++#define	ODM_REG_PIN_CTRL_11N			0x870
++#define	ODM_REG_BB_PWR_SAV1_11N			0x874
++#define	ODM_REG_ANTSEL_PATH_11N			0x878
++#define	ODM_REG_BB_3WIRE_11N			0x88C
++#define	ODM_REG_SC_CNT_11N			0x8C4
++#define	ODM_REG_PSD_DATA_11N			0x8B4
++#define	ODM_REG_CCX_PERIOD_11N			0x894
++#define	ODM_REG_NHM_TH9_TH10_11N		0x890
++#define	ODM_REG_CLM_11N				0x890
++#define	ODM_REG_NHM_TH3_TO_TH0_11N		0x898
++#define	ODM_REG_NHM_TH7_TO_TH4_11N		0x89c
++#define ODM_REG_NHM_TH8_11N			0xe28
++#define	ODM_REG_CLM_READY_11N			0x8b4
++#define	ODM_REG_CLM_RESULT_11N			0x8d0
++#define	ODM_REG_NHM_CNT_11N			0x8d8
++
++/* @For struct acs_info, Jeffery, 2014-12-26 */
++#define	ODM_REG_NHM_CNT7_TO_CNT4_11N		0x8dc
++#define	ODM_REG_NHM_CNT9_TO_CNT8_11N		0x8d0
++#define	ODM_REG_NHM_CNT10_TO_CNT11_11N		0x8d4
++
++/* PAGE 9 */
++#define	ODM_REG_BB_CTRL_PAGE9_11N		0x900
++#define	ODM_REG_DBG_RPT_11N			0x908
++#define	ODM_REG_BB_TX_PATH_11N			0x90c
++#define	ODM_REG_ANT_MAPPING1_11N		0x914
++#define	ODM_REG_ANT_MAPPING2_11N		0x918
++#define	ODM_REG_EDCCA_DOWN_OPT_11N		0x948
++#define	ODM_REG_RX_DFIR_MOD_97F			0x948
++#define	ODM_REG_SOML_97F			0x998
++
++/* PAGE A */
++#define	ODM_REG_CCK_ANTDIV_PARA1_11N		0xA00
++#define	ODM_REG_CCK_ANT_SEL_11N			0xA04
++#define	ODM_REG_CCK_CCA_11N			0xA0A
++#define	ODM_REG_CCK_ANTDIV_PARA2_11N		0xA0C
++#define	ODM_REG_CCK_ANTDIV_PARA3_11N		0xA10
++#define	ODM_REG_CCK_ANTDIV_PARA4_11N		0xA14
++#define	ODM_REG_CCK_FILTER_PARA1_11N		0xA22
++#define	ODM_REG_CCK_FILTER_PARA2_11N		0xA23
++#define	ODM_REG_CCK_FILTER_PARA3_11N		0xA24
++#define	ODM_REG_CCK_FILTER_PARA4_11N		0xA25
++#define	ODM_REG_CCK_FILTER_PARA5_11N		0xA26
++#define	ODM_REG_CCK_FILTER_PARA6_11N		0xA27
++#define	ODM_REG_CCK_FILTER_PARA7_11N		0xA28
++#define	ODM_REG_CCK_FILTER_PARA8_11N		0xA29
++#define	ODM_REG_CCK_FA_RST_11N			0xA2C
++#define	ODM_REG_CCK_FA_MSB_11N			0xA58
++#define	ODM_REG_CCK_FA_LSB_11N			0xA5C
++#define	ODM_REG_CCK_CCA_CNT_11N			0xA60
++#define	ODM_REG_BB_PWR_SAV4_11N			0xA74
++/* PAGE B */
++#define	ODM_REG_LNA_SWITCH_11N			0xB2C
++#define	ODM_REG_PATH_SWITCH_11N			0xB30
++#define	ODM_REG_RSSI_CTRL_11N			0xB38
++#define	ODM_REG_CONFIG_ANTA_11N			0xB68
++#define	ODM_REG_RSSI_BT_11N			0xB9C
++#define	ODM_REG_RXCK_RFMOD			0xBB0
++#define	ODM_REG_EDCCA_DCNF_97F			0xBC0
++
++/* PAGE C */
++#define	ODM_REG_OFDM_FA_HOLDC_11N		0xC00
++#define	ODM_REG_BB_RX_PATH_11N			0xC04
++#define	ODM_REG_TRMUX_11N			0xC08
++#define	ODM_REG_OFDM_FA_RSTC_11N		0xC0C
++#define	ODM_REG_DOWNSAM_FACTOR_11N		0xC10
++#define	ODM_REG_RXIQI_MATRIX_11N		0xC14
++#define	ODM_REG_TXIQK_MATRIX_LSB1_11N		0xC4C
++#define	ODM_REG_IGI_A_11N			0xC50
++#define	ODM_REG_ANTDIV_PARA2_11N		0xC54
++#define	ODM_REG_IGI_B_11N			0xC58
++#define	ODM_REG_ANTDIV_PARA3_11N		0xC5C
++#define   ODM_REG_L1SBD_PD_CH_11N		0XC6C
++#define	ODM_REG_BB_PWR_SAV2_11N			0xC70
++#define	ODM_REG_BB_AGC_SET_2_11N		0xc74
++#define	ODM_REG_RX_OFF_11N			0xC7C
++#define	ODM_REG_TXIQK_MATRIXA_11N		0xC80
++#define	ODM_REG_TXIQK_MATRIXB_11N		0xC88
++#define	ODM_REG_TXIQK_MATRIXA_LSB2_11N		0xC94
++#define	ODM_REG_TXIQK_MATRIXB_LSB2_11N		0xC9C
++#define	ODM_REG_RXIQK_MATRIX_LSB_11N		0xCA0
++#define	ODM_REG_ANTDIV_PARA1_11N		0xCA4
++#define	ODM_REG_SMALL_BANDWIDTH_11N		0xCE4
++#define	ODM_REG_OFDM_FA_TYPE1_11N		0xCF0
++/* PAGE D */
++#define	ODM_REG_OFDM_FA_RSTD_11N		0xD00
++#define	ODM_REG_BB_RX_ANT_11N			0xD04
++#define	ODM_REG_BB_ATC_11N			0xD2C
++#define	ODM_REG_OFDM_FA_TYPE2_11N		0xDA0
++#define	ODM_REG_OFDM_FA_TYPE3_11N		0xDA4
++#define	ODM_REG_OFDM_FA_TYPE4_11N		0xDA8
++#define	ODM_REG_RPT_11N				0xDF4
++/* PAGE E */
++#define	ODM_REG_TXAGC_A_6_18_11N		0xE00
++#define	ODM_REG_TXAGC_A_24_54_11N		0xE04
++#define	ODM_REG_TXAGC_A_1_MCS32_11N		0xE08
++#define	ODM_REG_TXAGC_A_MCS0_3_11N		0xE10
++#define	ODM_REG_TXAGC_A_MCS4_7_11N		0xE14
++#define	ODM_REG_TXAGC_A_MCS8_11_11N		0xE18
++#define	ODM_REG_TXAGC_A_MCS12_15_11N		0xE1C
++#define	ODM_REG_EDCCA_DCNF_11N			0xE24
++#define	ODM_REG_TAP_UPD_97F			0xE24
++#define	ODM_REG_FPGA0_IQK_11N			0xE28
++#define	ODM_REG_PAGE_B1_97F			0xE28
++#define	ODM_REG_TXIQK_TONE_A_11N		0xE30
++#define	ODM_REG_RXIQK_TONE_A_11N		0xE34
++#define	ODM_REG_TXIQK_PI_A_11N			0xE38
++#define	ODM_REG_RXIQK_PI_A_11N			0xE3C
++#define	ODM_REG_TXIQK_11N			0xE40
++#define	ODM_REG_RXIQK_11N			0xE44
++#define	ODM_REG_IQK_AGC_PTS_11N			0xE48
++#define	ODM_REG_IQK_AGC_RSP_11N			0xE4C
++#define	ODM_REG_BLUETOOTH_11N			0xE6C
++#define	ODM_REG_RX_WAIT_CCA_11N			0xE70
++#define	ODM_REG_TX_CCK_RFON_11N			0xE74
++#define	ODM_REG_TX_CCK_BBON_11N			0xE78
++#define	ODM_REG_OFDM_RFON_11N			0xE7C
++#define	ODM_REG_OFDM_BBON_11N			0xE80
++#define	ODM_REG_TX2RX_11N			0xE84
++#define	ODM_REG_TX2TX_11N			0xE88
++#define	ODM_REG_RX_CCK_11N			0xE8C
++#define	ODM_REG_RX_OFDM_11N			0xED0
++#define	ODM_REG_RX_WAIT_RIFS_11N		0xED4
++#define	ODM_REG_RX2RX_11N			0xED8
++#define	ODM_REG_STANDBY_11N			0xEDC
++#define	ODM_REG_SLEEP_11N			0xEE0
++#define	ODM_REG_PMPD_ANAEN_11N			0xEEC
++/* PAGE F */
++#define	ODM_REG_PAGE_F_RST_11N			0xF14
++#define	ODM_REG_IGI_C_11N			0xF84
++#define	ODM_REG_IGI_D_11N			0xF88
++#define	ODM_REG_CCK_CRC32_ERROR_CNT_11N		0xF84
++#define	ODM_REG_CCK_CRC32_OK_CNT_11N		0xF88
++#define	ODM_REG_HT_CRC32_CNT_11N		0xF90
++#define	ODM_REG_OFDM_CRC32_CNT_11N		0xF94
++#define	ODM_REG_HT_CRC32_CNT_11N_AGG		0xFB8
++
++/* @2 MAC REG LIST */
++#define	ODM_REG_BB_RST_11N			0x02
++#define	ODM_REG_ANTSEL_PIN_11N			0x4C
++#define	ODM_REG_EARLY_MODE_11N			0x4D0
++#define	ODM_REG_RSSI_MONITOR_11N		0x4FE
++#define	ODM_REG_EDCA_VO_11N			0x500
++#define	ODM_REG_EDCA_VI_11N			0x504
++#define	ODM_REG_EDCA_BE_11N			0x508
++#define	ODM_REG_EDCA_BK_11N			0x50C
++#define	ODM_REG_TXPAUSE_11N			0x522
++#define	ODM_REG_RESP_TX_11N			0x6D8
++#define	ODM_REG_ANT_TRAIN_PARA1_11N		0x7b0
++#define	ODM_REG_ANT_TRAIN_PARA2_11N		0x7b4
++
++
++/* @DIG Related */
++#define	ODM_BIT_IGI_11N				0x0000007F
++#define	ODM_BIT_CCK_RPT_FORMAT_11N		BIT(9)
++#define	ODM_BIT_BB_RX_PATH_11N			0xF
++#define	ODM_BIT_BB_TX_PATH_11N			0xF
++#define	ODM_BIT_BB_ATC_11N			BIT(11)
++#endif
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_regtable.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_regtable.h
+new file mode 100644
+index 000000000..a342db45a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_regtable.h
+@@ -0,0 +1,969 @@
++#define R_0x0 0x0
++#define R_0x00 0x00
++#define R_0x0106 0x0106
++#define R_0x0140 0x0140
++#define R_0x0144 0x0144
++#define R_0x0148 0x0148
++#define R_0x040 0x040
++#define R_0x10 0x10
++#define R_0x100 0x100
++#define R_0x1038 0x1038
++#define R_0x103c 0x103c
++#define R_0x1040 0x1040
++#define R_0x1048 0x1048
++#define R_0x1080 0x1080
++#define R_0x14 0x14
++#define R_0x14c0 0x14c0
++#define R_0x14c4 0x14c4
++#define R_0x14c8 0x14c8
++#define R_0x14cc 0x14cc
++#define R_0x1518 0x1518
++#define R_0x1684 0x1684
++#define R_0x1688 0x1688
++#define R_0x168c 0x168c
++#define R_0x1700 0x1700
++#define R_0x1704 0x1704
++#define R_0x1800 0x1800
++#define R_0x1804 0x1804
++#define R_0x1808 0x1808
++#define R_0x180c 0x180c
++#define R_0x1810 0x1810
++#define R_0x1814 0x1814
++#define R_0x1818 0x1818
++#define R_0x181c 0x181c
++#define R_0x1830 0x1830
++#define R_0x1834 0x1834
++#define R_0x1838 0x1838
++#define R_0x183c 0x183c
++#define R_0x1840 0x1840
++#define R_0x1844 0x1844
++#define R_0x1848 0x1848
++#define R_0x1860 0x1860
++#define R_0x1864 0x1864
++#define R_0x1868 0x1868
++#define R_0x186c 0x186c
++#define R_0x1870 0x1870
++#define R_0x1880 0x1880
++#define R_0x1884 0x1884
++#define R_0x188c 0x188c
++#define R_0x1894 0x1894
++#define R_0x189c 0x189c
++#define R_0x18a0 0x18a0
++#define R_0x18a4 0x18a4
++#define R_0x18a8 0x18a8
++#define R_0x18ac 0x18ac
++#define R_0x18e0 0x18e0
++#define R_0x18e8 0x18e8
++#define R_0x18ec 0x18ec
++#define R_0x18f0 0x18f0
++#define R_0x18f8 0x18f8
++#define R_0x18fc 0x18fc
++#define R_0x1900 0x1900
++#define R_0x1904 0x1904
++#define R_0x1908 0x1908
++#define R_0x1910 0x1910
++#define R_0x1918 0x1918
++#define R_0x191c 0x191c
++#define R_0x1928 0x1928
++#define R_0x1938 0x1938
++#define R_0x1940 0x1940
++#define R_0x1944 0x1944
++#define R_0x1950 0x1950
++#define R_0x1954 0x1954
++#define R_0x195c 0x195c
++#define R_0x1970 0x1970
++#define R_0x1984 0x1984
++#define R_0x1988 0x1988
++#define R_0x198c 0x198c
++#define R_0x1990 0x1990
++#define R_0x1991 0x1991
++#define R_0x1998 0x1998
++#define R_0x19a8 0x19a8
++#define R_0x19b8 0x19b8
++#define R_0x19d4 0x19d4
++#define R_0x19d8 0x19d8
++#define R_0x19e0 0x19e0
++#define R_0x19f0 0x19f0
++#define R_0x19f8 0x19f8
++#define R_0x1a00 0x1a00
++#define R_0x1a04 0x1a04
++#define R_0x1a08 0x1a08
++#define R_0x1a10 0x1a10
++#define R_0x1a14 0x1a14
++#define R_0x1a20 0x1a20
++#define R_0x1a24 0x1a24
++#define R_0x1a28 0x1a28
++#define R_0x1a2c 0x1a2c
++#define R_0x1a5c 0x1a5c
++#define R_0x1a70 0x1a70
++#define R_0x1a74 0x1a74
++#define R_0x1a80 0x1a80
++#define R_0x1a84 0x1a84
++#define R_0x1a8c 0x1a8c
++#define R_0x1a94 0x1a94
++#define R_0x1a98 0x1a98
++#define R_0x1a9c 0x1a9c
++#define R_0x1aa0 0x1aa0
++#define R_0x1aa8 0x1aa8
++#define R_0x1aac 0x1aac
++#define R_0x1ab0 0x1ab0
++#define R_0x1abc 0x1abc
++#define R_0x1ac0 0x1ac0
++#define R_0x1ac8 0x1ac8
++#define R_0x1acc 0x1acc
++#define R_0x1ad0 0x1ad0
++#define R_0x1ad4 0x1ad4
++#define R_0x1ae0 0x1ae0
++#define R_0x1ae8 0x1ae8
++#define R_0x1aec 0x1aec
++#define R_0x1b00 0x1b00
++#define R_0x1b04 0x1b04
++#define R_0x1b08 0x1b08
++#define R_0x1b0c 0x1b0c
++#define R_0x1b10 0x1b10
++#define R_0x1b14 0x1b14
++#define R_0x1b18 0x1b18
++#define R_0x1b1c 0x1b1c
++#define R_0x1b20 0x1b20
++#define R_0x1b23 0x1b23
++#define R_0x1b24 0x1b24
++#define R_0x1b28 0x1b28
++#define R_0x1b2c 0x1b2c
++#define R_0x1b30 0x1b30
++#define R_0x1b34 0x1b34
++#define R_0x1b38 0x1b38
++#define R_0x1b3c 0x1b3c
++#define R_0x1b40 0x1b40
++#define R_0x1b44 0x1b44
++#define R_0x1b48 0x1b48
++#define R_0x1b4c 0x1b4c
++#define R_0x1b50 0x1b50
++#define R_0x1b54 0x1b54
++#define R_0x1b58 0x1b58
++#define R_0x1b5c 0x1b5c
++#define R_0x1b60 0x1b60
++#define R_0x1b64 0x1b64
++#define R_0x1b67 0x1b67
++#define R_0x1b68 0x1b68
++#define R_0x1b6c 0x1b6c
++#define R_0x1b70 0x1b70
++#define R_0x1b74 0x1b74
++#define R_0x1b78 0x1b78
++#define R_0x1b7c 0x1b7c
++#define R_0x1b80 0x1b80
++#define R_0x1b83 0x1b83
++#define R_0x1b84 0x1b84
++#define R_0x1b88 0x1b88
++#define R_0x1b8c 0x1b8c
++#define R_0x1b90 0x1b90
++#define R_0x1b92 0x1b92
++#define R_0x1b94 0x1b94
++#define R_0x1b97 0x1b97
++#define R_0x1b98 0x1b98
++#define R_0x1b9c 0x1b9c
++#define R_0x1ba0 0x1ba0
++#define R_0x1ba4 0x1ba4
++#define R_0x1ba8 0x1ba8
++#define R_0x1bac 0x1bac
++#define R_0x1bb0 0x1bb0
++#define R_0x1bb4 0x1bb4
++#define R_0x1bb8 0x1bb8
++#define R_0x1bbc 0x1bbc
++#define R_0x1bc0 0x1bc0
++#define R_0x1bc8 0x1bc8
++#define R_0x1bca 0x1bca
++#define R_0x1bcb 0x1bcb
++#define R_0x1bcc 0x1bcc
++#define R_0x1bce 0x1bce
++#define R_0x1bd0 0x1bd0
++#define R_0x1bd4 0x1bd4
++#define R_0x1bd6 0x1bd6
++#define R_0x1bd8 0x1bd8
++#define R_0x1bdc 0x1bdc
++#define R_0x1be4 0x1be4
++#define R_0x1be8 0x1be8
++#define R_0x1beb 0x1beb
++#define R_0x1bec 0x1bec
++#define R_0x1bef 0x1bef
++#define R_0x1bf0 0x1bf0
++#define R_0x1bf4 0x1bf4
++#define R_0x1bf8 0x1bf8
++#define R_0x1bfc 0x1bfc
++#define R_0x1c 0x1c
++#define R_0x1c20 0x1c20
++#define R_0x1c24 0x1c24
++#define R_0x1c28 0x1c28
++#define R_0x1c2c 0x1c2c
++#define R_0x1c30 0x1c30
++#define R_0x1c34 0x1c34
++#define R_0x1c38 0x1c38
++#define R_0x1c3c 0x1c3c
++#define R_0x1c64 0x1c64
++#define R_0x1c68 0x1c68
++#define R_0x1c6c 0x1c6c
++#define R_0x1c74 0x1c74
++#define R_0x1c78 0x1c78
++#define R_0x1c7c 0x1c7c
++#define R_0x1c80 0x1c80
++#define R_0x1c90 0x1c90
++#define R_0x1c94 0x1c94
++#define R_0x1c98 0x1c98
++#define R_0x1c9c 0x1c9c
++#define R_0x1ca0 0x1ca0
++#define R_0x1ca4 0x1ca4
++#define R_0x1cb0 0x1cb0
++#define R_0x1cb8 0x1cb8
++#define R_0x1cc0 0x1cc0
++#define R_0x1cd0 0x1cd0
++#define R_0x1ce4 0x1ce4
++#define R_0x1ce8 0x1ce8
++#define R_0x1cec 0x1cec
++#define R_0x1cf0 0x1cf0
++#define R_0x1cf4 0x1cf4
++#define R_0x1cf8 0x1cf8
++#define R_0x1d04 0x1d04
++#define R_0x1d08 0x1d08
++#define R_0x1d0c 0x1d0c
++#define R_0x1d10 0x1d10
++#define R_0x1d2c 0x1d2c
++#define R_0x1d30 0x1d30
++#define R_0x1d3c 0x1d3c
++#define R_0x1d44 0x1d44
++#define R_0x1d48 0x1d48
++#define R_0x1d58 0x1d58
++#define R_0x1d60 0x1d60
++#define R_0x1d6c 0x1d6c
++#define R_0x1d70 0x1d70
++#define R_0x1d90 0x1d90
++#define R_0x1d94 0x1d94
++#define R_0x1d9c 0x1d9c
++#define R_0x1da4 0x1da4
++#define R_0x1da8 0x1da8
++#define R_0x1de8 0x1de8
++#define R_0x1e14 0x1e14
++#define R_0x1e18 0x1e18
++#define R_0x1e1c 0x1e1c
++#define R_0x1e24 0x1e24
++#define R_0x1e28 0x1e28
++#define R_0x1e2c 0x1e2c
++#define R_0x1e28 0x1e28
++#define R_0x1e30 0x1e30
++#define R_0x1e40 0x1e40
++#define R_0x1e44 0x1e44
++#define R_0x1e48 0x1e48
++#define R_0x1e5c 0x1e5c
++#define R_0x1e60 0x1e60
++#define R_0x1e64 0x1e64
++#define R_0x1e68 0x1e68
++#define R_0x1e6c 0x1e6c
++#define R_0x1e70 0x1e70
++#define R_0x1e7c 0x1e7c
++#define R_0x1e80 0x1e80
++#define R_0x1e84 0x1e84
++#define R_0x1e88 0x1e88
++#define R_0x1e8c 0x1e8c
++#define R_0x1ea4 0x1ea4
++#define R_0x1eb4 0x1eb4
++#define R_0x1eb8 0x1eb8
++#define R_0x1ee8 0x1ee8
++#define R_0x1eec 0x1eec
++#define R_0x1ef0 0x1ef0
++#define R_0x1ef4 0x1ef4
++#define R_0x1efc 0x1efc
++#define R_0x24 0x24
++#define R_0x28 0x28
++#define R_0x2c 0x2c
++#define R_0x28a4 0x28a4
++#define R_0x2c04 0x2c04
++#define R_0x2c08 0x2c08
++#define R_0x2c0c 0x2c0c
++#define R_0x2c10 0x2c10
++#define R_0x2c14 0x2c14
++#define R_0x2c18 0x2c18
++#define R_0x2c1c 0x2c1c
++#define R_0x2c20 0x2c20
++#define R_0x2c2c 0x2c2c
++#define R_0x2c30 0x2c30
++#define R_0x2c34 0x2c34
++#define R_0x2c54 0x2c54
++#define R_0x2d00 0x2d00
++#define R_0x2d04 0x2d04
++#define R_0x2d08 0x2d08
++#define R_0x2d0c 0x2d0c
++#define R_0x2d10 0x2d10
++#define R_0x2d20 0x2d20
++#define R_0x2d38 0x2d38
++#define R_0x2d40 0x2d40
++#define R_0x2d44 0x2d44
++#define R_0x2d48 0x2d48
++#define R_0x2d4c 0x2d4c
++#define R_0x2d88 0x2d88
++#define R_0x2d90 0x2d90
++#define R_0x2d9c 0x2d9c
++#define R_0x2db4 0x2db4
++#define R_0x2db8 0x2db8
++#define R_0x2dbc 0x2dbc
++#define R_0x2de0 0x2de0
++#define R_0x2de4 0x2de4
++#define R_0x2de8 0x2de8
++#define R_0x2e00 0x2e00
++#define R_0x2e20 0x2e20
++#define R_0x300 0x300
++#define R_0x38 0x38
++#define R_0x3a00 0x3a00
++#define R_0x3a04 0x3a04
++#define R_0x3a08 0x3a08
++#define R_0x3a0c 0x3a0c
++#define R_0x3a10 0x3a10
++#define R_0x3a14 0x3a14
++#define R_0x3a18 0x3a18
++#define R_0x3a1c 0x3a1c
++#define R_0x3a20 0x3a20
++#define R_0x3a24 0x3a24
++#define R_0x3a28 0x3a28
++#define R_0x3a2c 0x3a2c
++#define R_0x3a30 0x3a30
++#define R_0x3a34 0x3a34
++#define R_0x3a38 0x3a38
++#define R_0x3a3c 0x3a3c
++#define R_0x3a40 0x3a40
++#define R_0x3a44 0x3a44
++#define R_0x3a48 0x3a48
++#define R_0x3a4c 0x3a4c
++#define R_0x3a50 0x3a50               
++#define R_0x3a54 0x3a54
++#define R_0x3a58 0x3a58
++#define R_0x3a5c 0x3a5c
++#define R_0x3a60 0x3a60
++#define R_0x3a64 0x3a64
++#define R_0x3a68 0x3a68
++#define R_0x3a6c 0x3a6c
++#define R_0x3a70 0x3a70
++#define R_0x3a74 0x3a74
++#define R_0x3a78 0x3a78
++#define R_0x3a7c 0x3a7c
++#define R_0x3a80 0x3a80
++#define R_0x3a84 0x3a84
++#define R_0x3a88 0x3a88
++#define R_0x3a8c 0x3a8c
++#define R_0x3a90 0x3a90
++#define R_0x3a94 0x3a94
++#define R_0x3a98 0x3a98
++#define R_0x3a9c 0x3a9c
++#define R_0x3aa0 0x3aa0
++#define R_0x3aa4 0x3aa4
++#define R_0x3c00 0x3c00
++#define R_0x40 0x40
++#define R_0x4000 0x4000
++#define R_0x4008 0x4008
++#define R_0x4018 0x4018
++#define R_0x401c 0x401c
++#define R_0x4028 0x4028
++#define R_0x4040 0x4040
++#define R_0x4044 0x4044
++#define R_0x4100 0x4100
++#define R_0x4104 0x4104
++#define R_0x4108 0x4108
++#define R_0x410c 0x410c
++#define R_0x4110 0x4110
++#define R_0x4114 0x4114
++#define R_0x4118 0x4118
++#define R_0x411c 0x411c
++#define R_0x4130 0x4130
++#define R_0x4134 0x4134
++#define R_0x4138 0x4138
++#define R_0x413c 0x413c
++#define R_0x4140 0x4140
++#define R_0x4144 0x4144
++#define R_0x4148 0x4148
++#define R_0x4160 0x4160
++#define R_0x4164 0x4164
++#define R_0x4168 0x4168
++#define R_0x416c 0x416c
++#define R_0x4180 0x4180
++#define R_0x419c 0x419c
++#define R_0x41a0 0x41a0
++#define R_0x41a4 0x41a4
++#define R_0x41a8 0x41a8
++#define R_0x41ac 0x41ac
++#define R_0x41e0 0x41e0
++#define R_0x41e8 0x41e8
++#define R_0x41ec 0x41ec
++#define R_0x41f0 0x41f0
++#define R_0x41f8 0x41f8
++#define R_0x41fc 0x41fc
++#define R_0x42 0x42
++#define R_0x430 0x430
++#define R_0x434 0x434
++#define R_0x44 0x44
++#define R_0x440 0x440
++#define R_0x444 0x444
++#define R_0x448 0x448
++#define R_0x450 0x450
++#define R_0x454 0x454
++#define R_0x49c 0x49c
++#define R_0x4a0 0x4a0
++#define R_0x4a4 0x4a4
++#define R_0x4a8 0x4a8
++#define R_0x4c 0x4c
++#define R_0x4c8 0x4c8
++#define R_0x4cc 0x4cc
++#define R_0x45a4 0x45a4
++#define R_0x4c00 0x4c00
++#define R_0x5000 0x5000
++#define R_0x5008 0x5008
++#define R_0x5018 0x5018
++#define R_0x501c 0x501c
++#define R_0x5028 0x5028
++#define R_0x5040 0x5040
++#define R_0x5044 0x5044
++#define R_0x5100 0x5100
++#define R_0x5108 0x5108
++#define R_0x5118 0x5118
++#define R_0x511c 0x511c
++#define R_0x5128 0x5128
++#define R_0x5140 0x5140
++#define R_0x5144 0x5144
++#define R_0x520 0x520
++#define R_0x5200 0x5200
++#define R_0x520c 0x520c
++#define R_0x522 0x522
++#define R_0x524 0x524
++#define R_0x5230 0x5230
++#define R_0x5234 0x5234
++#define R_0x5238 0x5238
++#define R_0x523c 0x523c
++#define R_0x5240 0x5240
++#define R_0x5244 0x5244
++#define R_0x5248 0x5248
++#define R_0x526c 0x526c
++#define R_0x5280 0x5280
++#define R_0x52a0 0x52a0
++#define R_0x52a4 0x52a4
++#define R_0x52ac 0x52ac
++#define R_0x52e8 0x52e8
++#define R_0x5300 0x5300
++#define R_0x530c 0x530c
++#define R_0x5330 0x5330
++#define R_0x5334 0x5334
++#define R_0x5338 0x5338
++#define R_0x533c 0x533c
++#define R_0x5340 0x5340
++#define R_0x5344 0x5344
++#define R_0x5348 0x5348
++#define R_0x536c 0x536c
++#define R_0x5380 0x5380
++#define R_0x53a0 0x53a0
++#define R_0x53a4 0x53a4
++#define R_0x53ac 0x53ac
++#define R_0x53e8 0x53e8
++#define R_0x550 0x550
++#define R_0x551 0x551
++#define R_0x568 0x568
++#define R_0x588 0x588
++#define R_0x60 0x60
++#define R_0x604 0x604
++#define R_0x608 0x608
++#define R_0x60c 0x60c
++#define R_0x60f 0x60f
++#define R_0x64 0x64
++#define R_0x66 0x66
++#define R_0x660 0x660
++#define R_0x668 0x668
++#define R_0x688 0x688
++#define R_0x6a0 0x6a0
++#define R_0x6d8 0x6d8
++#define R_0x6dc 0x6dc
++#define R_0x6f8 0x6f8
++#define R_0x70 0x70
++#define R_0x74 0x74
++#define R_0x700 0x700
++#define R_0x71c 0x71c
++#define R_0x72c 0x72c
++#define R_0x764 0x764
++#define R_0x7b0 0x7b0
++#define R_0x7b4 0x7b4
++#define R_0x7c0 0x7c0
++#define R_0x7c4 0x7c4
++#define R_0x7c8 0x7c8
++#define R_0x7cc 0x7cc
++#define R_0x7f0 0x7f0
++#define R_0x7f4 0x7f4
++#define R_0x7f8 0x7f8
++#define R_0x7fc 0x7fc
++#define R_0x800 0x800
++#define R_0x8000 0x8000
++#define R_0x804 0x804
++#define R_0x808 0x808
++#define R_0x80c 0x80c
++#define R_0x810 0x810
++#define R_0x814 0x814
++#define R_0x818 0x818
++#define R_0x81c 0x81c
++#define R_0x820 0x820
++#define R_0x824 0x824
++#define R_0x828 0x828
++#define R_0x82c 0x82c
++#define R_0x830 0x830
++#define R_0x834 0x834
++#define R_0x838 0x838
++#define R_0x83c 0x83c
++#define R_0x840 0x840
++#define R_0x844 0x840
++#define R_0x848 0x848
++#define R_0x84c 0x84c
++#define R_0x850 0x850
++#define R_0x854 0x854
++#define R_0x858 0x858
++#define R_0x85c 0x85c
++#define R_0x860 0x860
++#define R_0x864 0x864
++#define R_0x868 0x868
++#define R_0x86c 0x86c
++#define R_0x870 0x870
++#define R_0x874 0x874
++#define R_0x878 0x878
++#define R_0x87c 0x87c
++#define R_0x880 0x880
++#define R_0x884 0x884
++#define R_0x888 0x888
++#define R_0x88c 0x88c
++#define R_0x890 0x890
++#define R_0x894 0x894
++#define R_0x898 0x898
++#define R_0x89c 0x89c
++#define R_0x8a0 0x8a0
++#define R_0x8a4 0x8a4
++#define R_0x8ac 0x8ac
++#define R_0x8b4 0x8b4
++#define R_0x8b8 0x8b8
++#define R_0x8c0 0x8c0
++#define R_0x8c4 0x8c4
++#define R_0x8c8 0x8c8
++#define R_0x8cc 0x8cc
++#define R_0x8d0 0x8d0
++#define R_0x8d4 0x8d4
++#define R_0x8d8 0x8d8
++#define R_0x8dc 0x8dc
++#define R_0x8f0 0x8f0
++#define R_0x8f8 0x8f8
++#define R_0x8fc 0x8fc
++#define R_0x900 0x900
++#define R_0x908 0x908
++#define R_0x90c 0x90c
++#define R_0x910 0x910
++#define R_0x914 0x914
++#define R_0x918 0x918
++#define R_0x91c 0x91c
++#define R_0x920 0x920
++#define R_0x924 0x924
++#define R_0x92c 0x92c
++#define R_0x930 0x930
++#define R_0x934 0x934
++#define R_0x938 0x938
++#define R_0x93c 0x93c
++#define R_0x940 0x940
++#define R_0x944 0x944
++#define R_0x948 0x948
++#define R_0x94c 0x94c
++#define R_0x950 0x950
++#define R_0x954 0x954
++#define R_0x958 0x958
++#define R_0x95c 0x95c
++#define R_0x960 0x960
++#define R_0x964 0x964
++#define R_0x968 0x968
++#define R_0x970 0x970
++#define R_0x974 0x974
++#define R_0x978 0x978
++#define R_0x97c 0x97c
++#define R_0x988 0x988
++#define R_0x98c 0x98c
++#define R_0x990 0x990
++#define R_0x994 0x994
++#define R_0x998 0x998
++#define R_0x99c 0x99c
++#define R_0x9a0 0x9a0
++#define R_0x9a4 0x9a4
++#define R_0x9ac 0x9ac
++#define R_0x9b0 0x9b0
++#define R_0x9b4 0x9b4
++#define R_0x9b8 0x9b8
++#define R_0x9cc 0x9cc
++#define R_0x9d0 0x9d0
++#define R_0x9e4 0x9e4
++#define R_0x9e8 0x9e8
++#define R_0x9f0 0x9f0
++#define R_0xa0 0xa0
++#define R_0xa00 0xa00
++#define R_0xa04 0xa04
++#define R_0xa08 0xa08
++#define R_0xa0a 0xa0a
++#define R_0xa0c 0xa0c
++#define R_0xa10 0xa10
++#define R_0xa14 0xa14
++#define R_0xa20 0xa20
++#define R_0xa24 0xa24
++#define R_0xa28 0xa28
++#define R_0xa2c 0xa2c
++#define R_0xa40 0xa40
++#define R_0xa44 0xa44
++#define R_0xa48 0xa48
++#define R_0xa4c 0xa4c
++#define R_0xa50 0xa50
++#define R_0xa54 0xa54
++#define R_0xa58 0xa58
++#define R_0xa68 0xa68
++#define R_0xa6c 0xa6c
++#define R_0xa70 0xa70
++#define R_0xa74 0xa74
++#define R_0xa78 0xa78
++#define R_0xa8 0xa8
++#define R_0xa80 0xa80
++#define R_0xa84 0xa84
++#define R_0xa98 0xa98
++#define R_0xa9c 0xa9c
++#define R_0xaa8 0xaa8
++#define R_0xaac 0xaac
++#define R_0xab4 0xab4
++#define R_0xabc 0xabc
++#define R_0xac8 0xac8
++#define R_0xacc 0xacc
++#define R_0xad0 0xad0
++#define R_0xb0 0xb0
++#define R_0xb00 0xb00
++#define R_0xb04 0xb04
++#define R_0xb07 0xb07
++#define R_0xb08 0xb08
++#define R_0xb0c 0xb0c
++#define R_0xb10 0xb10
++#define R_0xb14 0xb14
++#define R_0xb18 0xb18
++#define R_0xb1c 0xb1c
++#define R_0xb20 0xb20
++#define R_0xb24 0xb24
++#define R_0xb28 0xb28
++#define R_0xb2a 0xb2a
++#define R_0xb2b 0xb2b
++#define R_0xb2c 0xb2c
++#define R_0xb30 0xb30
++#define R_0xb34 0xb34
++#define R_0xb38 0xb38
++#define R_0xb3b 0xb3b
++#define R_0xb3c 0xb3c
++#define R_0xb40 0xb40
++#define R_0xb44 0xb44
++#define R_0xb48 0xb48
++#define R_0xb54 0xb54
++#define R_0xb58 0xb58
++#define R_0xb60 0xb60
++#define R_0xb64 0xb64
++#define R_0xb68 0xb68
++#define R_0xb6a 0xb6a
++#define R_0xb6b 0xb6b
++#define R_0xb6c 0xb6c
++#define R_0xb6e 0xb6e
++#define R_0xb70 0xb70
++#define R_0xb74 0xb74
++#define R_0xb77 0xb77
++#define R_0xb78 0xb78
++#define R_0xb7c 0xb7c
++#define R_0xb80 0xb80
++#define R_0xb84 0xb84
++#define R_0xb88 0xb88
++#define R_0xb8c 0xb8c
++#define R_0xb90 0xb90
++#define R_0xb94 0xb94
++#define R_0xb98 0xb98
++#define R_0xb9b 0xb9b
++#define R_0xb9c 0xb9c
++#define R_0xba0 0xba0
++#define R_0xba4 0xba4
++#define R_0xba8 0xba8
++#define R_0xbac 0xbac
++#define R_0xbad 0xbad
++#define R_0xbc0 0xbc0
++#define R_0xbc4 0xbc4
++#define R_0xbc8 0xbc8
++#define R_0xbcc 0xbcc
++#define R_0xbd8 0xbd8
++#define R_0xbdc 0xbdc
++#define R_0xbe0 0xbe0
++#define R_0xbe4 0xbe4
++#define R_0xbe8 0xbe8
++#define R_0xbec 0xbec
++#define R_0xbf0 0xbf0
++#define R_0xbf4 0xbf4
++#define R_0xbf8 0xbf8
++#define R_0xc00 0xc00
++#define R_0xc04 0xc04
++#define R_0xc08 0xc08
++#define R_0xc0c 0xc0c
++#define R_0xc10 0xc10
++#define R_0xc14 0xc14
++#define R_0xc18 0xc18
++#define R_0xc1c 0xc1c
++#define R_0xc20 0xc20
++#define R_0xc24 0xc24
++#define R_0xc2c 0xc2c
++#define R_0xc30 0xc30
++#define R_0xc38 0xc38
++#define R_0xc3c 0xc3c
++#define R_0xc40 0xc40
++#define R_0xc44 0xc44
++#define R_0xc4c 0xc4c
++#define R_0xc50 0xc50
++#define R_0xc54 0xc54
++#define R_0xc58 0xc58
++#define R_0xc5c 0xc5c
++#define R_0xc6c 0xc6c
++#define R_0xc70 0xc70
++#define R_0xc74 0xc74
++#define R_0xc78 0xc78
++#define R_0xc7c 0xc7c
++#define R_0xc80 0xc80
++#define R_0xc84 0xc84
++#define R_0xc88 0xc88
++#define R_0xc8c 0xc8c
++#define R_0xc90 0xc90
++#define R_0xc94 0xc94
++#define R_0xc9c 0xc9c
++#define R_0xca0 0xca0
++#define R_0xca4 0xca4
++#define R_0xca8 0xca8
++#define R_0xcac 0xcac
++#define R_0xcb0 0xcb0
++#define R_0xcb4 0xcb4
++#define R_0xcb8 0xcb8
++#define R_0xcbc 0xcbc
++#define R_0xcbd 0xcbd
++#define R_0xcbe 0xcbe
++#define R_0xcc0 0xcc0
++#define R_0xcc4 0xcc4
++#define R_0xcc8 0xcc8
++#define R_0xccc 0xccc
++#define R_0xcd0 0xcd0
++#define R_0xcd4 0xcd4
++#define R_0xcd8 0xcd8
++#define R_0xce0 0xce0
++#define R_0xce4 0xce4
++#define R_0xce8 0xce8
++#define R_0xd00 0xd00
++#define R_0xd04 0xd04
++#define R_0xd08 0xd08
++#define R_0xd0c 0xd0c
++#define R_0xd10 0xd10
++#define R_0xd14 0xd14
++#define R_0xd2c 0xd2c
++#define R_0xd30 0xd30
++#define R_0xd40 0xd40
++#define R_0xd44 0xd44
++#define R_0xd48 0xd48
++#define R_0xd4c 0xd4c
++#define R_0xd50 0xd50
++#define R_0xd54 0xd54
++#define R_0xd5c 0xd5c
++#define R_0xd6c 0xd6c
++#define R_0xd7c 0xd7c
++#define R_0xd80 0xd80
++#define R_0xd84 0xd84
++#define R_0xd8c 0xd8c
++#define R_0xd90 0xd90
++#define R_0xd94 0xd94
++#define R_0xdac 0xdac
++#define R_0xdb0 0xdb0
++#define R_0xdb4 0xdb4
++#define R_0xdb8 0xdb8
++#define R_0xdbc 0xdbc
++#define R_0xdcc 0xdcc
++#define R_0xdd0 0xdd0
++#define R_0xdd4 0xdd4
++#define R_0xdd8 0xdd8
++#define R_0xde0 0xde0
++#define R_0xdec 0xdec
++#define R_0xdf4 0xdf4
++#define R_0xe00 0xe00
++#define R_0xe04 0xe04
++#define R_0xe08 0xe08
++#define R_0xe10 0xe10
++#define R_0xe14 0xe14
++#define R_0xe18 0xe18
++#define R_0xe1c 0xe1c
++#define R_0xe20 0xe20
++#define R_0xe24 0xe24
++#define R_0xe28 0xe28
++#define R_0xe30 0xe30
++#define R_0xe34 0xe34
++#define R_0xe38 0xe38
++#define R_0xe3c 0xe3c
++#define R_0xe40 0xe40
++#define R_0xe44 0xe44
++#define R_0xe48 0xe48
++#define R_0xe4c 0xe4c
++#define R_0xe50 0xe50
++#define R_0xe54 0xe54
++#define R_0xe5c 0xe5c
++#define R_0xe64 0xe64
++#define R_0xe6c 0xe6c
++#define R_0xe70 0xe70
++#define R_0xe74 0xe74
++#define R_0xe78 0xe78
++#define R_0xe7c 0xe7c
++#define R_0xe80 0xe80
++#define R_0xe84 0xe84
++#define R_0xe88 0xe88
++#define R_0xe8c 0xe8c
++#define R_0xe90 0xe90
++#define R_0xe94 0xe94
++#define R_0xe98 0xe98
++#define R_0xe9c 0xe9c
++#define R_0xea0 0xea0
++#define R_0xea4 0xea4
++#define R_0xea8 0xea8
++#define R_0xeac 0xeac
++#define R_0xeb0 0xeb0
++#define R_0xeb4 0xeb4
++#define R_0xeb8 0xeb8
++#define R_0xebc 0xebc
++#define R_0xec 0xec
++#define R_0xec0 0xec0
++#define R_0xec4 0xec4
++#define R_0xec8 0xec8
++#define R_0xecc 0xecc
++#define R_0xed0 0xed0
++#define R_0xed4 0xed4
++#define R_0xed8 0xed8
++#define R_0xedc 0xedc
++#define R_0xee0 0xee0
++#define R_0xee8 0xee8
++#define R_0xeec 0xeec
++#define R_0xf0 0xf0
++#define R_0xf00 0xf00
++#define R_0xf04 0xf04
++#define R_0xf08 0xf08
++#define R_0xf0c 0xf0c
++#define R_0xf10 0xf10
++#define R_0xf14 0xf14
++#define R_0xf18 0xf18
++#define R_0xf1c 0xf1c
++#define R_0xf20 0xf20
++#define R_0xf2c 0xf2c
++#define R_0xf30 0xf30
++#define R_0xf34 0xf34
++#define R_0xf4 0xf4
++#define R_0xf44 0xf44
++#define R_0xf48 0xf48
++#define R_0xf4c 0xf4c
++#define R_0xf50 0xf50
++#define R_0xf54 0xf54
++#define R_0xf58 0xf58
++#define R_0xf5c 0xf5c
++#define R_0xf70 0xf70
++#define R_0xf74 0xf74
++#define R_0xf80 0xf80
++#define R_0xf84 0xf84
++#define R_0xf87 0xf87
++#define R_0xf88 0xf88
++#define R_0xf8c 0xf8c
++#define R_0xf90 0xf90
++#define R_0xf94 0xf94
++#define R_0xf98 0xf98
++#define R_0xf9c 0xf9c
++#define R_0xfa0 0xfa0
++#define R_0xfa4 0xfa4
++#define R_0xfa8 0xfa8
++#define R_0xfac 0xfac
++#define R_0xfb0 0xfb0
++#define R_0xfb4 0xfb4
++#define R_0xfb8 0xfb8
++#define R_0xfbc 0xfbc
++#define R_0xfc0 0xfc0
++#define R_0xfc4 0xfc4
++#define R_0xfc8 0xfc8
++#define R_0xfcc 0xfcc
++#define R_0xfd0 0xfd0
++#define R_0xff0 0xff0
++#define RF_0x0 0x0
++#define RF_0x00 0x00
++#define RF_0x08 0x08
++#define RF_0x0c 0x0c
++#define RF_0x0d 0x0d
++#define RF_0x1 0x1
++#define RF_0x18 0x18
++#define RF_0x19 0x19
++#define RF_0x1a 0x1a
++#define RF_0x1bf0 0x1bf0
++#define RF_0x2 0x2
++#define RF_0x3 0x3
++#define RF_0x30 0x30
++#define RF_0x31 0x31
++#define RF_0x32 0x32
++#define RF_0x33 0x33
++#define RF_0x35 0x35
++#define RF_0x3e 0x3e
++#define RF_0x3f 0x3f
++#define RF_0x4 0x4
++#define RF_0x42 0x42
++#define RF_0x43 0x43
++#define RF_0x51 0x51
++#define RF_0x52 0x52
++#define RF_0x53 0x53
++#define RF_0x54 0x54
++#define RF_0x55 0x55
++#define RF_0x56 0x56
++#define RF_0x57 0x57
++#define RF_0x58 0x58
++#define RF_0x5c 0x5c
++#define RF_0x5d 0x5d
++#define RF_0x60 0x60
++#define RF_0x61 0x61
++#define RF_0x63 0x63
++#define RF_0x64 0x64
++#define RF_0x65 0x65
++#define RF_0x66 0x66
++#define RF_0x67 0x67
++#define RF_0x6e 0x6e
++#define RF_0x6f 0x6f
++#define RF_0x75 0x75
++#define RF_0x76 0x76
++#define RF_0x78 0x78
++#define RF_0x7c 0x7c
++#define RF_0x7f 0x7f
++#define RF_0x8 0x8
++#define RF_0x80 0x80
++#define RF_0x81 0x81
++#define RF_0x82 0x82
++#define RF_0x83 0x83
++#define RF_0x85 0x85
++#define RF_0x86 0x86
++#define RF_0x87 0x87
++#define RF_0x8a 0x8a
++#define RF_0x8b 0x8b
++#define RF_0x8c 0x8c
++#define RF_0x8d 0x8d
++#define RF_0x8f 0x8f
++#define RF_0x93 0x93
++#define RF_0x9e 0x9e
++#define RF_0xa3 0xa3
++#define RF_0xa9 0xa9
++#define RF_0xae 0xae
++#define RF_0xb0 0xb0
++#define RF_0xb3 0xb3
++#define RF_0xb4 0xb4
++#define RF_0xb8 0xb8
++#define RF_0xbc 0xbc
++#define RF_0xbe 0xbe
++#define RF_0xc4 0xc4
++#define RF_0xc8 0xc8
++#define RF_0xc9 0xc9
++#define RF_0xca 0xca
++#define RF_0xcc 0xcc
++#define RF_0xd 0xd
++#define RF_0xdd 0xdd
++#define RF_0xde 0xde
++#define RF_0xdf 0xdf
++#define RF_0xed 0xed
++#define RF_0xee 0xee
++#define RF_0xef 0xef
++#define RF_0xf5 0xf5
++#define RF_0xf6 0xf6
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_rssi_monitor.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_rssi_monitor.c
+new file mode 100644
+index 000000000..1fde03691
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_rssi_monitor.c
+@@ -0,0 +1,189 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ ************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#ifdef PHYDM_SUPPORT_RSSI_MONITOR
++
++void phydm_rssi_monitor_h2c(void *dm_void, u8 macid)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_t = &dm->dm_ra_table;
++	struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
++	struct ra_sta_info *ra = NULL;
++	#ifdef CONFIG_BEAMFORMING
++	struct bf_cmn_info *bf = NULL;
++	#endif
++	u8 h2c[H2C_MAX_LENGTH] = {0};
++	u8 stbc_en, ldpc_en;
++	u8 bf_en = 0;
++	u8 is_rx, is_tx;
++
++	if (is_sta_active(sta)) {
++		ra = &sta->ra_info;
++	} else {
++		PHYDM_DBG(dm, DBG_RSSI_MNTR, "[Warning] %s\n", __func__);
++		return;
++	}
++
++	PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
++	PHYDM_DBG(dm, DBG_RSSI_MNTR, "MACID=%d\n", sta->mac_id);
++
++	is_rx = (ra->txrx_state == RX_STATE) ? 1 : 0;
++	is_tx = (ra->txrx_state == TX_STATE) ? 1 : 0;
++	stbc_en = (sta->stbc_en) ? 1 : 0;
++	ldpc_en = (sta->ldpc_en) ? 1 : 0;
++
++	#ifdef CONFIG_BEAMFORMING
++	bf = &sta->bf_info;
++
++	if ((bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMEE_ENABLE) ||
++	    (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMEE_ENABLE))
++		bf_en = 1;
++	#endif
++
++	PHYDM_DBG(dm, DBG_RSSI_MNTR, "RA_th_ofst=(( %s%d ))\n",
++		  ((ra_t->ra_ofst_direc) ? "+" : "-"), ra_t->ra_th_ofst);
++
++	h2c[0] = sta->mac_id;
++	h2c[1] = 0;
++	h2c[2] = sta->rssi_stat.rssi;
++	h2c[3] = is_rx | (stbc_en << 1) |
++		     ((dm->noisy_decision & 0x1) << 2) | (bf_en << 6);
++	h2c[4] = (ra_t->ra_th_ofst & 0x7f) |
++		     ((ra_t->ra_ofst_direc & 0x1) << 7);
++	h2c[5] = 0;
++	h2c[6] = ((ra_t->ra_trigger_mode) << 2);
++
++	PHYDM_DBG(dm, DBG_RSSI_MNTR, "PHYDM h2c[0x42]=0x%x %x %x %x %x %x %x\n",
++		  h2c[6], h2c[5], h2c[4], h2c[3], h2c[2], h2c[1], h2c[0]);
++
++	#if (RTL8188E_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8188E)
++		odm_ra_set_rssi_8188e(dm, sta->mac_id, sta->rssi_stat.rssi);
++	else
++	#endif
++	{
++		odm_fill_h2c_cmd(dm, ODM_H2C_RSSI_REPORT, H2C_MAX_LENGTH, h2c);
++	}
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++void phydm_sta_rssi_init(void *dm_void, u8 macid, u8 init_rssi)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *sta = NULL;
++	struct rssi_info *rssi_t = NULL;
++
++	PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
++
++	sta = dm->phydm_sta_info[macid];
++	rssi_t = &sta->rssi_stat;
++
++	rssi_t->rssi_acc = (init_rssi << RSSI_MA);
++	rssi_t->rssi = init_rssi;
++}
++#endif
++void phydm_calculate_rssi_min_max(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct cmn_sta_info *sta;
++	s8 rssi_max_tmp = 0, rssi_min_tmp = 100;
++	u8 i;
++	u8 sta_cnt = 0;
++
++	if (!dm->is_linked)
++		return;
++
++	PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
++
++	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
++		sta = dm->phydm_sta_info[i];
++		if (is_sta_active(sta)) {
++			sta_cnt++;
++
++			if (sta->rssi_stat.rssi < rssi_min_tmp) {
++				rssi_min_tmp = sta->rssi_stat.rssi;
++				dm->rssi_min_macid = i;
++			}
++
++			if (sta->rssi_stat.rssi > rssi_max_tmp) {
++				rssi_max_tmp = sta->rssi_stat.rssi;
++				dm->rssi_max_macid = i;
++			}
++
++			/*@[Send RSSI to FW]*/
++			if (!sta->ra_info.disable_ra)
++				phydm_rssi_monitor_h2c(dm, i);
++
++			if (sta_cnt == dm->number_linked_client)
++				break;
++		}
++	}
++	dm->pre_rssi_min = dm->rssi_min;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	if (dm->number_linked_client == 0)
++		return;
++#endif
++	dm->rssi_max = (u8)rssi_max_tmp;
++	dm->rssi_min = (u8)rssi_min_tmp;
++}
++
++void phydm_rssi_monitor_check(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (!(dm->support_ability & ODM_BB_RSSI_MONITOR))
++		return;
++
++	/*@for AP watchdog period = 1 sec*/
++	if ((dm->phydm_sys_up_time % 2) == 1)
++		return;
++
++	PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
++
++	phydm_calculate_rssi_min_max(dm);
++
++	PHYDM_DBG(dm, DBG_RSSI_MNTR, "RSSI {max, min} = {%d, %d}\n",
++		  dm->rssi_max, dm->rssi_min);
++}
++
++void phydm_rssi_monitor_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct ra_table *ra_tab = &dm->dm_ra_table;
++
++	dm->pre_rssi_min = 0;
++	dm->rssi_max = 0;
++	dm->rssi_min = 0;
++}
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_rssi_monitor.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_rssi_monitor.h
+new file mode 100644
+index 000000000..b0f446ea2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_rssi_monitor.h
+@@ -0,0 +1,58 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_RSSI_MONITOR_H__
++#define __PHYDM_RSSI_MONITOR_H__
++
++#define RSSI_MONITOR_VERSION "2.0"
++
++/* @1 ============================================================
++ * 1  Definition
++ * 1 ============================================================
++ */
++
++/* @1 ============================================================
++ * 1  structure
++ * 1 ============================================================
++ */
++
++/* @1 ============================================================
++ * 1  enumeration
++ * 1 ============================================================
++ */
++
++/* @1 ============================================================
++ * 1  function prototype
++ * 1 ============================================================
++ */
++
++void phydm_rssi_monitor_check(void *dm_void);
++
++void phydm_rssi_monitor_init(void *dm_void);
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++void phydm_sta_rssi_init(void *dm_void, u8 macid, u8 init_rssi);
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_smt_ant.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_smt_ant.c
+new file mode 100644
+index 000000000..8e805b3ce
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_smt_ant.c
+@@ -0,0 +1,2277 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/* ************************************************************
++ * include files
++ * ************************************************************ */
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++/*******************************************************
++ * when antenna test utility is on or some testing need to disable antenna diversity
++ * call this function to disable all ODM related mechanisms which will switch antenna.
++ ******************************************************/
++#if (defined(CONFIG_SMART_ANTENNA))
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++#if (RTL8198F_SUPPORT == 1)
++void phydm_smt_ant_init_98f(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 val = 0;
++
++	#if 0
++	odm_set_bb_reg(dm, R_0x1da4, 0x3c, 4); /*6.25*4 = 25ms*/
++	odm_set_bb_reg(dm, R_0x1da4, BIT(6), 1);
++	odm_set_bb_reg(dm, R_0x1da4, BIT(7), 1);
++	#endif
++}
++#endif
++#endif
++
++#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
++void phydm_cumitek_smt_ant_mapping_table_8822b(
++	void *dm_void,
++	u8 *table_path_a,
++	u8 *table_path_b)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 path_a_0to3_idx = 0;
++	u32 path_b_0to3_idx = 0;
++	u32 path_a_4to7_idx = 0;
++	u32 path_b_4to7_idx = 0;
++
++	path_a_0to3_idx = ((table_path_a[3] & 0xf) << 24) | ((table_path_a[2] & 0xf) << 16) | ((table_path_a[1] & 0xf) << 8) | (table_path_a[0] & 0xf);
++
++	path_b_0to3_idx = ((table_path_b[3] & 0xf) << 28) | ((table_path_b[2] & 0xf) << 20) | ((table_path_b[1] & 0xf) << 12) | ((table_path_b[0] & 0xf) << 4);
++
++	path_a_4to7_idx = ((table_path_a[7] & 0xf) << 24) | ((table_path_a[6] & 0xf) << 16) | ((table_path_a[5] & 0xf) << 8) | (table_path_a[4] & 0xf);
++
++	path_b_4to7_idx = ((table_path_b[7] & 0xf) << 28) | ((table_path_b[6] & 0xf) << 20) | ((table_path_b[5] & 0xf) << 12) | ((table_path_b[4] & 0xf) << 4);
++
++#if 0
++	/*PHYDM_DBG(dm, DBG_SMT_ANT, "mapping table{A, B} = {0x%x, 0x%x}\n", path_a_0to3_idx, path_b_0to3_idx);*/
++#endif
++
++	/*pathA*/
++	odm_set_bb_reg(dm, R_0xca4, MASKDWORD, path_a_0to3_idx); /*@ant map 1*/
++	odm_set_bb_reg(dm, R_0xca8, MASKDWORD, path_a_4to7_idx); /*@ant map 2*/
++
++	/*pathB*/
++	odm_set_bb_reg(dm, R_0xea4, MASKDWORD, path_b_0to3_idx); /*@ant map 1*/
++	odm_set_bb_reg(dm, R_0xea8, MASKDWORD, path_b_4to7_idx); /*@ant map 2*/
++}
++
++void phydm_cumitek_smt_ant_init_8822b(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant *smtant_table = &dm->smtant_table;
++	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
++	u32 value32;
++
++	PHYDM_DBG(dm, DBG_SMT_ANT, "[8822B Cumitek SmtAnt Int]\n");
++
++	/*@========= MAC GPIO setting =================================*/
++
++	/* Pin, pin_name, RFE_CTRL_NUM*/
++
++	/* @A0, 55, 5G_TRSW, 3*/
++	/* @A1, 52, 5G_TRSW, 0*/
++	/* @A2, 25, 5G_TRSW, 8*/
++
++	/* @B0, 16, 5G_TRSW, 4*/
++	/* @B1, 13, 5G_TRSW, 11*/
++	/* @B2, 24, 5G_TRSW, 9*/
++
++	/*@for RFE_CTRL 8 & 9*/
++	odm_set_mac_reg(dm, R_0x4c, BIT(24) | BIT(23), 2);
++	odm_set_mac_reg(dm, R_0x44, BIT(27) | BIT(26), 0);
++
++	/*@for RFE_CTRL 0*/
++	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
++	odm_set_mac_reg(dm, R_0x64, BIT(29), 1);
++
++	/*@for RFE_CTRL 2 & 3*/
++	odm_set_mac_reg(dm, R_0x4c, BIT(26), 0);
++	odm_set_mac_reg(dm, R_0x64, BIT(28), 1);
++
++	/*@for RFE_CTRL 11*/
++	odm_set_mac_reg(dm, R_0x40, BIT(3), 1);
++
++	/*@0x604[25]=1 : 2bit mode for pathA&B&C&D*/
++	/*@0x604[25]=0 : 3bit mode for pathA&B*/
++	smtant_table->tx_desc_mode = 0;
++	odm_set_mac_reg(dm, R_0x604, BIT(25), (u32)smtant_table->tx_desc_mode);
++
++	/*@========= BB RFE setting =================================*/
++#if 0
++	/*path A*/
++	odm_set_bb_reg(dm, R_0x1990, BIT(3), 0);		/*RFE_CTRL_3*/ /*A_0*/
++	odm_set_bb_reg(dm, R_0xcbc, BIT(3), 0);		/*@inv*/
++	odm_set_bb_reg(dm, R_0xcb0, 0xf000, 8);
++
++	odm_set_bb_reg(dm, R_0x1990, BIT(0), 0);		/*RFE_CTRL_0*/ /*A_1*/
++	odm_set_bb_reg(dm, R_0xcbc, BIT(0), 0);		/*@inv*/
++	odm_set_bb_reg(dm, R_0xcb0, 0xf, 0x9);
++
++	odm_set_bb_reg(dm, R_0x1990, BIT(8), 0);		/*RFE_CTRL_8*/ /*A_2*/
++	odm_set_bb_reg(dm, R_0xcbc, BIT(8), 0);		/*@inv*/
++	odm_set_bb_reg(dm, R_0xcb4, 0xf, 0xa);
++
++
++	/*path B*/
++	odm_set_bb_reg(dm, R_0x1990, BIT(4), 1);		/*RFE_CTRL_4*/	/*B_0*/
++	odm_set_bb_reg(dm, R_0xdbc, BIT(4), 0);		/*@inv*/
++	odm_set_bb_reg(dm, R_0xdb0, 0xf0000, 0xb);
++
++	odm_set_bb_reg(dm, R_0x1990, BIT(11), 1);	/*RFE_CTRL_11*/	/*B_1*/
++	odm_set_bb_reg(dm, R_0xdbc, BIT(11), 0);		/*@inv*/
++	odm_set_bb_reg(dm, R_0xdb4, 0xf000, 0xc);
++
++	odm_set_bb_reg(dm, R_0x1990, BIT(9), 1);		/*RFE_CTRL_9*/	/*B_2*/
++	odm_set_bb_reg(dm, R_0xdbc, BIT(9), 0);		/*@inv*/
++	odm_set_bb_reg(dm, R_0xdb4, 0xf0, 0xd);
++#endif
++	/*@========= BB SmtAnt setting =================================*/
++	odm_set_mac_reg(dm, R_0x6d8, BIT(22) | BIT(21), 2); /*resp tx by register*/
++	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
++	odm_set_bb_reg(dm, R_0x804, BIT(4), 0); /*@lathch antsel*/
++	odm_set_bb_reg(dm, R_0x818, 0xf00000, 0); /*@keep tx by rx*/
++	odm_set_bb_reg(dm, R_0x900, BIT(19), 0); /*@fast train*/
++	odm_set_bb_reg(dm, R_0x900, BIT(18), 1); /*@1: by TXDESC*/
++
++	/*pathA*/
++	odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x03020100); /*@ant map 1*/
++	odm_set_bb_reg(dm, R_0xca8, MASKDWORD, 0x07060504); /*@ant map 2*/
++	odm_set_bb_reg(dm, R_0xcac, BIT(9), 0); /*@keep antsel map by GNT_BT*/
++
++	/*pathB*/
++	odm_set_bb_reg(dm, R_0xea4, MASKDWORD, 0x30201000); /*@ant map 1*/
++	odm_set_bb_reg(dm, R_0xea8, MASKDWORD, 0x70605040); /*@ant map 2*/
++	odm_set_bb_reg(dm, R_0xeac, BIT(9), 0); /*@keep antsel map by GNT_BT*/
++}
++
++void phydm_cumitek_smt_ant_init_8197f(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant *smtant_table = &dm->smtant_table;
++	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
++	u32 value32;
++
++	PHYDM_DBG(dm, DBG_SMT_ANT, "[8197F Cumitek SmtAnt Int]\n");
++
++	/*@GPIO setting*/
++}
++
++void phydm_cumitek_smt_ant_init_8192f(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant *smtant_table = &dm->smtant_table;
++	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
++	u32 value32;
++	PHYDM_DBG(dm, DBG_SMT_ANT, "[8192F Cumitek SmtAnt Int]\n");
++
++	/*@GPIO setting*/
++}
++
++void phydm_cumitek_smt_tx_ant_update(
++	void *dm_void,
++	u8 tx_ant_idx_path_a,
++	u8 tx_ant_idx_path_b,
++	u32 mac_id)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant *smtant_table = &dm->smtant_table;
++	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[Cumitek] Set TX-ANT[%d] = (( A:0x%x ,  B:0x%x ))\n", mac_id,
++		  tx_ant_idx_path_a, tx_ant_idx_path_b);
++
++	/*path-A*/
++	cumi_smtant_table->tx_ant_idx[0][mac_id] = tx_ant_idx_path_a; /*@fill this value into TXDESC*/
++
++	/*path-B*/
++	cumi_smtant_table->tx_ant_idx[1][mac_id] = tx_ant_idx_path_b; /*@fill this value into TXDESC*/
++}
++
++void phydm_cumitek_smt_rx_default_ant_update(
++	void *dm_void,
++	u8 rx_ant_idx_path_a,
++	u8 rx_ant_idx_path_b)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant *smtant_table = &dm->smtant_table;
++	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[Cumitek] Set RX-ANT = (( A:0x%x, B:0x%x ))\n",
++		  rx_ant_idx_path_a, rx_ant_idx_path_b);
++
++	/*path-A*/
++	if (cumi_smtant_table->rx_default_ant_idx[0] != rx_ant_idx_path_a) {
++		#if (RTL8822B_SUPPORT == 1)
++		if (dm->support_ic_type == ODM_RTL8822B) {
++			odm_set_bb_reg(dm, R_0xc08, BIT(21) | BIT(20) | BIT(19), rx_ant_idx_path_a); /*@default RX antenna*/
++			odm_set_mac_reg(dm, R_0x6d8, BIT(2) | BIT(1) | BIT(0), rx_ant_idx_path_a); /*@default response TX antenna*/
++		}
++		#endif
++
++		#if (RTL8197F_SUPPORT == 1)
++		if (dm->support_ic_type == ODM_RTL8197F) {
++		}
++		#endif
++
++		/*@jj add 20170822*/
++		#if (RTL8192F_SUPPORT == 1)
++		if (dm->support_ic_type == ODM_RTL8192F) {
++		}
++		#endif
++		cumi_smtant_table->rx_default_ant_idx[0] = rx_ant_idx_path_a;
++	}
++
++	/*path-B*/
++	if (cumi_smtant_table->rx_default_ant_idx[1] != rx_ant_idx_path_b) {
++		#if (RTL8822B_SUPPORT == 1)
++		if (dm->support_ic_type == ODM_RTL8822B) {
++			odm_set_bb_reg(dm, R_0xe08, BIT(21) | BIT(20) | BIT(19), rx_ant_idx_path_b); /*@default antenna*/
++			odm_set_mac_reg(dm, R_0x6d8, BIT(5) | BIT(4) | BIT(3), rx_ant_idx_path_b); /*@default response TX antenna*/
++		}
++		#endif
++
++		#if (RTL8197F_SUPPORT == 1)
++		if (dm->support_ic_type == ODM_RTL8197F) {
++		}
++		#endif
++
++		/*@jj add 20170822*/
++		#if (RTL8192F_SUPPORT == 1)
++		if (dm->support_ic_type == ODM_RTL8192F) {
++		}
++		#endif
++		cumi_smtant_table->rx_default_ant_idx[1] = rx_ant_idx_path_b;
++	}
++}
++
++void phydm_cumitek_smt_ant_debug(
++	void *dm_void,
++	char input[][16],
++	u32 *_used,
++	char *output,
++	u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant *smtant_table = &dm->smtant_table;
++	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	char help[] = "-h";
++	u32 dm_value[10] = {0};
++	u8 i;
++
++	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &dm_value[0]);
++
++	if (strcmp(input[1], help) == 0) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{1} {PathA rx_ant_idx} {pathB rx_ant_idx}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{2} {PathA tx_ant_idx} {pathB tx_ant_idx} {macid}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{3} {PathA mapping table} {PathB mapping table}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "{4} {txdesc_mode 0:3bit, 1:2bit}\n");
++
++	} else if (dm_value[0] == 1) { /*@fix rx_idle pattern*/
++
++		PHYDM_SSCANF(input[2], DCMD_DECIMAL, &dm_value[1]);
++		PHYDM_SSCANF(input[3], DCMD_DECIMAL, &dm_value[2]);
++
++		phydm_cumitek_smt_rx_default_ant_update(dm, (u8)dm_value[1], (u8)dm_value[2]);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "RX Ant{A, B}={%d, %d}\n", dm_value[1], dm_value[2]);
++
++	} else if (dm_value[0] == 2) { /*@fix tx pattern*/
++
++		for (i = 1; i < 4; i++) {
++			if (input[i + 1])
++				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
++		}
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "STA[%d] TX Ant{A, B}={%d, %d}\n", dm_value[3],
++			 dm_value[1], dm_value[2]);
++		phydm_cumitek_smt_tx_ant_update(dm, (u8)dm_value[1], (u8)dm_value[2], (u8)dm_value[3]);
++
++	} else if (dm_value[0] == 3) {
++		u8 table_path_a[8] = {0};
++		u8 table_path_b[8] = {0};
++
++		for (i = 1; i < 4; i++) {
++			if (input[i + 1])
++				PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
++		}
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Set Path-AB mapping table={%d, %d}\n", dm_value[1],
++			 dm_value[2]);
++
++		for (i = 0; i < 8; i++) {
++			table_path_a[i] = (u8)((dm_value[1] >> (4 * i)) & 0xf);
++			table_path_b[i] = (u8)((dm_value[2] >> (4 * i)) & 0xf);
++		}
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Ant_Table_A[7:0]={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x}\n",
++			 table_path_a[7], table_path_a[6], table_path_a[5],
++			 table_path_a[4], table_path_a[3], table_path_a[2],
++			 table_path_a[1], table_path_a[0]);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "Ant_Table_B[7:0]={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x}\n",
++			 table_path_b[7], table_path_b[6], table_path_b[5],
++			 table_path_b[4], table_path_b[3], table_path_b[2],
++			 table_path_b[1], table_path_b[0]);
++
++		phydm_cumitek_smt_ant_mapping_table_8822b(dm, &table_path_a[0], &table_path_b[0]);
++
++	} else if (dm_value[0] == 4) {
++		smtant_table->tx_desc_mode = (u8)dm_value[1];
++		odm_set_mac_reg(dm, R_0x604, BIT(25), (u32)smtant_table->tx_desc_mode);
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++
++#endif
++
++#if (defined(CONFIG_HL_SMART_ANTENNA))
++#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
++
++#if (RTL8822B_SUPPORT == 1)
++void phydm_hl_smart_ant_type2_init_8822b(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	u8 j;
++	u8 rfu_codeword_table_init_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] = {
++		{1, 1}, /*@0*/
++		{1, 2},
++		{2, 1},
++		{2, 2},
++		{4, 0},
++		{5, 0},
++		{6, 0},
++		{7, 0},
++		{8, 0}, /*@8*/
++		{9, 0},
++		{0xa, 0},
++		{0xb, 0},
++		{0xc, 0},
++		{0xd, 0},
++		{0xe, 0},
++		{0xf, 0}};
++	u8 rfu_codeword_table_init_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] = {
++#if 1
++		{9, 1}, /*@0*/
++		{9, 9},
++		{1, 9},
++		{9, 6},
++		{2, 1},
++		{2, 9},
++		{9, 2},
++		{2, 2}, /*@8*/
++		{6, 1},
++		{6, 9},
++		{2, 9},
++		{2, 2},
++		{6, 2},
++		{6, 6},
++		{2, 6},
++		{1, 1}
++#else
++		{1, 1}, /*@0*/
++		{9, 1},
++		{9, 9},
++		{1, 9},
++		{1, 2},
++		{9, 2},
++		{9, 6},
++		{1, 6},
++		{2, 1}, /*@8*/
++		{6, 1},
++		{6, 9},
++		{2, 9},
++		{2, 2},
++		{6, 2},
++		{6, 6},
++		{2, 6}
++#endif
++	};
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "***RTK 8822B SmartAnt_Init: Hong-Bo SmrtAnt Type2]\n");
++
++	/* @---------------------------------------- */
++	/* @GPIO 0-1 for Beam control */
++	/* reg0x66[2:0]=0 */
++	/* reg0x44[25:24] = 0 */
++	/* reg0x44[23:16]  enable_output for P_GPIO[7:0] */
++	/* reg0x44[15:8]  output_value for P_GPIO[7:0] */
++	/* reg0x40[1:0] = 0  GPIO function */
++	/* @------------------------------------------ */
++
++	odm_move_memory(dm, sat_tab->rfu_codeword_table_2g, rfu_codeword_table_init_2g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B));
++	odm_move_memory(dm, sat_tab->rfu_codeword_table_5g, rfu_codeword_table_init_5g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B));
++
++	/*@GPIO setting*/
++	odm_set_mac_reg(dm, R_0x64, (BIT(18) | BIT(17) | BIT(16)), 0);
++	odm_set_mac_reg(dm, R_0x44, BIT(25) | BIT(24), 0); /*@config P_GPIO[3:2] to data port*/
++	odm_set_mac_reg(dm, R_0x44, BIT(17) | BIT(16), 0x3); /*@enable_output for P_GPIO[3:2]*/
++#if 0
++	/*odm_set_mac_reg(dm, R_0x44, BIT(9)|BIT(8), 0);*/ /*P_GPIO[3:2] output value*/
++#endif
++	odm_set_mac_reg(dm, R_0x40, BIT(1) | BIT(0), 0); /*@GPIO function*/
++
++	/*@Hong_lin smart antenna HW setting*/
++	sat_tab->rfu_protocol_type = 2;
++	sat_tab->rfu_protocol_delay_time = 45;
++
++	sat_tab->rfu_codeword_total_bit_num = 16; /*@max=32bit*/
++	sat_tab->rfu_each_ant_bit_num = 4;
++
++	sat_tab->total_beam_set_num = 4;
++	sat_tab->total_beam_set_num_2g = 4;
++	sat_tab->total_beam_set_num_5g = 8;
++
++#if DEV_BUS_TYPE == RT_SDIO_INTERFACE
++	if (dm->support_interface == ODM_ITRF_SDIO)
++		sat_tab->latch_time = 100; /*@mu sec*/
++#endif
++#if DEV_BUS_TYPE == RT_USB_INTERFACE
++	if (dm->support_interface == ODM_ITRF_USB)
++		sat_tab->latch_time = 100; /*@mu sec*/
++#endif
++	sat_tab->pkt_skip_statistic_en = 0;
++
++	sat_tab->ant_num = 2;
++	sat_tab->ant_num_total = MAX_PATH_NUM_8822B;
++	sat_tab->first_train_ant = MAIN_ANT;
++
++	sat_tab->fix_beam_pattern_en = 0;
++	sat_tab->decision_holding_period = 0;
++
++	/*@beam training setting*/
++	sat_tab->pkt_counter = 0;
++	sat_tab->per_beam_training_pkt_num = 10;
++
++	/*set default beam*/
++	sat_tab->fast_training_beam_num = 0;
++	sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
++
++	for (j = 0; j < SUPPORT_BEAM_SET_PATTERN_NUM; j++) {
++		sat_tab->beam_set_avg_rssi_pre[j] = 0;
++		sat_tab->beam_set_train_val_diff[j] = 0;
++		sat_tab->beam_set_train_cnt[j] = 0;
++	}
++	phydm_set_rfu_beam_pattern_type2(dm);
++	fat_tab->fat_state = FAT_BEFORE_LINK_STATE;
++}
++#endif
++
++u32 phydm_construct_hb_rfu_codeword_type2(
++	void *dm_void,
++	u32 beam_set_idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++	u32 sync_codeword = 0x7f;
++	u32 codeword = 0;
++	u32 data_tmp = 0;
++	u32 i;
++
++	for (i = 0; i < sat_tab->ant_num_total; i++) {
++		if (*dm->band_type == ODM_BAND_5G)
++			data_tmp = sat_tab->rfu_codeword_table_5g[beam_set_idx][i];
++		else
++			data_tmp = sat_tab->rfu_codeword_table_2g[beam_set_idx][i];
++
++		codeword |= (data_tmp << (i * sat_tab->rfu_each_ant_bit_num));
++	}
++
++	codeword = (codeword << 8) | sync_codeword;
++
++	return codeword;
++}
++
++void phydm_update_beam_pattern_type2(
++	void *dm_void,
++	u32 codeword,
++	u32 codeword_length)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++	u8 i;
++	boolean beam_ctrl_signal;
++	u32 one = 0x1;
++	u32 reg44_tmp_p, reg44_tmp_n, reg44_ori;
++	u8 devide_num = 4;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "Set codeword = ((0x%x))\n", codeword);
++
++	reg44_ori = odm_get_mac_reg(dm, R_0x44, MASKDWORD);
++	reg44_tmp_p = reg44_ori;
++#if 0
++	/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_ori =0x%x\n", reg44_ori);*/
++#endif
++
++	/*@devide_num = (sat_tab->rfu_protocol_type == 2) ? 8 : 4;*/
++
++	for (i = 0; i <= (codeword_length - 1); i++) {
++		beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i);
++
++		#if 1
++		if (dm->debug_components & DBG_ANT_DIV) {
++			if (i == (codeword_length - 1))
++				pr_debug("%d ]\n", beam_ctrl_signal);
++			else if (i == 0)
++				pr_debug("Start sending codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal);
++			else if ((i % devide_num) == (devide_num - 1))
++				pr_debug("%d  |  ", beam_ctrl_signal);
++			else
++				pr_debug("%d ", beam_ctrl_signal);
++		}
++		#endif
++
++		if (dm->support_ic_type == ODM_RTL8821) {
++			#if (RTL8821A_SUPPORT == 1)
++			reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT(10))); /*@clean bit 10 & 11*/
++			reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10));
++			reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10)));
++
++#if 0
++			/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n);*/
++#endif
++			odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
++			odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n);
++			#endif
++		}
++		#if (RTL8822B_SUPPORT == 1)
++		else if (dm->support_ic_type == ODM_RTL8822B) {
++			if (sat_tab->rfu_protocol_type == 2) {
++				reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*@clean bit 8*/
++				reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*@get new clk high/low, exclusive-or*/
++
++				reg44_tmp_p |= (beam_ctrl_signal << 8);
++
++				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
++				ODM_delay_us(sat_tab->rfu_protocol_delay_time);
++#if 0
++				/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal);*/
++#endif
++
++			} else {
++				reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT(8))); /*@clean bit 9 & 8*/
++				reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8));
++				reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8)));
++
++#if 0
++				/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n); */
++#endif
++				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
++				ODM_delay_us(10);
++				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n);
++				ODM_delay_us(10);
++			}
++		}
++		#endif
++	}
++}
++
++void phydm_update_rx_idle_beam_type2(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++	u32 i;
++
++	sat_tab->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(dm, sat_tab->rx_idle_beam_set_idx);
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[ Update Rx-Idle-Beam ] BeamSet idx = ((%d))\n",
++		  sat_tab->rx_idle_beam_set_idx);
++
++#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++	if (dm->support_interface == ODM_ITRF_PCIE)
++		phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
++#endif
++#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
++	if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
++		odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
++#if 0
++	/*odm_stall_execution(1);*/
++#endif
++#endif
++
++	sat_tab->pre_codeword = sat_tab->update_beam_codeword;
++}
++
++void phydm_hl_smt_ant_dbg_type2(
++	void *dm_void,
++	char input[][16],
++	u32 *_used,
++	char *output,
++	u32 *_out_len
++)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 one = 0x1;
++	u32 codeword_length = sat_tab->rfu_codeword_total_bit_num;
++	u32 beam_ctrl_signal, i;
++	u8 devide_num = 4;
++	char help[] = "-h";
++	u32 dm_value[10] = {0};
++
++	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &dm_value[0]);
++	PHYDM_SSCANF(input[2], DCMD_DECIMAL, &dm_value[1]);
++	PHYDM_SSCANF(input[3], DCMD_DECIMAL, &dm_value[2]);
++	PHYDM_SSCANF(input[4], DCMD_DECIMAL, &dm_value[3]);
++	PHYDM_SSCANF(input[5], DCMD_DECIMAL, &dm_value[4]);
++
++	if (strcmp(input[1], help) == 0) {
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 " 1 {fix_en} {codeword(Hex)}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 " 3 {Fix_training_num_en} {Per_beam_training_pkt_num} {Decision_holding_period}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 " 5 {0:show, 1:2G, 2:5G} {beam_num} {idxA(Hex)} {idxB(Hex)}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 " 7 {0:show, 1:2G, 2:5G} {total_beam_set_num}\n");
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 " 8 {0:show, 1:set} {RFU delay time(us)}\n");
++
++	} else if (dm_value[0] == 1) { /*@fix beam pattern*/
++
++		sat_tab->fix_beam_pattern_en = dm_value[1];
++
++		if (sat_tab->fix_beam_pattern_en == 1) {
++			PHYDM_SSCANF(input[3], DCMD_HEX, &dm_value[2]);
++			sat_tab->fix_beam_pattern_codeword = dm_value[2];
++
++			if (sat_tab->fix_beam_pattern_codeword > (one << codeword_length)) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n",
++					  sat_tab->fix_beam_pattern_codeword,
++					  codeword_length);
++
++				(sat_tab->fix_beam_pattern_codeword) &= 0xffffff;
++
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "[ SmartAnt ] Auto modify to (0x%x)\n",
++					  sat_tab->fix_beam_pattern_codeword);
++			}
++
++			sat_tab->update_beam_codeword = sat_tab->fix_beam_pattern_codeword;
++
++			/*@---------------------------------------------------------*/
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "Fix Beam Pattern\n");
++
++			/*@devide_num = (sat_tab->rfu_protocol_type == 2) ? 8 : 4;*/
++
++			for (i = 0; i <= (codeword_length - 1); i++) {
++				beam_ctrl_signal = (boolean)((sat_tab->update_beam_codeword & BIT(i)) >> i);
++
++				if (i == (codeword_length - 1))
++					PDM_SNPF(out_len, used,
++						 output + used,
++						 out_len - used,
++						 "%d]\n",
++						 beam_ctrl_signal);
++				else if (i == 0)
++					PDM_SNPF(out_len, used,
++						 output + used,
++						 out_len - used,
++						 "Send Codeword[1:%d] to RFU -> [%d",
++						 sat_tab->rfu_codeword_total_bit_num,
++						 beam_ctrl_signal);
++				else if ((i % devide_num) == (devide_num - 1))
++					PDM_SNPF(out_len, used,
++						 output + used,
++						 out_len - used, "%d|",
++						 beam_ctrl_signal);
++				else
++					PDM_SNPF(out_len, used,
++						 output + used,
++						 out_len - used, "%d",
++						 beam_ctrl_signal);
++			}
++/*@---------------------------------------------------------*/
++
++#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++			if (dm->support_interface == ODM_ITRF_PCIE)
++				phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
++#endif
++#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
++			if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
++			odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
++#if 0
++			/*odm_stall_execution(1);*/
++#endif
++#endif
++		} else if (sat_tab->fix_beam_pattern_en == 0)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[ SmartAnt ] Smart Antenna: Enable\n");
++
++	} else if (dm_value[0] == 2) { /*set latch time*/
++
++		sat_tab->latch_time = dm_value[1];
++		PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ]  latch_time =0x%x\n",
++			  sat_tab->latch_time);
++	} else if (dm_value[0] == 3) {
++		sat_tab->fix_training_num_en = dm_value[1];
++
++		if (sat_tab->fix_training_num_en == 1) {
++			sat_tab->per_beam_training_pkt_num = (u8)dm_value[2];
++			sat_tab->decision_holding_period = (u8)dm_value[3];
++
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[SmtAnt] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n",
++				 sat_tab->fix_training_num_en,
++				 sat_tab->per_beam_training_pkt_num,
++				 sat_tab->decision_holding_period);
++
++		} else if (sat_tab->fix_training_num_en == 0) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[ SmartAnt ]  AUTO per_beam_training_pkt_num\n");
++		}
++	} else if (dm_value[0] == 4) {
++		#if 0
++		if (dm_value[1] == 1) {
++			sat_tab->ant_num = 1;
++			sat_tab->first_train_ant = MAIN_ANT;
++
++		} else if (dm_value[1] == 2) {
++			sat_tab->ant_num = 1;
++			sat_tab->first_train_ant = AUX_ANT;
++
++		} else if (dm_value[1] == 3) {
++			sat_tab->ant_num = 2;
++			sat_tab->first_train_ant = MAIN_ANT;
++		}
++
++		PDM_SNPF((output + used, out_len - used,
++			 "[ SmartAnt ]  Set ant Num = (( %d )), first_train_ant = (( %d ))\n",
++			 sat_tab->ant_num, (sat_tab->first_train_ant - 1)));
++		#endif
++	} else if (dm_value[0] == 5) { /*set beam set table*/
++
++		PHYDM_SSCANF(input[4], DCMD_HEX, &dm_value[3]);
++		PHYDM_SSCANF(input[5], DCMD_HEX, &dm_value[4]);
++
++		if (dm_value[1] == 1) { /*@2G*/
++			if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) {
++				sat_tab->rfu_codeword_table_2g[dm_value[2]][0] = (u8)dm_value[3];
++				sat_tab->rfu_codeword_table_2g[dm_value[2]][1] = (u8)dm_value[4];
++				PDM_SNPF(out_len, used, output + used,
++					 out_len - used,
++					 "[SmtAnt] Set 2G Table[%d] = [A:0x%x, B:0x%x]\n",
++					 dm_value[2], dm_value[3], dm_value[4]);
++			}
++
++		} else if (dm_value[1] == 2) { /*@5G*/
++			if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) {
++				sat_tab->rfu_codeword_table_5g[dm_value[2]][0] = (u8)dm_value[3];
++				sat_tab->rfu_codeword_table_5g[dm_value[2]][1] = (u8)dm_value[4];
++				PDM_SNPF(out_len, used, output + used,
++					 out_len - used,
++					 "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n",
++					 dm_value[2], dm_value[3], dm_value[4]);
++			}
++		} else if (dm_value[1] == 0) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[SmtAnt] 2G Beam Table==============>\n");
++			for (i = 0; i < sat_tab->total_beam_set_num_2g; i++) {
++				PDM_SNPF(out_len, used, output + used,
++					 out_len - used,
++					 "2G Table[%d] = [A:0x%x, B:0x%x]\n", i,
++					 sat_tab->rfu_codeword_table_2g[i][0],
++					 sat_tab->rfu_codeword_table_2g[i][1]);
++			}
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[SmtAnt] 5G Beam Table==============>\n");
++			for (i = 0; i < sat_tab->total_beam_set_num_5g; i++) {
++				PDM_SNPF(out_len, used, output + used,
++					 out_len - used,
++					 "5G Table[%d] = [A:0x%x, B:0x%x]\n", i,
++					 sat_tab->rfu_codeword_table_5g[i][0],
++					 sat_tab->rfu_codeword_table_5g[i][1]);
++			}
++		}
++
++	} else if (dm_value[0] == 6) {
++#if 0
++		if (dm_value[1] == 0) {
++			if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) {
++				sat_tab->rfu_codeword_table_5g[dm_value[2] ][0] = (u8)dm_value[3];
++				sat_tab->rfu_codeword_table_5g[dm_value[2] ][1] = (u8)dm_value[4];
++				PDM_SNPF((output + used, out_len - used,
++					 "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n",
++					 dm_value[2], dm_value[3],
++					 dm_value[4]));
++			}
++		} else {
++			for (i = 0; i < sat_tab->total_beam_set_num_5g; i++) {
++				PDM_SNPF((output + used, out_len - used,
++					 "[SmtAnt] Read 5G Table[%d] = [A:0x%x, B:0x%x]\n",
++					 i,
++					 sat_tab->rfu_codeword_table_5g[i][0],
++					 sat_tab->rfu_codeword_table_5g[i][1]));
++			}
++		}
++#endif
++	} else if (dm_value[0] == 7) {
++		if (dm_value[1] == 1) {
++			sat_tab->total_beam_set_num_2g = (u8)(dm_value[2]);
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[ SmartAnt ] total_beam_set_num_2g = ((%d))\n",
++				 sat_tab->total_beam_set_num_2g);
++
++		} else if (dm_value[1] == 2) {
++			sat_tab->total_beam_set_num_5g = (u8)(dm_value[2]);
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[ SmartAnt ] total_beam_set_num_5g = ((%d))\n",
++				 sat_tab->total_beam_set_num_5g);
++		} else if (dm_value[1] == 0) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[ SmartAnt ] Show total_beam_set_num{2g,5g} = {%d,%d}\n",
++				 sat_tab->total_beam_set_num_2g,
++				 sat_tab->total_beam_set_num_5g);
++		}
++
++	} else if (dm_value[0] == 8) {
++		if (dm_value[1] == 1) {
++			sat_tab->rfu_protocol_delay_time = (u16)(dm_value[2]);
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[SmtAnt] Set rfu_protocol_delay_time = ((%d))\n",
++				 sat_tab->rfu_protocol_delay_time);
++		} else if (dm_value[1] == 0) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[SmtAnt] Read rfu_protocol_delay_time = ((%d))\n",
++				 sat_tab->rfu_protocol_delay_time);
++		}
++	}
++
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_set_rfu_beam_pattern_type2(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++
++	if (dm->ant_div_type != HL_SW_SMART_ANT_TYPE2)
++		return;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "Training beam_set index = (( 0x%x ))\n",
++		  sat_tab->fast_training_beam_num);
++	sat_tab->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(dm, sat_tab->fast_training_beam_num);
++
++	#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++	if (dm->support_interface == ODM_ITRF_PCIE)
++		phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
++	#endif
++	#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
++	if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
++		odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
++#if 0
++	/*odm_stall_execution(1);*/
++#endif
++	#endif
++}
++
++void phydm_fast_ant_training_hl_smart_antenna_type2(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
++	u32 codeword = 0;
++	u8 i = 0, j = 0;
++	u8 avg_rssi_tmp;
++	u8 avg_rssi_tmp_ma;
++	u8 max_beam_ant_rssi = 0;
++	u8 rssi_target_beam = 0, target_beam_max_rssi = 0;
++	u8 evm1ss_target_beam = 0, evm2ss_target_beam = 0;
++	u32 target_beam_max_evm1ss = 0, target_beam_max_evm2ss = 0;
++	u32 beam_tmp;
++	u8 per_beam_val_diff_tmp = 0, training_pkt_num_offset;
++	u32 avg_evm2ss[2] = {0}, avg_evm2ss_sum = 0;
++	u32 avg_evm1ss = 0;
++	u32 beam_path_evm_2ss_cnt_all = 0; /*sum of all 2SS-pattern cnt*/
++	u32 beam_path_evm_1ss_cnt_all = 0; /*sum of all 1SS-pattern cnt*/
++	u8 decision_type;
++
++	if (!dm->is_linked) {
++		PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
++
++		if (fat_tab->is_become_linked == true) {
++			sat_tab->decision_holding_period = 0;
++			PHYDM_DBG(dm, DBG_ANT_DIV, "Link->no Link\n");
++			fat_tab->fat_state = FAT_BEFORE_LINK_STATE;
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "change to (( %d )) FAT_state\n",
++				  fat_tab->fat_state);
++			fat_tab->is_become_linked = dm->is_linked;
++		}
++		return;
++
++	} else {
++		if (fat_tab->is_become_linked == false) {
++			PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
++
++			fat_tab->fat_state = FAT_PREPARE_STATE;
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "change to (( %d )) FAT_state\n",
++				  fat_tab->fat_state);
++
++			/*sat_tab->fast_training_beam_num = 0;*/
++			/*phydm_set_rfu_beam_pattern_type2(dm);*/
++
++			fat_tab->is_become_linked = dm->is_linked;
++		}
++	}
++
++#if 0
++	/*PHYDM_DBG(dm, DBG_ANT_DIV, "HL Smart ant Training: state (( %d ))\n", fat_tab->fat_state);*/
++#endif
++
++	/* @[DECISION STATE] */
++	/*@=======================================================================================*/
++	if (fat_tab->fat_state == FAT_DECISION_STATE) {
++		PHYDM_DBG(dm, DBG_ANT_DIV, "[ 3. In Decision state]\n");
++
++		/*@compute target beam in each antenna*/
++
++		for (j = 0; j < (sat_tab->total_beam_set_num); j++) {
++			/*@[Decision1: RSSI]-------------------------------------------------------------------*/
++			if (sat_tab->statistic_pkt_cnt[j] == 0) { /*@if new RSSI = 0 -> MA_RSSI-=2*/
++				avg_rssi_tmp = sat_tab->beam_set_avg_rssi_pre[j];
++				avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp;
++				avg_rssi_tmp_ma = avg_rssi_tmp;
++			} else {
++				avg_rssi_tmp = (u8)((sat_tab->beam_set_rssi_avg_sum[j]) / (sat_tab->statistic_pkt_cnt[j]));
++				avg_rssi_tmp_ma = (avg_rssi_tmp + sat_tab->beam_set_avg_rssi_pre[j]) >> 1;
++			}
++
++			sat_tab->beam_set_avg_rssi_pre[j] = avg_rssi_tmp;
++
++			if (avg_rssi_tmp > target_beam_max_rssi) {
++				rssi_target_beam = j;
++				target_beam_max_rssi = avg_rssi_tmp;
++			}
++
++			/*@[Decision2: EVM 2ss]-------------------------------------------------------------------*/
++			if (sat_tab->beam_path_evm_2ss_cnt[j] != 0) {
++				avg_evm2ss[0] = sat_tab->beam_path_evm_2ss_sum[j][0] / sat_tab->beam_path_evm_2ss_cnt[j];
++				avg_evm2ss[1] = sat_tab->beam_path_evm_2ss_sum[j][1] / sat_tab->beam_path_evm_2ss_cnt[j];
++				avg_evm2ss_sum = avg_evm2ss[0] + avg_evm2ss[1];
++				beam_path_evm_2ss_cnt_all += sat_tab->beam_path_evm_2ss_cnt[j];
++
++				sat_tab->beam_set_avg_evm_2ss_pre[j] = (u8)avg_evm2ss_sum;
++			}
++
++			if (avg_evm2ss_sum > target_beam_max_evm2ss) {
++				evm2ss_target_beam = j;
++				target_beam_max_evm2ss = avg_evm2ss_sum;
++			}
++
++			/*@[Decision3: EVM 1ss]-------------------------------------------------------------------*/
++			if (sat_tab->beam_path_evm_1ss_cnt[j] != 0) {
++				avg_evm1ss = sat_tab->beam_path_evm_1ss_sum[j] / sat_tab->beam_path_evm_1ss_cnt[j];
++				beam_path_evm_1ss_cnt_all += sat_tab->beam_path_evm_1ss_cnt[j];
++
++				sat_tab->beam_set_avg_evm_1ss_pre[j] = (u8)avg_evm1ss;
++			}
++
++			if (avg_evm1ss > target_beam_max_evm1ss) {
++				evm1ss_target_beam = j;
++				target_beam_max_evm1ss = avg_evm1ss;
++			}
++
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "Beam[%d] Pkt_cnt=(( %d )), avg{MA,rssi}={%d, %d}, EVM1={%d}, EVM2={%d, %d, %d}\n",
++				  j, sat_tab->statistic_pkt_cnt[j],
++				  avg_rssi_tmp_ma, avg_rssi_tmp, avg_evm1ss,
++				  avg_evm2ss[0], avg_evm2ss[1], avg_evm2ss_sum);
++
++			/*reset counter value*/
++			sat_tab->beam_set_rssi_avg_sum[j] = 0;
++			sat_tab->beam_path_rssi_sum[j][0] = 0;
++			sat_tab->beam_path_rssi_sum[j][1] = 0;
++			sat_tab->statistic_pkt_cnt[j] = 0;
++
++			sat_tab->beam_path_evm_2ss_sum[j][0] = 0;
++			sat_tab->beam_path_evm_2ss_sum[j][1] = 0;
++			sat_tab->beam_path_evm_2ss_cnt[j] = 0;
++
++			sat_tab->beam_path_evm_1ss_sum[j] = 0;
++			sat_tab->beam_path_evm_1ss_cnt[j] = 0;
++		}
++
++		/*@[Joint Decision]-------------------------------------------------------------------*/
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "--->1.[RSSI]      Target Beam(( %d )) RSSI_max=((%d))\n",
++			  rssi_target_beam, target_beam_max_rssi);
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "--->2.[Evm2SS] Target Beam(( %d )) EVM2SS_max=((%d))\n",
++			  evm2ss_target_beam, target_beam_max_evm2ss);
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "--->3.[Evm1SS] Target Beam(( %d )) EVM1SS_max=((%d))\n",
++			  evm1ss_target_beam, target_beam_max_evm1ss);
++
++		if (target_beam_max_rssi <= 10) {
++			sat_tab->rx_idle_beam_set_idx = rssi_target_beam;
++			decision_type = 1;
++		} else {
++			if (beam_path_evm_2ss_cnt_all != 0) {
++				sat_tab->rx_idle_beam_set_idx = evm2ss_target_beam;
++				decision_type = 2;
++			} else if (beam_path_evm_1ss_cnt_all != 0) {
++				sat_tab->rx_idle_beam_set_idx = evm1ss_target_beam;
++				decision_type = 3;
++			} else {
++				sat_tab->rx_idle_beam_set_idx = rssi_target_beam;
++				decision_type = 1;
++			}
++		}
++
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "---> Decision_type=((%d)), Final Target Beam(( %d ))\n",
++			  decision_type, sat_tab->rx_idle_beam_set_idx);
++
++		/*@Calculate packet counter offset*/
++		for (j = 0; j < (sat_tab->total_beam_set_num); j++) {
++			if (decision_type == 1) {
++				per_beam_val_diff_tmp = target_beam_max_rssi - sat_tab->beam_set_avg_rssi_pre[j];
++
++			} else if (decision_type == 2) {
++				per_beam_val_diff_tmp = ((u8)target_beam_max_evm2ss - sat_tab->beam_set_avg_evm_2ss_pre[j]) >> 1;
++			} else if (decision_type == 3) {
++				per_beam_val_diff_tmp = (u8)target_beam_max_evm1ss - sat_tab->beam_set_avg_evm_1ss_pre[j];
++			}
++			sat_tab->beam_set_train_val_diff[j] = per_beam_val_diff_tmp;
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "Beam_Set[%d]: diff= ((%d))\n", j,
++				  per_beam_val_diff_tmp);
++		}
++
++		/*set beam in each antenna*/
++		phydm_update_rx_idle_beam_type2(dm);
++		fat_tab->fat_state = FAT_PREPARE_STATE;
++	}
++	/* @[TRAINING STATE] */
++	else if (fat_tab->fat_state == FAT_TRAINING_STATE) {
++		PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2. In Training state]\n");
++
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "curr_beam_idx = (( %d )), pre_beam_idx = (( %d ))\n",
++			  sat_tab->fast_training_beam_num,
++			  sat_tab->pre_fast_training_beam_num);
++
++		if (sat_tab->fast_training_beam_num > sat_tab->pre_fast_training_beam_num)
++
++			sat_tab->force_update_beam_en = 0;
++
++		else {
++			sat_tab->force_update_beam_en = 1;
++
++			sat_tab->pkt_counter = 0;
++			beam_tmp = sat_tab->fast_training_beam_num;
++			if (sat_tab->fast_training_beam_num >= ((u32)sat_tab->total_beam_set_num - 1)) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "[Timeout Update]  Beam_num (( %d )) -> (( decision ))\n",
++					  sat_tab->fast_training_beam_num);
++				fat_tab->fat_state = FAT_DECISION_STATE;
++				phydm_fast_ant_training_hl_smart_antenna_type2(dm);
++
++			} else {
++				sat_tab->fast_training_beam_num++;
++
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "[Timeout Update]  Beam_num (( %d )) -> (( %d ))\n",
++					  beam_tmp,
++					  sat_tab->fast_training_beam_num);
++				phydm_set_rfu_beam_pattern_type2(dm);
++				fat_tab->fat_state = FAT_TRAINING_STATE;
++			}
++		}
++		sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
++		PHYDM_DBG(dm, DBG_ANT_DIV, "Update Pre_Beam =(( %d ))\n",
++			  sat_tab->pre_fast_training_beam_num);
++	}
++	/*  @[Prepare state] */
++	/*@=======================================================================================*/
++	else if (fat_tab->fat_state == FAT_PREPARE_STATE) {
++		PHYDM_DBG(dm, DBG_ANT_DIV, "\n\n[ 1. In Prepare state]\n");
++
++		if (dm->pre_traffic_load == dm->traffic_load) {
++			if (sat_tab->decision_holding_period != 0) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "Holding_period = (( %d )), return!!!\n",
++					  sat_tab->decision_holding_period);
++				sat_tab->decision_holding_period--;
++				return;
++			}
++		}
++
++		/* Set training packet number*/
++		if (sat_tab->fix_training_num_en == 0) {
++			switch (dm->traffic_load) {
++			case TRAFFIC_HIGH:
++				sat_tab->per_beam_training_pkt_num = 8;
++				sat_tab->decision_holding_period = 2;
++				break;
++			case TRAFFIC_MID:
++				sat_tab->per_beam_training_pkt_num = 6;
++				sat_tab->decision_holding_period = 3;
++				break;
++			case TRAFFIC_LOW:
++				sat_tab->per_beam_training_pkt_num = 3; /*ping 60000*/
++				sat_tab->decision_holding_period = 4;
++				break;
++			case TRAFFIC_ULTRA_LOW:
++				sat_tab->per_beam_training_pkt_num = 1;
++				sat_tab->decision_holding_period = 6;
++				break;
++			default:
++				break;
++			}
++		}
++
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "TrafficLoad = (( %d )), Fix_beam = (( %d )), per_beam_training_pkt_num = (( %d )), decision_holding_period = ((%d))\n",
++			  dm->traffic_load, sat_tab->fix_training_num_en,
++			  sat_tab->per_beam_training_pkt_num,
++			  sat_tab->decision_holding_period);
++
++		/*@Beam_set number*/
++		if (*dm->band_type == ODM_BAND_5G) {
++			sat_tab->total_beam_set_num = sat_tab->total_beam_set_num_5g;
++			PHYDM_DBG(dm, DBG_ANT_DIV, "5G beam_set num = ((%d))\n",
++				  sat_tab->total_beam_set_num);
++		} else {
++			sat_tab->total_beam_set_num = sat_tab->total_beam_set_num_2g;
++			PHYDM_DBG(dm, DBG_ANT_DIV, "2G beam_set num = ((%d))\n",
++				  sat_tab->total_beam_set_num);
++		}
++
++		for (j = 0; j < (sat_tab->total_beam_set_num); j++) {
++			training_pkt_num_offset = sat_tab->beam_set_train_val_diff[j];
++
++			if (sat_tab->per_beam_training_pkt_num > training_pkt_num_offset)
++				sat_tab->beam_set_train_cnt[j] = sat_tab->per_beam_training_pkt_num - training_pkt_num_offset;
++			else
++				sat_tab->beam_set_train_cnt[j] = 1;
++
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "Beam_Set[ %d ] training_pkt_offset = ((%d)), training_pkt_num = ((%d))\n",
++				  j, sat_tab->beam_set_train_val_diff[j],
++				  sat_tab->beam_set_train_cnt[j]);
++		}
++
++		sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
++		sat_tab->update_beam_idx = 0;
++		sat_tab->pkt_counter = 0;
++
++		sat_tab->fast_training_beam_num = 0;
++		phydm_set_rfu_beam_pattern_type2(dm);
++		sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
++		fat_tab->fat_state = FAT_TRAINING_STATE;
++	}
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++
++void phydm_beam_switch_workitem_callback(
++	void *context)
++{
++	void *adapter = (void *)context;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++
++#if DEV_BUS_TYPE != RT_PCI_INTERFACE
++	sat_tab->pkt_skip_statistic_en = 1;
++#endif
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n",
++		  sat_tab->pkt_skip_statistic_en);
++
++	phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
++
++#if DEV_BUS_TYPE != RT_PCI_INTERFACE
++#if 0
++	/*odm_stall_execution(sat_tab->latch_time);*/
++#endif
++	sat_tab->pkt_skip_statistic_en = 0;
++#endif
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n",
++		  sat_tab->pkt_skip_statistic_en, sat_tab->latch_time);
++}
++
++void phydm_beam_decision_workitem_callback(
++	void *context)
++{
++	void *adapter = (void *)context;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[ SmartAnt ] Beam decision Workitem Callback\n");
++	phydm_fast_ant_training_hl_smart_antenna_type2(dm);
++}
++#endif
++
++void phydm_process_rssi_for_hb_smtant_type2(
++	void *dm_void,
++	void *phy_info_void,
++	void *pkt_info_void,
++	u8 rssi_avg)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
++	struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++	u8 train_pkt_number;
++	u32 beam_tmp;
++	u8 rx_power_ant0 = phy_info->rx_mimo_signal_strength[0];
++	u8 rx_power_ant1 = phy_info->rx_mimo_signal_strength[1];
++	u8 rx_evm_ant0 = phy_info->rx_mimo_evm_dbm[0];
++	u8 rx_evm_ant1 = phy_info->rx_mimo_evm_dbm[1];
++
++	/*@[Beacon]*/
++	if (pktinfo->is_packet_beacon) {
++		sat_tab->beacon_counter++;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "MatchBSSID_beacon_counter = ((%d))\n",
++			  sat_tab->beacon_counter);
++
++		if (sat_tab->beacon_counter >= sat_tab->pre_beacon_counter + 2) {
++			sat_tab->update_beam_idx++;
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n",
++				  sat_tab->pre_beacon_counter,
++				  sat_tab->pkt_counter,
++				  sat_tab->update_beam_idx);
++
++			sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
++			sat_tab->pkt_counter = 0;
++		}
++	}
++	/*@[data]*/
++	else if (pktinfo->is_packet_to_self) {
++		if (sat_tab->pkt_skip_statistic_en == 0) {
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "ID[%d] pkt_cnt=((%d)): Beam_set = ((%d)), RSSI{A,B,avg} = {%d, %d, %d}\n",
++				  pktinfo->station_id, sat_tab->pkt_counter,
++				  sat_tab->fast_training_beam_num,
++				  rx_power_ant0, rx_power_ant1, rssi_avg);
++
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "Rate_ss = ((%d)), EVM{A,B} = {%d, %d}, RX Rate =",
++				  pktinfo->rate_ss, rx_evm_ant0, rx_evm_ant1);
++			phydm_print_rate(dm, dm->rx_rate, DBG_ANT_DIV);
++
++			if (sat_tab->pkt_counter >= 1) /*packet skip count*/
++			{
++				sat_tab->beam_set_rssi_avg_sum[sat_tab->fast_training_beam_num] += rssi_avg;
++				sat_tab->statistic_pkt_cnt[sat_tab->fast_training_beam_num]++;
++
++				sat_tab->beam_path_rssi_sum[sat_tab->fast_training_beam_num][0] += rx_power_ant0;
++				sat_tab->beam_path_rssi_sum[sat_tab->fast_training_beam_num][1] += rx_power_ant1;
++
++				if (pktinfo->rate_ss == 2) {
++					sat_tab->beam_path_evm_2ss_sum[sat_tab->fast_training_beam_num][0] += rx_evm_ant0;
++					sat_tab->beam_path_evm_2ss_sum[sat_tab->fast_training_beam_num][1] += rx_evm_ant1;
++					sat_tab->beam_path_evm_2ss_cnt[sat_tab->fast_training_beam_num]++;
++				} else {
++					sat_tab->beam_path_evm_1ss_sum[sat_tab->fast_training_beam_num] += rx_evm_ant0;
++					sat_tab->beam_path_evm_1ss_cnt[sat_tab->fast_training_beam_num]++;
++				}
++			}
++
++			sat_tab->pkt_counter++;
++
++			train_pkt_number = sat_tab->beam_set_train_cnt[sat_tab->fast_training_beam_num];
++
++			if (sat_tab->pkt_counter >= train_pkt_number) {
++				sat_tab->update_beam_idx++;
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "pre_beacon_counter = ((%d)), Update_new_beam = ((%d))\n",
++					  sat_tab->pre_beacon_counter,
++					  sat_tab->update_beam_idx);
++
++				sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
++				sat_tab->pkt_counter = 0;
++			}
++		}
++	}
++
++	if (sat_tab->update_beam_idx > 0) {
++		sat_tab->update_beam_idx = 0;
++
++		if (sat_tab->fast_training_beam_num >= ((u32)sat_tab->total_beam_set_num - 1)) {
++			fat_tab->fat_state = FAT_DECISION_STATE;
++
++			#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++			if (dm->support_interface == ODM_ITRF_PCIE)
++				phydm_fast_ant_training_hl_smart_antenna_type2(dm); /*@go to make decision*/
++			#endif
++			#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
++			if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
++				odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);
++			#endif
++
++		} else {
++			beam_tmp = sat_tab->fast_training_beam_num;
++			sat_tab->fast_training_beam_num++;
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "Update Beam_num (( %d )) -> (( %d ))\n",
++				  beam_tmp, sat_tab->fast_training_beam_num);
++			phydm_set_rfu_beam_pattern_type2(dm);
++			sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
++
++			fat_tab->fat_state = FAT_TRAINING_STATE;
++		}
++	}
++}
++#endif
++
++#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))
++
++void phydm_hl_smart_ant_type1_init_8821a(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	u32 value32;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "***8821A SmartAnt_Init => ant_div_type=[Hong-Lin Smart ant Type1]\n");
++
++#if 0
++	/* @---------------------------------------- */
++	/* @GPIO 2-3 for Beam control */
++	/* reg0x66[2]=0 */
++	/* reg0x44[27:26] = 0 */
++	/* reg0x44[23:16]  enable_output for P_GPIO[7:0] */
++	/* reg0x44[15:8]  output_value for P_GPIO[7:0] */
++	/* reg0x40[1:0] = 0  GPIO function */
++	/* @------------------------------------------ */
++#endif
++
++	/*@GPIO setting*/
++	odm_set_mac_reg(dm, R_0x64, BIT(18), 0);
++	odm_set_mac_reg(dm, R_0x44, BIT(27) | BIT(26), 0);
++	odm_set_mac_reg(dm, R_0x44, BIT(19) | BIT(18), 0x3); /*@enable_output for P_GPIO[3:2]*/
++#if 0
++	/*odm_set_mac_reg(dm, R_0x44, BIT(11)|BIT(10), 0);*/ /*output value*/
++#endif
++	odm_set_mac_reg(dm, R_0x40, BIT(1) | BIT(0), 0); /*@GPIO function*/
++
++	/*@Hong_lin smart antenna HW setting*/
++	sat_tab->rfu_codeword_total_bit_num = 24; /*@max=32*/
++	sat_tab->rfu_each_ant_bit_num = 4;
++	sat_tab->beam_patten_num_each_ant = 4;
++
++#if DEV_BUS_TYPE == RT_SDIO_INTERFACE
++	sat_tab->latch_time = 100; /*@mu sec*/
++#elif DEV_BUS_TYPE == RT_USB_INTERFACE
++	sat_tab->latch_time = 100; /*@mu sec*/
++#endif
++	sat_tab->pkt_skip_statistic_en = 0;
++
++	sat_tab->ant_num = 1; /*@max=8*/
++	sat_tab->ant_num_total = NUM_ANTENNA_8821A;
++	sat_tab->first_train_ant = MAIN_ANT;
++
++	sat_tab->rfu_codeword_table[0] = 0x0;
++	sat_tab->rfu_codeword_table[1] = 0x4;
++	sat_tab->rfu_codeword_table[2] = 0x8;
++	sat_tab->rfu_codeword_table[3] = 0xc;
++
++	sat_tab->rfu_codeword_table_5g[0] = 0x1;
++	sat_tab->rfu_codeword_table_5g[1] = 0x2;
++	sat_tab->rfu_codeword_table_5g[2] = 0x4;
++	sat_tab->rfu_codeword_table_5g[3] = 0x8;
++
++	sat_tab->fix_beam_pattern_en = 0;
++	sat_tab->decision_holding_period = 0;
++
++	/*@beam training setting*/
++	sat_tab->pkt_counter = 0;
++	sat_tab->per_beam_training_pkt_num = 10;
++
++	/*set default beam*/
++	sat_tab->fast_training_beam_num = 0;
++	sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
++	phydm_set_all_ant_same_beam_num(dm);
++
++	fat_tab->fat_state = FAT_BEFORE_LINK_STATE;
++
++	odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x01000100);
++	odm_set_bb_reg(dm, R_0xca8, MASKDWORD, 0x01000100);
++
++	/*@[BB] FAT setting*/
++	odm_set_bb_reg(dm, R_0xc08, BIT(18) | BIT(17) | BIT(16), sat_tab->ant_num);
++	odm_set_bb_reg(dm, R_0xc08, BIT(31), 0); /*@increase ant num every FAT period 0:+1, 1+2*/
++	odm_set_bb_reg(dm, R_0x8c4, BIT(2) | BIT(1), 1); /*@change cca antenna timming threshold if no CCA occurred: 0:200ms / 1:100ms / 2:no use / 3: 300*/
++	odm_set_bb_reg(dm, R_0x8c4, BIT(0), 1); /*@FAT_watchdog_en*/
++
++	value32 = odm_get_mac_reg(dm, R_0x7b4, MASKDWORD);
++	odm_set_mac_reg(dm, R_0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /*Reg7B4[16]=1 enable antenna training */
++	/*Reg7B4[17]=1 enable  match MAC addr*/
++	odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, 0); /*@Match MAC ADDR*/
++	odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, 0);
++}
++
++u32 phydm_construct_hl_beam_codeword(
++	void *dm_void,
++	u32 *beam_pattern_idx,
++	u32 ant_num)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++	u32 codeword = 0;
++	u32 data_tmp;
++	u32 i;
++	u32 break_counter = 0;
++
++	if (ant_num < 8) {
++		for (i = 0; i < (sat_tab->ant_num_total); i++) {
++#if 0
++			/*PHYDM_DBG(dm,DBG_ANT_DIV, "beam_pattern_num[%x] = %x\n",i,beam_pattern_num[i] );*/
++#endif
++			if ((i < (sat_tab->first_train_ant - 1)) || break_counter >= sat_tab->ant_num) {
++				data_tmp = 0;
++			} else {
++				break_counter++;
++
++				if (beam_pattern_idx[i] == 0) {
++					if (*dm->band_type == ODM_BAND_5G)
++						data_tmp = sat_tab->rfu_codeword_table_5g[0];
++					else
++						data_tmp = sat_tab->rfu_codeword_table[0];
++
++				} else if (beam_pattern_idx[i] == 1) {
++					if (*dm->band_type == ODM_BAND_5G)
++						data_tmp = sat_tab->rfu_codeword_table_5g[1];
++					else
++						data_tmp = sat_tab->rfu_codeword_table[1];
++
++				} else if (beam_pattern_idx[i] == 2) {
++					if (*dm->band_type == ODM_BAND_5G)
++						data_tmp = sat_tab->rfu_codeword_table_5g[2];
++					else
++						data_tmp = sat_tab->rfu_codeword_table[2];
++
++				} else if (beam_pattern_idx[i] == 3) {
++					if (*dm->band_type == ODM_BAND_5G)
++						data_tmp = sat_tab->rfu_codeword_table_5g[3];
++					else
++						data_tmp = sat_tab->rfu_codeword_table[3];
++				}
++			}
++
++			codeword |= (data_tmp << (i * 4));
++		}
++	}
++
++	return codeword;
++}
++
++void phydm_update_beam_pattern(
++	void *dm_void,
++	u32 codeword,
++	u32 codeword_length)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++	u8 i;
++	boolean beam_ctrl_signal;
++	u32 one = 0x1;
++	u32 reg44_tmp_p, reg44_tmp_n, reg44_ori;
++	u8 devide_num = 4;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] Set Beam Pattern =0x%x\n",
++		  codeword);
++
++	reg44_ori = odm_get_mac_reg(dm, R_0x44, MASKDWORD);
++	reg44_tmp_p = reg44_ori;
++#if 0
++	/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_ori =0x%x\n", reg44_ori);*/
++#endif
++
++	devide_num = (sat_tab->rfu_protocol_type == 2) ? 6 : 4;
++
++	for (i = 0; i <= (codeword_length - 1); i++) {
++		beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i);
++
++		if (dm->debug_components & DBG_ANT_DIV) {
++			if (i == (codeword_length - 1))
++				pr_debug("%d ]\n", beam_ctrl_signal);
++			else if (i == 0)
++				pr_debug("Send codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal);
++			else if ((i % devide_num) == (devide_num - 1))
++				pr_debug("%d  |  ", beam_ctrl_signal);
++			else
++				pr_debug("%d ", beam_ctrl_signal);
++		}
++
++		if (dm->support_ic_type == ODM_RTL8821) {
++			#if (RTL8821A_SUPPORT == 1)
++			reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT(10))); /*@clean bit 10 & 11*/
++			reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10));
++			reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10)));
++
++#if 0
++			/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n);*/
++#endif
++			odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
++			odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n);
++			#endif
++		}
++		#if (RTL8822B_SUPPORT == 1)
++		else if (dm->support_ic_type == ODM_RTL8822B) {
++			if (sat_tab->rfu_protocol_type == 2) {
++				reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*@clean bit 8*/
++				reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*@get new clk high/low, exclusive-or*/
++
++				reg44_tmp_p |= (beam_ctrl_signal << 8);
++
++				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
++				ODM_delay_us(10);
++#if 0
++				/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal);*/
++#endif
++
++			} else {
++				reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT(8))); /*@clean bit 9 & 8*/
++				reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8));
++				reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8)));
++
++#if 0
++				/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n); */
++#endif
++				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
++				ODM_delay_us(10);
++				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n);
++				ODM_delay_us(10);
++			}
++		}
++		#endif
++	}
++}
++
++void phydm_update_rx_idle_beam(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++	u32 i;
++
++	sat_tab->update_beam_codeword = phydm_construct_hl_beam_codeword(dm,
++									 &sat_tab->rx_idle_beam[0],
++									 sat_tab->ant_num);
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "Set target beam_pattern codeword = (( 0x%x ))\n",
++		  sat_tab->update_beam_codeword);
++
++	for (i = 0; i < (sat_tab->ant_num); i++)
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[ Update Rx-Idle-Beam ] RxIdleBeam[%d] =%d\n", i,
++			  sat_tab->rx_idle_beam[i]);
++
++#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++	if (dm->support_interface == ODM_ITRF_PCIE)
++		phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
++#endif
++#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
++	if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
++		odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
++#if 0
++	/*odm_stall_execution(1);*/
++#endif
++#endif
++
++	sat_tab->pre_codeword = sat_tab->update_beam_codeword;
++}
++
++void phydm_hl_smart_ant_debug(
++	void *dm_void,
++	char input[][16],
++	u32 *_used,
++	char *output,
++	u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 one = 0x1;
++	u32 codeword_length = sat_tab->rfu_codeword_total_bit_num;
++	u32 beam_ctrl_signal, i;
++	u8 devide_num = 4;
++
++	if (dm_value[0] == 1) { /*@fix beam pattern*/
++
++		sat_tab->fix_beam_pattern_en = dm_value[1];
++
++		if (sat_tab->fix_beam_pattern_en == 1) {
++			sat_tab->fix_beam_pattern_codeword = dm_value[2];
++
++			if (sat_tab->fix_beam_pattern_codeword > (one << codeword_length)) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n",
++					  sat_tab->fix_beam_pattern_codeword,
++					  codeword_length);
++
++				(sat_tab->fix_beam_pattern_codeword) &= 0xffffff;
++
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "[ SmartAnt ] Auto modify to (0x%x)\n",
++					  sat_tab->fix_beam_pattern_codeword);
++			}
++
++			sat_tab->update_beam_codeword = sat_tab->fix_beam_pattern_codeword;
++
++			/*@---------------------------------------------------------*/
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "Fix Beam Pattern\n");
++
++			devide_num = (sat_tab->rfu_protocol_type == 2) ? 6 : 4;
++
++			for (i = 0; i <= (codeword_length - 1); i++) {
++				beam_ctrl_signal = (boolean)((sat_tab->update_beam_codeword & BIT(i)) >> i);
++
++				if (i == (codeword_length - 1))
++					PDM_SNPF(out_len, used,
++						 output + used,
++						 out_len - used,
++						 "%d]\n",
++						 beam_ctrl_signal);
++				else if (i == 0)
++					PDM_SNPF(out_len, used,
++						 output + used,
++						 out_len - used,
++						 "Send Codeword[1:24] to RFU -> [%d",
++						 beam_ctrl_signal);
++				else if ((i % devide_num) == (devide_num - 1))
++					PDM_SNPF(out_len, used,
++						 output + used,
++						 out_len - used, "%d|",
++						 beam_ctrl_signal);
++				else
++					PDM_SNPF(out_len, used,
++						 output + used,
++						 out_len - used, "%d",
++						 beam_ctrl_signal);
++			}
++/*@---------------------------------------------------------*/
++
++			#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++			if (dm->support_interface == ODM_ITRF_PCIE)
++				phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
++			#endif
++			#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
++			if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
++				odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
++#if 0
++			/*odm_stall_execution(1);*/
++#endif
++			#endif
++		} else if (sat_tab->fix_beam_pattern_en == 0)
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[ SmartAnt ] Smart Antenna: Enable\n");
++
++	} else if (dm_value[0] == 2) { /*set latch time*/
++
++		sat_tab->latch_time = dm_value[1];
++		PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ]  latch_time =0x%x\n",
++			  sat_tab->latch_time);
++	} else if (dm_value[0] == 3) {
++		sat_tab->fix_training_num_en = dm_value[1];
++
++		if (sat_tab->fix_training_num_en == 1) {
++			sat_tab->per_beam_training_pkt_num = (u8)dm_value[2];
++			sat_tab->decision_holding_period = (u8)dm_value[3];
++
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[SmartAnt][Dbg] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n",
++				 sat_tab->fix_training_num_en,
++				 sat_tab->per_beam_training_pkt_num,
++				 sat_tab->decision_holding_period);
++
++		} else if (sat_tab->fix_training_num_en == 0) {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[ SmartAnt ]  AUTO per_beam_training_pkt_num\n");
++		}
++	} else if (dm_value[0] == 4) {
++		if (dm_value[1] == 1) {
++			sat_tab->ant_num = 1;
++			sat_tab->first_train_ant = MAIN_ANT;
++
++		} else if (dm_value[1] == 2) {
++			sat_tab->ant_num = 1;
++			sat_tab->first_train_ant = AUX_ANT;
++
++		} else if (dm_value[1] == 3) {
++			sat_tab->ant_num = 2;
++			sat_tab->first_train_ant = MAIN_ANT;
++		}
++
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "[ SmartAnt ]  Set ant Num = (( %d )), first_train_ant = (( %d ))\n",
++			 sat_tab->ant_num, (sat_tab->first_train_ant - 1));
++	} else if (dm_value[0] == 5) {
++		if (dm_value[1] <= 3) {
++			sat_tab->rfu_codeword_table[dm_value[1]] = dm_value[2];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[ SmartAnt ] Set Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n",
++				 dm_value[1], dm_value[2]);
++		} else {
++			for (i = 0; i < 4; i++) {
++				PDM_SNPF(out_len, used, output + used,
++					 out_len - used,
++					 "[ SmartAnt ] Show Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n",
++					 i, sat_tab->rfu_codeword_table[i]);
++			}
++		}
++	} else if (dm_value[0] == 6) {
++		if (dm_value[1] <= 3) {
++			sat_tab->rfu_codeword_table_5g[dm_value[1]] = dm_value[2];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[ SmartAnt ] Set Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n",
++				 dm_value[1], dm_value[2]);
++		} else {
++			for (i = 0; i < 4; i++) {
++				PDM_SNPF(out_len, used, output + used,
++					 out_len - used,
++					 "[ SmartAnt ] Show Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n",
++					 i, sat_tab->rfu_codeword_table_5g[i]);
++			}
++		}
++	} else if (dm_value[0] == 7) {
++		if (dm_value[1] <= 4) {
++			sat_tab->beam_patten_num_each_ant = dm_value[1];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[ SmartAnt ] Set Beam number = (( %d ))\n",
++				 sat_tab->beam_patten_num_each_ant);
++		} else {
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "[ SmartAnt ] Show Beam number = (( %d ))\n",
++				 sat_tab->beam_patten_num_each_ant);
++		}
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_set_all_ant_same_beam_num(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++
++	if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { /*@2ant for 8821A*/
++
++		sat_tab->rx_idle_beam[0] = sat_tab->fast_training_beam_num;
++		sat_tab->rx_idle_beam[1] = sat_tab->fast_training_beam_num;
++	}
++
++	sat_tab->update_beam_codeword = phydm_construct_hl_beam_codeword(dm,
++									 &sat_tab->rx_idle_beam[0],
++									 sat_tab->ant_num);
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[ SmartAnt ] Set all ant beam_pattern: codeword = (( 0x%x ))\n",
++		  sat_tab->update_beam_codeword);
++
++#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++	if (dm->support_interface == ODM_ITRF_PCIE)
++		phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
++#endif
++#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
++	if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
++		odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
++/*odm_stall_execution(1);*/
++#endif
++}
++
++void odm_fast_ant_training_hl_smart_antenna_type1(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
++	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
++	u32 codeword = 0, i, j;
++	u32 target_ant;
++	u32 avg_rssi_tmp, avg_rssi_tmp_ma;
++	u32 target_ant_beam_max_rssi[SUPPORT_RF_PATH_NUM] = {0};
++	u32 max_beam_ant_rssi = 0;
++	u32 target_ant_beam[SUPPORT_RF_PATH_NUM] = {0};
++	u32 beam_tmp;
++	u8 next_ant;
++	u32 rssi_sorting_seq[SUPPORT_BEAM_PATTERN_NUM] = {0};
++	u32 rank_idx_seq[SUPPORT_BEAM_PATTERN_NUM] = {0};
++	u32 rank_idx_out[SUPPORT_BEAM_PATTERN_NUM] = {0};
++	u8 per_beam_rssi_diff_tmp = 0, training_pkt_num_offset;
++	u32 break_counter = 0;
++	u32 used_ant;
++
++	if (!dm->is_linked) {
++		PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
++
++		if (fat_tab->is_become_linked == true) {
++			PHYDM_DBG(dm, DBG_ANT_DIV, "Link->no Link\n");
++			fat_tab->fat_state = FAT_BEFORE_LINK_STATE;
++			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
++			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "change to (( %d )) FAT_state\n",
++				  fat_tab->fat_state);
++
++			fat_tab->is_become_linked = dm->is_linked;
++		}
++		return;
++
++	} else {
++		if (fat_tab->is_become_linked == false) {
++			PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
++
++			fat_tab->fat_state = FAT_PREPARE_STATE;
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "change to (( %d )) FAT_state\n",
++				  fat_tab->fat_state);
++
++#if 0
++			/*sat_tab->fast_training_beam_num = 0;*/
++			/*phydm_set_all_ant_same_beam_num(dm);*/
++#endif
++
++			fat_tab->is_become_linked = dm->is_linked;
++		}
++	}
++
++	if (!(*fat_tab->p_force_tx_by_desc)) {
++		if (dm->is_one_entry_only == true)
++			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
++		else
++			odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
++	}
++
++#if 0
++	/*PHYDM_DBG(dm, DBG_ANT_DIV, "HL Smart ant Training: state (( %d ))\n", fat_tab->fat_state);*/
++#endif
++
++	/* @[DECISION STATE] */
++	/*@=======================================================================================*/
++	if (fat_tab->fat_state == FAT_DECISION_STATE) {
++		PHYDM_DBG(dm, DBG_ANT_DIV, "[ 3. In Decision state]\n");
++		phydm_fast_training_enable(dm, FAT_OFF);
++
++		break_counter = 0;
++		/*@compute target beam in each antenna*/
++		for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) {
++			for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) {
++				if (sat_tab->pkt_rssi_cnt[i][j] == 0) {
++					avg_rssi_tmp = sat_tab->pkt_rssi_pre[i][j];
++					avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp;
++					avg_rssi_tmp_ma = avg_rssi_tmp;
++				} else {
++					avg_rssi_tmp = (sat_tab->pkt_rssi_sum[i][j]) / (sat_tab->pkt_rssi_cnt[i][j]);
++					avg_rssi_tmp_ma = (avg_rssi_tmp + sat_tab->pkt_rssi_pre[i][j]) >> 1;
++				}
++
++				rssi_sorting_seq[j] = avg_rssi_tmp;
++				sat_tab->pkt_rssi_pre[i][j] = avg_rssi_tmp;
++
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "ant[%d], Beam[%d]: pkt_cnt=(( %d )), avg_rssi_MA=(( %d )), avg_rssi=(( %d ))\n",
++					  i, j, sat_tab->pkt_rssi_cnt[i][j],
++					  avg_rssi_tmp_ma, avg_rssi_tmp);
++
++				if (avg_rssi_tmp > target_ant_beam_max_rssi[i]) {
++					target_ant_beam[i] = j;
++					target_ant_beam_max_rssi[i] = avg_rssi_tmp;
++				}
++
++				/*reset counter value*/
++				sat_tab->pkt_rssi_sum[i][j] = 0;
++				sat_tab->pkt_rssi_cnt[i][j] = 0;
++			}
++			sat_tab->rx_idle_beam[i] = target_ant_beam[i];
++			PHYDM_DBG(dm, DBG_ANT_DIV,
++				  "---------> Target of ant[%d]: Beam_num-(( %d )) RSSI= ((%d))\n",
++				  i, target_ant_beam[i],
++				  target_ant_beam_max_rssi[i]);
++
++#if 0
++			/*sorting*/
++			/*@
++			PHYDM_DBG(dm, DBG_ANT_DIV, "[Pre]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3]);
++			*/
++
++			/*phydm_seq_sorting(dm, &rssi_sorting_seq[0], &rank_idx_seq[0], &rank_idx_out[0], SUPPORT_BEAM_PATTERN_NUM);*/
++
++			/*@
++			PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3]);
++			PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rank_idx_seq = [%d, %d, %d, %d]\n", rank_idx_seq[0], rank_idx_seq[1], rank_idx_seq[2], rank_idx_seq[3]);
++			PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rank_idx_out = [%d, %d, %d, %d]\n", rank_idx_out[0], rank_idx_out[1], rank_idx_out[2], rank_idx_out[3]);
++			*/
++#endif
++
++			if (target_ant_beam_max_rssi[i] > max_beam_ant_rssi) {
++				target_ant = i;
++				max_beam_ant_rssi = target_ant_beam_max_rssi[i];
++#if
++				/*PHYDM_DBG(dm, DBG_ANT_DIV, "Target of ant = (( %d )) max_beam_ant_rssi = (( %d ))\n",
++					target_ant,  max_beam_ant_rssi);*/
++#endif
++			}
++			break_counter++;
++			if (break_counter >= sat_tab->ant_num)
++				break;
++		}
++
++#ifdef CONFIG_FAT_PATCH
++		break_counter = 0;
++		for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) {
++			for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) {
++				per_beam_rssi_diff_tmp = (u8)(max_beam_ant_rssi - sat_tab->pkt_rssi_pre[i][j]);
++				sat_tab->beam_train_rssi_diff[i][j] = per_beam_rssi_diff_tmp;
++
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "ant[%d], Beam[%d]: RSSI_diff= ((%d))\n",
++					  i, j, per_beam_rssi_diff_tmp);
++			}
++			break_counter++;
++			if (break_counter >= sat_tab->ant_num)
++				break;
++		}
++#endif
++
++		if (target_ant == 0)
++			target_ant = MAIN_ANT;
++		else if (target_ant == 1)
++			target_ant = AUX_ANT;
++
++		if (sat_tab->ant_num > 1) {
++			/* @[ update RX ant ]*/
++			odm_update_rx_idle_ant(dm, (u8)target_ant);
++
++			/* @[ update TX ant ]*/
++			odm_update_tx_ant(dm, (u8)target_ant, (fat_tab->train_idx));
++		}
++
++		/*set beam in each antenna*/
++		phydm_update_rx_idle_beam(dm);
++
++		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
++		fat_tab->fat_state = FAT_PREPARE_STATE;
++		return;
++	}
++	/* @[TRAINING STATE] */
++	else if (fat_tab->fat_state == FAT_TRAINING_STATE) {
++		PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2. In Training state]\n");
++
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "fat_beam_n = (( %d )), pre_fat_beam_n = (( %d ))\n",
++			  sat_tab->fast_training_beam_num,
++			  sat_tab->pre_fast_training_beam_num);
++
++		if (sat_tab->fast_training_beam_num > sat_tab->pre_fast_training_beam_num)
++
++			sat_tab->force_update_beam_en = 0;
++
++		else {
++			sat_tab->force_update_beam_en = 1;
++
++			sat_tab->pkt_counter = 0;
++			beam_tmp = sat_tab->fast_training_beam_num;
++			if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "[Timeout Update]  Beam_num (( %d )) -> (( decision ))\n",
++					  sat_tab->fast_training_beam_num);
++				fat_tab->fat_state = FAT_DECISION_STATE;
++				odm_fast_ant_training_hl_smart_antenna_type1(dm);
++
++			} else {
++				sat_tab->fast_training_beam_num++;
++
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "[Timeout Update]  Beam_num (( %d )) -> (( %d ))\n",
++					  beam_tmp,
++					  sat_tab->fast_training_beam_num);
++				phydm_set_all_ant_same_beam_num(dm);
++				fat_tab->fat_state = FAT_TRAINING_STATE;
++			}
++		}
++		sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "[prepare state] Update Pre_Beam =(( %d ))\n",
++			  sat_tab->pre_fast_training_beam_num);
++	}
++	/*  @[Prepare state] */
++	/*@=======================================================================================*/
++	else if (fat_tab->fat_state == FAT_PREPARE_STATE) {
++		PHYDM_DBG(dm, DBG_ANT_DIV, "\n\n[ 1. In Prepare state]\n");
++
++		if (dm->pre_traffic_load == dm->traffic_load) {
++			if (sat_tab->decision_holding_period != 0) {
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "Holding_period = (( %d )), return!!!\n",
++					  sat_tab->decision_holding_period);
++				sat_tab->decision_holding_period--;
++				return;
++			}
++		}
++
++		/* Set training packet number*/
++		if (sat_tab->fix_training_num_en == 0) {
++			switch (dm->traffic_load) {
++			case TRAFFIC_HIGH:
++				sat_tab->per_beam_training_pkt_num = 8;
++				sat_tab->decision_holding_period = 2;
++				break;
++			case TRAFFIC_MID:
++				sat_tab->per_beam_training_pkt_num = 6;
++				sat_tab->decision_holding_period = 3;
++				break;
++			case TRAFFIC_LOW:
++				sat_tab->per_beam_training_pkt_num = 3; /*ping 60000*/
++				sat_tab->decision_holding_period = 4;
++				break;
++			case TRAFFIC_ULTRA_LOW:
++				sat_tab->per_beam_training_pkt_num = 1;
++				sat_tab->decision_holding_period = 6;
++				break;
++			default:
++				break;
++			}
++		}
++		PHYDM_DBG(dm, DBG_ANT_DIV,
++			  "Fix_training_en = (( %d )), training_pkt_num_base = (( %d )), holding_period = ((%d))\n",
++			  sat_tab->fix_training_num_en,
++			  sat_tab->per_beam_training_pkt_num,
++			  sat_tab->decision_holding_period);
++
++#ifdef CONFIG_FAT_PATCH
++		break_counter = 0;
++		for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) {
++			for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) {
++				per_beam_rssi_diff_tmp = sat_tab->beam_train_rssi_diff[i][j];
++				training_pkt_num_offset = per_beam_rssi_diff_tmp;
++
++				if (sat_tab->per_beam_training_pkt_num > training_pkt_num_offset)
++					sat_tab->beam_train_cnt[i][j] = sat_tab->per_beam_training_pkt_num - training_pkt_num_offset;
++				else
++					sat_tab->beam_train_cnt[i][j] = 1;
++
++				PHYDM_DBG(dm, DBG_ANT_DIV,
++					  "ant[%d]: Beam_num-(( %d ))  training_pkt_num = ((%d))\n",
++					  i, j, sat_tab->beam_train_cnt[i][j]);
++			}
++			break_counter++;
++			if (break_counter >= sat_tab->ant_num)
++				break;
++		}
++
++		phydm_fast_training_enable(dm, FAT_OFF);
++		sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
++		sat_tab->update_beam_idx = 0;
++
++		if (*dm->band_type == ODM_BAND_5G) {
++			PHYDM_DBG(dm, DBG_ANT_DIV, "Set 5G ant\n");
++			/*used_ant = (sat_tab->first_train_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;*/
++			used_ant = sat_tab->first_train_ant;
++		} else {
++			PHYDM_DBG(dm, DBG_ANT_DIV, "Set 2.4G ant\n");
++			used_ant = sat_tab->first_train_ant;
++		}
++
++		odm_update_rx_idle_ant(dm, (u8)used_ant);
++
++#else
++		/* Set training MAC addr. of target */
++		odm_set_next_mac_addr_target(dm);
++		phydm_fast_training_enable(dm, FAT_ON);
++#endif
++
++		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
++		sat_tab->pkt_counter = 0;
++		sat_tab->fast_training_beam_num = 0;
++		phydm_set_all_ant_same_beam_num(dm);
++		sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
++		fat_tab->fat_state = FAT_TRAINING_STATE;
++	}
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++
++void phydm_beam_switch_workitem_callback(
++	void *context)
++{
++	void *adapter = (void *)context;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
++
++#if DEV_BUS_TYPE != RT_PCI_INTERFACE
++	sat_tab->pkt_skip_statistic_en = 1;
++#endif
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n",
++		  sat_tab->pkt_skip_statistic_en);
++
++	phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
++
++#if DEV_BUS_TYPE != RT_PCI_INTERFACE
++#if 0
++	/*odm_stall_execution(sat_tab->latch_time);*/
++#endif
++	sat_tab->pkt_skip_statistic_en = 0;
++#endif
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n",
++		  sat_tab->pkt_skip_statistic_en, sat_tab->latch_time);
++}
++
++void phydm_beam_decision_workitem_callback(
++	void *context)
++{
++	void *adapter = (void *)context;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++
++	PHYDM_DBG(dm, DBG_ANT_DIV,
++		  "[ SmartAnt ] Beam decision Workitem Callback\n");
++	odm_fast_ant_training_hl_smart_antenna_type1(dm);
++}
++#endif
++
++#endif /*@#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/
++
++#endif /*@#ifdef CONFIG_HL_SMART_ANTENNA*/
++
++void phydm_smt_ant_config(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant *smtant_table = &dm->smtant_table;
++
++#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
++
++	dm->support_ability |= ODM_BB_SMT_ANT;
++	smtant_table->smt_ant_vendor = SMTANT_CUMITEK;
++	smtant_table->smt_ant_type = 1;
++#if (RTL8822B_SUPPORT == 1)
++	dm->rfe_type = SMTANT_TMP_RFE_TYPE;
++#endif
++#elif (defined(CONFIG_HL_SMART_ANTENNA))
++
++	dm->support_ability |= ODM_BB_SMT_ANT;
++	smtant_table->smt_ant_vendor = SMTANT_HON_BO;
++
++#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
++	smtant_table->smt_ant_type = 1;
++#endif
++
++#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
++	smtant_table->smt_ant_type = 2;
++#endif
++#endif
++
++	PHYDM_DBG(dm, DBG_SMT_ANT,
++		  "[SmtAnt Config] Vendor=((%d)), Smt_ant_type =((%d))\n",
++		  smtant_table->smt_ant_vendor, smtant_table->smt_ant_type);
++}
++
++void phydm_smt_ant_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct smt_ant *smtant_table = &dm->smtant_table;
++
++	phydm_smt_ant_config(dm);
++
++	if (smtant_table->smt_ant_vendor == SMTANT_CUMITEK) {
++#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
++#if (RTL8822B_SUPPORT == 1)
++		if (dm->support_ic_type == ODM_RTL8822B)
++			phydm_cumitek_smt_ant_init_8822b(dm);
++#endif
++
++#if (RTL8197F_SUPPORT == 1)
++		if (dm->support_ic_type == ODM_RTL8197F)
++			phydm_cumitek_smt_ant_init_8197f(dm);
++#endif
++/*@jj add 20170822*/
++#if (RTL8192F_SUPPORT == 1)
++		if (dm->support_ic_type == ODM_RTL8192F)
++			phydm_cumitek_smt_ant_init_8192f(dm);
++#endif
++#endif /*@#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))*/
++
++	} else if (smtant_table->smt_ant_vendor == SMTANT_HON_BO) {
++#if (defined(CONFIG_HL_SMART_ANTENNA))
++#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
++		if (dm->support_ic_type == ODM_RTL8821)
++			phydm_hl_smart_ant_type1_init_8821a(dm);
++#endif
++
++#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
++		if (dm->support_ic_type == ODM_RTL8822B)
++			phydm_hl_smart_ant_type2_init_8822b(dm);
++#endif
++#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/
++	}
++}
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_smt_ant.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_smt_ant.h
+new file mode 100644
+index 000000000..3a408c4c6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_smt_ant.h
+@@ -0,0 +1,210 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDMSMTANT_H__
++#define __PHYDMSMTANT_H__
++
++/*@#define SMT_ANT_VERSION	"1.1"*/ /*@2017.03.13*/
++/*@#define SMT_ANT_VERSION	"1.2"*/ /*@2017.03.28*/
++#define SMT_ANT_VERSION "2.0" /* @Add Cumitek SmtAnt 2017.05.25*/
++
++#define	SMTANT_RTK		1
++#define	SMTANT_HON_BO	2
++#define	SMTANT_CUMITEK	3
++
++#if (defined(CONFIG_SMART_ANTENNA))
++
++#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
++struct smt_ant_cumitek {
++	u8	tx_ant_idx[2][ODM_ASSOCIATE_ENTRY_NUM]; /*@[pathA~B] [MACID 0~128]*/
++	u8	rx_default_ant_idx[2]; /*@[pathA~B]*/
++};
++#endif
++
++#if (defined(CONFIG_HL_SMART_ANTENNA))
++struct smt_ant_honbo {
++	u32	latch_time;
++	boolean	pkt_skip_statistic_en;
++	u32	fix_beam_pattern_en;
++	u32	fix_training_num_en;
++	u32	fix_beam_pattern_codeword;
++	u32	update_beam_codeword;
++	u32	ant_num; /*number of "used" smart beam antenna*/
++	u32	ant_num_total;/*number of "total" smart beam antenna*/
++	u32	first_train_ant; /*@decide witch antenna to train first*/
++
++	#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
++	u32	pkt_rssi_pre[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];/*@rssi of each path with a certain beam pattern*/
++	u8	beam_train_rssi_diff[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
++	u8	beam_train_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
++	u32	rfu_codeword_table[4]; /*@2G beam truth table*/
++	u32	rfu_codeword_table_5g[4]; /*@5G beam truth table*/
++	u32	beam_patten_num_each_ant;/*@number of  beam can be switched in each antenna*/
++	u32	rx_idle_beam[SUPPORT_RF_PATH_NUM];
++	u32	pkt_rssi_sum[8][SUPPORT_BEAM_PATTERN_NUM];
++	u32	pkt_rssi_cnt[8][SUPPORT_BEAM_PATTERN_NUM];
++	#endif
++
++	u32	fast_training_beam_num;/*@current training beam_set index*/
++	u32	pre_fast_training_beam_num;/*pre training beam_set index*/
++	u32	rfu_codeword_total_bit_num; /* @total bit number of RFU protocol*/
++	u32	rfu_each_ant_bit_num; /* @bit number of RFU protocol for each ant*/
++	u8	per_beam_training_pkt_num;
++	u8	decision_holding_period;
++
++
++	u32	pre_codeword;
++	boolean	force_update_beam_en;
++	u32	beacon_counter;
++	u32	pre_beacon_counter;
++	u8	pkt_counter;		/*@packet number that each beam-set should be colected in training state*/
++	u8	update_beam_idx;	/*@the index announce that the beam can be updated*/
++	u8	rfu_protocol_type;
++	u16	rfu_protocol_delay_time;
++
++	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	RT_WORK_ITEM	hl_smart_antenna_workitem;
++	RT_WORK_ITEM	hl_smart_antenna_decision_workitem;
++	#endif
++
++
++	#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
++	u8	beam_set_avg_rssi_pre[SUPPORT_BEAM_SET_PATTERN_NUM];		/*@avg pre_rssi of each beam set*/
++	u8	beam_set_train_val_diff[SUPPORT_BEAM_SET_PATTERN_NUM];	/*@rssi of a beam pattern set, ex: a set = {ant1_beam=1, ant2_beam=3}*/
++	u8	beam_set_train_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];			/*@training pkt num of each beam set*/
++	u32	beam_set_rssi_avg_sum[SUPPORT_BEAM_SET_PATTERN_NUM];			/*@RSSI_sum of avg(pathA,pathB) for each beam-set)*/
++	u32	beam_path_rssi_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*@RSSI_sum of each path for each beam-set)*/
++
++	u8	beam_set_avg_evm_2ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM];
++	u32	beam_path_evm_2ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*@2SS evm_sum of each path for each beam-set)*/
++	u32	beam_path_evm_2ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];
++
++	u8	beam_set_avg_evm_1ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM];
++	u32	beam_path_evm_1ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM];/*@1SS evm_sum of each path for each beam-set)*/
++	u32	beam_path_evm_1ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];
++
++	u32	statistic_pkt_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];				/*@statistic_pkt_cnt for SmtAnt make decision*/
++
++	u8	total_beam_set_num;	/*@number of  beam set can be switched*/
++	u8	total_beam_set_num_2g;/*@number of  beam set can be switched in 2G*/
++	u8	total_beam_set_num_5g;/*@number of  beam set can be switched in 5G*/
++
++	u8	rfu_codeword_table_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*@2G beam truth table*/
++	u8	rfu_codeword_table_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*@5G beam truth table*/
++	u8	rx_idle_beam_set_idx;	/*the filanl decsion result*/
++	#endif
++
++
++};
++#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/
++
++struct smt_ant {
++	u8	smt_ant_vendor;
++	u8	smt_ant_type;
++	u8	tx_desc_mode; /*@0:3 bit mode, 1:2 bit mode*/
++	#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
++	struct	smt_ant_cumitek	cumi_smtant_table;
++	#endif
++};
++
++#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
++void phydm_cumitek_smt_tx_ant_update(
++	void *dm_void,
++	u8 tx_ant_idx_path_a,
++	u8 tx_ant_idx_path_b,
++	u32 mac_id);
++
++void phydm_cumitek_smt_rx_default_ant_update(
++	void *dm_void,
++	u8 rx_ant_idx_path_a,
++	u8 rx_ant_idx_path_b);
++
++void phydm_cumitek_smt_ant_debug(
++	void *dm_void,
++	char input[][16],
++	u32 *_used,
++	char *output,
++	u32 *_out_len);
++
++#endif
++
++#if (defined(CONFIG_HL_SMART_ANTENNA))
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void phydm_beam_switch_workitem_callback(
++	void *context);
++
++void phydm_beam_decision_workitem_callback(
++	void *context);
++#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
++
++#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
++void phydm_hl_smart_ant_type2_init_8822b(
++	void *dm_void);
++
++void phydm_update_beam_pattern_type2(
++	void *dm_void,
++	u32 codeword,
++	u32 codeword_length);
++
++void phydm_set_rfu_beam_pattern_type2(
++	void *dm_void);
++
++void phydm_hl_smt_ant_dbg_type2(
++	void *dm_void,
++	char input[][16],
++	u32 *_used,
++	char *output,
++	u32 *_out_len);
++
++void phydm_process_rssi_for_hb_smtant_type2(
++	void *dm_void,
++	void *phy_info_void,
++	void *pkt_info_void,
++	u8 rssi_avg);
++
++#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE2))*/
++
++#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))
++
++void phydm_update_beam_pattern(
++	void *dm_void,
++	u32 codeword,
++	u32 codeword_length);
++
++void phydm_set_all_ant_same_beam_num(
++	void *dm_void);
++
++void phydm_hl_smart_ant_debug(
++	void *dm_void,
++	char input[][16],
++	u32 *_used,
++	char *output,
++	u32 *_out_len);
++
++#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))*/
++#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/
++void phydm_smt_ant_init(void *dm_void);
++#endif /*@#if (defined(CONFIG_SMART_ANTENNA))*/
++#endif
+\ No newline at end of file
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_soml.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_soml.c
+new file mode 100644
+index 000000000..cba806ed0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_soml.c
+@@ -0,0 +1,1441 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++
++/*************************************************************
++ * include files
++ ************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#ifdef CONFIG_ADAPTIVE_SOML
++
++void phydm_dynamicsoftmletting(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 ret_val;
++
++#if (RTL8822B_SUPPORT == 1)
++	if (!*dm->mp_mode) {
++		if (dm->support_ic_type & ODM_RTL8822B) {
++			if (!dm->is_linked | dm->iot_table.is_linked_cmw500)
++				return;
++
++			if (dm->bsomlenabled) {
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "PHYDM_DynamicSoftMLSetting(): SoML has been enable, skip dynamic SoML switch\n");
++				return;
++			}
++
++			ret_val = odm_get_bb_reg(dm, R_0xf8c, MASKBYTE0);
++			PHYDM_DBG(dm, ODM_COMP_API,
++				  "PHYDM_DynamicSoftMLSetting(): Read 0xF8C = 0x%08X\n",
++				  ret_val);
++
++			if (ret_val < 0x16) {
++				PHYDM_DBG(dm, ODM_COMP_API,
++					  "PHYDM_DynamicSoftMLSetting(): 0xF8C(== 0x%08X) < 0x16, enable SoML\n",
++					  ret_val);
++				phydm_somlrxhp_setting(dm, true);
++#if 0
++			/*odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0xc10a0000);*/
++#endif
++				dm->bsomlenabled = true;
++			}
++		}
++	}
++#endif
++}
++
++void phydm_soml_on_off(void *dm_void, u8 swch)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++
++	if (swch == SOML_ON) {
++		PHYDM_DBG(dm, DBG_ADPTV_SOML, "(( Turn on )) SOML\n");
++
++		if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
++			odm_set_bb_reg(dm, R_0x998, BIT(6), swch);
++#if (RTL8822B_SUPPORT == 1)
++		else if (dm->support_ic_type == ODM_RTL8822B)
++			phydm_somlrxhp_setting(dm, true);
++#endif
++
++	} else if (swch == SOML_OFF) {
++		PHYDM_DBG(dm, DBG_ADPTV_SOML, "(( Turn off )) SOML\n");
++
++		if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
++			odm_set_bb_reg(dm, R_0x998, BIT(6), swch);
++#if (RTL8822B_SUPPORT == 1)
++		else if (dm->support_ic_type == ODM_RTL8822B)
++			phydm_somlrxhp_setting(dm, false);
++#endif
++	}
++	soml_tab->soml_on_off = swch;
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void phydm_adaptive_soml_callback(struct phydm_timer_list *timer)
++{
++	void *adapter = (void *)timer->Adapter;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++
++	#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++	#if USE_WORKITEM
++	odm_schedule_work_item(&soml_tab->phydm_adaptive_soml_workitem);
++	#else
++	{
++#if 0
++		/*@dbg_print("%s\n",__func__);*/
++#endif
++		phydm_adsl(dm);
++	}
++	#endif
++	#else
++	odm_schedule_work_item(&soml_tab->phydm_adaptive_soml_workitem);
++	#endif
++}
++
++void phydm_adaptive_soml_workitem_callback(void *context)
++{
++#ifdef CONFIG_ADAPTIVE_SOML
++	void *adapter = (void *)context;
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++
++#if 0
++	/*@dbg_print("%s\n",__func__);*/
++#endif
++	phydm_adsl(dm);
++#endif
++}
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++void phydm_adaptive_soml_callback(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	void *padapter = dm->adapter;
++
++	if (*dm->is_net_closed == true)
++		return;
++	if (dm->support_interface == ODM_ITRF_PCIE)
++		phydm_adsl(dm);
++	else {
++		/* @Can't do I/O in timer callback*/
++		phydm_run_in_thread_cmd(dm,
++					phydm_adaptive_soml_workitem_callback,
++					dm);
++	}
++}
++
++void phydm_adaptive_soml_workitem_callback(void *context)
++{
++	struct dm_struct *dm = (void *)context;
++
++#if 0
++	/*@dbg_print("%s\n",__func__);*/
++#endif
++	phydm_adsl(dm);
++}
++
++#else
++void phydm_adaptive_soml_callback(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_ADPTV_SOML, "******SOML_Callback******\n");
++	phydm_adsl(dm);
++}
++#endif
++
++void phydm_rx_rate_for_soml(void *dm_void, void *pkt_info_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++	struct phydm_perpkt_info_struct *pktinfo = NULL;
++	u8 data_rate;
++
++	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
++	data_rate = (pktinfo->data_rate & 0x7f);
++
++	if (pktinfo->data_rate >= ODM_RATEMCS0 &&
++	    pktinfo->data_rate <= ODM_RATEMCS31)
++		soml_tab->ht_cnt[data_rate - ODM_RATEMCS0]++;
++	else if ((pktinfo->data_rate >= ODM_RATEVHTSS1MCS0) &&
++		 (pktinfo->data_rate <= ODM_RATEVHTSS4MCS9))
++		soml_tab->vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++;
++}
++
++void phydm_rx_qam_for_soml(void *dm_void, void *pkt_info_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++	struct phydm_perpkt_info_struct *pktinfo = NULL;
++	u8 date_rate;
++
++	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
++	date_rate = (pktinfo->data_rate & 0x7f);
++	if (soml_tab->soml_state_cnt < (soml_tab->soml_train_num << 1)) {
++		if (soml_tab->soml_on_off == SOML_ON) {
++			return;
++		} else if (soml_tab->soml_on_off == SOML_OFF) {
++			if (date_rate >= ODM_RATEMCS8 &&
++			    date_rate <= ODM_RATEMCS10)
++				soml_tab->num_ht_qam[BPSK_QPSK]++;
++
++			else if ((date_rate >= ODM_RATEMCS11) &&
++				 (date_rate <= ODM_RATEMCS12))
++				soml_tab->num_ht_qam[QAM16]++;
++
++			else if ((date_rate >= ODM_RATEMCS13) &&
++				 (date_rate <= ODM_RATEMCS15))
++				soml_tab->num_ht_qam[QAM64]++;
++
++			else if ((date_rate >= ODM_RATEVHTSS2MCS0) &&
++				 (date_rate <= ODM_RATEVHTSS2MCS2))
++				soml_tab->num_vht_qam[BPSK_QPSK]++;
++
++			else if ((date_rate >= ODM_RATEVHTSS2MCS3) &&
++				 (date_rate <= ODM_RATEVHTSS2MCS4))
++				soml_tab->num_vht_qam[QAM16]++;
++
++			else if ((date_rate >= ODM_RATEVHTSS2MCS5) &&
++				 (date_rate <= ODM_RATEVHTSS2MCS5))
++				soml_tab->num_vht_qam[QAM64]++;
++
++			else if ((date_rate >= ODM_RATEVHTSS2MCS8) &&
++				 (date_rate <= ODM_RATEVHTSS2MCS9))
++				soml_tab->num_vht_qam[QAM256]++;
++		}
++	}
++}
++
++void phydm_soml_reset_rx_rate(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++	u8 order;
++
++	for (order = 0; order < HT_RATE_IDX; order++) {
++		soml_tab->ht_cnt[order] = 0;
++		soml_tab->pre_ht_cnt[order] = 0;
++		soml_tab->ht_cnt_on[order] = 0;
++		soml_tab->ht_cnt_off[order] = 0;
++		soml_tab->ht_crc_ok_cnt_on[order] = 0;
++		soml_tab->ht_crc_fail_cnt_on[order] = 0;
++		soml_tab->ht_crc_ok_cnt_off[order] = 0;
++		soml_tab->ht_crc_fail_cnt_off[order] = 0;
++	}
++
++	for (order = 0; order < VHT_RATE_IDX; order++) {
++		soml_tab->vht_cnt[order] = 0;
++		soml_tab->pre_vht_cnt[order] = 0;
++		soml_tab->vht_cnt_on[order] = 0;
++		soml_tab->vht_cnt_off[order] = 0;
++		soml_tab->vht_crc_ok_cnt_on[order] = 0;
++		soml_tab->vht_crc_fail_cnt_on[order] = 0;
++		soml_tab->vht_crc_ok_cnt_off[order] = 0;
++		soml_tab->vht_crc_fail_cnt_off[order] = 0;
++	}
++}
++
++void phydm_soml_reset_qam(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++	u8 order;
++
++	for (order = 0; order < HT_ORDER_TYPE; order++)
++		soml_tab->num_ht_qam[order] = 0;
++
++	for (order = 0; order < VHT_ORDER_TYPE; order++)
++		soml_tab->num_vht_qam[order] = 0;
++}
++
++void phydm_soml_cfo_process(void *dm_void, s32 *diff_a, s32 *diff_b)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 value32, value32_1, value32_2, value32_3;
++	s32 cfo_acq_a, cfo_acq_b, cfo_end_a, cfo_end_b;
++
++	value32 = odm_get_bb_reg(dm, R_0xd10, MASKDWORD);
++	value32_1 = odm_get_bb_reg(dm, R_0xd14, MASKDWORD);
++	value32_2 = odm_get_bb_reg(dm, R_0xd50, MASKDWORD);
++	value32_3 = odm_get_bb_reg(dm, R_0xd54, MASKDWORD);
++
++	cfo_acq_a = (s32)((value32 & 0x1fff0000) >> 16);
++	cfo_end_a = (s32)((value32_1 & 0x1fff0000) >> 16);
++	cfo_acq_b = (s32)((value32_2 & 0x1fff0000) >> 16);
++	cfo_end_b = (s32)((value32_3 & 0x1fff0000) >> 16);
++
++	*diff_a = ((cfo_acq_a >= cfo_end_a) ? (cfo_acq_a - cfo_end_a) :
++		  (cfo_end_a - cfo_acq_a));
++	*diff_b = ((cfo_acq_b >= cfo_end_b) ? (cfo_acq_b - cfo_end_b) :
++		  (cfo_end_b - cfo_acq_b));
++
++	*diff_a = ((*diff_a * 312) + (*diff_a >> 1)) >> 12; /* @312.5/2^12 */
++	*diff_b = ((*diff_b * 312) + (*diff_b >> 1)) >> 12; /* @312.5/2^12 */
++}
++
++void phydm_soml_debug(void *dm_void, char input[][16], u32 *_used,
++		      char *output, u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++	u32 used = *_used;
++	u32 out_len = *_out_len;
++	u32 dm_value[10] = {0};
++	u8 i = 0, input_idx = 0;
++
++	for (i = 0; i < 5; i++) {
++		if (input[i + 1]) {
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
++			input_idx++;
++		}
++	}
++
++	if (input_idx == 0)
++		return;
++
++	if (dm_value[0] == 1) { /*Turn on/off SOML*/
++		soml_tab->soml_select = (u8)dm_value[1];
++
++	} else if (dm_value[0] == 2) { /*training number for SOML*/
++
++		soml_tab->soml_train_num = (u8)dm_value[1];
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "soml_train_num = ((%d))\n",
++			 soml_tab->soml_train_num);
++	} else if (dm_value[0] == 3) { /*training interval for SOML*/
++
++		soml_tab->soml_intvl = (u8)dm_value[1];
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "soml_intvl = ((%d))\n", soml_tab->soml_intvl);
++	} else if (dm_value[0] == 4) { /*@function period for SOML*/
++
++		soml_tab->soml_period = (u8)dm_value[1];
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "soml_period = ((%d))\n", soml_tab->soml_period);
++	} else if (dm_value[0] == 5) { /*@delay_time for SOML*/
++
++		soml_tab->soml_delay_time = (u8)dm_value[1];
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "soml_delay_time = ((%d))\n",
++			 soml_tab->soml_delay_time);
++	} else if (dm_value[0] == 6) { /* @for SOML Rx QAM distribution th*/
++		if (dm_value[1] == 256) {
++			soml_tab->qam256_dist_th = (u8)dm_value[2];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "qam256_dist_th = ((%d))\n",
++				 soml_tab->qam256_dist_th);
++		} else if (dm_value[1] == 64) {
++			soml_tab->qam64_dist_th = (u8)dm_value[2];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "qam64_dist_th = ((%d))\n",
++				 soml_tab->qam64_dist_th);
++		} else if (dm_value[1] == 16) {
++			soml_tab->qam16_dist_th = (u8)dm_value[2];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "qam16_dist_th = ((%d))\n",
++				 soml_tab->qam16_dist_th);
++		} else if (dm_value[1] == 4) {
++			soml_tab->bpsk_qpsk_dist_th = (u8)dm_value[2];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "bpsk_qpsk_dist_th = ((%d))\n",
++				 soml_tab->bpsk_qpsk_dist_th);
++		}
++	} else if (dm_value[0] == 7) { /* @for SOML cfo th*/
++		if (dm_value[1] == 256) {
++			soml_tab->cfo_qam256_th = (u8)dm_value[2];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "cfo_qam256_th = ((%d KHz))\n",
++				 soml_tab->cfo_qam256_th);
++		} else if (dm_value[1] == 64) {
++			soml_tab->cfo_qam64_th = (u8)dm_value[2];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "cfo_qam64_th = ((%d KHz))\n",
++				 soml_tab->cfo_qam64_th);
++		} else if (dm_value[1] == 16) {
++			soml_tab->cfo_qam16_th = (u8)dm_value[2];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "cfo_qam16_th = ((%d KHz))\n",
++				 soml_tab->cfo_qam16_th);
++		} else if (dm_value[1] == 4) {
++			soml_tab->cfo_qpsk_th = (u8)dm_value[2];
++			PDM_SNPF(out_len, used, output + used, out_len - used,
++				 "cfo_qpsk_th = ((%d KHz))\n",
++				 soml_tab->cfo_qpsk_th);
++		}
++	} else if (dm_value[0] == 100) {
++		/*show parameters*/
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "soml_select = ((%d))\n", soml_tab->soml_select);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "soml_train_num = ((%d))\n",
++			 soml_tab->soml_train_num);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "soml_intvl = ((%d))\n", soml_tab->soml_intvl);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "soml_period = ((%d))\n", soml_tab->soml_period);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "soml_delay_time = ((%d))\n\n",
++			 soml_tab->soml_delay_time);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "qam256_dist_th = ((%d)),  qam64_dist_th = ((%d)), ",
++			 soml_tab->qam256_dist_th,
++			 soml_tab->qam64_dist_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "qam16_dist_th = ((%d)),  bpsk_qpsk_dist_th = ((%d))\n",
++			 soml_tab->qam16_dist_th,
++			 soml_tab->bpsk_qpsk_dist_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "cfo_qam256_th = ((%d KHz)),  cfo_qam64_th = ((%d KHz)), ",
++			 soml_tab->cfo_qam256_th,
++			 soml_tab->cfo_qam64_th);
++		PDM_SNPF(out_len, used, output + used, out_len - used,
++			 "cfo_qam16_th = ((%d KHz)),  cfo_qpsk_th  = ((%d KHz))\n",
++			 soml_tab->cfo_qam16_th,
++			 soml_tab->cfo_qpsk_th);
++	}
++	*_used = used;
++	*_out_len = out_len;
++}
++
++void phydm_soml_stats_ht_on(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++	u8 i, mcs0;
++	u16 num_bytes_diff, num_rate_diff;
++
++	mcs0 = ODM_RATEMCS0;
++	for (i = mcs0; i <= ODM_RATEMCS15; i++) {
++		num_rate_diff = soml_tab->ht_cnt[i - mcs0] -
++				soml_tab->pre_ht_cnt[i - mcs0];
++		soml_tab->ht_cnt_on[i - mcs0] += num_rate_diff;
++		soml_tab->pre_ht_cnt[i - mcs0] = soml_tab->ht_cnt[i - mcs0];
++		num_bytes_diff = soml_tab->ht_byte[i - mcs0] -
++				 soml_tab->pre_ht_byte[i - mcs0];
++		soml_tab->ht_byte_on[i - mcs0] += num_bytes_diff;
++		soml_tab->pre_ht_byte[i - mcs0] = soml_tab->ht_byte[i - mcs0];
++	}
++}
++
++void phydm_soml_stats_ht_off(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++	u8 i, mcs0;
++	u16 num_bytes_diff, num_rate_diff;
++
++	mcs0 = ODM_RATEMCS0;
++	for (i = mcs0; i <= ODM_RATEMCS15; i++) {
++		num_rate_diff = soml_tab->ht_cnt[i - mcs0] -
++				soml_tab->pre_ht_cnt[i - mcs0];
++		soml_tab->ht_cnt_off[i - mcs0] += num_rate_diff;
++		soml_tab->pre_ht_cnt[i - mcs0] = soml_tab->ht_cnt[i - mcs0];
++		num_bytes_diff = soml_tab->ht_byte[i - mcs0] -
++				 soml_tab->pre_ht_byte[i - mcs0];
++		soml_tab->ht_byte_off[i - mcs0] += num_bytes_diff;
++		soml_tab->pre_ht_byte[i - mcs0] = soml_tab->ht_byte[i - mcs0];
++	}
++}
++
++void phydm_soml_stats_vht_on(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++	u8 j, vht0;
++	u16 num_bytes_diff, num_rate_diff;
++
++	vht0 = ODM_RATEVHTSS1MCS0;
++	for (j = vht0; j <= ODM_RATEVHTSS2MCS9; j++) {
++		num_rate_diff = soml_tab->vht_cnt[j - vht0] -
++				soml_tab->pre_vht_cnt[j - vht0];
++		soml_tab->vht_cnt_on[j - vht0] += num_rate_diff;
++		soml_tab->pre_vht_cnt[j - vht0] = soml_tab->vht_cnt[j - vht0];
++		num_bytes_diff = soml_tab->vht_byte[j - vht0] -
++				 soml_tab->pre_vht_byte[j - vht0];
++		soml_tab->vht_byte_on[j - vht0] += num_bytes_diff;
++		soml_tab->pre_vht_byte[j - vht0] = soml_tab->vht_byte[j - vht0];
++	}
++}
++
++void phydm_soml_stats_vht_off(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++	u8 j, vht0;
++	u16 num_bytes_diff, num_rate_diff;
++
++	vht0 = ODM_RATEVHTSS1MCS0;
++	for (j = vht0; j <= ODM_RATEVHTSS2MCS9; j++) {
++		num_rate_diff = soml_tab->vht_cnt[j - vht0] -
++				soml_tab->pre_vht_cnt[j - vht0];
++		soml_tab->vht_cnt_off[j - vht0] += num_rate_diff;
++		soml_tab->pre_vht_cnt[j - vht0] = soml_tab->vht_cnt[j - vht0];
++		num_bytes_diff = soml_tab->vht_byte[j - vht0] -
++				 soml_tab->pre_vht_byte[j - vht0];
++		soml_tab->vht_byte_off[j - vht0] += num_bytes_diff;
++		soml_tab->pre_vht_byte[j - vht0] = soml_tab->vht_byte[j - vht0];
++	}
++}
++
++void phydm_soml_statistics(void *dm_void, u8 on_off_state)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++
++	if (on_off_state == SOML_ON) {
++		if (*dm->channel <= 14)
++			phydm_soml_stats_ht_on(dm);
++		if (dm->support_ic_type == ODM_RTL8822B)
++			phydm_soml_stats_vht_on(dm);
++	} else if (on_off_state == SOML_OFF) {
++		if (*dm->channel <= 14)
++			phydm_soml_stats_ht_off(dm);
++		if (dm->support_ic_type == ODM_RTL8822B)
++			phydm_soml_stats_vht_off(dm);
++	}
++}
++
++void phydm_adsl_init_state(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++
++	u8 next_on_off;
++	u16 ht_reset[HT_RATE_IDX] = {0}, vht_reset[VHT_RATE_IDX] = {0};
++	u8 size = sizeof(ht_reset[0]);
++
++	phydm_soml_reset_rx_rate(dm);
++	odm_move_memory(dm, soml_tab->ht_byte, ht_reset,
++			HT_RATE_IDX * size);
++	odm_move_memory(dm, soml_tab->ht_byte_on, ht_reset,
++			HT_RATE_IDX * size);
++	odm_move_memory(dm, soml_tab->ht_byte_off, ht_reset,
++			HT_RATE_IDX * size);
++	odm_move_memory(dm, soml_tab->vht_byte, vht_reset,
++			VHT_RATE_IDX * size);
++	odm_move_memory(dm, soml_tab->vht_byte_on, vht_reset,
++			VHT_RATE_IDX * size);
++	odm_move_memory(dm, soml_tab->vht_byte_off, vht_reset,
++			VHT_RATE_IDX * size);
++	if (dm->support_ic_type == ODM_RTL8822B) {
++		soml_tab->cfo_cnt++;
++		phydm_soml_cfo_process(dm,
++				       &soml_tab->cfo_diff_a,
++				       &soml_tab->cfo_diff_b);
++		PHYDM_DBG(dm, DBG_ADPTV_SOML,
++			  "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n",
++			  soml_tab->cfo_cnt, soml_tab->cfo_diff_a,
++			  soml_tab->cfo_diff_b);
++		soml_tab->cfo_diff_sum_a += soml_tab->cfo_diff_a;
++		soml_tab->cfo_diff_sum_b += soml_tab->cfo_diff_b;
++	}
++
++	soml_tab->is_soml_method_enable = 1;
++	#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	odm_set_mac_reg(dm, R_0x608, BIT(8), 1);
++	/*RCR accepts CRC32-Error packets*/
++	#endif
++	soml_tab->get_stats = false;
++	soml_tab->soml_state_cnt++;
++	next_on_off = (soml_tab->soml_on_off == SOML_ON) ? SOML_ON : SOML_OFF;
++	phydm_soml_on_off(dm, next_on_off);
++	odm_set_timer(dm, &soml_tab->phydm_adaptive_soml_timer,
++		      soml_tab->soml_delay_time); /*@ms*/
++}
++
++void phydm_adsl_odd_state(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++	u16 ht_reset[HT_RATE_IDX] = {0}, vht_reset[VHT_RATE_IDX] = {0};
++	u8 size = sizeof(ht_reset[0]);
++
++	soml_tab->get_stats = true;
++	soml_tab->soml_state_cnt++;
++	odm_move_memory(dm, soml_tab->pre_ht_cnt, soml_tab->ht_cnt,
++			HT_RATE_IDX * size);
++	odm_move_memory(dm, soml_tab->pre_vht_cnt, soml_tab->vht_cnt,
++			VHT_RATE_IDX * size);
++	odm_move_memory(dm, soml_tab->pre_ht_byte, soml_tab->ht_byte,
++			HT_RATE_IDX * size);
++	odm_move_memory(dm, soml_tab->pre_vht_byte, soml_tab->vht_byte,
++			VHT_RATE_IDX * size);
++
++	if (dm->support_ic_type == ODM_RTL8822B) {
++		soml_tab->cfo_cnt++;
++		phydm_soml_cfo_process(dm,
++				       &soml_tab->cfo_diff_a,
++				       &soml_tab->cfo_diff_b);
++		PHYDM_DBG(dm, DBG_ADPTV_SOML,
++			  "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n",
++			  soml_tab->cfo_cnt, soml_tab->cfo_diff_a,
++			  soml_tab->cfo_diff_b);
++		soml_tab->cfo_diff_sum_a += soml_tab->cfo_diff_a;
++		soml_tab->cfo_diff_sum_b += soml_tab->cfo_diff_b;
++	}
++	odm_set_timer(dm, &soml_tab->phydm_adaptive_soml_timer,
++		      soml_tab->soml_intvl); /*@ms*/
++}
++
++void phydm_adsl_even_state(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++	u8 next_on_off;
++
++	soml_tab->get_stats = false;
++	if (dm->support_ic_type == ODM_RTL8822B) {
++		soml_tab->cfo_cnt++;
++		phydm_soml_cfo_process(dm,
++				       &soml_tab->cfo_diff_a,
++				       &soml_tab->cfo_diff_b);
++		PHYDM_DBG(dm, DBG_ADPTV_SOML,
++			  "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n",
++			  soml_tab->cfo_cnt, soml_tab->cfo_diff_a,
++			  soml_tab->cfo_diff_b);
++		soml_tab->cfo_diff_sum_a += soml_tab->cfo_diff_a;
++		soml_tab->cfo_diff_sum_b += soml_tab->cfo_diff_b;
++	}
++	soml_tab->soml_state_cnt++;
++	phydm_soml_statistics(dm, soml_tab->soml_on_off);
++	next_on_off = (soml_tab->soml_on_off == SOML_ON) ? SOML_OFF : SOML_ON;
++	phydm_soml_on_off(dm, next_on_off);
++	odm_set_timer(dm, &soml_tab->phydm_adaptive_soml_timer,
++		      soml_tab->soml_delay_time); /*@ms*/
++}
++
++void phydm_adsl_decision_state(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++	boolean on_above = false, off_above = false;
++	u8 i, max_idx_on = 0, max_idx_off = 0;
++	u8 next_on_off = soml_tab->soml_last_state;
++	u8 mcs0 = ODM_RATEMCS0, vht0 = ODM_RATEVHTSS1MCS0;
++	u8 crc_taget = soml_tab->soml_last_state;
++	u8 rate_num = 1, ss_shift = 0;
++	u16 ht_ok_max_on = 0, ht_fail_max_on = 0, utility_on = 0;
++	u16 ht_ok_max_off = 0, ht_fail_max_off = 0, utility_off = 0;
++	u16 vht_ok_max_on = 0, vht_fail_max_on = 0;
++	u16 vht_ok_max_off = 0, vht_fail_max_off = 0;
++	u16 num_total_qam = 0;
++	u16 cnt_max_on = 0, cnt_max_off = 0;
++	u32 ht_total_cnt_on = 0, ht_total_cnt_off = 0;
++	u32 total_ht_rate_on = 0, total_ht_rate_off = 0;
++	u32 vht_total_cnt_on = 0, vht_total_cnt_off = 0;
++	u32 total_vht_rate_on = 0, total_vht_rate_off = 0;
++	u32 rate_per_pkt_on = 0, rate_per_pkt_off = 0;
++	s32 cfo_diff_avg_a, cfo_diff_avg_b;
++	u16 vht_phy_rate_table[] = {
++		/*@20M*/
++		6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1SS MCS0~9*/
++		13, 26, 39, 52, 78, 104, 117, 130, 156, 180 /*@2SSMCS0~9*/
++	};
++
++	if (dm->support_ic_type & ODM_IC_1SS)
++		rate_num = 1;
++	#ifdef PHYDM_COMPILE_ABOVE_2SS
++	else if (dm->support_ic_type & ODM_IC_2SS)
++		rate_num = 2;
++	#endif
++	#ifdef PHYDM_COMPILE_ABOVE_3SS
++	else if (dm->support_ic_type & ODM_IC_3SS)
++		rate_num = 3;
++	#endif
++	#ifdef PHYDM_COMPILE_ABOVE_4SS
++	else if (dm->support_ic_type & ODM_IC_4SS)
++		rate_num = 4;
++	#endif
++	else
++		pr_debug("%s: mismatch IC type %x\n", __func__,
++			 dm->support_ic_type);
++	soml_tab->get_stats = false;
++	#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	odm_set_mac_reg(dm, R_0x608, BIT(8), 0);
++	/* NOT Accept CRC32 Error packets. */
++	#endif
++	PHYDM_DBG(dm, DBG_ADPTV_SOML, "[Decisoin state ]\n");
++	phydm_soml_statistics(dm, soml_tab->soml_on_off);
++	if (*dm->channel <= 14) {
++		/* @[Search 1st and 2nd rate by counter] */
++		for (i = 0; i < rate_num; i++) {
++			ss_shift = (i << 3);
++			PHYDM_DBG(dm, DBG_ADPTV_SOML,
++				  "*ht_cnt_on  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
++				  (ss_shift), (ss_shift + 7),
++				  soml_tab->ht_cnt_on[ss_shift + 0],
++				  soml_tab->ht_cnt_on[ss_shift + 1],
++				  soml_tab->ht_cnt_on[ss_shift + 2],
++				  soml_tab->ht_cnt_on[ss_shift + 3],
++				  soml_tab->ht_cnt_on[ss_shift + 4],
++				  soml_tab->ht_cnt_on[ss_shift + 5],
++				  soml_tab->ht_cnt_on[ss_shift + 6],
++				  soml_tab->ht_cnt_on[ss_shift + 7]);
++		}
++
++		for (i = 0; i < rate_num; i++) {
++			ss_shift = (i << 3);
++			PHYDM_DBG(dm, DBG_ADPTV_SOML,
++				  "*ht_cnt_off  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
++				  (ss_shift), (ss_shift + 7),
++				  soml_tab->ht_cnt_off[ss_shift + 0],
++				  soml_tab->ht_cnt_off[ss_shift + 1],
++				  soml_tab->ht_cnt_off[ss_shift + 2],
++				  soml_tab->ht_cnt_off[ss_shift + 3],
++				  soml_tab->ht_cnt_off[ss_shift + 4],
++				  soml_tab->ht_cnt_off[ss_shift + 5],
++				  soml_tab->ht_cnt_off[ss_shift + 6],
++				  soml_tab->ht_cnt_off[ss_shift + 7]);
++		}
++
++		for (i = 0; i < rate_num; i++) {
++			ss_shift = (i << 3);
++			PHYDM_DBG(dm, DBG_ADPTV_SOML,
++				  "*ht_crc_ok_cnt_on  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
++				  (ss_shift), (ss_shift + 7),
++				  soml_tab->ht_crc_ok_cnt_on[ss_shift + 0],
++				  soml_tab->ht_crc_ok_cnt_on[ss_shift + 1],
++				  soml_tab->ht_crc_ok_cnt_on[ss_shift + 2],
++				  soml_tab->ht_crc_ok_cnt_on[ss_shift + 3],
++				  soml_tab->ht_crc_ok_cnt_on[ss_shift + 4],
++				  soml_tab->ht_crc_ok_cnt_on[ss_shift + 5],
++				  soml_tab->ht_crc_ok_cnt_on[ss_shift + 6],
++				  soml_tab->ht_crc_ok_cnt_on[ss_shift + 7]);
++		}
++
++		for (i = 0; i < rate_num; i++) {
++			ss_shift = (i << 3);
++			PHYDM_DBG(dm, DBG_ADPTV_SOML,
++				  "*ht_crc_fail_cnt_on  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
++				  (ss_shift), (ss_shift + 7),
++				  soml_tab->ht_crc_fail_cnt_on[ss_shift + 0],
++				  soml_tab->ht_crc_fail_cnt_on[ss_shift + 1],
++				  soml_tab->ht_crc_fail_cnt_on[ss_shift + 2],
++				  soml_tab->ht_crc_fail_cnt_on[ss_shift + 3],
++				  soml_tab->ht_crc_fail_cnt_on[ss_shift + 4],
++				  soml_tab->ht_crc_fail_cnt_on[ss_shift + 5],
++				  soml_tab->ht_crc_fail_cnt_on[ss_shift + 6],
++				  soml_tab->ht_crc_fail_cnt_on[ss_shift + 7]);
++		}
++
++		for (i = 0; i < rate_num; i++) {
++			ss_shift = (i << 3);
++			PHYDM_DBG(dm, DBG_ADPTV_SOML,
++				  "*ht_crc_ok_cnt_off  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
++				  (ss_shift), (ss_shift + 7),
++				  soml_tab->ht_crc_ok_cnt_off[ss_shift + 0],
++				  soml_tab->ht_crc_ok_cnt_off[ss_shift + 1],
++				  soml_tab->ht_crc_ok_cnt_off[ss_shift + 2],
++				  soml_tab->ht_crc_ok_cnt_off[ss_shift + 3],
++				  soml_tab->ht_crc_ok_cnt_off[ss_shift + 4],
++				  soml_tab->ht_crc_ok_cnt_off[ss_shift + 5],
++				  soml_tab->ht_crc_ok_cnt_off[ss_shift + 6],
++				  soml_tab->ht_crc_ok_cnt_off[ss_shift + 7]);
++		}
++
++		for (i = 0; i < rate_num; i++) {
++			ss_shift = (i << 3);
++			PHYDM_DBG(dm, DBG_ADPTV_SOML,
++				  "*ht_crc_fail_cnt_off  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
++				  (ss_shift), (ss_shift + 7),
++				  soml_tab->ht_crc_fail_cnt_off[ss_shift + 0],
++				  soml_tab->ht_crc_fail_cnt_off[ss_shift + 1],
++				  soml_tab->ht_crc_fail_cnt_off[ss_shift + 2],
++				  soml_tab->ht_crc_fail_cnt_off[ss_shift + 3],
++				  soml_tab->ht_crc_fail_cnt_off[ss_shift + 4],
++				  soml_tab->ht_crc_fail_cnt_off[ss_shift + 5],
++				  soml_tab->ht_crc_fail_cnt_off[ss_shift + 6],
++				  soml_tab->ht_crc_fail_cnt_off[ss_shift + 7]);
++		}
++		for (i = ODM_RATEMCS0; i <= ODM_RATEMCS15; i++) {
++			ht_total_cnt_on += soml_tab->ht_cnt_on[i - mcs0];
++			ht_total_cnt_off += soml_tab->ht_cnt_off[i - mcs0];
++			total_ht_rate_on += (soml_tab->ht_cnt_on[i - mcs0] *
++					    phy_rate_table[i]);
++			total_ht_rate_off += (soml_tab->ht_cnt_off[i - mcs0] *
++					     phy_rate_table[i]);
++			if (soml_tab->ht_cnt_on[i - mcs0] > cnt_max_on) {
++				cnt_max_on = soml_tab->ht_cnt_on[i - mcs0];
++				max_idx_on = i - mcs0;
++			}
++
++			if (soml_tab->ht_cnt_off[i - mcs0] > cnt_max_off) {
++				cnt_max_off = soml_tab->ht_cnt_off[i - mcs0];
++				max_idx_off = i - mcs0;
++			}
++		}
++		total_ht_rate_on = total_ht_rate_on << 3;
++		total_ht_rate_off = total_ht_rate_off << 3;
++		rate_per_pkt_on = (ht_total_cnt_on != 0) ?
++				  (total_ht_rate_on / ht_total_cnt_on) : 0;
++		rate_per_pkt_off = (ht_total_cnt_off != 0) ?
++				   (total_ht_rate_off / ht_total_cnt_off) : 0;
++		#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++		ht_ok_max_on = soml_tab->ht_crc_ok_cnt_on[max_idx_on];
++		ht_fail_max_on = soml_tab->ht_crc_fail_cnt_on[max_idx_on];
++		ht_ok_max_off = soml_tab->ht_crc_ok_cnt_off[max_idx_off];
++		ht_fail_max_off = soml_tab->ht_crc_fail_cnt_off[max_idx_off];
++
++		if (ht_fail_max_on == 0)
++			ht_fail_max_on = 1;
++
++		if (ht_fail_max_off == 0)
++			ht_fail_max_off = 1;
++
++		if (ht_ok_max_on > ht_fail_max_on)
++			on_above = true;
++
++		if (ht_ok_max_off > ht_fail_max_off)
++			off_above = true;
++
++		if (on_above && !off_above) {
++			crc_taget = SOML_ON;
++		} else if (!on_above && off_above) {
++			crc_taget = SOML_OFF;
++		} else if (on_above && off_above) {
++			utility_on = (ht_ok_max_on << 7) / ht_fail_max_on;
++			utility_off = (ht_ok_max_off << 7) / ht_fail_max_off;
++			crc_taget = (utility_on == utility_off) ?
++				    (soml_tab->soml_last_state) :
++				    ((utility_on > utility_off) ? SOML_ON :
++				    SOML_OFF);
++
++		} else if (!on_above && !off_above) {
++			if (ht_ok_max_on == 0)
++				ht_ok_max_on = 1;
++			if (ht_ok_max_off == 0)
++				ht_ok_max_off = 1;
++			utility_on = (ht_fail_max_on << 7) / ht_ok_max_on;
++			utility_off = (ht_fail_max_off << 7) / ht_ok_max_off;
++			crc_taget = (utility_on == utility_off) ?
++				    (soml_tab->soml_last_state) :
++				    ((utility_on < utility_off) ? SOML_ON :
++				    SOML_OFF);
++		}
++		#endif
++	} else if (dm->support_ic_type == ODM_RTL8822B) {
++		cfo_diff_avg_a = soml_tab->cfo_diff_sum_a / soml_tab->cfo_cnt;
++		cfo_diff_avg_b = soml_tab->cfo_diff_sum_b / soml_tab->cfo_cnt;
++		soml_tab->cfo_diff_avg_a = (soml_tab->cfo_cnt != 0) ?
++					   cfo_diff_avg_a : 0;
++		soml_tab->cfo_diff_avg_b = (soml_tab->cfo_cnt != 0) ?
++					   cfo_diff_avg_b : 0;
++		PHYDM_DBG(dm, DBG_ADPTV_SOML,
++			  "[ cfo_diff_avg_a = %d KHz; cfo_diff_avg_b = %d KHz]\n",
++			  soml_tab->cfo_diff_avg_a,
++			  soml_tab->cfo_diff_avg_b);
++		for (i = 0; i < VHT_ORDER_TYPE; i++)
++			num_total_qam += soml_tab->num_vht_qam[i];
++
++		PHYDM_DBG(dm, DBG_ADPTV_SOML,
++			  "[ ((2SS)) BPSK_QPSK_count = %d ; 16QAM_count = %d ; 64QAM_count = %d ; 256QAM_count = %d ; num_total_qam = %d]\n",
++			  soml_tab->num_vht_qam[BPSK_QPSK],
++			  soml_tab->num_vht_qam[QAM16],
++			  soml_tab->num_vht_qam[QAM64],
++			  soml_tab->num_vht_qam[QAM256],
++			  num_total_qam);
++		if (((soml_tab->num_vht_qam[QAM256] * 100) >
++		    (num_total_qam * soml_tab->qam256_dist_th)) &&
++		    cfo_diff_avg_a > soml_tab->cfo_qam256_th &&
++		    cfo_diff_avg_b > soml_tab->cfo_qam256_th) {
++			PHYDM_DBG(dm, DBG_ADPTV_SOML,
++				  "[  QAM256_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n",
++				  soml_tab->qam256_dist_th,
++				  soml_tab->cfo_qam256_th);
++			PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : ");
++			phydm_soml_on_off(dm, SOML_OFF);
++			return;
++		} else if (((soml_tab->num_vht_qam[QAM64] * 100) >
++			   (num_total_qam * soml_tab->qam64_dist_th)) &&
++			   (cfo_diff_avg_a > soml_tab->cfo_qam64_th) &&
++			   (cfo_diff_avg_b > soml_tab->cfo_qam64_th)) {
++			PHYDM_DBG(dm, DBG_ADPTV_SOML,
++				  "[  QAM64_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n",
++				  soml_tab->qam64_dist_th,
++				  soml_tab->cfo_qam64_th);
++			PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : ");
++			phydm_soml_on_off(dm, SOML_OFF);
++			return;
++		} else if (((soml_tab->num_vht_qam[QAM16] * 100) >
++			   (num_total_qam * soml_tab->qam16_dist_th)) &&
++			   (cfo_diff_avg_a > soml_tab->cfo_qam16_th) &&
++			   (cfo_diff_avg_b > soml_tab->cfo_qam16_th)) {
++			PHYDM_DBG(dm, DBG_ADPTV_SOML,
++				  "[  QAM16_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n",
++				  soml_tab->qam16_dist_th,
++				  soml_tab->cfo_qam16_th);
++			PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : ");
++			phydm_soml_on_off(dm, SOML_OFF);
++			return;
++		} else if (((soml_tab->num_vht_qam[BPSK_QPSK] * 100) >
++			   (num_total_qam * soml_tab->bpsk_qpsk_dist_th)) &&
++			   (cfo_diff_avg_a > soml_tab->cfo_qpsk_th) &&
++			   (cfo_diff_avg_b > soml_tab->cfo_qpsk_th)) {
++			PHYDM_DBG(dm, DBG_ADPTV_SOML,
++				  "[  BPSK_QPSK_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n",
++				  soml_tab->bpsk_qpsk_dist_th,
++				  soml_tab->cfo_qpsk_th);
++			PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : ");
++			phydm_soml_on_off(dm, SOML_OFF);
++			return;
++		}
++
++		for (i = 0; i < rate_num; i++) {
++			ss_shift = 10 * i;
++			PHYDM_DBG(dm, DBG_ADPTV_SOML,
++				  "[  vht_cnt_on  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n",
++				  (i + 1),
++				  soml_tab->vht_cnt_on[ss_shift + 0],
++				  soml_tab->vht_cnt_on[ss_shift + 1],
++				  soml_tab->vht_cnt_on[ss_shift + 2],
++				  soml_tab->vht_cnt_on[ss_shift + 3],
++				  soml_tab->vht_cnt_on[ss_shift + 4],
++				  soml_tab->vht_cnt_on[ss_shift + 5],
++				  soml_tab->vht_cnt_on[ss_shift + 6],
++				  soml_tab->vht_cnt_on[ss_shift + 7],
++				  soml_tab->vht_cnt_on[ss_shift + 8],
++				  soml_tab->vht_cnt_on[ss_shift + 9]);
++		}
++
++		for (i = 0; i < rate_num; i++) {
++			ss_shift = 10 * i;
++			PHYDM_DBG(dm, DBG_ADPTV_SOML,
++				  "[  vht_cnt_off  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n",
++				  (i + 1),
++				  soml_tab->vht_cnt_off[ss_shift + 0],
++				  soml_tab->vht_cnt_off[ss_shift + 1],
++				  soml_tab->vht_cnt_off[ss_shift + 2],
++				  soml_tab->vht_cnt_off[ss_shift + 3],
++				  soml_tab->vht_cnt_off[ss_shift + 4],
++				  soml_tab->vht_cnt_off[ss_shift + 5],
++				  soml_tab->vht_cnt_off[ss_shift + 6],
++				  soml_tab->vht_cnt_off[ss_shift + 7],
++				  soml_tab->vht_cnt_off[ss_shift + 8],
++				  soml_tab->vht_cnt_off[ss_shift + 9]);
++		}
++
++		for (i = 0; i < rate_num; i++) {
++			ss_shift = 10 * i;
++			PHYDM_DBG(dm, DBG_ADPTV_SOML,
++				  "*vht_crc_ok_cnt_on  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
++				  (i + 1),
++				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 0],
++				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 1],
++				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 2],
++				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 3],
++				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 4],
++				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 5],
++				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 6],
++				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 7],
++				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 8],
++				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 9]);
++		}
++		for (i = 0; i < rate_num; i++) {
++			ss_shift = 10 * i;
++			PHYDM_DBG(dm, DBG_ADPTV_SOML,
++				  "*vht_crc_fail_cnt_on  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
++				  (i + 1),
++				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 0],
++				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 1],
++				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 2],
++				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 3],
++				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 4],
++				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 5],
++				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 6],
++				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 7],
++				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 8],
++				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 9]);
++		}
++		for (i = 0; i < rate_num; i++) {
++			ss_shift = 10 * i;
++			PHYDM_DBG(dm, DBG_ADPTV_SOML,
++				  "*vht_crc_ok_cnt_off  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
++				  (i + 1),
++				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 0],
++				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 1],
++				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 2],
++				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 3],
++				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 4],
++				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 5],
++				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 6],
++				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 7],
++				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 8],
++				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 9]);
++		}
++		for (i = 0; i < rate_num; i++) {
++			ss_shift = 10 * i;
++			PHYDM_DBG(dm, DBG_ADPTV_SOML,
++				  "*vht_crc_fail_cnt_off  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
++				  (i + 1),
++				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 0],
++				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 1],
++				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 2],
++				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 3],
++				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 4],
++				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 5],
++				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 6],
++				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 7],
++				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 8],
++				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 9]);
++		}
++
++		for (i = ODM_RATEVHTSS2MCS0; i <= ODM_RATEVHTSS2MCS9; i++) {
++			vht_total_cnt_on += soml_tab->vht_cnt_on[i - vht0];
++			vht_total_cnt_off += soml_tab->vht_cnt_off[i - vht0];
++			total_vht_rate_on += (soml_tab->vht_cnt_on[i - vht0] *
++					     vht_phy_rate_table[i - vht0]);
++			total_vht_rate_off += (soml_tab->vht_cnt_off[i - vht0] *
++					      vht_phy_rate_table[i - vht0]);
++
++			if (soml_tab->vht_cnt_on[i - vht0] > cnt_max_on) {
++				cnt_max_on = soml_tab->vht_cnt_on[i - vht0];
++				max_idx_on = i - vht0;
++			}
++
++			if (soml_tab->vht_cnt_off[i - vht0] > cnt_max_off) {
++				cnt_max_off = soml_tab->vht_cnt_off[i - vht0];
++				max_idx_off = i - vht0;
++			}
++		}
++		total_vht_rate_on = total_vht_rate_on << 3;
++		total_vht_rate_off = total_vht_rate_off << 3;
++		rate_per_pkt_on = (vht_total_cnt_on != 0) ?
++				  (total_vht_rate_on / vht_total_cnt_on) : 0;
++		rate_per_pkt_off = (vht_total_cnt_off != 0) ?
++				   (total_vht_rate_off / vht_total_cnt_off) : 0;
++		#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++		vht_ok_max_on = soml_tab->vht_crc_ok_cnt_on[max_idx_on];
++		vht_fail_max_on = soml_tab->vht_crc_fail_cnt_on[max_idx_on];
++		vht_ok_max_off = soml_tab->vht_crc_ok_cnt_off[max_idx_off];
++		vht_fail_max_off = soml_tab->vht_crc_fail_cnt_off[max_idx_off];
++
++		if (vht_fail_max_on == 0)
++			vht_fail_max_on = 1;
++
++		if (vht_fail_max_off == 0)
++			vht_fail_max_off = 1;
++
++		if (vht_ok_max_on > vht_fail_max_on)
++			on_above = true;
++
++		if (vht_ok_max_off > vht_fail_max_off)
++			off_above = true;
++
++		if (on_above && !off_above) {
++			crc_taget = SOML_ON;
++		} else if (!on_above && off_above) {
++			crc_taget = SOML_OFF;
++		} else if (on_above && off_above) {
++			utility_on = (vht_ok_max_on << 7) / vht_fail_max_on;
++			utility_off = (vht_ok_max_off << 7) / vht_fail_max_off;
++			crc_taget = (utility_on == utility_off) ?
++				    (soml_tab->soml_last_state) :
++				    ((utility_on > utility_off) ? SOML_ON :
++				    SOML_OFF);
++
++		} else if (!on_above && !off_above) {
++			if (vht_ok_max_on == 0)
++				vht_ok_max_on = 1;
++			if (vht_ok_max_off == 0)
++				vht_ok_max_off = 1;
++			utility_on = (vht_fail_max_on << 7) / vht_ok_max_on;
++			utility_off = (vht_fail_max_off << 7) / vht_ok_max_off;
++			crc_taget = (utility_on == utility_off) ?
++				    (soml_tab->soml_last_state) :
++				    ((utility_on < utility_off) ? SOML_ON :
++				    SOML_OFF);
++		}
++		#endif
++
++	}
++
++	/* @[Decision] */
++	PHYDM_DBG(dm, DBG_ADPTV_SOML,
++		  "[  rate_per_pkt_on = %d ; rate_per_pkt_off = %d ]\n",
++		  rate_per_pkt_on, rate_per_pkt_off);
++	#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	if (max_idx_on == max_idx_off && max_idx_on != 0) {
++		PHYDM_DBG(dm, DBG_ADPTV_SOML,
++			  "[ max_idx_on == max_idx_off ]\n");
++		PHYDM_DBG(dm, DBG_ADPTV_SOML,
++			  "[ max_idx = %d, crc_utility_on = %d, crc_utility_off = %d, crc_target = %d]\n",
++			  max_idx_on, utility_on, utility_off,
++			  crc_taget);
++		next_on_off = crc_taget;
++	} else
++	#endif
++	if (rate_per_pkt_on > rate_per_pkt_off) {
++		next_on_off = SOML_ON;
++		PHYDM_DBG(dm, DBG_ADPTV_SOML,
++			  "[ rate_per_pkt_on > rate_per_pkt_off ==> SOML_ON ]\n");
++	} else if (rate_per_pkt_on < rate_per_pkt_off) {
++		next_on_off = SOML_OFF;
++		PHYDM_DBG(dm, DBG_ADPTV_SOML,
++			  "[ rate_per_pkt_on < rate_per_pkt_off ==> SOML_OFF ]\n");
++	} else {
++		PHYDM_DBG(dm, DBG_ADPTV_SOML,
++			  "[ stay at soml_last_state ]\n");
++		next_on_off = soml_tab->soml_last_state;
++	}
++
++	PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : ");
++	phydm_soml_on_off(dm, next_on_off);
++	soml_tab->soml_last_state = next_on_off;
++}
++
++void phydm_adsl(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++
++	if (dm->support_ic_type & PHYDM_ADAPTIVE_SOML_IC) {
++		PHYDM_DBG(dm, DBG_ADPTV_SOML, "soml_state_cnt =((%d))\n",
++			  soml_tab->soml_state_cnt);
++		/*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)===============*/
++		if (soml_tab->soml_state_cnt <
++		    (soml_tab->soml_train_num << 1)) {
++			if (soml_tab->soml_state_cnt == 0)
++				phydm_adsl_init_state(dm);
++			else if ((soml_tab->soml_state_cnt % 2) != 0)
++				phydm_adsl_odd_state(dm);
++			else if ((soml_tab->soml_state_cnt % 2) == 0)
++				phydm_adsl_even_state(dm);
++		} else {
++			phydm_adsl_decision_state(dm);
++		}
++	}
++}
++
++void phydm_adaptive_soml_reset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++
++	soml_tab->soml_state_cnt = 0;
++	soml_tab->is_soml_method_enable = 0;
++	soml_tab->soml_counter = 0;
++}
++
++void phydm_set_adsl_val(void *dm_void, u32 *val_buf, u8 val_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (val_len != 1) {
++		PHYDM_DBG(dm, ODM_COMP_API, "[Error][ADSL]Need val_len=1\n");
++		return;
++	}
++
++	phydm_soml_on_off(dm, (u8)val_buf[1]);
++}
++
++void phydm_soml_crc_acq(void *dm_void, u8 rate_id, boolean crc32, u32 length)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++	u8 offset = 0;
++
++	if (!soml_tab->get_stats)
++		return;
++	if (length < 1400)
++		return;
++
++	if (soml_tab->soml_on_off == SOML_ON) {
++		if (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS15) {
++			offset = rate_id - ODM_RATEMCS0;
++			if (crc32 == CRC_OK)
++				soml_tab->ht_crc_ok_cnt_on[offset]++;
++			else if (crc32 == CRC_FAIL)
++				soml_tab->ht_crc_fail_cnt_on[offset]++;
++		} else if (rate_id >= ODM_RATEVHTSS1MCS0 &&
++			   rate_id <= ODM_RATEVHTSS2MCS9) {
++			offset = rate_id - ODM_RATEVHTSS1MCS0;
++			if (crc32 == CRC_OK)
++				soml_tab->vht_crc_ok_cnt_on[offset]++;
++			else if (crc32 == CRC_FAIL)
++				soml_tab->vht_crc_fail_cnt_on[offset]++;
++		}
++	} else if (soml_tab->soml_on_off == SOML_OFF) {
++		if (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS15) {
++			offset = rate_id - ODM_RATEMCS0;
++			if (crc32 == CRC_OK)
++				soml_tab->ht_crc_ok_cnt_off[offset]++;
++			else if (crc32 == CRC_FAIL)
++				soml_tab->ht_crc_fail_cnt_off[offset]++;
++		} else if (rate_id >= ODM_RATEVHTSS1MCS0 &&
++			   rate_id <= ODM_RATEVHTSS2MCS9) {
++			offset = rate_id - ODM_RATEVHTSS1MCS0;
++			if (crc32 == CRC_OK)
++				soml_tab->vht_crc_ok_cnt_off[offset]++;
++			else if (crc32 == CRC_FAIL)
++				soml_tab->vht_crc_fail_cnt_off[offset]++;
++		}
++	}
++}
++
++void phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++	u8 offset = 0;
++
++
++	if (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS31) {
++		offset = rate_id - ODM_RATEMCS0;
++		if (offset > (HT_RATE_IDX - 1))
++			offset = HT_RATE_IDX - 1;
++
++		soml_tab->ht_byte[offset] += (u16)length;
++	} else if (rate_id >= ODM_RATEVHTSS1MCS0 &&
++		   rate_id <= ODM_RATEVHTSS4MCS9) {
++		offset = rate_id - ODM_RATEVHTSS1MCS0;
++		if (offset > (VHT_RATE_IDX - 1))
++			offset = VHT_RATE_IDX - 1;
++
++		soml_tab->vht_byte[offset] += (u16)length;
++	}
++}
++
++#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
++static void pre_phydm_adaptive_soml_callback(unsigned long task_dm)
++{
++	struct dm_struct *dm = (struct dm_struct *)task_dm;
++	struct rtl8192cd_priv *priv = dm->priv;
++	struct priv_shared_info *pshare = priv->pshare;
++
++	if (!(priv->drv_state & DRV_STATE_OPEN))
++		return;
++	if (pshare->bDriverStopped || pshare->bSurpriseRemoved) {
++		printk("[%s] bDriverStopped(%d) OR bSurpriseRemoved(%d)\n",
++		       __FUNCTION__, pshare->bDriverStopped,
++		       pshare->bSurpriseRemoved);
++		return;
++	}
++
++	rtw_enqueue_timer_event(priv, &pshare->adaptive_soml_event,
++				ENQUEUE_TO_TAIL);
++}
++
++void phydm_adaptive_soml_timers_usb(void *dm_void, u8 state)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++	struct rtl8192cd_priv *priv = dm->priv;
++
++	if (state == INIT_SOML_TIMMER) {
++		init_timer(&soml_tab->phydm_adaptive_soml_timer);
++		soml_tab->phydm_adaptive_soml_timer.data = (unsigned long)dm;
++		soml_tab->phydm_adaptive_soml_timer.function = pre_phydm_adaptive_soml_callback;
++		INIT_TIMER_EVENT_ENTRY(&priv->pshare->adaptive_soml_event,
++				       phydm_adaptive_soml_callback,
++				       (unsigned long)dm);
++	} else if (state == CANCEL_SOML_TIMMER) {
++		odm_cancel_timer(dm, &soml_tab->phydm_adaptive_soml_timer);
++	} else if (state == RELEASE_SOML_TIMMER) {
++		odm_release_timer(dm, &soml_tab->phydm_adaptive_soml_timer);
++	}
++}
++#endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
++
++void phydm_adaptive_soml_timers(void *dm_void, u8 state)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++
++#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
++	struct rtl8192cd_priv *priv = dm->priv;
++
++	if (priv->hci_type == RTL_HCI_USB) {
++		phydm_adaptive_soml_timers_usb(dm_void, state);
++	} else
++#endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
++	{
++	if (state == INIT_SOML_TIMMER) {
++		odm_initialize_timer(dm, &soml_tab->phydm_adaptive_soml_timer,
++				     (void *)phydm_adaptive_soml_callback, NULL,
++				     "phydm_adaptive_soml_timer");
++	} else if (state == CANCEL_SOML_TIMMER) {
++		odm_cancel_timer(dm, &soml_tab->phydm_adaptive_soml_timer);
++	} else if (state == RELEASE_SOML_TIMMER) {
++		odm_release_timer(dm, &soml_tab->phydm_adaptive_soml_timer);
++	}
++	}
++}
++
++void phydm_adaptive_soml_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++#if 0
++	if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) {
++		PHYDM_DBG(dm, DBG_ADPTV_SOML,
++			  "[Return]   Not Support Adaptive SOML\n");
++		return;
++	}
++#endif
++	PHYDM_DBG(dm, DBG_ADPTV_SOML, "%s\n", __func__);
++
++	soml_tab->soml_state_cnt = 0;
++	soml_tab->soml_delay_time = 40;
++	soml_tab->soml_intvl = 150;
++	soml_tab->soml_train_num = 4;
++	soml_tab->is_soml_method_enable = 0;
++	soml_tab->soml_counter = 0;
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++	soml_tab->soml_period = 1;
++#else
++	soml_tab->soml_period = 4;
++#endif
++	soml_tab->soml_select = 0;
++	soml_tab->cfo_cnt = 0;
++	soml_tab->cfo_diff_sum_a = 0;
++	soml_tab->cfo_diff_sum_b = 0;
++
++	soml_tab->cfo_qpsk_th = 94;
++	soml_tab->cfo_qam16_th = 38;
++	soml_tab->cfo_qam64_th = 17;
++	soml_tab->cfo_qam256_th = 7;
++
++	soml_tab->bpsk_qpsk_dist_th = 20;
++	soml_tab->qam16_dist_th = 20;
++	soml_tab->qam64_dist_th = 20;
++	soml_tab->qam256_dist_th = 20;
++
++	if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
++		odm_set_bb_reg(dm, 0x988, BIT(25), 1);
++}
++
++void phydm_adaptive_soml(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++
++	if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) {
++		PHYDM_DBG(dm, DBG_ADPTV_SOML,
++			  "[Return!!!] Not Support Adaptive SOML Function\n");
++		return;
++	}
++
++	if (dm->pause_ability & ODM_BB_ADAPTIVE_SOML) {
++		PHYDM_DBG(dm, DBG_ADPTV_SOML, "Return: Pause ADSL in LV=%d\n",
++			  dm->pause_lv_table.lv_adsl);
++		return;
++	}
++
++	if (soml_tab->soml_counter < soml_tab->soml_period) {
++		soml_tab->soml_counter++;
++		return;
++	}
++	soml_tab->soml_counter = 0;
++	soml_tab->soml_state_cnt = 0;
++	soml_tab->cfo_cnt = 0;
++	soml_tab->cfo_diff_sum_a = 0;
++	soml_tab->cfo_diff_sum_b = 0;
++
++	phydm_soml_reset_qam(dm);
++
++	if (soml_tab->soml_select == 0) {
++		PHYDM_DBG(dm, DBG_ADPTV_SOML,
++			  "[ Adaptive SOML Training !!!]\n");
++	} else if (soml_tab->soml_select == 1) {
++		PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Stop Adaptive SOML !!!]\n");
++		phydm_soml_on_off(dm, SOML_ON);
++		return;
++	} else if (soml_tab->soml_select == 2) {
++		PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Stop Adaptive SOML !!!]\n");
++		phydm_soml_on_off(dm, SOML_OFF);
++		return;
++	}
++
++	if (dm->support_ic_type & PHYDM_ADAPTIVE_SOML_IC)
++		phydm_adsl(dm);
++}
++
++void phydm_enable_adaptive_soml(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_ADPTV_SOML, "[%s]\n", __func__);
++	dm->support_ability |= ODM_BB_ADAPTIVE_SOML;
++	phydm_soml_on_off(dm, SOML_ON);
++}
++
++void phydm_stop_adaptive_soml(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_ADPTV_SOML, "[%s]\n", __func__);
++	dm->support_ability &= ~ODM_BB_ADAPTIVE_SOML;
++	phydm_soml_on_off(dm, SOML_ON);
++}
++
++void phydm_adaptive_soml_para_set(void *dm_void, u8 train_num, u8 intvl,
++				  u8 period, u8 delay_time)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
++
++	soml_tab->soml_train_num = train_num;
++	soml_tab->soml_intvl = intvl;
++	soml_tab->soml_period = period;
++	soml_tab->soml_delay_time = delay_time;
++}
++#endif /* @end of CONFIG_ADAPTIVE_SOML*/
++
++void phydm_init_soft_ml_setting(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 soml_mask = BIT(31) | BIT(30) | BIT(29) | BIT(28);
++
++#if (RTL8822B_SUPPORT == 1)
++	if (!*dm->mp_mode) {
++		if (dm->support_ic_type & ODM_RTL8822B) {
++#if 0
++			/*odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0xd10a0000);*/
++#endif
++			phydm_somlrxhp_setting(dm, true);
++			dm->bsomlenabled = true;
++		}
++	}
++#endif
++#if (RTL8821C_SUPPORT == 1)
++	if (!*dm->mp_mode) {
++		if (dm->support_ic_type & ODM_RTL8821C)
++			odm_set_bb_reg(dm, R_0x19a8, soml_mask, 0xd);
++	}
++#endif
++#if (RTL8195B_SUPPORT == 1)
++	if (!*dm->mp_mode) {
++		if (dm->support_ic_type & ODM_RTL8195B)
++			odm_set_bb_reg(dm, R_0x19a8, soml_mask, 0xd);
++	}
++#endif
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_soml.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_soml.h
+new file mode 100644
+index 000000000..e2c6e17c2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_soml.h
+@@ -0,0 +1,199 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++#ifndef __PHYDMSOML_H__
++#define __PHYDMSOML_H__
++
++/*@#define ADAPTIVE_SOML_VERSION	"1.0" Byte counter version*/
++#define ADAPTIVE_SOML_VERSION "2.0" /*@add avg. phy rate decision 20180126*/
++
++#define PHYDM_ADAPTIVE_SOML_IC	(ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)
++/*@jj add 20170822*/
++
++#define INIT_SOML_TIMMER			0
++#define CANCEL_SOML_TIMMER			1
++#define RELEASE_SOML_TIMMER		2
++
++#define SOML_RSSI_TH_HIGH	25
++#define SOML_RSSI_TH_LOW	20
++
++#define HT_RATE_IDX			16
++#define VHT_RATE_IDX		20
++
++#define HT_ORDER_TYPE		3
++#define VHT_ORDER_TYPE		4
++
++#define CRC_FAIL	1
++#define CRC_OK		0
++
++#if 0
++#define CFO_QPSK_TH			20
++#define CFO_QAM16_TH		20
++#define CFO_QAM64_TH		20
++#define CFO_QAM256_TH		20
++
++#define BPSK_QPSK_DIST		20
++#define QAM16_DIST			30
++#define QAM64_DIST			30
++#define QAM256_DIST			20
++#endif
++#define HT_TYPE		1
++#define VHT_TYPE		2
++
++#define SOML_ON		1
++#define SOML_OFF		0
++
++#ifdef CONFIG_ADAPTIVE_SOML
++
++struct adaptive_soml {
++	u32			rvrt_val; /*all rvrt_val for pause API must set to u32*/
++	boolean			is_soml_method_enable;
++	boolean			get_stats;
++	u8			soml_on_off;
++	u8			soml_state_cnt;
++	u8			soml_delay_time;
++	u8			soml_intvl;
++	u8			soml_train_num;
++	u8			soml_counter;
++	u8			soml_period;
++	u8			soml_select;
++	u8			soml_last_state;
++	u8			cfo_qpsk_th;
++	u8			cfo_qam16_th;
++	u8			cfo_qam64_th;
++	u8			cfo_qam256_th;
++	u8			bpsk_qpsk_dist_th;
++	u8			qam16_dist_th;
++	u8			qam64_dist_th;
++	u8			qam256_dist_th;
++	u8			cfo_cnt;
++	s32			cfo_diff_a;
++	s32			cfo_diff_b;
++	s32			cfo_diff_sum_a;
++	s32			cfo_diff_sum_b;
++	s32			cfo_diff_avg_a;
++	s32			cfo_diff_avg_b;
++	u16			ht_cnt[HT_RATE_IDX];
++	u16			pre_ht_cnt[HT_RATE_IDX];
++	u16			ht_cnt_on[HT_RATE_IDX];
++	u16			ht_cnt_off[HT_RATE_IDX];
++	u16			ht_crc_ok_cnt_on[HT_RATE_IDX];
++	u16			ht_crc_fail_cnt_on[HT_RATE_IDX];
++	u16			ht_crc_ok_cnt_off[HT_RATE_IDX];
++	u16			ht_crc_fail_cnt_off[HT_RATE_IDX];
++	u16			vht_crc_ok_cnt_on[VHT_RATE_IDX];
++	u16			vht_crc_fail_cnt_on[VHT_RATE_IDX];
++	u16			vht_crc_ok_cnt_off[VHT_RATE_IDX];
++	u16			vht_crc_fail_cnt_off[VHT_RATE_IDX];
++
++	u16			vht_cnt[VHT_RATE_IDX];
++	u16			pre_vht_cnt[VHT_RATE_IDX];
++	u16			vht_cnt_on[VHT_RATE_IDX];
++	u16			vht_cnt_off[VHT_RATE_IDX];
++
++	u16			num_ht_qam[HT_ORDER_TYPE];
++	u16			ht_byte[HT_RATE_IDX];
++	u16			pre_ht_byte[HT_RATE_IDX];
++	u16			ht_byte_on[HT_RATE_IDX];
++	u16			ht_byte_off[HT_RATE_IDX];
++	u16			num_vht_qam[VHT_ORDER_TYPE];
++	u16			vht_byte[VHT_RATE_IDX];
++	u16			pre_vht_byte[VHT_RATE_IDX];
++	u16			vht_byte_on[VHT_RATE_IDX];
++	u16			vht_byte_off[VHT_RATE_IDX];
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++#if USE_WORKITEM
++	RT_WORK_ITEM	phydm_adaptive_soml_workitem;
++#endif
++#endif
++	struct phydm_timer_list		phydm_adaptive_soml_timer;
++
++};
++
++enum qam_order {
++	BPSK_QPSK	= 0,
++	QAM16		= 1,
++	QAM64		= 2,
++	QAM256		= 3
++};
++
++void phydm_dynamicsoftmletting(void *dm_void);
++
++void phydm_soml_on_off(void *dm_void, u8 swch);
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void phydm_adaptive_soml_callback(struct phydm_timer_list *timer);
++
++void phydm_adaptive_soml_workitem_callback(void *context);
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++void phydm_adaptive_soml_callback(void *dm_void);
++
++void phydm_adaptive_soml_workitem_callback(void *context);
++
++#else
++void phydm_adaptive_soml_callback(void *dm_void);
++#endif
++
++void phydm_rx_rate_for_soml(void *dm_void, void *pkt_info_void);
++
++void phydm_rx_qam_for_soml(void *dm_void, void *pkt_info_void);
++
++void phydm_soml_reset_rx_rate(void *dm_void);
++
++void phydm_soml_reset_qam(void *dm_void);
++
++void phydm_soml_cfo_process(void *dm_void, s32 *diff_a, s32 *diff_b);
++
++void phydm_soml_debug(void *dm_void, char input[][16], u32 *_used,
++		      char *output, u32 *_out_len);
++
++void phydm_soml_statistics(void *dm_void, u8 on_off_state);
++
++void phydm_adsl(void *dm_void);
++
++void phydm_adaptive_soml_reset(void *dm_void);
++
++void phydm_set_adsl_val(void *dm_void, u32 *val_buf, u8 val_len);
++
++void phydm_soml_crc_acq(void *dm_void, u8 rate_id, boolean crc32, u32 length);
++
++void phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length);
++
++void phydm_adaptive_soml_timers(void *dm_void, u8 state);
++
++void phydm_adaptive_soml_init(void *dm_void);
++
++void phydm_adaptive_soml(void *dm_void);
++
++void phydm_enable_adaptive_soml(void *dm_void);
++
++void phydm_stop_adaptive_soml(void *dm_void);
++
++void phydm_adaptive_soml_para_set(void *dm_void, u8 train_num, u8 intvl,
++				  u8 period, u8 delay_time);
++#endif
++void phydm_init_soft_ml_setting(void *dm_void);
++#endif /*@#ifndef	__PHYDMSOML_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_types.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_types.h
+new file mode 100644
+index 000000000..4db8da5cf
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/phydm_types.h
+@@ -0,0 +1,413 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++#ifndef __ODM_TYPES_H__
++#define __ODM_TYPES_H__
++
++/*Define Different SW team support*/
++#define	ODM_AP			0x01	/*BIT(0)*/
++#define	ODM_CE			0x04	/*BIT(2)*/
++#define	ODM_WIN		0x08	/*BIT(3)*/
++#define	ODM_ADSL		0x10
++/*BIT(4)*/		/*already combine with ODM_AP, and is nouse now*/
++#define	ODM_IOT		0x20	/*BIT(5)*/
++
++/*For FW API*/
++#define	__iram_odm_func__
++#define	__odm_func__
++#define	__odm_func_aon__
++
++/*Deifne HW endian support*/
++#define	ODM_ENDIAN_BIG	0
++#define	ODM_ENDIAN_LITTLE	1
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	#define GET_PDM_ODM(__padapter)	((struct dm_struct*)(&(GET_HAL_DATA(__padapter))->DM_OutSrc))
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	#define GET_PDM_ODM(__padapter)	((struct dm_struct *)(&(GET_HAL_DATA(__padapter))->odmpriv))
++#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	#define GET_PDM_ODM(__padapter)	((struct dm_struct*)(&__padapter->pshare->_dmODM))
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
++	#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
++	/* enable PCI & USB HCI at the same time */
++  	#define RT_PCI_USB_INTERFACE			1
++  	#define	RT_PCI_INTERFACE			RT_PCI_USB_INTERFACE
++	#define RT_USB_INTERFACE			RT_PCI_USB_INTERFACE
++	#define	RT_SDIO_INTERFACE			3
++  	#else
++	#define	RT_PCI_INTERFACE			1
++	#define	RT_USB_INTERFACE			2
++	#define	RT_SDIO_INTERFACE			3
++	#endif
++#endif
++
++enum hal_status {
++	HAL_STATUS_SUCCESS,
++	HAL_STATUS_FAILURE,
++#if 0
++	RT_STATUS_PENDING,
++	RT_STATUS_RESOURCE,
++	RT_STATUS_INVALID_CONTEXT,
++	RT_STATUS_INVALID_PARAMETER,
++	RT_STATUS_NOT_SUPPORT,
++	RT_STATUS_OS_API_FAILED,
++#endif
++};
++
++#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
++
++#define		VISTA_USB_RX_REVISE			0
++
++/*
++ * Declare for ODM spin lock definition temporarily fro compile pass.
++ */
++enum rt_spinlock_type {
++	RT_TX_SPINLOCK = 1,
++	RT_RX_SPINLOCK = 2,
++	RT_RM_SPINLOCK = 3,
++	RT_CAM_SPINLOCK = 4,
++	RT_SCAN_SPINLOCK = 5,
++	RT_LOG_SPINLOCK = 7,
++	RT_BW_SPINLOCK = 8,
++	RT_CHNLOP_SPINLOCK = 9,
++	RT_RF_OPERATE_SPINLOCK = 10,
++	RT_INITIAL_SPINLOCK = 11,
++	RT_RF_STATE_SPINLOCK = 12,
++	/* For RF state. Added by Bruce, 2007-10-30. */
++#if VISTA_USB_RX_REVISE
++	RT_USBRX_CONTEXT_SPINLOCK = 13,
++	RT_USBRX_POSTPROC_SPINLOCK = 14,
++	/* protect data of adapter->IndicateW/ IndicateR */
++#endif
++	/* Shall we define Ndis 6.2 SpinLock Here ? */
++	RT_PORT_SPINLOCK = 16,
++	RT_VNIC_SPINLOCK = 17,
++	RT_HVL_SPINLOCK = 18,
++	RT_H2C_SPINLOCK = 20,
++	/* For H2C cmd. Added by tynli. 2009.11.09. */
++
++	rt_bt_data_spinlock = 25,
++
++	RT_WAPI_OPTION_SPINLOCK = 26,
++	RT_WAPI_RX_SPINLOCK = 27,
++
++	/* add for 92D CCK control issue */
++	RT_CCK_PAGEA_SPINLOCK = 28,
++	RT_BUFFER_SPINLOCK = 29,
++	RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
++	RT_GEN_TEMP_BUF_SPINLOCK = 31,
++	RT_AWB_SPINLOCK = 32,
++	RT_FW_PS_SPINLOCK = 33,
++	RT_HW_TIMER_SPIN_LOCK = 34,
++	RT_MPT_WI_SPINLOCK = 35,
++	RT_P2P_SPIN_LOCK = 36,	/* Protect P2P context */
++	RT_DBG_SPIN_LOCK = 37,
++	RT_IQK_SPINLOCK = 38,
++	RT_PENDED_OID_SPINLOCK = 39,
++	RT_CHNLLIST_SPINLOCK = 40,
++	RT_INDIC_SPINLOCK = 41,	/* protect indication */
++	RT_RFD_SPINLOCK = 42,
++	RT_SYNC_IO_CNT_SPINLOCK = 43,
++	RT_LAST_SPINLOCK,
++};
++
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	#define sta_info 	_RT_WLAN_STA
++	#define	__func__		__FUNCTION__
++	#define	PHYDM_TESTCHIP_SUPPORT	TESTCHIP_SUPPORT
++	#define MASKH3BYTES			0xffffff00
++	#define SUCCESS	0
++	#define FAIL	(-1)
++
++	#define	u8 		u1Byte
++	#define	s8 		s1Byte
++
++	#define	u16		u2Byte
++	#define	s16		s2Byte
++
++	#define	u32 	u4Byte
++	#define	s32 		s4Byte
++
++	#define	u64		u8Byte
++	#define	s64		s8Byte
++
++	#define	phydm_timer_list	_RT_TIMER
++
++	// for power limit table
++	enum odm_pw_lmt_regulation_type {
++		PW_LMT_REGU_FCC = 0,
++		PW_LMT_REGU_ETSI = 1,
++		PW_LMT_REGU_MKK = 2,
++		PW_LMT_REGU_WW13 = 3,
++		PW_LMT_REGU_IC = 4,
++		PW_LMT_REGU_KCC = 5,
++		PW_LMT_REGU_ACMA = 6,
++		PW_LMT_REGU_CHILE = 7,
++		PW_LMT_REGU_UKRAINE = 8,
++		PW_LMT_REGU_MEXICO = 9,
++		PW_LMT_REGU_CN = 10
++	};
++
++	enum odm_pw_lmt_band_type {
++		PW_LMT_BAND_2_4G = 0,
++		PW_LMT_BAND_5G = 1
++	};
++
++	enum odm_pw_lmt_bandwidth_type {
++		PW_LMT_BW_20M = 0,
++		PW_LMT_BW_40M = 1,
++		PW_LMT_BW_80M = 2,
++		PW_LMT_BW_160M = 3
++	};
++
++	enum odm_pw_lmt_ratesection_type {
++		PW_LMT_RS_CCK = 0,
++		PW_LMT_RS_OFDM = 1,
++		PW_LMT_RS_HT = 2,
++		PW_LMT_RS_VHT = 3
++	};
++
++	enum odm_pw_lmt_rfpath_type {
++		PW_LMT_PH_1T = 0,
++		PW_LMT_PH_2T = 1,
++		PW_LMT_PH_3T = 2,
++		PW_LMT_PH_4T = 3
++	};
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++	#include "../typedef.h"
++
++	#ifdef CONFIG_PCI_HCI
++	#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
++		#define DEV_BUS_TYPE		RT_PCI_USB_INTERFACE
++	#else
++		#define DEV_BUS_TYPE		RT_PCI_INTERFACE
++	#endif
++	#endif
++
++	#if (defined(TESTCHIP_SUPPORT))
++		#define	PHYDM_TESTCHIP_SUPPORT 1
++	#else
++		#define	PHYDM_TESTCHIP_SUPPORT 0
++	#endif
++
++	#define	sta_info stat_info
++	#define	boolean	bool
++
++	#define	phydm_timer_list	timer_list
++	#if defined(__ECOS)
++	#define s64	s8Byte
++	#endif 
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
++
++	#include <asm/byteorder.h>
++
++	#define DEV_BUS_TYPE	RT_PCI_INTERFACE
++
++	#if defined(__LITTLE_ENDIAN)
++		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_LITTLE
++	#elif defined(__BIG_ENDIAN)
++		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_BIG
++	#else
++		#error
++	#endif
++
++	/* define useless flag to avoid compile warning */
++	#define	USE_WORKITEM 0
++	#define	FOR_BRAZIL_PRETEST 0
++	#define	FPGA_TWO_MAC_VERIFICATION	0
++	#define	RTL8881A_SUPPORT	0
++	#define	PHYDM_TESTCHIP_SUPPORT 0
++
++
++	#define RATE_ADAPTIVE_SUPPORT			0
++	#define POWER_TRAINING_ACTIVE			0
++
++	#define sta_info	rtl_sta_info
++	#define	boolean		bool
++
++	#define	phydm_timer_list	timer_list
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	#include <drv_types.h>
++
++	#ifdef CONFIG_USB_HCI
++		#define DEV_BUS_TYPE	RT_USB_INTERFACE
++	#elif defined(CONFIG_PCI_HCI)
++		#define DEV_BUS_TYPE	RT_PCI_INTERFACE
++	#elif defined(CONFIG_SDIO_HCI)
++		#define DEV_BUS_TYPE	RT_SDIO_INTERFACE
++	#elif defined(CONFIG_GSPI_HCI)
++		#define DEV_BUS_TYPE	RT_SDIO_INTERFACE
++	#endif
++
++
++	#if defined(CONFIG_LITTLE_ENDIAN)
++		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_LITTLE
++	#elif defined(CONFIG_BIG_ENDIAN)
++		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_BIG
++	#endif
++
++	#define	boolean	bool
++
++	#define SET_TX_DESC_ANTSEL_A_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 8, 24, 1, __value)
++	#define SET_TX_DESC_ANTSEL_B_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 8, 25, 1, __value)
++	#define SET_TX_DESC_ANTSEL_C_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 28, 29, 1, __value)
++
++	/* define useless flag to avoid compile warning */
++	#define	USE_WORKITEM 0
++	#define	FOR_BRAZIL_PRETEST 0
++	#define	FPGA_TWO_MAC_VERIFICATION	0
++	#define	RTL8881A_SUPPORT	0
++
++	#if (defined(TESTCHIP_SUPPORT))
++		#define	PHYDM_TESTCHIP_SUPPORT 1
++	#else
++		#define	PHYDM_TESTCHIP_SUPPORT 0
++	#endif
++
++	#define	phydm_timer_list	rtw_timer_list
++
++	// for power limit table
++	enum odm_pw_lmt_regulation_type {
++		PW_LMT_REGU_FCC = 0,
++		PW_LMT_REGU_ETSI = 1,
++		PW_LMT_REGU_MKK = 2,
++		PW_LMT_REGU_WW13 = 3,
++		PW_LMT_REGU_IC = 4,
++		PW_LMT_REGU_KCC = 5,
++		PW_LMT_REGU_ACMA = 6,
++		PW_LMT_REGU_CHILE = 7,
++		PW_LMT_REGU_UKRAINE = 8,
++		PW_LMT_REGU_MEXICO = 9,
++		PW_LMT_REGU_CN = 10
++	};
++
++	enum odm_pw_lmt_band_type {
++		PW_LMT_BAND_2_4G = 0,
++		PW_LMT_BAND_5G = 1
++	};
++
++	enum odm_pw_lmt_bandwidth_type {
++		PW_LMT_BW_20M = 0,
++		PW_LMT_BW_40M = 1,
++		PW_LMT_BW_80M = 2,
++		PW_LMT_BW_160M = 3
++	};
++
++	enum odm_pw_lmt_ratesection_type {
++		PW_LMT_RS_CCK = 0,
++		PW_LMT_RS_OFDM = 1,
++		PW_LMT_RS_HT = 2,
++		PW_LMT_RS_VHT = 3
++	};
++
++	enum odm_pw_lmt_rfpath_type {
++		PW_LMT_PH_1T = 0,
++		PW_LMT_PH_2T = 1,
++		PW_LMT_PH_3T = 2,
++		PW_LMT_PH_4T = 3
++	};
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
++	#define	boolean	bool
++	#define true	_TRUE
++	#define false	_FALSE
++
++	// for power limit table
++	enum odm_pw_lmt_regulation_type {
++		PW_LMT_REGU_NULL = 0,
++		PW_LMT_REGU_FCC = 1,
++		PW_LMT_REGU_ETSI = 2,
++		PW_LMT_REGU_MKK = 3,
++		PW_LMT_REGU_WW13 = 4
++	};
++
++	enum odm_pw_lmt_band_type {
++		PW_LMT_BAND_NULL = 0,
++		PW_LMT_BAND_2_4G = 1,
++		PW_LMT_BAND_5G = 2
++	};
++
++	enum odm_pw_lmt_bandwidth_type {
++		PW_LMT_BW_NULL = 0,
++		PW_LMT_BW_20M = 1,
++		PW_LMT_BW_40M = 2,
++		PW_LMT_BW_80M = 3
++	};
++
++	enum odm_pw_lmt_ratesection_type {
++		PW_LMT_RS_NULL = 0,
++		PW_LMT_RS_CCK = 1,
++		PW_LMT_RS_OFDM = 2,
++		PW_LMT_RS_HT = 3,
++		PW_LMT_RS_VHT = 4
++	};
++
++	enum odm_pw_lmt_rfpath_type {
++		PW_LMT_PH_NULL = 0,
++		PW_LMT_PH_1T = 1,
++		PW_LMT_PH_2T = 2,
++		PW_LMT_PH_3T = 3,
++		PW_LMT_PH_4T = 4
++	};
++
++	#define	phydm_timer_list	timer_list
++
++#endif
++
++#define READ_NEXT_PAIR(v1, v2, i) do { if (i + 2 >= array_len) break; i += 2; v1 = array[i]; v2 = array[i + 1]; } while (0)
++#define COND_ELSE  2
++#define COND_ENDIF 3
++
++#define	MASKBYTE0		0xff
++#define	MASKBYTE1		0xff00
++#define	MASKBYTE2		0xff0000
++#define	MASKBYTE3		0xff000000
++#define	MASKHWORD		0xffff0000
++#define	MASKLWORD		0x0000ffff
++#define	MASKDWORD		0xffffffff
++
++#define	MASK7BITS		0x7f
++#define	MASK12BITS		0xfff
++#define	MASKH4BITS		0xf0000000
++#define	MASK20BITS		0xfffff
++#define	MASK24BITS		0xffffff
++#define	MASKOFDM_D		0xffc00000
++#define	MASKCCK			0x3f3f3f3f
++
++#define RFREGOFFSETMASK		0xfffff
++#define RFREG_MASK		0xfffff
++
++#define MASKH3BYTES		0xffffff00
++#define MASKL3BYTES		0x00ffffff
++#define MASKBYTE2HIGHNIBBLE	0x00f00000
++#define MASKBYTE3LOWNIBBLE	0x0f000000
++#define	MASKL3BYTES		0x00ffffff
++
++#endif /* __ODM_TYPES_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/hal8723dreg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/hal8723dreg.h
+new file mode 100644
+index 000000000..437fb4a7b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/hal8723dreg.h
+@@ -0,0 +1,947 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*****************************************************************************
++ *	Copyright(c) 2009,  RealTEK Technology Inc. All Right Reserved.
++ *
++ * Module:	__INC_HAL8723DREG_H
++ *
++ *
++ * Note:	1. Define Mac register address and corresponding bit mask map
++ *
++ *
++ * Export:	Constants, macro, functions(API), global variables(None).
++ *
++ * Abbrev:
++ *
++ * History:
++ *		data		Who		Remark
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8723DREG_H
++#define __INC_HAL8723DREG_H
++
++/*************************************************************
++ *
++ ************************************************************/
++
++/* -----------------------------------------------------
++ *
++ *	0x0000h ~ 0x00FFh	System Configuration
++ *
++ * -----------------------------------------------------
++ */
++#define REG_SYS_ISO_CTRL_8723D 0x0000 /* 2 Byte */
++#define REG_SYS_FUNC_EN_8723D 0x0002 /* 2 Byte */
++#define REG_SYS_PW_CTRL_8723D 0x0004 /* 4 Byte */
++#define REG_SYS_CLKR_8723D 0x0008 /* 2 Byte */
++#define REG_SYS_EEPROM_CTRL_8723D 0x000A /* 2 Byte */
++#define REG_EE_VPD_8723D 0x000C /* 2 Byte */
++#define REG_SYS_SWR_CTRL1_8723D 0x0010 /* 1 Byte */
++#define REG_SYS_SWR_CTRL2_8723D 0x0014 /* 1 Byte */
++#define REG_SYS_SWR_CTRL3_8723D 0x0018 /* 4 Byte */
++#define REG_RSV_CTRL_8723D 0x001C /* 3 Byte */
++#define REG_RF_CTRL_8723D 0x001F /* 1 Byte */
++#define REG_AFE_CTRL1_8723D 0x0024 /* 4 Byte */
++#define REG_AFE_CTRL2_8723D 0x0028 /* 4 Byte */
++#define REG_AFE_CTRL3_8723D 0x002c /* 4 Byte */
++#define REG_EFUSE_CTRL_8723D 0x0030
++#define REG_LDO_EFUSE_CTRL_8723D 0x0034
++#define REG_PWR_DATA_8723D 0x0038
++#define REG_CAL_TIMER_8723D 0x003C
++#define REG_ACLK_MON_8723D 0x003E
++#define REG_GPIO_MUXCFG_8723D 0x0040
++#define REG_GPIO_IO_SEL_8723D 0x0042
++#define REG_MAC_PINMUX_CFG_8723D 0x0043 /* ?????? */
++#define REG_GPIO_PIN_CTRL_8723D 0x0044
++#define REG_GPIO_INTM_8723D 0x0048
++#define BIT_REG_LED_CFG_8723D 0x004C
++#define REG_LEDCFG2_8723D 0x004E /* ?????? */
++#define REG_FSIMR_8723D 0x0050
++#define REG_FSISR_8723D 0x0054
++#define REG_HSIMR_8723D 0x0058
++#define REG_HSISR_8723D 0x005c
++#define REG_GPIO_EXT_CTRL_8723D 0x0060
++#define REG_MULTI_FUNC_CTRL_8723D 0x0068
++#define REG_GPIO_STATUS_8723D 0x006C
++#define REG_SDIO_CTRL_8723D 0x0070
++#define REG_HCI_OPT_CTRL_8723D 0x0074
++#define REG_AFE_CTRL4_8723D 0x0078
++#define REG_LDO_SWR_CTRL_8723D 0x007C
++#define REG_8051FW_CTRL_8723D 0x0080
++#define REG_FW_DBG_STATUS_8723D 0x0088
++#define REG_FW_DBG_CTRL_8723D 0x008F
++#define REG_WLLPS_CTRL_8723D 0x0090
++#define REG_HIMR0_8723D 0x00B0
++#define REG_HISR0_8723D 0x00B4
++#define REG_HIMR1_8723D 0x00B8
++#define REG_HISR1_8723D 0x00BC
++#define REG_PMC_DBG_CTRL2_8723D 0x00CC
++#define REG_EFUSE_BURN_GNT_8723D 0x00CF
++#define REG_XTAL_AAC_8723D 0x00EC
++#define REG_SYS_CFG1_8723D 0x00F0
++#define REG_SYS_CFG2_8723D 0x00FC
++#define REG_ROM_VERSION 0x00FD
++
++/* -----------------------------------------------------
++ *
++ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
++ *
++ * -----------------------------------------------------
++ */
++#define REG_CR_8723D 0x0100
++#define REG_PBP_8723D 0x0104 /* ?????? */
++#define REG_PKT_BUFF_ACCESS_CTRL_8723D 0x0106 /* ?????? */
++#define REG_TRXDMA_CTRL_8723D 0x010C
++#define REG_TRXFF_BNDY_8723D 0x0114
++#define REG_RXFF_PTR_8723D 0x011C
++#define REG_CPWM_8723D 0x012C
++#define REG_FWIMR_8723D 0x0130
++#define REG_FWISR_8723D 0x0134
++#define REG_FTIMR_8723D 0x0138
++#define REG_PKTBUF_DBG_CTRL_8723D 0x0140
++#define REG_RXPKTBUF_CTRL_8723D 0x0142 /* ?????? */
++#define REG_PKTBUF_DBG_DATA_L_8723D 0x0144
++#define REG_PKTBUF_DBG_DATA_H_8723D 0x0148
++
++#define REG_TC0_CTRL_8723D 0x0150
++#define REG_TC1_CTRL_8723D 0x0154
++#define REG_TC2_CTRL_8723D 0x0158
++#define REG_TC3_CTRL_8723D 0x015C
++#define REG_TC4_CTRL_8723D 0x0160
++#define REG_TCUNIT_BASE_8723D 0x0164
++#define REG_RSVD3_8723D 0x0168 /* ????? */
++
++#define REG_C2HEVT_MSG_NORMAL_8723D 0x01A0 /* ?????? */
++#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 /* ?????? */
++#define reg_c2h_evt_cmd_content_88xx 0x01A2 /* ?????? */
++#define REG_C2HEVT_CMD_LEN_88XX 0x01AE /* ?????? */
++#define REG_C2HEVT_CLEAR_8723D 0x01AF /* ?????? */
++#define REG_MCUTST_1_8723D 0x01C0
++#define REG_MCUTST_2_8723D 0x01C4
++#define REG_MCUTST_WOWLAN_8723D 0x01C7 /* ?????? */
++#define REG_FMETHR_8723D 0x01C8
++#define REG_HMETFR_8723D 0x01CC
++#define REG_HMEBOX_0_8723D 0x01D0
++#define REG_HMEBOX_1_8723D 0x01D4
++#define REG_HMEBOX_2_8723D 0x01D8
++#define REG_HMEBOX_3_8723D 0x01DC
++#define REG_LLT_INIT_8723D 0x01E0
++#define REG_HMEBOX_EXT0_8723D 0x01F0 /* ?????? */
++#define REG_HMEBOX_EXT1_8723D 0x01F4 /* ?????? */
++#define REG_HMEBOX_EXT2_8723D 0x01F8 /* ?????? */
++#define REG_HMEBOX_EXT3_8723D 0x01FC /* ?????? */
++
++/* -----------------------------------------------------
++ *
++ *	0x0200h ~ 0x027Fh	TXDMA Configuration
++ *
++ * -----------------------------------------------------
++ */
++#define REG_RQPN_8723D 0x0200
++#define REG_FIFOPAGE_8723D 0x0204
++#define REG_TDECTRL_8723D 0x0208
++#define REG_TXDMA_OFFSET_CHK_8723D 0x020C
++#define REG_TXDMA_STATUS_8723D 0x0210
++#define REG_RQPN_NPQ_8723D 0x0214
++#define REG_AUTO_LLT_8723D 0x0224
++#define REG_DWBCN1_CTRL_8723D 0x0228
++
++/* -----------------------------------------------------
++ *
++ *	0x0280h ~ 0x02FFh	RXDMA Configuration
++ *
++ * -----------------------------------------------------
++ */
++#define REG_RXDMA_AGG_PG_TH_8723D 0x0280
++#define REG_RXPKT_NUM_8723D 0x0284 /* The number of packets in RXPKTBUF. */
++#define REG_RXDMA_CONTROL_8723D 0x0286 /* ?????? Control the RX DMA. */
++#define REG_RXDMA_STATUS_8723D 0x0288
++#define REG_RXDMA_PRO_8723D 0x0290 /* ?????? */
++#define REG_EARLY_MODE_CONTROL_8723D 0x02BC /* ?????? */
++#define REG_RSVD5_8723D 0x02F0 /* ?????? */
++
++/* -----------------------------------------------------
++ *
++ *	0x0300h ~ 0x03FFh	PCIe
++ *
++ * -----------------------------------------------------
++ */
++#define REG_PCIE_CTRL_REG_8723D 0x0300
++#define REG_INT_MIG_8723D 0x0304 /* Interrupt Migration */
++#define REG_BCNQ_TXBD_DESA_8723D 0x0308 /* TX Beacon Descriptor Address */
++#define REG_MGQ_TXBD_DESA_8723D 0x0310 /* TX Manage Queue Descriptor Address */
++#define REG_VOQ_TXBD_DESA_8723D 0x0318 /* TX VO Queue Descriptor Address */
++#define REG_VIQ_TXBD_DESA_8723D 0x0320 /* TX VI Queue Descriptor Address */
++#define REG_BEQ_TXBD_DESA_8723D 0x0328 /* TX BE Queue Descriptor Address */
++#define REG_BKQ_TXBD_DESA_8723D 0x0330 /* TX BK Queue Descriptor Address */
++#define REG_RXQ_RXBD_DESA_8723D 0x0338 /* RX Queue	Descriptor Address */
++#define REG_HI0Q_TXBD_DESA_8723D 0x0340
++#define REG_HI1Q_TXBD_DESA_8723D 0x0348
++#define REG_HI2Q_TXBD_DESA_8723D 0x0350
++#define REG_HI3Q_TXBD_DESA_8723D 0x0358
++#define REG_HI4Q_TXBD_DESA_8723D 0x0360
++#define REG_HI5Q_TXBD_DESA_8723D 0x0368
++#define REG_HI6Q_TXBD_DESA_8723D 0x0370
++#define REG_HI7Q_TXBD_DESA_8723D 0x0378
++#define REG_MGQ_TXBD_NUM_8723D 0x0380
++#define REG_RX_RXBD_NUM_8723D 0x0382
++#define REG_VOQ_TXBD_NUM_8723D 0x0384
++#define REG_VIQ_TXBD_NUM_8723D 0x0386
++#define REG_BEQ_TXBD_NUM_8723D 0x0388
++#define REG_BKQ_TXBD_NUM_8723D 0x038A
++#define REG_HI0Q_TXBD_NUM_8723D 0x038C
++#define REG_HI1Q_TXBD_NUM_8723D 0x038E
++#define REG_HI2Q_TXBD_NUM_8723D 0x0390
++#define REG_HI3Q_TXBD_NUM_8723D 0x0392
++#define REG_HI4Q_TXBD_NUM_8723D 0x0394
++#define REG_HI5Q_TXBD_NUM_8723D 0x0396
++#define REG_HI6Q_TXBD_NUM_8723D 0x0398
++#define REG_HI7Q_TXBD_NUM_8723D 0x039A
++#define REG_TSFTIMER_HCI_8723D 0x039C
++
++/* Read Write Point */
++#define REG_VOQ_TXBD_IDX_8723D 0x03A0
++#define REG_VIQ_TXBD_IDX_8723D 0x03A4
++#define REG_BEQ_TXBD_IDX_8723D 0x03A8
++#define REG_BKQ_TXBD_IDX_8723D 0x03AC
++#define REG_MGQ_TXBD_IDX_8723D 0x03B0
++#define REG_RXQ_TXBD_IDX_8723D 0x03B4
++#define REG_HI0Q_TXBD_IDX_8723D 0x03B8
++#define REG_HI1Q_TXBD_IDX_8723D 0x03BC
++#define REG_HI2Q_TXBD_IDX_8723D 0x03C0
++#define REG_HI3Q_TXBD_IDX_8723D 0x03C4
++#define REG_HI4Q_TXBD_IDX_8723D 0x03C8
++#define REG_HI5Q_TXBD_IDX_8723D 0x03CC
++#define REG_HI6Q_TXBD_IDX_8723D 0x03D0
++#define REG_HI7Q_TXBD_IDX_8723D 0x03D4
++
++#define REG_PCIE_HCPWM_8723DE 0x03D8 /* ?????? */
++#define REG_PCIE_HRPWM_8723DE 0x03DC /* PCIe RPWM */ /* ?????? */
++#define REG_DBI_WDATA_V1_8723D 0x03E8
++#define REG_DBI_RDATA_V1_8723D 0x03EC
++#define REG_DBI_FLAG_V1_8723D 0x03F0
++#define REG_MDIO_V1_8723D 0x03F4
++#define REG_PCIE_MIX_CFG_8723D 0x03F8
++#define REG_HCI_MIX_CFG_8723D 0x03FC
++
++/* -----------------------------------------------------
++ *
++ *	0x0400h ~ 0x047Fh	Protocol Configuration
++ *
++ * -----------------------------------------------------
++ */
++#define REG_TXPKT_EMPTY_8723D 0x041A
++#define REG_PTCL_POLL_MGN_8723D 0x041F
++#define REG_FWHW_TXQ_CTRL_8723D 0x0420
++#define REG_HWSEQ_CTRL_8723D 0x0423
++#define REG_BCNQ_BDNY_8723D 0x0424
++#define REG_MGQ_BDNY_8723D 0x0425
++#define REG_LIFETIME_EN_8723D 0x0426
++#define REG_FW_FREE_TAIL_8723D 0x0427
++#define REG_SPEC_SIFS_8723D 0x0428
++#define REG_RETRY_LIMIT_8723D 0x042A
++#define REG_TXBF_CTRL_8723D 0x042C
++#define REG_DARFRC_8723D 0x0430
++#define REG_RARFRC_8723D 0x0438
++#define REG_RRSR_8723D 0x0440
++#define REG_ARFR0_8723D 0x0444
++#define REG_ARFR1_8723D 0x044C
++#define REG_CCK_CHECK_8723D 0x0454
++#define REG_BCNQ2_BDNY_8723D 0x0455
++#define REG_AMPDU_MAX_TIME_8723D 0x0456
++#define REG_BCNQ1_BDNY_8723D 0x0457
++#define REG_AMPDU_MAX_LENGTH_8723D 0x0458
++#define REG_WMAC_LBK_BUF_HD_8723D 0x045D
++#define REG_NDPA_OPT_CTRL_8723D 0x045F
++#define REG_FAST_EDCA_CTRL_8723D 0x0460
++#define REG_RD_RESP_PKT_TH_8723D 0x0463
++#define REG_DATA_SC_8723D 0x0483
++#define REG_TXRPT_START_OFFSET 0x04AC
++#define REG_POWER_STAGE1_8723D 0x04B4
++#define REG_PTCL_SDF_STATUS_8723D 0x04BB
++#define REG_SW_AMPDU_BURST_MODE_CTRL_8723D 0x04BC
++#define REG_EVTQ_BNDY_8723D 0x04BF
++#define REG_PKT_LIFE_TIME_8723D 0x04C0
++#define REG_PKT_BE_BK_LIFE_TIME_8723D 0x04C2 /* ?????? */
++
++#define REG_STBC_SETTING_8723D 0x04C4
++#define REG_HT_SINGLE_AMPDU_8723D 0x04C7
++#define REG_PROT_MODE_CTRL_8723D 0x04C8
++#define REG_MAX_AGGR_NUM_8723D 0x04CA
++#define REG_RTS_MAX_AGGR_NUM_8723D 0x04CB
++#define REG_BAR_MODE_CTRL_8723D 0x04CC
++#define REG_RA_TRY_RATE_AGG_LMT_8723D 0x04CF
++#define REG_MACID_SLEEP2_8723D 0x04D0
++#define REG_PTCL_HWSSN0_8723D 0x04D8
++#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723D 0x045D /* ?????? */
++
++/************* 0x1480~0x14A7 is for NAN ***************/
++/* Own Master Rank, 8Bytes */
++#define REG_NAN_INTERFACE_ADDR_8723D 0x2480 /* 6 bytes */
++#define REG_NAN_RANDOM_FACTOR_8723D 0x2486 /* 1 byte */
++#define REG_NAN_MASTER_PREF_8723D 0x2487 /* 1 byte */
++
++/* 0x5dc[25:24] NAN role */
++
++/* Current Anchor Master Record */
++#define REG_NAN_CAMR_L_8723D 0x2488 /* 4 bytes */
++#define REG_NAN_CAMR_H_8723D 0x248C /* 4 byte */
++#define REG_NAN_CAMR_AMBTT_8723D 0x2490 /* 4 bytes */
++
++/* Last Anchor Master Record */
++#define REG_NAN_LAMR_L_8723D 0x2494 /* 4 bytes */
++#define REG_NAN_LAMR_H_8723D 0x2498 /* 4 byte */
++#define REG_NAN_LAMR_AMBTT_8723D 0x249C /* 4 bytes */
++
++/* TSF Synced:bit 0
++ * Anchor Master: bit 7
++ */
++#define REG_NAN_STATUS_8723D 0x24A0 /* BIT0 */
++
++/* -----------------------------------------------------
++ *
++ *	0x0500h ~ 0x05FFh	EDCA Configuration
++ *
++ * -----------------------------------------------------
++ * gogogo
++ */
++#define REG_EDCA_VO_PARAM_8723D 0x0500
++#define REG_EDCA_VI_PARAM_8723D 0x0504
++#define REG_EDCA_BE_PARAM_8723D 0x0508
++#define REG_EDCA_BK_PARAM_8723D 0x050C
++#define REG_BCNTCFG_8723D 0x0510
++#define REG_PIFS_8723D 0x0512
++#define REG_RDG_PIFS_8723D 0x0513
++#define REG_SIFS_CTX_8723D 0x0514
++#define REG_SIFS_TRX_8723D 0x0516
++#define REG_AGGR_BREAK_TIME_8723D 0x051A
++#define REG_SLOT_8723D 0x051B
++#define REG_TX_PTCL_CTRL_8723D 0x0520
++#define REG_TXPAUSE_8723D 0x0522
++#define REG_DIS_TXREQ_CLR_8723D 0x0523
++#define REG_RD_CTRL_8723D 0x0524
++/*
++ * Format for offset 540h-542h:
++ *	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
++ *	[7:4]:   Reserved.
++ *	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
++ *	[23:20]: Reserved
++ * Description:
++ *	              |
++ * |<--Setup--|--Hold------------>|
++ *	--------------|----------------------
++ * |
++ * TBTT
++ * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
++ * Described by Designer Tim and Bruce, 2011-01-14.
++ *
++ */
++#define REG_TBTT_PROHIBIT_8723D 0x0540
++#define REG_RD_NAV_NXT_8723D 0x0544
++#define REG_NAV_PROT_LEN_8723D 0x0546
++#define REG_BCN_CTRL_8723D 0x0550
++#define REG_EDCA_BCNCTRL1_IOREG_8723D 0x0551
++#define REG_MBID_NUM_8723D 0x0552
++#define REG_DUAL_TSF_RST_8723D 0x0553
++#define REG_BCN_INTERVAL_8723D 0x0554
++#define REG_DRVERLYINT_8723D 0x0558
++#define REG_BCNDMATIM_8723D 0x0559
++#define REG_ATIMWND_8723D 0x055A
++#define REG_USTIME_TSF_8723D 0x055C
++#define REG_BCN_MAX_ERR_8723D 0x055D
++#define REG_RXTSF_OFFSET_CCK_8723D 0x055E
++#define REG_RXTSF_OFFSET_OFDM_8723D 0x055F
++#define REG_TSFTR_8723D 0x0560
++#define REG_CTWND_8723D 0x0572
++#define REG_SECONDARY_CCA_CTRL_8723D 0x0577 /* ?????? */
++#define REG_TSFTR2_8723D 0x0578
++#define REG_PSTIMER_8723D 0x0580
++#define REG_TIMER0_8723D 0x0584
++#define REG_TIMER1_8723D 0x0588
++#define REG_SCH_MULTI_BCN_8723D 0x05B2
++#define REG_SCH_CURRENT_BCN_8723D 0x05B3
++#define REG_ACMHWCTRL_8723D 0x05C0
++#define REG_SCH_SDFX_EARLY_8723D 0x05CF
++#define REG_SCH_PORT2_EARLY_8723D 0x05D0
++#define REG_SCH_TSFT_DIFF_8723D 0x05D2
++#define REG_EDCA_BCNCTRL2_IOREG_8723D 0x05D4
++#define REG_EDCA_DRVERLYINT1_IOREG_8723D 0x05D4
++#define REG_EDCA_BCNSPACE3_IOREG_8723D 0x05D8
++#define REG_EDCA_BCNSPACE4_IOREG_8723D 0x05DA
++#define REG_HOP_CNT_8723D 0x05DC
++#define REG_SCH_M_DW_8723D 0x05DD
++#define REG_SCH_M_SLOT_8723D 0x05DE
++#define REG_SCH_EARLY_DWEND_8723D 0x05DF
++#define REG_SCH_TXCMD_8723D 0x05F8
++
++/* -----------------------------------------------------
++ *
++ *	0x0600h ~ 0x07FFh	WMAC Configuration
++ *
++ * -----------------------------------------------------
++ * gogogo
++ */
++#define REG_MAC_CR_8723D 0x0600
++#define REG_TCR_8723D 0x0604
++#define REG_RCR_8723D 0x0608
++#define REG_RX_PKT_LIMIT_8723D 0x060C
++#define REG_RX_DLK_TIME_8723D 0x060D
++#define REG_RX_DRVINFO_SZ_8723D 0x060F
++
++#define REG_MACID_8723D 0x0610
++#define REG_BSSID_8723D 0x0618
++#define REG_MAR_8723D 0x0620
++#define REG_MBIDCAMCFG_8723D 0x0628
++
++#define REG_USTIME_EDCA_8723D 0x0638
++#define REG_MAC_SPEC_SIFS_8723D 0x063A
++#define REG_RESP_SIFP_CCK_8723D 0x063C
++#define REG_RESP_SIFS_OFDM_8723D 0x063E
++#define REG_ACKTO_8723D 0x0640
++#define REG_CTS2TO_8723D 0x0641
++#define REG_EIFS_8723D 0x0642
++
++#define REG_NAV_UPPER_8723D 0x0652 /* ?????? */
++#define REG_TRXPTCL_CTL_8723D 0x0668
++
++/* security */
++#define REG_CAMCMD_8723D 0x0670
++#define REG_CAMWRITE_8723D 0x0674
++#define REG_CAMREAD_8723D 0x0678
++#define REG_CAMDBG_8723D 0x067C
++#define REG_SECCFG_8723D 0x0680
++
++/* Power */
++#define REG_WOW_CTRL_8723D 0x0690
++#define REG_PS_RX_INFO_8723D 0x0692
++#define REG_UAPSD_TID_8723D 0x0693
++#define REG_WKFMCAM_NUM_8723D 0x0698
++#define REG_RXFLTMAP0_8723D 0x06A0
++#define REG_RXFLTMAP1_8723D 0x06A2
++#define REG_RXFLTMAP2_8723D 0x06A4
++#define REG_BCN_PSR_RPT_8723D 0x06A8
++#define REG_BT_COEX_TABLE_8723D 0x06C0
++#define REG_ASSOCIATED_BFMER0_INFO_8723D 0x06E4
++#define REG_ASSOCIATED_BFMER1_INFO_8723D 0x06EC
++#define REG_CSI_RPT_PARAM_BW20_8723D 0x06F4
++#define REG_CSI_RPT_PARAM_BW40_8723D 0x06F8
++#define REG_CSI_RPT_PARAM_BW80_8723D 0x06FC
++
++/* Hardware Port 2 */
++#define REG_MACID1_8723D 0x0700
++#define REG_BSSID1_8723D 0x0708
++#define REG_ASSOCIATED_BFMEE_SEL_8723D 0x0714
++#define REG_SND_PTCL_CTRL_8723D 0x0718
++
++/* -----------------------------------------------------
++ *
++ *	Redifine 8192C register definition for compatibility
++ *
++ * -----------------------------------------------------
++ */
++
++/* TODO: use these definition when using REG_xxx naming rule.
++ * NOTE: DO NOT Remove these definition. Use later.
++ */
++#define EFUSE_CTRL_8723D REG_EFUSE_CTRL_8723D /* E-Fuse Control. */
++#define EFUSE_TEST_8723D REG_LDO_EFUSE_CTRL_8723D /* E-Fuse Test. */
++#define MSR_8723D (REG_CR_8723D + 2) /* Media status register */
++#define ISR_8723D REG_HISR0_8723D
++#define TSFR_8723D REG_TSFTR_8723D /* Timing Sync Function Timer Register. */
++
++/* Redifine MACID register, to compatible prior ICs. */
++#define IDR0_8723D REG_MACID_8723D /* MAC ID Register, Offset 0x0050-0x0053 */
++#define IDR4_8723D (REG_MACID_8723D + 4) /* MAC ID Register, Offset 0x0054-0x0055 */
++
++/*
++ * 9. security Control Registers	(Offset: )
++ *
++ */
++#define RWCAM_8723D REG_CAMCMD_8723D /* 8190 data Sheet is called CAMcmd */
++#define WCAMI_8723D REG_CAMWRITE_8723D /* Software write CAM input content */
++#define RCAMO_8723D REG_CAMREAD_8723D /* Software read/write CAM config */
++#define CAMDBG_8723D REG_CAMDBG_8723D
++#define SECR_8723D REG_SECCFG_8723D /* security Configuration Register */
++
++/* ----------------------------------------------------------------------------
++ * 8195 IMR/ISR bits						(offset 0xB0,  8bits)
++ * ----------------------------------------------------------------------------
++ */
++#define IMR_DISABLED_8723D 0
++/* IMR DW0(0x00B0-00B3) Bit 0-31 */
++#define IMR_TIMER2_8723D BIT(31) /* Timeout interrupt 2 */
++#define IMR_TIMER1_8723D BIT(30) /* Timeout interrupt 1 */
++#define IMR_PSTIMEOUT_8723D BIT(29) /* Power Save Time Out Interrupt */
++#define IMR_GTINT4_8723D BIT(28) /* When GTIMER4 expires, this bit is set to 1 */
++#define IMR_GTINT3_8723D BIT(27) /* When GTIMER3 expires, this bit is set to 1 */
++#define IMR_TXBCN0ERR_8723D BIT(26) /* Transmit Beacon0 Error */
++#define IMR_TXBCN0OK_8723D BIT(25) /* Transmit Beacon0 OK */
++#define IMR_TSF_BIT32_TOGGLE_8723D BIT(24) /* TSF Timer BIT32 toggle indication interrupt */
++#define IMR_BCNDMAINT0_8723D BIT(20) /* Beacon DMA Interrupt 0 */
++#define IMR_BCNDERR0_8723D BIT(16) /* Beacon Queue DMA OK0 */
++#define IMR_HSISR_IND_ON_INT_8723D BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
++#define IMR_BCNDMAINT_E_8723D BIT(14) /* Beacon DMA Interrupt Extension for Win7 */
++#define IMR_ATIMEND_8723D BIT(12) /* CTWidnow End or ATIM Window End */
++#define IMR_C2HCMD_8723D BIT(10) /* CPU to Host Command INT status, Write 1 clear */
++#define IMR_CPWM2_8723D BIT(9) /* CPU power mode exchange INT status, Write 1 clear */
++#define IMR_CPWM_8723D BIT(8) /* CPU power mode exchange INT status, Write 1 clear */
++#define IMR_HIGHDOK_8723D BIT(7) /* High Queue DMA OK */
++#define IMR_MGNTDOK_8723D BIT(6) /* Management Queue DMA OK */
++#define IMR_BKDOK_8723D BIT(5) /* AC_BK DMA OK */
++#define IMR_BEDOK_8723D BIT(4) /* AC_BE DMA OK */
++#define IMR_VIDOK_8723D BIT(3) /* AC_VI DMA OK */
++#define IMR_VODOK_8723D BIT(2) /* AC_VO DMA OK */
++#define IMR_RDU_8723D BIT(1) /* Rx Descriptor Unavailable */
++#define IMR_ROK_8723D BIT(0) /* Receive DMA OK */
++
++/* IMR DW1(0x00B4-00B7) Bit 0-31 */
++#define IMR_BCNDMAINT7_8723D BIT(27) /* Beacon DMA Interrupt 7 */
++#define IMR_BCNDMAINT6_8723D BIT(26) /* Beacon DMA Interrupt 6 */
++#define IMR_BCNDMAINT5_8723D BIT(25) /* Beacon DMA Interrupt 5 */
++#define IMR_BCNDMAINT4_8723D BIT(24) /* Beacon DMA Interrupt 4 */
++#define IMR_BCNDMAINT3_8723D BIT(23) /* Beacon DMA Interrupt 3 */
++#define IMR_BCNDMAINT2_8723D BIT(22) /* Beacon DMA Interrupt 2 */
++#define IMR_BCNDMAINT1_8723D BIT(21) /* Beacon DMA Interrupt 1 */
++#define IMR_BCNDOK7_8723D BIT(20) /* Beacon Queue DMA OK Interrupt 7 */
++#define IMR_BCNDOK6_8723D BIT(19) /* Beacon Queue DMA OK Interrupt 6 */
++#define IMR_BCNDOK5_8723D BIT(18) /* Beacon Queue DMA OK Interrupt 5 */
++#define IMR_BCNDOK4_8723D BIT(17) /* Beacon Queue DMA OK Interrupt 4 */
++#define IMR_BCNDOK3_8723D BIT(16) /* Beacon Queue DMA OK Interrupt 3 */
++#define IMR_BCNDOK2_8723D BIT(15) /* Beacon Queue DMA OK Interrupt 2 */
++#define IMR_BCNDOK1_8723D BIT(14) /* Beacon Queue DMA OK Interrupt 1 */
++#define IMR_ATIMEND_E_8723D BIT(13) /* ATIM Window End Extension for Win7 */
++#define IMR_TXERR_8723D BIT(11) /* Tx Error Flag Interrupt status, write 1 clear. */
++#define IMR_RXERR_8723D BIT(10) /* Rx Error Flag INT status, Write 1 clear */
++#define IMR_TXFOVW_8723D BIT(9) /* Transmit FIFO Overflow */
++#define IMR_RXFOVW_8723D BIT(8) /* Receive FIFO Overflow */
++
++#define IMR_MCUERR_8723D BIT(28) /* Beacon DMA Interrupt 7 */
++
++/*===================================================================
++ *=====================================================================
++ *Here the register defines are for 92C. When the define is as same with 92C,
++ *we will use the 92C's define for the consistency
++ *So the following defines for 92C is not entire!!!!!!
++ *=====================================================================
++ *=====================================================================
++ */
++/*
++ * Based on Datasheet V33---090401
++ * Register Summary
++ * Current IOREG MAP
++ * 0x0000h ~ 0x00FFh   System Configuration (256 Bytes)
++ * 0x0100h ~ 0x01FFh   MACTOP General Configuration (256 Bytes)
++ * 0x0200h ~ 0x027Fh   TXDMA Configuration (128 Bytes)
++ * 0x0280h ~ 0x02FFh   RXDMA Configuration (128 Bytes)
++ * 0x0300h ~ 0x03FFh   PCIE EMAC Reserved Region (256 Bytes)
++ * 0x0400h ~ 0x04FFh   Protocol Configuration (256 Bytes)
++ * 0x0500h ~ 0x05FFh   EDCA Configuration (256 Bytes)
++ * 0x0600h ~ 0x07FFh   WMAC Configuration (512 Bytes)
++ * 0x2000h ~ 0x3FFFh   8051 FW Download Region (8196 Bytes)
++ */
++/* ----------------------------------------------------------------------------
++ *		 8195 (TXPAUSE) transmission pause	(Offset 0x522, 8 bits)
++ * ----------------------------------------------------------------------------
++ */
++#if 0
++#define		StopBecon			BIT(6)
++#define		StopHigh				BIT(5)
++#define		StopMgt				BIT(4)
++#define		StopVO				BIT(3)
++#define		StopVI				BIT(2)
++#define		StopBE				BIT(1)
++#define		StopBK				BIT(0)
++#endif
++
++
++/* ****************************************************************************
++ * 8192C Regsiter Bit and Content definition
++ * ****************************************************************************
++ * -----------------------------------------------------
++ *
++ *	0x0000h ~ 0x00FFh	System Configuration
++ *
++ * -----------------------------------------------------
++ */
++#if 0
++	/* 2 SYS_ISO_CTRL */
++#define ISO_MD2PP BIT(0)
++#define ISO_UA2USB BIT(1)
++#define ISO_UD2CORE BIT(2)
++#define ISO_PA2PCIE BIT(3)
++#define ISO_PD2CORE BIT(4)
++#define ISO_IP2MAC BIT(5)
++#define ISO_DIOP BIT(6)
++#define ISO_DIOE BIT(7)
++#define ISO_EB2CORE BIT(8)
++#define ISO_DIOR BIT(9)
++#define PWC_EV12V BIT(15)
++
++
++	/* 2 SYS_FUNC_EN */
++#define FEN_BBRSTB BIT(0)
++#define FEN_BB_GLB_RSTn BIT(1)
++#define FEN_USBA BIT(2)
++#define FEN_UPLL BIT(3)
++#define FEN_USBD BIT(4)
++#define FEN_DIO_PCIE BIT(5)
++#define FEN_PCIEA BIT(6)
++#define FEN_PPLL BIT(7)
++#define FEN_PCIED BIT(8)
++#define FEN_DIOE BIT(9)
++#define FEN_CPUEN BIT(10)
++#define FEN_DCORE BIT(11)
++#define FEN_ELDR BIT(12)
++#define FEN_DIO_RF BIT(13)
++#define FEN_HWPDN BIT(14)
++#define FEN_MREGEN BIT(15)
++
++	/* 2 APS_FSMCO */
++#define PFM_LDALL BIT(0)
++#define PFM_ALDN BIT(1)
++#define PFM_LDKP BIT(2)
++#define PFM_WOWL BIT(3)
++#define EnPDN BIT(4)
++#define PDN_PL BIT(5)
++#define APFM_ONMAC BIT(8)
++#define APFM_OFF BIT(9)
++#define APFM_RSM BIT(10)
++#define AFSM_HSUS BIT(11)
++#define AFSM_PCIE BIT(12)
++#define APDM_MAC BIT(13)
++#define APDM_HOST BIT(14)
++#define APDM_HPDN BIT(15)
++#define RDY_MACON BIT(16)
++#define SUS_HOST BIT(17)
++#define ROP_ALD BIT(20)
++#define ROP_PWR BIT(21)
++#define ROP_SPS BIT(22)
++#define SOP_MRST BIT(25)
++#define SOP_FUSE BIT(26)
++#define SOP_ABG BIT(27)
++#define SOP_AMB BIT(28)
++#define SOP_RCK BIT(29)
++#define SOP_A8M BIT(30)
++#define XOP_BTCK BIT(31)
++
++	/* 2 SYS_CLKR */
++#define ANAD16V_EN BIT(0)
++#define ANA8M BIT(1)
++#define MACSLP BIT(4)
++#define LOADER_CLK_EN BIT(5)
++
++
++	/* 2 9346CR */
++
++#define BOOT_FROM_EEPROM BIT(4)
++#define EEPROM_EN BIT(5)
++
++
++	/* 2 RF_CTRL */
++#define RF_EN BIT(0)
++#define RF_RSTB BIT(1)
++#define RF_SDMRSTB BIT(2)
++
++	/* 2 LDOV12D_CTRL */
++#define LDV12_EN BIT(0)
++#define LDV12_SDBY BIT(1)
++#define LPLDO_HSM BIT(2)
++#define LPLDO_LSM_DIS BIT(3)
++#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
++
++
++	/* 2 EFUSE_TEST (For RTL8723 partially) */
++#define EF_TRPT BIT(7)
++#define EF_CELL_SEL (BIT(8) | BIT(9))  /*  00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */
++#define LDOE25_EN BIT(31)
++#define EFUSE_SEL(x) (((x) & 0x3) << 8)
++#define EFUSE_SEL_MASK 0x300
++#define EFUSE_WIFI_SEL_0 0x0
++#define EFUSE_BT_SEL_0 0x1
++#define EFUSE_BT_SEL_1 0x2
++#define EFUSE_BT_SEL_2 0x3
++
++
++	/* 2 8051FWDL */
++	/* 2 MCUFWDL */
++#define MCUFWDL_EN BIT(0)
++#define MCUFWDL_RDY BIT(1)
++#define FWDL_ChkSum_rpt BIT(2)
++#define MACINI_RDY BIT(3)
++#define BBINI_RDY BIT(4)
++#define RFINI_RDY BIT(5)
++#define WINTINI_RDY BIT(6)
++#define RAM_DL_SEL BIT(7)
++#define ROM_DLEN BIT(19)
++#define CPRST BIT(23)
++
++
++
++	/* 2 REG_SYS_CFG */
++#define XCLK_VLD BIT(0)
++#define ACLK_VLD BIT(1)
++#define UCLK_VLD BIT(2)
++#define PCLK_VLD BIT(3)
++#define PCIRSTB BIT(4)
++#define V15_VLD BIT(5)
++#define TRP_B15V_EN BIT(7)
++#define SIC_IDLE BIT(8)
++#define BD_MAC2 BIT(9)
++#define BD_MAC1 BIT(10)
++#define IC_MACPHY_MODE BIT(11)
++#define CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15))
++#define BT_FUNC BIT(16)
++#define VENDOR_ID BIT(19)
++#define PAD_HWPD_IDN BIT(22)
++#define TRP_VAUX_EN BIT(23)	 /*  RTL ID */
++#define TRP_BT_EN BIT(24)
++#define BD_PKG_SEL BIT(25)
++#define BD_HCI_SEL BIT(26)
++#define TYPE_ID BIT(27)
++
++#define CHIP_VER_RTL_MASK 0xF000	 /* Bit 12 ~ 15 */
++#define CHIP_VER_RTL_SHIFT 12
++
++#endif
++/* -----------------------------------------------------
++ *
++ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
++ *
++ * -----------------------------------------------------
++ */
++#if 0
++
++	/* 2 Function Enable Registers */
++	/* 2 CR 0x0100-0x0103 */
++
++#define HCI_TXDMA_EN BIT(0)
++#define HCI_RXDMA_EN BIT(1)
++#define TXDMA_EN BIT(2)
++#define RXDMA_EN BIT(3)
++#define PROTOCOL_EN BIT(4)
++#define SCHEDULE_EN BIT(5)
++#define MACTXEN BIT(6)
++#define MACRXEN BIT(7)
++#define ENSWBCN BIT(8)
++#define ENSEC BIT(9)
++#define CALTMR_EN BIT(10)	 /*  32k CAL TMR enable */
++
++	/*  Network type */
++#define _NETTYPE(x) (((x) & 0x3) << 16)
++#define MASK_NETTYPE 0x30000
++#define NT_NO_LINK 0x0
++#define NT_LINK_AD_HOC 0x1
++#define NT_LINK_AP 0x2
++#define NT_AS_AP 0x3
++
++
++	/* 2 PBP - Page Size Register 0x0104 */
++#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
++#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
++#define _PSRX_MASK 0xF
++#define _PSTX_MASK 0xF0
++#define _PSRX(x) (x)
++#define _PSTX(x) ((x) << 4)
++
++#define PBP_64 0x0
++#define PBP_128 0x1
++#define PBP_256 0x2
++#define PBP_512 0x3
++#define PBP_1024 0x4
++
++
++	/* 2 TX/RXDMA 0x010C */
++#define RXDMA_ARBBW_EN BIT(0)
++#define RXSHFT_EN BIT(1)
++#define RXDMA_AGG_EN BIT(2)
++#define QS_VO_QUEUE BIT(8)
++#define QS_VI_QUEUE BIT(9)
++#define QS_BE_QUEUE BIT(10)
++#define QS_BK_QUEUE BIT(11)
++#define QS_MANAGER_QUEUE BIT(12)
++#define QS_HIGH_QUEUE BIT(13)
++
++#define HQSEL_VOQ BIT(0)
++#define HQSEL_VIQ BIT(1)
++#define HQSEL_BEQ BIT(2)
++#define HQSEL_BKQ BIT(3)
++#define HQSEL_MGTQ BIT(4)
++#define HQSEL_HIQ BIT(5)
++
++	/*  For normal driver, 0x10C */
++#define _TXDMA_HIQ_MAP(x) (((x) & 0x3) << 14)
++#define _TXDMA_MGQ_MAP(x) (((x) & 0x3) << 12)
++#define _TXDMA_BKQ_MAP(x) (((x) & 0x3) << 10)
++#define _TXDMA_BEQ_MAP(x) (((x) & 0x3) << 8)
++#define _TXDMA_VIQ_MAP(x) (((x) & 0x3) << 6)
++#define _TXDMA_VOQ_MAP(x) (((x) & 0x3) << 4)
++
++#define QUEUE_LOW 1
++#define QUEUE_NORMAL 2
++#define QUEUE_HIGH 3
++
++
++	/* 2 REG_C2HEVT_CLEAR 0x01AF */
++#define C2H_EVT_HOST_CLOSE 0x00	 /*  Set by driver and notify FW that the driver has read the C2H command message */
++#define C2H_EVT_FW_CLOSE 0xFF		 /*  Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. */
++
++
++
++	/* 2 LLT_INIT 0x01E0 */
++#define _LLT_NO_ACTIVE 0x0
++#define _LLT_WRITE_ACCESS 0x1
++#define _LLT_READ_ACCESS 0x2
++
++#define _LLT_INIT_DATA(x) ((x) & 0xFF)
++#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
++#define _LLT_OP(x) (((x) & 0x3) << 30)
++#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
++
++#endif
++/* -----------------------------------------------------
++ *
++ *	0x0200h ~ 0x027Fh	TXDMA Configuration
++ *
++ * -----------------------------------------------------
++ */
++#if 0
++	/* 2 TDECTL 0x0208 */
++#define BLK_DESC_NUM_SHIFT 4
++#define BLK_DESC_NUM_MASK 0xF
++
++
++	/* 2 TXDMA_OFFSET_CHK 0x020C */
++#define DROP_DATA_EN BIT(9)
++#endif
++/* -----------------------------------------------------
++ *
++ *	0x0280h ~ 0x028Bh	RX DMA Configuration
++ *
++ * -----------------------------------------------------
++ */
++#if 0
++	/* 2 REG_RXDMA_CONTROL, 0x0286h */
++
++	/*  Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before */
++	/*  this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. */
++#define RXPKT_RELEASE_POLL BIT(0)
++	/*  Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in */
++	/*  this bit. FW can start releasing packets after RXDMA entering idle mode. */
++#define RXDMA_IDLE BIT(1)
++	/*  When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host */
++	/*  completed, and stop DMA packet to host. RXDMA will then report Default: 0; */
++#define RW_RELEASE_EN BIT(2)
++#endif
++/* -----------------------------------------------------
++ *
++ *	0x0400h ~ 0x047Fh	Protocol Configuration
++ *
++ * -----------------------------------------------------
++ */
++#if 0
++	/* 2 FWHW_TXQ_CTRL 0x0420 */
++#define EN_AMPDU_RTY_NEW BIT(7)
++
++
++	/* 2 REG_LIFECTRL_CTRL 0x0426 */
++#define HAL92C_EN_PKT_LIFE_TIME_BK BIT(3)
++#define HAL92C_EN_PKT_LIFE_TIME_BE BIT(2)
++#define HAL92C_EN_PKT_LIFE_TIME_VI BIT(1)
++#define HAL92C_EN_PKT_LIFE_TIME_VO BIT(0)
++
++#define HAL92C_MSDU_LIFE_TIME_UNIT 128		 /*  in us, said by Tim. */
++
++
++	/* 2 SPEC SIFS 0x0428 */
++#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
++#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
++
++	/* 2 RL 0x042A */
++#define RETRY_LIMIT_SHORT_SHIFT 8
++#define RETRY_LIMIT_LONG_SHIFT 0
++
++#define _LRL(x) ((x) & 0x3F)
++#define _SRL(x) (((x) & 0x3F) << 8)
++#endif
++
++/* -----------------------------------------------------
++ *
++ *	0x0500h ~ 0x05FFh	EDCA Configuration
++ *
++ * -----------------------------------------------------
++ */
++#if 0
++	/* 2 EDCA setting 0x050C */
++#define AC_PARAM_TXOP_LIMIT_OFFSET 16
++#define AC_PARAM_ECW_MAX_OFFSET 12
++#define AC_PARAM_ECW_MIN_OFFSET 8
++#define AC_PARAM_AIFS_OFFSET 0
++
++
++	/* 2 BCN_CTRL 0x0550 */
++#define EN_TXBCN_RPT BIT(2)
++#define EN_BCN_FUNCTION BIT(3)
++
++	/* 2 TxPause 0x0522 */
++#define STOP_BCNQ BIT(6)
++#endif
++
++/* 2 ACMHWCTRL 0x05C0 */
++#define acm_hw_hw_en_8723d BIT(0)
++#define acm_hw_voq_en_8723d BIT(1)
++#define acm_hw_viq_en_8723d BIT(2)
++#define acm_hw_beq_en_8723d BIT(3)
++#define acm_hw_voq_status_8723d BIT(5)
++#define acm_hw_viq_status_8723d BIT(6)
++#define acm_hw_beq_status_8723d BIT(7)
++
++/* -----------------------------------------------------
++ *
++ *	0x0600h ~ 0x07FFh	WMAC Configuration
++ *
++ * -----------------------------------------------------
++ */
++#if 0
++
++	/* 2 TCR 0x0604 */
++#define DIS_GCLK BIT(1)
++#define PAD_SEL BIT(2)
++#define PWR_ST BIT(6)
++#define PWRBIT_OW_EN BIT(7)
++#define ACRC BIT(8)
++#define CFENDFORM BIT(9)
++#define ICV BIT(10)
++#endif
++
++/* ----------------------------------------------------------------------------
++ * 8195 (RCR) Receive Configuration Register	(Offset 0x608, 32 bits)
++ * ----------------------------------------------------------------------------
++ */
++#if 0
++#define RCR_APPFCS BIT(31)		 /*  WMAC append FCS after pauload */
++#define RCR_APP_MIC BIT(30)		 /*  MACRX will retain the MIC at the bottom of the packet. */
++#define RCR_APP_ICV BIT(29)        /*  MACRX will retain the ICV at the bottom of the packet. */
++#define RCR_APP_PHYST_RXFF BIT(28)        /*  HY status is appended before RX packet in RXFF */
++#define RCR_APP_BA_SSN BIT(27)		 /*  SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */
++#define RCR_RSVD_BIT(26) BIT26		 /*  Reserved */
++#endif
++#define RCR_TCPOFLD_EN BIT(25) /* Enable TCP checksum offload */
++#if 0
++#define RCR_ENMBID BIT(24)		 /*  Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. */
++#define RCR_LSIGEN BIT(23)		 /*  Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. */
++#define RCR_MFBEN BIT(22)		 /*  Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. */
++#endif
++
++#endif /*  #ifndef __INC_HAL8723DREG_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_bb.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_bb.c
+new file mode 100644
+index 000000000..b9d78d676
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_bb.c
+@@ -0,0 +1,908 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/*Image2HeaderVersion: 3.5.2*/
++#include "mp_precomp.h"
++#include "../phydm_precomp.h"
++
++#if (RTL8723D_SUPPORT == 1)
++static boolean
++check_positive(
++	struct dm_struct *dm,
++	const u32	condition1,
++	const u32	condition2,
++	const u32	condition3,
++	const u32	condition4
++)
++{
++	u8	_board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
++			((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
++			((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
++			((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
++			((dm->board_type & BIT(2)) >> 2) << 4 | /* _BT*/
++			((dm->board_type & BIT(1)) >> 1) << 5 | /* _NGFF*/
++			((dm->board_type & BIT(5)) >> 5) << 6;  /* _TRSWT*/
++
++	u32	cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
++
++	u8	cut_version_for_para = (dm->cut_version ==  ODM_CUT_A) ? 15 : dm->cut_version;
++	u8	pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type;
++
++	u32	driver1 = cut_version_for_para << 24 |
++			(dm->support_interface & 0xF0) << 16 |
++			dm->support_platform << 16 |
++			pkg_type_for_para << 12 |
++			(dm->support_interface & 0x0F) << 8  |
++			_board_type;
++
++	u32	driver2 = (dm->type_glna & 0xFF) <<  0 |
++			(dm->type_gpa & 0xFF)  <<  8 |
++			(dm->type_alna & 0xFF) << 16 |
++			(dm->type_apa & 0xFF)  << 24;
++
++	u32	driver3 = 0;
++
++	u32	driver4 = (dm->type_glna & 0xFF00) >>  8 |
++			(dm->type_gpa & 0xFF00) |
++			(dm->type_alna & 0xFF00) << 8 |
++			(dm->type_apa & 0xFF00)  << 16;
++
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
++		  __func__, cond1, cond2, cond3, cond4);
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
++		  __func__, driver1, driver2, driver3, driver4);
++
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "	(Platform, Interface) = (0x%X, 0x%X)\n",
++		  dm->support_platform, dm->support_interface);
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "	(Board, Package) = (0x%X, 0x%X)\n", dm->board_type,
++		  dm->package_type);
++
++
++	/*============== value Defined Check ===============*/
++	/*QFN type [15:12] and cut version [27:24] need to do value check*/
++
++	if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
++		return false;
++	if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
++		return false;
++
++	/*=============== Bit Defined Check ================*/
++	/* We don't care [31:28] */
++
++	cond1 &= 0x00FF0FFF;
++	driver1 &= 0x00FF0FFF;
++
++	if ((cond1 & driver1) == cond1) {
++		u32	bit_mask = 0;
++
++		if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
++			return true;
++
++		if ((cond1 & BIT(0)) != 0) /*GLNA*/
++			bit_mask |= 0x000000FF;
++		if ((cond1 & BIT(1)) != 0) /*GPA*/
++			bit_mask |= 0x0000FF00;
++		if ((cond1 & BIT(2)) != 0) /*ALNA*/
++			bit_mask |= 0x00FF0000;
++		if ((cond1 & BIT(3)) != 0) /*APA*/
++			bit_mask |= 0xFF000000;
++
++		if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask)))  /* board_type of each RF path is matched*/
++			return true;
++		else
++			return false;
++	} else
++		return false;
++}
++
++/******************************************************************************
++*                           agc_tab.TXT
++******************************************************************************/
++
++u32 array_mp_8723d_agc_tab[] = {
++		0xC78, 0xFE000101,
++		0xC78, 0xFD010101,
++		0xC78, 0xFC020101,
++		0xC78, 0xFB030101,
++		0xC78, 0xFA040101,
++		0xC78, 0xF9050101,
++		0xC78, 0xF8060101,
++		0xC78, 0xF7070101,
++		0xC78, 0xF6080101,
++		0xC78, 0xF5090101,
++		0xC78, 0xF40A0101,
++		0xC78, 0xF30B0101,
++		0xC78, 0xF20C0101,
++		0xC78, 0xF10D0101,
++		0xC78, 0xF00E0101,
++		0xC78, 0xEF0F0101,
++		0xC78, 0xEE100101,
++		0xC78, 0xED110101,
++		0xC78, 0xEC120101,
++		0xC78, 0xEB130101,
++		0xC78, 0xEA140101,
++		0xC78, 0xE9150101,
++		0xC78, 0xE8160101,
++		0xC78, 0xE7170101,
++		0xC78, 0xE6180101,
++		0xC78, 0xE5190101,
++		0xC78, 0xE41A0101,
++		0xC78, 0xE31B0101,
++		0xC78, 0xE21C0101,
++		0xC78, 0xE11D0101,
++		0xC78, 0xE01E0101,
++		0xC78, 0x861F0101,
++		0xC78, 0x85200101,
++		0xC78, 0x84210101,
++		0xC78, 0x83220101,
++		0xC78, 0x82230101,
++		0xC78, 0x81240101,
++		0xC78, 0x80250101,
++		0xC78, 0x44260101,
++		0xC78, 0x43270101,
++		0xC78, 0x42280101,
++		0xC78, 0x41290101,
++		0xC78, 0x402A0101,
++		0xC78, 0x022B0101,
++		0xC78, 0x012C0101,
++		0xC78, 0x002D0101,
++		0xC78, 0xC52E0001,
++		0xC78, 0xC42F0001,
++		0xC78, 0xC3300001,
++		0xC78, 0xC2310001,
++		0xC78, 0xC1320001,
++		0xC78, 0xC0330001,
++		0xC78, 0x04340001,
++		0xC78, 0x03350001,
++		0xC78, 0x02360001,
++		0xC78, 0x01370001,
++		0xC78, 0x00380001,
++		0xC78, 0x00390001,
++		0xC78, 0x003A0001,
++		0xC78, 0x003B0001,
++		0xC78, 0x003C0001,
++		0xC78, 0x003D0001,
++		0xC78, 0x003E0001,
++		0xC78, 0x003F0001,
++		0xC78, 0x6F002001,
++		0xC78, 0x6F012001,
++		0xC78, 0x6F022001,
++		0xC78, 0x6F032001,
++		0xC78, 0x6F042001,
++		0xC78, 0x6F052001,
++		0xC78, 0x6F062001,
++		0xC78, 0x6F072001,
++		0xC78, 0x6F082001,
++		0xC78, 0x6F092001,
++		0xC78, 0x6F0A2001,
++		0xC78, 0x6F0B2001,
++		0xC78, 0x6F0C2001,
++		0xC78, 0x6F0D2001,
++		0xC78, 0x6F0E2001,
++		0xC78, 0x6F0F2001,
++		0xC78, 0x6F102001,
++		0xC78, 0x6F112001,
++		0xC78, 0x6F122001,
++		0xC78, 0x6F132001,
++		0xC78, 0x6F142001,
++		0xC78, 0x6F152001,
++		0xC78, 0x6F162001,
++		0xC78, 0x6F172001,
++		0xC78, 0x6F182001,
++		0xC78, 0x6F192001,
++		0xC78, 0x6F1A2001,
++		0xC78, 0x6F1B2001,
++		0xC78, 0x6F1C2001,
++		0xC78, 0x6F1D2001,
++		0xC78, 0x6F1E2001,
++		0xC78, 0x6F1F2001,
++		0xC78, 0x6F202001,
++		0xC78, 0x6F212001,
++		0xC78, 0x6F222001,
++		0xC78, 0x6F232001,
++		0xC78, 0x6E242001,
++		0xC78, 0x6D252001,
++		0xC78, 0x6C262001,
++		0xC78, 0x6B272001,
++		0xC78, 0x6A282001,
++		0xC78, 0x69292001,
++		0xC78, 0x4B2A2001,
++		0xC78, 0x4A2B2001,
++		0xC78, 0x492C2001,
++		0xC78, 0x482D2001,
++		0xC78, 0x472E2001,
++		0xC78, 0x462F2001,
++		0xC78, 0x45302001,
++		0xC78, 0x44312001,
++		0xC78, 0x43322001,
++		0xC78, 0x42332001,
++		0xC78, 0x41342001,
++		0xC78, 0x40352001,
++		0xC78, 0x02362001,
++		0xC78, 0x01372001,
++		0xC78, 0x00382001,
++		0xC78, 0x00392001,
++		0xC78, 0x003A2001,
++		0xC78, 0x003B2001,
++		0xC78, 0x003C2001,
++		0xC78, 0x003D2001,
++		0xC78, 0x003E2001,
++		0xC78, 0x003F2001,
++		0xC78, 0x7F003101,
++		0xC78, 0x7F013101,
++		0xC78, 0x7F023101,
++		0xC78, 0x7F033101,
++		0xC78, 0x7F043101,
++		0xC78, 0x7F053101,
++		0xC78, 0x7F063101,
++		0xC78, 0x7F073101,
++		0xC78, 0x7E083101,
++		0xC78, 0x7D093101,
++		0xC78, 0x7C0A3101,
++		0xC78, 0x7B0B3101,
++		0xC78, 0x7A0C3101,
++		0xC78, 0x790D3101,
++		0xC78, 0x780E3101,
++		0xC78, 0x770F3101,
++		0xC78, 0x76103101,
++		0xC78, 0x75113101,
++		0xC78, 0x74123101,
++		0xC78, 0x73133101,
++		0xC78, 0x72143101,
++		0xC78, 0x71153101,
++		0xC78, 0x70163101,
++		0xC78, 0x6F173101,
++		0xC78, 0x6E183101,
++		0xC78, 0x6D193101,
++		0xC78, 0x6C1A3101,
++		0xC78, 0x6B1B3101,
++		0xC78, 0x6A1C3101,
++		0xC78, 0x691D3101,
++		0xC78, 0x681E3101,
++		0xC78, 0x4B1F3101,
++		0xC78, 0x4A203101,
++		0xC78, 0x49213101,
++		0xC78, 0x48223101,
++		0xC78, 0x47233101,
++		0xC78, 0x46243101,
++		0xC78, 0x45253101,
++		0xC78, 0x44263101,
++		0xC78, 0x43273101,
++		0xC78, 0x42283101,
++		0xC78, 0x41293101,
++		0xC78, 0x402A3101,
++		0xC78, 0x022B3101,
++		0xC78, 0x012C3101,
++		0xC78, 0x002D3101,
++		0xC78, 0x002E3101,
++		0xC78, 0x002F3101,
++		0xC78, 0x00303101,
++		0xC78, 0x00313101,
++		0xC78, 0x00323101,
++		0xC78, 0x00333101,
++		0xC78, 0x00343101,
++		0xC78, 0x00353101,
++		0xC78, 0x00363101,
++		0xC78, 0x00373101,
++		0xC78, 0x00383101,
++		0xC78, 0x00393101,
++		0xC78, 0x003A3101,
++		0xC78, 0x003B3101,
++		0xC78, 0x003C3101,
++		0xC78, 0x003D3101,
++		0xC78, 0x003E3101,
++		0xC78, 0x003F3101,
++		0xC78, 0xFE403101,
++		0xC78, 0xFD413101,
++		0xC78, 0xFC423101,
++		0xC78, 0xFB433101,
++		0xC78, 0xFA443101,
++		0xC78, 0xF9453101,
++		0xC78, 0xF8463101,
++		0xC78, 0xF7473101,
++		0xC78, 0xF6483101,
++		0xC78, 0xF5493101,
++		0xC78, 0xF44A3101,
++		0xC78, 0xF34B3101,
++		0xC78, 0xF24C3101,
++		0xC78, 0xF14D3101,
++		0xC78, 0xF04E3101,
++		0xC78, 0xEF4F3101,
++		0xC78, 0xEE503101,
++		0xC78, 0xED513101,
++		0xC78, 0xEC523101,
++		0xC78, 0xEB533101,
++		0xC78, 0xEA543101,
++		0xC78, 0xE9553101,
++		0xC78, 0xE8563101,
++		0xC78, 0xE7573101,
++		0xC78, 0xE6583101,
++		0xC78, 0xE5593101,
++		0xC78, 0xE45A3101,
++		0xC78, 0xE35B3101,
++		0xC78, 0xE25C3101,
++		0xC78, 0xE15D3101,
++		0xC78, 0xE05E3101,
++		0xC78, 0x865F3101,
++		0xC78, 0x85603101,
++		0xC78, 0x84613101,
++		0xC78, 0x83623101,
++		0xC78, 0x82633101,
++		0xC78, 0x81643101,
++		0xC78, 0x80653101,
++		0xC78, 0x80663101,
++		0xC78, 0x80673101,
++		0xC78, 0x80683101,
++		0xC78, 0x80693101,
++		0xC78, 0x806A3101,
++		0xC78, 0x806B3101,
++		0xC78, 0x806C3101,
++		0xC78, 0x806D3101,
++		0xC78, 0x806E3101,
++		0xC78, 0x806F3101,
++		0xC78, 0x80703101,
++		0xC78, 0x80713101,
++		0xC78, 0x80723101,
++		0xC78, 0x80733101,
++		0xC78, 0x80743101,
++		0xC78, 0x80753101,
++		0xC78, 0x80763101,
++		0xC78, 0x80773101,
++		0xC78, 0x80783101,
++		0xC78, 0x80793101,
++		0xC78, 0x807A3101,
++		0xC78, 0x807B3101,
++		0xC78, 0x807C3101,
++		0xC78, 0x807D3101,
++		0xC78, 0x807E3101,
++		0xC78, 0x807F3101,
++		0xC78, 0xEF402001,
++		0xC78, 0xEF412001,
++		0xC78, 0xEF422001,
++		0xC78, 0xEF432001,
++		0xC78, 0xEF442001,
++		0xC78, 0xEF452001,
++		0xC78, 0xEF462001,
++		0xC78, 0xEF472001,
++		0xC78, 0xEF482001,
++		0xC78, 0xEF492001,
++		0xC78, 0xEF4A2001,
++		0xC78, 0xEF4B2001,
++		0xC78, 0xEF4C2001,
++		0xC78, 0xEF4D2001,
++		0xC78, 0xEF4E2001,
++		0xC78, 0xEF4F2001,
++		0xC78, 0xEF502001,
++		0xC78, 0xEF512001,
++		0xC78, 0xEF522001,
++		0xC78, 0xEF532001,
++		0xC78, 0xEF542001,
++		0xC78, 0xEF552001,
++		0xC78, 0xEF562001,
++		0xC78, 0xEF572001,
++		0xC78, 0xEF582001,
++		0xC78, 0xEF592001,
++		0xC78, 0xEF5A2001,
++		0xC78, 0xEF5B2001,
++		0xC78, 0xEF5C2001,
++		0xC78, 0xEF5D2001,
++		0xC78, 0xEF5E2001,
++		0xC78, 0xEF5F2001,
++		0xC78, 0xEF602001,
++		0xC78, 0xEE612001,
++		0xC78, 0xED622001,
++		0xC78, 0xEC632001,
++		0xC78, 0xEB642001,
++		0xC78, 0xEA652001,
++		0xC78, 0xE9662001,
++		0xC78, 0xE8672001,
++		0xC78, 0xCB682001,
++		0xC78, 0xCA692001,
++		0xC78, 0xC96A2001,
++		0xC78, 0xC86B2001,
++		0xC78, 0xC76C2001,
++		0xC78, 0xC66D2001,
++		0xC78, 0xC56E2001,
++		0xC78, 0xC46F2001,
++		0xC78, 0xC3702001,
++		0xC78, 0xC2712001,
++		0xC78, 0xC1722001,
++		0xC78, 0xC0732001,
++		0xC78, 0x82742001,
++		0xC78, 0x81752001,
++		0xC78, 0x80762001,
++		0xC78, 0x80772001,
++		0xC78, 0x80782001,
++		0xC78, 0x80792001,
++		0xC78, 0x807A2001,
++		0xC78, 0x807B2001,
++		0xC78, 0x807C2001,
++		0xC78, 0x807D2001,
++		0xC78, 0x807E2001,
++		0xC78, 0x807F2001,
++		0xC78, 0xFA001101,
++		0xC78, 0xF9011101,
++		0xC78, 0xF8021101,
++		0xC78, 0xF7031101,
++		0xC78, 0xF6041101,
++		0xC78, 0xF5051101,
++		0xC78, 0xF4061101,
++		0xC78, 0xD7071101,
++		0xC78, 0xD6081101,
++		0xC78, 0xD5091101,
++		0xC78, 0xD40A1101,
++		0xC78, 0x970B1101,
++		0xC78, 0x960C1101,
++		0xC78, 0x950D1101,
++		0xC78, 0x940E1101,
++		0xC78, 0x930F1101,
++		0xC78, 0x92101101,
++		0xC78, 0x91111101,
++		0xC78, 0x90121101,
++		0xC78, 0x8F131101,
++		0xC78, 0x8E141101,
++		0xC78, 0x8D151101,
++		0xC78, 0x8C161101,
++		0xC78, 0x8B171101,
++		0xC78, 0x8A181101,
++		0xC78, 0x89191101,
++		0xC78, 0x881A1101,
++		0xC78, 0x871B1101,
++		0xC78, 0x861C1101,
++		0xC78, 0x851D1101,
++		0xC78, 0x841E1101,
++		0xC78, 0x831F1101,
++		0xC78, 0x82201101,
++		0xC78, 0x81211101,
++		0xC78, 0x80221101,
++		0xC78, 0x43231101,
++		0xC78, 0x42241101,
++		0xC78, 0x41251101,
++		0xC78, 0x04261101,
++		0xC78, 0x03271101,
++		0xC78, 0x02281101,
++		0xC78, 0x01291101,
++		0xC78, 0x002A1101,
++		0xC78, 0xC42B1001,
++		0xC78, 0xC32C1001,
++		0xC78, 0xC22D1001,
++		0xC78, 0xC12E1001,
++		0xC78, 0xC02F1001,
++		0xC78, 0x85301001,
++		0xC78, 0x84311001,
++		0xC78, 0x83321001,
++		0xC78, 0x82331001,
++		0xC78, 0x81341001,
++		0xC78, 0x80351001,
++		0xC78, 0x05361001,
++		0xC78, 0x04371001,
++		0xC78, 0x03381001,
++		0xC78, 0x02391001,
++		0xC78, 0x013A1001,
++		0xC78, 0x003B1001,
++		0xC78, 0x003C1001,
++		0xC78, 0x003D1001,
++		0xC78, 0x003E1001,
++		0xC78, 0x003F1001,
++		0xC50, 0x69553422,
++		0xC50, 0x69553420,
++
++};
++
++void
++odm_read_and_config_mp_8723d_agc_tab(struct dm_struct *dm)
++{
++	u32	i = 0;
++	u8	c_cond;
++	boolean	is_matched = true, is_skipped = false;
++	u32	array_len = sizeof(array_mp_8723d_agc_tab) / sizeof(u32);
++	u32	*array = array_mp_8723d_agc_tab;
++
++	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
++
++	while ((i + 1) < array_len) {
++		v1 = array[i];
++		v2 = array[i + 1];
++
++		if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
++			if (v1 & BIT(31)) {/* positive condition*/
++				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
++				if (c_cond == COND_ENDIF) {/*end*/
++					is_matched = true;
++					is_skipped = false;
++					PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
++				} else if (c_cond == COND_ELSE) { /*else*/
++					is_matched = is_skipped ? false : true;
++					PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
++				} else {/*if , else if*/
++					pre_v1 = v1;
++					pre_v2 = v2;
++					PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
++				}
++			} else if (v1 & BIT(30)) { /*negative condition*/
++				if (is_skipped == false) {
++					if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
++						is_matched = true;
++						is_skipped = true;
++					} else {
++						is_matched = false;
++						is_skipped = false;
++					}
++				} else
++					is_matched = false;
++			}
++		} else {
++			if (is_matched)
++				odm_config_bb_agc_8723d(dm, v1, MASKDWORD, v2);
++		}
++		i = i + 2;
++	}
++}
++
++u32
++odm_get_version_mp_8723d_agc_tab(void)
++{
++		return 40;
++}
++
++/******************************************************************************
++*                           phy_reg.TXT
++******************************************************************************/
++
++u32 array_mp_8723d_phy_reg[] = {
++		0x800, 0x80046C00,
++		0x804, 0x00000003,
++		0x808, 0x0000FC00,
++		0x80C, 0x0000000A,
++		0x810, 0x10001331,
++		0x814, 0x020C3910,
++		0x818, 0x00200385,
++		0x81C, 0x00000000,
++		0x820, 0x01000100,
++		0x824, 0x00390204,
++		0x828, 0x00000000,
++		0x82C, 0x00000000,
++		0x830, 0x00000000,
++		0x834, 0x00000000,
++		0x838, 0x00000000,
++		0x83C, 0x00000000,
++		0x840, 0x00010000,
++		0x844, 0x00000000,
++		0x848, 0x00000000,
++		0x84C, 0x00000000,
++		0x850, 0x00000000,
++		0x854, 0x00000000,
++		0x858, 0x569A11A9,
++		0x85C, 0x01000014,
++		0x860, 0x66F60110,
++		0x864, 0x461F0641,
++		0x868, 0x00000000,
++		0x86C, 0x27272700,
++		0x870, 0x07000460,
++		0x874, 0x25004000,
++		0x878, 0x00000808,
++		0x87C, 0x004F0201,
++		0x880, 0xB2002E12,
++		0x884, 0x00000007,
++		0x888, 0x00000000,
++		0x88C, 0xCCC000C0,
++		0x890, 0x00000800,
++		0x894, 0xFFFFFFFE,
++		0x898, 0x40302010,
++		0x89C, 0x00706050,
++		0x900, 0x00000000,
++		0x904, 0x00000023,
++		0x908, 0x00000000,
++		0x90C, 0x81121111,
++		0x910, 0x00000402,
++		0x914, 0x00000300,
++		0x920, 0x18C6318C,
++		0x924, 0x0000018C,
++		0x948, 0x99000000,
++		0x94C, 0x00000010,
++		0x950, 0x00003800,
++		0x954, 0x5A380000,
++		0x958, 0x4BC6D87A,
++		0x95C, 0x04EB9B79,
++		0x96C, 0x00000003,
++		0x970, 0x00000000,
++		0x974, 0x00000000,
++		0x978, 0x00000000,
++		0x97C, 0x13000000,
++		0x980, 0x00000000,
++		0xA00, 0x00D046C8,
++		0xA04, 0x80FF800C,
++		0xA08, 0x8C838300,
++		0xA0C, 0x2E20100F,
++		0xA10, 0x9500BB78,
++		0xA14, 0x1114D028,
++		0xA18, 0x00881117,
++		0xA1C, 0x89140F00,
++		0xA20, 0xE82C0001,
++		0xA24, 0x64B80C1C,
++		0xA28, 0x00008810,
++		0xA2C, 0x00D30000,
++		0xA70, 0x101FBF00,
++		0xA74, 0x00000007,
++		0xA78, 0x00008900,
++		0xA7C, 0x225B0606,
++		0xA80, 0x2180FA74,
++		0xA84, 0x00200000,
++		0xA88, 0x040C0000,
++		0xA8C, 0x12345678,
++		0xA90, 0xABCDEF00,
++		0xA94, 0x001B1B89,
++		0xA98, 0x00000000,
++		0xA9C, 0x00020000,
++		0xAA0, 0x00000000,
++		0xAA4, 0x0000000C,
++		0xAA8, 0xCA100008,
++		0xAAC, 0x01235667,
++		0xAB0, 0x00000000,
++		0xAB4, 0x20201402,
++		0xB2C, 0x00000000,
++		0xC00, 0x48071D40,
++		0xC04, 0x03A05611,
++		0xC08, 0x000000E4,
++		0xC0C, 0x6C6C6C6C,
++		0xC10, 0x28800000,
++		0xC14, 0x40000100,
++		0xC18, 0x08800000,
++		0xC1C, 0x40000100,
++		0xC20, 0x00000000,
++		0xC24, 0x00000000,
++		0xC28, 0x00000000,
++		0xC2C, 0x00000000,
++		0xC30, 0x69E9AC48,
++		0xC34, 0x31000040,
++		0xC38, 0x21688080,
++		0xC3C, 0x000016D4,
++		0xC40, 0x1F78403F,
++		0xC44, 0x00010036,
++		0xC48, 0xEC020107,
++		0xC4C, 0x007F037F,
++		0xC50, 0x69553420,
++		0xC54, 0x43BC0094,
++		0xC58, 0x00015969,
++		0xC5C, 0x00310492,
++		0xC60, 0x00280A00,
++		0xC64, 0x7112848B,
++		0xC68, 0x47C074FF,
++		0xC6C, 0x00000036,
++		0xC70, 0x2C7F000D,
++		0xC74, 0x020600DB,
++		0xC78, 0x0000001F,
++		0xC7C, 0x00B91612,
++		0xC80, 0x390000E4,
++		0xC84, 0x21F60000,
++		0xC88, 0x40000100,
++		0xC8C, 0x20200000,
++		0xC90, 0x00091521,
++		0xC94, 0x00000000,
++		0xC98, 0x00121820,
++		0xC9C, 0x00007F7F,
++		0xCA0, 0x00012000,
++		0xCA4, 0x800000A0,
++		0xCA8, 0x84E6C606,
++		0xCAC, 0x00000060,
++		0xCB0, 0x00000000,
++		0xCB4, 0x00000000,
++		0xCB8, 0x00000000,
++		0xCBC, 0x28000000,
++		0xCC0, 0x0010A3D0,
++		0xCC4, 0x00000F7D,
++		0xCC8, 0x000442D6,
++		0xCCC, 0x00000000,
++		0xCD0, 0x000001C8,
++		0xCD4, 0x001C8000,
++		0xCD8, 0x00000100,
++		0xCDC, 0x40100000,
++		0xCE0, 0x00222220,
++		0xCE4, 0x20000000,
++		0xCE8, 0x37644302,
++		0xCEC, 0x2F97D40C,
++		0xD00, 0x00030740,
++		0xD04, 0x40020401,
++		0xD08, 0x0000907F,
++		0xD0C, 0x20010201,
++		0xD10, 0xA0633333,
++		0xD14, 0x3333BC53,
++		0xD18, 0x7A8F5B6F,
++		0xD2C, 0xCC979975,
++		0xD30, 0x00000000,
++		0xD34, 0x40608000,
++		0xD38, 0x88000000,
++		0xD3C, 0xC0127343,
++		0xD40, 0x00000000,
++		0xD44, 0x00000000,
++		0xD48, 0x00000000,
++		0xD4C, 0x00000000,
++		0xD50, 0x00000038,
++		0xD54, 0x00000000,
++		0xD58, 0x00000282,
++		0xD5C, 0x30032064,
++		0xD60, 0x4653DE68,
++		0xD64, 0x04518A3C,
++		0xD68, 0x00002101,
++		0xE00, 0x2D2D2D2D,
++		0xE04, 0x2D2D2D2D,
++		0xE08, 0x0390272D,
++		0xE10, 0x2D2D2D2D,
++		0xE14, 0x2D2D2D2D,
++		0xE18, 0x2D2D2D2D,
++		0xE1C, 0x2D2D2D2D,
++		0xE28, 0x00000000,
++		0xE30, 0x1000DC1F,
++		0xE34, 0x10008C1F,
++		0xE38, 0x02140102,
++		0xE3C, 0x681604C2,
++		0xE40, 0x01007C00,
++		0xE44, 0x01004800,
++		0xE48, 0xFB000000,
++		0xE4C, 0x000028D1,
++		0xE50, 0x1000DC1F,
++		0xE54, 0x10008C1F,
++		0xE58, 0x02140102,
++		0xE5C, 0x28160D05,
++		0xE60, 0x00000008,
++		0xE68, 0x001B25A4,
++		0xE6C, 0x01C00014,
++		0xE70, 0x01C00016,
++		0xE74, 0x02000014,
++		0xE78, 0x02000014,
++		0xE7C, 0x02000014,
++		0xE80, 0x02000014,
++		0xE84, 0x01C00014,
++		0xE88, 0x02000014,
++		0xE8C, 0x01C00014,
++		0xED0, 0x01C00014,
++		0xED4, 0x01C00014,
++		0xED8, 0x01C00014,
++		0xEDC, 0x00000014,
++		0xEE0, 0x00000014,
++		0xEE8, 0x21555448,
++		0xEEC, 0x03C00014,
++		0xF14, 0x00000003,
++		0xF00, 0x00100300,
++		0xF08, 0x0000800B,
++		0xF0C, 0x0000F007,
++		0xF10, 0x0000A487,
++		0xF1C, 0x80000064,
++		0xF38, 0x00030155,
++		0xF3C, 0x0000003A,
++		0xF4C, 0x13000000,
++		0xF50, 0x00000000,
++		0xF18, 0x00000000,
++
++};
++
++void
++odm_read_and_config_mp_8723d_phy_reg(struct dm_struct *dm)
++{
++	u32	i = 0;
++	u8	c_cond;
++	boolean	is_matched = true, is_skipped = false;
++	u32	array_len = sizeof(array_mp_8723d_phy_reg) / sizeof(u32);
++	u32	*array = array_mp_8723d_phy_reg;
++
++	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
++
++	while ((i + 1) < array_len) {
++		v1 = array[i];
++		v2 = array[i + 1];
++
++		if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
++			if (v1 & BIT(31)) {/* positive condition*/
++				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
++				if (c_cond == COND_ENDIF) {/*end*/
++					is_matched = true;
++					is_skipped = false;
++					PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
++				} else if (c_cond == COND_ELSE) { /*else*/
++					is_matched = is_skipped ? false : true;
++					PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
++				} else {/*if , else if*/
++					pre_v1 = v1;
++					pre_v2 = v2;
++					PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
++				}
++			} else if (v1 & BIT(30)) { /*negative condition*/
++				if (is_skipped == false) {
++					if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
++						is_matched = true;
++						is_skipped = true;
++					} else {
++						is_matched = false;
++						is_skipped = false;
++					}
++				} else
++					is_matched = false;
++			}
++		} else {
++			if (is_matched)
++				odm_config_bb_phy_8723d(dm, v1, MASKDWORD, v2);
++		}
++		i = i + 2;
++	}
++}
++
++u32
++odm_get_version_mp_8723d_phy_reg(void)
++{
++		return 40;
++}
++
++/******************************************************************************
++*                           phy_reg_pg.TXT
++******************************************************************************/
++
++u32 array_mp_8723d_phy_reg_pg[] = {
++	0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200,
++	0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200,
++	0, 0, 0, 0x00000e00, 0xffffffff, 0x32343434,
++	0, 0, 0, 0x00000e04, 0xffffffff, 0x28303032,
++	0, 0, 0, 0x00000e10, 0xffffffff, 0x30323234,
++	0, 0, 0, 0x00000e14, 0xffffffff, 0x26282830
++};
++
++void
++odm_read_and_config_mp_8723d_phy_reg_pg(struct dm_struct *dm)
++{
++	u32	i = 0;
++	u32	array_len = sizeof(array_mp_8723d_phy_reg_pg) / sizeof(u32);
++	u32	*array = array_mp_8723d_phy_reg_pg;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void	*adapter = dm->adapter;
++	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++
++	PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
++	hal_data->nLinesReadPwrByRate = array_len / 6;
++#endif
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
++
++	dm->phy_reg_pg_version = 1;
++	dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
++
++	for (i = 0; i < array_len; i += 6) {
++		u32	v1 = array[i];
++		u32	v2 = array[i + 1];
++		u32	v3 = array[i + 2];
++		u32	v4 = array[i + 3];
++		u32	v5 = array[i + 4];
++		u32	v6 = array[i + 5];
++
++		odm_config_bb_phy_reg_pg_8723d(dm, v1, v2, v3, v4, v5, v6);
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	rsprintf((char *)hal_data->BufOfLinesPwrByRate[i / 6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,",
++		(v1 == 0 ? "2.4G" : "  5G"), (v2 == 0 ? "A" : "B"), (v3 == 0 ? "1Tx" : "2Tx"), v4, v5, v6);
++#endif
++	}
++}
++
++
++
++#endif /* end of HWIMG_SUPPORT*/
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_bb.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_bb.h
+new file mode 100644
+index 000000000..29322d69c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_bb.h
+@@ -0,0 +1,51 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/*Image2HeaderVersion: 3.5.2*/
++#if (RTL8723D_SUPPORT == 1)
++#ifndef __INC_MP_BB_HW_IMG_8723D_H
++#define __INC_MP_BB_HW_IMG_8723D_H
++
++
++/******************************************************************************
++*                           agc_tab.TXT
++******************************************************************************/
++
++void
++odm_read_and_config_mp_8723d_agc_tab( /* tc: Test Chip, mp: mp Chip*/
++				     struct dm_struct *dm);
++u32 odm_get_version_mp_8723d_agc_tab(void);
++
++/******************************************************************************
++*                           phy_reg.TXT
++******************************************************************************/
++
++void
++odm_read_and_config_mp_8723d_phy_reg( /* tc: Test Chip, mp: mp Chip*/
++				     struct dm_struct *dm);
++u32 odm_get_version_mp_8723d_phy_reg(void);
++
++/******************************************************************************
++*                           phy_reg_pg.TXT
++******************************************************************************/
++
++void
++odm_read_and_config_mp_8723d_phy_reg_pg( /* tc: Test Chip, mp: mp Chip*/
++					struct dm_struct *dm);
++u32	odm_get_version_mp_8723d_phy_reg_pg(void);
++
++#endif
++#endif /* end of HWIMG_SUPPORT*/
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_mac.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_mac.c
+new file mode 100644
+index 000000000..f116a271b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_mac.c
+@@ -0,0 +1,294 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/*Image2HeaderVersion: 3.5.2*/
++#include "mp_precomp.h"
++#include "../phydm_precomp.h"
++
++#if (RTL8723D_SUPPORT == 1)
++static boolean
++check_positive(
++	struct dm_struct *dm,
++	const u32	condition1,
++	const u32	condition2,
++	const u32	condition3,
++	const u32	condition4
++)
++{
++	u8	_board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
++			((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
++			((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
++			((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
++			((dm->board_type & BIT(2)) >> 2) << 4 | /* _BT*/
++			((dm->board_type & BIT(1)) >> 1) << 5 | /* _NGFF*/
++			((dm->board_type & BIT(5)) >> 5) << 6;  /* _TRSWT*/
++
++	u32	cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
++
++	u8	cut_version_for_para = (dm->cut_version ==  ODM_CUT_A) ? 15 : dm->cut_version;
++	u8	pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type;
++
++	u32	driver1 = cut_version_for_para << 24 |
++			(dm->support_interface & 0xF0) << 16 |
++			dm->support_platform << 16 |
++			pkg_type_for_para << 12 |
++			(dm->support_interface & 0x0F) << 8  |
++			_board_type;
++
++	u32	driver2 = (dm->type_glna & 0xFF) <<  0 |
++			(dm->type_gpa & 0xFF)  <<  8 |
++			(dm->type_alna & 0xFF) << 16 |
++			(dm->type_apa & 0xFF)  << 24;
++
++	u32	driver3 = 0;
++
++	u32	driver4 = (dm->type_glna & 0xFF00) >>  8 |
++			(dm->type_gpa & 0xFF00) |
++			(dm->type_alna & 0xFF00) << 8 |
++			(dm->type_apa & 0xFF00)  << 16;
++
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
++		  __func__, cond1, cond2, cond3, cond4);
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
++		  __func__, driver1, driver2, driver3, driver4);
++
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "	(Platform, Interface) = (0x%X, 0x%X)\n",
++		  dm->support_platform, dm->support_interface);
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "	(Board, Package) = (0x%X, 0x%X)\n", dm->board_type,
++		  dm->package_type);
++
++
++	/*============== value Defined Check ===============*/
++	/*QFN type [15:12] and cut version [27:24] need to do value check*/
++
++	if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
++		return false;
++	if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
++		return false;
++
++	/*=============== Bit Defined Check ================*/
++	/* We don't care [31:28] */
++
++	cond1 &= 0x00FF0FFF;
++	driver1 &= 0x00FF0FFF;
++
++	if ((cond1 & driver1) == cond1) {
++		u32	bit_mask = 0;
++
++		if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
++			return true;
++
++		if ((cond1 & BIT(0)) != 0) /*GLNA*/
++			bit_mask |= 0x000000FF;
++		if ((cond1 & BIT(1)) != 0) /*GPA*/
++			bit_mask |= 0x0000FF00;
++		if ((cond1 & BIT(2)) != 0) /*ALNA*/
++			bit_mask |= 0x00FF0000;
++		if ((cond1 & BIT(3)) != 0) /*APA*/
++			bit_mask |= 0xFF000000;
++
++		if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask)))  /* board_type of each RF path is matched*/
++			return true;
++		else
++			return false;
++	} else
++		return false;
++}
++
++/******************************************************************************
++*                           mac_reg.TXT
++******************************************************************************/
++
++u32 array_mp_8723d_mac_reg[] = {
++		0x020, 0x00000013,
++		0x02F, 0x00000010,
++		0x077, 0x00000007,
++		0x421, 0x0000000F,
++		0x422, 0x00000078,
++		0x428, 0x0000000A,
++		0x429, 0x00000010,
++		0x430, 0x00000000,
++		0x431, 0x00000000,
++		0x432, 0x00000000,
++		0x433, 0x00000001,
++		0x434, 0x00000002,
++		0x435, 0x00000003,
++		0x436, 0x00000005,
++		0x437, 0x00000007,
++		0x438, 0x00000000,
++		0x439, 0x00000000,
++		0x43A, 0x00000000,
++		0x43B, 0x00000001,
++		0x43C, 0x00000002,
++		0x43D, 0x00000003,
++		0x43E, 0x00000005,
++		0x43F, 0x00000007,
++		0x440, 0x0000005D,
++		0x441, 0x00000001,
++		0x442, 0x00000000,
++		0x444, 0x00000010,
++		0x445, 0x00000000,
++		0x446, 0x00000000,
++		0x447, 0x00000000,
++		0x448, 0x00000000,
++		0x449, 0x000000F0,
++		0x44A, 0x0000000F,
++		0x44B, 0x0000003E,
++		0x44C, 0x00000010,
++		0x44D, 0x00000000,
++		0x44E, 0x00000000,
++		0x44F, 0x00000000,
++		0x450, 0x00000000,
++		0x451, 0x000000F0,
++		0x452, 0x0000000F,
++		0x453, 0x00000000,
++		0x456, 0x0000005E,
++		0x460, 0x00000066,
++		0x461, 0x00000066,
++		0x4C8, 0x000000FF,
++		0x4C9, 0x00000008,
++		0x4CC, 0x000000FF,
++		0x4CD, 0x000000FF,
++		0x4CE, 0x00000001,
++		0x500, 0x00000026,
++		0x501, 0x000000A2,
++		0x502, 0x0000002F,
++		0x503, 0x00000000,
++		0x504, 0x00000028,
++		0x505, 0x000000A3,
++		0x506, 0x0000005E,
++		0x507, 0x00000000,
++		0x508, 0x0000002B,
++		0x509, 0x000000A4,
++		0x50A, 0x0000005E,
++		0x50B, 0x00000000,
++		0x50C, 0x0000004F,
++		0x50D, 0x000000A4,
++		0x50E, 0x00000000,
++		0x50F, 0x00000000,
++		0x512, 0x0000001C,
++		0x514, 0x0000000A,
++		0x516, 0x0000000A,
++		0x525, 0x0000004F,
++		0x550, 0x00000010,
++		0x551, 0x00000010,
++		0x559, 0x00000002,
++		0x55C, 0x00000028,
++		0x55D, 0x000000FF,
++		0x605, 0x00000030,
++		0x608, 0x0000000E,
++		0x609, 0x0000002A,
++		0x620, 0x000000FF,
++		0x621, 0x000000FF,
++		0x622, 0x000000FF,
++		0x623, 0x000000FF,
++		0x624, 0x000000FF,
++		0x625, 0x000000FF,
++		0x626, 0x000000FF,
++		0x627, 0x000000FF,
++		0x638, 0x00000028,
++		0x63C, 0x0000000A,
++		0x63D, 0x0000000A,
++		0x63E, 0x0000000C,
++		0x63F, 0x0000000C,
++		0x640, 0x00000040,
++		0x642, 0x00000040,
++		0x643, 0x00000000,
++		0x652, 0x000000C8,
++		0x66A, 0x000000B0,
++		0x66E, 0x00000005,
++		0x700, 0x00000021,
++		0x701, 0x00000043,
++		0x702, 0x00000065,
++		0x703, 0x00000087,
++		0x708, 0x00000021,
++		0x709, 0x00000043,
++		0x70A, 0x00000065,
++		0x70B, 0x00000087,
++		0x765, 0x00000018,
++		0x76E, 0x00000004,
++		0x7C0, 0x00000038,
++		0x7C2, 0x0000000F,
++		0x7C3, 0x000000C0,
++		0x7C4, 0x00000077,
++		0x07C, 0x00000003,
++		0x016, 0x000000B3,
++
++};
++
++void
++odm_read_and_config_mp_8723d_mac_reg(struct dm_struct *dm)
++{
++	u32	i = 0;
++	u8	c_cond;
++	boolean	is_matched = true, is_skipped = false;
++	u32	array_len = sizeof(array_mp_8723d_mac_reg) / sizeof(u32);
++	u32	*array = array_mp_8723d_mac_reg;
++
++	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
++
++	while ((i + 1) < array_len) {
++		v1 = array[i];
++		v2 = array[i + 1];
++
++		if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
++			if (v1 & BIT(31)) {/* positive condition*/
++				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
++				if (c_cond == COND_ENDIF) {/*end*/
++					is_matched = true;
++					is_skipped = false;
++					PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
++				} else if (c_cond == COND_ELSE) { /*else*/
++					is_matched = is_skipped ? false : true;
++					PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
++				} else {/*if , else if*/
++					pre_v1 = v1;
++					pre_v2 = v2;
++					PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
++				}
++			} else if (v1 & BIT(30)) { /*negative condition*/
++				if (is_skipped == false) {
++					if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
++						is_matched = true;
++						is_skipped = true;
++					} else {
++						is_matched = false;
++						is_skipped = false;
++					}
++				} else
++					is_matched = false;
++			}
++		} else {
++			if (is_matched)
++				odm_config_mac_8723d(dm, v1, (u8)v2);
++		}
++		i = i + 2;
++	}
++}
++
++u32
++odm_get_version_mp_8723d_mac_reg(void)
++{
++		return 40;
++}
++
++#endif /* end of HWIMG_SUPPORT*/
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_mac.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_mac.h
+new file mode 100644
+index 000000000..576d12db0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_mac.h
+@@ -0,0 +1,33 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/*Image2HeaderVersion: 3.5.2*/
++#if (RTL8723D_SUPPORT == 1)
++#ifndef __INC_MP_MAC_HW_IMG_8723D_H
++#define __INC_MP_MAC_HW_IMG_8723D_H
++
++
++/******************************************************************************
++*                           mac_reg.TXT
++******************************************************************************/
++
++void
++odm_read_and_config_mp_8723d_mac_reg( /* tc: Test Chip, mp: mp Chip*/
++				     struct dm_struct *dm);
++u32 odm_get_version_mp_8723d_mac_reg(void);
++
++#endif
++#endif /* end of HWIMG_SUPPORT*/
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_rf.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_rf.c
+new file mode 100644
+index 000000000..9a0f69f16
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_rf.c
+@@ -0,0 +1,1182 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/*Image2HeaderVersion: 3.5.2*/
++#include "mp_precomp.h"
++#include "../phydm_precomp.h"
++
++#if (RTL8723D_SUPPORT == 1)
++static boolean
++check_positive(
++	struct dm_struct *dm,
++	const u32	condition1,
++	const u32	condition2,
++	const u32	condition3,
++	const u32	condition4
++)
++{
++	u8	_board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
++			((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
++			((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
++			((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
++			((dm->board_type & BIT(2)) >> 2) << 4 | /* _BT*/
++			((dm->board_type & BIT(1)) >> 1) << 5 | /* _NGFF*/
++			((dm->board_type & BIT(5)) >> 5) << 6;  /* _TRSWT*/
++
++	u32	cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
++
++	u8	cut_version_for_para = (dm->cut_version ==  ODM_CUT_A) ? 15 : dm->cut_version;
++	u8	pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type;
++
++	u32	driver1 = cut_version_for_para << 24 |
++			(dm->support_interface & 0xF0) << 16 |
++			dm->support_platform << 16 |
++			pkg_type_for_para << 12 |
++			(dm->support_interface & 0x0F) << 8  |
++			_board_type;
++
++	u32	driver2 = (dm->type_glna & 0xFF) <<  0 |
++			(dm->type_gpa & 0xFF)  <<  8 |
++			(dm->type_alna & 0xFF) << 16 |
++			(dm->type_apa & 0xFF)  << 24;
++
++	u32	driver3 = 0;
++
++	u32	driver4 = (dm->type_glna & 0xFF00) >>  8 |
++			(dm->type_gpa & 0xFF00) |
++			(dm->type_alna & 0xFF00) << 8 |
++			(dm->type_apa & 0xFF00)  << 16;
++
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
++		  __func__, cond1, cond2, cond3, cond4);
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
++		  __func__, driver1, driver2, driver3, driver4);
++
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "	(Platform, Interface) = (0x%X, 0x%X)\n",
++		  dm->support_platform, dm->support_interface);
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "	(Board, Package) = (0x%X, 0x%X)\n", dm->board_type,
++		  dm->package_type);
++
++
++	/*============== value Defined Check ===============*/
++	/*QFN type [15:12] and cut version [27:24] need to do value check*/
++
++	if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
++		return false;
++	if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
++		return false;
++
++	/*=============== Bit Defined Check ================*/
++	/* We don't care [31:28] */
++
++	cond1 &= 0x00FF0FFF;
++	driver1 &= 0x00FF0FFF;
++
++	if ((cond1 & driver1) == cond1) {
++		u32	bit_mask = 0;
++
++		if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
++			return true;
++
++		if ((cond1 & BIT(0)) != 0) /*GLNA*/
++			bit_mask |= 0x000000FF;
++		if ((cond1 & BIT(1)) != 0) /*GPA*/
++			bit_mask |= 0x0000FF00;
++		if ((cond1 & BIT(2)) != 0) /*ALNA*/
++			bit_mask |= 0x00FF0000;
++		if ((cond1 & BIT(3)) != 0) /*APA*/
++			bit_mask |= 0xFF000000;
++
++		if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask)))  /* board_type of each RF path is matched*/
++			return true;
++		else
++			return false;
++	} else
++		return false;
++}
++
++/******************************************************************************
++*                           radioa.TXT
++******************************************************************************/
++
++u32 array_mp_8723d_radioa[] = {
++		0x050, 0x0001C000,
++		0x049, 0x0004AA00,
++		0x000, 0x00010000,
++		0x0B1, 0x00054573,
++		0x0B4, 0x000508AB,
++		0x0B7, 0x00014787,
++		0x0B8, 0x000064CB,
++		0x01B, 0x00073A40,
++		0x051, 0x00038CAF,
++		0x052, 0x000FCCA3,
++		0x053, 0x00090F38,
++		0x054, 0x00011083,
++		0x057, 0x000D0000,
++		0x08D, 0x00000A1A,
++		0x082, 0x00082AAC,
++		0x08E, 0x00076940,
++		0x08F, 0x00088400,
++		0x061, 0x00038CAF,
++		0x062, 0x000FCCA3,
++		0x063, 0x00090F38,
++		0x064, 0x00011083,
++		0x067, 0x000D0000,
++		0x092, 0x00082AAC,
++		0x0EF, 0x00000400,
++		0x030, 0x000008CA,
++		0x030, 0x000018CA,
++		0x030, 0x000028CA,
++		0x030, 0x000038CA,
++		0x0EF, 0x00000000,
++		0x0EE, 0x00000400,
++		0x030, 0x000008CA,
++		0x030, 0x000018CA,
++		0x030, 0x000028CA,
++		0x030, 0x000038CA,
++		0x0EE, 0x00000000,
++		0x0EF, 0x00000100,
++		0x033, 0x00000000,
++		0x03F, 0x0000CCA3,
++		0x033, 0x00000001,
++		0x03F, 0x0000CCA3,
++		0x033, 0x00000002,
++		0x03F, 0x0000CCA3,
++		0x033, 0x00000003,
++		0x03F, 0x0000CCA3,
++		0x033, 0x00000004,
++		0x03F, 0x0000CCA3,
++		0x033, 0x00000005,
++		0x03F, 0x0000CCA3,
++		0x033, 0x00000006,
++		0x03F, 0x0000CCA3,
++		0x033, 0x00000007,
++		0x03F, 0x0000CCA3,
++		0x0EF, 0x00000000,
++		0x0EE, 0x00000100,
++		0x033, 0x00000000,
++		0x03F, 0x0000CCA3,
++		0x033, 0x00000001,
++		0x03F, 0x0000CCA3,
++		0x033, 0x00000002,
++		0x03F, 0x0000CCA3,
++		0x033, 0x00000003,
++		0x03F, 0x0000CCA3,
++		0x033, 0x00000004,
++		0x03F, 0x0000CCA3,
++		0x033, 0x00000005,
++		0x03F, 0x0000CCA3,
++		0x033, 0x00000006,
++		0x03F, 0x0000CCA3,
++		0x033, 0x00000007,
++		0x03F, 0x0000CCA3,
++		0x0EE, 0x00000000,
++		0x0EF, 0x00000800,
++		0x030, 0x0000002D,
++		0x030, 0x0000122C,
++		0x030, 0x0000222F,
++		0x030, 0x0000326C,
++		0x030, 0x0000466B,
++		0x030, 0x0000566E,
++		0x030, 0x000066EB,
++		0x030, 0x000077EC,
++		0x030, 0x000087EF,
++		0x030, 0x000097F2,
++		0x030, 0x0000A7F5,
++		0x0EF, 0x00000000,
++		0x0EE, 0x00000800,
++		0x030, 0x00000001,
++		0x030, 0x00001011,
++		0x030, 0x00002011,
++		0x030, 0x00003013,
++		0x030, 0x00004033,
++		0x030, 0x00005033,
++		0x030, 0x00006037,
++		0x030, 0x0000703F,
++		0x030, 0x0000803F,
++		0x030, 0x0000903F,
++		0x030, 0x0000A03F,
++		0x0EE, 0x00000000,
++		0x082, 0x00083B8C,
++		0x0ED, 0x00000008,
++		0x030, 0x000030F6,
++		0x030, 0x00002004,
++		0x030, 0x000010F6,
++		0x030, 0x000000F6,
++		0x0ED, 0x00000000,
++		0x092, 0x00083B8C,
++		0x0EC, 0x00000008,
++		0x030, 0x000030F6,
++		0x030, 0x00002004,
++		0x030, 0x000010F6,
++		0x030, 0x000000F6,
++		0x0EC, 0x00000000,
++		0x0EF, 0x00010000,
++		0x030, 0x0001C11C,
++		0x030, 0x000181F4,
++		0x030, 0x00014108,
++		0x030, 0x000101E4,
++		0x030, 0x0000C11C,
++		0x030, 0x000081F4,
++		0x030, 0x00004108,
++		0x030, 0x000001E4,
++		0x0EF, 0x00000000,
++		0x0EE, 0x00010000,
++		0x030, 0x0001C11C,
++		0x030, 0x000181F4,
++		0x030, 0x00014108,
++		0x030, 0x000101E4,
++		0x030, 0x0000C11C,
++		0x030, 0x000081F4,
++		0x030, 0x00004108,
++		0x030, 0x000001E4,
++		0x0EE, 0x00000000,
++		0x0EF, 0x00080000,
++		0x033, 0x00000007,
++		0x03E, 0x0000005F,
++		0x03F, 0x000B3FDB,
++		0x033, 0x00000004,
++		0x03E, 0x0000005D,
++		0x03F, 0x000BFFE0,
++		0x033, 0x00000005,
++		0x03E, 0x0000005D,
++		0x03F, 0x000FBFCE,
++		0x033, 0x00000006,
++		0x03E, 0x0000005F,
++		0x03F, 0x000A7FFB,
++		0x0EF, 0x00000000,
++		0x0EE, 0x00000002,
++		0x030, 0x00000001,
++		0x030, 0x00002001,
++		0x030, 0x00004001,
++		0x030, 0x00007001,
++		0x030, 0x00006001,
++		0x030, 0x00020001,
++		0x030, 0x00022001,
++		0x030, 0x00024001,
++		0x030, 0x00027001,
++		0x030, 0x00026001,
++		0x030, 0x00034001,
++		0x030, 0x00037001,
++		0x030, 0x00036001,
++		0x030, 0x00008000,
++		0x030, 0x0000A000,
++		0x030, 0x0000C000,
++	0x83000100,	0x00000000,	0x40000000,	0x00000000,
++		0x030, 0x0000E024,
++	0xA0000000,	0x00000000,
++		0x030, 0x0000E000,
++	0xB0000000,	0x00000000,
++		0x030, 0x0001C000,
++		0x030, 0x0001E000,
++		0x0EE, 0x00000000,
++		0x0EE, 0x00020000,
++		0x0EF, 0x00020000,
++		0x030, 0x00000F75,
++		0x030, 0x00002F55,
++		0x030, 0x00003F75,
++		0x0EE, 0x00000000,
++		0x0EF, 0x00000000,
++		0x018, 0x00008401,
++		0xFFE, 0x00000000,
++
++};
++
++void
++odm_read_and_config_mp_8723d_radioa(struct dm_struct *dm)
++{
++	u32	i = 0;
++	u8	c_cond;
++	boolean	is_matched = true, is_skipped = false;
++	u32	array_len = sizeof(array_mp_8723d_radioa) / sizeof(u32);
++	u32	*array = array_mp_8723d_radioa;
++
++	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
++
++	while ((i + 1) < array_len) {
++		v1 = array[i];
++		v2 = array[i + 1];
++
++		if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
++			if (v1 & BIT(31)) {/* positive condition*/
++				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
++				if (c_cond == COND_ENDIF) {/*end*/
++					is_matched = true;
++					is_skipped = false;
++					PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
++				} else if (c_cond == COND_ELSE) { /*else*/
++					is_matched = is_skipped ? false : true;
++					PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
++				} else {/*if , else if*/
++					pre_v1 = v1;
++					pre_v2 = v2;
++					PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
++				}
++			} else if (v1 & BIT(30)) { /*negative condition*/
++				if (is_skipped == false) {
++					if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
++						is_matched = true;
++						is_skipped = true;
++					} else {
++						is_matched = false;
++						is_skipped = false;
++					}
++				} else
++					is_matched = false;
++			}
++		} else {
++			if (is_matched)
++				odm_config_rf_radio_a_8723d(dm, v1, v2);
++		}
++		i = i + 2;
++	}
++}
++
++u32
++odm_get_version_mp_8723d_radioa(void)
++{
++		return 40;
++}
++
++/******************************************************************************
++*                           txpowertrack_pcie.TXT
++******************************************************************************/
++
++#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_pcie_8723d[][DELTA_SWINGIDX_SIZE] = {
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18},
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
++};
++u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_pcie_8723d[][DELTA_SWINGIDX_SIZE] = {
++	{0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++};
++u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_pcie_8723d[][DELTA_SWINGIDX_SIZE] = {
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18},
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
++};
++u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_pcie_8723d[][DELTA_SWINGIDX_SIZE] = {
++	{0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++};
++u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_pcie_8723d[]    = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10};
++u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_pcie_8723d[]    = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10};
++u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_pcie_8723d[]    = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10};
++u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_pcie_8723d[]    = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10};
++u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_pcie_8723d[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11};
++u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_pcie_8723d[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11};
++u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_pcie_8723d[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11};
++u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_pcie_8723d[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11};
++#endif
++
++void
++odm_read_and_config_mp_8723d_txpowertrack_pcie(struct dm_struct *dm)
++{
++#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++	struct dm_rf_calibration_struct  *cali_info = &(dm->rf_calibrate_info);
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8723d\n");
++
++
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_pcie_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_pcie_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_pcie_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_pcie_8723d, DELTA_SWINGIDX_SIZE);
++
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_pcie_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_pcie_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_pcie_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_pcie_8723d, DELTA_SWINGIDX_SIZE);
++
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_pcie_8723d, DELTA_SWINGIDX_SIZE * 3);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_pcie_8723d, DELTA_SWINGIDX_SIZE * 3);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_pcie_8723d, DELTA_SWINGIDX_SIZE * 3);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_pcie_8723d, DELTA_SWINGIDX_SIZE * 3);
++#endif
++}
++
++/******************************************************************************
++*                           txpowertrack_sdio.TXT
++******************************************************************************/
++
++#if DEV_BUS_TYPE == RT_SDIO_INTERFACE
++u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_sdio_8723d[][DELTA_SWINGIDX_SIZE] = {
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18},
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
++};
++u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_sdio_8723d[][DELTA_SWINGIDX_SIZE] = {
++	{0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++};
++u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_sdio_8723d[][DELTA_SWINGIDX_SIZE] = {
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18},
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
++};
++u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_sdio_8723d[][DELTA_SWINGIDX_SIZE] = {
++	{0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++};
++u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_sdio_8723d[]    = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10};
++u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_sdio_8723d[]    = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10};
++u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_sdio_8723d[]    = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10};
++u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_sdio_8723d[]    = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10};
++u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_sdio_8723d[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11};
++u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_sdio_8723d[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11};
++u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_sdio_8723d[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11};
++u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_sdio_8723d[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11};
++#endif
++
++void
++odm_read_and_config_mp_8723d_txpowertrack_sdio(struct dm_struct *dm)
++{
++#if DEV_BUS_TYPE == RT_SDIO_INTERFACE
++	struct dm_rf_calibration_struct  *cali_info = &(dm->rf_calibrate_info);
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8723d\n");
++
++
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_sdio_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_sdio_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_sdio_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_sdio_8723d, DELTA_SWINGIDX_SIZE);
++
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_sdio_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_sdio_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_sdio_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_sdio_8723d, DELTA_SWINGIDX_SIZE);
++
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_sdio_8723d, DELTA_SWINGIDX_SIZE * 3);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_sdio_8723d, DELTA_SWINGIDX_SIZE * 3);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_sdio_8723d, DELTA_SWINGIDX_SIZE * 3);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_sdio_8723d, DELTA_SWINGIDX_SIZE * 3);
++#endif
++}
++
++/******************************************************************************
++*                           txpowertrack_usb.TXT
++******************************************************************************/
++
++#if DEV_BUS_TYPE == RT_USB_INTERFACE
++u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_usb_8723d[][DELTA_SWINGIDX_SIZE] = {
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18},
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
++};
++u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_usb_8723d[][DELTA_SWINGIDX_SIZE] = {
++	{0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++};
++u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_usb_8723d[][DELTA_SWINGIDX_SIZE] = {
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18},
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
++	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
++};
++u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_usb_8723d[][DELTA_SWINGIDX_SIZE] = {
++	{0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
++};
++u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_usb_8723d[]    = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10};
++u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_usb_8723d[]    = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10};
++u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_usb_8723d[]    = {0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10};
++u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_usb_8723d[]    = {0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10};
++u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_usb_8723d[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11};
++u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_usb_8723d[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11};
++u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_usb_8723d[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11};
++u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_usb_8723d[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11};
++#endif
++
++void
++odm_read_and_config_mp_8723d_txpowertrack_usb(struct dm_struct *dm)
++{
++#if DEV_BUS_TYPE == RT_USB_INTERFACE
++	struct dm_rf_calibration_struct  *cali_info = &(dm->rf_calibrate_info);
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8723d\n");
++
++
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_usb_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_usb_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_usb_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_usb_8723d, DELTA_SWINGIDX_SIZE);
++
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_usb_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_usb_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_usb_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_usb_8723d, DELTA_SWINGIDX_SIZE);
++
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_usb_8723d, DELTA_SWINGIDX_SIZE * 3);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_usb_8723d, DELTA_SWINGIDX_SIZE * 3);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_usb_8723d, DELTA_SWINGIDX_SIZE * 3);
++	odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_usb_8723d, DELTA_SWINGIDX_SIZE * 3);
++#endif
++}
++
++/******************************************************************************
++*                           txpwr_lmt.TXT
++******************************************************************************/
++
++const char *array_mp_8723d_txpwr_lmt[] = {
++	"FCC", "2.4G", "20M", "CCK", "1T", "01", "30",
++	"ETSI", "2.4G", "20M", "CCK", "1T", "01", "30",
++	"MKK", "2.4G", "20M", "CCK", "1T", "01", "30",
++	"FCC", "2.4G", "20M", "CCK", "1T", "02", "30",
++	"ETSI", "2.4G", "20M", "CCK", "1T", "02", "30",
++	"MKK", "2.4G", "20M", "CCK", "1T", "02", "30",
++	"FCC", "2.4G", "20M", "CCK", "1T", "03", "30",
++	"ETSI", "2.4G", "20M", "CCK", "1T", "03", "30",
++	"MKK", "2.4G", "20M", "CCK", "1T", "03", "30",
++	"FCC", "2.4G", "20M", "CCK", "1T", "04", "30",
++	"ETSI", "2.4G", "20M", "CCK", "1T", "04", "30",
++	"MKK", "2.4G", "20M", "CCK", "1T", "04", "30",
++	"FCC", "2.4G", "20M", "CCK", "1T", "05", "30",
++	"ETSI", "2.4G", "20M", "CCK", "1T", "05", "30",
++	"MKK", "2.4G", "20M", "CCK", "1T", "05", "30",
++	"FCC", "2.4G", "20M", "CCK", "1T", "06", "30",
++	"ETSI", "2.4G", "20M", "CCK", "1T", "06", "30",
++	"MKK", "2.4G", "20M", "CCK", "1T", "06", "30",
++	"FCC", "2.4G", "20M", "CCK", "1T", "07", "30",
++	"ETSI", "2.4G", "20M", "CCK", "1T", "07", "30",
++	"MKK", "2.4G", "20M", "CCK", "1T", "07", "30",
++	"FCC", "2.4G", "20M", "CCK", "1T", "08", "30",
++	"ETSI", "2.4G", "20M", "CCK", "1T", "08", "30",
++	"MKK", "2.4G", "20M", "CCK", "1T", "08", "30",
++	"FCC", "2.4G", "20M", "CCK", "1T", "09", "30",
++	"ETSI", "2.4G", "20M", "CCK", "1T", "09", "30",
++	"MKK", "2.4G", "20M", "CCK", "1T", "09", "30",
++	"FCC", "2.4G", "20M", "CCK", "1T", "10", "30",
++	"ETSI", "2.4G", "20M", "CCK", "1T", "10", "30",
++	"MKK", "2.4G", "20M", "CCK", "1T", "10", "30",
++	"FCC", "2.4G", "20M", "CCK", "1T", "11", "30",
++	"ETSI", "2.4G", "20M", "CCK", "1T", "11", "30",
++	"MKK", "2.4G", "20M", "CCK", "1T", "11", "30",
++	"FCC", "2.4G", "20M", "CCK", "1T", "12", "30",
++	"ETSI", "2.4G", "20M", "CCK", "1T", "12", "30",
++	"MKK", "2.4G", "20M", "CCK", "1T", "12", "30",
++	"FCC", "2.4G", "20M", "CCK", "1T", "13", "17",
++	"ETSI", "2.4G", "20M", "CCK", "1T", "13", "30",
++	"MKK", "2.4G", "20M", "CCK", "1T", "13", "30",
++	"FCC", "2.4G", "20M", "CCK", "1T", "14", "63",
++	"ETSI", "2.4G", "20M", "CCK", "1T", "14", "63",
++	"MKK", "2.4G", "20M", "CCK", "1T", "14", "30",
++	"FCC", "2.4G", "20M", "OFDM", "1T", "01", "26",
++	"ETSI", "2.4G", "20M", "OFDM", "1T", "01", "31",
++	"MKK", "2.4G", "20M", "OFDM", "1T", "01", "31",
++	"FCC", "2.4G", "20M", "OFDM", "1T", "02", "28",
++	"ETSI", "2.4G", "20M", "OFDM", "1T", "02", "31",
++	"MKK", "2.4G", "20M", "OFDM", "1T", "02", "31",
++	"FCC", "2.4G", "20M", "OFDM", "1T", "03", "30",
++	"ETSI", "2.4G", "20M", "OFDM", "1T", "03", "31",
++	"MKK", "2.4G", "20M", "OFDM", "1T", "03", "31",
++	"FCC", "2.4G", "20M", "OFDM", "1T", "04", "30",
++	"ETSI", "2.4G", "20M", "OFDM", "1T", "04", "31",
++	"MKK", "2.4G", "20M", "OFDM", "1T", "04", "31",
++	"FCC", "2.4G", "20M", "OFDM", "1T", "05", "30",
++	"ETSI", "2.4G", "20M", "OFDM", "1T", "05", "31",
++	"MKK", "2.4G", "20M", "OFDM", "1T", "05", "31",
++	"FCC", "2.4G", "20M", "OFDM", "1T", "06", "30",
++	"ETSI", "2.4G", "20M", "OFDM", "1T", "06", "31",
++	"MKK", "2.4G", "20M", "OFDM", "1T", "06", "31",
++	"FCC", "2.4G", "20M", "OFDM", "1T", "07", "30",
++	"ETSI", "2.4G", "20M", "OFDM", "1T", "07", "31",
++	"MKK", "2.4G", "20M", "OFDM", "1T", "07", "31",
++	"FCC", "2.4G", "20M", "OFDM", "1T", "08", "30",
++	"ETSI", "2.4G", "20M", "OFDM", "1T", "08", "31",
++	"MKK", "2.4G", "20M", "OFDM", "1T", "08", "31",
++	"FCC", "2.4G", "20M", "OFDM", "1T", "09", "30",
++	"ETSI", "2.4G", "20M", "OFDM", "1T", "09", "31",
++	"MKK", "2.4G", "20M", "OFDM", "1T", "09", "31",
++	"FCC", "2.4G", "20M", "OFDM", "1T", "10", "28",
++	"ETSI", "2.4G", "20M", "OFDM", "1T", "10", "31",
++	"MKK", "2.4G", "20M", "OFDM", "1T", "10", "31",
++	"FCC", "2.4G", "20M", "OFDM", "1T", "11", "26",
++	"ETSI", "2.4G", "20M", "OFDM", "1T", "11", "31",
++	"MKK", "2.4G", "20M", "OFDM", "1T", "11", "31",
++	"FCC", "2.4G", "20M", "OFDM", "1T", "12", "24",
++	"ETSI", "2.4G", "20M", "OFDM", "1T", "12", "31",
++	"MKK", "2.4G", "20M", "OFDM", "1T", "12", "31",
++	"FCC", "2.4G", "20M", "OFDM", "1T", "13", "14",
++	"ETSI", "2.4G", "20M", "OFDM", "1T", "13", "31",
++	"MKK", "2.4G", "20M", "OFDM", "1T", "13", "31",
++	"FCC", "2.4G", "20M", "OFDM", "1T", "14", "63",
++	"ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63",
++	"MKK", "2.4G", "20M", "OFDM", "1T", "14", "63",
++	"FCC", "2.4G", "20M", "HT", "1T", "01", "24",
++	"ETSI", "2.4G", "20M", "HT", "1T", "01", "31",
++	"MKK", "2.4G", "20M", "HT", "1T", "01", "31",
++	"FCC", "2.4G", "20M", "HT", "1T", "02", "26",
++	"ETSI", "2.4G", "20M", "HT", "1T", "02", "31",
++	"MKK", "2.4G", "20M", "HT", "1T", "02", "31",
++	"FCC", "2.4G", "20M", "HT", "1T", "03", "30",
++	"ETSI", "2.4G", "20M", "HT", "1T", "03", "31",
++	"MKK", "2.4G", "20M", "HT", "1T", "03", "31",
++	"FCC", "2.4G", "20M", "HT", "1T", "04", "30",
++	"ETSI", "2.4G", "20M", "HT", "1T", "04", "31",
++	"MKK", "2.4G", "20M", "HT", "1T", "04", "31",
++	"FCC", "2.4G", "20M", "HT", "1T", "05", "30",
++	"ETSI", "2.4G", "20M", "HT", "1T", "05", "31",
++	"MKK", "2.4G", "20M", "HT", "1T", "05", "31",
++	"FCC", "2.4G", "20M", "HT", "1T", "06", "30",
++	"ETSI", "2.4G", "20M", "HT", "1T", "06", "31",
++	"MKK", "2.4G", "20M", "HT", "1T", "06", "31",
++	"FCC", "2.4G", "20M", "HT", "1T", "07", "30",
++	"ETSI", "2.4G", "20M", "HT", "1T", "07", "31",
++	"MKK", "2.4G", "20M", "HT", "1T", "07", "31",
++	"FCC", "2.4G", "20M", "HT", "1T", "08", "30",
++	"ETSI", "2.4G", "20M", "HT", "1T", "08", "31",
++	"MKK", "2.4G", "20M", "HT", "1T", "08", "31",
++	"FCC", "2.4G", "20M", "HT", "1T", "09", "30",
++	"ETSI", "2.4G", "20M", "HT", "1T", "09", "31",
++	"MKK", "2.4G", "20M", "HT", "1T", "09", "31",
++	"FCC", "2.4G", "20M", "HT", "1T", "10", "26",
++	"ETSI", "2.4G", "20M", "HT", "1T", "10", "31",
++	"MKK", "2.4G", "20M", "HT", "1T", "10", "31",
++	"FCC", "2.4G", "20M", "HT", "1T", "11", "24",
++	"ETSI", "2.4G", "20M", "HT", "1T", "11", "31",
++	"MKK", "2.4G", "20M", "HT", "1T", "11", "31",
++	"FCC", "2.4G", "20M", "HT", "1T", "12", "23",
++	"ETSI", "2.4G", "20M", "HT", "1T", "12", "31",
++	"MKK", "2.4G", "20M", "HT", "1T", "12", "31",
++	"FCC", "2.4G", "20M", "HT", "1T", "13", "13",
++	"ETSI", "2.4G", "20M", "HT", "1T", "13", "31",
++	"MKK", "2.4G", "20M", "HT", "1T", "13", "31",
++	"FCC", "2.4G", "20M", "HT", "1T", "14", "63",
++	"ETSI", "2.4G", "20M", "HT", "1T", "14", "63",
++	"MKK", "2.4G", "20M", "HT", "1T", "14", "63",
++	"FCC", "2.4G", "20M", "HT", "2T", "01", "28",
++	"ETSI", "2.4G", "20M", "HT", "2T", "01", "30",
++	"MKK", "2.4G", "20M", "HT", "2T", "01", "30",
++	"FCC", "2.4G", "20M", "HT", "2T", "02", "28",
++	"ETSI", "2.4G", "20M", "HT", "2T", "02", "30",
++	"MKK", "2.4G", "20M", "HT", "2T", "02", "30",
++	"FCC", "2.4G", "20M", "HT", "2T", "03", "30",
++	"ETSI", "2.4G", "20M", "HT", "2T", "03", "30",
++	"MKK", "2.4G", "20M", "HT", "2T", "03", "30",
++	"FCC", "2.4G", "20M", "HT", "2T", "04", "30",
++	"ETSI", "2.4G", "20M", "HT", "2T", "04", "30",
++	"MKK", "2.4G", "20M", "HT", "2T", "04", "30",
++	"FCC", "2.4G", "20M", "HT", "2T", "05", "30",
++	"ETSI", "2.4G", "20M", "HT", "2T", "05", "30",
++	"MKK", "2.4G", "20M", "HT", "2T", "05", "30",
++	"FCC", "2.4G", "20M", "HT", "2T", "06", "30",
++	"ETSI", "2.4G", "20M", "HT", "2T", "06", "30",
++	"MKK", "2.4G", "20M", "HT", "2T", "06", "30",
++	"FCC", "2.4G", "20M", "HT", "2T", "07", "30",
++	"ETSI", "2.4G", "20M", "HT", "2T", "07", "30",
++	"MKK", "2.4G", "20M", "HT", "2T", "07", "30",
++	"FCC", "2.4G", "20M", "HT", "2T", "08", "30",
++	"ETSI", "2.4G", "20M", "HT", "2T", "08", "30",
++	"MKK", "2.4G", "20M", "HT", "2T", "08", "30",
++	"FCC", "2.4G", "20M", "HT", "2T", "09", "28",
++	"ETSI", "2.4G", "20M", "HT", "2T", "09", "30",
++	"MKK", "2.4G", "20M", "HT", "2T", "09", "30",
++	"FCC", "2.4G", "20M", "HT", "2T", "10", "28",
++	"ETSI", "2.4G", "20M", "HT", "2T", "10", "30",
++	"MKK", "2.4G", "20M", "HT", "2T", "10", "30",
++	"FCC", "2.4G", "20M", "HT", "2T", "11", "28",
++	"ETSI", "2.4G", "20M", "HT", "2T", "11", "30",
++	"MKK", "2.4G", "20M", "HT", "2T", "11", "30",
++	"FCC", "2.4G", "20M", "HT", "2T", "12", "63",
++	"ETSI", "2.4G", "20M", "HT", "2T", "12", "30",
++	"MKK", "2.4G", "20M", "HT", "2T", "12", "30",
++	"FCC", "2.4G", "20M", "HT", "2T", "13", "63",
++	"ETSI", "2.4G", "20M", "HT", "2T", "13", "30",
++	"MKK", "2.4G", "20M", "HT", "2T", "13", "30",
++	"FCC", "2.4G", "20M", "HT", "2T", "14", "63",
++	"ETSI", "2.4G", "20M", "HT", "2T", "14", "63",
++	"MKK", "2.4G", "20M", "HT", "2T", "14", "63",
++	"FCC", "2.4G", "40M", "HT", "1T", "01", "63",
++	"ETSI", "2.4G", "40M", "HT", "1T", "01", "63",
++	"MKK", "2.4G", "40M", "HT", "1T", "01", "63",
++	"FCC", "2.4G", "40M", "HT", "1T", "02", "63",
++	"ETSI", "2.4G", "40M", "HT", "1T", "02", "63",
++	"MKK", "2.4G", "40M", "HT", "1T", "02", "63",
++	"FCC", "2.4G", "40M", "HT", "1T", "03", "24",
++	"ETSI", "2.4G", "40M", "HT", "1T", "03", "30",
++	"MKK", "2.4G", "40M", "HT", "1T", "03", "30",
++	"FCC", "2.4G", "40M", "HT", "1T", "04", "24",
++	"ETSI", "2.4G", "40M", "HT", "1T", "04", "30",
++	"MKK", "2.4G", "40M", "HT", "1T", "04", "30",
++	"FCC", "2.4G", "40M", "HT", "1T", "05", "24",
++	"ETSI", "2.4G", "40M", "HT", "1T", "05", "30",
++	"MKK", "2.4G", "40M", "HT", "1T", "05", "30",
++	"FCC", "2.4G", "40M", "HT", "1T", "06", "24",
++	"ETSI", "2.4G", "40M", "HT", "1T", "06", "30",
++	"MKK", "2.4G", "40M", "HT", "1T", "06", "30",
++	"FCC", "2.4G", "40M", "HT", "1T", "07", "24",
++	"ETSI", "2.4G", "40M", "HT", "1T", "07", "30",
++	"MKK", "2.4G", "40M", "HT", "1T", "07", "30",
++	"FCC", "2.4G", "40M", "HT", "1T", "08", "24",
++	"ETSI", "2.4G", "40M", "HT", "1T", "08", "30",
++	"MKK", "2.4G", "40M", "HT", "1T", "08", "30",
++	"FCC", "2.4G", "40M", "HT", "1T", "09", "24",
++	"ETSI", "2.4G", "40M", "HT", "1T", "09", "30",
++	"MKK", "2.4G", "40M", "HT", "1T", "09", "30",
++	"FCC", "2.4G", "40M", "HT", "1T", "10", "22",
++	"ETSI", "2.4G", "40M", "HT", "1T", "10", "30",
++	"MKK", "2.4G", "40M", "HT", "1T", "10", "30",
++	"FCC", "2.4G", "40M", "HT", "1T", "11", "20",
++	"ETSI", "2.4G", "40M", "HT", "1T", "11", "30",
++	"MKK", "2.4G", "40M", "HT", "1T", "11", "30",
++	"FCC", "2.4G", "40M", "HT", "1T", "12", "63",
++	"ETSI", "2.4G", "40M", "HT", "1T", "12", "30",
++	"MKK", "2.4G", "40M", "HT", "1T", "12", "30",
++	"FCC", "2.4G", "40M", "HT", "1T", "13", "63",
++	"ETSI", "2.4G", "40M", "HT", "1T", "13", "30",
++	"MKK", "2.4G", "40M", "HT", "1T", "13", "30",
++	"FCC", "2.4G", "40M", "HT", "1T", "14", "63",
++	"ETSI", "2.4G", "40M", "HT", "1T", "14", "63",
++	"MKK", "2.4G", "40M", "HT", "1T", "14", "63",
++	"FCC", "2.4G", "40M", "HT", "2T", "01", "63",
++	"ETSI", "2.4G", "40M", "HT", "2T", "01", "63",
++	"MKK", "2.4G", "40M", "HT", "2T", "01", "63",
++	"FCC", "2.4G", "40M", "HT", "2T", "02", "63",
++	"ETSI", "2.4G", "40M", "HT", "2T", "02", "63",
++	"MKK", "2.4G", "40M", "HT", "2T", "02", "63",
++	"FCC", "2.4G", "40M", "HT", "2T", "03", "26",
++	"ETSI", "2.4G", "40M", "HT", "2T", "03", "26",
++	"MKK", "2.4G", "40M", "HT", "2T", "03", "26",
++	"FCC", "2.4G", "40M", "HT", "2T", "04", "26",
++	"ETSI", "2.4G", "40M", "HT", "2T", "04", "26",
++	"MKK", "2.4G", "40M", "HT", "2T", "04", "26",
++	"FCC", "2.4G", "40M", "HT", "2T", "05", "26",
++	"ETSI", "2.4G", "40M", "HT", "2T", "05", "26",
++	"MKK", "2.4G", "40M", "HT", "2T", "05", "26",
++	"FCC", "2.4G", "40M", "HT", "2T", "06", "26",
++	"ETSI", "2.4G", "40M", "HT", "2T", "06", "26",
++	"MKK", "2.4G", "40M", "HT", "2T", "06", "26",
++	"FCC", "2.4G", "40M", "HT", "2T", "07", "26",
++	"ETSI", "2.4G", "40M", "HT", "2T", "07", "26",
++	"MKK", "2.4G", "40M", "HT", "2T", "07", "26",
++	"FCC", "2.4G", "40M", "HT", "2T", "08", "26",
++	"ETSI", "2.4G", "40M", "HT", "2T", "08", "26",
++	"MKK", "2.4G", "40M", "HT", "2T", "08", "26",
++	"FCC", "2.4G", "40M", "HT", "2T", "09", "26",
++	"ETSI", "2.4G", "40M", "HT", "2T", "09", "26",
++	"MKK", "2.4G", "40M", "HT", "2T", "09", "26",
++	"FCC", "2.4G", "40M", "HT", "2T", "10", "26",
++	"ETSI", "2.4G", "40M", "HT", "2T", "10", "26",
++	"MKK", "2.4G", "40M", "HT", "2T", "10", "26",
++	"FCC", "2.4G", "40M", "HT", "2T", "11", "26",
++	"ETSI", "2.4G", "40M", "HT", "2T", "11", "26",
++	"MKK", "2.4G", "40M", "HT", "2T", "11", "26",
++	"FCC", "2.4G", "40M", "HT", "2T", "12", "63",
++	"ETSI", "2.4G", "40M", "HT", "2T", "12", "26",
++	"MKK", "2.4G", "40M", "HT", "2T", "12", "26",
++	"FCC", "2.4G", "40M", "HT", "2T", "13", "63",
++	"ETSI", "2.4G", "40M", "HT", "2T", "13", "26",
++	"MKK", "2.4G", "40M", "HT", "2T", "13", "26",
++	"FCC", "2.4G", "40M", "HT", "2T", "14", "63",
++	"ETSI", "2.4G", "40M", "HT", "2T", "14", "63",
++	"MKK", "2.4G", "40M", "HT", "2T", "14", "63",
++	"FCC", "5G", "20M", "OFDM", "1T", "36", "30",
++	"ETSI", "5G", "20M", "OFDM", "1T", "36", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "36", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "40", "30",
++	"ETSI", "5G", "20M", "OFDM", "1T", "40", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "40", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "44", "30",
++	"ETSI", "5G", "20M", "OFDM", "1T", "44", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "44", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "48", "30",
++	"ETSI", "5G", "20M", "OFDM", "1T", "48", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "48", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "52", "34",
++	"ETSI", "5G", "20M", "OFDM", "1T", "52", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "52", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "56", "34",
++	"ETSI", "5G", "20M", "OFDM", "1T", "56", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "56", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "60", "32",
++	"ETSI", "5G", "20M", "OFDM", "1T", "60", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "60", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "64", "28",
++	"ETSI", "5G", "20M", "OFDM", "1T", "64", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "64", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "100", "30",
++	"ETSI", "5G", "20M", "OFDM", "1T", "100", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "100", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "114", "30",
++	"ETSI", "5G", "20M", "OFDM", "1T", "114", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "114", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "108", "32",
++	"ETSI", "5G", "20M", "OFDM", "1T", "108", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "108", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "112", "34",
++	"ETSI", "5G", "20M", "OFDM", "1T", "112", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "112", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "116", "34",
++	"ETSI", "5G", "20M", "OFDM", "1T", "116", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "116", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "120", "34",
++	"ETSI", "5G", "20M", "OFDM", "1T", "120", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "120", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "124", "34",
++	"ETSI", "5G", "20M", "OFDM", "1T", "124", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "124", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "128", "32",
++	"ETSI", "5G", "20M", "OFDM", "1T", "128", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "128", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "132", "30",
++	"ETSI", "5G", "20M", "OFDM", "1T", "132", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "132", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "136", "30",
++	"ETSI", "5G", "20M", "OFDM", "1T", "136", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "136", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "140", "28",
++	"ETSI", "5G", "20M", "OFDM", "1T", "140", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "140", "32",
++	"FCC", "5G", "20M", "OFDM", "1T", "149", "34",
++	"ETSI", "5G", "20M", "OFDM", "1T", "149", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "149", "63",
++	"FCC", "5G", "20M", "OFDM", "1T", "153", "34",
++	"ETSI", "5G", "20M", "OFDM", "1T", "153", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "153", "63",
++	"FCC", "5G", "20M", "OFDM", "1T", "157", "34",
++	"ETSI", "5G", "20M", "OFDM", "1T", "157", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "157", "63",
++	"FCC", "5G", "20M", "OFDM", "1T", "161", "34",
++	"ETSI", "5G", "20M", "OFDM", "1T", "161", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "161", "63",
++	"FCC", "5G", "20M", "OFDM", "1T", "165", "34",
++	"ETSI", "5G", "20M", "OFDM", "1T", "165", "32",
++	"MKK", "5G", "20M", "OFDM", "1T", "165", "63",
++	"FCC", "5G", "20M", "HT", "1T", "36", "30",
++	"ETSI", "5G", "20M", "HT", "1T", "36", "32",
++	"MKK", "5G", "20M", "HT", "1T", "36", "32",
++	"FCC", "5G", "20M", "HT", "1T", "40", "30",
++	"ETSI", "5G", "20M", "HT", "1T", "40", "32",
++	"MKK", "5G", "20M", "HT", "1T", "40", "32",
++	"FCC", "5G", "20M", "HT", "1T", "44", "30",
++	"ETSI", "5G", "20M", "HT", "1T", "44", "32",
++	"MKK", "5G", "20M", "HT", "1T", "44", "32",
++	"FCC", "5G", "20M", "HT", "1T", "48", "30",
++	"ETSI", "5G", "20M", "HT", "1T", "48", "32",
++	"MKK", "5G", "20M", "HT", "1T", "48", "32",
++	"FCC", "5G", "20M", "HT", "1T", "52", "34",
++	"ETSI", "5G", "20M", "HT", "1T", "52", "32",
++	"MKK", "5G", "20M", "HT", "1T", "52", "32",
++	"FCC", "5G", "20M", "HT", "1T", "56", "34",
++	"ETSI", "5G", "20M", "HT", "1T", "56", "32",
++	"MKK", "5G", "20M", "HT", "1T", "56", "32",
++	"FCC", "5G", "20M", "HT", "1T", "60", "32",
++	"ETSI", "5G", "20M", "HT", "1T", "60", "32",
++	"MKK", "5G", "20M", "HT", "1T", "60", "32",
++	"FCC", "5G", "20M", "HT", "1T", "64", "28",
++	"ETSI", "5G", "20M", "HT", "1T", "64", "32",
++	"MKK", "5G", "20M", "HT", "1T", "64", "32",
++	"FCC", "5G", "20M", "HT", "1T", "100", "30",
++	"ETSI", "5G", "20M", "HT", "1T", "100", "32",
++	"MKK", "5G", "20M", "HT", "1T", "100", "32",
++	"FCC", "5G", "20M", "HT", "1T", "114", "30",
++	"ETSI", "5G", "20M", "HT", "1T", "114", "32",
++	"MKK", "5G", "20M", "HT", "1T", "114", "32",
++	"FCC", "5G", "20M", "HT", "1T", "108", "32",
++	"ETSI", "5G", "20M", "HT", "1T", "108", "32",
++	"MKK", "5G", "20M", "HT", "1T", "108", "32",
++	"FCC", "5G", "20M", "HT", "1T", "112", "34",
++	"ETSI", "5G", "20M", "HT", "1T", "112", "32",
++	"MKK", "5G", "20M", "HT", "1T", "112", "32",
++	"FCC", "5G", "20M", "HT", "1T", "116", "34",
++	"ETSI", "5G", "20M", "HT", "1T", "116", "32",
++	"MKK", "5G", "20M", "HT", "1T", "116", "32",
++	"FCC", "5G", "20M", "HT", "1T", "120", "34",
++	"ETSI", "5G", "20M", "HT", "1T", "120", "32",
++	"MKK", "5G", "20M", "HT", "1T", "120", "32",
++	"FCC", "5G", "20M", "HT", "1T", "124", "34",
++	"ETSI", "5G", "20M", "HT", "1T", "124", "32",
++	"MKK", "5G", "20M", "HT", "1T", "124", "32",
++	"FCC", "5G", "20M", "HT", "1T", "128", "32",
++	"ETSI", "5G", "20M", "HT", "1T", "128", "32",
++	"MKK", "5G", "20M", "HT", "1T", "128", "32",
++	"FCC", "5G", "20M", "HT", "1T", "132", "30",
++	"ETSI", "5G", "20M", "HT", "1T", "132", "32",
++	"MKK", "5G", "20M", "HT", "1T", "132", "32",
++	"FCC", "5G", "20M", "HT", "1T", "136", "30",
++	"ETSI", "5G", "20M", "HT", "1T", "136", "32",
++	"MKK", "5G", "20M", "HT", "1T", "136", "32",
++	"FCC", "5G", "20M", "HT", "1T", "140", "28",
++	"ETSI", "5G", "20M", "HT", "1T", "140", "32",
++	"MKK", "5G", "20M", "HT", "1T", "140", "32",
++	"FCC", "5G", "20M", "HT", "1T", "149", "34",
++	"ETSI", "5G", "20M", "HT", "1T", "149", "32",
++	"MKK", "5G", "20M", "HT", "1T", "149", "63",
++	"FCC", "5G", "20M", "HT", "1T", "153", "34",
++	"ETSI", "5G", "20M", "HT", "1T", "153", "32",
++	"MKK", "5G", "20M", "HT", "1T", "153", "63",
++	"FCC", "5G", "20M", "HT", "1T", "157", "34",
++	"ETSI", "5G", "20M", "HT", "1T", "157", "32",
++	"MKK", "5G", "20M", "HT", "1T", "157", "63",
++	"FCC", "5G", "20M", "HT", "1T", "161", "34",
++	"ETSI", "5G", "20M", "HT", "1T", "161", "32",
++	"MKK", "5G", "20M", "HT", "1T", "161", "63",
++	"FCC", "5G", "20M", "HT", "1T", "165", "34",
++	"ETSI", "5G", "20M", "HT", "1T", "165", "32",
++	"MKK", "5G", "20M", "HT", "1T", "165", "63",
++	"FCC", "5G", "20M", "HT", "2T", "36", "28",
++	"ETSI", "5G", "20M", "HT", "2T", "36", "30",
++	"MKK", "5G", "20M", "HT", "2T", "36", "30",
++	"FCC", "5G", "20M", "HT", "2T", "40", "28",
++	"ETSI", "5G", "20M", "HT", "2T", "40", "30",
++	"MKK", "5G", "20M", "HT", "2T", "40", "30",
++	"FCC", "5G", "20M", "HT", "2T", "44", "28",
++	"ETSI", "5G", "20M", "HT", "2T", "44", "30",
++	"MKK", "5G", "20M", "HT", "2T", "44", "30",
++	"FCC", "5G", "20M", "HT", "2T", "48", "28",
++	"ETSI", "5G", "20M", "HT", "2T", "48", "30",
++	"MKK", "5G", "20M", "HT", "2T", "48", "30",
++	"FCC", "5G", "20M", "HT", "2T", "52", "34",
++	"ETSI", "5G", "20M", "HT", "2T", "52", "30",
++	"MKK", "5G", "20M", "HT", "2T", "52", "30",
++	"FCC", "5G", "20M", "HT", "2T", "56", "32",
++	"ETSI", "5G", "20M", "HT", "2T", "56", "30",
++	"MKK", "5G", "20M", "HT", "2T", "56", "30",
++	"FCC", "5G", "20M", "HT", "2T", "60", "30",
++	"ETSI", "5G", "20M", "HT", "2T", "60", "30",
++	"MKK", "5G", "20M", "HT", "2T", "60", "30",
++	"FCC", "5G", "20M", "HT", "2T", "64", "26",
++	"ETSI", "5G", "20M", "HT", "2T", "64", "30",
++	"MKK", "5G", "20M", "HT", "2T", "64", "30",
++	"FCC", "5G", "20M", "HT", "2T", "100", "28",
++	"ETSI", "5G", "20M", "HT", "2T", "100", "30",
++	"MKK", "5G", "20M", "HT", "2T", "100", "30",
++	"FCC", "5G", "20M", "HT", "2T", "114", "28",
++	"ETSI", "5G", "20M", "HT", "2T", "114", "30",
++	"MKK", "5G", "20M", "HT", "2T", "114", "30",
++	"FCC", "5G", "20M", "HT", "2T", "108", "30",
++	"ETSI", "5G", "20M", "HT", "2T", "108", "30",
++	"MKK", "5G", "20M", "HT", "2T", "108", "30",
++	"FCC", "5G", "20M", "HT", "2T", "112", "32",
++	"ETSI", "5G", "20M", "HT", "2T", "112", "30",
++	"MKK", "5G", "20M", "HT", "2T", "112", "30",
++	"FCC", "5G", "20M", "HT", "2T", "116", "32",
++	"ETSI", "5G", "20M", "HT", "2T", "116", "30",
++	"MKK", "5G", "20M", "HT", "2T", "116", "30",
++	"FCC", "5G", "20M", "HT", "2T", "120", "34",
++	"ETSI", "5G", "20M", "HT", "2T", "120", "30",
++	"MKK", "5G", "20M", "HT", "2T", "120", "30",
++	"FCC", "5G", "20M", "HT", "2T", "124", "32",
++	"ETSI", "5G", "20M", "HT", "2T", "124", "30",
++	"MKK", "5G", "20M", "HT", "2T", "124", "30",
++	"FCC", "5G", "20M", "HT", "2T", "128", "30",
++	"ETSI", "5G", "20M", "HT", "2T", "128", "30",
++	"MKK", "5G", "20M", "HT", "2T", "128", "30",
++	"FCC", "5G", "20M", "HT", "2T", "132", "28",
++	"ETSI", "5G", "20M", "HT", "2T", "132", "30",
++	"MKK", "5G", "20M", "HT", "2T", "132", "30",
++	"FCC", "5G", "20M", "HT", "2T", "136", "28",
++	"ETSI", "5G", "20M", "HT", "2T", "136", "30",
++	"MKK", "5G", "20M", "HT", "2T", "136", "30",
++	"FCC", "5G", "20M", "HT", "2T", "140", "26",
++	"ETSI", "5G", "20M", "HT", "2T", "140", "30",
++	"MKK", "5G", "20M", "HT", "2T", "140", "30",
++	"FCC", "5G", "20M", "HT", "2T", "149", "34",
++	"ETSI", "5G", "20M", "HT", "2T", "149", "30",
++	"MKK", "5G", "20M", "HT", "2T", "149", "63",
++	"FCC", "5G", "20M", "HT", "2T", "153", "34",
++	"ETSI", "5G", "20M", "HT", "2T", "153", "30",
++	"MKK", "5G", "20M", "HT", "2T", "153", "63",
++	"FCC", "5G", "20M", "HT", "2T", "157", "34",
++	"ETSI", "5G", "20M", "HT", "2T", "157", "30",
++	"MKK", "5G", "20M", "HT", "2T", "157", "63",
++	"FCC", "5G", "20M", "HT", "2T", "161", "34",
++	"ETSI", "5G", "20M", "HT", "2T", "161", "30",
++	"MKK", "5G", "20M", "HT", "2T", "161", "63",
++	"FCC", "5G", "20M", "HT", "2T", "165", "34",
++	"ETSI", "5G", "20M", "HT", "2T", "165", "30",
++	"MKK", "5G", "20M", "HT", "2T", "165", "63",
++	"FCC", "5G", "40M", "HT", "1T", "38", "30",
++	"ETSI", "5G", "40M", "HT", "1T", "38", "32",
++	"MKK", "5G", "40M", "HT", "1T", "38", "32",
++	"FCC", "5G", "40M", "HT", "1T", "46", "30",
++	"ETSI", "5G", "40M", "HT", "1T", "46", "32",
++	"MKK", "5G", "40M", "HT", "1T", "46", "32",
++	"FCC", "5G", "40M", "HT", "1T", "54", "32",
++	"ETSI", "5G", "40M", "HT", "1T", "54", "32",
++	"MKK", "5G", "40M", "HT", "1T", "54", "32",
++	"FCC", "5G", "40M", "HT", "1T", "62", "32",
++	"ETSI", "5G", "40M", "HT", "1T", "62", "32",
++	"MKK", "5G", "40M", "HT", "1T", "62", "32",
++	"FCC", "5G", "40M", "HT", "1T", "102", "28",
++	"ETSI", "5G", "40M", "HT", "1T", "102", "32",
++	"MKK", "5G", "40M", "HT", "1T", "102", "32",
++	"FCC", "5G", "40M", "HT", "1T", "110", "32",
++	"ETSI", "5G", "40M", "HT", "1T", "110", "32",
++	"MKK", "5G", "40M", "HT", "1T", "110", "32",
++	"FCC", "5G", "40M", "HT", "1T", "118", "34",
++	"ETSI", "5G", "40M", "HT", "1T", "118", "32",
++	"MKK", "5G", "40M", "HT", "1T", "118", "32",
++	"FCC", "5G", "40M", "HT", "1T", "126", "34",
++	"ETSI", "5G", "40M", "HT", "1T", "126", "32",
++	"MKK", "5G", "40M", "HT", "1T", "126", "32",
++	"FCC", "5G", "40M", "HT", "1T", "134", "32",
++	"ETSI", "5G", "40M", "HT", "1T", "134", "32",
++	"MKK", "5G", "40M", "HT", "1T", "134", "32",
++	"FCC", "5G", "40M", "HT", "1T", "151", "34",
++	"ETSI", "5G", "40M", "HT", "1T", "151", "32",
++	"MKK", "5G", "40M", "HT", "1T", "151", "63",
++	"FCC", "5G", "40M", "HT", "1T", "159", "34",
++	"ETSI", "5G", "40M", "HT", "1T", "159", "32",
++	"MKK", "5G", "40M", "HT", "1T", "159", "63",
++	"FCC", "5G", "40M", "HT", "2T", "38", "28",
++	"ETSI", "5G", "40M", "HT", "2T", "38", "30",
++	"MKK", "5G", "40M", "HT", "2T", "38", "30",
++	"FCC", "5G", "40M", "HT", "2T", "46", "28",
++	"ETSI", "5G", "40M", "HT", "2T", "46", "30",
++	"MKK", "5G", "40M", "HT", "2T", "46", "30",
++	"FCC", "5G", "40M", "HT", "2T", "54", "30",
++	"ETSI", "5G", "40M", "HT", "2T", "54", "30",
++	"MKK", "5G", "40M", "HT", "2T", "54", "30",
++	"FCC", "5G", "40M", "HT", "2T", "62", "30",
++	"ETSI", "5G", "40M", "HT", "2T", "62", "30",
++	"MKK", "5G", "40M", "HT", "2T", "62", "30",
++	"FCC", "5G", "40M", "HT", "2T", "102", "26",
++	"ETSI", "5G", "40M", "HT", "2T", "102", "30",
++	"MKK", "5G", "40M", "HT", "2T", "102", "30",
++	"FCC", "5G", "40M", "HT", "2T", "110", "30",
++	"ETSI", "5G", "40M", "HT", "2T", "110", "30",
++	"MKK", "5G", "40M", "HT", "2T", "110", "30",
++	"FCC", "5G", "40M", "HT", "2T", "118", "34",
++	"ETSI", "5G", "40M", "HT", "2T", "118", "30",
++	"MKK", "5G", "40M", "HT", "2T", "118", "30",
++	"FCC", "5G", "40M", "HT", "2T", "126", "32",
++	"ETSI", "5G", "40M", "HT", "2T", "126", "30",
++	"MKK", "5G", "40M", "HT", "2T", "126", "30",
++	"FCC", "5G", "40M", "HT", "2T", "134", "30",
++	"ETSI", "5G", "40M", "HT", "2T", "134", "30",
++	"MKK", "5G", "40M", "HT", "2T", "134", "30",
++	"FCC", "5G", "40M", "HT", "2T", "151", "34",
++	"ETSI", "5G", "40M", "HT", "2T", "151", "30",
++	"MKK", "5G", "40M", "HT", "2T", "151", "63",
++	"FCC", "5G", "40M", "HT", "2T", "159", "34",
++	"ETSI", "5G", "40M", "HT", "2T", "159", "30",
++	"MKK", "5G", "40M", "HT", "2T", "159", "63",
++	"FCC", "5G", "80M", "VHT", "1T", "42", "30",
++	"ETSI", "5G", "80M", "VHT", "1T", "42", "32",
++	"MKK", "5G", "80M", "VHT", "1T", "42", "32",
++	"FCC", "5G", "80M", "VHT", "1T", "58", "28",
++	"ETSI", "5G", "80M", "VHT", "1T", "58", "32",
++	"MKK", "5G", "80M", "VHT", "1T", "58", "32",
++	"FCC", "5G", "80M", "VHT", "1T", "106", "30",
++	"ETSI", "5G", "80M", "VHT", "1T", "106", "32",
++	"MKK", "5G", "80M", "VHT", "1T", "106", "32",
++	"FCC", "5G", "80M", "VHT", "1T", "122", "34",
++	"ETSI", "5G", "80M", "VHT", "1T", "122", "32",
++	"MKK", "5G", "80M", "VHT", "1T", "122", "32",
++	"FCC", "5G", "80M", "VHT", "1T", "155", "34",
++	"ETSI", "5G", "80M", "VHT", "1T", "155", "32",
++	"MKK", "5G", "80M", "VHT", "1T", "155", "63",
++	"FCC", "5G", "80M", "VHT", "2T", "42", "28",
++	"ETSI", "5G", "80M", "VHT", "2T", "42", "30",
++	"MKK", "5G", "80M", "VHT", "2T", "42", "30",
++	"FCC", "5G", "80M", "VHT", "2T", "58", "26",
++	"ETSI", "5G", "80M", "VHT", "2T", "58", "30",
++	"MKK", "5G", "80M", "VHT", "2T", "58", "30",
++	"FCC", "5G", "80M", "VHT", "2T", "106", "28",
++	"ETSI", "5G", "80M", "VHT", "2T", "106", "30",
++	"MKK", "5G", "80M", "VHT", "2T", "106", "30",
++	"FCC", "5G", "80M", "VHT", "2T", "122", "32",
++	"ETSI", "5G", "80M", "VHT", "2T", "122", "30",
++	"MKK", "5G", "80M", "VHT", "2T", "122", "30",
++	"FCC", "5G", "80M", "VHT", "2T", "155", "34",
++	"ETSI", "5G", "80M", "VHT", "2T", "155", "30",
++	"MKK", "5G", "80M", "VHT", "2T", "155", "63"
++};
++
++void
++odm_read_and_config_mp_8723d_txpwr_lmt(struct dm_struct *dm)
++{
++	u32	i = 0;
++#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
++	u32	array_len = sizeof(array_mp_8723d_txpwr_lmt) / sizeof(u8);
++	u8	*array = (u8 *)array_mp_8723d_txpwr_lmt;
++#else
++	u32	array_len = sizeof(array_mp_8723d_txpwr_lmt) / sizeof(u8 *);
++	u8	**array = (u8 **)array_mp_8723d_txpwr_lmt;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void	*adapter = dm->adapter;
++	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++
++	PlatformZeroMemory(hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
++	hal_data->nLinesReadPwrLmt = array_len / 7;
++#endif
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
++
++	for (i = 0; i < array_len; i += 7) {
++#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
++		u8	regulation = array[i];
++		u8	band = array[i + 1];
++		u8	bandwidth = array[i + 2];
++		u8	rate = array[i + 3];
++		u8	rf_path = array[i + 4];
++		u8	chnl = array[i + 5];
++		u8	val = array[i + 6];
++#else
++		u8	*regulation = array[i];
++		u8	*band = array[i + 1];
++		u8	*bandwidth = array[i + 2];
++		u8	*rate = array[i + 3];
++		u8	*rf_path = array[i + 4];
++		u8	*chnl = array[i + 5];
++		u8	*val = array[i + 6];
++#endif
++
++		odm_config_bb_txpwr_lmt_8723d(dm, regulation, band, bandwidth, rate, rf_path, chnl, val);
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++		rsprintf((char *)hal_data->BufOfLinesPwrLmt[i / 7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",",
++		regulation, band, bandwidth, rate, rf_path, chnl, val);
++#endif
++	}
++}
++
++/******************************************************************************
++*                           txxtaltrack.TXT
++******************************************************************************/
++
++s8 g_delta_swing_table_xtal_mp_n_txxtaltrack_8723d[]    = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
++s8 g_delta_swing_table_xtal_mp_p_txxtaltrack_8723d[]    = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -10, -12, -14, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16};
++
++void
++odm_read_and_config_mp_8723d_txxtaltrack(struct dm_struct *dm)
++{
++	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
++
++	PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8723d\n");
++
++
++	odm_move_memory(dm, cali_info->delta_swing_table_xtal_p, g_delta_swing_table_xtal_mp_p_txxtaltrack_8723d, DELTA_SWINGIDX_SIZE);
++	odm_move_memory(dm, cali_info->delta_swing_table_xtal_n, g_delta_swing_table_xtal_mp_n_txxtaltrack_8723d, DELTA_SWINGIDX_SIZE);
++}
++
++#endif /* end of HWIMG_SUPPORT*/
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_rf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_rf.h
+new file mode 100644
+index 000000000..956f146f2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/halhwimg8723d_rf.h
+@@ -0,0 +1,78 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/*Image2HeaderVersion: 3.5.2*/
++#if (RTL8723D_SUPPORT == 1)
++#ifndef __INC_MP_RF_HW_IMG_8723D_H
++#define __INC_MP_RF_HW_IMG_8723D_H
++
++
++/******************************************************************************
++*                           radioa.TXT
++******************************************************************************/
++
++void
++odm_read_and_config_mp_8723d_radioa( /* tc: Test Chip, mp: mp Chip*/
++				    struct dm_struct *dm);
++u32 odm_get_version_mp_8723d_radioa(void);
++
++/******************************************************************************
++*                           txpowertrack_pcie.TXT
++******************************************************************************/
++
++void
++odm_read_and_config_mp_8723d_txpowertrack_pcie( /* tc: Test Chip, mp: mp Chip*/
++					       struct dm_struct *dm);
++u32	odm_get_version_mp_8723d_txpowertrack_pcie(void);
++
++/******************************************************************************
++*                           txpowertrack_sdio.TXT
++******************************************************************************/
++
++void
++odm_read_and_config_mp_8723d_txpowertrack_sdio( /* tc: Test Chip, mp: mp Chip*/
++					       struct dm_struct *dm);
++u32	odm_get_version_mp_8723d_txpowertrack_sdio(void);
++
++/******************************************************************************
++*                           txpowertrack_usb.TXT
++******************************************************************************/
++
++void
++odm_read_and_config_mp_8723d_txpowertrack_usb( /* tc: Test Chip, mp: mp Chip*/
++					      struct dm_struct *dm);
++u32	odm_get_version_mp_8723d_txpowertrack_usb(void);
++
++/******************************************************************************
++*                           txpwr_lmt.TXT
++******************************************************************************/
++
++void
++odm_read_and_config_mp_8723d_txpwr_lmt( /* tc: Test Chip, mp: mp Chip*/
++				       struct dm_struct *dm);
++u32	odm_get_version_mp_8723d_txpwr_lmt(void);
++
++/******************************************************************************
++*                           txxtaltrack.TXT
++******************************************************************************/
++
++void
++odm_read_and_config_mp_8723d_txxtaltrack( /* tc: Test Chip, mp: mp Chip*/
++					 struct dm_struct *dm);
++u32	odm_get_version_mp_8723d_txxtaltrack(void);
++
++#endif
++#endif /* end of HWIMG_SUPPORT*/
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/phydm_regconfig8723d.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/phydm_regconfig8723d.c
+new file mode 100644
+index 000000000..4f11f8a35
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/phydm_regconfig8723d.c
+@@ -0,0 +1,145 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include "mp_precomp.h"
++#include "../phydm_precomp.h"
++
++#if (RTL8723D_SUPPORT == 1)
++
++void odm_config_rf_reg_8723d(struct dm_struct *dm, u32 addr, u32 data,
++			     enum rf_path RF_PATH, u32 reg_addr)
++{
++	if (addr == 0xfe || addr == 0xffe) {
++#ifdef CONFIG_LONG_DELAY_ISSUE
++		ODM_sleep_ms(50);
++#else
++		ODM_delay_ms(50);
++#endif
++	} else {
++		odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
++		/* Add 1us delay between BB/RF register setting. */
++		ODM_delay_us(1);
++	}
++}
++
++void odm_config_rf_radio_a_8723d(struct dm_struct *dm, u32 addr, u32 data)
++{
++	u32 content = 0x1000; /* RF_Content: radioa_txt */
++	u32 maskfor_phy_set = (u32)(content & 0xE000);
++
++	odm_config_rf_reg_8723d(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
++
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n",
++		  addr, data);
++}
++
++void odm_config_rf_radio_b_8723d(struct dm_struct *dm, u32 addr, u32 data)
++{
++	u32 content = 0x1001; /* RF_Content: radiob_txt */
++	u32 maskfor_phy_set = (u32)(content & 0xE000);
++
++	odm_config_rf_reg_8723d(dm, addr, data, RF_PATH_B, addr | maskfor_phy_set);
++
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n",
++		  addr, data);
++}
++
++void odm_config_mac_8723d(struct dm_struct *dm, u32 addr, u8 data)
++{
++	odm_write_1byte(dm, addr, data);
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n",
++		  addr, data);
++}
++
++void odm_config_bb_agc_8723d(struct dm_struct *dm, u32 addr, u32 bitmask,
++			     u32 data)
++{
++	odm_set_bb_reg(dm, addr, bitmask, data);
++	/* Add 1us delay between BB/RF register setting. */
++	ODM_delay_us(1);
++
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n",
++		  addr, data);
++}
++
++void odm_config_bb_phy_reg_pg_8723d(struct dm_struct *dm, u32 band, u32 rf_path,
++				    u32 tx_num, u32 addr, u32 bitmask, u32 data)
++{
++	if (addr == 0xfe || addr == 0xffe)
++#ifdef CONFIG_LONG_DELAY_ISSUE
++		ODM_sleep_ms(50);
++#else
++		ODM_delay_ms(50);
++#endif
++#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	else
++		phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	else
++		PHY_StoreTxPowerByRate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
++#endif
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n",
++		  addr, bitmask, data);
++}
++
++void odm_config_bb_phy_8723d(struct dm_struct *dm, u32 addr, u32 bitmask,
++			     u32 data)
++{
++	/*dbg_print("odm_config_bb_phy_8723d(), addr = 0x%x, data = 0x%x\n", addr, data);*/
++	if (addr == 0xfe)
++#ifdef CONFIG_LONG_DELAY_ISSUE
++		ODM_sleep_ms(50);
++#else
++		ODM_delay_ms(50);
++#endif
++	else if (addr == 0xfd)
++		ODM_delay_ms(5);
++	else if (addr == 0xfc)
++		ODM_delay_ms(1);
++	else if (addr == 0xfb)
++		ODM_delay_us(50);
++	else if (addr == 0xfa)
++		ODM_delay_us(5);
++	else if (addr == 0xf9)
++		ODM_delay_us(1);
++	else
++		odm_set_bb_reg(dm, addr, bitmask, data);
++
++	/* Add 1us delay between BB/RF register setting. */
++	ODM_delay_us(1);
++	PHYDM_DBG(dm, ODM_COMP_INIT,
++		  "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n",
++		  addr, data);
++}
++
++void odm_config_bb_txpwr_lmt_8723d(struct dm_struct *dm, u8 *regulation,
++				   u8 *band, u8 *bandwidth, u8 *rate_section,
++				   u8 *rf_path, u8 *channel, u8 *power_limit)
++{
++#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
++	phy_set_tx_power_limit(dm, regulation, band,
++			       bandwidth, rate_section, rf_path, channel, power_limit);
++#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++	PHY_SetTxPowerLimit(dm, regulation, band,
++			    bandwidth, rate_section, rf_path, channel, power_limit);
++#endif
++}
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/phydm_regconfig8723d.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/phydm_regconfig8723d.h
+new file mode 100644
+index 000000000..f4237c9d4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/phydm_regconfig8723d.h
+@@ -0,0 +1,44 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_ODM_REGCONFIG_H_8723D
++#define __INC_ODM_REGCONFIG_H_8723D
++
++#if (RTL8723D_SUPPORT == 1)
++
++void odm_config_rf_reg_8723d(struct dm_struct *dm, u32 addr, u32 data,
++			     enum rf_path RF_PATH, u32 reg_addr);
++
++void odm_config_rf_radio_a_8723d(struct dm_struct *dm, u32 addr, u32 data);
++
++void odm_config_rf_radio_b_8723d(struct dm_struct *dm, u32 addr, u32 data);
++
++void odm_config_mac_8723d(struct dm_struct *dm, u32 addr, u8 data);
++
++void odm_config_bb_agc_8723d(struct dm_struct *dm, u32 addr, u32 bitmask,
++			     u32 data);
++
++void odm_config_bb_phy_reg_pg_8723d(struct dm_struct *dm, u32 band, u32 rf_path,
++				    u32 tx_num, u32 addr, u32 bitmask,
++				    u32 data);
++
++void odm_config_bb_phy_8723d(struct dm_struct *dm, u32 addr, u32 bitmask,
++			     u32 data);
++
++void odm_config_bb_txpwr_lmt_8723d(struct dm_struct *dm, u8 *regulation,
++				   u8 *band, u8 *bandwidth, u8 *rate_section,
++				   u8 *rf_path, u8 *channel, u8 *power_limit);
++
++#endif
++#endif /* end of SUPPORT */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/phydm_rtl8723d.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/phydm_rtl8723d.c
+new file mode 100644
+index 000000000..fb9a4023d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/phydm_rtl8723d.c
+@@ -0,0 +1,50 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/* ============================================================
++ *  include files
++ * ============================================================
++ */
++
++#include "mp_precomp.h"
++#include "../phydm_precomp.h"
++
++#if (RTL8723D_SUPPORT == 1)
++
++s8 phydm_cckrssi_8723d(struct dm_struct *dm, u8 lna_idx, u8 vga_idx)
++{
++	s8 rx_pwr_all = 0x00;
++
++	switch (lna_idx) {
++	case 0xf:
++		rx_pwr_all = -46 - (2 * vga_idx);
++		break;
++	case 0xa:
++		rx_pwr_all = -20 - (2 * vga_idx);
++		break;
++	case 7:
++		rx_pwr_all = -10 - (2 * vga_idx);
++		break;
++	case 4:
++		rx_pwr_all = 4 - (2 * vga_idx);
++		break;
++	default:
++		break;
++	}
++
++	return rx_pwr_all;
++}
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/phydm_rtl8723d.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/phydm_rtl8723d.h
+new file mode 100644
+index 000000000..b59317569
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/phydm_rtl8723d.h
+@@ -0,0 +1,24 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __ODM_RTL8723D_H__
++#define __ODM_RTL8723D_H__
++
++#if (RTL8723D_SUPPORT == 1)
++
++s8 phydm_cckrssi_8723d(struct dm_struct *dm, u8 lna_idx, u8 vga_idx);
++
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/version_rtl8723d.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/version_rtl8723d.h
+new file mode 100644
+index 000000000..8b1bf7952
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/rtl8723d/version_rtl8723d.h
+@@ -0,0 +1,4 @@
++/*RTL8723D PHY Parameters*/
++#define	RELEASE_DATE_8723D		20190506
++#define	COMMIT_BY_8723D			"BB_Jessica"
++#define	RELEASE_VERSION_8723D	40
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/sd4_phydm_2_kernel.mk b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/sd4_phydm_2_kernel.mk
+new file mode 100644
+index 000000000..f11c6ac90
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/sd4_phydm_2_kernel.mk
+@@ -0,0 +1,188 @@
++EXTRA_CFLAGS += -I$(src)/hal/phydm
++
++_PHYDM_FILES := hal/phydm/phydm_debug.o	\
++								hal/phydm/phydm_interface.o\
++								hal/phydm/phydm_phystatus.o\
++								hal/phydm/phydm_hwconfig.o\
++								hal/phydm/phydm.o\
++								hal/phydm/phydm_dig.o\
++								hal/phydm/phydm_rainfo.o\
++								hal/phydm/phydm_adaptivity.o\
++								hal/phydm/phydm_cfotracking.o\
++								hal/phydm/phydm_noisemonitor.o\
++								hal/phydm/phydm_beamforming.o\
++								hal/phydm/phydm_dfs.o\
++								hal/phydm/txbf/halcomtxbf.o\
++								hal/phydm/txbf/haltxbfinterface.o\
++								hal/phydm/txbf/phydm_hal_txbf_api.o\
++								hal/phydm/phydm_ccx.o\
++								hal/phydm/phydm_cck_pd.o\
++								hal/phydm/phydm_rssi_monitor.o\
++								hal/phydm/phydm_math_lib.o\
++								hal/phydm/phydm_api.o\
++								hal/phydm/halrf/halrf.o\
++								hal/phydm/halrf/halrf_debug.o\
++								hal/phydm/halrf/halphyrf_ce.o\
++								hal/phydm/halrf/halrf_powertracking_ce.o\
++								hal/phydm/halrf/halrf_powertracking.o\
++								hal/phydm/halrf/halrf_kfree.o
++
++ifeq ($(CONFIG_RTL8188E), y)
++RTL871X = rtl8188e
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\
++								hal/phydm/$(RTL871X)/hal8188erateadaptive.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8188e.o
++endif
++
++ifeq ($(CONFIG_RTL8192E), y)
++RTL871X = rtl8192e
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8192e.o
++endif
++
++
++ifeq ($(CONFIG_RTL8812A), y)
++RTL871X = rtl8812a
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8812a.o\
++								hal/phydm/txbf/haltxbfjaguar.o
++endif
++
++ifeq ($(CONFIG_RTL8821A), y)
++RTL871X = rtl8821a
++_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\
++								hal/phydm/rtl8821a/halhwimg8821a_bb.o\
++								hal/phydm/rtl8821a/halhwimg8821a_rf.o\
++								hal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\
++								hal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\
++								hal/phydm/rtl8821a/phydm_regconfig8821a.o\
++								hal/phydm/rtl8821a/phydm_rtl8821a.o\
++								hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\
++								hal/phydm/txbf/haltxbfjaguar.o
++endif
++
++
++ifeq ($(CONFIG_RTL8723B), y)
++RTL871X = rtl8723b
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\
++								hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8723b.o
++endif
++
++
++ifeq ($(CONFIG_RTL8814A), y)
++RTL871X = rtl8814a
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8814a_rf.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8814a.o\
++								hal/phydm/txbf/haltxbf8814a.o
++endif
++
++
++ifeq ($(CONFIG_RTL8723C), y)
++RTL871X = rtl8703b
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8703b.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8703b.o
++endif
++
++ifeq ($(CONFIG_RTL8723D), y)
++RTL871X = rtl8723d
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8723d.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8723d.o
++endif
++
++
++ifeq ($(CONFIG_RTL8710B), y)
++RTL871X = rtl8710b
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8710b_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8710b_rf.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8710b.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8710b.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8710b.o
++endif
++
++
++ifeq ($(CONFIG_RTL8188F), y)
++RTL871X = rtl8188f
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8188f.o \
++								hal/phydm/$(RTL871X)/phydm_rtl8188f.o
++endif
++
++ifeq ($(CONFIG_RTL8822B), y)
++RTL871X = rtl8822b
++_PHYDM_FILES +=	hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \
++								hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \
++								hal/phydm/$(RTL871X)/halhwimg8822b_rf.o \
++								hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \
++								hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \
++								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \
++								hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \
++								hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \
++								hal/phydm/$(RTL871X)/phydm_rtl8822b.o
++
++_PHYDM_FILES +=	hal/phydm/txbf/haltxbf8822b.o
++endif
++
++
++ifeq ($(CONFIG_RTL8821C), y)
++RTL871X = rtl8821c
++_PHYDM_FILES +=	hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \
++								hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \
++								hal/phydm/$(RTL871X)/halhwimg8821c_rf.o \
++								hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \
++								hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o
++endif
++ifeq ($(CONFIG_RTL8192F), y)
++RTL871X = rtl8192f
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8192f_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8192f_rf.o\
++								hal/phydm/$(RTL871X)/phydm_hal_api8192f.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8192f.o\
++								hal/phydm/$(RTL871X)/phydm_rtl8192f.o\
++								hal/phydm/halrf/$(RTL871X)/halrf_8192f.o
++endif
++
++ifeq ($(CONFIG_RTL8198F), y)
++RTL871X = rtl8198f
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\
++								hal/phydm/$(RTL871X)/halhwimg8198f_mac.o\
++								hal/phydm/$(RTL871X)/halhwimg8198f_rf.o\
++								hal/phydm/$(RTL871X)/phydm_hal_api8198f.o\
++								hal/phydm/$(RTL871X)/phydm_regconfig8198f.o
++endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/halcomtxbf.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/halcomtxbf.c
+new file mode 100644
+index 000000000..ae45a5b1a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/halcomtxbf.c
+@@ -0,0 +1,520 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*@************************************************************
++ * Description:
++ *
++ * This file is for TXBF mechanism
++ *
++ ************************************************************/
++#include "mp_precomp.h"
++#include "../phydm_precomp.h"
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++/*@Beamforming halcomtxbf API create by YuChen 2015/05*/
++
++void hal_com_txbf_beamform_init(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	boolean is_iqgen_setting_ok = false;
++
++	if (dm->support_ic_type & ODM_RTL8814A) {
++		is_iqgen_setting_ok = phydm_beamforming_set_iqgen_8814A(dm);
++		PHYDM_DBG(dm, DBG_TXBF, "[%s] is_iqgen_setting_ok = %d\n",
++			  __func__, is_iqgen_setting_ok);
++	}
++}
++
++/*Only used for MU BFer Entry when get GID management frame (self as MU STA)*/
++void hal_com_txbf_config_gtab(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->support_ic_type & ODM_RTL8822B)
++		hal_txbf_8822b_config_gtab(dm);
++}
++
++void phydm_beamform_set_sounding_enter(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
++
++	if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_enter_work_item))
++		odm_schedule_work_item(&p_txbf_info->txbf_enter_work_item);
++#else
++	hal_com_txbf_enter_work_item_callback(dm);
++#endif
++}
++
++void phydm_beamform_set_sounding_leave(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
++
++	if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_leave_work_item))
++		odm_schedule_work_item(&p_txbf_info->txbf_leave_work_item);
++#else
++	hal_com_txbf_leave_work_item_callback(dm);
++#endif
++}
++
++void phydm_beamform_set_sounding_rate(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
++
++	if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_rate_work_item))
++		odm_schedule_work_item(&p_txbf_info->txbf_rate_work_item);
++#else
++	hal_com_txbf_rate_work_item_callback(dm);
++#endif
++}
++
++void phydm_beamform_set_sounding_status(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
++
++	if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_status_work_item))
++		odm_schedule_work_item(&p_txbf_info->txbf_status_work_item);
++#else
++	hal_com_txbf_status_work_item_callback(dm);
++#endif
++}
++
++void phydm_beamform_set_sounding_fw_ndpa(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
++
++	if (*dm->is_fw_dw_rsvd_page_in_progress)
++		odm_set_timer(dm, &p_txbf_info->txbf_fw_ndpa_timer, 5);
++	else
++		odm_schedule_work_item(&p_txbf_info->txbf_fw_ndpa_work_item);
++#else
++	hal_com_txbf_fw_ndpa_work_item_callback(dm);
++#endif
++}
++
++void phydm_beamform_set_sounding_clk(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
++
++	if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_clk_work_item))
++		odm_schedule_work_item(&p_txbf_info->txbf_clk_work_item);
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	phydm_run_in_thread_cmd(dm, hal_com_txbf_clk_work_item_callback, dm);
++#else
++	hal_com_txbf_clk_work_item_callback(dm);
++#endif
++}
++
++void phydm_beamform_set_reset_tx_path(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
++	struct _RT_WORK_ITEM *pwi = &p_txbf_info->txbf_reset_tx_path_work_item;
++
++	if (!odm_is_work_item_scheduled(pwi))
++		odm_schedule_work_item(pwi);
++#else
++	hal_com_txbf_reset_tx_path_work_item_callback(dm);
++#endif
++}
++
++void phydm_beamform_set_get_tx_rate(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
++	struct _RT_WORK_ITEM *pwi = &p_txbf_info->txbf_get_tx_rate_work_item;
++
++	if (!odm_is_work_item_scheduled(pwi))
++		odm_schedule_work_item(pwi);
++#else
++	hal_com_txbf_get_tx_rate_work_item_callback(dm);
++#endif
++}
++
++void hal_com_txbf_enter_work_item_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter
++#else
++	void *dm_void
++#endif
++	)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++#else
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#endif
++	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
++	u8 idx = p_txbf_info->txbf_idx;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
++		hal_txbf_jaguar_enter(dm, idx);
++	else if (dm->support_ic_type & ODM_RTL8192E)
++		hal_txbf_8192e_enter(dm, idx);
++	else if (dm->support_ic_type & ODM_RTL8814A)
++		hal_txbf_8814a_enter(dm, idx);
++	else if (dm->support_ic_type & ODM_RTL8822B)
++		hal_txbf_8822b_enter(dm, idx);
++}
++
++void hal_com_txbf_leave_work_item_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter
++#else
++	void *dm_void
++#endif
++	)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++#else
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#endif
++	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
++
++	u8 idx = p_txbf_info->txbf_idx;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
++		hal_txbf_jaguar_leave(dm, idx);
++	else if (dm->support_ic_type & ODM_RTL8192E)
++		hal_txbf_8192e_leave(dm, idx);
++	else if (dm->support_ic_type & ODM_RTL8814A)
++		hal_txbf_8814a_leave(dm, idx);
++	else if (dm->support_ic_type & ODM_RTL8822B)
++		hal_txbf_8822b_leave(dm, idx);
++}
++
++void hal_com_txbf_fw_ndpa_work_item_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter
++#else
++	void *dm_void
++#endif
++	)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++#else
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#endif
++	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
++	u8 idx = p_txbf_info->ndpa_idx;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
++		hal_txbf_jaguar_fw_txbf(dm, idx);
++	else if (dm->support_ic_type & ODM_RTL8192E)
++		hal_txbf_8192e_fw_tx_bf(dm, idx);
++	else if (dm->support_ic_type & ODM_RTL8814A)
++		hal_txbf_8814a_fw_txbf(dm, idx);
++	else if (dm->support_ic_type & ODM_RTL8822B)
++		hal_txbf_8822b_fw_txbf(dm, idx);
++}
++
++void hal_com_txbf_clk_work_item_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter
++#else
++	void *dm_void
++#endif
++	)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++#else
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#endif
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	if (dm->support_ic_type & ODM_RTL8812)
++		hal_txbf_jaguar_clk_8812a(dm);
++}
++
++void hal_com_txbf_rate_work_item_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter
++#else
++	void *dm_void
++#endif
++	)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++#else
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#endif
++	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
++	u8 BW = p_txbf_info->BW;
++	u8 rate = p_txbf_info->rate;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	if (dm->support_ic_type & ODM_RTL8812)
++		hal_txbf_8812a_set_ndpa_rate(dm, BW, rate);
++	else if (dm->support_ic_type & ODM_RTL8192E)
++		hal_txbf_8192e_set_ndpa_rate(dm, BW, rate);
++	else if (dm->support_ic_type & ODM_RTL8814A)
++		hal_txbf_8814a_set_ndpa_rate(dm, BW, rate);
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void hal_com_txbf_fw_ndpa_timer_callback(
++	struct phydm_timer_list *timer)
++{
++	void *adapter = (void *)timer->Adapter;
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++
++	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	if (*dm->is_fw_dw_rsvd_page_in_progress)
++		odm_set_timer(dm, &(p_txbf_info->txbf_fw_ndpa_timer), 5);
++	else
++		odm_schedule_work_item(&(p_txbf_info->txbf_fw_ndpa_work_item));
++}
++#endif
++
++void hal_com_txbf_status_work_item_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter
++#else
++	void *dm_void
++#endif
++	)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++#else
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#endif
++	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
++
++	u8 idx = p_txbf_info->txbf_idx;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
++		hal_txbf_jaguar_status(dm, idx);
++	else if (dm->support_ic_type & ODM_RTL8192E)
++		hal_txbf_8192e_status(dm, idx);
++	else if (dm->support_ic_type & ODM_RTL8814A)
++		hal_txbf_8814a_status(dm, idx);
++	else if (dm->support_ic_type & ODM_RTL8822B)
++		hal_txbf_8822b_status(dm, idx);
++}
++
++void hal_com_txbf_reset_tx_path_work_item_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter
++#else
++	void *dm_void
++#endif
++	)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++#else
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#endif
++	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
++
++	u8 idx = p_txbf_info->txbf_idx;
++
++	if (dm->support_ic_type & ODM_RTL8814A)
++		hal_txbf_8814a_reset_tx_path(dm, idx);
++}
++
++void hal_com_txbf_get_tx_rate_work_item_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter
++#else
++	void *dm_void
++#endif
++	)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++#else
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#endif
++
++	if (dm->support_ic_type & ODM_RTL8814A)
++		hal_txbf_8814a_get_tx_rate(dm);
++}
++
++boolean
++hal_com_txbf_set(
++	void *dm_void,
++	u8 set_type,
++	void *p_in_buf)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 *p_u1_tmp = (u8 *)p_in_buf;
++	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] set_type = 0x%X\n", __func__, set_type);
++
++	switch (set_type) {
++	case TXBF_SET_SOUNDING_ENTER:
++		p_txbf_info->txbf_idx = *p_u1_tmp;
++		phydm_beamform_set_sounding_enter(dm);
++		break;
++
++	case TXBF_SET_SOUNDING_LEAVE:
++		p_txbf_info->txbf_idx = *p_u1_tmp;
++		phydm_beamform_set_sounding_leave(dm);
++		break;
++
++	case TXBF_SET_SOUNDING_RATE:
++		p_txbf_info->BW = p_u1_tmp[0];
++		p_txbf_info->rate = p_u1_tmp[1];
++		phydm_beamform_set_sounding_rate(dm);
++		break;
++
++	case TXBF_SET_SOUNDING_STATUS:
++		p_txbf_info->txbf_idx = *p_u1_tmp;
++		phydm_beamform_set_sounding_status(dm);
++		break;
++
++	case TXBF_SET_SOUNDING_FW_NDPA:
++		p_txbf_info->ndpa_idx = *p_u1_tmp;
++		phydm_beamform_set_sounding_fw_ndpa(dm);
++		break;
++
++	case TXBF_SET_SOUNDING_CLK:
++		phydm_beamform_set_sounding_clk(dm);
++		break;
++
++	case TXBF_SET_TX_PATH_RESET:
++		p_txbf_info->txbf_idx = *p_u1_tmp;
++		phydm_beamform_set_reset_tx_path(dm);
++		break;
++
++	case TXBF_SET_GET_TX_RATE:
++		phydm_beamform_set_get_tx_rate(dm);
++		break;
++	}
++
++	return true;
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++boolean
++hal_com_txbf_get(
++	void *adapter,
++	u8 get_type,
++	void *p_out_buf)
++{
++	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++	boolean *p_boolean = (boolean *)p_out_buf;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	if (get_type == TXBF_GET_EXPLICIT_BEAMFORMEE) {
++		if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter))
++			*p_boolean = false;
++		else if (/*@IS_HARDWARE_TYPE_8822B(adapter)	||*/
++			 IS_HARDWARE_TYPE_8821B(adapter) ||
++			 IS_HARDWARE_TYPE_8192E(adapter) ||
++			 IS_HARDWARE_TYPE_8192F(adapter) ||
++			 IS_HARDWARE_TYPE_JAGUAR(adapter) ||
++			 IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter) ||
++			 IS_HARDWARE_TYPE_JAGUAR3(adapter))
++			*p_boolean = true;
++		else
++			*p_boolean = false;
++	} else if (get_type == TXBF_GET_EXPLICIT_BEAMFORMER) {
++		if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter))
++			*p_boolean = false;
++		else if (/*@IS_HARDWARE_TYPE_8822B(adapter)	||*/
++			 IS_HARDWARE_TYPE_8821B(adapter) ||
++			 IS_HARDWARE_TYPE_8192E(adapter) ||
++			 IS_HARDWARE_TYPE_8192F(adapter) ||
++			 IS_HARDWARE_TYPE_JAGUAR(adapter) ||
++			 IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter) ||
++			 IS_HARDWARE_TYPE_JAGUAR3(adapter)) {
++			if (hal_data->RF_Type == RF_2T2R ||
++			    hal_data->RF_Type == RF_3T3R ||
++			    hal_data->RF_Type == RF_4T4R)
++				*p_boolean = true;
++			else
++				*p_boolean = false;
++		} else
++			*p_boolean = false;
++	} else if (get_type == TXBF_GET_MU_MIMO_STA) {
++#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) ||\
++	(RTL8822C_SUPPORT == 1))
++		if (IS_HARDWARE_TYPE_8822B(adapter) ||
++		    IS_HARDWARE_TYPE_8821C(adapter) ||
++		    IS_HARDWARE_TYPE_JAGUAR3(adapter))
++			*p_boolean = true;
++		else
++#endif
++			*p_boolean = false;
++
++	} else if (get_type == TXBF_GET_MU_MIMO_AP) {
++#if ((RTL8822B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
++		if (IS_HARDWARE_TYPE_8822B(adapter) ||
++		    IS_HARDWARE_TYPE_JAGUAR3(adapter))
++			*p_boolean = true;
++		else
++#endif
++			*p_boolean = false;
++	}
++
++	return true;
++}
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/halcomtxbf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/halcomtxbf.h
+new file mode 100644
+index 000000000..5ad303394
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/halcomtxbf.h
+@@ -0,0 +1,183 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++#ifndef __HAL_COM_TXBF_H__
++#define __HAL_COM_TXBF_H__
++
++#if 0
++typedef	bool
++(*TXBF_GET)(
++	void*			adapter,
++	u8			get_type,
++	void*			p_out_buf
++	);
++
++typedef	bool
++(*TXBF_SET)(
++	void*			adapter,
++	u8			set_type,
++	void*			p_in_buf
++	);
++#endif
++
++enum txbf_set_type {
++	TXBF_SET_SOUNDING_ENTER,
++	TXBF_SET_SOUNDING_LEAVE,
++	TXBF_SET_SOUNDING_RATE,
++	TXBF_SET_SOUNDING_STATUS,
++	TXBF_SET_SOUNDING_FW_NDPA,
++	TXBF_SET_SOUNDING_CLK,
++	TXBF_SET_TX_PATH_RESET,
++	TXBF_SET_GET_TX_RATE
++};
++
++enum txbf_get_type {
++	TXBF_GET_EXPLICIT_BEAMFORMEE,
++	TXBF_GET_EXPLICIT_BEAMFORMER,
++	TXBF_GET_MU_MIMO_STA,
++	TXBF_GET_MU_MIMO_AP
++};
++
++/* @2 HAL TXBF related */
++struct _HAL_TXBF_INFO {
++	u8 txbf_idx;
++	u8 ndpa_idx;
++	u8 BW;
++	u8 rate;
++
++	struct phydm_timer_list txbf_fw_ndpa_timer;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	RT_WORK_ITEM txbf_enter_work_item;
++	RT_WORK_ITEM txbf_leave_work_item;
++	RT_WORK_ITEM txbf_fw_ndpa_work_item;
++	RT_WORK_ITEM txbf_clk_work_item;
++	RT_WORK_ITEM txbf_status_work_item;
++	RT_WORK_ITEM txbf_rate_work_item;
++	RT_WORK_ITEM txbf_reset_tx_path_work_item;
++	RT_WORK_ITEM txbf_get_tx_rate_work_item;
++#endif
++};
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++
++void hal_com_txbf_beamform_init(
++	void *dm_void);
++
++void hal_com_txbf_config_gtab(
++	void *dm_void);
++
++void hal_com_txbf_enter_work_item_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter
++#else
++	void *dm_void
++#endif
++	);
++
++void hal_com_txbf_leave_work_item_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter
++#else
++	void *dm_void
++#endif
++	);
++
++void hal_com_txbf_fw_ndpa_work_item_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter
++#else
++	void *dm_void
++#endif
++	);
++
++void hal_com_txbf_clk_work_item_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter
++#else
++	void *dm_void
++#endif
++	);
++
++void hal_com_txbf_reset_tx_path_work_item_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter
++#else
++	void *dm_void
++#endif
++	);
++
++void hal_com_txbf_get_tx_rate_work_item_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter
++#else
++	void *dm_void
++#endif
++	);
++
++void hal_com_txbf_rate_work_item_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter
++#else
++	void *dm_void
++#endif
++	);
++
++void hal_com_txbf_fw_ndpa_timer_callback(
++	struct phydm_timer_list *timer);
++
++void hal_com_txbf_status_work_item_callback(
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	void *adapter
++#else
++	void *dm_void
++#endif
++	);
++
++boolean
++hal_com_txbf_set(
++	void *dm_void,
++	u8 set_type,
++	void *p_in_buf);
++
++boolean
++hal_com_txbf_get(
++	void *adapter,
++	u8 get_type,
++	void *p_out_buf);
++
++#else
++#define hal_com_txbf_beamform_init(dm_void) NULL
++#define hal_com_txbf_config_gtab(dm_void) NULL
++#define hal_com_txbf_enter_work_item_callback(_adapter) NULL
++#define hal_com_txbf_leave_work_item_callback(_adapter) NULL
++#define hal_com_txbf_fw_ndpa_work_item_callback(_adapter) NULL
++#define hal_com_txbf_clk_work_item_callback(_adapter) NULL
++#define hal_com_txbf_rate_work_item_callback(_adapter) NULL
++#define hal_com_txbf_fw_ndpa_timer_callback(_adapter) NULL
++#define hal_com_txbf_status_work_item_callback(_adapter) NULL
++#define hal_com_txbf_get(_adapter, _get_type, _pout_buf)
++
++#endif
++
++#endif /*  @#ifndef __HAL_COM_TXBF_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8192e.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8192e.c
+new file mode 100644
+index 000000000..daac3e58a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8192e.c
+@@ -0,0 +1,384 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*************************************************************
++ * Description:
++ *
++ * This file is for 8192E TXBF mechanism
++ *
++ ************************************************************/
++#include "mp_precomp.h"
++#include "../phydm_precomp.h"
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++#if (RTL8192E_SUPPORT == 1)
++
++void hal_txbf_8192e_set_ndpa_rate(
++	void *dm_void,
++	u8 BW,
++	u8 rate)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8192E, (rate << 2 | BW));
++}
++
++void hal_txbf_8192e_rf_mode(
++	void *dm_void,
++	struct _RT_BEAMFORMING_INFO *beam_info)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	if (dm->rf_type == RF_1T1R)
++		return;
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
++	odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
++
++	if (beam_info->beamformee_su_cnt > 0) {
++		/*Path_A*/
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode  0x30=0x18000*/
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/
++		/*Path_B*/
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/
++	} else {
++		/*Path_A*/
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/
++		/*Path_B*/
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/
++	}
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
++	odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
++
++	if (beam_info->beamformee_su_cnt > 0) {
++		odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333);
++		odm_set_bb_reg(dm, R_0xa04, MASKBYTE3, 0xc1);
++	} else
++		odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121313);
++}
++
++void hal_txbf_8192e_fw_txbf_cmd(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 idx, period0 = 0, period1 = 0;
++	u8 PageNum0 = 0xFF, PageNum1 = 0xFF;
++	u8 u1_tx_bf_parm[3] = {0};
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++
++	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
++		if (beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
++			if (idx == 0) {
++				if (beam_info->beamformee_entry[idx].is_sound)
++					PageNum0 = 0xFE;
++				else
++					PageNum0 = 0xFF; /* stop sounding */
++				period0 = (u8)(beam_info->beamformee_entry[idx].sound_period);
++			} else if (idx == 1) {
++				if (beam_info->beamformee_entry[idx].is_sound)
++					PageNum1 = 0xFE;
++				else
++					PageNum1 = 0xFF; /* stop sounding */
++				period1 = (u8)(beam_info->beamformee_entry[idx].sound_period);
++			}
++		}
++	}
++
++	u1_tx_bf_parm[0] = PageNum0;
++	u1_tx_bf_parm[1] = PageNum1;
++	u1_tx_bf_parm[2] = (period1 << 4) | period0;
++	odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
++
++	PHYDM_DBG(dm, DBG_TXBF,
++		  "[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n",
++		  __func__, PageNum0, period0, PageNum1, period1);
++}
++
++void hal_txbf_8192e_download_ndpa(
++	void *dm_void,
++	u8 idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 u1b_tmp = 0, tmp_reg422 = 0, head_page;
++	u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
++	boolean is_send_beacon = false;
++	u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812;
++	/*@default reseved 1 page for the IC type which is undefined.*/
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	*dm->is_fw_dw_rsvd_page_in_progress = true;
++#endif
++	if (idx == 0)
++		head_page = 0xFE;
++	else
++		head_page = 0xFE;
++
++	phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy);
++
++	/*Set REG_CR bit 8. DMA beacon by SW.*/
++	u1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1);
++	odm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp | BIT(0)));
++
++	/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
++	tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2);
++	odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422 & (~BIT(6)));
++
++	if (tmp_reg422 & BIT(6)) {
++		PHYDM_DBG(dm, DBG_TXBF,
++			  "%s There is an adapter is sending beacon.\n",
++			  __func__);
++		is_send_beacon = true;
++	}
++
++	/*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD	NDPA Head for TXDMA*/
++	odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, head_page);
++
++	do {
++		/*@Clear beacon valid check bit.*/
++		bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
++		odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 2, (bcn_valid_reg | BIT(0)));
++
++		/* @download NDPA rsvd page. */
++		beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
++
++#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
++		if (dm->support_interface == ODM_ITRF_PCIE) {
++			u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3);
++			count = 0;
++			while ((count < 20) && (u1b_tmp & BIT(4))) {
++				count++;
++				ODM_delay_us(10);
++				u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3);
++			}
++			odm_write_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3, u1b_tmp | BIT(4));
++		}
++#endif
++
++		/*@check rsvd page download OK.*/
++		bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
++		count = 0;
++		while (!(bcn_valid_reg & BIT(0)) && count < 20) {
++			count++;
++			ODM_delay_us(10);
++			bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
++		}
++		dl_bcn_count++;
++	} while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5);
++
++	if (!(bcn_valid_reg & BIT(0)))
++		PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n",
++			  __func__);
++
++	/*TDECTRL[15:8] 0x209[7:0] = 0xF9	Beacon Head for TXDMA*/
++	odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, tx_page_bndy);
++
++	/*To make sure that if there exists an adapter which would like to send beacon.*/
++	/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
++	/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
++	/*the beacon cannot be sent by HW.*/
++	/*@2010.06.23. Added by tynli.*/
++	if (is_send_beacon)
++		odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422);
++
++	/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
++	/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
++	u1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1);
++	odm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp & (~BIT(0))));
++
++	p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	*dm->is_fw_dw_rsvd_page_in_progress = false;
++#endif
++}
++
++void hal_txbf_8192e_enter(
++	void *dm_void,
++	u8 bfer_bfee_idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i = 0;
++	u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
++	u8 bfee_idx = (bfer_bfee_idx & 0xF);
++	u32 csi_param;
++	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
++	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
++	u16 sta_id = 0;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	hal_txbf_8192e_rf_mode(dm, beamforming_info);
++
++	if (dm->rf_type == RF_2T2R)
++		odm_write_4byte(dm, 0xd80, 0x00000000); /*nc =2*/
++
++	if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
++		beamformer_entry = beamforming_info->beamformer_entry[bfer_idx];
++
++		/*Sounding protocol control*/
++		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xCB);
++
++		/*@MAC address/Partial AID of Beamformer*/
++		if (bfer_idx == 0) {
++			for (i = 0; i < 6; i++)
++				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8192E + i), beamformer_entry.mac_addr[i]);
++		} else {
++			for (i = 0; i < 6; i++)
++				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8192E + i), beamformer_entry.mac_addr[i]);
++		}
++
++		/*@CSI report parameters of Beamformer Default use nc = 2*/
++		csi_param = 0x03090309;
++
++		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8192E, csi_param);
++		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW40_8192E, csi_param);
++		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8192E, csi_param);
++
++		/*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us,  MP chip)*/
++		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E + 3, 0x50);
++	}
++
++	if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
++		beamformee_entry = beamforming_info->beamformee_entry[bfee_idx];
++
++		if (phydm_acting_determine(dm, phydm_acting_as_ibss))
++			sta_id = beamformee_entry.mac_id;
++		else
++			sta_id = beamformee_entry.p_aid;
++
++		PHYDM_DBG(dm, DBG_TXBF, "[%s], sta_id=0x%X\n", __func__,
++			  sta_id);
++
++		/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
++		if (bfee_idx == 0) {
++			odm_write_2byte(dm, REG_TXBF_CTRL_8192E, sta_id);
++			odm_write_1byte(dm, REG_TXBF_CTRL_8192E + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 3) | BIT(4) | BIT(6) | BIT(7));
++		} else
++			odm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, sta_id | BIT(12) | BIT(14) | BIT(15));
++
++		/*@CSI report parameters of Beamformee*/
++		if (bfee_idx == 0) {
++			/*@Get BIT24 & BIT25*/
++			u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3) & 0x3;
++
++			odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3, tmp | 0x60);
++			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, sta_id | BIT(9));
++		} else {
++			/*Set BIT25*/
++			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, sta_id | 0xE200);
++		}
++		phydm_beamforming_notify(dm);
++	}
++}
++
++void hal_txbf_8192e_leave(
++	void *dm_void,
++	u8 idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++
++	hal_txbf_8192e_rf_mode(dm, beam_info);
++
++	/*	@Clear P_AID of Beamformee
++	*	Clear MAC addresss of Beamformer
++	*	Clear Associated Bfmee Sel
++	*/
++	if (beam_info->beamform_cap == BEAMFORMING_CAP_NONE)
++		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xC8);
++
++	if (idx == 0) {
++		odm_write_2byte(dm, REG_TXBF_CTRL_8192E, 0);
++		odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0);
++		odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E + 4, 0);
++		odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0);
++	} else {
++		odm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 2) & 0xF000);
++		odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0);
++		odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E + 4, 0);
++		odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2) & 0x60);
++	}
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] idx %d\n", __func__, idx);
++}
++
++void hal_txbf_8192e_status(
++	void *dm_void,
++	u8 idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u16 beam_ctrl_val;
++	u32 beam_ctrl_reg;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx];
++
++	if (phydm_acting_determine(dm, phydm_acting_as_ibss))
++		beam_ctrl_val = beamform_entry.mac_id;
++	else
++		beam_ctrl_val = beamform_entry.p_aid;
++
++	if (idx == 0)
++		beam_ctrl_reg = REG_TXBF_CTRL_8192E;
++	else {
++		beam_ctrl_reg = REG_TXBF_CTRL_8192E + 2;
++		beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
++	}
++
++	if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beam_info->apply_v_matrix == true) {
++		if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
++			beam_ctrl_val |= BIT(9);
++		else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
++			beam_ctrl_val |= BIT(10);
++	} else
++		beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
++
++	odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
++
++	PHYDM_DBG(dm, DBG_TXBF,
++		  "[%s] idx %d beam_ctrl_reg %x beam_ctrl_val %x\n", __func__,
++		  idx, beam_ctrl_reg, beam_ctrl_val);
++}
++
++void hal_txbf_8192e_fw_tx_bf(
++	void *dm_void,
++	u8 idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
++		hal_txbf_8192e_download_ndpa(dm, idx);
++
++	hal_txbf_8192e_fw_txbf_cmd(dm);
++}
++
++#endif /* @#if (RTL8192E_SUPPORT == 1)*/
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8192e.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8192e.h
+new file mode 100644
+index 000000000..9b0c8321f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8192e.h
+@@ -0,0 +1,71 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++#ifndef __HAL_TXBF_8192E_H__
++#define __HAL_TXBF_8192E_H__
++
++#if (RTL8192E_SUPPORT == 1)
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++
++void hal_txbf_8192e_set_ndpa_rate(
++	void *dm_void,
++	u8 BW,
++	u8 rate);
++
++void hal_txbf_8192e_enter(
++	void *dm_void,
++	u8 idx);
++
++void hal_txbf_8192e_leave(
++	void *dm_void,
++	u8 idx);
++
++void hal_txbf_8192e_status(
++	void *dm_void,
++	u8 idx);
++
++void hal_txbf_8192e_fw_tx_bf(
++	void *dm_void,
++	u8 idx);
++#else
++
++#define hal_txbf_8192e_set_ndpa_rate(dm_void, BW, rate)
++#define hal_txbf_8192e_enter(dm_void, idx)
++#define hal_txbf_8192e_leave(dm_void, idx)
++#define hal_txbf_8192e_status(dm_void, idx)
++#define hal_txbf_8192e_fw_tx_bf(dm_void, idx)
++
++#endif
++
++#else
++
++#define hal_txbf_8192e_set_ndpa_rate(dm_void, BW, rate)
++#define hal_txbf_8192e_enter(dm_void, idx)
++#define hal_txbf_8192e_leave(dm_void, idx)
++#define hal_txbf_8192e_status(dm_void, idx)
++#define hal_txbf_8192e_fw_tx_bf(dm_void, idx)
++
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8814a.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8814a.c
+new file mode 100644
+index 000000000..7ad6ca909
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8814a.c
+@@ -0,0 +1,675 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/* ************************************************************
++ * Description:
++ *
++ * This file is for 8814A TXBF mechanism
++ *
++ * ************************************************************ */
++
++#include "mp_precomp.h"
++#include "../phydm_precomp.h"
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++#if (RTL8814A_SUPPORT == 1)
++
++boolean
++phydm_beamforming_set_iqgen_8814A(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i = 0;
++	u16 counter = 0;
++	u32 rf_mode[4];
++
++	for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
++		odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
++
++	while (1) {
++		counter++;
++		for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
++			odm_set_rf_reg(dm, i, RF_RCK_OS, 0xfffff, 0x18000); /*Select Rx mode*/
++
++		ODM_delay_us(2);
++
++		for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
++			rf_mode[i] = odm_get_rf_reg(dm, i, RF_RCK_OS, 0xfffff);
++
++		if (rf_mode[0] == 0x18000 && rf_mode[1] == 0x18000 && rf_mode[2] == 0x18000 && rf_mode[3] == 0x18000)
++			break;
++		else if (counter == 100) {
++			PHYDM_DBG(dm, DBG_TXBF, "iqgen setting fail:8814A\n");
++			return false;
++		}
++	}
++
++	for (i = RF_PATH_A; i < MAX_RF_PATH; i++) {
++		odm_set_rf_reg(dm, i, RF_TXPA_G1, 0xfffff, 0xBE77F); /*Set Table data*/
++		odm_set_rf_reg(dm, i, RF_TXPA_G2, 0xfffff, 0x226BF); /*@Enable TXIQGEN in Rx mode*/
++	}
++	odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in Rx mode*/
++
++	for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
++		odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
++
++	return true;
++}
++
++void hal_txbf_8814a_set_ndpa_rate(void *dm_void, u8 BW, u8 rate)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8814A, BW);
++	odm_write_1byte(dm, REG_NDPA_RATE_8814A, (u8)rate);
++}
++#if 0
++#define PHYDM_MEMORY_MAP_BUF_READ 0x8000
++#define PHYDM_CTRL_INFO_PAGE 0x660
++
++void
++phydm_data_rate_8814a(
++	struct dm_struct			*dm,
++	u8				mac_id,
++	u32				*data,
++	u8				data_len
++)
++{
++	u8	i = 0;
++	u16	x_read_data_addr = 0;
++
++	odm_write_2byte(dm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE);
++	x_read_data_addr = PHYDM_MEMORY_MAP_BUF_READ + mac_id * 32; /*@Ctrl Info: 32Bytes for each macid(n)*/
++
++	if (x_read_data_addr < PHYDM_MEMORY_MAP_BUF_READ || x_read_data_addr > 0x8FFF) {
++		PHYDM_DBG(dm, DBG_TXBF,
++			  "x_read_data_addr(0x%x) is not correct!\n",
++			  x_read_data_addr);
++		return;
++	}
++
++	/* Read data */
++	for (i = 0; i < data_len; i++)
++		*(data + i) = odm_read_2byte(dm, x_read_data_addr + i);
++}
++#endif
++
++void hal_txbf_8814a_get_tx_rate(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY *entry;
++	struct ra_table *ra_tab = &dm->dm_ra_table;
++	struct cmn_sta_info *sta = NULL;
++	u8 data_rate = 0xFF;
++	u8 macid = 0;
++
++	entry = &(beam_info->beamformee_entry[beam_info->beamformee_cur_idx]);
++	macid = (u8)entry->mac_id;
++
++	sta = dm->phydm_sta_info[macid];
++
++	if (is_sta_active(sta)) {
++		data_rate = (sta->ra_info.curr_tx_rate) & 0x7f; /*@Bit7 indicates SGI*/
++		beam_info->tx_bf_data_rate = data_rate;
++	}
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] dm->tx_bf_data_rate = 0x%x\n", __func__,
++		  beam_info->tx_bf_data_rate);
++}
++
++void hal_txbf_8814a_reset_tx_path(void *dm_void, u8 idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if DEV_BUS_TYPE == RT_USB_INTERFACE
++	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
++	u8 nr_index = 0, tx_ss = 0;
++
++	if (idx < BEAMFORMEE_ENTRY_NUM)
++		beamformee_entry = beamforming_info->beamformee_entry[idx];
++	else
++		return;
++
++	if (beamforming_info->last_usb_hub != (*dm->hub_usb_mode)) {
++		nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer);
++
++		if (*dm->hub_usb_mode == 2) {
++			if (dm->rf_type == RF_4T4R)
++				tx_ss = 0xf;
++			else if (dm->rf_type == RF_3T3R)
++				tx_ss = 0xe;
++			else
++				tx_ss = 0x6;
++		} else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/
++			tx_ss = 0x6;
++		else
++			tx_ss = 0x6;
++
++		if (tx_ss == 0xf) {
++			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f);
++			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0);
++		} else if (tx_ss == 0xe) {
++			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e);
++			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0);
++		} else if (tx_ss == 0x6) {
++			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936);
++			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360);
++		}
++
++		if (idx == 0) {
++			switch (nr_index) {
++			case 0:
++				break;
++
++			case 1: /*Nsts = 2	BC*/
++				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
++				break;
++
++			case 2: /*Nsts = 3	BCD*/
++				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
++				break;
++
++			default: /*nr>3, same as Case 3*/
++				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
++				break;
++			}
++		} else {
++			switch (nr_index) {
++			case 0:
++				break;
++
++			case 1: /*Nsts = 2	BC*/
++				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
++				break;
++
++			case 2: /*Nsts = 3	BCD*/
++				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
++				break;
++
++			default: /*nr>3, same as Case 3*/
++				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
++				break;
++			}
++		}
++
++		beamforming_info->last_usb_hub = *dm->hub_usb_mode;
++	} else
++		return;
++#endif
++}
++
++u8 hal_txbf_8814a_get_ntx(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 ntx = 0, tx_ss = 3;
++
++#if DEV_BUS_TYPE == RT_USB_INTERFACE
++	tx_ss = *dm->hub_usb_mode;
++#endif
++	if (tx_ss == 3 || tx_ss == 2) {
++		if (dm->rf_type == RF_4T4R)
++			ntx = 3;
++		else if (dm->rf_type == RF_3T3R)
++			ntx = 2;
++		else
++			ntx = 1;
++	} else if (tx_ss == 1) /*USB 2.0 always 2Tx*/
++		ntx = 1;
++	else
++		ntx = 1;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] ntx = %d\n", __func__, ntx);
++	return ntx;
++}
++
++u8 hal_txbf_8814a_get_nrx(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 nrx = 0;
++
++	if (dm->rf_type == RF_4T4R)
++		nrx = 3;
++	else if (dm->rf_type == RF_3T3R)
++		nrx = 2;
++	else if (dm->rf_type == RF_2T2R)
++		nrx = 1;
++	else if (dm->rf_type == RF_2T3R)
++		nrx = 2;
++	else if (dm->rf_type == RF_2T4R)
++		nrx = 3;
++	else if (dm->rf_type == RF_1T1R)
++		nrx = 0;
++	else if (dm->rf_type == RF_1T2R)
++		nrx = 1;
++	else
++		nrx = 0;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] nrx = %d\n", __func__, nrx);
++	return nrx;
++}
++
++void hal_txbf_8814a_rf_mode(void *dm_void,
++			    struct _RT_BEAMFORMING_INFO *beamforming_info,
++			    u8 idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 nr_index = 0;
++	u8 tx_ss = 3; /*@default use 3 Tx*/
++	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
++
++	if (idx < BEAMFORMEE_ENTRY_NUM)
++		beamformee_entry = beamforming_info->beamformee_entry[idx];
++	else
++		return;
++
++	nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer);
++
++	if (dm->rf_type == RF_1T1R)
++		return;
++
++	if (beamforming_info->beamformee_su_cnt > 0) {
++#if DEV_BUS_TYPE == RT_USB_INTERFACE
++		beamforming_info->last_usb_hub = *dm->hub_usb_mode;
++		tx_ss = *dm->hub_usb_mode;
++#endif
++		if (tx_ss == 3 || tx_ss == 2) {
++			if (dm->rf_type == RF_4T4R)
++				tx_ss = 0xf;
++			else if (dm->rf_type == RF_3T3R)
++				tx_ss = 0xe;
++			else
++				tx_ss = 0x6;
++		} else if (tx_ss == 1) /*USB 2.0 always 2Tx*/
++			tx_ss = 0x6;
++		else
++			tx_ss = 0x6;
++
++		if (tx_ss == 0xf) {
++			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f);
++			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0);
++		} else if (tx_ss == 0xe) {
++			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e);
++			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0);
++		} else if (tx_ss == 0x6) {
++			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936);
++			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360);
++		}
++
++		/*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
++		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/
++		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT30, 0x1); /*@if Nsts > Nc don't apply V matrix*/
++
++		if (idx == 0) {
++			switch (nr_index) {
++			case 0:
++				break;
++
++			case 1: /*Nsts = 2	BC*/
++				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
++				break;
++
++			case 2: /*Nsts = 3	BCD*/
++				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
++				break;
++
++			default: /*nr>3, same as Case 3*/
++				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
++
++				break;
++			}
++		} else {
++			switch (nr_index) {
++			case 0:
++				break;
++
++			case 1: /*Nsts = 2	BC*/
++				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
++				break;
++
++			case 2: /*Nsts = 3	BCD*/
++				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
++				break;
++
++			default: /*nr>3, same as Case 3*/
++				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
++				break;
++			}
++		}
++	}
++
++	if (beamforming_info->beamformee_su_cnt == 0 && beamforming_info->beamformer_su_cnt == 0) {
++		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x932); /*set tx_path selection for 8814a BFer bug refine*/
++		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e9360);
++	}
++}
++#if 0
++void
++hal_txbf_8814a_download_ndpa(
++	void			*dm_void,
++	u8				idx
++)
++{
++	struct dm_struct	*dm = (struct dm_struct *)dm_void;
++	u8			u1b_tmp = 0, tmp_reg422 = 0;
++	u8			bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
++	u16			head_page = 0x7FE;
++	boolean			is_send_beacon = false;
++	u16			tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*@default reseved 1 page for the IC type which is undefined.*/
++	struct _RT_BEAMFORMING_INFO	*beam_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY	*p_beam_entry = beam_info->beamformee_entry + idx;
++	void		*adapter = dm->adapter;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	*dm->is_fw_dw_rsvd_page_in_progress = true;
++#endif
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy);
++
++	/*Set REG_CR bit 8. DMA beacon by SW.*/
++	u1b_tmp = odm_read_1byte(dm, REG_CR_8814A + 1);
++	odm_write_1byte(dm,  REG_CR_8814A + 1, (u1b_tmp | BIT(0)));
++
++
++	/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
++	tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2);
++	odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2,  tmp_reg422 & (~BIT(6)));
++
++	if (tmp_reg422 & BIT(6)) {
++		PHYDM_DBG(dm, DBG_TXBF,
++			  "%s: There is an adapter is sending beacon.\n",
++			  __func__);
++		is_send_beacon = true;
++	}
++
++	/*@0x204[11:0]	Beacon Head for TXDMA*/
++	odm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, head_page);
++
++	do {
++		/*@Clear beacon valid check bit.*/
++		bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1);
++		odm_write_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7)));
++
++		/*@download NDPA rsvd page.*/
++		if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
++			beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE);
++		else
++			beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
++
++		/*@check rsvd page download OK.*/
++		bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1);
++		count = 0;
++		while (!(bcn_valid_reg & BIT(7)) && count < 20) {
++			count++;
++			ODM_delay_ms(10);
++			bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 2);
++		}
++		dl_bcn_count++;
++	} while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5);
++
++	if (!(bcn_valid_reg & BIT(7)))
++		PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n",
++			  __func__);
++
++	/*@0x204[11:0]	Beacon Head for TXDMA*/
++	odm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy);
++
++	/*To make sure that if there exists an adapter which would like to send beacon.*/
++	/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
++	/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
++	/*the beacon cannot be sent by HW.*/
++	/*@2010.06.23. Added by tynli.*/
++	if (is_send_beacon)
++		odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422);
++
++	/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
++	/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
++	u1b_tmp = odm_read_1byte(dm, REG_CR_8814A + 1);
++	odm_write_1byte(dm, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0))));
++
++	p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	*dm->is_fw_dw_rsvd_page_in_progress = false;
++#endif
++}
++
++void
++hal_txbf_8814a_fw_txbf_cmd(
++	void			*dm_void
++)
++{
++	struct dm_struct	*dm = (struct dm_struct *)dm_void;
++	u8	idx, period = 0;
++	u8	PageNum0 = 0xFF, PageNum1 = 0xFF;
++	u8	u1_tx_bf_parm[3] = {0};
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++
++	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
++		if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
++			if (beam_info->beamformee_entry[idx].is_sound) {
++				PageNum0 = 0xFE;
++				PageNum1 = 0x07;
++				period = (u8)(beam_info->beamformee_entry[idx].sound_period);
++			} else if (PageNum0 == 0xFF) {
++				PageNum0 = 0xFF; /*stop sounding*/
++				PageNum1 = 0x0F;
++			}
++		}
++	}
++
++	u1_tx_bf_parm[0] = PageNum0;
++	u1_tx_bf_parm[1] = PageNum1;
++	u1_tx_bf_parm[2] = period;
++	odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
++
++	PHYDM_DBG(dm, DBG_TXBF,
++		  "[%s] PageNum0 = %d, PageNum1 = %d period = %d\n", __func__,
++		  PageNum0, PageNum1, period);
++}
++#endif
++void hal_txbf_8814a_enter(void *dm_void, u8 bfer_bfee_idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i = 0;
++	u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
++	u8 bfee_idx = (bfer_bfee_idx & 0xF);
++	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
++	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
++	u16 sta_id = 0, csi_param = 0;
++	u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] bfer_idx=%d, bfee_idx=%d\n", __func__,
++		  bfer_idx, bfee_idx);
++	odm_set_mac_reg(dm, REG_SND_PTCL_CTRL_8814A, MASKBYTE1 | MASKBYTE2, 0x0202);
++
++	if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
++		beamformer_entry = beamforming_info->beamformer_entry[bfer_idx];
++		/*Sounding protocol control*/
++		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xDB);
++
++		/*@MAC address/Partial AID of Beamformer*/
++		if (bfer_idx == 0) {
++			for (i = 0; i < 6; i++)
++				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), beamformer_entry.mac_addr[i]);
++		} else {
++			for (i = 0; i < 6; i++)
++				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), beamformer_entry.mac_addr[i]);
++		}
++
++		/*@CSI report parameters of Beamformer*/
++		nc_index = hal_txbf_8814a_get_nrx(dm); /*@for 8814A nrx = 3(4 ant), min=0(1 ant)*/
++		nr_index = beamformer_entry.num_of_sounding_dim; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
++
++		grouping = 0;
++
++		/*@for ac = 1, for n = 3*/
++		if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)
++			codebookinfo = 1;
++		else if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT)
++			codebookinfo = 3;
++
++		coefficientsize = 3;
++
++		csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index));
++
++		if (bfer_idx == 0)
++			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, csi_param);
++		else
++			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, csi_param);
++		/*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/
++		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A + 3, 0x40);
++	}
++
++	if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
++		beamformee_entry = beamforming_info->beamformee_entry[bfee_idx];
++
++		hal_txbf_8814a_rf_mode(dm, beamforming_info, bfee_idx);
++
++		if (phydm_acting_determine(dm, phydm_acting_as_ibss))
++			sta_id = beamformee_entry.mac_id;
++		else
++			sta_id = beamformee_entry.p_aid;
++
++		/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
++		if (bfee_idx == 0) {
++			odm_write_2byte(dm, REG_TXBF_CTRL_8814A, sta_id);
++			odm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7));
++		} else
++			odm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, sta_id | BIT(14) | BIT(15) | BIT(12));
++
++		/*@CSI report parameters of Beamformee*/
++		if (bfee_idx == 0) {
++			/*@Get BIT24 & BIT25*/
++			u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3;
++
++			odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60);
++			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, sta_id | BIT(9));
++		} else
++			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT25*/
++
++		phydm_beamforming_notify(dm);
++	}
++}
++
++void hal_txbf_8814a_leave(void *dm_void, u8 idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
++	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
++
++	if (idx < BEAMFORMER_ENTRY_NUM) {
++		beamformer_entry = beamforming_info->beamformer_entry[idx];
++		beamformee_entry = beamforming_info->beamformee_entry[idx];
++	} else
++		return;
++
++	/*@Clear P_AID of Beamformee*/
++	/*@Clear MAC address of Beamformer*/
++	/*@Clear Associated Bfmee Sel*/
++
++	if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
++		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xD8);
++		if (idx == 0) {
++			odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0);
++			odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0);
++			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, 0);
++		} else {
++			odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0);
++			odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0);
++			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0);
++		}
++	}
++
++	if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
++		hal_txbf_8814a_rf_mode(dm, beamforming_info, idx);
++		if (idx == 0) {
++			odm_write_2byte(dm, REG_TXBF_CTRL_8814A, 0x0);
++			odm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7));
++			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0);
++		} else {
++			odm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT(14) | BIT(15) | BIT(12));
++
++			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60);
++		}
++	}
++}
++
++void hal_txbf_8814a_status(void *dm_void, u8 idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u16 beam_ctrl_val, tmp_val;
++	u32 beam_ctrl_reg;
++	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY beamform_entry;
++
++	if (idx < BEAMFORMEE_ENTRY_NUM)
++		beamform_entry = beamforming_info->beamformee_entry[idx];
++	else
++		return;
++
++	if (phydm_acting_determine(dm, phydm_acting_as_ibss))
++		beam_ctrl_val = beamform_entry.mac_id;
++	else
++		beam_ctrl_val = beamform_entry.p_aid;
++
++	PHYDM_DBG(dm, DBG_TXBF, "@%s, beamform_entry.beamform_entry_state = %d",
++		  __func__, beamform_entry.beamform_entry_state);
++
++	if (idx == 0)
++		beam_ctrl_reg = REG_TXBF_CTRL_8814A;
++	else {
++		beam_ctrl_reg = REG_TXBF_CTRL_8814A + 2;
++		beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
++	}
++
++	if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beamforming_info->apply_v_matrix == true) {
++		if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
++			beam_ctrl_val |= BIT(9);
++		else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
++			beam_ctrl_val |= (BIT(9) | BIT(10));
++		else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80)
++			beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));
++	} else {
++		PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix", __func__);
++		beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
++	}
++
++	odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
++	/*@disable NDP packet use beamforming */
++	tmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8814A);
++	odm_write_2byte(dm, REG_TXBF_CTRL_8814A, tmp_val | BIT(15));
++}
++
++void hal_txbf_8814a_fw_txbf(void *dm_void, u8 idx)
++{
++#if 0
++	struct dm_struct	*dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO	*beam_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY	*p_beam_entry = beam_info->beamformee_entry + idx;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
++		hal_txbf_8814a_download_ndpa(dm, idx);
++
++	hal_txbf_8814a_fw_txbf_cmd(dm);
++#endif
++}
++
++#endif /* @(RTL8814A_SUPPORT == 1)*/
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8814a.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8814a.h
+new file mode 100644
+index 000000000..61b33bbfb
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8814a.h
+@@ -0,0 +1,77 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++#ifndef __HAL_TXBF_8814A_H__
++#define __HAL_TXBF_8814A_H__
++
++#if (RTL8814A_SUPPORT == 1)
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++
++boolean
++phydm_beamforming_set_iqgen_8814A(void *dm_void);
++
++void hal_txbf_8814a_set_ndpa_rate(void *dm_void, u8 BW, u8 rate);
++
++u8 hal_txbf_8814a_get_ntx(void *dm_void);
++
++void hal_txbf_8814a_enter(void *dm_void, u8 idx);
++
++void hal_txbf_8814a_leave(void *dm_void, u8 idx);
++
++void hal_txbf_8814a_status(void *dm_void, u8 idx);
++
++void hal_txbf_8814a_reset_tx_path(void *dm_void, u8 idx);
++
++void hal_txbf_8814a_get_tx_rate(void *dm_void);
++
++void hal_txbf_8814a_fw_txbf(void *dm_void, u8 idx);
++
++#else
++
++#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate)
++#define hal_txbf_8814a_get_ntx(dm_void) 0
++#define hal_txbf_8814a_enter(dm_void, idx)
++#define hal_txbf_8814a_leave(dm_void, idx)
++#define hal_txbf_8814a_status(dm_void, idx)
++#define hal_txbf_8814a_reset_tx_path(dm_void, idx)
++#define hal_txbf_8814a_get_tx_rate(dm_void)
++#define hal_txbf_8814a_fw_txbf(dm_void, idx)
++#define phydm_beamforming_set_iqgen_8814A(dm_void) 0
++
++#endif
++
++#else
++
++#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate)
++#define hal_txbf_8814a_get_ntx(dm_void) 0
++#define hal_txbf_8814a_enter(dm_void, idx)
++#define hal_txbf_8814a_leave(dm_void, idx)
++#define hal_txbf_8814a_status(dm_void, idx)
++#define hal_txbf_8814a_reset_tx_path(dm_void, idx)
++#define hal_txbf_8814a_get_tx_rate(dm_void)
++#define hal_txbf_8814a_fw_txbf(dm_void, idx)
++#define phydm_beamforming_set_iqgen_8814A(dm_void) 0
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8822b.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8822b.c
+new file mode 100644
+index 000000000..a1d35c9b1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8822b.c
+@@ -0,0 +1,1088 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*@============================================================*/
++/* @Description:                                              */
++/*                                                           @*/
++/* This file is for 8814A TXBF mechanism                     */
++/*                                                           @*/
++/*@============================================================*/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#if (RTL8822B_SUPPORT == 1)
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++
++u8 hal_txbf_8822b_get_ntx(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 ntx = 0;
++
++#if DEV_BUS_TYPE == RT_USB_INTERFACE
++	if (dm->support_interface == ODM_ITRF_USB) {
++		if (*dm->hub_usb_mode == 2) { /*USB3.0*/
++			if (dm->rf_type == RF_4T4R)
++				ntx = 3;
++			else if (dm->rf_type == RF_3T3R)
++				ntx = 2;
++			else
++				ntx = 1;
++		} else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/
++			ntx = 1;
++		else
++			ntx = 1;
++	} else
++#endif
++	{
++		if (dm->rf_type == RF_4T4R)
++			ntx = 3;
++		else if (dm->rf_type == RF_3T3R)
++			ntx = 2;
++		else
++			ntx = 1;
++	}
++
++	return ntx;
++}
++
++u8 hal_txbf_8822b_get_nrx(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 nrx = 0;
++
++	if (dm->rf_type == RF_4T4R)
++		nrx = 3;
++	else if (dm->rf_type == RF_3T3R)
++		nrx = 2;
++	else if (dm->rf_type == RF_2T2R)
++		nrx = 1;
++	else if (dm->rf_type == RF_2T3R)
++		nrx = 2;
++	else if (dm->rf_type == RF_2T4R)
++		nrx = 3;
++	else if (dm->rf_type == RF_1T1R)
++		nrx = 0;
++	else if (dm->rf_type == RF_1T2R)
++		nrx = 1;
++	else
++		nrx = 0;
++
++	return nrx;
++}
++
++/***************SU & MU BFee Entry********************/
++void hal_txbf_8822b_rf_mode(
++	void *dm_void,
++	struct _RT_BEAMFORMING_INFO *beamforming_info,
++	u8 idx)
++{
++#if 0
++	struct dm_struct	*dm = (struct dm_struct *)dm_void;
++	u8				i, nr_index = 0;
++	boolean				is_self_beamformer = false;
++	boolean				is_self_beamformee = false;
++	struct _RT_BEAMFORMEE_ENTRY	beamformee_entry;
++
++	if (idx < BEAMFORMEE_ENTRY_NUM)
++		beamformee_entry = beamforming_info->beamformee_entry[idx];
++	else
++		return;
++
++	if (dm->rf_type == RF_1T1R)
++		return;
++
++	for (i = RF_PATH_A; i < RF_PATH_B; i++) {
++		odm_set_rf_reg(dm, (enum rf_path)i, rf_welut_jaguar, 0x80000, 0x1);
++		/*RF mode table write enable*/
++	}
++
++	if (beamforming_info->beamformee_su_cnt > 0 || beamforming_info->beamformee_mu_cnt > 0) {
++		for (i = RF_PATH_A; i < RF_PATH_B; i++) {
++			odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_addr, 0xfffff, 0x18000);
++			/*Select RX mode*/
++			odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_data0, 0xfffff, 0xBE77F);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_data1, 0xfffff, 0x226BF);
++			/*@Enable TXIQGEN in RX mode*/
++		}
++		odm_set_rf_reg(dm, RF_PATH_A, rf_mode_table_data1, 0xfffff, 0xE26BF);
++		/*@Enable TXIQGEN in RX mode*/
++	}
++
++	for (i = RF_PATH_A; i < RF_PATH_B; i++) {
++		odm_set_rf_reg(dm, (enum rf_path)i, rf_welut_jaguar, 0x80000, 0x0);
++		/*RF mode table write disable*/
++	}
++
++	if (beamforming_info->beamformee_su_cnt > 0) {
++		/*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
++		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2);			/*@enable BB TxBF ant mapping register*/
++
++		if (idx == 0) {
++			/*Nsts = 2	AB*/
++			odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8822B, 0xffff, 0x0433);
++			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
++			/*odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430);*/
++
++		} else {/*@IDX =1*/
++			odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433);
++			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
++			/*odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430;*/
++		}
++	} else {
++		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*@1SS by path-A*/
++		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*@2SS by path-A,B*/
++	}
++
++	if (beamforming_info->beamformee_mu_cnt > 0) {
++		/*@MU STAs share the common setting*/
++		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1);
++		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433);
++		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
++	}
++#endif
++}
++#if 0
++void
++hal_txbf_8822b_download_ndpa(
++	void			*adapter,
++	u8				idx
++)
++{
++	u8			u1b_tmp = 0, tmp_reg422 = 0;
++	u8			bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
++	u16			head_page = 0x7FE;
++	boolean			is_send_beacon = false;
++	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(adapter);
++	u16			tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*@default reseved 1 page for the IC type which is undefined.*/
++	struct _RT_BEAMFORMING_INFO	*beam_info = GET_BEAMFORM_INFO(adapter);
++	struct _RT_BEAMFORMEE_ENTRY	*p_beam_entry = beam_info->beamformee_entry + idx;
++
++	hal_data->is_fw_dw_rsvd_page_in_progress = true;
++	phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy);
++
++	/*Set REG_CR bit 8. DMA beacon by SW.*/
++	u1b_tmp = platform_efio_read_1byte(adapter, REG_CR_8814A + 1);
++	platform_efio_write_1byte(adapter,  REG_CR_8814A + 1, (u1b_tmp | BIT(0)));
++
++
++	/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
++	tmp_reg422 = platform_efio_read_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2);
++	platform_efio_write_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2,  tmp_reg422 & (~BIT(6)));
++
++	if (tmp_reg422 & BIT(6)) {
++		RT_TRACE(COMP_INIT, DBG_LOUD, ("SetBeamformDownloadNDPA_8814A(): There is an adapter is sending beacon.\n"));
++		is_send_beacon = true;
++	}
++
++	/*@0x204[11:0]	Beacon Head for TXDMA*/
++	platform_efio_write_2byte(adapter, REG_FIFOPAGE_CTRL_2_8814A, head_page);
++
++	do {
++		/*@Clear beacon valid check bit.*/
++		bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1);
++		platform_efio_write_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7)));
++
++		/*@download NDPA rsvd page.*/
++		if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
++			beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE);
++		else
++			beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
++
++		/*@check rsvd page download OK.*/
++		bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1);
++		count = 0;
++		while (!(bcn_valid_reg & BIT(7)) && count < 20) {
++			count++;
++			delay_us(10);
++			bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 2);
++		}
++		dl_bcn_count++;
++	} while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5);
++
++	if (!(bcn_valid_reg & BIT(0)))
++		RT_DISP(FBEAM, FBEAM_ERROR, ("%s Download RSVD page failed!\n", __func__));
++
++	/*@0x204[11:0]	Beacon Head for TXDMA*/
++	platform_efio_write_2byte(adapter, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy);
++
++	/*To make sure that if there exists an adapter which would like to send beacon.*/
++	/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
++	/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
++	/*the beacon cannot be sent by HW.*/
++	/*@2010.06.23. Added by tynli.*/
++	if (is_send_beacon)
++		platform_efio_write_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422);
++
++	/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
++	/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
++	u1b_tmp = platform_efio_read_1byte(adapter, REG_CR_8814A + 1);
++	platform_efio_write_1byte(adapter, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0))));
++
++	p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
++
++	hal_data->is_fw_dw_rsvd_page_in_progress = false;
++}
++
++void
++hal_txbf_8822b_fw_txbf_cmd(
++	void	*adapter
++)
++{
++	u8	idx, period = 0;
++	u8	PageNum0 = 0xFF, PageNum1 = 0xFF;
++	u8	u1_tx_bf_parm[3] = {0};
++
++	PMGNT_INFO				mgnt_info = &(adapter->MgntInfo);
++	struct _RT_BEAMFORMING_INFO	*beam_info = GET_BEAMFORM_INFO(adapter);
++
++	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
++		if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
++			if (beam_info->beamformee_entry[idx].is_sound) {
++				PageNum0 = 0xFE;
++				PageNum1 = 0x07;
++				period = (u8)(beam_info->beamformee_entry[idx].sound_period);
++			} else if (PageNum0 == 0xFF) {
++				PageNum0 = 0xFF; /*stop sounding*/
++				PageNum1 = 0x0F;
++			}
++		}
++	}
++
++	u1_tx_bf_parm[0] = PageNum0;
++	u1_tx_bf_parm[1] = PageNum1;
++	u1_tx_bf_parm[2] = period;
++	fill_h2c_cmd(adapter, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
++
++	RT_DISP(FBEAM, FBEAM_FUN, ("@%s End, PageNum0 = 0x%x, PageNum1 = 0x%x period = %d", __func__, PageNum0, PageNum1, period));
++}
++#endif
++
++#if 0
++void
++hal_txbf_8822b_init(
++	void			*dm_void
++)
++{
++	struct dm_struct	*dm = (struct dm_struct *)dm_void;
++	u8		u1b_tmp;
++	struct _RT_BEAMFORMING_INFO		*beamforming_info = &dm->beamforming_info;
++	void				*adapter = dm->adapter;
++
++	odm_set_bb_reg(dm, R_0x14c0, BIT(16), 1); /*@Enable P1 aggr new packet according to P0 transfer time*/
++	odm_set_bb_reg(dm, R_0x14c0, BIT(15) | BIT14 | BIT13 | BIT12, 10); /*@MU Retry Limit*/
++	odm_set_bb_reg(dm, R_0x14c0, BIT(7), 0); /*@Disable Tx MU-MIMO until sounding done*/
++	odm_set_bb_reg(dm, R_0x14c0, 0x3F, 0); /* @Clear validity of MU STAs */
++	odm_write_1byte(dm, 0x167c, 0x70); /*@MU-MIMO Option as default value*/
++	odm_write_2byte(dm, 0x1680, 0); /*@MU-MIMO Control as default value*/
++
++	/* Set MU NDPA rate & BW source */
++	/* @0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */
++	u1b_tmp = odm_read_1byte(dm, 0x42C);
++	odm_write_1byte(dm, REG_TXBF_CTRL_8822B, (u1b_tmp | BIT(6)));
++	/* @0x45F[7:0] = 0x10 (rate=OFDM_6M, BW20) */
++	odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8822B, 0x10);
++
++	/*Temp Settings*/
++	odm_set_bb_reg(dm, R_0x6dc, 0x3F000000, 4); /*STA2's CSI rate is fixed at 6M*/
++	odm_set_bb_reg(dm, R_0x1c94, MASKDWORD, 0xAFFFAFFF); /*@Grouping bitmap parameters*/
++
++	/* @Init HW variable */
++	beamforming_info->reg_mu_tx_ctrl = odm_read_4byte(dm, 0x14c0);
++
++	if (dm->rf_type == RF_2T2R) { /*@2T2R*/
++		PHYDM_DBG(dm, DBG_TXBF, "%s: rf_type is 2T2R\n", __func__);
++		config_phydm_trx_mode_8822b(dm, (enum bb_path)3,
++					    (enum bb_path)3, BB_PATH_AB;
++	}
++
++#if (OMNIPEEK_SNIFFER_ENABLED == 1)
++	/* @Config HW to receive packet on the user position from registry for sniffer mode. */
++	/* odm_set_bb_reg(dm, R_0xb00, BIT(9), 1);*/ /* For A-cut only. RegB00[9] = 1 (enable PMAC Rx) */
++	odm_set_bb_reg(dm, R_0xb54, BIT(30), 1); /* RegB54[30] = 1 (force user position) */
++	odm_set_bb_reg(dm, R_0xb54, (BIT(29) | BIT28), adapter->MgntInfo.sniff_user_position); /* RegB54[29:28] = user position (0~3) */
++	PHYDM_DBG(dm, DBG_TXBF,
++		  "Set adapter->MgntInfo.sniff_user_position=%#X\n",
++		  adapter->MgntInfo.sniff_user_position);
++#endif
++}
++#endif
++
++void hal_txbf_8822b_enter(
++	void *dm_void,
++	u8 bfer_bfee_idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i = 0;
++	u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
++	u8 bfee_idx = (bfer_bfee_idx & 0xF);
++	u16 csi_param = 0;
++	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry;
++	struct _RT_BEAMFORMER_ENTRY *beamformer_entry;
++	u16 value16, sta_id = 0;
++	u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;
++	u32 gid_valid, user_position_l, user_position_h;
++	u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e};
++	u8 u1b_tmp;
++	u32 u4b_tmp;
++
++	RT_DISP(FBEAM, FBEAM_FUN, ("%s: bfer_bfee_idx=%d, bfer_idx=%d, bfee_idx=%d\n", __func__, bfer_bfee_idx, bfer_idx, bfee_idx));
++
++	/*************SU BFer Entry Init*************/
++	if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
++		beamformer_entry = &beamforming_info->beamformer_entry[bfer_idx];
++		beamformer_entry->is_mu_ap = false;
++		/*Sounding protocol control*/
++		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB);
++
++		for (i = 0; i < MAX_BEAMFORMER_SU; i++) {
++			if ((beamforming_info->beamformer_su_reg_maping & BIT(i)) == 0) {
++				beamforming_info->beamformer_su_reg_maping |= BIT(i);
++				beamformer_entry->su_reg_index = i;
++				break;
++			}
++		}
++
++		/*@MAC address/Partial AID of Beamformer*/
++		if (beamformer_entry->su_reg_index == 0) {
++			for (i = 0; i < 6; i++)
++				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), beamformer_entry->mac_addr[i]);
++		} else {
++			for (i = 0; i < 6; i++)
++				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8822B + i), beamformer_entry->mac_addr[i]);
++		}
++
++		/*@CSI report parameters of Beamformer*/
++		nc_index = hal_txbf_8822b_get_nrx(dm); /*@for 8814A nrx = 3(4 ant), min=0(1 ant)*/
++		nr_index = beamformer_entry->num_of_sounding_dim; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
++
++		grouping = 0;
++
++		/*@for ac = 1, for n = 3*/
++		if (beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)
++			codebookinfo = 1;
++		else if (beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT)
++			codebookinfo = 3;
++
++		coefficientsize = 3;
++
++		csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index));
++
++		if (bfer_idx == 0)
++			odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B, csi_param);
++		else
++			odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, csi_param);
++		/*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/
++		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B + 3, 0x70);
++	}
++
++	/*************SU BFee Entry Init*************/
++	if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
++		p_beamformee_entry = &beamforming_info->beamformee_entry[bfee_idx];
++		p_beamformee_entry->is_mu_sta = false;
++		hal_txbf_8822b_rf_mode(dm, beamforming_info, bfee_idx);
++
++		if (phydm_acting_determine(dm, phydm_acting_as_ibss))
++			sta_id = p_beamformee_entry->mac_id;
++		else
++			sta_id = p_beamformee_entry->p_aid;
++
++		for (i = 0; i < MAX_BEAMFORMEE_SU; i++) {
++			if ((beamforming_info->beamformee_su_reg_maping & BIT(i)) == 0) {
++				beamforming_info->beamformee_su_reg_maping |= BIT(i);
++				p_beamformee_entry->su_reg_index = i;
++				break;
++			}
++		}
++
++		/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
++		if (p_beamformee_entry->su_reg_index == 0) {
++			odm_write_2byte(dm, REG_TXBF_CTRL_8822B, sta_id);
++			odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7));
++		} else
++			odm_write_2byte(dm, REG_TXBF_CTRL_8822B + 2, sta_id | BIT(14) | BIT(15) | BIT(12));
++
++		/*@CSI report parameters of Beamformee*/
++		if (p_beamformee_entry->su_reg_index == 0) {
++			/*@Get BIT24 & BIT25*/
++			u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3) & 0x3;
++
++			odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3, tmp | 0x60);
++			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B, sta_id | BIT(9));
++		} else
++			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, sta_id | 0xE200); /*Set BIT25*/
++
++		phydm_beamforming_notify(dm);
++	}
++
++	/*************MU BFer Entry Init*************/
++	if (beamforming_info->beamformer_mu_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
++		beamformer_entry = &beamforming_info->beamformer_entry[bfer_idx];
++		beamforming_info->mu_ap_index = bfer_idx;
++		beamformer_entry->is_mu_ap = true;
++		for (i = 0; i < 8; i++)
++			beamformer_entry->gid_valid[i] = 0;
++		for (i = 0; i < 16; i++)
++			beamformer_entry->user_position[i] = 0;
++
++		/*Sounding protocol control*/
++		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB);
++
++		/* @MAC address */
++		for (i = 0; i < 6; i++)
++			odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), beamformer_entry->mac_addr[i]);
++
++		/* Set partial AID */
++		odm_write_2byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + 6), beamformer_entry->p_aid);
++
++		/* @Fill our AID to 0x1680[11:0] and [13:12] = 2b'00, BF report segment select to 3895 bytes*/
++		u1b_tmp = odm_read_1byte(dm, 0x1680);
++		u1b_tmp = (beamformer_entry->p_aid) & 0xFFF;
++		odm_write_1byte(dm, 0x1680, u1b_tmp);
++
++		/* Set 80us for leaving ndp_rx_standby_state */
++		odm_write_1byte(dm, 0x71B, 0x50);
++
++		/* Set 0x6A0[14] = 1 to accept action_no_ack */
++		u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP0_8822B + 1);
++		u1b_tmp |= 0x40;
++		odm_write_1byte(dm, REG_RXFLTMAP0_8822B + 1, u1b_tmp);
++		/* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */
++		u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP1_8822B);
++		u1b_tmp |= 0x30;
++		odm_write_1byte(dm, REG_RXFLTMAP1_8822B, u1b_tmp);
++
++		/*@CSI report parameters of Beamformer*/
++		nc_index = hal_txbf_8822b_get_nrx(dm); /* @Depend on RF type */
++		nr_index = 1; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
++		grouping = 0; /*no grouping*/
++		codebookinfo = 1; /*@7 bit for psi, 9 bit for phi*/
++		coefficientsize = 0; /*This is nothing really matter*/
++		csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index));
++		odm_write_2byte(dm, 0x6F4, csi_param);
++
++		/*@for B-cut*/
++		odm_set_bb_reg(dm, R_0x6a0, BIT(20), 0);
++		odm_set_bb_reg(dm, R_0x688, BIT(20), 0);
++	}
++
++	/*************MU BFee Entry Init*************/
++	if (beamforming_info->beamformee_mu_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
++		p_beamformee_entry = &beamforming_info->beamformee_entry[bfee_idx];
++		p_beamformee_entry->is_mu_sta = true;
++		for (i = 0; i < MAX_BEAMFORMEE_MU; i++) {
++			if ((beamforming_info->beamformee_mu_reg_maping & BIT(i)) == 0) {
++				beamforming_info->beamformee_mu_reg_maping |= BIT(i);
++				p_beamformee_entry->mu_reg_index = i;
++				break;
++			}
++		}
++
++		if (p_beamformee_entry->mu_reg_index == 0xFF) {
++			/* There is no valid bit in beamformee_mu_reg_maping */
++			RT_DISP(FBEAM, FBEAM_FUN, ("%s: ERROR! There is no valid bit in beamformee_mu_reg_maping!\n", __func__));
++			return;
++		}
++
++		/*User position table*/
++		switch (p_beamformee_entry->mu_reg_index) {
++		case 0:
++			gid_valid = 0x7fe;
++			user_position_l = 0x111110;
++			user_position_h = 0x0;
++			break;
++		case 1:
++			gid_valid = 0x7f806;
++			user_position_l = 0x11000004;
++			user_position_h = 0x11;
++			break;
++		case 2:
++			gid_valid = 0x1f81818;
++			user_position_l = 0x400040;
++			user_position_h = 0x11100;
++			break;
++		case 3:
++			gid_valid = 0x1e186060;
++			user_position_l = 0x4000400;
++			user_position_h = 0x1100040;
++			break;
++		case 4:
++			gid_valid = 0x66618180;
++			user_position_l = 0x40004000;
++			user_position_h = 0x10040400;
++			break;
++		case 5:
++			gid_valid = 0x79860600;
++			user_position_l = 0x40000;
++			user_position_h = 0x4404004;
++			break;
++		}
++
++		for (i = 0; i < 8; i++) {
++			if (i < 4) {
++				p_beamformee_entry->gid_valid[i] = (u8)(gid_valid & 0xFF);
++				gid_valid = (gid_valid >> 8);
++			} else
++				p_beamformee_entry->gid_valid[i] = 0;
++		}
++		for (i = 0; i < 16; i++) {
++			if (i < 4)
++				p_beamformee_entry->user_position[i] = (u8)((user_position_l >> (i * 8)) & 0xFF);
++			else if (i < 8)
++				p_beamformee_entry->user_position[i] = (u8)((user_position_h >> ((i - 4) * 8)) & 0xFF);
++			else
++				p_beamformee_entry->user_position[i] = 0;
++		}
++
++		/*Sounding protocol control*/
++		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB);
++
++		/*select MU STA table*/
++		beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));
++		beamforming_info->reg_mu_tx_ctrl |= (p_beamformee_entry->mu_reg_index << 8) & (BIT(8) | BIT(9) | BIT(10));
++		odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
++
++		odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, 0); /*Reset gid_valid table*/
++		odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l);
++		odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h);
++
++		/*set validity of MU STAs*/
++		beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0;
++		beamforming_info->reg_mu_tx_ctrl |= beamforming_info->beamformee_mu_reg_maping & 0x3F;
++		odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
++
++		PHYDM_DBG(dm, DBG_TXBF,
++			  "@%s, reg_mu_tx_ctrl = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n",
++			  __func__, beamforming_info->reg_mu_tx_ctrl,
++			  user_position_l, user_position_h);
++
++		value16 = odm_read_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index]);
++		value16 &= 0xFE00; /*@Clear PAID*/
++		value16 |= BIT(9); /*@Enable MU BFee*/
++		value16 |= p_beamformee_entry->p_aid;
++		odm_write_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index], value16);
++
++		/* @0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */
++		u1b_tmp = odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3);
++		u1b_tmp |= 0xD0; /* Set bit 28, 30, 31 to 3b'111*/
++		odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, u1b_tmp);
++		/* Set NDPA to 6M*/
++		odm_write_1byte(dm, REG_NDPA_RATE_8822B, 0x4);
++
++		u1b_tmp = odm_read_1byte(dm, REG_NDPA_OPT_CTRL_8822B);
++		u1b_tmp &= 0xFC; /* @Clear bit 0, 1*/
++		odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8822B, u1b_tmp);
++
++		u4b_tmp = odm_read_4byte(dm, REG_SND_PTCL_CTRL_8822B);
++		u4b_tmp = ((u4b_tmp & 0xFF0000FF) | 0x020200); /* Set [23:8] to 0x0202*/
++		odm_write_4byte(dm, REG_SND_PTCL_CTRL_8822B, u4b_tmp);
++
++		/* Set 0x6A0[14] = 1 to accept action_no_ack */
++		u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP0_8822B + 1);
++		u1b_tmp |= 0x40;
++		odm_write_1byte(dm, REG_RXFLTMAP0_8822B + 1, u1b_tmp);
++		/* @End of MAC registers setting */
++
++		hal_txbf_8822b_rf_mode(dm, beamforming_info, bfee_idx);
++#if (SUPPORT_MU_BF == 1)
++		/*Special for plugfest*/
++		delay_ms(50); /* wait for 4-way handshake ending*/
++		send_sw_vht_gid_mgnt_frame(dm, p_beamformee_entry->mac_addr, bfee_idx);
++#endif
++
++		phydm_beamforming_notify(dm);
++#if 1
++		{
++			u32 ctrl_info_offset, index;
++			/*Set Ctrl Info*/
++			odm_write_2byte(dm, 0x140, 0x660);
++			ctrl_info_offset = 0x8000 + 32 * p_beamformee_entry->mac_id;
++			/*Reset Ctrl Info*/
++			for (index = 0; index < 8; index++)
++				odm_write_4byte(dm, ctrl_info_offset + index * 4, 0);
++
++			odm_write_4byte(dm, ctrl_info_offset, (p_beamformee_entry->mu_reg_index + 1) << 16);
++			odm_write_1byte(dm, 0x81, 0x80); /*RPTBUF ready*/
++
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "@%s, mac_id = %d, ctrl_info_offset = 0x%x, mu_reg_index = %x\n",
++				  __func__, p_beamformee_entry->mac_id,
++				  ctrl_info_offset,
++				  p_beamformee_entry->mu_reg_index);
++		}
++#endif
++	}
++}
++
++void hal_txbf_8822b_leave(
++	void *dm_void,
++	u8 idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMER_ENTRY *beamformer_entry;
++	struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry;
++	u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e};
++
++	if (idx < BEAMFORMER_ENTRY_NUM) {
++		beamformer_entry = &beamforming_info->beamformer_entry[idx];
++		p_beamformee_entry = &beamforming_info->beamformee_entry[idx];
++	} else
++		return;
++
++	/*@Clear P_AID of Beamformee*/
++	/*@Clear MAC address of Beamformer*/
++	/*@Clear Associated Bfmee Sel*/
++
++	if (beamformer_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) {
++		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xD8);
++		if (beamformer_entry->is_mu_ap == 0) { /*SU BFer */
++			if (beamformer_entry->su_reg_index == 0) {
++				odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8822B, 0);
++				odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8822B + 4, 0);
++				odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B, 0);
++			} else {
++				odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8822B, 0);
++				odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8822B + 4, 0);
++				odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, 0);
++			}
++			beamforming_info->beamformer_su_reg_maping &= ~(BIT(beamformer_entry->su_reg_index));
++			beamformer_entry->su_reg_index = 0xFF;
++		} else { /*@MU BFer */
++			/*set validity of MU STA0 and MU STA1*/
++			beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0;
++			odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
++
++			odm_memory_set(dm, beamformer_entry->gid_valid, 0, 8);
++			odm_memory_set(dm, beamformer_entry->user_position, 0, 16);
++			beamformer_entry->is_mu_ap = false;
++		}
++	}
++
++	if (p_beamformee_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) {
++		hal_txbf_8822b_rf_mode(dm, beamforming_info, idx);
++		if (p_beamformee_entry->is_mu_sta == 0) { /*SU BFee*/
++			if (p_beamformee_entry->su_reg_index == 0) {
++				odm_write_2byte(dm, REG_TXBF_CTRL_8822B, 0x0);
++				odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7));
++				odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B, 0);
++			} else {
++				odm_write_2byte(dm, REG_TXBF_CTRL_8822B + 2, 0x0 | BIT(14) | BIT(15) | BIT(12));
++
++				odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2,
++						odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2) & 0x60);
++			}
++			beamforming_info->beamformee_su_reg_maping &= ~(BIT(p_beamformee_entry->su_reg_index));
++			p_beamformee_entry->su_reg_index = 0xFF;
++		} else { /*@MU BFee */
++			/*@Disable sending NDPA & BF-rpt-poll to this BFee*/
++			odm_write_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index], 0);
++			/*set validity of MU STA*/
++			beamforming_info->reg_mu_tx_ctrl &= ~(BIT(p_beamformee_entry->mu_reg_index));
++			odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
++
++			p_beamformee_entry->is_mu_sta = false;
++			beamforming_info->beamformee_mu_reg_maping &= ~(BIT(p_beamformee_entry->mu_reg_index));
++			p_beamformee_entry->mu_reg_index = 0xFF;
++		}
++	}
++}
++
++/***********SU & MU BFee Entry Only when souding done****************/
++void hal_txbf_8822b_status(
++	void *dm_void,
++	u8 beamform_idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u16 beam_ctrl_val, tmp_val;
++	u32 beam_ctrl_reg;
++	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry;
++	boolean is_mu_sounding = beamforming_info->is_mu_sounding, is_bitmap_ready = false;
++	u16 bitmap;
++	u8 idx, gid, i;
++	u8 id1, id0;
++	u32 gid_valid[6] = {0};
++	u32 value32;
++	boolean is_sounding_success[6] = {false};
++
++	if (beamform_idx < BEAMFORMEE_ENTRY_NUM)
++		beamform_entry = &beamforming_info->beamformee_entry[beamform_idx];
++	else
++		return;
++
++	/*SU sounding done */
++	if (is_mu_sounding == false) {
++		if (phydm_acting_determine(dm, phydm_acting_as_ibss))
++			beam_ctrl_val = beamform_entry->mac_id;
++		else
++			beam_ctrl_val = beamform_entry->p_aid;
++
++		PHYDM_DBG(dm, DBG_TXBF,
++			  "@%s, beamform_entry.beamform_entry_state = %d",
++			  __func__, beamform_entry->beamform_entry_state);
++
++		if (beamform_entry->su_reg_index == 0)
++			beam_ctrl_reg = REG_TXBF_CTRL_8822B;
++		else {
++			beam_ctrl_reg = REG_TXBF_CTRL_8822B + 2;
++			beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
++		}
++
++		if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
++			if (beamform_entry->sound_bw == CHANNEL_WIDTH_20)
++				beam_ctrl_val |= BIT(9);
++			else if (beamform_entry->sound_bw == CHANNEL_WIDTH_40)
++				beam_ctrl_val |= (BIT(9) | BIT(10));
++			else if (beamform_entry->sound_bw == CHANNEL_WIDTH_80)
++				beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));
++		} else {
++			PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix",
++				  __func__);
++			beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
++		}
++
++		odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
++		/*@disable NDP packet use beamforming */
++		tmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8822B);
++		odm_write_2byte(dm, REG_TXBF_CTRL_8822B, tmp_val | BIT(15));
++	} else {
++		PHYDM_DBG(dm, DBG_TXBF, "@%s, MU Sounding Done\n", __func__);
++		/*@MU sounding done */
++		if (1) { /* @(beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { */
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "@%s, BEAMFORMING_ENTRY_STATE_PROGRESSED\n",
++				  __func__);
++
++			value32 = odm_get_bb_reg(dm, R_0x1684, MASKDWORD);
++			is_sounding_success[0] = (value32 & BIT(10)) ? 1 : 0;
++			is_sounding_success[1] = (value32 & BIT(26)) ? 1 : 0;
++			value32 = odm_get_bb_reg(dm, R_0x1688, MASKDWORD);
++			is_sounding_success[2] = (value32 & BIT(10)) ? 1 : 0;
++			is_sounding_success[3] = (value32 & BIT(26)) ? 1 : 0;
++			value32 = odm_get_bb_reg(dm, R_0x168c, MASKDWORD);
++			is_sounding_success[4] = (value32 & BIT(10)) ? 1 : 0;
++			is_sounding_success[5] = (value32 & BIT(26)) ? 1 : 0;
++
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "@%s, is_sounding_success STA1:%d,  STA2:%d, STA3:%d, STA4:%d, STA5:%d, STA6:%d\n",
++				  __func__, is_sounding_success[0],
++				  is_sounding_success[1],
++				  is_sounding_success[2],
++				  is_sounding_success[3],
++				  is_sounding_success[4],
++				  is_sounding_success[5]);
++
++			value32 = odm_get_bb_reg(dm, R_0xf4c, 0xFFFF0000);
++			/* odm_set_bb_reg(dm, R_0x19e0, MASKHWORD, 0xFFFF);Let MAC ignore bitmap */
++
++			is_bitmap_ready = (boolean)((value32 & BIT(15)) >> 15);
++			bitmap = (u16)(value32 & 0x3FFF);
++
++			for (idx = 0; idx < 15; idx++) {
++				if (idx < 5) { /*@bit0~4*/
++					id0 = 0;
++					id1 = (u8)(idx + 1);
++				} else if (idx < 9) { /*@bit5~8*/
++					id0 = 1;
++					id1 = (u8)(idx - 3);
++				} else if (idx < 12) { /*@bit9~11*/
++					id0 = 2;
++					id1 = (u8)(idx - 6);
++				} else if (idx < 14) { /*@bit12~13*/
++					id0 = 3;
++					id1 = (u8)(idx - 8);
++				} else { /*@bit14*/
++					id0 = 4;
++					id1 = (u8)(idx - 9);
++				}
++				if (bitmap & BIT(idx)) {
++					/*Pair 1*/
++					gid = (idx << 1) + 1;
++					gid_valid[id0] |= (BIT(gid));
++					gid_valid[id1] |= (BIT(gid));
++					/*Pair 2*/
++					gid += 1;
++					gid_valid[id0] |= (BIT(gid));
++					gid_valid[id1] |= (BIT(gid));
++				} else {
++					/*Pair 1*/
++					gid = (idx << 1) + 1;
++					gid_valid[id0] &= ~(BIT(gid));
++					gid_valid[id1] &= ~(BIT(gid));
++					/*Pair 2*/
++					gid += 1;
++					gid_valid[id0] &= ~(BIT(gid));
++					gid_valid[id1] &= ~(BIT(gid));
++				}
++			}
++
++			for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
++				beamform_entry = &beamforming_info->beamformee_entry[i];
++				if (beamform_entry->is_mu_sta && beamform_entry->mu_reg_index < 6) {
++					value32 = gid_valid[beamform_entry->mu_reg_index];
++					for (idx = 0; idx < 4; idx++) {
++						beamform_entry->gid_valid[idx] = (u8)(value32 & 0xFF);
++						value32 = (value32 >> 8);
++					}
++				}
++			}
++
++			for (idx = 0; idx < 6; idx++) {
++				beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));
++				beamforming_info->reg_mu_tx_ctrl |= ((idx << 8) & (BIT(8) | BIT(9) | BIT(10)));
++				odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
++				odm_set_mac_reg(dm, R_0x14c4, MASKDWORD, gid_valid[idx]); /*set MU STA gid valid table*/
++			}
++
++			/*@Enable TxMU PPDU*/
++			if (beamforming_info->dbg_disable_mu_tx == false)
++				beamforming_info->reg_mu_tx_ctrl |= BIT(7);
++			else
++				beamforming_info->reg_mu_tx_ctrl &= ~BIT(7);
++			odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
++		}
++	}
++}
++
++/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/
++void hal_txbf_8822b_config_gtab(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL;
++	u32 gid_valid = 0, user_position_l = 0, user_position_h = 0, i;
++
++	if (beamforming_info->mu_ap_index < BEAMFORMER_ENTRY_NUM)
++		beamformer_entry = &beamforming_info->beamformer_entry[beamforming_info->mu_ap_index];
++	else
++		return;
++
++	PHYDM_DBG(dm, DBG_TXBF, "%s==>\n", __func__);
++
++	/*@For GID 0~31*/
++	for (i = 0; i < 4; i++)
++		gid_valid |= (beamformer_entry->gid_valid[i] << (i << 3));
++	for (i = 0; i < 8; i++) {
++		if (i < 4)
++			user_position_l |= (beamformer_entry->user_position[i] << (i << 3));
++		else
++			user_position_h |= (beamformer_entry->user_position[i] << ((i - 4) << 3));
++	}
++	/*select MU STA0 table*/
++	beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));
++	odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
++	odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, gid_valid);
++	odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l);
++	odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h);
++
++	PHYDM_DBG(dm, DBG_TXBF,
++		  "%s: STA0: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n",
++		  __func__, gid_valid, user_position_l, user_position_h);
++
++	gid_valid = 0;
++	user_position_l = 0;
++	user_position_h = 0;
++
++	/*@For GID 32~64*/
++	for (i = 4; i < 8; i++)
++		gid_valid |= (beamformer_entry->gid_valid[i] << ((i - 4) << 3));
++	for (i = 8; i < 16; i++) {
++		if (i < 4)
++			user_position_l |= (beamformer_entry->user_position[i] << ((i - 8) << 3));
++		else
++			user_position_h |= (beamformer_entry->user_position[i] << ((i - 12) << 3));
++	}
++	/*select MU STA1 table*/
++	beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));
++	beamforming_info->reg_mu_tx_ctrl |= BIT(8);
++	odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
++	odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, gid_valid);
++	odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l);
++	odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h);
++
++	PHYDM_DBG(dm, DBG_TXBF,
++		  "%s: STA1: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n",
++		  __func__, gid_valid, user_position_l, user_position_h);
++
++	/* Set validity of MU STA0 and MU STA1*/
++	beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0;
++	beamforming_info->reg_mu_tx_ctrl |= 0x3; /* STA0, STA1*/
++	odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
++}
++
++#if 0
++/*This function translate the bitmap to GTAB*/
++void
++haltxbf8822b_gtab_translation(
++	struct dm_struct			*dm
++)
++{
++	u8 idx, gid;
++	u8 id1, id0;
++	u32 gid_valid[6] = {0};
++	u32 user_position_lsb[6] = {0};
++	u32 user_position_msb[6] = {0};
++
++	for (idx = 0; idx < 15; idx++) {
++		if (idx < 5) {/*@bit0~4*/
++			id0 = 0;
++			id1 = (u8)(idx + 1);
++		} else if (idx < 9) { /*@bit5~8*/
++			id0 = 1;
++			id1 = (u8)(idx - 3);
++		} else if (idx < 12) { /*@bit9~11*/
++			id0 = 2;
++			id1 = (u8)(idx - 6);
++		} else if (idx < 14) { /*@bit12~13*/
++			id0 = 3;
++			id1 = (u8)(idx - 8);
++		} else { /*@bit14*/
++			id0 = 4;
++			id1 = (u8)(idx - 9);
++		}
++
++		/*Pair 1*/
++		gid = (idx << 1) + 1;
++		gid_valid[id0] |= (1 << gid);
++		gid_valid[id1] |= (1 << gid);
++		if (gid < 16) {
++			/*user_position_lsb[id0] |= (0 << (gid << 1));*/
++			user_position_lsb[id1] |= (1 << (gid << 1));
++		} else {
++			/*user_position_msb[id0] |= (0 << ((gid - 16) << 1));*/
++			user_position_msb[id1] |= (1 << ((gid - 16) << 1));
++		}
++
++		/*Pair 2*/
++		gid += 1;
++		gid_valid[id0] |= (1 << gid);
++		gid_valid[id1] |= (1 << gid);
++		if (gid < 16) {
++			user_position_lsb[id0] |= (1 << (gid << 1));
++			/*user_position_lsb[id1] |= (0 << (gid << 1));*/
++		} else {
++			user_position_msb[id0] |= (1 << ((gid - 16) << 1));
++			/*user_position_msb[id1] |= (0 << ((gid - 16) << 1));*/
++		}
++	}
++
++
++	for (idx = 0; idx < 6; idx++) {
++		/*@dbg_print("gid_valid[%d] = 0x%x\n", idx, gid_valid[idx]);
++		dbg_print("user_position[%d] = 0x%x   %x\n", idx, user_position_msb[idx], user_position_lsb[idx]);*/
++	}
++}
++#endif
++
++void hal_txbf_8822b_fw_txbf(
++	void *dm_void,
++	u8 idx)
++{
++#if 0
++	struct _RT_BEAMFORMING_INFO	*beam_info = GET_BEAMFORM_INFO(adapter);
++	struct _RT_BEAMFORMEE_ENTRY	*p_beam_entry = beam_info->beamformee_entry + idx;
++
++	if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
++		hal_txbf_8822b_download_ndpa(adapter, idx);
++
++	hal_txbf_8822b_fw_txbf_cmd(adapter);
++#endif
++}
++
++#endif
++
++#if (defined(CONFIG_BB_TXBF_API))
++/*this function is only used for BFer*/
++void phydm_8822btxbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i;
++
++	if (dm->rf_type == RF_1T1R)
++		return;
++
++	if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
++		for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), 0x1); /*RF mode table write enable*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3); /*Select RX mode*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff, 0x00036); /*Set Table data*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff, 0x5AFCE); /*Set Table data*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), 0x0); /*RF mode table write disable*/
++		}
++	}
++
++	odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(30), 1); /*@if Nsts > Nc, don't apply V matrix*/
++
++	if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
++		/*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
++		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/
++		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); /*@ignore user since 8822B only 2Tx*/
++
++		/*Nsts = 2	AB*/
++		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433);
++		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
++
++	} else {
++		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x0); /*@enable BB TxBF ant mapping register*/
++		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 0); /*@ignore user since 8822B only 2Tx*/
++
++		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*@1SS by path-A*/
++		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*@2SS by path-A,B*/
++	}
++}
++
++/*this function is for BFer bug workaround*/
++void phydm_8822b_sutxbfer_workaroud(void *dm_void, boolean enable_su_bfer,
++				    u8 nc, u8 nr, u8 ng, u8 CB, u8 BW,
++				    boolean is_vht)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (enable_su_bfer) {
++		odm_set_bb_reg(dm, R_0x19f8, BIT(22) | BIT(21) | BIT(20), 0x1);
++		odm_set_bb_reg(dm, R_0x19f8, BIT(25) | BIT(24) | BIT(23), 0x0);
++		odm_set_bb_reg(dm, R_0x19f8, BIT(16), 0x1);
++
++		if (is_vht)
++			odm_set_bb_reg(dm, R_0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x1f);
++		else
++			odm_set_bb_reg(dm, R_0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x22);
++
++		odm_set_bb_reg(dm, R_0x19f0, BIT(7) | BIT(6), nc);
++		odm_set_bb_reg(dm, R_0x19f0, BIT(9) | BIT(8), nr);
++		odm_set_bb_reg(dm, R_0x19f0, BIT(11) | BIT(10), ng);
++		odm_set_bb_reg(dm, R_0x19f0, BIT(13) | BIT(12), CB);
++
++		odm_set_bb_reg(dm, R_0xb58, BIT(3) | BIT(2), BW);
++		odm_set_bb_reg(dm, R_0xb58, BIT(7) | BIT(6) | BIT(5) | BIT(4), 0x0);
++		odm_set_bb_reg(dm, R_0xb58, BIT(9) | BIT(8), BW);
++		odm_set_bb_reg(dm, R_0xb58, BIT(13) | BIT(12) | BIT(11) | BIT(10), 0x0);
++	} else {
++		odm_set_bb_reg(dm, R_0x19f8, BIT(16), 0x0);
++	}
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] enable_su_bfer = %d, is_vht = %d\n",
++		  __func__, enable_su_bfer, is_vht);
++	PHYDM_DBG(dm, DBG_TXBF,
++		  "[%s] nc = %d, nr = %d, ng = %d, CB = %d, BW = %d\n",
++		  __func__, nc, nr, ng, CB, BW);
++}
++#endif
++#endif /* @(RTL8822B_SUPPORT == 1)*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8822b.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8822b.h
+new file mode 100644
+index 000000000..552fba2a7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbf8822b.h
+@@ -0,0 +1,78 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++#ifndef __HAL_TXBF_8822B_H__
++#define __HAL_TXBF_8822B_H__
++
++#if (RTL8822B_SUPPORT == 1)
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++
++void hal_txbf_8822b_enter(
++	void *dm_void,
++	u8 idx);
++
++void hal_txbf_8822b_leave(
++	void *dm_void,
++	u8 idx);
++
++void hal_txbf_8822b_status(
++	void *dm_void,
++	u8 beamform_idx);
++
++void hal_txbf_8822b_config_gtab(
++	void *dm_void);
++
++void hal_txbf_8822b_fw_txbf(
++	void *dm_void,
++	u8 idx);
++#else
++#define hal_txbf_8822b_enter(dm_void, idx)
++#define hal_txbf_8822b_leave(dm_void, idx)
++#define hal_txbf_8822b_status(dm_void, idx)
++#define hal_txbf_8822b_fw_txbf(dm_void, idx)
++#define hal_txbf_8822b_config_gtab(dm_void)
++
++#endif
++
++#if (defined(CONFIG_BB_TXBF_API))
++void phydm_8822btxbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt);
++
++void phydm_8822b_sutxbfer_workaroud(void *dm_void, boolean enable_su_bfer,
++				    u8 nc, u8 nr, u8 ng, u8 CB, u8 BW,
++				    boolean is_vht);
++
++#else
++#define phydm_8822btxbf_rfmode(dm_void, su_bfee_cnt, mu_bfee_cnt)
++#define phydm_8822b_sutxbfer_workaroud(dm_void, enable_su_bfer, nc, nr, ng, CB, BW, is_vht)
++#endif
++
++#else
++#define hal_txbf_8822b_enter(dm_void, idx)
++#define hal_txbf_8822b_leave(dm_void, idx)
++#define hal_txbf_8822b_status(dm_void, idx)
++#define hal_txbf_8822b_fw_txbf(dm_void, idx)
++#define hal_txbf_8822b_config_gtab(dm_void)
++
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbfinterface.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbfinterface.c
+new file mode 100644
+index 000000000..c125fecad
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbfinterface.c
+@@ -0,0 +1,1484 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*************************************************************
++ * Description:
++ *
++ * This file is for TXBF interface mechanism
++ *
++ ************************************************************/
++#include "mp_precomp.h"
++#include "../phydm_precomp.h"
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void beamforming_gid_paid(
++	void *adapter,
++	PRT_TCB tcb)
++{
++	u8 RA[6] = {0};
++	u8 *p_header = GET_FRAME_OF_FIRST_FRAG(adapter, tcb);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
++
++	if (((PADAPTER)adapter)->HardwareType < HARDWARE_TYPE_RTL8192EE)
++		return;
++	else if (IS_WIRELESS_MODE_N((PADAPTER)adapter) == false)
++		return;
++
++#if (SUPPORT_MU_BF == 1)
++	if (tcb->tx_bf_pkt_type == RT_BF_PKT_TYPE_BROADCAST_NDPA) { /* @MU NDPA */
++#else
++	if (0) {
++#endif
++		/* @Fill G_ID and P_AID */
++		tcb->G_ID = 63;
++		if (beam_info->first_mu_bfee_index < BEAMFORMEE_ENTRY_NUM) {
++			tcb->P_AID = beam_info->beamformee_entry[beam_info->first_mu_bfee_index].p_aid;
++			RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, tcb->G_ID, tcb->P_AID));
++		}
++	} else {
++		GET_80211_HDR_ADDRESS1(p_header, &RA);
++
++		/* VHT SU PPDU carrying one or more group addressed MPDUs or */
++		/* Transmitting a VHT NDP intended for multiple recipients */
++		if (MacAddr_isBcst(RA) || MacAddr_isMulticast(RA) || tcb->macId == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) {
++			tcb->G_ID = 63;
++			tcb->P_AID = 0;
++		} else if (ACTING_AS_AP(adapter)) {
++			u16 AID = (u16)(MacIdGetOwnerAssociatedClientAID(adapter, tcb->macId) & 0x1ff); /*@AID[0:8]*/
++
++			/*RT_DISP(FBEAM, FBEAM_FUN, ("@%s  tcb->mac_id=0x%X, AID=0x%X\n", __func__, tcb->mac_id, AID));*/
++			tcb->G_ID = 63;
++
++			if (AID == 0) /*@A PPDU sent by an AP to a non associated STA*/
++				tcb->P_AID = 0;
++			else { /*Sent by an AP and addressed to a STA associated with that AP*/
++				u16 BSSID = 0;
++				GET_80211_HDR_ADDRESS2(p_header, &RA);
++				BSSID = ((RA[5] & 0xf0) >> 4) ^ (RA[5] & 0xf); /*@BSSID[44:47] xor BSSID[40:43]*/
++				tcb->P_AID = (AID + BSSID * 32) & 0x1ff; /*@(dec(A) + dec(B)*32) mod 512*/
++			}
++		} else if (ACTING_AS_IBSS(((PADAPTER)adapter))) {
++			tcb->G_ID = 63;
++			/*P_AID for infrasturcture mode; MACID for ad-hoc mode. */
++			tcb->P_AID = tcb->macId;
++		} else if (MgntLinkStatusQuery(adapter)) { /*@Addressed to AP*/
++			tcb->G_ID = 0;
++			GET_80211_HDR_ADDRESS1(p_header, &RA);
++			tcb->P_AID = RA[5]; /*RA[39:47]*/
++			tcb->P_AID = (tcb->P_AID << 1) | (RA[4] >> 7);
++		} else {
++			tcb->G_ID = 63;
++			tcb->P_AID = 0;
++		}
++		/*RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, tcb->G_ID, tcb->P_AID));*/
++	}
++}
++
++enum rt_status
++beamforming_get_report_frame(
++	void *adapter,
++	PRT_RFD rfd,
++	POCTET_STRING p_pdu_os)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;
++	u8 *p_mimo_ctrl_field, p_csi_matrix;
++	u8 idx, nc, nr, CH_W;
++	u16 csi_matrix_len = 0;
++
++	ACT_PKT_TYPE pkt_type = ACT_PKT_TYPE_UNKNOWN;
++
++	/* @Memory comparison to see if CSI report is the same with previous one */
++	beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, Frame_Addr2(*p_pdu_os), &idx);
++
++	if (beamform_entry == NULL) {
++		PHYDM_DBG(dm, DBG_TXBF, "%s: Cannot find entry by addr\n",
++			  __func__);
++		return RT_STATUS_FAILURE;
++	}
++
++	pkt_type = PacketGetActionFrameType(p_pdu_os);
++
++	/* @-@ Modified by David */
++	if (pkt_type == ACT_PKT_VHT_COMPRESSED_BEAMFORMING) {
++		p_mimo_ctrl_field = p_pdu_os->Octet + 26;
++		nc = ((*p_mimo_ctrl_field) & 0x7) + 1;
++		nr = (((*p_mimo_ctrl_field) & 0x38) >> 3) + 1;
++		CH_W = (((*p_mimo_ctrl_field) & 0xC0) >> 6);
++		/*p_csi_matrix = p_mimo_ctrl_field + 3 + nc;*/ /* 24+(1+1+3)+2  MAC header+(Category+ActionCode+MIMOControlField) +SNR(nc=2) */
++		csi_matrix_len = p_pdu_os->Length - 26 - 3 - nc;
++	} else if (pkt_type == ACT_PKT_HT_COMPRESSED_BEAMFORMING) {
++		p_mimo_ctrl_field = p_pdu_os->Octet + 26;
++		nc = ((*p_mimo_ctrl_field) & 0x3) + 1;
++		nr = (((*p_mimo_ctrl_field) & 0xC) >> 2) + 1;
++		CH_W = (((*p_mimo_ctrl_field) & 0x10) >> 4);
++		/*p_csi_matrix = p_mimo_ctrl_field + 6 + nr;*/ /* 24+(1+1+6)+2  MAC header+(Category+ActionCode+MIMOControlField) +SNR(nc=2) */
++		csi_matrix_len = p_pdu_os->Length - 26 - 6 - nr;
++	} else
++		return RT_STATUS_SUCCESS;
++
++	PHYDM_DBG(dm, DBG_TXBF,
++		  "[%s] idx=%d, pkt type=%d, nc=%d, nr=%d, CH_W=%d\n", __func__,
++		  idx, pkt_type, nc, nr, CH_W);
++
++	return RT_STATUS_SUCCESS;
++}
++
++void construct_ht_ndpa_packet(
++	// 2017/11 MH PHYDM compile. But why need to use windows maco?
++	// For all linux code, it should be useless?
++	//void				*adapter = dm->adapter;
++	ADAPTER * adapter,
++	//void		*adapter,
++	u8 *RA,
++	u8 *buffer,
++	u32 *p_length,
++	enum channel_width BW)
++{
++	u16 duration = 0;
++	PMGNT_INFO mgnt_info = &(((PADAPTER)adapter)->MgntInfo);
++	//PMGNT_INFO				mgnt_info = &((MGNT_INFO)(((PADAPTER)adapter)->MgntInfo));
++	OCTET_STRING p_ndpa_frame, action_content;
++	u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c};
++
++	PlatformZeroMemory(buffer, 32);
++
++	SET_80211_HDR_FRAME_CONTROL(buffer, 0);
++
++	SET_80211_HDR_ORDER(buffer, 1);
++	SET_80211_HDR_TYPE_AND_SUBTYPE(buffer, Type_Action_No_Ack);
++
++	SET_80211_HDR_ADDRESS1(buffer, RA);
++	SET_80211_HDR_ADDRESS2(buffer, ((PADAPTER)adapter)->CurrentAddress);
++	SET_80211_HDR_ADDRESS3(buffer, ((PMGNT_INFO)mgnt_info)->Bssid);
++
++	duration = 2 * a_SifsTime + 40;
++
++	if (BW == CHANNEL_WIDTH_40)
++		duration += 87;
++	else
++		duration += 180;
++
++	SET_80211_HDR_DURATION(buffer, duration);
++
++	/* @HT control field */
++	SET_HT_CTRL_CSI_STEERING(buffer + sMacHdrLng, 3);
++	SET_HT_CTRL_NDP_ANNOUNCEMENT(buffer + sMacHdrLng, 1);
++
++	FillOctetString(p_ndpa_frame, buffer, sMacHdrLng + sHTCLng);
++
++	FillOctetString(action_content, action_hdr, 4);
++	PacketAppendData(&p_ndpa_frame, action_content);
++
++	*p_length = 32;
++}
++
++boolean
++send_fw_ht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	enum channel_width BW)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	void *adapter = dm->adapter;
++	PRT_TCB tcb;
++	PRT_TX_LOCAL_BUFFER p_buf;
++	boolean ret = true;
++	u32 buf_len;
++	u8 *buf_addr;
++	u8 desc_len = 0, idx = 0, ndp_tx_rate;
++	void *p_def_adapter = GetDefaultAdapter(((PADAPTER)adapter));
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	if (beamform_entry == NULL)
++		return false;
++
++	ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
++		  ndp_tx_rate);
++	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
++
++	if (MgntGetFWBuffer(p_def_adapter, &tcb, &p_buf)) {
++#if (DEV_BUS_TYPE != RT_PCI_INTERFACE)
++		desc_len = ((PADAPTER)adapter)->HWDescHeadLength - hal_data->USBALLDummyLength;
++#endif
++		buf_addr = p_buf->Buffer.VirtualAddress + desc_len;
++
++		construct_ht_ndpa_packet(
++			adapter,
++			RA,
++			buf_addr,
++			&buf_len,
++			BW);
++
++		tcb->PacketLength = buf_len + desc_len;
++
++		tcb->bTxEnableSwCalcDur = true;
++
++		tcb->BWOfPacket = BW;
++
++		if (ACTING_AS_IBSS(((PADAPTER)adapter)) || ACTING_AS_AP(((PADAPTER)adapter)))
++			tcb->G_ID = 63;
++
++		tcb->P_AID = beamform_entry->p_aid;
++		tcb->DataRate = ndp_tx_rate; /*rate of NDP decide by nr*/
++
++		((PADAPTER)adapter)->HalFunc.CmdSendPacketHandler(((PADAPTER)adapter), tcb, p_buf, tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false);
++	} else
++		ret = false;
++
++	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
++
++	if (ret)
++		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
++
++	return ret;
++}
++
++boolean
++send_sw_ht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	enum channel_width BW)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	void *adapter = dm->adapter;
++	PRT_TCB tcb;
++	PRT_TX_LOCAL_BUFFER p_buf;
++	boolean ret = true;
++	u8 idx = 0, ndp_tx_rate = 0;
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
++		  ndp_tx_rate);
++
++	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
++
++	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
++		construct_ht_ndpa_packet(
++			adapter,
++			RA,
++			p_buf->Buffer.VirtualAddress,
++			&tcb->PacketLength,
++			BW);
++
++		tcb->bTxEnableSwCalcDur = true;
++
++		tcb->BWOfPacket = BW;
++
++		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate);
++	} else
++		ret = false;
++
++	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
++
++	if (ret)
++		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
++
++	return ret;
++}
++
++void construct_vht_ndpa_packet(
++	struct dm_struct *dm,
++	u8 *RA,
++	u16 AID,
++	u8 *buffer,
++	u32 *p_length,
++	enum channel_width BW)
++{
++	u16 duration = 0;
++	u8 sequence = 0;
++	u8 *p_ndpa_frame = buffer;
++	struct _RT_NDPA_STA_INFO sta_info;
++	// 2017/11 MH PHYDM compile. But why need to use windows maco?
++	// For all linux code, it should be useless?
++	//void				*adapter = dm->adapter;
++	ADAPTER * adapter = (PADAPTER)(dm->adapter);
++	u8 idx = 0;
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
++	/* @Frame control. */
++	SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0);
++	SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA);
++
++	SET_80211_HDR_ADDRESS1(p_ndpa_frame, RA);
++	SET_80211_HDR_ADDRESS2(p_ndpa_frame, beamform_entry->my_mac_addr);
++
++	// 2017/11 MH PHYDM compile. But why need to use windows maco?
++	// For all linux code, it should be useless?
++	duration = 2 * a_SifsTime + 44;
++
++	if (BW == CHANNEL_WIDTH_80)
++		duration += 40;
++	else if (BW == CHANNEL_WIDTH_40)
++		duration += 87;
++	else
++		duration += 180;
++
++	SET_80211_HDR_DURATION(p_ndpa_frame, duration);
++
++	sequence = *(dm->sounding_seq) << 2;
++	odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1);
++
++	if (phydm_acting_determine(dm, phydm_acting_as_ibss) || phydm_acting_determine(dm, phydm_acting_as_ap) == false)
++		AID = 0;
++
++	sta_info.aid = AID;
++	sta_info.feedback_type = 0;
++	sta_info.nc_index = 0;
++
++	odm_move_memory(dm, p_ndpa_frame + 17, (u8 *)&sta_info, 2);
++
++	*p_length = 19;
++}
++
++boolean
++send_fw_vht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	u16 AID,
++	enum channel_width BW)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	void *adapter = dm->adapter;
++	PRT_TCB tcb;
++	PRT_TX_LOCAL_BUFFER p_buf;
++	boolean ret = true;
++	u32 buf_len;
++	u8 *buf_addr;
++	u8 desc_len = 0, idx = 0, ndp_tx_rate = 0;
++	void *p_def_adapter = GetDefaultAdapter(((PADAPTER)adapter));
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	if (beamform_entry == NULL)
++		return false;
++
++	ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
++		  ndp_tx_rate);
++
++	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
++
++	if (MgntGetFWBuffer(p_def_adapter, &tcb, &p_buf)) {
++#if (DEV_BUS_TYPE != RT_PCI_INTERFACE)
++		desc_len = ((PADAPTER)adapter)->HWDescHeadLength - hal_data->USBALLDummyLength;
++#endif
++		buf_addr = p_buf->Buffer.VirtualAddress + desc_len;
++
++		construct_vht_ndpa_packet(
++			dm,
++			RA,
++			AID,
++			buf_addr,
++			&buf_len,
++			BW);
++
++		tcb->PacketLength = buf_len + desc_len;
++
++		tcb->bTxEnableSwCalcDur = true;
++
++		tcb->BWOfPacket = BW;
++
++		if (phydm_acting_determine(dm, phydm_acting_as_ibss) || phydm_acting_determine(dm, phydm_acting_as_ap))
++			tcb->G_ID = 63;
++
++		tcb->P_AID = beamform_entry->p_aid;
++		tcb->DataRate = ndp_tx_rate; /*@decide by nr*/
++
++		((PADAPTER)adapter)->HalFunc.CmdSendPacketHandler(adapter, tcb, p_buf, tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false);
++	} else
++		ret = false;
++
++	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] End, ret=%d\n", __func__, ret);
++
++	if (ret)
++		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
++
++	return ret;
++}
++
++boolean
++send_sw_vht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	u16 AID,
++	enum channel_width BW)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	void *adapter = dm->adapter;
++	PRT_TCB tcb;
++	PRT_TX_LOCAL_BUFFER p_buf;
++	boolean ret = true;
++	u8 idx = 0, ndp_tx_rate = 0;
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
++
++	ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
++		  ndp_tx_rate);
++
++	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
++
++	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
++		construct_vht_ndpa_packet(
++			dm,
++			RA,
++			AID,
++			p_buf->Buffer.VirtualAddress,
++			&tcb->PacketLength,
++			BW);
++
++		tcb->bTxEnableSwCalcDur = true;
++		tcb->BWOfPacket = BW;
++
++		/*rate of NDP decide by nr*/
++		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate);
++	} else
++		ret = false;
++
++	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
++
++	if (ret)
++		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
++
++	return ret;
++}
++
++#ifdef SUPPORT_MU_BF
++#if (SUPPORT_MU_BF == 1)
++/*@
++ * Description: On VHT GID management frame by an MU beamformee.
++ *
++ * 2015.05.20. Created by tynli.
++ */
++enum rt_status
++beamforming_get_vht_gid_mgnt_frame(
++	void *adapter,
++	PRT_RFD rfd,
++	POCTET_STRING p_pdu_os)
++{
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++	struct dm_struct *dm = &hal_data->DM_OutSrc;
++	enum rt_status rt_status = RT_STATUS_SUCCESS;
++	u8 *p_buffer = NULL;
++	u8 *p_raddr = NULL;
++	u8 mem_status[8] = {0}, user_pos[16] = {0};
++	u8 idx;
++	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
++	struct _RT_BEAMFORMER_ENTRY *beamform_entry = &beam_info->beamformer_entry[beam_info->mu_ap_index];
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] On VHT GID mgnt frame!\n", __func__);
++
++	/* @Check length*/
++	if (p_pdu_os->length < (FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY + 16)) {
++		PHYDM_DBG(dm, DBG_TXBF, "%s: Invalid length (%d)\n", __func__,
++			  p_pdu_os->length);
++		return RT_STATUS_INVALID_LENGTH;
++	}
++
++	/* @Check RA*/
++	p_raddr = (u8 *)(p_pdu_os->Octet) + 4;
++	if (!eq_mac_addr(p_raddr, adapter->CurrentAddress)) {
++		PHYDM_DBG(dm, DBG_TXBF, "%s: Drop because of RA error.\n",
++			  __func__);
++		return RT_STATUS_PKT_DROP;
++	}
++
++	RT_DISP_DATA(FBEAM, FBEAM_DATA, "On VHT GID Mgnt Frame ==>:\n", p_pdu_os->Octet, p_pdu_os->length);
++
++	/*Parsing Membership status array*/
++	p_buffer = p_pdu_os->Octet + FRAME_OFFSET_VHT_GID_MGNT_MEMBERSHIP_STATUS_ARRAY;
++	for (idx = 0; idx < 8; idx++) {
++		mem_status[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx);
++		beamform_entry->gid_valid[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx);
++	}
++
++	RT_DISP_DATA(FBEAM, FBEAM_DATA, "mem_status: ", mem_status, 8);
++
++	/* Parsing User Position array*/
++	p_buffer = p_pdu_os->Octet + FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY;
++	for (idx = 0; idx < 16; idx++) {
++		user_pos[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx);
++		beamform_entry->user_position[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx);
++	}
++
++	RT_DISP_DATA(FBEAM, FBEAM_DATA, "user_pos: ", user_pos, 16);
++
++	/* @Group ID detail printed*/
++	{
++		u8 i, j;
++		u8 tmp_val;
++		u16 tmp_val2;
++
++		for (i = 0; i < 8; i++) {
++			tmp_val = mem_status[i];
++			tmp_val2 = ((user_pos[i * 2 + 1] << 8) & 0xFF00) + (user_pos[i * 2] & 0xFF);
++			for (j = 0; j < 8; j++) {
++				if ((tmp_val >> j) & BIT(0)) {
++					PHYDM_DBG(dm, DBG_TXBF, "Use Group ID (%d), User Position (%d)\n",
++						  (i * 8 + j), (tmp_val2 >> 2 * j) & 0x3);
++				}
++			}
++		}
++	}
++
++	/* @Indicate GID frame to IHV service. */
++	{
++		u8 indibuffer[24] = {0};
++		u8 indioffset = 0;
++
++		PlatformMoveMemory(indibuffer + indioffset, beamform_entry->gid_valid, 8);
++		indioffset += 8;
++		PlatformMoveMemory(indibuffer + indioffset, beamform_entry->user_position, 16);
++		indioffset += 16;
++
++		PlatformIndicateCustomStatus(
++			adapter,
++			RT_CUSTOM_EVENT_VHT_RECV_GID_MGNT_FRAME,
++			RT_CUSTOM_INDI_TARGET_IHV,
++			indibuffer,
++			indioffset);
++	}
++
++	/* @Config HW GID table */
++	hal_com_txbf_config_gtab(dm);
++
++	return rt_status;
++}
++
++/*@
++ * Description: Construct VHT Group ID (GID) management frame.
++ *
++ * 2015.05.20. Created by tynli.
++ */
++void construct_vht_gid_mgnt_frame(
++	struct dm_struct *dm,
++	u8 *RA,
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry,
++	u8 *buffer,
++	u32 *p_length
++
++	)
++{
++	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
++	void *adapter = beam_info->source_adapter;
++	OCTET_STRING os_ftm_frame, tmp;
++
++	FillOctetString(os_ftm_frame, buffer, 0);
++	*p_length = 0;
++
++	ConstructMaFrameHdr(
++		adapter,
++		RA,
++		ACT_CAT_VHT,
++		ACT_VHT_GROUPID_MANAGEMENT,
++		&os_ftm_frame);
++
++	/* @Membership status array*/
++	FillOctetString(tmp, beamform_entry->gid_valid, 8);
++	PacketAppendData(&os_ftm_frame, tmp);
++
++	/* User Position array*/
++	FillOctetString(tmp, beamform_entry->user_position, 16);
++	PacketAppendData(&os_ftm_frame, tmp);
++
++	*p_length = os_ftm_frame.length;
++
++	RT_DISP_DATA(FBEAM, FBEAM_DATA, "construct_vht_gid_mgnt_frame():\n", buffer, *p_length);
++}
++
++boolean
++send_sw_vht_gid_mgnt_frame(
++	void *dm_void,
++	u8 *RA,
++	u8 idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	PRT_TCB tcb;
++	PRT_TX_LOCAL_BUFFER p_buf;
++	boolean ret = true;
++	u8 data_rate = 0;
++	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = &beam_info->beamformee_entry[idx];
++	void *adapter = beam_info->source_adapter;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
++
++	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
++		construct_vht_gid_mgnt_frame(
++			dm,
++			RA,
++			beamform_entry,
++			p_buf->Buffer.VirtualAddress,
++			&tcb->PacketLength);
++
++		tcb->bw_of_packet = CHANNEL_WIDTH_20;
++		data_rate = MGN_6M;
++		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, data_rate);
++	} else
++		ret = false;
++
++	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
++
++	if (ret)
++		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
++
++	return ret;
++}
++
++/*@
++ * Description: Construct VHT beamforming report poll.
++ *
++ * 2015.05.20. Created by tynli.
++ */
++void construct_vht_bf_report_poll(
++	struct dm_struct *dm,
++	u8 *RA,
++	u8 *buffer,
++	u32 *p_length)
++{
++	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
++	void *adapter = beam_info->source_adapter;
++	u8 *p_bf_rpt_poll = buffer;
++
++	/* @Frame control*/
++	SET_80211_HDR_FRAME_CONTROL(p_bf_rpt_poll, 0);
++	SET_80211_HDR_TYPE_AND_SUBTYPE(p_bf_rpt_poll, Type_Beamforming_Report_Poll);
++
++	/* @duration*/
++	SET_80211_HDR_DURATION(p_bf_rpt_poll, 100);
++
++	/* RA*/
++	SET_VHT_BF_REPORT_POLL_RA(p_bf_rpt_poll, RA);
++
++	/* TA*/
++	SET_VHT_BF_REPORT_POLL_TA(p_bf_rpt_poll, adapter->CurrentAddress);
++
++	/* @Feedback Segment Retransmission Bitmap*/
++	SET_VHT_BF_REPORT_POLL_FEEDBACK_SEG_RETRAN_BITMAP(p_bf_rpt_poll, 0xFF);
++
++	*p_length = 17;
++
++	RT_DISP_DATA(FBEAM, FBEAM_DATA, "construct_vht_bf_report_poll():\n", buffer, *p_length);
++}
++
++boolean
++send_sw_vht_bf_report_poll(
++	void *dm_void,
++	u8 *RA,
++	boolean is_final_poll)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	PRT_TCB tcb;
++	PRT_TX_LOCAL_BUFFER p_buf;
++	boolean ret = true;
++	u8 idx = 0, data_rate = 0;
++	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
++	void *adapter = beam_info->source_adapter;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
++
++	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
++		construct_vht_bf_report_poll(
++			dm,
++			RA,
++			p_buf->Buffer.VirtualAddress,
++			&tcb->PacketLength);
++
++		tcb->bTxEnableSwCalcDur = true; /* @<tynli_note> need?*/
++		tcb->BWOfPacket = CHANNEL_WIDTH_20;
++
++		if (is_final_poll)
++			tcb->TxBFPktType = RT_BF_PKT_TYPE_FINAL_BF_REPORT_POLL;
++		else
++			tcb->TxBFPktType = RT_BF_PKT_TYPE_BF_REPORT_POLL;
++
++		data_rate = MGN_6M; /* @Legacy OFDM rate*/
++		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, data_rate);
++	} else
++		ret = false;
++
++	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
++
++	if (ret)
++		RT_DISP_DATA(FBEAM, FBEAM_DATA, "send_sw_vht_bf_report_poll:\n",
++		p_buf->Buffer.VirtualAddress, tcb->PacketLength);
++
++	return ret;
++}
++
++/*@
++ * Description: Construct VHT MU NDPA packet.
++ *	<Note> We should combine this function with construct_vht_ndpa_packet() in the future.
++ *
++ * 2015.05.21. Created by tynli.
++ */
++void construct_vht_mu_ndpa_packet(
++	struct dm_struct *dm,
++	enum channel_width BW,
++	u8 *buffer,
++	u32 *p_length)
++{
++	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
++	void *adapter = beam_info->source_adapter;
++	u16 duration = 0;
++	u8 sequence = 0;
++	u8 *p_ndpa_frame = buffer;
++	struct _RT_NDPA_STA_INFO sta_info;
++	u8 idx;
++	u8 dest_addr[6] = {0};
++	struct _RT_BEAMFORMEE_ENTRY *entry = NULL;
++
++	/* @Fill the first MU BFee entry (STA1) MAC addr to destination address then
++	     HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */
++	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
++		entry = &(beam_info->beamformee_entry[idx]);
++		if (entry->is_mu_sta) {
++			cp_mac_addr(dest_addr, entry->mac_addr);
++			break;
++		}
++	}
++	if (entry == NULL)
++		return;
++
++	/* @Frame control.*/
++	SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0);
++	SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA);
++
++	SET_80211_HDR_ADDRESS1(p_ndpa_frame, dest_addr);
++	SET_80211_HDR_ADDRESS2(p_ndpa_frame, entry->my_mac_addr);
++
++	/*@--------------------------------------------*/
++	/* @<Note> Need to modify "duration" to MU consideration. */
++	duration = 2 * a_SifsTime + 44;
++
++	if (BW == CHANNEL_WIDTH_80)
++		duration += 40;
++	else if (BW == CHANNEL_WIDTH_40)
++		duration += 87;
++	else
++		duration += 180;
++	/*@--------------------------------------------*/
++
++	SET_80211_HDR_DURATION(p_ndpa_frame, duration);
++
++	sequence = *(dm->sounding_seq) << 2;
++	odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1);
++
++	*p_length = 17;
++
++	/* @Construct STA info. for multiple STAs*/
++	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
++		entry = &(beam_info->beamformee_entry[idx]);
++		if (entry->is_mu_sta) {
++			sta_info.aid = entry->AID;
++			sta_info.feedback_type = 1; /* @1'b1: MU*/
++			sta_info.nc_index = 0;
++
++			PHYDM_DBG(dm, DBG_TXBF,
++				  "[%s] Get beamformee_entry idx(%d), AID =%d\n",
++				  __func__, idx, entry->AID);
++
++			odm_move_memory(dm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2);
++			*p_length += 2;
++		}
++	}
++}
++
++boolean
++send_sw_vht_mu_ndpa_packet(
++	void *dm_void,
++	enum channel_width BW)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	PRT_TCB tcb;
++	PRT_TX_LOCAL_BUFFER p_buf;
++	boolean ret = true;
++	u8 ndp_tx_rate = 0;
++	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
++	void *adapter = beam_info->source_adapter;
++
++	ndp_tx_rate = MGN_VHT2SS_MCS0;
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
++		  ndp_tx_rate);
++
++	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
++
++	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
++		construct_vht_mu_ndpa_packet(
++			dm,
++			BW,
++			p_buf->Buffer.VirtualAddress,
++			&tcb->PacketLength);
++
++		tcb->bTxEnableSwCalcDur = true;
++		tcb->BWOfPacket = BW;
++		tcb->TxBFPktType = RT_BF_PKT_TYPE_BROADCAST_NDPA;
++
++		/*rate of NDP decide by nr*/
++		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate);
++	} else
++		ret = false;
++
++	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
++
++	if (ret)
++		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
++
++	return ret;
++}
++
++void dbg_construct_vht_mundpa_packet(
++	struct dm_struct *dm,
++	enum channel_width BW,
++	u8 *buffer,
++	u32 *p_length)
++{
++	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
++	void *adapter = beam_info->source_adapter;
++	u16 duration = 0;
++	u8 sequence = 0;
++	u8 *p_ndpa_frame = buffer;
++	struct _RT_NDPA_STA_INFO sta_info;
++	u8 idx;
++	u8 dest_addr[6] = {0};
++	struct _RT_BEAMFORMEE_ENTRY *entry = NULL;
++
++	boolean is_STA1 = false;
++
++	/* @Fill the first MU BFee entry (STA1) MAC addr to destination address then
++	     HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */
++	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
++		entry = &(beam_info->beamformee_entry[idx]);
++		if (entry->is_mu_sta) {
++			if (is_STA1 == false) {
++				is_STA1 = true;
++				continue;
++			} else {
++				cp_mac_addr(dest_addr, entry->mac_addr);
++				break;
++			}
++		}
++	}
++
++	/* @Frame control.*/
++	SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0);
++	SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA);
++
++	SET_80211_HDR_ADDRESS1(p_ndpa_frame, dest_addr);
++	SET_80211_HDR_ADDRESS2(p_ndpa_frame, dm->CurrentAddress);
++
++	/*@--------------------------------------------*/
++	/* @<Note> Need to modify "duration" to MU consideration. */
++	duration = 2 * a_SifsTime + 44;
++
++	if (BW == CHANNEL_WIDTH_80)
++		duration += 40;
++	else if (BW == CHANNEL_WIDTH_40)
++		duration += 87;
++	else
++		duration += 180;
++	/*@--------------------------------------------*/
++
++	SET_80211_HDR_DURATION(p_ndpa_frame, duration);
++
++	sequence = *(dm->sounding_seq) << 2;
++	odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1);
++
++	*p_length = 17;
++
++	/*STA2's STA Info*/
++	sta_info.aid = entry->aid;
++	sta_info.feedback_type = 1; /* @1'b1: MU */
++	sta_info.nc_index = 0;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Get beamformee_entry idx(%d), AID =%d\n",
++		  __func__, idx, entry->aid);
++
++	odm_move_memory(dm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2);
++	*p_length += 2;
++}
++
++boolean
++dbg_send_sw_vht_mundpa_packet(
++	void *dm_void,
++	enum channel_width BW)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	PRT_TCB tcb;
++	PRT_TX_LOCAL_BUFFER p_buf;
++	boolean ret = true;
++	u8 ndp_tx_rate = 0;
++	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
++	void *adapter = beam_info->source_adapter;
++
++	ndp_tx_rate = MGN_VHT2SS_MCS0;
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
++		  ndp_tx_rate);
++
++	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
++
++	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
++		dbg_construct_vht_mundpa_packet(
++			dm,
++			BW,
++			p_buf->Buffer.VirtualAddress,
++			&tcb->PacketLength);
++
++		tcb->bTxEnableSwCalcDur = true;
++		tcb->BWOfPacket = BW;
++		tcb->TxBFPktType = RT_BF_PKT_TYPE_UNICAST_NDPA;
++
++		/*rate of NDP decide by nr*/
++		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate);
++	} else
++		ret = false;
++
++	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
++
++	if (ret)
++		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
++
++	return ret;
++}
++
++#endif /*@#if (SUPPORT_MU_BF == 1)*/
++#endif /*@#ifdef SUPPORT_MU_BF*/
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++
++u32 beamforming_get_report_frame(
++	void *dm_void,
++	union recv_frame *precv_frame)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u32 ret = _SUCCESS;
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;
++	u8 *pframe = precv_frame->u.hdr.rx_data;
++	u32 frame_len = precv_frame->u.hdr.len;
++	u8 *TA;
++	u8 idx, offset;
++
++	/*@Memory comparison to see if CSI report is the same with previous one*/
++	TA = get_addr2_ptr(pframe);
++	beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, TA, &idx);
++	if (beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
++		offset = 31; /*@24+(1+1+3)+2  MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/
++	else if (beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)
++		offset = 34; /*@24+(1+1+6)+2  MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/
++	else
++		return ret;
++
++	return ret;
++}
++
++boolean
++send_fw_ht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	enum channel_width BW)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ADAPTER *adapter = dm->adapter;
++	struct xmit_frame *pmgntframe;
++	struct pkt_attrib *pattrib;
++	struct rtw_ieee80211_hdr *pwlanhdr;
++	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c};
++	u8 *pframe;
++	u16 *fctrl;
++	u16 duration = 0;
++	u8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0;
++	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++
++	if (pmgntframe == NULL) {
++		PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n",
++			  __func__);
++		return false;
++	}
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(adapter, pattrib);
++
++	pattrib->qsel = QSLT_BEACON;
++	ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
++		  ndp_tx_rate);
++	pattrib->rate = ndp_tx_rate;
++	pattrib->bwmode = BW;
++	pattrib->order = 1;
++	pattrib->subtype = WIFI_ACTION_NOACK;
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &pwlanhdr->frame_ctl;
++	*(fctrl) = 0;
++
++	set_order_bit(pframe);
++	set_frame_sub_type(pframe, WIFI_ACTION_NOACK);
++
++	_rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++	if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
++		a_sifs_time = 10;
++	else
++		a_sifs_time = 16;
++
++	duration = 2 * a_sifs_time + 40;
++
++	if (BW == CHANNEL_WIDTH_40)
++		duration += 87;
++	else
++		duration += 180;
++
++	set_duration(pframe, duration);
++
++	/* @HT control field */
++	SET_HT_CTRL_CSI_STEERING(pframe + 24, 3);
++	SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1);
++
++	_rtw_memcpy(pframe + 28, action_hdr, 4);
++
++	pattrib->pktlen = 32;
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(adapter, pmgntframe);
++
++	return true;
++}
++
++boolean
++send_sw_ht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	enum channel_width BW)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ADAPTER *adapter = dm->adapter;
++	struct xmit_frame *pmgntframe;
++	struct pkt_attrib *pattrib;
++	struct rtw_ieee80211_hdr *pwlanhdr;
++	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c};
++	u8 *pframe;
++	u16 *fctrl;
++	u16 duration = 0;
++	u8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0;
++	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
++
++	ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++
++	if (pmgntframe == NULL) {
++		PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n",
++			  __func__);
++		return false;
++	}
++
++	/*update attribute*/
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(adapter, pattrib);
++	pattrib->qsel = QSLT_MGNT;
++	pattrib->rate = ndp_tx_rate;
++	pattrib->bwmode = BW;
++	pattrib->order = 1;
++	pattrib->subtype = WIFI_ACTION_NOACK;
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &pwlanhdr->frame_ctl;
++	*(fctrl) = 0;
++
++	set_order_bit(pframe);
++	set_frame_sub_type(pframe, WIFI_ACTION_NOACK);
++
++	_rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++	if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
++		a_sifs_time = 10;
++	else
++		a_sifs_time = 16;
++
++	duration = 2 * a_sifs_time + 40;
++
++	if (BW == CHANNEL_WIDTH_40)
++		duration += 87;
++	else
++		duration += 180;
++
++	set_duration(pframe, duration);
++
++	/*@HT control field*/
++	SET_HT_CTRL_CSI_STEERING(pframe + 24, 3);
++	SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1);
++
++	_rtw_memcpy(pframe + 28, action_hdr, 4);
++
++	pattrib->pktlen = 32;
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(adapter, pmgntframe);
++
++	return true;
++}
++
++boolean
++send_fw_vht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	u16 AID,
++	enum channel_width BW)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ADAPTER *adapter = dm->adapter;
++	struct xmit_frame *pmgntframe;
++	struct pkt_attrib *pattrib;
++	struct rtw_ieee80211_hdr *pwlanhdr;
++	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++	u8 *pframe;
++	u16 *fctrl;
++	u16 duration = 0;
++	u8 sequence = 0, a_sifs_time = 0, ndp_tx_rate = 0, idx = 0;
++	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
++	struct _RT_NDPA_STA_INFO sta_info;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++
++	if (pmgntframe == NULL) {
++		PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n",
++			  __func__);
++		return false;
++	}
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	_rtw_memcpy(pattrib->ra, RA, ETH_ALEN);
++	update_mgntframe_attrib(adapter, pattrib);
++
++	pattrib->qsel = QSLT_BEACON;
++	ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
++		  ndp_tx_rate);
++	pattrib->rate = ndp_tx_rate;
++	pattrib->bwmode = BW;
++	pattrib->subtype = WIFI_NDPA;
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &pwlanhdr->frame_ctl;
++	*(fctrl) = 0;
++
++	set_frame_sub_type(pframe, WIFI_NDPA);
++
++	_rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN);
++
++	if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
++		a_sifs_time = 16;
++	else
++		a_sifs_time = 10;
++
++	duration = 2 * a_sifs_time + 44;
++
++	if (BW == CHANNEL_WIDTH_80)
++		duration += 40;
++	else if (BW == CHANNEL_WIDTH_40)
++		duration += 87;
++	else
++		duration += 180;
++
++	set_duration(pframe, duration);
++
++	sequence = beam_info->sounding_sequence << 2;
++	if (beam_info->sounding_sequence >= 0x3f)
++		beam_info->sounding_sequence = 0;
++	else
++		beam_info->sounding_sequence++;
++
++	_rtw_memcpy(pframe + 16, &sequence, 1);
++
++	if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))
++		AID = 0;
++
++	sta_info.aid = AID;
++	sta_info.feedback_type = 0;
++	sta_info.nc_index = 0;
++
++	_rtw_memcpy(pframe + 17, (u8 *)&sta_info, 2);
++
++	pattrib->pktlen = 19;
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(adapter, pmgntframe);
++
++	return true;
++}
++
++boolean
++send_sw_vht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	u16 AID,
++	enum channel_width BW)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _ADAPTER *adapter = dm->adapter;
++	struct xmit_frame *pmgntframe;
++	struct pkt_attrib *pattrib;
++	struct rtw_ieee80211_hdr *pwlanhdr;
++	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
++	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++	struct _RT_NDPA_STA_INFO ndpa_sta_info;
++	u8 ndp_tx_rate = 0, sequence = 0, a_sifs_time = 0, idx = 0;
++	u8 *pframe;
++	u16 *fctrl;
++	u16 duration = 0;
++	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
++	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
++
++	ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
++		  ndp_tx_rate);
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++
++	if (pmgntframe == NULL) {
++		PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n",
++			  __func__);
++		return false;
++	}
++
++	/*update attribute*/
++	pattrib = &pmgntframe->attrib;
++	_rtw_memcpy(pattrib->ra, RA, ETH_ALEN);
++	update_mgntframe_attrib(adapter, pattrib);
++	pattrib->qsel = QSLT_MGNT;
++	pattrib->rate = ndp_tx_rate;
++	pattrib->bwmode = BW;
++	pattrib->subtype = WIFI_NDPA;
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &pwlanhdr->frame_ctl;
++	*(fctrl) = 0;
++
++	set_frame_sub_type(pframe, WIFI_NDPA);
++
++	_rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN);
++
++	if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
++		a_sifs_time = 16;
++	else
++		a_sifs_time = 10;
++
++	duration = 2 * a_sifs_time + 44;
++
++	if (BW == CHANNEL_WIDTH_80)
++		duration += 40;
++	else if (BW == CHANNEL_WIDTH_40)
++		duration += 87;
++	else
++		duration += 180;
++
++	set_duration(pframe, duration);
++
++	sequence = beam_info->sounding_sequence << 2;
++	if (beam_info->sounding_sequence >= 0x3f)
++		beam_info->sounding_sequence = 0;
++	else
++		beam_info->sounding_sequence++;
++
++	_rtw_memcpy(pframe + 16, &sequence, 1);
++	if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))
++		AID = 0;
++
++	ndpa_sta_info.aid = AID;
++	ndpa_sta_info.feedback_type = 0;
++	ndpa_sta_info.nc_index = 0;
++
++	_rtw_memcpy(pframe + 17, (u8 *)&ndpa_sta_info, 2);
++
++	pattrib->pktlen = 19;
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	dump_mgntframe(adapter, pmgntframe);
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] [%d]\n", __func__, __LINE__);
++
++	return true;
++}
++
++#endif
++
++void beamforming_get_ndpa_frame(
++	void *dm_void,
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	OCTET_STRING pdu_os
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	union recv_frame *precv_frame
++#endif
++	)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 *TA;
++	u8 idx, sequence;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	u8 *p_ndpa_frame = pdu_os.Octet;
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	u8 *p_ndpa_frame = precv_frame->u.hdr.rx_data;
++#endif
++	struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL; /*@Modified By Jeffery @2014-10-29*/
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	RT_DISP_DATA(FBEAM, FBEAM_DATA, "beamforming_get_ndpa_frame\n",
++	pdu_os.Octet, pdu_os.Length);
++	if (IsCtrlNDPA(p_ndpa_frame) == false)
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	if (get_frame_sub_type(p_ndpa_frame) != WIFI_NDPA)
++#endif
++		return;
++	else if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))) {
++		PHYDM_DBG(dm, DBG_TXBF, "[%s] not 8812 or 8821A, return\n",
++			  __func__);
++		return;
++	}
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	TA = Frame_Addr2(pdu_os);
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	TA = get_addr2_ptr(p_ndpa_frame);
++#endif
++	/*Remove signaling TA. */
++	TA[0] = TA[0] & 0xFE;
++
++	beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, TA, &idx); /* @Modified By Jeffery @2014-10-29 */
++
++	/*@Break options for Clock Reset*/
++	if (beamformer_entry == NULL)
++		return;
++	else if (!(beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU))
++		return;
++	/*@log_success: As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is NO LONGER needed !2015-04-10, Jeffery*/
++	/*@clock_reset_times: While BFer entry always doesn't receive our CSI, clock will reset again and again.So clock_reset_times is limited to 5 times.2015-04-13, Jeffery*/
++	else if ((beamformer_entry->log_success == 1) || (beamformer_entry->clock_reset_times == 5)) {
++		PHYDM_DBG(dm, DBG_TXBF,
++			  "[%s] log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, log_success=%d, clock_reset_times=%d, clock reset is no longer needed.\n",
++			  __func__, beamformer_entry->log_seq,
++			  beamformer_entry->pre_log_seq,
++			  beamformer_entry->log_retry_cnt,
++			  beamformer_entry->log_success,
++			  beamformer_entry->clock_reset_times);
++
++		return;
++	}
++
++	sequence = (p_ndpa_frame[16]) >> 2;
++
++	PHYDM_DBG(dm, DBG_TXBF,
++		  "[%s] Start, sequence=%d, log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, clock_reset_times=%d, log_success=%d\n",
++		  __func__, sequence, beamformer_entry->log_seq,
++		  beamformer_entry->pre_log_seq,
++		  beamformer_entry->log_retry_cnt,
++		  beamformer_entry->clock_reset_times,
++		  beamformer_entry->log_success);
++
++	if (beamformer_entry->log_seq != 0 && beamformer_entry->pre_log_seq != 0) {
++		/*Success condition*/
++		if (beamformer_entry->log_seq != sequence && beamformer_entry->pre_log_seq != beamformer_entry->log_seq) {
++			/* @break option for clcok reset, 2015-03-30, Jeffery */
++			beamformer_entry->log_retry_cnt = 0;
++			/*@As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is no longer needed.*/
++			/*That is, log_success is NOT needed to be reset to zero, 2015-04-13, Jeffery*/
++			beamformer_entry->log_success = 1;
++
++		} else { /*@Fail condition*/
++
++			if (beamformer_entry->log_retry_cnt == 5) {
++				beamformer_entry->clock_reset_times++;
++				beamformer_entry->log_retry_cnt = 0;
++
++				PHYDM_DBG(dm, DBG_TXBF,
++					  "[%s] Clock Reset!!! clock_reset_times=%d\n",
++					  __func__,
++					  beamformer_entry->clock_reset_times);
++				hal_com_txbf_set(dm, TXBF_SET_SOUNDING_CLK, NULL);
++
++			} else
++				beamformer_entry->log_retry_cnt++;
++		}
++	}
++
++	/*Update log_seq & pre_log_seq*/
++	beamformer_entry->pre_log_seq = beamformer_entry->log_seq;
++	beamformer_entry->log_seq = sequence;
++}
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbfinterface.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbfinterface.h
+new file mode 100644
+index 000000000..b97aa349e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbfinterface.h
+@@ -0,0 +1,167 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++#ifndef __HAL_TXBF_INTERFACE_H__
++#define __HAL_TXBF_INTERFACE_H__
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++
++#define a_SifsTime ((IS_WIRELESS_MODE_5G(adapter) || IS_WIRELESS_MODE_N_24G(adapter)) ? 16 : 10)
++
++void beamforming_gid_paid(
++	void *adapter,
++	PRT_TCB tcb);
++
++enum rt_status
++beamforming_get_report_frame(
++	void *adapter,
++	PRT_RFD rfd,
++	POCTET_STRING p_pdu_os);
++
++void beamforming_get_ndpa_frame(
++	void *dm_void,
++	OCTET_STRING pdu_os);
++
++boolean
++send_fw_ht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	enum channel_width BW);
++
++boolean
++send_fw_vht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	u16 AID,
++	enum channel_width BW);
++
++boolean
++send_sw_vht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	u16 AID,
++	enum channel_width BW);
++
++boolean
++send_sw_ht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	enum channel_width BW);
++
++#if (SUPPORT_MU_BF == 1)
++enum rt_status
++beamforming_get_vht_gid_mgnt_frame(
++	void *adapter,
++	PRT_RFD rfd,
++	POCTET_STRING p_pdu_os);
++
++boolean
++send_sw_vht_gid_mgnt_frame(
++	void *dm_void,
++	u8 *RA,
++	u8 idx);
++
++boolean
++send_sw_vht_bf_report_poll(
++	void *dm_void,
++	u8 *RA,
++	boolean is_final_poll);
++
++boolean
++send_sw_vht_mu_ndpa_packet(
++	void *dm_void,
++	enum channel_width BW);
++#else
++#define beamforming_get_vht_gid_mgnt_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE
++#define send_sw_vht_gid_mgnt_frame(dm_void, RA)
++#define send_sw_vht_bf_report_poll(dm_void, RA, is_final_poll)
++#define send_sw_vht_mu_ndpa_packet(dm_void, BW)
++#endif
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++
++u32 beamforming_get_report_frame(
++	void *dm_void,
++	union recv_frame *precv_frame);
++
++boolean
++send_fw_ht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	enum channel_width BW);
++
++boolean
++send_sw_ht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	enum channel_width BW);
++
++boolean
++send_fw_vht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	u16 AID,
++	enum channel_width BW);
++
++boolean
++send_sw_vht_ndpa_packet(
++	void *dm_void,
++	u8 *RA,
++	u16 AID,
++	enum channel_width BW);
++#endif
++
++void beamforming_get_ndpa_frame(
++	void *dm_void,
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	OCTET_STRING pdu_os
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++	union recv_frame *precv_frame
++#endif
++	);
++
++boolean
++dbg_send_sw_vht_mundpa_packet(
++	void *dm_void,
++	enum channel_width BW);
++
++#else
++#define beamforming_get_ndpa_frame(dm, _pdu_os)
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++#define beamforming_get_report_frame(adapter, precv_frame) RT_STATUS_FAILURE
++#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++#define beamforming_get_report_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE
++#define beamforming_get_vht_gid_mgnt_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE
++#endif
++#define send_fw_ht_ndpa_packet(dm_void, RA, BW)
++#define send_sw_ht_ndpa_packet(dm_void, RA, BW)
++#define send_fw_vht_ndpa_packet(dm_void, RA, AID, BW)
++#define send_sw_vht_ndpa_packet(dm_void, RA, AID, BW)
++#define send_sw_vht_gid_mgnt_frame(dm_void, RA, idx)
++#define send_sw_vht_bf_report_poll(dm_void, RA, is_final_poll)
++#define send_sw_vht_mu_ndpa_packet(dm_void, BW)
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbfjaguar.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbfjaguar.c
+new file mode 100644
+index 000000000..6f1892837
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbfjaguar.c
+@@ -0,0 +1,509 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*************************************************************
++ * Description:
++ *
++ * This file is for 8812/8821/8811 TXBF mechanism
++ *
++ ************************************************************/
++#include "mp_precomp.h"
++#include "../phydm_precomp.h"
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
++void hal_txbf_8812a_set_ndpa_rate(
++	void *dm_void,
++	u8 BW,
++	u8 rate)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8812A, (rate << 2 | BW));
++}
++
++void hal_txbf_jaguar_rf_mode(
++	void *dm_void,
++	struct _RT_BEAMFORMING_INFO *beam_info)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	if (dm->rf_type == RF_1T1R)
++		return;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] set TxIQGen\n", __func__);
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1); /*RF mode table write enable*/
++	odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1); /*RF mode table write enable*/
++
++	if (beam_info->beamformee_su_cnt > 0) {
++		/* Paath_A */
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in RX mode*/
++		/* Path_B */
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in RX mode*/
++	} else {
++		/* Paath_A */
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
++		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0xC26BF); /*@Disable TXIQGEN in RX mode*/
++		/* Path_B */
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
++		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0xC26BF); /*@Disable TXIQGEN in RX mode*/
++	}
++
++	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0); /*RF mode table write disable*/
++	odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0); /*RF mode table write disable*/
++
++	if (beam_info->beamformee_su_cnt > 0)
++		odm_set_bb_reg(dm, R_0x80c, MASKBYTE1, 0x33);
++	else
++		odm_set_bb_reg(dm, R_0x80c, MASKBYTE1, 0x11);
++}
++
++void hal_txbf_jaguar_download_ndpa(
++	void *dm_void,
++	u8 idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 u1b_tmp = 0, tmp_reg422 = 0, head_page;
++	u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
++	boolean is_send_beacon = false;
++	u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*@default reseved 1 page for the IC type which is undefined.*/
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
++	void *adapter = dm->adapter;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	*dm->is_fw_dw_rsvd_page_in_progress = true;
++#endif
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	/* if (idx == 0) head_page = 0xFE; */
++	/* else	head_page = 0xFE;*/
++	head_page = 0xFE;
++
++	phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy);
++
++	/*Set REG_CR bit 8. DMA beacon by SW.*/
++	u1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1);
++	odm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp | BIT(0)));
++
++	/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
++	tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2);
++	odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422 & (~BIT(6)));
++
++	if (tmp_reg422 & BIT(6)) {
++		PHYDM_DBG(dm, DBG_TXBF,
++			  "SetBeamformDownloadNDPA_8812(): There is an adapter is sending beacon.\n");
++		is_send_beacon = true;
++	}
++
++	/*TDECTRL[15:8] 0x209[7:0] = 0xF6	Beacon Head for TXDMA*/
++	odm_write_1byte(dm, REG_TDECTRL_8812A + 1, head_page);
++
++	do {
++		/*@Clear beacon valid check bit.*/
++		bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2);
++		odm_write_1byte(dm, REG_TDECTRL_8812A + 2, (bcn_valid_reg | BIT(0)));
++
++		/*@download NDPA rsvd page.*/
++		if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
++			beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->aid, p_beam_entry->sound_bw, BEACON_QUEUE);
++		else
++			beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
++
++		/*@check rsvd page download OK.*/
++		bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2);
++		count = 0;
++		while (!(bcn_valid_reg & BIT(0)) && count < 20) {
++			count++;
++			ODM_delay_ms(10);
++			bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2);
++		}
++		dl_bcn_count++;
++	} while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5);
++
++	if (!(bcn_valid_reg & BIT(0)))
++		PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n",
++			  __func__);
++
++	/*TDECTRL[15:8] 0x209[7:0] = 0xF6	Beacon Head for TXDMA*/
++	odm_write_1byte(dm, REG_TDECTRL_8812A + 1, tx_page_bndy);
++
++	/*To make sure that if there exists an adapter which would like to send beacon.*/
++	/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
++	/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
++	/*the beacon cannot be sent by HW.*/
++	/*@2010.06.23. Added by tynli.*/
++	if (is_send_beacon)
++		odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422);
++
++	/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
++	/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
++	u1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1);
++	odm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp & (~BIT(0))));
++
++	p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	*dm->is_fw_dw_rsvd_page_in_progress = false;
++#endif
++}
++
++void hal_txbf_jaguar_fw_txbf_cmd(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 idx, period0 = 0, period1 = 0;
++	u8 PageNum0 = 0xFF, PageNum1 = 0xFF;
++	u8 u1_tx_bf_parm[3] = {0};
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++
++	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
++		/*@Modified by David*/
++		if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
++			if (idx == 0) {
++				if (beam_info->beamformee_entry[idx].is_sound)
++					PageNum0 = 0xFE;
++				else
++					PageNum0 = 0xFF; /*stop sounding*/
++				period0 = (u8)(beam_info->beamformee_entry[idx].sound_period);
++			} else if (idx == 1) {
++				if (beam_info->beamformee_entry[idx].is_sound)
++					PageNum1 = 0xFE;
++				else
++					PageNum1 = 0xFF; /*stop sounding*/
++				period1 = (u8)(beam_info->beamformee_entry[idx].sound_period);
++			}
++		}
++	}
++
++	u1_tx_bf_parm[0] = PageNum0;
++	u1_tx_bf_parm[1] = PageNum1;
++	u1_tx_bf_parm[2] = (period1 << 4) | period0;
++	odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
++
++	PHYDM_DBG(dm, DBG_TXBF,
++		  "[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n",
++		  __func__, PageNum0, period0, PageNum1, period1);
++}
++
++void hal_txbf_jaguar_enter(
++	void *dm_void,
++	u8 bfer_bfee_idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i = 0;
++	u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
++	u8 bfee_idx = (bfer_bfee_idx & 0xF);
++	u32 csi_param;
++	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
++	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
++	u16 sta_id = 0;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s]Start!\n", __func__);
++
++	hal_txbf_jaguar_rf_mode(dm, beamforming_info);
++
++	if (dm->rf_type == RF_2T2R)
++		odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x00000000); /*nc =2*/
++	else
++		odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x01081008); /*nc =1*/
++
++	if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
++		beamformer_entry = beamforming_info->beamformer_entry[bfer_idx];
++
++		/*Sounding protocol control*/
++		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xCB);
++
++		/*@MAC address/Partial AID of Beamformer*/
++		if (bfer_idx == 0) {
++			for (i = 0; i < 6; i++)
++				odm_write_1byte(dm, (REG_BFMER0_INFO_8812A + i), beamformer_entry.mac_addr[i]);
++			/*@CSI report use legacy ofdm so don't need to fill P_AID. */
++			/*platform_efio_write_2byte(adapter, REG_BFMER0_INFO_8812A+6, beamform_entry.P_AID); */
++		} else {
++			for (i = 0; i < 6; i++)
++				odm_write_1byte(dm, (REG_BFMER1_INFO_8812A + i), beamformer_entry.mac_addr[i]);
++			/*@CSI report use legacy ofdm so don't need to fill P_AID.*/
++			/*platform_efio_write_2byte(adapter, REG_BFMER1_INFO_8812A+6, beamform_entry.P_AID);*/
++		}
++
++		/*@CSI report parameters of Beamformee*/
++		if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) {
++			if (dm->rf_type == RF_2T2R)
++				csi_param = 0x01090109;
++			else
++				csi_param = 0x01080108;
++		} else {
++			if (dm->rf_type == RF_2T2R)
++				csi_param = 0x03090309;
++			else
++				csi_param = 0x03080308;
++		}
++
++		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, csi_param);
++		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, csi_param);
++		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, csi_param);
++
++		/*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us,  MP chip)*/
++		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A + 3, 0x50);
++	}
++
++	if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
++		beamformee_entry = beamforming_info->beamformee_entry[bfee_idx];
++
++		if (phydm_acting_determine(dm, phydm_acting_as_ibss))
++			sta_id = beamformee_entry.mac_id;
++		else
++			sta_id = beamformee_entry.p_aid;
++
++		/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
++		if (bfee_idx == 0) {
++			odm_write_2byte(dm, REG_TXBF_CTRL_8812A, sta_id);
++			odm_write_1byte(dm, REG_TXBF_CTRL_8812A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8812A + 3) | BIT(4) | BIT(6) | BIT(7));
++		} else
++			odm_write_2byte(dm, REG_TXBF_CTRL_8812A + 2, sta_id | BIT(12) | BIT(14) | BIT(15));
++
++		/*@CSI report parameters of Beamformee*/
++		if (bfee_idx == 0) {
++			/*@Get BIT24 & BIT25*/
++			u8 tmp = odm_read_1byte(dm, REG_BFMEE_SEL_8812A + 3) & 0x3;
++
++			odm_write_1byte(dm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60);
++			odm_write_2byte(dm, REG_BFMEE_SEL_8812A, sta_id | BIT(9));
++		} else {
++			/*Set BIT25*/
++			odm_write_2byte(dm, REG_BFMEE_SEL_8812A + 2, sta_id | 0xE200);
++		}
++		phydm_beamforming_notify(dm);
++	}
++}
++
++void hal_txbf_jaguar_leave(
++	void *dm_void,
++	u8 idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
++	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
++
++	if (idx < BEAMFORMER_ENTRY_NUM) {
++		beamformer_entry = beamforming_info->beamformer_entry[idx];
++		beamformee_entry = beamforming_info->beamformee_entry[idx];
++	} else
++		return;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s]Start!, IDx = %d\n", __func__, idx);
++
++	/*@Clear P_AID of Beamformee*/
++	/*@Clear MAC address of Beamformer*/
++	/*@Clear Associated Bfmee Sel*/
++
++	if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
++		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xC8);
++		if (idx == 0) {
++			odm_write_4byte(dm, REG_BFMER0_INFO_8812A, 0);
++			odm_write_2byte(dm, REG_BFMER0_INFO_8812A + 4, 0);
++			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, 0);
++			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, 0);
++			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, 0);
++		} else {
++			odm_write_4byte(dm, REG_BFMER1_INFO_8812A, 0);
++			odm_write_2byte(dm, REG_BFMER1_INFO_8812A + 4, 0);
++			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, 0);
++			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, 0);
++			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, 0);
++		}
++	}
++
++	if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
++		hal_txbf_jaguar_rf_mode(dm, beamforming_info);
++		if (idx == 0) {
++			odm_write_2byte(dm, REG_TXBF_CTRL_8812A, 0x0);
++			odm_write_2byte(dm, REG_BFMEE_SEL_8812A, 0);
++		} else {
++			odm_write_2byte(dm, REG_TXBF_CTRL_8812A + 2, odm_read_2byte(dm, REG_TXBF_CTRL_8812A + 2) & 0xF000);
++			odm_write_2byte(dm, REG_BFMEE_SEL_8812A + 2, odm_read_2byte(dm, REG_BFMEE_SEL_8812A + 2) & 0x60);
++		}
++	}
++}
++
++void hal_txbf_jaguar_status(
++	void *dm_void,
++	u8 idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u16 beam_ctrl_val;
++	u32 beam_ctrl_reg;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx];
++
++	if (phydm_acting_determine(dm, phydm_acting_as_ibss))
++		beam_ctrl_val = beamform_entry.mac_id;
++	else
++		beam_ctrl_val = beamform_entry.p_aid;
++
++	if (idx == 0)
++		beam_ctrl_reg = REG_TXBF_CTRL_8812A;
++	else {
++		beam_ctrl_reg = REG_TXBF_CTRL_8812A + 2;
++		beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
++	}
++
++	if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beam_info->apply_v_matrix == true) {
++		if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
++			beam_ctrl_val |= BIT(9);
++		else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
++			beam_ctrl_val |= (BIT(9) | BIT(10));
++		else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80)
++			beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));
++	} else
++		beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] beam_ctrl_val = 0x%x!\n", __func__,
++		  beam_ctrl_val);
++
++	odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
++}
++
++void hal_txbf_jaguar_fw_txbf(
++	void *dm_void,
++	u8 idx)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++	struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
++		hal_txbf_jaguar_download_ndpa(dm, idx);
++
++	hal_txbf_jaguar_fw_txbf_cmd(dm);
++}
++
++void hal_txbf_jaguar_patch(
++	void *dm_void,
++	u8 operation)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	if (beam_info->beamform_cap == BEAMFORMING_CAP_NONE)
++		return;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	if (operation == SCAN_OPT_BACKUP_BAND0)
++		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xC8);
++	else if (operation == SCAN_OPT_RESTORE)
++		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xCB);
++#endif
++}
++
++void hal_txbf_jaguar_clk_8812a(
++	void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u16 u2btmp;
++	u8 count = 0, u1btmp;
++	void *adapter = dm->adapter;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
++
++	if (*dm->is_scan_in_process) {
++		PHYDM_DBG(dm, DBG_TXBF, "[%s] return by Scan\n", __func__);
++		return;
++	}
++#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++	/*Stop PCIe TxDMA*/
++	if (dm->support_interface == ODM_ITRF_PCIE)
++		odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE);
++#endif
++
++/*Stop Usb TxDMA*/
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++	RT_DISABLE_FUNC((PADAPTER)adapter, DF_TX_BIT);
++	PlatformReturnAllPendingTxPackets(adapter);
++#else
++	rtw_write_port_cancel(adapter);
++#endif
++
++	/*Wait TXFF empty*/
++	for (count = 0; count < 100; count++) {
++		u2btmp = odm_read_2byte(dm, REG_TXPKT_EMPTY_8812A);
++		u2btmp = u2btmp & 0xfff;
++		if (u2btmp != 0xfff) {
++			ODM_delay_ms(10);
++			continue;
++		} else
++			break;
++	}
++
++	/*TX pause*/
++	odm_write_1byte(dm, REG_TXPAUSE_8812A, 0xFF);
++
++	/*Wait TX state Machine OK*/
++	for (count = 0; count < 100; count++) {
++		if (odm_read_4byte(dm, REG_SCH_TXCMD_8812A) != 0)
++			continue;
++		else
++			break;
++	}
++
++	/*Stop RX DMA path*/
++	u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A);
++	odm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT(2));
++
++	for (count = 0; count < 100; count++) {
++		u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A);
++		if (u1btmp & BIT(1))
++			break;
++		else
++			ODM_delay_ms(10);
++	}
++
++	/*@Disable clock*/
++	odm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xf0);
++	/*@Disable 320M*/
++	odm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0x8);
++	/*@Enable 320M*/
++	odm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0xa);
++	/*@Enable clock*/
++	odm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xfc);
++
++	/*Release Tx pause*/
++	odm_write_1byte(dm, REG_TXPAUSE_8812A, 0);
++
++	/*@Enable RX DMA path*/
++	u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A);
++	odm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT(2)));
++#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++	/*@Enable PCIe TxDMA*/
++	if (dm->support_interface == ODM_ITRF_PCIE)
++		odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0);
++#endif
++	/*Start Usb TxDMA*/
++	RT_ENABLE_FUNC((PADAPTER)adapter, DF_TX_BIT);
++}
++
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbfjaguar.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbfjaguar.h
+new file mode 100644
+index 000000000..2c9a623ba
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/haltxbfjaguar.h
+@@ -0,0 +1,78 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++#ifndef __HAL_TXBF_JAGUAR_H__
++#define __HAL_TXBF_JAGUAR_H__
++#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++
++void hal_txbf_8812a_set_ndpa_rate(
++	void *dm_void,
++	u8 BW,
++	u8 rate);
++
++void hal_txbf_jaguar_enter(
++	void *dm_void,
++	u8 idx);
++
++void hal_txbf_jaguar_leave(
++	void *dm_void,
++	u8 idx);
++
++void hal_txbf_jaguar_status(
++	void *dm_void,
++	u8 idx);
++
++void hal_txbf_jaguar_fw_txbf(
++	void *dm_void,
++	u8 idx);
++
++void hal_txbf_jaguar_patch(
++	void *dm_void,
++	u8 operation);
++
++void hal_txbf_jaguar_clk_8812a(
++	void *dm_void);
++#else
++
++#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate)
++#define hal_txbf_jaguar_enter(dm_void, idx)
++#define hal_txbf_jaguar_leave(dm_void, idx)
++#define hal_txbf_jaguar_status(dm_void, idx)
++#define hal_txbf_jaguar_fw_txbf(dm_void, idx)
++#define hal_txbf_jaguar_patch(dm_void, operation)
++#define hal_txbf_jaguar_clk_8812a(dm_void)
++#endif
++#else
++
++#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate)
++#define hal_txbf_jaguar_enter(dm_void, idx)
++#define hal_txbf_jaguar_leave(dm_void, idx)
++#define hal_txbf_jaguar_status(dm_void, idx)
++#define hal_txbf_jaguar_fw_txbf(dm_void, idx)
++#define hal_txbf_jaguar_patch(dm_void, operation)
++#define hal_txbf_jaguar_clk_8812a(dm_void)
++#endif
++
++#endif /*  @#ifndef __HAL_TXBF_JAGUAR_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/phydm_hal_txbf_api.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/phydm_hal_txbf_api.c
+new file mode 100644
+index 000000000..7cdd2d352
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/phydm_hal_txbf_api.c
+@@ -0,0 +1,748 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++#if (defined(CONFIG_BB_TXBF_API))
++#if (RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8812F_SUPPORT == 1 ||\
++	RTL8822C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
++/*@Add by YuChen for 8822B MU-MIMO API*/
++
++/*this function is only used for BFer*/
++u8 phydm_get_ndpa_rate(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 ndpa_rate = ODM_RATE6M;
++
++	if (dm->rssi_min >= 30) /*@link RSSI > 30%*/
++		ndpa_rate = ODM_RATE24M;
++	else if (dm->rssi_min <= 25)
++		ndpa_rate = ODM_RATE6M;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndpa_rate = 0x%x\n", __func__, ndpa_rate);
++
++	return ndpa_rate;
++}
++
++/*this function is only used for BFer*/
++u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput,
++				       u8 total_bfee_num, u8 *tx_rate)
++{
++	u8 idx = 0;
++	u8 snddecision = 0xff;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	for (idx = 0; idx < total_bfee_num; idx++) {
++		if (dm->support_ic_type & (ODM_RTL8814A)) {
++			if ((tx_rate[idx] >= ODM_RATEVHTSS3MCS7 &&
++			     tx_rate[idx] <= ODM_RATEVHTSS3MCS9))
++				snddecision = snddecision & ~(1 << idx);
++		} else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8822C |
++			   ODM_RTL8812 | ODM_RTL8192F)) {
++			if ((tx_rate[idx] >= ODM_RATEVHTSS2MCS7 &&
++			     tx_rate[idx] <= ODM_RATEVHTSS2MCS9))
++				snddecision = snddecision & ~(1 << idx);
++		} else if (dm->support_ic_type & (ODM_RTL8814B)) {
++			if ((tx_rate[idx] >= ODM_RATEVHTSS4MCS7 &&
++			     tx_rate[idx] <= ODM_RATEVHTSS4MCS9))
++				snddecision = snddecision & ~(1 << idx);
++		}
++	}
++
++	for (idx = 0; idx < total_bfee_num; idx++) {
++		if (throughput[idx] <= 10)
++			snddecision = snddecision & ~(1 << idx);
++	}
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] soundingdecision = 0x%x\n", __func__,
++		  snddecision);
++
++	return snddecision;
++}
++
++/*this function is only used for BFer*/
++u8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput)
++{
++	u8 snding_score = 0;
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	/*throughput unit is Mbps*/
++	if (throughput >= 500)
++		snding_score = 100;
++	else if (throughput >= 450)
++		snding_score = 90;
++	else if (throughput >= 400)
++		snding_score = 80;
++	else if (throughput >= 350)
++		snding_score = 70;
++	else if (throughput >= 300)
++		snding_score = 60;
++	else if (throughput >= 250)
++		snding_score = 50;
++	else if (throughput >= 200)
++		snding_score = 40;
++	else if (throughput >= 150)
++		snding_score = 30;
++	else if (throughput >= 100)
++		snding_score = 20;
++	else if (throughput >= 50)
++		snding_score = 10;
++	else
++		snding_score = 0;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[%s] snding_score = 0x%x\n", __func__,
++		  snding_score);
++
++	return snding_score;
++}
++
++#endif
++#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
++u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 nr_index = 0;
++	u8 ndp_tx_rate;
++/*@Find nr*/
++#if (RTL8814A_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814A)
++		nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num);
++	else
++#endif
++		nr_index = tx_bf_nr(1, bfer_str_num);
++
++	switch (nr_index) {
++	case 1:
++		ndp_tx_rate = ODM_MGN_MCS8;
++		break;
++
++	case 2:
++		ndp_tx_rate = ODM_MGN_MCS16;
++		break;
++
++	case 3:
++		ndp_tx_rate = ODM_MGN_MCS24;
++		break;
++
++	default:
++		ndp_tx_rate = ODM_MGN_MCS8;
++		break;
++	}
++
++	return ndp_tx_rate;
++}
++
++u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 nr_index = 0;
++	u8 ndp_tx_rate;
++/*@Find nr*/
++#if (RTL8814A_SUPPORT == 1)
++	if (dm->support_ic_type & ODM_RTL8814A)
++		nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num);
++	else
++#endif
++		nr_index = tx_bf_nr(1, bfer_str_num);
++
++	switch (nr_index) {
++	case 1:
++		ndp_tx_rate = ODM_MGN_VHT2SS_MCS0;
++		break;
++
++	case 2:
++		ndp_tx_rate = ODM_MGN_VHT3SS_MCS0;
++		break;
++
++	case 3:
++		ndp_tx_rate = ODM_MGN_VHT4SS_MCS0;
++		break;
++
++	default:
++		ndp_tx_rate = ODM_MGN_VHT2SS_MCS0;
++		break;
++	}
++
++	return ndp_tx_rate;
++}
++#endif
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++/*this function is only used for BFer*/
++void phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i;
++
++	if (dm->rf_type == RF_1T1R)
++		return;
++#if (RTL8822C_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8822C) {
++		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
++			/*Path A ==================*/
++			/*RF mode table write enable*/
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x1);
++			/*Select RX mode*/
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, 0xF, 3);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, 0x3, 0x2);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0xfffff,
++				       0x65AFF);
++			/*RF mode table write disable*/
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x0);
++
++			/*Path B ==================*/
++			/*RF mode table write enable*/
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x1);
++			/*Select RX mode*/
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0xF, 3);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, 0xfffff,
++				       0x996BF);
++			/*Select Standby mode*/
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0xF, 1);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, 0xfffff,
++				       0x99230);
++			/*RF mode table write disable*/
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x0);
++		}
++
++		/*@if Nsts > Nc, don't apply V matrix*/
++		odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
++
++		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
++			/*@enable BB TxBF ant mapping register*/
++			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
++			odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
++
++			/* logic mapping */
++			/* TX BF logic map and TX path en for Nsts = 1~2 */
++			odm_set_bb_reg(dm, R_0x820, 0xff, 0x33);
++			odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x404);
++			odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0x33);
++			odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0x404);
++		} else {
++			/*@Disable BB TxBF ant mapping register*/
++			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
++			odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
++			/*@1SS~2ss A, AB*/
++			odm_set_bb_reg(dm, R_0x820, 0xff, 0x31);
++			odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x400);
++		}
++	}
++#endif
++#if (RTL8812F_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8812F) {
++		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
++			/*Path A ==================*/
++			/*RF mode table write enable*/
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x1);
++			/*Select RX mode*/
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, 0xF, 3);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, 0x3, 0x3);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0xfffff,
++				       0x61AFE);
++			/*RF mode table write disable*/
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x0);
++
++			/*Path B ==================*/
++			/*RF mode table write enable*/
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x1);
++			/*Select RX mode*/
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0xF, 3);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, 0xfffff,
++				       0xD86BF);
++			/*RF mode table write disable*/
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x0);
++		}
++
++		/*@if Nsts > Nc, don't apply V matrix*/
++		odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
++
++		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
++			/*@enable BB TxBF ant mapping register*/
++			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
++			odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
++
++			/* logic mapping */
++			/* TX BF logic map and TX path en for Nsts = 1~2 */
++			odm_set_bb_reg(dm, R_0x820, 0xff, 0x33);
++			odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x404);
++			odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0x33);
++			odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0x404);
++		} else {
++			/*@Disable BB TxBF ant mapping register*/
++			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
++			odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
++			/*@1SS~2ss A, AB*/
++			odm_set_bb_reg(dm, R_0x820, 0xff, 0x31);
++			odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x400);
++		}
++	}
++#endif
++#if (RTL8814B_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8814B) {
++		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
++			for (i = RF_PATH_A; i <= RF_PATH_D; i++) {
++				/*RF mode table write enable*/
++				odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
++					       BIT(19), 0x1);
++				/*Select RX mode*/
++				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33,
++					       0xF, 2);
++				/*Set Table data*/
++				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e,
++					       0xfffff, 0x3fc);
++				/*Set Table data*/
++				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f,
++					       0xfffff, 0x280f7);
++				/*Select RX mode*/
++				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33,
++					       0xF, 3);
++				/*Set Table data*/
++				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e,
++					       0xfffff, 0x365);
++				/*Set Table data*/
++				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f,
++					       0xfffff, 0xafcf7);
++				/*RF mode table write disable*/
++				odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
++					       BIT(19), 0x0);
++			}
++		}
++		/*@if Nsts > Nc, don't apply V matrix*/
++		odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
++
++		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
++			/*@enable BB TxBF ant mapping register*/
++			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
++			odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
++
++			/* logic mapping */
++			/* TX BF logic map and TX path en for Nsts = 1~4 */
++			odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xffff);
++			/*verification path-AC*/
++			odm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e4e4e4);
++		} else {
++			/*@Disable BB TxBF ant mapping register*/
++			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
++			odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
++			/*@1SS~4ss A, AB, ABC, ABCD*/
++			odm_set_bb_reg(dm, R_0x820, 0xffff, 0xf731);
++			odm_set_bb_reg(dm, R_0x1e2c, 0xffffffff, 0xe4240400);
++		}
++	}
++#endif
++#if (RTL8198F_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8198F) {
++		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
++			for (i = RF_PATH_A; i <= RF_PATH_D; i++) {
++				/*RF mode table write enable*/
++				odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
++					       BIT(19), 0x1);
++				/*Select RX mode*/
++				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x30,
++					       0xfffff, 0x18000);
++				/*Set Table data*/
++				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x31,
++					       0xfffff, 0x4f);
++				/*Select RX mode*/
++				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x32,
++					       0xfffff, 0x71fc0);
++				/*RF mode table write disable*/
++				odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
++					       BIT(19), 0x0);
++			}
++		}
++		/*@if Nsts > Nc, don't apply V matrix*/
++		odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
++
++		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
++			/*@enable BB TxBF ant mapping register*/
++			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
++			odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
++
++			/* logic mapping */
++			/* TX BF logic map and TX path en for Nsts = 1~4 */
++			odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xffff);
++			odm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e4e4e4);
++		} else {
++			/*@Disable BB TxBF ant mapping register*/
++			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
++			odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
++			/*@1SS~4ss A, AB, ABC, ABCD*/
++			odm_set_bb_reg(dm, R_0x820, 0xffff, 0xf731);
++			odm_set_bb_reg(dm, R_0x1e2c, 0xffffffff, 0xe4240400);
++		}
++	}
++#endif
++#if (RTL8197G_SUPPORT)
++	if (dm->support_ic_type == ODM_RTL8197G) {
++		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
++			/*Path A ==================*/
++			/*RF mode table write enable*/
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x1);
++			/*Set RF Rx mode table*/
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff,
++				       0x18000);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff,
++				       0x000cf);
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff,
++				       0x71fc2);
++			/*RF mode table write disable*/
++			odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x0);
++
++			/*Path B ==================*/
++			/*RF mode table write enable*/
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x1);
++			/*Set RF Rx mode table*/
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff,
++				       0x18000);
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff,
++				       0x000cf);
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff,
++				       0x71fc2);
++			/*Set RF Standby mode table*/
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff,
++				       0x18000);
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff,
++				       0x000ef);
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff,
++				       0x01042);
++			/*RF mode table write disable*/
++			odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x0);
++		}
++
++		/*@if Nsts > Nc, don't apply V matrix*/
++		odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
++
++		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
++			/*@enable BB TxBF ant mapping register*/
++			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
++			odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
++
++			/* logic mapping */
++			/* TX BF logic map and TX path en for Nsts = 1~2 */
++			odm_set_bb_reg(dm, R_0x820, 0xff, 0x33);
++			odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x404);
++			odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0x33);
++			odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0x404);
++		} else {
++			/*@Disable BB TxBF ant mapping register*/
++			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
++			odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
++			/*@1SS~2ss A, AB*/
++			odm_set_bb_reg(dm, R_0x820, 0xff, 0x31);
++			odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x400);
++		}
++	}
++#endif
++}
++
++void phydm_mu_rsoml_reset(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] %s cnt reset\n", __func__);
++
++	odm_memory_set(dm, &rateinfo->num_mu_vht_pkt[0], 0, VHT_RATE_NUM * 2);
++	odm_memory_set(dm, &rateinfo->num_qry_vht_pkt[0], 0, VHT_RATE_NUM * 2);
++}
++
++void phydm_mu_rsoml_init(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3;
++	u32 val = 0;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] %s\n", __func__);
++
++	/*OFDM Tx*/
++	val = odm_get_bb_reg(dm, R_0x820, MASKDWORD);
++	rateinfo->tx_path_en_ofdm_2sts = (u8)((val & 0xf0) >> 4);
++	rateinfo->tx_path_en_ofdm_1sts = (u8)(val & 0xf);
++	/*OFDM Rx*/
++	rateinfo->rx_path_en_ofdm = (u8)odm_get_bb_reg(dm, R_0x824, 0xf0000);
++
++	rateinfo->enable = 1;
++	rateinfo->mu_ratio_th = 30;
++	rateinfo->pre_mu_ratio = 0;
++	rateinfo->mu_set_trxpath = 0;
++	rateinfo->mu_been_iot = 0;
++
++	PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] %s tx1ss=%d, tx2ss=%d, rx=%d\n",
++		  __func__, rateinfo->tx_path_en_ofdm_1sts,
++		  rateinfo->tx_path_en_ofdm_2sts, rateinfo->rx_path_en_ofdm);
++
++	phydm_mu_rsoml_reset(dm);
++}
++
++void phydm_mu_rsoml_decision(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	struct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3;
++	struct phydm_iot_center	*iot_table = &dm->iot_table;
++	u8 offset = 0;
++	u32 mu_ratio = 0;
++	u32 su_pkt = 0;
++	u32 mu_pkt = 0;
++	u32 total_pkt = 0;
++
++	if (rateinfo->tx_path_en_ofdm_2sts != 3 ||
++	    rateinfo->rx_path_en_ofdm != 3) {
++		PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] Init Not 2T2R 22CE\n");
++		return;
++	}
++
++	PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML Decision eanble: %d\n",
++		  rateinfo->enable);
++
++	if (!rateinfo->enable)
++		return;
++
++	for (offset = 0; offset < VHT_RATE_NUM; offset++) {
++		mu_pkt +=  rateinfo->num_mu_vht_pkt[offset];
++		su_pkt +=  rateinfo->num_qry_vht_pkt[offset];
++	}
++	total_pkt = su_pkt + mu_pkt;
++
++	if (total_pkt == 0)
++		mu_ratio = 0;
++	else
++		mu_ratio = (mu_pkt * 100) / total_pkt; // unit:%
++
++	PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] MU rx ratio: %d, total pkt: %d\n",
++		  mu_ratio, total_pkt);
++
++	if (mu_ratio > rateinfo->mu_ratio_th &&
++	    rateinfo->pre_mu_ratio > rateinfo->mu_ratio_th) {
++		PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML status remain\n");
++	} else if (mu_ratio <= rateinfo->mu_ratio_th &&
++		 rateinfo->pre_mu_ratio <= rateinfo->mu_ratio_th) {
++		PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML status remain\n");
++	} else if (mu_ratio > rateinfo->mu_ratio_th) {
++		odm_set_bb_reg(dm, R_0xc00, BIT(26), 0);
++		PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML OFF\n");
++	} else {
++		odm_set_bb_reg(dm, R_0xc00, BIT(26), 1);
++		PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML ON\n");
++	}
++
++	PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] set_trxpath=%d, patch_10120200=%d\n",
++		  rateinfo->mu_set_trxpath, iot_table->patch_id_10120200);
++	if (rateinfo->mu_set_trxpath && iot_table->patch_id_10120200) {
++		if (mu_ratio > rateinfo->mu_ratio_th) {
++			phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_A,
++					   BB_PATH_AUTO);
++			PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] 22C IOT 2T1R\n");
++			rateinfo->mu_been_iot = 1;
++		} else {
++			phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB,
++					   BB_PATH_AUTO);
++			PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] 22C IOT 2T2R\n");
++			rateinfo->mu_been_iot = 0;
++		}
++	} else if (rateinfo->mu_been_iot == 1) {
++		if (odm_get_bb_reg(dm, R_0x824, 0xf0000) == 1) {
++			phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB,
++					   BB_PATH_AUTO);
++			PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] 22C IOT Restore\n");
++			rateinfo->mu_been_iot = 0;
++		}
++	}
++
++	rateinfo->pre_mu_ratio = mu_ratio;
++	phydm_mu_rsoml_reset(dm);
++}
++
++void phydm_txbf_avoid_hang(void *dm_void)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++	/* avoid CCK CCA hang when the BF mode */
++	odm_set_bb_reg(dm, R_0x1e6c, 0x100000, 0x1);
++}
++
++#if (RTL8814B_SUPPORT == 1)
++void phydm_txbf_80p80_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	u8 i;
++
++	if (dm->rf_type == RF_1T1R)
++		return;
++
++	if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
++		for (i = RF_PATH_A; i <= RF_PATH_D; i += 3) {
++			/*RF mode table write enable*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),
++				       0x1);
++			/*Select RX mode*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 2);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff,
++				       0x3fc);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
++				       0x280f7);
++			/*Select RX mode*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff,
++				       0x365);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
++				       0xafcf7);
++			/*RF mode table write disable*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),
++				       0x0);
++		}
++		for (i = RF_PATH_B; i <= RF_PATH_C; i++) {
++			/*RF mode table write enable*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),
++				       0x1);
++			/*Select RX mode*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 2);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
++				       0x280c7);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
++				       0x280c7);
++			/*Select RX mode*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff,
++				       0x365);
++			/*Set Table data*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
++				       0xafcc7);
++			/*RF mode table write disable*/
++			odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),
++				       0x0);
++		}
++	}
++	/*@if Nsts > Nc, don't apply V matrix*/
++	odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
++
++	if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
++		/*@enable BB TxBF ant mapping register*/
++		odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
++		odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
++
++		/* logic mapping */
++		/* TX BF logic map and TX path en for Nsts = 1~2 */
++		odm_set_bb_reg(dm, R_0x820, 0xff0000, 0x33); /*seg0*/
++		odm_set_bb_reg(dm, R_0x824, 0xff00, 0xcc); /*seg1*/
++		odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0xe4e4);
++
++	} else {
++		/*@Disable BB TxBF ant mapping register*/
++		odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
++		odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
++		/*@1SS~2ss A, AB*/
++		odm_set_bb_reg(dm, R_0x820, 0xff, 0x31); /*seg0*/
++		odm_set_bb_reg(dm, R_0x824, 0xff, 0xc8); /*seg1*/
++		odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0xe420);
++	}
++}
++#endif
++#endif /*PHYSTS_3RD_TYPE_IC*/
++
++void phydm_bf_debug(void *dm_void, char input[][16], u32 *_used, char *output,
++		    u32 *_out_len)
++{
++	struct dm_struct *dm = (struct dm_struct *)dm_void;
++	char help[] = "-h";
++	u32 var1[3] = {0};
++	u32 i;
++
++	if ((strcmp(input[1], help) == 0)) {
++		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++			 "{BF ver1 :0}, {NO applyV:0; applyV:1; default:2}\n");
++		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++			 "{MU RSOML:1}, {MU enable:1/0}, {MU Ratio:40}\n");
++		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++			 "{MU TRxPath:2}, {TRxPath enable:1/0}\n");
++		return;
++	}
++	for (i = 0; i < 3; i++) {
++		if (input[i + 1])
++			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
++	}
++	if (var1[0] == 0) {
++		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++		#ifdef PHYDM_BEAMFORMING_SUPPORT
++		struct _RT_BEAMFORMING_INFO *beamforming_info = NULL;
++
++		beamforming_info = &dm->beamforming_info;
++
++		if (var1[1] == 0) {
++			beamforming_info->apply_v_matrix = false;
++			beamforming_info->snding3ss = true;
++			PDM_SNPF(*_out_len, *_used, output + *_used,
++				 *_out_len - *_used,
++				"\r\n dont apply V matrix and 3SS 789 snding\n");
++		} else if (var1[1] == 1) {
++			beamforming_info->apply_v_matrix = true;
++			beamforming_info->snding3ss = true;
++			PDM_SNPF(*_out_len, *_used, output + *_used,
++				 *_out_len - *_used,
++				 "\r\n apply V matrix and 3SS 789 snding\n");
++		} else if (var1[1] == 2) {
++			beamforming_info->apply_v_matrix = true;
++			beamforming_info->snding3ss = false;
++			PDM_SNPF(*_out_len, *_used, output + *_used,
++				 *_out_len - *_used,
++				 "\r\n default txbf setting\n");
++		} else {
++			PDM_SNPF(*_out_len, *_used, output + *_used,
++				 *_out_len - *_used,
++				 "\r\n unknown cmd!!\n");
++		}
++		#endif
++		#endif
++	} else if (var1[0] == 1) {
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		struct dm_struct *dm = (struct dm_struct *)dm_void;
++		struct phydm_bf_rate_info_jgr3 *bfinfo = &dm->bf_rate_info_jgr3;
++
++		bfinfo->enable = (u8)var1[1];
++		bfinfo->mu_ratio_th = (u8)var1[2];
++		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++			 "[MU RSOML] enable= %d, MU ratio TH= %d\n",
++			 bfinfo->enable, bfinfo->mu_ratio_th);
++		#endif
++	} else if (var1[0] == 2) {
++		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++		struct dm_struct *dm = (struct dm_struct *)dm_void;
++		struct phydm_bf_rate_info_jgr3 *bfinfo = &dm->bf_rate_info_jgr3;
++
++		bfinfo->mu_set_trxpath = (u8)var1[1];
++		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
++			 "[MU TRxPath] mu_set_trxpath = %d\n",
++			 bfinfo->mu_set_trxpath);
++		#endif
++	}
++}
++
++#endif /*CONFIG_BB_TXBF_API*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/phydm_hal_txbf_api.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/phydm_hal_txbf_api.h
+new file mode 100644
+index 000000000..15659ccb3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/phydm/txbf/phydm_hal_txbf_api.h
+@@ -0,0 +1,89 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017  Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae <wlanfae@realtek.com>
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger <Larry.Finger@lwfinger.net>
++ *
++ *****************************************************************************/
++#ifndef __PHYDM_HAL_TXBF_API_H__
++#define __PHYDM_HAL_TXBF_API_H__
++
++#if (defined(CONFIG_BB_TXBF_API))
++
++#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
++#if defined(DM_ODM_CE_MAC80211)
++#define tx_bf_nr(a, b) ({	\
++	u8 __tx_bf_nr_a = (a);	\
++	u8 __tx_bf_nr_b = (b);	\
++	((__tx_bf_nr_a > __tx_bf_nr_b) ? (__tx_bf_nr_b) : (__tx_bf_nr_a)); })
++#else
++#define tx_bf_nr(a, b) ((a > b) ? (b) : (a))
++#endif
++
++u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num);
++
++u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num);
++
++#endif
++
++#if (RTL8822B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8192F_SUPPORT == 1 ||\
++	RTL8814B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 || RTL8812F_SUPPORT == 1)
++u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput,
++				       u8 total_bfee_num, u8 *tx_rate);
++u8 phydm_get_ndpa_rate(void *dm_void);
++
++u8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput);
++
++#else
++#define phydm_get_beamforming_sounding_info(dm, tp, bfee_num, rate) 0
++#define phydm_get_ndpa_rate(dm)
++#define phydm_get_mu_bfee_snding_decision(dm, tp)
++
++#endif
++
++#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++struct phydm_bf_rate_info_jgr3 {
++	u8			enable;
++	u8			mu_ratio_th;
++	u32			pre_mu_ratio;
++	u16			num_mu_vht_pkt[VHT_RATE_NUM];
++	u16			num_qry_vht_pkt[VHT_RATE_NUM];
++	boolean			mu_set_trxpath;
++	u8			tx_path_en_ofdm_1sts;
++	u8			tx_path_en_ofdm_2sts;
++	u8			rx_path_en_ofdm;
++	boolean			mu_been_iot;
++};
++
++/*this function is only used for BFer*/
++void phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt);
++void phydm_txbf_avoid_hang(void *dm_void);
++void phydm_mu_rsoml_init(void *dm_void);
++void phydm_mu_rsoml_decision(void *dm_void);
++
++#if (RTL8814B_SUPPORT == 1)
++void phydm_txbf_80p80_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt);
++#endif
++
++#endif /*#PHYDM_IC_JGR3_SERIES_SUPPORT*/
++void phydm_bf_debug(void *dm_void, char input[][16], u32 *_used, char *output,
++		    u32 *_out_len);
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/Hal8723DPwrSeq.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/Hal8723DPwrSeq.c
+new file mode 100644
+index 000000000..8e99a0b5c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/Hal8723DPwrSeq.c
+@@ -0,0 +1,84 @@
++/******************************************************************************
++ *
++ * Copyright(c) Semiconductor - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++
++#include "Hal8723DPwrSeq.h"
++
++
++/*
++    drivers should parse below arrays and do the corresponding actions
++*/
++/* 3 Power on  Array */
++WLAN_PWR_CFG rtl8723D_power_on_flow[RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS] = {
++	RTL8723D_TRANS_CARDEMU_TO_ACT
++	RTL8723D_TRANS_END
++};
++
++/* 3Radio off GPIO Array */
++WLAN_PWR_CFG rtl8723D_radio_off_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_END_STEPS] = {
++	RTL8723D_TRANS_ACT_TO_CARDEMU
++	RTL8723D_TRANS_END
++};
++
++/* 3Card Disable Array */
++WLAN_PWR_CFG rtl8723D_card_disable_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_CARDDIS_STEPS + RTL8723D_TRANS_END_STEPS] = {
++	RTL8723D_TRANS_ACT_TO_CARDEMU
++	RTL8723D_TRANS_CARDEMU_TO_CARDDIS
++	RTL8723D_TRANS_END
++};
++
++/* 3 Card Enable Array */
++WLAN_PWR_CFG rtl8723D_card_enable_flow[RTL8723D_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS] = {
++	RTL8723D_TRANS_CARDDIS_TO_CARDEMU
++	RTL8723D_TRANS_CARDEMU_TO_ACT
++	RTL8723D_TRANS_END
++};
++
++/* 3Suspend Array */
++WLAN_PWR_CFG rtl8723D_suspend_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723D_TRANS_END_STEPS] = {
++	RTL8723D_TRANS_ACT_TO_CARDEMU
++	RTL8723D_TRANS_CARDEMU_TO_SUS
++	RTL8723D_TRANS_END
++};
++
++/* 3 Resume Array */
++WLAN_PWR_CFG rtl8723D_resume_flow[RTL8723D_TRANS_SUS_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS] = {
++	RTL8723D_TRANS_SUS_TO_CARDEMU
++	RTL8723D_TRANS_CARDEMU_TO_ACT
++	RTL8723D_TRANS_END
++};
++
++
++
++/* 3HWPDN Array */
++WLAN_PWR_CFG rtl8723D_hwpdn_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723D_TRANS_END_STEPS] = {
++	RTL8723D_TRANS_ACT_TO_CARDEMU
++	RTL8723D_TRANS_CARDEMU_TO_PDN
++	RTL8723D_TRANS_END
++};
++
++/* 3 Enter LPS */
++WLAN_PWR_CFG rtl8723D_enter_lps_flow[RTL8723D_TRANS_ACT_TO_LPS_STEPS + RTL8723D_TRANS_END_STEPS] = {
++	/* FW behavior */
++	RTL8723D_TRANS_ACT_TO_LPS
++	RTL8723D_TRANS_END
++};
++
++/* 3 Leave LPS */
++WLAN_PWR_CFG rtl8723D_leave_lps_flow[RTL8723D_TRANS_LPS_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS] = {
++	/* FW behavior */
++	RTL8723D_TRANS_LPS_TO_ACT
++	RTL8723D_TRANS_END
++};
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/hal8723d_fw.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/hal8723d_fw.c
+new file mode 100644
+index 000000000..0da8e6ec8
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/hal8723d_fw.c
+@@ -0,0 +1,10915 @@
++/******************************************************************************
++*
++* Copyright(c) 2012 - 2017 Realtek Corporation.
++*
++* This program is free software; you can redistribute it and/or modify it
++* under the terms of version 2 of the GNU General Public License as
++* published by the Free Software Foundation.
++*
++* This program is distributed in the hope that it will be useful, but WITHOUT
++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++* more details.
++*
++******************************************************************************/
++
++#ifdef CONFIG_RTL8723D
++
++#include "drv_types.h"
++
++#ifdef LOAD_FW_HEADER_FROM_DRIVER
++
++#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))
++
++u8 array_mp_8723d_fw_ap[] = {
++0xD1, 0x23, 0x20, 0x00, 0x31, 0x00, 0x00, 0x00,
++0x11, 0x18, 0x20, 0x42, 0xFA, 0x64, 0x02, 0x00,
++0x72, 0xB6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x02, 0x85, 0xA9, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0xCC, 0xD3, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0xCF, 0x7F, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0xCE, 0xD1, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0xB1, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0xCF, 0x29, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x15, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x15,
++0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x05, 0xF0,
++0xFF, 0x0F, 0x00, 0x00, 0x00, 0x05, 0xF0, 0x0F,
++0x00, 0x00, 0x00, 0x00, 0x10, 0xF0, 0xFF, 0x0F,
++0x00, 0x00, 0x00, 0x10, 0xF0, 0x0F, 0x00, 0x00,
++0x00, 0x00, 0xF5, 0x0F, 0x00, 0x00, 0x00, 0x00,
++0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A,
++0x08, 0x03, 0x03, 0x00, 0x04, 0x09, 0x07, 0x03,
++0x03, 0x00, 0x04, 0x08, 0x06, 0x03, 0x02, 0x00,
++0x04, 0x08, 0x05, 0x03, 0x01, 0x00, 0x04, 0x0D,
++0x0A, 0x07, 0x05, 0x00, 0x08, 0x0C, 0x0A, 0x07,
++0x04, 0x00, 0x08, 0x0B, 0x0A, 0x06, 0x05, 0x00,
++0x08, 0x0B, 0x0A, 0x05, 0x03, 0x00, 0x08, 0x0B,
++0x0A, 0x03, 0x02, 0x00, 0x08, 0x14, 0x12, 0x0C,
++0x04, 0x00, 0x10, 0x14, 0x12, 0x09, 0x04, 0x00,
++0x10, 0x24, 0x22, 0x1C, 0x12, 0x00, 0x20, 0x24,
++0x22, 0x18, 0x0C, 0x00, 0x20, 0x24, 0x22, 0x14,
++0x06, 0x00, 0x20, 0x24, 0x22, 0x0F, 0x04, 0x00,
++0x20, 0x24, 0x21, 0x0A, 0x04, 0x00, 0x20, 0x23,
++0x21, 0x0C, 0x04, 0x00, 0x20, 0x23, 0x1F, 0x0A,
++0x04, 0x00, 0x20, 0x22, 0x1F, 0x0F, 0x04, 0x00,
++0x20, 0x21, 0x1F, 0x16, 0x0C, 0x00, 0x20, 0x31,
++0x2F, 0x20, 0x14, 0x00, 0x30, 0x31, 0x2F, 0x18,
++0x10, 0x00, 0x30, 0x31, 0x2C, 0x18, 0x0C, 0x00,
++0x30, 0x31, 0x2A, 0x14, 0x0C, 0x00, 0x30, 0x31,
++0x28, 0x14, 0x00, 0x00, 0x30, 0x31, 0x24, 0x14,
++0x00, 0x00, 0x30, 0x31, 0x1E, 0x14, 0x00, 0x00,
++0x30, 0x02, 0x02, 0x03, 0x04, 0x04, 0x08, 0x09,
++0x09, 0x0C, 0x0E, 0x10, 0x12, 0x02, 0x09, 0x0B,
++0x0E, 0x0D, 0x0F, 0x10, 0x12, 0x00, 0x04, 0x00,
++0x04, 0x00, 0x08, 0x00, 0x10, 0x00, 0x23, 0x00,
++0x2D, 0x00, 0x50, 0x00, 0x91, 0x00, 0xC3, 0x01,
++0x27, 0x01, 0x31, 0x01, 0x5E, 0x00, 0x8C, 0x00,
++0xC8, 0x00, 0xDC, 0x01, 0x5E, 0x01, 0x68, 0x01,
++0x9A, 0x01, 0xCC, 0x01, 0xEA, 0x02, 0x02, 0x04,
++0x08, 0x0C, 0x12, 0x18, 0x24, 0x30, 0x48, 0x60,
++0x6C, 0x14, 0x28, 0x32, 0x50, 0x78, 0xA0, 0xC8,
++0xE6, 0x01, 0x01, 0x01, 0x02, 0x01, 0x01, 0x02,
++0x02, 0x03, 0x03, 0x04, 0x04, 0x02, 0x04, 0x06,
++0x07, 0x07, 0x08, 0x08, 0x08, 0x01, 0x01, 0x01,
++0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02,
++0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02,
++0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02,
++0x02, 0x03, 0x03, 0x04, 0x05, 0x01, 0x02, 0x03,
++0x04, 0x05, 0x06, 0x07, 0x08, 0x03, 0x03, 0x03,
++0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x02, 0x02,
++0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
++0x02, 0x19, 0x06, 0x04, 0x02, 0x00, 0x18, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0xC2, 0xAF, 0x80, 0xFE, 0x32, 0x12, 0x83, 0x04,
++0x85, 0xD0, 0x0B, 0x75, 0xD0, 0x08, 0xAA, 0xE0,
++0xC2, 0x8C, 0xE5, 0x8A, 0x24, 0x67, 0xF5, 0x8A,
++0xE5, 0x8C, 0x34, 0x79, 0xF5, 0x8C, 0xD2, 0x8C,
++0xEC, 0x24, 0x8B, 0xF8, 0xE6, 0xBC, 0x02, 0x02,
++0x74, 0xFF, 0xC3, 0x95, 0x81, 0xB4, 0x40, 0x00,
++0x40, 0xCE, 0x79, 0x03, 0x78, 0x80, 0x16, 0xE6,
++0x08, 0x70, 0x0B, 0xC2, 0xAF, 0xE6, 0x30, 0xE1,
++0x03, 0x44, 0x18, 0xF6, 0xD2, 0xAF, 0x08, 0xD9,
++0xED, 0xEA, 0x8B, 0xD0, 0x22, 0xE5, 0x0C, 0xFF,
++0x23, 0x24, 0x81, 0xF8, 0x0F, 0x08, 0x08, 0xBF,
++0x03, 0x04, 0x7F, 0x00, 0x78, 0x81, 0xE6, 0x30,
++0xE4, 0xF2, 0x00, 0xE5, 0x0C, 0xC3, 0x9F, 0x50,
++0x20, 0x05, 0x0C, 0x74, 0x8A, 0x25, 0x0C, 0xF8,
++0xE6, 0xFD, 0xA6, 0x81, 0x08, 0xE6, 0xAE, 0x0C,
++0xBE, 0x02, 0x02, 0x74, 0xFF, 0xCD, 0xF8, 0xE8,
++0x6D, 0x60, 0xE0, 0x08, 0xE6, 0xC0, 0xE0, 0x80,
++0xF6, 0xE5, 0x0C, 0xD3, 0x9F, 0x40, 0x27, 0xE5,
++0x0C, 0x24, 0x8B, 0xF8, 0xE6, 0xAE, 0x0C, 0xBE,
++0x02, 0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xCD,
++0xF8, 0xE5, 0x81, 0x6D, 0x60, 0x06, 0xD0, 0xE0,
++0xF6, 0x18, 0x80, 0xF5, 0xE5, 0x0C, 0x24, 0x8A,
++0xC8, 0xF6, 0x15, 0x0C, 0x80, 0xD3, 0xE5, 0x0C,
++0x23, 0x24, 0x81, 0xF8, 0x7F, 0x04, 0xC2, 0xAF,
++0xE6, 0x30, 0xE0, 0x03, 0x10, 0xE2, 0x0C, 0x7F,
++0x00, 0x30, 0xE1, 0x07, 0x30, 0xE3, 0x04, 0x7F,
++0x08, 0x54, 0xF4, 0x54, 0x7C, 0xC6, 0xD2, 0xAF,
++0x54, 0x80, 0x42, 0x07, 0x22, 0x78, 0x8A, 0xA6,
++0x81, 0x74, 0x02, 0x60, 0x06, 0xFF, 0x08, 0x76,
++0xFF, 0xDF, 0xFB, 0x7F, 0x03, 0xE4, 0x78, 0x80,
++0xF6, 0x08, 0xF6, 0x08, 0xDF, 0xFA, 0x78, 0x81,
++0x76, 0x30, 0x90, 0x86, 0xC0, 0x74, 0x01, 0x93,
++0xC0, 0xE0, 0xE4, 0x93, 0xC0, 0xE0, 0x43, 0x89,
++0x01, 0x75, 0x8A, 0x60, 0x75, 0x8C, 0x79, 0xD2,
++0x8C, 0xD2, 0xAF, 0x22, 0x02, 0xEF, 0xD3, 0x94,
++0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0x74, 0x81,
++0x2F, 0x2F, 0xF8, 0xE6, 0x20, 0xE5, 0xF4, 0xC2,
++0xAF, 0xE6, 0x44, 0x30, 0xF6, 0xD2, 0xAF, 0xAE,
++0x0C, 0xEE, 0xC3, 0x9F, 0x50, 0x21, 0x0E, 0x74,
++0x8A, 0x2E, 0xF8, 0xE6, 0xF9, 0x08, 0xE6, 0x18,
++0xBE, 0x02, 0x02, 0x74, 0xFF, 0xFD, 0xED, 0x69,
++0x60, 0x09, 0x09, 0xE7, 0x19, 0x19, 0xF7, 0x09,
++0x09, 0x80, 0xF3, 0x16, 0x16, 0x80, 0xDA, 0xEE,
++0xD3, 0x9F, 0x40, 0x04, 0x05, 0x81, 0x05, 0x81,
++0xEE, 0xD3, 0x9F, 0x40, 0x22, 0x74, 0x8A, 0x2E,
++0xF8, 0x08, 0xE6, 0xF9, 0xEE, 0xB5, 0x0C, 0x02,
++0xA9, 0x81, 0x18, 0x06, 0x06, 0xE6, 0xFD, 0xED,
++0x69, 0x60, 0x09, 0x19, 0x19, 0xE7, 0x09, 0x09,
++0xF7, 0x19, 0x80, 0xF3, 0x1E, 0x80, 0xD9, 0xEF,
++0x24, 0x8A, 0xF8, 0xE6, 0x04, 0xF8, 0xEF, 0x2F,
++0x04, 0x90, 0x86, 0xC0, 0x93, 0xF6, 0x08, 0xEF,
++0x2F, 0x93, 0xF6, 0x7F, 0x00, 0x22, 0xEF, 0xD3,
++0x94, 0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0xEF,
++0x23, 0x24, 0x81, 0xF8, 0xE6, 0x30, 0xE5, 0xF4,
++0xC2, 0xAF, 0xE6, 0x54, 0x8C, 0xF6, 0xD2, 0xAF,
++0xE5, 0x0C, 0xB5, 0x07, 0x0A, 0x74, 0x8A, 0x2F,
++0xF8, 0xE6, 0xF5, 0x81, 0x02, 0x83, 0x4D, 0x50,
++0x2E, 0x74, 0x8B, 0x2F, 0xF8, 0xE6, 0xBF, 0x02,
++0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xF9, 0x74,
++0x8A, 0x2F, 0xF8, 0xFB, 0xE6, 0xFC, 0xE9, 0x6C,
++0x60, 0x08, 0xA8, 0x05, 0xE7, 0xF6, 0x1D, 0x19,
++0x80, 0xF4, 0xA8, 0x03, 0xA6, 0x05, 0x1F, 0xE5,
++0x0C, 0xB5, 0x07, 0xE3, 0x7F, 0x00, 0x22, 0x74,
++0x8B, 0x2F, 0xF8, 0xE6, 0xFD, 0x18, 0x86, 0x01,
++0x0F, 0x74, 0x8A, 0x2F, 0xF8, 0xA6, 0x01, 0x08,
++0x86, 0x04, 0xE5, 0x0C, 0xB5, 0x07, 0x02, 0xAC,
++0x81, 0xED, 0x6C, 0x60, 0x08, 0x0D, 0x09, 0xA8,
++0x05, 0xE6, 0xF7, 0x80, 0xF4, 0xE5, 0x0C, 0xB5,
++0x07, 0xDE, 0x89, 0x81, 0x7F, 0x00, 0x22, 0xEF,
++0xD3, 0x94, 0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22,
++0xEF, 0x23, 0x24, 0x81, 0xF8, 0xC2, 0xAF, 0xE6,
++0x30, 0xE5, 0x05, 0x30, 0xE0, 0x02, 0xD2, 0xE4,
++0xD2, 0xE2, 0xC6, 0xD2, 0xAF, 0x7F, 0x00, 0x30,
++0xE2, 0x01, 0x0F, 0x02, 0x83, 0x4C, 0x8F, 0xF0,
++0xE4, 0xFF, 0xFE, 0xE5, 0x0C, 0x23, 0x24, 0x80,
++0xF8, 0xC2, 0xA9, 0x30, 0xF7, 0x0D, 0x7F, 0x08,
++0xE6, 0x60, 0x0B, 0x2D, 0xF6, 0x60, 0x30, 0x50,
++0x2E, 0x80, 0x07, 0x30, 0xF1, 0x06, 0xED, 0xF6,
++0x60, 0x25, 0x7E, 0x02, 0x08, 0x30, 0xF0, 0x10,
++0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x23, 0x0E, 0x30,
++0xE2, 0x0C, 0xD2, 0xAF, 0x7F, 0x04, 0x80, 0x12,
++0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x13, 0x54, 0xEC,
++0x4E, 0xF6, 0xD2, 0xAF, 0x02, 0x83, 0x4D, 0x7F,
++0x08, 0x08, 0xEF, 0x44, 0x83, 0xF4, 0xC2, 0xAF,
++0x56, 0xC6, 0xD2, 0xAF, 0x54, 0x80, 0x4F, 0xFF,
++0x22, 0x02, 0x85, 0xE7, 0x02, 0x83, 0xDD, 0xE4,
++0x93, 0xA3, 0xF8, 0xE4, 0x93, 0xA3, 0x40, 0x03,
++0xF6, 0x80, 0x01, 0xF2, 0x08, 0xDF, 0xF4, 0x80,
++0x29, 0xE4, 0x93, 0xA3, 0xF8, 0x54, 0x07, 0x24,
++0x0C, 0xC8, 0xC3, 0x33, 0xC4, 0x54, 0x0F, 0x44,
++0x20, 0xC8, 0x83, 0x40, 0x04, 0xF4, 0x56, 0x80,
++0x01, 0x46, 0xF6, 0xDF, 0xE4, 0x80, 0x0B, 0x01,
++0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x90,
++0x86, 0xA5, 0xE4, 0x7E, 0x01, 0x93, 0x60, 0xBC,
++0xA3, 0xFF, 0x54, 0x3F, 0x30, 0xE5, 0x09, 0x54,
++0x1F, 0xFE, 0xE4, 0x93, 0xA3, 0x60, 0x01, 0x0E,
++0xCF, 0x54, 0xC0, 0x25, 0xE0, 0x60, 0xA8, 0x40,
++0xB8, 0xE4, 0x93, 0xA3, 0xFA, 0xE4, 0x93, 0xA3,
++0xF8, 0xE4, 0x93, 0xA3, 0xC8, 0xC5, 0x82, 0xC8,
++0xCA, 0xC5, 0x83, 0xCA, 0xF0, 0xA3, 0xC8, 0xC5,
++0x82, 0xC8, 0xCA, 0xC5, 0x83, 0xCA, 0xDF, 0xE9,
++0xDE, 0xE7, 0x80, 0xBE, 0xEF, 0x2B, 0xFF, 0xEE,
++0x3A, 0xFE, 0xED, 0x39, 0xFD, 0xEC, 0x38, 0xFC,
++0x22, 0xC3, 0xEF, 0x9B, 0xFF, 0xEE, 0x9A, 0xFE,
++0xED, 0x99, 0xFD, 0xEC, 0x98, 0xFC, 0x22, 0xEF,
++0x5B, 0xFF, 0xEE, 0x5A, 0xFE, 0xED, 0x59, 0xFD,
++0xEC, 0x58, 0xFC, 0x22, 0xEF, 0x4B, 0xFF, 0xEE,
++0x4A, 0xFE, 0xED, 0x49, 0xFD, 0xEC, 0x48, 0xFC,
++0x22, 0xE0, 0xF8, 0xA3, 0xE0, 0xF9, 0xA3, 0xE0,
++0xFA, 0xA3, 0xE0, 0xFB, 0x22, 0xE0, 0xFB, 0xA3,
++0xE0, 0xFA, 0xA3, 0xE0, 0xF9, 0x22, 0xEB, 0xF0,
++0xA3, 0xEA, 0xF0, 0xA3, 0xE9, 0xF0, 0x22, 0xD0,
++0x83, 0xD0, 0x82, 0xF8, 0xE4, 0x93, 0x70, 0x12,
++0x74, 0x01, 0x93, 0x70, 0x0D, 0xA3, 0xA3, 0x93,
++0xF8, 0x74, 0x01, 0x93, 0xF5, 0x82, 0x88, 0x83,
++0xE4, 0x73, 0x74, 0x02, 0x93, 0x68, 0x60, 0xEF,
++0xA3, 0xA3, 0xA3, 0x80, 0xDF, 0x41, 0x97, 0x0A,
++0x00, 0x41, 0x97, 0x0F, 0x00, 0x44, 0x96, 0xCA,
++0x41, 0x4E, 0x59, 0x00, 0x44, 0x96, 0xC6, 0x61,
++0x6E, 0x79, 0x00, 0x41, 0x97, 0x12, 0x00, 0x00,
++0x9C, 0xA5, 0xC9, 0x84, 0x94, 0xF3, 0x90, 0x97,
++0x09, 0xEF, 0xF0, 0x7F, 0x02, 0xB1, 0x27, 0x90,
++0x86, 0xAF, 0xE0, 0xFF, 0x90, 0x97, 0x09, 0xE0,
++0xFE, 0xEF, 0x4E, 0x90, 0x86, 0xAF, 0xF0, 0x22,
++0x90, 0x02, 0x09, 0xE0, 0xFD, 0x12, 0x02, 0x06,
++0xFE, 0xAF, 0x05, 0xED, 0x2E, 0x90, 0x86, 0xB4,
++0xF0, 0xF1, 0x9F, 0xFF, 0xED, 0x2F, 0x90, 0x86,
++0xB5, 0xF1, 0x26, 0xFF, 0xED, 0x2F, 0x90, 0x86,
++0xB6, 0xF1, 0x76, 0xFF, 0xED, 0x2F, 0x90, 0x86,
++0xB7, 0xF1, 0x80, 0xFF, 0xED, 0x2F, 0x90, 0x86,
++0xB8, 0xF1, 0x8E, 0xFF, 0xED, 0x2F, 0x90, 0x86,
++0xB9, 0xF1, 0x87, 0xFF, 0xAE, 0x05, 0xED, 0x2F,
++0x90, 0x86, 0xBA, 0xF0, 0x22, 0x4F, 0xF0, 0x90,
++0x00, 0x02, 0x02, 0x02, 0x1F, 0x12, 0x02, 0x06,
++0xFE, 0xF1, 0x27, 0xFF, 0x74, 0xD6, 0x2E, 0xF5,
++0x82, 0xE4, 0x34, 0x8D, 0xF1, 0x73, 0xFF, 0xF1,
++0x6A, 0xF1, 0x7D, 0xFF, 0x74, 0x18, 0x2E, 0xF1,
++0x95, 0xEF, 0xF0, 0xF1, 0x6A, 0xF5, 0x83, 0xE0,
++0x30, 0xE5, 0x16, 0x75, 0xF0, 0x12, 0xEE, 0xF1,
++0xBD, 0x13, 0x13, 0x54, 0x03, 0xFB, 0xAF, 0x06,
++0x74, 0xD6, 0x2E, 0xF1, 0xC9, 0xFD, 0x12, 0x6B,
++0xFD, 0x22, 0x74, 0xC6, 0x2E, 0xF5, 0x82, 0xE4,
++0x34, 0x8D, 0x22, 0xF5, 0x83, 0xEF, 0xF0, 0x90,
++0x00, 0x03, 0x02, 0x02, 0x1F, 0xF5, 0x83, 0xEF,
++0xF0, 0x90, 0x00, 0x04, 0x02, 0x02, 0x1F, 0xF0,
++0x90, 0x00, 0x06, 0x02, 0x02, 0x1F, 0xF0, 0x90,
++0x00, 0x05, 0x02, 0x02, 0x1F, 0xF5, 0x82, 0xE4,
++0x34, 0x96, 0xF5, 0x83, 0x22, 0xD1, 0x6D, 0x90,
++0x00, 0x01, 0x02, 0x02, 0x1F, 0x12, 0x02, 0x06,
++0x90, 0x93, 0x26, 0xF0, 0xF1, 0x9F, 0x90, 0x93,
++0x27, 0xF1, 0x26, 0x90, 0x93, 0x28, 0xF0, 0x22,
++0xFF, 0x75, 0xF0, 0x12, 0xED, 0x90, 0x89, 0x52,
++0x12, 0x04, 0x6E, 0xE0, 0x22, 0x74, 0xD6, 0x25,
++0x62, 0xF5, 0x82, 0xE4, 0x34, 0x8D, 0xF5, 0x83,
++0xE0, 0x22, 0x12, 0x02, 0x06, 0xFF, 0xF1, 0x9F,
++0x90, 0x94, 0xC0, 0xF1, 0x26, 0x90, 0x94, 0xC1,
++0xF1, 0x76, 0x90, 0x94, 0xC2, 0xF1, 0x80, 0x90,
++0x94, 0xC3, 0xF1, 0x8E, 0x90, 0x94, 0xC4, 0xF1,
++0x87, 0x90, 0x94, 0xC5, 0xF0, 0xEF, 0x24, 0xF9,
++0x60, 0x45, 0x14, 0x70, 0x03, 0x02, 0x88, 0x99,
++0x14, 0x70, 0x02, 0x01, 0x9C, 0x24, 0xFE, 0x70,
++0x02, 0x01, 0xDB, 0x14, 0x70, 0x02, 0x01, 0xFF,
++0x24, 0x06, 0x60, 0x02, 0x21, 0x0F, 0x90, 0x94,
++0xC0, 0xE0, 0x90, 0x88, 0xE1, 0xF0, 0x90, 0x94,
++0xC1, 0xE0, 0x90, 0x88, 0xE2, 0xF0, 0x90, 0x94,
++0xC2, 0xE0, 0x90, 0x88, 0xE3, 0xF0, 0x90, 0x94,
++0xC3, 0xE0, 0x90, 0x88, 0xE4, 0xF0, 0x90, 0x94,
++0xC4, 0xE0, 0x90, 0x88, 0xE5, 0xF0, 0x22, 0x90,
++0x94, 0xC0, 0xE0, 0x90, 0x94, 0xAE, 0xF0, 0x90,
++0x94, 0xC3, 0x31, 0x2C, 0x78, 0x10, 0x12, 0x03,
++0xFE, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0,
++0x07, 0x31, 0x2B, 0x78, 0x18, 0x12, 0x03, 0xFE,
++0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00,
++0x12, 0x86, 0x54, 0xC0, 0x04, 0xC0, 0x05, 0xC0,
++0x06, 0xC0, 0x07, 0x90, 0x94, 0xC2, 0x31, 0x2C,
++0x78, 0x08, 0x12, 0x03, 0xFE, 0xD0, 0x03, 0xD0,
++0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x86, 0x54,
++0x12, 0xC7, 0x5E, 0x90, 0x94, 0xC1, 0x31, 0x2C,
++0x12, 0x86, 0x54, 0x90, 0x94, 0xA4, 0x02, 0x04,
++0x31, 0x02, 0xDC, 0x04, 0x90, 0x94, 0xB0, 0xE0,
++0x44, 0x01, 0xFF, 0xF0, 0x90, 0x94, 0xC0, 0xE0,
++0x54, 0x7F, 0x25, 0xE0, 0xFE, 0xEF, 0x54, 0x01,
++0x4E, 0x90, 0x94, 0xB0, 0xF0, 0xE0, 0xFF, 0xC3,
++0x13, 0x54, 0x7F, 0xC3, 0x94, 0x1E, 0x50, 0x06,
++0xEF, 0x54, 0x01, 0x44, 0x3C, 0xF0, 0x90, 0x94,
++0xB0, 0xE0, 0xFF, 0xC3, 0x13, 0x54, 0x7F, 0xD3,
++0x94, 0x50, 0x40, 0x55, 0xEF, 0x54, 0x01, 0x44,
++0xA0, 0xF0, 0x22, 0x90, 0x94, 0xC0, 0xE0, 0xFF,
++0x54, 0xC0, 0xC4, 0x13, 0x13, 0x54, 0x03, 0xFE,
++0x90, 0x94, 0xBB, 0xE0, 0x54, 0xFC, 0x4E, 0xFE,
++0xF0, 0xEF, 0x54, 0x3F, 0x25, 0xE0, 0x25, 0xE0,
++0xFF, 0xEE, 0x54, 0x03, 0x4F, 0xF0, 0x22, 0x90,
++0x94, 0xC0, 0xE0, 0x54, 0x01, 0xFF, 0x90, 0x94,
++0xB7, 0xE0, 0x54, 0xFE, 0x4F, 0xF0, 0x22, 0x7E,
++0x01, 0x7F, 0xFF, 0xAD, 0x06, 0x7B, 0x01, 0x7A,
++0x94, 0x79, 0xC0, 0x90, 0x8A, 0xCF, 0xE0, 0xF8,
++0xA3, 0xE0, 0xF5, 0x82, 0x88, 0x83, 0x12, 0x04,
++0x7E, 0x22, 0xF0, 0xA3, 0xE0, 0xFF, 0xE4, 0xFC,
++0xFD, 0xFE, 0x22, 0x90, 0x96, 0xDB, 0xEF, 0xF0,
++0x90, 0x94, 0xB9, 0xE0, 0x04, 0xF0, 0x90, 0x8A,
++0xD9, 0x71, 0x03, 0x7F, 0x01, 0x12, 0x04, 0x7E,
++0x90, 0x88, 0xA1, 0xF1, 0xCB, 0x30, 0xE0, 0x04,
++0x7F, 0x03, 0x80, 0x02, 0x7F, 0x01, 0x12, 0x71,
++0x9A, 0x90, 0x96, 0xDB, 0xE0, 0xB4, 0x02, 0x13,
++0x90, 0x88, 0x9E, 0xE0, 0x24, 0x03, 0xFF, 0x90,
++0x88, 0xAD, 0xE0, 0xC3, 0x9F, 0xFF, 0x90, 0x8A,
++0xD1, 0xD1, 0xB2, 0xE4, 0x90, 0x88, 0xAF, 0xF0,
++0x90, 0x96, 0xDB, 0xE0, 0xFF, 0xB4, 0x02, 0x08,
++0x90, 0x88, 0xB0, 0xE0, 0x04, 0xF0, 0x80, 0x09,
++0xEF, 0xB4, 0x05, 0x05, 0xE4, 0x90, 0x88, 0xB0,
++0xF0, 0xF1, 0xEC, 0x30, 0xE0, 0x21, 0x90, 0x96,
++0xDB, 0xE0, 0xB4, 0x02, 0x09, 0x90, 0x8A, 0xF9,
++0x71, 0x03, 0x7D, 0x08, 0x80, 0x6E, 0x90, 0x96,
++0xDB, 0xE0, 0x64, 0x05, 0x70, 0x6B, 0x90, 0x8A,
++0xF9, 0x71, 0x03, 0x7D, 0x0E, 0x80, 0x5D, 0xF1,
++0xE4, 0x30, 0xE0, 0x2D, 0xF1, 0xFB, 0x20, 0xE0,
++0x07, 0xF1, 0xD3, 0xE4, 0xFD, 0x12, 0x04, 0x7E,
++0x90, 0x96, 0xDB, 0xE0, 0xB4, 0x02, 0x09, 0x90,
++0x8A, 0xF9, 0x71, 0x03, 0x7D, 0x09, 0x80, 0x3C,
++0x90, 0x96, 0xDB, 0xE0, 0x64, 0x05, 0x70, 0x39,
++0x90, 0x8A, 0xF9, 0x71, 0x03, 0x7D, 0x0F, 0x80,
++0x2B, 0x90, 0x88, 0x36, 0xE0, 0x60, 0x2A, 0xF1,
++0xD3, 0xE4, 0xFD, 0x12, 0x04, 0x7E, 0x90, 0x96,
++0xDB, 0xE0, 0xB4, 0x02, 0x09, 0x90, 0x8A, 0xF9,
++0x71, 0x03, 0x7D, 0x0A, 0x80, 0x0E, 0x90, 0x96,
++0xDB, 0xE0, 0xB4, 0x05, 0x0C, 0x90, 0x8A, 0xF9,
++0x71, 0x03, 0x7D, 0x10, 0x7F, 0x6F, 0x12, 0x04,
++0x7E, 0x90, 0x88, 0xA0, 0xE0, 0x30, 0xE0, 0x07,
++0x90, 0x8A, 0xF9, 0x71, 0x03, 0xF1, 0xF5, 0x90,
++0x88, 0xA0, 0xF1, 0xCB, 0x30, 0xE0, 0x0A, 0x90,
++0x8A, 0x97, 0x71, 0x03, 0xE4, 0xFF, 0x12, 0x04,
++0x7E, 0x90, 0x88, 0xA1, 0xE0, 0xFF, 0xC3, 0x13,
++0x30, 0xE0, 0x0E, 0x90, 0x06, 0xCD, 0xE0, 0x54,
++0xEF, 0xF0, 0x90, 0x06, 0xCF, 0xE0, 0x54, 0xEF,
++0xF0, 0x12, 0xB7, 0x95, 0x30, 0xE0, 0x18, 0xEF,
++0x13, 0x13, 0x54, 0x3F, 0x30, 0xE0, 0x10, 0xEE,
++0x44, 0x08, 0xF0, 0xA3, 0xE0, 0xC3, 0x13, 0x54,
++0x7F, 0xFF, 0x90, 0x8A, 0xD1, 0xD1, 0xB2, 0x90,
++0x05, 0x63, 0xE0, 0x90, 0x96, 0xDF, 0xF0, 0x90,
++0x05, 0x62, 0xE0, 0x90, 0x96, 0xDE, 0xF0, 0x90,
++0x05, 0x61, 0xE0, 0x90, 0x96, 0xDD, 0xF0, 0x90,
++0x05, 0x60, 0xE0, 0x90, 0x96, 0xDC, 0x31, 0x2A,
++0x12, 0xC7, 0x59, 0x90, 0x96, 0xDC, 0x31, 0x2C,
++0x12, 0x86, 0x54, 0xC0, 0x04, 0xC0, 0x05, 0xC0,
++0x06, 0xC0, 0x07, 0x90, 0x96, 0xDE, 0x31, 0x2C,
++0x78, 0x10, 0x12, 0x03, 0xFE, 0xD0, 0x03, 0xD0,
++0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x86, 0x54,
++0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07,
++0x31, 0x2B, 0x78, 0x18, 0x12, 0x03, 0xFE, 0xD0,
++0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12,
++0x86, 0x54, 0x90, 0x94, 0xB1, 0x12, 0x04, 0x31,
++0x12, 0xDD, 0x77, 0x90, 0x96, 0xE0, 0xF0, 0x7B,
++0x01, 0x7A, 0x96, 0x79, 0xE0, 0x90, 0x8A, 0xCF,
++0x71, 0x03, 0x7D, 0x01, 0x7F, 0x42, 0x02, 0x04,
++0x7E, 0x90, 0x8A, 0x77, 0xE0, 0xFE, 0xA3, 0xE0,
++0xFF, 0xF5, 0x82, 0x8E, 0x83, 0x12, 0x04, 0x7E,
++0x90, 0x8A, 0x79, 0xE0, 0xFE, 0xA3, 0xE0, 0xF5,
++0x82, 0x8E, 0x83, 0x22, 0xD3, 0x10, 0xAF, 0x01,
++0xC3, 0xC0, 0xD0, 0x90, 0x94, 0xC0, 0xEF, 0xF0,
++0xA3, 0x74, 0x02, 0xF0, 0x90, 0x88, 0xC2, 0xE0,
++0x44, 0x10, 0xF0, 0x90, 0x88, 0xAF, 0xE0, 0x60,
++0x02, 0xA1, 0x0D, 0x90, 0x8A, 0xD9, 0x71, 0x03,
++0xE4, 0xFF, 0x12, 0x04, 0x7E, 0x90, 0x88, 0xA1,
++0xE0, 0x30, 0xE0, 0x04, 0x7F, 0x01, 0x80, 0x36,
++0x90, 0x88, 0x9D, 0xF1, 0xC1, 0x30, 0xE0, 0x04,
++0x7F, 0x0D, 0x80, 0x2A, 0x90, 0x88, 0xA0, 0xE0,
++0xFF, 0xC4, 0x54, 0x0F, 0x30, 0xE0, 0x10, 0xEF,
++0x13, 0x13, 0x54, 0x3F, 0x30, 0xE0, 0x04, 0x7F,
++0x09, 0x80, 0x13, 0x7F, 0x03, 0x80, 0x0F, 0x90,
++0x88, 0xA0, 0xE0, 0xC3, 0x13, 0x30, 0xE0, 0x04,
++0x7F, 0x03, 0x80, 0x02, 0x7F, 0x09, 0x12, 0x71,
++0x9A, 0x90, 0x94, 0xC0, 0xE0, 0x64, 0x03, 0x70,
++0x34, 0xF1, 0xBE, 0x90, 0x88, 0x9E, 0x30, 0xE0,
++0x1F, 0xE0, 0xFF, 0x90, 0x8A, 0xD1, 0xD1, 0xB2,
++0x90, 0x88, 0xA5, 0x74, 0x04, 0xF0, 0xE4, 0x90,
++0x88, 0xB0, 0xF0, 0x90, 0x06, 0x92, 0x74, 0x04,
++0xF0, 0xE4, 0x90, 0x88, 0xB2, 0xF0, 0x80, 0x0D,
++0xE0, 0xFF, 0x90, 0x8A, 0xD1, 0xD1, 0xB2, 0x90,
++0x88, 0xB0, 0xE0, 0x04, 0xF0, 0x90, 0x88, 0xAF,
++0x74, 0x01, 0xF0, 0xF1, 0xEC, 0x30, 0xE0, 0x0B,
++0x90, 0x94, 0xC0, 0xE0, 0x70, 0x5A, 0x12, 0xAA,
++0xB1, 0x80, 0x55, 0xF1, 0xE4, 0x30, 0xE0, 0x37,
++0x90, 0x88, 0xA3, 0xE0, 0x44, 0x20, 0xF0, 0x90,
++0x88, 0x9C, 0xE0, 0x60, 0x09, 0x90, 0x8A, 0xB9,
++0x71, 0x03, 0x7D, 0x01, 0x80, 0x35, 0x12, 0xAA,
++0xB0, 0xF1, 0xC8, 0x90, 0x8A, 0xB9, 0x20, 0xE0,
++0x08, 0x71, 0x03, 0x7D, 0x01, 0x7F, 0x0C, 0x80,
++0x24, 0x71, 0x03, 0xE4, 0xFD, 0x7F, 0x0C, 0x12,
++0x04, 0x7E, 0x12, 0xCE, 0x56, 0x80, 0x19, 0x90,
++0x94, 0xC0, 0xE0, 0xB4, 0x03, 0x12, 0x90, 0x88,
++0x36, 0xE0, 0x60, 0x0C, 0x90, 0x8A, 0xB9, 0x71,
++0x03, 0xE4, 0xFD, 0x7F, 0x04, 0x12, 0x04, 0x7E,
++0x90, 0x88, 0x9C, 0xE0, 0x60, 0x17, 0x90, 0x94,
++0xC0, 0xE0, 0x70, 0x04, 0x7B, 0x04, 0x80, 0x09,
++0x90, 0x94, 0xC0, 0xE0, 0xB4, 0x03, 0x0E, 0x7B,
++0x0B, 0x7D, 0x6F, 0x80, 0x03, 0xE4, 0xFB, 0xFD,
++0x7F, 0xFF, 0x12, 0xAA, 0xB5, 0x90, 0x88, 0xA0,
++0xF1, 0xCB, 0x30, 0xE0, 0x0A, 0x90, 0x8A, 0x97,
++0x71, 0x03, 0x7F, 0x01, 0x12, 0x04, 0x7E, 0x90,
++0x88, 0xA1, 0xE0, 0xC3, 0x13, 0x30, 0xE0, 0x0E,
++0x90, 0x06, 0xCD, 0xE0, 0x44, 0x10, 0xF0, 0x90,
++0x06, 0xCF, 0xE0, 0x44, 0x10, 0xF0, 0x90, 0x05,
++0x63, 0xE0, 0x90, 0x94, 0xC5, 0xF0, 0x90, 0x05,
++0x62, 0xE0, 0x90, 0x94, 0xC4, 0xF0, 0x90, 0x05,
++0x61, 0xE0, 0x90, 0x94, 0xC3, 0xF0, 0x90, 0x05,
++0x60, 0xE0, 0x90, 0x94, 0xC2, 0x31, 0x2A, 0x12,
++0xC7, 0x59, 0x90, 0x94, 0xC2, 0x31, 0x2C, 0x12,
++0x86, 0x54, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06,
++0xC0, 0x07, 0x90, 0x94, 0xC4, 0x31, 0x2C, 0x78,
++0x10, 0x12, 0x03, 0xFE, 0xD0, 0x03, 0xD0, 0x02,
++0xD0, 0x01, 0xD0, 0x00, 0x12, 0x86, 0x54, 0xC0,
++0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x31,
++0x2B, 0x78, 0x18, 0x12, 0x03, 0xFE, 0xD0, 0x03,
++0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x86,
++0x54, 0xA3, 0x12, 0x04, 0x31, 0x90, 0x88, 0xA1,
++0x12, 0x9F, 0xBB, 0x30, 0xE0, 0x2F, 0x90, 0x94,
++0xB1, 0x12, 0x04, 0xB8, 0x90, 0x94, 0xC6, 0x12,
++0xE4, 0xC0, 0x40, 0x21, 0x90, 0x94, 0xB1, 0x12,
++0x86, 0x61, 0x90, 0x94, 0xC6, 0x12, 0x04, 0xB8,
++0x12, 0x86, 0x39, 0xE4, 0xFB, 0x7A, 0x78, 0xF9,
++0xF8, 0xC3, 0x12, 0x03, 0xDA, 0x50, 0x06, 0x90,
++0x94, 0xB6, 0xE0, 0x04, 0xF0, 0xD0, 0xD0, 0x92,
++0xAF, 0x22, 0x90, 0x94, 0xC0, 0xEF, 0xF0, 0x90,
++0x8A, 0xD1, 0x71, 0x03, 0x7F, 0x03, 0x12, 0x04,
++0x7E, 0x90, 0x88, 0xA0, 0xE0, 0xC4, 0x54, 0x0F,
++0x90, 0x88, 0xB0, 0x30, 0xE0, 0x05, 0x74, 0x05,
++0xF0, 0x80, 0x03, 0xE0, 0x04, 0xF0, 0x90, 0x88,
++0xA1, 0x12, 0xAF, 0xB1, 0x20, 0xE0, 0x09, 0xEF,
++0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0, 0x3C,
++0x90, 0x88, 0xA0, 0xE0, 0xC4, 0x54, 0x0F, 0x30,
++0xE0, 0x0A, 0x90, 0x88, 0x9E, 0xE0, 0xFF, 0x90,
++0x88, 0xAE, 0x80, 0x21, 0x90, 0x94, 0xC0, 0xE0,
++0xFC, 0xB4, 0x01, 0x0D, 0x90, 0x88, 0x9E, 0xE0,
++0xFE, 0x90, 0x88, 0xAD, 0xE0, 0xC3, 0x9E, 0x80,
++0x0F, 0xEC, 0xB4, 0x04, 0x0F, 0x90, 0x88, 0x9E,
++0xE0, 0xFF, 0x90, 0x88, 0xAD, 0xE0, 0xC3, 0x9F,
++0x90, 0x88, 0xB4, 0xF0, 0xF1, 0xEC, 0x30, 0xE0,
++0x2D, 0xF1, 0xFB, 0x20, 0xE0, 0x02, 0xC1, 0x2E,
++0x90, 0x88, 0xB4, 0xE0, 0xFF, 0xC3, 0x94, 0x20,
++0x50, 0x0F, 0xEF, 0x25, 0xE0, 0x25, 0xE0, 0xFB,
++0x90, 0x8A, 0x91, 0x71, 0x03, 0xE4, 0xFD, 0x80,
++0x0A, 0x90, 0x8A, 0x91, 0x71, 0x03, 0x7B, 0x7F,
++0x7D, 0xFF, 0xE4, 0xFF, 0x80, 0x75, 0xF1, 0xE4,
++0x30, 0xE0, 0x4E, 0x12, 0xE4, 0xC7, 0x90, 0x8A,
++0xB9, 0x71, 0x03, 0xE4, 0xFD, 0x7F, 0x04, 0x12,
++0x04, 0x7E, 0xF1, 0xBE, 0x30, 0xE0, 0x3A, 0x90,
++0x88, 0xA4, 0xE0, 0x44, 0x02, 0xF0, 0x54, 0xFB,
++0xF0, 0xE4, 0x90, 0x88, 0xB3, 0xF0, 0x90, 0x88,
++0xB0, 0xF0, 0x90, 0x94, 0xC0, 0xE0, 0xFF, 0xB4,
++0x01, 0x08, 0x90, 0x88, 0xA5, 0x74, 0x06, 0xF0,
++0x80, 0x0A, 0xEF, 0xB4, 0x04, 0x06, 0x90, 0x88,
++0xA5, 0x74, 0x07, 0xF0, 0x90, 0x88, 0x9C, 0xE0,
++0x60, 0x07, 0x90, 0x88, 0xA4, 0xE0, 0x44, 0x04,
++0xF0, 0x90, 0x94, 0xC0, 0xE0, 0xB4, 0x01, 0x0B,
++0x90, 0x8A, 0xF9, 0x71, 0x03, 0x7D, 0x06, 0x7F,
++0x6F, 0x80, 0x10, 0x90, 0x94, 0xC0, 0xE0, 0xB4,
++0x04, 0x0C, 0x90, 0x8A, 0xF9, 0x71, 0x03, 0x7D,
++0x0C, 0x7F, 0x6F, 0x12, 0x04, 0x7E, 0x90, 0x88,
++0xA1, 0x12, 0x97, 0x30, 0x30, 0xE0, 0x2E, 0x90,
++0x88, 0xB4, 0xE0, 0xFE, 0xC3, 0x94, 0x20, 0x90,
++0x86, 0xB9, 0xE0, 0xFF, 0x50, 0x13, 0xC0, 0x07,
++0xEE, 0x7D, 0x00, 0x25, 0xE0, 0x25, 0xE0, 0xFC,
++0x90, 0x8A, 0xBF, 0x71, 0x03, 0xD0, 0x07, 0x80,
++0x09, 0x90, 0x8A, 0xBF, 0xF1, 0xDB, 0x7D, 0xFF,
++0x7C, 0x7F, 0x12, 0x04, 0x7E, 0x90, 0x88, 0xA0,
++0xE0, 0x30, 0xE0, 0x07, 0x90, 0x8A, 0xF9, 0x71,
++0x03, 0xF1, 0xF5, 0x22, 0x90, 0x86, 0xB6, 0xE0,
++0xFF, 0x90, 0x96, 0xE2, 0xE0, 0xFB, 0x90, 0x92,
++0x13, 0x74, 0x0A, 0xF0, 0x7D, 0x01, 0x12, 0x66,
++0xDB, 0x90, 0x96, 0xE3, 0xEE, 0xF0, 0xFC, 0xA3,
++0xEF, 0xF0, 0xFD, 0x90, 0x96, 0xE1, 0xE0, 0xFF,
++0x90, 0x8A, 0x95, 0xE0, 0xFA, 0xA3, 0xE0, 0xFB,
++0xF5, 0x82, 0x8A, 0x83, 0x12, 0x04, 0x7E, 0x90,
++0x96, 0xE3, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x90,
++0x8A, 0x9B, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0xF5,
++0x82, 0x8C, 0x83, 0x02, 0x04, 0x7E, 0x90, 0x93,
++0x2A, 0xE0, 0x30, 0xE0, 0x60, 0xC4, 0x54, 0x0F,
++0x20, 0xE0, 0x1F, 0x12, 0xE4, 0x7C, 0x12, 0x97,
++0xA8, 0x90, 0x8A, 0xF9, 0x71, 0x03, 0x12, 0x90,
++0xD9, 0x12, 0x98, 0xE5, 0x30, 0xE0, 0x08, 0x90,
++0x8A, 0x89, 0x71, 0x03, 0x12, 0x98, 0x11, 0x02,
++0x98, 0xEC, 0x90, 0x93, 0x2A, 0xE0, 0xC4, 0x54,
++0x0F, 0x30, 0xE0, 0x31, 0xE4, 0x90, 0x92, 0x20,
++0xF0, 0x90, 0x93, 0x2D, 0x12, 0x97, 0xA8, 0x90,
++0x93, 0x2A, 0xE0, 0x54, 0xEF, 0xF0, 0xE0, 0xC3,
++0x13, 0x30, 0xE0, 0x0C, 0x90, 0x8A, 0x89, 0x71,
++0x03, 0x7D, 0x04, 0x7F, 0x01, 0x02, 0x04, 0x7E,
++0x90, 0x8A, 0xF9, 0x71, 0x03, 0x7D, 0x31, 0x12,
++0xDC, 0xA1, 0x12, 0x90, 0xE2, 0x22, 0xD3, 0x10,
++0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x96, 0xE1,
++0xEF, 0xF0, 0xA3, 0xED, 0xF0, 0x90, 0x86, 0xB1,
++0xE0, 0x04, 0xF0, 0x90, 0x88, 0x9D, 0xE0, 0x30,
++0xE0, 0x07, 0x90, 0x05, 0x10, 0xE4, 0xF0, 0xA3,
++0xF0, 0x90, 0x04, 0x1D, 0xE0, 0x60, 0x39, 0x90,
++0x05, 0x22, 0xE0, 0x90, 0x96, 0xE5, 0xF0, 0x7B,
++0x26, 0x12, 0xAB, 0x67, 0x90, 0x8A, 0xFD, 0x12,
++0x90, 0xE2, 0xEF, 0x64, 0x01, 0x70, 0x02, 0x80,
++0x05, 0xF1, 0xBE, 0x30, 0xE0, 0x07, 0xD1, 0x74,
++0x12, 0xD1, 0x72, 0xEE, 0xF0, 0x90, 0x96, 0xE5,
++0xE0, 0xFD, 0x7B, 0x27, 0xE4, 0xFF, 0x12, 0xAA,
++0xB5, 0x12, 0xE4, 0x85, 0xD1, 0xB2, 0x80, 0x0C,
++0x12, 0xE4, 0x85, 0xD1, 0xB2, 0xD1, 0x74, 0x12,
++0xD1, 0x72, 0xEE, 0xF0, 0x90, 0x88, 0x9D, 0xE0,
++0x30, 0xE0, 0x16, 0xF1, 0xBE, 0x30, 0xE0, 0x11,
++0x90, 0x05, 0x22, 0xE0, 0x54, 0x6F, 0xFF, 0x90,
++0x8A, 0xF9, 0xF1, 0xDB, 0x7D, 0x28, 0x12, 0x04,
++0x7E, 0x90, 0x04, 0x1F, 0x74, 0x20, 0xF0, 0x7F,
++0x01, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x88,
++0xA1, 0xE0, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x22,
++0x90, 0x94, 0xAF, 0xE0, 0xC4, 0x13, 0x13, 0x13,
++0x54, 0x01, 0x22, 0x90, 0x88, 0x38, 0xE0, 0xFF,
++0x90, 0x8A, 0xB9, 0xE0, 0xFC, 0xA3, 0xE0, 0xF5,
++0x82, 0x8C, 0x83, 0x22, 0x90, 0x88, 0x9D, 0xE0,
++0xC4, 0x54, 0x0F, 0x22, 0x90, 0x88, 0x9D, 0xE0,
++0xC4, 0x13, 0x54, 0x07, 0x22, 0xE4, 0xFD, 0xFF,
++0x02, 0x04, 0x7E, 0x90, 0x88, 0xA1, 0xE0, 0xC4,
++0x13, 0x54, 0x07, 0x22, 0x90, 0x94, 0xC0, 0x12,
++0x86, 0x76, 0x90, 0x93, 0x4D, 0xE0, 0x70, 0x12,
++0x11, 0xD3, 0x12, 0x02, 0x06, 0x13, 0x13, 0x54,
++0x3F, 0x30, 0xE0, 0x06, 0x90, 0x93, 0x53, 0x74,
++0x01, 0xF0, 0x90, 0x93, 0x4F, 0xE0, 0x70, 0x12,
++0x11, 0xD3, 0x12, 0x02, 0x06, 0xC4, 0x54, 0x0F,
++0xFF, 0xBF, 0x05, 0x06, 0x90, 0x93, 0x54, 0x74,
++0x01, 0xF0, 0x11, 0xD3, 0x12, 0x87, 0x9F, 0xFF,
++0x90, 0x94, 0xC4, 0xF0, 0x12, 0x02, 0x06, 0xC3,
++0x13, 0x30, 0xE0, 0x0B, 0x11, 0xD3, 0x12, 0x87,
++0x27, 0x90, 0x94, 0xC5, 0xF0, 0x80, 0x05, 0x90,
++0x94, 0xC5, 0xEF, 0xF0, 0x90, 0x94, 0xC4, 0xE0,
++0x90, 0x94, 0xC3, 0xF0, 0x90, 0x94, 0xC5, 0xE0,
++0xFE, 0x90, 0x94, 0xC3, 0xE0, 0xFF, 0xD3, 0x9E,
++0x50, 0x38, 0x11, 0xD3, 0x12, 0x02, 0x06, 0x54,
++0x01, 0xFD, 0x12, 0x6E, 0x71, 0x90, 0x94, 0xC3,
++0xE0, 0xFF, 0x12, 0x78, 0x4A, 0xEF, 0x90, 0x94,
++0xC3, 0x70, 0x06, 0xE0, 0xFF, 0xB1, 0x6C, 0x80,
++0x04, 0xE0, 0xFF, 0xF1, 0xB7, 0x90, 0x93, 0x54,
++0xE0, 0x60, 0x07, 0x90, 0x94, 0xC3, 0xE0, 0xFF,
++0xB1, 0x6C, 0x90, 0x94, 0xC3, 0xE0, 0x04, 0xF0,
++0x80, 0xBA, 0x90, 0x05, 0x5E, 0xE4, 0xF0, 0x90,
++0x94, 0xC4, 0xE0, 0x70, 0x17, 0xFF, 0x12, 0x78,
++0x4A, 0xEF, 0x70, 0x10, 0x11, 0xDF, 0x90, 0x8A,
++0xED, 0x11, 0xE2, 0x12, 0xAF, 0xC7, 0x54, 0xBF,
++0xF0, 0x54, 0x7F, 0xF0, 0x22, 0x90, 0x94, 0xC0,
++0x12, 0x86, 0x76, 0x90, 0x94, 0xC0, 0x02, 0x86,
++0x6D, 0xE4, 0xFD, 0xFF, 0x12, 0x04, 0x7E, 0x90,
++0x86, 0x0C, 0xE0, 0xFE, 0xA3, 0xE0, 0xAA, 0x06,
++0xF9, 0x02, 0x04, 0x7A, 0xD3, 0x10, 0xAF, 0x01,
++0xC3, 0xC0, 0xD0, 0x90, 0x97, 0x10, 0xED, 0xF0,
++0x90, 0x88, 0x31, 0xE0, 0xFE, 0xC4, 0x13, 0x13,
++0x54, 0x03, 0x30, 0xE0, 0x02, 0x41, 0x5E, 0xEE,
++0x12, 0x8F, 0xCC, 0x30, 0xE0, 0x02, 0x41, 0x5E,
++0x90, 0x88, 0x39, 0xE0, 0xFE, 0x6F, 0x70, 0x02,
++0x41, 0x5E, 0xEF, 0x70, 0x02, 0x21, 0xBA, 0x24,
++0xFE, 0x70, 0x02, 0x21, 0xFF, 0x24, 0xFE, 0x60,
++0x4F, 0x24, 0xFC, 0x70, 0x02, 0x41, 0x44, 0x24,
++0xFC, 0x60, 0x02, 0x41, 0x57, 0xEE, 0xB4, 0x0E,
++0x03, 0x12, 0x71, 0x5F, 0x90, 0x88, 0x39, 0xE0,
++0x70, 0x05, 0x7F, 0x01, 0x12, 0x78, 0xC0, 0x90,
++0x88, 0x39, 0xE0, 0xB4, 0x06, 0x03, 0x12, 0x71,
++0x24, 0x90, 0x88, 0x39, 0xE0, 0xB4, 0x04, 0x11,
++0x90, 0x97, 0x10, 0xE0, 0xFF, 0x60, 0x05, 0x12,
++0x67, 0x80, 0x80, 0x05, 0x90, 0x8A, 0xED, 0x11,
++0xE2, 0x90, 0x88, 0x39, 0xE0, 0x64, 0x08, 0x60,
++0x02, 0x41, 0x57, 0x12, 0x7B, 0xCC, 0x41, 0x57,
++0x90, 0x88, 0x39, 0xE0, 0x70, 0x05, 0x7F, 0x01,
++0x12, 0x78, 0xC0, 0x90, 0x88, 0x39, 0xE0, 0xB4,
++0x06, 0x03, 0x12, 0x71, 0x24, 0x90, 0x88, 0x39,
++0xE0, 0xB4, 0x0E, 0x0B, 0x90, 0x86, 0x00, 0x11,
++0xE2, 0xBF, 0x01, 0x03, 0x12, 0x71, 0x5F, 0x90,
++0x88, 0x39, 0xE0, 0x64, 0x0C, 0x60, 0x02, 0x41,
++0x57, 0x90, 0x86, 0x00, 0x11, 0xE2, 0xEF, 0x64,
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++0x41, 0x57, 0x90, 0x88, 0x39, 0xE0, 0xB4, 0x0E,
++0x0B, 0x90, 0x86, 0x00, 0x11, 0xE2, 0xBF, 0x01,
++0x03, 0x12, 0x71, 0x5F, 0x90, 0x88, 0x39, 0xE0,
++0xB4, 0x06, 0x03, 0x12, 0x71, 0x24, 0x90, 0x88,
++0x39, 0xE0, 0xB4, 0x0C, 0x0B, 0x90, 0x86, 0x00,
++0x11, 0xE2, 0xBF, 0x01, 0x03, 0x12, 0x68, 0xC2,
++0x90, 0x88, 0x39, 0xE0, 0x64, 0x04, 0x70, 0x67,
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++0x70, 0x5D, 0x12, 0x73, 0x5A, 0x80, 0x58, 0x90,
++0x88, 0x39, 0xE0, 0xB4, 0x0E, 0x0B, 0x90, 0x86,
++0x00, 0x11, 0xE2, 0xBF, 0x01, 0x03, 0x12, 0x71,
++0x5F, 0x90, 0x88, 0x39, 0xE0, 0xB4, 0x06, 0x03,
++0x12, 0x71, 0x24, 0x90, 0x88, 0x39, 0xE0, 0xB4,
++0x0C, 0x0B, 0x90, 0x86, 0x00, 0x11, 0xE2, 0xBF,
++0x01, 0x03, 0x12, 0x68, 0xC2, 0x90, 0x88, 0x39,
++0xE0, 0x70, 0x05, 0x7F, 0x01, 0x12, 0x78, 0xC0,
++0x90, 0x88, 0x39, 0xE0, 0xB4, 0x04, 0x18, 0x12,
++0x7A, 0x49, 0x80, 0x13, 0x90, 0x88, 0x39, 0xE0,
++0xB4, 0x0C, 0x0C, 0x90, 0x88, 0x32, 0x12, 0x9F,
++0xBB, 0x30, 0xE0, 0x03, 0x12, 0x79, 0xD4, 0x90,
++0x88, 0x39, 0x12, 0xB0, 0xA1, 0xF0, 0xD0, 0xD0,
++0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3,
++0xC0, 0xD0, 0x11, 0xCD, 0x12, 0x02, 0x06, 0xFF,
++0x54, 0x01, 0xFE, 0x90, 0x88, 0x9D, 0x12, 0xE4,
++0x21, 0xF0, 0xFC, 0x12, 0x02, 0x06, 0xFD, 0x54,
++0x04, 0x13, 0x13, 0x54, 0x3F, 0xFF, 0x90, 0x94,
++0xA3, 0xE0, 0x54, 0xFE, 0x4F, 0xF0, 0xED, 0x54,
++0x08, 0xFF, 0xEC, 0x54, 0xF7, 0x4F, 0xFF, 0x90,
++0x88, 0x9D, 0xF0, 0x12, 0x02, 0x06, 0xFE, 0x54,
++0x10, 0xFD, 0xEF, 0x54, 0xEF, 0xB1, 0xCF, 0x54,
++0x20, 0xFE, 0xEF, 0x54, 0xDF, 0x4E, 0x12, 0x9F,
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++0xCF, 0xB1, 0xC7, 0xF0, 0x11, 0xD3, 0xE9, 0x24,
++0x01, 0xF9, 0xE4, 0x3A, 0x8B, 0x45, 0xF5, 0x46,
++0x89, 0x47, 0x75, 0x48, 0x04, 0x7B, 0x01, 0x7A,
++0x88, 0x79, 0x9E, 0x12, 0x69, 0xF5, 0x11, 0xD3,
++0x12, 0x87, 0x27, 0xFF, 0x54, 0x03, 0x90, 0x88,
++0x9F, 0xF0, 0xEF, 0x54, 0x04, 0x13, 0x13, 0x54,
++0x01, 0x25, 0xE0, 0x25, 0xE0, 0xFF, 0x90, 0x94,
++0xAF, 0xE0, 0x54, 0xFB, 0x4F, 0xFF, 0x12, 0x87,
++0x26, 0x54, 0x08, 0x13, 0x12, 0xBF, 0xDE, 0x33,
++0xB1, 0xC7, 0x90, 0x94, 0xAF, 0xF0, 0x11, 0xD3,
++0x12, 0x02, 0x06, 0x20, 0xE0, 0x02, 0x81, 0x48,
++0x90, 0x05, 0x54, 0xE0, 0x90, 0x88, 0xAE, 0xF0,
++0xE0, 0xC3, 0x13, 0x90, 0x88, 0xAD, 0xF0, 0x90,
++0x88, 0xA0, 0xE0, 0xC4, 0x54, 0x0F, 0x30, 0xE0,
++0x08, 0x12, 0x87, 0x9F, 0x90, 0x88, 0x9E, 0x80,
++0x23, 0x12, 0x87, 0x9F, 0xFF, 0xC3, 0x94, 0x2A,
++0x50, 0x15, 0xEF, 0xC3, 0x94, 0x03, 0x50, 0x07,
++0x90, 0x88, 0x9E, 0x74, 0x03, 0x80, 0x06, 0x12,
++0x87, 0x9F, 0x90, 0x88, 0x9E, 0x80, 0x05, 0x90,
++0x88, 0x9E, 0x74, 0x2A, 0xF0, 0x24, 0x0A, 0x90,
++0x88, 0xCF, 0xF0, 0x12, 0x8F, 0xBE, 0x30, 0xE0,
++0x27, 0xB1, 0xD7, 0x90, 0x88, 0xA6, 0xF0, 0xE0,
++0xC3, 0x13, 0xA3, 0xF0, 0xB1, 0xD7, 0x90, 0x88,
++0xA8, 0xB1, 0xBF, 0x90, 0x88, 0xA9, 0xB1, 0xBF,
++0x90, 0x88, 0xAA, 0xF0, 0x90, 0x01, 0x3E, 0x74,
++0x08, 0xF0, 0xFD, 0x7F, 0x02, 0x12, 0x7C, 0x05,
++0xE4, 0x90, 0x88, 0xDD, 0xF0, 0x12, 0x8F, 0xE4,
++0x30, 0xE0, 0x18, 0x12, 0x8F, 0xFB, 0x30, 0xE0,
++0x0D, 0x90, 0x8A, 0x89, 0x12, 0x8B, 0x03, 0x7D,
++0x04, 0x7F, 0x02, 0x12, 0x04, 0x7E, 0xB1, 0xB7,
++0x74, 0x11, 0xF0, 0x90, 0x94, 0xA3, 0xE0, 0x30,
++0xE0, 0x31, 0x90, 0x94, 0xAC, 0x74, 0x01, 0xF0,
++0xE4, 0xA3, 0xF0, 0x90, 0x06, 0xC7, 0xE0, 0xFE,
++0x90, 0x06, 0xC6, 0xF1, 0xCD, 0xFE, 0xE4, 0xFD,
++0x78, 0x10, 0x12, 0xC7, 0x5B, 0x90, 0x06, 0xC5,
++0xE0, 0xFE, 0x90, 0x06, 0xC4, 0xF1, 0xCD, 0xFE,
++0xE4, 0xFD, 0x12, 0x86, 0x54, 0x90, 0x94, 0xA8,
++0x12, 0x04, 0x31, 0x90, 0x94, 0xAF, 0xE0, 0x13,
++0x13, 0x54, 0x3F, 0x30, 0xE0, 0x13, 0xA3, 0xE0,
++0x20, 0xE0, 0x07, 0x54, 0x01, 0x44, 0x64, 0xF0,
++0x80, 0x07, 0x90, 0x94, 0xB0, 0xE0, 0x54, 0xFE,
++0xF0, 0x90, 0x05, 0x58, 0x74, 0x05, 0xF0, 0x90,
++0x88, 0xA5, 0xE0, 0xB4, 0x01, 0x08, 0x90, 0x88,
++0xB0, 0x74, 0x01, 0xF0, 0x80, 0x2B, 0x90, 0x88,
++0xA5, 0xE0, 0xB4, 0x04, 0x08, 0x90, 0x88, 0xB0,
++0x74, 0x04, 0xF0, 0x80, 0x1C, 0x90, 0x88, 0xA5,
++0xE0, 0xB4, 0x06, 0x08, 0x90, 0x88, 0xB0, 0x74,
++0x02, 0xF0, 0x80, 0x0D, 0x90, 0x88, 0xA5, 0xE0,
++0xB4, 0x07, 0x06, 0x90, 0x88, 0xB0, 0x74, 0x05,
++0xF0, 0xE4, 0x90, 0x88, 0xA5, 0xF0, 0x80, 0x3B,
++0x90, 0x8A, 0xF1, 0x11, 0xE2, 0x90, 0x89, 0x04,
++0xE0, 0x90, 0x00, 0x40, 0x30, 0xE0, 0x08, 0xE0,
++0x54, 0x0F, 0x44, 0xA0, 0xF0, 0x80, 0x06, 0xE0,
++0x54, 0x0F, 0x44, 0x20, 0xF0, 0x11, 0xD3, 0x12,
++0x87, 0x77, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x30,
++0xE0, 0x04, 0x7F, 0x03, 0x80, 0x02, 0x7F, 0x01,
++0x12, 0x71, 0x9A, 0x12, 0xAA, 0xB0, 0xB1, 0xB7,
++0x74, 0x43, 0xF0, 0x12, 0xE4, 0xC7, 0xE4, 0x90,
++0x88, 0xAF, 0xF0, 0x90, 0x88, 0xA0, 0x12, 0x8F,
++0xCB, 0x30, 0xE0, 0x09, 0x90, 0x88, 0xD0, 0xE0,
++0x44, 0x02, 0xF0, 0x80, 0x12, 0x90, 0x8A, 0x97,
++0x12, 0x8B, 0x03, 0x7F, 0x01, 0x12, 0x04, 0x7E,
++0x90, 0x88, 0xD0, 0xE0, 0x54, 0xFD, 0xF0, 0x90,
++0x8A, 0xD9, 0x12, 0x8B, 0x03, 0x7F, 0x03, 0x12,
++0x04, 0x7E, 0x12, 0x8F, 0xC8, 0x30, 0xE0, 0x0E,
++0x90, 0x01, 0x36, 0x74, 0x20, 0xF0, 0xFD, 0x7F,
++0x02, 0x12, 0x7C, 0x74, 0x80, 0x07, 0x7D, 0x20,
++0x7F, 0x02, 0x12, 0x7C, 0x7E, 0x12, 0x9F, 0xEE,
++0x90, 0x88, 0x9D, 0xE0, 0x20, 0xE0, 0x07, 0x90,
++0x88, 0xA1, 0xE0, 0x54, 0xBF, 0xF0, 0xF1, 0xBC,
++0xA3, 0xF0, 0xA3, 0x74, 0x01, 0xF0, 0xD0, 0xD0,
++0x92, 0xAF, 0x22, 0xE4, 0xFB, 0xFA, 0xFD, 0x7F,
++0x01, 0x12, 0x85, 0x4E, 0x90, 0x95, 0x42, 0xEF,
++0xF0, 0x60, 0xF0, 0x90, 0x86, 0xAF, 0xE0, 0xFF,
++0x70, 0x04, 0xA3, 0xE0, 0x60, 0xE5, 0xC2, 0xAF,
++0xEF, 0x30, 0xE0, 0x0F, 0x90, 0x86, 0xAF, 0xE0,
++0x54, 0xFE, 0xF0, 0xE4, 0xFF, 0x12, 0xB9, 0xE9,
++0x12, 0xD3, 0x66, 0xB1, 0x64, 0xE0, 0x30, 0xE1,
++0x08, 0x54, 0xFD, 0xF0, 0x90, 0x86, 0x08, 0x11,
++0xE2, 0xB1, 0x64, 0xE0, 0x30, 0xE2, 0x08, 0x54,
++0xFB, 0xF0, 0x90, 0x86, 0x0A, 0x11, 0xE2, 0xB1,
++0x64, 0xE0, 0xFF, 0x30, 0xE5, 0x0C, 0x54, 0xDF,
++0xF0, 0x12, 0xDE, 0x0E, 0xBF, 0x01, 0x03, 0x12,
++0xA0, 0xC4, 0xB1, 0x64, 0xE0, 0x30, 0xE6, 0x08,
++0x54, 0xBF, 0xF0, 0x90, 0x8A, 0x7D, 0x11, 0xE2,
++0xD2, 0xAF, 0x80, 0x9F, 0xD2, 0xAF, 0xC2, 0xAF,
++0x90, 0x86, 0xAF, 0x22, 0x7D, 0x01, 0xD3, 0x10,
++0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x96, 0xFF,
++0xEF, 0xF0, 0xA3, 0xED, 0xF0, 0x90, 0x8A, 0xF9,
++0x12, 0x8B, 0x03, 0x7D, 0x44, 0x7F, 0x6F, 0x12,
++0x04, 0x7E, 0x90, 0x8A, 0xFD, 0x11, 0xE2, 0x90,
++0x97, 0x00, 0xE0, 0x90, 0x96, 0xFF, 0xB4, 0x01,
++0x09, 0xE0, 0xB1, 0xE2, 0xE0, 0x44, 0x04, 0xF0,
++0x80, 0x07, 0xE0, 0xB1, 0xE2, 0xE0, 0x54, 0xFB,
++0xF0, 0x90, 0x8A, 0xF9, 0x12, 0x8B, 0x03, 0x12,
++0x8F, 0xF5, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90,
++0x05, 0x00, 0x74, 0x1C, 0xF0, 0xA3, 0x22, 0xF0,
++0x90, 0x88, 0x9E, 0xE0, 0xC3, 0x13, 0x22, 0x54,
++0x80, 0xFE, 0xEF, 0x54, 0x7F, 0x4E, 0x22, 0x4D,
++0xFF, 0x90, 0x88, 0x9D, 0xF0, 0xEE, 0x22, 0x90,
++0x88, 0x9E, 0xE0, 0x75, 0xF0, 0x03, 0x84, 0x22,
++0xE5, 0x62, 0xC4, 0x54, 0xF0, 0x24, 0x05, 0xF5,
++0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0x22, 0x8D,
++0x0E, 0xEF, 0x30, 0xE6, 0x19, 0xE5, 0x0E, 0xD1,
++0xD1, 0xE0, 0xFD, 0xE5, 0x0E, 0xB1, 0xE2, 0xD1,
++0xDE, 0xE4, 0xFB, 0xAF, 0x0E, 0x12, 0x75, 0x80,
++0xD1, 0xC5, 0xE4, 0xF0, 0x80, 0x4E, 0xD1, 0xC5,
++0xE0, 0x04, 0xF0, 0xD1, 0xC5, 0xE0, 0x64, 0x02,
++0x70, 0x16, 0x74, 0x29, 0x25, 0x0E, 0x12, 0xBF,
++0x97, 0xE0, 0xFD, 0xF4, 0x60, 0x02, 0x80, 0x27,
++0xE5, 0x0E, 0xD1, 0xD1, 0xE0, 0xFD, 0x80, 0x1F,
++0xD1, 0xC5, 0xE0, 0xD3, 0x94, 0x03, 0x40, 0x11,
++0x90, 0x8A, 0xB3, 0x12, 0x8B, 0x03, 0xAF, 0x0E,
++0x12, 0x04, 0x7E, 0xD1, 0xC5, 0xE4, 0xF0, 0x80,
++0x13, 0xE5, 0x0E, 0xD1, 0xD1, 0xE0, 0xFD, 0xE5,
++0x0E, 0xB1, 0xE2, 0xD1, 0xDE, 0x7B, 0x01, 0xAF,
++0x0E, 0x12, 0x75, 0x80, 0xE5, 0x0E, 0xD1, 0xD1,
++0xE0, 0xFD, 0x90, 0x96, 0x41, 0x74, 0x05, 0xF0,
++0xE4, 0xFB, 0xAF, 0x0E, 0xD3, 0x10, 0xAF, 0x01,
++0xC3, 0xC0, 0xD0, 0x90, 0x96, 0x44, 0xED, 0xF0,
++0xA3, 0xEF, 0xF0, 0xA3, 0xEB, 0xF0, 0x90, 0x96,
++0x41, 0xE0, 0x90, 0x96, 0x47, 0xF0, 0xE4, 0xA3,
++0xF0, 0xEF, 0x12, 0xD3, 0x22, 0x34, 0x8D, 0xF5,
++0x83, 0xA3, 0xE0, 0x90, 0x96, 0x49, 0xF0, 0x74,
++0x46, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x8E, 0xF5,
++0x83, 0xE0, 0x90, 0x96, 0x4A, 0xF0, 0x90, 0x96,
++0x42, 0x74, 0x0C, 0xF0, 0x90, 0x96, 0x64, 0x74,
++0x07, 0xF0, 0x7B, 0x01, 0x7A, 0x96, 0x79, 0x42,
++0x12, 0x8A, 0xF1, 0x7F, 0x04, 0x12, 0x04, 0x7E,
++0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x74, 0xB6, 0x25,
++0x0E, 0xF5, 0x82, 0xE4, 0x34, 0x8E, 0xF5, 0x83,
++0x22, 0xC4, 0x54, 0xF0, 0x24, 0x00, 0xF5, 0x82,
++0xE4, 0x34, 0x81, 0xF5, 0x83, 0x22, 0xE0, 0x54,
++0x03, 0x90, 0x92, 0x80, 0xF0, 0x22, 0x90, 0x88,
++0xB8, 0xE0, 0x30, 0xE0, 0x05, 0x90, 0x8A, 0xEB,
++0x80, 0x27, 0x90, 0x94, 0xAF, 0xF1, 0x30, 0x30,
++0xE0, 0x1C, 0x90, 0x88, 0xC2, 0xE0, 0xC4, 0x54,
++0x0F, 0x20, 0xE0, 0x09, 0x90, 0x8A, 0xBB, 0x12,
++0x8B, 0x03, 0x12, 0xB3, 0x49, 0x90, 0x94, 0xAF,
++0xE0, 0x54, 0xF7, 0xF0, 0x80, 0x05, 0x90, 0x8A,
++0x99, 0x11, 0xE2, 0x90, 0x88, 0xF0, 0xE0, 0x30,
++0xE0, 0x05, 0x90, 0x8A, 0xE7, 0x11, 0xE2, 0x22,
++0xE4, 0x90, 0x92, 0x20, 0xF0, 0x90, 0x88, 0x3E,
++0xE0, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x22, 0xE4,
++0xF5, 0x77, 0x90, 0x88, 0x36, 0xE0, 0x60, 0x54,
++0x12, 0xB6, 0xD4, 0x70, 0x4F, 0x12, 0xE3, 0x97,
++0x75, 0x77, 0x01, 0xE5, 0x77, 0x60, 0x45, 0x90,
++0x88, 0x39, 0xE0, 0x20, 0xE2, 0x0D, 0x90, 0x8A,
++0xB9, 0x12, 0x8B, 0x03, 0x7D, 0x01, 0x7F, 0x04,
++0x12, 0x04, 0x7E, 0x12, 0xB7, 0x7C, 0x90, 0x88,
++0x3F, 0xE0, 0x60, 0x04, 0x64, 0x01, 0x70, 0x0F,
++0xF1, 0x28, 0xFF, 0xA3, 0xE0, 0x2F, 0xF1, 0xA9,
++0xF1, 0x2D, 0xFF, 0xA3, 0xE0, 0x80, 0x0B, 0xF1,
++0x28, 0xF1, 0x95, 0x2F, 0xF1, 0xA9, 0xF1, 0x2D,
++0xF1, 0x95, 0x2F, 0x33, 0x33, 0x33, 0x54, 0xF8,
++0x90, 0x88, 0x4F, 0xF0, 0x22, 0xFF, 0xA3, 0xE0,
++0x75, 0xF0, 0x03, 0xA4, 0x24, 0xFE, 0x22, 0xF0,
++0xE4, 0x90, 0x92, 0x20, 0xF0, 0x90, 0x88, 0x94,
++0xE0, 0x90, 0x92, 0x21, 0xF0, 0xE4, 0xFB, 0xFD,
++0x7F, 0x54, 0x7E, 0x01, 0x02, 0x66, 0x33, 0xE4,
++0xFD, 0xA1, 0x6E, 0xF0, 0x90, 0x94, 0xBB, 0xE0,
++0x13, 0x13, 0x54, 0x3F, 0x22, 0x90, 0x00, 0xAB,
++0xE0, 0xFE, 0x90, 0x00, 0xAA, 0xE0, 0x7C, 0x00,
++0x24, 0x00, 0xFF, 0xEC, 0x3E, 0x22, 0xF1, 0x37,
++0xE4, 0xFF, 0x12, 0xB3, 0x7A, 0x90, 0x93, 0x03,
++0xE0, 0x30, 0xE0, 0x03, 0x12, 0xDE, 0xA6, 0x90,
++0x8B, 0x07, 0x11, 0xE2, 0x90, 0x93, 0x2A, 0xE0,
++0x30, 0xE0, 0x1D, 0x90, 0x01, 0x57, 0xE4, 0xF0,
++0x90, 0x8A, 0xF9, 0x12, 0x8B, 0x03, 0x12, 0x90,
++0xD9, 0x11, 0xE5, 0x30, 0xE0, 0x08, 0x90, 0x8A,
++0x89, 0x12, 0x8B, 0x03, 0x11, 0x11, 0x11, 0xEC,
++0x22, 0x7D, 0x0C, 0x7F, 0x01, 0x02, 0x04, 0x7E,
++0x90, 0x94, 0xC0, 0xF1, 0xB5, 0xFF, 0x54, 0x01,
++0xFE, 0x90, 0x93, 0x2A, 0x12, 0xE4, 0x21, 0xF1,
++0xC2, 0x54, 0x04, 0xFD, 0xEF, 0x54, 0xFB, 0x4D,
++0xFF, 0x90, 0x93, 0x2A, 0xF0, 0xEE, 0x54, 0x08,
++0xFE, 0xEF, 0x54, 0xF7, 0x4E, 0xF0, 0x90, 0x05,
++0x52, 0xE0, 0x54, 0x07, 0x90, 0x94, 0xC0, 0x60,
++0x13, 0x12, 0x87, 0x9D, 0xFD, 0x90, 0x05, 0x56,
++0xE0, 0xC3, 0x9D, 0x90, 0x93, 0x2C, 0xF0, 0xA3,
++0xED, 0xF0, 0x80, 0x23, 0x12, 0x87, 0x9D, 0xFB,
++0xFF, 0x90, 0x05, 0x54, 0xE0, 0xC3, 0x9F, 0xFF,
++0xE4, 0x94, 0x00, 0xFE, 0x7C, 0x00, 0x7D, 0x05,
++0x12, 0x02, 0x92, 0x90, 0x93, 0x2C, 0xEF, 0xF0,
++0xEB, 0x75, 0xF0, 0x05, 0x84, 0xA3, 0xF0, 0x12,
++0x90, 0xD3, 0x12, 0x02, 0x06, 0x20, 0xE0, 0x13,
++0x12, 0x90, 0xDF, 0x90, 0x8A, 0xF9, 0x12, 0x8B,
++0x03, 0x12, 0x8F, 0xF5, 0x90, 0x01, 0x57, 0xE4,
++0xF0, 0x80, 0x0A, 0x90, 0x8A, 0x89, 0x12, 0x8B,
++0x03, 0x11, 0x11, 0x11, 0xEC, 0x31, 0x1B, 0x20,
++0xE0, 0x04, 0xEF, 0x44, 0x20, 0xF0, 0x11, 0xE5,
++0x30, 0xE0, 0x1A, 0x90, 0x88, 0x36, 0x74, 0x01,
++0xF0, 0xE4, 0x90, 0x88, 0x38, 0xF0, 0x90, 0x88,
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++0xE0, 0xC3, 0x13, 0x22, 0x90, 0x93, 0x2A, 0xE0,
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++0xE3, 0x5B, 0x22, 0x90, 0x93, 0x2A, 0xE0, 0xFF,
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++0x32, 0x31, 0x1E, 0x30, 0xE0, 0x10, 0xEF, 0xC4,
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++0x02, 0x7F, 0x02, 0x12, 0x7C, 0x7E, 0x90, 0x88,
++0x31, 0xF1, 0xBB, 0x30, 0xE0, 0x08, 0xEF, 0x12,
++0xB7, 0xAB, 0x70, 0x4C, 0x80, 0x48, 0x90, 0x88,
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++0x12, 0x8B, 0x03, 0x7D, 0x0C, 0x7F, 0x02, 0x12,
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++0x11, 0x11, 0x90, 0x86, 0xB3, 0xE0, 0xFF, 0xB4,
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++0xA3, 0x74, 0x0F, 0xF0, 0xA3, 0xE0, 0x54, 0x01,
++0x44, 0x28, 0xF0, 0xA3, 0x74, 0x07, 0xF0, 0x7E,
++0x00, 0x7F, 0x18, 0x7D, 0x00, 0x7B, 0x01, 0x7A,
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++0x7E, 0x7E, 0x00, 0x7F, 0x02, 0x7D, 0x00, 0x7B,
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++0x9C, 0xF0, 0x22, 0xF1, 0xAF, 0x12, 0x7B, 0xDB,
++0x90, 0x8A, 0xC5, 0x12, 0x90, 0xE2, 0x91, 0x2B,
++0x71, 0xF3, 0x31, 0xA1, 0x51, 0xC3, 0x91, 0x0E,
++0x90, 0x8A, 0x73, 0x12, 0x90, 0xE2, 0x90, 0x00,
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++0xFB, 0xFD, 0x7F, 0x68, 0x7E, 0x01, 0x12, 0x66,
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++0xF0, 0x54, 0xEF, 0xF0, 0x44, 0x08, 0xF0, 0x90,
++0x86, 0xB3, 0xE0, 0xFF, 0x64, 0x02, 0x70, 0x29,
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++0xF0, 0x7E, 0x00, 0x7F, 0x1B, 0x7D, 0x00, 0x7B,
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++0x12, 0x86, 0x76, 0x7A, 0x80, 0x79, 0xBF, 0x90,
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++0x04, 0xF0, 0x80, 0xEB, 0x22, 0x90, 0x00, 0x80,
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++0xE0, 0x44, 0x40, 0xF0, 0x75, 0x20, 0xFF, 0x12,
++0x7C, 0x97, 0x53, 0xA8, 0xFE, 0x90, 0x01, 0xA0,
++0xE0, 0xB4, 0xFD, 0x04, 0xE4, 0xFF, 0xB1, 0x20,
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++0x04, 0xF0, 0x12, 0xC7, 0xF3, 0x12, 0xD0, 0x10,
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++0x74, 0xFF, 0xF0, 0xE4, 0xFF, 0x02, 0x84, 0x9E,
++0x90, 0x94, 0xC0, 0xEF, 0xF1, 0x9C, 0x7F, 0xF4,
++0x7E, 0x01, 0x12, 0x5F, 0xA6, 0xBF, 0x01, 0x08,
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++0xF1, 0x9D, 0x7F, 0xF5, 0x7E, 0x01, 0x12, 0x5F,
++0xA6, 0xBF, 0x01, 0x08, 0x90, 0x95, 0x07, 0xE0,
++0x90, 0x95, 0x0A, 0xF0, 0xF1, 0x9D, 0x7F, 0xF6,
++0x7E, 0x01, 0x12, 0x5F, 0xA6, 0xBF, 0x01, 0x08,
++0x90, 0x95, 0x07, 0xE0, 0x90, 0x95, 0x0B, 0xF0,
++0xF1, 0x9D, 0x7F, 0xF7, 0x7E, 0x01, 0x12, 0x5F,
++0xA6, 0xBF, 0x01, 0x08, 0x90, 0x95, 0x07, 0xE0,
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++0x9D, 0xF1, 0xA4, 0x70, 0x52, 0x90, 0x95, 0x07,
++0xE0, 0x90, 0x95, 0x0F, 0xF0, 0x54, 0x07, 0x60,
++0x08, 0x90, 0x95, 0x07, 0xE0, 0x54, 0xE0, 0x70,
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++0xE0, 0xFF, 0x90, 0x95, 0x08, 0xE0, 0x54, 0xE0,
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++0x9D, 0x7F, 0xFD, 0xF1, 0xA6, 0x70, 0x47, 0x90,
++0x95, 0x07, 0xE0, 0xFE, 0x54, 0xCC, 0x90, 0x95,
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++0xEF, 0x70, 0x12, 0x90, 0x95, 0x10, 0xE0, 0xFF,
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++0x25, 0xE0, 0xFF, 0xEE, 0x4F, 0xF0, 0xF1, 0x9D,
++0x7F, 0xF0, 0x7E, 0x01, 0x12, 0x5F, 0xA6, 0xBF,
++0x01, 0x08, 0x90, 0x95, 0x07, 0xE0, 0x90, 0x95,
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++0x7F, 0xF2, 0x7E, 0x01, 0x12, 0x5F, 0xA6, 0xBF,
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++0x7F, 0xFC, 0x7E, 0x01, 0x12, 0x5F, 0xA6, 0xBF,
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++0x0F, 0xE0, 0x90, 0x94, 0xC9, 0xF0, 0x90, 0x95,
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++0xE4, 0x74, 0x1A, 0xF0, 0x90, 0x95, 0x06, 0x74,
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++0xE6, 0xF0, 0x90, 0x95, 0x12, 0xE0, 0x90, 0x94,
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++0xE9, 0xF0, 0x90, 0x95, 0x15, 0xE0, 0x90, 0x94,
++0xEA, 0xF0, 0x90, 0x00, 0x35, 0xE0, 0x54, 0xFC,
++0x44, 0x01, 0xF1, 0x9C, 0x7F, 0x6F, 0x7E, 0x00,
++0x12, 0x5F, 0xA6, 0xBF, 0x01, 0x08, 0x90, 0x95,
++0x07, 0xE0, 0x90, 0x95, 0x16, 0xF0, 0x90, 0x00,
++0x35, 0xE0, 0x54, 0xFC, 0xF0, 0x90, 0x94, 0xC0,
++0xE0, 0xB4, 0x01, 0x17, 0x7B, 0x01, 0x7A, 0x94,
++0x79, 0xC1, 0x12, 0xB7, 0xB8, 0x7B, 0x01, 0x7A,
++0x94, 0x79, 0xE4, 0x12, 0x8A, 0xF1, 0x7F, 0x04,
++0x02, 0x04, 0x7E, 0x75, 0x45, 0x01, 0x75, 0x46,
++0x94, 0x75, 0x47, 0xC3, 0x75, 0x48, 0x08, 0x7B,
++0x01, 0x7A, 0x01, 0x79, 0xA2, 0x12, 0x69, 0xF5,
++0x75, 0x45, 0x01, 0x75, 0x46, 0x94, 0x75, 0x47,
++0xE6, 0x75, 0x48, 0x05, 0x7B, 0x01, 0x7A, 0x01,
++0x79, 0xAA, 0x12, 0x69, 0xF5, 0x90, 0x95, 0x16,
++0xE0, 0x90, 0x01, 0xA1, 0xF0, 0x90, 0x01, 0xA0,
++0x74, 0x19, 0xF0, 0x22, 0xF0, 0x7B, 0x01, 0x7A,
++0x95, 0x79, 0x07, 0x22, 0x7F, 0xFB, 0x7E, 0x01,
++0x12, 0x5F, 0xA6, 0xEF, 0x64, 0x01, 0x22, 0xE4,
++0xFD, 0xFF, 0x02, 0x6E, 0x71, 0x12, 0x86, 0x76,
++0x02, 0x02, 0x06, 0xE0, 0xFF, 0x13, 0x13, 0x54,
++0x3F, 0x22, 0xFF, 0xF0, 0x12, 0x02, 0x06, 0xFE,
++0x22, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xF0, 0x22,
++0xE0, 0x54, 0xFE, 0xF0, 0x54, 0xFD, 0x22, 0x7F,
++0xF9, 0x7E, 0x01, 0x02, 0x5F, 0xA6, 0x12, 0x8F,
++0xD3, 0x7D, 0x01, 0x02, 0x04, 0x7E, 0xF0, 0x90,
++0x88, 0x34, 0xE0, 0x54, 0x0F, 0x22, 0x90, 0x06,
++0x04, 0xE0, 0x54, 0x7F, 0xF0, 0x22, 0x90, 0x94,
++0xC0, 0xF1, 0xB5, 0x30, 0xE0, 0x14, 0x12, 0xDE,
++0x65, 0x90, 0x86, 0xB3, 0xE0, 0x64, 0x01, 0x70,
++0x27, 0x90, 0xFE, 0x10, 0xE0, 0x44, 0x04, 0xF0,
++0x80, 0x1E, 0x90, 0x93, 0x26, 0xE0, 0x60, 0x16,
++0x7D, 0x10, 0xE4, 0xFF, 0x12, 0x7C, 0x3B, 0x90,
++0x01, 0x3C, 0xE0, 0x30, 0xE4, 0x03, 0x74, 0x10,
++0xF0, 0x90, 0x01, 0x63, 0xE4, 0xF0, 0x11, 0xA5,
++0x12, 0x90, 0xD3, 0x12, 0x87, 0x9F, 0x90, 0x93,
++0x04, 0x12, 0x87, 0x26, 0x90, 0x93, 0x05, 0xF0,
++0x90, 0x93, 0x04, 0xE0, 0x54, 0x01, 0x90, 0x93,
++0x12, 0xF0, 0x90, 0x93, 0x04, 0xE0, 0x54, 0x02,
++0x90, 0x93, 0x13, 0xF0, 0x90, 0x93, 0x04, 0xE0,
++0x54, 0x04, 0x90, 0x93, 0x14, 0xF0, 0x90, 0x93,
++0x04, 0xE0, 0x54, 0x08, 0x90, 0x93, 0x15, 0xF0,
++0x90, 0x93, 0x04, 0xE0, 0x54, 0x10, 0x90, 0x93,
++0x16, 0xF0, 0x90, 0x93, 0x05, 0xE0, 0x54, 0x01,
++0x90, 0x93, 0x17, 0xF0, 0x90, 0x93, 0x05, 0xE0,
++0x54, 0x02, 0x90, 0x93, 0x18, 0xF0, 0x90, 0x93,
++0x05, 0xE0, 0x54, 0x04, 0x90, 0x93, 0x19, 0xF0,
++0x90, 0x93, 0x05, 0xE0, 0x54, 0x08, 0x90, 0x93,
++0x1A, 0xF0, 0x90, 0x93, 0x05, 0xE0, 0x54, 0x10,
++0x90, 0x93, 0x1B, 0xF0, 0x22, 0xD3, 0x10, 0xAF,
++0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x93, 0x03, 0xE0,
++0xFE, 0xEE, 0x54, 0xFE, 0xF0, 0x12, 0xDD, 0x80,
++0xE4, 0x90, 0x93, 0x10, 0xF0, 0xA3, 0xF0, 0xD0,
++0xD0, 0x92, 0xAF, 0x22, 0x90, 0x93, 0x21, 0xE0,
++0x90, 0x95, 0xA6, 0xF0, 0x90, 0x93, 0x22, 0xE0,
++0x90, 0x95, 0xA7, 0xF0, 0x90, 0x93, 0x23, 0xE0,
++0x90, 0x95, 0xA8, 0xF0, 0x90, 0x93, 0x24, 0xE0,
++0x90, 0x95, 0xA9, 0xF0, 0x90, 0x93, 0x25, 0xE0,
++0x90, 0x95, 0xAA, 0xF0, 0x90, 0x93, 0x12, 0xE0,
++0x90, 0x95, 0xAB, 0xF0, 0x90, 0x93, 0x13, 0xE0,
++0x90, 0x95, 0xAC, 0xF0, 0x90, 0x93, 0x14, 0xE0,
++0x90, 0x95, 0xAD, 0xF0, 0x90, 0x93, 0x15, 0xE0,
++0x90, 0x95, 0xAE, 0xF0, 0x90, 0x93, 0x16, 0xE0,
++0x90, 0x95, 0xAF, 0xF0, 0x90, 0x93, 0x17, 0xE0,
++0x90, 0x95, 0xB0, 0xF0, 0x90, 0x93, 0x18, 0xE0,
++0x90, 0x95, 0xB1, 0xF0, 0x90, 0x93, 0x19, 0xE0,
++0x90, 0x95, 0xB2, 0xF0, 0x90, 0x93, 0x1A, 0xE0,
++0x90, 0x95, 0xB3, 0xF0, 0x90, 0x93, 0x1B, 0xE0,
++0x90, 0x95, 0xB4, 0xF0, 0xD1, 0x39, 0x90, 0x95,
++0x4E, 0xF0, 0xB1, 0xD1, 0x50, 0x09, 0xD1, 0x0F,
++0x74, 0x01, 0xF0, 0xB1, 0xCA, 0x80, 0xF3, 0x90,
++0x93, 0x03, 0xE0, 0xC4, 0x13, 0x54, 0x07, 0x30,
++0xE0, 0x12, 0x90, 0x01, 0x02, 0xE0, 0x54, 0x0C,
++0xFF, 0xBF, 0x08, 0x08, 0x90, 0x95, 0xC4, 0x74,
++0x01, 0xF0, 0x80, 0x05, 0xE4, 0x90, 0x95, 0xC4,
++0xF0, 0x90, 0x01, 0x1F, 0xE0, 0xFE, 0x90, 0x01,
++0x1E, 0x12, 0x97, 0xCD, 0x90, 0x95, 0x43, 0xF0,
++0xA3, 0xF1, 0xE8, 0xB1, 0xD1, 0x50, 0x4C, 0xB1,
++0xF7, 0x90, 0x95, 0x4E, 0xE0, 0xFE, 0x24, 0xB5,
++0xF5, 0x82, 0xE4, 0x34, 0x95, 0xD1, 0x1A, 0xE0,
++0x24, 0x4D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5,
++0x83, 0xE0, 0xFF, 0x74, 0x50, 0x2E, 0xF5, 0x82,
++0xE4, 0x34, 0x95, 0xD1, 0x1A, 0xE0, 0x24, 0x4E,
++0xF9, 0xE4, 0x34, 0xFC, 0xFA, 0x7B, 0x01, 0xEE,
++0x12, 0xE4, 0x3E, 0x12, 0x86, 0x76, 0xD1, 0x1E,
++0xE0, 0x24, 0x38, 0xF9, 0xE4, 0x34, 0xFC, 0xFA,
++0xEE, 0x12, 0xE4, 0x30, 0x12, 0x86, 0x76, 0xB1,
++0xCA, 0x80, 0xB0, 0x90, 0x02, 0x87, 0xE0, 0x70,
++0x02, 0xA1, 0xAA, 0x90, 0x93, 0x03, 0xE0, 0x20,
++0xE0, 0x02, 0xA1, 0xAA, 0xE4, 0x90, 0x95, 0xBF,
++0xD1, 0x41, 0x90, 0x95, 0x43, 0xE0, 0xFF, 0xA3,
++0xE0, 0xA3, 0xCF, 0xF0, 0xA3, 0xEF, 0xF0, 0x90,
++0x95, 0x45, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0xEC,
++0x90, 0xFD, 0x11, 0xF0, 0x74, 0x01, 0x2D, 0xF5,
++0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFE,
++0x74, 0x00, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFB,
++0xF5, 0x83, 0xE0, 0x7A, 0x00, 0x24, 0x00, 0xFF,
++0xEA, 0x3E, 0x54, 0x3F, 0x90, 0x95, 0x47, 0xF0,
++0xA3, 0xEF, 0xF0, 0x74, 0x02, 0x2D, 0xF5, 0x82,
++0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x54, 0x0F,
++0x33, 0x33, 0x33, 0x54, 0xF8, 0x90, 0x95, 0x4A,
++0xF0, 0xFC, 0x74, 0x07, 0x2D, 0xF5, 0x82, 0xE4,
++0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x54, 0xC0, 0x90,
++0x95, 0x4C, 0xF0, 0xEC, 0x24, 0x18, 0x90, 0x95,
++0x49, 0xF0, 0xFD, 0x90, 0x95, 0x45, 0xE0, 0xFE,
++0xA3, 0xE0, 0xFF, 0xB1, 0xAF, 0xEF, 0x54, 0xFC,
++0x90, 0x95, 0x4B, 0xF0, 0x90, 0x95, 0x4A, 0xE0,
++0x24, 0x18, 0xFF, 0xE4, 0x33, 0x90, 0x95, 0x47,
++0x8F, 0xF0, 0x12, 0x02, 0xE7, 0x90, 0x95, 0x47,
++0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x12, 0xDE, 0x43,
++0x90, 0x95, 0x43, 0xEE, 0x8F, 0xF0, 0x12, 0x02,
++0xE7, 0x90, 0x88, 0x27, 0xE0, 0xFE, 0xA3, 0xE0,
++0xFF, 0x90, 0x95, 0x43, 0x12, 0xE3, 0xD9, 0x9E,
++0x40, 0x1B, 0x90, 0x88, 0x28, 0xE0, 0x24, 0x01,
++0xFF, 0x90, 0x88, 0x27, 0xE0, 0x34, 0x00, 0xFE,
++0xC3, 0xED, 0x9F, 0xFF, 0xEC, 0x9E, 0x90, 0x95,
++0x43, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x95, 0x4B,
++0xE0, 0x24, 0xC0, 0x60, 0x02, 0x81, 0xAB, 0xB1,
++0xBE, 0xE0, 0x24, 0x18, 0xB1, 0xAE, 0xEF, 0x60,
++0x02, 0x81, 0x9D, 0xB1, 0xBE, 0xE0, 0x24, 0x19,
++0xB1, 0xAE, 0x90, 0x95, 0x64, 0x12, 0xE4, 0xB8,
++0x90, 0x95, 0x64, 0xE0, 0xFF, 0x90, 0x95, 0x4D,
++0xE0, 0xFD, 0xC3, 0x9F, 0x50, 0x16, 0xB1, 0xBE,
++0xE0, 0x24, 0x1A, 0xB1, 0xAB, 0x90, 0x95, 0x4D,
++0xE0, 0x24, 0x65, 0xF5, 0x82, 0xE4, 0x34, 0x95,
++0xB1, 0xEC, 0x80, 0xDC, 0x90, 0x95, 0x64, 0xE0,
++0x70, 0x02, 0x61, 0xCD, 0xE4, 0x90, 0x95, 0x4E,
++0xF0, 0xB1, 0xD1, 0x40, 0x02, 0x61, 0xB5, 0xB1,
++0xF7, 0x90, 0x95, 0x4E, 0xE0, 0xFF, 0x24, 0x50,
++0xF5, 0x82, 0xE4, 0x34, 0x95, 0xF5, 0x83, 0xE0,
++0xFE, 0x90, 0x95, 0x64, 0xE0, 0xFD, 0xEE, 0x6D,
++0x70, 0x1E, 0xEF, 0x12, 0xE4, 0x3E, 0x12, 0x86,
++0x6D, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0xD1,
++0x29, 0xED, 0xF0, 0xD0, 0x01, 0xD0, 0x02, 0xD0,
++0x03, 0xD1, 0x4B, 0xEF, 0x60, 0x02, 0x80, 0x48,
++0x90, 0x95, 0x64, 0xE0, 0x64, 0x03, 0x70, 0x4F,
++0xD1, 0x29, 0x74, 0x03, 0xF0, 0x7A, 0x96, 0x79,
++0xCA, 0xD1, 0x4B, 0xEF, 0x70, 0x0E, 0xD1, 0x29,
++0x74, 0x03, 0xF0, 0x7A, 0x96, 0x79, 0xC6, 0xD1,
++0x4B, 0xEF, 0x60, 0x2B, 0x90, 0x95, 0x4E, 0xE0,
++0xFF, 0x24, 0xB0, 0xF5, 0x82, 0xE4, 0x34, 0x95,
++0xF5, 0x83, 0xE0, 0x60, 0x02, 0x80, 0x0C, 0x90,
++0x95, 0x4E, 0xE0, 0xFF, 0x24, 0xAB, 0x12, 0xE4,
++0x97, 0x60, 0x05, 0x74, 0xBF, 0x2F, 0x80, 0x15,
++0xB1, 0xDE, 0x74, 0x01, 0xF0, 0x80, 0x12, 0x90,
++0x95, 0x4E, 0xE0, 0x24, 0xBF, 0x80, 0x06, 0x90,
++0x95, 0x4E, 0xE0, 0x24, 0xBF, 0xB1, 0xE4, 0xE4,
++0xF0, 0xB1, 0xCA, 0x61, 0x11, 0x90, 0x95, 0xBF,
++0xE0, 0x70, 0x50, 0xA3, 0xE0, 0x70, 0x4C, 0xA3,
++0xE0, 0x70, 0x48, 0xA3, 0xE0, 0x70, 0x44, 0xA3,
++0xE0, 0x70, 0x40, 0x81, 0x9D, 0xE4, 0x90, 0x95,
++0x4E, 0xF0, 0xB1, 0xD1, 0x50, 0x1D, 0x74, 0xAB,
++0x2E, 0x12, 0xE4, 0x97, 0x60, 0x09, 0x74, 0xBF,
++0x2E, 0xB1, 0xE4, 0xE4, 0xF0, 0x80, 0x08, 0x74,
++0xBF, 0x2E, 0xB1, 0xE4, 0x74, 0x01, 0xF0, 0xB1,
++0xCA, 0x80, 0xDF, 0x90, 0x95, 0xBF, 0xE0, 0x70,
++0x12, 0xA3, 0xE0, 0x70, 0x0E, 0xA3, 0xE0, 0x70,
++0x0A, 0xA3, 0xE0, 0x70, 0x06, 0xA3, 0xE0, 0x70,
++0x02, 0x81, 0x9D, 0xE4, 0x90, 0x95, 0x4E, 0xF0,
++0xB1, 0xD1, 0x40, 0x02, 0x81, 0x9D, 0xB1, 0xF7,
++0xB1, 0xDE, 0xE0, 0x60, 0x7C, 0x90, 0x93, 0x2A,
++0xE0, 0x30, 0xE0, 0x06, 0xC4, 0x54, 0x0F, 0x30,
++0xE0, 0x6F, 0xE4, 0xFF, 0xFE, 0x90, 0x04, 0x1D,
++0xE0, 0x60, 0x10, 0xD3, 0xEF, 0x94, 0xE8, 0xEE,
++0x94, 0x03, 0x50, 0x07, 0x0F, 0xBF, 0x00, 0x01,
++0x0E, 0x80, 0xEA, 0x90, 0x04, 0x1D, 0xE0, 0x70,
++0x50, 0x90, 0x95, 0x4E, 0xE0, 0x24, 0xA6, 0xF5,
++0x82, 0xE4, 0x34, 0x95, 0xF5, 0x83, 0xE0, 0xFF,
++0x90, 0x92, 0x13, 0x74, 0x06, 0xF0, 0x7B, 0x08,
++0x7D, 0x01, 0x12, 0x66, 0xDB, 0x90, 0x95, 0x47,
++0xEE, 0xF0, 0xA3, 0x12, 0xE4, 0xB8, 0xD1, 0x06,
++0x50, 0x1D, 0xB1, 0xBE, 0xE0, 0x24, 0x0A, 0xB1,
++0xAB, 0x90, 0x95, 0x47, 0xA3, 0xE0, 0xFE, 0x90,
++0x95, 0x4D, 0xE0, 0x2E, 0x24, 0x2C, 0xF5, 0x82,
++0xE4, 0x34, 0xFC, 0xB1, 0xEC, 0x80, 0xDF, 0x90,
++0x04, 0x1F, 0x74, 0x20, 0xF0, 0x90, 0x06, 0x35,
++0xF0, 0xB1, 0xCA, 0x81, 0x10, 0x12, 0xE4, 0x8E,
++0x12, 0xDE, 0x00, 0x90, 0x06, 0x36, 0x74, 0xDD,
++0xF0, 0x21, 0xD3, 0x90, 0x95, 0x4C, 0xE0, 0x60,
++0x02, 0xA1, 0xA2, 0xB1, 0xBE, 0xE0, 0x24, 0x16,
++0xB1, 0xAE, 0x90, 0x06, 0x34, 0xEF, 0xF0, 0xB1,
++0xBE, 0xE0, 0x24, 0x17, 0xB1, 0xAE, 0x90, 0x06,
++0x37, 0xF1, 0xE8, 0xB1, 0xD1, 0x50, 0x37, 0xB1,
++0xF7, 0xE4, 0x90, 0x95, 0x4D, 0xF0, 0xD1, 0x06,
++0x50, 0x28, 0xB1, 0xBE, 0xE0, 0x24, 0x04, 0x2D,
++0xB1, 0xAE, 0x90, 0x95, 0x4E, 0xE0, 0xFE, 0x12,
++0xE4, 0x30, 0x12, 0x86, 0x6D, 0x90, 0x95, 0x4D,
++0xE0, 0xF5, 0x82, 0xD1, 0x79, 0x6F, 0x60, 0x06,
++0xD1, 0x0F, 0xE4, 0xF0, 0x80, 0x04, 0xB1, 0xF0,
++0x80, 0xD4, 0xB1, 0xCA, 0x80, 0xC5, 0x90, 0x95,
++0xBA, 0xE0, 0x64, 0x01, 0x60, 0x17, 0xA3, 0xE0,
++0x64, 0x01, 0x60, 0x11, 0xA3, 0xE0, 0x64, 0x01,
++0x60, 0x0B, 0xA3, 0xE0, 0x64, 0x01, 0x60, 0x05,
++0xA3, 0xE0, 0xB4, 0x01, 0x06, 0x90, 0x95, 0x4F,
++0x74, 0x01, 0xF0, 0x90, 0x93, 0x03, 0x12, 0xAF,
++0xB1, 0x30, 0xE0, 0x43, 0x90, 0x01, 0x02, 0xE0,
++0x54, 0x0C, 0x64, 0x08, 0x70, 0x2C, 0x90, 0x95,
++0x4D, 0xF0, 0xD1, 0x06, 0x50, 0x24, 0xB1, 0xBE,
++0xE0, 0x24, 0x04, 0xB1, 0xAB, 0x90, 0x95, 0x4D,
++0xE0, 0xFE, 0xE4, 0x2E, 0xF5, 0x82, 0xE4, 0x34,
++0x07, 0xF5, 0x83, 0xE0, 0x6F, 0x60, 0x07, 0xE4,
++0x90, 0x95, 0xC4, 0xF0, 0x80, 0x04, 0xB1, 0xF0,
++0x80, 0xD8, 0x90, 0x95, 0xC4, 0xE0, 0xB4, 0x01,
++0x06, 0x90, 0x95, 0x4F, 0x74, 0x01, 0xF0, 0x90,
++0x95, 0x4F, 0xE0, 0xB4, 0x01, 0x11, 0x11, 0xA5,
++0x90, 0x93, 0x0D, 0xE0, 0x44, 0x01, 0xF0, 0x12,
++0xB7, 0x8C, 0x12, 0xB2, 0xA6, 0x21, 0xD3, 0xD1,
++0x39, 0x90, 0x95, 0x4E, 0xF0, 0xB1, 0xD1, 0x50,
++0x09, 0xD1, 0x0F, 0x74, 0x01, 0xF0, 0xB1, 0xCA,
++0x80, 0xF3, 0x12, 0xE4, 0x8E, 0x12, 0xDE, 0x00,
++0x21, 0xD3, 0x22, 0xFC, 0xED, 0x2C, 0xFD, 0x90,
++0x8A, 0xE9, 0xE0, 0xFA, 0xA3, 0xE0, 0xFB, 0xF5,
++0x82, 0x8A, 0x83, 0x02, 0x04, 0x7E, 0x90, 0x95,
++0x45, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x90, 0x95,
++0x49, 0x22, 0x90, 0x95, 0x4E, 0xE0, 0x04, 0xF0,
++0x22, 0x90, 0x93, 0x0F, 0xE0, 0xFF, 0x90, 0x95,
++0x4E, 0xE0, 0xFE, 0xC3, 0x9F, 0x22, 0x90, 0x95,
++0x4E, 0xE0, 0x24, 0xBF, 0xF5, 0x82, 0xE4, 0x34,
++0x95, 0xF5, 0x83, 0x22, 0xF5, 0x83, 0xEF, 0xF0,
++0x90, 0x95, 0x4D, 0xE0, 0x04, 0xF0, 0x22, 0x74,
++0xA6, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x95, 0xF5,
++0x83, 0xE0, 0xFF, 0x02, 0x7B, 0x07, 0x90, 0x95,
++0x4D, 0xE0, 0xFD, 0xC3, 0x94, 0x06, 0x22, 0x74,
++0xBA, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x95, 0xF5,
++0x83, 0x22, 0xF5, 0x83, 0xEF, 0xF0, 0x74, 0xB5,
++0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x95, 0xF5, 0x83,
++0x22, 0x7B, 0x01, 0x7A, 0x95, 0x79, 0x65, 0x90,
++0x95, 0xC8, 0x12, 0x86, 0x76, 0x90, 0x95, 0xCB,
++0x22, 0xE4, 0x90, 0x95, 0x4F, 0xF0, 0x90, 0x95,
++0xBA, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0,
++0xA3, 0xF0, 0x22, 0x90, 0x95, 0xC5, 0x12, 0x86,
++0x76, 0xE4, 0xFF, 0x90, 0x95, 0xCB, 0xE0, 0xFE,
++0xEF, 0xC3, 0x9E, 0x50, 0x14, 0x90, 0x95, 0xC8,
++0xD1, 0x74, 0xFE, 0x90, 0x95, 0xC5, 0xD1, 0x74,
++0x6E, 0x60, 0x03, 0x7F, 0x00, 0x22, 0x0F, 0x80,
++0xE2, 0x7F, 0x01, 0x22, 0x12, 0x86, 0x6D, 0x8F,
++0x82, 0x75, 0x83, 0x00, 0x02, 0x02, 0x1F, 0xD3,
++0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x96,
++0xBA, 0x12, 0xAF, 0xCF, 0x12, 0xC7, 0x67, 0x90,
++0x96, 0xC5, 0xF0, 0xE4, 0x90, 0x96, 0xC2, 0xF0,
++0x90, 0x96, 0xBA, 0x12, 0x99, 0x1E, 0x90, 0x96,
++0xBD, 0xF0, 0xEF, 0x54, 0x07, 0x90, 0x96, 0xBF,
++0xF1, 0xD6, 0xE0, 0x90, 0x96, 0xC0, 0xF0, 0x12,
++0xBF, 0x7B, 0x54, 0x7F, 0x90, 0x96, 0xC3, 0xF0,
++0x90, 0x96, 0xBA, 0xE0, 0x12, 0xD3, 0x2A, 0xE0,
++0x90, 0x96, 0xC4, 0xF0, 0xED, 0x54, 0x7F, 0x90,
++0x96, 0xBE, 0xF0, 0xEB, 0x70, 0x22, 0x90, 0x89,
++0x3D, 0x12, 0xE4, 0xEF, 0xFF, 0x12, 0xDA, 0x88,
++0xFD, 0x90, 0x89, 0x40, 0xD1, 0x74, 0x2D, 0xFF,
++0xE4, 0x35, 0xF0, 0xC3, 0x13, 0xFE, 0xEF, 0x13,
++0xFF, 0x90, 0x96, 0xBA, 0xE0, 0x12, 0xBF, 0xC3,
++0x90, 0x96, 0xC3, 0xE0, 0xFF, 0x90, 0x96, 0xBE,
++0xE0, 0xFE, 0xD3, 0x9F, 0x40, 0x0C, 0x90, 0x96,
++0xBB, 0xE0, 0x54, 0x80, 0xFD, 0xEF, 0x4D, 0xF0,
++0x80, 0x0F, 0x90, 0x96, 0xC4, 0xE0, 0xFF, 0xEE,
++0xC3, 0x9F, 0x50, 0x05, 0x90, 0x96, 0xBB, 0xEF,
++0xF0, 0x90, 0x96, 0xBB, 0xE0, 0xFE, 0x54, 0x7F,
++0x90, 0x96, 0xBE, 0xF0, 0xEE, 0x54, 0x80, 0x90,
++0x96, 0xC1, 0xF0, 0x90, 0x96, 0xBC, 0xE0, 0x70,
++0x26, 0xA3, 0x12, 0xE4, 0x0D, 0xC0, 0x83, 0xC0,
++0x82, 0xE0, 0xFF, 0x90, 0x96, 0xBF, 0x12, 0xAC,
++0xBA, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4,
++0x5F, 0xD0, 0x82, 0xD0, 0x83, 0xF0, 0x90, 0x96,
++0xC0, 0xE0, 0x54, 0x7F, 0xF0, 0x80, 0x3E, 0x90,
++0x96, 0xBD, 0x12, 0xE4, 0x0D, 0xC0, 0x83, 0xC0,
++0x82, 0xE0, 0xFF, 0x90, 0x96, 0xBF, 0x12, 0xAC,
++0xBA, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0x4F,
++0xD0, 0x82, 0xD0, 0x83, 0xF1, 0xD6, 0xE0, 0x54,
++0x07, 0xFF, 0x90, 0x96, 0xC0, 0xF0, 0x90, 0x89,
++0x46, 0x12, 0xE4, 0xEF, 0xF5, 0x82, 0xD1, 0x79,
++0x33, 0x33, 0x33, 0x54, 0xF8, 0x4F, 0x90, 0x96,
++0xC0, 0xF0, 0x44, 0x80, 0xF0, 0x90, 0x96, 0xBB,
++0x12, 0xE4, 0xE7, 0x12, 0x96, 0xD1, 0xEF, 0xF0,
++0xEE, 0x70, 0x05, 0x90, 0x01, 0xC8, 0xEF, 0xF0,
++0x90, 0x96, 0xC0, 0x12, 0xE4, 0xE7, 0xF1, 0xDB,
++0xEF, 0xF0, 0xEE, 0x12, 0x95, 0xE2, 0xE0, 0x54,
++0xFC, 0xFF, 0x90, 0x96, 0xC5, 0xE0, 0x54, 0x03,
++0x4F, 0xFE, 0x90, 0x96, 0xBA, 0xE0, 0xFF, 0x12,
++0x95, 0xE2, 0xEE, 0xF0, 0x7D, 0x01, 0x12, 0x61,
++0xF7, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xF0, 0x90,
++0x96, 0xBA, 0xE0, 0xC4, 0x54, 0xF0, 0x24, 0x01,
++0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0x22,
++0xEF, 0xF0, 0xE4, 0x90, 0x95, 0x4E, 0xF0, 0x22,
++0x12, 0x90, 0xCD, 0x12, 0xA8, 0x0D, 0x7B, 0x01,
++0x7A, 0x93, 0x79, 0x1C, 0x02, 0x69, 0xF5, 0x12,
++0x90, 0xCD, 0x11, 0x0D, 0x7B, 0x01, 0x7A, 0x93,
++0x79, 0x21, 0x02, 0x69, 0xF5, 0x8B, 0x45, 0x8A,
++0x46, 0x89, 0x47, 0x75, 0x48, 0x05, 0x22, 0x90,
++0x96, 0xE7, 0x12, 0x86, 0x76, 0x90, 0x96, 0xE6,
++0xEF, 0xF0, 0x12, 0x86, 0x7F, 0xA8, 0xAA, 0x00,
++0xA8, 0xB3, 0x01, 0xA8, 0xBC, 0x06, 0xA8, 0xD1,
++0x08, 0xA8, 0xDA, 0x09, 0xA8, 0xE3, 0x0A, 0xA8,
++0xEC, 0x12, 0xA8, 0xF4, 0x13, 0xA8, 0xFC, 0x14,
++0xA9, 0x04, 0x1E, 0xA9, 0x0C, 0x20, 0xA9, 0x14,
++0x25, 0xA9, 0x1D, 0x26, 0xA9, 0x26, 0x29, 0xA9,
++0x2F, 0x2A, 0xA9, 0x37, 0x40, 0xA9, 0x42, 0x42,
++0xA9, 0x51, 0x43, 0xA9, 0x5A, 0x44, 0xAA, 0x24,
++0x47, 0xA9, 0x63, 0x49, 0xA9, 0x6B, 0x60, 0xA9,
++0x74, 0x61, 0xA9, 0x7D, 0x62, 0xA9, 0x86, 0x63,
++0xA9, 0x8F, 0x64, 0xA9, 0x98, 0x65, 0xA9, 0xA1,
++0x66, 0xA9, 0xAA, 0x67, 0xA9, 0xB3, 0x68, 0xA9,
++0xBC, 0x69, 0xA9, 0xC5, 0x6B, 0xA9, 0xCE, 0x6C,
++0xA9, 0xD7, 0x6D, 0xA9, 0xE0, 0x6E, 0xA9, 0xE9,
++0x6F, 0xA9, 0xF2, 0x70, 0xA9, 0xFB, 0xC2, 0xAA,
++0x03, 0xC3, 0xAA, 0x0C, 0xC4, 0xA8, 0xC5, 0xC6,
++0xA8, 0xC5, 0xC7, 0xA8, 0xC5, 0xC8, 0x00, 0x00,
++0xAA, 0x15, 0x90, 0x96, 0xE7, 0x12, 0x86, 0x6D,
++0x02, 0x86, 0xE0, 0x90, 0x96, 0xE7, 0x12, 0x86,
++0x6D, 0x02, 0x90, 0x04, 0x90, 0x96, 0xE7, 0x12,
++0x86, 0x6D, 0x02, 0xC0, 0x04, 0x90, 0x96, 0xE6,
++0xE0, 0xFF, 0xA3, 0x12, 0x86, 0x6D, 0x02, 0xC0,
++0xA5, 0x90, 0x96, 0xE7, 0x12, 0x86, 0x6D, 0x02,
++0x9F, 0xF6, 0x90, 0x96, 0xE7, 0x12, 0x86, 0x6D,
++0x02, 0xA7, 0xF0, 0x90, 0x96, 0xE7, 0x12, 0x86,
++0x6D, 0x02, 0xA7, 0xFF, 0x90, 0x96, 0xE7, 0x12,
++0x86, 0x6D, 0x41, 0x32, 0x90, 0x96, 0xE7, 0x12,
++0x86, 0x6D, 0x61, 0x97, 0x90, 0x96, 0xE7, 0x12,
++0x86, 0x6D, 0xE1, 0xEA, 0x90, 0x96, 0xE7, 0x12,
++0x86, 0x6D, 0x41, 0x45, 0x90, 0x96, 0xE7, 0x12,
++0x86, 0x6D, 0xE1, 0xF9, 0x90, 0x96, 0xE7, 0x12,
++0x86, 0x6D, 0x02, 0xB7, 0xD9, 0x90, 0x96, 0xE7,
++0x12, 0x86, 0x6D, 0x02, 0x98, 0x18, 0x90, 0x96,
++0xE7, 0x12, 0x86, 0x6D, 0x02, 0xB8, 0x1C, 0x90,
++0x96, 0xE7, 0x12, 0x86, 0x6D, 0xA1, 0xB6, 0x90,
++0x96, 0xE7, 0x12, 0x86, 0x6D, 0x90, 0x8A, 0xA5,
++0x80, 0x09, 0x90, 0x96, 0xE7, 0x12, 0x86, 0x6D,
++0x90, 0x8A, 0xB5, 0x12, 0xDC, 0x46, 0x02, 0x04,
++0x7E, 0x90, 0x96, 0xE7, 0x12, 0x86, 0x6D, 0x02,
++0x25, 0xEC, 0x90, 0x96, 0xE7, 0x12, 0x86, 0x6D,
++0x02, 0x5B, 0xF3, 0x90, 0x96, 0xE7, 0x12, 0x86,
++0x6D, 0xE1, 0xBF, 0x90, 0x96, 0xE7, 0x12, 0x86,
++0x6D, 0x02, 0x92, 0x63, 0x90, 0x96, 0xE7, 0x12,
++0x86, 0x6D, 0x02, 0x77, 0x4F, 0x90, 0x96, 0xE7,
++0x12, 0x86, 0x6D, 0x02, 0x7C, 0x60, 0x90, 0x96,
++0xE7, 0x12, 0x86, 0x6D, 0x02, 0x7A, 0xC6, 0x90,
++0x96, 0xE7, 0x12, 0x86, 0x6D, 0x02, 0x5D, 0x36,
++0x90, 0x96, 0xE7, 0x12, 0x86, 0x6D, 0x02, 0x7B,
++0xE9, 0x90, 0x96, 0xE7, 0x12, 0x86, 0x6D, 0x02,
++0x70, 0x33, 0x90, 0x96, 0xE7, 0x12, 0x86, 0x6D,
++0x02, 0x48, 0xC9, 0x90, 0x96, 0xE7, 0x12, 0x86,
++0x6D, 0x02, 0x79, 0xF3, 0x90, 0x96, 0xE7, 0x12,
++0x86, 0x6D, 0x02, 0x87, 0xD2, 0x90, 0x96, 0xE7,
++0x12, 0x86, 0x6D, 0x02, 0x51, 0x7B, 0x90, 0x96,
++0xE7, 0x12, 0x86, 0x6D, 0x02, 0x79, 0x30, 0x90,
++0x96, 0xE7, 0x12, 0x86, 0x6D, 0x02, 0x57, 0xF2,
++0x90, 0x96, 0xE7, 0x12, 0x86, 0x6D, 0x02, 0x74,
++0x8D, 0x90, 0x96, 0xE7, 0x12, 0x86, 0x6D, 0x02,
++0x78, 0x9A, 0x90, 0x96, 0xE7, 0x12, 0x86, 0x6D,
++0x02, 0x5E, 0x0B, 0x90, 0x96, 0xE7, 0x12, 0x86,
++0x6D, 0x80, 0x22, 0x90, 0x96, 0xE7, 0x12, 0x86,
++0x6D, 0x02, 0xB8, 0x32, 0x90, 0x96, 0xE7, 0x12,
++0x86, 0x6D, 0x02, 0x87, 0xA5, 0x90, 0x01, 0xC0,
++0xE0, 0x44, 0x01, 0xF0, 0x90, 0x96, 0xE6, 0xE0,
++0x90, 0x01, 0xC2, 0xF0, 0x22, 0x12, 0x02, 0x06,
++0x90, 0x93, 0x4B, 0xF0, 0x70, 0x03, 0xF1, 0xB8,
++0xF0, 0x22, 0x12, 0x02, 0x06, 0xFF, 0x90, 0x93,
++0x29, 0xF0, 0xBF, 0x01, 0x07, 0xD1, 0xEC, 0xE4,
++0x90, 0x93, 0x29, 0xF0, 0x22, 0x12, 0x02, 0x06,
++0x90, 0x94, 0xE3, 0xF0, 0x12, 0x87, 0x9F, 0x90,
++0x94, 0xE4, 0xF0, 0x60, 0x0D, 0x51, 0xA8, 0x71,
++0x6D, 0x90, 0x94, 0xE4, 0x51, 0xA8, 0x7B, 0x57,
++0x51, 0xB5, 0x90, 0x88, 0x9D, 0xE0, 0x30, 0xE0,
++0x0D, 0x12, 0x8F, 0xC8, 0x30, 0xE0, 0x07, 0x90,
++0x06, 0x0A, 0xE0, 0x44, 0x07, 0xF0, 0x90, 0x94,
++0xC0, 0x74, 0x20, 0xF0, 0x90, 0x94, 0xE2, 0x74,
++0x03, 0xF0, 0x90, 0x05, 0x22, 0xE0, 0x90, 0x94,
++0xC2, 0xF0, 0x90, 0x93, 0x5E, 0xE0, 0x90, 0x94,
++0xC3, 0xF0, 0x90, 0x93, 0x5F, 0xE0, 0x90, 0x94,
++0xC4, 0xF0, 0x7B, 0x01, 0x7A, 0x94, 0x79, 0xC0,
++0x12, 0x8A, 0xF1, 0x7F, 0x04, 0x02, 0x04, 0x7E,
++0xE0, 0xFF, 0x90, 0x94, 0xE3, 0xE0, 0xFD, 0x22,
++0xE4, 0xFB, 0xFD, 0x7F, 0xFF, 0xEB, 0xB4, 0x57,
++0x04, 0x51, 0xD5, 0x80, 0x0E, 0xEF, 0x70, 0x07,
++0x90, 0x93, 0x5E, 0xE0, 0x4D, 0x80, 0x04, 0x71,
++0x85, 0x51, 0xD5, 0x90, 0x05, 0x22, 0xF0, 0x90,
++0x93, 0x01, 0xEB, 0xF0, 0x22, 0x90, 0x93, 0x5F,
++0xE0, 0xFF, 0x90, 0x93, 0x5E, 0xE0, 0x4F, 0x22,
++0xE4, 0x90, 0x96, 0xF6, 0xF0, 0xA3, 0xF0, 0x90,
++0x05, 0x22, 0xE0, 0x90, 0x96, 0xF8, 0xF0, 0x7B,
++0x47, 0x71, 0x67, 0x90, 0x05, 0xF8, 0xE0, 0x70,
++0x1A, 0xA3, 0xE0, 0x70, 0x16, 0xA3, 0xE0, 0x70,
++0x12, 0xA3, 0xE0, 0x70, 0x0E, 0x90, 0x96, 0xF8,
++0xE0, 0xFD, 0x7B, 0x48, 0xE4, 0xFF, 0x51, 0xB5,
++0x7F, 0x01, 0x22, 0x12, 0x8F, 0xBE, 0x30, 0xE0,
++0x19, 0xD3, 0x90, 0x96, 0xF7, 0xE0, 0x94, 0x03,
++0x90, 0x96, 0xF6, 0xE0, 0x94, 0x00, 0x40, 0x06,
++0x71, 0x5A, 0x7B, 0x5A, 0x80, 0x17, 0x7F, 0x01,
++0x80, 0x1C, 0xD3, 0x90, 0x96, 0xF7, 0xE0, 0x94,
++0xE8, 0x90, 0x96, 0xF6, 0xE0, 0x94, 0x03, 0x40,
++0x0B, 0x71, 0x5A, 0x7B, 0x5B, 0xE4, 0xFF, 0x51,
++0xB5, 0x7F, 0x00, 0x22, 0x7F, 0x32, 0x7E, 0x00,
++0x12, 0x7C, 0x6A, 0x90, 0x96, 0xF6, 0xF1, 0xAA,
++0x80, 0x99, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x20,
++0xF0, 0x90, 0x96, 0xF8, 0xE0, 0xFD, 0x22, 0x7D,
++0xFF, 0xE4, 0xFF, 0x41, 0xB5, 0xEF, 0xB4, 0xFF,
++0x06, 0x90, 0x93, 0x5E, 0xED, 0xF0, 0x22, 0xEF,
++0xF4, 0xFE, 0x90, 0x93, 0x5E, 0xE0, 0x5E, 0xFE,
++0xED, 0x5F, 0x4E, 0xF0, 0x22, 0xEF, 0xB4, 0xFF,
++0x06, 0x90, 0x93, 0x5F, 0xED, 0xF0, 0x22, 0xEF,
++0xF4, 0xFE, 0x90, 0x93, 0x5F, 0x80, 0xE6, 0x12,
++0x02, 0x06, 0xFF, 0x54, 0x80, 0xFE, 0x90, 0x93,
++0x58, 0xE0, 0x54, 0x7F, 0x4E, 0xFE, 0xF0, 0xEF,
++0x54, 0x40, 0xFF, 0xEE, 0x54, 0xBF, 0x4F, 0x12,
++0x9F, 0xC2, 0x54, 0x20, 0xFD, 0xEF, 0x54, 0xDF,
++0x4D, 0xFF, 0x90, 0x93, 0x58, 0xF0, 0xEE, 0x54,
++0x10, 0xFE, 0xEF, 0x54, 0xEF, 0x4E, 0xFF, 0xF0,
++0x12, 0x02, 0x06, 0x54, 0x0F, 0xFE, 0xEF, 0x54,
++0xF0, 0x4E, 0x90, 0x93, 0x58, 0xF0, 0x12, 0x87,
++0x9F, 0xFF, 0x54, 0x7F, 0x90, 0x93, 0x5A, 0xF0,
++0xEF, 0x54, 0x80, 0x12, 0x8F, 0xCC, 0xFF, 0x90,
++0x93, 0x59, 0xE0, 0x54, 0xFE, 0x12, 0x87, 0x25,
++0x90, 0x93, 0x5B, 0x12, 0x87, 0x76, 0x54, 0x01,
++0x25, 0xE0, 0xFF, 0x90, 0x93, 0x59, 0xE0, 0x54,
++0xFD, 0x4F, 0xF0, 0xB1, 0x60, 0x20, 0xE0, 0x02,
++0x7D, 0x01, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0,
++0xD0, 0x90, 0x97, 0x04, 0xED, 0xF0, 0x90, 0x97,
++0x03, 0xEF, 0xF0, 0xD3, 0x94, 0x07, 0x50, 0x42,
++0x7F, 0x47, 0x91, 0xB4, 0x80, 0x02, 0xC3, 0x33,
++0xD8, 0xFC, 0xF4, 0x5F, 0xFD, 0x7F, 0x47, 0x12,
++0x7B, 0x2E, 0x7F, 0x46, 0x91, 0xB4, 0x80, 0x02,
++0xC3, 0x33, 0xD8, 0xFC, 0x4F, 0xFD, 0x7F, 0x46,
++0xB1, 0x79, 0x60, 0x0D, 0x7F, 0x45, 0x91, 0xB4,
++0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0x4F, 0x80,
++0x0C, 0x7F, 0x45, 0x91, 0xB4, 0x80, 0x02, 0xC3,
++0x33, 0xD8, 0xFC, 0xF4, 0x5F, 0xFD, 0x7F, 0x45,
++0x80, 0x4A, 0x90, 0x97, 0x03, 0xE0, 0x24, 0xF8,
++0xF0, 0x7F, 0x63, 0x91, 0xB4, 0x80, 0x02, 0xC3,
++0x33, 0xD8, 0xFC, 0xF4, 0x5F, 0xFD, 0x7F, 0x63,
++0x12, 0x7B, 0x2E, 0x7F, 0x62, 0x91, 0xB4, 0x80,
++0x02, 0xC3, 0x33, 0xD8, 0xFC, 0x4F, 0xFD, 0x7F,
++0x62, 0xB1, 0x79, 0x60, 0x10, 0x7F, 0x61, 0x91,
++0xB4, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0x4F,
++0xFD, 0x7F, 0x61, 0x80, 0x0F, 0x7F, 0x61, 0x91,
++0xB4, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4,
++0x5F, 0xFD, 0x7F, 0x61, 0x12, 0x7B, 0x2E, 0xD0,
++0xD0, 0x92, 0xAF, 0x22, 0x12, 0x7B, 0x41, 0x90,
++0x97, 0x03, 0xE0, 0xFE, 0x74, 0x01, 0xA8, 0x06,
++0x08, 0x22, 0xAD, 0x07, 0x90, 0x93, 0x5A, 0xE0,
++0x75, 0xF0, 0x20, 0xA4, 0xFF, 0x90, 0x96, 0xD5,
++0xE5, 0xF0, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x93,
++0x5B, 0xE0, 0x75, 0xF0, 0x08, 0xA4, 0xAE, 0xF0,
++0x90, 0x96, 0xD7, 0xF0, 0xEE, 0xA3, 0xF0, 0xB1,
++0x71, 0x90, 0x96, 0xD9, 0xF0, 0xEE, 0xA3, 0xF0,
++0xED, 0x64, 0x01, 0x60, 0x63, 0x90, 0x93, 0x58,
++0xE0, 0xFE, 0x12, 0x8F, 0xCC, 0x30, 0xE0, 0x58,
++0xEE, 0xB1, 0x65, 0x20, 0xE0, 0x02, 0x7D, 0x01,
++0xB1, 0x59, 0xFE, 0x54, 0x0F, 0xFF, 0xEE, 0xC4,
++0x13, 0x13, 0x54, 0x01, 0xFD, 0xB1, 0x59, 0xC4,
++0x13, 0x54, 0x07, 0x30, 0xE0, 0x23, 0xA3, 0xE0,
++0x30, 0xE0, 0x0F, 0x90, 0x96, 0xDA, 0xE0, 0x90,
++0x92, 0x20, 0xF0, 0x90, 0x96, 0xD9, 0xB1, 0x81,
++0x80, 0x0F, 0xB1, 0x71, 0xFF, 0x12, 0x7C, 0x6A,
++0xB1, 0x60, 0x20, 0xE0, 0x02, 0x7D, 0x01, 0x91,
++0x0A, 0x90, 0x93, 0x58, 0xE0, 0xC4, 0x54, 0x0F,
++0x30, 0xE0, 0x0D, 0x90, 0x96, 0xD8, 0xE0, 0x90,
++0x92, 0x20, 0xF0, 0x90, 0x96, 0xD7, 0xB1, 0x81,
++0x22, 0x91, 0x0A, 0x90, 0x93, 0x58, 0xE0, 0x22,
++0x90, 0x93, 0x58, 0xE0, 0xFE, 0x54, 0x0F, 0xFF,
++0xEE, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x7D, 0x00,
++0x22, 0x90, 0x96, 0xD5, 0xE0, 0xFE, 0xA3, 0xE0,
++0x22, 0x12, 0x7B, 0x2E, 0x90, 0x97, 0x04, 0xE0,
++0x22, 0xE0, 0x90, 0x92, 0x21, 0xF0, 0xE4, 0xFB,
++0xFD, 0x7F, 0x58, 0x7E, 0x01, 0x02, 0x66, 0x33,
++0x90, 0x93, 0x58, 0xE0, 0xFF, 0x12, 0x8F, 0xCC,
++0x30, 0xE0, 0x1A, 0xEF, 0xC4, 0x54, 0x0F, 0x30,
++0xE0, 0x03, 0x12, 0xDA, 0xB1, 0x90, 0x93, 0x59,
++0xE0, 0x30, 0xE0, 0x09, 0xB1, 0x60, 0x20, 0xE0,
++0x02, 0x7D, 0x01, 0x91, 0x0A, 0x22, 0x90, 0x93,
++0x32, 0xE0, 0x20, 0xE0, 0x02, 0xC1, 0x77, 0xE4,
++0x90, 0x94, 0xC0, 0xF0, 0xF1, 0xD8, 0x40, 0x02,
++0xC1, 0x77, 0x12, 0xC4, 0x52, 0x80, 0x05, 0xC3,
++0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, 0xFF, 0x90,
++0x93, 0x33, 0xE0, 0xFD, 0xEF, 0x5D, 0x60, 0x02,
++0xC1, 0x6F, 0x12, 0x02, 0x06, 0xFF, 0x30, 0xE0,
++0x1A, 0x90, 0x93, 0x34, 0xE0, 0xFE, 0x90, 0x94,
++0xC0, 0xE0, 0xFD, 0x74, 0x01, 0xA8, 0x05, 0x08,
++0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0x4E, 0x90,
++0x93, 0x34, 0xF0, 0xEF, 0xC3, 0x13, 0x30, 0xE0,
++0x15, 0x90, 0x93, 0x35, 0xE0, 0xFF, 0x90, 0x94,
++0xC0, 0x91, 0xBA, 0x80, 0x02, 0xC3, 0x33, 0xD8,
++0xFC, 0x4F, 0x90, 0x93, 0x35, 0xF0, 0x12, 0x87,
++0x9F, 0xFF, 0x90, 0x94, 0xC0, 0xE0, 0xFE, 0x24,
++0x36, 0xF5, 0x82, 0xE4, 0x34, 0x93, 0xF5, 0x83,
++0xEF, 0x12, 0x87, 0x26, 0xFF, 0x74, 0x3B, 0x2E,
++0xF5, 0x82, 0xE4, 0x34, 0x93, 0x12, 0x87, 0x73,
++0xFF, 0x74, 0x40, 0x2E, 0xF5, 0x82, 0xE4, 0x34,
++0x93, 0x12, 0x87, 0x7D, 0xFF, 0x74, 0x45, 0x2E,
++0xF5, 0x82, 0xE4, 0x34, 0x93, 0xF5, 0x83, 0xEF,
++0xF0, 0x90, 0x93, 0x33, 0xE0, 0xFF, 0x74, 0x01,
++0xA8, 0x06, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8,
++0xFC, 0x4F, 0x90, 0x93, 0x33, 0xF0, 0x22, 0x90,
++0x94, 0xC0, 0xE0, 0x04, 0xF0, 0xA1, 0xC4, 0x22,
++0x90, 0x88, 0x36, 0xE0, 0x60, 0x14, 0x90, 0x06,
++0x92, 0xE0, 0x30, 0xE1, 0x08, 0x90, 0x8B, 0x01,
++0x12, 0x90, 0xE2, 0x80, 0x05, 0xF1, 0xC7, 0x12,
++0x9F, 0xDE, 0xA1, 0x90, 0x90, 0x94, 0xA2, 0xE0,
++0xB4, 0x01, 0x14, 0xE4, 0xF0, 0x90, 0x01, 0x5B,
++0xF0, 0x90, 0x92, 0x20, 0xF0, 0x90, 0x88, 0x95,
++0xE0, 0xC3, 0x13, 0x54, 0x7F, 0xB1, 0x82, 0x90,
++0x88, 0x31, 0xE0, 0xFF, 0xC4, 0x13, 0x13, 0x54,
++0x03, 0x30, 0xE0, 0x2F, 0xEF, 0x54, 0xBF, 0xF1,
++0xE1, 0x30, 0xE0, 0x06, 0xE0, 0x44, 0x01, 0xF0,
++0x80, 0x09, 0xE0, 0x54, 0xFE, 0x12, 0xB0, 0x96,
++0x74, 0x04, 0xF0, 0x90, 0x88, 0xA3, 0xF1, 0xB1,
++0x30, 0xE0, 0x0D, 0x90, 0x8A, 0xB9, 0x12, 0x8B,
++0x03, 0x7D, 0x01, 0x7F, 0x0C, 0x02, 0x04, 0x7E,
++0x12, 0x9F, 0xDE, 0x22, 0x7B, 0x01, 0x7A, 0x94,
++0x79, 0xC0, 0x7F, 0xEF, 0x7E, 0x01, 0x12, 0x5F,
++0xA6, 0xBF, 0x01, 0x06, 0x90, 0x94, 0xC0, 0xE0,
++0xA3, 0xF0, 0x7B, 0x01, 0x7A, 0x94, 0x79, 0xC0,
++0x7F, 0xEE, 0x7E, 0x01, 0x12, 0x5F, 0xA6, 0xBF,
++0x01, 0x08, 0x90, 0x94, 0xC0, 0xE0, 0x90, 0x94,
++0xC2, 0xF0, 0x7B, 0x01, 0x7A, 0x94, 0x79, 0xC0,
++0x7F, 0xED, 0x7E, 0x01, 0x12, 0x5F, 0xA6, 0xBF,
++0x01, 0x08, 0x90, 0x94, 0xC0, 0xE0, 0x90, 0x94,
++0xC3, 0xF0, 0x7B, 0x01, 0x7A, 0x94, 0x79, 0xC0,
++0x7F, 0xEC, 0x7E, 0x01, 0x12, 0x5F, 0xA6, 0xBF,
++0x01, 0x08, 0x90, 0x94, 0xC0, 0xE0, 0x90, 0x94,
++0xC4, 0xF0, 0x7B, 0x01, 0x7A, 0x94, 0x79, 0xC0,
++0x7F, 0xEB, 0x7E, 0x01, 0x12, 0x5F, 0xA6, 0xBF,
++0x01, 0x08, 0x90, 0x94, 0xC0, 0xE0, 0x90, 0x94,
++0xC5, 0xF0, 0x90, 0x94, 0xC1, 0xE0, 0xFF, 0xA3,
++0xE0, 0xFD, 0xA3, 0xE0, 0xFB, 0xA3, 0xE0, 0x90,
++0x94, 0xC9, 0xF0, 0x90, 0x94, 0xC5, 0xE0, 0x90,
++0x94, 0xCA, 0xF0, 0x90, 0x94, 0xCB, 0x74, 0x12,
++0xF0, 0x90, 0x94, 0xED, 0x74, 0x05, 0xF0, 0x90,
++0x94, 0xCD, 0xF1, 0xCF, 0x90, 0x94, 0xC9, 0xE0,
++0x90, 0x94, 0xD0, 0xF0, 0x90, 0x94, 0xCA, 0xE0,
++0x90, 0x94, 0xD1, 0xF0, 0x7B, 0x01, 0x7A, 0x94,
++0x79, 0xCB, 0x12, 0x8A, 0xF1, 0x7F, 0x04, 0x02,
++0x04, 0x7E, 0xE4, 0x75, 0xF0, 0x01, 0x02, 0x02,
++0xE7, 0xE0, 0xFF, 0xC4, 0x13, 0x54, 0x07, 0x22,
++0x90, 0x05, 0x21, 0xE0, 0x54, 0x7F, 0x22, 0x12,
++0x02, 0x06, 0x90, 0x96, 0x17, 0xF0, 0x22, 0x90,
++0x88, 0x31, 0xE0, 0x54, 0xF7, 0xF0, 0x22, 0xEF,
++0xF0, 0xA3, 0xED, 0xF0, 0xA3, 0xEB, 0xF0, 0x22,
++0x90, 0x94, 0xC0, 0xE0, 0xFF, 0xC3, 0x94, 0x05,
++0x22, 0xF0, 0x90, 0x04, 0xE0, 0xE0, 0x90, 0x88,
++0x32, 0x22, 0x12, 0x02, 0x06, 0x54, 0x01, 0xFF,
++0x90, 0x93, 0x5D, 0xE0, 0x54, 0xFE, 0x4F, 0xF0,
++0x22, 0x90, 0x94, 0xC0, 0x12, 0x9F, 0xB5, 0xFF,
++0x54, 0x7F, 0x90, 0x88, 0x36, 0xF0, 0xEF, 0x12,
++0x8F, 0xCC, 0xA3, 0xF0, 0x12, 0x87, 0x9F, 0xFD,
++0x54, 0xF0, 0xC4, 0x54, 0x0F, 0xFF, 0x90, 0x88,
++0x34, 0xE0, 0x54, 0xF0, 0x4F, 0x12, 0x87, 0x76,
++0xFC, 0x54, 0x01, 0x25, 0xE0, 0xFF, 0x90, 0x88,
++0x31, 0xE0, 0x54, 0xFD, 0x4F, 0xF0, 0xEC, 0x54,
++0x04, 0xC3, 0x13, 0xFF, 0x90, 0x88, 0x33, 0xE0,
++0x54, 0xFD, 0x4F, 0xF0, 0xED, 0x54, 0x0F, 0xC4,
++0x54, 0xF0, 0xFF, 0xA3, 0xE0, 0x54, 0x0F, 0x12,
++0x87, 0x25, 0x90, 0x88, 0x35, 0x12, 0x87, 0x80,
++0xFD, 0x90, 0x8A, 0x89, 0x12, 0x8B, 0x03, 0x7F,
++0x02, 0x12, 0x04, 0x7E, 0x90, 0x88, 0x9B, 0x12,
++0x9F, 0xD0, 0xF0, 0x54, 0xFB, 0xF0, 0x54, 0xF7,
++0xF0, 0x54, 0xEF, 0xF0, 0x54, 0xDF, 0xF0, 0x54,
++0xBF, 0xF0, 0x12, 0x90, 0xD3, 0x12, 0x5C, 0x5F,
++0x90, 0x88, 0x36, 0xE0, 0xB4, 0x01, 0x07, 0x90,
++0x88, 0x33, 0xE0, 0x54, 0xFB, 0xF0, 0x11, 0x97,
++0xF0, 0x90, 0x88, 0x36, 0x11, 0xA1, 0x12, 0x9F,
++0xE6, 0x90, 0x01, 0xBE, 0xF0, 0x22, 0xF0, 0x90,
++0x01, 0xB9, 0x74, 0x01, 0xF0, 0x90, 0x01, 0xB8,
++0x22, 0xE0, 0x90, 0x01, 0xBA, 0xF0, 0x90, 0x88,
++0x38, 0xE0, 0x90, 0x01, 0xBB, 0x22, 0x90, 0x88,
++0x31, 0xE0, 0xFF, 0x12, 0x8F, 0xCC, 0x30, 0xE0,
++0x1F, 0xEF, 0x54, 0x7F, 0x12, 0xAF, 0xE1, 0x30,
++0xE1, 0x06, 0xE0, 0x44, 0x02, 0xF0, 0x80, 0x07,
++0xE0, 0x54, 0xFD, 0x11, 0x96, 0x04, 0xF0, 0x90,
++0x88, 0x36, 0xE0, 0x60, 0x03, 0x12, 0x9F, 0xDE,
++0x12, 0x8F, 0xBE, 0x30, 0xE0, 0x21, 0x90, 0x88,
++0xA4, 0xE0, 0xFF, 0xC3, 0x13, 0x30, 0xE0, 0x17,
++0xEF, 0x54, 0xFD, 0xF0, 0x90, 0x04, 0xE0, 0xE0,
++0x90, 0x88, 0xA4, 0x30, 0xE1, 0x05, 0xE0, 0x44,
++0x04, 0xF0, 0x22, 0xE0, 0x54, 0xFB, 0xF0, 0x22,
++0xC0, 0xE0, 0xC0, 0xF0, 0xC0, 0x83, 0xC0, 0x82,
++0xC0, 0xD0, 0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0,
++0x01, 0xC0, 0x02, 0xC0, 0x03, 0xC0, 0x04, 0xC0,
++0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4,
++0x74, 0x00, 0xF0, 0x74, 0xB1, 0xA3, 0xF0, 0x12,
++0x75, 0x50, 0xE5, 0x3D, 0x30, 0xE0, 0x02, 0xB1,
++0x5C, 0xE5, 0x3D, 0x30, 0xE1, 0x03, 0x12, 0xCF,
++0xB0, 0xE5, 0x3D, 0x30, 0xE2, 0x03, 0x12, 0xAE,
++0x78, 0xE5, 0x3D, 0x30, 0xE3, 0x02, 0x71, 0x56,
++0xE5, 0x3D, 0x30, 0xE4, 0x02, 0x51, 0x90, 0xE5,
++0x3E, 0x30, 0xE0, 0x02, 0x71, 0xF3, 0xE5, 0x3E,
++0x30, 0xE3, 0x02, 0x31, 0xC0, 0xE5, 0x3F, 0x30,
++0xE2, 0x0A, 0x12, 0xCF, 0xCE, 0x90, 0x07, 0x8F,
++0xE0, 0x44, 0x10, 0xF0, 0xE5, 0x40, 0x30, 0xE1,
++0x0B, 0x90, 0x8A, 0xE5, 0x12, 0x8B, 0x03, 0x7F,
++0x04, 0x12, 0x04, 0x7E, 0xE5, 0x40, 0x30, 0xE4,
++0x02, 0x51, 0x80, 0xE5, 0x40, 0x30, 0xE5, 0x03,
++0x12, 0xAE, 0x94, 0xE5, 0x40, 0x30, 0xE6, 0x02,
++0x11, 0xAE, 0xE5, 0x40, 0x30, 0xE7, 0x03, 0x12,
++0x96, 0xE6, 0x74, 0x00, 0x04, 0x90, 0x01, 0xC4,
++0xF0, 0x74, 0xB1, 0xA3, 0xF0, 0xD0, 0x07, 0xD0,
++0x06, 0xD0, 0x05, 0xD0, 0x04, 0xD0, 0x03, 0xD0,
++0x02, 0xD0, 0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0,
++0x82, 0xD0, 0x83, 0xD0, 0xF0, 0xD0, 0xE0, 0x32,
++0x90, 0x01, 0x8C, 0xE4, 0xF0, 0xA3, 0xF0, 0xA3,
++0x74, 0x71, 0xF0, 0xA3, 0x74, 0x02, 0xF0, 0x90,
++0x01, 0x95, 0xE0, 0x54, 0xF0, 0x44, 0x07, 0xF0,
++0x90, 0x01, 0x98, 0x74, 0x7F, 0xF0, 0x90, 0x01,
++0x01, 0xE0, 0x54, 0xFB, 0xF0, 0xE0, 0x44, 0x04,
++0xF0, 0x22, 0x12, 0x97, 0xC5, 0x54, 0x7F, 0x90,
++0x95, 0xCC, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x94,
++0xBF, 0xE0, 0x54, 0x02, 0xFF, 0x90, 0x95, 0xCD,
++0xE0, 0x54, 0x02, 0xFD, 0xED, 0x6F, 0x30, 0xE1,
++0x04, 0x31, 0xC0, 0x51, 0x2F, 0x90, 0x95, 0xCD,
++0xE0, 0x20, 0xE1, 0x0B, 0x90, 0x94, 0xBF, 0xE0,
++0x20, 0xE1, 0x04, 0x31, 0xC0, 0x51, 0x2F, 0x90,
++0x95, 0xCC, 0xE0, 0xFF, 0xA3, 0xE0, 0x90, 0x94,
++0xBE, 0xCF, 0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0xE4,
++0x90, 0x97, 0x05, 0xF0, 0xA3, 0xF0, 0xF1, 0x9F,
++0xEF, 0x64, 0x01, 0x60, 0x3C, 0xC3, 0x90, 0x97,
++0x06, 0xE0, 0x94, 0x88, 0x90, 0x97, 0x05, 0xE0,
++0x94, 0x13, 0x40, 0x0F, 0x90, 0x01, 0xC1, 0xE0,
++0x44, 0x10, 0xF0, 0x90, 0x01, 0xC7, 0x74, 0xFD,
++0xF0, 0x80, 0x1E, 0x90, 0x97, 0x05, 0x12, 0xAF,
++0xAA, 0xF1, 0x65, 0xD3, 0x90, 0x97, 0x06, 0xE0,
++0x94, 0x32, 0x90, 0x97, 0x05, 0xE0, 0x94, 0x00,
++0x40, 0xC4, 0x90, 0x01, 0xC6, 0xE0, 0x30, 0xE3,
++0xBD, 0x90, 0x01, 0xC7, 0x74, 0xFE, 0xF0, 0x22,
++0x71, 0xB3, 0xB1, 0x5D, 0x7F, 0x01, 0x71, 0x7A,
++0x90, 0x8B, 0x07, 0xF1, 0x6C, 0x02, 0x04, 0x7A,
++0x90, 0x88, 0x9D, 0xE0, 0x30, 0xE0, 0x0D, 0x51,
++0xE1, 0x30, 0xE0, 0x08, 0x90, 0x8A, 0xBB, 0x12,
++0x8B, 0x03, 0x71, 0x49, 0xF1, 0x8C, 0x90, 0x97,
++0x0E, 0xEF, 0xF0, 0x90, 0x86, 0xB3, 0xE0, 0xB4,
++0x02, 0x12, 0x90, 0x97, 0x0E, 0xE0, 0xFF, 0x64,
++0x01, 0x60, 0x25, 0x90, 0x01, 0x4D, 0xE0, 0x64,
++0x80, 0xF0, 0x80, 0x19, 0x90, 0x01, 0x00, 0x74,
++0xFF, 0xF0, 0x7F, 0x64, 0x7E, 0x00, 0x12, 0x7C,
++0x6A, 0x90, 0x06, 0x90, 0xE0, 0x44, 0x01, 0xF0,
++0x90, 0x97, 0x0E, 0xE0, 0xFF, 0x12, 0xAC, 0xC2,
++0x22, 0x90, 0x88, 0xA1, 0xE0, 0x13, 0x13, 0x54,
++0x3F, 0x22, 0xEF, 0x64, 0x39, 0x70, 0x59, 0x90,
++0x01, 0x63, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x10,
++0xF0, 0x90, 0x88, 0x9D, 0xE0, 0x30, 0xE0, 0x48,
++0x51, 0xE1, 0x30, 0xE0, 0x43, 0x90, 0x88, 0xC2,
++0xE0, 0xFF, 0xC4, 0x54, 0x0F, 0x30, 0xE0, 0x38,
++0x90, 0x94, 0xB5, 0xE0, 0x04, 0xF0, 0xF1, 0x95,
++0x30, 0xE0, 0x11, 0xEE, 0x13, 0x13, 0x13, 0x54,
++0x1F, 0x30, 0xE0, 0x08, 0xEF, 0x54, 0xEF, 0x90,
++0x88, 0xC2, 0xF0, 0x22, 0x90, 0x88, 0xB0, 0xE0,
++0x70, 0x16, 0x71, 0x4E, 0x90, 0x88, 0x9D, 0xE0,
++0x30, 0xE0, 0x0D, 0x51, 0xE1, 0x30, 0xE0, 0x08,
++0x90, 0x8A, 0xBB, 0x12, 0x8B, 0x03, 0x71, 0x49,
++0x22, 0xE4, 0xFF, 0x12, 0x04, 0x7E, 0x90, 0x88,
++0xC2, 0xE0, 0x54, 0xEF, 0xF0, 0x22, 0xB1, 0x54,
++0x64, 0x03, 0x60, 0x03, 0xBF, 0x02, 0x1A, 0x90,
++0x94, 0xBD, 0xE0, 0x70, 0x09, 0x04, 0xF0, 0x91,
++0x47, 0x90, 0x8A, 0x87, 0x80, 0x08, 0xE4, 0x90,
++0x94, 0xBD, 0xF0, 0x90, 0x8B, 0x07, 0x12, 0x90,
++0xE2, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0,
++0xD0, 0x90, 0x88, 0x33, 0xE0, 0xC3, 0x13, 0x30,
++0xE0, 0x24, 0x90, 0x96, 0x65, 0x74, 0x1E, 0xF0,
++0x90, 0x96, 0x87, 0x74, 0x01, 0xF0, 0x90, 0x96,
++0x67, 0xEF, 0xF0, 0x7B, 0x01, 0x7A, 0x96, 0x79,
++0x65, 0xF1, 0xB8, 0x90, 0x8A, 0xE5, 0x12, 0x8B,
++0x03, 0x7F, 0x04, 0x12, 0x04, 0x7E, 0xD0, 0xD0,
++0x92, 0xAF, 0x22, 0xE4, 0x90, 0x95, 0xF3, 0xF0,
++0x90, 0x88, 0x36, 0xE0, 0x60, 0x34, 0xD1, 0xD4,
++0x70, 0x30, 0xD1, 0xCC, 0xF0, 0x12, 0xE3, 0x97,
++0x90, 0x95, 0xF3, 0x74, 0x01, 0xF0, 0xE4, 0x90,
++0x88, 0x3D, 0xF0, 0x04, 0x60, 0x1C, 0x90, 0x88,
++0x39, 0xE0, 0x20, 0xE2, 0x0D, 0x90, 0x8A, 0xB9,
++0x12, 0x8B, 0x03, 0x7D, 0x01, 0x7F, 0x04, 0x12,
++0x04, 0x7E, 0xF1, 0x7C, 0x12, 0x97, 0x28, 0x12,
++0x97, 0xA9, 0x22, 0x12, 0xDA, 0xE9, 0x90, 0x95,
++0xF3, 0xEF, 0xF0, 0x20, 0xE0, 0x06, 0x90, 0x01,
++0x3D, 0x74, 0x01, 0xF0, 0x90, 0x95, 0xF3, 0xE0,
++0x90, 0x8A, 0x89, 0x30, 0xE0, 0x13, 0x12, 0x8B,
++0x03, 0x7D, 0x01, 0xE4, 0xFF, 0x12, 0x04, 0x7E,
++0x90, 0x88, 0x33, 0xE0, 0x44, 0x04, 0xF0, 0x80,
++0x06, 0x12, 0x8B, 0x03, 0x12, 0x8F, 0xF5, 0x90,
++0x95, 0xF3, 0xE0, 0x30, 0xE6, 0x11, 0x90, 0x01,
++0x2F, 0xE0, 0x30, 0xE7, 0x04, 0xE4, 0xF0, 0x80,
++0x06, 0x90, 0x01, 0x2F, 0x74, 0x80, 0xF0, 0xF1,
++0xC8, 0x74, 0x02, 0xF0, 0x02, 0x6E, 0x2F, 0xB1,
++0x54, 0x70, 0x0C, 0xA3, 0xE0, 0x04, 0x12, 0x97,
++0xBB, 0xFE, 0xA3, 0xE0, 0xC3, 0x9E, 0x22, 0x90,
++0x94, 0xBC, 0xE0, 0xD3, 0x94, 0x00, 0x40, 0x3E,
++0xA3, 0xE0, 0x64, 0x01, 0x70, 0x16, 0xBF, 0x03,
++0x09, 0x90, 0x92, 0x20, 0xF0, 0xA3, 0x74, 0x32,
++0x80, 0x21, 0xE4, 0x90, 0x92, 0x20, 0xF0, 0xA3,
++0x74, 0x64, 0x80, 0x17, 0x90, 0x94, 0xBC, 0xE0,
++0x14, 0x12, 0x97, 0xBB, 0xFF, 0xA3, 0xE0, 0xC3,
++0x9F, 0x50, 0x1C, 0xE4, 0x90, 0x92, 0x20, 0xF0,
++0xA3, 0x74, 0x02, 0xF0, 0xE4, 0xFB, 0xFD, 0x7F,
++0x5C, 0x7E, 0x01, 0x02, 0x66, 0x33, 0x12, 0x97,
++0xBC, 0xA3, 0xF0, 0xA3, 0x74, 0x01, 0xF0, 0x22,
++0x91, 0x47, 0x90, 0x88, 0x9D, 0xE0, 0x30, 0xE0,
++0x5E, 0x90, 0x94, 0xA3, 0xE0, 0x30, 0xE0, 0x3D,
++0x90, 0x94, 0xAE, 0xE0, 0xFF, 0x90, 0x94, 0xAD,
++0xE0, 0xC3, 0x9F, 0x40, 0x24, 0xB1, 0x12, 0x90,
++0x06, 0xC4, 0xB1, 0x10, 0x78, 0x08, 0x12, 0x03,
++0xEB, 0x90, 0x06, 0xC5, 0xB1, 0x10, 0x78, 0x10,
++0x12, 0x03, 0xEB, 0x90, 0x06, 0xC6, 0xB1, 0x10,
++0xB1, 0x18, 0xE4, 0x90, 0x94, 0xAD, 0xF0, 0x80,
++0x1B, 0xB1, 0x23, 0xB1, 0x18, 0x90, 0x94, 0xAD,
++0xE0, 0x04, 0xF0, 0x80, 0x0F, 0x90, 0x94, 0xAC,
++0xE0, 0x60, 0x09, 0xB1, 0x23, 0xB1, 0x18, 0xE4,
++0x90, 0x94, 0xAC, 0xF0, 0x90, 0x8A, 0xBB, 0x12,
++0x8B, 0x03, 0xE4, 0xFF, 0x12, 0x04, 0x7E, 0x22,
++0xEF, 0xF0, 0x90, 0x94, 0xA4, 0x02, 0x04, 0xB8,
++0x78, 0x18, 0x12, 0x03, 0xEB, 0x90, 0x06, 0xC7,
++0xEF, 0xF0, 0x22, 0x90, 0x94, 0xA8, 0x12, 0x04,
++0xB8, 0x90, 0x06, 0xC4, 0xEF, 0xF0, 0x90, 0x94,
++0xA8, 0x12, 0x04, 0xB8, 0x78, 0x08, 0x12, 0x03,
++0xEB, 0x90, 0x06, 0xC5, 0xEF, 0xF0, 0x90, 0x94,
++0xA8, 0x12, 0x04, 0xB8, 0x78, 0x10, 0x12, 0x03,
++0xEB, 0x90, 0x06, 0xC6, 0xEF, 0xF0, 0x90, 0x94,
++0xA8, 0x02, 0x04, 0xB8, 0x90, 0x94, 0xBB, 0xE0,
++0x54, 0x03, 0xFF, 0x22, 0x22, 0x7D, 0x02, 0x7F,
++0x02, 0x02, 0x7C, 0x74, 0xE4, 0x90, 0x95, 0xCE,
++0xF0, 0xD1, 0xD5, 0x60, 0x02, 0xC1, 0xAF, 0x90,
++0x88, 0x36, 0xE0, 0x70, 0x02, 0xC1, 0xAF, 0x90,
++0x88, 0x9D, 0xE0, 0x20, 0xE0, 0x2E, 0x90, 0x06,
++0xA9, 0xE0, 0x54, 0xC0, 0x70, 0x26, 0x90, 0x88,
++0x9C, 0xE0, 0x70, 0x20, 0x90, 0x04, 0x1A, 0xE0,
++0xF4, 0x70, 0x19, 0xA3, 0xE0, 0x54, 0x07, 0xFF,
++0xBF, 0x07, 0x11, 0x90, 0x06, 0x62, 0xE0, 0x54,
++0x03, 0x70, 0x09, 0x90, 0x88, 0x39, 0xE0, 0xB4,
++0x04, 0x02, 0xF1, 0x74, 0x90, 0x05, 0x63, 0xE0,
++0x90, 0x88, 0x85, 0xF0, 0x90, 0x05, 0x62, 0xE0,
++0x90, 0x88, 0x86, 0xF0, 0x90, 0x05, 0x61, 0xE0,
++0x90, 0x88, 0x87, 0xF0, 0x90, 0x05, 0x60, 0xE0,
++0x90, 0x88, 0x88, 0xF0, 0x90, 0x07, 0xF1, 0xE0,
++0x90, 0x94, 0xA0, 0xF0, 0x90, 0x07, 0xF0, 0xE0,
++0x90, 0x94, 0xA1, 0xF0, 0xD1, 0xF4, 0xF0, 0x90,
++0x88, 0x3A, 0xE0, 0x54, 0xEC, 0xF0, 0xD1, 0xB8,
++0x24, 0xFD, 0x50, 0x02, 0x80, 0x03, 0x12, 0xCA,
++0xF8, 0xD1, 0xB8, 0x64, 0x01, 0x70, 0x3A, 0x90,
++0x06, 0xAB, 0xE0, 0x90, 0x88, 0x3D, 0xF0, 0x90,
++0x06, 0xA9, 0xE0, 0x30, 0xE5, 0x06, 0xA3, 0xE0,
++0x90, 0x95, 0xCE, 0xF0, 0x90, 0x95, 0xCE, 0xE0,
++0xFF, 0x60, 0x02, 0x80, 0x05, 0x90, 0x88, 0x3C,
++0xE0, 0xFF, 0x90, 0x88, 0x3C, 0xEF, 0xF0, 0xA3,
++0xE0, 0xFF, 0x70, 0x08, 0x90, 0x88, 0x3C, 0xE0,
++0xFE, 0xFF, 0x80, 0x00, 0x90, 0x88, 0x3D, 0xEF,
++0xF0, 0x12, 0xE0, 0x99, 0xE4, 0x90, 0x88, 0x3F,
++0xF0, 0xA3, 0xF0, 0x90, 0x88, 0x32, 0x12, 0x99,
++0x1E, 0x30, 0xE0, 0x64, 0xEF, 0xC4, 0x13, 0x13,
++0x54, 0x03, 0x20, 0xE0, 0x27, 0xD1, 0xB0, 0x6F,
++0x70, 0x56, 0xEF, 0x60, 0x53, 0x90, 0x88, 0x32,
++0xE0, 0x44, 0x40, 0xF0, 0xD1, 0xCC, 0xD1, 0xC1,
++0x12, 0x7C, 0x05, 0xF1, 0x5D, 0x7D, 0x02, 0x7F,
++0x02, 0x12, 0x7C, 0x7E, 0x90, 0x88, 0x3D, 0xE0,
++0x14, 0xF0, 0x80, 0x34, 0x90, 0x88, 0x34, 0xE0,
++0xC4, 0x54, 0x0F, 0x64, 0x01, 0x70, 0x29, 0xD1,
++0xB0, 0xFE, 0x6F, 0x60, 0x23, 0x90, 0x05, 0x73,
++0xE0, 0xFF, 0xEE, 0x6F, 0x60, 0x1A, 0x90, 0x88,
++0x32, 0x12, 0x9F, 0xBB, 0x30, 0xE0, 0x11, 0xEF,
++0x54, 0xBF, 0xD1, 0xC1, 0x12, 0x7C, 0x3B, 0x7D,
++0x01, 0x7F, 0x02, 0x12, 0x7C, 0x74, 0xB1, 0x5D,
++0x90, 0x88, 0x32, 0xE0, 0x44, 0x04, 0xF0, 0x22,
++0x90, 0x88, 0x3C, 0xE0, 0xFF, 0xA3, 0xE0, 0x22,
++0x90, 0x88, 0x34, 0xE0, 0xFF, 0xC4, 0x54, 0x0F,
++0x22, 0xF0, 0x90, 0x01, 0x3F, 0x74, 0x10, 0xF0,
++0xFD, 0x7F, 0x03, 0x22, 0x90, 0x88, 0x3C, 0xE0,
++0x90, 0x05, 0x73, 0x22, 0xE4, 0xFF, 0x12, 0x78,
++0x4A, 0xEF, 0x64, 0x01, 0x22, 0xD1, 0xD4, 0x70,
++0x12, 0x90, 0x88, 0x36, 0xE0, 0x60, 0x0C, 0x90,
++0x88, 0x3A, 0xE0, 0x20, 0xE4, 0x05, 0xD1, 0xF4,
++0x12, 0x97, 0x9F, 0x22, 0x90, 0x01, 0x57, 0xE4,
++0xF0, 0x90, 0x01, 0x3C, 0x74, 0x02, 0x22, 0xD1,
++0xD4, 0x70, 0x1B, 0x90, 0x88, 0x36, 0xE0, 0x60,
++0x15, 0x90, 0x88, 0x3A, 0xE0, 0x20, 0xE4, 0x0E,
++0xD1, 0xF4, 0xF0, 0x90, 0x88, 0x31, 0xE0, 0xF1,
++0xAB, 0x70, 0x03, 0x12, 0x9F, 0xDE, 0x22, 0x90,
++0x88, 0x39, 0xE0, 0x64, 0x02, 0x60, 0x28, 0x90,
++0x88, 0x9D, 0xE0, 0x30, 0xE0, 0x0B, 0x90, 0x94,
++0xAF, 0xE0, 0xFF, 0x12, 0x8F, 0xCC, 0x20, 0xE0,
++0x02, 0xB1, 0x64, 0x90, 0x88, 0x9D, 0xE0, 0x30,
++0xE0, 0x0D, 0x90, 0x94, 0xAF, 0xE0, 0xFF, 0x12,
++0x8F, 0xCC, 0x30, 0xE0, 0x02, 0xF1, 0x50, 0x22,
++0x90, 0x06, 0xA9, 0xE0, 0xF5, 0x77, 0x30, 0xE6,
++0x03, 0x12, 0xCE, 0x56, 0x22, 0x7D, 0x01, 0x7F,
++0x02, 0x02, 0x7C, 0x7E, 0xF0, 0x7F, 0x14, 0x7E,
++0x00, 0x02, 0x7C, 0x6A, 0xE0, 0xFE, 0xA3, 0xE0,
++0xAA, 0x06, 0xF9, 0x22, 0x90, 0x00, 0x02, 0xE0,
++0x54, 0xFE, 0xF0, 0x22, 0x90, 0x88, 0x3A, 0xE0,
++0x44, 0x10, 0xF0, 0x22, 0x90, 0x8A, 0xDF, 0xF1,
++0x6C, 0x02, 0x04, 0x7A, 0x90, 0x01, 0xC7, 0x74,
++0x66, 0xF0, 0xE4, 0xFF, 0x22, 0x90, 0x94, 0xAF,
++0xE0, 0xFE, 0x13, 0x13, 0x54, 0x3F, 0x22, 0x90,
++0x01, 0x95, 0xE0, 0x7F, 0x00, 0x30, 0xE4, 0x02,
++0x7F, 0x01, 0x22, 0x54, 0xFB, 0xF0, 0x90, 0x88,
++0x3A, 0xE0, 0x54, 0xFD, 0xF0, 0x54, 0x07, 0x22,
++0x90, 0x8A, 0x77, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF,
++0xF5, 0x82, 0x8E, 0x83, 0x02, 0x04, 0x7E, 0xF0,
++0x90, 0x88, 0x48, 0xE0, 0xFF, 0xA3, 0xE0, 0xFD,
++0x90, 0x88, 0x4F, 0xE0, 0xFB, 0x90, 0x92, 0x98,
++0x22, 0x12, 0x02, 0x06, 0x90, 0x88, 0x9C, 0xF0,
++0x60, 0x39, 0xA3, 0xE0, 0x20, 0xE0, 0x34, 0x90,
++0x8A, 0xB9, 0x12, 0x8B, 0x03, 0xE4, 0xFD, 0x7F,
++0x04, 0x12, 0x04, 0x7E, 0x90, 0x88, 0x9B, 0xE0,
++0xFF, 0xC3, 0x13, 0x30, 0xE0, 0x1D, 0xEF, 0x13,
++0x13, 0x13, 0x54, 0x1F, 0x20, 0xE0, 0x14, 0x90,
++0x88, 0x9B, 0xE0, 0x13, 0x13, 0x54, 0x3F, 0x30,
++0xE0, 0x04, 0x7F, 0x0D, 0x80, 0x02, 0x7F, 0x09,
++0x12, 0x71, 0x9A, 0x22, 0x12, 0x02, 0x06, 0x54,
++0x01, 0xFF, 0x90, 0x93, 0x32, 0xE0, 0x54, 0xFE,
++0x4F, 0xF0, 0x30, 0xE0, 0x04, 0xE4, 0x12, 0xA6,
++0x44, 0x22, 0x12, 0x02, 0x06, 0xFF, 0x90, 0x93,
++0x4C, 0xF0, 0xBF, 0x01, 0x0A, 0x7F, 0x01, 0x12,
++0x9D, 0x20, 0xE4, 0x90, 0x93, 0x4C, 0xF0, 0x22,
++0x90, 0x95, 0xCE, 0xEF, 0xF0, 0x90, 0x04, 0x7E,
++0xE0, 0xFF, 0xA3, 0xE0, 0x90, 0x95, 0xF2, 0xF0,
++0xE0, 0xFE, 0x6F, 0x60, 0x6E, 0x90, 0x95, 0xCF,
++0x74, 0x03, 0xF0, 0x90, 0x95, 0xF1, 0x74, 0x08,
++0xF0, 0xEE, 0x04, 0x54, 0x0F, 0xFF, 0xE4, 0xFE,
++0xEF, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x00, 0xF5,
++0x82, 0xE4, 0x34, 0x80, 0xF5, 0x83, 0xE5, 0x82,
++0x2E, 0x11, 0xD2, 0xE0, 0xFD, 0x74, 0xD1, 0x2E,
++0xF5, 0x82, 0xE4, 0x34, 0x95, 0xF5, 0x83, 0xED,
++0xF0, 0x0E, 0xEE, 0xB4, 0x08, 0xDA, 0x7B, 0x01,
++0x7A, 0x95, 0x79, 0xCF, 0x12, 0xB7, 0xB8, 0x90,
++0x95, 0xF2, 0xE0, 0x04, 0x54, 0x0F, 0xFF, 0xF0,
++0xBF, 0x0F, 0x02, 0xE4, 0xF0, 0x90, 0x95, 0xF2,
++0xE0, 0x90, 0x04, 0x7F, 0xF0, 0x90, 0x95, 0xCE,
++0xE0, 0x70, 0x05, 0x90, 0x8A, 0xE5, 0x80, 0x03,
++0x90, 0x8A, 0x79, 0x12, 0x8B, 0x03, 0x7F, 0x04,
++0x12, 0x04, 0x7E, 0x22, 0x12, 0x04, 0x6E, 0xE5,
++0x82, 0x2C, 0xF5, 0x82, 0xE4, 0x35, 0x83, 0xF5,
++0x83, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0,
++0xD0, 0x90, 0x01, 0xCC, 0xE0, 0x54, 0x0F, 0xFD,
++0xED, 0x70, 0x02, 0x21, 0xC5, 0x90, 0x87, 0x0B,
++0xE0, 0xFF, 0x70, 0x06, 0xA3, 0xE0, 0x64, 0x09,
++0x60, 0x0A, 0xEF, 0x14, 0xFF, 0x90, 0x87, 0x0C,
++0xE0, 0xB5, 0x07, 0x04, 0x7F, 0x01, 0x80, 0x02,
++0x7F, 0x00, 0xEF, 0x60, 0x09, 0x90, 0x01, 0xC1,
++0xE0, 0x44, 0x01, 0xF0, 0x21, 0xC5, 0x90, 0x97,
++0x0A, 0xE0, 0x12, 0xC4, 0x51, 0x80, 0x05, 0xC3,
++0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, 0xFF, 0xED,
++0xFB, 0xEF, 0x5B, 0x60, 0x7B, 0xE4, 0xFC, 0x31,
++0xCB, 0xA4, 0xFF, 0xEC, 0x7A, 0x00, 0x2F, 0xFF,
++0xEA, 0x35, 0xF0, 0xFE, 0x74, 0xD0, 0x31, 0xDE,
++0x90, 0x87, 0x0C, 0xE0, 0xF9, 0x75, 0xF0, 0x08,
++0x90, 0x86, 0xBB, 0x11, 0xCC, 0xEF, 0x31, 0xCA,
++0xA4, 0xFF, 0xEC, 0x2F, 0xFF, 0xEA, 0x35, 0xF0,
++0xFE, 0x74, 0xF0, 0x31, 0xDE, 0x75, 0xF0, 0x08,
++0xE9, 0x90, 0x86, 0xBF, 0x11, 0xCC, 0xEF, 0xF0,
++0x0C, 0xEC, 0xB4, 0x04, 0xC2, 0x31, 0xD3, 0x80,
++0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4, 0x5D, 0xFD,
++0x31, 0xD3, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC,
++0x90, 0x01, 0xCC, 0xF0, 0x90, 0x97, 0x0A, 0xE0,
++0x04, 0xF0, 0xE0, 0x54, 0x03, 0xF0, 0x90, 0x87,
++0x0C, 0xE0, 0x04, 0xF0, 0xE0, 0x7F, 0x00, 0xB4,
++0x0A, 0x02, 0x7F, 0x01, 0xEF, 0x70, 0x02, 0x01,
++0xE8, 0xE4, 0x90, 0x87, 0x0C, 0xF0, 0x01, 0xE8,
++0x90, 0x01, 0xC0, 0xE0, 0x44, 0x02, 0xF0, 0x90,
++0x97, 0x0A, 0xE0, 0x44, 0x80, 0x90, 0x00, 0x8A,
++0x31, 0xCA, 0x90, 0x01, 0xD0, 0x12, 0x04, 0x6E,
++0xE0, 0x90, 0x01, 0xC3, 0xF0, 0xD0, 0xD0, 0x92,
++0xAF, 0x22, 0xF0, 0x90, 0x97, 0x0A, 0xE0, 0x75,
++0xF0, 0x04, 0x22, 0x90, 0x97, 0x0A, 0xE0, 0xFF,
++0x74, 0x01, 0xA8, 0x07, 0x08, 0x22, 0x2F, 0xF5,
++0x82, 0x74, 0x01, 0x3E, 0xF5, 0x83, 0xE0, 0xFF,
++0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0,
++0x90, 0x96, 0x88, 0xEF, 0xF0, 0x90, 0x88, 0x2B,
++0xE0, 0x90, 0x96, 0x9A, 0xF0, 0xE4, 0x90, 0x96,
++0x89, 0xF0, 0x90, 0x96, 0x9A, 0xE0, 0xFE, 0x90,
++0x96, 0x89, 0xE0, 0xFF, 0xC3, 0x9E, 0x50, 0x2B,
++0xE0, 0xFE, 0x71, 0x08, 0xE4, 0xF0, 0xEE, 0x71,
++0x94, 0xE0, 0x30, 0xE7, 0x0A, 0x75, 0xF0, 0x12,
++0xEF, 0x71, 0x12, 0xE4, 0xF0, 0x80, 0x0C, 0x12,
++0x7C, 0x8F, 0x90, 0x96, 0x89, 0xE0, 0x71, 0x08,
++0x74, 0x01, 0xF0, 0x90, 0x96, 0x89, 0xE0, 0x04,
++0xF0, 0x80, 0xC7, 0x7F, 0x0C, 0x7E, 0x00, 0x12,
++0x7C, 0x6A, 0xE4, 0x90, 0x96, 0x89, 0xF0, 0x90,
++0x96, 0x9A, 0xE0, 0xFF, 0x90, 0x96, 0x89, 0xE0,
++0xFE, 0xC3, 0x9F, 0x40, 0x02, 0x61, 0x03, 0x74,
++0x8A, 0x2E, 0x71, 0x0A, 0xE0, 0x70, 0x02, 0x41,
++0xFB, 0xEE, 0xC4, 0x54, 0xF0, 0x24, 0x06, 0xF5,
++0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFD,
++0xEE, 0xC4, 0x54, 0xF0, 0x24, 0x07, 0xF5, 0x82,
++0xE4, 0x34, 0x81, 0xF5, 0x83, 0x71, 0x18, 0xFC,
++0x75, 0xF0, 0x12, 0x90, 0x89, 0x53, 0x71, 0x21,
++0xEC, 0xC4, 0x54, 0xF0, 0x24, 0x0A, 0xF5, 0x82,
++0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFD, 0xEC,
++0x71, 0x2A, 0x71, 0x18, 0x75, 0xF0, 0x12, 0x90,
++0x89, 0x57, 0x71, 0x21, 0x7F, 0x01, 0x90, 0x96,
++0x89, 0xE0, 0xFE, 0x71, 0x2A, 0xE5, 0x82, 0x2F,
++0x11, 0xD2, 0xE0, 0xFD, 0x75, 0xF0, 0x12, 0xEE,
++0x90, 0x89, 0x57, 0x12, 0x04, 0x6E, 0x75, 0xF0,
++0x02, 0xEF, 0x71, 0x37, 0xED, 0xF0, 0x0F, 0xEF,
++0xB4, 0x05, 0xDB, 0x90, 0x96, 0x89, 0xE0, 0xFF,
++0xC4, 0x54, 0xF0, 0x24, 0x09, 0xF5, 0x82, 0xE4,
++0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFE, 0x71, 0xA1,
++0xEE, 0xF0, 0x90, 0x96, 0x89, 0xE0, 0xFF, 0x90,
++0x96, 0x88, 0xE0, 0xFD, 0x12, 0x61, 0xF7, 0x90,
++0x96, 0x89, 0xE0, 0x75, 0xF0, 0x12, 0x71, 0x12,
++0x74, 0x01, 0xF0, 0x90, 0x96, 0x89, 0xE0, 0x04,
++0xF0, 0x41, 0x47, 0xD0, 0xD0, 0x92, 0xAF, 0x22,
++0x24, 0x8A, 0xF5, 0x82, 0xE4, 0x34, 0x96, 0xF5,
++0x83, 0x22, 0x90, 0x89, 0x56, 0x02, 0x04, 0x6E,
++0xE0, 0xFE, 0xED, 0xFF, 0x90, 0x96, 0x89, 0xE0,
++0x22, 0x12, 0x04, 0x6E, 0xEE, 0xF0, 0xA3, 0xEF,
++0xF0, 0x22, 0xC4, 0x54, 0xF0, 0x24, 0x0B, 0xF5,
++0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0x22, 0x12,
++0x04, 0x6E, 0xE4, 0xF0, 0xA3, 0x22, 0x7D, 0x07,
++0xAF, 0x62, 0xED, 0x30, 0xE0, 0x1E, 0x75, 0xF0,
++0x12, 0xEF, 0x90, 0x89, 0x57, 0x71, 0x87, 0x90,
++0x89, 0x59, 0x71, 0x87, 0x90, 0x89, 0x5B, 0x71,
++0x87, 0x90, 0x89, 0x5D, 0x71, 0x87, 0x90, 0x89,
++0x5F, 0x71, 0x37, 0xF0, 0xED, 0x30, 0xE1, 0x0A,
++0x75, 0xF0, 0x12, 0xEF, 0x90, 0x89, 0x53, 0x71,
++0x37, 0xF0, 0xED, 0x30, 0xE2, 0x04, 0x71, 0xA1,
++0xE4, 0xF0, 0x71, 0x93, 0xE0, 0x54, 0xBF, 0x44,
++0x80, 0xFE, 0x71, 0x93, 0xEE, 0xF0, 0x22, 0x12,
++0x04, 0x6E, 0xE4, 0xF0, 0xA3, 0xF0, 0x75, 0xF0,
++0x12, 0xEF, 0x22, 0xEF, 0xC4, 0x54, 0xF0, 0x24,
++0x03, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83,
++0x22, 0x75, 0xF0, 0x12, 0xEF, 0x90, 0x89, 0x55,
++0x02, 0x04, 0x6E, 0xD3, 0x10, 0xAF, 0x01, 0xC3,
++0xC0, 0xD0, 0x90, 0x97, 0x01, 0xEF, 0xF0, 0x90,
++0x00, 0x8F, 0xE0, 0x30, 0xE6, 0x3B, 0x90, 0x00,
++0x8D, 0xE0, 0x64, 0x01, 0x70, 0x33, 0x90, 0x97,
++0x02, 0xF0, 0x90, 0x97, 0x02, 0xE0, 0xFD, 0x90,
++0x97, 0x01, 0xE0, 0x12, 0x96, 0xD1, 0xE5, 0x82,
++0x2D, 0x11, 0xD2, 0xE0, 0xFB, 0xE4, 0xFF, 0x71,
++0xFE, 0x90, 0x97, 0x02, 0xE0, 0x04, 0xF0, 0xE0,
++0xC3, 0x94, 0x10, 0x40, 0xDD, 0x90, 0x00, 0x8F,
++0xE0, 0x30, 0xE0, 0x05, 0x90, 0x00, 0x8D, 0xE4,
++0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xEF, 0x70,
++0x04, 0x74, 0xF0, 0x80, 0x16, 0xEF, 0xB4, 0x01,
++0x04, 0x74, 0xF4, 0x80, 0x0E, 0xEF, 0xB4, 0x02,
++0x04, 0x74, 0xF8, 0x80, 0x06, 0xEF, 0xB4, 0x03,
++0x0C, 0x74, 0xFC, 0x2D, 0xF5, 0x82, 0xE4, 0x34,
++0x02, 0xF5, 0x83, 0xEB, 0xF0, 0x22, 0xD3, 0x10,
++0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x7F, 0x8F, 0x12,
++0x7B, 0x41, 0xEF, 0x20, 0xE6, 0x02, 0xA1, 0x51,
++0x90, 0x00, 0x8C, 0xE0, 0x90, 0x96, 0xF9, 0xF0,
++0x7F, 0x8D, 0x12, 0x7B, 0x41, 0x90, 0x96, 0xFA,
++0xEF, 0xF0, 0x90, 0x00, 0x8E, 0xE0, 0x90, 0x96,
++0xFB, 0xF0, 0x90, 0x96, 0xFA, 0xE0, 0x24, 0xFC,
++0x60, 0x0F, 0x24, 0x03, 0x60, 0x02, 0xA1, 0x41,
++0x90, 0x96, 0xF9, 0xE0, 0xFF, 0x71, 0xAB, 0xA1,
++0x41, 0x90, 0x96, 0xF9, 0xE0, 0x24, 0xD6, 0x12,
++0x87, 0xC9, 0xFB, 0xE4, 0xFD, 0xFF, 0xB1, 0x5B,
++0x75, 0xF0, 0x12, 0x12, 0x87, 0xBD, 0x13, 0x13,
++0x54, 0x03, 0xFB, 0x0D, 0xE4, 0xFF, 0xB1, 0x5B,
++0x75, 0xF0, 0x12, 0x90, 0x89, 0x52, 0x12, 0x04,
++0x6E, 0x12, 0x8F, 0xCB, 0xFB, 0x0D, 0xE4, 0xFF,
++0xB1, 0x5B, 0x75, 0xF0, 0x12, 0x12, 0x87, 0xBD,
++0xC4, 0x54, 0x03, 0xFB, 0x0D, 0xE4, 0xFF, 0xB1,
++0x5B, 0x75, 0xF0, 0x12, 0xF1, 0x7F, 0xFB, 0xE4,
++0xFD, 0x0F, 0xB1, 0x5B, 0x12, 0xD3, 0x2A, 0xB1,
++0x58, 0x75, 0xF0, 0x12, 0xB1, 0x67, 0xC4, 0x13,
++0x54, 0x01, 0xFB, 0x0D, 0x7F, 0x01, 0xB1, 0x5B,
++0x75, 0xF0, 0x12, 0xB1, 0x67, 0x54, 0x1F, 0xB1,
++0x59, 0xF1, 0x9F, 0xE0, 0xFB, 0xE4, 0xFD, 0x0F,
++0xB1, 0x5B, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x01,
++0xF5, 0x82, 0xE4, 0x34, 0x82, 0xB1, 0x56, 0x75,
++0xF0, 0x08, 0xA4, 0x24, 0x02, 0xF5, 0x82, 0xE4,
++0x34, 0x82, 0xB1, 0x56, 0x75, 0xF0, 0x08, 0xA4,
++0x24, 0x03, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0xB1,
++0x56, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x04, 0xF5,
++0x82, 0xE4, 0x34, 0x82, 0xF5, 0x83, 0xE0, 0xFB,
++0xE4, 0xFD, 0x0F, 0xB1, 0x5B, 0x75, 0xF0, 0x08,
++0xA4, 0x24, 0x05, 0xF5, 0x82, 0xE4, 0x34, 0x82,
++0xB1, 0x56, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x06,
++0xF5, 0x82, 0xE4, 0x34, 0x82, 0xB1, 0x56, 0x75,
++0xF0, 0x08, 0xA4, 0x24, 0x07, 0xF5, 0x82, 0xE4,
++0x34, 0x82, 0xF5, 0x83, 0xE0, 0xFB, 0x0D, 0x71,
++0xFE, 0x7F, 0x8F, 0x12, 0x7B, 0x41, 0xEF, 0x30,
++0xE0, 0x07, 0xE4, 0xFD, 0x7F, 0x8D, 0x12, 0x7B,
++0x2E, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xF5, 0x83,
++0xE0, 0xFB, 0x0D, 0x71, 0xFE, 0x90, 0x96, 0xF9,
++0xE0, 0x22, 0xFF, 0x75, 0xF0, 0x12, 0xED, 0x90,
++0x89, 0x51, 0x12, 0x04, 0x6E, 0xE0, 0x22, 0x90,
++0x96, 0xCE, 0x12, 0x9F, 0xB5, 0x54, 0x7F, 0xFD,
++0x12, 0x87, 0x9F, 0x54, 0x1F, 0xB1, 0x62, 0x54,
++0xE0, 0x4F, 0xF0, 0x12, 0x87, 0x9F, 0xFE, 0x54,
++0x60, 0xC4, 0x13, 0x54, 0x07, 0x90, 0x96, 0xD1,
++0xF0, 0xEE, 0x54, 0x80, 0x12, 0x8F, 0xCC, 0xC4,
++0x33, 0x54, 0xE0, 0xB1, 0x62, 0x54, 0xDF, 0x12,
++0x87, 0x25, 0xFE, 0x54, 0x03, 0xFC, 0xEE, 0x54,
++0x30, 0xC4, 0x54, 0x03, 0xC4, 0x54, 0xF0, 0x12,
++0x87, 0xB8, 0x54, 0xCF, 0x12, 0x87, 0x25, 0x54,
++0x40, 0xC4, 0xF1, 0xDE, 0x54, 0xC0, 0x12, 0x87,
++0xB8, 0x54, 0xBF, 0x12, 0x87, 0x25, 0x54, 0x80,
++0x12, 0x8F, 0xCC, 0xC4, 0x33, 0x33, 0x33, 0x54,
++0x80, 0x12, 0x87, 0xB8, 0x54, 0x7F, 0x12, 0x87,
++0x25, 0xFE, 0x54, 0x08, 0x13, 0x13, 0x13, 0x54,
++0x1F, 0x90, 0x96, 0xD3, 0xF0, 0xFB, 0xEE, 0x54,
++0x04, 0x13, 0x13, 0x54, 0x3F, 0xA3, 0xF0, 0xEC,
++0x54, 0x03, 0x12, 0x87, 0xB8, 0x54, 0xFC, 0x4F,
++0xF0, 0xEB, 0x70, 0x0E, 0xEC, 0x54, 0x03, 0x25,
++0xE0, 0x25, 0xE0, 0x12, 0x87, 0xB8, 0x54, 0xF3,
++0x4F, 0xF0, 0xD1, 0xA2, 0xF5, 0x83, 0xE0, 0x54,
++0xFB, 0xF0, 0xD1, 0xA2, 0xF5, 0x83, 0xC0, 0x83,
++0xC0, 0x82, 0xE0, 0xFF, 0x90, 0x96, 0xD4, 0xE0,
++0x12, 0xE4, 0xCF, 0xD0, 0x82, 0xD0, 0x83, 0xF0,
++0x90, 0x93, 0x53, 0xE0, 0x60, 0x34, 0x90, 0x96,
++0xCE, 0x12, 0x86, 0x6D, 0xE9, 0x24, 0x03, 0xF9,
++0xE4, 0x3A, 0xFA, 0x12, 0x02, 0x06, 0x54, 0x1F,
++0x12, 0x02, 0x4C, 0x90, 0x96, 0xD2, 0x74, 0x01,
++0xF0, 0x90, 0x96, 0xD2, 0xE0, 0xFF, 0xC3, 0x94,
++0x04, 0x50, 0x0F, 0xEF, 0xD1, 0xAB, 0xE4, 0x12,
++0x02, 0x5E, 0x90, 0x96, 0xD2, 0xE0, 0x04, 0xF0,
++0x80, 0xE7, 0x90, 0x93, 0x51, 0xE0, 0x54, 0x07,
++0xFF, 0xBF, 0x05, 0x0A, 0xEC, 0xB4, 0x01, 0x06,
++0x90, 0x93, 0x56, 0x74, 0x01, 0xF0, 0xE4, 0x90,
++0x96, 0xD2, 0xF0, 0x90, 0x96, 0xD2, 0xE0, 0xFC,
++0xD1, 0xAB, 0x12, 0x02, 0x1F, 0xFF, 0xED, 0xF1,
++0x9F, 0x11, 0xCF, 0xEF, 0xF0, 0x90, 0x96, 0xD2,
++0xE0, 0x04, 0xF0, 0xE0, 0xB4, 0x04, 0xE4, 0xAF,
++0x05, 0x90, 0x8A, 0xFF, 0x12, 0xDD, 0x87, 0x02,
++0x04, 0x7E, 0x74, 0xC6, 0x2D, 0xF5, 0x82, 0xE4,
++0x34, 0x8D, 0x22, 0x24, 0x03, 0xFF, 0xE4, 0x33,
++0xFE, 0x90, 0x96, 0xCE, 0x12, 0x86, 0x6D, 0x8F,
++0x82, 0x8E, 0x83, 0x22, 0x8F, 0x70, 0x8D, 0x71,
++0xEF, 0x12, 0x96, 0xD1, 0xE0, 0xFD, 0x54, 0x7F,
++0xF5, 0x72, 0xED, 0x54, 0x80, 0xF5, 0x73, 0xF1,
++0x7B, 0xF5, 0x75, 0x75, 0xF0, 0x12, 0xEF, 0x12,
++0x87, 0xBD, 0xC4, 0x54, 0x03, 0xF5, 0x76, 0xF1,
++0x93, 0x74, 0xFF, 0xF0, 0xF1, 0xAD, 0xE5, 0x73,
++0x4D, 0xFF, 0xF1, 0x87, 0xEF, 0xF0, 0xE5, 0x70,
++0x12, 0x95, 0xE2, 0xE0, 0x54, 0x03, 0xF5, 0x74,
++0x74, 0x46, 0x25, 0x70, 0xF5, 0x82, 0xE4, 0x34,
++0x8E, 0xF5, 0x83, 0xE5, 0x74, 0xF0, 0xE5, 0x72,
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++0xE0, 0x0B, 0xE5, 0x73, 0x70, 0x07, 0xE5, 0x72,
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++0x07, 0xAF, 0x70, 0x61, 0x42, 0xE5, 0x72, 0xC3,
++0x95, 0x75, 0x50, 0x34, 0xAB, 0x70, 0xAD, 0x75,
++0xAF, 0x72, 0x12, 0x72, 0x7F, 0xAD, 0x07, 0xE5,
++0x72, 0xC3, 0x94, 0x0C, 0x40, 0x28, 0x75, 0xF0,
++0x12, 0xE5, 0x70, 0xB1, 0x67, 0xFE, 0xC4, 0x13,
++0x54, 0x07, 0x30, 0xE0, 0x19, 0xE5, 0x71, 0x60,
++0x15, 0xE5, 0x73, 0x70, 0x11, 0xE5, 0x72, 0x44,
++0x80, 0xFD, 0xF1, 0x93, 0xEF, 0xF0, 0x80, 0x06,
++0xF1, 0x87, 0xE5, 0x75, 0xF0, 0xFD, 0x90, 0x92,
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++0x89, 0x4F, 0x12, 0x04, 0x6E, 0xE0, 0x22, 0x74,
++0xC6, 0x25, 0x70, 0xF5, 0x82, 0xE4, 0x34, 0x8E,
++0xF5, 0x83, 0x22, 0x74, 0x29, 0x25, 0x70, 0xF5,
++0x82, 0xE4, 0x34, 0x96, 0xF5, 0x83, 0x22, 0x75,
++0xF0, 0x08, 0xA4, 0x24, 0x00, 0xF5, 0x82, 0xE4,
++0x34, 0x82, 0xF5, 0x83, 0x22, 0xE5, 0x72, 0x25,
++0xE0, 0x24, 0x75, 0xF5, 0x82, 0xE4, 0x34, 0x81,
++0xF5, 0x83, 0xE4, 0x93, 0xFE, 0x74, 0x01, 0x93,
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++0x82, 0xE4, 0x34, 0x8D, 0xF5, 0x83, 0xEE, 0xF0,
++0xA3, 0xEF, 0xF0, 0x22, 0x81, 0x26, 0xE4, 0xFF,
++0x01, 0x48, 0xE4, 0xFF, 0x21, 0xE9, 0x13, 0x13,
++0x54, 0x01, 0xC4, 0x33, 0x33, 0x22, 0x90, 0x01,
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++0xF0, 0x90, 0x95, 0x07, 0xE0, 0xFF, 0xC3, 0x94,
++0x10, 0x50, 0x27, 0xEF, 0x11, 0x9B, 0x7A, 0x95,
++0x79, 0x06, 0x12, 0x5F, 0xA6, 0xBF, 0x01, 0x12,
++0x90, 0x95, 0x06, 0xE0, 0xFF, 0xA3, 0xE0, 0x24,
++0x08, 0xF5, 0x82, 0xE4, 0x34, 0x95, 0xF5, 0x83,
++0xEF, 0xF0, 0x90, 0x95, 0x07, 0xE0, 0x04, 0xF0,
++0x80, 0xCF, 0x75, 0x45, 0x01, 0x75, 0x46, 0x95,
++0x75, 0x47, 0x08, 0x75, 0x48, 0x08, 0x7B, 0x01,
++0x7A, 0x94, 0x79, 0xC2, 0x12, 0x69, 0xF5, 0x90,
++0x94, 0xC0, 0x74, 0x24, 0xF0, 0x90, 0x94, 0xE2,
++0x74, 0x08, 0xF0, 0x75, 0x45, 0x01, 0x75, 0x46,
++0x95, 0x75, 0x47, 0x10, 0xF5, 0x48, 0x7B, 0x01,
++0x7A, 0x94, 0x79, 0xE5, 0x12, 0x69, 0xF5, 0x90,
++0x94, 0xE3, 0x74, 0x25, 0xF0, 0x90, 0x95, 0x05,
++0x74, 0x08, 0xF0, 0x7B, 0x01, 0x7A, 0x94, 0x79,
++0xC0, 0x12, 0xB7, 0xB8, 0x7B, 0x01, 0x7A, 0x94,
++0x79, 0xE3, 0x12, 0x8A, 0xF1, 0x7F, 0x04, 0x12,
++0x04, 0x7E, 0x22, 0x24, 0xA8, 0xFF, 0xE4, 0x34,
++0x01, 0xFE, 0x7B, 0x01, 0x22, 0x90, 0x94, 0xC0,
++0x12, 0x9F, 0xB5, 0x64, 0x01, 0x60, 0x02, 0x21,
++0x36, 0xEF, 0x24, 0x39, 0x60, 0x12, 0x14, 0x60,
++0x19, 0x24, 0x02, 0x70, 0x1F, 0xE4, 0x90, 0x94,
++0xC6, 0xF0, 0xA3, 0x74, 0x06, 0xF0, 0x80, 0x14,
++0x90, 0x94, 0xC6, 0x74, 0x06, 0xF0, 0xA3, 0xF0,
++0x80, 0x0A, 0x90, 0x94, 0xC6, 0x74, 0x0C, 0xF0,
++0xA3, 0x74, 0x04, 0xF0, 0x31, 0x4A, 0x31, 0x37,
++0x40, 0x1B, 0x90, 0x94, 0xC4, 0xE0, 0x11, 0x9B,
++0x7A, 0x94, 0x79, 0xC3, 0x12, 0x5F, 0xA6, 0xBF,
++0x01, 0x07, 0x90, 0x94, 0xC3, 0xE0, 0xF4, 0x70,
++0x3D, 0x31, 0x3F, 0x80, 0xE1, 0x31, 0x4A, 0x31,
++0x37, 0x40, 0x33, 0x90, 0x94, 0xC4, 0xE0, 0xFD,
++0x7C, 0x00, 0x24, 0xA8, 0xFF, 0xEC, 0x34, 0x01,
++0xFE, 0xED, 0x24, 0x01, 0xFD, 0xEC, 0x33, 0xFC,
++0x90, 0x94, 0xC6, 0xE0, 0xFB, 0xC3, 0xED, 0x9B,
++0xFD, 0xEC, 0x94, 0x00, 0xFC, 0x12, 0x90, 0xD3,
++0x8D, 0x82, 0x8C, 0x83, 0x12, 0x02, 0x1F, 0xFD,
++0x31, 0x5B, 0x31, 0x3F, 0x80, 0xC9, 0x22, 0x90,
++0x94, 0xC5, 0xE0, 0xD3, 0x94, 0x00, 0x22, 0x90,
++0x94, 0xC4, 0xE0, 0x04, 0xF0, 0xA3, 0xE0, 0x14,
++0xF0, 0x22, 0x90, 0x94, 0xC6, 0xE0, 0x90, 0x94,
++0xC4, 0xF0, 0x90, 0x94, 0xC7, 0xE0, 0x90, 0x94,
++0xC5, 0xF0, 0x22, 0xE4, 0x90, 0x94, 0xC8, 0xF0,
++0x90, 0x00, 0x37, 0xE0, 0x44, 0x80, 0xF0, 0x90,
++0x00, 0xCF, 0x74, 0x69, 0xF0, 0xEF, 0x90, 0x00,
++0x31, 0xF0, 0xEE, 0x54, 0x03, 0xFF, 0xA3, 0xE0,
++0x54, 0xFC, 0x4F, 0xF0, 0x90, 0x00, 0x30, 0xED,
++0xF0, 0x90, 0x00, 0x33, 0xE0, 0x44, 0x80, 0xF0,
++0x90, 0x00, 0x33, 0xE0, 0x30, 0xE7, 0x09, 0x31,
++0xAD, 0x50, 0x05, 0xE0, 0x04, 0xF0, 0x80, 0xF0,
++0x90, 0x00, 0xCF, 0xE4, 0xF0, 0x90, 0x00, 0x37,
++0xE0, 0x54, 0x7F, 0xF0, 0x31, 0xAD, 0x7F, 0x00,
++0x50, 0x02, 0x7F, 0x01, 0x22, 0x90, 0x94, 0xC8,
++0xE0, 0xC3, 0x94, 0x64, 0x22, 0xE4, 0x90, 0x86,
++0xAF, 0x12, 0xA6, 0x43, 0x90, 0x93, 0x01, 0xF0,
++0x90, 0x93, 0x5E, 0xF0, 0xA3, 0xF0, 0x22, 0x75,
++0x21, 0x80, 0xE4, 0xF5, 0x22, 0xF5, 0x23, 0x75,
++0x24, 0x80, 0x90, 0x00, 0x50, 0xE5, 0x21, 0xF0,
++0xA3, 0xE5, 0x22, 0xF0, 0xA3, 0xE5, 0x23, 0xF0,
++0xA3, 0xE5, 0x24, 0xF0, 0x22, 0x31, 0xF3, 0x12,
++0x76, 0x6D, 0x12, 0x75, 0xE0, 0xD1, 0x18, 0xF1,
++0xC8, 0x80, 0xD4, 0x90, 0x00, 0x08, 0xE0, 0x54,
++0xEF, 0xF0, 0x22, 0xE4, 0x90, 0x95, 0x1B, 0xF0,
++0xF1, 0xA9, 0x31, 0xF3, 0xE4, 0xFF, 0x91, 0xB3,
++0x90, 0x93, 0x32, 0xE0, 0x20, 0xE0, 0x02, 0x41,
++0xEC, 0x90, 0x00, 0x02, 0xE0, 0x44, 0x02, 0xF0,
++0xE4, 0x90, 0x95, 0x1C, 0xF0, 0x90, 0x95, 0x1C,
++0xE0, 0xFF, 0xC3, 0x94, 0x05, 0x50, 0x2C, 0x91,
++0x52, 0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE,
++0xD8, 0xF9, 0xFF, 0x90, 0x93, 0x35, 0xE0, 0xFD,
++0xEF, 0x5D, 0x60, 0x0F, 0x90, 0x95, 0x1C, 0x91,
++0x72, 0x90, 0x95, 0x1C, 0x91, 0x92, 0x44, 0x40,
++0x12, 0xB7, 0x64, 0x90, 0x95, 0x1C, 0xE0, 0x04,
++0xF0, 0x80, 0xCA, 0x90, 0x07, 0xC7, 0xE4, 0xF0,
++0x90, 0x07, 0xC6, 0xF0, 0x90, 0x07, 0xC5, 0x74,
++0x77, 0xF0, 0x90, 0x07, 0xC4, 0xE4, 0xF0, 0x90,
++0x07, 0xC0, 0x74, 0x38, 0xF0, 0xA3, 0xE4, 0xF0,
++0xA3, 0x74, 0x0F, 0xF0, 0xA3, 0x74, 0xC0, 0xF0,
++0x90, 0x02, 0x26, 0xE0, 0x44, 0x01, 0xF0, 0xE0,
++0x90, 0x95, 0x1D, 0xF0, 0x90, 0x95, 0x1D, 0xE0,
++0x30, 0xE0, 0x18, 0x90, 0x95, 0x1B, 0xE0, 0x04,
++0xD1, 0x51, 0x90, 0x02, 0x26, 0xE0, 0x90, 0x95,
++0x1D, 0xF0, 0x90, 0x95, 0x1B, 0xE0, 0xD3, 0x94,
++0xFA, 0x40, 0xE1, 0x90, 0x02, 0x03, 0x74, 0x80,
++0xF0, 0x90, 0x04, 0x24, 0xE0, 0x90, 0x95, 0x1E,
++0xF0, 0x90, 0x04, 0x22, 0xE0, 0x44, 0x10, 0xF0,
++0x90, 0x02, 0x00, 0xE0, 0x90, 0x95, 0x1D, 0xF0,
++0x90, 0x02, 0x01, 0x51, 0xFB, 0x90, 0x02, 0x02,
++0x51, 0xFB, 0x90, 0x02, 0x14, 0x51, 0xFB, 0xE0,
++0x04, 0xF0, 0xE0, 0x90, 0x04, 0x24, 0xF0, 0xD1,
++0x59, 0x90, 0x95, 0x1E, 0xE0, 0x90, 0x04, 0x24,
++0xF0, 0x90, 0xFD, 0x09, 0x74, 0xFF, 0xF0, 0x90,
++0xFD, 0x08, 0xE4, 0xF0, 0x91, 0x5A, 0xE4, 0xFD,
++0x12, 0x76, 0xF7, 0x90, 0x88, 0x32, 0xE0, 0x54,
++0xEF, 0xF0, 0x22, 0xE0, 0xFF, 0x90, 0x95, 0x1D,
++0xE0, 0x2F, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01,
++0xC3, 0xC0, 0xD0, 0x71, 0x2D, 0x31, 0xFB, 0xD0,
++0xD0, 0x92, 0xAF, 0x22, 0x90, 0x88, 0x39, 0xE0,
++0xFF, 0x60, 0x03, 0xB4, 0x08, 0x0E, 0x12, 0xE0,
++0x2B, 0xBF, 0x01, 0x08, 0x71, 0x04, 0x90, 0x01,
++0xE5, 0xE0, 0x04, 0xF0, 0x22, 0x75, 0x61, 0x14,
++0x90, 0x88, 0x32, 0xE0, 0x44, 0x10, 0xF0, 0x91,
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++0x05, 0x74, 0x20, 0x2F, 0xF5, 0x82, 0xE4, 0x34,
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++0xE0, 0xFF, 0xAE, 0x05, 0x74, 0x18, 0x2E, 0xF5,
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++0xFF, 0xF0, 0x74, 0x29, 0x2F, 0xF5, 0x82, 0xE4,
++0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xF7, 0xF0,
++0x74, 0x0D, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC,
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++0x21, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5,
++0x83, 0x22, 0x90, 0x96, 0xE3, 0xA3, 0xE0, 0xFF,
++0x24, 0x12, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5,
++0x83, 0xE0, 0x54, 0x01, 0xFE, 0x90, 0x96, 0xE2,
++0xE0, 0x25, 0xE0, 0x25, 0xE0, 0x44, 0x02, 0x4E,
++0xFE, 0x74, 0x12, 0x2F, 0xF5, 0x82, 0xE4, 0x34,
++0xFC, 0xF5, 0x83, 0x22, 0x90, 0x97, 0x0B, 0xED,
++0xF0, 0x64, 0x01, 0x60, 0x27, 0xE0, 0xFE, 0x64,
++0x02, 0x60, 0x21, 0xEE, 0x64, 0x29, 0x60, 0x1C,
++0xEE, 0x64, 0x2A, 0x60, 0x17, 0xEE, 0x64, 0x36,
++0x60, 0x12, 0xEE, 0xB4, 0x37, 0x02, 0x80, 0x0C,
++0xAD, 0x07, 0x7F, 0xFF, 0x12, 0xAB, 0x85, 0x90,
++0x93, 0x5F, 0xE0, 0xFF, 0x90, 0x93, 0x5E, 0xE0,
++0x4F, 0x90, 0x05, 0x22, 0xF0, 0x90, 0x97, 0x0B,
++0xE0, 0x90, 0x93, 0x01, 0xF0, 0x22, 0xE6, 0xFD,
++0xAF, 0x62, 0xEF, 0x12, 0xA7, 0xDB, 0xE0, 0x54,
++0xF8, 0xF5, 0x70, 0xED, 0x42, 0x70, 0xEF, 0x12,
++0xA7, 0xDB, 0xE5, 0x70, 0xF0, 0x22, 0xE4, 0xF5,
++0x75, 0xEF, 0x14, 0xF5, 0x74, 0xED, 0xFF, 0xE5,
++0x74, 0xF5, 0x82, 0x33, 0x95, 0xE0, 0xF5, 0x83,
++0xC3, 0xE5, 0x82, 0x9F, 0x74, 0x80, 0xF8, 0x65,
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++0xA2, 0xE7, 0x13, 0xD8, 0xFB, 0xFF, 0x33, 0x95,
++0xE0, 0xFE, 0xEB, 0x12, 0xBF, 0x9F, 0xE5, 0x82,
++0x2F, 0xF5, 0x82, 0xE5, 0x83, 0x3E, 0xF5, 0x83,
++0xE0, 0xF5, 0x82, 0x75, 0x83, 0x00, 0xE5, 0x74,
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++0x33, 0xCE, 0xD8, 0xF9, 0xFF, 0xEE, 0x55, 0x83,
++0xFE, 0xEF, 0x55, 0x82, 0x4E, 0x60, 0x13, 0x85,
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++0x65, 0x75, 0x60, 0x0A, 0xE5, 0x76, 0xD3, 0x9D,
++0x40, 0x04, 0x15, 0x74, 0x80, 0x97, 0xAF, 0x76,
++0x22, 0xAA, 0x07, 0xA9, 0x05, 0xEA, 0x12, 0x96,
++0xD1, 0xE0, 0xF5, 0x70, 0x54, 0x7F, 0xF5, 0x72,
++0x75, 0xF0, 0x12, 0xEA, 0x71, 0x2D, 0xE0, 0x90,
++0x95, 0x52, 0xF0, 0x75, 0xF0, 0x12, 0xEA, 0x12,
++0xBF, 0x7F, 0xFF, 0xEA, 0x12, 0x95, 0xE2, 0xE0,
++0x54, 0x03, 0xF5, 0x71, 0xE5, 0x72, 0x90, 0x81,
++0x9D, 0x93, 0xFD, 0xEA, 0x71, 0x22, 0x34, 0x8D,
++0xF5, 0x83, 0xE4, 0xF0, 0xA3, 0xED, 0xF0, 0x75,
++0xF0, 0x12, 0xEA, 0x12, 0x87, 0xBD, 0xFE, 0xC4,
++0x54, 0x03, 0x90, 0x95, 0x51, 0xF0, 0x74, 0xC6,
++0x2A, 0x12, 0xBF, 0x8B, 0xE5, 0x72, 0xF0, 0x74,
++0x46, 0x2A, 0xF5, 0x82, 0xE4, 0x34, 0x8E, 0xF5,
++0x83, 0xE5, 0x71, 0xF0, 0xE5, 0x72, 0xD3, 0x9F,
++0x40, 0x04, 0x8F, 0x72, 0x8F, 0x70, 0x89, 0x73,
++0xE4, 0xFF, 0xEF, 0xC3, 0x95, 0x73, 0x50, 0x33,
++0xE5, 0x70, 0x30, 0xE7, 0x09, 0x85, 0x72, 0x70,
++0x19, 0xE9, 0x70, 0x24, 0x80, 0x25, 0x90, 0x95,
++0x52, 0xE0, 0xFD, 0xE5, 0x72, 0xD3, 0x9D, 0x40,
++0x0F, 0xAB, 0x02, 0x90, 0x95, 0x56, 0xE9, 0xF0,
++0xAF, 0x72, 0x31, 0xF6, 0x8F, 0x70, 0x80, 0x0B,
++0x90, 0x95, 0x52, 0xE0, 0xF5, 0x70, 0x80, 0x03,
++0x0F, 0x80, 0xC7, 0xAF, 0x02, 0x90, 0x92, 0x80,
++0xE5, 0x71, 0xF0, 0xE4, 0xFB, 0xAD, 0x70, 0x02,
++0x75, 0x80, 0x25, 0xE0, 0x24, 0x75, 0xF5, 0x82,
++0xE4, 0x22, 0x75, 0xF0, 0x12, 0x90, 0x89, 0x50,
++0x02, 0x04, 0x6E, 0xEF, 0x64, 0x13, 0x60, 0x04,
++0xEF, 0xB4, 0x0B, 0x05, 0x90, 0x88, 0xE3, 0x80,
++0x1F, 0xEF, 0x64, 0x12, 0x60, 0x04, 0xEF, 0xB4,
++0x0A, 0x05, 0x90, 0x88, 0xE4, 0x80, 0x11, 0xEF,
++0x64, 0x11, 0x60, 0x04, 0xEF, 0xB4, 0x09, 0x05,
++0x90, 0x88, 0xE5, 0x80, 0x03, 0x90, 0x88, 0xE2,
++0xE0, 0xF5, 0x0F, 0xAF, 0x0F, 0x22, 0x90, 0x04,
++0x85, 0xE0, 0xF5, 0x6B, 0x90, 0x96, 0x28, 0xE0,
++0x04, 0xF0, 0xE4, 0xF5, 0x62, 0x90, 0x88, 0x2B,
++0xE0, 0xFF, 0xE5, 0x62, 0xC3, 0x9F, 0x40, 0x03,
++0x02, 0xDA, 0x24, 0xE5, 0x62, 0x12, 0x96, 0xD1,
++0xE0, 0xF5, 0x6D, 0x12, 0xE4, 0x72, 0xF5, 0x83,
++0xE0, 0x65, 0x6D, 0x60, 0x17, 0x90, 0x96, 0x41,
++0x74, 0x06, 0xF0, 0xE4, 0xFB, 0xAD, 0x6D, 0xAF,
++0x62, 0x12, 0x96, 0x6C, 0x12, 0xE4, 0x72, 0xF5,
++0x83, 0xE5, 0x6D, 0xF0, 0x90, 0x04, 0xA0, 0xE0,
++0x64, 0x01, 0x70, 0x4B, 0xA3, 0xE0, 0x65, 0x62,
++0x70, 0x45, 0xA3, 0xE0, 0xF5, 0x63, 0xA3, 0xE0,
++0x90, 0x95, 0x4E, 0xF0, 0xE5, 0x62, 0x12, 0x96,
++0xD1, 0xE0, 0x65, 0x63, 0x70, 0x03, 0x02, 0xDA,
++0x1F, 0xE5, 0x62, 0x12, 0x96, 0xD1, 0xE5, 0x63,
++0xF0, 0x12, 0x95, 0xE0, 0xE0, 0x54, 0xFC, 0xFF,
++0x90, 0x95, 0x4E, 0xE0, 0x54, 0x03, 0x4F, 0xFF,
++0x12, 0x95, 0xE0, 0xEF, 0xF0, 0x90, 0x96, 0x41,
++0x74, 0x07, 0xF0, 0xE4, 0xFB, 0xAD, 0x63, 0xAF,
++0x62, 0x12, 0x96, 0x6C, 0x02, 0xDA, 0x1F, 0x75,
++0xF0, 0x12, 0xE5, 0x62, 0x12, 0xBB, 0xA5, 0xE0,
++0xFF, 0x90, 0x95, 0x46, 0xE4, 0xF0, 0xA3, 0xEF,
++0xF0, 0x75, 0xF0, 0x12, 0xE5, 0x62, 0x90, 0x89,
++0x53, 0x12, 0x04, 0x6E, 0xE0, 0xF5, 0x68, 0xA3,
++0xE0, 0xF5, 0x69, 0xE5, 0x62, 0x75, 0xF0, 0x12,
++0xA4, 0x24, 0x57, 0xF9, 0x74, 0x89, 0x35, 0xF0,
++0xFA, 0x7B, 0x01, 0x90, 0x95, 0x43, 0x12, 0x86,
++0x76, 0x12, 0xE4, 0x66, 0xFF, 0x12, 0x03, 0x13,
++0x2F, 0xFF, 0x12, 0xE4, 0x6C, 0x2F, 0xFF, 0x12,
++0xE4, 0x1B, 0x2F, 0xFF, 0x12, 0xE4, 0x4C, 0x2F,
++0xF5, 0x6C, 0xE5, 0x62, 0x12, 0x96, 0xD1, 0xE0,
++0xF5, 0x63, 0x54, 0x80, 0xF5, 0x65, 0xE5, 0x63,
++0x54, 0x7F, 0xF5, 0x64, 0x75, 0xF0, 0x12, 0xE5,
++0x62, 0x12, 0xBB, 0x12, 0xE0, 0x64, 0x01, 0x60,
++0x02, 0xA1, 0xDF, 0x12, 0xDA, 0x56, 0x12, 0xE4,
++0x66, 0xFF, 0xAE, 0xF0, 0x12, 0x03, 0x13, 0x2F,
++0xFF, 0xE5, 0xF0, 0x3E, 0xFE, 0x12, 0xE4, 0x6C,
++0x2F, 0xFF, 0xEE, 0x12, 0xE4, 0x18, 0x2F, 0xFF,
++0xEE, 0x35, 0xF0, 0xFE, 0x12, 0xE4, 0x4C, 0x2F,
++0xFF, 0xEE, 0x35, 0xF0, 0x90, 0x95, 0x48, 0xF0,
++0xA3, 0xEF, 0xF0, 0x12, 0x03, 0x13, 0xFF, 0xC3,
++0x90, 0x95, 0x49, 0xE0, 0x9F, 0xFE, 0x90, 0x95,
++0x48, 0xE0, 0x95, 0xF0, 0x90, 0x95, 0x4A, 0xF0,
++0xA3, 0xCE, 0xF0, 0x12, 0xE4, 0x1B, 0xFD, 0xAC,
++0xF0, 0x25, 0xE0, 0xFF, 0xEC, 0x33, 0xFE, 0xEF,
++0x2D, 0xFD, 0xEE, 0x3C, 0xFC, 0x12, 0xE4, 0x6C,
++0x25, 0xE0, 0xFF, 0xE5, 0xF0, 0x33, 0xFE, 0x12,
++0xE4, 0x66, 0x2F, 0xFF, 0xEE, 0x35, 0xF0, 0xCF,
++0x2D, 0xFD, 0xEF, 0x3C, 0xFC, 0x12, 0xDA, 0x56,
++0x12, 0xE4, 0x4C, 0xAE, 0xF0, 0x78, 0x02, 0xC3,
++0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, 0x2D, 0xFF,
++0xEC, 0x3E, 0x90, 0x95, 0x4C, 0xF0, 0xA3, 0xEF,
++0xF0, 0x90, 0x95, 0x46, 0x12, 0xE3, 0xE2, 0x12,
++0xE4, 0xA0, 0x34, 0x8E, 0x12, 0xE3, 0xD7, 0x9E,
++0x50, 0x08, 0x90, 0x95, 0x46, 0x12, 0xE4, 0x01,
++0x80, 0x04, 0x7E, 0xFF, 0x7F, 0xFF, 0xE5, 0x62,
++0x12, 0xE4, 0xA0, 0x34, 0x8E, 0x12, 0xBF, 0xCC,
++0x90, 0x95, 0x48, 0x12, 0xE3, 0xE2, 0x12, 0xE4,
++0xA8, 0x34, 0x8E, 0x12, 0xE3, 0xD7, 0x9E, 0x50,
++0x08, 0x90, 0x95, 0x48, 0x12, 0xE4, 0x01, 0x80,
++0x04, 0x7E, 0xFF, 0x7F, 0xFF, 0xE5, 0x62, 0x12,
++0xE4, 0xA8, 0x34, 0x8E, 0x12, 0xBF, 0xCC, 0x90,
++0x95, 0x4C, 0x12, 0xE3, 0xE2, 0x12, 0xE4, 0xB0,
++0x34, 0x8E, 0x12, 0xE3, 0xD7, 0x9E, 0x50, 0x08,
++0x90, 0x95, 0x4C, 0x12, 0xE4, 0x01, 0x80, 0x04,
++0x7E, 0xFF, 0x7F, 0xFF, 0xE5, 0x62, 0x12, 0xE4,
++0xB0, 0x34, 0x8E, 0x12, 0xBF, 0xCC, 0xC3, 0x74,
++0xFF, 0x95, 0x69, 0xFF, 0x74, 0xFF, 0x95, 0x68,
++0xFE, 0x12, 0xE4, 0x5C, 0x34, 0x8E, 0x12, 0xE3,
++0xD7, 0x9E, 0x50, 0x0A, 0xE5, 0x69, 0x2D, 0xFF,
++0xE5, 0x68, 0x3C, 0xFE, 0x80, 0x04, 0x7E, 0xFF,
++0x7F, 0xFF, 0x12, 0xE4, 0x5C, 0x34, 0x8E, 0x12,
++0xBF, 0xCC, 0x12, 0xE4, 0xDF, 0xFB, 0xC3, 0x74,
++0xFF, 0x9B, 0xFF, 0x74, 0xFF, 0x9E, 0xFE, 0x74,
++0xFF, 0x94, 0x00, 0xFD, 0x74, 0xFF, 0x94, 0x00,
++0xFC, 0x90, 0x8D, 0x71, 0x12, 0xE4, 0xC0, 0x50,
++0x12, 0x12, 0xE4, 0xDF, 0xFF, 0xE4, 0xFC, 0xFD,
++0x90, 0x8D, 0x71, 0x12, 0x86, 0x61, 0x12, 0x86,
++0x2C, 0x80, 0x06, 0x74, 0xFF, 0xFF, 0xFE, 0xFD,
++0xFC, 0x90, 0x8D, 0x71, 0x12, 0x04, 0x31, 0xAF,
++0x62, 0x12, 0x78, 0x4A, 0xEF, 0x70, 0x03, 0x02,
++0xDA, 0x1F, 0x75, 0xF0, 0x12, 0xE5, 0x62, 0x90,
++0x89, 0x52, 0x12, 0x04, 0x6E, 0x12, 0x8F, 0xCB,
++0x30, 0xE0, 0x03, 0x02, 0xDA, 0x1F, 0xE5, 0x62,
++0x13, 0x13, 0x13, 0x54, 0x1F, 0x12, 0xE4, 0x0E,
++0xE0, 0xFD, 0x7C, 0x00, 0xE5, 0x62, 0x12, 0xC4,
++0x4F, 0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE,
++0xD8, 0xF9, 0xFF, 0xEE, 0x5C, 0xFE, 0xEF, 0x5D,
++0x4E, 0x60, 0x03, 0x02, 0xDA, 0x1F, 0xE5, 0x69,
++0x45, 0x68, 0x70, 0x0D, 0x90, 0x95, 0x46, 0xE0,
++0x70, 0x02, 0xA3, 0xE0, 0x70, 0x03, 0x02, 0xDA,
++0x1F, 0x90, 0x96, 0x16, 0xE0, 0x60, 0x12, 0x75,
++0x6E, 0x0A, 0x12, 0xE3, 0xF3, 0xE4, 0x93, 0xC3,
++0x13, 0x74, 0x01, 0x93, 0x13, 0xF5, 0x6F, 0x80,
++0x0A, 0x7B, 0xFF, 0x12, 0xE4, 0x52, 0xE4, 0xF5,
++0x6E, 0xF5, 0x6F, 0x75, 0xF0, 0x12, 0xE5, 0x62,
++0x12, 0xBF, 0x7F, 0xFF, 0xE5, 0x64, 0xD3, 0x9F,
++0x40, 0x08, 0x8F, 0x64, 0xE5, 0x64, 0x45, 0x65,
++0xF5, 0x63, 0x12, 0xDA, 0x4A, 0xE0, 0xC3, 0x94,
++0x05, 0x40, 0x03, 0x02, 0xD8, 0x10, 0xE5, 0x64,
++0x90, 0x81, 0x61, 0x93, 0xF5, 0x6A, 0xFD, 0xAF,
++0x64, 0x12, 0x60, 0x6F, 0x8F, 0x6A, 0xE5, 0x65,
++0x60, 0x04, 0x05, 0x6A, 0x05, 0x6A, 0xE5, 0x64,
++0xC3, 0x94, 0x0C, 0x40, 0x1D, 0x74, 0x18, 0x25,
++0x62, 0x12, 0x87, 0x95, 0xE0, 0xFF, 0x54, 0x7F,
++0xFE, 0xEF, 0x30, 0xE7, 0x06, 0xE5, 0x6A, 0x2E,
++0xFF, 0x80, 0x05, 0xC3, 0xE5, 0x6A, 0x9E, 0xFF,
++0x8F, 0x6A, 0xE5, 0x6A, 0xD3, 0x94, 0x1A, 0xAF,
++0x6A, 0x40, 0x02, 0x7F, 0x1A, 0x8F, 0x6A, 0xE5,
++0x63, 0x90, 0x81, 0xD9, 0x93, 0xFF, 0xD3, 0x90,
++0x95, 0x47, 0xE0, 0x9F, 0x90, 0x95, 0x46, 0xE0,
++0x94, 0x00, 0x40, 0x02, 0xE1, 0xC2, 0xC3, 0xE5,
++0x69, 0x94, 0x0A, 0xE5, 0x68, 0x94, 0x00, 0x40,
++0x02, 0xE1, 0x6F, 0x12, 0xE3, 0xBF, 0xE0, 0xC3,
++0x94, 0x01, 0x40, 0x06, 0x12, 0xE3, 0xBF, 0xE0,
++0x14, 0xF0, 0x12, 0xDA, 0x56, 0x12, 0xE4, 0x4C,
++0xFF, 0x90, 0x95, 0x47, 0xE0, 0x2F, 0xFF, 0x90,
++0x95, 0x46, 0xE0, 0x12, 0xE4, 0x18, 0x2F, 0xFD,
++0xEE, 0x35, 0xF0, 0xFC, 0xE5, 0x68, 0xC3, 0x13,
++0xFE, 0xE5, 0x69, 0x13, 0xFF, 0xD3, 0xED, 0x9F,
++0xEC, 0x9E, 0x40, 0x0E, 0xE5, 0x62, 0x94, 0x05,
++0x50, 0x06, 0x12, 0xE3, 0xBF, 0x74, 0x02, 0xF0,
++0xE1, 0xC2, 0x12, 0xDA, 0x56, 0x12, 0x03, 0x13,
++0x65, 0x69, 0x70, 0x04, 0xE5, 0xF0, 0x65, 0x68,
++0x70, 0x27, 0xE5, 0x62, 0xC3, 0x94, 0x05, 0x50,
++0x13, 0x12, 0xE3, 0xBF, 0xE0, 0xD3, 0x94, 0x00,
++0x40, 0x0A, 0x7D, 0x06, 0xAF, 0x62, 0x12, 0xBB,
++0x42, 0x02, 0xDA, 0x1F, 0xE4, 0xFD, 0xAF, 0x62,
++0x12, 0xBE, 0xBC, 0x12, 0xBB, 0x3E, 0x02, 0xDA,
++0x04, 0x12, 0xDA, 0x81, 0x02, 0xDA, 0x04, 0x12,
++0xE3, 0xBF, 0xE4, 0xF0, 0x90, 0x91, 0x6C, 0x74,
++0x02, 0xF0, 0xAB, 0x6A, 0xAD, 0x62, 0xAF, 0x69,
++0xAE, 0x68, 0x12, 0x41, 0x9C, 0x8E, 0x66, 0x8F,
++0x67, 0x12, 0xE3, 0xF3, 0xC3, 0x74, 0x01, 0x93,
++0x95, 0x6F, 0xFF, 0xE4, 0x93, 0x94, 0x00, 0xFE,
++0xD3, 0xE5, 0x67, 0x9F, 0xE5, 0x66, 0x9E, 0x40,
++0x0F, 0x12, 0xE3, 0xCB, 0xE4, 0xF0, 0x7D, 0x01,
++0xAF, 0x62, 0x12, 0xBE, 0xBC, 0x02, 0xDA, 0x04,
++0x12, 0xE4, 0xD7, 0xC3, 0xE5, 0x67, 0x9F, 0xE5,
++0x66, 0x94, 0x00, 0x50, 0x0E, 0x12, 0xE3, 0xCB,
++0xE4, 0xF0, 0x7D, 0x01, 0xAF, 0x62, 0x51, 0x69,
++0x02, 0xDA, 0x04, 0x12, 0xBB, 0x3E, 0x12, 0xE3,
++0xCB, 0xE0, 0x04, 0xF0, 0xE5, 0x64, 0x90, 0x81,
++0xED, 0x93, 0x25, 0x6E, 0xFF, 0xE4, 0x33, 0xFE,
++0x12, 0xE3, 0xCB, 0xE0, 0xC3, 0x9F, 0xEE, 0x12,
++0xC7, 0x48, 0x50, 0x03, 0x02, 0xDA, 0x04, 0x12,
++0xE3, 0xCB, 0xE4, 0xF0, 0x12, 0xE4, 0xD7, 0x12,
++0xE3, 0xF3, 0x74, 0x01, 0x93, 0x2F, 0xFF, 0xE4,
++0x93, 0x34, 0x00, 0xC3, 0x13, 0xFE, 0xEF, 0x13,
++0xFF, 0xE5, 0x62, 0x12, 0xBF, 0xC3, 0x41, 0x04,
++0x51, 0x4A, 0xE0, 0x64, 0x05, 0x60, 0x02, 0x01,
++0xDF, 0x90, 0x04, 0xA0, 0xE0, 0x64, 0x02, 0x70,
++0x10, 0x51, 0x31, 0xE4, 0xF0, 0x90, 0x04, 0xA1,
++0xE0, 0x78, 0x88, 0xF6, 0x12, 0xD1, 0xDE, 0x41,
++0x18, 0xAD, 0x64, 0xAF, 0x62, 0x12, 0x72, 0xEE,
++0x51, 0x77, 0xF5, 0x83, 0xEF, 0xF0, 0xE5, 0x62,
++0x12, 0xA7, 0xDB, 0xE0, 0x54, 0x07, 0x78, 0x88,
++0xF6, 0x12, 0x87, 0xC5, 0xFF, 0xC3, 0x94, 0x30,
++0x40, 0x1E, 0x75, 0xF0, 0x12, 0xE5, 0x62, 0x12,
++0x87, 0xBD, 0xFE, 0xC4, 0x13, 0x13, 0x54, 0x03,
++0x20, 0xE0, 0x0D, 0x51, 0x77, 0xF5, 0x83, 0xE0,
++0x60, 0x06, 0x90, 0x96, 0x16, 0xE0, 0x60, 0x0A,
++0xE4, 0x78, 0x88, 0xF6, 0x51, 0x31, 0xE4, 0xF0,
++0x80, 0x5C, 0x51, 0x6D, 0xF5, 0x83, 0xE0, 0xFE,
++0x24, 0x05, 0xFD, 0xE4, 0x33, 0xFC, 0xEF, 0x12,
++0xC7, 0x45, 0x50, 0x1F, 0x12, 0x87, 0xC5, 0x24,
++0x05, 0xFD, 0xE4, 0x33, 0xFC, 0xEE, 0x12, 0xC7,
++0x45, 0x50, 0x10, 0x51, 0x63, 0xF5, 0x83, 0xE0,
++0xB5, 0x64, 0x08, 0x51, 0x3E, 0xE0, 0xC3, 0x94,
++0x0A, 0x40, 0x26, 0x78, 0x88, 0xE6, 0xFF, 0x70,
++0x04, 0x76, 0x01, 0x80, 0x0C, 0xEF, 0x78, 0x88,
++0xB4, 0x01, 0x04, 0x76, 0x03, 0x80, 0x02, 0x76,
++0x05, 0x51, 0x3E, 0xE4, 0xF0, 0x12, 0x87, 0xC5,
++0xFF, 0x51, 0x6D, 0xF5, 0x83, 0xEF, 0xF0, 0x80,
++0x05, 0x51, 0x31, 0xE0, 0x04, 0xF0, 0x51, 0x63,
++0xF5, 0x83, 0xE5, 0x64, 0xF0, 0x21, 0xFF, 0x51,
++0x4A, 0xE0, 0x64, 0x06, 0x60, 0x02, 0x41, 0x04,
++0xF5, 0x66, 0xF5, 0x67, 0xE5, 0x62, 0x12, 0xA7,
++0xDB, 0xE0, 0x54, 0x07, 0x78, 0x88, 0xF6, 0xD3,
++0xE5, 0x69, 0x94, 0xE8, 0xE5, 0x68, 0x94, 0x03,
++0x40, 0x06, 0x78, 0x86, 0x76, 0x05, 0x80, 0x15,
++0xD3, 0xE5, 0x69, 0x94, 0xFA, 0xE5, 0x68, 0x94,
++0x00, 0x40, 0x06, 0x78, 0x86, 0x76, 0x02, 0x80,
++0x04, 0xE4, 0x78, 0x86, 0xF6, 0xE5, 0x69, 0xAE,
++0x68, 0x78, 0x86, 0x86, 0x00, 0x08, 0x80, 0x05,
++0xCE, 0xC3, 0x13, 0xCE, 0x13, 0xD8, 0xF9, 0xFF,
++0x90, 0x82, 0x06, 0xE4, 0x51, 0x5C, 0x90, 0x95,
++0x4F, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0xE4, 0x78,
++0x87, 0xF6, 0x51, 0x56, 0x78, 0x87, 0xE6, 0xFD,
++0x51, 0x88, 0xAE, 0xF0, 0x78, 0x86, 0x86, 0x00,
++0x08, 0x80, 0x05, 0xCE, 0xC3, 0x13, 0xCE, 0x13,
++0xD8, 0xF9, 0xFF, 0xED, 0x90, 0x82, 0x01, 0x51,
++0x5C, 0xEF, 0x25, 0x67, 0xF5, 0x67, 0xEE, 0x35,
++0x66, 0xF5, 0x66, 0xC3, 0x90, 0x95, 0x50, 0xE0,
++0x95, 0x67, 0x90, 0x95, 0x4F, 0xE0, 0x95, 0x66,
++0x40, 0x07, 0x78, 0x87, 0x06, 0xE6, 0xB4, 0x05,
++0xC1, 0x78, 0x87, 0xE6, 0xC3, 0x13, 0xF6, 0xFD,
++0x08, 0xE6, 0x24, 0x01, 0xFF, 0xE4, 0x33, 0xA2,
++0xE7, 0x13, 0xEF, 0x13, 0x08, 0xF6, 0xD3, 0x9D,
++0x40, 0x07, 0xE6, 0x79, 0x87, 0x97, 0xF6, 0x80,
++0x04, 0xE4, 0x78, 0x89, 0xF6, 0x51, 0x25, 0xE0,
++0xC3, 0x13, 0xFF, 0x78, 0x89, 0xE6, 0xC4, 0x33,
++0x54, 0xE0, 0x2F, 0xFF, 0x51, 0x25, 0xEF, 0xF0,
++0x51, 0x25, 0xE0, 0xC3, 0x94, 0xC0, 0x40, 0x05,
++0x51, 0x25, 0x74, 0xC0, 0xF0, 0x51, 0x25, 0xE0,
++0x24, 0x1F, 0xFF, 0xE4, 0x33, 0xFE, 0xEF, 0x78,
++0x06, 0xCE, 0xA2, 0xE7, 0x13, 0xCE, 0x13, 0xD8,
++0xF8, 0x78, 0x89, 0xF6, 0xE6, 0x25, 0xE0, 0xF6,
++0x70, 0x03, 0xFF, 0x80, 0x05, 0x78, 0x89, 0xE6,
++0x14, 0xFF, 0x78, 0x88, 0xA6, 0x07, 0xD3, 0x90,
++0x95, 0x47, 0xE0, 0x94, 0x03, 0x90, 0x95, 0x46,
++0xE0, 0x94, 0x00, 0x40, 0x02, 0xE4, 0xF6, 0x78,
++0x88, 0x12, 0xD1, 0xDE, 0x51, 0x4A, 0xE0, 0xFF,
++0xD3, 0x94, 0x05, 0x50, 0x05, 0xEF, 0x04, 0xFF,
++0x80, 0x02, 0x7F, 0x00, 0x51, 0x4A, 0xEF, 0xF0,
++0xE4, 0xF5, 0x66, 0xF5, 0x67, 0x51, 0x81, 0x05,
++0x62, 0x02, 0xD3, 0x75, 0x22, 0x74, 0x4F, 0x25,
++0x62, 0xF5, 0x82, 0xE4, 0x34, 0x8D, 0xF5, 0x83,
++0x22, 0x74, 0x76, 0x25, 0x62, 0xF5, 0x82, 0xE4,
++0x34, 0x8E, 0xF5, 0x83, 0xE4, 0xF0, 0x74, 0xF6,
++0x25, 0x62, 0xF5, 0x82, 0xE4, 0x34, 0x8D, 0xF5,
++0x83, 0x22, 0x74, 0x76, 0x25, 0x62, 0xF5, 0x82,
++0xE4, 0x34, 0x8E, 0xF5, 0x83, 0x22, 0x90, 0x95,
++0x43, 0x02, 0x86, 0x6D, 0x93, 0xFD, 0x7C, 0x00,
++0x02, 0x02, 0x80, 0x74, 0xA6, 0x25, 0x62, 0xF5,
++0x82, 0xE4, 0x34, 0x8E, 0x22, 0x74, 0x5F, 0x25,
++0x62, 0xF5, 0x82, 0xE4, 0x34, 0x8D, 0x22, 0x74,
++0xE6, 0x25, 0x62, 0xF5, 0x82, 0xE4, 0x34, 0x8D,
++0x22, 0x7D, 0x01, 0xAF, 0x62, 0x02, 0x61, 0xF7,
++0x75, 0xF0, 0x02, 0xA4, 0xF5, 0x82, 0x85, 0xF0,
++0x83, 0x02, 0x03, 0x3E, 0x90, 0x93, 0x58, 0xE0,
++0x54, 0x7F, 0xF0, 0x54, 0xBF, 0xF0, 0x54, 0xDF,
++0xF0, 0x54, 0xF0, 0xF0, 0xE4, 0x90, 0x93, 0x5A,
++0xF0, 0x90, 0x93, 0x58, 0xE0, 0x54, 0xEF, 0xF0,
++0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0,
++0xE4, 0x90, 0x95, 0xF5, 0xF0, 0x90, 0x95, 0xF3,
++0x74, 0x14, 0xF0, 0x90, 0x96, 0x15, 0x74, 0x01,
++0xF0, 0xFB, 0x7A, 0x95, 0x79, 0xF3, 0x12, 0x8A,
++0xF1, 0x7F, 0x04, 0x12, 0x04, 0x7E, 0xD0, 0xD0,
++0x92, 0xAF, 0x22, 0x90, 0x01, 0x94, 0xE0, 0x44,
++0x01, 0xF0, 0x90, 0x01, 0xC7, 0xE4, 0xF0, 0x22,
++0x22, 0xE4, 0x90, 0x95, 0xF5, 0xF0, 0xA3, 0xF0,
++0x7F, 0x83, 0x12, 0x7B, 0x41, 0x90, 0x95, 0xF4,
++0xEF, 0xF0, 0x7F, 0x83, 0x12, 0x7B, 0x41, 0xAE,
++0x07, 0x90, 0x95, 0xF4, 0xE0, 0xFF, 0xB5, 0x06,
++0x01, 0x22, 0xC3, 0x90, 0x95, 0xF6, 0xE0, 0x94,
++0x64, 0x90, 0x95, 0xF5, 0xE0, 0x94, 0x00, 0x40,
++0x0D, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x40, 0xF0,
++0x90, 0x95, 0xF4, 0xE0, 0xFF, 0x22, 0x90, 0x95,
++0xF5, 0x12, 0xAF, 0xAA, 0x80, 0xC2, 0xD3, 0x10,
++0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x12, 0xC7, 0x67,
++0x90, 0x97, 0x0C, 0xF0, 0xED, 0x90, 0x00, 0x73,
++0x70, 0x0D, 0xE0, 0x44, 0x04, 0xF0, 0x90, 0x00,
++0x67, 0xE0, 0x44, 0x80, 0xF0, 0x80, 0x0B, 0xE0,
++0x54, 0xFB, 0xF0, 0x90, 0x00, 0x67, 0xE0, 0x54,
++0x7F, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3,
++0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0xD0, 0xD0,
++0x92, 0xAF, 0x22, 0x90, 0x88, 0xB8, 0xE0, 0x54,
++0xFE, 0xF0, 0x54, 0xE1, 0xF0, 0x90, 0x88, 0xBD,
++0xE0, 0xFF, 0x12, 0x71, 0x9A, 0x90, 0x88, 0x36,
++0xE0, 0x70, 0x0C, 0x12, 0x90, 0xDF, 0x90, 0x8A,
++0xF9, 0x12, 0x8B, 0x03, 0x12, 0x8F, 0xF5, 0x22,
++0x90, 0x94, 0xBB, 0xE0, 0xFF, 0x54, 0x03, 0x70,
++0x11, 0xEF, 0x13, 0x13, 0x54, 0x3F, 0xFF, 0xA3,
++0xE0, 0xC3, 0x9F, 0x40, 0x5E, 0xE4, 0x90, 0x94,
++0xBC, 0xF0, 0x90, 0x88, 0x9D, 0xE0, 0x30, 0xE0,
++0x52, 0xA3, 0xE0, 0xFF, 0x90, 0x8A, 0xD1, 0x12,
++0x8E, 0xB2, 0x90, 0x88, 0xB0, 0x74, 0x01, 0xF0,
++0xE4, 0x90, 0x88, 0xA5, 0xF0, 0x90, 0x88, 0xB2,
++0xF0, 0xA3, 0xF0, 0x90, 0x88, 0xAF, 0x04, 0xF0,
++0x90, 0x88, 0x9C, 0xE0, 0x60, 0x0D, 0x90, 0x8A,
++0xF9, 0x12, 0x8B, 0x03, 0x7D, 0x05, 0x7F, 0x6F,
++0x02, 0x04, 0x7E, 0x90, 0x8A, 0xF9, 0x12, 0x8B,
++0x03, 0x12, 0x8F, 0xF5, 0x90, 0x88, 0x9D, 0x12,
++0xAF, 0xB1, 0x20, 0xE0, 0x0E, 0xEF, 0x13, 0x13,
++0x54, 0x3F, 0x30, 0xE0, 0x06, 0x90, 0x8A, 0xE1,
++0x12, 0x90, 0xE2, 0x22, 0x90, 0x94, 0xC6, 0x74,
++0x27, 0xF0, 0x90, 0x94, 0xE8, 0x74, 0x08, 0xF0,
++0x90, 0x94, 0xC8, 0xF0, 0xE4, 0x12, 0xA6, 0x44,
++0x90, 0x94, 0xB5, 0xE0, 0x90, 0x94, 0xCC, 0xF0,
++0x90, 0x94, 0xB6, 0xE0, 0x90, 0x94, 0xCD, 0xF0,
++0x90, 0x94, 0xB9, 0xE0, 0x90, 0x94, 0xCE, 0xF0,
++0x90, 0x94, 0xBA, 0xE0, 0x90, 0x94, 0xCF, 0xF0,
++0x7B, 0x01, 0x7A, 0x94, 0x79, 0xC6, 0x90, 0x8A,
++0x77, 0x91, 0x46, 0x02, 0x04, 0x7E, 0xE0, 0xFE,
++0xA3, 0xE0, 0xFF, 0xF5, 0x82, 0x8E, 0x83, 0x22,
++0x90, 0x97, 0x0D, 0xEF, 0xF0, 0x90, 0x88, 0xB8,
++0xE0, 0x44, 0x01, 0xF0, 0x90, 0x8A, 0xF9, 0x12,
++0x8B, 0x03, 0x7D, 0x11, 0x91, 0xA1, 0x12, 0x90,
++0xE2, 0x90, 0x07, 0x78, 0xE0, 0x90, 0x88, 0xBD,
++0xF0, 0x90, 0x97, 0x0D, 0xE0, 0xFD, 0x70, 0x02,
++0x80, 0x1C, 0xED, 0xB4, 0x01, 0x06, 0x91, 0x9A,
++0x44, 0x20, 0xF0, 0x22, 0x90, 0x97, 0x0D, 0xE0,
++0xFD, 0xB4, 0x02, 0x06, 0x91, 0x9A, 0x44, 0x60,
++0xF0, 0x22, 0xED, 0xB4, 0x03, 0x03, 0x91, 0x9A,
++0xF0, 0x22, 0x90, 0x88, 0xB8, 0xE0, 0x54, 0x1F,
++0x22, 0x7F, 0xFF, 0x12, 0x04, 0x7E, 0x90, 0x8A,
++0xEF, 0x22, 0x90, 0x88, 0x9D, 0xE0, 0x20, 0xE0,
++0x02, 0xA1, 0x76, 0x90, 0x8A, 0xB1, 0x12, 0x90,
++0xE2, 0x90, 0x88, 0xB0, 0xE0, 0xFF, 0xB4, 0x01,
++0x02, 0x80, 0x22, 0x90, 0x88, 0xB0, 0xE0, 0xFF,
++0xB4, 0x02, 0x05, 0x90, 0x8A, 0xC1, 0x80, 0x18,
++0x90, 0x88, 0xB0, 0xE0, 0xFF, 0xB4, 0x03, 0x05,
++0x90, 0x8A, 0xBB, 0x80, 0x0B, 0x90, 0x88, 0xB0,
++0xE0, 0xFF, 0xB4, 0x04, 0x08, 0x90, 0x8A, 0xBD,
++0xB1, 0x87, 0x02, 0x04, 0x7E, 0x90, 0x88, 0xB0,
++0xE0, 0xFF, 0x64, 0x05, 0x60, 0x02, 0xA1, 0x76,
++0x90, 0x94, 0xB7, 0xE0, 0x20, 0xE0, 0x6A, 0x90,
++0x88, 0x9D, 0xE0, 0xFE, 0xC4, 0x54, 0x0F, 0x20,
++0xE0, 0x0A, 0xEE, 0xC4, 0x13, 0x54, 0x07, 0x30,
++0xE0, 0x02, 0x80, 0x55, 0xB1, 0x77, 0x70, 0x0E,
++0x90, 0x01, 0x34, 0x74, 0x08, 0xF0, 0xFD, 0xE4,
++0xFF, 0x12, 0x7C, 0x74, 0x80, 0x16, 0x90, 0x94,
++0xB8, 0xE0, 0x60, 0x30, 0xB1, 0x77, 0xC3, 0x94,
++0x05, 0x50, 0x29, 0xE4, 0xA3, 0xF0, 0x90, 0x94,
++0xBA, 0xE0, 0x04, 0xF0, 0x90, 0x8A, 0xD1, 0x12,
++0x8B, 0x03, 0x7F, 0x05, 0x12, 0x04, 0x7E, 0x90,
++0x94, 0xB7, 0xE0, 0xFF, 0xC3, 0x13, 0xFE, 0xEF,
++0x54, 0x01, 0xFF, 0xEE, 0x04, 0x54, 0x7F, 0x25,
++0xE0, 0x4F, 0xF0, 0x22, 0xB1, 0x80, 0x90, 0x01,
++0x34, 0x74, 0x08, 0xF0, 0x90, 0x88, 0xB0, 0xE0,
++0xFF, 0x90, 0x8A, 0xC1, 0x12, 0x8E, 0xB2, 0x90,
++0x94, 0xB7, 0xE0, 0x54, 0x01, 0xF0, 0x22, 0x90,
++0x94, 0xB7, 0xE0, 0xC3, 0x13, 0x54, 0x7F, 0x22,
++0x7D, 0x08, 0xE4, 0xFF, 0x02, 0x7C, 0x7E, 0xE0,
++0xFC, 0xA3, 0xE0, 0xFD, 0xF5, 0x82, 0x8C, 0x83,
++0x22, 0x90, 0x96, 0xB4, 0x12, 0x86, 0x76, 0x90,
++0x96, 0xB0, 0x12, 0x86, 0x6D, 0x90, 0x96, 0xB7,
++0x12, 0x86, 0x76, 0x90, 0x96, 0xB3, 0xE0, 0x24,
++0xFF, 0xFF, 0xE4, 0x34, 0xFF, 0xFE, 0x90, 0x96,
++0xB5, 0x8F, 0xF0, 0x12, 0x02, 0xE7, 0x90, 0x96,
++0xB8, 0xEE, 0x8F, 0xF0, 0x12, 0x02, 0xE7, 0x90,
++0x96, 0xB3, 0xE0, 0xD3, 0x94, 0x00, 0x40, 0x2E,
++0x90, 0x96, 0xB7, 0x12, 0x86, 0x6D, 0x12, 0x02,
++0x06, 0xFF, 0x90, 0x96, 0xB4, 0x12, 0x86, 0x6D,
++0x12, 0x02, 0x06, 0xFE, 0x6F, 0x60, 0x05, 0xC3,
++0xEE, 0x9F, 0xFF, 0x22, 0x90, 0x96, 0xB5, 0xB1,
++0xF9, 0x90, 0x96, 0xB8, 0xB1, 0xF9, 0x90, 0x96,
++0xB3, 0xE0, 0x14, 0xF0, 0x80, 0xC9, 0x7F, 0x00,
++0x22, 0x74, 0xFF, 0xF5, 0xF0, 0x02, 0x02, 0xE7,
++0x90, 0x02, 0x84, 0xEF, 0xF0, 0xEE, 0xA3, 0xF0,
++0xA3, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0xE4, 0x90,
++0x97, 0x07, 0xF0, 0xA3, 0xF0, 0x90, 0x02, 0x86,
++0xE0, 0x20, 0xE1, 0x24, 0xC3, 0x90, 0x97, 0x08,
++0xE0, 0x94, 0xD0, 0x90, 0x97, 0x07, 0xE0, 0x94,
++0x07, 0x40, 0x0A, 0x90, 0x01, 0xC1, 0xE0, 0x44,
++0x04, 0xF0, 0x7F, 0x00, 0x22, 0x90, 0x97, 0x07,
++0x12, 0xAF, 0xAA, 0x12, 0xC6, 0x52, 0x80, 0xD5,
++0x7F, 0x01, 0x22, 0x7D, 0x07, 0xEF, 0x5D, 0xC3,
++0x60, 0x0A, 0xD1, 0x58, 0x24, 0x08, 0xFF, 0xE4,
++0x3E, 0xFE, 0x80, 0x03, 0xD1, 0x58, 0xFF, 0x22,
++0x74, 0xFF, 0x9D, 0xFD, 0x74, 0xFF, 0x94, 0x00,
++0x5E, 0xFE, 0xED, 0x5F, 0x22, 0x90, 0x01, 0x17,
++0xE0, 0xFE, 0x90, 0x01, 0x16, 0x12, 0x97, 0xCD,
++0x90, 0x88, 0x27, 0xF0, 0xA3, 0xEF, 0xF0, 0x90,
++0x02, 0x86, 0xE0, 0x44, 0x04, 0xF0, 0x90, 0x93,
++0x03, 0xE0, 0x44, 0x01, 0xF0, 0x7D, 0x08, 0xE4,
++0xFF, 0x12, 0x7C, 0x74, 0x90, 0x05, 0x52, 0xE0,
++0x54, 0x07, 0x04, 0x90, 0x93, 0x0F, 0x12, 0x9F,
++0xC9, 0x02, 0xC6, 0x59, 0x90, 0x04, 0x24, 0xEF,
++0xF0, 0x90, 0x04, 0x57, 0xF0, 0x22, 0x90, 0x93,
++0x0F, 0xE0, 0xFD, 0x7C, 0x00, 0xA3, 0xE0, 0xFE,
++0xA3, 0xE0, 0xFF, 0x12, 0x02, 0x92, 0xED, 0x4C,
++0x70, 0x05, 0x90, 0x93, 0x1C, 0x80, 0x2A, 0xED,
++0x64, 0x01, 0x4C, 0x70, 0x05, 0x90, 0x93, 0x1D,
++0x80, 0x1F, 0xED, 0x64, 0x02, 0x4C, 0x70, 0x05,
++0x90, 0x93, 0x1E, 0x80, 0x14, 0xED, 0x64, 0x03,
++0x4C, 0x70, 0x05, 0x90, 0x93, 0x1F, 0x80, 0x09,
++0xED, 0x64, 0x04, 0x4C, 0x70, 0x0D, 0x90, 0x93,
++0x20, 0xE0, 0xFF, 0xD1, 0x9C, 0x90, 0x93, 0x10,
++0x12, 0xAF, 0xAA, 0x22, 0xD3, 0x10, 0xAF, 0x01,
++0xC3, 0xC0, 0xD0, 0x90, 0x88, 0x9D, 0xE0, 0x30,
++0xE0, 0x10, 0x90, 0x88, 0xA3, 0xE0, 0xC4, 0x13,
++0x54, 0x07, 0x30, 0xE0, 0x20, 0x75, 0x10, 0x10,
++0x80, 0x44, 0x12, 0x7A, 0x65, 0xEF, 0x64, 0x01,
++0x60, 0x05, 0x75, 0x10, 0x01, 0x80, 0x37, 0x90,
++0x88, 0x31, 0x12, 0x97, 0x30, 0x30, 0xE0, 0x05,
++0x75, 0x10, 0x02, 0x80, 0x29, 0x90, 0x88, 0x38,
++0xE0, 0xD3, 0x94, 0x04, 0x40, 0x05, 0x75, 0x10,
++0x08, 0x80, 0x1B, 0x90, 0x93, 0x2A, 0xE0, 0x30,
++0xE0, 0x0B, 0xC4, 0x54, 0x0F, 0x30, 0xE0, 0x05,
++0x75, 0x10, 0x11, 0x80, 0x09, 0x90, 0x01, 0xB8,
++0xE4, 0xF0, 0x7F, 0x01, 0x80, 0x0E, 0x90, 0x01,
++0xB9, 0x74, 0x02, 0xF0, 0x90, 0x01, 0xB8, 0xE5,
++0x10, 0xF0, 0x7F, 0x00, 0xD0, 0xD0, 0x92, 0xAF,
++0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0,
++0x90, 0x88, 0x9D, 0xE0, 0x30, 0xE0, 0x1F, 0x90,
++0x88, 0xAF, 0xE0, 0x60, 0x06, 0x75, 0x11, 0x40,
++0x02, 0xE0, 0x18, 0x90, 0x88, 0x38, 0xE0, 0xD3,
++0x94, 0x00, 0x40, 0x02, 0x80, 0x2D, 0x90, 0x88,
++0x9C, 0xE0, 0x60, 0x7B, 0x80, 0x55, 0x12, 0x7A,
++0x65, 0xEF, 0x64, 0x01, 0x60, 0x05, 0x75, 0x11,
++0x01, 0x80, 0x75, 0x90, 0x88, 0x3A, 0xE0, 0xFF,
++0x54, 0x03, 0x60, 0x05, 0x75, 0x11, 0x02, 0x80,
++0x67, 0x90, 0x88, 0x38, 0xE0, 0xFE, 0xE4, 0xC3,
++0x9E, 0x50, 0x05, 0x75, 0x11, 0x04, 0x80, 0x58,
++0xEF, 0x30, 0xE2, 0x05, 0x75, 0x11, 0x08, 0x80,
++0x4F, 0x90, 0x88, 0x3A, 0xE0, 0x30, 0xE4, 0x05,
++0x75, 0x11, 0x10, 0x80, 0x43, 0x90, 0x88, 0x32,
++0xE0, 0x13, 0x13, 0x54, 0x3F, 0x20, 0xE0, 0x05,
++0x75, 0x11, 0x20, 0x80, 0x33, 0x90, 0x88, 0x9C,
++0xE0, 0x60, 0x05, 0x75, 0x11, 0x80, 0x80, 0x28,
++0x90, 0x06, 0x62, 0xE0, 0x30, 0xE1, 0x05, 0x75,
++0x11, 0x11, 0x80, 0x1C, 0x90, 0x06, 0x62, 0xE0,
++0x30, 0xE0, 0x0C, 0xE0, 0x54, 0xFC, 0xFF, 0xBF,
++0x80, 0x05, 0x75, 0x11, 0x12, 0x80, 0x09, 0x90,
++0x01, 0xB8, 0xE4, 0xF0, 0x7F, 0x01, 0x80, 0x0E,
++0x90, 0x01, 0xB9, 0x74, 0x04, 0xF0, 0x90, 0x01,
++0xB8, 0xE5, 0x11, 0xF0, 0x7F, 0x00, 0xD0, 0xD0,
++0x92, 0xAF, 0x22, 0x90, 0x02, 0x87, 0xE0, 0x60,
++0x02, 0x80, 0x08, 0x90, 0x01, 0x00, 0xE0, 0x64,
++0x3F, 0x60, 0x05, 0x75, 0x61, 0x01, 0x80, 0x34,
++0x90, 0x02, 0x96, 0xE0, 0x60, 0x05, 0x75, 0x61,
++0x10, 0x80, 0x29, 0x90, 0x02, 0x86, 0xE0, 0x20,
++0xE1, 0x02, 0x80, 0x07, 0x90, 0x02, 0x86, 0xE0,
++0x30, 0xE3, 0x05, 0x75, 0x61, 0x04, 0x80, 0x14,
++0x90, 0x88, 0xE6, 0xE0, 0x30, 0xE0, 0x05, 0x75,
++0x61, 0x20, 0x80, 0x08, 0x90, 0x01, 0xB8, 0xE4,
++0xF0, 0x7F, 0x01, 0x22, 0x90, 0x01, 0xB9, 0x74,
++0x08, 0xF0, 0x90, 0x01, 0xB8, 0xE5, 0x61, 0xF0,
++0x7F, 0x00, 0x22, 0x90, 0x88, 0x8D, 0x74, 0x18,
++0xF0, 0xA3, 0xF0, 0xA3, 0xE4, 0xF0, 0xA3, 0x74,
++0x64, 0xF0, 0xA3, 0x74, 0x05, 0xF0, 0xA3, 0xF0,
++0x22, 0x90, 0x88, 0x85, 0x12, 0x04, 0xB8, 0xC0,
++0x06, 0xC0, 0x07, 0x90, 0x94, 0xA1, 0xE0, 0x24,
++0x46, 0xFF, 0x90, 0x94, 0xA0, 0xE0, 0x34, 0x00,
++0xAB, 0x07, 0xFA, 0xE4, 0xF9, 0xF8, 0xD0, 0x07,
++0xD0, 0x06, 0x12, 0x86, 0x39, 0x90, 0x88, 0x85,
++0x51, 0xBC, 0xEF, 0x24, 0x46, 0xFF, 0xE4, 0x3E,
++0xFE, 0xE4, 0x3D, 0xFD, 0xE4, 0x3C, 0xFC, 0x90,
++0x88, 0x89, 0x51, 0xBC, 0x90, 0x88, 0x85, 0x12,
++0x86, 0x61, 0xC3, 0x12, 0x03, 0xDA, 0x50, 0x02,
++0x21, 0x9C, 0x90, 0x88, 0x89, 0x12, 0x86, 0x61,
++0x90, 0x88, 0x85, 0x12, 0x04, 0xB8, 0x12, 0x86,
++0x39, 0x90, 0x95, 0xD3, 0x12, 0x04, 0x31, 0x90,
++0x88, 0x31, 0xE0, 0x30, 0xE0, 0x34, 0x90, 0x88,
++0x53, 0xE0, 0x24, 0x04, 0xFF, 0xE4, 0x33, 0xFE,
++0xEF, 0x78, 0x03, 0xC3, 0x33, 0xCE, 0x33, 0xCE,
++0xD8, 0xF9, 0x24, 0x50, 0xFF, 0xE4, 0x3E, 0xFE,
++0x90, 0x88, 0x4E, 0xE0, 0xFD, 0xC3, 0xEF, 0x9D,
++0xFB, 0xEE, 0x94, 0x00, 0xFA, 0x51, 0xAB, 0x78,
++0x07, 0x12, 0x03, 0xEB, 0xEB, 0x2F, 0xFF, 0xEA,
++0x80, 0x23, 0x90, 0x88, 0x33, 0x12, 0x9F, 0xBB,
++0x30, 0xE0, 0x02, 0x41, 0x9B, 0x51, 0xAB, 0x78,
++0x07, 0x12, 0x03, 0xEB, 0x90, 0x88, 0x4E, 0xE0,
++0xFD, 0xC3, 0x74, 0x60, 0x9D, 0xCD, 0xE4, 0x94,
++0x00, 0xCD, 0x2F, 0xFF, 0xED, 0x3E, 0x90, 0x95,
++0xCF, 0xF0, 0xA3, 0xEF, 0xF0, 0xC3, 0x90, 0x95,
++0xD0, 0xE0, 0x94, 0xA0, 0x90, 0x95, 0xCF, 0xE0,
++0x94, 0x00, 0x50, 0x30, 0xA3, 0xE0, 0xFB, 0x24,
++0x60, 0x51, 0xB4, 0xE0, 0x04, 0xF0, 0x51, 0xAB,
++0xEF, 0x54, 0x7F, 0xFF, 0x74, 0x00, 0x2B, 0x51,
++0xA3, 0xE0, 0xFE, 0xEF, 0xC3, 0x9E, 0x50, 0x09,
++0x90, 0x95, 0xCF, 0xA3, 0xE0, 0x51, 0xA1, 0xEF,
++0xF0, 0x90, 0x88, 0x4C, 0xE0, 0x04, 0xF0, 0xE0,
++0x90, 0x00, 0xFE, 0xF0, 0x90, 0x88, 0x4C, 0xE0,
++0xFF, 0xD3, 0x90, 0x88, 0x90, 0xE0, 0x9F, 0x90,
++0x88, 0x8F, 0xE0, 0x94, 0x00, 0x40, 0x02, 0x41,
++0x9B, 0xE4, 0xFF, 0xFE, 0x51, 0xB1, 0xE0, 0x2F,
++0xFF, 0x90, 0x88, 0x91, 0xE0, 0xFD, 0xEF, 0xD3,
++0x9D, 0x40, 0x07, 0x90, 0x95, 0xD1, 0xEE, 0xF0,
++0x80, 0x05, 0x0E, 0xEE, 0xB4, 0xA0, 0xE5, 0x51,
++0xC5, 0x9C, 0x40, 0x02, 0x80, 0x16, 0x90, 0x95,
++0xD1, 0xE0, 0x04, 0xFE, 0xEE, 0xC3, 0x94, 0xA0,
++0x50, 0x14, 0x51, 0xB1, 0xE0, 0x2F, 0xFF, 0x51,
++0xC5, 0x9C, 0x40, 0x07, 0x90, 0x95, 0xD2, 0xEE,
++0xF0, 0x80, 0x03, 0x0E, 0x80, 0xE6, 0x90, 0x05,
++0x5E, 0xE0, 0xFF, 0x51, 0x9C, 0xE0, 0xFD, 0xEF,
++0xC3, 0x9D, 0x40, 0x11, 0xEF, 0x9D, 0x90, 0x05,
++0x5E, 0xF0, 0x90, 0x88, 0x51, 0xEE, 0xF0, 0x90,
++0x95, 0xD2, 0xE0, 0x80, 0x18, 0x51, 0x9C, 0xE0,
++0xFD, 0xC3, 0x74, 0x80, 0x9D, 0x2F, 0x90, 0x05,
++0x5E, 0xF0, 0xEE, 0x04, 0x90, 0x88, 0x51, 0xF0,
++0x90, 0x95, 0xD2, 0xE0, 0x04, 0x90, 0x88, 0x52,
++0xF0, 0x90, 0x88, 0x51, 0xE0, 0xFF, 0xC3, 0x94,
++0x50, 0x40, 0x0A, 0xEF, 0x24, 0xB0, 0x90, 0x88,
++0x49, 0xF0, 0xE4, 0x80, 0x0E, 0xE4, 0x90, 0x88,
++0x49, 0xF0, 0x90, 0x88, 0x51, 0xE0, 0xFF, 0xC3,
++0x74, 0x50, 0x9F, 0x90, 0x88, 0x48, 0xF0, 0x90,
++0x88, 0x51, 0xE0, 0xFF, 0xA3, 0xE0, 0xC3, 0x9F,
++0x90, 0x88, 0x4F, 0xF0, 0x90, 0x88, 0x31, 0xE0,
++0x90, 0x88, 0x8E, 0xE0, 0x24, 0x08, 0xFF, 0x90,
++0x88, 0x4F, 0xE0, 0x2F, 0xF0, 0x90, 0x88, 0x4F,
++0xE0, 0xC3, 0x94, 0x50, 0x50, 0x03, 0x74, 0x50,
++0xF0, 0x90, 0x88, 0x4F, 0xE0, 0x24, 0x10, 0x12,
++0xB7, 0xC7, 0x74, 0x03, 0xF0, 0x12, 0x6E, 0x2F,
++0x90, 0x8A, 0xA3, 0x12, 0x8B, 0x03, 0xE4, 0xFF,
++0x12, 0x04, 0x7E, 0x22, 0x90, 0x95, 0xD1, 0xE0,
++0xFE, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, 0x94,
++0xF5, 0x83, 0x22, 0x90, 0x95, 0xD3, 0x02, 0x04,
++0xB8, 0x74, 0x60, 0x2E, 0xF5, 0x82, 0xE4, 0x34,
++0x93, 0xF5, 0x83, 0x22, 0x12, 0x04, 0x31, 0x90,
++0x88, 0x89, 0x02, 0x04, 0xB8, 0x90, 0x88, 0x91,
++0xE0, 0xFD, 0xC3, 0x90, 0x88, 0x90, 0xE0, 0x9D,
++0xFD, 0x90, 0x88, 0x8F, 0xE0, 0x94, 0x00, 0xFC,
++0xEF, 0xD3, 0x9D, 0xE4, 0x22, 0xE4, 0xFE, 0x51,
++0xB1, 0xE4, 0xF0, 0x74, 0x00, 0x2E, 0x51, 0xA3,
++0x74, 0xFF, 0xF0, 0x0E, 0xEE, 0xB4, 0xA0, 0xEF,
++0xE4, 0x90, 0x88, 0x4D, 0xF0, 0x90, 0x88, 0x4C,
++0xF0, 0x90, 0x88, 0x50, 0xF0, 0xEF, 0xB4, 0x01,
++0x07, 0xA3, 0x74, 0xA0, 0xF0, 0xE4, 0xA3, 0xF0,
++0x22, 0x71, 0x50, 0x9F, 0x40, 0x41, 0x90, 0x88,
++0x50, 0xE0, 0x04, 0xF0, 0x90, 0x88, 0x92, 0xE0,
++0xFF, 0x90, 0x88, 0x50, 0xE0, 0xD3, 0x9F, 0x50,
++0x2E, 0x90, 0x88, 0x48, 0xE0, 0x24, 0x08, 0xF0,
++0x90, 0x88, 0x3F, 0x12, 0x97, 0x97, 0x33, 0x33,
++0x33, 0x54, 0xF8, 0xFF, 0x90, 0x88, 0x3E, 0xE0,
++0x2F, 0x90, 0x88, 0x4F, 0xF0, 0xFB, 0x90, 0x88,
++0x48, 0xE0, 0xFF, 0xA3, 0xE0, 0xFD, 0x90, 0x92,
++0x98, 0x74, 0x03, 0xF0, 0x12, 0x6E, 0x2F, 0x22,
++0x90, 0x88, 0x93, 0xE0, 0xFF, 0x90, 0x88, 0x3F,
++0xE0, 0xD3, 0x22, 0x90, 0x93, 0x2A, 0xE0, 0x30,
++0xE0, 0x34, 0xC4, 0x13, 0x54, 0x07, 0x30, 0xE0,
++0x2D, 0x90, 0x97, 0x12, 0xE0, 0x04, 0xF0, 0xE0,
++0xD3, 0x94, 0xC8, 0x40, 0x21, 0x90, 0x93, 0x2A,
++0xE0, 0x54, 0xDF, 0xF0, 0xE4, 0x90, 0x97, 0x12,
++0xF0, 0x90, 0x93, 0x2A, 0xE0, 0x13, 0x30, 0xE0,
++0x0D, 0x90, 0x88, 0x31, 0xE0, 0x44, 0x01, 0xF0,
++0x90, 0x88, 0x41, 0x74, 0xD0, 0xF0, 0x22, 0x90,
++0x05, 0x63, 0xE0, 0x90, 0x88, 0x89, 0xF0, 0x90,
++0x05, 0x62, 0xE0, 0x90, 0x88, 0x8A, 0xF0, 0x90,
++0x05, 0x61, 0xE0, 0x90, 0x88, 0x8B, 0xF0, 0x90,
++0x05, 0x60, 0xE0, 0x90, 0x88, 0x8C, 0xF0, 0x90,
++0x88, 0x32, 0xE0, 0x44, 0x80, 0xF0, 0x22, 0x74,
++0x39, 0x25, 0x62, 0xF5, 0x82, 0xE4, 0x34, 0x96,
++0xF5, 0x83, 0x22, 0x74, 0xA6, 0x25, 0x62, 0xF5,
++0x82, 0xE4, 0x34, 0x8D, 0xF5, 0x83, 0x22, 0xF5,
++0x83, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0xD3, 0x9F,
++0xEC, 0x22, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xC3,
++0x74, 0xFF, 0x9F, 0xFF, 0x74, 0xFF, 0x9E, 0xFE,
++0xE5, 0x62, 0x22, 0xE5, 0x64, 0x25, 0xE0, 0x24,
++0x75, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83,
++0x22, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xED, 0x2F,
++0xFF, 0xEC, 0x3E, 0xFE, 0x22, 0xE0, 0x24, 0x6F,
++0xF5, 0x82, 0xE4, 0x34, 0x8D, 0xF5, 0x83, 0x22,
++0x35, 0xF0, 0xFE, 0x90, 0x00, 0x06, 0x02, 0x03,
++0x3E, 0xE0, 0x54, 0xFE, 0x4E, 0xFE, 0xF0, 0xEF,
++0x54, 0x02, 0xFF, 0xEE, 0x54, 0xFD, 0x4F, 0x22,
++0x75, 0xF0, 0x03, 0xA4, 0x24, 0x97, 0xF5, 0x82,
++0xE4, 0x34, 0x95, 0xF5, 0x83, 0x22, 0x75, 0xF0,
++0x03, 0xA4, 0x24, 0x55, 0xF5, 0x82, 0xE4, 0x34,
++0x95, 0xF5, 0x83, 0x22, 0x90, 0x00, 0x08, 0x02,
++0x03, 0x3E, 0x7A, 0x81, 0x79, 0xB1, 0x90, 0x89,
++0x46, 0x02, 0x86, 0x76, 0xE5, 0x62, 0x25, 0xE0,
++0x24, 0x86, 0xF5, 0x82, 0xE4, 0x22, 0x90, 0x00,
++0x02, 0x02, 0x03, 0x3E, 0x90, 0x00, 0x04, 0x02,
++0x03, 0x3E, 0x74, 0xB6, 0x25, 0x62, 0xF5, 0x82,
++0xE4, 0x34, 0x8D, 0x22, 0xE4, 0x90, 0x92, 0x20,
++0xF0, 0x90, 0x93, 0x2C, 0x22, 0x90, 0x96, 0xE1,
++0xE0, 0xFF, 0x90, 0x8A, 0xC7, 0x22, 0x90, 0x95,
++0x43, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x22, 0xF5,
++0x82, 0xE4, 0x34, 0x95, 0xF5, 0x83, 0xE0, 0x22,
++0x25, 0xE0, 0x24, 0x06, 0xF5, 0x82, 0xE4, 0x22,
++0x25, 0xE0, 0x24, 0x26, 0xF5, 0x82, 0xE4, 0x22,
++0x25, 0xE0, 0x24, 0x56, 0xF5, 0x82, 0xE4, 0x22,
++0xEF, 0xF0, 0xE4, 0x90, 0x95, 0x4D, 0xF0, 0x22,
++0x12, 0x86, 0x61, 0xD3, 0x02, 0x03, 0xDA, 0x90,
++0x88, 0xA3, 0xE0, 0x54, 0xDF, 0xF0, 0x22, 0x25,
++0xE0, 0x25, 0xE0, 0xFE, 0xEF, 0x4E, 0x22, 0xE5,
++0x64, 0x90, 0x81, 0x9D, 0x93, 0xFF, 0x22, 0x90,
++0x95, 0x4A, 0xE0, 0xFE, 0xA3, 0xE0, 0x22, 0xE0,
++0xFF, 0x90, 0x96, 0xBA, 0xE0, 0xFE, 0x22, 0x12,
++0x86, 0x6D, 0x90, 0x96, 0xBE, 0xE0, 0x22, 0x00,
++0xD2, 0xF8
++};
++
++u32 array_length_mp_8723d_fw_ap = 25882;
++
++#endif /*defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))*/
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE))
++
++u8 array_mp_8723d_fw_nic[] = {
++0xD1, 0x23, 0x10, 0x00, 0x31, 0x00, 0x00, 0x00,
++0x11, 0x18, 0x20, 0x41, 0x2E, 0x72, 0x02, 0x00,
++0x72, 0xB6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x02, 0x86, 0x71, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0xE1, 0x96, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0xE6, 0x43, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0xE1, 0x3E, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0xD4, 0xE6, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0xE5, 0xED, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x15, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x15,
++0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x05, 0xF0,
++0xFF, 0x0F, 0x00, 0x00, 0x00, 0x05, 0xF0, 0x0F,
++0x00, 0x00, 0x00, 0x00, 0x10, 0xF0, 0xFF, 0x0F,
++0x00, 0x00, 0x00, 0x10, 0xF0, 0x0F, 0x00, 0x00,
++0x00, 0x00, 0xF5, 0x0F, 0x00, 0x00, 0x00, 0x00,
++0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A,
++0x08, 0x03, 0x03, 0x00, 0x04, 0x09, 0x07, 0x03,
++0x03, 0x00, 0x04, 0x08, 0x06, 0x03, 0x02, 0x00,
++0x04, 0x08, 0x05, 0x03, 0x01, 0x00, 0x04, 0x0D,
++0x0A, 0x07, 0x05, 0x00, 0x08, 0x0C, 0x0A, 0x07,
++0x04, 0x00, 0x08, 0x0B, 0x0A, 0x06, 0x05, 0x00,
++0x08, 0x0B, 0x0A, 0x05, 0x03, 0x00, 0x08, 0x0B,
++0x0A, 0x03, 0x02, 0x00, 0x08, 0x14, 0x12, 0x0C,
++0x04, 0x00, 0x10, 0x14, 0x12, 0x09, 0x04, 0x00,
++0x10, 0x24, 0x22, 0x1C, 0x12, 0x00, 0x20, 0x24,
++0x22, 0x18, 0x0C, 0x00, 0x20, 0x24, 0x22, 0x14,
++0x06, 0x00, 0x20, 0x24, 0x22, 0x0F, 0x04, 0x00,
++0x20, 0x24, 0x21, 0x0A, 0x04, 0x00, 0x20, 0x23,
++0x21, 0x0C, 0x04, 0x00, 0x20, 0x23, 0x1F, 0x0A,
++0x04, 0x00, 0x20, 0x22, 0x1F, 0x0F, 0x04, 0x00,
++0x20, 0x21, 0x1F, 0x16, 0x0C, 0x00, 0x20, 0x31,
++0x2F, 0x20, 0x14, 0x00, 0x30, 0x31, 0x2F, 0x18,
++0x10, 0x00, 0x30, 0x31, 0x2C, 0x18, 0x0C, 0x00,
++0x30, 0x31, 0x2A, 0x14, 0x0C, 0x00, 0x30, 0x31,
++0x28, 0x14, 0x00, 0x00, 0x30, 0x31, 0x24, 0x14,
++0x00, 0x00, 0x30, 0x31, 0x1E, 0x14, 0x00, 0x00,
++0x30, 0x02, 0x02, 0x03, 0x04, 0x04, 0x08, 0x09,
++0x09, 0x0C, 0x0E, 0x10, 0x12, 0x02, 0x09, 0x0B,
++0x0E, 0x0D, 0x0F, 0x10, 0x12, 0x00, 0x04, 0x00,
++0x04, 0x00, 0x08, 0x00, 0x10, 0x00, 0x23, 0x00,
++0x2D, 0x00, 0x50, 0x00, 0x91, 0x00, 0xC3, 0x01,
++0x27, 0x01, 0x31, 0x01, 0x5E, 0x00, 0x8C, 0x00,
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++0x9A, 0x01, 0xCC, 0x01, 0xEA, 0x02, 0x02, 0x04,
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++0x6C, 0x14, 0x28, 0x32, 0x50, 0x78, 0xA0, 0xC8,
++0xE6, 0x01, 0x01, 0x01, 0x02, 0x01, 0x01, 0x02,
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++0x07, 0x07, 0x08, 0x08, 0x08, 0x01, 0x01, 0x01,
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++0x04, 0x05, 0x06, 0x07, 0x08, 0x03, 0x03, 0x03,
++0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x02, 0x02,
++0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
++0x02, 0x19, 0x06, 0x04, 0x02, 0x00, 0x18, 0x00,
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++0xC2, 0xAF, 0x80, 0xFE, 0x32, 0x12, 0x83, 0x04,
++0x85, 0xD0, 0x0B, 0x75, 0xD0, 0x08, 0xAA, 0xE0,
++0xC2, 0x8C, 0xE5, 0x8A, 0x24, 0x67, 0xF5, 0x8A,
++0xE5, 0x8C, 0x34, 0x79, 0xF5, 0x8C, 0xD2, 0x8C,
++0xEC, 0x24, 0x8B, 0xF8, 0xE6, 0xBC, 0x02, 0x02,
++0x74, 0xFF, 0xC3, 0x95, 0x81, 0xB4, 0x40, 0x00,
++0x40, 0xCE, 0x79, 0x03, 0x78, 0x80, 0x16, 0xE6,
++0x08, 0x70, 0x0B, 0xC2, 0xAF, 0xE6, 0x30, 0xE1,
++0x03, 0x44, 0x18, 0xF6, 0xD2, 0xAF, 0x08, 0xD9,
++0xED, 0xEA, 0x8B, 0xD0, 0x22, 0xE5, 0x0C, 0xFF,
++0x23, 0x24, 0x81, 0xF8, 0x0F, 0x08, 0x08, 0xBF,
++0x03, 0x04, 0x7F, 0x00, 0x78, 0x81, 0xE6, 0x30,
++0xE4, 0xF2, 0x00, 0xE5, 0x0C, 0xC3, 0x9F, 0x50,
++0x20, 0x05, 0x0C, 0x74, 0x8A, 0x25, 0x0C, 0xF8,
++0xE6, 0xFD, 0xA6, 0x81, 0x08, 0xE6, 0xAE, 0x0C,
++0xBE, 0x02, 0x02, 0x74, 0xFF, 0xCD, 0xF8, 0xE8,
++0x6D, 0x60, 0xE0, 0x08, 0xE6, 0xC0, 0xE0, 0x80,
++0xF6, 0xE5, 0x0C, 0xD3, 0x9F, 0x40, 0x27, 0xE5,
++0x0C, 0x24, 0x8B, 0xF8, 0xE6, 0xAE, 0x0C, 0xBE,
++0x02, 0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xCD,
++0xF8, 0xE5, 0x81, 0x6D, 0x60, 0x06, 0xD0, 0xE0,
++0xF6, 0x18, 0x80, 0xF5, 0xE5, 0x0C, 0x24, 0x8A,
++0xC8, 0xF6, 0x15, 0x0C, 0x80, 0xD3, 0xE5, 0x0C,
++0x23, 0x24, 0x81, 0xF8, 0x7F, 0x04, 0xC2, 0xAF,
++0xE6, 0x30, 0xE0, 0x03, 0x10, 0xE2, 0x0C, 0x7F,
++0x00, 0x30, 0xE1, 0x07, 0x30, 0xE3, 0x04, 0x7F,
++0x08, 0x54, 0xF4, 0x54, 0x7C, 0xC6, 0xD2, 0xAF,
++0x54, 0x80, 0x42, 0x07, 0x22, 0x78, 0x8A, 0xA6,
++0x81, 0x74, 0x02, 0x60, 0x06, 0xFF, 0x08, 0x76,
++0xFF, 0xDF, 0xFB, 0x7F, 0x03, 0xE4, 0x78, 0x80,
++0xF6, 0x08, 0xF6, 0x08, 0xDF, 0xFA, 0x78, 0x81,
++0x76, 0x30, 0x90, 0x86, 0xFD, 0x74, 0x01, 0x93,
++0xC0, 0xE0, 0xE4, 0x93, 0xC0, 0xE0, 0x43, 0x89,
++0x01, 0x75, 0x8A, 0x60, 0x75, 0x8C, 0x79, 0xD2,
++0x8C, 0xD2, 0xAF, 0x22, 0x02, 0xEF, 0xD3, 0x94,
++0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0x74, 0x81,
++0x2F, 0x2F, 0xF8, 0xE6, 0x20, 0xE5, 0xF4, 0xC2,
++0xAF, 0xE6, 0x44, 0x30, 0xF6, 0xD2, 0xAF, 0xAE,
++0x0C, 0xEE, 0xC3, 0x9F, 0x50, 0x21, 0x0E, 0x74,
++0x8A, 0x2E, 0xF8, 0xE6, 0xF9, 0x08, 0xE6, 0x18,
++0xBE, 0x02, 0x02, 0x74, 0xFF, 0xFD, 0xED, 0x69,
++0x60, 0x09, 0x09, 0xE7, 0x19, 0x19, 0xF7, 0x09,
++0x09, 0x80, 0xF3, 0x16, 0x16, 0x80, 0xDA, 0xEE,
++0xD3, 0x9F, 0x40, 0x04, 0x05, 0x81, 0x05, 0x81,
++0xEE, 0xD3, 0x9F, 0x40, 0x22, 0x74, 0x8A, 0x2E,
++0xF8, 0x08, 0xE6, 0xF9, 0xEE, 0xB5, 0x0C, 0x02,
++0xA9, 0x81, 0x18, 0x06, 0x06, 0xE6, 0xFD, 0xED,
++0x69, 0x60, 0x09, 0x19, 0x19, 0xE7, 0x09, 0x09,
++0xF7, 0x19, 0x80, 0xF3, 0x1E, 0x80, 0xD9, 0xEF,
++0x24, 0x8A, 0xF8, 0xE6, 0x04, 0xF8, 0xEF, 0x2F,
++0x04, 0x90, 0x86, 0xFD, 0x93, 0xF6, 0x08, 0xEF,
++0x2F, 0x93, 0xF6, 0x7F, 0x00, 0x22, 0xEF, 0xD3,
++0x94, 0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0xEF,
++0x23, 0x24, 0x81, 0xF8, 0xE6, 0x30, 0xE5, 0xF4,
++0xC2, 0xAF, 0xE6, 0x54, 0x8C, 0xF6, 0xD2, 0xAF,
++0xE5, 0x0C, 0xB5, 0x07, 0x0A, 0x74, 0x8A, 0x2F,
++0xF8, 0xE6, 0xF5, 0x81, 0x02, 0x83, 0x4D, 0x50,
++0x2E, 0x74, 0x8B, 0x2F, 0xF8, 0xE6, 0xBF, 0x02,
++0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xF9, 0x74,
++0x8A, 0x2F, 0xF8, 0xFB, 0xE6, 0xFC, 0xE9, 0x6C,
++0x60, 0x08, 0xA8, 0x05, 0xE7, 0xF6, 0x1D, 0x19,
++0x80, 0xF4, 0xA8, 0x03, 0xA6, 0x05, 0x1F, 0xE5,
++0x0C, 0xB5, 0x07, 0xE3, 0x7F, 0x00, 0x22, 0x74,
++0x8B, 0x2F, 0xF8, 0xE6, 0xFD, 0x18, 0x86, 0x01,
++0x0F, 0x74, 0x8A, 0x2F, 0xF8, 0xA6, 0x01, 0x08,
++0x86, 0x04, 0xE5, 0x0C, 0xB5, 0x07, 0x02, 0xAC,
++0x81, 0xED, 0x6C, 0x60, 0x08, 0x0D, 0x09, 0xA8,
++0x05, 0xE6, 0xF7, 0x80, 0xF4, 0xE5, 0x0C, 0xB5,
++0x07, 0xDE, 0x89, 0x81, 0x7F, 0x00, 0x22, 0xEF,
++0xD3, 0x94, 0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22,
++0xEF, 0x23, 0x24, 0x81, 0xF8, 0xC2, 0xAF, 0xE6,
++0x30, 0xE5, 0x05, 0x30, 0xE0, 0x02, 0xD2, 0xE4,
++0xD2, 0xE2, 0xC6, 0xD2, 0xAF, 0x7F, 0x00, 0x30,
++0xE2, 0x01, 0x0F, 0x02, 0x83, 0x4C, 0x8F, 0xF0,
++0xE4, 0xFF, 0xFE, 0xE5, 0x0C, 0x23, 0x24, 0x80,
++0xF8, 0xC2, 0xA9, 0x30, 0xF7, 0x0D, 0x7F, 0x08,
++0xE6, 0x60, 0x0B, 0x2D, 0xF6, 0x60, 0x30, 0x50,
++0x2E, 0x80, 0x07, 0x30, 0xF1, 0x06, 0xED, 0xF6,
++0x60, 0x25, 0x7E, 0x02, 0x08, 0x30, 0xF0, 0x10,
++0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x23, 0x0E, 0x30,
++0xE2, 0x0C, 0xD2, 0xAF, 0x7F, 0x04, 0x80, 0x12,
++0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x13, 0x54, 0xEC,
++0x4E, 0xF6, 0xD2, 0xAF, 0x02, 0x83, 0x4D, 0x7F,
++0x08, 0x08, 0xEF, 0x44, 0x83, 0xF4, 0xC2, 0xAF,
++0x56, 0xC6, 0xD2, 0xAF, 0x54, 0x80, 0x4F, 0xFF,
++0x22, 0xEF, 0x2B, 0xFF, 0xEE, 0x3A, 0xFE, 0xED,
++0x39, 0xFD, 0xEC, 0x38, 0xFC, 0x22, 0xC3, 0xEF,
++0x9B, 0xFF, 0xEE, 0x9A, 0xFE, 0xED, 0x99, 0xFD,
++0xEC, 0x98, 0xFC, 0x22, 0xE8, 0x8F, 0xF0, 0xA4,
++0xCC, 0x8B, 0xF0, 0xA4, 0x2C, 0xFC, 0xE9, 0x8E,
++0xF0, 0xA4, 0x2C, 0xFC, 0x8A, 0xF0, 0xED, 0xA4,
++0x2C, 0xFC, 0xEA, 0x8E, 0xF0, 0xA4, 0xCD, 0xA8,
++0xF0, 0x8B, 0xF0, 0xA4, 0x2D, 0xCC, 0x38, 0x25,
++0xF0, 0xFD, 0xE9, 0x8F, 0xF0, 0xA4, 0x2C, 0xCD,
++0x35, 0xF0, 0xFC, 0xEB, 0x8E, 0xF0, 0xA4, 0xFE,
++0xA9, 0xF0, 0xEB, 0x8F, 0xF0, 0xA4, 0xCF, 0xC5,
++0xF0, 0x2E, 0xCD, 0x39, 0xFE, 0xE4, 0x3C, 0xFC,
++0xEA, 0xA4, 0x2D, 0xCE, 0x35, 0xF0, 0xFD, 0xE4,
++0x3C, 0xFC, 0x22, 0xEF, 0x5B, 0xFF, 0xEE, 0x5A,
++0xFE, 0xED, 0x59, 0xFD, 0xEC, 0x58, 0xFC, 0x22,
++0xEF, 0x4B, 0xFF, 0xEE, 0x4A, 0xFE, 0xED, 0x49,
++0xFD, 0xEC, 0x48, 0xFC, 0x22, 0xE0, 0xF8, 0xA3,
++0xE0, 0xF9, 0xA3, 0xE0, 0xFA, 0xA3, 0xE0, 0xFB,
++0x22, 0xE0, 0xFB, 0xA3, 0xE0, 0xFA, 0xA3, 0xE0,
++0xF9, 0x22, 0xEB, 0xF0, 0xA3, 0xEA, 0xF0, 0xA3,
++0xE9, 0xF0, 0x22, 0xD0, 0x83, 0xD0, 0x82, 0xF8,
++0xE4, 0x93, 0x70, 0x12, 0x74, 0x01, 0x93, 0x70,
++0x0D, 0xA3, 0xA3, 0x93, 0xF8, 0x74, 0x01, 0x93,
++0xF5, 0x82, 0x88, 0x83, 0xE4, 0x73, 0x74, 0x02,
++0x93, 0x68, 0x60, 0xEF, 0xA3, 0xA3, 0xA3, 0x80,
++0xDF, 0x02, 0x86, 0xAF, 0x02, 0x83, 0xDD, 0xE4,
++0x93, 0xA3, 0xF8, 0xE4, 0x93, 0xA3, 0x40, 0x03,
++0xF6, 0x80, 0x01, 0xF2, 0x08, 0xDF, 0xF4, 0x80,
++0x29, 0xE4, 0x93, 0xA3, 0xF8, 0x54, 0x07, 0x24,
++0x0C, 0xC8, 0xC3, 0x33, 0xC4, 0x54, 0x0F, 0x44,
++0x20, 0xC8, 0x83, 0x40, 0x04, 0xF4, 0x56, 0x80,
++0x01, 0x46, 0xF6, 0xDF, 0xE4, 0x80, 0x0B, 0x01,
++0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x90,
++0x86, 0xF4, 0xE4, 0x7E, 0x01, 0x93, 0x60, 0xBC,
++0xA3, 0xFF, 0x54, 0x3F, 0x30, 0xE5, 0x09, 0x54,
++0x1F, 0xFE, 0xE4, 0x93, 0xA3, 0x60, 0x01, 0x0E,
++0xCF, 0x54, 0xC0, 0x25, 0xE0, 0x60, 0xA8, 0x40,
++0xB8, 0xE4, 0x93, 0xA3, 0xFA, 0xE4, 0x93, 0xA3,
++0xF8, 0xE4, 0x93, 0xA3, 0xC8, 0xC5, 0x82, 0xC8,
++0xCA, 0xC5, 0x83, 0xCA, 0xF0, 0xA3, 0xC8, 0xC5,
++0x82, 0xC8, 0xCA, 0xC5, 0x83, 0xCA, 0xDF, 0xE9,
++0xDE, 0xE7, 0x80, 0xBE, 0x41, 0x97, 0x71, 0x00,
++0x41, 0x97, 0x75, 0x00, 0x00, 0xCF, 0x74, 0xDE,
++0x7E, 0x8B, 0xE6, 0x90, 0x97, 0x70, 0xEF, 0xF0,
++0x7F, 0x02, 0xB1, 0x27, 0x90, 0x86, 0xAF, 0xE0,
++0xFF, 0x90, 0x97, 0x70, 0xE0, 0xFE, 0xEF, 0x4E,
++0x90, 0x86, 0xAF, 0xF0, 0x22, 0x90, 0x02, 0x09,
++0xE0, 0xFD, 0x12, 0x02, 0x06, 0xFE, 0xAF, 0x05,
++0xED, 0x2E, 0x90, 0x86, 0xB4, 0xF1, 0x9F, 0xFF,
++0xED, 0x2F, 0x90, 0x86, 0xB5, 0xF1, 0x71, 0xFF,
++0xED, 0x2F, 0x90, 0x86, 0xB6, 0x12, 0xB7, 0x77,
++0xFF, 0xED, 0x2F, 0x90, 0x86, 0xB7, 0xF1, 0xFC,
++0xFF, 0xED, 0x2F, 0x90, 0x86, 0xB8, 0xF0, 0xF1,
++0x63, 0xFF, 0xED, 0x2F, 0x90, 0x86, 0xB9, 0xF1,
++0x69, 0xFF, 0xAE, 0x05, 0xED, 0x2F, 0x90, 0x86,
++0xBA, 0xF0, 0x22, 0x90, 0x00, 0x05, 0x02, 0x02,
++0x1F, 0xF0, 0x90, 0x00, 0x06, 0x02, 0x02, 0x1F,
++0x4F, 0xF0, 0x90, 0x00, 0x02, 0x02, 0x02, 0x1F,
++0x12, 0xA4, 0x7F, 0x12, 0x02, 0x06, 0x90, 0x93,
++0x60, 0xF1, 0x9F, 0x90, 0x93, 0x61, 0xF1, 0x71,
++0x90, 0x93, 0x7B, 0x12, 0xB7, 0x77, 0x90, 0x93,
++0x7C, 0xF1, 0xFC, 0x90, 0x93, 0x96, 0xF0, 0xF1,
++0x63, 0x90, 0x93, 0x97, 0xF0, 0x22, 0x4F, 0xF0,
++0x90, 0x00, 0x01, 0x02, 0x02, 0x1F, 0x12, 0xB8,
++0x87, 0xFF, 0xF1, 0xA0, 0xFE, 0x54, 0x03, 0xFD,
++0xEE, 0x13, 0x13, 0x54, 0x07, 0xFB, 0xC0, 0x03,
++0xF1, 0xF4, 0xF1, 0x72, 0x54, 0x0F, 0x90, 0x97,
++0x5B, 0xF0, 0xD0, 0x03, 0x12, 0xEC, 0x54, 0xF1,
++0xF4, 0xF1, 0xA0, 0xFE, 0x54, 0x03, 0x12, 0x8D,
++0x25, 0x90, 0x95, 0x5A, 0x74, 0x10, 0xF0, 0x90,
++0x95, 0x7C, 0x74, 0x07, 0xF1, 0xF3, 0x12, 0x02,
++0x06, 0x90, 0x95, 0x5C, 0xF0, 0x7B, 0x01, 0x7A,
++0x95, 0x79, 0x5A, 0x12, 0x90, 0x33, 0x7F, 0x04,
++0x02, 0x04, 0x7E, 0xF0, 0x90, 0x95, 0x57, 0xC1,
++0x39, 0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x00, 0x04,
++0x02, 0x02, 0x1F, 0x90, 0x95, 0x57, 0x12, 0x86,
++0x42, 0x90, 0x93, 0xE7, 0xE0, 0x70, 0x13, 0x12,
++0x87, 0xF4, 0x12, 0x02, 0x06, 0x13, 0x13, 0x54,
++0x3F, 0x30, 0xE0, 0x06, 0x90, 0x93, 0xED, 0x74,
++0x01, 0xF0, 0x90, 0x93, 0xE9, 0xE0, 0x70, 0x13,
++0x12, 0x87, 0xF4, 0x12, 0x02, 0x06, 0xC4, 0x54,
++0x0F, 0xFF, 0xBF, 0x05, 0x06, 0x90, 0x93, 0xEE,
++0x74, 0x01, 0xF0, 0x12, 0x87, 0xF4, 0x12, 0x87,
++0xA0, 0xFF, 0x90, 0x95, 0x5B, 0xF0, 0x12, 0x02,
++0x06, 0xC3, 0x13, 0x30, 0xE0, 0x0C, 0x12, 0x87,
++0xF4, 0x12, 0x87, 0x72, 0x90, 0x95, 0x5C, 0xF0,
++0x80, 0x05, 0x90, 0x95, 0x5C, 0xEF, 0xF0, 0x90,
++0x95, 0x5B, 0xE0, 0x90, 0x95, 0x5A, 0xF0, 0x90,
++0x95, 0x5C, 0xE0, 0xFE, 0x90, 0x95, 0x5A, 0xE0,
++0xFF, 0xD3, 0x9E, 0x50, 0x3A, 0x12, 0x87, 0xF4,
++0x12, 0x02, 0x06, 0x54, 0x01, 0xFD, 0x12, 0x6E,
++0x71, 0x90, 0x95, 0x5A, 0xE0, 0xFF, 0x12, 0x78,
++0x4A, 0xEF, 0x90, 0x95, 0x5A, 0x70, 0x06, 0xE0,
++0xFF, 0xF1, 0xEB, 0x80, 0x05, 0xE0, 0xFF, 0x12,
++0xD8, 0x0C, 0x90, 0x93, 0xEE, 0xE0, 0x60, 0x07,
++0x90, 0x95, 0x5A, 0xE0, 0xFF, 0xF1, 0xEB, 0x90,
++0x95, 0x5A, 0xE0, 0x04, 0xF0, 0x80, 0xB8, 0x90,
++0x05, 0x5E, 0xE4, 0xF0, 0x90, 0x95, 0x5B, 0xE0,
++0x70, 0x1A, 0xFF, 0x12, 0x78, 0x4A, 0xEF, 0x70,
++0x13, 0x90, 0x86, 0x0C, 0x51, 0x65, 0x90, 0x8A,
++0xED, 0x51, 0x65, 0x12, 0xF2, 0x1B, 0x54, 0xBF,
++0xF0, 0x54, 0x7F, 0xF0, 0x22, 0x90, 0x97, 0x49,
++0x12, 0x86, 0x42, 0x90, 0x97, 0x48, 0xEF, 0xF0,
++0x12, 0x86, 0x4B, 0x89, 0x6B, 0x00, 0x89, 0x70,
++0x01, 0x89, 0x74, 0x06, 0x89, 0x8A, 0x10, 0x89,
++0x8F, 0x12, 0x89, 0x94, 0x14, 0x89, 0x99, 0x16,
++0x89, 0x9E, 0x18, 0x89, 0xA3, 0x19, 0x89, 0xA8,
++0x1B, 0x89, 0xAD, 0x1C, 0x89, 0xB2, 0x1E, 0x89,
++0xB7, 0x20, 0x89, 0xBC, 0x24, 0x89, 0xC1, 0x25,
++0x89, 0xC6, 0x27, 0x89, 0xCB, 0x29, 0x89, 0xD0,
++0x2A, 0x89, 0xD5, 0x40, 0x89, 0xDC, 0x42, 0x89,
++0xE7, 0x43, 0x8A, 0x55, 0x47, 0x89, 0xEC, 0x49,
++0x89, 0xF1, 0x60, 0x89, 0xF6, 0x61, 0x89, 0xFB,
++0x62, 0x8A, 0x00, 0x63, 0x8A, 0x05, 0x64, 0x8A,
++0x0A, 0x65, 0x8A, 0x0F, 0x66, 0x8A, 0x14, 0x67,
++0x8A, 0x19, 0x68, 0x8A, 0x1E, 0x69, 0x8A, 0x23,
++0x6B, 0x8A, 0x28, 0x6C, 0x8A, 0x2D, 0x6D, 0x8A,
++0x32, 0x6E, 0x8A, 0x37, 0x6F, 0x8A, 0x3C, 0x70,
++0x8A, 0x41, 0xC3, 0x89, 0x79, 0xC6, 0x89, 0x79,
++0xC7, 0x89, 0x79, 0xC8, 0x89, 0x85, 0xCB, 0x00,
++0x00, 0x8A, 0x46, 0x51, 0x56, 0x02, 0x87, 0x1D,
++0x51, 0x56, 0x01, 0x03, 0x51, 0x56, 0x02, 0xB1,
++0xB4, 0x90, 0x97, 0x48, 0xE0, 0xFF, 0xA3, 0x12,
++0x86, 0x39, 0x02, 0xD8, 0x11, 0x51, 0x56, 0x02,
++0xD9, 0x20, 0x51, 0x56, 0x02, 0x97, 0xFA, 0x51,
++0x56, 0x02, 0xAF, 0xE5, 0x51, 0x56, 0x02, 0xB7,
++0xDA, 0x51, 0x56, 0x02, 0x87, 0x78, 0x51, 0x56,
++0x02, 0x9F, 0xFA, 0x51, 0x56, 0x02, 0xA8, 0x28,
++0x51, 0x56, 0x02, 0xA8, 0xCA, 0x51, 0x56, 0x02,
++0x87, 0xA6, 0x51, 0x56, 0x02, 0xB1, 0x35, 0x51,
++0x56, 0x02, 0xB7, 0xE9, 0x51, 0x56, 0x02, 0xA1,
++0x12, 0x51, 0x56, 0x02, 0xC0, 0x04, 0x51, 0x56,
++0x02, 0xA9, 0x4B, 0x51, 0x56, 0x02, 0xCF, 0xF6,
++0x51, 0x56, 0x02, 0xC0, 0x43, 0x51, 0x56, 0x90,
++0x8A, 0xA5, 0x80, 0x05, 0x51, 0x56, 0x90, 0x8A,
++0xB5, 0x12, 0xB3, 0xE4, 0x02, 0x04, 0x7E, 0x51,
++0x56, 0x02, 0x25, 0xEC, 0x51, 0x56, 0x02, 0xE9,
++0xD7, 0x51, 0x56, 0x02, 0xD0, 0x0B, 0x51, 0x56,
++0x02, 0x77, 0x4F, 0x51, 0x56, 0x02, 0x7C, 0x60,
++0x51, 0x56, 0x02, 0x7A, 0xC6, 0x51, 0x56, 0x02,
++0x5D, 0x36, 0x51, 0x56, 0x02, 0x7B, 0xE9, 0x51,
++0x56, 0x02, 0x70, 0x33, 0x51, 0x56, 0x02, 0x48,
++0xC9, 0x51, 0x56, 0x02, 0x79, 0xF3, 0x51, 0x56,
++0x02, 0xB2, 0x49, 0x51, 0x56, 0x02, 0x51, 0x7B,
++0x51, 0x56, 0x02, 0x79, 0x30, 0x51, 0x56, 0x02,
++0x57, 0xF2, 0x51, 0x56, 0x02, 0x74, 0x8D, 0x51,
++0x56, 0x02, 0x78, 0x9A, 0x51, 0x56, 0x02, 0x5E,
++0x0B, 0x51, 0x56, 0x02, 0xD7, 0xF6, 0x90, 0x01,
++0xC0, 0xE0, 0x44, 0x01, 0xF0, 0x90, 0x97, 0x48,
++0xE0, 0x90, 0x01, 0xC2, 0xF0, 0x22, 0x90, 0x97,
++0x49, 0x02, 0x86, 0x39, 0x7D, 0xFF, 0xE4, 0xFF,
++0xF1, 0x5D, 0x90, 0x8A, 0xFD, 0xE0, 0xFE, 0xA3,
++0xE0, 0xAA, 0x06, 0xF9, 0x02, 0x04, 0x7A, 0xD3,
++0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x97,
++0x77, 0xED, 0xF0, 0x90, 0x88, 0x31, 0xE0, 0xFE,
++0xC4, 0x13, 0x13, 0x54, 0x03, 0x30, 0xE0, 0x02,
++0x61, 0xE1, 0xEE, 0x12, 0xAE, 0x75, 0x30, 0xE0,
++0x02, 0x61, 0xE1, 0x90, 0x88, 0x39, 0xE0, 0xFE,
++0x6F, 0x70, 0x02, 0x61, 0xE1, 0xEF, 0x70, 0x02,
++0x61, 0x3D, 0x24, 0xFE, 0x70, 0x02, 0x61, 0x82,
++0x24, 0xFE, 0x60, 0x4F, 0x24, 0xFC, 0x70, 0x02,
++0x61, 0xC7, 0x24, 0xFC, 0x60, 0x02, 0x61, 0xDA,
++0xEE, 0xB4, 0x0E, 0x03, 0x12, 0x71, 0x5F, 0x90,
++0x88, 0x39, 0xE0, 0x70, 0x05, 0x7F, 0x01, 0x12,
++0x78, 0xC0, 0x90, 0x88, 0x39, 0xE0, 0xB4, 0x06,
++0x03, 0x12, 0x71, 0x24, 0x90, 0x88, 0x39, 0xE0,
++0xB4, 0x04, 0x11, 0x90, 0x97, 0x77, 0xE0, 0xFF,
++0x60, 0x05, 0x12, 0x67, 0x80, 0x80, 0x05, 0x90,
++0x8A, 0xED, 0x51, 0x65, 0x90, 0x88, 0x39, 0xE0,
++0x64, 0x08, 0x60, 0x02, 0x61, 0xDA, 0x12, 0x7B,
++0xCC, 0x61, 0xDA, 0x90, 0x88, 0x39, 0xE0, 0x70,
++0x05, 0x7F, 0x01, 0x12, 0x78, 0xC0, 0x90, 0x88,
++0x39, 0xE0, 0xB4, 0x06, 0x03, 0x12, 0x71, 0x24,
++0x90, 0x88, 0x39, 0xE0, 0xB4, 0x0E, 0x0B, 0x90,
++0x86, 0x00, 0x51, 0x65, 0xBF, 0x01, 0x03, 0x12,
++0x71, 0x5F, 0x90, 0x88, 0x39, 0xE0, 0x64, 0x0C,
++0x60, 0x02, 0x61, 0xDA, 0x90, 0x86, 0x00, 0x51,
++0x65, 0xEF, 0x64, 0x01, 0x60, 0x02, 0x61, 0xDA,
++0x12, 0x68, 0xC2, 0x61, 0xDA, 0x90, 0x88, 0x39,
++0xE0, 0xB4, 0x0E, 0x0B, 0x90, 0x86, 0x00, 0x51,
++0x65, 0xBF, 0x01, 0x03, 0x12, 0x71, 0x5F, 0x90,
++0x88, 0x39, 0xE0, 0xB4, 0x06, 0x03, 0x12, 0x71,
++0x24, 0x90, 0x88, 0x39, 0xE0, 0xB4, 0x0C, 0x0B,
++0x90, 0x86, 0x00, 0x51, 0x65, 0xBF, 0x01, 0x03,
++0x12, 0x68, 0xC2, 0x90, 0x88, 0x39, 0xE0, 0x64,
++0x04, 0x70, 0x67, 0x90, 0x86, 0x02, 0x51, 0x65,
++0xEF, 0x64, 0x01, 0x70, 0x5D, 0x12, 0x73, 0x5A,
++0x80, 0x58, 0x90, 0x88, 0x39, 0xE0, 0xB4, 0x0E,
++0x0B, 0x90, 0x86, 0x00, 0x51, 0x65, 0xBF, 0x01,
++0x03, 0x12, 0x71, 0x5F, 0x90, 0x88, 0x39, 0xE0,
++0xB4, 0x06, 0x03, 0x12, 0x71, 0x24, 0x90, 0x88,
++0x39, 0xE0, 0xB4, 0x0C, 0x0B, 0x90, 0x86, 0x00,
++0x51, 0x65, 0xBF, 0x01, 0x03, 0x12, 0x68, 0xC2,
++0x90, 0x88, 0x39, 0xE0, 0x70, 0x05, 0x7F, 0x01,
++0x12, 0x78, 0xC0, 0x90, 0x88, 0x39, 0xE0, 0xB4,
++0x04, 0x18, 0x12, 0x7A, 0x49, 0x80, 0x13, 0x90,
++0x88, 0x39, 0xE0, 0xB4, 0x0C, 0x0C, 0x90, 0x88,
++0x32, 0x12, 0xA7, 0x7F, 0x30, 0xE0, 0x03, 0x12,
++0x79, 0xD4, 0x90, 0x88, 0x39, 0x12, 0xBF, 0xC2,
++0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xE4, 0xFB,
++0xFA, 0xFD, 0x7F, 0x01, 0x12, 0x85, 0x4E, 0x90,
++0x95, 0xD9, 0xEF, 0xF0, 0x60, 0xF0, 0x90, 0x86,
++0xAF, 0xE0, 0xFF, 0x70, 0x04, 0xA3, 0xE0, 0x60,
++0xE5, 0xC2, 0xAF, 0xEF, 0x30, 0xE0, 0x0F, 0x90,
++0x86, 0xAF, 0xE0, 0x54, 0xFE, 0xF0, 0xE4, 0xFF,
++0x12, 0xB5, 0x91, 0x12, 0xC5, 0x5D, 0x91, 0x41,
++0x30, 0xE1, 0x08, 0x54, 0xFD, 0xF0, 0x90, 0x86,
++0x08, 0x51, 0x65, 0x91, 0x41, 0x30, 0xE2, 0x08,
++0x54, 0xFB, 0xF0, 0x90, 0x86, 0x0A, 0x51, 0x65,
++0x91, 0x41, 0x30, 0xE6, 0x08, 0x54, 0xBF, 0xF0,
++0x90, 0x8A, 0x7D, 0x51, 0x65, 0xD2, 0xAF, 0x80,
++0xB5, 0xD2, 0xAF, 0xC2, 0xAF, 0x90, 0x86, 0xAF,
++0xE0, 0x22, 0x51, 0x62, 0xEF, 0x70, 0x02, 0xFF,
++0x22, 0x12, 0x99, 0x85, 0x90, 0x93, 0xAC, 0xF0,
++0x90, 0x93, 0x58, 0xE0, 0xFF, 0xC3, 0x13, 0xFE,
++0xEF, 0x54, 0xF1, 0xFF, 0xEE, 0x04, 0x54, 0x07,
++0x25, 0xE0, 0x4F, 0xF0, 0xA3, 0xE0, 0xFF, 0x90,
++0x93, 0x58, 0xE0, 0xFE, 0xC3, 0x13, 0x54, 0x07,
++0xB5, 0x07, 0x04, 0xEE, 0x54, 0xF1, 0xF0, 0x12,
++0x99, 0x85, 0xF5, 0x7D, 0xE4, 0x90, 0x93, 0x5A,
++0xF0, 0xE5, 0x7D, 0x75, 0xF0, 0x1B, 0xA4, 0x24,
++0x5F, 0xF5, 0x82, 0xE4, 0x34, 0x93, 0xF5, 0x83,
++0xE0, 0x30, 0xE0, 0x28, 0xB1, 0x19, 0xE0, 0x24,
++0xAF, 0xF5, 0x82, 0xE4, 0x34, 0x93, 0xF5, 0x83,
++0xE0, 0xFF, 0xD1, 0xF5, 0xF5, 0x83, 0xEF, 0xB1,
++0x18, 0xE0, 0x04, 0xB1, 0x18, 0xE0, 0xFF, 0x90,
++0x93, 0xAE, 0xE0, 0xFE, 0xEF, 0xB5, 0x06, 0x04,
++0xB1, 0x19, 0xE4, 0xF0, 0xD1, 0xF5, 0xF5, 0x83,
++0xE0, 0xFC, 0x90, 0x93, 0xAC, 0xE0, 0xD1, 0xF7,
++0xF5, 0x83, 0xE0, 0x6C, 0x60, 0x0D, 0xE5, 0x7D,
++0xF1, 0xD0, 0x12, 0xEC, 0x3F, 0xE5, 0x7D, 0xF1,
++0xD0, 0xB1, 0x25, 0xE5, 0x7D, 0x12, 0x9A, 0xB1,
++0xFF, 0x60, 0x03, 0xBF, 0x02, 0x0F, 0xE5, 0x7D,
++0x12, 0x98, 0x20, 0xE0, 0xFF, 0x7E, 0x00, 0x7B,
++0x04, 0xE4, 0xFD, 0xF1, 0x80, 0xAD, 0x7D, 0x7F,
++0x01, 0x12, 0x99, 0x91, 0x90, 0x93, 0xAD, 0xE0,
++0xC3, 0x13, 0x54, 0x03, 0xFF, 0xBF, 0x02, 0x05,
++0xE4, 0xFF, 0x12, 0xEB, 0x10, 0x7F, 0x01, 0x22,
++0xF0, 0x74, 0xD2, 0x25, 0x7D, 0xF5, 0x82, 0xE4,
++0x34, 0x93, 0xF5, 0x83, 0x22, 0xFF, 0xEE, 0x13,
++0x13, 0x54, 0x07, 0xFD, 0xD3, 0x10, 0xAF, 0x01,
++0xC3, 0xC0, 0xD0, 0x90, 0x97, 0x6E, 0xED, 0xF0,
++0xE4, 0xA3, 0xF0, 0xEF, 0x14, 0x60, 0x02, 0xC1,
++0x10, 0x90, 0x06, 0x03, 0xE0, 0x54, 0xFB, 0xF0,
++0x90, 0x97, 0x6E, 0xE0, 0xFB, 0xC4, 0x33, 0x54,
++0xE0, 0xFE, 0x90, 0x04, 0x42, 0xE0, 0x54, 0x9F,
++0x4E, 0xFE, 0xF0, 0xE4, 0xFD, 0x12, 0xEC, 0xDB,
++0x90, 0x97, 0x6F, 0xEF, 0xF0, 0x90, 0x04, 0x83,
++0xF0, 0x90, 0x97, 0x13, 0x12, 0x04, 0x3D, 0x00,
++0x00, 0x00, 0x01, 0x90, 0x97, 0x17, 0x12, 0x04,
++0x3D, 0x00, 0x00, 0x00, 0x01, 0xD1, 0xD8, 0x12,
++0x04, 0x3D, 0x00, 0x00, 0x00, 0x01, 0x90, 0x97,
++0x17, 0x12, 0x04, 0x3D, 0x00, 0x00, 0x00, 0x01,
++0x7F, 0x00, 0x7E, 0x09, 0xD1, 0xDC, 0x12, 0x04,
++0x3D, 0x00, 0x00, 0x00, 0x10, 0x90, 0x97, 0x6E,
++0xF1, 0xE4, 0xEF, 0x54, 0x03, 0xFF, 0xE4, 0x78,
++0x01, 0x12, 0x03, 0xEB, 0x78, 0x04, 0xD1, 0xE2,
++0x7F, 0x00, 0x7E, 0x0A, 0xD1, 0xDC, 0x12, 0x04,
++0x3D, 0x00, 0x00, 0x0C, 0x00, 0x90, 0x97, 0x6E,
++0xF1, 0xE4, 0xEF, 0x54, 0x03, 0xFF, 0xE4, 0x78,
++0x0A, 0xD1, 0xE2, 0x7F, 0x00, 0x7E, 0x0D, 0xD1,
++0xDC, 0x12, 0x04, 0x3D, 0x0C, 0x00, 0x00, 0x00,
++0x90, 0x97, 0x6F, 0xF1, 0xE4, 0xEF, 0x54, 0x03,
++0xFF, 0xE4, 0x78, 0x1A, 0xD1, 0xE2, 0x7F, 0x18,
++0xD1, 0xDA, 0x12, 0x04, 0x3D, 0x00, 0x00, 0x0C,
++0x00, 0x90, 0x97, 0x17, 0x12, 0x04, 0x3D, 0x00,
++0x00, 0x00, 0x00, 0xD1, 0xEB, 0x12, 0x04, 0x3D,
++0x00, 0x00, 0x0C, 0x00, 0x90, 0x97, 0x05, 0x12,
++0x04, 0x3D, 0x00, 0x00, 0x04, 0x00, 0x80, 0x58,
++0x90, 0x06, 0x03, 0xE0, 0x44, 0x04, 0xF0, 0x90,
++0x97, 0x13, 0x12, 0x04, 0x3D, 0x00, 0x00, 0x00,
++0x01, 0x90, 0x97, 0x17, 0x12, 0x04, 0x3D, 0x00,
++0x00, 0x00, 0x00, 0xD1, 0xD8, 0x12, 0x04, 0x3D,
++0x00, 0x00, 0x00, 0x01, 0x90, 0x97, 0x17, 0x12,
++0x04, 0x3D, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00,
++0x7E, 0x09, 0xD1, 0xDC, 0x12, 0x04, 0x3D, 0x00,
++0x00, 0x0C, 0x00, 0x90, 0x97, 0x17, 0x12, 0x04,
++0x3D, 0x00, 0x00, 0x0C, 0x00, 0xD1, 0xEB, 0x12,
++0x04, 0x3D, 0x00, 0x00, 0x0C, 0x00, 0x90, 0x97,
++0x05, 0x12, 0x04, 0x3D, 0x00, 0x00, 0x0C, 0x00,
++0x7D, 0x18, 0x7C, 0x00, 0xE4, 0xFF, 0x12, 0xEB,
++0xC9, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10,
++0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x97, 0x11,
++0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x12, 0x70, 0x70,
++0x90, 0x97, 0x1B, 0x12, 0x04, 0x31, 0x90, 0x97,
++0x13, 0x12, 0x04, 0xB8, 0x12, 0x03, 0xCD, 0x90,
++0x97, 0x1B, 0x12, 0xEC, 0xD5, 0xC0, 0x04, 0xC0,
++0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x97, 0x13,
++0x12, 0x04, 0xB8, 0x90, 0x97, 0x17, 0x12, 0xEC,
++0xD5, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0,
++0x00, 0x12, 0x86, 0x20, 0x90, 0x97, 0x1F, 0x12,
++0x04, 0x31, 0x90, 0x97, 0x1F, 0x12, 0xDF, 0x95,
++0x90, 0x97, 0x11, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF,
++0x12, 0x70, 0xAD, 0xD0, 0xD0, 0x92, 0xAF, 0x22,
++0x7F, 0x00, 0x7E, 0x08, 0xD1, 0x76, 0x90, 0x97,
++0x13, 0x22, 0x12, 0x03, 0xFE, 0x90, 0x97, 0x17,
++0x02, 0x04, 0x31, 0x7F, 0x84, 0x7E, 0x08, 0xD1,
++0x76, 0x90, 0x97, 0x01, 0x22, 0xE5, 0x7D, 0x75,
++0xF0, 0x1B, 0xA4, 0x24, 0x5B, 0xF5, 0x82, 0xE4,
++0x34, 0x93, 0x22, 0x8F, 0x65, 0x90, 0x05, 0x22,
++0xE0, 0x90, 0x95, 0x57, 0xF0, 0x7B, 0x17, 0x51,
++0x5C, 0xEF, 0x64, 0x01, 0x70, 0x34, 0xE5, 0x65,
++0xD1, 0xF7, 0xF5, 0x83, 0xE0, 0xFC, 0xF1, 0xCE,
++0x12, 0xEC, 0x3F, 0xF1, 0xCE, 0xB1, 0x25, 0xE5,
++0x65, 0x12, 0x9A, 0xB1, 0xFF, 0x60, 0x03, 0xBF,
++0x02, 0x0E, 0xE5, 0x65, 0x12, 0x98, 0x20, 0xE0,
++0xFF, 0x7E, 0x00, 0xE4, 0xFB, 0xFD, 0xF1, 0x80,
++0xAD, 0x65, 0x7F, 0x01, 0x12, 0x99, 0x91, 0x7F,
++0x01, 0x22, 0x90, 0x95, 0x57, 0xE0, 0xFD, 0x7B,
++0x49, 0xE4, 0xFF, 0xF1, 0x5D, 0x7F, 0x00, 0x22,
++0xE4, 0xFB, 0xFD, 0x7F, 0xFF, 0xEB, 0xB4, 0x57,
++0x05, 0x12, 0xF1, 0x9D, 0x80, 0x10, 0xEF, 0x70,
++0x07, 0x90, 0x93, 0xF3, 0xE0, 0x4D, 0x80, 0x06,
++0x12, 0xE9, 0xC4, 0x12, 0xF1, 0x9D, 0x90, 0x05,
++0x22, 0xF0, 0x90, 0x93, 0x01, 0xEB, 0xF0, 0x22,
++0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90,
++0x97, 0x36, 0xEE, 0xF0, 0xA3, 0x12, 0xB7, 0x6B,
++0x90, 0x04, 0x1D, 0xE0, 0x60, 0x2A, 0x90, 0x05,
++0x22, 0xE0, 0x90, 0x97, 0x3C, 0xF0, 0x7B, 0x14,
++0x51, 0x5C, 0xEF, 0x64, 0x01, 0x70, 0x08, 0x12,
++0xF0, 0x9D, 0x12, 0xF0, 0x8C, 0x80, 0x04, 0x7F,
++0x00, 0x80, 0x16, 0x90, 0x97, 0x3C, 0xE0, 0xFD,
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++0x04, 0x7E, 0x90, 0x86, 0xB3, 0xE0, 0xFF, 0xB4,
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++0xA3, 0x11, 0x45, 0x7F, 0x01, 0x12, 0x04, 0x7E,
++0x7E, 0x00, 0x7F, 0x02, 0x7D, 0x00, 0x7B, 0x01,
++0x7A, 0x88, 0x79, 0x9A, 0x12, 0x04, 0x80, 0x12,
++0xF1, 0xFB, 0x90, 0x06, 0x0A, 0xE0, 0x54, 0xF8,
++0xF0, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x90, 0x88,
++0x9C, 0xF0, 0x22, 0xE4, 0xFD, 0xFF, 0x02, 0x04,
++0x7E, 0xE0, 0xFF, 0x90, 0x8A, 0xD1, 0xE0, 0xFC,
++0xA3, 0xE0, 0xFD, 0xF5, 0x82, 0x8C, 0x83, 0x02,
++0x04, 0x7E, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0,
++0xD0, 0x90, 0x97, 0x43, 0xEF, 0xF0, 0xA3, 0xED,
++0xF0, 0x90, 0x86, 0xB1, 0xE0, 0x04, 0xF0, 0x90,
++0x88, 0x9D, 0xE0, 0x30, 0xE0, 0x07, 0x90, 0x05,
++0x10, 0xE4, 0xF0, 0xA3, 0xF0, 0x90, 0x04, 0x1D,
++0xE0, 0x60, 0x4A, 0x90, 0x05, 0x22, 0xE0, 0x90,
++0x97, 0x47, 0xF0, 0x7B, 0x26, 0x12, 0x8A, 0x5C,
++0xEF, 0x64, 0x01, 0x70, 0x0C, 0x12, 0xF0, 0x6A,
++0x90, 0x93, 0x58, 0xE0, 0x20, 0xE0, 0x1B, 0x80,
++0x0F, 0xF1, 0xBD, 0x30, 0xE0, 0x14, 0x12, 0xF0,
++0x6A, 0x90, 0x93, 0x58, 0xE0, 0x20, 0xE0, 0x0A,
++0x12, 0xF1, 0x62, 0xD1, 0xE6, 0x12, 0xE8, 0x98,
++0xEE, 0xF0, 0x90, 0x97, 0x47, 0xE0, 0xFD, 0x7B,
++0x27, 0xE4, 0xFF, 0x12, 0x8F, 0x5D, 0x12, 0xF1,
++0xD1, 0xD1, 0xE6, 0x80, 0x19, 0x12, 0xF1, 0xD1,
++0xD1, 0xE6, 0x12, 0xF0, 0x6A, 0x90, 0x93, 0x58,
++0xE0, 0x20, 0xE0, 0x0A, 0x12, 0xF1, 0x62, 0xD1,
++0xE6, 0x12, 0xE8, 0x98, 0xEE, 0xF0, 0x90, 0x88,
++0x9D, 0xE0, 0x30, 0xE0, 0x16, 0xF1, 0xBD, 0x30,
++0xE0, 0x11, 0x90, 0x05, 0x22, 0xE0, 0x54, 0x6F,
++0xFF, 0x90, 0x8A, 0xF9, 0xF1, 0xAB, 0x7D, 0x28,
++0x12, 0x04, 0x7E, 0x12, 0xF1, 0xC8, 0xD0, 0xD0,
++0x92, 0xAF, 0x22, 0x90, 0x88, 0x38, 0xE0, 0xFF,
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++0x82, 0x8C, 0x83, 0x22, 0x7F, 0xFB, 0x7E, 0x01,
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++0xE0, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x22, 0x90,
++0x8A, 0xF9, 0x11, 0x45, 0xD1, 0xDB, 0x90, 0x88,
++0x2F, 0x74, 0x01, 0xF0, 0x22, 0x90, 0x8A, 0xF9,
++0x11, 0x45, 0xD1, 0xDB, 0x12, 0xA4, 0x5D, 0x80,
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++0x8A, 0xF9, 0x11, 0x45, 0xD1, 0xDB, 0x80, 0xDE,
++0x80, 0xDC, 0x90, 0x88, 0x9D, 0xE0, 0xC4, 0x54,
++0x0F, 0x22, 0x90, 0x95, 0x57, 0x12, 0x86, 0x42,
++0x90, 0x04, 0x24, 0xE0, 0xFF, 0xE4, 0xFE, 0x12,
++0x87, 0xF4, 0x8E, 0x82, 0x12, 0xBC, 0x4E, 0x2F,
++0xFD, 0xEE, 0x11, 0x20, 0xED, 0xF0, 0x0E, 0xEE,
++0xB4, 0x03, 0xEC, 0x22, 0xC3, 0x13, 0x54, 0x07,
++0x75, 0xF0, 0x1B, 0xA4, 0x24, 0x64, 0xF5, 0x82,
++0xE4, 0x34, 0x93, 0xF5, 0x83, 0x22, 0xE4, 0x90,
++0x96, 0x23, 0xF0, 0x90, 0x93, 0x58, 0xE0, 0x20,
++0xE0, 0x02, 0x21, 0x0D, 0x51, 0xAD, 0x90, 0x96,
++0x20, 0xF0, 0x60, 0x05, 0xE0, 0x64, 0x02, 0x70,
++0x62, 0x90, 0x93, 0x5A, 0xE0, 0x70, 0x3E, 0x90,
++0x05, 0x22, 0xE0, 0x90, 0x96, 0x21, 0xF0, 0x7B,
++0x4E, 0x7D, 0x6F, 0xE4, 0xFF, 0x12, 0x8F, 0x5D,
++0x90, 0x93, 0x58, 0xE0, 0x11, 0x1C, 0xE0, 0xFF,
++0x7E, 0x00, 0x7B, 0x04, 0x7D, 0x01, 0x12, 0x8F,
++0x80, 0xBF, 0x01, 0x0D, 0x31, 0x0E, 0xE0, 0x44,
++0x01, 0xF0, 0x90, 0x93, 0x5A, 0x74, 0x01, 0xF0,
++0x22, 0x90, 0x96, 0x21, 0xE0, 0xFD, 0x7B, 0x4F,
++0xE4, 0xFF, 0x02, 0x8F, 0x5D, 0x90, 0x93, 0x5A,
++0xE0, 0xB4, 0x01, 0x03, 0x74, 0x05, 0xF0, 0x31,
++0x85, 0x31, 0x8E, 0x90, 0x93, 0x5A, 0xE0, 0x64,
++0x05, 0x70, 0x6A, 0x12, 0x8C, 0x4A, 0xEF, 0x70,
++0x64, 0x80, 0x5D, 0x90, 0x96, 0x20, 0xE0, 0xFF,
++0x64, 0x03, 0x60, 0x05, 0xEF, 0x64, 0x01, 0x70,
++0x54, 0x90, 0x93, 0x5A, 0xE0, 0x64, 0x05, 0x70,
++0x4C, 0x90, 0x96, 0x20, 0xE0, 0x64, 0x01, 0x70,
++0x35, 0x51, 0x95, 0xD3, 0x94, 0x1F, 0x90, 0x93,
++0x58, 0xE0, 0x40, 0x10, 0x11, 0x1D, 0xE0, 0xFF,
++0x90, 0x8A, 0xBF, 0x12, 0x97, 0xAB, 0x7D, 0x00,
++0x7C, 0x7C, 0x80, 0x17, 0x11, 0x1C, 0xE0, 0xFB,
++0x51, 0x95, 0x12, 0xF2, 0x03, 0xAF, 0x03, 0x90,
++0x8A, 0xBF, 0xE0, 0xFA, 0xA3, 0xE0, 0xFB, 0xF5,
++0x82, 0x8A, 0x83, 0x12, 0x04, 0x7E, 0x31, 0x85,
++0x31, 0x8E, 0x12, 0x8C, 0x4A, 0xEF, 0x70, 0x05,
++0x7F, 0x06, 0x12, 0xEB, 0x10, 0x22, 0x90, 0x93,
++0x58, 0xE0, 0xC3, 0x13, 0x54, 0x07, 0x75, 0xF0,
++0x1B, 0xA4, 0x24, 0x62, 0xF5, 0x82, 0xE4, 0x34,
++0x93, 0xF5, 0x83, 0x22, 0xE4, 0x90, 0x96, 0x1E,
++0xF0, 0x90, 0x93, 0x58, 0xE0, 0x30, 0xE0, 0x53,
++0xC3, 0x13, 0x54, 0x07, 0xFF, 0x31, 0x16, 0xE0,
++0xFE, 0x30, 0xE0, 0x47, 0xEF, 0x31, 0x16, 0xEE,
++0x54, 0xFE, 0xF0, 0xEF, 0x31, 0x16, 0x12, 0xA7,
++0x7F, 0x30, 0xE0, 0x0C, 0x90, 0x93, 0x58, 0xE0,
++0xFE, 0x31, 0x12, 0xEF, 0x54, 0xFB, 0xF1, 0xDE,
++0x90, 0x04, 0xE0, 0xE0, 0x30, 0xE1, 0x1B, 0xF1,
++0xCD, 0x31, 0x0E, 0xE0, 0x44, 0x02, 0xF0, 0xE4,
++0x90, 0x93, 0xDE, 0x31, 0x84, 0xFD, 0x7F, 0x02,
++0x31, 0x91, 0x90, 0x96, 0x1E, 0xE0, 0x60, 0x0B,
++0x01, 0x2E, 0x31, 0x0E, 0xE0, 0x54, 0xFD, 0xF0,
++0x12, 0x8F, 0x58, 0x22, 0xF0, 0x90, 0x93, 0x58,
++0xE0, 0xC3, 0x13, 0x54, 0x07, 0x22, 0xFD, 0x7F,
++0x02, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0,
++0x90, 0x97, 0x63, 0xED, 0xF0, 0x90, 0x97, 0x62,
++0xEF, 0xF0, 0x64, 0x02, 0x70, 0x25, 0x90, 0x05,
++0x22, 0xE0, 0x90, 0x97, 0x64, 0xF0, 0x7B, 0x4A,
++0x7D, 0x6F, 0x12, 0x8A, 0x5E, 0xBF, 0x01, 0x07,
++0x90, 0x04, 0xD4, 0x74, 0xFF, 0x80, 0x49, 0x90,
++0x97, 0x64, 0xE0, 0xFD, 0x7B, 0x46, 0x12, 0x8F,
++0x51, 0x80, 0x42, 0x90, 0x97, 0x62, 0xE0, 0x64,
++0x01, 0x70, 0x31, 0x12, 0x8F, 0x59, 0x90, 0x97,
++0x63, 0xE0, 0xFF, 0x75, 0xF0, 0x1B, 0xA4, 0x24,
++0x60, 0xF5, 0x82, 0xE4, 0x34, 0x93, 0xF5, 0x83,
++0xE0, 0xF4, 0x90, 0x04, 0xD4, 0xF0, 0xEF, 0x75,
++0xF0, 0x1B, 0xA4, 0x24, 0x61, 0xF5, 0x82, 0xE4,
++0x34, 0x93, 0xF5, 0x83, 0xE0, 0xF4, 0x90, 0x04,
++0xD5, 0xF0, 0x80, 0x07, 0x90, 0x04, 0xD4, 0xE4,
++0xF0, 0xA3, 0xF0, 0x7F, 0x01, 0xD0, 0xD0, 0x92,
++0xAF, 0x22, 0x90, 0x93, 0x58, 0xE0, 0x30, 0xE0,
++0x7B, 0x90, 0x93, 0xDA, 0xE0, 0x04, 0x31, 0x84,
++0x04, 0xFF, 0x90, 0x96, 0x1E, 0xF0, 0x90, 0x93,
++0x59, 0xE0, 0xB5, 0x07, 0x05, 0xE4, 0x90, 0x96,
++0x1E, 0xF0, 0x90, 0x93, 0xD8, 0xE0, 0xFF, 0x60,
++0x12, 0x90, 0x96, 0x1E, 0x51, 0x98, 0xC3, 0x9F,
++0xB1, 0x05, 0xFB, 0xFD, 0x7F, 0x50, 0x7E, 0x01,
++0x12, 0x66, 0x33, 0x90, 0x96, 0x1E, 0xE0, 0x51,
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++0x60, 0x0E, 0x14, 0x60, 0x07, 0x14, 0x60, 0x08,
++0x24, 0x03, 0x70, 0x08, 0xF1, 0xD4, 0x80, 0x02,
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++0x51, 0x98, 0x24, 0xFC, 0xFF, 0x12, 0xD3, 0x43,
++0xEF, 0xB1, 0x3D, 0x90, 0x96, 0x1E, 0x51, 0x98,
++0xB1, 0x05, 0xF1, 0xF1, 0x22, 0x90, 0x96, 0x22,
++0xE0, 0x75, 0xF0, 0x1B, 0xA4, 0x24, 0x5D, 0xF5,
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++0xE0, 0x54, 0x12, 0xF1, 0x6E, 0x40, 0x4F, 0x90,
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++0xF0, 0x90, 0x93, 0xE3, 0xE0, 0x90, 0x93, 0x5D,
++0xF0, 0x90, 0x93, 0xE4, 0xE0, 0x90, 0x93, 0x78,
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++0x51, 0xA8, 0xFF, 0x64, 0x02, 0x60, 0x03, 0xEF,
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++0xB1, 0x1D, 0x90, 0x92, 0x21, 0xF0, 0xE4, 0xF1,
++0xF1, 0xE4, 0x90, 0x93, 0xDA, 0xF0, 0x90, 0x93,
++0xD5, 0xE0, 0x20, 0xE0, 0x02, 0x81, 0xF4, 0x90,
++0x93, 0xD9, 0xE0, 0xFF, 0xC3, 0x13, 0xFE, 0x54,
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++0xFF, 0xEE, 0x14, 0x54, 0x1F, 0xFE, 0x25, 0xE0,
++0x4F, 0xF0, 0xE0, 0xC3, 0x13, 0x54, 0x1F, 0x60,
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++0xE0, 0x44, 0x01, 0xF0, 0xA3, 0xE0, 0x54, 0xFE,
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++0xF0, 0x90, 0x05, 0x22, 0xE0, 0x44, 0x40, 0xFD,
++0x7B, 0x58, 0x7F, 0x40, 0x12, 0x8F, 0x5D, 0x90,
++0x05, 0x50, 0xE0, 0x54, 0xF7, 0xF0, 0x90, 0x05,
++0x69, 0x12, 0x8F, 0xE4, 0xB1, 0x0F, 0x90, 0x05,
++0x68, 0x12, 0x8F, 0xE4, 0x12, 0x86, 0x20, 0xC0,
++0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90,
++0x05, 0x6A, 0x12, 0x8F, 0xE4, 0x78, 0x10, 0x12,
++0x03, 0xFE, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01,
++0xD0, 0x00, 0x12, 0x86, 0x20, 0xC0, 0x04, 0xC0,
++0x05, 0xC0, 0x06, 0xC0, 0x07, 0x12, 0x8F, 0xE3,
++0x78, 0x18, 0x12, 0x03, 0xFE, 0xD0, 0x03, 0xD0,
++0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x86, 0x20,
++0x90, 0x95, 0xF0, 0x12, 0x04, 0x31, 0x91, 0xF7,
++0x90, 0x95, 0xF8, 0x12, 0x04, 0x31, 0x90, 0x05,
++0x6D, 0x12, 0x8F, 0xE4, 0xB1, 0x0F, 0x90, 0x05,
++0x6C, 0x12, 0x8F, 0xE4, 0x12, 0x86, 0x20, 0xC0,
++0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90,
++0x05, 0x6E, 0x12, 0x8F, 0xE4, 0x78, 0x10, 0x12,
++0x03, 0xFE, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01,
++0xD0, 0x00, 0x12, 0x86, 0x20, 0xC0, 0x04, 0xC0,
++0x05, 0xC0, 0x06, 0xC0, 0x07, 0x12, 0x8F, 0xE3,
++0x78, 0x18, 0x12, 0x03, 0xFE, 0xD0, 0x03, 0xD0,
++0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x86, 0x20,
++0x90, 0x95, 0xF4, 0x12, 0x04, 0x31, 0x90, 0x95,
++0xF0, 0x12, 0x86, 0x2D, 0xC0, 0x00, 0xC0, 0x01,
++0xC0, 0x02, 0xC0, 0x03, 0x90, 0x93, 0xD5, 0xE0,
++0xC3, 0x13, 0x54, 0x7F, 0xFF, 0xE4, 0xFC, 0xFD,
++0xFE, 0xFB, 0x7A, 0x04, 0xF9, 0xF8, 0x12, 0x85,
++0xC4, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0,
++0x00, 0x12, 0x85, 0xA9, 0x90, 0x95, 0xF0, 0x12,
++0x04, 0x31, 0x90, 0x95, 0xF8, 0x12, 0x04, 0xB8,
++0x90, 0x95, 0xF0, 0x12, 0xAF, 0xD6, 0x50, 0x0E,
++0x91, 0xFF, 0xEF, 0x24, 0x01, 0x12, 0xF1, 0x92,
++0x90, 0x95, 0xF4, 0x12, 0x04, 0x31, 0x91, 0xFF,
++0x78, 0x18, 0x12, 0x03, 0xEB, 0x90, 0x05, 0x67,
++0x91, 0xFD, 0x78, 0x10, 0x12, 0x03, 0xEB, 0x90,
++0x05, 0x66, 0x91, 0xFD, 0x78, 0x08, 0x12, 0x03,
++0xEB, 0x90, 0x05, 0x65, 0x91, 0xFD, 0x90, 0x05,
++0x64, 0x91, 0xF5, 0x78, 0x18, 0x12, 0x03, 0xEB,
++0x90, 0x05, 0x63, 0x91, 0xF5, 0x78, 0x10, 0x12,
++0x03, 0xEB, 0x90, 0x05, 0x62, 0x91, 0xF5, 0x78,
++0x08, 0x12, 0x03, 0xEB, 0x90, 0x05, 0x61, 0x91,
++0xF5, 0x90, 0x05, 0x60, 0xEF, 0xF0, 0x90, 0x05,
++0x50, 0xE0, 0x44, 0x08, 0xF0, 0x90, 0x05, 0x22,
++0xE0, 0x54, 0xBF, 0xFD, 0x7B, 0x59, 0x7F, 0x40,
++0x12, 0x8F, 0x5D, 0x7F, 0x08, 0x12, 0xEB, 0x10,
++0x90, 0x93, 0xD9, 0xE0, 0x54, 0xC1, 0x44, 0x28,
++0xF0, 0x44, 0x01, 0xF0, 0x22, 0xEF, 0xF0, 0x90,
++0x95, 0xF0, 0x02, 0x04, 0xB8, 0xEF, 0xF0, 0x90,
++0x95, 0xF4, 0x02, 0x04, 0xB8, 0x90, 0x92, 0x21,
++0xF0, 0xE4, 0x90, 0x92, 0x20, 0xF0, 0x22, 0x78,
++0x08, 0x12, 0x03, 0xFE, 0xA8, 0x04, 0xA9, 0x05,
++0xAA, 0x06, 0xAB, 0x07, 0x22, 0xE4, 0x90, 0x92,
++0x20, 0xF0, 0x90, 0x95, 0xFC, 0xE0, 0xFF, 0x90,
++0x93, 0xD6, 0xE0, 0x2F, 0x22, 0xE0, 0x44, 0x02,
++0xF0, 0xE4, 0x90, 0x92, 0x20, 0xF0, 0x90, 0x88,
++0x94, 0xE0, 0x90, 0x92, 0x21, 0xF0, 0xE4, 0xFB,
++0xFD, 0x7F, 0x54, 0x7E, 0x01, 0x02, 0x66, 0x33,
++0xE4, 0xF5, 0x7C, 0x90, 0x88, 0x36, 0xE0, 0x60,
++0x66, 0xF1, 0xE6, 0x70, 0x62, 0x12, 0xF0, 0xCF,
++0xF0, 0x75, 0x7C, 0x01, 0x90, 0x88, 0x2C, 0xE0,
++0x30, 0xE0, 0x11, 0x90, 0x88, 0x30, 0xE0, 0xB4,
++0x02, 0x03, 0xE4, 0xF5, 0x7C, 0xD1, 0x4C, 0xEF,
++0x70, 0x02, 0xF5, 0x7C, 0xE5, 0x7C, 0x60, 0x3F,
++0x90, 0x88, 0x39, 0xE0, 0x20, 0xE2, 0x08, 0x90,
++0x8A, 0xB9, 0x12, 0x90, 0x45, 0xF1, 0xC6, 0xF1,
++0xD6, 0x90, 0x88, 0x3F, 0xE0, 0x60, 0x04, 0x64,
++0x01, 0x70, 0x0F, 0xB1, 0xB8, 0xFF, 0xA3, 0xE0,
++0x2F, 0xB1, 0x3A, 0xB1, 0xBD, 0xFF, 0xA3, 0xE0,
++0x80, 0x0B, 0xB1, 0xB8, 0xB1, 0xC7, 0x2F, 0xB1,
++0x3A, 0xB1, 0xBD, 0xB1, 0xC7, 0x2F, 0x33, 0x33,
++0x33, 0x54, 0xF8, 0x90, 0x88, 0x4F, 0xF0, 0x22,
++0xE4, 0x90, 0x92, 0x20, 0xF0, 0x90, 0x88, 0x3E,
++0xE0, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x22, 0xFF,
++0xA3, 0xE0, 0x75, 0xF0, 0x03, 0xA4, 0x24, 0xFE,
++0x22, 0x90, 0x88, 0x2C, 0xE0, 0x30, 0xE0, 0x10,
++0xA3, 0x74, 0x01, 0xF0, 0x90, 0x88, 0x2C, 0xE0,
++0xFF, 0xC3, 0x13, 0x30, 0xE0, 0x02, 0xD1, 0x58,
++0xB1, 0x48, 0xE4, 0xFF, 0x12, 0xAD, 0xED, 0x90,
++0x8B, 0x07, 0x12, 0x8A, 0x65, 0x41, 0xC2, 0xE4,
++0x90, 0x96, 0x1E, 0xF0, 0x90, 0x88, 0x36, 0xE0,
++0x60, 0x49, 0xF1, 0xE6, 0x70, 0x45, 0x12, 0xAF,
++0xDD, 0xF0, 0x12, 0xF0, 0xCF, 0xF1, 0xDE, 0xE4,
++0x90, 0x88, 0x3D, 0xF0, 0x90, 0x88, 0x2C, 0xE0,
++0x30, 0xE0, 0x15, 0x90, 0x88, 0x30, 0xE0, 0xB4,
++0x02, 0x05, 0xE4, 0x90, 0x96, 0x1E, 0xF0, 0xD1,
++0x4C, 0xEF, 0x70, 0x04, 0x90, 0x96, 0x1E, 0xF0,
++0x90, 0x96, 0x1E, 0xE0, 0x60, 0x15, 0x90, 0x88,
++0x39, 0xE0, 0x20, 0xE2, 0x08, 0x90, 0x8A, 0xB9,
++0x12, 0x90, 0x45, 0xF1, 0xC6, 0xF1, 0xD6, 0xB1,
++0xB8, 0xB1, 0x3A, 0x22, 0x90, 0x05, 0x43, 0xE0,
++0x7F, 0x00, 0x30, 0xE7, 0x02, 0x7F, 0x01, 0x22,
++0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0xD1,
++0x4C, 0xBF, 0x01, 0x04, 0x7F, 0x01, 0x80, 0x02,
++0x7F, 0x02, 0x12, 0xA2, 0x86, 0xD0, 0xD0, 0x92,
++0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0,
++0xD0, 0xE4, 0x90, 0x96, 0x24, 0xF0, 0x90, 0x05,
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++0x60, 0xE0, 0x90, 0x96, 0x25, 0x12, 0x8F, 0xE2,
++0xB1, 0x0F, 0x90, 0x96, 0x25, 0x12, 0x8F, 0xE4,
++0x12, 0x86, 0x20, 0xC0, 0x04, 0xC0, 0x05, 0xC0,
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++0xE4, 0x78, 0x10, 0x12, 0x03, 0xFE, 0xD0, 0x03,
++0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x86,
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++0x07, 0x12, 0x8F, 0xE3, 0x78, 0x18, 0x12, 0x03,
++0xFE, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0,
++0x00, 0x12, 0x86, 0x20, 0x90, 0x96, 0x2D, 0x12,
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++0xC0, 0x00, 0xC0, 0x01, 0xC0, 0x02, 0xC0, 0x03,
++0x90, 0x95, 0x54, 0xE0, 0x24, 0x01, 0xFF, 0xE4,
++0x33, 0xFE, 0xE4, 0xFC, 0xFD, 0xFB, 0x7A, 0x90,
++0x79, 0x01, 0xF8, 0x12, 0x85, 0xC4, 0xD0, 0x03,
++0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x85,
++0xA9, 0x90, 0x96, 0x2D, 0x12, 0x04, 0x31, 0xF1,
++0xBA, 0x90, 0x05, 0x2C, 0xEF, 0xF0, 0xF1, 0xBA,
++0x78, 0x08, 0x12, 0x03, 0xEB, 0x90, 0x05, 0x2D,
++0xEF, 0xF0, 0xF1, 0xBA, 0x78, 0x10, 0x12, 0x03,
++0xEB, 0x90, 0x05, 0x2E, 0xEF, 0xF0, 0xF1, 0xBA,
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++0xEF, 0x12, 0xD9, 0x61, 0x90, 0x96, 0x29, 0x12,
++0x04, 0x31, 0xF1, 0xC0, 0xE4, 0xFF, 0xFE, 0xED,
++0x54, 0x03, 0xFD, 0xE4, 0xFC, 0xFB, 0xFA, 0xF9,
++0xF8, 0xC3, 0x12, 0x03, 0xDA, 0x70, 0x4E, 0xF1,
++0xC0, 0xE4, 0xFF, 0xEE, 0x54, 0xFC, 0xFE, 0xE4,
++0xFD, 0xFC, 0x78, 0x0A, 0x12, 0x03, 0xEB, 0x90,
++0x96, 0x24, 0xEF, 0xF0, 0x90, 0x95, 0x53, 0xE0,
++0xFE, 0xEF, 0xD3, 0x9E, 0x50, 0x07, 0x90, 0x96,
++0x24, 0xE0, 0xB5, 0x06, 0x20, 0x90, 0x96, 0x31,
++0x74, 0x28, 0xF0, 0x90, 0x96, 0x53, 0x74, 0x04,
++0xF0, 0x90, 0x96, 0x24, 0xE0, 0x90, 0x96, 0x33,
++0xF0, 0x7B, 0x01, 0x7A, 0x96, 0x79, 0x31, 0x12,
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++0x96, 0x1E, 0x74, 0x01, 0xF0, 0x22, 0xE4, 0xFF,
++0x12, 0x78, 0x4A, 0xEF, 0x64, 0x01, 0x22, 0xC1,
++0x72, 0xFB, 0xFD, 0x7F, 0x58, 0x7E, 0x01, 0x02,
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++0xE0, 0x54, 0xFE, 0xFF, 0xF0, 0xE5, 0x64, 0x54,
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++0x12, 0x87, 0xFC, 0xC4, 0x13, 0x54, 0x07, 0x90,
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++0xFF, 0x12, 0x7C, 0x3B, 0xAF, 0x64, 0x12, 0x8F,
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++0x75, 0xF0, 0x1B, 0xA4, 0x24, 0x5B, 0xF9, 0x74,
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++0x7F, 0xFF, 0x12, 0x04, 0x7E, 0x90, 0x88, 0x2F,
++0x74, 0x03, 0xF0, 0x22, 0x90, 0x8A, 0xF9, 0x12,
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++0x7E, 0x91, 0x5D, 0x80, 0xE8, 0x90, 0x05, 0x27,
++0xE0, 0x44, 0x40, 0xF0, 0x22, 0x12, 0x97, 0xD5,
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++0xEF, 0x12, 0x8A, 0x65, 0x80, 0x87, 0x7F, 0xFF,
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++0x02, 0xF1, 0x20, 0x90, 0x88, 0x9D, 0xE0, 0x20,
++0xE0, 0x02, 0xB1, 0x3F, 0x22, 0x7E, 0x00, 0x7F,
++0x01, 0x7D, 0x00, 0x7B, 0x01, 0x7A, 0x88, 0x79,
++0x2C, 0x12, 0x04, 0x80, 0x90, 0x88, 0x2C, 0xE0,
++0x54, 0xFD, 0x12, 0xB7, 0x62, 0xA3, 0x74, 0x0C,
++0xF0, 0x22, 0x90, 0x88, 0x36, 0xE0, 0x70, 0x07,
++0x90, 0x88, 0x2C, 0xE0, 0x30, 0xE0, 0x11, 0x90,
++0x88, 0x2C, 0xE0, 0x30, 0xE0, 0x08, 0x12, 0x9E,
++0x4C, 0xBF, 0x01, 0x04, 0x80, 0x03, 0x91, 0xC2,
++0x22, 0x90, 0x88, 0x36, 0xE0, 0x64, 0x02, 0x60,
++0x17, 0xB1, 0x38, 0x60, 0x13, 0x12, 0x7A, 0x65,
++0xEF, 0x70, 0x0D, 0x90, 0x8A, 0xB9, 0x12, 0x90,
++0x45, 0xE4, 0xFD, 0x7F, 0x0C, 0x12, 0x04, 0x7E,
++0x22, 0x90, 0x88, 0x3A, 0xE0, 0x44, 0x01, 0xF0,
++0x90, 0x88, 0x34, 0xE0, 0x54, 0x0F, 0x22, 0x90,
++0x88, 0x36, 0xE0, 0x64, 0x01, 0x70, 0x29, 0xB1,
++0x38, 0x60, 0x16, 0x90, 0x8A, 0xB9, 0x12, 0x90,
++0x45, 0xE4, 0xFD, 0x7F, 0x0C, 0x12, 0x04, 0x7E,
++0x90, 0x8B, 0x01, 0x12, 0xE3, 0x14, 0x02, 0x04,
++0x7A, 0x90, 0x88, 0x39, 0xE0, 0x70, 0x09, 0x90,
++0x8A, 0xB9, 0x12, 0x90, 0x45, 0x12, 0x9F, 0xC6,
++0x22, 0x71, 0xD4, 0x30, 0xE0, 0x0B, 0xEF, 0xC4,
++0x13, 0x13, 0x54, 0x03, 0x30, 0xE0, 0x02, 0xF1,
++0xDE, 0xF1, 0x7C, 0x30, 0xE0, 0x09, 0xEF, 0xF1,
++0x86, 0x54, 0x07, 0x70, 0x3C, 0x80, 0x38, 0xF1,
++0x91, 0x40, 0x34, 0x12, 0x9F, 0xE6, 0x70, 0x31,
++0xB1, 0x38, 0x70, 0x08, 0x90, 0x8A, 0xF5, 0x12,
++0x8A, 0x65, 0x80, 0x26, 0x90, 0x8A, 0xF5, 0x12,
++0x8A, 0x65, 0x90, 0x88, 0x40, 0xE0, 0x04, 0xF0,
++0xE0, 0xD3, 0x94, 0x02, 0x40, 0x09, 0xB1, 0xCA,
++0xE4, 0x90, 0x88, 0x40, 0xF0, 0x80, 0x02, 0xF1,
++0xE5, 0xE4, 0x90, 0x88, 0x3F, 0xF0, 0x22, 0xD1,
++0xAF, 0x22, 0x90, 0x88, 0x32, 0xE0, 0x54, 0xFB,
++0xF0, 0x22, 0x90, 0x06, 0xA9, 0xE0, 0x90, 0x95,
++0xF1, 0xF0, 0xE0, 0xFD, 0x54, 0xC0, 0x70, 0x04,
++0xD1, 0x4B, 0x80, 0x63, 0xED, 0x30, 0xE6, 0x47,
++0x90, 0x88, 0x36, 0xE0, 0x64, 0x02, 0x70, 0x2C,
++0x90, 0x88, 0x31, 0xE0, 0xC3, 0x13, 0x20, 0xE0,
++0x09, 0x90, 0x88, 0x3A, 0xE0, 0x44, 0x01, 0xF0,
++0x80, 0x20, 0xB1, 0x38, 0x64, 0x01, 0x70, 0x29,
++0x90, 0x88, 0x3A, 0xE0, 0x44, 0x04, 0xF0, 0x90,
++0x8A, 0x71, 0x12, 0x90, 0x45, 0x7F, 0x01, 0x12,
++0x04, 0x7E, 0x80, 0x15, 0xB1, 0x31, 0x64, 0x02,
++0x60, 0x08, 0x90, 0x8A, 0xE1, 0x12, 0x8A, 0x65,
++0x80, 0x07, 0x12, 0x73, 0x8F, 0x80, 0x02, 0xD1,
++0x4B, 0x90, 0x95, 0xF1, 0xE0, 0x90, 0x88, 0x3A,
++0x30, 0xE7, 0x0B, 0x12, 0x9D, 0x2D, 0x90, 0x88,
++0x31, 0xE0, 0x44, 0x04, 0xF0, 0x22, 0xE0, 0x54,
++0xFD, 0xF0, 0x22, 0x90, 0x88, 0x3A, 0xE0, 0x54,
++0xFE, 0xF0, 0x22, 0xE4, 0xF5, 0x7C, 0x90, 0x06,
++0xA9, 0xE0, 0xF5, 0x7C, 0x54, 0xC0, 0x70, 0x0F,
++0xD1, 0x4B, 0x54, 0xFD, 0xF0, 0xD1, 0xAF, 0x90,
++0x88, 0x39, 0xE0, 0x60, 0x41, 0xE1, 0x20, 0xE5,
++0x7C, 0x30, 0xE6, 0x21, 0x90, 0x88, 0x36, 0xE0,
++0x64, 0x01, 0x70, 0x1B, 0xB1, 0x31, 0x64, 0x02,
++0x60, 0x0F, 0x90, 0x88, 0x9D, 0xE0, 0x20, 0xE0,
++0x0E, 0x90, 0x8A, 0xE1, 0x12, 0x8A, 0x65, 0x80,
++0x06, 0xF1, 0xE5, 0x80, 0x02, 0xD1, 0x4B, 0xE5,
++0x7C, 0x90, 0x88, 0x3A, 0x30, 0xE7, 0x0B, 0x12,
++0x9D, 0x2D, 0x90, 0x88, 0x31, 0xE0, 0x44, 0x04,
++0xF0, 0x22, 0xE0, 0x54, 0xFD, 0xF0, 0x22, 0x90,
++0x88, 0x2C, 0xE0, 0x90, 0x88, 0x38, 0x30, 0xE0,
++0x05, 0xE0, 0xFF, 0x02, 0xEF, 0x2F, 0x12, 0x97,
++0xA6, 0x7D, 0x01, 0x02, 0x04, 0x7E, 0x90, 0x95,
++0x37, 0xE0, 0xB4, 0x01, 0x1A, 0xE4, 0xF0, 0x90,
++0x01, 0x5B, 0xF0, 0x90, 0x92, 0x20, 0xF0, 0x90,
++0x88, 0x95, 0xE0, 0xC3, 0x13, 0x54, 0x7F, 0x90,
++0x92, 0x21, 0xF0, 0xE4, 0x12, 0x9F, 0xF1, 0x90,
++0x88, 0x31, 0x71, 0xAF, 0x30, 0xE0, 0x30, 0xEF,
++0x54, 0xBF, 0x12, 0xE7, 0xC1, 0x30, 0xE0, 0x06,
++0xE0, 0x44, 0x01, 0xF0, 0x80, 0x0A, 0xE0, 0x54,
++0xFE, 0xF0, 0x12, 0xBF, 0xA3, 0x74, 0x04, 0xF0,
++0x90, 0x88, 0xA3, 0xF1, 0xD7, 0x30, 0xE0, 0x0D,
++0x90, 0x8A, 0xB9, 0x12, 0x90, 0x45, 0x7D, 0x01,
++0x7F, 0x0C, 0x02, 0x04, 0x7E, 0xD1, 0xAF, 0x22,
++0x90, 0x00, 0x02, 0xE0, 0x44, 0x01, 0xF0, 0x22,
++0xE4, 0xFF, 0x12, 0x78, 0x4A, 0xBF, 0x01, 0x0E,
++0x90, 0x88, 0x36, 0xE0, 0x60, 0x08, 0xD1, 0x4B,
++0x54, 0x07, 0x70, 0x02, 0xD1, 0xAF, 0x22, 0x90,
++0x88, 0x36, 0xE0, 0x60, 0x14, 0x90, 0x88, 0x9D,
++0xE0, 0x30, 0xE0, 0x0B, 0x90, 0x95, 0x44, 0xE0,
++0xFF, 0x12, 0xAE, 0x75, 0x20, 0xE0, 0x02, 0xB1,
++0x71, 0x02, 0x98, 0x2E, 0x90, 0x01, 0x57, 0xE0,
++0x60, 0x19, 0xF1, 0xCF, 0xF0, 0xF1, 0x7C, 0x30,
++0xE0, 0x03, 0xEF, 0x80, 0x19, 0xF1, 0x91, 0x40,
++0x0A, 0xE4, 0xFF, 0x12, 0x78, 0x4A, 0xBF, 0x01,
++0x02, 0xB1, 0xCA, 0x22, 0x90, 0x88, 0x31, 0xE0,
++0xFF, 0x13, 0x13, 0x54, 0x3F, 0x22, 0x54, 0xFB,
++0xF0, 0x90, 0x88, 0x3A, 0xE0, 0x54, 0xFD, 0xF0,
++0x22, 0x90, 0x88, 0x3F, 0xE0, 0x04, 0xF0, 0x90,
++0x88, 0x3A, 0xE0, 0x54, 0xEF, 0xF0, 0x90, 0x88,
++0x93, 0xE0, 0xFF, 0x90, 0x88, 0x3F, 0xE0, 0xD3,
++0x9F, 0x22, 0x12, 0x9F, 0xE6, 0x70, 0x1C, 0x90,
++0x88, 0x36, 0xE0, 0x60, 0x16, 0x90, 0x88, 0x3A,
++0xE0, 0x20, 0xE4, 0x0F, 0xF1, 0xCC, 0xF0, 0x90,
++0x88, 0x31, 0xE0, 0xF1, 0x86, 0x54, 0x07, 0x70,
++0x02, 0xD1, 0xAF, 0x22, 0x90, 0x01, 0x57, 0xE4,
++0xF0, 0x90, 0x01, 0x3C, 0x74, 0x02, 0x22, 0xE0,
++0xFF, 0xC4, 0x13, 0x54, 0x07, 0x22, 0x7D, 0x02,
++0x7F, 0x02, 0x02, 0x7C, 0x7E, 0x90, 0x95, 0x37,
++0x74, 0x01, 0xF0, 0x90, 0x06, 0x92, 0x04, 0xF0,
++0x90, 0x01, 0x3C, 0x74, 0x04, 0xF0, 0x90, 0x88,
++0x31, 0xE0, 0x44, 0x08, 0xF0, 0x90, 0x88, 0x39,
++0xE0, 0x64, 0x0C, 0x60, 0x16, 0x90, 0x8A, 0xB9,
++0x12, 0x90, 0x45, 0xE4, 0xFD, 0x7F, 0x0C, 0x12,
++0x04, 0x7E, 0x90, 0x8A, 0xF9, 0x12, 0x90, 0x45,
++0x12, 0x96, 0xDB, 0x90, 0x8A, 0xAF, 0x12, 0x90,
++0x45, 0x7D, 0x08, 0xE4, 0xFF, 0x02, 0x04, 0x7E,
++0x12, 0xA4, 0x7F, 0x90, 0x93, 0xE0, 0xE0, 0x54,
++0xFE, 0xF0, 0x12, 0x87, 0x63, 0xFC, 0x30, 0xE0,
++0x43, 0x90, 0x93, 0xE1, 0xE0, 0x44, 0x01, 0xFE,
++0xF0, 0x12, 0x02, 0x06, 0x54, 0xFE, 0xFD, 0xEE,
++0x54, 0x01, 0x4D, 0x90, 0x93, 0xE1, 0x12, 0x87,
++0x9F, 0x90, 0x93, 0xE2, 0xF0, 0xEC, 0xC3, 0x13,
++0x54, 0x7F, 0xFF, 0xA3, 0x12, 0x87, 0x71, 0xFE,
++0xC3, 0x9F, 0x90, 0x93, 0xE4, 0xF0, 0xA3, 0xEE,
++0xF0, 0xBE, 0x64, 0x04, 0x74, 0x01, 0xF0, 0x22,
++0x90, 0x93, 0xE5, 0xE0, 0x64, 0x96, 0x70, 0x51,
++0x74, 0x03, 0xF0, 0x22, 0x90, 0x93, 0xE1, 0xE0,
++0x54, 0xFE, 0x12, 0xA1, 0x08, 0xFF, 0x54, 0x01,
++0xFE, 0x90, 0x93, 0xD5, 0xE0, 0x54, 0xFE, 0x4E,
++0xFE, 0xF0, 0xEF, 0x54, 0xFE, 0xFF, 0xEE, 0x54,
++0x01, 0x12, 0x87, 0x9E, 0x90, 0x93, 0xD6, 0x12,
++0x87, 0x71, 0x90, 0x93, 0xD7, 0xF0, 0xE4, 0xA3,
++0xF0, 0x90, 0x93, 0xD7, 0xE0, 0xFF, 0xB4, 0x64,
++0x05, 0x74, 0x01, 0xF0, 0x80, 0x0A, 0xEF, 0xB4,
++0x96, 0x06, 0x90, 0x93, 0xD7, 0x74, 0x03, 0xF0,
++0x90, 0x93, 0xD7, 0xE0, 0x04, 0x90, 0x93, 0xDA,
++0xF0, 0x22, 0x31, 0x43, 0x90, 0x93, 0x03, 0xE0,
++0x54, 0xFE, 0x4E, 0xF0, 0x30, 0xE0, 0x30, 0xEF,
++0x54, 0x04, 0x25, 0xE0, 0xFE, 0xE0, 0x54, 0xF7,
++0x4E, 0xFE, 0xF0, 0xEF, 0x54, 0x02, 0x25, 0xE0,
++0xFF, 0xEE, 0x54, 0xFB, 0x4F, 0xF0, 0x90, 0x04,
++0x57, 0xE0, 0x90, 0x93, 0x05, 0xF0, 0x90, 0x04,
++0x55, 0xE0, 0x90, 0x93, 0x04, 0xF0, 0x7D, 0x10,
++0x7F, 0x01, 0x12, 0x7C, 0x05, 0x80, 0x07, 0x7D,
++0x10, 0x7F, 0x01, 0x12, 0x7C, 0x3B, 0x90, 0x93,
++0x03, 0xE0, 0x54, 0x01, 0xFF, 0xEF, 0x90, 0x07,
++0xDC, 0x60, 0x25, 0xE4, 0xF0, 0xF0, 0x90, 0x07,
++0xDE, 0xF0, 0xA3, 0x04, 0xF0, 0x90, 0x07, 0xDD,
++0x74, 0x03, 0xF0, 0x90, 0x07, 0xE3, 0xE0, 0xF0,
++0xA3, 0x74, 0x50, 0xF0, 0xA3, 0x74, 0x10, 0xF0,
++0x90, 0x07, 0xDC, 0xE0, 0x44, 0x01, 0xF0, 0x22,
++0xE4, 0xF0, 0x22, 0x12, 0x02, 0x06, 0xFF, 0x54,
++0x01, 0xFE, 0x22, 0x31, 0x43, 0x90, 0x93, 0x3B,
++0x12, 0xF1, 0x3B, 0x12, 0x87, 0x9E, 0x90, 0x93,
++0x3C, 0x12, 0x87, 0x71, 0x90, 0x93, 0x3D, 0xF0,
++0xB1, 0xB7, 0x90, 0x93, 0x3B, 0xE0, 0x54, 0x01,
++0xFF, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0,
++0xEF, 0x64, 0x01, 0x70, 0x19, 0x31, 0xB5, 0x60,
++0x09, 0x31, 0xAE, 0x12, 0x7C, 0x05, 0xB1, 0xAE,
++0x80, 0x07, 0x31, 0xAE, 0x12, 0x7C, 0x3B, 0xB1,
++0x76, 0x12, 0x79, 0xD4, 0x80, 0x17, 0x31, 0xB5,
++0x60, 0x07, 0x31, 0xAE, 0x12, 0x7C, 0x05, 0x80,
++0x05, 0x31, 0xAE, 0x12, 0x7C, 0x3B, 0xB1, 0x68,
++0xB1, 0x6F, 0x12, 0x7B, 0xCC, 0xD0, 0xD0, 0x92,
++0xAF, 0x22, 0xF0, 0x90, 0x01, 0x3F, 0x74, 0x10,
++0xF0, 0xFD, 0x7F, 0x03, 0x22, 0x90, 0x93, 0x3D,
++0xE0, 0x90, 0x01, 0x3F, 0x22, 0xE4, 0x90, 0x95,
++0xF0, 0xF0, 0x12, 0x9F, 0xE7, 0x60, 0x02, 0x61,
++0x0C, 0x90, 0x88, 0x36, 0xE0, 0x70, 0x02, 0x61,
++0x0C, 0x90, 0x88, 0x2C, 0xE0, 0x20, 0xE0, 0x36,
++0x90, 0x88, 0x9D, 0xE0, 0x20, 0xE0, 0x2F, 0x90,
++0x06, 0xA9, 0xE0, 0x54, 0xC0, 0x70, 0x27, 0x90,
++0x88, 0x9C, 0xE0, 0x70, 0x21, 0x90, 0x04, 0x1A,
++0xE0, 0xF4, 0x70, 0x1A, 0xA3, 0xE0, 0x54, 0x07,
++0xFF, 0xBF, 0x07, 0x12, 0x90, 0x06, 0x62, 0xE0,
++0x54, 0x03, 0x70, 0x0A, 0x90, 0x88, 0x39, 0xE0,
++0xB4, 0x04, 0x03, 0x12, 0xE9, 0x7B, 0x90, 0x05,
++0x63, 0xE0, 0x90, 0x88, 0x85, 0xF0, 0x90, 0x05,
++0x62, 0xE0, 0x90, 0x88, 0x86, 0xF0, 0x90, 0x05,
++0x61, 0xE0, 0x90, 0x88, 0x87, 0xF0, 0x90, 0x05,
++0x60, 0xE0, 0x90, 0x88, 0x88, 0xF0, 0x90, 0x07,
++0xF1, 0xE0, 0x90, 0x95, 0x35, 0xF0, 0x90, 0x07,
++0xF0, 0xE0, 0x90, 0x95, 0x36, 0xF0, 0x12, 0xA7,
++0xCC, 0xF0, 0x90, 0x88, 0x3A, 0xE0, 0x54, 0xEC,
++0xF0, 0x71, 0x28, 0x24, 0xFD, 0x50, 0x02, 0x80,
++0x0F, 0x90, 0x88, 0x2C, 0xE0, 0x30, 0xE0, 0x05,
++0x12, 0xA5, 0xD2, 0x80, 0x03, 0x12, 0xA6, 0x53,
++0x71, 0x28, 0x64, 0x01, 0x70, 0x3A, 0x90, 0x06,
++0xAB, 0xE0, 0x90, 0x88, 0x3D, 0xF0, 0x90, 0x06,
++0xA9, 0xE0, 0x30, 0xE5, 0x06, 0xA3, 0xE0, 0x90,
++0x95, 0xF0, 0xF0, 0x90, 0x95, 0xF0, 0xE0, 0xFF,
++0x60, 0x02, 0x80, 0x05, 0x90, 0x88, 0x3C, 0xE0,
++0xFF, 0x90, 0x88, 0x3C, 0xEF, 0xF0, 0xA3, 0xE0,
++0xFF, 0x70, 0x08, 0x90, 0x88, 0x3C, 0xE0, 0xFE,
++0xFF, 0x80, 0x00, 0x90, 0x88, 0x3D, 0xEF, 0xF0,
++0x71, 0x31, 0xE4, 0x90, 0x88, 0x3F, 0xF0, 0xA3,
++0xF0, 0x12, 0xA3, 0xD4, 0x30, 0xE0, 0x5B, 0xEF,
++0xC4, 0x13, 0x13, 0x54, 0x03, 0x20, 0xE0, 0x23,
++0x71, 0x20, 0x6F, 0x70, 0x4D, 0xEF, 0x60, 0x4A,
++0x90, 0x88, 0x32, 0xE0, 0x44, 0x40, 0xF0, 0xF1,
++0xDD, 0x31, 0xAA, 0x12, 0x7C, 0x05, 0xB1, 0x7D,
++0x12, 0xA7, 0xDE, 0x90, 0x88, 0x3D, 0xE0, 0x14,
++0xF0, 0x80, 0x2F, 0x90, 0x88, 0x34, 0xE0, 0xC4,
++0x54, 0x0F, 0x64, 0x01, 0x70, 0x24, 0x71, 0x20,
++0xFE, 0x6F, 0x60, 0x1E, 0x90, 0x05, 0x73, 0xE0,
++0xFF, 0xEE, 0x6F, 0x60, 0x15, 0x90, 0x88, 0x32,
++0x12, 0xA7, 0x7F, 0x30, 0xE0, 0x0C, 0xEF, 0x54,
++0xBF, 0x31, 0xAA, 0x12, 0x7C, 0x3B, 0xB1, 0x6F,
++0xB1, 0x68, 0x71, 0x18, 0x90, 0x88, 0x2C, 0xE0,
++0xC3, 0x13, 0x20, 0xE0, 0x02, 0x71, 0x18, 0x22,
++0x90, 0x88, 0x32, 0xE0, 0x44, 0x04, 0xF0, 0x22,
++0x90, 0x88, 0x3C, 0xE0, 0xFF, 0xA3, 0xE0, 0x22,
++0x90, 0x88, 0x34, 0xE0, 0xFF, 0xC4, 0x54, 0x0F,
++0x22, 0x90, 0x88, 0x85, 0x12, 0x04, 0xB8, 0xC0,
++0x06, 0xC0, 0x07, 0x90, 0x95, 0x36, 0xE0, 0x24,
++0x46, 0xFF, 0x90, 0x95, 0x35, 0xE0, 0x34, 0x00,
++0xAB, 0x07, 0xFA, 0xE4, 0xF9, 0xF8, 0xD0, 0x07,
++0xD0, 0x06, 0x12, 0x85, 0xB6, 0x90, 0x88, 0x85,
++0xB1, 0x3B, 0xEF, 0x24, 0x46, 0x12, 0xF1, 0x92,
++0x90, 0x88, 0x89, 0xB1, 0x3B, 0x90, 0x88, 0x85,
++0xF1, 0xD6, 0x50, 0x02, 0x81, 0x22, 0x90, 0x88,
++0x89, 0x12, 0x86, 0x2D, 0x90, 0x88, 0x85, 0x12,
++0x04, 0xB8, 0x12, 0x85, 0xB6, 0x90, 0x95, 0xF5,
++0x12, 0x04, 0x31, 0x90, 0x88, 0x31, 0xE0, 0x30,
++0xE0, 0x2F, 0x90, 0x88, 0x53, 0xE0, 0x24, 0x04,
++0xFF, 0xE4, 0x33, 0xFE, 0xEF, 0x78, 0x03, 0xC3,
++0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, 0x24, 0x50,
++0xFF, 0xE4, 0x3E, 0xFE, 0x90, 0x88, 0x4E, 0xE0,
++0xFD, 0xC3, 0xEF, 0x9D, 0xFB, 0xEE, 0x94, 0x00,
++0xFA, 0xB1, 0x44, 0xEB, 0x2F, 0xFF, 0xEA, 0x80,
++0x1E, 0x90, 0x88, 0x33, 0x12, 0xA7, 0x7F, 0x30,
++0xE0, 0x02, 0xA1, 0x20, 0xB1, 0x44, 0x90, 0x88,
++0x4E, 0xE0, 0xFD, 0xC3, 0x74, 0x60, 0x9D, 0xCD,
++0xE4, 0x94, 0x00, 0xCD, 0x2F, 0xFF, 0xED, 0x3E,
++0x90, 0x95, 0xF1, 0xF0, 0xA3, 0xEF, 0xF0, 0xC3,
++0x90, 0x95, 0xF2, 0xE0, 0x94, 0xA0, 0x90, 0x95,
++0xF1, 0xE0, 0x94, 0x00, 0x50, 0x34, 0xA3, 0xE0,
++0xFB, 0x24, 0xF5, 0xB1, 0x33, 0xE0, 0x04, 0xF0,
++0x90, 0x95, 0xF5, 0x12, 0x04, 0xB8, 0xEF, 0x54,
++0x7F, 0xFF, 0x74, 0x95, 0x2B, 0xB1, 0x28, 0xE0,
++0xFE, 0xEF, 0xC3, 0x9E, 0x50, 0x09, 0x90, 0x95,
++0xF1, 0xA3, 0xE0, 0xB1, 0x26, 0xEF, 0xF0, 0x90,
++0x88, 0x4C, 0xE0, 0x04, 0xF0, 0xE0, 0x90, 0x00,
++0xFE, 0xF0, 0x90, 0x88, 0x4C, 0xE0, 0xFF, 0xD3,
++0x90, 0x88, 0x90, 0xE0, 0x9F, 0x90, 0x88, 0x8F,
++0xE0, 0x94, 0x00, 0x40, 0x02, 0xA1, 0x20, 0xE4,
++0xFF, 0xFE, 0xB1, 0x30, 0xE0, 0x2F, 0xFF, 0x90,
++0x88, 0x91, 0xE0, 0xFD, 0xEF, 0xD3, 0x9D, 0x40,
++0x07, 0x90, 0x95, 0xF3, 0xEE, 0xF0, 0x80, 0x05,
++0x0E, 0xEE, 0xB4, 0xA0, 0xE5, 0xB1, 0x4F, 0x40,
++0x02, 0x80, 0x15, 0x90, 0x95, 0xF3, 0xE0, 0x04,
++0xFE, 0xEE, 0xC3, 0x94, 0xA0, 0x50, 0x13, 0xB1,
++0x30, 0xE0, 0x2F, 0xFF, 0xB1, 0x4F, 0x40, 0x07,
++0x90, 0x95, 0xF4, 0xEE, 0xF0, 0x80, 0x03, 0x0E,
++0x80, 0xE7, 0x90, 0x05, 0x5E, 0xE0, 0xFF, 0xB1,
++0x21, 0xE0, 0xFD, 0xEF, 0xC3, 0x9D, 0x40, 0x11,
++0xEF, 0x9D, 0x90, 0x05, 0x5E, 0xF0, 0x90, 0x88,
++0x51, 0xEE, 0xF0, 0x90, 0x95, 0xF4, 0xE0, 0x80,
++0x18, 0xB1, 0x21, 0xE0, 0xFD, 0xC3, 0x74, 0x80,
++0x9D, 0x2F, 0x90, 0x05, 0x5E, 0xF0, 0xEE, 0x04,
++0x90, 0x88, 0x51, 0xF0, 0x90, 0x95, 0xF4, 0xE0,
++0x04, 0x90, 0x88, 0x52, 0xF0, 0x90, 0x88, 0x51,
++0xE0, 0xFF, 0xC3, 0x94, 0x50, 0x40, 0x0A, 0xEF,
++0x24, 0xB0, 0x90, 0x88, 0x49, 0xF0, 0xE4, 0x80,
++0x0E, 0xE4, 0x90, 0x88, 0x49, 0xF0, 0x90, 0x88,
++0x51, 0xE0, 0xFF, 0xC3, 0x74, 0x50, 0x9F, 0x90,
++0x88, 0x48, 0xF0, 0x90, 0x88, 0x51, 0xE0, 0xFF,
++0xA3, 0xE0, 0xC3, 0x9F, 0x90, 0x88, 0x4F, 0xF0,
++0x90, 0x88, 0x31, 0xE0, 0x90, 0x88, 0x8E, 0xE0,
++0x24, 0x08, 0xFF, 0x90, 0x88, 0x4F, 0xE0, 0x2F,
++0xF0, 0x90, 0x88, 0x4F, 0xE0, 0xC3, 0x94, 0x50,
++0x50, 0x03, 0x74, 0x50, 0xF0, 0x90, 0x88, 0x4F,
++0xE0, 0x24, 0x10, 0xF0, 0x12, 0xF1, 0x09, 0x74,
++0x03, 0xF0, 0x12, 0x6E, 0x2F, 0x90, 0x8A, 0xA3,
++0x12, 0x90, 0x45, 0xE4, 0xFF, 0x12, 0x04, 0x7E,
++0x22, 0x90, 0x95, 0xF3, 0xE0, 0xFE, 0x24, 0x95,
++0xF5, 0x82, 0xE4, 0x34, 0x94, 0xF5, 0x83, 0x22,
++0x74, 0xF5, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x93,
++0xF5, 0x83, 0x22, 0x12, 0x04, 0x31, 0x90, 0x88,
++0x89, 0x02, 0x04, 0xB8, 0x90, 0x95, 0xF5, 0x12,
++0x04, 0xB8, 0x78, 0x07, 0x02, 0x03, 0xEB, 0x90,
++0x88, 0x91, 0xE0, 0xFD, 0xC3, 0x90, 0x88, 0x90,
++0xE0, 0x9D, 0xFD, 0x90, 0x88, 0x8F, 0xE0, 0x94,
++0x00, 0xFC, 0xEF, 0xD3, 0x9D, 0xE4, 0x9C, 0x22,
++0x7D, 0x02, 0x7F, 0x02, 0x02, 0x7C, 0x74, 0x7D,
++0x01, 0x7F, 0x02, 0x02, 0x7C, 0x74, 0x7D, 0x02,
++0x7F, 0x02, 0x12, 0x7C, 0x7E, 0x7D, 0x01, 0x7F,
++0x02, 0x02, 0x7C, 0x7E, 0x12, 0x9D, 0xF7, 0xB1,
++0x68, 0x7F, 0x01, 0xB1, 0xED, 0x90, 0x8B, 0x07,
++0x12, 0x8A, 0x65, 0x90, 0x93, 0x3B, 0xE0, 0x30,
++0xE0, 0x13, 0xB1, 0xAE, 0x90, 0x93, 0x3E, 0xE0,
++0x60, 0x05, 0x14, 0xF0, 0x02, 0x79, 0xD4, 0xB1,
++0xB7, 0xE4, 0xFF, 0x31, 0x69, 0x22, 0x90, 0x93,
++0x3D, 0xE0, 0x90, 0x05, 0x73, 0xF0, 0x22, 0x90,
++0x93, 0x3C, 0xE0, 0x14, 0x90, 0x93, 0x3E, 0xF0,
++0x22, 0xE4, 0xFE, 0xB1, 0x30, 0xE4, 0xF0, 0x74,
++0x95, 0x2E, 0xB1, 0x28, 0x74, 0xFF, 0xF0, 0x0E,
++0xEE, 0xB4, 0xA0, 0xEF, 0xE4, 0x90, 0x88, 0x4D,
++0xF0, 0x90, 0x88, 0x4C, 0xF0, 0x90, 0x88, 0x50,
++0xF0, 0xEF, 0xB4, 0x01, 0x07, 0xA3, 0x74, 0xA0,
++0xF0, 0xE4, 0xA3, 0xF0, 0x22, 0xD3, 0x10, 0xAF,
++0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x88, 0x33, 0xE0,
++0xC3, 0x13, 0x30, 0xE0, 0x28, 0x90, 0x96, 0xC8,
++0x74, 0x1E, 0xF0, 0x90, 0x96, 0xEA, 0x74, 0x01,
++0xF0, 0x90, 0x96, 0xCA, 0xEF, 0xF0, 0x7B, 0x01,
++0x7A, 0x96, 0x79, 0xC8, 0x12, 0xB3, 0xE1, 0x12,
++0x04, 0x7E, 0x90, 0x8A, 0xE5, 0x12, 0x90, 0x45,
++0x7F, 0x04, 0x12, 0x04, 0x7E, 0xD0, 0xD0, 0x92,
++0xAF, 0x22, 0x90, 0x88, 0x2C, 0xE0, 0xFF, 0x30,
++0xE0, 0x05, 0x12, 0xA3, 0x95, 0x60, 0x39, 0x90,
++0x88, 0x36, 0xE0, 0x70, 0x04, 0xEF, 0x30, 0xE0,
++0x1B, 0x90, 0x88, 0x39, 0xE0, 0x64, 0x02, 0x60,
++0x27, 0x90, 0x88, 0x9D, 0xE0, 0x30, 0xE0, 0x0A,
++0x90, 0x95, 0x44, 0xE0, 0xFF, 0xD1, 0x75, 0x20,
++0xE0, 0x02, 0x31, 0xBD, 0x90, 0x88, 0x9D, 0xE0,
++0x30, 0xE0, 0x0D, 0x90, 0x95, 0x44, 0xE0, 0xFF,
++0xD1, 0x75, 0x30, 0xE0, 0x03, 0x12, 0xE3, 0x8A,
++0x22, 0x90, 0x95, 0x44, 0xE0, 0xC4, 0x13, 0x13,
++0x13, 0x54, 0x01, 0x22, 0xD3, 0x10, 0xAF, 0x01,
++0xC3, 0xC0, 0xD0, 0x7F, 0x8F, 0x12, 0x7B, 0x41,
++0xEF, 0x20, 0xE6, 0x02, 0xE1, 0xA8, 0x90, 0x00,
++0x8C, 0xE0, 0x90, 0x97, 0x5F, 0xF0, 0x7F, 0x8D,
++0x12, 0x7B, 0x41, 0x90, 0x97, 0x60, 0xEF, 0xF0,
++0x90, 0x00, 0x8E, 0xE0, 0x90, 0x97, 0x61, 0xF0,
++0x90, 0x97, 0x60, 0xE0, 0x24, 0xFC, 0x60, 0x10,
++0x24, 0x03, 0x60, 0x02, 0xE1, 0x98, 0x90, 0x97,
++0x5F, 0xE0, 0xFF, 0x12, 0xEA, 0x85, 0xE1, 0x98,
++0x90, 0x97, 0x5F, 0xE0, 0x24, 0xD6, 0x12, 0xCC,
++0x45, 0xFB, 0xE4, 0xFD, 0xFF, 0xF1, 0xB2, 0x75,
++0xF0, 0x12, 0xF1, 0xBF, 0x13, 0x13, 0x54, 0x03,
++0xFB, 0x0D, 0xE4, 0xFF, 0xF1, 0xB2, 0x75, 0xF0,
++0x12, 0x90, 0x89, 0x52, 0x12, 0x04, 0x6E, 0xD1,
++0x74, 0xFB, 0x0D, 0xE4, 0xFF, 0xF1, 0xB2, 0x75,
++0xF0, 0x12, 0xF1, 0xBF, 0xC4, 0x54, 0x03, 0xFB,
++0x0D, 0xE4, 0xFF, 0xF1, 0xB2, 0x75, 0xF0, 0x12,
++0x12, 0xC5, 0x55, 0xFB, 0xE4, 0xFD, 0x0F, 0xF1,
++0xB2, 0x12, 0xCC, 0x21, 0xF1, 0xAF, 0x75, 0xF0,
++0x12, 0xF1, 0xCC, 0xC4, 0x13, 0x54, 0x01, 0xFB,
++0x0D, 0x7F, 0x01, 0xF1, 0xB2, 0x75, 0xF0, 0x12,
++0xF1, 0xCC, 0x54, 0x1F, 0xF1, 0xB0, 0x12, 0xBF,
++0xCF, 0xE0, 0xFB, 0xE4, 0xFD, 0x0F, 0xF1, 0xB2,
++0x75, 0xF0, 0x08, 0xA4, 0x24, 0x01, 0xF5, 0x82,
++0xE4, 0x34, 0x82, 0xF1, 0xAD, 0x75, 0xF0, 0x08,
++0xA4, 0x24, 0x02, 0xF5, 0x82, 0xE4, 0x34, 0x82,
++0xF1, 0xAD, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x03,
++0xF5, 0x82, 0xE4, 0x34, 0x82, 0xF1, 0xAD, 0x75,
++0xF0, 0x08, 0xA4, 0x24, 0x04, 0xF5, 0x82, 0xE4,
++0x34, 0x82, 0xF5, 0x83, 0xE0, 0xFB, 0xE4, 0xFD,
++0x0F, 0xF1, 0xB2, 0x75, 0xF0, 0x08, 0xA4, 0x24,
++0x05, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0xF1, 0xAD,
++0x75, 0xF0, 0x08, 0xA4, 0x24, 0x06, 0xF5, 0x82,
++0xE4, 0x34, 0x82, 0xF1, 0xAD, 0x75, 0xF0, 0x08,
++0xA4, 0x24, 0x07, 0xF5, 0x82, 0xE4, 0x34, 0x82,
++0xF5, 0x83, 0xE0, 0xFB, 0x0D, 0x12, 0xEA, 0xD9,
++0x7F, 0x8F, 0x12, 0x7B, 0x41, 0xEF, 0x30, 0xE0,
++0x07, 0xE4, 0xFD, 0x7F, 0x8D, 0x12, 0x7B, 0x2E,
++0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xF5, 0x83, 0xE0,
++0xFB, 0x0D, 0x12, 0xEA, 0xD9, 0x90, 0x97, 0x5F,
++0xE0, 0x22, 0xFF, 0x75, 0xF0, 0x12, 0xED, 0x90,
++0x89, 0x52, 0x12, 0x04, 0x6E, 0xE0, 0x22, 0xFF,
++0x75, 0xF0, 0x12, 0xED, 0x90, 0x89, 0x51, 0x12,
++0x04, 0x6E, 0xE0, 0x22, 0xC1, 0x7C, 0x12, 0x86,
++0x2D, 0xC3, 0x02, 0x03, 0xDA, 0x90, 0x88, 0x3C,
++0xE0, 0x90, 0x05, 0x73, 0x22, 0x12, 0x02, 0x06,
++0xFF, 0x90, 0x93, 0x3A, 0xF0, 0xBF, 0x01, 0x07,
++0xF1, 0xF8, 0xE4, 0x90, 0x93, 0x3A, 0xF0, 0x22,
++0x12, 0xB0, 0xA3, 0x7F, 0xEF, 0x7E, 0x01, 0x12,
++0x5F, 0xA6, 0xBF, 0x01, 0x06, 0x90, 0x95, 0x57,
++0xE0, 0xA3, 0xF0, 0x11, 0xA3, 0x7F, 0xEE, 0x7E,
++0x01, 0x12, 0x5F, 0xA6, 0xBF, 0x01, 0x08, 0x90,
++0x95, 0x57, 0xE0, 0x90, 0x95, 0x59, 0xF0, 0x11,
++0xA3, 0x7F, 0xED, 0x7E, 0x01, 0x12, 0x5F, 0xA6,
++0xBF, 0x01, 0x08, 0x90, 0x95, 0x57, 0xE0, 0x90,
++0x95, 0x5A, 0xF0, 0x11, 0xA3, 0x7F, 0xEC, 0x7E,
++0x01, 0x12, 0x5F, 0xA6, 0xBF, 0x01, 0x08, 0x90,
++0x95, 0x57, 0xE0, 0x90, 0x95, 0x5B, 0xF0, 0x11,
++0xA3, 0x7F, 0xEB, 0x7E, 0x01, 0x12, 0x5F, 0xA6,
++0xBF, 0x01, 0x08, 0x90, 0x95, 0x57, 0xE0, 0x90,
++0x95, 0x5C, 0xF0, 0x90, 0x95, 0x58, 0xE0, 0xFF,
++0xA3, 0xE0, 0xFD, 0xA3, 0xE0, 0xFB, 0xA3, 0xE0,
++0x90, 0x95, 0x60, 0xF0, 0x90, 0x95, 0x5C, 0xE0,
++0x90, 0x95, 0x61, 0xF0, 0x90, 0x95, 0x62, 0x74,
++0x12, 0xF0, 0x90, 0x95, 0x84, 0x74, 0x05, 0xF0,
++0x90, 0x95, 0x64, 0xF1, 0x6B, 0x90, 0x95, 0x60,
++0xE0, 0x90, 0x95, 0x67, 0xF0, 0x90, 0x95, 0x61,
++0xE0, 0x90, 0x95, 0x68, 0xF0, 0x7B, 0x01, 0x7A,
++0x95, 0x79, 0x62, 0x12, 0x90, 0x33, 0x7F, 0x04,
++0x02, 0x04, 0x7E, 0x7B, 0x01, 0x7A, 0x95, 0x79,
++0x57, 0x22, 0x7E, 0x00, 0x7F, 0x0B, 0x7D, 0x00,
++0x7B, 0x01, 0x7A, 0x93, 0x79, 0xE7, 0x12, 0x04,
++0x80, 0x11, 0xA3, 0xF1, 0x5B, 0xBF, 0x01, 0x1C,
++0x90, 0x95, 0x57, 0xE0, 0xFE, 0x54, 0x01, 0x90,
++0x93, 0xE7, 0xF0, 0xEE, 0x54, 0x04, 0x90, 0x93,
++0xE9, 0xF0, 0x90, 0x95, 0x57, 0xE0, 0x54, 0x08,
++0x90, 0x93, 0xE8, 0xF0, 0x11, 0xA3, 0x12, 0x97,
++0xB4, 0x64, 0x01, 0x70, 0x35, 0x90, 0x95, 0x57,
++0xE0, 0x54, 0x07, 0x70, 0x15, 0x7B, 0x01, 0x7A,
++0x95, 0x79, 0x58, 0x7F, 0xFA, 0x7E, 0x01, 0x12,
++0x5F, 0xA6, 0xBF, 0x01, 0x0F, 0x90, 0x95, 0x58,
++0x80, 0x03, 0x90, 0x95, 0x57, 0xE0, 0x54, 0x07,
++0x90, 0x93, 0xEB, 0xF0, 0x90, 0x95, 0x57, 0xE0,
++0x54, 0xE0, 0xC4, 0x13, 0x54, 0x07, 0x90, 0x93,
++0xEA, 0xF0, 0x11, 0xA3, 0x7F, 0xFD, 0x7E, 0x01,
++0x12, 0x5F, 0xA6, 0xBF, 0x01, 0x0E, 0x90, 0x95,
++0x57, 0xE0, 0x54, 0x0C, 0x13, 0x13, 0x54, 0x3F,
++0x90, 0x93, 0xEC, 0xF0, 0x22, 0x12, 0x02, 0x06,
++0x90, 0x95, 0x7A, 0x12, 0x87, 0x9F, 0x90, 0x95,
++0x7B, 0xF0, 0x60, 0x0E, 0x31, 0x94, 0x31, 0x9C,
++0x90, 0x95, 0x7B, 0x31, 0x94, 0x7B, 0x57, 0x12,
++0x8F, 0x5D, 0x90, 0x88, 0x9D, 0xE0, 0x30, 0xE0,
++0x0D, 0x12, 0xAE, 0x71, 0x30, 0xE0, 0x07, 0x90,
++0x06, 0x0A, 0xE0, 0x44, 0x07, 0xF0, 0x90, 0x95,
++0x57, 0x74, 0x20, 0xF0, 0x90, 0x95, 0x79, 0x74,
++0x03, 0xF0, 0x90, 0x05, 0x22, 0xE0, 0x90, 0x95,
++0x59, 0xF0, 0x90, 0x93, 0xF3, 0xE0, 0x90, 0x95,
++0x5A, 0xF0, 0x90, 0x93, 0xF4, 0xE0, 0x90, 0x95,
++0x5B, 0xF0, 0x11, 0xA3, 0x12, 0x90, 0x33, 0x7F,
++0x04, 0x02, 0x04, 0x7E, 0xE0, 0xFF, 0x90, 0x95,
++0x7A, 0xE0, 0xFD, 0x22, 0xEF, 0xB4, 0xFF, 0x06,
++0x90, 0x93, 0xF3, 0xED, 0xF0, 0x22, 0xEF, 0xF4,
++0xFE, 0x90, 0x93, 0xF3, 0xE0, 0x5E, 0xFE, 0xED,
++0x5F, 0x4E, 0xF0, 0x22, 0x12, 0x02, 0x06, 0x64,
++0x01, 0x60, 0x02, 0x41, 0x48, 0x90, 0x95, 0x9E,
++0xF0, 0x90, 0x95, 0x9E, 0xE0, 0xFF, 0xC3, 0x94,
++0x10, 0x50, 0x27, 0xEF, 0xF1, 0xD0, 0x7A, 0x95,
++0x79, 0x9D, 0x12, 0x5F, 0xA6, 0xBF, 0x01, 0x12,
++0x90, 0x95, 0x9D, 0xE0, 0xFF, 0xA3, 0xE0, 0x24,
++0x9F, 0xF5, 0x82, 0xE4, 0x34, 0x95, 0xF5, 0x83,
++0xEF, 0xF0, 0x90, 0x95, 0x9E, 0xE0, 0x04, 0xF0,
++0x80, 0xCF, 0x75, 0x45, 0x01, 0x75, 0x46, 0x95,
++0x75, 0x47, 0x9F, 0x75, 0x48, 0x08, 0x7B, 0x01,
++0x7A, 0x95, 0x79, 0x59, 0x12, 0x69, 0xF5, 0x90,
++0x95, 0x57, 0x74, 0x24, 0xF0, 0x90, 0x95, 0x79,
++0x74, 0x08, 0xF0, 0x75, 0x45, 0x01, 0x75, 0x46,
++0x95, 0x75, 0x47, 0xA7, 0xF5, 0x48, 0x7B, 0x01,
++0x7A, 0x95, 0x79, 0x7C, 0x12, 0x69, 0xF5, 0x90,
++0x95, 0x7A, 0x74, 0x25, 0xF0, 0x90, 0x95, 0x9C,
++0x74, 0x08, 0xF0, 0x11, 0xA3, 0x71, 0xE1, 0x12,
++0x04, 0x7E, 0x7B, 0x01, 0x7A, 0x95, 0x79, 0x7A,
++0x12, 0x90, 0x33, 0x7F, 0x04, 0x12, 0x04, 0x7E,
++0x22, 0x12, 0x02, 0x06, 0xFF, 0x12, 0x87, 0xA0,
++0x90, 0x95, 0x57, 0x12, 0x87, 0x71, 0x90, 0x95,
++0x58, 0xF1, 0x77, 0x90, 0x95, 0x59, 0x12, 0x87,
++0xFC, 0x90, 0x95, 0x5A, 0xF0, 0x12, 0x87, 0x63,
++0x90, 0x95, 0x5B, 0x12, 0x87, 0x69, 0x90, 0x95,
++0x5C, 0xF0, 0xEF, 0x24, 0xF9, 0x60, 0x44, 0x14,
++0x70, 0x02, 0x61, 0x19, 0x14, 0x70, 0x02, 0x61,
++0x1B, 0x24, 0xFE, 0x70, 0x02, 0x61, 0x5A, 0x14,
++0x70, 0x02, 0x61, 0x7E, 0x24, 0x06, 0x60, 0x02,
++0x61, 0x8E, 0x90, 0x95, 0x57, 0xE0, 0x90, 0x88,
++0xE1, 0xF0, 0x90, 0x95, 0x58, 0xE0, 0x90, 0x88,
++0xE2, 0xF0, 0x90, 0x95, 0x59, 0xE0, 0x90, 0x88,
++0xE3, 0xF0, 0x90, 0x95, 0x5A, 0xE0, 0x90, 0x88,
++0xE4, 0xF0, 0x90, 0x95, 0x5B, 0xE0, 0x90, 0x88,
++0xE5, 0xF0, 0x22, 0x90, 0x95, 0x57, 0xE0, 0x90,
++0x95, 0x43, 0xF0, 0x90, 0x95, 0x5A, 0x12, 0x8F,
++0xE4, 0x78, 0x10, 0x12, 0x03, 0xFE, 0xC0, 0x04,
++0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x12, 0x8F,
++0xE3, 0x78, 0x18, 0x12, 0x03, 0xFE, 0xD0, 0x03,
++0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x86,
++0x20, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0,
++0x07, 0x90, 0x95, 0x59, 0x12, 0x8F, 0xE4, 0x78,
++0x08, 0x12, 0x03, 0xFE, 0xD0, 0x03, 0xD0, 0x02,
++0xD0, 0x01, 0xD0, 0x00, 0x12, 0x86, 0x20, 0x12,
++0x9D, 0x14, 0x90, 0x95, 0x58, 0x12, 0x8F, 0xE4,
++0x12, 0x86, 0x20, 0x90, 0x95, 0x39, 0x02, 0x04,
++0x31, 0x61, 0xA5, 0x90, 0x95, 0x45, 0xE0, 0x44,
++0x01, 0xFF, 0xF0, 0x90, 0x95, 0x57, 0xE0, 0x54,
++0x7F, 0x25, 0xE0, 0xFE, 0xEF, 0x54, 0x01, 0x4E,
++0x90, 0x95, 0x45, 0xF0, 0xE0, 0xFF, 0xC3, 0x13,
++0x54, 0x7F, 0xC3, 0x94, 0x1E, 0x50, 0x06, 0xEF,
++0x54, 0x01, 0x44, 0x3C, 0xF0, 0x90, 0x95, 0x45,
++0xE0, 0xFF, 0xC3, 0x13, 0x54, 0x7F, 0xD3, 0x94,
++0x50, 0x40, 0x51, 0xEF, 0x54, 0x01, 0x44, 0xA0,
++0xF0, 0x22, 0x90, 0x95, 0x57, 0xE0, 0xFF, 0x54,
++0xC0, 0xC4, 0x13, 0x13, 0x54, 0x03, 0xFE, 0x90,
++0x95, 0x50, 0xE0, 0x54, 0xFC, 0x4E, 0xFE, 0xF0,
++0xEF, 0x54, 0x3F, 0x25, 0xE0, 0x25, 0xE0, 0xFF,
++0xEE, 0x54, 0x03, 0x4F, 0xF0, 0x22, 0x90, 0x95,
++0x57, 0xE0, 0x54, 0x01, 0xFF, 0x90, 0x95, 0x4C,
++0xE0, 0x54, 0xFE, 0x4F, 0xF0, 0x22, 0x7E, 0x01,
++0x7F, 0xFF, 0xAD, 0x06, 0x11, 0xA3, 0x90, 0x8A,
++0xCF, 0xE0, 0xF8, 0xA3, 0xE0, 0xF5, 0x82, 0x88,
++0x83, 0x12, 0x04, 0x7E, 0x22, 0x90, 0x95, 0x5D,
++0x74, 0x27, 0xF0, 0x90, 0x95, 0x7F, 0x74, 0x08,
++0xF0, 0x90, 0x95, 0x5F, 0xF1, 0x62, 0x90, 0x95,
++0x4A, 0xE0, 0x90, 0x95, 0x63, 0xF0, 0x90, 0x95,
++0x4B, 0xE0, 0x90, 0x95, 0x64, 0xF0, 0x90, 0x95,
++0x4E, 0xE0, 0x90, 0x95, 0x65, 0xF0, 0x90, 0x95,
++0x4F, 0xE0, 0x90, 0x95, 0x66, 0xF0, 0x7B, 0x01,
++0x7A, 0x95, 0x79, 0x5D, 0x71, 0xE1, 0x02, 0x04,
++0x7E, 0x90, 0x8A, 0x77, 0xE0, 0xFE, 0xA3, 0xE0,
++0xFF, 0xF5, 0x82, 0x8E, 0x83, 0x22, 0x90, 0x95,
++0xF0, 0xEF, 0xF0, 0x90, 0x04, 0x7E, 0xE0, 0xFF,
++0xA3, 0xE0, 0x90, 0x96, 0x14, 0xF0, 0xE0, 0xFE,
++0x6F, 0x60, 0x70, 0x90, 0x95, 0xF1, 0x74, 0x03,
++0xF0, 0x90, 0x96, 0x13, 0x74, 0x08, 0xF0, 0xEE,
++0x04, 0x54, 0x0F, 0xFF, 0xE4, 0xFE, 0xEF, 0x75,
++0xF0, 0x08, 0xA4, 0x24, 0x00, 0xF5, 0x82, 0xE4,
++0x34, 0x80, 0xF5, 0x83, 0xE5, 0x82, 0x2E, 0x91,
++0x7A, 0xE0, 0xFD, 0x74, 0xF3, 0x2E, 0xF5, 0x82,
++0xE4, 0x34, 0x95, 0xF5, 0x83, 0xED, 0xF0, 0x0E,
++0xEE, 0xB4, 0x08, 0xDA, 0x7B, 0x01, 0x7A, 0x95,
++0x79, 0xF1, 0x71, 0xE1, 0x12, 0x04, 0x7E, 0x90,
++0x96, 0x14, 0xE0, 0x04, 0x54, 0x0F, 0xFF, 0xF0,
++0xBF, 0x0F, 0x02, 0xE4, 0xF0, 0x90, 0x96, 0x14,
++0xE0, 0x90, 0x04, 0x7F, 0xF0, 0x90, 0x95, 0xF0,
++0xE0, 0x70, 0x05, 0x90, 0x8A, 0xE5, 0x80, 0x03,
++0x90, 0x8A, 0x79, 0x12, 0x90, 0x45, 0x7F, 0x04,
++0x12, 0x04, 0x7E, 0x22, 0x12, 0x04, 0x6E, 0xE5,
++0x82, 0x2C, 0xF5, 0x82, 0xE4, 0x35, 0x83, 0xF5,
++0x83, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0,
++0xD0, 0x90, 0x01, 0xCC, 0xE0, 0x54, 0x0F, 0xFD,
++0xED, 0x70, 0x02, 0xA1, 0x6D, 0x90, 0x87, 0x0B,
++0xE0, 0xFF, 0x70, 0x06, 0xA3, 0xE0, 0x64, 0x09,
++0x60, 0x0A, 0xEF, 0x14, 0xFF, 0x90, 0x87, 0x0C,
++0xE0, 0xB5, 0x07, 0x04, 0x7F, 0x01, 0x80, 0x02,
++0x7F, 0x00, 0xEF, 0x60, 0x09, 0x90, 0x01, 0xC1,
++0xE0, 0x44, 0x01, 0xF0, 0xA1, 0x6D, 0x90, 0x97,
++0x71, 0xE0, 0x12, 0xBF, 0xB9, 0x80, 0x05, 0xC3,
++0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, 0xFF, 0xED,
++0xFB, 0xEF, 0x5B, 0x60, 0x7B, 0xE4, 0xFC, 0xB1,
++0x73, 0xA4, 0xFF, 0xEC, 0x7A, 0x00, 0x2F, 0xFF,
++0xEA, 0x35, 0xF0, 0xFE, 0x74, 0xD0, 0xB1, 0x86,
++0x90, 0x87, 0x0C, 0xE0, 0xF9, 0x75, 0xF0, 0x08,
++0x90, 0x86, 0xBB, 0x91, 0x74, 0xEF, 0xB1, 0x72,
++0xA4, 0xFF, 0xEC, 0x2F, 0xFF, 0xEA, 0x35, 0xF0,
++0xFE, 0x74, 0xF0, 0xB1, 0x86, 0x75, 0xF0, 0x08,
++0xE9, 0x90, 0x86, 0xBF, 0x91, 0x74, 0xEF, 0xF0,
++0x0C, 0xEC, 0xB4, 0x04, 0xC2, 0xB1, 0x7B, 0x80,
++0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4, 0x5D, 0xFD,
++0xB1, 0x7B, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC,
++0x90, 0x01, 0xCC, 0xF0, 0x90, 0x97, 0x71, 0xE0,
++0x04, 0xF0, 0xE0, 0x54, 0x03, 0xF0, 0x90, 0x87,
++0x0C, 0xE0, 0x04, 0xF0, 0xE0, 0x7F, 0x00, 0xB4,
++0x0A, 0x02, 0x7F, 0x01, 0xEF, 0x70, 0x02, 0x81,
++0x90, 0xE4, 0x90, 0x87, 0x0C, 0xF0, 0x81, 0x90,
++0x90, 0x01, 0xC0, 0xE0, 0x44, 0x02, 0xF0, 0x90,
++0x97, 0x71, 0xE0, 0x44, 0x80, 0x90, 0x00, 0x8A,
++0xB1, 0x72, 0x90, 0x01, 0xD0, 0x12, 0x04, 0x6E,
++0xE0, 0x90, 0x01, 0xC3, 0xF0, 0xD0, 0xD0, 0x92,
++0xAF, 0x22, 0xF0, 0x90, 0x97, 0x71, 0xE0, 0x75,
++0xF0, 0x04, 0x22, 0x90, 0x97, 0x71, 0xE0, 0xFF,
++0x74, 0x01, 0xA8, 0x07, 0x08, 0x22, 0x2F, 0xF5,
++0x82, 0x74, 0x01, 0x3E, 0xF5, 0x83, 0xE0, 0xFF,
++0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0,
++0x90, 0x96, 0xEB, 0xEF, 0xF0, 0x90, 0x88, 0x2B,
++0xE0, 0x90, 0x96, 0xFD, 0xF0, 0xE4, 0x90, 0x96,
++0xEC, 0xF0, 0x90, 0x96, 0xFD, 0xE0, 0xFE, 0x90,
++0x96, 0xEC, 0xE0, 0xFF, 0xC3, 0x9E, 0x50, 0x2B,
++0xE0, 0xFE, 0xD1, 0xB0, 0xE4, 0xF0, 0xEE, 0xD1,
++0xE7, 0xE0, 0x30, 0xE7, 0x0A, 0x75, 0xF0, 0x12,
++0xEF, 0xD1, 0xBA, 0xE4, 0xF0, 0x80, 0x0C, 0x12,
++0x7C, 0x8F, 0x90, 0x96, 0xEC, 0xE0, 0xD1, 0xB0,
++0x74, 0x01, 0xF0, 0x90, 0x96, 0xEC, 0xE0, 0x04,
++0xF0, 0x80, 0xC7, 0x7F, 0x0C, 0x7E, 0x00, 0x12,
++0x7C, 0x6A, 0xE4, 0x90, 0x96, 0xEC, 0xF0, 0x90,
++0x96, 0xFD, 0xE0, 0xFF, 0x90, 0x96, 0xEC, 0xE0,
++0xFE, 0xC3, 0x9F, 0x40, 0x02, 0xC1, 0xAB, 0x74,
++0xED, 0x2E, 0xD1, 0xB2, 0xE0, 0x70, 0x02, 0xC1,
++0xA3, 0xEE, 0xC4, 0x54, 0xF0, 0x24, 0x06, 0xF5,
++0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFD,
++0xEE, 0xC4, 0x54, 0xF0, 0x24, 0x07, 0xF5, 0x82,
++0xE4, 0x34, 0x81, 0xF5, 0x83, 0xD1, 0xC0, 0xFC,
++0x75, 0xF0, 0x12, 0x90, 0x89, 0x53, 0xD1, 0xC9,
++0xEC, 0xC4, 0x54, 0xF0, 0x24, 0x0A, 0xF5, 0x82,
++0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFD, 0xEC,
++0xD1, 0xD2, 0xD1, 0xC0, 0x75, 0xF0, 0x12, 0x90,
++0x89, 0x57, 0xD1, 0xC9, 0x7F, 0x01, 0x90, 0x96,
++0xEC, 0xE0, 0xFE, 0xD1, 0xD2, 0xE5, 0x82, 0x2F,
++0x91, 0x7A, 0xE0, 0xFD, 0x75, 0xF0, 0x12, 0xEE,
++0x90, 0x89, 0x57, 0x12, 0x04, 0x6E, 0x75, 0xF0,
++0x02, 0xEF, 0xD1, 0xDF, 0xED, 0xF0, 0x0F, 0xEF,
++0xB4, 0x05, 0xDB, 0x90, 0x96, 0xEC, 0xE0, 0xFF,
++0xC4, 0x54, 0xF0, 0x24, 0x09, 0xF5, 0x82, 0xE4,
++0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFE, 0xF1, 0x49,
++0xEE, 0xF0, 0x90, 0x96, 0xEC, 0xE0, 0xFF, 0x90,
++0x96, 0xEB, 0xE0, 0xFD, 0x12, 0x61, 0xF7, 0x90,
++0x96, 0xEC, 0xE0, 0x75, 0xF0, 0x12, 0xD1, 0xBA,
++0x74, 0x01, 0xF0, 0x90, 0x96, 0xEC, 0xE0, 0x04,
++0xF0, 0xA1, 0xEF, 0xD0, 0xD0, 0x92, 0xAF, 0x22,
++0x24, 0xED, 0xF5, 0x82, 0xE4, 0x34, 0x96, 0xF5,
++0x83, 0x22, 0x90, 0x89, 0x56, 0x02, 0x04, 0x6E,
++0xE0, 0xFE, 0xED, 0xFF, 0x90, 0x96, 0xEC, 0xE0,
++0x22, 0x12, 0x04, 0x6E, 0xEE, 0xF0, 0xA3, 0xEF,
++0xF0, 0x22, 0xC4, 0x54, 0xF0, 0x24, 0x0B, 0xF5,
++0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0x22, 0x12,
++0x04, 0x6E, 0xE4, 0xF0, 0xA3, 0x22, 0xEF, 0xC4,
++0x54, 0xF0, 0x24, 0x03, 0xF5, 0x82, 0xE4, 0x34,
++0x81, 0xF5, 0x83, 0x22, 0x7D, 0x07, 0xAF, 0x67,
++0xED, 0x30, 0xE0, 0x1E, 0x75, 0xF0, 0x12, 0xEF,
++0x90, 0x89, 0x57, 0xF1, 0x3D, 0x90, 0x89, 0x59,
++0xF1, 0x3D, 0x90, 0x89, 0x5B, 0xF1, 0x3D, 0x90,
++0x89, 0x5D, 0xF1, 0x3D, 0x90, 0x89, 0x5F, 0xD1,
++0xDF, 0xF0, 0xED, 0x30, 0xE1, 0x0A, 0x75, 0xF0,
++0x12, 0xEF, 0x90, 0x89, 0x53, 0xD1, 0xDF, 0xF0,
++0xED, 0x30, 0xE2, 0x04, 0xF1, 0x49, 0xE4, 0xF0,
++0xD1, 0xE6, 0xE0, 0x54, 0xBF, 0x44, 0x80, 0xFE,
++0xD1, 0xE6, 0xEE, 0xF0, 0x22, 0x12, 0x04, 0x6E,
++0xE4, 0xF0, 0xA3, 0xF0, 0x75, 0xF0, 0x12, 0xEF,
++0x22, 0x75, 0xF0, 0x12, 0xEF, 0x90, 0x89, 0x55,
++0x02, 0x04, 0x6E, 0xE4, 0xFF, 0x61, 0xEE, 0xE4,
++0xFF, 0xA1, 0x91, 0x7F, 0xF9, 0x7E, 0x01, 0x02,
++0x5F, 0xA6, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xF0,
++0xA3, 0xF0, 0x22, 0xEF, 0xF0, 0xA3, 0xED, 0xF0,
++0xA3, 0xEB, 0xF0, 0x22, 0xF5, 0x83, 0xEF, 0xF0,
++0x90, 0x00, 0x03, 0x02, 0x02, 0x1F, 0x12, 0x02,
++0x06, 0xFE, 0x12, 0x87, 0x72, 0xFF, 0x74, 0xD6,
++0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x8D, 0xF1, 0x74,
++0xFF, 0xF1, 0xBF, 0x12, 0x87, 0xF9, 0xFF, 0x74,
++0x56, 0x2E, 0xF1, 0xC8, 0xEF, 0xF0, 0xF1, 0xBF,
++0xF5, 0x83, 0xE0, 0x30, 0xE5, 0x18, 0x75, 0xF0,
++0x12, 0xEE, 0x12, 0xAF, 0xBF, 0x13, 0x13, 0x54,
++0x03, 0xFB, 0xAF, 0x06, 0x74, 0xD6, 0x2E, 0x12,
++0xCC, 0x45, 0xFD, 0x12, 0x6B, 0xFD, 0x22, 0x74,
++0xC6, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x8D, 0x22,
++0xF5, 0x82, 0xE4, 0x34, 0x96, 0xF5, 0x83, 0x22,
++0x24, 0xA8, 0xFF, 0xE4, 0x34, 0x01, 0xFE, 0x7B,
++0x01, 0x22, 0x12, 0x02, 0x06, 0x54, 0x01, 0xFF,
++0x90, 0x93, 0xF2, 0xE0, 0x54, 0xFE, 0x4F, 0xF0,
++0x22, 0x12, 0xB8, 0x87, 0xFF, 0x54, 0x7F, 0x90,
++0x88, 0x36, 0xF0, 0xEF, 0x12, 0xAE, 0x75, 0xA3,
++0x12, 0x87, 0x9F, 0xFD, 0x54, 0xF0, 0xC4, 0x54,
++0x0F, 0xFF, 0x90, 0x88, 0x34, 0xE0, 0x54, 0xF0,
++0x4F, 0x12, 0xB7, 0x77, 0xFC, 0x54, 0x01, 0x25,
++0xE0, 0xFF, 0x90, 0x88, 0x31, 0xE0, 0x54, 0xFD,
++0x4F, 0xF0, 0xEC, 0x54, 0x04, 0xC3, 0x13, 0xFF,
++0x90, 0x88, 0x33, 0xE0, 0x54, 0xFD, 0x4F, 0xF0,
++0xED, 0x54, 0x0F, 0xC4, 0x54, 0xF0, 0xFF, 0xA3,
++0xE0, 0x54, 0x0F, 0x12, 0x87, 0x70, 0x90, 0x88,
++0x35, 0x12, 0x87, 0xFC, 0xFD, 0x90, 0x8A, 0x89,
++0x12, 0x90, 0x45, 0x7F, 0x02, 0x11, 0x7F, 0x54,
++0xFE, 0xF0, 0x54, 0xFD, 0xF0, 0x54, 0xFB, 0xF0,
++0x54, 0xF7, 0xF0, 0x54, 0xEF, 0xF0, 0x54, 0xDF,
++0xF0, 0x54, 0xBF, 0x12, 0x87, 0xF3, 0x12, 0x5C,
++0x5F, 0x90, 0x88, 0x36, 0xE0, 0xB4, 0x01, 0x07,
++0x90, 0x88, 0x33, 0xE0, 0x54, 0xFB, 0xF0, 0xF1,
++0xA3, 0xF0, 0x90, 0x88, 0x36, 0xF1, 0xC2, 0x12,
++0xA5, 0x37, 0x90, 0x01, 0xBE, 0xF0, 0x22, 0x12,
++0x04, 0x7E, 0x90, 0x88, 0x9B, 0xE0, 0x22, 0x90,
++0x95, 0x57, 0x12, 0x86, 0x42, 0x02, 0x02, 0x06,
++0xEF, 0x70, 0x05, 0x90, 0x93, 0x05, 0x80, 0x03,
++0x90, 0x93, 0x04, 0xE0, 0xFF, 0x12, 0x7B, 0x07,
++0x90, 0x95, 0xF0, 0xEF, 0xF0, 0x90, 0x95, 0xF0,
++0xE0, 0x24, 0x38, 0xF9, 0xE4, 0x34, 0xFC, 0xFA,
++0x7B, 0x01, 0xA3, 0x12, 0x86, 0x42, 0xE4, 0xFF,
++0x74, 0x08, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x07,
++0xF5, 0x83, 0xE0, 0xFE, 0x90, 0x95, 0xF1, 0x12,
++0x86, 0x39, 0x8F, 0x82, 0x75, 0x83, 0x00, 0x31,
++0x4F, 0xB4, 0x06, 0xE4, 0x90, 0x95, 0xF0, 0xE0,
++0x24, 0x52, 0xF9, 0xE4, 0x34, 0xFC, 0xFA, 0x7B,
++0x01, 0xA3, 0x11, 0x8A, 0x70, 0x68, 0x90, 0x95,
++0xF1, 0x12, 0x86, 0x39, 0x12, 0x87, 0xA0, 0x64,
++0x02, 0x70, 0x5B, 0x90, 0x24, 0x87, 0xE0, 0x90,
++0x00, 0x03, 0x12, 0x02, 0x5E, 0x90, 0x24, 0x86,
++0xE0, 0x90, 0x00, 0x04, 0x12, 0x02, 0x5E, 0x90,
++0x95, 0xF1, 0x12, 0x86, 0x39, 0x12, 0x87, 0x63,
++0x64, 0x01, 0x70, 0x3A, 0x12, 0x87, 0x6A, 0x64,
++0x0D, 0x70, 0x33, 0xFF, 0x74, 0x88, 0x31, 0x60,
++0xEF, 0x24, 0x08, 0x31, 0x56, 0x31, 0x78, 0x31,
++0x4F, 0xB4, 0x08, 0xF0, 0x90, 0x05, 0xDC, 0xE0,
++0xFF, 0x90, 0x95, 0xF1, 0x12, 0x86, 0x39, 0x90,
++0x00, 0x10, 0xEF, 0x12, 0x02, 0x5E, 0xE4, 0xFF,
++0x31, 0x5E, 0xEF, 0x24, 0x11, 0x31, 0x56, 0x31,
++0x78, 0x31, 0x4F, 0xB4, 0x04, 0xF2, 0x22, 0xEE,
++0x12, 0x02, 0x5E, 0x0F, 0xEF, 0x22, 0xFD, 0xE4,
++0x33, 0xFC, 0x90, 0x95, 0xF1, 0x22, 0x74, 0x90,
++0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x24, 0xF5, 0x83,
++0xE0, 0xFE, 0x22, 0x7E, 0x00, 0xC3, 0x74, 0x07,
++0x9F, 0xFD, 0xE4, 0x9E, 0xFC, 0x90, 0x96, 0x19,
++0x12, 0x86, 0x39, 0x8D, 0x82, 0x8C, 0x83, 0x22,
++0x91, 0x1C, 0x90, 0x96, 0x1C, 0xF0, 0x90, 0x96,
++0x1C, 0xE0, 0xFF, 0xC3, 0x94, 0x08, 0x50, 0x27,
++0x31, 0x6B, 0x91, 0x54, 0x51, 0xEB, 0xC3, 0x9D,
++0x50, 0x03, 0x7F, 0x00, 0x22, 0x90, 0x96, 0x1C,
++0xE0, 0xFF, 0x31, 0x6B, 0x91, 0x54, 0x51, 0xEB,
++0xD3, 0x9D, 0x40, 0x03, 0x7F, 0x01, 0x22, 0x90,
++0x96, 0x1C, 0xE0, 0x04, 0xF0, 0x80, 0xCF, 0x7F,
++0x00, 0x22, 0xE4, 0x90, 0x96, 0x15, 0xF0, 0x90,
++0x93, 0x03, 0xE0, 0xFF, 0xC3, 0x13, 0x20, 0xE0,
++0x70, 0x51, 0x73, 0x31, 0x80, 0xEF, 0x60, 0x0D,
++0x7B, 0x01, 0x7A, 0x93, 0x79, 0x13, 0x51, 0x79,
++0x51, 0x84, 0xEF, 0x60, 0x54, 0x51, 0x73, 0x31,
++0x80, 0xEF, 0x60, 0x17, 0x7B, 0x01, 0x7A, 0x93,
++0x79, 0x13, 0x51, 0x79, 0x51, 0x84, 0xEF, 0x60,
++0x0A, 0x7B, 0x01, 0x7A, 0x93, 0x79, 0x1C, 0x91,
++0x0E, 0x70, 0x36, 0x7B, 0x01, 0x7A, 0x93, 0x79,
++0x20, 0x90, 0x96, 0x19, 0x12, 0x86, 0x42, 0x7A,
++0x93, 0x79, 0x06, 0x31, 0x80, 0xEF, 0x60, 0x10,
++0x51, 0x97, 0x51, 0x79, 0x31, 0x80, 0xEF, 0x60,
++0x07, 0x51, 0x73, 0x91, 0x24, 0xEF, 0x70, 0x11,
++0x51, 0x73, 0x51, 0x84, 0xEF, 0x60, 0x29, 0x7B,
++0x01, 0x7A, 0x93, 0x79, 0x0F, 0x91, 0x0E, 0x60,
++0x1F, 0x90, 0x96, 0x15, 0x74, 0x01, 0xF0, 0x80,
++0x17, 0x51, 0x97, 0x51, 0x79, 0x31, 0x80, 0xEF,
++0x60, 0x0E, 0x51, 0x97, 0x51, 0x79, 0x91, 0x24,
++0xEF, 0x70, 0x05, 0x90, 0x96, 0x15, 0x04, 0xF0,
++0x90, 0x96, 0x15, 0xE0, 0xFF, 0x90, 0x05, 0x18,
++0xE4, 0xF0, 0xA3, 0xF0, 0xEF, 0x90, 0x05, 0xB3,
++0x60, 0x0C, 0xE0, 0x44, 0x80, 0xF0, 0x90, 0x24,
++0xA0, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0xE0, 0x44,
++0x20, 0xF0, 0x22, 0x7B, 0x01, 0x7A, 0x93, 0x79,
++0x06, 0x90, 0x96, 0x19, 0x12, 0x86, 0x42, 0x7A,
++0x93, 0x79, 0x20, 0x22, 0x91, 0x1C, 0xFF, 0x91,
++0x37, 0x6E, 0x60, 0x03, 0x7F, 0x00, 0x22, 0x0F,
++0xEF, 0xB4, 0x08, 0xF3, 0x7F, 0x01, 0x22, 0x7B,
++0x01, 0x7A, 0x93, 0x79, 0x2D, 0x22, 0x91, 0x1C,
++0x90, 0x96, 0x1C, 0xF0, 0x90, 0x96, 0x1C, 0xE0,
++0xFF, 0xC3, 0x94, 0x04, 0x50, 0x1F, 0x51, 0xD0,
++0xC3, 0x9D, 0x50, 0x03, 0x7F, 0x00, 0x22, 0x90,
++0x96, 0x1C, 0xE0, 0xFF, 0x51, 0xD0, 0xD3, 0x9D,
++0x40, 0x03, 0x7F, 0x01, 0x22, 0x90, 0x96, 0x1C,
++0xE0, 0x04, 0xF0, 0x80, 0xD7, 0x7F, 0x00, 0x22,
++0x7E, 0x00, 0xC3, 0x74, 0x03, 0x9F, 0xFD, 0xE4,
++0x9E, 0xFC, 0x90, 0x96, 0x19, 0x12, 0x86, 0x39,
++0x8D, 0x82, 0x8C, 0x83, 0x12, 0x02, 0x1F, 0xFD,
++0xC3, 0x74, 0x03, 0x9F, 0xFF, 0xE4, 0x9E, 0xFE,
++0x90, 0x96, 0x16, 0x12, 0x86, 0x39, 0x8F, 0x82,
++0x8E, 0x83, 0x02, 0x02, 0x1F, 0xE4, 0x90, 0x96,
++0x19, 0xF0, 0xEF, 0x75, 0xF0, 0x40, 0xA4, 0x24,
++0x80, 0xF9, 0x74, 0x82, 0x35, 0xF0, 0xFA, 0x7B,
++0x01, 0x90, 0x96, 0x15, 0x11, 0x8A, 0x90, 0x96,
++0x18, 0xF0, 0xA3, 0x74, 0x1C, 0xF0, 0x90, 0x96,
++0x18, 0xE0, 0xFF, 0xA3, 0xE0, 0xFE, 0xC3, 0x9F,
++0x40, 0x02, 0x81, 0x02, 0x90, 0x96, 0x15, 0x12,
++0x86, 0x39, 0x8E, 0x82, 0x91, 0x4E, 0x90, 0x96,
++0x1A, 0xF0, 0xEE, 0xFD, 0x7C, 0x00, 0xF5, 0x82,
++0x8C, 0x83, 0xA3, 0xA3, 0x12, 0x02, 0x1F, 0xFE,
++0x8D, 0x82, 0x8C, 0x83, 0xA3, 0x12, 0x02, 0x1F,
++0xFD, 0xED, 0xFF, 0x90, 0x96, 0x1B, 0xEE, 0xF0,
++0xA3, 0xEF, 0xF0, 0x90, 0x96, 0x1A, 0xE0, 0x64,
++0x01, 0x60, 0x0E, 0xA3, 0xA3, 0xE0, 0x24, 0x03,
++0xFF, 0x90, 0x96, 0x19, 0xE0, 0x2F, 0xF0, 0x80,
++0xAD, 0xE4, 0x90, 0x96, 0x1D, 0xF0, 0x90, 0x96,
++0x1D, 0xE0, 0xFF, 0xC3, 0x94, 0x08, 0x50, 0x1A,
++0x90, 0x96, 0x19, 0xE0, 0x24, 0x03, 0x91, 0x5C,
++0x51, 0xF3, 0xFF, 0x90, 0x96, 0x1D, 0xE0, 0x24,
++0x20, 0xF5, 0x82, 0xE4, 0x34, 0x93, 0x91, 0x03,
++0x80, 0xDC, 0x90, 0x96, 0x19, 0xE0, 0x24, 0x0B,
++0xFF, 0xE4, 0x33, 0xFE, 0x90, 0x96, 0x15, 0x51,
++0xF3, 0x90, 0x93, 0x28, 0xF0, 0x70, 0x2A, 0x90,
++0x96, 0x1D, 0xF0, 0x90, 0x96, 0x1D, 0xE0, 0xFF,
++0x24, 0x10, 0xFD, 0xE4, 0x33, 0xFC, 0x90, 0x96,
++0x15, 0x31, 0x78, 0x12, 0x02, 0x1F, 0xFE, 0x74,
++0x29, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x93, 0xF5,
++0x83, 0xEE, 0x91, 0x06, 0xE0, 0xB4, 0x04, 0xDB,
++0x22, 0xE4, 0x90, 0x96, 0x1D, 0xF0, 0x90, 0x96,
++0x1D, 0xE0, 0xFF, 0xC3, 0x94, 0x04, 0x50, 0x1A,
++0x90, 0x96, 0x19, 0xE0, 0x24, 0x0C, 0x91, 0x5C,
++0x51, 0xF3, 0xFF, 0x90, 0x96, 0x1D, 0xE0, 0x24,
++0x29, 0xF5, 0x82, 0xE4, 0x34, 0x93, 0x91, 0x03,
++0x80, 0xDC, 0x22, 0xF5, 0x83, 0xEF, 0xF0, 0x90,
++0x96, 0x1D, 0xE0, 0x04, 0xF0, 0x22, 0x90, 0x96,
++0x19, 0x12, 0x86, 0x42, 0x7A, 0x93, 0x79, 0x29,
++0x51, 0x9E, 0xEF, 0x22, 0x90, 0x96, 0x16, 0x12,
++0x86, 0x42, 0xE4, 0x22, 0x91, 0x1C, 0xFF, 0x91,
++0x37, 0x6E, 0x60, 0x03, 0x7F, 0x00, 0x22, 0x0F,
++0xEF, 0xB4, 0x06, 0xF3, 0x7F, 0x01, 0x22, 0x90,
++0x96, 0x19, 0x12, 0x86, 0x39, 0x8F, 0x82, 0x75,
++0x83, 0x00, 0x12, 0x02, 0x1F, 0xFE, 0x90, 0x96,
++0x16, 0x12, 0x86, 0x39, 0x8F, 0x82, 0x75, 0x83,
++0x00, 0x02, 0x02, 0x1F, 0x12, 0x02, 0x1F, 0xFD,
++0xC3, 0x74, 0x07, 0x22, 0xFD, 0xE4, 0x33, 0xFC,
++0x7E, 0x00, 0xED, 0x2F, 0xFF, 0xEE, 0x3C, 0xFE,
++0x90, 0x96, 0x15, 0x22, 0x90, 0x93, 0x03, 0xE0,
++0x30, 0xE0, 0x1F, 0xE4, 0xFF, 0x12, 0xE2, 0xB0,
++0xE4, 0xFF, 0x11, 0x90, 0x7F, 0x01, 0x11, 0x90,
++0x90, 0x93, 0x03, 0xE0, 0x13, 0x13, 0x54, 0x3F,
++0x30, 0xE0, 0x07, 0x90, 0x04, 0x1F, 0xE0, 0x44,
++0x80, 0xF0, 0x22, 0xE4, 0xFF, 0x74, 0x94, 0x31,
++0x60, 0x74, 0x13, 0x2F, 0xF5, 0x82, 0xE4, 0x34,
++0x93, 0xB1, 0xA0, 0xB4, 0x08, 0xEF, 0xE4, 0xFF,
++0x74, 0x9C, 0x31, 0x60, 0x74, 0x1C, 0x2F, 0xF5,
++0x82, 0xE4, 0x34, 0x93, 0xB1, 0xA0, 0xB4, 0x04,
++0xEF, 0x22, 0xE4, 0x90, 0x95, 0xF1, 0xF0, 0x12,
++0xEF, 0x1B, 0xB1, 0xA7, 0xB1, 0x73, 0x91, 0x93,
++0x90, 0x07, 0xE3, 0xE0, 0x90, 0x95, 0xF0, 0xF0,
++0xE0, 0x60, 0x59, 0xE4, 0x90, 0x95, 0xF2, 0xF0,
++0x90, 0x96, 0x14, 0x74, 0x08, 0xF0, 0x90, 0x05,
++0x68, 0xE0, 0x90, 0x95, 0xF4, 0xF0, 0x90, 0x05,
++0x69, 0xE0, 0x90, 0x95, 0xF5, 0xF0, 0x90, 0x05,
++0x6A, 0xE0, 0x90, 0x95, 0xF6, 0xF0, 0x90, 0x05,
++0x6B, 0xE0, 0x90, 0x95, 0xF7, 0xF0, 0x90, 0x05,
++0x78, 0xE0, 0x90, 0x95, 0xF8, 0xF0, 0x90, 0x05,
++0x79, 0xE0, 0x90, 0x95, 0xF9, 0xF0, 0x90, 0x05,
++0x7A, 0xE0, 0x90, 0x95, 0xFA, 0xF0, 0x90, 0x05,
++0x7B, 0xE0, 0x90, 0x95, 0xFB, 0xF0, 0x7B, 0x01,
++0x7A, 0x95, 0x79, 0xF2, 0x12, 0x90, 0x33, 0x7F,
++0x04, 0x12, 0x04, 0x7E, 0x90, 0x95, 0xF0, 0xE0,
++0xFD, 0x60, 0x3F, 0xA3, 0xE0, 0xF1, 0xB9, 0x80,
++0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9,
++0xFF, 0xEF, 0x5D, 0x60, 0xE7, 0x90, 0x95, 0xF1,
++0xE0, 0xFB, 0x74, 0x01, 0xA8, 0x03, 0x08, 0x80,
++0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xFE, 0xF4, 0xFD,
++0x90, 0x95, 0xF0, 0xE0, 0x5D, 0xF0, 0x90, 0x07,
++0xE3, 0xE0, 0x4E, 0xF0, 0xAF, 0x03, 0x51, 0xFD,
++0x31, 0xBA, 0x90, 0x95, 0xF1, 0xE0, 0x04, 0xF0,
++0x80, 0xBA, 0x22, 0xE4, 0xFF, 0x74, 0x88, 0x31,
++0x60, 0x74, 0x06, 0x2F, 0xF5, 0x82, 0xE4, 0x34,
++0x93, 0xB1, 0xA0, 0xB4, 0x08, 0xEF, 0x90, 0x05,
++0xDC, 0xE0, 0x90, 0x93, 0x0E, 0xF0, 0xE4, 0xFF,
++0x31, 0x5E, 0x74, 0x0F, 0x2F, 0xF5, 0x82, 0xE4,
++0x34, 0x93, 0xB1, 0xA0, 0xB4, 0x04, 0xF1, 0x22,
++0xF5, 0x83, 0xEE, 0xF0, 0x0F, 0xEF, 0x22, 0xE4,
++0xFF, 0x74, 0x80, 0x31, 0x60, 0x74, 0x2D, 0x2F,
++0xF5, 0x82, 0xE4, 0x34, 0x93, 0xB1, 0xA0, 0xB4,
++0x08, 0xEF, 0x22, 0x90, 0x97, 0x2F, 0x11, 0x8A,
++0x54, 0x7F, 0xFD, 0x12, 0x87, 0xA0, 0x54, 0x1F,
++0x12, 0xAF, 0xC7, 0x54, 0xE0, 0x12, 0x87, 0x9E,
++0xFE, 0x54, 0x60, 0xC4, 0x13, 0x54, 0x07, 0x90,
++0x97, 0x32, 0xF0, 0xEE, 0x54, 0x80, 0x12, 0xAE,
++0x75, 0xC4, 0x33, 0x54, 0xE0, 0x12, 0xAF, 0xC7,
++0x54, 0xDF, 0x12, 0x87, 0x70, 0xFE, 0x54, 0x03,
++0xFC, 0xEE, 0x54, 0x30, 0xC4, 0x54, 0x03, 0xC4,
++0x54, 0xF0, 0x12, 0xAF, 0xBA, 0x54, 0xCF, 0x12,
++0x87, 0x70, 0x54, 0x40, 0xC4, 0x13, 0x13, 0xF1,
++0x05, 0x12, 0xAF, 0xBA, 0x54, 0xBF, 0x12, 0x87,
++0x70, 0x54, 0x80, 0x12, 0xAE, 0x75, 0xC4, 0x33,
++0x33, 0x33, 0x54, 0x80, 0x12, 0xAF, 0xBA, 0x54,
++0x7F, 0x12, 0x87, 0x70, 0xFE, 0x54, 0x08, 0x13,
++0x13, 0x13, 0x54, 0x1F, 0x90, 0x97, 0x34, 0xF0,
++0xFB, 0xEE, 0x54, 0x04, 0x13, 0x13, 0x54, 0x3F,
++0xA3, 0xF0, 0xEC, 0x54, 0x03, 0x12, 0xAF, 0xBA,
++0x54, 0xFC, 0x4F, 0xF0, 0xEB, 0x70, 0x0E, 0xEC,
++0x54, 0x03, 0x25, 0xE0, 0x25, 0xE0, 0x12, 0xAF,
++0xBA, 0x54, 0xF3, 0x4F, 0xF0, 0xD1, 0xF2, 0xF5,
++0x83, 0xE0, 0x54, 0xFB, 0xF0, 0xD1, 0xF2, 0xF5,
++0x83, 0xC0, 0x83, 0xC0, 0x82, 0xE0, 0xFF, 0x90,
++0x97, 0x35, 0xE0, 0xF1, 0x9B, 0xD0, 0x82, 0xD0,
++0x83, 0xF0, 0x90, 0x93, 0xED, 0xE0, 0x60, 0x3B,
++0x90, 0x97, 0x2F, 0x12, 0x86, 0x39, 0xE9, 0x24,
++0x03, 0xF9, 0xE4, 0x3A, 0xFA, 0x12, 0x02, 0x06,
++0x54, 0x1F, 0x12, 0x02, 0x4C, 0x90, 0x97, 0x33,
++0x74, 0x01, 0xF0, 0x90, 0x97, 0x33, 0xE0, 0xFF,
++0xC3, 0x94, 0x04, 0x50, 0x16, 0xEF, 0xD1, 0xFB,
++0x12, 0x86, 0x39, 0x8F, 0x82, 0x8E, 0x83, 0xE4,
++0x12, 0x02, 0x5E, 0x90, 0x97, 0x33, 0xE0, 0x04,
++0xF0, 0x80, 0xE0, 0x90, 0x93, 0xEB, 0xE0, 0x54,
++0x07, 0xFF, 0xBF, 0x05, 0x0A, 0xEC, 0xB4, 0x01,
++0x06, 0x90, 0x93, 0xF0, 0x74, 0x01, 0xF0, 0xE4,
++0x90, 0x97, 0x33, 0xF0, 0x90, 0x97, 0x33, 0xE0,
++0xFC, 0xD1, 0xFB, 0x51, 0xF3, 0xFF, 0xED, 0xF1,
++0xCF, 0x12, 0xB4, 0x77, 0xEF, 0xF0, 0x90, 0x97,
++0x33, 0xE0, 0x04, 0xF0, 0xE0, 0xB4, 0x04, 0xE4,
++0xAF, 0x05, 0x90, 0x8A, 0xFF, 0xF1, 0xAD, 0x02,
++0x04, 0x7E, 0x74, 0xC6, 0x2D, 0xF5, 0x82, 0xE4,
++0x34, 0x8D, 0x22, 0x24, 0x03, 0xFF, 0xE4, 0x33,
++0xFE, 0x90, 0x97, 0x2F, 0x22, 0x54, 0x01, 0xC4,
++0x33, 0x33, 0x54, 0xC0, 0x22, 0x7E, 0x00, 0x7F,
++0x33, 0x7D, 0x00, 0x7B, 0x01, 0x7A, 0x88, 0x79,
++0x9D, 0x12, 0x04, 0x80, 0x90, 0x88, 0x9E, 0x74,
++0x0B, 0xF0, 0xA3, 0x74, 0x08, 0xF0, 0x90, 0x86,
++0xB3, 0xE0, 0xFC, 0x64, 0x02, 0x70, 0x19, 0x90,
++0xFD, 0x80, 0xE0, 0x7E, 0x00, 0x30, 0xE2, 0x02,
++0x7E, 0x01, 0xEE, 0xF1, 0x05, 0xFE, 0x90, 0x88,
++0xA0, 0xE0, 0x54, 0xBF, 0x4E, 0xF0, 0x80, 0x31,
++0xEC, 0x64, 0x01, 0x70, 0x0D, 0x90, 0xFD, 0x70,
++0xE0, 0x7F, 0x00, 0x30, 0xE2, 0x02, 0x7F, 0x01,
++0x80, 0x13, 0x90, 0x86, 0xB3, 0xE0, 0x64, 0x03,
++0x70, 0x17, 0x90, 0xFD, 0x78, 0xE0, 0x7F, 0x00,
++0x30, 0xE2, 0x02, 0x7F, 0x01, 0xEF, 0xF1, 0x05,
++0xFF, 0x90, 0x88, 0xA0, 0xE0, 0x54, 0xBF, 0x4F,
++0xF0, 0x7E, 0x00, 0x7F, 0x1B, 0x7D, 0x00, 0x7B,
++0x01, 0x7A, 0x95, 0x79, 0x38, 0x12, 0x04, 0x80,
++0x90, 0x95, 0x50, 0xE0, 0x54, 0xFC, 0xF0, 0x54,
++0x03, 0x44, 0x04, 0xF0, 0x90, 0x95, 0x52, 0x74,
++0x01, 0xF0, 0x22, 0x25, 0xE0, 0x25, 0xE0, 0xFE,
++0xEF, 0x4E, 0x22, 0x90, 0x01, 0xB9, 0x74, 0x01,
++0xF0, 0x90, 0x01, 0xB8, 0x22, 0xE0, 0xFC, 0xA3,
++0xE0, 0xFD, 0xF5, 0x82, 0x8C, 0x83, 0x22, 0x54,
++0x07, 0xFF, 0x74, 0x01, 0x7E, 0x00, 0xA8, 0x07,
++0x08, 0x22, 0xE0, 0x90, 0x01, 0xBA, 0xF0, 0x90,
++0x88, 0x38, 0xE0, 0x90, 0x01, 0xBB, 0x22, 0x75,
++0xF0, 0x08, 0xA4, 0x24, 0x00, 0xF5, 0x82, 0xE4,
++0x34, 0x82, 0xF5, 0x83, 0x22, 0x90, 0x95, 0xDA,
++0x02, 0x86, 0x39, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x12, 0x02, 0x06, 0x90,
++0x88, 0x9C, 0xF0, 0x60, 0x35, 0xA3, 0xE0, 0x20,
++0xE0, 0x30, 0x90, 0x8A, 0xB9, 0x12, 0x90, 0x45,
++0xE4, 0xFD, 0x7F, 0x04, 0x12, 0xB8, 0x7F, 0xFF,
++0xC3, 0x13, 0x30, 0xE0, 0x1D, 0xEF, 0x13, 0x13,
++0x13, 0x54, 0x1F, 0x20, 0xE0, 0x14, 0x90, 0x88,
++0x9B, 0xE0, 0x13, 0x13, 0x54, 0x3F, 0x30, 0xE0,
++0x04, 0x7F, 0x0D, 0x80, 0x02, 0x7F, 0x09, 0x12,
++0x71, 0x9A, 0x22, 0x90, 0x93, 0x3F, 0xE0, 0x20,
++0xE0, 0x02, 0x21, 0x06, 0xE4, 0x90, 0x95, 0x57,
++0xF0, 0x12, 0xF1, 0xDA, 0x40, 0x02, 0x21, 0x06,
++0x12, 0xBF, 0xBA, 0x80, 0x05, 0xC3, 0x33, 0xCE,
++0x33, 0xCE, 0xD8, 0xF9, 0xFF, 0x90, 0x93, 0x40,
++0xE0, 0xFD, 0xEF, 0x5D, 0x60, 0x02, 0x01, 0xFE,
++0x12, 0x02, 0x06, 0xFF, 0x30, 0xE0, 0x1A, 0x90,
++0x93, 0x41, 0xE0, 0xFE, 0x90, 0x95, 0x57, 0xE0,
++0xFD, 0x74, 0x01, 0xA8, 0x05, 0x08, 0x80, 0x02,
++0xC3, 0x33, 0xD8, 0xFC, 0x4E, 0x90, 0x93, 0x41,
++0xF0, 0xEF, 0xC3, 0x13, 0x30, 0xE0, 0x16, 0x90,
++0x93, 0x42, 0xE0, 0xFF, 0x90, 0x95, 0x57, 0x31,
++0x0C, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC,
++0x4F, 0x90, 0x93, 0x42, 0xF0, 0x12, 0x87, 0xA0,
++0xFF, 0x90, 0x95, 0x57, 0xE0, 0xFE, 0x24, 0x43,
++0xF5, 0x82, 0xE4, 0x34, 0x93, 0xF5, 0x83, 0xEF,
++0x12, 0x87, 0x71, 0xFF, 0x74, 0x48, 0x2E, 0xF5,
++0x82, 0xE4, 0x34, 0x93, 0x12, 0xB7, 0x74, 0xFF,
++0x74, 0x4D, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x93,
++0x12, 0x87, 0xF9, 0xFF, 0x74, 0x52, 0x2E, 0xF5,
++0x82, 0xE4, 0x34, 0x93, 0xF5, 0x83, 0xEF, 0xF0,
++0x90, 0x93, 0x40, 0xE0, 0xFF, 0x74, 0x01, 0xA8,
++0x06, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC,
++0x4F, 0x90, 0x93, 0x40, 0xF0, 0x22, 0x90, 0x95,
++0x57, 0xE0, 0x04, 0xF0, 0x01, 0x51, 0x22, 0xE0,
++0xFF, 0x90, 0x97, 0x28, 0xE0, 0xFE, 0x74, 0x01,
++0xA8, 0x06, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3,
++0xC0, 0xD0, 0x90, 0x97, 0x23, 0x12, 0xB7, 0x6B,
++0x12, 0xED, 0x36, 0xF5, 0x83, 0xE0, 0x90, 0x97,
++0x2E, 0xF0, 0xE4, 0x90, 0x97, 0x2B, 0xF0, 0x90,
++0x97, 0x23, 0x12, 0xA3, 0xD7, 0x90, 0x97, 0x26,
++0xF0, 0xEF, 0x54, 0x07, 0x90, 0x97, 0x28, 0x51,
++0x5C, 0xE0, 0x90, 0x97, 0x29, 0xF0, 0xB1, 0x51,
++0x54, 0x7F, 0x90, 0x97, 0x2C, 0xF0, 0x90, 0x97,
++0x23, 0xE0, 0x12, 0xCC, 0x21, 0xE0, 0x90, 0x97,
++0x2D, 0xF0, 0xED, 0x54, 0x7F, 0x90, 0x97, 0x27,
++0xF0, 0xEB, 0x70, 0x21, 0x90, 0x89, 0x3D, 0x51,
++0x76, 0xFF, 0x12, 0xF1, 0x56, 0xFD, 0x90, 0x89,
++0x40, 0x12, 0xBC, 0x49, 0x2D, 0xFF, 0xE4, 0x35,
++0xF0, 0xC3, 0x13, 0xFE, 0xEF, 0x13, 0xFF, 0x90,
++0x97, 0x23, 0xE0, 0x71, 0xB4, 0x90, 0x97, 0x2C,
++0xE0, 0xFF, 0x90, 0x97, 0x27, 0xE0, 0xFE, 0xD3,
++0x9F, 0x40, 0x0C, 0x90, 0x97, 0x24, 0xE0, 0x54,
++0x80, 0xFD, 0xEF, 0x4D, 0xF0, 0x80, 0x0F, 0x90,
++0x97, 0x2D, 0xE0, 0xFF, 0xEE, 0xC3, 0x9F, 0x50,
++0x05, 0x90, 0x97, 0x24, 0xEF, 0xF0, 0x90, 0x97,
++0x24, 0xE0, 0xFE, 0x54, 0x7F, 0x90, 0x97, 0x27,
++0xF0, 0xEE, 0x54, 0x80, 0x90, 0x97, 0x2A, 0xF0,
++0x90, 0x97, 0x25, 0xE0, 0x70, 0x21, 0xA3, 0xE0,
++0x51, 0x7E, 0xC0, 0x83, 0xC0, 0x82, 0x31, 0x07,
++0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4,
++0x5F, 0xD0, 0x82, 0xD0, 0x83, 0xF0, 0x90, 0x97,
++0x29, 0xE0, 0x54, 0x7F, 0xF0, 0x80, 0x39, 0x90,
++0x97, 0x26, 0xE0, 0x51, 0x7E, 0xC0, 0x83, 0xC0,
++0x82, 0x31, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33,
++0xD8, 0xFC, 0x4F, 0xD0, 0x82, 0xD0, 0x83, 0x51,
++0x5C, 0xE0, 0x54, 0x07, 0xFF, 0x90, 0x97, 0x29,
++0xF0, 0x90, 0x89, 0x46, 0x51, 0x76, 0xF5, 0x82,
++0x12, 0xBC, 0x4E, 0x33, 0x33, 0x33, 0x54, 0xF8,
++0x4F, 0x90, 0x97, 0x29, 0xF0, 0x44, 0x80, 0xF0,
++0x90, 0x97, 0x24, 0x51, 0x6E, 0x51, 0x8A, 0xEF,
++0xF0, 0xEE, 0x70, 0x05, 0x90, 0x01, 0xC8, 0xEF,
++0xF0, 0x90, 0x97, 0x29, 0x51, 0x6E, 0x51, 0x61,
++0xEF, 0xF0, 0xEE, 0x71, 0x73, 0xE0, 0x54, 0xFC,
++0xFF, 0x90, 0x97, 0x2E, 0xE0, 0x54, 0x03, 0x4F,
++0xFE, 0x90, 0x97, 0x23, 0xE0, 0xFF, 0x71, 0x73,
++0xEE, 0xF0, 0x7D, 0x01, 0x12, 0x61, 0xF7, 0xD0,
++0xD0, 0x92, 0xAF, 0x22, 0xF0, 0x90, 0x97, 0x23,
++0xE0, 0xC4, 0x54, 0xF0, 0x24, 0x01, 0xF5, 0x82,
++0xE4, 0x34, 0x81, 0xF5, 0x83, 0x22, 0xE0, 0xFF,
++0x90, 0x97, 0x23, 0xE0, 0xFE, 0x22, 0x12, 0x86,
++0x39, 0x90, 0x97, 0x27, 0xE0, 0x22, 0x24, 0x6F,
++0xF5, 0x82, 0xE4, 0x34, 0x8D, 0xF5, 0x83, 0x22,
++0xE5, 0x67, 0xC4, 0x54, 0xF0, 0x24, 0x00, 0xF5,
++0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0x22, 0x8D,
++0x0E, 0xEF, 0x30, 0xE6, 0x19, 0xE5, 0x0E, 0x51,
++0x8A, 0xE0, 0xFD, 0xE5, 0x0E, 0x71, 0x73, 0x71,
++0x80, 0xE4, 0xFB, 0xAF, 0x0E, 0x12, 0x75, 0x80,
++0x71, 0x65, 0xE4, 0xF0, 0x80, 0x4D, 0x71, 0x65,
++0xE0, 0x04, 0xF0, 0x71, 0x65, 0xE0, 0x64, 0x02,
++0x70, 0x15, 0x74, 0x67, 0x25, 0x0E, 0x91, 0x84,
++0xE0, 0xFD, 0xF4, 0x60, 0x02, 0x80, 0x27, 0xE5,
++0x0E, 0x51, 0x8A, 0xE0, 0xFD, 0x80, 0x1F, 0x71,
++0x65, 0xE0, 0xD3, 0x94, 0x03, 0x40, 0x11, 0x90,
++0x8A, 0xB3, 0x12, 0x90, 0x45, 0xAF, 0x0E, 0x12,
++0x04, 0x7E, 0x71, 0x65, 0xE4, 0xF0, 0x80, 0x13,
++0xE5, 0x0E, 0x51, 0x8A, 0xE0, 0xFD, 0xE5, 0x0E,
++0x71, 0x73, 0x71, 0x80, 0x7B, 0x01, 0xAF, 0x0E,
++0x12, 0x75, 0x80, 0xE5, 0x0E, 0x51, 0x8A, 0xE0,
++0xFD, 0x90, 0x96, 0x7F, 0x74, 0x05, 0xF0, 0xE4,
++0xFB, 0xAF, 0x0E, 0xD3, 0x10, 0xAF, 0x01, 0xC3,
++0xC0, 0xD0, 0x90, 0x96, 0x82, 0xED, 0xF0, 0xA3,
++0xEF, 0xF0, 0xA3, 0xEB, 0xF0, 0x90, 0x96, 0x7F,
++0xE0, 0x90, 0x96, 0x85, 0xF0, 0xE4, 0xA3, 0xF0,
++0xEF, 0x12, 0xF1, 0xA8, 0xF5, 0x83, 0xA3, 0xE0,
++0x90, 0x96, 0x87, 0xF0, 0x74, 0x46, 0x2F, 0xB1,
++0x49, 0xE0, 0x90, 0x96, 0x88, 0xF0, 0x90, 0x96,
++0x80, 0x74, 0x0C, 0xF0, 0x90, 0x96, 0xA2, 0x74,
++0x07, 0xF0, 0x7B, 0x01, 0x7A, 0x96, 0x79, 0x80,
++0x12, 0x90, 0x33, 0x7F, 0x04, 0x12, 0x04, 0x7E,
++0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x74, 0xB6, 0x25,
++0x0E, 0xF5, 0x82, 0xE4, 0x34, 0x8E, 0xF5, 0x83,
++0x22, 0xE5, 0x67, 0xC4, 0x54, 0xF0, 0x24, 0x05,
++0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0x22,
++0xE0, 0x54, 0x03, 0x90, 0x92, 0x80, 0xF0, 0x22,
++0xE6, 0xFD, 0xAF, 0x67, 0xEF, 0x51, 0x61, 0xE0,
++0x54, 0xF8, 0xF5, 0x75, 0xED, 0x42, 0x75, 0xEF,
++0x51, 0x61, 0xE5, 0x75, 0xF0, 0x22, 0xE5, 0x77,
++0x25, 0xE0, 0x24, 0x75, 0xF5, 0x82, 0xE4, 0x34,
++0x81, 0xF5, 0x83, 0xE4, 0x93, 0xFE, 0x74, 0x01,
++0x93, 0xFF, 0xE5, 0x75, 0x25, 0xE0, 0x24, 0x75,
++0xF5, 0x82, 0xE4, 0x34, 0x8D, 0xF5, 0x83, 0xEE,
++0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0x8F, 0x75, 0x8D,
++0x76, 0xEF, 0x51, 0x8A, 0xE0, 0xFD, 0x54, 0x7F,
++0xF5, 0x77, 0xED, 0x54, 0x80, 0xF5, 0x78, 0xB1,
++0x51, 0xF5, 0x7A, 0x75, 0xF0, 0x12, 0xEF, 0x12,
++0xAF, 0xBF, 0xC4, 0x54, 0x03, 0xF5, 0x7B, 0x91,
++0x80, 0x74, 0xFF, 0xF0, 0x71, 0x9E, 0xE5, 0x78,
++0x4D, 0xFF, 0x91, 0x8C, 0xEF, 0xF0, 0xE5, 0x75,
++0x71, 0x73, 0xE0, 0x54, 0x03, 0xF5, 0x79, 0x74,
++0x46, 0x25, 0x75, 0xB1, 0x49, 0xE5, 0x79, 0xF0,
++0xE5, 0x77, 0x65, 0x7A, 0x70, 0x23, 0x75, 0xF0,
++0x12, 0xE5, 0x75, 0x12, 0xAF, 0xCC, 0xC4, 0x13,
++0x54, 0x07, 0x30, 0xE0, 0x0B, 0xE5, 0x78, 0x70,
++0x07, 0xE5, 0x77, 0x44, 0x80, 0xFD, 0x80, 0x4B,
++0x71, 0x9E, 0x7D, 0x07, 0xAF, 0x75, 0x02, 0xB6,
++0xF8, 0xE5, 0x77, 0xC3, 0x95, 0x7A, 0x50, 0x35,
++0xAB, 0x75, 0xAD, 0x7A, 0xAF, 0x77, 0x12, 0x72,
++0x7F, 0xAD, 0x07, 0xE5, 0x77, 0xC3, 0x94, 0x0C,
++0x40, 0x29, 0x75, 0xF0, 0x12, 0xE5, 0x75, 0x12,
++0xAF, 0xCC, 0xFE, 0xC4, 0x13, 0x54, 0x07, 0x30,
++0xE0, 0x19, 0xE5, 0x76, 0x60, 0x15, 0xE5, 0x78,
++0x70, 0x11, 0xE5, 0x77, 0x44, 0x80, 0xFD, 0x91,
++0x80, 0xEF, 0xF0, 0x80, 0x06, 0x91, 0x8C, 0xE5,
++0x7A, 0xF0, 0xFD, 0x90, 0x92, 0x80, 0xE5, 0x79,
++0xF0, 0xAB, 0x76, 0xAF, 0x75, 0x02, 0x75, 0x80,
++0x74, 0x67, 0x25, 0x75, 0xF5, 0x82, 0xE4, 0x34,
++0x96, 0xF5, 0x83, 0x22, 0x74, 0xC6, 0x25, 0x75,
++0xF5, 0x82, 0xE4, 0x34, 0x8E, 0xF5, 0x83, 0x22,
++0xAA, 0x07, 0xA9, 0x05, 0xEA, 0x51, 0x8A, 0xE0,
++0xF5, 0x75, 0x54, 0x7F, 0xF5, 0x77, 0x75, 0xF0,
++0x12, 0xEA, 0x12, 0xCC, 0x24, 0xE0, 0x90, 0x95,
++0xE9, 0xF0, 0x75, 0xF0, 0x12, 0xEA, 0xB1, 0x55,
++0xFF, 0xEA, 0x71, 0x73, 0xE0, 0x54, 0x03, 0xF5,
++0x76, 0xE5, 0x77, 0x90, 0x81, 0x9D, 0x93, 0xFD,
++0xEA, 0x12, 0xF1, 0xA8, 0xF5, 0x83, 0xE4, 0xF0,
++0xA3, 0xED, 0xF0, 0x75, 0xF0, 0x12, 0xEA, 0x12,
++0xAF, 0xBF, 0xFE, 0xC4, 0x54, 0x03, 0x90, 0x95,
++0xE8, 0xF0, 0x74, 0xC6, 0x2A, 0x91, 0x90, 0xE5,
++0x77, 0xF0, 0x74, 0x46, 0x2A, 0xB1, 0x49, 0xE5,
++0x76, 0xF0, 0xE5, 0x77, 0xD3, 0x9F, 0x40, 0x04,
++0x8F, 0x77, 0x8F, 0x75, 0x89, 0x78, 0xE4, 0xFF,
++0xEF, 0xC3, 0x95, 0x78, 0x50, 0x34, 0xE5, 0x75,
++0x30, 0xE7, 0x09, 0x85, 0x77, 0x75, 0x19, 0xE9,
++0x70, 0x25, 0x80, 0x26, 0x90, 0x95, 0xE9, 0xE0,
++0xFD, 0xE5, 0x77, 0xD3, 0x9D, 0x40, 0x10, 0xAB,
++0x02, 0x90, 0x95, 0xED, 0xE9, 0xF0, 0xAF, 0x77,
++0x12, 0xE9, 0xDF, 0x8F, 0x75, 0x80, 0x0B, 0x90,
++0x95, 0xE9, 0xE0, 0xF5, 0x75, 0x80, 0x03, 0x0F,
++0x80, 0xC6, 0xAF, 0x02, 0x90, 0x92, 0x80, 0xE5,
++0x76, 0xF0, 0xE4, 0xFB, 0xAD, 0x75, 0x02, 0x75,
++0x80, 0xF5, 0x82, 0xE4, 0x34, 0x8E, 0xF5, 0x83,
++0x22, 0x75, 0xF0, 0x12, 0xEF, 0x90, 0x89, 0x4F,
++0x12, 0x04, 0x6E, 0xE0, 0x22, 0x90, 0x04, 0x85,
++0xE0, 0xF5, 0x70, 0x90, 0x96, 0x66, 0xE0, 0x04,
++0xF0, 0xE4, 0xF5, 0x67, 0x90, 0x88, 0x2B, 0xE0,
++0xFF, 0xE5, 0x67, 0xC3, 0x9F, 0x40, 0x03, 0x02,
++0xCB, 0xD9, 0x51, 0x88, 0xE0, 0xF5, 0x72, 0x12,
++0xF1, 0x86, 0xE0, 0x65, 0x72, 0x60, 0x14, 0x90,
++0x96, 0x7F, 0x74, 0x06, 0xF0, 0xE4, 0xFB, 0xAD,
++0x72, 0xAF, 0x67, 0x71, 0x13, 0x12, 0xF1, 0x86,
++0xE5, 0x72, 0xF0, 0x90, 0x04, 0xA0, 0xE0, 0x64,
++0x01, 0x70, 0x42, 0xA3, 0xE0, 0x65, 0x67, 0x70,
++0x3C, 0xA3, 0xE0, 0xF5, 0x68, 0xA3, 0xE0, 0x90,
++0x95, 0xE5, 0xF0, 0x51, 0x88, 0xE0, 0x65, 0x68,
++0x70, 0x03, 0x02, 0xCB, 0xD4, 0x51, 0x88, 0xE5,
++0x68, 0xF0, 0x71, 0x71, 0xE0, 0x54, 0xFC, 0xFF,
++0x90, 0x95, 0xE5, 0xE0, 0x54, 0x03, 0x4F, 0xFF,
++0x71, 0x71, 0xEF, 0xF0, 0x90, 0x96, 0x7F, 0x74,
++0x07, 0xF0, 0xE4, 0xFB, 0xAD, 0x68, 0xAF, 0x67,
++0x71, 0x13, 0x02, 0xCB, 0xD4, 0x75, 0xF0, 0x12,
++0xE5, 0x67, 0x12, 0xB7, 0x4D, 0xE0, 0xFF, 0x90,
++0x95, 0xDD, 0xE4, 0xF0, 0xA3, 0xEF, 0xF0, 0x75,
++0xF0, 0x12, 0xE5, 0x67, 0x90, 0x89, 0x53, 0x12,
++0x04, 0x6E, 0xE0, 0xF5, 0x6D, 0xA3, 0xE0, 0xF5,
++0x6E, 0xE5, 0x67, 0x75, 0xF0, 0x12, 0xA4, 0x24,
++0x57, 0xF9, 0x74, 0x89, 0x35, 0xF0, 0xFA, 0x7B,
++0x01, 0x90, 0x95, 0xDA, 0x12, 0x86, 0x42, 0x12,
++0xF1, 0xBC, 0xFF, 0x12, 0x03, 0x13, 0x2F, 0xFF,
++0x12, 0xF1, 0xC2, 0x2F, 0xFF, 0x12, 0xCC, 0x6D,
++0x2F, 0xFF, 0x12, 0xCC, 0x4E, 0x2F, 0xF5, 0x71,
++0x51, 0x88, 0xE0, 0xF5, 0x68, 0x54, 0x80, 0xF5,
++0x6A, 0xE5, 0x68, 0x54, 0x7F, 0xF5, 0x69, 0x75,
++0xF0, 0x12, 0xE5, 0x67, 0x12, 0xB6, 0xBA, 0xE0,
++0x64, 0x01, 0x60, 0x02, 0xE1, 0xB0, 0x12, 0xBF,
++0xDD, 0x12, 0xF1, 0xBC, 0xFF, 0xAE, 0xF0, 0x12,
++0x03, 0x13, 0x2F, 0xFF, 0xE5, 0xF0, 0x3E, 0xFE,
++0x12, 0xF1, 0xC2, 0x2F, 0xFF, 0xEE, 0x12, 0xCC,
++0x6A, 0x2F, 0xFF, 0xEE, 0x35, 0xF0, 0xFE, 0x12,
++0xCC, 0x4E, 0x2F, 0xFF, 0xEE, 0x35, 0xF0, 0x90,
++0x95, 0xDF, 0xF0, 0xA3, 0xEF, 0xF0, 0x12, 0x03,
++0x13, 0xFF, 0xC3, 0x90, 0x95, 0xE0, 0xE0, 0x9F,
++0xFE, 0x90, 0x95, 0xDF, 0xE0, 0x95, 0xF0, 0x90,
++0x95, 0xE1, 0xF0, 0xA3, 0xCE, 0xF0, 0x12, 0xCC,
++0x6D, 0xFD, 0xAC, 0xF0, 0x25, 0xE0, 0xFF, 0xEC,
++0x33, 0xFE, 0xEF, 0x2D, 0xFD, 0xEE, 0x3C, 0xFC,
++0x12, 0xF1, 0xC2, 0x25, 0xE0, 0xFF, 0xE5, 0xF0,
++0x33, 0xFE, 0x12, 0xF1, 0xBC, 0x2F, 0xFF, 0xEE,
++0x35, 0xF0, 0xCF, 0x2D, 0xFD, 0xEF, 0x3C, 0xFC,
++0x12, 0xBF, 0xDD, 0x12, 0xCC, 0x4E, 0xAE, 0xF0,
++0x78, 0x02, 0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8,
++0xF9, 0x2D, 0xFF, 0xEC, 0x3E, 0x90, 0x95, 0xE3,
++0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x95, 0xDD, 0x12,
++0xF0, 0xF6, 0x12, 0xF1, 0xE3, 0x12, 0xF1, 0x1A,
++0x50, 0x08, 0x90, 0x95, 0xDD, 0x12, 0xF1, 0x26,
++0x80, 0x04, 0x7E, 0xFF, 0x7F, 0xFF, 0xE5, 0x67,
++0x25, 0xE0, 0x12, 0xF1, 0xE3, 0x71, 0xBD, 0x90,
++0x95, 0xDF, 0x12, 0xF0, 0xF6, 0x12, 0xF1, 0xEB,
++0x12, 0xF1, 0x1A, 0x50, 0x08, 0x90, 0x95, 0xDF,
++0x12, 0xF1, 0x26, 0x80, 0x04, 0x7E, 0xFF, 0x7F,
++0xFF, 0xE5, 0x67, 0x25, 0xE0, 0x12, 0xF1, 0xEB,
++0x71, 0xBD, 0x90, 0x95, 0xE3, 0x12, 0xF0, 0xF6,
++0x12, 0xF1, 0xF3, 0x12, 0xF1, 0x1A, 0x50, 0x08,
++0x90, 0x95, 0xE3, 0x12, 0xF1, 0x26, 0x80, 0x04,
++0x7E, 0xFF, 0x7F, 0xFF, 0xE5, 0x67, 0x25, 0xE0,
++0x12, 0xF1, 0xF3, 0x71, 0xBD, 0xC3, 0x74, 0xFF,
++0x95, 0x6E, 0xFF, 0x74, 0xFF, 0x95, 0x6D, 0xFE,
++0x12, 0xF1, 0x7A, 0x12, 0xF1, 0x1A, 0x50, 0x0A,
++0xE5, 0x6E, 0x2D, 0xFF, 0xE5, 0x6D, 0x3C, 0xFE,
++0x80, 0x04, 0x7E, 0xFF, 0x7F, 0xFF, 0x12, 0xF1,
++0x7A, 0x71, 0xBD, 0x12, 0xF2, 0x13, 0xFB, 0xC3,
++0x74, 0xFF, 0x9B, 0xFF, 0x74, 0xFF, 0x9E, 0xFE,
++0x74, 0xFF, 0x94, 0x00, 0xFD, 0x74, 0xFF, 0x94,
++0x00, 0xFC, 0x90, 0x8D, 0x71, 0x12, 0xE5, 0xDD,
++0x50, 0x12, 0x12, 0xF2, 0x13, 0xFF, 0xE4, 0xFC,
++0xFD, 0x90, 0x8D, 0x71, 0x12, 0x86, 0x2D, 0x12,
++0x85, 0xA9, 0x80, 0x06, 0x74, 0xFF, 0xFF, 0xFE,
++0xFD, 0xFC, 0x90, 0x8D, 0x71, 0x12, 0x04, 0x31,
++0xAF, 0x67, 0x12, 0x78, 0x4A, 0xEF, 0x70, 0x03,
++0x02, 0xCB, 0xD4, 0x75, 0xF0, 0x12, 0xE5, 0x67,
++0x90, 0x89, 0x52, 0x12, 0x04, 0x6E, 0x12, 0xAE,
++0x74, 0x30, 0xE0, 0x03, 0x02, 0xCB, 0xD4, 0xE5,
++0x67, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x51, 0x7E,
++0xE0, 0xFD, 0x7C, 0x00, 0xE5, 0x67, 0x12, 0xBF,
++0xB7, 0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE,
++0xD8, 0xF9, 0xFF, 0xEE, 0x5C, 0xFE, 0xEF, 0x5D,
++0x4E, 0x60, 0x03, 0x02, 0xCB, 0xD4, 0xE5, 0x6E,
++0x45, 0x6D, 0x70, 0x0C, 0x90, 0x95, 0xDD, 0xE0,
++0x70, 0x02, 0xA3, 0xE0, 0x70, 0x02, 0x61, 0xD4,
++0x90, 0x96, 0x54, 0xE0, 0x60, 0x13, 0x75, 0x73,
++0x0A, 0x91, 0x35, 0xF5, 0x83, 0xE4, 0x93, 0xC3,
++0x13, 0x74, 0x01, 0x93, 0x13, 0xF5, 0x74, 0x80,
++0x09, 0x7B, 0xFF, 0xD1, 0x90, 0xE4, 0xF5, 0x73,
++0xF5, 0x74, 0x75, 0xF0, 0x12, 0xE5, 0x67, 0x12,
++0xC5, 0x55, 0xFF, 0xE5, 0x69, 0xD3, 0x9F, 0x40,
++0x08, 0x8F, 0x69, 0xE5, 0x69, 0x45, 0x6A, 0xF5,
++0x68, 0x71, 0xE4, 0xE0, 0xC3, 0x94, 0x05, 0x40,
++0x02, 0x21, 0xD4, 0xE5, 0x69, 0x90, 0x81, 0x61,
++0x93, 0xF5, 0x6F, 0xFD, 0xAF, 0x69, 0x12, 0x60,
++0x6F, 0x8F, 0x6F, 0xE5, 0x6A, 0x60, 0x04, 0x05,
++0x6F, 0x05, 0x6F, 0xE5, 0x69, 0xC3, 0x94, 0x0C,
++0x40, 0x1D, 0x74, 0x56, 0x25, 0x67, 0x12, 0xB7,
++0xC8, 0xE0, 0xFF, 0x54, 0x7F, 0xFE, 0xEF, 0x30,
++0xE7, 0x06, 0xE5, 0x6F, 0x2E, 0xFF, 0x80, 0x05,
++0xC3, 0xE5, 0x6F, 0x9E, 0xFF, 0x8F, 0x6F, 0xE5,
++0x6F, 0xD3, 0x94, 0x1A, 0xAF, 0x6F, 0x40, 0x02,
++0x7F, 0x1A, 0x8F, 0x6F, 0xE5, 0x68, 0x90, 0x81,
++0xD9, 0x93, 0xFF, 0xD3, 0x90, 0x95, 0xDE, 0xE0,
++0x9F, 0x90, 0x95, 0xDD, 0xE0, 0x94, 0x00, 0x40,
++0x02, 0x21, 0x8B, 0xC3, 0xE5, 0x6E, 0x94, 0x0A,
++0xE5, 0x6D, 0x94, 0x00, 0x40, 0x02, 0x21, 0x3A,
++0x71, 0xDA, 0xF5, 0x83, 0xE0, 0xC3, 0x94, 0x01,
++0x40, 0x07, 0x71, 0xDA, 0xF5, 0x83, 0xE0, 0x14,
++0xF0, 0x12, 0xBF, 0xDD, 0x91, 0x4E, 0xFF, 0x90,
++0x95, 0xDE, 0xE0, 0x2F, 0xFF, 0x90, 0x95, 0xDD,
++0xE0, 0x91, 0x6A, 0x2F, 0xFD, 0xEE, 0x35, 0xF0,
++0xFC, 0xE5, 0x6D, 0xC3, 0x13, 0xFE, 0xE5, 0x6E,
++0x13, 0xFF, 0xD3, 0xED, 0x9F, 0xEC, 0x9E, 0x40,
++0x0F, 0xE5, 0x67, 0x94, 0x05, 0x50, 0x07, 0x71,
++0xDA, 0xF5, 0x83, 0x74, 0x02, 0xF0, 0x21, 0x8B,
++0x12, 0xBF, 0xDD, 0x12, 0x03, 0x13, 0x65, 0x6E,
++0x70, 0x04, 0xE5, 0xF0, 0x65, 0x6D, 0x70, 0x26,
++0xE5, 0x67, 0xC3, 0x94, 0x05, 0x50, 0x13, 0x71,
++0xDA, 0xF5, 0x83, 0xE0, 0xD3, 0x94, 0x00, 0x40,
++0x09, 0x7D, 0x06, 0xAF, 0x67, 0x12, 0xB6, 0xF8,
++0x61, 0xD4, 0xE4, 0xFD, 0xAF, 0x67, 0x12, 0xC3,
++0xC5, 0x12, 0xB6, 0xF4, 0x61, 0xB9, 0x91, 0x54,
++0x61, 0xB9, 0x71, 0xDA, 0xF5, 0x83, 0xE4, 0xF0,
++0x90, 0x91, 0x6C, 0x74, 0x02, 0xF0, 0xAB, 0x6F,
++0xAD, 0x67, 0xAF, 0x6E, 0xAE, 0x6D, 0x12, 0x41,
++0x9C, 0x8E, 0x6B, 0x8F, 0x6C, 0x91, 0x35, 0xF5,
++0x83, 0xC3, 0x74, 0x01, 0x93, 0x95, 0x74, 0xFF,
++0xE4, 0x93, 0x94, 0x00, 0xFE, 0xD3, 0xE5, 0x6C,
++0x9F, 0xE5, 0x6B, 0x9E, 0x40, 0x0D, 0x71, 0xFC,
++0xE4, 0xF0, 0x7D, 0x01, 0xAF, 0x67, 0x12, 0xC3,
++0xC5, 0x61, 0xB9, 0x91, 0x62, 0xC3, 0xE5, 0x6C,
++0x9F, 0xE5, 0x6B, 0x94, 0x00, 0x50, 0x0D, 0x71,
++0xFC, 0xE4, 0xF0, 0x7D, 0x01, 0xAF, 0x67, 0x12,
++0xC4, 0x98, 0x61, 0xB9, 0x12, 0xB6, 0xF4, 0x71,
++0xFC, 0xE0, 0x04, 0xF0, 0xE5, 0x69, 0x90, 0x81,
++0xED, 0x93, 0x25, 0x73, 0xFF, 0xE4, 0x33, 0xFE,
++0x71, 0xFC, 0xE0, 0xC3, 0x9F, 0xEE, 0x91, 0x2E,
++0x50, 0x02, 0x61, 0xB9, 0x71, 0xFC, 0xE4, 0xF0,
++0x91, 0x62, 0x91, 0x35, 0xF5, 0x83, 0x74, 0x01,
++0x93, 0x2F, 0xFF, 0xE4, 0x93, 0x34, 0x00, 0xC3,
++0x13, 0xFE, 0xEF, 0x13, 0xFF, 0xE5, 0x67, 0x12,
++0xC3, 0xB4, 0x61, 0xB9, 0x71, 0xE4, 0xE0, 0x64,
++0x05, 0x60, 0x02, 0x41, 0x92, 0x90, 0x04, 0xA0,
++0xE0, 0x64, 0x02, 0x70, 0x10, 0x91, 0x08, 0xE4,
++0xF0, 0x90, 0x04, 0xA1, 0xE0, 0x78, 0x88, 0xF6,
++0x12, 0xC3, 0x88, 0x61, 0xCD, 0xAD, 0x69, 0xAF,
++0x67, 0x12, 0x72, 0xEE, 0x91, 0x8B, 0xEF, 0xF0,
++0xE5, 0x67, 0x12, 0xC2, 0x61, 0xE0, 0x54, 0x07,
++0x78, 0x88, 0xF6, 0x91, 0x41, 0xFF, 0xC3, 0x94,
++0x30, 0x40, 0x1C, 0x75, 0xF0, 0x12, 0xE5, 0x67,
++0x12, 0xAF, 0xBF, 0xFE, 0xC4, 0x13, 0x13, 0x54,
++0x03, 0x20, 0xE0, 0x0B, 0x91, 0x8B, 0xE0, 0x60,
++0x06, 0x90, 0x96, 0x54, 0xE0, 0x60, 0x0A, 0xE4,
++0x78, 0x88, 0xF6, 0x91, 0x08, 0xE4, 0xF0, 0x80,
++0x52, 0x91, 0x7F, 0xE0, 0xFE, 0x24, 0x05, 0xFD,
++0xE4, 0x33, 0xFC, 0xEF, 0x91, 0x2B, 0x50, 0x1B,
++0x91, 0x41, 0x24, 0x05, 0xFD, 0xE4, 0x33, 0xFC,
++0xEE, 0x91, 0x2B, 0x50, 0x0E, 0x91, 0x73, 0xE0,
++0xB5, 0x69, 0x08, 0x91, 0x15, 0xE0, 0xC3, 0x94,
++0x0A, 0x40, 0x23, 0x78, 0x88, 0xE6, 0xFF, 0x70,
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++0xB4, 0x01, 0x04, 0x76, 0x03, 0x80, 0x02, 0x76,
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++0x91, 0x7F, 0xEF, 0xF0, 0x80, 0x05, 0x91, 0x08,
++0xE0, 0x04, 0xF0, 0x91, 0x73, 0xE5, 0x69, 0xF0,
++0x61, 0xB4, 0x71, 0xE4, 0xE0, 0x64, 0x06, 0x60,
++0x02, 0x61, 0xB9, 0xF5, 0x6B, 0xF5, 0x6C, 0xE5,
++0x67, 0x12, 0xC2, 0x61, 0xE0, 0x54, 0x07, 0x78,
++0x88, 0xF6, 0xD3, 0xE5, 0x6E, 0x94, 0xE8, 0xE5,
++0x6D, 0x94, 0x03, 0x40, 0x06, 0x78, 0x86, 0x76,
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++0xE5, 0x6D, 0x94, 0x00, 0x40, 0x06, 0x78, 0x86,
++0x76, 0x02, 0x80, 0x04, 0xE4, 0x78, 0x86, 0xF6,
++0xE5, 0x6E, 0xAE, 0x6D, 0x78, 0x86, 0x86, 0x00,
++0x08, 0x80, 0x05, 0xCE, 0xC3, 0x13, 0xCE, 0x13,
++0xD8, 0xF9, 0xFF, 0x90, 0x82, 0x06, 0xE4, 0x91,
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++0xF0, 0xE4, 0x78, 0x87, 0xF6, 0x12, 0xBF, 0xDD,
++0x78, 0x87, 0xE6, 0xFD, 0x12, 0xF1, 0x56, 0xAE,
++0xF0, 0x78, 0x86, 0x86, 0x00, 0x08, 0x80, 0x05,
++0xCE, 0xC3, 0x13, 0xCE, 0x13, 0xD8, 0xF9, 0xFF,
++0xED, 0x90, 0x82, 0x01, 0x91, 0x5B, 0xEF, 0x25,
++0x6C, 0xF5, 0x6C, 0xEE, 0x35, 0x6B, 0xF5, 0x6B,
++0xC3, 0x90, 0x95, 0xE7, 0xE0, 0x95, 0x6C, 0x90,
++0x95, 0xE6, 0xE0, 0x95, 0x6B, 0x40, 0x07, 0x78,
++0x87, 0x06, 0xE6, 0xB4, 0x05, 0xBF, 0x78, 0x87,
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++0x01, 0xFF, 0xE4, 0x33, 0xA2, 0xE7, 0x13, 0xEF,
++0x13, 0x08, 0xF6, 0xD3, 0x9D, 0x40, 0x07, 0xE6,
++0x79, 0x87, 0x97, 0xF6, 0x80, 0x04, 0xE4, 0x78,
++0x89, 0xF6, 0x71, 0xF0, 0xE0, 0xC3, 0x13, 0xFF,
++0x78, 0x89, 0xE6, 0xC4, 0x33, 0x54, 0xE0, 0x2F,
++0xFF, 0x71, 0xF0, 0xEF, 0xF0, 0x71, 0xF0, 0xE0,
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++0xC0, 0xF0, 0x71, 0xF0, 0xE0, 0x24, 0x1F, 0xFF,
++0xE4, 0x33, 0xFE, 0xEF, 0x78, 0x06, 0xCE, 0xA2,
++0xE7, 0x13, 0xCE, 0x13, 0xD8, 0xF8, 0x78, 0x89,
++0xF6, 0xE6, 0x25, 0xE0, 0xF6, 0x70, 0x03, 0xFF,
++0x80, 0x05, 0x78, 0x89, 0xE6, 0x14, 0xFF, 0x78,
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++0x94, 0x03, 0x90, 0x95, 0xDD, 0xE0, 0x94, 0x00,
++0x40, 0x02, 0xE4, 0xF6, 0x78, 0x88, 0x12, 0xC3,
++0x88, 0x71, 0xE4, 0xE0, 0xFF, 0xD3, 0x94, 0x05,
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++0x36, 0xF5, 0x83, 0xE0, 0x90, 0x97, 0x78, 0xF0,
++0x90, 0x88, 0x32, 0x12, 0xAE, 0x74, 0x30, 0xE0,
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++0x33, 0x33, 0x33, 0x54, 0xF8, 0x90, 0x88, 0x4B,
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++0x33, 0x54, 0xF8, 0x90, 0x88, 0x4A, 0xF0, 0x80,
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++0x88, 0x4A, 0x74, 0x08, 0xF0, 0x74, 0x10, 0x2B,
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++0x3E, 0xEB, 0xF0, 0x90, 0x88, 0x4B, 0xE0, 0xC3,
++0x9D, 0x2F, 0x80, 0x11, 0xC3, 0xED, 0x9E, 0x2B,
++0x90, 0x88, 0x3E, 0xF0, 0x90, 0x88, 0x4A, 0xE0,
++0xFF, 0xA3, 0xE0, 0xC3, 0x9F, 0x90, 0x88, 0x4E,
++0xF0, 0x90, 0x88, 0x4B, 0xB1, 0x6D, 0x90, 0x88,
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++0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xE0, 0xFF, 0x24,
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++0x12, 0x76, 0xF7, 0x90, 0x88, 0xE6, 0xE0, 0x54,
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++0xE0, 0xB4, 0x14, 0x09, 0x90, 0x04, 0x9C, 0xE4,
++0xF0, 0x90, 0x88, 0xE8, 0xF0, 0x90, 0x88, 0x2C,
++0xE0, 0x30, 0xE0, 0x06, 0x90, 0x88, 0x2E, 0x74,
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++0x90, 0x05, 0x61, 0x12, 0x8F, 0xE4, 0x12, 0x9D,
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++0x78, 0x10, 0x12, 0x03, 0xFE, 0xD0, 0x03, 0xD0,
++0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x86, 0x20,
++0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07,
++0x12, 0x8F, 0xE3, 0x78, 0x18, 0x12, 0x03, 0xFE,
++0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00,
++0x12, 0x86, 0x20, 0x90, 0x88, 0x81, 0x12, 0x04,
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++0xA3, 0xE0, 0x30, 0xE0, 0x0B, 0x12, 0xF1, 0x09,
++0x74, 0x05, 0xF0, 0x12, 0x6E, 0x2F, 0xB1, 0x76,
++0x90, 0x88, 0x32, 0x12, 0x9D, 0xC0, 0x30, 0xE0,
++0x0A, 0x90, 0x01, 0x3B, 0xE0, 0x30, 0xE4, 0x03,
++0x12, 0xAD, 0x76, 0x90, 0x8A, 0xE5, 0x12, 0x90,
++0x45, 0x7F, 0x01, 0x12, 0x04, 0x7E, 0x90, 0x93,
++0x3B, 0xE0, 0x30, 0xE0, 0x0A, 0x90, 0x01, 0x3B,
++0xE0, 0x30, 0xE4, 0x03, 0x12, 0xAD, 0x76, 0x22,
++0x7A, 0x81, 0x79, 0xB1, 0x90, 0x89, 0x46, 0x02,
++0x86, 0x42, 0x7B, 0x00, 0x7A, 0x00, 0x79, 0x00,
++0x90, 0x89, 0x2E, 0x12, 0x86, 0x42, 0x7B, 0xFF,
++0x7A, 0x80, 0x79, 0x80, 0x90, 0x89, 0x31, 0x12,
++0x86, 0x42, 0x7A, 0x80, 0x79, 0xBF, 0x90, 0x89,
++0x34, 0x12, 0x86, 0x42, 0x7A, 0x81, 0x79, 0x61,
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++0x79, 0x75, 0x90, 0x89, 0x3D, 0x12, 0x86, 0x42,
++0x7A, 0x81, 0x79, 0x9D, 0x90, 0x89, 0x40, 0x12,
++0x86, 0x42, 0xD1, 0x90, 0x7A, 0x81, 0x79, 0xD9,
++0x90, 0x89, 0x49, 0x12, 0x86, 0x42, 0x7A, 0x82,
++0x79, 0x01, 0x90, 0x89, 0x4C, 0x12, 0x86, 0x42,
++0xE4, 0x90, 0x96, 0x66, 0xF0, 0x90, 0x96, 0x55,
++0xF0, 0x90, 0x95, 0x57, 0xF0, 0x12, 0xF1, 0xDA,
++0x50, 0x14, 0x74, 0x77, 0x2F, 0xF5, 0x82, 0xE4,
++0x34, 0x96, 0xF5, 0x83, 0xE4, 0xF0, 0x90, 0x95,
++0x57, 0xE0, 0x04, 0xF0, 0x80, 0xE7, 0x22, 0xF1,
++0xF0, 0x12, 0x7B, 0xDB, 0x90, 0x8A, 0xC5, 0x12,
++0x8A, 0x65, 0xD1, 0x9A, 0xF1, 0x59, 0x12, 0xA4,
++0xD5, 0x12, 0x95, 0xF2, 0xF1, 0x53, 0x12, 0xEB,
++0x01, 0x90, 0x8A, 0x73, 0x12, 0x8A, 0x65, 0x90,
++0x00, 0x6A, 0xE0, 0x30, 0xE2, 0x14, 0x90, 0x92,
++0x20, 0x74, 0x01, 0xF0, 0xA3, 0x74, 0xF4, 0xF0,
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++0x66, 0x33, 0x22, 0x12, 0xF1, 0x49, 0x02, 0x04,
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++0x44, 0x80, 0xF0, 0x12, 0xDF, 0xE4, 0x12, 0xEB,
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++0x06, 0x0A, 0xE0, 0x44, 0x10, 0xF0, 0x90, 0x07,
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++0x90, 0x88, 0x9E, 0x80, 0x23, 0x12, 0x87, 0xA0,
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++0xF0, 0xD0, 0x07, 0xD0, 0x06, 0xD0, 0x05, 0xD0,
++0x04, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0,
++0x00, 0xD0, 0xD0, 0xD0, 0x82, 0xD0, 0x83, 0xD0,
++0xF0, 0xD0, 0xE0, 0x32, 0x90, 0x93, 0x58, 0xE0,
++0x30, 0xE0, 0x0B, 0x90, 0x93, 0xD8, 0xE0, 0x60,
++0x05, 0x7F, 0x07, 0x12, 0xEB, 0x10, 0x22, 0x90,
++0x88, 0x9D, 0xE0, 0x30, 0xE0, 0x0D, 0xB1, 0xF4,
++0x30, 0xE0, 0x08, 0x90, 0x8A, 0xBB, 0x12, 0x90,
++0x45, 0xD1, 0x5D, 0x22, 0x90, 0x88, 0xA1, 0xE0,
++0x13, 0x13, 0x54, 0x3F, 0x22, 0xEF, 0x64, 0x39,
++0x70, 0x5A, 0x90, 0x01, 0x63, 0xF0, 0x90, 0x01,
++0x3C, 0x74, 0x10, 0xF0, 0x90, 0x88, 0x9D, 0xE0,
++0x30, 0xE0, 0x49, 0xB1, 0xF4, 0x30, 0xE0, 0x44,
++0x90, 0x88, 0xC2, 0xE0, 0xFF, 0xC4, 0x54, 0x0F,
++0x30, 0xE0, 0x39, 0x90, 0x95, 0x4A, 0xE0, 0x04,
++0xF0, 0x12, 0xF1, 0xB2, 0x30, 0xE0, 0x11, 0xEE,
++0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0, 0x08,
++0xEF, 0x54, 0xEF, 0x90, 0x88, 0xC2, 0xF0, 0x22,
++0x90, 0x88, 0xB0, 0xE0, 0x70, 0x16, 0xD1, 0x62,
++0x90, 0x88, 0x9D, 0xE0, 0x30, 0xE0, 0x0D, 0xB1,
++0xF4, 0x30, 0xE0, 0x08, 0x90, 0x8A, 0xBB, 0x12,
++0x90, 0x45, 0xD1, 0x5D, 0x22, 0xE4, 0xFF, 0x12,
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++0xF0, 0x22, 0x90, 0x88, 0x36, 0xE0, 0x60, 0x15,
++0x90, 0x06, 0x92, 0xE0, 0x30, 0xE1, 0x08, 0x90,
++0x8B, 0x01, 0x12, 0x8A, 0x65, 0x80, 0x06, 0x12,
++0xF2, 0x1B, 0x12, 0xA6, 0xAF, 0x02, 0x9A, 0x12,
++0x90, 0x88, 0xB8, 0xE0, 0x30, 0xE0, 0x05, 0x90,
++0x8A, 0xEB, 0x80, 0x27, 0x90, 0x95, 0x44, 0x12,
++0x9D, 0xC0, 0x30, 0xE0, 0x1B, 0x90, 0x88, 0xC2,
++0xE0, 0xC4, 0x54, 0x0F, 0x20, 0xE0, 0x08, 0x90,
++0x8A, 0xBB, 0x12, 0x90, 0x45, 0xD1, 0x5D, 0x90,
++0x95, 0x44, 0xE0, 0x54, 0xF7, 0xF0, 0x80, 0x06,
++0x90, 0x8A, 0x99, 0x12, 0x8A, 0x65, 0x90, 0x88,
++0xF0, 0xE0, 0x30, 0xE0, 0x06, 0x90, 0x8A, 0xE7,
++0x12, 0x8A, 0x65, 0x22, 0xF1, 0x20, 0x90, 0x96,
++0x1E, 0xEF, 0xF0, 0x20, 0xE0, 0x06, 0x90, 0x01,
++0x3D, 0x74, 0x01, 0xF0, 0x90, 0x96, 0x1E, 0xE0,
++0x90, 0x8A, 0x89, 0x30, 0xE0, 0x13, 0x12, 0x90,
++0x45, 0x7D, 0x01, 0xE4, 0xFF, 0x12, 0x04, 0x7E,
++0x90, 0x88, 0x33, 0xE0, 0x44, 0x04, 0xF0, 0x80,
++0x06, 0x12, 0x90, 0x45, 0x12, 0x96, 0xDB, 0x90,
++0x96, 0x1E, 0xE0, 0x30, 0xE6, 0x11, 0x90, 0x01,
++0x2F, 0xE0, 0x30, 0xE7, 0x04, 0xE4, 0xF0, 0x80,
++0x06, 0x90, 0x01, 0x2F, 0x74, 0x80, 0xF0, 0x12,
++0xF1, 0x09, 0x74, 0x02, 0xF0, 0x02, 0x6E, 0x2F,
++0xE4, 0x90, 0x96, 0x20, 0xF0, 0xA3, 0xF0, 0x7F,
++0x83, 0x12, 0x7B, 0x41, 0x90, 0x96, 0x1F, 0xEF,
++0xF0, 0x7F, 0x83, 0x12, 0x7B, 0x41, 0xAE, 0x07,
++0x90, 0x96, 0x1F, 0xE0, 0xFF, 0xB5, 0x06, 0x01,
++0x22, 0xC3, 0x90, 0x96, 0x21, 0xE0, 0x94, 0x64,
++0x90, 0x96, 0x20, 0xE0, 0x94, 0x00, 0x40, 0x0D,
++0x90, 0x01, 0xC0, 0xE0, 0x44, 0x40, 0xF0, 0x90,
++0x96, 0x1F, 0xE0, 0xFF, 0x22, 0x90, 0x96, 0x20,
++0xF1, 0x66, 0x80, 0xC3, 0x22, 0x22, 0xE4, 0x75,
++0xF0, 0x01, 0x02, 0x02, 0xE7, 0xE4, 0x90, 0x97,
++0x5C, 0xF0, 0xA3, 0xF0, 0x90, 0x05, 0x22, 0xE0,
++0x90, 0x97, 0x5E, 0xF0, 0x7B, 0x47, 0x7D, 0xFF,
++0xE4, 0xFF, 0x12, 0x8F, 0x5D, 0x90, 0x05, 0xF8,
++0xE0, 0x70, 0x1B, 0xA3, 0xE0, 0x70, 0x17, 0xA3,
++0xE0, 0x70, 0x13, 0xA3, 0xE0, 0x70, 0x0F, 0x90,
++0x97, 0x5E, 0xE0, 0xFD, 0x7B, 0x48, 0xE4, 0xFF,
++0x12, 0x8F, 0x5D, 0x7F, 0x01, 0x22, 0x12, 0x97,
++0xBD, 0x30, 0xE0, 0x19, 0xD3, 0x90, 0x97, 0x5D,
++0xE0, 0x94, 0x03, 0x90, 0x97, 0x5C, 0xE0, 0x94,
++0x00, 0x40, 0x06, 0xF1, 0xE9, 0x7B, 0x5A, 0x80,
++0x17, 0x7F, 0x01, 0x80, 0x18, 0xD3, 0x90, 0x97,
++0x5D, 0xE0, 0x94, 0xE8, 0x90, 0x97, 0x5C, 0xE0,
++0x94, 0x03, 0x40, 0x07, 0xF1, 0xE9, 0x7B, 0x5B,
++0x02, 0x8F, 0x51, 0x7F, 0x32, 0x7E, 0x00, 0x12,
++0x7C, 0x6A, 0x90, 0x97, 0x5C, 0xF1, 0x66, 0x80,
++0x9C, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x20, 0xF0,
++0x90, 0x97, 0x5E, 0xE0, 0xFD, 0x22, 0x12, 0x02,
++0x06, 0xFF, 0x90, 0x93, 0xE6, 0xF0, 0xBF, 0x01,
++0x0A, 0x7F, 0x01, 0x12, 0x93, 0x64, 0xE4, 0x90,
++0x93, 0xE6, 0xF0, 0x22, 0xE4, 0xFD, 0x02, 0x8F,
++0xED, 0x12, 0xB8, 0x87, 0x64, 0x01, 0x60, 0x02,
++0x01, 0xA2, 0xEF, 0x24, 0x39, 0x60, 0x12, 0x14,
++0x60, 0x19, 0x24, 0x02, 0x70, 0x1F, 0xE4, 0x90,
++0x95, 0x5D, 0xF0, 0xA3, 0x74, 0x06, 0xF0, 0x80,
++0x14, 0x90, 0x95, 0x5D, 0x74, 0x06, 0xF0, 0xA3,
++0xF0, 0x80, 0x0A, 0x90, 0x95, 0x5D, 0x74, 0x0C,
++0xF0, 0xA3, 0x74, 0x04, 0xF0, 0x11, 0xB6, 0xF0,
++0x11, 0xA3, 0x40, 0x1C, 0x90, 0x95, 0x5B, 0xE0,
++0x12, 0xB7, 0xD0, 0x7A, 0x95, 0x79, 0x5A, 0x12,
++0x5F, 0xA6, 0xBF, 0x01, 0x07, 0x90, 0x95, 0x5A,
++0xE0, 0xF4, 0x70, 0x3E, 0x11, 0xAB, 0x80, 0xE0,
++0x11, 0xB6, 0xF0, 0x11, 0xA3, 0x40, 0x33, 0x90,
++0x95, 0x5B, 0xE0, 0xFD, 0x7C, 0x00, 0x24, 0xA8,
++0xFF, 0xEC, 0x34, 0x01, 0xFE, 0xED, 0x24, 0x01,
++0xFD, 0xEC, 0x33, 0xFC, 0x90, 0x95, 0x5D, 0xE0,
++0xFB, 0xC3, 0xED, 0x9B, 0xFD, 0xEC, 0x94, 0x00,
++0xFC, 0x12, 0x87, 0xF4, 0x8D, 0x82, 0x8C, 0x83,
++0x12, 0x02, 0x1F, 0xFD, 0x11, 0xC6, 0x11, 0xAB,
++0x80, 0xC9, 0x22, 0x90, 0x95, 0x5C, 0xE0, 0xD3,
++0x94, 0x00, 0x22, 0x90, 0x95, 0x5B, 0xE0, 0x04,
++0xF0, 0xA3, 0xE0, 0x14, 0xF0, 0x22, 0x90, 0x95,
++0x5D, 0xE0, 0x90, 0x95, 0x5B, 0xF0, 0x90, 0x95,
++0x5E, 0xE0, 0x90, 0x95, 0x5C, 0x22, 0xE4, 0x90,
++0x95, 0x5F, 0xF0, 0x90, 0x00, 0x37, 0xE0, 0x44,
++0x80, 0xF0, 0x90, 0x00, 0xCF, 0x74, 0x69, 0xF0,
++0xEF, 0x90, 0x00, 0x31, 0xF0, 0xEE, 0x54, 0x03,
++0xFF, 0xA3, 0xE0, 0x54, 0xFC, 0x4F, 0xF0, 0x90,
++0x00, 0x30, 0xED, 0xF0, 0x90, 0x00, 0x33, 0xE0,
++0x44, 0x80, 0xF0, 0x90, 0x00, 0x33, 0xE0, 0x30,
++0xE7, 0x09, 0x31, 0x18, 0x50, 0x05, 0xE0, 0x04,
++0xF0, 0x80, 0xF0, 0x90, 0x00, 0xCF, 0xE4, 0xF0,
++0x90, 0x00, 0x37, 0xE0, 0x54, 0x7F, 0xF0, 0x31,
++0x18, 0x7F, 0x00, 0x50, 0x02, 0x7F, 0x01, 0x22,
++0x90, 0x95, 0x5F, 0xE0, 0xC3, 0x94, 0x64, 0x22,
++0x12, 0x02, 0x06, 0x64, 0x01, 0x70, 0x2B, 0x12,
++0x87, 0xA0, 0x90, 0x95, 0x53, 0x12, 0x87, 0x71,
++0x90, 0x95, 0x54, 0x31, 0x61, 0x31, 0x69, 0x12,
++0x79, 0x53, 0x90, 0x01, 0x25, 0x74, 0x08, 0xF0,
++0xFD, 0x7F, 0x01, 0x12, 0x7B, 0xF7, 0x90, 0x05,
++0x1F, 0xE0, 0x54, 0xFC, 0x44, 0x08, 0xF0, 0x02,
++0x9E, 0x72, 0x7D, 0x08, 0x7F, 0x01, 0x12, 0x7C,
++0x2E, 0x90, 0x05, 0x1F, 0xE0, 0x54, 0xF7, 0xF0,
++0x22, 0xF0, 0x7D, 0x42, 0xE4, 0xFF, 0x02, 0x7B,
++0xBD, 0xED, 0x44, 0x03, 0xFD, 0xEC, 0x90, 0x8B,
++0x9F, 0x12, 0x04, 0x31, 0x7D, 0x42, 0xE4, 0xFF,
++0x22, 0xE4, 0x90, 0x86, 0xAF, 0xF0, 0x12, 0xB7,
++0x64, 0x90, 0x93, 0x01, 0xF0, 0x90, 0x93, 0xF3,
++0xF0, 0xA3, 0xF0, 0x22, 0x75, 0x21, 0x80, 0xE4,
++0xF5, 0x22, 0xF5, 0x23, 0x75, 0x24, 0x80, 0x90,
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++0xF0, 0xA3, 0xE5, 0x23, 0xF0, 0xA3, 0xE5, 0x24,
++0xF0, 0x22, 0x31, 0xB8, 0x12, 0x76, 0x6D, 0x12,
++0x75, 0xE0, 0xB1, 0xE5, 0xB1, 0xBA, 0x80, 0xD4,
++0x90, 0x00, 0x08, 0xE0, 0x54, 0xEF, 0xF0, 0x22,
++0xE4, 0x90, 0x95, 0xB2, 0xF0, 0xB1, 0x9B, 0x31,
++0xB8, 0xE4, 0xFF, 0x71, 0x18, 0x90, 0x93, 0x3F,
++0xE0, 0x20, 0xE0, 0x02, 0x41, 0xB7, 0x90, 0x00,
++0x02, 0xE0, 0x44, 0x02, 0xF0, 0xE4, 0x90, 0x95,
++0xB3, 0xF0, 0x90, 0x95, 0xB3, 0xE0, 0xFF, 0xC3,
++0x94, 0x05, 0x50, 0x2D, 0x12, 0xBF, 0xBA, 0x80,
++0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9,
++0xFF, 0x90, 0x93, 0x42, 0xE0, 0xFD, 0xEF, 0x5D,
++0x60, 0x0F, 0x90, 0x95, 0xB3, 0x91, 0xB0, 0x90,
++0x95, 0xB3, 0x91, 0xD0, 0x44, 0x40, 0xF0, 0x91,
++0x92, 0x90, 0x95, 0xB3, 0xE0, 0x04, 0xF0, 0x80,
++0xC9, 0x90, 0x07, 0xC7, 0xE4, 0xF0, 0x90, 0x07,
++0xC6, 0xF0, 0x90, 0x07, 0xC5, 0x74, 0x77, 0xF0,
++0x90, 0x07, 0xC4, 0xE4, 0xF0, 0x90, 0x07, 0xC0,
++0x74, 0x38, 0xF0, 0xA3, 0xE4, 0xF0, 0xA3, 0x74,
++0x0F, 0xF0, 0xA3, 0x74, 0xC0, 0xF0, 0x90, 0x02,
++0x26, 0xE0, 0x44, 0x01, 0xF0, 0xE0, 0x90, 0x95,
++0xB4, 0xF0, 0x90, 0x95, 0xB4, 0xE0, 0x30, 0xE0,
++0x18, 0x90, 0x95, 0xB2, 0xE0, 0x04, 0xB1, 0x54,
++0x90, 0x02, 0x26, 0xE0, 0x90, 0x95, 0xB4, 0xF0,
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++0xE1, 0x90, 0x02, 0x03, 0x74, 0x80, 0xF0, 0x90,
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++0xE0, 0x54, 0xEF, 0xF0, 0x90, 0x95, 0xB5, 0xE0,
++0x90, 0x04, 0x24, 0xF0, 0x90, 0xFD, 0x09, 0x74,
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++0xFF, 0x90, 0x95, 0xB4, 0xE0, 0x2F, 0xF0, 0x22,
++0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x71,
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++0x90, 0x88, 0x39, 0xE0, 0xFF, 0x60, 0x03, 0xB4,
++0x08, 0x0D, 0x91, 0xF1, 0xBF, 0x01, 0x08, 0x51,
++0xD0, 0x90, 0x01, 0xE5, 0xE0, 0x04, 0xF0, 0x22,
++0x90, 0x88, 0x31, 0xE0, 0x30, 0xE0, 0x18, 0x90,
++0x88, 0x2C, 0xE0, 0xFF, 0x30, 0xE0, 0x0E, 0xC3,
++0x13, 0x30, 0xE0, 0x07, 0xB1, 0x5C, 0xBF, 0x01,
++0x06, 0x80, 0x02, 0x80, 0x00, 0x51, 0xE0, 0x22,
++0x90, 0x97, 0x65, 0xEF, 0xF0, 0xE4, 0xA3, 0xF0,
++0xA3, 0xF0, 0x90, 0x01, 0x09, 0xE0, 0x7F, 0x00,
++0x30, 0xE7, 0x02, 0x7F, 0x01, 0x90, 0x97, 0x65,
++0xE0, 0x6F, 0x60, 0x32, 0xC3, 0x90, 0x97, 0x67,
++0xE0, 0x94, 0x88, 0x90, 0x97, 0x66, 0xE0, 0x94,
++0x13, 0x40, 0x08, 0x90, 0x01, 0xC0, 0xE0, 0x44,
++0x10, 0xF0, 0x22, 0x90, 0x97, 0x66, 0x91, 0x8B,
++0xD3, 0x90, 0x97, 0x67, 0xE0, 0x94, 0x32, 0x90,
++0x97, 0x66, 0xE0, 0x94, 0x00, 0x40, 0xC3, 0x90,
++0x01, 0xC6, 0xE0, 0x30, 0xE0, 0xBC, 0x22, 0x75,
++0x66, 0x14, 0x90, 0x88, 0x32, 0xE0, 0x44, 0x10,
++0xF0, 0x91, 0x99, 0xF0, 0x7D, 0x01, 0x12, 0x76,
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++0x2F, 0xE0, 0x30, 0xE7, 0x05, 0x74, 0x10, 0xF0,
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++0x90, 0x93, 0x3F, 0xE0, 0x30, 0xE0, 0x60, 0x90,
++0xFD, 0x09, 0xE4, 0xF0, 0x90, 0xFD, 0x08, 0xF0,
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++0x90, 0x95, 0xB2, 0xF0, 0x90, 0x95, 0xB2, 0xE0,
++0xFF, 0xC3, 0x94, 0x05, 0x50, 0x2D, 0x12, 0xBF,
++0xBA, 0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE,
++0xD8, 0xF9, 0xFF, 0x90, 0x93, 0x41, 0xE0, 0xFD,
++0xEF, 0x5D, 0x60, 0x0F, 0x90, 0x95, 0xB2, 0x91,
++0xB0, 0x90, 0x95, 0xB2, 0x91, 0xD0, 0x44, 0x20,
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++0xF0, 0x80, 0xC9, 0x90, 0x00, 0x92, 0xE0, 0x54,
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++0x02, 0xE0, 0x54, 0xFD, 0xF0, 0x80, 0x07, 0x90,
++0x00, 0x92, 0xE0, 0x44, 0x01, 0xF0, 0x90, 0x00,
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++0x02, 0x7C, 0x6A, 0xE4, 0x75, 0xF0, 0x01, 0x12,
++0x02, 0xE7, 0x7F, 0x14, 0x7E, 0x00, 0x02, 0x7C,
++0x6A, 0x90, 0x88, 0xA0, 0xE0, 0xC4, 0x13, 0x13,
++0x54, 0x01, 0xFF, 0x90, 0x88, 0xE0, 0xE0, 0xFB,
++0x90, 0x88, 0xDF, 0xE0, 0x90, 0x92, 0x90, 0x22,
++0xE0, 0xFF, 0x24, 0x4D, 0xF5, 0x82, 0xE4, 0x34,
++0x93, 0xF5, 0x83, 0xE0, 0x90, 0x01, 0xB0, 0xF0,
++0x74, 0x52, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x93,
++0xF5, 0x83, 0xE0, 0x90, 0x01, 0xB1, 0xF0, 0x22,
++0xE0, 0xFF, 0x24, 0x43, 0xF5, 0x82, 0xE4, 0x34,
++0x93, 0xF5, 0x83, 0xE0, 0x90, 0x01, 0xB2, 0xF0,
++0x74, 0x48, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x93,
++0xF5, 0x83, 0xE0, 0x90, 0x01, 0xB3, 0xF0, 0xE0,
++0x22, 0x90, 0x93, 0x3B, 0xE0, 0xC3, 0x13, 0x20,
++0xE0, 0x35, 0x90, 0x02, 0x87, 0xE0, 0x60, 0x02,
++0x80, 0x08, 0x90, 0x01, 0x00, 0xE0, 0x64, 0x3F,
++0x60, 0x05, 0x75, 0x66, 0x01, 0x80, 0x2E, 0x90,
++0x02, 0x96, 0xE0, 0x60, 0x05, 0x75, 0x66, 0x10,
++0x80, 0x23, 0x90, 0x02, 0x86, 0xE0, 0x20, 0xE1,
++0x02, 0x80, 0x07, 0x90, 0x02, 0x86, 0xE0, 0x30,
++0xE3, 0x05, 0x75, 0x66, 0x04, 0x80, 0x0E, 0x90,
++0x88, 0xE6, 0xE0, 0x30, 0xE0, 0x05, 0x75, 0x66,
++0x20, 0x80, 0x02, 0x80, 0x0F, 0x90, 0x01, 0xB9,
++0x74, 0x08, 0xF0, 0x90, 0x01, 0xB8, 0xE5, 0x66,
++0xF0, 0x7F, 0x00, 0x22, 0x90, 0x01, 0xB8, 0xE4,
++0xF0, 0x7F, 0x01, 0x22, 0xF0, 0x7F, 0x0A, 0x7E,
++0x00, 0x02, 0x7C, 0x6A, 0x90, 0x88, 0x2F, 0xE0,
++0x64, 0x02, 0x7F, 0x01, 0x60, 0x02, 0x7F, 0x00,
++0x22, 0x90, 0x01, 0x9A, 0xE0, 0x54, 0xC0, 0x44,
++0x0B, 0xB1, 0x54, 0x90, 0x01, 0x98, 0xE0, 0x54,
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++0xF5, 0x0F, 0xAF, 0x0F, 0x22, 0xD3, 0x10, 0xAF,
++0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x97, 0x6A, 0xEF,
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++0xFD, 0x90, 0x97, 0x6A, 0xE0, 0x12, 0xC2, 0x8A,
++0xE5, 0x82, 0x2D, 0x12, 0xB4, 0x7A, 0xE0, 0xFB,
++0xE4, 0xFF, 0x51, 0xD9, 0x90, 0x97, 0x6B, 0xE0,
++0x04, 0xF0, 0xE0, 0xC3, 0x94, 0x10, 0x40, 0xDC,
++0x90, 0x00, 0x8F, 0xE0, 0x30, 0xE0, 0x05, 0x90,
++0x00, 0x8D, 0xE4, 0xF0, 0xD0, 0xD0, 0x92, 0xAF,
++0x22, 0xEF, 0x70, 0x04, 0x74, 0xF0, 0x80, 0x16,
++0xEF, 0xB4, 0x01, 0x04, 0x74, 0xF4, 0x80, 0x0E,
++0xEF, 0xB4, 0x02, 0x04, 0x74, 0xF8, 0x80, 0x06,
++0xEF, 0xB4, 0x03, 0x0C, 0x74, 0xFC, 0x2D, 0xF5,
++0x82, 0xE4, 0x34, 0x02, 0xF5, 0x83, 0xEB, 0xF0,
++0x22, 0x7E, 0x00, 0x7F, 0x8E, 0x7D, 0x00, 0x7B,
++0x01, 0x7A, 0x93, 0x79, 0x58, 0x02, 0x04, 0x80,
++0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0xAD,
++0x07, 0x90, 0x05, 0x63, 0xE0, 0xFE, 0x90, 0x05,
++0x62, 0xE0, 0x7A, 0x00, 0x24, 0x00, 0xFF, 0xEA,
++0x3E, 0x90, 0x96, 0xC6, 0xF0, 0xA3, 0xEF, 0xF0,
++0x90, 0x05, 0x61, 0xE0, 0xFE, 0x90, 0x05, 0x60,
++0xE0, 0x24, 0x00, 0xFF, 0xEA, 0x3E, 0xFE, 0xED,
++0xB4, 0x08, 0x0A, 0x90, 0x05, 0x58, 0xE0, 0xFC,
++0x2F, 0xFF, 0xEA, 0x3E, 0xFE, 0x90, 0x96, 0xA3,
++0x74, 0x17, 0xF0, 0x90, 0x96, 0xC5, 0x74, 0x06,
++0xF0, 0x90, 0x96, 0xA5, 0xED, 0xF0, 0x90, 0x93,
++0x58, 0xE0, 0xFD, 0xC3, 0x13, 0x54, 0x07, 0x12,
++0x8E, 0xF7, 0xF5, 0x83, 0xE0, 0x90, 0x96, 0xA6,
++0xF0, 0xA3, 0xEF, 0xF0, 0xEE, 0xA3, 0xF0, 0x90,
++0x96, 0xC6, 0xE0, 0xFE, 0xA3, 0xE0, 0x90, 0x96,
++0xA9, 0xF0, 0xEE, 0xA3, 0xF0, 0x7B, 0x01, 0x7A,
++0x96, 0x79, 0xA3, 0x12, 0x90, 0x33, 0x7F, 0x04,
++0x12, 0x04, 0x7E, 0xD0, 0xD0, 0x92, 0xAF, 0x22,
++0x90, 0x01, 0x94, 0xE0, 0x44, 0x01, 0xF0, 0x90,
++0x01, 0xC7, 0xE4, 0xF0, 0x22, 0x90, 0x01, 0x95,
++0xE0, 0x7F, 0x00, 0x30, 0xE4, 0x02, 0x7F, 0x01,
++0x22, 0x22, 0x90, 0x93, 0x03, 0xE0, 0x30, 0xE0,
++0x0F, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0,
++0x07, 0x90, 0x04, 0x1F, 0xE0, 0x44, 0x40, 0xF0,
++0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0,
++0x90, 0x96, 0xFF, 0xEC, 0xF0, 0xA3, 0xED, 0xF0,
++0x90, 0x96, 0xFE, 0xEF, 0xF0, 0xA3, 0xA3, 0xE0,
++0xFD, 0x12, 0x7B, 0xBD, 0x90, 0x97, 0x09, 0x12,
++0x04, 0x31, 0x90, 0x97, 0x01, 0x12, 0x04, 0xB8,
++0x12, 0x03, 0xCD, 0x90, 0x97, 0x09, 0x91, 0xD5,
++0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07,
++0x90, 0x97, 0x01, 0x12, 0x04, 0xB8, 0x90, 0x97,
++0x05, 0x91, 0xD5, 0xD0, 0x03, 0xD0, 0x02, 0xD0,
++0x01, 0xD0, 0x00, 0x12, 0x86, 0x20, 0x90, 0x97,
++0x0D, 0x12, 0x04, 0x31, 0x90, 0x96, 0xFF, 0xA3,
++0xE0, 0xFD, 0xC0, 0x05, 0x90, 0x97, 0x0D, 0x12,
++0x04, 0xB8, 0x90, 0x8B, 0x9F, 0x12, 0x04, 0x31,
++0x90, 0x96, 0xFE, 0xE0, 0xFF, 0xD0, 0x05, 0x12,
++0x79, 0x53, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xFD,
++0xEE, 0x13, 0x13, 0x54, 0x07, 0xFB, 0x90, 0x93,
++0x58, 0xE0, 0xFE, 0xC4, 0x54, 0x0F, 0x90, 0x97,
++0x5B, 0xF0, 0xAF, 0x04, 0xD3, 0x10, 0xAF, 0x01,
++0xC3, 0xC0, 0xD0, 0x90, 0x97, 0x58, 0xEF, 0xF0,
++0xED, 0x64, 0x01, 0x70, 0x2E, 0xEB, 0xB4, 0x01,
++0x07, 0xE0, 0x24, 0x02, 0xF5, 0x10, 0x80, 0x08,
++0x90, 0x97, 0x58, 0xE0, 0x24, 0xFE, 0xF5, 0x10,
++0x90, 0x97, 0x01, 0x12, 0x04, 0x3D, 0x00, 0x00,
++0x00, 0xFF, 0xAF, 0x10, 0x91, 0xC6, 0x91, 0xBE,
++0x12, 0x04, 0x3D, 0x00, 0x00, 0x00, 0xFF, 0xAF,
++0x10, 0x80, 0x20, 0x90, 0x97, 0x01, 0x12, 0x04,
++0x3D, 0x00, 0x00, 0x00, 0xFF, 0x90, 0x97, 0x58,
++0x12, 0x8F, 0xE4, 0x91, 0xCA, 0x91, 0xBE, 0x12,
++0x04, 0x3D, 0x00, 0x00, 0x00, 0xFF, 0x90, 0x97,
++0x58, 0xE0, 0xFF, 0x91, 0xC6, 0x7F, 0x01, 0x71,
++0xC9, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xE4, 0xFF,
++0x71, 0xC9, 0x90, 0x97, 0x01, 0x22, 0xE4, 0xFC,
++0xFD, 0xFE, 0x90, 0x97, 0x05, 0x12, 0x04, 0x31,
++0x7D, 0x18, 0x7C, 0x00, 0x22, 0x12, 0x86, 0x2D,
++0x02, 0x86, 0x13, 0xD3, 0x10, 0xAF, 0x01, 0xC3,
++0xC0, 0xD0, 0xE4, 0xFE, 0xFD, 0xEF, 0xB4, 0x01,
++0x0D, 0xEB, 0xB4, 0x02, 0x03, 0x0D, 0x80, 0x06,
++0xEB, 0xB4, 0x01, 0x02, 0x7D, 0x02, 0xAF, 0x06,
++0xEF, 0xC4, 0x54, 0xF0, 0x4D, 0xFF, 0xD0, 0xD0,
++0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3,
++0xC0, 0xD0, 0xB1, 0x36, 0xF5, 0x83, 0xE0, 0x90,
++0x97, 0x73, 0xF0, 0xED, 0x90, 0x00, 0x73, 0x70,
++0x0D, 0xE0, 0x44, 0x04, 0xF0, 0x90, 0x00, 0x67,
++0xE0, 0x44, 0x80, 0xF0, 0x80, 0x0B, 0xE0, 0x54,
++0xFB, 0xF0, 0x90, 0x00, 0x67, 0xE0, 0x54, 0x7F,
++0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x86,
++0xAD, 0xA3, 0xE0, 0x24, 0x7F, 0xF5, 0x82, 0xE4,
++0x34, 0x84, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3,
++0xC0, 0xD0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90,
++0x88, 0xB8, 0xE0, 0x54, 0xFE, 0xF0, 0x54, 0xE1,
++0xF0, 0x90, 0x88, 0xBD, 0xE0, 0xFF, 0x12, 0x71,
++0x9A, 0x90, 0x88, 0x36, 0xE0, 0x70, 0x16, 0x90,
++0x93, 0x3B, 0xE0, 0x20, 0xE0, 0x0F, 0x90, 0x86,
++0x0C, 0x12, 0x8A, 0x65, 0x90, 0x8A, 0xF9, 0x12,
++0x90, 0x45, 0x12, 0x96, 0xDB, 0x22, 0x90, 0x95,
++0x50, 0xE0, 0xFF, 0x54, 0x03, 0x70, 0x11, 0xEF,
++0x13, 0x13, 0x54, 0x3F, 0xFF, 0xA3, 0xE0, 0xC3,
++0x9F, 0x40, 0x59, 0xE4, 0x90, 0x95, 0x51, 0xF0,
++0x90, 0x88, 0x9D, 0xE0, 0x30, 0xE0, 0x4D, 0xA3,
++0x12, 0x96, 0xE1, 0x90, 0x88, 0xB0, 0x74, 0x01,
++0xF0, 0xE4, 0x90, 0x88, 0xA5, 0xF0, 0x90, 0x88,
++0xB2, 0xF0, 0xA3, 0xF0, 0x90, 0x88, 0xAF, 0x04,
++0xF0, 0x90, 0x88, 0x9C, 0xE0, 0x60, 0x0D, 0x90,
++0x8A, 0xF9, 0x12, 0x90, 0x45, 0x7D, 0x05, 0x7F,
++0x6F, 0x02, 0x04, 0x7E, 0x90, 0x8A, 0xF9, 0x12,
++0x90, 0x45, 0x12, 0x96, 0xDB, 0x90, 0x88, 0x9D,
++0x12, 0xA7, 0xD7, 0x20, 0xE0, 0x0E, 0xEF, 0x13,
++0x13, 0x54, 0x3F, 0x30, 0xE0, 0x06, 0x90, 0x8A,
++0xE1, 0x12, 0x8A, 0x65, 0x22, 0x90, 0x97, 0x74,
++0xEF, 0xF0, 0x90, 0x88, 0xB8, 0xE0, 0x44, 0x01,
++0xF0, 0x90, 0x8A, 0xF9, 0x12, 0x90, 0x45, 0x7D,
++0x11, 0x12, 0xA4, 0x96, 0x12, 0x8A, 0x65, 0x90,
++0x07, 0x78, 0xE0, 0x90, 0x88, 0xBD, 0xF0, 0x90,
++0x97, 0x74, 0xE0, 0xFD, 0x70, 0x02, 0x80, 0x1C,
++0xED, 0xB4, 0x01, 0x06, 0xD1, 0x38, 0x44, 0x20,
++0xF0, 0x22, 0x90, 0x97, 0x74, 0xE0, 0xFD, 0xB4,
++0x02, 0x06, 0xD1, 0x38, 0x44, 0x60, 0xF0, 0x22,
++0xED, 0xB4, 0x03, 0x03, 0xD1, 0x38, 0xF0, 0x22,
++0x90, 0x88, 0xB8, 0xE0, 0x54, 0x1F, 0x22, 0x90,
++0x88, 0x9D, 0xE0, 0x20, 0xE0, 0x02, 0xE1, 0x11,
++0x90, 0x8A, 0xB1, 0x12, 0x8A, 0x65, 0x90, 0x88,
++0xB0, 0xE0, 0xFF, 0xB4, 0x01, 0x02, 0x80, 0x22,
++0x90, 0x88, 0xB0, 0xE0, 0xFF, 0xB4, 0x02, 0x05,
++0x90, 0x8A, 0xC1, 0x80, 0x18, 0x90, 0x88, 0xB0,
++0xE0, 0xFF, 0xB4, 0x03, 0x05, 0x90, 0x8A, 0xBB,
++0x80, 0x0B, 0x90, 0x88, 0xB0, 0xE0, 0xFF, 0xB4,
++0x04, 0x09, 0x90, 0x8A, 0xBD, 0x12, 0xBF, 0xAD,
++0x02, 0x04, 0x7E, 0x90, 0x88, 0xB0, 0xE0, 0xFF,
++0x64, 0x05, 0x60, 0x02, 0xE1, 0x11, 0x90, 0x95,
++0x4C, 0xE0, 0x20, 0xE0, 0x6F, 0x90, 0x88, 0x9D,
++0xE0, 0xFE, 0xC4, 0x54, 0x0F, 0x20, 0xE0, 0x0A,
++0xEE, 0xC4, 0x13, 0x54, 0x07, 0x30, 0xE0, 0x02,
++0x80, 0x5A, 0xF1, 0x12, 0x70, 0x0E, 0x90, 0x01,
++0x34, 0x74, 0x08, 0xF0, 0xFD, 0xE4, 0xFF, 0x12,
++0x7C, 0x74, 0x80, 0x16, 0x90, 0x95, 0x4D, 0xE0,
++0x60, 0x30, 0xF1, 0x12, 0xC3, 0x94, 0x05, 0x50,
++0x29, 0xE4, 0xA3, 0xF0, 0x90, 0x95, 0x4F, 0xE0,
++0x04, 0xF0, 0x90, 0x8A, 0xD1, 0x12, 0x90, 0x45,
++0x7F, 0x05, 0x12, 0x04, 0x7E, 0x90, 0x95, 0x4C,
++0xE0, 0xFF, 0xC3, 0x13, 0xFE, 0xEF, 0x54, 0x01,
++0xFF, 0xEE, 0x04, 0x54, 0x7F, 0x25, 0xE0, 0x4F,
++0xF0, 0x22, 0x7D, 0x08, 0xE4, 0xFF, 0x12, 0x7C,
++0x7E, 0x90, 0x01, 0x34, 0x74, 0x08, 0xF0, 0x90,
++0x88, 0xB0, 0xE0, 0xFF, 0x90, 0x8A, 0xC1, 0x12,
++0x96, 0xE6, 0x90, 0x95, 0x4C, 0xE0, 0x54, 0x01,
++0xF0, 0x22, 0x90, 0x95, 0x4C, 0xE0, 0xC3, 0x13,
++0x54, 0x7F, 0x22, 0x90, 0x24, 0xA0, 0xE0, 0x90,
++0x93, 0x03, 0x30, 0xE7, 0x05, 0xE0, 0x44, 0x02,
++0xF0, 0x22, 0xE0, 0x54, 0xFD, 0xF0, 0x22, 0xAE,
++0x07, 0x12, 0x9E, 0x4C, 0xBF, 0x01, 0x16, 0x90,
++0x88, 0x2C, 0x12, 0x97, 0xC0, 0x20, 0xE0, 0x0D,
++0xAF, 0x06, 0x12, 0x97, 0xA8, 0x7D, 0x01, 0x12,
++0x04, 0x7E, 0x7F, 0x01, 0x22, 0x7F, 0x00, 0x22,
++0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90,
++0x88, 0x9D, 0xE0, 0x30, 0xE0, 0x1E, 0x90, 0x88,
++0xAF, 0xE0, 0x60, 0x05, 0x75, 0x12, 0x40, 0xE1,
++0xFA, 0x90, 0x88, 0x38, 0xE0, 0xD3, 0x94, 0x00,
++0x40, 0x02, 0x80, 0x2D, 0x90, 0x88, 0x9C, 0xE0,
++0x60, 0x7B, 0x80, 0x55, 0x12, 0x7A, 0x65, 0xEF,
++0x64, 0x01, 0x60, 0x05, 0x75, 0x12, 0x01, 0x80,
++0x71, 0x90, 0x88, 0x3A, 0xE0, 0xFF, 0x54, 0x03,
++0x60, 0x05, 0x75, 0x12, 0x02, 0x80, 0x63, 0x90,
++0x88, 0x38, 0xE0, 0xFE, 0xE4, 0xC3, 0x9E, 0x50,
++0x05, 0x75, 0x12, 0x04, 0x80, 0x54, 0xEF, 0x30,
++0xE2, 0x05, 0x75, 0x12, 0x08, 0x80, 0x4B, 0x90,
++0x88, 0x3A, 0xE0, 0x30, 0xE4, 0x05, 0x75, 0x12,
++0x10, 0x80, 0x3F, 0x90, 0x88, 0x32, 0xE0, 0x13,
++0x13, 0x54, 0x3F, 0x20, 0xE0, 0x05, 0x75, 0x12,
++0x20, 0x80, 0x2F, 0x90, 0x88, 0x9C, 0xE0, 0x60,
++0x05, 0x75, 0x12, 0x80, 0x80, 0x24, 0x90, 0x06,
++0x62, 0xE0, 0x30, 0xE1, 0x05, 0x75, 0x12, 0x11,
++0x80, 0x18, 0x90, 0x06, 0x62, 0xE0, 0x30, 0xE0,
++0x0C, 0xE0, 0x54, 0xFC, 0xFF, 0xBF, 0x80, 0x05,
++0x75, 0x12, 0x12, 0x80, 0x05, 0x12, 0xDD, 0x4C,
++0x80, 0x0E, 0x90, 0x01, 0xB9, 0x74, 0x04, 0xF0,
++0x90, 0x01, 0xB8, 0xE5, 0x12, 0xF0, 0x7F, 0x00,
++0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x88, 0x8D,
++0x74, 0x18, 0xF0, 0xA3, 0xF0, 0xA3, 0xE4, 0xF0,
++0xA3, 0x74, 0x64, 0xF0, 0xA3, 0x74, 0x05, 0xF0,
++0xA3, 0xF0, 0x22, 0x12, 0xA7, 0x9E, 0x40, 0x41,
++0x90, 0x88, 0x50, 0xE0, 0x04, 0xF0, 0x90, 0x88,
++0x92, 0xE0, 0xFF, 0x90, 0x88, 0x50, 0xE0, 0xD3,
++0x9F, 0x50, 0x2E, 0x90, 0x88, 0x48, 0xE0, 0x24,
++0x08, 0xF0, 0x90, 0x88, 0x3F, 0x12, 0x9D, 0xC9,
++0x33, 0x33, 0x33, 0x54, 0xF8, 0xFF, 0x90, 0x88,
++0x3E, 0xE0, 0x2F, 0x90, 0x88, 0x4F, 0xF0, 0xFB,
++0x90, 0x88, 0x48, 0xE0, 0xFF, 0xA3, 0xE0, 0xFD,
++0x90, 0x92, 0x98, 0x74, 0x03, 0xF0, 0x12, 0x6E,
++0x2F, 0x22, 0x90, 0x86, 0xB6, 0xE0, 0xFF, 0x90,
++0x97, 0x44, 0xE0, 0xFB, 0x90, 0x92, 0x13, 0x74,
++0x0A, 0xF0, 0x7D, 0x01, 0x12, 0x66, 0xDB, 0x90,
++0x97, 0x45, 0xEE, 0xF0, 0xFC, 0xA3, 0xEF, 0xF0,
++0xFD, 0x90, 0x97, 0x43, 0xE0, 0xFF, 0x90, 0x8A,
++0x95, 0xE0, 0xFA, 0xA3, 0xE0, 0xFB, 0xF5, 0x82,
++0x8A, 0x83, 0x02, 0x04, 0x7E, 0x90, 0x97, 0x36,
++0xA3, 0xE0, 0xFF, 0x90, 0x92, 0x13, 0x74, 0x03,
++0xF0, 0x7B, 0x06, 0x7D, 0x01, 0x12, 0x66, 0xDB,
++0x90, 0x97, 0x3A, 0xEE, 0xF0, 0xFC, 0xA3, 0xEF,
++0xF0, 0xFD, 0x90, 0x97, 0x39, 0xE0, 0xFF, 0x74,
++0x10, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5,
++0x83, 0xEF, 0xF0, 0x90, 0x97, 0x38, 0x22, 0x90,
++0x05, 0x63, 0xE0, 0x90, 0x88, 0x89, 0xF0, 0x90,
++0x05, 0x62, 0xE0, 0x90, 0x88, 0x8A, 0xF0, 0x90,
++0x05, 0x61, 0xE0, 0x90, 0x88, 0x8B, 0xF0, 0x90,
++0x05, 0x60, 0xE0, 0x90, 0x88, 0x8C, 0xF0, 0x90,
++0x88, 0x32, 0xE0, 0x44, 0x80, 0x22, 0xE0, 0xFE,
++0xA3, 0xE0, 0xFF, 0xC3, 0x74, 0xFF, 0x9F, 0xFF,
++0x74, 0xFF, 0x9E, 0xFE, 0xE5, 0x67, 0x25, 0xE0,
++0x22, 0x90, 0x88, 0x48, 0xE0, 0xFF, 0xA3, 0xE0,
++0xFD, 0x90, 0x88, 0x4F, 0xE0, 0xFB, 0x90, 0x92,
++0x98, 0x22, 0xF5, 0x83, 0xE0, 0xFC, 0xA3, 0xE0,
++0xFD, 0xD3, 0x9F, 0xEC, 0x9E, 0x22, 0xE0, 0xFE,
++0xA3, 0xE0, 0xFF, 0xED, 0x2F, 0xFF, 0xEC, 0x3E,
++0xFE, 0x22, 0x90, 0x88, 0xA1, 0xE0, 0xC4, 0x13,
++0x54, 0x07, 0x22, 0xE0, 0x54, 0xFE, 0x4E, 0xFE,
++0xF0, 0xEF, 0x54, 0x02, 0xFF, 0xEE, 0x54, 0xFD,
++0x22, 0x7E, 0x00, 0x7F, 0x04, 0x7D, 0x00, 0x7B,
++0x01, 0x7A, 0x93, 0x79, 0x3B, 0x22, 0x75, 0xF0,
++0x02, 0xA4, 0xF5, 0x82, 0x85, 0xF0, 0x83, 0x02,
++0x03, 0x3E, 0x90, 0x97, 0x45, 0xE0, 0xFE, 0xA3,
++0xE0, 0xFF, 0x90, 0x8A, 0x9B, 0x22, 0x90, 0x93,
++0xD7, 0xE0, 0xFF, 0x90, 0x93, 0xDA, 0xE0, 0xD3,
++0x9F, 0x22, 0xE5, 0x67, 0x25, 0xE0, 0x24, 0x86,
++0xF5, 0x82, 0xE4, 0x34, 0x8E, 0x22, 0x74, 0xB6,
++0x25, 0x67, 0xF5, 0x82, 0xE4, 0x34, 0x8D, 0xF5,
++0x83, 0x22, 0xFF, 0xE4, 0x3E, 0xFE, 0xE4, 0x3D,
++0xFD, 0xE4, 0x3C, 0xFC, 0x22, 0x90, 0x93, 0xF4,
++0xE0, 0xFF, 0x90, 0x93, 0xF3, 0xE0, 0x4F, 0x22,
++0x25, 0xE0, 0x24, 0x75, 0xF5, 0x82, 0xE4, 0x34,
++0x8D, 0x22, 0x90, 0x95, 0x44, 0xE0, 0xFE, 0x13,
++0x13, 0x54, 0x3F, 0x22, 0x90, 0x00, 0x02, 0x02,
++0x03, 0x3E, 0x90, 0x00, 0x04, 0x02, 0x03, 0x3E,
++0x90, 0x04, 0x1F, 0x74, 0x20, 0xF0, 0x7F, 0x01,
++0x22, 0x90, 0x97, 0x43, 0xE0, 0xFF, 0x90, 0x8A,
++0xC7, 0x22, 0x90, 0x95, 0x57, 0xE0, 0xFF, 0xC3,
++0x94, 0x05, 0x22, 0x24, 0x06, 0xF5, 0x82, 0xE4,
++0x34, 0x8E, 0x22, 0x24, 0x26, 0xF5, 0x82, 0xE4,
++0x34, 0x8E, 0x22, 0x24, 0x56, 0xF5, 0x82, 0xE4,
++0x34, 0x8E, 0x22, 0x90, 0x06, 0x04, 0xE0, 0x54,
++0x7F, 0xF0, 0x22, 0x7D, 0x00, 0x25, 0xE0, 0x25,
++0xE0, 0xFC, 0x22, 0x90, 0x88, 0xA3, 0xE0, 0x54,
++0xDF, 0xF0, 0x22, 0x90, 0x95, 0xE1, 0xE0, 0xFE,
++0xA3, 0xE0, 0x22, 0x90, 0x88, 0x31, 0xE0, 0x54,
++0xF7, 0xF0, 0x22, 0xF5, 0x46, 0x89, 0x47, 0x75,
++0x48, 0x04, 0x22, 0x00, 0x89, 0xFC
++};
++
++u32 array_length_mp_8723d_fw_nic = 29262;
++
++#ifdef CONFIG_WOWLAN
++
++u8 array_mp_8723d_fw_wowlan[] = {
++0xD1, 0x23, 0x30, 0x00, 0x31, 0x00, 0x00, 0x00,
++0x11, 0x18, 0x20, 0x42, 0xEC, 0x7B, 0x02, 0x00,
++0x72, 0xB6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x02, 0x86, 0xA9, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0xB6, 0xA6, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0xDF, 0x42, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0xD9, 0xD1, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0xDA, 0x77, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x02, 0xBF, 0xF9, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF,
++0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0xEF, 0x2B, 0xFF, 0xEE, 0x3A, 0xFE, 0xED, 0x39,
++0xFD, 0xEC, 0x38, 0xFC, 0x22, 0xC3, 0xEF, 0x9B,
++0xFF, 0xEE, 0x9A, 0xFE, 0xED, 0x99, 0xFD, 0xEC,
++0x98, 0xFC, 0x22, 0xE8, 0x8F, 0xF0, 0xA4, 0xCC,
++0x8B, 0xF0, 0xA4, 0x2C, 0xFC, 0xE9, 0x8E, 0xF0,
++0xA4, 0x2C, 0xFC, 0x8A, 0xF0, 0xED, 0xA4, 0x2C,
++0xFC, 0xEA, 0x8E, 0xF0, 0xA4, 0xCD, 0xA8, 0xF0,
++0x8B, 0xF0, 0xA4, 0x2D, 0xCC, 0x38, 0x25, 0xF0,
++0xFD, 0xE9, 0x8F, 0xF0, 0xA4, 0x2C, 0xCD, 0x35,
++0xF0, 0xFC, 0xEB, 0x8E, 0xF0, 0xA4, 0xFE, 0xA9,
++0xF0, 0xEB, 0x8F, 0xF0, 0xA4, 0xCF, 0xC5, 0xF0,
++0x2E, 0xCD, 0x39, 0xFE, 0xE4, 0x3C, 0xFC, 0xEA,
++0xA4, 0x2D, 0xCE, 0x35, 0xF0, 0xFD, 0xE4, 0x3C,
++0xFC, 0x22, 0x75, 0xF0, 0x08, 0x75, 0x82, 0x00,
++0xEF, 0x2F, 0xFF, 0xEE, 0x33, 0xFE, 0xCD, 0x33,
++0xCD, 0xCC, 0x33, 0xCC, 0xC5, 0x82, 0x33, 0xC5,
++0x82, 0x9B, 0xED, 0x9A, 0xEC, 0x99, 0xE5, 0x82,
++0x98, 0x40, 0x0C, 0xF5, 0x82, 0xEE, 0x9B, 0xFE,
++0xED, 0x9A, 0xFD, 0xEC, 0x99, 0xFC, 0x0F, 0xD5,
++0xF0, 0xD6, 0xE4, 0xCE, 0xFB, 0xE4, 0xCD, 0xFA,
++0xE4, 0xCC, 0xF9, 0xA8, 0x82, 0x22, 0xB8, 0x00,
++0xC1, 0xB9, 0x00, 0x59, 0xBA, 0x00, 0x2D, 0xEC,
++0x8B, 0xF0, 0x84, 0xCF, 0xCE, 0xCD, 0xFC, 0xE5,
++0xF0, 0xCB, 0xF9, 0x78, 0x18, 0xEF, 0x2F, 0xFF,
++0xEE, 0x33, 0xFE, 0xED, 0x33, 0xFD, 0xEC, 0x33,
++0xFC, 0xEB, 0x33, 0xFB, 0x10, 0xD7, 0x03, 0x99,
++0x40, 0x04, 0xEB, 0x99, 0xFB, 0x0F, 0xD8, 0xE5,
++0xE4, 0xF9, 0xFA, 0x22, 0x78, 0x18, 0xEF, 0x2F,
++0xFF, 0xEE, 0x33, 0xFE, 0xED, 0x33, 0xFD, 0xEC,
++0x33, 0xFC, 0xC9, 0x33, 0xC9, 0x10, 0xD7, 0x05,
++0x9B, 0xE9, 0x9A, 0x40, 0x07, 0xEC, 0x9B, 0xFC,
++0xE9, 0x9A, 0xF9, 0x0F, 0xD8, 0xE0, 0xE4, 0xC9,
++0xFA, 0xE4, 0xCC, 0xFB, 0x22, 0x75, 0xF0, 0x10,
++0xEF, 0x2F, 0xFF, 0xEE, 0x33, 0xFE, 0xED, 0x33,
++0xFD, 0xCC, 0x33, 0xCC, 0xC8, 0x33, 0xC8, 0x10,
++0xD7, 0x07, 0x9B, 0xEC, 0x9A, 0xE8, 0x99, 0x40,
++0x0A, 0xED, 0x9B, 0xFD, 0xEC, 0x9A, 0xFC, 0xE8,
++0x99, 0xF8, 0x0F, 0xD5, 0xF0, 0xDA, 0xE4, 0xCD,
++0xFB, 0xE4, 0xCC, 0xFA, 0xE4, 0xC8, 0xF9, 0x22,
++0xEF, 0x5B, 0xFF, 0xEE, 0x5A, 0xFE, 0xED, 0x59,
++0xFD, 0xEC, 0x58, 0xFC, 0x22, 0xEF, 0x4B, 0xFF,
++0xEE, 0x4A, 0xFE, 0xED, 0x49, 0xFD, 0xEC, 0x48,
++0xFC, 0x22, 0xE0, 0xF8, 0xA3, 0xE0, 0xF9, 0xA3,
++0xE0, 0xFA, 0xA3, 0xE0, 0xFB, 0x22, 0xE0, 0xFB,
++0xA3, 0xE0, 0xFA, 0xA3, 0xE0, 0xF9, 0x22, 0xEB,
++0xF0, 0xA3, 0xEA, 0xF0, 0xA3, 0xE9, 0xF0, 0x22,
++0xD0, 0x83, 0xD0, 0x82, 0xF8, 0xE4, 0x93, 0x70,
++0x12, 0x74, 0x01, 0x93, 0x70, 0x0D, 0xA3, 0xA3,
++0x93, 0xF8, 0x74, 0x01, 0x93, 0xF5, 0x82, 0x88,
++0x83, 0xE4, 0x73, 0x74, 0x02, 0x93, 0x68, 0x60,
++0xEF, 0xA3, 0xA3, 0xA3, 0x80, 0xDF, 0xE3, 0xF5,
++0xF0, 0x09, 0xE2, 0x08, 0xB5, 0xF0, 0x6B, 0xDF,
++0xF5, 0x80, 0x67, 0xE3, 0xF5, 0xF0, 0x09, 0xE6,
++0x08, 0xB5, 0xF0, 0x5E, 0xDF, 0xF5, 0x80, 0x5A,
++0x87, 0xF0, 0x09, 0xE6, 0x08, 0xB5, 0xF0, 0x52,
++0xDF, 0xF6, 0x80, 0x4E, 0x87, 0xF0, 0x09, 0xE2,
++0x08, 0xB5, 0xF0, 0x46, 0xDF, 0xF6, 0x80, 0x42,
++0x88, 0x82, 0x8C, 0x83, 0x87, 0xF0, 0x09, 0xE0,
++0xA3, 0xB5, 0xF0, 0x36, 0xDF, 0xF6, 0x80, 0x32,
++0x88, 0x82, 0x8C, 0x83, 0x87, 0xF0, 0x09, 0xE4,
++0x93, 0xA3, 0xB5, 0xF0, 0x25, 0xDF, 0xF5, 0x80,
++0x21, 0x88, 0x82, 0x8C, 0x83, 0xE3, 0xF5, 0xF0,
++0x09, 0xE0, 0xA3, 0xB5, 0xF0, 0x14, 0xDF, 0xF5,
++0x80, 0x10, 0x88, 0x82, 0x8C, 0x83, 0xE3, 0xF5,
++0xF0, 0x09, 0xE4, 0x93, 0xA3, 0xB5, 0xF0, 0x02,
++0xDF, 0xF4, 0x02, 0x83, 0x85, 0x80, 0x87, 0x80,
++0xE9, 0x80, 0x90, 0x80, 0xD4, 0x80, 0x3E, 0x80,
++0x15, 0x80, 0x6E, 0x80, 0x7E, 0x80, 0x9D, 0x80,
++0xB7, 0x80, 0x8D, 0x80, 0xA3, 0x80, 0x51, 0x80,
++0x74, 0x80, 0x3C, 0x02, 0x83, 0x91, 0x89, 0x82,
++0x8A, 0x83, 0xEC, 0xFA, 0xE4, 0x93, 0xF5, 0xF0,
++0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83,
++0xCC, 0xE4, 0x93, 0xA3, 0xC8, 0xC5, 0x82, 0xC8,
++0xCC, 0xC5, 0x83, 0xCC, 0xB5, 0xF0, 0x76, 0xDF,
++0xE3, 0xDE, 0xE1, 0x80, 0x70, 0x89, 0x82, 0x8A,
++0x83, 0xE4, 0x93, 0xF5, 0xF0, 0xA3, 0xE2, 0x08,
++0xB5, 0xF0, 0x62, 0xDF, 0xF4, 0x80, 0x5E, 0x89,
++0x82, 0x8A, 0x83, 0xE0, 0xF5, 0xF0, 0xA3, 0xE6,
++0x08, 0xB5, 0xF0, 0x51, 0xDF, 0xF5, 0x80, 0x4D,
++0x89, 0x82, 0x8A, 0x83, 0xE0, 0xF5, 0xF0, 0xA3,
++0xE2, 0x08, 0xB5, 0xF0, 0x40, 0xDF, 0xF5, 0x80,
++0x3C, 0x89, 0x82, 0x8A, 0x83, 0xE4, 0x93, 0xF5,
++0xF0, 0xA3, 0xE6, 0x08, 0xB5, 0xF0, 0x2E, 0xDF,
++0xF4, 0x80, 0x2A, 0x80, 0x02, 0x80, 0x57, 0x89,
++0x82, 0x8A, 0x83, 0xEC, 0xFA, 0xE4, 0x93, 0xF5,
++0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5,
++0x83, 0xCC, 0xE0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8,
++0xCC, 0xC5, 0x83, 0xCC, 0xB5, 0xF0, 0x06, 0xDF,
++0xE4, 0xDE, 0xE2, 0x80, 0x00, 0x7F, 0xFF, 0xB5,
++0xF0, 0x02, 0x0F, 0x22, 0x40, 0x02, 0x7F, 0x01,
++0x22, 0x89, 0x82, 0x8A, 0x83, 0xEC, 0xFA, 0xE0,
++0xF5, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC,
++0xC5, 0x83, 0xCC, 0xE0, 0xA3, 0xC8, 0xC5, 0x82,
++0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xB5, 0xF0, 0xD5,
++0xDF, 0xE5, 0xDE, 0xE3, 0x80, 0xCF, 0x89, 0x82,
++0x8A, 0x83, 0xEC, 0xFA, 0xE0, 0xF5, 0xF0, 0xA3,
++0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC,
++0xE4, 0x93, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC,
++0xC5, 0x83, 0xCC, 0xB5, 0xF0, 0xAF, 0xDF, 0xE4,
++0xDE, 0xE2, 0x80, 0xA9, 0x88, 0xF0, 0xEF, 0x60,
++0x01, 0x0E, 0x4E, 0x60, 0xAB, 0xED, 0x24, 0x02,
++0xB4, 0x04, 0x00, 0x50, 0x98, 0xF5, 0x82, 0xEB,
++0x24, 0x02, 0xB4, 0x04, 0x00, 0x50, 0x8E, 0x23,
++0x23, 0x45, 0x82, 0x23, 0x90, 0x82, 0xCD, 0x73,
++0xC2, 0xAF, 0x80, 0xFE, 0x32, 0x12, 0x84, 0x04,
++0x85, 0xD0, 0x0B, 0x75, 0xD0, 0x08, 0xAA, 0xE0,
++0xC2, 0x8C, 0xE5, 0x8A, 0x24, 0x67, 0xF5, 0x8A,
++0xE5, 0x8C, 0x34, 0x79, 0xF5, 0x8C, 0xD2, 0x8C,
++0xEC, 0x24, 0x87, 0xF8, 0xE6, 0xBC, 0x02, 0x02,
++0x74, 0xFF, 0xC3, 0x95, 0x81, 0xB4, 0x40, 0x00,
++0x40, 0xCE, 0x79, 0x03, 0x78, 0x80, 0x16, 0xE6,
++0x08, 0x70, 0x0B, 0xC2, 0xAF, 0xE6, 0x30, 0xE1,
++0x03, 0x44, 0x18, 0xF6, 0xD2, 0xAF, 0x08, 0xD9,
++0xED, 0xEA, 0x8B, 0xD0, 0x22, 0xE5, 0x0C, 0xFF,
++0x23, 0x24, 0x81, 0xF8, 0x0F, 0x08, 0x08, 0xBF,
++0x03, 0x04, 0x7F, 0x00, 0x78, 0x81, 0xE6, 0x30,
++0xE4, 0xF2, 0x00, 0xE5, 0x0C, 0xC3, 0x9F, 0x50,
++0x20, 0x05, 0x0C, 0x74, 0x86, 0x25, 0x0C, 0xF8,
++0xE6, 0xFD, 0xA6, 0x81, 0x08, 0xE6, 0xAE, 0x0C,
++0xBE, 0x02, 0x02, 0x74, 0xFF, 0xCD, 0xF8, 0xE8,
++0x6D, 0x60, 0xE0, 0x08, 0xE6, 0xC0, 0xE0, 0x80,
++0xF6, 0xE5, 0x0C, 0xD3, 0x9F, 0x40, 0x27, 0xE5,
++0x0C, 0x24, 0x87, 0xF8, 0xE6, 0xAE, 0x0C, 0xBE,
++0x02, 0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xCD,
++0xF8, 0xE5, 0x81, 0x6D, 0x60, 0x06, 0xD0, 0xE0,
++0xF6, 0x18, 0x80, 0xF5, 0xE5, 0x0C, 0x24, 0x86,
++0xC8, 0xF6, 0x15, 0x0C, 0x80, 0xD3, 0xE5, 0x0C,
++0x23, 0x24, 0x81, 0xF8, 0x7F, 0x04, 0xC2, 0xAF,
++0xE6, 0x30, 0xE0, 0x03, 0x10, 0xE2, 0x0C, 0x7F,
++0x00, 0x30, 0xE1, 0x07, 0x30, 0xE3, 0x04, 0x7F,
++0x08, 0x54, 0xF4, 0x54, 0x7C, 0xC6, 0xD2, 0xAF,
++0x54, 0x80, 0x42, 0x07, 0x22, 0x78, 0x86, 0xA6,
++0x81, 0x74, 0x02, 0x60, 0x06, 0xFF, 0x08, 0x76,
++0xFF, 0xDF, 0xFB, 0x7F, 0x03, 0xE4, 0x78, 0x80,
++0xF6, 0x08, 0xF6, 0x08, 0xDF, 0xFA, 0x78, 0x81,
++0x76, 0x30, 0x90, 0x87, 0x44, 0x74, 0x01, 0x93,
++0xC0, 0xE0, 0xE4, 0x93, 0xC0, 0xE0, 0x43, 0x89,
++0x01, 0x75, 0x8A, 0x60, 0x75, 0x8C, 0x79, 0xD2,
++0x8C, 0xD2, 0xAF, 0x22, 0x02, 0xEF, 0xD3, 0x94,
++0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0x74, 0x81,
++0x2F, 0x2F, 0xF8, 0xE6, 0x20, 0xE5, 0xF4, 0xC2,
++0xAF, 0xE6, 0x44, 0x30, 0xF6, 0xD2, 0xAF, 0xAE,
++0x0C, 0xEE, 0xC3, 0x9F, 0x50, 0x21, 0x0E, 0x74,
++0x86, 0x2E, 0xF8, 0xE6, 0xF9, 0x08, 0xE6, 0x18,
++0xBE, 0x02, 0x02, 0x74, 0xFF, 0xFD, 0xED, 0x69,
++0x60, 0x09, 0x09, 0xE7, 0x19, 0x19, 0xF7, 0x09,
++0x09, 0x80, 0xF3, 0x16, 0x16, 0x80, 0xDA, 0xEE,
++0xD3, 0x9F, 0x40, 0x04, 0x05, 0x81, 0x05, 0x81,
++0xEE, 0xD3, 0x9F, 0x40, 0x22, 0x74, 0x86, 0x2E,
++0xF8, 0x08, 0xE6, 0xF9, 0xEE, 0xB5, 0x0C, 0x02,
++0xA9, 0x81, 0x18, 0x06, 0x06, 0xE6, 0xFD, 0xED,
++0x69, 0x60, 0x09, 0x19, 0x19, 0xE7, 0x09, 0x09,
++0xF7, 0x19, 0x80, 0xF3, 0x1E, 0x80, 0xD9, 0xEF,
++0x24, 0x86, 0xF8, 0xE6, 0x04, 0xF8, 0xEF, 0x2F,
++0x04, 0x90, 0x87, 0x44, 0x93, 0xF6, 0x08, 0xEF,
++0x2F, 0x93, 0xF6, 0x7F, 0x00, 0x22, 0xEF, 0xD3,
++0x94, 0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0xEF,
++0x23, 0x24, 0x81, 0xF8, 0xE6, 0x30, 0xE5, 0xF4,
++0xC2, 0xAF, 0xE6, 0x54, 0x8C, 0xF6, 0xD2, 0xAF,
++0xE5, 0x0C, 0xB5, 0x07, 0x0A, 0x74, 0x86, 0x2F,
++0xF8, 0xE6, 0xF5, 0x81, 0x02, 0x84, 0x4D, 0x50,
++0x2E, 0x74, 0x87, 0x2F, 0xF8, 0xE6, 0xBF, 0x02,
++0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xF9, 0x74,
++0x86, 0x2F, 0xF8, 0xFB, 0xE6, 0xFC, 0xE9, 0x6C,
++0x60, 0x08, 0xA8, 0x05, 0xE7, 0xF6, 0x1D, 0x19,
++0x80, 0xF4, 0xA8, 0x03, 0xA6, 0x05, 0x1F, 0xE5,
++0x0C, 0xB5, 0x07, 0xE3, 0x7F, 0x00, 0x22, 0x74,
++0x87, 0x2F, 0xF8, 0xE6, 0xFD, 0x18, 0x86, 0x01,
++0x0F, 0x74, 0x86, 0x2F, 0xF8, 0xA6, 0x01, 0x08,
++0x86, 0x04, 0xE5, 0x0C, 0xB5, 0x07, 0x02, 0xAC,
++0x81, 0xED, 0x6C, 0x60, 0x08, 0x0D, 0x09, 0xA8,
++0x05, 0xE6, 0xF7, 0x80, 0xF4, 0xE5, 0x0C, 0xB5,
++0x07, 0xDE, 0x89, 0x81, 0x7F, 0x00, 0x22, 0xEF,
++0xD3, 0x94, 0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22,
++0xEF, 0x23, 0x24, 0x81, 0xF8, 0xC2, 0xAF, 0xE6,
++0x30, 0xE5, 0x05, 0x30, 0xE0, 0x02, 0xD2, 0xE4,
++0xD2, 0xE2, 0xC6, 0xD2, 0xAF, 0x7F, 0x00, 0x30,
++0xE2, 0x01, 0x0F, 0x02, 0x84, 0x4C, 0x8F, 0xF0,
++0xE4, 0xFF, 0xFE, 0xE5, 0x0C, 0x23, 0x24, 0x80,
++0xF8, 0xC2, 0xA9, 0x30, 0xF7, 0x0D, 0x7F, 0x08,
++0xE6, 0x60, 0x0B, 0x2D, 0xF6, 0x60, 0x30, 0x50,
++0x2E, 0x80, 0x07, 0x30, 0xF1, 0x06, 0xED, 0xF6,
++0x60, 0x25, 0x7E, 0x02, 0x08, 0x30, 0xF0, 0x10,
++0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x23, 0x0E, 0x30,
++0xE2, 0x0C, 0xD2, 0xAF, 0x7F, 0x04, 0x80, 0x12,
++0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x13, 0x54, 0xEC,
++0x4E, 0xF6, 0xD2, 0xAF, 0x02, 0x84, 0x4D, 0x7F,
++0x08, 0x08, 0xEF, 0x44, 0x83, 0xF4, 0xC2, 0xAF,
++0x56, 0xC6, 0xD2, 0xAF, 0x54, 0x80, 0x4F, 0xFF,
++0x22, 0x02, 0x86, 0xE7, 0x02, 0x84, 0xDD, 0xE4,
++0x93, 0xA3, 0xF8, 0xE4, 0x93, 0xA3, 0x40, 0x03,
++0xF6, 0x80, 0x01, 0xF2, 0x08, 0xDF, 0xF4, 0x80,
++0x29, 0xE4, 0x93, 0xA3, 0xF8, 0x54, 0x07, 0x24,
++0x0C, 0xC8, 0xC3, 0x33, 0xC4, 0x54, 0x0F, 0x44,
++0x20, 0xC8, 0x83, 0x40, 0x04, 0xF4, 0x56, 0x80,
++0x01, 0x46, 0xF6, 0xDF, 0xE4, 0x80, 0x0B, 0x01,
++0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x90,
++0x87, 0x2C, 0xE4, 0x7E, 0x01, 0x93, 0x60, 0xBC,
++0xA3, 0xFF, 0x54, 0x3F, 0x30, 0xE5, 0x09, 0x54,
++0x1F, 0xFE, 0xE4, 0x93, 0xA3, 0x60, 0x01, 0x0E,
++0xCF, 0x54, 0xC0, 0x25, 0xE0, 0x60, 0xA8, 0x40,
++0xB8, 0xE4, 0x93, 0xA3, 0xFA, 0xE4, 0x93, 0xA3,
++0xF8, 0xE4, 0x93, 0xA3, 0xC8, 0xC5, 0x82, 0xC8,
++0xCA, 0xC5, 0x83, 0xCA, 0xF0, 0xA3, 0xC8, 0xC5,
++0x82, 0xC8, 0xCA, 0xC5, 0x83, 0xCA, 0xDF, 0xE9,
++0xDE, 0xE7, 0x80, 0xBE, 0x41, 0x9C, 0xE0, 0x00,
++0x41, 0x9C, 0xE5, 0x00, 0x41, 0x9B, 0x89, 0x00,
++0x41, 0x9B, 0x08, 0x00, 0x44, 0x9C, 0xC3, 0x00,
++0x50, 0xF2, 0x01, 0x00, 0xC8, 0xA7, 0xD0, 0x50,
++0xD8, 0xAC, 0x90, 0x9C, 0xDF, 0xEF, 0xF0, 0x7F,
++0x02, 0xD1, 0x27, 0x90, 0x86, 0xAF, 0xE0, 0xFF,
++0x90, 0x9C, 0xDF, 0xE0, 0xFE, 0xEF, 0x4E, 0x90,
++0x86, 0xAF, 0xF0, 0x22, 0xF1, 0xED, 0x2E, 0x90,
++0x86, 0xB4, 0xF0, 0x12, 0x9C, 0x58, 0xFF, 0xED,
++0x2F, 0x90, 0x86, 0xB5, 0xF1, 0xE6, 0xFF, 0xED,
++0x2F, 0x90, 0x86, 0xB6, 0xF1, 0xA3, 0xFF, 0xED,
++0x2F, 0x90, 0x86, 0xB7, 0xF1, 0xD1, 0xFF, 0xED,
++0x2F, 0x90, 0x86, 0xB8, 0xF1, 0x9B, 0xFF, 0xED,
++0x2F, 0x90, 0x86, 0xB9, 0xF1, 0xD8, 0x90, 0x86,
++0xBA, 0xF0, 0x22, 0xF0, 0x90, 0x00, 0x05, 0x02,
++0x02, 0x1F, 0x4F, 0xF0, 0x90, 0x00, 0x03, 0x02,
++0x02, 0x1F, 0x90, 0x02, 0x09, 0xE0, 0xFD, 0xF1,
++0xA4, 0xFE, 0xAF, 0x05, 0xED, 0x2E, 0x90, 0x98,
++0x41, 0xF1, 0xD1, 0xFF, 0xED, 0x2F, 0x90, 0x98,
++0x42, 0xF1, 0x9B, 0xFF, 0xED, 0x2F, 0x90, 0x98,
++0x43, 0xF1, 0xD8, 0x90, 0x98, 0x44, 0xF0, 0x22,
++0x4F, 0xF0, 0x90, 0x00, 0x04, 0x02, 0x02, 0x1F,
++0xF0, 0x90, 0x00, 0x06, 0x12, 0x02, 0x1F, 0xFF,
++0xAE, 0x05, 0xED, 0x2F, 0x22, 0x4F, 0xF0, 0x90,
++0x00, 0x02, 0x02, 0x02, 0x1F, 0x90, 0x02, 0x09,
++0xE0, 0xFD, 0x12, 0x02, 0x06, 0xFE, 0xAF, 0x05,
++0xED, 0x22, 0x90, 0x99, 0xB1, 0x51, 0x27, 0x90,
++0x98, 0x59, 0xE0, 0x70, 0x0F, 0xF1, 0x6A, 0x13,
++0x13, 0x54, 0x3F, 0x30, 0xE0, 0x06, 0x90, 0x98,
++0x5F, 0x74, 0x01, 0xF0, 0x90, 0x98, 0x5B, 0xE0,
++0x70, 0x0F, 0xF1, 0x6A, 0xC4, 0x54, 0x0F, 0xFF,
++0xBF, 0x05, 0x06, 0x90, 0x98, 0x60, 0x74, 0x01,
++0xF0, 0x90, 0x99, 0xB1, 0x12, 0x9C, 0x55, 0xFF,
++0x90, 0x99, 0xB5, 0xF0, 0x12, 0x02, 0x06, 0xC3,
++0x13, 0x30, 0xE0, 0x0C, 0x12, 0xC7, 0x9B, 0x12,
++0x87, 0xE7, 0x90, 0x99, 0xB6, 0xF0, 0x80, 0x05,
++0x90, 0x99, 0xB6, 0xEF, 0xF0, 0x90, 0x99, 0xB5,
++0xE0, 0x90, 0x99, 0xB4, 0xF0, 0x90, 0x99, 0xB6,
++0xE0, 0xFE, 0x90, 0x99, 0xB4, 0xE0, 0xFF, 0xD3,
++0x9E, 0x50, 0x36, 0xF1, 0x6A, 0x54, 0x01, 0xFD,
++0x12, 0x6E, 0x71, 0x90, 0x99, 0xB4, 0xE0, 0xFF,
++0x12, 0x78, 0x4A, 0xEF, 0x90, 0x99, 0xB4, 0x70,
++0x06, 0xE0, 0xFF, 0xF1, 0xF3, 0x80, 0x05, 0xE0,
++0xFF, 0x12, 0xC0, 0x30, 0x90, 0x98, 0x60, 0xE0,
++0x60, 0x07, 0x90, 0x99, 0xB4, 0xE0, 0xFF, 0xF1,
++0xF3, 0x90, 0x99, 0xB4, 0xE0, 0x04, 0xF0, 0x80,
++0xBC, 0x90, 0x05, 0x5E, 0xE4, 0xF0, 0x90, 0x99,
++0xB5, 0xE0, 0x70, 0x1A, 0xFF, 0x12, 0x78, 0x4A,
++0xEF, 0x70, 0x13, 0x90, 0x86, 0x0C, 0x11, 0xC8,
++0x90, 0x8A, 0xED, 0x11, 0xC8, 0x12, 0xDE, 0x66,
++0x54, 0xBF, 0xF0, 0x54, 0x7F, 0xF0, 0x22, 0x7D,
++0xFF, 0xE4, 0xFF, 0xB1, 0x1E, 0x90, 0x8A, 0xFD,
++0xE0, 0xFE, 0xA3, 0xE0, 0xAA, 0x06, 0xF9, 0x02,
++0x04, 0x7A, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0,
++0xD0, 0x90, 0x9C, 0xE6, 0xED, 0xF0, 0x90, 0x88,
++0x31, 0xE0, 0xFE, 0xC4, 0x13, 0x13, 0x54, 0x03,
++0x30, 0xE0, 0x02, 0x41, 0x40, 0xEE, 0x12, 0xA8,
++0xAE, 0x30, 0xE0, 0x02, 0x41, 0x40, 0x90, 0x88,
++0x39, 0xE0, 0xFE, 0x6F, 0x70, 0x02, 0x41, 0x40,
++0xEF, 0x70, 0x02, 0x21, 0xA0, 0x24, 0xFE, 0x70,
++0x02, 0x21, 0xE5, 0x24, 0xFE, 0x60, 0x4F, 0x24,
++0xFC, 0x70, 0x02, 0x41, 0x2A, 0x24, 0xFC, 0x60,
++0x02, 0x41, 0x3A, 0xEE, 0xB4, 0x0E, 0x03, 0x12,
++0x71, 0x5F, 0x90, 0x88, 0x39, 0xE0, 0x70, 0x05,
++0x7F, 0x01, 0x12, 0x78, 0xC0, 0x90, 0x88, 0x39,
++0xE0, 0xB4, 0x06, 0x03, 0x12, 0x71, 0x24, 0x90,
++0x88, 0x39, 0xE0, 0xB4, 0x04, 0x11, 0x90, 0x9C,
++0xE6, 0xE0, 0xFF, 0x60, 0x05, 0x12, 0x67, 0x80,
++0x80, 0x05, 0x90, 0x8A, 0xED, 0x11, 0xC8, 0x90,
++0x88, 0x39, 0xE0, 0x64, 0x08, 0x60, 0x02, 0x41,
++0x3A, 0x12, 0x7B, 0xCC, 0x41, 0x3A, 0x90, 0x88,
++0x39, 0xE0, 0x70, 0x05, 0x7F, 0x01, 0x12, 0x78,
++0xC0, 0x90, 0x88, 0x39, 0xE0, 0xB4, 0x06, 0x03,
++0x12, 0x71, 0x24, 0x90, 0x88, 0x39, 0xE0, 0xB4,
++0x0E, 0x0B, 0x90, 0x86, 0x00, 0x11, 0xC8, 0xBF,
++0x01, 0x03, 0x12, 0x71, 0x5F, 0x90, 0x88, 0x39,
++0xE0, 0x64, 0x0C, 0x60, 0x02, 0x41, 0x3A, 0x90,
++0x86, 0x00, 0x11, 0xC8, 0xEF, 0x64, 0x01, 0x60,
++0x02, 0x41, 0x3A, 0x12, 0x68, 0xC2, 0x41, 0x3A,
++0x90, 0x88, 0x39, 0xE0, 0xB4, 0x0E, 0x0B, 0x90,
++0x86, 0x00, 0x11, 0xC8, 0xBF, 0x01, 0x03, 0x12,
++0x71, 0x5F, 0x90, 0x88, 0x39, 0xE0, 0xB4, 0x06,
++0x03, 0x12, 0x71, 0x24, 0x90, 0x88, 0x39, 0xE0,
++0xB4, 0x0C, 0x0B, 0x90, 0x86, 0x00, 0x11, 0xC8,
++0xBF, 0x01, 0x03, 0x12, 0x68, 0xC2, 0x90, 0x88,
++0x39, 0xE0, 0x64, 0x04, 0x70, 0x64, 0x90, 0x86,
++0x02, 0x11, 0xC8, 0xEF, 0x64, 0x01, 0x70, 0x5A,
++0x12, 0x73, 0x5A, 0x80, 0x55, 0x90, 0x88, 0x39,
++0xE0, 0xB4, 0x0E, 0x0B, 0x90, 0x86, 0x00, 0x11,
++0xC8, 0xBF, 0x01, 0x03, 0x12, 0x71, 0x5F, 0x90,
++0x88, 0x39, 0xE0, 0xB4, 0x06, 0x03, 0x12, 0x71,
++0x24, 0x90, 0x88, 0x39, 0xE0, 0xB4, 0x0C, 0x0B,
++0x90, 0x86, 0x00, 0x11, 0xC8, 0xBF, 0x01, 0x03,
++0x12, 0x68, 0xC2, 0x90, 0x88, 0x39, 0xE0, 0x70,
++0x05, 0x7F, 0x01, 0x12, 0x78, 0xC0, 0x90, 0x88,
++0x39, 0xE0, 0xB4, 0x04, 0x15, 0x12, 0x7A, 0x49,
++0x80, 0x10, 0x90, 0x88, 0x39, 0xE0, 0xB4, 0x0C,
++0x09, 0x12, 0xB4, 0xA1, 0x30, 0xE0, 0x03, 0x12,
++0x79, 0xD4, 0x90, 0x88, 0x39, 0x12, 0xFA, 0xF6,
++0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x9A, 0x61,
++0x12, 0x82, 0x27, 0x90, 0x05, 0x22, 0xE0, 0x90,
++0x9A, 0x72, 0xF0, 0x90, 0x04, 0x1D, 0xE0, 0x60,
++0x0B, 0x7B, 0x39, 0x11, 0xBF, 0xEF, 0x64, 0x01,
++0x70, 0x1C, 0x80, 0x00, 0x90, 0x98, 0x39, 0xE0,
++0xFF, 0x90, 0x92, 0x13, 0x74, 0x11, 0xF0, 0x7B,
++0x18, 0x7D, 0x01, 0x12, 0x66, 0xDB, 0x90, 0x9A,
++0x6F, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x9A,
++0x6F, 0xD1, 0xA3, 0x90, 0x9A, 0x71, 0xEF, 0xF0,
++0x90, 0x9A, 0x6F, 0x12, 0xFA, 0xAE, 0x7B, 0x01,
++0x90, 0x9A, 0x6D, 0xE0, 0xFD, 0x12, 0xE7, 0xF7,
++0x90, 0x9A, 0x6E, 0xE0, 0x60, 0x02, 0x61, 0x21,
++0xB1, 0x48, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01,
++0x90, 0x9A, 0x64, 0x71, 0xE0, 0x75, 0x48, 0x06,
++0xD0, 0x01, 0xD0, 0x02, 0xD0, 0x03, 0x71, 0xD0,
++0xF1, 0xE9, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01,
++0x90, 0x9A, 0x61, 0x71, 0xE0, 0x75, 0x48, 0x10,
++0xD0, 0x01, 0xD0, 0x02, 0xD0, 0x03, 0x71, 0xD0,
++0xB1, 0x4B, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01,
++0x71, 0xDD, 0x75, 0x48, 0x10, 0xD0, 0x01, 0xD0,
++0x02, 0xD0, 0x03, 0x71, 0xD0, 0x24, 0x60, 0xF9,
++0xE4, 0x34, 0xFC, 0xFA, 0x7B, 0x01, 0xC0, 0x03,
++0xC0, 0x02, 0xC0, 0x01, 0x71, 0xDD, 0x75, 0x48,
++0x10, 0xD0, 0x01, 0xD0, 0x02, 0xD0, 0x03, 0x71,
++0xD0, 0x24, 0x72, 0xF9, 0xE4, 0x34, 0xFC, 0xFA,
++0x7B, 0x01, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01,
++0x90, 0x9A, 0x6A, 0x71, 0xE0, 0x75, 0x48, 0x06,
++0xD0, 0x01, 0xD0, 0x02, 0xD0, 0x03, 0x12, 0x69,
++0xF5, 0x90, 0x9A, 0x67, 0x12, 0x82, 0x1E, 0x90,
++0x9A, 0x9E, 0x12, 0x82, 0x27, 0x90, 0x9A, 0xA1,
++0x12, 0x04, 0x3D, 0x00, 0x00, 0x00, 0x20, 0x90,
++0x9A, 0xA5, 0x74, 0x3A, 0xF0, 0x90, 0x9A, 0x61,
++0x12, 0x82, 0x1E, 0x12, 0xF3, 0x81, 0x71, 0xD3,
++0xF1, 0xE2, 0xB1, 0xC9, 0x75, 0x48, 0x28, 0x7B,
++0x01, 0x7A, 0x9A, 0x79, 0x73, 0x71, 0xD0, 0xF1,
++0xE2, 0xFA, 0x7B, 0x01, 0xC0, 0x03, 0x8B, 0x45,
++0x75, 0x46, 0x93, 0x75, 0x47, 0xD1, 0x75, 0x48,
++0x28, 0xD0, 0x03, 0x12, 0x69, 0xF5, 0x90, 0x9A,
++0x71, 0xE0, 0xFF, 0x90, 0x9A, 0x70, 0xE0, 0x2F,
++0xFF, 0x90, 0x9A, 0x6F, 0xE0, 0x34, 0x00, 0xCF,
++0x24, 0x30, 0xFD, 0xE4, 0x3F, 0xFC, 0x90, 0x98,
++0x39, 0xE0, 0xFB, 0x7F, 0x3A, 0x12, 0xC3, 0xFD,
++0x71, 0xD3, 0xF1, 0xE2, 0xFA, 0x7B, 0x01, 0xC0,
++0x03, 0x8B, 0x45, 0x75, 0x46, 0x9A, 0x75, 0x47,
++0x73, 0x75, 0x48, 0x28, 0xD0, 0x03, 0x12, 0x69,
++0xF5, 0x90, 0x98, 0x35, 0xE0, 0xB4, 0x02, 0x0D,
++0x90, 0x98, 0x39, 0xE0, 0xFF, 0x90, 0x9A, 0x71,
++0xE0, 0xFD, 0x12, 0xEC, 0x86, 0x90, 0x06, 0x33,
++0xE0, 0x44, 0x02, 0xF0, 0x90, 0x9A, 0x72, 0xE0,
++0xFD, 0x7B, 0x3A, 0x12, 0xFB, 0x48, 0xF0, 0x22,
++0x12, 0x69, 0xF5, 0x90, 0x9A, 0x6F, 0xA3, 0xE0,
++0xFF, 0xA3, 0xE0, 0x2F, 0x22, 0x90, 0x9A, 0x67,
++0x12, 0x82, 0x1E, 0x8B, 0x45, 0x8A, 0x46, 0x89,
++0x47, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0,
++0xD0, 0x90, 0x9C, 0x3F, 0x12, 0x82, 0x27, 0x78,
++0x4B, 0x7C, 0x9C, 0x7D, 0x01, 0x7B, 0xFF, 0x7A,
++0x80, 0x79, 0x8E, 0x7E, 0x00, 0x7F, 0x06, 0x12,
++0x01, 0xE0, 0x90, 0x05, 0x22, 0xE0, 0x90, 0x9C,
++0x4A, 0xF0, 0x90, 0x04, 0x1D, 0xE0, 0x60, 0x0B,
++0x7B, 0x33, 0x11, 0xBF, 0xEF, 0x64, 0x01, 0x70,
++0x1C, 0x80, 0x00, 0x90, 0x98, 0x38, 0xE0, 0xFF,
++0x90, 0x92, 0x13, 0x74, 0x10, 0xF0, 0x7B, 0x18,
++0x7D, 0x01, 0x12, 0x66, 0xDB, 0x90, 0x9C, 0x47,
++0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x9C, 0x47,
++0xD1, 0xA3, 0x90, 0x9C, 0x49, 0xEF, 0xF0, 0x90,
++0x9C, 0x47, 0x12, 0xFA, 0xAE, 0x7B, 0x01, 0x90,
++0x9C, 0x45, 0xE0, 0xFD, 0x12, 0xE7, 0xF7, 0x90,
++0x9C, 0x46, 0xE0, 0x70, 0x4D, 0xB1, 0x48, 0xC0,
++0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, 0x9C, 0x42,
++0x71, 0xE0, 0x75, 0x48, 0x06, 0xD0, 0x01, 0xD0,
++0x02, 0xD0, 0x03, 0xB1, 0x41, 0x71, 0xD6, 0xF1,
++0xDB, 0xFA, 0x7B, 0x01, 0xC0, 0x03, 0xC0, 0x02,
++0xC0, 0x01, 0x90, 0x9C, 0x42, 0x71, 0xE0, 0x75,
++0x48, 0x06, 0xD0, 0x01, 0xD0, 0x02, 0xD0, 0x03,
++0xB1, 0x41, 0x71, 0xD6, 0xF1, 0xE9, 0xC0, 0x03,
++0xC0, 0x02, 0xC0, 0x01, 0x90, 0x9C, 0x3F, 0x71,
++0xE0, 0x75, 0x48, 0x04, 0xD0, 0x01, 0xD0, 0x02,
++0x80, 0x44, 0x90, 0x9C, 0x46, 0xE0, 0x64, 0x01,
++0x70, 0x41, 0xB1, 0x48, 0xC0, 0x03, 0x8B, 0x45,
++0x75, 0x46, 0x93, 0x75, 0x47, 0x4D, 0x75, 0x48,
++0x06, 0xD0, 0x03, 0xB1, 0x41, 0x71, 0xD6, 0xF1,
++0xDB, 0xFA, 0x7B, 0x01, 0xC0, 0x03, 0x8B, 0x45,
++0x75, 0x46, 0x93, 0x75, 0x47, 0x57, 0x75, 0x48,
++0x06, 0xD0, 0x03, 0xB1, 0x41, 0x71, 0xD6, 0xF1,
++0xE9, 0xC0, 0x03, 0x8B, 0x45, 0x75, 0x46, 0x93,
++0x75, 0x47, 0x5D, 0x75, 0x48, 0x04, 0xD0, 0x03,
++0x12, 0x69, 0xF5, 0x90, 0x98, 0x35, 0xE0, 0xB4,
++0x02, 0x0D, 0x90, 0x98, 0x38, 0xE0, 0xFF, 0x90,
++0x9C, 0x49, 0xE0, 0xFD, 0x12, 0xEC, 0x86, 0x90,
++0x06, 0x30, 0xE0, 0x44, 0x10, 0xF0, 0x90, 0x9C,
++0x4A, 0xE0, 0xFD, 0x7B, 0x34, 0x12, 0xFB, 0x48,
++0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xEB, 0xB4,
++0x57, 0x05, 0x12, 0xFB, 0x53, 0x80, 0x10, 0xEF,
++0x70, 0x07, 0x90, 0x98, 0x6A, 0xE0, 0x4D, 0x80,
++0x06, 0x12, 0xC0, 0x4D, 0x12, 0xFB, 0x53, 0x90,
++0x05, 0x22, 0xF0, 0x90, 0x93, 0x01, 0xEB, 0xF0,
++0x22, 0x12, 0x69, 0xF5, 0x90, 0x9C, 0x47, 0x22,
++0xA3, 0xA3, 0xE0, 0x24, 0x38, 0xF9, 0xE4, 0x34,
++0xFC, 0xFA, 0x7B, 0x01, 0x22, 0xD1, 0x82, 0xE4,
++0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x99, 0xB1, 0xD1,
++0xA3, 0x90, 0x99, 0xB3, 0xEF, 0xF0, 0x90, 0x99,
++0xB1, 0xA3, 0xE0, 0x24, 0x38, 0xF9, 0xE4, 0x34,
++0xFC, 0xB1, 0xC9, 0x75, 0x48, 0x06, 0x7B, 0x01,
++0x7A, 0x93, 0x79, 0x4D, 0xF1, 0x63, 0x71, 0xD6,
++0x24, 0x3E, 0xF9, 0xE4, 0x34, 0xFC, 0xB1, 0xC9,
++0x75, 0x48, 0x04, 0x7B, 0x01, 0x7A, 0x93, 0x79,
++0x53, 0xF1, 0x63, 0x71, 0xD6, 0xF1, 0xDB, 0xB1,
++0xC9, 0x75, 0x48, 0x06, 0x7B, 0x01, 0x7A, 0x93,
++0x79, 0x57, 0xF1, 0x63, 0x71, 0xD6, 0x24, 0x48,
++0xF9, 0xE4, 0x34, 0xFC, 0xB1, 0xC9, 0x75, 0x48,
++0x04, 0x7B, 0x01, 0x7A, 0x93, 0x79, 0x5D, 0x02,
++0x69, 0xF5, 0xE0, 0xFF, 0x90, 0x99, 0xB1, 0xE0,
++0x2F, 0xF0, 0xE0, 0x24, 0x00, 0xF9, 0xE4, 0x34,
++0xFC, 0x75, 0x45, 0x01, 0xF5, 0x46, 0x89, 0x47,
++0x22, 0x90, 0x98, 0x42, 0xD1, 0x80, 0xEF, 0xF0,
++0xE0, 0xFE, 0x12, 0xFB, 0x27, 0xFF, 0x74, 0x29,
++0x2E, 0x12, 0xE0, 0x62, 0xFD, 0x90, 0x99, 0xB1,
++0xE0, 0x24, 0x2C, 0xD1, 0xC0, 0x90, 0x99, 0xB1,
++0xE0, 0x2F, 0x24, 0x30, 0xA3, 0xF0, 0xE0, 0xFD,
++0x24, 0x04, 0x12, 0xD6, 0xF8, 0xFE, 0x74, 0x05,
++0x2D, 0x12, 0xC7, 0xAF, 0x12, 0xC7, 0x92, 0x90,
++0x95, 0x9D, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x99,
++0xB2, 0xE0, 0x24, 0x0C, 0xF9, 0xE4, 0x34, 0xFC,
++0xB1, 0xC9, 0x75, 0x48, 0x04, 0x7B, 0x01, 0x7A,
++0x95, 0x79, 0x9F, 0x12, 0x69, 0xF5, 0x90, 0x99,
++0xB2, 0xE0, 0x24, 0x14, 0xF0, 0xE0, 0xFD, 0x24,
++0x01, 0x12, 0xC3, 0xF5, 0xE0, 0xFE, 0x74, 0x00,
++0x2D, 0xD1, 0x9B, 0x12, 0xC7, 0x92, 0x90, 0x95,
++0xA3, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x98, 0x43,
++0xD1, 0x80, 0xEF, 0xF0, 0x90, 0x95, 0x99, 0xE0,
++0xFE, 0xA3, 0xE0, 0xFF, 0x4E, 0x60, 0x10, 0x90,
++0x99, 0xB1, 0xB1, 0xC2, 0x8F, 0x48, 0x7B, 0x01,
++0x7A, 0x95, 0x79, 0xA7, 0x12, 0x69, 0xF5, 0x90,
++0x98, 0x44, 0xD1, 0x80, 0xEF, 0xF0, 0xB1, 0xC3,
++0x90, 0x95, 0x9B, 0xA3, 0xE0, 0xF5, 0x48, 0x7B,
++0x01, 0x7A, 0x95, 0x79, 0xC7, 0x02, 0x69, 0xF5,
++0xE0, 0xFF, 0x12, 0x7B, 0x07, 0x90, 0x99, 0xB1,
++0x22, 0x12, 0x80, 0xC0, 0xA8, 0x04, 0xA9, 0x05,
++0xAA, 0x06, 0xAB, 0x07, 0x90, 0x99, 0xB1, 0xA3,
++0xE0, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, 0xFC,
++0xF5, 0x83, 0x22, 0xA3, 0xE0, 0xFE, 0x24, 0x28,
++0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0,
++0xFF, 0x74, 0x29, 0x2E, 0xF5, 0x82, 0xE4, 0x34,
++0xFC, 0xF5, 0x83, 0xE0, 0xFD, 0x74, 0x2C, 0x2E,
++0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0,
++0xFB, 0xE4, 0xFE, 0xEF, 0x30, 0xE7, 0x04, 0x7C,
++0x02, 0x80, 0x02, 0xE4, 0xFC, 0xED, 0x30, 0xE6,
++0x09, 0xAF, 0x03, 0x12, 0xE7, 0xB8, 0xAE, 0x07,
++0x80, 0x02, 0xE4, 0xFE, 0xEC, 0x24, 0x18, 0x2E,
++0xFF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0,
++0xD0, 0x90, 0x93, 0x07, 0x12, 0xD7, 0xE4, 0xD1,
++0x9B, 0xE0, 0x90, 0x9B, 0x26, 0xF0, 0x74, 0x01,
++0x2F, 0x12, 0xC3, 0xF5, 0xE0, 0x90, 0x9B, 0x47,
++0x12, 0xD6, 0xE7, 0x90, 0x9B, 0x68, 0xF0, 0xEF,
++0x24, 0x20, 0x90, 0x99, 0xB1, 0xF0, 0xB1, 0xC3,
++0x90, 0x9B, 0x26, 0xE0, 0xF5, 0x48, 0x7B, 0x01,
++0x7A, 0x9B, 0x79, 0x27, 0x12, 0x69, 0xF5, 0x90,
++0x9B, 0x26, 0xB1, 0xBA, 0x90, 0x9B, 0x47, 0xE0,
++0xF5, 0x48, 0x7B, 0x01, 0x7A, 0x9B, 0x79, 0x48,
++0x12, 0x69, 0xF5, 0x90, 0x9B, 0x47, 0xB1, 0xBA,
++0x90, 0x9B, 0x68, 0xE0, 0xF5, 0x48, 0x7B, 0x01,
++0x7A, 0x9B, 0x79, 0x69, 0x12, 0x69, 0xF5, 0xE4,
++0xFF, 0x90, 0x9B, 0x26, 0xE0, 0xFE, 0xEF, 0xC3,
++0x9E, 0x50, 0x03, 0x0F, 0x80, 0xF3, 0xD0, 0xD0,
++0x92, 0xAF, 0x22, 0x12, 0x69, 0xF5, 0x90, 0x99,
++0xB1, 0x22, 0x90, 0x99, 0xB1, 0x12, 0x82, 0x1E,
++0x02, 0x02, 0x06, 0xD3, 0x10, 0xAF, 0x01, 0xC3,
++0xC0, 0xD0, 0x90, 0x9C, 0xA6, 0xEF, 0xF0, 0xA3,
++0xED, 0xF0, 0x90, 0x86, 0xB1, 0xE0, 0x04, 0xF0,
++0x90, 0x04, 0x1D, 0xE0, 0x60, 0x2F, 0x90, 0x05,
++0x22, 0xE0, 0x90, 0x9C, 0xAA, 0xF0, 0x7B, 0x26,
++0x11, 0xBF, 0xEF, 0x64, 0x01, 0x70, 0x0B, 0x12,
++0xF9, 0xE8, 0x12, 0xAF, 0xD2, 0x12, 0xE0, 0x21,
++0xEE, 0xF0, 0x90, 0x9C, 0xAA, 0xE0, 0xFD, 0x7B,
++0x27, 0xE4, 0xFF, 0xB1, 0x1E, 0x12, 0xFA, 0x9C,
++0x12, 0x04, 0x7E, 0x80, 0x11, 0x12, 0xFA, 0x9C,
++0x12, 0x04, 0x7E, 0x12, 0xF9, 0xE8, 0x12, 0xAF,
++0xD2, 0x12, 0xE0, 0x21, 0xEE, 0xF0, 0x90, 0x04,
++0x1F, 0x74, 0x20, 0xF0, 0x7F, 0x01, 0xD0, 0xD0,
++0x92, 0xAF, 0x22, 0x24, 0x42, 0xF9, 0xE4, 0x34,
++0xFC, 0x22, 0x24, 0x30, 0xF9, 0xE4, 0x34, 0xFC,
++0x22, 0x24, 0x48, 0xF9, 0xE4, 0x34, 0xFC, 0xFA,
++0x7B, 0x01, 0x22, 0x7D, 0x01, 0xD3, 0x10, 0xAF,
++0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x9C, 0xD3, 0xEF,
++0xF0, 0xA3, 0xED, 0xF0, 0x90, 0x8A, 0xF9, 0x11,
++0x47, 0x7D, 0x44, 0x7F, 0x6F, 0x12, 0x04, 0x7E,
++0x12, 0x88, 0xC5, 0x90, 0x9C, 0xD4, 0xE0, 0x90,
++0x9C, 0xD3, 0xB4, 0x01, 0x07, 0x91, 0xF6, 0x44,
++0x04, 0xF0, 0x80, 0x05, 0x91, 0xF6, 0x54, 0xFB,
++0xF0, 0x90, 0x8A, 0xF9, 0x11, 0x47, 0x91, 0x9E,
++0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x8A, 0x77,
++0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xF5, 0x82, 0x8E,
++0x83, 0x12, 0x04, 0x7E, 0x90, 0x8A, 0x79, 0xE0,
++0xFE, 0xA3, 0xE0, 0xF5, 0x82, 0x8E, 0x83, 0x22,
++0x90, 0x99, 0xB1, 0xEF, 0x51, 0xD3, 0x7F, 0xF4,
++0x7E, 0x01, 0x12, 0x5F, 0xA6, 0xBF, 0x01, 0x08,
++0x90, 0x99, 0xF8, 0xE0, 0x90, 0x99, 0xFA, 0xF0,
++0x51, 0xD4, 0x7F, 0xF5, 0x7E, 0x01, 0x12, 0x5F,
++0xA6, 0xBF, 0x01, 0x08, 0x90, 0x99, 0xF8, 0xE0,
++0x90, 0x99, 0xFB, 0xF0, 0x51, 0xD4, 0x7F, 0xF6,
++0x7E, 0x01, 0x12, 0x5F, 0xA6, 0xBF, 0x01, 0x08,
++0x90, 0x99, 0xF8, 0xE0, 0x90, 0x99, 0xFC, 0xF0,
++0x51, 0xD4, 0x7F, 0xF7, 0x7E, 0x01, 0x12, 0x5F,
++0xA6, 0xBF, 0x01, 0x08, 0x90, 0x99, 0xF8, 0xE0,
++0x90, 0x99, 0xFD, 0xF0, 0x51, 0xD4, 0x7F, 0xF8,
++0x7E, 0x01, 0x12, 0x5F, 0xA6, 0xBF, 0x01, 0x08,
++0x90, 0x99, 0xF8, 0xE0, 0x90, 0x99, 0xFE, 0xF0,
++0x51, 0xD4, 0x12, 0xFB, 0xE2, 0xBF, 0x01, 0x08,
++0x90, 0x99, 0xF8, 0xE0, 0x90, 0x99, 0xFF, 0xF0,
++0x51, 0xD4, 0x71, 0xCD, 0x64, 0x01, 0x70, 0x54,
++0x90, 0x99, 0xF8, 0xE0, 0x90, 0x9A, 0x00, 0xF0,
++0x54, 0x07, 0x60, 0x08, 0x90, 0x99, 0xF8, 0xE0,
++0x54, 0xE0, 0x70, 0x40, 0x7B, 0x01, 0x7A, 0x99,
++0x79, 0xF9, 0x7F, 0xFA, 0x71, 0xCF, 0x64, 0x01,
++0x70, 0x32, 0x90, 0x99, 0xF8, 0xE0, 0xFC, 0x54,
++0x07, 0x70, 0x12, 0x90, 0x9A, 0x00, 0xE0, 0xFE,
++0x90, 0x99, 0xF9, 0xE0, 0x54, 0x07, 0xFD, 0xEE,
++0x4D, 0x90, 0x9A, 0x00, 0xF0, 0xEC, 0x54, 0xE0,
++0x70, 0x12, 0x90, 0x9A, 0x00, 0xE0, 0xFF, 0x90,
++0x99, 0xF9, 0xE0, 0x54, 0xE0, 0xFE, 0xEF, 0x4E,
++0x90, 0x9A, 0x00, 0xF0, 0x51, 0xD4, 0x7F, 0xFD,
++0x71, 0xCF, 0x64, 0x01, 0x70, 0x4B, 0x90, 0x99,
++0xF8, 0xE0, 0xFE, 0x54, 0xCC, 0x90, 0x9A, 0x01,
++0xF0, 0xEE, 0x54, 0x0C, 0xFF, 0x60, 0x08, 0x90,
++0x99, 0xF8, 0xE0, 0x54, 0xC0, 0x70, 0x32, 0xEF,
++0x70, 0x16, 0x90, 0x9A, 0x01, 0xE0, 0xFF, 0x90,
++0x99, 0xF8, 0xE0, 0x54, 0x03, 0x25, 0xE0, 0x25,
++0xE0, 0xFE, 0xEF, 0x4E, 0x90, 0x9A, 0x01, 0xF0,
++0x90, 0x99, 0xF8, 0xE0, 0xFF, 0x54, 0xC0, 0x70,
++0x10, 0x90, 0x9A, 0x01, 0xE0, 0xFE, 0xEF, 0x54,
++0x30, 0x25, 0xE0, 0x25, 0xE0, 0xFF, 0xEE, 0x4F,
++0xF0, 0x51, 0xD4, 0x7F, 0xF0, 0x7E, 0x01, 0x12,
++0x5F, 0xA6, 0xBF, 0x01, 0x08, 0x90, 0x99, 0xF8,
++0xE0, 0x90, 0x9A, 0x02, 0xF0, 0x51, 0xD4, 0x7F,
++0xF1, 0x7E, 0x01, 0x12, 0x5F, 0xA6, 0xBF, 0x01,
++0x08, 0x90, 0x99, 0xF8, 0xE0, 0x90, 0x9A, 0x03,
++0xF0, 0x51, 0xD4, 0x7F, 0xF2, 0x7E, 0x01, 0x12,
++0x5F, 0xA6, 0xBF, 0x01, 0x08, 0x90, 0x99, 0xF8,
++0xE0, 0x90, 0x9A, 0x04, 0xF0, 0x51, 0xD4, 0x7F,
++0xF3, 0x7E, 0x01, 0x12, 0x5F, 0xA6, 0xBF, 0x01,
++0x08, 0x90, 0x99, 0xF8, 0xE0, 0x90, 0x9A, 0x05,
++0xF0, 0x51, 0xD4, 0x7F, 0xFC, 0x7E, 0x01, 0x12,
++0x5F, 0xA6, 0xBF, 0x01, 0x08, 0x90, 0x99, 0xF8,
++0xE0, 0x90, 0x9A, 0x06, 0xF0, 0x90, 0x99, 0xB2,
++0x74, 0x19, 0xF0, 0x90, 0x99, 0xD4, 0x74, 0x08,
++0xF0, 0x90, 0x99, 0xFA, 0xE0, 0x90, 0x99, 0xB4,
++0xF0, 0x90, 0x99, 0xFB, 0xE0, 0x90, 0x99, 0xB5,
++0xF0, 0x90, 0x99, 0xFC, 0xE0, 0x90, 0x99, 0xB6,
++0xF0, 0x90, 0x99, 0xFD, 0xE0, 0x90, 0x99, 0xB7,
++0xF0, 0x90, 0x99, 0xFE, 0xE0, 0x90, 0x99, 0xB8,
++0xF0, 0x90, 0x99, 0xFF, 0xE0, 0x90, 0x99, 0xB9,
++0xF0, 0x90, 0x9A, 0x00, 0xE0, 0x90, 0x99, 0xBA,
++0xF0, 0x90, 0x9A, 0x01, 0xE0, 0x90, 0x99, 0xBB,
++0xF0, 0x90, 0x99, 0xD5, 0x74, 0x1A, 0xF0, 0x90,
++0x99, 0xF7, 0x74, 0x05, 0xF0, 0x90, 0x9A, 0x02,
++0xE0, 0x90, 0x99, 0xD7, 0xF0, 0x90, 0x9A, 0x03,
++0xE0, 0x90, 0x99, 0xD8, 0xF0, 0x90, 0x9A, 0x04,
++0xE0, 0x90, 0x99, 0xD9, 0xF0, 0x90, 0x9A, 0x05,
++0xE0, 0x90, 0x99, 0xDA, 0xF0, 0x90, 0x9A, 0x06,
++0xE0, 0x90, 0x99, 0xDB, 0xF0, 0x90, 0x00, 0x35,
++0xE0, 0x54, 0xFC, 0x44, 0x01, 0x51, 0xD3, 0x7F,
++0x6F, 0x7E, 0x00, 0x12, 0x5F, 0xA6, 0xBF, 0x01,
++0x08, 0x90, 0x99, 0xF8, 0xE0, 0x90, 0x9A, 0x07,
++0xF0, 0x90, 0x00, 0x35, 0xE0, 0x54, 0xFC, 0xF0,
++0x90, 0x99, 0xB1, 0xE0, 0xB4, 0x01, 0x16, 0x7B,
++0x01, 0x7A, 0x99, 0x79, 0xB2, 0x12, 0xFA, 0x71,
++0x7B, 0x01, 0x7A, 0x99, 0x79, 0xD5, 0x11, 0x35,
++0x7F, 0x04, 0x02, 0x04, 0x7E, 0x75, 0x45, 0x01,
++0x75, 0x46, 0x99, 0x75, 0x47, 0xB4, 0x75, 0x48,
++0x08, 0x7B, 0x01, 0x7A, 0x01, 0x79, 0xA2, 0x12,
++0xEE, 0xAE, 0x75, 0x46, 0x99, 0x75, 0x47, 0xD7,
++0x75, 0x48, 0x05, 0x7B, 0x01, 0x7A, 0x01, 0x79,
++0xAA, 0x12, 0x69, 0xF5, 0x90, 0x9A, 0x07, 0xE0,
++0x90, 0x01, 0xA1, 0xF0, 0x90, 0x01, 0xA0, 0x74,
++0x19, 0xF0, 0x22, 0xF0, 0x7B, 0x01, 0x7A, 0x99,
++0x79, 0xF8, 0x22, 0x7E, 0x00, 0x7F, 0x62, 0x7D,
++0x00, 0x7B, 0x01, 0x7A, 0x88, 0x79, 0x31, 0x12,
++0x04, 0x80, 0x12, 0xFB, 0x0D, 0x12, 0x04, 0x80,
++0xE4, 0x90, 0x99, 0xAF, 0xF0, 0x90, 0x88, 0x35,
++0x74, 0x02, 0xF0, 0x90, 0x88, 0x3C, 0x14, 0xF0,
++0xA3, 0xF0, 0xA3, 0x74, 0x50, 0xF0, 0x90, 0x88,
++0x42, 0xE4, 0xF0, 0xA3, 0x74, 0x02, 0xF0, 0x90,
++0x88, 0x4E, 0x74, 0x10, 0xF0, 0xA3, 0x74, 0x50,
++0xF0, 0x12, 0xF9, 0x3A, 0x90, 0x8A, 0x89, 0x11,
++0x47, 0x91, 0x9E, 0x90, 0x8A, 0x89, 0x11, 0x47,
++0x7D, 0x0C, 0x7F, 0x02, 0x12, 0x04, 0x7E, 0x90,
++0x8A, 0x89, 0x11, 0x47, 0x7D, 0x0C, 0x7F, 0x01,
++0x12, 0x04, 0x7E, 0x90, 0x86, 0xB3, 0xE0, 0xFF,
++0xB4, 0x01, 0x08, 0x90, 0x88, 0x41, 0x74, 0xD4,
++0xF0, 0x80, 0x11, 0xEF, 0xB4, 0x03, 0x08, 0x90,
++0x88, 0x41, 0x74, 0x14, 0xF0, 0x80, 0x05, 0xE4,
++0x90, 0x88, 0x41, 0xF0, 0x90, 0x00, 0x79, 0xE0,
++0x54, 0x03, 0xFF, 0xBF, 0x02, 0x0D, 0x90, 0x00,
++0x28, 0xE0, 0x30, 0xE2, 0x06, 0x90, 0x88, 0x53,
++0x74, 0x02, 0xF0, 0x90, 0x88, 0x93, 0x74, 0x03,
++0xF0, 0xA3, 0x74, 0x0F, 0xF0, 0xA3, 0xE0, 0x54,
++0x01, 0x44, 0x28, 0xF0, 0xA3, 0x74, 0x07, 0xF0,
++0x7E, 0x00, 0x7F, 0x18, 0x7D, 0x00, 0x7B, 0x01,
++0x7A, 0x93, 0x79, 0x0C, 0x12, 0x04, 0x80, 0x90,
++0x8A, 0xA3, 0x11, 0x47, 0x7F, 0x01, 0x12, 0x04,
++0x7E, 0x90, 0x05, 0x58, 0x74, 0x02, 0xF0, 0x7E,
++0x00, 0xFF, 0x7D, 0x00, 0x7B, 0x01, 0x7A, 0x88,
++0x79, 0x9A, 0x12, 0x04, 0x80, 0x90, 0x06, 0x04,
++0xE0, 0x54, 0x7F, 0xF0, 0x90, 0x06, 0x0A, 0xE0,
++0x54, 0xF8, 0xF0, 0x90, 0x05, 0x22, 0xE4, 0xF0,
++0x90, 0x88, 0x9C, 0xF0, 0x22, 0x7F, 0xFB, 0x7E,
++0x01, 0x12, 0x5F, 0xA6, 0xEF, 0x22, 0x90, 0x99,
++0xAF, 0x74, 0x01, 0xF0, 0x90, 0x06, 0x92, 0x04,
++0xF0, 0x90, 0x01, 0x3C, 0x74, 0x04, 0xF0, 0x90,
++0x88, 0x31, 0xE0, 0x44, 0x08, 0xF0, 0x90, 0x88,
++0x39, 0xE0, 0x64, 0x0C, 0x60, 0x13, 0x90, 0x8A,
++0xB9, 0x11, 0x47, 0xE4, 0xFD, 0x7F, 0x0C, 0x12,
++0x04, 0x7E, 0x90, 0x8A, 0xF9, 0x11, 0x47, 0x91,
++0x9E, 0x90, 0x8A, 0xAF, 0x11, 0x47, 0x7D, 0x08,
++0xE4, 0xFF, 0x02, 0x04, 0x7E, 0xE4, 0x90, 0x9A,
++0x35, 0xF0, 0x90, 0x9B, 0x89, 0x04, 0xF0, 0x90,
++0x06, 0x32, 0xE0, 0x44, 0x04, 0xF0, 0x90, 0x98,
++0x31, 0x12, 0x04, 0xB8, 0xEF, 0x24, 0x01, 0x12,
++0xB7, 0xEB, 0x90, 0x98, 0x31, 0x12, 0x04, 0x31,
++0x12, 0xD3, 0x2A, 0xE4, 0x90, 0x9B, 0x0A, 0xF0,
++0xFF, 0x12, 0xF5, 0x97, 0xF1, 0xE8, 0x70, 0x48,
++0x90, 0x8A, 0xB9, 0x11, 0x47, 0x7D, 0x01, 0x7F,
++0x02, 0x12, 0x04, 0x7E, 0x7F, 0x05, 0x7E, 0x00,
++0x12, 0x7A, 0xAE, 0x12, 0xFB, 0x86, 0x90, 0x8A,
++0x89, 0x11, 0x47, 0x12, 0xFB, 0xBC, 0x90, 0x88,
++0x39, 0xE0, 0x64, 0x02, 0x60, 0x22, 0x90, 0x9A,
++0x35, 0xE0, 0x04, 0xF0, 0x7F, 0x01, 0x7E, 0x00,
++0x12, 0x7A, 0xAE, 0x90, 0x8A, 0xB9, 0x11, 0x47,
++0x7D, 0x01, 0x7F, 0x02, 0x12, 0x04, 0x7E, 0x90,
++0x9A, 0x35, 0xE0, 0xD3, 0x94, 0x0A, 0x40, 0xD6,
++0x90, 0x9C, 0x9B, 0x12, 0x04, 0x3D, 0x00, 0x00,
++0x00, 0x0A, 0xF1, 0xE0, 0xA1, 0x3D, 0xE4, 0xFD,
++0xFF, 0x02, 0x04, 0x7E, 0x12, 0xE3, 0x40, 0x90,
++0x9B, 0x04, 0xEF, 0xF0, 0x20, 0xE0, 0x06, 0x90,
++0x01, 0x3D, 0x74, 0x01, 0xF0, 0x90, 0x9B, 0x04,
++0xE0, 0x90, 0x8A, 0x89, 0x30, 0xE0, 0x12, 0x11,
++0x47, 0x7D, 0x01, 0xE4, 0xFF, 0x12, 0x04, 0x7E,
++0x90, 0x88, 0x33, 0xE0, 0x44, 0x04, 0xF0, 0x80,
++0x04, 0x11, 0x47, 0x91, 0x9E, 0x90, 0x9B, 0x04,
++0xE0, 0x30, 0xE6, 0x11, 0x90, 0x01, 0x2F, 0xE0,
++0x30, 0xE7, 0x04, 0xE4, 0xF0, 0x80, 0x06, 0x90,
++0x01, 0x2F, 0x74, 0x80, 0xF0, 0x12, 0xFA, 0x60,
++0x74, 0x02, 0xF0, 0x02, 0x6E, 0x2F, 0xE0, 0xC4,
++0x54, 0xF0, 0x24, 0x05, 0xF5, 0x82, 0xE4, 0x34,
++0x81, 0xF5, 0x83, 0xE0, 0x22, 0x90, 0x88, 0x36,
++0xE0, 0x64, 0x01, 0x70, 0x28, 0xF1, 0xF1, 0x60,
++0x12, 0x90, 0x8A, 0xB9, 0x11, 0x47, 0xE4, 0xFD,
++0x7F, 0x0C, 0x12, 0x04, 0x7E, 0x12, 0xDE, 0xA7,
++0x02, 0x04, 0x7A, 0x90, 0x88, 0x39, 0xE0, 0x70,
++0x0C, 0x90, 0x8A, 0xB9, 0x11, 0x47, 0x7D, 0x01,
++0x7F, 0x04, 0x12, 0x04, 0x7E, 0x22, 0xE4, 0x90,
++0x9C, 0x9F, 0xF0, 0x7F, 0x03, 0xD3, 0x10, 0xAF,
++0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x9C, 0x9A, 0xEF,
++0xF0, 0x12, 0xA0, 0x01, 0x90, 0x9C, 0x9A, 0xE0,
++0xFF, 0x12, 0xFA, 0x11, 0x74, 0x01, 0xF0, 0x90,
++0x9C, 0x9F, 0xE0, 0xFE, 0xEF, 0xF1, 0xF8, 0xEE,
++0xF0, 0x90, 0x9C, 0x9A, 0xE0, 0xB1, 0xA3, 0x12,
++0x04, 0x3D, 0x00, 0x00, 0x00, 0x01, 0xB1, 0x98,
++0x78, 0x10, 0x12, 0x03, 0xEB, 0xAB, 0x07, 0xB1,
++0x98, 0x78, 0x08, 0x12, 0x03, 0xEB, 0x90, 0x92,
++0x20, 0xEF, 0xF0, 0xB1, 0x98, 0x90, 0x92, 0x21,
++0xEF, 0xF0, 0x7D, 0x01, 0x7F, 0x50, 0x7E, 0x01,
++0x12, 0x66, 0x33, 0xD0, 0xD0, 0x92, 0xAF, 0x22,
++0x90, 0x9C, 0x9B, 0x02, 0x04, 0xB8, 0x90, 0x9A,
++0x34, 0xE0, 0xFB, 0x75, 0xF0, 0x0A, 0xA4, 0x24,
++0x8A, 0xF5, 0x82, 0xE4, 0x34, 0x9B, 0xF5, 0x83,
++0x22, 0xE4, 0x90, 0x9A, 0x34, 0xF0, 0x90, 0x9A,
++0x34, 0xE0, 0xFF, 0xC3, 0x94, 0x08, 0x40, 0x02,
++0xC1, 0x46, 0x12, 0xFA, 0x10, 0xE0, 0x64, 0x01,
++0x70, 0x74, 0x90, 0x9A, 0x34, 0xE0, 0xB1, 0xA3,
++0x12, 0x04, 0xB8, 0xE4, 0x7B, 0x01, 0xF1, 0x51,
++0x70, 0x3A, 0x90, 0x9A, 0x34, 0xE0, 0xFB, 0xF1,
++0xF8, 0xE0, 0x60, 0x21, 0x14, 0x70, 0x57, 0xEB,
++0x75, 0xF0, 0x0A, 0xA4, 0x24, 0x8E, 0xF5, 0x82,
++0xE4, 0x34, 0x9B, 0xF5, 0x83, 0x12, 0x04, 0xB8,
++0xEB, 0xB1, 0xA3, 0x12, 0x04, 0x31, 0x90, 0x9A,
++0x34, 0xE0, 0xFF, 0x80, 0x0B, 0xB1, 0x9E, 0x12,
++0x04, 0x3D, 0x00, 0x00, 0x00, 0x00, 0xAF, 0x03,
++0xF1, 0x58, 0x80, 0x2A, 0x90, 0x9A, 0x34, 0xE0,
++0xB1, 0xA3, 0x12, 0x04, 0xB8, 0xE4, 0xFB, 0xF1,
++0x51, 0x50, 0x1B, 0xB1, 0x9E, 0x12, 0x04, 0xB8,
++0xEF, 0x24, 0xFF, 0xFF, 0xEE, 0x34, 0xFF, 0xFE,
++0xED, 0x34, 0xFF, 0xFD, 0xEC, 0x34, 0xFF, 0xFC,
++0xEB, 0xB1, 0xA3, 0x12, 0x04, 0x31, 0x90, 0x9A,
++0x34, 0xE0, 0x04, 0xF0, 0xA1, 0xB6, 0x22, 0xD3,
++0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x9B,
++0x1D, 0xE0, 0xFF, 0x12, 0xF5, 0xCD, 0xEF, 0x70,
++0x02, 0xE1, 0x05, 0x90, 0x9B, 0x1E, 0xE0, 0xFB,
++0xD3, 0x94, 0x00, 0x40, 0x1A, 0x90, 0x9C, 0x2F,
++0x12, 0x04, 0x3D, 0x00, 0x00, 0x00, 0x0F, 0xAF,
++0x03, 0xE4, 0xFC, 0xFD, 0xFE, 0x12, 0xD4, 0x09,
++0x7F, 0x08, 0x7E, 0x0E, 0x12, 0xD1, 0x75, 0x90,
++0x9B, 0x1D, 0xE0, 0xFF, 0x90, 0x06, 0x33, 0xF0,
++0x12, 0xD5, 0x16, 0xE4, 0xFB, 0xFD, 0x12, 0xD4,
++0x95, 0x90, 0x9B, 0x20, 0xE0, 0x60, 0x08, 0x90,
++0x93, 0x05, 0xE0, 0xFF, 0x12, 0xF5, 0xF8, 0x12,
++0xCF, 0xDB, 0x30, 0xE0, 0x3B, 0x90, 0x95, 0xEA,
++0xE0, 0x60, 0x35, 0xE4, 0x90, 0x9A, 0x36, 0xF0,
++0x90, 0x95, 0xEA, 0xE0, 0xFF, 0x90, 0x9A, 0x36,
++0xE0, 0xC3, 0x9F, 0x50, 0x23, 0x7F, 0x03, 0x7E,
++0x00, 0x12, 0x7A, 0xAE, 0x90, 0x9A, 0x36, 0xE0,
++0x24, 0x29, 0x12, 0xC7, 0xE8, 0xE0, 0xFF, 0x12,
++0xF5, 0xF8, 0x90, 0x01, 0xA6, 0xE0, 0x04, 0xF0,
++0x90, 0x9A, 0x36, 0xE0, 0x04, 0xF0, 0x80, 0xD0,
++0x90, 0x9B, 0x1F, 0xE0, 0x90, 0x9A, 0x35, 0xF0,
++0x90, 0x9B, 0x0A, 0xE0, 0x04, 0xF0, 0xE0, 0xFF,
++0x12, 0xF5, 0x97, 0x90, 0x9A, 0x35, 0x12, 0xAF,
++0x1B, 0x90, 0x9C, 0x9B, 0x12, 0x04, 0x31, 0xF1,
++0xE0, 0xB1, 0x3D, 0x80, 0x47, 0xE4, 0x90, 0x9B,
++0x0A, 0xF0, 0x90, 0x9B, 0x89, 0xF0, 0x90, 0x06,
++0x32, 0xE0, 0x54, 0xFB, 0xF0, 0x12, 0xD3, 0x99,
++0xE4, 0xFF, 0x12, 0x78, 0x4A, 0xBF, 0x01, 0x12,
++0x90, 0x9B, 0x22, 0xE0, 0xFD, 0x90, 0x8A, 0x89,
++0x11, 0x47, 0x7F, 0x02, 0x12, 0x04, 0x7E, 0x12,
++0x7B, 0xAD, 0x90, 0x9A, 0x37, 0x74, 0x07, 0xF0,
++0x90, 0x9A, 0x59, 0xF0, 0x7B, 0x01, 0x7A, 0x9A,
++0x79, 0x37, 0x11, 0x35, 0x7F, 0x04, 0x12, 0x04,
++0x7E, 0x12, 0xB5, 0x7A, 0xD0, 0xD0, 0x92, 0xAF,
++0x22, 0xFA, 0xF9, 0xF8, 0xC3, 0x02, 0x03, 0xDA,
++0xEF, 0x24, 0xFC, 0x60, 0x05, 0x04, 0x70, 0x04,
++0x81, 0x15, 0xD1, 0x47, 0x22, 0xE4, 0xF5, 0x0F,
++0x90, 0x88, 0x36, 0xE0, 0x60, 0x58, 0xF1, 0xE8,
++0x70, 0x54, 0x12, 0xF9, 0xC0, 0x75, 0x0F, 0x01,
++0xE5, 0x0F, 0x60, 0x4A, 0x90, 0x88, 0x39, 0xE0,
++0x20, 0xE2, 0x0C, 0x90, 0x8A, 0xB9, 0x11, 0x47,
++0x7D, 0x01, 0x7F, 0x04, 0x12, 0x04, 0x7E, 0x12,
++0xB7, 0xB1, 0x90, 0x88, 0x3F, 0xE0, 0x60, 0x04,
++0x64, 0x01, 0x70, 0x11, 0xE4, 0x90, 0x92, 0x20,
++0xF0, 0xF1, 0xD6, 0xFF, 0xA3, 0xE0, 0xF1, 0xC7,
++0xFF, 0xA3, 0xE0, 0x80, 0x0F, 0xE4, 0x90, 0x92,
++0x20, 0xF0, 0xF1, 0xD6, 0x12, 0xF9, 0x97, 0xF1,
++0xC7, 0x12, 0xF9, 0x97, 0x2F, 0x33, 0x33, 0x33,
++0x54, 0xF8, 0x90, 0x88, 0x4F, 0xF0, 0x22, 0x2F,
++0x90, 0x92, 0x21, 0xF0, 0xE4, 0xFB, 0xFD, 0x7F,
++0x54, 0x7E, 0x01, 0x12, 0x66, 0x33, 0x90, 0x88,
++0x3E, 0xE0, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x22,
++0xE4, 0x90, 0x9C, 0x9F, 0xF0, 0x7F, 0x04, 0x22,
++0xE4, 0xFF, 0x12, 0x78, 0x4A, 0xEF, 0x64, 0x01,
++0x22, 0x90, 0x88, 0x34, 0xE0, 0x54, 0x0F, 0x22,
++0x75, 0xF0, 0x0A, 0xA4, 0x24, 0x92, 0xF5, 0x82,
++0xE4, 0x34, 0x9B, 0xF5, 0x83, 0x22, 0x12, 0x02,
++0x06, 0xFF, 0x90, 0x93, 0x03, 0xF0, 0xBF, 0x01,
++0x07, 0x11, 0xFA, 0xE4, 0x90, 0x93, 0x03, 0xF0,
++0x22, 0x90, 0x9C, 0xAC, 0x12, 0x82, 0x27, 0x90,
++0x9C, 0xAB, 0xEF, 0xF0, 0x12, 0x82, 0x30, 0x98,
++0x73, 0x00, 0x98, 0x78, 0x01, 0x98, 0x7D, 0x03,
++0x98, 0x82, 0x04, 0x98, 0x87, 0x06, 0x98, 0x97,
++0x12, 0x98, 0x9B, 0x14, 0x98, 0xA0, 0x1E, 0x98,
++0xA4, 0x20, 0x98, 0xA9, 0x25, 0x98, 0xAE, 0x27,
++0x98, 0xB3, 0x29, 0x98, 0xB8, 0x2A, 0x98, 0xC1,
++0x80, 0x98, 0xBD, 0x81, 0x98, 0xC6, 0x82, 0x98,
++0xCB, 0x83, 0x98, 0xD0, 0x84, 0x98, 0xDA, 0x86,
++0x98, 0xD5, 0x88, 0x98, 0xDF, 0xC3, 0x98, 0x8B,
++0xC6, 0x98, 0x8B, 0xC7, 0x98, 0x8B, 0xC8, 0x00,
++0x00, 0x98, 0xE4, 0x11, 0xF4, 0x02, 0x87, 0x64,
++0x11, 0xF4, 0x02, 0x87, 0xFA, 0x11, 0xF4, 0x02,
++0xE6, 0x91, 0x11, 0xF4, 0x02, 0xDC, 0xB3, 0x11,
++0xF4, 0x41, 0x8D, 0x90, 0x9C, 0xAB, 0xE0, 0xFF,
++0xA3, 0x12, 0x82, 0x1E, 0x02, 0xC0, 0xA0, 0x11,
++0xF4, 0x01, 0x06, 0x11, 0xF4, 0x02, 0xA8, 0x05,
++0x11, 0xF4, 0x41, 0x3A, 0x11, 0xF4, 0x02, 0xA8,
++0x14, 0x11, 0xF4, 0x02, 0xAF, 0xFB, 0x11, 0xF4,
++0x02, 0xB0, 0x03, 0x11, 0xF4, 0x02, 0xC0, 0x04,
++0x11, 0xF4, 0x02, 0xB7, 0xF6, 0x11, 0xF4, 0x61,
++0x1D, 0x11, 0xF4, 0x02, 0xDC, 0xFB, 0x11, 0xF4,
++0x02, 0xF4, 0x72, 0x11, 0xF4, 0x02, 0xF4, 0x81,
++0x11, 0xF4, 0x02, 0x87, 0xAA, 0x11, 0xF4, 0x02,
++0xF4, 0xBE, 0x11, 0xF4, 0x02, 0xD5, 0x28, 0x11,
++0xF4, 0x02, 0xC0, 0x1A, 0x90, 0x01, 0xC0, 0xE0,
++0x44, 0x01, 0xF0, 0x90, 0x9C, 0xAB, 0xE0, 0x90,
++0x01, 0xC2, 0xF0, 0x22, 0x90, 0x9C, 0xAC, 0x02,
++0x82, 0x1E, 0x31, 0xA7, 0x7F, 0xEF, 0x7E, 0x01,
++0x12, 0x5F, 0xA6, 0xBF, 0x01, 0x06, 0x90, 0x99,
++0xB1, 0xE0, 0xA3, 0xF0, 0x31, 0xA7, 0x7F, 0xEE,
++0x7E, 0x01, 0x12, 0x5F, 0xA6, 0xBF, 0x01, 0x08,
++0x90, 0x99, 0xB1, 0xE0, 0x90, 0x99, 0xB3, 0xF0,
++0x31, 0xA7, 0x7F, 0xED, 0x7E, 0x01, 0x12, 0x5F,
++0xA6, 0xBF, 0x01, 0x08, 0x90, 0x99, 0xB1, 0xE0,
++0x90, 0x99, 0xB4, 0xF0, 0x31, 0xA7, 0x7F, 0xEC,
++0x7E, 0x01, 0x12, 0x5F, 0xA6, 0xBF, 0x01, 0x08,
++0x90, 0x99, 0xB1, 0xE0, 0x90, 0x99, 0xB5, 0xF0,
++0x31, 0xA7, 0x7F, 0xEB, 0x7E, 0x01, 0x12, 0x5F,
++0xA6, 0xBF, 0x01, 0x08, 0x90, 0x99, 0xB1, 0xE0,
++0x90, 0x99, 0xB6, 0xF0, 0x90, 0x99, 0xB2, 0xE0,
++0xFF, 0xA3, 0xE0, 0xFD, 0xA3, 0xE0, 0xFB, 0xA3,
++0xE0, 0x90, 0x99, 0xBA, 0xF0, 0x90, 0x99, 0xB6,
++0xE0, 0x90, 0x99, 0xBB, 0xF0, 0x90, 0x99, 0xBC,
++0x74, 0x12, 0xF0, 0x90, 0x99, 0xDE, 0x74, 0x05,
++0xF0, 0x90, 0x99, 0xBE, 0xEF, 0x12, 0xC7, 0xE0,
++0x90, 0x99, 0xBA, 0xE0, 0x90, 0x99, 0xC1, 0xF0,
++0x90, 0x99, 0xBB, 0xE0, 0x90, 0x99, 0xC2, 0xF0,
++0x7B, 0x01, 0x7A, 0x99, 0x79, 0xBC, 0x12, 0x90,
++0x35, 0x7F, 0x04, 0x02, 0x04, 0x7E, 0xF0, 0x7B,
++0x01, 0x7A, 0x99, 0x79, 0xB1, 0x22, 0x7E, 0x00,
++0x7F, 0x0B, 0x7D, 0x00, 0x7B, 0x01, 0x7A, 0x98,
++0x79, 0x59, 0x12, 0x04, 0x80, 0x31, 0xA7, 0x12,
++0xFB, 0xE2, 0xBF, 0x01, 0x1C, 0x90, 0x99, 0xB1,
++0xE0, 0xFE, 0x54, 0x01, 0x90, 0x98, 0x59, 0xF0,
++0xEE, 0x54, 0x04, 0x90, 0x98, 0x5B, 0xF0, 0x90,
++0x99, 0xB1, 0xE0, 0x54, 0x08, 0x90, 0x98, 0x5A,
++0xF0, 0x31, 0xA7, 0x12, 0x93, 0xCD, 0x64, 0x01,
++0x70, 0x35, 0x90, 0x99, 0xB1, 0xE0, 0x54, 0x07,
++0x70, 0x15, 0x7B, 0x01, 0x7A, 0x99, 0x79, 0xB2,
++0x7F, 0xFA, 0x7E, 0x01, 0x12, 0x5F, 0xA6, 0xBF,
++0x01, 0x0F, 0x90, 0x99, 0xB2, 0x80, 0x03, 0x90,
++0x99, 0xB1, 0xE0, 0x54, 0x07, 0x90, 0x98, 0x5D,
++0xF0, 0x90, 0x99, 0xB1, 0xE0, 0x54, 0xE0, 0xC4,
++0x13, 0x54, 0x07, 0x90, 0x98, 0x5C, 0xF0, 0x31,
++0xA7, 0x7F, 0xFD, 0x7E, 0x01, 0x12, 0x5F, 0xA6,
++0xBF, 0x01, 0x0E, 0x90, 0x99, 0xB1, 0xE0, 0x54,
++0x0C, 0x13, 0x13, 0x54, 0x3F, 0x90, 0x98, 0x5E,
++0xF0, 0x22, 0x12, 0x02, 0x06, 0x90, 0x99, 0xD4,
++0xF0, 0x91, 0x58, 0x90, 0x99, 0xD5, 0xF0, 0x60,
++0x0F, 0x51, 0x85, 0x12, 0xC0, 0x35, 0x90, 0x99,
++0xD5, 0x51, 0x85, 0x7B, 0x57, 0x12, 0x8D, 0x1E,
++0x90, 0x99, 0xB1, 0x74, 0x20, 0xF0, 0x90, 0x99,
++0xD3, 0x74, 0x03, 0xF0, 0x90, 0x05, 0x22, 0xE0,
++0x90, 0x99, 0xB3, 0xF0, 0x90, 0x98, 0x6A, 0xE0,
++0x90, 0x99, 0xB4, 0xF0, 0x90, 0x98, 0x6B, 0xE0,
++0x90, 0x99, 0xB5, 0x31, 0xA6, 0x12, 0x90, 0x35,
++0x7F, 0x04, 0x02, 0x04, 0x7E, 0xE0, 0xFF, 0x90,
++0x99, 0xD4, 0xE0, 0xFD, 0x22, 0x12, 0x02, 0x06,
++0x64, 0x01, 0x60, 0x02, 0x61, 0x1C, 0x90, 0x99,
++0xF8, 0xF0, 0x90, 0x99, 0xF8, 0xE0, 0xFF, 0xC3,
++0x94, 0x10, 0x50, 0x28, 0xEF, 0x12, 0xFB, 0x73,
++0x7A, 0x99, 0x79, 0xF7, 0x12, 0x5F, 0xA6, 0xBF,
++0x01, 0x12, 0x90, 0x99, 0xF7, 0xE0, 0xFF, 0xA3,
++0xE0, 0x24, 0xF9, 0xF5, 0x82, 0xE4, 0x34, 0x99,
++0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x99, 0xF8, 0xE0,
++0x04, 0xF0, 0x80, 0xCE, 0x75, 0x45, 0x01, 0x75,
++0x46, 0x99, 0x75, 0x47, 0xF9, 0x75, 0x48, 0x08,
++0x7B, 0x01, 0x7A, 0x99, 0x79, 0xB3, 0x12, 0x8F,
++0x63, 0x74, 0x24, 0xF0, 0x90, 0x99, 0xD3, 0x74,
++0x08, 0xF0, 0x75, 0x45, 0x01, 0x75, 0x46, 0x9A,
++0x75, 0x47, 0x01, 0xF5, 0x48, 0x7B, 0x01, 0x7A,
++0x99, 0x79, 0xD6, 0x12, 0x69, 0xF5, 0x90, 0x99,
++0xD4, 0x74, 0x25, 0xF0, 0x90, 0x99, 0xF6, 0x74,
++0x08, 0x31, 0xA6, 0x12, 0xFA, 0x71, 0x7B, 0x01,
++0x7A, 0x99, 0x79, 0xD4, 0x12, 0x90, 0x35, 0x7F,
++0x04, 0x12, 0x04, 0x7E, 0x22, 0xD3, 0x10, 0xAF,
++0x01, 0xC3, 0xC0, 0xD0, 0x12, 0x02, 0x06, 0xFF,
++0x54, 0x01, 0xFE, 0x90, 0x93, 0x24, 0x12, 0xDE,
++0xC9, 0xFD, 0xEF, 0x54, 0xFB, 0x4D, 0xFF, 0x90,
++0x93, 0x24, 0xF1, 0xDF, 0x12, 0xDE, 0x77, 0xFF,
++0x90, 0x93, 0x24, 0x12, 0xDE, 0x89, 0xF1, 0xE7,
++0x12, 0xDE, 0x80, 0xFF, 0x90, 0x93, 0x24, 0x12,
++0xDE, 0x92, 0x12, 0x87, 0xE6, 0xFF, 0x54, 0x01,
++0xFE, 0x90, 0x93, 0x26, 0xE0, 0x54, 0xFE, 0x4E,
++0xF0, 0x91, 0x58, 0xFE, 0x54, 0x01, 0xFD, 0x90,
++0x93, 0x25, 0xE0, 0x54, 0xFE, 0x4D, 0xFD, 0xF0,
++0xEE, 0x54, 0x04, 0xFE, 0xED, 0x54, 0xFB, 0x4E,
++0xFE, 0xF0, 0x91, 0x58, 0xFD, 0x54, 0x08, 0xFC,
++0xEE, 0x54, 0xF7, 0x4C, 0xFE, 0x90, 0x93, 0x25,
++0xF0, 0xED, 0x54, 0x10, 0xFD, 0xEE, 0x54, 0xEF,
++0x4D, 0xFE, 0xF0, 0x91, 0x58, 0xFD, 0x54, 0x20,
++0xFC, 0xEE, 0x54, 0xDF, 0x4C, 0x90, 0x93, 0x25,
++0xF0, 0xEF, 0x54, 0x10, 0xFF, 0xA3, 0xE0, 0x54,
++0xEF, 0x4F, 0xFF, 0x12, 0x87, 0xE6, 0xFE, 0x54,
++0x20, 0xFC, 0xEF, 0x54, 0xDF, 0x4C, 0x90, 0x93,
++0x26, 0xF0, 0xED, 0x54, 0x40, 0xFF, 0x90, 0x93,
++0x25, 0xE0, 0x54, 0xBF, 0x12, 0x87, 0xA2, 0x54,
++0x07, 0xFF, 0x90, 0x93, 0x27, 0xE0, 0x54, 0xF8,
++0x4F, 0xF0, 0xEE, 0x54, 0x40, 0xFF, 0x90, 0x93,
++0x26, 0xE0, 0x54, 0xBF, 0x4F, 0x12, 0xC7, 0x89,
++0x12, 0xCF, 0xD3, 0x90, 0x93, 0x24, 0xE0, 0xC3,
++0x13, 0x54, 0x01, 0xFF, 0x12, 0xF4, 0xDC, 0xF1,
++0xA4, 0x54, 0x01, 0xFF, 0x12, 0xEE, 0xDD, 0x90,
++0x93, 0x25, 0x12, 0x97, 0xD9, 0x30, 0xE0, 0x1F,
++0x90, 0x93, 0x24, 0x12, 0xB4, 0xAE, 0x20, 0xE0,
++0x0E, 0xEF, 0xC3, 0x13, 0x20, 0xE0, 0x08, 0xE0,
++0x13, 0x13, 0x54, 0x3F, 0x30, 0xE0, 0x04, 0x7F,
++0x01, 0x80, 0x0A, 0x7F, 0x00, 0x80, 0x06, 0xF1,
++0xA4, 0x13, 0x54, 0x01, 0xFF, 0x12, 0xEE, 0x66,
++0x90, 0x93, 0x24, 0xE0, 0xC4, 0x54, 0x01, 0xFF,
++0x12, 0xF4, 0xE8, 0x90, 0x93, 0x24, 0xE0, 0xC4,
++0x13, 0x13, 0x54, 0x01, 0xFF, 0x12, 0xF4, 0xF6,
++0x90, 0x93, 0x24, 0xE0, 0x54, 0x01, 0xFF, 0x12,
++0xCC, 0xB6, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x12,
++0x02, 0x4C, 0x90, 0x9C, 0x90, 0x12, 0x82, 0x1E,
++0x90, 0x00, 0x01, 0x02, 0x02, 0x1F, 0x90, 0x9C,
++0x8D, 0x12, 0x82, 0x27, 0x90, 0x9C, 0x93, 0xE0,
++0xFF, 0xB4, 0x04, 0x1C, 0x90, 0x9C, 0x90, 0x12,
++0x8F, 0x6D, 0xFE, 0x91, 0xF6, 0xEE, 0x91, 0x4F,
++0xFE, 0x91, 0xF6, 0x90, 0x00, 0x01, 0xEE, 0x12,
++0x02, 0x5E, 0x90, 0x00, 0x02, 0xE4, 0x80, 0x20,
++0xEF, 0x64, 0x02, 0x70, 0x1E, 0x91, 0x52, 0x91,
++0xF5, 0xEF, 0x91, 0x4F, 0x44, 0x20, 0x54, 0x7F,
++0x91, 0xF5, 0x90, 0x00, 0x01, 0xB1, 0xCF, 0x12,
++0x8F, 0x6D, 0x91, 0xF5, 0x90, 0x00, 0x02, 0xEF,
++0x12, 0x02, 0x5E, 0x91, 0xF6, 0xE9, 0x24, 0x03,
++0xF9, 0xE4, 0x3A, 0xFA, 0x12, 0x02, 0x06, 0x44,
++0x20, 0x12, 0x02, 0x4C, 0x90, 0x9C, 0x90, 0x12,
++0x82, 0x1E, 0x12, 0x87, 0xE7, 0x91, 0xF5, 0x90,
++0x00, 0x04, 0xB1, 0xCF, 0x12, 0x82, 0x1E, 0x12,
++0x87, 0xA4, 0x91, 0xF5, 0x90, 0x00, 0x05, 0xB1,
++0xCF, 0x12, 0x82, 0x1E, 0x12, 0x87, 0xD2, 0x91,
++0xF5, 0x90, 0x00, 0x06, 0xB1, 0xCF, 0x12, 0x82,
++0x1E, 0x12, 0x87, 0x9C, 0x91, 0xF5, 0x90, 0x00,
++0x07, 0xEF, 0x02, 0x02, 0x5E, 0xFF, 0x90, 0x9C,
++0x8D, 0x02, 0x82, 0x1E, 0x90, 0x9C, 0x7B, 0x12,
++0x82, 0x27, 0x90, 0x9C, 0x84, 0xE0, 0xFF, 0x64,
++0x04, 0x70, 0x4C, 0xB1, 0xBF, 0x12, 0x02, 0x06,
++0xB1, 0xC8, 0xEE, 0x12, 0x02, 0x4C, 0x90, 0x9C,
++0x7B, 0x91, 0x55, 0xB1, 0xC8, 0x90, 0x00, 0x01,
++0xB1, 0xBB, 0x90, 0x00, 0x04, 0xB1, 0xC5, 0x90,
++0x00, 0x02, 0xB1, 0xBB, 0x90, 0x00, 0x05, 0xB1,
++0xC5, 0x90, 0x00, 0x03, 0xB1, 0xBB, 0x90, 0x00,
++0x06, 0xB1, 0xC5, 0x90, 0x00, 0x04, 0xB1, 0xBB,
++0x90, 0x00, 0x07, 0xB1, 0xC5, 0x90, 0x00, 0x05,
++0xB1, 0xBB, 0x12, 0x87, 0xA4, 0xFE, 0x90, 0x9C,
++0x81, 0x12, 0x82, 0x1E, 0xEE, 0x80, 0x60, 0xEF,
++0x64, 0x02, 0x70, 0x5E, 0xB1, 0xBF, 0x12, 0x87,
++0xE7, 0xFF, 0xB1, 0xC9, 0xEF, 0x12, 0x02, 0x4C,
++0xB1, 0xBF, 0x12, 0x02, 0x06, 0xFF, 0xB1, 0xC9,
++0x90, 0x00, 0x01, 0xEF, 0xB1, 0xBC, 0x12, 0x87,
++0xD2, 0xFF, 0xB1, 0xC9, 0x90, 0x00, 0x02, 0xEF,
++0xB1, 0xBC, 0x12, 0x87, 0x9C, 0xFF, 0xB1, 0xC9,
++0x90, 0x00, 0x03, 0xEF, 0xB1, 0xBC, 0x90, 0x00,
++0x06, 0x12, 0x02, 0x1F, 0xFF, 0xB1, 0xC9, 0x90,
++0x00, 0x04, 0xEF, 0xB1, 0xBC, 0x90, 0x00, 0x07,
++0x12, 0x02, 0x1F, 0xFF, 0xB1, 0xC9, 0x90, 0x00,
++0x05, 0xEF, 0xB1, 0xBC, 0x12, 0x87, 0xA4, 0xFF,
++0x90, 0x9C, 0x81, 0x12, 0x82, 0x1E, 0xEF, 0x12,
++0x02, 0x4C, 0x22, 0xEE, 0x12, 0x02, 0x5E, 0x90,
++0x9C, 0x7B, 0x02, 0x82, 0x1E, 0x12, 0x02, 0x1F,
++0xFE, 0x90, 0x9C, 0x7E, 0x02, 0x82, 0x1E, 0xEF,
++0x12, 0x02, 0x5E, 0x90, 0x9C, 0x90, 0x22, 0x90,
++0x9A, 0x42, 0x12, 0x82, 0x27, 0xF1, 0x8E, 0xD1,
++0x3E, 0x12, 0x04, 0x80, 0xF1, 0x8E, 0xD1, 0x37,
++0x12, 0x04, 0x80, 0xD1, 0x3E, 0xF1, 0x7D, 0x7A,
++0x9A, 0x79, 0x5A, 0xD1, 0x45, 0x90, 0x9C, 0x84,
++0xF1, 0x95, 0x91, 0xFC, 0xD1, 0x37, 0xF1, 0x7D,
++0x7A, 0x9A, 0x79, 0x59, 0xD1, 0x45, 0x90, 0x9C,
++0x84, 0xF0, 0x90, 0x9A, 0x45, 0x12, 0x82, 0x1E,
++0x91, 0xFC, 0xD1, 0x3E, 0x12, 0xE5, 0x17, 0x74,
++0x08, 0xF0, 0x7A, 0x9A, 0x79, 0x51, 0x12, 0xE5,
++0x21, 0x40, 0x11, 0xD1, 0x37, 0x90, 0x9C, 0x90,
++0xD1, 0x48, 0x90, 0x9C, 0x93, 0xF1, 0x95, 0x91,
++0x5E, 0x7F, 0x01, 0x22, 0x7F, 0x00, 0x22, 0x7B,
++0x01, 0x7A, 0x9A, 0x79, 0x51, 0x22, 0x7B, 0x01,
++0x7A, 0x9A, 0x79, 0x49, 0x22, 0x90, 0x9C, 0x81,
++0x12, 0x82, 0x27, 0x90, 0x9A, 0x48, 0xE0, 0x22,
++0xFF, 0x90, 0x9A, 0xF6, 0xF0, 0x7B, 0x01, 0x7A,
++0x9A, 0x79, 0xF7, 0x12, 0x02, 0x06, 0x90, 0x06,
++0x74, 0xF0, 0x91, 0x58, 0x90, 0x06, 0x75, 0x12,
++0x87, 0xE6, 0x90, 0x06, 0x76, 0x12, 0x87, 0xA3,
++0x90, 0x06, 0x77, 0xF0, 0x12, 0xF5, 0x48, 0x04,
++0x12, 0xF5, 0x3E, 0x02, 0x7C, 0x6A, 0x90, 0x9A,
++0xF1, 0xEF, 0xF0, 0xA3, 0xED, 0xF0, 0xA3, 0x12,
++0x82, 0x27, 0x90, 0x9A, 0xF3, 0x12, 0x8B, 0xE0,
++0xF1, 0x0C, 0x24, 0x02, 0xD1, 0x50, 0x90, 0x9A,
++0xF3, 0x12, 0x82, 0x1E, 0xE9, 0x24, 0x04, 0xF1,
++0x03, 0x24, 0x03, 0xD1, 0x50, 0x90, 0x9A, 0xF3,
++0x12, 0x82, 0x1E, 0xE9, 0x24, 0x08, 0xF1, 0x03,
++0x24, 0x04, 0xD1, 0x50, 0x90, 0x9A, 0xF3, 0x12,
++0x82, 0x1E, 0xE9, 0x24, 0x0C, 0xF1, 0x03, 0x24,
++0x05, 0xD1, 0x50, 0x90, 0x9A, 0xF2, 0xE0, 0xFD,
++0xB4, 0x02, 0x08, 0x90, 0x9A, 0xF1, 0xE0, 0x44,
++0x48, 0x80, 0x0A, 0xED, 0xB4, 0x04, 0x0A, 0x90,
++0x9A, 0xF1, 0xE0, 0x44, 0x50, 0x90, 0x9A, 0xF7,
++0xF0, 0x90, 0x9A, 0xF8, 0x74, 0x80, 0xF0, 0xA3,
++0x74, 0xFF, 0xF0, 0xA3, 0xF0, 0xF1, 0x18, 0xD1,
++0x50, 0x90, 0x9A, 0xF7, 0x74, 0xFF, 0xF1, 0xAD,
++0xF1, 0x18, 0x04, 0xD1, 0x50, 0x90, 0x06, 0x72,
++0xE4, 0xF0, 0x22, 0xF9, 0xE4, 0x3A, 0x8B, 0x45,
++0xF5, 0x46, 0x89, 0x47, 0x75, 0x48, 0x04, 0x7B,
++0x01, 0x7A, 0x9A, 0x79, 0xF7, 0x12, 0x69, 0xF5,
++0x90, 0x9A, 0xF1, 0xE0, 0x75, 0xF0, 0x08, 0xA4,
++0x22, 0x90, 0x9C, 0x60, 0x12, 0x82, 0x27, 0xC0,
++0x03, 0xC0, 0x02, 0xC0, 0x01, 0x7B, 0x01, 0x7A,
++0x9C, 0x79, 0x65, 0xF1, 0x7D, 0x7A, 0x9C, 0x79,
++0x6D, 0x90, 0x9C, 0x81, 0xF1, 0x9C, 0x90, 0x9C,
++0x84, 0xF0, 0xD0, 0x01, 0xD0, 0x02, 0xD0, 0x03,
++0x91, 0xFC, 0xED, 0x70, 0x19, 0xFF, 0xF1, 0x83,
++0xE0, 0xB4, 0xFF, 0x06, 0xF1, 0x83, 0xE4, 0xF0,
++0x80, 0x07, 0xF1, 0x83, 0xE0, 0x04, 0xF0, 0x80,
++0x05, 0x0F, 0xEF, 0xB4, 0x06, 0xE8, 0x7B, 0x01,
++0x7A, 0x9C, 0x79, 0x65, 0x90, 0x9C, 0x90, 0xF1,
++0x9C, 0x90, 0x9C, 0x93, 0xF0, 0x90, 0x9C, 0x60,
++0x12, 0x82, 0x1E, 0x81, 0x5E, 0x90, 0x9C, 0x7E,
++0x02, 0x82, 0x27, 0x74, 0x65, 0x2F, 0xF5, 0x82,
++0xE4, 0x34, 0x9C, 0xF5, 0x83, 0x22, 0x7E, 0x00,
++0x7F, 0x08, 0x7D, 0x00, 0x22, 0xF0, 0x90, 0x9A,
++0x42, 0x02, 0x82, 0x1E, 0x12, 0x82, 0x27, 0x90,
++0x9C, 0x64, 0xE0, 0x22, 0x90, 0x93, 0x24, 0xE0,
++0x13, 0x13, 0x22, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0,
++0xA3, 0xF0, 0xA3, 0xF0, 0x22, 0x12, 0xAD, 0xFB,
++0xE4, 0x90, 0x98, 0x41, 0xF1, 0xAD, 0x90, 0x95,
++0x93, 0xF1, 0xAB, 0xA3, 0xF1, 0xAB, 0x90, 0x95,
++0xA5, 0xF0, 0xA3, 0xF0, 0x90, 0x95, 0xE7, 0xF0,
++0xA3, 0xF0, 0x22, 0x90, 0x93, 0x24, 0x12, 0xDE,
++0x5E, 0x30, 0xE0, 0x02, 0xF1, 0xB5, 0x22, 0xF0,
++0xEE, 0x54, 0x08, 0xFE, 0xEF, 0x54, 0xF7, 0x4E,
++0xFF, 0xF0, 0x02, 0x02, 0x06, 0xF1, 0xD3, 0x90,
++0x93, 0x24, 0xE0, 0xFF, 0xC4, 0x54, 0x0F, 0x30,
++0xE0, 0x06, 0x12, 0xA0, 0x01, 0x12, 0xCA, 0x2D,
++0x22, 0x90, 0x01, 0x53, 0xE4, 0xF0, 0xFF, 0x12,
++0xFA, 0x10, 0xE4, 0xF0, 0x0F, 0xEF, 0xB4, 0x08,
++0xF6, 0x22, 0x90, 0x9A, 0x38, 0xEC, 0xF0, 0xA3,
++0xED, 0xF0, 0x90, 0x9A, 0x36, 0xEE, 0xF0, 0xA3,
++0xEF, 0xF0, 0xE4, 0x90, 0x9A, 0x5C, 0xF0, 0xEF,
++0x24, 0x24, 0xFF, 0xE4, 0x3E, 0xFE, 0xC0, 0x06,
++0x91, 0xAD, 0xD0, 0x06, 0xE4, 0xFB, 0xFA, 0x91,
++0x61, 0x4E, 0x60, 0x39, 0xE0, 0x24, 0x01, 0x71,
++0xC5, 0x51, 0x39, 0x90, 0x9A, 0x3B, 0x91, 0x96,
++0x90, 0x9A, 0x3B, 0x91, 0x81, 0xFE, 0xC3, 0x9F,
++0x50, 0x23, 0x90, 0x9A, 0x5E, 0xE0, 0x24, 0x02,
++0xFD, 0x71, 0xC6, 0xFC, 0xEE, 0x7E, 0x00, 0x2D,
++0x51, 0x36, 0x90, 0x9A, 0x3A, 0xE0, 0x24, 0x3C,
++0xF5, 0x82, 0xE4, 0x34, 0x9A, 0xF5, 0x83, 0xEF,
++0xF0, 0x91, 0x77, 0x80, 0xD3, 0x91, 0x9E, 0xC0,
++0x06, 0x91, 0xAD, 0xD0, 0x06, 0x7B, 0x03, 0x91,
++0x5E, 0x90, 0x9A, 0x37, 0xE0, 0x24, 0x22, 0x91,
++0xA4, 0x90, 0x9A, 0x5D, 0xF0, 0xA3, 0xEF, 0xF0,
++0x51, 0x3A, 0xEF, 0x20, 0xE4, 0x02, 0x21, 0x38,
++0x90, 0x9A, 0x5C, 0xE0, 0x04, 0xF0, 0x91, 0x9E,
++0xC0, 0x06, 0x91, 0xAD, 0xD0, 0x06, 0x7B, 0x30,
++0x91, 0x5E, 0x4E, 0x60, 0x3C, 0xE0, 0x24, 0x08,
++0x71, 0xC5, 0x51, 0x39, 0x91, 0x93, 0x91, 0x7E,
++0xC3, 0x9F, 0x50, 0x2D, 0x90, 0x9A, 0x5E, 0xE0,
++0x24, 0x0D, 0x71, 0xC5, 0x51, 0x39, 0x90, 0x9A,
++0x5F, 0xEF, 0xF0, 0xBF, 0x02, 0x09, 0x90, 0x9A,
++0x5C, 0xE0, 0x24, 0x20, 0xF0, 0x80, 0x0E, 0x90,
++0x9A, 0x5F, 0xE0, 0xB4, 0x04, 0x07, 0x90, 0x9A,
++0x5C, 0xE0, 0x24, 0x40, 0xF0, 0x91, 0x6D, 0x80,
++0xCD, 0x91, 0x9E, 0xC0, 0x06, 0x91, 0xAD, 0xD0,
++0x06, 0x7B, 0xDD, 0x7A, 0x00, 0x7D, 0x01, 0x91,
++0x62, 0x4E, 0x60, 0x41, 0xE0, 0x24, 0x0C, 0x71,
++0xC5, 0x51, 0x39, 0x91, 0x93, 0x91, 0x7E, 0xC3,
++0x9F, 0x50, 0x32, 0x90, 0x9A, 0x5E, 0xE0, 0x24,
++0x11, 0x71, 0xC5, 0x51, 0x39, 0x90, 0x9A, 0x5F,
++0xEF, 0xF0, 0xBF, 0x02, 0x09, 0x90, 0x9A, 0x5C,
++0xE0, 0x24, 0x02, 0xF0, 0x80, 0x0E, 0x90, 0x9A,
++0x5F, 0xE0, 0xB4, 0x04, 0x07, 0x90, 0x9A, 0x5C,
++0xE0, 0x24, 0x04, 0xF0, 0x91, 0x6D, 0x80, 0xCD,
++0xE4, 0x90, 0x9A, 0x5C, 0xF0, 0x90, 0x95, 0xE9,
++0xE0, 0x90, 0x04, 0xFD, 0x91, 0x97, 0x90, 0x95,
++0xE9, 0x91, 0x81, 0xFE, 0xC3, 0x9F, 0x50, 0x5C,
++0x12, 0xFB, 0x7D, 0xF5, 0x83, 0xF1, 0xDB, 0x6F,
++0x70, 0x4E, 0x90, 0x04, 0xFC, 0xE0, 0x04, 0xF0,
++0x90, 0x9A, 0x3A, 0xE0, 0x24, 0x09, 0xF5, 0x82,
++0xE4, 0x34, 0x96, 0xF5, 0x83, 0xE0, 0xFF, 0x90,
++0x9A, 0x5C, 0xE0, 0xFD, 0x4F, 0x60, 0x04, 0xED,
++0x5F, 0x60, 0x2D, 0xEE, 0xFF, 0x7E, 0x00, 0xC0,
++0x06, 0xC0, 0x07, 0x90, 0x9A, 0x3A, 0xE0, 0x75,
++0xF0, 0x20, 0xA4, 0x24, 0x31, 0xF9, 0x74, 0x96,
++0xF1, 0x85, 0x7D, 0x01, 0xD0, 0x07, 0xD0, 0x06,
++0x12, 0x83, 0xDC, 0xEF, 0x70, 0x0A, 0x90, 0x01,
++0xC7, 0x74, 0x55, 0xF1, 0x6D, 0x12, 0x9F, 0xEF,
++0x91, 0x77, 0x80, 0x9A, 0xE4, 0x90, 0x9A, 0x3A,
++0xF0, 0x90, 0x9A, 0x3A, 0xE0, 0xFF, 0xC3, 0x94,
++0x03, 0x50, 0x5E, 0xA3, 0xE0, 0xFE, 0x60, 0x55,
++0xEF, 0x75, 0xF0, 0x21, 0xA4, 0x24, 0x26, 0xF5,
++0x82, 0xE4, 0x34, 0x9B, 0xF5, 0x83, 0xE0, 0xFF,
++0xEE, 0x6F, 0x70, 0x41, 0x90, 0x04, 0xFC, 0xE0,
++0x04, 0xF0, 0x90, 0x9A, 0x3B, 0xE0, 0xFF, 0x7E,
++0x00, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x9A, 0x3A,
++0xE0, 0x75, 0xF0, 0x21, 0xA4, 0x24, 0x27, 0xF9,
++0x74, 0x9B, 0xF1, 0x85, 0x7D, 0x01, 0xD0, 0x07,
++0xD0, 0x06, 0x12, 0x83, 0xDC, 0xEF, 0x70, 0x15,
++0x90, 0x01, 0xC7, 0x74, 0x24, 0xF1, 0x6D, 0x12,
++0xD5, 0xE5, 0x30, 0xE0, 0x02, 0x11, 0x01, 0xF1,
++0x7F, 0xE4, 0xFF, 0xD1, 0xC7, 0x91, 0x77, 0x80,
++0x98, 0x22, 0x90, 0x9A, 0x36, 0xE0, 0xFD, 0x90,
++0x9A, 0x35, 0xE0, 0x2D, 0xFD, 0x90, 0x9A, 0x34,
++0xE0, 0x34, 0x00, 0xCD, 0x24, 0x10, 0xCD, 0x34,
++0x00, 0xFC, 0x7E, 0x00, 0xED, 0x2F, 0xFF, 0xEE,
++0x3C, 0xFE, 0x90, 0x8A, 0xE9, 0xE0, 0xFC, 0xA3,
++0xE0, 0xF5, 0x82, 0x8C, 0x83, 0xE4, 0xFD, 0x02,
++0x04, 0x7E, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0,
++0xD0, 0x90, 0x06, 0x31, 0xE0, 0x54, 0xEF, 0x44,
++0x08, 0xF0, 0xED, 0x2F, 0xFF, 0xE4, 0x3E, 0xFE,
++0x7C, 0x00, 0xEF, 0x24, 0x08, 0x12, 0xFB, 0x32,
++0x7E, 0x00, 0x7F, 0xE3, 0x7D, 0x00, 0x7B, 0x01,
++0x7A, 0x94, 0x79, 0x39, 0x12, 0x04, 0x80, 0x90,
++0x9A, 0x3E, 0xE0, 0x24, 0x01, 0x71, 0xBD, 0x51,
++0x39, 0x90, 0x94, 0x3A, 0xEF, 0xF0, 0x90, 0x9A,
++0x3E, 0xE0, 0x24, 0x04, 0x71, 0xBD, 0x51, 0x39,
++0x90, 0x94, 0x3D, 0xEF, 0xF0, 0x90, 0x9A, 0x3E,
++0xE0, 0x24, 0x05, 0x71, 0xBD, 0x51, 0x39, 0x90,
++0x94, 0x3E, 0xEF, 0xF0, 0x90, 0x9A, 0x3E, 0xE0,
++0x24, 0x06, 0x71, 0xBD, 0x51, 0x39, 0x90, 0x94,
++0x3F, 0xEF, 0xF0, 0x90, 0x9A, 0x3E, 0xE0, 0x24,
++0x07, 0x71, 0xBD, 0x51, 0x39, 0x90, 0x94, 0x40,
++0xEF, 0xF0, 0x90, 0x9A, 0x3E, 0xE0, 0x24, 0x08,
++0x71, 0xBD, 0x51, 0x39, 0x90, 0x94, 0x41, 0xEF,
++0xF0, 0xE4, 0x90, 0x9A, 0x3C, 0xF0, 0xD1, 0x36,
++0x94, 0x08, 0x50, 0x1C, 0x90, 0x9A, 0x3E, 0xE0,
++0x24, 0x09, 0xFD, 0x90, 0x9A, 0x3D, 0xE0, 0x51,
++0x2F, 0x90, 0x9A, 0x3C, 0xE0, 0x24, 0x42, 0xF5,
++0x82, 0xE4, 0x34, 0x94, 0x91, 0x88, 0x80, 0xDE,
++0xE4, 0x90, 0x9A, 0x3C, 0xF0, 0xD1, 0x36, 0x94,
++0x02, 0x50, 0x1C, 0x90, 0x9A, 0x3E, 0xE0, 0x24,
++0x61, 0xFD, 0x90, 0x9A, 0x3D, 0xE0, 0x51, 0x2F,
++0x90, 0x9A, 0x3C, 0xE0, 0x24, 0x9A, 0xF5, 0x82,
++0xE4, 0x34, 0x94, 0x91, 0x88, 0x80, 0xDE, 0xE4,
++0x90, 0x9A, 0x3C, 0xF0, 0xD1, 0x36, 0x94, 0x10,
++0x50, 0x1C, 0x90, 0x9A, 0x3E, 0xE0, 0x24, 0x31,
++0xFD, 0x90, 0x9A, 0x3D, 0xE0, 0x51, 0x2F, 0x90,
++0x9A, 0x3C, 0xE0, 0x24, 0x6A, 0xF5, 0x82, 0xE4,
++0x34, 0x94, 0x91, 0x88, 0x80, 0xDE, 0xE4, 0x90,
++0x9A, 0x3C, 0xF0, 0x90, 0x94, 0x9B, 0xE0, 0xFF,
++0x90, 0x9A, 0x3C, 0xE0, 0xFE, 0xC3, 0x9F, 0x50,
++0x1F, 0x90, 0x9A, 0x3E, 0xE0, 0x24, 0x63, 0xFD,
++0x71, 0xBE, 0xFC, 0xEE, 0x7E, 0x00, 0x2D, 0x51,
++0x36, 0x90, 0x9A, 0x3C, 0xE0, 0x24, 0x9C, 0xF5,
++0x82, 0xE4, 0x34, 0x94, 0x91, 0x88, 0x80, 0xD3,
++0x90, 0x94, 0x3E, 0x12, 0xF3, 0x67, 0x90, 0x9A,
++0x3A, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x30, 0xE3,
++0x0D, 0x90, 0x01, 0xC7, 0x74, 0x03, 0xF0, 0x7F,
++0x01, 0x12, 0xAD, 0x64, 0x80, 0x20, 0x7E, 0x00,
++0x90, 0x9A, 0x3B, 0xE0, 0x54, 0x07, 0xFF, 0x64,
++0x01, 0x60, 0x05, 0xEF, 0x64, 0x02, 0x70, 0x0E,
++0xE4, 0xFD, 0x12, 0xEE, 0x2D, 0x90, 0x06, 0x31,
++0xE0, 0x54, 0xF7, 0x44, 0x10, 0xF0, 0x7F, 0x00,
++0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xFF, 0x90, 0x9A,
++0x3D, 0xE0, 0x34, 0x00, 0x22, 0xFF, 0x90, 0x9A,
++0x5D, 0xE0, 0x34, 0x00, 0x22, 0xF1, 0xE3, 0xA3,
++0xEA, 0xF0, 0xA3, 0xEB, 0xF0, 0xC3, 0x90, 0x9A,
++0x67, 0xE0, 0x94, 0x01, 0x90, 0x9A, 0x66, 0xE0,
++0x94, 0x00, 0x50, 0x02, 0x80, 0x74, 0xE4, 0x90,
++0x9A, 0x6A, 0xF0, 0xA3, 0xF0, 0xF1, 0x76, 0x51,
++0x3A, 0x90, 0x9A, 0x64, 0xE0, 0x70, 0x03, 0xA3,
++0xE0, 0x6F, 0x70, 0x1D, 0x90, 0x9A, 0x62, 0xE0,
++0x24, 0x02, 0xFF, 0x90, 0x9A, 0x61, 0xE0, 0x34,
++0x00, 0xFE, 0x90, 0x9A, 0x63, 0xE0, 0xFD, 0x12,
++0xF6, 0xFB, 0xBF, 0x01, 0x02, 0xE1, 0x76, 0x80,
++0x00, 0x90, 0x9A, 0x62, 0xE0, 0x24, 0x01, 0xFF,
++0x90, 0x9A, 0x61, 0xE0, 0x34, 0x00, 0x51, 0x39,
++0x7E, 0x00, 0x90, 0x9A, 0x68, 0xEE, 0xF0, 0xA3,
++0xEF, 0xF0, 0x24, 0x02, 0xFF, 0xEE, 0x33, 0xFE,
++0x90, 0x9A, 0x61, 0x8F, 0xF0, 0x12, 0x02, 0xE7,
++0x90, 0x9A, 0x6A, 0xEE, 0x8F, 0xF0, 0x12, 0x02,
++0xE7, 0x90, 0x9A, 0x66, 0xF1, 0xEF, 0x90, 0x9A,
++0x6B, 0xE0, 0x9F, 0x90, 0x9A, 0x6A, 0xE0, 0x9E,
++0x40, 0x93, 0xE4, 0xFE, 0xFF, 0x22, 0x7A, 0x00,
++0xE4, 0xFD, 0x71, 0xCD, 0x90, 0x9A, 0x5D, 0xEE,
++0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0x90, 0x9A, 0x5D,
++0xE4, 0x75, 0xF0, 0x04, 0x12, 0x02, 0xE7, 0x90,
++0x9A, 0x3A, 0xE0, 0x04, 0xF0, 0x22, 0x90, 0x9A,
++0x60, 0xE0, 0xFF, 0x90, 0x9A, 0x3A, 0xE0, 0x22,
++0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x9A, 0x3C, 0xE0,
++0x04, 0xF0, 0x22, 0x90, 0x9A, 0x60, 0xEF, 0xF0,
++0xE4, 0x90, 0x9A, 0x3A, 0xF0, 0x22, 0x90, 0x9A,
++0x37, 0xE0, 0x24, 0x24, 0xFF, 0x90, 0x9A, 0x36,
++0xE0, 0x34, 0x00, 0xFE, 0x22, 0x90, 0x9A, 0x39,
++0xE0, 0x24, 0xDC, 0xFE, 0x90, 0x9A, 0x38, 0xE0,
++0x34, 0xFF, 0x90, 0x9A, 0x66, 0xF0, 0xA3, 0xCE,
++0xF0, 0x22, 0x12, 0xE7, 0x60, 0xA3, 0xED, 0xF0,
++0x12, 0xFB, 0xAA, 0x7A, 0x80, 0x79, 0x80, 0x7E,
++0x00, 0x7F, 0x06, 0x12, 0x01, 0xE0, 0x78, 0x43,
++0x7C, 0x9A, 0x7D, 0x01, 0x7B, 0xFF, 0x7A, 0x80,
++0x79, 0x86, 0x7E, 0x00, 0x7F, 0x04, 0x12, 0x01,
++0xE0, 0x78, 0x47, 0x7C, 0x9A, 0x7D, 0x01, 0x7B,
++0xFF, 0x7A, 0x80, 0x79, 0x8A, 0x7E, 0x00, 0x7F,
++0x04, 0x12, 0x01, 0xE0, 0xE4, 0x90, 0x9A, 0x4C,
++0xF0, 0xD1, 0x24, 0xCF, 0x24, 0x06, 0xCF, 0x34,
++0x00, 0x51, 0x39, 0xEF, 0x64, 0x08, 0x60, 0x02,
++0xC1, 0x0C, 0xD1, 0x24, 0xCF, 0x24, 0x07, 0xCF,
++0x34, 0x00, 0x51, 0x39, 0xEF, 0x64, 0x06, 0x60,
++0x02, 0xC1, 0x0C, 0x90, 0x9A, 0x4C, 0x04, 0xF0,
++0xE4, 0x90, 0x9A, 0x4B, 0xF0, 0xD1, 0x12, 0x94,
++0x06, 0x50, 0x17, 0x90, 0x9A, 0x35, 0xE0, 0x24,
++0x0A, 0xFD, 0x90, 0x9A, 0x34, 0xE0, 0x51, 0x2F,
++0x90, 0x9A, 0x4B, 0x12, 0xF3, 0x78, 0xD1, 0x19,
++0x80, 0xE3, 0x78, 0x37, 0x7C, 0x9A, 0x7D, 0x01,
++0x7B, 0x01, 0x7A, 0x93, 0x79, 0x38, 0x12, 0xE7,
++0x4F, 0x60, 0x02, 0xC1, 0x0C, 0x90, 0x9A, 0x4B,
++0xF0, 0xD1, 0x12, 0x94, 0x04, 0x50, 0x18, 0xF1,
++0x8F, 0xD1, 0x2F, 0xCD, 0x24, 0x20, 0x51, 0x2E,
++0x90, 0x9A, 0x4B, 0xE0, 0x24, 0x47, 0xF5, 0x82,
++0xE4, 0x34, 0x9A, 0xD1, 0x19, 0x80, 0xE2, 0x78,
++0x47, 0x7C, 0x9A, 0xF1, 0xF6, 0xEF, 0x70, 0x7B,
++0x90, 0x06, 0x30, 0xE0, 0x44, 0x01, 0x54, 0xDF,
++0xF0, 0x90, 0x93, 0x26, 0xE0, 0x30, 0xE0, 0x02,
++0x80, 0x10, 0x90, 0x98, 0x35, 0xE0, 0xB4, 0x02,
++0x12, 0x90, 0x93, 0x25, 0x12, 0x97, 0xD9, 0x20,
++0xE0, 0x09, 0x90, 0x01, 0xC7, 0x74, 0x09, 0xF1,
++0x6D, 0x80, 0x59, 0xE4, 0x90, 0x9A, 0x4B, 0xF0,
++0xD1, 0x12, 0x94, 0x06, 0x50, 0x0C, 0x51, 0x1A,
++0x90, 0x9A, 0x4B, 0x12, 0xF3, 0x6F, 0xD1, 0x19,
++0x80, 0xEE, 0xE4, 0x90, 0x9A, 0x4B, 0xF0, 0xD1,
++0x12, 0x94, 0x04, 0x50, 0x18, 0xF1, 0x8F, 0xD1,
++0x2F, 0xCD, 0x24, 0x16, 0x51, 0x2E, 0x90, 0x9A,
++0x4B, 0xE0, 0x24, 0x43, 0xF5, 0x82, 0xE4, 0x34,
++0x9A, 0xD1, 0x19, 0x80, 0xE2, 0x12, 0x95, 0x05,
++0x7B, 0x01, 0x7A, 0x9A, 0x79, 0x3D, 0x12, 0xFB,
++0x1A, 0xF0, 0x7A, 0x9A, 0x79, 0x43, 0x12, 0x8B,
++0xEA, 0x80, 0x09, 0x90, 0x06, 0x30, 0xE0, 0x44,
++0x21, 0x54, 0xEF, 0xF0, 0x90, 0x9A, 0x4C, 0xE0,
++0xFF, 0x22, 0x90, 0x9A, 0x4B, 0xE0, 0xFF, 0xC3,
++0x22, 0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x9A, 0x4B,
++0xE0, 0x04, 0xF0, 0x22, 0x90, 0x9A, 0x36, 0xE0,
++0xFF, 0x90, 0x9A, 0x35, 0xE0, 0x2F, 0xFF, 0x90,
++0x9A, 0x34, 0xE0, 0x34, 0x00, 0x22, 0x90, 0x9A,
++0x3C, 0xE0, 0xFF, 0xC3, 0x22, 0x90, 0x9A, 0x3B,
++0xF1, 0xE6, 0x78, 0x3F, 0x7C, 0x9A, 0x7D, 0x01,
++0x7B, 0xFF, 0x7A, 0x80, 0x79, 0xBA, 0x7E, 0x00,
++0x7F, 0x04, 0x12, 0x01, 0xE0, 0x90, 0x9A, 0x3D,
++0xE0, 0xFF, 0x90, 0x9A, 0x3C, 0xE0, 0x2F, 0x12,
++0xFB, 0x04, 0x90, 0x9A, 0x43, 0xF0, 0xA3, 0xEF,
++0xF0, 0x24, 0x06, 0xFF, 0xE4, 0x3E, 0x51, 0x39,
++0xEF, 0x64, 0x08, 0x70, 0x51, 0x90, 0x9A, 0x44,
++0xE0, 0x24, 0x07, 0xFF, 0x90, 0x9A, 0x43, 0xE0,
++0x34, 0x00, 0x51, 0x39, 0xEF, 0x70, 0x3F, 0x90,
++0x9A, 0x3E, 0xF0, 0x90, 0x9A, 0x3E, 0xE0, 0xFF,
++0xC3, 0x94, 0x04, 0x50, 0x24, 0x90, 0x9A, 0x44,
++0xE0, 0x24, 0x18, 0xFD, 0x90, 0x9A, 0x43, 0xE0,
++0x51, 0x2F, 0x90, 0x9A, 0x3E, 0xE0, 0x24, 0x3F,
++0xF5, 0x82, 0xE4, 0x34, 0x9A, 0xF5, 0x83, 0xEF,
++0xF0, 0x90, 0x9A, 0x3E, 0xE0, 0x04, 0xF0, 0x80,
++0xD2, 0x78, 0x3F, 0x7C, 0x9A, 0xF1, 0xF6, 0xEF,
++0x7F, 0x00, 0x70, 0x02, 0x7F, 0x01, 0x22, 0xD3,
++0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x9C,
++0xE8, 0xEF, 0xF0, 0x90, 0x93, 0x04, 0x12, 0xB4,
++0xAE, 0x30, 0xE0, 0x39, 0x12, 0xB7, 0xD5, 0x60,
++0x10, 0x12, 0xB7, 0xCB, 0x40, 0x0B, 0xE4, 0x7F,
++0x0A, 0xFE, 0xFD, 0xFC, 0x90, 0x95, 0xF5, 0x80,
++0x09, 0xE4, 0x7F, 0x0A, 0xFE, 0xFD, 0xFC, 0x90,
++0x95, 0xED, 0x12, 0x82, 0x12, 0x12, 0x80, 0xDB,
++0xC0, 0x07, 0x90, 0x93, 0x0A, 0xE0, 0xFB, 0xE4,
++0xFA, 0xF9, 0xF8, 0xD0, 0x07, 0x12, 0x81, 0x66,
++0x90, 0x93, 0x0B, 0xEF, 0xF0, 0x90, 0x9C, 0xE8,
++0xE0, 0x64, 0x01, 0x70, 0x1B, 0xF1, 0x65, 0x60,
++0x0A, 0xF1, 0x5E, 0x12, 0x7C, 0x05, 0x12, 0xB7,
++0xB9, 0x80, 0x08, 0xF1, 0x5E, 0x12, 0x7C, 0x3B,
++0x12, 0xF9, 0xB2, 0x12, 0x79, 0xD4, 0x80, 0x1D,
++0xF1, 0x65, 0x60, 0x07, 0xF1, 0x5E, 0x12, 0x7C,
++0x05, 0x80, 0x05, 0xF1, 0x5E, 0x12, 0x7C, 0x3B,
++0x7D, 0x02, 0x7F, 0x02, 0x12, 0x7C, 0x74, 0x12,
++0xB7, 0xA2, 0x12, 0x7B, 0xCC, 0xD0, 0xD0, 0x92,
++0xAF, 0x22, 0xF0, 0x90, 0x01, 0x3F, 0x74, 0x10,
++0xF0, 0xFD, 0x7F, 0x03, 0x22, 0x90, 0x93, 0x0A,
++0xE0, 0x90, 0x01, 0x3F, 0x22, 0xF0, 0x90, 0x93,
++0x31, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0x90, 0x9A,
++0x61, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x22, 0x12,
++0xFB, 0x0D, 0x02, 0x04, 0x80, 0x35, 0xF0, 0xFA,
++0x7B, 0x01, 0x78, 0x3C, 0x7C, 0x9A, 0x22, 0x90,
++0x9A, 0x36, 0xE0, 0xFD, 0x90, 0x9A, 0x35, 0xE0,
++0x2D, 0xFD, 0x22, 0x12, 0xE7, 0x60, 0x12, 0xC7,
++0xE1, 0xE4, 0x90, 0x9A, 0x3B, 0xF0, 0xF0, 0x90,
++0x9A, 0x37, 0xF1, 0xDB, 0xC3, 0x9F, 0x50, 0x2A,
++0xF1, 0x8F, 0xD1, 0x2F, 0xFC, 0xEF, 0x12, 0xFB,
++0x69, 0xEE, 0x7E, 0x00, 0x2D, 0x51, 0x36, 0x90,
++0x9A, 0x38, 0x12, 0x82, 0x1E, 0x90, 0x9A, 0x3B,
++0xE0, 0xF5, 0x82, 0x75, 0x83, 0x00, 0xEF, 0x12,
++0x02, 0x5E, 0x90, 0x9A, 0x3B, 0xE0, 0x04, 0xF0,
++0x80, 0xCD, 0x22, 0xE0, 0xFF, 0x90, 0x9A, 0x3B,
++0xE0, 0xFE, 0x22, 0x90, 0x9A, 0x61, 0xEE, 0xF0,
++0xA3, 0xEF, 0xF0, 0xA3, 0xED, 0xF0, 0x22, 0xE0,
++0xFE, 0xA3, 0xE0, 0xFF, 0xC3, 0x22, 0x7D, 0x01,
++0x7B, 0x01, 0x7A, 0x93, 0x79, 0x53, 0x7E, 0x00,
++0x7F, 0x04, 0x02, 0x83, 0xDC, 0x12, 0x02, 0x06,
++0x54, 0x01, 0xFF, 0x90, 0x98, 0x69, 0xE0, 0x54,
++0xFE, 0x4F, 0xF0, 0x22, 0x12, 0xDE, 0x6E, 0xFF,
++0x54, 0x7F, 0x90, 0x88, 0x36, 0xF0, 0xEF, 0x11,
++0xAE, 0xA3, 0xF0, 0x12, 0x9C, 0x58, 0xFD, 0x54,
++0xF0, 0xC4, 0x54, 0x0F, 0xFF, 0x90, 0x88, 0x34,
++0xE0, 0x54, 0xF0, 0x12, 0x87, 0xA2, 0xFC, 0x54,
++0x01, 0x25, 0xE0, 0xFF, 0x90, 0x88, 0x31, 0xE0,
++0x54, 0xFD, 0x4F, 0xF0, 0xEC, 0x54, 0x04, 0xC3,
++0x13, 0xFF, 0x90, 0x88, 0x33, 0xE0, 0x54, 0xFD,
++0x4F, 0xF0, 0xED, 0x54, 0x0F, 0xC4, 0x54, 0xF0,
++0xFF, 0xA3, 0xE0, 0x54, 0x0F, 0x12, 0x87, 0xE5,
++0x90, 0x88, 0x35, 0x12, 0x87, 0xD1, 0xFD, 0x90,
++0x8A, 0x89, 0x12, 0x90, 0x47, 0x7F, 0x02, 0x12,
++0x04, 0x7E, 0x90, 0x9B, 0x89, 0xE0, 0x60, 0x0C,
++0x12, 0xFB, 0x86, 0x90, 0x8A, 0x89, 0x12, 0x90,
++0x47, 0x12, 0xFB, 0xBC, 0x12, 0xC7, 0x9B, 0x12,
++0x5C, 0x5F, 0x90, 0x88, 0x36, 0xE0, 0xB4, 0x01,
++0x07, 0x90, 0x88, 0x33, 0xE0, 0x54, 0xFB, 0xF0,
++0x12, 0xDC, 0x9B, 0xF0, 0x90, 0x88, 0x36, 0x12,
++0xFA, 0xF6, 0x12, 0x97, 0xF1, 0x90, 0x01, 0xBE,
++0xF0, 0x22, 0x90, 0x93, 0x2A, 0xE0, 0xC4, 0x13,
++0x13, 0x13, 0x54, 0x01, 0x22, 0xD3, 0x10, 0xAF,
++0x01, 0xC3, 0xC0, 0xD0, 0xE4, 0x90, 0x9C, 0x08,
++0xF0, 0xA3, 0x74, 0x08, 0xF0, 0xA3, 0x12, 0xCA,
++0x89, 0x90, 0x9C, 0x0F, 0xF0, 0xA3, 0xF0, 0x90,
++0x9C, 0x19, 0x12, 0xF6, 0xD3, 0x12, 0xC7, 0x92,
++0x90, 0x9B, 0xFD, 0x12, 0xFB, 0xA1, 0x90, 0x9C,
++0x06, 0xF0, 0x90, 0x93, 0x24, 0xE0, 0x20, 0xE0,
++0x02, 0x81, 0x30, 0xE4, 0x90, 0x9C, 0x05, 0xF0,
++0x90, 0x9C, 0x06, 0xE0, 0xFF, 0x90, 0x9C, 0x05,
++0xE0, 0xC3, 0x9F, 0x40, 0x02, 0x81, 0x30, 0x12,
++0xFB, 0x8F, 0xEC, 0xFF, 0x90, 0xFD, 0x11, 0xF0,
++0x90, 0x9C, 0x0F, 0xEF, 0xF0, 0x12, 0xF6, 0xDD,
++0x3E, 0x54, 0x3F, 0xFE, 0x90, 0x9B, 0xFF, 0xF0,
++0xA3, 0xEF, 0xF0, 0x90, 0x9C, 0x0B, 0xEE, 0x12,
++0xFA, 0x80, 0x30, 0xE0, 0x0A, 0xC3, 0x13, 0x20,
++0xE0, 0x05, 0x12, 0xFA, 0xE7, 0x80, 0x02, 0x7E,
++0x00, 0xEF, 0x24, 0x18, 0x2E, 0xFF, 0x90, 0x9C,
++0x10, 0xF0, 0x90, 0x9B, 0xFE, 0xE0, 0x2F, 0xFF,
++0x90, 0x9B, 0xFD, 0xE0, 0x34, 0x00, 0xFE, 0x90,
++0x9C, 0x01, 0xF0, 0xA3, 0xEF, 0xF0, 0x12, 0xA2,
++0x3A, 0xC0, 0x07, 0x90, 0x9C, 0x01, 0x91, 0x4F,
++0x7D, 0x01, 0x12, 0x04, 0x7E, 0xC0, 0x07, 0x90,
++0x9C, 0x01, 0x91, 0x4F, 0x7D, 0x04, 0x12, 0x04,
++0x7E, 0xAB, 0x07, 0xD0, 0x05, 0xD0, 0x07, 0x12,
++0x8E, 0xC9, 0x90, 0x9C, 0x07, 0xEF, 0xF0, 0x91,
++0x43, 0x12, 0xA2, 0x3A, 0xEF, 0x54, 0xFC, 0x90,
++0x9C, 0x03, 0xF0, 0x90, 0x9C, 0x10, 0xE0, 0xFF,
++0x90, 0x9B, 0xFF, 0xE4, 0x8F, 0xF0, 0x12, 0x02,
++0xE7, 0x12, 0xFB, 0x98, 0x12, 0xCF, 0x64, 0x90,
++0x9B, 0xFF, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x90,
++0x9B, 0xFD, 0x91, 0x4F, 0x7D, 0x0F, 0x12, 0x04,
++0x7E, 0x90, 0x9C, 0x04, 0xEF, 0xF0, 0x90, 0x9B,
++0x89, 0xE0, 0x60, 0x3B, 0x90, 0x9C, 0x03, 0xE0,
++0x24, 0xB0, 0x60, 0x16, 0x24, 0xD0, 0x60, 0x02,
++0x61, 0x52, 0x12, 0xD5, 0xE5, 0x20, 0xE0, 0x18,
++0x12, 0xDC, 0x82, 0x20, 0xE0, 0x02, 0x61, 0x52,
++0x80, 0x0E, 0x12, 0xD5, 0xE5, 0x20, 0xE0, 0x08,
++0x12, 0xDC, 0x82, 0x20, 0xE0, 0x02, 0x61, 0x52,
++0x91, 0x43, 0x90, 0x9C, 0x0B, 0xE0, 0xFC, 0xA3,
++0xE0, 0xFD, 0x12, 0xE7, 0x69, 0x61, 0x52, 0x90,
++0x9C, 0x03, 0xE0, 0x24, 0xF8, 0x60, 0x35, 0x24,
++0x80, 0x60, 0x31, 0x24, 0xC8, 0x60, 0x06, 0x24,
++0x20, 0x60, 0x02, 0x61, 0x52, 0x90, 0x93, 0x29,
++0x11, 0xAD, 0x20, 0xE0, 0x02, 0x61, 0x52, 0x91,
++0x43, 0xB1, 0x12, 0xEF, 0x70, 0x02, 0x61, 0x52,
++0x91, 0x43, 0x12, 0xE7, 0x0C, 0xEF, 0x70, 0x02,
++0x61, 0x52, 0x90, 0x9C, 0x03, 0xE0, 0xFF, 0x12,
++0xE6, 0xFA, 0x61, 0x52, 0x12, 0xFA, 0xC8, 0xFF,
++0x12, 0xE7, 0xB8, 0xAC, 0x07, 0x91, 0x35, 0xAB,
++0x04, 0xC0, 0x03, 0x7B, 0x01, 0x7A, 0x9C, 0x79,
++0x11, 0x90, 0x9A, 0x38, 0x12, 0x82, 0x27, 0xD0,
++0x03, 0x12, 0xA7, 0x9B, 0x91, 0x43, 0xB1, 0x12,
++0x90, 0x9A, 0x38, 0xEF, 0xF0, 0x7B, 0x01, 0x7A,
++0x9C, 0x79, 0x11, 0x12, 0xFA, 0xC8, 0xFD, 0x12,
++0xE5, 0x2A, 0xEF, 0x70, 0x02, 0x61, 0x52, 0x90,
++0x93, 0x24, 0xD1, 0x03, 0x30, 0xE0, 0x5F, 0x90,
++0x9C, 0x07, 0xE0, 0xFF, 0x90, 0x9C, 0x02, 0xE0,
++0x2F, 0xFF, 0x90, 0x9C, 0x01, 0xE0, 0x34, 0x00,
++0xCF, 0x24, 0x08, 0xCF, 0x34, 0x00, 0xFE, 0x90,
++0x9C, 0x0D, 0xF0, 0xA3, 0xEF, 0xF0, 0x12, 0xA2,
++0x3A, 0xEF, 0x64, 0x45, 0x70, 0x38, 0xB1, 0x09,
++0x12, 0xF7, 0xAA, 0xEF, 0x64, 0x01, 0x70, 0x2E,
++0xB1, 0x09, 0x12, 0xE7, 0x82, 0xEF, 0x64, 0x01,
++0x70, 0x24, 0x90, 0x9C, 0x19, 0x04, 0xB1, 0x08,
++0xA3, 0xE0, 0xFD, 0x12, 0xF7, 0x08, 0xEF, 0x70,
++0x0D, 0x90, 0x9C, 0x0F, 0xE0, 0xFD, 0x90, 0xFD,
++0x11, 0xB1, 0x08, 0x12, 0xF7, 0x63, 0x90, 0x9C,
++0x0F, 0xE0, 0x90, 0xFD, 0x11, 0xF0, 0x91, 0x43,
++0xB1, 0x12, 0xEF, 0x60, 0x30, 0x91, 0x35, 0x90,
++0x9C, 0x0A, 0xE0, 0xFB, 0x90, 0x9C, 0x0F, 0xE0,
++0x90, 0x9A, 0x38, 0xF0, 0xF1, 0x2C, 0xEF, 0x60,
++0x02, 0xB1, 0x01, 0x90, 0x93, 0x25, 0xE0, 0xC4,
++0x13, 0x54, 0x07, 0x30, 0xE0, 0x0F, 0x91, 0x35,
++0x90, 0x9C, 0x0A, 0xE0, 0xFB, 0x12, 0xF3, 0xC0,
++0xEF, 0x60, 0x02, 0xB1, 0x01, 0x90, 0x93, 0x24,
++0xE0, 0xC3, 0x13, 0x30, 0xE0, 0x0A, 0x91, 0x35,
++0x12, 0xA4, 0xC2, 0xEF, 0x60, 0x02, 0xB1, 0x01,
++0x12, 0x9F, 0xA4, 0x54, 0x3F, 0x30, 0xE0, 0x0A,
++0x91, 0x35, 0x12, 0xEF, 0x20, 0xEF, 0x60, 0x02,
++0xB1, 0x01, 0x90, 0x93, 0x24, 0x11, 0xAD, 0x30,
++0xE0, 0x16, 0x90, 0x9C, 0x19, 0xE0, 0x70, 0x10,
++0x91, 0x35, 0xF1, 0xDE, 0xEF, 0x60, 0x09, 0x12,
++0xA7, 0x6E, 0x90, 0x01, 0xC7, 0x74, 0x22, 0xF0,
++0x91, 0x35, 0x91, 0x60, 0xEF, 0x60, 0x03, 0x12,
++0xC9, 0x35, 0x90, 0x9C, 0x04, 0xE0, 0xFF, 0x7D,
++0x01, 0x12, 0xF4, 0x30, 0xEF, 0x60, 0x12, 0x12,
++0xA7, 0x6E, 0x90, 0x9B, 0xFD, 0x91, 0x4F, 0x7D,
++0x10, 0x12, 0x04, 0x7E, 0x90, 0x95, 0x65, 0xEF,
++0xF0, 0x90, 0x9C, 0x19, 0xE0, 0x70, 0x1E, 0x90,
++0x93, 0x26, 0xD1, 0x03, 0x30, 0xE0, 0x16, 0x90,
++0x9C, 0x03, 0xE0, 0xFF, 0x64, 0x08, 0x60, 0x04,
++0xEF, 0xB4, 0x88, 0x09, 0x12, 0xA7, 0x6E, 0x90,
++0x01, 0xC7, 0x74, 0x25, 0xF0, 0x90, 0x93, 0x31,
++0xE0, 0x30, 0xE0, 0x13, 0x90, 0x93, 0x25, 0xD1,
++0x03, 0x30, 0xE0, 0x0B, 0x91, 0x35, 0x12, 0xBC,
++0x14, 0xBF, 0x01, 0x03, 0x12, 0xC9, 0x35, 0x12,
++0xFB, 0x98, 0x90, 0x9B, 0xFD, 0x12, 0xFA, 0xD8,
++0x12, 0xFB, 0x8F, 0xD3, 0x9F, 0xEC, 0x9E, 0x40,
++0x0F, 0x12, 0xFA, 0xB8, 0xED, 0x9F, 0xFF, 0xEC,
++0x9E, 0x90, 0x9B, 0xFD, 0xF0, 0xA3, 0xEF, 0xF0,
++0x90, 0x93, 0x31, 0xE0, 0x30, 0xE0, 0x04, 0x7F,
++0x01, 0xB1, 0x64, 0x12, 0xE6, 0xE3, 0xEF, 0x64,
++0x01, 0x70, 0x31, 0x12, 0xE6, 0xCD, 0xAD, 0x07,
++0xEF, 0x64, 0x01, 0x60, 0x1F, 0x12, 0xA7, 0x6E,
++0xED, 0xB4, 0x02, 0x08, 0x90, 0x01, 0xC7, 0x74,
++0x42, 0xF0, 0x80, 0x0A, 0xED, 0xB4, 0x04, 0x06,
++0x90, 0x01, 0xC7, 0x74, 0x43, 0xF0, 0x7F, 0x01,
++0xB1, 0x64, 0x80, 0x24, 0x90, 0x9B, 0xFD, 0x12,
++0xE6, 0xBA, 0x80, 0x14, 0x90, 0x93, 0x26, 0xE0,
++0xC4, 0x13, 0x54, 0x07, 0x20, 0xE0, 0x11, 0x90,
++0x93, 0x24, 0xE0, 0x54, 0xFE, 0xF0, 0x80, 0x08,
++0x90, 0x9C, 0x05, 0xE0, 0x04, 0xF0, 0x01, 0xF0,
++0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x9C, 0x01,
++0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x90, 0x9C, 0x07,
++0xE0, 0xFD, 0x22, 0x90, 0x9C, 0x01, 0xE0, 0xFE,
++0xA3, 0xE0, 0xFF, 0x22, 0x90, 0x9A, 0x39, 0xE0,
++0xFE, 0xA3, 0xE0, 0xFF, 0x90, 0x8A, 0xE9, 0xE0,
++0xFC, 0xA3, 0xE0, 0xF5, 0x82, 0x8C, 0x83, 0x22,
++0x90, 0x9A, 0x36, 0xED, 0x12, 0xE7, 0x5F, 0xB1,
++0x12, 0xEF, 0x70, 0x02, 0x81, 0xFE, 0xF1, 0x23,
++0xF1, 0xF3, 0x70, 0x02, 0x81, 0xFE, 0x12, 0xA6,
++0x24, 0xCF, 0x24, 0x08, 0x12, 0xFB, 0x3D, 0x90,
++0x93, 0x25, 0xE0, 0xC4, 0x54, 0x0F, 0x30, 0xE0,
++0x33, 0x91, 0x4C, 0x7D, 0x09, 0x12, 0x04, 0x7E,
++0xEF, 0x64, 0x06, 0x70, 0x27, 0x91, 0x4C, 0x7D,
++0x14, 0x12, 0x04, 0x7E, 0xEF, 0x70, 0x1D, 0x91,
++0x4C, 0x7D, 0x15, 0x12, 0x04, 0x7E, 0xEF, 0x64,
++0x50, 0x70, 0x11, 0x91, 0x4C, 0x7D, 0x21, 0x12,
++0x04, 0x7E, 0xEF, 0x20, 0xE0, 0x03, 0x30, 0xE2,
++0x03, 0x7F, 0x01, 0x22, 0x90, 0x93, 0x25, 0xE0,
++0x13, 0x13, 0x54, 0x3F, 0x30, 0xE0, 0x37, 0x91,
++0x4C, 0x7D, 0x09, 0x12, 0x04, 0x7E, 0xEF, 0x64,
++0x11, 0x70, 0x2B, 0x90, 0x9A, 0x3A, 0xE0, 0x24,
++0x14, 0xFF, 0x90, 0x9A, 0x39, 0xE0, 0x34, 0x00,
++0xFE, 0x12, 0xFB, 0xCB, 0x91, 0x54, 0x7D, 0x02,
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++0x37, 0x91, 0x4F, 0x7D, 0x03, 0x12, 0x04, 0x7E,
++0xBF, 0x89, 0x03, 0x7F, 0x01, 0x22, 0x7F, 0x00,
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++0xF0, 0x90, 0x9C, 0x0D, 0xE0, 0xFE, 0xA3, 0xE0,
++0xFF, 0x22, 0x90, 0x9A, 0x3B, 0xEE, 0xF0, 0xA3,
++0xEF, 0xF0, 0xE4, 0x90, 0x9A, 0x43, 0xF0, 0x90,
++0x9A, 0x43, 0xE0, 0xFD, 0xC3, 0x94, 0x06, 0x50,
++0x1D, 0x90, 0x9A, 0x3C, 0xE0, 0x24, 0x04, 0x12,
++0xFB, 0x04, 0xF1, 0xCF, 0x90, 0x9A, 0x43, 0x12,
++0xF3, 0x6F, 0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x9A,
++0x43, 0xE0, 0x04, 0xF0, 0x80, 0xD9, 0x78, 0x32,
++0x7C, 0x93, 0x7D, 0x01, 0x7B, 0x01, 0x7A, 0x9A,
++0x79, 0x3D, 0x12, 0xE7, 0x4F, 0x7F, 0x00, 0x70,
++0x02, 0x7F, 0x01, 0x22, 0x90, 0x01, 0xC7, 0x74,
++0x10, 0xF0, 0x7F, 0x01, 0x90, 0x9C, 0xE4, 0xEF,
++0xF0, 0x90, 0x86, 0xB3, 0xE0, 0x64, 0x02, 0x70,
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++0x70, 0x7D, 0x12, 0xA7, 0x6E, 0x11, 0xAA, 0x30,
++0xE0, 0x09, 0x90, 0x01, 0x4D, 0xE0, 0x64, 0x80,
++0xF0, 0x80, 0x6C, 0xAF, 0x05, 0x12, 0xE2, 0x3D,
++0x80, 0x65, 0x90, 0x86, 0xB3, 0xE0, 0x64, 0x03,
++0x70, 0x2E, 0x90, 0x99, 0xB0, 0xE0, 0xFF, 0x30,
++0xE0, 0x26, 0x90, 0x00, 0xD4, 0xE0, 0x54, 0xEF,
++0xF0, 0x90, 0x00, 0xC6, 0xE0, 0x54, 0xFD, 0xF0,
++0x90, 0x00, 0x01, 0xE0, 0x44, 0x30, 0xF0, 0x90,
++0x00, 0x23, 0xE0, 0x44, 0x80, 0xF0, 0x12, 0xBF,
++0x91, 0xEF, 0x54, 0xFE, 0x90, 0x99, 0xB0, 0xF0,
++0x90, 0x06, 0x90, 0xE0, 0x44, 0x20, 0x12, 0xE0,
++0xAC, 0x12, 0xEE, 0xB5, 0x90, 0x06, 0x90, 0xE0,
++0x44, 0x01, 0xF0, 0x90, 0x9C, 0xE4, 0xE0, 0xFF,
++0x12, 0xE2, 0x3D, 0x12, 0xBF, 0xA0, 0xFD, 0x12,
++0xBA, 0x4D, 0x12, 0xD9, 0x6A, 0x12, 0xBF, 0x8B,
++0x90, 0x00, 0x04, 0xE0, 0x44, 0x08, 0xF0, 0x12,
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++0xC1, 0x98, 0x90, 0x88, 0x4D, 0xE0, 0x04, 0xF0,
++0x90, 0x05, 0x61, 0xF1, 0x1B, 0x78, 0x08, 0x12,
++0x03, 0xFE, 0xA8, 0x04, 0xA9, 0x05, 0xAA, 0x06,
++0xAB, 0x07, 0x90, 0x05, 0x60, 0xF1, 0x1B, 0x12,
++0x82, 0x05, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06,
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++0xD0, 0x01, 0xD0, 0x00, 0x12, 0x82, 0x05, 0xC0,
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++0xF1, 0x1B, 0x78, 0x18, 0x12, 0x03, 0xFE, 0xD0,
++0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12,
++0x82, 0x05, 0x90, 0x88, 0x81, 0x12, 0x04, 0x31,
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++0xE0, 0x30, 0xE0, 0x0C, 0x12, 0xFA, 0x60, 0x74,
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++0x12, 0xB4, 0xAB, 0x30, 0xE0, 0x0A, 0x90, 0x01,
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++0x12, 0xDC, 0x03, 0x12, 0xE6, 0x54, 0xE4, 0x90,
++0x98, 0x4F, 0xF0, 0x12, 0xF9, 0xA1, 0x90, 0x93,
++0x24, 0xD1, 0x03, 0x30, 0xE0, 0x51, 0x90, 0x95,
++0x93, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x7C, 0x00,
++0x7D, 0x64, 0x12, 0x02, 0x92, 0x90, 0x95, 0xE7,
++0xE0, 0x6E, 0x70, 0x03, 0xA3, 0xE0, 0x6F, 0x60,
++0x0A, 0x90, 0x95, 0xE7, 0xE4, 0x75, 0xF0, 0x01,
++0x02, 0x02, 0xE7, 0x90, 0x95, 0x97, 0xE0, 0xFE,
++0xA3, 0xE0, 0xFF, 0x90, 0x95, 0xA5, 0xE0, 0xB5,
++0x06, 0x13, 0xA3, 0xE0, 0xB5, 0x07, 0x0E, 0xEF,
++0x4E, 0x60, 0x0A, 0x90, 0x01, 0xC7, 0x74, 0x31,
++0xF0, 0x7F, 0x01, 0xA1, 0x64, 0x12, 0xC6, 0x0C,
++0xE4, 0x90, 0x95, 0xE7, 0xF0, 0xA3, 0xF0, 0x22,
++0x12, 0x04, 0x31, 0x90, 0x99, 0xB1, 0xE4, 0x75,
++0xF0, 0x04, 0x12, 0x02, 0xE7, 0x90, 0x99, 0xB1,
++0xA3, 0xE0, 0x24, 0x02, 0xF5, 0x82, 0xE4, 0x34,
++0xFC, 0xF5, 0x83, 0xE0, 0xFF, 0xE4, 0xFC, 0xFD,
++0xFE, 0x22, 0xF0, 0x90, 0x9A, 0x34, 0xE0, 0xFE,
++0xA3, 0xE0, 0xFF, 0x22, 0x12, 0xE7, 0x58, 0xE4,
++0x90, 0x9A, 0x39, 0xF0, 0x12, 0xA2, 0x3A, 0xEF,
++0x54, 0x0C, 0x64, 0x08, 0x70, 0x75, 0xF1, 0x23,
++0xA3, 0xE0, 0x24, 0x06, 0xF1, 0xCE, 0xEF, 0x64,
++0x88, 0x70, 0x68, 0xF1, 0x23, 0xA3, 0xE0, 0x24,
++0x07, 0xF1, 0xCE, 0xEF, 0x64, 0x8E, 0x70, 0x5B,
++0x90, 0x9A, 0x39, 0xF1, 0xB9, 0xEF, 0x64, 0x03,
++0x70, 0x51, 0xF1, 0x23, 0x12, 0xF4, 0x25, 0x24,
++0x06, 0xF1, 0xCE, 0xEF, 0x30, 0xE3, 0x07, 0x90,
++0x01, 0xC7, 0x74, 0x01, 0x80, 0x3A, 0x90, 0x93,
++0x24, 0x12, 0x97, 0xD9, 0x30, 0xE0, 0x24, 0x90,
++0x98, 0x35, 0xE0, 0x64, 0x02, 0x70, 0x12, 0x90,
++0x93, 0x25, 0x12, 0x97, 0xD9, 0x30, 0xE0, 0x02,
++0x80, 0x07, 0x90, 0x01, 0xC7, 0x74, 0x02, 0x80,
++0x17, 0xF1, 0x23, 0xA3, 0xE0, 0xFD, 0x12, 0xA2,
++0x4A, 0x80, 0x10, 0x90, 0x93, 0x29, 0xD1, 0x03,
++0x30, 0xE0, 0x08, 0x90, 0x01, 0xC7, 0x74, 0x02,
++0x12, 0xA7, 0x6D, 0x90, 0x9A, 0x39, 0xE0, 0xFF,
++0x22, 0x04, 0xF0, 0x90, 0x9A, 0x34, 0xE0, 0xFE,
++0xA3, 0xE0, 0xFF, 0x90, 0x9A, 0x37, 0xE0, 0xFD,
++0x90, 0x9A, 0x36, 0xE0, 0x2D, 0x04, 0xFD, 0x90,
++0x8A, 0xE9, 0xE0, 0xFA, 0xA3, 0xE0, 0xFB, 0xF5,
++0x82, 0x8A, 0x83, 0x02, 0x04, 0x7E, 0x90, 0x9A,
++0x36, 0xED, 0x12, 0xE7, 0x5F, 0xB1, 0x12, 0xEF,
++0x60, 0x08, 0xF1, 0x23, 0xF1, 0xF3, 0x60, 0x02,
++0x7F, 0x01, 0x22, 0xA3, 0xE0, 0xFD, 0x12, 0xA6,
++0x3D, 0xEF, 0x22, 0x12, 0x02, 0x06, 0x90, 0x88,
++0x9C, 0xF0, 0x22, 0x12, 0x02, 0x06, 0xFF, 0x54,
++0x01, 0xFE, 0x90, 0x93, 0x08, 0xE0, 0x54, 0xFE,
++0x4E, 0xFE, 0xF0, 0xEF, 0x54, 0x02, 0xFF, 0xEE,
++0x54, 0xFD, 0x4F, 0xF0, 0x12, 0x9C, 0x58, 0x90,
++0x93, 0x09, 0x12, 0x87, 0xE6, 0x90, 0x93, 0x0A,
++0xF0, 0x11, 0x35, 0x90, 0x93, 0x08, 0xE0, 0x54,
++0x01, 0xFF, 0x02, 0xA6, 0xC7, 0x90, 0x93, 0x09,
++0xE0, 0x14, 0x90, 0x93, 0x0B, 0xF0, 0x22, 0x90,
++0x93, 0x08, 0xE0, 0x30, 0xE0, 0x37, 0xF1, 0xB9,
++0x90, 0x93, 0x0B, 0xE0, 0x60, 0x0B, 0x14, 0xF0,
++0x90, 0x9B, 0x89, 0xE0, 0x70, 0x27, 0x02, 0x79,
++0xD4, 0x11, 0x35, 0xE4, 0xFF, 0x12, 0xA6, 0xC7,
++0x90, 0x93, 0x04, 0xE0, 0xFF, 0x20, 0xE0, 0x08,
++0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0, 0x0D,
++0x90, 0x9C, 0x9B, 0x12, 0x04, 0x3D, 0x00, 0x00,
++0x00, 0x01, 0x12, 0x95, 0x36, 0x22, 0x11, 0xC7,
++0x7D, 0x02, 0x7F, 0x02, 0x12, 0x7C, 0x74, 0x7F,
++0x01, 0x11, 0x8D, 0x80, 0xB2, 0xD3, 0x10, 0xAF,
++0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x88, 0x33, 0xE0,
++0xC3, 0x13, 0x30, 0xE0, 0x25, 0x90, 0x9B, 0xDA,
++0x74, 0x1E, 0xF0, 0x90, 0x9B, 0xFC, 0x74, 0x01,
++0xF0, 0x90, 0x9B, 0xDC, 0xEF, 0xF0, 0x7B, 0x01,
++0x7A, 0x9B, 0x79, 0xDA, 0x12, 0xFA, 0x71, 0x90,
++0x8A, 0xE5, 0x12, 0x90, 0x47, 0x7F, 0x04, 0x12,
++0x04, 0x7E, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xE4,
++0x90, 0x9B, 0x04, 0xF0, 0x90, 0x88, 0x36, 0xE0,
++0x60, 0x39, 0x12, 0x97, 0xE8, 0x70, 0x34, 0x31,
++0x13, 0xF0, 0x12, 0xF9, 0xC0, 0x90, 0x9B, 0x04,
++0x74, 0x01, 0xF0, 0xE4, 0x90, 0x88, 0x3D, 0xF0,
++0x04, 0x60, 0x20, 0x90, 0x88, 0x39, 0xE0, 0x20,
++0xE2, 0x0D, 0x90, 0x8A, 0xB9, 0x12, 0x90, 0x47,
++0x7D, 0x01, 0x7F, 0x04, 0x12, 0x04, 0x7E, 0xF1,
++0xB1, 0xE4, 0x90, 0x92, 0x20, 0xF0, 0x12, 0x97,
++0xD6, 0xD1, 0x56, 0x22, 0x12, 0x97, 0x65, 0xE4,
++0xFF, 0x01, 0x8D, 0x90, 0x88, 0x3C, 0xE0, 0x90,
++0x05, 0x73, 0x22, 0xE4, 0x90, 0x9A, 0xFB, 0xF0,
++0x12, 0x97, 0xE9, 0x60, 0x02, 0x41, 0x54, 0x90,
++0x88, 0x36, 0xE0, 0x70, 0x02, 0x41, 0x54, 0x90,
++0x06, 0xA9, 0xE0, 0x54, 0xC0, 0x70, 0x26, 0x90,
++0x88, 0x9C, 0xE0, 0x70, 0x20, 0x90, 0x04, 0x1A,
++0xE0, 0xF4, 0x70, 0x19, 0xA3, 0xE0, 0x54, 0x07,
++0xFF, 0xBF, 0x07, 0x11, 0x90, 0x06, 0x62, 0xE0,
++0x54, 0x03, 0x70, 0x09, 0x90, 0x88, 0x39, 0xE0,
++0xB4, 0x04, 0x02, 0xF1, 0xA9, 0x90, 0x05, 0x63,
++0xE0, 0x90, 0x88, 0x85, 0xF0, 0x90, 0x05, 0x62,
++0xE0, 0x90, 0x88, 0x86, 0xF0, 0x90, 0x05, 0x61,
++0xE0, 0x90, 0x88, 0x87, 0xF0, 0x90, 0x05, 0x60,
++0xE0, 0x90, 0x88, 0x88, 0xF0, 0x90, 0x07, 0xF1,
++0xE0, 0x90, 0x99, 0xAD, 0xF0, 0x90, 0x07, 0xF0,
++0xE0, 0x90, 0x99, 0xAE, 0xF0, 0xD1, 0x7B, 0xF0,
++0x90, 0x88, 0x3A, 0xE0, 0x54, 0xEC, 0xF0, 0x51,
++0x5D, 0x24, 0xFD, 0x50, 0x02, 0x80, 0x02, 0xB1,
++0xCA, 0x51, 0x5D, 0x64, 0x01, 0x70, 0x3A, 0x90,
++0x06, 0xAB, 0xE0, 0x90, 0x88, 0x3D, 0xF0, 0x90,
++0x06, 0xA9, 0xE0, 0x30, 0xE5, 0x06, 0xA3, 0xE0,
++0x90, 0x9A, 0xFB, 0xF0, 0x90, 0x9A, 0xFB, 0xE0,
++0xFF, 0x60, 0x02, 0x80, 0x05, 0x90, 0x88, 0x3C,
++0xE0, 0xFF, 0x90, 0x88, 0x3C, 0xEF, 0xF0, 0xA3,
++0xE0, 0xFF, 0x70, 0x08, 0x90, 0x88, 0x3C, 0xE0,
++0xFE, 0xFF, 0x80, 0x00, 0x90, 0x88, 0x3D, 0xEF,
++0xF0, 0x51, 0x66, 0xE4, 0x90, 0x88, 0x3F, 0xF0,
++0xA3, 0xF0, 0x91, 0xAB, 0x30, 0xE0, 0x5E, 0xEF,
++0xC4, 0x13, 0x13, 0x54, 0x03, 0x20, 0xE0, 0x24,
++0x51, 0x55, 0x6F, 0x70, 0x50, 0xEF, 0x60, 0x4D,
++0x90, 0x88, 0x32, 0xE0, 0x44, 0x40, 0xF0, 0x31,
++0x13, 0x12, 0xA7, 0x5A, 0x12, 0x7C, 0x05, 0x12,
++0xF9, 0xB9, 0xB1, 0x28, 0x90, 0x88, 0x3D, 0xE0,
++0x14, 0xF0, 0x80, 0x31, 0x90, 0x88, 0x34, 0xE0,
++0xC4, 0x54, 0x0F, 0x64, 0x01, 0x70, 0x26, 0x51,
++0x55, 0xFE, 0x6F, 0x60, 0x20, 0x90, 0x05, 0x73,
++0xE0, 0xFF, 0xEE, 0x6F, 0x60, 0x17, 0x91, 0xA1,
++0x30, 0xE0, 0x12, 0xEF, 0x54, 0xBF, 0x12, 0xA7,
++0x5A, 0x12, 0x7C, 0x3B, 0xF1, 0xA2, 0x7D, 0x02,
++0x7F, 0x02, 0x12, 0x7C, 0x74, 0x90, 0x88, 0x32,
++0xE0, 0x44, 0x04, 0xF0, 0x22, 0x90, 0x88, 0x3C,
++0xE0, 0xFF, 0xA3, 0xE0, 0x22, 0x90, 0x88, 0x34,
++0xE0, 0xFF, 0xC4, 0x54, 0x0F, 0x22, 0x90, 0x88,
++0x85, 0x12, 0x04, 0xB8, 0xC0, 0x06, 0xC0, 0x07,
++0x90, 0x99, 0xAE, 0xE0, 0x24, 0x46, 0xFF, 0x90,
++0x99, 0xAD, 0xE0, 0x34, 0x00, 0xAB, 0x07, 0xFA,
++0xE4, 0xF9, 0xF8, 0xD0, 0x07, 0xD0, 0x06, 0x12,
++0x80, 0xCD, 0x90, 0x88, 0x85, 0x91, 0x7F, 0xEF,
++0x24, 0x46, 0xF1, 0xEB, 0x90, 0x88, 0x89, 0x91,
++0x7F, 0x90, 0x88, 0x85, 0x12, 0x82, 0x12, 0xC3,
++0x12, 0x03, 0xDA, 0x50, 0x02, 0x61, 0x60, 0x90,
++0x88, 0x89, 0x12, 0x82, 0x12, 0x90, 0x88, 0x85,
++0x12, 0x04, 0xB8, 0x12, 0x80, 0xCD, 0x90, 0x9B,
++0x00, 0x12, 0x04, 0x31, 0x90, 0x88, 0x31, 0xE0,
++0x30, 0xE0, 0x34, 0x90, 0x88, 0x53, 0xE0, 0x24,
++0x04, 0xFF, 0xE4, 0x33, 0xFE, 0xEF, 0x78, 0x03,
++0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, 0x24,
++0x50, 0xFF, 0xE4, 0x3E, 0xFE, 0x90, 0x88, 0x4E,
++0xE0, 0xFD, 0xC3, 0xEF, 0x9D, 0xFB, 0xEE, 0x94,
++0x00, 0xFA, 0x91, 0x6E, 0x78, 0x07, 0x12, 0x03,
++0xEB, 0xEB, 0x2F, 0xFF, 0xEA, 0x80, 0x22, 0x90,
++0x88, 0x33, 0x91, 0xA4, 0x30, 0xE0, 0x02, 0x81,
++0x5E, 0x91, 0x6E, 0x78, 0x07, 0x12, 0x03, 0xEB,
++0x90, 0x88, 0x4E, 0xE0, 0xFD, 0xC3, 0x74, 0x60,
++0x9D, 0xCD, 0xE4, 0x94, 0x00, 0xCD, 0x2F, 0xFF,
++0xED, 0x3E, 0x90, 0x9A, 0xFC, 0xF0, 0xA3, 0xEF,
++0xF0, 0xC3, 0x90, 0x9A, 0xFD, 0xE0, 0x94, 0xA0,
++0x90, 0x9A, 0xFC, 0xE0, 0x94, 0x00, 0x50, 0x30,
++0xA3, 0xE0, 0xFB, 0x24, 0x6D, 0x91, 0x77, 0xE0,
++0x04, 0xF0, 0x91, 0x6E, 0xEF, 0x54, 0x7F, 0xFF,
++0x74, 0x0D, 0x2B, 0x91, 0x66, 0xE0, 0xFE, 0xEF,
++0xC3, 0x9E, 0x50, 0x09, 0x90, 0x9A, 0xFC, 0xA3,
++0xE0, 0x91, 0x64, 0xEF, 0xF0, 0x90, 0x88, 0x4C,
++0xE0, 0x04, 0xF0, 0xE0, 0x90, 0x00, 0xFE, 0xF0,
++0x90, 0x88, 0x4C, 0xE0, 0xFF, 0xD3, 0x90, 0x88,
++0x90, 0xE0, 0x9F, 0x90, 0x88, 0x8F, 0xE0, 0x94,
++0x00, 0x40, 0x02, 0x81, 0x5E, 0xE4, 0xFF, 0xFE,
++0x91, 0x74, 0xE0, 0x2F, 0xFF, 0x90, 0x88, 0x91,
++0xE0, 0xFD, 0xEF, 0xD3, 0x9D, 0x40, 0x07, 0x90,
++0x9A, 0xFE, 0xEE, 0xF0, 0x80, 0x05, 0x0E, 0xEE,
++0xB4, 0xA0, 0xE5, 0x91, 0x88, 0x40, 0x02, 0x80,
++0x15, 0x90, 0x9A, 0xFE, 0xE0, 0x04, 0xFE, 0xEE,
++0xC3, 0x94, 0xA0, 0x50, 0x13, 0x91, 0x74, 0xE0,
++0x2F, 0xFF, 0x91, 0x88, 0x40, 0x07, 0x90, 0x9A,
++0xFF, 0xEE, 0xF0, 0x80, 0x03, 0x0E, 0x80, 0xE7,
++0x90, 0x05, 0x5E, 0xE0, 0xFF, 0x91, 0x5F, 0xE0,
++0xFD, 0xEF, 0xC3, 0x9D, 0x40, 0x11, 0xEF, 0x9D,
++0x90, 0x05, 0x5E, 0xF0, 0x90, 0x88, 0x51, 0xEE,
++0xF0, 0x90, 0x9A, 0xFF, 0xE0, 0x80, 0x18, 0x91,
++0x5F, 0xE0, 0xFD, 0xC3, 0x74, 0x80, 0x9D, 0x2F,
++0x90, 0x05, 0x5E, 0xF0, 0xEE, 0x04, 0x90, 0x88,
++0x51, 0xF0, 0x90, 0x9A, 0xFF, 0xE0, 0x04, 0x90,
++0x88, 0x52, 0xF0, 0x90, 0x88, 0x51, 0xE0, 0xFF,
++0xC3, 0x94, 0x50, 0x40, 0x0A, 0xEF, 0x24, 0xB0,
++0x90, 0x88, 0x49, 0xF0, 0xE4, 0x80, 0x0E, 0xE4,
++0x90, 0x88, 0x49, 0xF0, 0x90, 0x88, 0x51, 0xE0,
++0xFF, 0xC3, 0x74, 0x50, 0x9F, 0x90, 0x88, 0x48,
++0xF0, 0x90, 0x88, 0x51, 0xE0, 0xFF, 0xA3, 0xE0,
++0xC3, 0x9F, 0x90, 0x88, 0x4F, 0xF0, 0x90, 0x88,
++0x31, 0xE0, 0x90, 0x88, 0x8E, 0xE0, 0x24, 0x08,
++0xFF, 0x90, 0x88, 0x4F, 0xE0, 0x2F, 0xF0, 0x90,
++0x88, 0x4F, 0xE0, 0xC3, 0x94, 0x50, 0x50, 0x03,
++0x74, 0x50, 0xF0, 0x90, 0x88, 0x4F, 0xE0, 0x24,
++0x10, 0xF0, 0x12, 0xFA, 0x60, 0x74, 0x03, 0xF0,
++0x12, 0x6E, 0x2F, 0x90, 0x8A, 0xA3, 0x12, 0x90,
++0x47, 0xE4, 0xFF, 0x12, 0x04, 0x7E, 0x22, 0x90,
++0x9A, 0xFE, 0xE0, 0xFE, 0x24, 0x0D, 0xF5, 0x82,
++0xE4, 0x34, 0x99, 0xF5, 0x83, 0x22, 0x90, 0x9B,
++0x00, 0x02, 0x04, 0xB8, 0x74, 0x6D, 0x2E, 0xF5,
++0x82, 0xE4, 0x34, 0x98, 0xF5, 0x83, 0x22, 0x12,
++0x04, 0x31, 0x90, 0x88, 0x89, 0x02, 0x04, 0xB8,
++0x90, 0x88, 0x91, 0xE0, 0xFD, 0xC3, 0x90, 0x88,
++0x90, 0xE0, 0x9D, 0xFD, 0x90, 0x88, 0x8F, 0xE0,
++0x94, 0x00, 0xFC, 0xEF, 0xD3, 0x9D, 0xE4, 0x9C,
++0x22, 0x90, 0x88, 0x32, 0xE0, 0xFF, 0x13, 0x13,
++0x54, 0x3F, 0x22, 0x90, 0x88, 0x32, 0xE0, 0xFF,
++0x13, 0x13, 0x13, 0x54, 0x1F, 0x22, 0x91, 0xAB,
++0x30, 0xE0, 0x0B, 0xEF, 0xC4, 0x13, 0x13, 0x54,
++0x03, 0x30, 0xE0, 0x02, 0xB1, 0x28, 0x90, 0x88,
++0x31, 0x91, 0xA4, 0x30, 0xE0, 0x07, 0xEF, 0xF1,
++0x69, 0x70, 0x4C, 0x80, 0x48, 0x90, 0x88, 0x3F,
++0xE0, 0x04, 0xF0, 0x90, 0x88, 0x3A, 0xE0, 0x54,
++0xEF, 0xF0, 0xF1, 0xE0, 0x9F, 0x40, 0x36, 0x12,
++0x97, 0xE8, 0x70, 0x33, 0x12, 0x97, 0xF1, 0x70,
++0x08, 0x90, 0x8A, 0xF5, 0x12, 0x88, 0xC8, 0x80,
++0x27, 0x90, 0x8A, 0xF5, 0x12, 0x88, 0xC8, 0x90,
++0x88, 0x40, 0xE0, 0x04, 0xF0, 0xE0, 0xD3, 0x94,
++0x02, 0x40, 0x09, 0xB1, 0x20, 0xE4, 0x90, 0x88,
++0x40, 0xF0, 0x80, 0x03, 0x12, 0x93, 0xD6, 0xE4,
++0x90, 0x88, 0x3F, 0xF0, 0x22, 0xD1, 0x3C, 0x22,
++0x90, 0x88, 0x32, 0xE0, 0x54, 0xFB, 0xF0, 0x22,
++0x7D, 0x02, 0x7F, 0x02, 0x02, 0x7C, 0x7E, 0x90,
++0x98, 0x4C, 0x91, 0xA4, 0x30, 0xE0, 0x0A, 0xF1,
++0x9B, 0x12, 0xFB, 0x1A, 0x04, 0xF0, 0x02, 0x8B,
++0xEA, 0x90, 0x8A, 0xAF, 0x12, 0x90, 0x47, 0x7D,
++0x08, 0xE4, 0xFF, 0x02, 0x04, 0x7E, 0xE4, 0xFE,
++0x91, 0x74, 0xE4, 0xF0, 0x74, 0x0D, 0x2E, 0x91,
++0x66, 0x74, 0xFF, 0xF0, 0x0E, 0xEE, 0xB4, 0xA0,
++0xEF, 0xE4, 0x90, 0x88, 0x4D, 0xF0, 0x90, 0x88,
++0x4C, 0xF0, 0x90, 0x88, 0x50, 0xF0, 0xEF, 0xB4,
++0x01, 0x07, 0xA3, 0x74, 0xA0, 0xF0, 0xE4, 0xA3,
++0xF0, 0x22, 0x90, 0x93, 0x04, 0x91, 0xAE, 0x30,
++0xE0, 0x31, 0xEF, 0xC4, 0x54, 0x0F, 0x20, 0xE0,
++0x25, 0xF1, 0xD5, 0x60, 0x0B, 0xF1, 0xCB, 0x40,
++0x07, 0xB1, 0xC2, 0x90, 0x95, 0xF5, 0x80, 0x05,
++0xB1, 0xC2, 0x90, 0x95, 0xED, 0x12, 0x82, 0x12,
++0x12, 0x80, 0xDB, 0x90, 0x9C, 0x9B, 0x12, 0x04,
++0x31, 0x12, 0x95, 0x36, 0x80, 0x05, 0x7F, 0x01,
++0x12, 0xA6, 0xC7, 0x90, 0x93, 0x04, 0xE0, 0xC3,
++0x13, 0x30, 0xE0, 0x05, 0x7F, 0x01, 0x12, 0xA6,
++0xC7, 0x22, 0xE4, 0x7F, 0xE8, 0x7E, 0x03, 0xFD,
++0xFC, 0x22, 0xE4, 0xF5, 0x0F, 0x90, 0x06, 0xA9,
++0xE0, 0xF5, 0x0F, 0x54, 0xC0, 0x70, 0x12, 0xD1,
++0x35, 0xF0, 0x54, 0xFD, 0xF0, 0xD1, 0x3C, 0x90,
++0x88, 0x39, 0xE0, 0x60, 0x4F, 0xF1, 0x83, 0xF0,
++0x22, 0xE5, 0x0F, 0x30, 0xE6, 0x2A, 0x90, 0x88,
++0x36, 0xE0, 0x64, 0x01, 0x70, 0x25, 0x90, 0x88,
++0x3A, 0xE0, 0x44, 0x01, 0xF0, 0x12, 0x97, 0xF1,
++0x64, 0x02, 0x60, 0x0F, 0x90, 0x88, 0x9D, 0xE0,
++0x20, 0xE0, 0x10, 0x90, 0x8A, 0xE1, 0x12, 0x88,
++0xC8, 0x80, 0x08, 0x12, 0x93, 0xD6, 0x80, 0x03,
++0xD1, 0x35, 0xF0, 0xE5, 0x0F, 0x90, 0x88, 0x3A,
++0x30, 0xE7, 0x0D, 0xE0, 0x44, 0x02, 0xD1, 0x4C,
++0x90, 0x88, 0x31, 0xE0, 0x44, 0x04, 0xF0, 0x22,
++0xE0, 0x54, 0xFD, 0xF0, 0x22, 0x90, 0x88, 0x3A,
++0xE0, 0x54, 0xFE, 0x22, 0x90, 0x88, 0x38, 0xE0,
++0xFF, 0x90, 0x8A, 0xB9, 0x12, 0xAC, 0x57, 0x7D,
++0x01, 0x02, 0x04, 0x7E, 0xF0, 0xE4, 0x90, 0x92,
++0x20, 0xF0, 0x90, 0x88, 0x94, 0xE0, 0x90, 0x92,
++0x21, 0xF0, 0xE4, 0xFB, 0xFD, 0x7F, 0x54, 0x7E,
++0x01, 0x02, 0x66, 0x33, 0x12, 0x97, 0xE8, 0x70,
++0x11, 0x90, 0x88, 0x36, 0xE0, 0x60, 0x0B, 0x90,
++0x88, 0x3A, 0xE0, 0x20, 0xE4, 0x04, 0xD1, 0x7B,
++0xD1, 0x4C, 0x22, 0x90, 0x01, 0x57, 0xE4, 0xF0,
++0x90, 0x01, 0x3C, 0x74, 0x02, 0x22, 0x12, 0x97,
++0xE8, 0x70, 0x1A, 0x90, 0x88, 0x36, 0xE0, 0x60,
++0x14, 0x90, 0x88, 0x3A, 0xE0, 0x20, 0xE4, 0x0D,
++0xD1, 0x7B, 0xF0, 0x90, 0x88, 0x31, 0xE0, 0xF1,
++0x69, 0x70, 0x02, 0xD1, 0x3C, 0x22, 0xC0, 0xE0,
++0xC0, 0xF0, 0xC0, 0x83, 0xC0, 0x82, 0xC0, 0xD0,
++0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0, 0x01, 0xC0,
++0x02, 0xC0, 0x03, 0xC0, 0x04, 0xC0, 0x05, 0xC0,
++0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4, 0x74, 0xA6,
++0xF0, 0x74, 0xB6, 0xA3, 0xF0, 0x12, 0x64, 0x7F,
++0xE5, 0x30, 0x30, 0xE1, 0x02, 0xF1, 0x60, 0xE5,
++0x2D, 0x30, 0xE3, 0x03, 0x12, 0xE2, 0xB8, 0xE5,
++0x2D, 0x30, 0xE4, 0x03, 0x12, 0xE2, 0xCB, 0xE5,
++0x2D, 0x30, 0xE5, 0x03, 0x12, 0xE2, 0xDC, 0xE5,
++0x2F, 0x30, 0xE0, 0x02, 0x31, 0x0C, 0xE5, 0x2F,
++0x30, 0xE1, 0x03, 0x12, 0xAE, 0x0A, 0xE5, 0x2F,
++0x30, 0xE2, 0x02, 0xF1, 0x8A, 0xE5, 0x2F, 0x30,
++0xE3, 0x02, 0xD1, 0x64, 0xE5, 0x2F, 0x30, 0xE4,
++0x02, 0xD1, 0x86, 0xE5, 0x2F, 0x30, 0xE5, 0x03,
++0x12, 0xDE, 0xE0, 0xE5, 0x2F, 0x30, 0xE6, 0x02,
++0xF1, 0x48, 0x74, 0xA6, 0x04, 0x90, 0x01, 0xC4,
++0xF0, 0x74, 0xB6, 0xA3, 0xF0, 0xD0, 0x07, 0xD0,
++0x06, 0xD0, 0x05, 0xD0, 0x04, 0xD0, 0x03, 0xD0,
++0x02, 0xD0, 0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0,
++0x82, 0xD0, 0x83, 0xD0, 0xF0, 0xD0, 0xE0, 0x32,
++0xE4, 0xFF, 0x12, 0x78, 0x4A, 0xBF, 0x01, 0x0F,
++0x90, 0x88, 0x36, 0xE0, 0x60, 0x09, 0xD1, 0x35,
++0xF0, 0x54, 0x07, 0x70, 0x02, 0xD1, 0x3C, 0x22,
++0x90, 0x88, 0x36, 0xE0, 0x60, 0x02, 0xF1, 0x76,
++0x22, 0x54, 0xFB, 0xF0, 0x90, 0x88, 0x3A, 0xE0,
++0x54, 0xFD, 0xF0, 0x54, 0x07, 0x22, 0x90, 0x88,
++0x39, 0xE0, 0xB4, 0x04, 0x03, 0xF1, 0x83, 0xF0,
++0x02, 0x95, 0x05, 0x90, 0x00, 0x02, 0xE0, 0x44,
++0x01, 0x22, 0x90, 0x98, 0x56, 0xE0, 0x04, 0xF0,
++0x90, 0x88, 0x39, 0xE0, 0x64, 0x02, 0x60, 0x02,
++0x31, 0x1B, 0x22, 0x7B, 0x00, 0x7A, 0x00, 0x79,
++0x00, 0x22, 0x7D, 0x01, 0x7F, 0x02, 0x02, 0x7C,
++0x74, 0x90, 0x00, 0x02, 0xE0, 0x54, 0xFE, 0xF0,
++0x22, 0x90, 0x88, 0x3A, 0xE0, 0x44, 0x10, 0xF0,
++0x22, 0x90, 0x93, 0x0A, 0xE0, 0x90, 0x05, 0x73,
++0xF0, 0x22, 0x90, 0x88, 0x36, 0xE0, 0x60, 0x02,
++0x91, 0xB6, 0x22, 0x90, 0x98, 0x31, 0x12, 0x82,
++0x12, 0xD3, 0x02, 0x03, 0xDA, 0x90, 0x95, 0xF1,
++0x12, 0x04, 0xB8, 0xEC, 0x4D, 0x4E, 0x4F, 0x22,
++0x90, 0x88, 0x93, 0xE0, 0xFF, 0x90, 0x88, 0x3F,
++0xE0, 0xD3, 0x22, 0xFF, 0xE4, 0x3E, 0xFE, 0xE4,
++0x3D, 0xFD, 0xE4, 0x3C, 0xFC, 0x22, 0x90, 0x93,
++0x0C, 0xE0, 0x20, 0xE0, 0x03, 0x02, 0xB8, 0xC3,
++0xE4, 0x90, 0x99, 0xB1, 0xF0, 0x90, 0x99, 0xB1,
++0xE0, 0xFF, 0xC3, 0x94, 0x05, 0x40, 0x02, 0x01,
++0xC3, 0x91, 0x0C, 0x80, 0x05, 0xC3, 0x33, 0xCE,
++0x33, 0xCE, 0xD8, 0xF9, 0xFF, 0x90, 0x93, 0x0D,
++0xE0, 0xFD, 0xEF, 0x5D, 0x60, 0x02, 0x01, 0xBB,
++0x12, 0x02, 0x06, 0xFF, 0x30, 0xE0, 0x1A, 0x90,
++0x93, 0x0E, 0xE0, 0xFE, 0x90, 0x99, 0xB1, 0xE0,
++0xFD, 0x74, 0x01, 0xA8, 0x05, 0x08, 0x80, 0x02,
++0xC3, 0x33, 0xD8, 0xFC, 0x4E, 0x90, 0x93, 0x0E,
++0xF0, 0xEF, 0xC3, 0x13, 0x30, 0xE0, 0x15, 0x90,
++0x93, 0x0F, 0xE0, 0xFF, 0x90, 0x99, 0xB1, 0x11,
++0xCA, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0x4F,
++0x90, 0x93, 0x0F, 0xF0, 0x12, 0x9C, 0x58, 0xFF,
++0x90, 0x99, 0xB1, 0xE0, 0xFE, 0x24, 0x10, 0xF5,
++0x82, 0xE4, 0x34, 0x93, 0xF5, 0x83, 0xEF, 0x12,
++0x87, 0xE6, 0xFF, 0x74, 0x15, 0x2E, 0xF5, 0x82,
++0xE4, 0x34, 0x93, 0xF5, 0x83, 0xEF, 0x12, 0x87,
++0xA3, 0xFF, 0x74, 0x1A, 0x2E, 0xF5, 0x82, 0xE4,
++0x34, 0x93, 0xF5, 0x83, 0xEF, 0x12, 0x87, 0xD1,
++0xFF, 0x74, 0x1F, 0x2E, 0xF5, 0x82, 0xE4, 0x34,
++0x93, 0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x93, 0x0D,
++0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x06, 0x08, 0x80,
++0x02, 0xC3, 0x33, 0xD8, 0xFC, 0x4F, 0x90, 0x93,
++0x0D, 0xF0, 0x22, 0x90, 0x99, 0xB1, 0xE0, 0x04,
++0xF0, 0x01, 0x05, 0x22, 0x12, 0x7B, 0x41, 0x90,
++0x9C, 0xD7, 0xE0, 0xFE, 0x74, 0x01, 0xA8, 0x06,
++0x08, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0,
++0xD0, 0x90, 0x9C, 0xD8, 0xED, 0xF0, 0x90, 0x9C,
++0xD7, 0xEF, 0xF0, 0xD3, 0x94, 0x07, 0x50, 0x42,
++0x7F, 0x47, 0x11, 0xC4, 0x80, 0x02, 0xC3, 0x33,
++0xD8, 0xFC, 0xF4, 0x5F, 0xFD, 0x7F, 0x47, 0x12,
++0x7B, 0x2E, 0x7F, 0x46, 0x11, 0xC4, 0x80, 0x02,
++0xC3, 0x33, 0xD8, 0xFC, 0x4F, 0xFD, 0x7F, 0x46,
++0x51, 0xF7, 0x60, 0x0D, 0x7F, 0x45, 0x11, 0xC4,
++0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0x4F, 0x80,
++0x0C, 0x7F, 0x45, 0x11, 0xC4, 0x80, 0x02, 0xC3,
++0x33, 0xD8, 0xFC, 0xF4, 0x5F, 0xFD, 0x7F, 0x45,
++0x80, 0x4A, 0x90, 0x9C, 0xD7, 0xE0, 0x24, 0xF8,
++0xF0, 0x7F, 0x63, 0x11, 0xC4, 0x80, 0x02, 0xC3,
++0x33, 0xD8, 0xFC, 0xF4, 0x5F, 0xFD, 0x7F, 0x63,
++0x12, 0x7B, 0x2E, 0x7F, 0x62, 0x11, 0xC4, 0x80,
++0x02, 0xC3, 0x33, 0xD8, 0xFC, 0x4F, 0xFD, 0x7F,
++0x62, 0x51, 0xF7, 0x60, 0x10, 0x7F, 0x61, 0x11,
++0xC4, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0x4F,
++0xFD, 0x7F, 0x61, 0x80, 0x0F, 0x7F, 0x61, 0x11,
++0xC4, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4,
++0x5F, 0xFD, 0x7F, 0x61, 0x12, 0x7B, 0x2E, 0xD0,
++0xD0, 0x92, 0xAF, 0x22, 0x90, 0x9C, 0x94, 0xEE,
++0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x9C, 0x97, 0xEB,
++0xF0, 0x90, 0x9C, 0x96, 0xED, 0xF0, 0x60, 0x13,
++0x51, 0xEF, 0x78, 0x03, 0xC3, 0x33, 0xCE, 0x33,
++0xCE, 0xD8, 0xF9, 0xF0, 0xEE, 0x90, 0x9C, 0x94,
++0xF0, 0x80, 0x19, 0x51, 0xEF, 0x78, 0x06, 0xC3,
++0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, 0xF0, 0xEE,
++0x90, 0x9C, 0x94, 0xF0, 0x74, 0xFF, 0x75, 0xF0,
++0xD0, 0x12, 0x02, 0xE7, 0x51, 0x1F, 0x54, 0x07,
++0x7D, 0x00, 0x20, 0xE0, 0x02, 0x7D, 0x01, 0x11,
++0xD2, 0x51, 0x1F, 0x54, 0x01, 0xFD, 0x11, 0xD2,
++0x90, 0x9C, 0x98, 0xE0, 0x60, 0x3B, 0x51, 0x12,
++0x54, 0x07, 0x7D, 0x00, 0x20, 0xE0, 0x02, 0x7D,
++0x01, 0x11, 0xD2, 0xE4, 0x90, 0x9C, 0x99, 0xF0,
++0x90, 0x9C, 0x97, 0xE0, 0xFF, 0x90, 0x9C, 0x99,
++0xE0, 0xC3, 0x9F, 0x50, 0x1C, 0x51, 0x12, 0x54,
++0x01, 0xFD, 0x11, 0xD2, 0x51, 0x12, 0x54, 0x07,
++0x7D, 0x00, 0x20, 0xE0, 0x02, 0x7D, 0x01, 0x11,
++0xD2, 0x90, 0x9C, 0x99, 0xE0, 0x04, 0xF0, 0x80,
++0xD7, 0x22, 0x90, 0x9C, 0x94, 0xE0, 0xFE, 0xA3,
++0xE0, 0xFF, 0xA3, 0xE0, 0xFD, 0x51, 0x2E, 0x90,
++0x93, 0x2A, 0xE0, 0x54, 0x7F, 0xFF, 0x90, 0x93,
++0x29, 0xE0, 0xFE, 0xC4, 0x13, 0x22, 0xD3, 0x10,
++0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x8E, 0x10, 0x8F,
++0x11, 0xBD, 0x01, 0x05, 0x12, 0x7A, 0xAE, 0x80,
++0x07, 0xAF, 0x11, 0xAE, 0x10, 0x12, 0x7C, 0x6A,
++0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF,
++0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x9C, 0xD1, 0xED,
++0xF0, 0xA3, 0xEB, 0xF0, 0x90, 0x9C, 0xD0, 0xEF,
++0xF0, 0xC3, 0x94, 0x08, 0x40, 0x04, 0xE0, 0x24,
++0xF8, 0xF0, 0x7F, 0x62, 0x51, 0xE8, 0x11, 0xCA,
++0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4, 0x5F,
++0xFD, 0x7F, 0x62, 0x12, 0x7B, 0x2E, 0x90, 0x9C,
++0xD1, 0xE0, 0x60, 0x3F, 0x7F, 0x63, 0x51, 0xE8,
++0x11, 0xCA, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC,
++0x4F, 0xFD, 0x7F, 0x63, 0x12, 0x7B, 0x2E, 0x90,
++0x9C, 0xD2, 0xE0, 0x60, 0x12, 0x51, 0xFF, 0x08,
++0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4, 0xFF,
++0x90, 0x00, 0x49, 0xE0, 0x5F, 0x80, 0x0F, 0x51,
++0xFF, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC,
++0xFF, 0x90, 0x00, 0x49, 0xE0, 0x4F, 0xFD, 0x7F,
++0x49, 0x80, 0x11, 0x7F, 0x63, 0x51, 0xE8, 0x11,
++0xCA, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4,
++0x5F, 0xFD, 0x7F, 0x63, 0x12, 0x7B, 0x2E, 0x90,
++0x00, 0x4A, 0xE0, 0x54, 0xF0, 0xFD, 0x7F, 0x4A,
++0x12, 0x7B, 0x2E, 0xD0, 0xD0, 0x92, 0xAF, 0x22,
++0x12, 0x7B, 0x41, 0x90, 0x9C, 0xD0, 0x22, 0x90,
++0x9C, 0x94, 0xE0, 0xFE, 0xA3, 0xE0, 0x22, 0x12,
++0x7B, 0x2E, 0x90, 0x9C, 0xD8, 0xE0, 0x22, 0x90,
++0x9C, 0xD0, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07,
++0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0,
++0x90, 0x01, 0xCC, 0xE0, 0x54, 0x0F, 0xFD, 0xED,
++0x70, 0x02, 0x61, 0xFC, 0x90, 0x87, 0x0B, 0xE0,
++0xFF, 0x70, 0x06, 0xA3, 0xE0, 0x64, 0x09, 0x60,
++0x0A, 0xEF, 0x14, 0xFF, 0x90, 0x87, 0x0C, 0xE0,
++0xB5, 0x07, 0x04, 0x7F, 0x01, 0x80, 0x02, 0x7F,
++0x00, 0xEF, 0x60, 0x09, 0x90, 0x01, 0xC1, 0xE0,
++0x44, 0x01, 0xF0, 0x61, 0xFC, 0x90, 0x9C, 0xE0,
++0x91, 0x0A, 0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33,
++0xCE, 0xD8, 0xF9, 0xFF, 0xED, 0xFB, 0xEF, 0x5B,
++0x70, 0x02, 0x61, 0xDF, 0xE4, 0xFC, 0x91, 0x02,
++0xA4, 0xFF, 0xEC, 0x7A, 0x00, 0x2F, 0xFF, 0xEA,
++0x35, 0xF0, 0xFE, 0x74, 0xD0, 0xB1, 0xD0, 0x90,
++0x87, 0x0C, 0xE0, 0xF9, 0x75, 0xF0, 0x08, 0x90,
++0x86, 0xBB, 0xB1, 0xDB, 0xEF, 0x91, 0x01, 0xA4,
++0xFF, 0xEC, 0x2F, 0xFF, 0xEA, 0x35, 0xF0, 0xFE,
++0x74, 0xF0, 0xB1, 0xD0, 0x75, 0xF0, 0x08, 0xE9,
++0x90, 0x86, 0xBF, 0xB1, 0xDB, 0xEF, 0xF0, 0x0C,
++0xEC, 0xB4, 0x04, 0xC2, 0x90, 0x9C, 0xE0, 0x71,
++0x02, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC,
++0xF4, 0x5D, 0xFD, 0x90, 0x9C, 0xE0, 0x71, 0x02,
++0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0x90,
++0x01, 0xCC, 0xF0, 0x90, 0x9C, 0xE0, 0xE0, 0x04,
++0xF0, 0xE0, 0x54, 0x03, 0xF0, 0x90, 0x87, 0x0C,
++0xE0, 0x04, 0xF0, 0xE0, 0x7F, 0x00, 0xB4, 0x0A,
++0x02, 0x7F, 0x01, 0xEF, 0x70, 0x02, 0x61, 0x17,
++0xE4, 0x90, 0x87, 0x0C, 0xF0, 0x61, 0x17, 0x90,
++0x01, 0xC0, 0xE0, 0x44, 0x02, 0xF0, 0x90, 0x9C,
++0xE0, 0xE0, 0x44, 0x80, 0x90, 0x00, 0x8A, 0x91,
++0x01, 0x90, 0x01, 0xD0, 0x12, 0x04, 0x6E, 0xE0,
++0x90, 0x01, 0xC3, 0xF0, 0xD0, 0xD0, 0x92, 0xAF,
++0x22, 0xF0, 0x90, 0x9C, 0xE0, 0xE0, 0x75, 0xF0,
++0x04, 0x22, 0xE0, 0xFF, 0x74, 0x01, 0x7E, 0x00,
++0xA8, 0x07, 0x08, 0x22, 0x12, 0xE7, 0x60, 0xA3,
++0xED, 0xF0, 0x90, 0x98, 0x47, 0xE0, 0xFF, 0x12,
++0x7B, 0x07, 0x90, 0x9A, 0x37, 0xE4, 0xF0, 0xA3,
++0xEF, 0xF0, 0x90, 0xFD, 0x10, 0xE0, 0x90, 0x9A,
++0x37, 0x75, 0xF0, 0x00, 0x12, 0x02, 0xE7, 0xE4,
++0x90, 0x9A, 0x41, 0xF0, 0x90, 0x93, 0x27, 0xE0,
++0x54, 0x07, 0xFF, 0x90, 0x9A, 0x41, 0xE0, 0xC3,
++0x9F, 0x40, 0x02, 0xA1, 0xAD, 0x90, 0x9A, 0x35,
++0xE0, 0x24, 0x04, 0xFE, 0x12, 0xA6, 0x2F, 0x90,
++0x9A, 0x39, 0xF0, 0xA3, 0xCE, 0xF0, 0x90, 0x9A,
++0x38, 0xE0, 0x24, 0x01, 0xFF, 0x90, 0x9A, 0x37,
++0xB1, 0xBE, 0x7F, 0x00, 0xFE, 0xC0, 0x06, 0xC0,
++0x07, 0x90, 0x9A, 0x37, 0xE0, 0xFE, 0xA3, 0xE0,
++0xFF, 0x12, 0x7A, 0x7E, 0xEF, 0xFD, 0xD0, 0xE0,
++0x2D, 0xFF, 0xD0, 0xE0, 0x34, 0x00, 0xFE, 0x90,
++0x9A, 0x3B, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x9A,
++0x38, 0xE0, 0x24, 0x02, 0xFD, 0x90, 0x9A, 0x37,
++0xE0, 0x34, 0x00, 0xFC, 0x90, 0x9A, 0x3F, 0xF0,
++0xA3, 0xED, 0xF0, 0x2F, 0x12, 0xFB, 0x32, 0x90,
++0x9A, 0x44, 0x74, 0x01, 0xF0, 0xE4, 0x90, 0x9A,
++0x43, 0xF0, 0x90, 0x9A, 0x43, 0xE0, 0xFF, 0xFD,
++0xD3, 0x90, 0x9A, 0x3C, 0xE0, 0x9D, 0x90, 0x9A,
++0x3B, 0xE0, 0x94, 0x00, 0x50, 0x02, 0xA1, 0x79,
++0xEF, 0xB4, 0x12, 0x09, 0x12, 0xA6, 0x24, 0xCF,
++0x24, 0x06, 0x12, 0xFB, 0x3D, 0x90, 0x9A, 0x43,
++0xE0, 0x75, 0xF0, 0x02, 0xA4, 0xFD, 0xAC, 0xF0,
++0xAE, 0x04, 0x78, 0x03, 0xCE, 0xA2, 0xE7, 0x13,
++0xCE, 0x13, 0xD8, 0xF8, 0xFF, 0xED, 0x54, 0x07,
++0x90, 0x9A, 0x42, 0xF0, 0x90, 0x9A, 0x3E, 0xE0,
++0x2F, 0x12, 0xA3, 0xBD, 0xFE, 0x12, 0x7A, 0x7E,
++0x90, 0x9A, 0x45, 0xEF, 0xF0, 0xFD, 0x90, 0x9A,
++0x42, 0x91, 0x0A, 0x80, 0x05, 0xC3, 0x33, 0xCE,
++0x33, 0xCE, 0xD8, 0xF9, 0xFF, 0xEF, 0x5D, 0x6F,
++0x70, 0x01, 0xEE, 0x70, 0x16, 0xB1, 0xB0, 0x54,
++0x0F, 0xFF, 0xC0, 0x07, 0xB1, 0xC7, 0x12, 0xA2,
++0x3A, 0xEF, 0x54, 0x0F, 0xD0, 0x07, 0x6F, 0x60,
++0x02, 0x80, 0x32, 0x90, 0x9A, 0x42, 0xE0, 0x04,
++0x91, 0x0B, 0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33,
++0xCE, 0xD8, 0xF9, 0xFF, 0x90, 0x9A, 0x45, 0xE0,
++0xFD, 0xEF, 0x5D, 0x6F, 0x70, 0x01, 0xEE, 0x70,
++0x1B, 0xB1, 0xB0, 0x54, 0xF0, 0xFF, 0xC0, 0x07,
++0xB1, 0xC7, 0x12, 0xA2, 0x3A, 0xEF, 0x54, 0xF0,
++0xD0, 0x07, 0x6F, 0x60, 0x07, 0xE4, 0x90, 0x9A,
++0x44, 0xF0, 0x80, 0x0D, 0x90, 0x9A, 0x39, 0xF1,
++0xF1, 0x90, 0x9A, 0x43, 0xE0, 0x04, 0xF0, 0x81,
++0xB2, 0x90, 0x9A, 0x44, 0xE0, 0xB4, 0x01, 0x03,
++0x7F, 0x01, 0x22, 0x90, 0x9A, 0x3C, 0xE0, 0x24,
++0x03, 0x12, 0xFB, 0x04, 0xEF, 0x78, 0x02, 0xCE,
++0xC3, 0x13, 0xCE, 0x13, 0xD8, 0xF9, 0xFF, 0x90,
++0x9A, 0x3E, 0xE0, 0x2F, 0xFF, 0x90, 0x9A, 0x3D,
++0xE0, 0x3E, 0x12, 0xFB, 0xCB, 0x90, 0x9A, 0x41,
++0xE0, 0x04, 0xF0, 0x81, 0x3C, 0x7F, 0x00, 0x22,
++0x90, 0x9A, 0x43, 0xE0, 0xFF, 0x90, 0x9A, 0x40,
++0xE0, 0x2F, 0xFF, 0x90, 0x9A, 0x3F, 0xE0, 0x34,
++0x00, 0xFE, 0x12, 0x7A, 0x7E, 0xEF, 0x22, 0x90,
++0x9A, 0x39, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x22,
++0x2F, 0xF5, 0x82, 0x74, 0x01, 0x3E, 0xF5, 0x83,
++0xE0, 0xFF, 0x22, 0x12, 0x04, 0x6E, 0xE5, 0x82,
++0x2C, 0xF5, 0x82, 0xE4, 0x35, 0x83, 0xF5, 0x83,
++0x22, 0xE4, 0x90, 0x9A, 0x0C, 0xF0, 0x12, 0xE3,
++0x85, 0x12, 0xFB, 0xDA, 0xE4, 0xFF, 0x12, 0xCA,
++0xF1, 0x90, 0x93, 0x0C, 0xE0, 0x20, 0xE0, 0x02,
++0xC1, 0xE5, 0x90, 0x00, 0x02, 0xE0, 0x44, 0x02,
++0xF0, 0xE4, 0x90, 0x9A, 0x0D, 0xF0, 0x90, 0x9A,
++0x0D, 0xE0, 0xFF, 0xC3, 0x94, 0x05, 0x50, 0x2F,
++0x91, 0x0C, 0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33,
++0xCE, 0xD8, 0xF9, 0xFF, 0x90, 0x93, 0x0F, 0xE0,
++0xFD, 0xEF, 0x5D, 0x60, 0x12, 0x90, 0x9A, 0x0D,
++0x12, 0xFA, 0x40, 0x90, 0x9A, 0x0D, 0x12, 0xFA,
++0x1F, 0x44, 0x40, 0xF0, 0x12, 0xCB, 0x91, 0x90,
++0x9A, 0x0D, 0xE0, 0x04, 0xF0, 0x80, 0xC7, 0x90,
++0x07, 0xC7, 0xE4, 0xF0, 0x90, 0x07, 0xC6, 0xF0,
++0x90, 0x07, 0xC5, 0x74, 0x77, 0xF0, 0x90, 0x07,
++0xC4, 0xE4, 0xF0, 0x90, 0x07, 0xC0, 0x74, 0x38,
++0xF0, 0xA3, 0xE4, 0xF0, 0xA3, 0x74, 0x0F, 0xF0,
++0xA3, 0x74, 0xC0, 0xF0, 0x90, 0x02, 0x26, 0xE0,
++0x44, 0x01, 0xF0, 0xE0, 0x90, 0x9A, 0x0E, 0xF0,
++0x90, 0x9A, 0x0E, 0xE0, 0x30, 0xE0, 0x18, 0x90,
++0x9A, 0x0C, 0xE0, 0x04, 0xD1, 0xF6, 0x90, 0x02,
++0x26, 0xE0, 0x90, 0x9A, 0x0E, 0xF0, 0x90, 0x9A,
++0x0C, 0xE0, 0xD3, 0x94, 0xFA, 0x40, 0xE1, 0x90,
++0x02, 0x03, 0x74, 0x80, 0xF0, 0x90, 0x04, 0x24,
++0xE0, 0x90, 0x9A, 0x0F, 0xF0, 0x90, 0x04, 0x22,
++0xE0, 0x44, 0x10, 0xF0, 0x90, 0x02, 0x00, 0xE0,
++0x90, 0x9A, 0x0E, 0xF0, 0x90, 0x02, 0x01, 0xD1,
++0xED, 0x90, 0x02, 0x02, 0xD1, 0xED, 0x90, 0x02,
++0x14, 0xD1, 0xED, 0xE0, 0x04, 0xF0, 0xE0, 0x90,
++0x04, 0x24, 0xF0, 0x90, 0x04, 0x22, 0xE0, 0x54,
++0xEF, 0xF0, 0x90, 0x9A, 0x0F, 0xE0, 0x90, 0x04,
++0x24, 0xF0, 0x90, 0xFD, 0x09, 0x74, 0xFF, 0xF0,
++0x90, 0xFD, 0x08, 0xE4, 0xF0, 0x90, 0x88, 0x32,
++0xE0, 0x54, 0xEF, 0xF0, 0x22, 0xE0, 0xFF, 0x90,
++0x9A, 0x0E, 0xE0, 0x2F, 0xF0, 0x22, 0xF0, 0x7F,
++0x0A, 0x7E, 0x00, 0x02, 0x7C, 0x6A, 0xF1, 0x99,
++0x30, 0xE0, 0x22, 0xF1, 0xBA, 0x70, 0x19, 0x90,
++0x93, 0x2D, 0xE0, 0x30, 0xE0, 0x0E, 0xF1, 0x7C,
++0x90, 0x93, 0x2D, 0xE0, 0xC4, 0x54, 0x0F, 0x20,
++0xE0, 0x02, 0xD1, 0xF7, 0xF1, 0xB0, 0x80, 0x03,
++0xF1, 0xA0, 0xFD, 0x41, 0x4D, 0x90, 0x93, 0x2D,
++0xE0, 0x30, 0xE0, 0x10, 0xF1, 0x7C, 0x90, 0x93,
++0x2D, 0xE0, 0xC4, 0x54, 0x0F, 0x20, 0xE0, 0x02,
++0xD1, 0xF7, 0xF1, 0xA8, 0x22, 0xF1, 0x99, 0x30,
++0xE0, 0x22, 0xF1, 0xBA, 0x70, 0x19, 0x90, 0x93,
++0x2D, 0xE0, 0x30, 0xE0, 0x0E, 0xF1, 0x7C, 0x90,
++0x93, 0x2D, 0xE0, 0xC4, 0x54, 0x0F, 0x20, 0xE0,
++0x02, 0xD1, 0xF7, 0xF1, 0xB0, 0x80, 0x03, 0xF1,
++0xA0, 0xFD, 0x41, 0x4D, 0x90, 0x93, 0x2D, 0xE0,
++0x30, 0xE0, 0x10, 0xF1, 0x7C, 0x90, 0x93, 0x2D,
++0xE0, 0xC4, 0x54, 0x0F, 0x20, 0xE0, 0x02, 0xD1,
++0xF7, 0xF1, 0xA8, 0x22, 0x90, 0x00, 0xCC, 0xE0,
++0x44, 0x04, 0xF0, 0x7F, 0x02, 0x12, 0x7B, 0x41,
++0xEF, 0x54, 0xFB, 0xFD, 0x7F, 0x02, 0x12, 0x7B,
++0x2E, 0x90, 0x00, 0xCC, 0xE0, 0x54, 0xFB, 0xF0,
++0x22, 0x90, 0x93, 0x2D, 0xE0, 0xC3, 0x13, 0x22,
++0x90, 0x98, 0x48, 0xE0, 0xFF, 0xE4, 0xFB, 0x22,
++0x90, 0x93, 0x2D, 0xE0, 0x54, 0xFE, 0xF0, 0x22,
++0x90, 0x98, 0x48, 0xE0, 0xFF, 0x7B, 0x01, 0x7D,
++0x01, 0x22, 0x7F, 0x60, 0x12, 0x7B, 0x41, 0xEF,
++0x54, 0x01, 0x90, 0x98, 0x4A, 0xF0, 0x22, 0xD3,
++0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x12, 0xCB,
++0x98, 0xB1, 0xE9, 0xD0, 0xD0, 0x92, 0xAF, 0x22,
++0x90, 0x88, 0x39, 0xE0, 0xFF, 0x60, 0x03, 0xB4,
++0x08, 0x0E, 0x12, 0xF8, 0xCE, 0xBF, 0x01, 0x08,
++0xF1, 0xC7, 0x90, 0x01, 0xE5, 0xE0, 0x04, 0xF0,
++0x22, 0xE4, 0x75, 0xF0, 0x01, 0x02, 0x02, 0xE7,
++0x22, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++0x00, 0x00, 0x00, 0x00, 0x12, 0x02, 0x06, 0x54,
++0x01, 0xFF, 0x90, 0x93, 0x0C, 0xE0, 0x54, 0xFE,
++0x4F, 0xF0, 0x30, 0xE0, 0x04, 0xE4, 0x12, 0x9F,
++0xAE, 0x22, 0x12, 0x02, 0x06, 0xFF, 0x90, 0x98,
++0x58, 0xF0, 0xBF, 0x01, 0x0A, 0x7F, 0x01, 0x12,
++0x90, 0x50, 0xE4, 0x90, 0x98, 0x58, 0xF0, 0x22,
++0xE4, 0xFD, 0x02, 0x8F, 0xF5, 0xEF, 0xB4, 0xFF,
++0x06, 0x90, 0x98, 0x6A, 0xED, 0xF0, 0x22, 0xEF,
++0xF4, 0xFE, 0x90, 0x98, 0x6A, 0xE0, 0x5E, 0xFE,
++0xED, 0x5F, 0x4E, 0xF0, 0x22, 0xEF, 0xB4, 0xFF,
++0x06, 0x90, 0x98, 0x6B, 0xED, 0xF0, 0x22, 0xEF,
++0xF4, 0xFE, 0x90, 0x98, 0x6B, 0x80, 0xE6, 0x90,
++0x9C, 0xE1, 0xED, 0xF0, 0x64, 0x01, 0x60, 0x26,
++0xE0, 0xFE, 0x64, 0x02, 0x60, 0x20, 0xEE, 0x64,
++0x29, 0x60, 0x1B, 0xEE, 0x64, 0x2A, 0x60, 0x16,
++0xEE, 0x64, 0x36, 0x60, 0x11, 0xEE, 0xB4, 0x37,
++0x02, 0x80, 0x0B, 0xAD, 0x07, 0x7F, 0xFF, 0x11,
++0x4D, 0x90, 0x98, 0x6B, 0xE0, 0xFF, 0x90, 0x98,
++0x6A, 0xE0, 0x4F, 0x90, 0x05, 0x22, 0xF0, 0x90,
++0x9C, 0xE1, 0xE0, 0x90, 0x93, 0x01, 0xF0, 0x22,
++0x12, 0xDE, 0x6E, 0x64, 0x01, 0x60, 0x02, 0x21,
++0x33, 0xEF, 0x24, 0x39, 0x60, 0x12, 0x14, 0x60,
++0x19, 0x24, 0x02, 0x70, 0x1F, 0xE4, 0x90, 0x99,
++0xB7, 0xF0, 0xA3, 0x74, 0x06, 0xF0, 0x80, 0x14,
++0x90, 0x99, 0xB7, 0x74, 0x06, 0xF0, 0xA3, 0xF0,
++0x80, 0x0A, 0x90, 0x99, 0xB7, 0x74, 0x0C, 0xF0,
++0xA3, 0x74, 0x04, 0xF0, 0xB1, 0xFC, 0xF0, 0x71,
++0xE7, 0x40, 0x20, 0x90, 0x99, 0xB5, 0xE0, 0x12,
++0xFB, 0x73, 0x7A, 0x99, 0x79, 0xB4, 0x12, 0x5F,
++0xA6, 0xBF, 0x01, 0x07, 0x90, 0x99, 0xB4, 0xE0,
++0xF4, 0x70, 0x40, 0x31, 0x34, 0xA3, 0xE0, 0x14,
++0xF0, 0x80, 0xDC, 0xB1, 0xFC, 0xF0, 0x71, 0xE7,
++0x40, 0x31, 0x90, 0x99, 0xB5, 0xE0, 0xFD, 0x7C,
++0x00, 0x24, 0xA8, 0xFF, 0xEC, 0x34, 0x01, 0xFE,
++0xED, 0x24, 0x01, 0xFD, 0xEC, 0x33, 0xFC, 0x90,
++0x99, 0xB7, 0xE0, 0x12, 0xFB, 0x69, 0xF1, 0x9B,
++0x8D, 0x82, 0x8C, 0x83, 0x12, 0x02, 0x1F, 0xFD,
++0x12, 0xC8, 0x3B, 0x31, 0x34, 0xA3, 0xE0, 0x14,
++0xF0, 0x80, 0xCB, 0x22, 0x90, 0x99, 0xB5, 0xE0,
++0x04, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3,
++0xC0, 0xD0, 0xE4, 0x90, 0x99, 0xB1, 0xF0, 0xA3,
++0xF0, 0x90, 0x99, 0xB6, 0xF0, 0x90, 0x02, 0x09,
++0xE0, 0x90, 0x99, 0xB7, 0xF0, 0x90, 0x98, 0x45,
++0xF1, 0xF0, 0x90, 0x99, 0xB1, 0xEE, 0xF0, 0xA3,
++0xEF, 0xF0, 0x12, 0x8E, 0x99, 0xE0, 0x90, 0x95,
++0xE9, 0xF0, 0x74, 0x01, 0x2F, 0x71, 0xF5, 0xE0,
++0x90, 0x95, 0xEA, 0xF0, 0x71, 0xDF, 0x12, 0x02,
++0xE7, 0x90, 0x99, 0xB1, 0xA3, 0xE0, 0x24, 0x02,
++0x12, 0xD6, 0xEB, 0xFF, 0xE4, 0xFC, 0xFD, 0x78,
++0x10, 0x12, 0x03, 0xFE, 0xC0, 0x04, 0xC0, 0x05,
++0xC0, 0x06, 0xC0, 0x07, 0x71, 0xD2, 0x12, 0xAF,
++0x19, 0x78, 0x18, 0x12, 0x03, 0xFE, 0xD0, 0x03,
++0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x80,
++0xC0, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0,
++0x07, 0x71, 0xC5, 0x12, 0xAF, 0x19, 0x78, 0x08,
++0x12, 0x03, 0xFE, 0xD0, 0x03, 0xD0, 0x02, 0xD0,
++0x01, 0xD0, 0x00, 0x12, 0x8E, 0x89, 0x12, 0xAF,
++0x1B, 0x12, 0x80, 0xC0, 0x90, 0x95, 0xED, 0x12,
++0xAF, 0x00, 0x78, 0x10, 0x12, 0x03, 0xFE, 0xC0,
++0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x71,
++0xD2, 0x12, 0xAF, 0x19, 0x78, 0x18, 0x12, 0x03,
++0xFE, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0,
++0x00, 0x12, 0x80, 0xC0, 0xC0, 0x04, 0xC0, 0x05,
++0xC0, 0x06, 0xC0, 0x07, 0x71, 0xC5, 0x12, 0xAF,
++0x19, 0x78, 0x08, 0x12, 0x03, 0xFE, 0xD0, 0x03,
++0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x8E,
++0x89, 0x12, 0xAF, 0x1B, 0x12, 0x80, 0xC0, 0x90,
++0x95, 0xF1, 0x12, 0xAF, 0x00, 0x78, 0x10, 0x12,
++0x03, 0xFE, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06,
++0xC0, 0x07, 0x71, 0xD2, 0x12, 0xAF, 0x19, 0x78,
++0x18, 0x12, 0x03, 0xFE, 0xD0, 0x03, 0xD0, 0x02,
++0xD0, 0x01, 0xD0, 0x00, 0x12, 0x80, 0xC0, 0xC0,
++0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x71,
++0xC5, 0x12, 0xAF, 0x19, 0x78, 0x08, 0x12, 0x03,
++0xFE, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0,
++0x00, 0x12, 0x8E, 0x89, 0x12, 0xAF, 0x1B, 0x12,
++0x80, 0xC0, 0x90, 0x95, 0xF5, 0x12, 0x04, 0x31,
++0x71, 0xDF, 0x71, 0xB1, 0x71, 0xBA, 0x12, 0x8E,
++0x99, 0xE0, 0xFF, 0x12, 0xFB, 0x7D, 0x71, 0x9F,
++0xE0, 0xB4, 0x10, 0xF0, 0x71, 0xAA, 0x71, 0xBA,
++0x12, 0x8E, 0x99, 0xE0, 0xFF, 0x74, 0x09, 0x2E,
++0xF5, 0x82, 0xE4, 0x34, 0x96, 0x71, 0x9F, 0xE0,
++0xB4, 0x10, 0xEB, 0x71, 0xAA, 0x71, 0xBA, 0x12,
++0x8E, 0x99, 0xE0, 0xFF, 0x74, 0x19, 0x2E, 0xF5,
++0x82, 0xE4, 0x34, 0x96, 0x71, 0x9F, 0xE0, 0xB4,
++0x10, 0xEB, 0x90, 0x99, 0xB1, 0xF1, 0xA1, 0x90,
++0x98, 0x45, 0x12, 0x8E, 0x80, 0xE4, 0xF0, 0xA3,
++0xEF, 0xF0, 0x90, 0x99, 0xB1, 0xE4, 0x75, 0xF0,
++0x40, 0x71, 0xB1, 0x90, 0x99, 0xB3, 0xE0, 0xFF,
++0xC3, 0x94, 0x08, 0x50, 0x1F, 0x90, 0x99, 0xB1,
++0xA3, 0xE0, 0xFE, 0xEF, 0x2E, 0x12, 0x8E, 0x99,
++0xE0, 0xFE, 0x90, 0x99, 0xB7, 0xE0, 0xFD, 0xEE,
++0x2D, 0xFE, 0x74, 0x29, 0x2F, 0xF1, 0xE8, 0xEE,
++0x71, 0xA2, 0x80, 0xD7, 0x90, 0x98, 0x45, 0xE0,
++0x04, 0x90, 0x99, 0xB5, 0xF0, 0xE4, 0x90, 0x99,
++0xB4, 0xF0, 0x90, 0x95, 0xE9, 0xE0, 0x13, 0x13,
++0x54, 0x3F, 0x24, 0x01, 0xFF, 0xE4, 0x33, 0xFE,
++0x90, 0x99, 0xB4, 0xE0, 0xC3, 0x9F, 0xEE, 0xD1,
++0xA5, 0x50, 0x75, 0xA3, 0x12, 0x8E, 0x80, 0xE4,
++0xF0, 0xA3, 0xEF, 0xF0, 0xE4, 0xA3, 0xF0, 0x90,
++0x99, 0xB3, 0xE0, 0xFD, 0xC3, 0x94, 0x04, 0x50,
++0x55, 0xA3, 0xE0, 0x75, 0xF0, 0x04, 0xA4, 0x7C,
++0x00, 0x2D, 0xFF, 0xEC, 0x35, 0xF0, 0xFE, 0x90,
++0x95, 0xE9, 0xE0, 0xFD, 0xC3, 0xEF, 0x9D, 0x74,
++0x80, 0xF8, 0x6E, 0x98, 0x50, 0x38, 0xEF, 0x78,
++0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9,
++0x24, 0x31, 0xF9, 0x74, 0x96, 0x3E, 0xFA, 0x7B,
++0x01, 0xC0, 0x03, 0xC0, 0x01, 0x90, 0x99, 0xB1,
++0xA3, 0xE0, 0x24, 0x00, 0xF9, 0xE4, 0x34, 0xFC,
++0x8B, 0x45, 0xF5, 0x46, 0x89, 0x47, 0x75, 0x48,
++0x20, 0xD0, 0x01, 0xD0, 0x03, 0x12, 0x8F, 0x63,
++0xF1, 0xA8, 0x71, 0xA3, 0x80, 0xA1, 0x31, 0x34,
++0x90, 0x99, 0xB4, 0xE0, 0x04, 0xF0, 0x41, 0xFA,
++0xE4, 0x90, 0x99, 0xB3, 0xF0, 0xE4, 0xFF, 0x0F,
++0xEF, 0xB4, 0x20, 0xFB, 0x71, 0xA3, 0xE0, 0xB4,
++0x10, 0xF3, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xF5,
++0x83, 0xEF, 0xF0, 0x90, 0x99, 0xB3, 0xE0, 0x04,
++0xF0, 0x22, 0x90, 0x99, 0xB1, 0xE4, 0x75, 0xF0,
++0x10, 0x12, 0x02, 0xE7, 0xE4, 0x90, 0x99, 0xB3,
++0xF0, 0x22, 0x90, 0x99, 0xB1, 0xA3, 0xE0, 0xFF,
++0xA3, 0xE0, 0xFE, 0x2F, 0x22, 0x90, 0x99, 0xB1,
++0xA3, 0xE0, 0x24, 0x01, 0xF5, 0x82, 0xE4, 0x34,
++0xFC, 0x22, 0x90, 0x99, 0xB1, 0xA3, 0xE0, 0x24,
++0x03, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0x22, 0x90,
++0x99, 0xB1, 0xE4, 0x75, 0xF0, 0x04, 0x22, 0x90,
++0x99, 0xB6, 0xE0, 0xD3, 0x94, 0x00, 0x22, 0x74,
++0x03, 0xF0, 0x74, 0x01, 0x2E, 0xF5, 0x82, 0xE4,
++0x34, 0xFC, 0xF5, 0x83, 0x22, 0xD3, 0x10, 0xAF,
++0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x9C, 0x6E, 0xEC,
++0xF1, 0xE0, 0xAA, 0x07, 0x90, 0x9C, 0x75, 0x12,
++0x04, 0x3D, 0x00, 0x00, 0x00, 0x00, 0xB1, 0xF1,
++0xEA, 0x24, 0xEF, 0x60, 0x3A, 0x24, 0xD7, 0x70,
++0x02, 0xA1, 0x59, 0x24, 0x3A, 0x60, 0x02, 0xA1,
++0x93, 0xB1, 0xC7, 0x24, 0x0A, 0xB1, 0xD5, 0xED,
++0xF0, 0xFE, 0x12, 0x8E, 0x99, 0xE4, 0x71, 0xF1,
++0xE4, 0xF0, 0xFE, 0x74, 0x00, 0x2F, 0xB1, 0xE9,
++0x7D, 0x14, 0xB1, 0xB0, 0x12, 0xB7, 0x9B, 0xB1,
++0xBB, 0x90, 0x90, 0xBE, 0x12, 0x04, 0x31, 0x7D,
++0x14, 0x7C, 0x00, 0xE4, 0xFF, 0xA1, 0x54, 0x90,
++0x9C, 0x6E, 0xE4, 0x75, 0xF0, 0x14, 0x12, 0x02,
++0xE7, 0x90, 0x9C, 0x6E, 0xA3, 0xE0, 0xFB, 0xFF,
++0x24, 0x06, 0xFC, 0xB1, 0xD6, 0xCC, 0xF0, 0x90,
++0x9C, 0x79, 0xA3, 0xE0, 0xFE, 0x12, 0x8E, 0x99,
++0xE4, 0x71, 0xF1, 0xE4, 0x12, 0xD6, 0xF4, 0xFE,
++0xA9, 0x03, 0x74, 0x05, 0x29, 0xF1, 0xAF, 0xF1,
++0x92, 0xFE, 0x90, 0x9C, 0x73, 0xF0, 0xA3, 0xEF,
++0xF0, 0x90, 0x9C, 0x6E, 0xE0, 0xFC, 0xA3, 0xE0,
++0x2F, 0xFF, 0xEC, 0x3E, 0xFE, 0xD3, 0xEF, 0x94,
++0x00, 0xEE, 0x94, 0x01, 0x90, 0x9C, 0x6E, 0x40,
++0x67, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xE9, 0x7C,
++0x00, 0x24, 0x00, 0xF9, 0xEC, 0x34, 0xFC, 0xFA,
++0x7B, 0x01, 0xC3, 0xE4, 0x9F, 0xFD, 0x74, 0x01,
++0x9E, 0xFC, 0xB1, 0xB2, 0x90, 0x9C, 0x70, 0xE0,
++0x24, 0x01, 0xFF, 0xE4, 0x33, 0xA2, 0xE7, 0x13,
++0xEF, 0x13, 0x90, 0xFD, 0x10, 0xF0, 0xB1, 0xE3,
++0xC0, 0x00, 0xC0, 0x01, 0xC0, 0x02, 0xC0, 0x03,
++0x7B, 0x01, 0x7A, 0xFC, 0x79, 0x00, 0x90, 0x9C,
++0x6E, 0x12, 0xA7, 0xEF, 0xE4, 0x9F, 0xFF, 0x74,
++0x01, 0x9E, 0xFE, 0xB1, 0xCE, 0xE0, 0xC3, 0x9F,
++0xFD, 0xEC, 0x9E, 0xFC, 0x12, 0x45, 0xC2, 0xD0,
++0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12,
++0x80, 0xC0, 0xB1, 0xB5, 0xB1, 0xF1, 0x80, 0x0E,
++0xA3, 0xE0, 0x7E, 0x00, 0x24, 0x00, 0xB1, 0xE9,
++0xB1, 0xCE, 0xE0, 0xFD, 0xB1, 0xB2, 0x90, 0x9C,
++0x6E, 0x74, 0xFF, 0x75, 0xF0, 0xEC, 0x12, 0x02,
++0xE7, 0xB1, 0xC7, 0x7E, 0x00, 0x24, 0x0C, 0xF9,
++0xEE, 0x34, 0xFC, 0xFA, 0x7B, 0x01, 0xC0, 0x02,
++0xC0, 0x01, 0x74, 0x10, 0x2F, 0xF9, 0xEE, 0x34,
++0xFC, 0xFA, 0xB1, 0xBB, 0x90, 0x90, 0xBE, 0x12,
++0x04, 0x31, 0xB1, 0xCE, 0xE0, 0xFD, 0xD0, 0x01,
++0xD0, 0x02, 0x7F, 0x11, 0x12, 0x3C, 0xD9, 0x80,
++0x32, 0xB1, 0xC7, 0x24, 0x2A, 0xB1, 0xD5, 0xED,
++0xF0, 0xFE, 0x12, 0x8E, 0x99, 0xE4, 0x71, 0xF1,
++0xE4, 0xF0, 0x12, 0xEE, 0xA3, 0x7D, 0x48, 0xB1,
++0xB0, 0xB1, 0xC1, 0xB1, 0xDE, 0x12, 0x80, 0xC0,
++0xE4, 0xFD, 0xFC, 0xB1, 0xB5, 0xB1, 0xC1, 0xB1,
++0xDE, 0x12, 0x80, 0xC0, 0xB1, 0xB5, 0xB1, 0xC1,
++0x12, 0x03, 0xCD, 0x90, 0x9C, 0x71, 0xEE, 0xF0,
++0xA3, 0xEF, 0xF0, 0x90, 0x9C, 0x71, 0xE0, 0xFC,
++0xA3, 0xE0, 0xFD, 0xEC, 0xFF, 0x90, 0x9C, 0x79,
++0xA3, 0xE0, 0xFE, 0x12, 0x8E, 0x99, 0xEF, 0x71,
++0xF1, 0xED, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22,
++0x7C, 0x00, 0x12, 0x45, 0xC2, 0x90, 0x9C, 0x75,
++0x02, 0x04, 0x31, 0x90, 0x90, 0xBB, 0x12, 0x82,
++0x27, 0x90, 0x9C, 0x75, 0x02, 0x04, 0xB8, 0x90,
++0x9C, 0x6E, 0xA3, 0xE0, 0xFF, 0x22, 0x90, 0x9C,
++0x73, 0xE0, 0xFC, 0xA3, 0x22, 0xFD, 0xE4, 0x33,
++0x90, 0x9C, 0x79, 0xF0, 0xA3, 0x22, 0x78, 0x10,
++0x12, 0x03, 0xEB, 0x90, 0x9C, 0x75, 0x02, 0x82,
++0x12, 0xF9, 0xEE, 0x34, 0xFC, 0xFA, 0x7B, 0x01,
++0x22, 0x90, 0x9C, 0x70, 0xE0, 0xC3, 0x13, 0x90,
++0xFD, 0x10, 0xF0, 0x22, 0x90, 0x99, 0xB7, 0xE0,
++0x90, 0x99, 0xB5, 0xF0, 0x90, 0x99, 0xB8, 0xE0,
++0x90, 0x99, 0xB6, 0x22, 0xE4, 0x90, 0x9A, 0xFE,
++0xF0, 0xA3, 0xF0, 0x90, 0x06, 0x32, 0xE0, 0x44,
++0x20, 0xF0, 0x12, 0x76, 0x9B, 0xEF, 0x64, 0x01,
++0x70, 0x75, 0x90, 0x98, 0x42, 0xE0, 0xFF, 0x90,
++0x92, 0x13, 0x74, 0x0D, 0xF0, 0x7B, 0x08, 0x7D,
++0x01, 0x12, 0x66, 0xDB, 0x90, 0x9A, 0xFB, 0xEE,
++0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x9A, 0xFB, 0x12,
++0x8E, 0xA3, 0x90, 0x9A, 0xFD, 0xEF, 0xF0, 0x90,
++0x9A, 0xFB, 0x12, 0xFA, 0xAE, 0x7B, 0x01, 0xE4,
++0xFD, 0x12, 0xE7, 0xF7, 0x90, 0x9A, 0xFD, 0xE0,
++0xFF, 0x90, 0x9A, 0xFC, 0xE0, 0x2F, 0xFF, 0x90,
++0x9A, 0xFB, 0xE0, 0x34, 0x00, 0xCF, 0x24, 0x30,
++0xCF, 0x34, 0x00, 0xFE, 0x90, 0x9A, 0xFE, 0xF0,
++0xA3, 0xEF, 0xF0, 0xF1, 0xB7, 0xD1, 0x98, 0x90,
++0x98, 0x42, 0xE0, 0xFB, 0xE4, 0xFF, 0x71, 0xFD,
++0xD1, 0x98, 0x90, 0x98, 0x3E, 0xE0, 0xFB, 0x7F,
++0x11, 0x71, 0xFD, 0x90, 0x04, 0x1F, 0x74, 0x20,
++0xF0, 0x90, 0x95, 0xA5, 0x12, 0xBF, 0xF1, 0x22,
++0x90, 0x9A, 0xFE, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD,
++0x22, 0xE0, 0xD3, 0x9D, 0xEC, 0x64, 0x80, 0xF8,
++0x74, 0x80, 0x98, 0x22, 0xD3, 0x10, 0xAF, 0x01,
++0xC3, 0xC0, 0xD0, 0x12, 0xE3, 0xD4, 0x90, 0x9C,
++0xE7, 0xF0, 0x90, 0x88, 0x32, 0x12, 0xA8, 0xAD,
++0x30, 0xE0, 0x02, 0xE1, 0x74, 0x90, 0x88, 0x31,
++0xE0, 0x30, 0xE0, 0x1F, 0x90, 0x88, 0x53, 0xE0,
++0x24, 0x04, 0x33, 0x33, 0x33, 0x54, 0xF8, 0x90,
++0x88, 0x4B, 0xF0, 0x90, 0x88, 0x53, 0xE0, 0x04,
++0x33, 0x33, 0x33, 0x54, 0xF8, 0x90, 0x88, 0x4A,
++0xF0, 0x80, 0x10, 0x90, 0x88, 0x4B, 0x74, 0x10,
++0xF0, 0x90, 0x88, 0x4A, 0x74, 0x08, 0xF0, 0x74,
++0x10, 0x2B, 0xFB, 0x90, 0x88, 0x4A, 0xE0, 0xFE,
++0x90, 0x88, 0x49, 0xE0, 0xD3, 0x9E, 0x50, 0x0E,
++0x90, 0x88, 0x3E, 0xEB, 0xF0, 0x90, 0x88, 0x4B,
++0xE0, 0xC3, 0x9D, 0x2F, 0x80, 0x11, 0xC3, 0xED,
++0x9E, 0x2B, 0x90, 0x88, 0x3E, 0xF0, 0x90, 0x88,
++0x4A, 0xE0, 0xFF, 0xA3, 0xE0, 0xC3, 0x9F, 0x90,
++0x88, 0x4E, 0xF0, 0x90, 0x88, 0x4B, 0xF1, 0x80,
++0x90, 0x88, 0x4E, 0xD1, 0xA1, 0x40, 0x04, 0xEF,
++0x24, 0x50, 0xF0, 0x90, 0x88, 0x4E, 0xF1, 0x80,
++0x90, 0x88, 0x3E, 0xD1, 0xA1, 0x40, 0x04, 0xEF,
++0x24, 0x50, 0xF0, 0x90, 0x88, 0x4E, 0x12, 0x97,
++0xD9, 0xFF, 0x7E, 0x00, 0x90, 0x88, 0x42, 0xEE,
++0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x05, 0x58, 0xF0,
++0x90, 0x88, 0x4E, 0xE0, 0x54, 0x07, 0xFF, 0x90,
++0x05, 0xB1, 0xE0, 0x54, 0xF8, 0x4F, 0xF0, 0x12,
++0xFB, 0xC3, 0x80, 0x07, 0x90, 0x88, 0x33, 0xE0,
++0x44, 0x01, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22,
++0xE0, 0xFF, 0x24, 0x50, 0xFD, 0xE4, 0x33, 0xFC,
++0x22, 0xF0, 0x90, 0x01, 0x17, 0xE0, 0xFE, 0x90,
++0x01, 0x16, 0xE0, 0x7C, 0x00, 0x24, 0x00, 0xFF,
++0xEC, 0x3E, 0x22, 0x90, 0x99, 0xB1, 0x02, 0x82,
++0x1E, 0xE4, 0x75, 0xF0, 0x10, 0x02, 0x02, 0xE7,
++0xE4, 0x75, 0xF0, 0x20, 0x02, 0x02, 0xE7, 0xF5,
++0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0x22, 0xAD,
++0x07, 0x90, 0x95, 0x9D, 0x12, 0xBF, 0xF1, 0x90,
++0x95, 0x9D, 0xE0, 0xFF, 0xAE, 0x05, 0x74, 0x04,
++0x2E, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83,
++0xEF, 0xF0, 0x90, 0x95, 0x9D, 0xA3, 0xE0, 0xFF,
++0x74, 0x05, 0x2E, 0xF1, 0xAF, 0xEF, 0xF0, 0x22,
++0xF0, 0xA3, 0xED, 0xF0, 0xA3, 0xEB, 0xF0, 0x22,
++0xF5, 0x82, 0xE4, 0x34, 0x96, 0xF5, 0x83, 0x22,
++0xE0, 0xFF, 0x12, 0x7B, 0x07, 0x7E, 0x00, 0x22,
++0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x7F,
++0x8F, 0x12, 0x7B, 0x41, 0xEF, 0x30, 0xE6, 0x2E,
++0x90, 0x00, 0x8C, 0xE0, 0x90, 0x9C, 0xCA, 0xF0,
++0x7F, 0x8D, 0x12, 0x7B, 0x41, 0x90, 0x9C, 0xCB,
++0xEF, 0xF0, 0x90, 0x00, 0x8E, 0xE0, 0x90, 0x9C,
++0xCC, 0xF0, 0x90, 0x9C, 0xCB, 0xE0, 0x7F, 0x8F,
++0x12, 0x7B, 0x41, 0xEF, 0x30, 0xE0, 0x07, 0xE4,
++0xFD, 0x7F, 0x8D, 0x12, 0x7B, 0x2E, 0xD0, 0xD0,
++0x92, 0xAF, 0x22, 0xE4, 0x90, 0x99, 0xB9, 0xF0,
++0x90, 0x00, 0x37, 0xE0, 0x44, 0x80, 0xF0, 0x90,
++0x00, 0xCF, 0x74, 0x69, 0xF0, 0xEF, 0x90, 0x00,
++0x31, 0xF0, 0xEE, 0x54, 0x03, 0xFF, 0xA3, 0xE0,
++0x54, 0xFC, 0x4F, 0xF0, 0x90, 0x00, 0x30, 0xED,
++0xF0, 0x90, 0x00, 0x33, 0xE0, 0x44, 0x80, 0xF0,
++0x90, 0x00, 0x33, 0xE0, 0x30, 0xE7, 0x09, 0x11,
++0x8D, 0x50, 0x05, 0xE0, 0x04, 0xF0, 0x80, 0xF0,
++0x90, 0x00, 0xCF, 0xE4, 0xF0, 0x90, 0x00, 0x37,
++0xE0, 0x54, 0x7F, 0xF0, 0x11, 0x8D, 0x7F, 0x00,
++0x50, 0x02, 0x7F, 0x01, 0x22, 0x90, 0x99, 0xB9,
++0xE0, 0xC3, 0x94, 0x64, 0x22, 0xE4, 0x90, 0x86,
++0xAF, 0x12, 0x9F, 0xAD, 0x90, 0x93, 0x01, 0xF0,
++0x90, 0x98, 0x6A, 0xF0, 0xA3, 0xF0, 0x22, 0x90,
++0x00, 0x80, 0xE0, 0x44, 0x80, 0xF0, 0x12, 0xD7,
++0xED, 0x31, 0x2D, 0x12, 0x7B, 0x79, 0x12, 0xE2,
++0x69, 0x11, 0x95, 0x7F, 0x01, 0x12, 0x85, 0x15,
++0x90, 0x98, 0x4B, 0x74, 0x02, 0xF0, 0xFF, 0x12,
++0x85, 0x15, 0x90, 0x98, 0x4B, 0xE0, 0x04, 0xF0,
++0x51, 0x90, 0x31, 0x5A, 0x90, 0x00, 0x80, 0xE0,
++0x44, 0x40, 0xF0, 0x75, 0x20, 0xFF, 0x12, 0x7C,
++0x97, 0x53, 0xA8, 0xFE, 0x90, 0x01, 0xA0, 0xE0,
++0xB4, 0xFD, 0x05, 0xE4, 0xFF, 0x12, 0x90, 0x50,
++0x71, 0x3F, 0x31, 0x42, 0x90, 0x00, 0x81, 0xE0,
++0x44, 0x04, 0xF0, 0x12, 0xD0, 0x0A, 0x12, 0x99,
++0xAE, 0x90, 0x00, 0xAA, 0xE0, 0x44, 0x02, 0xF0,
++0xA3, 0xE0, 0x44, 0x80, 0xF0, 0x90, 0x99, 0xB0,
++0xE0, 0x54, 0xFE, 0xF0, 0x90, 0x06, 0x0A, 0xE0,
++0x44, 0x10, 0xF0, 0x90, 0x07, 0xDB, 0xE0, 0x44,
++0x80, 0xF0, 0x90, 0x06, 0x0D, 0x74, 0xFF, 0xF0,
++0xE4, 0xFF, 0x02, 0x85, 0x9E, 0x90, 0x01, 0x94,
++0xE0, 0x44, 0x01, 0x80, 0x06, 0x90, 0x93, 0x31,
++0xE0, 0x54, 0xFE, 0xF0, 0x90, 0x01, 0xC7, 0xE4,
++0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0,
++0xD0, 0xE4, 0xFF, 0x12, 0xFA, 0x10, 0xE4, 0xF0,
++0x0F, 0xEF, 0xB4, 0x08, 0xF6, 0xD0, 0xD0, 0x92,
++0xAF, 0x22, 0xF1, 0xBF, 0x12, 0x7B, 0xDB, 0x12,
++0x92, 0xDB, 0x12, 0xA7, 0x7F, 0x31, 0x89, 0x51,
++0x79, 0x12, 0xDE, 0xB2, 0x90, 0x98, 0x64, 0xE0,
++0x54, 0x7F, 0xF0, 0x54, 0xBF, 0xF0, 0x54, 0xDF,
++0xF0, 0x54, 0xF0, 0xF0, 0xE4, 0x90, 0x98, 0x66,
++0xF0, 0x90, 0x98, 0x64, 0xE0, 0x54, 0xEF, 0xF0,
++0x22, 0x7E, 0x00, 0x7F, 0x29, 0x7D, 0x00, 0x7B,
++0x01, 0x7A, 0x93, 0x79, 0x24, 0x12, 0x04, 0x80,
++0x90, 0x06, 0x90, 0xE0, 0x54, 0xDF, 0xF0, 0xB1,
++0xFE, 0x12, 0x9F, 0xB5, 0x90, 0x86, 0xB3, 0xE0,
++0xFF, 0x64, 0x02, 0x70, 0x2E, 0x90, 0xFD, 0x80,
++0xE0, 0x7E, 0x00, 0x30, 0xE0, 0x02, 0x7E, 0x01,
++0x90, 0x93, 0x47, 0x51, 0x72, 0x7E, 0x00, 0x30,
++0xE1, 0x02, 0x7E, 0x01, 0x90, 0x93, 0x45, 0x51,
++0x72, 0x7E, 0x00, 0x30, 0xE2, 0x02, 0x7E, 0x01,
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++0xF0, 0x80, 0x52, 0xEF, 0x64, 0x01, 0x70, 0x21,
++0x51, 0x6B, 0x30, 0xE0, 0x02, 0x7F, 0x01, 0x90,
++0x93, 0x47, 0xEF, 0xF0, 0x51, 0x6B, 0x30, 0xE1,
++0x02, 0x7F, 0x01, 0x90, 0x93, 0x45, 0xEF, 0xF0,
++0x51, 0x6B, 0x30, 0xE2, 0x02, 0x7F, 0x01, 0x80,
++0x27, 0x90, 0x86, 0xB3, 0xE0, 0x64, 0x03, 0x70,
++0x24, 0x51, 0x64, 0x30, 0xE0, 0x02, 0x7F, 0x01,
++0x90, 0x93, 0x47, 0xEF, 0xF0, 0x51, 0x64, 0x30,
++0xE1, 0x02, 0x7F, 0x01, 0x90, 0x93, 0x45, 0xEF,
++0xF0, 0x51, 0x64, 0x30, 0xE2, 0x02, 0x7F, 0x01,
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++0xE0, 0x54, 0xEF, 0xF0, 0xE4, 0x90, 0x95, 0xE9,
++0xF0, 0xA3, 0xF0, 0x90, 0x95, 0xF1, 0x12, 0x04,
++0x3D, 0x00, 0x00, 0x00, 0x00, 0x90, 0x95, 0xF5,
++0x12, 0x04, 0x3D, 0x00, 0x00, 0x00, 0x00, 0x90,
++0x95, 0xED, 0x12, 0x04, 0x3D, 0x00, 0x00, 0x00,
++0x00, 0x90, 0x98, 0x31, 0x12, 0x04, 0x3D, 0x00,
++0x00, 0x00, 0x00, 0x22, 0x90, 0xFD, 0x78, 0xE0,
++0x7F, 0x00, 0x22, 0x90, 0xFD, 0x70, 0xE0, 0x7F,
++0x00, 0x22, 0xEE, 0xF0, 0x90, 0xFD, 0x80, 0xE0,
++0x22, 0x90, 0x98, 0x4C, 0xE0, 0x54, 0xFE, 0xF0,
++0x54, 0x7F, 0xF0, 0x54, 0xFB, 0xF0, 0xA3, 0x74,
++0x0A, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xF0, 0x22,
++0x12, 0x7B, 0x1B, 0x90, 0x86, 0xB3, 0xEF, 0xF0,
++0x51, 0xAA, 0x90, 0x01, 0x64, 0x74, 0x01, 0xF0,
++0x90, 0x04, 0x23, 0xE0, 0x44, 0x80, 0xF0, 0x02,
++0x67, 0xD2, 0x12, 0xFB, 0xDA, 0x12, 0x76, 0x6D,
++0x12, 0x75, 0xE0, 0xF1, 0x86, 0xF1, 0xEB, 0xE4,
++0xF5, 0x21, 0x90, 0x86, 0xB3, 0xE0, 0xFF, 0xB4,
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++0xF5, 0x22, 0xEF, 0xB4, 0x01, 0x0A, 0x90, 0x00,
++0x75, 0xE0, 0x54, 0xFB, 0xF0, 0x75, 0x22, 0x04,
++0x75, 0x23, 0x10, 0x75, 0x24, 0x80, 0x90, 0x00,
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++0xA3, 0xE5, 0x23, 0xF0, 0xA3, 0xE5, 0x24, 0xF0,
++0x22, 0x90, 0x9C, 0xCD, 0xEF, 0x51, 0x89, 0x90,
++0x01, 0x09, 0xE0, 0x7F, 0x00, 0x30, 0xE7, 0x02,
++0x7F, 0x01, 0x90, 0x9C, 0xCD, 0xE0, 0x6F, 0x60,
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++0x90, 0x9C, 0xCE, 0xE0, 0x94, 0x13, 0x40, 0x08,
++0x90, 0x01, 0xC0, 0xE0, 0x44, 0x10, 0xF0, 0x22,
++0x90, 0x9C, 0xCE, 0x12, 0xBF, 0xF1, 0x71, 0x91,
++0xD3, 0x90, 0x9C, 0xCF, 0xE0, 0x94, 0x32, 0x90,
++0x9C, 0xCE, 0xE0, 0x94, 0x00, 0x40, 0xC0, 0x90,
++0x01, 0xC6, 0xE0, 0x30, 0xE0, 0xB9, 0x22, 0xE4,
++0x90, 0x9C, 0xD9, 0xF0, 0xA3, 0xF0, 0x12, 0xE2,
++0xAC, 0xEF, 0x64, 0x01, 0x60, 0x3C, 0xC3, 0x90,
++0x9C, 0xDA, 0xE0, 0x94, 0x88, 0x90, 0x9C, 0xD9,
++0xE0, 0x94, 0x13, 0x40, 0x0F, 0x90, 0x01, 0xC1,
++0xE0, 0x44, 0x10, 0xF0, 0x90, 0x01, 0xC7, 0x74,
++0xFD, 0xF0, 0x80, 0x1E, 0x90, 0x9C, 0xD9, 0x12,
++0xBF, 0xF1, 0x71, 0x91, 0xD3, 0x90, 0x9C, 0xDA,
++0xE0, 0x94, 0x32, 0x90, 0x9C, 0xD9, 0xE0, 0x94,
++0x00, 0x40, 0xC3, 0x90, 0x01, 0xC6, 0xE0, 0x30,
++0xE3, 0xBC, 0x90, 0x01, 0xC7, 0x74, 0xFE, 0xF0,
++0x22, 0x7F, 0x14, 0x7E, 0x00, 0x02, 0x7C, 0x6A,
++0x75, 0x0D, 0x14, 0x90, 0x88, 0x32, 0xE0, 0x44,
++0x10, 0xF0, 0x90, 0x00, 0x06, 0xE0, 0x44, 0x40,
++0xF0, 0x90, 0x88, 0x41, 0xE0, 0x90, 0x00, 0x93,
++0xF0, 0x90, 0x88, 0x37, 0xE0, 0x60, 0x12, 0x90,
++0x01, 0x2F, 0xE0, 0x30, 0xE7, 0x05, 0x74, 0x10,
++0xF0, 0x80, 0x06, 0x90, 0x01, 0x2F, 0x74, 0x90,
++0xF0, 0x90, 0x93, 0x0C, 0xE0, 0x30, 0xE0, 0x62,
++0x90, 0xFD, 0x09, 0xE4, 0xF0, 0x90, 0xFD, 0x08,
++0xF0, 0x90, 0x0E, 0x4B, 0xE0, 0x54, 0xFC, 0xF0,
++0xE4, 0x90, 0x9A, 0x0C, 0xF0, 0x90, 0x9A, 0x0C,
++0xE0, 0xFF, 0xC3, 0x94, 0x05, 0x50, 0x2F, 0x12,
++0xBC, 0x0C, 0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33,
++0xCE, 0xD8, 0xF9, 0xFF, 0x90, 0x93, 0x0E, 0xE0,
++0xFD, 0xEF, 0x5D, 0x60, 0x11, 0x90, 0x9A, 0x0C,
++0x12, 0xFA, 0x40, 0x90, 0x9A, 0x0C, 0x12, 0xFA,
++0x1F, 0x44, 0x20, 0xF0, 0x71, 0x91, 0x90, 0x9A,
++0x0C, 0xE0, 0x04, 0xF0, 0x80, 0xC7, 0x90, 0x00,
++0x92, 0xE0, 0x54, 0xFE, 0xF0, 0xE0, 0x44, 0x08,
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++0x80, 0x07, 0x90, 0x00, 0x92, 0xE0, 0x44, 0x01,
++0xF0, 0x90, 0x00, 0x08, 0xE0, 0x44, 0x10, 0xF0,
++0x7F, 0x01, 0x51, 0xF1, 0x90, 0x00, 0x90, 0xE0,
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++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F,
++0x14, 0x7E, 0x00, 0x02, 0x7C, 0x6A, 0xEF, 0x70,
++0x02, 0xA1, 0x68, 0x90, 0x06, 0x0F, 0xE0, 0x20,
++0xE6, 0x1D, 0x90, 0x98, 0x6C, 0xE0, 0x54, 0xFE,
++0xF0, 0x90, 0x06, 0x0F, 0xE0, 0x20, 0xE5, 0x07,
++0x90, 0x01, 0x0C, 0xE0, 0x30, 0xE1, 0x45, 0x90,
++0x01, 0xC7, 0x74, 0x44, 0xF0, 0x80, 0xFE, 0x90,
++0x98, 0x6C, 0xE0, 0x44, 0x01, 0xF0, 0x90, 0x06,
++0x0F, 0xE0, 0x30, 0xE5, 0x10, 0x90, 0x01, 0x0C,
++0xE0, 0x20, 0xE1, 0x09, 0x90, 0x98, 0x6C, 0xE0,
++0x54, 0xFD, 0xF0, 0x80, 0x1F, 0x90, 0x06, 0x0F,
++0xE0, 0x20, 0xE5, 0x10, 0x90, 0x01, 0x0C, 0xE0,
++0x30, 0xE1, 0x09, 0x90, 0x98, 0x6C, 0xE0, 0x44,
++0x02, 0xF0, 0x80, 0x08, 0x90, 0x01, 0xC7, 0x74,
++0x44, 0xF0, 0x80, 0xFE, 0x90, 0x98, 0x37, 0xE0,
++0xFF, 0x60, 0x03, 0x12, 0xD7, 0x0A, 0x90, 0x01,
++0xC7, 0xE4, 0x12, 0xC7, 0x89, 0xF1, 0xD3, 0x90,
++0x06, 0x09, 0xE0, 0x54, 0xFE, 0xF0, 0x7B, 0x35,
++0x7D, 0xFF, 0x7F, 0xFF, 0x12, 0x8D, 0x1E, 0x90,
++0x8A, 0xEF, 0x12, 0x88, 0xC8, 0xF1, 0xC5, 0xF0,
++0xD1, 0x11, 0xB1, 0x80, 0x90, 0x86, 0x0C, 0x12,
++0x88, 0xC8, 0xE4, 0xFB, 0xFD, 0x7F, 0xFF, 0x12,
++0x8D, 0x1E, 0xB1, 0xA1, 0x90, 0x01, 0x34, 0x74,
++0x08, 0xF0, 0xFD, 0xE4, 0xFF, 0x02, 0x7C, 0x74,
++0x7D, 0x08, 0xE4, 0xFF, 0x12, 0x7C, 0x7E, 0x90,
++0x06, 0x90, 0xE0, 0x54, 0xF0, 0xF0, 0xF1, 0xCC,
++0xF0, 0xB1, 0xD4, 0x12, 0x9F, 0xED, 0x21, 0x89,
++0x12, 0xBF, 0xF8, 0xF1, 0xDB, 0x30, 0xE0, 0x18,
++0x90, 0x93, 0x04, 0xE0, 0xFF, 0xC4, 0x54, 0x0F,
++0x20, 0xE0, 0x0D, 0x90, 0x9C, 0x9B, 0x12, 0x04,
++0x3D, 0x00, 0x00, 0x00, 0x14, 0x12, 0x95, 0x36,
++0x22, 0xE4, 0xFF, 0x74, 0x18, 0xB1, 0xC9, 0x74,
++0x38, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x93, 0xF5,
++0x83, 0xEE, 0xF0, 0x74, 0x10, 0xB1, 0xC9, 0x74,
++0x32, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x93, 0xF5,
++0x83, 0xEE, 0xF0, 0x0F, 0xEF, 0xB4, 0x06, 0xDB,
++0x22, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x06, 0xF5,
++0x83, 0xE0, 0xFE, 0x22, 0xB1, 0xFE, 0x90, 0x98,
++0x46, 0xE0, 0xFF, 0xD1, 0x5E, 0x90, 0x01, 0x3F,
++0x74, 0x04, 0xF0, 0x90, 0x86, 0xB3, 0xE0, 0xFF,
++0xB4, 0x01, 0x07, 0x90, 0xFD, 0x00, 0xE0, 0x54,
++0xEF, 0xF0, 0xEF, 0xB4, 0x01, 0x07, 0x90, 0xFE,
++0x10, 0xE0, 0x54, 0xFB, 0xF0, 0x22, 0xD3, 0x10,
++0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0xE4, 0xFD, 0x7F,
++0x8F, 0x12, 0x7B, 0x2E, 0xD0, 0xD0, 0x92, 0xAF,
++0x22, 0x12, 0xE6, 0xCD, 0xAD, 0x07, 0x90, 0x01,
++0xC4, 0x74, 0x11, 0xF0, 0x74, 0xCE, 0xA3, 0xF0,
++0xED, 0x64, 0x01, 0x60, 0x1E, 0x12, 0xA7, 0x6E,
++0xED, 0xB4, 0x02, 0x08, 0x90, 0x01, 0xC7, 0x74,
++0x40, 0xF0, 0x80, 0x0A, 0xED, 0xB4, 0x04, 0x06,
++0x90, 0x01, 0xC7, 0x74, 0x41, 0xF0, 0x7F, 0x01,
++0x02, 0xAD, 0x64, 0xD1, 0xC8, 0x90, 0x02, 0x87,
++0xE0, 0x70, 0xF8, 0x90, 0x06, 0x90, 0xE0, 0x44,
++0x02, 0xF0, 0x74, 0x11, 0x04, 0x90, 0x01, 0xC4,
++0xF0, 0x74, 0xCE, 0xA3, 0xF0, 0x22, 0x90, 0x99,
++0xB4, 0xEF, 0xF0, 0xE4, 0xFF, 0x74, 0x33, 0x2F,
++0xF1, 0xE3, 0xE0, 0xFE, 0x74, 0x84, 0x2F, 0xF5,
++0x82, 0xE4, 0x34, 0x04, 0xF5, 0x83, 0xEE, 0xF0,
++0x0F, 0xEF, 0xB4, 0x08, 0xE8, 0x90, 0x95, 0x63,
++0xE0, 0x90, 0x04, 0x8C, 0xF0, 0x90, 0x95, 0x65,
++0xE0, 0x90, 0x04, 0x8D, 0xF0, 0x90, 0x95, 0x66,
++0x74, 0x01, 0xF0, 0xF5, 0x45, 0x75, 0x46, 0x94,
++0x75, 0x47, 0x42, 0x75, 0x48, 0x08, 0xFB, 0x7A,
++0x95, 0x79, 0x3B, 0x12, 0x69, 0xF5, 0x90, 0x98,
++0x46, 0xE0, 0x60, 0x1B, 0x90, 0x99, 0xB4, 0x12,
++0xC7, 0xF0, 0x12, 0xEE, 0xA3, 0xC0, 0x03, 0x8B,
++0x45, 0x75, 0x46, 0x95, 0x75, 0x47, 0x33, 0x75,
++0x48, 0x60, 0xD0, 0x03, 0x12, 0x69, 0xF5, 0x22,
++0x12, 0xF6, 0xD4, 0x12, 0xC7, 0x92, 0x90, 0x99,
++0xB1, 0x12, 0xFB, 0xA1, 0xF9, 0x90, 0x93, 0x24,
++0xE0, 0x20, 0xE0, 0x02, 0xE1, 0x63, 0xEC, 0xC3,
++0x99, 0x40, 0x02, 0xE1, 0x63, 0x90, 0x99, 0xB1,
++0xE0, 0xFA, 0xA3, 0xE0, 0xFB, 0xEA, 0x90, 0xFD,
++0x11, 0xF0, 0xAF, 0x03, 0xAD, 0x07, 0x12, 0xF6,
++0xDD, 0x3E, 0x54, 0x3F, 0x90, 0x99, 0xB3, 0x12,
++0xFA, 0x80, 0x30, 0xE0, 0x0A, 0xC3, 0x13, 0x20,
++0xE0, 0x05, 0x12, 0xFA, 0xE7, 0x80, 0x02, 0x7E,
++0x00, 0xEE, 0xFB, 0xEF, 0x24, 0x18, 0xFF, 0xE4,
++0x33, 0xCF, 0x2B, 0xCF, 0x34, 0x00, 0x90, 0x99,
++0xB3, 0x8F, 0xF0, 0x12, 0x02, 0xE7, 0x90, 0x99,
++0xB3, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0xF1, 0x64,
++0x90, 0x99, 0xB3, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0,
++0x90, 0x99, 0xB1, 0x12, 0xFA, 0xD8, 0xD3, 0x90,
++0x99, 0xB2, 0xE0, 0x9F, 0x90, 0x99, 0xB1, 0xE0,
++0x9E, 0x40, 0x0F, 0x12, 0xFA, 0xB8, 0x90, 0x99,
++0xB2, 0xE0, 0x9F, 0xF0, 0x90, 0x99, 0xB1, 0xE0,
++0x9E, 0xF0, 0x90, 0x99, 0xB1, 0x12, 0xE6, 0xBA,
++0x0C, 0xC1, 0xDE, 0x22, 0x7D, 0x07, 0xEF, 0x5D,
++0xC3, 0x60, 0x0A, 0xF1, 0x79, 0x24, 0x08, 0xFF,
++0xE4, 0x3E, 0xFE, 0x80, 0x03, 0xF1, 0x79, 0xFF,
++0x22, 0x74, 0xFF, 0x9D, 0xFD, 0x74, 0xFF, 0x94,
++0x00, 0x5E, 0xFE, 0xED, 0x5F, 0x22, 0x75, 0x29,
++0x10, 0xE4, 0xF5, 0x2A, 0x75, 0x2B, 0x07, 0x75,
++0x2C, 0x02, 0xF5, 0x31, 0xF5, 0x32, 0xF5, 0x33,
++0xF5, 0x34, 0x90, 0x01, 0x30, 0xE5, 0x29, 0xF0,
++0xA3, 0xE5, 0x2A, 0xF0, 0xA3, 0xE5, 0x2B, 0xF0,
++0xA3, 0xE5, 0x2C, 0xF0, 0x90, 0x01, 0x20, 0xE5,
++0x31, 0xF0, 0xA3, 0xE5, 0x32, 0xF0, 0xA3, 0xE5,
++0x33, 0xF0, 0xA3, 0xE5, 0x34, 0xF0, 0x22, 0xE4,
++0xFD, 0xFF, 0x02, 0x6E, 0x71, 0x90, 0x02, 0x86,
++0xE0, 0x44, 0x04, 0x22, 0x90, 0x02, 0x86, 0xE0,
++0x54, 0xFB, 0x22, 0x90, 0x88, 0x27, 0xF0, 0xA3,
++0xEF, 0xF0, 0x22, 0x90, 0x93, 0x24, 0xE0, 0xC4,
++0x54, 0x0F, 0x22, 0xF5, 0x82, 0xE4, 0x34, 0x95,
++0xF5, 0x83, 0x22, 0x75, 0x39, 0x0F, 0x75, 0x3A,
++0x01, 0x75, 0x3B, 0x03, 0x75, 0x3C, 0x62, 0x90,
++0x01, 0x38, 0xE5, 0x39, 0xF0, 0xA3, 0xE5, 0x3A,
++0xF0, 0xA3, 0xE5, 0x3B, 0xF0, 0xA3, 0xE5, 0x3C,
++0xF0, 0x22, 0x90, 0x01, 0xE4, 0x74, 0x31, 0xF0,
++0xA3, 0xE4, 0xF0, 0x22, 0x7D, 0x02, 0x90, 0x01,
++0xC4, 0x74, 0x14, 0xF0, 0x74, 0xD0, 0xA3, 0xF0,
++0x90, 0x98, 0x4B, 0xE0, 0xFF, 0xED, 0xC3, 0x9F,
++0x50, 0x18, 0xED, 0x25, 0xE0, 0x24, 0x81, 0xF8,
++0xE6, 0x30, 0xE4, 0x0B, 0x90, 0x01, 0xB8, 0x74,
++0x08, 0xF0, 0xA3, 0xF0, 0x7F, 0x00, 0x22, 0x0D,
++0x80, 0xDE, 0x74, 0x14, 0x04, 0x90, 0x01, 0xC4,
++0xF0, 0x74, 0xD0, 0xA3, 0xF0, 0x7F, 0x01, 0x22,
++0xE4, 0x90, 0x9A, 0x09, 0xF0, 0xA3, 0xF0, 0xA3,
++0xF0, 0x90, 0x9A, 0x09, 0xE0, 0x64, 0x01, 0xF0,
++0x90, 0x98, 0x62, 0xE0, 0x70, 0x18, 0x90, 0x98,
++0x5F, 0xE0, 0x70, 0x12, 0xA3, 0xE0, 0x70, 0x0E,
++0x90, 0x9A, 0x09, 0xE0, 0x24, 0x50, 0x90, 0x01,
++0xC4, 0xF0, 0x74, 0xD0, 0xA3, 0xF0, 0x12, 0x7C,
++0x54, 0xBF, 0x01, 0x03, 0x12, 0x54, 0x9F, 0x90,
++0x88, 0x36, 0xE0, 0x60, 0x0F, 0x90, 0x88, 0x39,
++0xE0, 0xFF, 0x90, 0x88, 0x38, 0xE0, 0x6F, 0x60,
++0x03, 0x12, 0xB6, 0x3C, 0xC2, 0xAF, 0x11, 0x14,
++0xBF, 0x01, 0x03, 0x12, 0xF9, 0x2F, 0xD2, 0xAF,
++0x11, 0xB2, 0x12, 0xC7, 0xF8, 0x12, 0x84, 0x4D,
++0x80, 0xA7, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0,
++0xD0, 0x90, 0x98, 0x5F, 0xE0, 0x60, 0x24, 0x7F,
++0x54, 0x7E, 0x09, 0x12, 0x70, 0x70, 0x31, 0x5E,
++0x12, 0x04, 0xB8, 0xEF, 0x44, 0xFE, 0xFF, 0xEE,
++0x44, 0x03, 0xFE, 0xED, 0x44, 0x04, 0xFD, 0xEC,
++0x31, 0x5E, 0x31, 0x68, 0x7F, 0x54, 0x7E, 0x09,
++0x12, 0x70, 0xAD, 0x90, 0x98, 0x5A, 0xE0, 0x70,
++0x29, 0x90, 0x07, 0xCC, 0xE0, 0x30, 0xE0, 0x22,
++0xE4, 0xF0, 0x90, 0x9A, 0x10, 0x74, 0x22, 0xF0,
++0x90, 0x9A, 0x32, 0x74, 0x01, 0xF0, 0x90, 0x9A,
++0x12, 0x74, 0x03, 0xF0, 0x7B, 0x01, 0x7A, 0x9A,
++0x79, 0x10, 0x12, 0x90, 0x35, 0x7F, 0x04, 0x12,
++0x04, 0x7E, 0x90, 0x98, 0x62, 0xE0, 0xFF, 0x70,
++0x0A, 0x90, 0x98, 0x5F, 0xE0, 0x70, 0x04, 0xA3,
++0xE0, 0x60, 0x15, 0x90, 0x00, 0x1F, 0xE0, 0x54,
++0xF0, 0xF0, 0x90, 0x01, 0xC5, 0x74, 0xEA, 0xF0,
++0xA3, 0x74, 0xEF, 0xF0, 0xA3, 0x74, 0xFD, 0xF0,
++0xEF, 0x60, 0x06, 0x90, 0x01, 0xC4, 0x74, 0x07,
++0xF0, 0x90, 0x98, 0x5F, 0xE0, 0x60, 0x06, 0x90,
++0x01, 0xC4, 0x74, 0x01, 0xF0, 0x90, 0x98, 0x60,
++0xE0, 0x60, 0x06, 0x90, 0x01, 0xC4, 0x74, 0x02,
++0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x9A,
++0x0C, 0x12, 0x04, 0x31, 0x90, 0x9A, 0x0C, 0x22,
++0x12, 0x04, 0xB8, 0x90, 0x92, 0x18, 0x02, 0x04,
++0x31, 0x7F, 0x58, 0x7E, 0x0C, 0xD3, 0x10, 0xAF,
++0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x9C, 0x2D, 0xEE,
++0xF0, 0xA3, 0xEF, 0xF0, 0x12, 0x70, 0x70, 0x90,
++0x9C, 0x37, 0x12, 0x04, 0x31, 0x90, 0x9C, 0x2F,
++0x12, 0x04, 0xB8, 0x12, 0x03, 0xCD, 0x90, 0x9C,
++0x37, 0x91, 0x19, 0xC0, 0x04, 0xC0, 0x05, 0xC0,
++0x06, 0xC0, 0x07, 0x90, 0x9C, 0x2F, 0x12, 0x04,
++0xB8, 0x90, 0x9C, 0x33, 0x91, 0x19, 0xD0, 0x03,
++0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x82,
++0x05, 0x90, 0x9C, 0x3B, 0x12, 0x04, 0x31, 0x90,
++0x9C, 0x3B, 0x31, 0x68, 0x90, 0x9C, 0x2D, 0xE0,
++0xFE, 0xA3, 0xE0, 0xFF, 0x12, 0x70, 0xAD, 0xD0,
++0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01,
++0xC3, 0xC0, 0xD0, 0x90, 0x9C, 0xDB, 0xED, 0xF0,
++0xE4, 0xA3, 0xF0, 0xEF, 0x14, 0x60, 0x02, 0x41,
++0xBB, 0x90, 0x06, 0x03, 0xE0, 0x54, 0xFB, 0xF0,
++0x90, 0x9C, 0xDB, 0xE0, 0xFB, 0xC4, 0x33, 0x54,
++0xE0, 0xFE, 0x90, 0x04, 0x42, 0xE0, 0x54, 0x9F,
++0x4E, 0xFE, 0xF0, 0xE4, 0xFD, 0x12, 0xE3, 0x18,
++0x90, 0x9C, 0xDC, 0xEF, 0xF0, 0x90, 0x04, 0x83,
++0xF0, 0x90, 0x9C, 0x2F, 0x12, 0x04, 0x3D, 0x00,
++0x00, 0x00, 0x01, 0x90, 0x9C, 0x33, 0x12, 0x04,
++0x3D, 0x00, 0x00, 0x00, 0x01, 0x71, 0x20, 0x12,
++0x04, 0x3D, 0x00, 0x00, 0x00, 0x01, 0x90, 0x9C,
++0x33, 0x12, 0x04, 0x3D, 0x00, 0x00, 0x00, 0x01,
++0x7F, 0x00, 0x7E, 0x09, 0x71, 0x24, 0x12, 0x04,
++0x3D, 0x00, 0x00, 0x00, 0x10, 0x90, 0x9C, 0xDB,
++0x12, 0xAF, 0x1B, 0xEF, 0x54, 0x03, 0xFF, 0xE4,
++0x78, 0x01, 0x12, 0x03, 0xEB, 0x78, 0x04, 0x91,
++0x06, 0x7F, 0x00, 0x7E, 0x0A, 0x71, 0x24, 0x12,
++0x04, 0x3D, 0x00, 0x00, 0x0C, 0x00, 0x90, 0x9C,
++0xDB, 0x12, 0xAF, 0x1B, 0xEF, 0x54, 0x03, 0xFF,
++0xE4, 0x78, 0x0A, 0x91, 0x06, 0x7F, 0x00, 0x7E,
++0x0D, 0x71, 0x24, 0x12, 0x04, 0x3D, 0x0C, 0x00,
++0x00, 0x00, 0x90, 0x9C, 0xDC, 0x12, 0xAF, 0x1B,
++0xEF, 0x54, 0x03, 0xFF, 0xE4, 0x78, 0x1A, 0x91,
++0x06, 0x7F, 0x18, 0x71, 0x22, 0x12, 0x04, 0x3D,
++0x00, 0x00, 0x0C, 0x00, 0x90, 0x9C, 0x33, 0x12,
++0x04, 0x3D, 0x00, 0x00, 0x00, 0x00, 0x91, 0x0F,
++0x12, 0x04, 0x3D, 0x00, 0x00, 0x0C, 0x00, 0x90,
++0x9C, 0x21, 0x12, 0x04, 0x3D, 0x00, 0x00, 0x04,
++0x00, 0x80, 0x58, 0x90, 0x06, 0x03, 0xE0, 0x44,
++0x04, 0xF0, 0x90, 0x9C, 0x2F, 0x12, 0x04, 0x3D,
++0x00, 0x00, 0x00, 0x01, 0x90, 0x9C, 0x33, 0x12,
++0x04, 0x3D, 0x00, 0x00, 0x00, 0x00, 0x71, 0x20,
++0x12, 0x04, 0x3D, 0x00, 0x00, 0x00, 0x01, 0x90,
++0x9C, 0x33, 0x12, 0x04, 0x3D, 0x00, 0x00, 0x00,
++0x00, 0x7F, 0x00, 0x7E, 0x09, 0x71, 0x24, 0x12,
++0x04, 0x3D, 0x00, 0x00, 0x0C, 0x00, 0x90, 0x9C,
++0x33, 0x12, 0x04, 0x3D, 0x00, 0x00, 0x0C, 0x00,
++0x91, 0x0F, 0x12, 0x04, 0x3D, 0x00, 0x00, 0x0C,
++0x00, 0x90, 0x9C, 0x21, 0x12, 0x04, 0x3D, 0x00,
++0x00, 0x0C, 0x00, 0x7D, 0x18, 0x7C, 0x00, 0xE4,
++0xFF, 0x91, 0x1F, 0xD0, 0xD0, 0x92, 0xAF, 0x22,
++0x7F, 0x00, 0x7E, 0x08, 0x31, 0x75, 0x90, 0x9C,
++0x2F, 0x22, 0x7F, 0x50, 0x7E, 0x0C, 0x12, 0x70,
++0x70, 0x90, 0x9B, 0x0B, 0xEF, 0xF0, 0x7F, 0x58,
++0x7E, 0x0C, 0x12, 0x70, 0x70, 0x90, 0x9B, 0x0C,
++0xEF, 0xF0, 0x90, 0x9C, 0x2F, 0x12, 0x04, 0x3D,
++0x00, 0x00, 0x00, 0x7F, 0x90, 0x9C, 0x33, 0x12,
++0x04, 0x3D, 0x00, 0x00, 0x00, 0x17, 0x7F, 0x50,
++0x7E, 0x0C, 0x71, 0x24, 0x12, 0x04, 0x3D, 0x00,
++0x00, 0x00, 0x7F, 0x90, 0x9C, 0x33, 0x12, 0x04,
++0x3D, 0x00, 0x00, 0x00, 0x17, 0x31, 0x71, 0x90,
++0x06, 0x08, 0xE0, 0x90, 0x9B, 0x21, 0xF0, 0x90,
++0x06, 0xA1, 0xE0, 0xFE, 0x90, 0x06, 0xA0, 0x12,
++0xC7, 0x92, 0x90, 0x9B, 0x23, 0xF0, 0xA3, 0xEF,
++0xB1, 0x1F, 0x90, 0x06, 0xA0, 0x74, 0x20, 0xF0,
++0xA3, 0x74, 0x01, 0xF0, 0xE4, 0xFD, 0xFF, 0x21,
++0xD4, 0x90, 0x93, 0x04, 0x12, 0xB4, 0xA4, 0x30,
++0xE0, 0x09, 0x12, 0xCF, 0xCC, 0xF0, 0xE4, 0x90,
++0x9B, 0x25, 0xF0, 0x90, 0x9C, 0x2F, 0x12, 0x04,
++0x3D, 0x00, 0x00, 0x00, 0x7F, 0x90, 0x9B, 0x0B,
++0x12, 0xAF, 0x1B, 0x91, 0x09, 0x7F, 0x50, 0x7E,
++0x0C, 0x71, 0x24, 0x12, 0x04, 0x3D, 0x00, 0x00,
++0x00, 0x7F, 0x90, 0x9B, 0x0C, 0x12, 0xAF, 0x1B,
++0x91, 0x09, 0x31, 0x71, 0x90, 0x9B, 0x21, 0xE0,
++0x90, 0x06, 0x08, 0xF0, 0x90, 0x9B, 0x23, 0xA3,
++0xE0, 0x90, 0x06, 0xA0, 0xF0, 0xA3, 0xE4, 0xF0,
++0x90, 0x9B, 0x0F, 0xE0, 0xFF, 0x60, 0x05, 0xA3,
++0xE0, 0xFD, 0x31, 0xD4, 0x90, 0x9B, 0x0E, 0xE0,
++0xFF, 0x60, 0x0A, 0xA3, 0xE0, 0xFD, 0xA3, 0xE0,
++0xFB, 0xB1, 0x16, 0x91, 0x95, 0x22, 0x12, 0x03,
++0xFE, 0x90, 0x9C, 0x33, 0x02, 0x04, 0x31, 0x7F,
++0x84, 0x7E, 0x08, 0x31, 0x75, 0x90, 0x9C, 0x1D,
++0x22, 0x12, 0x82, 0x12, 0x02, 0x81, 0xF8, 0xD3,
++0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x9C,
++0x1B, 0xEC, 0xF0, 0xA3, 0xED, 0xF0, 0x90, 0x9C,
++0x1A, 0xEF, 0xF0, 0xA3, 0xA3, 0xE0, 0xFD, 0x12,
++0x7B, 0xBD, 0x90, 0x9C, 0x25, 0x12, 0x04, 0x31,
++0x90, 0x9C, 0x1D, 0x12, 0x04, 0xB8, 0x12, 0x03,
++0xCD, 0x90, 0x9C, 0x25, 0x91, 0x19, 0xC0, 0x04,
++0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x9C,
++0x1D, 0x12, 0x04, 0xB8, 0x90, 0x9C, 0x21, 0x91,
++0x19, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0,
++0x00, 0x12, 0x82, 0x05, 0x90, 0x9C, 0x29, 0x12,
++0x04, 0x31, 0x90, 0x9C, 0x1B, 0xA3, 0xE0, 0xFD,
++0xC0, 0x05, 0x90, 0x9C, 0x29, 0x12, 0x04, 0xB8,
++0x90, 0x8B, 0x9F, 0x12, 0x04, 0x31, 0x90, 0x9C,
++0x1A, 0xE0, 0xFF, 0xD0, 0x05, 0x12, 0x79, 0x53,
++0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF,
++0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x9C, 0xBB, 0xEF,
++0xF0, 0xED, 0x64, 0x01, 0x70, 0x2E, 0xEB, 0xB4,
++0x01, 0x07, 0xE0, 0x24, 0x02, 0xF5, 0x13, 0x80,
++0x08, 0x90, 0x9C, 0xBB, 0xE0, 0x24, 0xFE, 0xF5,
++0x13, 0x90, 0x9C, 0x1D, 0x12, 0x04, 0x3D, 0x00,
++0x00, 0x00, 0xFF, 0xAF, 0x13, 0xB1, 0x07, 0x91,
++0xFF, 0x12, 0x04, 0x3D, 0x00, 0x00, 0x00, 0xFF,
++0xAF, 0x13, 0x80, 0x20, 0x90, 0x9C, 0x1D, 0x12,
++0x04, 0x3D, 0x00, 0x00, 0x00, 0xFF, 0x90, 0x9C,
++0xBB, 0x12, 0xAF, 0x1B, 0xB1, 0x0B, 0x91, 0xFF,
++0x12, 0x04, 0x3D, 0x00, 0x00, 0x00, 0xFF, 0x90,
++0x9C, 0xBB, 0xE0, 0xFF, 0xB1, 0x07, 0x7F, 0x01,
++0x91, 0x1F, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xE4,
++0xFF, 0x91, 0x1F, 0x90, 0x9C, 0x1D, 0x22, 0xE4,
++0xFC, 0xFD, 0xFE, 0x90, 0x9C, 0x21, 0x12, 0x04,
++0x31, 0x7D, 0x18, 0x7C, 0x00, 0x22, 0x90, 0x9B,
++0x15, 0xE0, 0x90, 0x9C, 0xBE, 0xF0, 0x22, 0xF0,
++0x90, 0x06, 0x08, 0xE0, 0x54, 0x7F, 0xF0, 0x22,
++0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90,
++0x02, 0x09, 0xE0, 0xFD, 0x12, 0x02, 0x06, 0xFF,
++0x54, 0x01, 0xFE, 0x90, 0x93, 0x04, 0x12, 0xDE,
++0xC9, 0xFC, 0xEF, 0x54, 0xFB, 0x4C, 0xFF, 0x90,
++0x93, 0x04, 0x12, 0x9F, 0xDF, 0x54, 0x10, 0xFE,
++0xEF, 0x54, 0xEF, 0x4E, 0x90, 0x93, 0x04, 0xF0,
++0x12, 0x9C, 0x58, 0xFF, 0xED, 0x2F, 0x90, 0x93,
++0x05, 0x12, 0x87, 0xE6, 0xFF, 0xED, 0x2F, 0x90,
++0x93, 0x06, 0x12, 0x87, 0xA3, 0xFF, 0xAE, 0x05,
++0xED, 0x2F, 0x90, 0x93, 0x07, 0xF0, 0x90, 0x93,
++0x04, 0xE0, 0xFF, 0x20, 0xE0, 0x08, 0x13, 0x13,
++0x13, 0x54, 0x1F, 0x30, 0xE0, 0x09, 0x90, 0x06,
++0x31, 0xE0, 0x44, 0x40, 0xF0, 0xB1, 0xED, 0x90,
++0x93, 0x04, 0xE0, 0xFF, 0x30, 0xE0, 0x3A, 0x90,
++0x06, 0x32, 0xE0, 0x44, 0x01, 0xF0, 0x90, 0x06,
++0x09, 0xE0, 0x54, 0xFE, 0xB1, 0x1F, 0xEF, 0x13,
++0x13, 0x54, 0x3F, 0x30, 0xE0, 0x0A, 0x12, 0xCF,
++0xC5, 0xF0, 0x90, 0x9B, 0x25, 0x74, 0x01, 0xF0,
++0x7D, 0x08, 0xE4, 0xFF, 0x12, 0x7C, 0x74, 0xB1,
++0xE5, 0x20, 0xE0, 0x0D, 0x90, 0x9C, 0x9B, 0x12,
++0x04, 0x3D, 0x00, 0x00, 0x27, 0x10, 0x12, 0x95,
++0x36, 0xB1, 0xE5, 0x30, 0xE0, 0x0A, 0x90, 0x06,
++0x32, 0xE0, 0x44, 0x02, 0xF0, 0x12, 0x8E, 0xEA,
++0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x93, 0x04,
++0xE0, 0xFF, 0xC3, 0x13, 0x22, 0x90, 0x93, 0x06,
++0xF1, 0xE4, 0x12, 0x8E, 0x9B, 0xE0, 0x90, 0x9B,
++0x0D, 0xF0, 0x74, 0x01, 0x2F, 0x12, 0xC3, 0xF5,
++0xE0, 0x90, 0x9B, 0x0E, 0xD1, 0xE7, 0x90, 0x9B,
++0x0F, 0xF0, 0x74, 0x03, 0x2F, 0xD1, 0x40, 0xE0,
++0x90, 0x9B, 0x10, 0xD1, 0xF4, 0x90, 0x9B, 0x11,
++0xF0, 0x74, 0x05, 0x2F, 0x12, 0xC7, 0xAF, 0xE0,
++0x90, 0x9B, 0x12, 0xF0, 0x74, 0x06, 0x2F, 0xD1,
++0xD5, 0x90, 0x9B, 0x13, 0xF0, 0x74, 0x07, 0x2F,
++0xD1, 0xDE, 0x90, 0x9B, 0x14, 0xF0, 0x74, 0x08,
++0x2F, 0xD1, 0xCC, 0x90, 0x9B, 0x15, 0xF0, 0x22,
++0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0x22,
++0xE4, 0xFD, 0xFC, 0x90, 0x98, 0x41, 0x12, 0xEE,
++0xBC, 0xAB, 0x05, 0x74, 0x01, 0x2B, 0x12, 0xC3,
++0xF5, 0xE0, 0xFE, 0x74, 0x00, 0x2B, 0x12, 0x8E,
++0x9B, 0x12, 0xF6, 0xF3, 0x3E, 0x90, 0x95, 0x93,
++0xF0, 0xA3, 0xEF, 0xF0, 0x74, 0x03, 0x2B, 0xD1,
++0x40, 0xE0, 0xFE, 0x74, 0x02, 0x2B, 0xD1, 0xEB,
++0x24, 0x00, 0xFF, 0xEA, 0x3E, 0x90, 0x95, 0x95,
++0xF0, 0xA3, 0xEF, 0xF0, 0x74, 0x05, 0x2B, 0x12,
++0xC7, 0xAF, 0xE0, 0xFE, 0x74, 0x04, 0x2B, 0xD1,
++0xF8, 0x24, 0x00, 0xFF, 0xEA, 0x3E, 0x90, 0x95,
++0x97, 0xF0, 0xA3, 0xEF, 0xF0, 0x74, 0x07, 0x2B,
++0xD1, 0xDE, 0xFE, 0x74, 0x06, 0x2B, 0xD1, 0xD5,
++0x24, 0x00, 0xFF, 0xEA, 0x3E, 0x90, 0x95, 0x99,
++0xF0, 0xA3, 0xEF, 0xF0, 0x74, 0x09, 0x2B, 0xF1,
++0x01, 0xFE, 0x74, 0x08, 0x2B, 0xD1, 0xCC, 0x24,
++0x00, 0xFF, 0xEC, 0x3E, 0x90, 0x95, 0x9B, 0xF0,
++0xA3, 0xEF, 0xF0, 0x22, 0xF5, 0x82, 0xE4, 0x34,
++0xFC, 0xF5, 0x83, 0xE0, 0x22, 0xF5, 0x82, 0xE4,
++0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x22, 0xF5, 0x82,
++0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x22, 0xF0,
++0x74, 0x02, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC,
++0xF5, 0x83, 0xE0, 0x22, 0xF0, 0x74, 0x04, 0x2F,
++0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0,
++0x22, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83,
++0xE0, 0x22, 0x12, 0x7B, 0x07, 0x7E, 0x00, 0xE4,
++0xFD, 0xEF, 0x2D, 0x12, 0x8E, 0x99, 0xE0, 0xFC,
++0x74, 0x33, 0x2D, 0x12, 0xCF, 0xE3, 0xEC, 0xF0,
++0x0D, 0xED, 0xB4, 0x08, 0xEC, 0xAC, 0x07, 0x74,
++0x08, 0x2C, 0xD1, 0xCC, 0x64, 0xDD, 0x60, 0x02,
++0xE1, 0xD3, 0x74, 0x09, 0x2C, 0xF1, 0x01, 0xFC,
++0x30, 0xE0, 0x1B, 0xE4, 0xFD, 0xEF, 0x2D, 0x24,
++0x10, 0xF1, 0xDC, 0xE0, 0xFB, 0x74, 0x6B, 0x2D,
++0xF5, 0x82, 0xE4, 0x34, 0x95, 0xF5, 0x83, 0xEB,
++0xF0, 0x0D, 0xED, 0xB4, 0x08, 0xE7, 0xEC, 0x30,
++0xE1, 0x79, 0x74, 0x0A, 0x2F, 0xF5, 0x82, 0xE4,
++0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x90, 0x95, 0x63,
++0xF0, 0xE4, 0xFD, 0xA9, 0x07, 0xE9, 0x2D, 0xFC,
++0x24, 0x18, 0xF1, 0xD4, 0xE0, 0xFB, 0x74, 0x73,
++0x2D, 0xF5, 0x82, 0xE4, 0x34, 0x95, 0xF5, 0x83,
++0xEB, 0xF0, 0x74, 0x20, 0x2C, 0x12, 0xFB, 0xB3,
++0xFC, 0x74, 0x7B, 0x2D, 0xF5, 0x82, 0xE4, 0x34,
++0x95, 0xF5, 0x83, 0xEC, 0xF0, 0xE9, 0x2D, 0xFC,
++0x12, 0xFB, 0x27, 0xFB, 0x74, 0x83, 0x2D, 0xF5,
++0x82, 0xE4, 0x34, 0x95, 0xF5, 0x83, 0xEB, 0xF0,
++0x74, 0x30, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC,
++0xF5, 0x83, 0xE0, 0xFC, 0x74, 0x8B, 0x2D, 0xF5,
++0x82, 0xE4, 0x34, 0x95, 0xF5, 0x83, 0xEC, 0xF0,
++0x0D, 0xED, 0xB4, 0x08, 0xA6, 0x90, 0x95, 0x63,
++0xE0, 0xFF, 0x7B, 0x01, 0x7A, 0x95, 0x79, 0x43,
++0x12, 0xF5, 0x52, 0x22, 0xF5, 0x82, 0xE4, 0x34,
++0xFC, 0xF5, 0x83, 0x22, 0xF5, 0x82, 0xE4, 0x34,
++0xFC, 0xF5, 0x83, 0x22, 0xE0, 0xFF, 0x12, 0x7B,
++0x07, 0x74, 0x00, 0x2F, 0x22, 0x90, 0x8A, 0x79,
++0x74, 0x87, 0xF0, 0xA3, 0x74, 0x4A, 0xF0, 0x90,
++0x8A, 0xE5, 0x74, 0xD9, 0xF0, 0xA3, 0x74, 0xAF,
++0xF0, 0x90, 0x8B, 0x03, 0x74, 0x98, 0xF0, 0xA3,
++0x74, 0x19, 0xF0, 0x90, 0x8A, 0xB9, 0x74, 0x88,
++0xF0, 0xA3, 0x74, 0xD2, 0xF0, 0x90, 0x8A, 0x75,
++0x74, 0xBB, 0xF0, 0xA3, 0x74, 0x09, 0xF0, 0x90,
++0x8A, 0xC3, 0x74, 0xE3, 0xF0, 0xA3, 0x74, 0xA4,
++0xF0, 0x90, 0x8A, 0xF3, 0x74, 0xE3, 0xF0, 0xA3,
++0x74, 0xE4, 0xF0, 0x90, 0x8A, 0x85, 0x74, 0xE3,
++0xF0, 0xA3, 0x74, 0xF0, 0xF0, 0x90, 0x86, 0x0C,
++0x74, 0xE0, 0xF0, 0xA3, 0x74, 0x6B, 0xF0, 0x90,
++0x8A, 0xEF, 0x74, 0xE0, 0xF0, 0xA3, 0x74, 0xD3,
++0xF0, 0x90, 0x86, 0x00, 0x74, 0xF7, 0xF0, 0xA3,
++0x74, 0xE6, 0xF0, 0x90, 0x86, 0x02, 0x74, 0xF8,
++0xF0, 0xA3, 0x74, 0x32, 0xF0, 0x90, 0x8A, 0xFD,
++0x74, 0xE1, 0xF0, 0xA3, 0x74, 0x4B, 0xF0, 0x90,
++0x8A, 0xF9, 0x74, 0xC0, 0xF0, 0xA3, 0x74, 0x5F,
++0xF0, 0x90, 0x8A, 0xAF, 0x74, 0x8F, 0xF0, 0xA3,
++0x74, 0x73, 0xF0, 0x90, 0x8A, 0xD3, 0x74, 0xC6,
++0xF0, 0xA3, 0x74, 0xAC, 0xF0, 0x90, 0x8A, 0xF5,
++0x74, 0xF9, 0xF0, 0xA3, 0x74, 0x50, 0xF0, 0x90,
++0x8A, 0xA3, 0x74, 0xB5, 0xF0, 0xA3, 0x74, 0x4E,
++0xF0, 0x90, 0x86, 0x06, 0x74, 0xDF, 0xF0, 0xA3,
++0x74, 0x73, 0xF0, 0x22, 0xE4, 0xFB, 0xFA, 0xFD,
++0x7F, 0x01, 0x12, 0x86, 0x4E, 0x90, 0x9A, 0x33,
++0xEF, 0xF0, 0x60, 0xF0, 0x90, 0x86, 0xAF, 0xE0,
++0xFF, 0x70, 0x04, 0xA3, 0xE0, 0x60, 0xE5, 0xC2,
++0xAF, 0xEF, 0x30, 0xE1, 0x0D, 0x90, 0x86, 0xAF,
++0xE0, 0x54, 0xFD, 0xF0, 0x90, 0x86, 0x08, 0x12,
++0x88, 0xC8, 0x31, 0x1A, 0x30, 0xE2, 0x09, 0x54,
++0xFB, 0xF0, 0x90, 0x86, 0x0A, 0x12, 0x88, 0xC8,
++0x31, 0x1A, 0xFF, 0x30, 0xE4, 0x0B, 0x54, 0xEF,
++0xF0, 0x31, 0x7A, 0xBF, 0x01, 0x03, 0x12, 0xA8,
++0xB5, 0x31, 0x1A, 0xFF, 0x30, 0xE7, 0x06, 0x54,
++0x7F, 0xF0, 0x12, 0x95, 0xB1, 0xD2, 0xAF, 0xC2,
++0xAF, 0x90, 0x86, 0xB0, 0xE0, 0xFF, 0x30, 0xE2,
++0x05, 0x54, 0xFB, 0xF0, 0x31, 0x23, 0xD2, 0xAF,
++0x80, 0xA2, 0xD2, 0xAF, 0xC2, 0xAF, 0x90, 0x86,
++0xAF, 0xE0, 0x22, 0x12, 0xBF, 0x99, 0x30, 0xE0,
++0x40, 0x12, 0xBF, 0xBA, 0x60, 0x10, 0x31, 0x6A,
++0x12, 0xBF, 0x8B, 0xE4, 0x90, 0x92, 0x20, 0xF0,
++0xA3, 0x04, 0xF0, 0xE4, 0x80, 0x22, 0x90, 0x93,
++0x2D, 0x12, 0x97, 0xD9, 0x30, 0xE0, 0x0B, 0xA3,
++0xE0, 0x90, 0x92, 0x20, 0xF0, 0xE4, 0xA3, 0xF0,
++0x80, 0x0E, 0xE4, 0x90, 0x92, 0x20, 0xF0, 0x90,
++0x93, 0x2E, 0xE0, 0x90, 0x92, 0x21, 0xF0, 0xE4,
++0xFB, 0xFD, 0x7F, 0x5C, 0x7E, 0x01, 0x12, 0x66,
++0x33, 0x22, 0x90, 0x00, 0xCC, 0xE0, 0x44, 0x04,
++0xF0, 0x7F, 0x02, 0x12, 0x7B, 0x41, 0xEF, 0x44,
++0x04, 0x22, 0xE4, 0x90, 0x9C, 0xDD, 0xF0, 0xA3,
++0xF0, 0x90, 0x02, 0x86, 0xE0, 0x20, 0xE1, 0x24,
++0xC3, 0x90, 0x9C, 0xDE, 0xE0, 0x94, 0xD0, 0x90,
++0x9C, 0xDD, 0xE0, 0x94, 0x07, 0x40, 0x0A, 0x90,
++0x01, 0xC1, 0xE0, 0x44, 0x04, 0xF0, 0x7F, 0x00,
++0x22, 0x90, 0x9C, 0xDD, 0x12, 0xBF, 0xF1, 0x12,
++0xBE, 0xF7, 0x80, 0xD5, 0x7F, 0x01, 0x22, 0x8F,
++0x12, 0x7F, 0x02, 0x12, 0x86, 0x27, 0x90, 0x86,
++0xAF, 0xE0, 0x45, 0x12, 0xF0, 0x22, 0x8F, 0x0E,
++0x7F, 0x02, 0x12, 0x86, 0x27, 0x90, 0x86, 0xB0,
++0xE0, 0x45, 0x0E, 0xF0, 0x22, 0x7F, 0x04, 0x80,
++0xED, 0xC0, 0xE0, 0xC0, 0xF0, 0xC0, 0x83, 0xC0,
++0x82, 0xC0, 0xD0, 0x75, 0xD0, 0x00, 0xC0, 0x00,
++0xC0, 0x01, 0xC0, 0x02, 0xC0, 0x03, 0xC0, 0x04,
++0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x01,
++0xC4, 0x74, 0xD1, 0xF0, 0x74, 0xD9, 0xA3, 0xF0,
++0x12, 0x6C, 0xD6, 0xE5, 0x27, 0x30, 0xE4, 0x02,
++0x31, 0xCD, 0x90, 0x86, 0xB3, 0xE0, 0xFC, 0x64,
++0x03, 0x70, 0x37, 0x90, 0x99, 0xB0, 0xE0, 0xFE,
++0x20, 0xE0, 0x2F, 0xE5, 0x26, 0x30, 0xE3, 0x2A,
++0x90, 0x00, 0xCC, 0xE0, 0x44, 0x04, 0xF0, 0x90,
++0x00, 0xD4, 0xE0, 0x44, 0x10, 0xF0, 0x90, 0x00,
++0xC6, 0xE0, 0x44, 0x02, 0xF0, 0x90, 0x00, 0x01,
++0xE0, 0x54, 0xCF, 0xF0, 0x90, 0x00, 0x23, 0xE0,
++0x54, 0x7F, 0xF0, 0xEE, 0x44, 0x01, 0x90, 0x99,
++0xB0, 0xF0, 0xEC, 0xB4, 0x01, 0x0B, 0xE5, 0x26,
++0x30, 0xE2, 0x06, 0x90, 0x88, 0x41, 0x74, 0xDD,
++0xF0, 0x74, 0xD1, 0x04, 0x90, 0x01, 0xC4, 0xF0,
++0x74, 0xD9, 0xA3, 0xF0, 0xD0, 0x07, 0xD0, 0x06,
++0xD0, 0x05, 0xD0, 0x04, 0xD0, 0x03, 0xD0, 0x02,
++0xD0, 0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0, 0x82,
++0xD0, 0x83, 0xD0, 0xF0, 0xD0, 0xE0, 0x32, 0xC0,
++0xE0, 0xC0, 0xF0, 0xC0, 0x83, 0xC0, 0x82, 0xC0,
++0xD0, 0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0, 0x01,
++0xC0, 0x02, 0xC0, 0x03, 0xC0, 0x04, 0xC0, 0x05,
++0xC0, 0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4, 0x74,
++0x77, 0xF0, 0x74, 0xDA, 0xA3, 0xF0, 0x12, 0x75,
++0x50, 0xE5, 0x3D, 0x30, 0xE0, 0x02, 0xD1, 0x9C,
++0xE5, 0x3D, 0x30, 0xE1, 0x03, 0x12, 0xB7, 0xC2,
++0xE5, 0x3D, 0x30, 0xE2, 0x02, 0x71, 0x13, 0xE5,
++0x3D, 0x30, 0xE3, 0x03, 0x12, 0xBE, 0xFE, 0xE5,
++0x3E, 0x30, 0xE0, 0x03, 0x12, 0x94, 0xA4, 0xE5,
++0x40, 0x30, 0xE1, 0x0B, 0x90, 0x8A, 0xE5, 0x12,
++0x90, 0x47, 0x7F, 0x04, 0x12, 0x04, 0x7E, 0xE5,
++0x40, 0x30, 0xE4, 0x03, 0x12, 0xB0, 0x7E, 0xE5,
++0x40, 0x30, 0xE5, 0x02, 0x71, 0xAF, 0xE5, 0x40,
++0x30, 0xE6, 0x02, 0x71, 0x2B, 0x74, 0x77, 0x04,
++0x90, 0x01, 0xC4, 0xF0, 0x74, 0xDA, 0xA3, 0xF0,
++0xD0, 0x07, 0xD0, 0x06, 0xD0, 0x05, 0xD0, 0x04,
++0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00,
++0xD0, 0xD0, 0xD0, 0x82, 0xD0, 0x83, 0xD0, 0xF0,
++0xD0, 0xE0, 0x32, 0x90, 0x88, 0x36, 0xE0, 0x60,
++0x11, 0x90, 0x06, 0x92, 0xE0, 0x30, 0xE1, 0x05,
++0xD1, 0xA7, 0x02, 0x04, 0x7A, 0xD1, 0x66, 0x12,
++0xB6, 0x3C, 0x22, 0x90, 0x88, 0x31, 0xE0, 0xFF,
++0x12, 0xA8, 0xAE, 0x30, 0xE0, 0x1F, 0xEF, 0x54,
++0x7F, 0x91, 0x92, 0x30, 0xE1, 0x06, 0xE0, 0x44,
++0x02, 0xF0, 0x80, 0x08, 0xE0, 0x54, 0xFD, 0xF0,
++0x91, 0x9B, 0x04, 0xF0, 0x90, 0x88, 0x36, 0xE0,
++0x60, 0x03, 0x12, 0xB6, 0x3C, 0x7F, 0x01, 0x90,
++0x98, 0x50, 0xE0, 0xFD, 0x30, 0xE0, 0x4F, 0x90,
++0x98, 0x55, 0xE0, 0xFC, 0x60, 0x48, 0x12, 0xBC,
++0x0C, 0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE,
++0xD8, 0xF9, 0xFF, 0x90, 0x04, 0xE0, 0xE0, 0xFB,
++0xEF, 0x5B, 0x60, 0x0B, 0xE4, 0x90, 0x98, 0x55,
++0xF0, 0x90, 0x98, 0x57, 0x04, 0xF0, 0x22, 0x90,
++0x98, 0x52, 0xE0, 0xD3, 0x9C, 0x50, 0x17, 0xED,
++0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, 0xE0, 0x07,
++0x91, 0x89, 0x12, 0x8F, 0xF3, 0x80, 0x03, 0x12,
++0xAD, 0x5C, 0x71, 0xFC, 0xF0, 0x22, 0x90, 0x8A,
++0xAF, 0x12, 0x90, 0x47, 0x91, 0xA5, 0x22, 0x90,
++0x99, 0xAF, 0xE0, 0xB4, 0x01, 0x20, 0xE4, 0xF0,
++0x90, 0x01, 0x5B, 0xF0, 0x90, 0x92, 0x20, 0xF0,
++0x90, 0x88, 0x95, 0xE0, 0xC3, 0x13, 0x54, 0x7F,
++0x90, 0x92, 0x21, 0xF0, 0xE4, 0xFB, 0xFD, 0x7F,
++0x58, 0x7E, 0x01, 0x12, 0x66, 0x33, 0x90, 0x88,
++0x31, 0xD1, 0x5E, 0x30, 0xE0, 0x1A, 0xEF, 0x54,
++0xBF, 0x91, 0x92, 0x30, 0xE0, 0x06, 0xE0, 0x44,
++0x01, 0xF0, 0x80, 0x09, 0xE0, 0x54, 0xFE, 0xF0,
++0x91, 0x9B, 0x74, 0x04, 0xF0, 0x12, 0xB6, 0x3C,
++0xE4, 0xFF, 0x61, 0x57, 0x90, 0x98, 0x50, 0xE0,
++0x54, 0xFE, 0x22, 0x90, 0x98, 0x50, 0xE0, 0x30,
++0xE0, 0x77, 0x90, 0x98, 0x54, 0xE0, 0x04, 0xF0,
++0x90, 0x98, 0x57, 0xE0, 0x64, 0x01, 0x70, 0x30,
++0x90, 0x98, 0x50, 0x12, 0xB4, 0xA4, 0x30, 0xE0,
++0x27, 0x90, 0x98, 0x56, 0xE0, 0x70, 0x21, 0x90,
++0x98, 0x53, 0xE0, 0xFE, 0xA3, 0xE0, 0xC3, 0x9E,
++0x40, 0x16, 0x91, 0x82, 0x30, 0xE0, 0x0A, 0x91,
++0x89, 0x12, 0x8F, 0xF3, 0x71, 0xFC, 0xF0, 0x80,
++0x07, 0x12, 0xAD, 0x5C, 0x71, 0xFC, 0xF0, 0x22,
++0x90, 0x98, 0x54, 0xE0, 0xFF, 0x90, 0x98, 0x51,
++0xE0, 0xD3, 0x9F, 0x50, 0x2C, 0x90, 0x06, 0x92,
++0xE0, 0x20, 0xE2, 0x16, 0x90, 0x98, 0x56, 0xE0,
++0x70, 0x10, 0x90, 0x8A, 0xAF, 0x12, 0x90, 0x47,
++0x91, 0xA5, 0x90, 0x98, 0x4F, 0xE0, 0x04, 0xF0,
++0x80, 0x06, 0x90, 0x06, 0x92, 0x74, 0x04, 0xF0,
++0xE4, 0x90, 0x98, 0x54, 0xF0, 0x90, 0x98, 0x56,
++0xF0, 0x22, 0xEF, 0x13, 0x13, 0x13, 0x54, 0x1F,
++0x22, 0xE4, 0xFD, 0xFF, 0x12, 0x6E, 0x71, 0xE4,
++0xFF, 0x22, 0xF0, 0x90, 0x04, 0xE0, 0xE0, 0x90,
++0x88, 0x32, 0x22, 0x90, 0x01, 0xB9, 0x74, 0x01,
++0xF0, 0x90, 0x01, 0xB8, 0x22, 0x7D, 0x08, 0xE4,
++0xFF, 0x12, 0x04, 0x7E, 0x90, 0x98, 0x55, 0xE0,
++0x04, 0xF0, 0x22, 0x90, 0x99, 0xB1, 0x12, 0x82,
++0x27, 0xD1, 0xB2, 0x12, 0x8F, 0x6A, 0xFF, 0x54,
++0x01, 0xFE, 0x71, 0xFC, 0x4E, 0xF0, 0xEF, 0xC3,
++0x13, 0x30, 0xE0, 0x2E, 0x12, 0x9C, 0x58, 0x90,
++0x98, 0x51, 0x12, 0x87, 0xE6, 0x90, 0x98, 0x52,
++0xF0, 0x12, 0x02, 0x06, 0xFF, 0x54, 0x04, 0xFE,
++0x90, 0x98, 0x50, 0xE0, 0x54, 0xFB, 0x4E, 0x12,
++0x87, 0xA3, 0x90, 0x98, 0x53, 0xF0, 0xEF, 0x54,
++0x08, 0xFF, 0x90, 0x98, 0x50, 0xE0, 0x54, 0xF7,
++0x4F, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3,
++0xC0, 0xD0, 0xD1, 0x6E, 0x20, 0xE0, 0x0C, 0x90,
++0x00, 0x04, 0xE0, 0x54, 0xF7, 0xF0, 0x12, 0xCD,
++0xD4, 0xC1, 0x59, 0x12, 0x8F, 0x6A, 0xFF, 0x54,
++0x01, 0xFE, 0x90, 0x93, 0x29, 0xD1, 0xC9, 0xFD,
++0xEF, 0x54, 0xFB, 0x4D, 0xFF, 0x90, 0x93, 0x29,
++0x12, 0x9F, 0xDF, 0xD1, 0x77, 0xFF, 0x90, 0x93,
++0x29, 0xD1, 0x89, 0x12, 0x9F, 0xE7, 0xD1, 0x80,
++0xFF, 0x90, 0x93, 0x29, 0xD1, 0x92, 0xF0, 0x12,
++0x9C, 0x58, 0x54, 0x80, 0xFF, 0x90, 0x93, 0x2A,
++0xE0, 0x54, 0x7F, 0x12, 0x87, 0xD0, 0xFF, 0x54,
++0x02, 0xFE, 0x90, 0x93, 0x2D, 0xE0, 0x54, 0xFD,
++0x4E, 0xFE, 0xF0, 0xEF, 0x54, 0x08, 0xFF, 0xEE,
++0x54, 0xF7, 0x4F, 0x12, 0x87, 0x9B, 0x90, 0x93,
++0x2E, 0x12, 0x87, 0xD1, 0x54, 0x10, 0xFF, 0x90,
++0x93, 0x2D, 0xE0, 0x54, 0xEF, 0x4F, 0xF0, 0x12,
++0x02, 0x06, 0xFF, 0x13, 0x13, 0x54, 0x3F, 0x30,
++0xE0, 0x07, 0x90, 0x06, 0x90, 0xE0, 0x44, 0x04,
++0xF0, 0x91, 0x82, 0x30, 0xE0, 0x07, 0x90, 0x06,
++0x90, 0xE0, 0x44, 0x08, 0xF0, 0x90, 0x93, 0x2E,
++0xE0, 0x70, 0x02, 0x04, 0xF0, 0x12, 0xC7, 0x9B,
++0x12, 0x87, 0xD2, 0xC4, 0x54, 0x0F, 0x30, 0xE0,
++0x0E, 0x7F, 0x05, 0x12, 0x7B, 0x41, 0xEF, 0x54,
++0x7F, 0xFD, 0x7F, 0x05, 0x12, 0x7B, 0x2E, 0x90,
++0x86, 0xB3, 0xE0, 0xB4, 0x02, 0x06, 0x12, 0xA8,
++0xAA, 0x20, 0xE0, 0x66, 0x90, 0x99, 0xB1, 0x12,
++0x9C, 0x55, 0x54, 0x7F, 0xFF, 0x90, 0x93, 0x2A,
++0xE0, 0x54, 0x80, 0x12, 0x87, 0xE5, 0x54, 0x7F,
++0xFF, 0x90, 0x93, 0x2B, 0xE0, 0x54, 0x80, 0x12,
++0x87, 0xA2, 0xFF, 0x54, 0x01, 0xFE, 0x90, 0x93,
++0x2C, 0xE0, 0x54, 0xFE, 0x4E, 0xFE, 0xF0, 0xEF,
++0x54, 0xFE, 0xFF, 0xEE, 0x54, 0x01, 0x12, 0x87,
++0xD0, 0xFF, 0x54, 0x04, 0xFE, 0x90, 0x93, 0x2D,
++0xE0, 0x54, 0xFB, 0x4E, 0xFE, 0xF0, 0xEF, 0x54,
++0x01, 0xFF, 0xEE, 0x54, 0xFE, 0x4F, 0xF0, 0x12,
++0xBA, 0x1F, 0x54, 0x07, 0x7D, 0x00, 0x20, 0xE0,
++0x02, 0x7D, 0x01, 0x12, 0xB8, 0xD2, 0x90, 0x93,
++0x2D, 0xE0, 0xFF, 0xC3, 0x13, 0x30, 0xE0, 0x02,
++0xF1, 0x01, 0x90, 0x86, 0xB3, 0xE0, 0xB4, 0x01,
++0x07, 0x90, 0xFE, 0x10, 0xE0, 0x44, 0x04, 0xF0,
++0x7E, 0x00, 0x7F, 0x60, 0x7D, 0x00, 0x7B, 0x01,
++0x7A, 0x95, 0x79, 0x33, 0x12, 0x04, 0x80, 0x90,
++0x95, 0x63, 0x74, 0x05, 0xF0, 0x12, 0x9F, 0x8E,
++0x7B, 0x01, 0x7A, 0x94, 0x79, 0x42, 0x12, 0x04,
++0x80, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xE0, 0xFF,
++0xC4, 0x13, 0x13, 0x54, 0x03, 0x22, 0x90, 0x88,
++0x31, 0xE0, 0x54, 0xF7, 0xF0, 0x22, 0x90, 0x99,
++0xB1, 0x12, 0x82, 0x27, 0x02, 0x02, 0x06, 0xFE,
++0x54, 0x10, 0xFD, 0xEF, 0x54, 0xEF, 0x4D, 0x22,
++0xFE, 0x54, 0x40, 0xFD, 0xEF, 0x54, 0xBF, 0x4D,
++0x22, 0xF0, 0xEE, 0x54, 0x20, 0xFE, 0xEF, 0x54,
++0xDF, 0x22, 0xF0, 0xEE, 0x54, 0x80, 0xFE, 0xEF,
++0x54, 0x7F, 0x4E, 0x22, 0x90, 0x8A, 0xE5, 0x12,
++0x90, 0x47, 0x7F, 0x80, 0x02, 0x04, 0x7E, 0x90,
++0x8B, 0x01, 0xE0, 0xFE, 0xA3, 0xE0, 0xAA, 0x06,
++0xF9, 0x22, 0x12, 0x9F, 0x8E, 0x7B, 0x01, 0x7A,
++0x98, 0x79, 0x50, 0x12, 0x04, 0x80, 0x90, 0x98,
++0x51, 0x74, 0x08, 0xF0, 0xA3, 0x74, 0x03, 0xF0,
++0x22, 0xE0, 0x54, 0xFE, 0x4E, 0xFE, 0xF0, 0xEF,
++0x54, 0x02, 0xFF, 0xEE, 0x54, 0xFD, 0x4F, 0xFF,
++0xF0, 0x12, 0x02, 0x06, 0xFE, 0x54, 0x04, 0x22,
++0xE4, 0xFF, 0x12, 0x78, 0x4A, 0xBF, 0x01, 0x18,
++0x90, 0x88, 0x36, 0xE0, 0x60, 0x12, 0x12, 0x97,
++0xF1, 0x64, 0x02, 0x60, 0x08, 0x90, 0x8A, 0xE1,
++0xD1, 0xAA, 0x02, 0x04, 0x7A, 0x12, 0x73, 0x8F,
++0x22, 0x90, 0x98, 0x49, 0x74, 0x06, 0xF0, 0x90,
++0x98, 0x48, 0x74, 0x08, 0xF0, 0x90, 0x00, 0x4A,
++0xE0, 0x54, 0xFE, 0xF0, 0x90, 0x00, 0x4F, 0xE0,
++0x44, 0x40, 0xF0, 0x90, 0x00, 0x40, 0xE0, 0x44,
++0x08, 0xF0, 0x90, 0x93, 0x29, 0xE0, 0xC4, 0x13,
++0x54, 0x07, 0x90, 0x00, 0x65, 0x30, 0xE0, 0x06,
++0xE0, 0x44, 0x20, 0xF0, 0x80, 0x04, 0xE0, 0x54,
++0xDF, 0xF0, 0x12, 0xBF, 0xA0, 0x7D, 0x01, 0x02,
++0xBA, 0x4D, 0xC0, 0xE0, 0xC0, 0x83, 0xC0, 0x82,
++0xC0, 0xD0, 0x75, 0xD0, 0x00, 0xC0, 0x05, 0xC0,
++0x07, 0x7D, 0x42, 0x90, 0x01, 0xC4, 0xED, 0xF0,
++0x74, 0xDF, 0xFF, 0xA3, 0xF0, 0xED, 0x04, 0x90,
++0x01, 0xC4, 0xF0, 0xA3, 0xEF, 0xF0, 0xD0, 0x07,
++0xD0, 0x05, 0xD0, 0xD0, 0xD0, 0x82, 0xD0, 0x83,
++0xD0, 0xE0, 0x32, 0xD3, 0x10, 0xAF, 0x01, 0xC3,
++0xC0, 0xD0, 0x90, 0x9C, 0xB0, 0xED, 0xF0, 0xA3,
++0xEB, 0xF0, 0x90, 0x9C, 0xAF, 0xEF, 0xF0, 0xE4,
++0xFD, 0xFC, 0x12, 0xE3, 0xD4, 0x90, 0x9C, 0xB2,
++0xF0, 0x12, 0xEE, 0xBE, 0x90, 0x9C, 0xAF, 0xE0,
++0x90, 0x04, 0x25, 0xF0, 0x90, 0x9C, 0xB0, 0xE0,
++0x60, 0x07, 0x12, 0xFB, 0x5E, 0xE0, 0x44, 0x80,
++0xF0, 0xAF, 0x05, 0x74, 0x20, 0x2F, 0x12, 0xFB,
++0xB3, 0x54, 0xC0, 0xF0, 0x12, 0xFB, 0x5E, 0xE0,
++0x54, 0xC0, 0xF0, 0x90, 0x9C, 0xB2, 0xE0, 0xFF,
++0xAE, 0x05, 0x74, 0x18, 0x2E, 0x12, 0xD7, 0xD4,
++0xEF, 0xF0, 0x90, 0x00, 0x8B, 0xE0, 0xD3, 0x94,
++0x03, 0x74, 0x10, 0x2E, 0x12, 0xD7, 0xDC, 0x74,
++0x04, 0xF0, 0xAF, 0x05, 0x12, 0xE0, 0x57, 0xE0,
++0x54, 0x01, 0xFE, 0x90, 0x9C, 0xB1, 0xE0, 0x25,
++0xE0, 0x25, 0xE0, 0xFB, 0xEE, 0x44, 0x02, 0x4B,
++0x12, 0xE0, 0x56, 0xEE, 0xF0, 0x74, 0x11, 0x2F,
++0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0x74,
++0xFF, 0xF0, 0x74, 0x29, 0x2F, 0x11, 0x62, 0x54,
++0xF7, 0xF0, 0x74, 0x0D, 0x2D, 0xF5, 0x82, 0xE4,
++0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x80, 0xF0,
++0xAE, 0x04, 0xAF, 0x05, 0xD0, 0xD0, 0x92, 0xAF,
++0x22, 0x90, 0x9C, 0xA8, 0xE0, 0xFE, 0xA3, 0xE0,
++0xFF, 0x90, 0x8A, 0x9B, 0xE0, 0xFC, 0xA3, 0xE0,
++0xFD, 0xF5, 0x82, 0x8C, 0x83, 0x12, 0x04, 0x7E,
++0x90, 0x9C, 0xA8, 0xA3, 0xE0, 0xFF, 0x24, 0x12,
++0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0,
++0x54, 0x01, 0xFE, 0x90, 0x9C, 0xA7, 0xE0, 0x25,
++0xE0, 0x25, 0xE0, 0x44, 0x02, 0x4E, 0xFE, 0x74,
++0x12, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5,
++0x83, 0x22, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5,
++0x83, 0xE0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3,
++0xC0, 0xD0, 0x11, 0xB4, 0x90, 0x9C, 0xB3, 0x12,
++0x04, 0x31, 0x90, 0x9C, 0xB3, 0x12, 0xD1, 0x68,
++0x7F, 0x30, 0x7E, 0x08, 0x12, 0x70, 0xAD, 0x90,
++0x01, 0x01, 0xE0, 0x44, 0x02, 0x11, 0xAC, 0x90,
++0x06, 0xB7, 0x74, 0x09, 0xF0, 0x90, 0x06, 0xB4,
++0x74, 0x86, 0xF0, 0x11, 0xC1, 0xF0, 0xE4, 0xFD,
++0x12, 0x76, 0xF7, 0x12, 0xB7, 0x83, 0xF0, 0xD0,
++0xD0, 0x92, 0xAF, 0x22, 0xF0, 0x90, 0x01, 0x00,
++0x74, 0xFF, 0xF0, 0x22, 0x7F, 0x30, 0x7E, 0x08,
++0x12, 0x70, 0x70, 0xED, 0x44, 0x80, 0xFD, 0xEC,
++0x22, 0x90, 0x93, 0x46, 0xE0, 0xFF, 0x90, 0x93,
++0x45, 0xE0, 0xFB, 0x90, 0x93, 0x47, 0xE0, 0x90,
++0x92, 0x90, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3,
++0xC0, 0xD0, 0x11, 0xB4, 0x90, 0x9C, 0xB7, 0x12,
++0x04, 0x31, 0x90, 0x9C, 0xB7, 0x12, 0xD1, 0x68,
++0x7F, 0x30, 0x7E, 0x08, 0x12, 0x70, 0xAD, 0x11,
++0xC1, 0xF0, 0x7D, 0x01, 0x12, 0x76, 0xF7, 0x12,
++0x88, 0xC5, 0x90, 0x06, 0xB7, 0x74, 0x11, 0xF0,
++0x7F, 0x03, 0x7E, 0x00, 0x12, 0x7C, 0x6A, 0x90,
++0x06, 0xB4, 0xE0, 0x54, 0x0F, 0x70, 0xF1, 0x90,
++0x07, 0xD5, 0xE0, 0x44, 0x80, 0xF0, 0x7F, 0x0A,
++0x80, 0x09, 0x90, 0x06, 0x62, 0xE0, 0x30, 0xE0,
++0x09, 0x7F, 0x01, 0x7E, 0x00, 0x12, 0x7C, 0x6A,
++0x80, 0xF0, 0x12, 0xB7, 0xA9, 0x90, 0x01, 0x00,
++0x74, 0x3F, 0xF0, 0xA3, 0xE0, 0x54, 0xFD, 0xF0,
++0x90, 0x05, 0x53, 0xE0, 0x44, 0x20, 0xF0, 0x90,
++0x07, 0xD5, 0xE0, 0x54, 0x7F, 0xF0, 0xD0, 0xD0,
++0x92, 0xAF, 0x22, 0xE4, 0x90, 0x9C, 0xC7, 0xF0,
++0xA3, 0xF0, 0x90, 0x05, 0x22, 0xE0, 0x90, 0x9C,
++0xC9, 0xF0, 0x7B, 0x47, 0x7D, 0xFF, 0xE4, 0xFF,
++0x12, 0x8D, 0x1E, 0x90, 0x05, 0xF8, 0xE0, 0x70,
++0x1B, 0xA3, 0xE0, 0x70, 0x17, 0xA3, 0xE0, 0x70,
++0x13, 0xA3, 0xE0, 0x70, 0x0F, 0x90, 0x9C, 0xC9,
++0xE0, 0xFD, 0x7B, 0x48, 0xE4, 0xFF, 0x12, 0x8D,
++0x1E, 0x7F, 0x01, 0x22, 0xD3, 0x90, 0x9C, 0xC8,
++0xE0, 0x94, 0xE8, 0x90, 0x9C, 0xC7, 0xE0, 0x94,
++0x03, 0x40, 0x16, 0x90, 0x01, 0xC0, 0xE0, 0x44,
++0x20, 0xF0, 0x90, 0x9C, 0xC9, 0xE0, 0xFD, 0x7B,
++0x5B, 0xE4, 0xFF, 0x12, 0x8D, 0x1E, 0x7F, 0x00,
++0x22, 0x7F, 0x32, 0x7E, 0x00, 0x12, 0x7C, 0x6A,
++0x90, 0x9C, 0xC7, 0x12, 0xBF, 0xF1, 0x80, 0xAB,
++0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90,
++0x9C, 0xD5, 0xEF, 0xF0, 0x90, 0x00, 0x8F, 0xE0,
++0x30, 0xE6, 0x45, 0x90, 0x00, 0x8D, 0xE0, 0x64,
++0x01, 0x70, 0x3D, 0x90, 0x9C, 0xD6, 0xF0, 0x90,
++0x9C, 0xD6, 0xE0, 0xFD, 0x90, 0x9C, 0xD5, 0xE0,
++0xC4, 0x54, 0xF0, 0x24, 0x00, 0xF5, 0x82, 0xE4,
++0x34, 0x81, 0xF5, 0x83, 0xE5, 0x82, 0x2D, 0x12,
++0xBD, 0xE1, 0xE0, 0xFB, 0xE4, 0xFF, 0x51, 0x15,
++0x90, 0x9C, 0xD6, 0xE0, 0x04, 0xF0, 0xE0, 0xC3,
++0x94, 0x10, 0x40, 0xD3, 0x90, 0x00, 0x8F, 0xE0,
++0x30, 0xE0, 0x05, 0x90, 0x00, 0x8D, 0xE4, 0xF0,
++0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xEF, 0x70, 0x04,
++0x74, 0xF0, 0x80, 0x16, 0xEF, 0xB4, 0x01, 0x04,
++0x74, 0xF4, 0x80, 0x0E, 0xEF, 0xB4, 0x02, 0x04,
++0x74, 0xF8, 0x80, 0x06, 0xEF, 0xB4, 0x03, 0x0C,
++0x74, 0xFC, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0x02,
++0xF5, 0x83, 0xEB, 0xF0, 0x22, 0xEF, 0x64, 0x01,
++0x70, 0x26, 0x90, 0x93, 0x2B, 0xE0, 0x54, 0x7F,
++0xFF, 0x7E, 0x00, 0x90, 0x93, 0x2D, 0xE0, 0x13,
++0x13, 0x54, 0x01, 0xFD, 0x90, 0x93, 0x2C, 0xE0,
++0xFC, 0xC3, 0x13, 0x54, 0x7F, 0xFB, 0xEC, 0x54,
++0x01, 0x90, 0x9C, 0x98, 0xF0, 0x12, 0xB9, 0x7C,
++0x22, 0x90, 0x01, 0x8C, 0xE4, 0xF0, 0xA3, 0xF0,
++0xA3, 0x74, 0x71, 0xF0, 0xA3, 0x74, 0x02, 0xF0,
++0x90, 0x01, 0x95, 0xE0, 0x54, 0xF0, 0x44, 0x07,
++0xF0, 0x90, 0x01, 0x98, 0x74, 0x7F, 0xF0, 0x90,
++0x01, 0x01, 0xE0, 0x54, 0xFB, 0xF0, 0xE0, 0x44,
++0x04, 0xF0, 0x22, 0x90, 0x01, 0x9A, 0xE0, 0x54,
++0xC0, 0x44, 0x0B, 0x12, 0xBE, 0xF6, 0x90, 0x01,
++0x98, 0xE0, 0x54, 0xC0, 0x7F, 0x00, 0xB4, 0x40,
++0x02, 0x7F, 0x01, 0x22, 0x90, 0x01, 0x95, 0xE0,
++0x7F, 0x00, 0x30, 0xE4, 0x02, 0x7F, 0x01, 0x22,
++0x90, 0x93, 0x24, 0xE0, 0x30, 0xE0, 0x0B, 0x90,
++0x8A, 0xE5, 0x12, 0x90, 0x47, 0x7F, 0x10, 0x12,
++0x04, 0x7E, 0x22, 0x90, 0x8A, 0x75, 0x12, 0x88,
++0xC8, 0x90, 0x8A, 0xE5, 0x12, 0x90, 0x47, 0x7F,
++0x02, 0x02, 0x04, 0x7E, 0x90, 0x01, 0xCF, 0xE0,
++0x90, 0x9A, 0xFB, 0xF0, 0xE0, 0xFF, 0x30, 0xE0,
++0x07, 0x90, 0x01, 0xCF, 0xE0, 0x54, 0xFE, 0xF0,
++0xEF, 0x30, 0xE5, 0x23, 0x90, 0x01, 0xCF, 0xE0,
++0x54, 0xDF, 0xF0, 0x90, 0x01, 0x34, 0x74, 0x20,
++0xF0, 0xE4, 0xF5, 0xA8, 0xF5, 0xE8, 0x12, 0x76,
++0x6D, 0x90, 0x00, 0x03, 0xE0, 0x54, 0xFB, 0xFD,
++0x7F, 0x03, 0x12, 0x7B, 0x2E, 0x80, 0xFE, 0x22,
++0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0xE4,
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++0x04, 0xF0, 0xA3, 0x14, 0xF0, 0x91, 0x3C, 0xEF,
++0x64, 0xFE, 0x90, 0x9A, 0x5E, 0x70, 0x1D, 0xA3,
++0xE0, 0x24, 0x00, 0xD1, 0xA6, 0xC0, 0x03, 0x8B,
++0x45, 0x91, 0x50, 0xD0, 0x03, 0xD1, 0xAE, 0x91,
++0x50, 0x7B, 0x01, 0x7A, 0x9A, 0x79, 0x69, 0x12,
++0x69, 0xF5, 0x80, 0x22, 0xE0, 0xFE, 0xA3, 0xE0,
++0xFF, 0x24, 0x00, 0xF5, 0x82, 0x74, 0xFC, 0x3E,
++0xF5, 0x83, 0xE4, 0xF0, 0x74, 0x01, 0x2F, 0xF5,
++0x82, 0x74, 0xFC, 0x3E, 0xF5, 0x83, 0xE4, 0xF0,
++0x90, 0x9A, 0x69, 0xF0, 0xA3, 0xF0, 0x91, 0x3C,
++0xE4, 0x90, 0x9A, 0x5B, 0xF0, 0x91, 0x5A, 0xFE,
++0x90, 0x9A, 0x5E, 0xA3, 0xE0, 0xFD, 0xEF, 0x2D,
++0x12, 0x8E, 0x99, 0xEE, 0xF0, 0x91, 0x5A, 0xFE,
++0x74, 0x6B, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x9A,
++0xF5, 0x83, 0xEE, 0x91, 0x00, 0xF0, 0xE0, 0xB4,
++0x08, 0xDB, 0x91, 0x11, 0x90, 0x9A, 0x5E, 0x12,
++0xC7, 0xA8, 0x90, 0x9A, 0x5E, 0x12, 0xC7, 0xA1,
++0x91, 0x07, 0xE4, 0x90, 0x9A, 0xE5, 0xF0, 0xE4,
++0x90, 0x9A, 0x5B, 0xF0, 0x91, 0x33, 0x50, 0x10,
++0x91, 0x6A, 0xA3, 0x71, 0xF9, 0x91, 0x46, 0x12,
++0x8E, 0x98, 0xE4, 0x91, 0x00, 0xF0, 0x80, 0xEC,
++0xD1, 0xB5, 0x90, 0x06, 0x31, 0xE0, 0x54, 0xFB,
++0xF0, 0x90, 0x98, 0x3B, 0xE0, 0xFD, 0xB1, 0xD5,
++0xCE, 0xC3, 0x13, 0xCE, 0x13, 0xD8, 0xF9, 0x91,
++0x7C, 0xED, 0xFF, 0x90, 0x98, 0x3A, 0xB1, 0xBE,
++0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, 0xFF,
++0x90, 0x9A, 0x5A, 0xE0, 0x7C, 0x00, 0x2F, 0xFF,
++0xEC, 0x3E, 0xCF, 0x24, 0x38, 0xCF, 0x34, 0x00,
++0xFE, 0x90, 0x92, 0x06, 0x74, 0x10, 0xF0, 0x7B,
++0x63, 0xE4, 0xFD, 0x12, 0x71, 0xD4, 0x90, 0x9A,
++0x42, 0xE0, 0x70, 0x04, 0xA3, 0xE0, 0x64, 0x01,
++0x7B, 0x01, 0x7A, 0x9A, 0x79, 0x62, 0x70, 0x15,
++0x90, 0x91, 0xA0, 0x91, 0x2B, 0x90, 0x91, 0xA3,
++0x12, 0x82, 0x27, 0x90, 0x91, 0xA6, 0x91, 0x23,
++0x12, 0x6F, 0x34, 0x80, 0x13, 0x90, 0x91, 0x96,
++0x91, 0x2B, 0x90, 0x91, 0x99, 0x12, 0x82, 0x27,
++0x90, 0x91, 0x9C, 0x91, 0x23, 0x12, 0x6E, 0xF3,
++0x90, 0x9A, 0xE5, 0xE0, 0x04, 0xF0, 0x90, 0x06,
++0x31, 0xE0, 0x30, 0xE2, 0x06, 0x91, 0x1B, 0x50,
++0x02, 0x41, 0x9F, 0x91, 0x1B, 0x40, 0x0A, 0x90,
++0x06, 0x35, 0xE0, 0x44, 0x20, 0x90, 0x06, 0x34,
++0xF0, 0xE4, 0x90, 0x9A, 0x5B, 0xF0, 0x91, 0x33,
++0x50, 0x22, 0x91, 0x6A, 0xA3, 0x71, 0xF9, 0x91,
++0x46, 0x90, 0x9A, 0x5B, 0xE0, 0x24, 0x45, 0xF5,
++0x82, 0xE4, 0x34, 0x9A, 0xF5, 0x83, 0xE0, 0xFF,
++0x90, 0x9A, 0x59, 0x12, 0x8E, 0x98, 0xEF, 0x91,
++0x00, 0xF0, 0x80, 0xDA, 0x90, 0x9A, 0x42, 0xE0,
++0x70, 0x04, 0xA3, 0xE0, 0x64, 0x01, 0x70, 0x0E,
++0x90, 0x98, 0x3A, 0xE0, 0xFF, 0x90, 0x9A, 0x5A,
++0xE0, 0x24, 0x08, 0xFD, 0x91, 0x86, 0x90, 0x04,
++0x1D, 0xE0, 0x60, 0x24, 0x90, 0x05, 0x22, 0xE0,
++0x90, 0x9A, 0xE4, 0xF0, 0x7B, 0x1D, 0x12, 0x88,
++0xBF, 0xBF, 0x01, 0x06, 0x71, 0xE4, 0x90, 0x04,
++0x25, 0xF0, 0x90, 0x9A, 0xE4, 0xE0, 0xFD, 0x7B,
++0x1E, 0xE4, 0xFF, 0x12, 0x8D, 0x1E, 0x80, 0x06,
++0x71, 0xE4, 0x90, 0x04, 0x25, 0xF0, 0x90, 0x04,
++0x1F, 0x74, 0x20, 0xF0, 0x90, 0x88, 0x39, 0xE0,
++0x70, 0x05, 0x7F, 0x01, 0x12, 0x78, 0xC0, 0xD0,
++0xD0, 0x92, 0xAF, 0x22, 0x90, 0x98, 0x3A, 0xE0,
++0xFF, 0x90, 0x92, 0x13, 0x74, 0x08, 0xF0, 0x7B,
++0x18, 0x7D, 0x01, 0x12, 0x66, 0xDB, 0x90, 0x9A,
++0x59, 0xEF, 0xF0, 0x90, 0x98, 0x3A, 0xE0, 0x22,
++0xF0, 0x90, 0x9A, 0x5B, 0xE0, 0x04, 0x22, 0x90,
++0x9A, 0x5E, 0xE4, 0x75, 0xF0, 0x08, 0x12, 0x02,
++0xE7, 0x90, 0x9A, 0x5E, 0xE4, 0x75, 0xF0, 0x08,
++0x02, 0x02, 0xE7, 0x90, 0x9A, 0xE5, 0xE0, 0xC3,
++0x94, 0x0A, 0x22, 0x74, 0x10, 0xF0, 0x7A, 0x93,
++0x79, 0xF9, 0x22, 0x12, 0x82, 0x27, 0x7A, 0x9A,
++0x79, 0x45, 0x22, 0x90, 0x9A, 0x5B, 0xE0, 0xFF,
++0xC3, 0x94, 0x10, 0x22, 0x90, 0x9A, 0x5E, 0xE4,
++0x75, 0xF0, 0x02, 0x02, 0x02, 0xE7, 0xFD, 0x12,
++0x7B, 0x8B, 0x90, 0x9A, 0x59, 0xEF, 0xF0, 0x22,
++0x75, 0x46, 0x94, 0x75, 0x47, 0x40, 0x75, 0x48,
++0x02, 0x22, 0x90, 0x9A, 0x5B, 0xE0, 0xFF, 0x24,
++0x42, 0xF5, 0x82, 0xE4, 0x34, 0x94, 0xF5, 0x83,
++0xE0, 0x22, 0x90, 0x9A, 0x5F, 0xE0, 0x2F, 0xFF,
++0x90, 0x9A, 0x5E, 0xE0, 0x34, 0x00, 0xFE, 0x90,
++0x9A, 0xE2, 0xF0, 0x22, 0xFF, 0x90, 0x92, 0x07,
++0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0xD3, 0x10,
++0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x9C, 0x52,
++0xED, 0xF0, 0x90, 0x9C, 0x51, 0xEF, 0xF0, 0x12,
++0x7B, 0x07, 0x90, 0x9C, 0x5F, 0xEF, 0xF0, 0xE0,
++0xFD, 0x24, 0x01, 0x12, 0xC3, 0xF5, 0xE0, 0xFE,
++0x74, 0x00, 0x2D, 0x12, 0x8E, 0x9B, 0x12, 0xC7,
++0x92, 0x54, 0x3F, 0x90, 0x9C, 0x5C, 0xF0, 0xA3,
++0xEF, 0xF0, 0xE4, 0x90, 0x9C, 0x5B, 0xF0, 0xB1,
++0xF6, 0x50, 0x0A, 0xB1, 0xFF, 0x12, 0x8E, 0x98,
++0xE4, 0xB1, 0xDE, 0x80, 0xF2, 0x90, 0x9C, 0x5D,
++0xE0, 0x24, 0xF8, 0xFB, 0x90, 0x9C, 0x5C, 0xE0,
++0x34, 0xFF, 0xFA, 0x90, 0x9C, 0x52, 0xE0, 0xFF,
++0x90, 0x91, 0xDC, 0xE4, 0xF0, 0xA3, 0xEF, 0xF0,
++0xA3, 0x74, 0x01, 0xF0, 0x7D, 0x0A, 0x7C, 0x00,
++0x7F, 0x10, 0x7E, 0x00, 0x12, 0x6D, 0xED, 0x90,
++0x98, 0x3B, 0xE0, 0xFF, 0x90, 0x9C, 0x51, 0xE0,
++0xFD, 0xD3, 0x9F, 0x40, 0x36, 0x90, 0x98, 0x3B,
++0xE0, 0xFC, 0xB1, 0xD5, 0xCE, 0xC3, 0x13, 0xCE,
++0x13, 0xD8, 0xF9, 0x91, 0x7C, 0xEC, 0xFF, 0xC3,
++0xED, 0xB1, 0xC0, 0xC3, 0x33, 0xCE, 0x33, 0xCE,
++0xD8, 0xF9, 0x24, 0x28, 0xFF, 0xE4, 0x3E, 0xFE,
++0xB1, 0xEE, 0xFD, 0x90, 0x9C, 0x52, 0xE0, 0xFC,
++0xC3, 0xED, 0x9C, 0xB1, 0xE6, 0x7D, 0x38, 0x7C,
++0x00, 0x80, 0x35, 0x90, 0x9C, 0x51, 0xE0, 0xFD,
++0xB1, 0xD5, 0xCE, 0xC3, 0x13, 0xCE, 0x13, 0xD8,
++0xF9, 0x91, 0x7C, 0xED, 0xFF, 0x90, 0x98, 0x3B,
++0xB1, 0xBE, 0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8,
++0xF9, 0x24, 0x38, 0xFD, 0xE4, 0x3E, 0xFC, 0xB1,
++0xEE, 0xFF, 0x90, 0x9C, 0x52, 0xE0, 0xFE, 0xC3,
++0xEF, 0x9E, 0xB1, 0xE6, 0x7F, 0x28, 0x7E, 0x00,
++0x12, 0x71, 0xD4, 0x12, 0xB7, 0x9B, 0x90, 0x91,
++0x45, 0x12, 0x82, 0x27, 0x0B, 0x7A, 0x9C, 0x79,
++0x53, 0x90, 0x91, 0x48, 0x12, 0x82, 0x27, 0x90,
++0x91, 0x4B, 0x74, 0x08, 0xF0, 0x7A, 0x94, 0x79,
++0x31, 0x12, 0x4E, 0xA5, 0xE4, 0x90, 0x9C, 0x5B,
++0xF0, 0xB1, 0xF6, 0x50, 0x1C, 0xB1, 0xFF, 0x90,
++0x9C, 0x5B, 0xE0, 0x24, 0x53, 0xF5, 0x82, 0xE4,
++0x34, 0x9C, 0xF5, 0x83, 0xE0, 0xFF, 0x90, 0x9C,
++0x5E, 0x12, 0x8E, 0x98, 0xEF, 0xB1, 0xDE, 0x80,
++0xE0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xE0, 0xC3,
++0x9F, 0xFF, 0xE4, 0x94, 0x00, 0xFE, 0xEF, 0x78,
++0x07, 0x22, 0xE4, 0xFD, 0x7F, 0x03, 0x12, 0x54,
++0x1E, 0x90, 0x98, 0x3C, 0xE0, 0x75, 0xF0, 0x80,
++0xA4, 0xAE, 0xF0, 0x78, 0x03, 0x22, 0xF0, 0x90,
++0x9C, 0x5B, 0xE0, 0x04, 0xF0, 0x22, 0xFB, 0x90,
++0x92, 0x06, 0x74, 0x08, 0xF0, 0x22, 0x90, 0x9C,
++0x5C, 0xA3, 0xE0, 0x24, 0xF8, 0x22, 0x90, 0x9C,
++0x5B, 0xE0, 0xFF, 0xC3, 0x94, 0x08, 0x22, 0x90,
++0x9C, 0x5F, 0xE0, 0xFD, 0x90, 0x9C, 0x5D, 0xE0,
++0x2D, 0xFD, 0x90, 0x9C, 0x5C, 0xE0, 0x34, 0x00,
++0xCD, 0x24, 0x20, 0xCD, 0x34, 0x00, 0xFC, 0x7E,
++0x00, 0xED, 0x2F, 0xFF, 0xEE, 0x3C, 0xFE, 0x90,
++0x9C, 0x51, 0xE0, 0xFD, 0x12, 0x7B, 0x8B, 0x90,
++0x9C, 0x5E, 0xEF, 0xF0, 0x22, 0x90, 0x9A, 0x3F,
++0x12, 0xA7, 0xE6, 0xD1, 0x4A, 0xD1, 0x41, 0x12,
++0xF1, 0x20, 0xD1, 0x41, 0xA3, 0xE0, 0xFD, 0x01,
++0xF8, 0x90, 0x9A, 0x3F, 0xE0, 0xFE, 0xA3, 0xE0,
++0xFF, 0x22, 0xE4, 0xFD, 0x7F, 0x03, 0x12, 0x54,
++0x1E, 0x90, 0x01, 0x85, 0xE0, 0x54, 0xFE, 0xF0,
++0xB1, 0xCA, 0xCE, 0xC3, 0x13, 0xCE, 0x13, 0xD8,
++0xF9, 0xD1, 0x9A, 0x02, 0x54, 0x1E, 0xE4, 0xFD,
++0xFC, 0xEF, 0x60, 0x2D, 0x90, 0x98, 0x3B, 0xD1,
++0xBC, 0xD1, 0xA3, 0x90, 0x99, 0xB1, 0x12, 0x82,
++0x27, 0x90, 0x99, 0xB1, 0x12, 0x8B, 0xE0, 0x75,
++0x48, 0x40, 0x7B, 0x01, 0x7A, 0x93, 0x79, 0xF9,
++0x12, 0x69, 0xF5, 0xB1, 0xCA, 0xCE, 0xC3, 0x13,
++0xCE, 0x13, 0xD8, 0xF9, 0xD1, 0x9A, 0x12, 0x54,
++0x1E, 0x22, 0xFF, 0x12, 0x77, 0xA4, 0x7D, 0x01,
++0x7F, 0x03, 0x22, 0x74, 0x00, 0x2F, 0xF9, 0xE4,
++0x34, 0xFC, 0xFA, 0x7B, 0x01, 0x22, 0x12, 0x69,
++0xF5, 0x75, 0x45, 0x01, 0x22, 0x7F, 0x64, 0x7E,
++0x00, 0x02, 0x7C, 0x6A, 0xE0, 0xFF, 0x12, 0x7B,
++0x07, 0x7C, 0x00, 0xAD, 0x07, 0x22, 0x12, 0x7B,
++0x07, 0x7E, 0x00, 0x74, 0x00, 0x2F, 0x12, 0x8D,
++0xC5, 0x75, 0x48, 0x70, 0x7B, 0x01, 0x7A, 0x93,
++0x79, 0x61, 0x02, 0x69, 0xF5, 0xEF, 0x60, 0x07,
++0x90, 0x98, 0x3D, 0xE0, 0xFF, 0xD1, 0xC6, 0x22,
++0x12, 0xA7, 0xE3, 0x2F, 0xFF, 0xE4, 0x3E, 0xCF,
++0x24, 0x06, 0xCF, 0x34, 0x00, 0x12, 0xA2, 0x39,
++0xEF, 0x64, 0x86, 0x70, 0x20, 0x90, 0x9A, 0x63,
++0xE0, 0xFF, 0x90, 0x9A, 0x62, 0xE0, 0x2F, 0xFF,
++0x90, 0x9A, 0x61, 0xE0, 0x34, 0x00, 0xCF, 0x24,
++0x07, 0xCF, 0x34, 0x00, 0x12, 0xA2, 0x39, 0xBF,
++0xDD, 0x03, 0x7F, 0x01, 0x22, 0x7F, 0x00, 0x22,
++0x12, 0xE7, 0x60, 0xA3, 0xED, 0xF0, 0x78, 0x37,
++0x7C, 0x9A, 0x7D, 0x01, 0x7B, 0xFF, 0x7A, 0x80,
++0x79, 0x94, 0x7E, 0x00, 0x7F, 0x06, 0x12, 0x01,
++0xE0, 0x12, 0xFB, 0xAA, 0x7A, 0x80, 0x79, 0x9A,
++0x12, 0xFB, 0xD3, 0x78, 0x4D, 0x7C, 0x9A, 0x7D,
++0x01, 0x7B, 0xFF, 0x7A, 0x80, 0x79, 0xAA, 0x12,
++0xFB, 0xD3, 0xE4, 0x90, 0x9A, 0x60, 0x12, 0xAF,
++0x22, 0xA3, 0xE0, 0xFD, 0xD1, 0xE8, 0xEF, 0x64,
++0x01, 0x60, 0x03, 0x02, 0xF0, 0xFD, 0x12, 0xA6,
++0x24, 0xCF, 0x24, 0x0E, 0xCF, 0x34, 0x00, 0x12,
++0xA2, 0x39, 0xEF, 0x64, 0x3A, 0x60, 0x03, 0x02,
++0xF0, 0xFD, 0x12, 0xA6, 0x24, 0xCF, 0x24, 0x30,
++0xCF, 0x34, 0x00, 0x12, 0xA2, 0x39, 0xEF, 0x64,
++0x87, 0x60, 0x03, 0x02, 0xF0, 0xFD, 0x90, 0x9A,
++0x60, 0x04, 0xF0, 0xE4, 0x90, 0x9A, 0x5D, 0xF0,
++0x12, 0xF1, 0x03, 0x94, 0x10, 0x50, 0x1C, 0x12,
++0xA7, 0x8F, 0x12, 0xA6, 0x2F, 0xCD, 0x24, 0x38,
++0x12, 0xA2, 0x2E, 0x90, 0x9A, 0x5D, 0xE0, 0x24,
++0x4D, 0xF5, 0x82, 0xE4, 0x34, 0x9A, 0x12, 0xF1,
++0x0A, 0x80, 0xDD, 0xE4, 0x90, 0x9A, 0x5E, 0xF0,
++0x90, 0x9A, 0x5E, 0xE0, 0xFF, 0xC3, 0x94, 0x02,
++0x40, 0x03, 0x02, 0xF0, 0xFD, 0x75, 0xF0, 0x38,
++0xEF, 0x12, 0xF3, 0x56, 0x20, 0xE0, 0x03, 0x02,
++0xF0, 0xFD, 0xE4, 0x90, 0x9A, 0x5F, 0xF0, 0x12,
++0xF3, 0x5E, 0x90, 0x93, 0x62, 0x12, 0x04, 0x6E,
++0xE0, 0xFE, 0x90, 0x9A, 0x5F, 0xE0, 0xC3, 0x9E,
++0x40, 0x03, 0x02, 0xF0, 0xF4, 0xEF, 0x75, 0xF0,
++0x38, 0xA4, 0x24, 0x79, 0xF9, 0x74, 0x93, 0x35,
++0xF0, 0xFA, 0x7B, 0x01, 0xE0, 0x75, 0xF0, 0x10,
++0xA4, 0x29, 0xF9, 0xEA, 0x35, 0xF0, 0xFA, 0x78,
++0x4D, 0x7C, 0x9A, 0x31, 0x15, 0x60, 0x02, 0x01,
++0xE4, 0x90, 0x06, 0x33, 0xE0, 0x44, 0x01, 0x54,
++0xFB, 0xF0, 0xE4, 0x90, 0x9A, 0x5D, 0xF0, 0x31,
++0x03, 0x94, 0x06, 0x50, 0x15, 0x12, 0xA7, 0x8F,
++0x12, 0xA6, 0x2F, 0xCD, 0x24, 0x4A, 0x12, 0xA2,
++0x2E, 0x90, 0x9A, 0x5D, 0x71, 0x78, 0x31, 0x0A,
++0x80, 0xE5, 0xE4, 0x90, 0x9A, 0x5D, 0xF0, 0x31,
++0x03, 0x94, 0x10, 0x50, 0x0C, 0x12, 0xA2, 0x1A,
++0x90, 0x9A, 0x5D, 0x71, 0x6F, 0x31, 0x0A, 0x80,
++0xEE, 0x71, 0x5E, 0x71, 0x56, 0xFE, 0xC3, 0x13,
++0x30, 0xE0, 0x2B, 0xEF, 0x75, 0xF0, 0x38, 0xA4,
++0x24, 0x69, 0xF9, 0x74, 0x93, 0x35, 0xF0, 0xFA,
++0x7B, 0x01, 0x78, 0x3D, 0x7C, 0x9A, 0x31, 0x15,
++0x70, 0x71, 0x90, 0x98, 0x35, 0xE0, 0xB4, 0x02,
++0x0B, 0x90, 0x93, 0x25, 0x12, 0xB4, 0xAE, 0x20,
++0xE0, 0x1E, 0x80, 0x12, 0x80, 0x1A, 0x90, 0x98,
++0x35, 0xE0, 0xB4, 0x02, 0x13, 0x90, 0x93, 0x25,
++0x12, 0xB4, 0xAE, 0x20, 0xE0, 0x0A, 0x90, 0x01,
++0xC7, 0x74, 0x0A, 0x12, 0xA7, 0x6D, 0x80, 0x55,
++0x7B, 0x01, 0x7A, 0x9A, 0x79, 0x37, 0x90, 0x9A,
++0x64, 0x12, 0x82, 0x27, 0x7A, 0x9A, 0x79, 0x4D,
++0x90, 0x9A, 0x67, 0x12, 0x82, 0x27, 0x90, 0x9A,
++0x5E, 0xE0, 0x75, 0xF0, 0x38, 0xA4, 0x24, 0x63,
++0xF9, 0x74, 0x93, 0x35, 0xF0, 0xFA, 0x90, 0x9A,
++0x6A, 0x12, 0x82, 0x27, 0xE4, 0x90, 0x9A, 0x6D,
++0xF0, 0xA3, 0xF0, 0x7A, 0x9A, 0x79, 0x3D, 0x12,
++0x8A, 0x45, 0x80, 0x07, 0x90, 0x06, 0x33, 0xE0,
++0x44, 0x05, 0xF0, 0x90, 0x9A, 0x5F, 0xE0, 0x04,
++0xF0, 0x02, 0xEF, 0xDF, 0x90, 0x9A, 0x5E, 0xE0,
++0x04, 0xF0, 0x02, 0xEF, 0xC0, 0x90, 0x9A, 0x60,
++0xE0, 0xFF, 0x22, 0x90, 0x9A, 0x5D, 0xE0, 0xFF,
++0xC3, 0x22, 0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x9A,
++0x5D, 0xE0, 0x04, 0xF0, 0x22, 0x7D, 0x01, 0x7E,
++0x00, 0x7F, 0x10, 0x12, 0x83, 0xDC, 0xEF, 0x22,
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++0x9A, 0x42, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x90,
++0x98, 0x36, 0xE0, 0xFF, 0xB4, 0x02, 0x07, 0x71,
++0x17, 0x74, 0x08, 0xF0, 0x80, 0x09, 0xEF, 0xB4,
++0x04, 0x05, 0x71, 0x17, 0x74, 0x10, 0xF0, 0x90,
++0x9A, 0x42, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x64,
++0x02, 0x4E, 0x60, 0x08, 0xEF, 0x64, 0x01, 0x4E,
++0x60, 0x02, 0x41, 0xED, 0x90, 0x94, 0x9A, 0x71,
++0x67, 0x90, 0x9A, 0xCF, 0xEE, 0xF0, 0xA3, 0xEF,
++0xF0, 0x7E, 0x00, 0x7F, 0x28, 0x7D, 0x00, 0x7B,
++0x01, 0x7A, 0x9A, 0x79, 0x65, 0x12, 0x04, 0x80,
++0x7E, 0x00, 0x7F, 0x40, 0x7D, 0x00, 0x7B, 0x01,
++0x7A, 0x9A, 0x79, 0x8D, 0x12, 0x04, 0x80, 0x90,
++0x9A, 0x42, 0xE0, 0x70, 0x04, 0xA3, 0xE0, 0x64,
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++0x94, 0x75, 0x47, 0x6A, 0x75, 0x48, 0x10, 0x7B,
++0x01, 0x7A, 0x9A, 0x79, 0xD1, 0x12, 0xEE, 0xAE,
++0x75, 0x46, 0x94, 0x75, 0x47, 0x09, 0x75, 0x48,
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++0x71, 0x1F, 0x90, 0x8F, 0x40, 0xF0, 0x7A, 0x9A,
++0x79, 0xD1, 0x12, 0x4C, 0x23, 0x75, 0x45, 0x01,
++0x75, 0x46, 0x9A, 0x75, 0x47, 0x8D, 0x80, 0x24,
++0x71, 0x28, 0x74, 0x10, 0x71, 0x42, 0x90, 0x91,
++0x8C, 0x71, 0x0F, 0x90, 0x91, 0x8F, 0x71, 0x1F,
++0x90, 0x91, 0x92, 0xF0, 0x7A, 0x94, 0x79, 0x09,
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++0x90, 0x94, 0x3F, 0xE0, 0x54, 0x30, 0xFF, 0xC4,
++0x54, 0x0F, 0x71, 0x07, 0x75, 0x46, 0x9A, 0x75,
++0x47, 0x65, 0x71, 0x32, 0xE0, 0x44, 0x10, 0xF0,
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++0x90, 0x9A, 0x6B, 0xE0, 0x54, 0x03, 0x71, 0x07,
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++0x01, 0x7B, 0x01, 0x7A, 0x9A, 0x79, 0x44, 0x31,
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++0x08, 0xF0, 0x80, 0x71, 0x90, 0x9A, 0x64, 0xE0,
++0xFF, 0xC3, 0x94, 0x04, 0x50, 0x61, 0x90, 0x95,
++0x63, 0xEF, 0xF0, 0x75, 0x45, 0x01, 0x75, 0x46,
++0x9A, 0x75, 0x47, 0x44, 0x75, 0x48, 0x20, 0x7B,
++0x01, 0x7A, 0x95, 0x79, 0x43, 0x12, 0x69, 0xF5,
++0x90, 0x9A, 0x64, 0xE0, 0xFF, 0x90, 0x98, 0x36,
++0xE0, 0xFD, 0x7B, 0x01, 0x7A, 0x9A, 0x79, 0x44,
++0x12, 0x9E, 0x7E, 0x90, 0x95, 0x63, 0xE0, 0x14,
++0x60, 0x12, 0x14, 0x60, 0x17, 0x14, 0x60, 0x1C,
++0x24, 0x03, 0x70, 0x29, 0x51, 0xF2, 0x7A, 0x95,
++0x79, 0x73, 0x80, 0x16, 0x51, 0xF2, 0x7A, 0x95,
++0x79, 0x7B, 0x80, 0x0E, 0x51, 0xF2, 0x7A, 0x95,
++0x79, 0x83, 0x80, 0x06, 0x51, 0xF2, 0x7A, 0x95,
++0x79, 0x8B, 0x12, 0x9C, 0x5E, 0x80, 0x06, 0x90,
++0x95, 0x63, 0x74, 0x05, 0xF0, 0xD0, 0xD0, 0x92,
++0xAF, 0x22, 0x7B, 0x01, 0x7A, 0x94, 0x79, 0x7A,
++0x90, 0x9C, 0x90, 0x12, 0x82, 0x27, 0x90, 0x98,
++0x36, 0xE0, 0x90, 0x9C, 0x93, 0xF0, 0x22, 0x90,
++0x9A, 0x64, 0xF0, 0x75, 0x45, 0x01, 0x22, 0x12,
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++0x9A, 0xCD, 0x74, 0x80, 0xF0, 0xA3, 0x22, 0x12,
++0x82, 0x27, 0x90, 0x9A, 0xCF, 0xA3, 0xE0, 0x22,
++0x90, 0x9A, 0xCF, 0xA3, 0xE0, 0xFB, 0x90, 0x92,
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++0x9A, 0x79, 0x44, 0x12, 0x69, 0xF5, 0x90, 0x06,
++0x33, 0x22, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xF0,
++0xFD, 0xFC, 0xFF, 0xFE, 0x12, 0x71, 0xD4, 0x7B,
++0x01, 0x7A, 0x94, 0x79, 0x9C, 0x22, 0x90, 0x93,
++0x61, 0x12, 0x04, 0x6E, 0xE0, 0x22, 0x90, 0x9A,
++0x5E, 0xE0, 0xFF, 0x75, 0xF0, 0x38, 0x22, 0xE0,
++0xFE, 0xA3, 0xE0, 0xFD, 0xED, 0xFF, 0x22, 0xE0,
++0x24, 0x3D, 0xF5, 0x82, 0xE4, 0x34, 0x9A, 0x22,
++0xE0, 0x24, 0x37, 0xF5, 0x82, 0xE4, 0x34, 0x9A,
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++0x9A, 0x9E, 0x12, 0x8B, 0xE0, 0x75, 0x48, 0x10,
++0x7B, 0x01, 0x7A, 0x93, 0x79, 0xD1, 0x12, 0x69,
++0xF5, 0x90, 0x9A, 0x9B, 0x12, 0x8B, 0xE0, 0x75,
++0x48, 0x10, 0x7B, 0x01, 0x7A, 0x93, 0x79, 0xE1,
++0x12, 0x69, 0xF5, 0x90, 0x9A, 0xA1, 0x12, 0x04,
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++0x01, 0xC7, 0x74, 0x0B, 0x12, 0xA7, 0x6D, 0x90,
++0x9A, 0x38, 0xE0, 0xFF, 0x22, 0x90, 0x9A, 0x37,
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++0xE4, 0xFE, 0xED, 0x30, 0xE1, 0x11, 0x90, 0x01,
++0x3F, 0xE0, 0x30, 0xE2, 0x0A, 0x74, 0x04, 0xF0,
++0x90, 0x01, 0xC7, 0x74, 0x23, 0xF0, 0x0E, 0xED,
++0x30, 0xE0, 0x24, 0xEF, 0x30, 0xE6, 0x08, 0x90,
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++0x01, 0xC7, 0x74, 0x23, 0xF0, 0x7E, 0x01, 0xAF,
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++0x22, 0x12, 0x87, 0xED, 0x2E, 0x90, 0x98, 0x37,
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++0x98, 0x38, 0x12, 0x87, 0xE6, 0xFF, 0xED, 0x2F,
++0x90, 0x98, 0x39, 0x12, 0x87, 0xA3, 0xFF, 0xED,
++0x2F, 0x90, 0x98, 0x3A, 0x12, 0x87, 0xD1, 0xFF,
++0xED, 0x2F, 0x90, 0x98, 0x3B, 0x12, 0x87, 0x9B,
++0xFF, 0xED, 0x2F, 0x90, 0x98, 0x3C, 0x12, 0x87,
++0xD8, 0x90, 0x98, 0x3D, 0xF0, 0x22, 0x12, 0x87,
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++0x58, 0xFF, 0xED, 0x2F, 0x90, 0x98, 0x46, 0x12,
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++0x98, 0x47, 0xF0, 0x22, 0xEF, 0x60, 0x08, 0x90,
++0x98, 0x38, 0xE0, 0xFF, 0x12, 0x8D, 0x55, 0x22,
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++0x90, 0x99, 0xB6, 0x12, 0x82, 0x27, 0xB1, 0x48,
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++0xB1, 0x36, 0xEF, 0x12, 0x02, 0x4C, 0x90, 0x06,
++0x79, 0xB1, 0x36, 0x90, 0x00, 0x01, 0xEF, 0x12,
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++0x02, 0x12, 0x02, 0x5E, 0x90, 0x06, 0x7B, 0xE0,
++0x90, 0x00, 0x03, 0x02, 0x02, 0x5E, 0xE0, 0xFF,
++0x90, 0x99, 0xB6, 0x02, 0x82, 0x1E, 0xF0, 0xA3,
++0x74, 0x80, 0xF0, 0x7F, 0x01, 0x7E, 0x00, 0x22,
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++0x12, 0x82, 0x27, 0xE4, 0x90, 0x99, 0xB5, 0xF0,
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++0x04, 0x50, 0x2B, 0xEF, 0x75, 0xF0, 0x04, 0xA4,
++0xFF, 0x90, 0x99, 0xB2, 0x12, 0x82, 0x1E, 0xE9,
++0x2F, 0xF9, 0xEA, 0x35, 0xF0, 0xFA, 0x90, 0x99,
++0xB1, 0xE0, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x02,
++0xFF, 0x90, 0x99, 0xB5, 0xE0, 0x2F, 0xFF, 0xB1,
++0x00, 0x12, 0xC1, 0x34, 0x80, 0xCB, 0x22, 0xD3,
++0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x9A,
++0x5A, 0xEF, 0xF0, 0x90, 0x93, 0x06, 0xE0, 0xFF,
++0x12, 0x7B, 0x07, 0x74, 0x10, 0x2F, 0xFF, 0x90,
++0x9A, 0x5A, 0xE0, 0x25, 0xE0, 0x25, 0xE0, 0x2F,
++0xFF, 0x12, 0x8D, 0xC3, 0x75, 0x48, 0x04, 0x7B,
++0x01, 0x7A, 0x9B, 0x79, 0x1D, 0x12, 0x69, 0xF5,
++0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF,
++0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x9B, 0x0D, 0xE0,
++0xFE, 0x90, 0x9B, 0x0A, 0xE0, 0xC3, 0x9E, 0x40,
++0x04, 0x7F, 0x00, 0x80, 0x0E, 0xEF, 0x60, 0x05,
++0xD3, 0x94, 0x0E, 0x40, 0x04, 0x7F, 0x00, 0x80,
++0x02, 0x7F, 0x01, 0xD0, 0xD0, 0x92, 0xAF, 0x22,
++0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90,
++0x9A, 0x5A, 0xEF, 0xF0, 0x12, 0x76, 0x9B, 0xBF,
++0x01, 0x27, 0x90, 0x06, 0x32, 0xE0, 0x44, 0x08,
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++0x13, 0x74, 0x07, 0xF0, 0x7B, 0x18, 0x7D, 0x01,
++0x12, 0x66, 0xDB, 0x90, 0x9A, 0x5B, 0xEE, 0xF0,
++0xA3, 0xEF, 0xF0, 0x90, 0x04, 0x1F, 0x74, 0x20,
++0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xE4, 0xFD,
++0xFC, 0x90, 0x01, 0x1D, 0xE0, 0xFE, 0x90, 0x01,
++0x1C, 0xD1, 0xF3, 0x3E, 0x90, 0x9C, 0xBF, 0xF0,
++0xA3, 0xEF, 0xD1, 0xD3, 0xE0, 0x24, 0x00, 0xFF,
++0xEA, 0x3E, 0x90, 0x9C, 0xC1, 0xF0, 0xA3, 0xEF,
++0xF0, 0xD1, 0xCA, 0x90, 0x9C, 0xBF, 0xE0, 0xFA,
++0xA3, 0xE0, 0xFB, 0xB5, 0x07, 0x06, 0xEA, 0xB5,
++0x06, 0x02, 0x80, 0x3D, 0xD1, 0xCA, 0xD3, 0xEB,
++0x9F, 0xEA, 0x9E, 0x40, 0x0E, 0x90, 0x9C, 0xC0,
++0xE0, 0x9F, 0xFD, 0x90, 0x9C, 0xBF, 0xE0, 0x9E,
++0xFC, 0x80, 0x26, 0xD1, 0xCA, 0xC3, 0x90, 0x9C,
++0xC0, 0xE0, 0x9F, 0x90, 0x9C, 0xBF, 0xE0, 0x9E,
++0x50, 0x17, 0x12, 0xA7, 0xEF, 0x90, 0x9C, 0xC2,
++0xE0, 0x9F, 0xFF, 0x90, 0x9C, 0xC1, 0xE0, 0x9E,
++0xFE, 0xC3, 0xE4, 0x9F, 0xFD, 0x74, 0x40, 0x9E,
++0xFC, 0xD3, 0xED, 0x94, 0x00, 0xEC, 0x94, 0x38,
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++0xF0, 0x22, 0x90, 0x9C, 0xC1, 0xE0, 0xFE, 0xA3,
++0xE0, 0xFF, 0x22, 0xF0, 0x90, 0x01, 0x1F, 0xE0,
++0xFE, 0x90, 0x01, 0x1E, 0x22, 0x74, 0x01, 0x2D,
++0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0,
++0xFE, 0x74, 0x00, 0x2D, 0xF5, 0x82, 0xE4, 0x34,
++0xFB, 0xF5, 0x83, 0xE0, 0x7A, 0x00, 0x24, 0x00,
++0xFF, 0xEA, 0x22, 0xED, 0x14, 0x60, 0x06, 0x04,
++0x70, 0x03, 0x7F, 0x01, 0x22, 0x7F, 0x01, 0x22,
++0x12, 0xE7, 0x60, 0xA3, 0xED, 0xF0, 0x90, 0x95,
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++0xE4, 0x90, 0x9A, 0x37, 0xF0, 0xF1, 0x5A, 0x50,
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++0xF5, 0x82, 0xE4, 0x34, 0x95, 0xF5, 0x83, 0xE0,
++0x6F, 0x60, 0x03, 0x7F, 0x00, 0x22, 0x90, 0x9A,
++0x37, 0xE0, 0x04, 0xF0, 0x80, 0xD7, 0x7F, 0x00,
++0x22, 0x90, 0x06, 0x32, 0xE0, 0x44, 0x40, 0xF0,
++0xE4, 0x90, 0x95, 0xA5, 0xF0, 0xA3, 0xF0, 0x7F,
++0x01, 0x22, 0x90, 0x9A, 0x37, 0xE0, 0xFD, 0xC3,
++0x94, 0x02, 0x22, 0x12, 0xE7, 0x60, 0xA3, 0xED,
++0xF0, 0xE4, 0xA3, 0xF0, 0xF1, 0x5A, 0x50, 0x22,
++0x12, 0xAF, 0x23, 0xED, 0x24, 0x1C, 0x12, 0xAF,
++0xCE, 0x90, 0x9A, 0x37, 0xE0, 0x24, 0xC7, 0xF5,
++0x82, 0xE4, 0x34, 0x95, 0xF5, 0x83, 0xE0, 0xB5,
++0x07, 0x1D, 0x90, 0x9A, 0x37, 0xE0, 0x04, 0xF0,
++0x80, 0xDA, 0x90, 0x06, 0x32, 0xE0, 0x44, 0x80,
++0xF0, 0x90, 0x01, 0xC7, 0x74, 0x30, 0xF0, 0x7F,
++0x01, 0x12, 0xAD, 0x64, 0x7F, 0x01, 0x22, 0x7F,
++0x00, 0x22, 0x12, 0xE7, 0x60, 0xE4, 0xA3, 0xF0,
++0x90, 0x9A, 0x36, 0xE0, 0xFD, 0xC3, 0x94, 0x04,
++0x50, 0x29, 0x90, 0x9A, 0x35, 0xE0, 0x24, 0x10,
++0x12, 0xA6, 0x2E, 0xFE, 0x12, 0xAF, 0xCF, 0x90,
++0x9A, 0x36, 0xE0, 0x24, 0x9F, 0xF5, 0x82, 0xE4,
++0x34, 0x95, 0xF5, 0x83, 0xE0, 0x6F, 0x60, 0x03,
++0x7F, 0x00, 0x22, 0x90, 0x9A, 0x36, 0xE0, 0x04,
++0xF0, 0x80, 0xCD, 0x7F, 0x01, 0x22, 0xD3, 0x10,
++0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x12, 0x7A, 0x65,
++0xEF, 0x64, 0x01, 0x60, 0x05, 0x75, 0x14, 0x01,
++0x80, 0x25, 0x90, 0x88, 0x31, 0x12, 0x97, 0xD9,
++0x30, 0xE0, 0x05, 0x75, 0x14, 0x02, 0x80, 0x17,
++0x90, 0x88, 0x38, 0xE0, 0xD3, 0x94, 0x04, 0x40,
++0x05, 0x75, 0x14, 0x08, 0x80, 0x09, 0x90, 0x01,
++0xB8, 0xE4, 0xF0, 0x7F, 0x01, 0x80, 0x0E, 0x90,
++0x01, 0xB9, 0x74, 0x02, 0xF0, 0x90, 0x01, 0xB8,
++0xE5, 0x14, 0xF0, 0x7F, 0x00, 0xD0, 0xD0, 0x92,
++0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0,
++0xD0, 0x12, 0x7A, 0x65, 0xEF, 0x64, 0x01, 0x60,
++0x05, 0x75, 0x15, 0x01, 0x80, 0x75, 0x90, 0x88,
++0x3A, 0xE0, 0xFF, 0x54, 0x03, 0x60, 0x05, 0x75,
++0x15, 0x02, 0x80, 0x67, 0x90, 0x88, 0x38, 0xE0,
++0xFE, 0xE4, 0xC3, 0x9E, 0x50, 0x05, 0x75, 0x15,
++0x04, 0x80, 0x58, 0xEF, 0x30, 0xE2, 0x05, 0x75,
++0x15, 0x08, 0x80, 0x4F, 0x90, 0x88, 0x3A, 0xE0,
++0x30, 0xE4, 0x05, 0x75, 0x15, 0x10, 0x80, 0x43,
++0x90, 0x88, 0x32, 0xE0, 0x13, 0x13, 0x54, 0x3F,
++0x20, 0xE0, 0x05, 0x75, 0x15, 0x20, 0x80, 0x33,
++0x90, 0x88, 0x9C, 0xE0, 0x60, 0x05, 0x75, 0x15,
++0x80, 0x80, 0x28, 0x90, 0x06, 0x62, 0xE0, 0x30,
++0xE1, 0x05, 0x75, 0x15, 0x11, 0x80, 0x1C, 0x90,
++0x06, 0x62, 0xE0, 0x30, 0xE0, 0x0C, 0xE0, 0x54,
++0xFC, 0xFF, 0xBF, 0x80, 0x05, 0x75, 0x15, 0x12,
++0x80, 0x09, 0x90, 0x01, 0xB8, 0xE4, 0xF0, 0x7F,
++0x01, 0x80, 0x0E, 0x90, 0x01, 0xB9, 0x74, 0x04,
++0xF0, 0x90, 0x01, 0xB8, 0xE5, 0x15, 0xF0, 0x7F,
++0x00, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x93,
++0x08, 0xE0, 0xC3, 0x13, 0x20, 0xE0, 0x36, 0x90,
++0x02, 0x87, 0xE0, 0x60, 0x02, 0x80, 0x08, 0x90,
++0x01, 0x00, 0xE0, 0x64, 0x3F, 0x60, 0x05, 0x75,
++0x0D, 0x01, 0x80, 0x34, 0x90, 0x93, 0x31, 0xE0,
++0x30, 0xE0, 0x05, 0x75, 0x0D, 0x08, 0x80, 0x28,
++0x90, 0x02, 0x86, 0xE0, 0x20, 0xE1, 0x02, 0x80,
++0x07, 0x90, 0x02, 0x86, 0xE0, 0x30, 0xE3, 0x05,
++0x75, 0x0D, 0x04, 0x80, 0x13, 0x90, 0x04, 0x1D,
++0xE0, 0x60, 0x05, 0x75, 0x0D, 0x40, 0x80, 0x08,
++0x90, 0x01, 0xB8, 0xE4, 0xF0, 0x7F, 0x01, 0x22,
++0x90, 0x01, 0xB9, 0x74, 0x08, 0xF0, 0x90, 0x01,
++0xB8, 0xE5, 0x0D, 0xF0, 0x7F, 0x00, 0x22, 0x90,
++0x88, 0x31, 0xE0, 0x30, 0xE0, 0x03, 0x12, 0xBF,
++0xD8, 0x22, 0x90, 0x88, 0x8D, 0x74, 0x18, 0xF0,
++0xA3, 0xF0, 0xA3, 0xE4, 0xF0, 0xA3, 0x74, 0x64,
++0xF0, 0xA3, 0x74, 0x05, 0xF0, 0xA3, 0xF0, 0x22,
++0x12, 0xB7, 0xE0, 0x9F, 0x40, 0x40, 0x90, 0x88,
++0x50, 0xE0, 0x04, 0xF0, 0x90, 0x88, 0x92, 0xE0,
++0xFF, 0x90, 0x88, 0x50, 0xE0, 0xD3, 0x9F, 0x50,
++0x2D, 0x90, 0x88, 0x48, 0xE0, 0x24, 0x08, 0xF0,
++0x90, 0x88, 0x3F, 0x31, 0x99, 0x33, 0x33, 0x33,
++0x54, 0xF8, 0xFF, 0x90, 0x88, 0x3E, 0xE0, 0x2F,
++0x90, 0x88, 0x4F, 0xF0, 0xFB, 0x90, 0x88, 0x48,
++0xE0, 0xFF, 0xA3, 0xE0, 0xFD, 0x90, 0x92, 0x98,
++0x74, 0x03, 0xF0, 0x12, 0x6E, 0x2F, 0x22, 0xFF,
++0xA3, 0xE0, 0x75, 0xF0, 0x03, 0xA4, 0x24, 0xFE,
++0x22, 0x90, 0x93, 0x08, 0xE0, 0x30, 0xE0, 0x09,
++0x90, 0x01, 0x3B, 0xE0, 0x30, 0xE4, 0x02, 0x31,
++0xB2, 0x22, 0x7D, 0x02, 0x7F, 0x02, 0x12, 0x7C,
++0x7E, 0x7D, 0x01, 0x7F, 0x02, 0x02, 0x7C, 0x7E,
++0x90, 0x05, 0x63, 0xE0, 0x90, 0x88, 0x89, 0xF0,
++0x90, 0x05, 0x62, 0xE0, 0x90, 0x88, 0x8A, 0xF0,
++0x90, 0x05, 0x61, 0xE0, 0x90, 0x88, 0x8B, 0xF0,
++0x90, 0x05, 0x60, 0xE0, 0x90, 0x88, 0x8C, 0xF0,
++0x90, 0x88, 0x32, 0xE0, 0x44, 0x80, 0xF0, 0x22,
++0x90, 0x86, 0xB6, 0xE0, 0xFF, 0x90, 0x9C, 0xA7,
++0xE0, 0xFB, 0x90, 0x92, 0x13, 0x74, 0x0A, 0xF0,
++0x7D, 0x01, 0x12, 0x66, 0xDB, 0x90, 0x9C, 0xA8,
++0xEE, 0xF0, 0xFC, 0xA3, 0xEF, 0xF0, 0xFD, 0x90,
++0x9C, 0xA6, 0xE0, 0xFF, 0x90, 0x8A, 0x95, 0x22,
++0xEF, 0x75, 0xF0, 0x0A, 0xA4, 0x24, 0x93, 0xF5,
++0x82, 0xE4, 0x34, 0x9B, 0xF5, 0x83, 0x22, 0xE0,
++0xFF, 0x24, 0x10, 0xF5, 0x82, 0xE4, 0x34, 0x93,
++0xF5, 0x83, 0xE0, 0x90, 0x01, 0xB2, 0xF0, 0x74,
++0x15, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x93, 0xF5,
++0x83, 0xE0, 0x90, 0x01, 0xB3, 0xF0, 0xE0, 0x22,
++0xE0, 0xFF, 0x24, 0x1A, 0xF5, 0x82, 0xE4, 0x34,
++0x93, 0xF5, 0x83, 0xE0, 0x90, 0x01, 0xB0, 0xF0,
++0x74, 0x1F, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x93,
++0xF5, 0x83, 0xE0, 0x90, 0x01, 0xB1, 0xF0, 0x22,
++0x90, 0x88, 0x48, 0xE0, 0xFF, 0xA3, 0xE0, 0xFD,
++0x90, 0x88, 0x4F, 0xE0, 0xFB, 0x90, 0x92, 0x98,
++0x22, 0x90, 0x8A, 0x77, 0xE0, 0xFE, 0xA3, 0xE0,
++0xFF, 0xF5, 0x82, 0x8E, 0x83, 0x02, 0x04, 0x7E,
++0xF0, 0xA3, 0xEF, 0xF0, 0x74, 0x02, 0x2D, 0xF5,
++0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x54,
++0x0F, 0x33, 0x33, 0x33, 0x54, 0xF8, 0xFF, 0x90,
++0x98, 0x6C, 0xE0, 0x22, 0x90, 0x9C, 0xA6, 0xE0,
++0xFF, 0x90, 0x8A, 0xC7, 0xE0, 0xFC, 0xA3, 0xE0,
++0xFD, 0xF5, 0x82, 0x8C, 0x83, 0x22, 0xA3, 0xE0,
++0x24, 0x28, 0xF9, 0xE4, 0x34, 0xFC, 0xFA, 0x22,
++0x90, 0x88, 0x28, 0xE0, 0x24, 0x01, 0xFF, 0x90,
++0x88, 0x27, 0xE0, 0x34, 0x00, 0xFE, 0xC3, 0x22,
++0x90, 0x9C, 0x01, 0xA3, 0xE0, 0x24, 0x04, 0xF5,
++0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x22,
++0xEE, 0x8F, 0xF0, 0x12, 0x02, 0xE7, 0x90, 0x88,
++0x27, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x22, 0x74,
++0x03, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5,
++0x83, 0xE0, 0x54, 0x03, 0xFE, 0x22, 0xE0, 0x90,
++0x01, 0xBA, 0xF0, 0x90, 0x88, 0x38, 0xE0, 0x90,
++0x01, 0xBB, 0xF0, 0x22, 0xFF, 0x90, 0x9A, 0x3B,
++0xE0, 0x34, 0x00, 0xFE, 0x22, 0x7E, 0x00, 0x7F,
++0x04, 0x7D, 0x00, 0x7B, 0x01, 0x7A, 0x93, 0x79,
++0x08, 0x22, 0x90, 0x9C, 0x42, 0x12, 0x82, 0x27,
++0xE4, 0x90, 0x9C, 0x45, 0xF0, 0xA3, 0x22, 0x24,
++0x28, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83,
++0xE0, 0x22, 0xFF, 0xEC, 0x3E, 0x90, 0x9A, 0x3D,
++0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0xCF, 0x34, 0x00,
++0x90, 0x9A, 0x39, 0xF0, 0xA3, 0xEF, 0xF0, 0x22,
++0xE4, 0xFF, 0x12, 0x8D, 0x1E, 0x90, 0x04, 0x1F,
++0x74, 0x20, 0x22, 0x90, 0x98, 0x6B, 0xE0, 0xFF,
++0x90, 0x98, 0x6A, 0xE0, 0x4F, 0x22, 0x74, 0x21,
++0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83,
++0x22, 0xFB, 0xC3, 0xED, 0x9B, 0xFD, 0xEC, 0x94,
++0x00, 0xFC, 0x22, 0x24, 0xA8, 0xFF, 0xE4, 0x34,
++0x01, 0xFE, 0x7B, 0x01, 0x22, 0x74, 0xF9, 0x2E,
++0xF5, 0x82, 0xE4, 0x34, 0x95, 0x22, 0x90, 0x88,
++0x38, 0xE0, 0x90, 0x9B, 0x22, 0xF0, 0x22, 0x90,
++0x9B, 0xFD, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0x22,
++0x90, 0x9B, 0xFF, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF,
++0x22, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x02, 0x87,
++0xE0, 0x22, 0x78, 0x3D, 0x7C, 0x9A, 0x7D, 0x01,
++0x7B, 0xFF, 0x22, 0xF5, 0x82, 0xE4, 0x34, 0xFC,
++0xF5, 0x83, 0xE0, 0x22, 0x7D, 0x02, 0x7F, 0x02,
++0x02, 0x04, 0x7E, 0x90, 0x88, 0x33, 0xE0, 0x54,
++0xFE, 0xF0, 0x22, 0x90, 0x9A, 0x37, 0xF0, 0xA3,
++0xEF, 0xF0, 0x22, 0x7E, 0x00, 0x7F, 0x10, 0x02,
++0x01, 0xE0, 0x90, 0x00, 0x08, 0xE0, 0x54, 0xEF,
++0xF0, 0x22, 0x7F, 0xF9, 0x7E, 0x01, 0x02, 0x5F,
++0xA6, 0x00, 0xEF, 0x02
++};
++
++u32 array_length_mp_8723d_fw_wowlan = 31756;
++
++#endif /*CONFIG_WOWLAN*/
++
++#endif
++
++#endif /* end of LOAD_FW_HEADER_FROM_DRIVER */
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/hal8723d_fw.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/hal8723d_fw.h
+new file mode 100644
+index 000000000..991788787
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/hal8723d_fw.h
+@@ -0,0 +1,40 @@
++/******************************************************************************
++*
++* Copyright(c) 2012 - 2017 Realtek Corporation.
++*
++* This program is free software; you can redistribute it and/or modify it
++* under the terms of version 2 of the GNU General Public License as
++* published by the Free Software Foundation.
++*
++* This program is distributed in the hope that it will be useful, but WITHOUT
++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++* more details.
++*
++******************************************************************************/
++
++#ifdef CONFIG_RTL8723D
++
++#ifndef _FW_HEADER_8723D_H
++#define _FW_HEADER_8723D_H
++
++#ifdef LOAD_FW_HEADER_FROM_DRIVER
++#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))
++extern u8 array_mp_8723d_fw_ap[25882];
++extern u32 array_length_mp_8723d_fw_ap;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE))
++extern u8 array_mp_8723d_fw_nic[29262];
++extern u32 array_length_mp_8723d_fw_nic;
++#ifdef CONFIG_WOWLAN
++extern u8 array_mp_8723d_fw_wowlan[31756];
++extern u32 array_length_mp_8723d_fw_wowlan;
++#endif /*CONFIG_WOWLAN*/
++#endif
++#endif /* end of LOAD_FW_HEADER_FROM_DRIVER */
++
++#endif
++
++#endif
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_cmd.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_cmd.c
+new file mode 100644
+index 000000000..e08df1ca7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_cmd.c
+@@ -0,0 +1,476 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTL8723D_CMD_C_
++
++#include <rtl8723d_hal.h>
++#include "hal_com_h2c.h"
++
++#define MAX_H2C_BOX_NUMS	4
++#define MESSAGE_BOX_SIZE		4
++
++#define RTL8723D_MAX_CMD_LEN	7
++#define RTL8723D_EX_MESSAGE_BOX_SIZE	4
++
++static u8 _is_fw_read_cmd_down(_adapter *padapter, u8 msgbox_num)
++{
++	u8	read_down = _FALSE;
++	int	retry_cnts = 100;
++
++	u8 valid;
++
++	/* RTW_INFO(" _is_fw_read_cmd_down ,reg_1cc(%x),msg_box(%d)...\n",rtw_read8(padapter,REG_HMETFR),msgbox_num); */
++
++	do {
++		valid = rtw_read8(padapter, REG_HMETFR) & BIT(msgbox_num);
++		if (0 == valid)
++			read_down = _TRUE;
++		else
++			rtw_msleep_os(1);
++	} while ((!read_down) && (retry_cnts--));
++
++	return read_down;
++
++}
++
++
++/*****************************************
++* H2C Msg format :
++*| 31 - 8		|7-5	| 4 - 0	|
++*| h2c_msg	|Class	|CMD_ID	|
++*| 31-0						|
++*| Ext msg					|
++*
++******************************************/
++s32 FillH2CCmd8723D(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
++{
++	u8 h2c_box_num;
++	u8 h2c[RTL8723D_MAX_CMD_LEN + 1] = {0};
++	u32	msgbox_addr;
++	u32 msgbox_ex_addr = 0;
++	u32	h2c_cmd = 0;
++	u32	h2c_cmd_ex = 0;
++	s32 ret = _FAIL;
++	PHAL_DATA_TYPE pHalData;		
++	struct dvobj_priv *psdpriv = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
++
++
++	padapter = GET_PRIMARY_ADAPTER(padapter);
++	pHalData = GET_HAL_DATA(padapter);
++#ifdef DBG_CHECK_FW_PS_STATE
++#ifdef DBG_CHECK_FW_PS_STATE_H2C
++	if (rtw_fw_ps_state(padapter) == _FAIL) {
++		RTW_INFO("%s: h2c doesn't leave 32k ElementID=%02x\n", __FUNCTION__, ElementID);
++		pdbgpriv->dbg_h2c_leave32k_fail_cnt++;
++	}
++
++	/* RTW_INFO("H2C ElementID=%02x , pHalData->LastHMEBoxNum=%02x\n", ElementID, pHalData->LastHMEBoxNum); */
++#endif /* DBG_CHECK_FW_PS_STATE_H2C */
++#endif /* DBG_CHECK_FW_PS_STATE */
++	_enter_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL);
++
++	if (!pCmdBuffer)
++		goto exit;
++	if (CmdLen > RTL8723D_MAX_CMD_LEN)
++		goto exit;
++	if (rtw_is_surprise_removed(padapter))
++		goto exit;
++
++	h2c[0] = ElementID;
++	_rtw_memcpy(h2c + 1, pCmdBuffer, CmdLen);
++	
++	/* pay attention to if  race condition happened in  H2C cmd setting. */
++	do {
++		h2c_box_num = pHalData->LastHMEBoxNum;
++
++		if (!_is_fw_read_cmd_down(padapter, h2c_box_num)) {
++			RTW_INFO(" fw read cmd failed...\n");
++#ifdef DBG_CHECK_FW_PS_STATE
++			RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
++				, rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
++#endif /* DBG_CHECK_FW_PS_STATE */
++			/* RTW_INFO(" 0x1c0: 0x%8x\n", rtw_read32(padapter, 0x1c0)); */
++			/* RTW_INFO(" 0x1c4: 0x%8x\n", rtw_read32(padapter, 0x1c4)); */
++			goto exit;
++		}
++
++		/* Write Ext command (byte 4~7) */
++		msgbox_ex_addr = REG_HMEBOX_EXT0_8723D + (h2c_box_num * RTL8723D_EX_MESSAGE_BOX_SIZE);
++		_rtw_memcpy((u8 *)(&h2c_cmd_ex), h2c + 4, RTL8723D_EX_MESSAGE_BOX_SIZE);
++		h2c_cmd_ex = le32_to_cpu(h2c_cmd_ex);
++		rtw_write32(padapter, msgbox_ex_addr, h2c_cmd_ex);
++		/* Write command (byte 0~3) */
++		msgbox_addr = REG_HMEBOX_0_8723D + (h2c_box_num * MESSAGE_BOX_SIZE);
++		_rtw_memcpy((u8 *)(&h2c_cmd), h2c, 4);
++		h2c_cmd = le32_to_cpu(h2c_cmd);
++		rtw_write32(padapter, msgbox_addr, h2c_cmd);
++
++		/* RTW_INFO("MSG_BOX:%d, CmdLen(%d), CmdID(0x%x), reg:0x%x =>h2c_cmd:0x%.8x, reg:0x%x =>h2c_cmd_ex:0x%.8x\n" */
++		/*	,pHalData->LastHMEBoxNum , CmdLen, ElementID, msgbox_addr, h2c_cmd, msgbox_ex_addr, h2c_cmd_ex); */
++
++		/* update last msg box number */
++		pHalData->LastHMEBoxNum = (h2c_box_num + 1) % MAX_H2C_BOX_NUMS;
++
++	} while (0);
++
++	ret = _SUCCESS;
++
++exit:
++
++	_exit_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL);
++
++
++	return ret;
++}
++
++/*
++ * Description: Get the reserved page number in Tx packet buffer.
++ * Retrun value: the page number.
++ * 2012.08.09, by tynli.
++ *   */
++u8 GetTxBufferRsvdPageNum8723D(_adapter *padapter, bool wowlan)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	u8	RsvdPageNum = 0;
++	/* default reseved 1 page for the IC type which is undefined. */
++	u8	TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8723D;
++
++	rtw_hal_get_def_var(padapter, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&TxPageBndy);
++
++	RsvdPageNum = LAST_ENTRY_OF_TX_PKT_BUFFER_8723D - TxPageBndy + 1;
++
++	return RsvdPageNum;
++}
++
++void rtl8723d_set_FwPwrMode_cmd(PADAPTER padapter, u8 psmode)
++{
++	u8 smart_ps = 0;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	u8 u1H2CPwrModeParm[H2C_PWRMODE_LEN] = {0};
++	u8 PowerState = 0, awake_intvl = 1, rlbm = 0;
++#ifdef CONFIG_P2P
++	struct wifidirect_info *wdinfo = &(padapter->wdinfo);
++#endif /* CONFIG_P2P */
++	u8 allQueueUAPSD = 0;
++
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++	if (psmode == PS_MODE_DTIM)
++		psmode = PS_MODE_MAX;
++#endif /* CONFIG_PLATFORM_INTEL_BYT */
++
++
++	if (pwrpriv->dtim > 0)
++		RTW_INFO("%s(): FW LPS mode = %d, SmartPS=%d, dtim=%d\n", __func__, psmode, pwrpriv->smart_ps, pwrpriv->dtim);
++	else
++		RTW_INFO("%s(): FW LPS mode = %d, SmartPS=%d\n", __func__, psmode, pwrpriv->smart_ps);
++
++	if (psmode == PS_MODE_MIN) {
++		rlbm = 0;
++		awake_intvl = 2;
++		smart_ps = pwrpriv->smart_ps;
++	} else if (psmode == PS_MODE_MAX) {
++		rlbm = 1;
++		awake_intvl = 2;
++		smart_ps = pwrpriv->smart_ps;
++	} else if (psmode == PS_MODE_DTIM) { /* For WOWLAN LPS, DTIM = (awake_intvl - 1) */
++		if (pwrpriv->dtim > 0 && pwrpriv->dtim < 16)
++			awake_intvl = pwrpriv->dtim + 1; /* DTIM = (awake_intvl - 1) */
++		else
++			awake_intvl = 4;/* DTIM=3 */
++
++
++		rlbm = 2;
++		smart_ps = pwrpriv->smart_ps;
++	} else {
++		rlbm = 2;
++		awake_intvl = 4;
++		smart_ps = pwrpriv->smart_ps;
++	}
++
++#ifdef CONFIG_P2P
++	if (!rtw_p2p_chk_state(wdinfo, P2P_STATE_NONE)) {
++		awake_intvl = 2;
++		rlbm = 1;
++	}
++#endif /* CONFIG_P2P */
++
++	if (padapter->registrypriv.wifi_spec == 1) {
++		awake_intvl = 2;
++		rlbm = 1;
++	}
++
++	if (psmode > 0) {
++#ifdef CONFIG_BT_COEXIST
++		if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
++			PowerState = rtw_btcoex_RpwmVal(padapter);
++		else
++#endif /* CONFIG_BT_COEXIST */
++			PowerState = 0x00;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */
++	} else
++		PowerState = 0x0C;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */
++
++	SET_8723D_H2CCMD_PWRMODE_PARM_MODE(u1H2CPwrModeParm, (psmode > 0) ? 1 : 0);
++	SET_8723D_H2CCMD_PWRMODE_PARM_SMART_PS(u1H2CPwrModeParm, smart_ps);
++	SET_8723D_H2CCMD_PWRMODE_PARM_RLBM(u1H2CPwrModeParm, rlbm);
++	SET_8723D_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1H2CPwrModeParm, awake_intvl);
++	SET_8723D_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1H2CPwrModeParm, allQueueUAPSD);
++	SET_8723D_H2CCMD_PWRMODE_PARM_PWR_STATE(u1H2CPwrModeParm, PowerState);
++
++#ifdef CONFIG_BT_COEXIST
++	rtw_btcoex_RecordPwrMode(padapter, u1H2CPwrModeParm, H2C_PWRMODE_LEN);
++#endif /* CONFIG_BT_COEXIST */
++
++	RTW_DBG_DUMP("u1H2CPwrModeParm:",
++		     u1H2CPwrModeParm, H2C_PWRMODE_LEN);
++
++	FillH2CCmd8723D(padapter, H2C_8723D_SET_PWR_MODE, H2C_PWRMODE_LEN, u1H2CPwrModeParm);
++}
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_TDLS_CH_SW
++void rtl8723d_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable)
++{
++	u8	u1H2CSetPwrMode[H2C_PWRMODE_LEN] = {0};
++
++	SET_8723D_H2CCMD_PWRMODE_PARM_MODE(u1H2CSetPwrMode, 1);
++	SET_8723D_H2CCMD_PWRMODE_PARM_RLBM(u1H2CSetPwrMode, 1);
++	SET_8723D_H2CCMD_PWRMODE_PARM_SMART_PS(u1H2CSetPwrMode, 0);
++	SET_8723D_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1H2CSetPwrMode, 0);
++	SET_8723D_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1H2CSetPwrMode, 0);
++	SET_8723D_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(u1H2CSetPwrMode, enable);
++	SET_8723D_H2CCMD_PWRMODE_PARM_PWR_STATE(u1H2CSetPwrMode, 0x0C);
++	FillH2CCmd8723D(padapter, H2C_8723D_SET_PWR_MODE, sizeof(u1H2CSetPwrMode), u1H2CSetPwrMode);
++}
++#endif
++#endif
++
++void rtl8723d_set_FwPsTuneParam_cmd(PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	u8 u1H2CPsTuneParm[H2C_PSTUNEPARAM_LEN] = {0};
++	u8 bcn_to_limit = 10; /* 10 * 100 * awakeinterval (ms) */
++	u8 dtim_timeout = 5; /* ms //wait broadcast data timer */
++	u8 ps_timeout = 20;  /* ms //Keep awake when tx */
++	u8 dtim_period = 3;
++
++	/* RTW_INFO("%s(): FW LPS mode = %d\n", __func__, psmode); */
++
++	SET_8723D_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(u1H2CPsTuneParm, bcn_to_limit);
++	SET_8723D_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(u1H2CPsTuneParm, dtim_timeout);
++	SET_8723D_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(u1H2CPsTuneParm, ps_timeout);
++	SET_8723D_H2CCMD_PSTUNE_PARM_ADOPT(u1H2CPsTuneParm, 1);
++	SET_8723D_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(u1H2CPsTuneParm, dtim_period);
++
++	RTW_DBG_DUMP("u1H2CPsTuneParm:",
++		     u1H2CPsTuneParm, H2C_PSTUNEPARAM_LEN);
++
++	FillH2CCmd8723D(padapter, H2C_8723D_PS_TUNING_PARA, H2C_PSTUNEPARAM_LEN, u1H2CPsTuneParm);
++}
++
++void rtl8723d_download_rsvd_page(PADAPTER padapter, u8 mstatus)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	BOOLEAN		bcn_valid = _FALSE;
++	u8	DLBcnCount = 0;
++	u32 poll = 0;
++	u8 RegFwHwTxQCtrl;
++
++
++	RTW_INFO("+" FUNC_ADPT_FMT ": hw_port=%d mstatus(%x)\n",
++		 FUNC_ADPT_ARG(padapter), get_hw_port(padapter), mstatus);
++
++	if (mstatus == RT_MEDIA_CONNECT) {
++		u8 bcn_ctrl = rtw_read8(padapter, REG_BCN_CTRL);
++		BOOLEAN bRecover = _FALSE;
++		u8 v8;
++
++		/* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */
++		/* Suggested by filen. Added by tynli. */
++		rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000 | pmlmeinfo->aid));
++
++		/* set REG_CR bit 8 */
++		v8 = rtw_read8(padapter, REG_CR + 1);
++		v8 |= BIT(0); /* ENSWBCN */
++		rtw_write8(padapter,  REG_CR + 1, v8);
++
++		/* Disable Hw protection for a time which revserd for Hw sending beacon. */
++		/* Fix download reserved page packet fail that access collision with the protection time. */
++		/* 2010.05.11. Added by tynli. */
++		rtw_write8(padapter, REG_BCN_CTRL, (bcn_ctrl & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT);
++
++		/* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */
++		RegFwHwTxQCtrl = rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2);
++		if (RegFwHwTxQCtrl & BIT(6))
++			bRecover = _TRUE;
++
++		/* To tell Hw the packet is not a real beacon frame. */
++		RegFwHwTxQCtrl &= ~BIT(6);
++		rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, RegFwHwTxQCtrl);
++
++		/* Clear beacon valid check bit. */
++		rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
++		rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
++
++		DLBcnCount = 0;
++		poll = 0;
++		do {
++			/* download rsvd page. */
++			rtw_hal_set_fw_rsvd_page(padapter, _FALSE);
++			DLBcnCount++;
++			do {
++				rtw_yield_os();
++				/* rtw_mdelay_os(10); */
++				/* check rsvd page download OK. */
++				rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8 *)(&bcn_valid));
++				poll++;
++			} while (!bcn_valid && (poll % 10) != 0 && !RTW_CANNOT_RUN(padapter));
++
++		} while (!bcn_valid && DLBcnCount <= 100 && !RTW_CANNOT_RUN(padapter));
++
++		if (RTW_CANNOT_RUN(padapter))
++			;
++		else if (!bcn_valid)
++			RTW_ERR(ADPT_FMT": 1 DL RSVD page failed! DLBcnCount:%u, poll:%u\n",
++				 ADPT_ARG(padapter) , DLBcnCount, poll);
++		else {
++			struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
++
++			pwrctl->fw_psmode_iface_id = padapter->iface_id;
++			rtw_hal_set_fw_rsvd_page(padapter, _TRUE);
++			RTW_INFO(ADPT_FMT": 1 DL RSVD page success! DLBcnCount:%u, poll:%u\n",
++				 ADPT_ARG(padapter), DLBcnCount, poll);
++		}
++
++		/* restore bcn_ctrl */
++		rtw_write8(padapter, REG_BCN_CTRL, bcn_ctrl);
++
++		/* To make sure that if there exists an adapter which would like to send beacon. */
++		/* If exists, the origianl value of 0x422[6] will be 1, we should check this to */
++		/* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
++		/* the beacon cannot be sent by HW. */
++		/* 2010.06.23. Added by tynli. */
++		if (bRecover) {
++			RegFwHwTxQCtrl |= BIT(6);
++			rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, RegFwHwTxQCtrl);
++		}
++
++		/* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
++#ifndef CONFIG_PCI_HCI
++		v8 = rtw_read8(padapter, REG_CR + 1);
++		v8 &= ~BIT(0); /* ~ENSWBCN */
++		rtw_write8(padapter, REG_CR + 1, v8);
++#endif
++	}
++
++}
++
++void rtl8723d_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus)
++{
++	if (mstatus == 1)
++		rtl8723d_download_rsvd_page(padapter, RT_MEDIA_CONNECT);
++}
++
++#ifdef CONFIG_BT_COEXIST
++void rtl8723d_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter)
++{
++	rtl8723d_download_rsvd_page(padapter, RT_MEDIA_CONNECT);
++}
++#endif /* CONFIG_BT_COEXIST */
++
++#ifdef CONFIG_P2P
++void rtl8723d_set_p2p_ps_offload_cmd(_adapter *padapter, u8 p2p_ps_state)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct pwrctrl_priv		*pwrpriv = adapter_to_pwrctl(padapter);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++	struct P2P_PS_Offload_t	*p2p_ps_offload = (struct P2P_PS_Offload_t *)(&pHalData->p2p_ps_offload);
++	u8	i;
++
++
++#if 1
++	switch (p2p_ps_state) {
++	case P2P_PS_DISABLE:
++		RTW_INFO("P2P_PS_DISABLE\n");
++		_rtw_memset(p2p_ps_offload, 0 , 1);
++		break;
++	case P2P_PS_ENABLE:
++		RTW_INFO("P2P_PS_ENABLE\n");
++		/* update CTWindow value. */
++		if (pwdinfo->ctwindow > 0) {
++			p2p_ps_offload->CTWindow_En = 1;
++			rtw_write8(padapter, REG_P2P_CTWIN, pwdinfo->ctwindow);
++		}
++
++		/* hw only support 2 set of NoA */
++		for (i = 0 ; i < pwdinfo->noa_num ; i++) {
++			/* To control the register setting for which NOA */
++			rtw_write8(padapter, REG_NOA_DESC_SEL, (i << 4));
++			if (i == 0)
++				p2p_ps_offload->NoA0_En = 1;
++			else
++				p2p_ps_offload->NoA1_En = 1;
++
++			/* config P2P NoA Descriptor Register */
++			/* RTW_INFO("%s(): noa_duration = %x\n",__FUNCTION__,pwdinfo->noa_duration[i]); */
++			rtw_write32(padapter, REG_NOA_DESC_DURATION, pwdinfo->noa_duration[i]);
++
++			/* RTW_INFO("%s(): noa_interval = %x\n",__FUNCTION__,pwdinfo->noa_interval[i]); */
++			rtw_write32(padapter, REG_NOA_DESC_INTERVAL, pwdinfo->noa_interval[i]);
++
++			/* RTW_INFO("%s(): start_time = %x\n",__FUNCTION__,pwdinfo->noa_start_time[i]); */
++			rtw_write32(padapter, REG_NOA_DESC_START, pwdinfo->noa_start_time[i]);
++
++			/* RTW_INFO("%s(): noa_count = %x\n",__FUNCTION__,pwdinfo->noa_count[i]); */
++			rtw_write8(padapter, REG_NOA_DESC_COUNT, pwdinfo->noa_count[i]);
++		}
++
++		if ((pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0)) {
++			/* rst p2p circuit */
++			rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(4));
++
++			p2p_ps_offload->Offload_En = 1;
++
++			if (pwdinfo->role == P2P_ROLE_GO) {
++				p2p_ps_offload->role = 1;
++				p2p_ps_offload->AllStaSleep = 0;
++			} else
++				p2p_ps_offload->role = 0;
++
++			p2p_ps_offload->discovery = 0;
++		}
++		break;
++	case P2P_PS_SCAN:
++		RTW_INFO("P2P_PS_SCAN\n");
++		p2p_ps_offload->discovery = 1;
++		break;
++	case P2P_PS_SCAN_DONE:
++		RTW_INFO("P2P_PS_SCAN_DONE\n");
++		p2p_ps_offload->discovery = 0;
++		pwdinfo->p2p_ps_state = P2P_PS_ENABLE;
++		break;
++	default:
++		break;
++	}
++
++	FillH2CCmd8723D(padapter, H2C_8723D_P2P_PS_OFFLOAD, 1, (u8 *)p2p_ps_offload);
++#endif
++
++
++}
++#endif /* CONFIG_P2P */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_dm.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_dm.c
+new file mode 100644
+index 000000000..71f4ab06c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_dm.c
+@@ -0,0 +1,310 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/* ************************************************************
++ * Description:
++ *
++ * This file is for 92CE/92CU dynamic mechanism only
++ *
++ *
++ * ************************************************************ */
++#define _RTL8723D_DM_C_
++
++/* ************************************************************
++ * include files
++ * ************************************************************ */
++#include <rtl8723d_hal.h>
++
++/* ************************************************************
++ * Global var
++ * ************************************************************ */
++#ifdef CONFIG_SUPPORT_HW_WPS_PBC
++static void dm_CheckPbcGPIO(_adapter *padapter)
++{
++	u8	tmp1byte;
++	u8	bPbcPressed = _FALSE;
++
++	if (!padapter->registrypriv.hw_wps_pbc)
++		return;
++
++#ifdef CONFIG_USB_HCI
++	tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
++	tmp1byte |= (HAL_8192C_HW_GPIO_WPS_BIT);
++	rtw_write8(padapter, GPIO_IO_SEL, tmp1byte);	/* enable GPIO[2] as output mode */
++
++	tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
++	rtw_write8(padapter,  GPIO_IN, tmp1byte);		/* reset the floating voltage level */
++
++	tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
++	tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
++	rtw_write8(padapter, GPIO_IO_SEL, tmp1byte);	/* enable GPIO[2] as input mode */
++
++	tmp1byte = rtw_read8(padapter, GPIO_IN);
++
++	if (tmp1byte == 0xff)
++		return;
++
++	if (tmp1byte & HAL_8192C_HW_GPIO_WPS_BIT)
++		bPbcPressed = _TRUE;
++#else
++	tmp1byte = rtw_read8(padapter, GPIO_IN);
++
++	if (tmp1byte == 0xff || padapter->init_adpt_in_progress)
++		return;
++
++	if ((tmp1byte & HAL_8192C_HW_GPIO_WPS_BIT) == 0)
++		bPbcPressed = _TRUE;
++#endif
++
++	if (_TRUE == bPbcPressed) {
++		/* Here we only set bPbcPressed to true */
++		/* After trigger PBC, the variable will be set to false */
++		RTW_INFO("CheckPbcGPIO - PBC is pressed\n");
++		rtw_request_wps_pbc_event(padapter);
++	}
++}
++#endif /* #ifdef CONFIG_SUPPORT_HW_WPS_PBC */
++
++
++#ifdef CONFIG_PCI_HCI
++/*
++ *	Description:
++ *		Perform interrupt migration dynamically to reduce CPU utilization.
++ *
++ *	Assumption:
++ *		1. Do not enable migration under WIFI test.
++ *
++ *	Created by Roger, 2010.03.05.
++ *   */
++void
++dm_InterruptMigration(
++		PADAPTER	Adapter
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);
++	BOOLEAN			bCurrentIntMt, bCurrentACIntDisable;
++	BOOLEAN			IntMtToSet = _FALSE;
++	BOOLEAN			ACIntToSet = _FALSE;
++
++
++	/* Retrieve current interrupt migration and Tx four ACs IMR settings first. */
++	bCurrentIntMt = pHalData->bInterruptMigration;
++	bCurrentACIntDisable = pHalData->bDisableTxInt;
++
++	/* */
++	/* <Roger_Notes> Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics */
++	/* when interrupt migration is set before. 2010.03.05. */
++	/* */
++	if (!Adapter->registrypriv.wifi_spec &&
++	    (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) &&
++	    pmlmepriv->LinkDetectInfo.bHigherBusyTraffic) {
++		IntMtToSet = _TRUE;
++
++		/* To check whether we should disable Tx interrupt or not. */
++		if (pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic)
++			ACIntToSet = _TRUE;
++	}
++
++	/* Update current settings. */
++	if (bCurrentIntMt != IntMtToSet) {
++		RTW_INFO("%s(): Update interrupt migration(%d)\n", __FUNCTION__, IntMtToSet);
++		if (IntMtToSet) {
++			/* */
++			/* <Roger_Notes> Set interrupt migration timer and corresponging Tx/Rx counter. */
++			/* timer 25ns*0xfa0=100us for 0xf packets. */
++			/* 2010.03.05. */
++			/* */
++			rtw_write32(Adapter, REG_INT_MIG_8723D, 0xff000fa0);/* 0x306:Rx, 0x307:Tx */
++			pHalData->bInterruptMigration = IntMtToSet;
++		} else {
++			/* Reset all interrupt migration settings. */
++			rtw_write32(Adapter, REG_INT_MIG_8723D, 0);
++			pHalData->bInterruptMigration = IntMtToSet;
++		}
++	}
++
++	/*if( bCurrentACIntDisable != ACIntToSet ){
++		RTW_INFO("%s(): Update AC interrupt(%d)\n",__FUNCTION__,ACIntToSet);
++		if(ACIntToSet)
++		{
++
++
++
++
++
++			UpdateInterruptMask8192CE( Adapter, 0, RT_AC_INT_MASKS );
++			pHalData->bDisableTxInt = ACIntToSet;
++		}
++		else
++		{
++			UpdateInterruptMask8192CE( Adapter, RT_AC_INT_MASKS, 0 );
++			pHalData->bDisableTxInt = ACIntToSet;
++		}
++	}*/
++
++}
++
++#endif
++
++/*
++ * Initialize GPIO setting registers
++ *   */
++#ifdef CONFIG_USB_HCI
++static void
++dm_InitGPIOSetting(
++		PADAPTER	Adapter
++)
++{
++	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(Adapter);
++
++	u8	tmp1byte;
++
++	tmp1byte = rtw_read8(Adapter, REG_GPIO_MUXCFG);
++	tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT);
++
++	rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte);
++}
++#endif
++/* ************************************************************
++ * functions
++ * ************************************************************ */
++static void Init_ODM_ComInfo_8723d(PADAPTER	Adapter)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
++	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
++	u8	cut_ver, fab_ver;
++
++	Init_ODM_ComInfo(Adapter);
++
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, pHalData->PackageType);
++
++	fab_ver = ODM_TSMC;
++	cut_ver = GET_CVID_CUT_VERSION(pHalData->version_id);
++
++	RTW_INFO("%s(): Fv=%d Cv=%d\n", __func__, fab_ver, cut_ver);
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_FAB_VER, fab_ver);
++	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_CUT_VER, cut_ver);
++}
++
++void
++rtl8723d_InitHalDm(
++		PADAPTER	Adapter
++)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
++	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
++
++#ifdef CONFIG_USB_HCI
++	dm_InitGPIOSetting(Adapter);
++#endif
++	rtw_phydm_init(Adapter);
++}
++
++void
++rtl8723d_HalDmWatchDog(
++		PADAPTER	Adapter
++)
++{
++	BOOLEAN		bFwCurrentInPSMode = _FALSE;
++	u8 bFwPSAwake = _TRUE;
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter);
++	u8 in_lps = _FALSE;
++
++#ifdef CONFIG_MP_INCLUDED
++	/* #if MP_DRIVER */
++	if (Adapter->registrypriv.mp_mode == 1 && Adapter->mppriv.mp_dm == 0) /* for MP power tracking */
++		return;
++	/* #endif */
++#endif
++
++	if (!rtw_is_hw_init_completed(Adapter))
++		goto skip_dm;
++
++#ifdef CONFIG_LPS
++	bFwCurrentInPSMode = pwrpriv->bFwCurrentInPSMode;
++	rtw_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, &bFwPSAwake);
++#endif
++
++#ifdef CONFIG_P2P
++	/* Fw is under p2p powersaving mode, driver should stop dynamic mechanism. */
++	/* modifed by thomas. 2011.06.11. */
++	if (Adapter->wdinfo.p2p_ps_mode)
++		bFwPSAwake = _FALSE;
++#endif /* CONFIG_P2P */
++
++
++	if ((rtw_is_hw_init_completed(Adapter))
++	    && ((!bFwCurrentInPSMode) && bFwPSAwake)) {
++
++		rtw_hal_check_rxfifo_full(Adapter);
++		/* */
++		/* Dynamically switch RTS/CTS protection. */
++		/* */
++
++#ifdef CONFIG_PCI_HCI
++		/* 20100630 Joseph: Disable Interrupt Migration mechanism temporarily because it degrades Rx throughput. */
++		/* Tx Migration settings. */
++		/* dm_InterruptMigration(Adapter); */
++
++		/* if(Adapter->HalFunc.TxCheckStuckHandler(Adapter)) */
++		/*	PlatformScheduleWorkItem(&(GET_HAL_DATA(Adapter)->HalResetWorkItem)); */
++#endif
++	}
++
++#ifdef CONFIG_DISABLE_ODM
++	goto skip_dm;
++#endif
++
++#ifdef CONFIG_LPS
++	if (pwrpriv->bLeisurePs && bFwCurrentInPSMode && pwrpriv->pwr_mode != PS_MODE_ACTIVE)
++		in_lps = _TRUE;
++#endif
++
++	rtw_phydm_watchdog(Adapter, in_lps);
++
++skip_dm:
++
++	/* Check GPIO to determine current RF on/off and Pbc status. */
++	/* Check Hardware Radio ON/OFF or not */
++	/* if(Adapter->MgntInfo.PowerSaveControl.bGpioRfSw) */
++	/* { */
++	/* RTPRINT(FPWR, PWRHW, ("dm_CheckRfCtrlGPIO\n")); */
++	/*	dm_CheckRfCtrlGPIO(Adapter); */
++	/* } */
++#ifdef CONFIG_SUPPORT_HW_WPS_PBC
++	dm_CheckPbcGPIO(Adapter);
++#endif
++	return;
++}
++
++void rtl8723d_init_dm_priv(PADAPTER Adapter)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
++	struct dm_struct		*podmpriv = &pHalData->odmpriv;
++
++	Init_ODM_ComInfo_8723d(Adapter);
++	odm_init_all_timers(podmpriv);
++
++}
++
++void rtl8723d_deinit_dm_priv(PADAPTER Adapter)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
++	struct dm_struct		*podmpriv = &pHalData->odmpriv;
++
++	odm_cancel_all_timers(podmpriv);
++
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_hal_init.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_hal_init.c
+new file mode 100755
+index 000000000..11f51e96b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_hal_init.c
+@@ -0,0 +1,5476 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _HAL_INIT_C_
++
++#include <rtl8723d_hal.h>
++#include "hal_com_h2c.h"
++#include <hal_com.h>
++#include "hal8723d_fw.h"
++
++#ifndef CONFIG_DLFW_TXPKT
++#define DL_FW_MAX 15
++#else
++#define FW_DOWNLOAD_SIZE_8723D 8192
++#endif
++
++static void
++_FWDownloadEnable(
++		PADAPTER		padapter,
++		BOOLEAN			enable
++)
++{
++	u8	tmp, count = 0;
++
++	if (enable) {
++		/* 8051 enable */
++		tmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
++		rtw_write8(padapter, REG_SYS_FUNC_EN + 1, tmp | 0x04);
++
++		tmp = rtw_read8(padapter, REG_MCUFWDL);
++		rtw_write8(padapter, REG_MCUFWDL, tmp | 0x01);
++
++		do {
++			tmp = rtw_read8(padapter, REG_MCUFWDL);
++			if (tmp & 0x01)
++				break;
++			rtw_write8(padapter, REG_MCUFWDL, tmp | 0x01);
++			rtw_msleep_os(1);
++		} while (count++ < 100);
++		if (count > 0)
++			RTW_INFO("%s: !!!!!!!!Write 0x80 Fail!: count = %d\n", __func__, count);
++
++		/* 8051 reset */
++		tmp = rtw_read8(padapter, REG_MCUFWDL + 2);
++		rtw_write8(padapter, REG_MCUFWDL + 2, tmp & 0xf7);
++	} else {
++		/* MCU firmware download disable. */
++		tmp = rtw_read8(padapter, REG_MCUFWDL);
++		rtw_write8(padapter, REG_MCUFWDL, tmp & 0xfe);
++	}
++}
++
++#ifdef CONFIG_USB_HCI
++static int _BlockWrite(struct _ADAPTER *padapter, void *buffer, u32 buffSize)
++{
++	int ret = _SUCCESS;
++
++	u32 blockSize_p1 = 254;	/* Phase #1 */
++	u32 blockSize_p2 = 8;	/* Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. */
++	u32 blockSize_p3 = 1;	/* Phase #3 : Use 1-byte, the remnant of FW image. */
++	u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0;
++	u32 remainSize_p1 = 0, remainSize_p2 = 0;
++	u8 *bufferPtr = (u8 *)buffer;
++	u32 i = 0, offset = 0;
++
++
++	/* Phase #1 */
++	blockCount_p1 = buffSize / blockSize_p1;
++	remainSize_p1 = buffSize % blockSize_p1;
++
++	for (i = 0; i < blockCount_p1; i++) {
++		ret = rtw_writeN(padapter,
++				 (FW_8723D_START_ADDRESS + i * blockSize_p1),
++				 blockSize_p1, (bufferPtr + i * blockSize_p1));
++		if (ret == _FAIL) {
++			RTW_ERR("====>%s %d i:%d\n", __func__, __LINE__, i);
++			goto exit;
++		}
++	}
++
++	/* Phase #2 */
++	if (remainSize_p1) {
++		offset = blockCount_p1 * blockSize_p1;
++
++		blockCount_p2 = remainSize_p1 / blockSize_p2;
++		remainSize_p2 = remainSize_p1 % blockSize_p2;
++
++		for (i = 0; i < blockCount_p2; i++) {
++			ret = rtw_writeN(padapter,
++					 (FW_8723D_START_ADDRESS + offset + i * blockSize_p2),
++					 blockSize_p2,
++					 (bufferPtr + offset + i * blockSize_p2));
++			if (ret == _FAIL)
++				goto exit;
++		}
++	}
++
++	/* Phase #3 */
++	if (remainSize_p2) {
++		offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2);
++
++		blockCount_p3 = remainSize_p2 / blockSize_p3;
++
++		for (i = 0 ; i < blockCount_p3 ; i++) {
++			ret = rtw_write8(padapter, (FW_8723D_START_ADDRESS + offset + i), *(bufferPtr + offset + i));
++			if (ret == _FAIL) {
++				RTW_ERR("====>%s %d i:%d\n", __func__, __LINE__, i);
++				goto exit;
++			}
++		}
++	}
++
++exit:
++	return ret;
++}
++#else /* !CONFIG_USB_HCI */
++static int _BlockWrite(struct _ADAPTER *padapter, void *buffer, u32 buffSize)
++{
++	int ret = _SUCCESS;
++
++	u32 blockSize_p1 = 4;	/* Phase #1 : PCI muse use 4-byte write to download FW */
++				/* Phase #2 : write the remnant of FW image. */
++	u32 blockCount_p1 = 0;
++	u32 remainSize_p1 = 0;
++	u8 *bufferPtr = (u8 *)buffer;
++	u32 i = 0, offset = 0;
++#ifdef CONFIG_PCI_HCI
++	u8 remainFW[4] = {0, 0, 0, 0};
++#endif
++
++
++	/* Phase #1 */
++	blockCount_p1 = buffSize / blockSize_p1;
++	remainSize_p1 = buffSize % blockSize_p1;
++
++	for (i = 0; i < blockCount_p1; i++) {
++		ret = rtw_write32(padapter,
++				  (FW_8723D_START_ADDRESS + i * blockSize_p1),
++				  le32_to_cpu(*((u32 *)(bufferPtr + i * blockSize_p1))));
++		if (ret == _FAIL) {
++			RTW_ERR("====>%s %d i:%d\n", __func__, __LINE__, i);
++			goto exit;
++		}
++	}
++
++	/* Phase #2 */
++	if (remainSize_p1) {
++		offset = (blockCount_p1 * blockSize_p1);
++		bufferPtr += offset;
++#ifdef CONFIG_PCI_HCI
++		switch (remainSize_p1) {
++		case 3:
++			remainFW[2] = *(bufferPtr + 2);
++		case 2:
++			remainFW[1] = *(bufferPtr + 1);
++		case 1:
++			remainFW[0] = *(bufferPtr);
++			ret = rtw_write32(padapter,
++					  (FW_8723D_START_ADDRESS + offset),
++					  le32_to_cpu(*(u32 *)remainFW));
++		}
++#else /* !CONFIG_PCI_HCI */
++		for (i = 0; i < remainSize_p1; i++) {
++			ret = rtw_write8(padapter,
++					 (FW_8723D_START_ADDRESS + offset + i),
++					 *(bufferPtr + i));
++			if (ret == _FAIL) {
++				RTW_ERR("====>%s %d i:%d\n", __func__, __LINE__, i);
++				goto exit;
++			}
++		}
++#endif /* !CONFIG_PCI_HCI */
++	}
++
++exit:
++	return ret;
++}
++#endif /* !CONFIG_USB_HCI */
++
++static int
++_PageWrite(
++			PADAPTER	padapter,
++			u32			page,
++			void			*buffer,
++			u32			size
++)
++{
++	u8 value8;
++	u8 u8Page = (u8)(page & 0x07);
++
++	value8 = (rtw_read8(padapter, REG_MCUFWDL + 2) & 0xF8) | u8Page;
++	rtw_write8(padapter, REG_MCUFWDL + 2, value8);
++
++	return _BlockWrite(padapter, buffer, size);
++}
++#ifdef CONFIG_PCI_HCI
++static void
++_FillDummy(
++	u8		*pFwBuf,
++	u32	*pFwLen
++)
++{
++	u32	FwLen = *pFwLen;
++	u8	remain = (u8)(FwLen % 4);
++
++	remain = (remain == 0) ? 0 : (4 - remain);
++
++	while (remain > 0) {
++		pFwBuf[FwLen] = 0;
++		FwLen++;
++		remain--;
++	}
++
++	*pFwLen = FwLen;
++}
++#endif
++static int
++_WriteFW(
++		PADAPTER padapter,
++		void *buffer,
++		u32 size
++)
++{
++	/* Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */
++	int ret = _SUCCESS;
++	u32 pageNums, remainSize;
++	u32 page, offset;
++	u8 *bufferPtr = (u8 *)buffer;
++
++#ifdef CONFIG_PCI_HCI
++	/* 20100120 Joseph: Add for 88CE normal chip. */
++	/* Fill in zero to make firmware image to dword alignment. */
++	_FillDummy(bufferPtr, &size);
++#endif
++
++	pageNums = size / MAX_DLFW_PAGE_SIZE;
++	/* RT_ASSERT((pageNums <= 4), ("Page numbers should not greater then 4\n")); */
++	remainSize = size % MAX_DLFW_PAGE_SIZE;
++
++	for (page = 0; page < pageNums; page++) {
++		offset = page * MAX_DLFW_PAGE_SIZE;
++		ret = _PageWrite(padapter, page, bufferPtr + offset, MAX_DLFW_PAGE_SIZE);
++
++		if (ret == _FAIL) {
++			printk(KERN_ERR "====>%s %d\n", __func__, __LINE__);
++			goto exit;
++		}
++	}
++	if (remainSize) {
++		offset = pageNums * MAX_DLFW_PAGE_SIZE;
++		page = pageNums;
++		ret = _PageWrite(padapter, page, bufferPtr + offset, remainSize);
++
++		if (ret == _FAIL) {
++			printk(KERN_ERR "====>%s %d\n", __func__, __LINE__);
++			goto exit;
++		}
++	}
++
++exit:
++	return ret;
++}
++
++void _8051Reset8723(PADAPTER padapter)
++{
++	u8 cpu_rst;
++	u8 io_rst;
++
++#if 0
++	io_rst = rtw_read8(padapter, REG_RSV_CTRL);
++	rtw_write8(padapter, REG_RSV_CTRL, io_rst & (~BIT(1)));
++#endif
++
++	/* Reset 8051(WLMCU) IO wrapper */
++	/* 0x1c[8] = 0 */
++	/* Suggested by Isaac@SD1 and Gimmy@SD1, coding by Lucas@20130624 */
++	io_rst = rtw_read8(padapter, REG_RSV_CTRL + 1);
++	io_rst &= ~BIT(0);
++	rtw_write8(padapter, REG_RSV_CTRL + 1, io_rst);
++
++	cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
++	cpu_rst &= ~BIT(2);
++	rtw_write8(padapter, REG_SYS_FUNC_EN + 1, cpu_rst);
++
++#if 0
++	io_rst = rtw_read8(padapter, REG_RSV_CTRL);
++	rtw_write8(padapter, REG_RSV_CTRL, io_rst & (~BIT(1)));
++#endif
++
++	/* Enable 8051 IO wrapper	 */
++	/* 0x1c[8] = 1 */
++	io_rst = rtw_read8(padapter, REG_RSV_CTRL + 1);
++	io_rst |= BIT(0);
++	rtw_write8(padapter, REG_RSV_CTRL + 1, io_rst);
++
++	cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
++	cpu_rst |= BIT(2);
++	rtw_write8(padapter, REG_SYS_FUNC_EN + 1, cpu_rst);
++
++	RTW_INFO("%s: Finish\n", __FUNCTION__);
++}
++
++static s32 polling_fwdl_chksum(_adapter *adapter, u32 min_cnt, u32 timeout_ms)
++{
++	s32 ret = _FAIL;
++	u32 value32;
++	systime start = rtw_get_current_time();
++	u32 cnt = 0;
++
++	/* polling CheckSum report */
++	do {
++		cnt++;
++		value32 = rtw_read32(adapter, REG_MCUFWDL);
++		if (value32 & FWDL_ChkSum_rpt || RTW_CANNOT_IO(adapter))
++			break;
++		rtw_yield_os();
++	} while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt);
++
++	if (!(value32 & FWDL_ChkSum_rpt))
++		goto exit;
++
++	if (rtw_fwdl_test_trigger_chksum_fail())
++		goto exit;
++
++	ret = _SUCCESS;
++
++exit:
++	RTW_INFO("%s: Checksum report %s! (%u, %dms), REG_MCUFWDL:0x%08x\n", __FUNCTION__
++		, (ret == _SUCCESS) ? "OK" : "Fail", cnt, rtw_get_passing_time_ms(start), value32);
++
++	return ret;
++}
++
++static s32 _FWFreeToGo(_adapter *adapter, u32 min_cnt, u32 timeout_ms)
++{
++	s32 ret = _FAIL;
++	u32	value32;
++	systime start = rtw_get_current_time();
++	u32 cnt = 0;
++	u32 value_to_check = 0;
++	u32 value_expected = (MCUFWDL_RDY | FWDL_ChkSum_rpt | WINTINI_RDY | RAM_DL_SEL);
++
++	value32 = rtw_read32(adapter, REG_MCUFWDL);
++	value32 |= MCUFWDL_RDY;
++	value32 &= ~WINTINI_RDY;
++	rtw_write32(adapter, REG_MCUFWDL, value32);
++
++	_8051Reset8723(adapter);
++
++	/*  polling for FW ready */
++	do {
++		cnt++;
++		value32 = rtw_read32(adapter, REG_MCUFWDL);
++		value_to_check = value32 & value_expected;
++		if ((value_to_check == value_expected) || RTW_CANNOT_IO(adapter))
++			break;
++		rtw_yield_os();
++	} while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt);
++
++	if (value_to_check != value_expected)
++		goto exit;
++
++	if (rtw_fwdl_test_trigger_wintint_rdy_fail())
++		goto exit;
++
++	ret = _SUCCESS;
++
++exit:
++	RTW_INFO("%s: Polling FW ready %s! (%u, %dms), REG_MCUFWDL:0x%08x\n", __FUNCTION__
++		, (ret == _SUCCESS) ? "OK" : "Fail", cnt, rtw_get_passing_time_ms(start), value32);
++
++	return ret;
++}
++
++#define IS_FW_81xxC(padapter)	(((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0)
++
++void rtl8723d_FirmwareSelfReset(PADAPTER padapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	u8	u1bTmp;
++	u8	Delay = 100;
++
++	if (!(IS_FW_81xxC(padapter) &&
++	      ((pHalData->firmware_version < 0x21) ||
++	       (pHalData->firmware_version == 0x21 &&
++		pHalData->firmware_sub_version < 0x01)))) { /* after 88C Fw v33.1 */
++		/* 0x1cf=0x20. Inform 8051 to reset. 2009.12.25. tynli_test */
++		rtw_write8(padapter, REG_HMETFR + 3, 0x20);
++
++		u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
++		while (u1bTmp & BIT(2)) {
++			Delay--;
++			if (Delay == 0)
++				break;
++			rtw_udelay_os(50);
++			u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
++		}
++
++		if (Delay == 0) {
++			/* force firmware reset */
++			u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
++			rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp & (~BIT(2)));
++		}
++	}
++}
++
++#ifdef CONFIG_FILE_FWIMG
++	u8 FwBuffer[FW_8723D_SIZE];
++#endif /* CONFIG_FILE_FWIMG */
++
++#ifdef CONFIG_MP_INCLUDED
++int _WriteBTFWtoTxPktBuf8723D(
++			PADAPTER	Adapter,
++			void			*buffer,
++			u32			FwBufLen,
++			u8			times
++)
++{
++	int			rtStatus = _SUCCESS;
++	/* u32				value32; */
++	/* u8				numHQ, numLQ, numPubQ;//, txpktbuf_bndy; */
++	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
++	/* PMGNT_INFO		pMgntInfo = &(Adapter->MgntInfo); */
++	u8				BcnValidReg;
++	u8				count = 0, DLBcnCount = 0;
++	u8 *FwbufferPtr = (u8 *)buffer;
++	/* PRT_TCB			pTcb, ptempTcb; */
++	/* PRT_TX_LOCAL_BUFFER pBuf; */
++
++	u8 *ReservedPagePacket = NULL;
++	u8 *pGenBufReservedPagePacket = NULL;
++	u32				TotalPktLen, txpktbuf_bndy;
++	/* u8				tmpReg422; */
++	/* u8				u1bTmp; */
++	u8			*pframe;
++	struct xmit_priv	*pxmitpriv = &(Adapter->xmitpriv);
++	struct xmit_frame	*pmgntframe;
++	struct pkt_attrib	*pattrib;
++	u8			txdesc_offset = TXDESC_OFFSET;
++	u8			val8, RegFwHwTxQCtrl;
++#ifdef CONFIG_PCI_HCI
++	u8			u1bTmp;
++#endif
++
++#if 1/* #ifdef CONFIG_PCI_HCI */
++	TotalPktLen = FwBufLen;
++#else
++	TotalPktLen = FwBufLen + pHalData->HWDescHeadLength;
++#endif
++
++	if ((TotalPktLen + TXDESC_OFFSET) > MAX_CMDBUF_SZ) {
++		RTW_INFO(" WARNING %s => Total packet len = %d > MAX_CMDBUF_SZ:%d\n"
++			, __FUNCTION__, (TotalPktLen + TXDESC_OFFSET), MAX_CMDBUF_SZ);
++		return _FAIL;
++	}
++
++	pGenBufReservedPagePacket = rtw_zmalloc(TotalPktLen);/* GetGenTempBuffer (Adapter, TotalPktLen); */
++	if (!pGenBufReservedPagePacket)
++		return _FAIL;
++
++	ReservedPagePacket = (u8 *)pGenBufReservedPagePacket;
++
++	_rtw_memset(ReservedPagePacket, 0, TotalPktLen);
++
++#if 1/* #ifdef CONFIG_PCI_HCI */
++	_rtw_memcpy(ReservedPagePacket, FwbufferPtr, FwBufLen);
++
++#else
++	PlatformMoveMemory(ReservedPagePacket + Adapter->HWDescHeadLength , FwbufferPtr, FwBufLen);
++#endif
++
++	/* --------------------------------------------------------- */
++	/* 1. Pause BCN */
++	/* --------------------------------------------------------- */
++	/* Set REG_CR bit 8. DMA beacon by SW. */
++#ifdef CONFIG_PCI_HCI
++	u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR + 1);
++	PlatformEFIOWrite1Byte(Adapter,  REG_CR + 1, (u1bTmp | BIT(0)));
++#else
++	/* Remove for temparaily because of the code on v2002 is not sync to MERGE_TMEP for USB/SDIO. */
++	/* De not remove this part on MERGE_TEMP. by tynli. */
++#endif
++
++	/* Disable Hw protection for a time which revserd for Hw sending beacon. */
++	/* Fix download reserved page packet fail that access collision with the protection time. */
++	/* 2010.05.11. Added by tynli. */
++	val8 = rtw_read8(Adapter, REG_BCN_CTRL);
++	val8 &= ~EN_BCN_FUNCTION;
++	val8 |= DIS_TSF_UDT;
++	rtw_write8(Adapter, REG_BCN_CTRL, val8);
++
++#if 0/* #ifdef CONFIG_PCI_HCI */
++	tmpReg422 = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2);
++	if (tmpReg422 & BIT(6))
++		bRecover = TRUE;
++	PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2,  tmpReg422 & (~BIT(6)));
++#else
++	/* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */
++	RegFwHwTxQCtrl = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2);
++
++	RegFwHwTxQCtrl &= (~BIT(6));
++	PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2, RegFwHwTxQCtrl);
++#endif
++
++	/* --------------------------------------------------------- */
++	/* 2. Adjust LLT table to an even boundary. */
++	/* --------------------------------------------------------- */
++#if 0/* #ifdef CONFIG_SDIO_HCI */
++	txpktbuf_bndy = 10; /* rsvd page start address should be an even value.														 */
++	rtStatus =	InitLLTTable8723DS(Adapter, txpktbuf_bndy);
++	if (RT_STATUS_SUCCESS != rtStatus) {
++		RTW_INFO("_CheckWLANFwPatchBTFwReady_8723D(): Failed to init LLT!\n");
++		return RT_STATUS_FAILURE;
++	}
++
++	/* Init Tx boundary. */
++	PlatformEFIOWrite1Byte(Adapter, REG_DWBCN0_CTRL_8723D + 1, (u8)txpktbuf_bndy);
++#endif
++
++
++	/* --------------------------------------------------------- */
++	/* 3. Write Fw to Tx packet buffer by reseverd page. */
++	/* --------------------------------------------------------- */
++	do {
++		/* download rsvd page. */
++		/* Clear beacon valid check bit. */
++		BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 2);
++		PlatformEFIOWrite1Byte(Adapter, REG_TDECTRL + 2, BcnValidReg & (~BIT(0)));
++
++		/* BT patch is big, we should set 0x209 < 0x40 suggested from Gimmy */
++
++		PlatformEFIOWrite1Byte(Adapter, REG_TDECTRL + 1, (0x90 - 0x20 * (times - 1)));
++		RTW_INFO("0x209:0x%x\n", PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 1));
++
++#if 0
++		/* Acquice TX spin lock before GetFwBuf and send the packet to prevent system deadlock. */
++		/* Advertised by Roger. Added by tynli. 2010.02.22. */
++		PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK);
++		if (MgntGetFWBuffer(Adapter, &pTcb, &pBuf)) {
++			PlatformMoveMemory(pBuf->Buffer.VirtualAddress, ReservedPagePacket, TotalPktLen);
++			CmdSendPacket(Adapter, pTcb, pBuf, TotalPktLen, DESC_PACKET_TYPE_NORMAL, FALSE);
++		} else
++			dbgdump("SetFwRsvdPagePkt(): MgntGetFWBuffer FAIL!!!!!!!!.\n");
++		PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK);
++#else
++		/*---------------------------------------------------------
++		tx reserved_page_packet
++		----------------------------------------------------------*/
++		pmgntframe = rtw_alloc_cmdxmitframe(pxmitpriv);
++		if (pmgntframe == NULL) {
++			rtStatus = _FAIL;
++			goto exit;
++		}
++		/* update attribute */
++		pattrib = &pmgntframe->attrib;
++		update_mgntframe_attrib(Adapter, pattrib);
++
++		pattrib->qsel = QSLT_BEACON;
++		pattrib->pktlen = pattrib->last_txcmdsz = FwBufLen;
++
++		/* _rtw_memset(pmgntframe->buf_addr, 0, TotalPktLen+txdesc_size); */
++		/* pmgntframe->buf_addr = ReservedPagePacket ; */
++
++		_rtw_memcpy((u8 *)(pmgntframe->buf_addr + txdesc_offset), ReservedPagePacket, FwBufLen);
++		RTW_INFO("[%d]===>TotalPktLen + TXDESC_OFFSET TotalPacketLen:%d\n", DLBcnCount, (FwBufLen + txdesc_offset));
++
++#ifdef CONFIG_PCI_HCI
++		dump_mgntframe(Adapter, pmgntframe);
++#else
++		dump_mgntframe_and_wait(Adapter, pmgntframe, 100);
++#endif
++
++#endif
++#if 1
++		/* check rsvd page download OK. */
++		BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 2);
++		while (!(BcnValidReg & BIT(0)) && count < 200) {
++			count++;
++			/* PlatformSleepUs(10); */
++			rtw_msleep_os(1);
++			BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 2);
++		}
++		DLBcnCount++;
++		/* RTW_INFO("##0x208:%08x,0x210=%08x\n",PlatformEFIORead4Byte(Adapter, REG_TDECTRL),PlatformEFIORead4Byte(Adapter, 0x210)); */
++
++		PlatformEFIOWrite1Byte(Adapter, REG_TDECTRL + 2, BcnValidReg);
++
++	} while ((!(BcnValidReg & BIT(0))) && DLBcnCount < 5);
++
++
++#endif
++	if (DLBcnCount >= 5) {
++		RTW_INFO(" check rsvd page download OK DLBcnCount =%d\n", DLBcnCount);
++		rtStatus = _FAIL;
++		goto exit;
++	}
++
++	if (!(BcnValidReg & BIT(0))) {
++		RTW_INFO("_WriteFWtoTxPktBuf(): 1 Download RSVD page failed!\n");
++		rtStatus = _FAIL;
++		goto exit;
++	}
++
++	/* --------------------------------------------------------- */
++	/* 4. Set Tx boundary to the initial value */
++	/* --------------------------------------------------------- */
++
++
++	/* --------------------------------------------------------- */
++	/* 5. Reset beacon setting to the initial value. */
++	/*	 After _CheckWLANFwPatchBTFwReady(). */
++	/* --------------------------------------------------------- */
++
++exit:
++
++	if (pGenBufReservedPagePacket) {
++		RTW_INFO("_WriteBTFWtoTxPktBuf8723D => rtw_mfree pGenBufReservedPagePacket!\n");
++		rtw_mfree((u8 *)pGenBufReservedPagePacket, TotalPktLen);
++	}
++	return rtStatus;
++}
++
++
++
++/*
++ * Description: Determine the contents of H2C BT_FW_PATCH Command sent to FW.
++ * 2011.10.20 by tynli
++ *   */
++void
++SetFwBTFwPatchCmd(
++		PADAPTER	Adapter,
++		u16		FwSize
++)
++{
++	u8 u1BTFwPatchParm[H2C_BT_FW_PATCH_LEN] = {0};
++	u8 addr0 = 0;
++	u8 addr1 = 0xa0;
++	u8 addr2 = 0x10;
++	u8 addr3 = 0x80;
++
++
++	SET_8723D_H2CCMD_BT_FW_PATCH_SIZE(u1BTFwPatchParm, FwSize);
++	SET_8723D_H2CCMD_BT_FW_PATCH_ADDR0(u1BTFwPatchParm, addr0);
++	SET_8723D_H2CCMD_BT_FW_PATCH_ADDR1(u1BTFwPatchParm, addr1);
++	SET_8723D_H2CCMD_BT_FW_PATCH_ADDR2(u1BTFwPatchParm, addr2);
++	SET_8723D_H2CCMD_BT_FW_PATCH_ADDR3(u1BTFwPatchParm, addr3);
++
++	FillH2CCmd8723D(Adapter, H2C_8723D_BT_FW_PATCH, H2C_BT_FW_PATCH_LEN, u1BTFwPatchParm);
++
++}
++
++void
++SetFwBTPwrCmd(
++		PADAPTER	Adapter,
++		u8	PwrIdx
++)
++{
++	u8		u1BTPwrIdxParm[H2C_FORCE_BT_TXPWR_LEN] = {0};
++
++	SET_8723D_H2CCMD_BT_PWR_IDX(u1BTPwrIdxParm, PwrIdx);
++
++
++	FillH2CCmd8723D(Adapter, H2C_8723D_FORCE_BT_TXPWR, H2C_FORCE_BT_TXPWR_LEN, u1BTPwrIdxParm);
++}
++
++/*
++ * Description: WLAN Fw will write BT Fw to BT XRAM and signal driver.
++ *
++ * 2011.10.20. by tynli.
++ *   */
++int
++_CheckWLANFwPatchBTFwReady(
++	PADAPTER Adapter,
++	BOOLEAN bRecover
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++	u32	count = 0;
++	u8	u1bTmp;
++	int ret = _FAIL;
++
++	/* --------------------------------------------------------- */
++	/* Check if BT FW patch procedure is ready. */
++	/* --------------------------------------------------------- */
++	do {
++		u1bTmp = PlatformEFIORead1Byte(Adapter, REG_HMEBOX_DBG_0_8723D);
++		if ((u1bTmp & BIT(6)) || (u1bTmp & BIT(7))) {
++			ret = _SUCCESS;
++			break;
++		}
++
++		count++;
++		rtw_msleep_os(50); /* 50ms */
++	} while (!((u1bTmp & BIT(6)) || (u1bTmp & BIT(7))) && count < 50);
++
++
++
++
++	/* --------------------------------------------------------- */
++	/* Reset beacon setting to the initial value. */
++	/* --------------------------------------------------------- */
++#if 0/* #ifdef CONFIG_PCI_HCI */
++	if (LLT_table_init(Adapter, FALSE, 0) == RT_STATUS_FAILURE) {
++		dbgdump("Init self define for BT Fw patch LLT table fail.\n");
++		/* return RT_STATUS_FAILURE; */
++	}
++#endif
++	u1bTmp = rtw_read8(Adapter, REG_BCN_CTRL);
++	u1bTmp |= EN_BCN_FUNCTION;
++	u1bTmp &= ~DIS_TSF_UDT;
++	rtw_write8(Adapter, REG_BCN_CTRL, u1bTmp);
++
++	/* To make sure that if there exists an adapter which would like to send beacon. */
++	/* If exists, the origianl value of 0x422[6] will be 1, we should check this to */
++	/* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
++	/* the beacon cannot be sent by HW. */
++	/* 2010.06.23. Added by tynli. */
++	if (bRecover) {
++		u1bTmp = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2);
++		PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2, (u1bTmp | BIT(6)));
++	}
++
++	/* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
++	u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR + 1);
++	PlatformEFIOWrite1Byte(Adapter, REG_CR + 1, (u1bTmp & (~BIT(0))));
++
++	return ret;
++}
++
++int ReservedPage_Compare(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware, u32 BTPatchSize)
++{
++	u8 temp, ret, lastBTsz;
++	u32 u1bTmp = 0, address_start = 0, count = 0, i = 0;
++	u8	*myBTFwBuffer = NULL;
++
++	myBTFwBuffer = rtw_zmalloc(BTPatchSize);
++	if (myBTFwBuffer == NULL) {
++		RTW_INFO("%s can't be executed due to the failed malloc.\n", __FUNCTION__);
++		Adapter->mppriv.bTxBufCkFail = _TRUE;
++		return _FALSE;
++	}
++
++	temp = rtw_read8(Adapter, 0x209);
++
++	address_start = (temp * 128) / 8;
++
++	rtw_write32(Adapter, 0x140, 0x00000000);
++	rtw_write32(Adapter, 0x144, 0x00000000);
++	rtw_write32(Adapter, 0x148, 0x00000000);
++
++	rtw_write8(Adapter, 0x106, 0x69);
++
++	for (i = 0; i < (BTPatchSize / 8); i++) {
++		rtw_write32(Adapter, 0x140, address_start + 5 + i);
++
++		/* polling until reg 0x140[23]=1; */
++		do {
++			u1bTmp = rtw_read32(Adapter, 0x140);
++			if (u1bTmp & BIT(23)) {
++				ret = _SUCCESS;
++				break;
++			}
++			count++;
++			RTW_INFO("0x140=%x, wait for 10 ms (%d) times.\n", u1bTmp, count);
++			rtw_msleep_os(10); /* 10ms */
++		} while (!(u1bTmp & BIT(23)) && count < 50);
++
++		myBTFwBuffer[i * 8 + 0] = rtw_read8(Adapter, 0x144);
++		myBTFwBuffer[i * 8 + 1] = rtw_read8(Adapter, 0x145);
++		myBTFwBuffer[i * 8 + 2] = rtw_read8(Adapter, 0x146);
++		myBTFwBuffer[i * 8 + 3] = rtw_read8(Adapter, 0x147);
++		myBTFwBuffer[i * 8 + 4] = rtw_read8(Adapter, 0x148);
++		myBTFwBuffer[i * 8 + 5] = rtw_read8(Adapter, 0x149);
++		myBTFwBuffer[i * 8 + 6] = rtw_read8(Adapter, 0x14a);
++		myBTFwBuffer[i * 8 + 7] = rtw_read8(Adapter, 0x14b);
++	}
++
++	rtw_write32(Adapter, 0x140, address_start + 5 + BTPatchSize / 8);
++
++	lastBTsz = BTPatchSize % 8;
++
++	/* polling until reg 0x140[23]=1; */
++	u1bTmp = 0;
++	count = 0;
++	do {
++		u1bTmp = rtw_read32(Adapter, 0x140);
++		if (u1bTmp & BIT(23)) {
++			ret = _SUCCESS;
++			break;
++		}
++		count++;
++		RTW_INFO("0x140=%x, wait for 10 ms (%d) times.\n", u1bTmp, count);
++		rtw_msleep_os(10); /* 10ms */
++	} while (!(u1bTmp & BIT(23)) && count < 50);
++
++	for (i = 0; i < lastBTsz; i++)
++		myBTFwBuffer[(BTPatchSize / 8) * 8 + i] = rtw_read8(Adapter, (0x144 + i));
++
++
++	for (i = 0; i < BTPatchSize; i++) {
++		if (myBTFwBuffer[i] != pFirmware->szFwBuffer[i]) {
++			RTW_INFO(" In direct myBTFwBuffer[%d]=%x , pFirmware->szFwBuffer=%x\n", i, myBTFwBuffer[i], pFirmware->szFwBuffer[i]);
++			Adapter->mppriv.bTxBufCkFail = _TRUE;
++			break;
++		}
++	}
++
++	if (myBTFwBuffer != NULL)
++		rtw_mfree(myBTFwBuffer, BTPatchSize);
++
++	return _TRUE;
++}
++
++/* As the size of bt firmware is more than 16k which is too big for some platforms, we divide it
++ * into four parts to transfer. The last parameter of _WriteBTFWtoTxPktBuf8723D is used to indicate
++ * the location of every part. We call the first 4096 byte of bt firmware as part 1, the second 4096
++ * part as part 2, the third 4096 part as part 3, the remain as part 4. First we transform the part
++ * 4 and set the register 0x209 to 0x90, then the 32 bytes description are added to the head of part
++ * 4, and those bytes are putted at the location 0x90. Second we transform the part 3 and set the
++ * register 0x209 to 0x70. The 32 bytes description and part 3(4196 bytes) are putted at the location
++ * 0x70. It can contain 4196 bytes between 0x70 and 0x90. So the last 32 bytes os part 3 will cover the
++ * 32 bytes description of part4. Using this method, we can put the whole bt firmware to 0x30 and only
++ * has 32 bytes descrption at the head of part 1.
++*/
++s32 FirmwareDownloadBT(PADAPTER padapter, PRT_MP_FIRMWARE pFirmware)
++{
++	s32 rtStatus;
++	u8 *pBTFirmwareBuf;
++	u32 BTFirmwareLen;
++	u8 download_time;
++	s8 i;
++	BOOLEAN bRecover = _FALSE;
++	u8 RegFwHwTxQCtrl;
++
++	rtStatus = _SUCCESS;
++	pBTFirmwareBuf = NULL;
++	BTFirmwareLen = 0;
++
++#if 0
++	/* */
++	/* Patch BT Fw. Download BT RAM code to Tx packet buffer. */
++	/* */
++	if (GET_HAL_DATA(padapter)->bBTFWReady) {
++		RTW_INFO("%s: BT Firmware is ready!!\n", __FUNCTION__);
++		return _FAIL;
++	}
++
++#ifdef CONFIG_FILE_FWIMG
++	if (rtw_is_file_readable(rtw_fw_mp_bt_file_path) == _TRUE) {
++		RTW_INFO("%s: acquire MP BT FW from file:%s\n", __FUNCTION__, rtw_fw_mp_bt_file_path);
++
++		rtStatus = rtw_retrieve_from_file(rtw_fw_mp_bt_file_path, FwBuffer, FW_8723D_SIZE);
++		BTFirmwareLen = rtStatus >= 0 ? rtStatus : 0;
++		pBTFirmwareBuf = FwBuffer;
++	} else
++#endif /* CONFIG_FILE_FWIMG */
++	{
++#ifdef CONFIG_EMBEDDED_FWIMG
++		RTW_INFO("%s: Download MP BT FW from header\n", __FUNCTION__);
++
++		pBTFirmwareBuf = (u8 *)Rtl8723DFwBTImgArray;
++		BTFirmwareLen = Rtl8723DFwBTImgArrayLength;
++		pFirmware->szFwBuffer = pBTFirmwareBuf;
++		pFirmware->ulFwLength = BTFirmwareLen;
++#endif /* CONFIG_EMBEDDED_FWIMG */
++	}
++
++	RTW_INFO("%s: MP BT Firmware size=%d\n", __FUNCTION__, BTFirmwareLen);
++
++	/* for h2c cam here should be set to  true */
++	GET_HAL_DATA(padapter)->bFWReady = _TRUE;
++
++	download_time = (BTFirmwareLen + 4095) / 4096;
++	RTW_INFO("%s: download_time is %d\n", __FUNCTION__, download_time);
++	RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL + 2);
++
++	if (RegFwHwTxQCtrl & BIT(6))
++		bRecover = _TRUE;
++
++	/* Download BT patch Fw. */
++	for (i = (download_time - 1); i >= 0; i--) {
++		if (i == (download_time - 1)) {
++			rtStatus = _WriteBTFWtoTxPktBuf8723D(padapter, pBTFirmwareBuf + (4096 * i), (BTFirmwareLen - (4096 * i)), 1);
++			RTW_INFO("%s: start %d, len %d, time 1\n", __FUNCTION__, 4096 * i, BTFirmwareLen - (4096 * i));
++		} else {
++			rtStatus = _WriteBTFWtoTxPktBuf8723D(padapter, pBTFirmwareBuf + (4096 * i), 4096, (download_time - i));
++			RTW_INFO("%s: start %d, len 4096, time %d\n", __FUNCTION__, 4096 * i, download_time - i);
++		}
++
++		if (rtStatus != _SUCCESS) {
++			RTW_INFO("%s: BT Firmware download to Tx packet buffer fail!\n", __FUNCTION__);
++			GET_HAL_DATA(padapter)->bBTFWReady = _FALSE;
++			return rtStatus;
++		}
++	}
++
++	ReservedPage_Compare(padapter, pFirmware, BTFirmwareLen);
++
++	GET_HAL_DATA(padapter)->bBTFWReady = _TRUE;
++	SetFwBTFwPatchCmd(padapter, (u16)BTFirmwareLen);
++	rtStatus = _CheckWLANFwPatchBTFwReady(padapter, bRecover);
++
++	RTW_INFO("<===%s: return %s!\n", __FUNCTION__, rtStatus == _SUCCESS ? "SUCCESS" : "FAIL");
++#endif
++
++	return rtStatus;
++}
++#endif /* CONFIG_MP_INCLUDED */
++
++#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_DLFW_TXPKT)
++u8 send_fw_packet(PADAPTER padapter, u8 *pRam_code, u32 length)
++{
++	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
++	struct xmit_buf xmit_buf_tmp;
++	struct submit_ctx sctx_tmp;
++	u8 *pTx_data_buffer = NULL;
++	u8 *pTmp_buffer = NULL;
++	u8 bRet = 0, value8 = 0, res = _FAIL;
++	u32 modify_ram_size = 0;
++	u32 tmp_size = 0, tmp_value = 0;
++	u32 i = 0, counter = 0;
++	u32 dwDataLength = 0, writeLength = 0;
++
++	/* Due to SDIO can not send 32K packet */
++	if (FW_DOWNLOAD_SIZE_8723D == length)
++		length--;
++
++	modify_ram_size = length << 2;
++
++	pTx_data_buffer = rtw_zmalloc(modify_ram_size);
++
++	if (NULL == pTx_data_buffer) {
++		RTW_INFO("Allocate buffer fail!!\n");
++		return _FALSE;
++	}
++
++	_rtw_memset(pTx_data_buffer, 0, modify_ram_size);
++
++	/* Transfer to new format */
++	tmp_size = length >> 1;
++	for (i = 0; i <= tmp_size; i++) {
++		*(pTx_data_buffer + i * 8) = *(pRam_code + i * 2);
++		*(pTx_data_buffer + i * 8 + 1) = *(pRam_code + i * 2 + 1);
++	}
++
++	/* Gen TX_DESC */
++	_rtw_memset(pTx_data_buffer, 0, TXDESC_SIZE);
++	pTmp_buffer = pTx_data_buffer;
++	SET_TX_DESC_QUEUE_SEL_8723D(pTmp_buffer, QSLT_BEACON);
++	SET_TX_DESC_PKT_SIZE_8723D(pTmp_buffer, modify_ram_size - TXDESC_SIZE);
++	SET_TX_DESC_OFFSET_8723D(pTmp_buffer, TXDESC_SIZE);
++
++	/* Send packet */
++	xmit_buf_tmp.pdata = pTx_data_buffer;
++	xmit_buf_tmp.len = modify_ram_size;
++	rtw_sctx_init(&sctx_tmp, 10);
++	xmit_buf_tmp.sctx = &sctx_tmp;
++
++	res = rtw_write_port(padapter,
++			     pdvobjpriv->Queue2Pipe[BCN_QUEUE_INX],
++			     xmit_buf_tmp.len,
++			     (u8 *)&xmit_buf_tmp);
++	if (res == _FAIL) {
++		RTW_INFO("rtw_write_port fail\n");
++		return _FAIL;
++	}
++
++	/* check if DMA is OK */
++	counter = 100;
++	do {
++		if (0 == counter) {
++			RTW_INFO("DMA time out!!\n");
++			return _FALSE;
++		}
++		value8 = rtw_read8(padapter, REG_DWBCN0_CTRL_8723D + 2);
++		counter--;
++	} while (0 == (value8 & BIT(0)));
++
++	rtw_write8(padapter, REG_DWBCN0_CTRL_8723D + 2, value8);
++
++	/* Modify ram code by IO method */
++	tmp_value = rtw_read8(padapter, REG_MCUFWDL + 1);
++	/* Disable DMA */
++	rtw_write8(padapter, REG_MCUFWDL + 1, (u8)tmp_value & ~(BIT(5)));
++	tmp_value = (tmp_value >> 6) << 1;
++	/* Set page start address */
++	rtw_write8(padapter, REG_MCUFWDL + 2,
++		   (rtw_read8(padapter, REG_MCUFWDL + 2) & 0xF8) | tmp_value);
++	tmp_size = TXDESC_SIZE >> 2; /* 10bytes */
++
++	_BlockWrite(padapter, pRam_code, tmp_size);
++
++	if (pTmp_buffer != NULL)
++		rtw_mfree((u8 *)pTmp_buffer, modify_ram_size);
++
++	return _TRUE;
++}
++#endif /* CONFIG_SDIO_HCI */
++
++/*
++ *	Description:
++ *		Download 8192C firmware code.
++ *
++ *   */
++s32 rtl8723d_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw)
++{
++	s32	rtStatus = _SUCCESS;
++	u8 write_fw = 0;
++	systime fwdl_start_time;
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++	u8			*FwImage;
++	u32			FwImageLen;
++	u8			*pFwImageFileName;
++#ifdef CONFIG_WOWLAN
++	u8			*FwImageWoWLAN;
++	u32			FwImageWoWLANLen;
++#endif
++	u8			*pucMappedFile = NULL;
++	PRT_FIRMWARE_8723D	pFirmware = NULL;
++	PRT_8723D_FIRMWARE_HDR		pFwHdr = NULL;
++	u8			*pFirmwareBuf;
++	u32			FirmwareLen;
++#ifdef CONFIG_FILE_FWIMG
++	u8 *fwfilepath;
++#endif /* CONFIG_FILE_FWIMG */
++	u8			value8;
++	u16			value16;
++	u32			value32;
++	u8			dma_iram_sel;
++	u16		new_chk_sum = 0;
++	u32		send_pkt_size, pkt_size_tmp;
++	u32		mem_offset;
++	u32			counter;
++	struct dvobj_priv *psdpriv = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++
++
++	pFirmware = (PRT_FIRMWARE_8723D)rtw_zmalloc(sizeof(RT_FIRMWARE_8723D));
++
++	if (!pFirmware) {
++		rtStatus = _FAIL;
++		goto exit;
++	}
++
++	{
++		u8 tmp_ps = 0, tmp_rf = 0;
++
++		tmp_ps = rtw_read8(padapter, 0xa3);
++		tmp_ps &= 0xf8;
++		tmp_ps |= 0x02;
++		/* 1. write 0xA3[:2:0] = 3b'010 */
++		rtw_write8(padapter, 0xa3, tmp_ps);
++		/* 2. read power_state = 0xA0[1:0] */
++		tmp_ps = rtw_read8(padapter, 0xa0);
++		tmp_ps &= 0x03;
++		if (tmp_ps != 0x01) {
++			RTW_INFO(FUNC_ADPT_FMT" tmp_ps=%x\n",
++				 FUNC_ADPT_ARG(padapter), tmp_ps);
++			pdbgpriv->dbg_downloadfw_pwr_state_cnt++;
++		}
++	}
++
++#ifdef CONFIG_BT_COEXIST
++	rtw_btcoex_PreLoadFirmware(padapter);
++#endif /* CONFIG_BT_COEXIST */
++
++#ifdef CONFIG_FILE_FWIMG
++#ifdef CONFIG_WOWLAN
++	if (bUsedWoWLANFw)
++		fwfilepath = rtw_fw_wow_file_path;
++	else
++#endif /* CONFIG_WOWLAN */
++	{
++		fwfilepath = rtw_fw_file_path;
++	}
++#endif /* CONFIG_FILE_FWIMG */
++
++#ifdef CONFIG_FILE_FWIMG
++	if (rtw_is_file_readable(fwfilepath) == _TRUE) {
++		RTW_INFO("%s acquire FW from file:%s\n", __FUNCTION__, fwfilepath);
++		pFirmware->eFWSource = FW_SOURCE_IMG_FILE;
++	} else
++#endif /* CONFIG_FILE_FWIMG */
++	{
++#ifdef CONFIG_EMBEDDED_FWIMG
++		pFirmware->eFWSource = FW_SOURCE_HEADER_FILE;
++#else /* !CONFIG_EMBEDDED_FWIMG */
++		pFirmware->eFWSource = FW_SOURCE_IMG_FILE; /* We should decided by Reg. */
++#endif /* !CONFIG_EMBEDDED_FWIMG */
++	}
++
++	switch (pFirmware->eFWSource) {
++	case FW_SOURCE_IMG_FILE:
++#ifdef CONFIG_FILE_FWIMG
++		rtStatus = rtw_retrieve_from_file(fwfilepath, FwBuffer, FW_8723D_SIZE);
++		pFirmware->ulFwLength = rtStatus >= 0 ? rtStatus : 0;
++		pFirmware->szFwBuffer = FwBuffer;
++#endif /* CONFIG_FILE_FWIMG */
++		break;
++
++	case FW_SOURCE_HEADER_FILE:
++		if (bUsedWoWLANFw) {
++	#ifdef CONFIG_WOWLAN
++			if (pwrpriv->wowlan_mode) {
++				pFirmware->szFwBuffer = array_mp_8723d_fw_wowlan;
++				pFirmware->ulFwLength = array_length_mp_8723d_fw_wowlan;
++				RTW_INFO(" ===> %s fw: %s, size: %d\n",
++					 __FUNCTION__, "WoWLAN", pFirmware->ulFwLength);
++			}
++	#endif /* CONFIG_WOWLAN */
++
++	#ifdef CONFIG_AP_WOWLAN
++			if (pwrpriv->wowlan_ap_mode) {
++				pFirmware->szFwBuffer = array_mp_8723d_fw_ap;
++				pFirmware->ulFwLength = array_length_mp_8723d_fw_ap;
++				RTW_INFO(" ===> %s fw: %s, size: %d\n",
++					 __FUNCTION__, "AP_WoWLAN", pFirmware->ulFwLength);
++			}
++	#endif /* CONFIG_AP_WOWLAN */
++		} else {
++			pFirmware->szFwBuffer = array_mp_8723d_fw_nic;
++			pFirmware->ulFwLength = array_length_mp_8723d_fw_nic;
++			RTW_INFO("%s fw: %s, size: %d\n", __FUNCTION__, "FW_NIC", pFirmware->ulFwLength);
++		}
++		break;
++	}
++
++	if ((pFirmware->ulFwLength - 32) > FW_8723D_SIZE) {
++		rtStatus = _FAIL;
++		RTW_ERR("Firmware size:%u exceed %u\n",
++			pFirmware->ulFwLength, FW_8723D_SIZE);
++		goto exit;
++	}
++
++	pFirmwareBuf = pFirmware->szFwBuffer;
++	FirmwareLen = pFirmware->ulFwLength;
++
++	/* To Check Fw header. Added by tynli. 2009.12.04. */
++	pFwHdr = (PRT_8723D_FIRMWARE_HDR)pFirmwareBuf;
++
++	pHalData->firmware_version =  le16_to_cpu(pFwHdr->Version);
++	pHalData->firmware_sub_version = le16_to_cpu(pFwHdr->Subversion);
++	pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature);
++
++	RTW_INFO("%s: fw_ver=%x fw_subver=%04x sig=0x%x, Month=%02x, Date=%02x, Hour=%02x, Minute=%02x\n",
++		 __func__, pHalData->firmware_version,
++		 pHalData->firmware_sub_version, pHalData->FirmwareSignature
++		 , pFwHdr->Month, pFwHdr->Date, pFwHdr->Hour, pFwHdr->Minute);
++
++	if (IS_FW_HEADER_EXIST_8723D(pFwHdr)) {
++		RTW_INFO("%s(): Shift for fw header!\n", __FUNCTION__);
++		/* Shift 32 bytes for FW header */
++		pFirmwareBuf = pFirmwareBuf + 32;
++		FirmwareLen = FirmwareLen - 32;
++	}
++
++	fwdl_start_time = rtw_get_current_time();
++
++	/* To check if FW already exists before download FW */
++	if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) {
++		RTW_INFO("%s: FW exists before download FW\n", __func__);
++		rtw_write8(padapter, REG_MCUFWDL, 0x00);
++		_8051Reset8723(padapter);
++	}
++
++#ifndef CONFIG_DLFW_TXPKT
++	RTW_INFO("%s by IO write!\n", __func__);
++
++	_FWDownloadEnable(padapter, _TRUE);
++
++	while (!RTW_CANNOT_IO(padapter) &&
++	       (write_fw++ < DL_FW_MAX ||
++		rtw_get_passing_time_ms(fwdl_start_time) < 500)) {
++		/* reset FWDL chksum */
++		rtw_write8(padapter, REG_MCUFWDL,
++			   rtw_read8(padapter, REG_MCUFWDL) | FWDL_ChkSum_rpt);
++
++		rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen);
++		if (rtStatus != _SUCCESS)
++			continue;
++
++		rtStatus = polling_fwdl_chksum(padapter, 2, 10);
++		if (rtStatus == _SUCCESS) {
++			RTW_INFO("%s: download FW count:%d\n", __func__,
++				 write_fw);
++			break;
++		} else {
++			rtw_mdelay_os(10);
++		}
++	}
++#else
++	RTW_INFO("%s by Tx pkt write!\n", __func__);
++
++	if ((rtw_read8(padapter, REG_MCUFWDL) & MCUFWDL_RDY) == 0) {
++		/*
++		 * SDIO DMA condition:
++		 * all queue must be 256 (0x100 = 0x20 + 0xE0)
++		*/
++
++		value32 = 0x802000E0;
++		rtw_write32(padapter, REG_RQPN, value32);
++
++		/* Set beacon boundary to TXFIFO header */
++		rtw_write8(padapter, REG_BCNQ_BDNY, 0);
++		rtw_write16(padapter, REG_DWBCN0_CTRL_8723D + 1, BIT(8));
++
++		/* SDIO need read this register before send packet */
++		rtw_read32(padapter, 0x10250020);
++
++		_FWDownloadEnable(padapter, _TRUE);
++
++		/* Get original check sum */
++		new_chk_sum = *(pFirmwareBuf + FirmwareLen - 2) |
++			      ((u16)*(pFirmwareBuf + FirmwareLen - 1) << 8);
++
++		/* Send ram code flow */
++		dma_iram_sel = 0;
++		mem_offset = 0;
++		pkt_size_tmp = FirmwareLen;
++		while (0 != pkt_size_tmp) {
++			if (pkt_size_tmp >= FW_DOWNLOAD_SIZE_8723D) {
++				send_pkt_size = FW_DOWNLOAD_SIZE_8723D;
++				/* Modify check sum value */
++				new_chk_sum = (u16)(new_chk_sum ^ (((send_pkt_size - 1) << 2) - TXDESC_SIZE));
++			} else {
++				send_pkt_size = pkt_size_tmp;
++				new_chk_sum = (u16)(new_chk_sum ^ ((send_pkt_size << 2) - TXDESC_SIZE));
++
++			}
++
++			if (send_pkt_size == pkt_size_tmp) {
++				/* last partition packet, write new check sum to ram code file */
++				*(pFirmwareBuf + FirmwareLen - 2) = new_chk_sum & 0xFF;
++				*(pFirmwareBuf + FirmwareLen - 1) = (new_chk_sum & 0xFF00) >> 8;
++			}
++
++			/* IRAM select */
++			rtw_write8(padapter, REG_MCUFWDL + 1,
++				(rtw_read8(padapter, REG_MCUFWDL + 1) & 0x3F) | (dma_iram_sel << 6));
++			/* Enable DMA */
++			rtw_write8(padapter, REG_MCUFWDL + 1,
++				rtw_read8(padapter, REG_MCUFWDL + 1) | BIT(5));
++
++			if (_FALSE == send_fw_packet(padapter, pFirmwareBuf + mem_offset, send_pkt_size)) {
++				RTW_INFO("%s: Send FW fail !\n", __FUNCTION__);
++				rtStatus = _FAIL;
++				goto DLFW_FAIL;
++			}
++
++			dma_iram_sel++;
++			mem_offset += send_pkt_size;
++			pkt_size_tmp -= send_pkt_size;
++		}
++	} else {
++		RTW_INFO("%s: Download FW fail since MCUFWDL_RDY is not set!\n", __FUNCTION__);
++		rtStatus = _FAIL;
++		goto DLFW_FAIL;
++	}
++#endif
++
++	_FWDownloadEnable(padapter, _FALSE);
++
++	if (rtStatus == _SUCCESS)
++		rtStatus = _FWFreeToGo(padapter, 10, 200);
++	else
++		goto DLFW_FAIL;
++
++	if (_SUCCESS != rtStatus)
++		goto DLFW_FAIL;
++
++DLFW_FAIL:
++	if (rtStatus == _FAIL) {
++		/* Disable FWDL_EN */
++		value8 = rtw_read8(padapter, REG_MCUFWDL);
++		value8 = (value8 & ~(BIT(0)) & ~(BIT(1)));
++		rtw_write8(padapter, REG_MCUFWDL, value8);
++	}
++
++	RTW_INFO("%s %s. write_fw:%u, %dms\n"
++		 , __FUNCTION__, (rtStatus == _SUCCESS) ? "success" : "fail"
++		 , write_fw
++		 , rtw_get_passing_time_ms(fwdl_start_time)
++		);
++
++exit:
++	if (pFirmware)
++		rtw_mfree((u8 *)pFirmware, sizeof(RT_FIRMWARE_8723D));
++
++	rtl8723d_InitializeFirmwareVars(padapter);
++
++	RTW_INFO(" <=== %s()\n", __FUNCTION__);
++
++	return rtStatus;
++}
++
++void rtl8723d_InitializeFirmwareVars(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++
++	/* Init Fw LPS related. */
++	adapter_to_pwrctl(padapter)->bFwCurrentInPSMode = _FALSE;
++
++	/* Init H2C cmd. */
++	rtw_write8(padapter, REG_HMETFR, 0x0f);
++
++	/* Init H2C counter. by tynli. 2009.12.09. */
++	pHalData->LastHMEBoxNum = 0;
++	/*	pHalData->H2CQueueHead = 0;
++	 *	pHalData->H2CQueueTail = 0;
++	 *	pHalData->H2CStopInsertQueue = _FALSE; */
++}
++
++/* ***********************************************************
++ *				Efuse related code
++ * *********************************************************** */
++static u8
++hal_EfuseSwitchToBank(
++	PADAPTER	padapter,
++	u8			bank,
++	u8			bPseudoTest)
++{
++	u8 bRet = _FALSE;
++	u32 value32 = 0;
++#ifdef HAL_EFUSE_MEMORY
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++	PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
++#endif
++
++
++	RTW_INFO("%s: Efuse switch bank to %d\n", __FUNCTION__, bank);
++	if (bPseudoTest) {
++#ifdef HAL_EFUSE_MEMORY
++		pEfuseHal->fakeEfuseBank = bank;
++#else
++		fakeEfuseBank = bank;
++#endif
++		bRet = _TRUE;
++	} else {
++		value32 = rtw_read32(padapter, EFUSE_TEST);
++		bRet = _TRUE;
++		switch (bank) {
++		case 0:
++			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
++			break;
++		case 1:
++			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0);
++			break;
++		case 2:
++			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1);
++			break;
++		case 3:
++			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2);
++			break;
++		default:
++			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
++			bRet = _FALSE;
++			break;
++		}
++		rtw_write32(padapter, EFUSE_TEST, value32);
++	}
++
++	return bRet;
++}
++
++static void
++Hal_GetEfuseDefinition(
++	PADAPTER	padapter,
++	u8			efuseType,
++	u8			type,
++	void		*pOut,
++	u8			bPseudoTest)
++{
++	switch (type) {
++	case TYPE_EFUSE_MAX_SECTION: {
++		u8 *pMax_section;
++
++		pMax_section = (u8 *)pOut;
++
++		if (efuseType == EFUSE_WIFI)
++			*pMax_section = EFUSE_MAX_SECTION_8723D;
++		else
++			*pMax_section = EFUSE_BT_MAX_SECTION;
++	}
++	break;
++
++	case TYPE_EFUSE_REAL_CONTENT_LEN: {
++		u16 *pu2Tmp;
++
++		pu2Tmp = (u16 *)pOut;
++
++		if (efuseType == EFUSE_WIFI)
++			*pu2Tmp = EFUSE_REAL_CONTENT_LEN_8723D;
++		else
++			*pu2Tmp = EFUSE_BT_REAL_CONTENT_LEN;
++	}
++	break;
++
++	case TYPE_AVAILABLE_EFUSE_BYTES_BANK: {
++		u16	*pu2Tmp;
++
++		pu2Tmp = (u16 *)pOut;
++
++		if (efuseType == EFUSE_WIFI)
++			*pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8723D - EFUSE_OOB_PROTECT_BYTES);
++		else
++			*pu2Tmp = (EFUSE_BT_REAL_BANK_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK);
++	}
++	break;
++
++	case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL: {
++		u16 *pu2Tmp;
++
++		pu2Tmp = (u16 *)pOut;
++
++		if (efuseType == EFUSE_WIFI)
++			*pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8723D - EFUSE_OOB_PROTECT_BYTES);
++		else
++			*pu2Tmp = (EFUSE_BT_REAL_CONTENT_LEN - (EFUSE_PROTECT_BYTES_BANK * 3));
++	}
++	break;
++
++	case TYPE_EFUSE_MAP_LEN: {
++		u16 *pu2Tmp;
++
++		pu2Tmp = (u16 *)pOut;
++
++		if (efuseType == EFUSE_WIFI)
++			*pu2Tmp = EFUSE_MAP_LEN_8723D;
++		else
++			*pu2Tmp = EFUSE_BT_MAP_LEN;
++	}
++	break;
++
++	case TYPE_EFUSE_PROTECT_BYTES_BANK: {
++		u8 *pu1Tmp;
++
++		pu1Tmp = (u8 *)pOut;
++
++		if (efuseType == EFUSE_WIFI)
++			*pu1Tmp = EFUSE_OOB_PROTECT_BYTES;
++		else
++			*pu1Tmp = EFUSE_PROTECT_BYTES_BANK;
++	}
++	break;
++
++	case TYPE_EFUSE_CONTENT_LEN_BANK: {
++		u16 *pu2Tmp;
++
++		pu2Tmp = (u16 *)pOut;
++
++		if (efuseType == EFUSE_WIFI)
++			*pu2Tmp = EFUSE_REAL_CONTENT_LEN_8723D;
++		else
++			*pu2Tmp = EFUSE_BT_REAL_BANK_CONTENT_LEN;
++	}
++	break;
++
++	default: {
++		u8 *pu1Tmp;
++
++		pu1Tmp = (u8 *)pOut;
++		*pu1Tmp = 0;
++	}
++	break;
++	}
++}
++
++#define VOLTAGE_V25		0x03
++#define LDOE25_SHIFT	28
++
++/* *****************************************************************
++ *	The following is for compile ok
++ *	That should be merged with the original in the future
++ * ***************************************************************** */
++#define EFUSE_ACCESS_ON_8723			0x69	/* For RTL8723 only. */
++#define EFUSE_ACCESS_OFF_8723			0x00	/* For RTL8723 only. */
++#define REG_EFUSE_ACCESS_8723			0x00CF	/* Efuse access protection for RTL8723 */
++
++/* ***************************************************************** */
++static void Hal_BT_EfusePowerSwitch(
++	PADAPTER	padapter,
++	u8			bWrite,
++	u8			PwrState)
++{
++	u8 tempval;
++
++	if (PwrState == _TRUE) {
++		/* enable BT power cut */
++		/* 0x6A[14] = 1 */
++		tempval = rtw_read8(padapter, 0x6B);
++		tempval |= BIT(6);
++		rtw_write8(padapter, 0x6B, tempval);
++
++		/* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay */
++		/* So don't write 0x6A[14]=1 and 0x6A[15]=0 together! */
++		rtw_usleep_os(100);
++		/* disable BT output isolation */
++		/* 0x6A[15] = 0 */
++		tempval = rtw_read8(padapter, 0x6B);
++		tempval &= ~BIT(7);
++		rtw_write8(padapter, 0x6B, tempval);
++	} else {
++		/* enable BT output isolation */
++		/* 0x6A[15] = 1 */
++		tempval = rtw_read8(padapter, 0x6B);
++		tempval |= BIT(7);
++		rtw_write8(padapter, 0x6B, tempval);
++
++		/* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay */
++		/* So don't write 0x6A[14]=1 and 0x6A[15]=0 together! */
++
++		/* disable BT power cut */
++		/* 0x6A[14] = 1 */
++		tempval = rtw_read8(padapter, 0x6B);
++		tempval &= ~BIT(6);
++		rtw_write8(padapter, 0x6B, tempval);
++	}
++
++}
++static void
++Hal_EfusePowerSwitch(
++	PADAPTER	padapter,
++	u8			bWrite,
++	u8			PwrState)
++{
++	u8	tempval;
++	u16	tmpV16;
++
++
++	if (PwrState == _TRUE) {
++#ifdef CONFIG_SDIO_HCI
++		/* To avoid cannot access efuse regsiters after disable/enable several times during DTM test. */
++		/* Suggested by SD1 IsaacHsu. 2013.07.08, added by tynli. */
++		tempval = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HSUS_CTRL);
++		if (tempval & BIT(0)) { /* SDIO local register is suspend */
++			u8 count = 0;
++
++
++			tempval &= ~BIT(0);
++			rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HSUS_CTRL, tempval);
++
++			/* check 0x86[1:0]=10'2h, wait power state to leave suspend */
++			do {
++				tempval = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HSUS_CTRL);
++				tempval &= 0x3;
++				if (tempval == 0x02)
++					break;
++
++				count++;
++				if (count >= 100)
++					break;
++
++				rtw_mdelay_os(10);
++			} while (1);
++
++			if (count >= 100) {
++				RTW_INFO(FUNC_ADPT_FMT ": Leave SDIO local register suspend fail! Local 0x86=%#X\n",
++					 FUNC_ADPT_ARG(padapter), tempval);
++			} else {
++				RTW_INFO(FUNC_ADPT_FMT ": Leave SDIO local register suspend OK! Local 0x86=%#X\n",
++					 FUNC_ADPT_ARG(padapter), tempval);
++			}
++		}
++#endif /* CONFIG_SDIO_HCI */
++
++		rtw_write8(padapter, REG_EFUSE_ACCESS_8723, EFUSE_ACCESS_ON_8723);
++
++		/* Reset: 0x0000h[28], default valid */
++		tmpV16 =  rtw_read16(padapter, REG_SYS_FUNC_EN);
++		if (!(tmpV16 & FEN_ELDR)) {
++			tmpV16 |= FEN_ELDR;
++			rtw_write16(padapter, REG_SYS_FUNC_EN, tmpV16);
++		}
++
++		/* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid */
++		tmpV16 = rtw_read16(padapter, REG_SYS_CLKR);
++		if ((!(tmpV16 & LOADER_CLK_EN))  || (!(tmpV16 & ANA8M))) {
++			tmpV16 |= (LOADER_CLK_EN | ANA8M);
++			rtw_write16(padapter, REG_SYS_CLKR, tmpV16);
++		}
++
++		if (bWrite == _TRUE) {
++			/* Enable LDO 2.5V before read/write action */
++			tempval = rtw_read8(padapter, EFUSE_TEST + 3);
++			tempval &= 0x0F;
++			tempval |= (VOLTAGE_V25 << 4);
++			rtw_write8(padapter, EFUSE_TEST + 3, (tempval | 0x80));
++
++			/* rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); */
++		}
++	} else {
++		rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
++
++		if (bWrite == _TRUE) {
++			/* Disable LDO 2.5V after read/write action */
++			tempval = rtw_read8(padapter, EFUSE_TEST + 3);
++			rtw_write8(padapter, EFUSE_TEST + 3, (tempval & 0x7F));
++		}
++
++	}
++}
++
++static void
++hal_ReadEFuse_WiFi(
++	PADAPTER	padapter,
++	u16			_offset,
++	u16			_size_byte,
++	u8			*pbuf,
++	u8			bPseudoTest)
++{
++#ifdef HAL_EFUSE_MEMORY
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++	PEFUSE_HAL		pEfuseHal = &pHalData->EfuseHal;
++#endif
++	u8	*efuseTbl = NULL;
++	u16	eFuse_Addr = 0;
++	u8	offset, wden;
++	u8	efuseHeader, efuseExtHdr, efuseData;
++	u16	i, total, used;
++	u8	efuse_usage = 0;
++
++	/* RTW_INFO("YJ: ====>%s():_offset=%d _size_byte=%d bPseudoTest=%d\n", __func__, _offset, _size_byte, bPseudoTest); */
++	/* */
++	/* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
++	/* */
++	if ((_offset + _size_byte) > EFUSE_MAX_MAP_LEN) {
++		RTW_INFO("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __FUNCTION__, _offset, _size_byte);
++		return;
++	}
++
++	efuseTbl = (u8 *)rtw_malloc(EFUSE_MAX_MAP_LEN);
++	if (efuseTbl == NULL) {
++		RTW_INFO("%s: alloc efuseTbl fail!\n", __FUNCTION__);
++		return;
++	}
++	/* 0xff will be efuse default value instead of 0x00. */
++	_rtw_memset(efuseTbl, 0xFF, EFUSE_MAX_MAP_LEN);
++
++
++#ifdef CONFIG_DEBUG
++	if (0) {
++		for (i = 0; i < 256; i++)
++			/* ReadEFuseByte(padapter, i, &efuseTbl[i], _FALSE); */
++			efuse_OneByteRead(padapter, i, &efuseTbl[i], _FALSE);
++		RTW_INFO("Efuse Content:\n");
++		for (i = 0; i < 256; i++) {
++			if (i % 16 == 0)
++				printk(KERN_ERR"\n");
++			printk(KERN_ERR"%02X ", efuseTbl[i]);
++		}
++		printk(KERN_ERR"\n");
++	}
++#endif
++
++
++	/* switch bank back to bank 0 for later BT and wifi use. */
++	hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
++
++	while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
++		/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); */
++		efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
++		if (efuseHeader == 0xFF) {
++			RTW_INFO("%s: data end at address=%#x\n", __FUNCTION__, eFuse_Addr - 1);
++			break;
++		}
++		/* RTW_INFO("%s: efuse[0x%X]=0x%02X\n", __FUNCTION__, eFuse_Addr-1, efuseHeader); */
++
++		/* Check PG header for section num. */
++		if (EXT_HEADER(efuseHeader)) {	/* extended header */
++			offset = GET_HDR_OFFSET_2_0(efuseHeader);
++			/* RTW_INFO("%s: extended header offset=0x%X\n", __FUNCTION__, offset); */
++
++			/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); */
++			efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
++			/* RTW_INFO("%s: efuse[0x%X]=0x%02X\n", __FUNCTION__, eFuse_Addr-1, efuseExtHdr); */
++			if (ALL_WORDS_DISABLED(efuseExtHdr))
++				continue;
++
++			offset |= ((efuseExtHdr & 0xF0) >> 1);
++			wden = (efuseExtHdr & 0x0F);
++		} else {
++			offset = ((efuseHeader >> 4) & 0x0f);
++			wden = (efuseHeader & 0x0f);
++		}
++		/* RTW_INFO("%s: Offset=%d Worden=0x%X\n", __FUNCTION__, offset, wden); */
++
++		if (offset < EFUSE_MAX_SECTION_8723D) {
++			u16 addr;
++			/* Get word enable value from PG header
++			*			RTW_INFO("%s: Offset=%d Worden=0x%X\n", __FUNCTION__, offset, wden); */
++
++			addr = offset * PGPKT_DATA_SIZE;
++			for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
++				/* Check word enable condition in the section */
++				if (!(wden & (0x01 << i))) {
++					efuseData = 0;
++					/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
++					efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
++					/*					RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr-1, efuseData); */
++					efuseTbl[addr] = efuseData;
++
++					efuseData = 0;
++					/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
++					efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
++					/*					RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr-1, efuseData); */
++					efuseTbl[addr + 1] = efuseData;
++				}
++				addr += 2;
++			}
++		} else {
++			RTW_INFO(KERN_ERR "%s: offset(%d) is illegal!!\n", __FUNCTION__, offset);
++			eFuse_Addr += Efuse_CalculateWordCnts(wden) * 2;
++		}
++	}
++
++	/* Copy from Efuse map to output pointer memory!!! */
++	for (i = 0; i < _size_byte; i++)
++		pbuf[i] = efuseTbl[_offset + i];
++
++	/* Calculate Efuse utilization */
++	total = 0;
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest);
++	used = eFuse_Addr - 1;
++	if (total)
++		efuse_usage = (u8)((used * 100) / total);
++	else
++		efuse_usage = 100;
++	if (bPseudoTest) {
++#ifdef HAL_EFUSE_MEMORY
++		pEfuseHal->fakeEfuseUsedBytes = used;
++#else
++		fakeEfuseUsedBytes = used;
++#endif
++	} else {
++		rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&used);
++		rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_USAGE, (u8 *)&efuse_usage);
++	}
++
++	if (efuseTbl)
++		rtw_mfree(efuseTbl, EFUSE_MAX_MAP_LEN);
++}
++
++static void
++hal_ReadEFuse_BT(
++	PADAPTER	padapter,
++	u16			_offset,
++	u16			_size_byte,
++	u8			*pbuf,
++	u8			bPseudoTest
++)
++{
++#ifdef HAL_EFUSE_MEMORY
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++	PEFUSE_HAL		pEfuseHal = &pHalData->EfuseHal;
++#endif
++	u8	*efuseTbl;
++	u8	bank;
++	u16	eFuse_Addr;
++	u8	efuseHeader, efuseExtHdr, efuseData;
++	u8	offset, wden;
++	u16	i, total, used;
++	u8	efuse_usage;
++
++
++	/* */
++	/* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
++	/* */
++	if ((_offset + _size_byte) > EFUSE_BT_MAP_LEN) {
++		RTW_INFO("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __FUNCTION__, _offset, _size_byte);
++		return;
++	}
++
++	efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN);
++	if (efuseTbl == NULL) {
++		RTW_INFO("%s: efuseTbl malloc fail!\n", __FUNCTION__);
++		return;
++	}
++	/* 0xff will be efuse default value instead of 0x00. */
++	_rtw_memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);
++
++	total = 0;
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &total, bPseudoTest);
++
++	for (bank = 1; bank < 3; bank++) { /* 8723d Max bake 0~2 */
++		if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == _FALSE) {
++			RTW_INFO("%s: hal_EfuseSwitchToBank Fail!!\n", __FUNCTION__);
++			goto exit;
++		}
++
++		eFuse_Addr = 0;
++
++		while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
++			/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); */
++			efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
++			if (efuseHeader == 0xFF)
++				break;
++			RTW_INFO("%s: efuse[%#X]=0x%02x (header)\n", __FUNCTION__, (((bank - 1) * EFUSE_REAL_CONTENT_LEN_8723D) + eFuse_Addr - 1), efuseHeader);
++
++			/* Check PG header for section num. */
++			if (EXT_HEADER(efuseHeader)) {	/* extended header */
++				offset = GET_HDR_OFFSET_2_0(efuseHeader);
++				RTW_INFO("%s: extended header offset_2_0=0x%X\n", __FUNCTION__, offset);
++
++				/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); */
++				efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
++				RTW_INFO("%s: efuse[%#X]=0x%02x (ext header)\n", __FUNCTION__, (((bank - 1) * EFUSE_REAL_CONTENT_LEN_8723D) + eFuse_Addr - 1), efuseExtHdr);
++				if (ALL_WORDS_DISABLED(efuseExtHdr))
++					continue;
++
++				offset |= ((efuseExtHdr & 0xF0) >> 1);
++				wden = (efuseExtHdr & 0x0F);
++			} else {
++				offset = ((efuseHeader >> 4) & 0x0f);
++				wden = (efuseHeader & 0x0f);
++			}
++
++			if (offset < EFUSE_BT_MAX_SECTION) {
++				u16 addr;
++
++				/* Get word enable value from PG header */
++				RTW_INFO("%s: Offset=%d Worden=%#X\n", __FUNCTION__, offset, wden);
++
++				addr = offset * PGPKT_DATA_SIZE;
++				for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
++					/* Check word enable condition in the section */
++					if (!(wden & (0x01 << i))) {
++						efuseData = 0;
++						/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
++						efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
++						RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr - 1, efuseData);
++						efuseTbl[addr] = efuseData;
++
++						efuseData = 0;
++						/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
++						efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
++						RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr - 1, efuseData);
++						efuseTbl[addr + 1] = efuseData;
++					}
++					addr += 2;
++				}
++			} else {
++				RTW_INFO("%s: offset(%d) is illegal!!\n", __FUNCTION__, offset);
++				eFuse_Addr += Efuse_CalculateWordCnts(wden) * 2;
++			}
++		}
++
++		if ((eFuse_Addr - 1) < total) {
++			RTW_INFO("%s: bank(%d) data end at %#x\n", __FUNCTION__, bank, eFuse_Addr - 1);
++			break;
++		}
++	}
++
++	/* switch bank back to bank 0 for later BT and wifi use. */
++	hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
++
++	/* Copy from Efuse map to output pointer memory!!! */
++	for (i = 0; i < _size_byte; i++)
++		pbuf[i] = efuseTbl[_offset + i];
++
++	/* */
++	/* Calculate Efuse utilization. */
++	/* */
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest);
++	used = (EFUSE_BT_REAL_BANK_CONTENT_LEN * (bank - 1)) + eFuse_Addr - 1;
++	RTW_INFO("%s: bank(%d) data end at %#x ,used =%d\n", __FUNCTION__, bank, eFuse_Addr - 1, used);
++	efuse_usage = (u8)((used * 100) / total);
++	if (bPseudoTest) {
++#ifdef HAL_EFUSE_MEMORY
++		pEfuseHal->fakeBTEfuseUsedBytes = used;
++#else
++		fakeBTEfuseUsedBytes = used;
++#endif
++	} else {
++		rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&used);
++		rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_USAGE, (u8 *)&efuse_usage);
++	}
++
++exit:
++	if (efuseTbl)
++		rtw_mfree(efuseTbl, EFUSE_BT_MAP_LEN);
++}
++
++static void
++Hal_ReadEFuse(
++	PADAPTER	padapter,
++	u8			efuseType,
++	u16			_offset,
++	u16			_size_byte,
++	u8			*pbuf,
++	u8			bPseudoTest)
++{
++	if (efuseType == EFUSE_WIFI)
++		hal_ReadEFuse_WiFi(padapter, _offset, _size_byte, pbuf, bPseudoTest);
++	else
++		hal_ReadEFuse_BT(padapter, _offset, _size_byte, pbuf, bPseudoTest);
++}
++
++static u16
++hal_EfuseGetCurrentSize_WiFi(
++	PADAPTER	padapter,
++	u8			bPseudoTest)
++{
++#ifdef HAL_EFUSE_MEMORY
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++	PEFUSE_HAL		pEfuseHal = &pHalData->EfuseHal;
++#endif
++	u16	efuse_addr = 0;
++	u16 start_addr = 0; /* for debug */
++	u8	hoffset = 0, hworden = 0;
++	u8	efuse_data, word_cnts = 0;
++	u32 count = 0; /* for debug */
++
++
++	if (bPseudoTest) {
++#ifdef HAL_EFUSE_MEMORY
++		efuse_addr = (u16)pEfuseHal->fakeEfuseUsedBytes;
++#else
++		efuse_addr = (u16)fakeEfuseUsedBytes;
++#endif
++	} else
++		rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
++	start_addr = efuse_addr;
++	RTW_INFO("%s: start_efuse_addr=0x%X\n", __FUNCTION__, efuse_addr);
++
++	/* switch bank back to bank 0 for later BT and wifi use. */
++	hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
++
++#if 0 /* for debug test */
++	efuse_OneByteRead(padapter, 0x1FF, &efuse_data, bPseudoTest);
++	RTW_INFO(FUNC_ADPT_FMT ": efuse raw 0x1FF=0x%02X\n",
++		 FUNC_ADPT_ARG(padapter), efuse_data);
++	efuse_data = 0xFF;
++#endif /* for debug test */
++
++	count = 0;
++	while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
++#if 1
++		if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == _FALSE) {
++			RTW_INFO(KERN_ERR "%s: efuse_OneByteRead Fail! addr=0x%X !!\n", __FUNCTION__, efuse_addr);
++			goto error;
++		}
++#else
++		ReadEFuseByte(padapter, efuse_addr, &efuse_data, bPseudoTest);
++#endif
++
++		if (efuse_data == 0xFF)
++			break;
++
++		if ((start_addr != 0) && (efuse_addr == start_addr)) {
++			count++;
++			RTW_INFO(FUNC_ADPT_FMT ": [WARNING] efuse raw 0x%X=0x%02X not 0xFF!!(%d times)\n",
++				FUNC_ADPT_ARG(padapter), efuse_addr, efuse_data, count);
++
++			efuse_data = 0xFF;
++			if (count < 4) {
++				/* try again! */
++
++				if (count > 2) {
++					/* try again form address 0 */
++					efuse_addr = 0;
++					start_addr = 0;
++				}
++
++				continue;
++			}
++
++			goto error;
++		}
++
++		if (EXT_HEADER(efuse_data)) {
++			hoffset = GET_HDR_OFFSET_2_0(efuse_data);
++			efuse_addr++;
++			efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
++			if (ALL_WORDS_DISABLED(efuse_data))
++				continue;
++
++			hoffset |= ((efuse_data & 0xF0) >> 1);
++			hworden = efuse_data & 0x0F;
++		} else {
++			hoffset = (efuse_data >> 4) & 0x0F;
++			hworden = efuse_data & 0x0F;
++		}
++
++		word_cnts = Efuse_CalculateWordCnts(hworden);
++		efuse_addr += (word_cnts * 2) + 1;
++	}
++
++	if (bPseudoTest) {
++#ifdef HAL_EFUSE_MEMORY
++		pEfuseHal->fakeEfuseUsedBytes = efuse_addr;
++#else
++		fakeEfuseUsedBytes = efuse_addr;
++#endif
++	} else
++		rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
++
++	goto exit;
++
++error:
++	/* report max size to prevent write efuse */
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_addr, bPseudoTest);
++
++exit:
++	RTW_INFO("%s: CurrentSize=%d\n", __FUNCTION__, efuse_addr);
++
++	return efuse_addr;
++}
++
++static u16
++hal_EfuseGetCurrentSize_BT(
++	PADAPTER	padapter,
++	u8			bPseudoTest)
++{
++#ifdef HAL_EFUSE_MEMORY
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++	PEFUSE_HAL		pEfuseHal = &pHalData->EfuseHal;
++#endif
++	u16 btusedbytes;
++	u16	efuse_addr;
++	u8	bank, startBank;
++	u8	hoffset = 0, hworden = 0;
++	u8	efuse_data, word_cnts = 0;
++	u16	retU2 = 0;
++	u8 bContinual = _TRUE;
++
++
++	if (bPseudoTest) {
++#ifdef HAL_EFUSE_MEMORY
++		btusedbytes = pEfuseHal->fakeBTEfuseUsedBytes;
++#else
++		btusedbytes = fakeBTEfuseUsedBytes;
++#endif
++	} else {
++		btusedbytes = 0;
++		rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&btusedbytes);
++	}
++	efuse_addr = (u16)((btusedbytes % EFUSE_BT_REAL_BANK_CONTENT_LEN));
++	startBank = (u8)(1 + (btusedbytes / EFUSE_BT_REAL_BANK_CONTENT_LEN));
++
++	RTW_INFO("%s: start from bank=%d addr=0x%X\n", __FUNCTION__, startBank, efuse_addr);
++
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &retU2, bPseudoTest);
++
++	for (bank = startBank; bank < 3; bank++) {
++		if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == _FALSE) {
++			RTW_INFO(KERN_ERR "%s: switch bank(%d) Fail!!\n", __FUNCTION__, bank);
++			/* bank = EFUSE_MAX_BANK; */
++			break;
++		}
++
++		/* only when bank is switched we have to reset the efuse_addr. */
++		if (bank != startBank)
++			efuse_addr = 0;
++#if 1
++
++		while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
++			if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == _FALSE) {
++				RTW_INFO(KERN_ERR "%s: efuse_OneByteRead Fail! addr=0x%X !!\n", __FUNCTION__, efuse_addr);
++				/* bank = EFUSE_MAX_BANK; */
++				break;
++			}
++			RTW_INFO("%s: efuse_OneByteRead ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank);
++
++			if (efuse_data == 0xFF)
++				break;
++
++			if (EXT_HEADER(efuse_data)) {
++				hoffset = GET_HDR_OFFSET_2_0(efuse_data);
++				efuse_addr++;
++				efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
++				RTW_INFO("%s: efuse_OneByteRead EXT_HEADER ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank);
++
++				if (ALL_WORDS_DISABLED(efuse_data)) {
++					efuse_addr++;
++					continue;
++				}
++
++				/*				hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); */
++				hoffset |= ((efuse_data & 0xF0) >> 1);
++				hworden = efuse_data & 0x0F;
++			} else {
++				hoffset = (efuse_data >> 4) & 0x0F;
++				hworden =  efuse_data & 0x0F;
++			}
++
++			RTW_INFO(FUNC_ADPT_FMT": Offset=%d Worden=%#X\n",
++				 FUNC_ADPT_ARG(padapter), hoffset, hworden);
++
++			word_cnts = Efuse_CalculateWordCnts(hworden);
++			/* read next header */
++			efuse_addr += (word_cnts * 2) + 1;
++		}
++#else
++		while (bContinual &&
++		       efuse_OneByteRead(padapter, efuse_addr , &efuse_data, bPseudoTest) &&
++		       AVAILABLE_EFUSE_ADDR(efuse_addr)) {
++			if (efuse_data != 0xFF) {
++				if ((efuse_data & 0x1F) == 0x0F) {	/* extended header */
++					hoffset = efuse_data;
++					efuse_addr++;
++					efuse_OneByteRead(padapter, efuse_addr , &efuse_data, bPseudoTest);
++					if ((efuse_data & 0x0F) == 0x0F) {
++						efuse_addr++;
++						continue;
++					} else {
++						hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
++						hworden = efuse_data & 0x0F;
++					}
++				} else {
++					hoffset = (efuse_data >> 4) & 0x0F;
++					hworden =  efuse_data & 0x0F;
++				}
++				word_cnts = Efuse_CalculateWordCnts(hworden);
++				/* read next header							 */
++				efuse_addr = efuse_addr + (word_cnts * 2) + 1;
++			} else
++				bContinual = _FALSE;
++		}
++#endif
++
++
++		/* Check if we need to check next bank efuse */
++		if (efuse_addr < retU2)
++			break;/* don't need to check next bank. */
++	}
++#if 0
++	retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;
++	if (bPseudoTest) {
++#ifdef HAL_EFUSE_MEMORY
++		pEfuseHal->fakeBTEfuseUsedBytes = retU2;
++#else
++		fakeBTEfuseUsedBytes = retU2;
++#endif
++	} else
++		rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&retU2);
++#else
++	retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;
++	if (bPseudoTest) {
++		pEfuseHal->fakeBTEfuseUsedBytes = retU2;
++		/* RT_DISP(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT92C(), already use %u bytes\n", pEfuseHal->fakeBTEfuseUsedBytes)); */
++	} else {
++		pEfuseHal->BTEfuseUsedBytes = retU2;
++		/* RT_DISP(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT92C(), already use %u bytes\n", pEfuseHal->BTEfuseUsedBytes)); */
++	}
++#endif
++
++	RTW_INFO("%s: CurrentSize=%d\n", __FUNCTION__, retU2);
++	return retU2;
++}
++
++static u16
++Hal_EfuseGetCurrentSize(
++	PADAPTER	pAdapter,
++	u8			efuseType,
++	u8			bPseudoTest)
++{
++	u16	ret = 0;
++
++	if (efuseType == EFUSE_WIFI)
++		ret = hal_EfuseGetCurrentSize_WiFi(pAdapter, bPseudoTest);
++	else
++		ret = hal_EfuseGetCurrentSize_BT(pAdapter, bPseudoTest);
++
++	return ret;
++}
++
++static u8
++Hal_EfuseWordEnableDataWrite(
++	PADAPTER	padapter,
++	u16			efuse_addr,
++	u8			word_en,
++	u8			*data,
++	u8			bPseudoTest)
++{
++	u16	tmpaddr = 0;
++	u16	start_addr = efuse_addr;
++	u8	badworden = 0x0F;
++	u8	tmpdata[PGPKT_DATA_SIZE];
++
++
++	/*	RTW_INFO("%s: efuse_addr=%#x word_en=%#x\n", __FUNCTION__, efuse_addr, word_en); */
++	_rtw_memset(tmpdata, 0xFF, PGPKT_DATA_SIZE);
++
++	if (!(word_en & BIT(0))) {
++		tmpaddr = start_addr;
++		efuse_OneByteWrite(padapter, start_addr++, data[0], bPseudoTest);
++		efuse_OneByteWrite(padapter, start_addr++, data[1], bPseudoTest);
++
++		efuse_OneByteRead(padapter, tmpaddr, &tmpdata[0], bPseudoTest);
++		efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[1], bPseudoTest);
++		if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1]))
++			badworden &= (~BIT(0));
++	}
++	if (!(word_en & BIT(1))) {
++		tmpaddr = start_addr;
++		efuse_OneByteWrite(padapter, start_addr++, data[2], bPseudoTest);
++		efuse_OneByteWrite(padapter, start_addr++, data[3], bPseudoTest);
++
++		efuse_OneByteRead(padapter, tmpaddr, &tmpdata[2], bPseudoTest);
++		efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[3], bPseudoTest);
++		if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3]))
++			badworden &= (~BIT(1));
++	}
++	if (!(word_en & BIT(2))) {
++		tmpaddr = start_addr;
++		efuse_OneByteWrite(padapter, start_addr++, data[4], bPseudoTest);
++		efuse_OneByteWrite(padapter, start_addr++, data[5], bPseudoTest);
++
++		efuse_OneByteRead(padapter, tmpaddr, &tmpdata[4], bPseudoTest);
++		efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[5], bPseudoTest);
++		if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5]))
++			badworden &= (~BIT(2));
++	}
++	if (!(word_en & BIT(3))) {
++		tmpaddr = start_addr;
++		efuse_OneByteWrite(padapter, start_addr++, data[6], bPseudoTest);
++		efuse_OneByteWrite(padapter, start_addr++, data[7], bPseudoTest);
++
++		efuse_OneByteRead(padapter, tmpaddr, &tmpdata[6], bPseudoTest);
++		efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[7], bPseudoTest);
++		if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7]))
++			badworden &= (~BIT(3));
++	}
++
++	return badworden;
++}
++
++static s32
++Hal_EfusePgPacketRead(
++	PADAPTER	padapter,
++	u8			offset,
++	u8			*data,
++	u8			bPseudoTest)
++{
++	u8	bDataEmpty = _TRUE;
++	u8	efuse_data, word_cnts = 0;
++	u16	efuse_addr = 0;
++	u8	hoffset = 0, hworden = 0;
++	u8	i;
++	u8	max_section = 0;
++	s32	ret;
++
++
++	if (data == NULL)
++		return _FALSE;
++
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION, &max_section, bPseudoTest);
++	if (offset > max_section) {
++		RTW_INFO("%s: Packet offset(%d) is illegal(>%d)!\n", __FUNCTION__, offset, max_section);
++		return _FALSE;
++	}
++
++	_rtw_memset(data, 0xFF, PGPKT_DATA_SIZE);
++	ret = _TRUE;
++
++	/* */
++	/* <Roger_TODO> Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. */
++	/* Skip dummy parts to prevent unexpected data read from Efuse. */
++	/* By pass right now. 2009.02.19. */
++	/* */
++	while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
++		if (efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest) == _FALSE) {
++			ret = _FALSE;
++			break;
++		}
++
++		if (efuse_data == 0xFF)
++			break;
++
++		if (EXT_HEADER(efuse_data)) {
++			hoffset = GET_HDR_OFFSET_2_0(efuse_data);
++			efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
++			if (ALL_WORDS_DISABLED(efuse_data)) {
++				RTW_INFO("%s: Error!! All words disabled!\n", __FUNCTION__);
++				continue;
++			}
++
++			hoffset |= ((efuse_data & 0xF0) >> 1);
++			hworden = efuse_data & 0x0F;
++		} else {
++			hoffset = (efuse_data >> 4) & 0x0F;
++			hworden =  efuse_data & 0x0F;
++		}
++
++		if (hoffset == offset) {
++			for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
++				/* Check word enable condition in the section */
++				if (!(hworden & (0x01 << i))) {
++					/* ReadEFuseByte(padapter, efuse_addr++, &efuse_data, bPseudoTest); */
++					efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
++					/*					RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, efuse_addr+tmpidx, efuse_data); */
++					data[i * 2] = efuse_data;
++
++					/* ReadEFuseByte(padapter, efuse_addr++, &efuse_data, bPseudoTest); */
++					efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
++					/*					RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, efuse_addr+tmpidx, efuse_data); */
++					data[(i * 2) + 1] = efuse_data;
++				}
++			}
++		} else {
++			word_cnts = Efuse_CalculateWordCnts(hworden);
++			efuse_addr += word_cnts * 2;
++		}
++	}
++
++	return ret;
++}
++
++static u8
++hal_EfusePgCheckAvailableAddr(
++	PADAPTER	pAdapter,
++	u8			efuseType,
++	u8		bPseudoTest)
++{
++	u16	max_available = 0;
++	u16 current_size;
++
++
++	EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &max_available, bPseudoTest);
++	/*	RTW_INFO("%s: max_available=%d\n", __FUNCTION__, max_available); */
++
++	current_size = Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest);
++	if (current_size >= max_available) {
++		RTW_INFO("%s: Error!! current_size(%d)>max_available(%d)\n", __FUNCTION__, current_size, max_available);
++		return _FALSE;
++	}
++	return _TRUE;
++}
++
++static void
++hal_EfuseConstructPGPkt(
++	u8				offset,
++	u8				word_en,
++	u8				*pData,
++	PPGPKT_STRUCT	pTargetPkt)
++{
++	_rtw_memset(pTargetPkt->data, 0xFF, PGPKT_DATA_SIZE);
++	pTargetPkt->offset = offset;
++	pTargetPkt->word_en = word_en;
++	efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data);
++	pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
++}
++
++#if 0
++static u8
++wordEnMatched(
++	PPGPKT_STRUCT	pTargetPkt,
++	PPGPKT_STRUCT	pCurPkt,
++	u8				*pWden)
++{
++	u8	match_word_en = 0x0F;	/* default all words are disabled */
++	u8	i;
++
++	/* check if the same words are enabled both target and current PG packet */
++	if (((pTargetPkt->word_en & BIT(0)) == 0) &&
++	    ((pCurPkt->word_en & BIT(0)) == 0)) {
++		match_word_en &= ~BIT(0);				/* enable word 0 */
++	}
++	if (((pTargetPkt->word_en & BIT(1)) == 0) &&
++	    ((pCurPkt->word_en & BIT(1)) == 0)) {
++		match_word_en &= ~BIT(1);				/* enable word 1 */
++	}
++	if (((pTargetPkt->word_en & BIT(2)) == 0) &&
++	    ((pCurPkt->word_en & BIT(2)) == 0)) {
++		match_word_en &= ~BIT(2);				/* enable word 2 */
++	}
++	if (((pTargetPkt->word_en & BIT(3)) == 0) &&
++	    ((pCurPkt->word_en & BIT(3)) == 0)) {
++		match_word_en &= ~BIT(3);				/* enable word 3 */
++	}
++
++	*pWden = match_word_en;
++
++	if (match_word_en != 0xf)
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++static u8
++hal_EfuseCheckIfDatafollowed(
++	PADAPTER		pAdapter,
++	u8				word_cnts,
++	u16				startAddr,
++	u8				bPseudoTest)
++{
++	u8 bRet = _FALSE;
++	u8 i, efuse_data;
++
++	for (i = 0; i < (word_cnts * 2); i++) {
++		if (efuse_OneByteRead(pAdapter, (startAddr + i) , &efuse_data, bPseudoTest) == _FALSE) {
++			RTW_INFO("%s: efuse_OneByteRead FAIL!!\n", __FUNCTION__);
++			bRet = _TRUE;
++			break;
++		}
++
++		if (efuse_data != 0xFF) {
++			bRet = _TRUE;
++			break;
++		}
++	}
++
++	return bRet;
++}
++#endif
++
++static u8
++hal_EfusePartialWriteCheck(
++	PADAPTER		padapter,
++	u8				efuseType,
++	u16				*pAddr,
++	PPGPKT_STRUCT	pTargetPkt,
++	u8				bPseudoTest)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++	PEFUSE_HAL		pEfuseHal = &pHalData->EfuseHal;
++	u8	bRet = _FALSE;
++	u16	startAddr = 0, efuse_max_available_len = 0, efuse_max = 0;
++	u8	efuse_data = 0;
++#if 0
++	u8	i, cur_header = 0;
++	u8	new_wden = 0, matched_wden = 0, badworden = 0;
++	PGPKT_STRUCT	curPkt;
++#endif
++
++
++	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_max_available_len, bPseudoTest);
++	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_CONTENT_LEN_BANK, &efuse_max, bPseudoTest);
++
++	if (efuseType == EFUSE_WIFI) {
++		if (bPseudoTest) {
++#ifdef HAL_EFUSE_MEMORY
++			startAddr = (u16)pEfuseHal->fakeEfuseUsedBytes;
++#else
++			startAddr = (u16)fakeEfuseUsedBytes;
++#endif
++		} else
++			rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr);
++	} else {
++		if (bPseudoTest) {
++#ifdef HAL_EFUSE_MEMORY
++			startAddr = (u16)pEfuseHal->fakeBTEfuseUsedBytes;
++#else
++			startAddr = (u16)fakeBTEfuseUsedBytes;
++#endif
++		} else
++			rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&startAddr);
++	}
++	startAddr %= efuse_max;
++	RTW_INFO("%s: startAddr=%#X\n", __FUNCTION__, startAddr);
++
++	while (1) {
++		if (startAddr >= efuse_max_available_len) {
++			bRet = _FALSE;
++			RTW_INFO("%s: startAddr(%d) >= efuse_max_available_len(%d)\n",
++				__FUNCTION__, startAddr, efuse_max_available_len);
++			break;
++		}
++
++		if (efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest) && (efuse_data != 0xFF)) {
++#if 1
++			bRet = _FALSE;
++			RTW_INFO("%s: Something Wrong! last bytes(%#X=0x%02X) is not 0xFF\n",
++				 __FUNCTION__, startAddr, efuse_data);
++			break;
++#else
++			if (EXT_HEADER(efuse_data)) {
++				cur_header = efuse_data;
++				startAddr++;
++				efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest);
++				if (ALL_WORDS_DISABLED(efuse_data)) {
++					RTW_INFO("%s: Error condition, all words disabled!", __FUNCTION__);
++					bRet = _FALSE;
++					break;
++				} /*else*/
++				{
++					curPkt.offset = ((cur_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
++					curPkt.word_en = efuse_data & 0x0F;
++				}
++			} else {
++				cur_header  =  efuse_data;
++				curPkt.offset = (cur_header >> 4) & 0x0F;
++				curPkt.word_en = cur_header & 0x0F;
++			}
++
++			curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en);
++			/* if same header is found but no data followed */
++			/* write some part of data followed by the header. */
++			if ((curPkt.offset == pTargetPkt->offset) &&
++			    (hal_EfuseCheckIfDatafollowed(padapter, curPkt.word_cnts, startAddr + 1, bPseudoTest) == _FALSE) &&
++			    wordEnMatched(pTargetPkt, &curPkt, &matched_wden) == _TRUE) {
++				RTW_INFO("%s: Need to partial write data by the previous wrote header\n", __FUNCTION__);
++				/* Here to write partial data */
++				badworden = Efuse_WordEnableDataWrite(padapter, startAddr + 1, matched_wden, pTargetPkt->data, bPseudoTest);
++				if (badworden != 0x0F) {
++					u32	PgWriteSuccess = 0;
++					/* if write fail on some words, write these bad words again */
++					if (efuseType == EFUSE_WIFI)
++						PgWriteSuccess = Efuse_PgPacketWrite(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
++					else
++						PgWriteSuccess = Efuse_PgPacketWrite_BT(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
++
++					if (!PgWriteSuccess) {
++						bRet = _FALSE;	/* write fail, return */
++						break;
++					}
++				}
++				/* partial write ok, update the target packet for later use */
++				for (i = 0; i < 4; i++) {
++					if ((matched_wden & (0x1 << i)) == 0) {	/* this word has been written */
++						pTargetPkt->word_en |= (0x1 << i);	/* disable the word */
++					}
++				}
++				pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
++			}
++			/* read from next header */
++			startAddr = startAddr + (curPkt.word_cnts * 2) + 1;
++#endif
++		} else {
++			/* not used header, 0xff */
++			*pAddr = startAddr;
++			/*			RTW_INFO("%s: Started from unused header offset=%d\n", __FUNCTION__, startAddr)); */
++			bRet = _TRUE;
++			break;
++		}
++	}
++
++	return bRet;
++}
++
++static u8
++hal_EfusePgPacketWrite1ByteHeader(
++	PADAPTER		pAdapter,
++	u8				efuseType,
++	u16				*pAddr,
++	PPGPKT_STRUCT	pTargetPkt,
++	u8				bPseudoTest)
++{
++	u8	bRet = _FALSE;
++	u8	pg_header = 0, tmp_header = 0;
++	u16	efuse_addr = *pAddr;
++	u8	repeatcnt = 0;
++
++
++	/*	RTW_INFO("%s\n", __FUNCTION__); */
++	pg_header = ((pTargetPkt->offset << 4) & 0xf0) | pTargetPkt->word_en;
++
++	do {
++		efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
++		efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
++		if (tmp_header != 0xFF)
++			break;
++		if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
++			RTW_INFO("%s: Repeat over limit for pg_header!!\n", __FUNCTION__);
++			return _FALSE;
++		}
++	} while (1);
++
++	if (tmp_header != pg_header) {
++		RTW_INFO(KERN_ERR "%s: PG Header Fail!!(pg=0x%02X read=0x%02X)\n", __FUNCTION__, pg_header, tmp_header);
++		return _FALSE;
++	}
++
++	*pAddr = efuse_addr;
++
++	return _TRUE;
++}
++
++static u8
++hal_EfusePgPacketWrite2ByteHeader(
++	PADAPTER		padapter,
++	u8				efuseType,
++	u16				*pAddr,
++	PPGPKT_STRUCT	pTargetPkt,
++	u8				bPseudoTest)
++{
++	u16	efuse_addr, efuse_max_available_len = 0;
++	u8	pg_header = 0, tmp_header = 0;
++	u8	repeatcnt = 0;
++
++
++	/*	RTW_INFO("%s\n", __FUNCTION__); */
++	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &efuse_max_available_len, bPseudoTest);
++
++	efuse_addr = *pAddr;
++	if (efuse_addr >= efuse_max_available_len) {
++		RTW_INFO("%s: addr(%d) over available(%d)!!\n", __FUNCTION__, efuse_addr, efuse_max_available_len);
++		return _FALSE;
++	}
++
++	pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F;
++	/*	RTW_INFO("%s: pg_header=0x%x\n", __FUNCTION__, pg_header); */
++
++	do {
++		efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
++		efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
++		if (tmp_header != 0xFF)
++			break;
++		if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
++			RTW_INFO("%s: Repeat over limit for pg_header!!\n", __FUNCTION__);
++			return _FALSE;
++		}
++	} while (1);
++
++	if (tmp_header != pg_header) {
++		RTW_INFO(KERN_ERR "%s: PG Header Fail!!(pg=0x%02X read=0x%02X)\n", __FUNCTION__, pg_header, tmp_header);
++		return _FALSE;
++	}
++
++	/* to write ext_header */
++	efuse_addr++;
++	pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en;
++
++	do {
++		efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
++		efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
++		if (tmp_header != 0xFF)
++			break;
++		if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
++			RTW_INFO("%s: Repeat over limit for ext_header!!\n", __FUNCTION__);
++			return _FALSE;
++		}
++	} while (1);
++
++	if (tmp_header != pg_header) {	/* offset PG fail */
++		RTW_INFO(KERN_ERR "%s: PG EXT Header Fail!!(pg=0x%02X read=0x%02X)\n", __FUNCTION__, pg_header, tmp_header);
++		return _FALSE;
++	}
++
++	*pAddr = efuse_addr;
++
++	return _TRUE;
++}
++
++static u8
++hal_EfusePgPacketWriteHeader(
++	PADAPTER		padapter,
++	u8				efuseType,
++	u16				*pAddr,
++	PPGPKT_STRUCT	pTargetPkt,
++	u8				bPseudoTest)
++{
++	u8 bRet = _FALSE;
++
++	if (pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE)
++		bRet = hal_EfusePgPacketWrite2ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
++	else
++		bRet = hal_EfusePgPacketWrite1ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
++
++	return bRet;
++}
++
++static u8
++hal_EfusePgPacketWriteData(
++	PADAPTER		pAdapter,
++	u8				efuseType,
++	u16				*pAddr,
++	PPGPKT_STRUCT	pTargetPkt,
++	u8				bPseudoTest)
++{
++	u16	efuse_addr;
++	u8	badworden;
++
++
++	efuse_addr = *pAddr;
++	badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr + 1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest);
++	if (badworden != 0x0F) {
++		RTW_INFO("%s: Fail!!\n", __FUNCTION__);
++		return _FALSE;
++	}
++
++	/*	RTW_INFO("%s: ok\n", __FUNCTION__); */
++	return _TRUE;
++}
++
++static s32
++Hal_EfusePgPacketWrite(
++	PADAPTER	padapter,
++	u8			offset,
++	u8			word_en,
++	u8			*pData,
++	u8			bPseudoTest)
++{
++	PGPKT_STRUCT targetPkt;
++	u16 startAddr = 0;
++	u8 efuseType = EFUSE_WIFI;
++
++	if (!hal_EfusePgCheckAvailableAddr(padapter, efuseType, bPseudoTest))
++		return _FALSE;
++
++	hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
++
++	if (!hal_EfusePartialWriteCheck(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
++		return _FALSE;
++
++	if (!hal_EfusePgPacketWriteHeader(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
++		return _FALSE;
++
++	if (!hal_EfusePgPacketWriteData(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
++		return _FALSE;
++
++	return _TRUE;
++}
++
++static u8
++Hal_EfusePgPacketWrite_BT(
++	PADAPTER	pAdapter,
++	u8			offset,
++	u8			word_en,
++	u8			*pData,
++	u8			bPseudoTest)
++{
++	PGPKT_STRUCT targetPkt;
++	u16 startAddr = 0;
++	u8 efuseType = EFUSE_BT;
++
++	if (!hal_EfusePgCheckAvailableAddr(pAdapter, efuseType, bPseudoTest))
++		return _FALSE;
++
++	hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
++
++	if (!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
++		return _FALSE;
++
++	if (!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
++		return _FALSE;
++
++	if (!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
++		return _FALSE;
++
++	return _TRUE;
++}
++
++
++static void read_chip_version_8723d(PADAPTER padapter)
++{
++	u32				value32;
++	HAL_DATA_TYPE	*pHalData;
++
++	pHalData = GET_HAL_DATA(padapter);
++
++	value32 = rtw_read32(padapter, REG_SYS_CFG);
++	pHalData->version_id.ICType = CHIP_8723D;
++	pHalData->version_id.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
++	pHalData->version_id.RFType = RF_TYPE_1T1R;
++	pHalData->version_id.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
++	pHalData->version_id.CUTVersion = (value32 & CHIP_VER_RTL_MASK) >> CHIP_VER_RTL_SHIFT; /* IC version (CUT) */
++
++	/* For regulator mode. by tynli. 2011.01.14 */
++	pHalData->RegulatorMode = ((value32 & SPS_SEL) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
++
++	value32 = rtw_read32(padapter, REG_GPIO_OUTSTS);
++	pHalData->version_id.ROMVer = ((value32 & RF_RL_ID) >> 20);	/* ROM code version. */
++
++	/* For multi-function consideration. Added by Roger, 2010.10.06. */
++	pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
++	value32 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL);
++	pHalData->MultiFunc |= ((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0);
++	pHalData->MultiFunc |= ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0);
++	pHalData->MultiFunc |= ((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0);
++	pHalData->PolarityCtl = ((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT);
++
++	/*
++		if( IS_B_CUT(pHalData->version_id) || IS_C_CUT(pHalData->version_id))
++		{
++			RTW_INFO(" IS_B/C_CUT SWR up 1 level !!!!!!!!!!!!!!!!!\n");
++			phy_set_mac_reg(padapter, 0x14, BIT(23)|BIT(22)|BIT(21)|BIT(20), 0x5);
++		}else if ( IS_D_CUT(pHalData->version_id))
++		{
++			RTW_INFO(" IS_D_CUT SKIP SWR !!!!!!!!!!!!!!!!!\n");
++		}
++	*/
++
++#if 1
++	dump_chip_info(pHalData->version_id);
++#endif
++
++}
++
++
++void rtl8723d_InitBeaconParameters(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++	u16 val16;
++	u8 val8;
++
++
++	val8 = DIS_TSF_UDT;
++	val16 = val8 | (val8 << 8); /* port0 and port1 */
++#ifdef CONFIG_BT_COEXIST
++	/* Enable prot0 beacon function for PSTDMA */
++	val16 |= EN_BCN_FUNCTION;
++#endif
++
++#ifdef CONFIG_CONCURRENT_MODE
++	val16 |= (EN_BCN_FUNCTION << 8);
++#endif
++	rtw_write16(padapter, REG_BCN_CTRL, val16);
++
++	/* TBTT setup time */
++	rtw_write8(padapter, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME);
++
++	/* TBTT hold time: 0x540[19:8] */
++	rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);
++	rtw_write8(padapter, REG_TBTT_PROHIBIT + 2,
++		(rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8));
++
++	/* Firmware will control REG_DRVERLYINT when power saving is enable, */
++	/* so don't set this register on STA mode. */
++	if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _FALSE)
++		rtw_write8(padapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME_8723D); /* 5ms */
++	rtw_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME_8723D); /* 2ms */
++
++	/* Suggested by designer timchen. Change beacon AIFS to the largest number */
++	/* beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */
++	rtw_write16(padapter, REG_BCNTCFG, 0x4413);
++
++}
++
++void rtl8723d_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode)
++{
++#ifdef CONFIG_ADHOC_WORKAROUND_SETTING
++	rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF);
++#else
++	/* rtw_write8(Adapter, REG_BCN_MAX_ERR, (InfraMode ? 0xFF : 0x10)); */
++#endif
++}
++
++void _InitMacAPLLSetting_8723D(PADAPTER Adapter)
++{
++
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
++	u16 RegValue;
++	u8	afe;
++
++	RegValue = rtw_read16(Adapter, REG_AFE_CTRL_4_8723D);
++	RegValue |= BIT(4);
++	RegValue |= BIT(15);
++	rtw_write16(Adapter, REG_AFE_CTRL_4_8723D, RegValue);
++
++	/*
++	 *	8723D with 24MHz xtal has VCO noise issue
++	 *  This will cause some TRx test fail
++	 *	Therefore, set MAC GM parameter for 24MHz xtal
++	 *	AFE[0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ] =
++	 *	[ 40M 25M 13M 19.2M 20M 26M 38.4M 17.664M 16M 14.318M 12M 52M 48M 27M 24M ]
++	 */
++	afe = (pHalData->efuse_eeprom_data[4] >>4);
++	if( afe == 14) {
++		rtw_write32(Adapter, 0x2c, (rtw_read32(Adapter, 0x2c) | BIT28));
++		rtw_write32(Adapter, 0x24, (rtw_read32(Adapter, 0x24) & 0xFFFFFF0F));
++		rtw_write32(Adapter, 0x7c, ((rtw_read32(Adapter, 0x7c) | BIT29) & (~BIT28)));
++	}
++
++}
++
++static void _BeaconFunctionEnable(PADAPTER padapter, u8 Enable, u8 Linked)
++{
++	rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
++	rtw_write8(padapter, REG_RD_CTRL + 1, 0x6F);
++}
++
++static void rtl8723d_SetBeaconRelatedRegisters(PADAPTER padapter)
++{
++	u8 val8;
++	u32 value32;
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
++	u32 bcn_ctrl_reg;
++
++	/* reset TSF, enable update TSF, correcting TSF On Beacon */
++
++	/* REG_MBSSID_BCN_SPACE */
++	/* REG_BCNDMATIM */
++	/* REG_ATIMWND */
++	/* REG_TBTT_PROHIBIT */
++	/* REG_DRVERLYINT */
++	/* REG_BCN_MAX_ERR */
++	/* REG_BCNTCFG //(0x510) */
++	/* REG_DUAL_TSF_RST */
++	/* REG_BCN_CTRL //(0x550) */
++
++
++	bcn_ctrl_reg = REG_BCN_CTRL;
++#ifdef CONFIG_CONCURRENT_MODE
++	if (padapter->hw_port == HW_PORT1)
++		bcn_ctrl_reg = REG_BCN_CTRL_1;
++#endif
++
++	/* */
++	/* ATIM window */
++	/* */
++	rtw_write16(padapter, REG_ATIMWND, 2);
++
++	/* */
++	/* Beacon interval (in unit of TU). */
++	/* */
++	rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)&pmlmeinfo->bcn_interval);
++
++	rtl8723d_InitBeaconParameters(padapter);
++
++	rtw_write8(padapter, REG_SLOT, 0x09);
++
++	/* */
++	/* Reset TSF Timer to zero, added by Roger. 2008.06.24 */
++	/* */
++	value32 = rtw_read32(padapter, REG_TCR);
++	value32 &= ~TSFRST;
++	rtw_write32(padapter, REG_TCR, value32);
++
++	value32 |= TSFRST;
++	rtw_write32(padapter, REG_TCR, value32);
++
++	/* NOTE: Fix test chip's bug (about contention windows's randomness) */
++	if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE | WIFI_MESH_STATE) == _TRUE) {
++		rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
++		rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
++	}
++
++	_BeaconFunctionEnable(padapter, _TRUE, _TRUE);
++
++	ResumeTxBeacon(padapter);
++	val8 = rtw_read8(padapter, bcn_ctrl_reg);
++	val8 |= DIS_BCNQ_SUB;
++	rtw_write8(padapter, bcn_ctrl_reg, val8);
++}
++
++void hal_notch_filter_8723d(_adapter *adapter, bool enable)
++{
++	if (enable) {
++		RTW_INFO("Enable notch filter\n");
++		rtw_write8(adapter, rOFDM0_RxDSP + 1, rtw_read8(adapter, rOFDM0_RxDSP + 1) | BIT(1));
++	} else {
++		RTW_INFO("Disable notch filter\n");
++		rtw_write8(adapter, rOFDM0_RxDSP + 1, rtw_read8(adapter, rOFDM0_RxDSP + 1) & ~BIT(1));
++	}
++}
++
++/*
++ * Description: In normal chip, we should send some packet to Hw which will be used by Fw
++ *			in FW LPS mode. The function is to fill the Tx descriptor of this packets, then
++ *			Fw can tell Hw to send these packet derectly.
++ * Added by tynli. 2009.10.15.
++ *
++ * type1:pspoll, type2:null */
++void rtl8723d_fill_fake_txdesc(
++	PADAPTER	padapter,
++	u8			*pDesc,
++	u32			BufferLen,
++	u8			IsPsPoll,
++	u8			IsBTQosNull,
++	u8			bDataFrame)
++{
++	/* Clear all status */
++	_rtw_memset(pDesc, 0, TXDESC_SIZE);
++
++	SET_TX_DESC_OFFSET_8723D(pDesc, 0x28); /* Offset = 32 */
++
++	SET_TX_DESC_PKT_SIZE_8723D(pDesc, BufferLen); /* Buffer size + command header */
++	SET_TX_DESC_QUEUE_SEL_8723D(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */
++
++	/* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw. */
++	if (_TRUE == IsPsPoll)
++		SET_TX_DESC_NAV_USE_HDR_8723D(pDesc, 1);
++	else {
++		SET_TX_DESC_HWSEQ_EN_8723D(pDesc, 1); /* Hw set sequence number */
++		SET_TX_DESC_HWSEQ_SEL_8723D(pDesc, 0);
++	}
++
++	if (_TRUE == IsBTQosNull)
++		SET_TX_DESC_BT_INT_8723D(pDesc, 1);
++
++	SET_TX_DESC_USE_RATE_8723D(pDesc, 1); /* use data rate which is set by Sw */
++
++	SET_TX_DESC_TX_RATE_8723D(pDesc, DESC8723D_RATE1M);
++
++	/* */
++	/* Encrypt the data frame if under security mode excepct null data. Suggested by CCW. */
++	/* */
++	if (_TRUE == bDataFrame) {
++		u32 EncAlg;
++
++		EncAlg = padapter->securitypriv.dot11PrivacyAlgrthm;
++		switch (EncAlg) {
++		case _NO_PRIVACY_:
++			SET_TX_DESC_SEC_TYPE_8723D(pDesc, 0x0);
++			break;
++		case _WEP40_:
++		case _WEP104_:
++		case _TKIP_:
++			SET_TX_DESC_SEC_TYPE_8723D(pDesc, 0x1);
++			break;
++		case _SMS4_:
++			SET_TX_DESC_SEC_TYPE_8723D(pDesc, 0x2);
++			break;
++		case _AES_:
++			SET_TX_DESC_SEC_TYPE_8723D(pDesc, 0x3);
++			break;
++		default:
++			SET_TX_DESC_SEC_TYPE_8723D(pDesc, 0x0);
++			break;
++		}
++	}
++
++#if defined(CONFIG_USB_HCI)
++	/*
++	 * USB interface drop packet if the checksum of descriptor isn't correct.
++	 * Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.).
++	 */
++	rtl8723d_cal_txdesc_chksum((struct tx_desc *)pDesc);
++#endif
++}
++
++void rtl8723d_InitAntenna_Selection(PADAPTER padapter)
++{
++	rtw_write8(padapter, REG_LEDCFG2, 0x82);
++}
++
++void rtl8723d_CheckAntenna_Selection(PADAPTER padapter)
++{
++#if 0
++	PHAL_DATA_TYPE pHalData;
++	u8 val;
++
++
++	pHalData = GET_HAL_DATA(padapter);
++
++	val = rtw_read8(padapter, REG_LEDCFG2);
++	/* Let 8051 take control antenna setting */
++	if (!(val & BIT(7))) {
++		val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
++		rtw_write8(padapter, REG_LEDCFG2, val);
++	}
++#endif
++}
++void rtl8723d_DeinitAntenna_Selection(PADAPTER padapter)
++{
++#if 0
++	PHAL_DATA_TYPE pHalData;
++	u8 val;
++
++
++	pHalData = GET_HAL_DATA(padapter);
++	val = rtw_read8(padapter, REG_LEDCFG2);
++	/* Let 8051 take control antenna setting */
++	val &= ~BIT(7); /* DPDT_SEL_EN, clear 0x4C[23] */
++	rtw_write8(padapter, REG_LEDCFG2, val);
++#endif
++}
++
++void init_hal_spec_8723d(_adapter *adapter)
++{
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++
++	hal_spec->ic_name = "rtl8723d";
++	hal_spec->macid_num = 16;
++	hal_spec->sec_cam_ent_num = 32;
++	hal_spec->sec_cap = SEC_CAP_CHK_BMC;
++	hal_spec->macid_cap = MACID_DROP_INDIRECT;
++	hal_spec->macid_txrpt = 0x8100;
++	hal_spec->macid_txrpt_pgsz = 16;
++
++	hal_spec->rfpath_num_2g = 2;
++	hal_spec->rfpath_num_5g = 0;
++	hal_spec->rf_reg_path_num = hal_spec->rf_reg_path_avail_num = 1;
++	hal_spec->rf_reg_trx_path_bmp = 0x11;
++	hal_spec->max_tx_cnt = 1;
++
++	hal_spec->tx_nss_num = 1;
++	hal_spec->rx_nss_num = 1;
++	hal_spec->band_cap = BAND_CAP_2G;
++	hal_spec->bw_cap = BW_CAP_20M | BW_CAP_40M;
++	hal_spec->port_num = 3;
++	hal_spec->proto_cap = PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N;
++
++	hal_spec->txgi_max = 63;
++	hal_spec->txgi_pdbm = 2;
++
++	hal_spec->wl_func = 0
++			    | WL_FUNC_P2P
++			    | WL_FUNC_MIRACAST
++			    | WL_FUNC_TDLS
++			    ;
++
++	hal_spec->tx_aclt_unit_factor = 8;
++
++	hal_spec->pg_txpwr_saddr = 0x10;
++	hal_spec->pg_txgi_diff_factor = 1;
++
++	rtw_macid_ctl_init_sleep_reg(adapter_to_macidctl(adapter)
++		, REG_MACID_SLEEP, 0, 0, 0);
++}
++
++void rtl8723d_init_default_value(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE pHalData;
++	u8 i;
++
++	pHalData = GET_HAL_DATA(padapter);
++
++	/* init default value */
++	pHalData->fw_ractrl = _FALSE;
++	if (!adapter_to_pwrctl(padapter)->bkeepfwalive)
++		pHalData->LastHMEBoxNum = 0;
++
++	/* init phydm default value */
++	pHalData->bIQKInitialized = _FALSE;
++
++	/* init Efuse variables */
++	pHalData->EfuseUsedBytes = 0;
++	pHalData->EfuseUsedPercentage = 0;
++#ifdef HAL_EFUSE_MEMORY
++	pHalData->EfuseHal.fakeEfuseBank = 0;
++	pHalData->EfuseHal.fakeEfuseUsedBytes = 0;
++	_rtw_memset(pHalData->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE);
++	_rtw_memset(pHalData->EfuseHal.fakeEfuseInitMap, 0xFF, EFUSE_MAX_MAP_LEN);
++	_rtw_memset(pHalData->EfuseHal.fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);
++	pHalData->EfuseHal.BTEfuseUsedBytes = 0;
++	pHalData->EfuseHal.BTEfuseUsedPercentage = 0;
++	_rtw_memset(pHalData->EfuseHal.BTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK * EFUSE_MAX_HW_SIZE);
++	_rtw_memset(pHalData->EfuseHal.BTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
++	_rtw_memset(pHalData->EfuseHal.BTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
++	pHalData->EfuseHal.fakeBTEfuseUsedBytes = 0;
++	_rtw_memset(pHalData->EfuseHal.fakeBTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK * EFUSE_MAX_HW_SIZE);
++	_rtw_memset(pHalData->EfuseHal.fakeBTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
++	_rtw_memset(pHalData->EfuseHal.fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
++#endif
++	pHalData->need_restore = _FALSE;
++}
++
++u8 GetEEPROMSize8723D(PADAPTER padapter)
++{
++	u8 size = 0;
++	u32	cr;
++
++	cr = rtw_read16(padapter, REG_9346CR);
++	/* 6: EEPROM used is 93C46, 4: boot from E-Fuse. */
++	size = (cr & BOOT_FROM_EEPROM) ? 6 : 4;
++
++	RTW_INFO("EEPROM type is %s\n", size == 4 ? "E-FUSE" : "93C46");
++
++	return size;
++}
++
++/* -------------------------------------------------------------------------
++ *
++ * LLT R/W/Init function
++ *
++ * ------------------------------------------------------------------------- */
++s32 rtl8723d_InitLLTTable(PADAPTER padapter)
++{
++	systime start;
++	u32 passing_time;
++	u32 val32;
++	s32 ret;
++
++
++	ret = _FAIL;
++
++	val32 = rtw_read32(padapter, REG_AUTO_LLT);
++	val32 |= BIT_AUTO_INIT_LLT;
++	rtw_write32(padapter, REG_AUTO_LLT, val32);
++
++	start = rtw_get_current_time();
++
++	do {
++		val32 = rtw_read32(padapter, REG_AUTO_LLT);
++		if (!(val32 & BIT_AUTO_INIT_LLT)) {
++			ret = _SUCCESS;
++			break;
++		}
++
++		passing_time = rtw_get_passing_time_ms(start);
++		if (passing_time > 1000) {
++			RTW_INFO("%s: FAIL!! REG_AUTO_LLT(0x%X)=%08x\n",
++				 __FUNCTION__, REG_AUTO_LLT, val32);
++			break;
++		}
++
++		rtw_usleep_os(2);
++	} while (1);
++
++	return ret;
++}
++
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++void _DisableGPIO(PADAPTER	padapter)
++{
++	/***************************************
++	j. GPIO_PIN_CTRL 0x44[31:0]=0x000
++	k.Value = GPIO_PIN_CTRL[7:0]
++	l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8);
++	m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
++	n. LEDCFG 0x4C[15:0] = 0x8080
++	***************************************/
++	u8	value8;
++	u16	value16;
++	u32	value32;
++	u32	u4bTmp;
++
++
++	/* 1. Disable GPIO[7:0] */
++	rtw_write16(padapter, REG_GPIO_PIN_CTRL + 2, 0x0000);
++	value32 = rtw_read32(padapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
++	u4bTmp = value32 & 0x000000FF;
++	value32 |= ((u4bTmp << 8) | 0x00FF0000);
++	rtw_write32(padapter, REG_GPIO_PIN_CTRL, value32);
++
++
++	/* 2. Disable GPIO[10:8] */
++	rtw_write8(padapter, REG_MAC_PINMUX_CFG, 0x00);
++	value16 = rtw_read16(padapter, REG_GPIO_IO_SEL) & 0xFF0F;
++	value8 = (u8)(value16 & 0x000F);
++	value16 |= ((value8 << 4) | 0x0780);
++	rtw_write16(padapter, REG_GPIO_IO_SEL, value16);
++
++
++	/* 3. Disable LED0 & 1 */
++	rtw_write16(padapter, REG_LEDCFG0, 0x8080);
++
++} /* end of _DisableGPIO() */
++
++void _DisableRFAFEAndResetBB8723D(PADAPTER padapter)
++{
++	/**************************************
++	a.	TXPAUSE 0x522[7:0] = 0xFF
++	b.	RF path 0 offset 0x00 = 0x00
++	c.	APSD_CTRL 0x600[7:0] = 0x40
++	d.	SYS_FUNC_EN 0x02[7:0] = 0x16
++	e.	SYS_FUNC_EN 0x02[7:0] = 0x14
++	***************************************/
++	enum rf_path eRFPath = RF_PATH_A, value8 = 0;
++
++	rtw_write8(padapter, REG_TXPAUSE, 0xFF);
++
++	phy_set_rf_reg(padapter, eRFPath, 0x0, bMaskByte0, 0x0);
++
++	value8 |= APSDOFF;
++	rtw_write8(padapter, REG_APSD_CTRL, value8);/* 0x40 */
++
++	/* Set BB reset at first */
++	value8 = 0;
++	value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
++	rtw_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x16 */
++
++	/* Set global reset. */
++	value8 &= ~FEN_BB_GLB_RSTn;
++	rtw_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x14 */
++
++	/* 2010/08/12 MH We need to set BB/GLBAL reset to save power for SS mode. */
++
++}
++
++void _DisableRFAFEAndResetBB(PADAPTER padapter)
++{
++	_DisableRFAFEAndResetBB8723D(padapter);
++}
++
++void _ResetDigitalProcedure1_8723D(PADAPTER padapter, BOOLEAN bWithoutHWSM)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	if (IS_FW_81xxC(padapter) && (pHalData->firmware_version <= 0x20)) {
++#if 0
++		/*****************************
++				f.	SYS_FUNC_EN 0x03[7:0]=0x54
++				g.	MCUFWDL 0x80[7:0]=0
++		******************************/
++		u32	value32 = 0;
++
++		rtw_write8(padapter, REG_SYS_FUNC_EN + 1, 0x54);
++		rtw_write8(padapter, REG_MCUFWDL, 0);
++#else
++		/*****************************
++		f.	MCUFWDL 0x80[7:0]=0
++		g.	SYS_FUNC_EN 0x02[10]= 0
++		h.	SYS_FUNC_EN 0x02[15-12]= 5
++		i.     SYS_FUNC_EN 0x02[10]= 1
++		******************************/
++		u16 valu16 = 0;
++
++		rtw_write8(padapter, REG_MCUFWDL, 0);
++
++		valu16 = rtw_read16(padapter, REG_SYS_FUNC_EN);
++		rtw_write16(padapter, REG_SYS_FUNC_EN, (valu16 & (~FEN_CPUEN)));/* reset MCU ,8051 */
++
++		valu16 = rtw_read16(padapter, REG_SYS_FUNC_EN) & 0x0FFF;
++		rtw_write16(padapter, REG_SYS_FUNC_EN, (valu16 | (FEN_HWPDN | FEN_ELDR))); /* reset MAC */
++
++		valu16 = rtw_read16(padapter, REG_SYS_FUNC_EN);
++		rtw_write16(padapter, REG_SYS_FUNC_EN, (valu16 | FEN_CPUEN));/* enable MCU ,8051 */
++#endif
++	} else {
++		u8 retry_cnts = 0;
++
++		/* 2010/08/12 MH For USB SS, we can not stop 8051 when we are trying to */
++		/* enter IPS/HW&SW radio off. For S3/S4/S5/Disable, we can stop 8051 because */
++		/* we will init FW when power on again. */
++		/* if(!pDevice->RegUsbSS) */
++		{	/* If we want to SS mode, we can not reset 8051. */
++			if (rtw_read8(padapter, REG_MCUFWDL) & BIT(1)) {
++				/* IF fw in RAM code, do reset */
++
++
++				if (pHalData->bFWReady) {
++					/* 2010/08/25 MH According to RD alfred's suggestion, we need to disable other */
++					/* HRCV INT to influence 8051 reset. */
++					rtw_write8(padapter, REG_FWIMR, 0x20);
++					/* 2011/02/15 MH According to Alex's suggestion, close mask to prevent incorrect FW write operation. */
++					rtw_write8(padapter, REG_FTIMR, 0x00);
++					rtw_write8(padapter, REG_FSIMR, 0x00);
++
++					rtw_write8(padapter, REG_HMETFR + 3, 0x20); /* 8051 reset by self */
++
++					while ((retry_cnts++ < 100) && (FEN_CPUEN & rtw_read16(padapter, REG_SYS_FUNC_EN))) {
++						rtw_udelay_os(50);/* us */
++						/* 2010/08/25 For test only We keep on reset 5051 to prevent fail. */
++						/* rtw_write8(padapter, REG_HMETFR+3, 0x20);//8051 reset by self */
++					}
++					/*					RT_ASSERT((retry_cnts < 100), ("8051 reset failed!\n")); */
++
++					if (retry_cnts >= 100) {
++						/* if 8051 reset fail we trigger GPIO 0 for LA */
++						/* rtw_write32(	padapter, */
++						/*						REG_GPIO_PIN_CTRL, */
++						/*						0x00010100); */
++						/* 2010/08/31 MH According to Filen's info, if 8051 reset fail, reset MAC directly. */
++						rtw_write8(padapter, REG_SYS_FUNC_EN + 1, 0x50);	/* Reset MAC and Enable 8051 */
++						rtw_mdelay_os(10);
++					}
++
++				}
++			}
++
++			rtw_write8(padapter, REG_SYS_FUNC_EN + 1, 0x54);	/* Reset MAC and Enable 8051 */
++			rtw_write8(padapter, REG_MCUFWDL, 0);
++		}
++	}
++
++	/* if(pDevice->RegUsbSS) */
++	/* bWithoutHWSM = TRUE;	// Sugest by Filen and Issau. */
++
++	if (bWithoutHWSM) {
++		/* HAL_DATA_TYPE		*pHalData	= GET_HAL_DATA(padapter); */
++		/*****************************
++			Without HW auto state machine
++		g.	SYS_CLKR 0x08[15:0] = 0x30A3
++		h.	AFE_PLL_CTRL 0x28[7:0] = 0x80
++		i.	AFE_XTAL_CTRL 0x24[15:0] = 0x880F
++		j.	SYS_ISO_CTRL 0x00[7:0] = 0xF9
++		******************************/
++		/* rtw_write16(padapter, REG_SYS_CLKR, 0x30A3); */
++		/* if(!pDevice->RegUsbSS) */
++		/* 2011/01/26 MH SD4 Scott suggest to fix UNC-B cut bug. */
++		rtw_write16(padapter, REG_SYS_CLKR, 0x70A3);  /* modify to 0x70A3 by Scott. */
++		rtw_write8(padapter, REG_AFE_PLL_CTRL, 0x80);
++		rtw_write16(padapter, REG_AFE_XTAL_CTRL, 0x880F);
++		/* if(!pDevice->RegUsbSS) */
++		rtw_write8(padapter, REG_SYS_ISO_CTRL, 0xF9);
++	} else {
++		/* Disable all RF/BB power */
++		rtw_write8(padapter, REG_RF_CTRL, 0x00);
++	}
++
++}
++
++void _ResetDigitalProcedure1(PADAPTER padapter, BOOLEAN bWithoutHWSM)
++{
++	_ResetDigitalProcedure1_8723D(padapter, bWithoutHWSM);
++}
++
++void _ResetDigitalProcedure2(PADAPTER padapter)
++{
++	/* HAL_DATA_TYPE		*pHalData	= GET_HAL_DATA(padapter);
++	*****************************
++	k.	SYS_FUNC_EN 0x03[7:0] = 0x44
++	l.	SYS_CLKR 0x08[15:0] = 0x3083
++	m.	SYS_ISO_CTRL 0x01[7:0] = 0x83
++	******************************/
++	/* rtw_write8(padapter, REG_SYS_FUNC_EN+1, 0x44); //marked by Scott. */
++	/* 2011/01/26 MH SD4 Scott suggest to fix UNC-B cut bug. */
++	rtw_write16(padapter, REG_SYS_CLKR, 0x70a3); /* modify to 0x70a3 by Scott. */
++	rtw_write8(padapter, REG_SYS_ISO_CTRL + 1, 0x82); /* modify to 0x82 by Scott. */
++}
++
++void _DisableAnalog(PADAPTER padapter, BOOLEAN bWithoutHWSM)
++{
++	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
++	u16 value16 = 0;
++	u8 value8 = 0;
++
++
++	if (bWithoutHWSM) {
++		/*****************************
++		n.	LDOA15_CTRL 0x20[7:0] = 0x04
++		o.	LDOV12D_CTRL 0x21[7:0] = 0x54
++		r.	When driver call disable, the ASIC will turn off remaining clock automatically
++		******************************/
++
++		rtw_write8(padapter, REG_LDOA15_CTRL, 0x04);
++		/* rtw_write8(padapter, REG_LDOV12D_CTRL, 0x54); */
++
++		value8 = rtw_read8(padapter, REG_LDOV12D_CTRL);
++		value8 &= (~LDV12_EN);
++		rtw_write8(padapter, REG_LDOV12D_CTRL, value8);
++	}
++
++	/*****************************
++	h.	SPS0_CTRL 0x11[7:0] = 0x23
++	i.	APS_FSMCO 0x04[15:0] = 0x4802
++	******************************/
++	value8 = 0x23;
++
++	rtw_write8(padapter, REG_SPS0_CTRL, value8);
++
++	if (bWithoutHWSM) {
++		/* value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN); */
++		/* 2010/08/31 According to Filen description, we need to use HW to shut down 8051 automatically. */
++		/* Because suspend operation need the asistance of 8051 to wait for 3ms. */
++		value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
++	} else
++		value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
++
++	rtw_write16(padapter, REG_APS_FSMCO, value16);/* 0x4802 */
++
++	rtw_write8(padapter, REG_RSV_CTRL, 0x0e);
++
++#if 0
++	/* tynli_test for suspend mode. */
++	if (!bWithoutHWSM)
++		rtw_write8(padapter, 0xfe10, 0x19);
++#endif
++
++}
++
++/* HW Auto state machine */
++s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU)
++{
++	int rtStatus = _SUCCESS;
++
++
++	if (RTW_CANNOT_RUN(padapter))
++		return rtStatus;
++
++	/* ==== RF Off Sequence ==== */
++	_DisableRFAFEAndResetBB(padapter);
++
++	/* ==== Reset digital sequence   ====== */
++	_ResetDigitalProcedure1(padapter, _FALSE);
++
++	/* ==== Pull GPIO PIN to balance level and LED control ====== */
++	_DisableGPIO(padapter);
++
++	/* ==== Disable analog sequence === */
++	_DisableAnalog(padapter, _FALSE);
++
++
++	return rtStatus;
++}
++
++/* without HW Auto state machine */
++s32 CardDisableWithoutHWSM(PADAPTER padapter)
++{
++	s32 rtStatus = _SUCCESS;
++
++
++	if (RTW_CANNOT_RUN(padapter))
++		return rtStatus;
++
++
++	/* ==== RF Off Sequence ==== */
++	_DisableRFAFEAndResetBB(padapter);
++
++	/* ==== Reset digital sequence   ====== */
++	_ResetDigitalProcedure1(padapter, _TRUE);
++
++	/* ==== Pull GPIO PIN to balance level and LED control ====== */
++	_DisableGPIO(padapter);
++
++	/* ==== Reset digital sequence   ====== */
++	_ResetDigitalProcedure2(padapter);
++
++	/* ==== Disable analog sequence === */
++	_DisableAnalog(padapter, _TRUE);
++
++	return rtStatus;
++}
++#endif /* CONFIG_USB_HCI || CONFIG_SDIO_HCI || CONFIG_GSPI_HCI */
++
++void
++Hal_InitPGData(
++	PADAPTER	padapter,
++	u8			*PROMContent)
++{
++
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	u32			i;
++	u16			value16;
++
++	if (_FALSE == pHalData->bautoload_fail_flag) {
++		/* autoload OK.
++		*		if (IS_BOOT_FROM_EEPROM(padapter)) */
++		if (_TRUE == pHalData->EepromOrEfuse) {
++			/* Read all Content from EEPROM or EFUSE. */
++			for (i = 0; i < HWSET_MAX_SIZE_8723D; i += 2) {
++				/*				value16 = EF2Byte(ReadEEprom(pAdapter, (u16) (i>>1)));
++				 *				*((u16*)(&PROMContent[i])) = value16; */
++			}
++		} else {
++			/* Read EFUSE real map to shadow. */
++			EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE);
++			_rtw_memcpy((void *)PROMContent, (void *)pHalData->efuse_eeprom_data, HWSET_MAX_SIZE_8723D);
++		}
++	} else {
++		/* autoload fail */
++		/*		pHalData->AutoloadFailFlag = _TRUE; */
++		/* update to default value 0xFF */
++		if (_FALSE == pHalData->EepromOrEfuse)
++			EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE);
++		_rtw_memcpy((void *)PROMContent, (void *)pHalData->efuse_eeprom_data, HWSET_MAX_SIZE_8723D);
++	}
++
++#ifdef CONFIG_EFUSE_CONFIG_FILE
++	if (check_phy_efuse_tx_power_info_valid(padapter) == _FALSE) {
++		if (Hal_readPGDataFromConfigFile(padapter) != _SUCCESS)
++			RTW_ERR("invalid phy efuse and read from file fail, will use driver default!!\n");
++	}
++#endif
++}
++
++void
++Hal_EfuseParseIDCode(
++		PADAPTER	padapter,
++		u8			*hwinfo
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	u16			EEPROMId;
++
++
++	/* Checl 0x8129 again for making sure autoload status!! */
++	EEPROMId = le16_to_cpu(*((u16 *)hwinfo));
++	if (EEPROMId != RTL_EEPROM_ID) {
++		RTW_INFO("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
++		pHalData->bautoload_fail_flag = _TRUE;
++	} else
++		pHalData->bautoload_fail_flag = _FALSE;
++
++}
++void
++Hal_EfuseParseTxPowerInfo_8723D(
++		PADAPTER		padapter,
++		u8			*PROMContent,
++		BOOLEAN			AutoLoadFail
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	pHalData->txpwr_pg_mode = TXPWR_PG_WITH_PWR_IDX;
++
++	/* 2010/10/19 MH Add Regulator recognize for CU. */
++	if (!AutoLoadFail) {
++		pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_8723D] & 0x7);	/* bit0~2 */
++		if (PROMContent[EEPROM_RF_BOARD_OPTION_8723D] == 0xFF)
++			pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION & 0x7);	/* bit0~2 */
++	} else
++		pHalData->EEPROMRegulatory = 0;
++}
++
++void
++Hal_EfuseParseBoardType_8723D(
++		PADAPTER	Adapter,
++		u8			*PROMContent,
++		BOOLEAN		AutoloadFail
++)
++{
++
++
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++
++	if (!AutoloadFail) {
++		pHalData->InterfaceSel = (PROMContent[EEPROM_RF_BOARD_OPTION_8723D] & 0xE0) >> 5;
++		if (PROMContent[EEPROM_RF_BOARD_OPTION_8723D] == 0xFF)
++			pHalData->InterfaceSel = (EEPROM_DEFAULT_BOARD_OPTION & 0xE0) >> 5;
++	} else
++		pHalData->InterfaceSel = 0;
++
++}
++
++void
++Hal_EfuseParseBTCoexistInfo_8723D(
++		PADAPTER padapter,
++		u8 *hwinfo,
++		BOOLEAN AutoLoadFail
++)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++	u8 tempval;
++	u32 tmpu4;
++
++	if (!AutoLoadFail) {
++		tmpu4 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL);
++		if (tmpu4 & BT_FUNC_EN)
++			pHalData->EEPROMBluetoothCoexist = _TRUE;
++		else
++			pHalData->EEPROMBluetoothCoexist = _FALSE;
++
++		pHalData->EEPROMBluetoothType = BT_RTL8723D;
++
++		tempval = hwinfo[EEPROM_RF_BT_SETTING_8723D];
++		if (tempval != 0xFF) {
++			/* 0:Ant_x2, 1:Ant_x1 */
++			pHalData->EEPROMBluetoothAntNum = tempval & BIT(0);
++			/*
++			 * EFUSE_0xC3[6] == 0, Wi-Fi at BTGS1(Main, Ant2) - RF_PATH_A (default)
++			 * EFUSE_0xC3[6] == 1, Wi-Fi at BTGS0( Aux, Ant1) - RF_PATH_B
++			 */
++			pHalData->ant_path = (tempval & BIT(6)) ? RF_PATH_B : RF_PATH_A;
++		} else {
++			pHalData->EEPROMBluetoothAntNum = Ant_x1;
++			pHalData->ant_path = RF_PATH_A;
++		}
++	} else {
++		if (padapter->registrypriv.mp_mode == 1)
++			pHalData->EEPROMBluetoothCoexist = _TRUE;
++		else
++			pHalData->EEPROMBluetoothCoexist = _FALSE;
++
++		pHalData->EEPROMBluetoothType = BT_RTL8723D;
++		pHalData->EEPROMBluetoothAntNum = Ant_x1;
++		pHalData->ant_path = RF_PATH_A;
++	}
++
++#ifdef CONFIG_BT_COEXIST
++	if (padapter->registrypriv.ant_num > 0) {
++		RTW_INFO("%s: Apply driver defined antenna number(%d) to replace origin(%d)\n"
++			 , __func__
++			 , padapter->registrypriv.ant_num
++			 , pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1);
++
++		switch (padapter->registrypriv.ant_num) {
++		case 1:
++			pHalData->EEPROMBluetoothAntNum = Ant_x1;
++			break;
++		case 2:
++			pHalData->EEPROMBluetoothAntNum = Ant_x2;
++			break;
++		default:
++			RTW_INFO("%s: Discard invalid driver defined antenna number(%d)!\n"
++				 , __func__, padapter->registrypriv.ant_num);
++			break;
++		}
++	}
++#endif /* CONFIG_BT_COEXIST */
++
++	RTW_INFO("%s: %s BT-coex, ant_num=%d\n"
++		 , __func__
++		, pHalData->EEPROMBluetoothCoexist == _TRUE ? "Enable" : "Disable"
++		 , pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1);
++}
++
++void
++Hal_EfuseParseEEPROMVer_8723D(
++		PADAPTER		padapter,
++		u8			*hwinfo,
++		BOOLEAN			AutoLoadFail
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	if (!AutoLoadFail)
++		pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_8723D];
++	else
++		pHalData->EEPROMVersion = 1;
++}
++
++void
++Hal_EfuseParseVoltage_8723D(
++		PADAPTER		pAdapter,
++		u8			*hwinfo,
++		BOOLEAN	AutoLoadFail
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++
++	/* _rtw_memcpy(pHalData->adjuseVoltageVal, &hwinfo[EEPROM_Voltage_ADDR_8723D], 1); */
++	RTW_INFO("%s hwinfo[EEPROM_Voltage_ADDR_8723D] =%02x\n", __func__, hwinfo[EEPROM_Voltage_ADDR_8723D]);
++	pHalData->adjuseVoltageVal = (hwinfo[EEPROM_Voltage_ADDR_8723D] & 0xf0) >> 4;
++	RTW_INFO("%s pHalData->adjuseVoltageVal =%x\n", __func__, pHalData->adjuseVoltageVal);
++}
++
++void
++Hal_EfuseParseChnlPlan_8723D(
++		PADAPTER		padapter,
++		u8			*hwinfo,
++		BOOLEAN			AutoLoadFail
++)
++{
++	hal_com_config_channel_plan(
++		padapter
++		, hwinfo ? &hwinfo[EEPROM_COUNTRY_CODE_8723D] : NULL
++		, hwinfo ? hwinfo[EEPROM_ChannelPlan_8723D] : 0xFF
++		, padapter->registrypriv.alpha2
++		, padapter->registrypriv.channel_plan
++		, AutoLoadFail
++	);
++}
++
++void
++Hal_EfuseParseCustomerID_8723D(
++		PADAPTER		padapter,
++		u8			*hwinfo,
++		BOOLEAN			AutoLoadFail
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	if (!AutoLoadFail)
++		pHalData->EEPROMCustomerID = hwinfo[EEPROM_CustomID_8723D];
++	else
++		pHalData->EEPROMCustomerID = 0;
++}
++
++void
++Hal_EfuseParseAntennaDiversity_8723D(
++		PADAPTER		pAdapter,
++		u8				*hwinfo,
++		BOOLEAN			AutoLoadFail
++)
++{
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(pAdapter);
++	struct registry_priv	*registry_par = &pAdapter->registrypriv;
++	u8				get_efuse_div_type;
++
++	if (pHalData->EEPROMBluetoothAntNum == Ant_x1)
++		pHalData->AntDivCfg = 0;
++	else {
++		if (registry_par->antdiv_cfg == 2) /* 0:OFF , 1:ON, 2:By EFUSE */
++			pHalData->AntDivCfg = 1;
++		else
++			pHalData->AntDivCfg = registry_par->antdiv_cfg;
++	}
++
++	pHalData->TRxAntDivType = S0S1_TRX_HW_ANTDIV; /* it's the only diversity-type for 8723D*/
++	pHalData->with_extenal_ant_switch = ((hwinfo[EEPROM_RF_BT_SETTING_8723D] & BIT7) >> 7);
++
++	if (pHalData->AntDivCfg != 0) {
++
++		get_efuse_div_type = hwinfo[EEPROM_RFE_OPTION_8723D];
++
++		if (get_efuse_div_type == 0x11) {
++			pHalData->b_fix_tx_ant = NO_FIX_TX_ANT;
++		} else if (get_efuse_div_type == 0x13) {
++			pHalData->b_fix_tx_ant = FIX_TX_AT_MAIN;/* RX diversity only*/
++		} else
++			pHalData->AntDivCfg = FALSE;
++	}
++
++	RTW_INFO("%s: AntDivCfg=%d, AntDivType=%d\n",
++		 __FUNCTION__, pHalData->AntDivCfg, pHalData->TRxAntDivType);
++#endif
++}
++
++void
++Hal_EfuseParseXtal_8723D(
++		PADAPTER		pAdapter,
++		u8			*hwinfo,
++		BOOLEAN		AutoLoadFail
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++
++	if (!AutoLoadFail) {
++		pHalData->crystal_cap = hwinfo[EEPROM_XTAL_8723D];
++		if (pHalData->crystal_cap == 0xFF)
++			pHalData->crystal_cap = EEPROM_Default_CrystalCap_8723D;	   /* what value should 8812 set? */
++	} else
++		pHalData->crystal_cap = EEPROM_Default_CrystalCap_8723D;
++}
++
++
++void
++Hal_EfuseParseThermalMeter_8723D(
++	PADAPTER	padapter,
++	u8			*PROMContent,
++	u8			AutoLoadFail
++)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++
++	/* */
++	/* ThermalMeter from EEPROM */
++	/* */
++	if (_FALSE == AutoLoadFail)
++		pHalData->eeprom_thermal_meter = PROMContent[EEPROM_THERMAL_METER_8723D];
++	else
++		pHalData->eeprom_thermal_meter = EEPROM_Default_ThermalMeter_8723D;
++
++	if ((pHalData->eeprom_thermal_meter == 0xff) || (_TRUE == AutoLoadFail)) {
++		pHalData->odmpriv.rf_calibrate_info.is_apk_thermal_meter_ignore = _TRUE;
++		pHalData->eeprom_thermal_meter = EEPROM_Default_ThermalMeter_8723D;
++	}
++
++}
++
++
++void Hal_ReadRFGainOffset(
++			PADAPTER		Adapter,
++			u8			*PROMContent,
++			BOOLEAN		AutoloadFail)
++{
++#ifdef CONFIG_RF_POWER_TRIM
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++	struct kfree_data_t *kfree_data = &pHalData->kfree_data;
++	u8 pg_pwrtrim = 0xFF, pg_therm = 0xFF;
++
++	efuse_OneByteRead(Adapter,
++		PPG_BB_GAIN_2G_TX_OFFSET_8723D, &pg_pwrtrim, _FALSE);
++	efuse_OneByteRead(Adapter,
++		PPG_THERMAL_OFFSET_8723D, &pg_therm, _FALSE);
++
++	if (pg_pwrtrim != 0xFF) {
++		kfree_data->bb_gain[BB_GAIN_2G][PPG_8723D_S1]
++			= KFREE_BB_GAIN_2G_TX_OFFSET(pg_pwrtrim & PPG_BB_GAIN_2G_TX_OFFSET_MASK);
++		kfree_data->bb_gain[BB_GAIN_2G][PPG_8723D_S0]
++			= KFREE_BB_GAIN_2G_TXB_OFFSET(pg_pwrtrim & PPG_BB_GAIN_2G_TXB_OFFSET_MASK);
++		kfree_data->flag |= KFREE_FLAG_ON;
++	}
++
++	if (pg_therm != 0xFF) {
++		kfree_data->thermal
++			= KFREE_THERMAL_OFFSET(pg_therm  & PPG_THERMAL_OFFSET_MASK);
++		/* kfree_data->flag |= KFREE_FLAG_THERMAL_K_ON; */ /* Default disable thermel kfree by realsil Alan 20160428 */
++	}
++
++	if (kfree_data->flag & KFREE_FLAG_THERMAL_K_ON)
++		pHalData->eeprom_thermal_meter += kfree_data->thermal;
++
++	RTW_INFO("kfree Pwr Trim flag:%u\n", kfree_data->flag);
++	if (kfree_data->flag & KFREE_FLAG_ON) {
++		RTW_INFO("bb_gain(S1):%d\n", kfree_data->bb_gain[BB_GAIN_2G][PPG_8723D_S1]);
++		RTW_INFO("bb_gain(S0):%d\n", kfree_data->bb_gain[BB_GAIN_2G][PPG_8723D_S0]);
++	}
++	if (kfree_data->flag & KFREE_FLAG_THERMAL_K_ON)
++		RTW_INFO("thermal:%d\n", kfree_data->thermal);
++#endif /*CONFIG_RF_POWER_TRIM */
++}
++
++u8
++BWMapping_8723D(
++		PADAPTER		Adapter,
++		struct pkt_attrib	*pattrib
++)
++{
++	u8	BWSettingOfDesc = 0;
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
++
++	/* RTW_INFO("BWMapping pHalData->current_channel_bw %d, pattrib->bwmode %d\n",pHalData->current_channel_bw,pattrib->bwmode); */
++
++	if (pHalData->current_channel_bw == CHANNEL_WIDTH_80) {
++		if (pattrib->bwmode == CHANNEL_WIDTH_80)
++			BWSettingOfDesc = 2;
++		else if (pattrib->bwmode == CHANNEL_WIDTH_40)
++			BWSettingOfDesc = 1;
++		else
++			BWSettingOfDesc = 0;
++	} else if (pHalData->current_channel_bw == CHANNEL_WIDTH_40) {
++		if ((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80))
++			BWSettingOfDesc = 1;
++		else
++			BWSettingOfDesc = 0;
++	} else
++		BWSettingOfDesc = 0;
++
++	/* if(pTcb->bBTTxPacket) */
++	/*	BWSettingOfDesc = 0; */
++
++	return BWSettingOfDesc;
++}
++
++u8	SCMapping_8723D(PADAPTER Adapter, struct pkt_attrib *pattrib)
++{
++	u8	SCSettingOfDesc = 0;
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
++
++	/* RTW_INFO("SCMapping: pHalData->current_channel_bw %d, pHalData->nCur80MhzPrimeSC %d, pHalData->nCur40MhzPrimeSC %d\n",pHalData->current_channel_bw,pHalData->nCur80MhzPrimeSC,pHalData->nCur40MhzPrimeSC); */
++
++	if (pHalData->current_channel_bw == CHANNEL_WIDTH_80) {
++		if (pattrib->bwmode == CHANNEL_WIDTH_80)
++			SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
++		else if (pattrib->bwmode == CHANNEL_WIDTH_40) {
++			if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
++				SCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ;
++			else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
++				SCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ;
++			else
++				RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
++		} else {
++			if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
++				SCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
++			else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
++				SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
++			else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
++				SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
++			else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
++				SCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
++			else
++				RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
++		}
++	} else if (pHalData->current_channel_bw == CHANNEL_WIDTH_40) {
++		/* RTW_INFO("SCMapping: HT Case: pHalData->current_channel_bw %d, pHalData->nCur40MhzPrimeSC %d\n",pHalData->current_channel_bw,pHalData->nCur40MhzPrimeSC); */
++
++		if (pattrib->bwmode == CHANNEL_WIDTH_40)
++			SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
++		else if (pattrib->bwmode == CHANNEL_WIDTH_20) {
++			if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
++				SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
++			else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
++				SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
++			else
++				SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
++		}
++	} else
++		SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
++
++	return SCSettingOfDesc;
++}
++
++void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc)
++{
++	if ((pattrib->encrypt > 0) && (!pattrib->bswenc)
++	    && (pattrib->bmc_camid != INVALID_SEC_MAC_CAM_ID)) {
++
++		SET_TX_DESC_EN_DESC_ID_8723D(ptxdesc, 1);
++		SET_TX_DESC_MACID_8723D(ptxdesc, pattrib->bmc_camid);
++	}
++}
++
++void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc)
++{
++	SET_TX_DESC_USE_RATE_8723D(ptxdesc, 1);
++	SET_TX_DESC_TX_RATE_8723D(ptxdesc, MRateToHwRate(pattrib->rate));
++	SET_TX_DESC_DISABLE_FB_8723D(ptxdesc, 1);
++}
++
++static u8 fill_txdesc_sectype(struct pkt_attrib *pattrib)
++{
++	u8 sectype = 0;
++
++	if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
++		switch (pattrib->encrypt) {
++		/* SEC_TYPE */
++		case _WEP40_:
++		case _WEP104_:
++		case _TKIP_:
++		case _TKIP_WTMIC_:
++			sectype = 1;
++			break;
++
++#ifdef CONFIG_WAPI_SUPPORT
++		case _SMS4_:
++			sectype = 2;
++			break;
++#endif
++		case _AES_:
++			sectype = 3;
++			break;
++
++		case _NO_PRIVACY_:
++		default:
++			break;
++		}
++	}
++	return sectype;
++}
++
++static void fill_txdesc_vcs_8723d(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
++{
++	/* RTW_INFO("cvs_mode=%d\n", pattrib->vcs_mode); */
++
++	if (pattrib->vcs_mode) {
++		switch (pattrib->vcs_mode) {
++		case RTS_CTS:
++			SET_TX_DESC_RTS_ENABLE_8723D(ptxdesc, 1);
++			SET_TX_DESC_HW_RTS_ENABLE_8723D(ptxdesc, 1);
++			break;
++
++		case CTS_TO_SELF:
++			SET_TX_DESC_CTS2SELF_8723D(ptxdesc, 1);
++			break;
++
++		case NONE_VCS:
++		default:
++			break;
++		}
++
++		SET_TX_DESC_RTS_RATE_8723D(ptxdesc, 8); /* RTS Rate=24M */
++		SET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(ptxdesc, 0xF);
++
++		if (padapter->mlmeextpriv.mlmext_info.preamble_mode == PREAMBLE_SHORT)
++			SET_TX_DESC_RTS_SHORT_8723D(ptxdesc, 1);
++
++		/* Set RTS BW */
++		if (pattrib->ht_en)
++			SET_TX_DESC_RTS_SC_8723D(ptxdesc, SCMapping_8723D(padapter, pattrib));
++	}
++}
++
++static void fill_txdesc_phy_8723d(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
++{
++	/* RTW_INFO("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset); */
++
++	if (pattrib->ht_en) {
++		SET_TX_DESC_DATA_BW_8723D(ptxdesc, BWMapping_8723D(padapter, pattrib));
++		SET_TX_DESC_DATA_SC_8723D(ptxdesc, SCMapping_8723D(padapter, pattrib));
++	}
++}
++
++static void rtl8723d_fill_default_txdesc(
++	struct xmit_frame *pxmitframe,
++	u8 *pbuf)
++{
++	PADAPTER padapter;
++	HAL_DATA_TYPE *pHalData;
++	struct mlme_ext_priv *pmlmeext;
++	struct mlme_ext_info *pmlmeinfo;
++	struct pkt_attrib *pattrib;
++	s32 bmcst;
++
++	_rtw_memset(pbuf, 0, TXDESC_SIZE);
++
++	padapter = pxmitframe->padapter;
++	pHalData = GET_HAL_DATA(padapter);
++	pmlmeext = &padapter->mlmeextpriv;
++	pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	pattrib = &pxmitframe->attrib;
++	bmcst = IS_MCAST(pattrib->ra);
++
++	if (pHalData->rf_type == RF_1T1R)
++		SET_TX_DESC_PATH_A_EN_8723D(pbuf, 1);
++
++	if (pxmitframe->frame_tag == DATA_FRAMETAG) {
++		u8 drv_userate = 0;
++
++		SET_TX_DESC_MACID_8723D(pbuf, pattrib->mac_id);
++		SET_TX_DESC_RATE_ID_8723D(pbuf, pattrib->raid);
++		SET_TX_DESC_QUEUE_SEL_8723D(pbuf, pattrib->qsel);
++		SET_TX_DESC_SEQ_8723D(pbuf, pattrib->seqnum);
++
++		SET_TX_DESC_SEC_TYPE_8723D(pbuf, fill_txdesc_sectype(pattrib));
++
++		if (bmcst)
++			fill_txdesc_force_bmc_camid(pattrib, pbuf);
++
++		fill_txdesc_vcs_8723d(padapter, pattrib, pbuf);
++
++#ifdef CONFIG_P2P
++		if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) {
++			if (pattrib->icmp_pkt == 1 && padapter->registrypriv.wifi_spec == 1)
++				drv_userate = 1;
++		}
++#endif
++
++		if ((pattrib->ether_type != 0x888e) &&
++		    (pattrib->ether_type != 0x0806) &&
++		    (pattrib->ether_type != 0x88B4) &&
++		    (pattrib->dhcp_pkt != 1) &&
++		    (drv_userate != 1)
++#ifdef CONFIG_AUTO_AP_MODE
++		    && (pattrib->pctrl != _TRUE)
++#endif
++		   ) {
++			/* Non EAP & ARP & DHCP type data packet */
++
++			if (pattrib->ampdu_en == _TRUE) {
++				SET_TX_DESC_AGG_ENABLE_8723D(pbuf, 1);
++				SET_TX_DESC_MAX_AGG_NUM_8723D(pbuf, 0x1F);
++				SET_TX_DESC_AMPDU_DENSITY_8723D(pbuf, pattrib->ampdu_spacing);
++			} else
++				SET_TX_DESC_BK_8723D(pbuf, 1);
++
++			fill_txdesc_phy_8723d(padapter, pattrib, pbuf);
++
++			SET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(pbuf, 0x1F);
++
++			if (pHalData->fw_ractrl == _FALSE) {
++				SET_TX_DESC_USE_RATE_8723D(pbuf, 1);
++
++				if (pHalData->INIDATA_RATE[pattrib->mac_id] & BIT(7))
++					SET_TX_DESC_DATA_SHORT_8723D(pbuf, 1);
++
++				SET_TX_DESC_TX_RATE_8723D(pbuf, pHalData->INIDATA_RATE[pattrib->mac_id] & 0x7F);
++			}
++			if (bmcst)
++				fill_txdesc_bmc_tx_rate(pattrib, pbuf);
++
++			/* modify data rate by iwpriv */
++			if (padapter->fix_rate != 0xFF) {
++				SET_TX_DESC_USE_RATE_8723D(pbuf, 1);
++				if (padapter->fix_rate & BIT(7))
++					SET_TX_DESC_DATA_SHORT_8723D(pbuf, 1);
++				SET_TX_DESC_TX_RATE_8723D(pbuf, padapter->fix_rate & 0x7F);
++				if (!padapter->data_fb)
++					SET_TX_DESC_DISABLE_FB_8723D(pbuf, 1);
++			}
++
++			if (pattrib->stbc)
++				SET_TX_DESC_DATA_STBC_8723D(pbuf, 1);
++
++#ifdef CONFIG_CMCC_TEST
++			SET_TX_DESC_DATA_SHORT_8723D(pbuf, 1); /* use cck short premble */
++#endif
++		} else {
++			/* EAP data packet and ARP packet. */
++			/* Use the 1M data rate to send the EAP/ARP packet. */
++			/* This will maybe make the handshake smooth. */
++
++			SET_TX_DESC_BK_8723D(pbuf, 1);
++			SET_TX_DESC_USE_RATE_8723D(pbuf, 1);
++			if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
++				SET_TX_DESC_DATA_SHORT_8723D(pbuf, 1);
++#ifdef CONFIG_IP_R_MONITOR
++			if((pattrib->ether_type == ETH_P_ARP) &&
++				(IsSupportedTxOFDM(padapter->registrypriv.wireless_mode))) 
++				SET_TX_DESC_TX_RATE_8723D(pbuf, MRateToHwRate(IEEE80211_OFDM_RATE_6MB));
++			 else
++#endif/*CONFIG_IP_R_MONITOR*/
++				SET_TX_DESC_TX_RATE_8723D(pbuf, MRateToHwRate(pmlmeext->tx_rate));
++
++			RTW_INFO(FUNC_ADPT_FMT ": SP Packet(0x%04X) rate=0x%x SeqNum = %d\n",
++				FUNC_ADPT_ARG(padapter), pattrib->ether_type, MRateToHwRate(pmlmeext->tx_rate), pattrib->seqnum);
++		}
++
++#if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++		SET_TX_DESC_USB_TXAGG_NUM_8723D(pbuf, pxmitframe->agg_num);
++#endif
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_XMIT_ACK
++		/* CCX-TXRPT ack for xmit mgmt frames. */
++		if (pxmitframe->ack_report) {
++#ifdef DBG_CCX
++			RTW_INFO("%s set spe_rpt\n", __func__);
++#endif
++			SET_TX_DESC_CCX_8723D(pbuf, 1);
++			SET_TX_DESC_SW_DEFINE_8723D(pbuf, (u8)(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.seq_no));
++		}
++#endif /* CONFIG_XMIT_ACK */
++#endif
++	} else if (pxmitframe->frame_tag == MGNT_FRAMETAG) {
++
++		SET_TX_DESC_MACID_8723D(pbuf, pattrib->mac_id);
++		SET_TX_DESC_QUEUE_SEL_8723D(pbuf, pattrib->qsel);
++		SET_TX_DESC_RATE_ID_8723D(pbuf, pattrib->raid);
++		SET_TX_DESC_SEQ_8723D(pbuf, pattrib->seqnum);
++		SET_TX_DESC_USE_RATE_8723D(pbuf, 1);
++
++		SET_TX_DESC_MBSSID_8723D(pbuf, pattrib->mbssid & 0xF);
++
++		SET_TX_DESC_RETRY_LIMIT_ENABLE_8723D(pbuf, 1);
++#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
++		SET_TX_DESC_DATA_RETRY_LIMIT_8723D(pbuf, 48);
++#else
++		if (pattrib->retry_ctrl == _TRUE)
++			SET_TX_DESC_DATA_RETRY_LIMIT_8723D(pbuf, 6);
++		else
++			SET_TX_DESC_DATA_RETRY_LIMIT_8723D(pbuf, 12);
++#endif
++		SET_TX_DESC_TX_RATE_8723D(pbuf, MRateToHwRate(pattrib->rate));
++
++#ifdef CONFIG_XMIT_ACK
++		/* CCX-TXRPT ack for xmit mgmt frames. */
++		if (pxmitframe->ack_report) {
++#ifdef DBG_CCX
++			RTW_INFO("%s set spe_rpt\n", __FUNCTION__);
++#endif
++			SET_TX_DESC_CCX_8723D(pbuf, 1);
++			SET_TX_DESC_SW_DEFINE_8723D(pbuf, (u8)(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.seq_no));
++		}
++#endif /* CONFIG_XMIT_ACK */
++	} else if (pxmitframe->frame_tag == TXAGG_FRAMETAG) {
++	}
++#ifdef CONFIG_MP_INCLUDED
++	else if (pxmitframe->frame_tag == MP_FRAMETAG) {
++		fill_txdesc_for_mp(padapter, pbuf);
++	}
++#endif
++	else {
++
++		SET_TX_DESC_MACID_8723D(pbuf, pattrib->mac_id);
++		SET_TX_DESC_RATE_ID_8723D(pbuf, pattrib->raid);
++		SET_TX_DESC_QUEUE_SEL_8723D(pbuf, pattrib->qsel);
++		SET_TX_DESC_SEQ_8723D(pbuf, pattrib->seqnum);
++		SET_TX_DESC_USE_RATE_8723D(pbuf, 1);
++		SET_TX_DESC_TX_RATE_8723D(pbuf, MRateToHwRate(pmlmeext->tx_rate));
++	}
++
++	SET_TX_DESC_PKT_SIZE_8723D(pbuf, pattrib->last_txcmdsz);
++
++	{
++		u8 pkt_offset, offset;
++
++		pkt_offset = 0;
++		offset = TXDESC_SIZE;
++#ifdef CONFIG_USB_HCI
++		pkt_offset = pxmitframe->pkt_offset;
++		offset += (pxmitframe->pkt_offset >> 3);
++#endif /* CONFIG_USB_HCI */
++
++#ifdef CONFIG_TX_EARLY_MODE
++		if (pxmitframe->frame_tag == DATA_FRAMETAG) {
++			pkt_offset = 1;
++			offset += EARLY_MODE_INFO_SIZE;
++		}
++#endif /* CONFIG_TX_EARLY_MODE */
++
++		SET_TX_DESC_PKT_OFFSET_8723D(pbuf, pkt_offset);
++		SET_TX_DESC_OFFSET_8723D(pbuf, offset);
++	}
++
++	if (bmcst)
++		SET_TX_DESC_BMC_8723D(pbuf, 1);
++
++	/* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. */
++	/* (1) The sequence number of each non-Qos frame / broadcast / multicast / */
++	/* mgnt frame should be controlled by Hw because Fw will also send null data */
++	/* which we cannot control when Fw LPS enable. */
++	/* --> default enable non-Qos data sequense number. 2010.06.23. by tynli. */
++	/* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. */
++	/* (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. */
++	/* 2010.06.23. Added by tynli. */
++	if (!pattrib->qos_en)
++		SET_TX_DESC_HWSEQ_EN_8723D(pbuf, 1);
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	if (!bmcst && pattrib->psta)
++		odm_set_tx_ant_by_tx_info(adapter_to_phydm(padapter), pbuf, pattrib->psta->cmn.mac_id);
++#endif
++}
++
++/*
++ *	Description:
++ *
++ *	Parameters:
++ *		pxmitframe	xmitframe
++ *		pbuf		where to fill tx desc
++ */
++void rtl8723d_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)
++{
++	rtl8723d_fill_default_txdesc(pxmitframe, pbuf);
++
++#if defined(CONFIG_USB_HCI)
++	rtl8723d_cal_txdesc_chksum((struct tx_desc *)pbuf);
++#endif
++}
++
++static void hw_var_set_monitor(PADAPTER adapter, u8 variable, u8 *val)
++{
++#ifdef CONFIG_WIFI_MONITOR
++	u32 tmp_32bit;
++	struct net_device *ndev = adapter->pnetdev;
++	struct mon_reg_backup *mon = &GET_HAL_DATA(adapter)->mon_backup;
++
++	mon->known_rcr = 1;
++	rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)& mon->rcr);
++
++	/* Receive all type */
++	tmp_32bit = RCR_AAP | RCR_APP_PHYST_RXFF;
++
++	if (ndev->type == ARPHRD_IEEE80211_RADIOTAP) {
++		/* Append FCS */
++		tmp_32bit |= RCR_APPFCS;
++	}
++
++	rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)& tmp_32bit);
++
++	/* Receive all data frames */
++	mon->known_rxfilter = 1;
++	mon->rxfilter0 = rtw_read16(adapter, REG_RXFLTMAP0_8723D);
++	mon->rxfilter1 = rtw_read16(adapter, REG_RXFLTMAP1_8723D);
++	mon->rxfilter2 = rtw_read16(adapter, REG_RXFLTMAP2_8723D);
++	rtw_write16(adapter, REG_RXFLTMAP0_8723D, 0xFFFF);
++	rtw_write16(adapter, REG_RXFLTMAP1_8723D, 0xFFFF);
++	rtw_write16(adapter, REG_RXFLTMAP2_8723D, 0xFFFF);
++#endif /* CONFIG_WIFI_MONITOR */
++}
++
++static void hw_var_set_opmode(PADAPTER padapter, u8 variable, u8 *val)
++{
++	u8 val8;
++	u8 mode = *((u8 *)val);
++	static u8 isMonitor = _FALSE;
++
++	HAL_DATA_TYPE			*pHalData = GET_HAL_DATA(padapter);
++
++	if (isMonitor == _TRUE) {
++#ifdef CONFIG_WIFI_MONITOR
++		struct mon_reg_backup *backup = &GET_HAL_DATA(padapter)->mon_backup;
++
++		if (backup->known_rcr) {
++			backup->known_rcr = 0;
++			rtw_hal_set_hwreg(padapter, HW_VAR_RCR, (u8 *)&backup->rcr);
++			rtw_hal_rcr_set_chk_bssid(padapter, MLME_ACTION_NONE);
++		}
++		if (backup->known_rxfilter) {
++			backup->known_rxfilter = 0;
++			rtw_write16(padapter, REG_RXFLTMAP0_8723D, backup->rxfilter0);
++			rtw_write16(padapter, REG_RXFLTMAP1_8723D, backup->rxfilter1);
++			rtw_write16(padapter, REG_RXFLTMAP2_8723D, backup->rxfilter2);
++		}
++#endif /* CONFIG_WIFI_MONITOR */
++		isMonitor = _FALSE;
++	}
++
++	if (mode == _HW_STATE_MONITOR_) {
++		isMonitor = _TRUE;
++		/* set net_type */
++		Set_MSR(padapter, _HW_STATE_NOLINK_);
++
++		hw_var_set_monitor(padapter, variable, val);
++		return;
++	}
++	/* set mac addr to mac register */
++	rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR,
++			  adapter_mac_addr(padapter));
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (padapter->hw_port == HW_PORT1) {
++		/* disable Port1 TSF update */
++		rtw_iface_disable_tsf_update(padapter);
++
++		Set_MSR(padapter, mode);
++
++		RTW_INFO("#### %s()-%d hw_port(%d) mode=%d ####\n",
++			 __func__, __LINE__, padapter->hw_port, mode);
++
++		if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
++			if (!rtw_mi_get_ap_num(padapter) && !rtw_mi_get_mesh_num(padapter)) {
++				StopTxBeacon(padapter);
++#ifdef CONFIG_PCI_HCI
++				UpdateInterruptMask8723DE(padapter, 0, 0, RT_BCN_INT_MASKS, 0);
++#else /* !CONFIG_PCI_HCI */
++#ifdef CONFIG_INTERRUPT_BASED_TXBCN
++
++#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
++				rtw_write8(padapter, REG_DRVERLYINT, 0x05);/* restore early int time to 5ms */
++				UpdateInterruptMask8723DU(padapter, _TRUE, 0, IMR_BCNDMAINT0_8723D);
++#endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
++
++#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
++				UpdateInterruptMask8723DU(padapter, _TRUE , 0, (IMR_TXBCN0ERR_8723D | IMR_TXBCN0OK_8723D));
++#endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
++
++#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
++#endif /* !CONFIG_PCI_HCI */
++			}
++
++			/* disable atim wnd */
++			rtw_write8(padapter, REG_BCN_CTRL_1, DIS_TSF_UDT | DIS_ATIM | EN_BCN_FUNCTION);
++		} else if (mode == _HW_STATE_ADHOC_) {
++			ResumeTxBeacon(padapter);
++			rtw_write8(padapter, REG_BCN_CTRL_1, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
++		} else if (mode == _HW_STATE_AP_) {
++#ifdef CONFIG_PCI_HCI
++			UpdateInterruptMask8723DE(padapter, RT_BCN_INT_MASKS, 0, 0, 0);
++#else /* !CONFIG_PCI_HCI */
++#ifdef CONFIG_INTERRUPT_BASED_TXBCN
++
++#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
++			UpdateInterruptMask8723DU(padapter, _TRUE, IMR_BCNDMAINT0_8723D, 0);
++#endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
++
++#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
++			UpdateInterruptMask8723DU(padapter, _TRUE, (IMR_TXBCN0ERR_8723D | IMR_TXBCN0OK_8723D), 0);
++#endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
++
++#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
++#endif /* !CONFIG_PCI_HCI */
++
++			rtw_write8(padapter, REG_BCN_CTRL_1, DIS_TSF_UDT | DIS_BCNQ_SUB);
++
++			/* enable to rx data frame*/
++			rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
++			/* enable to rx ps-poll */
++			rtw_write16(padapter, REG_RXFLTMAP1, 0x0400);
++
++			/* Beacon Control related register for first time */
++			rtw_write8(padapter, REG_BCNDMATIM, 0x02); /* 2ms */
++
++			/* rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF); */
++			rtw_write8(padapter, REG_ATIMWND_1, 0x0c); /* 13ms for port1 */
++
++			rtw_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
++
++			/* reset TSF2 */
++			rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(1));
++
++			/* enable BCN1 Function for if2 */
++			/* don't enable update TSF1 for if2 (due to TSF update when beacon/probe rsp are received) */
++			rtw_write8(padapter, REG_BCN_CTRL_1, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB));
++
++			/* SW_BCN_SEL - Port1 */
++			/* rtw_write8(Adapter, REG_DWBCN1_CTRL_8192E+2, rtw_read8(Adapter, REG_DWBCN1_CTRL_8192E+2)|BIT4); */
++			rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
++
++			/* select BCN on port 1 */
++			rtw_write8(padapter, REG_CCK_CHECK_8723D,
++				(rtw_read8(padapter, REG_CCK_CHECK_8723D) | BIT_BCN_PORT_SEL));
++
++			/* BCN1 TSF will sync to BCN0 TSF with offset(0x518) if if1_sta linked */
++			/* rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1)|BIT(5)); */
++			/* rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(3)); */
++
++			/* dis BCN0 ATIM  WND if if1 is station */
++			rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) | DIS_ATIM);
++
++#ifdef CONFIG_TSF_RESET_OFFLOAD
++			/* Reset TSF for STA+AP concurrent mode */
++			if (DEV_STA_LD_NUM(adapter_to_dvobj(padapter))) {
++				if (rtw_hal_reset_tsf(padapter, HW_PORT1) == _FAIL)
++					RTW_INFO("ERROR! %s()-%d: Reset port1 TSF fail\n",
++						 __FUNCTION__, __LINE__);
++			}
++#endif /* CONFIG_TSF_RESET_OFFLOAD */
++		}
++	} else /* else for port0 */
++#endif /* CONFIG_CONCURRENT_MODE */
++	{
++#ifdef CONFIG_MI_WITH_MBSSID_CAM /*For Port0 - MBSS CAM*/
++		hw_var_set_opmode_mbid(padapter, mode);
++#else
++		/* disable Port0 TSF update */
++		rtw_iface_disable_tsf_update(padapter);
++
++		/* set net_type */
++		Set_MSR(padapter, mode);
++		RTW_INFO("#### %s() -%d hw_port(0) mode = %d ####\n",
++			 __func__, __LINE__, mode);
++
++		if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
++#ifdef CONFIG_CONCURRENT_MODE
++			if (!rtw_mi_get_ap_num(padapter) && !rtw_mi_get_mesh_num(padapter)) {
++#else
++			{
++#endif /* CONFIG_CONCURRENT_MODE */
++				StopTxBeacon(padapter);
++#ifdef CONFIG_PCI_HCI
++				UpdateInterruptMask8723DE(padapter, 0, 0, RT_BCN_INT_MASKS, 0);
++#else /* !CONFIG_PCI_HCI */
++#ifdef CONFIG_INTERRUPT_BASED_TXBCN
++#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
++				rtw_write8(padapter, REG_DRVERLYINT, 0x05); /* restore early int time to 5ms */
++				UpdateInterruptMask8812AU(padapter, _TRUE, 0, IMR_BCNDMAINT0_8723D);
++#endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
++
++#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
++				UpdateInterruptMask8812AU(padapter, _TRUE , 0, (IMR_TXBCN0ERR_8723D | IMR_TXBCN0OK_8723D));
++#endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
++
++#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
++#endif /* !CONFIG_PCI_HCI */
++			}
++
++			/* disable atim wnd */
++			rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_ATIM);
++			/* rtw_write8(padapter,REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION); */
++		} else if (mode == _HW_STATE_ADHOC_) {
++			ResumeTxBeacon(padapter);
++			rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
++		} else if (mode == _HW_STATE_AP_) {
++#ifdef CONFIG_PCI_HCI
++			UpdateInterruptMask8723DE(padapter, RT_BCN_INT_MASKS, 0, 0, 0);
++#else /* !CONFIG_PCI_HCI */
++#ifdef CONFIG_INTERRUPT_BASED_TXBCN
++#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
++			UpdateInterruptMask8723DU(padapter, _TRUE , IMR_BCNDMAINT0_8723D, 0);
++#endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
++
++#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
++			UpdateInterruptMask8723DU(padapter, _TRUE , (IMR_TXBCN0ERR_8723D | IMR_TXBCN0OK_8723D), 0);
++#endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
++
++#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
++#endif
++
++			rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | DIS_BCNQ_SUB);
++
++			/* enable to rx data frame */
++			rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
++			/* enable to rx ps-poll */
++			rtw_write16(padapter, REG_RXFLTMAP1, 0x0400);
++
++			/* Beacon Control related register for first time */
++			rtw_write8(padapter, REG_BCNDMATIM, 0x02); /* 2ms */
++
++			/* rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF); */
++			rtw_write8(padapter, REG_ATIMWND, 0x0c); /* 13ms */
++
++			rtw_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
++
++			/* reset TSF */
++			rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
++
++			/* enable BCN0 Function for if1 */
++			/* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */
++			rtw_write8(padapter, REG_BCN_CTRL, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB));
++
++			/* SW_BCN_SEL - Port0 */
++			/* rtw_write8(Adapter, REG_DWBCN1_CTRL_8192E+2, rtw_read8(Adapter, REG_DWBCN1_CTRL_8192E+2) & ~BIT4); */
++			rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
++
++			/* select BCN on port 0 */
++			rtw_write8(padapter, REG_CCK_CHECK_8723D,
++				(rtw_read8(padapter, REG_CCK_CHECK_8723D) & ~BIT_BCN_PORT_SEL));
++
++			/* dis BCN1 ATIM  WND if if2 is station */
++			val8 = rtw_read8(padapter, REG_BCN_CTRL_1);
++			val8 |= DIS_ATIM;
++			rtw_write8(padapter, REG_BCN_CTRL_1, val8);
++#ifdef CONFIG_TSF_RESET_OFFLOAD
++			/* Reset TSF for STA+AP concurrent mode */
++			if (DEV_STA_LD_NUM(adapter_to_dvobj(padapter))) {
++				if (rtw_hal_reset_tsf(padapter, HW_PORT0) == _FAIL)
++					RTW_INFO("ERROR! %s()-%d: Reset port0 TSF fail\n",
++						 __FUNCTION__, __LINE__);
++			}
++#endif /* CONFIG_TSF_RESET_OFFLOAD */
++		}
++#endif /* !CONFIG_MI_WITH_MBSSID_CAM */
++	}
++}
++
++void CCX_FwC2HTxRpt_8723d(PADAPTER padapter, u8 *pdata, u8 len)
++{
++	u8 seq_no;
++
++#define	GET_8723D_C2H_TX_RPT_LIFE_TIME_OVER(_Header)	LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
++#define	GET_8723D_C2H_TX_RPT_RETRY_OVER(_Header)	LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
++
++	/* RTW_INFO("%s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", __func__,  */
++	/**pdata, *(pdata+1), *(pdata+2), *(pdata+3), *(pdata+4), *(pdata+5), *(pdata+6), *(pdata+7)); */
++
++	seq_no = *(pdata + 6);
++
++#ifdef CONFIG_XMIT_ACK
++	if (GET_8723D_C2H_TX_RPT_RETRY_OVER(pdata) | GET_8723D_C2H_TX_RPT_LIFE_TIME_OVER(pdata))
++		rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
++	/*
++	else if(seq_no != padapter->xmitpriv.seq_no) {
++		RTW_INFO("tx_seq_no=%d, rpt_seq_no=%d\n", padapter->xmitpriv.seq_no, seq_no);
++		rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
++	}
++	*/
++	else
++		rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_SUCCESS);
++#endif
++}
++
++s32 c2h_handler_8723d(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
++{
++	s32 ret = _SUCCESS;
++
++	switch (id) {
++	case C2H_CCX_TX_RPT:
++		CCX_FwC2HTxRpt_8723d(adapter, payload, plen);
++		break;
++	default:
++		ret = _FAIL;
++		break;
++	}
++
++	return ret;
++}
++
++u8 SetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
++	u8 ret = _SUCCESS;
++	u8 val8;
++	u16 val16;
++	u32 val32;
++
++
++	switch (variable) {
++	case HW_VAR_SET_OPMODE:
++		hw_var_set_opmode(padapter, variable, val);
++		break;
++
++	case HW_VAR_BASIC_RATE:
++		rtw_var_set_basic_rate(padapter, val);
++		break;
++
++	case HW_VAR_TXPAUSE:
++		rtw_write8(padapter, REG_TXPAUSE, *val);
++		break;
++
++	case HW_VAR_SLOT_TIME:
++		rtw_write8(padapter, REG_SLOT, *val);
++		break;
++
++	case HW_VAR_RESP_SIFS:
++#if 0
++		/* SIFS for OFDM Data ACK */
++		rtw_write8(padapter, REG_SIFS_CTX + 1, val[0]);
++		/* SIFS for OFDM consecutive tx like CTS data! */
++		rtw_write8(padapter, REG_SIFS_TRX + 1, val[1]);
++
++		rtw_write8(padapter, REG_SPEC_SIFS + 1, val[0]);
++		rtw_write8(padapter, REG_MAC_SPEC_SIFS + 1, val[0]);
++
++		/* 20100719 Joseph: Revise SIFS setting due to Hardware register definition change. */
++		rtw_write8(padapter, REG_R2T_SIFS + 1, val[0]);
++		rtw_write8(padapter, REG_T2T_SIFS + 1, val[0]);
++
++#else
++		/* SIFS_Timer = 0x0a0a0808; */
++		/* RESP_SIFS for CCK */
++		rtw_write8(padapter, REG_RESP_SIFS_CCK, val[0]); /* SIFS_T2T_CCK (0x08) */
++		rtw_write8(padapter, REG_RESP_SIFS_CCK + 1, val[1]); /* SIFS_R2T_CCK(0x08) */
++		/* RESP_SIFS for OFDM */
++		rtw_write8(padapter, REG_RESP_SIFS_OFDM, val[2]); /* SIFS_T2T_OFDM (0x0a) */
++		rtw_write8(padapter, REG_RESP_SIFS_OFDM + 1, val[3]); /* SIFS_R2T_OFDM(0x0a) */
++#endif
++		break;
++
++	case HW_VAR_ACK_PREAMBLE: {
++		u8 regTmp;
++		u8 bShortPreamble = *val;
++
++		/* Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */
++		/* regTmp = (pHalData->nCur40MhzPrimeSC)<<5; */
++		regTmp = rtw_read8(padapter, REG_WMAC_TRXPTCL_CTL + 2);
++		if (bShortPreamble) {
++			regTmp |= BIT(1);/*668[17]*/
++		} else {
++			regTmp &= ~BIT(1);
++		}
++		rtw_write8(padapter, REG_WMAC_TRXPTCL_CTL + 2, regTmp);
++	}
++		break;
++
++	case HW_VAR_CAM_INVALID_ALL:
++		rtw_write32(padapter, REG_CAMCMD, BIT(31) | BIT(30));
++		break;
++
++	case HW_VAR_AC_PARAM_VO:
++		rtw_write32(padapter, REG_EDCA_VO_PARAM, *((u32 *)val));
++		break;
++
++	case HW_VAR_AC_PARAM_VI:
++		rtw_write32(padapter, REG_EDCA_VI_PARAM, *((u32 *)val));
++		break;
++
++	case HW_VAR_AC_PARAM_BE:
++		pHalData->ac_param_be = ((u32 *)(val))[0];
++		rtw_write32(padapter, REG_EDCA_BE_PARAM, *((u32 *)val));
++		break;
++
++	case HW_VAR_AC_PARAM_BK:
++		rtw_write32(padapter, REG_EDCA_BK_PARAM, *((u32 *)val));
++		break;
++
++	case HW_VAR_ACM_CTRL: {
++		u8 ctrl = *((u8 *)val);
++		u8 hwctrl = 0;
++
++		if (ctrl != 0) {
++			hwctrl |= AcmHw_HwEn;
++
++		if (ctrl & BIT(3)) /* BE */
++			hwctrl |= AcmHw_BeqEn;
++
++		if (ctrl & BIT(2)) /* VI */
++			hwctrl |= AcmHw_ViqEn;
++
++		if (ctrl & BIT(1)) /* VO */
++			hwctrl |= AcmHw_VoqEn;
++		}
++
++		RTW_INFO("[HW_VAR_ACM_CTRL] Write 0x%02X\n", hwctrl);
++		rtw_write8(padapter, REG_ACMHWCTRL, hwctrl);
++	}
++		break;
++#ifdef CONFIG_80211N_HT
++	case HW_VAR_AMPDU_FACTOR: {
++		u32	AMPDULen = (*((u8 *)val));
++
++		if (AMPDULen < HT_AGG_SIZE_32K)
++			AMPDULen = (0x2000 << (*((u8 *)val))) - 1;
++		else
++			AMPDULen = 0x7fff;
++
++		rtw_write32(padapter, REG_AMPDU_MAX_LENGTH_8723D, AMPDULen);
++	}
++		break;
++#endif /* CONFIG_80211N_HT */
++	case HW_VAR_H2C_FW_PWRMODE: {
++		u8 psmode = *val;
++
++		/* if (psmode != PS_MODE_ACTIVE)	{ */
++			/*rtl8723d_set_lowpwr_lps_cmd(padapter, _TRUE); */
++		/* } else { */
++			/*	rtl8723d_set_lowpwr_lps_cmd(padapter, _FALSE); */
++		/* } */
++		rtl8723d_set_FwPwrMode_cmd(padapter, psmode);
++	}
++		break;
++	case HW_VAR_H2C_PS_TUNE_PARAM:
++		rtl8723d_set_FwPsTuneParam_cmd(padapter);
++		break;
++
++	case HW_VAR_H2C_FW_JOINBSSRPT:
++		rtl8723d_set_FwJoinBssRpt_cmd(padapter, *val);
++#ifdef CONFIG_LPS_POFF
++		rtl8723d_lps_poff_h2c_ctrl(padapter, *val);
++#endif
++		break;
++
++	case HW_VAR_DL_RSVD_PAGE:
++#ifdef CONFIG_BT_COEXIST
++		if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
++			rtl8723d_download_BTCoex_AP_mode_rsvd_page(padapter);
++		else
++#endif /* CONFIG_BT_COEXIST */
++		{
++			rtl8723d_download_rsvd_page(padapter, RT_MEDIA_CONNECT);
++		}
++		break;
++
++#ifdef CONFIG_P2P
++	case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
++		rtl8723d_set_p2p_ps_offload_cmd(padapter, *val);
++		break;
++#endif /* CONFIG_P2P */
++#ifdef CONFIG_LPS_POFF
++	case HW_VAR_LPS_POFF_INIT:
++		rtl8723d_lps_poff_init(padapter);
++		break;
++	case HW_VAR_LPS_POFF_DEINIT:
++		rtl8723d_lps_poff_deinit(padapter);
++		break;
++	case HW_VAR_LPS_POFF_SET_MODE:
++		rtl8723d_lps_poff_set_ps_mode(padapter, *val);
++		break;
++	case HW_VAR_LPS_POFF_WOW_EN:
++		rtl8723d_lps_poff_h2c_ctrl(padapter, *val);
++		break;
++#endif /*CONFIG_LPS_POFF*/
++
++	case HW_VAR_EFUSE_USAGE:
++		pHalData->EfuseUsedPercentage = *val;
++		break;
++
++	case HW_VAR_EFUSE_BYTES:
++		pHalData->EfuseUsedBytes = *((u16 *)val);
++		break;
++
++	case HW_VAR_EFUSE_BT_USAGE:
++#ifdef HAL_EFUSE_MEMORY
++		pHalData->EfuseHal.BTEfuseUsedPercentage = *val;
++#endif
++		break;
++
++	case HW_VAR_EFUSE_BT_BYTES:
++#ifdef HAL_EFUSE_MEMORY
++		pHalData->EfuseHal.BTEfuseUsedBytes = *((u16 *)val);
++#else
++		BTEfuseUsedBytes = *((u16 *)val);
++#endif
++		break;
++
++	case HW_VAR_FIFO_CLEARN_UP: {
++#define RW_RELEASE_EN		BIT(18)
++#define RXDMA_IDLE			BIT(17)
++
++		struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++		u8 trycnt = 100;
++
++		/* pause tx */
++		rtw_write8(padapter, REG_TXPAUSE, 0xff);
++
++		/* keep sn */
++		padapter->xmitpriv.nqos_ssn = rtw_read16(padapter, REG_NQOS_SEQ);
++
++		if (pwrpriv->bkeepfwalive != _TRUE) {
++			/* RX DMA stop */
++			val32 = rtw_read32(padapter, REG_RXPKT_NUM);
++			val32 |= RW_RELEASE_EN;
++			rtw_write32(padapter, REG_RXPKT_NUM, val32);
++			do {
++				val32 = rtw_read32(padapter, REG_RXPKT_NUM);
++				val32 &= RXDMA_IDLE;
++				if (val32)
++					break;
++
++				RTW_INFO("%s: [HW_VAR_FIFO_CLEARN_UP] val=%x times:%d\n", __FUNCTION__, val32, trycnt);
++			} while (--trycnt);
++			if (trycnt == 0)
++				RTW_INFO("[HW_VAR_FIFO_CLEARN_UP] Stop RX DMA failed......\n");
++
++			/* RQPN Load 0 */
++			rtw_write16(padapter, REG_RQPN_NPQ, 0);
++			rtw_write32(padapter, REG_RQPN, 0x80000000);
++			rtw_mdelay_os(2);
++		}
++	}
++	break;
++
++	case HW_VAR_RESTORE_HW_SEQ:
++		/* restore Sequence No. */
++		rtw_write8(padapter, 0x4dc, padapter->xmitpriv.nqos_ssn);
++		break;
++
++#ifdef CONFIG_CONCURRENT_MODE
++	case HW_VAR_CHECK_TXBUF: {
++		u32 i;
++		u8 RetryLimit = 0x01;
++		u32 reg_200, reg_204;
++
++		val16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit);
++		rtw_write16(padapter, REG_RETRY_LIMIT, val16);
++
++		for (i = 0; i < 200; i++) { /* polling 200x10=2000 msec */
++			reg_200 = rtw_read32(padapter, 0x200);
++			reg_204 = rtw_read32(padapter, 0x204);
++			if (reg_200 != reg_204) {
++			/* RTW_INFO("packet in tx packet buffer - 0x204=%x, 0x200=%x (%d)\n", rtw_read32(padapter, 0x204), rtw_read32(padapter, 0x200), i); */
++				rtw_msleep_os(10);
++			} else {
++				RTW_INFO("[HW_VAR_CHECK_TXBUF] no packet in tx packet buffer (%d)\n", i);
++				break;
++			}
++		}
++
++		if (reg_200 != reg_204)
++			RTW_INFO("packets in tx buffer - 0x204=%x, 0x200=%x\n", reg_204, reg_200);
++
++		RetryLimit = RL_VAL_STA;
++		val16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit);
++		rtw_write16(padapter, REG_RETRY_LIMIT, val16);
++	}
++		break;
++#endif /* CONFIG_CONCURRENT_MODE */
++
++	case HW_VAR_NAV_UPPER: {
++		u32 usNavUpper = *((u32 *)val);
++
++		if (usNavUpper > HAL_NAV_UPPER_UNIT_8723D * 0xFF) {
++		break;
++	}
++
++		/* The value of ((usNavUpper + HAL_NAV_UPPER_UNIT_8723D - 1) / HAL_NAV_UPPER_UNIT_8723D) */
++		/* is getting the upper integer. */
++		usNavUpper = (usNavUpper + HAL_NAV_UPPER_UNIT_8723D - 1) / HAL_NAV_UPPER_UNIT_8723D;
++		rtw_write8(padapter, REG_NAV_UPPER, (u8)usNavUpper);
++	}
++		break;
++
++	case HW_VAR_BCN_VALID:
++#ifdef CONFIG_CONCURRENT_MODE
++		if (padapter->hw_port == HW_PORT1) {
++			val8 = rtw_read8(padapter,  REG_DWBCN1_CTRL_8723D + 2);
++			val8 |= BIT(0);
++			rtw_write8(padapter, REG_DWBCN1_CTRL_8723D + 2, val8);
++		} else
++#endif /* CONFIG_CONCURRENT_MODE */
++		{
++		/* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */
++			val8 = rtw_read8(padapter, REG_TDECTRL + 2);
++			val8 |= BIT(0);
++			rtw_write8(padapter, REG_TDECTRL + 2, val8);
++		}
++		break;
++	case HW_VAR_DL_BCN_SEL:
++#ifdef CONFIG_CONCURRENT_MODE
++		if (padapter->hw_port == HW_PORT1) {
++			/* SW_BCN_SEL - Port1 */
++			val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8723D + 2);
++			val8 |= BIT(4);
++			rtw_write8(padapter, REG_DWBCN1_CTRL_8723D + 2, val8);
++		} else
++#endif /* CONFIG_CONCURRENT_MODE */
++		{
++			/* SW_BCN_SEL - Port0 */
++			val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8723D + 2);
++			val8 &= ~BIT(4);
++			rtw_write8(padapter, REG_DWBCN1_CTRL_8723D + 2, val8);
++		}
++		break;
++
++#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
++	case HW_VAR_TDLS_BCN_EARLY_C2H_RPT:
++		rtl8723d_set_BcnEarly_C2H_Rpt_cmd(padapter, *val);
++		break;
++#endif	
++	default:
++		ret = SetHwReg(padapter, variable, val);
++		break;
++	}
++
++	return ret;
++}
++
++struct qinfo_8723d {
++	u32 head:8;
++	u32 pkt_num:7;
++	u32 tail:8;
++	u32 ac:2;
++	u32 macid:7;
++};
++
++struct bcn_qinfo_8723d {
++	u16 head:8;
++	u16 pkt_num:8;
++};
++
++void dump_qinfo_8723d(void *sel, struct qinfo_8723d *info, const char *tag)
++{
++	/* if (info->pkt_num) */
++	RTW_PRINT_SEL(sel, "%shead:0x%02x, tail:0x%02x, pkt_num:%u, macid:%u, ac:%u\n"
++		, tag ? tag : "", info->head, info->tail,
++		info->pkt_num, info->macid, info->ac);
++}
++
++void dump_bcn_qinfo_8723d(void *sel, struct bcn_qinfo_8723d *info, const char *tag)
++{
++	/* if (info->pkt_num) */
++	RTW_PRINT_SEL(sel, "%shead:0x%02x, pkt_num:%u\n"
++		      , tag ? tag : "", info->head, info->pkt_num);
++}
++
++void dump_mac_qinfo_8723d(void *sel, _adapter *adapter)
++{
++	u32 q0_info;
++	u32 q1_info;
++	u32 q2_info;
++	u32 q3_info;
++	u32 q4_info;
++	u32 q5_info;
++	u32 q6_info;
++	u32 q7_info;
++	u32 mg_q_info;
++	u32 hi_q_info;
++	u16 bcn_q_info;
++
++	q0_info = rtw_read32(adapter, REG_Q0_INFO);
++	q1_info = rtw_read32(adapter, REG_Q1_INFO);
++	q2_info = rtw_read32(adapter, REG_Q2_INFO);
++	q3_info = rtw_read32(adapter, REG_Q3_INFO);
++	q4_info = rtw_read32(adapter, REG_Q4_INFO);
++	q5_info = rtw_read32(adapter, REG_Q5_INFO);
++	q6_info = rtw_read32(adapter, REG_Q6_INFO);
++	q7_info = rtw_read32(adapter, REG_Q7_INFO);
++	mg_q_info = rtw_read32(adapter, REG_MGQ_INFO);
++	hi_q_info = rtw_read32(adapter, REG_HGQ_INFO);
++	bcn_q_info = rtw_read16(adapter, REG_BCNQ_INFO);
++
++	dump_qinfo_8723d(sel, (struct qinfo_8723d *)&q0_info, "Q0 ");
++	dump_qinfo_8723d(sel, (struct qinfo_8723d *)&q1_info, "Q1 ");
++	dump_qinfo_8723d(sel, (struct qinfo_8723d *)&q2_info, "Q2 ");
++	dump_qinfo_8723d(sel, (struct qinfo_8723d *)&q3_info, "Q3 ");
++	dump_qinfo_8723d(sel, (struct qinfo_8723d *)&q4_info, "Q4 ");
++	dump_qinfo_8723d(sel, (struct qinfo_8723d *)&q5_info, "Q5 ");
++	dump_qinfo_8723d(sel, (struct qinfo_8723d *)&q6_info, "Q6 ");
++	dump_qinfo_8723d(sel, (struct qinfo_8723d *)&q7_info, "Q7 ");
++	dump_qinfo_8723d(sel, (struct qinfo_8723d *)&mg_q_info, "MG ");
++	dump_qinfo_8723d(sel, (struct qinfo_8723d *)&hi_q_info, "HI ");
++	dump_bcn_qinfo_8723d(sel, (struct bcn_qinfo_8723d *)&bcn_q_info, "BCN ");
++}
++
++static void dump_mac_txfifo_8723d(void *sel, _adapter *adapter)
++{
++	u32 rqpn, rqpn_npq;
++	u32 hpq, lpq, npq, epq, pubq;
++
++	rqpn = rtw_read32(adapter, REG_FIFOPAGE);
++	rqpn_npq = rtw_read32(adapter, REG_RQPN_NPQ);
++
++	hpq = (rqpn & 0xFF);
++	lpq = ((rqpn & 0xFF00)>>8);
++	pubq = ((rqpn & 0xFF0000)>>16);
++	npq = ((rqpn_npq & 0xFF00)>>8);
++	epq = ((rqpn_npq & 0xFF000000)>>24);
++
++	RTW_PRINT_SEL(sel, "Tx: available page num: ");
++	if ((hpq == 0xEA) && (hpq == lpq) && (hpq == pubq))
++		RTW_PRINT_SEL(sel, "N/A (reg val = 0xea)\n");
++	else
++		RTW_PRINT_SEL(sel, "HPQ: %d, LPQ: %d, NPQ: %d, EPQ: %d, PUBQ: %d\n"
++			, hpq, lpq, npq, epq, pubq);
++}
++
++void rtl8723d_read_wmmedca_reg(PADAPTER adapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params)
++{
++	u8 vo_reg_params[4];
++	u8 vi_reg_params[4];
++	u8 be_reg_params[4];
++	u8 bk_reg_params[4];
++
++	GetHwReg8723D(adapter, HW_VAR_AC_PARAM_VO, vo_reg_params);
++	GetHwReg8723D(adapter, HW_VAR_AC_PARAM_VI, vi_reg_params);
++	GetHwReg8723D(adapter, HW_VAR_AC_PARAM_BE, be_reg_params);
++	GetHwReg8723D(adapter, HW_VAR_AC_PARAM_BK, bk_reg_params);
++
++	vo_params[0] = vo_reg_params[0];
++	vo_params[1] = vo_reg_params[1] & 0x0F;
++	vo_params[2] = (vo_reg_params[1] & 0xF0) >> 4;
++	vo_params[3] = ((vo_reg_params[3] << 8) | (vo_reg_params[2])) * 32;
++
++	vi_params[0] = vi_reg_params[0];
++	vi_params[1] = vi_reg_params[1] & 0x0F;
++	vi_params[2] = (vi_reg_params[1] & 0xF0) >> 4;
++	vi_params[3] = ((vi_reg_params[3] << 8) | (vi_reg_params[2])) * 32;
++
++	be_params[0] = be_reg_params[0];
++	be_params[1] = be_reg_params[1] & 0x0F;
++	be_params[2] = (be_reg_params[1] & 0xF0) >> 4;
++	be_params[3] = ((be_reg_params[3] << 8) | (be_reg_params[2])) * 32;
++
++	bk_params[0] = bk_reg_params[0];
++	bk_params[1] = bk_reg_params[1] & 0x0F;
++	bk_params[2] = (bk_reg_params[1] & 0xF0) >> 4;
++	bk_params[3] = ((bk_reg_params[3] << 8) | (bk_reg_params[2])) * 32;
++
++	vo_params[1] = (1 << vo_params[1]) - 1;
++	vo_params[2] = (1 << vo_params[2]) - 1;
++	vi_params[1] = (1 << vi_params[1]) - 1;
++	vi_params[2] = (1 << vi_params[2]) - 1;
++	be_params[1] = (1 << be_params[1]) - 1;
++	be_params[2] = (1 << be_params[2]) - 1;
++	bk_params[1] = (1 << bk_params[1]) - 1;
++	bk_params[2] = (1 << bk_params[2]) - 1;
++}
++
++void GetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++	u8 val8;
++	u16 val16;
++	u32 val32;
++
++	switch (variable) {
++	case HW_VAR_TXPAUSE:
++		*val = rtw_read8(padapter, REG_TXPAUSE);
++		break;
++
++	case HW_VAR_BCN_VALID:
++#ifdef CONFIG_CONCURRENT_MODE
++		if (padapter->hw_port == HW_PORT1) {
++			val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8723D + 2);
++			*val = (BIT(0) & val8) ? _TRUE : _FALSE;
++		} else
++#endif
++		{
++			/* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 */
++			val8 = rtw_read8(padapter, REG_TDECTRL + 2);
++			*val = (BIT(0) & val8) ? _TRUE : _FALSE;
++		}
++		break;
++
++	case HW_VAR_AC_PARAM_VO:
++		val32 = rtw_read32(padapter, REG_EDCA_VO_PARAM);
++		val[0] = val32 & 0xFF;
++		val[1] = (val32 >> 8) & 0xFF;
++		val[2] = (val32 >> 16) & 0xFF;
++		val[3] = (val32 >> 24) & 0x07;
++		break;
++
++	case HW_VAR_AC_PARAM_VI:
++		val32 = rtw_read32(padapter, REG_EDCA_VI_PARAM);
++		val[0] = val32 & 0xFF;
++		val[1] = (val32 >> 8) & 0xFF;
++		val[2] = (val32 >> 16) & 0xFF;
++		val[3] = (val32 >> 24) & 0x07;
++		break;
++
++	case HW_VAR_AC_PARAM_BE:
++		val32 = rtw_read32(padapter, REG_EDCA_BE_PARAM);
++		val[0] = val32 & 0xFF;
++		val[1] = (val32 >> 8) & 0xFF;
++		val[2] = (val32 >> 16) & 0xFF;
++		val[3] = (val32 >> 24) & 0x07;
++		break;
++
++	case HW_VAR_AC_PARAM_BK:
++		val32 = rtw_read32(padapter, REG_EDCA_BK_PARAM);
++		val[0] = val32 & 0xFF;
++		val[1] = (val32 >> 8) & 0xFF;
++		val[2] = (val32 >> 16) & 0xFF;
++		val[3] = (val32 >> 24) & 0x07;
++		break;
++
++	case HW_VAR_EFUSE_USAGE:
++		*val = pHalData->EfuseUsedPercentage;
++		break;
++
++	case HW_VAR_EFUSE_BYTES:
++		*((u16 *)val) = pHalData->EfuseUsedBytes;
++		break;
++
++	case HW_VAR_EFUSE_BT_USAGE:
++#ifdef HAL_EFUSE_MEMORY
++		*val = pHalData->EfuseHal.BTEfuseUsedPercentage;
++#endif
++		break;
++
++	case HW_VAR_EFUSE_BT_BYTES:
++#ifdef HAL_EFUSE_MEMORY
++		*((u16 *)val) = pHalData->EfuseHal.BTEfuseUsedBytes;
++#else
++		*((u16 *)val) = BTEfuseUsedBytes;
++#endif
++		break;
++
++	case HW_VAR_CHK_HI_QUEUE_EMPTY:
++		val16 = rtw_read16(padapter, REG_TXPKT_EMPTY);
++		*val = (val16 & BIT(10)) ? _TRUE : _FALSE;
++		break;
++	case HW_VAR_CHK_MGQ_CPU_EMPTY:
++		val16 = rtw_read16(padapter, REG_TXPKT_EMPTY);
++		*val = (val16 & BIT(8)) ? _TRUE : _FALSE;
++		break;
++#ifdef CONFIG_WOWLAN
++	case HW_VAR_RPWM_TOG:
++		*val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1) & BIT(7);
++		break;
++	case HW_VAR_WAKEUP_REASON:
++		*val = rtw_read8(padapter, REG_WOWLAN_WAKE_REASON);
++		if (*val == 0xEA)
++			*val = 0;
++		break;
++	case HW_VAR_SYS_CLKR:
++		*val = rtw_read8(padapter, REG_SYS_CLKR);
++		break;
++#endif
++	case HW_VAR_DUMP_MAC_QUEUE_INFO:
++		dump_mac_qinfo_8723d(val, padapter);
++		break;
++	case HW_VAR_DUMP_MAC_TXFIFO:
++		dump_mac_txfifo_8723d(val, padapter);
++		break;
++	default:
++		GetHwReg(padapter, variable, val);
++		break;
++	}
++}
++
++/*
++ *	Description:
++ *		Change default setting of specified variable.
++ */
++u8 SetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval)
++{
++	PHAL_DATA_TYPE pHalData;
++	u8 bResult;
++
++	bResult = _SUCCESS;
++
++	switch (variable) {
++	default:
++		bResult = SetHalDefVar(padapter, variable, pval);
++		break;
++	}
++
++	return bResult;
++}
++
++void hal_ra_info_dump(_adapter *padapter , void *sel)
++{
++	int i;
++	u8 mac_id;
++	u32 cmd;
++	u32 ra_info1, ra_info2, bw_set;
++	u32 rate_mask1, rate_mask2;
++	u8 curr_tx_rate, curr_tx_sgi, hight_rate, lowest_rate;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++	HAL_DATA_TYPE *HalData = GET_HAL_DATA(padapter);
++
++	for (i = 0; i < macid_ctl->num; i++) {
++
++		if (rtw_macid_is_used(macid_ctl, i) && !rtw_macid_is_bmc(macid_ctl, i)) {
++
++			mac_id = (u8) i;
++			_RTW_PRINT_SEL(sel , "============ RA status check  Mac_id:%d ===================\n", mac_id);
++
++			cmd = 0x40000100 | mac_id;
++			rtw_write32(padapter, REG_HMEBOX_DBG_2_8723D, cmd);
++			rtw_msleep_os(10);
++			ra_info1 = rtw_read32(padapter, 0x2F0);
++			curr_tx_sgi = rtw_get_current_tx_sgi(padapter, macid_ctl->sta[mac_id]);
++			curr_tx_rate = rtw_get_current_tx_rate(padapter, macid_ctl->sta[mac_id]);
++
++			_RTW_PRINT_SEL(sel , "[ ra_info1:0x%08x ] =>cur_tx_rate= %s,cur_sgi:%d\n", ra_info1, HDATA_RATE(curr_tx_rate), curr_tx_sgi);
++			_RTW_PRINT_SEL(sel , "[ ra_info1:0x%08x ] => PWRSTS = 0x%02x\n", ra_info1, (ra_info1 >> 8)  & 0x07);
++
++			cmd = 0x40000400 | mac_id;
++			rtw_write32(padapter, REG_HMEBOX_DBG_2_8723D, cmd);
++			rtw_msleep_os(10);
++			ra_info1 = rtw_read32(padapter, 0x2F0);
++			ra_info2 = rtw_read32(padapter, 0x2F4);
++			rate_mask1 = rtw_read32(padapter, 0x2F8);
++			rate_mask2 = rtw_read32(padapter, 0x2FC);
++			hight_rate = ra_info2 & 0xFF;
++			lowest_rate = (ra_info2 >> 8)  & 0xFF;
++			bw_set = (ra_info1 >> 8)  & 0xFF;
++
++			_RTW_PRINT_SEL(sel , "[ ra_info1:0x%08x ] => VHT_EN=0x%02x, ", ra_info1, (ra_info1 >> 24) & 0xFF);
++
++
++			switch (bw_set) {
++
++			case CHANNEL_WIDTH_20:
++				_RTW_PRINT_SEL(sel , "BW_setting=20M\n");
++				break;
++
++			case CHANNEL_WIDTH_40:
++				_RTW_PRINT_SEL(sel , "BW_setting=40M\n");
++				break;
++
++			case CHANNEL_WIDTH_80:
++				_RTW_PRINT_SEL(sel , "BW_setting=80M\n");
++				break;
++
++			case CHANNEL_WIDTH_160:
++				_RTW_PRINT_SEL(sel , "BW_setting=160M\n");
++				break;
++
++			default:
++				_RTW_PRINT_SEL(sel , "BW_setting=0x%02x\n", bw_set);
++				break;
++
++			}
++
++			_RTW_PRINT_SEL(sel , "[ ra_info1:0x%08x ] =>RSSI=%d, DISRA=0x%02x\n",
++				       ra_info1,
++				       ra_info1 & 0xFF,
++				       (ra_info1 >> 16) & 0xFF);
++
++			_RTW_PRINT_SEL(sel , "[ ra_info2:0x%08x ] =>hight_rate=%s, lowest_rate=%s, SGI=0x%02x, RateID=%d\n",
++				       ra_info2,
++				       HDATA_RATE(hight_rate),
++				       HDATA_RATE(lowest_rate),
++				       (ra_info2 >> 16) & 0xFF,
++				       (ra_info2 >> 24) & 0xFF);
++
++			_RTW_PRINT_SEL(sel , "rate_mask2=0x%08x, rate_mask1=0x%08x\n", rate_mask2, rate_mask1);
++
++		}
++	}
++}
++
++/*
++ *	Description:
++ *		Query setting of specified variable.
++ */
++u8 GetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval)
++{
++	PHAL_DATA_TYPE pHalData;
++	u8 bResult;
++
++	pHalData = GET_HAL_DATA(padapter);
++	bResult = _SUCCESS;
++
++	switch (variable) {
++	case HAL_DEF_MAX_RECVBUF_SZ:
++		*((u32 *)pval) = MAX_RECVBUF_SZ;
++		break;
++	case HAL_DEF_RX_PACKET_OFFSET:
++#ifdef CONFIG_TRX_BD_ARCH
++		*((u32 *)pval) = RX_WIFI_INFO_SIZE + DRVINFO_SZ * 8;
++#else
++		*((u32 *)pval) = RXDESC_SIZE + DRVINFO_SZ * 8;
++#endif
++		break;
++
++	case HW_VAR_MAX_RX_AMPDU_FACTOR:
++		/* Stanley@BB.SD3 suggests 16K can get stable performance */
++		/* The experiment was done on SDIO interface */
++		/* coding by Lucas@20130730 */
++		*(HT_CAP_AMPDU_FACTOR *)pval = MAX_AMPDU_FACTOR_16K;
++		break;
++	case HW_VAR_BEST_AMPDU_DENSITY:
++		*((u32 *)pval) = AMPDU_DENSITY_VALUE_7;
++		break;
++	case HAL_DEF_TX_LDPC:
++	case HAL_DEF_RX_LDPC:
++		*((u8 *)pval) = _FALSE;
++		break;
++	case HAL_DEF_RX_STBC:
++		*((u8 *)pval) = 1;
++		break;
++	case HAL_DEF_EXPLICIT_BEAMFORMER:
++	case HAL_DEF_EXPLICIT_BEAMFORMEE:
++		*((u8 *)pval) = _FALSE;
++		break;
++
++	case HW_DEF_RA_INFO_DUMP:
++		hal_ra_info_dump(padapter, pval);
++		break;
++
++	case HAL_DEF_TX_PAGE_BOUNDARY:
++		if (!padapter->registrypriv.wifi_spec)
++			*(u8 *)pval = TX_PAGE_BOUNDARY_8723D;
++		else
++			*(u8 *)pval = WMM_NORMAL_TX_PAGE_BOUNDARY_8723D;
++		break;
++	case HAL_DEF_TX_PAGE_SIZE:
++		*((u32 *)pval) = PAGE_SIZE_128;
++		break;
++	case HAL_DEF_RX_DMA_SZ_WOW:
++		*(u32 *)pval = RX_DMA_SIZE_8723D - RESV_FMWF;
++		break;
++	case HAL_DEF_RX_DMA_SZ:
++		*(u32 *)pval = RX_DMA_BOUNDARY_8723D + 1;
++		break;
++	case HAL_DEF_RX_PAGE_SIZE:
++		*((u32 *)pval) = 8;
++		break;
++	default:
++		bResult = GetHalDefVar(padapter, variable, pval);
++		break;
++	}
++
++	return bResult;
++}
++
++#ifdef CONFIG_WOWLAN
++void Hal_DetectWoWMode(PADAPTER pAdapter)
++{
++	adapter_to_pwrctl(pAdapter)->bSupportRemoteWakeup = _TRUE;
++	RTW_INFO("%s\n", __func__);
++}
++#endif /* CONFIG_WOWLAN */
++
++void rtl8723d_start_thread(_adapter *padapter)
++{
++#if (defined CONFIG_SDIO_HCI) || (defined CONFIG_GSPI_HCI)
++#ifndef CONFIG_SDIO_TX_TASKLET
++	struct xmit_priv *xmitpriv = &padapter->xmitpriv;
++
++	if (xmitpriv->SdioXmitThread == NULL) {
++		RTW_INFO(FUNC_ADPT_FMT " start RTWHALXT\n", FUNC_ADPT_ARG(padapter));
++		xmitpriv->SdioXmitThread = kthread_run(rtl8723ds_xmit_thread, padapter, "RTWHALXT");
++		if (IS_ERR(xmitpriv->SdioXmitThread)) {
++			RTW_ERR("%s: start rtl8723ds_xmit_thread FAIL!!\n", __func__);
++			xmitpriv->SdioXmitThread = NULL;
++		}
++	}
++#endif
++#endif
++}
++
++void rtl8723d_stop_thread(_adapter *padapter)
++{
++#if (defined CONFIG_SDIO_HCI) || (defined CONFIG_GSPI_HCI)
++#ifndef CONFIG_SDIO_TX_TASKLET
++	struct xmit_priv *xmitpriv = &padapter->xmitpriv;
++
++	/* stop xmit_buf_thread */
++	if (xmitpriv->SdioXmitThread) {
++		_rtw_up_sema(&xmitpriv->SdioXmitSema);
++		#ifdef SDIO_FREE_XMIT_BUF_SEMA
++		rtw_sdio_free_xmitbuf_sema_up(xmitpriv);
++		rtw_sdio_free_xmitbuf_sema_down(xmitpriv);
++		#endif
++		rtw_thread_stop(xmitpriv->SdioXmitThread);
++		xmitpriv->SdioXmitThread = NULL;
++	}
++#endif
++#endif
++}
++
++#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
++void rtl8723ds_init_checkbthang_workqueue(_adapter *adapter)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
++	adapter->priv_checkbt_wq = alloc_workqueue("sdio_wq", 0, 0);
++#else
++	adapter->priv_checkbt_wq = create_workqueue("sdio_wq");
++#endif
++	INIT_DELAYED_WORK(&adapter->checkbt_work, (void *)check_bt_status_work);
++}
++
++void rtl8723ds_free_checkbthang_workqueue(_adapter *adapter)
++{
++	if (adapter->priv_checkbt_wq) {
++		cancel_delayed_work_sync(&adapter->checkbt_work);
++		flush_workqueue(adapter->priv_checkbt_wq);
++		destroy_workqueue(adapter->priv_checkbt_wq);
++		adapter->priv_checkbt_wq = NULL;
++	}
++}
++
++void rtl8723ds_cancle_checkbthang_workqueue(_adapter *adapter)
++{
++	if (adapter->priv_checkbt_wq)
++		cancel_delayed_work_sync(&adapter->checkbt_work);
++}
++
++void rtl8723ds_hal_check_bt_hang(_adapter *adapter)
++{
++	if (adapter->priv_checkbt_wq)
++		queue_delayed_work(adapter->priv_checkbt_wq, &(adapter->checkbt_work), 0);
++}
++#endif
++
++void rtl8723d_set_hal_ops(struct hal_ops *pHalFunc)
++{
++	pHalFunc->dm_init = &rtl8723d_init_dm_priv;
++	pHalFunc->dm_deinit = &rtl8723d_deinit_dm_priv;
++	pHalFunc->read_chip_version = read_chip_version_8723d;
++	pHalFunc->set_chnl_bw_handler = &PHY_SetSwChnlBWMode8723D;
++	pHalFunc->set_tx_power_level_handler = &PHY_SetTxPowerLevel8723D;
++	pHalFunc->set_tx_power_index_handler = PHY_SetTxPowerIndex_8723D;
++	pHalFunc->get_tx_power_index_handler = hal_com_get_txpwr_idx;
++	pHalFunc->hal_dm_watchdog = &rtl8723d_HalDmWatchDog;
++
++	pHalFunc->SetBeaconRelatedRegistersHandler = &rtl8723d_SetBeaconRelatedRegisters;
++	pHalFunc->run_thread = &rtl8723d_start_thread;
++	pHalFunc->cancel_thread = &rtl8723d_stop_thread;
++	pHalFunc->read_bbreg = &PHY_QueryBBReg_8723D;
++	pHalFunc->write_bbreg = &PHY_SetBBReg_8723D;
++	pHalFunc->read_rfreg = &PHY_QueryRFReg_8723D;
++	pHalFunc->write_rfreg = &PHY_SetRFReg_8723D;
++	pHalFunc->read_wmmedca_reg = &rtl8723d_read_wmmedca_reg;
++
++	/* Efuse related function */
++	pHalFunc->BTEfusePowerSwitch = &Hal_BT_EfusePowerSwitch;
++	pHalFunc->EfusePowerSwitch = &Hal_EfusePowerSwitch;
++	pHalFunc->ReadEFuse = &Hal_ReadEFuse;
++	pHalFunc->EFUSEGetEfuseDefinition = &Hal_GetEfuseDefinition;
++	pHalFunc->EfuseGetCurrentSize = &Hal_EfuseGetCurrentSize;
++	pHalFunc->Efuse_PgPacketRead = &Hal_EfusePgPacketRead;
++	pHalFunc->Efuse_PgPacketWrite = &Hal_EfusePgPacketWrite;
++	pHalFunc->Efuse_WordEnableDataWrite = &Hal_EfuseWordEnableDataWrite;
++	pHalFunc->Efuse_PgPacketWrite_BT = &Hal_EfusePgPacketWrite_BT;
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++	pHalFunc->sreset_init_value = &sreset_init_value;
++	pHalFunc->sreset_reset_value = &sreset_reset_value;
++	pHalFunc->silentreset = &sreset_reset;
++	pHalFunc->sreset_xmit_status_check = &rtl8723d_sreset_xmit_status_check;
++	pHalFunc->sreset_linked_status_check  = &rtl8723d_sreset_linked_status_check;
++	pHalFunc->sreset_get_wifi_status  = &sreset_get_wifi_status;
++	pHalFunc->sreset_inprogress = &sreset_inprogress;
++#endif
++	pHalFunc->GetHalODMVarHandler = GetHalODMVar;
++	pHalFunc->SetHalODMVarHandler = SetHalODMVar;
++
++#ifdef CONFIG_XMIT_THREAD_MODE
++	pHalFunc->xmit_thread_handler = &hal_xmit_handler;
++#endif
++	pHalFunc->hal_notch_filter = &hal_notch_filter_8723d;
++	pHalFunc->c2h_handler = c2h_handler_8723d;
++	pHalFunc->fill_h2c_cmd = &FillH2CCmd8723D;
++	pHalFunc->fill_fake_txdesc = &rtl8723d_fill_fake_txdesc;
++	pHalFunc->fw_dl = &rtl8723d_FirmwareDownload;
++	pHalFunc->hal_get_tx_buff_rsvd_page_num = &GetTxBufferRsvdPageNum8723D;
++}
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_lps_poff.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_lps_poff.c
+new file mode 100644
+index 000000000..1fb8f7f11
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_lps_poff.c
+@@ -0,0 +1,871 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#include <rtl8723d_hal.h>
++
++#ifdef CONFIG_LPS_POFF
++/****************************************************************************
++ * Function: constuct Register Setting for HW to Backup Before LPS
++ *		    page 2/4/6/7/8~F and page 0x24(for NAN)
++*****************************************************************************/
++static bool hal_construct_poff_static_file(PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	lps_poff_info_t *lps_poff_info = NULL;
++	u8	*staticFile = NULL;
++	u8	*start_at = NULL;
++	u8	page_count = 0, page_offset = 0, round = 0;
++	/*There are 256 bytes in each register bank, and  64 dwords*/
++	u8	total = 256 / 4;
++	u16	offset = 0, addr_value = 0;
++
++	if (pwrpriv->plps_poff_info == NULL) {
++		RTW_INFO("%s: please alloc plps_poff_info first!!\n", __func__);
++		return _FALSE;
++	}
++
++	lps_poff_info = pwrpriv->plps_poff_info;
++
++	if (lps_poff_info->pStaticFile == NULL) {
++		RTW_INFO("%s: please alloc static configure file first!!\n",
++			 __func__);
++		return _FALSE;
++	}
++	staticFile = lps_poff_info->pStaticFile + TXDESC_SIZE;
++
++	for (page_count = 2 ; page_count < 16 ; page_count++) {
++		page_offset = 0;
++		if (page_count == 3 || page_count == 5)
++			continue;
++
++		offset = (round << 9);
++
++		for (page_offset = 0 ; page_offset < total ; page_offset++) {
++			start_at = staticFile + offset + (page_offset << 3);
++			addr_value =
++				((page_count << 8) + (page_offset << 2)) >> 2;
++
++			SET_HOIE_ENTRY_LOW_DATA(start_at, 0);
++			SET_HOIE_ENTRY_HIGH_DATA(start_at, 0);
++			SET_HOIE_ENTRY_MODE_SELECT(start_at, 0);
++			SET_HOIE_ENTRY_ADDRESS(start_at, addr_value);
++			SET_HOIE_ENTRY_BYTE_MASK(start_at, 0xF);
++			SET_HOIE_ENTRY_IO_LOCK(start_at, 0);
++			SET_HOIE_ENTRY_WR_EN(start_at, 1);
++			SET_HOIE_ENTRY_RD_EN(start_at, 1);
++			SET_HOIE_ENTRY_RAW_RW(start_at, 0);
++			SET_HOIE_ENTRY_RAW(start_at, 0);
++			SET_HOIE_ENTRY_IO_DELAY(start_at, 0);
++		}
++
++		round++;
++	}
++
++	/*construct page 24*/
++	offset = (round << 9);
++	for (page_offset = 0 ; page_offset < total ; page_offset++) {
++		start_at = staticFile + offset + (page_offset << 3);
++		addr_value = ((0x24 << 8) + (page_offset << 2)) >> 2;
++
++		SET_HOIE_ENTRY_LOW_DATA(start_at, 0);
++		SET_HOIE_ENTRY_HIGH_DATA(start_at, 0);
++		SET_HOIE_ENTRY_MODE_SELECT(start_at, 0);
++		SET_HOIE_ENTRY_ADDRESS(start_at, addr_value);
++		SET_HOIE_ENTRY_BYTE_MASK(start_at, 0xF);
++		SET_HOIE_ENTRY_IO_LOCK(start_at, 0);
++		SET_HOIE_ENTRY_WR_EN(start_at, 1);
++		SET_HOIE_ENTRY_RD_EN(start_at, 1);
++		SET_HOIE_ENTRY_RAW_RW(start_at, 0);
++		SET_HOIE_ENTRY_RAW(start_at, 0);
++		SET_HOIE_ENTRY_IO_DELAY(start_at, 0);
++	}
++	RTW_INFO("%s: (round << 9) + (PageOffset << 3) = %#08x\n",
++		 __func__, offset + (page_offset << 3));
++
++	start_at = staticFile + offset + (page_offset << 3);
++	/* add last command: 00 00 00 00 00 40 30 00,suggested by DD */
++	*(start_at) = 0;
++	*(start_at + 1) = 0;
++	*(start_at + 2) = 0;
++	*(start_at + 3) = 0;
++	*(start_at + 4) = 0;
++	*(start_at + 5) = 0x40;
++	*(start_at + 6) = 0x30;
++	*(start_at + 7) = 0;
++
++	return _TRUE;
++}
++
++/****************************************************************************
++Function: send Location of configuration file and other info for FW
++*****************************************************************************/
++static void rtl8723d_lps_poff_h2c_param(PADAPTER padapter, u8 tx_bndy, u16 len,
++					bool isDynamic)
++{
++	u8 lps_poff_param[H2C_LPS_POFF_PARAM_LEN] = {0};
++	u8 start_addr_l = 0, start_addr_h = 0;
++	u8 end_addr_l = 0, end_addr_h = 0;
++	u16 start_addr = 0, end_addr = 0;
++
++	if (len < 8)
++		return;
++	/*
++	set start address, The parameter is entrys. every page has 16 entrys
++	The Tx Descriptor is 40Byte which locate 5 entries
++	*/
++
++	start_addr = (tx_bndy << 4) + 5;
++	end_addr = start_addr + (len >> 3) - 1;
++
++	RTW_INFO("%s: start_addr = %#02X, end_addr= %#02X\n",
++		 __func__, start_addr, end_addr);
++
++	start_addr_l = (u8)start_addr;
++	start_addr_h = (u8)(start_addr >> 8);
++
++	end_addr_l = (u8)end_addr;
++	end_addr_h = (u8)(end_addr >> 8);
++
++	/*construct H2C Cmd*/
++	if (isDynamic)
++		SET_H2CCMD_LPS_POFF_PARAM_RDVLD(lps_poff_param, 0);
++	else
++		SET_H2CCMD_LPS_POFF_PARAM_RDVLD(lps_poff_param, 1);
++
++	SET_H2CCMD_LPS_POFF_PARAM_WRVLD(lps_poff_param, 1);
++	SET_H2CCMD_LPS_POFF_PARAM_STARTADDL(lps_poff_param, start_addr_l);
++	SET_H2CCMD_LPS_POFF_PARAM_STARTADDH(lps_poff_param, start_addr_h);
++	SET_H2CCMD_LPS_POFF_PARAM_ENDADDL(lps_poff_param, end_addr_l);
++	SET_H2CCMD_LPS_POFF_PARAM_ENDADDH(lps_poff_param, end_addr_h);
++
++	rtw_hal_fill_h2c_cmd(padapter, H2C_LPS_POFF_PARAM,
++			     H2C_LPS_POFF_PARAM_LEN, lps_poff_param);
++}
++
++/*************************************************************************
++Function: SET Location of Configuration File to FW
++**************************************************************************/
++static void rtl8723d_lps_poff_set_param(PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	lps_poff_info_t *plps_poff_info = pwrpriv->plps_poff_info;
++
++	u8 static_tx_bndy = 0;
++	u8 dynamic_tx_bndy = 0;
++	u16 static_len = 0, dynamic_len = 0;
++
++	static_tx_bndy = plps_poff_info->tx_bndy_static;
++	dynamic_tx_bndy = plps_poff_info->tx_bndy_dynamic;
++
++	dynamic_len = plps_poff_info->ConfLenForPTK +
++		      plps_poff_info->ConfLenForGTK;
++
++	if (ATOMIC_READ(&plps_poff_info->bSetPOFFParm) == _TRUE)
++		return;
++
++	/* download static configuration */
++	static_len = LPS_POFF_STATIC_FILE_LEN - TXDESC_SIZE;
++	rtl8723d_lps_poff_h2c_param(padapter, static_tx_bndy,
++				    static_len, _FALSE);
++
++	/* download dynamic configuration */
++	/* the length must be add more 8 Byte due to hard bug */
++	if (dynamic_len != 0) {
++		dynamic_len += 8;
++		rtl8723d_lps_poff_h2c_param(padapter, dynamic_tx_bndy,
++					    dynamic_len, _TRUE);
++	}
++
++	ATOMIC_SET(&plps_poff_info->bSetPOFFParm, _TRUE);
++}
++
++
++/****************************************************************************
++Function: change tx boundary
++*****************************************************************************/
++static void rtl8723d_lps_poff_set_tx_bndy(PADAPTER padapter, u8 tx_bndy)
++{
++	u32	numHQ = 0x10;
++	u32	numLQ = 0x10;
++	u32	numPubQ = 0;
++	u8	numNQ = 0;
++
++	u32	val32 = 0;
++	u8	val8  = 0;
++
++#ifdef CONFIG_PCI_HCI
++	numHQ = 0x8;
++	numLQ = 0x8;
++#endif
++	numPubQ = tx_bndy - numHQ - numLQ - numNQ - 1;
++	val8 = _NPQ(numNQ);
++	val32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
++
++	rtw_write8(padapter, REG_RQPN_NPQ, val8);
++	rtw_write32(padapter, REG_RQPN, val32);
++}
++
++/****************************************************************************
++Function: change tx boundary flow
++*****************************************************************************/
++static bool rtl8723d_lps_poff_tx_bndy_flow(PADAPTER padapter, bool enable)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct xmit_priv *pxmitpriv;
++	lps_poff_info_t *plps_poff_info = pwrpriv->plps_poff_info;
++	u8	tx_bndy = 0, tx_bndy_new = 0, count = 0, queue_pending = _FALSE;
++	u8	val8 = 0;
++	u16	val16 = 0;
++	u32	val32 = 0;
++
++	pxmitpriv = &padapter->xmitpriv;
++	rtw_hal_get_def_var(padapter, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_bndy);
++
++	RTW_INFO("%s: tx_bndy: %#X, tx_bndy_static: %#X\n",
++		 __func__, tx_bndy, plps_poff_info->tx_bndy_static);
++
++	if (enable)
++		tx_bndy_new = plps_poff_info->tx_bndy_static + 1;
++	else
++		tx_bndy_new = tx_bndy;
++
++	ATOMIC_SET(&plps_poff_info->bTxBoundInProgress, _TRUE);
++
++	/* stop os layer TX*/
++	rtw_mi_netif_stop_queue(padapter);
++
++	val16 = rtw_read16(padapter, REG_TXPKT_EMPTY);
++
++	/* stop tx process and wait tx empty */
++	while ((val16 & 0x05FF) != 0x05FF) {
++		rtw_mdelay_os(10);
++		val16 = rtw_read16(padapter, REG_TXPKT_EMPTY);
++
++		count++;
++		if (count >= 100) {
++			val16 = rtw_read16(padapter, REG_TXPKT_EMPTY);
++			RTW_INFO("%s, txpkt_empty: %#04x\n", __func__, val16);
++			val8 = rtw_read8(padapter, REG_CPU_MGQ_INFORMATION);
++			RTW_INFO("%s, REG_CPU_MGQ_INFORMATION: %#02x\n",
++				 __func__, val8);
++			RTW_INFO("%s, wait for tx empty timeout!!\n", __func__);
++			ATOMIC_SET(&plps_poff_info->bTxBoundInProgress, _FALSE);
++			rtw_mi_netif_wake_queue(padapter);
++			return _FALSE;
++		}
++	}
++
++	/* change tx boundary*/
++	rtl8723d_lps_poff_set_tx_bndy(padapter, tx_bndy_new);
++
++	/* set free tail */
++	val32 = rtw_read32(padapter, REG_FWHW_TXQ_CTRL);
++	val32 |= BIT20;
++	rtw_write32(padapter, REG_FWHW_TXQ_CTRL, val32);
++	rtw_write8(padapter, REG_BCNQ_BDNY, tx_bndy_new);
++
++	RTW_INFO("%s: free tail = %#x after\n", __func__,
++		 rtw_read8(padapter, REG_FW_FREE_TAIL_8723D));
++
++	/* set bcn head */
++	val32 = rtw_read32(padapter, REG_FWHW_TXQ_CTRL);
++	val32 &= ~BIT20;
++	rtw_write32(padapter, REG_FWHW_TXQ_CTRL, val32);
++	rtw_write8(padapter, REG_BCNQ_BDNY, tx_bndy);
++
++	/* reinit LLT */
++	rtl8723d_InitLLTTable(padapter);
++
++	/* clear 0x210 ??*/
++	val32 = rtw_read32(padapter, REG_TXDMA_STATUS);
++
++	if (val32 != 0) {
++		RTW_INFO("%s: REG_TXDMA_STATUS: %#08x\n", __func__, val32);
++		rtw_write32(padapter, REG_TXDMA_STATUS, val32);
++	}
++
++	ATOMIC_SET(&plps_poff_info->bTxBoundInProgress, _FALSE);
++
++
++	/* restart tx */
++
++	rtw_mi_netif_wake_queue(padapter);
++
++	return _TRUE;
++}
++
++/****************************************************************************
++Function: Append extra bytes for dynamic confiure file
++	  Add one entry to fix hw bug,
++	  list command: 00 00 00 00 00 40 30 00, suggested by DD
++*****************************************************************************/
++static u8 rtl8723d_lps_poff_append_extra_info(PADAPTER padapter, u32 len)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	lps_poff_info_t *plps_poff_info = pwrpriv->plps_poff_info;
++	u32 data_offset = len + plps_poff_info->ConfFileOffset;
++
++	*(plps_poff_info->pDynamicFile + (data_offset)) = 0x00;
++	*(plps_poff_info->pDynamicFile + (data_offset + 1)) = 0x00;
++	*(plps_poff_info->pDynamicFile + (data_offset + 2)) = 0x00;
++	*(plps_poff_info->pDynamicFile + (data_offset + 3)) = 0x00;
++	*(plps_poff_info->pDynamicFile + (data_offset + 4)) = 0x00;
++	*(plps_poff_info->pDynamicFile + (data_offset + 5)) = 0x40;
++	*(plps_poff_info->pDynamicFile + (data_offset + 6)) = 0x30;
++	*(plps_poff_info->pDynamicFile + (data_offset + 7)) = 0x00;
++	return 8;
++}
++
++/****************************************************************************
++Function: xmit config file to write port.
++*****************************************************************************/
++static void rtl8723d_lps_poff_send_config_frame(PADAPTER padapter,
++		u8 *pFile, u32 len)
++{
++	struct xmit_frame	*pcmdframe = NULL;
++	struct pkt_attrib	*pattrib;
++	struct xmit_priv	*pxmitpriv;
++	int i = 0;
++
++	pxmitpriv = &padapter->xmitpriv;
++	pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv);
++
++	if (pcmdframe == NULL)
++		RTW_INFO("%s: alloc cmdframe fail\n", __func__);
++
++	_rtw_memcpy(pcmdframe->buf_addr, pFile, len);
++
++	pattrib = &pcmdframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++	pattrib->qsel = QSLT_BEACON;
++	pattrib->pktlen = len - TXDESC_OFFSET;
++	pattrib->last_txcmdsz = len - TXDESC_OFFSET;
++
++	RTW_INFO("%s, len: %d, MAX_CMDBUF_SZ: %d\n", __func__, len,
++		 MAX_CMDBUF_SZ);
++#ifdef CONFIG_PCI_HCI
++	dump_mgntframe(padapter, pcmdframe);
++#else
++	dump_mgntframe_and_wait(padapter, pcmdframe, 100);
++#endif
++
++}
++
++/****************************************************************************
++Function: download config file flow
++*****************************************************************************/
++static void rtl8723d_lps_poff_send_config_file(PADAPTER padapter,
++		u8 *pFile, u8 loc, u32 len)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	bool bRecover = _FALSE, bcn_valid = _FALSE;
++	u8 DLBcnCount = 0, val8 = 0, tx_bndy = 0;
++	u32 poll = 0;
++	u8 RegFwHwTxQCtrl;
++	rtw_hal_get_def_var(padapter,
++			    HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_bndy);
++
++	/* set 0x100[8]=1 for SW beacon */
++	val8 = rtw_read8(padapter, REG_CR + 1);
++	val8 |= BIT(0);
++	rtw_write8(padapter,  REG_CR + 1, val8);
++
++	/*set 0x422[6]=0 to disable beacon DMA pass to MACTx*/
++	RegFwHwTxQCtrl = rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2);
++	if (RegFwHwTxQCtrl & BIT(6))
++		bRecover = _TRUE;
++
++	RegFwHwTxQCtrl &= ~BIT(6);
++
++	rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, RegFwHwTxQCtrl);
++
++	/* Clear beacon valid check bit. */
++	rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
++	rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
++
++	/* set 0x209[7:0] beacon queue head page to start download location */
++	rtw_write8(padapter, REG_TDECTRL_8723D + 1, loc);
++
++	DLBcnCount = 0;
++	poll = 0;
++
++	do {
++		rtl8723d_lps_poff_send_config_frame(padapter, pFile, len);
++		DLBcnCount++;
++		do {
++			rtw_mdelay_os(10);
++			/*check rsvd page download OK.*/
++			rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID,
++					  (u8 *)(&bcn_valid));
++			poll++;
++		} while (!bcn_valid && (poll % 10) != 0
++			 && !RTW_CANNOT_RUN(padapter));
++	} while (!bcn_valid && DLBcnCount <= 100 && !RTW_CANNOT_RUN(padapter));
++
++	if (!bcn_valid)
++		RTW_INFO(ADPT_FMT": 1 DL RSVD page failed! DLBcnCount:%u, poll:%u\n",
++			 ADPT_ARG(padapter), DLBcnCount, poll);
++	else
++		RTW_INFO(ADPT_FMT": 1 DL RSVD page success! DLBcnCount:%u, poll:%u\n",
++			 ADPT_ARG(padapter), DLBcnCount, poll);
++
++	/*restore bcn operation*/
++	rtw_write8(padapter, REG_TDECTRL_8723D + 1, tx_bndy);
++
++	/*restore 0x422[6]=1 for normal bcn*/
++	if (bRecover) {
++		RegFwHwTxQCtrl |= BIT(6);
++		rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, RegFwHwTxQCtrl);
++	}
++
++	/*restore 0x100[8]=0 for SW beacon*/
++	/* Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
++#ifndef CONFIG_PCI_HCI
++	val8 = rtw_read8(padapter, REG_CR + 1);
++	val8 &= ~BIT(0);
++	rtw_write8(padapter, REG_CR + 1, val8);
++#endif
++}
++
++/****************************************************************************
++Function: Prepare Confiure File
++*****************************************************************************/
++static void rtl8723d_lps_poff_dl_config_file(PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	lps_poff_info_t *plps_poff_info = pwrpriv->plps_poff_info;
++	u8 count = 0, append_len = 0;
++	u32 offset = 0, static_file_len = 0, dynamic_file_len = 0;
++	int i = 0, j = 0;
++
++	offset = plps_poff_info->ConfFileOffset;
++
++	static_file_len = LPS_POFF_STATIC_FILE_LEN - offset;
++
++	dynamic_file_len =
++		plps_poff_info->ConfLenForPTK + plps_poff_info->ConfLenForGTK;
++
++	RTW_INFO("%s: static_file_len: %d dynamic_file_len: %d, offset: %d\n",
++		 __func__, static_file_len, dynamic_file_len, offset);
++
++	/*static file*/
++	rtl8723d_lps_poff_send_config_file(padapter,
++					   plps_poff_info->pStaticFile + offset,
++					   plps_poff_info->tx_bndy_static,
++					   static_file_len);
++
++	/*dynamic file*/
++	if (dynamic_file_len != 0) {
++		dynamic_file_len += TXDESC_SIZE - offset;
++
++		append_len =
++			rtl8723d_lps_poff_append_extra_info(padapter,
++					dynamic_file_len);
++		dynamic_file_len += append_len;
++		rtl8723d_lps_poff_send_config_file(padapter,
++				   plps_poff_info->pDynamicFile + offset,
++					   plps_poff_info->tx_bndy_dynamic,
++						   dynamic_file_len);
++	}
++}
++
++static u8 rtl8723d_lps_poff_set_dynamic_file(u8 *pFile, u32 type, u32 wdata)
++{
++	SET_HOIE_ENTRY_LOW_DATA(pFile, (u16)wdata);
++	SET_HOIE_ENTRY_HIGH_DATA(pFile, (u16)(wdata >> 16));
++	SET_HOIE_ENTRY_MODE_SELECT(pFile, 0);
++	SET_HOIE_ENTRY_ADDRESS(pFile, (type >> 2));
++	SET_HOIE_ENTRY_BYTE_MASK(pFile, 0xF);
++	SET_HOIE_ENTRY_IO_LOCK(pFile, 0);
++	SET_HOIE_ENTRY_WR_EN(pFile, 1);
++	SET_HOIE_ENTRY_RD_EN(pFile, 0);
++	SET_HOIE_ENTRY_RAW_RW(pFile, 0);
++	SET_HOIE_ENTRY_RAW(pFile, 0);
++	SET_HOIE_ENTRY_IO_DELAY(pFile, 0);
++
++	return 8;
++}
++
++static void rtl8723d_lps_poff_dynamic_file(PADAPTER padapter, u8 index, u8 isGK)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	lps_poff_info_t *plps_poff_info = pwrpriv->plps_poff_info;
++	u8 *ptkfile = NULL;
++	u8 ret = 0;
++	u32 tgt_cmd = 0, tgt_wdata = 0;
++	int i = 0, j = 0;
++
++	for (i = 0 ; i < CAM_CONTENT_COUNT; i++) {
++		if (!isGK)
++			ptkfile = plps_poff_info->pDynamicFile +
++				  plps_poff_info->ConfLenForPTK + TXDESC_SIZE;
++		else
++			ptkfile = plps_poff_info->pDynamicFile +
++				  plps_poff_info->ConfLenForPTK +
++				  plps_poff_info->ConfLenForGTK + TXDESC_SIZE;
++
++		tgt_cmd = i + (CAM_CONTENT_COUNT * index);
++		tgt_cmd = tgt_cmd | CAM_POLLINIG | CAM_WRITE;
++
++		switch (i) {
++		case 0:
++			tgt_wdata = dvobj->cam_cache[index].ctrl |
++				    dvobj->cam_cache[index].mac[0] << 16 |
++				    dvobj->cam_cache[index].mac[1] << 24;
++			break;
++		case 1:
++			tgt_wdata = dvobj->cam_cache[index].mac[2] |
++				    dvobj->cam_cache[index].mac[3] << 8 |
++				    dvobj->cam_cache[index].mac[4] << 16 |
++				    dvobj->cam_cache[index].mac[5] << 24;
++			break;
++		default:
++			j = (i - 2) << 2;
++			tgt_wdata =
++				dvobj->cam_cache[index].key[j + 3] << 24 |
++				dvobj->cam_cache[index].key[j + 2] << 16 |
++				dvobj->cam_cache[index].key[j + 1] << 8 |
++				dvobj->cam_cache[index].key[j];
++			break;
++		}
++
++		ret = rtl8723d_lps_poff_set_dynamic_file(ptkfile,
++				REG_CAMWRITE, tgt_wdata);
++
++		if (!isGK) {
++			plps_poff_info->ConfLenForPTK += ret;
++
++			ptkfile = plps_poff_info->pDynamicFile +
++				  plps_poff_info->ConfLenForPTK + TXDESC_SIZE;
++		} else {
++			plps_poff_info->ConfLenForGTK += ret;
++			ptkfile = plps_poff_info->pDynamicFile +
++				  plps_poff_info->ConfLenForPTK +
++				  plps_poff_info->ConfLenForGTK + TXDESC_SIZE;
++		}
++
++		ret = rtl8723d_lps_poff_set_dynamic_file(ptkfile,
++				REG_CAMCMD, tgt_cmd);
++
++		if (!isGK)
++			plps_poff_info->ConfLenForPTK += ret;
++		else
++			plps_poff_info->ConfLenForGTK += ret;
++
++#if 0
++		RTW_INFO("%s: tgt_wdata: %#08x\n", __func__, tgt_wdata);
++#endif
++	}
++}
++
++static void rtl8723d_lps_poff_sec_cam_opt(PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	lps_poff_info_t *plps_poff_info = pwrpriv->plps_poff_info;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	int i = 0;
++	u8 isValid = 0, isGK = 0, index = 0, key_id = 0xff, gk_start = 0xff;
++	u16 val16 = 0, len = 0;
++
++	/*Using cam cache to create config file for FW use.*/
++	/*1- deail with pairwise key*/
++
++	for (i = 0 ; i < cam_ctl->num ; i++) {
++
++		val16 = dvobj->cam_cache[i].ctrl;
++		isValid = (val16 >> 15) & 0x01;
++		isGK = (val16 >> 6) & 0x01;
++
++		if (isValid && !isGK) {
++			rtl8723d_lps_poff_dynamic_file(padapter, i, _FALSE);
++			RTW_INFO("%s: id: %2u, kid: %3u, ctrl: %#04x, "MAC_FMT""KEY_FMT"\n",
++				 __func__, i, (dvobj->cam_cache[i].ctrl) & 0x03,
++				 dvobj->cam_cache[i].ctrl,
++				 MAC_ARG(dvobj->cam_cache[i].mac),
++				 KEY_ARG(dvobj->cam_cache[i].key));
++		} else if (isGK) {
++			key_id = dvobj->cam_cache[i].ctrl & 0x03;
++			if (key_id == pmlmeinfo->key_index)
++				gk_start = i;
++			RTW_INFO("%s: GK_start at %d\n", __func__, gk_start);
++			RTW_INFO("%s: id: %2u, kid: %3u, ctrl: %#04x, "MAC_FMT""KEY_FMT"\n",
++				 __func__, i, key_id, dvobj->cam_cache[i].ctrl,
++				 MAC_ARG(dvobj->cam_cache[i].mac),
++				 KEY_ARG(dvobj->cam_cache[i].key));
++		}
++	}
++
++	/*2- deail with group key*/
++	rtl8723d_lps_poff_dynamic_file(padapter, gk_start, _TRUE);
++
++	RTW_INFO("%s: ConfLenForPTK: %d, ConfLenForGTK: %d\n", __func__,
++		 plps_poff_info->ConfLenForPTK, plps_poff_info->ConfLenForGTK);
++}
++
++/****************************************************************************
++Function: Prepare enter LPS partial off status.
++change tx boundary, download configuration file if necessary and send info to FW
++*****************************************************************************/
++static bool rtl8723d_prepare_for_enter_poff(PADAPTER padapter, bool bEnterLPS)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	lps_poff_info_t *plps_poff_info = pwrpriv->plps_poff_info;
++	bool ret = _FALSE;
++	u8 i = 0, cam_cache_num = 0;
++
++	for (i = 0 ; i < cam_ctl->num; i++) {
++		if (dvobj->cam_cache[i].ctrl != 0)
++			cam_cache_num++;
++	}
++
++	ret = rtl8723d_lps_poff_tx_bndy_flow(padapter, bEnterLPS);
++
++	if (ret == _TRUE) {
++		if (cam_cache_num > 0) {
++			rtl8723d_lps_poff_sec_cam_opt(padapter);
++		} else {
++			plps_poff_info->ConfLenForPTK = 0;
++			plps_poff_info->ConfLenForGTK = 0;
++		}
++		rtl8723d_lps_poff_dl_config_file(padapter);
++		rtl8723d_lps_poff_set_param(padapter);
++	}
++	return ret;
++}
++
++/*************************************************************************
++Function: SET H2C To Enable Partial Off
++**************************************************************************/
++void rtl8723d_lps_poff_h2c_ctrl(PADAPTER padapter, u8 en)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++	lps_poff_info_t *plps_poff_info = pwrpriv->plps_poff_info;
++	u8 param = 0;
++
++	if (pregistrypriv->wifi_spec == 1)
++		return;
++
++	if (plps_poff_info->bEn == _FALSE)
++		return;
++
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
++		if (en) {
++			RTW_INFO("%s: enable case\n", __func__);
++			SET_H2CCMD_LPS_POFF_CTRL_EN(&param, 1);
++		} else {
++			RTW_INFO("%s: disable case\n", __func__);
++			ATOMIC_SET(&plps_poff_info->bSetPOFFParm, _FALSE);
++			SET_H2CCMD_LPS_POFF_CTRL_EN(&param, 0);
++		}
++		rtw_hal_fill_h2c_cmd(padapter, H2C_LPS_POFF_CTRL,
++				     H2C_LPS_POFF_CTRL_LEN, &param);
++	}
++}
++
++/*************************************************************************
++Function: The operation to Enter or Leave FWLPS 32K when partial off enable
++**************************************************************************/
++void rtl8723d_lps_poff_set_ps_mode(PADAPTER padapter, bool bEnterLPS)
++{
++
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	lps_poff_info_t *plps_poff_info = pwrpriv->plps_poff_info;
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++	bool res = _FALSE;
++
++	if (pregistrypriv->wifi_spec == 1)
++		return;
++
++	if (plps_poff_info->bEn) {
++
++		plps_poff_info->ConfLenForPTK = 0;
++		plps_poff_info->ConfLenForGTK = 0;
++
++		if (bEnterLPS) {
++			res = rtl8723d_prepare_for_enter_poff(padapter,
++							      bEnterLPS);
++			ATOMIC_SET(&plps_poff_info->bEnterPOFF, res);
++		} else
++			rtl8723d_lps_poff_tx_bndy_flow(padapter, bEnterLPS);
++	}
++}
++
++/*************************************************************************
++Function: Get LPS-POFF Enter Status
++**************************************************************************/
++bool rtl8723d_lps_poff_get_status(PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	lps_poff_info_t *plps_poff_info = pwrpriv->plps_poff_info;
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++
++	if (pregistrypriv->wifi_spec == 1) {
++		RTW_INFO("%s: wifi_spec is enable\n", __func__);
++		return _FALSE;
++	}
++
++	if (plps_poff_info->bEn == _FALSE) {
++		RTW_INFO("%s: POFF is disable\n", __func__);
++		return _FALSE;
++	}
++
++	return ATOMIC_READ(&plps_poff_info->bEnterPOFF);
++}
++
++/*************************************************************************
++Function: Get LPS-POFF change tx bndy status
++**************************************************************************/
++bool rtl8723d_lps_poff_get_txbndy_status(PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	lps_poff_info_t *plps_poff_info = pwrpriv->plps_poff_info;
++
++	return ATOMIC_READ(&plps_poff_info->bTxBoundInProgress);
++}
++
++/*************************************************************************
++Function: Get LPS-POFF initial
++**************************************************************************/
++void rtl8723d_lps_poff_init(PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++	lps_poff_info_t *lps_poff_info;
++	u8 tx_bndy = 0, page_size = 0, total_page = 0, page_num = 0;
++	u8 val = 0;
++
++	if (pregistrypriv->wifi_spec == 1)
++		return;
++
++	if (is_primary_adapter(padapter)) {
++
++		rtw_hal_get_def_var(padapter,
++				    HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&val);
++		tx_bndy = val;
++
++		rtw_hal_get_def_var(padapter,
++				    HAL_DEF_TX_PAGE_SIZE, (u8 *)&val);
++		page_size = val;
++
++		total_page = PageNum(LPS_POFF_STATIC_FILE_LEN, page_size) +
++			     PageNum(LPS_POFF_DYNAMIC_FILE_LEN, page_size);
++
++		lps_poff_info =
++			(lps_poff_info_t *)rtw_zmalloc(sizeof(lps_poff_info_t));
++
++		if (lps_poff_info != NULL) {
++			pwrpriv->plps_poff_info = lps_poff_info;
++
++			lps_poff_info->pStaticFile =
++				(u8 *)rtw_zmalloc(LPS_POFF_STATIC_FILE_LEN);
++			if (lps_poff_info->pStaticFile == NULL) {
++				RTW_INFO("%s: alloc pStaticFile fail\n",
++					 __func__);
++				goto alloc_static_conf_file_fail;
++			} else {
++				pwrpriv->plps_poff_info->pStaticFile =
++					lps_poff_info->pStaticFile;
++			}
++
++			lps_poff_info->pDynamicFile =
++				(u8 *)rtw_zmalloc(LPS_POFF_DYNAMIC_FILE_LEN);
++			if (lps_poff_info->pDynamicFile == NULL) {
++				RTW_INFO("%s: alloc pDynamicFile fail\n",
++					 __func__);
++				goto alloc_dynamic_conf_file_fail;
++			} else {
++				pwrpriv->plps_poff_info->pDynamicFile =
++					lps_poff_info->pDynamicFile;
++			}
++
++			pwrpriv->plps_poff_info->bEn = _TRUE;
++			ATOMIC_SET(&pwrpriv->plps_poff_info->bEnterPOFF,
++				   _FALSE);
++			ATOMIC_SET(&pwrpriv->plps_poff_info->bSetPOFFParm,
++				   _FALSE);
++			ATOMIC_SET(&pwrpriv->plps_poff_info->bTxBoundInProgress,
++				   _FALSE);
++#ifdef CONFIG_PCI_HCI
++			pwrpriv->plps_poff_info->ConfFileOffset = 40;
++#else
++			pwrpriv->plps_poff_info->ConfFileOffset = 0;
++#endif
++			pwrpriv->plps_poff_info->tx_bndy_static =
++				tx_bndy - total_page;
++			page_num = PageNum(LPS_POFF_DYNAMIC_FILE_LEN,
++					   page_size);
++			pwrpriv->plps_poff_info->tx_bndy_dynamic =
++				tx_bndy - page_num;
++			/*
++			   construct static DLConfiguration File
++			*/
++			hal_construct_poff_static_file(padapter);
++			goto exit;
++		} else {
++			RTW_INFO("%s: alloc lps_poff_info fail\n",  __func__);
++			goto exit;
++		}
++	}
++
++alloc_dynamic_conf_file_fail:
++	rtw_mfree((u8 *)pwrpriv->plps_poff_info->pStaticFile,
++		  LPS_POFF_STATIC_FILE_LEN);
++	pwrpriv->plps_poff_info->pStaticFile = NULL;
++alloc_static_conf_file_fail:
++	rtw_mfree((u8 *)pwrpriv->plps_poff_info, sizeof(lps_poff_info_t));
++	pwrpriv->plps_poff_info = NULL;
++exit:
++	return;
++}
++
++/*************************************************************************
++Function: Get LPS-POFF de-initial
++**************************************************************************/
++void rtl8723d_lps_poff_deinit(PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	lps_poff_info_t *plps_poff_info = pwrpriv->plps_poff_info;
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++
++	if (pregistrypriv->wifi_spec == 1)
++		return;
++
++	if (is_primary_adapter(padapter)) {
++		if (plps_poff_info->pDynamicFile != NULL) {
++			rtw_mfree((u8 *)plps_poff_info->pDynamicFile,
++				  LPS_POFF_DYNAMIC_FILE_LEN);
++			plps_poff_info->pDynamicFile = NULL;
++		}
++		if (plps_poff_info->pStaticFile != NULL) {
++			rtw_mfree((u8 *)plps_poff_info->pStaticFile,
++				  LPS_POFF_STATIC_FILE_LEN);
++			plps_poff_info->pStaticFile = NULL;
++		}
++		if (plps_poff_info != NULL) {
++			rtw_mfree((u8 *)plps_poff_info,
++				  sizeof(lps_poff_info_t));
++			plps_poff_info = NULL;
++		}
++	}
++
++}
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_phycfg.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_phycfg.c
+new file mode 100644
+index 000000000..a23aea0f8
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_phycfg.c
+@@ -0,0 +1,1193 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTL8723D_PHYCFG_C_
++
++#include <rtl8723d_hal.h>
++
++
++/*---------------------------Define Local Constant---------------------------*/
++/* Channel switch:The size of command tables for switch channel*/
++#define MAX_PRECMD_CNT 16
++#define MAX_RFDEPENDCMD_CNT 16
++#define MAX_POSTCMD_CNT 16
++
++#define MAX_DOZE_WAITING_TIMES_9x 64
++
++/*---------------------------Define Local Constant---------------------------*/
++
++
++/*------------------------Define global variable-----------------------------*/
++
++/*------------------------Define local variable------------------------------*/
++
++
++/*--------------------Define export function prototype-----------------------*/
++/* Please refer to header file
++ *--------------------Define export function prototype-----------------------*/
++
++/*----------------------------Function Body----------------------------------*/
++/*
++ * 1. BB register R/W API
++ *   */
++
++/**
++* Function:	phy_CalculateBitShift
++*
++* OverView:	Get shifted position of the BitMask
++*
++* Input:
++*			u32		BitMask,
++*
++* Output:	none
++* Return:		u32		Return the shift bit bit position of the mask
++*/
++static	u32
++phy_CalculateBitShift(
++	u32 BitMask
++)
++{
++	u32 i;
++
++	for (i = 0; i <= 31; i++) {
++		if (((BitMask >> i) &  0x1) == 1)
++			break;
++	}
++
++	return i;
++}
++
++
++/**
++* Function:	PHY_QueryBBReg
++*
++* OverView:	Read "sepcific bits" from BB register
++*
++* Input:
++*			PADAPTER		Adapter,
++*			u32			RegAddr,
++*			u32			BitMask
++*
++* Output:	None
++* Return:		u32			Data
++* Note:		This function is equal to "GetRegSetting" in PHY programming guide
++*/
++u32
++PHY_QueryBBReg_8723D(
++		PADAPTER	Adapter,
++		u32		RegAddr,
++		u32		BitMask
++)
++{
++	u32	ReturnValue = 0, OriginalValue, BitShift;
++	u16	BBWaitCounter = 0;
++
++#if (DISABLE_BB_RF == 1)
++	return 0;
++#endif
++
++
++	OriginalValue = rtw_read32(Adapter, RegAddr);
++	BitShift = phy_CalculateBitShift(BitMask);
++	ReturnValue = (OriginalValue & BitMask) >> BitShift;
++
++	return ReturnValue;
++
++}
++
++
++/**
++* Function:	PHY_SetBBReg
++*
++* OverView:	Write "Specific bits" to BB register (page 8~)
++*
++* Input:
++*			PADAPTER		Adapter,
++*			u32			RegAddr,
++*			u32			BitMask
++*
++*			u32			Data
++*
++*
++* Output:	None
++* Return:		None
++* Note:		This function is equal to "PutRegSetting" in PHY programming guide
++*/
++
++void
++PHY_SetBBReg_8723D(
++		PADAPTER	Adapter,
++		u32		RegAddr,
++		u32		BitMask,
++		u32		Data
++)
++{
++	HAL_DATA_TYPE	*pHalData		= GET_HAL_DATA(Adapter);
++	/* u16			BBWaitCounter	= 0; */
++	u32			OriginalValue, BitShift;
++
++#if (DISABLE_BB_RF == 1)
++	return;
++#endif
++
++
++	if (BitMask != bMaskDWord) { /* if not "double word" write */
++		OriginalValue = rtw_read32(Adapter, RegAddr);
++		BitShift = phy_CalculateBitShift(BitMask);
++		Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
++	}
++
++	rtw_write32(Adapter, RegAddr, Data);
++
++}
++
++
++/*
++ * 2. RF register R/W API
++ *   */
++static	u32
++phy_RFSerialRead_8723D(
++		PADAPTER			Adapter,
++		enum rf_path			eRFPath,
++		u32				Offset
++)
++{
++	u32						retValue = 0;
++	HAL_DATA_TYPE				*pHalData = GET_HAL_DATA(Adapter);
++	BB_REGISTER_DEFINITION_T	*pPhyReg = &pHalData->PHYRegDef[eRFPath];
++	u32						NewOffset;
++	u32						tmplong, tmplong2;
++	u8					RfPiEnable = 0;
++	u32						MaskforPhySet = 0;
++	int i = 0;
++
++	_enter_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
++	/* */
++	/* Make sure RF register offset is correct */
++	/* */
++	Offset &= 0xff;
++
++	NewOffset = Offset;
++
++	if (eRFPath == RF_PATH_A) {
++		tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
++		tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge;	/* T65 RF */
++		phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
++	} else {
++		tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord);
++		tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge;	/* T65 RF */
++		phy_set_bb_reg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
++	}
++
++	tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
++	phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
++	phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
++
++	rtw_udelay_os(10);
++
++	for (i = 0; i < 2; i++)
++		rtw_udelay_os(MAX_STALL_TIME);
++	rtw_udelay_os(10);
++
++	if (eRFPath == RF_PATH_A)
++		RfPiEnable = (u8)phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT(8));
++	else if (eRFPath == RF_PATH_B)
++		RfPiEnable = (u8)phy_query_bb_reg(Adapter, rFPGA0_XB_HSSIParameter1 | MaskforPhySet, BIT(8));
++
++	if (RfPiEnable) {
++		/* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
++		retValue = phy_query_bb_reg(Adapter, pPhyReg->rfLSSIReadBackPi | MaskforPhySet, bLSSIReadBackData);
++
++		/* RT_DISP(FINIT, INIT_RF, ("Readback from RF-PI : 0x%x\n", retValue)); */
++	} else {
++		/* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
++		retValue = phy_query_bb_reg(Adapter, pPhyReg->rfLSSIReadBack | MaskforPhySet, bLSSIReadBackData);
++
++		/* RT_DISP(FINIT, INIT_RF,("Readback from RF-SI : 0x%x\n", retValue)); */
++	}
++	_exit_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
++	return retValue;
++
++}
++
++/**
++* Function:	phy_RFSerialWrite_8723D
++*
++* OverView:	Write data to RF register (page 8~)
++*
++* Input:
++*			PADAPTER		Adapter,
++			enum rf_path		eRFPath,
++*			u32			Offset,
++*			u32			Data
++*
++*
++* Output:	None
++* Return:		None
++* Note:		Threre are three types of serial operations:
++*			1. Software serial write
++*			2. Hardware LSSI-Low Speed Serial Interface
++*			3. Hardware HSSI-High speed
++*			serial write. Driver need to implement (1) and (2).
++*			This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
++ *
++ * Note:		  For RF8256 only
++ *			 The total count of RTL8256(Zebra4) register is around 36 bit it only employs
++ *			 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
++ *			 to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
++ *			 programming guide" for more details.
++ *			 Thus, we define a sub-finction for RTL8526 register address conversion
++ *		       ===========================================================
++ *			 Register Mode		RegCTL[1]		RegCTL[0]		Note
++ *								(Reg00[12])		(Reg00[10])
++ *		       ===========================================================
++ *			 Reg_Mode0				0				x			Reg 0 ~15(0x0 ~ 0xf)
++ *		       ------------------------------------------------------------------
++ *			 Reg_Mode1				1				0			Reg 16 ~30(0x1 ~ 0xf)
++ *		       ------------------------------------------------------------------
++ *			 Reg_Mode2				1				1			Reg 31 ~ 45(0x1 ~ 0xf)
++ *		       ------------------------------------------------------------------
++ *
++ *	2008/09/02	MH	Add 92S RF definition
++ *
++ *
++ *
++*/
++static	void
++phy_RFSerialWrite_8723D(
++		PADAPTER			Adapter,
++		enum rf_path			eRFPath,
++		u32				Offset,
++		u32				Data
++)
++{
++	u32						DataAndAddr = 0;
++	HAL_DATA_TYPE				*pHalData = GET_HAL_DATA(Adapter);
++	BB_REGISTER_DEFINITION_T	*pPhyReg = &pHalData->PHYRegDef[eRFPath];
++	u32						NewOffset;
++
++	Offset &= 0xff;
++
++	/* */
++	/* Shadow Update */
++	/* */
++	/* PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data); */
++
++	/* */
++	/* Switch page for 8256 RF IC */
++	/* */
++	NewOffset = Offset;
++
++	/* */
++	/* Put write addr in [5:0]  and write data in [31:16] */
++	/* */
++	/* DataAndAddr = (Data<<16) | (NewOffset&0x3f); */
++	DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff;	/* T65 RF */
++
++	/* */
++	/* Write Operation */
++	/* */
++	phy_set_bb_reg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
++	/* RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); */
++
++}
++
++
++/**
++* Function:	PHY_QueryRFReg
++*
++* OverView:	Query "Specific bits" to RF register (page 8~)
++*
++* Input:
++*			PADAPTER		Adapter,
++			enum rf_path			eRFPath,
++*			u32			RegAddr,
++*			u32			BitMask
++*
++*
++* Output:	None
++* Return:		u32			Readback value
++* Note:		This function is equal to "GetRFRegSetting" in PHY programming guide
++*/
++u32
++PHY_QueryRFReg_8723D(
++		PADAPTER			Adapter,
++		enum rf_path			eRFPath,
++		u32				RegAddr,
++		u32				BitMask
++)
++{
++	u32 Original_Value, Readback_Value, BitShift;
++
++#if (DISABLE_BB_RF == 1)
++	return 0;
++#endif
++
++	Original_Value = phy_RFSerialRead_8723D(Adapter, eRFPath, RegAddr);
++
++	BitShift =  phy_CalculateBitShift(BitMask);
++	Readback_Value = (Original_Value & BitMask) >> BitShift;
++
++	return Readback_Value;
++}
++
++/**
++* Function:	PHY_SetRFReg
++*
++* OverView:	Write "Specific bits" to RF register (page 8~)
++*
++* Input:
++*			PADAPTER		Adapter,
++*			RF_PATH			eRFPath,
++*			u32			RegAddr,
++*			u32			BitMask
++*
++*			u32			Data
++*
++*
++* Output:	None
++* Return:		None
++* Note:		This function is equal to "PutRFRegSetting" in PHY programming guide
++*/
++void
++PHY_SetRFReg_8723D(
++		PADAPTER			Adapter,
++		enum rf_path			eRFPath,
++		u32				RegAddr,
++		u32				BitMask,
++		u32				Data
++)
++{
++	u32		Original_Value, BitShift;
++
++#if (DISABLE_BB_RF == 1)
++	return;
++#endif
++
++	/* RF data is 12 bits only */
++	if (BitMask != bRFRegOffsetMask) {
++		Original_Value = phy_RFSerialRead_8723D(Adapter, eRFPath, RegAddr);
++		BitShift =  phy_CalculateBitShift(BitMask);
++		Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
++	}
++
++	phy_RFSerialWrite_8723D(Adapter, eRFPath, RegAddr, Data);
++}
++
++
++/*
++ * 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
++ *   */
++
++
++/*-----------------------------------------------------------------------------
++ * Function:    PHY_MACConfig8192C
++ *
++ * Overview:	Condig MAC by header file or parameter file.
++ *
++ * Input:       NONE
++ *
++ * Output:      NONE
++ *
++ * Return:      NONE
++ *
++ * Revised History:
++ *  When		Who		Remark
++ *  08/12/2008	MHC		Create Version 0.
++ *
++ *---------------------------------------------------------------------------*/
++s32 PHY_MACConfig8723D(PADAPTER Adapter)
++{
++	int		rtStatus = _SUCCESS;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++
++	/* */
++	/* Config MAC */
++	/* */
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++	rtStatus = phy_ConfigMACWithParaFile(Adapter, PHY_FILE_MAC_REG);
++	if (rtStatus == _FAIL)
++#endif
++	{
++#ifdef CONFIG_EMBEDDED_FWIMG
++		odm_config_mac_with_header_file(&pHalData->odmpriv);
++		rtStatus = _SUCCESS;
++#endif/* CONFIG_EMBEDDED_FWIMG */
++	}
++
++	return rtStatus;
++}
++
++/**
++* Function:	phy_InitBBRFRegisterDefinition
++*
++* OverView:	Initialize Register definition offset for Radio Path A/B/C/D
++*
++* Input:
++*			PADAPTER		Adapter,
++*
++* Output:	None
++* Return:		None
++* Note:		The initialization value is constant and it should never be changes
++*/
++static	void
++phy_InitBBRFRegisterDefinition(
++		PADAPTER		Adapter
++)
++{
++	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
++
++	/* RF Interface Sowrtware Control */
++	pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */
++	pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
++
++	/* RF Interface Output (and Enable) */
++	pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */
++	pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */
++
++	/* RF Interface (Output and)  Enable */
++	pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
++	pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
++
++	pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */
++	pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
++
++	pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  /* wire control parameter2 */
++	pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  /* wire control parameter2 */
++
++	/* Tranceiver Readback LSSI/HSPI mode */
++	pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
++	pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
++	pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
++	pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
++
++}
++
++static	int
++phy_BB8723d_Config_ParaFile(
++		PADAPTER	Adapter
++)
++{
++	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
++	int			rtStatus = _SUCCESS;
++
++	/* */
++	/* 1. Read PHY_REG.TXT BB INIT!! */
++	/* */
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++	if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_PHY_REG, CONFIG_BB_PHY_REG) == _FAIL)
++#endif
++	{
++#ifdef CONFIG_EMBEDDED_FWIMG
++		if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
++			rtStatus = _FAIL;
++#endif
++	}
++
++	if (rtStatus != _SUCCESS) {
++		RTW_INFO("%s():Write BB Reg Fail!!", __func__);
++		goto phy_BB8190_Config_ParaFile_Fail;
++	}
++
++#if MP_DRIVER == 1
++	if (Adapter->registrypriv.mp_mode == 1) {
++		/*20160504, Suggested by jessica_wang. To Fix CCK ACPR issue*/
++		phy_set_bb_reg(Adapter, 0xCE0, BIT1|BIT0, 0);/*RXHP=low corner*/
++		phy_set_bb_reg(Adapter, 0xC3C, 0xFF, 0xCC);/*make sure low rate sensitivity*/
++	}
++#endif	/*  #if (MP_DRIVER == 1) */
++
++	/* */
++	/* 2. Read BB AGC table Initialization */
++	/* */
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++	if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_AGC_TAB, CONFIG_BB_AGC_TAB) == _FAIL)
++#endif
++	{
++#ifdef CONFIG_EMBEDDED_FWIMG
++		if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
++			rtStatus = _FAIL;
++#endif
++	}
++
++	if (rtStatus != _SUCCESS) {
++		RTW_INFO("%s():AGC Table Fail\n", __func__);
++		goto phy_BB8190_Config_ParaFile_Fail;
++	}
++
++phy_BB8190_Config_ParaFile_Fail:
++
++	return rtStatus;
++}
++
++
++int
++PHY_BBConfig8723D(
++		PADAPTER Adapter
++)
++{
++	int	rtStatus = _SUCCESS;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++	u16	RegVal;
++	u8	TmpU1B = 0;
++	u8	value8;
++
++	phy_InitBBRFRegisterDefinition(Adapter);
++
++	/* Enable BB and RF */
++	RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
++	RegVal |= FEN_EN_25_1 | FEN_BB_GLB_RSTn | FEN_BBRSTB;
++	rtw_write16(Adapter, REG_SYS_FUNC_EN, RegVal);
++
++	rtw_write8(Adapter, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
++
++#if defined(CONFIG_PCI_HCI)
++	rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
++#endif
++
++#ifdef CONFIG_USB_HCI
++	/* To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23. */
++	PlatformEFIOWrite1Byte(Adapter, REG_LDOHCI12_CTRL, 0x0f);
++	PlatformEFIOWrite1Byte(Adapter, 0x15, 0xe9);
++#endif
++
++	rtw_write8(Adapter, REG_AFE_XTAL_CTRL + 1, 0x80);
++
++	/*
++	 * Config BB and AGC
++	 */
++	rtStatus = phy_BB8723d_Config_ParaFile(Adapter);
++
++	if (rtw_phydm_set_crystal_cap(Adapter, pHalData->crystal_cap) == _FALSE) {
++		RTW_ERR("Init crystal_cap failed\n");
++		rtw_warn_on(1);
++		rtStatus = _FAIL;
++	}
++
++	return rtStatus;
++}
++#if 0
++/* Block & Path enable */
++#define		rOFDMCCKEN_Jaguar		0x808 /* OFDM/CCK block enable */
++#define		bOFDMEN_Jaguar			0x20000000
++#define		bCCKEN_Jaguar			0x10000000
++#define		rRxPath_Jaguar			0x808	/* Rx antenna */
++#define		bRxPath_Jaguar			0xff
++#define		rTxPath_Jaguar			0x80c	/* Tx antenna */
++#define		bTxPath_Jaguar			0x0fffffff
++#define		rCCK_RX_Jaguar			0xa04	/* for cck rx path selection */
++#define		bCCK_RX_Jaguar			0x0c000000
++#define		rVhtlen_Use_Lsig_Jaguar	0x8c3	/* Use LSIG for VHT length */
++void
++PHY_BB8723D_Config_1T(
++		PADAPTER Adapter
++)
++{
++	/* BB OFDM RX Path_A */
++	phy_set_bb_reg(Adapter, rRxPath_Jaguar, bRxPath_Jaguar, 0x11);
++	/* BB OFDM TX Path_A */
++	phy_set_bb_reg(Adapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
++	/* BB CCK R/Rx Path_A */
++	phy_set_bb_reg(Adapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
++	/* MCS support */
++	phy_set_bb_reg(Adapter, 0x8bc, 0xc0000060, 0x4);
++	/* RF Path_B HSSI OFF */
++	phy_set_bb_reg(Adapter, 0xe00, 0xf, 0x4);
++	/* RF Path_B Power Down */
++	phy_set_bb_reg(Adapter, 0xe90, bMaskDWord, 0);
++	/* ADDA Path_B OFF */
++	phy_set_bb_reg(Adapter, 0xe60, bMaskDWord, 0);
++	phy_set_bb_reg(Adapter, 0xe64, bMaskDWord, 0);
++}
++#endif
++
++int
++PHY_RFConfig8723D(
++		PADAPTER	Adapter
++)
++{
++	int		rtStatus = _SUCCESS;
++
++	/* */
++	/* RF config */
++	/* */
++	rtStatus = PHY_RF6052_Config8723D(Adapter);
++	/* 20151207 LCK done at RadioA table */
++	/* PHY_BB8723D_Config_1T(Adapter); */
++
++	return rtStatus;
++}
++
++/*-----------------------------------------------------------------------------
++ * Function:    PHY_ConfigRFWithParaFile()
++ *
++ * Overview:    This function read RF parameters from general file format, and do RF 3-wire
++ *
++ * Input:	PADAPTER			Adapter
++ *			ps1Byte				pFileName
++ *			enum rf_path				eRFPath
++ *
++ * Output:      NONE
++ *
++ * Return:      RT_STATUS_SUCCESS: configuration file exist
++ *
++ * Note:		Delay may be required for RF configuration
++ *---------------------------------------------------------------------------*/
++int
++PHY_ConfigRFWithParaFile_8723D(
++		PADAPTER			Adapter,
++		u8					*pFileName,
++	enum rf_path				eRFPath
++)
++{
++	return _SUCCESS;
++}
++
++/**************************************************************************************************************
++ *   Description:
++ *       The low-level interface to set TxAGC , called by both MP and Normal Driver.
++ *
++ *                                                                                    <20120830, Kordan>
++ **************************************************************************************************************/
++
++void
++PHY_SetTxPowerIndex_8723D(
++		PADAPTER			Adapter,
++		u32					PowerIndex,
++		enum rf_path			RFPath,
++		u8					Rate
++)
++{
++	if (RFPath == RF_PATH_A || RFPath == RF_PATH_B) {
++		switch (Rate) {
++		case MGN_1M:
++			phy_set_bb_reg(Adapter, rTxAGC_A_CCK1_Mcs32,      bMaskByte1, PowerIndex);
++			break;
++		case MGN_2M:
++			phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex);
++			break;
++		case MGN_5_5M:
++			phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex);
++			break;
++		case MGN_11M:
++			phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex);
++			break;
++
++		case MGN_6M:
++			phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex);
++			break;
++		case MGN_9M:
++			phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex);
++			break;
++		case MGN_12M:
++			phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex);
++			break;
++		case MGN_18M:
++			phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex);
++			break;
++
++		case MGN_24M:
++			phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex);
++			break;
++		case MGN_36M:
++			phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex);
++			break;
++		case MGN_48M:
++			phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex);
++			break;
++		case MGN_54M:
++			phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex);
++			break;
++
++		case MGN_MCS0:
++			phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex);
++			break;
++		case MGN_MCS1:
++			phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex);
++			break;
++		case MGN_MCS2:
++			phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex);
++			break;
++		case MGN_MCS3:
++			phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex);
++			break;
++
++		case MGN_MCS4:
++			phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex);
++			break;
++		case MGN_MCS5:
++			phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex);
++			break;
++		case MGN_MCS6:
++			phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex);
++			break;
++		case MGN_MCS7:
++			phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex);
++			break;
++
++		default:
++			RTW_INFO("Invalid Rate!!\n");
++			break;
++		}
++	}
++}
++
++void
++PHY_SetTxPowerLevel8723D(
++		PADAPTER		Adapter,
++		u8				Channel
++)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
++	u8				cur_antenna;
++	enum rf_path		RFPath = RF_PATH_A;
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	rtw_hal_get_odm_var(Adapter, HAL_ODM_ANTDIV_SELECT, &cur_antenna, NULL);
++
++	if (pHalData->AntDivCfg)  /* antenna diversity Enable */
++		RFPath = ((cur_antenna == MAIN_ANT) ? RF_PATH_A : RF_PATH_B);
++	else   /* antenna diversity disable */
++#endif
++		RFPath = pHalData->ant_path;
++
++
++
++	phy_set_tx_power_level_by_path(Adapter, Channel, RFPath);
++
++}
++
++/* <20160217, Jessica> A workaround to eliminate the 2472MHz & 2484MHz spur of 8723D. */
++void
++phy_SpurCalibration_8723D(
++		PADAPTER					pAdapter,
++		u8						ToChannel,
++		u8						threshold
++)
++{
++	u32		freq[2] = {0xFCCD, 0xFF9A}; /* {chnl 13, 14} */
++	u8		idx = 0xFF;
++	u8		b_doNotch = FALSE;
++	u8		initial_gain;
++
++	/* add for notch */
++	u32				wlan_channel, CurrentChannel;
++	HAL_DATA_TYPE		*pHalData	= GET_HAL_DATA(pAdapter);
++	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
++
++	/* check threshold */
++	if (threshold <= 0x0)
++		threshold = 0x16;
++
++	RTW_DBG("===>phy_SpurCalibration_8723D: Channel = %d\n", ToChannel);
++
++	if (ToChannel == 13)
++		idx = 0;
++	else if (ToChannel == 14)
++		idx = 1;
++
++	/* If current channel=13,14 */
++	if (idx < 0xFF) {
++		initial_gain = (u8)(odm_get_bb_reg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0) & 0x7f);
++		odm_pause_dig(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, 0x30);
++		phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccf000c0);		/* disable 3-wire */
++
++		phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]);				/* Setup PSD */
++		phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, 0x400000 | freq[idx]); /* Start PSD	 */
++
++		rtw_msleep_os(30);
++
++		if (phy_query_bb_reg(pAdapter, rFPGA0_PSDReport, bMaskDWord) >= threshold)
++			b_doNotch = TRUE;
++
++		phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]); /* turn off PSD */
++		phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccc000c0);	/* enable 3-wire */
++		odm_pause_dig(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, NONE);
++	}
++
++	/* --- Notch Filter --- Asked by Rock	 */
++	if (b_doNotch) {
++		CurrentChannel = odm_get_rf_reg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
++		wlan_channel   = CurrentChannel & 0x0f;						    /* Get center frequency */
++
++		switch (wlan_channel) {											/* Set notch filter				 */
++		case 13:
++			odm_set_bb_reg(pDM_Odm, 0xC40, BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24), 0xB);
++			odm_set_bb_reg(pDM_Odm, 0xC40, BIT(9), 0x1);                    /* enable notch filter */
++			odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x04000000);
++			odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
++			odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
++			odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
++			odm_set_bb_reg(pDM_Odm, 0xD2C, BIT(28), 0x1);                   /* enable CSI mask */
++			break;
++		case 14:
++			odm_set_bb_reg(pDM_Odm, 0xC40, BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24), 0x5);
++			odm_set_bb_reg(pDM_Odm, 0xC40, BIT(9), 0x1);                   /* enable notch filter */
++			odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
++			odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
++			odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
++			odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00080000);
++			odm_set_bb_reg(pDM_Odm, 0xD2C, BIT(28), 0x1);                   /* enable CSI mask */
++			break;
++		default:
++			odm_set_bb_reg(pDM_Odm, 0xC40, BIT(9), 0x0);						/* disable notch filter */
++			odm_set_bb_reg(pDM_Odm, 0xD2C, BIT(28), 0x0);                   /* disable CSI mask	function */
++			break;
++		} /* switch(wlan_channel)	 */
++		return;
++	}
++
++	odm_set_bb_reg(pDM_Odm, 0xC40, BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24), 0x1f);
++	odm_set_bb_reg(pDM_Odm, 0xC40, BIT(9), 0x0);                     /* disable notch filter */
++	odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
++	odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
++	odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
++	odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
++	odm_set_bb_reg(pDM_Odm, 0xD2C, BIT(28), 0x0);                    /* disable CSI mask */
++}
++
++void
++phy_SetRegBW_8723D(
++		PADAPTER		Adapter,
++	enum channel_width	CurrentBW
++)
++{
++	u16	RegRfMod_BW, u2tmp = 0;
++
++	RegRfMod_BW = rtw_read16(Adapter, REG_TRXPTCL_CTL_8723D);
++
++	switch (CurrentBW) {
++	case CHANNEL_WIDTH_20:
++		rtw_write16(Adapter, REG_TRXPTCL_CTL_8723D, (RegRfMod_BW & 0xFE7F)); /* BIT 7 = 0, BIT 8 = 0 */
++		break;
++
++	case CHANNEL_WIDTH_40:
++		u2tmp = RegRfMod_BW | BIT(7);
++		rtw_write16(Adapter, REG_TRXPTCL_CTL_8723D, (u2tmp & 0xFEFF)); /* BIT 7 = 1, BIT 8 = 0 */
++		break;
++
++	case CHANNEL_WIDTH_80:
++		u2tmp = RegRfMod_BW | BIT(8);
++		rtw_write16(Adapter, REG_TRXPTCL_CTL_8723D, (u2tmp & 0xFF7F)); /* BIT 7 = 0, BIT 8 = 1 */
++		break;
++
++	default:
++		RTW_INFO("phy_PostSetBWMode8723D():	unknown Bandwidth: %#X\n", CurrentBW);
++		break;
++	}
++}
++
++u8
++phy_GetSecondaryChnl_8723D(
++		PADAPTER	Adapter
++)
++{
++	u8	SCSettingOf40 = 0, SCSettingOf20 = 0;
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
++
++	if (pHalData->current_channel_bw == CHANNEL_WIDTH_80) {
++		if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
++			SCSettingOf40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
++		else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
++			SCSettingOf40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
++
++
++		if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
++			SCSettingOf20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
++		else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
++			SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
++		else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
++			SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
++		else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
++			SCSettingOf20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
++
++	} else if (pHalData->current_channel_bw == CHANNEL_WIDTH_40) {
++
++		if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
++			SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
++		else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
++			SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
++
++	}
++
++	return (SCSettingOf40 << 4) | SCSettingOf20;
++}
++
++void
++phy_PostSetBwMode8723D(
++		PADAPTER padapter
++)
++{
++	u8 SubChnlNum = 0;
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++	/* 2 Set Reg668 Reg440 BW */
++	phy_SetRegBW_8723D(padapter, pHalData->current_channel_bw);
++
++	/* 3 Set Reg483 */
++	SubChnlNum = phy_GetSecondaryChnl_8723D(padapter);
++	rtw_write8(padapter, REG_DATA_SC_8723D, SubChnlNum);
++
++	switch (pHalData->current_channel_bw) {
++	/* 20 MHz channel*/
++	case CHANNEL_WIDTH_20:
++		/*
++		0x800[0]=1'b0
++		0x900[0]=1'b0
++		0x954[19]=1'b1
++		0x954[27:24]= 10
++		*/
++		phy_set_bb_reg(padapter, rFPGA0_RFMOD, bRFMOD, 0x0);
++		phy_set_bb_reg(padapter, rFPGA1_RFMOD, bRFMOD, 0x0);
++		phy_set_bb_reg(padapter, rBBrx_DFIR, BIT(19), 1);
++		phy_set_bb_reg(padapter, rBBrx_DFIR,
++			     (BIT(27) | BIT(26) | BIT(25) | BIT(24)), 0xa);
++		break;
++	/* 40 MHz channel*/
++	case CHANNEL_WIDTH_40:
++		/*
++		0x800[0]=1'b1
++		0x900[0]=1'b1
++		0x954[19]=1'b0
++		0x954[23:20]=2'b11(For ACPR)
++		0xa00[4]=1/0
++		*/
++		phy_set_bb_reg(padapter, rFPGA0_RFMOD, bRFMOD, 0x1);
++		phy_set_bb_reg(padapter, rFPGA1_RFMOD, bRFMOD, 0x1);
++		phy_set_bb_reg(padapter, rBBrx_DFIR, BIT(19), 0);
++		phy_set_bb_reg(padapter, rCCK0_System, bCCKSideBand,
++			     (pHalData->nCur40MhzPrimeSC >> 1));
++
++		break;
++	default:
++		break;
++	}
++
++	/*3<3>Set RF related register */
++	PHY_RF6052SetBandwidth8723D(padapter, pHalData->current_channel_bw);
++}
++
++void
++phy_SwChnl8723D(
++		PADAPTER					pAdapter
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
++	u8		channelToSW = pHalData->current_channel;
++	u8		i = 0;
++
++	if (pHalData->rf_chip == RF_PSEUDO_11N) {
++		RTW_WARN("phy_SwChnl8723D: return for PSEUDO\n");
++		return;
++	}
++
++	pHalData->RfRegChnlVal[0] =
++		((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW);
++	phy_set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
++		     0x3FF, pHalData->RfRegChnlVal[0]);
++	phy_set_rf_reg(pAdapter, RF_PATH_B, RF_CHNLBW,
++		     0x3FF, pHalData->RfRegChnlVal[0]);
++
++	phy_SpurCalibration_8723D(pAdapter, channelToSW, 0x16);
++
++	/* 2.4G CCK TX DFIR */
++	/* 2016.01.20 Suggest from RS BB mingzhi*/
++	if (channelToSW >= 1 && channelToSW <= 13) {
++		if (pHalData->need_restore == _TRUE) {
++			for (i = 0 ; i < 3 ; i++) {
++				phy_set_bb_reg(pAdapter,
++					     pHalData->RegForRecover[i].offset,
++					     bMaskDWord,
++					     pHalData->RegForRecover[i].value);
++			}
++			pHalData->need_restore = _FALSE;
++		}
++	} else if (channelToSW == 14) {
++		pHalData->need_restore = _TRUE;
++		phy_set_bb_reg(pAdapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
++		phy_set_bb_reg(pAdapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
++		phy_set_bb_reg(pAdapter, 0xAAC, bMaskDWord, 0x00003667);
++	}
++
++	RTW_DBG("===>phy_SwChnl8723D: Channel = %d\n", channelToSW);
++}
++
++void
++phy_SwChnlAndSetBwMode8723D(
++		PADAPTER		Adapter
++)
++{
++	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
++
++	if (Adapter->bNotifyChannelChange) {
++		RTW_INFO("[%s] bSwChnl=%d, ch=%d, bSetChnlBW=%d, bw=%d\n",
++			 __func__,
++			 pHalData->bSwChnl,
++			 pHalData->current_channel,
++			 pHalData->bSetChnlBW,
++			 pHalData->current_channel_bw);
++	}
++
++	if (RTW_CANNOT_RUN(Adapter))
++		return;
++
++	if (pHalData->bSwChnl) {
++		phy_SwChnl8723D(Adapter);
++		pHalData->bSwChnl = _FALSE;
++	}
++
++	if (pHalData->bSetChnlBW) {
++		phy_PostSetBwMode8723D(Adapter);
++		pHalData->bSetChnlBW = _FALSE;
++	}
++
++	if (pHalData->bNeedIQK == _TRUE) {
++		if (pHalData->neediqk_24g == _TRUE) {
++
++			halrf_iqk_trigger(&pHalData->odmpriv, _FALSE);
++			pHalData->bIQKInitialized = _TRUE;
++			pHalData->neediqk_24g = _FALSE;
++		}
++		pHalData->bNeedIQK = _FALSE;
++	}
++
++	rtw_hal_set_tx_power_level(Adapter, pHalData->current_channel);
++}
++
++void
++PHY_HandleSwChnlAndSetBW8723D(
++		PADAPTER			Adapter,
++		BOOLEAN				bSwitchChannel,
++		BOOLEAN				bSetBandWidth,
++		u8					ChannelNum,
++		enum channel_width	ChnlWidth,
++		EXTCHNL_OFFSET	ExtChnlOffsetOf40MHz,
++		EXTCHNL_OFFSET	ExtChnlOffsetOf80MHz,
++		u8					CenterFrequencyIndex1
++)
++{
++	/* static BOOLEAN		bInitialzed = _FALSE; */
++	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(Adapter);
++	u8					tmpChannel = pHalData->current_channel;
++	enum channel_width	tmpBW = pHalData->current_channel_bw;
++	u8					tmpnCur40MhzPrimeSC = pHalData->nCur40MhzPrimeSC;
++	u8					tmpnCur80MhzPrimeSC = pHalData->nCur80MhzPrimeSC;
++	u8					tmpCenterFrequencyIndex1 = pHalData->CurrentCenterFrequencyIndex1;
++	struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
++
++	/* RTW_INFO("=> PHY_HandleSwChnlAndSetBW8812: bSwitchChannel %d, bSetBandWidth %d\n",bSwitchChannel,bSetBandWidth); */
++
++	/* check is swchnl or setbw */
++	if (!bSwitchChannel && !bSetBandWidth) {
++		RTW_INFO("PHY_HandleSwChnlAndSetBW8812:  not switch channel and not set bandwidth\n");
++		return;
++	}
++
++	/* skip change for channel or bandwidth is the same */
++	if (bSwitchChannel) {
++		/* if(pHalData->current_channel != ChannelNum) */
++		{
++			if (HAL_IsLegalChannel(Adapter, ChannelNum))
++				pHalData->bSwChnl = _TRUE;
++		}
++	}
++
++	if (bSetBandWidth) {
++#if 0
++		if (bInitialzed == _FALSE) {
++			bInitialzed = _TRUE;
++			pHalData->bSetChnlBW = _TRUE;
++		} else if ((pHalData->current_channel_bw != ChnlWidth) || (pHalData->nCur40MhzPrimeSC != ExtChnlOffsetOf40MHz) || (pHalData->CurrentCenterFrequencyIndex1 != CenterFrequencyIndex1))
++			pHalData->bSetChnlBW = _TRUE;
++#else
++		pHalData->bSetChnlBW = _TRUE;
++#endif
++	}
++
++	if (!pHalData->bSetChnlBW && !pHalData->bSwChnl) {
++		/* RTW_INFO("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d\n",pHalData->bSwChnl,pHalData->bSetChnlBW); */
++		return;
++	}
++
++
++	if (pHalData->bSwChnl) {
++		pHalData->current_channel = ChannelNum;
++		pHalData->CurrentCenterFrequencyIndex1 = ChannelNum;
++	}
++
++
++	if (pHalData->bSetChnlBW) {
++		pHalData->current_channel_bw = ChnlWidth;
++#if 0
++		if (ExtChnlOffsetOf40MHz == EXTCHNL_OFFSET_LOWER)
++			pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
++		else if (ExtChnlOffsetOf40MHz == EXTCHNL_OFFSET_UPPER)
++			pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
++		else
++			pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++		if (ExtChnlOffsetOf80MHz == EXTCHNL_OFFSET_LOWER)
++			pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
++		else if (ExtChnlOffsetOf80MHz == EXTCHNL_OFFSET_UPPER)
++			pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
++		else
++			pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++#else
++		pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz;
++		pHalData->nCur80MhzPrimeSC = ExtChnlOffsetOf80MHz;
++#endif
++
++		pHalData->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1;
++	}
++
++	/* Switch workitem or set timer to do switch channel or setbandwidth operation */
++	if (!RTW_CANNOT_RUN(Adapter))
++		phy_SwChnlAndSetBwMode8723D(Adapter);
++	else {
++		if (pHalData->bSwChnl) {
++			pHalData->current_channel = tmpChannel;
++			pHalData->CurrentCenterFrequencyIndex1 = tmpChannel;
++		}
++		if (pHalData->bSetChnlBW) {
++			pHalData->current_channel_bw = tmpBW;
++			pHalData->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC;
++			pHalData->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC;
++			pHalData->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1;
++		}
++	}
++
++	/* RTW_INFO("Channel %d ChannelBW %d ",pHalData->current_channel, pHalData->current_channel_bw); */
++	/* RTW_INFO("40MhzPrimeSC %d 80MhzPrimeSC %d ",pHalData->nCur40MhzPrimeSC, pHalData->nCur80MhzPrimeSC); */
++	/* RTW_INFO("CenterFrequencyIndex1 %d\n",pHalData->CurrentCenterFrequencyIndex1); */
++
++	/* RTW_INFO("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d\n",pHalData->bSwChnl,pHalData->bSetChnlBW); */
++
++}
++
++void
++PHY_SetSwChnlBWMode8723D(
++		PADAPTER			Adapter,
++		u8					channel,
++		enum channel_width	Bandwidth,
++		u8					Offset40,
++		u8					Offset80
++)
++{
++	/* RTW_INFO("%s()===>\n",__FUNCTION__); */
++
++	PHY_HandleSwChnlAndSetBW8723D(Adapter, _TRUE, _TRUE, channel, Bandwidth, Offset40, Offset80, channel);
++
++	/* RTW_INFO("<==%s()\n",__FUNCTION__); */
++}
++ 
+\ No newline at end of file
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_rf6052.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_rf6052.c
+new file mode 100644
+index 000000000..39f281a46
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_rf6052.c
+@@ -0,0 +1,235 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/******************************************************************************
++ *
++ *
++ * Module:	rtl8192c_rf6052.c	( Source C File)
++ *
++ * Note:	Provide RF 6052 series relative API.
++ *
++ * Function:
++ *
++ * Export:
++ *
++ * Abbrev:
++ *
++ * History:
++ * Data			Who		Remark
++ *
++ * 09/25/2008	MHC		Create initial version.
++ * 11/05/2008	MHC		Add API for tw power setting.
++ *
++ *
++******************************************************************************/
++
++#include <rtl8723d_hal.h>
++
++/*---------------------------Define Local Constant---------------------------*/
++/*---------------------------Define Local Constant---------------------------*/
++
++
++/*------------------------Define global variable-----------------------------*/
++/*------------------------Define global variable-----------------------------*/
++
++
++/*------------------------Define local variable------------------------------*/
++#ifdef CONFIG_RF_SHADOW_RW
++/* 2008/11/20 MH For Debug only, RF
++ * static	RF_SHADOW_T	RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0}; */
++static	RF_SHADOW_T	RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
++#endif /*CONFIG_RF_SHADOW_RW*/
++/*------------------------Define local variable------------------------------*/
++
++/*-----------------------------------------------------------------------------
++ * Function:    PHY_RF6052SetBandwidth()
++ *
++ * Overview:    This function is called by SetBWModeCallback8190Pci() only
++ *
++ * Input:       PADAPTER				Adapter
++ *			WIRELESS_BANDWIDTH_E	Bandwidth
++ *
++ * Output:      NONE
++ *
++ * Return:      NONE
++ *
++ * Note:		For RF type 0222D
++ *---------------------------------------------------------------------------*/
++void
++PHY_RF6052SetBandwidth8723D(
++		PADAPTER padapter,
++		enum channel_width Bandwidth)	/* 20M or 40M */
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++	switch (Bandwidth) {
++	case CHANNEL_WIDTH_20:
++		/*
++		RF_A_reg 0x18[11:10]=2'b11
++		RF_A_reg 0x18[9:0]
++		*/
++		pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11));
++		phy_set_rf_reg(padapter, RF_PATH_A, 0x18, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); /* RF TRX_BW */
++		break;
++	case CHANNEL_WIDTH_40:
++		/*
++		RF_A_reg 0x18[11:10]=2'b01
++		RF_A_reg 0x18[9:0]
++		*/
++		pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10));
++		phy_set_rf_reg(padapter, RF_PATH_A, 0x18, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); /* RF TRX_BW */
++		break;
++	default:
++		break;
++	}
++}
++
++static int
++phy_RF6052_Config_ParaFile(
++		PADAPTER		Adapter
++)
++{
++	u32					u4RegValue = 0;
++	enum rf_path			eRFPath;
++	BB_REGISTER_DEFINITION_T	*pPhyReg;
++
++	int					rtStatus = _SUCCESS;
++	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
++
++	/* 3//----------------------------------------------------------------- */
++	/* 3// <2> Initialize RF */
++	/* 3//----------------------------------------------------------------- */
++	for (eRFPath = RF_PATH_A; eRFPath < hal_spec->rf_reg_path_num; eRFPath++) {
++
++		pPhyReg = &pHalData->PHYRegDef[eRFPath];
++
++		/*----Store original RFENV control type----*/
++		switch (eRFPath) {
++		case RF_PATH_A:
++		case RF_PATH_C:
++			u4RegValue = phy_query_bb_reg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
++			break;
++		case RF_PATH_B:
++		case RF_PATH_D:
++			u4RegValue = phy_query_bb_reg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV << 16);
++			break;
++		default:
++			RTW_ERR("Invalid rf_path:%d\n", eRFPath);
++			break;
++		}
++
++		/*----Set RF_ENV enable----*/
++		phy_set_bb_reg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1);
++		rtw_udelay_os(1);/* PlatformStallExecution(1); */
++
++		/*----Set RF_ENV output high----*/
++		phy_set_bb_reg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
++		rtw_udelay_os(1);/* PlatformStallExecution(1); */
++
++		/* Set bit number of Address and Data for RF register */
++		phy_set_bb_reg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);	/* Set 1 to 4 bits for 8255 */
++		rtw_udelay_os(1);/* PlatformStallExecution(1); */
++
++		phy_set_bb_reg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);	/* Set 0 to 12  bits for 8255 */
++		rtw_udelay_os(1);/* PlatformStallExecution(1); */
++
++		/*----Initialize RF fom connfiguration file----*/
++		switch (eRFPath) {
++		case RF_PATH_A:
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++			if (PHY_ConfigRFWithParaFile(Adapter, PHY_FILE_RADIO_A, eRFPath) == _FAIL)
++#endif
++			{
++#ifdef CONFIG_EMBEDDED_FWIMG
++				if (odm_config_rf_with_header_file(&pHalData->odmpriv, CONFIG_RF_RADIO, eRFPath) == HAL_STATUS_FAILURE)
++					rtStatus = _FAIL;
++#endif
++			}
++			break;
++		case RF_PATH_B:
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++			if (PHY_ConfigRFWithParaFile(Adapter, PHY_FILE_RADIO_B, eRFPath) == _FAIL)
++#endif
++			{
++#ifdef CONFIG_EMBEDDED_FWIMG
++				if (odm_config_rf_with_header_file(&pHalData->odmpriv, CONFIG_RF_RADIO, eRFPath) == HAL_STATUS_FAILURE)
++					rtStatus = _FAIL;
++#endif
++			}
++			break;
++		case RF_PATH_C:
++			break;
++		case RF_PATH_D:
++			break;
++		default:
++			RTW_ERR("Invalid rf_path:%d\n", eRFPath);
++			break;
++		}
++
++		/*----Restore RFENV control type----*/;
++		switch (eRFPath) {
++		case RF_PATH_A:
++		case RF_PATH_C:
++			phy_set_bb_reg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
++			break;
++		case RF_PATH_B:
++		case RF_PATH_D:
++			phy_set_bb_reg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV << 16, u4RegValue);
++			break;
++		default:
++			RTW_ERR("Invalid rf_path:%d\n", eRFPath);
++			break;
++		}
++
++		if (rtStatus != _SUCCESS) {
++			goto phy_RF6052_Config_ParaFile_Fail;
++		}
++
++	}
++
++	/* 3 ----------------------------------------------------------------- */
++	/* 3 Configuration of Tx Power Tracking */
++	/* 3 ----------------------------------------------------------------- */
++
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++	if (PHY_ConfigRFWithTxPwrTrackParaFile(Adapter, PHY_FILE_TXPWR_TRACK) == _FAIL)
++#endif
++	{
++#ifdef CONFIG_EMBEDDED_FWIMG
++		odm_config_rf_with_tx_pwr_track_header_file(&pHalData->odmpriv);
++#endif
++	}
++
++	return rtStatus;
++
++phy_RF6052_Config_ParaFile_Fail:
++	return rtStatus;
++}
++
++
++int
++PHY_RF6052_Config8723D(
++		PADAPTER		Adapter)
++{
++	int					rtStatus = _SUCCESS;
++
++	/* */
++	/* Config BB and RF */
++	/* */
++	rtStatus = phy_RF6052_Config_ParaFile(Adapter);
++	return rtStatus;
++}
++
++/* End of HalRf6052.c */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_rxdesc.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_rxdesc.c
+new file mode 100644
+index 000000000..7dc37b84e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_rxdesc.c
+@@ -0,0 +1,57 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTL8723D_REDESC_C_
++
++#include <rtl8723d_hal.h>
++
++void rtl8723d_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc)
++{
++	struct rx_pkt_attrib *pattrib;
++
++
++	pattrib = &precvframe->u.hdr.attrib;
++	_rtw_memset(pattrib, 0, sizeof(struct rx_pkt_attrib));
++
++	pattrib->pkt_len = (u16)GET_RX_STATUS_DESC_PKT_LEN_8723D(pdesc);
++	pattrib->pkt_rpt_type = GET_RX_STATUS_DESC_RPT_SEL_8723D(pdesc) ? C2H_PACKET : NORMAL_RX;
++
++	if (pattrib->pkt_rpt_type == NORMAL_RX) {
++		/* Offset 0 */
++		pattrib->crc_err = (u8)GET_RX_STATUS_DESC_CRC32_8723D(pdesc);
++		pattrib->icv_err = (u8)GET_RX_STATUS_DESC_ICV_8723D(pdesc);
++		pattrib->drvinfo_sz = (u8)GET_RX_STATUS_DESC_DRVINFO_SIZE_8723D(pdesc) << 3;
++		pattrib->encrypt = (u8)GET_RX_STATUS_DESC_SECURITY_8723D(pdesc);
++		pattrib->qos = (u8)GET_RX_STATUS_DESC_QOS_8723D(pdesc);
++		pattrib->shift_sz = (u8)GET_RX_STATUS_DESC_SHIFT_8723D(pdesc);
++		pattrib->physt = (u8)GET_RX_STATUS_DESC_PHY_STATUS_8723D(pdesc);
++		pattrib->bdecrypted = (u8)GET_RX_STATUS_DESC_SWDEC_8723D(pdesc) ? 0 : 1;
++
++		/* Offset 4 */
++		pattrib->priority = (u8)GET_RX_STATUS_DESC_TID_8723D(pdesc);
++		pattrib->amsdu = (u8)GET_RX_STATUS_DESC_AMSDU_8723D(pdesc);
++		pattrib->mdata = (u8)GET_RX_STATUS_DESC_MORE_DATA_8723D(pdesc);
++		pattrib->mfrag = (u8)GET_RX_STATUS_DESC_MORE_FRAG_8723D(pdesc);
++
++		/* Offset 8 */
++		pattrib->seq_num = (u16)GET_RX_STATUS_DESC_SEQ_8723D(pdesc);
++		pattrib->frag_num = (u8)GET_RX_STATUS_DESC_FRAG_8723D(pdesc);
++
++		/* Offset 12 */
++		pattrib->data_rate = (u8)GET_RX_STATUS_DESC_RX_RATE_8723D(pdesc);
++		pattrib->bw = CHANNEL_WIDTH_MAX;
++		/* Offset 20 */
++		/* pattrib->tsfl=(u8)GET_RX_STATUS_DESC_TSFL_8723D(pdesc); */
++	}
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_sreset.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_sreset.c
+new file mode 100644
+index 000000000..de73fbc4c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/rtl8723d_sreset.c
+@@ -0,0 +1,101 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTL8723D_SRESET_C_
++
++#include <rtl8723d_hal.h>
++
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++void rtl8723d_sreset_xmit_status_check(_adapter *padapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++
++	systime current_time;
++	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
++	unsigned int diff_time;
++	u32 txdma_status;
++
++	txdma_status = rtw_read32(padapter, REG_TXDMA_STATUS);
++	if (txdma_status != 0x00 && txdma_status != 0xeaeaeaea) {
++		RTW_INFO("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);
++		rtw_hal_sreset_reset(padapter);
++	}
++
++#ifdef CONFIG_USB_HCI
++	/* total xmit irp = 4 */
++	/* DBG_8192C("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt); */
++	/* if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1) */
++	current_time = rtw_get_current_time();
++
++	if (0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {
++
++		diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time);
++
++		if (diff_time > 2000) {
++			if (psrtpriv->last_tx_complete_time == 0)
++				psrtpriv->last_tx_complete_time = current_time;
++			else {
++				diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time);
++				if (diff_time > 4000) {
++
++					/* padapter->Wifi_Error_Status = WIFI_TX_HANG; */
++					RTW_INFO("%s tx hang %s\n", __FUNCTION__,
++						(rtw_odm_adaptivity_needed(padapter)) ? "ODM_BB_ADAPTIVITY" : "");
++
++					if (!rtw_odm_adaptivity_needed(padapter))
++						rtw_hal_sreset_reset(padapter);
++				}
++			}
++		}
++	}
++#endif /*  #ifdef CONFIG_USB_HCI */
++
++	if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) {
++		psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
++		rtw_hal_sreset_reset(padapter);
++		return;
++	}
++}
++
++void rtl8723d_sreset_linked_status_check(_adapter *padapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++#if 0
++	u32 regc50, regc58, reg824, reg800;
++
++	regc50 = rtw_read32(padapter, 0xc50);
++	regc58 = rtw_read32(padapter, 0xc58);
++	reg824 = rtw_read32(padapter, 0x824);
++	reg800 = rtw_read32(padapter, 0x800);
++	if (((regc50 & 0xFFFFFF00) != 0x69543400) ||
++	    ((regc58 & 0xFFFFFF00) != 0x69543400) ||
++	    (((reg824 & 0xFFFFFF00) != 0x00390000) && (((reg824 & 0xFFFFFF00) != 0x80390000))) ||
++	    (((reg800 & 0xFFFFFF00) != 0x03040000) && ((reg800 & 0xFFFFFF00) != 0x83040000))) {
++		DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __FUNCTION__,
++			  regc50, regc58, reg824, reg800);
++		rtw_hal_sreset_reset(padapter);
++	}
++#endif
++
++	if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {
++		psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
++		rtw_hal_sreset_reset(padapter);
++		return;
++	}
++}
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/sdio/rtl8723ds_led.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/sdio/rtl8723ds_led.c
+new file mode 100644
+index 000000000..0df289cb4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/sdio/rtl8723ds_led.c
+@@ -0,0 +1,123 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTL8723DS_LED_C_
++#ifdef CONFIG_RTW_SW_LED
++
++#include "rtl8723d_hal.h"
++
++/* ********************************************************************************
++ * LED object.
++ * ******************************************************************************** */
++
++
++/* ********************************************************************************
++ *	Prototype of protected function.
++ * ******************************************************************************** */
++
++/* ********************************************************************************
++ * LED_819xUsb routines.
++ * ******************************************************************************** */
++
++/*
++ *	Description:
++ *		Turn on LED according to LedPin specified.
++ *   */
++void
++SwLedOn_8723DS(
++	_adapter			*padapter,
++	PLED_SDIO		pLed
++)
++{
++	u8	LedCfg;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	if (RTW_CANNOT_RUN(padapter))
++		return;
++
++	pLed->bLedOn = _TRUE;
++
++}
++
++
++/*
++ *	Description:
++ *		Turn off LED according to LedPin specified.
++ *   */
++void
++SwLedOff_8723DS(
++	_adapter			*padapter,
++	PLED_SDIO		pLed
++)
++{
++	u8	LedCfg;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	if (RTW_CANNOT_RUN(padapter))
++		goto exit;
++
++exit:
++	pLed->bLedOn = _FALSE;
++
++}
++
++/* ********************************************************************************
++ * Interface to manipulate LED objects.
++ * ******************************************************************************** */
++
++/* ********************************************************************************
++ * Default LED behavior.
++ * ******************************************************************************** */
++
++/*
++ *	Description:
++ *		Initialize all LED_871x objects.
++ *   */
++void
++rtl8723ds_InitSwLeds(
++	_adapter	*padapter
++)
++{
++#if 0
++	struct led_priv *pledpriv = adapter_to_led(padapter);
++
++	pledpriv->LedControlHandler = LedControlSDIO;
++
++	pledpriv->SwLedOn = SwLedOn_8723DS;
++	pledpriv->SwLedOff = SwLedOff_8723DS;
++
++	InitLed871x(padapter, &(pledpriv->SwLed0), LED_PIN_LED0);
++
++	InitLed871x(padapter, &(pledpriv->SwLed1), LED_PIN_LED1);
++#endif
++}
++
++
++/*
++ *	Description:
++ *		DeInitialize all LED_819xUsb objects.
++ *   */
++void
++rtl8723ds_DeInitSwLeds(
++	_adapter	*padapter
++)
++{
++#if 0
++	struct led_priv	*ledpriv = adapter_to_led(padapter);
++
++	DeInitLed871x(&(ledpriv->SwLed0));
++	DeInitLed871x(&(ledpriv->SwLed1));
++#endif
++}
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/sdio/rtl8723ds_recv.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/sdio/rtl8723ds_recv.c
+new file mode 100644
+index 000000000..ceb395e90
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/sdio/rtl8723ds_recv.c
+@@ -0,0 +1,510 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTL8723DS_RECV_C_
++
++#include <rtl8723d_hal.h>
++
++
++static s32 initrecvbuf(struct recv_buf *precvbuf, PADAPTER padapter)
++{
++	_rtw_init_listhead(&precvbuf->list);
++	_rtw_spinlock_init(&precvbuf->recvbuf_lock);
++
++	precvbuf->adapter = padapter;
++
++	return _SUCCESS;
++}
++
++static void freerecvbuf(struct recv_buf *precvbuf)
++{
++	_rtw_spinlock_free(&precvbuf->recvbuf_lock);
++}
++
++#ifdef CONFIG_SDIO_RX_COPY
++s32 rtl8723ds_recv_hdl(_adapter *padapter)
++{
++	PHAL_DATA_TYPE		pHalData;
++	struct recv_priv		*precvpriv;
++	struct recv_buf	*precvbuf;
++	union recv_frame		*precvframe;
++	struct recv_frame_hdr	*phdr;
++	struct rx_pkt_attrib	*pattrib;
++	u8	*ptr;
++	u32	pkt_len, pkt_offset;
++	u8	rx_report_sz = 0;
++
++	pHalData = GET_HAL_DATA(padapter);
++	precvpriv = &padapter->recvpriv;
++
++	do {
++		precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue);
++		if (NULL == precvbuf)
++			break;
++
++		ptr = precvbuf->pdata;
++
++		while (ptr < precvbuf->ptail) {
++			precvframe = rtw_alloc_recvframe(&precvpriv->free_recv_queue);
++			if (precvframe == NULL) {
++				RTW_INFO("%s: no enough recv frame!\n", __FUNCTION__);
++				rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
++				return RTW_RFRAME_UNAVAIL;
++			}
++
++			/* rx desc parsing */
++			rtl8723d_query_rx_desc_status(precvframe, ptr);
++
++			pattrib = &precvframe->u.hdr.attrib;
++
++			/* fix Hardware RX data error, drop whole recv_buffer */
++			if (!rtw_hal_rcr_check(padapter, RCR_ACRC32) && pattrib->crc_err) {
++#if !(MP_DRIVER == 1)
++				RTW_INFO("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__);
++#endif
++				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
++				break;
++			}
++
++			rx_report_sz = RXDESC_SIZE + pattrib->drvinfo_sz;
++			pkt_offset = rx_report_sz + pattrib->shift_sz + pattrib->pkt_len;
++
++			if ((ptr + pkt_offset) > precvbuf->ptail) {
++				RTW_INFO("%s()-%d: : next pkt len(%p,%d) exceed ptail(%p)!\n", __FUNCTION__, __LINE__, ptr, pkt_offset, precvbuf->ptail);
++				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
++				break;
++			}
++
++			if ((pattrib->crc_err) || (pattrib->icv_err)) {
++#ifdef CONFIG_MP_INCLUDED
++				if (padapter->registrypriv.mp_mode == 1) {
++					if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _TRUE) { /* &&(padapter->mppriv.check_mp_pkt == 0)) */
++						if (pattrib->crc_err == 1)
++							padapter->mppriv.rx_crcerrpktcount++;
++					}
++				} else
++#endif
++				{
++					RTW_INFO("%s: crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err);
++				}
++				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
++			} else {
++#ifdef CONFIG_RX_PACKET_APPEND_FCS
++				if (check_fwstate(&padapter->mlmepriv, WIFI_MONITOR_STATE) == _FALSE)
++					if ((pattrib->pkt_rpt_type == NORMAL_RX) && rtw_hal_rcr_check(padapter, RCR_APPFCS))
++						pattrib->pkt_len -= IEEE80211_FCS_LEN;
++#endif
++
++				if (rtw_os_alloc_recvframe(padapter, precvframe,
++					(ptr + rx_report_sz + pattrib->shift_sz), precvbuf->pskb) == _FAIL) {
++					rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
++					break;
++				}
++
++				recvframe_put(precvframe, pattrib->pkt_len);
++				/* move to drv info position */
++				ptr += RXDESC_SIZE;
++
++				/* update drv info */
++				if (rtw_hal_rcr_check(padapter, RCR_APP_BA_SSN)) {
++					/* rtl8723s_update_bassn(padapter, pdrvinfo); */
++					ptr += 4;
++				}
++
++				if (pattrib->pkt_rpt_type == NORMAL_RX) {
++					/* skip the rx packet with abnormal length */
++					if (pattrib->pkt_len < 14 || pattrib->pkt_len > 8192) {
++						RTW_INFO("skip abnormal rx packet(%d)\n", pattrib->pkt_len);
++						rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
++						break;
++					}
++
++					pre_recv_entry(precvframe, pattrib->physt ? ptr : NULL);
++
++				} else {
++#ifdef CONFIG_FW_C2H_PKT
++					if (pattrib->pkt_rpt_type == C2H_PACKET)
++						rtw_hal_c2h_pkt_pre_hdl(padapter, precvframe->u.hdr.rx_data, pattrib->pkt_len);
++					else {
++						RTW_INFO("%s: [WARNNING] RX type(%d) not be handled!\n",
++							__FUNCTION__, pattrib->pkt_rpt_type);
++					}
++#endif
++					rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
++				}
++			}
++
++			pkt_offset = _RND8(pkt_offset);
++			precvbuf->pdata += pkt_offset;
++			ptr = precvbuf->pdata;
++			precvframe = NULL;
++		}
++
++		rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue);
++	} while (1);
++
++#ifdef CONFIG_RTW_NAPI
++#ifdef CONFIG_RTW_NAPI_V2
++	if (padapter->registrypriv.en_napi) {
++		struct dvobj_priv *d;
++		struct _ADAPTER *a;
++		u8 i;
++
++		d = adapter_to_dvobj(padapter);
++		for (i = 0; i < d->iface_nums; i++) {
++			a = d->padapters[i];
++			precvpriv = &a->recvpriv;
++			if (rtw_if_up(a) == _TRUE
++				&& skb_queue_len(&precvpriv->rx_napi_skb_queue))
++				napi_schedule(&a->napi);
++	
++		}
++	}
++#endif /* CONFIG_RTW_NAPI_V2 */
++#endif /* CONFIG_RTW_NAPI */
++	
++	return _SUCCESS;
++}
++
++static void rtl8723ds_recv_tasklet(void *priv)
++{
++	_adapter *adapter = (_adapter *)priv;
++	s32 ret;
++
++	ret = rtl8723ds_recv_hdl(adapter);
++	if (ret == RTW_RFRAME_UNAVAIL
++		|| ret == RTW_RFRAME_PKT_UNAVAIL
++	) {
++		/* schedule again and hope recvframe/packet is available next time. */
++		#ifdef PLATFORM_LINUX
++		tasklet_schedule(&adapter->recvpriv.recv_tasklet);
++		#endif
++	}
++}
++#else
++static void rtl8723ds_recv_tasklet(void *priv)
++{
++	PADAPTER				padapter;
++	PHAL_DATA_TYPE			pHalData;
++	struct recv_priv		*precvpriv;
++	struct recv_buf		*precvbuf;
++	union recv_frame		*precvframe;
++	struct recv_frame_hdr	*phdr;
++	struct rx_pkt_attrib	*pattrib;
++	u8			*ptr;
++	_pkt		*ppkt;
++	u32		pkt_offset;
++
++	padapter = (PADAPTER)priv;
++	pHalData = GET_HAL_DATA(padapter);
++	precvpriv = &padapter->recvpriv;
++
++	do {
++		precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue);
++		if (NULL == precvbuf)
++			break;
++
++		ptr = precvbuf->pdata;
++
++		while (ptr < precvbuf->ptail) {
++			precvframe = rtw_alloc_recvframe(&precvpriv->free_recv_queue);
++			if (precvframe == NULL) {
++				rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
++
++				/* The case of can't allocate recvframe should be temporary, */
++				/* schedule again and hope recvframe is available next time. */
++#ifdef PLATFORM_LINUX
++				tasklet_schedule(&precvpriv->recv_tasklet);
++#endif
++				return;
++			}
++
++			phdr = &precvframe->u.hdr;
++			pattrib = &phdr->attrib;
++
++			rtl8723d_query_rx_desc_status(precvframe, ptr);
++
++#if 0
++			{
++				int i, len = 64;
++				u8 *pptr = ptr;
++
++				if ((*(pptr + RXDESC_SIZE + pattrib->drvinfo_sz) != 0x80) && (*(pptr + RXDESC_SIZE + pattrib->drvinfo_sz) != 0x40)) {
++					RTW_INFO("##############RxDESC###############\n");
++					for (i = 0; i < 32; i = i + 16)
++						RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(pptr + i),
++							*(pptr + i + 1), *(pptr + i + 2) , *(pptr + i + 3) , *(pptr + i + 4), *(pptr + i + 5), *(pptr + i + 6), *(pptr + i + 7), *(pptr + i + 8),
++							*(pptr + i + 9), *(pptr + i + 10),
++							*(pptr + i + 11), *(pptr + i + 12), *(pptr + i + 13), *(pptr + i + 14), *(pptr + i + 15));
++
++					if (pattrib->pkt_len < 100)
++						len = pattrib->pkt_len;
++					pptr = ptr + RXDESC_SIZE + pattrib->drvinfo_sz;
++					RTW_INFO("##############Len=%d###############\n", pattrib->pkt_len);
++					for (i = 0; i < len; i = i + 16)
++						RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(pptr + i),
++							*(pptr + i + 1), *(pptr + i + 2) , *(pptr + i + 3) , *(pptr + i + 4), *(pptr + i + 5), *(pptr + i + 6), *(pptr + i + 7), *(pptr + i + 8),
++							*(pptr + i + 9), *(pptr + i + 10),
++							*(pptr + i + 11), *(pptr + i + 12), *(pptr + i + 13), *(pptr + i + 14), *(pptr + i + 15));
++					RTW_INFO("#############################\n");
++				}
++			}
++#endif
++
++			/* fix Hardware RX data error, drop whole recv_buffer */
++			if (!rtw_hal_rcr_check(padapter, RCR_ACRC32) && pattrib->crc_err) {
++				RTW_INFO("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__);
++				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
++				break;
++			}
++
++			pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->pkt_len;
++#if 0 /* reduce check to speed up */
++			if ((ptr + pkt_offset) > precvbuf->ptail) {
++				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
++				break;
++			}
++#endif
++
++			if ((pattrib->crc_err) || (pattrib->icv_err)) {
++#ifdef CONFIG_MP_INCLUDED
++				if (padapter->registrypriv.mp_mode == 1) {
++					if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _TRUE) { /* &&(padapter->mppriv.check_mp_pkt == 0)) */
++						if (pattrib->crc_err == 1)
++							padapter->mppriv.rx_crcerrpktcount++;
++					}
++				} else
++#endif
++				{
++					RTW_INFO("%s: crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err);
++				}
++				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
++			} else {
++				ppkt = rtw_skb_clone(precvbuf->pskb);
++				if (ppkt == NULL) {
++					RTW_INFO("%s: no enough memory to allocate SKB!\n", __FUNCTION__);
++					rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
++					rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
++
++					/* The case of can't allocate skb is serious and may never be recovered, */
++					/* once bDriverStopped is enable, this task should be stopped. */
++					if (!rtw_is_drv_stopped(padapter)) {
++#ifdef PLATFORM_LINUX
++						tasklet_schedule(&precvpriv->recv_tasklet);
++#endif
++					}
++
++					return;
++				}
++
++				phdr->pkt = ppkt;
++				phdr->len = 0;
++				phdr->rx_head = precvbuf->phead;
++				phdr->rx_data = phdr->rx_tail = precvbuf->pdata;
++				phdr->rx_end = precvbuf->pend;
++				recvframe_put(precvframe, pkt_offset);
++				recvframe_pull(precvframe, RXDESC_SIZE + pattrib->drvinfo_sz);
++				skb_pull(ppkt, RXDESC_SIZE + pattrib->drvinfo_sz);
++
++#ifdef CONFIG_RX_PACKET_APPEND_FCS
++				if (check_fwstate(&padapter->mlmepriv, WIFI_MONITOR_STATE) == _FALSE) {
++					if ((pattrib->pkt_rpt_type == NORMAL_RX) && rtw_hal_rcr_check(padapter, RCR_APPFCS)) {
++						recvframe_pull_tail(precvframe, IEEE80211_FCS_LEN);
++						pattrib->pkt_len -= IEEE80211_FCS_LEN;
++						ppkt->len = pattrib->pkt_len;
++					}
++				}
++#endif
++
++				/* move to drv info position */
++				ptr += RXDESC_SIZE;
++
++				/* update drv info */
++				if (rtw_hal_rcr_check(padapter, RCR_APP_BA_SSN)) {
++					/* rtl8723s_update_bassn(padapter, pdrvinfo); */
++					ptr += 4;
++				}
++
++				if (pattrib->pkt_rpt_type == NORMAL_RX)
++					pre_recv_entry(precvframe, pattrib->physt ? ptr : NULL);
++				else {
++#ifdef CONFIG_FW_C2H_PKT
++					if (pattrib->pkt_rpt_type == C2H_PACKET)
++						rtw_hal_c2h_pkt_pre_hdl(padapter, precvframe->u.hdr.rx_data, pattrib->pkt_len);
++					else {
++						RTW_INFO("%s: [WARNNING] RX type(%d) not be handled!\n",
++							__FUNCTION__, pattrib->pkt_rpt_type);
++					}
++#endif
++					rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
++				}
++			}
++
++			pkt_offset = _RND8(pkt_offset);
++			precvbuf->pdata += pkt_offset;
++			ptr = precvbuf->pdata;
++		}
++
++		rtw_skb_free(precvbuf->pskb);
++		precvbuf->pskb = NULL;
++		rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue);
++	} while (1);
++}
++#endif
++
++/*
++ * Initialize recv private variable for hardware dependent
++ * 1. recv buf
++ * 2. recv tasklet
++ *
++ */
++s32 rtl8723ds_init_recv_priv(PADAPTER padapter)
++{
++	s32			res;
++	u32			i, n;
++	struct recv_priv	*precvpriv;
++	struct recv_buf		*precvbuf;
++
++
++	res = _SUCCESS;
++	precvpriv = &padapter->recvpriv;
++
++	/* 3 1. init recv buffer */
++	_rtw_init_queue(&precvpriv->free_recv_buf_queue);
++	_rtw_init_queue(&precvpriv->recv_buf_pending_queue);
++
++	n = NR_RECVBUFF * sizeof(struct recv_buf) + 4;
++	precvpriv->pallocated_recv_buf = rtw_zmalloc(n);
++	if (precvpriv->pallocated_recv_buf == NULL) {
++		res = _FAIL;
++		goto exit;
++	}
++
++	precvpriv->precv_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_recv_buf), 4);
++
++	/* init each recv buffer */
++	precvbuf = (struct recv_buf *)precvpriv->precv_buf;
++	for (i = 0; i < NR_RECVBUFF; i++) {
++		res = initrecvbuf(precvbuf, padapter);
++		if (res == _FAIL)
++			break;
++
++		res = rtw_os_recvbuf_resource_alloc(padapter, precvbuf);
++		if (res == _FAIL) {
++			freerecvbuf(precvbuf);
++			break;
++		}
++
++#ifdef CONFIG_SDIO_RX_COPY
++		if (precvbuf->pskb == NULL) {
++			SIZE_PTR tmpaddr = 0;
++			SIZE_PTR alignment = 0;
++
++			precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
++
++			if (precvbuf->pskb) {
++				precvbuf->pskb->dev = padapter->pnetdev;
++
++				tmpaddr = (SIZE_PTR)precvbuf->pskb->data;
++				alignment = tmpaddr & (RECVBUFF_ALIGN_SZ - 1);
++				skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment));
++			}
++
++			if (precvbuf->pskb == NULL)
++				RTW_INFO("%s: alloc_skb fail!\n", __FUNCTION__);
++		}
++#endif
++
++		rtw_list_insert_tail(&precvbuf->list, &precvpriv->free_recv_buf_queue.queue);
++
++		precvbuf++;
++	}
++	precvpriv->free_recv_buf_queue_cnt = i;
++
++	if (res == _FAIL)
++		goto initbuferror;
++
++	/* 3 2. init tasklet */
++#ifdef PLATFORM_LINUX
++	tasklet_init(&precvpriv->recv_tasklet,
++		     (void(*)(unsigned long))rtl8723ds_recv_tasklet,
++		     (unsigned long)padapter);
++#endif
++
++	goto exit;
++
++initbuferror:
++	precvbuf = (struct recv_buf *)precvpriv->precv_buf;
++	if (precvbuf) {
++		n = precvpriv->free_recv_buf_queue_cnt;
++		precvpriv->free_recv_buf_queue_cnt = 0;
++		for (i = 0; i < n ; i++) {
++			rtw_list_delete(&precvbuf->list);
++			rtw_os_recvbuf_resource_free(padapter, precvbuf);
++			freerecvbuf(precvbuf);
++			precvbuf++;
++		}
++		precvpriv->precv_buf = NULL;
++	}
++
++	if (precvpriv->pallocated_recv_buf) {
++		n = NR_RECVBUFF * sizeof(struct recv_buf) + 4;
++		rtw_mfree(precvpriv->pallocated_recv_buf, n);
++		precvpriv->pallocated_recv_buf = NULL;
++	}
++
++exit:
++	return res;
++}
++
++/*
++ * Free recv private variable of hardware dependent
++ * 1. recv buf
++ * 2. recv tasklet
++ *
++ */
++void rtl8723ds_free_recv_priv(PADAPTER padapter)
++{
++	u32			i, n;
++	struct recv_priv	*precvpriv;
++	struct recv_buf		*precvbuf;
++
++
++	precvpriv = &padapter->recvpriv;
++
++	/* 3 1. kill tasklet */
++#ifdef PLATFORM_LINUX
++	tasklet_kill(&precvpriv->recv_tasklet);
++#endif
++
++	/* 3 2. free all recv buffers */
++	precvbuf = (struct recv_buf *)precvpriv->precv_buf;
++	if (precvbuf) {
++		n = NR_RECVBUFF;
++		precvpriv->free_recv_buf_queue_cnt = 0;
++		for (i = 0; i < n ; i++) {
++			rtw_list_delete(&precvbuf->list);
++			rtw_os_recvbuf_resource_free(padapter, precvbuf);
++			freerecvbuf(precvbuf);
++			precvbuf++;
++		}
++		precvpriv->precv_buf = NULL;
++	}
++
++	if (precvpriv->pallocated_recv_buf) {
++		n = NR_RECVBUFF * sizeof(struct recv_buf) + 4;
++		rtw_mfree(precvpriv->pallocated_recv_buf, n);
++		precvpriv->pallocated_recv_buf = NULL;
++	}
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/sdio/rtl8723ds_xmit.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/sdio/rtl8723ds_xmit.c
+new file mode 100644
+index 000000000..84c91fec7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/sdio/rtl8723ds_xmit.c
+@@ -0,0 +1,797 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTL8723DS_XMIT_C_
++
++#include <rtl8723d_hal.h>
++
++static u8 rtw_sdio_wait_enough_TxOQT_space(PADAPTER padapter, u8 agg_num)
++{
++	u32 n = 0;
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++	while (pHalData->SdioTxOQTFreeSpace < agg_num) {
++		if (RTW_CANNOT_RUN(padapter)) {
++			RTW_INFO("%s: bSurpriseRemoved or bDriverStopped (wait TxOQT)\n", __func__);
++			return _FALSE;
++		}
++
++		HalQueryTxOQTBufferStatus8723DSdio(padapter);
++
++		if ((++n % 60) == 0) {
++			if ((n % 300) == 0) {
++				RTW_INFO("%s(%d): QOT free space(%d), agg_num: %d\n",
++					__func__, n, pHalData->SdioTxOQTFreeSpace, agg_num);
++			}
++			rtw_msleep_os(1);
++			/* yield(); */
++		}
++	}
++
++	pHalData->SdioTxOQTFreeSpace -= agg_num;
++
++	/* if (n > 1) */
++	/*	++priv->pshare->nr_out_of_txoqt_space; */
++
++	return _TRUE;
++}
++
++s32 _dequeue_writeport(PADAPTER padapter)
++{
++	#if defined(DBG_TX_FREE_PAGE) || defined(CONFIG_SDIO_TX_ENABLE_AVAL_INT)
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
++	#endif
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
++	struct xmit_buf *pxmitbuf;
++	u8	PageIdx = 0;
++	u32	deviceId;
++#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
++	u8	bUpdatePageNum = _FALSE;
++#else
++	u32	polling_num = 0;
++#endif
++
++	pxmitbuf = select_and_dequeue_pending_xmitbuf(padapter);
++
++	if (pxmitbuf == NULL)
++		return _TRUE;
++
++	deviceId = ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr);
++
++	/* translate fifo addr to queue index */
++	switch (deviceId) {
++	case WLAN_TX_HIQ_DEVICE_ID:
++		PageIdx = HI_QUEUE_IDX;
++		break;
++
++	case WLAN_TX_MIQ_DEVICE_ID:
++		PageIdx = MID_QUEUE_IDX;
++		break;
++
++	case WLAN_TX_LOQ_DEVICE_ID:
++		PageIdx = LOW_QUEUE_IDX;
++		break;
++	}
++
++query_free_page:
++	/* check if hardware tx fifo page is enough */
++	if (_FALSE == rtw_hal_sdio_query_tx_freepage(padapter, PageIdx, pxmitbuf->pg_num)) {
++		if (RTW_CANNOT_RUN(padapter))
++			goto free_xmitbuf;
++#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
++		if (!bUpdatePageNum) {
++			rtw_hal_sdio_avail_page_threshold_en(padapter, PageIdx, pxmitbuf->pg_num);
++			/* Total number of page is NOT available, so update current FIFO status */
++			HalQueryTxBufferStatus8723DSdio(padapter);
++			bUpdatePageNum = _TRUE;
++			goto query_free_page;
++		} else {
++			bUpdatePageNum = _FALSE;
++			enqueue_pending_xmitbuf_to_head(pxmitpriv, pxmitbuf);
++			#ifdef DBG_TX_FREE_PAGE
++			RTW_INFO("DQWP page not enough, len:%d, agg:%d, req %s:%u, cur H:%u, M:%u, L:%u, P:%u\n"
++				, pxmitbuf->len, pxmitbuf->agg_num
++				, sdio_tx_queue_str(PageIdx), pxmitbuf->pg_num
++				, hal_data->SdioTxFIFOFreePage[HI_QUEUE_IDX]
++				, hal_data->SdioTxFIFOFreePage[MID_QUEUE_IDX]
++				, hal_data->SdioTxFIFOFreePage[LOW_QUEUE_IDX]
++				, hal_data->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]
++			);
++			#endif
++			return _TRUE;
++		}
++#else /* CONFIG_SDIO_TX_ENABLE_AVAL_INT */
++		polling_num++;
++		if ((polling_num % 0x10) == 0) {
++			enqueue_pending_xmitbuf_to_head(pxmitpriv, pxmitbuf);
++			#ifdef DBG_TX_FREE_PAGE
++			RTW_INFO("DQWP FIFO starvation!(%d), len:%u, agg:%u, req %s:%u, cur H:%u, M:%u, L:%u, P:%u\n"
++				, polling_num, pxmitbuf->len, pxmitbuf->agg_num
++				, sdio_tx_queue_str(PageIdx), pxmitbuf->pg_num
++				, hal_data->SdioTxFIFOFreePage[HI_QUEUE_IDX]
++				, hal_data->SdioTxFIFOFreePage[MID_QUEUE_IDX]
++				, hal_data->SdioTxFIFOFreePage[LOW_QUEUE_IDX]
++				, hal_data->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]
++			);
++			#endif
++			rtw_usleep_os(50);
++			return _FALSE;
++		}
++
++		/* Total number of page is NOT available, so update current FIFO status */
++		HalQueryTxBufferStatus8723DSdio(padapter);
++		goto query_free_page;
++#endif /* CONFIG_SDIO_TX_ENABLE_AVAL_INT */
++	}
++
++#ifdef CONFIG_LPS_POFF
++	if (rtl8723d_lps_poff_get_txbndy_status(padapter) == _TRUE) {
++		RTW_INFO("%s: enqueue xmitbuf to pending queue head~~~\n",
++			 __func__);
++		enqueue_pending_xmitbuf_to_head(pxmitpriv, pxmitbuf);
++		return _TRUE;
++	}
++#endif
++
++	if (rtw_sdio_wait_enough_TxOQT_space(padapter, pxmitbuf->agg_num) == _FALSE)
++		goto free_xmitbuf;
++
++#ifdef CONFIG_CHECK_LEAVE_LPS
++	#ifdef CONFIG_LPS_CHK_BY_TP
++	if (!adapter_to_pwrctl(padapter)->lps_chk_by_tp)
++	#endif
++		traffic_check_for_leave_lps(padapter, _TRUE, pxmitbuf->agg_num);
++#endif
++	#ifdef DBG_TX_FREE_PAGE
++	RTW_INFO("DQWP write, %s:%u\n", sdio_tx_queue_str(PageIdx), pxmitbuf->pg_num);
++	#endif
++
++	rtw_write_port(padapter, deviceId, pxmitbuf->len, (u8 *)pxmitbuf);
++
++	rtw_hal_sdio_update_tx_freepage(padapter, PageIdx, pxmitbuf->pg_num);
++	#ifdef DBG_TX_FREE_PAGE
++	RTW_INFO("DQWP write done, cur H:%u, M:%u, L:%u, P:%u\n"
++		, hal_data->SdioTxFIFOFreePage[HI_QUEUE_IDX]
++		, hal_data->SdioTxFIFOFreePage[MID_QUEUE_IDX]
++		, hal_data->SdioTxFIFOFreePage[LOW_QUEUE_IDX]
++		, hal_data->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]
++	);
++	#endif
++
++free_xmitbuf:
++	/* rtw_free_xmitframe(pxmitpriv, pframe); */
++	/* pxmitbuf->priv_data = NULL; */
++	rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
++	#ifdef SDIO_FREE_XMIT_BUF_SEMA
++	if (pxmitbuf->buf_tag == XMITBUF_DATA)
++		rtw_sdio_free_xmitbuf_sema_up(pxmitpriv);
++	#endif
++#if 0 /* improve TX/RX throughput balance */
++	{
++		PSDIO_DATA psdio;
++		struct sdio_func *func;
++		static u8 i = 0;
++		u32 sdio_hisr;
++		u8 j;
++
++		psdio = &adapter_to_dvobj(padapter)->intf_data;
++		func = psdio->func;
++
++		if (i == 2) {
++			j = 0;
++			while (j < 10) {
++				sdio_hisr = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HISR);
++				sdio_hisr &= GET_HAL_DATA(padapter)->sdio_himr;
++				if (sdio_hisr & SDIO_HISR_RX_REQUEST) {
++					sdio_claim_host(func);
++					sd_int_hdl(GET_PRIMARY_ADAPTER(padapter));
++					sdio_release_host(func);
++				} else
++					break;
++				j++;
++			}
++			i = 0;
++		} else
++			i++;
++	}
++#endif
++
++#ifdef CONFIG_SDIO_TX_TASKLET
++	tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
++#endif
++
++	return _FALSE;
++}
++
++/*
++ * Description
++ *	Transmit xmitbuf to hardware tx fifo
++ *
++ * Return
++ *	_SUCCESS	ok
++ *	_FAIL		something error
++ */
++s32 rtl8723ds_xmit_buf_handler(PADAPTER padapter)
++{
++	struct xmit_priv *pxmitpriv;
++	u8	queue_empty;
++	s32	ret;
++
++
++	pxmitpriv = &padapter->xmitpriv;
++
++	ret = _rtw_down_sema(&pxmitpriv->xmit_sema);
++	if (_FAIL == ret) {
++		RTW_ERR("%s: down SdioXmitBufSema fail!\n", __func__);
++		return _FAIL;
++	}
++
++	if (RTW_CANNOT_RUN(padapter)) {
++		RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n",
++			FUNC_ADPT_ARG(padapter),
++			rtw_is_drv_stopped(padapter) ? "True" : "False",
++			rtw_is_surprise_removed(padapter) ? "True" : "False");
++		return _FAIL;
++	}
++
++	if (rtw_mi_check_pending_xmitbuf(padapter) == 0)
++		return _SUCCESS;
++
++#ifdef CONFIG_LPS_LCLK
++	ret = rtw_register_tx_alive(padapter);
++	if (ret != _SUCCESS)
++		return _SUCCESS;
++#endif
++	do {
++		queue_empty = rtw_mi_dequeue_writeport(padapter);
++	} while (!queue_empty);
++#ifdef CONFIG_LPS_LCLK
++	rtw_unregister_tx_alive(padapter);
++#endif
++
++	return _SUCCESS;
++}
++
++/*
++ * Description:
++ *	Aggregation packets and send to hardware
++ *
++ * Return:
++ *	0	Success
++ *	-1	Hardware resource(TX FIFO) not ready
++ *	-2	Software resource(xmitbuf) not ready
++ */
++static s32 xmit_xmitframes(PADAPTER padapter, struct xmit_priv *pxmitpriv)
++{
++	s32 err, ret;
++	u32 k = 0;
++	struct hw_xmit *hwxmits, *phwxmit;
++	u8 no_res, idx, hwentry;
++	_irqL irql;
++	struct tx_servq *ptxservq;
++	_list *sta_plist, *sta_phead, *frame_plist, *frame_phead;
++	struct xmit_frame *pxmitframe;
++	_queue *pframe_queue;
++	struct xmit_buf *pxmitbuf;
++	u32 txlen, max_xmit_len, page_size;
++	u8 txdesc_size = TXDESC_SIZE;
++	int inx[4];
++	u8 pre_qsel = 0xFF, next_qsel = 0xFF;
++	u8 single_sta_in_queue = _FALSE;
++#ifdef SDIO_FREE_XMIT_BUF_SEMA
++	u32 consume;
++#endif
++	err = 0;
++	no_res = _FALSE;
++	hwxmits = pxmitpriv->hwxmits;
++	hwentry = pxmitpriv->hwxmit_entry;
++	ptxservq = NULL;
++	pxmitframe = NULL;
++	pframe_queue = NULL;
++	pxmitbuf = NULL;
++
++	rtw_hal_get_def_var(padapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
++
++	if (padapter->registrypriv.wifi_spec == 1) {
++		for (idx = 0; idx < 4; idx++)
++			inx[idx] = pxmitpriv->wmm_para_seq[idx];
++	} else {
++		inx[0] = 0;
++		inx[1] = 1;
++		inx[2] = 2;
++		inx[3] = 3;
++	}
++
++	/* 0(VO), 1(VI), 2(BE), 3(BK) */
++	for (idx = 0; idx < hwentry; idx++) {
++		phwxmit = hwxmits + inx[idx];
++		#ifdef SDIO_FREE_XMIT_BUF_SEMA
++		consume = 0;
++		#endif
++		if ((check_pending_xmitbuf(pxmitpriv) == _TRUE) && (padapter->mlmepriv.LinkDetectInfo.bHigherBusyTxTraffic == _TRUE)) {
++			if ((phwxmit->accnt > 0) && (phwxmit->accnt < 5)) {
++				err = RTW_TX_WAIT_MORE_FRAME;
++				break;
++			}
++		}
++
++		max_xmit_len = rtw_hal_get_sdio_tx_max_length(padapter, inx[idx]);
++
++		_enter_critical_bh(&pxmitpriv->lock, &irql);
++
++		sta_phead = get_list_head(phwxmit->sta_queue);
++		sta_plist = get_next(sta_phead);
++		/* because stop_sta_xmit may delete sta_plist at any time */
++		/* so we should add lock here, or while loop can not exit */
++
++		single_sta_in_queue = rtw_end_of_queue_search(sta_phead, get_next(sta_plist));
++
++		while (rtw_end_of_queue_search(sta_phead, sta_plist) == _FALSE) {
++			ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending);
++			sta_plist = get_next(sta_plist);
++
++#ifdef DBG_XMIT_BUF
++			RTW_INFO("%s idx:%d hwxmit_pkt_num:%d ptxservq_pkt_num:%d\n", __func__, idx, phwxmit->accnt, ptxservq->qcnt);
++			RTW_INFO("%s free_xmit_extbuf_cnt=%d free_xmitbuf_cnt=%d free_xmitframe_cnt=%d\n",
++				__func__, pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xmitbuf_cnt,
++				 pxmitpriv->free_xmitframe_cnt);
++#endif
++			pframe_queue = &ptxservq->sta_pending;
++
++			frame_phead = get_list_head(pframe_queue);
++
++			while (rtw_is_list_empty(frame_phead) == _FALSE) {
++				frame_plist = get_next(frame_phead);
++				pxmitframe = LIST_CONTAINOR(frame_plist, struct xmit_frame, list);
++
++				/* check xmit_buf size enough or not */
++				txlen = txdesc_size + rtw_wlan_pkt_size(pxmitframe);
++				next_qsel = pxmitframe->attrib.qsel;
++				if ((NULL == pxmitbuf) ||
++				    (pxmitbuf->pg_num + PageNum(txlen, page_size) > PageNum(max_xmit_len, page_size))
++				    || (k >= (rtw_hal_sdio_max_txoqt_free_space(padapter) - 1))
++				    || ((k != 0) && (_FAIL == rtw_hal_busagg_qsel_check(padapter, pre_qsel, next_qsel)))
++				   ) {
++					if (pxmitbuf) {
++						/* pxmitbuf->priv_data will be NULL, and will crash here */
++						if (pxmitbuf->len > 0 && pxmitbuf->priv_data) {
++							struct xmit_frame *pframe;
++
++							pframe = (struct xmit_frame *)pxmitbuf->priv_data;
++							pframe->agg_num = k;
++							pxmitbuf->agg_num = k;
++							rtl8723d_update_txdesc(pframe, pframe->buf_addr);
++							rtw_free_xmitframe(pxmitpriv, pframe);
++							pxmitbuf->priv_data = NULL;
++							enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
++							/* can not yield under lock */
++
++							/* rtw_yield_os(); */
++							if (single_sta_in_queue == _FALSE) {
++								/* break the loop in case there is more than one sta in this ac queue */
++								pxmitbuf = NULL;
++								err = RTW_TX_BALANCE;
++								break;
++							}
++						} else
++						{
++							rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
++							#ifdef SDIO_FREE_XMIT_BUF_SEMA
++							consume--;
++							#endif
++						}
++					}
++
++					pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
++					if (pxmitbuf == NULL) {
++#ifdef DBG_XMIT_BUF
++						RTW_ERR("%s: xmit_buf is not enough!\n", __func__);
++#endif
++						err = RTW_XBUF_UNAVAIL;
++						break;
++					}
++					#ifdef SDIO_FREE_XMIT_BUF_SEMA
++					consume++;
++					#endif
++					k = 0;
++				}
++
++				/* ok to send, remove frame from queue */
++#ifdef CONFIG_AP_MODE
++				if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
++					if ((pxmitframe->attrib.psta->state & WIFI_SLEEP_STATE) &&
++					    (pxmitframe->attrib.triggered == 0)) {
++						RTW_INFO("%s: one not triggered pkt in queue when this STA sleep, break and goto next sta\n", __func__);
++						break;
++					}
++				}
++#endif
++				rtw_list_delete(&pxmitframe->list);
++				ptxservq->qcnt--;
++				phwxmit->accnt--;
++
++				if (k == 0) {
++					pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);
++					pxmitbuf->priv_data = (u8 *)pxmitframe;
++				}
++
++				/* coalesce the xmitframe to xmitbuf */
++				pxmitframe->pxmitbuf = pxmitbuf;
++				pxmitframe->buf_addr = pxmitbuf->ptail;
++
++				ret = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
++				if (ret == _FAIL) {
++					RTW_ERR("%s: coalesce FAIL!", __func__);
++					/* Todo: error handler */
++				} else {
++					k++;
++					if (k != 1)
++						rtl8723d_update_txdesc(pxmitframe, pxmitframe->buf_addr);
++					rtw_count_tx_stats(padapter, pxmitframe, pxmitframe->attrib.last_txcmdsz);
++					pre_qsel = pxmitframe->attrib.qsel;
++					txlen = txdesc_size + pxmitframe->attrib.last_txcmdsz;
++					pxmitframe->pg_num = (txlen + 127) / 128;
++					pxmitbuf->pg_num += (txlen + 127) / 128;
++					/* if (k != 1) */
++					/*	((struct xmit_frame*)pxmitbuf->priv_data)->pg_num += pxmitframe->pg_num; */
++					pxmitbuf->ptail += _RND(txlen, 8); /* round to 8 bytes alignment */
++					pxmitbuf->len = _RND(pxmitbuf->len, 8) + txlen;
++				}
++
++				if (k != 1)
++					rtw_free_xmitframe(pxmitpriv, pxmitframe);
++				pxmitframe = NULL;
++			}
++
++			if (_rtw_queue_empty(pframe_queue) == _TRUE)
++				rtw_list_delete(&ptxservq->tx_pending);
++			else if (err == RTW_TX_BALANCE) {
++				/* Re-arrange the order of stations in this ac queue to balance the service for these stations */
++				rtw_list_delete(&ptxservq->tx_pending);
++				rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(phwxmit->sta_queue));
++			}
++
++			if (err)
++				break;
++		}
++		_exit_critical_bh(&pxmitpriv->lock, &irql);
++		#ifdef SDIO_FREE_XMIT_BUF_SEMA
++		#ifdef DBG_SDIO_FREE_XMIT_BUF_SEMA
++			if (consume)
++				RTW_INFO(FUNC_ADPT_FMT" acq[%u], consume:%u\n", FUNC_ADPT_ARG(padapter), inx[idx], consume);
++		#endif
++			while (consume--)
++				rtw_sdio_free_xmitbuf_sema_down(pxmitpriv);
++		#endif
++		/* dump xmit_buf to hw tx fifo */
++		if (pxmitbuf) {
++
++			if (pxmitbuf->len > 0) {
++				struct xmit_frame *pframe;
++
++				pframe = (struct xmit_frame *)pxmitbuf->priv_data;
++				pframe->agg_num = k;
++				pxmitbuf->agg_num = k;
++				rtl8723d_update_txdesc(pframe, pframe->buf_addr);
++				rtw_free_xmitframe(pxmitpriv, pframe);
++				pxmitbuf->priv_data = NULL;
++				enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
++				rtw_yield_os();
++			} else{
++				rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
++				#ifdef SDIO_FREE_XMIT_BUF_SEMA
++				rtw_sdio_free_xmitbuf_sema_up(pxmitpriv);
++				#endif
++			}
++			pxmitbuf = NULL;
++		}
++
++		if (err == RTW_XBUF_UNAVAIL)
++			break;
++	}
++
++	return err;
++}
++
++/*
++ * Description
++ *	Transmit xmitframe from queue
++ *
++ * Return
++ *	_SUCCESS	ok
++ *	_FAIL		something error
++ */
++s32 rtl8723ds_xmit_handler(PADAPTER padapter)
++{
++	struct xmit_priv *pxmitpriv;
++	s32 ret;
++	_irqL irql;
++
++
++	pxmitpriv = &padapter->xmitpriv;
++
++	ret = _rtw_down_sema(&pxmitpriv->SdioXmitSema);
++	if (_FAIL == ret) {
++		RTW_ERR("%s: down sema fail!\n", __func__);
++		return _FAIL;
++	}
++
++next:
++	if (RTW_CANNOT_RUN(padapter)) {
++		RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n",
++			FUNC_ADPT_ARG(padapter),
++			rtw_is_drv_stopped(padapter) ? "True" : "False",
++			rtw_is_surprise_removed(padapter) ? "True" : "False");
++		return _FAIL;
++	}
++
++	_enter_critical_bh(&pxmitpriv->lock, &irql);
++	ret = rtw_txframes_pending(padapter);
++	_exit_critical_bh(&pxmitpriv->lock, &irql);
++	if (ret == 0)
++		return _SUCCESS;
++
++	/* dequeue frame and write to hardware */
++
++	ret = xmit_xmitframes(padapter, pxmitpriv);
++	if (ret == RTW_XBUF_UNAVAIL
++		|| ret == RTW_TX_WAIT_MORE_FRAME
++	) {
++	#ifdef SDIO_FREE_XMIT_BUF_SEMA
++		if (ret == RTW_XBUF_UNAVAIL) {
++			rtw_sdio_free_xmitbuf_sema_down(pxmitpriv);
++			rtw_sdio_free_xmitbuf_sema_up(pxmitpriv);
++			goto next;
++		}
++	#endif
++
++		if (padapter->registrypriv.wifi_spec)
++			rtw_msleep_os(1);
++		else {
++		#ifdef CONFIG_REDUCE_TX_CPU_LOADING
++			rtw_msleep_os(1);
++		#else
++			rtw_yield_os();
++		#endif
++		}
++		goto next;
++	}
++	_enter_critical_bh(&pxmitpriv->lock, &irql);
++	ret = rtw_txframes_pending(padapter);
++	_exit_critical_bh(&pxmitpriv->lock, &irql);
++	if (ret == 1) {
++#ifdef CONFIG_REDUCE_TX_CPU_LOADING
++		rtw_msleep_os(1);
++#endif
++		goto next;
++	}
++
++	return _SUCCESS;
++}
++
++thread_return rtl8723ds_xmit_thread(thread_context context)
++{
++	s32 ret;
++	PADAPTER padapter;
++	struct xmit_priv *pxmitpriv;
++	u8 thread_name[20] = {0};
++#ifdef RTW_XMIT_THREAD_HIGH_PRIORITY_AGG
++#ifdef PLATFORM_LINUX
++	struct sched_param param = { .sched_priority = 1 };
++
++	sched_setscheduler(current, SCHED_FIFO, &param);
++#endif /* PLATFORM_LINUX */
++#endif /* RTW_XMIT_THREAD_HIGH_PRIORITY_AGG */
++
++	ret = _SUCCESS;
++	padapter = (PADAPTER)context;
++	pxmitpriv = &padapter->xmitpriv;
++
++	rtw_sprintf(thread_name, 20, "RTWHALXT-"ADPT_FMT, ADPT_ARG(padapter));
++	thread_enter(thread_name);
++
++	RTW_INFO("start "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++	do {
++		ret = rtl8723ds_xmit_handler(padapter);
++		flush_signals_thread();
++	} while (_SUCCESS == ret);
++
++	RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(padapter));
++
++	rtw_thread_wait_stop();
++
++	return 0;
++}
++
++s32 rtl8723ds_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe)
++{
++	s32 ret = _SUCCESS;
++	struct pkt_attrib *pattrib;
++	struct xmit_buf *pxmitbuf;
++	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
++	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
++	u8 *pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	u8 txdesc_size = TXDESC_SIZE;
++
++
++	pattrib = &pmgntframe->attrib;
++	pxmitbuf = pmgntframe->pxmitbuf;
++
++	rtl8723d_update_txdesc(pmgntframe, pmgntframe->buf_addr);
++
++	pxmitbuf->len = txdesc_size + pattrib->last_txcmdsz;
++	/* pmgntframe->pg_num = (pxmitbuf->len + 127)/128; // 128 is tx page size */
++	pxmitbuf->pg_num = (pxmitbuf->len + 127) / 128; /* 128 is tx page size */
++	pxmitbuf->ptail = pmgntframe->buf_addr + pxmitbuf->len;
++	pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pmgntframe);
++
++	rtw_count_tx_stats(padapter, pmgntframe, pattrib->last_txcmdsz);
++
++	rtw_free_xmitframe(pxmitpriv, pmgntframe);
++
++	pxmitbuf->priv_data = NULL;
++
++	if (get_frame_sub_type(pframe) == WIFI_BEACON ||
++	    pxmitbuf->buf_tag == XMITBUF_CMD) {
++
++#ifdef CONFIG_LPS_POFF
++		if (rtl8723d_lps_poff_get_txbndy_status(padapter) == _TRUE) {
++			RTW_INFO("%s: enqueue xmitbuf to pending queue ~~~\n",
++				 __func__);
++			enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
++			return ret;
++		}
++#endif
++		ret = rtw_write_port(padapter, pdvobjpriv->Queue2Pipe[pxmitbuf->ff_hwaddr], pxmitbuf->len, (u8 *)pxmitbuf);
++		if (ret != _SUCCESS)
++			rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_WRITE_PORT_ERR);
++
++		rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
++	} else
++		enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
++
++	return ret;
++}
++
++/*
++ * Description:
++ *	Handle xmitframe(packet) come from rtw_xmit()
++ *
++ * Return:
++ *	_TRUE	dump packet directly ok
++ *	_FALSE	enqueue, temporary can't transmit packets to hardware
++ */
++s32 rtl8723ds_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe)
++{
++	struct xmit_priv *pxmitpriv;
++	_irqL irql;
++	s32 err;
++
++
++	pxmitframe->attrib.qsel = pxmitframe->attrib.priority;
++	pxmitpriv = &padapter->xmitpriv;
++
++#ifdef CONFIG_80211N_HT
++	if ((pxmitframe->frame_tag == DATA_FRAMETAG) &&
++	    (pxmitframe->attrib.ether_type != 0x0806) &&
++	    (pxmitframe->attrib.ether_type != 0x888e) &&
++	    (pxmitframe->attrib.dhcp_pkt != 1)) {
++		rtw_issue_addbareq_cmd(padapter, pxmitframe, _TRUE);
++	}
++#endif
++
++	_enter_critical_bh(&pxmitpriv->lock, &irql);
++	err = rtw_xmitframe_enqueue(padapter, pxmitframe);
++	_exit_critical_bh(&pxmitpriv->lock, &irql);
++	if (err != _SUCCESS) {
++		rtw_free_xmitframe(pxmitpriv, pxmitframe);
++
++		pxmitpriv->tx_drop++;
++		return _TRUE;
++	}
++
++	_rtw_up_sema(&pxmitpriv->SdioXmitSema);
++
++	return _FALSE;
++}
++
++s32	rtl8723ds_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
++{
++	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
++	s32 err;
++
++	err = rtw_xmitframe_enqueue(padapter, pxmitframe);
++	if (err != _SUCCESS) {
++		rtw_free_xmitframe(pxmitpriv, pxmitframe);
++
++		pxmitpriv->tx_drop++;
++	} else {
++#ifdef CONFIG_SDIO_TX_TASKLET
++		tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
++#else
++		_rtw_up_sema(&pxmitpriv->SdioXmitSema);
++#endif
++	}
++
++	return err;
++
++}
++
++/*
++ * Return
++ *	_SUCCESS	start thread ok
++ *	_FAIL		start thread fail
++ *
++ */
++s32 rtl8723ds_init_xmit_priv(PADAPTER padapter)
++{
++	struct xmit_priv *xmitpriv = &padapter->xmitpriv;
++	PHAL_DATA_TYPE phal;
++
++
++	phal = GET_HAL_DATA(padapter);
++
++	_rtw_spinlock_init(&phal->SdioTxFIFOFreePageLock);
++	_rtw_init_sema(&xmitpriv->SdioXmitSema, 0);
++	#ifdef SDIO_FREE_XMIT_BUF_SEMA
++	_rtw_init_sema(&xmitpriv->sdio_free_xmitbuf_sema, xmitpriv->free_xmitbuf_cnt);
++	#endif
++	return _SUCCESS;
++}
++
++void rtl8723ds_free_xmit_priv(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE phal;
++	struct xmit_priv *pxmitpriv;
++	struct xmit_buf *pxmitbuf;
++	_queue *pqueue;
++	_list *plist, *phead;
++	_list tmplist;
++	_irqL irql;
++
++
++	phal = GET_HAL_DATA(padapter);
++	pxmitpriv = &padapter->xmitpriv;
++	pqueue = &pxmitpriv->pending_xmitbuf_queue;
++	phead = get_list_head(pqueue);
++	_rtw_init_listhead(&tmplist);
++
++	_enter_critical_bh(&pqueue->lock, &irql);
++	if (_rtw_queue_empty(pqueue) == _FALSE) {
++		/* Insert tmplist to end of queue, and delete phead */
++		/* then tmplist become head of queue. */
++		rtw_list_insert_tail(&tmplist, phead);
++		rtw_list_delete(phead);
++	}
++	_exit_critical_bh(&pqueue->lock, &irql);
++
++	phead = &tmplist;
++	while (rtw_is_list_empty(phead) == _FALSE) {
++		plist = get_next(phead);
++		rtw_list_delete(plist);
++
++		pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
++		rtw_free_xmitframe(pxmitpriv, (struct xmit_frame *)pxmitbuf->priv_data);
++		pxmitbuf->priv_data = NULL;
++		rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
++		#ifdef SDIO_FREE_XMIT_BUF_SEMA
++		if (pxmitbuf->buf_tag == XMITBUF_DATA)
++			rtw_sdio_free_xmitbuf_sema_up(pxmitpriv);
++		#endif
++	}
++	_rtw_spinlock_free(&phal->SdioTxFIFOFreePageLock);
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/sdio/sdio_halinit.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/sdio/sdio_halinit.c
+new file mode 100644
+index 000000000..6efd46220
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/sdio/sdio_halinit.c
+@@ -0,0 +1,1761 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _SDIO_HALINIT_C_
++
++#include <rtl8723d_hal.h>
++#include "hal_com_h2c.h"
++
++/*
++ * Description:
++ *	Call power on sequence to enable card
++ *
++ * Return:
++ *	_SUCCESS	enable success
++ *	_FAIL		enable fail
++ */
++static u8 CardEnable(PADAPTER padapter)
++{
++	u8 val8 = 0;
++	u8 bMacPwrCtrlOn;
++	u8 ret = _FAIL;
++
++	bMacPwrCtrlOn = _FALSE;
++	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++	if (bMacPwrCtrlOn == _FALSE) {
++		/* RSV_CTRL 0x1C[7:0] = 0x00 */
++		/* unlock ISO/CLK/Power control register */
++		val8 = rtw_read8(padapter, REG_WLLPS_CTRL + 3);
++
++		if (val8 & BIT(1))
++			RTW_INFO("%s: LP-LPS: %02x\n", __func__, val8);
++
++		rtw_write8(padapter, REG_RSV_CTRL, 0x0);
++
++		ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723D_card_enable_flow);
++		if (ret == _SUCCESS) {
++			u8 bMacPwrCtrlOn = _TRUE;
++
++			rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++		}
++	} else
++		ret = _SUCCESS;
++
++	return ret;
++}
++
++/* static */
++u32 _InitPowerOn_8723DS(PADAPTER padapter)
++{
++	u8 value8;
++	u16 value16;
++	u32 value32;
++	u8 ret;
++	u8 pwron_chk_cnt = 0;
++	/*	u8 bMacPwrCtrlOn; */
++
++_init_power_on:
++
++#if 1
++	/* all of these MUST be configured before power on */
++#ifdef CONFIG_XTAL_26M
++	/* Config PLL Reference CLK, */
++	/* Change crystal to 26M, APLL_FREF_SEL = 4b'0101 */
++	/* APLL_FREF_SEL[0]=1b'1 */
++	value8 = rtw_read8(padapter, REG_AFE_PLL_CTRL);
++	value8 |= BIT(2);
++	rtw_write8(padapter, REG_AFE_PLL_CTRL, value8);
++	/* APLL_FREF_SEL[2:1]=2b'10 */
++	value8 = rtw_read8(padapter, REG_AFE_CTRL_4_8723D + 1);
++	value8 &= ~(BIT(1) | BIT(0));
++	value8 |= BIT(1);
++	rtw_write16(padapter, REG_AFE_CTRL_4_8723D + 1, value8);
++	/* APLL_FREF_SEL[3]=1b'0 */
++	value8 = rtw_read8(padapter, REG_AFE_CTRL_4_8723D);
++	value8 &= ~BIT(7);
++	rtw_write16(padapter, REG_AFE_CTRL_4_8723D, value8);
++#endif /* CONFIG_XTAL_26M */
++
++#ifdef CONFIG_EXT_CLK
++	/* Use external crystal(XTAL) */
++	value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723D + 2);
++	value8 |=  BIT(7);
++	rtw_write8(padapter, REG_PAD_CTRL1_8723D + 2, value8);
++
++	/* CLK_REQ High active or Low Active */
++	/* Request GPIO polarity: */
++	/* 0: low active */
++	/* 1: high active */
++	value8 = rtw_read8(padapter, REG_MULTI_FUNC_CTRL + 1);
++	value8 |= BIT(5);
++	rtw_write8(padapter, REG_MULTI_FUNC_CTRL + 1, value8);
++#endif /* CONFIG_EXT_CLK */
++#endif /* all of these MUST be configured before power on */
++
++	/* only cmd52 can be used before power on(card enable) */
++	ret = CardEnable(padapter);
++	if (ret == _FALSE) {
++		return _FAIL;
++	}
++
++	/* Radio-Off Pin Trigger */
++	value8 = rtw_read8(padapter, REG_GPIO_INTM + 1);
++	value8 |= BIT(1); /* Enable falling edge triggering interrupt */
++	rtw_write8(padapter, REG_GPIO_INTM + 1, value8);
++	value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2 + 1);
++	value8 |= BIT(1);
++	rtw_write8(padapter, REG_GPIO_IO_SEL_2 + 1, value8);
++
++	/* Enable power down and GPIO interrupt */
++	value16 = rtw_read16(padapter, REG_APS_FSMCO);
++	value16 |= EnPDN; /* Enable HW power down and RF on */
++	rtw_write16(padapter, REG_APS_FSMCO, value16);
++
++	/* Enable CMD53 R/W Operation
++	*	bMacPwrCtrlOn = _TRUE;
++	*	rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); */
++
++	rtw_write8(padapter, REG_CR, 0x00);
++	/* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
++	value16 = rtw_read16(padapter, REG_CR);
++	value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
++		    | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
++	rtw_write16(padapter, REG_CR, value16);
++
++
++	/* PowerOnCheck() */
++	ret = sdio_power_on_check(padapter);
++	pwron_chk_cnt++;
++	if (_FAIL == ret) {
++		if (pwron_chk_cnt > 1) {
++			RTW_INFO("Failed to init Power On!\n");
++			return _FAIL;
++		}
++		RTW_INFO("Power on Fail! do it again\n");
++		goto _init_power_on;
++	} else {
++		/* MAC team suggest to keep ana clock at 12MHz  0x04[22] = 1 */
++		value8 = rtw_read8(padapter, REG_APS_FSMCO + 2);
++		value8 |= BIT(6);
++		rtw_write8(padapter, REG_APS_FSMCO + 2, value8);
++	}
++
++	value8 = rtw_read8(padapter, REG_SYS_CFG1_8723D + 1);
++	RTW_INFO("%s: %s\n", __func__,
++		(value8 & BIT3) ? "Test Mode" : "Normal Mode");
++
++	value8 = rtw_read8(padapter, REG_SYS_CFG1_8723D + 3);
++	RTW_INFO("%s: %s\n", __func__,
++		(value8 & BIT0) ? "LDO Mode" : "SPS Mode");
++
++	return _SUCCESS;
++}
++
++ 
++
++static void _InitQueueReservedPage(PADAPTER padapter)
++{
++	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
++	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
++	u32			outEPNum	= (u32)pHalData->OutEpNumber;
++	u32			numHQ		= 0;
++	u32			numLQ		= 0;
++	u32			numNQ		= 0;
++	u32			numPubQ;
++	u32			value32;
++	u8			value8;
++	BOOLEAN			bWiFiConfig	= pregistrypriv->wifi_spec;
++
++	if (pHalData->OutEpQueueSel & TX_SELE_HQ)
++		numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8723D : NORMAL_PAGE_NUM_HPQ_8723D;
++
++	if (pHalData->OutEpQueueSel & TX_SELE_LQ)
++		numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8723D : NORMAL_PAGE_NUM_LPQ_8723D;
++
++	/* NOTE: This step shall be proceed before writing REG_RQPN. */
++	if (pHalData->OutEpQueueSel & TX_SELE_NQ)
++		numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8723D : NORMAL_PAGE_NUM_NPQ_8723D;
++
++	numPubQ = TX_TOTAL_PAGE_NUMBER_8723D - numHQ - numLQ - numNQ;
++
++	value8 = (u8)_NPQ(numNQ);
++	rtw_write8(padapter, REG_RQPN_NPQ, value8);
++
++	/* TX DMA */
++	value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
++	rtw_write32(padapter, REG_RQPN, value32);
++
++	rtw_hal_set_sdio_tx_max_length(padapter, numHQ, numNQ, numLQ, numPubQ, SDIO_TX_DIV_NUM);
++
++#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
++	rtw_hal_sdio_avail_page_threshold_init(padapter);
++#endif
++}
++static void _InitTxBufferBoundary(PADAPTER padapter)
++{
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++#ifdef CONFIG_CONCURRENT_MODE
++	u8 val8;
++#endif /* CONFIG_CONCURRENT_MODE */
++
++	/* u16	txdmactrl; */
++	u8	txpktbuf_bndy;
++
++	if (!pregistrypriv->wifi_spec)
++		txpktbuf_bndy = TX_PAGE_BOUNDARY_8723D;
++	else {
++		/* for WMM */
++		txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8723D;
++	}
++
++	rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8723D, txpktbuf_bndy);
++	rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8723D, txpktbuf_bndy);
++	rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8723D, txpktbuf_bndy);
++	rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
++	rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy);
++
++#ifdef CONFIG_CONCURRENT_MODE
++	val8 = txpktbuf_bndy + BCNQ_PAGE_NUM_8723D + WOWLAN_PAGE_NUM_8723D;
++	rtw_write8(padapter, REG_BCNQ1_BDNY, val8);
++	rtw_write8(padapter, REG_DWBCN1_CTRL_8723D + 1, val8); /* BCN1_HEAD */
++
++	val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8723D + 2);
++	val8 |= BIT(1); /* BIT1- BIT_SW_BCN_SEL_EN */
++	rtw_write8(padapter, REG_DWBCN1_CTRL_8723D + 2, val8);
++#endif /* CONFIG_CONCURRENT_MODE */
++}
++
++static void
++_InitNormalChipRegPriority(
++		PADAPTER	Adapter,
++		u16		beQ,
++		u16		bkQ,
++		u16		viQ,
++		u16		voQ,
++		u16		mgtQ,
++		u16		hiQ
++)
++{
++	u16 value16		= (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
++
++	value16 |=	_TXDMA_BEQ_MAP(beQ)	| _TXDMA_BKQ_MAP(bkQ) |
++			_TXDMA_VIQ_MAP(viQ)	| _TXDMA_VOQ_MAP(voQ) |
++			_TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
++
++	rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
++}
++
++static void
++_InitNormalChipOneOutEpPriority(
++		PADAPTER Adapter
++)
++{
++	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
++
++	u16	value = 0;
++
++	switch (pHalData->OutEpQueueSel) {
++	case TX_SELE_HQ:
++		value = QUEUE_HIGH;
++		break;
++	case TX_SELE_LQ:
++		value = QUEUE_LOW;
++		break;
++	case TX_SELE_NQ:
++		value = QUEUE_NORMAL;
++		break;
++	default:
++		/* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
++		break;
++	}
++
++	_InitNormalChipRegPriority(Adapter,
++				   value,
++				   value,
++				   value,
++				   value,
++				   value,
++				   value
++				  );
++
++}
++
++static void
++_InitNormalChipTwoOutEpPriority(
++		PADAPTER Adapter
++)
++{
++	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
++	struct registry_priv *pregistrypriv = &Adapter->registrypriv;
++	u16			beQ, bkQ, viQ, voQ, mgtQ, hiQ;
++
++
++	u16	valueHi = 0;
++	u16	valueLow = 0;
++
++	switch (pHalData->OutEpQueueSel) {
++	case (TX_SELE_HQ | TX_SELE_LQ):
++		valueHi = QUEUE_HIGH;
++		valueLow = QUEUE_LOW;
++		break;
++	case (TX_SELE_NQ | TX_SELE_LQ):
++		valueHi = QUEUE_NORMAL;
++		valueLow = QUEUE_LOW;
++		break;
++	case (TX_SELE_HQ | TX_SELE_NQ):
++		valueHi = QUEUE_HIGH;
++		valueLow = QUEUE_NORMAL;
++		break;
++	default:
++		/* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
++		break;
++	}
++
++	if (!pregistrypriv->wifi_spec) {
++		beQ		= valueLow;
++		bkQ		= valueLow;
++		viQ		= valueHi;
++		voQ		= valueHi;
++		mgtQ	= valueHi;
++		hiQ		= valueHi;
++	} else { /* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
++		beQ		= valueLow;
++		bkQ		= valueHi;
++		viQ		= valueHi;
++		voQ		= valueLow;
++		mgtQ	= valueHi;
++		hiQ		= valueHi;
++	}
++
++	_InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
++
++}
++
++static void
++_InitNormalChipThreeOutEpPriority(
++		PADAPTER padapter
++)
++{
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++	u16			beQ, bkQ, viQ, voQ, mgtQ, hiQ;
++
++	if (!pregistrypriv->wifi_spec) { /* typical setting */
++		beQ		= QUEUE_LOW;
++		bkQ		= QUEUE_LOW;
++		viQ		= QUEUE_NORMAL;
++		voQ		= QUEUE_HIGH;
++		mgtQ	= QUEUE_HIGH;
++		hiQ		= QUEUE_HIGH;
++	} else { /* for WMM */
++		beQ		= QUEUE_LOW;
++		bkQ		= QUEUE_NORMAL;
++		viQ		= QUEUE_NORMAL;
++		voQ		= QUEUE_HIGH;
++		mgtQ	= QUEUE_HIGH;
++		hiQ		= QUEUE_HIGH;
++	}
++	_InitNormalChipRegPriority(padapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
++}
++
++static void
++_InitNormalChipQueuePriority(
++		PADAPTER Adapter
++)
++{
++	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
++
++	switch (pHalData->OutEpNumber) {
++	case 1:
++		_InitNormalChipOneOutEpPriority(Adapter);
++		break;
++	case 2:
++		_InitNormalChipTwoOutEpPriority(Adapter);
++		break;
++	case 3:
++		_InitNormalChipThreeOutEpPriority(Adapter);
++		break;
++	default:
++		/* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
++		break;
++	}
++
++
++}
++
++static void _InitQueuePriority(PADAPTER padapter)
++{
++	_InitNormalChipQueuePriority(padapter);
++}
++
++static void _InitPageBoundary(PADAPTER padapter)
++{
++	/* RX Page Boundary */
++	u16 rxff_bndy = RX_DMA_BOUNDARY_8723D;
++
++	rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
++}
++
++static void _InitTransferPageSize(PADAPTER padapter)
++{
++	/* Tx page size is always 128. */
++
++	u8 value8;
++
++	value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
++	rtw_write8(padapter, REG_PBP, value8);
++}
++
++void _InitDriverInfoSize(PADAPTER padapter, u8 drvInfoSize)
++{
++	rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize);
++}
++
++void _InitNetworkType(PADAPTER padapter)
++{
++	u32 value32;
++
++	value32 = rtw_read32(padapter, REG_CR);
++
++	/* TODO: use the other function to set network type
++	*	value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); */
++	value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
++
++	rtw_write32(padapter, REG_CR, value32);
++}
++
++void _InitWMACSetting(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE pHalData;
++	u16 value16;
++	u32 rcr;
++
++	pHalData = GET_HAL_DATA(padapter);
++
++	rcr = 0
++		| RCR_APM | RCR_AM | RCR_AB
++		| RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF
++		| RCR_HTC_LOC_CTRL
++		| RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC
++		#ifdef CONFIG_MAC_LOOPBACK_DRIVER
++		| RCR_AAP
++		| RCR_ADD3 | RCR_APWRMGT | RCR_ACRC32 | RCR_ADF
++		#endif
++		;
++	rtw_hal_set_hwreg(padapter, HW_VAR_RCR, (u8 *)&rcr);
++
++	/* Accept all multicast address */
++	rtw_write32(padapter, REG_MAR, 0xFFFFFFFF);
++	rtw_write32(padapter, REG_MAR + 4, 0xFFFFFFFF);
++
++	/* Accept all data frames */
++	value16 = 0xFFFF;
++	rtw_write16(padapter, REG_RXFLTMAP2, value16);
++
++	/* 2010.09.08 hpfan */
++	/* Since ADF is removed from RCR, ps-poll will not be indicate to driver, */
++	/* RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */
++	value16 = 0x400;
++	rtw_write16(padapter, REG_RXFLTMAP1, value16);
++
++	/* Accept all management frames */
++	value16 = 0xFFFF;
++	rtw_write16(padapter, REG_RXFLTMAP0, value16);
++}
++
++void _InitAdaptiveCtrl(PADAPTER padapter)
++{
++	u16	value16;
++	u32	value32;
++
++	/* Response Rate Set */
++	value32 = rtw_read32(padapter, REG_RRSR);
++	value32 &= ~RATE_BITMAP_ALL;
++	value32 |= RATE_RRSR_CCK_ONLY_1M;
++
++	rtw_phydm_set_rrsr(padapter, value32, TRUE);
++
++
++	/* CF-END Threshold */
++	/* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */
++
++	/* SIFS (used in NAV) */
++	value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
++	rtw_write16(padapter, REG_SPEC_SIFS, value16);
++
++	/* Retry Limit */
++	value16 = BIT_LRL(RL_VAL_STA) | BIT_SRL(RL_VAL_STA);
++	rtw_write16(padapter, REG_RETRY_LIMIT, value16);
++}
++
++void _InitEDCA(PADAPTER padapter)
++{
++	/* Set Spec SIFS (used in NAV) */
++	rtw_write16(padapter, REG_SPEC_SIFS, 0x100a);
++	rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a);
++
++	/* Set SIFS for CCK */
++	rtw_write16(padapter, REG_SIFS_CTX, 0x100a);
++
++	/* Set SIFS for OFDM */
++	rtw_write16(padapter, REG_SIFS_TRX, 0x100a);
++
++	/* TXOP */
++	rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B);
++	rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F);
++	rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324);
++	rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226);
++}
++
++void _InitRetryFunction(PADAPTER padapter)
++{
++	u8	value8;
++
++	value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL);
++	value8 |= EN_AMPDU_RTY_NEW;
++	rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8);
++
++	/* Set ACK timeout */
++	rtw_write8(padapter, REG_ACKTO, 0x40);
++}
++
++static void HalRxAggr8723DSdio(PADAPTER padapter)
++{
++	u8	dma_time_th;
++	u8	dma_len_th;
++
++	if (padapter->registrypriv.wifi_spec) {
++		dma_time_th = 0x01;
++		dma_len_th = 0x0f;
++	} else {
++		dma_time_th = 0x03;
++		dma_len_th = 0x0a;
++	}
++
++	if (dma_len_th * 1024 > MAX_RECVBUF_SZ) {
++		RTW_PRINT("Reduce RXDMA_AGG_LEN_TH from %u to %u\n"
++			  , dma_len_th, MAX_RECVBUF_SZ / 1024);
++		dma_len_th = MAX_RECVBUF_SZ / 1024;
++	}
++
++	rtw_write16(padapter, REG_RXDMA_AGG_PG_TH, (dma_time_th << 8) | dma_len_th);
++
++}
++
++void sdio_AggSettingRxUpdate(PADAPTER padapter)
++{
++	HAL_DATA_TYPE *pHalData;
++	u8 val8;
++	u8 valueDMA;
++	u8 valueRxAggCtrl = 0;
++	u8 aggBurstNum = 3;  /* 0:1, 1:2, 2:3, 3:4 */
++	u8 aggBurstSize = 0;  /* 0:1K, 1:512Byte, 2:256Byte... */
++
++	pHalData = GET_HAL_DATA(padapter);
++
++	val8 = rtw_read8(padapter, REG_RXDMA_AGG_PG_TH + 3);
++	val8 = val8 | BIT(7) | BIT(5);
++	rtw_write8(padapter, REG_RXDMA_AGG_PG_TH + 3, val8);
++	
++	valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
++	valueDMA |= RXDMA_AGG_EN;
++	rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
++
++	valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
++	valueRxAggCtrl |= ((aggBurstNum << 2) & 0x0C);
++	valueRxAggCtrl |= ((aggBurstSize << 4) & 0x30);
++	rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8723D, valueRxAggCtrl);/* RxAggLowThresh = 4*1K */
++}
++
++void _initSdioAggregationSetting(PADAPTER padapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	/* Tx aggregation setting
++	*	sdio_AggSettingTxUpdate(padapter); */
++
++	/* Rx aggregation setting */
++	HalRxAggr8723DSdio(padapter);
++
++	sdio_AggSettingRxUpdate(padapter);
++}
++#if 0
++static void _RXAggrSwitch(PADAPTER padapter, u8 enable)
++{
++	PHAL_DATA_TYPE pHalData;
++	u8 valueDMA;
++	u8 valueRxAggCtrl;
++
++
++	pHalData = GET_HAL_DATA(padapter);
++
++	valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
++	valueRxAggCtrl = rtw_read8(padapter, REG_RXDMA_MODE_CTRL_8723D);
++
++	if (_TRUE == enable) {
++		valueDMA |= RXDMA_AGG_EN;
++		valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
++	} else {
++		valueDMA &= ~RXDMA_AGG_EN;
++		valueRxAggCtrl &= ~RXDMA_AGG_MODE_EN;
++	}
++
++	rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
++	rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8723D, valueRxAggCtrl);
++}
++#endif
++
++void _InitInterrupt(PADAPTER padapter)
++{
++	/* HISR - turn all off */
++	rtw_write32(padapter, REG_HISR, 0);
++
++	/* HIMR - turn all off */
++	rtw_write32(padapter, REG_HIMR, 0);
++
++	/* */
++	/* Initialize and enable SDIO Host Interrupt. */
++	/* */
++	InitInterrupt8723DSdio(padapter);
++
++	/* */
++	/* Initialize system Host Interrupt. */
++	/* */
++	InitSysInterrupt8723DSdio(padapter);
++}
++
++void _InitRDGSetting(PADAPTER padapter)
++{
++	rtw_write8(padapter, REG_RD_CTRL, 0xFF);
++	rtw_write16(padapter, REG_RD_NAV_NXT, 0x200);
++	rtw_write8(padapter, REG_RD_RESP_PKT_TH, 0x05);
++}
++
++static void _InitRFType(PADAPTER padapter)
++{
++	struct registry_priv *pregpriv = &padapter->registrypriv;
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++#if	DISABLE_BB_RF
++	pHalData->rf_chip	= RF_PSEUDO_11N;
++	return;
++#endif
++	pHalData->rf_chip	= RF_6052;
++
++	RTW_INFO("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
++}
++
++/* Set CCK and OFDM Block "ON" */
++static void _BBTurnOnBlock(PADAPTER padapter)
++{
++#if (DISABLE_BB_RF)
++	return;
++#endif
++
++	phy_set_bb_reg(padapter, rFPGA0_RFMOD, bCCKEn, 0x1);
++	phy_set_bb_reg(padapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
++}
++
++void _InitBBRegBackup_8723DS(PADAPTER	Adapter)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++	u8	i;
++
++	/* For Channel 1~11 (Default Value)*/
++	pHalData->RegForRecover[0].offset = rCCK0_TxFilter2;
++	pHalData->RegForRecover[0].value =
++		phy_query_bb_reg(Adapter,
++			       pHalData->RegForRecover[0].offset, bMaskDWord);
++
++	pHalData->RegForRecover[1].offset = rCCK0_DebugPort;
++	pHalData->RegForRecover[1].value =
++		phy_query_bb_reg(Adapter,
++			       pHalData->RegForRecover[1].offset, bMaskDWord);
++
++	pHalData->RegForRecover[2].offset = 0xAAC;
++	pHalData->RegForRecover[2].value =
++		phy_query_bb_reg(Adapter,
++			       pHalData->RegForRecover[2].offset, bMaskDWord);
++#if 0
++	/* For 20 MHz	(Default Value)*/
++	pHalData->RegForRecover[2].offset = rBBrx_DFIR;
++	pHalData->RegForRecover[2].value = phy_query_bb_reg(Adapter, pHalData->RegForRecover[2].offset, bMaskDWord);
++
++	pHalData->RegForRecover[3].offset = rOFDM0_XATxAFE;
++	pHalData->RegForRecover[3].value = phy_query_bb_reg(Adapter, pHalData->RegForRecover[3].offset, bMaskDWord);
++
++	pHalData->RegForRecover[4].offset = 0x1E;
++	pHalData->RegForRecover[4].value = phy_query_rf_reg(Adapter, RF_PATH_A, pHalData->RegForRecover[4].offset, bRFRegOffsetMask);
++#endif
++}
++
++/*
++ * 2010/08/09 MH Add for power down check.
++ *   */
++static BOOLEAN HalDetectPwrDownMode(PADAPTER Adapter)
++{
++	u8 tmpvalue;
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
++
++
++	EFUSE_ShadowRead(Adapter, 1, EEPROM_FEATURE_OPTION_8723D, (u32 *)&tmpvalue);
++
++	/* 2010/08/25 MH INF priority > PDN Efuse value. */
++	if (tmpvalue & BIT(4) && pwrctrlpriv->reg_pdnmode)
++		pHalData->pwrdown = _TRUE;
++	else
++		pHalData->pwrdown = _FALSE;
++
++	RTW_INFO("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
++
++	return pHalData->pwrdown;
++}	/* HalDetectPwrDownMode */
++
++static void	rtl8723ds_init_burst_pkt_len(PADAPTER padapter)
++{
++	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
++
++	rtw_write8(padapter, 0x4c7, rtw_read8(padapter, 0x4c7) | BIT(7)); /* enable single pkt ampdu */
++	rtw_write8(padapter, REG_RX_PKT_LIMIT_8723D, 0x18);		/* for VHT packet length 11K */
++	rtw_write8(padapter, REG_MAX_AGGR_NUM_8723D, 0x1F);
++	rtw_write8(padapter, REG_PIFS_8723D, 0x00);
++	rtw_write8(padapter, REG_FWHW_TXQ_CTRL_8723D, rtw_read8(padapter, REG_FWHW_TXQ_CTRL) & (~BIT(7)));
++	if (pHalData->AMPDUBurstMode)
++		rtw_write8(padapter, REG_AMPDU_BURST_MODE_8723D,  0x5F);
++	rtw_write8(padapter, REG_AMPDU_MAX_TIME_8723D, 0x70);
++
++	/* ARFB table 9 for 11ac 5G 2SS */
++	rtw_write32(padapter, REG_ARFR0_8723D, 0x00000010);
++	if (IS_NORMAL_CHIP(pHalData->version_id))
++		rtw_write32(padapter, REG_ARFR0_8723D + 4, 0xfffff000);
++	else
++		rtw_write32(padapter, REG_ARFR0_8723D + 4, 0x3e0ff000);
++
++	/* ARFB table 10 for 11ac 5G 1SS */
++	rtw_write32(padapter, REG_ARFR1_8723D, 0x00000010);
++	rtw_write32(padapter, REG_ARFR1_8723D + 4, 0x003ff000);
++}
++
++#if 0
++static void rtl8723ds_init_lte_coex(PADAPTER padapter)
++{
++	/* LTE COEX setting */
++	rtw_write16(padapter, REG_LTECOEX_WRITE_DATA, 0x7700);
++	rtw_write32(padapter, REG_LTECOEX_CTRL, 0xc0020038);
++	rtw_write8(padapter, 0x73, 0x04);
++}
++#endif
++
++static u32 rtl8723ds_hal_init(PADAPTER padapter)
++{
++	s32 ret;
++	PHAL_DATA_TYPE pHalData;
++	struct pwrctrl_priv *pwrctrlpriv;
++	struct registry_priv *pregistrypriv;
++	struct sreset_priv *psrtpriv;
++	struct dvobj_priv *psdpriv = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
++	rt_rf_power_state eRfPowerStateToSet;
++	u32 NavUpper = WiFiNavUpperUs;
++	u8 u1bTmp;
++	u16 value16;
++	u8 typeid;
++	u32 u4Tmp;
++
++	pHalData = GET_HAL_DATA(padapter);
++	psrtpriv = &pHalData->srestpriv;
++	pwrctrlpriv = adapter_to_pwrctl(padapter);
++	pregistrypriv = &padapter->registrypriv;
++
++#ifdef CONFIG_SWLPS_IN_IPS
++	if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE) {
++		u8 val8, bMacPwrCtrlOn = _TRUE;
++
++		RTW_INFO("%s: run LPS flow in IPS\n", __FUNCTION__);
++
++		/* ser rpwm */
++		val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
++		val8 &= 0x80;
++		val8 += 0x80;
++		val8 |= BIT(6);
++		rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
++
++		adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
++
++		rtw_mdelay_os(5); /* wait set rpwm already */
++
++		ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723D_leave_swlps_flow);
++		if (ret == _FALSE) {
++			RTW_INFO("%s: run LPS flow in IPS fail!\n", __FUNCTION__);
++			return _FAIL;
++		}
++
++		rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++
++		pHalData->LastHMEBoxNum = 0;
++
++#ifdef CONFIG_BT_COEXIST
++		rtw_btcoex_HAL_Initialize(padapter, _FALSE);
++#else
++		rtw_btcoex_HAL_Initialize(padapter, _TRUE);
++#endif /* CONFIG_BT_COEXIST */
++
++		return _SUCCESS;
++	}
++#elif defined(CONFIG_FWLPS_IN_IPS)
++	if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE
++	    && adapter_to_pwrctl(padapter)->pre_ips_type == 0) {
++		systime start_time;
++		u8 cpwm_orig, cpwm_now;
++		u8 val8, bMacPwrCtrlOn = _TRUE;
++
++		RTW_INFO("%s: Leaving IPS in FWLPS state\n", __FUNCTION__);
++
++		/* for polling cpwm */
++		cpwm_orig = 0;
++		rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
++
++		/* ser rpwm */
++		val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
++		val8 &= 0x80;
++		val8 += 0x80;
++		val8 |= BIT(6);
++		rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
++		RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
++		adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
++
++		/* do polling cpwm */
++		start_time = rtw_get_current_time();
++		do {
++
++			rtw_mdelay_os(1);
++
++			rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
++			if ((cpwm_orig ^ cpwm_now) & 0x80) {
++#ifdef DBG_CHECK_FW_PS_STATE
++				RTW_INFO("%s: polling cpwm ok when leaving IPS in FWLPS state, cpwm_orig=%02x, cpwm_now=%02x, 0x100=0x%x\n"
++					, __FUNCTION__, cpwm_orig, cpwm_now, rtw_read8(padapter, REG_CR));
++#endif /* DBG_CHECK_FW_PS_STATE */
++				break;
++			}
++
++			if (rtw_get_passing_time_ms(start_time) > 100) {
++				RTW_INFO("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __FUNCTION__);
++				break;
++			}
++		} while (1);
++
++		rtw_set_fw_in_ips_mode(padapter, 0);
++
++		rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++
++#ifdef CONFIG_BT_COEXIST
++		rtw_btcoex_HAL_Initialize(padapter, _FALSE);
++#else
++		rtw_btcoex_HAL_Initialize(padapter, _TRUE);
++#endif /* CONFIG_BT_COEXIST */
++
++#ifdef DBG_CHECK_FW_PS_STATE
++		if (rtw_fw_ps_state(padapter) == _FAIL) {
++			RTW_INFO("after hal init, fw ps state in 32k\n");
++			pdbgpriv->dbg_ips_drvopen_fail_cnt++;
++		}
++#endif /* DBG_CHECK_FW_PS_STATE */
++		return _SUCCESS;
++	}
++#endif /* CONFIG_SWLPS_IN_IPS */
++
++	/* Disable Interrupt first.
++	*	rtw_hal_disable_interrupt(padapter); */
++
++	if (rtw_read8(padapter, REG_MCUFWDL) == 0xc6)
++		RTW_INFO("FW exist before power on!!\n");
++	else
++		RTW_INFO("FW does not exist before power on!!\n");
++#ifdef DBG_CHECK_FW_PS_STATE
++	if (rtw_fw_ps_state(padapter) == _FAIL) {
++		RTW_INFO("check fw_ps_state fail before PowerOn!\n");
++		pdbgpriv->dbg_ips_drvopen_fail_cnt++;
++	}
++#endif
++	ret = rtw_hal_power_on(padapter);
++	if (_FAIL == ret) {
++		return _FAIL;
++	}
++	RTW_INFO("Power on ok!\n");
++#ifdef DBG_CHECK_FW_PS_STATE
++	if (rtw_fw_ps_state(padapter) == _FAIL) {
++		RTW_INFO("check fw_ps_state fail after PowerOn!\n");
++		pdbgpriv->dbg_ips_drvopen_fail_cnt++;
++	}
++#endif
++
++	rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0);
++
++	if (padapter->registrypriv.mp_mode == 0
++		#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)
++		|| padapter->registrypriv.mp_customer_str
++		#endif
++	) {
++		ret = rtl8723d_FirmwareDownload(padapter, _FALSE);
++		if (ret != _SUCCESS) {
++			pHalData->bFWReady = _FALSE;
++			pHalData->fw_ractrl = _FALSE;
++			return ret;
++		} /*else*/
++		{
++			pHalData->bFWReady = _TRUE;
++			pHalData->fw_ractrl = _TRUE;
++		}
++	}
++
++	/*	SIC_Init(padapter); */
++
++	if (pwrctrlpriv->reg_rfoff == _TRUE)
++		pwrctrlpriv->rf_pwrstate = rf_off;
++
++	/* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
++	/* HW GPIO pin. Before PHY_RFConfig8192C. */
++	HalDetectPwrDownMode(padapter);
++
++	/* Set RF type for BB/RF configuration */
++	_InitRFType(padapter);
++
++	/* Save target channel */
++	/* <Roger_Notes> Current Channel will be updated again later. */
++	pHalData->current_channel = 6;
++
++#if (HAL_MAC_ENABLE == 1)
++	ret = PHY_MACConfig8723D(padapter);
++	if (ret != _SUCCESS) {
++		return ret;
++	}
++#endif
++	/* */
++	/* d. Initialize BB related configurations. */
++	/* */
++#if (HAL_BB_ENABLE == 1)
++	ret = PHY_BBConfig8723D(padapter);
++	if (ret != _SUCCESS) {
++		return ret;
++	}
++
++#endif
++
++	/* If RF is on, we need to init RF. Otherwise, skip the procedure. */
++	/* We need to follow SU method to change the RF cfg.txt. Default disable RF TX/RX mode. */
++	/* if(pHalData->eRFPowerState == eRfOn) */
++	{
++#if (HAL_RF_ENABLE == 1)
++		ret = PHY_RFConfig8723D(padapter);
++		if (ret != _SUCCESS) {
++			return ret;
++		}
++#endif
++	}
++
++	_InitBBRegBackup_8723DS(padapter);
++
++	_InitMacAPLLSetting_8723D(padapter);
++
++	/* */
++	/* Joseph Note: Keep RfRegChnlVal for later use. */
++	/* */
++	pHalData->RfRegChnlVal[0] = phy_query_rf_reg(padapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
++	pHalData->RfRegChnlVal[1] = phy_query_rf_reg(padapter, RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask);
++
++#ifdef CONFIG_DLFW_TXPKT
++	/* Specially add for FWDL by Tx pkt write.
++	   Reset Tx/Rx DMA since the Tx boundary setting
++	   is changed during FW download */
++	rtw_write8(padapter, REG_CR, 0x00);
++	rtw_write8(padapter, REG_CR, 0xFF);
++#endif
++
++	/* if (!pHalData->bMACFuncEnable) { */
++	_InitQueueReservedPage(padapter);
++	_InitTxBufferBoundary(padapter);
++	/* init LLT after tx buffer boundary is defined */
++	ret = rtl8723d_InitLLTTable(padapter);
++	if (_SUCCESS != ret) {
++		RTW_INFO("%s: Failed to init LLT Table!\n", __func__);
++		return _FAIL;
++	}
++	/* } */
++	_InitQueuePriority(padapter);
++	_InitPageBoundary(padapter);
++	_InitTransferPageSize(padapter);
++
++	/* Get Rx PHY status in order to report RSSI and others. */
++	_InitDriverInfoSize(padapter, DRVINFO_SZ);
++	_InitNetworkType(padapter);
++	_InitWMACSetting(padapter);
++	_InitAdaptiveCtrl(padapter);
++	_InitEDCA(padapter);
++	_InitRetryFunction(padapter);
++	_initSdioAggregationSetting(padapter);
++	rtl8723d_InitBeaconParameters(padapter);
++	rtl8723d_InitBeaconMaxError(padapter, _TRUE);
++	_InitInterrupt(padapter);
++	rtl8723ds_init_burst_pkt_len(padapter);
++
++#if 0
++	/* 8723D new ADD */
++	rtl8723ds_init_lte_coex(padapter);
++#endif
++
++	/* YJ,TODO */
++	rtw_write8(padapter, REG_SECONDARY_CCA_CTRL_8723D, 0x3);	/* CCA */
++	rtw_write8(padapter, 0x976, 0);	/* hpfan_todo: 2nd CCA related */
++
++	_BBTurnOnBlock(padapter);
++
++	invalidate_cam_all(padapter);
++
++	rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,
++		CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
++
++	rtl8723d_InitAntenna_Selection(padapter);
++
++	/* */
++	/* Disable BAR, suggested by Scott */
++	/* 2010.04.09 add by hpfan */
++	/* */
++	rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
++
++	/* HW SEQ CTRL */
++	/* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
++	rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
++
++
++#ifdef CONFIG_MAC_LOOPBACK_DRIVER
++	u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN);
++	u1bTmp &= ~(FEN_BBRSTB | FEN_BB_GLB_RSTn);
++	rtw_write8(padapter, REG_SYS_FUNC_EN, u1bTmp);
++
++	rtw_write8(padapter, REG_RD_CTRL, 0x0F);
++	rtw_write8(padapter, REG_RD_CTRL + 1, 0xCF);
++	rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, 0x80);
++	rtw_write32(padapter, REG_CR, 0x0b0202ff);
++#endif
++
++	/* */
++	/* Configure SDIO TxRx Control to enable Rx DMA timer masking. */
++	/* 2010.02.24. */
++	/* */
++	rtw_write32(padapter, SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL, 0);
++
++	rtl8723d_InitHalDm(padapter);
++
++	/* dbg_print("pHalData->DefaultTxPwrDbm = %d\n", pHalData->DefaultTxPwrDbm); */
++
++#if 0
++	if (pHalData->SwBeaconType < HAL92CSDIO_DEFAULT_BEACON_TYPE) /*  The lowest Beacon Type that HW can support */
++		*pHalData->SwBeaconType = HAL92CSDIO_DEFAULT_BEACON_TYPE;
++#endif
++
++	/* */
++	/* Update current Tx FIFO page status. */
++	/* */
++	HalQueryTxBufferStatus8723DSdio(padapter);
++	HalQueryTxOQTBufferStatus8723DSdio(padapter);
++	pHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace;
++
++	/* Enable MACTXEN/MACRXEN block */
++	u1bTmp = rtw_read8(padapter, REG_CR);
++	u1bTmp |= (MACTXEN | MACRXEN);
++	rtw_write8(padapter, REG_CR, u1bTmp);
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper);
++
++#ifdef CONFIG_XMIT_ACK
++	/* ack for xmit mgmt frames. */
++	rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12));
++#endif /* CONFIG_XMIT_ACK	 */
++
++	/*	pHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80; */
++
++#if (MP_DRIVER == 1)
++	if (padapter->registrypriv.mp_mode == 1) {
++		padapter->mppriv.channel = pHalData->current_channel;
++		MPT_InitializeAdapter(padapter, padapter->mppriv.channel);
++	} else
++#endif /* #if (MP_DRIVER == 1) */
++	{
++		pwrctrlpriv->rf_pwrstate = rf_on;
++
++		halrf_lck_trigger(&pHalData->odmpriv);
++
++		pHalData->neediqk_24g = _TRUE;
++
++		odm_txpowertracking_check(&pHalData->odmpriv);
++	}
++
++#ifdef CONFIG_BT_COEXIST
++	/* Init BT hw config.*/
++	if (padapter->registrypriv.mp_mode == 1)
++		rtw_btcoex_HAL_Initialize(padapter, _TRUE);
++	else
++		rtw_btcoex_HAL_Initialize(padapter, _FALSE);
++#endif
++
++	if (padapter->registrypriv.wifi_spec == 1)
++		phy_set_bb_reg(padapter, rOFDM0_ECCAThreshold,
++			       0x00ff00ff, 0x00250029);
++
++	return _SUCCESS;
++}
++
++static void CardDisableRTL8723DSdio(PADAPTER padapter)
++{
++	u8		u1bTmp;
++	u16		u2bTmp;
++	u32		u4bTmp;
++	u8		bMacPwrCtrlOn;
++	u8		ret = _FAIL;
++
++	/* Run LPS WL RFOFF flow */
++	ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723D_enter_lps_flow);
++	if (ret == _FAIL)
++		RTW_INFO(KERN_ERR "%s: run RF OFF flow fail!\n", __func__);
++
++	/*	==== Reset digital sequence   ====== */
++
++	u1bTmp = rtw_read8(padapter, REG_MCUFWDL);
++	if ((u1bTmp & RAM_DL_SEL) && GET_HAL_DATA(padapter)->bFWReady) /* 8051 RAM code */
++		rtl8723d_FirmwareSelfReset(padapter);
++
++	/* Reset MCU 0x2[10]=0. Suggested by Filen. 2011.01.26. by tynli. */
++	u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
++	u1bTmp &= ~BIT(2);	/* 0x2[10], FEN_CPUEN */
++	rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp);
++
++	/* MCUFWDL 0x80[1:0]=0 */
++	/* reset MCU ready status */
++	rtw_write8(padapter, REG_MCUFWDL, 0);
++
++	/* Reset MCU IO Wrapper, added by Roger, 2011.08.30 */
++	u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
++	u1bTmp &= ~BIT(0);
++	rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp);
++	u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
++	u1bTmp |= BIT(0);
++	rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp);
++
++	/*	==== Reset digital sequence end ====== */
++
++	bMacPwrCtrlOn = _FALSE;	/* Disable CMD53 R/W */
++	ret = _FALSE;
++	rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++	ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723D_card_disable_flow);
++	if (ret == _FALSE)
++		RTW_INFO(KERN_ERR "%s: run CARD DISABLE flow fail!\n", __func__);
++
++	GET_HAL_DATA(padapter)->bFWReady = _FALSE;
++}
++
++static u32 rtl8723ds_hal_deinit(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++	struct dvobj_priv *psdpriv = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
++
++#ifdef CONFIG_MP_INCLUDED
++	if (padapter->registrypriv.mp_mode == 1)
++		MPT_DeInitAdapter(padapter);
++#endif
++
++	if (rtw_is_hw_init_completed(padapter)) {
++#ifdef CONFIG_SWLPS_IN_IPS
++		if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE) {
++			u8	bMacPwrCtrlOn;
++			u8 ret =  _TRUE;
++
++			RTW_INFO("%s: run LPS flow in IPS\n", __FUNCTION__);
++
++			rtw_write32(padapter, 0x130, 0x0);
++			rtw_write32(padapter, 0x138, 0x100);
++			rtw_write8(padapter, 0x13d, 0x1);
++
++
++			bMacPwrCtrlOn = _FALSE;	/* Disable CMD53 R/W	 */
++			rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++
++			ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723D_enter_swlps_flow);
++			if (ret == _FALSE) {
++				RTW_INFO("%s: run LPS flow in IPS fail!\n", __FUNCTION__);
++				return _FAIL;
++			}
++		} else
++#elif defined(CONFIG_FWLPS_IN_IPS)
++		if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE) {
++			if (padapter->netif_up == _TRUE) {
++				int cnt = 0;
++				u8 val8 = 0;
++
++				RTW_INFO("%s: issue H2C to FW when entering IPS\n", __FUNCTION__);
++
++				rtw_set_fw_in_ips_mode(padapter, 0x1);
++				/* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW. */
++				do {
++					val8 = rtw_read8(padapter, REG_HMETFR);
++					cnt++;
++					RTW_INFO("%s  polling REG_HMETFR=0x%x, cnt=%d\n", __FUNCTION__, val8, cnt);
++					rtw_mdelay_os(10);
++				} while (cnt < 100 && (val8 != 0));
++				/* H2C done, enter 32k */
++				if (val8 == 0) {
++					/* ser rpwm to enter 32k */
++					val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
++					val8 += 0x80;
++					val8 |= BIT(0);
++					rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
++					RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
++					adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
++					cnt = val8 = 0;
++					do {
++						val8 = rtw_read8(padapter, REG_CR);
++						cnt++;
++						RTW_INFO("%s  polling 0x100=0x%x, cnt=%d\n", __FUNCTION__, val8, cnt);
++						rtw_mdelay_os(10);
++					} while (cnt < 100 && (val8 != 0xEA));
++#ifdef DBG_CHECK_FW_PS_STATE
++					if (val8 != 0xEA)
++						RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
++							, rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
++#endif /* DBG_CHECK_FW_PS_STATE */
++				} else {
++					RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
++						, rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
++				}
++
++				RTW_INFO("polling done when entering IPS, check result : 0x100=0x%x, cnt=%d, MAC_1cc=0x%02x\n"
++					, rtw_read8(padapter, REG_CR), cnt, rtw_read8(padapter, REG_HMETFR));
++
++				adapter_to_pwrctl(padapter)->pre_ips_type = 0;
++
++			} else {
++				pdbgpriv->dbg_carddisable_cnt++;
++#ifdef DBG_CHECK_FW_PS_STATE
++				if (rtw_fw_ps_state(padapter) == _FAIL) {
++					RTW_INFO("card disable should leave 32k\n");
++					pdbgpriv->dbg_carddisable_error_cnt++;
++				}
++#endif /* DBG_CHECK_FW_PS_STATE */
++				rtw_hal_power_off(padapter);
++
++				adapter_to_pwrctl(padapter)->pre_ips_type = 1;
++			}
++
++		} else
++#endif /* CONFIG_SWLPS_IN_IPS */
++		{
++			pdbgpriv->dbg_carddisable_cnt++;
++#ifdef DBG_CHECK_FW_PS_STATE
++			if (rtw_fw_ps_state(padapter) == _FAIL) {
++				RTW_INFO("card disable should leave 32k\n");
++				pdbgpriv->dbg_carddisable_error_cnt++;
++			}
++#endif /* DBG_CHECK_FW_PS_STATE */
++			rtw_hal_power_off(padapter);
++		}
++	} else
++		pdbgpriv->dbg_deinit_fail_cnt++;
++
++	return _SUCCESS;
++}
++static void rtl8723ds_init_default_value(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE pHalData;
++
++
++	pHalData = GET_HAL_DATA(padapter);
++
++	rtl8723d_init_default_value(padapter);
++
++	/* interface related variable */
++	pHalData->SdioRxFIFOCnt = 0;
++}
++
++static void rtl8723ds_interface_configure(PADAPTER padapter)
++{
++	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
++	struct dvobj_priv		*pdvobjpriv = adapter_to_dvobj(padapter);
++	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
++	BOOLEAN		bWiFiConfig	= pregistrypriv->wifi_spec;
++
++
++	pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID;
++	pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID;
++	pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID;
++
++	if (bWiFiConfig)
++		pHalData->OutEpNumber = 2;
++	else
++		pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE;
++
++	switch (pHalData->OutEpNumber) {
++	case 3:
++		pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
++		break;
++	case 2:
++		pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
++		break;
++	case 1:
++		pHalData->OutEpQueueSel = TX_SELE_HQ;
++		break;
++	default:
++		break;
++	}
++
++	Hal_MappingOutPipe(padapter, pHalData->OutEpNumber);
++}
++
++/*
++ *	Description:
++ *		We should set Efuse cell selection to WiFi cell in default.
++ *
++ *	Assumption:
++ *		PASSIVE_LEVEL
++ *
++ *	Added by Roger, 2010.11.23.
++ *   */
++static void
++_EfuseCellSel(
++		PADAPTER	padapter
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	u32			value32;
++
++	/* if(INCLUDE_MULTI_FUNC_BT(padapter)) */
++	{
++		value32 = rtw_read32(padapter, EFUSE_TEST);
++		value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
++		rtw_write32(padapter, EFUSE_TEST, value32);
++	}
++}
++
++static void
++_ReadRFType(
++		PADAPTER	Adapter
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++
++#if DISABLE_BB_RF
++	pHalData->rf_chip = RF_PSEUDO_11N;
++#else
++	pHalData->rf_chip = RF_6052;
++#endif
++}
++
++static u8
++_ReadEfuseInfo8723DS(
++		PADAPTER			padapter
++)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++	u8 *hwinfo = NULL;
++	u8 ret = _FAIL;
++
++	/* */
++	/* This part read and parse the eeprom/efuse content */
++	/* */
++
++	if (sizeof(pHalData->efuse_eeprom_data) < HWSET_MAX_SIZE_8723D)
++		RTW_INFO("[WARNING] size of efuse_eeprom_data is less than HWSET_MAX_SIZE_8723D!\n");
++
++	hwinfo = pHalData->efuse_eeprom_data;
++
++	Hal_InitPGData(padapter, hwinfo);
++
++	Hal_EfuseParseIDCode(padapter, hwinfo);
++	Hal_EfuseParseEEPROMVer_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
++	hal_config_macaddr(padapter, pHalData->bautoload_fail_flag);
++	Hal_EfuseParseTxPowerInfo_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
++	Hal_EfuseParseBoardType_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
++
++	/* */
++	/* Read Bluetooth co-exist and initialize */
++	/* */
++	Hal_EfuseParseBTCoexistInfo_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
++	Hal_EfuseParseChnlPlan_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
++	Hal_EfuseParseXtal_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
++	Hal_EfuseParseThermalMeter_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
++	Hal_EfuseParseAntennaDiversity_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
++	Hal_EfuseParseCustomerID_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
++
++	Hal_EfuseParseVoltage_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
++
++#ifdef CONFIG_WOWLAN
++	Hal_DetectWoWMode(padapter);
++#endif
++
++#ifdef CONFIG_RF_POWER_TRIM
++	Hal_ReadRFGainOffset(padapter, hwinfo, pHalData->bautoload_fail_flag);
++#endif /* CONFIG_RF_GAIN_OFFSET */
++
++	/* set coex. ant info once efuse parsing is done */
++	rtw_btcoex_set_ant_info(padapter);
++
++	if (hal_read_mac_hidden_rpt(padapter) != _SUCCESS)
++		goto exit;
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++
++static u8 _ReadPROMContent(
++		PADAPTER		padapter
++)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++	u8			eeValue;
++	u8 ret = _FAIL;
++
++	eeValue = rtw_read8(padapter, REG_9346CR);
++	/* To check system boot selection. */
++	pHalData->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
++	pHalData->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
++
++
++	/*	pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; */
++
++	if (_ReadEfuseInfo8723DS(padapter) != _SUCCESS)
++		goto exit;
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++
++static void
++_InitOtherVariable(
++		PADAPTER		Adapter
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++
++
++	/* if(Adapter->bInHctTest){ */
++	/*	pMgntInfo->PowerSaveControl.bInactivePs = FALSE; */
++	/*	pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE; */
++	/*	pMgntInfo->PowerSaveControl.bLeisurePs = FALSE; */
++	/*	pMgntInfo->keepAliveLevel = 0; */
++	/* } */
++
++
++
++}
++
++/*
++ *	Description:
++ *		Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
++ *
++ *	Assumption:
++ *		PASSIVE_LEVEL (SDIO interface)
++ *
++ *   */
++static u8 ReadAdapterInfo8723DS(PADAPTER padapter)
++{
++	u8 val8;
++	u8 ret = _FAIL;
++
++	val8 = rtw_read8(padapter, 0x4e);
++	RTW_INFO("%s, 0x4e=0x%x\n", __func__, val8);
++	val8 |= BIT(6);
++	rtw_write8(padapter, 0x4e, val8);
++
++	/* Read EEPROM size before call any EEPROM function */
++	padapter->EepromAddressSize = GetEEPROMSize8723D(padapter);
++
++	_EfuseCellSel(padapter);
++	_ReadRFType(padapter);
++	if (_ReadPROMContent(padapter) != _SUCCESS)
++		goto exit;
++
++	_InitOtherVariable(padapter);
++
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++	{ /* for BT, let BT can control ANT when wifi disable */
++		u32 val32;
++
++		RTW_INFO("%s, 0x4c=0x%x\n", __func__, rtw_read32(padapter, 0x4c));
++		val32 = rtw_read32(padapter, 0x64);
++		RTW_INFO("%s, 0x64=0x%x\n", __func__, val32);
++		val32 |= BIT(13);
++		rtw_write32(padapter, 0x64, val32);
++		RTW_INFO("%s, 0x64=0x%x\n", __func__, rtw_read32(padapter, 0x64));
++	}
++#endif /* CONFIG_PLATFORM_INTEL_BYT */
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++
++/*
++ * If variable not handled here,
++ * some variables will be processed in SetHwReg8723D()
++ */
++u8 SetHwReg8723DS(PADAPTER padapter, u8 variable, u8 *val)
++{
++	PHAL_DATA_TYPE pHalData;
++	u8 ret = _SUCCESS;
++	u8 val8;
++
++
++	pHalData = GET_HAL_DATA(padapter);
++
++	switch (variable) {
++	case HW_VAR_SET_RPWM:
++		/* rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) */
++		/* BIT0 value - 1: 32k, 0:40MHz. */
++		/* BIT6 value - 1: report cpwm value after success set, 0:do not report. */
++		/* BIT7 value - Toggle bit change. */
++	{
++		val8 = *val;
++		val8 &= 0xC1;
++		rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
++	}
++	break;
++	case HW_VAR_SET_REQ_FW_PS:
++		/* 1. driver write 0x8f[4]=1  //request fw ps state (only can write bit4) */
++	{
++		u8 req_fw_ps = 0;
++
++		req_fw_ps = rtw_read8(padapter, 0x8f);
++		req_fw_ps |= 0x10;
++		rtw_write8(padapter, 0x8f, req_fw_ps);
++	}
++	break;
++	case HW_VAR_RXDMA_AGG_PG_TH:
++		#if 0
++		val8 = *val;
++
++		/* TH=1 => invalidate RX DMA aggregation */
++		/* TH=0 => validate RX DMA aggregation, use init value. */
++		if (val8 == 0) {
++			/* enable RXDMA aggregation */
++			/* _RXAggrSwitch(padapter, _TRUE); */
++		} else {
++			/* disable RXDMA aggregation */
++			/* _RXAggrSwitch(padapter, _FALSE); */
++		}
++		#endif
++		break;
++#ifdef CONFIG_GPIO_WAKEUP
++	case HW_SET_GPIO_WL_CTRL: {
++		struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++		u8 enable = *val;
++		u8 value = 0;
++
++		if (pwrpriv->wowlan_gpio_index != 6)
++			break;
++
++		value = rtw_read8(padapter, REG_GPIO_MUXCFG);
++
++		if (enable && (value & BIT(3))) {
++			value &= ~BIT(3);
++			rtw_write8(padapter, REG_GPIO_MUXCFG, value);
++		} else if (enable == _FALSE) {
++			RTW_INFO("%s: keep WLAN ctrl\n", __func__);
++		}
++		/*0x66 bit4*/
++		value = rtw_read8(padapter, REG_PAD_CTRL_1 + 2);
++		if (enable && (value & BIT(4))) {
++			value &= ~BIT(4);
++			rtw_write8(padapter, REG_PAD_CTRL_1 + 2, value);
++		} else if (enable == _FALSE) {
++			value |= BIT(4);
++			rtw_write8(padapter, REG_PAD_CTRL_1 + 2, value);
++		}
++
++		/*0x66 bit8*/
++		value = rtw_read8(padapter, REG_PAD_CTRL_1 + 3);
++		if (enable && (value & BIT(0))) {
++			value &= ~BIT(0);
++			rtw_write8(padapter, REG_PAD_CTRL_1 + 3, value);
++		} else if (enable == _FALSE) {
++			value |= BIT(0);
++			rtw_write8(padapter, REG_PAD_CTRL_1 + 3, value);
++		}
++		RTW_INFO("%s: HW_SET_GPIO_WL_CTRL\n", __func__);
++	}
++		break;
++#endif
++	default:
++		ret = SetHwReg8723D(padapter, variable, val);
++		break;
++	}
++
++	return ret;
++}
++
++/*
++ * If variable not handled here,
++ * some variables will be processed in GetHwReg8723D()
++ */
++void GetHwReg8723DS(PADAPTER padapter, u8 variable, u8 *val)
++{
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++
++
++	switch (variable) {
++	case HW_VAR_CPWM:
++		*val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1_8723D);
++		break;
++
++	case HW_VAR_FW_PS_STATE: {
++		/* 3. read dword 0x88               //driver read fw ps state */
++		*((u16 *)val) = rtw_read16(padapter, 0x88);
++	}
++	break;
++	default:
++		GetHwReg8723D(padapter, variable, val);
++		break;
++	}
++
++}
++
++/*
++ *	Description:
++ *		Query setting of specified variable.
++ *   */
++u8
++GetHalDefVar8723DSDIO(
++		PADAPTER				Adapter,
++		HAL_DEF_VARIABLE		eVariable,
++		void						*pValue
++)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);
++	PSDIO_DATA psdio_data = NULL;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
++	u8			bResult = _SUCCESS;
++
++	switch (eVariable) {
++	case HAL_DEF_IS_SUPPORT_ANT_DIV:
++#ifdef CONFIG_ANTENNA_DIVERSITY
++		*((u8 *)pValue) = _FALSE;
++#endif
++		break;
++
++	case HW_VAR_MAX_RX_AMPDU_FACTOR:
++		/* Stanley@BB.SD3 suggests 16K can get stable performance */
++		/* coding by Lucas@20130730 */
++		psdio_data = &dvobj->intf_data;
++		if (psdio_data->clock > RTW_SDIO_CLK_40M)
++			*(HT_CAP_AMPDU_FACTOR *)pValue = MAX_AMPDU_FACTOR_32K;
++		else
++			*(HT_CAP_AMPDU_FACTOR *)pValue = MAX_AMPDU_FACTOR_16K;
++		break;
++	default:
++		bResult = GetHalDefVar8723D(Adapter, eVariable, pValue);
++		break;
++	}
++
++	return bResult;
++}
++
++/*
++ *	Description:
++ *		Change default setting of specified variable.
++ *   */
++u8
++SetHalDefVar8723DSDIO(
++		PADAPTER				Adapter,
++		HAL_DEF_VARIABLE		eVariable,
++		void						*pValue
++)
++{
++	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
++	u8			bResult = _SUCCESS;
++
++	switch (eVariable) {
++	default:
++		bResult = SetHalDefVar8723D(Adapter, eVariable, pValue);
++		break;
++	}
++
++	return bResult;
++}
++
++void rtl8723ds_set_hal_ops(PADAPTER padapter)
++{
++	struct hal_ops *pHalFunc = &padapter->hal_func;
++
++
++	rtl8723d_set_hal_ops(pHalFunc);
++
++	pHalFunc->hal_power_on = &_InitPowerOn_8723DS;
++	pHalFunc->hal_power_off = &CardDisableRTL8723DSdio;
++
++
++	pHalFunc->hal_init = &rtl8723ds_hal_init;
++	pHalFunc->hal_deinit = &rtl8723ds_hal_deinit;
++
++	pHalFunc->init_xmit_priv = &rtl8723ds_init_xmit_priv;
++	pHalFunc->free_xmit_priv = &rtl8723ds_free_xmit_priv;
++
++	pHalFunc->init_recv_priv = &rtl8723ds_init_recv_priv;
++	pHalFunc->free_recv_priv = &rtl8723ds_free_recv_priv;
++#ifdef CONFIG_RECV_THREAD_MODE
++	pHalFunc->recv_hdl = rtl8723ds_recv_hdl;
++#endif /* CONFIG_RECV_THREAD_MODE */
++#ifdef CONFIG_RTW_SW_LED
++	pHalFunc->InitSwLeds = &rtl8723ds_InitSwLeds;
++	pHalFunc->DeInitSwLeds = &rtl8723ds_DeInitSwLeds;
++#endif
++	pHalFunc->init_default_value = &rtl8723ds_init_default_value;
++	pHalFunc->intf_chip_configure = &rtl8723ds_interface_configure;
++	pHalFunc->read_adapter_info = &ReadAdapterInfo8723DS;
++
++	pHalFunc->enable_interrupt = &EnableInterrupt8723DSdio;
++	pHalFunc->disable_interrupt = &DisableInterrupt8723DSdio;
++	pHalFunc->check_ips_status = &CheckIPSStatus;
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++	pHalFunc->clear_interrupt = &ClearInterrupt8723DSdio;
++#endif
++	pHalFunc->set_hw_reg_handler = &SetHwReg8723DS;
++	pHalFunc->GetHwRegHandler = &GetHwReg8723DS;
++	pHalFunc->get_hal_def_var_handler = &GetHalDefVar8723DSDIO;
++	pHalFunc->SetHalDefVarHandler = &SetHalDefVar8723DSDIO;
++
++	pHalFunc->hal_xmit = &rtl8723ds_hal_xmit;
++	pHalFunc->mgnt_xmit = &rtl8723ds_mgnt_xmit;
++	pHalFunc->hal_xmitframe_enqueue = &rtl8723ds_hal_xmitframe_enqueue;
++
++#ifdef CONFIG_HOSTAPD_MLME
++	pHalFunc->hostap_mgnt_xmit_entry = NULL;
++#endif
++
++#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
++	pHalFunc->hal_init_checkbthang_workqueue =
++		&rtl8723ds_init_checkbthang_workqueue;
++	pHalFunc->hal_free_checkbthang_workqueue =
++		&rtl8723ds_free_checkbthang_workqueue;
++	pHalFunc->hal_cancle_checkbthang_workqueue =
++		&rtl8723ds_cancle_checkbthang_workqueue;
++	pHalFunc->hal_checke_bt_hang = &rtl8723ds_hal_check_bt_hang;
++#endif
++
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/sdio/sdio_ops.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/sdio/sdio_ops.c
+new file mode 100644
+index 000000000..72229d02d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/hal/rtl8723d/sdio/sdio_ops.c
+@@ -0,0 +1,1815 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _SDIO_OPS_C_
++
++#include <rtl8723d_hal.h>
++
++/* #define SDIO_DEBUG_IO 1 */
++
++
++/*
++ * Description:
++ *	The following mapping is for SDIO host local register space.
++ *
++ * Creadted by Roger, 2011.01.31.
++ *   */
++static void HalSdioGetCmdAddr8723DSdio(
++		PADAPTER			padapter,
++		u8				DeviceID,
++		u32				Addr,
++		u32				*pCmdAddr
++)
++{
++	switch (DeviceID) {
++	case SDIO_LOCAL_DEVICE_ID:
++		*pCmdAddr = ((SDIO_LOCAL_DEVICE_ID << 13) | (Addr & SDIO_LOCAL_MSK));
++		break;
++
++	case WLAN_IOREG_DEVICE_ID:
++		*pCmdAddr = ((WLAN_IOREG_DEVICE_ID << 13) | (Addr & WLAN_IOREG_MSK));
++		break;
++
++	case WLAN_TX_HIQ_DEVICE_ID:
++		*pCmdAddr = ((WLAN_TX_HIQ_DEVICE_ID << 13) | (Addr & WLAN_FIFO_MSK));
++		break;
++
++	case WLAN_TX_MIQ_DEVICE_ID:
++		*pCmdAddr = ((WLAN_TX_MIQ_DEVICE_ID << 13) | (Addr & WLAN_FIFO_MSK));
++		break;
++
++	case WLAN_TX_LOQ_DEVICE_ID:
++		*pCmdAddr = ((WLAN_TX_LOQ_DEVICE_ID << 13) | (Addr & WLAN_FIFO_MSK));
++		break;
++
++	case WLAN_RX0FF_DEVICE_ID:
++		*pCmdAddr = ((WLAN_RX0FF_DEVICE_ID << 13) | (Addr & WLAN_RX0FF_MSK));
++		break;
++
++	default:
++		break;
++	}
++}
++
++static u8 get_deviceid(u32 addr)
++{
++	u8 devideId;
++	u16 pseudoId;
++
++
++	pseudoId = (u16)(addr >> 16);
++	switch (pseudoId) {
++	case 0x1025:
++		devideId = SDIO_LOCAL_DEVICE_ID;
++		break;
++
++	case 0x1026:
++		devideId = WLAN_IOREG_DEVICE_ID;
++		break;
++
++	/*		case 0x1027:
++	 *			devideId = SDIO_FIRMWARE_FIFO;
++	 *			break; */
++
++	case 0x1031:
++		devideId = WLAN_TX_HIQ_DEVICE_ID;
++		break;
++
++	case 0x1032:
++		devideId = WLAN_TX_MIQ_DEVICE_ID;
++		break;
++
++	case 0x1033:
++		devideId = WLAN_TX_LOQ_DEVICE_ID;
++		break;
++
++	case 0x1034:
++		devideId = WLAN_RX0FF_DEVICE_ID;
++		break;
++
++	default:
++		/*			devideId = (u8)((addr >> 13) & 0xF); */
++		devideId = WLAN_IOREG_DEVICE_ID;
++		break;
++	}
++
++	return devideId;
++}
++
++/*
++ * Ref:
++ *	HalSdioGetCmdAddr8723DSdio()
++ */
++static u32 _cvrt2ftaddr(const u32 addr, u8 *pdeviceId, u16 *poffset)
++{
++	u8 deviceId;
++	u16 offset;
++	u32 ftaddr;
++
++
++	deviceId = get_deviceid(addr);
++	offset = 0;
++
++	switch (deviceId) {
++	case SDIO_LOCAL_DEVICE_ID:
++		offset = addr & SDIO_LOCAL_MSK;
++		break;
++
++	case WLAN_TX_HIQ_DEVICE_ID:
++	case WLAN_TX_MIQ_DEVICE_ID:
++	case WLAN_TX_LOQ_DEVICE_ID:
++		offset = addr & WLAN_FIFO_MSK;
++		break;
++
++	case WLAN_RX0FF_DEVICE_ID:
++		offset = addr & WLAN_RX0FF_MSK;
++		break;
++
++	case WLAN_IOREG_DEVICE_ID:
++	default:
++		deviceId = WLAN_IOREG_DEVICE_ID;
++		offset = addr & WLAN_IOREG_MSK;
++		break;
++	}
++	ftaddr = (deviceId << 13) | offset;
++
++	if (pdeviceId)
++		*pdeviceId = deviceId;
++	if (poffset)
++		*poffset = offset;
++
++	return ftaddr;
++}
++
++u8 sdio_read8(struct intf_hdl *pintfhdl, u32 addr)
++{
++	u32 ftaddr;
++	u8 val;
++
++	ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
++	val = sd_read8(pintfhdl, ftaddr, NULL);
++
++
++	return val;
++}
++
++u16 sdio_read16(struct intf_hdl *pintfhdl, u32 addr)
++{
++	u32 ftaddr;
++	u16 val;
++
++	ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
++	val = 0;
++	sd_cmd52_read(pintfhdl, ftaddr, 2, (u8 *)&val);
++	val = le16_to_cpu(val);
++
++
++	return val;
++}
++
++u32 sdio_read32(struct intf_hdl *pintfhdl, u32 addr)
++{
++	PADAPTER padapter;
++	u8 bMacPwrCtrlOn;
++	u8 deviceId;
++	u16 offset;
++	u32 ftaddr;
++	u8 shift;
++	u32 val;
++	s32 err;
++
++
++	padapter = pintfhdl->padapter;
++	ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset);
++
++	bMacPwrCtrlOn = _FALSE;
++	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++	if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100))
++	    || (_FALSE == bMacPwrCtrlOn)
++#ifdef CONFIG_LPS_LCLK
++	    || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode)
++#endif
++	   ) {
++		val = 0;
++		err = sd_cmd52_read(pintfhdl, ftaddr, 4, (u8 *)&val);
++#ifdef SDIO_DEBUG_IO
++		if (!err) {
++#endif
++			val = le32_to_cpu(val);
++			return val;
++#ifdef SDIO_DEBUG_IO
++		}
++
++		RTW_ERR("%s: Mac Power off, Read FAIL(%d)! addr=0x%x\n",
++			__func__, err, addr);
++
++		return SDIO_ERR_VAL32;
++#endif
++	}
++
++	/* 4 bytes alignment */
++	shift = ftaddr & 0x3;
++	if (shift == 0)
++		val = sd_read32(pintfhdl, ftaddr, NULL);
++	else {
++		u8 *ptmpbuf;
++
++		ptmpbuf = (u8 *)rtw_malloc(8);
++		if (NULL == ptmpbuf) {
++			RTW_ERR("%s: Allocate memory FAIL!(size=8) addr=0x%x\n",
++				__func__, addr);
++			return SDIO_ERR_VAL32;
++		}
++
++		ftaddr &= ~(u16)0x3;
++		sd_read(pintfhdl, ftaddr, 8, ptmpbuf);
++		_rtw_memcpy(&val, ptmpbuf + shift, 4);
++		val = le32_to_cpu(val);
++
++		rtw_mfree(ptmpbuf, 8);
++	}
++
++
++	return val;
++}
++
++s32 sdio_readN(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pbuf)
++{
++	PADAPTER padapter;
++	u8 bMacPwrCtrlOn;
++	u8 deviceId;
++	u16 offset;
++	u32 ftaddr;
++	u8 shift;
++	s32 err;
++
++
++	padapter = pintfhdl->padapter;
++	err = 0;
++
++	ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset);
++
++	bMacPwrCtrlOn = _FALSE;
++	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++	if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100))
++	    || (_FALSE == bMacPwrCtrlOn)
++#ifdef CONFIG_LPS_LCLK
++	    || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode)
++#endif
++	   ) {
++		err = sd_cmd52_read(pintfhdl, ftaddr, cnt, pbuf);
++		return err;
++	}
++
++	/* 4 bytes alignment */
++	shift = ftaddr & 0x3;
++	if (shift == 0)
++		err = sd_read(pintfhdl, ftaddr, cnt, pbuf);
++	else {
++		u8 *ptmpbuf;
++		u32 n;
++
++		ftaddr &= ~(u16)0x3;
++		n = cnt + shift;
++		ptmpbuf = rtw_malloc(n);
++		if (NULL == ptmpbuf)
++			return -1;
++		err = sd_read(pintfhdl, ftaddr, n, ptmpbuf);
++		if (!err)
++			_rtw_memcpy(pbuf, ptmpbuf + shift, cnt);
++		rtw_mfree(ptmpbuf, n);
++	}
++
++
++	return err;
++}
++
++s32 sdio_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
++{
++	u32 ftaddr;
++	s32 err;
++
++	ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
++	err = 0;
++	sd_write8(pintfhdl, ftaddr, val, &err);
++
++
++	return err;
++}
++
++s32 sdio_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val)
++{
++	u32 ftaddr;
++	u8 shift;
++	s32 err;
++
++	ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
++	val = cpu_to_le16(val);
++	err = sd_cmd52_write(pintfhdl, ftaddr, 2, (u8 *)&val);
++
++
++	return err;
++}
++
++s32 sdio_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
++{
++	PADAPTER padapter;
++	u8 bMacPwrCtrlOn;
++	u8 deviceId;
++	u16 offset;
++	u32 ftaddr;
++	u8 shift;
++	s32 err;
++
++
++	padapter = pintfhdl->padapter;
++	err = 0;
++
++	ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset);
++
++	bMacPwrCtrlOn = _FALSE;
++	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++	if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100))
++	    || (_FALSE == bMacPwrCtrlOn)
++#ifdef CONFIG_LPS_LCLK
++	    || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode)
++#endif
++	   ) {
++		val = cpu_to_le32(val);
++		err = sd_cmd52_write(pintfhdl, ftaddr, 4, (u8 *)&val);
++		return err;
++	}
++
++	/* 4 bytes alignment */
++	shift = ftaddr & 0x3;
++#if 1
++	if (shift == 0)
++		sd_write32(pintfhdl, ftaddr, val, &err);
++	else {
++		val = cpu_to_le32(val);
++		err = sd_cmd52_write(pintfhdl, ftaddr, 4, (u8 *)&val);
++	}
++#else
++	if (shift == 0)
++		sd_write32(pintfhdl, ftaddr, val, &err);
++	else {
++		u8 *ptmpbuf;
++
++		ptmpbuf = (u8 *)rtw_malloc(8);
++		if (NULL == ptmpbuf)
++			return -1;
++
++		ftaddr &= ~(u16)0x3;
++		err = sd_read(pintfhdl, ftaddr, 8, ptmpbuf);
++		if (err) {
++			rtw_mfree(ptmpbuf, 8);
++			return err;
++		}
++		val = cpu_to_le32(val);
++		_rtw_memcpy(ptmpbuf + shift, &val, 4);
++		err = sd_write(pintfhdl, ftaddr, 8, ptmpbuf);
++
++		rtw_mfree(ptmpbuf, 8);
++	}
++#endif
++
++
++	return err;
++}
++
++s32 sdio_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pbuf)
++{
++	PADAPTER padapter;
++	u8 bMacPwrCtrlOn;
++	u8 deviceId;
++	u16 offset;
++	u32 ftaddr;
++	u8 shift;
++	s32 err;
++
++
++	padapter = pintfhdl->padapter;
++	err = 0;
++
++	ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset);
++
++	bMacPwrCtrlOn = _FALSE;
++	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++	if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100))
++	    || (_FALSE == bMacPwrCtrlOn)
++#ifdef CONFIG_LPS_LCLK
++	    || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode)
++#endif
++	   ) {
++		err = sd_cmd52_write(pintfhdl, ftaddr, cnt, pbuf);
++		return err;
++	}
++
++	shift = ftaddr & 0x3;
++	if (shift == 0)
++		err = sd_write(pintfhdl, ftaddr, cnt, pbuf);
++	else {
++		u8 *ptmpbuf;
++		u32 n;
++
++		ftaddr &= ~(u16)0x3;
++		n = cnt + shift;
++		ptmpbuf = rtw_malloc(n);
++		if (NULL == ptmpbuf)
++			return -1;
++		err = sd_read(pintfhdl, ftaddr, 4, ptmpbuf);
++		if (err) {
++			rtw_mfree(ptmpbuf, n);
++			return err;
++		}
++		_rtw_memcpy(ptmpbuf + shift, pbuf, cnt);
++		err = sd_write(pintfhdl, ftaddr, n, ptmpbuf);
++		rtw_mfree(ptmpbuf, n);
++	}
++
++
++	return err;
++}
++
++u8 sdio_f0_read8(struct intf_hdl *pintfhdl, u32 addr)
++{
++	u32 ftaddr;
++	u8 val;
++
++	val = sd_f0_read8(pintfhdl, addr, NULL);
++
++
++	return val;
++}
++
++void sdio_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
++{
++	s32 err;
++
++
++	err = sdio_readN(pintfhdl, addr, cnt, rmem);
++
++}
++
++void sdio_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem)
++{
++
++	sdio_writeN(pintfhdl, addr, cnt, wmem);
++
++}
++
++/*
++ * Description:
++ *	Read from RX FIFO
++ *	Round read size to block size,
++ *	and make sure data transfer will be done in one command.
++ *
++ * Parameters:
++ *	pintfhdl	a pointer of intf_hdl
++ *	addr		port ID
++ *	cnt			size to read
++ *	rmem		address to put data
++ *
++ * Return:
++ *	_SUCCESS(1)		Success
++ *	_FAIL(0)		Fail
++ */
++static u32 sdio_read_port(
++	struct intf_hdl *pintfhdl,
++	u32 addr,
++	u32 cnt,
++	u8 *mem)
++{
++	PADAPTER padapter;
++	PHAL_DATA_TYPE phal;
++	u32 oldcnt;
++#ifdef SDIO_DYNAMIC_ALLOC_MEM
++	u8 *oldmem;
++#endif
++	s32 err;
++
++
++	padapter = pintfhdl->padapter;
++	phal = GET_HAL_DATA(padapter);
++
++	HalSdioGetCmdAddr8723DSdio(padapter, addr, phal->SdioRxFIFOCnt++, &addr);
++
++	oldcnt = cnt;
++	cnt = rtw_sdio_cmd53_align_size(adapter_to_dvobj(padapter), cnt);
++
++	if (oldcnt != cnt) {
++#ifdef SDIO_DYNAMIC_ALLOC_MEM
++		oldmem = mem;
++		mem = rtw_malloc(cnt);
++		if (mem == NULL) {
++			RTW_WARN("%s: allocate memory %d bytes fail!\n",
++				 __func__, cnt);
++			mem = oldmem;
++			oldmem == NULL;
++		}
++#else
++		/* in this case, caller should gurante the buffer is big enough */
++		/* to receive data after alignment */
++#endif
++	}
++
++	err = _sd_read(pintfhdl, addr, cnt, mem);
++
++#ifdef SDIO_DYNAMIC_ALLOC_MEM
++	if ((oldcnt != cnt) && (oldmem)) {
++		_rtw_memcpy(oldmem, mem, oldcnt);
++		rtw_mfree(mem, cnt);
++	}
++#endif
++
++	if (err)
++		return _FAIL;
++	return _SUCCESS;
++}
++
++/*
++ * Description:
++ *	Write to TX FIFO
++ *	Align write size block size,
++ *	and make sure data could be written in one command.
++ *
++ * Parameters:
++ *	pintfhdl	a pointer of intf_hdl
++ *	addr		port ID
++ *	cnt			size to write
++ *	wmem		data pointer to write
++ *
++ * Return:
++ *	_SUCCESS(1)		Success
++ *	_FAIL(0)		Fail
++ */
++static u32 sdio_write_port(
++	struct intf_hdl *pintfhdl,
++	u32 addr,
++	u32 cnt,
++	u8 *mem)
++{
++	PADAPTER padapter;
++	s32 err;
++	struct xmit_buf *xmitbuf = (struct xmit_buf *)mem;
++
++	padapter = pintfhdl->padapter;
++
++#ifndef CONFIG_DLFW_TXPKT
++	if (!rtw_is_hw_init_completed(padapter)) {
++		RTW_INFO("%s [addr=0x%x cnt=%d] hw_init_completed is FALSE\n",
++			 __func__, addr, cnt);
++		return _FAIL;
++	}
++#endif
++
++	cnt = _RND4(cnt);
++	HalSdioGetCmdAddr8723DSdio(padapter, addr, cnt >> 2, &addr);
++
++	cnt = rtw_sdio_cmd53_align_size(adapter_to_dvobj(padapter), cnt);
++
++	err = sd_write(pintfhdl, addr, cnt, xmitbuf->pdata);
++
++	rtw_sctx_done_err(&xmitbuf->sctx,
++		  err ? RTW_SCTX_DONE_WRITE_PORT_ERR : RTW_SCTX_DONE_SUCCESS);
++
++	if (err)
++		return _FAIL;
++	return _SUCCESS;
++}
++
++void sdio_set_intf_ops(_adapter *padapter, struct _io_ops *pops)
++{
++
++	pops->_read8 = &sdio_read8;
++	pops->_read16 = &sdio_read16;
++	pops->_read32 = &sdio_read32;
++	pops->_read_mem = &sdio_read_mem;
++	pops->_read_port = &sdio_read_port;
++
++	pops->_write8 = &sdio_write8;
++	pops->_write16 = &sdio_write16;
++	pops->_write32 = &sdio_write32;
++	pops->_writeN = &sdio_writeN;
++	pops->_write_mem = &sdio_write_mem;
++	pops->_write_port = &sdio_write_port;
++
++	pops->_sd_f0_read8 = sdio_f0_read8;
++
++}
++
++/*
++ * Todo: align address to 4 bytes.
++ */
++s32 _sdio_local_read(
++	PADAPTER	padapter,
++	u32			addr,
++	u32			cnt,
++	u8			*pbuf)
++{
++	struct intf_hdl *pintfhdl;
++	u8 bMacPwrCtrlOn;
++	s32 err;
++	u8 *ptmpbuf;
++	u32 n;
++
++
++	pintfhdl = &padapter->iopriv.intf;
++
++	HalSdioGetCmdAddr8723DSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
++
++	bMacPwrCtrlOn = _FALSE;
++	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++	if (_FALSE == bMacPwrCtrlOn) {
++		err = _sd_cmd52_read(pintfhdl, addr, cnt, pbuf);
++		return err;
++	}
++
++	n = RND4(cnt);
++	ptmpbuf = (u8 *)rtw_malloc(n);
++	if (!ptmpbuf)
++		return -1;
++
++	err = _sd_read(pintfhdl, addr, n, ptmpbuf);
++	if (!err)
++		_rtw_memcpy(pbuf, ptmpbuf, cnt);
++
++	if (ptmpbuf)
++		rtw_mfree(ptmpbuf, n);
++
++	return err;
++}
++
++/*
++ * Todo: align address to 4 bytes.
++ */
++s32 sdio_local_read(
++	PADAPTER	padapter,
++	u32			addr,
++	u32			cnt,
++	u8			*pbuf)
++{
++	struct intf_hdl *pintfhdl;
++	u8 bMacPwrCtrlOn;
++	s32 err;
++	u8 *ptmpbuf;
++	u32 n;
++
++	pintfhdl = &padapter->iopriv.intf;
++
++	HalSdioGetCmdAddr8723DSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
++
++	bMacPwrCtrlOn = _FALSE;
++	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++	if ((_FALSE == bMacPwrCtrlOn)
++#ifdef CONFIG_LPS_LCLK
++	    || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode)
++#endif
++	   ) {
++		err = sd_cmd52_read(pintfhdl, addr, cnt, pbuf);
++		return err;
++	}
++
++	n = RND4(cnt);
++	ptmpbuf = (u8 *)rtw_malloc(n);
++	if (!ptmpbuf)
++		return -1;
++
++	err = sd_read(pintfhdl, addr, n, ptmpbuf);
++	if (!err)
++		_rtw_memcpy(pbuf, ptmpbuf, cnt);
++
++	if (ptmpbuf)
++		rtw_mfree(ptmpbuf, n);
++
++	return err;
++}
++
++/*
++ * Todo: align address to 4 bytes.
++ */
++s32 _sdio_local_write(
++	PADAPTER	padapter,
++	u32			addr,
++	u32			cnt,
++	u8			*pbuf)
++{
++	struct intf_hdl *pintfhdl;
++	u8 bMacPwrCtrlOn;
++	s32 err;
++	u8 *ptmpbuf;
++
++	if (addr & 0x3)
++		RTW_INFO("%s, address must be 4 bytes alignment\n", __func__);
++
++	if (cnt  & 0x3)
++		RTW_INFO("%s, size must be the multiple of 4\n", __func__);
++
++	pintfhdl = &padapter->iopriv.intf;
++
++	HalSdioGetCmdAddr8723DSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
++
++	bMacPwrCtrlOn = _FALSE;
++	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++	if ((_FALSE == bMacPwrCtrlOn)
++#ifdef CONFIG_LPS_LCLK
++	    || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode)
++#endif
++	   ) {
++		err = _sd_cmd52_write(pintfhdl, addr, cnt, pbuf);
++		return err;
++	}
++
++	ptmpbuf = (u8 *)rtw_malloc(cnt);
++	if (!ptmpbuf)
++		return -1;
++
++	_rtw_memcpy(ptmpbuf, pbuf, cnt);
++
++	err = _sd_write(pintfhdl, addr, cnt, ptmpbuf);
++
++	if (ptmpbuf)
++		rtw_mfree(ptmpbuf, cnt);
++
++	return err;
++}
++
++/*
++ * Todo: align address to 4 bytes.
++ */
++s32 sdio_local_write(
++	PADAPTER	padapter,
++	u32		addr,
++	u32		cnt,
++	u8		*pbuf)
++{
++	struct intf_hdl *pintfhdl;
++	u8 bMacPwrCtrlOn;
++	s32 err;
++	u8 *ptmpbuf;
++
++	if (addr & 0x3)
++		RTW_INFO("%s, address must be 4 bytes alignment\n", __func__);
++
++	if (cnt  & 0x3)
++		RTW_INFO("%s, size must be the multiple of 4\n", __func__);
++
++	pintfhdl = &padapter->iopriv.intf;
++
++	HalSdioGetCmdAddr8723DSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
++
++	bMacPwrCtrlOn = _FALSE;
++	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++	if ((_FALSE == bMacPwrCtrlOn)
++#ifdef CONFIG_LPS_LCLK
++	    || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode)
++#endif
++	   ) {
++		err = sd_cmd52_write(pintfhdl, addr, cnt, pbuf);
++		return err;
++	}
++
++	ptmpbuf = (u8 *)rtw_malloc(cnt);
++	if (!ptmpbuf)
++		return -1;
++
++	_rtw_memcpy(ptmpbuf, pbuf, cnt);
++
++	err = sd_write(pintfhdl, addr, cnt, ptmpbuf);
++
++	if (ptmpbuf)
++		rtw_mfree(ptmpbuf, cnt);
++
++	return err;
++}
++
++u8 SdioLocalCmd52Read1Byte(PADAPTER padapter, u32 addr)
++{
++	u8 val = 0;
++	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
++
++	HalSdioGetCmdAddr8723DSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
++	sd_cmd52_read(pintfhdl, addr, 1, &val);
++
++	return val;
++}
++
++u16 SdioLocalCmd52Read2Byte(PADAPTER padapter, u32 addr)
++{
++	u16 val = 0;
++	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
++
++	HalSdioGetCmdAddr8723DSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
++	sd_cmd52_read(pintfhdl, addr, 2, (u8 *)&val);
++
++	val = le16_to_cpu(val);
++
++	return val;
++}
++
++u32 SdioLocalCmd52Read4Byte(PADAPTER padapter, u32 addr)
++{
++	u32 val = 0;
++	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
++
++	HalSdioGetCmdAddr8723DSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
++	sd_cmd52_read(pintfhdl, addr, 4, (u8 *)&val);
++
++	val = le32_to_cpu(val);
++
++	return val;
++}
++
++u32 SdioLocalCmd53Read4Byte(PADAPTER padapter, u32 addr)
++{
++
++	u8 bMacPwrCtrlOn;
++	u32 val = 0;
++	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
++
++	HalSdioGetCmdAddr8723DSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
++	bMacPwrCtrlOn = _FALSE;
++	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++	if ((_FALSE == bMacPwrCtrlOn)
++#ifdef CONFIG_LPS_LCLK
++	    || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode)
++#endif
++	   ) {
++		sd_cmd52_read(pintfhdl, addr, 4, (u8 *)&val);
++		val = le32_to_cpu(val);
++	} else
++		val = sd_read32(pintfhdl, addr, NULL);
++
++	return val;
++}
++
++void SdioLocalCmd52Write1Byte(PADAPTER padapter, u32 addr, u8 v)
++{
++	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
++
++	HalSdioGetCmdAddr8723DSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
++	sd_cmd52_write(pintfhdl, addr, 1, &v);
++}
++
++void SdioLocalCmd52Write2Byte(PADAPTER padapter, u32 addr, u16 v)
++{
++	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
++
++	HalSdioGetCmdAddr8723DSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
++	v = cpu_to_le16(v);
++	sd_cmd52_write(pintfhdl, addr, 2, (u8 *)&v);
++}
++
++void SdioLocalCmd52Write4Byte(PADAPTER padapter, u32 addr, u32 v)
++{
++	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
++
++	HalSdioGetCmdAddr8723DSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
++	v = cpu_to_le32(v);
++	sd_cmd52_write(pintfhdl, addr, 4, (u8 *)&v);
++}
++
++#if 0
++void
++DumpLoggedInterruptHistory8723Sdio(
++	PADAPTER		padapter
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	u32				DebugLevel = DBG_LOUD;
++
++	if (DBG_Var.DbgPrintIsr == 0)
++		return;
++
++	DBG_ChkDrvResource(padapter);
++
++
++
++}
++
++void
++LogInterruptHistory8723Sdio(
++	PADAPTER			padapter,
++	PRT_ISR_CONTENT	pIsrContent
++)
++{
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_RX_REQUEST_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_RX_REQUEST))
++		pHalData->InterruptLog.nISR_RX_REQUEST++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_AVAL_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_AVAL))
++		pHalData->InterruptLog.nISR_AVAL++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_TXERR_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_TXERR))
++		pHalData->InterruptLog.nISR_TXERR++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_RXERR_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_RXERR))
++		pHalData->InterruptLog.nISR_RXERR++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_TXFOVW_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_TXFOVW))
++		pHalData->InterruptLog.nISR_TXFOVW++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_RXFOVW_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_RXFOVW))
++		pHalData->InterruptLog.nISR_RXFOVW++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_TXBCNOK_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_TXBCNOK))
++		pHalData->InterruptLog.nISR_TXBCNOK++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_TXBCNERR_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_TXBCNERR))
++		pHalData->InterruptLog.nISR_TXBCNERR++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_BCNERLY_INT_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_BCNERLY_INT))
++		pHalData->InterruptLog.nISR_BCNERLY_INT++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_C2HCMD_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_C2HCMD))
++		pHalData->InterruptLog.nISR_C2HCMD++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_CPWM1_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_CPWM1))
++		pHalData->InterruptLog.nISR_CPWM1++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_CPWM2_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_CPWM2))
++		pHalData->InterruptLog.nISR_CPWM2++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_HSISR_IND_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_HSISR_IND))
++		pHalData->InterruptLog.nISR_HSISR_IND++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_GTINT3_IND_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_GTINT3_IND))
++		pHalData->InterruptLog.nISR_GTINT3_IND++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_GTINT4_IND_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_GTINT4_IND))
++		pHalData->InterruptLog.nISR_GTINT4_IND++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_PSTIMEOUT_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_PSTIMEOUT))
++		pHalData->InterruptLog.nISR_PSTIMEOUT++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_OCPINT_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_OCPINT))
++		pHalData->InterruptLog.nISR_OCPINT++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_ATIMEND_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_ATIMEND))
++		pHalData->InterruptLog.nISR_ATIMEND++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_ATIMEND_E_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_ATIMEND_E))
++		pHalData->InterruptLog.nISR_ATIMEND_E++;
++	if ((pHalData->IntrMask[0] & SDIO_HIMR_CTWEND_MSK) &&
++	    (pIsrContent->IntArray[0] & SDIO_HISR_CTWEND))
++		pHalData->InterruptLog.nISR_CTWEND++;
++
++}
++
++void
++DumpHardwareProfile8723Sdio(
++		PADAPTER		padapter
++)
++{
++	DumpLoggedInterruptHistory8723Sdio(padapter);
++}
++#endif
++
++#ifndef CMD52_ACCESS_HISR_RX_REQ_LEN
++#define CMD52_ACCESS_HISR_RX_REQ_LEN 0
++#endif
++
++#if CMD52_ACCESS_HISR_RX_REQ_LEN
++static s32 ReadInterrupt8723DSdio(PADAPTER padapter, u32 *phisr)
++{
++	u32 hisr, himr;
++	u8 val8, hisr_len;
++
++
++	if (phisr == NULL)
++		return _FALSE;
++
++	himr = GET_HAL_DATA(padapter)->sdio_himr;
++
++	/* decide how many bytes need to be read */
++	hisr_len = 0;
++	while (himr) {
++		hisr_len++;
++		himr >>= 8;
++	}
++
++	hisr = 0;
++	while (hisr_len != 0) {
++		hisr_len--;
++		val8 = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HISR + hisr_len);
++		hisr |= (val8 << (8 * hisr_len));
++	}
++
++	*phisr = hisr;
++
++	return _TRUE;
++}
++#endif /*#if CMD52_ACCESS_HISR_RX_REQ_LEN*/
++/*
++ *	Description:
++ *		Initialize SDIO Host Interrupt Mask configuration variables for future use.
++ *
++ *	Assumption:
++ *		Using SDIO Local register ONLY for configuration.
++ *
++ *	Created by Roger, 2011.02.11.
++ *   */
++void InitInterrupt8723DSdio(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE pHalData;
++
++
++	pHalData = GET_HAL_DATA(padapter);
++	pHalData->sdio_himr = (u32)(
++				      SDIO_HIMR_RX_REQUEST_MSK			|
++#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
++				      SDIO_HIMR_AVAL_MSK					|
++#endif
++				      /*								SDIO_HIMR_TXERR_MSK				|
++				       *								SDIO_HIMR_RXERR_MSK				|
++				       *								SDIO_HIMR_TXFOVW_MSK				|
++				       *								SDIO_HIMR_RXFOVW_MSK				|
++				       *								SDIO_HIMR_TXBCNOK_MSK				|
++				       *								SDIO_HIMR_TXBCNERR_MSK			|
++				       *								SDIO_HIMR_BCNERLY_INT_MSK			|
++				       *								SDIO_HIMR_C2HCMD_MSK				| */
++#if defined(CONFIG_LPS_LCLK) && !defined(CONFIG_DETECT_CPWM_BY_POLLING)
++				      SDIO_HIMR_CPWM1_MSK				|
++				      /*								SDIO_HIMR_CPWM2_MSK				| */
++#endif /* CONFIG_LPS_LCLK && !CONFIG_DETECT_CPWM_BY_POLLING
++ *								SDIO_HIMR_HSISR_IND_MSK			|
++ *								SDIO_HIMR_GTINT3_IND_MSK			|
++ *								SDIO_HIMR_GTINT4_IND_MSK			|
++ *								SDIO_HIMR_PSTIMEOUT_MSK			|
++ *								SDIO_HIMR_OCPINT_MSK				|
++ *								SDIO_HIMR_ATIMEND_MSK				|
++ *								SDIO_HIMR_ATIMEND_E_MSK			|
++ *								SDIO_HIMR_CTWEND_MSK				| */
++				      0);
++}
++
++/*
++ *	Description:
++ *		Initialize System Host Interrupt Mask configuration variables for future use.
++ *
++ *	Created by Roger, 2011.08.03.
++ *   */
++void InitSysInterrupt8723DSdio(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE pHalData;
++
++
++	pHalData = GET_HAL_DATA(padapter);
++
++	pHalData->SysIntrMask = (
++					/*							HSIMR_GPIO12_0_INT_EN			|
++					 *							HSIMR_SPS_OCP_INT_EN			|
++					 *							HSIMR_RON_INT_EN				|
++					 *							HSIMR_PDNINT_EN				|
++					 *							HSIMR_GPIO9_INT_EN				| */
++					0);
++}
++
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++/*
++ *	Description:
++ *		Clear corresponding SDIO Host ISR interrupt service.
++ *
++ *	Assumption:
++ *		Using SDIO Local register ONLY for configuration.
++ *
++ *	Created by Roger, 2011.02.11.
++ *   */
++void ClearInterrupt8723DSdio(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE pHalData;
++	u8 *clear;
++	u8 val_8 = 0;
++	u32 val_32 = 0;
++
++	if (rtw_is_surprise_removed(padapter))
++		return;
++
++	pHalData = GET_HAL_DATA(padapter);
++	clear = rtw_zmalloc(4);
++
++	/* Clear corresponding HISR Content if needed */
++	val_8 = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HISR + 2);
++
++	val_32 = pHalData->sdio_hisr & MASK_SDIO_HISR_CLEAR;
++
++	if (val_8 && BIT3)
++		*(u32 *)clear = cpu_to_le32(val_32 | SDIO_HISR_CPWM2);
++	else
++		*(u32 *)clear = cpu_to_le32(val_32);
++
++	if (*(u32 *)clear) {
++		/* Perform write one clear operation */
++		sdio_local_write(padapter, SDIO_REG_HISR, 4, clear);
++	}
++
++	rtw_mfree(clear, 4);
++}
++#endif
++
++/*
++ *	Description:
++ *		Clear corresponding system Host ISR interrupt service.
++ *
++ *
++ *	Created by Roger, 2011.02.11.
++ *   */
++void ClearSysInterrupt8723DSdio(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE pHalData;
++	u32 clear;
++
++
++	if (rtw_is_surprise_removed(padapter))
++		return;
++
++	pHalData = GET_HAL_DATA(padapter);
++
++	/* Clear corresponding HISR Content if needed */
++	clear = pHalData->SysIntrStatus & MASK_HSISR_CLEAR;
++	if (clear) {
++		/* Perform write one clear operation */
++		rtw_write32(padapter, REG_HSISR, clear);
++	}
++}
++
++/*
++ *	Description:
++ *		Enalbe SDIO Host Interrupt Mask configuration on SDIO local domain.
++ *
++ *	Assumption:
++ *		1. Using SDIO Local register ONLY for configuration.
++ *		2. PASSIVE LEVEL
++ *
++ *	Created by Roger, 2011.02.11.
++ *   */
++void EnableInterrupt8723DSdio(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE pHalData;
++	u32 himr;
++
++	pHalData = GET_HAL_DATA(padapter);
++
++	himr = cpu_to_le32(pHalData->sdio_himr);
++	sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr);
++
++
++	/* Update current system IMR settings */
++	himr = rtw_read32(padapter, REG_HSIMR);
++	rtw_write32(padapter, REG_HSIMR, himr | pHalData->SysIntrMask);
++
++
++	/* */
++	/* <Roger_Notes> There are some C2H CMDs have been sent before system interrupt is enabled, e.g., C2H, CPWM. */
++	/* So we need to clear all C2H events that FW has notified, otherwise FW won't schedule any commands anymore. */
++	/* 2011.10.19. */
++	/* */
++	rtw_write8(padapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
++}
++
++/*
++ *	Description:
++ *		Disable SDIO Host IMR configuration to mask unnecessary interrupt service.
++ *
++ *	Assumption:
++ *		Using SDIO Local register ONLY for configuration.
++ *
++ *	Created by Roger, 2011.02.11.
++ *   */
++void DisableInterrupt8723DSdio(PADAPTER padapter)
++{
++	u32 himr;
++
++	himr = cpu_to_le32(SDIO_HIMR_DISABLED);
++	sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr);
++
++}
++
++/*
++ *	Description:
++ *		Using 0x100 to check the power status of FW.
++ *
++ *	Assumption:
++ *		Using SDIO Local register ONLY for configuration.
++ *
++ *	Created by Isaac, 2013.09.10.
++ *   */
++u8 CheckIPSStatus(PADAPTER padapter)
++{
++	RTW_INFO("%s(): Read 0x100=0x%02x 0x86=0x%02x\n", __func__,
++		 rtw_read8(padapter, 0x100), rtw_read8(padapter, 0x86));
++
++	if (rtw_read8(padapter, 0x100) == 0xEA)
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++#ifdef CONFIG_WOWLAN
++void DisableInterruptButCpwm28723DSdio(PADAPTER padapter)
++{
++	u32 himr, tmp;
++
++	sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
++	RTW_INFO("DisableInterruptButCpwm28723DSdio(): Read SDIO_REG_HIMR: 0x%08x\n", tmp);
++
++	himr = cpu_to_le32(SDIO_HIMR_DISABLED) | SDIO_HIMR_CPWM2_MSK;
++	sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr);
++
++	sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
++	RTW_INFO("DisableInterruptButCpwm28723DSdio(): Read again SDIO_REG_HIMR: 0x%08x\n", tmp);
++}
++#endif /* CONFIG_WOWLAN
++ *
++ *	Description:
++ *		Update SDIO Host Interrupt Mask configuration on SDIO local domain.
++ *
++ *	Assumption:
++ *		1. Using SDIO Local register ONLY for configuration.
++ *		2. PASSIVE LEVEL
++ *
++ *	Created by Roger, 2011.02.11.
++ *   */
++void UpdateInterruptMask8723DSdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR)
++{
++	HAL_DATA_TYPE *pHalData;
++
++	pHalData = GET_HAL_DATA(padapter);
++
++	if (AddMSR)
++		pHalData->sdio_himr |= AddMSR;
++
++	if (RemoveMSR)
++		pHalData->sdio_himr &= (~RemoveMSR);
++
++	DisableInterrupt8723DSdio(padapter);
++	EnableInterrupt8723DSdio(padapter);
++}
++
++#ifdef CONFIG_MAC_LOOPBACK_DRIVER
++static void sd_recv_loopback(PADAPTER padapter, u32 size)
++{
++	PLOOPBACKDATA ploopback;
++	u32 readsize, allocsize;
++	u8 *preadbuf;
++
++
++	readsize = size;
++	RTW_INFO("%s: read size=%d\n", __func__, readsize);
++	allocsize = _RND(readsize, rtw_sdio_get_block_size(adapter_to_dvobj(padapter)));
++
++	ploopback = padapter->ploopback;
++	if (ploopback) {
++		ploopback->rxsize = readsize;
++		preadbuf = ploopback->rxbuf;
++	} else {
++		preadbuf = rtw_malloc(allocsize);
++		if (preadbuf == NULL) {
++			RTW_INFO("%s: malloc fail size=%d\n", __func__, allocsize);
++			return;
++		}
++	}
++
++	/*	rtw_read_port(padapter, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf); */
++	sdio_read_port(&padapter->iopriv.intf, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf);
++
++	if (ploopback)
++		_rtw_up_sema(&ploopback->sema);
++	else {
++		u32 i;
++
++		RTW_INFO("%s: drop pkt\n", __func__);
++		for (i = 0; i < readsize; i += 4) {
++			RTW_INFO("%08X", *(u32 *)(preadbuf + i));
++			if ((i + 4) & 0x1F)
++				printk(KERN_ERR " ");
++			else
++				printk(KERN_ERR "\n");
++		}
++		printk(KERN_ERR "\n");
++		rtw_mfree(preadbuf, allocsize);
++	}
++}
++#endif /* CONFIG_MAC_LOOPBACK_DRIVER */
++
++#ifdef CONFIG_SDIO_RX_COPY
++static u32 sd_recv_rxfifo(PADAPTER padapter, u32 size,
++			  struct recv_buf **recvbuf_ret)
++{
++	u32 readsize, ret;
++	u8 *preadbuf;
++	struct recv_priv *precvpriv;
++	struct recv_buf	*precvbuf;
++
++	*recvbuf_ret = NULL;
++
++#if 0
++	readsize = size;
++#else
++	/* Patch for some SDIO Host 4 bytes issue */
++	/* ex. RK3188 */
++	readsize = RND4(size);
++#endif
++
++	/* 3 1. alloc recvbuf */
++	precvpriv = &padapter->recvpriv;
++	precvbuf = rtw_dequeue_recvbuf(&precvpriv->free_recv_buf_queue);
++	if (precvbuf == NULL) {
++		RTW_INFO("%s: recvbuf unavailable\n", __func__);
++		ret = RTW_RBUF_UNAVAIL;
++		goto exit;
++	}
++
++	/* 3 2. alloc skb */
++	if (precvbuf->pskb == NULL) {
++		SIZE_PTR tmpaddr = 0;
++		SIZE_PTR alignment = 0;
++
++		precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
++		if (precvbuf->pskb == NULL) {
++			RTW_INFO("%s: alloc_skb fail! read=%d\n", __func__, readsize);
++			rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue);
++			ret = RTW_RBUF_PKT_UNAVAIL;
++			goto exit;
++		}
++
++		precvbuf->pskb->dev = padapter->pnetdev;
++
++		tmpaddr = (SIZE_PTR)precvbuf->pskb->data;
++		alignment = tmpaddr & (RECVBUFF_ALIGN_SZ - 1);
++		skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment));
++	}
++
++	/* 3 3. read data from rxfifo */
++	preadbuf = precvbuf->pskb->data;
++	/*	rtw_read_port(padapter, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf); */
++	ret = sdio_read_port(&padapter->iopriv.intf, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf);
++	if (ret == _FAIL) {
++		rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue);
++		goto exit;
++	}
++
++	/* 3 4. init recvbuf */
++	precvbuf->len = size;
++	precvbuf->phead = precvbuf->pskb->head;
++	precvbuf->pdata = precvbuf->pskb->data;
++	skb_set_tail_pointer(precvbuf->pskb, size);
++	precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
++	precvbuf->pend = skb_end_pointer(precvbuf->pskb);
++
++	*recvbuf_ret = precvbuf;
++exit:
++	return ret;
++}
++#else /* !CONFIG_SDIO_RX_COPY */
++static struct recv_buf *sd_recv_rxfifo(PADAPTER padapter, u32 size)
++{
++	u32 readsize, allocsize, ret;
++	u8 *preadbuf;
++	_pkt *ppkt;
++	struct recv_priv *precvpriv;
++	struct recv_buf	*precvbuf;
++
++
++#if 0
++	readsize = size;
++#else
++	/* Patch for some SDIO Host 4 bytes issue */
++	/* ex. RK3188 */
++	readsize = RND4(size);
++#endif
++
++	/* 3 1. alloc skb */
++	/* align to block size */
++	allocsize = rtw_sdio_cmd53_align_size(adapter_to_dvobj(padapter), readsize);
++
++	ppkt = rtw_skb_alloc(allocsize);
++
++	if (ppkt == NULL) {
++		return NULL;
++	}
++
++	/* 3 2. read data from rxfifo */
++	preadbuf = skb_put(ppkt, size);
++	/*	rtw_read_port(padapter, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf); */
++	ret = sdio_read_port(&padapter->iopriv.intf, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf);
++	if (ret == _FAIL) {
++		rtw_skb_free(ppkt);
++		return NULL;
++	}
++
++	/* 3 3. alloc recvbuf */
++	precvpriv = &padapter->recvpriv;
++	precvbuf = rtw_dequeue_recvbuf(&precvpriv->free_recv_buf_queue);
++	if (precvbuf == NULL) {
++		rtw_skb_free(ppkt);
++		RTW_ERR("%s: alloc recvbuf FAIL!\n", __func__);
++		return NULL;
++	}
++
++	/* 3 4. init recvbuf */
++	precvbuf->pskb = ppkt;
++
++	precvbuf->len = ppkt->len;
++
++	precvbuf->phead = ppkt->head;
++	precvbuf->pdata = ppkt->data;
++	precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
++	precvbuf->pend = skb_end_pointer(precvbuf->pskb);
++
++	return precvbuf;
++}
++#endif /* !CONFIG_SDIO_RX_COPY */
++
++static void sd_rxhandler(PADAPTER padapter, struct recv_buf *precvbuf)
++{
++	struct recv_priv *precvpriv;
++	_queue *ppending_queue;
++
++
++	precvpriv = &padapter->recvpriv;
++	ppending_queue = &precvpriv->recv_buf_pending_queue;
++
++	/* 3 1. enqueue recvbuf */
++	rtw_enqueue_recvbuf(precvbuf, ppending_queue);
++
++	/* 3 2. trigger recv hdl */
++#ifdef CONFIG_RECV_THREAD_MODE
++	_rtw_up_sema(&precvpriv->recv_sema);
++#else
++	#ifdef PLATFORM_LINUX
++	tasklet_schedule(&precvpriv->recv_tasklet);
++	#endif /* PLATFORM_LINUX */
++#endif /* CONFIG_RECV_THREAD_MODE */
++}
++
++
++#ifndef SD_INT_HDL_DIS_HIMR_RX_REQ
++#define SD_INT_HDL_DIS_HIMR_RX_REQ 1
++#endif
++
++#if SD_INT_HDL_DIS_HIMR_RX_REQ
++static void disable_himr_rx_req_8723d_sdio(_adapter *adapter)
++{
++	HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
++	u32 himr = cpu_to_le32(hal->sdio_himr & ~SDIO_HISR_RX_REQUEST);
++
++	SdioLocalCmd52Write1Byte(adapter, SDIO_REG_HIMR, *((u8 *)&himr));
++}
++static void restore_himr_8723d_sdio(_adapter *adapter)
++{
++	HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
++	u32 himr = cpu_to_le32(hal->sdio_himr);
++
++	SdioLocalCmd52Write1Byte(adapter, SDIO_REG_HIMR, *((u8 *)&himr));
++}
++#endif
++#ifdef CONFIG_RECV_THREAD_MODE
++static u32 sdio_recv_and_drop(PADAPTER padapter, u32 size)
++{
++	u32 readsz, blksz, bufsz;
++	u8 *rbuf;
++	s32 ret = _SUCCESS;
++
++	/*
++	 * Patch for some SDIO Host 4 bytes issue
++	 * ex. RK3188
++	 */
++	readsz = RND4(size);
++
++	/* round to block size */
++	blksz = adapter_to_dvobj(padapter)->intf_data.block_transfer_len;
++	if (readsz > blksz)
++		bufsz = _RND(readsz, blksz);
++	else
++		bufsz = readsz;
++
++	rbuf = rtw_zmalloc(bufsz);
++	if (NULL == rbuf) {
++		RTW_ERR("%s: NULL == rbuf!\n", __FUNCTION__);
++		ret = _FAIL;
++		goto _exit;
++	}
++
++	ret = sdio_read_port(&padapter->iopriv.intf, WLAN_RX0FF_DEVICE_ID, bufsz, rbuf);
++	if (_FAIL == ret)
++		RTW_ERR("%s: read port FAIL!\n", __FUNCTION__);
++
++	if (NULL != rbuf)
++		rtw_mfree(rbuf, bufsz);
++
++_exit:
++	return ret;
++}
++#endif
++void sd_recv(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE phal = GET_HAL_DATA(padapter);
++	struct recv_buf *precvbuf;
++	int alloc_fail_time = 0;
++	u32 rx_cnt = 0;
++
++	do {
++		if (phal->SdioRxFIFOSize == 0) {
++			#if CMD52_ACCESS_HISR_RX_REQ_LEN
++			u16 rx_req_len;
++
++			rx_req_len = SdioLocalCmd52Read2Byte(padapter, SDIO_REG_RX0_REQ_LEN);
++			if (rx_req_len) {
++				if (rx_req_len % 256 == 0)
++					rx_req_len += SdioLocalCmd52Read1Byte(padapter, SDIO_REG_RX0_REQ_LEN);
++				phal->SdioRxFIFOSize = rx_req_len;
++			}
++			#else
++			u8 data[4];
++
++			_sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, data);
++			phal->SdioRxFIFOSize = le16_to_cpu(*(u16 *)data);
++			#endif
++		}
++
++		if (phal->SdioRxFIFOSize != 0) {
++			u32 ret;
++
++			#ifdef CONFIG_MAC_LOOPBACK_DRIVER
++			sd_recv_loopback(padapter, phal->SdioRxFIFOSize);
++			#else
++			ret = sd_recv_rxfifo(padapter, phal->SdioRxFIFOSize, &precvbuf);
++			if (precvbuf) {
++				sd_rxhandler(padapter, precvbuf);
++				phal->SdioRxFIFOSize = 0;
++				rx_cnt++;
++			} else {
++				alloc_fail_time++;
++#ifdef CONFIG_RECV_THREAD_MODE
++					if (alloc_fail_time >= 10) {
++						if (_FAIL == sdio_recv_and_drop(padapter, phal->SdioRxFIFOSize))
++							break;
++		
++						alloc_fail_time = 0;
++						phal->SdioRxFIFOSize = 0;
++						rx_cnt = 0;
++						RTW_INFO("%s RECV_THREAD_MODE drop pkt due to alloc_fail_time >= 10 \n",__func__);
++					} else {
++						rtw_msleep_os(1);
++						continue;
++					}
++#else /* !CONFIG_RECV_THREAD_MODE */
++				if (ret == RTW_RBUF_UNAVAIL || ret == RTW_RBUF_PKT_UNAVAIL)
++					rtw_msleep_os(10);
++				else {
++					RTW_INFO("%s: recv fail!(time=%d)\n", __func__, alloc_fail_time);
++					phal->SdioRxFIFOSize = 0;
++				}
++				if (alloc_fail_time >= 10 && rx_cnt != 0)
++					break;
++#endif /* !CONFIG_RECV_THREAD_MODE */
++			}
++			#endif
++		} else
++			break;
++	} while (1);
++
++	if (alloc_fail_time >= 10)
++		RTW_INFO("%s: exit because recv failed more than 10 times!, rx_cnt:%u\n", __func__, rx_cnt);
++}
++void sd_int_dpc(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE phal;
++	struct dvobj_priv *dvobj;
++	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
++	struct pwrctrl_priv *pwrctl;
++
++
++	phal = GET_HAL_DATA(padapter);
++	dvobj = adapter_to_dvobj(padapter);
++	pwrctl = dvobj_to_pwrctl(dvobj);
++
++#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
++	if (phal->sdio_hisr & SDIO_HISR_AVAL) {
++		/* _irqL irql; */
++		u8 freepage[4];
++
++		_sdio_local_read(padapter, SDIO_REG_FREE_TXPG, 4, freepage);
++		#ifdef DBG_TX_FREE_PAGE
++		RTW_INFO("SDIO_HISR_AVAL, Tx Free Page = H:%u, M:%u, L:%u, P:%u\n",
++			freepage[0], freepage[1], freepage[2], freepage[3]);
++		#endif
++
++		_rtw_up_sema(&(padapter->xmitpriv.xmit_sema));
++	}
++#endif
++	if (phal->sdio_hisr & SDIO_HISR_CPWM1) {
++		struct reportpwrstate_parm report;
++
++#ifdef CONFIG_LPS_RPWM_TIMER
++		_cancel_timer_ex(&(pwrctl->pwr_rpwm_timer));
++#endif /* CONFIG_LPS_RPWM_TIMER */
++
++		report.state = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HCPWM1_8723D);
++
++#ifdef CONFIG_LPS_LCLK
++		/* cpwm_int_hdl(padapter, &report); */
++		_set_workitem(&(pwrctl->cpwm_event));
++#endif
++	}
++
++	if (phal->sdio_hisr & SDIO_HISR_TXERR) {
++		u8 *status;
++		u32 addr;
++
++		status = rtw_malloc(4);
++		if (status) {
++			addr = REG_TXDMA_STATUS;
++			HalSdioGetCmdAddr8723DSdio(padapter, WLAN_IOREG_DEVICE_ID, addr, &addr);
++			_sd_read(pintfhdl, addr, 4, status);
++			_sd_write(pintfhdl, addr, 4, status);
++			RTW_INFO("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, le32_to_cpu(*(u32 *)status));
++			rtw_mfree(status, 4);
++		} else
++			RTW_INFO("%s: SDIO_HISR_TXERR, but can't allocate memory to read status!\n", __func__);
++	}
++
++	if (phal->sdio_hisr & SDIO_HISR_TXBCNOK)
++		RTW_INFO("%s: SDIO_HISR_TXBCNOK\n", __func__);
++
++	if (phal->sdio_hisr & SDIO_HISR_TXBCNERR)
++		RTW_INFO("%s: SDIO_HISR_TXBCNERR\n", __func__);
++
++#ifdef CONFIG_FW_C2H_REG
++	if (phal->sdio_hisr & SDIO_HISR_C2HCMD) {
++		RTW_INFO("%s: C2H Command\n", __func__);
++		sd_c2h_hisr_hdl(padapter);
++	}
++#endif
++
++	if (phal->sdio_hisr & SDIO_HISR_RXFOVW)
++		RTW_INFO("%s: Rx Overflow\n", __func__);
++	if (phal->sdio_hisr & SDIO_HISR_RXERR)
++		RTW_INFO("%s: Rx Error\n", __func__);
++
++	if (phal->sdio_hisr & SDIO_HISR_RX_REQUEST) {
++		phal->sdio_hisr ^= SDIO_HISR_RX_REQUEST;
++		sd_recv(padapter);
++	}
++}
++#ifndef DBG_SD_INT_HISR_HIMR
++#define DBG_SD_INT_HISR_HIMR 0
++#endif
++void sd_int_hdl(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE phal;
++	#if !CMD52_ACCESS_HISR_RX_REQ_LEN
++	u8 data[6];
++	#endif
++
++	if (RTW_CANNOT_RUN(padapter))
++		return;
++
++	phal = GET_HAL_DATA(padapter);
++
++	#if SD_INT_HDL_DIS_HIMR_RX_REQ
++	disable_himr_rx_req_8723d_sdio(padapter);
++	#endif
++
++	#if CMD52_ACCESS_HISR_RX_REQ_LEN
++	phal->sdio_hisr = 0;
++	ReadInterrupt8723DSdio(padapter, &phal->sdio_hisr);
++	#else
++	_sdio_local_read(padapter, SDIO_REG_HISR, 6, data);
++	phal->sdio_hisr = le32_to_cpu(*(u32 *)data);
++	phal->SdioRxFIFOSize = le16_to_cpu(*(u16 *)&data[4]);
++	#endif
++	
++	if (phal->sdio_hisr & phal->sdio_himr) {
++		u32 v32;
++		#if DBG_SD_INT_HISR_HIMR
++		static u32 match_cnt = 0;
++
++		if ((match_cnt++) % 1000 == 0)
++			RTW_INFO("%s: HISR(0x%08x) and HIMR(0x%08x) match!\n"
++				, __func__, phal->sdio_hisr, phal->sdio_himr);
++		#endif
++		
++		phal->sdio_hisr &= phal->sdio_himr;
++
++		/* clear HISR */
++		v32 = phal->sdio_hisr & MASK_SDIO_HISR_CLEAR;
++		if (v32) {
++			#if CMD52_ACCESS_HISR_RX_REQ_LEN
++			SdioLocalCmd52Write4Byte(padapter, SDIO_REG_HISR, v32);
++			#else
++			v32 = cpu_to_le32(v32);
++			_sdio_local_write(padapter, SDIO_REG_HISR, 4, (u8 *)&v32);
++			#endif
++		}
++
++		sd_int_dpc(padapter);
++	}
++	#if DBG_SD_INT_HISR_HIMR
++	else
++		RTW_INFO("%s: HISR(0x%08x) and HIMR(0x%08x) not match!\n"
++			, __func__, phal->sdio_hisr, phal->sdio_himr);
++	#endif
++
++	#if SD_INT_HDL_DIS_HIMR_RX_REQ
++	restore_himr_8723d_sdio(padapter);
++	#endif	
++}
++
++/*
++ *	Description:
++ *		Query SDIO Local register to query current the number of Free TxPacketBuffer page.
++ *
++ *	Assumption:
++ *		1. Running at PASSIVE_LEVEL
++ *		2. RT_TX_SPINLOCK is NOT acquired.
++ *
++ *	Created by Roger, 2011.01.28.
++ *   */
++u8 HalQueryTxBufferStatus8723DSdio(PADAPTER padapter)
++{
++	PHAL_DATA_TYPE phal;
++	u32 NumOfFreePage;
++	/* _irqL irql; */
++
++
++	phal = GET_HAL_DATA(padapter);
++
++	NumOfFreePage = SdioLocalCmd53Read4Byte(padapter, SDIO_REG_FREE_TXPG);
++
++	/* _enter_critical_bh(&phal->SdioTxFIFOFreePageLock, &irql); */
++	_rtw_memcpy(phal->SdioTxFIFOFreePage, &NumOfFreePage, 4);
++	/* _exit_critical_bh(&phal->SdioTxFIFOFreePageLock, &irql); */
++
++	return _TRUE;
++}
++
++/*
++ *	Description:
++ *		Query SDIO Local register to get the current number of TX OQT Free Space.
++ *   */
++u8 HalQueryTxOQTBufferStatus8723DSdio(PADAPTER padapter)
++{
++	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++	pHalData->SdioTxOQTFreeSpace = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_OQT_FREE_PG);
++	return _TRUE;
++}
++
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++u8 RecvOnePkt(PADAPTER padapter)
++{
++	struct recv_buf *precvbuf;
++	struct dvobj_priv *psddev;
++	PSDIO_DATA psdio_data;
++	struct sdio_func *func;
++	u32 tmp = 0;
++	u16 len = 0;
++	u8 res = _FALSE;
++
++	if (padapter == NULL) {
++		RTW_ERR("%s: padapter is NULL!\n", __func__);
++		return _FALSE;
++	}
++
++	psddev = adapter_to_dvobj(padapter);
++	psdio_data = &psddev->intf_data;
++	func = psdio_data->func;
++
++	/* If RX_DMA is not idle, receive one pkt from DMA */
++	res = sdio_local_read(padapter,
++			  SDIO_REG_RX0_REQ_LEN, 4, (u8 *)&tmp);
++	len = le16_to_cpu(tmp);
++	RTW_INFO("+%s: size: %d+\n", __func__, len);
++
++	if (len) {
++		sdio_claim_host(func);
++		res = sd_recv_rxfifo(padapter, len, &precvbuf);
++
++		if (precvbuf) {
++			/* printk("Completed Recv One Pkt.\n"); */
++			sd_rxhandler(padapter, precvbuf);
++			res = _TRUE;
++		} else
++			res = _FALSE;
++		sdio_release_host(func);
++	}
++	RTW_INFO("-%s-\n", __func__);
++	return res;
++}
++#endif /* CONFIG_WOWLAN */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/ifcfg-wlan0 b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/ifcfg-wlan0
+new file mode 100644
+index 000000000..7ecb7ae62
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/ifcfg-wlan0
+@@ -0,0 +1,4 @@
++#DHCP client
++DEVICE=wlan0
++BOOTPROTO=dhcp
++ONBOOT=yes
+\ No newline at end of file
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188EPhyCfg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188EPhyCfg.h
+new file mode 100644
+index 000000000..38983f751
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188EPhyCfg.h
+@@ -0,0 +1,249 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8188EPHYCFG_H__
++#define __INC_HAL8188EPHYCFG_H__
++
++
++/*--------------------------Define Parameters-------------------------------*/
++#define LOOP_LIMIT				5
++#define MAX_STALL_TIME			50		/* us */
++#define AntennaDiversityValue		0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
++#define MAX_TXPWR_IDX_NMODE_92S	63
++#define Reset_Cnt_Limit			3
++
++#ifdef CONFIG_PCI_HCI
++	#define MAX_AGGR_NUM	0x0B
++#else
++	#define MAX_AGGR_NUM	0x07
++#endif /* CONFIG_PCI_HCI */
++
++
++/*--------------------------Define Parameters-------------------------------*/
++
++
++/*------------------------------Define structure----------------------------*/
++
++#define	MAX_TX_COUNT_8188E			1
++
++/* BB/RF related */
++
++
++/*------------------------------Define structure----------------------------*/
++
++
++/*------------------------Export global variable----------------------------*/
++/*------------------------Export global variable----------------------------*/
++
++
++/*------------------------Export Marco Definition---------------------------*/
++/*------------------------Export Marco Definition---------------------------*/
++
++
++/*--------------------------Exported Function prototype---------------------*/
++/*
++ * BB and RF register read/write
++ *   */
++u32	PHY_QueryBBReg8188E(PADAPTER	Adapter,
++				u32		RegAddr,
++				u32		BitMask);
++void	PHY_SetBBReg8188E(PADAPTER	Adapter,
++				u32		RegAddr,
++				u32		BitMask,
++				u32		Data);
++u32	PHY_QueryRFReg8188E(PADAPTER	Adapter,
++				enum rf_path		eRFPath,
++				u32				RegAddr,
++				u32				BitMask);
++void	PHY_SetRFReg8188E(PADAPTER		Adapter,
++				enum rf_path		eRFPath,
++				u32				RegAddr,
++				u32				BitMask,
++				u32				Data);
++
++/*
++ * Initialization related function
++ */
++/* MAC/BB/RF HAL config */
++int	PHY_MACConfig8188E(PADAPTER	Adapter);
++int	PHY_BBConfig8188E(PADAPTER	Adapter);
++int	PHY_RFConfig8188E(PADAPTER	Adapter);
++
++/* RF config */
++int	rtl8188e_PHY_ConfigRFWithParaFile( PADAPTER Adapter, u8 *pFileName, enum rf_path eRFPath);
++
++/*
++ * RF Power setting
++ */
++/* extern	BOOLEAN	PHY_SetRFPowerState(PADAPTER			Adapter,
++ *										RT_RF_POWER_STATE	eRFPowerState); */
++
++/*
++ * BB TX Power R/W
++ *   */
++void	PHY_SetTxPowerLevel8188E(PADAPTER		Adapter,
++					u8			channel);
++
++void
++PHY_SetTxPowerIndex_8188E(
++		PADAPTER			Adapter,
++		u32					PowerIndex,
++		enum rf_path			RFPath,
++		u8					Rate
++);
++
++s8 phy_get_txpwr_target_extra_bias_8188e(_adapter *adapter, enum rf_path rfpath
++	, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch);
++
++/*
++ * Switch bandwidth for 8192S
++ */
++/* extern	void	PHY_SetBWModeCallback8192C(PRT_TIMER		pTimer	); */
++void	PHY_SetBWMode8188E(PADAPTER			pAdapter,
++				enum channel_width	ChnlWidth,
++				unsigned char	Offset);
++
++/*
++ * Set FW CMD IO for 8192S.
++ */
++/* extern	BOOLEAN HalSetIO8192C(PADAPTER			Adapter,
++ *								IO_TYPE				IOType); */
++
++/*
++ * Set A2 entry to fw for 8192S
++ *   */
++extern	void FillA2Entry8192C(PADAPTER			Adapter,
++				u8				index,
++				u8				*val);
++
++
++/*
++ * channel switch related funciton
++ */
++/* extern	void	PHY_SwChnlCallback8192C(PRT_TIMER		pTimer	); */
++void	PHY_SwChnl8188E(PADAPTER		pAdapter,
++				u8			channel);
++
++void
++PHY_SetSwChnlBWMode8188E(
++		PADAPTER			Adapter,
++		u8					channel,
++		enum channel_width	Bandwidth,
++		u8					Offset40,
++		u8					Offset80
++);
++
++void
++PHY_SetRFEReg_8188E(
++		PADAPTER		Adapter
++);
++/*
++ * BB/MAC/RF other monitor API
++ *   */
++void phy_set_rf_path_switch_8188e(struct dm_struct	*phydm, bool		bMain);
++
++extern	void
++PHY_SwitchEphyParameter(
++		PADAPTER			Adapter
++);
++
++extern	void
++PHY_EnableHostClkReq(
++		PADAPTER			Adapter
++);
++
++BOOLEAN
++SetAntennaConfig92C(
++		PADAPTER	Adapter,
++		u8		DefaultAnt
++);
++
++/*--------------------------Exported Function prototype---------------------*/
++
++/*
++ * Initialization related function
++ *
++ * MAC/BB/RF HAL config */
++/* extern s32 PHY_MACConfig8723(PADAPTER padapter);
++ * s32 PHY_BBConfig8723(PADAPTER padapter);
++ * s32 PHY_RFConfig8723(PADAPTER padapter); */
++
++
++
++/* ******************************************************************
++ * Note: If SIC_ENABLE under PCIE, because of the slow operation
++ *	you should
++ * 	2) "#define RTL8723_FPGA_VERIFICATION	1"				in Precomp.h.WlanE.Windows
++ * 	3) "#define RTL8190_Download_Firmware_From_Header	0"	in Precomp.h.WlanE.Windows if needed.
++ *   */
++#if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1)
++	#define	SIC_ENABLE				1
++	#define	SIC_HW_SUPPORT		1
++#else
++	#define	SIC_ENABLE				0
++	#define	SIC_HW_SUPPORT		0
++#endif
++/* ****************************************************************** */
++
++
++#define	SIC_MAX_POLL_CNT		5
++
++#if (SIC_HW_SUPPORT == 1)
++	#define	SIC_CMD_READY			0
++	#define	SIC_CMD_PREWRITE		0x1
++	#if (RTL8188E_SUPPORT == 1)
++		#define	SIC_CMD_WRITE			0x40
++		#define	SIC_CMD_PREREAD		0x2
++		#define	SIC_CMD_READ			0x80
++		#define	SIC_CMD_INIT			0xf0
++		#define	SIC_INIT_VAL			0xff
++
++		#define	SIC_INIT_REG			0x1b7
++		#define	SIC_CMD_REG			0x1EB		/* 1byte */
++		#define	SIC_ADDR_REG			0x1E8		/* 1b4~1b5, 2 bytes */
++		#define	SIC_DATA_REG			0x1EC		/* 1b0~1b3 */
++	#else
++		#define	SIC_CMD_WRITE			0x11
++		#define	SIC_CMD_PREREAD		0x2
++		#define	SIC_CMD_READ			0x12
++		#define	SIC_CMD_INIT			0x1f
++		#define	SIC_INIT_VAL			0xff
++
++		#define	SIC_INIT_REG			0x1b7
++		#define	SIC_CMD_REG			0x1b6		/* 1byte */
++		#define	SIC_ADDR_REG			0x1b4		/* 1b4~1b5, 2 bytes */
++		#define	SIC_DATA_REG			0x1b0		/* 1b0~1b3 */
++	#endif
++#else
++	#define	SIC_CMD_READY			0
++	#define	SIC_CMD_WRITE			1
++	#define	SIC_CMD_READ			2
++
++	#if (RTL8188E_SUPPORT == 1)
++		#define	SIC_CMD_REG			0x1EB		/* 1byte */
++		#define	SIC_ADDR_REG			0x1E8		/* 1b9~1ba, 2 bytes */
++		#define	SIC_DATA_REG			0x1EC		/* 1bc~1bf */
++	#else
++		#define	SIC_CMD_REG			0x1b8		/* 1byte */
++		#define	SIC_ADDR_REG			0x1b9		/* 1b9~1ba, 2 bytes */
++		#define	SIC_DATA_REG			0x1bc		/* 1bc~1bf */
++	#endif
++#endif
++
++#if (SIC_ENABLE == 1)
++	void SIC_Init( PADAPTER Adapter);
++#endif
++
++
++#endif /* __INC_HAL8192CPHYCFG_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188EPhyReg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188EPhyReg.h
+new file mode 100644
+index 000000000..2eab8313a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188EPhyReg.h
+@@ -0,0 +1,1100 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8188EPHYREG_H__
++#define __INC_HAL8188EPHYREG_H__
++/*--------------------------Define Parameters-------------------------------*/
++/*
++ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
++ * 3. RF register 0x00-2E
++ * 4. Bit Mask for BB/RF register
++ * 5. Other defintion for BB/RF R/W
++ *   */
++
++
++/*
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 1. Page1(0x100)
++ *   */
++#define		rPMAC_Reset					0x100
++#define		rPMAC_TxStart				0x104
++#define		rPMAC_TxLegacySIG			0x108
++#define		rPMAC_TxHTSIG1				0x10c
++#define		rPMAC_TxHTSIG2				0x110
++#define		rPMAC_PHYDebug				0x114
++#define		rPMAC_TxPacketNum			0x118
++#define		rPMAC_TxIdle					0x11c
++#define		rPMAC_TxMACHeader0			0x120
++#define		rPMAC_TxMACHeader1			0x124
++#define		rPMAC_TxMACHeader2			0x128
++#define		rPMAC_TxMACHeader3			0x12c
++#define		rPMAC_TxMACHeader4			0x130
++#define		rPMAC_TxMACHeader5			0x134
++#define		rPMAC_TxDataType				0x138
++#define		rPMAC_TxRandomSeed			0x13c
++#define		rPMAC_CCKPLCPPreamble		0x140
++#define		rPMAC_CCKPLCPHeader			0x144
++#define		rPMAC_CCKCRC16				0x148
++#define		rPMAC_OFDMRxCRC32OK		0x170
++#define		rPMAC_OFDMRxCRC32Er		0x174
++#define		rPMAC_OFDMRxParityEr			0x178
++#define		rPMAC_OFDMRxCRC8Er			0x17c
++#define		rPMAC_CCKCRxRC16Er			0x180
++#define		rPMAC_CCKCRxRC32Er			0x184
++#define		rPMAC_CCKCRxRC32OK			0x188
++#define		rPMAC_TxStatus				0x18c
++
++/*
++ * 2. Page2(0x200)
++ *
++ * The following two definition are only used for USB interface. */
++#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
++#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
++
++/*
++ * 3. Page8(0x800)
++ *   */
++#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
++
++#define		rFPGA0_TxInfo					0x804	/* Status report?? */
++#define		rFPGA0_PSDFunction			0x808
++
++#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
++
++#define		rFPGA0_RFTiming1				0x810	/* Useless now */
++#define		rFPGA0_RFTiming2				0x814
++
++#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
++#define		rFPGA0_XA_HSSIParameter2		0x824
++#define		rFPGA0_XB_HSSIParameter1		0x828
++#define		rFPGA0_XB_HSSIParameter2		0x82c
++
++#define		rFPGA0_XA_LSSIParameter		0x840
++#define		rFPGA0_XB_LSSIParameter		0x844
++
++#define		rFPGA0_RFWakeUpParameter	0x850	/* Useless now */
++#define		rFPGA0_RFSleepUpParameter		0x854
++
++#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
++#define		rFPGA0_XCD_SwitchControl		0x85c
++
++#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
++#define		rFPGA0_XB_RFInterfaceOE		0x864
++#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
++#define		rFPGA0_XCD_RFInterfaceSW		0x874
++
++#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
++#define		rFPGA0_XCD_RFParameter		0x87c
++
++#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
++#define		rFPGA0_AnalogParameter2		0x884
++#define		rFPGA0_AnalogParameter3		0x888
++#define		rFPGA0_AdDaClockEn			0x888	/* enable ad/da clock1 for dual-phy */
++#define		rFPGA0_AnalogParameter4		0x88c
++
++#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
++#define		rFPGA0_XB_LSSIReadBack		0x8a4
++#define		rFPGA0_XC_LSSIReadBack		0x8a8
++#define		rFPGA0_XD_LSSIReadBack		0x8ac
++
++#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
++#define		TransceiverA_HSPI_Readback		0x8b8	/* Transceiver A HSPI Readback */
++#define		TransceiverB_HSPI_Readback		0x8bc	/* Transceiver B HSPI Readback */
++#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
++#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
++
++/*
++ * 4. Page9(0x900)
++ *   */
++#define		rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
++
++#define		rFPGA1_TxBlock				0x904	/* Useless now */
++#define		rFPGA1_DebugSelect			0x908	/* Useless now */
++#define		rFPGA1_TxInfo					0x90c	/* Useless now */ /* Status report?? */
++
++/*
++ * 5. PageA(0xA00)
++ *
++ * Set Control channel to upper or lower. These settings are required only for 40MHz */
++#define		rCCK0_System					0xa00
++
++#define		rCCK0_AFESetting				0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
++#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
++
++#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
++#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
++
++#define		rCCK0_RxHP					0xa14
++
++#define		rCCK0_DSPParameter1			0xa18	/* Timing recovery & Channel estimation threshold */
++#define		rCCK0_DSPParameter2			0xa1c	/* SQ threshold */
++
++#define		rCCK0_TxFilter1				0xa20
++#define		rCCK0_TxFilter2				0xa24
++#define		rCCK0_DebugPort				0xa28	/* debug port and Tx filter3 */
++#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
++#define		rCCK0_TRSSIReport			0xa50
++#define		rCCK0_RxReport            			0xa54  /* 0xa57 */
++#define		rCCK0_FACounterLower      		0xa5c  /* 0xa5b */
++#define		rCCK0_FACounterUpper      		0xa58  /* 0xa5c */
++
++/*
++ * PageB(0xB00)
++ *   */
++#define		rPdp_AntA					0xb00
++#define		rPdp_AntA_4				0xb04
++#define		rConfig_Pmpd_AntA			0xb28
++#define		rConfig_ram64x16				0xb2c
++#define		rConfig_AntA					0xb68
++#define		rConfig_AntB					0xb6c
++#define		rPdp_AntB					0xb70
++#define		rPdp_AntB_4					0xb74
++#define		rConfig_Pmpd_AntB			0xb98
++#define		rAPK							0xbd8
++
++
++
++/*
++ * 6. PageC(0xC00)
++ *   */
++#define		rOFDM0_LSTF					0xc00
++
++#define		rOFDM0_TRxPathEnable			0xc04
++#define		rOFDM0_TRMuxPar				0xc08
++#define		rOFDM0_TRSWIsolation			0xc0c
++
++#define		rOFDM0_XARxAFE				0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
++#define		rOFDM0_XARxIQImbalance    		0xc14  /* RxIQ imblance matrix */
++#define		rOFDM0_XBRxAFE			0xc18
++#define		rOFDM0_XBRxIQImbalance		0xc1c
++#define		rOFDM0_XCRxAFE			0xc20
++#define		rOFDM0_XCRxIQImbalance		0xc24
++#define		rOFDM0_XDRxAFE			0xc28
++#define		rOFDM0_XDRxIQImbalance		0xc2c
++
++#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
++#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
++#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
++#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
++
++#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
++#define		rOFDM0_CFOandDAGC			0xc44  /* CFO & DAGC */
++#define		rOFDM0_CCADropThreshold		0xc48 /* CCA Drop threshold */
++#define		rOFDM0_ECCAThreshold			0xc4c /* energy CCA */
++
++#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
++#define		rOFDM0_XAAGCCore2			0xc54
++#define		rOFDM0_XBAGCCore1			0xc58
++#define		rOFDM0_XBAGCCore2			0xc5c
++#define		rOFDM0_XCAGCCore1			0xc60
++#define		rOFDM0_XCAGCCore2			0xc64
++#define		rOFDM0_XDAGCCore1			0xc68
++#define		rOFDM0_XDAGCCore2			0xc6c
++
++#define		rOFDM0_AGCParameter1		0xc70
++#define		rOFDM0_AGCParameter2		0xc74
++#define		rOFDM0_AGCRSSITable			0xc78
++#define		rOFDM0_HTSTFAGC				0xc7c
++
++#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
++#define		rOFDM0_XATxAFE				0xc84
++#define		rOFDM0_XBTxIQImbalance		0xc88
++#define		rOFDM0_XBTxAFE				0xc8c
++#define		rOFDM0_XCTxIQImbalance		0xc90
++#define		rOFDM0_XCTxAFE			0xc94
++#define		rOFDM0_XDTxIQImbalance		0xc98
++#define		rOFDM0_XDTxAFE				0xc9c
++
++#define		rOFDM0_RxIQExtAnta			0xca0
++#define		rOFDM0_TxCoeff1				0xca4
++#define		rOFDM0_TxCoeff2				0xca8
++#define		rOFDM0_TxCoeff3				0xcac
++#define		rOFDM0_TxCoeff4				0xcb0
++#define		rOFDM0_TxCoeff5				0xcb4
++#define		rOFDM0_TxCoeff6				0xcb8
++#define		rOFDM0_RxHPParameter		0xce0
++#define		rOFDM0_TxPseudoNoiseWgt		0xce4
++#define		rOFDM0_FrameSync			0xcf0
++#define		rOFDM0_DFSReport			0xcf4
++
++
++/*
++ * 7. PageD(0xD00)
++ *   */
++#define		rOFDM1_LSTF					0xd00
++#define		rOFDM1_TRxPathEnable			0xd04
++
++#define		rOFDM1_CFO					0xd08	/* No setting now */
++#define		rOFDM1_CSI1					0xd10
++#define		rOFDM1_SBD					0xd14
++#define		rOFDM1_CSI2					0xd18
++#define		rOFDM1_CFOTracking			0xd2c
++#define		rOFDM1_TRxMesaure1			0xd34
++#define		rOFDM1_IntfDet				0xd3c
++#define		rOFDM1_csi_fix_mask1				0xd40
++#define		rOFDM1_csi_fix_mask2				0xd44
++#define		rOFDM1_PseudoNoiseStateAB	0xd50
++#define		rOFDM1_PseudoNoiseStateCD	0xd54
++#define		rOFDM1_RxPseudoNoiseWgt		0xd58
++
++#define		rOFDM_PHYCounter1			0xda0  /* cca, parity fail */
++#define		rOFDM_PHYCounter2			0xda4  /* rate illegal, crc8 fail */
++#define		rOFDM_PHYCounter3			0xda8  /* MCS not support */
++
++#define		rOFDM_ShortCFOAB			0xdac	/* No setting now */
++#define		rOFDM_ShortCFOCD			0xdb0
++#define		rOFDM_LongCFOAB				0xdb4
++#define		rOFDM_LongCFOCD				0xdb8
++#define		rOFDM_TailCFOAB				0xdbc
++#define		rOFDM_TailCFOCD				0xdc0
++#define		rOFDM_PWMeasure1		0xdc4
++#define		rOFDM_PWMeasure2		0xdc8
++#define		rOFDM_BWReport				0xdcc
++#define		rOFDM_AGCReport				0xdd0
++#define		rOFDM_RxSNR				0xdd4
++#define		rOFDM_RxEVMCSI				0xdd8
++#define		rOFDM_SIGReport				0xddc
++
++
++/*
++ * 8. PageE(0xE00)
++ *   */
++#define		rTxAGC_A_Rate18_06			0xe00
++#define		rTxAGC_A_Rate54_24			0xe04
++#define		rTxAGC_A_CCK1_Mcs32			0xe08
++#define		rTxAGC_A_Mcs03_Mcs00		0xe10
++#define		rTxAGC_A_Mcs07_Mcs04		0xe14
++#define		rTxAGC_A_Mcs11_Mcs08		0xe18
++#define		rTxAGC_A_Mcs15_Mcs12		0xe1c
++
++#define		rTxAGC_B_Rate18_06			0x830
++#define		rTxAGC_B_Rate54_24			0x834
++#define		rTxAGC_B_CCK1_55_Mcs32		0x838
++#define		rTxAGC_B_Mcs03_Mcs00		0x83c
++#define		rTxAGC_B_Mcs07_Mcs04		0x848
++#define		rTxAGC_B_Mcs11_Mcs08		0x84c
++#define		rTxAGC_B_Mcs15_Mcs12		0x868
++#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
++
++#define		rFPGA0_IQK					0xe28
++#define		rTx_IQK_Tone_A				0xe30
++#define		rRx_IQK_Tone_A				0xe34
++#define		rTx_IQK_PI_A					0xe38
++#define		rRx_IQK_PI_A					0xe3c
++
++#define		rTx_IQK						0xe40
++#define		rRx_IQK						0xe44
++#define		rIQK_AGC_Pts					0xe48
++#define		rIQK_AGC_Rsp					0xe4c
++#define		rTx_IQK_Tone_B				0xe50
++#define		rRx_IQK_Tone_B				0xe54
++#define		rTx_IQK_PI_B					0xe58
++#define		rRx_IQK_PI_B					0xe5c
++#define		rIQK_AGC_Cont				0xe60
++
++#define		rBlue_Tooth					0xe6c
++#define		rRx_Wait_CCA					0xe70
++#define		rTx_CCK_RFON					0xe74
++#define		rTx_CCK_BBON				0xe78
++#define		rTx_OFDM_RFON				0xe7c
++#define		rTx_OFDM_BBON				0xe80
++#define		rTx_To_Rx					0xe84
++#define		rTx_To_Tx					0xe88
++#define		rRx_CCK						0xe8c
++
++#define		rTx_Power_Before_IQK_A		0xe94
++#define		rTx_Power_After_IQK_A			0xe9c
++
++#define		rRx_Power_Before_IQK_A		0xea0
++#define		rRx_Power_Before_IQK_A_2		0xea4
++#define		rRx_Power_After_IQK_A			0xea8
++#define		rRx_Power_After_IQK_A_2		0xeac
++
++#define		rTx_Power_Before_IQK_B		0xeb4
++#define		rTx_Power_After_IQK_B			0xebc
++
++#define		rRx_Power_Before_IQK_B		0xec0
++#define		rRx_Power_Before_IQK_B_2		0xec4
++#define		rRx_Power_After_IQK_B			0xec8
++#define		rRx_Power_After_IQK_B_2		0xecc
++
++#define		rRx_OFDM					0xed0
++#define		rRx_Wait_RIFS				0xed4
++#define		rRx_TO_Rx					0xed8
++#define		rStandby						0xedc
++#define		rSleep						0xee0
++#define		rPMPD_ANAEN				0xeec
++
++/*
++ * 7. RF Register 0x00-0x2E (RF 8256)
++ * RF-0222D 0x00-3F
++ *
++ * Zebra1 */
++#define		rZebra1_HSSIEnable				0x0	/* Useless now */
++#define		rZebra1_TRxEnable1			0x1
++#define		rZebra1_TRxEnable2			0x2
++#define		rZebra1_AGC					0x4
++#define		rZebra1_ChargePump			0x5
++#define		rZebra1_Channel				0x7	/* RF channel switch */
++
++/* #endif */
++#define		rZebra1_TxGain				0x8	/* Useless now */
++#define		rZebra1_TxLPF					0x9
++#define		rZebra1_RxLPF					0xb
++#define		rZebra1_RxHPFCorner			0xc
++
++/* Zebra4 */
++#define		rGlobalCtrl					0	/* Useless now */
++#define		rRTL8256_TxLPF				19
++#define		rRTL8256_RxLPF				11
++
++/* RTL8258 */
++#define		rRTL8258_TxLPF				0x11	/* Useless now */
++#define		rRTL8258_RxLPF				0x13
++#define		rRTL8258_RSSILPF				0xa
++
++/*
++ * RL6052 Register definition
++ *   */
++#define		RF_AC						0x00	/*  */
++
++#define		RF_IQADJ_G1					0x01	/*  */
++#define		RF_IQADJ_G2					0x02	/*  */
++
++#define		RF_POW_TRSW				0x05	/*  */
++
++#define		RF_GAIN_RX					0x06	/*  */
++#define		RF_GAIN_TX					0x07	/*  */
++
++#define		RF_TXM_IDAC					0x08	/*  */
++#define		RF_IPA_G						0x09	/*  */
++#define		RF_TXBIAS_G					0x0A
++#define		RF_TXPA_AG					0x0B
++#define		RF_IPA_A						0x0C	/*  */
++#define		RF_TXBIAS_A					0x0D
++#define		RF_BS_PA_APSET_G9_G11		0x0E
++#define		RF_BS_IQGEN					0x0F	/*  */
++
++#define		RF_MODE1					0x10	/*  */
++#define		RF_MODE2					0x11	/*  */
++
++#define		RF_RX_AGC_HP				0x12	/*  */
++#define		RF_TX_AGC					0x13	/*  */
++#define		RF_BIAS						0x14	/*  */
++#define		RF_IPA						0x15	/*  */
++#define		RF_TXBIAS					0x16
++#define		RF_POW_ABILITY				0x17	/*  */
++#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
++#define		RF_TOP						0x19	/*  */
++
++#define		RF_RX_G1					0x1A	/*  */
++#define		RF_RX_G2					0x1B	/*  */
++
++#define		RF_RX_BB2					0x1C	/*  */
++#define		RF_RX_BB1					0x1D	/*  */
++
++#define		RF_RCK1						0x1E	/*  */
++#define		RF_RCK2						0x1F	/*  */
++
++#define		RF_TX_G1						0x20	/*  */
++#define		RF_TX_G2						0x21	/*  */
++#define		RF_TX_G3						0x22	/*  */
++
++#define		RF_TX_BB1					0x23	/*  */
++
++#define		RF_T_METER_88E					0x42	/*  */
++#define		RF_T_METER					0x24	/*  */
++
++#define		RF_SYN_G1					0x25	/* RF TX Power control */
++#define		RF_SYN_G2					0x26	/* RF TX Power control */
++#define		RF_SYN_G3					0x27	/* RF TX Power control */
++#define		RF_SYN_G4					0x28	/* RF TX Power control */
++#define		RF_SYN_G5					0x29	/* RF TX Power control */
++#define		RF_SYN_G6					0x2A	/* RF TX Power control */
++#define		RF_SYN_G7					0x2B	/* RF TX Power control */
++#define		RF_SYN_G8					0x2C	/* RF TX Power control */
++
++#define		RF_RCK_OS					0x30	/* RF TX PA control */
++#define		RF_TXPA_G1					0x31	/* RF TX PA control */
++#define		RF_TXPA_G2					0x32	/* RF TX PA control */
++#define		RF_TXPA_G3					0x33	/* RF TX PA control */
++#define		RF_TX_BIAS_A					0x35
++#define		RF_TX_BIAS_D					0x36
++#define		RF_LOBF_9					0x38
++#define		RF_RXRF_A3					0x3C	/*	 */
++#define		RF_TRSW						0x3F
++
++#define		RF_TXRF_A2					0x41
++#define		RF_TXPA_G4					0x46
++#define		RF_TXPA_A4					0x4B
++#define	RF_0x52					0x52
++#define		RF_WE_LUT					0xEF
++
++
++/*
++ * Bit Mask
++ *
++ * 1. Page1(0x100) */
++#define		bBBResetB					0x100	/* Useless now? */
++#define		bGlobalResetB					0x200
++#define		bOFDMTxStart					0x4
++#define		bCCKTxStart					0x8
++#define		bCRC32Debug					0x100
++#define		bPMACLoopback				0x10
++#define		bTxLSIG						0xffffff
++#define		bOFDMTxRate					0xf
++#define		bOFDMTxReserved				0x10
++#define		bOFDMTxLength				0x1ffe0
++#define		bOFDMTxParity				0x20000
++#define		bTxHTSIG1					0xffffff
++#define		bTxHTMCSRate				0x7f
++#define		bTxHTBW						0x80
++#define		bTxHTLength					0xffff00
++#define		bTxHTSIG2					0xffffff
++#define		bTxHTSmoothing				0x1
++#define		bTxHTSounding				0x2
++#define		bTxHTReserved				0x4
++#define		bTxHTAggreation				0x8
++#define		bTxHTSTBC					0x30
++#define		bTxHTAdvanceCoding			0x40
++#define		bTxHTShortGI					0x80
++#define		bTxHTNumberHT_LTF			0x300
++#define		bTxHTCRC8					0x3fc00
++#define		bCounterReset				0x10000
++#define		bNumOfOFDMTx				0xffff
++#define		bNumOfCCKTx					0xffff0000
++#define		bTxIdleInterval				0xffff
++#define		bOFDMService					0xffff0000
++#define		bTxMACHeader				0xffffffff
++#define		bTxDataInit					0xff
++#define		bTxHTMode					0x100
++#define		bTxDataType					0x30000
++#define		bTxRandomSeed				0xffffffff
++#define		bCCKTxPreamble				0x1
++#define		bCCKTxSFD					0xffff0000
++#define		bCCKTxSIG					0xff
++#define		bCCKTxService					0xff00
++#define		bCCKLengthExt					0x8000
++#define		bCCKTxLength					0xffff0000
++#define		bCCKTxCRC16					0xffff
++#define		bCCKTxStatus					0x1
++#define		bOFDMTxStatus				0x2
++
++#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
++
++/* 2. Page8(0x800) */
++#define		bRFMOD						0x1	/* Reg 0x800 rFPGA0_RFMOD */
++#define		bJapanMode					0x2
++#define		bCCKTxSC						0x30
++#define		bCCKEn						0x1000000
++#define		bOFDMEn					0x2000000
++
++#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
++#define		bOFDMTxDACPhase		0x40000
++#define		bXATxAGC				0x3f
++
++#define		bAntennaSelect			0x0300
++
++#define		bXBTxAGC                  				0xf00	/* Reg 80c rFPGA0_TxGainStage */
++#define		bXCTxAGC				0xf000
++#define		bXDTxAGC				0xf0000
++
++#define		bPAStart                  				0xf0000000	/* Useless now */
++#define		bTRStart				0x00f00000
++#define		bRFStart				0x0000f000
++#define		bBBStart				0x000000f0
++#define		bBBCCKStart			0x0000000f
++#define		bPAEnd                    				0xf          /* Reg0x814 */
++#define		bTREnd				0x0f000000
++#define		bRFEnd				0x000f0000
++#define		bCCAMask                  				0x000000f0   /* T2R */
++#define		bR2RCCAMask			0x00000f00
++#define		bHSSI_R2TDelay			0xf8000000
++#define		bHSSI_T2RDelay			0xf80000
++#define		bContTxHSSI               			0x400     /* chane gain at continue Tx */
++#define		bIGFromCCK			0x200
++#define		bAGCAddress			0x3f
++#define		bRxHPTx				0x7000
++#define		bRxHPT2R				0x38000
++#define		bRxHPCCKIni			0xc0000
++#define		bAGCTxCode			0xc00000
++#define		bAGCRxCode			0x300000
++
++#define		b3WireDataLength          			0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
++#define		b3WireAddressLength		0x400
++
++#define		b3WireRFPowerDown         		0x1	/* Useless now
++ * #define bHWSISelect		0x8 */
++#define		b5GPAPEPolarity			0x40000000
++#define		b2GPAPEPolarity			0x80000000
++#define		bRFSW_TxDefaultAnt		0x3
++#define		bRFSW_TxOptionAnt		0x30
++#define		bRFSW_RxDefaultAnt		0x300
++#define		bRFSW_RxOptionAnt		0x3000
++#define		bRFSI_3WireData			0x1
++#define		bRFSI_3WireClock			0x2
++#define		bRFSI_3WireLoad			0x4
++#define		bRFSI_3WireRW			0x8
++#define		bRFSI_3Wire			0xf
++
++#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
++
++#define		bRFSI_TRSW                		0x20	/* Useless now */
++#define		bRFSI_TRSWB		0x40
++#define		bRFSI_ANTSW		0x100
++#define		bRFSI_ANTSWB		0x200
++#define		bRFSI_PAPE			0x400
++#define		bRFSI_PAPE5G		0x800
++#define		bBandSelect			0x1
++#define		bHTSIG2_GI			0x80
++#define		bHTSIG2_Smoothing		0x01
++#define		bHTSIG2_Sounding		0x02
++#define		bHTSIG2_Aggreaton		0x08
++#define		bHTSIG2_STBC		0x30
++#define		bHTSIG2_AdvCoding		0x40
++#define		bHTSIG2_NumOfHTLTF	0x300
++#define		bHTSIG2_CRC8		0x3fc
++#define		bHTSIG1_MCS		0x7f
++#define		bHTSIG1_BandWidth		0x80
++#define		bHTSIG1_HTLength		0xffff
++#define		bLSIG_Rate			0xf
++#define		bLSIG_Reserved		0x10
++#define		bLSIG_Length		0x1fffe
++#define		bLSIG_Parity			0x20
++#define		bCCKRxPhase		0x4
++
++#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
++
++#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
++
++#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
++
++#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
++#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
++#define		bRegulator0Standby		0x1
++#define		bRegulatorPLLStandby	0x2
++#define		bRegulator1Standby		0x4
++#define		bPLLPowerUp		0x8
++#define		bDPLLPowerUp		0x10
++#define		bDA10PowerUp		0x20
++#define		bAD7PowerUp		0x200
++#define		bDA6PowerUp		0x2000
++#define		bXtalPowerUp		0x4000
++#define		b40MDClkPowerUP	0x8000
++#define		bDA6DebugMode		0x20000
++#define		bDA6Swing			0x380000
++
++#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
++
++#define		b80MClkDelay              		0x18000000	/* Useless */
++#define		bAFEWatchDogEnable	0x20000000
++
++#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
++#define		bXtalCap23			0x3
++#define		bXtalCap92x				0x0f000000
++#define		bXtalCap			0x0f000000
++
++#define		bIntDifClkEnable          		0x400	/* Useless */
++#define		bExtSigClkEnable		0x800
++#define		bBandgapMbiasPowerUp	0x10000
++#define		bAD11SHGain		0xc0000
++#define		bAD11InputRange		0x700000
++#define		bAD11OPCurrent		0x3800000
++#define		bIPathLoopback		0x4000000
++#define		bQPathLoopback		0x8000000
++#define		bAFELoopback		0x10000000
++#define		bDA10Swing		0x7e0
++#define		bDA10Reverse		0x800
++#define		bDAClkSource		0x1000
++#define		bAD7InputRange		0x6000
++#define		bAD7Gain			0x38000
++#define		bAD7OutputCMMode	0x40000
++#define		bAD7InputCMMode	0x380000
++#define		bAD7Current		0xc00000
++#define		bRegulatorAdjust		0x7000000
++#define		bAD11PowerUpAtTx	0x1
++#define		bDA10PSAtTx		0x10
++#define		bAD11PowerUpAtRx	0x100
++#define		bDA10PSAtRx		0x1000
++#define		bCCKRxAGCFormat		0x200
++#define		bPSDFFTSamplepPoint	0xc000
++#define		bPSDAverageNum		0x3000
++#define		bIQPathControl		0xc00
++#define		bPSDFreq			0x3ff
++#define		bPSDAntennaPath		0x30
++#define		bPSDIQSwitch		0x40
++#define		bPSDRxTrigger		0x400000
++#define		bPSDTxTrigger		0x80000000
++#define		bPSDSineToneScale		0x7f000000
++#define		bPSDReport		0xffff
++
++/* 3. Page9(0x900) */
++#define		bOFDMTxSC                 		0x30000000	/* Useless */
++#define		bCCKTxOn			0x1
++#define		bOFDMTxOn		0x2
++#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
++#define		bDebugItem                		0xff   /* reset debug page and LWord */
++#define		bAntL				0x10
++#define		bAntNonHT			0x100
++#define		bAntHT1			0x1000
++#define		bAntHT2			0x10000
++#define		bAntHT1S1			0x100000
++#define		bAntNonHTS1		0x1000000
++
++/* 4. PageA(0xA00) */
++#define		bCCKBBMode                		0x3	/* Useless */
++#define		bCCKTxPowerSaving		0x80
++#define		bCCKRxPowerSaving		0x40
++
++#define		bCCKSideBand              		0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
++
++#define		bCCKScramble              		0x8	/* Useless */
++#define		bCCKAntDiversity			0x8000
++#define		bCCKCarrierRecovery		0x4000
++#define		bCCKTxRate			0x3000
++#define		bCCKDCCancel		0x0800
++#define		bCCKISICancel		0x0400
++#define		bCCKMatchFilter		0x0200
++#define		bCCKEqualizer		0x0100
++#define		bCCKPreambleDetect		0x800000
++#define		bCCKFastFalseCCA		0x400000
++#define		bCCKChEstStart		0x300000
++#define		bCCKCCACount		0x080000
++#define		bCCKcs_lim			0x070000
++#define		bCCKBistMode		0x80000000
++#define		bCCKCCAMask		0x40000000
++#define		bCCKTxDACPhase		0x4
++#define		bCCKRxADCPhase         	   	0x20000000   /* r_rx_clk */
++#define		bCCKr_cp_mode0		0x0100
++#define		bCCKTxDCOffset		0xf0
++#define		bCCKRxDCOffset		0xf
++#define		bCCKCCAMode		0xc000
++#define		bCCKFalseCS_lim		0x3f00
++#define		bCCKCS_ratio		0xc00000
++#define		bCCKCorgBit_sel		0x300000
++#define		bCCKPD_lim		0x0f0000
++#define		bCCKNewCCA		0x80000000
++#define		bCCKRxHPofIG		0x8000
++#define		bCCKRxIG			0x7f00
++#define		bCCKLNAPolarity		0x800000
++#define		bCCKRx1stGain		0x7f0000
++#define		bCCKRFExtend              		0x20000000 /* CCK Rx Iinital gain polarity */
++#define		bCCKRxAGCSatLevel		0x1f000000
++#define		bCCKRxAGCSatCount		0xe0
++#define		bCCKRxRFSettle            		0x1f       /* AGCsamp_dly */
++#define		bCCKFixedRxAGC		0x8000
++/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
++#define		bCCKAntennaPolarity		0x2000
++#define		bCCKTxFilterType		0x0c00
++#define		bCCKRxAGCReportType		0x0300
++#define		bCCKRxDAGCEn		0x80000000
++#define		bCCKRxDAGCPeriod		0x20000000
++#define		bCCKRxDAGCSatLevel		0x1f000000
++#define		bCCKTimingRecovery		0x800000
++#define		bCCKTxC0			0x3f0000
++#define		bCCKTxC1			0x3f000000
++#define		bCCKTxC2			0x3f
++#define		bCCKTxC3			0x3f00
++#define		bCCKTxC4			0x3f0000
++#define		bCCKTxC5			0x3f000000
++#define		bCCKTxC6			0x3f
++#define		bCCKTxC7			0x3f00
++#define		bCCKDebugPort		0xff0000
++#define		bCCKDACDebug		0x0f000000
++#define		bCCKFalseAlarmEnable	0x8000
++#define		bCCKFalseAlarmRead	0x4000
++#define		bCCKTRSSI			0x7f
++#define		bCCKRxAGCReport		0xfe
++#define		bCCKRxReport_AntSel	0x80000000
++#define		bCCKRxReport_MFOff	0x40000000
++#define		bCCKRxRxReport_SQLoss	0x20000000
++#define		bCCKRxReport_Pktloss	0x10000000
++#define		bCCKRxReport_Lockedbit	0x08000000
++#define		bCCKRxReport_RateError	0x04000000
++#define		bCCKRxReport_RxRate	0x03000000
++#define		bCCKRxFACounterLower	0xff
++#define		bCCKRxFACounterUpper	0xff000000
++#define		bCCKRxHPAGCStart		0xe000
++#define		bCCKRxHPAGCFinal		0x1c00
++#define		bCCKRxFalseAlarmEnable	0x8000
++#define		bCCKFACounterFreeze	0x4000
++#define		bCCKTxPathSel		0x10000000
++#define		bCCKDefaultRxPath		0xc000000
++#define		bCCKOptionRxPath		0x3000000
++
++/* 5. PageC(0xC00) */
++#define		bNumOfSTF                			0x3	/* Useless */
++#define		bShift_L			0xc0
++#define		bGI_TH			0xc
++#define		bRxPathA			0x1
++#define		bRxPathB			0x2
++#define		bRxPathC			0x4
++#define		bRxPathD			0x8
++#define		bTxPathA			0x1
++#define		bTxPathB			0x2
++#define		bTxPathC			0x4
++#define		bTxPathD			0x8
++#define		bTRSSIFreq			0x200
++#define		bADCBackoff			0x3000
++#define		bDFIRBackoff			0xc000
++#define		bTRSSILatchPhase		0x10000
++#define		bRxIDCOffset			0xff
++#define		bRxQDCOffset		0xff00
++#define		bRxDFIRMode		0x1800000
++#define		bRxDCNFType		0xe000000
++#define		bRXIQImb_A		0x3ff
++#define		bRXIQImb_B			0xfc00
++#define		bRXIQImb_C			0x3f0000
++#define		bRXIQImb_D		0xffc00000
++#define		bDC_dc_Notch		0x60000
++#define		bRxNBINotch		0x1f000000
++#define		bPD_TH			0xf
++#define		bPD_TH_Opt2		0xc000
++#define		bPWED_TH			0x700
++#define		bIfMF_Win_L		0x800
++#define		bPD_Option			0x1000
++#define		bMF_Win_L			0xe000
++#define		bBW_Search_L		0x30000
++#define		bwin_enh_L			0xc0000
++#define		bBW_TH			0x700000
++#define		bED_TH2			0x3800000
++#define		bBW_option			0x4000000
++#define		bRatio_TH			0x18000000
++#define		bWindow_L			0xe0000000
++#define		bSBD_Option		0x1
++#define		bFrame_TH			0x1c
++#define		bFS_Option			0x60
++#define		bDC_Slope_check		0x80
++#define		bFGuard_Counter_DC_L	0xe00
++#define		bFrame_Weight_Short	0x7000
++#define		bSub_Tune			0xe00000
++#define		bFrame_DC_Length		0xe000000
++#define		bSBD_start_offset		0x30000000
++#define		bFrame_TH_2		0x7
++#define		bFrame_GI2_TH		0x38
++#define		bGI2_Sync_en		0x40
++#define		bSarch_Short_Early		0x300
++#define		bSarch_Short_Late		0xc00
++#define		bSarch_GI2_Late		0x70000
++#define		bCFOAntSum		0x1
++#define		bCFOAcc			0x2
++#define		bCFOStartOffset		0xc
++#define		bCFOLookBack		0x70
++#define		bCFOSumWeight		0x80
++#define		bDAGCEnable		0x10000
++#define		bTXIQImb_A			0x3ff
++#define		bTXIQImb_B			0xfc00
++#define		bTXIQImb_C			0x3f0000
++#define		bTXIQImb_D			0xffc00000
++#define		bTxIDCOffset			0xff
++#define		bTxQDCOffset		0xff00
++#define		bTxDFIRMode		0x10000
++#define		bTxPesudoNoiseOn		0x4000000
++#define		bTxPesudoNoise_A		0xff
++#define		bTxPesudoNoise_B		0xff00
++#define		bTxPesudoNoise_C		0xff0000
++#define		bTxPesudoNoise_D		0xff000000
++#define		bCCADropOption		0x20000
++#define		bCCADropThres		0xfff00000
++#define		bEDCCA_H			0xf
++#define		bEDCCA_L			0xf0
++#define		bLambda_ED		0x300
++#define		bRxInitialGain			0x7f
++#define		bRxAntDivEn		0x80
++#define		bRxAGCAddressForLNA	0x7f00
++#define		bRxHighPowerFlow		0x8000
++#define		bRxAGCFreezeThres		0xc0000
++#define		bRxFreezeStep_AGC1	0x300000
++#define		bRxFreezeStep_AGC2	0xc00000
++#define		bRxFreezeStep_AGC3	0x3000000
++#define		bRxFreezeStep_AGC0	0xc000000
++#define		bRxRssi_Cmp_En		0x10000000
++#define		bRxQuickAGCEn		0x20000000
++#define		bRxAGCFreezeThresMode	0x40000000
++#define		bRxOverFlowCheckType	0x80000000
++#define		bRxAGCShift			0x7f
++#define		bTRSW_Tri_Only		0x80
++#define		bPowerThres		0x300
++#define		bRxAGCEn			0x1
++#define		bRxAGCTogetherEn		0x2
++#define		bRxAGCMin		0x4
++#define		bRxHP_Ini			0x7
++#define		bRxHP_TRLNA		0x70
++#define		bRxHP_RSSI			0x700
++#define		bRxHP_BBP1		0x7000
++#define		bRxHP_BBP2		0x70000
++#define		bRxHP_BBP3		0x700000
++#define		bRSSI_H                  			0x7f0000     /* the threshold for high power */
++#define		bRSSI_Gen                			0x7f000000   /* the threshold for ant diversity */
++#define		bRxSettle_TRSW		0x7
++#define		bRxSettle_LNA		0x38
++#define		bRxSettle_RSSI		0x1c0
++#define		bRxSettle_BBP		0xe00
++#define		bRxSettle_RxHP		0x7000
++#define		bRxSettle_AntSW_RSSI	0x38000
++#define		bRxSettle_AntSW		0xc0000
++#define		bRxProcessTime_DAGC	0x300000
++#define		bRxSettle_HSSI		0x400000
++#define		bRxProcessTime_BBPPW	0x800000
++#define		bRxAntennaPowerShift	0x3000000
++#define		bRSSITableSelect		0xc000000
++#define		bRxHP_Final			0x7000000
++#define		bRxHTSettle_BBP		0x7
++#define		bRxHTSettle_HSSI		0x8
++#define		bRxHTSettle_RxHP		0x70
++#define		bRxHTSettle_BBPPW		0x80
++#define		bRxHTSettle_Idle		0x300
++#define		bRxHTSettle_Reserved	0x1c00
++#define		bRxHTRxHPEn		0x8000
++#define		bRxHTAGCFreezeThres	0x30000
++#define		bRxHTAGCTogetherEn	0x40000
++#define		bRxHTAGCMin		0x80000
++#define		bRxHTAGCEn		0x100000
++#define		bRxHTDAGCEn		0x200000
++#define		bRxHTRxHP_BBP		0x1c00000
++#define		bRxHTRxHP_Final		0xe0000000
++#define		bRxPWRatioTH		0x3
++#define		bRxPWRatioEn		0x4
++#define		bRxMFHold			0x3800
++#define		bRxPD_Delay_TH1		0x38
++#define		bRxPD_Delay_TH2		0x1c0
++#define		bRxPD_DC_COUNT_MAX	0x600
++/* #define bRxMF_Hold               0x3800 */
++#define		bRxPD_Delay_TH		0x8000
++#define		bRxProcess_Delay		0xf0000
++#define		bRxSearchrange_GI2_Early	0x700000
++#define		bRxFrame_Guard_Counter_L	0x3800000
++#define		bRxSGI_Guard_L		0xc000000
++#define		bRxSGI_Search_L		0x30000000
++#define		bRxSGI_TH			0xc0000000
++#define		bDFSCnt0			0xff
++#define		bDFSCnt1			0xff00
++#define		bDFSFlag			0xf0000
++#define		bMFWeightSum		0x300000
++#define		bMinIdxTH			0x7f000000
++#define		bDAFormat			0x40000
++#define		bTxChEmuEnable		0x01000000
++#define		bTRSWIsolation_A		0x7f
++#define		bTRSWIsolation_B		0x7f00
++#define		bTRSWIsolation_C		0x7f0000
++#define		bTRSWIsolation_D		0x7f000000
++#define		bExtLNAGain		0x7c00
++
++/* 6. PageE(0xE00) */
++#define		bSTBCEn                  			0x4	/* Useless */
++#define		bAntennaMapping		0x10
++#define		bNss			0x20
++#define		bCFOAntSumD		0x200
++#define		bPHYCounterReset		0x8000000
++#define		bCFOReportGet		0x4000000
++#define		bOFDMContinueTx		0x10000000
++#define		bOFDMSingleCarrier		0x20000000
++#define		bOFDMSingleTone		0x40000000
++/* #define bRxPath1                 0x01 */
++/* #define bRxPath2                 0x02 */
++/* #define bRxPath3                 0x04 */
++/* #define bRxPath4                 0x08 */
++/* #define bTxPath1                 0x10 */
++/* #define bTxPath2                 0x20 */
++#define		bHTDetect			0x100
++#define		bCFOEn			0x10000
++#define		bCFOValue			0xfff00000
++#define		bSigTone_Re			0x3f
++#define		bSigTone_Im			0x7f00
++#define		bCounter_CCA		0xffff
++#define		bCounter_ParityFail		0xffff0000
++#define		bCounter_RateIllegal		0xffff
++#define		bCounter_CRC8Fail		0xffff0000
++#define		bCounter_MCSNoSupport	0xffff
++#define		bCounter_FastSync		0xffff
++#define		bShortCFO			0xfff
++#define		bShortCFOTLength         		12   /* total */
++#define		bShortCFOFLength         		11   /* fraction */
++#define		bLongCFO			0x7ff
++#define		bLongCFOTLength		11
++#define		bLongCFOFLength		11
++#define		bTailCFO			0x1fff
++#define		bTailCFOTLength		13
++#define		bTailCFOFLength		12
++#define		bmax_en_pwdB		0xffff
++#define		bCC_power_dB		0xffff0000
++#define		bnoise_pwdB		0xffff
++#define		bPowerMeasTLength	10
++#define		bPowerMeasFLength	3
++#define		bRx_HT_BW		0x1
++#define		bRxSC			0x6
++#define		bRx_HT			0x8
++#define		bNB_intf_det_on		0x1
++#define		bIntf_win_len_cfg		0x30
++#define		bNB_Intf_TH_cfg		0x1c0
++#define		bRFGain			0x3f
++#define		bTableSel			0x40
++#define		bTRSW			0x80
++#define		bRxSNR_A			0xff
++#define		bRxSNR_B			0xff00
++#define		bRxSNR_C			0xff0000
++#define		bRxSNR_D			0xff000000
++#define		bSNREVMTLength		8
++#define		bSNREVMFLength		1
++#define		bCSI1st			0xff
++#define		bCSI2nd			0xff00
++#define		bRxEVM1st			0xff0000
++#define		bRxEVM2nd		0xff000000
++#define		bSIGEVM			0xff
++#define		bPWDB			0xff00
++#define		bSGIEN			0x10000
++
++#define		bSFactorQAM1             		0xf	/* Useless */
++#define		bSFactorQAM2		0xf0
++#define		bSFactorQAM3		0xf00
++#define		bSFactorQAM4		0xf000
++#define		bSFactorQAM5		0xf0000
++#define		bSFactorQAM6		0xf0000
++#define		bSFactorQAM7		0xf00000
++#define		bSFactorQAM8		0xf000000
++#define		bSFactorQAM9		0xf0000000
++#define		bCSIScheme			0x100000
++
++#define		bNoiseLvlTopSet          		0x3	/* Useless */
++#define		bChSmooth			0x4
++#define		bChSmoothCfg1		0x38
++#define		bChSmoothCfg2		0x1c0
++#define		bChSmoothCfg3		0xe00
++#define		bChSmoothCfg4		0x7000
++#define		bMRCMode		0x800000
++#define		bTHEVMCfg			0x7000000
++
++#define		bLoopFitType             			0x1	/* Useless */
++#define		bUpdCFO			0x40
++#define		bUpdCFOOffData		0x80
++#define		bAdvUpdCFO		0x100
++#define		bAdvTimeCtrl		0x800
++#define		bUpdClko			0x1000
++#define		bFC				0x6000
++#define		bTrackingMode		0x8000
++#define		bPhCmpEnable		0x10000
++#define		bUpdClkoLTF			0x20000
++#define		bComChCFO		0x40000
++#define		bCSIEstiMode		0x80000
++#define		bAdvUpdEqz		0x100000
++#define		bUChCfg			0x7000000
++#define		bUpdEqz			0x8000000
++
++/* Rx Pseduo noise */
++#define		bRxPesudoNoiseOn         		0x20000000	/* Useless */
++#define		bRxPesudoNoise_A		0xff
++#define		bRxPesudoNoise_B		0xff00
++#define		bRxPesudoNoise_C		0xff0000
++#define		bRxPesudoNoise_D		0xff000000
++#define		bPesudoNoiseState_A	0xffff
++#define		bPesudoNoiseState_B	0xffff0000
++#define		bPesudoNoiseState_C		0xffff
++#define		bPesudoNoiseState_D	0xffff0000
++
++/* 7. RF Register
++ * Zebra1 */
++#define		bZebra1_HSSIEnable        		0x8		/* Useless */
++#define		bZebra1_TRxControl		0xc00
++#define		bZebra1_TRxGainSetting	0x07f
++#define		bZebra1_RxCorner		0xc00
++#define		bZebra1_TxChargePump	0x38
++#define		bZebra1_RxChargePump	0x7
++#define		bZebra1_ChannelNum	0xf80
++#define		bZebra1_TxLPFBW		0x400
++#define		bZebra1_RxLPFBW		0x600
++
++/* Zebra4 */
++#define		bRTL8256RegModeCtrl1      	0x100	/* Useless */
++#define		bRTL8256RegModeCtrl0	0x40
++#define		bRTL8256_TxLPFBW	0x18
++#define		bRTL8256_RxLPFBW	0x600
++
++/* RTL8258 */
++#define		bRTL8258_TxLPFBW          	0xc	/* Useless */
++#define		bRTL8258_RxLPFBW	0xc00
++#define		bRTL8258_RSSILPFBW	0xc0
++
++
++/*
++ * Other Definition
++ *   */
++
++/* byte endable for sb_write */
++#define		bByte0                    			0x1	/* Useless */
++#define		bByte1			0x2
++#define		bByte2			0x4
++#define		bByte3			0x8
++#define		bWord0			0x3
++#define		bWord1			0xc
++#define		bDWord			0xf
++
++/* for PutRegsetting & GetRegSetting BitMask */
++#define		bMaskByte0                		0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
++#define		bMaskByte1		0xff00
++#define		bMaskByte2		0xff0000
++#define		bMaskByte3		0xff000000
++#define		bMaskHWord		0xffff0000
++#define		bMaskLWord		0x0000ffff
++#define		bMaskDWord		0xffffffff
++#define		bMaskH3Bytes				0xffffff00
++#define		bMask12Bits				0xfff
++#define		bMaskH4Bits				0xf0000000
++#define		bMaskOFDM_D			0xffc00000
++#define		bMaskCCK				0x3f3f3f3f
++
++
++
++#define		bEnable                   0x1	/* Useless */
++#define		bDisable                  0x0
++
++#define		LeftAntenna               			0x0	/* Useless */
++#define		RightAntenna		0x1
++
++#define		tCheckTxStatus            		500   /* 500ms */ /* Useless */
++#define		tUpdateRxCounter          		100   /* 100ms */
++
++#define		rateCCK     				0	/* Useless */
++#define		rateOFDM				1
++#define		rateHT					2
++
++/* define Register-End */
++#define		bPMAC_End                 		0x1ff	/* Useless */
++#define		bFPGAPHY0_End		0x8ff
++#define		bFPGAPHY1_End		0x9ff
++#define		bCCKPHY0_End		0xaff
++#define		bOFDMPHY0_End		0xcff
++#define		bOFDMPHY1_End		0xdff
++
++/* define max debug item in each debug page
++ * #define bMaxItem_FPGA_PHY0        0x9
++ * #define bMaxItem_FPGA_PHY1        0x3
++ * #define bMaxItem_PHY_11B          0x16
++ * #define bMaxItem_OFDM_PHY0        0x29
++ * #define bMaxItem_OFDM_PHY1        0x0 */
++
++#define		bPMACControl              		0x0		/* Useless */
++#define		bWMACControl		0x1
++#define		bWNICControl		0x2
++
++#define		PathA                     			0x0	/* Useless */
++#define		PathB			0x1
++#define		PathC			0x2
++#define		PathD			0x3
++
++/*--------------------------Define Parameters-------------------------------*/
++
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188EPwrSeq.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188EPwrSeq.h
+new file mode 100644
+index 000000000..46c61abac
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188EPwrSeq.h
+@@ -0,0 +1,170 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++
++#ifndef __HAL8188EPWRSEQ_H__
++#define __HAL8188EPWRSEQ_H__
++
++#include "HalPwrSeqCmd.h"
++
++/*
++	Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
++	There are 6 HW Power States:
++	0: POFF--Power Off
++	1: PDN--Power Down
++	2: CARDEMU--Card Emulation
++	3: ACT--Active Mode
++	4: LPS--Low Power State
++	5: SUS--Suspend
++
++	The transision from different states are defined below
++	TRANS_CARDEMU_TO_ACT
++	TRANS_ACT_TO_CARDEMU
++	TRANS_CARDEMU_TO_SUS
++	TRANS_SUS_TO_CARDEMU
++	TRANS_CARDEMU_TO_PDN
++	TRANS_ACT_TO_LPS
++	TRANS_LPS_TO_ACT
++
++	TRANS_END
++
++    PWR SEQ Version: rtl8188E_PwrSeq_V09.h
++*/
++#define	RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS	10
++#define	RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS	10
++#define	RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS	10
++#define	RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS	10
++#define	RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS	10
++#define	RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS	10
++#define	RTL8188E_TRANS_ACT_TO_LPS_STEPS	15
++#define	RTL8188E_TRANS_LPS_TO_ACT_STEPS	15
++#define	RTL8188E_TRANS_END_STEPS	1
++
++
++#define RTL8188E_TRANS_CARDEMU_TO_ACT														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0}, /* 0x02[1:0] = 0	reset BB*/			\
++	{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[8] = 1 polling until return 0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, /*wait till 0x04[8] = 0*/	\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*LDO normal mode*/	\
++
++#define RTL8188E_TRANS_ACT_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
++
++#define RTL8188E_TRANS_CARDEMU_TO_SUS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/	\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT7}, /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */	\
++	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */	\
++	{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register  0xfe10[4]=1 */	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
++
++#define RTL8188E_TRANS_SUS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
++
++#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */	\
++	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */	\
++	{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register  0xfe10[4]=1 */	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
++
++#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
++
++#define RTL8188E_TRANS_CARDEMU_TO_PDN												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
++
++#define RTL8188E_TRANS_PDN_TO_CARDEMU												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
++
++	/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
++#define RTL8188E_TRANS_ACT_TO_LPS														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/	\
++	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/	\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
++	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
++
++
++#define RTL8188E_TRANS_LPS_TO_ACT															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
++	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
++	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
++	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
++	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
++
++#define RTL8188E_TRANS_END															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
++
++
++	extern WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188E_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188E_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS + RTL8188E_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
++
++#endif /* __HAL8188EPWRSEQ_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188FPhyCfg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188FPhyCfg.h
+new file mode 100644
+index 000000000..1bc60dc52
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188FPhyCfg.h
+@@ -0,0 +1,120 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8188FPHYCFG_H__
++#define __INC_HAL8188FPHYCFG_H__
++
++/*--------------------------Define Parameters-------------------------------*/
++#define LOOP_LIMIT				5
++#define MAX_STALL_TIME			50		/* us */
++#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
++#define MAX_TXPWR_IDX_NMODE_92S	63
++#define Reset_Cnt_Limit			3
++
++#ifdef CONFIG_PCI_HCI
++	#define MAX_AGGR_NUM	0x0B
++#else
++	#define MAX_AGGR_NUM	0x07
++#endif /* CONFIG_PCI_HCI */
++
++
++/*--------------------------Define Parameters End-------------------------------*/
++
++
++/*------------------------------Define structure----------------------------*/
++
++/*------------------------------Define structure End----------------------------*/
++
++/*--------------------------Exported Function prototype---------------------*/
++u32
++PHY_QueryBBReg_8188F(
++		PADAPTER	Adapter,
++		u32		RegAddr,
++		u32		BitMask
++);
++
++void
++PHY_SetBBReg_8188F(
++		PADAPTER	Adapter,
++		u32		RegAddr,
++		u32		BitMask,
++		u32		Data
++);
++
++u32
++PHY_QueryRFReg_8188F(
++		PADAPTER			Adapter,
++		enum rf_path			eRFPath,
++		u32				RegAddr,
++		u32				BitMask
++);
++
++void
++PHY_SetRFReg_8188F(
++		PADAPTER			Adapter,
++		enum rf_path			eRFPath,
++		u32				RegAddr,
++		u32				BitMask,
++		u32				Data
++);
++
++/* MAC/BB/RF HAL config */
++int PHY_BBConfig8188F(PADAPTER	Adapter);
++
++int PHY_RFConfig8188F(PADAPTER	Adapter);
++
++s32 PHY_MACConfig8188F(PADAPTER padapter);
++
++int
++PHY_ConfigRFWithParaFile_8188F(
++		PADAPTER			Adapter,
++		u8					*pFileName,
++	enum rf_path				eRFPath
++);
++
++void
++PHY_SetTxPowerIndex_8188F(
++		PADAPTER			Adapter,
++		u32					PowerIndex,
++		enum rf_path			RFPath,
++		u8					Rate
++);
++
++void
++PHY_SetTxPowerLevel8188F(
++		PADAPTER		Adapter,
++		u8			channel
++);
++
++void rtl8188f_set_txpwr_done(_adapter *adapter);
++
++void
++PHY_SetSwChnlBWMode8188F(
++		PADAPTER			Adapter,
++		u8					channel,
++		enum channel_width	Bandwidth,
++		u8					Offset40,
++		u8					Offset80
++);
++
++void phy_set_rf_path_switch_8188f(
++		struct		dm_struct *phydm,
++		bool		bMain
++);
++
++void BBTurnOnBlock_8188F(_adapter *adapter);
++
++/*--------------------------Exported Function prototype End---------------------*/
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188FPhyReg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188FPhyReg.h
+new file mode 100644
+index 000000000..a831faade
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188FPhyReg.h
+@@ -0,0 +1,1165 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8188FPHYREG_H__
++#define __INC_HAL8188FPHYREG_H__
++
++/*--------------------------Define Parameters-------------------------------*/
++
++/* ************************************************************
++ * Regsiter offset definition
++ * ************************************************************ */
++
++/*
++ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
++ * 3. RF register 0x00-2E
++ * 4. Bit Mask for BB/RF register
++ * 5. Other defintion for BB/RF R/W
++ *   */
++
++
++/*
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 1. Page1(0x100)
++ *   */
++#define		rPMAC_Reset					0x100
++#define		rPMAC_TxStart					0x104
++#define		rPMAC_TxLegacySIG				0x108
++#define		rPMAC_TxHTSIG1				0x10c
++#define		rPMAC_TxHTSIG2				0x110
++#define		rPMAC_PHYDebug				0x114
++#define		rPMAC_TxPacketNum				0x118
++#define		rPMAC_TxIdle					0x11c
++#define		rPMAC_TxMACHeader0			0x120
++#define		rPMAC_TxMACHeader1			0x124
++#define		rPMAC_TxMACHeader2			0x128
++#define		rPMAC_TxMACHeader3			0x12c
++#define		rPMAC_TxMACHeader4			0x130
++#define		rPMAC_TxMACHeader5			0x134
++#define		rPMAC_TxDataType				0x138
++#define		rPMAC_TxRandomSeed			0x13c
++#define		rPMAC_CCKPLCPPreamble			0x140
++#define		rPMAC_CCKPLCPHeader			0x144
++#define		rPMAC_CCKCRC16				0x148
++#define		rPMAC_OFDMRxCRC32OK			0x170
++#define		rPMAC_OFDMRxCRC32Er			0x174
++#define		rPMAC_OFDMRxParityEr			0x178
++#define		rPMAC_OFDMRxCRC8Er			0x17c
++#define		rPMAC_CCKCRxRC16Er			0x180
++#define		rPMAC_CCKCRxRC32Er			0x184
++#define		rPMAC_CCKCRxRC32OK			0x188
++#define		rPMAC_TxStatus					0x18c
++
++/*
++ * 2. Page2(0x200)
++ *
++ * The following two definition are only used for USB interface. */
++#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
++#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
++
++/*
++ * 3. Page8(0x800)
++ *   */
++#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
++
++#define		rFPGA0_TxInfo				0x804	/* Status report?? */
++#define		rFPGA0_PSDFunction			0x808
++
++#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
++
++#define		rFPGA0_RFTiming1			0x810	/* Useless now */
++#define		rFPGA0_RFTiming2			0x814
++
++#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
++#define		rFPGA0_XA_HSSIParameter2		0x824
++#define		rFPGA0_XB_HSSIParameter1		0x828
++#define		rFPGA0_XB_HSSIParameter2		0x82c
++#define		rTxAGC_B_Rate18_06				0x830
++#define		rTxAGC_B_Rate54_24				0x834
++#define		rTxAGC_B_CCK1_55_Mcs32		0x838
++#define		rTxAGC_B_Mcs03_Mcs00			0x83c
++
++#define		rTxAGC_B_Mcs07_Mcs04			0x848
++#define		rTxAGC_B_Mcs11_Mcs08			0x84c
++
++#define		rFPGA0_XA_LSSIParameter		0x840
++#define		rFPGA0_XB_LSSIParameter		0x844
++
++#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
++#define		rFPGA0_RFSleepUpParameter		0x854
++
++#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
++#define		rFPGA0_XCD_SwitchControl		0x85c
++
++#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
++#define		rFPGA0_XB_RFInterfaceOE		0x864
++
++#define		rTxAGC_B_Mcs15_Mcs12			0x868
++#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
++
++#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
++#define		rFPGA0_XCD_RFInterfaceSW		0x874
++
++#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
++#define		rFPGA0_XCD_RFParameter		0x87c
++
++#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
++#define		rFPGA0_AnalogParameter2		0x884
++#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
++#define		rFPGA0_AnalogParameter4		0x88c
++
++#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
++#define		rFPGA0_XB_LSSIReadBack		0x8a4
++#define		rFPGA0_XC_LSSIReadBack		0x8a8
++#define		rFPGA0_XD_LSSIReadBack		0x8ac
++
++#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
++#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
++#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
++#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
++#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
++
++/*
++ * 4. Page9(0x900)
++ *   */
++#define		rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
++
++#define		rFPGA1_TxBlock				0x904	/* Useless now */
++#define		rFPGA1_DebugSelect			0x908	/* Useless now */
++#define		rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
++#define	rS0S1_PathSwitch			0x948
++
++/*
++ * 5. PageA(0xA00)
++ *
++ * Set Control channel to upper or lower. These settings are required only for 40MHz */
++#define		rCCK0_System				0xa00
++
++#define		rCCK0_AFESetting			0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
++#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
++
++#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
++#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
++
++#define		rCCK0_RxHP					0xa14
++
++#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
++#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
++
++#define		rCCK0_TxFilter1				0xa20
++#define		rCCK0_TxFilter2				0xa24
++#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
++#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
++#define		rCCK0_TRSSIReport		0xa50
++#define		rCCK0_RxReport            		0xa54  /* 0xa57 */
++#define		rCCK0_FACounterLower      	0xa5c  /* 0xa5b */
++#define		rCCK0_FACounterUpper      	0xa58  /* 0xa5c
++ *
++ * PageB(0xB00)
++ *   */
++#define		rPdp_AntA				0xb00
++#define		rPdp_AntA_4				0xb04
++#define		rConfig_Pmpd_AntA			0xb28
++#define		rConfig_AntA				0xb68
++#define		rConfig_AntB				0xb6c
++#define		rPdp_AntB					0xb70
++#define		rPdp_AntB_4				0xb74
++#define		rConfig_Pmpd_AntB			0xb98
++#define		rAPK						0xbd8
++
++/*
++ * 6. PageC(0xC00)
++ *   */
++#define		rOFDM0_LSTF				0xc00
++
++#define		rOFDM0_TRxPathEnable		0xc04
++#define		rOFDM0_TRMuxPar			0xc08
++#define		rOFDM0_TRSWIsolation		0xc0c
++
++#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
++#define		rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
++#define		rOFDM0_XBRxAFE		0xc18
++#define		rOFDM0_XBRxIQImbalance	0xc1c
++#define		rOFDM0_XCRxAFE		0xc20
++#define		rOFDM0_XCRxIQImbalance	0xc24
++#define		rOFDM0_XDRxAFE		0xc28
++#define		rOFDM0_XDRxIQImbalance	0xc2c
++
++#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
++#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
++#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
++#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
++
++#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
++#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
++#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
++#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
++
++#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
++#define		rOFDM0_XAAGCCore2			0xc54
++#define		rOFDM0_XBAGCCore1			0xc58
++#define		rOFDM0_XBAGCCore2			0xc5c
++#define		rOFDM0_XCAGCCore1			0xc60
++#define		rOFDM0_XCAGCCore2			0xc64
++#define		rOFDM0_XDAGCCore1			0xc68
++#define		rOFDM0_XDAGCCore2			0xc6c
++
++#define		rOFDM0_AGCParameter1			0xc70
++#define		rOFDM0_AGCParameter2			0xc74
++#define		rOFDM0_AGCRSSITable			0xc78
++#define		rOFDM0_HTSTFAGC				0xc7c
++
++#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
++#define		rOFDM0_XATxAFE				0xc84
++#define		rOFDM0_XBTxIQImbalance		0xc88
++#define		rOFDM0_XBTxAFE				0xc8c
++#define		rOFDM0_XCTxIQImbalance		0xc90
++#define		rOFDM0_XCTxAFE			0xc94
++#define		rOFDM0_XDTxIQImbalance		0xc98
++#define		rOFDM0_XDTxAFE				0xc9c
++
++#define		rOFDM0_RxIQExtAnta			0xca0
++#define		rOFDM0_TxCoeff1				0xca4
++#define		rOFDM0_TxCoeff2				0xca8
++#define		rOFDM0_TxCoeff3				0xcac
++#define		rOFDM0_TxCoeff4				0xcb0
++#define		rOFDM0_TxCoeff5				0xcb4
++#define		rOFDM0_TxCoeff6				0xcb8
++#define		rOFDM0_RxHPParameter			0xce0
++#define		rOFDM0_TxPseudoNoiseWgt		0xce4
++#define		rOFDM0_FrameSync				0xcf0
++#define		rOFDM0_DFSReport				0xcf4
++
++/*
++ * 7. PageD(0xD00)
++ *   */
++#define		rOFDM1_LSTF					0xd00
++#define		rOFDM1_TRxPathEnable			0xd04
++
++#define		rOFDM1_CFO						0xd08	/* No setting now */
++#define		rOFDM1_CSI1					0xd10
++#define		rOFDM1_SBD						0xd14
++#define		rOFDM1_CSI2					0xd18
++#define		rOFDM1_CFOTracking			0xd2c
++#define		rOFDM1_TRxMesaure1			0xd34
++#define		rOFDM1_IntfDet					0xd3c
++#define		rOFDM1_PseudoNoiseStateAB		0xd50
++#define		rOFDM1_PseudoNoiseStateCD		0xd54
++#define		rOFDM1_RxPseudoNoiseWgt		0xd58
++
++#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
++#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
++#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
++
++#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
++#define		rOFDM_ShortCFOCD				0xdb0
++#define		rOFDM_LongCFOAB				0xdb4
++#define		rOFDM_LongCFOCD				0xdb8
++#define		rOFDM_TailCFOAB				0xdbc
++#define		rOFDM_TailCFOCD				0xdc0
++#define		rOFDM_PWMeasure1		0xdc4
++#define		rOFDM_PWMeasure2		0xdc8
++#define		rOFDM_BWReport				0xdcc
++#define		rOFDM_AGCReport				0xdd0
++#define		rOFDM_RxSNR					0xdd4
++#define		rOFDM_RxEVMCSI				0xdd8
++#define		rOFDM_SIGReport				0xddc
++
++
++/*
++ * 8. PageE(0xE00)
++ *   */
++#define		rTxAGC_A_Rate18_06			0xe00
++#define		rTxAGC_A_Rate54_24			0xe04
++#define		rTxAGC_A_CCK1_Mcs32			0xe08
++#define		rTxAGC_A_Mcs03_Mcs00			0xe10
++#define		rTxAGC_A_Mcs07_Mcs04			0xe14
++#define		rTxAGC_A_Mcs11_Mcs08			0xe18
++#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
++
++#define		rFPGA0_IQK					0xe28
++#define		rTx_IQK_Tone_A				0xe30
++#define		rRx_IQK_Tone_A				0xe34
++#define		rTx_IQK_PI_A					0xe38
++#define		rRx_IQK_PI_A					0xe3c
++
++#define		rTx_IQK						0xe40
++#define		rRx_IQK						0xe44
++#define		rIQK_AGC_Pts					0xe48
++#define		rIQK_AGC_Rsp					0xe4c
++#define		rTx_IQK_Tone_B				0xe50
++#define		rRx_IQK_Tone_B				0xe54
++#define		rTx_IQK_PI_B					0xe58
++#define		rRx_IQK_PI_B					0xe5c
++#define		rIQK_AGC_Cont				0xe60
++
++#define		rBlue_Tooth					0xe6c
++#define		rRx_Wait_CCA					0xe70
++#define		rTx_CCK_RFON					0xe74
++#define		rTx_CCK_BBON				0xe78
++#define		rTx_OFDM_RFON				0xe7c
++#define		rTx_OFDM_BBON				0xe80
++#define		rTx_To_Rx					0xe84
++#define		rTx_To_Tx					0xe88
++#define		rRx_CCK						0xe8c
++
++#define		rTx_Power_Before_IQK_A		0xe94
++#define		rTx_Power_After_IQK_A			0xe9c
++
++#define		rRx_Power_Before_IQK_A		0xea0
++#define		rRx_Power_Before_IQK_A_2		0xea4
++#define		rRx_Power_After_IQK_A			0xea8
++#define		rRx_Power_After_IQK_A_2		0xeac
++
++#define		rTx_Power_Before_IQK_B		0xeb4
++#define		rTx_Power_After_IQK_B			0xebc
++
++#define		rRx_Power_Before_IQK_B		0xec0
++#define		rRx_Power_Before_IQK_B_2		0xec4
++#define		rRx_Power_After_IQK_B			0xec8
++#define		rRx_Power_After_IQK_B_2		0xecc
++
++#define		rRx_OFDM					0xed0
++#define		rRx_Wait_RIFS				0xed4
++#define		rRx_TO_Rx					0xed8
++#define		rStandby						0xedc
++#define		rSleep						0xee0
++#define		rPMPD_ANAEN				0xeec
++
++/*
++ * 7. RF Register 0x00-0x2E (RF 8256)
++ * RF-0222D 0x00-3F
++ *
++ * Zebra1 */
++#define		rZebra1_HSSIEnable				0x0	/* Useless now */
++#define		rZebra1_TRxEnable1				0x1
++#define		rZebra1_TRxEnable2				0x2
++#define		rZebra1_AGC					0x4
++#define		rZebra1_ChargePump			0x5
++#define		rZebra1_Channel				0x7	/* RF channel switch */
++
++/* #endif */
++#define		rZebra1_TxGain					0x8	/* Useless now */
++#define		rZebra1_TxLPF					0x9
++#define		rZebra1_RxLPF					0xb
++#define		rZebra1_RxHPFCorner			0xc
++
++/* Zebra4 */
++#define		rGlobalCtrl						0	/* Useless now */
++#define		rRTL8256_TxLPF					19
++#define		rRTL8256_RxLPF					11
++
++/* RTL8258 */
++#define		rRTL8258_TxLPF					0x11	/* Useless now */
++#define		rRTL8258_RxLPF					0x13
++#define		rRTL8258_RSSILPF				0xa
++
++/*
++ * RL6052 Register definition
++ *   */
++#define		RF_AC						0x00	/*  */
++
++#define		RF_IQADJ_G1				0x01	/*  */
++#define		RF_IQADJ_G2				0x02	/*  */
++#define		RF_BS_PA_APSET_G1_G4		0x03
++#define		RF_BS_PA_APSET_G5_G8		0x04
++#define		RF_POW_TRSW				0x05	/*  */
++
++#define		RF_GAIN_RX					0x06	/*  */
++#define		RF_GAIN_TX					0x07	/*  */
++
++#define		RF_TXM_IDAC				0x08	/*  */
++#define		RF_IPA_G					0x09	/*  */
++#define		RF_TXBIAS_G				0x0A
++#define		RF_TXPA_AG					0x0B
++#define		RF_IPA_A					0x0C	/*  */
++#define		RF_TXBIAS_A				0x0D
++#define		RF_BS_PA_APSET_G9_G11	0x0E
++#define		RF_BS_IQGEN				0x0F	/*  */
++
++#define		RF_MODE1					0x10	/*  */
++#define		RF_MODE2					0x11	/*  */
++
++#define		RF_RX_AGC_HP				0x12	/*  */
++#define		RF_TX_AGC					0x13	/*  */
++#define		RF_BIAS						0x14	/*  */
++#define		RF_IPA						0x15	/*  */
++#define		RF_TXBIAS					0x16
++#define		RF_POW_ABILITY			0x17	/*  */
++#define		RF_MODE_AG				0x18	/*  */
++#define		rRfChannel					0x18	/* RF channel and BW switch */
++#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
++#define		RF_TOP						0x19	/*  */
++
++#define		RF_RX_G1					0x1A	/*  */
++#define		RF_RX_G2					0x1B	/*  */
++
++#define		RF_RX_BB2					0x1C	/*  */
++#define		RF_RX_BB1					0x1D	/*  */
++
++#define		RF_RCK1					0x1E	/*  */
++#define		RF_RCK2					0x1F	/*  */
++
++#define		RF_TX_G1					0x20	/*  */
++#define		RF_TX_G2					0x21	/*  */
++#define		RF_TX_G3					0x22	/*  */
++
++#define		RF_TX_BB1					0x23	/*  */
++
++#define		RF_T_METER					0x24	/*  */
++
++#define		RF_SYN_G1					0x25	/* RF TX Power control */
++#define		RF_SYN_G2					0x26	/* RF TX Power control */
++#define		RF_SYN_G3					0x27	/* RF TX Power control */
++#define		RF_SYN_G4					0x28	/* RF TX Power control */
++#define		RF_SYN_G5					0x29	/* RF TX Power control */
++#define		RF_SYN_G6					0x2A	/* RF TX Power control */
++#define		RF_SYN_G7					0x2B	/* RF TX Power control */
++#define		RF_SYN_G8					0x2C	/* RF TX Power control */
++
++#define		RF_RCK_OS					0x30	/* RF TX PA control */
++
++#define		RF_TXPA_G1					0x31	/* RF TX PA control */
++#define		RF_TXPA_G2					0x32	/* RF TX PA control */
++#define		RF_TXPA_G3					0x33	/* RF TX PA control */
++#define	RF_TX_BIAS_A				0x35
++#define	RF_TX_BIAS_D				0x36
++#define	RF_LOBF_9					0x38
++#define 	RF_RXRF_A3					0x3C	/*	 */
++#define	RF_TRSW					0x3F
++
++#define	RF_TXRF_A2					0x41
++#define	RF_TXPA_G4					0x46
++#define	RF_TXPA_A4					0x4B
++#define	RF_0x52					0x52
++#define		RF_RXG_MIX_SWBW				0x87
++#define		RF_DBG_LP_RX2				0xDF
++#define	RF_WE_LUT					0xEF
++#define	RF_S0S1					0xB0
++
++#define RF_TX_GAIN_OFFSET_8188F(_val) (abs((_val)) | (((_val) > 0) ? BIT5 : 0))
++
++/*
++ * Bit Mask
++ *
++ * 1. Page1(0x100) */
++#define		bBBResetB						0x100	/* Useless now? */
++#define		bGlobalResetB					0x200
++#define		bOFDMTxStart					0x4
++#define		bCCKTxStart						0x8
++#define		bCRC32Debug					0x100
++#define		bPMACLoopback					0x10
++#define		bTxLSIG							0xffffff
++#define		bOFDMTxRate					0xf
++#define		bOFDMTxReserved				0x10
++#define		bOFDMTxLength					0x1ffe0
++#define		bOFDMTxParity					0x20000
++#define		bTxHTSIG1						0xffffff
++#define		bTxHTMCSRate					0x7f
++#define		bTxHTBW						0x80
++#define		bTxHTLength					0xffff00
++#define		bTxHTSIG2						0xffffff
++#define		bTxHTSmoothing					0x1
++#define		bTxHTSounding					0x2
++#define		bTxHTReserved					0x4
++#define		bTxHTAggreation				0x8
++#define		bTxHTSTBC						0x30
++#define		bTxHTAdvanceCoding			0x40
++#define		bTxHTShortGI					0x80
++#define		bTxHTNumberHT_LTF			0x300
++#define		bTxHTCRC8						0x3fc00
++#define		bCounterReset					0x10000
++#define		bNumOfOFDMTx					0xffff
++#define		bNumOfCCKTx					0xffff0000
++#define		bTxIdleInterval					0xffff
++#define		bOFDMService					0xffff0000
++#define		bTxMACHeader					0xffffffff
++#define		bTxDataInit						0xff
++#define		bTxHTMode						0x100
++#define		bTxDataType					0x30000
++#define		bTxRandomSeed					0xffffffff
++#define		bCCKTxPreamble					0x1
++#define		bCCKTxSFD						0xffff0000
++#define		bCCKTxSIG						0xff
++#define		bCCKTxService					0xff00
++#define		bCCKLengthExt					0x8000
++#define		bCCKTxLength					0xffff0000
++#define		bCCKTxCRC16					0xffff
++#define		bCCKTxStatus					0x1
++#define		bOFDMTxStatus					0x2
++
++#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
++
++/* 2. Page8(0x800) */
++#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
++#define		bJapanMode						0x2
++#define		bCCKTxSC						0x30
++#define		bCCKEn							0x1000000
++#define		bOFDMEn						0x2000000
++
++#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
++#define		bOFDMTxDACPhase		0x40000
++#define		bXATxAGC			0x3f
++
++#define		bAntennaSelect		0x0300
++
++#define		bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
++#define		bXCTxAGC			0xf000
++#define		bXDTxAGC			0xf0000
++
++#define		bPAStart                  			0xf0000000	/* Useless now */
++#define		bTRStart			0x00f00000
++#define		bRFStart			0x0000f000
++#define		bBBStart			0x000000f0
++#define		bBBCCKStart		0x0000000f
++#define		bPAEnd                    			0xf          /* Reg0x814 */
++#define		bTREnd			0x0f000000
++#define		bRFEnd			0x000f0000
++#define		bCCAMask                  			0x000000f0   /* T2R */
++#define		bR2RCCAMask		0x00000f00
++#define		bHSSI_R2TDelay		0xf8000000
++#define		bHSSI_T2RDelay		0xf80000
++#define		bContTxHSSI               		0x400     /* chane gain at continue Tx */
++#define		bIGFromCCK		0x200
++#define		bAGCAddress		0x3f
++#define		bRxHPTx			0x7000
++#define		bRxHPT2R			0x38000
++#define		bRxHPCCKIni		0xc0000
++#define		bAGCTxCode		0xc00000
++#define		bAGCRxCode		0x300000
++
++#define		b3WireDataLength          		0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
++#define		b3WireAddressLength		0x400
++
++#define		b3WireRFPowerDown         		0x1	/* Useless now
++ * #define bHWSISelect		0x8 */
++#define		b5GPAPEPolarity		0x40000000
++#define		b2GPAPEPolarity		0x80000000
++#define		bRFSW_TxDefaultAnt		0x3
++#define		bRFSW_TxOptionAnt		0x30
++#define		bRFSW_RxDefaultAnt		0x300
++#define		bRFSW_RxOptionAnt		0x3000
++#define		bRFSI_3WireData		0x1
++#define		bRFSI_3WireClock		0x2
++#define		bRFSI_3WireLoad		0x4
++#define		bRFSI_3WireRW		0x8
++#define		bRFSI_3Wire			0xf
++
++#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
++
++#define		bRFSI_TRSW                		0x20	/* Useless now */
++#define		bRFSI_TRSWB		0x40
++#define		bRFSI_ANTSW		0x100
++#define		bRFSI_ANTSWB		0x200
++#define		bRFSI_PAPE			0x400
++#define		bRFSI_PAPE5G		0x800
++#define		bBandSelect			0x1
++#define		bHTSIG2_GI			0x80
++#define		bHTSIG2_Smoothing		0x01
++#define		bHTSIG2_Sounding		0x02
++#define		bHTSIG2_Aggreaton		0x08
++#define		bHTSIG2_STBC		0x30
++#define		bHTSIG2_AdvCoding		0x40
++#define		bHTSIG2_NumOfHTLTF	0x300
++#define		bHTSIG2_CRC8		0x3fc
++#define		bHTSIG1_MCS		0x7f
++#define		bHTSIG1_BandWidth		0x80
++#define		bHTSIG1_HTLength		0xffff
++#define		bLSIG_Rate			0xf
++#define		bLSIG_Reserved		0x10
++#define		bLSIG_Length		0x1fffe
++#define		bLSIG_Parity			0x20
++#define		bCCKRxPhase		0x4
++
++#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
++
++#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
++
++#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
++
++#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
++#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
++#define		bRegulator0Standby		0x1
++#define		bRegulatorPLLStandby		0x2
++#define		bRegulator1Standby		0x4
++#define		bPLLPowerUp		0x8
++#define		bDPLLPowerUp		0x10
++#define		bDA10PowerUp		0x20
++#define		bAD7PowerUp		0x200
++#define		bDA6PowerUp		0x2000
++#define		bXtalPowerUp		0x4000
++#define		b40MDClkPowerUP		0x8000
++#define		bDA6DebugMode		0x20000
++#define		bDA6Swing			0x380000
++
++#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
++
++#define		b80MClkDelay              		0x18000000	/* Useless */
++#define		bAFEWatchDogEnable		0x20000000
++
++#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
++#define		bXtalCap23			0x3
++#define		bXtalCap92x					0x0f000000
++#define		bXtalCap			0x0f000000
++
++#define		bIntDifClkEnable          		0x400	/* Useless */
++#define		bExtSigClkEnable		0x800
++#define		bBandgapMbiasPowerUp	0x10000
++#define		bAD11SHGain		0xc0000
++#define		bAD11InputRange		0x700000
++#define		bAD11OPCurrent		0x3800000
++#define		bIPathLoopback		0x4000000
++#define		bQPathLoopback		0x8000000
++#define		bAFELoopback		0x10000000
++#define		bDA10Swing		0x7e0
++#define		bDA10Reverse		0x800
++#define		bDAClkSource		0x1000
++#define		bAD7InputRange		0x6000
++#define		bAD7Gain			0x38000
++#define		bAD7OutputCMMode		0x40000
++#define		bAD7InputCMMode		0x380000
++#define		bAD7Current			0xc00000
++#define		bRegulatorAdjust		0x7000000
++#define		bAD11PowerUpAtTx		0x1
++#define		bDA10PSAtTx		0x10
++#define		bAD11PowerUpAtRx		0x100
++#define		bDA10PSAtRx		0x1000
++#define		bCCKRxAGCFormat		0x200
++#define		bPSDFFTSamplepPoint		0xc000
++#define		bPSDAverageNum		0x3000
++#define		bIQPathControl		0xc00
++#define		bPSDFreq			0x3ff
++#define		bPSDAntennaPath		0x30
++#define		bPSDIQSwitch		0x40
++#define		bPSDRxTrigger		0x400000
++#define		bPSDTxTrigger		0x80000000
++#define		bPSDSineToneScale		0x7f000000
++#define		bPSDReport			0xffff
++
++/* 3. Page9(0x900) */
++#define		bOFDMTxSC                 		0x30000000	/* Useless */
++#define		bCCKTxOn			0x1
++#define		bOFDMTxOn		0x2
++#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
++#define		bDebugItem                		0xff   /* reset debug page and LWord */
++#define		bAntL			0x10
++#define		bAntNonHT				0x100
++#define		bAntHT1			0x1000
++#define		bAntHT2			0x10000
++#define		bAntHT1S1			0x100000
++#define		bAntNonHTS1		0x1000000
++
++/* 4. PageA(0xA00) */
++#define		bCCKBBMode				0x3	/* Useless */
++#define		bCCKTxPowerSaving		0x80
++#define		bCCKRxPowerSaving		0x40
++
++#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
++
++#define		bCCKScramble			0x8	/* Useless */
++#define		bCCKAntDiversity		0x8000
++#define		bCCKCarrierRecovery		0x4000
++#define		bCCKTxRate				0x3000
++#define		bCCKDCCancel			0x0800
++#define		bCCKISICancel			0x0400
++#define		bCCKMatchFilter			0x0200
++#define		bCCKEqualizer			0x0100
++#define		bCCKPreambleDetect		0x800000
++#define		bCCKFastFalseCCA		0x400000
++#define		bCCKChEstStart			0x300000
++#define		bCCKCCACount			0x080000
++#define		bCCKcs_lim				0x070000
++#define		bCCKBistMode			0x80000000
++#define		bCCKCCAMask			0x40000000
++#define		bCCKTxDACPhase		0x4
++#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
++#define		bCCKr_cp_mode0		0x0100
++#define		bCCKTxDCOffset			0xf0
++#define		bCCKRxDCOffset			0xf
++#define		bCCKCCAMode			0xc000
++#define		bCCKFalseCS_lim			0x3f00
++#define		bCCKCS_ratio			0xc00000
++#define		bCCKCorgBit_sel			0x300000
++#define		bCCKPD_lim				0x0f0000
++#define		bCCKNewCCA			0x80000000
++#define		bCCKRxHPofIG			0x8000
++#define		bCCKRxIG				0x7f00
++#define		bCCKLNAPolarity			0x800000
++#define		bCCKRx1stGain			0x7f0000
++#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
++#define		bCCKRxAGCSatLevel		0x1f000000
++#define		bCCKRxAGCSatCount		0xe0
++#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
++#define		bCCKFixedRxAGC			0x8000
++/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
++#define		bCCKAntennaPolarity		0x2000
++#define		bCCKTxFilterType		0x0c00
++#define		bCCKRxAGCReportType	0x0300
++#define		bCCKRxDAGCEn			0x80000000
++#define		bCCKRxDAGCPeriod		0x20000000
++#define		bCCKRxDAGCSatLevel		0x1f000000
++#define		bCCKTimingRecovery		0x800000
++#define		bCCKTxC0				0x3f0000
++#define		bCCKTxC1				0x3f000000
++#define		bCCKTxC2				0x3f
++#define		bCCKTxC3				0x3f00
++#define		bCCKTxC4				0x3f0000
++#define		bCCKTxC5				0x3f000000
++#define		bCCKTxC6				0x3f
++#define		bCCKTxC7				0x3f00
++#define		bCCKDebugPort			0xff0000
++#define		bCCKDACDebug			0x0f000000
++#define		bCCKFalseAlarmEnable	0x8000
++#define		bCCKFalseAlarmRead		0x4000
++#define		bCCKTRSSI				0x7f
++#define		bCCKRxAGCReport		0xfe
++#define		bCCKRxReport_AntSel	0x80000000
++#define		bCCKRxReport_MFOff		0x40000000
++#define		bCCKRxRxReport_SQLoss	0x20000000
++#define		bCCKRxReport_Pktloss	0x10000000
++#define		bCCKRxReport_Lockedbit	0x08000000
++#define		bCCKRxReport_RateError	0x04000000
++#define		bCCKRxReport_RxRate	0x03000000
++#define		bCCKRxFACounterLower	0xff
++#define		bCCKRxFACounterUpper	0xff000000
++#define		bCCKRxHPAGCStart		0xe000
++#define		bCCKRxHPAGCFinal		0x1c00
++#define		bCCKRxFalseAlarmEnable	0x8000
++#define		bCCKFACounterFreeze	0x4000
++#define		bCCKTxPathSel			0x10000000
++#define		bCCKDefaultRxPath		0xc000000
++#define		bCCKOptionRxPath		0x3000000
++
++/* 5. PageC(0xC00) */
++#define		bNumOfSTF				0x3	/* Useless */
++#define		bShift_L					0xc0
++#define		bGI_TH					0xc
++#define		bRxPathA				0x1
++#define		bRxPathB				0x2
++#define		bRxPathC				0x4
++#define		bRxPathD				0x8
++#define		bTxPathA				0x1
++#define		bTxPathB				0x2
++#define		bTxPathC				0x4
++#define		bTxPathD				0x8
++#define		bTRSSIFreq				0x200
++#define		bADCBackoff				0x3000
++#define		bDFIRBackoff			0xc000
++#define		bTRSSILatchPhase		0x10000
++#define		bRxIDCOffset			0xff
++#define		bRxQDCOffset			0xff00
++#define		bRxDFIRMode			0x1800000
++#define		bRxDCNFType			0xe000000
++#define		bRXIQImb_A				0x3ff
++#define		bRXIQImb_B				0xfc00
++#define		bRXIQImb_C				0x3f0000
++#define		bRXIQImb_D				0xffc00000
++#define		bDC_dc_Notch			0x60000
++#define		bRxNBINotch			0x1f000000
++#define		bPD_TH					0xf
++#define		bPD_TH_Opt2			0xc000
++#define		bPWED_TH				0x700
++#define		bIfMF_Win_L			0x800
++#define		bPD_Option				0x1000
++#define		bMF_Win_L				0xe000
++#define		bBW_Search_L			0x30000
++#define		bwin_enh_L				0xc0000
++#define		bBW_TH					0x700000
++#define		bED_TH2				0x3800000
++#define		bBW_option				0x4000000
++#define		bRatio_TH				0x18000000
++#define		bWindow_L				0xe0000000
++#define		bSBD_Option				0x1
++#define		bFrame_TH				0x1c
++#define		bFS_Option				0x60
++#define		bDC_Slope_check		0x80
++#define		bFGuard_Counter_DC_L	0xe00
++#define		bFrame_Weight_Short	0x7000
++#define		bSub_Tune				0xe00000
++#define		bFrame_DC_Length		0xe000000
++#define		bSBD_start_offset		0x30000000
++#define		bFrame_TH_2			0x7
++#define		bFrame_GI2_TH			0x38
++#define		bGI2_Sync_en			0x40
++#define		bSarch_Short_Early		0x300
++#define		bSarch_Short_Late		0xc00
++#define		bSarch_GI2_Late		0x70000
++#define		bCFOAntSum				0x1
++#define		bCFOAcc				0x2
++#define		bCFOStartOffset			0xc
++#define		bCFOLookBack			0x70
++#define		bCFOSumWeight			0x80
++#define		bDAGCEnable			0x10000
++#define		bTXIQImb_A				0x3ff
++#define		bTXIQImb_B				0xfc00
++#define		bTXIQImb_C				0x3f0000
++#define		bTXIQImb_D				0xffc00000
++#define		bTxIDCOffset			0xff
++#define		bTxQDCOffset			0xff00
++#define		bTxDFIRMode			0x10000
++#define		bTxPesudoNoiseOn		0x4000000
++#define		bTxPesudoNoise_A		0xff
++#define		bTxPesudoNoise_B		0xff00
++#define		bTxPesudoNoise_C		0xff0000
++#define		bTxPesudoNoise_D		0xff000000
++#define		bCCADropOption			0x20000
++#define		bCCADropThres			0xfff00000
++#define		bEDCCA_H				0xf
++#define		bEDCCA_L				0xf0
++#define		bLambda_ED			0x300
++#define		bRxInitialGain			0x7f
++#define		bRxAntDivEn				0x80
++#define		bRxAGCAddressForLNA	0x7f00
++#define		bRxHighPowerFlow		0x8000
++#define		bRxAGCFreezeThres		0xc0000
++#define		bRxFreezeStep_AGC1	0x300000
++#define		bRxFreezeStep_AGC2	0xc00000
++#define		bRxFreezeStep_AGC3	0x3000000
++#define		bRxFreezeStep_AGC0	0xc000000
++#define		bRxRssi_Cmp_En			0x10000000
++#define		bRxQuickAGCEn			0x20000000
++#define		bRxAGCFreezeThresMode	0x40000000
++#define		bRxOverFlowCheckType	0x80000000
++#define		bRxAGCShift				0x7f
++#define		bTRSW_Tri_Only			0x80
++#define		bPowerThres			0x300
++#define		bRxAGCEn				0x1
++#define		bRxAGCTogetherEn		0x2
++#define		bRxAGCMin				0x4
++#define		bRxHP_Ini				0x7
++#define		bRxHP_TRLNA			0x70
++#define		bRxHP_RSSI				0x700
++#define		bRxHP_BBP1				0x7000
++#define		bRxHP_BBP2				0x70000
++#define		bRxHP_BBP3				0x700000
++#define		bRSSI_H					0x7f0000     /* the threshold for high power */
++#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
++#define		bRxSettle_TRSW			0x7
++#define		bRxSettle_LNA			0x38
++#define		bRxSettle_RSSI			0x1c0
++#define		bRxSettle_BBP			0xe00
++#define		bRxSettle_RxHP			0x7000
++#define		bRxSettle_AntSW_RSSI	0x38000
++#define		bRxSettle_AntSW		0xc0000
++#define		bRxProcessTime_DAGC	0x300000
++#define		bRxSettle_HSSI			0x400000
++#define		bRxProcessTime_BBPPW	0x800000
++#define		bRxAntennaPowerShift	0x3000000
++#define		bRSSITableSelect		0xc000000
++#define		bRxHP_Final				0x7000000
++#define		bRxHTSettle_BBP			0x7
++#define		bRxHTSettle_HSSI		0x8
++#define		bRxHTSettle_RxHP		0x70
++#define		bRxHTSettle_BBPPW		0x80
++#define		bRxHTSettle_Idle		0x300
++#define		bRxHTSettle_Reserved	0x1c00
++#define		bRxHTRxHPEn			0x8000
++#define		bRxHTAGCFreezeThres	0x30000
++#define		bRxHTAGCTogetherEn	0x40000
++#define		bRxHTAGCMin			0x80000
++#define		bRxHTAGCEn				0x100000
++#define		bRxHTDAGCEn			0x200000
++#define		bRxHTRxHP_BBP			0x1c00000
++#define		bRxHTRxHP_Final		0xe0000000
++#define		bRxPWRatioTH			0x3
++#define		bRxPWRatioEn			0x4
++#define		bRxMFHold				0x3800
++#define		bRxPD_Delay_TH1		0x38
++#define		bRxPD_Delay_TH2		0x1c0
++#define		bRxPD_DC_COUNT_MAX	0x600
++/* #define bRxMF_Hold               0x3800 */
++#define		bRxPD_Delay_TH			0x8000
++#define		bRxProcess_Delay		0xf0000
++#define		bRxSearchrange_GI2_Early	0x700000
++#define		bRxFrame_Guard_Counter_L	0x3800000
++#define		bRxSGI_Guard_L			0xc000000
++#define		bRxSGI_Search_L		0x30000000
++#define		bRxSGI_TH				0xc0000000
++#define		bDFSCnt0				0xff
++#define		bDFSCnt1				0xff00
++#define		bDFSFlag				0xf0000
++#define		bMFWeightSum			0x300000
++#define		bMinIdxTH				0x7f000000
++#define		bDAFormat				0x40000
++#define		bTxChEmuEnable		0x01000000
++#define		bTRSWIsolation_A		0x7f
++#define		bTRSWIsolation_B		0x7f00
++#define		bTRSWIsolation_C		0x7f0000
++#define		bTRSWIsolation_D		0x7f000000
++#define		bExtLNAGain				0x7c00
++
++/* 6. PageE(0xE00) */
++#define		bSTBCEn				0x4	/* Useless */
++#define		bAntennaMapping		0x10
++#define		bNss					0x20
++#define		bCFOAntSumD			0x200
++#define		bPHYCounterReset		0x8000000
++#define		bCFOReportGet			0x4000000
++#define		bOFDMContinueTx		0x10000000
++#define		bOFDMSingleCarrier		0x20000000
++#define		bOFDMSingleTone		0x40000000
++/* #define bRxPath1                 0x01 */
++/* #define bRxPath2                 0x02 */
++/* #define bRxPath3                 0x04 */
++/* #define bRxPath4                 0x08 */
++/* #define bTxPath1                 0x10 */
++/* #define bTxPath2                 0x20 */
++#define		bHTDetect			0x100
++#define		bCFOEn				0x10000
++#define		bCFOValue			0xfff00000
++#define		bSigTone_Re		0x3f
++#define		bSigTone_Im		0x7f00
++#define		bCounter_CCA		0xffff
++#define		bCounter_ParityFail	0xffff0000
++#define		bCounter_RateIllegal		0xffff
++#define		bCounter_CRC8Fail	0xffff0000
++#define		bCounter_MCSNoSupport	0xffff
++#define		bCounter_FastSync	0xffff
++#define		bShortCFO			0xfff
++#define		bShortCFOTLength	12   /* total */
++#define		bShortCFOFLength	11   /* fraction */
++#define		bLongCFO			0x7ff
++#define		bLongCFOTLength	11
++#define		bLongCFOFLength	11
++#define		bTailCFO			0x1fff
++#define		bTailCFOTLength		13
++#define		bTailCFOFLength		12
++#define		bmax_en_pwdB		0xffff
++#define		bCC_power_dB		0xffff0000
++#define		bnoise_pwdB		0xffff
++#define		bPowerMeasTLength	10
++#define		bPowerMeasFLength	3
++#define		bRx_HT_BW			0x1
++#define		bRxSC				0x6
++#define		bRx_HT				0x8
++#define		bNB_intf_det_on		0x1
++#define		bIntf_win_len_cfg	0x30
++#define		bNB_Intf_TH_cfg		0x1c0
++#define		bRFGain				0x3f
++#define		bTableSel			0x40
++#define		bTRSW				0x80
++#define		bRxSNR_A			0xff
++#define		bRxSNR_B			0xff00
++#define		bRxSNR_C			0xff0000
++#define		bRxSNR_D			0xff000000
++#define		bSNREVMTLength		8
++#define		bSNREVMFLength		1
++#define		bCSI1st				0xff
++#define		bCSI2nd				0xff00
++#define		bRxEVM1st			0xff0000
++#define		bRxEVM2nd			0xff000000
++#define		bSIGEVM			0xff
++#define		bPWDB				0xff00
++#define		bSGIEN				0x10000
++
++#define		bSFactorQAM1		0xf	/* Useless */
++#define		bSFactorQAM2		0xf0
++#define		bSFactorQAM3		0xf00
++#define		bSFactorQAM4		0xf000
++#define		bSFactorQAM5		0xf0000
++#define		bSFactorQAM6		0xf0000
++#define		bSFactorQAM7		0xf00000
++#define		bSFactorQAM8		0xf000000
++#define		bSFactorQAM9		0xf0000000
++#define		bCSIScheme			0x100000
++
++#define		bNoiseLvlTopSet		0x3	/* Useless */
++#define		bChSmooth			0x4
++#define		bChSmoothCfg1		0x38
++#define		bChSmoothCfg2		0x1c0
++#define		bChSmoothCfg3		0xe00
++#define		bChSmoothCfg4		0x7000
++#define		bMRCMode			0x800000
++#define		bTHEVMCfg			0x7000000
++
++#define		bLoopFitType		0x1	/* Useless */
++#define		bUpdCFO			0x40
++#define		bUpdCFOOffData		0x80
++#define		bAdvUpdCFO			0x100
++#define		bAdvTimeCtrl		0x800
++#define		bUpdClko			0x1000
++#define		bFC					0x6000
++#define		bTrackingMode		0x8000
++#define		bPhCmpEnable		0x10000
++#define		bUpdClkoLTF		0x20000
++#define		bComChCFO			0x40000
++#define		bCSIEstiMode		0x80000
++#define		bAdvUpdEqz			0x100000
++#define		bUChCfg				0x7000000
++#define		bUpdEqz			0x8000000
++
++/* Rx Pseduo noise */
++#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
++#define		bRxPesudoNoise_A		0xff
++#define		bRxPesudoNoise_B		0xff00
++#define		bRxPesudoNoise_C		0xff0000
++#define		bRxPesudoNoise_D		0xff000000
++#define		bPesudoNoiseState_A	0xffff
++#define		bPesudoNoiseState_B	0xffff0000
++#define		bPesudoNoiseState_C	0xffff
++#define		bPesudoNoiseState_D	0xffff0000
++
++/* 7. RF Register
++ * Zebra1 */
++#define		bZebra1_HSSIEnable		0x8		/* Useless */
++#define		bZebra1_TRxControl		0xc00
++#define		bZebra1_TRxGainSetting	0x07f
++#define		bZebra1_RxCorner		0xc00
++#define		bZebra1_TxChargePump	0x38
++#define		bZebra1_RxChargePump	0x7
++#define		bZebra1_ChannelNum	0xf80
++#define		bZebra1_TxLPFBW		0x400
++#define		bZebra1_RxLPFBW		0x600
++
++/* Zebra4 */
++#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
++#define		bRTL8256RegModeCtrl0	0x40
++#define		bRTL8256_TxLPFBW		0x18
++#define		bRTL8256_RxLPFBW		0x600
++
++/* RTL8258 */
++#define		bRTL8258_TxLPFBW		0xc	/* Useless */
++#define		bRTL8258_RxLPFBW		0xc00
++#define		bRTL8258_RSSILPFBW	0xc0
++
++
++/*
++ * Other Definition
++ *   */
++
++/* byte endable for sb_write */
++#define		bByte0				0x1	/* Useless */
++#define		bByte1				0x2
++#define		bByte2				0x4
++#define		bByte3				0x8
++#define		bWord0				0x3
++#define		bWord1				0xc
++#define		bDWord				0xf
++
++/* for PutRegsetting & GetRegSetting BitMask */
++#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
++#define		bMaskByte1			0xff00
++#define		bMaskByte2			0xff0000
++#define		bMaskByte3			0xff000000
++#define		bMaskHWord		0xffff0000
++#define		bMaskLWord			0x0000ffff
++#define		bMaskDWord		0xffffffff
++#define		bMaskH3Bytes		0xffffff00
++#define		bMask12Bits			0xfff
++#define		bMaskH4Bits			0xf0000000
++#define		bMaskOFDM_D		0xffc00000
++#define		bMaskCCK			0x3f3f3f3f
++
++
++#define		bEnable			0x1	/* Useless */
++#define		bDisable		0x0
++
++#define		LeftAntenna		0x0	/* Useless */
++#define		RightAntenna	0x1
++
++#define		tCheckTxStatus		500   /* 500ms */ /* Useless */
++#define		tUpdateRxCounter	100   /* 100ms */
++
++#define		rateCCK		0	/* Useless */
++#define		rateOFDM	1
++#define		rateHT		2
++
++/* define Register-End */
++#define		bPMAC_End			0x1ff	/* Useless */
++#define		bFPGAPHY0_End		0x8ff
++#define		bFPGAPHY1_End		0x9ff
++#define		bCCKPHY0_End		0xaff
++#define		bOFDMPHY0_End		0xcff
++#define		bOFDMPHY1_End		0xdff
++
++/* define max debug item in each debug page
++ * #define bMaxItem_FPGA_PHY0        0x9
++ * #define bMaxItem_FPGA_PHY1        0x3
++ * #define bMaxItem_PHY_11B          0x16
++ * #define bMaxItem_OFDM_PHY0        0x29
++ * #define bMaxItem_OFDM_PHY1        0x0 */
++
++#define		bPMACControl		0x0		/* Useless */
++#define		bWMACControl		0x1
++#define		bWNICControl		0x2
++
++#define		PathA			0x0	/* Useless */
++#define		PathB			0x1
++#define		PathC			0x2
++#define		PathD			0x3
++
++/*--------------------------Define Parameters-------------------------------*/
++
++
++/* BB Register Definition
++ *
++ * 4. Page9(0x900)
++ *   */
++#define rDPDT_control				0x92c
++#define rfe_ctrl_anta_src				0x930
++#define rS0S1_PathSwitch			0x948
++#define	BBrx_DFIR						0x954
++#define AGC_table_select				0xb2c
++
++/*
++ * PageB(0xB00)
++ *   */
++#define rPdp_AntA						0xb00
++#define rPdp_AntA_4						0xb04
++#define rPdp_AntA_8						0xb08
++#define rPdp_AntA_C						0xb0c
++#define rPdp_AntA_10					0xb10
++#define rPdp_AntA_14					0xb14
++#define rPdp_AntA_18					0xb18
++#define rPdp_AntA_1C					0xb1c
++#define rPdp_AntA_20					0xb20
++#define rPdp_AntA_24					0xb24
++
++#define rConfig_Pmpd_AntA				0xb28
++#define rConfig_ram64x16				0xb2c
++
++#define rBndA							0xb30
++#define rHssiPar						0xb34
++
++#define rConfig_AntA					0xb68
++#define rConfig_AntB					0xb6c
++
++#define rPdp_AntB						0xb70
++#define rPdp_AntB_4						0xb74
++#define rPdp_AntB_8						0xb78
++#define rPdp_AntB_C						0xb7c
++#define rPdp_AntB_10					0xb80
++#define rPdp_AntB_14					0xb84
++#define rPdp_AntB_18					0xb88
++#define rPdp_AntB_1C					0xb8c
++#define rPdp_AntB_20					0xb90
++#define rPdp_AntB_24					0xb94
++
++#define rConfig_Pmpd_AntB				0xb98
++
++#define rBndB							0xba0
++
++#define rAPK							0xbd8
++#define rPm_Rx0_AntA					0xbdc
++#define rPm_Rx1_AntA					0xbe0
++#define rPm_Rx2_AntA					0xbe4
++#define rPm_Rx3_AntA					0xbe8
++#define rPm_Rx0_AntB					0xbec
++#define rPm_Rx1_AntB					0xbf0
++#define rPm_Rx2_AntB					0xbf4
++#define rPm_Rx3_AntB					0xbf8
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188FPwrSeq.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188FPwrSeq.h
+new file mode 100644
+index 000000000..5cad428fd
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8188FPwrSeq.h
+@@ -0,0 +1,212 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef REALTEK_POWER_SEQUENCE_8188F
++#define REALTEK_POWER_SEQUENCE_8188F
++
++#include "HalPwrSeqCmd.h"
++
++/*
++	Check document WM-20130815-JackieLau-RTL8188F_Power_Architecture v08.vsd
++	There are 6 HW Power States:
++	0: POFF--Power Off
++	1: PDN--Power Down
++	2: CARDEMU--Card Emulation
++	3: ACT--Active Mode
++	4: LPS--Low Power State
++	5: SUS--Suspend
++
++	The transision from different states are defined below
++	TRANS_CARDEMU_TO_ACT
++	TRANS_ACT_TO_CARDEMU
++	TRANS_CARDEMU_TO_SUS
++	TRANS_SUS_TO_CARDEMU
++	TRANS_CARDEMU_TO_PDN
++	TRANS_ACT_TO_LPS
++	TRANS_LPS_TO_ACT
++
++	TRANS_END
++*/
++#define	RTL8188F_TRANS_CARDEMU_TO_ACT_STEPS	13
++#define	RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS	15
++#define	RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS	14
++#define	RTL8188F_TRANS_SUS_TO_CARDEMU_STEPS	15
++#define	RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS	15
++#define	RTL8188F_TRANS_PDN_TO_CARDEMU_STEPS	15
++#define	RTL8188F_TRANS_ACT_TO_LPS_STEPS		11
++#define	RTL8188F_TRANS_LPS_TO_ACT_STEPS		13
++#define	RTL8188F_TRANS_ACT_TO_SWLPS_STEPS		21
++#define	RTL8188F_TRANS_SWLPS_TO_ACT_STEPS		14
++#define	RTL8188F_TRANS_END_STEPS		1
++
++
++#define RTL8188F_TRANS_CARDEMU_TO_ACT														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT3), 0},/*  0x4[11]=1'b0 disable WL suspend*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* 0x4[8]=1 polling until return 0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	 \
++	{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x35}, /*0x27<=35 to reduce RF noise*/
++
++#define RTL8188F_TRANS_ACT_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
++	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
++	{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x34}, /*0x27 <= 34, xtal_qsel = 0 to xtal bring up*/\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
++
++#define RTL8188F_TRANS_CARDEMU_TO_SUS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /*0x07 = 0x00 , SOP option to disable BG/MB*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ \
++	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
++
++#define RTL8188F_TRANS_SUS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/	\
++	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
++
++#define RTL8188F_TRANS_CARDEMU_TO_CARDDIS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /*0x07 = 0x00 , SOP option to disable BG/MB*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ \
++	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
++
++#define RTL8188F_TRANS_CARDDIS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/	\
++	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
++
++
++#define RTL8188F_TRANS_CARDEMU_TO_PDN												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
++
++#define RTL8188F_TRANS_PDN_TO_CARDEMU												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
++
++#define RTL8188F_TRANS_ACT_TO_LPS														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*set RPWM IMR*/	\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
++	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/	\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
++	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
++
++
++#define RTL8188F_TRANS_LPS_TO_ACT															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84},  /*SDIO RPWM*/\
++	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
++	{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x35},/*xtal_qsel = 1 for low noise*/	\
++	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
++	{0x002B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x1c, 0x1c},   /*.	0x2b[4:2] = 3b'111	to enable BB, AFE clock*/\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0},  /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
++
++
++#define RTL8188F_TRANS_ACT_TO_SWLPS														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*set RPWM IMR*/	\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
++	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/	\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
++	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
++	{0x002b, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x1C, 0x00},/*0x2b[4:2]<=0 to gated BB, AFE clock*/	\
++	{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x34},/*xtal_qsel = 0 for bring up*/	\
++	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x00},/* sdio LPS option*/	\
++	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x83},/* usb LPS option, open bandgap, xtal*/	\
++	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /* 0xC4[5]<=0, digital LDO no standby mode*/	\
++	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /* 0xC4[7]<=1, on domain voltage adjust*/	\
++	{0x00a7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0xe0}, /* low power LPS enable for sdio*/	\
++	{0x00a7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0xe4}, /* low power LPS enable for usb*/	\
++	{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /* enable WL_LPS_EN*/
++
++
++#define RTL8188F_TRANS_SWLPS_TO_ACT															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1, enable security engine*/\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
++	{0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x09}, /*.	reset MAC rx state machine*/\
++	{0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x86}, /*.	reset MAC rx state machine*/\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/	\
++	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/	\
++	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/	\
++	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/	\
++	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/	\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */	\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
++
++#define RTL8188F_TRANS_END															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
++
++
++	extern WLAN_PWR_CFG rtl8188F_power_on_flow[RTL8188F_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188F_radio_off_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188F_card_disable_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188F_card_enable_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188F_suspend_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188F_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188F_resume_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188F_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188F_hwpdn_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188F_enter_lps_flow[RTL8188F_TRANS_ACT_TO_LPS_STEPS + RTL8188F_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188F_leave_lps_flow[RTL8188F_TRANS_LPS_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188F_enter_swlps_flow[RTL8188F_TRANS_ACT_TO_SWLPS_STEPS + RTL8188F_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8188F_leave_swlps_flow[RTL8188F_TRANS_SWLPS_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS];
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192EPhyCfg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192EPhyCfg.h
+new file mode 100644
+index 000000000..021d95335
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192EPhyCfg.h
+@@ -0,0 +1,136 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2012 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8192EPHYCFG_H__
++#define __INC_HAL8192EPHYCFG_H__
++
++
++/*--------------------------Define Parameters-------------------------------*/
++#define LOOP_LIMIT				5
++#define MAX_STALL_TIME			50		/* us */
++#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
++#define MAX_TXPWR_IDX_NMODE_92S	63
++#define Reset_Cnt_Limit			3
++
++#ifdef CONFIG_PCI_HCI
++	#define MAX_AGGR_NUM	0x0B
++#else
++	#define MAX_AGGR_NUM	0x07
++#endif /* CONFIG_PCI_HCI */
++
++
++/*--------------------------Define Parameters-------------------------------*/
++
++/*------------------------------Define structure----------------------------*/
++
++/* BB/RF related */
++
++/*------------------------------Define structure----------------------------*/
++
++
++/*------------------------Export global variable----------------------------*/
++/*------------------------Export global variable----------------------------*/
++
++
++/*------------------------Export Marco Definition---------------------------*/
++/*------------------------Export Marco Definition---------------------------*/
++
++
++/*--------------------------Exported Function prototype---------------------*/
++/*
++ * BB and RF register read/write
++ *   */
++u32	PHY_QueryBBReg8192E(PADAPTER	Adapter,
++				u32			RegAddr,
++				u32			BitMask);
++void	PHY_SetBBReg8192E(PADAPTER		Adapter,
++				u32			RegAddr,
++				u32			BitMask,
++				u32			Data);
++u32	PHY_QueryRFReg8192E(PADAPTER	Adapter,
++				enum rf_path	eRFPath,
++				u32			RegAddr,
++				u32			BitMask);
++void	PHY_SetRFReg8192E(PADAPTER		Adapter,
++				enum rf_path	eRFPath,
++				u32			RegAddr,
++				u32			BitMask,
++				u32			Data);
++
++/*
++ * Initialization related function
++ *
++ * MAC/BB/RF HAL config */
++int	PHY_MACConfig8192E(PADAPTER	Adapter);
++int	PHY_BBConfig8192E(PADAPTER	Adapter);
++int	PHY_RFConfig8192E(PADAPTER	Adapter);
++
++/* RF config */
++
++
++/*
++ * BB TX Power R/W
++ *   */
++void	PHY_SetTxPowerLevel8192E(PADAPTER	Adapter, u8	channel);
++
++void
++PHY_SetTxPowerIndex_8192E(
++		PADAPTER			Adapter,
++		u32					PowerIndex,
++		enum rf_path			RFPath,
++		u8					Rate
++);
++
++/*
++ * channel switch related funciton
++ *   */
++void
++PHY_SetSwChnlBWMode8192E(
++		PADAPTER			Adapter,
++		u8					channel,
++		enum channel_width	Bandwidth,
++		u8					Offset40,
++		u8					Offset80
++);
++
++void
++PHY_SetRFEReg_8192E(
++		PADAPTER		Adapter
++);
++
++void
++phy_SpurCalibration_8192E(
++		PADAPTER			Adapter,
++		enum spur_cal_method	method
++);
++void PHY_SpurCalibration_8192E( PADAPTER Adapter);
++
++#ifdef CONFIG_SPUR_CAL_NBI
++void
++phy_SpurCalibration_8192E_NBI(
++		PADAPTER			Adapter
++);
++#endif
++/*
++ * BB/MAC/RF other monitor API
++ *   */
++
++void
++phy_set_rf_path_switch_8192e(
++		struct dm_struct		*phydm,
++		bool		bMain
++);
++
++/*--------------------------Exported Function prototype---------------------*/
++#endif /* __INC_HAL8192CPHYCFG_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192EPhyReg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192EPhyReg.h
+new file mode 100644
+index 000000000..30b771111
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192EPhyReg.h
+@@ -0,0 +1,1146 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2012 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*****************************************************************************
++ *	Copyright(c) 2008,  RealTEK Technology Inc. All Right Reserved.
++ *
++ * Module:	__INC_HAL8192SPHYREG_H
++ *
++ *
++ * Note:	1. Define PMAC/BB register map
++ *			2. Define RF register map
++ *			3. PMAC/BB register bit mask.
++ *			4. RF reg bit mask.
++ *			5. Other BB/RF relative definition.
++ *
++ *
++ * Export:	Constants, macro, functions(API), global variables(None).
++ *
++ * Abbrev:
++ *
++ * History:
++ *		Data		Who		Remark
++ *      08/07/2007  MHC	1. Porting from 9x series PHYCFG.h.
++ *							2. Reorganize code architecture.
++ *	09/25/2008	MH		1. Add RL6052 register definition
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8192EPHYREG_H
++#define __INC_HAL8192EPHYREG_H
++
++
++/*--------------------------Define Parameters-------------------------------*/
++
++/* ************************************************************
++ * 8192S Regsiter offset definition
++ * ************************************************************ */
++
++/*
++ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
++ * 3. RF register 0x00-2E
++ * 4. Bit Mask for BB/RF register
++ * 5. Other defintion for BB/RF R/W
++ *   */
++
++
++/*
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 1. Page1(0x100)
++ *   */
++#define		rPMAC_Reset					0x100
++#define		rPMAC_TxStart				0x104
++#define		rPMAC_TxLegacySIG			0x108
++#define		rPMAC_TxHTSIG1				0x10c
++#define		rPMAC_TxHTSIG2				0x110
++#define		rPMAC_PHYDebug				0x114
++#define		rPMAC_TxPacketNum			0x118
++#define		rPMAC_TxIdle					0x11c
++#define		rPMAC_TxMACHeader0			0x120
++#define		rPMAC_TxMACHeader1			0x124
++#define		rPMAC_TxMACHeader2			0x128
++#define		rPMAC_TxMACHeader3			0x12c
++#define		rPMAC_TxMACHeader4			0x130
++#define		rPMAC_TxMACHeader5			0x134
++#define		rPMAC_TxDataType				0x138
++#define		rPMAC_TxRandomSeed			0x13c
++#define		rPMAC_CCKPLCPPreamble		0x140
++#define		rPMAC_CCKPLCPHeader			0x144
++#define		rPMAC_CCKCRC16				0x148
++#define		rPMAC_OFDMRxCRC32OK		0x170
++#define		rPMAC_OFDMRxCRC32Er		0x174
++#define		rPMAC_OFDMRxParityEr			0x178
++#define		rPMAC_OFDMRxCRC8Er			0x17c
++#define		rPMAC_CCKCRxRC16Er			0x180
++#define		rPMAC_CCKCRxRC32Er			0x184
++#define		rPMAC_CCKCRxRC32OK			0x188
++#define		rPMAC_TxStatus				0x18c
++
++
++/*
++ * 3. Page8(0x800)
++ *   */
++#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
++
++#define		rFPGA0_TxInfo					0x804	/* Status report?? */
++#define		rFPGA0_PSDFunction			0x808
++
++#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
++
++#define		rFPGA0_RFTiming1				0x810	/* Useless now */
++#define		rFPGA0_RFTiming2				0x814
++
++#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
++#define		rFPGA0_XA_HSSIParameter2		0x824
++#define		rFPGA0_XB_HSSIParameter1		0x828
++#define		rFPGA0_XB_HSSIParameter2		0x82c
++
++#define		rFPGA0_XA_LSSIParameter		0x840
++#define		rFPGA0_XB_LSSIParameter		0x844
++
++#define		rFPGA0_RFWakeUpParameter	0x850	/* Useless now */
++#define		rFPGA0_RFSleepUpParameter		0x854
++
++#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
++#define		rFPGA0_XCD_SwitchControl		0x85c
++
++#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
++#define		rFPGA0_XB_RFInterfaceOE		0x864
++
++#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
++#define		rFPGA0_XCD_RFInterfaceSW		0x874
++
++#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
++#define		rFPGA0_XCD_RFParameter		0x87c
++
++#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
++#define		rFPGA0_AnalogParameter2		0x884
++#define		rFPGA0_AnalogParameter3		0x888
++#define		rFPGA0_AdDaClockEn			0x888	/* enable ad/da clock1 for dual-phy */
++#define		rFPGA0_AnalogParameter4		0x88c
++
++#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
++#define		rFPGA0_XB_LSSIReadBack		0x8a4
++#define		rFPGA0_XC_LSSIReadBack		0x8a8
++#define		rFPGA0_XD_LSSIReadBack		0x8ac
++
++#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
++#define		TransceiverA_HSPI_Readback		0x8b8	/* Transceiver A HSPI Readback */
++#define		TransceiverB_HSPI_Readback		0x8bc	/* Transceiver B HSPI Readback */
++#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
++#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
++
++/*
++ * 4. Page9(0x900)
++ *   */
++#define		rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
++
++#define		rFPGA1_TxBlock				0x904	/* Useless now */
++#define		rFPGA1_DebugSelect			0x908	/* Useless now */
++#define		rFPGA1_TxInfo					0x90c	/* Useless now */ /* Status report?? */
++
++/*
++ * 5. PageA(0xA00)
++ *
++ * Set Control channel to upper or lower. These settings are required only for 40MHz */
++#define		rCCK0_System					0xa00
++
++#define		rCCK0_AFESetting				0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
++#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
++
++#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
++#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
++
++#define		rCCK0_RxHP					0xa14
++
++#define		rCCK0_DSPParameter1			0xa18	/* Timing recovery & Channel estimation threshold */
++#define		rCCK0_DSPParameter2			0xa1c	/* SQ threshold */
++
++#define		rCCK0_TxFilter1				0xa20
++#define		rCCK0_TxFilter2				0xa24
++#define		rCCK0_DebugPort				0xa28	/* debug port and Tx filter3 */
++#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
++#define		rCCK0_TRSSIReport			0xa50
++#define		rCCK0_RxReport            			0xa54  /* 0xa57 */
++#define		rCCK0_FACounterLower      		0xa5c  /* 0xa5b */
++#define		rCCK0_FACounterUpper      		0xa58  /* 0xa5c */
++
++/*
++ * PageB(0xB00)
++ *   */
++#define		rPdp_AntA					0xb00
++#define		rPdp_AntA_4				0xb04
++#define		rConfig_Pmpd_AntA			0xb28
++#define		rConfig_ram64x16				0xb2c
++
++#define		rConfig_AntA					0xb68
++#define		rConfig_AntB					0xb6c
++#define		rPdp_AntB					0xb70
++#define		rPdp_AntB_4					0xb74
++#define		rConfig_Pmpd_AntB			0xb98
++#define		rAPK							0xbd8
++
++
++
++/*
++ * 6. PageC(0xC00)
++ *   */
++#define		rOFDM0_LSTF					0xc00
++
++#define		rOFDM0_TRxPathEnable			0xc04
++#define		rOFDM0_TRMuxPar				0xc08
++#define		rOFDM0_TRSWIsolation			0xc0c
++
++#define		rOFDM0_XARxAFE				0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
++#define		rOFDM0_XARxIQImbalance    		0xc14  /* RxIQ imblance matrix */
++#define		rOFDM0_XBRxAFE			0xc18
++#define		rOFDM0_XBRxIQImbalance		0xc1c
++#define		rOFDM0_XCRxAFE			0xc20
++#define		rOFDM0_XCRxIQImbalance		0xc24
++#define		rOFDM0_XDRxAFE			0xc28
++#define		rOFDM0_XDRxIQImbalance		0xc2c
++
++#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
++#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
++#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
++#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
++
++#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
++#define		rOFDM0_CFOandDAGC			0xc44  /* CFO & DAGC */
++#define		rOFDM0_CCADropThreshold		0xc48 /* CCA Drop threshold */
++#define		rOFDM0_ECCAThreshold			0xc4c /* energy CCA */
++
++#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
++#define		rOFDM0_XAAGCCore2			0xc54
++#define		rOFDM0_XBAGCCore1			0xc58
++#define		rOFDM0_XBAGCCore2			0xc5c
++#define		rOFDM0_XCAGCCore1			0xc60
++#define		rOFDM0_XCAGCCore2			0xc64
++#define		rOFDM0_XDAGCCore1			0xc68
++#define		rOFDM0_XDAGCCore2			0xc6c
++
++#define		rOFDM0_AGCParameter1		0xc70
++#define		rOFDM0_AGCParameter2		0xc74
++#define		rOFDM0_AGCRSSITable			0xc78
++#define		rOFDM0_HTSTFAGC				0xc7c
++
++#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
++#define		rOFDM0_XATxAFE				0xc84
++#define		rOFDM0_XBTxIQImbalance		0xc88
++#define		rOFDM0_XBTxAFE				0xc8c
++#define		rOFDM0_XCTxIQImbalance		0xc90
++#define		rOFDM0_XCTxAFE			0xc94
++#define		rOFDM0_XDTxIQImbalance		0xc98
++#define		rOFDM0_XDTxAFE				0xc9c
++
++#define		rOFDM0_RxIQExtAnta			0xca0
++#define		rOFDM0_TxCoeff1				0xca4
++#define		rOFDM0_TxCoeff2				0xca8
++#define		rOFDM0_TxCoeff3				0xcac
++#define		rOFDM0_TxCoeff4				0xcb0
++#define		rOFDM0_TxCoeff5				0xcb4
++#define		rOFDM0_RxHPParameter		0xce0
++#define		rOFDM0_TxPseudoNoiseWgt		0xce4
++#define		rOFDM0_FrameSync			0xcf0
++#define		rOFDM0_DFSReport			0xcf4
++
++
++/*
++ * 7. PageD(0xD00)
++ *   */
++#define		rOFDM1_LSTF					0xd00
++#define		rOFDM1_TRxPathEnable			0xd04
++
++#define		rOFDM1_CFO					0xd08	/* No setting now */
++#define		rOFDM1_CSI1					0xd10
++#define		rOFDM1_SBD					0xd14
++#define		rOFDM1_CSI2					0xd18
++#define		rOFDM1_CFOTracking			0xd2c
++#define		rOFDM1_TRxMesaure1			0xd34
++#define		rOFDM1_IntfDet				0xd3c
++#define		rOFDM1_PseudoNoiseStateAB	0xd50
++#define		rOFDM1_PseudoNoiseStateCD	0xd54
++#define		rOFDM1_RxPseudoNoiseWgt		0xd58
++
++#define		rOFDM_PHYCounter1			0xda0  /* cca, parity fail */
++#define		rOFDM_PHYCounter2			0xda4  /* rate illegal, crc8 fail */
++#define		rOFDM_PHYCounter3			0xda8  /* MCS not support */
++
++#define		rOFDM_ShortCFOAB			0xdac	/* No setting now */
++#define		rOFDM_ShortCFOCD			0xdb0
++#define		rOFDM_LongCFOAB				0xdb4
++#define		rOFDM_LongCFOCD				0xdb8
++#define		rOFDM_TailCFOAB				0xdbc
++#define		rOFDM_TailCFOCD				0xdc0
++#define		rOFDM_PWMeasure1		0xdc4
++#define		rOFDM_PWMeasure2		0xdc8
++#define		rOFDM_BWReport				0xdcc
++#define		rOFDM_AGCReport				0xdd0
++#define		rOFDM_RxSNR				0xdd4
++#define		rOFDM_RxEVMCSI				0xdd8
++#define		rOFDM_SIGReport				0xddc
++
++
++/*
++ * 8. PageE(0xE00)
++ *   */
++#define		rTxAGC_A_Rate18_06			0xe00
++#define		rTxAGC_A_Rate54_24			0xe04
++#define		rTxAGC_A_CCK1_Mcs32			0xe08
++#define		rTxAGC_A_Mcs03_Mcs00		0xe10
++#define		rTxAGC_A_Mcs07_Mcs04		0xe14
++#define		rTxAGC_A_Mcs11_Mcs08		0xe18
++#define		rTxAGC_A_Mcs15_Mcs12		0xe1c
++
++#define		rTxAGC_B_Rate18_06			0x830
++#define		rTxAGC_B_Rate54_24			0x834
++#define		rTxAGC_B_CCK1_55_Mcs32		0x838
++#define		rTxAGC_B_Mcs03_Mcs00		0x83c
++#define		rTxAGC_B_Mcs07_Mcs04		0x848
++#define		rTxAGC_B_Mcs11_Mcs08		0x84c
++#define		rTxAGC_B_Mcs15_Mcs12		0x868
++#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
++
++#define		rFPGA0_IQK					0xe28
++#define		rTx_IQK_Tone_A				0xe30
++#define		rRx_IQK_Tone_A				0xe34
++#define		rTx_IQK_PI_A					0xe38
++#define		rRx_IQK_PI_A					0xe3c
++
++#define		rTx_IQK						0xe40
++#define		rRx_IQK						0xe44
++#define		rIQK_AGC_Pts					0xe48
++#define		rIQK_AGC_Rsp					0xe4c
++#define		rTx_IQK_Tone_B				0xe50
++#define		rRx_IQK_Tone_B				0xe54
++#define		rTx_IQK_PI_B					0xe58
++#define		rRx_IQK_PI_B					0xe5c
++#define		rIQK_AGC_Cont				0xe60
++
++#define		rBlue_Tooth					0xe6c
++#define		rRx_Wait_CCA					0xe70
++#define		rTx_CCK_RFON					0xe74
++#define		rTx_CCK_BBON				0xe78
++#define		rTx_OFDM_RFON				0xe7c
++#define		rTx_OFDM_BBON				0xe80
++#define		rTx_To_Rx					0xe84
++#define		rTx_To_Tx					0xe88
++#define		rRx_CCK						0xe8c
++
++#define		rTx_Power_Before_IQK_A		0xe94
++#define		rTx_Power_After_IQK_A			0xe9c
++
++#define		rRx_Power_Before_IQK_A		0xea0
++#define		rRx_Power_Before_IQK_A_2		0xea4
++#define		rRx_Power_After_IQK_A			0xea8
++#define		rRx_Power_After_IQK_A_2		0xeac
++
++#define		rTx_Power_Before_IQK_B		0xeb4
++#define		rTx_Power_After_IQK_B			0xebc
++
++#define		rRx_Power_Before_IQK_B		0xec0
++#define		rRx_Power_Before_IQK_B_2		0xec4
++#define		rRx_Power_After_IQK_B			0xec8
++#define		rRx_Power_After_IQK_B_2		0xecc
++
++#define		rRx_OFDM					0xed0
++#define		rRx_Wait_RIFS				0xed4
++#define		rRx_TO_Rx					0xed8
++#define		rStandby						0xedc
++#define		rSleep						0xee0
++#define		rPMPD_ANAEN				0xeec
++
++/*
++ * 7. RF Register 0x00-0x2E (RF 8256)
++ * RF-0222D 0x00-3F
++ *
++ * Zebra1 */
++#define		rZebra1_HSSIEnable				0x0	/* Useless now */
++#define		rZebra1_TRxEnable1			0x1
++#define		rZebra1_TRxEnable2			0x2
++#define		rZebra1_AGC					0x4
++#define		rZebra1_ChargePump			0x5
++#define		rZebra1_Channel				0x7	/* RF channel switch */
++
++/* #endif */
++#define		rZebra1_TxGain				0x8	/* Useless now */
++#define		rZebra1_TxLPF					0x9
++#define		rZebra1_RxLPF					0xb
++#define		rZebra1_RxHPFCorner			0xc
++
++/* Zebra4 */
++#define		rGlobalCtrl					0	/* Useless now */
++#define		rRTL8256_TxLPF				19
++#define		rRTL8256_RxLPF				11
++
++/* RTL8258 */
++#define		rRTL8258_TxLPF				0x11	/* Useless now */
++#define		rRTL8258_RxLPF				0x13
++#define		rRTL8258_RSSILPF				0xa
++
++/*
++ * RL6052 Register definition
++ *   */
++#define		RF_AC						0x00	/*  */
++
++#define		RF_IQADJ_G1					0x01	/*  */
++#define		RF_IQADJ_G2					0x02	/*  */
++
++#define		RF_POW_TRSW				0x05	/*  */
++
++#define		RF_GAIN_RX					0x06	/*  */
++#define		RF_GAIN_TX					0x07	/*  */
++
++#define		RF_TXM_IDAC					0x08	/*  */
++#define		RF_IPA_G						0x09	/*  */
++#define		RF_TXBIAS_G					0x0A
++#define		RF_TXPA_AG					0x0B
++#define		RF_IPA_A						0x0C	/*  */
++#define		RF_TXBIAS_A					0x0D
++#define		RF_BS_PA_APSET_G9_G11		0x0E
++#define		RF_BS_IQGEN					0x0F	/*  */
++
++#define		RF_MODE1					0x10	/*  */
++#define		RF_MODE2					0x11	/*  */
++
++#define		RF_RX_AGC_HP				0x12	/*  */
++#define		RF_TX_AGC					0x13	/*  */
++#define		RF_BIAS						0x14	/*  */
++#define		RF_IPA						0x15	/*  */
++#define		RF_TXBIAS					0x16
++#define		RF_POW_ABILITY				0x17	/*  */
++#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
++#define		RF_TOP						0x19	/*  */
++
++#define		RF_RX_G1					0x1A	/*  */
++#define		RF_RX_G2					0x1B	/*  */
++
++#define		RF_RX_BB2					0x1C	/*  */
++#define		RF_RX_BB1					0x1D	/*  */
++
++#define		RF_RCK1						0x1E	/*  */
++#define		RF_RCK2						0x1F	/*  */
++
++#define		RF_TX_G1						0x20	/*  */
++#define		RF_TX_G2						0x21	/*  */
++#define		RF_TX_G3						0x22	/*  */
++
++#define		RF_TX_BB1					0x23	/*  */
++
++#define		RF_T_METER_8192E			0x42	/*  */
++#define		RF_T_METER_88E				0x42
++#define		RF_T_METER					0x24	/*  */
++
++/* #endif */
++
++#define		RF_SYN_G1					0x25	/* RF TX Power control */
++#define		RF_SYN_G2					0x26	/* RF TX Power control */
++#define		RF_SYN_G3					0x27	/* RF TX Power control */
++#define		RF_SYN_G4					0x28	/* RF TX Power control */
++#define		RF_SYN_G5					0x29	/* RF TX Power control */
++#define		RF_SYN_G6					0x2A	/* RF TX Power control */
++#define		RF_SYN_G7					0x2B	/* RF TX Power control */
++#define		RF_SYN_G8					0x2C	/* RF TX Power control */
++
++#define		RF_RCK_OS					0x30	/* RF TX PA control */
++#define		RF_TXPA_G1					0x31	/* RF TX PA control */
++#define		RF_TXPA_G2					0x32	/* RF TX PA control */
++#define		RF_TXPA_G3					0x33	/* RF TX PA control */
++#define		RF_TX_BIAS_A					0x35
++#define		RF_TX_BIAS_D					0x36
++#define		RF_LOBF_9					0x38
++#define		RF_RXRF_A3					0x3C	/*	 */
++#define		RF_TRSW						0x3F
++
++#define		RF_TXRF_A2					0x41
++#define		RF_TXPA_G4					0x46
++#define		RF_TXPA_A4					0x4B
++#define		RF_0x52						0x52
++#define		RF_LDO						0xB1
++#define		RF_WE_LUT					0xEF
++
++
++/*
++ * Bit Mask
++ *
++ * 1. Page1(0x100) */
++#define		bBBResetB					0x100	/* Useless now? */
++#define		bGlobalResetB					0x200
++#define		bOFDMTxStart					0x4
++#define		bCCKTxStart					0x8
++#define		bCRC32Debug					0x100
++#define		bPMACLoopback				0x10
++#define		bTxLSIG						0xffffff
++#define		bOFDMTxRate					0xf
++#define		bOFDMTxReserved				0x10
++#define		bOFDMTxLength				0x1ffe0
++#define		bOFDMTxParity				0x20000
++#define		bTxHTSIG1					0xffffff
++#define		bTxHTMCSRate				0x7f
++#define		bTxHTBW						0x80
++#define		bTxHTLength					0xffff00
++#define		bTxHTSIG2					0xffffff
++#define		bTxHTSmoothing				0x1
++#define		bTxHTSounding				0x2
++#define		bTxHTReserved				0x4
++#define		bTxHTAggreation				0x8
++#define		bTxHTSTBC					0x30
++#define		bTxHTAdvanceCoding			0x40
++#define		bTxHTShortGI					0x80
++#define		bTxHTNumberHT_LTF			0x300
++#define		bTxHTCRC8					0x3fc00
++#define		bCounterReset				0x10000
++#define		bNumOfOFDMTx				0xffff
++#define		bNumOfCCKTx					0xffff0000
++#define		bTxIdleInterval				0xffff
++#define		bOFDMService					0xffff0000
++#define		bTxMACHeader				0xffffffff
++#define		bTxDataInit					0xff
++#define		bTxHTMode					0x100
++#define		bTxDataType					0x30000
++#define		bTxRandomSeed				0xffffffff
++#define		bCCKTxPreamble				0x1
++#define		bCCKTxSFD					0xffff0000
++#define		bCCKTxSIG					0xff
++#define		bCCKTxService					0xff00
++#define		bCCKLengthExt					0x8000
++#define		bCCKTxLength					0xffff0000
++#define		bCCKTxCRC16					0xffff
++#define		bCCKTxStatus					0x1
++#define		bOFDMTxStatus				0x2
++
++#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
++#define		RF_TX_GAIN_OFFSET_8192E(_val)		((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
++
++
++/* 2. Page8(0x800) */
++#define		bRFMOD						0x1	/* Reg 0x800 rFPGA0_RFMOD */
++#define		bJapanMode					0x2
++#define		bCCKTxSC						0x30
++#define		bCCKEn						0x1000000
++#define		bOFDMEn					0x2000000
++
++#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
++#define		bOFDMTxDACPhase		0x40000
++#define		bXATxAGC				0x3f
++
++#define		bAntennaSelect			0x0300
++
++#define		bXBTxAGC                  				0xf00	/* Reg 80c rFPGA0_TxGainStage */
++#define		bXCTxAGC				0xf000
++#define		bXDTxAGC				0xf0000
++
++#define		bPAStart                  				0xf0000000	/* Useless now */
++#define		bTRStart				0x00f00000
++#define		bRFStart				0x0000f000
++#define		bBBStart				0x000000f0
++#define		bBBCCKStart			0x0000000f
++#define		bPAEnd                    				0xf          /* Reg0x814 */
++#define		bTREnd				0x0f000000
++#define		bRFEnd				0x000f0000
++#define		bCCAMask                  				0x000000f0   /* T2R */
++#define		bR2RCCAMask			0x00000f00
++#define		bHSSI_R2TDelay			0xf8000000
++#define		bHSSI_T2RDelay			0xf80000
++#define		bContTxHSSI               			0x400     /* chane gain at continue Tx */
++#define		bIGFromCCK			0x200
++#define		bAGCAddress			0x3f
++#define		bRxHPTx				0x7000
++#define		bRxHPT2R				0x38000
++#define		bRxHPCCKIni			0xc0000
++#define		bAGCTxCode			0xc00000
++#define		bAGCRxCode			0x300000
++
++#define		b3WireDataLength          			0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
++#define		b3WireAddressLength		0x400
++
++#define		b3WireRFPowerDown         		0x1	/* Useless now
++ * #define bHWSISelect		0x8 */
++#define		b5GPAPEPolarity			0x40000000
++#define		b2GPAPEPolarity			0x80000000
++#define		bRFSW_TxDefaultAnt		0x3
++#define		bRFSW_TxOptionAnt		0x30
++#define		bRFSW_RxDefaultAnt		0x300
++#define		bRFSW_RxOptionAnt		0x3000
++#define		bRFSI_3WireData			0x1
++#define		bRFSI_3WireClock			0x2
++#define		bRFSI_3WireLoad			0x4
++#define		bRFSI_3WireRW			0x8
++#define		bRFSI_3Wire			0xf
++
++#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
++
++#define		bRFSI_TRSW                		0x20	/* Useless now */
++#define		bRFSI_TRSWB		0x40
++#define		bRFSI_ANTSW		0x100
++#define		bRFSI_ANTSWB		0x200
++#define		bRFSI_PAPE			0x400
++#define		bRFSI_PAPE5G		0x800
++#define		bBandSelect			0x1
++#define		bHTSIG2_GI			0x80
++#define		bHTSIG2_Smoothing		0x01
++#define		bHTSIG2_Sounding		0x02
++#define		bHTSIG2_Aggreaton		0x08
++#define		bHTSIG2_STBC		0x30
++#define		bHTSIG2_AdvCoding		0x40
++#define		bHTSIG2_NumOfHTLTF	0x300
++#define		bHTSIG2_CRC8		0x3fc
++#define		bHTSIG1_MCS		0x7f
++#define		bHTSIG1_BandWidth		0x80
++#define		bHTSIG1_HTLength		0xffff
++#define		bLSIG_Rate			0xf
++#define		bLSIG_Reserved		0x10
++#define		bLSIG_Length		0x1fffe
++#define		bLSIG_Parity			0x20
++#define		bCCKRxPhase		0x4
++
++#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
++
++#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
++
++#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
++
++#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
++#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
++#define		bRegulator0Standby		0x1
++#define		bRegulatorPLLStandby	0x2
++#define		bRegulator1Standby		0x4
++#define		bPLLPowerUp		0x8
++#define		bDPLLPowerUp		0x10
++#define		bDA10PowerUp		0x20
++#define		bAD7PowerUp		0x200
++#define		bDA6PowerUp		0x2000
++#define		bXtalPowerUp		0x4000
++#define		b40MDClkPowerUP	0x8000
++#define		bDA6DebugMode		0x20000
++#define		bDA6Swing			0x380000
++
++#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
++
++#define		b80MClkDelay              		0x18000000	/* Useless */
++#define		bAFEWatchDogEnable	0x20000000
++
++#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
++#define		bXtalCap23			0x3
++#define		bXtalCap92x				0x0f000000
++#define		bXtalCap			0x0f000000
++
++#define		bIntDifClkEnable          		0x400	/* Useless */
++#define		bExtSigClkEnable		0x800
++#define		bBandgapMbiasPowerUp	0x10000
++#define		bAD11SHGain		0xc0000
++#define		bAD11InputRange		0x700000
++#define		bAD11OPCurrent		0x3800000
++#define		bIPathLoopback		0x4000000
++#define		bQPathLoopback		0x8000000
++#define		bAFELoopback		0x10000000
++#define		bDA10Swing		0x7e0
++#define		bDA10Reverse		0x800
++#define		bDAClkSource		0x1000
++#define		bAD7InputRange		0x6000
++#define		bAD7Gain			0x38000
++#define		bAD7OutputCMMode	0x40000
++#define		bAD7InputCMMode	0x380000
++#define		bAD7Current		0xc00000
++#define		bRegulatorAdjust		0x7000000
++#define		bAD11PowerUpAtTx	0x1
++#define		bDA10PSAtTx		0x10
++#define		bAD11PowerUpAtRx	0x100
++#define		bDA10PSAtRx		0x1000
++#define		bCCKRxAGCFormat		0x200
++#define		bPSDFFTSamplepPoint	0xc000
++#define		bPSDAverageNum		0x3000
++#define		bIQPathControl		0xc00
++#define		bPSDFreq			0x3ff
++#define		bPSDAntennaPath		0x30
++#define		bPSDIQSwitch		0x40
++#define		bPSDRxTrigger		0x400000
++#define		bPSDTxTrigger		0x80000000
++#define		bPSDSineToneScale		0x7f000000
++#define		bPSDReport		0xffff
++
++/* 3. Page9(0x900) */
++#define		bOFDMTxSC                 		0x30000000	/* Useless */
++#define		bCCKTxOn			0x1
++#define		bOFDMTxOn		0x2
++#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
++#define		bDebugItem                		0xff   /* reset debug page and LWord */
++#define		bAntL				0x10
++#define		bAntNonHT			0x100
++#define		bAntHT1			0x1000
++#define		bAntHT2			0x10000
++#define		bAntHT1S1			0x100000
++#define		bAntNonHTS1		0x1000000
++
++/* 4. PageA(0xA00) */
++#define		bCCKBBMode                		0x3	/* Useless */
++#define		bCCKTxPowerSaving		0x80
++#define		bCCKRxPowerSaving		0x40
++
++#define		bCCKSideBand              		0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
++
++#define		bCCKScramble              		0x8	/* Useless */
++#define		bCCKAntDiversity			0x8000
++#define		bCCKCarrierRecovery		0x4000
++#define		bCCKTxRate			0x3000
++#define		bCCKDCCancel		0x0800
++#define		bCCKISICancel		0x0400
++#define		bCCKMatchFilter		0x0200
++#define		bCCKEqualizer		0x0100
++#define		bCCKPreambleDetect		0x800000
++#define		bCCKFastFalseCCA		0x400000
++#define		bCCKChEstStart		0x300000
++#define		bCCKCCACount		0x080000
++#define		bCCKcs_lim			0x070000
++#define		bCCKBistMode		0x80000000
++#define		bCCKCCAMask		0x40000000
++#define		bCCKTxDACPhase		0x4
++#define		bCCKRxADCPhase         	   	0x20000000   /* r_rx_clk */
++#define		bCCKr_cp_mode0		0x0100
++#define		bCCKTxDCOffset		0xf0
++#define		bCCKRxDCOffset		0xf
++#define		bCCKCCAMode		0xc000
++#define		bCCKFalseCS_lim		0x3f00
++#define		bCCKCS_ratio		0xc00000
++#define		bCCKCorgBit_sel		0x300000
++#define		bCCKPD_lim		0x0f0000
++#define		bCCKNewCCA		0x80000000
++#define		bCCKRxHPofIG		0x8000
++#define		bCCKRxIG			0x7f00
++#define		bCCKLNAPolarity		0x800000
++#define		bCCKRx1stGain		0x7f0000
++#define		bCCKRFExtend              		0x20000000 /* CCK Rx Iinital gain polarity */
++#define		bCCKRxAGCSatLevel		0x1f000000
++#define		bCCKRxAGCSatCount		0xe0
++#define		bCCKRxRFSettle            		0x1f       /* AGCsamp_dly */
++#define		bCCKFixedRxAGC		0x8000
++/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
++#define		bCCKAntennaPolarity		0x2000
++#define		bCCKTxFilterType		0x0c00
++#define		bCCKRxAGCReportType		0x0300
++#define		bCCKRxDAGCEn		0x80000000
++#define		bCCKRxDAGCPeriod		0x20000000
++#define		bCCKRxDAGCSatLevel		0x1f000000
++#define		bCCKTimingRecovery		0x800000
++#define		bCCKTxC0			0x3f0000
++#define		bCCKTxC1			0x3f000000
++#define		bCCKTxC2			0x3f
++#define		bCCKTxC3			0x3f00
++#define		bCCKTxC4			0x3f0000
++#define		bCCKTxC5			0x3f000000
++#define		bCCKTxC6			0x3f
++#define		bCCKTxC7			0x3f00
++#define		bCCKDebugPort		0xff0000
++#define		bCCKDACDebug		0x0f000000
++#define		bCCKFalseAlarmEnable	0x8000
++#define		bCCKFalseAlarmRead	0x4000
++#define		bCCKTRSSI			0x7f
++#define		bCCKRxAGCReport		0xfe
++#define		bCCKRxReport_AntSel	0x80000000
++#define		bCCKRxReport_MFOff	0x40000000
++#define		bCCKRxRxReport_SQLoss	0x20000000
++#define		bCCKRxReport_Pktloss	0x10000000
++#define		bCCKRxReport_Lockedbit	0x08000000
++#define		bCCKRxReport_RateError	0x04000000
++#define		bCCKRxReport_RxRate	0x03000000
++#define		bCCKRxFACounterLower	0xff
++#define		bCCKRxFACounterUpper	0xff000000
++#define		bCCKRxHPAGCStart		0xe000
++#define		bCCKRxHPAGCFinal		0x1c00
++#define		bCCKRxFalseAlarmEnable	0x8000
++#define		bCCKFACounterFreeze	0x4000
++#define		bCCKTxPathSel		0x10000000
++#define		bCCKDefaultRxPath		0xc000000
++#define		bCCKOptionRxPath		0x3000000
++
++/* 5. PageC(0xC00) */
++#define		bNumOfSTF                			0x3	/* Useless */
++#define		bShift_L			0xc0
++#define		bGI_TH			0xc
++#define		bRxPathA			0x1
++#define		bRxPathB			0x2
++#define		bRxPathC			0x4
++#define		bRxPathD			0x8
++#define		bTxPathA			0x1
++#define		bTxPathB			0x2
++#define		bTxPathC			0x4
++#define		bTxPathD			0x8
++#define		bTRSSIFreq			0x200
++#define		bADCBackoff			0x3000
++#define		bDFIRBackoff			0xc000
++#define		bTRSSILatchPhase		0x10000
++#define		bRxIDCOffset			0xff
++#define		bRxQDCOffset		0xff00
++#define		bRxDFIRMode		0x1800000
++#define		bRxDCNFType		0xe000000
++#define		bRXIQImb_A		0x3ff
++#define		bRXIQImb_B			0xfc00
++#define		bRXIQImb_C			0x3f0000
++#define		bRXIQImb_D		0xffc00000
++#define		bDC_dc_Notch		0x60000
++#define		bRxNBINotch		0x1f000000
++#define		bPD_TH			0xf
++#define		bPD_TH_Opt2		0xc000
++#define		bPWED_TH			0x700
++#define		bIfMF_Win_L		0x800
++#define		bPD_Option			0x1000
++#define		bMF_Win_L			0xe000
++#define		bBW_Search_L		0x30000
++#define		bwin_enh_L			0xc0000
++#define		bBW_TH			0x700000
++#define		bED_TH2			0x3800000
++#define		bBW_option			0x4000000
++#define		bRatio_TH			0x18000000
++#define		bWindow_L			0xe0000000
++#define		bSBD_Option		0x1
++#define		bFrame_TH			0x1c
++#define		bFS_Option			0x60
++#define		bDC_Slope_check		0x80
++#define		bFGuard_Counter_DC_L	0xe00
++#define		bFrame_Weight_Short	0x7000
++#define		bSub_Tune			0xe00000
++#define		bFrame_DC_Length		0xe000000
++#define		bSBD_start_offset		0x30000000
++#define		bFrame_TH_2		0x7
++#define		bFrame_GI2_TH		0x38
++#define		bGI2_Sync_en		0x40
++#define		bSarch_Short_Early		0x300
++#define		bSarch_Short_Late		0xc00
++#define		bSarch_GI2_Late		0x70000
++#define		bCFOAntSum		0x1
++#define		bCFOAcc			0x2
++#define		bCFOStartOffset		0xc
++#define		bCFOLookBack		0x70
++#define		bCFOSumWeight		0x80
++#define		bDAGCEnable		0x10000
++#define		bTXIQImb_A			0x3ff
++#define		bTXIQImb_B			0xfc00
++#define		bTXIQImb_C			0x3f0000
++#define		bTXIQImb_D			0xffc00000
++#define		bTxIDCOffset			0xff
++#define		bTxQDCOffset		0xff00
++#define		bTxDFIRMode		0x10000
++#define		bTxPesudoNoiseOn		0x4000000
++#define		bTxPesudoNoise_A		0xff
++#define		bTxPesudoNoise_B		0xff00
++#define		bTxPesudoNoise_C		0xff0000
++#define		bTxPesudoNoise_D		0xff000000
++#define		bCCADropOption		0x20000
++#define		bCCADropThres		0xfff00000
++#define		bEDCCA_H			0xf
++#define		bEDCCA_L			0xf0
++#define		bLambda_ED		0x300
++#define		bRxInitialGain			0x7f
++#define		bRxAntDivEn		0x80
++#define		bRxAGCAddressForLNA	0x7f00
++#define		bRxHighPowerFlow		0x8000
++#define		bRxAGCFreezeThres		0xc0000
++#define		bRxFreezeStep_AGC1	0x300000
++#define		bRxFreezeStep_AGC2	0xc00000
++#define		bRxFreezeStep_AGC3	0x3000000
++#define		bRxFreezeStep_AGC0	0xc000000
++#define		bRxRssi_Cmp_En		0x10000000
++#define		bRxQuickAGCEn		0x20000000
++#define		bRxAGCFreezeThresMode	0x40000000
++#define		bRxOverFlowCheckType	0x80000000
++#define		bRxAGCShift			0x7f
++#define		bTRSW_Tri_Only		0x80
++#define		bPowerThres		0x300
++#define		bRxAGCEn			0x1
++#define		bRxAGCTogetherEn		0x2
++#define		bRxAGCMin		0x4
++#define		bRxHP_Ini			0x7
++#define		bRxHP_TRLNA		0x70
++#define		bRxHP_RSSI			0x700
++#define		bRxHP_BBP1		0x7000
++#define		bRxHP_BBP2		0x70000
++#define		bRxHP_BBP3		0x700000
++#define		bRSSI_H                  			0x7f0000     /* the threshold for high power */
++#define		bRSSI_Gen                			0x7f000000   /* the threshold for ant diversity */
++#define		bRxSettle_TRSW		0x7
++#define		bRxSettle_LNA		0x38
++#define		bRxSettle_RSSI		0x1c0
++#define		bRxSettle_BBP		0xe00
++#define		bRxSettle_RxHP		0x7000
++#define		bRxSettle_AntSW_RSSI	0x38000
++#define		bRxSettle_AntSW		0xc0000
++#define		bRxProcessTime_DAGC	0x300000
++#define		bRxSettle_HSSI		0x400000
++#define		bRxProcessTime_BBPPW	0x800000
++#define		bRxAntennaPowerShift	0x3000000
++#define		bRSSITableSelect		0xc000000
++#define		bRxHP_Final			0x7000000
++#define		bRxHTSettle_BBP		0x7
++#define		bRxHTSettle_HSSI		0x8
++#define		bRxHTSettle_RxHP		0x70
++#define		bRxHTSettle_BBPPW		0x80
++#define		bRxHTSettle_Idle		0x300
++#define		bRxHTSettle_Reserved	0x1c00
++#define		bRxHTRxHPEn		0x8000
++#define		bRxHTAGCFreezeThres	0x30000
++#define		bRxHTAGCTogetherEn	0x40000
++#define		bRxHTAGCMin		0x80000
++#define		bRxHTAGCEn		0x100000
++#define		bRxHTDAGCEn		0x200000
++#define		bRxHTRxHP_BBP		0x1c00000
++#define		bRxHTRxHP_Final		0xe0000000
++#define		bRxPWRatioTH		0x3
++#define		bRxPWRatioEn		0x4
++#define		bRxMFHold			0x3800
++#define		bRxPD_Delay_TH1		0x38
++#define		bRxPD_Delay_TH2		0x1c0
++#define		bRxPD_DC_COUNT_MAX	0x600
++/* #define bRxMF_Hold               0x3800 */
++#define		bRxPD_Delay_TH		0x8000
++#define		bRxProcess_Delay		0xf0000
++#define		bRxSearchrange_GI2_Early	0x700000
++#define		bRxFrame_Guard_Counter_L	0x3800000
++#define		bRxSGI_Guard_L		0xc000000
++#define		bRxSGI_Search_L		0x30000000
++#define		bRxSGI_TH			0xc0000000
++#define		bDFSCnt0			0xff
++#define		bDFSCnt1			0xff00
++#define		bDFSFlag			0xf0000
++#define		bMFWeightSum		0x300000
++#define		bMinIdxTH			0x7f000000
++#define		bDAFormat			0x40000
++#define		bTxChEmuEnable		0x01000000
++#define		bTRSWIsolation_A		0x7f
++#define		bTRSWIsolation_B		0x7f00
++#define		bTRSWIsolation_C		0x7f0000
++#define		bTRSWIsolation_D		0x7f000000
++#define		bExtLNAGain		0x7c00
++
++/* 6. PageE(0xE00) */
++#define		bSTBCEn                  			0x4	/* Useless */
++#define		bAntennaMapping		0x10
++#define		bNss			0x20
++#define		bCFOAntSumD		0x200
++#define		bPHYCounterReset		0x8000000
++#define		bCFOReportGet		0x4000000
++#define		bOFDMContinueTx		0x10000000
++#define		bOFDMSingleCarrier		0x20000000
++#define		bOFDMSingleTone		0x40000000
++/* #define bRxPath1                 0x01 */
++/* #define bRxPath2                 0x02 */
++/* #define bRxPath3                 0x04 */
++/* #define bRxPath4                 0x08 */
++/* #define bTxPath1                 0x10 */
++/* #define bTxPath2                 0x20 */
++#define		bHTDetect			0x100
++#define		bCFOEn			0x10000
++#define		bCFOValue			0xfff00000
++#define		bSigTone_Re			0x3f
++#define		bSigTone_Im			0x7f00
++#define		bCounter_CCA		0xffff
++#define		bCounter_ParityFail		0xffff0000
++#define		bCounter_RateIllegal		0xffff
++#define		bCounter_CRC8Fail		0xffff0000
++#define		bCounter_MCSNoSupport	0xffff
++#define		bCounter_FastSync		0xffff
++#define		bShortCFO			0xfff
++#define		bShortCFOTLength         		12   /* total */
++#define		bShortCFOFLength         		11   /* fraction */
++#define		bLongCFO			0x7ff
++#define		bLongCFOTLength		11
++#define		bLongCFOFLength		11
++#define		bTailCFO			0x1fff
++#define		bTailCFOTLength		13
++#define		bTailCFOFLength		12
++#define		bmax_en_pwdB		0xffff
++#define		bCC_power_dB		0xffff0000
++#define		bnoise_pwdB		0xffff
++#define		bPowerMeasTLength	10
++#define		bPowerMeasFLength	3
++#define		bRx_HT_BW		0x1
++#define		bRxSC			0x6
++#define		bRx_HT			0x8
++#define		bNB_intf_det_on		0x1
++#define		bIntf_win_len_cfg		0x30
++#define		bNB_Intf_TH_cfg		0x1c0
++#define		bRFGain			0x3f
++#define		bTableSel			0x40
++#define		bTRSW			0x80
++#define		bRxSNR_A			0xff
++#define		bRxSNR_B			0xff00
++#define		bRxSNR_C			0xff0000
++#define		bRxSNR_D			0xff000000
++#define		bSNREVMTLength		8
++#define		bSNREVMFLength		1
++#define		bCSI1st			0xff
++#define		bCSI2nd			0xff00
++#define		bRxEVM1st			0xff0000
++#define		bRxEVM2nd		0xff000000
++#define		bSIGEVM			0xff
++#define		bPWDB			0xff00
++#define		bSGIEN			0x10000
++
++#define		bSFactorQAM1             		0xf	/* Useless */
++#define		bSFactorQAM2		0xf0
++#define		bSFactorQAM3		0xf00
++#define		bSFactorQAM4		0xf000
++#define		bSFactorQAM5		0xf0000
++#define		bSFactorQAM6		0xf0000
++#define		bSFactorQAM7		0xf00000
++#define		bSFactorQAM8		0xf000000
++#define		bSFactorQAM9		0xf0000000
++#define		bCSIScheme			0x100000
++
++#define		bNoiseLvlTopSet          		0x3	/* Useless */
++#define		bChSmooth			0x4
++#define		bChSmoothCfg1		0x38
++#define		bChSmoothCfg2		0x1c0
++#define		bChSmoothCfg3		0xe00
++#define		bChSmoothCfg4		0x7000
++#define		bMRCMode		0x800000
++#define		bTHEVMCfg			0x7000000
++
++#define		bLoopFitType             			0x1	/* Useless */
++#define		bUpdCFO			0x40
++#define		bUpdCFOOffData		0x80
++#define		bAdvUpdCFO		0x100
++#define		bAdvTimeCtrl		0x800
++#define		bUpdClko			0x1000
++#define		bFC				0x6000
++#define		bTrackingMode		0x8000
++#define		bPhCmpEnable		0x10000
++#define		bUpdClkoLTF			0x20000
++#define		bComChCFO		0x40000
++#define		bCSIEstiMode		0x80000
++#define		bAdvUpdEqz		0x100000
++#define		bUChCfg			0x7000000
++#define		bUpdEqz			0x8000000
++
++/* Rx Pseduo noise */
++#define		bRxPesudoNoiseOn         		0x20000000	/* Useless */
++#define		bRxPesudoNoise_A		0xff
++#define		bRxPesudoNoise_B		0xff00
++#define		bRxPesudoNoise_C		0xff0000
++#define		bRxPesudoNoise_D		0xff000000
++#define		bPesudoNoiseState_A	0xffff
++#define		bPesudoNoiseState_B	0xffff0000
++#define		bPesudoNoiseState_C		0xffff
++#define		bPesudoNoiseState_D	0xffff0000
++
++/* 7. RF Register
++ * Zebra1 */
++#define		bZebra1_HSSIEnable        		0x8		/* Useless */
++#define		bZebra1_TRxControl		0xc00
++#define		bZebra1_TRxGainSetting	0x07f
++#define		bZebra1_RxCorner		0xc00
++#define		bZebra1_TxChargePump	0x38
++#define		bZebra1_RxChargePump	0x7
++#define		bZebra1_ChannelNum	0xf80
++#define		bZebra1_TxLPFBW		0x400
++#define		bZebra1_RxLPFBW		0x600
++
++/* Zebra4 */
++#define		bRTL8256RegModeCtrl1      	0x100	/* Useless */
++#define		bRTL8256RegModeCtrl0	0x40
++#define		bRTL8256_TxLPFBW	0x18
++#define		bRTL8256_RxLPFBW	0x600
++
++/* RTL8258 */
++#define		bRTL8258_TxLPFBW          	0xc	/* Useless */
++#define		bRTL8258_RxLPFBW	0xc00
++#define		bRTL8258_RSSILPFBW	0xc0
++
++
++/*
++ * Other Definition
++ *   */
++
++/* byte endable for sb_write */
++#define		bByte0                    			0x1	/* Useless */
++#define		bByte1			0x2
++#define		bByte2			0x4
++#define		bByte3			0x8
++#define		bWord0			0x3
++#define		bWord1			0xc
++#define		bDWord			0xf
++
++/* for PutRegsetting & GetRegSetting BitMask */
++#define		bMaskByte0                		0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
++#define		bMaskByte1		0xff00
++#define		bMaskByte2		0xff0000
++#define		bMaskByte3		0xff000000
++#define		bMaskHWord		0xffff0000
++#define		bMaskLWord		0x0000ffff
++#define		bMaskDWord		0xffffffff
++#define		bMaskH3Bytes				0xffffff00
++#define		bMask12Bits				0xfff
++#define		bMaskH4Bits				0xf0000000
++#define		bMaskOFDM_D			0xffc00000
++#define		bMaskCCK				0x3f3f3f3f
++
++/* for PutRFRegsetting & GetRFRegSetting BitMask
++ * #define		bMask12Bits               0xfffff */	/* RF Reg mask bits
++ * #define		bMask20Bits               0xfffff */	/* RF Reg mask bits T65 RF */
++#define		bRFRegOffsetMask			0xfffff
++
++#define		bEnable                   0x1	/* Useless */
++#define		bDisable                  0x0
++
++#define		LeftAntenna               			0x0	/* Useless */
++#define		RightAntenna		0x1
++
++#define		tCheckTxStatus            		500   /* 500ms */ /* Useless */
++#define		tUpdateRxCounter          		100   /* 100ms */
++
++#define		rateCCK     				0	/* Useless */
++#define		rateOFDM				1
++#define		rateHT					2
++
++/* define Register-End */
++#define		bPMAC_End                 		0x1ff	/* Useless */
++#define		bFPGAPHY0_End		0x8ff
++#define		bFPGAPHY1_End		0x9ff
++#define		bCCKPHY0_End		0xaff
++#define		bOFDMPHY0_End		0xcff
++#define		bOFDMPHY1_End		0xdff
++
++/* define max debug item in each debug page
++ * #define bMaxItem_FPGA_PHY0        0x9
++ * #define bMaxItem_FPGA_PHY1        0x3
++ * #define bMaxItem_PHY_11B          0x16
++ * #define bMaxItem_OFDM_PHY0        0x29
++ * #define bMaxItem_OFDM_PHY1        0x0 */
++
++#define		bPMACControl              		0x0		/* Useless */
++#define		bWMACControl		0x1
++#define		bWNICControl		0x2
++
++#define		PathA                     			0x0	/* Useless */
++#define		PathB			0x1
++#define		PathC			0x2
++#define		PathD			0x3
++
++
++/* RSSI Dump Message */
++#define		rA_RSSIDump_92E			0xcb0
++#define		rB_RSSIDump_92E			0xcb1
++#define		rS1_RXevmDump_92E			0xcb2
++#define		rS2_RXevmDump_92E			0xcb3
++#define		rA_RXsnrDump_92E			0xcb4
++#define		rB_RXsnrDump_92E			0xcb5
++#define		rA_CfoShortDump_92E		0xcb6
++#define		rB_CfoShortDump_92E		0xcb8
++#define	rA_CfoLongDump_92E			0xcba
++#define		rB_CfoLongDump_92E			0xcbc
++
++/*--------------------------Define Parameters-------------------------------*/
++
++
++#endif /* __INC_HAL8188EPHYREG_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192EPwrSeq.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192EPwrSeq.h
+new file mode 100644
+index 000000000..1f2ba8722
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192EPwrSeq.h
+@@ -0,0 +1,169 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2012 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef REALTEK_POWER_SEQUENCE_8192E
++#define REALTEK_POWER_SEQUENCE_8192E
++
++#include "HalPwrSeqCmd.h"
++/*
++	Check document WM-20110607-Paul-RTL8192E_Power_Architecture-R02.vsd
++	There are 6 HW Power States:
++	0: POFF--Power Off
++	1: PDN--Power Down
++	2: CARDEMU--Card Emulation
++	3: ACT--Active Mode
++	4: LPS--Low Power State
++	5: SUS--Suspend
++
++	The transision from different states are defined below
++	TRANS_CARDEMU_TO_ACT
++	TRANS_ACT_TO_CARDEMU
++	TRANS_CARDEMU_TO_SUS
++	TRANS_SUS_TO_CARDEMU
++	TRANS_CARDEMU_TO_PDN
++	TRANS_ACT_TO_LPS
++	TRANS_LPS_TO_ACT
++
++	TRANS_END
++*/
++#define	RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS	18
++#define	RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS	18
++#define	RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS	18
++#define	RTL8192E_TRANS_SUS_TO_CARDEMU_STEPS	18
++#define	RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS	18
++#define	RTL8192E_TRANS_PDN_TO_CARDEMU_STEPS	18
++#define	RTL8192E_TRANS_ACT_TO_LPS_STEPS	23
++#define	RTL8192E_TRANS_LPS_TO_ACT_STEPS	23
++#define	RTL8192E_TRANS_END_STEPS	1
++
++
++#define RTL8192E_TRANS_CARDEMU_TO_ACT														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	\
++
++
++#define RTL8192E_TRANS_ACT_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
++	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
++
++
++#define RTL8192E_TRANS_CARDEMU_TO_SUS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
++
++#define RTL8192E_TRANS_SUS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
++
++#define RTL8192E_TRANS_CARDEMU_TO_CARDDIS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
++	{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*Unlock small LDO Register*/	\
++	{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*Disable small LDO*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
++
++#define RTL8192E_TRANS_CARDDIS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++	{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*Enable small LDO*/	\
++	{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*Lock small LDO Register*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
++
++
++#define RTL8192E_TRANS_CARDEMU_TO_PDN												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
++
++#define RTL8192E_TRANS_PDN_TO_CARDEMU												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
++
++#define RTL8192E_TRANS_ACT_TO_LPS														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
++	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
++	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
++	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
++
++
++#define RTL8192E_TRANS_LPS_TO_ACT															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM, For Repeatly In and out, Taggle bit should be changed*/\
++	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
++	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
++	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/\
++	{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*Clear ISR*/
++
++#define RTL8192E_TRANS_END															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
++
++
++	extern WLAN_PWR_CFG rtl8192E_power_on_flow[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8192E_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8192E_radio_off_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8192E_card_disable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8192E_card_enable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8192E_suspend_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8192E_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8192E_resume_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8192E_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8192E_hwpdn_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8192E_enter_lps_flow[RTL8192E_TRANS_ACT_TO_LPS_STEPS + RTL8192E_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8192E_leave_lps_flow[RTL8192E_TRANS_LPS_TO_ACT_STEPS + RTL8192E_TRANS_END_STEPS];
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192FPhyCfg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192FPhyCfg.h
+new file mode 100644
+index 000000000..dd9fdcc09
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192FPhyCfg.h
+@@ -0,0 +1,115 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8192FPHYCFG_H__
++#define __INC_HAL8192FPHYCFG_H__
++
++/*--------------------------Define Parameters-------------------------------*/
++#define LOOP_LIMIT				5
++#define MAX_STALL_TIME			50		/* us */
++#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
++#define MAX_TXPWR_IDX_NMODE_92S	63
++#define Reset_Cnt_Limit			3
++
++#ifdef CONFIG_PCI_HCI
++	#define MAX_AGGR_NUM	0x0B
++#else
++	#define MAX_AGGR_NUM	0x07
++#endif /* CONFIG_PCI_HCI */
++
++
++/*--------------------------Define Parameters End-------------------------------*/
++
++
++/*------------------------------Define structure----------------------------*/
++
++/*------------------------------Define structure End----------------------------*/
++
++/*--------------------------Exported Function prototype---------------------*/
++u32
++PHY_QueryBBReg_8192F(
++		PADAPTER	Adapter,
++		u32		RegAddr,
++		u32		BitMask
++);
++
++void
++PHY_SetBBReg_8192F(
++		PADAPTER	Adapter,
++		u32		RegAddr,
++		u32		BitMask,
++		u32		Data
++);
++
++u32
++PHY_QueryRFReg_8192F(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				RegAddr,
++		u32				BitMask
++);
++
++void
++PHY_SetRFReg_8192F(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				RegAddr,
++		u32				BitMask,
++		u32				Data
++);
++
++/* MAC/BB/RF HAL config */
++int PHY_BBConfig8192F(PADAPTER	Adapter	);
++
++int PHY_RFConfig8192F(PADAPTER	Adapter);
++
++s32 PHY_MACConfig8192F(PADAPTER padapter);
++
++int
++PHY_ConfigRFWithParaFile_8192F(
++		PADAPTER			Adapter,
++		u8				*pFileName,
++	enum rf_path				eRFPath
++);
++
++void
++PHY_SetTxPowerIndex_8192F(
++		PADAPTER			Adapter,
++		u32					PowerIndex,
++		enum rf_path			RFPath,
++		u8					Rate
++);
++
++void
++PHY_SetTxPowerLevel8192F(
++		PADAPTER		Adapter,
++		u8			channel
++);
++
++void
++PHY_SetSwChnlBWMode8192F(
++		PADAPTER			Adapter,
++		u8					channel,
++		enum channel_width	Bandwidth,
++		u8					Offset40,
++		u8					Offset80
++);
++
++void phy_set_rf_path_switch_8192f(
++		PADAPTER	pAdapter,
++		bool		bMain
++);
++/*--------------------------Exported Function prototype End---------------------*/
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192FPhyReg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192FPhyReg.h
+new file mode 100644
+index 000000000..b82f7f986
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192FPhyReg.h
+@@ -0,0 +1,1134 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8192FPHYREG_H__
++#define __INC_HAL8192FPHYREG_H__
++
++#define		rSYM_WLBT_PAPE_SEL		0x64
++/*
++ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
++ * 3. RF register 0x00-2E
++ * 4. Bit Mask for BB/RF register
++ * 5. Other definition for BB/RF R/W
++ *   */
++
++
++/*
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 1. Page1(0x100)
++ *   */
++#define		rPMAC_Reset					0x100
++#define		rPMAC_TxStart					0x104
++#define		rPMAC_TxLegacySIG				0x108
++#define		rPMAC_TxHTSIG1				0x10c
++#define		rPMAC_TxHTSIG2				0x110
++#define		rPMAC_PHYDebug				0x114
++#define		rPMAC_TxPacketNum				0x118
++#define		rPMAC_TxIdle					0x11c
++#define		rPMAC_TxMACHeader0			0x120
++#define		rPMAC_TxMACHeader1			0x124
++#define		rPMAC_TxMACHeader2			0x128
++#define		rPMAC_TxMACHeader3			0x12c
++#define		rPMAC_TxMACHeader4			0x130
++#define		rPMAC_TxMACHeader5			0x134
++#define		rPMAC_TxDataType				0x138
++#define		rPMAC_TxRandomSeed			0x13c
++#define		rPMAC_CCKPLCPPreamble			0x140
++#define		rPMAC_CCKPLCPHeader			0x144
++#define		rPMAC_CCKCRC16				0x148
++#define		rPMAC_OFDMRxCRC32OK			0x170
++#define		rPMAC_OFDMRxCRC32Er			0x174
++#define		rPMAC_OFDMRxParityEr			0x178
++#define		rPMAC_OFDMRxCRC8Er			0x17c
++#define		rPMAC_CCKCRxRC16Er			0x180
++#define		rPMAC_CCKCRxRC32Er			0x184
++#define		rPMAC_CCKCRxRC32OK			0x188
++#define		rPMAC_TxStatus					0x18c
++
++/*
++ * 2. Page2(0x200)
++ *
++ * The following two definition are only used for USB interface. */
++#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
++#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
++
++/*
++ * 3. Page8(0x800)
++ *   */
++#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC // RF BW Setting?? */
++
++#define		rFPGA0_TxInfo				0x804	/* Status report?? */
++#define		rFPGA0_PSDFunction			0x808
++
++#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
++
++#define		rFPGA0_RFTiming1			0x810	/* Useless now */
++#define		rFPGA0_RFTiming2			0x814
++
++#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
++#define		rFPGA0_XA_HSSIParameter2		0x824
++#define		rFPGA0_XB_HSSIParameter1		0x828
++#define		rFPGA0_XB_HSSIParameter2		0x82c
++#define		rTxAGC_B_Rate18_06				0x830
++#define		rTxAGC_B_Rate54_24				0x834
++#define		rTxAGC_B_CCK1_55_Mcs32		0x838
++#define		rTxAGC_B_Mcs03_Mcs00			0x83c
++
++#define		rTxAGC_B_Mcs07_Mcs04			0x848
++#define		rTxAGC_B_Mcs11_Mcs08			0x84c
++
++#define		rFPGA0_XA_LSSIParameter		0x840
++#define		rFPGA0_XB_LSSIParameter		0x844
++
++#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
++#define		rFPGA0_RFSleepUpParameter		0x854
++
++#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
++#define		rFPGA0_XCD_SwitchControl		0x85c
++
++#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
++#define		rFPGA0_XB_RFInterfaceOE		0x864
++
++#define		rTxAGC_B_Mcs15_Mcs12			0x868
++#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
++
++#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
++#define		rFPGA0_XCD_RFInterfaceSW		0x874
++
++#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
++#define		rFPGA0_XCD_RFParameter		0x87c
++
++#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
++#define		rFPGA0_AnalogParameter2		0x884
++#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
++#define		rFPGA0_AnalogParameter4		0x88c
++
++#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
++#define		rFPGA0_XB_LSSIReadBack		0x8a4
++#define		rFPGA0_XC_LSSIReadBack		0x8a8
++#define		rFPGA0_XD_LSSIReadBack		0x8ac
++
++#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
++#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
++#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
++#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now // RF Interface Readback Value */
++#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
++
++/*
++ * 4. Page9(0x900)
++ *   */
++#define	rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC // RF BW Setting?? */
++#define	rFPGA1_TxBlock				0x904	/* Useless now */
++#define	rFPGA1_DebugSelect			0x908	/* Useless now */
++#define	rFPGA1_TxInfo				0x90c	/* Useless now // Status report?? */
++#define	rDPDT_control				0x92c
++#define	rfe_ctrl_anta_src				0x930
++#define	rS0S1_PathSwitch			0x948
++#define	rBBrx_DFIR					0x954
++
++/*
++ * 5. PageA(0xA00)
++ *
++ * Set Control channel to upper or lower. These settings are required only for 40MHz */
++#define		rCCK0_System				0xa00
++
++#define		rCCK0_AFESetting			0xa04	/* Disable init gain now // Select RX path by RSSI */
++#define		rCCK0_CCA					0xa08	/* Disable init gain now // Init gain */
++
++#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
++#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
++
++#define		rCCK0_RxHP					0xa14
++
++#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
++#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
++
++#define		rCCK0_TxFilter1				0xa20
++#define		rCCK0_TxFilter2				0xa24
++#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
++#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
++#define		rCCK0_TRSSIReport		0xa50
++#define		rCCK0_RxReport			0xa54  /* 0xa57 */
++#define		rCCK0_FACounterLower		0xa5c  /* 0xa5b */
++#define		rCCK0_FACounterUpper		0xa58  /* 0xa5c */
++
++/*
++ * PageB(0xB00)
++ *   */
++#define rPdp_AntA						0xb00
++#define rPdp_AntA_4						0xb04
++#define rPdp_AntA_8						0xb08
++#define rPdp_AntA_C						0xb0c
++#define rPdp_AntA_10					0xb10
++#define rPdp_AntA_14					0xb14
++#define rPdp_AntA_18					0xb18
++#define rPdp_AntA_1C					0xb1c
++#define rPdp_AntA_20					0xb20
++#define rPdp_AntA_24					0xb24
++
++#define rConfig_Pmpd_AntA				0xb28
++#define rConfig_ram64x16				0xb2c
++
++#define rBndA							0xb30
++#define rHssiPar						0xb34
++
++#define rConfig_AntA					0xb68
++#define rConfig_AntB					0xb6c
++
++#define rPdp_AntB						0xb70
++#define rPdp_AntB_4						0xb74
++#define rPdp_AntB_8						0xb78
++#define rPdp_AntB_C						0xb7c
++#define rPdp_AntB_10					0xb80
++#define rPdp_AntB_14					0xb84
++#define rPdp_AntB_18					0xb88
++#define rPdp_AntB_1C					0xb8c
++#define rPdp_AntB_20					0xb90
++#define rPdp_AntB_24					0xb94
++
++#define rConfig_Pmpd_AntB				0xb98
++
++#define rBndB							0xba0
++
++#define rAPK							0xbd8
++#define rPm_Rx0_AntA					0xbdc
++#define rPm_Rx1_AntA					0xbe0
++#define rPm_Rx2_AntA					0xbe4
++#define rPm_Rx3_AntA					0xbe8
++#define rPm_Rx0_AntB					0xbec
++#define rPm_Rx1_AntB					0xbf0
++#define rPm_Rx2_AntB					0xbf4
++#define rPm_Rx3_AntB					0xbf8
++/*
++ * 6. PageC(0xC00)
++ *   */
++#define		rOFDM0_LSTF				0xc00
++
++#define		rOFDM0_TRxPathEnable		0xc04
++#define		rOFDM0_TRMuxPar			0xc08
++#define		rOFDM0_TRSWIsolation		0xc0c
++
++#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
++#define		rOFDM0_XARxIQImbalance		0xc14  /* RxIQ imbalance matrix */
++#define		rOFDM0_XBRxAFE		0xc18
++#define		rOFDM0_XBRxIQImbalance	0xc1c
++#define		rOFDM0_XCRxAFE		0xc20
++#define		rOFDM0_XCRxIQImbalance	0xc24
++#define		rOFDM0_XDRxAFE		0xc28
++#define		rOFDM0_XDRxIQImbalance	0xc2c
++
++#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	// DM tune init gain */
++#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
++#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
++#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
++
++#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
++#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
++#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
++#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
++
++#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
++#define		rOFDM0_XAAGCCore2			0xc54
++#define		rOFDM0_XBAGCCore1			0xc58
++#define		rOFDM0_XBAGCCore2			0xc5c
++#define		rOFDM0_XCAGCCore1			0xc60
++#define		rOFDM0_XCAGCCore2			0xc64
++#define		rOFDM0_XDAGCCore1			0xc68
++#define		rOFDM0_XDAGCCore2			0xc6c
++
++#define		rOFDM0_AGCParameter1			0xc70
++#define		rOFDM0_AGCParameter2			0xc74
++#define		rOFDM0_AGCRSSITable			0xc78
++#define		rOFDM0_HTSTFAGC				0xc7c
++
++#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
++#define		rOFDM0_XATxAFE				0xc84
++#define		rOFDM0_XBTxIQImbalance		0xc88
++#define		rOFDM0_XBTxAFE				0xc8c
++#define		rOFDM0_XCTxIQImbalance		0xc90
++#define		rOFDM0_XCTxAFE			0xc94
++#define		rOFDM0_XDTxIQImbalance		0xc98
++#define		rOFDM0_XDTxAFE				0xc9c
++
++#define		rOFDM0_RxIQExtAnta			0xca0
++#define		rOFDM0_TxCoeff1				0xca4
++#define		rOFDM0_TxCoeff2				0xca8
++#define		rOFDM0_TxCoeff3				0xcac
++#define		rOFDM0_TxCoeff4				0xcb0
++#define		rOFDM0_TxCoeff5				0xcb4
++#define		rOFDM0_TxCoeff6				0xcb8
++#define		rOFDM0_RxHPParameter			0xce0
++#define		rOFDM0_TxPseudoNoiseWgt		0xce4
++#define		rOFDM0_FrameSync				0xcf0
++#define		rOFDM0_DFSReport				0xcf4
++
++/*
++ * 7. PageD(0xD00)
++ *   */
++#define		rOFDM1_LSTF					0xd00
++#define		rOFDM1_TRxPathEnable			0xd04
++
++#define		rOFDM1_CFO						0xd08	/* No setting now */
++#define		rOFDM1_CSI1					0xd10
++#define		rOFDM1_SBD						0xd14
++#define		rOFDM1_CSI2					0xd18
++#define		rOFDM1_CFOTracking			0xd2c
++#define		rOFDM1_TRxMesaure1			0xd34
++#define		rOFDM1_IntfDet					0xd3c
++#define		rOFDM1_PseudoNoiseStateAB		0xd50
++#define		rOFDM1_PseudoNoiseStateCD		0xd54
++#define		rOFDM1_RxPseudoNoiseWgt		0xd58
++
++#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
++#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
++#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
++
++#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
++#define		rOFDM_ShortCFOCD				0xdb0
++#define		rOFDM_LongCFOAB				0xdb4
++#define		rOFDM_LongCFOCD				0xdb8
++#define		rOFDM_TailCFOAB				0xdbc
++#define		rOFDM_TailCFOCD				0xdc0
++#define		rOFDM_PWMeasure1		0xdc4
++#define		rOFDM_PWMeasure2		0xdc8
++#define		rOFDM_BWReport				0xdcc
++#define		rOFDM_AGCReport				0xdd0
++#define		rOFDM_RxSNR					0xdd4
++#define		rOFDM_RxEVMCSI				0xdd8
++#define		rOFDM_SIGReport				0xddc
++
++
++/*
++ * 8. PageE(0xE00)
++ *   */
++#define		rTxAGC_A_Rate18_06			0xe00
++#define		rTxAGC_A_Rate54_24			0xe04
++#define		rTxAGC_A_CCK1_Mcs32			0xe08
++#define		rTxAGC_A_Mcs03_Mcs00			0xe10
++#define		rTxAGC_A_Mcs07_Mcs04			0xe14
++#define		rTxAGC_A_Mcs11_Mcs08			0xe18
++#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
++
++#define		rFPGA0_IQK					0xe28
++#define		rTx_IQK_Tone_A				0xe30
++#define		rRx_IQK_Tone_A				0xe34
++#define		rTx_IQK_PI_A					0xe38
++#define		rRx_IQK_PI_A					0xe3c
++
++#define		rTx_IQK						0xe40
++#define		rRx_IQK						0xe44
++#define		rIQK_AGC_Pts					0xe48
++#define		rIQK_AGC_Rsp					0xe4c
++#define		rTx_IQK_Tone_B				0xe50
++#define		rRx_IQK_Tone_B				0xe54
++#define		rTx_IQK_PI_B					0xe58
++#define		rRx_IQK_PI_B					0xe5c
++#define		rIQK_AGC_Cont				0xe60
++
++#define		rBlue_Tooth					0xe6c
++#define		rRx_Wait_CCA					0xe70
++#define		rTx_CCK_RFON					0xe74
++#define		rTx_CCK_BBON				0xe78
++#define		rTx_OFDM_RFON				0xe7c
++#define		rTx_OFDM_BBON				0xe80
++#define		rTx_To_Rx					0xe84
++#define		rTx_To_Tx					0xe88
++#define		rRx_CCK						0xe8c
++
++#define		rTx_Power_Before_IQK_A		0xe94
++#define		rTx_Power_After_IQK_A			0xe9c
++
++#define		rRx_Power_Before_IQK_A		0xea0
++#define		rRx_Power_Before_IQK_A_2		0xea4
++#define		rRx_Power_After_IQK_A			0xea8
++#define		rRx_Power_After_IQK_A_2		0xeac
++
++#define		rTx_Power_Before_IQK_B		0xeb4
++#define		rTx_Power_After_IQK_B			0xebc
++
++#define		rRx_Power_Before_IQK_B		0xec0
++#define		rRx_Power_Before_IQK_B_2		0xec4
++#define		rRx_Power_After_IQK_B			0xec8
++#define		rRx_Power_After_IQK_B_2		0xecc
++
++#define		rRx_OFDM					0xed0
++#define		rRx_Wait_RIFS				0xed4
++#define		rRx_TO_Rx					0xed8
++#define		rStandby						0xedc
++#define		rSleep						0xee0
++#define		rPMPD_ANAEN				0xeec
++
++/*
++ * 7. RF Register 0x00-0x2E (RF 8256)
++ * RF-0222D 0x00-3F
++ *
++ * Zebra1 */
++#define		rZebra1_HSSIEnable				0x0	/* Useless now */
++#define		rZebra1_TRxEnable1				0x1
++#define		rZebra1_TRxEnable2				0x2
++#define		rZebra1_AGC					0x4
++#define		rZebra1_ChargePump			0x5
++#define		rZebra1_Channel				0x7	/* RF channel switch */
++
++/* #endif */
++#define		rZebra1_TxGain					0x8	/* Useless now */
++#define		rZebra1_TxLPF					0x9
++#define		rZebra1_RxLPF					0xb
++#define		rZebra1_RxHPFCorner			0xc
++
++/* Zebra4 */
++#define		rGlobalCtrl						0	/* Useless now */
++#define		rRTL8256_TxLPF					19
++#define		rRTL8256_RxLPF					11
++
++/* RTL8258 */
++#define		rRTL8258_TxLPF					0x11	/* Useless now */
++#define		rRTL8258_RxLPF					0x13
++#define		rRTL8258_RSSILPF				0xa
++
++/*
++ * RL6052 Register definition
++ *   */
++#define		RF_AC						0x00	/* */
++
++#define		RF_IQADJ_G1				0x01	/* */
++#define		RF_IQADJ_G2				0x02	/* */
++#define		RF_BS_PA_APSET_G1_G4		0x03
++#define		RF_BS_PA_APSET_G5_G8		0x04
++#define		RF_POW_TRSW				0x05	/* */
++
++#define		RF_GAIN_RX					0x06	/* */
++#define		RF_GAIN_TX					0x07	/* */
++
++#define		RF_TXM_IDAC				0x08	/* */
++#define		RF_IPA_G					0x09	/* */
++#define		RF_TXBIAS_G				0x0A
++#define		RF_TXPA_AG					0x0B
++#define		RF_IPA_A					0x0C	/* */
++#define		RF_TXBIAS_A				0x0D
++#define		RF_BS_PA_APSET_G9_G11	0x0E
++#define		RF_BS_IQGEN				0x0F	/* */
++
++#define		RF_MODE1					0x10	/* */
++#define		RF_MODE2					0x11	/* */
++
++#define		RF_RX_AGC_HP				0x12	/* */
++#define		RF_TX_AGC					0x13	/* */
++#define		RF_BIAS						0x14	/* */
++#define		RF_IPA						0x15	/* */
++#define		RF_TXBIAS					0x16
++#define		RF_POW_ABILITY			0x17	/* */
++#define		RF_MODE_AG				0x18	/* */
++#define		rRfChannel					0x18	/* RF channel and BW switch */
++#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
++#define		RF_TOP						0x19	/* */
++
++#define		RF_RX_G1					0x1A	/* */
++#define		RF_RX_G2					0x1B	/* */
++
++#define		RF_RX_BB2					0x1C	/* */
++#define		RF_RX_BB1					0x1D	/* */
++
++#define		RF_RCK1					0x1E	/* */
++#define		RF_RCK2					0x1F	/* */
++
++#define		RF_TX_G1					0x20	/* */
++#define		RF_TX_G2					0x21	/* */
++#define		RF_TX_G3					0x22	/* */
++
++#define		RF_TX_BB1					0x23	/* */
++
++#define		RF_T_METER					0x24	/* */
++
++#define		RF_SYN_G1					0x25	/* RF TX Power control */
++#define		RF_SYN_G2					0x26	/* RF TX Power control */
++#define		RF_SYN_G3					0x27	/* RF TX Power control */
++#define		RF_SYN_G4					0x28	/* RF TX Power control */
++#define		RF_SYN_G5					0x29	/* RF TX Power control */
++#define		RF_SYN_G6					0x2A	/* RF TX Power control */
++#define		RF_SYN_G7					0x2B	/* RF TX Power control */
++#define		RF_SYN_G8					0x2C	/* RF TX Power control */
++
++#define		RF_RCK_OS					0x30	/* RF TX PA control */
++
++#define		RF_TXPA_G1					0x31	/* RF TX PA control */
++#define		RF_TXPA_G2					0x32	/* RF TX PA control */
++#define		RF_TXPA_G3					0x33	/* RF TX PA control */
++#define	RF_TX_BIAS_A				0x35
++#define	RF_TX_BIAS_D				0x36
++#define	RF_LOBF_9					0x38
++#define	RF_RXRF_A3					0x3C	/*	 */
++#define	RF_TRSW					0x3F
++
++#define	RF_TXRF_A2					0x41
++#define	RF_T_METER_88E				0x42
++#define	RF_TXPA_G4					0x46
++#define	RF_TXPA_A4					0x4B
++#define	RF_0x52					0x52
++#define	RF_WE_LUT					0xEF
++#define	RF_S0S1					0xB0
++
++/*
++ * Bit Mask
++ *
++ * 1. Page1(0x100) */
++#define		bBBResetB						0x100	/* Useless now? */
++#define		bGlobalResetB					0x200
++#define		bOFDMTxStart					0x4
++#define		bCCKTxStart						0x8
++#define		bCRC32Debug					0x100
++#define		bPMACLoopback					0x10
++#define		bTxLSIG							0xffffff
++#define		bOFDMTxRate					0xf
++#define		bOFDMTxReserved				0x10
++#define		bOFDMTxLength					0x1ffe0
++#define		bOFDMTxParity					0x20000
++#define		bTxHTSIG1						0xffffff
++#define		bTxHTMCSRate					0x7f
++#define		bTxHTBW						0x80
++#define		bTxHTLength					0xffff00
++#define		bTxHTSIG2						0xffffff
++#define		bTxHTSmoothing					0x1
++#define		bTxHTSounding					0x2
++#define		bTxHTReserved					0x4
++#define		bTxHTAggreation				0x8
++#define		bTxHTSTBC						0x30
++#define		bTxHTAdvanceCoding			0x40
++#define		bTxHTShortGI					0x80
++#define		bTxHTNumberHT_LTF			0x300
++#define		bTxHTCRC8						0x3fc00
++#define		bCounterReset					0x10000
++#define		bNumOfOFDMTx					0xffff
++#define		bNumOfCCKTx					0xffff0000
++#define		bTxIdleInterval					0xffff
++#define		bOFDMService					0xffff0000
++#define		bTxMACHeader					0xffffffff
++#define		bTxDataInit						0xff
++#define		bTxHTMode						0x100
++#define		bTxDataType					0x30000
++#define		bTxRandomSeed					0xffffffff
++#define		bCCKTxPreamble					0x1
++#define		bCCKTxSFD						0xffff0000
++#define		bCCKTxSIG						0xff
++#define		bCCKTxService					0xff00
++#define		bCCKLengthExt					0x8000
++#define		bCCKTxLength					0xffff0000
++#define		bCCKTxCRC16					0xffff
++#define		bCCKTxStatus					0x1
++#define		bOFDMTxStatus					0x2
++
++#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
++#define		RF_TX_GAIN_OFFSET_8192F(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0))
++
++/* 2. Page8(0x800) */
++#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
++#define		bJapanMode						0x2
++#define		bCCKTxSC						0x30
++#define		bCCKEn							0x1000000
++#define		bOFDMEn						0x2000000
++
++#define		bOFDMRxADCPhase           0x10000	/* Useless now */
++#define		bOFDMTxDACPhase		0x40000
++#define		bXATxAGC			0x3f
++
++#define		bAntennaSelect		0x0300
++
++#define		bXBTxAGC                 0xf00	/* Reg 80c rFPGA0_TxGainStage */
++#define		bXCTxAGC			0xf000
++#define		bXDTxAGC			0xf0000
++
++#define		bPAStart                 0xf0000000	/* Useless now */
++#define		bTRStart			0x00f00000
++#define		bRFStart			0x0000f000
++#define		bBBStart			0x000000f0
++#define		bBBCCKStart		0x0000000f
++#define		bPAEnd                    0xf          /* Reg0x814 */
++#define		bTREnd			0x0f000000
++#define		bRFEnd			0x000f0000
++#define		bCCAMask                  0x000000f0   /* T2R */
++#define		bR2RCCAMask		0x00000f00
++#define		bHSSI_R2TDelay		0xf8000000
++#define		bHSSI_T2RDelay		0xf80000
++#define		bContTxHSSI              0x400     /* chane gain at continue Tx */
++#define		bIGFromCCK		0x200
++#define		bAGCAddress		0x3f
++#define		bRxHPTx			0x7000
++#define		bRxHPT2R			0x38000
++#define		bRxHPCCKIni		0xc0000
++#define		bAGCTxCode		0xc00000
++#define		bAGCRxCode		0x300000
++
++#define		b3WireDataLength         0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
++#define		b3WireAddressLength		0x400
++
++#define		b3WireRFPowerDown         0x1	/* Useless now
++ * #define bHWSISelect		0x8 */
++#define		b5GPAPEPolarity		0x40000000
++#define		b2GPAPEPolarity		0x80000000
++#define		bRFSW_TxDefaultAnt		0x3
++#define		bRFSW_TxOptionAnt		0x30
++#define		bRFSW_RxDefaultAnt		0x300
++#define		bRFSW_RxOptionAnt		0x3000
++#define		bRFSI_3WireData		0x1
++#define		bRFSI_3WireClock		0x2
++#define		bRFSI_3WireLoad		0x4
++#define		bRFSI_3WireRW		0x8
++#define		bRFSI_3Wire			0xf
++
++#define		bRFSI_RFENV              0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
++
++#define		bRFSI_TRSW               0x20	/* Useless now */
++#define		bRFSI_TRSWB		0x40
++#define		bRFSI_ANTSW		0x100
++#define		bRFSI_ANTSWB		0x200
++#define		bRFSI_PAPE			0x400
++#define		bRFSI_PAPE5G		0x800
++#define		bBandSelect			0x1
++#define		bHTSIG2_GI			0x80
++#define		bHTSIG2_Smoothing		0x01
++#define		bHTSIG2_Sounding		0x02
++#define		bHTSIG2_Aggreaton		0x08
++#define		bHTSIG2_STBC		0x30
++#define		bHTSIG2_AdvCoding		0x40
++#define		bHTSIG2_NumOfHTLTF	0x300
++#define		bHTSIG2_CRC8		0x3fc
++#define		bHTSIG1_MCS		0x7f
++#define		bHTSIG1_BandWidth		0x80
++#define		bHTSIG1_HTLength		0xffff
++#define		bLSIG_Rate			0xf
++#define		bLSIG_Reserved		0x10
++#define		bLSIG_Length		0x1fffe
++#define		bLSIG_Parity			0x20
++#define		bCCKRxPhase		0x4
++
++#define		bLSSIReadAddress          0x7f800000   /* T65 RF */
++
++#define		bLSSIReadEdge             0x80000000   /* LSSI "Read" edge signal */
++
++#define		bLSSIReadBackData         0xfffff		/* T65 RF */
++
++#define		bLSSIReadOKFlag           0x1000	/* Useless now */
++#define		bCCKSampleRate            0x8       /* 0: 44MHz, 1:88MHz     */
++#define		bRegulator0Standby		0x1
++#define		bRegulatorPLLStandby		0x2
++#define		bRegulator1Standby		0x4
++#define		bPLLPowerUp		0x8
++#define		bDPLLPowerUp		0x10
++#define		bDA10PowerUp		0x20
++#define		bAD7PowerUp		0x200
++#define		bDA6PowerUp		0x2000
++#define		bXtalPowerUp		0x4000
++#define		b40MDClkPowerUP		0x8000
++#define		bDA6DebugMode		0x20000
++#define		bDA6Swing			0x380000
++
++#define		bADClkPhase               0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
++
++#define		b80MClkDelay              0x18000000	/* Useless */
++#define		bAFEWatchDogEnable		0x20000000
++
++#define		bXtalCap01                0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
++#define		bXtalCap23			0x3
++#define		bXtalCap92x					0x0f000000
++#define		bXtalCap			0x0f000000
++
++#define		bIntDifClkEnable          0x400	/* Useless */
++#define		bExtSigClkEnable		0x800
++#define		bBandgapMbiasPowerUp	0x10000
++#define		bAD11SHGain		0xc0000
++#define		bAD11InputRange		0x700000
++#define		bAD11OPCurrent		0x3800000
++#define		bIPathLoopback		0x4000000
++#define		bQPathLoopback		0x8000000
++#define		bAFELoopback		0x10000000
++#define		bDA10Swing		0x7e0
++#define		bDA10Reverse		0x800
++#define		bDAClkSource		0x1000
++#define		bAD7InputRange		0x6000
++#define		bAD7Gain			0x38000
++#define		bAD7OutputCMMode		0x40000
++#define		bAD7InputCMMode		0x380000
++#define		bAD7Current			0xc00000
++#define		bRegulatorAdjust		0x7000000
++#define		bAD11PowerUpAtTx		0x1
++#define		bDA10PSAtTx		0x10
++#define		bAD11PowerUpAtRx		0x100
++#define		bDA10PSAtRx		0x1000
++#define		bCCKRxAGCFormat		0x200
++#define		bPSDFFTSamplepPoint		0xc000
++#define		bPSDAverageNum		0x3000
++#define		bIQPathControl		0xc00
++#define		bPSDFreq			0x3ff
++#define		bPSDAntennaPath		0x30
++#define		bPSDIQSwitch		0x40
++#define		bPSDRxTrigger		0x400000
++#define		bPSDTxTrigger		0x80000000
++#define		bPSDSineToneScale		0x7f000000
++#define		bPSDReport			0xffff
++
++/* 3. Page9(0x900) */
++#define		bOFDMTxSC                 0x30000000	/* Useless */
++#define		bCCKTxOn			0x1
++#define		bOFDMTxOn		0x2
++#define		bDebugPage                0xfff  /* reset debug page and also HWord, LWord */
++#define		bDebugItem                0xff   /* reset debug page and LWord */
++#define		bAntL			0x10
++#define		bAntNonHT				0x100
++#define		bAntHT1			0x1000
++#define		bAntHT2			0x10000
++#define		bAntHT1S1			0x100000
++#define		bAntNonHTS1		0x1000000
++
++/* 4. PageA(0xA00) */
++#define		bCCKBBMode				0x3	/* Useless */
++#define		bCCKTxPowerSaving		0x80
++#define		bCCKRxPowerSaving		0x40
++
++#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
++
++#define		bCCKScramble			0x8	/* Useless */
++#define		bCCKAntDiversity		0x8000
++#define		bCCKCarrierRecovery		0x4000
++#define		bCCKTxRate				0x3000
++#define		bCCKDCCancel			0x0800
++#define		bCCKISICancel			0x0400
++#define		bCCKMatchFilter			0x0200
++#define		bCCKEqualizer			0x0100
++#define		bCCKPreambleDetect		0x800000
++#define		bCCKFastFalseCCA		0x400000
++#define		bCCKChEstStart			0x300000
++#define		bCCKCCACount			0x080000
++#define		bCCKcs_lim				0x070000
++#define		bCCKBistMode			0x80000000
++#define		bCCKCCAMask			0x40000000
++#define		bCCKTxDACPhase		0x4
++#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
++#define		bCCKr_cp_mode0		0x0100
++#define		bCCKTxDCOffset			0xf0
++#define		bCCKRxDCOffset			0xf
++#define		bCCKCCAMode			0xc000
++#define		bCCKFalseCS_lim			0x3f00
++#define		bCCKCS_ratio			0xc00000
++#define		bCCKCorgBit_sel			0x300000
++#define		bCCKPD_lim				0x0f0000
++#define		bCCKNewCCA			0x80000000
++#define		bCCKRxHPofIG			0x8000
++#define		bCCKRxIG				0x7f00
++#define		bCCKLNAPolarity			0x800000
++#define		bCCKRx1stGain			0x7f0000
++#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
++#define		bCCKRxAGCSatLevel		0x1f000000
++#define		bCCKRxAGCSatCount		0xe0
++#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
++#define		bCCKFixedRxAGC			0x8000
++/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
++#define		bCCKAntennaPolarity		0x2000
++#define		bCCKTxFilterType		0x0c00
++#define		bCCKRxAGCReportType	0x0300
++#define		bCCKRxDAGCEn			0x80000000
++#define		bCCKRxDAGCPeriod		0x20000000
++#define		bCCKRxDAGCSatLevel		0x1f000000
++#define		bCCKTimingRecovery		0x800000
++#define		bCCKTxC0				0x3f0000
++#define		bCCKTxC1				0x3f000000
++#define		bCCKTxC2				0x3f
++#define		bCCKTxC3				0x3f00
++#define		bCCKTxC4				0x3f0000
++#define		bCCKTxC5				0x3f000000
++#define		bCCKTxC6				0x3f
++#define		bCCKTxC7				0x3f00
++#define		bCCKDebugPort			0xff0000
++#define		bCCKDACDebug			0x0f000000
++#define		bCCKFalseAlarmEnable	0x8000
++#define		bCCKFalseAlarmRead		0x4000
++#define		bCCKTRSSI				0x7f
++#define		bCCKRxAGCReport		0xfe
++#define		bCCKRxReport_AntSel	0x80000000
++#define		bCCKRxReport_MFOff		0x40000000
++#define		bCCKRxRxReport_SQLoss	0x20000000
++#define		bCCKRxReport_Pktloss	0x10000000
++#define		bCCKRxReport_Lockedbit	0x08000000
++#define		bCCKRxReport_RateError	0x04000000
++#define		bCCKRxReport_RxRate	0x03000000
++#define		bCCKRxFACounterLower	0xff
++#define		bCCKRxFACounterUpper	0xff000000
++#define		bCCKRxHPAGCStart		0xe000
++#define		bCCKRxHPAGCFinal		0x1c00
++#define		bCCKRxFalseAlarmEnable	0x8000
++#define		bCCKFACounterFreeze	0x4000
++#define		bCCKTxPathSel			0x10000000
++#define		bCCKDefaultRxPath		0xc000000
++#define		bCCKOptionRxPath		0x3000000
++
++/* 5. PageC(0xC00) */
++#define		bNumOfSTF				0x3	/* Useless */
++#define		bShift_L					0xc0
++#define		bGI_TH					0xc
++#define		bRxPathA				0x1
++#define		bRxPathB				0x2
++#define		bRxPathC				0x4
++#define		bRxPathD				0x8
++#define		bTxPathA				0x1
++#define		bTxPathB				0x2
++#define		bTxPathC				0x4
++#define		bTxPathD				0x8
++#define		bTRSSIFreq				0x200
++#define		bADCBackoff				0x3000
++#define		bDFIRBackoff			0xc000
++#define		bTRSSILatchPhase		0x10000
++#define		bRxIDCOffset			0xff
++#define		bRxQDCOffset			0xff00
++#define		bRxDFIRMode			0x1800000
++#define		bRxDCNFType			0xe000000
++#define		bRXIQImb_A				0x3ff
++#define		bRXIQImb_B				0xfc00
++#define		bRXIQImb_C				0x3f0000
++#define		bRXIQImb_D				0xffc00000
++#define		bDC_dc_Notch			0x60000
++#define		bRxNBINotch			0x1f000000
++#define		bPD_TH					0xf
++#define		bPD_TH_Opt2			0xc000
++#define		bPWED_TH				0x700
++#define		bIfMF_Win_L			0x800
++#define		bPD_Option				0x1000
++#define		bMF_Win_L				0xe000
++#define		bBW_Search_L			0x30000
++#define		bwin_enh_L				0xc0000
++#define		bBW_TH					0x700000
++#define		bED_TH2				0x3800000
++#define		bBW_option				0x4000000
++#define		bRatio_TH				0x18000000
++#define		bWindow_L				0xe0000000
++#define		bSBD_Option				0x1
++#define		bFrame_TH				0x1c
++#define		bFS_Option				0x60
++#define		bDC_Slope_check		0x80
++#define		bFGuard_Counter_DC_L	0xe00
++#define		bFrame_Weight_Short	0x7000
++#define		bSub_Tune				0xe00000
++#define		bFrame_DC_Length		0xe000000
++#define		bSBD_start_offset		0x30000000
++#define		bFrame_TH_2			0x7
++#define		bFrame_GI2_TH			0x38
++#define		bGI2_Sync_en			0x40
++#define		bSarch_Short_Early		0x300
++#define		bSarch_Short_Late		0xc00
++#define		bSarch_GI2_Late		0x70000
++#define		bCFOAntSum				0x1
++#define		bCFOAcc				0x2
++#define		bCFOStartOffset			0xc
++#define		bCFOLookBack			0x70
++#define		bCFOSumWeight			0x80
++#define		bDAGCEnable			0x10000
++#define		bTXIQImb_A				0x3ff
++#define		bTXIQImb_B				0xfc00
++#define		bTXIQImb_C				0x3f0000
++#define		bTXIQImb_D				0xffc00000
++#define		bTxIDCOffset			0xff
++#define		bTxQDCOffset			0xff00
++#define		bTxDFIRMode			0x10000
++#define		bTxPesudoNoiseOn		0x4000000
++#define		bTxPesudoNoise_A		0xff
++#define		bTxPesudoNoise_B		0xff00
++#define		bTxPesudoNoise_C		0xff0000
++#define		bTxPesudoNoise_D		0xff000000
++#define		bCCADropOption			0x20000
++#define		bCCADropThres			0xfff00000
++#define		bEDCCA_H				0xf
++#define		bEDCCA_L				0xf0
++#define		bLambda_ED			0x300
++#define		bRxInitialGain			0x7f
++#define		bRxAntDivEn				0x80
++#define		bRxAGCAddressForLNA	0x7f00
++#define		bRxHighPowerFlow		0x8000
++#define		bRxAGCFreezeThres		0xc0000
++#define		bRxFreezeStep_AGC1	0x300000
++#define		bRxFreezeStep_AGC2	0xc00000
++#define		bRxFreezeStep_AGC3	0x3000000
++#define		bRxFreezeStep_AGC0	0xc000000
++#define		bRxRssi_Cmp_En			0x10000000
++#define		bRxQuickAGCEn			0x20000000
++#define		bRxAGCFreezeThresMode	0x40000000
++#define		bRxOverFlowCheckType	0x80000000
++#define		bRxAGCShift				0x7f
++#define		bTRSW_Tri_Only			0x80
++#define		bPowerThres			0x300
++#define		bRxAGCEn				0x1
++#define		bRxAGCTogetherEn		0x2
++#define		bRxAGCMin				0x4
++#define		bRxHP_Ini				0x7
++#define		bRxHP_TRLNA			0x70
++#define		bRxHP_RSSI				0x700
++#define		bRxHP_BBP1				0x7000
++#define		bRxHP_BBP2				0x70000
++#define		bRxHP_BBP3				0x700000
++#define		bRSSI_H					0x7f0000     /* the threshold for high power */
++#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
++#define		bRxSettle_TRSW			0x7
++#define		bRxSettle_LNA			0x38
++#define		bRxSettle_RSSI			0x1c0
++#define		bRxSettle_BBP			0xe00
++#define		bRxSettle_RxHP			0x7000
++#define		bRxSettle_AntSW_RSSI	0x38000
++#define		bRxSettle_AntSW		0xc0000
++#define		bRxProcessTime_DAGC	0x300000
++#define		bRxSettle_HSSI			0x400000
++#define		bRxProcessTime_BBPPW	0x800000
++#define		bRxAntennaPowerShift	0x3000000
++#define		bRSSITableSelect		0xc000000
++#define		bRxHP_Final				0x7000000
++#define		bRxHTSettle_BBP			0x7
++#define		bRxHTSettle_HSSI		0x8
++#define		bRxHTSettle_RxHP		0x70
++#define		bRxHTSettle_BBPPW		0x80
++#define		bRxHTSettle_Idle		0x300
++#define		bRxHTSettle_Reserved	0x1c00
++#define		bRxHTRxHPEn			0x8000
++#define		bRxHTAGCFreezeThres	0x30000
++#define		bRxHTAGCTogetherEn	0x40000
++#define		bRxHTAGCMin			0x80000
++#define		bRxHTAGCEn				0x100000
++#define		bRxHTDAGCEn			0x200000
++#define		bRxHTRxHP_BBP			0x1c00000
++#define		bRxHTRxHP_Final		0xe0000000
++#define		bRxPWRatioTH			0x3
++#define		bRxPWRatioEn			0x4
++#define		bRxMFHold				0x3800
++#define		bRxPD_Delay_TH1		0x38
++#define		bRxPD_Delay_TH2		0x1c0
++#define		bRxPD_DC_COUNT_MAX	0x600
++/* #define bRxMF_Hold               0x3800 */
++#define		bRxPD_Delay_TH			0x8000
++#define		bRxProcess_Delay		0xf0000
++#define		bRxSearchrange_GI2_Early	0x700000
++#define		bRxFrame_Guard_Counter_L	0x3800000
++#define		bRxSGI_Guard_L			0xc000000
++#define		bRxSGI_Search_L		0x30000000
++#define		bRxSGI_TH				0xc0000000
++#define		bDFSCnt0				0xff
++#define		bDFSCnt1				0xff00
++#define		bDFSFlag				0xf0000
++#define		bMFWeightSum			0x300000
++#define		bMinIdxTH				0x7f000000
++#define		bDAFormat				0x40000
++#define		bTxChEmuEnable		0x01000000
++#define		bTRSWIsolation_A		0x7f
++#define		bTRSWIsolation_B		0x7f00
++#define		bTRSWIsolation_C		0x7f0000
++#define		bTRSWIsolation_D		0x7f000000
++#define		bExtLNAGain				0x7c00
++
++/* 6. PageE(0xE00) */
++#define		bSTBCEn				0x4	/* Useless */
++#define		bAntennaMapping		0x10
++#define		bNss					0x20
++#define		bCFOAntSumD			0x200
++#define		bPHYCounterReset		0x8000000
++#define		bCFOReportGet			0x4000000
++#define		bOFDMContinueTx		0x10000000
++#define		bOFDMSingleCarrier		0x20000000
++#define		bOFDMSingleTone		0x40000000
++/* #define bRxPath1                 0x01 */
++/* #define bRxPath2                 0x02 */
++/* #define bRxPath3                 0x04 */
++/* #define bRxPath4                 0x08 */
++/* #define bTxPath1                 0x10 */
++/* #define bTxPath2                 0x20 */
++#define		bHTDetect			0x100
++#define		bCFOEn				0x10000
++#define		bCFOValue			0xfff00000
++#define		bSigTone_Re		0x3f
++#define		bSigTone_Im		0x7f00
++#define		bCounter_CCA		0xffff
++#define		bCounter_ParityFail	0xffff0000
++#define		bCounter_RateIllegal		0xffff
++#define		bCounter_CRC8Fail	0xffff0000
++#define		bCounter_MCSNoSupport	0xffff
++#define		bCounter_FastSync	0xffff
++#define		bShortCFO			0xfff
++#define		bShortCFOTLength	12   /* total */
++#define		bShortCFOFLength	11   /* fraction */
++#define		bLongCFO			0x7ff
++#define		bLongCFOTLength	11
++#define		bLongCFOFLength	11
++#define		bTailCFO			0x1fff
++#define		bTailCFOTLength		13
++#define		bTailCFOFLength		12
++#define		bmax_en_pwdB		0xffff
++#define		bCC_power_dB		0xffff0000
++#define		bnoise_pwdB		0xffff
++#define		bPowerMeasTLength	10
++#define		bPowerMeasFLength	3
++#define		bRx_HT_BW			0x1
++#define		bRxSC				0x6
++#define		bRx_HT				0x8
++#define		bNB_intf_det_on		0x1
++#define		bIntf_win_len_cfg	0x30
++#define		bNB_Intf_TH_cfg		0x1c0
++#define		bRFGain				0x3f
++#define		bTableSel			0x40
++#define		bTRSW				0x80
++#define		bRxSNR_A			0xff
++#define		bRxSNR_B			0xff00
++#define		bRxSNR_C			0xff0000
++#define		bRxSNR_D			0xff000000
++#define		bSNREVMTLength		8
++#define		bSNREVMFLength		1
++#define		bCSI1st				0xff
++#define		bCSI2nd				0xff00
++#define		bRxEVM1st			0xff0000
++#define		bRxEVM2nd			0xff000000
++#define		bSIGEVM			0xff
++#define		bPWDB				0xff00
++#define		bSGIEN				0x10000
++
++#define		bSFactorQAM1		0xf	/* Useless */
++#define		bSFactorQAM2		0xf0
++#define		bSFactorQAM3		0xf00
++#define		bSFactorQAM4		0xf000
++#define		bSFactorQAM5		0xf0000
++#define		bSFactorQAM6		0xf0000
++#define		bSFactorQAM7		0xf00000
++#define		bSFactorQAM8		0xf000000
++#define		bSFactorQAM9		0xf0000000
++#define		bCSIScheme			0x100000
++
++#define		bNoiseLvlTopSet		0x3	/* Useless */
++#define		bChSmooth			0x4
++#define		bChSmoothCfg1		0x38
++#define		bChSmoothCfg2		0x1c0
++#define		bChSmoothCfg3		0xe00
++#define		bChSmoothCfg4		0x7000
++#define		bMRCMode			0x800000
++#define		bTHEVMCfg			0x7000000
++
++#define		bLoopFitType		0x1	/* Useless */
++#define		bUpdCFO			0x40
++#define		bUpdCFOOffData		0x80
++#define		bAdvUpdCFO			0x100
++#define		bAdvTimeCtrl		0x800
++#define		bUpdClko			0x1000
++#define		bFC					0x6000
++#define		bTrackingMode		0x8000
++#define		bPhCmpEnable		0x10000
++#define		bUpdClkoLTF		0x20000
++#define		bComChCFO			0x40000
++#define		bCSIEstiMode		0x80000
++#define		bAdvUpdEqz			0x100000
++#define		bUChCfg				0x7000000
++#define		bUpdEqz			0x8000000
++
++/* Rx Pseduo noise */
++#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
++#define		bRxPesudoNoise_A		0xff
++#define		bRxPesudoNoise_B		0xff00
++#define		bRxPesudoNoise_C		0xff0000
++#define		bRxPesudoNoise_D		0xff000000
++#define		bPesudoNoiseState_A	0xffff
++#define		bPesudoNoiseState_B	0xffff0000
++#define		bPesudoNoiseState_C	0xffff
++#define		bPesudoNoiseState_D	0xffff0000
++
++/* 7. RF Register
++ * Zebra1 */
++#define		bZebra1_HSSIEnable		0x8		/* Useless */
++#define		bZebra1_TRxControl		0xc00
++#define		bZebra1_TRxGainSetting	0x07f
++#define		bZebra1_RxCorner		0xc00
++#define		bZebra1_TxChargePump	0x38
++#define		bZebra1_RxChargePump	0x7
++#define		bZebra1_ChannelNum	0xf80
++#define		bZebra1_TxLPFBW		0x400
++#define		bZebra1_RxLPFBW		0x600
++
++/* Zebra4 */
++#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
++#define		bRTL8256RegModeCtrl0	0x40
++#define		bRTL8256_TxLPFBW		0x18
++#define		bRTL8256_RxLPFBW		0x600
++
++/* RTL8258 */
++#define		bRTL8258_TxLPFBW		0xc	/* Useless */
++#define		bRTL8258_RxLPFBW		0xc00
++#define		bRTL8258_RSSILPFBW	0xc0
++
++
++/*
++ * Other Definition
++ *   */
++
++/* byte endable for sb_write */
++#define		bByte0				0x1	/* Useless */
++#define		bByte1				0x2
++#define		bByte2				0x4
++#define		bByte3				0x8
++#define		bWord0				0x3
++#define		bWord1				0xc
++#define		bDWord				0xf
++
++/* for PutRegsetting & GetRegSetting BitMask */
++#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
++#define		bMaskByte1			0xff00
++#define		bMaskByte2			0xff0000
++#define		bMaskByte3			0xff000000
++#define		bMaskHWord		0xffff0000
++#define		bMaskLWord			0x0000ffff
++#define		bMaskDWord		0xffffffff
++#define		bMaskH3Bytes		0xffffff00
++#define		bMask12Bits			0xfff
++#define		bMaskH4Bits			0xf0000000
++#define		bMaskOFDM_D		0xffc00000
++#define		bMaskCCK			0x3f3f3f3f
++
++
++#define		bEnable			0x1	/* Useless */
++#define		bDisable		0x0
++
++#define		LeftAntenna		0x0	/* Useless */
++#define		RightAntenna	0x1
++
++#define		tCheckTxStatus		500   /* 500ms // Useless */
++#define		tUpdateRxCounter	100   /* 100ms */
++
++#define		rateCCK		0	/* Useless */
++#define		rateOFDM	1
++#define		rateHT		2
++
++/* define Register-End */
++#define		bPMAC_End			0x1ff	/* Useless */
++#define		bFPGAPHY0_End		0x8ff
++#define		bFPGAPHY1_End		0x9ff
++#define		bCCKPHY0_End		0xaff
++#define		bOFDMPHY0_End		0xcff
++#define		bOFDMPHY1_End		0xdff
++
++/* define max debug item in each debug page
++ * #define bMaxItem_FPGA_PHY0        0x9
++ * #define bMaxItem_FPGA_PHY1        0x3
++ * #define bMaxItem_PHY_11B          0x16
++ * #define bMaxItem_OFDM_PHY0        0x29
++ * #define bMaxItem_OFDM_PHY1        0x0 */
++
++#define		bPMACControl		0x0		/* Useless */
++#define		bWMACControl		0x1
++#define		bWNICControl		0x2
++
++#define		PathA			0x0	/* Useless */
++#define		PathB			0x1
++#define		PathC			0x2
++#define		PathD			0x3
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192FPwrSeq.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192FPwrSeq.h
+new file mode 100644
+index 000000000..2b0bdc7e3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8192FPwrSeq.h
+@@ -0,0 +1,220 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef REALTEK_POWER_SEQUENCE_8192F
++#define REALTEK_POWER_SEQUENCE_8192F
++#define POWER_SEQUENCE_8192F_VER 04
++/* #include "PwrSeqCmd.h" */
++#include "HalPwrSeqCmd.h"
++
++/*
++	Check document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd
++	There are 6 HW Power States:
++	0: POFF--Power Off
++	1: PDN--Power Down
++	2: CARDEMU--Card Emulation
++	3: ACT--Active Mode
++	4: LPS--Low Power State
++	5: SUS--Suspend
++
++	The transition from different states are defined below
++	TRANS_CARDEMU_TO_ACT
++	TRANS_ACT_TO_CARDEMU
++	TRANS_CARDEMU_TO_SUS
++	TRANS_SUS_TO_CARDEMU
++	TRANS_CARDEMU_TO_PDN
++	TRANS_ACT_TO_LPS
++	TRANS_LPS_TO_ACT
++
++	TRANS_END
++*/
++#define	RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS	38
++#define	RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS	8
++#define	RTL8192F_TRANS_CARDEMU_TO_SUS_STEPS	7
++#define	RTL8192F_TRANS_SUS_TO_CARDEMU_STEPS	5
++#define	RTL8192F_TRANS_CARDEMU_TO_CARDDIS_STEPS	8
++#define	RTL8192F_TRANS_CARDDIS_TO_CARDEMU_STEPS	8
++#define	RTL8192F_TRANS_CARDEMU_TO_PDN_STEPS	4
++#define	RTL8192F_TRANS_PDN_TO_CARDEMU_STEPS	1
++#define	RTL8192F_TRANS_ACT_TO_LPS_STEPS		13
++#define	RTL8192F_TRANS_LPS_TO_ACT_STEPS		11	
++#define	RTL8192F_TRANS_END_STEPS	1
++
++
++#define RTL8192F_TRANS_CARDEMU_TO_ACT 														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/	\
++	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/	\
++	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
++	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \
++	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
++	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/ \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, (BIT1|BIT0), 0}, \
++	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},/* SWR OCP enable 0x10[18]=1*/ \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
++	{0x007f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x7c[31]=1,LDO has max output capability*/ \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \
++	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \
++	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
++	{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 data mode*/\
++	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
++	{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
++	{0x0068, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/*RF HW ON/OFF Enable*/\
++	{0x001C, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/*Register Lock Disable*/\
++	{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\
++	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S1*/\
++	{0x007B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S0*/\
++	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/*enable RF path S1*/\
++	{0x007B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/*enalbe RF path S0*/\
++	{0x0097, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*AFE_Ctrl*/\
++	{0x00DC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xCC},/*AFE_Ctrl*/\
++	{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x18, 0x00},/*AFE_Ctrl 0x24[4:3]=00 for xtal gmn*/\
++	{0x1050, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[7:0] Pull down software register*/\
++	{0x1051, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[15:8] Pull down software register*/\
++	{0x1052, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[23:16] Pull down software register*/\
++	{0x1053, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[31:24] Pull down software register*/\
++	{0x105B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_B[7:0] Pull down software register*/\
++	{0x001C, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*Register Lock Enable*/\
++	{0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT7|BIT6), 0x3},/*set HCI Power sequence state delay time:0*/
++
++	
++#define RTL8192F_TRANS_ACT_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x2[0]=0 Reset BB,RF enter Power Down mode*/ \
++	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/ \
++	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x10[18] = 0 to disable ocp*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
++	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
++	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
++
++
++#define RTL8192F_TRANS_CARDEMU_TO_SUS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 USB|SDIO SOP option to disable BG/MB/ACK/SWR*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
++
++#define RTL8192F_TRANS_SUS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
++	
++
++#define RTL8192F_TRANS_CARDEMU_TO_CARDDIS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend*/	\
++	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
++
++#define RTL8192F_TRANS_CARDDIS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/	\
++	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x10[18] = 1 to enable ocp*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
++
++
++#define RTL8192F_TRANS_CARDEMU_TO_PDN												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
++
++#define RTL8192F_TRANS_PDN_TO_CARDEMU												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
++
++#define RTL8192F_TRANS_ACT_TO_LPS														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
++	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
++	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
++	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
++
++
++#define RTL8192F_TRANS_LPS_TO_ACT															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
++	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
++	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0 	 switch TSF to 40M*/\
++	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
++	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
++ 
++#define RTL8192F_TRANS_END															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
++
++
++extern WLAN_PWR_CFG rtl8192F_power_on_flow[RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8192F_radio_off_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8192F_card_disable_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_CARDDIS_STEPS+RTL8192F_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8192F_card_enable_flow[RTL8192F_TRANS_CARDDIS_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8192F_suspend_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_SUS_STEPS+RTL8192F_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8192F_resume_flow[RTL8192F_TRANS_SUS_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8192F_hwpdn_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192F_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8192F_enter_lps_flow[RTL8192F_TRANS_ACT_TO_LPS_STEPS+RTL8192F_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8192F_leave_lps_flow[RTL8192F_TRANS_LPS_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8703BPhyCfg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8703BPhyCfg.h
+new file mode 100644
+index 000000000..57a421a03
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8703BPhyCfg.h
+@@ -0,0 +1,116 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8703BPHYCFG_H__
++#define __INC_HAL8703BPHYCFG_H__
++
++/*--------------------------Define Parameters-------------------------------*/
++#define LOOP_LIMIT				5
++#define MAX_STALL_TIME			50		/* us */
++#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
++#define MAX_TXPWR_IDX_NMODE_92S	63
++#define Reset_Cnt_Limit			3
++
++#ifdef CONFIG_PCI_HCI
++	#define MAX_AGGR_NUM	0x0B
++#else
++	#define MAX_AGGR_NUM	0x07
++#endif /* CONFIG_PCI_HCI */
++
++
++/*--------------------------Define Parameters End-------------------------------*/
++
++
++/*------------------------------Define structure----------------------------*/
++
++/*------------------------------Define structure End----------------------------*/
++
++/*--------------------------Exported Function prototype---------------------*/
++u32
++PHY_QueryBBReg_8703B(
++		PADAPTER	Adapter,
++		u32		RegAddr,
++		u32		BitMask
++);
++
++void
++PHY_SetBBReg_8703B(
++		PADAPTER	Adapter,
++		u32		RegAddr,
++		u32		BitMask,
++		u32		Data
++);
++
++u32
++PHY_QueryRFReg_8703B(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				RegAddr,
++		u32				BitMask
++);
++
++void
++PHY_SetRFReg_8703B(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				RegAddr,
++		u32				BitMask,
++		u32				Data
++);
++
++/* MAC/BB/RF HAL config */
++int PHY_BBConfig8703B(PADAPTER	Adapter);
++
++int PHY_RFConfig8703B(PADAPTER	Adapter);
++
++s32 PHY_MACConfig8703B(PADAPTER padapter);
++
++int
++PHY_ConfigRFWithParaFile_8703B(
++		PADAPTER			Adapter,
++		u8					*pFileName,
++	enum rf_path				eRFPath
++);
++
++void
++PHY_SetTxPowerIndex_8703B(
++		PADAPTER			Adapter,
++		u32					PowerIndex,
++		enum rf_path			RFPath,
++		u8					Rate
++);
++
++void
++PHY_SetTxPowerLevel8703B(
++		PADAPTER		Adapter,
++		u8			channel
++);
++
++void
++PHY_SetSwChnlBWMode8703B(
++		PADAPTER			Adapter,
++		u8					channel,
++		enum channel_width	Bandwidth,
++		u8					Offset40,
++		u8					Offset80
++);
++
++void phy_set_rf_path_switch_8703b(
++		struct dm_struct		*phydm,
++		bool		bMain
++);
++
++/*--------------------------Exported Function prototype End---------------------*/
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8703BPhyReg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8703BPhyReg.h
+new file mode 100644
+index 000000000..881a13cfa
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8703BPhyReg.h
+@@ -0,0 +1,1133 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8703BPHYREG_H__
++#define __INC_HAL8703BPHYREG_H__
++
++#define		rSYM_WLBT_PAPE_SEL		0x64
++/*
++ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
++ * 3. RF register 0x00-2E
++ * 4. Bit Mask for BB/RF register
++ * 5. Other defintion for BB/RF R/W
++ *   */
++
++
++/*
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 1. Page1(0x100)
++ *   */
++#define		rPMAC_Reset					0x100
++#define		rPMAC_TxStart					0x104
++#define		rPMAC_TxLegacySIG				0x108
++#define		rPMAC_TxHTSIG1				0x10c
++#define		rPMAC_TxHTSIG2				0x110
++#define		rPMAC_PHYDebug				0x114
++#define		rPMAC_TxPacketNum				0x118
++#define		rPMAC_TxIdle					0x11c
++#define		rPMAC_TxMACHeader0			0x120
++#define		rPMAC_TxMACHeader1			0x124
++#define		rPMAC_TxMACHeader2			0x128
++#define		rPMAC_TxMACHeader3			0x12c
++#define		rPMAC_TxMACHeader4			0x130
++#define		rPMAC_TxMACHeader5			0x134
++#define		rPMAC_TxDataType				0x138
++#define		rPMAC_TxRandomSeed			0x13c
++#define		rPMAC_CCKPLCPPreamble			0x140
++#define		rPMAC_CCKPLCPHeader			0x144
++#define		rPMAC_CCKCRC16				0x148
++#define		rPMAC_OFDMRxCRC32OK			0x170
++#define		rPMAC_OFDMRxCRC32Er			0x174
++#define		rPMAC_OFDMRxParityEr			0x178
++#define		rPMAC_OFDMRxCRC8Er			0x17c
++#define		rPMAC_CCKCRxRC16Er			0x180
++#define		rPMAC_CCKCRxRC32Er			0x184
++#define		rPMAC_CCKCRxRC32OK			0x188
++#define		rPMAC_TxStatus					0x18c
++
++/*
++ * 2. Page2(0x200)
++ *
++ * The following two definition are only used for USB interface. */
++#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
++#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
++
++/*
++ * 3. Page8(0x800)
++ *   */
++#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
++
++#define		rFPGA0_TxInfo				0x804	/* Status report?? */
++#define		rFPGA0_PSDFunction			0x808
++
++#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
++
++#define		rFPGA0_RFTiming1			0x810	/* Useless now */
++#define		rFPGA0_RFTiming2			0x814
++
++#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
++#define		rFPGA0_XA_HSSIParameter2		0x824
++#define		rFPGA0_XB_HSSIParameter1		0x828
++#define		rFPGA0_XB_HSSIParameter2		0x82c
++#define		rTxAGC_B_Rate18_06				0x830
++#define		rTxAGC_B_Rate54_24				0x834
++#define		rTxAGC_B_CCK1_55_Mcs32		0x838
++#define		rTxAGC_B_Mcs03_Mcs00			0x83c
++
++#define		rTxAGC_B_Mcs07_Mcs04			0x848
++#define		rTxAGC_B_Mcs11_Mcs08			0x84c
++
++#define		rFPGA0_XA_LSSIParameter		0x840
++#define		rFPGA0_XB_LSSIParameter		0x844
++
++#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
++#define		rFPGA0_RFSleepUpParameter		0x854
++
++#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
++#define		rFPGA0_XCD_SwitchControl		0x85c
++
++#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
++#define		rFPGA0_XB_RFInterfaceOE		0x864
++
++#define		rTxAGC_B_Mcs15_Mcs12			0x868
++#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
++
++#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
++#define		rFPGA0_XCD_RFInterfaceSW		0x874
++
++#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
++#define		rFPGA0_XCD_RFParameter		0x87c
++
++#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
++#define		rFPGA0_AnalogParameter2		0x884
++#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
++#define		rFPGA0_AnalogParameter4		0x88c
++
++#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
++#define		rFPGA0_XB_LSSIReadBack		0x8a4
++#define		rFPGA0_XC_LSSIReadBack		0x8a8
++#define		rFPGA0_XD_LSSIReadBack		0x8ac
++
++#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
++#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
++#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
++#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
++#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
++
++/*
++ * 4. Page9(0x900)
++ *   */
++#define	rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
++#define	rFPGA1_TxBlock				0x904	/* Useless now */
++#define	rFPGA1_DebugSelect			0x908	/* Useless now */
++#define	rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
++#define	rDPDT_control				0x92c
++#define	rfe_ctrl_anta_src				0x930
++#define	rS0S1_PathSwitch			0x948
++#define	rBBrx_DFIR					0x954
++
++/*
++ * 5. PageA(0xA00)
++ *
++ * Set Control channel to upper or lower. These settings are required only for 40MHz */
++#define		rCCK0_System				0xa00
++
++#define		rCCK0_AFESetting			0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
++#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
++
++#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
++#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
++
++#define		rCCK0_RxHP					0xa14
++
++#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
++#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
++
++#define		rCCK0_TxFilter1				0xa20
++#define		rCCK0_TxFilter2				0xa24
++#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
++#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
++#define		rCCK0_TRSSIReport		0xa50
++#define		rCCK0_RxReport            		0xa54  /* 0xa57 */
++#define		rCCK0_FACounterLower      	0xa5c  /* 0xa5b */
++#define		rCCK0_FACounterUpper      	0xa58  /* 0xa5c */
++
++/*
++ * PageB(0xB00)
++ *   */
++#define rPdp_AntA						0xb00
++#define rPdp_AntA_4						0xb04
++#define rPdp_AntA_8						0xb08
++#define rPdp_AntA_C						0xb0c
++#define rPdp_AntA_10					0xb10
++#define rPdp_AntA_14					0xb14
++#define rPdp_AntA_18					0xb18
++#define rPdp_AntA_1C					0xb1c
++#define rPdp_AntA_20					0xb20
++#define rPdp_AntA_24					0xb24
++
++#define rConfig_Pmpd_AntA				0xb28
++#define rConfig_ram64x16				0xb2c
++
++#define rBndA							0xb30
++#define rHssiPar						0xb34
++
++#define rConfig_AntA					0xb68
++#define rConfig_AntB					0xb6c
++
++#define rPdp_AntB						0xb70
++#define rPdp_AntB_4						0xb74
++#define rPdp_AntB_8						0xb78
++#define rPdp_AntB_C						0xb7c
++#define rPdp_AntB_10					0xb80
++#define rPdp_AntB_14					0xb84
++#define rPdp_AntB_18					0xb88
++#define rPdp_AntB_1C					0xb8c
++#define rPdp_AntB_20					0xb90
++#define rPdp_AntB_24					0xb94
++
++#define rConfig_Pmpd_AntB				0xb98
++
++#define rBndB							0xba0
++
++#define rAPK							0xbd8
++#define rPm_Rx0_AntA					0xbdc
++#define rPm_Rx1_AntA					0xbe0
++#define rPm_Rx2_AntA					0xbe4
++#define rPm_Rx3_AntA					0xbe8
++#define rPm_Rx0_AntB					0xbec
++#define rPm_Rx1_AntB					0xbf0
++#define rPm_Rx2_AntB					0xbf4
++#define rPm_Rx3_AntB					0xbf8
++/*
++ * 6. PageC(0xC00)
++ *   */
++#define		rOFDM0_LSTF				0xc00
++
++#define		rOFDM0_TRxPathEnable		0xc04
++#define		rOFDM0_TRMuxPar			0xc08
++#define		rOFDM0_TRSWIsolation		0xc0c
++
++#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
++#define		rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
++#define		rOFDM0_XBRxAFE		0xc18
++#define		rOFDM0_XBRxIQImbalance	0xc1c
++#define		rOFDM0_XCRxAFE		0xc20
++#define		rOFDM0_XCRxIQImbalance	0xc24
++#define		rOFDM0_XDRxAFE		0xc28
++#define		rOFDM0_XDRxIQImbalance	0xc2c
++
++#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
++#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
++#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
++#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
++
++#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
++#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
++#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
++#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
++
++#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
++#define		rOFDM0_XAAGCCore2			0xc54
++#define		rOFDM0_XBAGCCore1			0xc58
++#define		rOFDM0_XBAGCCore2			0xc5c
++#define		rOFDM0_XCAGCCore1			0xc60
++#define		rOFDM0_XCAGCCore2			0xc64
++#define		rOFDM0_XDAGCCore1			0xc68
++#define		rOFDM0_XDAGCCore2			0xc6c
++
++#define		rOFDM0_AGCParameter1			0xc70
++#define		rOFDM0_AGCParameter2			0xc74
++#define		rOFDM0_AGCRSSITable			0xc78
++#define		rOFDM0_HTSTFAGC				0xc7c
++
++#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
++#define		rOFDM0_XATxAFE				0xc84
++#define		rOFDM0_XBTxIQImbalance		0xc88
++#define		rOFDM0_XBTxAFE				0xc8c
++#define		rOFDM0_XCTxIQImbalance		0xc90
++#define		rOFDM0_XCTxAFE			0xc94
++#define		rOFDM0_XDTxIQImbalance		0xc98
++#define		rOFDM0_XDTxAFE				0xc9c
++
++#define		rOFDM0_RxIQExtAnta			0xca0
++#define		rOFDM0_TxCoeff1				0xca4
++#define		rOFDM0_TxCoeff2				0xca8
++#define		rOFDM0_TxCoeff3				0xcac
++#define		rOFDM0_TxCoeff4				0xcb0
++#define		rOFDM0_TxCoeff5				0xcb4
++#define		rOFDM0_TxCoeff6				0xcb8
++#define		rOFDM0_RxHPParameter			0xce0
++#define		rOFDM0_TxPseudoNoiseWgt		0xce4
++#define		rOFDM0_FrameSync				0xcf0
++#define		rOFDM0_DFSReport				0xcf4
++
++/*
++ * 7. PageD(0xD00)
++ *   */
++#define		rOFDM1_LSTF					0xd00
++#define		rOFDM1_TRxPathEnable			0xd04
++
++#define		rOFDM1_CFO						0xd08	/* No setting now */
++#define		rOFDM1_CSI1					0xd10
++#define		rOFDM1_SBD						0xd14
++#define		rOFDM1_CSI2					0xd18
++#define		rOFDM1_CFOTracking			0xd2c
++#define		rOFDM1_TRxMesaure1			0xd34
++#define		rOFDM1_IntfDet					0xd3c
++#define		rOFDM1_PseudoNoiseStateAB		0xd50
++#define		rOFDM1_PseudoNoiseStateCD		0xd54
++#define		rOFDM1_RxPseudoNoiseWgt		0xd58
++
++#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
++#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
++#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
++
++#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
++#define		rOFDM_ShortCFOCD				0xdb0
++#define		rOFDM_LongCFOAB				0xdb4
++#define		rOFDM_LongCFOCD				0xdb8
++#define		rOFDM_TailCFOAB				0xdbc
++#define		rOFDM_TailCFOCD				0xdc0
++#define		rOFDM_PWMeasure1		0xdc4
++#define		rOFDM_PWMeasure2		0xdc8
++#define		rOFDM_BWReport				0xdcc
++#define		rOFDM_AGCReport				0xdd0
++#define		rOFDM_RxSNR					0xdd4
++#define		rOFDM_RxEVMCSI				0xdd8
++#define		rOFDM_SIGReport				0xddc
++
++
++/*
++ * 8. PageE(0xE00)
++ *   */
++#define		rTxAGC_A_Rate18_06			0xe00
++#define		rTxAGC_A_Rate54_24			0xe04
++#define		rTxAGC_A_CCK1_Mcs32			0xe08
++#define		rTxAGC_A_Mcs03_Mcs00			0xe10
++#define		rTxAGC_A_Mcs07_Mcs04			0xe14
++#define		rTxAGC_A_Mcs11_Mcs08			0xe18
++#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
++
++#define		rFPGA0_IQK					0xe28
++#define		rTx_IQK_Tone_A				0xe30
++#define		rRx_IQK_Tone_A				0xe34
++#define		rTx_IQK_PI_A					0xe38
++#define		rRx_IQK_PI_A					0xe3c
++
++#define		rTx_IQK						0xe40
++#define		rRx_IQK						0xe44
++#define		rIQK_AGC_Pts					0xe48
++#define		rIQK_AGC_Rsp					0xe4c
++#define		rTx_IQK_Tone_B				0xe50
++#define		rRx_IQK_Tone_B				0xe54
++#define		rTx_IQK_PI_B					0xe58
++#define		rRx_IQK_PI_B					0xe5c
++#define		rIQK_AGC_Cont				0xe60
++
++#define		rBlue_Tooth					0xe6c
++#define		rRx_Wait_CCA					0xe70
++#define		rTx_CCK_RFON					0xe74
++#define		rTx_CCK_BBON				0xe78
++#define		rTx_OFDM_RFON				0xe7c
++#define		rTx_OFDM_BBON				0xe80
++#define		rTx_To_Rx					0xe84
++#define		rTx_To_Tx					0xe88
++#define		rRx_CCK						0xe8c
++
++#define		rTx_Power_Before_IQK_A		0xe94
++#define		rTx_Power_After_IQK_A			0xe9c
++
++#define		rRx_Power_Before_IQK_A		0xea0
++#define		rRx_Power_Before_IQK_A_2		0xea4
++#define		rRx_Power_After_IQK_A			0xea8
++#define		rRx_Power_After_IQK_A_2		0xeac
++
++#define		rTx_Power_Before_IQK_B		0xeb4
++#define		rTx_Power_After_IQK_B			0xebc
++
++#define		rRx_Power_Before_IQK_B		0xec0
++#define		rRx_Power_Before_IQK_B_2		0xec4
++#define		rRx_Power_After_IQK_B			0xec8
++#define		rRx_Power_After_IQK_B_2		0xecc
++
++#define		rRx_OFDM					0xed0
++#define		rRx_Wait_RIFS				0xed4
++#define		rRx_TO_Rx					0xed8
++#define		rStandby						0xedc
++#define		rSleep						0xee0
++#define		rPMPD_ANAEN				0xeec
++
++/*
++ * 7. RF Register 0x00-0x2E (RF 8256)
++ * RF-0222D 0x00-3F
++ *
++ * Zebra1 */
++#define		rZebra1_HSSIEnable				0x0	/* Useless now */
++#define		rZebra1_TRxEnable1				0x1
++#define		rZebra1_TRxEnable2				0x2
++#define		rZebra1_AGC					0x4
++#define		rZebra1_ChargePump			0x5
++#define		rZebra1_Channel				0x7	/* RF channel switch */
++
++/* #endif */
++#define		rZebra1_TxGain					0x8	/* Useless now */
++#define		rZebra1_TxLPF					0x9
++#define		rZebra1_RxLPF					0xb
++#define		rZebra1_RxHPFCorner			0xc
++
++/* Zebra4 */
++#define		rGlobalCtrl						0	/* Useless now */
++#define		rRTL8256_TxLPF					19
++#define		rRTL8256_RxLPF					11
++
++/* RTL8258 */
++#define		rRTL8258_TxLPF					0x11	/* Useless now */
++#define		rRTL8258_RxLPF					0x13
++#define		rRTL8258_RSSILPF				0xa
++
++/*
++ * RL6052 Register definition
++ *   */
++#define		RF_AC						0x00	/*  */
++
++#define		RF_IQADJ_G1				0x01	/*  */
++#define		RF_IQADJ_G2				0x02	/*  */
++#define		RF_BS_PA_APSET_G1_G4		0x03
++#define		RF_BS_PA_APSET_G5_G8		0x04
++#define		RF_POW_TRSW				0x05	/*  */
++
++#define		RF_GAIN_RX					0x06	/*  */
++#define		RF_GAIN_TX					0x07	/*  */
++
++#define		RF_TXM_IDAC				0x08	/*  */
++#define		RF_IPA_G					0x09	/*  */
++#define		RF_TXBIAS_G				0x0A
++#define		RF_TXPA_AG					0x0B
++#define		RF_IPA_A					0x0C	/*  */
++#define		RF_TXBIAS_A				0x0D
++#define		RF_BS_PA_APSET_G9_G11	0x0E
++#define		RF_BS_IQGEN				0x0F	/*  */
++
++#define		RF_MODE1					0x10	/*  */
++#define		RF_MODE2					0x11	/*  */
++
++#define		RF_RX_AGC_HP				0x12	/*  */
++#define		RF_TX_AGC					0x13	/*  */
++#define		RF_BIAS						0x14	/*  */
++#define		RF_IPA						0x15	/*  */
++#define		RF_TXBIAS					0x16
++#define		RF_POW_ABILITY			0x17	/*  */
++#define		RF_MODE_AG				0x18	/*  */
++#define		rRfChannel					0x18	/* RF channel and BW switch */
++#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
++#define		RF_TOP						0x19	/*  */
++
++#define		RF_RX_G1					0x1A	/*  */
++#define		RF_RX_G2					0x1B	/*  */
++
++#define		RF_RX_BB2					0x1C	/*  */
++#define		RF_RX_BB1					0x1D	/*  */
++
++#define		RF_RCK1					0x1E	/*  */
++#define		RF_RCK2					0x1F	/*  */
++
++#define		RF_TX_G1					0x20	/*  */
++#define		RF_TX_G2					0x21	/*  */
++#define		RF_TX_G3					0x22	/*  */
++
++#define		RF_TX_BB1					0x23	/*  */
++
++#define		RF_T_METER					0x24	/*  */
++
++#define		RF_SYN_G1					0x25	/* RF TX Power control */
++#define		RF_SYN_G2					0x26	/* RF TX Power control */
++#define		RF_SYN_G3					0x27	/* RF TX Power control */
++#define		RF_SYN_G4					0x28	/* RF TX Power control */
++#define		RF_SYN_G5					0x29	/* RF TX Power control */
++#define		RF_SYN_G6					0x2A	/* RF TX Power control */
++#define		RF_SYN_G7					0x2B	/* RF TX Power control */
++#define		RF_SYN_G8					0x2C	/* RF TX Power control */
++
++#define		RF_RCK_OS					0x30	/* RF TX PA control */
++
++#define		RF_TXPA_G1					0x31	/* RF TX PA control */
++#define		RF_TXPA_G2					0x32	/* RF TX PA control */
++#define		RF_TXPA_G3					0x33	/* RF TX PA control */
++#define	RF_TX_BIAS_A				0x35
++#define	RF_TX_BIAS_D				0x36
++#define	RF_LOBF_9					0x38
++#define 	RF_RXRF_A3					0x3C	/*	 */
++#define	RF_TRSW					0x3F
++
++#define	RF_TXRF_A2					0x41
++#define	RF_TXPA_G4					0x46
++#define	RF_TXPA_A4					0x4B
++#define	RF_0x52					0x52
++#define	RF_WE_LUT					0xEF
++#define	RF_S0S1					0xB0
++
++/*
++ * Bit Mask
++ *
++ * 1. Page1(0x100) */
++#define		bBBResetB						0x100	/* Useless now? */
++#define		bGlobalResetB					0x200
++#define		bOFDMTxStart					0x4
++#define		bCCKTxStart						0x8
++#define		bCRC32Debug					0x100
++#define		bPMACLoopback					0x10
++#define		bTxLSIG							0xffffff
++#define		bOFDMTxRate					0xf
++#define		bOFDMTxReserved				0x10
++#define		bOFDMTxLength					0x1ffe0
++#define		bOFDMTxParity					0x20000
++#define		bTxHTSIG1						0xffffff
++#define		bTxHTMCSRate					0x7f
++#define		bTxHTBW						0x80
++#define		bTxHTLength					0xffff00
++#define		bTxHTSIG2						0xffffff
++#define		bTxHTSmoothing					0x1
++#define		bTxHTSounding					0x2
++#define		bTxHTReserved					0x4
++#define		bTxHTAggreation				0x8
++#define		bTxHTSTBC						0x30
++#define		bTxHTAdvanceCoding			0x40
++#define		bTxHTShortGI					0x80
++#define		bTxHTNumberHT_LTF			0x300
++#define		bTxHTCRC8						0x3fc00
++#define		bCounterReset					0x10000
++#define		bNumOfOFDMTx					0xffff
++#define		bNumOfCCKTx					0xffff0000
++#define		bTxIdleInterval					0xffff
++#define		bOFDMService					0xffff0000
++#define		bTxMACHeader					0xffffffff
++#define		bTxDataInit						0xff
++#define		bTxHTMode						0x100
++#define		bTxDataType					0x30000
++#define		bTxRandomSeed					0xffffffff
++#define		bCCKTxPreamble					0x1
++#define		bCCKTxSFD						0xffff0000
++#define		bCCKTxSIG						0xff
++#define		bCCKTxService					0xff00
++#define		bCCKLengthExt					0x8000
++#define		bCCKTxLength					0xffff0000
++#define		bCCKTxCRC16					0xffff
++#define		bCCKTxStatus					0x1
++#define		bOFDMTxStatus					0x2
++
++#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
++#define	RF_TX_GAIN_OFFSET_8703B(_val) (abs((_val)) | (((_val) > 0) ? BIT5 : 0))
++
++/* 2. Page8(0x800) */
++#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
++#define		bJapanMode						0x2
++#define		bCCKTxSC						0x30
++#define		bCCKEn							0x1000000
++#define		bOFDMEn						0x2000000
++
++#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
++#define		bOFDMTxDACPhase		0x40000
++#define		bXATxAGC			0x3f
++
++#define		bAntennaSelect		0x0300
++
++#define		bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
++#define		bXCTxAGC			0xf000
++#define		bXDTxAGC			0xf0000
++
++#define		bPAStart                  			0xf0000000	/* Useless now */
++#define		bTRStart			0x00f00000
++#define		bRFStart			0x0000f000
++#define		bBBStart			0x000000f0
++#define		bBBCCKStart		0x0000000f
++#define		bPAEnd                    			0xf          /* Reg0x814 */
++#define		bTREnd			0x0f000000
++#define		bRFEnd			0x000f0000
++#define		bCCAMask                  			0x000000f0   /* T2R */
++#define		bR2RCCAMask		0x00000f00
++#define		bHSSI_R2TDelay		0xf8000000
++#define		bHSSI_T2RDelay		0xf80000
++#define		bContTxHSSI               		0x400     /* chane gain at continue Tx */
++#define		bIGFromCCK		0x200
++#define		bAGCAddress		0x3f
++#define		bRxHPTx			0x7000
++#define		bRxHPT2R			0x38000
++#define		bRxHPCCKIni		0xc0000
++#define		bAGCTxCode		0xc00000
++#define		bAGCRxCode		0x300000
++
++#define		b3WireDataLength          		0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
++#define		b3WireAddressLength		0x400
++
++#define		b3WireRFPowerDown         		0x1	/* Useless now
++ * #define bHWSISelect		0x8 */
++#define		b5GPAPEPolarity		0x40000000
++#define		b2GPAPEPolarity		0x80000000
++#define		bRFSW_TxDefaultAnt		0x3
++#define		bRFSW_TxOptionAnt		0x30
++#define		bRFSW_RxDefaultAnt		0x300
++#define		bRFSW_RxOptionAnt		0x3000
++#define		bRFSI_3WireData		0x1
++#define		bRFSI_3WireClock		0x2
++#define		bRFSI_3WireLoad		0x4
++#define		bRFSI_3WireRW		0x8
++#define		bRFSI_3Wire			0xf
++
++#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
++
++#define		bRFSI_TRSW                		0x20	/* Useless now */
++#define		bRFSI_TRSWB		0x40
++#define		bRFSI_ANTSW		0x100
++#define		bRFSI_ANTSWB		0x200
++#define		bRFSI_PAPE			0x400
++#define		bRFSI_PAPE5G		0x800
++#define		bBandSelect			0x1
++#define		bHTSIG2_GI			0x80
++#define		bHTSIG2_Smoothing		0x01
++#define		bHTSIG2_Sounding		0x02
++#define		bHTSIG2_Aggreaton		0x08
++#define		bHTSIG2_STBC		0x30
++#define		bHTSIG2_AdvCoding		0x40
++#define		bHTSIG2_NumOfHTLTF	0x300
++#define		bHTSIG2_CRC8		0x3fc
++#define		bHTSIG1_MCS		0x7f
++#define		bHTSIG1_BandWidth		0x80
++#define		bHTSIG1_HTLength		0xffff
++#define		bLSIG_Rate			0xf
++#define		bLSIG_Reserved		0x10
++#define		bLSIG_Length		0x1fffe
++#define		bLSIG_Parity			0x20
++#define		bCCKRxPhase		0x4
++
++#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
++
++#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
++
++#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
++
++#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
++#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
++#define		bRegulator0Standby		0x1
++#define		bRegulatorPLLStandby		0x2
++#define		bRegulator1Standby		0x4
++#define		bPLLPowerUp		0x8
++#define		bDPLLPowerUp		0x10
++#define		bDA10PowerUp		0x20
++#define		bAD7PowerUp		0x200
++#define		bDA6PowerUp		0x2000
++#define		bXtalPowerUp		0x4000
++#define		b40MDClkPowerUP		0x8000
++#define		bDA6DebugMode		0x20000
++#define		bDA6Swing			0x380000
++
++#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
++
++#define		b80MClkDelay              		0x18000000	/* Useless */
++#define		bAFEWatchDogEnable		0x20000000
++
++#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
++#define		bXtalCap23			0x3
++#define		bXtalCap92x					0x0f000000
++#define		bXtalCap			0x0f000000
++
++#define		bIntDifClkEnable          		0x400	/* Useless */
++#define		bExtSigClkEnable		0x800
++#define		bBandgapMbiasPowerUp	0x10000
++#define		bAD11SHGain		0xc0000
++#define		bAD11InputRange		0x700000
++#define		bAD11OPCurrent		0x3800000
++#define		bIPathLoopback		0x4000000
++#define		bQPathLoopback		0x8000000
++#define		bAFELoopback		0x10000000
++#define		bDA10Swing		0x7e0
++#define		bDA10Reverse		0x800
++#define		bDAClkSource		0x1000
++#define		bAD7InputRange		0x6000
++#define		bAD7Gain			0x38000
++#define		bAD7OutputCMMode		0x40000
++#define		bAD7InputCMMode		0x380000
++#define		bAD7Current			0xc00000
++#define		bRegulatorAdjust		0x7000000
++#define		bAD11PowerUpAtTx		0x1
++#define		bDA10PSAtTx		0x10
++#define		bAD11PowerUpAtRx		0x100
++#define		bDA10PSAtRx		0x1000
++#define		bCCKRxAGCFormat		0x200
++#define		bPSDFFTSamplepPoint		0xc000
++#define		bPSDAverageNum		0x3000
++#define		bIQPathControl		0xc00
++#define		bPSDFreq			0x3ff
++#define		bPSDAntennaPath		0x30
++#define		bPSDIQSwitch		0x40
++#define		bPSDRxTrigger		0x400000
++#define		bPSDTxTrigger		0x80000000
++#define		bPSDSineToneScale		0x7f000000
++#define		bPSDReport			0xffff
++
++/* 3. Page9(0x900) */
++#define		bOFDMTxSC                 		0x30000000	/* Useless */
++#define		bCCKTxOn			0x1
++#define		bOFDMTxOn		0x2
++#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
++#define		bDebugItem                		0xff   /* reset debug page and LWord */
++#define		bAntL			0x10
++#define		bAntNonHT				0x100
++#define		bAntHT1			0x1000
++#define		bAntHT2			0x10000
++#define		bAntHT1S1			0x100000
++#define		bAntNonHTS1		0x1000000
++
++/* 4. PageA(0xA00) */
++#define		bCCKBBMode				0x3	/* Useless */
++#define		bCCKTxPowerSaving		0x80
++#define		bCCKRxPowerSaving		0x40
++
++#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
++
++#define		bCCKScramble			0x8	/* Useless */
++#define		bCCKAntDiversity		0x8000
++#define		bCCKCarrierRecovery		0x4000
++#define		bCCKTxRate				0x3000
++#define		bCCKDCCancel			0x0800
++#define		bCCKISICancel			0x0400
++#define		bCCKMatchFilter			0x0200
++#define		bCCKEqualizer			0x0100
++#define		bCCKPreambleDetect		0x800000
++#define		bCCKFastFalseCCA		0x400000
++#define		bCCKChEstStart			0x300000
++#define		bCCKCCACount			0x080000
++#define		bCCKcs_lim				0x070000
++#define		bCCKBistMode			0x80000000
++#define		bCCKCCAMask			0x40000000
++#define		bCCKTxDACPhase		0x4
++#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
++#define		bCCKr_cp_mode0		0x0100
++#define		bCCKTxDCOffset			0xf0
++#define		bCCKRxDCOffset			0xf
++#define		bCCKCCAMode			0xc000
++#define		bCCKFalseCS_lim			0x3f00
++#define		bCCKCS_ratio			0xc00000
++#define		bCCKCorgBit_sel			0x300000
++#define		bCCKPD_lim				0x0f0000
++#define		bCCKNewCCA			0x80000000
++#define		bCCKRxHPofIG			0x8000
++#define		bCCKRxIG				0x7f00
++#define		bCCKLNAPolarity			0x800000
++#define		bCCKRx1stGain			0x7f0000
++#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
++#define		bCCKRxAGCSatLevel		0x1f000000
++#define		bCCKRxAGCSatCount		0xe0
++#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
++#define		bCCKFixedRxAGC			0x8000
++/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
++#define		bCCKAntennaPolarity		0x2000
++#define		bCCKTxFilterType		0x0c00
++#define		bCCKRxAGCReportType	0x0300
++#define		bCCKRxDAGCEn			0x80000000
++#define		bCCKRxDAGCPeriod		0x20000000
++#define		bCCKRxDAGCSatLevel		0x1f000000
++#define		bCCKTimingRecovery		0x800000
++#define		bCCKTxC0				0x3f0000
++#define		bCCKTxC1				0x3f000000
++#define		bCCKTxC2				0x3f
++#define		bCCKTxC3				0x3f00
++#define		bCCKTxC4				0x3f0000
++#define		bCCKTxC5				0x3f000000
++#define		bCCKTxC6				0x3f
++#define		bCCKTxC7				0x3f00
++#define		bCCKDebugPort			0xff0000
++#define		bCCKDACDebug			0x0f000000
++#define		bCCKFalseAlarmEnable	0x8000
++#define		bCCKFalseAlarmRead		0x4000
++#define		bCCKTRSSI				0x7f
++#define		bCCKRxAGCReport		0xfe
++#define		bCCKRxReport_AntSel	0x80000000
++#define		bCCKRxReport_MFOff		0x40000000
++#define		bCCKRxRxReport_SQLoss	0x20000000
++#define		bCCKRxReport_Pktloss	0x10000000
++#define		bCCKRxReport_Lockedbit	0x08000000
++#define		bCCKRxReport_RateError	0x04000000
++#define		bCCKRxReport_RxRate	0x03000000
++#define		bCCKRxFACounterLower	0xff
++#define		bCCKRxFACounterUpper	0xff000000
++#define		bCCKRxHPAGCStart		0xe000
++#define		bCCKRxHPAGCFinal		0x1c00
++#define		bCCKRxFalseAlarmEnable	0x8000
++#define		bCCKFACounterFreeze	0x4000
++#define		bCCKTxPathSel			0x10000000
++#define		bCCKDefaultRxPath		0xc000000
++#define		bCCKOptionRxPath		0x3000000
++
++/* 5. PageC(0xC00) */
++#define		bNumOfSTF				0x3	/* Useless */
++#define		bShift_L					0xc0
++#define		bGI_TH					0xc
++#define		bRxPathA				0x1
++#define		bRxPathB				0x2
++#define		bRxPathC				0x4
++#define		bRxPathD				0x8
++#define		bTxPathA				0x1
++#define		bTxPathB				0x2
++#define		bTxPathC				0x4
++#define		bTxPathD				0x8
++#define		bTRSSIFreq				0x200
++#define		bADCBackoff				0x3000
++#define		bDFIRBackoff			0xc000
++#define		bTRSSILatchPhase		0x10000
++#define		bRxIDCOffset			0xff
++#define		bRxQDCOffset			0xff00
++#define		bRxDFIRMode			0x1800000
++#define		bRxDCNFType			0xe000000
++#define		bRXIQImb_A				0x3ff
++#define		bRXIQImb_B				0xfc00
++#define		bRXIQImb_C				0x3f0000
++#define		bRXIQImb_D				0xffc00000
++#define		bDC_dc_Notch			0x60000
++#define		bRxNBINotch			0x1f000000
++#define		bPD_TH					0xf
++#define		bPD_TH_Opt2			0xc000
++#define		bPWED_TH				0x700
++#define		bIfMF_Win_L			0x800
++#define		bPD_Option				0x1000
++#define		bMF_Win_L				0xe000
++#define		bBW_Search_L			0x30000
++#define		bwin_enh_L				0xc0000
++#define		bBW_TH					0x700000
++#define		bED_TH2				0x3800000
++#define		bBW_option				0x4000000
++#define		bRatio_TH				0x18000000
++#define		bWindow_L				0xe0000000
++#define		bSBD_Option				0x1
++#define		bFrame_TH				0x1c
++#define		bFS_Option				0x60
++#define		bDC_Slope_check		0x80
++#define		bFGuard_Counter_DC_L	0xe00
++#define		bFrame_Weight_Short	0x7000
++#define		bSub_Tune				0xe00000
++#define		bFrame_DC_Length		0xe000000
++#define		bSBD_start_offset		0x30000000
++#define		bFrame_TH_2			0x7
++#define		bFrame_GI2_TH			0x38
++#define		bGI2_Sync_en			0x40
++#define		bSarch_Short_Early		0x300
++#define		bSarch_Short_Late		0xc00
++#define		bSarch_GI2_Late		0x70000
++#define		bCFOAntSum				0x1
++#define		bCFOAcc				0x2
++#define		bCFOStartOffset			0xc
++#define		bCFOLookBack			0x70
++#define		bCFOSumWeight			0x80
++#define		bDAGCEnable			0x10000
++#define		bTXIQImb_A				0x3ff
++#define		bTXIQImb_B				0xfc00
++#define		bTXIQImb_C				0x3f0000
++#define		bTXIQImb_D				0xffc00000
++#define		bTxIDCOffset			0xff
++#define		bTxQDCOffset			0xff00
++#define		bTxDFIRMode			0x10000
++#define		bTxPesudoNoiseOn		0x4000000
++#define		bTxPesudoNoise_A		0xff
++#define		bTxPesudoNoise_B		0xff00
++#define		bTxPesudoNoise_C		0xff0000
++#define		bTxPesudoNoise_D		0xff000000
++#define		bCCADropOption			0x20000
++#define		bCCADropThres			0xfff00000
++#define		bEDCCA_H				0xf
++#define		bEDCCA_L				0xf0
++#define		bLambda_ED			0x300
++#define		bRxInitialGain			0x7f
++#define		bRxAntDivEn				0x80
++#define		bRxAGCAddressForLNA	0x7f00
++#define		bRxHighPowerFlow		0x8000
++#define		bRxAGCFreezeThres		0xc0000
++#define		bRxFreezeStep_AGC1	0x300000
++#define		bRxFreezeStep_AGC2	0xc00000
++#define		bRxFreezeStep_AGC3	0x3000000
++#define		bRxFreezeStep_AGC0	0xc000000
++#define		bRxRssi_Cmp_En			0x10000000
++#define		bRxQuickAGCEn			0x20000000
++#define		bRxAGCFreezeThresMode	0x40000000
++#define		bRxOverFlowCheckType	0x80000000
++#define		bRxAGCShift				0x7f
++#define		bTRSW_Tri_Only			0x80
++#define		bPowerThres			0x300
++#define		bRxAGCEn				0x1
++#define		bRxAGCTogetherEn		0x2
++#define		bRxAGCMin				0x4
++#define		bRxHP_Ini				0x7
++#define		bRxHP_TRLNA			0x70
++#define		bRxHP_RSSI				0x700
++#define		bRxHP_BBP1				0x7000
++#define		bRxHP_BBP2				0x70000
++#define		bRxHP_BBP3				0x700000
++#define		bRSSI_H					0x7f0000     /* the threshold for high power */
++#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
++#define		bRxSettle_TRSW			0x7
++#define		bRxSettle_LNA			0x38
++#define		bRxSettle_RSSI			0x1c0
++#define		bRxSettle_BBP			0xe00
++#define		bRxSettle_RxHP			0x7000
++#define		bRxSettle_AntSW_RSSI	0x38000
++#define		bRxSettle_AntSW		0xc0000
++#define		bRxProcessTime_DAGC	0x300000
++#define		bRxSettle_HSSI			0x400000
++#define		bRxProcessTime_BBPPW	0x800000
++#define		bRxAntennaPowerShift	0x3000000
++#define		bRSSITableSelect		0xc000000
++#define		bRxHP_Final				0x7000000
++#define		bRxHTSettle_BBP			0x7
++#define		bRxHTSettle_HSSI		0x8
++#define		bRxHTSettle_RxHP		0x70
++#define		bRxHTSettle_BBPPW		0x80
++#define		bRxHTSettle_Idle		0x300
++#define		bRxHTSettle_Reserved	0x1c00
++#define		bRxHTRxHPEn			0x8000
++#define		bRxHTAGCFreezeThres	0x30000
++#define		bRxHTAGCTogetherEn	0x40000
++#define		bRxHTAGCMin			0x80000
++#define		bRxHTAGCEn				0x100000
++#define		bRxHTDAGCEn			0x200000
++#define		bRxHTRxHP_BBP			0x1c00000
++#define		bRxHTRxHP_Final		0xe0000000
++#define		bRxPWRatioTH			0x3
++#define		bRxPWRatioEn			0x4
++#define		bRxMFHold				0x3800
++#define		bRxPD_Delay_TH1		0x38
++#define		bRxPD_Delay_TH2		0x1c0
++#define		bRxPD_DC_COUNT_MAX	0x600
++/* #define bRxMF_Hold               0x3800 */
++#define		bRxPD_Delay_TH			0x8000
++#define		bRxProcess_Delay		0xf0000
++#define		bRxSearchrange_GI2_Early	0x700000
++#define		bRxFrame_Guard_Counter_L	0x3800000
++#define		bRxSGI_Guard_L			0xc000000
++#define		bRxSGI_Search_L		0x30000000
++#define		bRxSGI_TH				0xc0000000
++#define		bDFSCnt0				0xff
++#define		bDFSCnt1				0xff00
++#define		bDFSFlag				0xf0000
++#define		bMFWeightSum			0x300000
++#define		bMinIdxTH				0x7f000000
++#define		bDAFormat				0x40000
++#define		bTxChEmuEnable		0x01000000
++#define		bTRSWIsolation_A		0x7f
++#define		bTRSWIsolation_B		0x7f00
++#define		bTRSWIsolation_C		0x7f0000
++#define		bTRSWIsolation_D		0x7f000000
++#define		bExtLNAGain				0x7c00
++
++/* 6. PageE(0xE00) */
++#define		bSTBCEn				0x4	/* Useless */
++#define		bAntennaMapping		0x10
++#define		bNss					0x20
++#define		bCFOAntSumD			0x200
++#define		bPHYCounterReset		0x8000000
++#define		bCFOReportGet			0x4000000
++#define		bOFDMContinueTx		0x10000000
++#define		bOFDMSingleCarrier		0x20000000
++#define		bOFDMSingleTone		0x40000000
++/* #define bRxPath1                 0x01 */
++/* #define bRxPath2                 0x02 */
++/* #define bRxPath3                 0x04 */
++/* #define bRxPath4                 0x08 */
++/* #define bTxPath1                 0x10 */
++/* #define bTxPath2                 0x20 */
++#define		bHTDetect			0x100
++#define		bCFOEn				0x10000
++#define		bCFOValue			0xfff00000
++#define		bSigTone_Re		0x3f
++#define		bSigTone_Im		0x7f00
++#define		bCounter_CCA		0xffff
++#define		bCounter_ParityFail	0xffff0000
++#define		bCounter_RateIllegal		0xffff
++#define		bCounter_CRC8Fail	0xffff0000
++#define		bCounter_MCSNoSupport	0xffff
++#define		bCounter_FastSync	0xffff
++#define		bShortCFO			0xfff
++#define		bShortCFOTLength	12   /* total */
++#define		bShortCFOFLength	11   /* fraction */
++#define		bLongCFO			0x7ff
++#define		bLongCFOTLength	11
++#define		bLongCFOFLength	11
++#define		bTailCFO			0x1fff
++#define		bTailCFOTLength		13
++#define		bTailCFOFLength		12
++#define		bmax_en_pwdB		0xffff
++#define		bCC_power_dB		0xffff0000
++#define		bnoise_pwdB		0xffff
++#define		bPowerMeasTLength	10
++#define		bPowerMeasFLength	3
++#define		bRx_HT_BW			0x1
++#define		bRxSC				0x6
++#define		bRx_HT				0x8
++#define		bNB_intf_det_on		0x1
++#define		bIntf_win_len_cfg	0x30
++#define		bNB_Intf_TH_cfg		0x1c0
++#define		bRFGain				0x3f
++#define		bTableSel			0x40
++#define		bTRSW				0x80
++#define		bRxSNR_A			0xff
++#define		bRxSNR_B			0xff00
++#define		bRxSNR_C			0xff0000
++#define		bRxSNR_D			0xff000000
++#define		bSNREVMTLength		8
++#define		bSNREVMFLength		1
++#define		bCSI1st				0xff
++#define		bCSI2nd				0xff00
++#define		bRxEVM1st			0xff0000
++#define		bRxEVM2nd			0xff000000
++#define		bSIGEVM			0xff
++#define		bPWDB				0xff00
++#define		bSGIEN				0x10000
++
++#define		bSFactorQAM1		0xf	/* Useless */
++#define		bSFactorQAM2		0xf0
++#define		bSFactorQAM3		0xf00
++#define		bSFactorQAM4		0xf000
++#define		bSFactorQAM5		0xf0000
++#define		bSFactorQAM6		0xf0000
++#define		bSFactorQAM7		0xf00000
++#define		bSFactorQAM8		0xf000000
++#define		bSFactorQAM9		0xf0000000
++#define		bCSIScheme			0x100000
++
++#define		bNoiseLvlTopSet		0x3	/* Useless */
++#define		bChSmooth			0x4
++#define		bChSmoothCfg1		0x38
++#define		bChSmoothCfg2		0x1c0
++#define		bChSmoothCfg3		0xe00
++#define		bChSmoothCfg4		0x7000
++#define		bMRCMode			0x800000
++#define		bTHEVMCfg			0x7000000
++
++#define		bLoopFitType		0x1	/* Useless */
++#define		bUpdCFO			0x40
++#define		bUpdCFOOffData		0x80
++#define		bAdvUpdCFO			0x100
++#define		bAdvTimeCtrl		0x800
++#define		bUpdClko			0x1000
++#define		bFC					0x6000
++#define		bTrackingMode		0x8000
++#define		bPhCmpEnable		0x10000
++#define		bUpdClkoLTF		0x20000
++#define		bComChCFO			0x40000
++#define		bCSIEstiMode		0x80000
++#define		bAdvUpdEqz			0x100000
++#define		bUChCfg				0x7000000
++#define		bUpdEqz			0x8000000
++
++/* Rx Pseduo noise */
++#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
++#define		bRxPesudoNoise_A		0xff
++#define		bRxPesudoNoise_B		0xff00
++#define		bRxPesudoNoise_C		0xff0000
++#define		bRxPesudoNoise_D		0xff000000
++#define		bPesudoNoiseState_A	0xffff
++#define		bPesudoNoiseState_B	0xffff0000
++#define		bPesudoNoiseState_C	0xffff
++#define		bPesudoNoiseState_D	0xffff0000
++
++/* 7. RF Register
++ * Zebra1 */
++#define		bZebra1_HSSIEnable		0x8		/* Useless */
++#define		bZebra1_TRxControl		0xc00
++#define		bZebra1_TRxGainSetting	0x07f
++#define		bZebra1_RxCorner		0xc00
++#define		bZebra1_TxChargePump	0x38
++#define		bZebra1_RxChargePump	0x7
++#define		bZebra1_ChannelNum	0xf80
++#define		bZebra1_TxLPFBW		0x400
++#define		bZebra1_RxLPFBW		0x600
++
++/* Zebra4 */
++#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
++#define		bRTL8256RegModeCtrl0	0x40
++#define		bRTL8256_TxLPFBW		0x18
++#define		bRTL8256_RxLPFBW		0x600
++
++/* RTL8258 */
++#define		bRTL8258_TxLPFBW		0xc	/* Useless */
++#define		bRTL8258_RxLPFBW		0xc00
++#define		bRTL8258_RSSILPFBW	0xc0
++
++
++/*
++ * Other Definition
++ *   */
++
++/* byte endable for sb_write */
++#define		bByte0				0x1	/* Useless */
++#define		bByte1				0x2
++#define		bByte2				0x4
++#define		bByte3				0x8
++#define		bWord0				0x3
++#define		bWord1				0xc
++#define		bDWord				0xf
++
++/* for PutRegsetting & GetRegSetting BitMask */
++#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
++#define		bMaskByte1			0xff00
++#define		bMaskByte2			0xff0000
++#define		bMaskByte3			0xff000000
++#define		bMaskHWord		0xffff0000
++#define		bMaskLWord			0x0000ffff
++#define		bMaskDWord		0xffffffff
++#define		bMaskH3Bytes		0xffffff00
++#define		bMask12Bits			0xfff
++#define		bMaskH4Bits			0xf0000000
++#define		bMaskOFDM_D		0xffc00000
++#define		bMaskCCK			0x3f3f3f3f
++
++
++#define		bEnable			0x1	/* Useless */
++#define		bDisable		0x0
++
++#define		LeftAntenna		0x0	/* Useless */
++#define		RightAntenna	0x1
++
++#define		tCheckTxStatus		500   /* 500ms */ /* Useless */
++#define		tUpdateRxCounter	100   /* 100ms */
++
++#define		rateCCK		0	/* Useless */
++#define		rateOFDM	1
++#define		rateHT		2
++
++/* define Register-End */
++#define		bPMAC_End			0x1ff	/* Useless */
++#define		bFPGAPHY0_End		0x8ff
++#define		bFPGAPHY1_End		0x9ff
++#define		bCCKPHY0_End		0xaff
++#define		bOFDMPHY0_End		0xcff
++#define		bOFDMPHY1_End		0xdff
++
++/* define max debug item in each debug page
++ * #define bMaxItem_FPGA_PHY0        0x9
++ * #define bMaxItem_FPGA_PHY1        0x3
++ * #define bMaxItem_PHY_11B          0x16
++ * #define bMaxItem_OFDM_PHY0        0x29
++ * #define bMaxItem_OFDM_PHY1        0x0 */
++
++#define		bPMACControl		0x0		/* Useless */
++#define		bWMACControl		0x1
++#define		bWNICControl		0x2
++
++#define		PathA			0x0	/* Useless */
++#define		PathB			0x1
++#define		PathC			0x2
++#define		PathD			0x3
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8703BPwrSeq.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8703BPwrSeq.h
+new file mode 100644
+index 000000000..0dac13ee3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8703BPwrSeq.h
+@@ -0,0 +1,198 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef REALTEK_POWER_SEQUENCE_8703B
++#define REALTEK_POWER_SEQUENCE_8703B
++
++#include "HalPwrSeqCmd.h"
++
++/*
++	Check document WM-20140402-JackieLau-RTL8703B_Power_Architecture v09.vsd
++	There are 6 HW Power States:
++	0: POFF--Power Off
++	1: PDN--Power Down
++	2: CARDEMU--Card Emulation
++	3: ACT--Active Mode
++	4: LPS--Low Power State
++	5: SUS--Suspend
++
++	The transision from different states are defined below
++	TRANS_CARDEMU_TO_ACT
++	TRANS_ACT_TO_CARDEMU
++	TRANS_CARDEMU_TO_SUS
++	TRANS_SUS_TO_CARDEMU
++	TRANS_CARDEMU_TO_PDN
++	TRANS_ACT_TO_LPS
++	TRANS_LPS_TO_ACT
++
++	TRANS_END
++*/
++#define	RTL8703B_TRANS_CARDEMU_TO_ACT_STEPS	23
++#define	RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS	15
++#define	RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS	15
++#define	RTL8703B_TRANS_SUS_TO_CARDEMU_STEPS	15
++#define	RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS	15
++#define	RTL8703B_TRANS_PDN_TO_CARDEMU_STEPS	15
++#define	RTL8703B_TRANS_ACT_TO_LPS_STEPS		15
++#define	RTL8703B_TRANS_LPS_TO_ACT_STEPS		15
++#define	RTL8703B_TRANS_END_STEPS		1
++
++
++#define RTL8703B_TRANS_CARDEMU_TO_ACT														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \
++	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/	\
++	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
++	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/	\
++	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */	\
++	{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 , BIT3},/* enabled usb resume */	\
++	{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 , 0},/* disable usb resume */	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
++	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	\
++	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/	\
++	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
++	{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
++	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
++	{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
++	{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
++	{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\
++	{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\
++
++
++#define RTL8703B_TRANS_ACT_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
++	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
++	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\
++	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
++	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
++
++
++#define RTL8703B_TRANS_CARDEMU_TO_SUS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
++
++#define RTL8703B_TRANS_SUS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
++
++#define RTL8703B_TRANS_CARDEMU_TO_CARDDIS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
++	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
++
++#define RTL8703B_TRANS_CARDDIS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
++
++
++#define RTL8703B_TRANS_CARDEMU_TO_PDN												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
++
++#define RTL8703B_TRANS_PDN_TO_CARDEMU												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
++
++#define RTL8703B_TRANS_ACT_TO_LPS														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
++	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
++	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
++	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
++
++
++#define RTL8703B_TRANS_LPS_TO_ACT															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
++	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
++	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
++	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
++	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
++
++#define RTL8703B_TRANS_END															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
++
++
++	extern WLAN_PWR_CFG rtl8703B_power_on_flow[RTL8703B_TRANS_CARDEMU_TO_ACT_STEPS + RTL8703B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8703B_radio_off_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8703B_card_disable_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8703B_card_enable_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8703B_suspend_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8703B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8703B_resume_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8703B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8703B_hwpdn_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8703B_enter_lps_flow[RTL8703B_TRANS_ACT_TO_LPS_STEPS + RTL8703B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8703B_leave_lps_flow[RTL8703B_TRANS_LPS_TO_ACT_STEPS + RTL8703B_TRANS_END_STEPS];
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8710BPhyCfg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8710BPhyCfg.h
+new file mode 100644
+index 000000000..3c5808e92
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8710BPhyCfg.h
+@@ -0,0 +1,111 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8710BPHYCFG_H__
++#define __INC_HAL8710BPHYCFG_H__
++
++/*--------------------------Define Parameters-------------------------------*/
++#define LOOP_LIMIT				5
++#define MAX_STALL_TIME			50		/* us */
++#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
++#define MAX_TXPWR_IDX_NMODE_92S	63
++#define Reset_Cnt_Limit			3
++
++#ifdef CONFIG_PCI_HCI
++	#define MAX_AGGR_NUM	0x0B
++#else
++	#define MAX_AGGR_NUM	0x07
++#endif /* CONFIG_PCI_HCI */
++
++
++/*--------------------------Define Parameters End-------------------------------*/
++
++
++/*------------------------------Define structure----------------------------*/
++
++/*------------------------------Define structure End----------------------------*/
++
++/*--------------------------Exported Function prototype---------------------*/
++u32
++PHY_QueryBBReg_8710B(
++		PADAPTER	Adapter,
++		u32		RegAddr,
++		u32		BitMask
++);
++
++void
++PHY_SetBBReg_8710B(
++		PADAPTER	Adapter,
++		u32		RegAddr,
++		u32		BitMask,
++		u32		Data
++);
++
++u32
++PHY_QueryRFReg_8710B(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				RegAddr,
++		u32				BitMask
++);
++
++void
++PHY_SetRFReg_8710B(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				RegAddr,
++		u32				BitMask,
++		u32				Data
++);
++
++/* MAC/BB/RF HAL config */
++int PHY_BBConfig8710B(PADAPTER	Adapter);
++
++int PHY_RFConfig8710B(PADAPTER	Adapter);
++
++s32 PHY_MACConfig8710B(PADAPTER padapter);
++
++int
++PHY_ConfigRFWithParaFile_8710B(
++		PADAPTER			Adapter,
++		u8				*pFileName,
++	enum rf_path				eRFPath
++);
++
++void
++PHY_SetTxPowerIndex_8710B(
++		PADAPTER			Adapter,
++		u32					PowerIndex,
++		enum rf_path			RFPath,
++		u8					Rate
++);
++
++void
++PHY_SetTxPowerLevel8710B(
++		PADAPTER		Adapter,
++		u8			channel
++);
++
++void
++PHY_SetSwChnlBWMode8710B(
++		PADAPTER			Adapter,
++		u8					channel,
++		enum channel_width	Bandwidth,
++		u8					Offset40,
++		u8					Offset80
++);
++
++/*--------------------------Exported Function prototype End---------------------*/
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8710BPhyReg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8710BPhyReg.h
+new file mode 100644
+index 000000000..337e03207
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8710BPhyReg.h
+@@ -0,0 +1,1134 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8710BPHYREG_H__
++#define __INC_HAL8710BPHYREG_H__
++
++#define		rSYM_WLBT_PAPE_SEL		0x64
++/*
++ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
++ * 3. RF register 0x00-2E
++ * 4. Bit Mask for BB/RF register
++ * 5. Other definition for BB/RF R/W
++ *   */
++
++
++/*
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 1. Page1(0x100)
++ *   */
++#define		rPMAC_Reset					0x100
++#define		rPMAC_TxStart					0x104
++#define		rPMAC_TxLegacySIG				0x108
++#define		rPMAC_TxHTSIG1				0x10c
++#define		rPMAC_TxHTSIG2				0x110
++#define		rPMAC_PHYDebug				0x114
++#define		rPMAC_TxPacketNum				0x118
++#define		rPMAC_TxIdle					0x11c
++#define		rPMAC_TxMACHeader0			0x120
++#define		rPMAC_TxMACHeader1			0x124
++#define		rPMAC_TxMACHeader2			0x128
++#define		rPMAC_TxMACHeader3			0x12c
++#define		rPMAC_TxMACHeader4			0x130
++#define		rPMAC_TxMACHeader5			0x134
++#define		rPMAC_TxDataType				0x138
++#define		rPMAC_TxRandomSeed			0x13c
++#define		rPMAC_CCKPLCPPreamble			0x140
++#define		rPMAC_CCKPLCPHeader			0x144
++#define		rPMAC_CCKCRC16				0x148
++#define		rPMAC_OFDMRxCRC32OK			0x170
++#define		rPMAC_OFDMRxCRC32Er			0x174
++#define		rPMAC_OFDMRxParityEr			0x178
++#define		rPMAC_OFDMRxCRC8Er			0x17c
++#define		rPMAC_CCKCRxRC16Er			0x180
++#define		rPMAC_CCKCRxRC32Er			0x184
++#define		rPMAC_CCKCRxRC32OK			0x188
++#define		rPMAC_TxStatus					0x18c
++
++/*
++ * 2. Page2(0x200)
++ *
++ * The following two definition are only used for USB interface. */
++#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
++#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
++
++/*
++ * 3. Page8(0x800)
++ *   */
++#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC // RF BW Setting?? */
++
++#define		rFPGA0_TxInfo				0x804	/* Status report?? */
++#define		rFPGA0_PSDFunction			0x808
++
++#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
++
++#define		rFPGA0_RFTiming1			0x810	/* Useless now */
++#define		rFPGA0_RFTiming2			0x814
++
++#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
++#define		rFPGA0_XA_HSSIParameter2		0x824
++#define		rFPGA0_XB_HSSIParameter1		0x828
++#define		rFPGA0_XB_HSSIParameter2		0x82c
++#define		rTxAGC_B_Rate18_06				0x830
++#define		rTxAGC_B_Rate54_24				0x834
++#define		rTxAGC_B_CCK1_55_Mcs32		0x838
++#define		rTxAGC_B_Mcs03_Mcs00			0x83c
++
++#define		rTxAGC_B_Mcs07_Mcs04			0x848
++#define		rTxAGC_B_Mcs11_Mcs08			0x84c
++
++#define		rFPGA0_XA_LSSIParameter		0x840
++#define		rFPGA0_XB_LSSIParameter		0x844
++
++#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
++#define		rFPGA0_RFSleepUpParameter		0x854
++
++#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
++#define		rFPGA0_XCD_SwitchControl		0x85c
++
++#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
++#define		rFPGA0_XB_RFInterfaceOE		0x864
++
++#define		rTxAGC_B_Mcs15_Mcs12			0x868
++#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
++
++#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
++#define		rFPGA0_XCD_RFInterfaceSW		0x874
++
++#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
++#define		rFPGA0_XCD_RFParameter		0x87c
++
++#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
++#define		rFPGA0_AnalogParameter2		0x884
++#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
++#define		rFPGA0_AnalogParameter4		0x88c
++
++#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
++#define		rFPGA0_XB_LSSIReadBack		0x8a4
++#define		rFPGA0_XC_LSSIReadBack		0x8a8
++#define		rFPGA0_XD_LSSIReadBack		0x8ac
++
++#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
++#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
++#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
++#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now // RF Interface Readback Value */
++#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
++
++/*
++ * 4. Page9(0x900)
++ *   */
++#define	rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC // RF BW Setting?? */
++#define	rFPGA1_TxBlock				0x904	/* Useless now */
++#define	rFPGA1_DebugSelect			0x908	/* Useless now */
++#define	rFPGA1_TxInfo				0x90c	/* Useless now // Status report?? */
++#define	rDPDT_control				0x92c
++#define	rfe_ctrl_anta_src				0x930
++#define	rS0S1_PathSwitch			0x948
++#define	rBBrx_DFIR					0x954
++
++/*
++ * 5. PageA(0xA00)
++ *
++ * Set Control channel to upper or lower. These settings are required only for 40MHz */
++#define		rCCK0_System				0xa00
++
++#define		rCCK0_AFESetting			0xa04	/* Disable init gain now // Select RX path by RSSI */
++#define		rCCK0_CCA					0xa08	/* Disable init gain now // Init gain */
++
++#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
++#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
++
++#define		rCCK0_RxHP					0xa14
++
++#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
++#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
++
++#define		rCCK0_TxFilter1				0xa20
++#define		rCCK0_TxFilter2				0xa24
++#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
++#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
++#define		rCCK0_TRSSIReport		0xa50
++#define		rCCK0_RxReport			0xa54  /* 0xa57 */
++#define		rCCK0_FACounterLower		0xa5c  /* 0xa5b */
++#define		rCCK0_FACounterUpper		0xa58  /* 0xa5c */
++
++/*
++ * PageB(0xB00)
++ *   */
++#define rPdp_AntA						0xb00
++#define rPdp_AntA_4						0xb04
++#define rPdp_AntA_8						0xb08
++#define rPdp_AntA_C						0xb0c
++#define rPdp_AntA_10					0xb10
++#define rPdp_AntA_14					0xb14
++#define rPdp_AntA_18					0xb18
++#define rPdp_AntA_1C					0xb1c
++#define rPdp_AntA_20					0xb20
++#define rPdp_AntA_24					0xb24
++
++#define rConfig_Pmpd_AntA				0xb28
++#define rConfig_ram64x16				0xb2c
++
++#define rBndA							0xb30
++#define rHssiPar						0xb34
++
++#define rConfig_AntA					0xb68
++#define rConfig_AntB					0xb6c
++
++#define rPdp_AntB						0xb70
++#define rPdp_AntB_4						0xb74
++#define rPdp_AntB_8						0xb78
++#define rPdp_AntB_C						0xb7c
++#define rPdp_AntB_10					0xb80
++#define rPdp_AntB_14					0xb84
++#define rPdp_AntB_18					0xb88
++#define rPdp_AntB_1C					0xb8c
++#define rPdp_AntB_20					0xb90
++#define rPdp_AntB_24					0xb94
++
++#define rConfig_Pmpd_AntB				0xb98
++
++#define rBndB							0xba0
++
++#define rAPK							0xbd8
++#define rPm_Rx0_AntA					0xbdc
++#define rPm_Rx1_AntA					0xbe0
++#define rPm_Rx2_AntA					0xbe4
++#define rPm_Rx3_AntA					0xbe8
++#define rPm_Rx0_AntB					0xbec
++#define rPm_Rx1_AntB					0xbf0
++#define rPm_Rx2_AntB					0xbf4
++#define rPm_Rx3_AntB					0xbf8
++/*
++ * 6. PageC(0xC00)
++ *   */
++#define		rOFDM0_LSTF				0xc00
++
++#define		rOFDM0_TRxPathEnable		0xc04
++#define		rOFDM0_TRMuxPar			0xc08
++#define		rOFDM0_TRSWIsolation		0xc0c
++
++#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
++#define		rOFDM0_XARxIQImbalance		0xc14  /* RxIQ imbalance matrix */
++#define		rOFDM0_XBRxAFE		0xc18
++#define		rOFDM0_XBRxIQImbalance	0xc1c
++#define		rOFDM0_XCRxAFE		0xc20
++#define		rOFDM0_XCRxIQImbalance	0xc24
++#define		rOFDM0_XDRxAFE		0xc28
++#define		rOFDM0_XDRxIQImbalance	0xc2c
++
++#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	// DM tune init gain */
++#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
++#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
++#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
++
++#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
++#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
++#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
++#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
++
++#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
++#define		rOFDM0_XAAGCCore2			0xc54
++#define		rOFDM0_XBAGCCore1			0xc58
++#define		rOFDM0_XBAGCCore2			0xc5c
++#define		rOFDM0_XCAGCCore1			0xc60
++#define		rOFDM0_XCAGCCore2			0xc64
++#define		rOFDM0_XDAGCCore1			0xc68
++#define		rOFDM0_XDAGCCore2			0xc6c
++
++#define		rOFDM0_AGCParameter1			0xc70
++#define		rOFDM0_AGCParameter2			0xc74
++#define		rOFDM0_AGCRSSITable			0xc78
++#define		rOFDM0_HTSTFAGC				0xc7c
++
++#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
++#define		rOFDM0_XATxAFE				0xc84
++#define		rOFDM0_XBTxIQImbalance		0xc88
++#define		rOFDM0_XBTxAFE				0xc8c
++#define		rOFDM0_XCTxIQImbalance		0xc90
++#define		rOFDM0_XCTxAFE			0xc94
++#define		rOFDM0_XDTxIQImbalance		0xc98
++#define		rOFDM0_XDTxAFE				0xc9c
++
++#define		rOFDM0_RxIQExtAnta			0xca0
++#define		rOFDM0_TxCoeff1				0xca4
++#define		rOFDM0_TxCoeff2				0xca8
++#define		rOFDM0_TxCoeff3				0xcac
++#define		rOFDM0_TxCoeff4				0xcb0
++#define		rOFDM0_TxCoeff5				0xcb4
++#define		rOFDM0_TxCoeff6				0xcb8
++#define		rOFDM0_RxHPParameter			0xce0
++#define		rOFDM0_TxPseudoNoiseWgt		0xce4
++#define		rOFDM0_FrameSync				0xcf0
++#define		rOFDM0_DFSReport				0xcf4
++
++/*
++ * 7. PageD(0xD00)
++ *   */
++#define		rOFDM1_LSTF					0xd00
++#define		rOFDM1_TRxPathEnable			0xd04
++
++#define		rOFDM1_CFO						0xd08	/* No setting now */
++#define		rOFDM1_CSI1					0xd10
++#define		rOFDM1_SBD						0xd14
++#define		rOFDM1_CSI2					0xd18
++#define		rOFDM1_CFOTracking			0xd2c
++#define		rOFDM1_TRxMesaure1			0xd34
++#define		rOFDM1_IntfDet					0xd3c
++#define		rOFDM1_PseudoNoiseStateAB		0xd50
++#define		rOFDM1_PseudoNoiseStateCD		0xd54
++#define		rOFDM1_RxPseudoNoiseWgt		0xd58
++
++#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
++#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
++#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
++
++#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
++#define		rOFDM_ShortCFOCD				0xdb0
++#define		rOFDM_LongCFOAB				0xdb4
++#define		rOFDM_LongCFOCD				0xdb8
++#define		rOFDM_TailCFOAB				0xdbc
++#define		rOFDM_TailCFOCD				0xdc0
++#define		rOFDM_PWMeasure1		0xdc4
++#define		rOFDM_PWMeasure2		0xdc8
++#define		rOFDM_BWReport				0xdcc
++#define		rOFDM_AGCReport				0xdd0
++#define		rOFDM_RxSNR					0xdd4
++#define		rOFDM_RxEVMCSI				0xdd8
++#define		rOFDM_SIGReport				0xddc
++
++
++/*
++ * 8. PageE(0xE00)
++ *   */
++#define		rTxAGC_A_Rate18_06			0xe00
++#define		rTxAGC_A_Rate54_24			0xe04
++#define		rTxAGC_A_CCK1_Mcs32			0xe08
++#define		rTxAGC_A_Mcs03_Mcs00			0xe10
++#define		rTxAGC_A_Mcs07_Mcs04			0xe14
++#define		rTxAGC_A_Mcs11_Mcs08			0xe18
++#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
++
++#define		rFPGA0_IQK					0xe28
++#define		rTx_IQK_Tone_A				0xe30
++#define		rRx_IQK_Tone_A				0xe34
++#define		rTx_IQK_PI_A					0xe38
++#define		rRx_IQK_PI_A					0xe3c
++
++#define		rTx_IQK						0xe40
++#define		rRx_IQK						0xe44
++#define		rIQK_AGC_Pts					0xe48
++#define		rIQK_AGC_Rsp					0xe4c
++#define		rTx_IQK_Tone_B				0xe50
++#define		rRx_IQK_Tone_B				0xe54
++#define		rTx_IQK_PI_B					0xe58
++#define		rRx_IQK_PI_B					0xe5c
++#define		rIQK_AGC_Cont				0xe60
++
++#define		rBlue_Tooth					0xe6c
++#define		rRx_Wait_CCA					0xe70
++#define		rTx_CCK_RFON					0xe74
++#define		rTx_CCK_BBON				0xe78
++#define		rTx_OFDM_RFON				0xe7c
++#define		rTx_OFDM_BBON				0xe80
++#define		rTx_To_Rx					0xe84
++#define		rTx_To_Tx					0xe88
++#define		rRx_CCK						0xe8c
++
++#define		rTx_Power_Before_IQK_A		0xe94
++#define		rTx_Power_After_IQK_A			0xe9c
++
++#define		rRx_Power_Before_IQK_A		0xea0
++#define		rRx_Power_Before_IQK_A_2		0xea4
++#define		rRx_Power_After_IQK_A			0xea8
++#define		rRx_Power_After_IQK_A_2		0xeac
++
++#define		rTx_Power_Before_IQK_B		0xeb4
++#define		rTx_Power_After_IQK_B			0xebc
++
++#define		rRx_Power_Before_IQK_B		0xec0
++#define		rRx_Power_Before_IQK_B_2		0xec4
++#define		rRx_Power_After_IQK_B			0xec8
++#define		rRx_Power_After_IQK_B_2		0xecc
++
++#define		rRx_OFDM					0xed0
++#define		rRx_Wait_RIFS				0xed4
++#define		rRx_TO_Rx					0xed8
++#define		rStandby						0xedc
++#define		rSleep						0xee0
++#define		rPMPD_ANAEN				0xeec
++
++/*
++ * 7. RF Register 0x00-0x2E (RF 8256)
++ * RF-0222D 0x00-3F
++ *
++ * Zebra1 */
++#define		rZebra1_HSSIEnable				0x0	/* Useless now */
++#define		rZebra1_TRxEnable1				0x1
++#define		rZebra1_TRxEnable2				0x2
++#define		rZebra1_AGC					0x4
++#define		rZebra1_ChargePump			0x5
++#define		rZebra1_Channel				0x7	/* RF channel switch */
++
++/* #endif */
++#define		rZebra1_TxGain					0x8	/* Useless now */
++#define		rZebra1_TxLPF					0x9
++#define		rZebra1_RxLPF					0xb
++#define		rZebra1_RxHPFCorner			0xc
++
++/* Zebra4 */
++#define		rGlobalCtrl						0	/* Useless now */
++#define		rRTL8256_TxLPF					19
++#define		rRTL8256_RxLPF					11
++
++/* RTL8258 */
++#define		rRTL8258_TxLPF					0x11	/* Useless now */
++#define		rRTL8258_RxLPF					0x13
++#define		rRTL8258_RSSILPF				0xa
++
++/*
++ * RL6052 Register definition
++ *   */
++#define		RF_AC						0x00	/* */
++
++#define		RF_IQADJ_G1				0x01	/* */
++#define		RF_IQADJ_G2				0x02	/* */
++#define		RF_BS_PA_APSET_G1_G4		0x03
++#define		RF_BS_PA_APSET_G5_G8		0x04
++#define		RF_POW_TRSW				0x05	/* */
++
++#define		RF_GAIN_RX					0x06	/* */
++#define		RF_GAIN_TX					0x07	/* */
++
++#define		RF_TXM_IDAC				0x08	/* */
++#define		RF_IPA_G					0x09	/* */
++#define		RF_TXBIAS_G				0x0A
++#define		RF_TXPA_AG					0x0B
++#define		RF_IPA_A					0x0C	/* */
++#define		RF_TXBIAS_A				0x0D
++#define		RF_BS_PA_APSET_G9_G11	0x0E
++#define		RF_BS_IQGEN				0x0F	/* */
++
++#define		RF_MODE1					0x10	/* */
++#define		RF_MODE2					0x11	/* */
++
++#define		RF_RX_AGC_HP				0x12	/* */
++#define		RF_TX_AGC					0x13	/* */
++#define		RF_BIAS						0x14	/* */
++#define		RF_IPA						0x15	/* */
++#define		RF_TXBIAS					0x16
++#define		RF_POW_ABILITY			0x17	/* */
++#define		RF_MODE_AG				0x18	/* */
++#define		rRfChannel					0x18	/* RF channel and BW switch */
++#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
++#define		RF_TOP						0x19	/* */
++
++#define		RF_RX_G1					0x1A	/* */
++#define		RF_RX_G2					0x1B	/* */
++
++#define		RF_RX_BB2					0x1C	/* */
++#define		RF_RX_BB1					0x1D	/* */
++
++#define		RF_RCK1					0x1E	/* */
++#define		RF_RCK2					0x1F	/* */
++
++#define		RF_TX_G1					0x20	/* */
++#define		RF_TX_G2					0x21	/* */
++#define		RF_TX_G3					0x22	/* */
++
++#define		RF_TX_BB1					0x23	/* */
++
++#define		RF_T_METER					0x24	/* */
++
++#define		RF_SYN_G1					0x25	/* RF TX Power control */
++#define		RF_SYN_G2					0x26	/* RF TX Power control */
++#define		RF_SYN_G3					0x27	/* RF TX Power control */
++#define		RF_SYN_G4					0x28	/* RF TX Power control */
++#define		RF_SYN_G5					0x29	/* RF TX Power control */
++#define		RF_SYN_G6					0x2A	/* RF TX Power control */
++#define		RF_SYN_G7					0x2B	/* RF TX Power control */
++#define		RF_SYN_G8					0x2C	/* RF TX Power control */
++
++#define		RF_RCK_OS					0x30	/* RF TX PA control */
++
++#define		RF_TXPA_G1					0x31	/* RF TX PA control */
++#define		RF_TXPA_G2					0x32	/* RF TX PA control */
++#define		RF_TXPA_G3					0x33	/* RF TX PA control */
++#define	RF_TX_BIAS_A				0x35
++#define	RF_TX_BIAS_D				0x36
++#define	RF_LOBF_9					0x38
++#define	RF_RXRF_A3					0x3C	/*	 */
++#define	RF_TRSW					0x3F
++
++#define	RF_TXRF_A2					0x41
++#define	RF_T_METER_88E				0x42
++#define	RF_TXPA_G4					0x46
++#define	RF_TXPA_A4					0x4B
++#define	RF_0x52					0x52
++#define	RF_WE_LUT					0xEF
++#define	RF_S0S1					0xB0
++
++/*
++ * Bit Mask
++ *
++ * 1. Page1(0x100) */
++#define		bBBResetB						0x100	/* Useless now? */
++#define		bGlobalResetB					0x200
++#define		bOFDMTxStart					0x4
++#define		bCCKTxStart						0x8
++#define		bCRC32Debug					0x100
++#define		bPMACLoopback					0x10
++#define		bTxLSIG							0xffffff
++#define		bOFDMTxRate					0xf
++#define		bOFDMTxReserved				0x10
++#define		bOFDMTxLength					0x1ffe0
++#define		bOFDMTxParity					0x20000
++#define		bTxHTSIG1						0xffffff
++#define		bTxHTMCSRate					0x7f
++#define		bTxHTBW						0x80
++#define		bTxHTLength					0xffff00
++#define		bTxHTSIG2						0xffffff
++#define		bTxHTSmoothing					0x1
++#define		bTxHTSounding					0x2
++#define		bTxHTReserved					0x4
++#define		bTxHTAggreation				0x8
++#define		bTxHTSTBC						0x30
++#define		bTxHTAdvanceCoding			0x40
++#define		bTxHTShortGI					0x80
++#define		bTxHTNumberHT_LTF			0x300
++#define		bTxHTCRC8						0x3fc00
++#define		bCounterReset					0x10000
++#define		bNumOfOFDMTx					0xffff
++#define		bNumOfCCKTx					0xffff0000
++#define		bTxIdleInterval					0xffff
++#define		bOFDMService					0xffff0000
++#define		bTxMACHeader					0xffffffff
++#define		bTxDataInit						0xff
++#define		bTxHTMode						0x100
++#define		bTxDataType					0x30000
++#define		bTxRandomSeed					0xffffffff
++#define		bCCKTxPreamble					0x1
++#define		bCCKTxSFD						0xffff0000
++#define		bCCKTxSIG						0xff
++#define		bCCKTxService					0xff00
++#define		bCCKLengthExt					0x8000
++#define		bCCKTxLength					0xffff0000
++#define		bCCKTxCRC16					0xffff
++#define		bCCKTxStatus					0x1
++#define		bOFDMTxStatus					0x2
++
++#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
++#define		RF_TX_GAIN_OFFSET_8710B(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0))
++
++/* 2. Page8(0x800) */
++#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
++#define		bJapanMode						0x2
++#define		bCCKTxSC						0x30
++#define		bCCKEn							0x1000000
++#define		bOFDMEn						0x2000000
++
++#define		bOFDMRxADCPhase           0x10000	/* Useless now */
++#define		bOFDMTxDACPhase		0x40000
++#define		bXATxAGC			0x3f
++
++#define		bAntennaSelect		0x0300
++
++#define		bXBTxAGC                 0xf00	/* Reg 80c rFPGA0_TxGainStage */
++#define		bXCTxAGC			0xf000
++#define		bXDTxAGC			0xf0000
++
++#define		bPAStart                 0xf0000000	/* Useless now */
++#define		bTRStart			0x00f00000
++#define		bRFStart			0x0000f000
++#define		bBBStart			0x000000f0
++#define		bBBCCKStart		0x0000000f
++#define		bPAEnd                    0xf          /* Reg0x814 */
++#define		bTREnd			0x0f000000
++#define		bRFEnd			0x000f0000
++#define		bCCAMask                  0x000000f0   /* T2R */
++#define		bR2RCCAMask		0x00000f00
++#define		bHSSI_R2TDelay		0xf8000000
++#define		bHSSI_T2RDelay		0xf80000
++#define		bContTxHSSI              0x400     /* chane gain at continue Tx */
++#define		bIGFromCCK		0x200
++#define		bAGCAddress		0x3f
++#define		bRxHPTx			0x7000
++#define		bRxHPT2R			0x38000
++#define		bRxHPCCKIni		0xc0000
++#define		bAGCTxCode		0xc00000
++#define		bAGCRxCode		0x300000
++
++#define		b3WireDataLength         0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
++#define		b3WireAddressLength		0x400
++
++#define		b3WireRFPowerDown         0x1	/* Useless now
++ * #define bHWSISelect		0x8 */
++#define		b5GPAPEPolarity		0x40000000
++#define		b2GPAPEPolarity		0x80000000
++#define		bRFSW_TxDefaultAnt		0x3
++#define		bRFSW_TxOptionAnt		0x30
++#define		bRFSW_RxDefaultAnt		0x300
++#define		bRFSW_RxOptionAnt		0x3000
++#define		bRFSI_3WireData		0x1
++#define		bRFSI_3WireClock		0x2
++#define		bRFSI_3WireLoad		0x4
++#define		bRFSI_3WireRW		0x8
++#define		bRFSI_3Wire			0xf
++
++#define		bRFSI_RFENV              0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
++
++#define		bRFSI_TRSW               0x20	/* Useless now */
++#define		bRFSI_TRSWB		0x40
++#define		bRFSI_ANTSW		0x100
++#define		bRFSI_ANTSWB		0x200
++#define		bRFSI_PAPE			0x400
++#define		bRFSI_PAPE5G		0x800
++#define		bBandSelect			0x1
++#define		bHTSIG2_GI			0x80
++#define		bHTSIG2_Smoothing		0x01
++#define		bHTSIG2_Sounding		0x02
++#define		bHTSIG2_Aggreaton		0x08
++#define		bHTSIG2_STBC		0x30
++#define		bHTSIG2_AdvCoding		0x40
++#define		bHTSIG2_NumOfHTLTF	0x300
++#define		bHTSIG2_CRC8		0x3fc
++#define		bHTSIG1_MCS		0x7f
++#define		bHTSIG1_BandWidth		0x80
++#define		bHTSIG1_HTLength		0xffff
++#define		bLSIG_Rate			0xf
++#define		bLSIG_Reserved		0x10
++#define		bLSIG_Length		0x1fffe
++#define		bLSIG_Parity			0x20
++#define		bCCKRxPhase		0x4
++
++#define		bLSSIReadAddress          0x7f800000   /* T65 RF */
++
++#define		bLSSIReadEdge             0x80000000   /* LSSI "Read" edge signal */
++
++#define		bLSSIReadBackData         0xfffff		/* T65 RF */
++
++#define		bLSSIReadOKFlag           0x1000	/* Useless now */
++#define		bCCKSampleRate            0x8       /* 0: 44MHz, 1:88MHz     */
++#define		bRegulator0Standby		0x1
++#define		bRegulatorPLLStandby		0x2
++#define		bRegulator1Standby		0x4
++#define		bPLLPowerUp		0x8
++#define		bDPLLPowerUp		0x10
++#define		bDA10PowerUp		0x20
++#define		bAD7PowerUp		0x200
++#define		bDA6PowerUp		0x2000
++#define		bXtalPowerUp		0x4000
++#define		b40MDClkPowerUP		0x8000
++#define		bDA6DebugMode		0x20000
++#define		bDA6Swing			0x380000
++
++#define		bADClkPhase               0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
++
++#define		b80MClkDelay              0x18000000	/* Useless */
++#define		bAFEWatchDogEnable		0x20000000
++
++#define		bXtalCap01                0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
++#define		bXtalCap23			0x3
++#define		bXtalCap92x					0x0f000000
++#define		bXtalCap			0x0f000000
++
++#define		bIntDifClkEnable          0x400	/* Useless */
++#define		bExtSigClkEnable		0x800
++#define		bBandgapMbiasPowerUp	0x10000
++#define		bAD11SHGain		0xc0000
++#define		bAD11InputRange		0x700000
++#define		bAD11OPCurrent		0x3800000
++#define		bIPathLoopback		0x4000000
++#define		bQPathLoopback		0x8000000
++#define		bAFELoopback		0x10000000
++#define		bDA10Swing		0x7e0
++#define		bDA10Reverse		0x800
++#define		bDAClkSource		0x1000
++#define		bAD7InputRange		0x6000
++#define		bAD7Gain			0x38000
++#define		bAD7OutputCMMode		0x40000
++#define		bAD7InputCMMode		0x380000
++#define		bAD7Current			0xc00000
++#define		bRegulatorAdjust		0x7000000
++#define		bAD11PowerUpAtTx		0x1
++#define		bDA10PSAtTx		0x10
++#define		bAD11PowerUpAtRx		0x100
++#define		bDA10PSAtRx		0x1000
++#define		bCCKRxAGCFormat		0x200
++#define		bPSDFFTSamplepPoint		0xc000
++#define		bPSDAverageNum		0x3000
++#define		bIQPathControl		0xc00
++#define		bPSDFreq			0x3ff
++#define		bPSDAntennaPath		0x30
++#define		bPSDIQSwitch		0x40
++#define		bPSDRxTrigger		0x400000
++#define		bPSDTxTrigger		0x80000000
++#define		bPSDSineToneScale		0x7f000000
++#define		bPSDReport			0xffff
++
++/* 3. Page9(0x900) */
++#define		bOFDMTxSC                 0x30000000	/* Useless */
++#define		bCCKTxOn			0x1
++#define		bOFDMTxOn		0x2
++#define		bDebugPage                0xfff  /* reset debug page and also HWord, LWord */
++#define		bDebugItem                0xff   /* reset debug page and LWord */
++#define		bAntL			0x10
++#define		bAntNonHT				0x100
++#define		bAntHT1			0x1000
++#define		bAntHT2			0x10000
++#define		bAntHT1S1			0x100000
++#define		bAntNonHTS1		0x1000000
++
++/* 4. PageA(0xA00) */
++#define		bCCKBBMode				0x3	/* Useless */
++#define		bCCKTxPowerSaving		0x80
++#define		bCCKRxPowerSaving		0x40
++
++#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
++
++#define		bCCKScramble			0x8	/* Useless */
++#define		bCCKAntDiversity		0x8000
++#define		bCCKCarrierRecovery		0x4000
++#define		bCCKTxRate				0x3000
++#define		bCCKDCCancel			0x0800
++#define		bCCKISICancel			0x0400
++#define		bCCKMatchFilter			0x0200
++#define		bCCKEqualizer			0x0100
++#define		bCCKPreambleDetect		0x800000
++#define		bCCKFastFalseCCA		0x400000
++#define		bCCKChEstStart			0x300000
++#define		bCCKCCACount			0x080000
++#define		bCCKcs_lim				0x070000
++#define		bCCKBistMode			0x80000000
++#define		bCCKCCAMask			0x40000000
++#define		bCCKTxDACPhase		0x4
++#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
++#define		bCCKr_cp_mode0		0x0100
++#define		bCCKTxDCOffset			0xf0
++#define		bCCKRxDCOffset			0xf
++#define		bCCKCCAMode			0xc000
++#define		bCCKFalseCS_lim			0x3f00
++#define		bCCKCS_ratio			0xc00000
++#define		bCCKCorgBit_sel			0x300000
++#define		bCCKPD_lim				0x0f0000
++#define		bCCKNewCCA			0x80000000
++#define		bCCKRxHPofIG			0x8000
++#define		bCCKRxIG				0x7f00
++#define		bCCKLNAPolarity			0x800000
++#define		bCCKRx1stGain			0x7f0000
++#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
++#define		bCCKRxAGCSatLevel		0x1f000000
++#define		bCCKRxAGCSatCount		0xe0
++#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
++#define		bCCKFixedRxAGC			0x8000
++/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
++#define		bCCKAntennaPolarity		0x2000
++#define		bCCKTxFilterType		0x0c00
++#define		bCCKRxAGCReportType	0x0300
++#define		bCCKRxDAGCEn			0x80000000
++#define		bCCKRxDAGCPeriod		0x20000000
++#define		bCCKRxDAGCSatLevel		0x1f000000
++#define		bCCKTimingRecovery		0x800000
++#define		bCCKTxC0				0x3f0000
++#define		bCCKTxC1				0x3f000000
++#define		bCCKTxC2				0x3f
++#define		bCCKTxC3				0x3f00
++#define		bCCKTxC4				0x3f0000
++#define		bCCKTxC5				0x3f000000
++#define		bCCKTxC6				0x3f
++#define		bCCKTxC7				0x3f00
++#define		bCCKDebugPort			0xff0000
++#define		bCCKDACDebug			0x0f000000
++#define		bCCKFalseAlarmEnable	0x8000
++#define		bCCKFalseAlarmRead		0x4000
++#define		bCCKTRSSI				0x7f
++#define		bCCKRxAGCReport		0xfe
++#define		bCCKRxReport_AntSel	0x80000000
++#define		bCCKRxReport_MFOff		0x40000000
++#define		bCCKRxRxReport_SQLoss	0x20000000
++#define		bCCKRxReport_Pktloss	0x10000000
++#define		bCCKRxReport_Lockedbit	0x08000000
++#define		bCCKRxReport_RateError	0x04000000
++#define		bCCKRxReport_RxRate	0x03000000
++#define		bCCKRxFACounterLower	0xff
++#define		bCCKRxFACounterUpper	0xff000000
++#define		bCCKRxHPAGCStart		0xe000
++#define		bCCKRxHPAGCFinal		0x1c00
++#define		bCCKRxFalseAlarmEnable	0x8000
++#define		bCCKFACounterFreeze	0x4000
++#define		bCCKTxPathSel			0x10000000
++#define		bCCKDefaultRxPath		0xc000000
++#define		bCCKOptionRxPath		0x3000000
++
++/* 5. PageC(0xC00) */
++#define		bNumOfSTF				0x3	/* Useless */
++#define		bShift_L					0xc0
++#define		bGI_TH					0xc
++#define		bRxPathA				0x1
++#define		bRxPathB				0x2
++#define		bRxPathC				0x4
++#define		bRxPathD				0x8
++#define		bTxPathA				0x1
++#define		bTxPathB				0x2
++#define		bTxPathC				0x4
++#define		bTxPathD				0x8
++#define		bTRSSIFreq				0x200
++#define		bADCBackoff				0x3000
++#define		bDFIRBackoff			0xc000
++#define		bTRSSILatchPhase		0x10000
++#define		bRxIDCOffset			0xff
++#define		bRxQDCOffset			0xff00
++#define		bRxDFIRMode			0x1800000
++#define		bRxDCNFType			0xe000000
++#define		bRXIQImb_A				0x3ff
++#define		bRXIQImb_B				0xfc00
++#define		bRXIQImb_C				0x3f0000
++#define		bRXIQImb_D				0xffc00000
++#define		bDC_dc_Notch			0x60000
++#define		bRxNBINotch			0x1f000000
++#define		bPD_TH					0xf
++#define		bPD_TH_Opt2			0xc000
++#define		bPWED_TH				0x700
++#define		bIfMF_Win_L			0x800
++#define		bPD_Option				0x1000
++#define		bMF_Win_L				0xe000
++#define		bBW_Search_L			0x30000
++#define		bwin_enh_L				0xc0000
++#define		bBW_TH					0x700000
++#define		bED_TH2				0x3800000
++#define		bBW_option				0x4000000
++#define		bRatio_TH				0x18000000
++#define		bWindow_L				0xe0000000
++#define		bSBD_Option				0x1
++#define		bFrame_TH				0x1c
++#define		bFS_Option				0x60
++#define		bDC_Slope_check		0x80
++#define		bFGuard_Counter_DC_L	0xe00
++#define		bFrame_Weight_Short	0x7000
++#define		bSub_Tune				0xe00000
++#define		bFrame_DC_Length		0xe000000
++#define		bSBD_start_offset		0x30000000
++#define		bFrame_TH_2			0x7
++#define		bFrame_GI2_TH			0x38
++#define		bGI2_Sync_en			0x40
++#define		bSarch_Short_Early		0x300
++#define		bSarch_Short_Late		0xc00
++#define		bSarch_GI2_Late		0x70000
++#define		bCFOAntSum				0x1
++#define		bCFOAcc				0x2
++#define		bCFOStartOffset			0xc
++#define		bCFOLookBack			0x70
++#define		bCFOSumWeight			0x80
++#define		bDAGCEnable			0x10000
++#define		bTXIQImb_A				0x3ff
++#define		bTXIQImb_B				0xfc00
++#define		bTXIQImb_C				0x3f0000
++#define		bTXIQImb_D				0xffc00000
++#define		bTxIDCOffset			0xff
++#define		bTxQDCOffset			0xff00
++#define		bTxDFIRMode			0x10000
++#define		bTxPesudoNoiseOn		0x4000000
++#define		bTxPesudoNoise_A		0xff
++#define		bTxPesudoNoise_B		0xff00
++#define		bTxPesudoNoise_C		0xff0000
++#define		bTxPesudoNoise_D		0xff000000
++#define		bCCADropOption			0x20000
++#define		bCCADropThres			0xfff00000
++#define		bEDCCA_H				0xf
++#define		bEDCCA_L				0xf0
++#define		bLambda_ED			0x300
++#define		bRxInitialGain			0x7f
++#define		bRxAntDivEn				0x80
++#define		bRxAGCAddressForLNA	0x7f00
++#define		bRxHighPowerFlow		0x8000
++#define		bRxAGCFreezeThres		0xc0000
++#define		bRxFreezeStep_AGC1	0x300000
++#define		bRxFreezeStep_AGC2	0xc00000
++#define		bRxFreezeStep_AGC3	0x3000000
++#define		bRxFreezeStep_AGC0	0xc000000
++#define		bRxRssi_Cmp_En			0x10000000
++#define		bRxQuickAGCEn			0x20000000
++#define		bRxAGCFreezeThresMode	0x40000000
++#define		bRxOverFlowCheckType	0x80000000
++#define		bRxAGCShift				0x7f
++#define		bTRSW_Tri_Only			0x80
++#define		bPowerThres			0x300
++#define		bRxAGCEn				0x1
++#define		bRxAGCTogetherEn		0x2
++#define		bRxAGCMin				0x4
++#define		bRxHP_Ini				0x7
++#define		bRxHP_TRLNA			0x70
++#define		bRxHP_RSSI				0x700
++#define		bRxHP_BBP1				0x7000
++#define		bRxHP_BBP2				0x70000
++#define		bRxHP_BBP3				0x700000
++#define		bRSSI_H					0x7f0000     /* the threshold for high power */
++#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
++#define		bRxSettle_TRSW			0x7
++#define		bRxSettle_LNA			0x38
++#define		bRxSettle_RSSI			0x1c0
++#define		bRxSettle_BBP			0xe00
++#define		bRxSettle_RxHP			0x7000
++#define		bRxSettle_AntSW_RSSI	0x38000
++#define		bRxSettle_AntSW		0xc0000
++#define		bRxProcessTime_DAGC	0x300000
++#define		bRxSettle_HSSI			0x400000
++#define		bRxProcessTime_BBPPW	0x800000
++#define		bRxAntennaPowerShift	0x3000000
++#define		bRSSITableSelect		0xc000000
++#define		bRxHP_Final				0x7000000
++#define		bRxHTSettle_BBP			0x7
++#define		bRxHTSettle_HSSI		0x8
++#define		bRxHTSettle_RxHP		0x70
++#define		bRxHTSettle_BBPPW		0x80
++#define		bRxHTSettle_Idle		0x300
++#define		bRxHTSettle_Reserved	0x1c00
++#define		bRxHTRxHPEn			0x8000
++#define		bRxHTAGCFreezeThres	0x30000
++#define		bRxHTAGCTogetherEn	0x40000
++#define		bRxHTAGCMin			0x80000
++#define		bRxHTAGCEn				0x100000
++#define		bRxHTDAGCEn			0x200000
++#define		bRxHTRxHP_BBP			0x1c00000
++#define		bRxHTRxHP_Final		0xe0000000
++#define		bRxPWRatioTH			0x3
++#define		bRxPWRatioEn			0x4
++#define		bRxMFHold				0x3800
++#define		bRxPD_Delay_TH1		0x38
++#define		bRxPD_Delay_TH2		0x1c0
++#define		bRxPD_DC_COUNT_MAX	0x600
++/* #define bRxMF_Hold               0x3800 */
++#define		bRxPD_Delay_TH			0x8000
++#define		bRxProcess_Delay		0xf0000
++#define		bRxSearchrange_GI2_Early	0x700000
++#define		bRxFrame_Guard_Counter_L	0x3800000
++#define		bRxSGI_Guard_L			0xc000000
++#define		bRxSGI_Search_L		0x30000000
++#define		bRxSGI_TH				0xc0000000
++#define		bDFSCnt0				0xff
++#define		bDFSCnt1				0xff00
++#define		bDFSFlag				0xf0000
++#define		bMFWeightSum			0x300000
++#define		bMinIdxTH				0x7f000000
++#define		bDAFormat				0x40000
++#define		bTxChEmuEnable		0x01000000
++#define		bTRSWIsolation_A		0x7f
++#define		bTRSWIsolation_B		0x7f00
++#define		bTRSWIsolation_C		0x7f0000
++#define		bTRSWIsolation_D		0x7f000000
++#define		bExtLNAGain				0x7c00
++
++/* 6. PageE(0xE00) */
++#define		bSTBCEn				0x4	/* Useless */
++#define		bAntennaMapping		0x10
++#define		bNss					0x20
++#define		bCFOAntSumD			0x200
++#define		bPHYCounterReset		0x8000000
++#define		bCFOReportGet			0x4000000
++#define		bOFDMContinueTx		0x10000000
++#define		bOFDMSingleCarrier		0x20000000
++#define		bOFDMSingleTone		0x40000000
++/* #define bRxPath1                 0x01 */
++/* #define bRxPath2                 0x02 */
++/* #define bRxPath3                 0x04 */
++/* #define bRxPath4                 0x08 */
++/* #define bTxPath1                 0x10 */
++/* #define bTxPath2                 0x20 */
++#define		bHTDetect			0x100
++#define		bCFOEn				0x10000
++#define		bCFOValue			0xfff00000
++#define		bSigTone_Re		0x3f
++#define		bSigTone_Im		0x7f00
++#define		bCounter_CCA		0xffff
++#define		bCounter_ParityFail	0xffff0000
++#define		bCounter_RateIllegal		0xffff
++#define		bCounter_CRC8Fail	0xffff0000
++#define		bCounter_MCSNoSupport	0xffff
++#define		bCounter_FastSync	0xffff
++#define		bShortCFO			0xfff
++#define		bShortCFOTLength	12   /* total */
++#define		bShortCFOFLength	11   /* fraction */
++#define		bLongCFO			0x7ff
++#define		bLongCFOTLength	11
++#define		bLongCFOFLength	11
++#define		bTailCFO			0x1fff
++#define		bTailCFOTLength		13
++#define		bTailCFOFLength		12
++#define		bmax_en_pwdB		0xffff
++#define		bCC_power_dB		0xffff0000
++#define		bnoise_pwdB		0xffff
++#define		bPowerMeasTLength	10
++#define		bPowerMeasFLength	3
++#define		bRx_HT_BW			0x1
++#define		bRxSC				0x6
++#define		bRx_HT				0x8
++#define		bNB_intf_det_on		0x1
++#define		bIntf_win_len_cfg	0x30
++#define		bNB_Intf_TH_cfg		0x1c0
++#define		bRFGain				0x3f
++#define		bTableSel			0x40
++#define		bTRSW				0x80
++#define		bRxSNR_A			0xff
++#define		bRxSNR_B			0xff00
++#define		bRxSNR_C			0xff0000
++#define		bRxSNR_D			0xff000000
++#define		bSNREVMTLength		8
++#define		bSNREVMFLength		1
++#define		bCSI1st				0xff
++#define		bCSI2nd				0xff00
++#define		bRxEVM1st			0xff0000
++#define		bRxEVM2nd			0xff000000
++#define		bSIGEVM			0xff
++#define		bPWDB				0xff00
++#define		bSGIEN				0x10000
++
++#define		bSFactorQAM1		0xf	/* Useless */
++#define		bSFactorQAM2		0xf0
++#define		bSFactorQAM3		0xf00
++#define		bSFactorQAM4		0xf000
++#define		bSFactorQAM5		0xf0000
++#define		bSFactorQAM6		0xf0000
++#define		bSFactorQAM7		0xf00000
++#define		bSFactorQAM8		0xf000000
++#define		bSFactorQAM9		0xf0000000
++#define		bCSIScheme			0x100000
++
++#define		bNoiseLvlTopSet		0x3	/* Useless */
++#define		bChSmooth			0x4
++#define		bChSmoothCfg1		0x38
++#define		bChSmoothCfg2		0x1c0
++#define		bChSmoothCfg3		0xe00
++#define		bChSmoothCfg4		0x7000
++#define		bMRCMode			0x800000
++#define		bTHEVMCfg			0x7000000
++
++#define		bLoopFitType		0x1	/* Useless */
++#define		bUpdCFO			0x40
++#define		bUpdCFOOffData		0x80
++#define		bAdvUpdCFO			0x100
++#define		bAdvTimeCtrl		0x800
++#define		bUpdClko			0x1000
++#define		bFC					0x6000
++#define		bTrackingMode		0x8000
++#define		bPhCmpEnable		0x10000
++#define		bUpdClkoLTF		0x20000
++#define		bComChCFO			0x40000
++#define		bCSIEstiMode		0x80000
++#define		bAdvUpdEqz			0x100000
++#define		bUChCfg				0x7000000
++#define		bUpdEqz			0x8000000
++
++/* Rx Pseduo noise */
++#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
++#define		bRxPesudoNoise_A		0xff
++#define		bRxPesudoNoise_B		0xff00
++#define		bRxPesudoNoise_C		0xff0000
++#define		bRxPesudoNoise_D		0xff000000
++#define		bPesudoNoiseState_A	0xffff
++#define		bPesudoNoiseState_B	0xffff0000
++#define		bPesudoNoiseState_C	0xffff
++#define		bPesudoNoiseState_D	0xffff0000
++
++/* 7. RF Register
++ * Zebra1 */
++#define		bZebra1_HSSIEnable		0x8		/* Useless */
++#define		bZebra1_TRxControl		0xc00
++#define		bZebra1_TRxGainSetting	0x07f
++#define		bZebra1_RxCorner		0xc00
++#define		bZebra1_TxChargePump	0x38
++#define		bZebra1_RxChargePump	0x7
++#define		bZebra1_ChannelNum	0xf80
++#define		bZebra1_TxLPFBW		0x400
++#define		bZebra1_RxLPFBW		0x600
++
++/* Zebra4 */
++#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
++#define		bRTL8256RegModeCtrl0	0x40
++#define		bRTL8256_TxLPFBW		0x18
++#define		bRTL8256_RxLPFBW		0x600
++
++/* RTL8258 */
++#define		bRTL8258_TxLPFBW		0xc	/* Useless */
++#define		bRTL8258_RxLPFBW		0xc00
++#define		bRTL8258_RSSILPFBW	0xc0
++
++
++/*
++ * Other Definition
++ *   */
++
++/* byte endable for sb_write */
++#define		bByte0				0x1	/* Useless */
++#define		bByte1				0x2
++#define		bByte2				0x4
++#define		bByte3				0x8
++#define		bWord0				0x3
++#define		bWord1				0xc
++#define		bDWord				0xf
++
++/* for PutRegsetting & GetRegSetting BitMask */
++#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
++#define		bMaskByte1			0xff00
++#define		bMaskByte2			0xff0000
++#define		bMaskByte3			0xff000000
++#define		bMaskHWord		0xffff0000
++#define		bMaskLWord			0x0000ffff
++#define		bMaskDWord		0xffffffff
++#define		bMaskH3Bytes		0xffffff00
++#define		bMask12Bits			0xfff
++#define		bMaskH4Bits			0xf0000000
++#define		bMaskOFDM_D		0xffc00000
++#define		bMaskCCK			0x3f3f3f3f
++
++
++#define		bEnable			0x1	/* Useless */
++#define		bDisable		0x0
++
++#define		LeftAntenna		0x0	/* Useless */
++#define		RightAntenna	0x1
++
++#define		tCheckTxStatus		500   /* 500ms // Useless */
++#define		tUpdateRxCounter	100   /* 100ms */
++
++#define		rateCCK		0	/* Useless */
++#define		rateOFDM	1
++#define		rateHT		2
++
++/* define Register-End */
++#define		bPMAC_End			0x1ff	/* Useless */
++#define		bFPGAPHY0_End		0x8ff
++#define		bFPGAPHY1_End		0x9ff
++#define		bCCKPHY0_End		0xaff
++#define		bOFDMPHY0_End		0xcff
++#define		bOFDMPHY1_End		0xdff
++
++/* define max debug item in each debug page
++ * #define bMaxItem_FPGA_PHY0        0x9
++ * #define bMaxItem_FPGA_PHY1        0x3
++ * #define bMaxItem_PHY_11B          0x16
++ * #define bMaxItem_OFDM_PHY0        0x29
++ * #define bMaxItem_OFDM_PHY1        0x0 */
++
++#define		bPMACControl		0x0		/* Useless */
++#define		bWMACControl		0x1
++#define		bWNICControl		0x2
++
++#define		PathA			0x0	/* Useless */
++#define		PathB			0x1
++#define		PathC			0x2
++#define		PathD			0x3
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8710BPwrSeq.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8710BPwrSeq.h
+new file mode 100644
+index 000000000..31ad29c79
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8710BPwrSeq.h
+@@ -0,0 +1,167 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef REALTEK_POWER_SEQUENCE_8710B
++#define REALTEK_POWER_SEQUENCE_8710B
++
++/* #include "PwrSeqCmd.h" */
++#include "HalPwrSeqCmd.h"
++
++/*
++	Check document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd
++	There are 6 HW Power States:
++	0: POFF--Power Off
++	1: PDN--Power Down
++	2: CARDEMU--Card Emulation
++	3: ACT--Active Mode
++	4: LPS--Low Power State
++	5: SUS--Suspend
++
++	The transition from different states are defined below
++	TRANS_CARDEMU_TO_ACT
++	TRANS_ACT_TO_CARDEMU
++	TRANS_CARDEMU_TO_SUS
++	TRANS_SUS_TO_CARDEMU
++	TRANS_CARDEMU_TO_PDN
++	TRANS_ACT_TO_LPS
++	TRANS_LPS_TO_ACT
++
++	TRANS_END
++*/
++#define RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS 5
++#define RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS 4
++#define RTL8710B_TRANS_CARDEMU_TO_SUS_STEPS 7
++#define RTL8710B_TRANS_SUS_TO_CARDEMU_STEPS 15
++#define RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS 15
++#define RTL8710B_TRANS_PDN_TO_CARDEMU_STEPS 15
++#define RTL8710B_TRANS_ACT_TO_LPS_STEPS 	15
++#define RTL8710B_TRANS_LPS_TO_ACT_STEPS 	15	
++#define RTL8710B_TRANS_ACT_TO_SWLPS_STEPS		22
++#define RTL8710B_TRANS_SWLPS_TO_ACT_STEPS		15
++#define RTL8710B_TRANS_END_STEPS		1
++
++
++#define RTL8710B_TRANS_CARDEMU_TO_ACT 														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x005D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*AFE power mode selection:1:  LDO mode ,0:  Power-cut mode*/\
++	{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\
++	{0x0056, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x0E},\
++	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\
++	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ 
++
++	
++#define RTL8710B_TRANS_ACT_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/	\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1|BIT2), 0},/*0x04[24:26] = 0 turn off RF*/	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1), 0},/*0x04[16:17] = 0 BB reset*/	\
++	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x20[1] = 1 turn off MAC by HW state machine*/	\
++	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x20[1] = 0 polling until return 0 to disable*/ \
++
++
++#define RTL8710B_TRANS_CARDEMU_TO_SUS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
++
++#define RTL8710B_TRANS_SUS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
++	
++
++#define RTL8710B_TRANS_CARDEMU_TO_CARDDIS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
++
++#define RTL8710B_TRANS_CARDDIS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++
++
++#define RTL8710B_TRANS_CARDEMU_TO_PDN												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
++
++#define RTL8710B_TRANS_PDN_TO_CARDEMU												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
++
++#define RTL8710B_TRANS_ACT_TO_LPS														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
++	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
++	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
++	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	
++
++
++#define RTL8710B_TRANS_LPS_TO_ACT															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
++	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
++	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0 	 switch TSF to 40M*/\
++	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
++	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
++ 
++#define RTL8710B_TRANS_END															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
++
++
++extern WLAN_PWR_CFG rtl8710B_power_on_flow[RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8710B_radio_off_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8710B_card_disable_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8710B_card_enable_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8710B_suspend_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8710B_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8710B_resume_flow[RTL8710B_TRANS_SUS_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8710B_hwpdn_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8710B_enter_lps_flow[RTL8710B_TRANS_ACT_TO_LPS_STEPS+RTL8710B_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8710B_leave_lps_flow[RTL8710B_TRANS_LPS_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723BPhyCfg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723BPhyCfg.h
+new file mode 100644
+index 000000000..0f59b8b24
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723BPhyCfg.h
+@@ -0,0 +1,116 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8723BPHYCFG_H__
++#define __INC_HAL8723BPHYCFG_H__
++
++/*--------------------------Define Parameters-------------------------------*/
++#define LOOP_LIMIT				5
++#define MAX_STALL_TIME			50		/* us */
++#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
++#define MAX_TXPWR_IDX_NMODE_92S	63
++#define Reset_Cnt_Limit			3
++
++#ifdef CONFIG_PCI_HCI
++	#define MAX_AGGR_NUM	0x0B
++#else
++	#define MAX_AGGR_NUM	0x07
++#endif /* CONFIG_PCI_HCI */
++
++
++/*--------------------------Define Parameters End-------------------------------*/
++
++
++/*------------------------------Define structure----------------------------*/
++
++/*------------------------------Define structure End----------------------------*/
++
++/*--------------------------Exported Function prototype---------------------*/
++u32
++PHY_QueryBBReg_8723B(
++		PADAPTER	Adapter,
++		u32		RegAddr,
++		u32		BitMask
++);
++
++void
++PHY_SetBBReg_8723B(
++		PADAPTER	Adapter,
++		u32		RegAddr,
++		u32		BitMask,
++		u32		Data
++);
++
++u32
++PHY_QueryRFReg_8723B(
++		PADAPTER			Adapter,
++		enum rf_path			eRFPath,
++		u32				RegAddr,
++		u32				BitMask
++);
++
++void
++PHY_SetRFReg_8723B(
++		PADAPTER			Adapter,
++		enum rf_path			eRFPath,
++		u32				RegAddr,
++		u32				BitMask,
++		u32				Data
++);
++
++/* MAC/BB/RF HAL config */
++int PHY_BBConfig8723B(PADAPTER	Adapter);
++
++int PHY_RFConfig8723B(PADAPTER	Adapter);
++
++s32 PHY_MACConfig8723B(PADAPTER padapter);
++
++int
++PHY_ConfigRFWithParaFile_8723B(
++		PADAPTER			Adapter,
++		u8					*pFileName,
++	enum rf_path				eRFPath
++);
++
++void
++PHY_SetTxPowerIndex_8723B(
++		PADAPTER			Adapter,
++		u32					PowerIndex,
++		enum rf_path			RFPath,
++		u8					Rate
++);
++
++void
++PHY_SetTxPowerLevel8723B(
++		PADAPTER		Adapter,
++		u8			channel
++);
++
++void
++PHY_SetSwChnlBWMode8723B(
++		PADAPTER			Adapter,
++		u8					channel,
++		enum channel_width	Bandwidth,
++		u8					Offset40,
++		u8					Offset80
++);
++
++void phy_set_rf_path_switch_8723b(
++		struct dm_struct		*phydm,
++		bool		bMain
++);
++
++/*--------------------------Exported Function prototype End---------------------*/
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723BPhyReg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723BPhyReg.h
+new file mode 100644
+index 000000000..ce485c2ab
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723BPhyReg.h
+@@ -0,0 +1,1131 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8723BPHYREG_H__
++#define __INC_HAL8723BPHYREG_H__
++
++#define		rSYM_WLBT_PAPE_SEL		0x64
++/*
++ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
++ * 3. RF register 0x00-2E
++ * 4. Bit Mask for BB/RF register
++ * 5. Other defintion for BB/RF R/W
++ *   */
++
++
++/*
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 1. Page1(0x100)
++ *   */
++#define		rPMAC_Reset					0x100
++#define		rPMAC_TxStart					0x104
++#define		rPMAC_TxLegacySIG				0x108
++#define		rPMAC_TxHTSIG1				0x10c
++#define		rPMAC_TxHTSIG2				0x110
++#define		rPMAC_PHYDebug				0x114
++#define		rPMAC_TxPacketNum				0x118
++#define		rPMAC_TxIdle					0x11c
++#define		rPMAC_TxMACHeader0			0x120
++#define		rPMAC_TxMACHeader1			0x124
++#define		rPMAC_TxMACHeader2			0x128
++#define		rPMAC_TxMACHeader3			0x12c
++#define		rPMAC_TxMACHeader4			0x130
++#define		rPMAC_TxMACHeader5			0x134
++#define		rPMAC_TxDataType				0x138
++#define		rPMAC_TxRandomSeed			0x13c
++#define		rPMAC_CCKPLCPPreamble			0x140
++#define		rPMAC_CCKPLCPHeader			0x144
++#define		rPMAC_CCKCRC16				0x148
++#define		rPMAC_OFDMRxCRC32OK			0x170
++#define		rPMAC_OFDMRxCRC32Er			0x174
++#define		rPMAC_OFDMRxParityEr			0x178
++#define		rPMAC_OFDMRxCRC8Er			0x17c
++#define		rPMAC_CCKCRxRC16Er			0x180
++#define		rPMAC_CCKCRxRC32Er			0x184
++#define		rPMAC_CCKCRxRC32OK			0x188
++#define		rPMAC_TxStatus					0x18c
++
++/*
++ * 2. Page2(0x200)
++ *
++ * The following two definition are only used for USB interface. */
++#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
++#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
++
++/*
++ * 3. Page8(0x800)
++ *   */
++#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
++
++#define		rFPGA0_TxInfo				0x804	/* Status report?? */
++#define		rFPGA0_PSDFunction			0x808
++
++#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
++
++#define		rFPGA0_RFTiming1			0x810	/* Useless now */
++#define		rFPGA0_RFTiming2			0x814
++
++#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
++#define		rFPGA0_XA_HSSIParameter2		0x824
++#define		rFPGA0_XB_HSSIParameter1		0x828
++#define		rFPGA0_XB_HSSIParameter2		0x82c
++#define		rTxAGC_B_Rate18_06				0x830
++#define		rTxAGC_B_Rate54_24				0x834
++#define		rTxAGC_B_CCK1_55_Mcs32		0x838
++#define		rTxAGC_B_Mcs03_Mcs00			0x83c
++
++#define		rTxAGC_B_Mcs07_Mcs04			0x848
++#define		rTxAGC_B_Mcs11_Mcs08			0x84c
++
++#define		rFPGA0_XA_LSSIParameter		0x840
++#define		rFPGA0_XB_LSSIParameter		0x844
++
++#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
++#define		rFPGA0_RFSleepUpParameter		0x854
++
++#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
++#define		rFPGA0_XCD_SwitchControl		0x85c
++
++#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
++#define		rFPGA0_XB_RFInterfaceOE		0x864
++
++#define		rTxAGC_B_Mcs15_Mcs12			0x868
++#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
++
++#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
++#define		rFPGA0_XCD_RFInterfaceSW		0x874
++
++#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
++#define		rFPGA0_XCD_RFParameter		0x87c
++
++#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
++#define		rFPGA0_AnalogParameter2		0x884
++#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
++#define		rFPGA0_AnalogParameter4		0x88c
++
++#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
++#define		rFPGA0_XB_LSSIReadBack		0x8a4
++#define		rFPGA0_XC_LSSIReadBack		0x8a8
++#define		rFPGA0_XD_LSSIReadBack		0x8ac
++
++#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
++#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
++#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
++#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
++#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
++
++/*
++ * 4. Page9(0x900)
++ *   */
++#define	rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
++#define	rFPGA1_TxBlock				0x904	/* Useless now */
++#define	rFPGA1_DebugSelect			0x908	/* Useless now */
++#define	rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
++#define	rDPDT_control				0x92c
++#define	rfe_ctrl_anta_src				0x930
++#define	rS0S1_PathSwitch			0x948
++
++/*
++ * 5. PageA(0xA00)
++ *
++ * Set Control channel to upper or lower. These settings are required only for 40MHz */
++#define		rCCK0_System				0xa00
++
++#define		rCCK0_AFESetting			0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
++#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
++
++#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
++#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
++
++#define		rCCK0_RxHP					0xa14
++
++#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
++#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
++
++#define		rCCK0_TxFilter1				0xa20
++#define		rCCK0_TxFilter2				0xa24
++#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
++#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
++#define		rCCK0_TRSSIReport		0xa50
++#define		rCCK0_RxReport            		0xa54  /* 0xa57 */
++#define		rCCK0_FACounterLower      	0xa5c  /* 0xa5b */
++#define		rCCK0_FACounterUpper      	0xa58  /* 0xa5c */
++
++/*
++ * PageB(0xB00)
++ *   */
++#define rPdp_AntA						0xb00
++#define rPdp_AntA_4						0xb04
++#define rPdp_AntA_8						0xb08
++#define rPdp_AntA_C						0xb0c
++#define rPdp_AntA_10					0xb10
++#define rPdp_AntA_14					0xb14
++#define rPdp_AntA_18					0xb18
++#define rPdp_AntA_1C					0xb1c
++#define rPdp_AntA_20					0xb20
++#define rPdp_AntA_24					0xb24
++
++#define rConfig_Pmpd_AntA				0xb28
++#define rConfig_ram64x16				0xb2c
++
++#define rBndA							0xb30
++#define rHssiPar						0xb34
++
++#define rConfig_AntA					0xb68
++#define rConfig_AntB					0xb6c
++
++#define rPdp_AntB						0xb70
++#define rPdp_AntB_4						0xb74
++#define rPdp_AntB_8						0xb78
++#define rPdp_AntB_C						0xb7c
++#define rPdp_AntB_10					0xb80
++#define rPdp_AntB_14					0xb84
++#define rPdp_AntB_18					0xb88
++#define rPdp_AntB_1C					0xb8c
++#define rPdp_AntB_20					0xb90
++#define rPdp_AntB_24					0xb94
++
++#define rConfig_Pmpd_AntB				0xb98
++
++#define rBndB							0xba0
++
++#define rAPK							0xbd8
++#define rPm_Rx0_AntA					0xbdc
++#define rPm_Rx1_AntA					0xbe0
++#define rPm_Rx2_AntA					0xbe4
++#define rPm_Rx3_AntA					0xbe8
++#define rPm_Rx0_AntB					0xbec
++#define rPm_Rx1_AntB					0xbf0
++#define rPm_Rx2_AntB					0xbf4
++#define rPm_Rx3_AntB					0xbf8
++/*
++ * 6. PageC(0xC00)
++ *   */
++#define		rOFDM0_LSTF				0xc00
++
++#define		rOFDM0_TRxPathEnable		0xc04
++#define		rOFDM0_TRMuxPar			0xc08
++#define		rOFDM0_TRSWIsolation		0xc0c
++
++#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
++#define		rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
++#define		rOFDM0_XBRxAFE		0xc18
++#define		rOFDM0_XBRxIQImbalance	0xc1c
++#define		rOFDM0_XCRxAFE		0xc20
++#define		rOFDM0_XCRxIQImbalance	0xc24
++#define		rOFDM0_XDRxAFE		0xc28
++#define		rOFDM0_XDRxIQImbalance	0xc2c
++
++#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
++#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
++#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
++#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
++
++#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
++#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
++#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
++#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
++
++#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
++#define		rOFDM0_XAAGCCore2			0xc54
++#define		rOFDM0_XBAGCCore1			0xc58
++#define		rOFDM0_XBAGCCore2			0xc5c
++#define		rOFDM0_XCAGCCore1			0xc60
++#define		rOFDM0_XCAGCCore2			0xc64
++#define		rOFDM0_XDAGCCore1			0xc68
++#define		rOFDM0_XDAGCCore2			0xc6c
++
++#define		rOFDM0_AGCParameter1			0xc70
++#define		rOFDM0_AGCParameter2			0xc74
++#define		rOFDM0_AGCRSSITable			0xc78
++#define		rOFDM0_HTSTFAGC				0xc7c
++
++#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
++#define		rOFDM0_XATxAFE				0xc84
++#define		rOFDM0_XBTxIQImbalance		0xc88
++#define		rOFDM0_XBTxAFE				0xc8c
++#define		rOFDM0_XCTxIQImbalance		0xc90
++#define		rOFDM0_XCTxAFE			0xc94
++#define		rOFDM0_XDTxIQImbalance		0xc98
++#define		rOFDM0_XDTxAFE				0xc9c
++
++#define		rOFDM0_RxIQExtAnta			0xca0
++#define		rOFDM0_TxCoeff1				0xca4
++#define		rOFDM0_TxCoeff2				0xca8
++#define		rOFDM0_TxCoeff3				0xcac
++#define		rOFDM0_TxCoeff4				0xcb0
++#define		rOFDM0_TxCoeff5				0xcb4
++#define		rOFDM0_TxCoeff6				0xcb8
++#define		rOFDM0_RxHPParameter			0xce0
++#define		rOFDM0_TxPseudoNoiseWgt		0xce4
++#define		rOFDM0_FrameSync				0xcf0
++#define		rOFDM0_DFSReport				0xcf4
++
++/*
++ * 7. PageD(0xD00)
++ *   */
++#define		rOFDM1_LSTF					0xd00
++#define		rOFDM1_TRxPathEnable			0xd04
++
++#define		rOFDM1_CFO						0xd08	/* No setting now */
++#define		rOFDM1_CSI1					0xd10
++#define		rOFDM1_SBD						0xd14
++#define		rOFDM1_CSI2					0xd18
++#define		rOFDM1_CFOTracking			0xd2c
++#define		rOFDM1_TRxMesaure1			0xd34
++#define		rOFDM1_IntfDet					0xd3c
++#define		rOFDM1_PseudoNoiseStateAB		0xd50
++#define		rOFDM1_PseudoNoiseStateCD		0xd54
++#define		rOFDM1_RxPseudoNoiseWgt		0xd58
++
++#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
++#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
++#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
++
++#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
++#define		rOFDM_ShortCFOCD				0xdb0
++#define		rOFDM_LongCFOAB				0xdb4
++#define		rOFDM_LongCFOCD				0xdb8
++#define		rOFDM_TailCFOAB				0xdbc
++#define		rOFDM_TailCFOCD				0xdc0
++#define		rOFDM_PWMeasure1		0xdc4
++#define		rOFDM_PWMeasure2		0xdc8
++#define		rOFDM_BWReport				0xdcc
++#define		rOFDM_AGCReport				0xdd0
++#define		rOFDM_RxSNR					0xdd4
++#define		rOFDM_RxEVMCSI				0xdd8
++#define		rOFDM_SIGReport				0xddc
++
++
++/*
++ * 8. PageE(0xE00)
++ *   */
++#define		rTxAGC_A_Rate18_06			0xe00
++#define		rTxAGC_A_Rate54_24			0xe04
++#define		rTxAGC_A_CCK1_Mcs32			0xe08
++#define		rTxAGC_A_Mcs03_Mcs00			0xe10
++#define		rTxAGC_A_Mcs07_Mcs04			0xe14
++#define		rTxAGC_A_Mcs11_Mcs08			0xe18
++#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
++
++#define		rFPGA0_IQK					0xe28
++#define		rTx_IQK_Tone_A				0xe30
++#define		rRx_IQK_Tone_A				0xe34
++#define		rTx_IQK_PI_A					0xe38
++#define		rRx_IQK_PI_A					0xe3c
++
++#define		rTx_IQK						0xe40
++#define		rRx_IQK						0xe44
++#define		rIQK_AGC_Pts					0xe48
++#define		rIQK_AGC_Rsp					0xe4c
++#define		rTx_IQK_Tone_B				0xe50
++#define		rRx_IQK_Tone_B				0xe54
++#define		rTx_IQK_PI_B					0xe58
++#define		rRx_IQK_PI_B					0xe5c
++#define		rIQK_AGC_Cont				0xe60
++
++#define		rBlue_Tooth					0xe6c
++#define		rRx_Wait_CCA					0xe70
++#define		rTx_CCK_RFON					0xe74
++#define		rTx_CCK_BBON				0xe78
++#define		rTx_OFDM_RFON				0xe7c
++#define		rTx_OFDM_BBON				0xe80
++#define		rTx_To_Rx					0xe84
++#define		rTx_To_Tx					0xe88
++#define		rRx_CCK						0xe8c
++
++#define		rTx_Power_Before_IQK_A		0xe94
++#define		rTx_Power_After_IQK_A			0xe9c
++
++#define		rRx_Power_Before_IQK_A		0xea0
++#define		rRx_Power_Before_IQK_A_2		0xea4
++#define		rRx_Power_After_IQK_A			0xea8
++#define		rRx_Power_After_IQK_A_2		0xeac
++
++#define		rTx_Power_Before_IQK_B		0xeb4
++#define		rTx_Power_After_IQK_B			0xebc
++
++#define		rRx_Power_Before_IQK_B		0xec0
++#define		rRx_Power_Before_IQK_B_2		0xec4
++#define		rRx_Power_After_IQK_B			0xec8
++#define		rRx_Power_After_IQK_B_2		0xecc
++
++#define		rRx_OFDM					0xed0
++#define		rRx_Wait_RIFS				0xed4
++#define		rRx_TO_Rx					0xed8
++#define		rStandby						0xedc
++#define		rSleep						0xee0
++#define		rPMPD_ANAEN				0xeec
++
++/*
++ * 7. RF Register 0x00-0x2E (RF 8256)
++ * RF-0222D 0x00-3F
++ *
++ * Zebra1 */
++#define		rZebra1_HSSIEnable				0x0	/* Useless now */
++#define		rZebra1_TRxEnable1				0x1
++#define		rZebra1_TRxEnable2				0x2
++#define		rZebra1_AGC					0x4
++#define		rZebra1_ChargePump			0x5
++#define		rZebra1_Channel				0x7	/* RF channel switch */
++
++/* #endif */
++#define		rZebra1_TxGain					0x8	/* Useless now */
++#define		rZebra1_TxLPF					0x9
++#define		rZebra1_RxLPF					0xb
++#define		rZebra1_RxHPFCorner			0xc
++
++/* Zebra4 */
++#define		rGlobalCtrl						0	/* Useless now */
++#define		rRTL8256_TxLPF					19
++#define		rRTL8256_RxLPF					11
++
++/* RTL8258 */
++#define		rRTL8258_TxLPF					0x11	/* Useless now */
++#define		rRTL8258_RxLPF					0x13
++#define		rRTL8258_RSSILPF				0xa
++
++/*
++ * RL6052 Register definition
++ *   */
++#define		RF_AC						0x00	/*  */
++
++#define		RF_IQADJ_G1				0x01	/*  */
++#define		RF_IQADJ_G2				0x02	/*  */
++#define		RF_BS_PA_APSET_G1_G4		0x03
++#define		RF_BS_PA_APSET_G5_G8		0x04
++#define		RF_POW_TRSW				0x05	/*  */
++
++#define		RF_GAIN_RX					0x06	/*  */
++#define		RF_GAIN_TX					0x07	/*  */
++
++#define		RF_TXM_IDAC				0x08	/*  */
++#define		RF_IPA_G					0x09	/*  */
++#define		RF_TXBIAS_G				0x0A
++#define		RF_TXPA_AG					0x0B
++#define		RF_IPA_A					0x0C	/*  */
++#define		RF_TXBIAS_A				0x0D
++#define		RF_BS_PA_APSET_G9_G11	0x0E
++#define		RF_BS_IQGEN				0x0F	/*  */
++
++#define		RF_MODE1					0x10	/*  */
++#define		RF_MODE2					0x11	/*  */
++
++#define		RF_RX_AGC_HP				0x12	/*  */
++#define		RF_TX_AGC					0x13	/*  */
++#define		RF_BIAS						0x14	/*  */
++#define		RF_IPA						0x15	/*  */
++#define		RF_TXBIAS					0x16
++#define		RF_POW_ABILITY			0x17	/*  */
++#define		RF_MODE_AG				0x18	/*  */
++#define		rRfChannel					0x18	/* RF channel and BW switch */
++#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
++#define		RF_TOP						0x19	/*  */
++
++#define		RF_RX_G1					0x1A	/*  */
++#define		RF_RX_G2					0x1B	/*  */
++
++#define		RF_RX_BB2					0x1C	/*  */
++#define		RF_RX_BB1					0x1D	/*  */
++
++#define		RF_RCK1					0x1E	/*  */
++#define		RF_RCK2					0x1F	/*  */
++
++#define		RF_TX_G1					0x20	/*  */
++#define		RF_TX_G2					0x21	/*  */
++#define		RF_TX_G3					0x22	/*  */
++
++#define		RF_TX_BB1					0x23	/*  */
++
++#define		RF_T_METER					0x24	/*  */
++
++#define		RF_SYN_G1					0x25	/* RF TX Power control */
++#define		RF_SYN_G2					0x26	/* RF TX Power control */
++#define		RF_SYN_G3					0x27	/* RF TX Power control */
++#define		RF_SYN_G4					0x28	/* RF TX Power control */
++#define		RF_SYN_G5					0x29	/* RF TX Power control */
++#define		RF_SYN_G6					0x2A	/* RF TX Power control */
++#define		RF_SYN_G7					0x2B	/* RF TX Power control */
++#define		RF_SYN_G8					0x2C	/* RF TX Power control */
++
++#define		RF_RCK_OS					0x30	/* RF TX PA control */
++
++#define		RF_TXPA_G1					0x31	/* RF TX PA control */
++#define		RF_TXPA_G2					0x32	/* RF TX PA control */
++#define		RF_TXPA_G3					0x33	/* RF TX PA control */
++#define	RF_TX_BIAS_A				0x35
++#define	RF_TX_BIAS_D				0x36
++#define	RF_LOBF_9					0x38
++#define 	RF_RXRF_A3					0x3C	/*	 */
++#define	RF_TRSW					0x3F
++
++#define	RF_TXRF_A2					0x41
++#define	RF_TXPA_G4					0x46
++#define	RF_TXPA_A4					0x4B
++#define	RF_0x52					0x52
++#define	RF_WE_LUT					0xEF
++#define	RF_S0S1					0xB0
++
++/*
++ * Bit Mask
++ *
++ * 1. Page1(0x100) */
++#define		bBBResetB						0x100	/* Useless now? */
++#define		bGlobalResetB					0x200
++#define		bOFDMTxStart					0x4
++#define		bCCKTxStart						0x8
++#define		bCRC32Debug					0x100
++#define		bPMACLoopback					0x10
++#define		bTxLSIG							0xffffff
++#define		bOFDMTxRate					0xf
++#define		bOFDMTxReserved				0x10
++#define		bOFDMTxLength					0x1ffe0
++#define		bOFDMTxParity					0x20000
++#define		bTxHTSIG1						0xffffff
++#define		bTxHTMCSRate					0x7f
++#define		bTxHTBW						0x80
++#define		bTxHTLength					0xffff00
++#define		bTxHTSIG2						0xffffff
++#define		bTxHTSmoothing					0x1
++#define		bTxHTSounding					0x2
++#define		bTxHTReserved					0x4
++#define		bTxHTAggreation				0x8
++#define		bTxHTSTBC						0x30
++#define		bTxHTAdvanceCoding			0x40
++#define		bTxHTShortGI					0x80
++#define		bTxHTNumberHT_LTF			0x300
++#define		bTxHTCRC8						0x3fc00
++#define		bCounterReset					0x10000
++#define		bNumOfOFDMTx					0xffff
++#define		bNumOfCCKTx					0xffff0000
++#define		bTxIdleInterval					0xffff
++#define		bOFDMService					0xffff0000
++#define		bTxMACHeader					0xffffffff
++#define		bTxDataInit						0xff
++#define		bTxHTMode						0x100
++#define		bTxDataType					0x30000
++#define		bTxRandomSeed					0xffffffff
++#define		bCCKTxPreamble					0x1
++#define		bCCKTxSFD						0xffff0000
++#define		bCCKTxSIG						0xff
++#define		bCCKTxService					0xff00
++#define		bCCKLengthExt					0x8000
++#define		bCCKTxLength					0xffff0000
++#define		bCCKTxCRC16					0xffff
++#define		bCCKTxStatus					0x1
++#define		bOFDMTxStatus					0x2
++
++#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
++
++/* 2. Page8(0x800) */
++#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
++#define		bJapanMode						0x2
++#define		bCCKTxSC						0x30
++#define		bCCKEn							0x1000000
++#define		bOFDMEn						0x2000000
++
++#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
++#define		bOFDMTxDACPhase		0x40000
++#define		bXATxAGC			0x3f
++
++#define		bAntennaSelect		0x0300
++
++#define		bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
++#define		bXCTxAGC			0xf000
++#define		bXDTxAGC			0xf0000
++
++#define		bPAStart                  			0xf0000000	/* Useless now */
++#define		bTRStart			0x00f00000
++#define		bRFStart			0x0000f000
++#define		bBBStart			0x000000f0
++#define		bBBCCKStart		0x0000000f
++#define		bPAEnd                    			0xf          /* Reg0x814 */
++#define		bTREnd			0x0f000000
++#define		bRFEnd			0x000f0000
++#define		bCCAMask                  			0x000000f0   /* T2R */
++#define		bR2RCCAMask		0x00000f00
++#define		bHSSI_R2TDelay		0xf8000000
++#define		bHSSI_T2RDelay		0xf80000
++#define		bContTxHSSI               		0x400     /* chane gain at continue Tx */
++#define		bIGFromCCK		0x200
++#define		bAGCAddress		0x3f
++#define		bRxHPTx			0x7000
++#define		bRxHPT2R			0x38000
++#define		bRxHPCCKIni		0xc0000
++#define		bAGCTxCode		0xc00000
++#define		bAGCRxCode		0x300000
++
++#define		b3WireDataLength          		0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
++#define		b3WireAddressLength		0x400
++
++#define		b3WireRFPowerDown         		0x1	/* Useless now
++ * #define bHWSISelect		0x8 */
++#define		b5GPAPEPolarity		0x40000000
++#define		b2GPAPEPolarity		0x80000000
++#define		bRFSW_TxDefaultAnt		0x3
++#define		bRFSW_TxOptionAnt		0x30
++#define		bRFSW_RxDefaultAnt		0x300
++#define		bRFSW_RxOptionAnt		0x3000
++#define		bRFSI_3WireData		0x1
++#define		bRFSI_3WireClock		0x2
++#define		bRFSI_3WireLoad		0x4
++#define		bRFSI_3WireRW		0x8
++#define		bRFSI_3Wire			0xf
++
++#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
++
++#define		bRFSI_TRSW                		0x20	/* Useless now */
++#define		bRFSI_TRSWB		0x40
++#define		bRFSI_ANTSW		0x100
++#define		bRFSI_ANTSWB		0x200
++#define		bRFSI_PAPE			0x400
++#define		bRFSI_PAPE5G		0x800
++#define		bBandSelect			0x1
++#define		bHTSIG2_GI			0x80
++#define		bHTSIG2_Smoothing		0x01
++#define		bHTSIG2_Sounding		0x02
++#define		bHTSIG2_Aggreaton		0x08
++#define		bHTSIG2_STBC		0x30
++#define		bHTSIG2_AdvCoding		0x40
++#define		bHTSIG2_NumOfHTLTF	0x300
++#define		bHTSIG2_CRC8		0x3fc
++#define		bHTSIG1_MCS		0x7f
++#define		bHTSIG1_BandWidth		0x80
++#define		bHTSIG1_HTLength		0xffff
++#define		bLSIG_Rate			0xf
++#define		bLSIG_Reserved		0x10
++#define		bLSIG_Length		0x1fffe
++#define		bLSIG_Parity			0x20
++#define		bCCKRxPhase		0x4
++
++#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
++
++#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
++
++#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
++
++#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
++#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
++#define		bRegulator0Standby		0x1
++#define		bRegulatorPLLStandby		0x2
++#define		bRegulator1Standby		0x4
++#define		bPLLPowerUp		0x8
++#define		bDPLLPowerUp		0x10
++#define		bDA10PowerUp		0x20
++#define		bAD7PowerUp		0x200
++#define		bDA6PowerUp		0x2000
++#define		bXtalPowerUp		0x4000
++#define		b40MDClkPowerUP		0x8000
++#define		bDA6DebugMode		0x20000
++#define		bDA6Swing			0x380000
++
++#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
++
++#define		b80MClkDelay              		0x18000000	/* Useless */
++#define		bAFEWatchDogEnable		0x20000000
++
++#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
++#define		bXtalCap23			0x3
++#define		bXtalCap92x					0x0f000000
++#define		bXtalCap			0x0f000000
++
++#define		bIntDifClkEnable          		0x400	/* Useless */
++#define		bExtSigClkEnable		0x800
++#define		bBandgapMbiasPowerUp	0x10000
++#define		bAD11SHGain		0xc0000
++#define		bAD11InputRange		0x700000
++#define		bAD11OPCurrent		0x3800000
++#define		bIPathLoopback		0x4000000
++#define		bQPathLoopback		0x8000000
++#define		bAFELoopback		0x10000000
++#define		bDA10Swing		0x7e0
++#define		bDA10Reverse		0x800
++#define		bDAClkSource		0x1000
++#define		bAD7InputRange		0x6000
++#define		bAD7Gain			0x38000
++#define		bAD7OutputCMMode		0x40000
++#define		bAD7InputCMMode		0x380000
++#define		bAD7Current			0xc00000
++#define		bRegulatorAdjust		0x7000000
++#define		bAD11PowerUpAtTx		0x1
++#define		bDA10PSAtTx		0x10
++#define		bAD11PowerUpAtRx		0x100
++#define		bDA10PSAtRx		0x1000
++#define		bCCKRxAGCFormat		0x200
++#define		bPSDFFTSamplepPoint		0xc000
++#define		bPSDAverageNum		0x3000
++#define		bIQPathControl		0xc00
++#define		bPSDFreq			0x3ff
++#define		bPSDAntennaPath		0x30
++#define		bPSDIQSwitch		0x40
++#define		bPSDRxTrigger		0x400000
++#define		bPSDTxTrigger		0x80000000
++#define		bPSDSineToneScale		0x7f000000
++#define		bPSDReport			0xffff
++
++/* 3. Page9(0x900) */
++#define		bOFDMTxSC                 		0x30000000	/* Useless */
++#define		bCCKTxOn			0x1
++#define		bOFDMTxOn		0x2
++#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
++#define		bDebugItem                		0xff   /* reset debug page and LWord */
++#define		bAntL			0x10
++#define		bAntNonHT				0x100
++#define		bAntHT1			0x1000
++#define		bAntHT2			0x10000
++#define		bAntHT1S1			0x100000
++#define		bAntNonHTS1		0x1000000
++
++/* 4. PageA(0xA00) */
++#define		bCCKBBMode				0x3	/* Useless */
++#define		bCCKTxPowerSaving		0x80
++#define		bCCKRxPowerSaving		0x40
++
++#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
++
++#define		bCCKScramble			0x8	/* Useless */
++#define		bCCKAntDiversity		0x8000
++#define		bCCKCarrierRecovery		0x4000
++#define		bCCKTxRate				0x3000
++#define		bCCKDCCancel			0x0800
++#define		bCCKISICancel			0x0400
++#define		bCCKMatchFilter			0x0200
++#define		bCCKEqualizer			0x0100
++#define		bCCKPreambleDetect		0x800000
++#define		bCCKFastFalseCCA		0x400000
++#define		bCCKChEstStart			0x300000
++#define		bCCKCCACount			0x080000
++#define		bCCKcs_lim				0x070000
++#define		bCCKBistMode			0x80000000
++#define		bCCKCCAMask			0x40000000
++#define		bCCKTxDACPhase		0x4
++#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
++#define		bCCKr_cp_mode0		0x0100
++#define		bCCKTxDCOffset			0xf0
++#define		bCCKRxDCOffset			0xf
++#define		bCCKCCAMode			0xc000
++#define		bCCKFalseCS_lim			0x3f00
++#define		bCCKCS_ratio			0xc00000
++#define		bCCKCorgBit_sel			0x300000
++#define		bCCKPD_lim				0x0f0000
++#define		bCCKNewCCA			0x80000000
++#define		bCCKRxHPofIG			0x8000
++#define		bCCKRxIG				0x7f00
++#define		bCCKLNAPolarity			0x800000
++#define		bCCKRx1stGain			0x7f0000
++#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
++#define		bCCKRxAGCSatLevel		0x1f000000
++#define		bCCKRxAGCSatCount		0xe0
++#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
++#define		bCCKFixedRxAGC			0x8000
++/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
++#define		bCCKAntennaPolarity		0x2000
++#define		bCCKTxFilterType		0x0c00
++#define		bCCKRxAGCReportType	0x0300
++#define		bCCKRxDAGCEn			0x80000000
++#define		bCCKRxDAGCPeriod		0x20000000
++#define		bCCKRxDAGCSatLevel		0x1f000000
++#define		bCCKTimingRecovery		0x800000
++#define		bCCKTxC0				0x3f0000
++#define		bCCKTxC1				0x3f000000
++#define		bCCKTxC2				0x3f
++#define		bCCKTxC3				0x3f00
++#define		bCCKTxC4				0x3f0000
++#define		bCCKTxC5				0x3f000000
++#define		bCCKTxC6				0x3f
++#define		bCCKTxC7				0x3f00
++#define		bCCKDebugPort			0xff0000
++#define		bCCKDACDebug			0x0f000000
++#define		bCCKFalseAlarmEnable	0x8000
++#define		bCCKFalseAlarmRead		0x4000
++#define		bCCKTRSSI				0x7f
++#define		bCCKRxAGCReport		0xfe
++#define		bCCKRxReport_AntSel	0x80000000
++#define		bCCKRxReport_MFOff		0x40000000
++#define		bCCKRxRxReport_SQLoss	0x20000000
++#define		bCCKRxReport_Pktloss	0x10000000
++#define		bCCKRxReport_Lockedbit	0x08000000
++#define		bCCKRxReport_RateError	0x04000000
++#define		bCCKRxReport_RxRate	0x03000000
++#define		bCCKRxFACounterLower	0xff
++#define		bCCKRxFACounterUpper	0xff000000
++#define		bCCKRxHPAGCStart		0xe000
++#define		bCCKRxHPAGCFinal		0x1c00
++#define		bCCKRxFalseAlarmEnable	0x8000
++#define		bCCKFACounterFreeze	0x4000
++#define		bCCKTxPathSel			0x10000000
++#define		bCCKDefaultRxPath		0xc000000
++#define		bCCKOptionRxPath		0x3000000
++
++/* 5. PageC(0xC00) */
++#define		bNumOfSTF				0x3	/* Useless */
++#define		bShift_L					0xc0
++#define		bGI_TH					0xc
++#define		bRxPathA				0x1
++#define		bRxPathB				0x2
++#define		bRxPathC				0x4
++#define		bRxPathD				0x8
++#define		bTxPathA				0x1
++#define		bTxPathB				0x2
++#define		bTxPathC				0x4
++#define		bTxPathD				0x8
++#define		bTRSSIFreq				0x200
++#define		bADCBackoff				0x3000
++#define		bDFIRBackoff			0xc000
++#define		bTRSSILatchPhase		0x10000
++#define		bRxIDCOffset			0xff
++#define		bRxQDCOffset			0xff00
++#define		bRxDFIRMode			0x1800000
++#define		bRxDCNFType			0xe000000
++#define		bRXIQImb_A				0x3ff
++#define		bRXIQImb_B				0xfc00
++#define		bRXIQImb_C				0x3f0000
++#define		bRXIQImb_D				0xffc00000
++#define		bDC_dc_Notch			0x60000
++#define		bRxNBINotch			0x1f000000
++#define		bPD_TH					0xf
++#define		bPD_TH_Opt2			0xc000
++#define		bPWED_TH				0x700
++#define		bIfMF_Win_L			0x800
++#define		bPD_Option				0x1000
++#define		bMF_Win_L				0xe000
++#define		bBW_Search_L			0x30000
++#define		bwin_enh_L				0xc0000
++#define		bBW_TH					0x700000
++#define		bED_TH2				0x3800000
++#define		bBW_option				0x4000000
++#define		bRatio_TH				0x18000000
++#define		bWindow_L				0xe0000000
++#define		bSBD_Option				0x1
++#define		bFrame_TH				0x1c
++#define		bFS_Option				0x60
++#define		bDC_Slope_check		0x80
++#define		bFGuard_Counter_DC_L	0xe00
++#define		bFrame_Weight_Short	0x7000
++#define		bSub_Tune				0xe00000
++#define		bFrame_DC_Length		0xe000000
++#define		bSBD_start_offset		0x30000000
++#define		bFrame_TH_2			0x7
++#define		bFrame_GI2_TH			0x38
++#define		bGI2_Sync_en			0x40
++#define		bSarch_Short_Early		0x300
++#define		bSarch_Short_Late		0xc00
++#define		bSarch_GI2_Late		0x70000
++#define		bCFOAntSum				0x1
++#define		bCFOAcc				0x2
++#define		bCFOStartOffset			0xc
++#define		bCFOLookBack			0x70
++#define		bCFOSumWeight			0x80
++#define		bDAGCEnable			0x10000
++#define		bTXIQImb_A				0x3ff
++#define		bTXIQImb_B				0xfc00
++#define		bTXIQImb_C				0x3f0000
++#define		bTXIQImb_D				0xffc00000
++#define		bTxIDCOffset			0xff
++#define		bTxQDCOffset			0xff00
++#define		bTxDFIRMode			0x10000
++#define		bTxPesudoNoiseOn		0x4000000
++#define		bTxPesudoNoise_A		0xff
++#define		bTxPesudoNoise_B		0xff00
++#define		bTxPesudoNoise_C		0xff0000
++#define		bTxPesudoNoise_D		0xff000000
++#define		bCCADropOption			0x20000
++#define		bCCADropThres			0xfff00000
++#define		bEDCCA_H				0xf
++#define		bEDCCA_L				0xf0
++#define		bLambda_ED			0x300
++#define		bRxInitialGain			0x7f
++#define		bRxAntDivEn				0x80
++#define		bRxAGCAddressForLNA	0x7f00
++#define		bRxHighPowerFlow		0x8000
++#define		bRxAGCFreezeThres		0xc0000
++#define		bRxFreezeStep_AGC1	0x300000
++#define		bRxFreezeStep_AGC2	0xc00000
++#define		bRxFreezeStep_AGC3	0x3000000
++#define		bRxFreezeStep_AGC0	0xc000000
++#define		bRxRssi_Cmp_En			0x10000000
++#define		bRxQuickAGCEn			0x20000000
++#define		bRxAGCFreezeThresMode	0x40000000
++#define		bRxOverFlowCheckType	0x80000000
++#define		bRxAGCShift				0x7f
++#define		bTRSW_Tri_Only			0x80
++#define		bPowerThres			0x300
++#define		bRxAGCEn				0x1
++#define		bRxAGCTogetherEn		0x2
++#define		bRxAGCMin				0x4
++#define		bRxHP_Ini				0x7
++#define		bRxHP_TRLNA			0x70
++#define		bRxHP_RSSI				0x700
++#define		bRxHP_BBP1				0x7000
++#define		bRxHP_BBP2				0x70000
++#define		bRxHP_BBP3				0x700000
++#define		bRSSI_H					0x7f0000     /* the threshold for high power */
++#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
++#define		bRxSettle_TRSW			0x7
++#define		bRxSettle_LNA			0x38
++#define		bRxSettle_RSSI			0x1c0
++#define		bRxSettle_BBP			0xe00
++#define		bRxSettle_RxHP			0x7000
++#define		bRxSettle_AntSW_RSSI	0x38000
++#define		bRxSettle_AntSW		0xc0000
++#define		bRxProcessTime_DAGC	0x300000
++#define		bRxSettle_HSSI			0x400000
++#define		bRxProcessTime_BBPPW	0x800000
++#define		bRxAntennaPowerShift	0x3000000
++#define		bRSSITableSelect		0xc000000
++#define		bRxHP_Final				0x7000000
++#define		bRxHTSettle_BBP			0x7
++#define		bRxHTSettle_HSSI		0x8
++#define		bRxHTSettle_RxHP		0x70
++#define		bRxHTSettle_BBPPW		0x80
++#define		bRxHTSettle_Idle		0x300
++#define		bRxHTSettle_Reserved	0x1c00
++#define		bRxHTRxHPEn			0x8000
++#define		bRxHTAGCFreezeThres	0x30000
++#define		bRxHTAGCTogetherEn	0x40000
++#define		bRxHTAGCMin			0x80000
++#define		bRxHTAGCEn				0x100000
++#define		bRxHTDAGCEn			0x200000
++#define		bRxHTRxHP_BBP			0x1c00000
++#define		bRxHTRxHP_Final		0xe0000000
++#define		bRxPWRatioTH			0x3
++#define		bRxPWRatioEn			0x4
++#define		bRxMFHold				0x3800
++#define		bRxPD_Delay_TH1		0x38
++#define		bRxPD_Delay_TH2		0x1c0
++#define		bRxPD_DC_COUNT_MAX	0x600
++/* #define bRxMF_Hold               0x3800 */
++#define		bRxPD_Delay_TH			0x8000
++#define		bRxProcess_Delay		0xf0000
++#define		bRxSearchrange_GI2_Early	0x700000
++#define		bRxFrame_Guard_Counter_L	0x3800000
++#define		bRxSGI_Guard_L			0xc000000
++#define		bRxSGI_Search_L		0x30000000
++#define		bRxSGI_TH				0xc0000000
++#define		bDFSCnt0				0xff
++#define		bDFSCnt1				0xff00
++#define		bDFSFlag				0xf0000
++#define		bMFWeightSum			0x300000
++#define		bMinIdxTH				0x7f000000
++#define		bDAFormat				0x40000
++#define		bTxChEmuEnable		0x01000000
++#define		bTRSWIsolation_A		0x7f
++#define		bTRSWIsolation_B		0x7f00
++#define		bTRSWIsolation_C		0x7f0000
++#define		bTRSWIsolation_D		0x7f000000
++#define		bExtLNAGain				0x7c00
++
++/* 6. PageE(0xE00) */
++#define		bSTBCEn				0x4	/* Useless */
++#define		bAntennaMapping		0x10
++#define		bNss					0x20
++#define		bCFOAntSumD			0x200
++#define		bPHYCounterReset		0x8000000
++#define		bCFOReportGet			0x4000000
++#define		bOFDMContinueTx		0x10000000
++#define		bOFDMSingleCarrier		0x20000000
++#define		bOFDMSingleTone		0x40000000
++/* #define bRxPath1                 0x01 */
++/* #define bRxPath2                 0x02 */
++/* #define bRxPath3                 0x04 */
++/* #define bRxPath4                 0x08 */
++/* #define bTxPath1                 0x10 */
++/* #define bTxPath2                 0x20 */
++#define		bHTDetect			0x100
++#define		bCFOEn				0x10000
++#define		bCFOValue			0xfff00000
++#define		bSigTone_Re		0x3f
++#define		bSigTone_Im		0x7f00
++#define		bCounter_CCA		0xffff
++#define		bCounter_ParityFail	0xffff0000
++#define		bCounter_RateIllegal		0xffff
++#define		bCounter_CRC8Fail	0xffff0000
++#define		bCounter_MCSNoSupport	0xffff
++#define		bCounter_FastSync	0xffff
++#define		bShortCFO			0xfff
++#define		bShortCFOTLength	12   /* total */
++#define		bShortCFOFLength	11   /* fraction */
++#define		bLongCFO			0x7ff
++#define		bLongCFOTLength	11
++#define		bLongCFOFLength	11
++#define		bTailCFO			0x1fff
++#define		bTailCFOTLength		13
++#define		bTailCFOFLength		12
++#define		bmax_en_pwdB		0xffff
++#define		bCC_power_dB		0xffff0000
++#define		bnoise_pwdB		0xffff
++#define		bPowerMeasTLength	10
++#define		bPowerMeasFLength	3
++#define		bRx_HT_BW			0x1
++#define		bRxSC				0x6
++#define		bRx_HT				0x8
++#define		bNB_intf_det_on		0x1
++#define		bIntf_win_len_cfg	0x30
++#define		bNB_Intf_TH_cfg		0x1c0
++#define		bRFGain				0x3f
++#define		bTableSel			0x40
++#define		bTRSW				0x80
++#define		bRxSNR_A			0xff
++#define		bRxSNR_B			0xff00
++#define		bRxSNR_C			0xff0000
++#define		bRxSNR_D			0xff000000
++#define		bSNREVMTLength		8
++#define		bSNREVMFLength		1
++#define		bCSI1st				0xff
++#define		bCSI2nd				0xff00
++#define		bRxEVM1st			0xff0000
++#define		bRxEVM2nd			0xff000000
++#define		bSIGEVM			0xff
++#define		bPWDB				0xff00
++#define		bSGIEN				0x10000
++
++#define		bSFactorQAM1		0xf	/* Useless */
++#define		bSFactorQAM2		0xf0
++#define		bSFactorQAM3		0xf00
++#define		bSFactorQAM4		0xf000
++#define		bSFactorQAM5		0xf0000
++#define		bSFactorQAM6		0xf0000
++#define		bSFactorQAM7		0xf00000
++#define		bSFactorQAM8		0xf000000
++#define		bSFactorQAM9		0xf0000000
++#define		bCSIScheme			0x100000
++
++#define		bNoiseLvlTopSet		0x3	/* Useless */
++#define		bChSmooth			0x4
++#define		bChSmoothCfg1		0x38
++#define		bChSmoothCfg2		0x1c0
++#define		bChSmoothCfg3		0xe00
++#define		bChSmoothCfg4		0x7000
++#define		bMRCMode			0x800000
++#define		bTHEVMCfg			0x7000000
++
++#define		bLoopFitType		0x1	/* Useless */
++#define		bUpdCFO			0x40
++#define		bUpdCFOOffData		0x80
++#define		bAdvUpdCFO			0x100
++#define		bAdvTimeCtrl		0x800
++#define		bUpdClko			0x1000
++#define		bFC					0x6000
++#define		bTrackingMode		0x8000
++#define		bPhCmpEnable		0x10000
++#define		bUpdClkoLTF		0x20000
++#define		bComChCFO			0x40000
++#define		bCSIEstiMode		0x80000
++#define		bAdvUpdEqz			0x100000
++#define		bUChCfg				0x7000000
++#define		bUpdEqz			0x8000000
++
++/* Rx Pseduo noise */
++#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
++#define		bRxPesudoNoise_A		0xff
++#define		bRxPesudoNoise_B		0xff00
++#define		bRxPesudoNoise_C		0xff0000
++#define		bRxPesudoNoise_D		0xff000000
++#define		bPesudoNoiseState_A	0xffff
++#define		bPesudoNoiseState_B	0xffff0000
++#define		bPesudoNoiseState_C	0xffff
++#define		bPesudoNoiseState_D	0xffff0000
++
++/* 7. RF Register
++ * Zebra1 */
++#define		bZebra1_HSSIEnable		0x8		/* Useless */
++#define		bZebra1_TRxControl		0xc00
++#define		bZebra1_TRxGainSetting	0x07f
++#define		bZebra1_RxCorner		0xc00
++#define		bZebra1_TxChargePump	0x38
++#define		bZebra1_RxChargePump	0x7
++#define		bZebra1_ChannelNum	0xf80
++#define		bZebra1_TxLPFBW		0x400
++#define		bZebra1_RxLPFBW		0x600
++
++/* Zebra4 */
++#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
++#define		bRTL8256RegModeCtrl0	0x40
++#define		bRTL8256_TxLPFBW		0x18
++#define		bRTL8256_RxLPFBW		0x600
++
++/* RTL8258 */
++#define		bRTL8258_TxLPFBW		0xc	/* Useless */
++#define		bRTL8258_RxLPFBW		0xc00
++#define		bRTL8258_RSSILPFBW	0xc0
++
++
++/*
++ * Other Definition
++ *   */
++
++/* byte endable for sb_write */
++#define		bByte0				0x1	/* Useless */
++#define		bByte1				0x2
++#define		bByte2				0x4
++#define		bByte3				0x8
++#define		bWord0				0x3
++#define		bWord1				0xc
++#define		bDWord				0xf
++
++/* for PutRegsetting & GetRegSetting BitMask */
++#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
++#define		bMaskByte1			0xff00
++#define		bMaskByte2			0xff0000
++#define		bMaskByte3			0xff000000
++#define		bMaskHWord		0xffff0000
++#define		bMaskLWord			0x0000ffff
++#define		bMaskDWord		0xffffffff
++#define		bMaskH3Bytes		0xffffff00
++#define		bMask12Bits			0xfff
++#define		bMaskH4Bits			0xf0000000
++#define		bMaskOFDM_D		0xffc00000
++#define		bMaskCCK			0x3f3f3f3f
++
++
++#define		bEnable			0x1	/* Useless */
++#define		bDisable		0x0
++
++#define		LeftAntenna		0x0	/* Useless */
++#define		RightAntenna	0x1
++
++#define		tCheckTxStatus		500   /* 500ms */ /* Useless */
++#define		tUpdateRxCounter	100   /* 100ms */
++
++#define		rateCCK		0	/* Useless */
++#define		rateOFDM	1
++#define		rateHT		2
++
++/* define Register-End */
++#define		bPMAC_End			0x1ff	/* Useless */
++#define		bFPGAPHY0_End		0x8ff
++#define		bFPGAPHY1_End		0x9ff
++#define		bCCKPHY0_End		0xaff
++#define		bOFDMPHY0_End		0xcff
++#define		bOFDMPHY1_End		0xdff
++
++/* define max debug item in each debug page
++ * #define bMaxItem_FPGA_PHY0        0x9
++ * #define bMaxItem_FPGA_PHY1        0x3
++ * #define bMaxItem_PHY_11B          0x16
++ * #define bMaxItem_OFDM_PHY0        0x29
++ * #define bMaxItem_OFDM_PHY1        0x0 */
++
++#define		bPMACControl		0x0		/* Useless */
++#define		bWMACControl		0x1
++#define		bWNICControl		0x2
++
++#define		PathA			0x0	/* Useless */
++#define		PathB			0x1
++#define		PathC			0x2
++#define		PathD			0x3
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723BPwrSeq.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723BPwrSeq.h
+new file mode 100644
+index 000000000..1aec885cb
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723BPwrSeq.h
+@@ -0,0 +1,246 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef REALTEK_POWER_SEQUENCE_8723B
++#define REALTEK_POWER_SEQUENCE_8723B
++
++#include "HalPwrSeqCmd.h"
++
++/*
++	Check document WM-20130815-JackieLau-RTL8723B_Power_Architecture v08.vsd
++	There are 6 HW Power States:
++	0: POFF--Power Off
++	1: PDN--Power Down
++	2: CARDEMU--Card Emulation
++	3: ACT--Active Mode
++	4: LPS--Low Power State
++	5: SUS--Suspend
++
++	The transision from different states are defined below
++	TRANS_CARDEMU_TO_ACT
++	TRANS_ACT_TO_CARDEMU
++	TRANS_CARDEMU_TO_SUS
++	TRANS_SUS_TO_CARDEMU
++	TRANS_CARDEMU_TO_PDN
++	TRANS_ACT_TO_LPS
++	TRANS_LPS_TO_ACT
++
++	TRANS_END
++*/
++#define	RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS	26
++#define	RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS	15
++#define	RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS	15
++#define	RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS	15
++#define	RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS	15
++#define	RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS	15
++#define	RTL8723B_TRANS_ACT_TO_LPS_STEPS		15
++#define	RTL8723B_TRANS_LPS_TO_ACT_STEPS		15
++#define	RTL8723B_TRANS_ACT_TO_SWLPS_STEPS		22
++#define	RTL8723B_TRANS_SWLPS_TO_ACT_STEPS		15
++#define	RTL8723B_TRANS_END_STEPS		1
++
++
++#define RTL8723B_TRANS_CARDEMU_TO_ACT														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \
++	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/	\
++	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
++	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/	\
++	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
++	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	\
++	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/	\
++	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
++	{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
++	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
++	{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
++	{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
++	{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\
++	{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\
++
++
++#define RTL8723B_TRANS_ACT_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
++	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
++	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\
++	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
++	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
++
++
++#define RTL8723B_TRANS_CARDEMU_TO_SUS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
++
++#define RTL8723B_TRANS_SUS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
++
++#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
++	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
++
++#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
++
++
++#define RTL8723B_TRANS_CARDEMU_TO_PDN												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
++
++#define RTL8723B_TRANS_PDN_TO_CARDEMU												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
++
++#define RTL8723B_TRANS_ACT_TO_LPS														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
++	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
++	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
++	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
++
++
++#define RTL8723B_TRANS_LPS_TO_ACT															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
++	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
++	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
++	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
++	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
++
++
++#define RTL8723B_TRANS_ACT_TO_SWLPS														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable 32 K source*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/	\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*disable security engine*/	\
++	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x40},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
++	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TSF*/	\
++	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/	\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*Reset MCUFWDL register*/	\
++	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/	\
++	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*Reset CPU IO Wrapper*/	\
++	{0x0287, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*polling RXFF packet number = 0 */	\
++	{0x0286, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/*polling RXDMA idle */	\
++	{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Clear FW RPWM interrupt */\
++	{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW RPWM interrupt source*/\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*switch TSF to 32K*/\
++	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF stable*/\
++	{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW LPS*/	\
++	{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/*polling FW LPS ready */
++
++
++#define RTL8723B_TRANS_SWLPS_TO_ACT															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*switch TSF to 32K*/\
++	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1, enable security engine*/\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
++	{0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x09}, /*.	reset MAC rx state machine*/\
++	{0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x86}, /*.	reset MAC rx state machine*/\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/	\
++	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/	\
++	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/	\
++	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/	\
++	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/	\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */	\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
++
++#define RTL8723B_TRANS_END															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
++
++
++	extern WLAN_PWR_CFG rtl8723B_power_on_flow[RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723B_radio_off_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723B_card_disable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723B_card_enable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723B_suspend_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723B_resume_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723B_hwpdn_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723B_enter_lps_flow[RTL8723B_TRANS_ACT_TO_LPS_STEPS + RTL8723B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723B_leave_lps_flow[RTL8723B_TRANS_LPS_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723B_enter_swlps_flow[RTL8723B_TRANS_ACT_TO_SWLPS_STEPS + RTL8723B_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723B_leave_swlps_flow[RTL8723B_TRANS_SWLPS_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS];
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723DPhyCfg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723DPhyCfg.h
+new file mode 100644
+index 000000000..b89243551
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723DPhyCfg.h
+@@ -0,0 +1,115 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8723DPHYCFG_H__
++#define __INC_HAL8723DPHYCFG_H__
++
++/*--------------------------Define Parameters-------------------------------*/
++#define LOOP_LIMIT				5
++#define MAX_STALL_TIME			50		/* us */
++#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
++#define MAX_TXPWR_IDX_NMODE_92S	63
++#define Reset_Cnt_Limit			3
++
++#ifdef CONFIG_PCI_HCI
++	#define MAX_AGGR_NUM	0x0B
++#else
++	#define MAX_AGGR_NUM	0x07
++#endif /* CONFIG_PCI_HCI */
++
++
++/*--------------------------Define Parameters End-------------------------------*/
++
++
++/*------------------------------Define structure----------------------------*/
++
++/*------------------------------Define structure End----------------------------*/
++
++/*--------------------------Exported Function prototype---------------------*/
++u32
++PHY_QueryBBReg_8723D(
++		PADAPTER	Adapter,
++		u32		RegAddr,
++		u32		BitMask
++);
++
++void
++PHY_SetBBReg_8723D(
++		PADAPTER	Adapter,
++		u32		RegAddr,
++		u32		BitMask,
++		u32		Data
++);
++
++u32
++PHY_QueryRFReg_8723D(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				RegAddr,
++		u32				BitMask
++);
++
++void
++PHY_SetRFReg_8723D(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				RegAddr,
++		u32				BitMask,
++		u32				Data
++);
++
++/* MAC/BB/RF HAL config */
++int PHY_BBConfig8723D(PADAPTER	Adapter);
++
++int PHY_RFConfig8723D(PADAPTER	Adapter);
++
++s32 PHY_MACConfig8723D(PADAPTER padapter);
++
++int
++PHY_ConfigRFWithParaFile_8723D(
++		PADAPTER			Adapter,
++		u8				*pFileName,
++	enum rf_path				eRFPath
++);
++
++void
++PHY_SetTxPowerIndex_8723D(
++		PADAPTER			Adapter,
++		u32					PowerIndex,
++		enum rf_path			RFPath,
++		u8					Rate
++);
++
++void
++PHY_SetTxPowerLevel8723D(
++		PADAPTER		Adapter,
++		u8			channel
++);
++
++void
++PHY_SetSwChnlBWMode8723D(
++		PADAPTER			Adapter,
++		u8					channel,
++		enum channel_width	Bandwidth,
++		u8					Offset40,
++		u8					Offset80
++);
++
++void phy_set_rf_path_switch_8723d(
++		struct dm_struct		*phydm,
++		bool		bMain
++);
++/*--------------------------Exported Function prototype End---------------------*/
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723DPhyReg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723DPhyReg.h
+new file mode 100644
+index 000000000..036144a38
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723DPhyReg.h
+@@ -0,0 +1,1134 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8723DPHYREG_H__
++#define __INC_HAL8723DPHYREG_H__
++
++#define		rSYM_WLBT_PAPE_SEL		0x64
++/*
++ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
++ * 3. RF register 0x00-2E
++ * 4. Bit Mask for BB/RF register
++ * 5. Other definition for BB/RF R/W
++ *   */
++
++
++/*
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 1. Page1(0x100)
++ *   */
++#define		rPMAC_Reset					0x100
++#define		rPMAC_TxStart					0x104
++#define		rPMAC_TxLegacySIG				0x108
++#define		rPMAC_TxHTSIG1				0x10c
++#define		rPMAC_TxHTSIG2				0x110
++#define		rPMAC_PHYDebug				0x114
++#define		rPMAC_TxPacketNum				0x118
++#define		rPMAC_TxIdle					0x11c
++#define		rPMAC_TxMACHeader0			0x120
++#define		rPMAC_TxMACHeader1			0x124
++#define		rPMAC_TxMACHeader2			0x128
++#define		rPMAC_TxMACHeader3			0x12c
++#define		rPMAC_TxMACHeader4			0x130
++#define		rPMAC_TxMACHeader5			0x134
++#define		rPMAC_TxDataType				0x138
++#define		rPMAC_TxRandomSeed			0x13c
++#define		rPMAC_CCKPLCPPreamble			0x140
++#define		rPMAC_CCKPLCPHeader			0x144
++#define		rPMAC_CCKCRC16				0x148
++#define		rPMAC_OFDMRxCRC32OK			0x170
++#define		rPMAC_OFDMRxCRC32Er			0x174
++#define		rPMAC_OFDMRxParityEr			0x178
++#define		rPMAC_OFDMRxCRC8Er			0x17c
++#define		rPMAC_CCKCRxRC16Er			0x180
++#define		rPMAC_CCKCRxRC32Er			0x184
++#define		rPMAC_CCKCRxRC32OK			0x188
++#define		rPMAC_TxStatus					0x18c
++
++/*
++ * 2. Page2(0x200)
++ *
++ * The following two definition are only used for USB interface. */
++#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
++#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
++
++/*
++ * 3. Page8(0x800)
++ *   */
++#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC // RF BW Setting?? */
++
++#define		rFPGA0_TxInfo				0x804	/* Status report?? */
++#define		rFPGA0_PSDFunction			0x808
++
++#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
++
++#define		rFPGA0_RFTiming1			0x810	/* Useless now */
++#define		rFPGA0_RFTiming2			0x814
++
++#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
++#define		rFPGA0_XA_HSSIParameter2		0x824
++#define		rFPGA0_XB_HSSIParameter1		0x828
++#define		rFPGA0_XB_HSSIParameter2		0x82c
++#define		rTxAGC_B_Rate18_06				0x830
++#define		rTxAGC_B_Rate54_24				0x834
++#define		rTxAGC_B_CCK1_55_Mcs32		0x838
++#define		rTxAGC_B_Mcs03_Mcs00			0x83c
++
++#define		rTxAGC_B_Mcs07_Mcs04			0x848
++#define		rTxAGC_B_Mcs11_Mcs08			0x84c
++
++#define		rFPGA0_XA_LSSIParameter		0x840
++#define		rFPGA0_XB_LSSIParameter		0x844
++
++#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
++#define		rFPGA0_RFSleepUpParameter		0x854
++
++#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
++#define		rFPGA0_XCD_SwitchControl		0x85c
++
++#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
++#define		rFPGA0_XB_RFInterfaceOE		0x864
++
++#define		rTxAGC_B_Mcs15_Mcs12			0x868
++#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
++
++#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
++#define		rFPGA0_XCD_RFInterfaceSW		0x874
++
++#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
++#define		rFPGA0_XCD_RFParameter		0x87c
++
++#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
++#define		rFPGA0_AnalogParameter2		0x884
++#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
++#define		rFPGA0_AnalogParameter4		0x88c
++
++#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
++#define		rFPGA0_XB_LSSIReadBack		0x8a4
++#define		rFPGA0_XC_LSSIReadBack		0x8a8
++#define		rFPGA0_XD_LSSIReadBack		0x8ac
++
++#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
++#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
++#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
++#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now // RF Interface Readback Value */
++#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
++
++/*
++ * 4. Page9(0x900)
++ *   */
++#define	rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC // RF BW Setting?? */
++#define	rFPGA1_TxBlock				0x904	/* Useless now */
++#define	rFPGA1_DebugSelect			0x908	/* Useless now */
++#define	rFPGA1_TxInfo				0x90c	/* Useless now // Status report?? */
++#define	rDPDT_control				0x92c
++#define	rfe_ctrl_anta_src				0x930
++#define	rS0S1_PathSwitch			0x948
++#define	rBBrx_DFIR					0x954
++
++/*
++ * 5. PageA(0xA00)
++ *
++ * Set Control channel to upper or lower. These settings are required only for 40MHz */
++#define		rCCK0_System				0xa00
++
++#define		rCCK0_AFESetting			0xa04	/* Disable init gain now // Select RX path by RSSI */
++#define		rCCK0_CCA					0xa08	/* Disable init gain now // Init gain */
++
++#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
++#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
++
++#define		rCCK0_RxHP					0xa14
++
++#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
++#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
++
++#define		rCCK0_TxFilter1				0xa20
++#define		rCCK0_TxFilter2				0xa24
++#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
++#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
++#define		rCCK0_TRSSIReport		0xa50
++#define		rCCK0_RxReport			0xa54  /* 0xa57 */
++#define		rCCK0_FACounterLower		0xa5c  /* 0xa5b */
++#define		rCCK0_FACounterUpper		0xa58  /* 0xa5c */
++
++/*
++ * PageB(0xB00)
++ *   */
++#define rPdp_AntA						0xb00
++#define rPdp_AntA_4						0xb04
++#define rPdp_AntA_8						0xb08
++#define rPdp_AntA_C						0xb0c
++#define rPdp_AntA_10					0xb10
++#define rPdp_AntA_14					0xb14
++#define rPdp_AntA_18					0xb18
++#define rPdp_AntA_1C					0xb1c
++#define rPdp_AntA_20					0xb20
++#define rPdp_AntA_24					0xb24
++
++#define rConfig_Pmpd_AntA				0xb28
++#define rConfig_ram64x16				0xb2c
++
++#define rBndA							0xb30
++#define rHssiPar						0xb34
++
++#define rConfig_AntA					0xb68
++#define rConfig_AntB					0xb6c
++
++#define rPdp_AntB						0xb70
++#define rPdp_AntB_4						0xb74
++#define rPdp_AntB_8						0xb78
++#define rPdp_AntB_C						0xb7c
++#define rPdp_AntB_10					0xb80
++#define rPdp_AntB_14					0xb84
++#define rPdp_AntB_18					0xb88
++#define rPdp_AntB_1C					0xb8c
++#define rPdp_AntB_20					0xb90
++#define rPdp_AntB_24					0xb94
++
++#define rConfig_Pmpd_AntB				0xb98
++
++#define rBndB							0xba0
++
++#define rAPK							0xbd8
++#define rPm_Rx0_AntA					0xbdc
++#define rPm_Rx1_AntA					0xbe0
++#define rPm_Rx2_AntA					0xbe4
++#define rPm_Rx3_AntA					0xbe8
++#define rPm_Rx0_AntB					0xbec
++#define rPm_Rx1_AntB					0xbf0
++#define rPm_Rx2_AntB					0xbf4
++#define rPm_Rx3_AntB					0xbf8
++/*
++ * 6. PageC(0xC00)
++ *   */
++#define		rOFDM0_LSTF				0xc00
++
++#define		rOFDM0_TRxPathEnable		0xc04
++#define		rOFDM0_TRMuxPar			0xc08
++#define		rOFDM0_TRSWIsolation		0xc0c
++
++#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
++#define		rOFDM0_XARxIQImbalance		0xc14  /* RxIQ imbalance matrix */
++#define		rOFDM0_XBRxAFE		0xc18
++#define		rOFDM0_XBRxIQImbalance	0xc1c
++#define		rOFDM0_XCRxAFE		0xc20
++#define		rOFDM0_XCRxIQImbalance	0xc24
++#define		rOFDM0_XDRxAFE		0xc28
++#define		rOFDM0_XDRxIQImbalance	0xc2c
++
++#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	// DM tune init gain */
++#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
++#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
++#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
++
++#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
++#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
++#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
++#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
++
++#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
++#define		rOFDM0_XAAGCCore2			0xc54
++#define		rOFDM0_XBAGCCore1			0xc58
++#define		rOFDM0_XBAGCCore2			0xc5c
++#define		rOFDM0_XCAGCCore1			0xc60
++#define		rOFDM0_XCAGCCore2			0xc64
++#define		rOFDM0_XDAGCCore1			0xc68
++#define		rOFDM0_XDAGCCore2			0xc6c
++
++#define		rOFDM0_AGCParameter1			0xc70
++#define		rOFDM0_AGCParameter2			0xc74
++#define		rOFDM0_AGCRSSITable			0xc78
++#define		rOFDM0_HTSTFAGC				0xc7c
++
++#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
++#define		rOFDM0_XATxAFE				0xc84
++#define		rOFDM0_XBTxIQImbalance		0xc88
++#define		rOFDM0_XBTxAFE				0xc8c
++#define		rOFDM0_XCTxIQImbalance		0xc90
++#define		rOFDM0_XCTxAFE			0xc94
++#define		rOFDM0_XDTxIQImbalance		0xc98
++#define		rOFDM0_XDTxAFE				0xc9c
++
++#define		rOFDM0_RxIQExtAnta			0xca0
++#define		rOFDM0_TxCoeff1				0xca4
++#define		rOFDM0_TxCoeff2				0xca8
++#define		rOFDM0_TxCoeff3				0xcac
++#define		rOFDM0_TxCoeff4				0xcb0
++#define		rOFDM0_TxCoeff5				0xcb4
++#define		rOFDM0_TxCoeff6				0xcb8
++#define		rOFDM0_RxHPParameter			0xce0
++#define		rOFDM0_TxPseudoNoiseWgt		0xce4
++#define		rOFDM0_FrameSync				0xcf0
++#define		rOFDM0_DFSReport				0xcf4
++
++/*
++ * 7. PageD(0xD00)
++ *   */
++#define		rOFDM1_LSTF					0xd00
++#define		rOFDM1_TRxPathEnable			0xd04
++
++#define		rOFDM1_CFO						0xd08	/* No setting now */
++#define		rOFDM1_CSI1					0xd10
++#define		rOFDM1_SBD						0xd14
++#define		rOFDM1_CSI2					0xd18
++#define		rOFDM1_CFOTracking			0xd2c
++#define		rOFDM1_TRxMesaure1			0xd34
++#define		rOFDM1_IntfDet					0xd3c
++#define		rOFDM1_PseudoNoiseStateAB		0xd50
++#define		rOFDM1_PseudoNoiseStateCD		0xd54
++#define		rOFDM1_RxPseudoNoiseWgt		0xd58
++
++#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
++#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
++#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
++
++#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
++#define		rOFDM_ShortCFOCD				0xdb0
++#define		rOFDM_LongCFOAB				0xdb4
++#define		rOFDM_LongCFOCD				0xdb8
++#define		rOFDM_TailCFOAB				0xdbc
++#define		rOFDM_TailCFOCD				0xdc0
++#define		rOFDM_PWMeasure1		0xdc4
++#define		rOFDM_PWMeasure2		0xdc8
++#define		rOFDM_BWReport				0xdcc
++#define		rOFDM_AGCReport				0xdd0
++#define		rOFDM_RxSNR					0xdd4
++#define		rOFDM_RxEVMCSI				0xdd8
++#define		rOFDM_SIGReport				0xddc
++
++
++/*
++ * 8. PageE(0xE00)
++ *   */
++#define		rTxAGC_A_Rate18_06			0xe00
++#define		rTxAGC_A_Rate54_24			0xe04
++#define		rTxAGC_A_CCK1_Mcs32			0xe08
++#define		rTxAGC_A_Mcs03_Mcs00			0xe10
++#define		rTxAGC_A_Mcs07_Mcs04			0xe14
++#define		rTxAGC_A_Mcs11_Mcs08			0xe18
++#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
++
++#define		rFPGA0_IQK					0xe28
++#define		rTx_IQK_Tone_A				0xe30
++#define		rRx_IQK_Tone_A				0xe34
++#define		rTx_IQK_PI_A					0xe38
++#define		rRx_IQK_PI_A					0xe3c
++
++#define		rTx_IQK						0xe40
++#define		rRx_IQK						0xe44
++#define		rIQK_AGC_Pts					0xe48
++#define		rIQK_AGC_Rsp					0xe4c
++#define		rTx_IQK_Tone_B				0xe50
++#define		rRx_IQK_Tone_B				0xe54
++#define		rTx_IQK_PI_B					0xe58
++#define		rRx_IQK_PI_B					0xe5c
++#define		rIQK_AGC_Cont				0xe60
++
++#define		rBlue_Tooth					0xe6c
++#define		rRx_Wait_CCA					0xe70
++#define		rTx_CCK_RFON					0xe74
++#define		rTx_CCK_BBON				0xe78
++#define		rTx_OFDM_RFON				0xe7c
++#define		rTx_OFDM_BBON				0xe80
++#define		rTx_To_Rx					0xe84
++#define		rTx_To_Tx					0xe88
++#define		rRx_CCK						0xe8c
++
++#define		rTx_Power_Before_IQK_A		0xe94
++#define		rTx_Power_After_IQK_A			0xe9c
++
++#define		rRx_Power_Before_IQK_A		0xea0
++#define		rRx_Power_Before_IQK_A_2		0xea4
++#define		rRx_Power_After_IQK_A			0xea8
++#define		rRx_Power_After_IQK_A_2		0xeac
++
++#define		rTx_Power_Before_IQK_B		0xeb4
++#define		rTx_Power_After_IQK_B			0xebc
++
++#define		rRx_Power_Before_IQK_B		0xec0
++#define		rRx_Power_Before_IQK_B_2		0xec4
++#define		rRx_Power_After_IQK_B			0xec8
++#define		rRx_Power_After_IQK_B_2		0xecc
++
++#define		rRx_OFDM					0xed0
++#define		rRx_Wait_RIFS				0xed4
++#define		rRx_TO_Rx					0xed8
++#define		rStandby						0xedc
++#define		rSleep						0xee0
++#define		rPMPD_ANAEN				0xeec
++
++/*
++ * 7. RF Register 0x00-0x2E (RF 8256)
++ * RF-0222D 0x00-3F
++ *
++ * Zebra1 */
++#define		rZebra1_HSSIEnable				0x0	/* Useless now */
++#define		rZebra1_TRxEnable1				0x1
++#define		rZebra1_TRxEnable2				0x2
++#define		rZebra1_AGC					0x4
++#define		rZebra1_ChargePump			0x5
++#define		rZebra1_Channel				0x7	/* RF channel switch */
++
++/* #endif */
++#define		rZebra1_TxGain					0x8	/* Useless now */
++#define		rZebra1_TxLPF					0x9
++#define		rZebra1_RxLPF					0xb
++#define		rZebra1_RxHPFCorner			0xc
++
++/* Zebra4 */
++#define		rGlobalCtrl						0	/* Useless now */
++#define		rRTL8256_TxLPF					19
++#define		rRTL8256_RxLPF					11
++
++/* RTL8258 */
++#define		rRTL8258_TxLPF					0x11	/* Useless now */
++#define		rRTL8258_RxLPF					0x13
++#define		rRTL8258_RSSILPF				0xa
++
++/*
++ * RL6052 Register definition
++ *   */
++#define		RF_AC						0x00	/* */
++
++#define		RF_IQADJ_G1				0x01	/* */
++#define		RF_IQADJ_G2				0x02	/* */
++#define		RF_BS_PA_APSET_G1_G4		0x03
++#define		RF_BS_PA_APSET_G5_G8		0x04
++#define		RF_POW_TRSW				0x05	/* */
++
++#define		RF_GAIN_RX					0x06	/* */
++#define		RF_GAIN_TX					0x07	/* */
++
++#define		RF_TXM_IDAC				0x08	/* */
++#define		RF_IPA_G					0x09	/* */
++#define		RF_TXBIAS_G				0x0A
++#define		RF_TXPA_AG					0x0B
++#define		RF_IPA_A					0x0C	/* */
++#define		RF_TXBIAS_A				0x0D
++#define		RF_BS_PA_APSET_G9_G11	0x0E
++#define		RF_BS_IQGEN				0x0F	/* */
++
++#define		RF_MODE1					0x10	/* */
++#define		RF_MODE2					0x11	/* */
++
++#define		RF_RX_AGC_HP				0x12	/* */
++#define		RF_TX_AGC					0x13	/* */
++#define		RF_BIAS						0x14	/* */
++#define		RF_IPA						0x15	/* */
++#define		RF_TXBIAS					0x16
++#define		RF_POW_ABILITY			0x17	/* */
++#define		RF_MODE_AG				0x18	/* */
++#define		rRfChannel					0x18	/* RF channel and BW switch */
++#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
++#define		RF_TOP						0x19	/* */
++
++#define		RF_RX_G1					0x1A	/* */
++#define		RF_RX_G2					0x1B	/* */
++
++#define		RF_RX_BB2					0x1C	/* */
++#define		RF_RX_BB1					0x1D	/* */
++
++#define		RF_RCK1					0x1E	/* */
++#define		RF_RCK2					0x1F	/* */
++
++#define		RF_TX_G1					0x20	/* */
++#define		RF_TX_G2					0x21	/* */
++#define		RF_TX_G3					0x22	/* */
++
++#define		RF_TX_BB1					0x23	/* */
++
++#define		RF_T_METER					0x24	/* */
++
++#define		RF_SYN_G1					0x25	/* RF TX Power control */
++#define		RF_SYN_G2					0x26	/* RF TX Power control */
++#define		RF_SYN_G3					0x27	/* RF TX Power control */
++#define		RF_SYN_G4					0x28	/* RF TX Power control */
++#define		RF_SYN_G5					0x29	/* RF TX Power control */
++#define		RF_SYN_G6					0x2A	/* RF TX Power control */
++#define		RF_SYN_G7					0x2B	/* RF TX Power control */
++#define		RF_SYN_G8					0x2C	/* RF TX Power control */
++
++#define		RF_RCK_OS					0x30	/* RF TX PA control */
++
++#define		RF_TXPA_G1					0x31	/* RF TX PA control */
++#define		RF_TXPA_G2					0x32	/* RF TX PA control */
++#define		RF_TXPA_G3					0x33	/* RF TX PA control */
++#define	RF_TX_BIAS_A				0x35
++#define	RF_TX_BIAS_D				0x36
++#define	RF_LOBF_9					0x38
++#define	RF_RXRF_A3					0x3C	/*	 */
++#define	RF_TRSW					0x3F
++
++#define	RF_TXRF_A2					0x41
++#define	RF_T_METER_88E				0x42
++#define	RF_TXPA_G4					0x46
++#define	RF_TXPA_A4					0x4B
++#define	RF_0x52					0x52
++#define	RF_WE_LUT					0xEF
++#define	RF_S0S1					0xB0
++
++/*
++ * Bit Mask
++ *
++ * 1. Page1(0x100) */
++#define		bBBResetB						0x100	/* Useless now? */
++#define		bGlobalResetB					0x200
++#define		bOFDMTxStart					0x4
++#define		bCCKTxStart						0x8
++#define		bCRC32Debug					0x100
++#define		bPMACLoopback					0x10
++#define		bTxLSIG							0xffffff
++#define		bOFDMTxRate					0xf
++#define		bOFDMTxReserved				0x10
++#define		bOFDMTxLength					0x1ffe0
++#define		bOFDMTxParity					0x20000
++#define		bTxHTSIG1						0xffffff
++#define		bTxHTMCSRate					0x7f
++#define		bTxHTBW						0x80
++#define		bTxHTLength					0xffff00
++#define		bTxHTSIG2						0xffffff
++#define		bTxHTSmoothing					0x1
++#define		bTxHTSounding					0x2
++#define		bTxHTReserved					0x4
++#define		bTxHTAggreation				0x8
++#define		bTxHTSTBC						0x30
++#define		bTxHTAdvanceCoding			0x40
++#define		bTxHTShortGI					0x80
++#define		bTxHTNumberHT_LTF			0x300
++#define		bTxHTCRC8						0x3fc00
++#define		bCounterReset					0x10000
++#define		bNumOfOFDMTx					0xffff
++#define		bNumOfCCKTx					0xffff0000
++#define		bTxIdleInterval					0xffff
++#define		bOFDMService					0xffff0000
++#define		bTxMACHeader					0xffffffff
++#define		bTxDataInit						0xff
++#define		bTxHTMode						0x100
++#define		bTxDataType					0x30000
++#define		bTxRandomSeed					0xffffffff
++#define		bCCKTxPreamble					0x1
++#define		bCCKTxSFD						0xffff0000
++#define		bCCKTxSIG						0xff
++#define		bCCKTxService					0xff00
++#define		bCCKLengthExt					0x8000
++#define		bCCKTxLength					0xffff0000
++#define		bCCKTxCRC16					0xffff
++#define		bCCKTxStatus					0x1
++#define		bOFDMTxStatus					0x2
++
++#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
++#define		RF_TX_GAIN_OFFSET_8723D(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0))
++
++/* 2. Page8(0x800) */
++#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
++#define		bJapanMode						0x2
++#define		bCCKTxSC						0x30
++#define		bCCKEn							0x1000000
++#define		bOFDMEn						0x2000000
++
++#define		bOFDMRxADCPhase           0x10000	/* Useless now */
++#define		bOFDMTxDACPhase		0x40000
++#define		bXATxAGC			0x3f
++
++#define		bAntennaSelect		0x0300
++
++#define		bXBTxAGC                 0xf00	/* Reg 80c rFPGA0_TxGainStage */
++#define		bXCTxAGC			0xf000
++#define		bXDTxAGC			0xf0000
++
++#define		bPAStart                 0xf0000000	/* Useless now */
++#define		bTRStart			0x00f00000
++#define		bRFStart			0x0000f000
++#define		bBBStart			0x000000f0
++#define		bBBCCKStart		0x0000000f
++#define		bPAEnd                    0xf          /* Reg0x814 */
++#define		bTREnd			0x0f000000
++#define		bRFEnd			0x000f0000
++#define		bCCAMask                  0x000000f0   /* T2R */
++#define		bR2RCCAMask		0x00000f00
++#define		bHSSI_R2TDelay		0xf8000000
++#define		bHSSI_T2RDelay		0xf80000
++#define		bContTxHSSI              0x400     /* chane gain at continue Tx */
++#define		bIGFromCCK		0x200
++#define		bAGCAddress		0x3f
++#define		bRxHPTx			0x7000
++#define		bRxHPT2R			0x38000
++#define		bRxHPCCKIni		0xc0000
++#define		bAGCTxCode		0xc00000
++#define		bAGCRxCode		0x300000
++
++#define		b3WireDataLength         0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
++#define		b3WireAddressLength		0x400
++
++#define		b3WireRFPowerDown         0x1	/* Useless now
++ * #define bHWSISelect		0x8 */
++#define		b5GPAPEPolarity		0x40000000
++#define		b2GPAPEPolarity		0x80000000
++#define		bRFSW_TxDefaultAnt		0x3
++#define		bRFSW_TxOptionAnt		0x30
++#define		bRFSW_RxDefaultAnt		0x300
++#define		bRFSW_RxOptionAnt		0x3000
++#define		bRFSI_3WireData		0x1
++#define		bRFSI_3WireClock		0x2
++#define		bRFSI_3WireLoad		0x4
++#define		bRFSI_3WireRW		0x8
++#define		bRFSI_3Wire			0xf
++
++#define		bRFSI_RFENV              0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
++
++#define		bRFSI_TRSW               0x20	/* Useless now */
++#define		bRFSI_TRSWB		0x40
++#define		bRFSI_ANTSW		0x100
++#define		bRFSI_ANTSWB		0x200
++#define		bRFSI_PAPE			0x400
++#define		bRFSI_PAPE5G		0x800
++#define		bBandSelect			0x1
++#define		bHTSIG2_GI			0x80
++#define		bHTSIG2_Smoothing		0x01
++#define		bHTSIG2_Sounding		0x02
++#define		bHTSIG2_Aggreaton		0x08
++#define		bHTSIG2_STBC		0x30
++#define		bHTSIG2_AdvCoding		0x40
++#define		bHTSIG2_NumOfHTLTF	0x300
++#define		bHTSIG2_CRC8		0x3fc
++#define		bHTSIG1_MCS		0x7f
++#define		bHTSIG1_BandWidth		0x80
++#define		bHTSIG1_HTLength		0xffff
++#define		bLSIG_Rate			0xf
++#define		bLSIG_Reserved		0x10
++#define		bLSIG_Length		0x1fffe
++#define		bLSIG_Parity			0x20
++#define		bCCKRxPhase		0x4
++
++#define		bLSSIReadAddress          0x7f800000   /* T65 RF */
++
++#define		bLSSIReadEdge             0x80000000   /* LSSI "Read" edge signal */
++
++#define		bLSSIReadBackData         0xfffff		/* T65 RF */
++
++#define		bLSSIReadOKFlag           0x1000	/* Useless now */
++#define		bCCKSampleRate            0x8       /* 0: 44MHz, 1:88MHz     */
++#define		bRegulator0Standby		0x1
++#define		bRegulatorPLLStandby		0x2
++#define		bRegulator1Standby		0x4
++#define		bPLLPowerUp		0x8
++#define		bDPLLPowerUp		0x10
++#define		bDA10PowerUp		0x20
++#define		bAD7PowerUp		0x200
++#define		bDA6PowerUp		0x2000
++#define		bXtalPowerUp		0x4000
++#define		b40MDClkPowerUP		0x8000
++#define		bDA6DebugMode		0x20000
++#define		bDA6Swing			0x380000
++
++#define		bADClkPhase               0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
++
++#define		b80MClkDelay              0x18000000	/* Useless */
++#define		bAFEWatchDogEnable		0x20000000
++
++#define		bXtalCap01                0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
++#define		bXtalCap23			0x3
++#define		bXtalCap92x					0x0f000000
++#define		bXtalCap			0x0f000000
++
++#define		bIntDifClkEnable          0x400	/* Useless */
++#define		bExtSigClkEnable		0x800
++#define		bBandgapMbiasPowerUp	0x10000
++#define		bAD11SHGain		0xc0000
++#define		bAD11InputRange		0x700000
++#define		bAD11OPCurrent		0x3800000
++#define		bIPathLoopback		0x4000000
++#define		bQPathLoopback		0x8000000
++#define		bAFELoopback		0x10000000
++#define		bDA10Swing		0x7e0
++#define		bDA10Reverse		0x800
++#define		bDAClkSource		0x1000
++#define		bAD7InputRange		0x6000
++#define		bAD7Gain			0x38000
++#define		bAD7OutputCMMode		0x40000
++#define		bAD7InputCMMode		0x380000
++#define		bAD7Current			0xc00000
++#define		bRegulatorAdjust		0x7000000
++#define		bAD11PowerUpAtTx		0x1
++#define		bDA10PSAtTx		0x10
++#define		bAD11PowerUpAtRx		0x100
++#define		bDA10PSAtRx		0x1000
++#define		bCCKRxAGCFormat		0x200
++#define		bPSDFFTSamplepPoint		0xc000
++#define		bPSDAverageNum		0x3000
++#define		bIQPathControl		0xc00
++#define		bPSDFreq			0x3ff
++#define		bPSDAntennaPath		0x30
++#define		bPSDIQSwitch		0x40
++#define		bPSDRxTrigger		0x400000
++#define		bPSDTxTrigger		0x80000000
++#define		bPSDSineToneScale		0x7f000000
++#define		bPSDReport			0xffff
++
++/* 3. Page9(0x900) */
++#define		bOFDMTxSC                 0x30000000	/* Useless */
++#define		bCCKTxOn			0x1
++#define		bOFDMTxOn		0x2
++#define		bDebugPage                0xfff  /* reset debug page and also HWord, LWord */
++#define		bDebugItem                0xff   /* reset debug page and LWord */
++#define		bAntL			0x10
++#define		bAntNonHT				0x100
++#define		bAntHT1			0x1000
++#define		bAntHT2			0x10000
++#define		bAntHT1S1			0x100000
++#define		bAntNonHTS1		0x1000000
++
++/* 4. PageA(0xA00) */
++#define		bCCKBBMode				0x3	/* Useless */
++#define		bCCKTxPowerSaving		0x80
++#define		bCCKRxPowerSaving		0x40
++
++#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
++
++#define		bCCKScramble			0x8	/* Useless */
++#define		bCCKAntDiversity		0x8000
++#define		bCCKCarrierRecovery		0x4000
++#define		bCCKTxRate				0x3000
++#define		bCCKDCCancel			0x0800
++#define		bCCKISICancel			0x0400
++#define		bCCKMatchFilter			0x0200
++#define		bCCKEqualizer			0x0100
++#define		bCCKPreambleDetect		0x800000
++#define		bCCKFastFalseCCA		0x400000
++#define		bCCKChEstStart			0x300000
++#define		bCCKCCACount			0x080000
++#define		bCCKcs_lim				0x070000
++#define		bCCKBistMode			0x80000000
++#define		bCCKCCAMask			0x40000000
++#define		bCCKTxDACPhase		0x4
++#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
++#define		bCCKr_cp_mode0		0x0100
++#define		bCCKTxDCOffset			0xf0
++#define		bCCKRxDCOffset			0xf
++#define		bCCKCCAMode			0xc000
++#define		bCCKFalseCS_lim			0x3f00
++#define		bCCKCS_ratio			0xc00000
++#define		bCCKCorgBit_sel			0x300000
++#define		bCCKPD_lim				0x0f0000
++#define		bCCKNewCCA			0x80000000
++#define		bCCKRxHPofIG			0x8000
++#define		bCCKRxIG				0x7f00
++#define		bCCKLNAPolarity			0x800000
++#define		bCCKRx1stGain			0x7f0000
++#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
++#define		bCCKRxAGCSatLevel		0x1f000000
++#define		bCCKRxAGCSatCount		0xe0
++#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
++#define		bCCKFixedRxAGC			0x8000
++/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
++#define		bCCKAntennaPolarity		0x2000
++#define		bCCKTxFilterType		0x0c00
++#define		bCCKRxAGCReportType	0x0300
++#define		bCCKRxDAGCEn			0x80000000
++#define		bCCKRxDAGCPeriod		0x20000000
++#define		bCCKRxDAGCSatLevel		0x1f000000
++#define		bCCKTimingRecovery		0x800000
++#define		bCCKTxC0				0x3f0000
++#define		bCCKTxC1				0x3f000000
++#define		bCCKTxC2				0x3f
++#define		bCCKTxC3				0x3f00
++#define		bCCKTxC4				0x3f0000
++#define		bCCKTxC5				0x3f000000
++#define		bCCKTxC6				0x3f
++#define		bCCKTxC7				0x3f00
++#define		bCCKDebugPort			0xff0000
++#define		bCCKDACDebug			0x0f000000
++#define		bCCKFalseAlarmEnable	0x8000
++#define		bCCKFalseAlarmRead		0x4000
++#define		bCCKTRSSI				0x7f
++#define		bCCKRxAGCReport		0xfe
++#define		bCCKRxReport_AntSel	0x80000000
++#define		bCCKRxReport_MFOff		0x40000000
++#define		bCCKRxRxReport_SQLoss	0x20000000
++#define		bCCKRxReport_Pktloss	0x10000000
++#define		bCCKRxReport_Lockedbit	0x08000000
++#define		bCCKRxReport_RateError	0x04000000
++#define		bCCKRxReport_RxRate	0x03000000
++#define		bCCKRxFACounterLower	0xff
++#define		bCCKRxFACounterUpper	0xff000000
++#define		bCCKRxHPAGCStart		0xe000
++#define		bCCKRxHPAGCFinal		0x1c00
++#define		bCCKRxFalseAlarmEnable	0x8000
++#define		bCCKFACounterFreeze	0x4000
++#define		bCCKTxPathSel			0x10000000
++#define		bCCKDefaultRxPath		0xc000000
++#define		bCCKOptionRxPath		0x3000000
++
++/* 5. PageC(0xC00) */
++#define		bNumOfSTF				0x3	/* Useless */
++#define		bShift_L					0xc0
++#define		bGI_TH					0xc
++#define		bRxPathA				0x1
++#define		bRxPathB				0x2
++#define		bRxPathC				0x4
++#define		bRxPathD				0x8
++#define		bTxPathA				0x1
++#define		bTxPathB				0x2
++#define		bTxPathC				0x4
++#define		bTxPathD				0x8
++#define		bTRSSIFreq				0x200
++#define		bADCBackoff				0x3000
++#define		bDFIRBackoff			0xc000
++#define		bTRSSILatchPhase		0x10000
++#define		bRxIDCOffset			0xff
++#define		bRxQDCOffset			0xff00
++#define		bRxDFIRMode			0x1800000
++#define		bRxDCNFType			0xe000000
++#define		bRXIQImb_A				0x3ff
++#define		bRXIQImb_B				0xfc00
++#define		bRXIQImb_C				0x3f0000
++#define		bRXIQImb_D				0xffc00000
++#define		bDC_dc_Notch			0x60000
++#define		bRxNBINotch			0x1f000000
++#define		bPD_TH					0xf
++#define		bPD_TH_Opt2			0xc000
++#define		bPWED_TH				0x700
++#define		bIfMF_Win_L			0x800
++#define		bPD_Option				0x1000
++#define		bMF_Win_L				0xe000
++#define		bBW_Search_L			0x30000
++#define		bwin_enh_L				0xc0000
++#define		bBW_TH					0x700000
++#define		bED_TH2				0x3800000
++#define		bBW_option				0x4000000
++#define		bRatio_TH				0x18000000
++#define		bWindow_L				0xe0000000
++#define		bSBD_Option				0x1
++#define		bFrame_TH				0x1c
++#define		bFS_Option				0x60
++#define		bDC_Slope_check		0x80
++#define		bFGuard_Counter_DC_L	0xe00
++#define		bFrame_Weight_Short	0x7000
++#define		bSub_Tune				0xe00000
++#define		bFrame_DC_Length		0xe000000
++#define		bSBD_start_offset		0x30000000
++#define		bFrame_TH_2			0x7
++#define		bFrame_GI2_TH			0x38
++#define		bGI2_Sync_en			0x40
++#define		bSarch_Short_Early		0x300
++#define		bSarch_Short_Late		0xc00
++#define		bSarch_GI2_Late		0x70000
++#define		bCFOAntSum				0x1
++#define		bCFOAcc				0x2
++#define		bCFOStartOffset			0xc
++#define		bCFOLookBack			0x70
++#define		bCFOSumWeight			0x80
++#define		bDAGCEnable			0x10000
++#define		bTXIQImb_A				0x3ff
++#define		bTXIQImb_B				0xfc00
++#define		bTXIQImb_C				0x3f0000
++#define		bTXIQImb_D				0xffc00000
++#define		bTxIDCOffset			0xff
++#define		bTxQDCOffset			0xff00
++#define		bTxDFIRMode			0x10000
++#define		bTxPesudoNoiseOn		0x4000000
++#define		bTxPesudoNoise_A		0xff
++#define		bTxPesudoNoise_B		0xff00
++#define		bTxPesudoNoise_C		0xff0000
++#define		bTxPesudoNoise_D		0xff000000
++#define		bCCADropOption			0x20000
++#define		bCCADropThres			0xfff00000
++#define		bEDCCA_H				0xf
++#define		bEDCCA_L				0xf0
++#define		bLambda_ED			0x300
++#define		bRxInitialGain			0x7f
++#define		bRxAntDivEn				0x80
++#define		bRxAGCAddressForLNA	0x7f00
++#define		bRxHighPowerFlow		0x8000
++#define		bRxAGCFreezeThres		0xc0000
++#define		bRxFreezeStep_AGC1	0x300000
++#define		bRxFreezeStep_AGC2	0xc00000
++#define		bRxFreezeStep_AGC3	0x3000000
++#define		bRxFreezeStep_AGC0	0xc000000
++#define		bRxRssi_Cmp_En			0x10000000
++#define		bRxQuickAGCEn			0x20000000
++#define		bRxAGCFreezeThresMode	0x40000000
++#define		bRxOverFlowCheckType	0x80000000
++#define		bRxAGCShift				0x7f
++#define		bTRSW_Tri_Only			0x80
++#define		bPowerThres			0x300
++#define		bRxAGCEn				0x1
++#define		bRxAGCTogetherEn		0x2
++#define		bRxAGCMin				0x4
++#define		bRxHP_Ini				0x7
++#define		bRxHP_TRLNA			0x70
++#define		bRxHP_RSSI				0x700
++#define		bRxHP_BBP1				0x7000
++#define		bRxHP_BBP2				0x70000
++#define		bRxHP_BBP3				0x700000
++#define		bRSSI_H					0x7f0000     /* the threshold for high power */
++#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
++#define		bRxSettle_TRSW			0x7
++#define		bRxSettle_LNA			0x38
++#define		bRxSettle_RSSI			0x1c0
++#define		bRxSettle_BBP			0xe00
++#define		bRxSettle_RxHP			0x7000
++#define		bRxSettle_AntSW_RSSI	0x38000
++#define		bRxSettle_AntSW		0xc0000
++#define		bRxProcessTime_DAGC	0x300000
++#define		bRxSettle_HSSI			0x400000
++#define		bRxProcessTime_BBPPW	0x800000
++#define		bRxAntennaPowerShift	0x3000000
++#define		bRSSITableSelect		0xc000000
++#define		bRxHP_Final				0x7000000
++#define		bRxHTSettle_BBP			0x7
++#define		bRxHTSettle_HSSI		0x8
++#define		bRxHTSettle_RxHP		0x70
++#define		bRxHTSettle_BBPPW		0x80
++#define		bRxHTSettle_Idle		0x300
++#define		bRxHTSettle_Reserved	0x1c00
++#define		bRxHTRxHPEn			0x8000
++#define		bRxHTAGCFreezeThres	0x30000
++#define		bRxHTAGCTogetherEn	0x40000
++#define		bRxHTAGCMin			0x80000
++#define		bRxHTAGCEn				0x100000
++#define		bRxHTDAGCEn			0x200000
++#define		bRxHTRxHP_BBP			0x1c00000
++#define		bRxHTRxHP_Final		0xe0000000
++#define		bRxPWRatioTH			0x3
++#define		bRxPWRatioEn			0x4
++#define		bRxMFHold				0x3800
++#define		bRxPD_Delay_TH1		0x38
++#define		bRxPD_Delay_TH2		0x1c0
++#define		bRxPD_DC_COUNT_MAX	0x600
++/* #define bRxMF_Hold               0x3800 */
++#define		bRxPD_Delay_TH			0x8000
++#define		bRxProcess_Delay		0xf0000
++#define		bRxSearchrange_GI2_Early	0x700000
++#define		bRxFrame_Guard_Counter_L	0x3800000
++#define		bRxSGI_Guard_L			0xc000000
++#define		bRxSGI_Search_L		0x30000000
++#define		bRxSGI_TH				0xc0000000
++#define		bDFSCnt0				0xff
++#define		bDFSCnt1				0xff00
++#define		bDFSFlag				0xf0000
++#define		bMFWeightSum			0x300000
++#define		bMinIdxTH				0x7f000000
++#define		bDAFormat				0x40000
++#define		bTxChEmuEnable		0x01000000
++#define		bTRSWIsolation_A		0x7f
++#define		bTRSWIsolation_B		0x7f00
++#define		bTRSWIsolation_C		0x7f0000
++#define		bTRSWIsolation_D		0x7f000000
++#define		bExtLNAGain				0x7c00
++
++/* 6. PageE(0xE00) */
++#define		bSTBCEn				0x4	/* Useless */
++#define		bAntennaMapping		0x10
++#define		bNss					0x20
++#define		bCFOAntSumD			0x200
++#define		bPHYCounterReset		0x8000000
++#define		bCFOReportGet			0x4000000
++#define		bOFDMContinueTx		0x10000000
++#define		bOFDMSingleCarrier		0x20000000
++#define		bOFDMSingleTone		0x40000000
++/* #define bRxPath1                 0x01 */
++/* #define bRxPath2                 0x02 */
++/* #define bRxPath3                 0x04 */
++/* #define bRxPath4                 0x08 */
++/* #define bTxPath1                 0x10 */
++/* #define bTxPath2                 0x20 */
++#define		bHTDetect			0x100
++#define		bCFOEn				0x10000
++#define		bCFOValue			0xfff00000
++#define		bSigTone_Re		0x3f
++#define		bSigTone_Im		0x7f00
++#define		bCounter_CCA		0xffff
++#define		bCounter_ParityFail	0xffff0000
++#define		bCounter_RateIllegal		0xffff
++#define		bCounter_CRC8Fail	0xffff0000
++#define		bCounter_MCSNoSupport	0xffff
++#define		bCounter_FastSync	0xffff
++#define		bShortCFO			0xfff
++#define		bShortCFOTLength	12   /* total */
++#define		bShortCFOFLength	11   /* fraction */
++#define		bLongCFO			0x7ff
++#define		bLongCFOTLength	11
++#define		bLongCFOFLength	11
++#define		bTailCFO			0x1fff
++#define		bTailCFOTLength		13
++#define		bTailCFOFLength		12
++#define		bmax_en_pwdB		0xffff
++#define		bCC_power_dB		0xffff0000
++#define		bnoise_pwdB		0xffff
++#define		bPowerMeasTLength	10
++#define		bPowerMeasFLength	3
++#define		bRx_HT_BW			0x1
++#define		bRxSC				0x6
++#define		bRx_HT				0x8
++#define		bNB_intf_det_on		0x1
++#define		bIntf_win_len_cfg	0x30
++#define		bNB_Intf_TH_cfg		0x1c0
++#define		bRFGain				0x3f
++#define		bTableSel			0x40
++#define		bTRSW				0x80
++#define		bRxSNR_A			0xff
++#define		bRxSNR_B			0xff00
++#define		bRxSNR_C			0xff0000
++#define		bRxSNR_D			0xff000000
++#define		bSNREVMTLength		8
++#define		bSNREVMFLength		1
++#define		bCSI1st				0xff
++#define		bCSI2nd				0xff00
++#define		bRxEVM1st			0xff0000
++#define		bRxEVM2nd			0xff000000
++#define		bSIGEVM			0xff
++#define		bPWDB				0xff00
++#define		bSGIEN				0x10000
++
++#define		bSFactorQAM1		0xf	/* Useless */
++#define		bSFactorQAM2		0xf0
++#define		bSFactorQAM3		0xf00
++#define		bSFactorQAM4		0xf000
++#define		bSFactorQAM5		0xf0000
++#define		bSFactorQAM6		0xf0000
++#define		bSFactorQAM7		0xf00000
++#define		bSFactorQAM8		0xf000000
++#define		bSFactorQAM9		0xf0000000
++#define		bCSIScheme			0x100000
++
++#define		bNoiseLvlTopSet		0x3	/* Useless */
++#define		bChSmooth			0x4
++#define		bChSmoothCfg1		0x38
++#define		bChSmoothCfg2		0x1c0
++#define		bChSmoothCfg3		0xe00
++#define		bChSmoothCfg4		0x7000
++#define		bMRCMode			0x800000
++#define		bTHEVMCfg			0x7000000
++
++#define		bLoopFitType		0x1	/* Useless */
++#define		bUpdCFO			0x40
++#define		bUpdCFOOffData		0x80
++#define		bAdvUpdCFO			0x100
++#define		bAdvTimeCtrl		0x800
++#define		bUpdClko			0x1000
++#define		bFC					0x6000
++#define		bTrackingMode		0x8000
++#define		bPhCmpEnable		0x10000
++#define		bUpdClkoLTF		0x20000
++#define		bComChCFO			0x40000
++#define		bCSIEstiMode		0x80000
++#define		bAdvUpdEqz			0x100000
++#define		bUChCfg				0x7000000
++#define		bUpdEqz			0x8000000
++
++/* Rx Pseduo noise */
++#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
++#define		bRxPesudoNoise_A		0xff
++#define		bRxPesudoNoise_B		0xff00
++#define		bRxPesudoNoise_C		0xff0000
++#define		bRxPesudoNoise_D		0xff000000
++#define		bPesudoNoiseState_A	0xffff
++#define		bPesudoNoiseState_B	0xffff0000
++#define		bPesudoNoiseState_C	0xffff
++#define		bPesudoNoiseState_D	0xffff0000
++
++/* 7. RF Register
++ * Zebra1 */
++#define		bZebra1_HSSIEnable		0x8		/* Useless */
++#define		bZebra1_TRxControl		0xc00
++#define		bZebra1_TRxGainSetting	0x07f
++#define		bZebra1_RxCorner		0xc00
++#define		bZebra1_TxChargePump	0x38
++#define		bZebra1_RxChargePump	0x7
++#define		bZebra1_ChannelNum	0xf80
++#define		bZebra1_TxLPFBW		0x400
++#define		bZebra1_RxLPFBW		0x600
++
++/* Zebra4 */
++#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
++#define		bRTL8256RegModeCtrl0	0x40
++#define		bRTL8256_TxLPFBW		0x18
++#define		bRTL8256_RxLPFBW		0x600
++
++/* RTL8258 */
++#define		bRTL8258_TxLPFBW		0xc	/* Useless */
++#define		bRTL8258_RxLPFBW		0xc00
++#define		bRTL8258_RSSILPFBW	0xc0
++
++
++/*
++ * Other Definition
++ *   */
++
++/* byte endable for sb_write */
++#define		bByte0				0x1	/* Useless */
++#define		bByte1				0x2
++#define		bByte2				0x4
++#define		bByte3				0x8
++#define		bWord0				0x3
++#define		bWord1				0xc
++#define		bDWord				0xf
++
++/* for PutRegsetting & GetRegSetting BitMask */
++#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
++#define		bMaskByte1			0xff00
++#define		bMaskByte2			0xff0000
++#define		bMaskByte3			0xff000000
++#define		bMaskHWord		0xffff0000
++#define		bMaskLWord			0x0000ffff
++#define		bMaskDWord		0xffffffff
++#define		bMaskH3Bytes		0xffffff00
++#define		bMask12Bits			0xfff
++#define		bMaskH4Bits			0xf0000000
++#define		bMaskOFDM_D		0xffc00000
++#define		bMaskCCK			0x3f3f3f3f
++
++
++#define		bEnable			0x1	/* Useless */
++#define		bDisable		0x0
++
++#define		LeftAntenna		0x0	/* Useless */
++#define		RightAntenna	0x1
++
++#define		tCheckTxStatus		500   /* 500ms // Useless */
++#define		tUpdateRxCounter	100   /* 100ms */
++
++#define		rateCCK		0	/* Useless */
++#define		rateOFDM	1
++#define		rateHT		2
++
++/* define Register-End */
++#define		bPMAC_End			0x1ff	/* Useless */
++#define		bFPGAPHY0_End		0x8ff
++#define		bFPGAPHY1_End		0x9ff
++#define		bCCKPHY0_End		0xaff
++#define		bOFDMPHY0_End		0xcff
++#define		bOFDMPHY1_End		0xdff
++
++/* define max debug item in each debug page
++ * #define bMaxItem_FPGA_PHY0        0x9
++ * #define bMaxItem_FPGA_PHY1        0x3
++ * #define bMaxItem_PHY_11B          0x16
++ * #define bMaxItem_OFDM_PHY0        0x29
++ * #define bMaxItem_OFDM_PHY1        0x0 */
++
++#define		bPMACControl		0x0		/* Useless */
++#define		bWMACControl		0x1
++#define		bWNICControl		0x2
++
++#define		PathA			0x0	/* Useless */
++#define		PathB			0x1
++#define		PathC			0x2
++#define		PathD			0x3
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723DPwrSeq.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723DPwrSeq.h
+new file mode 100644
+index 000000000..60cb53b27
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723DPwrSeq.h
+@@ -0,0 +1,206 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef REALTEK_POWER_SEQUENCE_8723D
++#define REALTEK_POWER_SEQUENCE_8723D
++
++/* #include "PwrSeqCmd.h" */
++#include "HalPwrSeqCmd.h"
++
++/*
++	Check document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd
++	There are 6 HW Power States:
++	0: POFF--Power Off
++	1: PDN--Power Down
++	2: CARDEMU--Card Emulation
++	3: ACT--Active Mode
++	4: LPS--Low Power State
++	5: SUS--Suspend
++
++	The transition from different states are defined below
++	TRANS_CARDEMU_TO_ACT
++	TRANS_ACT_TO_CARDEMU
++	TRANS_CARDEMU_TO_SUS
++	TRANS_SUS_TO_CARDEMU
++	TRANS_CARDEMU_TO_PDN
++	TRANS_ACT_TO_LPS
++	TRANS_LPS_TO_ACT
++
++	TRANS_END
++*/
++#define	RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS	27
++#define	RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS	8
++#define	RTL8723D_TRANS_CARDEMU_TO_SUS_STEPS	7
++#define	RTL8723D_TRANS_SUS_TO_CARDEMU_STEPS	5
++#define	RTL8723D_TRANS_CARDEMU_TO_CARDDIS_STEPS	8
++#define	RTL8723D_TRANS_CARDDIS_TO_CARDEMU_STEPS	7
++#define	RTL8723D_TRANS_CARDEMU_TO_PDN_STEPS	4
++#define	RTL8723D_TRANS_PDN_TO_CARDEMU_STEPS	1
++#define	RTL8723D_TRANS_ACT_TO_LPS_STEPS		13
++#define	RTL8723D_TRANS_LPS_TO_ACT_STEPS		11
++#define	RTL8723D_TRANS_END_STEPS	1
++
++
++#define RTL8723D_TRANS_CARDEMU_TO_ACT														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
++	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/	\
++	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
++	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \
++	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)},/* Disable USB suspend */	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},/* wait till 0x04[17] = 1    power ready*/	\
++	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0},/* Enable USB suspend */	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* release WLON reset  0x04[16]=1*/ \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0}, \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* disable HWPDN 0x04[15]=0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},/* disable WL suspend*/ \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* polling until return 0*/ \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},/**/ \
++	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},/* Enable WL control XTAL setting*/ \
++	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable falling edge triggering interrupt*/\
++	{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable GPIO9 interrupt mode*/\
++	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Enable GPIO9 input mode*/\
++	{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/*Enable HSISR GPIO[C:0] interrupt*/\
++	{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable HSISR GPIO9 interrupt*/\
++	{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)},/*For GPIO9 internal pull high setting by test chip*/\
++	{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},/*For GPIO9 internal pull high setting*/\
++	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S1*/\
++	{0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S0*/\
++	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/*enable RF path S1*/\
++	{0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/*enalbe RF path S0*/\
++
++
++#define RTL8723D_TRANS_ACT_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
++	/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x2[0]=0 Reset BB, RF enter Power Down mode*/ \
++	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Enable rising edge triggering interrupt*/ \
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* release WLON reset  0x04[16]=1*/ \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
++	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0},/* Enable BT control XTAL setting*/\
++	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
++	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
++
++
++#define RTL8723D_TRANS_CARDEMU_TO_SUS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
++
++#define RTL8723D_TRANS_SUS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/ \
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
++
++
++#define RTL8723D_TRANS_CARDEMU_TO_CARDDIS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/	\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, /*0x04[10] = 1, enable SW LPS*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend*/	\
++	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
++
++#define RTL8723D_TRANS_CARDDIS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/ \
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\
++	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
++
++
++#define RTL8723D_TRANS_CARDEMU_TO_PDN												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
++
++#define RTL8723D_TRANS_PDN_TO_CARDEMU												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
++
++#define RTL8723D_TRANS_ACT_TO_LPS														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
++	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/*CCK and OFDM are disabled, and clock are gated*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/	\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \
++	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
++	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},/*Respond TxOK to scheduler*/	\
++
++
++#define RTL8723D_TRANS_LPS_TO_ACT															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
++	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
++	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*.	0x08[4] = 0  switch TSF to 40M*/\
++	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
++	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, /*.	0x101[1] = 1*/\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
++
++#define RTL8723D_TRANS_END															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
++	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
++
++
++	extern WLAN_PWR_CFG rtl8723D_power_on_flow[RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723D_radio_off_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723D_card_disable_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_CARDDIS_STEPS + RTL8723D_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723D_card_enable_flow[RTL8723D_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723D_suspend_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723D_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723D_resume_flow[RTL8723D_TRANS_SUS_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723D_hwpdn_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723D_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723D_enter_lps_flow[RTL8723D_TRANS_ACT_TO_LPS_STEPS + RTL8723D_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723D_leave_lps_flow[RTL8723D_TRANS_LPS_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723PwrSeq.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723PwrSeq.h
+new file mode 100644
+index 000000000..22de83375
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8723PwrSeq.h
+@@ -0,0 +1,183 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL8723PWRSEQ_H__
++#define __HAL8723PWRSEQ_H__
++/*
++	Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
++	There are 6 HW Power States:
++	0: POFF--Power Off
++	1: PDN--Power Down
++	2: CARDEMU--Card Emulation
++	3: ACT--Active Mode
++	4: LPS--Low Power State
++	5: SUS--Suspend
++
++	The transision from different states are defined below
++	TRANS_CARDEMU_TO_ACT
++	TRANS_ACT_TO_CARDEMU
++	TRANS_CARDEMU_TO_SUS
++	TRANS_SUS_TO_CARDEMU
++	TRANS_CARDEMU_TO_PDN
++	TRANS_ACT_TO_LPS
++	TRANS_LPS_TO_ACT
++
++	TRANS_END
++*/
++#include "HalPwrSeqCmd.h"
++
++#define	RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS	15
++#define	RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS	15
++#define	RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS	15
++#define	RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS	15
++#define	RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS	15
++#define	RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS	15
++#define	RTL8723A_TRANS_ACT_TO_LPS_STEPS	15
++#define	RTL8723A_TRANS_LPS_TO_ACT_STEPS	15
++#define	RTL8723A_TRANS_END_STEPS	1
++
++
++#define RTL8723A_TRANS_CARDEMU_TO_ACT														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \
++	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/	\
++	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
++	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	\
++	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 1},/*0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */\
++
++#define RTL8723A_TRANS_ACT_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
++	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
++	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
++	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/   \
++
++
++#define RTL8723A_TRANS_CARDEMU_TO_SUS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
++
++#define RTL8723A_TRANS_SUS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
++
++#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
++	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
++
++#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
++
++
++#define RTL8723A_TRANS_CARDEMU_TO_PDN												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
++
++#define RTL8723A_TRANS_PDN_TO_CARDEMU												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
++
++#define RTL8723A_TRANS_ACT_TO_LPS														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
++	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
++	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
++	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
++
++
++#define RTL8723A_TRANS_LPS_TO_ACT															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
++	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
++	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
++	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
++	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
++
++#define RTL8723A_TRANS_END															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
++
++
++	extern WLAN_PWR_CFG rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723A_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723A_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS + RTL8723A_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS];
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8812PhyCfg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8812PhyCfg.h
+new file mode 100644
+index 000000000..69c70d30e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8812PhyCfg.h
+@@ -0,0 +1,134 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8812PHYCFG_H__
++#define __INC_HAL8812PHYCFG_H__
++
++
++/*--------------------------Define Parameters-------------------------------*/
++#define LOOP_LIMIT				5
++#define MAX_STALL_TIME			50		/* us */
++#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
++#define MAX_TXPWR_IDX_NMODE_92S	63
++#define Reset_Cnt_Limit			3
++
++
++#ifdef CONFIG_PCI_HCI
++	#define MAX_AGGR_NUM	0x0B
++#else
++	#define MAX_AGGR_NUM	0x07
++#endif /* CONFIG_PCI_HCI */
++
++
++/*--------------------------Define Parameters-------------------------------*/
++
++/*------------------------------Define structure----------------------------*/
++
++
++/* BB/RF related */
++
++/*------------------------------Define structure----------------------------*/
++
++
++/*------------------------Export global variable----------------------------*/
++/*------------------------Export global variable----------------------------*/
++
++
++/*------------------------Export Marco Definition---------------------------*/
++/*------------------------Export Marco Definition---------------------------*/
++
++
++/*--------------------------Exported Function prototype---------------------*/
++/*
++ * BB and RF register read/write
++ *   */
++u32	PHY_QueryBBReg8812(PADAPTER	Adapter,
++				u32			RegAddr,
++				u32			BitMask);
++void	PHY_SetBBReg8812(PADAPTER		Adapter,
++				u32			RegAddr,
++				u32			BitMask,
++				u32			Data);
++u32	PHY_QueryRFReg8812(PADAPTER	Adapter,
++				enum rf_path	eRFPath,
++				u32			RegAddr,
++				u32			BitMask);
++void	PHY_SetRFReg8812(PADAPTER		Adapter,
++				enum rf_path	eRFPath,
++				u32			RegAddr,
++				u32			BitMask,
++				u32			Data);
++
++/*
++ * Initialization related function
++ *
++ * MAC/BB/RF HAL config */
++int	PHY_MACConfig8812(PADAPTER	Adapter);
++int	PHY_BBConfig8812(PADAPTER	Adapter);
++void	PHY_BB8812_Config_1T(PADAPTER	Adapter);
++int	PHY_RFConfig8812(PADAPTER	Adapter);
++
++/* RF config */
++
++s32
++PHY_SwitchWirelessBand8812(
++		PADAPTER		Adapter,
++		u8			Band
++);
++
++/*
++ * BB TX Power R/W
++ *   */
++void	PHY_SetTxPowerLevel8812(PADAPTER	Adapter, u8	Channel);
++
++bool phy_get_txpwr_target_skip_by_rate_8812a(_adapter *adapter, enum MGN_RATE rate);
++
++u32 phy_get_tx_bb_swing_8812a(
++		PADAPTER	Adapter,
++		BAND_TYPE	Band,
++		enum rf_path	RFPath
++);
++
++void
++PHY_SetTxPowerIndex_8812A(
++		PADAPTER		Adapter,
++		u32				PowerIndex,
++		enum rf_path		RFPath,
++		u8				Rate
++);
++
++/*
++ * channel switch related funciton
++ *   */
++void
++PHY_SetSwChnlBWMode8812(
++		PADAPTER			Adapter,
++		u8					channel,
++		enum channel_width	Bandwidth,
++		u8					Offset40,
++		u8					Offset80
++);
++
++/*
++ * BB/MAC/RF other monitor API
++ *   */
++
++void
++phy_set_rf_path_switch_8812a(
++		struct dm_struct		*phydm,
++		bool		bMain
++);
++
++/*--------------------------Exported Function prototype---------------------*/
++#endif /* __INC_HAL8192CPHYCFG_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8812PhyReg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8812PhyReg.h
+new file mode 100644
+index 000000000..521ebb202
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8812PhyReg.h
+@@ -0,0 +1,735 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8812PHYREG_H__
++#define __INC_HAL8812PHYREG_H__
++/*--------------------------Define Parameters-------------------------------*/
++/*
++ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
++ * 3. RF register 0x00-2E
++ * 4. Bit Mask for BB/RF register
++ * 5. Other defintion for BB/RF R/W
++ *   */
++
++
++/* BB Register Definition */
++
++#define rCCAonSec_Jaguar		0x838
++#define rPwed_TH_Jaguar			0x830
++
++/* BW and sideband setting */
++#define rBWIndication_Jaguar		0x834
++#define rL1PeakTH_Jaguar			0x848
++#define rFPGA0_XA_LSSIReadBack	0x8a0	/*Tranceiver LSSI Readback*/
++#define rRFMOD_Jaguar			0x8ac	/* RF mode */
++#define rADC_Buf_Clk_Jaguar		0x8c4
++#define rRFECTRL_Jaguar			0x900
++#define bRFMOD_Jaguar			0xc3
++#define rCCK_System_Jaguar		0xa00   /* for cck sideband */
++#define bCCK_System_Jaguar		0x10
++
++/* Block & Path enable */
++#define rOFDMCCKEN_Jaguar 		0x808 /* OFDM/CCK block enable */
++#define bOFDMEN_Jaguar			0x20000000
++#define bCCKEN_Jaguar			0x10000000
++#define rRxPath_Jaguar			0x808	/* Rx antenna */
++#define bRxPath_Jaguar			0xff
++#define rTxPath_Jaguar			0x80c	/* Tx antenna */
++#define bTxPath_Jaguar			0x0fffffff
++#define rCCK_RX_Jaguar			0xa04	/* for cck rx path selection */
++#define bCCK_RX_Jaguar			0x0c000000
++#define rVhtlen_Use_Lsig_Jaguar	0x8c3	/* Use LSIG for VHT length */
++
++/* RF read/write-related */
++#define rHSSIRead_Jaguar			0x8b0  /* RF read addr */
++#define bHSSIRead_addr_Jaguar		0xff
++#define bHSSIRead_trigger_Jaguar	0x100
++#define rA_PIRead_Jaguar			0xd04 /* RF readback with PI */
++#define rB_PIRead_Jaguar			0xd44 /* RF readback with PI */
++#define rA_SIRead_Jaguar			0xd08 /* RF readback with SI */
++#define rB_SIRead_Jaguar			0xd48 /* RF readback with SI */
++#define rRead_data_Jaguar			0xfffff
++#define rA_LSSIWrite_Jaguar			0xc90 /* RF write addr */
++#define rB_LSSIWrite_Jaguar			0xe90 /* RF write addr */
++#define bLSSIWrite_data_Jaguar		0x000fffff
++#define bLSSIWrite_addr_Jaguar		0x0ff00000
++
++
++
++/* YN: mask the following register definition temporarily */
++#define rFPGA0_XA_RFInterfaceOE			0x860	/* RF Channel switch */
++#define rFPGA0_XB_RFInterfaceOE			0x864
++
++#define rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
++#define rFPGA0_XCD_RFInterfaceSW		0x874
++
++/* #define rFPGA0_XAB_RFParameter		0x878 */	/* RF Parameter
++ * #define rFPGA0_XCD_RFParameter		0x87c */
++
++/* #define rFPGA0_AnalogParameter1		0x880 */	/* Crystal cap setting RF-R/W protection for parameter4??
++ * #define rFPGA0_AnalogParameter2		0x884
++ * #define rFPGA0_AnalogParameter3		0x888
++ * #define rFPGA0_AdDaClockEn			0x888 */	/* enable ad/da clock1 for dual-phy
++ * #define rFPGA0_AnalogParameter4		0x88c */
++
++
++/* CCK TX scaling */
++#define rCCK_TxFilter1_Jaguar		0xa20
++#define bCCK_TxFilter1_C0_Jaguar	0x00ff0000
++#define bCCK_TxFilter1_C1_Jaguar		0xff000000
++#define rCCK_TxFilter2_Jaguar		0xa24
++#define bCCK_TxFilter2_C2_Jaguar		0x000000ff
++#define bCCK_TxFilter2_C3_Jaguar		0x0000ff00
++#define bCCK_TxFilter2_C4_Jaguar		0x00ff0000
++#define bCCK_TxFilter2_C5_Jaguar		0xff000000
++#define rCCK_TxFilter3_Jaguar		0xa28
++#define bCCK_TxFilter3_C6_Jaguar		0x000000ff
++#define bCCK_TxFilter3_C7_Jaguar		0x0000ff00
++
++
++/* YN: mask the following register definition temporarily
++ * #define rPdp_AntA					0xb00
++ * #define rPdp_AntA_4				0xb04
++ * #define rConfig_Pmpd_AntA			0xb28
++ * #define rConfig_AntA					0xb68
++ * #define rConfig_AntB					0xb6c
++ * #define rPdp_AntB					0xb70
++ * #define rPdp_AntB_4					0xb74
++ * #define rConfig_Pmpd_AntB			0xb98
++ * #define rAPK							0xbd8 */
++
++/* RXIQC */
++#define rA_RxIQC_AB_Jaguar    	0xc10  /* RxIQ imblance matrix coeff. A & B */
++#define rA_RxIQC_CD_Jaguar    	0xc14  /* RxIQ imblance matrix coeff. C & D */
++#define rA_TxScale_Jaguar 		0xc1c  /* Pah_A TX scaling factor */
++#define rB_TxScale_Jaguar 		0xe1c  /* Path_B TX scaling factor */
++#define rB_RxIQC_AB_Jaguar    	0xe10  /* RxIQ imblance matrix coeff. A & B */
++#define rB_RxIQC_CD_Jaguar    	0xe14  /* RxIQ imblance matrix coeff. C & D */
++#define b_RxIQC_AC_Jaguar		0x02ff  /* bit mask for IQC matrix element A & C */
++#define b_RxIQC_BD_Jaguar		0x02ff0000 /* bit mask for IQC matrix element A & C */
++
++
++/* DIG-related */
++#define rA_IGI_Jaguar				0xc50	/* Initial Gain for path-A */
++#define rB_IGI_Jaguar				0xe50	/* Initial Gain for path-B */
++#define rOFDM_FalseAlarm1_Jaguar	0xf48  /* counter for break */
++#define rOFDM_FalseAlarm2_Jaguar	0xf4c  /* counter for spoofing */
++#define rCCK_FalseAlarm_Jaguar        	0xa5c /* counter for cck false alarm */
++#define b_FalseAlarm_Jaguar			0xffff
++#define rCCK_CCA_Jaguar				0xa08	/* cca threshold */
++#define bCCK_CCA_Jaguar				0x00ff0000
++
++/* Tx Power Ttraining-related */
++#define rA_TxPwrTraing_Jaguar		0xc54
++#define rB_TxPwrTraing_Jaguar		0xe54
++
++/* Report-related */
++#define rOFDM_ShortCFOAB_Jaguar	0xf60
++#define rOFDM_LongCFOAB_Jaguar		0xf64
++#define rOFDM_EndCFOAB_Jaguar		0xf70
++#define rOFDM_AGCReport_Jaguar		0xf84
++#define rOFDM_RxSNR_Jaguar			0xf88
++#define rOFDM_RxEVMCSI_Jaguar		0xf8c
++#define rOFDM_SIGReport_Jaguar		0xf90
++
++/* Misc functions */
++#define rEDCCA_Jaguar				0x8a4 /* EDCCA */
++#define bEDCCA_Jaguar				0xffff
++#define rAGC_table_Jaguar			0x82c   /* AGC tabel select */
++#define bAGC_table_Jaguar			0x3
++#define b_sel5g_Jaguar    				0x1000 /* sel5g */
++#define b_LNA_sw_Jaguar				0x8000 /* HW/WS control for LNA */
++#define rFc_area_Jaguar				0x860   /* fc_area */
++#define bFc_area_Jaguar				0x1ffe000
++#define rSingleTone_ContTx_Jaguar	0x914
++
++/* RFE */
++#define rA_RFE_Pinmux_Jaguar	0xcb0  /* Path_A RFE cotrol pinmux */
++#define rB_RFE_Pinmux_Jaguar	0xeb0 /* Path_B RFE control pinmux */
++#define rA_RFE_Inv_Jaguar		0xcb4  /* Path_A RFE cotrol   */
++#define rB_RFE_Inv_Jaguar		0xeb4 /* Path_B RFE control */
++#define rA_RFE_Jaguar			0xcb8  /* Path_A RFE cotrol   */
++#define rB_RFE_Jaguar			0xeb8 /* Path_B RFE control */
++#define	rA_RFE_Inverse_Jaguar	0xCBC	/* Path_A RFE control inverse */
++#define	rB_RFE_Inverse_Jaguar	0xEBC	/* Path_B RFE control inverse */
++#define r_ANTSEL_SW_Jaguar		0x900 /* ANTSEL SW Control */
++#define bMask_RFEInv_Jaguar		0x3ff00000
++#define bMask_AntselPathFollow_Jaguar 0x00030000
++
++/* TX AGC */
++#define rTxAGC_A_CCK11_CCK1_JAguar				0xc20
++#define rTxAGC_A_Ofdm18_Ofdm6_JAguar				0xc24
++#define rTxAGC_A_Ofdm54_Ofdm24_JAguar			0xc28
++#define rTxAGC_A_MCS3_MCS0_JAguar					0xc2c
++#define rTxAGC_A_MCS7_MCS4_JAguar					0xc30
++#define rTxAGC_A_MCS11_MCS8_JAguar				0xc34
++#define rTxAGC_A_MCS15_MCS12_JAguar				0xc38
++#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar	0xc3c
++#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar	0xc40
++#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar	0xc44
++#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar	0xc48
++#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar	0xc4c
++#define rTxAGC_B_CCK11_CCK1_JAguar				0xe20
++#define rTxAGC_B_Ofdm18_Ofdm6_JAguar				0xe24
++#define rTxAGC_B_Ofdm54_Ofdm24_JAguar			0xe28
++#define rTxAGC_B_MCS3_MCS0_JAguar					0xe2c
++#define rTxAGC_B_MCS7_MCS4_JAguar					0xe30
++#define rTxAGC_B_MCS11_MCS8_JAguar				0xe34
++#define rTxAGC_B_MCS15_MCS12_JAguar				0xe38
++#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar		0xe3c
++#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar		0xe40
++#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar		0xe44
++#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar		0xe48
++#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar		0xe4c
++#define bTxAGC_byte0_Jaguar							0xff
++#define bTxAGC_byte1_Jaguar							0xff00
++#define bTxAGC_byte2_Jaguar							0xff0000
++#define bTxAGC_byte3_Jaguar							0xff000000
++
++/* IQK YN: temporaily mask this part
++ * #define rFPGA0_IQK					0xe28
++ * #define rTx_IQK_Tone_A				0xe30
++ * #define rRx_IQK_Tone_A				0xe34
++ * #define rTx_IQK_PI_A					0xe38
++ * #define rRx_IQK_PI_A					0xe3c */
++
++/* #define rTx_IQK						0xe40 */
++/* #define rRx_IQK						0xe44 */
++/* #define rIQK_AGC_Pts					0xe48 */
++/* #define rIQK_AGC_Rsp					0xe4c */
++/* #define rTx_IQK_Tone_B				0xe50 */
++/* #define rRx_IQK_Tone_B				0xe54 */
++/* #define rTx_IQK_PI_B					0xe58 */
++/* #define rRx_IQK_PI_B					0xe5c */
++/* #define rIQK_AGC_Cont				0xe60 */
++
++
++/* AFE-related */
++#define rA_AFEPwr1_Jaguar					0xc60 /* dynamic AFE power control */
++#define rA_AFEPwr2_Jaguar					0xc64 /* dynamic AFE power control */
++#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar	0xc68
++#define rA_Tx_CCKBBON_OFDMRFON_Jaguar	0xc6c
++#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar		0xc70
++#define rA_Tx2Tx_RXCCK_Jaguar				0xc74
++#define rA_Rx_OFDM_WaitRIFS_Jaguar			0xc78
++#define rA_Rx2Rx_BT_Jaguar					0xc7c
++#define rA_sleep_nav_Jaguar					0xc80
++#define rA_pmpd_Jaguar						0xc84
++#define rB_AFEPwr1_Jaguar					0xe60 /* dynamic AFE power control */
++#define rB_AFEPwr2_Jaguar					0xe64 /* dynamic AFE power control */
++#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar	0xe68
++#define rB_Tx_CCKBBON_OFDMRFON_Jaguar	0xe6c
++#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar		0xe70
++#define rB_Tx2Tx_RXCCK_Jaguar				0xe74
++#define rB_Rx_OFDM_WaitRIFS_Jaguar			0xe78
++#define rB_Rx2Rx_BT_Jaguar					0xe7c
++#define rB_sleep_nav_Jaguar					0xe80
++#define rB_pmpd_Jaguar						0xe84
++
++
++/* YN: mask these registers temporaily
++ * #define rTx_Power_Before_IQK_A		0xe94
++ * #define rTx_Power_After_IQK_A			0xe9c */
++
++/* #define rRx_Power_Before_IQK_A		0xea0 */
++/* #define rRx_Power_Before_IQK_A_2		0xea4 */
++/* #define rRx_Power_After_IQK_A			0xea8 */
++/* #define rRx_Power_After_IQK_A_2		0xeac */
++
++/* #define rTx_Power_Before_IQK_B		0xeb4 */
++/* #define rTx_Power_After_IQK_B			0xebc */
++
++/* #define rRx_Power_Before_IQK_B		0xec0 */
++/* #define rRx_Power_Before_IQK_B_2		0xec4 */
++/* #define rRx_Power_After_IQK_B			0xec8 */
++/* #define rRx_Power_After_IQK_B_2		0xecc */
++
++
++/* RSSI Dump */
++#define rA_RSSIDump_Jaguar			0xBF0
++#define rB_RSSIDump_Jaguar			0xBF1
++#define rS1_RXevmDump_Jaguar		0xBF4
++#define rS2_RXevmDump_Jaguar		0xBF5
++#define rA_RXsnrDump_Jaguar		0xBF6
++#define rB_RXsnrDump_Jaguar		0xBF7
++#define rA_CfoShortDump_Jaguar		0xBF8
++#define rB_CfoShortDump_Jaguar		0xBFA
++#define rA_CfoLongDump_Jaguar		0xBEC
++#define rB_CfoLongDump_Jaguar		0xBEE
++
++
++/* RF Register
++ *   */
++#define RF_AC_Jaguar				0x00	/*  */
++#define RF_RF_Top_Jaguar			0x07	/*  */
++#define RF_TXLOK_Jaguar				0x08	/*  */
++#define RF_TXAPK_Jaguar				0x0B
++#define RF_CHNLBW_Jaguar 			0x18	/* RF channel and BW switch */
++#define RF_RCK1_Jaguar				0x1c	/*  */
++#define RF_RCK2_Jaguar				0x1d
++#define RF_RCK3_Jaguar			0x1e
++#define RF_ModeTableAddr			0x30
++#define RF_ModeTableData0			0x31
++#define RF_ModeTableData1			0x32
++#define RF_TxLCTank_Jaguar	0x54
++#define RF_APK_Jaguar				0x63
++#define RF_LCK						0xB4
++#define RF_WeLut_Jaguar				0xEF
++
++#define bRF_CHNLBW_MOD_AG_Jaguar	0x70300
++#define bRF_CHNLBW_BW				0xc00
++
++
++/*
++ * RL6052 Register definition
++ *   */
++#define RF_AC						0x00	/*  */
++#define RF_IPA_A					0x0C	/*  */
++#define RF_TXBIAS_A					0x0D
++#define RF_BS_PA_APSET_G9_G11		0x0E
++#define RF_MODE1					0x10	/*  */
++#define RF_MODE2					0x11	/*  */
++#define RF_CHNLBW					0x18	/* RF channel and BW switch */
++#define RF_RCK_OS					0x30	/* RF TX PA control */
++#define RF_TXPA_G1					0x31	/* RF TX PA control */
++#define RF_TXPA_G2					0x32	/* RF TX PA control */
++#define RF_TXPA_G3					0x33	/* RF TX PA control */
++#define RF_0x52						0x52
++#define RF_WE_LUT					0xEF
++
++#define RF_TX_GAIN_OFFSET_8812A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
++#define RF_TX_GAIN_OFFSET_8821A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
++
++/*
++ * Bit Mask
++ *
++ * 1. Page1(0x100) */
++#define bBBResetB					0x100	/* Useless now? */
++#define bGlobalResetB				0x200
++#define bOFDMTxStart				0x4
++#define bCCKTxStart					0x8
++#define bCRC32Debug					0x100
++#define bPMACLoopback				0x10
++#define bTxLSIG						0xffffff
++#define bOFDMTxRate					0xf
++#define bOFDMTxReserved			0x10
++#define bOFDMTxLength				0x1ffe0
++#define bOFDMTxParity				0x20000
++#define bTxHTSIG1					0xffffff
++#define bTxHTMCSRate				0x7f
++#define bTxHTBW						0x80
++#define bTxHTLength					0xffff00
++#define bTxHTSIG2					0xffffff
++#define bTxHTSmoothing				0x1
++#define bTxHTSounding				0x2
++#define bTxHTReserved				0x4
++#define bTxHTAggreation				0x8
++#define bTxHTSTBC					0x30
++#define bTxHTAdvanceCoding			0x40
++#define bTxHTShortGI					0x80
++#define bTxHTNumberHT_LTF			0x300
++#define bTxHTCRC8					0x3fc00
++#define bCounterReset				0x10000
++#define bNumOfOFDMTx				0xffff
++#define bNumOfCCKTx					0xffff0000
++#define bTxIdleInterval				0xffff
++#define bOFDMService				0xffff0000
++#define bTxMACHeader				0xffffffff
++#define bTxDataInit					0xff
++#define bTxHTMode					0x100
++#define bTxDataType					0x30000
++#define bTxRandomSeed				0xffffffff
++#define bCCKTxPreamble				0x1
++#define bCCKTxSFD					0xffff0000
++#define bCCKTxSIG					0xff
++#define bCCKTxService				0xff00
++#define bCCKLengthExt				0x8000
++#define bCCKTxLength				0xffff0000
++#define bCCKTxCRC16					0xffff
++#define bCCKTxStatus					0x1
++#define bOFDMTxStatus				0x2
++
++
++/*
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 1. Page1(0x100)
++ *   */
++#define rPMAC_Reset					0x100
++#define rPMAC_TxStart				0x104
++#define rPMAC_TxLegacySIG			0x108
++#define rPMAC_TxHTSIG1				0x10c
++#define rPMAC_TxHTSIG2				0x110
++#define rPMAC_PHYDebug				0x114
++#define rPMAC_TxPacketNum			0x118
++#define rPMAC_TxIdle					0x11c
++#define rPMAC_TxMACHeader0			0x120
++#define rPMAC_TxMACHeader1			0x124
++#define rPMAC_TxMACHeader2			0x128
++#define rPMAC_TxMACHeader3			0x12c
++#define rPMAC_TxMACHeader4			0x130
++#define rPMAC_TxMACHeader5			0x134
++#define rPMAC_TxDataType			0x138
++#define rPMAC_TxRandomSeed		0x13c
++#define rPMAC_CCKPLCPPreamble		0x140
++#define rPMAC_CCKPLCPHeader		0x144
++#define rPMAC_CCKCRC16				0x148
++#define rPMAC_OFDMRxCRC32OK		0x170
++#define rPMAC_OFDMRxCRC32Er		0x174
++#define rPMAC_OFDMRxParityEr		0x178
++#define rPMAC_OFDMRxCRC8Er			0x17c
++#define rPMAC_CCKCRxRC16Er			0x180
++#define rPMAC_CCKCRxRC32Er			0x184
++#define rPMAC_CCKCRxRC32OK			0x188
++#define rPMAC_TxStatus				0x18c
++
++/*
++ * 3. Page8(0x800)
++ *   */
++#define rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
++
++#define rFPGA0_TxInfo				0x804	/* Status report?? */
++#define rFPGA0_PSDFunction			0x808
++#define rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
++
++#define rFPGA0_XA_HSSIParameter1	0x820	/* RF 3 wire register */
++#define rFPGA0_XA_HSSIParameter2	0x824
++#define rFPGA0_XB_HSSIParameter1	0x828
++#define rFPGA0_XB_HSSIParameter2	0x82c
++
++#define rFPGA0_XAB_SwitchControl	0x858	/* RF Channel switch */
++#define rFPGA0_XCD_SwitchControl	0x85c
++
++#define rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
++#define rFPGA0_XCD_RFParameter		0x87c
++
++#define rFPGA0_AnalogParameter1	0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
++#define rFPGA0_AnalogParameter2	0x884
++#define rFPGA0_AnalogParameter3	0x888
++#define rFPGA0_AdDaClockEn			0x888	/* enable ad/da clock1 for dual-phy */
++#define rFPGA0_AnalogParameter4	0x88c
++#define rFPGA0_XB_LSSIReadBack		0x8a4
++#define rFPGA0_XCD_RFPara	0x8b4
++
++/*
++ * 4. Page9(0x900)
++ *   */
++#define rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
++
++#define rFPGA1_TxBlock				0x904	/* Useless now */
++#define rFPGA1_DebugSelect			0x908	/* Useless now */
++#define rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
++
++/*
++ * PageA(0xA00)
++ *   */
++#define rCCK0_System				0xa00
++#define rCCK0_AFESetting				0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
++#define	rCCK0_DSPParameter2			0xa1c	/* SQ threshold */
++#define rCCK0_TxFilter1				0xa20
++#define rCCK0_TxFilter2				0xa24
++#define rCCK0_DebugPort				0xa28	/* debug port and Tx filter3 */
++#define	rCCK0_FalseAlarmReport			0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
++
++/*
++ * PageB(0xB00)
++ *   */
++#define rPdp_AntA				0xb00
++#define rPdp_AntA_4				0xb04
++#define rConfig_Pmpd_AntA			0xb28
++#define rConfig_AntA					0xb68
++#define rConfig_AntB					0xb6c
++#define rPdp_AntB					0xb70
++#define rPdp_AntB_4					0xb74
++#define rConfig_Pmpd_AntB			0xb98
++#define rAPK							0xbd8
++
++/*
++ * 6. PageC(0xC00)
++ *   */
++#define rOFDM0_LSTF					0xc00
++
++#define rOFDM0_TRxPathEnable		0xc04
++#define rOFDM0_TRMuxPar			0xc08
++#define rOFDM0_TRSWIsolation		0xc0c
++
++#define rOFDM0_XARxAFE				0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
++#define rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
++#define rOFDM0_XBRxAFE		0xc18
++#define rOFDM0_XBRxIQImbalance	0xc1c
++#define rOFDM0_XCRxAFE		0xc20
++#define rOFDM0_XCRxIQImbalance	0xc24
++#define rOFDM0_XDRxAFE		0xc28
++#define rOFDM0_XDRxIQImbalance	0xc2c
++
++#define rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
++#define rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
++#define rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
++#define rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
++
++#define rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
++#define rOFDM0_CFOandDAGC			0xc44  /* CFO & DAGC */
++#define rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
++#define rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
++
++#define rOFDM0_XAAGCCore1			0xc50	/* DIG */
++#define rOFDM0_XAAGCCore2			0xc54
++#define rOFDM0_XBAGCCore1			0xc58
++#define rOFDM0_XBAGCCore2			0xc5c
++#define rOFDM0_XCAGCCore1			0xc60
++#define rOFDM0_XCAGCCore2			0xc64
++#define rOFDM0_XDAGCCore1			0xc68
++#define rOFDM0_XDAGCCore2			0xc6c
++
++#define rOFDM0_AGCParameter1		0xc70
++#define rOFDM0_AGCParameter2		0xc74
++#define rOFDM0_AGCRSSITable		0xc78
++#define rOFDM0_HTSTFAGC			0xc7c
++
++#define rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
++#define rOFDM0_XATxAFE				0xc84
++#define rOFDM0_XBTxIQImbalance		0xc88
++#define rOFDM0_XBTxAFE				0xc8c
++#define rOFDM0_XCTxIQImbalance		0xc90
++#define rOFDM0_XCTxAFE		0xc94
++#define rOFDM0_XDTxIQImbalance		0xc98
++#define rOFDM0_XDTxAFE				0xc9c
++
++#define rOFDM0_RxIQExtAnta			0xca0
++#define rOFDM0_TxCoeff1				0xca4
++#define rOFDM0_TxCoeff2				0xca8
++#define rOFDM0_TxCoeff3				0xcac
++#define rOFDM0_TxCoeff4				0xcb0
++#define rOFDM0_TxCoeff5				0xcb4
++#define rOFDM0_TxCoeff6				0xcb8
++#define rOFDM0_RxHPParameter		0xce0
++#define rOFDM0_TxPseudoNoiseWgt	0xce4
++#define rOFDM0_FrameSync			0xcf0
++#define rOFDM0_DFSReport			0xcf4
++
++/*
++ * 7. PageD(0xD00)
++ *   */
++#define rOFDM1_LSTF					0xd00
++#define rOFDM1_TRxPathEnable		0xd04
++
++/*
++ * 8. PageE(0xE00)
++ *   */
++#define rTxAGC_A_Rate18_06			0xe00
++#define rTxAGC_A_Rate54_24			0xe04
++#define rTxAGC_A_CCK1_Mcs32		0xe08
++#define rTxAGC_A_Mcs03_Mcs00		0xe10
++#define rTxAGC_A_Mcs07_Mcs04		0xe14
++#define rTxAGC_A_Mcs11_Mcs08		0xe18
++#define rTxAGC_A_Mcs15_Mcs12		0xe1c
++
++#define rTxAGC_B_Rate18_06			0x830
++#define rTxAGC_B_Rate54_24			0x834
++#define rTxAGC_B_CCK1_55_Mcs32	0x838
++#define rTxAGC_B_Mcs03_Mcs00		0x83c
++#define rTxAGC_B_Mcs07_Mcs04		0x848
++#define rTxAGC_B_Mcs11_Mcs08		0x84c
++#define rTxAGC_B_Mcs15_Mcs12		0x868
++#define rTxAGC_B_CCK11_A_CCK2_11	0x86c
++
++#define rFPGA0_IQK					0xe28
++#define rTx_IQK_Tone_A				0xe30
++#define rRx_IQK_Tone_A				0xe34
++#define rTx_IQK_PI_A				0xe38
++#define rRx_IQK_PI_A				0xe3c
++
++#define rTx_IQK						0xe40
++#define rRx_IQK						0xe44
++#define rIQK_AGC_Pts					0xe48
++#define rIQK_AGC_Rsp				0xe4c
++#define rTx_IQK_Tone_B				0xe50
++#define rRx_IQK_Tone_B				0xe54
++#define rTx_IQK_PI_B					0xe58
++#define rRx_IQK_PI_B					0xe5c
++#define rIQK_AGC_Cont				0xe60
++
++#define rBlue_Tooth					0xe6c
++#define rRx_Wait_CCA				0xe70
++#define rTx_CCK_RFON				0xe74
++#define rTx_CCK_BBON				0xe78
++#define rTx_OFDM_RFON				0xe7c
++#define rTx_OFDM_BBON				0xe80
++#define rTx_To_Rx					0xe84
++#define rTx_To_Tx					0xe88
++#define rRx_CCK						0xe8c
++
++#define rTx_Power_Before_IQK_A		0xe94
++#define rTx_Power_After_IQK_A		0xe9c
++
++#define rRx_Power_Before_IQK_A		0xea0
++#define rRx_Power_Before_IQK_A_2	0xea4
++#define rRx_Power_After_IQK_A		0xea8
++#define rRx_Power_After_IQK_A_2		0xeac
++
++#define rTx_Power_Before_IQK_B		0xeb4
++#define rTx_Power_After_IQK_B		0xebc
++
++#define rRx_Power_Before_IQK_B		0xec0
++#define rRx_Power_Before_IQK_B_2	0xec4
++#define rRx_Power_After_IQK_B		0xec8
++#define rRx_Power_After_IQK_B_2		0xecc
++
++#define rRx_OFDM					0xed0
++#define rRx_Wait_RIFS				0xed4
++#define rRx_TO_Rx					0xed8
++#define rStandby						0xedc
++#define rSleep						0xee0
++#define rPMPD_ANAEN				0xeec
++
++
++/* 2. Page8(0x800) */
++#define bRFMOD						0x1	/* Reg 0x800 rFPGA0_RFMOD */
++#define bJapanMode					0x2
++#define bCCKTxSC					0x30
++#define bCCKEn						0x1000000
++#define bOFDMEn						0x2000000
++#define bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
++#define bXCTxAGC			0xf000
++#define bXDTxAGC			0xf0000
++
++/* 4. PageA(0xA00) */
++#define bCCKBBMode                			0x3	/* Useless */
++#define bCCKTxPowerSaving		0x80
++#define bCCKRxPowerSaving		0x40
++
++#define bCCKSideBand              		0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
++
++#define bCCKScramble              		0x8	/* Useless */
++#define bCCKAntDiversity			0x8000
++#define bCCKCarrierRecovery		0x4000
++#define bCCKTxRate			0x3000
++#define bCCKDCCancel			0x0800
++#define bCCKISICancel			0x0400
++#define bCCKMatchFilter		0x0200
++#define bCCKEqualizer			0x0100
++#define bCCKPreambleDetect		0x800000
++#define bCCKFastFalseCCA		0x400000
++#define bCCKChEstStart		0x300000
++#define bCCKCCACount		0x080000
++#define bCCKcs_lim			0x070000
++#define bCCKBistMode			0x80000000
++#define bCCKCCAMask			0x40000000
++#define bCCKTxDACPhase		0x4
++#define bCCKRxADCPhase         	   	0x20000000   /* r_rx_clk */
++#define bCCKr_cp_mode0		0x0100
++#define bCCKTxDCOffset		0xf0
++#define bCCKRxDCOffset		0xf
++#define bCCKCCAMode			0xc000
++#define bCCKFalseCS_lim		0x3f00
++#define bCCKCS_ratio			0xc00000
++#define bCCKCorgBit_sel		0x300000
++#define bCCKPD_lim			0x0f0000
++#define bCCKNewCCA		0x80000000
++#define bCCKRxHPofIG		0x8000
++#define bCCKRxIG			0x7f00
++#define bCCKLNAPolarity		0x800000
++#define bCCKRx1stGain		0x7f0000
++#define bCCKRFExtend              		0x20000000 /* CCK Rx Iinital gain polarity */
++#define bCCKRxAGCSatLevel		0x1f000000
++#define bCCKRxAGCSatCount		0xe0
++#define bCCKRxRFSettle            		0x1f       /* AGCsamp_dly */
++#define bCCKFixedRxAGC		0x8000
++/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
++#define bCCKAntennaPolarity		0x2000
++#define bCCKTxFilterType		0x0c00
++#define bCCKRxAGCReportType		0x0300
++#define bCCKRxDAGCEn		0x80000000
++#define bCCKRxDAGCPeriod		0x20000000
++#define bCCKRxDAGCSatLevel		0x1f000000
++#define bCCKTimingRecovery		0x800000
++#define bCCKTxC0			0x3f0000
++#define bCCKTxC1			0x3f000000
++#define bCCKTxC2			0x3f
++#define bCCKTxC3			0x3f00
++#define bCCKTxC4			0x3f0000
++#define bCCKTxC5			0x3f000000
++#define bCCKTxC6			0x3f
++#define bCCKTxC7			0x3f00
++#define bCCKDebugPort		0xff0000
++#define bCCKDACDebug		0x0f000000
++#define bCCKFalseAlarmEnable		0x8000
++#define bCCKFalseAlarmRead		0x4000
++#define bCCKTRSSI			0x7f
++#define bCCKRxAGCReport		0xfe
++#define bCCKRxReport_AntSel		0x80000000
++#define bCCKRxReport_MFOff		0x40000000
++#define bCCKRxRxReport_SQLoss	0x20000000
++#define bCCKRxReport_Pktloss		0x10000000
++#define bCCKRxReport_Lockedbit	0x08000000
++#define bCCKRxReport_RateError	0x04000000
++#define bCCKRxReport_RxRate		0x03000000
++#define bCCKRxFACounterLower	0xff
++#define bCCKRxFACounterUpper	0xff000000
++#define bCCKRxHPAGCStart		0xe000
++#define bCCKRxHPAGCFinal		0x1c00
++#define bCCKRxFalseAlarmEnable	0x8000
++#define bCCKFACounterFreeze		0x4000
++#define bCCKTxPathSel		0x10000000
++#define bCCKDefaultRxPath		0xc000000
++#define bCCKOptionRxPath		0x3000000
++
++/* 6. PageE(0xE00) */
++#define bSTBCEn                  			0x4	/* Useless */
++#define bAntennaMapping		0x10
++#define bNss				0x20
++#define bCFOAntSumD		0x200
++#define bPHYCounterReset		0x8000000
++#define bCFOReportGet			0x4000000
++#define bOFDMContinueTx		0x10000000
++#define bOFDMSingleCarrier		0x20000000
++#define bOFDMSingleTone		0x40000000
++
++
++/*
++ * Other Definition
++ *   */
++
++#define bEnable                   0x1	/* Useless */
++#define bDisable                  0x0
++
++/* byte endable for srwrite */
++#define bByte0                    		0x1	/* Useless */
++#define bByte1		0x2
++#define bByte2		0x4
++#define bByte3		0x8
++#define bWord0		0x3
++#define bWord1		0xc
++#define bDWord		0xf
++
++/* for PutRegsetting & GetRegSetting BitMask */
++#define bMaskByte0                		0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
++#define bMaskByte1		0xff00
++#define bMaskByte2		0xff0000
++#define bMaskByte3		0xff000000
++#define bMaskHWord	0xffff0000
++#define bMaskLWord		0x0000ffff
++#define bMaskDWord	0xffffffff
++#define bMaskH3Bytes				0xffffff00
++#define bMask12Bits				0xfff
++#define bMaskH4Bits				0xf0000000
++#define bMaskOFDM_D			0xffc00000
++#define bMaskCCK				0x3f3f3f3f
++
++
++/*--------------------------Define Parameters-------------------------------*/
++
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8812PwrSeq.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8812PwrSeq.h
+new file mode 100644
+index 000000000..498faf811
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8812PwrSeq.h
+@@ -0,0 +1,208 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++
++#ifndef __HAL8812PWRSEQ_H__
++#define __HAL8812PWRSEQ_H__
++
++#include "HalPwrSeqCmd.h"
++
++/*
++	Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf
++	There are 6 HW Power States:
++	0: POFF--Power Off
++	1: PDN--Power Down
++	2: CARDEMU--Card Emulation
++	3: ACT--Active Mode
++	4: LPS--Low Power State
++	5: SUS--Suspend
++
++	The transision from different states are defined below
++	TRANS_CARDEMU_TO_ACT
++	TRANS_ACT_TO_CARDEMU
++	TRANS_CARDEMU_TO_SUS
++	TRANS_SUS_TO_CARDEMU
++	TRANS_CARDEMU_TO_PDN
++	TRANS_ACT_TO_LPS
++	TRANS_LPS_TO_ACT
++
++	TRANS_END
++*/
++#define	RTL8812_TRANS_CARDEMU_TO_ACT_STEPS	15
++#define	RTL8812_TRANS_ACT_TO_CARDEMU_STEPS	15
++#define	RTL8812_TRANS_CARDEMU_TO_SUS_STEPS	15
++#define	RTL8812_TRANS_SUS_TO_CARDEMU_STEPS	15
++#define	RTL8812_TRANS_CARDEMU_TO_PDN_STEPS	15
++#define	RTL8812_TRANS_PDN_TO_CARDEMU_STEPS	15
++#define	RTL8812_TRANS_ACT_TO_LPS_STEPS	15
++#define	RTL8812_TRANS_LPS_TO_ACT_STEPS	15
++#define	RTL8812_TRANS_END_STEPS	1
++
++
++#define RTL8812_TRANS_CARDEMU_TO_ACT														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
++	/*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, disable HWPDN 0x04[15]=0*/ \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/   \
++	{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x24[1] Choose the type of buffer after xosc: nand*/   \
++	{0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /* 0x28[33] Choose the type of buffer after xosc: nand*/
++
++#define RTL8812_TRANS_ACT_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4	turn off 3-wire */	\
++	{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4	turn off 3-wire */	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0	 RESET BB, CLOSE RF */	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
++	/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},//0x1F[7:0] = 0 turn off RF*/	\
++	/*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},//0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */	\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x2A}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/	\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */	\
++	/*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0}, //  0x02[1:0] = 0	reset BB */	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
++
++#define RTL8812_TRANS_CARDEMU_TO_SUS													\
++	/* format */								\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\
++	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\
++	{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */	\
++	{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */	\
++	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */	\
++	{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */	\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */	\
++	{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */	\
++	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */	\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */	\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'11 enable WL suspend for PCIe*/
++
++#define RTL8812_TRANS_SUS_TO_CARDEMU													\
++	/* format */								\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/   \
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */	\
++	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */	\
++	{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */	\
++	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */	\
++	{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
++
++#define RTL8812_TRANS_CARDEMU_TO_CARDDIS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	/**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/	\
++	/**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/	\
++	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 8051*/	\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x05}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/	\
++	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\
++	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\
++	{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */	\
++	{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */	\
++	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */	\
++	{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */	\
++	{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */	\
++	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */	\
++	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/*0x12[0] = 0 force PFM mode */	\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */	\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */	\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
++	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x01f[1]=0 , disable RFC_0  control  REG_RF_CTRL_8812 */	\
++	{0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x076[1]=0 , disable RFC_1  control REG_OPT_CTRL_8812 +2 */	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'01 enable WL suspend*/
++
++#define RTL8812_TRANS_CARDDIS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/                       \
++	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x12[0] = 1 force PWM mode */	\
++	{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */	\
++	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */	\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */	\
++	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */	\
++	{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/	\
++	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x03[2] = 1, enable 8051*/	\
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/  \
++	{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /* 0x24[1] Choose the type of buffer after xosc: schmitt trigger*/ \
++	{0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /* 0x28[33] Choose the type of buffer after xosc: schmitt trigger*/
++
++
++#define RTL8812_TRANS_CARDEMU_TO_PDN												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
++
++#define RTL8812_TRANS_PDN_TO_CARDEMU												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
++
++#define RTL8812_TRANS_ACT_TO_LPS														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/		\
++	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4	turn off 3-wire */	\
++	{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4	turn off 3-wire */	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/			\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/		\
++	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
++
++
++#define RTL8812_TRANS_LPS_TO_ACT															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/	\
++	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/	\
++	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/	\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/	\
++	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/			\
++	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/	\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/					\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/	\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
++
++#define RTL8812_TRANS_END																\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/		\
++	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
++
++
++extern WLAN_PWR_CFG rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS + RTL8812_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS];
++
++#endif /* __HAL8812PWRSEQ_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8814PhyCfg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8814PhyCfg.h
+new file mode 100644
+index 000000000..0fdc34077
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8814PhyCfg.h
+@@ -0,0 +1,236 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8814PHYCFG_H__
++#define __INC_HAL8814PHYCFG_H__
++
++
++/*--------------------------Define Parameters-------------------------------*/
++#define LOOP_LIMIT				5
++#define MAX_STALL_TIME			50		/* us */
++#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
++#define MAX_TXPWR_IDX_NMODE_92S	63
++#define Reset_Cnt_Limit			3
++
++
++#ifdef CONFIG_PCI_HCI
++	#define MAX_AGGR_NUM	0x0B
++#else
++	#define MAX_AGGR_NUM	0x07
++#endif /* CONFIG_PCI_HCI */
++
++
++/*--------------------------Define Parameters-------------------------------*/
++
++/*------------------------------Define structure----------------------------*/
++
++
++/* BB/RF related */
++
++#define	SIC_ENABLE				0
++
++/*------------------------------Define structure----------------------------*/
++
++
++/*------------------------Export global variable----------------------------*/
++/*------------------------Export global variable----------------------------*/
++
++
++/*------------------------Export Marco Definition---------------------------*/
++/*------------------------Export Marco Definition---------------------------*/
++
++
++/*--------------------------Exported Function prototype---------------------*/
++/* 1. BB register R/W API */
++
++extern	u32
++PHY_QueryBBReg8814A(PADAPTER	Adapter,
++			u32		RegAddr,
++			u32		BitMask);
++
++
++void
++PHY_SetBBReg8814A(PADAPTER	Adapter,
++			u32		RegAddr,
++			u32		BitMask,
++			u32		Data);
++
++
++extern	u32
++PHY_QueryRFReg8814A(PADAPTER			Adapter,
++			enum rf_path	eRFPath,
++			u32			RegAddr,
++			u32			BitMask);
++
++
++void
++PHY_SetRFReg8814A(PADAPTER			Adapter,
++			enum rf_path		eRFPath,
++			u32				RegAddr,
++			u32				BitMask,
++			u32				Data);
++
++/* 1 3. Initial BB/RF config by reading MAC/BB/RF txt. */
++s32
++phy_BB8814A_Config_ParaFile(
++		PADAPTER	Adapter
++);
++
++void
++PHY_ConfigBB_8814A(
++		PADAPTER	Adapter
++);
++
++
++void
++phy_ADC_CLK_8814A(
++		PADAPTER	Adapter
++);
++
++s32
++PHY_RFConfig8814A(
++		PADAPTER	Adapter
++);
++
++/*
++ * RF Power setting
++ *
++ * BOOLEAN	PHY_SetRFPowerState8814A(PADAPTER Adapter, rt_rf_power_state	eRFPowerState); */
++
++/* 1 5. Tx  Power setting API */
++
++void
++PHY_SetTxPowerLevel8814(
++		PADAPTER		Adapter,
++		u8			Channel
++);
++
++u8
++phy_get_tx_power_index_8814a(
++		PADAPTER		Adapter,
++		enum rf_path		RFPath,
++		u8				Rate,
++		enum channel_width BandWidth,
++		u8				Channel
++);
++
++void
++PHY_SetTxPowerIndex_8814A(
++		PADAPTER		Adapter,
++		u32				PowerIndex,
++		enum rf_path		RFPath,
++		u8				Rate
++);
++
++u32
++PHY_GetTxBBSwing_8814A(
++		PADAPTER	Adapter,
++		BAND_TYPE	Band,
++		enum rf_path	RFPath
++);
++
++
++
++/* 1 6. Channel setting API */
++#if 0
++void
++PHY_SwChnlTimerCallback8814A(
++		struct timer_list		*p_timer
++);
++#endif
++void
++PHY_SwChnlWorkItemCallback8814A(
++		void *pContext
++);
++
++
++void
++HAL_HandleSwChnl8814A(
++		PADAPTER	pAdapter,
++		u8		channel
++);
++
++void
++PHY_SwChnlSynchronously8814A(PADAPTER		pAdapter,
++				u8			channel);
++
++void
++PHY_HandleSwChnlAndSetBW8814A(
++		PADAPTER			Adapter,
++		BOOLEAN				bSwitchChannel,
++		BOOLEAN				bSetBandWidth,
++		u8					ChannelNum,
++		enum channel_width	ChnlWidth,
++		u8					ChnlOffsetOf40MHz,
++		u8					ChnlOffsetOf80MHz,
++		u8					CenterFrequencyIndex1
++);
++
++
++BOOLEAN
++PHY_QueryRFPathSwitch_8814A(PADAPTER	pAdapter);
++
++
++
++#if (USE_WORKITEM)
++void
++RtCheckForHangWorkItemCallback8814A(
++		void *pContext
++);
++#endif
++
++BOOLEAN
++SetAntennaConfig8814A(
++		PADAPTER	Adapter,
++		u8		DefaultAnt
++);
++
++void
++PHY_SetRFEReg8814A(
++		PADAPTER		Adapter,
++		BOOLEAN		bInit,
++		u8		Band
++);
++
++
++s32
++PHY_SwitchWirelessBand8814A(
++		PADAPTER		 Adapter,
++		u8		Band
++);
++
++void
++PHY_SetIO_8814A(
++	PADAPTER		pAdapter
++);
++
++void
++PHY_SetSwChnlBWMode8814(
++		PADAPTER			Adapter,
++		u8					channel,
++		enum channel_width	Bandwidth,
++		u8					Offset40,
++		u8					Offset80
++);
++
++s32 PHY_MACConfig8814(PADAPTER Adapter);
++int PHY_BBConfig8814(PADAPTER	Adapter);
++void PHY_Set_SecCCATH_by_RXANT_8814A(PADAPTER	pAdapter, u32 ulAntennaRx);
++
++
++
++/*--------------------------Exported Function prototype---------------------*/
++
++/*--------------------------Exported Function prototype---------------------*/
++#endif /* __INC_HAL8192CPHYCFG_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8814PhyReg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8814PhyReg.h
+new file mode 100644
+index 000000000..21851a898
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8814PhyReg.h
+@@ -0,0 +1,863 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8814PHYREG_H__
++#define __INC_HAL8814PHYREG_H__
++/*--------------------------Define Parameters-------------------------------*/
++/*
++ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
++ * 3. RF register 0x00-2E
++ * 4. Bit Mask for BB/RF register
++ * 5. Other defintion for BB/RF R/W
++ *   */
++
++
++/* BB Register Definition */
++
++#define rCCAonSec_Jaguar		0x838
++#define rPwed_TH_Jaguar			0x830
++#define rL1_Weight_Jaguar		0x840
++#define	r_L1_SBD_start_time		0x844
++
++/* BW and sideband setting */
++#define rBWIndication_Jaguar		0x834
++#define rL1PeakTH_Jaguar		0x848
++#define rRFMOD_Jaguar			0x8ac	/* RF mode */
++#define rADC_Buf_Clk_Jaguar		0x8c4
++#define	rADC_Buf_40_Clk_Jaguar2		0x8c8
++#define rRFECTRL_Jaguar			0x900
++#define bRFMOD_Jaguar			0xc3
++#define rCCK_System_Jaguar		0xa00   /* for cck sideband */
++#define bCCK_System_Jaguar		0x10
++
++/* Block & Path enable */
++#define rOFDMCCKEN_Jaguar 		0x808 /* OFDM/CCK block enable */
++#define bOFDMEN_Jaguar			0x20000000
++#define bCCKEN_Jaguar			0x10000000
++#define rRxPath_Jaguar			0x808	/* Rx antenna */
++#define bRxPath_Jaguar			0xff
++#define rTxPath_Jaguar			0x80c	/* Tx antenna */
++#define bTxPath_Jaguar			0x0fffffff
++#define rCCK_RX_Jaguar			0xa04	/* for cck rx path selection */
++#define bCCK_RX_Jaguar			0x0c000000
++#define rVhtlen_Use_Lsig_Jaguar	0x8c3	/* Use LSIG for VHT length */
++
++#define	rRxPath_Jaguar2				0xa04	/* Rx antenna */
++#define	rTxAnt_1Nsts_Jaguar2		0x93c	/* Tx antenna for 1Nsts */
++#define	rTxAnt_23Nsts_Jaguar2		0x940	/* Tx antenna for 2Nsts and 3Nsts */
++
++
++/* RF read/write-related */
++#define rHSSIRead_Jaguar			0x8b0  /* RF read addr */
++#define bHSSIRead_addr_Jaguar		0xff
++#define bHSSIRead_trigger_Jaguar	0x100
++#define rA_PIRead_Jaguar			0xd04 /* RF readback with PI */
++#define rB_PIRead_Jaguar			0xd44 /* RF readback with PI */
++#define rA_SIRead_Jaguar			0xd08 /* RF readback with SI */
++#define rB_SIRead_Jaguar			0xd48 /* RF readback with SI */
++#define rRead_data_Jaguar			0xfffff
++#define rA_LSSIWrite_Jaguar			0xc90 /* RF write addr */
++#define rB_LSSIWrite_Jaguar			0xe90 /* RF write addr */
++#define bLSSIWrite_data_Jaguar		0x000fffff
++#define bLSSIWrite_addr_Jaguar		0x0ff00000
++
++#define	rC_PIRead_Jaguar2			0xd84 /* RF readback with PI */
++#define	rD_PIRead_Jaguar2			0xdC4 /* RF readback with PI */
++#define	rC_SIRead_Jaguar2			0xd88 /* RF readback with SI */
++#define	rD_SIRead_Jaguar2			0xdC8 /* RF readback with SI */
++#define	rC_LSSIWrite_Jaguar2		0x1890 /* RF write addr */
++#define	rD_LSSIWrite_Jaguar2		0x1A90 /* RF write addr */
++
++
++/* YN: mask the following register definition temporarily */
++#define rFPGA0_XA_RFInterfaceOE			0x860	/* RF Channel switch */
++#define rFPGA0_XB_RFInterfaceOE			0x864
++
++#define rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
++#define rFPGA0_XCD_RFInterfaceSW		0x874
++
++/* #define rFPGA0_XAB_RFParameter		0x878 */	/* RF Parameter
++ * #define rFPGA0_XCD_RFParameter		0x87c */
++
++/* #define rFPGA0_AnalogParameter1		0x880 */	/* Crystal cap setting RF-R/W protection for parameter4??
++ * #define rFPGA0_AnalogParameter2		0x884
++ * #define rFPGA0_AnalogParameter3		0x888
++ * #define rFPGA0_AdDaClockEn			0x888 */	/* enable ad/da clock1 for dual-phy
++ * #define rFPGA0_AnalogParameter4		0x88c */
++
++
++/* CCK TX scaling */
++#define rCCK_TxFilter1_Jaguar		0xa20
++#define bCCK_TxFilter1_C0_Jaguar	0x00ff0000
++#define bCCK_TxFilter1_C1_Jaguar		0xff000000
++#define rCCK_TxFilter2_Jaguar		0xa24
++#define bCCK_TxFilter2_C2_Jaguar		0x000000ff
++#define bCCK_TxFilter2_C3_Jaguar		0x0000ff00
++#define bCCK_TxFilter2_C4_Jaguar		0x00ff0000
++#define bCCK_TxFilter2_C5_Jaguar		0xff000000
++#define rCCK_TxFilter3_Jaguar		0xa28
++#define bCCK_TxFilter3_C6_Jaguar		0x000000ff
++#define bCCK_TxFilter3_C7_Jaguar		0x0000ff00
++/* NBI & CSI Mask setting */
++#define	rCSI_Mask_Setting1_Jaguar	0x874
++#define	rCSI_Fix_Mask0_Jaguar		0x880
++#define	rCSI_Fix_Mask1_Jaguar		0x884
++#define	rCSI_Fix_Mask2_Jaguar		0x888
++#define	rCSI_Fix_Mask3_Jaguar		0x88c
++#define	rCSI_Fix_Mask4_Jaguar		0x890
++#define	rCSI_Fix_Mask5_Jaguar		0x894
++#define	rCSI_Fix_Mask6_Jaguar		0x898
++#define	rCSI_Fix_Mask7_Jaguar		0x89c
++#define	rNBI_Setting_Jaguar			0x87c
++
++
++/* YN: mask the following register definition temporarily
++ * #define rPdp_AntA					0xb00
++ * #define rPdp_AntA_4				0xb04
++ * #define rConfig_Pmpd_AntA			0xb28
++ * #define rConfig_AntA					0xb68
++ * #define rConfig_AntB					0xb6c
++ * #define rPdp_AntB					0xb70
++ * #define rPdp_AntB_4					0xb74
++ * #define rConfig_Pmpd_AntB			0xb98
++ * #define rAPK							0xbd8 */
++
++/* RXIQC */
++#define rA_RxIQC_AB_Jaguar    	0xc10  /* RxIQ imblance matrix coeff. A & B */
++#define rA_RxIQC_CD_Jaguar    	0xc14  /* RxIQ imblance matrix coeff. C & D */
++#define rA_TxScale_Jaguar 		0xc1c  /* Pah_A TX scaling factor */
++#define rB_TxScale_Jaguar 		0xe1c  /* Path_B TX scaling factor */
++#define rB_RxIQC_AB_Jaguar    	0xe10  /* RxIQ imblance matrix coeff. A & B */
++#define rB_RxIQC_CD_Jaguar    	0xe14  /* RxIQ imblance matrix coeff. C & D */
++#define b_RxIQC_AC_Jaguar		0x02ff  /* bit mask for IQC matrix element A & C */
++#define b_RxIQC_BD_Jaguar		0x02ff0000 /* bit mask for IQC matrix element A & C */
++
++#define	rC_TxScale_Jaguar2 		0x181c  /* Pah_C TX scaling factor */
++#define	rD_TxScale_Jaguar2 		0x1A1c  /* Path_D TX scaling factor */
++#define	rRF_TxGainOffset		0x55
++
++/* DIG-related */
++#define rA_IGI_Jaguar				0xc50	/* Initial Gain for path-A */
++#define rB_IGI_Jaguar				0xe50	/* Initial Gain for path-B */
++#define	rC_IGI_Jaguar2				0x1850	/* Initial Gain for path-C */
++#define	rD_IGI_Jaguar2				0x1A50	/* Initial Gain for path-D */
++
++#define rOFDM_FalseAlarm1_Jaguar	0xf48  /* counter for break */
++#define rOFDM_FalseAlarm2_Jaguar	0xf4c  /* counter for spoofing */
++#define rCCK_FalseAlarm_Jaguar        	0xa5c /* counter for cck false alarm */
++#define b_FalseAlarm_Jaguar			0xffff
++#define rCCK_CCA_Jaguar				0xa08	/* cca threshold */
++#define bCCK_CCA_Jaguar				0x00ff0000
++
++/* Tx Power Ttraining-related */
++#define rA_TxPwrTraing_Jaguar		0xc54
++#define rB_TxPwrTraing_Jaguar		0xe54
++
++/* Report-related */
++#define rOFDM_ShortCFOAB_Jaguar	0xf60
++#define rOFDM_LongCFOAB_Jaguar		0xf64
++#define rOFDM_EndCFOAB_Jaguar		0xf70
++#define rOFDM_AGCReport_Jaguar		0xf84
++#define rOFDM_RxSNR_Jaguar			0xf88
++#define rOFDM_RxEVMCSI_Jaguar		0xf8c
++#define rOFDM_SIGReport_Jaguar		0xf90
++
++/* Misc functions */
++#define rEDCCA_Jaguar				0x8a4 /* EDCCA */
++#define bEDCCA_Jaguar				0xffff
++#define rAGC_table_Jaguar			0x82c   /* AGC tabel select */
++#define bAGC_table_Jaguar			0x3
++#define b_sel5g_Jaguar    				0x1000 /* sel5g */
++#define b_LNA_sw_Jaguar				0x8000 /* HW/WS control for LNA */
++#define rFc_area_Jaguar				0x860   /* fc_area */
++#define bFc_area_Jaguar				0x1ffe000
++#define rSingleTone_ContTx_Jaguar	0x914
++
++#define	rAGC_table_Jaguar2			0x958	/* AGC tabel select */
++#define	rDMA_trigger_Jaguar2		0x95C	/* ADC sample mode */
++
++
++/* RFE */
++#define rA_RFE_Pinmux_Jaguar	0xcb0  /* Path_A RFE cotrol pinmux */
++#define rB_RFE_Pinmux_Jaguar	0xeb0 /* Path_B RFE control pinmux */
++#define rA_RFE_Inv_Jaguar		0xcb4  /* Path_A RFE cotrol   */
++#define rB_RFE_Inv_Jaguar		0xeb4 /* Path_B RFE control */
++#define rA_RFE_Jaguar			0xcb8  /* Path_A RFE cotrol   */
++#define rB_RFE_Jaguar			0xeb8 /* Path_B RFE control */
++#define	rA_RFE_Inverse_Jaguar	0xCBC	/* Path_A RFE control inverse */
++#define	rB_RFE_Inverse_Jaguar	0xEBC	/* Path_B RFE control inverse */
++#define r_ANTSEL_SW_Jaguar		0x900 /* ANTSEL SW Control */
++#define bMask_RFEInv_Jaguar		0x3ff00000
++#define bMask_AntselPathFollow_Jaguar 0x00030000
++
++#define	rC_RFE_Pinmux_Jaguar	0x18B4	/* Path_C RFE cotrol pinmux */
++#define	rD_RFE_Pinmux_Jaguar	0x1AB4	/* Path_D RFE cotrol pinmux */
++#define	rA_RFE_Sel_Jaguar2		0x1990
++
++
++
++/* TX AGC */
++#define rTxAGC_A_CCK11_CCK1_JAguar				0xc20
++#define rTxAGC_A_Ofdm18_Ofdm6_JAguar				0xc24
++#define rTxAGC_A_Ofdm54_Ofdm24_JAguar			0xc28
++#define rTxAGC_A_MCS3_MCS0_JAguar					0xc2c
++#define rTxAGC_A_MCS7_MCS4_JAguar					0xc30
++#define rTxAGC_A_MCS11_MCS8_JAguar				0xc34
++#define rTxAGC_A_MCS15_MCS12_JAguar				0xc38
++#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar	0xc3c
++#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar	0xc40
++#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar	0xc44
++#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar	0xc48
++#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar	0xc4c
++#define rTxAGC_B_CCK11_CCK1_JAguar				0xe20
++#define rTxAGC_B_Ofdm18_Ofdm6_JAguar				0xe24
++#define rTxAGC_B_Ofdm54_Ofdm24_JAguar			0xe28
++#define rTxAGC_B_MCS3_MCS0_JAguar					0xe2c
++#define rTxAGC_B_MCS7_MCS4_JAguar					0xe30
++#define rTxAGC_B_MCS11_MCS8_JAguar				0xe34
++#define rTxAGC_B_MCS15_MCS12_JAguar				0xe38
++#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar		0xe3c
++#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar		0xe40
++#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar		0xe44
++#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar		0xe48
++#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar		0xe4c
++#define bTxAGC_byte0_Jaguar							0xff
++#define bTxAGC_byte1_Jaguar							0xff00
++#define bTxAGC_byte2_Jaguar							0xff0000
++#define bTxAGC_byte3_Jaguar							0xff000000
++
++
++/* TX AGC */
++#define		rTxAGC_A_CCK11_CCK1_Jaguar2	0xc20
++#define		rTxAGC_A_Ofdm18_Ofdm6_Jaguar2	0xc24
++#define		rTxAGC_A_Ofdm54_Ofdm24_Jaguar2	0xc28
++#define		rTxAGC_A_MCS3_MCS0_Jaguar2	0xc2c
++#define		rTxAGC_A_MCS7_MCS4_Jaguar2	0xc30
++#define		rTxAGC_A_MCS11_MCS8_Jaguar2	0xc34
++#define		rTxAGC_A_MCS15_MCS12_Jaguar2	0xc38
++#define		rTxAGC_A_MCS19_MCS16_Jaguar2	0xcd8
++#define		rTxAGC_A_MCS23_MCS20_Jaguar2	0xcdc
++#define		rTxAGC_A_Nss1Index3_Nss1Index0_Jaguar2	0xc3c
++#define		rTxAGC_A_Nss1Index7_Nss1Index4_Jaguar2	0xc40
++#define		rTxAGC_A_Nss2Index1_Nss1Index8_Jaguar2	0xc44
++#define		rTxAGC_A_Nss2Index5_Nss2Index2_Jaguar2	0xc48
++#define		rTxAGC_A_Nss2Index9_Nss2Index6_Jaguar2	0xc4c
++#define		rTxAGC_A_Nss3Index3_Nss3Index0_Jaguar2	0xce0
++#define		rTxAGC_A_Nss3Index7_Nss3Index4_Jaguar2	0xce4
++#define		rTxAGC_A_Nss3Index9_Nss3Index8_Jaguar2	0xce8
++#define		rTxAGC_B_CCK11_CCK1_Jaguar2	0xe20
++#define		rTxAGC_B_Ofdm18_Ofdm6_Jaguar2	0xe24
++#define		rTxAGC_B_Ofdm54_Ofdm24_Jaguar2	0xe28
++#define		rTxAGC_B_MCS3_MCS0_Jaguar2	0xe2c
++#define		rTxAGC_B_MCS7_MCS4_Jaguar2	0xe30
++#define		rTxAGC_B_MCS11_MCS8_Jaguar2	0xe34
++#define		rTxAGC_B_MCS15_MCS12_Jaguar2	0xe38
++#define		rTxAGC_B_MCS19_MCS16_Jaguar2	0xed8
++#define		rTxAGC_B_MCS23_MCS20_Jaguar2	0xedc
++#define		rTxAGC_B_Nss1Index3_Nss1Index0_Jaguar2	0xe3c
++#define		rTxAGC_B_Nss1Index7_Nss1Index4_Jaguar2	0xe40
++#define		rTxAGC_B_Nss2Index1_Nss1Index8_Jaguar2	0xe44
++#define		rTxAGC_B_Nss2Index5_Nss2Index2_Jaguar2	0xe48
++#define		rTxAGC_B_Nss2Index9_Nss2Index6_Jaguar2	0xe4c
++#define		rTxAGC_B_Nss3Index3_Nss3Index0_Jaguar2	0xee0
++#define		rTxAGC_B_Nss3Index7_Nss3Index4_Jaguar2	0xee4
++#define		rTxAGC_B_Nss3Index9_Nss3Index8_Jaguar2	0xee8
++#define		rTxAGC_C_CCK11_CCK1_Jaguar2	0x1820
++#define		rTxAGC_C_Ofdm18_Ofdm6_Jaguar2	0x1824
++#define		rTxAGC_C_Ofdm54_Ofdm24_Jaguar2	0x1828
++#define		rTxAGC_C_MCS3_MCS0_Jaguar2	0x182c
++#define		rTxAGC_C_MCS7_MCS4_Jaguar2	0x1830
++#define		rTxAGC_C_MCS11_MCS8_Jaguar2	0x1834
++#define		rTxAGC_C_MCS15_MCS12_Jaguar2	0x1838
++#define		rTxAGC_C_MCS19_MCS16_Jaguar2	0x18d8
++#define		rTxAGC_C_MCS23_MCS20_Jaguar2	0x18dc
++#define		rTxAGC_C_Nss1Index3_Nss1Index0_Jaguar2	0x183c
++#define		rTxAGC_C_Nss1Index7_Nss1Index4_Jaguar2	0x1840
++#define		rTxAGC_C_Nss2Index1_Nss1Index8_Jaguar2	0x1844
++#define		rTxAGC_C_Nss2Index5_Nss2Index2_Jaguar2	0x1848
++#define		rTxAGC_C_Nss2Index9_Nss2Index6_Jaguar2	0x184c
++#define		rTxAGC_C_Nss3Index3_Nss3Index0_Jaguar2	0x18e0
++#define		rTxAGC_C_Nss3Index7_Nss3Index4_Jaguar2	0x18e4
++#define		rTxAGC_C_Nss3Index9_Nss3Index8_Jaguar2	0x18e8
++#define		rTxAGC_D_CCK11_CCK1_Jaguar2	0x1a20
++#define		rTxAGC_D_Ofdm18_Ofdm6_Jaguar2	0x1a24
++#define		rTxAGC_D_Ofdm54_Ofdm24_Jaguar2	0x1a28
++#define		rTxAGC_D_MCS3_MCS0_Jaguar2	0x1a2c
++#define		rTxAGC_D_MCS7_MCS4_Jaguar2	0x1a30
++#define		rTxAGC_D_MCS11_MCS8_Jaguar2	0x1a34
++#define		rTxAGC_D_MCS15_MCS12_Jaguar2	0x1a38
++#define		rTxAGC_D_MCS19_MCS16_Jaguar2	0x1ad8
++#define		rTxAGC_D_MCS23_MCS20_Jaguar2	0x1adc
++#define		rTxAGC_D_Nss1Index3_Nss1Index0_Jaguar2	0x1a3c
++#define		rTxAGC_D_Nss1Index7_Nss1Index4_Jaguar2	0x1a40
++#define		rTxAGC_D_Nss2Index1_Nss1Index8_Jaguar2	0x1a44
++#define		rTxAGC_D_Nss2Index5_Nss2Index2_Jaguar2	0x1a48
++#define		rTxAGC_D_Nss2Index9_Nss2Index6_Jaguar2	0x1a4c
++#define		rTxAGC_D_Nss3Index3_Nss3Index0_Jaguar2	0x1ae0
++#define		rTxAGC_D_Nss3Index7_Nss3Index4_Jaguar2	0x1ae4
++#define		rTxAGC_D_Nss3Index9_Nss3Index8_Jaguar2	0x1ae8
++/* IQK YN: temporaily mask this part
++ * #define rFPGA0_IQK					0xe28
++ * #define rTx_IQK_Tone_A				0xe30
++ * #define rRx_IQK_Tone_A				0xe34
++ * #define rTx_IQK_PI_A					0xe38
++ * #define rRx_IQK_PI_A					0xe3c */
++
++/* #define rTx_IQK						0xe40 */
++/* #define rRx_IQK						0xe44 */
++/* #define rIQK_AGC_Pts					0xe48 */
++/* #define rIQK_AGC_Rsp					0xe4c */
++/* #define rTx_IQK_Tone_B				0xe50 */
++/* #define rRx_IQK_Tone_B				0xe54 */
++/* #define rTx_IQK_PI_B					0xe58 */
++/* #define rRx_IQK_PI_B					0xe5c */
++/* #define rIQK_AGC_Cont				0xe60 */
++
++
++/* AFE-related */
++#define rA_AFEPwr1_Jaguar					0xc60 /* dynamic AFE power control */
++#define rA_AFEPwr2_Jaguar					0xc64 /* dynamic AFE power control */
++#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar	0xc68
++#define rA_Tx_CCKBBON_OFDMRFON_Jaguar	0xc6c
++#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar		0xc70
++#define rA_Tx2Tx_RXCCK_Jaguar				0xc74
++#define rA_Rx_OFDM_WaitRIFS_Jaguar			0xc78
++#define rA_Rx2Rx_BT_Jaguar					0xc7c
++#define rA_sleep_nav_Jaguar					0xc80
++#define rA_pmpd_Jaguar						0xc84
++#define rB_AFEPwr1_Jaguar					0xe60 /* dynamic AFE power control */
++#define rB_AFEPwr2_Jaguar					0xe64 /* dynamic AFE power control */
++#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar	0xe68
++#define rB_Tx_CCKBBON_OFDMRFON_Jaguar	0xe6c
++#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar		0xe70
++#define rB_Tx2Tx_RXCCK_Jaguar				0xe74
++#define rB_Rx_OFDM_WaitRIFS_Jaguar			0xe78
++#define rB_Rx2Rx_BT_Jaguar					0xe7c
++#define rB_sleep_nav_Jaguar					0xe80
++#define rB_pmpd_Jaguar						0xe84
++
++
++/* YN: mask these registers temporaily
++ * #define rTx_Power_Before_IQK_A		0xe94
++ * #define rTx_Power_After_IQK_A			0xe9c */
++
++/* #define rRx_Power_Before_IQK_A		0xea0 */
++/* #define rRx_Power_Before_IQK_A_2		0xea4 */
++/* #define rRx_Power_After_IQK_A			0xea8 */
++/* #define rRx_Power_After_IQK_A_2		0xeac */
++
++/* #define rTx_Power_Before_IQK_B		0xeb4 */
++/* #define rTx_Power_After_IQK_B			0xebc */
++
++/* #define rRx_Power_Before_IQK_B		0xec0 */
++/* #define rRx_Power_Before_IQK_B_2		0xec4 */
++/* #define rRx_Power_After_IQK_B			0xec8 */
++/* #define rRx_Power_After_IQK_B_2		0xecc */
++
++
++/* RSSI Dump */
++#define rA_RSSIDump_Jaguar			0xBF0
++#define rB_RSSIDump_Jaguar			0xBF1
++#define rS1_RXevmDump_Jaguar		0xBF4
++#define rS2_RXevmDump_Jaguar		0xBF5
++#define rA_RXsnrDump_Jaguar		0xBF6
++#define rB_RXsnrDump_Jaguar		0xBF7
++#define rA_CfoShortDump_Jaguar		0xBF8
++#define rB_CfoShortDump_Jaguar		0xBFA
++#define rA_CfoLongDump_Jaguar		0xBEC
++#define rB_CfoLongDump_Jaguar		0xBEE
++
++
++/* RF Register
++ *   */
++#define RF_AC_Jaguar				0x00	/*  */
++#define RF_RF_Top_Jaguar			0x07	/*  */
++#define RF_TXLOK_Jaguar				0x08	/*  */
++#define RF_TXAPK_Jaguar				0x0B
++#define RF_CHNLBW_Jaguar 			0x18	/* RF channel and BW switch */
++#define RF_RCK1_Jaguar				0x1c	/*  */
++#define RF_RCK2_Jaguar				0x1d
++#define RF_RCK3_Jaguar			0x1e
++#define RF_ModeTableAddr			0x30
++#define RF_ModeTableData0			0x31
++#define RF_ModeTableData1			0x32
++#define RF_TxLCTank_Jaguar	0x54
++#define RF_APK_Jaguar				0x63
++#define RF_LCK						0xB4
++#define RF_WeLut_Jaguar				0xEF
++
++#define bRF_CHNLBW_MOD_AG_Jaguar	0x70300
++#define bRF_CHNLBW_BW				0xc00
++
++
++/*
++ * RL6052 Register definition
++ *   */
++#define RF_AC						0x00	/*  */
++#define RF_IPA_A					0x0C	/*  */
++#define RF_TXBIAS_A					0x0D
++#define RF_BS_PA_APSET_G9_G11		0x0E
++#define RF_MODE1					0x10	/*  */
++#define RF_MODE2					0x11	/*  */
++#define RF_CHNLBW					0x18	/* RF channel and BW switch */
++#define RF_RCK_OS					0x30	/* RF TX PA control */
++#define RF_TXPA_G1					0x31	/* RF TX PA control */
++#define RF_TXPA_G2					0x32	/* RF TX PA control */
++#define RF_TXPA_G3					0x33	/* RF TX PA control */
++#define RF_0x52						0x52
++#define RF_WE_LUT					0xEF
++
++/*
++ * Bit Mask
++ *
++ * 1. Page1(0x100) */
++#define bBBResetB					0x100	/* Useless now? */
++#define bGlobalResetB				0x200
++#define bOFDMTxStart				0x4
++#define bCCKTxStart					0x8
++#define bCRC32Debug					0x100
++#define bPMACLoopback				0x10
++#define bTxLSIG						0xffffff
++#define bOFDMTxRate					0xf
++#define bOFDMTxReserved			0x10
++#define bOFDMTxLength				0x1ffe0
++#define bOFDMTxParity				0x20000
++#define bTxHTSIG1					0xffffff
++#define bTxHTMCSRate				0x7f
++#define bTxHTBW						0x80
++#define bTxHTLength					0xffff00
++#define bTxHTSIG2					0xffffff
++#define bTxHTSmoothing				0x1
++#define bTxHTSounding				0x2
++#define bTxHTReserved				0x4
++#define bTxHTAggreation				0x8
++#define bTxHTSTBC					0x30
++#define bTxHTAdvanceCoding			0x40
++#define bTxHTShortGI					0x80
++#define bTxHTNumberHT_LTF			0x300
++#define bTxHTCRC8					0x3fc00
++#define bCounterReset				0x10000
++#define bNumOfOFDMTx				0xffff
++#define bNumOfCCKTx					0xffff0000
++#define bTxIdleInterval				0xffff
++#define bOFDMService				0xffff0000
++#define bTxMACHeader				0xffffffff
++#define bTxDataInit					0xff
++#define bTxHTMode					0x100
++#define bTxDataType					0x30000
++#define bTxRandomSeed				0xffffffff
++#define bCCKTxPreamble				0x1
++#define bCCKTxSFD					0xffff0000
++#define bCCKTxSIG					0xff
++#define bCCKTxService				0xff00
++#define bCCKLengthExt				0x8000
++#define bCCKTxLength				0xffff0000
++#define bCCKTxCRC16					0xffff
++#define bCCKTxStatus					0x1
++#define bOFDMTxStatus				0x2
++
++
++/*
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 1. Page1(0x100)
++ *   */
++#define rPMAC_Reset					0x100
++#define rPMAC_TxStart				0x104
++#define rPMAC_TxLegacySIG			0x108
++#define rPMAC_TxHTSIG1				0x10c
++#define rPMAC_TxHTSIG2				0x110
++#define rPMAC_PHYDebug				0x114
++#define rPMAC_TxPacketNum			0x118
++#define rPMAC_TxIdle					0x11c
++#define rPMAC_TxMACHeader0			0x120
++#define rPMAC_TxMACHeader1			0x124
++#define rPMAC_TxMACHeader2			0x128
++#define rPMAC_TxMACHeader3			0x12c
++#define rPMAC_TxMACHeader4			0x130
++#define rPMAC_TxMACHeader5			0x134
++#define rPMAC_TxDataType			0x138
++#define rPMAC_TxRandomSeed		0x13c
++#define rPMAC_CCKPLCPPreamble		0x140
++#define rPMAC_CCKPLCPHeader		0x144
++#define rPMAC_CCKCRC16				0x148
++#define rPMAC_OFDMRxCRC32OK		0x170
++#define rPMAC_OFDMRxCRC32Er		0x174
++#define rPMAC_OFDMRxParityEr		0x178
++#define rPMAC_OFDMRxCRC8Er			0x17c
++#define rPMAC_CCKCRxRC16Er			0x180
++#define rPMAC_CCKCRxRC32Er			0x184
++#define rPMAC_CCKCRxRC32OK			0x188
++#define rPMAC_TxStatus				0x18c
++
++/*
++ * 3. Page8(0x800)
++ *   */
++#define rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
++
++#define rFPGA0_TxInfo				0x804	/* Status report?? */
++#define rFPGA0_PSDFunction			0x808
++#define rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
++
++#define rFPGA0_XA_HSSIParameter1	0x820	/* RF 3 wire register */
++#define rFPGA0_XA_HSSIParameter2	0x824
++#define rFPGA0_XB_HSSIParameter1	0x828
++#define rFPGA0_XB_HSSIParameter2	0x82c
++
++#define	rFPGA0_XA_LSSIParameter		0x840
++#define	rFPGA0_XB_LSSIParameter		0x844
++
++#define rFPGA0_XAB_SwitchControl	0x858	/* RF Channel switch */
++#define rFPGA0_XCD_SwitchControl	0x85c
++
++#define rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
++#define rFPGA0_XCD_RFParameter		0x87c
++
++#define rFPGA0_AnalogParameter1	0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
++#define rFPGA0_AnalogParameter2	0x884
++#define rFPGA0_AnalogParameter3	0x888
++#define rFPGA0_AdDaClockEn			0x888	/* enable ad/da clock1 for dual-phy */
++#define rFPGA0_AnalogParameter4	0x88c
++
++#define	rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
++#define	rFPGA0_XB_LSSIReadBack		0x8a4
++#define	rFPGA0_XC_LSSIReadBack		0x8a8
++#define	rFPGA0_XD_LSSIReadBack		0x8ac
++
++#define rFPGA0_XCD_RFPara	0x8b4
++#define	rFPGA0_PSDReport				0x8b4	/* Useless now */
++#define	TransceiverA_HSPI_Readback		0x8b8	/* Transceiver A HSPI Readback */
++#define	TransceiverB_HSPI_Readback		0x8bc	/* Transceiver B HSPI Readback */
++#define	rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
++#define	rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
++
++/*
++ * 4. Page9(0x900)
++ *   */
++#define rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
++#define	REG_BB_TX_PATH_SEL_1_8814A		0x93c
++#define	REG_BB_TX_PATH_SEL_2_8814A		0x940
++#define rFPGA1_TxBlock				0x904	/* Useless now */
++#define rFPGA1_DebugSelect			0x908	/* Useless now */
++#define rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
++/*Page 19 for TxBF*/
++#define	REG_BB_TXBF_ANT_SET_BF1_8814A	0x19ac
++#define	REG_BB_TXBF_ANT_SET_BF0_8814A	0x19b4
++/*
++ * PageA(0xA00)
++ *   */
++#define rCCK0_System				0xa00
++#define rCCK0_AFESetting				0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
++#define	rCCK0_DSPParameter2			0xa1c	/* SQ threshold */
++#define rCCK0_TxFilter1				0xa20
++#define rCCK0_TxFilter2				0xa24
++#define rCCK0_DebugPort				0xa28	/* debug port and Tx filter3 */
++#define	rCCK0_FalseAlarmReport			0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
++
++/*
++ * PageB(0xB00)
++ *   */
++#define rPdp_AntA				0xb00
++#define rPdp_AntA_4				0xb04
++#define rConfig_Pmpd_AntA			0xb28
++#define rConfig_AntA					0xb68
++#define rConfig_AntB					0xb6c
++#define rPdp_AntB					0xb70
++#define rPdp_AntB_4					0xb74
++#define rConfig_Pmpd_AntB			0xb98
++#define rAPK							0xbd8
++
++/*
++ * 6. PageC(0xC00)
++ *   */
++#define rOFDM0_LSTF					0xc00
++
++#define rOFDM0_TRxPathEnable		0xc04
++#define rOFDM0_TRMuxPar			0xc08
++#define rOFDM0_TRSWIsolation		0xc0c
++
++#define rOFDM0_XARxAFE				0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
++#define rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
++#define rOFDM0_XBRxAFE		0xc18
++#define rOFDM0_XBRxIQImbalance	0xc1c
++#define rOFDM0_XCRxAFE		0xc20
++#define rOFDM0_XCRxIQImbalance	0xc24
++#define rOFDM0_XDRxAFE		0xc28
++#define rOFDM0_XDRxIQImbalance	0xc2c
++
++#define rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
++#define rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
++#define rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
++#define rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
++
++#define rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
++#define rOFDM0_CFOandDAGC			0xc44  /* CFO & DAGC */
++#define rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
++#define rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
++
++#define rOFDM0_XAAGCCore1			0xc50	/* DIG */
++#define rOFDM0_XAAGCCore2			0xc54
++#define rOFDM0_XBAGCCore1			0xc58
++#define rOFDM0_XBAGCCore2			0xc5c
++#define rOFDM0_XCAGCCore1			0xc60
++#define rOFDM0_XCAGCCore2			0xc64
++#define rOFDM0_XDAGCCore1			0xc68
++#define rOFDM0_XDAGCCore2			0xc6c
++
++#define rOFDM0_AGCParameter1		0xc70
++#define rOFDM0_AGCParameter2		0xc74
++#define rOFDM0_AGCRSSITable		0xc78
++#define rOFDM0_HTSTFAGC			0xc7c
++
++#define rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
++#define rOFDM0_XATxAFE				0xc84
++#define rOFDM0_XBTxIQImbalance		0xc88
++#define rOFDM0_XBTxAFE				0xc8c
++#define rOFDM0_XCTxIQImbalance		0xc90
++#define rOFDM0_XCTxAFE		0xc94
++#define rOFDM0_XDTxIQImbalance		0xc98
++#define rOFDM0_XDTxAFE				0xc9c
++
++#define rOFDM0_RxIQExtAnta			0xca0
++#define rOFDM0_TxCoeff1				0xca4
++#define rOFDM0_TxCoeff2				0xca8
++#define rOFDM0_TxCoeff3				0xcac
++#define rOFDM0_TxCoeff4				0xcb0
++#define rOFDM0_TxCoeff5				0xcb4
++#define rOFDM0_TxCoeff6				0xcb8
++#define rOFDM0_RxHPParameter		0xce0
++#define rOFDM0_TxPseudoNoiseWgt	0xce4
++#define rOFDM0_FrameSync			0xcf0
++#define rOFDM0_DFSReport			0xcf4
++
++/*
++ * 7. PageD(0xD00)
++ *   */
++#define rOFDM1_LSTF					0xd00
++#define rOFDM1_TRxPathEnable		0xd04
++
++/*
++ * 8. PageE(0xE00)
++ *   */
++#define rTxAGC_A_Rate18_06			0xe00
++#define rTxAGC_A_Rate54_24			0xe04
++#define rTxAGC_A_CCK1_Mcs32		0xe08
++#define rTxAGC_A_Mcs03_Mcs00		0xe10
++#define rTxAGC_A_Mcs07_Mcs04		0xe14
++#define rTxAGC_A_Mcs11_Mcs08		0xe18
++#define rTxAGC_A_Mcs15_Mcs12		0xe1c
++
++#define rTxAGC_B_Rate18_06			0x830
++#define rTxAGC_B_Rate54_24			0x834
++#define rTxAGC_B_CCK1_55_Mcs32	0x838
++#define rTxAGC_B_Mcs03_Mcs00		0x83c
++#define rTxAGC_B_Mcs07_Mcs04		0x848
++#define rTxAGC_B_Mcs11_Mcs08		0x84c
++#define rTxAGC_B_Mcs15_Mcs12		0x868
++#define rTxAGC_B_CCK11_A_CCK2_11	0x86c
++
++#define rFPGA0_IQK					0xe28
++#define rTx_IQK_Tone_A				0xe30
++#define rRx_IQK_Tone_A				0xe34
++#define rTx_IQK_PI_A				0xe38
++#define rRx_IQK_PI_A				0xe3c
++
++#define rTx_IQK						0xe40
++#define rRx_IQK						0xe44
++#define rIQK_AGC_Pts					0xe48
++#define rIQK_AGC_Rsp				0xe4c
++#define rTx_IQK_Tone_B				0xe50
++#define rRx_IQK_Tone_B				0xe54
++#define rTx_IQK_PI_B					0xe58
++#define rRx_IQK_PI_B					0xe5c
++#define rIQK_AGC_Cont				0xe60
++
++#define rBlue_Tooth					0xe6c
++#define rRx_Wait_CCA				0xe70
++#define rTx_CCK_RFON				0xe74
++#define rTx_CCK_BBON				0xe78
++#define rTx_OFDM_RFON				0xe7c
++#define rTx_OFDM_BBON				0xe80
++#define rTx_To_Rx					0xe84
++#define rTx_To_Tx					0xe88
++#define rRx_CCK						0xe8c
++
++#define rTx_Power_Before_IQK_A		0xe94
++#define rTx_Power_After_IQK_A		0xe9c
++
++#define rRx_Power_Before_IQK_A		0xea0
++#define rRx_Power_Before_IQK_A_2	0xea4
++#define rRx_Power_After_IQK_A		0xea8
++#define rRx_Power_After_IQK_A_2		0xeac
++
++#define rTx_Power_Before_IQK_B		0xeb4
++#define rTx_Power_After_IQK_B		0xebc
++
++#define rRx_Power_Before_IQK_B		0xec0
++#define rRx_Power_Before_IQK_B_2	0xec4
++#define rRx_Power_After_IQK_B		0xec8
++#define rRx_Power_After_IQK_B_2		0xecc
++
++#define rRx_OFDM					0xed0
++#define rRx_Wait_RIFS				0xed4
++#define rRx_TO_Rx					0xed8
++#define rStandby						0xedc
++#define rSleep						0xee0
++#define rPMPD_ANAEN				0xeec
++
++
++/* 2. Page8(0x800) */
++#define bRFMOD						0x1	/* Reg 0x800 rFPGA0_RFMOD */
++#define bJapanMode					0x2
++#define bCCKTxSC					0x30
++#define bCCKEn						0x1000000
++#define bOFDMEn						0x2000000
++#define bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
++#define bXCTxAGC			0xf000
++#define bXDTxAGC			0xf0000
++
++/* 4. PageA(0xA00) */
++#define bCCKBBMode                			0x3	/* Useless */
++#define bCCKTxPowerSaving		0x80
++#define bCCKRxPowerSaving		0x40
++
++#define bCCKSideBand              		0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
++
++#define bCCKScramble              		0x8	/* Useless */
++#define bCCKAntDiversity			0x8000
++#define bCCKCarrierRecovery		0x4000
++#define bCCKTxRate			0x3000
++#define bCCKDCCancel			0x0800
++#define bCCKISICancel			0x0400
++#define bCCKMatchFilter		0x0200
++#define bCCKEqualizer			0x0100
++#define bCCKPreambleDetect		0x800000
++#define bCCKFastFalseCCA		0x400000
++#define bCCKChEstStart		0x300000
++#define bCCKCCACount		0x080000
++#define bCCKcs_lim			0x070000
++#define bCCKBistMode			0x80000000
++#define bCCKCCAMask			0x40000000
++#define bCCKTxDACPhase		0x4
++#define bCCKRxADCPhase         	   	0x20000000   /* r_rx_clk */
++#define bCCKr_cp_mode0		0x0100
++#define bCCKTxDCOffset		0xf0
++#define bCCKRxDCOffset		0xf
++#define bCCKCCAMode			0xc000
++#define bCCKFalseCS_lim		0x3f00
++#define bCCKCS_ratio			0xc00000
++#define bCCKCorgBit_sel		0x300000
++#define bCCKPD_lim			0x0f0000
++#define bCCKNewCCA		0x80000000
++#define bCCKRxHPofIG		0x8000
++#define bCCKRxIG			0x7f00
++#define bCCKLNAPolarity		0x800000
++#define bCCKRx1stGain		0x7f0000
++#define bCCKRFExtend              		0x20000000 /* CCK Rx Iinital gain polarity */
++#define bCCKRxAGCSatLevel		0x1f000000
++#define bCCKRxAGCSatCount		0xe0
++#define bCCKRxRFSettle            		0x1f       /* AGCsamp_dly */
++#define bCCKFixedRxAGC		0x8000
++/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
++#define bCCKAntennaPolarity		0x2000
++#define bCCKTxFilterType		0x0c00
++#define bCCKRxAGCReportType		0x0300
++#define bCCKRxDAGCEn		0x80000000
++#define bCCKRxDAGCPeriod		0x20000000
++#define bCCKRxDAGCSatLevel		0x1f000000
++#define bCCKTimingRecovery		0x800000
++#define bCCKTxC0			0x3f0000
++#define bCCKTxC1			0x3f000000
++#define bCCKTxC2			0x3f
++#define bCCKTxC3			0x3f00
++#define bCCKTxC4			0x3f0000
++#define bCCKTxC5			0x3f000000
++#define bCCKTxC6			0x3f
++#define bCCKTxC7			0x3f00
++#define bCCKDebugPort		0xff0000
++#define bCCKDACDebug		0x0f000000
++#define bCCKFalseAlarmEnable		0x8000
++#define bCCKFalseAlarmRead		0x4000
++#define bCCKTRSSI			0x7f
++#define bCCKRxAGCReport		0xfe
++#define bCCKRxReport_AntSel		0x80000000
++#define bCCKRxReport_MFOff		0x40000000
++#define bCCKRxRxReport_SQLoss	0x20000000
++#define bCCKRxReport_Pktloss		0x10000000
++#define bCCKRxReport_Lockedbit	0x08000000
++#define bCCKRxReport_RateError	0x04000000
++#define bCCKRxReport_RxRate		0x03000000
++#define bCCKRxFACounterLower	0xff
++#define bCCKRxFACounterUpper	0xff000000
++#define bCCKRxHPAGCStart		0xe000
++#define bCCKRxHPAGCFinal		0x1c00
++#define bCCKRxFalseAlarmEnable	0x8000
++#define bCCKFACounterFreeze		0x4000
++#define bCCKTxPathSel		0x10000000
++#define bCCKDefaultRxPath		0xc000000
++#define bCCKOptionRxPath		0x3000000
++
++#define		RF_T_METER_88E				0x42
++
++/* 6. PageE(0xE00) */
++#define bSTBCEn                  			0x4	/* Useless */
++#define bAntennaMapping		0x10
++#define bNss				0x20
++#define bCFOAntSumD		0x200
++#define bPHYCounterReset		0x8000000
++#define bCFOReportGet			0x4000000
++#define bOFDMContinueTx		0x10000000
++#define bOFDMSingleCarrier		0x20000000
++#define bOFDMSingleTone		0x40000000
++
++
++/*
++ * Other Definition
++ *   */
++
++#define bEnable                   0x1	/* Useless */
++#define bDisable                  0x0
++
++/* byte endable for srwrite */
++#define bByte0                    		0x1	/* Useless */
++#define bByte1		0x2
++#define bByte2		0x4
++#define bByte3		0x8
++#define bWord0		0x3
++#define bWord1		0xc
++#define bDWord		0xf
++
++/* for PutRegsetting & GetRegSetting BitMask */
++#define bMaskByte0                		0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
++#define bMaskByte1		0xff00
++#define bMaskByte2		0xff0000
++#define bMaskByte3		0xff000000
++#define bMaskHWord	0xffff0000
++#define bMaskLWord		0x0000ffff
++#define bMaskDWord	0xffffffff
++#define bMaskH3Bytes				0xffffff00
++#define bMask12Bits				0xfff
++#define bMaskH4Bits				0xf0000000
++#define bMaskOFDM_D			0xffc00000
++#define bMaskCCK				0x3f3f3f3f
++#define bMask7bits				0x7f
++#define bMaskByte2HighNibble			0x00f00000
++#define bMaskByte3LowNibble				0x0f000000
++#define bMaskL3Bytes			0x00ffffff
++
++/*--------------------------Define Parameters-------------------------------*/
++
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8814PwrSeq.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8814PwrSeq.h
+new file mode 100644
+index 000000000..0138850c9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8814PwrSeq.h
+@@ -0,0 +1,231 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++
++#ifndef __HAL8814PWRSEQ_H__
++#define __HAL8814PWRSEQ_H__
++
++#include "HalPwrSeqCmd.h"
++
++/*
++	Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf
++	There are 6 HW Power States:
++	0: POFF--Power Off
++	1: PDN--Power Down
++	2: CARDEMU--Card Emulation
++	3: ACT--Active Mode
++	4: LPS--Low Power State
++	5: SUS--Suspend
++
++	The transision from different states are defined below
++	TRANS_CARDEMU_TO_ACT
++	TRANS_ACT_TO_CARDEMU
++	TRANS_CARDEMU_TO_SUS
++	TRANS_SUS_TO_CARDEMU
++	TRANS_CARDEMU_TO_PDN
++	TRANS_ACT_TO_LPS
++	TRANS_LPS_TO_ACT
++
++	TRANS_END
++*/
++#define	RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS	16
++#define	RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS	20
++#define	RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS	17
++#define	RTL8814A_TRANS_SUS_TO_CARDEMU_STEPS	15
++#define	RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS	17
++#define	RTL8814A_TRANS_PDN_TO_CARDEMU_STEPS	16
++#define	RTL8814A_TRANS_ACT_TO_LPS_STEPS	20
++#define	RTL8814A_TRANS_LPS_TO_ACT_STEPS	15
++#define	RTL8814A_TRANS_END_STEPS	1
++
++
++#define RTL8814A_TRANS_CARDEMU_TO_ACT														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
++	{0x002B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /* ??0x28[24]=1, enable pll phase select*/ \
++	{0x0015, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT3 | BIT2 | BIT1), (BIT3 | BIT2 | BIT1)},/* 0x14[11:9]=3'b111, OCP current threshold = 1.5A */ \
++	{0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0E, 0x08},/* 0x2C[11:9]=3'b100, select lpf R3 */ \
++	{0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x70, 0x50},/* 0x2C[14:12]=3'b101, select lpf Rs*/ \
++	{0x007B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x78[30]=1'b1, SDM order select*/ \
++	/*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, */ /* disable HWPDN 0x04[15]=0*/ \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/	\
++	{0x00F0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* */	\
++	{0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x30, 0x20},/* */	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/
++
++#define RTL8814A_TRANS_ACT_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4	turn off 3-wire */	\
++	{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4	turn off 3-wire */	\
++	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},  /* 0x2[0] = 0	 RESET BB, CLOSE RF */	\
++	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/	\
++	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
++	{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},  /* 0x2[0] = 0	 RESET BB, CLOSE RF */	\
++	{0x0002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/	\
++	{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
++	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},  /*0x1F[7:0] = 0 turn off RF*/	\
++	/*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},*/  /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */	\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x28},   /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/	\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},   /*0x8[1] = 0 ANA clk = 500k */	\
++	/*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0},*/   /*  0x02[1:0] = 0	reset BB */	\
++	{0x0066, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},   /*0x66[7]=0, disable ckreq for gpio7 output SUS */	\
++	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},   /*0x41[4]=0, disable sic for gpio7 output SUS */	\
++	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},   /*0x42[1]=0, disable ckout for gpio7 output SUS */	\
++	{0x004e, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},   /*0x4E[5]=1, disable LED2 for gpio7 output SUS */	\
++	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},   /*0x41[0]=0, disable uart for gpio7 output SUS */	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
++
++#define RTL8814A_TRANS_CARDEMU_TO_SUS													\
++	/* format */								\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0c},\
++	{0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0E},\
++	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x07},/* gpio11 input mode, gpio10~8 output mode */	\
++	{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */	\
++	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */	\
++	{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */	\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */	\
++	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x14[13] = 1 turn on ZCD */	\
++	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x14[14] =1 trun on ZCD */	\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */	\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */	\
++	{0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */	\
++	{0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend */
++
++#define RTL8814A_TRANS_SUS_TO_CARDEMU													\
++	/* format */								\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0 enable WL suspend*/   \
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */	\
++	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x14[14] =0 trun off ZCD */	\
++	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x14[13] = 0 turn off ZCD */	\
++	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */	\
++	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
++
++#define RTL8814A_TRANS_CARDEMU_TO_CARDDIS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	/**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/	\
++	/**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/	\
++	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 3081*/	\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x01}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/	\
++	{0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x30}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/	\
++	/*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},*/   \
++	/*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},*/   \
++	/*{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},*/  /* gpio11 input mode, gpio10~8 output mode */	\
++	{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */	\
++	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */	\
++	{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */	\
++	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x15[6] =1 trun on ZCD output */	\
++	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x15[5] = 1 turn on ZCD */	\
++	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*0x12[6] = 0 force PFM mode */	\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */	\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */	\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
++	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x01f[1]=0 , disable RFC_0  control  REG_RF_CTRL_8814A */	\
++	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x020[1]=0 , disable RFC_1  control  REG_RF_CTRL_8814A */	\
++	{0x0021, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x021[1]=0 , disable RFC_2  control  REG_RF_CTRL_8814A */	\
++	{0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x076[1]=0 , disable RFC_3  control REG_OPT_CTRL_8814A +2 */	\
++	{0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */	\
++	{0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend*/
++
++#define RTL8814A_TRANS_CARDDIS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/                       \
++	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*0x12[6] = 1 force PWM mode */	\
++	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x15[5] = 0 turn off ZCD */	\
++	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x15[6] =0 trun off ZCD output */	\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */	\
++	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */	\
++	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /* gpio11 input mode, gpio10~8 input mode */ \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0, enable WL suspend*/	\
++	/*{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},*/ /*0x03[2] = 1, enable 3081*/	\
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/		\
++	{0x0071, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*0x70[10] = 0, CPHY_MBIAS_EN disable*/
++
++
++#define RTL8814A_TRANS_CARDEMU_TO_PDN												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
++
++#define RTL8814A_TRANS_PDN_TO_CARDEMU												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
++
++#define RTL8814A_TRANS_ACT_TO_LPS														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/		\
++	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4	turn off 3-wire */	\
++	{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4	turn off 3-wire */	\
++	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/	\
++	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
++	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
++	{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/	\
++	{0x0002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
++	{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/			\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/		\
++	{0x05F1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Respond TxOK to scheduler*/
++
++
++#define RTL8814A_TRANS_LPS_TO_ACT															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/	\
++	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/	\
++	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /* Delay*/	\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/	\
++	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /* Polling 0x109[7]=0  TSF in 40M*/			\
++	/*{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, */ /*.	??0x29[7:6] = 2b'00	 enable BB clock*/	\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/					\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/	\
++	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/	\
++	{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x1002[1:0] = 2b'11	 enable BB macro*/	\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
++
++#define RTL8814A_TRANS_END																\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/		\
++	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
++
++
++extern WLAN_PWR_CFG rtl8814A_power_on_flow[RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8814A_radio_off_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8814A_card_disable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8814A_card_enable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8814A_suspend_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8814A_resume_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8814A_hwpdn_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8814A_enter_lps_flow[RTL8814A_TRANS_ACT_TO_LPS_STEPS + RTL8814A_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8814A_leave_lps_flow[RTL8814A_TRANS_LPS_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS];
++
++#endif /* __HAL8814PWRSEQ_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8821APwrSeq.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8821APwrSeq.h
+new file mode 100644
+index 000000000..568b8e5fc
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/Hal8821APwrSeq.h
+@@ -0,0 +1,200 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef REALTEK_POWER_SEQUENCE_8821
++#define REALTEK_POWER_SEQUENCE_8821
++
++#include "HalPwrSeqCmd.h"
++
++/*
++	Check document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd
++	There are 6 HW Power States:
++	0: POFF--Power Off
++	1: PDN--Power Down
++	2: CARDEMU--Card Emulation
++	3: ACT--Active Mode
++	4: LPS--Low Power State
++	5: SUS--Suspend
++
++	The transision from different states are defined below
++	TRANS_CARDEMU_TO_ACT
++	TRANS_ACT_TO_CARDEMU
++	TRANS_CARDEMU_TO_SUS
++	TRANS_SUS_TO_CARDEMU
++	TRANS_CARDEMU_TO_PDN
++	TRANS_ACT_TO_LPS
++	TRANS_LPS_TO_ACT
++
++	TRANS_END
++*/
++#define	RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS	25
++#define	RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS	15
++#define	RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS	15
++#define	RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS	15
++#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS	15
++#define	RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS	15
++#define	RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS	15
++#define	RTL8821A_TRANS_ACT_TO_LPS_STEPS	15
++#define	RTL8821A_TRANS_LPS_TO_ACT_STEPS	15
++#define	RTL8821A_TRANS_END_STEPS	1
++
++
++#define RTL8821A_TRANS_CARDEMU_TO_ACT														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \
++	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/	\
++	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
++	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/	\
++	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
++	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */	\
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	\
++	{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */\
++	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5 | BIT4), (BIT5 | BIT4)},/*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */\
++	{0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*anapar_mac<118> , 0x25[6]=0 by wlan single function*/\
++	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
++	{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
++	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
++	{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
++	{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
++	{0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3A},/*0x7A = 0x3A start BT*/\
++	{0x002E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF , 0x82 },/* 0x2C[23:12]=0x820 ; XTAL trim */ \
++	{0x0010, PWR_CUT_A_MSK , PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 },/* 0x10[6]=1 ; MP·s¼W¹ï©ó0x2Cªº±±¨îÅv¡A¶·§â0x10[6]³]¬°1¤~¯àÅýWLAN±±¨î */ \
++
++
++#define RTL8821A_TRANS_ACT_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
++	{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
++	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
++	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
++	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/   \
++
++
++#define RTL8821A_TRANS_CARDEMU_TO_SUS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
++
++#define RTL8821A_TRANS_SUS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
++
++#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
++	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
++
++#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU													\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
++	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
++
++
++#define RTL8821A_TRANS_CARDEMU_TO_PDN												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
++	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
++	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
++
++#define RTL8821A_TRANS_PDN_TO_CARDEMU												\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
++
++#define RTL8821A_TRANS_ACT_TO_LPS														\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
++	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
++	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
++	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
++
++
++#define RTL8821A_TRANS_LPS_TO_ACT															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
++	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
++	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
++	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
++	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
++	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
++	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
++	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
++	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
++	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
++
++#define RTL8821A_TRANS_END															\
++	/* format */																\
++	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
++	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
++
++
++	extern WLAN_PWR_CFG rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8821A_card_enable_flow[RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS + RTL8821A_TRANS_END_STEPS];
++	extern WLAN_PWR_CFG rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/HalPwrSeqCmd.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/HalPwrSeqCmd.h
+new file mode 100644
+index 000000000..f67ed22d1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/HalPwrSeqCmd.h
+@@ -0,0 +1,130 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HALPWRSEQCMD_H__
++#define __HALPWRSEQCMD_H__
++
++#include <drv_types.h>
++
++/*---------------------------------------------*/
++/* 3 The value of cmd: 4 bits
++ *---------------------------------------------*/
++#define PWR_CMD_READ			0x00
++/* offset: the read register offset
++ * msk: the mask of the read value
++ * value: N/A, left by 0
++ * note: dirver shall implement this function by read & msk */
++
++#define PWR_CMD_WRITE			0x01
++/* offset: the read register offset
++ * msk: the mask of the write bits
++ * value: write value
++ * note: driver shall implement this cmd by read & msk after write */
++
++#define PWR_CMD_POLLING			0x02
++/* offset: the read register offset
++ * msk: the mask of the polled value
++ * value: the value to be polled, masked by the msd field.
++ * note: driver shall implement this cmd by
++ * do {
++ * if( (Read(offset) & msk) == (value & msk) )
++ * break;
++ * } while(not timeout); */
++
++#define PWR_CMD_DELAY			0x03
++/* offset: the value to delay
++ * msk: N/A
++ * value: the unit of delay, 0: us, 1: ms */
++
++#define PWR_CMD_END				0x04
++/* offset: N/A
++ * msk: N/A
++ * value: N/A */
++
++/*---------------------------------------------*/
++/* 3 The value of base: 4 bits
++ *---------------------------------------------
++    * define the base address of each block */
++#define PWR_BASEADDR_MAC		0x00
++#define PWR_BASEADDR_USB		0x01
++#define PWR_BASEADDR_PCIE		0x02
++#define PWR_BASEADDR_SDIO		0x03
++
++/*---------------------------------------------*/
++/* 3 The value of interface_msk: 4 bits
++ *---------------------------------------------*/
++#define	PWR_INTF_SDIO_MSK		BIT(0)
++#define	PWR_INTF_USB_MSK		BIT(1)
++#define	PWR_INTF_PCI_MSK		BIT(2)
++#define	PWR_INTF_ALL_MSK		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
++
++/*---------------------------------------------*/
++/* 3 The value of fab_msk: 4 bits
++ *---------------------------------------------*/
++#define	PWR_FAB_TSMC_MSK		BIT(0)
++#define	PWR_FAB_UMC_MSK			BIT(1)
++#define	PWR_FAB_ALL_MSK			(BIT(0) | BIT(1) | BIT(2) | BIT(3))
++
++/*---------------------------------------------*/
++/* 3 The value of cut_msk: 8 bits
++ *---------------------------------------------*/
++#define	PWR_CUT_TESTCHIP_MSK	BIT(0)
++#define	PWR_CUT_A_MSK			BIT(1)
++#define	PWR_CUT_B_MSK			BIT(2)
++#define	PWR_CUT_C_MSK			BIT(3)
++#define	PWR_CUT_D_MSK			BIT(4)
++#define	PWR_CUT_E_MSK			BIT(5)
++#define	PWR_CUT_F_MSK			BIT(6)
++#define	PWR_CUT_G_MSK			BIT(7)
++#define	PWR_CUT_ALL_MSK			0xFF
++
++
++typedef enum _PWRSEQ_CMD_DELAY_UNIT_ {
++	PWRSEQ_DELAY_US,
++	PWRSEQ_DELAY_MS,
++} PWRSEQ_DELAY_UNIT;
++
++typedef struct _WL_PWR_CFG_ {
++	u16 offset;
++	u8 cut_msk;
++	u8 fab_msk:4;
++	u8 interface_msk:4;
++	u8 base:4;
++	u8 cmd:4;
++	u8 msk;
++	u8 value;
++} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
++
++
++#define GET_PWR_CFG_OFFSET(__PWR_CMD)		((__PWR_CMD).offset)
++#define GET_PWR_CFG_CUT_MASK(__PWR_CMD)		((__PWR_CMD).cut_msk)
++#define GET_PWR_CFG_FAB_MASK(__PWR_CMD)		((__PWR_CMD).fab_msk)
++#define GET_PWR_CFG_INTF_MASK(__PWR_CMD)	((__PWR_CMD).interface_msk)
++#define GET_PWR_CFG_BASE(__PWR_CMD)			((__PWR_CMD).base)
++#define GET_PWR_CFG_CMD(__PWR_CMD)			((__PWR_CMD).cmd)
++#define GET_PWR_CFG_MASK(__PWR_CMD)			((__PWR_CMD).msk)
++#define GET_PWR_CFG_VALUE(__PWR_CMD)		((__PWR_CMD).value)
++
++
++/* ********************************************************************************
++ *	Prototype of protected function.
++ * ******************************************************************************** */
++u8 HalPwrSeqCmdParsing(
++	PADAPTER		padapter,
++	u8				CutVersion,
++	u8				FabVersion,
++	u8				InterfaceType,
++	WLAN_PWR_CFG	PwrCfgCmd[]);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/HalVerDef.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/HalVerDef.h
+new file mode 100644
+index 000000000..4067119b6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/HalVerDef.h
+@@ -0,0 +1,207 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL_VERSION_DEF_H__
++#define __HAL_VERSION_DEF_H__
++
++#define TRUE	_TRUE
++#define FALSE	_FALSE
++
++/* HAL_IC_TYPE_E */
++typedef enum tag_HAL_IC_Type_Definition {
++	CHIP_8192S	=	0,
++	CHIP_8188C	=	1,
++	CHIP_8192C	=	2,
++	CHIP_8192D	=	3,
++	CHIP_8723A	=	4,
++	CHIP_8188E	=	5,
++	CHIP_8812	=	6,
++	CHIP_8821	=	7,
++	CHIP_8723B	=	8,
++	CHIP_8192E	=	9,
++	CHIP_8814A	=	10,
++	CHIP_8703B	=	11,
++	CHIP_8188F	=	12,
++	CHIP_8822B	=	13,
++	CHIP_8723D	=	14,
++	CHIP_8821C	=	15,
++	CHIP_8710B	=	16,
++	CHIP_8192F	=	17,
++	CHIP_8188GTV =	18,
++	CHIP_8822C	=	19,
++	CHIP_8814B	=	20,
++} HAL_IC_TYPE_E;
++
++/* HAL_CHIP_TYPE_E */
++typedef enum tag_HAL_CHIP_Type_Definition {
++	TEST_CHIP		=	0,
++	NORMAL_CHIP	=	1,
++	FPGA			=	2,
++} HAL_CHIP_TYPE_E;
++
++/* HAL_CUT_VERSION_E */
++typedef enum tag_HAL_Cut_Version_Definition {
++	A_CUT_VERSION		=	0,
++	B_CUT_VERSION		=	1,
++	C_CUT_VERSION		=	2,
++	D_CUT_VERSION		=	3,
++	E_CUT_VERSION		=	4,
++	F_CUT_VERSION		=	5,
++	G_CUT_VERSION		=	6,
++	H_CUT_VERSION		=	7,
++	I_CUT_VERSION		=	8,
++	J_CUT_VERSION		=	9,
++	K_CUT_VERSION		=	10,
++} HAL_CUT_VERSION_E;
++
++/* HAL_Manufacturer */
++typedef enum tag_HAL_Manufacturer_Version_Definition {
++	CHIP_VENDOR_TSMC	=	0,
++	CHIP_VENDOR_UMC	=	1,
++	CHIP_VENDOR_SMIC	=	2,
++} HAL_VENDOR_E;
++
++typedef enum tag_HAL_RF_Type_Definition {
++	RF_TYPE_1T1R	=	0,
++	RF_TYPE_1T2R	=	1,
++	RF_TYPE_2T2R	=	2,
++	RF_TYPE_2T3R	=	3,
++	RF_TYPE_2T4R	=	4,
++	RF_TYPE_3T3R	=	5,
++	RF_TYPE_3T4R	=	6,
++	RF_TYPE_4T4R	=	7,
++} HAL_RF_TYPE_E;
++
++typedef	struct tag_HAL_VERSION {
++	HAL_IC_TYPE_E		ICType;
++	HAL_CHIP_TYPE_E		ChipType;
++	HAL_CUT_VERSION_E	CUTVersion;
++	HAL_VENDOR_E		VendorType;
++	HAL_RF_TYPE_E		RFType;
++	u8					ROMVer;
++} HAL_VERSION, *PHAL_VERSION;
++
++/* VERSION_8192C			VersionID;
++ * HAL_VERSION			VersionID; */
++
++/* Get element */
++#define GET_CVID_IC_TYPE(version)			((HAL_IC_TYPE_E)(((HAL_VERSION)version).ICType))
++#define GET_CVID_CHIP_TYPE(version)			((HAL_CHIP_TYPE_E)(((HAL_VERSION)version).ChipType))
++#define GET_CVID_RF_TYPE(version)			((HAL_RF_TYPE_E)(((HAL_VERSION)version).RFType))
++#define GET_CVID_MANUFACTUER(version)		((HAL_VENDOR_E)(((HAL_VERSION)version).VendorType))
++#define GET_CVID_CUT_VERSION(version)		((HAL_CUT_VERSION_E)(((HAL_VERSION)version).CUTVersion))
++#define GET_CVID_ROM_VERSION(version)		((((HAL_VERSION)version).ROMVer) & ROM_VERSION_MASK)
++
++/* ----------------------------------------------------------------------------
++ * Common Macro. --
++ * ----------------------------------------------------------------------------
++ * HAL_VERSION VersionID */
++
++/* HAL_IC_TYPE_E */
++#if 0
++	#define IS_81XXC(version)				(((GET_CVID_IC_TYPE(version) == CHIP_8192C) || (GET_CVID_IC_TYPE(version) == CHIP_8188C)) ? TRUE : FALSE)
++	#define IS_8723_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8723A) ? TRUE : FALSE)
++	#define IS_92D(version)					((GET_CVID_IC_TYPE(version) == CHIP_8192D) ? TRUE : FALSE)
++#endif
++
++#define IS_8188E(version)					((GET_CVID_IC_TYPE(version) == CHIP_8188E) ? TRUE : FALSE)
++#define IS_8188F(version)					((GET_CVID_IC_TYPE(version) == CHIP_8188F) ? TRUE : FALSE)
++#define IS_8188GTV(version)					((GET_CVID_IC_TYPE(version) == CHIP_8188GTV) ? TRUE : FALSE)
++#define IS_8192E(version)					((GET_CVID_IC_TYPE(version) == CHIP_8192E) ? TRUE : FALSE)
++#define IS_8812_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8812) ? TRUE : FALSE)
++#define IS_8821_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8821) ? TRUE : FALSE)
++#define IS_8814A_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8814A) ? TRUE : FALSE)
++#define IS_8723B_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8723B) ? TRUE : FALSE)
++#define IS_8703B_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8703B) ? TRUE : FALSE)
++#define IS_8822B_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8822B) ? TRUE : FALSE)
++#define IS_8821C_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8821C) ? TRUE : FALSE)
++#define IS_8723D_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8723D) ? TRUE : FALSE)
++#define IS_8710B_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8710B) ? TRUE : FALSE)
++#define IS_8822C_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8822C) ? TRUE : FALSE)
++#define IS_8814B_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8814B) ? TRUE : FALSE)
++
++#define IS_8192F_SERIES(version)\
++	((GET_CVID_IC_TYPE(version) == CHIP_8192F) ? TRUE : FALSE)
++/* HAL_CHIP_TYPE_E */
++#define IS_TEST_CHIP(version)			((GET_CVID_CHIP_TYPE(version) == TEST_CHIP) ? TRUE : FALSE)
++#define IS_NORMAL_CHIP(version)			((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE)
++
++/* HAL_CUT_VERSION_E */
++#define IS_A_CUT(version)				((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? TRUE : FALSE)
++#define IS_B_CUT(version)				((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? TRUE : FALSE)
++#define IS_C_CUT(version)				((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? TRUE : FALSE)
++#define IS_D_CUT(version)				((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? TRUE : FALSE)
++#define IS_E_CUT(version)				((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE)
++#define IS_F_CUT(version)				((GET_CVID_CUT_VERSION(version) == F_CUT_VERSION) ? TRUE : FALSE)
++#define IS_I_CUT(version)				((GET_CVID_CUT_VERSION(version) == I_CUT_VERSION) ? TRUE : FALSE)
++#define IS_J_CUT(version)				((GET_CVID_CUT_VERSION(version) == J_CUT_VERSION) ? TRUE : FALSE)
++#define IS_K_CUT(version)				((GET_CVID_CUT_VERSION(version) == K_CUT_VERSION) ? TRUE : FALSE)
++
++/* HAL_VENDOR_E */
++#define IS_CHIP_VENDOR_TSMC(version)	((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC) ? TRUE : FALSE)
++#define IS_CHIP_VENDOR_UMC(version)	((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC) ? TRUE : FALSE)
++#define IS_CHIP_VENDOR_SMIC(version)	((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_SMIC) ? TRUE : FALSE)
++
++/* HAL_RF_TYPE_E */
++#define IS_1T1R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R) ? TRUE : FALSE)
++#define IS_1T2R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? TRUE : FALSE)
++#define IS_2T2R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? TRUE : FALSE)
++#define IS_2T3R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_2T3R) ? TRUE : FALSE)
++#define IS_2T4R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_2T4R) ? TRUE : FALSE)
++#define IS_3T3R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_3T3R) ? TRUE : FALSE)
++#define IS_3T4R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_3T4R) ? TRUE : FALSE)
++#define IS_4T4R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_4T4R) ? TRUE : FALSE)
++
++
++
++/* ----------------------------------------------------------------------------
++ * Chip version Macro. --
++ * ---------------------------------------------------------------------------- */
++#if 0
++	#define IS_81XXC_TEST_CHIP(version)		((IS_81XXC(version) && (!IS_NORMAL_CHIP(version))) ? TRUE : FALSE)
++
++	#define IS_92C_SERIAL(version)					((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE)
++	#define IS_81xxC_VENDOR_UMC_A_CUT(version)	(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
++	#define IS_81xxC_VENDOR_UMC_B_CUT(version)	(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
++	#define IS_81xxC_VENDOR_UMC_C_CUT(version)	(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
++
++	#define IS_NORMAL_CHIP92D(version)		((IS_92D(version)) ? ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE) : FALSE)
++
++	#define IS_92D_SINGLEPHY(version)		((IS_92D(version)) ? (IS_2T2R(version) ? TRUE : FALSE) : FALSE)
++	#define IS_92D_C_CUT(version)			((IS_92D(version)) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE)
++	#define IS_92D_D_CUT(version)			((IS_92D(version)) ? (IS_D_CUT(version) ? TRUE : FALSE) : FALSE)
++	#define IS_92D_E_CUT(version)			((IS_92D(version)) ? (IS_E_CUT(version) ? TRUE : FALSE) : FALSE)
++
++	#define IS_8723A_A_CUT(version)				((IS_8723_SERIES(version)) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE)
++	#define IS_8723A_B_CUT(version)				((IS_8723_SERIES(version)) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE)
++#endif
++#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter)		((IS_8188E(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE)
++#define IS_VENDOR_8812A_TEST_CHIP(_Adapter)		((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
++#define IS_VENDOR_8812A_MP_CHIP(_Adapter)		((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
++#define IS_VENDOR_8812A_C_CUT(_Adapter)			((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == C_CUT_VERSION) ? TRUE : FALSE) : FALSE)
++
++#define IS_VENDOR_8821A_TEST_CHIP(_Adapter)	((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
++#define IS_VENDOR_8821A_MP_CHIP(_Adapter)		((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
++
++#define IS_VENDOR_8192E_B_CUT(_Adapter)		((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == B_CUT_VERSION) ? TRUE : FALSE)
++
++#define IS_VENDOR_8723B_TEST_CHIP(_Adapter)	((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
++#define IS_VENDOR_8723B_MP_CHIP(_Adapter)		((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
++
++#define IS_VENDOR_8703B_TEST_CHIP(_Adapter)	((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
++#define IS_VENDOR_8703B_MP_CHIP(_Adapter)		((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
++#define IS_VENDOR_8814A_TEST_CHIP(_Adapter)	((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
++#define IS_VENDOR_8814A_MP_CHIP(_Adapter)		((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/autoconf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/autoconf.h
+new file mode 100644
+index 000000000..a19ee74f6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/autoconf.h
+@@ -0,0 +1,303 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*
++ * Public General Config
++ */
++#define AUTOCONF_INCLUDED
++
++#define RTL871X_MODULE_NAME "8723DS"
++#define DRV_NAME "rtl8723ds"
++
++#ifndef CONFIG_RTL8723D
++#define CONFIG_RTL8723D
++#endif
++#define CONFIG_SDIO_HCI
++
++#define PLATFORM_LINUX
++
++
++/*
++ * Wi-Fi Functions Config
++ */
++#define CONFIG_80211N_HT
++#define CONFIG_RECV_REORDERING_CTRL
++
++/* #define CONFIG_IOCTL_CFG80211 */		/* Set from Makefile */
++#ifdef CONFIG_IOCTL_CFG80211
++	/*
++	 * Indecate new sta asoc through cfg80211_new_sta
++	 * If kernel version >= 3.2 or
++	 * version < 3.2 but already apply cfg80211 patch,
++	 * RTW_USE_CFG80211_STA_EVENT must be defiend!
++	 */
++	/* #define RTW_USE_CFG80211_STA_EVENT */ /* Indecate new sta asoc through cfg80211_new_sta */
++	#ifndef CONFIG_PLATFORM_INTEL_BYT
++	#define CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
++	#endif /* !CONFIG_PLATFORM_INTEL_BYT */
++	/* #define CONFIG_DEBUG_CFG80211 */
++	#define CONFIG_SET_SCAN_DENY_TIMER
++#endif
++
++#define CONFIG_AP_MODE
++#ifdef CONFIG_AP_MODE
++	#define CONFIG_NATIVEAP_MLME
++	#ifndef CONFIG_NATIVEAP_MLME
++		#define CONFIG_HOSTAPD_MLME
++	#endif
++	/* #define CONFIG_FIND_BEST_CHANNEL */
++#endif
++
++#define CONFIG_P2P
++#ifdef CONFIG_P2P
++	/* Added by Albert 20110812
++	The CONFIG_WFD is for supporting the Wi-Fi display */
++	#define CONFIG_WFD
++
++	#define CONFIG_P2P_REMOVE_GROUP_INFO
++
++	/* #define CONFIG_DBG_P2P */
++	#define CONFIG_P2P_PS
++	#define CONFIG_P2P_OP_CHK_SOCIAL_CH
++	#define CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT  /* replace CONFIG_P2P_CHK_INVITE_CH_LIST flag */
++	/*#define CONFIG_P2P_INVITE_IOT*/
++#endif
++
++/* Added by Kurt 20110511 */
++#ifdef CONFIG_TDLS
++	#define CONFIG_TDLS_DRIVER_SETUP
++	/* #ifndef CONFIG_WFD
++		#define CONFIG_WFD
++	#endif */
++	/* #define CONFIG_TDLS_AUTOSETUP */
++	#define CONFIG_TDLS_AUTOCHECKALIVE
++	#define CONFIG_TDLS_CH_SW		/* Enable "CONFIG_TDLS_CH_SW" by default, however limit it to only work in wifi logo test mode but not in normal mode currently */
++#endif
++
++/* #define CONFIG_CONCURRENT_MODE */	/* Set from Makefile */
++#ifdef CONFIG_CONCURRENT_MODE
++	#define CONFIG_RUNTIME_PORT_SWITCH
++	#ifndef CONFIG_RUNTIME_PORT_SWITCH
++		#define CONFIG_TSF_RESET_OFFLOAD			/* For 2 PORT TSF SYNC. */
++	#endif
++	/* #define DBG_RUNTIME_PORT_SWITCH */
++#endif /* CONFIG_CONCURRENT_MODE */
++
++#define CONFIG_LAYER2_ROAMING
++#define CONFIG_LAYER2_ROAMING_RESUME
++
++/*
++ * Hareware/Firmware Related Config
++ */
++/* #define CONFIG_BT_COEXIST */	/* Set from Makefile */
++/* #define CONFIG_ANTENNA_DIVERSITY */
++/* #define SUPPORT_HW_RFOFF_DETECTED */
++
++/*#define CONFIG_RTW_LED*/
++#ifdef CONFIG_RTW_LED
++	/*#define CONFIG_RTW_SW_LED*/
++#endif /* CONFIG_RTW_LED */
++
++#define CONFIG_XMIT_ACK
++#ifdef CONFIG_XMIT_ACK
++	#define CONFIG_ACTIVE_KEEP_ALIVE_CHECK
++#endif
++
++#define CONFIG_RF_POWER_TRIM
++
++#define DISABLE_BB_RF	0
++
++#define RTW_NOTCH_FILTER 0 /* 0:Disable, 1:Enable, */
++
++
++/*
++ * Interface Related Config
++ */
++#define CONFIG_TX_AGGREGATION
++#define CONFIG_SDIO_RX_COPY
++#define CONFIG_XMIT_THREAD_MODE
++/* #define RTW_XMIT_THREAD_HIGH_PRIORITY */
++/* #define RTW_XMIT_THREAD_HIGH_PRIORITY_AGG */
++/* #define CONFIG_SDIO_TX_ENABLE_AVAL_INT */
++/* #define SDIO_FREE_XMIT_BUF_SEMA */
++#define CONFIG_RECV_THREAD_MODE
++#ifdef CONFIG_RECV_THREAD_MODE
++#define RTW_RECV_THREAD_HIGH_PRIORITY
++#endif/*CONFIG_RECV_THREAD_MODE*/
++
++/*
++ * Others
++ */
++/* #define CONFIG_MAC_LOOPBACK_DRIVER */
++
++#define CONFIG_SKB_COPY	/* for amsdu */
++
++#define CONFIG_NEW_SIGNAL_STAT_PROCESS
++
++#define CONFIG_EMBEDDED_FWIMG
++
++#ifdef CONFIG_EMBEDDED_FWIMG
++	#define	LOAD_FW_HEADER_FROM_DRIVER
++#endif
++/* #define CONFIG_FILE_FWIMG */
++/* download fw via tx packet or trafitional I/O*/
++/* #define CONFIG_DLFW_TXPKT */
++
++#define CONFIG_LONG_DELAY_ISSUE
++/* #define CONFIG_PATCH_JOIN_WRONG_CHANNEL */
++
++
++/*
++ * Auto Config Section
++ */
++#ifdef CONFIG_MAC_LOOPBACK_DRIVER
++#undef CONFIG_IOCTL_CFG80211
++#undef CONFIG_AP_MODE
++#undef CONFIG_NATIVEAP_MLME
++#undef CONFIG_POWER_SAVING
++#undef CONFIG_BT_COEXIST
++#undef CONFIG_ANTENNA_DIVERSITY
++#undef SUPPORT_HW_RFOFF_DETECTED
++#endif
++
++#ifdef CONFIG_MP_INCLUDED
++	#define MP_DRIVER	1
++	#define CONFIG_MP_IWPRIV_SUPPORT
++	/* disable unnecessary functions for MP */
++	/* #undef CONFIG_POWER_SAVING
++	#undef CONFIG_BT_COEXIST
++	#undef CONFIG_ANTENNA_DIVERSITY
++	#undef SUPPORT_HW_RFOFF_DETECTED */
++#else /* !CONFIG_MP_INCLUDED */
++	#define MP_DRIVER	0
++	#undef CONFIG_MP_IWPRIV_SUPPORT
++#endif /* !CONFIG_MP_INCLUDED */
++
++#ifdef CONFIG_POWER_SAVING
++	#define CONFIG_IPS
++	#define CONFIG_LPS
++
++	#if defined(CONFIG_LPS) && (defined(CONFIG_GSPI_HCI) || defined(CONFIG_SDIO_HCI))
++	#define CONFIG_LPS_LCLK
++	#endif
++
++	#ifdef CONFIG_LPS
++		#define CONFIG_CHECK_LEAVE_LPS
++		#ifndef CONFIG_PLATFORM_INTEL_BYT
++		#define CONFIG_LPS_SLOW_TRANSITION
++		#endif /* !CONFIG_PLATFORM_INTEL_BYT */
++	#endif
++
++	#ifdef CONFIG_LPS_LCLK
++	#define CONFIG_DETECT_CPWM_BY_POLLING
++	#define CONFIG_LPS_RPWM_TIMER
++	#if defined(CONFIG_LPS_RPWM_TIMER) || defined(CONFIG_DETECT_CPWM_BY_POLLING)
++	#define LPS_RPWM_WAIT_MS 300
++	#endif
++	#define CONFIG_LPS_LCLK_WD_TIMER /* Watch Dog timer in LPS LCLK */
++	#endif
++
++	#ifdef CONFIG_IPS
++	#define CONFIG_IPS_CHECK_IN_WD /* Do IPS Check in WatchDog. */
++	/* #define CONFIG_SWLPS_IN_IPS */ /* Do SW LPS flow when entering and leaving IPS */
++	/* #define CONFIG_FWLPS_IN_IPS */ /* issue H2C command to let FW do LPS when entering IPS */
++	#endif
++#endif /* CONFIG_POWER_SAVING */
++
++#ifdef CONFIG_BT_COEXIST
++	/* for ODM and outsrc BT-Coex */
++	#ifndef CONFIG_LPS
++		#define CONFIG_LPS	/* download reserved page to FW */
++	#endif
++#endif /* !CONFIG_BT_COEXIST */
++
++#ifdef CONFIG_WOWLAN
++	#define CONFIG_GTK_OL
++	/* #define CONFIG_ARP_KEEP_ALIVE */
++#endif /* CONFIG_WOWLAN */
++
++#ifdef CONFIG_GPIO_WAKEUP
++	#ifndef WAKEUP_GPIO_IDX
++		#define WAKEUP_GPIO_IDX	6	/* WIFI Chip Side */
++	#endif /* !WAKEUP_GPIO_IDX */
++#endif /* CONFIG_GPIO_WAKEUP */
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++#define CONFIG_HW_ANTENNA_DIVERSITY
++#endif
++
++#if (CONFIG_RTW_ADAPTIVITY_EN == 1)
++	#define CONFIG_RTW_ADAPTIVITY_TH_L2H_INI 0xf3
++#endif
++
++#ifdef CONFIG_RTW_NAPI
++/*#define CONFIG_RTW_NAPI_DYNAMIC*/
++#define CONFIG_RTW_NAPI_V2
++#endif
++
++/*
++ * Platform dependent
++ */
++#ifdef CONFIG_PLATFORM_SPRD
++
++#undef CONFIG_SDIO_RX_COPY
++
++#ifdef ANDROID_2X
++
++#define CONFIG_SDIO_RX_COPY
++
++#else /*  !ANDROID_2X */
++	#undef CONFIG_WOWLAN
++	#undef CONFIG_WOWLAN_8723
++	/* #define CONFIG_SDIO_RX_COPY */
++	/* #define CONFIG_LINKED_LCOK */
++	#define CONFIG_AUTH_DIRECT_WITHOUT_BCN
++	/* #define CONFIG_DISCONNECT_H2CWAY */
++	/* #define CONFIG_DONT_CARE_TP */
++	#define CONFIG_LOW_PWR_LPS
++	/* #define CONFIG_CMCC_TEST */
++
++	/* 1) LPS unit is only 102 ms, it's not
++	a good idear to retry it use timer,
++	2) we must wait ACK, or lots of IO
++	is not allowed under 32k, because
++	this will cause hw hang */
++	#undef CONFIG_LPS_RPWM_TIMER
++	#define CONFIG_WAIT_PS_ACK
++	#define CONFIG_SOFTAP_11N
++	#define CONFIG_CHECK_BT_HANG
++
++	/* #define CONFIG_8703BS_TEST */
++#endif /* !ANDROID_2X */
++
++#endif /* CONFIG_PLATFORM_SPRD */
++
++
++/*
++ * Debug Related Config
++ */
++#define CONFIG_DEBUG
++
++#ifdef CONFIG_DEBUG
++#define DBG	1	/* for ODM & BTCOEX debug */
++#else /* !CONFIG_DEBUG */
++#define DBG	0	/* for ODM & BTCOEX debug */
++#endif /* !CONFIG_DEBUG */
++
++#define DBG_CONFIG_ERROR_DETECT
++/* #define DBG_XMIT_BUF */
++/* #define DBG_XMIT_BUF_EXT */
++#define DBG_CHECK_FW_PS_STATE
++/* #define DBG_CHECK_FW_PS_STATE_H2C */
++/* #define CONFIG_FW_C2H_DEBUG */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/basic_types.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/basic_types.h
+new file mode 100644
+index 000000000..45e513156
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/basic_types.h
+@@ -0,0 +1,357 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __BASIC_TYPES_H__
++#define __BASIC_TYPES_H__
++
++
++#define SUCCESS	0
++#define FAIL	(-1)
++
++#ifndef TRUE
++	#define _TRUE	1
++#else
++	#define _TRUE	TRUE
++#endif
++
++#ifndef FALSE
++	#define _FALSE	0
++#else
++	#define _FALSE	FALSE
++#endif
++
++#ifdef PLATFORM_WINDOWS
++
++	typedef signed char s8;
++	typedef unsigned char u8;
++
++	typedef signed short s16;
++	typedef unsigned short u16;
++
++	typedef signed long s32;
++	typedef unsigned long u32;
++
++	typedef unsigned int	uint;
++	typedef	signed int		sint;
++
++
++	typedef signed long long s64;
++	typedef unsigned long long u64;
++
++	#ifdef NDIS50_MINIPORT
++
++		#define NDIS_MAJOR_VERSION       5
++		#define NDIS_MINOR_VERSION       0
++
++	#endif
++
++	#ifdef NDIS51_MINIPORT
++
++		#define NDIS_MAJOR_VERSION       5
++		#define NDIS_MINOR_VERSION       1
++
++	#endif
++
++	typedef NDIS_PROC proc_t;
++
++	typedef LONG atomic_t;
++
++#endif
++
++
++#ifdef PLATFORM_LINUX
++	#include <linux/version.h>
++	#include <linux/types.h>
++	#include <linux/module.h>
++	#include <linux/kernel.h>
++	#include <linux/init.h>
++	#include <linux/utsname.h>
++
++	typedef	signed int sint;
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19))
++typedef _Bool bool;
++
++enum {
++	false	= 0,
++	true	= 1
++};
++#endif
++
++	typedef void (*proc_t)(void *);
++
++	typedef	__kernel_size_t	SIZE_T;
++	typedef	__kernel_ssize_t	SSIZE_T;
++	#define FIELD_OFFSET(s, field)	((SSIZE_T)&((s *)(0))->field)
++
++#define NDIS_OID uint
++#endif /*PLATFORM_LINUX*/
++
++
++#ifdef PLATFORM_FREEBSD
++
++	typedef signed char s8;
++	typedef unsigned char u8;
++
++	typedef signed short s16;
++	typedef unsigned short u16;
++
++	typedef signed int s32;
++	typedef unsigned int u32;
++
++	typedef unsigned int	uint;
++	typedef	signed int		sint;
++	typedef long atomic_t;
++
++	typedef signed long long s64;
++	typedef unsigned long long u64;
++
++	typedef u32 dma_addr_t;
++
++	typedef void (*proc_t)(void *);
++
++	typedef unsigned int __kernel_size_t;
++	typedef int __kernel_ssize_t;
++
++	typedef	__kernel_size_t	SIZE_T;
++	typedef	__kernel_ssize_t	SSIZE_T;
++	#define FIELD_OFFSET(s, field)	((SSIZE_T)&((s *)(0))->field)
++
++#endif
++
++#define MEM_ALIGNMENT_OFFSET	(sizeof (SIZE_T))
++#define MEM_ALIGNMENT_PADDING	(sizeof(SIZE_T) - 1)
++
++#define SIZE_PTR SIZE_T
++#define SSIZE_PTR SSIZE_T
++
++/*
++* Continuous bits starting from least significant bit
++* Example:
++* BIT_LEN_MASK_32(0) => 0x00000000
++* BIT_LEN_MASK_32(1) => 0x00000001
++* BIT_LEN_MASK_32(2) => 0x00000003
++* BIT_LEN_MASK_32(32) => 0xFFFFFFFF
++*/
++#define BIT_LEN_MASK_32(__BitLen) ((u32)(0xFFFFFFFF >> (32 - (__BitLen))))
++#define BIT_LEN_MASK_16(__BitLen) ((u16)(0xFFFF >> (16 - (__BitLen))))
++#define BIT_LEN_MASK_8(__BitLen) ((u8)(0xFF >> (8 - (__BitLen))))
++
++/*
++* Continuous bits starting from least significant bit
++* Example:
++* BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
++* BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
++*/
++#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ((u32)(BIT_LEN_MASK_32(__BitLen) << (__BitOffset)))
++#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ((u16)(BIT_LEN_MASK_16(__BitLen) << (__BitOffset)))
++#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ((u8)(BIT_LEN_MASK_8(__BitLen) << (__BitOffset)))
++
++/*
++* Convert LE data to host byte order
++*/
++#define EF1Byte (u8)
++#define EF2Byte le16_to_cpu
++#define EF4Byte le32_to_cpu
++
++/*
++* Read LE data from memory to host byte order
++*/
++#define ReadLE4Byte(_ptr)	le32_to_cpu(*((u32 *)(_ptr)))
++#define ReadLE2Byte(_ptr)	le16_to_cpu(*((u16 *)(_ptr)))
++#define ReadLE1Byte(_ptr)	(*((u8 *)(_ptr)))
++
++/*
++* Read BE data from memory to host byte order
++*/
++#define ReadBEE4Byte(_ptr)	be32_to_cpu(*((u32 *)(_ptr)))
++#define ReadBE2Byte(_ptr)	be16_to_cpu(*((u16 *)(_ptr)))
++#define ReadBE1Byte(_ptr)	(*((u8 *)(_ptr)))
++
++/*
++* Write host byte order data to memory in LE order
++*/
++#define WriteLE4Byte(_ptr, _val)	((*((u32 *)(_ptr))) = cpu_to_le32(_val))
++#define WriteLE2Byte(_ptr, _val)	((*((u16 *)(_ptr))) = cpu_to_le16(_val))
++#define WriteLE1Byte(_ptr, _val)	((*((u8 *)(_ptr))) = ((u8)(_val)))
++
++/*
++* Write host byte order data to memory in BE order
++*/
++#define WriteBE4Byte(_ptr, _val)	((*((u32 *)(_ptr))) = cpu_to_be32(_val))
++#define WriteBE2Byte(_ptr, _val)	((*((u16 *)(_ptr))) = cpu_to_be16(_val))
++#define WriteBE1Byte(_ptr, _val)	((*((u8 *)(_ptr))) = ((u8)(_val)))
++
++/*
++* Return 4-byte value in host byte ordering from 4-byte pointer in litten-endian system.
++*/
++#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) (le32_to_cpu(*((u32 *)(__pStart))))
++#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) (le16_to_cpu(*((u16 *)(__pStart))))
++#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) ((*((u8 *)(__pStart))))
++
++/*
++* Return 4-byte value in host byte ordering from 4-byte pointer in big-endian system.
++*/
++#define BE_P4BYTE_TO_HOST_4BYTE(__pStart) (be32_to_cpu(*((u32 *)(__pStart))))
++#define BE_P2BYTE_TO_HOST_2BYTE(__pStart) (be16_to_cpu(*((u16 *)(__pStart))))
++#define BE_P1BYTE_TO_HOST_1BYTE(__pStart) ((*((u8 *)(__pStart))))
++
++/*
++* Translate subfield (continuous bits in little-endian) of 4-byte value in LE byte to
++* 4-byte value in host byte ordering.
++*/
++#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
++	((LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_32(__BitLen))
++
++#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
++	((LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_16(__BitLen))
++
++#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
++	((LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_8(__BitLen))
++
++/*
++* Translate subfield (continuous bits in big-endian) of 4-byte value in BE byte to
++* 4-byte value in host byte ordering.
++*/
++#define BE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
++	((BE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_32(__BitLen))
++
++#define BE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
++	((BE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_16(__BitLen))
++
++#define BE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
++	((BE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_8(__BitLen))
++
++/*
++* Mask subfield (continuous bits in little-endian) of 4-byte value in LE byte oredering
++* and return the result in 4-byte value in host byte ordering.
++*/
++#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
++	(LE_P4BYTE_TO_HOST_4BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)))
++
++#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
++	(LE_P2BYTE_TO_HOST_2BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen)))
++
++#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
++	(LE_P1BYTE_TO_HOST_1BYTE(__pStart) & ((u8)(~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen))))
++
++/*
++* Mask subfield (continuous bits in big-endian) of 4-byte value in BE byte oredering
++* and return the result in 4-byte value in host byte ordering.
++*/
++#define BE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
++	(BE_P4BYTE_TO_HOST_4BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)))
++
++#define BE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
++	(BE_P2BYTE_TO_HOST_2BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen)))
++
++#define BE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
++	(BE_P1BYTE_TO_HOST_1BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen)))
++
++/*
++* Set subfield of little-endian 4-byte value to specified value.
++*/
++#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
++	do { \
++		if (__BitOffset == 0 && __BitLen == 32) \
++			WriteLE4Byte(__pStart, __Value); \
++		else { \
++			WriteLE4Byte(__pStart, \
++				LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
++				| \
++				((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \
++			); \
++		} \
++	} while (0)
++
++#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
++	do { \
++		if (__BitOffset == 0 && __BitLen == 16) \
++			WriteLE2Byte(__pStart, __Value); \
++		else { \
++			WriteLE2Byte(__pStart, \
++				LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
++				| \
++				((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \
++			); \
++		} \
++	} while (0)
++
++#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \
++	do { \
++		if (__BitOffset == 0 && __BitLen == 8) \
++			WriteLE1Byte(__pStart, __Value); \
++		else { \
++			WriteLE1Byte(__pStart, \
++				LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
++				| \
++				((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \
++			); \
++		} \
++	} while (0)
++
++/*
++* Set subfield of big-endian 4-byte value to specified value.
++*/
++#define SET_BITS_TO_BE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
++	do { \
++		if (__BitOffset == 0 && __BitLen == 32) \
++			WriteBE4Byte(__pStart, __Value); \
++		else { \
++			WriteBE4Byte(__pStart, \
++				BE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
++				| \
++				((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \
++			); \
++		} \
++	} while (0)
++
++#define SET_BITS_TO_BE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
++	do { \
++		if (__BitOffset == 0 && __BitLen == 16) \
++			WriteBE2Byte(__pStart, __Value); \
++		else { \
++			WriteBE2Byte(__pStart, \
++				BE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
++				| \
++				((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \
++			); \
++		} \
++	} while (0)
++
++#define SET_BITS_TO_BE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \
++	do { \
++		if (__BitOffset == 0 && __BitLen == 8) \
++			WriteBE1Byte(__pStart, __Value); \
++		else { \
++			WriteBE1Byte(__pStart, \
++				BE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
++				| \
++				((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \
++			); \
++		} \
++	} while (0)
++
++/* Get the N-bytes aligment offset from the current length */
++#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment))
++
++typedef unsigned char	BOOLEAN, *PBOOLEAN, boolean;
++
++#define TEST_FLAG(__Flag, __testFlag)		(((__Flag) & (__testFlag)) != 0)
++#define SET_FLAG(__Flag, __setFlag)			((__Flag) |= __setFlag)
++#define CLEAR_FLAG(__Flag, __clearFlag)		((__Flag) &= ~(__clearFlag))
++#define CLEAR_FLAGS(__Flag)					((__Flag) = 0)
++#define TEST_FLAGS(__Flag, __testFlags)		(((__Flag) & (__testFlags)) == (__testFlags))
++
++#endif /* __BASIC_TYPES_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/byteorder/big_endian.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/byteorder/big_endian.h
+new file mode 100644
+index 000000000..6b1dc449e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/byteorder/big_endian.h
+@@ -0,0 +1,82 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H
++#define _LINUX_BYTEORDER_BIG_ENDIAN_H
++
++#ifndef __BIG_ENDIAN
++	#define __BIG_ENDIAN 4321
++#endif
++#ifndef __BIG_ENDIAN_BITFIELD
++	#define __BIG_ENDIAN_BITFIELD
++#endif
++
++#include <byteorder/swab.h>
++
++#define __constant_htonl(x) ((__u32)(x))
++#define __constant_ntohl(x) ((__u32)(x))
++#define __constant_htons(x) ((__u16)(x))
++#define __constant_ntohs(x) ((__u16)(x))
++#define __constant_cpu_to_le64(x) ___constant_swab64((x))
++#define __constant_le64_to_cpu(x) ___constant_swab64((x))
++#define __constant_cpu_to_le32(x) ___constant_swab32((x))
++#define __constant_le32_to_cpu(x) ___constant_swab32((x))
++#define __constant_cpu_to_le16(x) ___constant_swab16((x))
++#define __constant_le16_to_cpu(x) ___constant_swab16((x))
++#define __constant_cpu_to_be64(x) ((__u64)(x))
++#define __constant_be64_to_cpu(x) ((__u64)(x))
++#define __constant_cpu_to_be32(x) ((__u32)(x))
++#define __constant_be32_to_cpu(x) ((__u32)(x))
++#define __constant_cpu_to_be16(x) ((__u16)(x))
++#define __constant_be16_to_cpu(x) ((__u16)(x))
++#define __cpu_to_le64(x) __swab64((x))
++#define __le64_to_cpu(x) __swab64((x))
++#define __cpu_to_le32(x) __swab32((x))
++#define __le32_to_cpu(x) __swab32((x))
++#define __cpu_to_le16(x) __swab16((x))
++#define __le16_to_cpu(x) __swab16((x))
++#define __cpu_to_be64(x) ((__u64)(x))
++#define __be64_to_cpu(x) ((__u64)(x))
++#define __cpu_to_be32(x) ((__u32)(x))
++#define __be32_to_cpu(x) ((__u32)(x))
++#define __cpu_to_be16(x) ((__u16)(x))
++#define __be16_to_cpu(x) ((__u16)(x))
++#define __cpu_to_le64p(x) __swab64p((x))
++#define __le64_to_cpup(x) __swab64p((x))
++#define __cpu_to_le32p(x) __swab32p((x))
++#define __le32_to_cpup(x) __swab32p((x))
++#define __cpu_to_le16p(x) __swab16p((x))
++#define __le16_to_cpup(x) __swab16p((x))
++#define __cpu_to_be64p(x) (*(__u64 *)(x))
++#define __be64_to_cpup(x) (*(__u64 *)(x))
++#define __cpu_to_be32p(x) (*(__u32 *)(x))
++#define __be32_to_cpup(x) (*(__u32 *)(x))
++#define __cpu_to_be16p(x) (*(__u16 *)(x))
++#define __be16_to_cpup(x) (*(__u16 *)(x))
++#define __cpu_to_le64s(x) __swab64s((x))
++#define __le64_to_cpus(x) __swab64s((x))
++#define __cpu_to_le32s(x) __swab32s((x))
++#define __le32_to_cpus(x) __swab32s((x))
++#define __cpu_to_le16s(x) __swab16s((x))
++#define __le16_to_cpus(x) __swab16s((x))
++#define __cpu_to_be64s(x) do {} while (0)
++#define __be64_to_cpus(x) do {} while (0)
++#define __cpu_to_be32s(x) do {} while (0)
++#define __be32_to_cpus(x) do {} while (0)
++#define __cpu_to_be16s(x) do {} while (0)
++#define __be16_to_cpus(x) do {} while (0)
++
++#include <byteorder/generic.h>
++
++#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/byteorder/generic.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/byteorder/generic.h
+new file mode 100644
+index 000000000..f85114bf7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/byteorder/generic.h
+@@ -0,0 +1,207 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _LINUX_BYTEORDER_GENERIC_H
++#define _LINUX_BYTEORDER_GENERIC_H
++
++/*
++ * linux/byteorder_generic.h
++ * Generic Byte-reordering support
++ *
++ * Francois-Rene Rideau <fare@tunes.org> 19970707
++ *    gathered all the good ideas from all asm-foo/byteorder.h into one file,
++ *    cleaned them up.
++ *    I hope it is compliant with non-GCC compilers.
++ *    I decided to put __BYTEORDER_HAS_U64__ in byteorder.h,
++ *    because I wasn't sure it would be ok to put it in types.h
++ *    Upgraded it to 2.1.43
++ * Francois-Rene Rideau <fare@tunes.org> 19971012
++ *    Upgraded it to 2.1.57
++ *    to please Linus T., replaced huge #ifdef's between little/big endian
++ *    by nestedly #include'd files.
++ * Francois-Rene Rideau <fare@tunes.org> 19971205
++ *    Made it to 2.1.71; now a facelift:
++ *    Put files under include/linux/byteorder/
++ *    Split swab from generic support.
++ *
++ * TODO:
++ *   = Regular kernel maintainers could also replace all these manual
++ *    byteswap macros that remain, disseminated among drivers,
++ *    after some grep or the sources...
++ *   = Linus might want to rename all these macros and files to fit his taste,
++ *    to fit his personal naming scheme.
++ *   = it seems that a few drivers would also appreciate
++ *    nybble swapping support...
++ *   = every architecture could add their byteswap macro in asm/byteorder.h
++ *    see how some architectures already do (i386, alpha, ppc, etc)
++ *   = cpu_to_beXX and beXX_to_cpu might some day need to be well
++ *    distinguished throughout the kernel. This is not the case currently,
++ *    since little endian, big endian, and pdp endian machines needn't it.
++ *    But this might be the case for, say, a port of Linux to 20/21 bit
++ *    architectures (and F21 Linux addict around?).
++ */
++
++/*
++ * The following macros are to be defined by <asm/byteorder.h>:
++ *
++ * Conversion of long and short int between network and host format
++ *	ntohl(__u32 x)
++ *	ntohs(__u16 x)
++ *	htonl(__u32 x)
++ *	htons(__u16 x)
++ * It seems that some programs (which? where? or perhaps a standard? POSIX?)
++ * might like the above to be functions, not macros (why?).
++ * if that's true, then detect them, and take measures.
++ * Anyway, the measure is: define only ___ntohl as a macro instead,
++ * and in a separate file, have
++ * unsigned long inline ntohl(x){return ___ntohl(x);}
++ *
++ * The same for constant arguments
++ *	__constant_ntohl(__u32 x)
++ *	__constant_ntohs(__u16 x)
++ *	__constant_htonl(__u32 x)
++ *	__constant_htons(__u16 x)
++ *
++ * Conversion of XX-bit integers (16- 32- or 64-)
++ * between native CPU format and little/big endian format
++ * 64-bit stuff only defined for proper architectures
++ *	cpu_to_[bl]eXX(__uXX x)
++ *	[bl]eXX_to_cpu(__uXX x)
++ *
++ * The same, but takes a pointer to the value to convert
++ *	cpu_to_[bl]eXXp(__uXX x)
++ *	[bl]eXX_to_cpup(__uXX x)
++ *
++ * The same, but change in situ
++ *	cpu_to_[bl]eXXs(__uXX x)
++ *	[bl]eXX_to_cpus(__uXX x)
++ *
++ * See asm-foo/byteorder.h for examples of how to provide
++ * architecture-optimized versions
++ *
++ */
++
++
++#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS) || defined(PLATFORM_MPIXEL) || defined(PLATFORM_FREEBSD)
++	/*
++	* inside the kernel, we can use nicknames;
++	* outside of it, we must avoid POSIX namespace pollution...
++	*/
++	#define cpu_to_le64 __cpu_to_le64
++	#define le64_to_cpu __le64_to_cpu
++	#define cpu_to_le32 __cpu_to_le32
++	#define le32_to_cpu __le32_to_cpu
++	#define cpu_to_le16 __cpu_to_le16
++	#define le16_to_cpu __le16_to_cpu
++	#define cpu_to_be64 __cpu_to_be64
++	#define be64_to_cpu __be64_to_cpu
++	#define cpu_to_be32 __cpu_to_be32
++	#define be32_to_cpu __be32_to_cpu
++	#define cpu_to_be16 __cpu_to_be16
++	#define be16_to_cpu __be16_to_cpu
++	#define cpu_to_le64p __cpu_to_le64p
++	#define le64_to_cpup __le64_to_cpup
++	#define cpu_to_le32p __cpu_to_le32p
++	#define le32_to_cpup __le32_to_cpup
++	#define cpu_to_le16p __cpu_to_le16p
++	#define le16_to_cpup __le16_to_cpup
++	#define cpu_to_be64p __cpu_to_be64p
++	#define be64_to_cpup __be64_to_cpup
++	#define cpu_to_be32p __cpu_to_be32p
++	#define be32_to_cpup __be32_to_cpup
++	#define cpu_to_be16p __cpu_to_be16p
++	#define be16_to_cpup __be16_to_cpup
++	#define cpu_to_le64s __cpu_to_le64s
++	#define le64_to_cpus __le64_to_cpus
++	#define cpu_to_le32s __cpu_to_le32s
++	#define le32_to_cpus __le32_to_cpus
++	#define cpu_to_le16s __cpu_to_le16s
++	#define le16_to_cpus __le16_to_cpus
++	#define cpu_to_be64s __cpu_to_be64s
++	#define be64_to_cpus __be64_to_cpus
++	#define cpu_to_be32s __cpu_to_be32s
++	#define be32_to_cpus __be32_to_cpus
++	#define cpu_to_be16s __cpu_to_be16s
++	#define be16_to_cpus __be16_to_cpus
++#endif
++
++
++/*
++ * Handle ntohl and suches. These have various compatibility
++ * issues - like we want to give the prototype even though we
++ * also have a macro for them in case some strange program
++ * wants to take the address of the thing or something..
++ *
++ * Note that these used to return a "long" in libc5, even though
++ * long is often 64-bit these days.. Thus the casts.
++ *
++ * They have to be macros in order to do the constant folding
++ * correctly - if the argument passed into a inline function
++ * it is no longer constant according to gcc..
++ */
++
++#undef ntohl
++#undef ntohs
++#undef htonl
++#undef htons
++
++/*
++ * Do the prototypes. Somebody might want to take the
++ * address or some such sick thing..
++ */
++#if defined(PLATFORM_LINUX) || (defined(__GLIBC__) && __GLIBC__ >= 2)
++	extern __u32			ntohl(__u32);
++	extern __u32			htonl(__u32);
++#else /* defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2) */
++	#ifndef PLATFORM_FREEBSD
++		extern unsigned long int	ntohl(unsigned long int);
++		extern unsigned long int	htonl(unsigned long int);
++	#endif
++#endif
++#ifndef PLATFORM_FREEBSD
++	extern unsigned short int	ntohs(unsigned short int);
++	extern unsigned short int	htons(unsigned short int);
++#endif
++
++#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) || defined(PLATFORM_MPIXEL)
++
++	#define ___htonl(x) __cpu_to_be32(x)
++	#define ___htons(x) __cpu_to_be16(x)
++	#define ___ntohl(x) __be32_to_cpu(x)
++	#define ___ntohs(x) __be16_to_cpu(x)
++
++	#if defined(PLATFORM_LINUX) || (defined(__GLIBC__) && __GLIBC__ >= 2)
++		#define htonl(x) ___htonl(x)
++		#define ntohl(x) ___ntohl(x)
++	#else
++		#define htonl(x) ((unsigned long)___htonl(x))
++		#define ntohl(x) ((unsigned long)___ntohl(x))
++	#endif
++	#define htons(x) ___htons(x)
++	#define ntohs(x) ___ntohs(x)
++
++#endif /* OPTIMIZE */
++
++
++#if defined(PLATFORM_WINDOWS)
++
++	#define htonl(x) __cpu_to_be32(x)
++	#define ntohl(x) __be32_to_cpu(x)
++	#define htons(x) __cpu_to_be16(x)
++	#define ntohs(x) __be16_to_cpu(x)
++
++
++#endif
++
++#endif /* _LINUX_BYTEORDER_GENERIC_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/byteorder/little_endian.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/byteorder/little_endian.h
+new file mode 100644
+index 000000000..c4b64512f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/byteorder/little_endian.h
+@@ -0,0 +1,84 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H
++#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H
++
++#ifndef __LITTLE_ENDIAN
++	#define __LITTLE_ENDIAN 1234
++#endif
++#ifndef __LITTLE_ENDIAN_BITFIELD
++	#define __LITTLE_ENDIAN_BITFIELD
++#endif
++
++#include <byteorder/swab.h>
++
++#ifndef __constant_htonl
++	#define __constant_htonl(x) ___constant_swab32((x))
++	#define __constant_ntohl(x) ___constant_swab32((x))
++	#define __constant_htons(x) ___constant_swab16((x))
++	#define __constant_ntohs(x) ___constant_swab16((x))
++	#define __constant_cpu_to_le64(x) ((__u64)(x))
++	#define __constant_le64_to_cpu(x) ((__u64)(x))
++	#define __constant_cpu_to_le32(x) ((__u32)(x))
++	#define __constant_le32_to_cpu(x) ((__u32)(x))
++	#define __constant_cpu_to_le16(x) ((__u16)(x))
++	#define __constant_le16_to_cpu(x) ((__u16)(x))
++	#define __constant_cpu_to_be64(x) ___constant_swab64((x))
++	#define __constant_be64_to_cpu(x) ___constant_swab64((x))
++	#define __constant_cpu_to_be32(x) ___constant_swab32((x))
++	#define __constant_be32_to_cpu(x) ___constant_swab32((x))
++	#define __constant_cpu_to_be16(x) ___constant_swab16((x))
++	#define __constant_be16_to_cpu(x) ___constant_swab16((x))
++	#define __cpu_to_le64(x) ((__u64)(x))
++	#define __le64_to_cpu(x) ((__u64)(x))
++	#define __cpu_to_le32(x) ((__u32)(x))
++	#define __le32_to_cpu(x) ((__u32)(x))
++	#define __cpu_to_le16(x) ((__u16)(x))
++	#define __le16_to_cpu(x) ((__u16)(x))
++	#define __cpu_to_be64(x) __swab64((x))
++	#define __be64_to_cpu(x) __swab64((x))
++	#define __cpu_to_be32(x) __swab32((x))
++	#define __be32_to_cpu(x) __swab32((x))
++	#define __cpu_to_be16(x) __swab16((x))
++	#define __be16_to_cpu(x) __swab16((x))
++	#define __cpu_to_le64p(x) (*(__u64 *)(x))
++	#define __le64_to_cpup(x) (*(__u64 *)(x))
++	#define __cpu_to_le32p(x) (*(__u32 *)(x))
++	#define __le32_to_cpup(x) (*(__u32 *)(x))
++	#define __cpu_to_le16p(x) (*(__u16 *)(x))
++	#define __le16_to_cpup(x) (*(__u16 *)(x))
++	#define __cpu_to_be64p(x) __swab64p((x))
++	#define __be64_to_cpup(x) __swab64p((x))
++	#define __cpu_to_be32p(x) __swab32p((x))
++	#define __be32_to_cpup(x) __swab32p((x))
++	#define __cpu_to_be16p(x) __swab16p((x))
++	#define __be16_to_cpup(x) __swab16p((x))
++	#define __cpu_to_le64s(x) do {} while (0)
++	#define __le64_to_cpus(x) do {} while (0)
++	#define __cpu_to_le32s(x) do {} while (0)
++	#define __le32_to_cpus(x) do {} while (0)
++	#define __cpu_to_le16s(x) do {} while (0)
++	#define __le16_to_cpus(x) do {} while (0)
++	#define __cpu_to_be64s(x) __swab64s((x))
++	#define __be64_to_cpus(x) __swab64s((x))
++	#define __cpu_to_be32s(x) __swab32s((x))
++	#define __be32_to_cpus(x) __swab32s((x))
++	#define __cpu_to_be16s(x) __swab16s((x))
++	#define __be16_to_cpus(x) __swab16s((x))
++#endif /* __constant_htonl */
++
++#include <byteorder/generic.h>
++
++#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/byteorder/swab.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/byteorder/swab.h
+new file mode 100644
+index 000000000..a8dd46bd3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/byteorder/swab.h
+@@ -0,0 +1,136 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _LINUX_BYTEORDER_SWAB_H
++#define _LINUX_BYTEORDER_SWAB_H
++
++#if !defined(CONFIG_PLATFORM_MSTAR)
++#ifndef __u16
++	typedef unsigned short __u16;
++#endif
++
++#ifndef __u32
++	typedef unsigned int	__u32;
++#endif
++
++#ifndef __u8
++	typedef unsigned char __u8;
++#endif
++
++#ifndef __u64
++	typedef unsigned long long	__u64;
++#endif
++
++
++__inline static __u16  ___swab16(__u16 x)
++{
++	__u16 __x = x;
++	return
++		 (__u16)(
++			 (((__u16)(__x)&(__u16)0x00ffU) << 8) |
++			 (((__u16)(__x)&(__u16)0xff00U) >> 8));
++
++}
++
++__inline static __u32  ___swab32(__u32 x)
++{
++	__u32 __x = (x);
++	return  (__u32)(
++			(((__u32)(__x)&(__u32)0x000000ffUL) << 24) |
++			(((__u32)(__x)&(__u32)0x0000ff00UL) <<  8) |
++			(((__u32)(__x)&(__u32)0x00ff0000UL) >>  8) |
++			(((__u32)(__x)&(__u32)0xff000000UL) >> 24));
++}
++
++__inline static __u64  ___swab64(__u64 x)
++{
++	__u64 __x = (x);
++
++	return
++		 (__u64)(\
++		 (__u64)(((__u64)(__x)&(__u64)0x00000000000000ffULL) << 56) | \
++		 (__u64)(((__u64)(__x)&(__u64)0x000000000000ff00ULL) << 40) | \
++		 (__u64)(((__u64)(__x)&(__u64)0x0000000000ff0000ULL) << 24) | \
++		 (__u64)(((__u64)(__x)&(__u64)0x00000000ff000000ULL) <<  8) | \
++		 (__u64)(((__u64)(__x)&(__u64)0x000000ff00000000ULL) >>  8) | \
++		 (__u64)(((__u64)(__x)&(__u64)0x0000ff0000000000ULL) >> 24) | \
++		 (__u64)(((__u64)(__x)&(__u64)0x00ff000000000000ULL) >> 40) | \
++		 (__u64)(((__u64)(__x)&(__u64)0xff00000000000000ULL) >> 56));
++	\
++}
++#endif /* CONFIG_PLATFORM_MSTAR */
++
++#ifndef __arch__swab16
++__inline static __u16 __arch__swab16(__u16 x)
++{
++	return ___swab16(x);
++}
++
++#endif
++
++#ifndef __arch__swab32
++__inline static __u32 __arch__swab32(__u32 x)
++{
++	__u32 __tmp = (x) ;
++	return ___swab32(__tmp);
++}
++#endif
++
++#ifndef __arch__swab64
++
++__inline static __u64 __arch__swab64(__u64 x)
++{
++	__u64 __tmp = (x) ;
++	return ___swab64(__tmp);
++}
++
++
++#endif
++
++#ifndef __swab16
++	#define __swab16(x) __fswab16(x)
++	#define __swab32(x) __fswab32(x)
++	#define __swab64(x) __fswab64(x)
++#endif /* __swab16 */
++
++#ifdef PLATFORM_FREEBSD
++	__inline static __u16 __fswab16(__u16 x)
++#else
++	__inline static const __u16 __fswab16(__u16 x)
++#endif /* PLATFORM_FREEBSD */
++{
++	return __arch__swab16(x);
++}
++#ifdef PLATFORM_FREEBSD
++	__inline static __u32 __fswab32(__u32 x)
++#else
++	__inline static const __u32 __fswab32(__u32 x)
++#endif /* PLATFORM_FREEBSD */
++{
++	return __arch__swab32(x);
++}
++
++#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS)
++	#define swab16 __swab16
++	#define swab32 __swab32
++	#define swab64 __swab64
++	#define swab16p __swab16p
++	#define swab32p __swab32p
++	#define swab64p __swab64p
++	#define swab16s __swab16s
++	#define swab32s __swab32s
++	#define swab64s __swab64s
++#endif
++
++#endif /* _LINUX_BYTEORDER_SWAB_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/byteorder/swabb.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/byteorder/swabb.h
+new file mode 100644
+index 000000000..634519a0b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/byteorder/swabb.h
+@@ -0,0 +1,151 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _LINUX_BYTEORDER_SWABB_H
++#define _LINUX_BYTEORDER_SWABB_H
++
++/*
++ * linux/byteorder/swabb.h
++ * SWAp Bytes Bizarrely
++ *	swaHHXX[ps]?(foo)
++ *
++ * Support for obNUXIous pdp-endian and other bizarre architectures.
++ * Will Linux ever run on such ancient beasts? if not, this file
++ * will be but a programming pearl. Still, it's a reminder that we
++ * shouldn't be making too many assumptions when trying to be portable.
++ *
++ */
++
++/*
++ * Meaning of the names I chose (vaxlinux people feel free to correct them):
++ * swahw32	swap 16-bit half-words in a 32-bit word
++ * swahb32	swap 8-bit halves of each 16-bit half-word in a 32-bit word
++ *
++ * No 64-bit support yet. I don't know NUXI conventions for long longs.
++ * I guarantee it will be a mess when it's there, though :->
++ * It will be even worse if there are conflicting 64-bit conventions.
++ * Hopefully, no one ever used 64-bit objects on NUXI machines.
++ *
++ */
++
++#define ___swahw32(x) \
++	({ \
++		__u32 __x = (x); \
++		((__u32)(\
++			 (((__u32)(__x) & (__u32)0x0000ffffUL) << 16) | \
++			 (((__u32)(__x) & (__u32)0xffff0000UL) >> 16))); \
++	})
++#define ___swahb32(x) \
++	({ \
++		__u32 __x = (x); \
++		((__u32)(\
++			 (((__u32)(__x) & (__u32)0x00ff00ffUL) << 8) | \
++			 (((__u32)(__x) & (__u32)0xff00ff00UL) >> 8))); \
++	})
++
++#define ___constant_swahw32(x) \
++	((__u32)(\
++		 (((__u32)(x) & (__u32)0x0000ffffUL) << 16) | \
++		 (((__u32)(x) & (__u32)0xffff0000UL) >> 16)))
++#define ___constant_swahb32(x) \
++	((__u32)(\
++		 (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) | \
++		 (((__u32)(x) & (__u32)0xff00ff00UL) >> 8)))
++
++/*
++ * provide defaults when no architecture-specific optimization is detected
++ */
++#ifndef __arch__swahw32
++	#define __arch__swahw32(x) ___swahw32(x)
++#endif
++#ifndef __arch__swahb32
++	#define __arch__swahb32(x) ___swahb32(x)
++#endif
++
++#ifndef __arch__swahw32p
++	#define __arch__swahw32p(x) __swahw32(*(x))
++#endif
++#ifndef __arch__swahb32p
++	#define __arch__swahb32p(x) __swahb32(*(x))
++#endif
++
++#ifndef __arch__swahw32s
++	#define __arch__swahw32s(x) do { *(x) = __swahw32p((x)); } while (0)
++#endif
++#ifndef __arch__swahb32s
++	#define __arch__swahb32s(x) do { *(x) = __swahb32p((x)); } while (0)
++#endif
++
++
++/*
++ * Allow constant folding
++ */
++#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__)
++#  define __swahw32(x) \
++	(__builtin_constant_p((__u32)(x)) ? \
++	 ___swahw32((x)) : \
++	 __fswahw32((x)))
++#  define __swahb32(x) \
++	(__builtin_constant_p((__u32)(x)) ? \
++	 ___swahb32((x)) : \
++	 __fswahb32((x)))
++#else
++#  define __swahw32(x) __fswahw32(x)
++#  define __swahb32(x) __fswahb32(x)
++#endif /* OPTIMIZE */
++
++
++__inline static__ __const__ __u32 __fswahw32(__u32 x)
++{
++	return __arch__swahw32(x);
++}
++__inline static__ __u32 __swahw32p(__u32 *x)
++{
++	return __arch__swahw32p(x);
++}
++__inline static__ void __swahw32s(__u32 *addr)
++{
++	__arch__swahw32s(addr);
++}
++
++
++__inline static__ __const__ __u32 __fswahb32(__u32 x)
++{
++	return __arch__swahb32(x);
++}
++__inline static__ __u32 __swahb32p(__u32 *x)
++{
++	return __arch__swahb32p(x);
++}
++__inline static__ void __swahb32s(__u32 *addr)
++{
++	__arch__swahb32s(addr);
++}
++
++#ifdef __BYTEORDER_HAS_U64__
++	/*
++	* Not supported yet
++	*/
++#endif /* __BYTEORDER_HAS_U64__ */
++
++#if defined(PLATFORM_LINUX)
++	#define swahw32 __swahw32
++	#define swahb32 __swahb32
++	#define swahw32p __swahw32p
++	#define swahb32p __swahb32p
++	#define swahw32s __swahw32s
++	#define swahb32s __swahb32s
++#endif
++
++#endif /* _LINUX_BYTEORDER_SWABB_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/circ_buf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/circ_buf.h
+new file mode 100644
+index 000000000..7a5b8ef1a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/circ_buf.h
+@@ -0,0 +1,23 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __CIRC_BUF_H_
++#define __CIRC_BUF_H_ 1
++
++#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1))
++
++#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))
++
++#endif //_CIRC_BUF_H_
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/cmd_osdep.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/cmd_osdep.h
+new file mode 100644
+index 000000000..e4ba2b6d3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/cmd_osdep.h
+@@ -0,0 +1,26 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __CMD_OSDEP_H_
++#define __CMD_OSDEP_H_
++
++
++extern sint _rtw_init_cmd_priv(struct	cmd_priv *pcmdpriv);
++extern sint _rtw_init_evt_priv(struct evt_priv *pevtpriv);
++extern void _rtw_free_evt_priv(struct	evt_priv *pevtpriv);
++extern void _rtw_free_cmd_priv(struct	cmd_priv *pcmdpriv);
++extern sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head);
++extern struct cmd_obj *_rtw_dequeue_cmd(_queue *queue);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/cmn_info/rtw_sta_info.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/cmn_info/rtw_sta_info.h
+new file mode 100644
+index 000000000..ae987ebfe
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/cmn_info/rtw_sta_info.h
+@@ -0,0 +1,277 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++ /*This header file is for all driver teams to use the same station info.
++If you want to change this file please make sure notify all driver teams maintainers.*/
++
++/*Created by YuChen 20170301*/
++
++#ifndef __INC_RTW_STA_INFO_H
++#define __INC_RTW_STA_INFO_H
++
++/*--------------------Define ---------------------------------------*/
++
++#define STA_DM_CTRL_ACTIVE			BIT(0)
++#define STA_DM_CTRL_CFO_TRACKING	BIT(1)
++
++#ifdef CONFIG_BEAMFORMING
++#define	BEAMFORMING_HT_BEAMFORMER_ENABLE	BIT(0)	/*Declare sta support beamformer*/
++#define	BEAMFORMING_HT_BEAMFORMEE_ENABLE	BIT(1)	/*Declare sta support beamformee*/
++#define	BEAMFORMING_HT_BEAMFORMER_TEST		BIT(2)	/*Transmiting Beamforming no matter the target supports it or not*/
++#define	BEAMFORMING_HT_BEAMFORMER_STEER_NUM		(BIT(4)|BIT(5))		/*Sta Bfer's capability*/
++#define	BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP	(BIT(6)|BIT(7))		/*Sta BFee's capability*/
++
++#define	BEAMFORMING_VHT_BEAMFORMER_ENABLE	BIT(0)	/*Declare sta support beamformer*/
++#define	BEAMFORMING_VHT_BEAMFORMEE_ENABLE	BIT(1)	/*Declare sta support beamformee*/
++#define	BEAMFORMING_VHT_MU_MIMO_AP_ENABLE	BIT(2)	/*Declare sta support MU beamformer*/
++#define	BEAMFORMING_VHT_MU_MIMO_STA_ENABLE	BIT(3)	/*Declare sta support MU beamformer*/
++#define	BEAMFORMING_VHT_BEAMFORMER_TEST		BIT(4)	/*Transmiting Beamforming no matter the target supports it or not*/
++#define	BEAMFORMING_VHT_BEAMFORMER_STS_CAP		(BIT(8)|BIT(9)|BIT(10))		/*Sta BFee's capability*/
++#define	BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM	(BIT(12)|BIT(13)|BIT(14))	/*Sta Bfer's capability*/
++#endif
++
++#define HT_STBC_EN	BIT(0)
++#define VHT_STBC_EN	BIT(1)
++
++#define HT_LDPC_EN	BIT(0)
++#define VHT_LDPC_EN	BIT(1)
++
++#define	SM_PS_STATIC	0
++#define	SM_PS_DYNAMIC	1
++#define	SM_PS_INVALID	2
++#define	SM_PS_DISABLE	3
++
++
++/*cmn_sta_info.ra_sta_info.txrx_state*/
++#define	TX_STATE				0
++#define	RX_STATE				1
++#define	BI_DIRECTION_STATE	2
++
++/*--------------------Define Enum-----------------------------------*/
++enum channel_width {
++	CHANNEL_WIDTH_20		= 0,
++	CHANNEL_WIDTH_40		= 1,
++	CHANNEL_WIDTH_80		= 2,
++	CHANNEL_WIDTH_160		= 3,
++	CHANNEL_WIDTH_80_80	= 4,
++	CHANNEL_WIDTH_5		= 5,
++	CHANNEL_WIDTH_10	= 6,
++	CHANNEL_WIDTH_MAX	= 7,
++};
++
++enum rf_type {
++	RF_1T1R			= 0,
++	RF_1T2R			= 1,
++	RF_2T1R			= 2,
++	RF_2T2R			= 3,
++	RF_1T3R			= 4,
++	RF_2T3R			= 5,
++	RF_3T1R			= 6,
++	RF_3T2R			= 7,
++	RF_3T3R			= 8,
++	RF_1T4R			= 9,
++	RF_2T4R			= 10,
++	RF_3T4R			= 11,
++	RF_4T1R			= 12,
++	RF_4T2R			= 13,
++	RF_4T3R			= 14,
++	RF_4T4R			= 15,
++	RF_TYPE_MAX,
++};
++
++enum bb_path {
++	BB_PATH_NON = 0,
++	BB_PATH_A = 0x00000001,
++	BB_PATH_B = 0x00000002,
++	BB_PATH_C = 0x00000004,
++	BB_PATH_D = 0x00000008,
++
++	BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
++	BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
++	BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
++	BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
++	BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
++	BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
++
++	BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
++	BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
++	BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
++	BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
++
++	BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
++	BB_PATH_AUTO = 0xff /*for path diversity*/
++};
++
++enum rf_path {
++	RF_PATH_A = 0,
++	RF_PATH_B = 1,
++	RF_PATH_C = 2,
++	RF_PATH_D = 3,
++	RF_PATH_AB,
++	RF_PATH_AC,
++	RF_PATH_AD,
++	RF_PATH_BC,
++	RF_PATH_BD,
++	RF_PATH_CD,
++	RF_PATH_ABC,
++	RF_PATH_ABD,
++	RF_PATH_ACD,
++	RF_PATH_BCD,
++	RF_PATH_ABCD,
++};
++
++enum rf_syn {
++	RF_SYN0 = 0,
++	RF_SYN1 = 1,
++};
++
++enum rfc_mode {
++	rfc_4x4 = 0,
++	rfc_2x2 = 1,
++};
++
++enum wireless_set {
++	WIRELESS_CCK	= 0x00000001,
++	WIRELESS_OFDM	= 0x00000002,
++	WIRELESS_HT	= 0x00000004,
++	WIRELESS_VHT	= 0x00000008,
++};
++
++/*--------------------Define MACRO---------------------------------*/
++
++/*--------------------Define Struct-----------------------------------*/
++
++#ifdef CONFIG_BEAMFORMING
++struct bf_cmn_info {
++	u8	ht_beamform_cap;		/*Sta capablity*/
++	u16	vht_beamform_cap;		/*Sta capablity*/
++	u16	p_aid;
++	u8	g_id;
++};
++#endif
++struct rssi_info {
++	s8		rssi;
++	s8		rssi_cck;
++	s8		rssi_ofdm;
++	u8		packet_map;
++	u8		ofdm_pkt_cnt;
++	u8		cck_pkt_cnt;
++	u16		cck_sum_power;
++	u8		is_send_rssi;
++	u8		valid_bit;
++	s16		rssi_acc;	/*accumulate RSSI for per packet MA sum*/
++};
++
++struct ra_sta_info {
++	u8	rate_id;			/*[PHYDM] ratr_idx*/
++	u8	rssi_level;			/*[PHYDM]*/
++	u8	is_first_connect:1;		/*[PHYDM] CE: ra_rpt_linked, AP: H2C_rssi_rpt*/
++	u8	is_support_sgi:1;		/*[driver]*/
++	u8	is_vht_enable:2;		/*[driver]*/
++	u8	disable_ra:1;			/*[driver]*/
++	u8	disable_pt:1;			/*[driver] remove is_disable_power_training*/
++	u8	txrx_state:2;			/*[PHYDM] 0: Tx, 1:Rx, 2:bi-direction*/
++	u8	is_noisy:1;			/*[PHYDM]*/
++	u8	curr_tx_rate;			/*[PHYDM] FW->Driver*/
++	enum channel_width	ra_bw_mode;	/*[Driver] max bandwidth, for RA only*/
++	enum channel_width	curr_tx_bw;	/*[PHYDM] FW->Driver*/
++	u8	curr_retry_ratio;		/*[PHYDM] FW->Driver*/
++	u64	ramask;
++};
++
++struct dtp_info {
++	u8	dyn_tx_power;	/*Dynamic Tx power offset*/
++	u8	last_tx_power;
++	u8	sta_tx_high_power_lvl:4;
++	u8	sta_last_dtp_lvl:4;
++};
++
++struct cmn_sta_info {
++	u16	dm_ctrl;			/*[Driver]*/
++	enum channel_width	bw_mode;	/*[Driver] max support BW*/
++	u8	mac_id;				/*[Driver]*/
++	u8	mac_addr[6];			/*[Driver]*/
++	u16	aid;				/*[Driver]*/
++	enum rf_type mimo_type;			/*[Driver] sta XTXR*/
++	struct rssi_info	rssi_stat;	/*[PHYDM]*/
++	struct ra_sta_info	ra_info;	/*[Driver&PHYDM]*/
++	u16	tx_moving_average_tp;		/*[Driver] tx average MBps*/
++	u16	rx_moving_average_tp;		/*[Driver] rx average MBps*/
++	u8	stbc_en:2;			/*[Driver] really transmitt STBC*/
++	u8	ldpc_en:2;			/*[Driver] really transmitt LDPC*/
++	enum wireless_set	support_wireless_set;/*[Driver]*/
++#ifdef CONFIG_BEAMFORMING
++	struct bf_cmn_info	bf_info;	/*[Driver]*/
++#endif
++	u8	sm_ps:2;			/*[Driver]*/
++	struct dtp_info dtp_stat;		/*[PHYDM] Dynamic Tx power offset*/
++	/*u8		pw2cca_over_TH_cnt;*/
++	/*u8		total_pw2cca_cnt;*/
++};
++
++struct phydm_phyinfo_fw_struct {
++	u8		rx_rssi[4];	/* RSSI in 0~100 index */
++};
++
++struct phydm_phyinfo_struct {
++	boolean		physts_rpt_valid; /* @if physts_rpt_valid is false, please ignore the parsing result in this structure*/
++	u8		rx_pwdb_all;
++	u8		signal_quality;				/* OFDM: signal_quality=rx_mimo_signal_quality[0], CCK: signal qualityin 0-100 index. */
++	u8		rx_mimo_signal_strength[4];	/* RSSI in 0~100 index */
++	s8		rx_mimo_signal_quality[4];		/* OFDM: per-path's EVM translate to 0~100% , no used for CCK*/
++	u8		rx_mimo_evm_dbm[4];			/* per-path's original EVM (dbm) */
++	s16		cfo_short[4];					/* per-path's cfo_short */
++	s16		cfo_tail[4];					/* per-path's cfo_tail */
++	s8		rx_power;					/* in dBm Translate from PWdB */
++	s8		recv_signal_power;			/* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */
++	u8		bt_rx_rssi_percentage;
++	u8		signal_strength;				/* in 0-100 index. */
++	s8		rx_pwr[4];					/* per-path's pwdb */
++	s8		rx_snr[4];					/* per-path's SNR	*/
++	u8		ant_idx[4];	/*per-path's antenna index*/
++/*ODM_PHY_STATUS_NEW_TYPE_SUPPORT*/
++	u8		rx_count:2;					/* RX path counter---*/
++	u8		band_width:3;
++	u8		rxsc:4;						/* sub-channel---*/
++	u8		channel;						/* channel number---*/
++	u8		is_mu_packet:1;				/* is MU packet or not---boolean*/
++	u8		is_beamformed:1;				/* BF packet---boolean*/
++	u8		cnt_pw2cca;
++	u8		cnt_cca2agc_rdy;
++/*ODM_PHY_STATUS_NEW_TYPE_SUPPORT*/
++};
++
++struct phydm_perpkt_info_struct {
++	u8		data_rate;
++	u8		station_id;
++	u8		is_cck_rate: 1;
++	u8		rate_ss:3;			/*spatial stream of data rate*/
++	u8		is_packet_match_bssid:1;	/*boolean*/
++	u8		is_packet_to_self:1;		/*boolean*/
++	u8		is_packet_beacon:1;		/*boolean*/
++	u8		is_to_self:1;				/*boolean*/
++	u8		ppdu_cnt;
++};
++
++/*--------------------Export global variable----------------------------*/
++
++/*--------------------Function declaration-----------------------------*/
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/custom_gpio.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/custom_gpio.h
+new file mode 100644
+index 000000000..3c67735d6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/custom_gpio.h
+@@ -0,0 +1,34 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __CUSTOM_GPIO_H__
++#define __CUSTOM_GPIO_H___
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++
++typedef enum cust_gpio_modes {
++	WLAN_PWDN_ON,
++	WLAN_PWDN_OFF,
++	WLAN_POWER_ON,
++	WLAN_POWER_OFF,
++	WLAN_BT_PWDN_ON,
++	WLAN_BT_PWDN_OFF
++} cust_gpio_modes_t;
++
++extern int rtw_wifi_gpio_init(void);
++extern int rtw_wifi_gpio_deinit(void);
++extern void rtw_wifi_gpio_wlan_ctrl(int onoff);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_conf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_conf.h
+new file mode 100755
+index 000000000..4784373fb
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_conf.h
+@@ -0,0 +1,729 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __DRV_CONF_H__
++#define __DRV_CONF_H__
++#include "autoconf.h"
++#include "hal_ic_cfg.h"
++
++#define CONFIG_RSSI_PRIORITY
++
++/* 
++ * RTW_BUSY_DENY_SCAN control if scan would be denied by busy traffic.
++ * When this defined, BUSY_TRAFFIC_SCAN_DENY_PERIOD would be used to judge if 
++ * scan request coming from scan UI. Scan request from scan UI would be
++ * exception and never be denied by busy traffic.
++ */
++#define RTW_BUSY_DENY_SCAN
++
++#ifdef CONFIG_RTW_REPEATER_SON
++	#ifndef CONFIG_AP
++		#define CONFIG_AP
++	#endif
++	#ifndef CONFIG_CONCURRENT_MODE
++		#define CONFIG_CONCURRENT_MODE
++	#endif
++	#ifndef CONFIG_BR_EXT
++		#define CONFIG_BR_EXT
++	#endif
++	#ifndef CONFIG_RTW_REPEATER_SON_ID
++		#define CONFIG_RTW_REPEATER_SON_ID			0x02040608
++	#endif
++	//#define CONFIG_RTW_REPEATER_SON_ROOT
++	#ifndef CONFIG_RTW_REPEATER_SON_ROOT
++		#define CONFIG_LAYER2_ROAMING_ACTIVE
++	#endif
++	#undef CONFIG_POWER_SAVING
++#endif
++
++#if defined(CONFIG_MCC_MODE) && (!defined(CONFIG_CONCURRENT_MODE))
++
++	#error "Enable CONCURRENT_MODE before enable MCC MODE\n"
++
++#endif
++
++#if defined(CONFIG_MCC_MODE) && defined(CONFIG_BT_COEXIST)
++
++	#error "Disable BT COEXIST before enable MCC MODE\n"
++
++#endif
++
++#if defined(CONFIG_MCC_MODE) && defined(CONFIG_TDLS)
++
++	#error "Disable TDLS before enable MCC MODE\n"
++
++#endif
++
++#if defined(CONFIG_RTW_80211R) && !defined(CONFIG_LAYER2_ROAMING)
++
++	#error "Enable CONFIG_LAYER2_ROAMING before enable CONFIG_RTW_80211R\n"
++
++#endif
++
++/* Default enable single wiphy if driver ver >= 5.9 */
++#define RTW_SINGLE_WIPHY
++
++#ifdef CONFIG_RTW_ANDROID
++
++	#include <linux/version.h>
++	
++	#ifndef CONFIG_IOCTL_CFG80211
++	#define CONFIG_IOCTL_CFG80211
++	#endif
++	
++	#ifndef RTW_USE_CFG80211_STA_EVENT
++	#define RTW_USE_CFG80211_STA_EVENT
++	#endif
++
++	#if (CONFIG_RTW_ANDROID > 4)
++	#ifndef CONFIG_RADIO_WORK
++	#define CONFIG_RADIO_WORK
++	#endif
++	#endif
++
++	#if (CONFIG_RTW_ANDROID <= 7)
++		#ifdef RTW_SINGLE_WIPHY
++		#undef RTW_SINGLE_WIPHY
++		#endif
++	#endif
++
++	#if (CONFIG_RTW_ANDROID >= 8)
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,0))
++		#ifndef CONFIG_RTW_WIFI_HAL
++		#define CONFIG_RTW_WIFI_HAL
++		#endif
++		#else
++ 		#error "Linux kernel version is too old\n"
++		#endif
++	#endif
++
++	#ifdef CONFIG_RTW_WIFI_HAL
++	#ifndef CONFIG_RTW_WIFI_HAL_DEBUG
++	//#define CONFIG_RTW_WIFI_HAL_DEBUG
++	#endif
++	#ifndef CONFIG_RTW_CFGVENDOR_LLSTATS
++	#define CONFIG_RTW_CFGVENDOR_LLSTATS
++	#endif
++	#ifndef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++	#define CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++	#endif
++	#ifndef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
++	#define CONFIG_RTW_CFGVENDOR_RSSIMONITOR
++	#endif
++	#ifndef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER
++	#define CONFIG_RTW_CFGVENDOR_WIFI_LOGGER
++	#endif
++	#if (CONFIG_RTW_ANDROID >= 10)
++	#ifndef CONFIG_RTW_CFGVENDOR_WIFI_OFFLOAD
++	//#define CONFIG_RTW_CFGVENDOR_WIFI_OFFLOAD
++	#endif
++	#endif
++	#endif // CONFIG_RTW_WIFI_HAL
++
++
++	/* Some Android build will restart the UI while non-printable ascii is passed
++	* between java and c/c++ layer (JNI). We force CONFIG_VALIDATE_SSID
++	* for Android here. If you are sure there is no risk on your system about this,
++	* mask this macro define to support non-printable ascii ssid.
++	* #define CONFIG_VALIDATE_SSID */
++
++	/* Android expect dbm as the rx signal strength unit */
++	#define CONFIG_SIGNAL_DISPLAY_DBM
++#endif // CONFIG_RTW_ANDROID
++
++/*
++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(CONFIG_RESUME_IN_WORKQUEUE)
++	#warning "You have CONFIG_HAS_EARLYSUSPEND enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
++	#undef CONFIG_RESUME_IN_WORKQUEUE
++#endif
++
++#if defined(CONFIG_ANDROID_POWER) && defined(CONFIG_RESUME_IN_WORKQUEUE)
++	#warning "You have CONFIG_ANDROID_POWER enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
++	#undef CONFIG_RESUME_IN_WORKQUEUE
++#endif
++*/
++
++#ifdef CONFIG_RESUME_IN_WORKQUEUE /* this can be removed, because there is no case for this... */
++	#if !defined(CONFIG_WAKELOCK) && !defined(CONFIG_ANDROID_POWER)
++		#error "enable CONFIG_RESUME_IN_WORKQUEUE without CONFIG_WAKELOCK or CONFIG_ANDROID_POWER will suffer from the danger of wifi's unfunctionality..."
++		#error "If you still want to enable CONFIG_RESUME_IN_WORKQUEUE in this case, mask this preprossor checking and GOOD LUCK..."
++	#endif
++#endif
++
++/* About USB VENDOR REQ */
++#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
++	#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically"
++	#define CONFIG_USB_VENDOR_REQ_MUTEX
++#endif
++#if defined(CONFIG_VENDOR_REQ_RETRY) &&  !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
++	#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_VENDOR_REQ_RETRY automatically"
++	#define CONFIG_USB_VENDOR_REQ_MUTEX
++#endif
++
++#ifdef CONFIG_WIFI_MONITOR
++	/*	#define CONFIG_MONITOR_MODE_XMIT	*/
++#endif
++
++#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
++	#ifndef CONFIG_WIFI_MONITOR
++		#define CONFIG_WIFI_MONITOR
++	#endif
++	#ifdef CONFIG_POWER_SAVING
++		#undef CONFIG_POWER_SAVING
++	#endif
++#endif
++
++#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
++	#ifdef CONFIG_POWER_SAVING
++		#undef CONFIG_POWER_SAVING
++	#endif
++	#ifdef CONFIG_BEAMFORMING
++		#undef CONFIG_BEAMFORMING
++	#endif
++#endif
++
++#ifndef CONFIG_RTW_DATA_BMC_TO_UC
++#define CONFIG_RTW_DATA_BMC_TO_UC 0
++#endif
++
++#ifdef CONFIG_AP_MODE
++	#define CONFIG_LIMITED_AP_NUM 1
++
++	#ifndef CONFIG_RTW_AP_DATA_BMC_TO_UC
++	#define CONFIG_RTW_AP_DATA_BMC_TO_UC 1
++	#endif
++	#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++	#undef CONFIG_RTW_DATA_BMC_TO_UC
++	#define CONFIG_RTW_DATA_BMC_TO_UC 1
++	#endif
++	#ifndef CONFIG_RTW_AP_SRC_B2U_FLAGS
++	#define CONFIG_RTW_AP_SRC_B2U_FLAGS 0x8 /* see RTW_AP_B2U_XXX */
++	#endif
++	#ifndef CONFIG_RTW_AP_FWD_B2U_FLAGS
++	#define CONFIG_RTW_AP_FWD_B2U_FLAGS 0x8 /* see RTW_AP_B2U_XXX */
++	#endif
++#endif
++
++#ifdef CONFIG_RTW_MULTI_AP
++	#ifndef CONFIG_AP_MODE
++	#error "enable CONFIG_RTW_MULTI_AP without CONFIG_AP_MODE"
++	#endif
++	#ifndef CONFIG_RTW_WDS
++	#define CONFIG_RTW_WDS
++	#endif
++#endif
++
++#ifdef CONFIG_RTW_MESH
++	#ifndef CONFIG_RTW_MESH_ACNODE_PREVENT
++	#define CONFIG_RTW_MESH_ACNODE_PREVENT 1
++	#endif
++
++	#ifndef CONFIG_RTW_MESH_OFFCH_CAND
++	#define CONFIG_RTW_MESH_OFFCH_CAND 1
++	#endif
++
++	#ifndef CONFIG_RTW_MESH_PEER_BLACKLIST
++	#define CONFIG_RTW_MESH_PEER_BLACKLIST 1
++	#endif
++
++	#ifndef CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++	#define CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST 1
++	#endif
++	#ifndef CONFIG_RTW_MESH_CTO_MGATE_CARRIER
++	#define CONFIG_RTW_MESH_CTO_MGATE_CARRIER CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++	#endif
++
++	#ifndef CONFIG_RTW_MPM_TX_IES_SYNC_BSS
++	#define CONFIG_RTW_MPM_TX_IES_SYNC_BSS 1
++	#endif
++	#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS
++		#ifndef CONFIG_RTW_MESH_AEK
++		#define CONFIG_RTW_MESH_AEK
++		#endif
++	#endif
++
++	#ifndef CONFIG_RTW_MESH_DATA_BMC_TO_UC
++	#define CONFIG_RTW_MESH_DATA_BMC_TO_UC 1
++	#endif
++	#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++	#undef CONFIG_RTW_DATA_BMC_TO_UC
++	#define CONFIG_RTW_DATA_BMC_TO_UC 1
++	#endif
++	#ifndef CONFIG_RTW_MSRC_B2U_FLAGS
++	#define CONFIG_RTW_MSRC_B2U_FLAGS 0x0 /* see RTW_MESH_B2U_XXX */
++	#endif
++	#ifndef CONFIG_RTW_MFWD_B2U_FLAGS
++	#define CONFIG_RTW_MFWD_B2U_FLAGS 0x2 /* see RTW_MESH_B2U_XXX */
++	#endif
++#endif
++
++#if !defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE)
++#define CONFIG_SCAN_BACKOP
++#endif
++
++#define RTW_SCAN_SPARSE_MIRACAST 1
++#define RTW_SCAN_SPARSE_BG 0
++#define RTW_SCAN_SPARSE_ROAMING_ACTIVE 1
++
++#ifndef CONFIG_TX_AC_LIFETIME
++#define CONFIG_TX_AC_LIFETIME 1
++#endif
++#ifndef CONFIG_TX_ACLT_FLAGS
++#define CONFIG_TX_ACLT_FLAGS 0x00
++#endif
++#ifndef CONFIG_TX_ACLT_CONF_DEFAULT
++#define CONFIG_TX_ACLT_CONF_DEFAULT {0x0, 1024 * 1000, 1024 * 1000}
++#endif
++#ifndef CONFIG_TX_ACLT_CONF_AP_M2U
++#define CONFIG_TX_ACLT_CONF_AP_M2U {0xF, 256 * 1000, 256 * 1000}
++#endif
++#ifndef CONFIG_TX_ACLT_CONF_MESH
++#define CONFIG_TX_ACLT_CONF_MESH {0xF, 256 * 1000, 256 * 1000}
++#endif
++
++#ifndef CONFIG_RTW_HIQ_FILTER
++	#define CONFIG_RTW_HIQ_FILTER 1
++#endif
++
++#ifndef CONFIG_RTW_ADAPTIVITY_EN
++	#define CONFIG_RTW_ADAPTIVITY_EN 0
++#endif
++
++#ifndef CONFIG_RTW_ADAPTIVITY_MODE
++	#define CONFIG_RTW_ADAPTIVITY_MODE 0
++#endif
++
++#ifndef CONFIG_RTW_ADAPTIVITY_TH_L2H_INI
++	#define CONFIG_RTW_ADAPTIVITY_TH_L2H_INI 0
++#endif
++
++#ifndef CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF
++	#define CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF 0
++#endif
++
++#ifndef CONFIG_RTW_EXCL_CHS
++	#define CONFIG_RTW_EXCL_CHS {0}
++#endif
++
++#ifndef CONFIG_IEEE80211_BAND_5GHZ
++	#if defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8821C) \
++		|| defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) \
++		|| defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8814B)
++	#define CONFIG_IEEE80211_BAND_5GHZ 1
++	#else
++	#define CONFIG_IEEE80211_BAND_5GHZ 0
++	#endif
++#endif
++
++#ifndef CONFIG_DFS
++#define CONFIG_DFS 1
++#endif
++
++#if CONFIG_IEEE80211_BAND_5GHZ && CONFIG_DFS && defined(CONFIG_AP_MODE)
++	#if !defined(CONFIG_DFS_SLAVE_WITH_RADAR_DETECT)
++	#define CONFIG_DFS_SLAVE_WITH_RADAR_DETECT 0
++	#endif
++	#if !defined(CONFIG_DFS_MASTER) || CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
++	#define CONFIG_DFS_MASTER
++	#endif
++	#if defined(CONFIG_DFS_MASTER) && !defined(CONFIG_RTW_DFS_REGION_DOMAIN)
++	#define CONFIG_RTW_DFS_REGION_DOMAIN 0
++	#endif
++#else
++	#undef CONFIG_DFS_MASTER
++	#undef CONFIG_RTW_DFS_REGION_DOMAIN
++	#define CONFIG_RTW_DFS_REGION_DOMAIN 0
++	#undef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
++	#define CONFIG_DFS_SLAVE_WITH_RADAR_DETECT 0
++#endif
++
++#ifndef CONFIG_TXPWR_BY_RATE_EN
++#define CONFIG_TXPWR_BY_RATE_EN 2 /* by efuse */
++#endif
++#ifndef CONFIG_TXPWR_LIMIT_EN
++#define CONFIG_TXPWR_LIMIT_EN 2 /* by efuse */
++#endif
++
++#ifndef CONFIG_RTW_CHPLAN
++#define CONFIG_RTW_CHPLAN 0xFF /* RTW_CHPLAN_UNSPECIFIED */
++#endif
++
++/* compatible with old fashion configuration */
++#if defined(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY)
++	#undef CONFIG_TXPWR_BY_RATE_EN
++	#undef CONFIG_TXPWR_LIMIT_EN
++	#define CONFIG_TXPWR_BY_RATE_EN 1
++	#define CONFIG_TXPWR_LIMIT_EN 1
++#elif defined(CONFIG_CALIBRATE_TX_POWER_TO_MAX)
++	#undef CONFIG_TXPWR_BY_RATE_EN
++	#undef CONFIG_TXPWR_LIMIT_EN
++	#define CONFIG_TXPWR_BY_RATE_EN 1
++	#define CONFIG_TXPWR_LIMIT_EN 0
++#endif
++
++#ifndef RTW_DEF_MODULE_REGULATORY_CERT
++	#define RTW_DEF_MODULE_REGULATORY_CERT 0
++#endif
++
++#if RTW_DEF_MODULE_REGULATORY_CERT
++	/* force enable TX power by rate and TX power limit */
++	#undef CONFIG_TXPWR_BY_RATE_EN
++	#undef CONFIG_TXPWR_LIMIT_EN
++	#define CONFIG_TXPWR_BY_RATE_EN 1
++	#define CONFIG_TXPWR_LIMIT_EN 1
++#endif
++
++#if !CONFIG_TXPWR_LIMIT && CONFIG_TXPWR_LIMIT_EN
++	#undef CONFIG_TXPWR_LIMIT
++	#define CONFIG_TXPWR_LIMIT 1
++#endif
++
++#ifdef CONFIG_RTW_IPCAM_APPLICATION
++	#undef CONFIG_TXPWR_BY_RATE_EN
++	#define CONFIG_TXPWR_BY_RATE_EN 1
++	#define CONFIG_RTW_CUSTOMIZE_BEEDCA		0x0000431C
++	#define CONFIG_RTW_CUSTOMIZE_BWMODE		0x00
++	#define CONFIG_RTW_CUSTOMIZE_RLSTA		0x30
++#if defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B)
++	#define CONFIG_RTW_TX_NPATH_EN		/*	mutually incompatible with STBC_TX & Beamformer	*/
++#endif
++#endif
++/* #define CONFIG_RTW_TOKEN_BASED_XMIT */
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	#define NR_TBTX_SLOT			4
++	#define NR_MAXSTA_INSLOT		5
++	#define TBTX_TX_DURATION		30
++	
++	#define MAX_TXPAUSE_DURATION	(TBTX_TX_DURATION*NR_TBTX_SLOT)
++#endif
++
++/*#define CONFIG_EXTEND_LOWRATE_TXOP			*/
++
++#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS
++	#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS {0xFF, 0xFF, 0xFF, 0xFF}
++#endif
++#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS
++	#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS {0xFF, 0xFF, 0xFF, 0xFF}
++#endif
++#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS
++	#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS {0xFF, 0xFF, 0xFF, 0xFF}
++#endif
++#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS
++	#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS {0xFF, 0xFF, 0xFF, 0xFF}
++#endif
++
++#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_A
++	#define CONFIG_RTW_TARGET_TX_PWR_2G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
++#endif
++
++#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_B
++	#define CONFIG_RTW_TARGET_TX_PWR_2G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
++#endif
++
++#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_C
++	#define CONFIG_RTW_TARGET_TX_PWR_2G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
++#endif
++
++#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_D
++	#define CONFIG_RTW_TARGET_TX_PWR_2G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
++#endif
++
++#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_A
++	#define CONFIG_RTW_TARGET_TX_PWR_5G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1}
++#endif
++
++#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_B
++	#define CONFIG_RTW_TARGET_TX_PWR_5G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1}
++#endif
++
++#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_C
++	#define CONFIG_RTW_TARGET_TX_PWR_5G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1}
++#endif
++
++#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_D
++	#define CONFIG_RTW_TARGET_TX_PWR_5G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1}
++#endif
++
++#ifndef CONFIG_RTW_AMPLIFIER_TYPE_2G
++	#define CONFIG_RTW_AMPLIFIER_TYPE_2G 0
++#endif
++
++#ifndef CONFIG_RTW_AMPLIFIER_TYPE_5G
++	#define CONFIG_RTW_AMPLIFIER_TYPE_5G 0
++#endif
++
++#ifndef CONFIG_RTW_RFE_TYPE
++	#define CONFIG_RTW_RFE_TYPE 64
++#endif
++
++#ifndef CONFIG_RTW_GLNA_TYPE
++	#define CONFIG_RTW_GLNA_TYPE 0
++#endif
++
++#ifndef CONFIG_RTW_PLL_REF_CLK_SEL
++	#define CONFIG_RTW_PLL_REF_CLK_SEL 0x0F
++#endif
++
++#ifndef CONFIG_IFACE_NUMBER
++	#ifdef CONFIG_CONCURRENT_MODE
++		#define CONFIG_IFACE_NUMBER	2
++	#else
++		#define CONFIG_IFACE_NUMBER	1
++	#endif
++#endif
++
++#ifndef CONFIG_CONCURRENT_MODE
++	#if (CONFIG_IFACE_NUMBER > 1)
++		#error "CONFIG_IFACE_NUMBER over 1,but CONFIG_CONCURRENT_MODE not defined"
++	#endif
++#endif
++
++#if (CONFIG_IFACE_NUMBER == 0)
++	#error "CONFIG_IFACE_NUMBER cound not be 0 !!"
++#endif
++
++#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8188F) || \
++defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8192F) || \
++defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8710B) || \
++defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8723D)
++#define CONFIG_HWMPCAP_GEN1
++#elif defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) /*|| defined(CONFIG_RTL8814A)*/
++#define CONFIG_HWMPCAP_GEN2
++#elif defined(CONFIG_RTL8814B) /*Address CAM - 128*/
++#define CONFIG_HWMPCAP_GEN3
++#endif
++
++#if defined(CONFIG_HWMPCAP_GEN1) && (CONFIG_IFACE_NUMBER > 2) 
++	#ifdef CONFIG_POWER_SAVING
++	/*#warning "Disable PS when CONFIG_IFACE_NUMBER > 2"*/
++	#undef CONFIG_POWER_SAVING
++	#endif
++
++	#ifdef CONFIG_WOWLAN
++	#error "This IC can't support MI and WoWLan at the same time"
++	#endif
++#endif
++
++#if defined(CONFIG_HWMPCAP_GEN1) && (CONFIG_IFACE_NUMBER > 3)
++        #error " This IC can't support over 3 interfaces !!"
++#endif
++
++#if (CONFIG_IFACE_NUMBER > 4)
++	#error "Not support over 4 interfaces yet !!"
++#endif
++
++#if (CONFIG_IFACE_NUMBER > 8)	/*IFACE_ID_MAX*/
++	#error "HW count not support over 8 interfaces !!"
++#endif
++
++#if (CONFIG_IFACE_NUMBER > 2)
++	#define CONFIG_MI_WITH_MBSSID_CAM
++
++	#ifdef CONFIG_MI_WITH_MBSSID_CAM
++		#define CONFIG_MBSSID_CAM
++		#if defined(CONFIG_RUNTIME_PORT_SWITCH)
++			#undef CONFIG_RUNTIME_PORT_SWITCH
++		#endif
++	#endif
++
++	#ifdef CONFIG_AP_MODE
++		#undef CONFIG_LIMITED_AP_NUM
++		#define CONFIG_LIMITED_AP_NUM	2
++
++		#define CONFIG_SUPPORT_MULTI_BCN
++
++		#define CONFIG_SWTIMER_BASED_TXBCN
++
++		#ifdef CONFIG_HWMPCAP_GEN2 /*CONFIG_RTL8822B/CONFIG_RTL8821C/CONFIG_RTL8822C*/
++		#define CONFIG_FW_HANDLE_TXBCN
++
++		#ifdef CONFIG_FW_HANDLE_TXBCN
++			#ifdef CONFIG_SWTIMER_BASED_TXBCN
++				#undef CONFIG_SWTIMER_BASED_TXBCN
++			#endif
++			#undef CONFIG_LIMITED_AP_NUM
++			#define CONFIG_LIMITED_AP_NUM	4
++		#endif
++
++		#endif /*CONFIG_HWMPCAP_GEN2*/
++	#endif /*CONFIG_AP_MODE*/
++
++	#ifdef CONFIG_HWMPCAP_GEN2 /*CONFIG_RTL8822B/CONFIG_RTL8821C/CONFIG_RTL8822C*/
++	#define CONFIG_CLIENT_PORT_CFG
++	#define CONFIG_NEW_NETDEV_HDL
++	#endif/*CONFIG_HWMPCAP_GEN2*/
++#endif/*(CONFIG_IFACE_NUMBER > 2)*/
++
++#define MACID_NUM_SW_LIMIT 32
++#define SEC_CAM_ENT_NUM_SW_LIMIT 32
++
++#ifdef SEC_DEFAULT_KEY_SEARCH
++	#if (CONFIG_IFACE_NUMBER >= 2)
++		#error "Default Key Search only work with only one interface case!"
++	#endif
++#endif
++
++#if defined(CONFIG_WOWLAN) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B))
++	#define CONFIG_WOW_PATTERN_HW_CAM
++#endif
++
++#ifndef CONFIG_TSF_UPDATE_PAUSE_FACTOR
++#define CONFIG_TSF_UPDATE_PAUSE_FACTOR 200
++#endif
++
++#ifndef CONFIG_TSF_UPDATE_RESTORE_FACTOR
++#define CONFIG_TSF_UPDATE_RESTORE_FACTOR 5
++#endif
++
++/*
++	Mark CONFIG_DEAUTH_BEFORE_CONNECT by Arvin 2015/07/20
++	If the failure of Wi-Fi connection is due to some irregular disconnection behavior (like unplug dongle,
++	power down etc.) in last time, we can unmark this flag to avoid some unpredictable response from AP.
++*/
++/*#define CONFIG_DEAUTH_BEFORE_CONNECT */
++
++/*#define CONFIG_WEXT_DONT_JOIN_BYSSID	*/
++/* #include <rtl871x_byteorder.h> */
++
++
++/*#define CONFIG_DOSCAN_IN_BUSYTRAFFIC	*/
++/*#define CONFIG_PHDYM_FW_FIXRATE		*/	/*	Another way to fix tx rate	*/
++
++/*Don't release SDIO irq in suspend/resume procedure*/
++#define CONFIG_RTW_SDIO_KEEP_IRQ	0
++
++/*
++ * Add by Lucas@2016/02/15
++ * For RX Aggregation
++ */
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_RX_AGGREGATION)
++	#define RTW_RX_AGGREGATION
++#endif /* CONFIG_SDIO_HCI || CONFIG_USB_RX_AGGREGATION */
++
++#ifdef CONFIG_RTW_HOSTAPD_ACS
++	#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
++		#ifndef CONFIG_FIND_BEST_CHANNEL
++			#define CONFIG_FIND_BEST_CHANNEL
++		#endif
++	#else
++		#ifdef CONFIG_FIND_BEST_CHANNEL
++			#undef CONFIG_FIND_BEST_CHANNEL
++		#endif
++		#ifndef CONFIG_RTW_ACS
++			#define CONFIG_RTW_ACS
++		#endif
++		#ifndef CONFIG_BACKGROUND_NOISE_MONITOR
++			#define CONFIG_BACKGROUND_NOISE_MONITOR
++		#endif
++	#endif
++#endif
++
++#ifdef CONFIG_RTW_80211K
++	#ifndef CONFIG_RTW_ACS
++		#define CONFIG_RTW_ACS
++	#endif
++#endif /*CONFIG_RTW_80211K*/
++
++#ifdef DBG_CONFIG_ERROR_RESET
++#ifndef CONFIG_IPS
++#define CONFIG_IPS
++#endif
++#endif
++
++/* IPS */
++#ifndef RTW_IPS_MODE
++	#if defined(CONFIG_IPS)
++		#define RTW_IPS_MODE 1
++	#else
++		#define RTW_IPS_MODE 0
++	#endif
++#endif /* !RTW_IPS_MODE */
++
++#if (RTW_IPS_MODE > 1 || RTW_IPS_MODE < 0)
++	#error "The CONFIG_IPS_MODE value is wrong. Please follow HowTo_enable_the_power_saving_functionality.pdf.\n"
++#endif
++
++/* LPS */
++#ifndef RTW_LPS_MODE
++	#if defined(CONFIG_LPS_PG) || defined(CONFIG_LPS_PG_DDMA)
++		#define RTW_LPS_MODE 3
++	#elif defined(CONFIG_LPS_LCLK)
++		#define RTW_LPS_MODE 2
++	#elif defined(CONFIG_LPS)
++		#define RTW_LPS_MODE 1
++	#else
++		#define RTW_LPS_MODE 0
++	#endif 
++#endif /* !RTW_LPS_MODE */
++
++#if (RTW_LPS_MODE > 3 || RTW_LPS_MODE < 0)
++	#error "The CONFIG_LPS_MODE value is wrong. Please follow HowTo_enable_the_power_saving_functionality.pdf.\n"
++#endif
++
++#ifndef RTW_LPS_1T1R
++#define RTW_LPS_1T1R 0
++#endif
++
++#ifndef RTW_WOW_LPS_1T1R
++#define RTW_WOW_LPS_1T1R 0
++#endif
++
++/* WOW LPS */
++#ifndef RTW_WOW_LPS_MODE
++	#if defined(CONFIG_LPS_PG) || defined(CONFIG_LPS_PG_DDMA)
++		#define RTW_WOW_LPS_MODE 3
++	#elif defined(CONFIG_LPS_LCLK)
++		#define RTW_WOW_LPS_MODE 2
++	#elif defined(CONFIG_LPS)
++		#define RTW_WOW_LPS_MODE 1
++	#else
++		#define RTW_WOW_LPS_MODE 0
++	#endif
++#endif /* !RTW_WOW_LPS_MODE */
++
++#if (RTW_WOW_LPS_MODE > 3 || RTW_WOW_LPS_MODE < 0)
++	#error "The RTW_WOW_LPS_MODE value is wrong. Please follow HowTo_enable_the_power_saving_functionality.pdf.\n"
++#endif
++
++#ifdef RTW_REDUCE_SCAN_SWITCH_CH_TIME
++#ifndef CONFIG_RTL8822B
++	#error "Only 8822B support RTW_REDUCE_SCAN_SWITCH_CH_TIME"
++#endif
++	#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
++		#define RTW_CHANNEL_SWITCH_OFFLOAD
++	#endif
++#endif
++
++#define CONFIG_RTW_TPT_MODE 
++
++#ifdef CONFIG_PCI_BCN_POLLING
++#define CONFIG_BCN_ICF
++#endif 
++
++#ifndef CONFIG_PCI_MSI
++#define CONFIG_RTW_PCI_MSI_DISABLE
++#endif
++
++#if defined(CONFIG_PCI_DYNAMIC_ASPM_L1_LATENCY) ||	\
++    defined(CONFIG_PCI_DYNAMIC_ASPM_LINK_CTRL)
++#define CONFIG_PCI_DYNAMIC_ASPM
++#endif
++
++#if 0
++/* Debug related compiler flags */
++#define DBG_THREAD_PID	/* Add thread pid to debug message prefix */
++#define DBG_CPU_INFO	/* Add CPU info to debug message prefix */
++#endif
++
++#endif /* __DRV_CONF_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types.h
+new file mode 100755
+index 000000000..33a6d7c83
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types.h
+@@ -0,0 +1,1982 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*-------------------------------------------------------------------------------
++
++	For type defines and data structure defines
++
++--------------------------------------------------------------------------------*/
++
++
++#ifndef __DRV_TYPES_H__
++#define __DRV_TYPES_H__
++
++#include <drv_conf.h>
++#include <basic_types.h>
++#include <osdep_service.h>
++#include <rtw_byteorder.h>
++#include <wlan_bssdef.h>
++#include <wifi.h>
++#include <ieee80211.h>
++#ifdef CONFIG_ARP_KEEP_ALIVE
++	#include <net/neighbour.h>
++	#include <net/arp.h>
++#endif
++
++#ifdef PLATFORM_OS_XP
++	#include <drv_types_xp.h>
++#endif
++
++#ifdef PLATFORM_OS_CE
++	#include <drv_types_ce.h>
++#endif
++
++#ifdef PLATFORM_LINUX
++	#include <drv_types_linux.h>
++#endif
++
++enum _NIC_VERSION {
++
++	RTL8711_NIC,
++	RTL8712_NIC,
++	RTL8713_NIC,
++	RTL8716_NIC
++
++};
++
++typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER;
++
++#include <rtw_debug.h>
++#include <cmn_info/rtw_sta_info.h>
++#include <rtw_rf.h>
++#include "../core/rtw_chplan.h"
++
++#ifdef CONFIG_80211N_HT
++	#include <rtw_ht.h>
++#endif
++
++#ifdef CONFIG_80211AC_VHT
++	#include <rtw_vht.h>
++#endif
++
++#include <rtw_cmd.h>
++#include <cmd_osdep.h>
++#include <rtw_security.h>
++#include <rtw_xmit.h>
++#include <xmit_osdep.h>
++#include <rtw_recv.h>
++#include <rtw_rm.h>
++
++#ifdef CONFIG_BEAMFORMING
++	#include <rtw_beamforming.h>
++#endif
++
++#include <recv_osdep.h>
++#include <rtw_efuse.h>
++#include <rtw_sreset.h>
++#include <hal_intf.h>
++#include <hal_com.h>
++#include<hal_com_h2c.h>
++#include <hal_com_led.h>
++#include "../hal/hal_dm.h"
++#include <rtw_qos.h>
++#include <rtw_pwrctrl.h>
++#ifdef CONFIG_RTW_80211R
++#include <rtw_ft.h>
++#endif
++#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
++#include <rtw_wnm.h>
++#endif
++#ifdef CONFIG_RTW_MBO
++#include <rtw_mbo.h>
++#endif
++#include <rtw_mlme.h>
++#include <mlme_osdep.h>
++#include <rtw_io.h>
++#include <rtw_ioctl.h>
++#include <rtw_ioctl_set.h>
++#include <rtw_ioctl_query.h>
++#include <osdep_intf.h>
++#include <rtw_eeprom.h>
++#include <sta_info.h>
++#include <rtw_event.h>
++#include <rtw_mlme_ext.h>
++#include <rtw_mi.h>
++#include <rtw_ap.h>
++#ifdef CONFIG_RTW_WDS
++#include "../core/wds/rtw_wds.h"
++#endif
++#ifdef CONFIG_RTW_MESH
++#include "../core/mesh/rtw_mesh.h"
++#endif
++#ifdef CONFIG_WIFI_MONITOR
++#include "../core/monitor/rtw_radiotap.h"
++#endif
++#include <rtw_efuse.h>
++#include <rtw_version.h>
++#include <rtw_odm.h>
++
++#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
++	#include <rtw_mem.h>
++#endif
++
++#include <rtw_p2p.h>
++
++#ifdef CONFIG_TDLS
++	#include <rtw_tdls.h>
++#endif /* CONFIG_TDLS */
++
++#ifdef CONFIG_WAPI_SUPPORT
++	#include <rtw_wapi.h>
++#endif /* CONFIG_WAPI_SUPPORT */
++
++#ifdef CONFIG_MP_INCLUDED
++	#include <rtw_mp.h>
++#endif /* CONFIG_MP_INCLUDED */
++
++#ifdef CONFIG_BR_EXT
++	#include <rtw_br_ext.h>
++#endif /* CONFIG_BR_EXT */
++
++#ifdef CONFIG_IOL
++	#include <rtw_iol.h>
++#endif /* CONFIG_IOL */
++
++#include <ip.h>
++#include <if_ether.h>
++#include <ethernet.h>
++#include <circ_buf.h>
++
++#include <rtw_android.h>
++
++#include <rtw_btcoex_wifionly.h>
++#include <rtw_btcoex.h>
++
++#ifdef CONFIG_MCC_MODE
++	#include <rtw_mcc.h>
++#endif /*CONFIG_MCC_MODE */
++
++#ifdef CONFIG_RTW_REPEATER_SON
++	#include <rtw_rson.h>
++#endif /*CONFIG_RTW_REPEATER_SON */
++
++#define SPEC_DEV_ID_NONE BIT(0)
++#define SPEC_DEV_ID_DISABLE_HT BIT(1)
++#define SPEC_DEV_ID_ENABLE_PS BIT(2)
++#define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3)
++#define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4)
++#define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5)
++
++struct specific_device_id {
++
++	u32		flags;
++
++	u16		idVendor;
++	u16		idProduct;
++
++};
++
++struct registry_priv {
++	u8	chip_version;
++	u8	rfintfs;
++	u8	lbkmode;
++	u8	hci;
++	NDIS_802_11_SSID	ssid;
++	u8	network_mode;	/* infra, ad-hoc, auto */
++	u8	channel;/* ad-hoc support requirement */
++	u8	wireless_mode;/* A, B, G, auto */
++	u8	scan_mode;/* active, passive */
++	u8	radio_enable;
++	u8	preamble;/* long, short, auto */
++	u8	vrtl_carrier_sense;/* Enable, Disable, Auto */
++	u8	vcs_type;/* RTS/CTS, CTS-to-self */
++	u16	rts_thresh;
++	u16  frag_thresh;
++	u8	adhoc_tx_pwr;
++	u8	soft_ap;
++	u8	power_mgnt;
++	u8	ips_mode;
++	u8	lps_level;
++#ifdef CONFIG_LPS_1T1R
++	u8	lps_1t1r;
++#endif
++	u8	lps_chk_by_tp;
++#ifdef CONFIG_WOWLAN
++	u8	wow_power_mgnt;
++	u8	wow_lps_level;
++	#ifdef CONFIG_LPS_1T1R
++	u8	wow_lps_1t1r;
++	#endif
++#endif /* CONFIG_WOWLAN */
++	u8	smart_ps;
++#ifdef CONFIG_WMMPS_STA
++	u8	wmm_smart_ps;
++#endif /* CONFIG_WMMPS_STA */
++	u8   usb_rxagg_mode;
++	u8	dynamic_agg_enable;
++	u8	long_retry_lmt;
++	u8	short_retry_lmt;
++	u16	busy_thresh;
++	u16	max_bss_cnt;
++	u8	ack_policy;
++	u8	mp_mode;
++#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)
++	u8 mp_customer_str;
++#endif
++	u8  mp_dm;
++	u8	software_encrypt;
++	u8	software_decrypt;
++#ifdef CONFIG_TX_EARLY_MODE
++	u8   early_mode;
++#endif
++#ifdef CONFIG_NARROWBAND_SUPPORTING
++	u8	rtw_nb_config;
++#endif
++	u8	acm_method;
++	/* WMM */
++	u8	wmm_enable;
++#ifdef CONFIG_WMMPS_STA
++	/* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */
++	u8	uapsd_max_sp_len;
++	/* BIT0: AC_VO UAPSD, BIT1: AC_VI UAPSD, BIT2: AC_BK UAPSD, BIT3: AC_BE UAPSD */
++	u8	uapsd_ac_enable;
++#endif /* CONFIG_WMMPS_STA */
++
++	WLAN_BSSID_EX    dev_network;
++
++#if CONFIG_TX_AC_LIFETIME
++	u8 tx_aclt_flags;
++	struct tx_aclt_conf_t tx_aclt_confs[TX_ACLT_CONF_NUM];
++#endif
++
++	u8 tx_bw_mode;
++#ifdef CONFIG_AP_MODE
++	u8 bmc_tx_rate;
++	#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++	u8 ap_src_b2u_flags;
++	u8 ap_fwd_b2u_flags;
++	#endif
++#endif
++
++#ifdef CONFIG_RTW_MESH
++	#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++	u8 msrc_b2u_flags;
++	u8 mfwd_b2u_flags;
++	#endif
++#endif
++
++#ifdef CONFIG_80211N_HT
++	u8	ht_enable;
++	/* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz */
++	/* 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7 */
++	/* 0x21 means enable 2.4G 40MHz & 5G 80MHz */
++	u8	bw_mode;
++	u8	ampdu_enable;/* for tx */
++	u8	rx_stbc;
++	u8	rx_ampdu_amsdu;/* Rx A-MPDU Supports A-MSDU is permitted */
++	u8	tx_ampdu_amsdu;/* Tx A-MPDU Supports A-MSDU is permitted */
++	u8	tx_quick_addba_req;
++	u8 rx_ampdu_sz_limit_by_nss_bw[4][4]; /* 1~4SS, BW20~BW160 */
++	/* Short GI support Bit Map */
++	/* BIT0 - 20MHz, 1: support, 0: non-support */
++	/* BIT1 - 40MHz, 1: support, 0: non-support */
++	/* BIT2 - 80MHz, 1: support, 0: non-support */
++	/* BIT3 - 160MHz, 1: support, 0: non-support */
++	u8	short_gi;
++	/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */
++	u8	ldpc_cap;
++	/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */
++	u8	stbc_cap;
++	#if defined(CONFIG_RTW_TX_NPATH_EN)
++	u8	tx_npath;
++	#endif
++	#if defined(CONFIG_RTW_PATH_DIV)
++	u8 path_div;
++	#endif
++	/*
++	 * BIT0: Enable VHT SU Beamformer
++	 * BIT1: Enable VHT SU Beamformee
++	 * BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer
++	 * BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee
++	 * BIT4: Enable HT Beamformer
++	 * BIT5: Enable HT Beamformee
++	 */
++	u8	beamform_cap;
++	u8	beamformer_rf_num;
++	u8	beamformee_rf_num;
++#endif /* CONFIG_80211N_HT */
++
++#ifdef CONFIG_80211AC_VHT
++	u8	vht_enable; /* 0:disable, 1:enable, 2:auto */
++	u8	ampdu_factor;
++	u8 vht_rx_mcs_map[2];
++#endif /* CONFIG_80211AC_VHT */
++
++	u8	lowrate_two_xmit;
++
++	u8	low_power ;
++
++	u8	wifi_spec;/* !turbo_mode */
++
++	u8 trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp, 0: not specified */
++	u8 tx_path_lmt; /* limit of TX path number, 0: not specified */
++	u8 rx_path_lmt; /* limit of TX path number, 0: not specified */
++	u8 tx_nss;
++	u8 rx_nss;
++
++	char alpha2[2];
++	u8	channel_plan;
++	u8	excl_chs[MAX_CHANNEL_NUM];
++	u8	full_ch_in_p2p_handshake; /* 0: reply only softap channel, 1: reply full channel list*/
++
++#ifdef CONFIG_BT_COEXIST
++	u8	btcoex;
++	u8	bt_iso;
++	u8	bt_sco;
++	u8	bt_ampdu;
++	u8	ant_num;
++	u8	single_ant_path;
++#endif
++	BOOLEAN	bAcceptAddbaReq;
++
++	u8	antdiv_cfg;
++	u8	antdiv_type;
++	u8	drv_ant_band_switch;
++
++	u8	switch_usb_mode;
++
++	u8	usbss_enable;/* 0:disable,1:enable */
++	u8	hwpdn_mode;/* 0:disable,1:enable,2:decide by EFUSE config */
++	u8	hwpwrp_detect;/* 0:disable,1:enable */
++
++	u8	hw_wps_pbc;/* 0:disable,1:enable */
++
++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
++	char	adaptor_info_caching_file_path[PATH_LENGTH_MAX];
++#endif
++
++#ifdef CONFIG_LAYER2_ROAMING
++	u8	max_roaming_times; /* the max number driver will try to roaming */
++#endif
++
++#ifdef CONFIG_IOL
++	u8 fw_iol; /* enable iol without other concern */
++#endif
++
++#ifdef CONFIG_80211D
++	u8 enable80211d;
++#endif
++
++	u8 ifname[16];
++	u8 if2name[16];
++
++	u8 notch_filter;
++
++	/* for pll reference clock selction */
++	u8 pll_ref_clk_sel;
++
++	/* define for tx power adjust */
++#if CONFIG_TXPWR_LIMIT
++	u8	RegEnableTxPowerLimit;
++#endif
++	u8	RegEnableTxPowerByRate;
++
++	u8 target_tx_pwr_valid;
++	s8 target_tx_pwr_2g[RF_PATH_MAX][RATE_SECTION_NUM];
++#if CONFIG_IEEE80211_BAND_5GHZ
++	s8 target_tx_pwr_5g[RF_PATH_MAX][RATE_SECTION_NUM - 1];
++#endif
++
++	u8 tsf_update_pause_factor;
++	u8 tsf_update_restore_factor;
++
++	s8	TxBBSwing_2G;
++	s8	TxBBSwing_5G;
++	u8	AmplifierType_2G;
++	u8	AmplifierType_5G;
++	u8	bEn_RFE;
++	u8	RFE_Type;
++	u8	PowerTracking_Type;
++	u8	GLNA_Type;
++	u8  check_fw_ps;
++	u8	RegPwrTrimEnable;
++
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++	u8	load_phy_file;
++	u8	RegDecryptCustomFile;
++#endif
++#ifdef CONFIG_CONCURRENT_MODE
++	u8 virtual_iface_num;
++#ifdef CONFIG_P2P
++	u8 sel_p2p_iface;
++#endif
++#endif
++	u8 qos_opt_enable;
++
++	u8 hiq_filter;
++	u8 adaptivity_en;
++	u8 adaptivity_mode;
++	s8 adaptivity_th_l2h_ini;
++	s8 adaptivity_th_edcca_hl_diff;
++
++	u8 boffefusemask;
++	BOOLEAN bFileMaskEfuse;
++	BOOLEAN bBTFileMaskEfuse;
++#ifdef CONFIG_RTW_ACS
++	u8 acs_auto_scan;
++	u8 acs_mode;
++#endif
++
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++	u8 nm_mode;
++#endif
++	u32	reg_rxgain_offset_2g;
++	u32	reg_rxgain_offset_5gl;
++	u32	reg_rxgain_offset_5gm;
++	u32	reg_rxgain_offset_5gh;
++
++#ifdef CONFIG_DFS_MASTER
++	u8 dfs_region_domain;
++#endif
++
++#ifdef CONFIG_MCC_MODE
++	u8 en_mcc;
++	u32 rtw_mcc_single_tx_cri;
++	u32 rtw_mcc_ap_bw20_target_tx_tp;
++	u32 rtw_mcc_ap_bw40_target_tx_tp;
++	u32 rtw_mcc_ap_bw80_target_tx_tp;
++	u32 rtw_mcc_sta_bw20_target_tx_tp;
++	u32 rtw_mcc_sta_bw40_target_tx_tp;
++	u32 rtw_mcc_sta_bw80_target_tx_tp;
++	s8 rtw_mcc_policy_table_idx;
++	u8 rtw_mcc_duration;
++	u8 rtw_mcc_enable_runtime_duration;
++	u8 rtw_mcc_phydm_offload;
++#endif /* CONFIG_MCC_MODE */
++
++#ifdef CONFIG_RTW_NAPI
++	u8 en_napi;
++#ifdef CONFIG_RTW_NAPI_DYNAMIC
++	u32 napi_threshold;	/* unit: Mbps */
++#endif /* CONFIG_RTW_NAPI_DYNAMIC */
++#ifdef CONFIG_RTW_GRO
++	u8 en_gro;
++#endif /* CONFIG_RTW_GRO */
++#endif /* CONFIG_RTW_NAPI */
++
++#ifdef CONFIG_WOWLAN
++	u8 wowlan_enable;
++	u8 wakeup_event;
++	u8 suspend_type;
++#endif
++
++#ifdef CONFIG_SUPPORT_TRX_SHARED
++	u8 trx_share_mode;
++#endif
++	u8 check_hw_status;
++	u8 wowlan_sta_mix_mode;
++
++#ifdef CONFIG_PCI_HCI
++	u32 pci_aspm_config;
++	u32 pci_dynamic_aspm_linkctrl;
++#endif
++
++	u8 iqk_fw_offload;
++	u8 ch_switch_offload;
++
++#ifdef CONFIG_TDLS
++	u8 en_tdls;
++#endif
++
++#ifdef CONFIG_ADVANCE_OTA
++	u8	adv_ota;
++#endif
++
++#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
++	u8 fw_param_init;
++#endif
++#ifdef CONFIG_DYNAMIC_SOML
++	u8 dyn_soml_en;
++	u8 dyn_soml_train_num;
++	u8 dyn_soml_interval;
++	u8 dyn_soml_period;
++	u8 dyn_soml_delay;
++#endif
++#ifdef CONFIG_FW_HANDLE_TXBCN
++	u8 fw_tbtt_rpt;
++#endif
++
++#ifdef DBG_LA_MODE
++	u8 la_mode_en;
++#endif
++	u32 phydm_ability;
++	u32 halrf_ability;
++#ifdef CONFIG_TDMADIG
++	u8 tdmadig_en;
++	u8 tdmadig_mode;
++	u8 tdmadig_dynamic;
++#endif/*CONFIG_TDMADIG*/
++	u8 en_dyn_rrsr;
++	u32 set_rrsr_value;
++#ifdef CONFIG_RTW_MESH
++	u8 peer_alive_based_preq;
++#endif
++
++#ifdef RTW_BUSY_DENY_SCAN
++	/*
++	 * scan_interval_thr means scan interval threshold which is used to
++	 * judge if user is in scan page or not.
++	 * If scan interval < scan_interval_thr we guess user is in scan page,
++	 * and driver won't deny any scan request at that time.
++	 * Its default value comes from compiler flag
++	 * BUSY_TRAFFIC_SCAN_DENY_PERIOD, and unit is ms.
++	 */
++	u32 scan_interval_thr;
++#endif
++
++#ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY
++	u8 rtw_8822c_xcap_overwrite;
++#endif
++};
++
++/* For registry parameters */
++#define RGTRY_OFT(field) ((u32)FIELD_OFFSET(struct registry_priv, field))
++#define RGTRY_SZ(field)   sizeof(((struct registry_priv *) 0)->field)
++
++#define GetRegAmplifierType2G(_Adapter)	(_Adapter->registrypriv.AmplifierType_2G)
++#define GetRegAmplifierType5G(_Adapter)	(_Adapter->registrypriv.AmplifierType_5G)
++
++#define GetRegTxBBSwing_2G(_Adapter)	(_Adapter->registrypriv.TxBBSwing_2G)
++#define GetRegTxBBSwing_5G(_Adapter)	(_Adapter->registrypriv.TxBBSwing_5G)
++
++#define GetRegbENRFEType(_Adapter)	(_Adapter->registrypriv.bEn_RFE)
++#define GetRegRFEType(_Adapter)	(_Adapter->registrypriv.RFE_Type)
++#define GetRegGLNAType(_Adapter)	(_Adapter->registrypriv.GLNA_Type)
++#define GetRegPowerTrackingType(_Adapter)	(_Adapter->registrypriv.PowerTracking_Type)
++
++#define WOWLAN_IS_STA_MIX_MODE(_Adapter)	(_Adapter->registrypriv.wowlan_sta_mix_mode)
++#define BSSID_OFT(field) ((u32)FIELD_OFFSET(WLAN_BSSID_EX, field))
++#define BSSID_SZ(field)   sizeof(((PWLAN_BSSID_EX) 0)->field)
++
++#define BW_MODE_2G(bw_mode) ((bw_mode) & 0x0F)
++#define BW_MODE_5G(bw_mode) ((bw_mode) >> 4)
++#ifdef CONFIG_80211N_HT
++#define REGSTY_BW_2G(regsty) BW_MODE_2G((regsty)->bw_mode)
++#define REGSTY_BW_5G(regsty) BW_MODE_5G((regsty)->bw_mode)
++#else
++#define REGSTY_BW_2G(regsty) CHANNEL_WIDTH_20
++#define REGSTY_BW_5G(regsty) CHANNEL_WIDTH_20
++#endif
++#define REGSTY_IS_BW_2G_SUPPORT(regsty, bw) (REGSTY_BW_2G((regsty)) >= (bw))
++#define REGSTY_IS_BW_5G_SUPPORT(regsty, bw) (REGSTY_BW_5G((regsty)) >= (bw))
++
++#ifdef CONFIG_80211AC_VHT
++#define REGSTY_IS_11AC_ENABLE(regsty) ((regsty)->vht_enable != 0)
++#define REGSTY_IS_11AC_AUTO(regsty) ((regsty)->vht_enable == 2)
++#else
++#define REGSTY_IS_11AC_ENABLE(regsty) 0
++#define REGSTY_IS_11AC_AUTO(regsty) 0
++#endif
++
++typedef struct rtw_if_operations {
++	int __must_check (*read)(struct dvobj_priv *d, unsigned int addr, void *buf,
++				size_t len, bool fixed);
++	int __must_check (*write)(struct dvobj_priv *d, unsigned int addr, void *buf,
++				 size_t len, bool fixed);
++} RTW_IF_OPS, *PRTW_IF_OPS;
++
++#ifdef CONFIG_SDIO_HCI
++	#include <drv_types_sdio.h>
++	#define INTF_DATA	SDIO_DATA
++	#define INTF_OPS	PRTW_IF_OPS
++#elif defined(CONFIG_GSPI_HCI)
++	#include <drv_types_gspi.h>
++	#define INTF_DATA GSPI_DATA
++#elif defined(CONFIG_PCI_HCI)
++	#include <drv_types_pci.h>
++#endif
++
++#define get_hw_port(adapter) (adapter->hw_port)
++
++#ifdef CONFIG_CONCURRENT_MODE
++	#define is_primary_adapter(adapter) (adapter->adapter_type == PRIMARY_ADAPTER)
++	#define is_vir_adapter(adapter) (adapter->adapter_type == VIRTUAL_ADAPTER)
++#else
++	#define is_primary_adapter(adapter) (1)
++	#define is_vir_adapter(adapter) (0)
++#endif
++#define GET_PRIMARY_ADAPTER(padapter) (((_adapter *)padapter)->dvobj->padapters[IFACE_ID0])
++#define GET_IFACE_NUMS(padapter) (((_adapter *)padapter)->dvobj->iface_nums)
++#define GET_ADAPTER(padapter, iface_id) (((_adapter *)padapter)->dvobj->padapters[iface_id])
++
++#define GetDefaultAdapter(padapter)	padapter
++
++enum _IFACE_ID {
++	IFACE_ID0, /*PRIMARY_ADAPTER*/
++	IFACE_ID1,
++	IFACE_ID2,
++	IFACE_ID3,
++	IFACE_ID4,
++	IFACE_ID5,
++	IFACE_ID6,
++	IFACE_ID7,
++	IFACE_ID_MAX,
++};
++
++#define VIF_START_ID	1
++
++#ifdef CONFIG_DBG_COUNTER
++
++struct rx_logs {
++	u32 intf_rx;
++	u32 intf_rx_err_recvframe;
++	u32 intf_rx_err_skb;
++	u32 intf_rx_report;
++	u32 core_rx;
++	u32 core_rx_pre;
++	u32 core_rx_pre_ver_err;
++	u32 core_rx_pre_mgmt;
++	u32 core_rx_pre_mgmt_err_80211w;
++	u32 core_rx_pre_mgmt_err;
++	u32 core_rx_pre_ctrl;
++	u32 core_rx_pre_ctrl_err;
++	u32 core_rx_pre_data;
++	u32 core_rx_pre_data_wapi_seq_err;
++	u32 core_rx_pre_data_wapi_key_err;
++	u32 core_rx_pre_data_handled;
++	u32 core_rx_pre_data_err;
++	u32 core_rx_pre_data_unknown;
++	u32 core_rx_pre_unknown;
++	u32 core_rx_enqueue;
++	u32 core_rx_dequeue;
++	u32 core_rx_post;
++	u32 core_rx_post_decrypt;
++	u32 core_rx_post_decrypt_wep;
++	u32 core_rx_post_decrypt_tkip;
++	u32 core_rx_post_decrypt_aes;
++	u32 core_rx_post_decrypt_wapi;
++	u32 core_rx_post_decrypt_gcmp;
++	u32 core_rx_post_decrypt_hw;
++	u32 core_rx_post_decrypt_unknown;
++	u32 core_rx_post_decrypt_err;
++	u32 core_rx_post_defrag_err;
++	u32 core_rx_post_portctrl_err;
++	u32 core_rx_post_indicate;
++	u32 core_rx_post_indicate_in_oder;
++	u32 core_rx_post_indicate_reoder;
++	u32 core_rx_post_indicate_err;
++	u32 os_indicate;
++	u32 os_indicate_ap_mcast;
++	u32 os_indicate_ap_forward;
++	u32 os_indicate_ap_self;
++	u32 os_indicate_err;
++	u32 os_netif_ok;
++	u32 os_netif_err;
++};
++
++struct tx_logs {
++	u32 os_tx;
++	u32 os_tx_err_up;
++	u32 os_tx_err_xmit;
++	u32 os_tx_m2u;
++	u32 os_tx_m2u_ignore_fw_linked;
++	u32 os_tx_m2u_ignore_self;
++	u32 os_tx_m2u_entry;
++	u32 os_tx_m2u_entry_err_xmit;
++	u32 os_tx_m2u_entry_err_skb;
++	u32 os_tx_m2u_stop;
++	u32 core_tx;
++	u32 core_tx_err_pxmitframe;
++	u32 core_tx_err_brtx;
++	u32 core_tx_upd_attrib;
++	u32 core_tx_upd_attrib_adhoc;
++	u32 core_tx_upd_attrib_sta;
++	u32 core_tx_upd_attrib_ap;
++	u32 core_tx_upd_attrib_unknown;
++	u32 core_tx_upd_attrib_dhcp;
++	u32 core_tx_upd_attrib_icmp;
++	u32 core_tx_upd_attrib_active;
++	u32 core_tx_upd_attrib_err_ucast_sta;
++	u32 core_tx_upd_attrib_err_ucast_ap_link;
++	u32 core_tx_upd_attrib_err_sta;
++	u32 core_tx_upd_attrib_err_link;
++	u32 core_tx_upd_attrib_err_sec;
++	u32 core_tx_ap_enqueue_warn_fwstate;
++	u32 core_tx_ap_enqueue_warn_sta;
++	u32 core_tx_ap_enqueue_warn_nosta;
++	u32 core_tx_ap_enqueue_warn_link;
++	u32 core_tx_ap_enqueue_warn_trigger;
++	u32 core_tx_ap_enqueue_mcast;
++	u32 core_tx_ap_enqueue_ucast;
++	u32 core_tx_ap_enqueue;
++	u32 intf_tx;
++	u32 intf_tx_pending_ac;
++	u32 intf_tx_pending_fw_under_survey;
++	u32 intf_tx_pending_fw_under_linking;
++	u32 intf_tx_pending_xmitbuf;
++	u32 intf_tx_enqueue;
++	u32 core_tx_enqueue;
++	u32 core_tx_enqueue_class;
++	u32 core_tx_enqueue_class_err_sta;
++	u32 core_tx_enqueue_class_err_nosta;
++	u32 core_tx_enqueue_class_err_fwlink;
++	u32 intf_tx_direct;
++	u32 intf_tx_direct_err_coalesce;
++	u32 intf_tx_dequeue;
++	u32 intf_tx_dequeue_err_coalesce;
++	u32 intf_tx_dump_xframe;
++	u32 intf_tx_dump_xframe_err_txdesc;
++	u32 intf_tx_dump_xframe_err_port;
++};
++
++struct int_logs {
++	u32 all;
++	u32 err;
++	u32 tbdok;
++	u32 tbder;
++	u32 bcnderr;
++	u32 bcndma;
++	u32 bcndma_e;
++	u32 rx;
++	u32 rx_rdu;
++	u32 rx_fovw;
++	u32 txfovw;
++	u32 mgntok;
++	u32 highdok;
++	u32 bkdok;
++	u32 bedok;
++	u32 vidok;
++	u32 vodok;
++};
++
++#endif /* CONFIG_DBG_COUNTER */
++
++struct debug_priv {
++	u32 dbg_sdio_free_irq_error_cnt;
++	u32 dbg_sdio_alloc_irq_error_cnt;
++	u32 dbg_sdio_free_irq_cnt;
++	u32 dbg_sdio_alloc_irq_cnt;
++	u32 dbg_sdio_deinit_error_cnt;
++	u32 dbg_sdio_init_error_cnt;
++	u32 dbg_suspend_error_cnt;
++	u32 dbg_suspend_cnt;
++	u32 dbg_resume_cnt;
++	u32 dbg_resume_error_cnt;
++	u32 dbg_deinit_fail_cnt;
++	u32 dbg_carddisable_cnt;
++	u32 dbg_carddisable_error_cnt;
++	u32 dbg_ps_insuspend_cnt;
++	u32	dbg_dev_unload_inIPS_cnt;
++	u32 dbg_wow_leave_ps_fail_cnt;
++	u32 dbg_scan_pwr_state_cnt;
++	u32 dbg_downloadfw_pwr_state_cnt;
++	u32 dbg_fw_read_ps_state_fail_cnt;
++	u32 dbg_leave_ips_fail_cnt;
++	u32 dbg_leave_lps_fail_cnt;
++	u32 dbg_h2c_leave32k_fail_cnt;
++	u32 dbg_diswow_dload_fw_fail_cnt;
++	u32 dbg_enwow_dload_fw_fail_cnt;
++	u32 dbg_ips_drvopen_fail_cnt;
++	u32 dbg_poll_fail_cnt;
++	u32 dbg_rpwm_toogle_cnt;
++	u32 dbg_rpwm_timeout_fail_cnt;
++	u32 dbg_sreset_cnt;
++	u32 dbg_fw_mem_dl_error_cnt;
++	u64 dbg_rx_fifo_last_overflow;
++	u64 dbg_rx_fifo_curr_overflow;
++	u64 dbg_rx_fifo_diff_overflow;
++};
++
++struct rtw_traffic_statistics {
++	/* tx statistics */
++	u64	tx_bytes;
++	u64	tx_pkts;
++	u64	tx_drop;
++	u64	cur_tx_bytes;
++	u64	last_tx_bytes;
++	u32	cur_tx_tp; /* Tx throughput in Mbps. */
++
++	/* rx statistics */
++	u64	rx_bytes;
++	u64	rx_pkts;
++	u64	rx_drop;
++	u64	cur_rx_bytes;
++	u64	last_rx_bytes;
++	u32	cur_rx_tp; /* Rx throughput in Mbps. */
++};
++
++#define SEC_CAP_CHK_BMC	BIT0
++#define SEC_CAP_CHK_EXTRA_SEC	BIT1 /* 256 bit */
++
++#define MACID_DROP BIT0
++#define MACID_DROP_INDIRECT BIT1
++
++#define SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH	BIT0
++
++struct sec_cam_bmp {
++	u32 m0;
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
++	u32 m1;
++#endif
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
++	u32 m2;
++#endif
++#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
++	u32 m3;
++#endif
++};
++
++struct cam_ctl_t {
++	_lock lock;
++
++	u8 sec_cap;
++	u32 flags;
++
++	u8 num;
++	struct sec_cam_bmp used;
++
++	_mutex sec_cam_access_mutex;
++};
++
++struct sec_cam_ent {
++	u16 ctrl;
++	u8 mac[ETH_ALEN];
++	u8 key[16];
++};
++
++#define KEY_FMT "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
++#define KEY_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \
++	((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9], ((u8 *)(x))[10], ((u8 *)(x))[11], \
++	((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15]
++
++#define RTW_DEFAULT_MGMT_MACID 1
++
++struct macid_bmp {
++	u32 m0;
++#if (MACID_NUM_SW_LIMIT > 32)
++	u32 m1;
++#endif
++#if (MACID_NUM_SW_LIMIT > 64)
++	u32 m2;
++#endif
++#if (MACID_NUM_SW_LIMIT > 96)
++	u32 m3;
++#endif
++};
++
++#ifdef CONFIG_CLIENT_PORT_CFG
++struct clt_port_t{
++	_lock lock;
++	u8 bmp;
++	s8 num;
++};
++#define get_clt_num(adapter) (adapter_to_dvobj(adapter)->clt_port.num)
++#endif
++
++struct macid_ctl_t {
++	_lock lock;
++	u8 num;
++	struct macid_bmp used;
++	struct macid_bmp bmc;
++	struct macid_bmp if_g[CONFIG_IFACE_NUMBER];
++	struct macid_bmp ch_g[2]; /* 2 ch concurrency */
++
++	u8 iface_bmc[CONFIG_IFACE_NUMBER]; /* bmc TX macid for each iface*/
++
++	u8 h2c_msr[MACID_NUM_SW_LIMIT];
++	u8 bw[MACID_NUM_SW_LIMIT];
++	u8 vht_en[MACID_NUM_SW_LIMIT];
++	u32 rate_bmp0[MACID_NUM_SW_LIMIT];
++	u32 rate_bmp1[MACID_NUM_SW_LIMIT];
++	u8 op_num[H2C_MSR_ROLE_MAX]; /* number of macid having h2c_msr's OPMODE = 1 for specific ROLE */
++
++	struct sta_info *sta[MACID_NUM_SW_LIMIT]; /* corresponding stainfo when macid is not shared */
++
++	u8 macid_cap;
++	/* macid sleep registers */
++#ifdef CONFIG_PROTSEL_MACSLEEP
++	u16 reg_sleep_ctrl;
++	u16 reg_sleep_info;
++	u16 reg_drop_ctrl;
++	u16 reg_drop_info;
++#else
++	u16 reg_sleep_m0;
++	u16 reg_drop_m0;
++#if (MACID_NUM_SW_LIMIT > 32)
++	u16 reg_sleep_m1;
++	u16 reg_drop_m1;
++#endif
++#if (MACID_NUM_SW_LIMIT > 64)
++	u16 reg_sleep_m2;
++	u16 reg_drop_m2;
++#endif
++#if (MACID_NUM_SW_LIMIT > 96)
++	u16 reg_sleep_m3;
++	u16 reg_drop_m3;
++#endif
++#endif
++	u16 macid_txrpt;
++	u8 macid_txrpt_pgsz;
++};
++
++/* used for rf_ctl_t.rate_bmp_cck_ofdm */
++#define RATE_BMP_CCK		0x000F
++#define RATE_BMP_OFDM		0xFFF0
++#define RATE_BMP_HAS_CCK(_bmp_cck_ofdm)		(_bmp_cck_ofdm & RATE_BMP_CCK)
++#define RATE_BMP_HAS_OFDM(_bmp_cck_ofdm)	(_bmp_cck_ofdm & RATE_BMP_OFDM)
++#define RATE_BMP_GET_CCK(_bmp_cck_ofdm)		(_bmp_cck_ofdm & RATE_BMP_CCK)
++#define RATE_BMP_GET_OFDM(_bmp_cck_ofdm)	((_bmp_cck_ofdm & RATE_BMP_OFDM) >> 4)
++
++/* used for rf_ctl_t.rate_bmp_ht_by_bw */
++#define RATE_BMP_HT_1SS		0x000000FF
++#define RATE_BMP_HT_2SS		0x0000FF00
++#define RATE_BMP_HT_3SS		0x00FF0000
++#define RATE_BMP_HT_4SS		0xFF000000
++#define RATE_BMP_HAS_HT_1SS(_bmp_ht)		(_bmp_ht & RATE_BMP_HT_1SS)
++#define RATE_BMP_HAS_HT_2SS(_bmp_ht)		(_bmp_ht & RATE_BMP_HT_2SS)
++#define RATE_BMP_HAS_HT_3SS(_bmp_ht)		(_bmp_ht & RATE_BMP_HT_3SS)
++#define RATE_BMP_HAS_HT_4SS(_bmp_ht)		(_bmp_ht & RATE_BMP_HT_4SS)
++#define RATE_BMP_GET_HT_1SS(_bmp_ht)		(_bmp_ht & RATE_BMP_HT_1SS)
++#define RATE_BMP_GET_HT_2SS(_bmp_ht)		((_bmp_ht & RATE_BMP_HT_2SS) >> 8)
++#define RATE_BMP_GET_HT_3SS(_bmp_ht)		((_bmp_ht & RATE_BMP_HT_3SS) >> 16)
++#define RATE_BMP_GET_HT_4SS(_bmp_ht)		((_bmp_ht & RATE_BMP_HT_4SS) >> 24)
++
++/* used for rf_ctl_t.rate_bmp_vht_by_bw */
++#define RATE_BMP_VHT_1SS	0x00000003FF
++#define RATE_BMP_VHT_2SS	0x00000FFC00
++#define RATE_BMP_VHT_3SS	0x003FF00000
++#define RATE_BMP_VHT_4SS	0xFFC0000000
++#define RATE_BMP_HAS_VHT_1SS(_bmp_vht)		(_bmp_vht & RATE_BMP_VHT_1SS)
++#define RATE_BMP_HAS_VHT_2SS(_bmp_vht)		(_bmp_vht & RATE_BMP_VHT_2SS)
++#define RATE_BMP_HAS_VHT_3SS(_bmp_vht)		(_bmp_vht & RATE_BMP_VHT_3SS)
++#define RATE_BMP_HAS_VHT_4SS(_bmp_vht)		(_bmp_vht & RATE_BMP_VHT_4SS)
++#define RATE_BMP_GET_VHT_1SS(_bmp_vht)		((u16)(_bmp_vht & RATE_BMP_VHT_1SS))
++#define RATE_BMP_GET_VHT_2SS(_bmp_vht)		((u16)((_bmp_vht & RATE_BMP_VHT_2SS) >> 10))
++#define RATE_BMP_GET_VHT_3SS(_bmp_vht)		((u16)((_bmp_vht & RATE_BMP_VHT_3SS) >> 20))
++#define RATE_BMP_GET_VHT_4SS(_bmp_vht)		((u16)((_bmp_vht & RATE_BMP_VHT_4SS) >> 30))
++
++#define TXPWR_LMT_REF_VHT_FROM_HT	BIT0
++#define TXPWR_LMT_REF_HT_FROM_VHT	BIT1
++
++#define TXPWR_LMT_HAS_CCK_1T	BIT0
++#define TXPWR_LMT_HAS_CCK_2T	BIT1
++#define TXPWR_LMT_HAS_CCK_3T	BIT2
++#define TXPWR_LMT_HAS_CCK_4T	BIT3
++#define TXPWR_LMT_HAS_OFDM_1T	BIT4
++#define TXPWR_LMT_HAS_OFDM_2T	BIT5
++#define TXPWR_LMT_HAS_OFDM_3T	BIT6
++#define TXPWR_LMT_HAS_OFDM_4T	BIT7
++
++#define OFFCHS_NONE			0
++#define OFFCHS_LEAVING_OP	1
++#define OFFCHS_LEAVE_OP		2
++#define OFFCHS_BACKING_OP	3
++
++struct rf_ctl_t {
++	const struct country_chplan *country_ent;
++	u8 ChannelPlan;
++	u8 max_chan_nums;
++	RT_CHANNEL_INFO channel_set[MAX_CHANNEL_NUM];
++	u32 cap_spt_op_class_ch_bmp[RTW_GLOBAL_OP_CLASS_NUM];
++	u8 cap_spt_op_class_num;
++	u32 cur_spt_op_class_ch_bmp[RTW_GLOBAL_OP_CLASS_NUM];
++	u8 cur_spt_op_class_num;
++	struct p2p_channels channel_list;
++#ifdef CONFIG_RTW_MBO
++	struct npref_ch_rtp ch_rtp;
++#endif
++
++	_mutex offch_mutex;
++	u8 offch_state;
++
++	/* used for debug or by tx power limit */
++	u16 rate_bmp_cck_ofdm;		/* 20MHz */
++	u32 rate_bmp_ht_by_bw[2];	/* 20MHz, 40MHz. 4SS supported */
++	u64 rate_bmp_vht_by_bw[4];	/* 20MHz, 40MHz, 80MHz, 160MHz. 4SS supported */
++
++#if CONFIG_TXPWR_LIMIT
++	u8 highest_ht_rate_bw_bmp;
++	u8 highest_vht_rate_bw_bmp;
++
++	_mutex txpwr_lmt_mutex;
++	_list reg_exc_list;
++	u8 regd_exc_num;
++	_list txpwr_lmt_list;
++	u8 txpwr_regd_num;
++	const char *regd_name;
++
++	u8 txpwr_lmt_2g_cck_ofdm_state;
++	#if CONFIG_IEEE80211_BAND_5GHZ
++	u8 txpwr_lmt_5g_cck_ofdm_state;
++	u8 txpwr_lmt_5g_20_40_ref;
++	#endif
++#endif
++
++	bool ch_sel_within_same_band;
++
++#if CONFIG_DFS
++	u8 csa_ch;
++
++#ifdef CONFIG_DFS_MASTER
++	u8 dfs_region_domain;
++	_timer radar_detect_timer;
++	bool radar_detect_by_others;
++	u8 radar_detect_enabled;
++	bool radar_detected;
++
++	u8 radar_detect_ch;
++	u8 radar_detect_bw;
++	u8 radar_detect_offset;
++
++	systime cac_start_time;
++	systime cac_end_time;
++	u8 cac_force_stop;
++
++#if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
++	u8 dfs_slave_with_rd;
++#endif
++	u8 dfs_ch_sel_d_flags;
++
++	u8 dbg_dfs_fake_radar_detect_cnt;
++	u8 dbg_dfs_radar_detect_trigger_non;
++	u8 dbg_dfs_choose_dfs_ch_first;
++#endif /* CONFIG_DFS_MASTER */
++#endif /* CONFIG_DFS */
++};
++
++struct wow_ctl_t {
++	u8 wow_cap;
++};
++
++#define WOW_CAP_TKIP_OL BIT0
++
++#define RTW_CAC_STOPPED 0
++#ifdef CONFIG_DFS_MASTER
++#define IS_CAC_STOPPED(rfctl) ((rfctl)->cac_end_time == RTW_CAC_STOPPED)
++#define IS_CH_WAITING(rfctl) (!IS_CAC_STOPPED(rfctl) && rtw_time_after((rfctl)->cac_end_time, rtw_get_current_time()))
++#define IS_UNDER_CAC(rfctl) (IS_CH_WAITING(rfctl) && rtw_time_after(rtw_get_current_time(), (rfctl)->cac_start_time))
++#define IS_RADAR_DETECTED(rfctl) ((rfctl)->radar_detected)
++#else
++#define IS_CAC_STOPPED(rfctl) 1
++#define IS_CH_WAITING(rfctl) 0
++#define IS_UNDER_CAC(rfctl) 0
++#define IS_RADAR_DETECTED(rfctl) 0
++#endif /* CONFIG_DFS_MASTER */
++
++#if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
++#define IS_DFS_SLAVE_WITH_RD(rfctl) ((rfctl)->dfs_slave_with_rd)
++#else
++#define IS_DFS_SLAVE_WITH_RD(rfctl) 0
++#endif
++
++#ifdef CONFIG_MBSSID_CAM
++#define TOTAL_MBID_CAM_NUM	8
++#define INVALID_CAM_ID			0xFF
++struct mbid_cam_ctl_t {
++	_lock lock;
++	u8 bitmap;
++	ATOMIC_T mbid_entry_num;
++};
++struct mbid_cam_cache {
++	u8 iface_id;
++	/*u8 role;*/ /*WIFI_STATION_STATE or WIFI_AP_STATE*/
++	u8 mac_addr[ETH_ALEN];
++};
++#endif /*CONFIG_MBSSID_CAM*/
++
++#ifdef RTW_HALMAC
++struct halmac_indicator {
++	struct submit_ctx *sctx;
++	u8 *buffer;
++	u32 buf_size;
++	u32 ret_size;
++	u32 status;
++};
++
++struct halmacpriv {
++	/* flags */
++#ifdef CONFIG_SDIO_HCI
++	/*
++	 * Indirect Access for SDIO,
++	 * 0:default, 1:enable, 2:disable
++	 */
++	u8 sdio_io_indir;
++#endif /* CONFIG_SDIO_HCI */
++
++	/* For asynchronous functions */
++	struct halmac_indicator *indicator;
++
++	/* Hardware parameters */
++#ifdef CONFIG_SDIO_HCI
++	/* Store hardware tx queue page number setting */
++	u16 txpage[HW_QUEUE_ENTRY];
++#endif /* CONFIG_SDIO_HCI */
++};
++#endif /* RTW_HALMAC */
++
++#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++/*info for H2C-0x2C*/
++struct dft_info {
++	u8 port_id;
++	u8 mac_id;
++};
++#endif
++
++#ifdef CONFIG_HW_P0_TSF_SYNC
++struct tsf_info {
++	u8 sync_port;/*port_x's tsf sync to port_0*/
++	u8 offset; /*tsf timer offset*/
++};
++#endif
++
++struct protsel {
++	_mutex mutex;		/* protect this structure */
++	ATOMIC_T refcnt;	/* reference count */
++	u32 sel;		/* save the last sel port */
++};
++
++#ifdef CONFIG_RTL8814B
++#define MAX_BULKOUT_NUM 7
++#ifdef CONFIG_USB_HCI
++#define MAX_ENDPOINT_NUM 8
++#endif
++#else
++#define MAX_BULKOUT_NUM 4
++#ifdef CONFIG_USB_HCI
++#define MAX_ENDPOINT_NUM 6
++#endif
++#endif
++
++struct dvobj_priv {
++	/*-------- below is common data --------*/
++	u8	chip_type;
++	u8	HardwareType;
++	u8	interface_type;/*USB,SDIO,SPI,PCI*/
++
++	ATOMIC_T	bSurpriseRemoved;
++	ATOMIC_T	bDriverStopped;
++
++	s32	processing_dev_remove;
++
++	struct debug_priv drv_dbg;
++
++	_mutex hw_init_mutex;
++	_mutex h2c_fwcmd_mutex;
++
++	_mutex ioctrl_mutex;
++
++#ifdef CONFIG_RTW_CUSTOMER_STR
++	_mutex customer_str_mutex;
++	struct submit_ctx *customer_str_sctx;
++	u8 customer_str[RTW_CUSTOMER_STR_LEN];
++#endif
++
++	_mutex setch_mutex;
++	_mutex setbw_mutex;
++	_mutex rf_read_reg_mutex;
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++	_mutex sd_indirect_access_mutex;
++#endif
++
++#ifdef CONFIG_SYSON_INDIRECT_ACCESS
++	_mutex syson_indirect_access_mutex;	/* System On Reg R/W */
++#endif
++
++	unsigned char	oper_channel; /* saved channel info when call set_channel_bw */
++	unsigned char	oper_bwmode;
++	unsigned char	oper_ch_offset;/* PRIME_CHNL_OFFSET */
++	systime on_oper_ch_time;
++
++	_adapter *padapters[CONFIG_IFACE_NUMBER];/*IFACE_ID_MAX*/
++	u8 iface_nums; /* total number of ifaces used runtime */
++	struct mi_state iface_state;
++
++#ifdef CONFIG_AP_MODE
++	#ifdef CONFIG_SUPPORT_MULTI_BCN
++	u8		nr_ap_if; /* total interface number of ap /go /mesh / nan mode. */
++	u16		inter_bcn_space; /* unit:ms */
++	_queue	ap_if_q;
++	u8		vap_map;
++	u8		fw_bcn_offload;
++	u8		vap_tbtt_rpt_map;
++	#endif /*CONFIG_SUPPORT_MULTI_BCN*/
++	#ifdef CONFIG_RTW_REPEATER_SON
++	struct rtw_rson_struct  rson_data;
++	#endif
++#endif
++#ifdef CONFIG_CLIENT_PORT_CFG
++	struct clt_port_t clt_port;
++#endif
++
++#ifdef CONFIG_HW_P0_TSF_SYNC
++	struct tsf_info p0_tsf;
++#endif
++	systime periodic_tsf_update_etime;
++	_timer periodic_tsf_update_end_timer;
++
++	struct macid_ctl_t macid_ctl;
++
++	struct cam_ctl_t cam_ctl;
++	struct sec_cam_ent cam_cache[SEC_CAM_ENT_NUM_SW_LIMIT];
++	
++	struct wow_ctl_t wow_ctl;
++
++#ifdef CONFIG_MBSSID_CAM
++	struct mbid_cam_ctl_t mbid_cam_ctl;
++	struct mbid_cam_cache mbid_cam_cache[TOTAL_MBID_CAM_NUM];
++#endif
++
++	struct rf_ctl_t rf_ctl;
++
++#if CONFIG_TX_AC_LIFETIME
++	struct tx_aclt_conf_t tx_aclt_force_val;
++	u8 tx_aclt_flags;
++	struct tx_aclt_conf_t tx_aclt_confs[TX_ACLT_CONF_NUM];
++#endif
++
++	/* In /Out Pipe information */
++	int	RtInPipe[2];
++	int	RtOutPipe[MAX_BULKOUT_NUM];
++	u8	Queue2Pipe[HW_QUEUE_ENTRY];/* for out pipe mapping */
++
++	u8	irq_alloc;
++	ATOMIC_T continual_io_error;
++
++	ATOMIC_T disable_func;
++
++	u8 xmit_block;
++	_lock xmit_block_lock;
++
++	struct pwrctrl_priv pwrctl_priv;
++
++	struct rtw_traffic_statistics	traffic_stat;
++
++#ifdef PLATFORM_LINUX
++	_thread_hdl_ rtnl_lock_holder;
++
++	#if defined(CONFIG_IOCTL_CFG80211) && defined(RTW_SINGLE_WIPHY)
++	struct wiphy *wiphy;
++	#endif
++#endif /* PLATFORM_LINUX */
++
++#ifdef CONFIG_SWTIMER_BASED_TXBCN
++	_timer txbcn_timer;
++#endif
++	_timer dynamic_chk_timer; /* dynamic/periodic check timer */
++	
++#ifdef CONFIG_RTW_NAPI_DYNAMIC
++	u8 en_napi_dynamic;
++#endif /* CONFIG_RTW_NAPI_DYNAMIC */
++
++#ifdef RTW_HALMAC
++	void *halmac;
++	struct halmacpriv hmpriv;
++#endif /* RTW_HALMAC */
++
++#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++	/*info for H2C-0x2C*/
++	struct dft_info dft;
++#endif
++
++#ifdef CONFIG_RTW_WIFI_HAL
++	u32 nodfs;
++#endif
++
++	/*-------- below is for SDIO INTERFACE --------*/
++
++#ifdef INTF_DATA
++	INTF_DATA intf_data;
++#endif
++#ifdef INTF_OPS
++	INTF_OPS intf_ops;
++#endif
++
++#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
++	u8 tx_aval_int_thr_mode;/* if 0=>threhold set by reques(default) ;if 1=>fixed by proc; if 2: fixed by sdio_tx_max_len */
++	u8 tx_aval_int_thr_value;
++#endif/*CONFIG_SDIO_TX_ENABLE_AVAL_INT*/
++
++	/*-------- below is for USB INTERFACE --------*/
++
++#ifdef CONFIG_USB_HCI
++
++	u8	usb_speed; /* 1.1, 2.0 or 3.0 */
++	u8	nr_endpoint;
++	u8	RtNumInPipes;
++	u8	RtNumOutPipes;
++	int	ep_num[MAX_ENDPOINT_NUM]; /* endpoint number */
++
++	int	RegUsbSS;
++
++	_sema	usb_suspend_sema;
++
++#ifdef CONFIG_USB_VENDOR_REQ_MUTEX
++	_mutex  usb_vendor_req_mutex;
++#endif
++
++#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC
++	u8 *usb_alloc_vendor_req_buf;
++	u8 *usb_vendor_req_buf;
++#endif
++
++#ifdef PLATFORM_LINUX
++	struct usb_interface *pusbintf;
++	struct usb_device *pusbdev;
++#endif/* PLATFORM_LINUX */
++
++#ifdef PLATFORM_FREEBSD
++	struct usb_interface *pusbintf;
++	struct usb_device *pusbdev;
++#endif/* PLATFORM_FREEBSD */
++
++#endif/* CONFIG_USB_HCI */
++
++	/*-------- below is for PCIE INTERFACE --------*/
++
++#ifdef CONFIG_PCI_HCI
++
++#ifdef PLATFORM_LINUX
++	struct pci_dev *ppcidev;
++
++	/* PCI MEM map */
++	unsigned long	pci_mem_end;	/* shared mem end	*/
++	unsigned long	pci_mem_start;	/* shared mem start	*/
++
++	/* PCI IO map */
++	unsigned long	pci_base_addr;	/* device I/O address	*/
++
++#ifdef RTK_129X_PLATFORM
++	unsigned long	ctrl_start;
++	/* PCI MASK addr */
++	unsigned long	mask_addr;
++
++	/* PCI TRANSLATE addr */
++	unsigned long	tran_addr;
++
++	_lock   io_reg_lock;
++#endif
++
++	/* PciBridge */
++	struct pci_priv	pcipriv;
++
++	unsigned int irq; /* get from pci_dev.irq, store to net_device.irq */
++	u16	irqline;
++	u8	irq_enabled;
++	RT_ISR_CONTENT	isr_content;
++	_lock	irq_th_lock;
++
++	u8	bdma64;
++#endif/* PLATFORM_LINUX */
++
++#endif/* CONFIG_PCI_HCI */
++
++#ifdef CONFIG_MCC_MODE
++	struct mcc_obj_priv mcc_objpriv;
++#endif /*CONFIG_MCC_MODE */
++
++#ifdef CONFIG_RTW_TPT_MODE
++	u8 tpt_mode; /* RTK T/P Testing Mode, 0:default mode */
++	u32 edca_be_ul;
++	u32 edca_be_dl;
++#endif 
++	/* also for RTK T/P Testing Mode */ 
++	u8 scan_deny;
++
++	/* protect sel to safely access */
++#ifdef CONFIG_PROTSEL_PORT
++	struct protsel protsel_port;
++#endif
++#ifdef CONFIG_PROTSEL_ATIMDTIM
++	struct protsel protsel_atimdtim;
++#endif
++#ifdef CONFIG_PROTSEL_MACSLEEP
++	struct protsel protsel_macsleep;
++#endif
++#ifdef CONFIG_WOWLAN
++	u8  bcn_ctrl_clint3_bf_suspend;
++	u16 rxfltmap2_bf_suspend;
++	u8	lifetime_en;
++	u32	pkt_lifetime;
++	u32 rcr_bf_suspend;
++	u32 cr_ext_bf_suspend;
++#endif /* CONFIG_WOWLAN */
++};
++
++#define DEV_STA_NUM(_dvobj)			MSTATE_STA_NUM(&((_dvobj)->iface_state))
++#define DEV_STA_LD_NUM(_dvobj)		MSTATE_STA_LD_NUM(&((_dvobj)->iface_state))
++#define DEV_STA_LG_NUM(_dvobj)		MSTATE_STA_LG_NUM(&((_dvobj)->iface_state))
++#define DEV_TDLS_LD_NUM(_dvobj)		MSTATE_TDLS_LD_NUM(&((_dvobj)->iface_state))
++#define DEV_AP_NUM(_dvobj)			MSTATE_AP_NUM(&((_dvobj)->iface_state))
++#define DEV_AP_STARTING_NUM(_dvobj)	MSTATE_AP_STARTING_NUM(&((_dvobj)->iface_state))
++#define DEV_AP_LD_NUM(_dvobj)		MSTATE_AP_LD_NUM(&((_dvobj)->iface_state))
++#define DEV_ADHOC_NUM(_dvobj)		MSTATE_ADHOC_NUM(&((_dvobj)->iface_state))
++#define DEV_ADHOC_LD_NUM(_dvobj)	MSTATE_ADHOC_LD_NUM(&((_dvobj)->iface_state))
++#define DEV_MESH_NUM(_dvobj)		MSTATE_MESH_NUM(&((_dvobj)->iface_state))
++#define DEV_MESH_LD_NUM(_dvobj)		MSTATE_MESH_LD_NUM(&((_dvobj)->iface_state))
++#define DEV_P2P_DV_NUM(_dvobj)		MSTATE_P2P_DV_NUM(&((_dvobj)->iface_state))
++#define DEV_P2P_GC_NUM(_dvobj)		MSTATE_P2P_GC_NUM(&((_dvobj)->iface_state))
++#define DEV_P2P_GO_NUM(_dvobj)		MSTATE_P2P_GO_NUM(&((_dvobj)->iface_state))
++#define DEV_SCAN_NUM(_dvobj)		MSTATE_SCAN_NUM(&((_dvobj)->iface_state))
++#define DEV_WPS_NUM(_dvobj)			MSTATE_WPS_NUM(&((_dvobj)->iface_state))
++#define DEV_ROCH_NUM(_dvobj)		MSTATE_ROCH_NUM(&((_dvobj)->iface_state))
++#define DEV_MGMT_TX_NUM(_dvobj)		MSTATE_MGMT_TX_NUM(&((_dvobj)->iface_state))
++#define DEV_U_CH(_dvobj)			MSTATE_U_CH(&((_dvobj)->iface_state))
++#define DEV_U_BW(_dvobj)			MSTATE_U_BW(&((_dvobj)->iface_state))
++#define DEV_U_OFFSET(_dvobj)		MSTATE_U_OFFSET(&((_dvobj)->iface_state))
++
++#define dvobj_to_pwrctl(dvobj) (&(dvobj->pwrctl_priv))
++#define pwrctl_to_dvobj(pwrctl) container_of(pwrctl, struct dvobj_priv, pwrctl_priv)
++#define dvobj_to_macidctl(dvobj) (&(dvobj->macid_ctl))
++#define dvobj_to_sec_camctl(dvobj) (&(dvobj->cam_ctl))
++#define dvobj_to_regsty(dvobj) (&(dvobj->padapters[IFACE_ID0]->registrypriv))
++#if defined(CONFIG_IOCTL_CFG80211) && defined(RTW_SINGLE_WIPHY)
++#define dvobj_to_wiphy(dvobj) ((dvobj)->wiphy)
++#endif
++#define dvobj_to_rfctl(dvobj) (&(dvobj->rf_ctl))
++#define rfctl_to_dvobj(rfctl) container_of((rfctl), struct dvobj_priv, rf_ctl)
++
++static inline void dev_set_surprise_removed(struct dvobj_priv *dvobj)
++{
++	ATOMIC_SET(&dvobj->bSurpriseRemoved, _TRUE);
++}
++static inline void dev_clr_surprise_removed(struct dvobj_priv *dvobj)
++{
++	ATOMIC_SET(&dvobj->bSurpriseRemoved, _FALSE);
++}
++static inline void dev_set_drv_stopped(struct dvobj_priv *dvobj)
++{
++	ATOMIC_SET(&dvobj->bDriverStopped, _TRUE);
++}
++static inline void dev_clr_drv_stopped(struct dvobj_priv *dvobj)
++{
++	ATOMIC_SET(&dvobj->bDriverStopped, _FALSE);
++}
++#define dev_is_surprise_removed(dvobj)	(ATOMIC_READ(&dvobj->bSurpriseRemoved) == _TRUE)
++#define dev_is_drv_stopped(dvobj)		(ATOMIC_READ(&dvobj->bDriverStopped) == _TRUE)
++
++#ifdef PLATFORM_LINUX
++static inline struct device *dvobj_to_dev(struct dvobj_priv *dvobj)
++{
++	/* todo: get interface type from dvobj and the return the dev accordingly */
++#ifdef RTW_DVOBJ_CHIP_HW_TYPE
++#endif
++
++#ifdef CONFIG_USB_HCI
++	return &dvobj->pusbintf->dev;
++#endif
++#ifdef CONFIG_SDIO_HCI
++	return &dvobj->intf_data.func->dev;
++#endif
++#ifdef CONFIG_GSPI_HCI
++	return &dvobj->intf_data.func->dev;
++#endif
++#ifdef CONFIG_PCI_HCI
++	return &dvobj->ppcidev->dev;
++#endif
++}
++#endif
++
++_adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj);
++_adapter *dvobj_get_unregisterd_adapter(struct dvobj_priv *dvobj);
++_adapter *dvobj_get_adapter_by_addr(struct dvobj_priv *dvobj, u8 *addr);
++#define dvobj_get_primary_adapter(dvobj)	((dvobj)->padapters[IFACE_ID0])
++
++enum _hw_port {
++	HW_PORT0,
++	HW_PORT1,
++	HW_PORT2,
++	HW_PORT3,
++	HW_PORT4,
++	MAX_HW_PORT,
++};
++
++#ifdef CONFIG_CLIENT_PORT_CFG
++enum _client_port {
++	CLT_PORT0 = HW_PORT1,
++	CLT_PORT1 = HW_PORT2,
++	CLT_PORT2 = HW_PORT3,
++	CLT_PORT3 = HW_PORT4,
++	CLT_PORT_INVALID = HW_PORT0,
++};
++
++#define MAX_CLIENT_PORT_NUM	4
++#define get_clt_port(adapter) (adapter->client_port)
++#endif
++
++enum _ADAPTER_TYPE {
++	PRIMARY_ADAPTER,
++	VIRTUAL_ADAPTER,
++	MAX_ADAPTER = 0xFF,
++};
++
++typedef enum _DRIVER_STATE {
++	DRIVER_NORMAL = 0,
++	DRIVER_DISAPPEAR = 1,
++	DRIVER_REPLACE_DONGLE = 2,
++} DRIVER_STATE;
++
++#ifdef CONFIG_RTW_NAPI
++enum _NAPI_STATE {
++	NAPI_DISABLE = 0,
++	NAPI_ENABLE = 1,
++};
++#endif
++
++#ifdef CONFIG_MAC_LOOPBACK_DRIVER
++typedef struct loopbackdata {
++	_sema	sema;
++	_thread_hdl_ lbkthread;
++	u8 bstop;
++	u32 cnt;
++	u16 size;
++	u16 txsize;
++	u8 txbuf[0x8000];
++	u16 rxsize;
++	u8 rxbuf[0x8000];
++	u8 msg[100];
++
++} LOOPBACKDATA, *PLOOPBACKDATA;
++#endif
++
++#define ADAPTER_TX_BW_2G(adapter) BW_MODE_2G((adapter)->driver_tx_bw_mode)
++#define ADAPTER_TX_BW_5G(adapter) BW_MODE_5G((adapter)->driver_tx_bw_mode)
++
++struct _ADAPTER {
++	int	DriverState;/* for disable driver using module, use dongle to replace module. */
++	int	pid[3];/* process id from UI, 0:wps, 1:hostapd, 2:dhcpcd */
++	int	bDongle;/* build-in module or external dongle */
++
++	#if defined(CONFIG_AP_MODE) && defined(CONFIG_SUPPORT_MULTI_BCN)
++	_list	list;
++	u8 vap_id;
++	#endif
++	struct dvobj_priv *dvobj;
++	struct	mlme_priv mlmepriv;
++	struct	mlme_ext_priv mlmeextpriv;
++	struct	cmd_priv	cmdpriv;
++	struct	evt_priv	evtpriv;
++
++#ifdef CONFIG_RTW_80211K
++	struct	rm_priv		rmpriv;
++#endif
++	/* struct	io_queue	*pio_queue; */
++	struct	io_priv	iopriv;
++	struct	xmit_priv	xmitpriv;
++	struct	recv_priv	recvpriv;
++	struct	sta_priv	stapriv;
++	struct	security_priv	securitypriv;
++	_lock   security_key_mutex; /* add for CONFIG_IEEE80211W, none 11w also can use */
++	struct	registry_priv	registrypriv;
++
++#ifdef CONFIG_RTW_NAPI
++	struct	napi_struct napi;
++	u8	napi_state;
++#endif
++
++#ifdef CONFIG_MP_INCLUDED
++	struct	mp_priv	mppriv;
++#endif
++
++#ifdef CONFIG_AP_MODE
++	struct	hostapd_priv	*phostapdpriv;
++#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++#ifdef CONFIG_P2P
++	struct cfg80211_wifidirect_info	cfg80211_wdinfo;
++#endif /* CONFIG_P2P */
++#endif /* CONFIG_IOCTL_CFG80211 */
++	u32	setband;
++	ATOMIC_T bandskip;
++
++#ifdef CONFIG_P2P
++	struct wifidirect_info	wdinfo;
++#endif /* CONFIG_P2P */
++
++#ifdef CONFIG_TDLS
++	struct tdls_info	tdlsinfo;
++#endif /* CONFIG_TDLS */
++
++#ifdef CONFIG_WAPI_SUPPORT
++	u8	WapiSupport;
++	RT_WAPI_T	wapiInfo;
++#endif
++
++#ifdef CONFIG_RTW_REPEATER_SON
++	u8	rtw_rson_scanstage;
++#endif
++
++#ifdef CONFIG_WFD
++	struct wifi_display_info wfd_info;
++#endif /* CONFIG_WFD */
++
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++	struct bt_coex_info coex_info;
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++
++	ERROR_CODE		LastError; /* <20130613, Kordan> Only the functions associated with MP records the error code by now. */
++
++	void *HalData;
++	u32 hal_data_sz;
++	struct hal_ops	hal_func;
++
++	u32	IsrContent;
++	u32	ImrContent;
++
++	u8	EepromAddressSize;
++	u8	bDriverIsGoingToUnload;
++	u8	init_adpt_in_progress;
++	u8	bHaltInProgress;
++#ifdef CONFIG_GPIO_API
++	u8	pre_gpio_pin;
++	struct gpio_int_priv {
++		u8 interrupt_mode;
++		u8 interrupt_enable_mask;
++		void (*callback[8])(u8 level);
++	} gpiointpriv;
++#endif
++	_thread_hdl_ cmdThread;
++#ifdef CONFIG_EVENT_THREAD_MODE
++	_thread_hdl_ evtThread;
++#endif
++#ifdef CONFIG_XMIT_THREAD_MODE
++	_thread_hdl_ xmitThread;
++#endif
++#ifdef CONFIG_RECV_THREAD_MODE
++	_thread_hdl_ recvThread;
++#endif
++	u8 registered;
++
++	void (*intf_start)(_adapter *adapter);
++	void (*intf_stop)(_adapter *adapter);
++
++#ifdef PLATFORM_LINUX
++	_nic_hdl pnetdev;
++	char old_ifname[IFNAMSIZ];
++
++	/* used by rtw_rereg_nd_name related function */
++	struct rereg_nd_name_data {
++		_nic_hdl old_pnetdev;
++		char old_ifname[IFNAMSIZ];
++		u8 old_ips_mode;
++		u8 old_bRegUseLed;
++	} rereg_nd_name_priv;
++
++	u8 ndev_unregistering;
++	int bup;
++	struct net_device_stats stats;
++	struct iw_statistics iwstats;
++	struct proc_dir_entry *dir_dev;/* for proc directory */
++	struct proc_dir_entry *dir_odm;
++
++#ifdef CONFIG_MCC_MODE
++	struct proc_dir_entry *dir_mcc;
++#endif /* CONFIG_MCC_MODE */
++
++#ifdef CONFIG_IOCTL_CFG80211
++	struct wireless_dev *rtw_wdev;
++	struct rtw_wdev_priv wdev_data;
++
++#if !defined(RTW_SINGLE_WIPHY)
++	struct wiphy *wiphy;
++#endif
++
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++#endif /* PLATFORM_LINUX */
++
++#ifdef PLATFORM_FREEBSD
++	_nic_hdl pifp;
++	int bup;
++	_lock glock;
++#endif /* PLATFORM_FREEBSD */
++	u8 mac_addr[ETH_ALEN];
++	int net_closed;
++
++	u8 netif_up;
++
++	u8 bLinkInfoDump;
++	/*	Added by Albert 2012/10/26 */
++	/*	The driver will show up the desired channel number when this flag is 1. */
++	u8 bNotifyChannelChange;
++	u8 bsta_tp_dump;
++#ifdef CONFIG_P2P
++	/*	Added by Albert 2012/12/06 */
++	/*	The driver will show the current P2P status when the upper application reads it. */
++	u8 bShowGetP2PState;
++#endif
++
++	u8 isprimary; /* is primary adapter or not */
++	/* notes:
++	**	if isprimary is true, the adapter_type value is 0, iface_id is IFACE_ID0 for PRIMARY_ADAPTER
++	**	if isprimary is false, the adapter_type value is 1, iface_id is IFACE_ID1 for VIRTUAL_ADAPTER
++	**	refer to iface_id if iface_nums>2 and isprimary is false and the adapter_type value is 0xff.*/
++	u8 adapter_type;/*be used in  Multi-interface to recognize whether is PRIMARY_ADAPTER  or not(PRIMARY_ADAPTER/VIRTUAL_ADAPTER) .*/
++	u8 hw_port; /*interface port type, it depends on HW port */
++
++	#ifdef CONFIG_CLIENT_PORT_CFG
++	u8 client_id;
++	u8 client_port;
++	#endif
++	/*struct tsf_info tsf;*//*reserve define for 8814B*/
++
++	/*extend to support multi interface*/
++	u8 iface_id;
++
++#ifdef CONFIG_BR_EXT
++	_lock					br_ext_lock;
++	/* unsigned int			macclone_completed; */
++	struct nat25_network_db_entry	*nethash[NAT25_HASH_SIZE];
++	int				pppoe_connection_in_progress;
++	unsigned char			pppoe_addr[MACADDRLEN];
++	unsigned char			scdb_mac[MACADDRLEN];
++	unsigned char			scdb_ip[4];
++	struct nat25_network_db_entry	*scdb_entry;
++	unsigned char			br_mac[MACADDRLEN];
++	unsigned char			br_ip[4];
++
++	struct br_ext_info		ethBrExtInfo;
++#endif /* CONFIG_BR_EXT */
++
++#ifdef CONFIG_MAC_LOOPBACK_DRIVER
++	PLOOPBACKDATA ploopback;
++#endif
++#ifdef CONFIG_AP_MODE
++	u8 bmc_tx_rate;
++	#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++	u8 b2u_flags_ap_src;
++	u8 b2u_flags_ap_fwd;
++	#endif
++#endif
++
++	/* for debug purpose */
++	u8 fix_rate;
++	u8 fix_bw;
++	u8 data_fb; /* data rate fallback, valid only when fix_rate is not 0xff */
++	u8 power_offset;
++	u8 driver_tx_bw_mode;
++	u8 rsvd_page_offset;
++	u8 rsvd_page_num;
++	u8 ch_clm_ratio;
++	u8 ch_nhm_ratio;
++#ifdef CONFIG_SUPPORT_FIFO_DUMP
++	u8 fifo_sel;
++	u32 fifo_addr;
++	u32 fifo_size;
++#endif
++
++	u8 driver_vcs_en; /* Enable=1, Disable=0 driver control vrtl_carrier_sense for tx */
++	u8 driver_vcs_type;/* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */
++	u8 driver_ampdu_spacing;/* driver control AMPDU Density for peer sta's rx */
++	u8 driver_rx_ampdu_factor;/* 0xff: disable drv ctrl, 0:8k, 1:16k, 2:32k, 3:64k; */
++	u8 driver_rx_ampdu_spacing;  /* driver control Rx AMPDU Density */
++	u8 fix_rx_ampdu_accept;
++	u8 fix_rx_ampdu_size; /* 0~127, TODO:consider each sta and each TID */
++#ifdef CONFIG_TX_AMSDU
++	u8 tx_amsdu;
++	u16 tx_amsdu_rate;
++#endif
++	u8 driver_tx_max_agg_num; /*fix tx desc max agg num , 0xff: disable drv ctrl*/
++#ifdef DBG_RX_COUNTER_DUMP
++	u8 dump_rx_cnt_mode;/*BIT0:drv,BIT1:mac,BIT2:phy*/
++	u32 drv_rx_cnt_ok;
++	u32 drv_rx_cnt_crcerror;
++	u32 drv_rx_cnt_drop;
++#endif
++
++#ifdef CONFIG_DBG_COUNTER
++	struct rx_logs rx_logs;
++	struct tx_logs tx_logs;
++	struct int_logs int_logs;
++#endif
++
++#ifdef CONFIG_MCC_MODE
++	struct mcc_adapter_priv mcc_adapterpriv;
++#endif /* CONFIG_MCC_MODE */
++
++#ifdef CONFIG_RTW_WDS
++	bool use_wds; /* for STA, AP mode */
++	#ifdef CONFIG_AP_MODE
++	struct rtw_wds_table *wds_paths;
++	ATOMIC_T wds_path_num;
++	#endif
++#endif /* CONFIG_RTW_WDS */
++
++#ifdef CONFIG_RTW_MULTI_AP
++	u8 multi_ap;
++#endif
++
++#ifdef CONFIG_RTW_MESH
++	struct rtw_mesh_cfg mesh_cfg;
++	struct rtw_mesh_info mesh_info;
++	_timer mesh_path_timer;
++	_timer mesh_path_root_timer;
++	_timer mesh_atlm_param_req_timer; /* airtime link metrics param request timer */
++	_workitem mesh_work;
++	unsigned long wrkq_flags;
++#endif /* CONFIG_RTW_MESH */
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	ATOMIC_T tbtx_tx_pause;
++	ATOMIC_T tbtx_remove_tx_pause;
++	u8 tbtx_capability;
++	u32	tbtx_duration;
++#endif /* CONFIG_RTW_TOKEN_BASED_XMIT */
++
++#ifdef RTW_SIMPLE_CONFIG
++	u8 rtw_simple_config;
++#endif
++};
++
++#define adapter_to_dvobj(adapter) ((adapter)->dvobj)
++#define adapter_to_regsty(adapter) dvobj_to_regsty(adapter_to_dvobj((adapter)))
++#define adapter_to_pwrctl(adapter) dvobj_to_pwrctl(adapter_to_dvobj((adapter)))
++#define adapter_wdev_data(adapter) (&((adapter)->wdev_data))
++#if defined(RTW_SINGLE_WIPHY)
++#define adapter_to_wiphy(adapter) dvobj_to_wiphy(adapter_to_dvobj(adapter))
++#else
++#define adapter_to_wiphy(adapter) ((adapter)->wiphy)
++#endif
++
++#define adapter_to_rfctl(adapter) dvobj_to_rfctl(adapter_to_dvobj((adapter)))
++#define adapter_to_macidctl(adapter) dvobj_to_macidctl(adapter_to_dvobj((adapter)))
++
++#ifdef CONFIG_RTW_WDS
++#define adapter_use_wds(adapter) (adapter->use_wds)
++#define adapter_set_use_wds(adapter, en) do { \
++		(adapter)->use_wds = (en) ? 1 : 0; \
++		RTW_INFO(FUNC_ADPT_FMT" set use_wds=%d\n", FUNC_ADPT_ARG(adapter), (adapter)->use_wds); \
++	} while (0)
++#else
++#define adapter_use_wds(adapter) 0
++#endif
++
++#define adapter_mac_addr(adapter) (adapter->mac_addr)
++#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++#define adapter_pno_mac_addr(adapter) \
++	((adapter_wdev_data(adapter))->pno_mac_addr)
++#endif
++
++#define adapter_to_chset(adapter) (adapter_to_rfctl((adapter))->channel_set)
++
++#define mlme_to_adapter(mlme) container_of((mlme), struct _ADAPTER, mlmepriv)
++#define tdls_info_to_adapter(tdls) container_of((tdls), struct _ADAPTER, tdlsinfo)
++
++#define rtw_get_chip_type(adapter) (((PADAPTER)adapter)->dvobj->chip_type)
++#define rtw_get_hw_type(adapter) (((PADAPTER)adapter)->dvobj->HardwareType)
++#define rtw_get_intf_type(adapter) (((PADAPTER)adapter)->dvobj->interface_type)
++
++#define rtw_get_mi_nums(adapter) (((PADAPTER)adapter)->dvobj->iface_nums)
++
++static inline void rtw_set_surprise_removed(_adapter *padapter)
++{
++	dev_set_surprise_removed(adapter_to_dvobj(padapter));
++}
++static inline void rtw_clr_surprise_removed(_adapter *padapter)
++{
++	dev_clr_surprise_removed(adapter_to_dvobj(padapter));
++}
++static inline void rtw_set_drv_stopped(_adapter *padapter)
++{
++	dev_set_drv_stopped(adapter_to_dvobj(padapter));
++}
++static inline void rtw_clr_drv_stopped(_adapter *padapter)
++{
++	dev_clr_drv_stopped(adapter_to_dvobj(padapter));
++}
++#define rtw_is_surprise_removed(padapter)	(dev_is_surprise_removed(adapter_to_dvobj(padapter)))
++#define rtw_is_drv_stopped(padapter)		(dev_is_drv_stopped(adapter_to_dvobj(padapter)))
++
++/*
++ * Function disabled.
++ *   */
++#define DF_TX_BIT		BIT0			/*write_port_cancel*/
++#define DF_RX_BIT		BIT1			/*read_port_cancel*/
++#define DF_IO_BIT		BIT2
++
++/* #define RTW_DISABLE_FUNC(padapter, func) (ATOMIC_ADD(&adapter_to_dvobj(padapter)->disable_func, (func))) */
++/* #define RTW_ENABLE_FUNC(padapter, func) (ATOMIC_SUB(&adapter_to_dvobj(padapter)->disable_func, (func))) */
++__inline static void RTW_DISABLE_FUNC(_adapter *padapter, int func_bit)
++{
++	int	df = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func);
++	df |= func_bit;
++	ATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df);
++}
++
++__inline static void RTW_ENABLE_FUNC(_adapter *padapter, int func_bit)
++{
++	int	df = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func);
++	df &= ~(func_bit);
++	ATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df);
++}
++
++#define RTW_CANNOT_RUN(padapter) \
++	(rtw_is_surprise_removed(padapter) || \
++	 rtw_is_drv_stopped(padapter))
++
++#define RTW_IS_FUNC_DISABLED(padapter, func_bit) (ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func) & (func_bit))
++
++#define RTW_CANNOT_IO(padapter) \
++	(rtw_is_surprise_removed(padapter) || \
++	 RTW_IS_FUNC_DISABLED((padapter), DF_IO_BIT))
++
++#define RTW_CANNOT_RX(padapter) \
++	(RTW_CANNOT_RUN(padapter) || \
++	 RTW_IS_FUNC_DISABLED((padapter), DF_RX_BIT))
++
++#define RTW_CANNOT_TX(padapter) \
++	(RTW_CANNOT_RUN(padapter) || \
++	 RTW_IS_FUNC_DISABLED((padapter), DF_TX_BIT))
++
++#ifdef CONFIG_PNO_SUPPORT
++int rtw_parse_ssid_list_tlv(char **list_str, pno_ssid_t *ssid, int max, int *bytes_left);
++int rtw_dev_pno_set(struct net_device *net, pno_ssid_t *ssid, int num,
++		    int pno_time, int pno_repeat, int pno_freq_expo_max);
++#ifdef CONFIG_PNO_SET_DEBUG
++	void rtw_dev_pno_debug(struct net_device *net);
++#endif /* CONFIG_PNO_SET_DEBUG */
++#endif /* CONFIG_PNO_SUPPORT */
++
++int rtw_suspend_free_assoc_resource(_adapter *padapter);
++#ifdef CONFIG_WOWLAN
++	int rtw_suspend_wow(_adapter *padapter);
++	int rtw_resume_process_wow(_adapter *padapter);
++#endif
++
++/* HCI Related header file */
++#ifdef CONFIG_USB_HCI
++	#include <usb_osintf.h>
++	#include <usb_ops.h>
++	#include <usb_hal.h>
++#endif
++
++#ifdef CONFIG_SDIO_HCI
++	#include <sdio_osintf.h>
++	#include <sdio_ops.h>
++	#include <sdio_hal.h>
++#endif
++
++#ifdef CONFIG_GSPI_HCI
++	#include <gspi_osintf.h>
++	#include <gspi_ops.h>
++	#include <gspi_hal.h>
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	#include <pci_osintf.h>
++	#include <pci_ops.h>
++	#include <pci_hal.h>
++#endif
++
++#endif /* __DRV_TYPES_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_ce.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_ce.h
+new file mode 100644
+index 000000000..c00dea8e6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_ce.h
+@@ -0,0 +1,86 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __DRV_TYPES_CE_H__
++#define __DRV_TYPES_CE_H__
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++
++#include <Sdcardddk.h>
++
++#define MAX_ACTIVE_REG_PATH 256
++
++#define MAX_MCAST_LIST_NUM					32
++
++
++
++/* for ioctl */
++#define MAKE_DRIVER_VERSION(_MainVer, _MinorVer)	((((u32)(_MainVer))<<16)+_MinorVer)
++
++#define NIC_HEADER_SIZE				14			/* !< can be moved to typedef.h */
++#define NIC_MAX_PACKET_SIZE			1514		/* !< can be moved to typedef.h */
++#define NIC_MAX_SEND_PACKETS			10		/* max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h */
++#define NIC_VENDOR_DRIVER_VERSION       MAKE_DRIVER_VERSION(0, 001)	/* !< can be moved to typedef.h */
++#define NIC_MAX_PACKET_SIZE			1514		/* !< can be moved to typedef.h */
++
++typedef struct _MP_REG_ENTRY {
++
++	NDIS_STRING		RegName;	/* variable name text */
++	BOOLEAN			bRequired;	/* 1->required, 0->optional */
++
++	u8			Type;		/* NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString */
++	uint			FieldOffset;	/* offset to MP_ADAPTER field */
++	uint			FieldSize;	/* size (in bytes) of the field */
++
++#ifdef UNDER_AMD64
++	u64			Default;
++#else
++	u32			Default;		/* default value to use */
++#endif
++
++	u32			Min;			/* minimum value allowed */
++	u32			Max;		/* maximum value allowed */
++} MP_REG_ENTRY, *PMP_REG_ENTRY;
++
++#ifdef CONFIG_USB_HCI
++typedef struct _USB_EXTENSION {
++	LPCUSB_FUNCS    _lpUsbFuncs;
++	USB_HANDLE	    _hDevice;
++	PVOID		    pAdapter;
++
++#if 0
++	USB_ENDPOINT_DESCRIPTOR		_endpACLIn;
++	USB_ENDPOINT_DESCRIPTOR		_endpACLOutHigh;
++	USB_ENDPOINT_DESCRIPTOR		_endpACLOutNormal;
++
++	USB_PIPE        pPipeIn;
++	USB_PIPE        pPipeOutNormal;
++	USB_PIPE        pPipeOutHigh;
++#endif
++
++} USB_EXTENSION, *PUSB_EXTENSION;
++#endif
++
++
++typedef struct _OCTET_STRING {
++	u8      *Octet;
++	u16      Length;
++} OCTET_STRING, *POCTET_STRING;
++
++
++
++
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_gspi.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_gspi.h
+new file mode 100644
+index 000000000..c22c49722
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_gspi.h
+@@ -0,0 +1,49 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __DRV_TYPES_GSPI_H__
++#define __DRV_TYPES_GSPI_H__
++
++/* SPI Header Files */
++#ifdef PLATFORM_LINUX
++	#include <linux/platform_device.h>
++	#include <linux/spi/spi.h>
++	#include <linux/gpio.h>
++	/* #include <mach/ldo.h> */
++	#include <asm/mach-types.h>
++	#include <asm/gpio.h>
++	#include <asm/io.h>
++	#include <mach/board.h>
++	#include <mach/hardware.h>
++	#include <mach/irqs.h>
++	#include <custom_gpio.h>
++#endif
++
++
++typedef struct gspi_data {
++	u8  func_number;
++
++	u8  tx_block_mode;
++	u8  rx_block_mode;
++	u32 block_transfer_len;
++
++#ifdef PLATFORM_LINUX
++	struct spi_device *func;
++
++	struct workqueue_struct *priv_wq;
++	struct delayed_work irq_work;
++#endif
++} GSPI_DATA, *PGSPI_DATA;
++
++#endif /*  #ifndef __DRV_TYPES_GSPI_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_linux.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_linux.h
+new file mode 100644
+index 000000000..91ca68b39
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_linux.h
+@@ -0,0 +1,19 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __DRV_TYPES_LINUX_H__
++#define __DRV_TYPES_LINUX_H__
++
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_pci.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_pci.h
+new file mode 100644
+index 000000000..2c550ecc0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_pci.h
+@@ -0,0 +1,60 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __DRV_TYPES_PCI_H__
++#define __DRV_TYPES_PCI_H__
++
++#ifdef PLATFORM_LINUX
++	#include <linux/pci.h>
++#endif
++
++#define	INTEL_VENDOR_ID				0x8086
++#define	SIS_VENDOR_ID					0x1039
++#define	ATI_VENDOR_ID					0x1002
++#define	ATI_DEVICE_ID					0x7914
++#define	AMD_VENDOR_ID					0x1022
++
++#define PCI_VENDER_ID_REALTEK		0x10ec
++
++enum aspm_mode {
++	ASPM_MODE_UND,
++	ASPM_MODE_PERF,
++	ASPM_MODE_PS,
++	ASPM_MODE_DEF,
++};
++
++struct pci_priv {
++	BOOLEAN		pci_clk_req;
++
++	u8	pciehdr_offset;
++
++	u8	linkctrl_reg;
++	u8	pcibridge_linkctrlreg;
++
++	u8	amd_l1_patch;
++
++#ifdef CONFIG_PCI_DYNAMIC_ASPM
++	u8	aspm_mode;
++#endif
++};
++
++typedef struct _RT_ISR_CONTENT {
++	union {
++		u32			IntArray[2];
++		u32			IntReg4Byte;
++		u16			IntReg2Byte;
++	};
++} RT_ISR_CONTENT, *PRT_ISR_CONTENT;
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_sdio.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_sdio.h
+new file mode 100644
+index 000000000..29006d981
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_sdio.h
+@@ -0,0 +1,94 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __DRV_TYPES_SDIO_H__
++#define __DRV_TYPES_SDIO_H__
++
++/* SDIO Header Files */
++#ifdef PLATFORM_LINUX
++	#include <linux/mmc/sdio_func.h>
++	#include <linux/mmc/sdio_ids.h>
++	#include <linux/mmc/host.h>
++	#include <linux/mmc/card.h>
++
++	#ifdef CONFIG_PLATFORM_SPRD
++		#include <linux/gpio.h>
++		#include <custom_gpio.h>
++	#endif /* CONFIG_PLATFORM_SPRD */
++#endif
++
++#define RTW_SDIO_CLK_33M	33000000
++#define RTW_SDIO_CLK_40M	40000000
++#define RTW_SDIO_CLK_80M	80000000
++#define RTW_SDIO_CLK_160M	160000000
++
++typedef struct sdio_data {
++	u8  func_number;
++
++	u8  tx_block_mode;
++	u8  rx_block_mode;
++	u32 block_transfer_len;
++
++#ifdef PLATFORM_LINUX
++	struct mmc_card *card;
++	struct sdio_func	*func;
++	_thread_hdl_ sys_sdio_irq_thd;
++	unsigned int clock;
++	unsigned int timing;
++	u8	sd3_bus_mode;
++#endif
++
++#ifdef DBG_SDIO
++#ifdef PLATFORM_LINUX
++	struct proc_dir_entry *proc_sdio_dbg;
++#endif /* PLATFORM_LINUX */
++
++	u32 cmd52_err_cnt;	/* CMD52 I/O error count */
++	u32 cmd53_err_cnt;	/* CMD53 I/O error count */
++
++#if (DBG_SDIO >= 1)
++	u32 reg_dump_mark;	/* reg dump at specific error count */
++#endif /* DBG_SDIO >= 1 */
++
++#if (DBG_SDIO >= 2)
++	u8 *dbg_msg;		/* Messages for debug */
++	u8 dbg_msg_size;
++	u8 *reg_mac;		/* Device MAC register, 0x0~0x800 */
++	u8 *reg_mac_ext;	/* Device MAC extend register, 0x1000~0x1800 */
++	u8 *reg_local;		/* Device SDIO local register, 0x0~0xFF */
++	u8 *reg_cia;		/* SDIO CIA(CCCR, FBR and etc.), 0x0~0x1FF */
++#endif /* DBG_SDIO >= 2 */
++
++#if (DBG_SDIO >= 3)
++	u8 dbg_enable;		/* 0/1: disable/enable debug mode */
++	u8 err_stop;		/* Stop(surprise remove) when I/O error happen */
++	u8 err_test;		/* Simulate error happen */
++	u8 err_test_triggered;	/* Simulate error already triggered */
++#endif /* DBG_SDIO >= 3 */
++#endif /* DBG_SDIO */
++} SDIO_DATA, *PSDIO_DATA;
++
++#define dvobj_to_sdio_func(d)	((d)->intf_data.func)
++
++#define RTW_SDIO_ADDR_CMD52_BIT		(1<<17)
++#define RTW_SDIO_ADDR_CMD52_GEN(a)	(a | RTW_SDIO_ADDR_CMD52_BIT)
++#define RTW_SDIO_ADDR_CMD52_CLR(a)	(a&~RTW_SDIO_ADDR_CMD52_BIT)
++#define RTW_SDIO_ADDR_CMD52_CHK(a)	(a&RTW_SDIO_ADDR_CMD52_BIT ? 1 : 0)
++
++#define RTW_SDIO_ADDR_F0_BIT		(1<<18)
++#define RTW_SDIO_ADDR_F0_GEN(a)		(a | RTW_SDIO_ADDR_F0_BIT)
++#define RTW_SDIO_ADDR_F0_CLR(a)		(a&~RTW_SDIO_ADDR_F0_BIT)
++#define RTW_SDIO_ADDR_F0_CHK(a)		(a&RTW_SDIO_ADDR_F0_BIT ? 1 : 0)
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_xp.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_xp.h
+new file mode 100644
+index 000000000..81c45047a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/drv_types_xp.h
+@@ -0,0 +1,88 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __DRV_TYPES_XP_H__
++#define __DRV_TYPES_XP_H__
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++
++
++
++#define MAX_MCAST_LIST_NUM					32
++
++
++
++/* for ioctl */
++#define MAKE_DRIVER_VERSION(_MainVer, _MinorVer)	((((u32)(_MainVer))<<16)+_MinorVer)
++
++#define NIC_HEADER_SIZE				14			/* !< can be moved to typedef.h */
++#define NIC_MAX_PACKET_SIZE			1514		/* !< can be moved to typedef.h */
++#define NIC_MAX_SEND_PACKETS			10		/* max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h */
++#define NIC_VENDOR_DRIVER_VERSION       MAKE_DRIVER_VERSION(0, 001)	/* !< can be moved to typedef.h */
++#define NIC_MAX_PACKET_SIZE			1514		/* !< can be moved to typedef.h */
++
++
++#undef ON_VISTA
++/* added by Jackson */
++#ifndef ON_VISTA
++	/*
++	* Bus driver versions
++	*   */
++
++	#define SDBUS_DRIVER_VERSION_1          0x100
++	#define SDBUS_DRIVER_VERSION_2          0x200
++
++	#define    SDP_FUNCTION_TYPE	4
++	#define    SDP_BUS_DRIVER_VERSION 5
++	#define    SDP_BUS_WIDTH 6
++	#define    SDP_BUS_CLOCK 7
++	#define    SDP_BUS_INTERFACE_CONTROL 8
++	#define    SDP_HOST_BLOCK_LENGTH 9
++	#define    SDP_FUNCTION_BLOCK_LENGTH 10
++	#define    SDP_FN0_BLOCK_LENGTH 11
++	#define    SDP_FUNCTION_INT_ENABLE 12
++#endif
++
++
++typedef struct _MP_REG_ENTRY {
++
++	NDIS_STRING		RegName;	/* variable name text */
++	BOOLEAN			bRequired;	/* 1->required, 0->optional */
++
++	u8			Type;		/* NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString */
++	uint			FieldOffset;	/* offset to MP_ADAPTER field */
++	uint			FieldSize;	/* size (in bytes) of the field */
++
++#ifdef UNDER_AMD64
++	u64			Default;
++#else
++	u32			Default;		/* default value to use */
++#endif
++
++	u32			Min;			/* minimum value allowed */
++	u32			Max;		/* maximum value allowed */
++} MP_REG_ENTRY, *PMP_REG_ENTRY;
++
++
++typedef struct _OCTET_STRING {
++	u8      *Octet;
++	u16      Length;
++} OCTET_STRING, *POCTET_STRING;
++
++
++
++
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/ethernet.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/ethernet.h
+new file mode 100644
+index 000000000..ef518cc41
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/ethernet.h
+@@ -0,0 +1,36 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*! \file */
++#ifndef __INC_ETHERNET_H
++#define __INC_ETHERNET_H
++
++#define ETHERNET_ADDRESS_LENGTH				6		/* !< Ethernet Address Length */
++#define ETHERNET_HEADER_SIZE				14		/* !< Ethernet Header Length */
++#define LLC_HEADER_SIZE						6		/* !< LLC Header Length */
++#define TYPE_LENGTH_FIELD_SIZE				2		/* !< Type/Length Size */
++#define MINIMUM_ETHERNET_PACKET_SIZE		60		/* !< Minimum Ethernet Packet Size */
++#define MAXIMUM_ETHERNET_PACKET_SIZE		1514	/* !< Maximum Ethernet Packet Size */
++
++#define RT_ETH_IS_MULTICAST(_pAddr)	((((u8 *)(_pAddr))[0]&0x01) != 0)		/* !< Is Multicast Address? */
++#define RT_ETH_IS_BROADCAST(_pAddr)	(\
++		((u8 *)(_pAddr))[0] == 0xff	&&		\
++		((u8 *)(_pAddr))[1] == 0xff	&&		\
++		((u8 *)(_pAddr))[2] == 0xff	&&		\
++		((u8 *)(_pAddr))[3] == 0xff	&&		\
++		((u8 *)(_pAddr))[4] == 0xff	&&		\
++		((u8 *)(_pAddr))[5] == 0xff)	/* !< Is Broadcast Address? */
++
++
++#endif /*  #ifndef __INC_ETHERNET_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/gspi_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/gspi_hal.h
+new file mode 100644
+index 000000000..6da0f071d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/gspi_hal.h
+@@ -0,0 +1,30 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __GSPI_HAL_H__
++#define __GSPI_HAL_H__
++
++
++void spi_int_dpc(PADAPTER padapter, u32 sdio_hisr);
++u8 rtw_set_hal_ops(_adapter *padapter);
++
++#ifdef CONFIG_RTL8188E
++	void rtl8188es_set_hal_ops(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_RTL8723B
++	void rtl8723bs_set_hal_ops(PADAPTER padapter);
++#endif
++
++#endif /* __GSPI_HAL_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/gspi_ops.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/gspi_ops.h
+new file mode 100644
+index 000000000..bcfaad2e0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/gspi_ops.h
+@@ -0,0 +1,180 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __GSPI_OPS_H__
++#define __GSPI_OPS_H__
++
++/* follwing defination is based on
++ * GSPI spec of RTL8723, we temp
++ * suppose that it will be the same
++ * for diff chips of GSPI, if not
++ * we should move it to HAL folder */
++#define SPI_LOCAL_DOMAIN				0x0
++#define WLAN_IOREG_DOMAIN			0x8
++#define FW_FIFO_DOMAIN				0x4
++#define TX_HIQ_DOMAIN					0xc
++#define TX_MIQ_DOMAIN					0xd
++#define TX_LOQ_DOMAIN					0xe
++#define RX_RXFIFO_DOMAIN				0x1f
++
++/* IO Bus domain address mapping */
++#define DEFUALT_OFFSET					0x0
++#define SPI_LOCAL_OFFSET				0x10250000
++#define WLAN_IOREG_OFFSET			0x10260000
++#define FW_FIFO_OFFSET				0x10270000
++#define TX_HIQ_OFFSET					0x10310000
++#define TX_MIQ_OFFSET					0x1032000
++#define TX_LOQ_OFFSET					0x10330000
++#define RX_RXOFF_OFFSET				0x10340000
++
++/* SPI Local registers */
++#define SPI_REG_TX_CTRL					0x0000 /* SPI Tx Control */
++#define SPI_REG_STATUS_RECOVERY		0x0004
++#define SPI_REG_INT_TIMEOUT			0x0006
++#define SPI_REG_HIMR					0x0014 /* SPI Host Interrupt Mask */
++#define SPI_REG_HISR					0x0018 /* SPI Host Interrupt Service Routine */
++#define SPI_REG_RX0_REQ_LEN			0x001C /* RXDMA Request Length */
++#define SPI_REG_FREE_TXPG				0x0020 /* Free Tx Buffer Page */
++#define SPI_REG_HCPWM1					0x0024 /* HCI Current Power Mode 1 */
++#define SPI_REG_HCPWM2					0x0026 /* HCI Current Power Mode 2 */
++#define SPI_REG_HTSFR_INFO				0x0030 /* HTSF Informaion */
++#define SPI_REG_HRPWM1					0x0080 /* HCI Request Power Mode 1 */
++#define SPI_REG_HRPWM2					0x0082 /* HCI Request Power Mode 2 */
++#define SPI_REG_HPS_CLKR				0x0084 /* HCI Power Save Clock */
++#define SPI_REG_HSUS_CTRL				0x0086 /* SPI HCI Suspend Control */
++#define SPI_REG_HIMR_ON				0x0090 /* SPI Host Extension Interrupt Mask Always */
++#define SPI_REG_HISR_ON				0x0091 /* SPI Host Extension Interrupt Status Always */
++#define SPI_REG_CFG						0x00F0 /* SPI Configuration Register */
++
++#define SPI_TX_CTRL				(SPI_REG_TX_CTRL | SPI_LOCAL_OFFSET)
++#define SPI_STATUS_RECOVERY			(SPI_REG_STATUS_RECOVERY | SPI_LOCAL_OFFSET)
++#define SPI_INT_TIMEOUT					(SPI_REG_INT_TIMEOUT | SPI_LOCAL_OFFSET)
++#define SPI_HIMR				(SPI_REG_HIMR | SPI_LOCAL_OFFSET)
++#define SPI_HISR				(SPI_REG_HISR | SPI_LOCAL_OFFSET)
++#define SPI_RX0_REQ_LEN_1_BYTE		(SPI_REG_RX0_REQ_LEN | SPI_LOCAL_OFFSET)
++#define SPI_FREE_TXPG			(SPI_REG_FREE_TXPG | SPI_LOCAL_OFFSET)
++
++#define	SPI_HIMR_DISABLED				0
++
++/* SPI HIMR MASK diff with SDIO */
++#define SPI_HISR_RX_REQUEST			BIT(0)
++#define SPI_HISR_AVAL					BIT(1)
++#define SPI_HISR_TXERR					BIT(2)
++#define SPI_HISR_RXERR					BIT(3)
++#define SPI_HISR_TXFOVW				BIT(4)
++#define SPI_HISR_RXFOVW				BIT(5)
++#define SPI_HISR_TXBCNOK				BIT(6)
++#define SPI_HISR_TXBCNERR				BIT(7)
++#define SPI_HISR_BCNERLY_INT			BIT(16)
++#define SPI_HISR_ATIMEND				BIT(17)
++#define SPI_HISR_ATIMEND_E				BIT(18)
++#define SPI_HISR_CTWEND				BIT(19)
++#define SPI_HISR_C2HCMD				BIT(20)
++#define SPI_HISR_CPWM1					BIT(21)
++#define SPI_HISR_CPWM2					BIT(22)
++#define SPI_HISR_HSISR_IND				BIT(23)
++#define SPI_HISR_GTINT3_IND				BIT(24)
++#define SPI_HISR_GTINT4_IND				BIT(25)
++#define SPI_HISR_PSTIMEOUT				BIT(26)
++#define SPI_HISR_OCPINT					BIT(27)
++#define SPI_HISR_TSF_BIT32_TOGGLE		BIT(29)
++
++#define MASK_SPI_HISR_CLEAR		(SPI_HISR_TXERR |\
++		SPI_HISR_RXERR |\
++		SPI_HISR_TXFOVW |\
++		SPI_HISR_RXFOVW |\
++		SPI_HISR_TXBCNOK |\
++		SPI_HISR_TXBCNERR |\
++		SPI_HISR_C2HCMD |\
++		SPI_HISR_CPWM1 |\
++		SPI_HISR_CPWM2 |\
++		SPI_HISR_HSISR_IND |\
++		SPI_HISR_GTINT3_IND |\
++		SPI_HISR_GTINT4_IND |\
++		SPI_HISR_PSTIMEOUT |\
++		SPI_HISR_OCPINT)
++
++#define REG_LEN_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)/* (x<<(unsigned int)24) */
++#define REG_ADDR_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)/* (x<<(unsigned int)16) */
++#define REG_DOMAIN_ID_FORMAT(pcmd, x) 		SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)/* (x<<(unsigned int)0) */
++#define REG_FUN_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)/* (x<<(unsigned int)5) */
++#define REG_RW_FORMAT(pcmd, x) 				SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)/* (x<<(unsigned int)7) */
++
++#define FIFO_LEN_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)/* (x<<(unsigned int)24)
++ * #define FIFO_ADDR_FORMAT(pcmd,x) 			SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x) */ /* (x<<(unsigned int)16) */
++#define FIFO_DOMAIN_ID_FORMAT(pcmd, x) 	SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)/* (x<<(unsigned int)0) */
++#define FIFO_FUN_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)/* (x<<(unsigned int)5) */
++#define FIFO_RW_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)/* (x<<(unsigned int)7) */
++
++
++/* get status dword0 */
++#define GET_STATUS_PUB_PAGE_NUM(status)		LE_BITS_TO_4BYTE(status, 24, 8)
++#define GET_STATUS_HI_PAGE_NUM(status)		LE_BITS_TO_4BYTE(status, 18, 6)
++#define GET_STATUS_MID_PAGE_NUM(status)		LE_BITS_TO_4BYTE(status, 12, 6)
++#define GET_STATUS_LOW_PAGE_NUM(status)		LE_BITS_TO_4BYTE(status, 6, 6)
++#define GET_STATUS_HISR_HI6BIT(status)			LE_BITS_TO_4BYTE(status, 0, 6)
++
++/* get status dword1 */
++#define GET_STATUS_HISR_MID8BIT(status)		LE_BITS_TO_4BYTE(status + 4, 24, 8)
++#define GET_STATUS_HISR_LOW8BIT(status)		LE_BITS_TO_4BYTE(status + 4, 16, 8)
++#define GET_STATUS_ERROR(status)				LE_BITS_TO_4BYTE(status + 4, 17, 1)
++#define GET_STATUS_INT(status)				LE_BITS_TO_4BYTE(status + 4, 16, 1)
++#define GET_STATUS_RX_LENGTH(status)			LE_BITS_TO_4BYTE(status + 4, 0, 16)
++
++
++#define RXDESC_SIZE	24
++
++
++struct spi_more_data {
++	unsigned long more_data;
++	unsigned long len;
++};
++
++#ifdef CONFIG_RTL8188E
++	void rtl8188es_set_hal_ops(PADAPTER padapter);
++	#define set_hal_ops rtl8188es_set_hal_ops
++#endif
++extern void spi_set_chip_endian(PADAPTER padapter);
++extern unsigned int spi_write8_endian(ADAPTER *Adapter, unsigned int addr, unsigned int buf, u32 big);
++extern void spi_set_intf_ops(_adapter *padapter, struct _io_ops *pops);
++extern void spi_set_chip_endian(PADAPTER padapter);
++extern void InitInterrupt8723ASdio(PADAPTER padapter);
++extern void InitSysInterrupt8723ASdio(PADAPTER padapter);
++extern void EnableInterrupt8723ASdio(PADAPTER padapter);
++extern void DisableInterrupt8723ASdio(PADAPTER padapter);
++extern void spi_int_hdl(PADAPTER padapter);
++extern u8 HalQueryTxBufferStatus8723ASdio(PADAPTER padapter);
++#ifdef CONFIG_RTL8723B
++	extern void InitInterrupt8723BSdio(PADAPTER padapter);
++	extern void InitSysInterrupt8723BSdio(PADAPTER padapter);
++	extern void EnableInterrupt8723BSdio(PADAPTER padapter);
++	extern void DisableInterrupt8723BSdio(PADAPTER padapter);
++	extern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_RTL8188E
++	extern void InitInterrupt8188EGspi(PADAPTER padapter);
++	extern void EnableInterrupt8188EGspi(PADAPTER padapter);
++	extern void DisableInterrupt8188EGspi(PADAPTER padapter);
++	extern void UpdateInterruptMask8188EGspi(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);
++	extern u8 HalQueryTxBufferStatus8189EGspi(PADAPTER padapter);
++	extern u8 HalQueryTxOQTBufferStatus8189EGspi(PADAPTER padapter);
++	extern void ClearInterrupt8188EGspi(PADAPTER padapter);
++	extern u8 CheckIPSStatus(PADAPTER padapter);
++#endif /* CONFIG_RTL8188E */
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++	extern u8 RecvOnePkt(PADAPTER padapter);
++#endif /* CONFIG_WOWLAN */
++
++#endif /* __GSPI_OPS_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/gspi_ops_linux.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/gspi_ops_linux.h
+new file mode 100644
+index 000000000..0ba263de8
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/gspi_ops_linux.h
+@@ -0,0 +1,18 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __SDIO_OPS_LINUX_H__
++#define __SDIO_OPS_LINUX_H__
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/gspi_osintf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/gspi_osintf.h
+new file mode 100644
+index 000000000..a94e65679
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/gspi_osintf.h
+@@ -0,0 +1,19 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __SDIO_OSINTF_H__
++#define __SDIO_OSINTF_H__
++
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/h2clbk.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/h2clbk.h
+new file mode 100644
+index 000000000..4df14b98d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/h2clbk.h
+@@ -0,0 +1,26 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++
++#define _H2CLBK_H_
++
++
++void _lbk_cmd(PADAPTER Adapter);
++
++void _lbk_rsp(PADAPTER Adapter);
++
++void _lbk_evt(PADAPTER Adapter);
++
++void h2c_event_callback(unsigned char *dev, unsigned char *pbuf);
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_btcoex.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_btcoex.h
+new file mode 100644
+index 000000000..40ddafb5d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_btcoex.h
+@@ -0,0 +1,106 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL_BTCOEX_H__
++#define __HAL_BTCOEX_H__
++
++#include <drv_types.h>
++
++/* Some variables can't get from outsrc BT-Coex,
++ * so we need to save here */
++typedef struct _BT_COEXIST {
++	u8 bBtExist;
++	u8 btTotalAntNum;
++	u8 btChipType;
++	u8 bInitlized;
++	u8 btAntisolation;
++} BT_COEXIST, *PBT_COEXIST;
++
++void DBG_BT_INFO(u8 *dbgmsg);
++
++void hal_btcoex_SetBTCoexist(PADAPTER padapter, u8 bBtExist);
++u8 hal_btcoex_IsBtExist(PADAPTER padapter);
++u8 hal_btcoex_IsBtDisabled(PADAPTER);
++void hal_btcoex_SetChipType(PADAPTER padapter, u8 chipType);
++void hal_btcoex_SetPgAntNum(PADAPTER padapter, u8 antNum);
++
++u8 hal_btcoex_Initialize(PADAPTER padapter);
++void hal_btcoex_PowerOnSetting(PADAPTER padapter);
++void hal_btcoex_AntInfoSetting(PADAPTER padapter);
++void hal_btcoex_PowerOffSetting(PADAPTER padapter);
++void hal_btcoex_PreLoadFirmware(PADAPTER padapter);
++void hal_btcoex_InitHwConfig(PADAPTER padapter, u8 bWifiOnly);
++
++void hal_btcoex_IpsNotify(PADAPTER padapter, u8 type);
++void hal_btcoex_LpsNotify(PADAPTER padapter, u8 type);
++void hal_btcoex_ScanNotify(PADAPTER padapter, u8 type);
++void hal_btcoex_ConnectNotify(PADAPTER padapter, u8 action);
++void hal_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus);
++void hal_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType);
++void hal_btcoex_IQKNotify(PADAPTER padapter, u8 state);
++void hal_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf);
++void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf);
++void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state);
++void hal_btcoex_HaltNotify(PADAPTER padapter, u8 do_halt);
++void hal_btcoex_SwitchBtTRxMask(PADAPTER padapter);
++
++void hal_btcoex_Hanlder(PADAPTER padapter);
++
++s32 hal_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter);
++s32 hal_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter);
++u32 hal_btcoex_GetAMPDUSize(PADAPTER padapter);
++void hal_btcoex_SetManualControl(PADAPTER padapter, u8 bmanual);
++u8 hal_btcoex_1Ant(PADAPTER padapter);
++u8 hal_btcoex_IsBtControlLps(PADAPTER);
++u8 hal_btcoex_IsLpsOn(PADAPTER);
++u8 hal_btcoex_RpwmVal(PADAPTER);
++u8 hal_btcoex_LpsVal(PADAPTER);
++u32 hal_btcoex_GetRaMask(PADAPTER);
++u8 hal_btcoex_query_reduced_wl_pwr_lvl(PADAPTER padapter);
++void hal_btcoex_set_reduced_wl_pwr_lvl(PADAPTER padapter, u8 val);
++void hal_btcoex_do_reduce_wl_pwr_lvl(PADAPTER padapter);
++void hal_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen);
++void hal_btcoex_DisplayBtCoexInfo(PADAPTER, u8 *pbuf, u32 bufsize);
++void hal_btcoex_SetDBG(PADAPTER, u32 *pDbgModule);
++u32 hal_btcoex_GetDBG(PADAPTER, u8 *pStrBuf, u32 bufSize);
++u8 hal_btcoex_IncreaseScanDeviceNum(PADAPTER);
++u8 hal_btcoex_IsBtLinkExist(PADAPTER);
++void hal_btcoex_SetBtPatchVersion(PADAPTER, u16 btHciVer, u16 btPatchVer);
++void hal_btcoex_SetHciVersion(PADAPTER, u16 hciVersion);
++void hal_btcoex_SendScanNotify(PADAPTER, u8 type);
++void hal_btcoex_StackUpdateProfileInfo(void);
++void hal_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON);
++void hal_btcoex_SetAntIsolationType(PADAPTER padapter, u8 anttype);
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++	int hal_btcoex_AntIsolationConfig_ParaFile(PADAPTER	Adapter, char *pFileName);
++	int hal_btcoex_ParseAntIsolationConfigFile(PADAPTER Adapter, char	*buffer);
++#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */
++u16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data);
++u16 hal_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val);
++void hal_btcoex_set_rfe_type(u8 type);
++void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type);
++void hal_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length);
++void hal_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id);
++u16 hal_btcoex_btset_testode(PADAPTER padapter, u8 type);
++
++#ifdef CONFIG_RF4CE_COEXIST
++void hal_btcoex_set_rf4ce_link_state(u8 state);
++u8 hal_btcoex_get_rf4ce_link_state(void);
++#endif
++
++#ifdef CONFIG_SDIO_HCI
++#include <hal_sdio_coex.h>	/* sdio multi coex */
++#endif
++
++#endif /* !__HAL_BTCOEX_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_btcoex_wifionly.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_btcoex_wifionly.h
+new file mode 100644
+index 000000000..d28bfceec
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_btcoex_wifionly.h
+@@ -0,0 +1,88 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HALBTC_WIFIONLY_H__
++#define __HALBTC_WIFIONLY_H__
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++/* Define the ICs that support wifi only cfg in coex. codes */
++#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
++#define CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG 1
++#else
++#define CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG 0
++#endif
++
++/* Define the ICs that support hal btc common file structure */
++#if defined(CONFIG_RTL8822C) || (defined(CONFIG_RTL8192F) && defined(CONFIG_BT_COEXIST))
++#define CONFIG_BTCOEX_SUPPORT_BTC_CMN 1
++#else
++#define CONFIG_BTCOEX_SUPPORT_BTC_CMN 0
++#endif
++
++#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1)
++
++typedef enum _WIFIONLY_CHIP_INTERFACE {
++	WIFIONLY_INTF_UNKNOWN	= 0,
++	WIFIONLY_INTF_PCI		= 1,
++	WIFIONLY_INTF_USB		= 2,
++	WIFIONLY_INTF_SDIO		= 3,
++	WIFIONLY_INTF_MAX
++} WIFIONLY_CHIP_INTERFACE, *PWIFIONLY_CHIP_INTERFACE;
++
++typedef enum _WIFIONLY_CUSTOMER_ID {
++	CUSTOMER_NORMAL			= 0,
++	CUSTOMER_HP_1			= 1
++} WIFIONLY_CUSTOMER_ID, *PWIFIONLY_CUSTOMER_ID;
++
++struct wifi_only_haldata {
++	u16		customer_id;
++	u8		efuse_pg_antnum;
++	u8		efuse_pg_antpath;
++	u8		rfe_type;
++	u8		ant_div_cfg;
++};
++
++struct wifi_only_cfg {
++	void *Adapter;
++	struct wifi_only_haldata	haldata_info;
++	WIFIONLY_CHIP_INTERFACE	chip_interface;
++};
++
++void halwifionly_write1byte(void *pwifionlyContext, u32 RegAddr, u8 Data);
++void halwifionly_write2byte(void *pwifionlyContext, u32 RegAddr, u16 Data);
++void halwifionly_write4byte(void *pwifionlyContext, u32 RegAddr, u32 Data);
++u8 halwifionly_read1byte(void *pwifionlyContext, u32 RegAddr);
++u16 halwifionly_read2byte(void *pwifionlyContext, u32 RegAddr);
++u32 halwifionly_read4byte(void *pwifionlyContext, u32 RegAddr);
++void halwifionly_bitmaskwrite1byte(void *pwifionlyContext, u32 regAddr, u8 bitMask, u8 data);
++void halwifionly_phy_set_rf_reg(void *pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
++void halwifionly_phy_set_bb_reg(void *pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data);
++void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter);
++void hal_btcoex_wifionly_scan_notify(PADAPTER padapter);
++void hal_btcoex_wifionly_connect_notify(PADAPTER padapter);
++void hal_btcoex_wifionly_hw_config(PADAPTER padapter);
++void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter);
++void hal_btcoex_wifionly_AntInfoSetting(PADAPTER padapter);
++#else
++#define hal_btcoex_wifionly_switchband_notify(padapter)
++#define hal_btcoex_wifionly_scan_notify(padapter)
++#define hal_btcoex_wifionly_connect_notify(padapter)
++#define hal_btcoex_wifionly_hw_config(padapter)
++#define hal_btcoex_wifionly_initlizevariables(padapter)
++#define hal_btcoex_wifionly_AntInfoSetting(padapter)
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_com.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_com.h
+new file mode 100644
+index 000000000..282469390
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_com.h
+@@ -0,0 +1,803 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL_COMMON_H__
++#define __HAL_COMMON_H__
++
++#include "HalVerDef.h"
++#include "hal_pg.h"
++#include "hal_phy.h"
++#include "hal_phy_reg.h"
++#include "hal_com_reg.h"
++#include "hal_com_phycfg.h"
++#include "../hal/hal_com_c2h.h"
++
++/*------------------------------ Tx Desc definition Macro ------------------------*/
++/* #pragma mark -- Tx Desc related definition. -- */
++/* ----------------------------------------------------------------------------
++ * -----------------------------------------------------------
++ *	Rate
++ * -----------------------------------------------------------
++ * CCK Rates, TxHT = 0 */
++#define DESC_RATE1M					0x00
++#define DESC_RATE2M					0x01
++#define DESC_RATE5_5M				0x02
++#define DESC_RATE11M				0x03
++
++/* OFDM Rates, TxHT = 0 */
++#define DESC_RATE6M					0x04
++#define DESC_RATE9M					0x05
++#define DESC_RATE12M				0x06
++#define DESC_RATE18M				0x07
++#define DESC_RATE24M				0x08
++#define DESC_RATE36M				0x09
++#define DESC_RATE48M				0x0a
++#define DESC_RATE54M				0x0b
++
++/* MCS Rates, TxHT = 1 */
++#define DESC_RATEMCS0				0x0c
++#define DESC_RATEMCS1				0x0d
++#define DESC_RATEMCS2				0x0e
++#define DESC_RATEMCS3				0x0f
++#define DESC_RATEMCS4				0x10
++#define DESC_RATEMCS5				0x11
++#define DESC_RATEMCS6				0x12
++#define DESC_RATEMCS7				0x13
++#define DESC_RATEMCS8				0x14
++#define DESC_RATEMCS9				0x15
++#define DESC_RATEMCS10				0x16
++#define DESC_RATEMCS11				0x17
++#define DESC_RATEMCS12				0x18
++#define DESC_RATEMCS13				0x19
++#define DESC_RATEMCS14				0x1a
++#define DESC_RATEMCS15				0x1b
++#define DESC_RATEMCS16				0x1C
++#define DESC_RATEMCS17				0x1D
++#define DESC_RATEMCS18				0x1E
++#define DESC_RATEMCS19				0x1F
++#define DESC_RATEMCS20				0x20
++#define DESC_RATEMCS21				0x21
++#define DESC_RATEMCS22				0x22
++#define DESC_RATEMCS23				0x23
++#define DESC_RATEMCS24				0x24
++#define DESC_RATEMCS25				0x25
++#define DESC_RATEMCS26				0x26
++#define DESC_RATEMCS27				0x27
++#define DESC_RATEMCS28				0x28
++#define DESC_RATEMCS29				0x29
++#define DESC_RATEMCS30				0x2A
++#define DESC_RATEMCS31				0x2B
++#define DESC_RATEVHTSS1MCS0		0x2C
++#define DESC_RATEVHTSS1MCS1		0x2D
++#define DESC_RATEVHTSS1MCS2		0x2E
++#define DESC_RATEVHTSS1MCS3		0x2F
++#define DESC_RATEVHTSS1MCS4		0x30
++#define DESC_RATEVHTSS1MCS5		0x31
++#define DESC_RATEVHTSS1MCS6		0x32
++#define DESC_RATEVHTSS1MCS7		0x33
++#define DESC_RATEVHTSS1MCS8		0x34
++#define DESC_RATEVHTSS1MCS9		0x35
++#define DESC_RATEVHTSS2MCS0		0x36
++#define DESC_RATEVHTSS2MCS1		0x37
++#define DESC_RATEVHTSS2MCS2		0x38
++#define DESC_RATEVHTSS2MCS3		0x39
++#define DESC_RATEVHTSS2MCS4		0x3A
++#define DESC_RATEVHTSS2MCS5		0x3B
++#define DESC_RATEVHTSS2MCS6		0x3C
++#define DESC_RATEVHTSS2MCS7		0x3D
++#define DESC_RATEVHTSS2MCS8		0x3E
++#define DESC_RATEVHTSS2MCS9		0x3F
++#define DESC_RATEVHTSS3MCS0		0x40
++#define DESC_RATEVHTSS3MCS1		0x41
++#define DESC_RATEVHTSS3MCS2		0x42
++#define DESC_RATEVHTSS3MCS3		0x43
++#define DESC_RATEVHTSS3MCS4		0x44
++#define DESC_RATEVHTSS3MCS5		0x45
++#define DESC_RATEVHTSS3MCS6		0x46
++#define DESC_RATEVHTSS3MCS7		0x47
++#define DESC_RATEVHTSS3MCS8		0x48
++#define DESC_RATEVHTSS3MCS9		0x49
++#define DESC_RATEVHTSS4MCS0		0x4A
++#define DESC_RATEVHTSS4MCS1		0x4B
++#define DESC_RATEVHTSS4MCS2		0x4C
++#define DESC_RATEVHTSS4MCS3		0x4D
++#define DESC_RATEVHTSS4MCS4		0x4E
++#define DESC_RATEVHTSS4MCS5		0x4F
++#define DESC_RATEVHTSS4MCS6		0x50
++#define DESC_RATEVHTSS4MCS7		0x51
++#define DESC_RATEVHTSS4MCS8		0x52
++#define DESC_RATEVHTSS4MCS9		0x53
++
++#define IS_CCK_HRATE(_rate)		((_rate) <= DESC_RATE11M)
++#define IS_OFDM_HRATE(_rate)	((_rate) >= DESC_RATE6M && (_rate) <= DESC_RATE54M)
++#define IS_LEGACY_HRATE(_rate)	((_rate) <= DESC_RATE54M)
++#define IS_HT_HRATE(_rate)		((_rate) >= DESC_RATEMCS0 && (_rate) <= DESC_RATEMCS31)
++#define IS_VHT_HRATE(_rate)		((_rate) >= DESC_RATEVHTSS1MCS0 && (_rate) <= DESC_RATEVHTSS4MCS9)
++
++#define IS_HT1SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS0 && (_rate) <= DESC_RATEMCS7)
++#define IS_HT2SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS8 && (_rate) <= DESC_RATEMCS15)
++#define IS_HT3SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS16 && (_rate) <= DESC_RATEMCS23)
++#define IS_HT4SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS24 && (_rate) <= DESC_RATEMCS31)
++
++#define IS_VHT1SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS1MCS0 && (_rate) <= DESC_RATEVHTSS1MCS9)
++#define IS_VHT2SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS2MCS0 && (_rate) <= DESC_RATEVHTSS2MCS9)
++#define IS_VHT3SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS3MCS0 && (_rate) <= DESC_RATEVHTSS3MCS9)
++#define IS_VHT4SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS4MCS0 && (_rate) <= DESC_RATEVHTSS4MCS9)
++
++#define IS_1SS_HRATE(_rate)	(IS_CCK_HRATE((_rate)) || IS_OFDM_HRATE((_rate)) || IS_HT1SS_HRATE((_rate)) || IS_VHT1SS_HRATE((_rate)))
++#define IS_2SS_HRATE(_rate)	(IS_HT2SS_HRATE((_rate)) || IS_VHT2SS_HRATE((_rate)))
++#define IS_3SS_HRATE(_rate)	(IS_HT3SS_HRATE((_rate)) || IS_VHT3SS_HRATE((_rate)))
++#define IS_4SS_HRATE(_rate)	(IS_HT4SS_HRATE((_rate)) || IS_VHT4SS_HRATE((_rate)))
++
++#define HRARE_SS_NUM(_rate) (IS_1SS_HRATE(_rate) ? 1 : (IS_2SS_HRATE(_rate) ? 2 : (IS_3SS_HRATE(_rate) ? 3 : (IS_4SS_HRATE(_rate) ? 4 : 0))))
++
++#define HDATA_RATE(rate)\
++	(rate == DESC_RATE1M) ? "CCK_1M" :\
++	(rate == DESC_RATE2M) ? "CCK_2M" :\
++	(rate == DESC_RATE5_5M) ? "CCK5_5M" :\
++	(rate == DESC_RATE11M) ? "CCK_11M" :\
++	(rate == DESC_RATE6M) ? "OFDM_6M" :\
++	(rate == DESC_RATE9M) ? "OFDM_9M" :\
++	(rate == DESC_RATE12M) ? "OFDM_12M" :\
++	(rate == DESC_RATE18M) ? "OFDM_18M" :\
++	(rate == DESC_RATE24M) ? "OFDM_24M" :\
++	(rate == DESC_RATE36M) ? "OFDM_36M" :\
++	(rate == DESC_RATE48M) ? "OFDM_48M" :\
++	(rate == DESC_RATE54M) ? "OFDM_54M" :\
++	(rate == DESC_RATEMCS0) ? "MCS0" :\
++	(rate == DESC_RATEMCS1) ? "MCS1" :\
++	(rate == DESC_RATEMCS2) ? "MCS2" :\
++	(rate == DESC_RATEMCS3) ? "MCS3" :\
++	(rate == DESC_RATEMCS4) ? "MCS4" :\
++	(rate == DESC_RATEMCS5) ? "MCS5" :\
++	(rate == DESC_RATEMCS6) ? "MCS6" :\
++	(rate == DESC_RATEMCS7) ? "MCS7" :\
++	(rate == DESC_RATEMCS8) ? "MCS8" :\
++	(rate == DESC_RATEMCS9) ? "MCS9" :\
++	(rate == DESC_RATEMCS10) ? "MCS10" :\
++	(rate == DESC_RATEMCS11) ? "MCS11" :\
++	(rate == DESC_RATEMCS12) ? "MCS12" :\
++	(rate == DESC_RATEMCS13) ? "MCS13" :\
++	(rate == DESC_RATEMCS14) ? "MCS14" :\
++	(rate == DESC_RATEMCS15) ? "MCS15" :\
++	(rate == DESC_RATEMCS16) ? "MCS16" :\
++	(rate == DESC_RATEMCS17) ? "MCS17" :\
++	(rate == DESC_RATEMCS18) ? "MCS18" :\
++	(rate == DESC_RATEMCS19) ? "MCS19" :\
++	(rate == DESC_RATEMCS20) ? "MCS20" :\
++	(rate == DESC_RATEMCS21) ? "MCS21" :\
++	(rate == DESC_RATEMCS22) ? "MCS22" :\
++	(rate == DESC_RATEMCS23) ? "MCS23" :\
++	(rate == DESC_RATEMCS24) ? "MCS24" :\
++	(rate == DESC_RATEMCS25) ? "MCS25" :\
++	(rate == DESC_RATEMCS26) ? "MCS26" :\
++	(rate == DESC_RATEMCS27) ? "MCS27" :\
++	(rate == DESC_RATEMCS28) ? "MCS28" :\
++	(rate == DESC_RATEMCS29) ? "MCS29" :\
++	(rate == DESC_RATEMCS30) ? "MCS30" :\
++	(rate == DESC_RATEMCS31) ? "MCS31" :\
++	(rate == DESC_RATEVHTSS1MCS0) ? "VHTSS1MCS0" :\
++	(rate == DESC_RATEVHTSS1MCS1) ? "VHTSS1MCS1" :\
++	(rate == DESC_RATEVHTSS1MCS2) ? "VHTSS1MCS2" :\
++	(rate == DESC_RATEVHTSS1MCS3) ? "VHTSS1MCS3" :\
++	(rate == DESC_RATEVHTSS1MCS4) ? "VHTSS1MCS4" :\
++	(rate == DESC_RATEVHTSS1MCS5) ? "VHTSS1MCS5" :\
++	(rate == DESC_RATEVHTSS1MCS6) ? "VHTSS1MCS6" :\
++	(rate == DESC_RATEVHTSS1MCS7) ? "VHTSS1MCS7" :\
++	(rate == DESC_RATEVHTSS1MCS8) ? "VHTSS1MCS8" :\
++	(rate == DESC_RATEVHTSS1MCS9) ? "VHTSS1MCS9" :\
++	(rate == DESC_RATEVHTSS2MCS0) ? "VHTSS2MCS0" :\
++	(rate == DESC_RATEVHTSS2MCS1) ? "VHTSS2MCS1" :\
++	(rate == DESC_RATEVHTSS2MCS2) ? "VHTSS2MCS2" :\
++	(rate == DESC_RATEVHTSS2MCS3) ? "VHTSS2MCS3" :\
++	(rate == DESC_RATEVHTSS2MCS4) ? "VHTSS2MCS4" :\
++	(rate == DESC_RATEVHTSS2MCS5) ? "VHTSS2MCS5" :\
++	(rate == DESC_RATEVHTSS2MCS6) ? "VHTSS2MCS6" :\
++	(rate == DESC_RATEVHTSS2MCS7) ? "VHTSS2MCS7" :\
++	(rate == DESC_RATEVHTSS2MCS8) ? "VHTSS2MCS8" :\
++	(rate == DESC_RATEVHTSS2MCS9) ? "VHTSS2MCS9" :\
++	(rate == DESC_RATEVHTSS3MCS0) ? "VHTSS3MCS0" :\
++	(rate == DESC_RATEVHTSS3MCS1) ? "VHTSS3MCS1" :\
++	(rate == DESC_RATEVHTSS3MCS2) ? "VHTSS3MCS2" :\
++	(rate == DESC_RATEVHTSS3MCS3) ? "VHTSS3MCS3" :\
++	(rate == DESC_RATEVHTSS3MCS4) ? "VHTSS3MCS4" :\
++	(rate == DESC_RATEVHTSS3MCS5) ? "VHTSS3MCS5" :\
++	(rate == DESC_RATEVHTSS3MCS6) ? "VHTSS3MCS6" :\
++	(rate == DESC_RATEVHTSS3MCS7) ? "VHTSS3MCS7" :\
++	(rate == DESC_RATEVHTSS3MCS8) ? "VHTSS3MCS8" :\
++	(rate == DESC_RATEVHTSS3MCS9) ? "VHTSS3MCS9" :\
++	(rate == DESC_RATEVHTSS4MCS0) ? "VHTSS4MCS0" :\
++	(rate == DESC_RATEVHTSS4MCS1) ? "VHTSS4MCS1" :\
++	(rate == DESC_RATEVHTSS4MCS2) ? "VHTSS4MCS2" :\
++	(rate == DESC_RATEVHTSS4MCS3) ? "VHTSS4MCS3" :\
++	(rate == DESC_RATEVHTSS4MCS4) ? "VHTSS4MCS4" :\
++	(rate == DESC_RATEVHTSS4MCS5) ? "VHTSS4MCS5" :\
++	(rate == DESC_RATEVHTSS4MCS6) ? "VHTSS4MCS6" :\
++	(rate == DESC_RATEVHTSS4MCS7) ? "VHTSS4MCS7" :\
++	(rate == DESC_RATEVHTSS4MCS8) ? "VHTSS4MCS8" :\
++	(rate == DESC_RATEVHTSS4MCS9) ? "VHTSS4MCS9" :\
++	"UNKNOWN"
++
++enum {
++	UP_LINK,
++	DOWN_LINK,
++};
++typedef enum _RT_MEDIA_STATUS {
++	RT_MEDIA_DISCONNECT = 0,
++	RT_MEDIA_CONNECT       = 1
++} RT_MEDIA_STATUS;
++
++#define MAX_DLFW_PAGE_SIZE			4096	/* @ page : 4k bytes */
++typedef enum _FIRMWARE_SOURCE {
++	FW_SOURCE_IMG_FILE = 0,
++	FW_SOURCE_HEADER_FILE = 1,		/* from header file */
++} FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
++
++typedef enum _CH_SW_USE_CASE {
++	CH_SW_USE_CASE_TDLS		= 0,
++	CH_SW_USE_CASE_MCC		= 1
++} CH_SW_USE_CASE;
++
++typedef enum _WAKEUP_REASON{
++	RX_PAIRWISEKEY					= 0x01,
++	RX_GTK							= 0x02,
++	RX_FOURWAY_HANDSHAKE			= 0x03,
++	RX_DISASSOC						= 0x04,
++	RX_DEAUTH						= 0x08,
++	RX_ARP_REQUEST					= 0x09,
++	FW_DECISION_DISCONNECT			= 0x10,
++	RX_MAGIC_PKT					= 0x21,
++	RX_UNICAST_PKT					= 0x22,
++	RX_PATTERN_PKT					= 0x23,
++	RTD3_SSID_MATCH					= 0x24,
++	RX_REALWOW_V2_WAKEUP_PKT		= 0x30,
++	RX_REALWOW_V2_ACK_LOST			= 0x31,
++	ENABLE_FAIL_DMA_IDLE			= 0x40,
++	ENABLE_FAIL_DMA_PAUSE			= 0x41,
++	RTIME_FAIL_DMA_IDLE				= 0x42,
++	RTIME_FAIL_DMA_PAUSE			= 0x43,
++	RX_PNO							= 0x55,
++	AP_OFFLOAD_WAKEUP				= 0x66,
++	CLK_32K_UNLOCK					= 0xFD,
++	CLK_32K_LOCK					= 0xFE
++}WAKEUP_REASON;
++
++/*
++ * Queue Select Value in TxDesc
++ *   */
++#define QSLT_BK							0x2/* 0x01 */
++#define QSLT_BE							0x0
++#define QSLT_VI							0x5/* 0x4 */
++#define QSLT_VO							0x7/* 0x6 */
++#define QSLT_BEACON						0x10
++#define QSLT_HIGH						0x11
++#define QSLT_MGNT						0x12
++#define QSLT_CMD						0x13
++
++/* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
++ * #define MAX_TX_QUEUE		9 */
++
++#define TX_SELE_HQ			BIT(0)		/* High Queue */
++#define TX_SELE_LQ			BIT(1)		/* Low Queue */
++#define TX_SELE_NQ			BIT(2)		/* Normal Queue */
++#define TX_SELE_EQ			BIT(3)		/* Extern Queue */
++
++#define PageNum_128(_Len)		(u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
++#define PageNum_256(_Len)		(u32)(((_Len)>>8) + ((_Len) & 0xFF ? 1 : 0))
++#define PageNum_512(_Len)		(u32)(((_Len)>>9) + ((_Len) & 0x1FF ? 1 : 0))
++#define PageNum(_Len, _Size)		(u32)(((_Len)/(_Size)) + ((_Len)&((_Size) - 1) ? 1 : 0))
++
++struct dbg_rx_counter {
++	u32	rx_pkt_ok;
++	u32	rx_pkt_crc_error;
++	u32	rx_pkt_drop;
++	u32	rx_ofdm_fa;
++	u32	rx_cck_fa;
++	u32	rx_ht_fa;
++};
++
++u8 rtw_hal_get_port(_adapter *adapter);
++
++#ifdef CONFIG_MBSSID_CAM
++	/*#define DBG_MBID_CAM_DUMP*/
++
++	void rtw_mbid_cam_init(struct dvobj_priv *dvobj);
++	void rtw_mbid_cam_deinit(struct dvobj_priv *dvobj);
++	void rtw_mbid_cam_reset(_adapter *adapter);
++	u8 rtw_get_max_mbid_cam_id(_adapter *adapter);
++	u8 rtw_get_mbid_cam_entry_num(_adapter *adapter);
++	int rtw_mbid_cam_cache_dump(void *sel, const char *fun_name , _adapter *adapter);
++	int rtw_mbid_cam_dump(void *sel, const char *fun_name, _adapter *adapter);
++	void rtw_mi_set_mbid_cam(_adapter *adapter);
++	u8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr);
++	void rtw_ap_set_mbid_num(_adapter *adapter, u8 ap_num);
++	void rtw_mbid_cam_enable(_adapter *adapter);
++#endif
++
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++	void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr);
++	void rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr);
++	#ifdef CONFIG_SWTIMER_BASED_TXBCN
++	u16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval);
++	#endif
++	void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode);
++#endif
++
++void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter);
++void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter);
++void rtw_reset_mac_rx_counters(_adapter *padapter);
++void rtw_reset_phy_rx_counters(_adapter *padapter);
++void rtw_reset_phy_trx_ok_counters(_adapter *padapter);
++
++#ifdef DBG_RX_COUNTER_DUMP
++	#define DUMP_DRV_RX_COUNTER	BIT0
++	#define DUMP_MAC_RX_COUNTER	BIT1
++	#define DUMP_PHY_RX_COUNTER	BIT2
++	#define DUMP_DRV_TRX_COUNTER_DATA	BIT3
++
++	void rtw_dump_phy_rxcnts_preprocess(_adapter *padapter, u8 rx_cnt_mode);
++	void rtw_dump_rx_counters(_adapter *padapter);
++#endif
++
++void dump_chip_info(HAL_VERSION	ChipVersion);
++
++#define BAND_CAP_2G			BIT0
++#define BAND_CAP_5G			BIT1
++#define BAND_CAP_BIT_NUM	2
++
++#define BW_CAP_5M		BIT0
++#define BW_CAP_10M		BIT1
++#define BW_CAP_20M		BIT2
++#define BW_CAP_40M		BIT3
++#define BW_CAP_80M		BIT4
++#define BW_CAP_160M		BIT5
++#define BW_CAP_80_80M	BIT6
++#define BW_CAP_BIT_NUM	7
++
++#define PROTO_CAP_11B		BIT0
++#define PROTO_CAP_11G		BIT1
++#define PROTO_CAP_11N		BIT2
++#define PROTO_CAP_11AC		BIT3
++#define PROTO_CAP_BIT_NUM	4
++
++#define WL_FUNC_P2P			BIT0
++#define WL_FUNC_MIRACAST	BIT1
++#define WL_FUNC_TDLS		BIT2
++#define WL_FUNC_FTM			BIT3
++#define WL_FUNC_BIT_NUM		4
++
++#define TBTT_PROHIBIT_SETUP_TIME 0x04 /* 128us, unit is 32us */
++#define TBTT_PROHIBIT_HOLD_TIME 0x80 /* 4ms, unit is 32us*/
++#define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64 /* 3.2ms unit is 32us*/
++
++int hal_spec_init(_adapter *adapter);
++void dump_hal_spec(void *sel, _adapter *adapter);
++
++bool hal_chk_band_cap(_adapter *adapter, u8 cap);
++bool hal_chk_bw_cap(_adapter *adapter, u8 cap);
++bool hal_chk_proto_cap(_adapter *adapter, u8 cap);
++bool hal_is_band_support(_adapter *adapter, u8 band);
++bool hal_is_bw_support(_adapter *adapter, u8 bw);
++bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode);
++bool hal_is_mimo_support(_adapter *adapter);
++u8 hal_largest_bw(_adapter *adapter, u8 in_bw);
++
++bool hal_chk_wl_func(_adapter *adapter, u8 func);
++
++void hal_com_config_channel_plan(
++		PADAPTER padapter,
++		char *hw_alpha2,
++		u8 hw_chplan,
++		char *sw_alpha2,
++		u8 sw_chplan,
++		BOOLEAN AutoLoadFail
++);
++
++int hal_config_macaddr(_adapter *adapter, bool autoload_fail);
++#ifdef RTW_HALMAC
++void rtw_hal_hw_port_enable(_adapter *adapter);
++void rtw_hal_hw_port_disable(_adapter *adapter);
++#endif
++
++BOOLEAN
++HAL_IsLegalChannel(
++		PADAPTER	Adapter,
++		u32			Channel
++);
++
++u8	MRateToHwRate(u8 rate);
++
++u8	hw_rate_to_m_rate(u8 rate);
++
++void	HalSetBrateCfg(
++		PADAPTER		Adapter,
++		u8			*mBratesOS,
++		u16			*pBrateCfg);
++
++BOOLEAN
++Hal_MappingOutPipe(
++		PADAPTER	pAdapter,
++		u8		NumOutPipe
++);
++
++void rtw_dump_fw_info(void *sel, _adapter *adapter);
++void rtw_restore_hw_port_cfg(_adapter *adapter);
++void rtw_mi_set_mac_addr(_adapter *adapter);/*set mac addr when hal_init for all iface*/
++void rtw_hal_dump_macaddr(void *sel, _adapter *adapter);
++
++void rtw_init_hal_com_default_value(PADAPTER Adapter);
++
++#ifdef CONFIG_FW_C2H_REG
++void c2h_evt_clear(_adapter *adapter);
++s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf);
++#endif
++
++#ifdef CONFIG_FW_C2H_PKT
++void rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len);
++void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len);
++#endif
++
++u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type);
++
++void rtw_hal_update_sta_wset(_adapter *adapter, struct sta_info *psta);
++s8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta);
++s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta);
++void rtw_hal_update_sta_ra_info(PADAPTER padapter, struct sta_info *psta);
++
++/* access HW only */
++u32 rtw_sec_read_cam(_adapter *adapter, u8 addr);
++void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata);
++void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key);
++void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key);
++void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id);
++bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id);
++
++u8 rtw_hal_rcr_check(_adapter *adapter, u32 check_bit);
++
++u8 rtw_hal_rcr_add(_adapter *adapter, u32 add);
++u8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear);
++void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action);
++
++void rtw_iface_enable_tsf_update(_adapter *adapter);
++void rtw_iface_disable_tsf_update(_adapter *adapter);
++void rtw_hal_periodic_tsf_update_chk(_adapter *adapter);
++void rtw_hal_periodic_tsf_update_end_timer_hdl(void *ctx);
++
++#if CONFIG_TX_AC_LIFETIME
++#define TX_ACLT_CONF_DEFAULT	0
++#define TX_ACLT_CONF_AP_M2U		1
++#define TX_ACLT_CONF_MESH		2
++#define TX_ACLT_CONF_NUM		3
++
++extern const char *const _tx_aclt_conf_str[];
++#define tx_aclt_conf_str(conf) (((conf) >= TX_ACLT_CONF_NUM) ? _tx_aclt_conf_str[TX_ACLT_CONF_NUM] : _tx_aclt_conf_str[(conf)])
++
++struct tx_aclt_conf_t {
++	u8 en;
++	u32 vo_vi;
++	u32 be_bk;
++};
++
++void dump_tx_aclt_force_val(void *sel, struct dvobj_priv *dvobj);
++void rtw_hal_set_tx_aclt_force_val(_adapter *adapter, struct tx_aclt_conf_t *input, u8 arg_num);
++void dump_tx_aclt_confs(void *sel, struct dvobj_priv *dvobj);
++void rtw_hal_set_tx_aclt_conf(_adapter *adapter, u8 conf_idx, struct tx_aclt_conf_t *input, u8 arg_num);
++void rtw_hal_update_tx_aclt(_adapter *adapter);
++#endif
++
++void hw_var_port_switch(_adapter *adapter);
++void rtw_var_set_basic_rate(PADAPTER padapter, u8 *val);
++u8 SetHwReg(PADAPTER padapter, u8 variable, u8 *val);
++void GetHwReg(PADAPTER padapter, u8 variable, u8 *val);
++void rtw_hal_check_rxfifo_full(_adapter *adapter);
++void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid);
++
++u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
++u8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
++
++u32
++MapCharToHexDigit(
++		char	chTmp
++);
++
++BOOLEAN
++GetHexValueFromString(
++			char		*szStr,
++			u32			*pu4bVal,
++			u32			*pu4bMove
++);
++
++BOOLEAN
++GetFractionValueFromString(
++			char	*szStr,
++			u8		*pInteger,
++			u8		*pFraction,
++			u32		*pu4bMove
++);
++
++BOOLEAN
++IsCommentString(
++			char		*szStr
++);
++
++BOOLEAN
++ParseQualifiedString(
++		char *In,
++		u32 *Start,
++		char *Out,
++		char LeftQualifier,
++		char RightQualifier
++);
++
++BOOLEAN
++GetU1ByteIntegerFromStringInDecimal(
++			char *Str,
++			u8 *pInt
++);
++
++BOOLEAN
++isAllSpaceOrTab(
++	u8	*data,
++	u8	size
++);
++
++void linked_info_dump(_adapter *padapter, u8 benable);
++#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
++	void rtw_get_raw_rssi_info(void *sel, _adapter *padapter);
++	void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel);
++#endif
++
++#ifdef DBG_RX_DFRAME_RAW_DATA
++	void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel);
++#endif
++void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe);
++#define		HWSET_MAX_SIZE			1024
++
++#ifdef CONFIG_EFUSE_CONFIG_FILE
++u32 Hal_readPGDataFromConfigFile(PADAPTER padapter);
++u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr);
++#endif /* CONFIG_EFUSE_CONFIG_FILE */
++
++int hal_efuse_macaddr_offset(_adapter *adapter);
++int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr);
++void rtw_dump_cur_efuse(PADAPTER padapter);
++
++#ifdef CONFIG_RF_POWER_TRIM
++	void rtw_bb_rf_gain_offset(_adapter *padapter);
++#endif /*CONFIG_RF_POWER_TRIM*/
++
++void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer);
++u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qsel);
++
++u8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta);
++u8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta);
++#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
++void rtw_hal_set_pathb_phase(_adapter *adapter, u8 phase_idx);
++#endif
++void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished);
++u8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter);
++
++#ifdef CONFIG_TSF_RESET_OFFLOAD
++int rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port);
++#endif
++u64 rtw_hal_get_tsftr_by_port(_adapter *adapter, u8 port);
++
++#ifdef CONFIG_TDLS
++	#ifdef CONFIG_TDLS_CH_SW
++		s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode);
++	#endif
++#endif
++#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
++s32 rtw_hal_set_wifi_btc_port_id_cmd(_adapter *adapter);
++#endif
++
++void rtw_lps_state_chk(_adapter *adapter, u8 ps_mode);
++
++#ifdef CONFIG_GPIO_API
++	u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num);
++	int rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh);
++	int rtw_hal_config_gpio(_adapter *adapter, u8 gpio_num, bool isOutput);
++	int rtw_hal_register_gpio_interrupt(_adapter *adapter, int gpio_num, void(*callback)(u8 level));
++	int rtw_hal_disable_gpio_interrupt(_adapter *adapter, int gpio_num);
++#endif
++
++s8 rtw_hal_ch_sw_iqk_info_search(_adapter *padapter, u8 central_chnl, u8 bw_mode);
++void rtw_hal_ch_sw_iqk_info_backup(_adapter *adapter);
++void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case);
++
++#ifdef CONFIG_GPIO_WAKEUP
++void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable);
++void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval);
++void rtw_hal_set_input_gpio(_adapter *padapter, u8 index);
++#define GPIO_OUTPUT_LOW		0
++#define GPIO_OUTPUT_HIGH	1
++#endif
++
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++	extern char *rtw_phy_file_path;
++	extern char rtw_phy_para_file_path[PATH_LENGTH_MAX];
++	#define GetLineFromBuffer(buffer)   strsep(&buffer, "\r\n")
++#endif
++
++void update_IOT_info(_adapter *padapter);
++#ifdef CONFIG_RTS_FULL_BW
++void rtw_set_rts_bw(_adapter *padapter);
++#endif/*CONFIG_RTS_FULL_BW*/
++
++void ResumeTxBeacon(_adapter *padapter);
++void StopTxBeacon(_adapter *padapter);
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	u8	rtw_hal_antdiv_before_linked(_adapter *padapter);
++	void	rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
++#endif
++
++#ifdef DBG_SEC_CAM_MOVE
++	void rtw_hal_move_sta_gk_to_dk(_adapter *adapter);
++	void rtw_hal_read_sta_dk_key(_adapter *adapter, u8 key_id);
++#endif
++
++#ifdef CONFIG_LPS_PG
++#define LPSPG_RSVD_PAGE_SET_MACID(_rsvd_pag, _value)		SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 0, 8, _value)/*used macid*/
++#define LPSPG_RSVD_PAGE_SET_MBSSCAMID(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 8, 8, _value)/*used BSSID CAM entry*/
++#define LPSPG_RSVD_PAGE_SET_PMC_NUM(_rsvd_pag, _value)		SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 16, 8, _value)/*Max used Pattern Match CAM entry*/
++#define LPSPG_RSVD_PAGE_SET_MU_RAID_GID(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 24, 8, _value)/*Max MU rate table Group ID*/
++#define LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 0, 8, _value)/*used Security CAM entry number*/
++#define LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 8, 8, _value)/*Txbuf used page number for fw offload*/
++#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID1(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 0, 8, _value)/*used Security CAM entry -1*/
++#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID2(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 8, 8, _value)/*used Security CAM entry -2*/
++#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID3(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 16, 8, _value)/*used Security CAM entry -3*/
++#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID4(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 24, 8, _value)/*used Security CAM entry -4*/
++#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID5(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 0, 8, _value)/*used Security CAM entry -5*/
++#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID6(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 8, 8, _value)/*used Security CAM entry -6*/
++#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID7(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 16, 8, _value)/*used Security CAM entry -7*/
++#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID8(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 24, 8, _value)/*used Security CAM entry -8*/
++enum lps_pg_hdl_id {
++	LPS_PG_INFO_CFG = 0,
++	LPS_PG_REDLEMEM,
++	LPS_PG_PHYDM_DIS,
++	LPS_PG_PHYDM_EN,
++};
++
++u8 rtw_hal_set_lps_pg_info_cmd(_adapter *adapter);
++u8 rtw_hal_set_lps_pg_info(_adapter *adapter);
++#endif
++
++int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, u32 page_num, u8 *buffer, u32 buffer_size);
++void rtw_hal_construct_beacon(_adapter *padapter, u8 *pframe, u32 *pLength);
++void rtw_hal_construct_NullFunctionData(PADAPTER, u8 *pframe, u32 *pLength,
++				u8 bQoS, u8 AC, u8 bEosp, u8 bForcePowerSave);
++
++bool _rtw_wow_chk_cap(_adapter *adapter, u8 cap);
++#ifdef CONFIG_WOWLAN
++struct rtl_wow_pattern {
++	u16	crc;
++	u8	type;
++	u32	mask[4];
++};
++void rtw_wow_pattern_cam_dump(_adapter *adapter);
++
++#ifdef CONFIG_WOW_PATTERN_HW_CAM
++void rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct  rtl_wow_pattern *context);
++void rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx);
++#endif
++
++struct rtw_ndp_info {
++	u8 enable:1;
++	u8 check_remote_ip:1; /* Need to Check Sender IP or not */
++	u8 rsvd:6;
++	u8 num_of_target_ip; /* Number of Check IP which NA query IP */
++	u8 target_link_addr[6]; /* DUT's MAC address */
++	u8 remote_ipv6_addr[16]; /* Just respond IP */
++	u8 target_ipv6_addr[16]; /* target IP */
++};
++#define REMOTE_INFO_CTRL_SET_VALD_EN(target, _value) \
++	SET_BITS_TO_LE_4BYTE(target + 0, 0, 8, _value)
++#define REMOTE_INFO_CTRL_SET_PTK_EN(target, _value) \
++	SET_BITS_TO_LE_4BYTE(target + 1, 0, 1, _value)
++#define REMOTE_INFO_CTRL_SET_GTK_EN(target, _value) \
++	SET_BITS_TO_LE_4BYTE(target + 1, 1, 1, _value)
++#define REMOTE_INFO_CTRL_SET_GTK_IDX(target, _value) \
++	SET_BITS_TO_LE_4BYTE(target + 2, 0, 8, _value)
++#endif /*CONFIG_WOWLAN*/
++
++void rtw_dump_phy_cap(void *sel, _adapter *adapter);
++void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num);
++#ifdef CONFIG_SUPPORT_FIFO_DUMP
++void rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 fifo_size);
++#endif
++
++#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++s32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id);
++s32 rtw_set_default_port_id(_adapter *adapter);
++s32 rtw_set_ps_rsvd_page(_adapter *adapter);
++
++#define get_dft_portid(adapter) (adapter_to_dvobj(adapter)->dft.port_id)
++#define get_dft_macid(adapter) (adapter_to_dvobj(adapter)->dft.mac_id)
++
++/*void rtw_search_default_port(_adapter *adapter);*/
++#endif
++
++#ifdef CONFIG_P2P_PS
++#ifdef RTW_HALMAC
++void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state);
++#endif
++#endif
++
++#ifdef RTW_CHANNEL_SWITCH_OFFLOAD
++void rtw_hal_switch_chnl_and_set_bw_offload(_adapter *adapter, u8 central_ch, u8 pri_ch_idx, u8 bw);
++#endif
++
++s16 translate_dbm_to_percentage(s16 signal);
++
++#ifdef CONFIG_SUPPORT_MULTI_BCN
++void rtw_ap_multi_bcn_cfg(_adapter *adapter);
++#endif
++
++#ifdef CONFIG_SWTIMER_BASED_TXBCN
++#ifdef CONFIG_BCN_RECOVERY
++u8 rtw_ap_bcn_recovery(_adapter *padapter);
++#endif
++#ifdef CONFIG_BCN_XMIT_PROTECT
++u8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms);
++#endif
++#endif /*CONFIG_SWTIMER_BASED_TXBCN*/
++
++#ifdef CONFIG_FW_HANDLE_TXBCN
++void rtw_ap_mbid_bcn_en(_adapter *adapter, u8 mbcn_id);
++void rtw_ap_mbid_bcn_dis(_adapter *adapter, u8 mbcn_id);
++#endif
++
++void rtw_hal_get_trx_path(struct dvobj_priv *d, enum rf_type *type,
++			 enum bb_path *tx, enum bb_path *rx);
++#ifdef CONFIG_BEAMFORMING
++#ifdef RTW_BEAMFORMING_VERSION_2
++void rtw_hal_beamforming_config_csirate(PADAPTER adapter);
++#endif
++#endif
++
++u8 phy_get_current_tx_num(PADAPTER pAdapter, u8 Rate);
++
++#ifdef CONFIG_RTL8812A
++u8 * rtw_hal_set_8812a_vendor_ie(_adapter *padapter , u8 *pframe ,uint *frlen );
++#endif
++
++#ifdef CONFIG_PROTSEL_PORT
++void rtw_enter_protsel_port(_adapter *padapter, u8 port_sel);
++bool rtw_assert_protsel_port(_adapter *padapter, u32 addr, u8 len);
++void rtw_leave_protsel_port(_adapter *padapter);
++#else
++static inline void rtw_enter_protsel_port(_adapter *padapter, u8 port_sel) {}
++static inline bool rtw_assert_protsel_port(_adapter *padapter, u32 addr, u8 len) {return true; }
++static inline void rtw_leave_protsel_port(_adapter *padapter) {}
++#endif
++#ifdef CONFIG_PROTSEL_ATIMDTIM
++void rtw_enter_protsel_atimdtim(_adapter *padapter, u8 port_sel);
++bool rtw_assert_protsel_atimdtim(_adapter *padapter, u32 addr, u8 len);
++void rtw_leave_protsel_atimdtim(_adapter *padapter);
++#else
++static inline void rtw_enter_protsel_atimdtim(_adapter *padapter, u8 port_sel) {}
++static inline bool rtw_assert_protsel_atimdtim(_adapter *padapter, u32 addr, u8 len) {return true; }
++static inline void rtw_leave_protsel_atimdtim(_adapter *padapter) {}
++#endif
++#ifdef CONFIG_PROTSEL_MACSLEEP
++void rtw_enter_protsel_macsleep(_adapter *padapter, u8 sel);
++bool rtw_assert_protsel_macsleep(_adapter *padapter, u32 addr, u8 len);
++void rtw_leave_protsel_macsleep(_adapter *padapter);
++#else
++static inline void rtw_enter_protsel_macsleep(_adapter *padapter, u8 port_sel) {}
++static inline bool rtw_assert_protsel_macsleep(_adapter *padapter, u32 addr, u8 len) {return true; }
++static inline void rtw_leave_protsel_macsleep(_adapter *padapter) {}
++#endif
++#endif /* __HAL_COMMON_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_com_h2c.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_com_h2c.h
+new file mode 100644
+index 000000000..6c3f6ce02
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_com_h2c.h
+@@ -0,0 +1,673 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __COMMON_H2C_H__
++#define __COMMON_H2C_H__
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
++ * ---------------------------------------------------------------------------------------------------------
++ * 88e, 8723b, 8812, 8821, 92e use the same FW code base */
++enum h2c_cmd {
++	/* Common Class: 000 */
++	H2C_RSVD_PAGE = 0x00,
++	H2C_MEDIA_STATUS_RPT = 0x01,
++	H2C_SCAN_ENABLE = 0x02,
++	H2C_KEEP_ALIVE = 0x03,
++	H2C_DISCON_DECISION = 0x04,
++	H2C_PSD_OFFLOAD = 0x05,
++	H2C_CUSTOMER_STR_REQ = 0x06,
++	H2C_TXPWR_IDX_OFFLOAD = 0x07,
++	H2C_AP_OFFLOAD = 0x08,
++	H2C_BCN_RSVDPAGE = 0x09,
++	H2C_PROBERSP_RSVDPAGE = 0x0A,
++	H2C_FCS_RSVDPAGE = 0x10,
++	H2C_FCS_INFO = 0x11,
++	H2C_AP_WOW_GPIO_CTRL = 0x13,
++#ifdef CONFIG_MCC_MODE
++	H2C_MCC_RQT_TSF = 0x15,
++	H2C_MCC_MACID_BITMAP = 0x16,
++	H2C_MCC_LOCATION = 0x10,
++	H2C_MCC_CTRL_V2 = 0x17,
++	H2C_MCC_CTRL = 0x18,
++	H2C_MCC_TIME_SETTING = 0x19,
++	H2C_MCC_IQK_PARAM = 0x1A,
++#endif /* CONFIG_MCC_MODE */
++	H2C_CHNL_SWITCH_OPER_OFFLOAD = 0x1C,
++	H2C_SINGLE_CHANNELSWITCH_V2 = 0x1D,
++
++	/* PoweSave Class: 001 */
++	H2C_SET_PWR_MODE = 0x20,
++	H2C_PS_TUNING_PARA = 0x21,
++	H2C_PS_TUNING_PARA2 = 0x22,
++	H2C_P2P_LPS_PARAM = 0x23,
++	H2C_P2P_PS_OFFLOAD = 0x24,
++	H2C_PS_SCAN_ENABLE = 0x25,
++	H2C_SAP_PS_ = 0x26,
++	H2C_INACTIVE_PS_ = 0x27, /* Inactive_PS */
++	H2C_FWLPS_IN_IPS_ = 0x28,
++#ifdef CONFIG_LPS_POFF
++	H2C_LPS_POFF_CTRL = 0x29,
++	H2C_LPS_POFF_PARAM = 0x2A,
++#endif
++#ifdef CONFIG_LPS_PG
++	H2C_LPS_PG_INFO = 0x2B,
++#endif
++
++#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++	H2C_DEFAULT_PORT_ID = 0x2C,
++#endif
++	/* Dynamic Mechanism Class: 010 */
++	H2C_MACID_CFG = 0x40,
++	H2C_TXBF = 0x41,
++	H2C_RSSI_SETTING = 0x42,
++	H2C_AP_REQ_TXRPT = 0x43,
++	H2C_INIT_RATE_COLLECT = 0x44,
++	H2C_IQ_CALIBRATION	= 0x45,
++
++	H2C_RA_MASK_3SS = 0x46,/* for 8814A */
++	H2C_RA_PARA_ADJUST = 0x47,/* CONFIG_RA_DBG_CMD */
++	H2C_DYNAMIC_TX_PATH = 0x48,/* for 8814A */
++
++	H2C_FW_TRACE_EN = 0x49,
++#ifdef RTW_PER_CMD_SUPPORT_FW
++	H2C_REQ_PER_RPT = 0x4e,
++#endif
++	/* BT Class: 011 */
++	H2C_B_TYPE_TDMA = 0x60,
++	H2C_BT_INFO = 0x61,
++	H2C_FORCE_BT_TXPWR = 0x62,
++	H2C_BT_IGNORE_WLANACT = 0x63,
++	H2C_DAC_SWING_VALUE = 0x64,
++	H2C_ANT_SEL_RSV = 0x65,
++	H2C_WL_OPMODE = 0x66,
++	H2C_BT_MP_OPER = 0x67,
++	H2C_BT_CONTROL = 0x68,
++	H2C_BT_WIFI_CTRL = 0x69,
++	H2C_BT_FW_PATCH = 0x6A,
++#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
++	H2C_BTC_WL_PORT_ID = 0x71,
++#endif
++	/* WOWLAN Class: 100 */
++	H2C_WOWLAN = 0x80,
++	H2C_REMOTE_WAKE_CTRL = 0x81,
++	H2C_AOAC_GLOBAL_INFO = 0x82,
++	H2C_AOAC_RSVD_PAGE = 0x83,
++	H2C_AOAC_RSVD_PAGE2 = 0x84,
++	H2C_D0_SCAN_OFFLOAD_CTRL = 0x85,
++	H2C_D0_SCAN_OFFLOAD_INFO = 0x86,
++	H2C_CHNL_SWITCH_OFFLOAD = 0x87,
++	H2C_AOAC_RSVDPAGE3 = 0x88,
++	H2C_GPIO_CUSTOM = 0x89,
++	H2C_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
++	H2C_P2P_OFFLOAD = 0x8B,
++#ifdef CONFIG_FW_HANDLE_TXBCN
++	H2C_FW_BCN_OFFLOAD = 0xBA,
++#endif
++	H2C_RESET_TSF = 0xC0,
++#ifdef CONFIG_FW_CORRECT_BCN
++	H2C_BCNHWSEQ = 0xC5,
++#endif
++	H2C_CUSTOMER_STR_W1 = 0xC6,
++	H2C_CUSTOMER_STR_W2 = 0xC7,
++	H2C_CUSTOMER_STR_W3 = 0xC8,
++#ifdef DBG_FW_DEBUG_MSG_PKT
++	H2C_FW_DBG_MSG_PKT = 0xE1,
++#endif /*DBG_FW_DEBUG_MSG_PKT*/
++	H2C_MAXID,
++};
++
++#define H2C_INACTIVE_PS_LEN		4
++#define H2C_RSVDPAGE_LOC_LEN		5
++#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++#define H2C_DEFAULT_PORT_ID_LEN		2
++#define H2C_MEDIA_STATUS_RPT_LEN		4
++#else
++#define H2C_MEDIA_STATUS_RPT_LEN		3
++#endif
++#define H2C_GPIO_CUSTOM_LEN		3
++#define H2C_KEEP_ALIVE_CTRL_LEN	2
++#define H2C_DISCON_DECISION_LEN		3
++#define H2C_AP_OFFLOAD_LEN		3
++#define H2C_AP_WOW_GPIO_CTRL_LEN	4
++#define H2C_AP_PS_LEN			2
++#define H2C_PWRMODE_LEN			7
++#define H2C_PSTUNEPARAM_LEN			4
++#define H2C_MACID_CFG_LEN		7
++#define H2C_BTMP_OPER_LEN			5
++#define H2C_WOWLAN_LEN			7
++#define H2C_REMOTE_WAKE_CTRL_LEN	3
++#define H2C_AOAC_GLOBAL_INFO_LEN	2
++#define H2C_AOAC_RSVDPAGE_LOC_LEN	7
++#define H2C_SCAN_OFFLOAD_CTRL_LEN	4
++#define H2C_BT_FW_PATCH_LEN			6
++#define H2C_RSSI_SETTING_LEN		4
++#define H2C_AP_REQ_TXRPT_LEN		3
++#define H2C_FORCE_BT_TXPWR_LEN		3
++#define H2C_BCN_RSVDPAGE_LEN		5
++#define H2C_PROBERSP_RSVDPAGE_LEN	5
++#define H2C_P2PRSVDPAGE_LOC_LEN	5
++#define H2C_P2P_OFFLOAD_LEN	3
++#ifdef CONFIG_MCC_MODE
++	#define H2C_MCC_CTRL_LEN			7
++#ifdef CONFIG_MCC_MODE_V2
++	#define H2C_MCC_LOCATION_LEN		7
++#else
++	#define H2C_MCC_LOCATION_LEN		3
++#endif
++	#define H2C_MCC_MACID_BITMAP_LEN	6
++	#define H2C_MCC_RQT_TSF_LEN		1
++	#define H2C_MCC_TIME_SETTING_LEN		6
++	#define H2C_MCC_IQK_PARAM_LEN		7
++#endif /* CONFIG_MCC_MODE */
++#ifdef CONFIG_LPS_PG
++#ifdef CONFIG_RTL8822C
++	#define H2C_LPS_PG_INFO_LEN		4
++#else
++	#define H2C_LPS_PG_INFO_LEN		2
++#endif
++	#define H2C_LPSPG_LEN			16
++#endif
++#ifdef CONFIG_LPS_POFF
++	#define H2C_LPS_POFF_CTRL_LEN		1
++	#define H2C_LPS_POFF_PARAM_LEN		5
++#endif
++
++#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
++#define H2C_BTC_WL_PORT_ID_LEN	1
++#endif
++
++#ifdef DBG_FW_DEBUG_MSG_PKT
++	#define H2C_FW_DBG_MSG_PKT_LEN	2
++#endif /*DBG_FW_DEBUG_MSG_PKT*/
++
++#define H2C_SINGLE_CHANNELSWITCH_V2_LEN 2
++
++#define eq_mac_addr(a, b)						(((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0)
++#define cp_mac_addr(des, src)					((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5])
++#define cpIpAddr(des, src)					((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3])
++
++
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++#define FW_WOWLAN_FUN_EN				BIT(0)
++#define FW_WOWLAN_PATTERN_MATCH			BIT(1)
++#define FW_WOWLAN_MAGIC_PKT				BIT(2)
++#define FW_WOWLAN_UNICAST				BIT(3)
++#define FW_WOWLAN_ALL_PKT_DROP			BIT(4)
++#define FW_WOWLAN_GPIO_ACTIVE			BIT(5)
++#define FW_WOWLAN_REKEY_WAKEUP			BIT(6)
++#define FW_WOWLAN_DEAUTH_WAKEUP			BIT(7)
++
++#define FW_WOWLAN_GPIO_WAKEUP_EN		BIT(0)
++#define FW_FW_PARSE_MAGIC_PKT			BIT(1)
++
++#define FW_REMOTE_WAKE_CTRL_EN			BIT(0)
++#define FW_REALWOWLAN_EN				BIT(5)
++
++#define FW_WOWLAN_KEEP_ALIVE_EN			BIT(0)
++#define FW_ADOPT_USER					BIT(1)
++#define FW_WOWLAN_KEEP_ALIVE_PKT_TYPE	BIT(2)
++
++#define FW_REMOTE_WAKE_CTRL_EN			BIT(0)
++#define FW_ARP_EN						BIT(1)
++#define FW_REALWOWLAN_EN				BIT(5)
++#define FW_WOW_FW_UNICAST_EN			BIT(7)
++
++#define FW_IPS_DISABLE_BBRF		BIT(0)
++#define FW_IPS_WRC				BIT(1)
++
++#endif /* CONFIG_WOWLAN */
++
++/* _RSVDPAGE_LOC_CMD_0x00 */
++#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++/* _MEDIA_STATUS_RPT_PARM_CMD_0x01 */
++#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
++#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 1, 1, (__Value))
++#define SET_H2CCMD_MSRRPT_PARM_MIRACAST(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 2, 1, (__Value))
++#define SET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 3, 1, (__Value))
++#define SET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 4, 4, (__Value))
++#define SET_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 1, 0, 8, (__Value))
++#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 2, 0, 8, (__Value))
++#define SET_H2CCMD_MSRRPT_PARM_PORT_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 3, 0, 3, (__Value))
++
++#define GET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd)		LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 0, 1)
++#define GET_H2CCMD_MSRRPT_PARM_MIRACAST(__pH2CCmd)		LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 2, 1)
++#define GET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(__pH2CCmd)	LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 3, 1)
++#define GET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd)			LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 4, 4)
++
++#define H2C_MSR_ROLE_RSVD	0
++#define H2C_MSR_ROLE_STA	1
++#define H2C_MSR_ROLE_AP		2
++#define H2C_MSR_ROLE_GC		3
++#define H2C_MSR_ROLE_GO		4
++#define H2C_MSR_ROLE_TDLS	5
++#define H2C_MSR_ROLE_ADHOC	6
++#define H2C_MSR_ROLE_MESH	7
++#define H2C_MSR_ROLE_MAX	8
++
++extern const char *const _h2c_msr_role_str[];
++#define h2c_msr_role_str(role) (((role) >= H2C_MSR_ROLE_MAX) ? _h2c_msr_role_str[H2C_MSR_ROLE_MAX] : _h2c_msr_role_str[(role)])
++
++#define H2C_MSR_FMT "%s %s%s"
++#define H2C_MSR_ARG(h2c_msr) \
++	GET_H2CCMD_MSRRPT_PARM_OPMODE((h2c_msr)) ? " C" : "", \
++	h2c_msr_role_str(GET_H2CCMD_MSRRPT_PARM_ROLE((h2c_msr))), \
++	GET_H2CCMD_MSRRPT_PARM_MIRACAST((h2c_msr)) ? (GET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK((h2c_msr)) ? " MSINK" : " MSRC") : ""
++
++s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, bool macid_ind, u8 macid_end);
++s32 rtw_hal_set_FwMediaStatusRpt_single_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid);
++s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, u8 macid_end);
++
++/* _KEEP_ALIVE_CMD_0x03 */
++#define SET_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
++#define SET_H2CCMD_KEEPALIVE_PARM_PORT_NUM(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 3, __Value)
++#define SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++
++/* _DISCONNECT_DECISION_CMD_0x04 */
++#define SET_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_H2CCMD_DISCONDECISION_PARM_TRY_BCN_FAIL_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
++#define SET_H2CCMD_DISCONDECISION_PARM_DISCONNECT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
++#define SET_H2CCMD_DISCONDECISION_PORT_NUM(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 3, __Value)
++#define SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
++#define SET_H2CCMD_DISCONDECISION_PARM_TRY_OK_BCN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++
++#ifdef CONFIG_RTW_CUSTOMER_STR
++#define RTW_CUSTOMER_STR_LEN 16
++#define RTW_CUSTOMER_STR_FMT "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x"
++#define RTW_CUSTOMER_STR_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \
++	((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9], ((u8 *)(x))[10], ((u8 *)(x))[11], \
++	((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15]
++
++/* H2C_CUSTOMER_STR_REQ  0x06 */
++#define H2C_CUSTOMER_STR_REQ_LEN 1
++#define SET_H2CCMD_CUSTOMER_STR_REQ_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
++s32 rtw_hal_h2c_customer_str_req(_adapter *adapter);
++s32 rtw_hal_customer_str_read(_adapter *adapter, u8 *cs);
++
++/* H2C_CUSTOMER_STR_W1 0xC6 */
++#define H2C_CUSTOMER_STR_W1_LEN 7
++#define SET_H2CCMD_CUSTOMER_STR_W1_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
++#define H2CCMD_CUSTOMER_STR_W1_BYTE0(__pH2CCmd)				(((u8 *)(__pH2CCmd)) + 1)
++
++/* H2C_CUSTOMER_STR_W2 0xC7 */
++#define H2C_CUSTOMER_STR_W2_LEN 7
++#define SET_H2CCMD_CUSTOMER_STR_W2_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
++#define H2CCMD_CUSTOMER_STR_W2_BYTE6(__pH2CCmd)				(((u8 *)(__pH2CCmd)) + 1)
++
++/* H2C_CUSTOMER_STR_W3 0xC8 */
++#define H2C_CUSTOMER_STR_W3_LEN 5
++#define SET_H2CCMD_CUSTOMER_STR_W3_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
++#define H2CCMD_CUSTOMER_STR_W3_BYTE12(__pH2CCmd)			(((u8 *)(__pH2CCmd)) + 1)
++s32 rtw_hal_h2c_customer_str_write(_adapter *adapter, const u8 *cs);
++s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs);
++#endif /* CONFIG_RTW_CUSTOMER_STR */
++
++#ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
++#define H2C_TXPWR_IDX_OFFLOAD_LEN 3
++#define SET_H2CCMD_TXPWR_IDX_CCK(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_H2CCMD_TXPWR_IDX_OFDM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd + 1, 0, 8, __Value)
++#define SET_H2CCMD_TXPWR_IDX_HT1SS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd  + 2, 0, 8, __Value)
++#endif
++
++/* _AP_Offload 0x08 */
++#define SET_H2CCMD_AP_WOWLAN_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++/* _BCN_RsvdPage	0x09 */
++#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_BCN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++/* _Probersp_RsvdPage 0x0a */
++#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_ProbeRsp(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++/* _Probersp_RsvdPage 0x13 */
++#define SET_H2CCMD_AP_WOW_GPIO_CTRL_INDEX(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
++#define SET_H2CCMD_AP_WOW_GPIO_CTRL_C2H_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
++#define SET_H2CCMD_AP_WOW_GPIO_CTRL_PLUS(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
++#define SET_H2CCMD_AP_WOW_GPIO_CTRL_HIGH_ACTIVE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
++#define SET_H2CCMD_AP_WOW_GPIO_CTRL_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
++#define SET_H2CCMD_AP_WOW_GPIO_CTRL_DURATION(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_H2CCMD_AP_WOW_GPIO_CTRL_C2H_DURATION(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++/* _AP_PS 0x26 */
++#define SET_H2CCMD_AP_WOW_PS_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_H2CCMD_AP_WOW_PS_32K_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_H2CCMD_AP_WOW_PS_RF(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
++#define SET_H2CCMD_AP_WOW_PS_DURATION(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++
++/* INACTIVE_PS 0x27, duration unit is TBTT */
++#define SET_H2CCMD_INACTIVE_PS_EN(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_H2CCMD_INACTIVE_IGNORE_PS(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_H2CCMD_INACTIVE_PERIOD_SCAN_EN(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
++#define SET_H2CCMD_INACTIVE_DISBBRF(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
++#define SET_H2CCMD_INACTIVE_PORT_NUM(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 3, __Value)	
++#define SET_H2CCMD_INACTIVE_PS_FREQ(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE(__pH2CCmd + 1, 0, 8, __Value)
++#define SET_H2CCMD_INACTIVE_PS_DURATION(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE(__pH2CCmd + 2, 0, 8, __Value)
++#define SET_H2CCMD_INACTIVE_PS_PERIOD_SCAN_TIME(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE(__pH2CCmd + 3, 0, 8, __Value)
++
++#ifdef CONFIG_LPS_POFF
++/*PARTIAL OFF Control 0x29*/
++#define SET_H2CCMD_LPS_POFF_CTRL_EN(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++/*PARTIAL OFF PARAM   0x2A*/
++#define SET_H2CCMD_LPS_POFF_PARAM_RDVLD(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_H2CCMD_LPS_POFF_PARAM_WRVLD(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_H2CCMD_LPS_POFF_PARAM_STARTADDL(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_H2CCMD_LPS_POFF_PARAM_STARTADDH(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
++#define SET_H2CCMD_LPS_POFF_PARAM_ENDADDL(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++#define SET_H2CCMD_LPS_POFF_PARAM_ENDADDH(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
++#endif
++
++#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
++/* DEFAULT PORT ID 0x2C*/
++#define SET_H2CCMD_DFTPID_PORT_ID(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 8, (__Value))
++#define SET_H2CCMD_DFTPID_MAC_ID(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 1, 0, 8, (__Value))
++#endif
++
++#ifdef CONFIG_MCC_MODE
++/* MCC LOC CMD 0x10 */
++#define SET_H2CCMD_MCC_RSVDPAGE_LOC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_H2CCMD_MCC_PWRIDX_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 0, 1, __Value)
++#define SET_H2CCMD_MCC_PWRIDX_OFFLOAD_RFNUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 4, 4, __Value)
++#define SET_H2CCMD_MCC_PWRIDX_RSVDPAGE_LOC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 4, 0, 8, __Value)
++
++/* MCC RQT TSF 0x15 */
++#define SET_H2CCMD_MCC_RQT_TSFX(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
++#define SET_H2CCMD_MCC_RQT_TSFY(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
++
++/* MCC MAC ID CMD 0x16 */
++#define SET_H2CCMD_MCC_MACID_BITMAP_L(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_H2CCMD_MCC_MACID_BITMAP_H(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++
++/* NEW MCC CTRL CMD 0x17 */
++#define SET_H2CCMD_MCC_CTRL_V2_ORDER(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
++#define SET_H2CCMD_MCC_CTRL_V2_TOTALNUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
++#define SET_H2CCMD_MCC_CTRL_V2_CENTRAL_CH(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_H2CCMD_MCC_CTRL_V2_PRIMARY_CH(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 4, __Value)
++#define SET_H2CCMD_MCC_CTRL_V2_BW(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 4, 4, __Value)
++#define SET_H2CCMD_MCC_CTRL_V2_DURATION(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_H2CCMD_MCC_CTRL_V2_ROLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 3, __Value)			
++#define SET_H2CCMD_MCC_CTRL_V2_INCURCH(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value)
++#define SET_H2CCMD_MCC_CTRL_V2_DIS_SW_RETRY(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 1, __Value)
++#define SET_H2CCMD_MCC_CTRL_V2_DISTXNULL(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 5, 1, __Value)
++#define SET_H2CCMD_MCC_CTRL_V2_C2HRPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 6, 2, __Value)
++#define SET_H2CCMD_MCC_CTRL_V2_TSFX(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 4, __Value)
++#define SET_H2CCMD_MCC_CTRL_V2_NULL_EARLY(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 4, 4, __Value)
++#define SET_H2CCMD_MCC_CTRL_V2_UPDATE_PARM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 7, 1, __Value)
++
++
++/* MCC CTRL CMD 0x18 */
++#define SET_H2CCMD_MCC_CTRL_ORDER(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
++#define SET_H2CCMD_MCC_CTRL_TOTALNUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
++#define SET_H2CCMD_MCC_CTRL_CHIDX(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_H2CCMD_MCC_CTRL_BW(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value)
++#define SET_H2CCMD_MCC_CTRL_BW40SC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 2, 3, __Value)
++#define SET_H2CCMD_MCC_CTRL_BW80SC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 5, 3, __Value)
++#define SET_H2CCMD_MCC_CTRL_DURATION(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_H2CCMD_MCC_CTRL_ROLE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 3, __Value)
++#define SET_H2CCMD_MCC_CTRL_INCURCH(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value)
++#define SET_H2CCMD_MCC_CTRL_RSVD0(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 4, __Value)
++#define SET_H2CCMD_MCC_CTRL_RSVD1(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
++#define SET_H2CCMD_MCC_CTRL_RFETYPE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 4, __Value)
++#define SET_H2CCMD_MCC_CTRL_DISTXNULL(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 4, 1, __Value)
++#define SET_H2CCMD_MCC_CTRL_C2HRPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 5, 2, __Value)
++#define SET_H2CCMD_MCC_CTRL_CHSCAN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 7, 1, __Value)
++
++/* MCC Time CMD 0x19 */
++#define SET_H2CCMD_MCC_TIME_SETTING_FW_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 7, __Value)
++#define SET_H2CCMD_MCC_TIME_SETTING_START_TIME(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define  SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 4, __Value)
++#define  SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 4, __Value)
++#define  SET_H2CCMD_MCC_TIME_SETTING_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 1, __Value)
++#define  SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 1, 7, __Value)
++
++/* MCC IQK CMD 0x1A */
++#define SET_H2CCMD_MCC_IQK_READY(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_H2CCMD_MCC_IQK_ORDER(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 4, __Value)
++#define SET_H2CCMD_MCC_IQK_PATH(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 2, __Value)
++#define SET_H2CCMD_MCC_IQK_RX_L(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_H2CCMD_MCC_IQK_RX_M1(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value)
++#define SET_H2CCMD_MCC_IQK_RX_M2(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 2, 6, __Value)
++#define SET_H2CCMD_MCC_IQK_RX_H(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 4, __Value)
++#define SET_H2CCMD_MCC_IQK_TX_L(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++#define SET_H2CCMD_MCC_IQK_TX_M1(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 3, __Value)
++#define SET_H2CCMD_MCC_IQK_TX_M2(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 3, 5, __Value)
++#define SET_H2CCMD_MCC_IQK_TX_H(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 6, __Value)
++#endif /* CONFIG_MCC_MODE */
++
++/* CHNL SWITCH OPER OFFLOAD 0x1C */
++#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_CH_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_MODE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 2, __Value)
++#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_40M_SC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 2, 3, __Value)
++#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_80M_SC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 5, 3, __Value)
++#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 2, 0, 4, __Value)
++
++/* H2C_SINGLE_CHANNELSWITCH_V2 = 0x1D */
++#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_CENTRAL_CH_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_PRIMARY_CH_IDX(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 4, __Value)
++#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_BW(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 4, 4, __Value)
++
++
++#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
++#define SET_H2CCMD_BTC_WL_PORT_ID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
++#endif
++
++/* _WoWLAN PARAM_CMD_0x80 */
++#define SET_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
++#define SET_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
++#define SET_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
++#define SET_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
++#define SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
++#define SET_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
++#define SET_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 7, __Value)
++#define SET_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 7, 1, __Value)
++#define SET_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 1, __Value)
++#define SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 1, 7, __Value)
++#define SET_H2CCMD_WOWLAN_DISABLE_UPHY(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 1, __Value)
++#define SET_H2CCMD_WOWLAN_HST2DEV_EN(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 1, 1, __Value)
++#define SET_H2CCMD_WOWLAN_GPIO_DURATION_MS(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 2, 1, __Value)
++#define SET_H2CCMD_WOWLAN_CHANGE_UNIT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 2, 1, __Value)
++#define SET_H2CCMD_WOWLAN_UNIT_FOR_UPHY_DISABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value)
++#define SET_H2CCMD_WOWLAN_TAKE_PDN_UPHY_DIS_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 1, __Value)
++#define SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 5, 1, __Value)
++#define SET_H2CCMD_WOWLAN_DEV2HST_EN(__pH2CCmd, __Value) 	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 7, 1, __Value)
++#define SET_H2CCMD_WOWLAN_TIME_FOR_UPHY_DISABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
++#define SET_H2CCMD_WOWLAN_RISE_HST2DEV(__pH2CCmd, __Value) 	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 2, 1, __Value)
++
++/* _REMOTE_WAKEUP_CMD_0x81 */
++#define SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
++#define SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
++#define SET_H2CCMD_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
++#define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
++#define SET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 1, __Value)
++#define SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 2, 1, __Value)
++#define SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 3, 1, __Value)
++
++#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 1, __Value)
++#define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_PARSING_UNTIL_WAKEUP(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 4, 1, __Value)
++
++/* AOAC_GLOBAL_INFO_0x82 */
++#define SET_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++
++/* AOAC_RSVDPAGE_LOC_0x83 */
++#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
++#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++#ifdef CONFIG_GTK_OL
++#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
++#endif /* CONFIG_GTK_OL */
++#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NDP_INFO(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 8, __Value)
++
++/* AOAC_RSVDPAGE_2_0x84 */
++
++/* AOAC_RSVDPAGE_3_0x88 */
++#ifdef CONFIG_PNO_SUPPORT
++#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NLO_INFO(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
++#endif
++#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_AOAC_REPORT(__pH2CCmd, __Value) \
++	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 8, __Value)
++
++#ifdef CONFIG_PNO_SUPPORT
++/* D0_Scan_Offload_Info_0x86 */
++#define SET_H2CCMD_AOAC_NLO_FUN_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd), 3, 1, __Value)
++#define SET_H2CCMD_AOAC_NLO_IPS_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd), 4, 1, __Value)
++#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_PACKET(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SCAN_INFO(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SSID_INFO(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#endif /* CONFIG_PNO_SUPPORT */
++
++/* _GPIO_CUSTOM_CMD_0x89 */
++#define SET_H2CCMD_CUSTOMERID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_H2CCMD_SPECIAL_WAKE_REASON(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_H2CCMD_CUSTOM_WAKE_REASON(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 1, __Value)
++
++#ifdef CONFIG_P2P_WOWLAN
++/* P2P_RsvdPage_0x8a */
++#define SET_H2CCMD_RSVDPAGE_LOC_P2P_BCN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_H2CCMD_RSVDPAGE_LOC_P2P_PROBE_RSP(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_H2CCMD_RSVDPAGE_LOC_P2P_NEGO_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_H2CCMD_RSVDPAGE_LOC_P2P_INVITE_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_H2CCMD_RSVDPAGE_LOC_P2P_PD_RSP(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++#endif /* CONFIG_P2P_WOWLAN */
++
++#ifdef CONFIG_LPS_PG
++#define SET_H2CCMD_LPSPG_SEC_CAM_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)/*SecurityCAM_En*/
++#define SET_H2CCMD_LPSPG_MBID_CAM_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)/*BSSIDCAM_En*/
++#define SET_H2CCMD_LPSPG_PMC_CAM_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)/*PatternMatchCAM_En*/
++#define SET_H2CCMD_LPSPG_MACID_SEARCH_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)/*MACIDSearch_En*/
++#define SET_H2CCMD_LPSPG_TXSC_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)/*TXSC_En*/
++#define SET_H2CCMD_LPSPG_MU_RATE_TB_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)/*MURateTable_En*/
++#define SET_H2CCMD_LPSPG_LOC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)/*Loc_LPS_PG*/
++#define SET_H2CCMD_LPSPG_DPK_INFO_LOC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)/*Loc_LPS_PG_DPK_info*/
++#define SET_H2CCMD_LPSPG_IQK_INFO_LOC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 0, 8, __Value)/*Loc_IQK_result*/
++#endif
++
++#ifdef DBG_FW_DEBUG_MSG_PKT
++#define SET_H2CCMD_FW_DBG_MSG_PKT_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)/*sniffer_dbg_en*/
++#define SET_H2CCMD_RSVDPAGE_LOC_FW_DBG_MSG_PKT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) /*loc_debug_packet*/
++#endif /*DBG_FW_DEBUG_MSG_PKT*/
++
++#ifdef DBG_RSVD_PAGE_CFG
++#define RSVD_PAGE_CFG(ops, v1, v2, v3)	\
++	RTW_INFO("=== [RSVD][%s]-NeedPage:%d, TotalPageNum:%d TotalPacketLen:%d ===\n",	\
++		ops, v1, v2, v3)
++#else
++#define RSVD_PAGE_CFG(ops, v1, v2, v3) do {} while (0)
++#endif
++
++/* ---------------------------------------------------------------------------------------------------------
++ * -------------------------------------------    Structure    --------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++typedef struct _RSVDPAGE_LOC {
++	u8 LocProbeRsp;
++	u8 LocPsPoll;
++	u8 LocNullData;
++	u8 LocQosNull;
++	u8 LocBTQosNull;
++#ifdef CONFIG_WOWLAN
++	u8 LocRemoteCtrlInfo;
++	u8 LocArpRsp;
++	u8 LocNbrAdv;
++	u8 LocGTKRsp;
++	u8 LocGTKInfo;
++	u8 LocProbeReq;
++	u8 LocNetList;
++#ifdef CONFIG_GTK_OL
++	u8 LocGTKEXTMEM;
++#endif /* CONFIG_GTK_OL */
++	u8 LocNDPInfo;
++	u8 LocAOACReport;
++#ifdef CONFIG_PNO_SUPPORT
++	u8 LocPNOInfo;
++	u8 LocScanInfo;
++	u8 LocSSIDInfo;
++	u8 LocProbePacket;
++#endif /* CONFIG_PNO_SUPPORT */
++#endif /* CONFIG_WOWLAN	 */
++	u8 LocApOffloadBCN;
++#ifdef CONFIG_P2P_WOWLAN
++	u8 LocP2PBeacon;
++	u8 LocP2PProbeRsp;
++	u8 LocNegoRsp;
++	u8 LocInviteRsp;
++	u8 LocPDRsp;
++#endif /* CONFIG_P2P_WOWLAN */
++#ifdef DBG_FW_DEBUG_MSG_PKT
++	u8 loc_fw_dbg_msg_pkt;
++#endif /*DBG_FW_DEBUG_MSG_PKT*/
++} RSVDPAGE_LOC, *PRSVDPAGE_LOC;
++
++struct rsvd_page_cache_t {
++	char *name;
++	u8 loc;
++	u8 page_num;
++	u8 *data;
++	u32 size;
++};
++
++bool rsvd_page_cache_update_all(struct rsvd_page_cache_t *cache, u8 loc
++	, u8 txdesc_len, u32 page_size, u8 *info, u32 info_len);
++bool rsvd_page_cache_update_data(struct rsvd_page_cache_t *cache, u8 *info
++	, u32 info_len);
++void rsvd_page_cache_free_data(struct rsvd_page_cache_t *cache);
++void rsvd_page_cache_free(struct rsvd_page_cache_t *cache);
++
++#endif
++void dump_TX_FIFO(PADAPTER padapter, u8 page_num, u16 page_size);
++u8 rtw_hal_set_fw_media_status_cmd(_adapter *adapter, u8 mstatus, u8 macid);
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++	/* WOW command function */
++	void rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable);
++	#ifdef CONFIG_P2P_WOWLAN
++		/* H2C 0x8A */
++		u8 rtw_hal_set_FwP2PRsvdPage_cmd(_adapter *adapter, PRSVDPAGE_LOC rsvdpageloc);
++		/* H2C 0x8B */
++		u8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter *adapter);
++	#endif /* CONFIG_P2P_WOWLAN */
++#endif
++
++#ifdef RTW_PER_CMD_SUPPORT_FW
++u8 rtw_hal_set_req_per_rpt_cmd(_adapter *adapter, u8 group_macid,
++			       u8 rpt_type, u32 macid_bitmap);
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_com_led.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_com_led.h
+new file mode 100644
+index 000000000..379c4fdd1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_com_led.h
+@@ -0,0 +1,437 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL_COMMON_LED_H_
++#define __HAL_COMMON_LED_H_
++
++#define NO_LED 0
++#define HW_LED 1
++
++#ifdef CONFIG_RTW_LED
++#define MSECS(t)        (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000)
++
++/* ********************************************************************************
++ *	LED Behavior Constant.
++ * ********************************************************************************
++ * Default LED behavior.
++ *   */
++#define LED_BLINK_NORMAL_INTERVAL	100
++#define LED_BLINK_SLOWLY_INTERVAL	200
++#define LED_BLINK_LONG_INTERVAL	400
++#define LED_INITIAL_INTERVAL		1800
++
++/* LED Customerization */
++
++/* NETTRONIX */
++#define LED_BLINK_NORMAL_INTERVAL_NETTRONIX	100
++#define LED_BLINK_SLOWLY_INTERVAL_NETTRONIX	2000
++
++/* PORNET */
++#define LED_BLINK_SLOWLY_INTERVAL_PORNET	1000
++#define LED_BLINK_NORMAL_INTERVAL_PORNET	100
++#define LED_BLINK_FAST_INTERVAL_BITLAND		30
++
++/* AzWave. */
++#define LED_CM2_BLINK_ON_INTERVAL		250
++#define LED_CM2_BLINK_OFF_INTERVAL		4750
++#define LED_CM8_BLINK_OFF_INTERVAL		3750	/* for QMI */
++
++/* RunTop */
++#define LED_RunTop_BLINK_INTERVAL		300
++
++/* ALPHA */
++#define LED_BLINK_NO_LINK_INTERVAL_ALPHA	1000
++#define LED_BLINK_NO_LINK_INTERVAL_ALPHA_500MS 500 /* add by ylb 20121012 for customer led for alpha */
++#define LED_BLINK_LINK_INTERVAL_ALPHA		500	/* 500 */
++#define LED_BLINK_SCAN_INTERVAL_ALPHA		180	/* 150 */
++#define LED_BLINK_FASTER_INTERVAL_ALPHA		50
++#define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA	5000
++
++/* 111122 by hpfan: Customized for Xavi */
++#define LED_CM11_BLINK_INTERVAL			300
++#define LED_CM11_LINK_ON_INTERVEL		3000
++
++/* Netgear */
++#define LED_BLINK_LINK_INTERVAL_NETGEAR		500
++#define LED_BLINK_LINK_SLOWLY_INTERVAL_NETGEAR		1000
++
++#define LED_WPS_BLINK_OFF_INTERVAL_NETGEAR		100
++#define LED_WPS_BLINK_ON_INTERVAL_NETGEAR		500
++
++/* Belkin AC950 */
++#define LED_BLINK_LINK_INTERVAL_ON_BELKIN		200
++#define LED_BLINK_LINK_INTERVAL_OFF_BELKIN		100
++#define LED_BLINK_ERROR_INTERVAL_BELKIN		100
++
++/* by chiyokolin for Azurewave */
++#define LED_CM12_BLINK_INTERVAL_5Mbps		160
++#define LED_CM12_BLINK_INTERVAL_10Mbps		80
++#define LED_CM12_BLINK_INTERVAL_20Mbps		50
++#define LED_CM12_BLINK_INTERVAL_40Mbps		40
++#define LED_CM12_BLINK_INTERVAL_80Mbps		30
++#define LED_CM12_BLINK_INTERVAL_MAXMbps		25
++
++/* Dlink */
++#define	LED_BLINK_NO_LINK_INTERVAL		1000
++#define	LED_BLINK_LINK_IDEL_INTERVAL		100
++
++#define	LED_BLINK_SCAN_ON_INTERVAL		30
++#define	LED_BLINK_SCAN_OFF_INTERVAL		300
++
++#define LED_WPS_BLINK_ON_INTERVAL_DLINK		30
++#define LED_WPS_BLINK_OFF_INTERVAL_DLINK			300
++#define LED_WPS_BLINK_LINKED_ON_INTERVAL_DLINK			5000
++
++/* ********************************************************************************
++ * LED object.
++ * ******************************************************************************** */
++
++typedef enum _LED_CTL_MODE {
++	LED_CTL_POWER_ON = 1,
++	LED_CTL_LINK = 2,
++	LED_CTL_NO_LINK = 3,
++	LED_CTL_TX = 4, /* unspecific data TX, including single & group addressed */
++	LED_CTL_RX = 5, /* unspecific data RX, including single & group addressed */
++	LED_CTL_UC_TX = 6, /* single addressed data TX */
++	LED_CTL_UC_RX = 7, /* single addressed data RX */
++	LED_CTL_BMC_TX = 8, /* group addressed data TX */
++	LED_CTL_BMC_RX = 9, /* group addressed data RX */
++	LED_CTL_SITE_SURVEY = 10,
++	LED_CTL_POWER_OFF = 11,
++	LED_CTL_START_TO_LINK = 12,
++	LED_CTL_START_WPS = 13,
++	LED_CTL_STOP_WPS = 14,
++	LED_CTL_START_WPS_BOTTON = 15, /* added for runtop */
++	LED_CTL_STOP_WPS_FAIL = 16, /* added for ALPHA	 */
++	LED_CTL_STOP_WPS_FAIL_OVERLAP = 17, /* added for BELKIN */
++	LED_CTL_CONNECTION_NO_TRANSFER = 18,
++} LED_CTL_MODE;
++
++typedef	enum _LED_STATE {
++	LED_UNKNOWN = 0,
++	RTW_LED_ON = 1,
++	RTW_LED_OFF = 2,
++	LED_BLINK_NORMAL = 3,
++	LED_BLINK_SLOWLY = 4,
++	LED_BLINK_POWER_ON = 5,
++	LED_BLINK_SCAN = 6,	/* LED is blinking during scanning period, the # of times to blink is depend on time for scanning. */
++	LED_BLINK_NO_LINK = 7, /* LED is blinking during no link state. */
++	LED_BLINK_StartToBlink = 8, /* Customzied for Sercomm Printer Server case */
++	LED_BLINK_TXRX = 9,
++	LED_BLINK_WPS = 10,	/* LED is blinkg during WPS communication */
++	LED_BLINK_WPS_STOP = 11,	/* for ALPHA */
++	LED_BLINK_WPS_STOP_OVERLAP = 12,	/* for BELKIN */
++	LED_BLINK_RUNTOP = 13,	/* Customized for RunTop */
++	LED_BLINK_CAMEO = 14,
++	LED_BLINK_XAVI = 15,
++	LED_BLINK_ALWAYS_ON = 16,
++	LED_BLINK_LINK_IN_PROCESS = 17,  /* Customized for Belkin AC950 */
++	LED_BLINK_AUTH_ERROR = 18,  /* Customized for Belkin AC950 */
++	LED_BLINK_Azurewave_5Mbps = 19,
++	LED_BLINK_Azurewave_10Mbps = 20,
++	LED_BLINK_Azurewave_20Mbps = 21,
++	LED_BLINK_Azurewave_40Mbps = 22,
++	LED_BLINK_Azurewave_80Mbps = 23,
++	LED_BLINK_Azurewave_MAXMbps = 24,
++	LED_BLINK_LINK_IDEL = 25,
++	LED_BLINK_WPS_LINKED = 26,
++} LED_STATE;
++
++typedef enum _LED_PIN {
++	LED_PIN_GPIO0,
++	LED_PIN_LED0,
++	LED_PIN_LED1,
++	LED_PIN_LED2
++} LED_PIN;
++
++
++/* ********************************************************************************
++ * PCIE LED Definition.
++ * ******************************************************************************** */
++#ifdef CONFIG_PCI_HCI
++typedef	enum _LED_STRATEGY_PCIE {
++	/* start from 2 */
++	SW_LED_MODE_UC_TRX_ONLY = 2,
++	SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
++	SW_LED_MODE1, /* SW control for PCI Express */
++	SW_LED_MODE2, /* SW control for Cameo. */
++	SW_LED_MODE3, /* SW contorl for RunTop. */
++	SW_LED_MODE4, /* SW control for Netcore */
++	SW_LED_MODE5, /* added by vivi, for led new mode, DLINK */
++	SW_LED_MODE6, /* added by vivi, for led new mode, PRONET */
++	SW_LED_MODE7, /* added by chiyokolin, for Lenovo, PCI Express Minicard Spec Rev.1.2 spec */
++	SW_LED_MODE8, /* added by chiyokolin, for QMI */
++	SW_LED_MODE9, /* added by chiyokolin, for BITLAND-LENOVO, PCI Express Minicard Spec Rev.1.1	 */
++	SW_LED_MODE10, /* added by chiyokolin, for Edimax-ASUS */
++	SW_LED_MODE11,	/* added by hpfan, for Xavi */
++	SW_LED_MODE12,	/* added by chiyokolin, for Azurewave */
++} LED_STRATEGY_PCIE, *PLED_STRATEGY_PCIE;
++
++typedef struct _LED_PCIE {
++	PADAPTER		padapter;
++
++	LED_PIN			LedPin;	/* Identify how to implement this SW led. */
++
++	LED_STATE		CurrLedState; /* Current LED state. */
++	BOOLEAN			bLedOn; /* TRUE if LED is ON, FALSE if LED is OFF. */
++
++	BOOLEAN			bLedBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */
++	BOOLEAN			bLedWPSBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */
++
++	BOOLEAN			bLedSlowBlinkInProgress;/* added by vivi, for led new mode */
++	u32				BlinkTimes; /* Number of times to toggle led state for blinking. */
++	LED_STATE		BlinkingLedState; /* Next state for blinking, either LED_ON or LED_OFF are. */
++
++	_timer			BlinkTimer; /* Timer object for led blinking. */
++} LED_PCIE, *PLED_PCIE;
++
++typedef struct _LED_PCIE	LED_DATA, *PLED_DATA;
++typedef enum _LED_STRATEGY_PCIE	LED_STRATEGY, *PLED_STRATEGY;
++
++void
++LedControlPCIE(
++		PADAPTER		Adapter,
++		LED_CTL_MODE		LedAction
++);
++
++void
++gen_RefreshLedState(
++		PADAPTER		Adapter);
++
++/* ********************************************************************************
++ * USB  LED Definition.
++ * ******************************************************************************** */
++#elif defined(CONFIG_USB_HCI)
++
++#define IS_LED_WPS_BLINKING(_LED_USB)	(((PLED_USB)_LED_USB)->CurrLedState == LED_BLINK_WPS \
++		|| ((PLED_USB)_LED_USB)->CurrLedState == LED_BLINK_WPS_STOP \
++		|| ((PLED_USB)_LED_USB)->bLedWPSBlinkInProgress)
++
++#define IS_LED_BLINKING(_LED_USB)	(((PLED_USB)_LED_USB)->bLedWPSBlinkInProgress \
++		|| ((PLED_USB)_LED_USB)->bLedScanBlinkInProgress)
++
++
++typedef	enum _LED_STRATEGY_USB {
++	/* start from 2 */
++	SW_LED_MODE_UC_TRX_ONLY = 2,
++	SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
++	SW_LED_MODE1, /* 2 LEDs, through LED0 and LED1. For ALPHA. */
++	SW_LED_MODE2, /* SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. */
++	SW_LED_MODE3, /* SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. */
++	SW_LED_MODE4, /* for Edimax / Belkin */
++	SW_LED_MODE5, /* for Sercomm / Belkin	 */
++	SW_LED_MODE6,	/* for 88CU minicard, porting from ce SW_LED_MODE7 */
++	SW_LED_MODE7,	/* for Netgear special requirement */
++	SW_LED_MODE8, /* for LC */
++	SW_LED_MODE9, /* for Belkin AC950 */
++	SW_LED_MODE10, /* for Netgear A6200V2 */
++	SW_LED_MODE11, /* for Edimax / ASUS */
++	SW_LED_MODE12, /* for WNC/NEC */
++	SW_LED_MODE13, /* for Netgear A6100, 8811Au */
++	SW_LED_MODE14, /* for Buffalo, DNI, 8811Au */
++	SW_LED_MODE15, /* for DLINK,  8811Au/8812AU	 */
++} LED_STRATEGY_USB, *PLED_STRATEGY_USB;
++
++
++typedef struct _LED_USB {
++	PADAPTER			padapter;
++
++	LED_PIN				LedPin;	/* Identify how to implement this SW led. */
++
++	LED_STATE			CurrLedState; /* Current LED state. */
++	BOOLEAN				bLedOn; /* TRUE if LED is ON, FALSE if LED is OFF. */
++
++	BOOLEAN				bSWLedCtrl;
++
++	BOOLEAN				bLedBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */
++	/* ALPHA, added by chiyoko, 20090106 */
++	BOOLEAN				bLedNoLinkBlinkInProgress;
++	BOOLEAN				bLedLinkBlinkInProgress;
++	BOOLEAN				bLedStartToLinkBlinkInProgress;
++	BOOLEAN				bLedScanBlinkInProgress;
++	BOOLEAN				bLedWPSBlinkInProgress;
++
++	u32					BlinkTimes; /* Number of times to toggle led state for blinking. */
++	u8					BlinkCounter; /* Added for turn off overlap led after blinking a while, by page, 20120821 */
++	LED_STATE			BlinkingLedState; /* Next state for blinking, either LED_ON or LED_OFF are. */
++
++	_timer				BlinkTimer; /* Timer object for led blinking. */
++
++	_workitem			BlinkWorkItem; /* Workitem used by BlinkTimer to manipulate H/W to blink LED.' */
++} LED_USB, *PLED_USB;
++
++typedef struct _LED_USB	LED_DATA, *PLED_DATA;
++typedef enum _LED_STRATEGY_USB	LED_STRATEGY, *PLED_STRATEGY;
++#ifdef CONFIG_RTW_SW_LED
++void
++LedControlUSB(
++		PADAPTER		Adapter,
++		LED_CTL_MODE		LedAction
++);
++#endif
++
++
++/* ********************************************************************************
++ * SDIO LED Definition.
++ * ******************************************************************************** */
++#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++
++#define IS_LED_WPS_BLINKING(_LED_SDIO)	(((PLED_SDIO)_LED_SDIO)->CurrLedState == LED_BLINK_WPS \
++		|| ((PLED_SDIO)_LED_SDIO)->CurrLedState == LED_BLINK_WPS_STOP \
++		|| ((PLED_SDIO)_LED_SDIO)->bLedWPSBlinkInProgress)
++
++#define IS_LED_BLINKING(_LED_SDIO)	(((PLED_SDIO)_LED_SDIO)->bLedWPSBlinkInProgress \
++		|| ((PLED_SDIO)_LED_SDIO)->bLedScanBlinkInProgress)
++
++
++typedef	enum _LED_STRATEGY_SDIO {
++	/* start from 2 */
++	SW_LED_MODE_UC_TRX_ONLY = 2,
++	SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
++	SW_LED_MODE1, /* 2 LEDs, through LED0 and LED1. For ALPHA. */
++	SW_LED_MODE2, /* SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. */
++	SW_LED_MODE3, /* SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. */
++	SW_LED_MODE4, /* for Edimax / Belkin */
++	SW_LED_MODE5, /* for Sercomm / Belkin	 */
++	SW_LED_MODE6,	/* for 88CU minicard, porting from ce SW_LED_MODE7 */
++} LED_STRATEGY_SDIO, *PLED_STRATEGY_SDIO;
++
++typedef struct _LED_SDIO {
++	PADAPTER			padapter;
++
++	LED_PIN				LedPin;	/* Identify how to implement this SW led. */
++
++	LED_STATE			CurrLedState; /* Current LED state. */
++	BOOLEAN				bLedOn; /* TRUE if LED is ON, FALSE if LED is OFF. */
++
++	BOOLEAN				bSWLedCtrl;
++
++	BOOLEAN				bLedBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */
++	/* ALPHA, added by chiyoko, 20090106 */
++	BOOLEAN				bLedNoLinkBlinkInProgress;
++	BOOLEAN				bLedLinkBlinkInProgress;
++	BOOLEAN				bLedStartToLinkBlinkInProgress;
++	BOOLEAN				bLedScanBlinkInProgress;
++	BOOLEAN				bLedWPSBlinkInProgress;
++
++	u32					BlinkTimes; /* Number of times to toggle led state for blinking. */
++	LED_STATE			BlinkingLedState; /* Next state for blinking, either LED_ON or LED_OFF are. */
++
++	_timer				BlinkTimer; /* Timer object for led blinking. */
++
++	_workitem			BlinkWorkItem; /* Workitem used by BlinkTimer to manipulate H/W to blink LED. */
++} LED_SDIO, *PLED_SDIO;
++
++typedef struct _LED_SDIO	LED_DATA, *PLED_DATA;
++typedef enum _LED_STRATEGY_SDIO	LED_STRATEGY, *PLED_STRATEGY;
++
++void
++LedControlSDIO(
++		PADAPTER		Adapter,
++		LED_CTL_MODE		LedAction
++);
++
++#endif
++
++struct led_priv {
++	LED_STRATEGY		LedStrategy;
++#ifdef CONFIG_RTW_SW_LED
++	LED_DATA			SwLed0;
++	LED_DATA			SwLed1;
++	LED_DATA			SwLed2;
++	u8					bRegUseLed;
++	u8 iface_en_mask;
++	u32 ctl_en_mask[CONFIG_IFACE_NUMBER];
++	void (*LedControlHandler)(_adapter *padapter, LED_CTL_MODE LedAction);
++	void (*SwLedOn)(_adapter *padapter, PLED_DATA pLed);
++	void (*SwLedOff)(_adapter *padapter, PLED_DATA pLed);
++#endif
++};
++
++#define SwLedOn(adapter, pLed) \
++	do { \
++		if (adapter_to_led(adapter)->SwLedOn) \
++			adapter_to_led(adapter)->SwLedOn((adapter), (pLed)); \
++	} while (0)
++
++#define SwLedOff(adapter, pLed) \
++	do { \
++		if (adapter_to_led(adapter)->SwLedOff) \
++			adapter_to_led(adapter)->SwLedOff((adapter), (pLed)); \
++	} while (0)
++
++void BlinkTimerCallback(void *data);
++void BlinkWorkItemCallback(_workitem *work);
++
++void ResetLedStatus(PLED_DATA pLed);
++
++void
++InitLed(
++	_adapter			*padapter,
++	PLED_DATA		pLed,
++	LED_PIN			LedPin
++);
++
++void
++DeInitLed(
++	PLED_DATA		pLed
++);
++
++/* hal... */
++extern void BlinkHandler(PLED_DATA	pLed);
++void dump_led_config(void *sel, _adapter *adapter);
++void rtw_led_set_strategy(_adapter *adapter, u8 strategy);
++#endif /* CONFIG_RTW_LED */
++
++#if defined(CONFIG_RTW_LED)
++#define rtw_led_get_strategy(adapter) (adapter_to_led(adapter)->LedStrategy)
++#else
++#define rtw_led_get_strategy(adapter) NO_LED
++#endif
++
++#define IS_NO_LED_STRATEGY(s) ((s) == NO_LED)
++#define IS_HW_LED_STRATEGY(s) ((s) == HW_LED)
++#define IS_SW_LED_STRATEGY(s) ((s) != NO_LED && (s) != HW_LED)
++
++#if defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED)
++
++#ifndef CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
++#define CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY 0
++#endif
++
++#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
++void rtw_sw_led_blink_uc_trx_only(LED_DATA *led);
++void rtw_sw_led_ctl_mode_uc_trx_only(_adapter *adapter, LED_CTL_MODE ctl);
++#endif
++void rtw_led_control(_adapter *adapter, LED_CTL_MODE ctl);
++void rtw_led_tx_control(_adapter *adapter, const u8 *da);
++void rtw_led_rx_control(_adapter *adapter, const u8 *da);
++void rtw_led_set_iface_en(_adapter *adapter, u8 en);
++void rtw_led_set_iface_en_mask(_adapter *adapter, u8 mask);
++void rtw_led_set_ctl_en_mask(_adapter *adapter, u32 ctl_mask);
++void rtw_led_set_ctl_en_mask_primary(_adapter *adapter);
++void rtw_led_set_ctl_en_mask_virtual(_adapter *adapter);
++#else
++#define rtw_led_control(adapter, ctl) do {} while (0)
++#define rtw_led_tx_control(adapter, da) do {} while (0)
++#define rtw_led_rx_control(adapter, da) do {} while (0)
++#define rtw_led_set_iface_en(adapter, en) do {} while (0)
++#define rtw_led_set_iface_en_mask(adapter, mask) do {} while (0)
++#define rtw_led_set_ctl_en_mask(adapter, ctl_mask) do {} while (0)
++#define rtw_led_set_ctl_en_mask_primary(adapter) do {} while (0)
++#define rtw_led_set_ctl_en_mask_virtual(adapter) do {} while (0)
++#endif /* defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED) */
++
++#endif /*__HAL_COMMON_LED_H_*/
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_com_phycfg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_com_phycfg.h
+new file mode 100644
+index 000000000..e2439ff9c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_com_phycfg.h
+@@ -0,0 +1,350 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL_COM_PHYCFG_H__
++#define __HAL_COM_PHYCFG_H__
++
++#ifndef DBG_TX_POWER_IDX
++#define DBG_TX_POWER_IDX 0
++#endif
++
++#define		PathA                     			0x0	/* Useless */
++#define		PathB			0x1
++#define		PathC			0x2
++#define		PathD			0x3
++
++typedef enum _RF_TX_NUM {
++	RF_1TX = 0,
++	RF_2TX,
++	RF_3TX,
++	RF_4TX,
++	RF_MAX_TX_NUM,
++	RF_TX_NUM_NONIMPLEMENT,
++} RF_TX_NUM;
++
++enum txpwr_pg_mode {
++	TXPWR_PG_WITH_PWR_IDX,
++	TXPWR_PG_WITH_TSSI_OFFSET,
++	TXPWR_PG_UNKNOWN, /* keep last */
++};
++
++/*------------------------------Define structure----------------------------*/
++typedef struct _BB_REGISTER_DEFINITION {
++	u32 rfintfs;			/* set software control: */
++	/*		0x870~0x877[8 bytes] */
++
++	u32 rfintfo; 			/* output data: */
++	/*		0x860~0x86f [16 bytes] */
++
++	u32 rfintfe; 			/* output enable: */
++	/*		0x860~0x86f [16 bytes] */
++
++	u32 rf3wireOffset;	/* LSSI data: */
++	/*		0x840~0x84f [16 bytes] */
++
++	u32 rfHSSIPara2;	/* wire parameter control2 :  */
++	/*		0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] */
++
++	u32 rfLSSIReadBack;	/* LSSI RF readback data SI mode */
++	/*		0x8a0~0x8af [16 bytes] */
++
++	u32 rfLSSIReadBackPi;	/* LSSI RF readback data PI mode 0x8b8-8bc for Path A and B */
++
++} BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
++
++
++/* ---------------------------------------------------------------------- */
++
++extern const char *const _txpwr_pg_mode_str[];
++#define txpwr_pg_mode_str(_mode) (((_mode) >= TXPWR_PG_UNKNOWN) ? _txpwr_pg_mode_str[TXPWR_PG_UNKNOWN] : _txpwr_pg_mode_str[(_mode)])
++
++u8 phy_get_target_txpwr(
++		PADAPTER		Adapter,
++		u8				Band,
++		u8				RfPath,
++		RATE_SECTION	RateSection
++);
++
++void
++PHY_GetRateValuesOfTxPowerByRate(
++		PADAPTER pAdapter,
++		u32 RegAddr,
++		u32 BitMask,
++		u32 Value,
++		u8 *Rate,
++		s8 *PwrByRateVal,
++		u8 *RateNum
++);
++
++u8
++PHY_GetRateIndexOfTxPowerByRate(
++		u8	Rate
++);
++
++void
++phy_set_tx_power_index_by_rate_section(
++		PADAPTER		pAdapter,
++		enum rf_path		RFPath,
++		u8				Channel,
++		u8				RateSection
++);
++
++s8
++_PHY_GetTxPowerByRate(
++		PADAPTER	pAdapter,
++		u8			Band,
++		enum rf_path	RFPath,
++		u8			RateIndex
++);
++
++s8
++PHY_GetTxPowerByRate(
++		PADAPTER	pAdapter,
++		u8			Band,
++		enum rf_path	RFPath,
++		RATE_SECTION rs,
++		enum MGN_RATE rate
++);
++
++void
++PHY_SetTxPowerByRate(
++		PADAPTER	pAdapter,
++		u8			Band,
++		enum rf_path	RFPath,
++		u8			Rate,
++		s8			Value
++);
++
++void
++phy_set_tx_power_level_by_path(
++		PADAPTER	Adapter,
++		u8			channel,
++		u8			path
++);
++
++void
++PHY_InitTxPowerByRate(
++		PADAPTER	pAdapter
++);
++
++void
++phy_store_tx_power_by_rate(
++		PADAPTER	pAdapter,
++		u32			Band,
++		u32			RfPath,
++		u32			TxNum,
++		u32			RegAddr,
++		u32			BitMask,
++		u32			Data
++);
++
++void
++PHY_TxPowerByRateConfiguration(
++	  PADAPTER			pAdapter
++);
++
++bool phy_chk_ch_setting_consistency(_adapter *adapter, u8 ch);
++
++#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
++u8 phy_get_pg_txpwr_idx(_adapter *pAdapter
++	, enum rf_path RFPath, RATE_SECTION rs, u8 ntx_idx
++	, enum channel_width BandWidth, u8 band, u8 Channel);
++#endif
++
++#if CONFIG_TXPWR_LIMIT
++s8 phy_get_txpwr_lmt(_adapter *adapter
++	, const char *regd_name
++	, BAND_TYPE band, enum channel_width bw
++	, u8 tlrs, u8 ntx_idx, u8 cch, u8 lock
++);
++
++s8 phy_get_txpwr_lmt_diff(_adapter *adapter
++	, const char *regd_name
++	, BAND_TYPE band, enum channel_width bw
++	, u8 rfpath, u8 rs, u8 tlrs, u8 ntx_idx, u8 cch, u8 lock
++);
++
++s8 phy_get_txpwr_lmt_sub_chs(_adapter *adapter
++	, const char *regd_name
++	, BAND_TYPE band, enum channel_width bw
++	, u8 rfpath, u8 rate, u8 ntx_idx, u8 cch, u8 opch
++);
++#else
++#define phy_get_txpwr_lmt(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max)
++#define phy_get_txpwr_lmt_diff(adapter, regd_name, band, bw, rfpath, rs, tlrs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max)
++#define phy_get_txpwr_lmt_sub_chs(adapter, regd_name, band, bw, rfpath, rate, ntx_idx, cch, opch) (GET_HAL_SPEC(adapter)->txgi_max)
++#endif /* CONFIG_TXPWR_LIMIT */
++
++s8 phy_get_txpwr_target(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate, u8 ntx_idx
++	, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch, struct txpwr_idx_comp *tic);
++s8 phy_get_txpwr_amends(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate, u8 ntx_idx
++	, enum channel_width bw, BAND_TYPE band, u8 cch, struct txpwr_idx_comp *tic);
++#ifdef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
++s8 phy_get_tssi_txpwr_by_rate_ref(_adapter *adapter, enum rf_path path
++	, enum channel_width bw, u8 cch, u8 opch);
++#endif
++u8 hal_com_get_txpwr_idx(_adapter *adapter, enum rf_path rfpath
++	, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch
++	, struct txpwr_idx_comp *tic);
++
++s16 phy_get_txpwr_single_mbm(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate
++	, enum channel_width bw, u8 cch, u8 opch, struct txpwr_idx_comp *tic);
++s16 phy_get_txpwr_total_mbm(_adapter *adapter, RATE_SECTION rs, u8 rate
++	, enum channel_width bw, u8 cch, u8 opch, struct txpwr_idx_comp *tic);
++
++s16 phy_get_txpwr_single_max_mbm(_adapter *adapter, u8 rfpath
++	, enum channel_width bw, u8 cch, u8 opch, u16 bmp_cck_ofdm, u32 bmp_ht, u64 bmp_vht);
++s16 phy_get_txpwr_total_max_mbm(_adapter *adapter
++	, enum channel_width bw, u8 cch, u8 opch, u16 bmp_cck_ofdm, u32 bmp_ht, u64 bmp_vht);
++
++s8
++phy_get_tx_power_final_absolute_value(_adapter *adapter, u8 rfpath, u8 rate,
++				      enum channel_width bw, u8 channel);
++
++s8
++PHY_GetTxPowerTrackingOffset(
++	PADAPTER	pAdapter,
++	enum rf_path	RFPath,
++	u8			Rate
++);
++
++struct txpwr_idx_comp {
++	u8 ntx_idx;
++	s8 target;
++	s8 base;
++
++	/* for target */
++	s8 by_rate;
++	s8 btc;
++	s8 extra;
++	s8 utarget;
++	s8 limit;
++	s8 ulimit;
++
++	/* for amends */
++	s8 tpt;
++	s8 dpd;
++};
++
++u8 phy_get_tx_power_index_ex(_adapter *adapter
++	, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate
++	, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch);
++
++u8
++phy_get_tx_power_index(
++		PADAPTER			pAdapter,
++		enum rf_path			RFPath,
++		u8					Rate,
++		enum channel_width	BandWidth,
++		u8					Channel
++);
++
++void
++PHY_SetTxPowerIndex(
++		PADAPTER		pAdapter,
++		u32				PowerIndex,
++		enum rf_path		RFPath,
++		u8				Rate
++);
++
++bool phy_is_txpwr_user_mbm_valid(_adapter *adapter, s16 mbm);
++bool phy_is_txpwr_user_target_specified(_adapter *adapter);
++
++void dump_tx_power_index_inline(void *sel, _adapter *adapter, u8 rfpath
++	, enum channel_width bw, u8 cch, enum MGN_RATE rate, u8 pwr_idx, struct txpwr_idx_comp *tic);
++void dump_tx_power_idx_title(void *sel, _adapter *adapter
++	, enum channel_width bw, u8 cch, u8 opch);
++void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath
++	, RATE_SECTION rs, enum channel_width bw, u8 cch, u8 opch);
++void dump_tx_power_idx(void *sel, _adapter *adapter
++	, enum channel_width bw, u8 cch, u8 opch);
++void dump_txpwr_total_dbm_title(void *sel, _adapter *adapter
++	, enum channel_width bw, u8 cch, u8 opch);
++void dump_txpwr_total_dbm_by_rs(void *sel, _adapter *adapter, u8 rs
++	, enum channel_width bw, u8 cch, u8 opch);
++void dump_txpwr_total_dbm(void *sel, _adapter *adapter
++	, enum channel_width bw, u8 cch, u8 opch);
++
++bool phy_is_tx_power_limit_needed(_adapter *adapter);
++bool phy_is_tx_power_by_rate_needed(_adapter *adapter);
++int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file);
++#if CONFIG_TXPWR_LIMIT
++int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file);
++#endif
++void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file);
++void phy_reload_tx_power_ext_info(_adapter *adapter);
++void phy_reload_default_tx_power_ext_info(_adapter *adapter);
++
++const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter);
++
++#ifdef CONFIG_EFUSE_CONFIG_FILE
++int check_phy_efuse_tx_power_info_valid(_adapter *adapter);
++#endif
++
++#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
++void dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt);
++void dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt);
++
++void hal_load_txpwr_info(_adapter *adapter);
++#endif
++
++void dump_tx_power_ext_info(void *sel, _adapter *adapter);
++void dump_target_tx_power(void *sel, _adapter *adapter);
++void dump_tx_power_by_rate(void *sel, _adapter *adapter);
++
++int rtw_get_phy_file_path(_adapter *adapter, const char *file_name);
++
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++#define MAC_FILE_FW_NIC			"FW_NIC.bin"
++#define MAC_FILE_FW_WW_IMG		"FW_WoWLAN.bin"
++#define PHY_FILE_MAC_REG		"MAC_REG.txt"
++
++#define PHY_FILE_AGC_TAB		"AGC_TAB.txt"
++#define PHY_FILE_PHY_REG		"PHY_REG.txt"
++#define PHY_FILE_PHY_REG_MP		"PHY_REG_MP.txt"
++#define PHY_FILE_PHY_REG_PG		"PHY_REG_PG.txt"
++
++#define PHY_FILE_RADIO_A		"RadioA.txt"
++#define PHY_FILE_RADIO_B		"RadioB.txt"
++#define PHY_FILE_RADIO_C		"RadioC.txt"
++#define PHY_FILE_RADIO_D		"RadioD.txt"
++#define PHY_FILE_TXPWR_TRACK	"TxPowerTrack.txt"
++#define PHY_FILE_TXPWR_LMT		"TXPWR_LMT.txt"
++
++#define PHY_FILE_WIFI_ANT_ISOLATION	"wifi_ant_isolation.txt"
++
++#define MAX_PARA_FILE_BUF_LEN	32768 /* 32k */
++
++#define LOAD_MAC_PARA_FILE				BIT0
++#define LOAD_BB_PARA_FILE					BIT1
++#define LOAD_BB_PG_PARA_FILE				BIT2
++#define LOAD_BB_MP_PARA_FILE				BIT3
++#define LOAD_RF_PARA_FILE					BIT4
++#define LOAD_RF_TXPWR_TRACK_PARA_FILE	BIT5
++#define LOAD_RF_TXPWR_LMT_PARA_FILE		BIT6
++
++int phy_ConfigMACWithParaFile(PADAPTER	Adapter, char	*pFileName);
++int phy_ConfigBBWithParaFile(PADAPTER	Adapter, char	*pFileName, u32	ConfigType);
++int phy_ConfigBBWithPgParaFile(PADAPTER	Adapter, const char *pFileName);
++int phy_ConfigBBWithMpParaFile(PADAPTER	Adapter, char	*pFileName);
++int PHY_ConfigRFWithParaFile(PADAPTER	Adapter, char	*pFileName, enum rf_path	eRFPath);
++int PHY_ConfigRFWithTxPwrTrackParaFile(PADAPTER	Adapter, char	*pFileName);
++#if CONFIG_TXPWR_LIMIT
++int PHY_ConfigRFWithPowerLimitTableParaFile(PADAPTER	Adapter, const char *pFileName);
++#endif
++void phy_free_filebuf_mask(_adapter *padapter, u8 mask);
++void phy_free_filebuf(_adapter *padapter);
++#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */
++u8 phy_check_under_survey_ch(_adapter *adapter);
++#endif /* __HAL_COMMON_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_com_reg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_com_reg.h
+new file mode 100755
+index 000000000..5219ba9c8
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_com_reg.h
+@@ -0,0 +1,1889 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL_COMMON_REG_H__
++#define __HAL_COMMON_REG_H__
++
++
++#define MAC_ADDR_LEN				6
++
++#define HAL_NAV_UPPER_UNIT		128		/* micro-second */
++
++/* 8188E PKT_BUFF_ACCESS_CTRL value */
++#define TXPKT_BUF_SELECT				0x69
++#define RXPKT_BUF_SELECT				0xA5
++#define TXREPORT_BUF_SELECT			0x7F
++#define DISABLE_TRXPKT_BUF_ACCESS		0x0
++
++#ifndef RTW_HALMAC
++/* ************************************************************
++*
++* ************************************************************ */
++
++/* -----------------------------------------------------
++*
++*	0x0000h ~ 0x00FFh	System Configuration
++*
++* ----------------------------------------------------- */
++#define REG_SYS_ISO_CTRL				0x0000
++#define REG_SYS_FUNC_EN				0x0002
++#define REG_APS_FSMCO					0x0004
++#define REG_SYS_CLKR					0x0008
++#define REG_SYS_CLK_CTRL				REG_SYS_CLKR
++#define REG_9346CR						0x000A
++#define REG_SYS_EEPROM_CTRL			0x000A
++#define REG_EE_VPD						0x000C
++#define REG_AFE_MISC					0x0010
++#define REG_SPS0_CTRL					0x0011
++#define REG_SPS0_CTRL_6					0x0016
++#define REG_POWER_OFF_IN_PROCESS		0x0017
++#define REG_SPS_OCP_CFG				0x0018
++#define REG_RSV_CTRL					0x001C
++#define REG_RF_CTRL						0x001F
++#define REG_LDOA15_CTRL				0x0020
++#define REG_LDOV12D_CTRL				0x0021
++#define REG_LDOHCI12_CTRL				0x0022
++#define REG_LPLDO_CTRL					0x0023
++#define REG_AFE_XTAL_CTRL				0x0024
++#define REG_AFE_LDO_CTRL				0x0027 /* 1.5v for 8188EE test chip, 1.4v for MP chip */
++#define REG_AFE_PLL_CTRL				0x0028
++#define REG_MAC_PHY_CTRL				0x002c /* for 92d, DMDP, SMSP, DMSP contrl */
++#define REG_APE_PLL_CTRL_EXT			0x002c
++#define REG_EFUSE_CTRL					0x0030
++#define REG_EFUSE_TEST					0x0034
++#define REG_PWR_DATA					0x0038
++#define REG_CAL_TIMER					0x003C
++#define REG_ACLK_MON					0x003E
++#define REG_GPIO_MUXCFG				0x0040
++#define REG_GPIO_IO_SEL					0x0042
++#define REG_MAC_PINMUX_CFG			0x0043
++#define REG_GPIO_PIN_CTRL				0x0044
++#define REG_GPIO_INTM					0x0048
++#define REG_LEDCFG0						0x004C
++#define REG_LEDCFG1						0x004D
++#define REG_LEDCFG2						0x004E
++#define REG_LEDCFG3						0x004F
++#define REG_FSIMR						0x0050
++#define REG_FSISR						0x0054
++#define REG_HSIMR						0x0058
++#define REG_HSISR						0x005c
++#define REG_GPIO_PIN_CTRL_2			0x0060 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
++#define REG_GPIO_IO_SEL_2				0x0062 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
++#define REG_PAD_CTRL_1				0x0064
++#define REG_MULTI_FUNC_CTRL			0x0068 /* RTL8723 WIFI/BT/GPS Multi-Function control source. */
++#define REG_GSSR						0x006c
++#define REG_AFE_XTAL_CTRL_EXT			0x0078 /* RTL8188E */
++#define REG_XCK_OUT_CTRL				0x007c /* RTL8188E */
++#define REG_MCUFWDL					0x0080
++#define REG_WOL_EVENT					0x0081 /* RTL8188E */
++#define REG_MCUTSTCFG					0x0084
++#define REG_FDHM0						0x0088
++#define REG_HOST_SUSP_CNT				0x00BC	/* RTL8192C Host suspend counter on FPGA platform */
++#define REG_SYSTEM_ON_CTRL			0x00CC	/* For 8723AE Reset after S3 */
++#define REG_EFUSE_ACCESS				0x00CF	/* Efuse access protection for RTL8723 */
++#define REG_BIST_SCAN					0x00D0
++#define REG_BIST_RPT					0x00D4
++#define REG_BIST_ROM_RPT				0x00D8
++#define REG_USB_SIE_INTF				0x00E0
++#define REG_PCIE_MIO_INTF				0x00E4
++#define REG_PCIE_MIO_INTD				0x00E8
++#define REG_HPON_FSM					0x00EC
++#define REG_SYS_CFG						0x00F0
++#define REG_GPIO_OUTSTS				0x00F4	/* For RTL8723 only. */
++#define REG_TYPE_ID						0x00FC
++
++/*
++* 2010/12/29 MH Add for 92D
++*   */
++#define REG_MAC_PHY_CTRL_NORMAL		0x00f8
++
++
++/* -----------------------------------------------------
++*
++*	0x0100h ~ 0x01FFh	MACTOP General Configuration
++*
++* ----------------------------------------------------- */
++#define REG_CR							0x0100
++#define REG_PBP							0x0104
++#define REG_PKT_BUFF_ACCESS_CTRL		0x0106
++#define REG_TRXDMA_CTRL				0x010C
++#define REG_TRXFF_BNDY					0x0114
++#define REG_TRXFF_STATUS				0x0118
++#define REG_RXFF_PTR					0x011C
++#define REG_HIMR						0x0120
++#define REG_FE1IMR						0x0120
++#define REG_HISR							0x0124
++#define REG_HIMRE						0x0128
++#define REG_HISRE						0x012C
++#define REG_CPWM						0x012F
++#define REG_FWIMR						0x0130
++#define REG_FWISR						0x0134
++#define REG_FTIMR						0x0138
++#define REG_FTISR						0x013C /* RTL8192C */
++#define REG_PKTBUF_DBG_CTRL			0x0140
++#define REG_RXPKTBUF_CTRL				(REG_PKTBUF_DBG_CTRL+2)
++#define REG_PKTBUF_DBG_DATA_L			0x0144
++#define REG_PKTBUF_DBG_DATA_H		0x0148
++
++#define REG_TC0_CTRL					0x0150
++#define REG_TC1_CTRL					0x0154
++#define REG_TC2_CTRL					0x0158
++#define REG_TC3_CTRL					0x015C
++#define REG_TC4_CTRL					0x0160
++#define REG_TCUNIT_BASE				0x0164
++#define REG_MBIST_START				0x0174
++#define REG_MBIST_DONE					0x0178
++#define REG_MBIST_FAIL					0x017C
++#define REG_32K_CTRL					0x0194 /* RTL8188E */
++#define REG_C2HEVT_MSG_NORMAL		0x01A0
++#define REG_C2HEVT_CLEAR				0x01AF
++#define REG_MCUTST_1					0x01c0
++#define REG_MCUTST_WOWLAN			0x01C7	/* Defined after 8188E series. */
++#define REG_FMETHR						0x01C8
++#define REG_HMETFR						0x01CC
++#define REG_HMEBOX_0					0x01D0
++#define REG_HMEBOX_1					0x01D4
++#define REG_HMEBOX_2					0x01D8
++#define REG_HMEBOX_3					0x01DC
++#define REG_LLT_INIT					0x01E0
++#define REG_HMEBOX_EXT_0				0x01F0
++#define REG_HMEBOX_EXT_1				0x01F4
++#define REG_HMEBOX_EXT_2				0x01F8
++#define REG_HMEBOX_EXT_3				0x01FC
++
++
++/* -----------------------------------------------------
++*
++*	0x0200h ~ 0x027Fh	TXDMA Configuration
++*
++* ----------------------------------------------------- */
++#define REG_RQPN						0x0200
++#define REG_FIFOPAGE					0x0204
++#define REG_TDECTRL						0x0208
++#define REG_TXDMA_OFFSET_CHK			0x020C
++#define REG_TXDMA_STATUS				0x0210
++#define REG_RQPN_NPQ					0x0214
++#define REG_TQPNT1						0x0218
++#define REG_TQPNT2						0x021C
++#define REG_AUTO_LLT					0x0224
++
++
++/* -----------------------------------------------------
++*
++*	0x0280h ~ 0x02FFh	RXDMA Configuration
++*
++* ----------------------------------------------------- */
++#define REG_RXDMA_AGG_PG_TH			0x0280
++#define REG_RXPKT_NUM					0x0284
++#define REG_RXDMA_STATUS				0x0288
++
++/* -----------------------------------------------------
++*
++*	0x0300h ~ 0x03FFh	PCIe
++*
++* ----------------------------------------------------- */
++#ifndef CONFIG_TRX_BD_ARCH	/* prevent CONFIG_TRX_BD_ARCH to use old registers */
++
++#define REG_PCIE_CTRL_REG				0x0300
++#define REG_INT_MIG					0x0304	/* Interrupt Migration */
++#define REG_BCNQ_DESA					0x0308	/* TX Beacon Descriptor Address */
++#define REG_HQ_DESA					0x0310	/* TX High Queue Descriptor Address */
++#define REG_MGQ_DESA					0x0318	/* TX Manage Queue Descriptor Address */
++#define REG_VOQ_DESA					0x0320	/* TX VO Queue Descriptor Address */
++#define REG_VIQ_DESA					0x0328	/* TX VI Queue Descriptor Address */
++#define REG_BEQ_DESA					0x0330	/* TX BE Queue Descriptor Address */
++#define REG_BKQ_DESA					0x0338	/* TX BK Queue Descriptor Address */
++#define REG_RX_DESA					0x0340	/* RX Queue Descriptor Address */
++/* sherry added for DBI Read/Write  20091126 */
++#define REG_DBI_WDATA					0x0348	/*  Backdoor REG for Access Configuration */
++#define REG_DBI_RDATA					0x034C	/* Backdoor REG for Access Configuration */
++#define REG_DBI_CTRL					0x0350	/* Backdoor REG for Access Configuration */
++#define REG_DBI_FLAG					0x0352	/* Backdoor REG for Access Configuration */
++#define REG_MDIO					0x0354	/* MDIO for Access PCIE PHY */
++#define REG_DBG_SEL					0x0360	/* Debug Selection Register */
++#define REG_WATCH_DOG					0x0368
++#define REG_RX_RXBD_NUM					0x0382
++
++/* RTL8723 series ------------------------------- */
++#define REG_PCIE_HISR_EN				0x0394	/* PCIE Local Interrupt Enable Register */
++#define REG_PCIE_HISR					0x03A0
++#define REG_PCIE_HISRE					0x03A4
++#define REG_PCIE_HIMR					0x03A8
++#define REG_PCIE_HIMRE					0x03AC
++
++#endif /* !CONFIG_TRX_BD_ARCH */
++
++#define REG_USB_HIMR					0xFE38
++#define REG_USB_HIMRE					0xFE3C
++#define REG_USB_HISR					0xFE78
++#define REG_USB_HISRE					0xFE7C
++
++
++/* -----------------------------------------------------
++*
++*	0x0400h ~ 0x047Fh	Protocol Configuration
++*
++* ----------------------------------------------------- */
++
++/* 92C, 92D */
++#define REG_VOQ_INFO	0x0400
++#define REG_VIQ_INFO	0x0404
++#define REG_BEQ_INFO	0x0408
++#define REG_BKQ_INFO	0x040C
++
++/* 88E, 8723A, 8812A, 8821A, 92E, 8723B */
++#define REG_Q0_INFO	0x400
++#define REG_Q1_INFO	0x404
++#define REG_Q2_INFO	0x408
++#define REG_Q3_INFO	0x40C
++
++#define REG_MGQ_INFO	0x0410
++#define REG_HGQ_INFO	0x0414
++#define REG_BCNQ_INFO	0x0418
++#define REG_TXPKT_EMPTY				0x041A
++#define REG_CPU_MGQ_INFORMATION		0x041C
++#define REG_FWHW_TXQ_CTRL				0x0420
++#define REG_HWSEQ_CTRL					0x0423
++#define REG_BCNQ_BDNY					0x0424
++#define REG_MGQ_BDNY					0x0425
++#define REG_LIFETIME_EN					0x0426
++#define REG_MULTI_BCNQ_OFFSET			0x0427
++#define REG_SPEC_SIFS					0x0428
++#define REG_RETRY_LIMIT					0x042A
++#define REG_DARFRC						0x0430
++#define REG_RARFRC						0x0438
++#define REG_RRSR						0x0440
++#define REG_ARFR0						0x0444
++#define REG_ARFR1						0x0448
++#define REG_ARFR2						0x044C
++#define REG_ARFR3						0x0450
++#define REG_CCK_CHECK					0x0454
++#define REG_BCNQ1_BDNY					0x0457
++
++#define REG_AGGLEN_LMT					0x0458
++#define REG_AMPDU_MIN_SPACE			0x045C
++#define REG_WMAC_LBK_BF_HD			0x045D
++#define REG_FAST_EDCA_CTRL				0x0460
++#define REG_RD_RESP_PKT_TH				0x0463
++
++/* 8723A, 8812A, 8821A, 92E, 8723B */
++#define REG_Q4_INFO	0x468
++#define REG_Q5_INFO	0x46C
++#define REG_Q6_INFO	0x470
++#define REG_Q7_INFO	0x474
++
++#define REG_INIRTS_RATE_SEL				0x0480
++#define REG_INIDATA_RATE_SEL			0x0484
++
++/* 8723B, 92E, 8812A, 8821A*/
++#define REG_MACID_SLEEP_3				0x0484
++#define REG_MACID_SLEEP_1				0x0488
++
++#define REG_POWER_STAGE1				0x04B4
++#define REG_POWER_STAGE2				0x04B8
++#define REG_PKT_LIFE_TIME			0x04C0
++#define REG_PKT_LIFE_TIME_VO_VI		0x04C0
++#define REG_PKT_LIFE_TIME_BE_BK		0x04C2
++#define REG_STBC_SETTING				0x04C4
++#define REG_QUEUE_CTRL					0x04C6
++#define REG_SINGLE_AMPDU_CTRL			0x04c7
++#define REG_PROT_MODE_CTRL			0x04C8
++#define REG_MAX_AGGR_NUM				0x04CA
++#define REG_RTS_MAX_AGGR_NUM			0x04CB
++#define REG_BAR_MODE_CTRL				0x04CC
++#define REG_RA_TRY_RATE_AGG_LMT		0x04CF
++
++/* 8723A */
++#define REG_MACID_DROP	0x04D0
++
++/* 88E */
++#define REG_EARLY_MODE_CONTROL	0x04D0
++
++/* 8723B, 92E, 8812A, 8821A */
++#define REG_MACID_SLEEP_2	0x04D0
++
++/* 8723A, 8723B, 92E, 8812A, 8821A */
++#define REG_MACID_SLEEP	0x04D4
++
++#define REG_NQOS_SEQ					0x04DC
++#define REG_HW_SEQ0						0x04D8
++#define REG_HW_SEQ1						0x04DA
++#define REG_HW_SEQ2						0x04DC
++#define REG_HW_SEQ3						0x04DE
++
++#define REG_QOS_SEQ					0x04DE
++#define REG_NEED_CPU_HANDLE			0x04E0
++#define REG_PKT_LOSE_RPT				0x04E1
++#define REG_PTCL_ERR_STATUS			0x04E2
++#define REG_TX_RPT_CTRL					0x04EC
++#define REG_TX_RPT_TIME					0x04F0	/* 2 byte */
++#define REG_DUMMY						0x04FC
++
++/* -----------------------------------------------------
++*
++*	0x0500h ~ 0x05FFh	EDCA Configuration
++*
++* ----------------------------------------------------- */
++#define REG_EDCA_VO_PARAM				0x0500
++#define REG_EDCA_VI_PARAM				0x0504
++#define REG_EDCA_BE_PARAM				0x0508
++#define REG_EDCA_BK_PARAM				0x050C
++#define REG_BCNTCFG						0x0510
++#define REG_PIFS							0x0512
++#define REG_RDG_PIFS					0x0513
++#define REG_SIFS_CTX					0x0514
++#define REG_SIFS_TRX					0x0516
++#define REG_TSFTR_SYN_OFFSET			0x0518
++#define REG_AGGR_BREAK_TIME			0x051A
++#define REG_SLOT						0x051B
++#define REG_TX_PTCL_CTRL				0x0520
++#define REG_TXPAUSE						0x0522
++#define REG_DIS_TXREQ_CLR				0x0523
++#define REG_RD_CTRL						0x0524
++/*
++* Format for offset 540h-542h:
++*	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
++*	[7:4]:   Reserved.
++*	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
++*	[23:20]: Reserved
++* Description:
++*	              |
++*      |<--Setup--|--Hold------------>|
++*   --------------|----------------------
++*                 |
++*                TBTT
++* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
++* Described by Designer Tim and Bruce, 2011-01-14.
++*   */
++#define REG_TBTT_PROHIBIT				0x0540
++#define REG_RD_NAV_NXT					0x0544
++#define REG_NAV_PROT_LEN				0x0546
++#define REG_BCN_CTRL					0x0550
++#define REG_BCN_CTRL_1					0x0551
++#define REG_MBID_NUM					0x0552
++#define REG_DUAL_TSF_RST				0x0553
++#define REG_MBSSID_BCN_SPACE			0x0554
++#define REG_DRVERLYINT					0x0558
++#define REG_BCNDMATIM					0x0559
++#define REG_ATIMWND					0x055A
++#define REG_USTIME_TSF					0x055C
++#define REG_BCN_MAX_ERR				0x055D
++#define REG_RXTSF_OFFSET_CCK			0x055E
++#define REG_RXTSF_OFFSET_OFDM			0x055F
++#define REG_TSFTR						0x0560
++#define REG_TSFTR1						0x0568	/* HW Port 1 TSF Register */
++#define REG_ATIMWND_1					0x0570
++#define REG_P2P_CTWIN					0x0572 /* 1 Byte long (in unit of TU) */
++#define REG_PSTIMER						0x0580
++#define REG_TIMER0						0x0584
++#define REG_TIMER1						0x0588
++#define REG_HIQ_NO_LMT_EN				0x05A7
++#define REG_ACMHWCTRL					0x05C0
++#define REG_NOA_DESC_SEL				0x05CF
++#define REG_NOA_DESC_DURATION		0x05E0
++#define REG_NOA_DESC_INTERVAL			0x05E4
++#define REG_NOA_DESC_START			0x05E8
++#define REG_NOA_DESC_COUNT			0x05EC
++
++#define REG_DMC							0x05F0	/* Dual MAC Co-Existence Register */
++#define REG_SCH_TX_CMD					0x05F8
++
++#define REG_FW_RESET_TSF_CNT_1		0x05FC
++#define REG_FW_RESET_TSF_CNT_0		0x05FD
++#define REG_FW_BCN_DIS_CNT			0x05FE
++
++/* -----------------------------------------------------
++*
++*	0x0600h ~ 0x07FFh	WMAC Configuration
++*
++* ----------------------------------------------------- */
++#define REG_APSD_CTRL					0x0600
++#define REG_BWOPMODE					0x0603
++#define REG_TCR							0x0604
++#define REG_RCR							0x0608
++#define REG_RX_PKT_LIMIT				0x060C
++#define REG_RX_DLK_TIME				0x060D
++#define REG_RX_DRVINFO_SZ				0x060F
++
++#define REG_MACID						0x0610
++#define REG_BSSID						0x0618
++#define REG_MAR							0x0620
++#define REG_MBIDCAMCFG_1				0x0628
++#define REG_MBIDCAMCFG_2				0x062C
++
++#define REG_PNO_STATUS					0x0631
++#define REG_USTIME_EDCA				0x0638
++#define REG_MAC_SPEC_SIFS				0x063A
++/* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */
++#define REG_RESP_SIFS_CCK				0x063C	/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */
++#define REG_RESP_SIFS_OFDM                    0x063E	/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */
++
++#define REG_ACKTO						0x0640
++#define REG_CTS2TO						0x0641
++#define REG_EIFS							0x0642
++
++/*REG_TCR*/
++#define BIT_PWRBIT_OW_EN BIT(7)
++
++/* RXERR_RPT */
++#define RXERR_TYPE_OFDM_PPDU			0
++#define RXERR_TYPE_OFDM_FALSE_ALARM	1
++#define RXERR_TYPE_OFDM_MPDU_OK		2
++#define RXERR_TYPE_OFDM_MPDU_FAIL	3
++#define RXERR_TYPE_CCK_PPDU			4
++#define RXERR_TYPE_CCK_FALSE_ALARM	5
++#define RXERR_TYPE_CCK_MPDU_OK		6
++#define RXERR_TYPE_CCK_MPDU_FAIL		7
++#define RXERR_TYPE_HT_PPDU				8
++#define RXERR_TYPE_HT_FALSE_ALARM	9
++#define RXERR_TYPE_HT_MPDU_TOTAL		10
++#define RXERR_TYPE_HT_MPDU_OK			11
++#define RXERR_TYPE_HT_MPDU_FAIL		12
++#define RXERR_TYPE_RX_FULL_DROP		15
++
++#define RXERR_COUNTER_MASK			0xFFFFF
++#define RXERR_RPT_RST					BIT(27)
++#define _RXERR_RPT_SEL(type)			((type) << 28)
++
++/*
++* Note:
++*	The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is
++*	always too small, but the WiFi TestPlan test by 25,000 microseconds of NAV through sending
++*	CTS in the air. We must update this value greater than 25,000 microseconds to pass the item.
++*	The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented
++*	by SD1 Scott.
++* By Bruce, 2011-07-18.
++*   */
++#define REG_NAV_UPPER					0x0652	/* unit of 128 */
++
++/* WMA, BA, CCX */
++#define REG_NAV_CTRL					0x0650
++#define REG_BACAMCMD					0x0654
++#define REG_BACAMCONTENT				0x0658
++#define REG_LBDLY						0x0660
++#define REG_FWDLY						0x0661
++#define REG_RXERR_RPT					0x0664
++#define REG_WMAC_TRXPTCL_CTL			0x0668
++
++/* Security */
++#define REG_CAMCMD						0x0670
++#define REG_CAMWRITE					0x0674
++#define REG_CAMREAD					0x0678
++#define REG_CAMDBG						0x067C
++#define REG_SECCFG						0x0680
++
++/* Power */
++#define REG_WOW_CTRL					0x0690
++#define REG_PS_RX_INFO					0x0692
++#define REG_WMMPS_UAPSD_TID			0x0693
++#define REG_WKFMCAM_CMD				0x0698
++#define REG_WKFMCAM_NUM				REG_WKFMCAM_CMD
++#define REG_WKFMCAM_RWD				0x069C
++#define REG_RXFLTMAP0					0x06A0
++#define REG_RXFLTMAP1					0x06A2
++#define REG_RXFLTMAP2					0x06A4
++#define REG_BCN_PSR_RPT				0x06A8
++#define REG_BT_COEX_TABLE				0x06C0
++
++#define BIT_WKFCAM_WE					BIT(16)
++#define BIT_WKFCAM_POLLING_V1				BIT(31)
++#define BIT_WKFCAM_CLR_V1				BIT(30)
++#define BIT_SHIFT_WKFCAM_ADDR_V2			8
++#define BIT_MASK_WKFCAM_ADDR_V2			0xff
++#define BIT_WKFCAM_ADDR_V2(x)				(((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2)
++
++/* Hardware Port 1 */
++#define REG_MACID1						0x0700
++#define REG_BSSID1						0x0708
++
++/* Enable/Disable Port 0 and Port 1 for Specific ICs (ex. 8192F)*/
++#define REG_WLAN_ACT_MASK_CTRL_1		0x076C
++
++/* GPIO Control */
++#define REG_SW_GPIO_SHARE_CTRL_0		0x1038
++#define REG_SW_GPIO_SHARE_CTRL_1		0x103C
++#define REG_SW_GPIO_A_OUT				0x1040
++#define REG_SW_GPIO_A_OEN				0x1044
++#define REG_SW_GPIO_B_OEN				0x1058
++#define REG_SW_GPIO_B_OUT				0x105C
++
++/* Hardware Port 2 */
++#define REG_MACID2						0x1620
++#define REG_BSSID2						0x1628
++/* Hardware Port 3*/
++#define REG_MACID3						0x1630
++#define REG_BSSID3						0x1638
++/* Hardware Port 4 */
++#define REG_MACID4						0x1640
++#define REG_BSSID4						0x1648
++
++
++#define REG_CR_EXT						0x1100
++
++/* -----------------------------------------------------
++*
++*	0xFE00h ~ 0xFE55h	USB Configuration
++*
++* ----------------------------------------------------- */
++#define REG_USB_INFO					0xFE17
++#define REG_USB_SPECIAL_OPTION		0xFE55
++#define REG_USB_DMA_AGG_TO			0xFE5B
++#define REG_USB_AGG_TO					0xFE5C
++#define REG_USB_AGG_TH					0xFE5D
++
++#define REG_USB_HRPWM					0xFE58
++#define REG_USB_HCPWM					0xFE57
++
++/* for 92DU high_Queue low_Queue Normal_Queue select */
++#define REG_USB_High_NORMAL_Queue_Select_MAC0	0xFE44
++/* #define REG_USB_LOW_Queue_Select_MAC0		0xFE45 */
++#define REG_USB_High_NORMAL_Queue_Select_MAC1	0xFE47
++/* #define REG_USB_LOW_Queue_Select_MAC1		0xFE48 */
++
++/* For test chip */
++#define REG_TEST_USB_TXQS				0xFE48
++#define REG_TEST_SIE_VID				0xFE60		/* 0xFE60~0xFE61 */
++#define REG_TEST_SIE_PID				0xFE62		/* 0xFE62~0xFE63 */
++#define REG_TEST_SIE_OPTIONAL			0xFE64
++#define REG_TEST_SIE_CHIRP_K			0xFE65
++#define REG_TEST_SIE_PHY				0xFE66		/* 0xFE66~0xFE6B */
++#define REG_TEST_SIE_MAC_ADDR			0xFE70		/* 0xFE70~0xFE75 */
++#define REG_TEST_SIE_STRING			0xFE80		/* 0xFE80~0xFEB9 */
++
++
++/* For normal chip */
++#define REG_NORMAL_SIE_VID				0xFE60		/* 0xFE60~0xFE61 */
++#define REG_NORMAL_SIE_PID				0xFE62		/* 0xFE62~0xFE63 */
++#define REG_NORMAL_SIE_OPTIONAL		0xFE64
++#define REG_NORMAL_SIE_EP				0xFE65		/* 0xFE65~0xFE67 */
++#define REG_NORMAL_SIE_PHY			0xFE68		/* 0xFE68~0xFE6B */
++#define REG_NORMAL_SIE_OPTIONAL2		0xFE6C
++#define REG_NORMAL_SIE_GPS_EP			0xFE6D		/* 0xFE6D, for RTL8723 only. */
++#define REG_NORMAL_SIE_MAC_ADDR		0xFE70		/* 0xFE70~0xFE75 */
++#define REG_NORMAL_SIE_STRING			0xFE80		/* 0xFE80~0xFEDF */
++
++
++/* -----------------------------------------------------
++*
++*	Redifine 8192C register definition for compatibility
++*
++* ----------------------------------------------------- */
++
++/* TODO: use these definition when using REG_xxx naming rule.
++* NOTE: DO NOT Remove these definition. Use later. */
++
++#define EFUSE_CTRL				REG_EFUSE_CTRL		/* E-Fuse Control. */
++#define EFUSE_TEST				REG_EFUSE_TEST		/* E-Fuse Test. */
++#define MSR						(REG_CR + 2)		/* Media Status register */
++/* #define ISR						REG_HISR */
++#define MSR1						REG_CR_EXT
++
++#define TSFR						REG_TSFTR			/* Timing Sync Function Timer Register. */
++#define TSFR1					REG_TSFTR1			/* HW Port 1 TSF Register */
++
++#define PBP						REG_PBP
++
++/* Redifine MACID register, to compatible prior ICs. */
++#define IDR0						REG_MACID			/* MAC ID Register, Offset 0x0050-0x0053 */
++#define IDR4						(REG_MACID + 4)		/* MAC ID Register, Offset 0x0054-0x0055 */
++
++/* Unused register */
++#define UnusedRegister			0x1BF
++#define DCAM					UnusedRegister
++#define PSR						UnusedRegister
++#define BBAddr					UnusedRegister
++#define PhyDataR					UnusedRegister
++
++/* Min Spacing related settings. */
++#define MAX_MSS_DENSITY_2T			0x13
++#define MAX_MSS_DENSITY_1T			0x0A
++
++/* ----------------------------------------------------------------------------
++* 8192C Cmd9346CR bits					(Offset 0xA, 16bit)
++* ---------------------------------------------------------------------------- */
++#define CmdEEPROM_En				BIT(5)	 /* EEPROM enable when set 1 */
++#define CmdEERPOMSEL				BIT(4)	/* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */
++#define Cmd9346CR_9356SEL			BIT(4)
++
++/* ----------------------------------------------------------------------------
++* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte)
++* ---------------------------------------------------------------------------- */
++#define GPIOSEL_GPIO				0
++#define GPIOSEL_ENBT				BIT(5)
++
++/* ----------------------------------------------------------------------------
++* 8192C GPIO PIN Control Register (offset 0x44, 4 byte)
++* ---------------------------------------------------------------------------- */
++#define GPIO_IN					REG_GPIO_PIN_CTRL		/* GPIO pins input value */
++#define GPIO_OUT				(REG_GPIO_PIN_CTRL+1)	/* GPIO pins output value */
++#define GPIO_IO_SEL				(REG_GPIO_PIN_CTRL+2)	/* GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. */
++#define GPIO_MOD				(REG_GPIO_PIN_CTRL+3)
++
++/* ----------------------------------------------------------------------------
++* 8811A GPIO PIN Control Register (offset 0x60, 4 byte)
++* ---------------------------------------------------------------------------- */
++#define GPIO_IN_8811A			REG_GPIO_PIN_CTRL_2		/* GPIO pins input value */
++#define GPIO_OUT_8811A			(REG_GPIO_PIN_CTRL_2+1)	/* GPIO pins output value */
++#define GPIO_IO_SEL_8811A		(REG_GPIO_PIN_CTRL_2+2)	/* GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. */
++#define GPIO_MOD_8811A			(REG_GPIO_PIN_CTRL_2+3)
++
++/* ----------------------------------------------------------------------------
++* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte)
++* ---------------------------------------------------------------------------- */
++#define HSIMR_GPIO12_0_INT_EN			BIT(0)
++#define HSIMR_SPS_OCP_INT_EN			BIT(5)
++#define HSIMR_RON_INT_EN				BIT(6)
++#define HSIMR_PDN_INT_EN				BIT(7)
++#define HSIMR_GPIO9_INT_EN				BIT(25)
++
++/* ----------------------------------------------------------------------------
++* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte)
++* ---------------------------------------------------------------------------- */
++#define HSISR_GPIO12_0_INT				BIT(0)
++#define HSISR_SPS_OCP_INT				BIT(5)
++#define HSISR_RON_INT					BIT(6)
++#define HSISR_PDNINT					BIT(7)
++#define HSISR_GPIO9_INT					BIT(25)
++
++/* ----------------------------------------------------------------------------
++* 8192C (MSR) Media Status Register	(Offset 0x4C, 8 bits)
++* ---------------------------------------------------------------------------- */
++/*
++Network Type
++00: No link
++01: Link in ad hoc network
++10: Link in infrastructure network
++11: AP mode
++Default: 00b.
++*/
++#define MSR_NOLINK				0x00
++#define MSR_ADHOC				0x01
++#define MSR_INFRA				0x02
++#define MSR_AP					0x03
++
++/* ----------------------------------------------------------------------------
++* USB INTR CONTENT
++* ---------------------------------------------------------------------------- */
++#define USB_C2H_CMDID_OFFSET					0
++#define USB_C2H_SEQ_OFFSET					1
++#define USB_C2H_EVENT_OFFSET					2
++#define USB_INTR_CPWM_OFFSET					16
++#define USB_INTR_CONTENT_C2H_OFFSET			0
++#define USB_INTR_CONTENT_CPWM1_OFFSET		16
++#define USB_INTR_CONTENT_CPWM2_OFFSET		20
++#define USB_INTR_CONTENT_HISR_OFFSET			48
++#define USB_INTR_CONTENT_HISRE_OFFSET		52
++#define USB_INTR_CONTENT_LENGTH				56
++
++
++/* WOL bit information */
++#define HAL92C_WOL_PTK_UPDATE_EVENT		BIT(0)
++#define HAL92C_WOL_GTK_UPDATE_EVENT		BIT(1)
++#define HAL92C_WOL_DISASSOC_EVENT		BIT(2)
++#define HAL92C_WOL_DEAUTH_EVENT			BIT(3)
++#define HAL92C_WOL_FW_DISCONNECT_EVENT	BIT(4)
++
++
++/*----------------------------------------------------------------------------
++**      REG_CCK_CHECK						(offset 0x454)
++------------------------------------------------------------------------------*/
++#define BIT_BCN_PORT_SEL		BIT(5)
++#define BIT_EN_BCN_PKT_REL		BIT(6)
++
++#endif /* RTW_HALMAC */
++
++/* ----------------------------------------------------------------------------
++* Response Rate Set Register	(offset 0x440, 24bits)
++* ---------------------------------------------------------------------------- */
++#define RRSR_1M					BIT(0)
++#define RRSR_2M					BIT(1)
++#define RRSR_5_5M				BIT(2)
++#define RRSR_11M				BIT(3)
++#define RRSR_6M					BIT(4)
++#define RRSR_9M					BIT(5)
++#define RRSR_12M				BIT(6)
++#define RRSR_18M				BIT(7)
++#define RRSR_24M				BIT(8)
++#define RRSR_36M				BIT(9)
++#define RRSR_48M				BIT(10)
++#define RRSR_54M				BIT(11)
++#define RRSR_MCS0				BIT(12)
++#define RRSR_MCS1				BIT(13)
++#define RRSR_MCS2				BIT(14)
++#define RRSR_MCS3				BIT(15)
++#define RRSR_MCS4				BIT(16)
++#define RRSR_MCS5				BIT(17)
++#define RRSR_MCS6				BIT(18)
++#define RRSR_MCS7				BIT(19)
++
++#define RRSR_CCK_RATES (RRSR_11M | RRSR_5_5M | RRSR_2M | RRSR_1M)
++#define RRSR_OFDM_RATES (RRSR_54M | RRSR_48M | RRSR_36M | RRSR_24M | RRSR_18M | RRSR_12M | RRSR_9M | RRSR_6M)
++
++/* ----------------------------------------------------------------------------
++ * Rate Definition
++ * ---------------------------------------------------------------------------- */
++/* CCK */
++#define	RATR_1M					0x00000001
++#define	RATR_2M					0x00000002
++#define	RATR_55M					0x00000004
++#define	RATR_11M					0x00000008
++/* OFDM		 */
++#define	RATR_6M					0x00000010
++#define	RATR_9M					0x00000020
++#define	RATR_12M					0x00000040
++#define	RATR_18M					0x00000080
++#define	RATR_24M					0x00000100
++#define	RATR_36M					0x00000200
++#define	RATR_48M					0x00000400
++#define	RATR_54M					0x00000800
++/* MCS 1 Spatial Stream	 */
++#define	RATR_MCS0					0x00001000
++#define	RATR_MCS1					0x00002000
++#define	RATR_MCS2					0x00004000
++#define	RATR_MCS3					0x00008000
++#define	RATR_MCS4					0x00010000
++#define	RATR_MCS5					0x00020000
++#define	RATR_MCS6					0x00040000
++#define	RATR_MCS7					0x00080000
++/* MCS 2 Spatial Stream */
++#define	RATR_MCS8					0x00100000
++#define	RATR_MCS9					0x00200000
++#define	RATR_MCS10					0x00400000
++#define	RATR_MCS11					0x00800000
++#define	RATR_MCS12					0x01000000
++#define	RATR_MCS13					0x02000000
++#define	RATR_MCS14					0x04000000
++#define	RATR_MCS15					0x08000000
++
++/* CCK */
++#define RATE_1M					BIT(0)
++#define RATE_2M					BIT(1)
++#define RATE_5_5M				BIT(2)
++#define RATE_11M				BIT(3)
++/* OFDM */
++#define RATE_6M					BIT(4)
++#define RATE_9M					BIT(5)
++#define RATE_12M				BIT(6)
++#define RATE_18M				BIT(7)
++#define RATE_24M				BIT(8)
++#define RATE_36M				BIT(9)
++#define RATE_48M				BIT(10)
++#define RATE_54M				BIT(11)
++/* MCS 1 Spatial Stream */
++#define RATE_MCS0				BIT(12)
++#define RATE_MCS1				BIT(13)
++#define RATE_MCS2				BIT(14)
++#define RATE_MCS3				BIT(15)
++#define RATE_MCS4				BIT(16)
++#define RATE_MCS5				BIT(17)
++#define RATE_MCS6				BIT(18)
++#define RATE_MCS7				BIT(19)
++/* MCS 2 Spatial Stream */
++#define RATE_MCS8				BIT(20)
++#define RATE_MCS9				BIT(21)
++#define RATE_MCS10				BIT(22)
++#define RATE_MCS11				BIT(23)
++#define RATE_MCS12				BIT(24)
++#define RATE_MCS13				BIT(25)
++#define RATE_MCS14				BIT(26)
++#define RATE_MCS15				BIT(27)
++
++
++/* ALL CCK Rate */
++#define	RATE_ALL_CCK				(RATR_1M | RATR_2M | RATR_55M | RATR_11M)
++#define	RATE_ALL_OFDM_AG			(RATR_6M | RATR_9M | RATR_12M | RATR_18M | RATR_24M|\
++	RATR_36M | RATR_48M | RATR_54M)
++#define	RATE_ALL_OFDM_1SS			(RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | RATR_MCS3 |\
++	RATR_MCS4 | RATR_MCS5 | RATR_MCS6 | RATR_MCS7)
++#define	RATE_ALL_OFDM_2SS			(RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | RATR_MCS11|\
++	RATR_MCS12 | RATR_MCS13 | RATR_MCS14 | RATR_MCS15)
++
++#define RATE_BITMAP_ALL			0xFFFFF
++
++/* Only use CCK 1M rate for ACK */
++#define RATE_RRSR_CCK_ONLY_1M		0xFFFF1
++#define RATE_RRSR_WITHOUT_CCK		0xFFFF0
++
++/* ----------------------------------------------------------------------------
++ * BW_OPMODE bits				(Offset 0x603, 8bit)
++ * ---------------------------------------------------------------------------- */
++#define BW_OPMODE_20MHZ			BIT(2)
++#define BW_OPMODE_5G				BIT(1)
++
++/* ----------------------------------------------------------------------------
++ * CAM Config Setting (offset 0x680, 1 byte)
++ * ----------------------------------------------------------------------------			 */
++#define CAM_VALID				BIT(15)
++#define CAM_NOTVALID			0x0000
++#define CAM_USEDK				BIT(5)
++
++#define CAM_CONTENT_COUNT	8
++
++#define CAM_NONE				0x0
++#define CAM_WEP40				0x01
++#define CAM_TKIP				0x02
++#define CAM_AES					0x04
++#define CAM_WEP104				0x05
++#define CAM_SMS4				0x6
++
++#define TOTAL_CAM_ENTRY		32
++#define HALF_CAM_ENTRY			16
++
++#define CAM_CONFIG_USEDK		_TRUE
++#define CAM_CONFIG_NO_USEDK	_FALSE
++
++#define CAM_WRITE				BIT(16)
++#define CAM_READ				0x00000000
++#define CAM_POLLINIG			BIT(31)
++
++/*
++ * 10. Power Save Control Registers
++ *   */
++#define WOW_PMEN				BIT(0) /* Power management Enable. */
++#define WOW_WOMEN				BIT(1) /* WoW function on or off. */
++#define WOW_MAGIC				BIT(2) /* Magic packet */
++#define WOW_UWF				BIT(3) /* Unicast Wakeup frame. */
++
++/*
++ * 12. Host Interrupt Status Registers
++ *
++ * ----------------------------------------------------------------------------
++ * 8190 IMR/ISR bits
++ * ---------------------------------------------------------------------------- */
++#define IMR8190_DISABLED		0x0
++#define IMR_DISABLED			0x0
++/* IMR DW0 Bit 0-31 */
++#define IMR_BCNDMAINT6			BIT(31)		/* Beacon DMA Interrupt 6 */
++#define IMR_BCNDMAINT5			BIT(30)		/* Beacon DMA Interrupt 5 */
++#define IMR_BCNDMAINT4			BIT(29)		/* Beacon DMA Interrupt 4 */
++#define IMR_BCNDMAINT3			BIT(28)		/* Beacon DMA Interrupt 3 */
++#define IMR_BCNDMAINT2			BIT(27)		/* Beacon DMA Interrupt 2 */
++#define IMR_BCNDMAINT1			BIT(26)		/* Beacon DMA Interrupt 1 */
++#define IMR_BCNDOK8				BIT(25)		/* Beacon Queue DMA OK Interrupt 8 */
++#define IMR_BCNDOK7				BIT(24)		/* Beacon Queue DMA OK Interrupt 7 */
++#define IMR_BCNDOK6				BIT(23)		/* Beacon Queue DMA OK Interrupt 6 */
++#define IMR_BCNDOK5				BIT(22)		/* Beacon Queue DMA OK Interrupt 5 */
++#define IMR_BCNDOK4				BIT(21)		/* Beacon Queue DMA OK Interrupt 4 */
++#define IMR_BCNDOK3				BIT(20)		/* Beacon Queue DMA OK Interrupt 3 */
++#define IMR_BCNDOK2				BIT(19)		/* Beacon Queue DMA OK Interrupt 2 */
++#define IMR_BCNDOK1				BIT(18)		/* Beacon Queue DMA OK Interrupt 1 */
++#define IMR_TIMEOUT2			BIT(17)		/* Timeout interrupt 2 */
++#define IMR_TIMEOUT1			BIT(16)		/* Timeout interrupt 1 */
++#define IMR_TXFOVW				BIT(15)		/* Transmit FIFO Overflow */
++#define IMR_PSTIMEOUT			BIT(14)		/* Power save time out interrupt */
++#define IMR_BcnInt				BIT(13)		/* Beacon DMA Interrupt 0 */
++#define IMR_RXFOVW				BIT(12)		/* Receive FIFO Overflow */
++#define IMR_RDU					BIT(11)		/* Receive Descriptor Unavailable */
++#define IMR_ATIMEND				BIT(10)		/* For 92C, ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt. */
++#define IMR_BDOK				BIT(9)		/* Beacon Queue DMA OK Interrupt */
++#define IMR_HIGHDOK				BIT(8)		/* High Queue DMA OK Interrupt */
++#define IMR_TBDOK				BIT(7)		/* Transmit Beacon OK interrupt */
++#define IMR_MGNTDOK			BIT(6)		/* Management Queue DMA OK Interrupt */
++#define IMR_TBDER				BIT(5)		/* For 92C, Transmit Beacon Error Interrupt */
++#define IMR_BKDOK				BIT(4)		/* AC_BK DMA OK Interrupt */
++#define IMR_BEDOK				BIT(3)		/* AC_BE DMA OK Interrupt */
++#define IMR_VIDOK				BIT(2)		/* AC_VI DMA OK Interrupt */
++#define IMR_VODOK				BIT(1)		/* AC_VO DMA Interrupt */
++#define IMR_ROK					BIT(0)		/* Receive DMA OK Interrupt */
++
++/* 13. Host Interrupt Status Extension Register	 (Offset: 0x012C-012Eh) */
++#define IMR_TSF_BIT32_TOGGLE	BIT(15)
++#define IMR_BcnInt_E				BIT(12)
++#define IMR_TXERR				BIT(11)
++#define IMR_RXERR				BIT(10)
++#define IMR_C2HCMD				BIT(9)
++#define IMR_CPWM				BIT(8)
++/* RSVD [2-7] */
++#define IMR_OCPINT				BIT(1)
++#define IMR_WLANOFF			BIT(0)
++
++/* ----------------------------------------------------------------------------
++ * 8723E series PCIE Host IMR/ISR bit
++ * ---------------------------------------------------------------------------- */
++/* IMR DW0 Bit 0-31 */
++#define PHIMR_TIMEOUT2				BIT(31)
++#define PHIMR_TIMEOUT1				BIT(30)
++#define PHIMR_PSTIMEOUT			BIT(29)
++#define PHIMR_GTINT4				BIT(28)
++#define PHIMR_GTINT3				BIT(27)
++#define PHIMR_TXBCNERR				BIT(26)
++#define PHIMR_TXBCNOK				BIT(25)
++#define PHIMR_TSF_BIT32_TOGGLE	BIT(24)
++#define PHIMR_BCNDMAINT3			BIT(23)
++#define PHIMR_BCNDMAINT2			BIT(22)
++#define PHIMR_BCNDMAINT1			BIT(21)
++#define PHIMR_BCNDMAINT0			BIT(20)
++#define PHIMR_BCNDOK3				BIT(19)
++#define PHIMR_BCNDOK2				BIT(18)
++#define PHIMR_BCNDOK1				BIT(17)
++#define PHIMR_BCNDOK0				BIT(16)
++#define PHIMR_HSISR_IND_ON			BIT(15)
++#define PHIMR_BCNDMAINT_E			BIT(14)
++#define PHIMR_ATIMEND_E			BIT(13)
++#define PHIMR_ATIM_CTW_END		BIT(12)
++#define PHIMR_HISRE_IND			BIT(11)	/* RO. HISRE Indicator (HISRE & HIMRE is true, this bit is set to 1) */
++#define PHIMR_C2HCMD				BIT(10)
++#define PHIMR_CPWM2				BIT(9)
++#define PHIMR_CPWM					BIT(8)
++#define PHIMR_HIGHDOK				BIT(7)		/* High Queue DMA OK Interrupt */
++#define PHIMR_MGNTDOK				BIT(6)		/* Management Queue DMA OK Interrupt */
++#define PHIMR_BKDOK					BIT(5)		/* AC_BK DMA OK Interrupt */
++#define PHIMR_BEDOK					BIT(4)		/* AC_BE DMA OK Interrupt */
++#define PHIMR_VIDOK					BIT(3)		/* AC_VI DMA OK Interrupt */
++#define PHIMR_VODOK				BIT(2)		/* AC_VO DMA Interrupt */
++#define PHIMR_RDU					BIT(1)		/* Receive Descriptor Unavailable */
++#define PHIMR_ROK					BIT(0)		/* Receive DMA OK Interrupt */
++
++/* PCIE Host Interrupt Status Extension bit */
++#define PHIMR_BCNDMAINT7			BIT(23)
++#define PHIMR_BCNDMAINT6			BIT(22)
++#define PHIMR_BCNDMAINT5			BIT(21)
++#define PHIMR_BCNDMAINT4			BIT(20)
++#define PHIMR_BCNDOK7				BIT(19)
++#define PHIMR_BCNDOK6				BIT(18)
++#define PHIMR_BCNDOK5				BIT(17)
++#define PHIMR_BCNDOK4				BIT(16)
++/* bit12 15: RSVD */
++#define PHIMR_TXERR					BIT(11)
++#define PHIMR_RXERR					BIT(10)
++#define PHIMR_TXFOVW				BIT(9)
++#define PHIMR_RXFOVW				BIT(8)
++/* bit2-7: RSVD */
++#define PHIMR_OCPINT				BIT(1)
++/* bit0: RSVD */
++
++#define UHIMR_TIMEOUT2				BIT(31)
++#define UHIMR_TIMEOUT1				BIT(30)
++#define UHIMR_PSTIMEOUT			BIT(29)
++#define UHIMR_GTINT4				BIT(28)
++#define UHIMR_GTINT3				BIT(27)
++#define UHIMR_TXBCNERR				BIT(26)
++#define UHIMR_TXBCNOK				BIT(25)
++#define UHIMR_TSF_BIT32_TOGGLE	BIT(24)
++#define UHIMR_BCNDMAINT3			BIT(23)
++#define UHIMR_BCNDMAINT2			BIT(22)
++#define UHIMR_BCNDMAINT1			BIT(21)
++#define UHIMR_BCNDMAINT0			BIT(20)
++#define UHIMR_BCNDOK3				BIT(19)
++#define UHIMR_BCNDOK2				BIT(18)
++#define UHIMR_BCNDOK1				BIT(17)
++#define UHIMR_BCNDOK0				BIT(16)
++#define UHIMR_HSISR_IND			BIT(15)
++#define UHIMR_BCNDMAINT_E			BIT(14)
++/* RSVD	BIT(13) */
++#define UHIMR_CTW_END				BIT(12)
++/* RSVD	BIT(11) */
++#define UHIMR_C2HCMD				BIT(10)
++#define UHIMR_CPWM2				BIT(9)
++#define UHIMR_CPWM					BIT(8)
++#define UHIMR_HIGHDOK				BIT(7)		/* High Queue DMA OK Interrupt */
++#define UHIMR_MGNTDOK				BIT(6)		/* Management Queue DMA OK Interrupt */
++#define UHIMR_BKDOK				BIT(5)		/* AC_BK DMA OK Interrupt */
++#define UHIMR_BEDOK				BIT(4)		/* AC_BE DMA OK Interrupt */
++#define UHIMR_VIDOK					BIT(3)		/* AC_VI DMA OK Interrupt */
++#define UHIMR_VODOK				BIT(2)		/* AC_VO DMA Interrupt */
++#define UHIMR_RDU					BIT(1)		/* Receive Descriptor Unavailable */
++#define UHIMR_ROK					BIT(0)		/* Receive DMA OK Interrupt */
++
++/* USB Host Interrupt Status Extension bit */
++#define UHIMR_BCNDMAINT7			BIT(23)
++#define UHIMR_BCNDMAINT6			BIT(22)
++#define UHIMR_BCNDMAINT5			BIT(21)
++#define UHIMR_BCNDMAINT4			BIT(20)
++#define UHIMR_BCNDOK7				BIT(19)
++#define UHIMR_BCNDOK6				BIT(18)
++#define UHIMR_BCNDOK5				BIT(17)
++#define UHIMR_BCNDOK4				BIT(16)
++/* bit14-15: RSVD */
++#define UHIMR_ATIMEND_E			BIT(13)
++#define UHIMR_ATIMEND				BIT(12)
++#define UHIMR_TXERR					BIT(11)
++#define UHIMR_RXERR					BIT(10)
++#define UHIMR_TXFOVW				BIT(9)
++#define UHIMR_RXFOVW				BIT(8)
++/* bit2-7: RSVD */
++#define UHIMR_OCPINT				BIT(1)
++/* bit0: RSVD */
++
++
++#define HAL_NIC_UNPLUG_ISR			0xFFFFFFFF	/* The value when the NIC is unplugged for PCI. */
++#define HAL_NIC_UNPLUG_PCI_ISR		0xEAEAEAEA	/* The value when the NIC is unplugged for PCI in PCI interrupt (page 3). */
++
++/* ----------------------------------------------------------------------------
++ * 8188 IMR/ISR bits
++ * ---------------------------------------------------------------------------- */
++#define IMR_DISABLED_88E			0x0
++/* IMR DW0(0x0060-0063) Bit 0-31 */
++#define IMR_TXCCK_88E				BIT(30)		/* TXRPT interrupt when CCX bit of the packet is set	 */
++#define IMR_PSTIMEOUT_88E			BIT(29)		/* Power Save Time Out Interrupt */
++#define IMR_GTINT4_88E				BIT(28)		/* When GTIMER4 expires, this bit is set to 1	 */
++#define IMR_GTINT3_88E				BIT(27)		/* When GTIMER3 expires, this bit is set to 1	 */
++#define IMR_TBDER_88E				BIT(26)		/* Transmit Beacon0 Error			 */
++#define IMR_TBDOK_88E				BIT(25)		/* Transmit Beacon0 OK			 */
++#define IMR_TSF_BIT32_TOGGLE_88E	BIT(24)		/* TSF Timer BIT32 toggle indication interrupt			 */
++#define IMR_BCNDMAINT0_88E		BIT(20)		/* Beacon DMA Interrupt 0			 */
++#define IMR_BCNDERR0_88E			BIT(16)		/* Beacon Queue DMA Error 0 */
++#define IMR_HSISR_IND_ON_INT_88E	BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)			 */
++#define IMR_BCNDMAINT_E_88E		BIT(14)		/* Beacon DMA Interrupt Extension for Win7			 */
++#define IMR_ATIMEND_88E			BIT(12)		/* CTWidnow End or ATIM Window End */
++#define IMR_HISR1_IND_INT_88E		BIT(11)		/* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */
++#define IMR_C2HCMD_88E				BIT(10)		/* CPU to Host Command INT Status, Write 1 clear	 */
++#define IMR_CPWM2_88E				BIT(9)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
++#define IMR_CPWM_88E				BIT(8)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
++#define IMR_HIGHDOK_88E			BIT(7)			/* High Queue DMA OK	 */
++#define IMR_MGNTDOK_88E			BIT(6)			/* Management Queue DMA OK	 */
++#define IMR_BKDOK_88E				BIT(5)			/* AC_BK DMA OK		 */
++#define IMR_BEDOK_88E				BIT(4)			/* AC_BE DMA OK	 */
++#define IMR_VIDOK_88E				BIT(3)			/* AC_VI DMA OK		 */
++#define IMR_VODOK_88E				BIT(2)			/* AC_VO DMA OK	 */
++#define IMR_RDU_88E					BIT(1)			/* Rx Descriptor Unavailable	 */
++#define IMR_ROK_88E					BIT(0)			/* Receive DMA OK */
++
++/* IMR DW1(0x00B4-00B7) Bit 0-31 */
++#define IMR_BCNDMAINT7_88E		BIT(27)		/* Beacon DMA Interrupt 7 */
++#define IMR_BCNDMAINT6_88E		BIT(26)		/* Beacon DMA Interrupt 6 */
++#define IMR_BCNDMAINT5_88E		BIT(25)		/* Beacon DMA Interrupt 5 */
++#define IMR_BCNDMAINT4_88E		BIT(24)		/* Beacon DMA Interrupt 4 */
++#define IMR_BCNDMAINT3_88E		BIT(23)		/* Beacon DMA Interrupt 3 */
++#define IMR_BCNDMAINT2_88E		BIT(22)		/* Beacon DMA Interrupt 2 */
++#define IMR_BCNDMAINT1_88E		BIT(21)		/* Beacon DMA Interrupt 1 */
++#define IMR_BCNDOK7_88E			BIT(20)		/* Beacon Queue DMA OK Interrupt 7 */
++#define IMR_BCNDOK6_88E			BIT(19)		/* Beacon Queue DMA OK Interrupt 6 */
++#define IMR_BCNDOK5_88E			BIT(18)		/* Beacon Queue DMA OK Interrupt 5 */
++#define IMR_BCNDOK4_88E			BIT(17)		/* Beacon Queue DMA OK Interrupt 4 */
++#define IMR_BCNDOK3_88E			BIT(16)		/* Beacon Queue DMA OK Interrupt 3 */
++#define IMR_BCNDOK2_88E			BIT(15)		/* Beacon Queue DMA OK Interrupt 2 */
++#define IMR_BCNDOK1_88E			BIT(14)		/* Beacon Queue DMA OK Interrupt 1 */
++#define IMR_ATIMEND_E_88E			BIT(13)		/* ATIM Window End Extension for Win7 */
++#define IMR_TXERR_88E				BIT(11)		/* Tx Error Flag Interrupt Status, write 1 clear. */
++#define IMR_RXERR_88E				BIT(10)		/* Rx Error Flag INT Status, Write 1 clear */
++#define IMR_TXFOVW_88E				BIT(9)			/* Transmit FIFO Overflow */
++#define IMR_RXFOVW_88E				BIT(8)			/* Receive FIFO Overflow */
++
++/*===================================================================
++=====================================================================
++Here the register defines are for 92C. When the define is as same with 92C,
++we will use the 92C's define for the consistency
++So the following defines for 92C is not entire!!!!!!
++=====================================================================
++=====================================================================*/
++/*
++Based on Datasheet V33---090401
++Register Summary
++Current IOREG MAP
++0x0000h ~ 0x00FFh   System Configuration (256 Bytes)
++0x0100h ~ 0x01FFh   MACTOP General Configuration (256 Bytes)
++0x0200h ~ 0x027Fh   TXDMA Configuration (128 Bytes)
++0x0280h ~ 0x02FFh   RXDMA Configuration (128 Bytes)
++0x0300h ~ 0x03FFh   PCIE EMAC Reserved Region (256 Bytes)
++0x0400h ~ 0x04FFh   Protocol Configuration (256 Bytes)
++0x0500h ~ 0x05FFh   EDCA Configuration (256 Bytes)
++0x0600h ~ 0x07FFh   WMAC Configuration (512 Bytes)
++0x2000h ~ 0x3FFFh   8051 FW Download Region (8196 Bytes)
++*/
++/* ---------------------------------------------------------------------------- */
++/*		 8192C (TXPAUSE) transmission pause 	(Offset 0x522, 8 bits) */
++/* ---------------------------------------------------------------------------- */
++/* Note:
++*	The the bits of stoping AC(VO/VI/BE/BK) queue in datasheet RTL8192S/RTL8192C are wrong,
++*	the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, and BK - Bit3.
++*	8723 and 88E may be not correct either in the eralier version. Confirmed with DD Tim.
++* By Bruce, 2011-09-22. */
++#define StopBecon		BIT(6)
++#define StopHigh			BIT(5)
++#define StopMgt			BIT(4)
++#define StopBK			BIT(3)
++#define StopBE			BIT(2)
++#define StopVI			BIT(1)
++#define StopVO			BIT(0)
++
++/* ----------------------------------------------------------------------------
++ * 8192C (RCR) Receive Configuration Register	(Offset 0x608, 32 bits)
++ * ---------------------------------------------------------------------------- */
++#define RCR_APPFCS				BIT(31)	/* WMAC append FCS after pauload */
++#define RCR_APP_MIC				BIT(30)	/* MACRX will retain the MIC at the bottom of the packet. */
++#define RCR_APP_ICV				BIT(29)	/* MACRX will retain the ICV at the bottom of the packet. */
++#define RCR_APP_PHYST_RXFF		BIT(28)	/* PHY Status is appended before RX packet in RXFF */
++#define RCR_APP_BA_SSN			BIT(27)	/* SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */
++#define RCR_VHT_DACK			BIT(26)	/* This bit to control response type for vht single mpdu data packet. 1. ACK as response 0. BA as response */
++#define RCR_TCPOFLD_EN			BIT(25)	/* Enable TCP checksum offload */
++#define RCR_ENMBID				BIT(24)	/* Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. */
++#define RCR_LSIGEN				BIT(23)	/* Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. */
++#define RCR_MFBEN				BIT(22)	/* Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. */
++#define RCR_DISCHKPPDLLEN		BIT(21)	/* Do not check PPDU while the PPDU length is smaller than 14 byte. */
++#define RCR_PKTCTL_DLEN			BIT(20)	/* While rx path dead lock occurs, reset rx path */
++#define RCR_DISGCLK				BIT(19)	/* Disable macrx clock gating control (no used) */
++#define RCR_TIM_PARSER_EN		BIT(18)	/* RX Beacon TIM Parser. */
++#define RCR_BC_MD_EN			BIT(17)	/* Broadcast data packet more data bit check interrupt enable.*/
++#define RCR_UC_MD_EN			BIT(16)	/* Unicast data packet more data bit check interrupt enable. */
++#define RCR_RXSK_PERPKT			BIT(15)	/* Executing key search per MPDU */
++#define RCR_HTC_LOC_CTRL		BIT(14)	/* MFC<--HTC = 1 MFC-->HTC = 0 */
++#define RCR_AMF					BIT(13)	/* Accept management type frame */
++#define RCR_ACF					BIT(12)	/* Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. */
++#define RCR_ADF					BIT(11)	/* Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). */
++#define RCR_DISDECMYPKT			BIT(10)	/* This bit determines whether hw need to do decryption.1: If A1 match, do decryption.0: Do decryption. */
++#define RCR_AICV					BIT(9)		/* Accept ICV error packet */
++#define RCR_ACRC32				BIT(8)		/* Accept CRC32 error packet */
++#define RCR_CBSSID_BCN			BIT(7)		/* Accept BSSID match packet (Rx beacon, probe rsp) */
++#define RCR_CBSSID_DATA		BIT(6)		/* Accept BSSID match packet (Data) */
++#define RCR_APWRMGT			BIT(5)		/* Accept power management packet */
++#define RCR_ADD3				BIT(4)		/* Accept address 3 match packet */
++#define RCR_AB					BIT(3)		/* Accept broadcast packet */
++#define RCR_AM					BIT(2)		/* Accept multicast packet */
++#define RCR_APM					BIT(1)		/* Accept physical match packet */
++#define RCR_AAP					BIT(0)		/* Accept all unicast packet */
++
++
++/* -----------------------------------------------------
++ *
++ *	0x0000h ~ 0x00FFh	System Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* 2 SYS_ISO_CTRL */
++#define ISO_MD2PP				BIT(0)
++#define ISO_UA2USB				BIT(1)
++#define ISO_UD2CORE				BIT(2)
++#define ISO_PA2PCIE				BIT(3)
++#define ISO_PD2CORE				BIT(4)
++#define ISO_IP2MAC				BIT(5)
++#define ISO_DIOP					BIT(6)
++#define ISO_DIOE					BIT(7)
++#define ISO_EB2CORE				BIT(8)
++#define ISO_DIOR					BIT(9)
++#define PWC_EV12V				BIT(15)
++
++
++/* 2 SYS_FUNC_EN */
++#define FEN_BBRSTB				BIT(0)
++#define FEN_BB_GLB_RSTn		BIT(1)
++#define FEN_USBA				BIT(2)
++#define FEN_UPLL				BIT(3)
++#define FEN_USBD				BIT(4)
++#define FEN_DIO_PCIE			BIT(5)
++#define FEN_PCIEA				BIT(6)
++#define FEN_PPLL					BIT(7)
++#define FEN_PCIED				BIT(8)
++#define FEN_DIOE				BIT(9)
++#define FEN_CPUEN				BIT(10)
++#define FEN_DCORE				BIT(11)
++#define FEN_ELDR				BIT(12)
++#define FEN_EN_25_1				BIT(13)
++#define FEN_HWPDN				BIT(14)
++#define FEN_MREGEN				BIT(15)
++
++/* 2 APS_FSMCO */
++#define PFM_LDALL				BIT(0)
++#define PFM_ALDN				BIT(1)
++#define PFM_LDKP				BIT(2)
++#define PFM_WOWL				BIT(3)
++#define EnPDN					BIT(4)
++#define PDN_PL					BIT(5)
++#define APFM_ONMAC				BIT(8)
++#define APFM_OFF				BIT(9)
++#define APFM_RSM				BIT(10)
++#define AFSM_HSUS				BIT(11)
++#define AFSM_PCIE				BIT(12)
++#define APDM_MAC				BIT(13)
++#define APDM_HOST				BIT(14)
++#define APDM_HPDN				BIT(15)
++#define RDY_MACON				BIT(16)
++#define SUS_HOST				BIT(17)
++#define ROP_ALD					BIT(20)
++#define ROP_PWR					BIT(21)
++#define ROP_SPS					BIT(22)
++#define SOP_MRST				BIT(25)
++#define SOP_FUSE				BIT(26)
++#define SOP_ABG					BIT(27)
++#define SOP_AMB					BIT(28)
++#define SOP_RCK					BIT(29)
++#define SOP_A8M					BIT(30)
++#define XOP_BTCK				BIT(31)
++
++/* 2 SYS_CLKR */
++#define ANAD16V_EN				BIT(0)
++#define ANA8M					BIT(1)
++#define MACSLP					BIT(4)
++#define LOADER_CLK_EN			BIT(5)
++
++
++/* 2 9346CR /REG_SYS_EEPROM_CTRL */
++#define BOOT_FROM_EEPROM		BIT(4)
++#define EEPROMSEL				BIT(4)
++#define EEPROM_EN				BIT(5)
++
++
++/* 2 RF_CTRL */
++#define RF_EN					BIT(0)
++#define RF_RSTB					BIT(1)
++#define RF_SDMRSTB				BIT(2)
++
++
++/* 2 LDOV12D_CTRL */
++#define LDV12_EN				BIT(0)
++#define LDV12_SDBY				BIT(1)
++#define LPLDO_HSM				BIT(2)
++#define LPLDO_LSM_DIS			BIT(3)
++#define _LDV12_VADJ(x)			(((x) & 0xF) << 4)
++
++
++
++/* 2 EFUSE_TEST (For RTL8723 partially) */
++#define EF_TRPT					BIT(7)
++#define EF_CELL_SEL				(BIT(8) | BIT(9)) /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */
++#define LDOE25_EN				BIT(31)
++#define EFUSE_SEL(x)				(((x) & 0x3) << 8)
++#define EFUSE_SEL_MASK			0x300
++#define EFUSE_WIFI_SEL_0		0x0
++#define EFUSE_BT_SEL_0			0x1
++#define EFUSE_BT_SEL_1			0x2
++#define EFUSE_BT_SEL_2			0x3
++
++/* 2 REG_GPIO_INTM				(Offset 0x0048) */
++#define BIT_EXTWOL_EN 			BIT(16)
++
++/* 2 REG_LED_CFG				(Offset 0x004C) */
++#define BIT_SW_SPDT_SEL			BIT(22)
++
++/* 2 REG_SW_GPIO_SHARE_CTRL_0	(Offset 0x1038) */
++#define BIT_BTGP_WAKE_LOC		(BIT(10) | BIT(11))
++#define BIT_SW_GPIO_FUNC 		BIT(0)
++
++/* 2 REG_SW_GPIO_SHARE_CTRL_1	(Offset 0x103C) */
++#define 	BIT_WLMAC_DBG_LOC	(BIT(9) | BIT(10))
++#define 	BIT_WL_GPIO_SEL		(BIT(30) | BIT(31))
++
++/* 2 8051FWDL
++ * 2 MCUFWDL */
++#define MCUFWDL_EN				BIT(0)
++#define MCUFWDL_RDY			BIT(1)
++#define FWDL_ChkSum_rpt		BIT(2)
++#define MACINI_RDY				BIT(3)
++#define BBINI_RDY				BIT(4)
++#define RFINI_RDY				BIT(5)
++#define WINTINI_RDY				BIT(6)
++#define RAM_DL_SEL				BIT(7)
++#define CPU_DL_READY			BIT(15) /* add flag  by gw for fw download ready 20130826 */
++#define ROM_DLEN				BIT(19)
++#define CPRST					BIT(23)
++
++
++/* 2 REG_SYS_CFG */
++#define XCLK_VLD				BIT(0)
++#define ACLK_VLD				BIT(1)
++#define UCLK_VLD				BIT(2)
++#define PCLK_VLD				BIT(3)
++#define PCIRSTB					BIT(4)
++#define V15_VLD					BIT(5)
++#define SW_OFFLOAD_EN			BIT(7)
++#define SIC_IDLE					BIT(8)
++#define BD_MAC2					BIT(9)
++#define BD_MAC1					BIT(10)
++#define IC_MACPHY_MODE		BIT(11)
++#define CHIP_VER				(BIT(12) | BIT(13) | BIT(14) | BIT(15))
++#define BT_FUNC					BIT(16)
++#define VENDOR_ID				BIT(19)
++#define EXT_VENDOR_ID			(BIT(18) | BIT(19)) /* Currently only for RTL8723B */
++#define PAD_HWPD_IDN			BIT(22)
++#define TRP_VAUX_EN				BIT(23)	/* RTL ID */
++#define TRP_BT_EN				BIT(24)
++#define BD_PKG_SEL				BIT(25)
++#define BD_HCI_SEL				BIT(26)
++#define TYPE_ID					BIT(27)
++#define RF_TYPE_ID				BIT(27)
++
++#define RTL_ID					BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */
++#define SPS_SEL					BIT(24) /* 1:LDO regulator mode; 0:Switching regulator mode */
++
++
++#define CHIP_VER_RTL_MASK		0xF000	/* Bit 12 ~ 15 */
++#define CHIP_VER_RTL_SHIFT		12
++#define EXT_VENDOR_ID_SHIFT	18
++
++/* 2 REG_GPIO_OUTSTS (For RTL8723 only) */
++#define EFS_HCI_SEL				(BIT(0) | BIT(1))
++#define PAD_HCI_SEL				(BIT(2) | BIT(3))
++#define HCI_SEL					(BIT(4) | BIT(5))
++#define PKG_SEL_HCI				BIT(6)
++#define FEN_GPS					BIT(7)
++#define FEN_BT					BIT(8)
++#define FEN_WL					BIT(9)
++#define FEN_PCI					BIT(10)
++#define FEN_USB					BIT(11)
++#define BTRF_HWPDN_N			BIT(12)
++#define WLRF_HWPDN_N			BIT(13)
++#define PDN_BT_N				BIT(14)
++#define PDN_GPS_N				BIT(15)
++#define BT_CTL_HWPDN			BIT(16)
++#define GPS_CTL_HWPDN			BIT(17)
++#define PPHY_SUSB				BIT(20)
++#define UPHY_SUSB				BIT(21)
++#define PCI_SUSEN				BIT(22)
++#define USB_SUSEN				BIT(23)
++#define RF_RL_ID					(BIT(31) | BIT(30) | BIT(29) | BIT(28))
++
++
++/* -----------------------------------------------------
++ *
++ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* 2 Function Enable Registers
++ * 2 CR */
++#define HCI_TXDMA_EN			BIT(0)
++#define HCI_RXDMA_EN			BIT(1)
++#define TXDMA_EN				BIT(2)
++#define RXDMA_EN				BIT(3)
++#define PROTOCOL_EN				BIT(4)
++#define SCHEDULE_EN				BIT(5)
++#define MACTXEN					BIT(6)
++#define MACRXEN					BIT(7)
++#define ENSWBCN					BIT(8)
++#define ENSEC					BIT(9)
++#define CALTMR_EN				BIT(10)	/* 32k CAL TMR enable */
++
++/* Network type */
++#define _NETTYPE(x)				(((x) & 0x3) << 16)
++#define MASK_NETTYPE			0x30000
++#define NT_NO_LINK				0x0
++#define NT_LINK_AD_HOC			0x1
++#define NT_LINK_AP				0x2
++#define NT_AS_AP				0x3
++
++/* 2 PBP - Page Size Register */
++#define GET_RX_PAGE_SIZE(value)			((value) & 0xF)
++#define GET_TX_PAGE_SIZE(value)			(((value) & 0xF0) >> 4)
++#define _PSRX_MASK				0xF
++#define _PSTX_MASK				0xF0
++#define _PSRX(x)				(x)
++#define _PSTX(x)				((x) << 4)
++
++#define PBP_64					0x0
++#define PBP_128					0x1
++#define PBP_256					0x2
++#define PBP_512					0x3
++#define PBP_1024				0x4
++
++
++/* 2 TX/RXDMA */
++#define RXDMA_ARBBW_EN		BIT(0)
++#define RXSHFT_EN				BIT(1)
++#define RXDMA_AGG_EN			BIT(2)
++#define QS_VO_QUEUE			BIT(8)
++#define QS_VI_QUEUE				BIT(9)
++#define QS_BE_QUEUE			BIT(10)
++#define QS_BK_QUEUE			BIT(11)
++#define QS_MANAGER_QUEUE		BIT(12)
++#define QS_HIGH_QUEUE			BIT(13)
++
++#define HQSEL_VOQ				BIT(0)
++#define HQSEL_VIQ				BIT(1)
++#define HQSEL_BEQ				BIT(2)
++#define HQSEL_BKQ				BIT(3)
++#define HQSEL_MGTQ				BIT(4)
++#define HQSEL_HIQ				BIT(5)
++
++/* For normal driver, 0x10C */
++#define _TXDMA_CMQ_MAP(x)			(((x) & 0x3) << 16)
++#define _TXDMA_HIQ_MAP(x)			(((x) & 0x3) << 14)
++#define _TXDMA_MGQ_MAP(x)			(((x) & 0x3) << 12)
++#define _TXDMA_BKQ_MAP(x)			(((x) & 0x3) << 10)
++#define _TXDMA_BEQ_MAP(x)			(((x) & 0x3) << 8)
++#define _TXDMA_VIQ_MAP(x)			(((x) & 0x3) << 6)
++#define _TXDMA_VOQ_MAP(x)			(((x) & 0x3) << 4)
++
++#define QUEUE_EXTRA				0
++#define QUEUE_LOW				1
++#define QUEUE_NORMAL			2
++#define QUEUE_HIGH				3
++#define QUEUE_EXTRA_1			4
++#define QUEUE_EXTRA_2			5
++
++/* 2 TRXFF_BNDY */
++
++
++/* 2 LLT_INIT */
++#define _LLT_NO_ACTIVE				0x0
++#define _LLT_WRITE_ACCESS			0x1
++#define _LLT_READ_ACCESS			0x2
++
++#define _LLT_INIT_DATA(x)			((x) & 0xFF)
++#define _LLT_INIT_ADDR(x)			(((x) & 0xFF) << 8)
++#define _LLT_OP(x)					(((x) & 0x3) << 30)
++#define _LLT_OP_VALUE(x)			(((x) >> 30) & 0x3)
++
++
++/* -----------------------------------------------------
++ *
++ *	0x0200h ~ 0x027Fh	TXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++/* 2 RQPN */
++#define _HPQ(x)					((x) & 0xFF)
++#define _LPQ(x)					(((x) & 0xFF) << 8)
++#define _PUBQ(x)					(((x) & 0xFF) << 16)
++#define _NPQ(x)					((x) & 0xFF)			/* NOTE: in RQPN_NPQ register */
++#define _EPQ(x)					(((x) & 0xFF) << 16)	/* NOTE: in RQPN_EPQ register */
++
++
++#define HPQ_PUBLIC_DIS			BIT(24)
++#define LPQ_PUBLIC_DIS			BIT(25)
++#define LD_RQPN					BIT(31)
++
++
++/* 2 TDECTL */
++#define BLK_DESC_NUM_SHIFT			4
++#define BLK_DESC_NUM_MASK			0xF
++
++
++/* 2 TXDMA_OFFSET_CHK */
++#define DROP_DATA_EN				BIT(9)
++
++/* 2 AUTO_LLT */
++#define BIT_SHIFT_TXPKTNUM 24
++#define BIT_MASK_TXPKTNUM 0xff
++#define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM)
++
++#define BIT_TDE_DBG_SEL BIT(23)
++#define BIT_AUTO_INIT_LLT BIT(16)
++
++#define BIT_SHIFT_Tx_OQT_free_space 8
++#define BIT_MASK_Tx_OQT_free_space 0xff
++#define BIT_Tx_OQT_free_space(x) (((x) & BIT_MASK_Tx_OQT_free_space) << BIT_SHIFT_Tx_OQT_free_space)
++
++
++/* -----------------------------------------------------
++ *
++ *	0x0120h ~ 0x0123h	RX DMA Configuration
++ *
++ * ----------------------------------------------------- */
++#define BIT_FS_RXDONE_INT_EN				BIT(16)
++
++
++/* REG_RXPKT_NUM				(Offset 0x0284) */
++#define BIT_RW_RELEASE_EN				BIT(18)
++
++/* -----------------------------------------------------
++ *
++ *	0x0280h ~ 0x028Bh	RX DMA Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* 2 REG_RXDMA_CONTROL, 0x0286h
++ * Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before
++ * this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear.
++ * #define RXPKT_RELEASE_POLL			BIT(0)
++ * Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in
++ * this bit. FW can start releasing packets after RXDMA entering idle mode.
++ * #define RXDMA_IDLE					BIT(1)
++ * When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host
++ * completed, and stop DMA packet to host. RXDMA will then report Default: 0;
++ * #define RW_RELEASE_EN				BIT(2) */
++
++/* 2 REG_RXPKT_NUM, 0x0284 */
++#define	RXPKT_RELEASE_POLL	BIT(16)
++#define	RXDMA_IDLE				BIT(17)
++#define	RW_RELEASE_EN			BIT(18)
++
++/* -----------------------------------------------------
++ *
++ *	0x0400h ~ 0x047Fh	Protocol Configuration
++ *
++ * ----------------------------------------------------- */
++/* 2 FWHW_TXQ_CTRL */
++#define EN_AMPDU_RTY_NEW			BIT(7)
++
++
++/* 2 SPEC SIFS */
++#define _SPEC_SIFS_CCK(x)			((x) & 0xFF)
++#define _SPEC_SIFS_OFDM(x)			(((x) & 0xFF) << 8)
++
++/* 2 RL */
++#define BIT_SHIFT_SRL 8
++#define BIT_MASK_SRL 0x3f
++#define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL)
++
++#define BIT_SHIFT_LRL 0
++#define BIT_MASK_LRL 0x3f
++#define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL)
++
++#define	RL_VAL_AP					7
++#ifdef CONFIG_RTW_CUSTOMIZE_RLSTA
++#define	RL_VAL_STA					CONFIG_RTW_CUSTOMIZE_RLSTA
++#else
++#define	RL_VAL_STA					0x30
++#endif
++/* -----------------------------------------------------
++ *
++ *	0x0500h ~ 0x05FFh	EDCA Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* 2 EDCA setting */
++#define AC_PARAM_TXOP_LIMIT_OFFSET		16
++#define AC_PARAM_ECW_MAX_OFFSET			12
++#define AC_PARAM_ECW_MIN_OFFSET			8
++#define AC_PARAM_AIFS_OFFSET				0
++
++/* 2 BCN_CTRL */
++#define EN_TXBCN_RPT			BIT(2)
++#define EN_BCN_FUNCTION		BIT(3)
++#define STOP_BCNQ				BIT(6)
++#define DIS_RX_BSSID_FIT		BIT(6)
++
++#define DIS_ATIM					BIT(0)
++#define DIS_BCNQ_SUB			BIT(1)
++#define DIS_TSF_UDT				BIT(4)
++
++/* 2 ACMHWCTRL */
++#define AcmHw_HwEn				BIT(0)
++#define AcmHw_VoqEn			BIT(1)
++#define AcmHw_ViqEn				BIT(2)
++#define AcmHw_BeqEn			BIT(3)
++#define AcmHw_VoqStatus		BIT(5)
++#define AcmHw_ViqStatus			BIT(6)
++#define AcmHw_BeqStatus		BIT(7)
++
++/* 2 */ /* REG_DUAL_TSF_RST (0x553) */
++#define DUAL_TSF_RST_P2P		BIT(4)
++
++/* 2 */ /* REG_NOA_DESC_SEL (0x5CF) */
++#define NOA_DESC_SEL_0			0
++#define NOA_DESC_SEL_1			BIT(4)
++
++/* -----------------------------------------------------
++ *
++ *	0x0600h ~ 0x07FFh	WMAC Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* 2 APSD_CTRL */
++#define APSDOFF					BIT(6)
++
++/* 2 TCR */
++#define TSFRST					BIT(0)
++#define DIS_GCLK					BIT(1)
++#define PAD_SEL					BIT(2)
++#define PWR_ST					BIT(6)
++#define PWRBIT_OW_EN			BIT(7)
++#define ACRC						BIT(8)
++#define CFENDFORM				BIT(9)
++#define ICV						BIT(10)
++
++
++/* 2 RCR */
++#define AAP						BIT(0)
++#define APM						BIT(1)
++#define AM						BIT(2)
++#define AB						BIT(3)
++#define ADD3						BIT(4)
++#define APWRMGT				BIT(5)
++#define CBSSID					BIT(6)
++#define CBSSID_DATA				BIT(6)
++#define CBSSID_BCN				BIT(7)
++#define ACRC32					BIT(8)
++#define AICV						BIT(9)
++#define ADF						BIT(11)
++#define ACF						BIT(12)
++#define AMF						BIT(13)
++#define HTC_LOC_CTRL			BIT(14)
++#define UC_DATA_EN				BIT(16)
++#define BM_DATA_EN				BIT(17)
++#define MFBEN					BIT(22)
++#define LSIGEN					BIT(23)
++#define EnMBID					BIT(24)
++#define FORCEACK				BIT(26)
++#define APP_BASSN				BIT(27)
++#define APP_PHYSTS				BIT(28)
++#define APP_ICV					BIT(29)
++#define APP_MIC					BIT(30)
++#define APP_FCS					BIT(31)
++
++
++/* 2 SECCFG */
++#define SCR_TxUseDK				BIT(0)			/* Force Tx Use Default Key */
++#define SCR_RxUseDK				BIT(1)			/* Force Rx Use Default Key */
++#define SCR_TxEncEnable			BIT(2)			/* Enable Tx Encryption */
++#define SCR_RxDecEnable			BIT(3)			/* Enable Rx Decryption */
++#define SCR_SKByA2				BIT(4)			/* Search kEY BY A2 */
++#define SCR_NoSKMC				BIT(5)			/* No Key Search Multicast */
++#define SCR_TXBCUSEDK			BIT(6)			/* Force Tx Broadcast packets Use Default Key */
++#define SCR_RXBCUSEDK			BIT(7)			/* Force Rx Broadcast packets Use Default Key */
++#define SCR_CHK_KEYID			BIT(8)
++#define SCR_CHK_BMC				BIT(9)			/* add option to support a2+keyid+bcm */
++
++/*REG_MBIDCAMCFG           (Offset 0x0628/0x62C)*/
++#define BIT_MBIDCAM_POLL		BIT(31)
++#define BIT_MBIDCAM_WT_EN		BIT(30)
++
++#define MBIDCAM_ADDR_MASK		0x1F
++#define MBIDCAM_ADDR_SHIFT		24
++
++#define BIT_MBIDCAM_VALID		BIT(23)
++#define BIT_LSIC_TXOP_EN		BIT(17)
++#define BIT_CTS_EN				BIT(16)
++
++/*REG_RXFLTMAP1 (Offset 0x6A2)*/
++#define BIT_CTRLFLT10EN	BIT(10) /*PS-POLL*/
++
++/*REG_WLAN_ACT_MASK_CTRL_1	(Offset 0x76C)*/
++#define EN_PORT_0_FUNCTION		BIT(12)
++#define EN_PORT_1_FUNCTION		BIT(13)
++
++/* -----------------------------------------------------
++ *
++ *	SDIO Bus Specification
++ *
++ * ----------------------------------------------------- */
++
++/* I/O bus domain address mapping */
++#define SDIO_LOCAL_BASE		0x10250000
++#define WLAN_IOREG_BASE		0x10260000
++#define FIRMWARE_FIFO_BASE	0x10270000
++#define TX_HIQ_BASE				0x10310000
++#define TX_MIQ_BASE				0x10320000
++#define TX_LOQ_BASE				0x10330000
++#define TX_EPQ_BASE				0x10350000
++#define RX_RX0FF_BASE			0x10340000
++
++/* SDIO host local register space mapping. */
++#define SDIO_LOCAL_MSK				0x0FFF
++#define WLAN_IOREG_MSK		0x7FFF
++#define WLAN_FIFO_MSK			      	0x1FFF	/* Aggregation Length[12:0] */
++#define WLAN_RX0FF_MSK				0x0003
++
++#define SDIO_WITHOUT_REF_DEVICE_ID	0	/* Without reference to the SDIO Device ID */
++#define SDIO_LOCAL_DEVICE_ID           		0	/* 0b[16], 000b[15:13] */
++#define WLAN_TX_HIQ_DEVICE_ID			4	/* 0b[16], 100b[15:13] */
++#define WLAN_TX_MIQ_DEVICE_ID 		5	/* 0b[16], 101b[15:13] */
++#define WLAN_TX_LOQ_DEVICE_ID 		6	/* 0b[16], 110b[15:13] */
++#define WLAN_TX_EXQ_DEVICE_ID		3	/* 0b[16], 011b[15:13] */
++#define WLAN_RX0FF_DEVICE_ID 			7	/* 0b[16], 111b[15:13] */
++#define WLAN_IOREG_DEVICE_ID 			8	/* 1b[16] */
++
++/* SDIO Tx Free Page Index */
++#define HI_QUEUE_IDX			0
++#define MID_QUEUE_IDX			1
++#define LOW_QUEUE_IDX				2
++#define PUBLIC_QUEUE_IDX			3
++
++#define SDIO_MAX_TX_QUEUE			3		/* HIQ, MIQ and LOQ */
++#define SDIO_MAX_RX_QUEUE			1
++
++#define SDIO_REG_TX_CTRL			0x0000 /* SDIO Tx Control */
++#define SDIO_REG_TIMEOUT			0x0002/*SDIO status timeout*/
++#define SDIO_REG_HIMR				0x0014 /* SDIO Host Interrupt Mask */
++#define SDIO_REG_HISR				0x0018 /* SDIO Host Interrupt Service Routine */
++#define SDIO_REG_HCPWM			0x0019 /* HCI Current Power Mode */
++#define SDIO_REG_RX0_REQ_LEN		0x001C /* RXDMA Request Length */
++#define SDIO_REG_OQT_FREE_PG		0x001E /* OQT Free Page */
++#define SDIO_REG_FREE_TXPG			0x0020 /* Free Tx Buffer Page */
++#define SDIO_REG_HCPWM1			0x0024 /* HCI Current Power Mode 1 */
++#define SDIO_REG_HCPWM2			0x0026 /* HCI Current Power Mode 2 */
++#define SDIO_REG_FREE_TXPG_SEQ	0x0028 /* Free Tx Page Sequence */
++#define SDIO_REG_HTSFR_INFO		0x0030 /* HTSF Informaion */
++#define SDIO_REG_HRPWM1			0x0080 /* HCI Request Power Mode 1 */
++#define SDIO_REG_HRPWM2			0x0082 /* HCI Request Power Mode 2 */
++#define SDIO_REG_HPS_CLKR			0x0084 /* HCI Power Save Clock */
++#define SDIO_REG_HSUS_CTRL			0x0086 /* SDIO HCI Suspend Control */
++#define SDIO_REG_HIMR_ON			0x0090 /* SDIO Host Extension Interrupt Mask Always */
++#define SDIO_REG_HISR_ON			0x0091 /* SDIO Host Extension Interrupt Status Always */
++
++#define SDIO_HIMR_DISABLED			0
++
++/* RTL8723/RTL8188E SDIO Host Interrupt Mask Register */
++#define SDIO_HIMR_RX_REQUEST_MSK		BIT(0)
++#define SDIO_HIMR_AVAL_MSK			BIT(1)
++#define SDIO_HIMR_TXERR_MSK			BIT(2)
++#define SDIO_HIMR_RXERR_MSK			BIT(3)
++#define SDIO_HIMR_TXFOVW_MSK			BIT(4)
++#define SDIO_HIMR_RXFOVW_MSK			BIT(5)
++#define SDIO_HIMR_TXBCNOK_MSK			BIT(6)
++#define SDIO_HIMR_TXBCNERR_MSK		BIT(7)
++#define SDIO_HIMR_BCNERLY_INT_MSK		BIT(16)
++#define SDIO_HIMR_C2HCMD_MSK			BIT(17)
++#define SDIO_HIMR_CPWM1_MSK			BIT(18)
++#define SDIO_HIMR_CPWM2_MSK			BIT(19)
++#define SDIO_HIMR_HSISR_IND_MSK		BIT(20)
++#define SDIO_HIMR_GTINT3_IND_MSK		BIT(21)
++#define SDIO_HIMR_GTINT4_IND_MSK		BIT(22)
++#define SDIO_HIMR_PSTIMEOUT_MSK		BIT(23)
++#define SDIO_HIMR_OCPINT_MSK			BIT(24)
++#define SDIO_HIMR_ATIMEND_MSK			BIT(25)
++#define SDIO_HIMR_ATIMEND_E_MSK		BIT(26)
++#define SDIO_HIMR_CTWEND_MSK			BIT(27)
++
++/* RTL8188E SDIO Specific */
++#define SDIO_HIMR_MCU_ERR_MSK			BIT(28)
++#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK		BIT(29)
++
++/* SDIO Host Interrupt Service Routine */
++#define SDIO_HISR_RX_REQUEST			BIT(0)
++#define SDIO_HISR_AVAL					BIT(1)
++#define SDIO_HISR_TXERR					BIT(2)
++#define SDIO_HISR_RXERR					BIT(3)
++#define SDIO_HISR_TXFOVW				BIT(4)
++#define SDIO_HISR_RXFOVW				BIT(5)
++#define SDIO_HISR_TXBCNOK				BIT(6)
++#define SDIO_HISR_TXBCNERR				BIT(7)
++#define SDIO_HISR_BCNERLY_INT			BIT(16)
++#define SDIO_HISR_C2HCMD				BIT(17)
++#define SDIO_HISR_CPWM1				BIT(18)
++#define SDIO_HISR_CPWM2				BIT(19)
++#define SDIO_HISR_HSISR_IND			BIT(20)
++#define SDIO_HISR_GTINT3_IND			BIT(21)
++#define SDIO_HISR_GTINT4_IND			BIT(22)
++#define SDIO_HISR_PSTIMEOUT			BIT(23)
++#define SDIO_HISR_OCPINT				BIT(24)
++#define SDIO_HISR_ATIMEND				BIT(25)
++#define SDIO_HISR_ATIMEND_E			BIT(26)
++#define SDIO_HISR_CTWEND				BIT(27)
++
++/* RTL8188E SDIO Specific */
++#define SDIO_HISR_MCU_ERR				BIT(28)
++#define SDIO_HISR_TSF_BIT32_TOGGLE	BIT(29)
++
++#define MASK_SDIO_HISR_CLEAR		(SDIO_HISR_TXERR |\
++		SDIO_HISR_RXERR |\
++		SDIO_HISR_TXFOVW |\
++		SDIO_HISR_RXFOVW |\
++		SDIO_HISR_TXBCNOK |\
++		SDIO_HISR_TXBCNERR |\
++		SDIO_HISR_C2HCMD |\
++		SDIO_HISR_CPWM1 |\
++		SDIO_HISR_CPWM2 |\
++		SDIO_HISR_HSISR_IND |\
++		SDIO_HISR_GTINT3_IND |\
++		SDIO_HISR_GTINT4_IND |\
++		SDIO_HISR_PSTIMEOUT |\
++		SDIO_HISR_OCPINT)
++
++/* SDIO HCI Suspend Control Register */
++#define HCI_RESUME_PWR_RDY			BIT(1)
++#define HCI_SUS_CTRL					BIT(0)
++
++/* SDIO Tx FIFO related */
++#define SDIO_TX_FREE_PG_QUEUE			4	/* The number of Tx FIFO free page */
++#define SDIO_TX_FIFO_PAGE_SZ			128
++
++/* indirect access */
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++#define SDIO_REG_INDIRECT_REG_CFG		0x40
++#define SDIO_REG_INDIRECT_REG_DATA	0x44
++#define SET_INDIRECT_REG_ADDR(_cmd, _addr)	SET_BITS_TO_LE_2BYTE(((u8 *)(_cmd)) + 0, 0, 16, (_addr))
++#define SET_INDIRECT_REG_SIZE_1BYTE(_cmd)		SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 0)
++#define SET_INDIRECT_REG_SIZE_2BYTE(_cmd)		SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 1)
++#define SET_INDIRECT_REG_SIZE_4BYTE(_cmd)		SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 2)
++#define SET_INDIRECT_REG_WRITE(_cmd)			SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 2, 1, 1)
++#define SET_INDIRECT_REG_READ(_cmd)			SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 3, 1, 1)
++#define GET_INDIRECT_REG_RDY(_cmd)			LE_BITS_TO_1BYTE(((u8 *)(_cmd)) + 2, 4, 1)
++#endif/*CONFIG_SDIO_INDIRECT_ACCESS*/
++
++#ifdef CONFIG_SDIO_HCI
++	#define MAX_TX_AGG_PACKET_NUMBER	0x8
++#else
++	#define MAX_TX_AGG_PACKET_NUMBER	0xFF
++	#define MAX_TX_AGG_PACKET_NUMBER_8812	64
++#endif
++
++/* -----------------------------------------------------
++ *
++ *	0xFE00h ~ 0xFE55h	USB Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* 2 USB Information (0xFE17) */
++#define USB_IS_HIGH_SPEED			0
++#define USB_IS_FULL_SPEED			1
++#define USB_SPEED_MASK				BIT(5)
++
++#define USB_NORMAL_SIE_EP_MASK	0xF
++#define USB_NORMAL_SIE_EP_SHIFT	4
++
++/* 2 Special Option */
++#define USB_AGG_EN				BIT(3)
++
++/* 0; Use interrupt endpoint to upload interrupt pkt
++ * 1; Use bulk endpoint to upload interrupt pkt, */
++#define INT_BULK_SEL			BIT(4)
++
++/* 2REG_C2HEVT_CLEAR */
++#define C2H_EVT_HOST_CLOSE		0x00	/* Set by driver and notify FW that the driver has read the C2H command message */
++#define C2H_EVT_FW_CLOSE		0xFF	/* Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. */
++
++
++/* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */
++#define WL_HWPDN_EN			BIT(0)	/* Enable GPIO[9] as WiFi HW PDn source */
++#define WL_HWPDN_SL			BIT(1)	/* WiFi HW PDn polarity control */
++#define WL_FUNC_EN				BIT(2)	/* WiFi function enable */
++#define WL_HWROF_EN			BIT(3)	/* Enable GPIO[9] as WiFi RF HW PDn source */
++#define BT_HWPDN_EN			BIT(16)	/* Enable GPIO[11] as BT HW PDn source */
++#define BT_HWPDN_SL			BIT(17)	/* BT HW PDn polarity control */
++#define BT_FUNC_EN				BIT(18)	/* BT function enable */
++#define BT_HWROF_EN			BIT(19)	/* Enable GPIO[11] as BT/GPS RF HW PDn source */
++#define GPS_HWPDN_EN			BIT(20)	/* Enable GPIO[10] as GPS HW PDn source */
++#define GPS_HWPDN_SL			BIT(21)	/* GPS HW PDn polarity control */
++#define GPS_FUNC_EN			BIT(22)	/* GPS function enable */
++
++/* 3 REG_LIFECTRL_CTRL */
++#define HAL92C_EN_PKT_LIFE_TIME_BK		BIT(3)
++#define HAL92C_EN_PKT_LIFE_TIME_BE		BIT(2)
++#define HAL92C_EN_PKT_LIFE_TIME_VI		BIT(1)
++#define HAL92C_EN_PKT_LIFE_TIME_VO		BIT(0)
++
++#define HAL92C_MSDU_LIFE_TIME_UNIT		128	/* in us, said by Tim. */
++
++/* 2 8192D PartNo. */
++#define PARTNO_92D_NIC							(BIT7 | BIT6)
++#define PARTNO_92D_NIC_REMARK				(BIT5 | BIT4)
++#define PARTNO_SINGLE_BAND_VS				BIT(3)
++#define PARTNO_SINGLE_BAND_VS_REMARK		BIT(1)
++#define PARTNO_CONCURRENT_BAND_VC			(BIT3 | BIT2)
++#define PARTNO_CONCURRENT_BAND_VC_REMARK	(BIT1 | BIT0)
++
++/* ********************************************************
++ * General definitions
++ * ******************************************************** */
++
++#ifdef CONFIG_USB_HCI
++	#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter)	(175)
++#else
++	#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter)	(IS_VENDOR_8188E_I_CUT_SERIES(__Adapter) ? 255 : 175)
++#endif
++#define LAST_ENTRY_OF_TX_PKT_BUFFER_8812			255
++#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B		255
++#define LAST_ENTRY_OF_TX_PKT_BUFFER_8192C		255
++#define LAST_ENTRY_OF_TX_PKT_BUFFER_8703B		255
++#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC	127
++#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188F		255
++#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188GTV		255
++#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723D		255
++#define LAST_ENTRY_OF_TX_PKT_BUFFER_8710B		255
++#define LAST_ENTRY_OF_TX_PKT_BUFFER_8192F		255
++#define POLLING_LLT_THRESHOLD				20
++#if defined(CONFIG_RTL8723B) && defined(CONFIG_PCI_HCI)
++	#define POLLING_READY_TIMEOUT_COUNT		6000
++#else
++	#define POLLING_READY_TIMEOUT_COUNT		1000
++#endif
++
++
++/* GPIO BIT */
++#define	HAL_8812A_HW_GPIO_WPS_BIT	BIT(2)
++#define	HAL_8192C_HW_GPIO_WPS_BIT	BIT(2)
++#define	HAL_8192EU_HW_GPIO_WPS_BIT	BIT(7)
++#define	HAL_8188E_HW_GPIO_WPS_BIT	BIT(7)
++
++#endif /* __HAL_COMMON_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_data.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_data.h
+new file mode 100755
+index 000000000..dd6991c5d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_data.h
+@@ -0,0 +1,879 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL_DATA_H__
++#define __HAL_DATA_H__
++
++#if 1/* def  CONFIG_SINGLE_IMG */
++
++#include "../hal/phydm/phydm_precomp.h"
++#ifdef CONFIG_BT_COEXIST
++	#include <hal_btcoex.h>
++#endif
++	#include <hal_btcoex_wifionly.h>
++
++#ifdef CONFIG_SDIO_HCI
++	#include <hal_sdio.h>
++#endif
++#ifdef CONFIG_GSPI_HCI
++	#include <hal_gspi.h>
++#endif
++
++#if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)
++#include "../hal/hal_dm_acs.h"
++#endif
++
++/*
++ * <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
++ *   */
++typedef enum _RT_MULTI_FUNC {
++	RT_MULTI_FUNC_NONE	= 0x00,
++	RT_MULTI_FUNC_WIFI	= 0x01,
++	RT_MULTI_FUNC_BT		= 0x02,
++	RT_MULTI_FUNC_GPS	= 0x04,
++} RT_MULTI_FUNC, *PRT_MULTI_FUNC;
++/*
++ * <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
++ *   */
++typedef enum _RT_POLARITY_CTL {
++	RT_POLARITY_LOW_ACT	= 0,
++	RT_POLARITY_HIGH_ACT	= 1,
++} RT_POLARITY_CTL, *PRT_POLARITY_CTL;
++
++/* For RTL8723 regulator mode. by tynli. 2011.01.14. */
++typedef enum _RT_REGULATOR_MODE {
++	RT_SWITCHING_REGULATOR	= 0,
++	RT_LDO_REGULATOR			= 1,
++} RT_REGULATOR_MODE, *PRT_REGULATOR_MODE;
++
++/*
++ * Interface type.
++ *   */
++typedef	enum _INTERFACE_SELECT_PCIE {
++	INTF_SEL0_SOLO_MINICARD			= 0,		/* WiFi solo-mCard */
++	INTF_SEL1_BT_COMBO_MINICARD		= 1,		/* WiFi+BT combo-mCard */
++	INTF_SEL2_PCIe						= 2,		/* PCIe Card */
++} INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE;
++
++
++typedef	enum _INTERFACE_SELECT_USB {
++	INTF_SEL0_USB 				= 0,		/* USB */
++	INTF_SEL1_USB_High_Power  	= 1,		/* USB with high power PA */
++	INTF_SEL2_MINICARD		  	= 2,		/* Minicard */
++	INTF_SEL3_USB_Solo 		= 3,		/* USB solo-Slim module */
++	INTF_SEL4_USB_Combo		= 4,		/* USB Combo-Slim module */
++	INTF_SEL5_USB_Combo_MF	= 5,		/* USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card */
++} INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB;
++
++typedef enum _RT_AMPDU_BRUST_MODE {
++	RT_AMPDU_BRUST_NONE		= 0,
++	RT_AMPDU_BRUST_92D		= 1,
++	RT_AMPDU_BRUST_88E		= 2,
++	RT_AMPDU_BRUST_8812_4	= 3,
++	RT_AMPDU_BRUST_8812_8	= 4,
++	RT_AMPDU_BRUST_8812_12	= 5,
++	RT_AMPDU_BRUST_8812_15	= 6,
++	RT_AMPDU_BRUST_8723B		= 7,
++} RT_AMPDU_BRUST, *PRT_AMPDU_BRUST_MODE;
++
++/* Tx Power Limit Table Size */
++#define MAX_REGULATION_NUM						4
++#define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE	4
++#define MAX_2_4G_BANDWIDTH_NUM					2
++#define MAX_RATE_SECTION_NUM						10
++#define MAX_5G_BANDWIDTH_NUM						4
++
++#define NUM_OF_TARGET_TXPWR_2G	10 /* CCK:1, OFDM:1, HT:4, VHT:4 */
++#define NUM_OF_TARGET_TXPWR_5G	9 /* OFDM:1, HT:4, VHT:4 */
++
++#ifdef RTW_RX_AGGREGATION
++typedef enum _RX_AGG_MODE {
++	RX_AGG_DISABLE,
++	RX_AGG_DMA,
++	RX_AGG_USB,
++	RX_AGG_MIX
++} RX_AGG_MODE;
++
++/* #define MAX_RX_DMA_BUFFER_SIZE	10240 */		/* 10K for 8192C RX DMA buffer */
++
++#endif /* RTW_RX_AGGREGATION */
++
++/* E-Fuse */
++#ifdef CONFIG_RTL8188E
++	#define EFUSE_MAP_SIZE	512
++#endif
++#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
++	#define EFUSE_MAP_SIZE	512
++#endif
++#ifdef CONFIG_RTL8192E
++	#define EFUSE_MAP_SIZE	512
++#endif
++#ifdef CONFIG_RTL8723B
++	#define EFUSE_MAP_SIZE	512
++#endif
++#ifdef CONFIG_RTL8814A
++	#define EFUSE_MAP_SIZE	512
++#endif
++#ifdef CONFIG_RTL8703B
++	#define EFUSE_MAP_SIZE	512
++#endif
++#ifdef CONFIG_RTL8723D
++	#define EFUSE_MAP_SIZE	512
++#endif
++#ifdef CONFIG_RTL8188F
++	#define EFUSE_MAP_SIZE	512
++#endif
++#ifdef CONFIG_RTL8188GTV
++	#define EFUSE_MAP_SIZE	512
++#endif
++#ifdef CONFIG_RTL8710B
++	#define EFUSE_MAP_SIZE	512
++#endif
++#ifdef CONFIG_RTL8192F
++	#define EFUSE_MAP_SIZE	512
++#endif
++
++#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8814B)
++	#define EFUSE_MAX_SIZE	1024
++#elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8710B)
++	#define EFUSE_MAX_SIZE	256
++#else
++	#define EFUSE_MAX_SIZE	512
++#endif
++/* end of E-Fuse */
++
++#define Mac_OFDM_OK			0x00000000
++#define Mac_OFDM_Fail		0x10000000
++#define Mac_OFDM_FasleAlarm	0x20000000
++#define Mac_CCK_OK			0x30000000
++#define Mac_CCK_Fail		0x40000000
++#define Mac_CCK_FasleAlarm	0x50000000
++#define Mac_HT_OK			0x60000000
++#define Mac_HT_Fail			0x70000000
++#define Mac_HT_FasleAlarm	0x90000000
++#define Mac_DropPacket		0xA0000000
++
++#ifdef CONFIG_RF_POWER_TRIM
++#if defined(CONFIG_RTL8723B)
++	#define REG_RF_BB_GAIN_OFFSET	0x7f
++	#define RF_GAIN_OFFSET_MASK		0xfffff
++#elif defined(CONFIG_RTL8188E)
++	#define REG_RF_BB_GAIN_OFFSET	0x55
++	#define RF_GAIN_OFFSET_MASK		0xfffff
++#else
++	#define REG_RF_BB_GAIN_OFFSET	0x55
++	#define RF_GAIN_OFFSET_MASK		0xfffff
++#endif /* CONFIG_RTL8723B */
++#endif /*CONFIG_RF_POWER_TRIM*/
++
++/* For store initial value of BB register */
++typedef struct _BB_INIT_REGISTER {
++	u16	offset;
++	u32	value;
++
++} BB_INIT_REGISTER, *PBB_INIT_REGISTER;
++
++#define PAGE_SIZE_128	128
++#define PAGE_SIZE_256	256
++#define PAGE_SIZE_512	512
++
++#define HCI_SUS_ENTER		0
++#define HCI_SUS_LEAVING		1
++#define HCI_SUS_LEAVE		2
++#define HCI_SUS_ENTERING	3
++#define HCI_SUS_ERR			4
++
++#define EFUSE_FILE_UNUSED 0
++#define EFUSE_FILE_FAILED 1
++#define EFUSE_FILE_LOADED 2
++
++#define MACADDR_FILE_UNUSED 0
++#define MACADDR_FILE_FAILED 1
++#define MACADDR_FILE_LOADED 2
++
++#define MAX_IQK_INFO_BACKUP_CHNL_NUM	5
++#define MAX_IQK_INFO_BACKUP_REG_NUM		10
++
++struct kfree_data_t {
++	u8 flag;
++	s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX];
++
++#if CONFIG_IEEE80211_BAND_5GHZ
++	s8 pa_bias_5g[RF_PATH_MAX];
++	s8 pad_bias_5g[RF_PATH_MAX];
++#endif
++	s8 thermal;
++};
++
++bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data);
++
++struct hal_spec_t {
++	char *ic_name;
++	u8 macid_num;
++
++	u8 sec_cam_ent_num;
++	u8 sec_cap;
++	u8 wow_cap;
++	u8 macid_cap;
++	u16 macid_txrpt;
++	u8 macid_txrpt_pgsz;
++
++	u8 rfpath_num_2g:4;	/* used for tx power index path */
++	u8 rfpath_num_5g:4;	/* used for tx power index path */
++	u8 rf_reg_path_num;
++	u8 rf_reg_path_avail_num;
++	u8 rf_reg_trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp */
++	u8 max_tx_cnt;
++
++	u8 tx_nss_num:4;
++	u8 rx_nss_num:4;
++
++	u8 band_cap;	/* value of BAND_CAP_XXX */
++	u8 bw_cap;		/* value of BW_CAP_XXX */
++	u8 port_num;
++	u8 proto_cap;	/* value of PROTO_CAP_XXX */
++
++	u8 txgi_max; /* maximum tx power gain index */
++	u8 txgi_pdbm; /* tx power gain index per dBm */
++
++	u8 wl_func;		/* value of WL_FUNC_XXX */
++
++	u8 tx_aclt_unit_factor; /* how many 32us */
++
++	u8 rx_tsf_filter:1;
++
++	u8 pg_txpwr_saddr; /* starting address of PG tx power info */
++	u8 pg_txgi_diff_factor; /* PG tx power gain index diff to tx power gain index */
++
++	u8 hci_type;	/* value of HCI Type */
++};
++
++#define HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) ((_spec)->rfpath_num_2g > (_path))
++#define HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) ((_spec)->rfpath_num_5g > (_path))
++#define HAL_SPEC_CHK_RF_PATH(_spec, _band, _path) ( \
++	_band == BAND_ON_2_4G ? HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) : \
++	_band == BAND_ON_5G ? HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) : 0)
++
++#ifdef CONFIG_PHY_CAPABILITY_QUERY
++struct phy_spec_t {
++	u32 trx_cap;
++	u32 stbc_cap;
++	u32 ldpc_cap;
++	u32 txbf_param;
++	u32 txbf_cap;
++};
++#endif
++struct hal_iqk_reg_backup {
++	u8 central_chnl;
++	u8 bw_mode;
++	u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM];
++};
++
++
++typedef struct hal_p2p_ps_para {
++	/*DW0*/
++	u8  offload_en:1;
++	u8  role:1;
++	u8  ctwindow_en:1;
++	u8  noa_en:1;
++	u8  noa_sel:1;
++	u8  all_sta_sleep:1;
++	u8  discovery:1;
++	u8  disable_close_rf:1;
++	u8  p2p_port_id;
++	u8  p2p_group;
++	u8  p2p_macid;
++
++	/*DW1*/
++	u8 ctwindow_length;
++	u8 rsvd3;
++	u8 rsvd4;
++	u8 rsvd5;
++
++	/*DW2*/
++	u32 noa_duration_para;
++
++	/*DW3*/
++	u32 noa_interval_para;
++
++	/*DW4*/
++	u32 noa_start_time_para;
++
++	/*DW5*/
++	u32 noa_count_para;
++} HAL_P2P_PS_PARA, *PHAL_P2P_PS_PARA;
++
++#define TXPWR_LMT_RS_CCK	0
++#define TXPWR_LMT_RS_OFDM	1
++#define TXPWR_LMT_RS_HT		2
++#define TXPWR_LMT_RS_VHT	3
++#define TXPWR_LMT_RS_NUM	4
++
++#define TXPWR_LMT_RS_NUM_2G	4 /* CCK, OFDM, HT, VHT */
++#define TXPWR_LMT_RS_NUM_5G	3 /* OFDM, HT, VHT */
++
++#if CONFIG_TXPWR_LIMIT
++extern const char *const _txpwr_lmt_rs_str[];
++#define txpwr_lmt_rs_str(rs) (((rs) >= TXPWR_LMT_RS_NUM) ? _txpwr_lmt_rs_str[TXPWR_LMT_RS_NUM] : _txpwr_lmt_rs_str[(rs)])
++
++struct txpwr_lmt_ent {
++	_list list;
++
++	s8 lmt_2g[MAX_2_4G_BANDWIDTH_NUM]
++		[TXPWR_LMT_RS_NUM_2G]
++		[CENTER_CH_2G_NUM]
++		[MAX_TX_COUNT];
++
++#if CONFIG_IEEE80211_BAND_5GHZ
++	s8 lmt_5g[MAX_5G_BANDWIDTH_NUM]
++		[TXPWR_LMT_RS_NUM_5G]
++		[CENTER_CH_5G_ALL_NUM]
++		[MAX_TX_COUNT];
++#endif
++
++	char regd_name[0];
++};
++#endif /* CONFIG_TXPWR_LIMIT */
++
++typedef struct hal_com_data {
++	HAL_VERSION			version_id;
++	RT_MULTI_FUNC		MultiFunc; /* For multi-function consideration. */
++	RT_POLARITY_CTL		PolarityCtl; /* For Wifi PDn Polarity control. */
++	RT_REGULATOR_MODE	RegulatorMode; /* switching regulator or LDO */
++	u8	hw_init_completed;
++	/****** FW related ******/
++	u32 firmware_size;
++	u16 firmware_version;
++	u16	FirmwareVersionRev;
++	u16 firmware_sub_version;
++	u16	FirmwareSignature;
++	u8	RegFWOffload;
++	u8	bFWReady;
++	u8	bBTFWReady;
++	u8	fw_ractrl;
++	u8	LastHMEBoxNum;	/* H2C - for host message to fw */
++#ifdef CONFIG_LPS_1T1R
++	u8 lps_1t1r;
++#endif
++
++	/****** current WIFI_PHY values ******/
++	WIRELESS_MODE	CurrentWirelessMode;
++	enum channel_width current_channel_bw;
++	BAND_TYPE		current_band_type;	/* 0:2.4G, 1:5G */
++	u8				current_channel;
++	u8				cch_20;
++	u8				cch_40;
++	u8				cch_80;
++	u8				CurrentCenterFrequencyIndex1;
++	u8				nCur40MhzPrimeSC;	/* Control channel sub-carrier */
++	u8				nCur80MhzPrimeSC;   /* used for primary 40MHz of 80MHz mode */
++	BOOLEAN		bSwChnlAndSetBWInProgress;
++	u8				bDisableSWChannelPlan; /* flag of disable software change channel plan	 */
++	u16				BasicRateSet;
++	u32				ReceiveConfig;
++#ifdef CONFIG_WIFI_MONITOR
++	struct mon_reg_backup		mon_backup; /* used for switching back from monitor mode */
++#endif /* CONFIG_WIFI_MONITOR */
++	u8				rx_tsf_addr_filter_config; /* for 8822B/8821C USE */
++	BOOLEAN			bSwChnl;
++	BOOLEAN			bSetChnlBW;
++	BOOLEAN			bSWToBW40M;
++	BOOLEAN			bSWToBW80M;
++	BOOLEAN			bChnlBWInitialized;
++
++#ifdef CONFIG_RTW_ACS
++	struct auto_chan_sel acs;
++#endif
++#ifdef CONFIG_BCN_RECOVERY
++	u8 issue_bcn_fail;
++#endif /*CONFIG_BCN_RECOVERY*/
++
++	/****** rf_ctrl *****/
++	u8	rf_chip;
++
++	u8 trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp */
++	u8	rf_type;	/*enum rf_type , is RF_PATH - GET_HAL_RFPATH*/
++	u8	NumTotalRFPath; /*GET_HAL_RFPATH_NUM*/
++	u8 max_tx_cnt;
++	u8	tx_nss; /*tx Spatial Streams - GET_HAL_TX_NSS*/
++	u8	rx_nss; /*rx Spatial Streams - GET_HAL_RX_NSS*/
++
++	u8	PackageType;
++	u8	antenna_test;
++
++	/* runtime TRX path setting */
++	enum bb_path txpath; /* TX path bmp */
++	enum bb_path rxpath; /* RX path bmp */
++	enum bb_path txpath_nss[4]; /* path bmp for NSS TX, [0] for 1SS, [3] for 4SS */
++	u8 txpath_num_nss[4]; /* path num for NSS TX, [0] for 1SS, [3] for 4SS */
++
++	/****** Debug ******/
++	u16	ForcedDataRate;	/* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */
++	u8	bDumpRxPkt;
++	u8	bDumpTxPkt;
++	u8	dis_turboedca; /* 1: disable turboedca, 
++						  2: disable turboedca and setting EDCA parameter based on the input parameter*/
++	u32 edca_param_mode;
++
++	/****** EEPROM setting.******/
++	u8	bautoload_fail_flag;
++	u8	efuse_file_status;
++	u8	macaddr_file_status;
++	u8	EepromOrEfuse;
++	u8	efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/
++	u8	InterfaceSel; /* board type kept in eFuse */
++	u16	CustomerID;
++
++	u16	EEPROMVID;
++	u16	EEPROMSVID;
++#ifdef CONFIG_USB_HCI
++	u8	EEPROMUsbSwitch;
++	u16	EEPROMPID;
++	u16	EEPROMSDID;
++#endif
++#ifdef CONFIG_PCI_HCI
++	u16	EEPROMDID;
++	u16	EEPROMSMID;
++#endif
++
++	u8	EEPROMCustomerID;
++	u8	EEPROMSubCustomerID;
++	u8	EEPROMVersion;
++	u8	EEPROMRegulatory;
++	u8	eeprom_thermal_meter;
++	u8	EEPROMBluetoothCoexist;
++	u8	EEPROMBluetoothType;
++	u8	EEPROMBluetoothAntNum;
++	u8	EEPROMBluetoothAntIsolation;
++	u8	EEPROMBluetoothRadioShared;
++	u8	EEPROMMACAddr[ETH_ALEN];
++
++	u8 eeprom_trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp. 0x00:not specified */
++	u8 eeprom_max_tx_cnt; /* 0: not specified */
++
++	u8	tx_bbswing_24G;
++	u8	tx_bbswing_5G;
++	u8	efuse0x3d7;	/* efuse[0x3D7] */
++	u8	efuse0x3d8;	/* efuse[0x3D8] */
++
++#ifdef CONFIG_RF_POWER_TRIM
++	u8	EEPROMRFGainOffset;
++	u8	EEPROMRFGainVal;
++	struct kfree_data_t kfree_data;
++#endif /*CONFIG_RF_POWER_TRIM*/
++
++#ifdef CONFIG_RTL8814A
++	u32	BackUp_BB_REG_4_2nd_CCA[3];
++#endif
++#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \
++	defined(CONFIG_RTL8723D) || \
++	defined(CONFIG_RTL8192F)
++
++	u8	adjuseVoltageVal;
++	u8	need_restore;
++#endif
++	u8	EfuseUsedPercentage;
++	u16	EfuseUsedBytes;
++	/*u8		EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/
++	EFUSE_HAL	EfuseHal;
++
++	u8 txpwr_pg_mode; /* enum txpwr_pg_mode */
++
++	/*---------------------------------------------------------------------------------*/
++#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	/* 2.4G TX power info for target TX power*/
++	u8	Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
++	u8	Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
++	s8	CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
++	s8	OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
++	s8	BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
++	s8	BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
++
++	/* 5G TX power info for target TX power*/
++#if CONFIG_IEEE80211_BAND_5GHZ
++	u8	Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM];
++	u8	Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM];
++	s8	OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
++	s8	BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
++	s8	BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
++	s8	BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
++#endif
++#endif /* CONFIG_TXPWR_PG_WITH_PWR_IDX */
++
++	u8 txpwr_by_rate_undefined_band_path[TX_PWR_BY_RATE_NUM_BAND]
++		[TX_PWR_BY_RATE_NUM_RF];
++
++	s8	TxPwrByRate[TX_PWR_BY_RATE_NUM_BAND]
++		[TX_PWR_BY_RATE_NUM_RF]
++		[TX_PWR_BY_RATE_NUM_RATE];
++
++	/* Store the target power for each rate section and rf path */
++	u8	target_txpwr_2g[TX_PWR_BY_RATE_NUM_RF]
++		[NUM_OF_TARGET_TXPWR_2G];
++	u8	target_txpwr_5g[TX_PWR_BY_RATE_NUM_RF]
++		[NUM_OF_TARGET_TXPWR_5G];
++
++	bool set_entire_txpwr;
++
++#if defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
++	u32 txagc_set_buf;
++#endif
++
++#ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
++	u8 txpwr_idx_offload_buf[3]; /* for CCK, OFDM, HT1SS */
++	struct submit_ctx txpwr_idx_offload_sctx;
++#endif
++
++	u8	txpwr_by_rate_loaded:1;
++	u8	txpwr_by_rate_from_file:1;
++	u8	txpwr_limit_loaded:1;
++	u8	txpwr_limit_from_file:1;
++
++	/* Read/write are allow for following hardware information variables	 */
++	u8	crystal_cap;
++
++	u8	PAType_2G;
++	u8	PAType_5G;
++	u8	LNAType_2G;
++	u8	LNAType_5G;
++	u8	ExternalPA_2G;
++	u8	ExternalLNA_2G;
++	u8	external_pa_5g;
++	u8	external_lna_5g;
++	u16	TypeGLNA;
++	u16	TypeGPA;
++	u16	TypeALNA;
++	u16	TypeAPA;
++	u16	rfe_type;
++
++	u8	bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
++	u32	ac_param_be; /* Original parameter for BE, use for EDCA turbo.	*/
++	u8	is_turbo_edca;
++	u8	prv_traffic_idx;
++	BB_REGISTER_DEFINITION_T	PHYRegDef[MAX_RF_PATH];	/* Radio A/B/C/D */
++
++	u32	RfRegChnlVal[MAX_RF_PATH];
++
++	/* RDG enable */
++	BOOLEAN	 bRDGEnable;
++
++	#if defined (CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
++	u32 RegRRSR;
++	#endif
++
++	/****** antenna diversity ******/
++	u8	AntDivCfg;
++	u8	with_extenal_ant_switch;
++	u8	b_fix_tx_ant;
++	u8	AntDetection;
++	u8	TRxAntDivType;
++	u8	ant_path; /* for 8723B s0/s1 selection	 */
++	u32	antenna_tx_path;					/* Antenna path Tx */
++	u32	AntennaRxPath;					/* Antenna path Rx */
++	u8 sw_antdiv_bl_state;
++
++	/******** PHY DM & DM Section **********/
++	_lock		IQKSpinLock;
++	u8			INIDATA_RATE[MACID_NUM_SW_LIMIT];
++
++	struct dm_struct	 odmpriv;
++	u64			bk_rf_ability;
++	u8			bIQKInitialized;
++	u8			bNeedIQK;
++	u8			neediqk_24g;
++	u8			IQK_MP_Switch;
++	u8			bScanInProcess;
++	u8			phydm_init_result; /*BB and RF para match or not*/
++	/******** PHY DM & DM Section **********/
++
++
++
++	/* 2010/08/09 MH Add CU power down mode. */
++	BOOLEAN		pwrdown;
++
++#ifdef CONFIG_P2P
++#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
++	u16 p2p_ps_offload;
++#else
++	u8	p2p_ps_offload;
++#endif
++#endif
++	/* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
++	u8	bMacPwrCtrlOn;
++	u8 hci_sus_state;
++
++	u8	RegIQKFWOffload;
++	struct submit_ctx	iqk_sctx;
++	u8 ch_switch_offload;
++	struct submit_ctx chsw_sctx;
++
++	RT_AMPDU_BRUST		AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */
++
++	u8	OutEpQueueSel;
++	u8	OutEpNumber;
++
++#ifdef RTW_RX_AGGREGATION
++	RX_AGG_MODE rxagg_mode;
++
++	/* For RX Aggregation DMA Mode */
++	u8 rxagg_dma_size;
++	u8 rxagg_dma_timeout;
++#endif /* RTW_RX_AGGREGATION */
++
++	bool intf_start;
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	/*  */
++	/* For SDIO Interface HAL related */
++	/*  */
++
++	/*  */
++	/* SDIO ISR Related */
++	/*
++	*	u32			IntrMask[1];
++	*	u32			IntrMaskToSet[1];
++	*	LOG_INTERRUPT		InterruptLog; */
++	u32			sdio_himr;
++	u32			sdio_hisr;
++#ifndef RTW_HALMAC
++	/*  */
++	/* SDIO Tx FIFO related. */
++	/*  */
++	/* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */
++#ifdef CONFIG_RTL8192F
++	u16			SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
++#else
++	u8			SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
++#endif/*CONFIG_RTL8192F*/
++#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
++	u8			sdio_avail_int_en_q;
++#endif
++	_lock		SdioTxFIFOFreePageLock;
++	u8			SdioTxOQTMaxFreeSpace;
++	u8			SdioTxOQTFreeSpace;
++#else /* RTW_HALMAC */
++	u16			SdioTxOQTFreeSpace;
++#endif /* RTW_HALMAC */
++
++	/*  */
++	/* SDIO Rx FIFO related. */
++	/*  */
++	u8			SdioRxFIFOCnt;
++#ifdef CONFIG_RTL8822C
++	u32			SdioRxFIFOSize;
++#else
++	u16			SdioRxFIFOSize;
++#endif
++
++#ifndef RTW_HALMAC
++	u32			sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */
++#else
++#ifdef CONFIG_RTL8821C
++	u16			tx_high_page;
++	u16			tx_low_page;
++	u16			tx_normal_page;
++	u16			tx_extra_page;
++	u16			tx_pub_page;
++	u8			max_oqt_size;
++	#ifdef XMIT_BUF_SIZE
++	u32			max_xmit_size_vovi;
++	u32			max_xmit_size_bebk;
++	#endif /*XMIT_BUF_SIZE*/
++	u16			max_xmit_page;
++	u16			max_xmit_page_vo;
++	u16			max_xmit_page_vi;
++	u16			max_xmit_page_be;
++	u16			max_xmit_page_bk;
++
++#endif /*#ifdef CONFIG_RTL8821C*/
++#endif /* !RTW_HALMAC */
++#endif /* CONFIG_SDIO_HCI */
++
++#ifdef CONFIG_USB_HCI
++
++	/* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */
++	BOOLEAN		UsbRxHighSpeedMode;
++	BOOLEAN		UsbTxVeryHighSpeedMode;
++	u32			UsbBulkOutSize;
++	BOOLEAN		bSupportUSB3;
++	u8			usb_intf_start;
++
++	/* Interrupt relatd register information. */
++	u32			IntArray[3];/* HISR0,HISR1,HSISR */
++	u32			IntrMask[3];
++#ifdef CONFIG_USB_TX_AGGREGATION
++	u8			UsbTxAggMode;
++	u8			UsbTxAggDescNum;
++#endif /* CONFIG_USB_TX_AGGREGATION */
++
++#ifdef CONFIG_USB_RX_AGGREGATION
++	u16			HwRxPageSize;				/* Hardware setting */
++
++	/* For RX Aggregation USB Mode */
++	u8			rxagg_usb_size;
++	u8			rxagg_usb_timeout;
++#endif/* CONFIG_USB_RX_AGGREGATION */
++#endif /* CONFIG_USB_HCI */
++
++
++#ifdef CONFIG_PCI_HCI
++	/*  */
++	/* EEPROM setting. */
++	/*  */
++	u32			TransmitConfig;
++	u32			IntrMaskToSet[2];
++	u32			IntArray[4];
++	u32			IntrMask[4];
++	u32			SysIntArray[1];
++	u32			SysIntrMask[1];
++	u32			IntrMaskReg[2];
++	u32			IntrMaskDefault[4];
++
++	u32			pci_backdoor_ctrl;
++
++	u8			bDefaultAntenna;
++
++	u8			bInterruptMigration;
++	u8			bDisableTxInt;
++
++	u16			RxTag;
++#endif /* CONFIG_PCI_HCI */
++
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++	struct sreset_priv srestpriv;
++#endif /* #ifdef DBG_CONFIG_ERROR_DETECT */
++
++#ifdef CONFIG_BT_COEXIST
++	/* For bluetooth co-existance */
++	BT_COEXIST		bt_coexist;
++#endif /* CONFIG_BT_COEXIST */
++
++#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) \
++	|| defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D)|| defined(CONFIG_RTL8192F)
++#ifndef CONFIG_PCI_HCI	/* mutual exclusive with PCI -- so they're SDIO and GSPI */
++	/* Interrupt relatd register information. */
++	u32			SysIntrStatus;
++	u32			SysIntrMask;
++#endif
++#endif /*endif CONFIG_RTL8723B	*/
++
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++	char	para_file_buf[MAX_PARA_FILE_BUF_LEN];
++	char *mac_reg;
++	u32	mac_reg_len;
++	char *bb_phy_reg;
++	u32	bb_phy_reg_len;
++	char *bb_agc_tab;
++	u32	bb_agc_tab_len;
++	char *bb_phy_reg_pg;
++	u32	bb_phy_reg_pg_len;
++	char *bb_phy_reg_mp;
++	u32	bb_phy_reg_mp_len;
++	char *rf_radio_a;
++	u32	rf_radio_a_len;
++	char *rf_radio_b;
++	u32	rf_radio_b_len;
++	char *rf_tx_pwr_track;
++	u32	rf_tx_pwr_track_len;
++	char *rf_tx_pwr_lmt;
++	u32	rf_tx_pwr_lmt_len;
++#endif
++
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++	struct noise_monitor nm;
++#endif
++
++	struct hal_spec_t hal_spec;
++#ifdef CONFIG_PHY_CAPABILITY_QUERY
++	struct phy_spec_t phy_spec;
++#endif
++	u8	RfKFreeEnable;
++	u8	RfKFree_ch_group;
++	BOOLEAN				bCCKinCH14;
++	BB_INIT_REGISTER	RegForRecover[5];
++
++#if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN)
++	BOOLEAN bCorrectBCN;
++#endif
++#ifdef CONFIG_RTL8814A
++	u32 RxGainOffset[4]; /*{2G, 5G_Low, 5G_Middle, G_High}*/
++	u8 BackUp_IG_REG_4_Chnl_Section[4]; /*{A,B,C,D}*/
++#endif
++	struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM];
++
++#ifdef RTW_HALMAC
++	u16 drv_rsvd_page_number;
++#endif
++
++#ifdef CONFIG_BEAMFORMING
++	u8 backup_snd_ptcl_ctrl;
++#ifdef RTW_BEAMFORMING_VERSION_2
++	struct beamforming_info beamforming_info;
++#endif /* RTW_BEAMFORMING_VERSION_2 */
++#endif /* CONFIG_BEAMFORMING */
++
++	u8 not_xmitframe_fw_dl; /*not use xmitframe to download fw*/
++	u8 phydm_op_mode;
++
++	u8 in_cta_test;
++
++#ifdef CONFIG_RTW_LED
++	struct led_priv led;
++#endif
++	/* for multi channel case (ex: MCC/TDLS) */
++	u8 multi_ch_switch_mode;
++	
++#ifdef CONFIG_RTL8814B
++	u8 dma_ch_map[32];	/* TXDESC qsel maximum size */
++#endif
++
++} HAL_DATA_COMMON, *PHAL_DATA_COMMON;
++
++typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE;
++#define GET_HAL_DATA(__pAdapter)		((HAL_DATA_TYPE *)(((struct _ADAPTER*)__pAdapter)->HalData))
++#define GET_HAL_SPEC(__pAdapter)			(&(GET_HAL_DATA((__pAdapter))->hal_spec))
++#define adapter_to_led(adapter) (&(GET_HAL_DATA(adapter)->led))
++
++#define RT_GetInterfaceSelection(_Adapter)		(GET_HAL_DATA(_Adapter)->InterfaceSel)
++
++#define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data))
++
++#define	SUPPORT_HW_RADIO_DETECT(Adapter)	(RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD || \
++		RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo || \
++		RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo)
++
++#define get_hal_mac_addr(adapter)				(GET_HAL_DATA(adapter)->EEPROMMACAddr)
++#define is_boot_from_eeprom(adapter)			(GET_HAL_DATA(adapter)->EepromOrEfuse)
++#define rtw_get_hw_init_completed(adapter)		(GET_HAL_DATA(adapter)->hw_init_completed)
++#define rtw_set_hw_init_completed(adapter, cmp)	(GET_HAL_DATA(adapter)->hw_init_completed = cmp)
++#define rtw_is_hw_init_completed(adapter)		(GET_HAL_DATA(adapter)->hw_init_completed == _TRUE)
++
++/* refer to (hal_data->version_id.RFType / registrypriv->rf_path / 8814a from efuse or registrypriv)*/
++#define GET_HAL_RFPATH(adapter)			(GET_HAL_DATA(adapter)->rf_type)
++#define GET_HAL_RFPATH_NUM(adapter)		(GET_HAL_DATA(adapter)->NumTotalRFPath)
++#define GET_HAL_TX_PATH_BMP(adapter)	((GET_HAL_DATA(adapter)->trx_path_bmp & 0xF0) >> 4)
++#define GET_HAL_RX_PATH_BMP(adapter)	(GET_HAL_DATA(adapter)->trx_path_bmp & 0x0F)
++
++/* refer to (registrypriv-> tx_nss,rx_nss / hal_spec->tx_nss_num,rx_nss_num)*/
++#define GET_HAL_TX_NSS(adapter)			(GET_HAL_DATA(adapter)->tx_nss)
++#define GET_HAL_RX_NSS(adapter)			(GET_HAL_DATA(adapter)->rx_nss)
++
++#endif
++
++#ifdef RTW_HALMAC
++int rtw_halmac_deinit_adapter(struct dvobj_priv *);
++#endif /* RTW_HALMAC */
++
++#endif /* __HAL_DATA_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_gspi.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_gspi.h
+new file mode 100644
+index 000000000..51d491cdb
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_gspi.h
+@@ -0,0 +1,26 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL_GSPI_H_
++#define __HAL_GSPI_H_
++
++#define ffaddr2deviceId(pdvobj, addr)	(pdvobj->Queue2Pipe[addr])
++
++u8 rtw_hal_gspi_max_txoqt_free_space(_adapter *padapter);
++u8 rtw_hal_gspi_query_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
++void rtw_hal_gspi_update_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
++void rtw_hal_set_gspi_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ);
++u32 rtw_hal_get_gspi_tx_max_length(PADAPTER padapter, u8 queue_idx);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_ic_cfg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_ic_cfg.h
+new file mode 100644
+index 000000000..aef4dd2bf
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_ic_cfg.h
+@@ -0,0 +1,602 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL_IC_CFG_H__
++#define __HAL_IC_CFG_H__
++
++#define RTL8188E_SUPPORT				0
++#define RTL8812A_SUPPORT				0
++#define RTL8821A_SUPPORT				0
++#define RTL8723B_SUPPORT				0
++#define RTL8723D_SUPPORT				0
++#define RTL8192E_SUPPORT				0
++#define RTL8192F_SUPPORT				0
++#define RTL8814A_SUPPORT				0
++#define RTL8195A_SUPPORT				0
++#define RTL8197F_SUPPORT				0
++#define RTL8703B_SUPPORT				0
++#define RTL8188F_SUPPORT				0
++#define RTL8822B_SUPPORT				0
++#define RTL8821B_SUPPORT				0
++#define RTL8821C_SUPPORT				0
++#define RTL8710B_SUPPORT				0
++#define RTL8814B_SUPPORT				0
++#define RTL8824B_SUPPORT				0
++#define RTL8198F_SUPPORT				0
++#define RTL8195B_SUPPORT				0
++#define RTL8822C_SUPPORT				0
++#define RTL8721D_SUPPORT				0
++#define RTL8812F_SUPPORT				0
++#define RTL8197G_SUPPORT				0
++#define RTL8710C_SUPPORT				0
++
++
++/*#if (RTL8188E_SUPPORT==1)*/
++#define RATE_ADAPTIVE_SUPPORT			0
++#define POWER_TRAINING_ACTIVE			0
++
++#ifdef CONFIG_MULTIDRV
++#endif
++
++#ifdef CONFIG_RTL8188E
++	#undef RTL8188E_SUPPORT
++	#undef RATE_ADAPTIVE_SUPPORT
++	#undef POWER_TRAINING_ACTIVE
++
++	#define RTL8188E_SUPPORT				1
++	#define RATE_ADAPTIVE_SUPPORT			1
++	#define POWER_TRAINING_ACTIVE			1
++
++	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#endif
++#endif
++
++#ifdef CONFIG_RTL8812A
++	#undef RTL8812A_SUPPORT
++	#define RTL8812A_SUPPORT				1
++	#ifndef CONFIG_FW_C2H_PKT
++		#define CONFIG_FW_C2H_PKT
++	#endif
++	#ifdef CONFIG_BEAMFORMING
++		#define CONFIG_BEAMFORMER_FW_NDPA
++		#define BEAMFORMING_SUPPORT		1	/*for phydm beamforming*/
++		#define SUPPORT_MU_BF				0
++	#endif /*CONFIG_BEAMFORMING*/
++	#define CONFIG_RTS_FULL_BW
++
++	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#endif
++#endif
++
++#ifdef CONFIG_RTL8821A
++	#undef RTL8821A_SUPPORT
++	#define RTL8821A_SUPPORT				1
++	#ifndef CONFIG_FW_C2H_PKT
++		#define CONFIG_FW_C2H_PKT
++	#endif
++	#ifdef CONFIG_BEAMFORMING
++		#define CONFIG_BEAMFORMER_FW_NDPA
++		#define BEAMFORMING_SUPPORT		1	/*for phydm beamforming*/
++		#define SUPPORT_MU_BF				0
++	#endif
++	#define CONFIG_RTS_FULL_BW
++
++	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#endif
++#endif
++
++#ifdef CONFIG_RTL8192E
++	#undef RTL8192E_SUPPORT
++	#define RTL8192E_SUPPORT				1
++	#ifndef CONFIG_FW_C2H_PKT
++		#define CONFIG_FW_C2H_PKT
++	#endif
++	#define CONFIG_RTS_FULL_BW
++
++	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#endif
++#endif
++
++#ifdef CONFIG_RTL8192F
++	#undef RTL8192F_SUPPORT
++	#define RTL8192F_SUPPORT				1
++	#ifndef CONFIG_FW_C2H_PKT
++		#define CONFIG_FW_C2H_PKT
++	#endif
++	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
++		#define CONFIG_RTW_MAC_HIDDEN_RPT
++	#endif
++	/*#define CONFIG_AMPDU_PRETX_CD*/
++	/*#define DBG_LA_MODE*/
++	#ifdef CONFIG_P2P_PS
++		#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
++	#endif
++	#define CONFIG_RTS_FULL_BW
++/*	#define CONFIG_NARROWBAND_SUPPORTING	*/
++	#ifdef CONFIG_NARROWBAND_SUPPORTING
++		#define CONFIG_NB_VALUE		RTW_NB_CONFIG_NONE	/*RTW_NB_CONFIG_WIDTH_10 or RTW_NB_CONFIG_WIDTH_5	*/
++	#endif
++	#ifdef CONFIG_WOWLAN
++		#define CONFIG_WOW_PATTERN_IN_TXFIFO
++	#endif
++
++	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#endif
++#endif
++
++#ifdef CONFIG_RTL8723B
++	#undef RTL8723B_SUPPORT
++	#define RTL8723B_SUPPORT				1
++	#ifndef CONFIG_FW_C2H_PKT
++		#define CONFIG_FW_C2H_PKT
++	#endif
++	#define CONFIG_RTS_FULL_BW
++
++	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#endif
++#endif
++
++#ifdef CONFIG_RTL8723D
++	#undef RTL8723D_SUPPORT
++	#define RTL8723D_SUPPORT				1
++	#ifndef CONFIG_FW_C2H_PKT
++		#define CONFIG_FW_C2H_PKT
++	#endif
++	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
++		#define CONFIG_RTW_MAC_HIDDEN_RPT
++	#endif
++	#ifndef CONFIG_RTW_CUSTOMER_STR
++		#define CONFIG_RTW_CUSTOMER_STR
++	#endif
++	#define CONFIG_RTS_FULL_BW
++
++	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#endif
++#endif
++
++#ifdef CONFIG_RTL8814A
++	#undef RTL8814A_SUPPORT
++	#define RTL8814A_SUPPORT				1
++	#ifndef CONFIG_FW_C2H_PKT
++		#define CONFIG_FW_C2H_PKT
++	#endif
++	#define CONFIG_FW_CORRECT_BCN
++	#ifdef CONFIG_BEAMFORMING
++		#define BEAMFORMING_SUPPORT		1	/*for phydm beamforming*/
++		#define SUPPORT_MU_BF				0
++	#endif
++	#define CONFIG_RTS_FULL_BW
++
++	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#endif
++#endif
++
++#ifdef CONFIG_RTL8703B
++	#undef RTL8703B_SUPPORT
++	#define RTL8703B_SUPPORT				1
++	#ifndef CONFIG_FW_C2H_PKT
++		#define CONFIG_FW_C2H_PKT
++	#endif
++	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
++		#define CONFIG_RTW_MAC_HIDDEN_RPT
++	#endif
++	#define CONFIG_RTS_FULL_BW
++
++	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#endif
++#endif
++
++#ifdef CONFIG_RTL8188F
++	#undef RTL8188F_SUPPORT
++	#define RTL8188F_SUPPORT				1
++	#ifndef CONFIG_FW_C2H_PKT
++		#define CONFIG_FW_C2H_PKT
++	#endif
++	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
++		#define CONFIG_RTW_MAC_HIDDEN_RPT
++	#endif
++	#ifndef CONFIG_RTW_CUSTOMER_STR
++		#define CONFIG_RTW_CUSTOMER_STR
++	#endif
++	#define CONFIG_RTS_FULL_BW
++
++	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#endif
++#endif
++
++#ifdef CONFIG_RTL8188GTV
++	#undef RTL8188F_SUPPORT
++	#define RTL8188F_SUPPORT				1
++	#ifndef CONFIG_FW_C2H_PKT
++		#define CONFIG_FW_C2H_PKT
++	#endif
++	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
++		#define CONFIG_RTW_MAC_HIDDEN_RPT
++	#endif
++	#ifndef CONFIG_RTW_CUSTOMER_STR
++		#define CONFIG_RTW_CUSTOMER_STR
++	#endif
++	#define CONFIG_RTS_FULL_BW
++
++	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#endif
++#endif
++
++#ifdef CONFIG_RTL8822B
++	#undef RTL8822B_SUPPORT
++	#define RTL8822B_SUPPORT				1
++	#ifndef CONFIG_FW_C2H_PKT
++		#define CONFIG_FW_C2H_PKT
++	#endif /* CONFIG_FW_C2H_PKT */
++	#define RTW_TX_PA_BIAS	/* Adjust TX PA Bias from eFuse */
++	#define RTW_AMPDU_AGG_RETRY_AND_NEW
++
++	#ifdef CONFIG_WOWLAN
++		#define CONFIG_GTK_OL
++		/*#define CONFIG_ARP_KEEP_ALIVE*/
++
++		#ifdef CONFIG_GPIO_WAKEUP
++			#ifndef WAKEUP_GPIO_IDX
++				#define WAKEUP_GPIO_IDX	6	/* WIFI Chip Side */
++			#endif /* !WAKEUP_GPIO_IDX */
++		#endif /* CONFIG_GPIO_WAKEUP */
++	#endif /* CONFIG_WOWLAN */
++
++	#ifdef CONFIG_CONCURRENT_MODE
++		#define CONFIG_AP_PORT_SWAP
++		#define CONFIG_FW_MULTI_PORT_SUPPORT
++	#endif /* CONFIG_CONCURRENT_MODE */
++
++	/*
++	 * Beamforming related definition
++	 */
++	/* Only support new beamforming mechanism */
++	#ifdef CONFIG_BEAMFORMING
++		#define RTW_BEAMFORMING_VERSION_2
++	#endif /* CONFIG_BEAMFORMING */
++
++	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
++		#define CONFIG_RTW_MAC_HIDDEN_RPT
++	#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */
++
++	#ifndef DBG_RX_DFRAME_RAW_DATA
++		#define DBG_RX_DFRAME_RAW_DATA
++	#endif /* DBG_RX_DFRAME_RAW_DATA */
++
++	#ifndef RTW_IQK_FW_OFFLOAD
++		#define RTW_IQK_FW_OFFLOAD
++	#endif /* RTW_IQK_FW_OFFLOAD */
++
++	/* Checksum offload feature */
++	/*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/
++	#if defined(CONFIG_TCP_CSUM_OFFLOAD_TX) && !defined(CONFIG_RTW_NETIF_SG)
++		#define CONFIG_RTW_NETIF_SG
++	#endif
++	#define CONFIG_TCP_CSUM_OFFLOAD_RX
++
++	#define CONFIG_ADVANCE_OTA
++
++	#ifdef CONFIG_MCC_MODE
++		#define CONFIG_MCC_MODE_V2
++		#define CONFIG_MCC_PHYDM_OFFLOAD
++	#endif /* CONFIG_MCC_MODE */
++
++	#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
++		#define CONFIG_TDLS_CH_SW_V2
++	#endif
++
++	#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
++		#ifdef CONFIG_TDLS_CH_SW_V2
++			#define RTW_CHANNEL_SWITCH_OFFLOAD
++		#endif
++	#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
++
++	#if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW)
++		/* Supported since fw v22.1 */
++		#define RTW_PER_CMD_SUPPORT_FW
++	#endif /* RTW_PER_CMD_SUPPORT_FW */
++	#define CONFIG_SUPPORT_FIFO_DUMP
++	#define CONFIG_HW_P0_TSF_SYNC
++	#define CONFIG_BCN_RECV_TIME
++	#ifdef CONFIG_P2P_PS
++		#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
++	#endif
++	#define CONFIG_RTS_FULL_BW
++
++	#ifdef CONFIG_LPS
++		#define CONFIG_LPS_ACK	/* Supported after FW v30 & v27.9 */
++	#endif
++
++	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#endif
++#endif /* CONFIG_RTL8822B */
++
++#ifdef CONFIG_RTL8822C
++	#undef RTL8822C_SUPPORT
++	#define RTL8822C_SUPPORT				1
++	/*#define DBG_LA_MODE*/
++	#ifndef CONFIG_FW_C2H_PKT
++		#define CONFIG_FW_C2H_PKT
++	#endif /* CONFIG_FW_C2H_PKT */
++	#define RTW_TX_PA_BIAS	/* Adjust TX PA Bias from eFuse */
++
++	#ifdef CONFIG_WOWLAN
++		#define CONFIG_GTK_OL
++		/*#define CONFIG_ARP_KEEP_ALIVE*/
++
++		#ifdef CONFIG_GPIO_WAKEUP
++			#ifndef WAKEUP_GPIO_IDX
++				#define WAKEUP_GPIO_IDX	6	/* WIFI Chip Side */
++			#endif /* !WAKEUP_GPIO_IDX */
++		#endif /* CONFIG_GPIO_WAKEUP */
++	#endif /* CONFIG_WOWLAN */
++
++	#ifdef CONFIG_CONCURRENT_MODE
++		#define CONFIG_AP_PORT_SWAP
++		#define CONFIG_FW_MULTI_PORT_SUPPORT
++	#endif /* CONFIG_CONCURRENT_MODE */
++
++	/*
++	 * Beamforming related definition
++	 */
++	/* Only support new beamforming mechanism */
++	#ifdef CONFIG_BEAMFORMING
++		#define RTW_BEAMFORMING_VERSION_2
++	#endif /* CONFIG_BEAMFORMING */
++
++	#ifdef CONFIG_NO_FW
++		#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
++			#undef CONFIG_RTW_MAC_HIDDEN_RPT
++		#endif
++	#else
++		#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
++			#define CONFIG_RTW_MAC_HIDDEN_RPT
++		#endif
++	#endif
++
++	#ifndef DBG_RX_DFRAME_RAW_DATA
++		#define DBG_RX_DFRAME_RAW_DATA
++	#endif /* DBG_RX_DFRAME_RAW_DATA */
++
++	#ifndef RTW_IQK_FW_OFFLOAD
++		/* #define RTW_IQK_FW_OFFLOAD */
++	#endif /* RTW_IQK_FW_OFFLOAD */
++	#define CONFIG_ADVANCE_OTA
++
++	#ifdef CONFIG_MCC_MODE
++		#define CONFIG_MCC_MODE_V2
++		#define CONFIG_MCC_PHYDM_OFFLOAD
++	#endif /* CONFIG_MCC_MODE */
++
++	#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
++		#define CONFIG_TDLS_CH_SW_V2
++	#endif
++
++	#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
++		#ifdef CONFIG_TDLS_CH_SW_V2
++			#define RTW_CHANNEL_SWITCH_OFFLOAD
++		#endif
++	#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
++
++	#if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW)
++		/* Supported since fw v22.1 */
++		#define RTW_PER_CMD_SUPPORT_FW
++	#endif /* RTW_PER_CMD_SUPPORT_FW */
++	#define CONFIG_SUPPORT_FIFO_DUMP
++	#define CONFIG_HW_P0_TSF_SYNC
++	#define CONFIG_BCN_RECV_TIME
++
++	/*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/
++	#if defined(CONFIG_TCP_CSUM_OFFLOAD_TX) && !defined(CONFIG_RTW_NETIF_SG)
++		#define CONFIG_RTW_NETIF_SG
++	#endif
++	#define CONFIG_TCP_CSUM_OFFLOAD_RX
++
++	#ifdef CONFIG_P2P_PS
++		#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
++	#endif
++	#define CONFIG_RTS_FULL_BW
++	
++	#ifdef CONFIG_LPS
++		#define CONFIG_LPS_ACK	/* Supported after FW v07 */
++		#define CONFIG_LPS_1T1R /* Supported after FW v07 */
++	#endif
++
++	#define CONFIG_BT_EFUSE_MASK
++
++	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#endif
++	#ifndef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
++	#define CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
++	#endif
++
++	#define CONFIG_RTL8822C_XCAP_NEW_POLICY
++#endif /* CONFIG_RTL8822C */
++
++#ifdef CONFIG_RTL8821C
++	#undef RTL8821C_SUPPORT
++	#define RTL8821C_SUPPORT				1
++	#ifndef CONFIG_FW_C2H_PKT
++		#define CONFIG_FW_C2H_PKT
++	#endif
++	#ifdef CONFIG_NO_FW
++		#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
++			#undef CONFIG_RTW_MAC_HIDDEN_RPT
++		#endif
++	#else
++		#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
++			#define CONFIG_RTW_MAC_HIDDEN_RPT
++		#endif
++	#endif
++	#define LOAD_FW_HEADER_FROM_DRIVER
++	#define CONFIG_PHY_CAPABILITY_QUERY
++	#ifdef CONFIG_CONCURRENT_MODE
++	#define CONFIG_AP_PORT_SWAP
++	#define CONFIG_FW_MULTI_PORT_SUPPORT
++	#endif
++	#define CONFIG_SUPPORT_FIFO_DUMP
++	#ifndef RTW_IQK_FW_OFFLOAD
++		#define RTW_IQK_FW_OFFLOAD
++	#endif /* RTW_IQK_FW_OFFLOAD */
++	/*#define CONFIG_AMPDU_PRETX_CD*/
++	/*#define DBG_PRE_TX_HANG*/
++
++	/* Beamforming related definition */
++	/* Only support new beamforming mechanism */
++	#ifdef CONFIG_BEAMFORMING
++		#define RTW_BEAMFORMING_VERSION_2
++	#endif /* CONFIG_BEAMFORMING */
++	#define CONFIG_HW_P0_TSF_SYNC
++	#define CONFIG_BCN_RECV_TIME
++	#ifdef CONFIG_P2P_PS
++		#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
++	#endif
++	#define CONFIG_RTS_FULL_BW
++
++	#ifdef CONFIG_LPS
++		/* #define CONFIG_LPS_ACK */	/* Supported after FW v25 */
++	#endif
++
++	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#endif
++#endif /*CONFIG_RTL8821C*/
++
++#ifdef CONFIG_RTL8710B
++	#undef RTL8710B_SUPPORT
++	#define RTL8710B_SUPPORT				1
++	#ifndef CONFIG_FW_C2H_PKT
++		#define CONFIG_FW_C2H_PKT
++	#endif
++	#define CONFIG_RTS_FULL_BW
++
++	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#endif
++#endif
++
++#ifdef CONFIG_RTL8814B
++	#undef RTL8814B_SUPPORT
++	#define RTL8814B_SUPPORT				1
++	#ifndef CONFIG_FW_C2H_PKT
++		#define CONFIG_FW_C2H_PKT
++	#endif /* CONFIG_FW_C2H_PKT */
++	#define RTW_TX_PA_BIAS	/* Adjust TX PA Bias from eFuse */
++	#define RTW_AMPDU_AGG_RETRY_AND_NEW
++
++	#ifdef CONFIG_WOWLAN
++		#define CONFIG_GTK_OL
++		/*#define CONFIG_ARP_KEEP_ALIVE*/
++
++		#ifdef CONFIG_GPIO_WAKEUP
++			#ifndef WAKEUP_GPIO_IDX
++				#define WAKEUP_GPIO_IDX	6	/* WIFI Chip Side */
++			#endif /* !WAKEUP_GPIO_IDX */
++		#endif /* CONFIG_GPIO_WAKEUP */
++	#endif /* CONFIG_WOWLAN */
++
++	#ifdef CONFIG_CONCURRENT_MODE
++		/*#define CONFIG_AP_PORT_SWAP*/
++		#define CONFIG_FW_MULTI_PORT_SUPPORT
++		#define CONFIG_SUPPORT_AP_PORT1
++	#endif /* CONFIG_CONCURRENT_MODE */
++
++	/*
++	 * Beamforming related definition
++	 */
++	/* Only support new beamforming mechanism */
++	#ifdef CONFIG_BEAMFORMING
++		#define RTW_BEAMFORMING_VERSION_2
++	#endif /* CONFIG_BEAMFORMING */
++
++	#ifndef DBG_RX_DFRAME_RAW_DATA
++		#define DBG_RX_DFRAME_RAW_DATA
++	#endif /* DBG_RX_DFRAME_RAW_DATA */
++
++	#ifndef RTW_IQK_FW_OFFLOAD
++		#define RTW_IQK_FW_OFFLOAD
++	#endif /* RTW_IQK_FW_OFFLOAD */
++
++	/* Checksum offload feature */
++	/*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/ /* not ready */
++	#define CONFIG_TCP_CSUM_OFFLOAD_RX
++
++	#define CONFIG_ADVANCE_OTA
++
++	#ifdef CONFIG_MCC_MODE
++		#define CONFIG_MCC_MODE_V2
++		#define CONFIG_MCC_PHYDM_OFFLOAD
++	#endif /* CONFIG_MCC_MODE */
++
++	#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
++		#define CONFIG_TDLS_CH_SW_V2
++	#endif
++
++	#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
++		#ifdef CONFIG_TDLS_CH_SW_V2
++			#define RTW_CHANNEL_SWITCH_OFFLOAD
++		#endif
++	#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
++
++	#if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW)
++		/* Supported since fw v22.1 */
++		#define RTW_PER_CMD_SUPPORT_FW
++	#endif /* RTW_PER_CMD_SUPPORT_FW */
++	#define CONFIG_SUPPORT_FIFO_DUMP
++	#define CONFIG_HW_P0_TSF_SYNC
++	#define CONFIG_BCN_RECV_TIME
++	#ifdef CONFIG_P2P_PS
++		#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
++	#endif
++	#define CONFIG_RTS_FULL_BW
++
++	#define CONFIG_PROTSEL_PORT
++	#define CONFIG_PROTSEL_ATIMDTIM
++	#define CONFIG_PROTSEL_MACSLEEP
++
++	#define CONFIG_HAS_HW_VAR_BCN_CTRL_ADDR
++	#define CONFIG_HAS_HW_VAR_BCN_FUNC
++	#define CONFIG_HAS_HW_VAR_MLME_DISCONNECT
++	#define CONFIG_HAS_HW_VAR_MLME_JOIN
++	#define CONFIG_HAS_HW_VAR_CORRECT_TSF
++	#define CONFIG_HAS_TX_BEACON_PAUSE
++
++	#define CONFIG_RTW_TX_NPATH_EN		/* 8814B is always 4TX */
++
++	#ifdef CONFIG_LPS
++		#define CONFIG_LPS_ACK	/* Supported after FW v04 */
++	#endif
++
++	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
++	#endif
++	#ifndef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
++	#define CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
++	#endif
++#endif /* CONFIG_RTL8814B */
++
++#endif /*__HAL_IC_CFG_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_intf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_intf.h
+new file mode 100755
+index 000000000..419e17481
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_intf.h
+@@ -0,0 +1,895 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL_INTF_H__
++#define __HAL_INTF_H__
++
++
++enum RTL871X_HCI_TYPE {
++	RTW_PCIE	= BIT0,
++	RTW_USB	= BIT1,
++	RTW_SDIO	= BIT2,
++	RTW_GSPI	= BIT3,
++};
++
++enum _CHIP_TYPE {
++
++	NULL_CHIP_TYPE,
++	RTL8188E,
++	RTL8192E,
++	RTL8812,
++	RTL8821, /* RTL8811 */
++	RTL8723B,
++	RTL8814A,
++	RTL8703B,
++	RTL8188F,
++	RTL8188GTV,
++	RTL8822B,
++	RTL8723D,
++	RTL8821C,
++	RTL8710B,
++	RTL8192F,
++	RTL8822C,
++	RTL8814B,
++	MAX_CHIP_TYPE
++};
++
++#ifdef RTW_HALMAC
++enum fw_mem {
++	FW_EMEM,
++	FW_IMEM,
++	FW_DMEM,
++};
++#endif
++
++extern const u32 _chip_type_to_odm_ic_type[];
++#define chip_type_to_odm_ic_type(chip_type) (((chip_type) >= MAX_CHIP_TYPE) ? _chip_type_to_odm_ic_type[MAX_CHIP_TYPE] : _chip_type_to_odm_ic_type[(chip_type)])
++
++typedef enum _HAL_HW_TIMER_TYPE {
++	HAL_TIMER_NONE = 0,
++	HAL_TIMER_TXBF = 1,
++	HAL_TIMER_EARLYMODE = 2,
++} HAL_HW_TIMER_TYPE, *PHAL_HW_TIMER_TYPE;
++
++
++typedef enum _HW_VARIABLES {
++	HW_VAR_MEDIA_STATUS,
++	HW_VAR_SET_OPMODE,
++	HW_VAR_MAC_ADDR,
++	HW_VAR_BSSID,
++	HW_VAR_INIT_RTS_RATE,
++	HW_VAR_BASIC_RATE,
++	HW_VAR_TXPAUSE,
++	HW_VAR_BCN_FUNC,
++	HW_VAR_BCN_CTRL_ADDR,
++	HW_VAR_CORRECT_TSF,
++	HW_VAR_RCR,
++	HW_VAR_MLME_DISCONNECT,
++	HW_VAR_MLME_SITESURVEY,
++	HW_VAR_MLME_JOIN,
++	HW_VAR_ON_RCR_AM,
++	HW_VAR_OFF_RCR_AM,
++	HW_VAR_BEACON_INTERVAL,
++	HW_VAR_SLOT_TIME,
++	HW_VAR_RESP_SIFS,
++	HW_VAR_ACK_PREAMBLE,
++	HW_VAR_SEC_CFG,
++	HW_VAR_SEC_DK_CFG,
++	HW_VAR_BCN_VALID,
++	HW_VAR_FREECNT,
++
++	/* PHYDM odm->SupportAbility */
++	HW_VAR_CAM_EMPTY_ENTRY,
++	HW_VAR_CAM_INVALID_ALL,
++	HW_VAR_AC_PARAM_VO,
++	HW_VAR_AC_PARAM_VI,
++	HW_VAR_AC_PARAM_BE,
++	HW_VAR_AC_PARAM_BK,
++	HW_VAR_ACM_CTRL,
++#ifdef CONFIG_WMMPS_STA
++	HW_VAR_UAPSD_TID,
++#endif /* CONFIG_WMMPS_STA */
++	HW_VAR_AMPDU_MIN_SPACE,
++#ifdef CONFIG_80211N_HT
++	HW_VAR_AMPDU_FACTOR,
++#endif /* CONFIG_80211N_HT */
++	HW_VAR_RXDMA_AGG_PG_TH,
++	HW_VAR_SET_RPWM,
++	HW_VAR_CPWM,
++	HW_VAR_H2C_FW_PWRMODE,
++	HW_VAR_H2C_FW_PWRMODE_RFON_CTRL,
++	HW_VAR_H2C_INACTIVE_IPS,
++	HW_VAR_H2C_PS_TUNE_PARAM,
++	HW_VAR_H2C_FW_JOINBSSRPT,
++	HW_VAR_FWLPS_RF_ON,
++	HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
++#ifdef CONFIG_LPS_POFF
++	HW_VAR_LPS_POFF_INIT,
++	HW_VAR_LPS_POFF_DEINIT,
++	HW_VAR_LPS_POFF_SET_MODE,
++	HW_VAR_LPS_POFF_WOW_EN,
++#endif
++#ifdef CONFIG_LPS_PG
++	HW_VAR_LPS_PG_HANDLE,
++#endif
++	HW_VAR_TRIGGER_GPIO_0,
++	HW_VAR_BT_SET_COEXIST,
++	HW_VAR_BT_ISSUE_DELBA,
++	HW_VAR_SWITCH_EPHY_WoWLAN,
++	HW_VAR_EFUSE_USAGE,
++	HW_VAR_EFUSE_BYTES,
++	HW_VAR_EFUSE_BT_USAGE,
++	HW_VAR_EFUSE_BT_BYTES,
++	HW_VAR_FIFO_CLEARN_UP,
++	HW_VAR_RESTORE_HW_SEQ,
++	HW_VAR_CHECK_TXBUF,
++	HW_VAR_PCIE_STOP_TX_DMA,
++	HW_VAR_APFM_ON_MAC, /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
++	HW_VAR_HCI_SUS_STATE,
++	/* The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. */
++	/* Unit in microsecond. 0 means disable this function. */
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++	HW_VAR_WOWLAN,
++	HW_VAR_WAKEUP_REASON,
++#endif
++	HW_VAR_RPWM_TOG,
++#ifdef CONFIG_GPIO_WAKEUP
++	HW_VAR_WOW_OUTPUT_GPIO,
++	HW_VAR_WOW_INPUT_GPIO,
++	HW_SET_GPIO_WL_CTRL,
++#endif
++	HW_VAR_SYS_CLKR,
++	HW_VAR_NAV_UPPER,
++	HW_VAR_RPT_TIMER_SETTING,
++	HW_VAR_TX_RPT_MAX_MACID,
++	HW_VAR_CHK_HI_QUEUE_EMPTY,
++	HW_VAR_CHK_MGQ_CPU_EMPTY,
++	HW_VAR_DL_BCN_SEL,
++	HW_VAR_AMPDU_MAX_TIME,
++	HW_VAR_WIRELESS_MODE,
++	HW_VAR_USB_MODE,
++	HW_VAR_PORT_SWITCH,
++	HW_VAR_PORT_CFG,
++	HW_VAR_DO_IQK,
++	HW_VAR_DM_IN_LPS_LCLK,/*flag CONFIG_LPS_LCLK_WD_TIMER*/
++	HW_VAR_SET_REQ_FW_PS,
++	HW_VAR_FW_PS_STATE,
++	HW_VAR_SOUNDING_ENTER,
++	HW_VAR_SOUNDING_LEAVE,
++	HW_VAR_SOUNDING_RATE,
++	HW_VAR_SOUNDING_STATUS,
++	HW_VAR_SOUNDING_FW_NDPA,
++	HW_VAR_SOUNDING_CLK,
++	HW_VAR_SOUNDING_SET_GID_TABLE,
++	HW_VAR_SOUNDING_CSI_REPORT,
++	/*Add by YuChen for TXBF HW timer*/
++	HW_VAR_HW_REG_TIMER_INIT,
++	HW_VAR_HW_REG_TIMER_RESTART,
++	HW_VAR_HW_REG_TIMER_START,
++	HW_VAR_HW_REG_TIMER_STOP,
++	/*Add by YuChen for TXBF HW timer*/
++	HW_VAR_DL_RSVD_PAGE,
++	HW_VAR_MACID_LINK,
++	HW_VAR_MACID_NOLINK,
++	HW_VAR_DUMP_MAC_QUEUE_INFO,
++	HW_VAR_ASIX_IOT,
++#ifdef CONFIG_MBSSID_CAM
++	HW_VAR_MBSSID_CAM_WRITE,
++	HW_VAR_MBSSID_CAM_CLEAR,
++	HW_VAR_RCR_MBSSID_EN,
++#endif
++	HW_VAR_EN_HW_UPDATE_TSF,
++	HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO,
++	HW_VAR_CH_SW_IQK_INFO_BACKUP,
++	HW_VAR_CH_SW_IQK_INFO_RESTORE,
++
++	HW_VAR_DBI,
++	HW_VAR_MDIO,
++	HW_VAR_L1OFF_CAPABILITY,
++	HW_VAR_L1OFF_NIC_SUPPORT,
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_TDLS_CH_SW
++	HW_VAR_TDLS_BCN_EARLY_C2H_RPT,
++#endif
++#endif
++	HW_VAR_DUMP_MAC_TXFIFO,
++	HW_VAR_PWR_CMD,
++#ifdef CONFIG_FW_HANDLE_TXBCN
++	HW_VAR_BCN_HEAD_SEL,
++#endif
++	HW_VAR_SET_SOML_PARAM,
++	HW_VAR_ENABLE_RX_BAR,
++	HW_VAR_TSF_AUTO_SYNC,
++	HW_VAR_LPS_STATE_CHK,
++	HW_VAR_LPS_RFON_CHK,
++	#ifdef CONFIG_RTS_FULL_BW
++	HW_VAR_SET_RTS_BW,
++	#endif
++#if defined(CONFIG_PCI_HCI)
++	HW_VAR_ENSWBCN,
++#endif
++#ifdef CONFIG_WOWLAN
++	HW_VAR_VENDOR_WOW_MODE,
++#endif /* CONFIG_WOWLAN */
++} HW_VARIABLES;
++
++typedef enum _HAL_DEF_VARIABLE {
++	HAL_DEF_UNDERCORATEDSMOOTHEDPWDB,
++	HAL_DEF_IS_SUPPORT_ANT_DIV,
++	HAL_DEF_DRVINFO_SZ,
++	HAL_DEF_MAX_RECVBUF_SZ,
++	HAL_DEF_RX_PACKET_OFFSET,
++	HAL_DEF_RX_DMA_SZ_WOW,
++	HAL_DEF_RX_DMA_SZ,
++	HAL_DEF_RX_PAGE_SIZE,
++	HAL_DEF_DBG_DUMP_RXPKT,/* for dbg */
++	HAL_DEF_RA_DECISION_RATE,
++	HAL_DEF_RA_SGI,
++	HAL_DEF_PT_PWR_STATUS,
++	HAL_DEF_TX_LDPC,				/* LDPC support */
++	HAL_DEF_RX_LDPC,				/* LDPC support */
++	HAL_DEF_TX_STBC,				/* TX STBC support */
++	HAL_DEF_RX_STBC,				/* RX STBC support */
++	HAL_DEF_EXPLICIT_BEAMFORMER,/* Explicit  Compressed Steering Capable */
++	HAL_DEF_EXPLICIT_BEAMFORMEE,/* Explicit Compressed Beamforming Feedback Capable */
++	HAL_DEF_VHT_MU_BEAMFORMER,	/* VHT MU Beamformer support */
++	HAL_DEF_VHT_MU_BEAMFORMEE,	/* VHT MU Beamformee support */
++	HAL_DEF_BEAMFORMER_CAP,
++	HAL_DEF_BEAMFORMEE_CAP,
++	HW_VAR_MAX_RX_AMPDU_FACTOR,
++	HW_DEF_RA_INFO_DUMP,
++	HAL_DEF_DBG_DUMP_TXPKT,
++
++	HAL_DEF_TX_PAGE_SIZE,
++	HAL_DEF_TX_PAGE_BOUNDARY,
++	HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN,
++	HAL_DEF_TX_BUFFER_LAST_ENTRY,
++	HAL_DEF_ANT_DETECT,/* to do for 8723a */
++	HAL_DEF_PCI_ASPM_OSC, /* Support for ASPM OSC, added by Roger, 2013.03.27. */
++	HAL_DEF_EFUSE_USAGE,	/* Get current EFUSE utilization. 2008.12.19. Added by Roger. */
++	HAL_DEF_EFUSE_BYTES,
++	HW_VAR_BEST_AMPDU_DENSITY,
++} HAL_DEF_VARIABLE;
++
++typedef enum _HAL_ODM_VARIABLE {
++	HAL_ODM_STA_INFO,
++	HAL_ODM_P2P_STATE,
++	HAL_ODM_WIFI_DISPLAY_STATE,
++	HAL_ODM_REGULATION,
++	HAL_ODM_INITIAL_GAIN,
++	HAL_ODM_RX_INFO_DUMP,
++	HAL_ODM_RX_Dframe_INFO,
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	HAL_ODM_ANTDIV_SELECT
++#endif
++} HAL_ODM_VARIABLE;
++
++typedef enum _HAL_INTF_PS_FUNC {
++	HAL_USB_SELECT_SUSPEND,
++	HAL_MAX_ID,
++} HAL_INTF_PS_FUNC;
++
++typedef s32(*c2h_id_filter)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
++
++struct txpwr_idx_comp;
++
++struct hal_ops {
++	/*** initialize section ***/
++	void	(*read_chip_version)(_adapter *padapter);
++	void	(*init_default_value)(_adapter *padapter);
++	void	(*intf_chip_configure)(_adapter *padapter);
++	u8	(*read_adapter_info)(_adapter *padapter);
++	u32(*hal_power_on)(_adapter *padapter);
++	void	(*hal_power_off)(_adapter *padapter);
++	u32(*hal_init)(_adapter *padapter);
++	u32(*hal_deinit)(_adapter *padapter);
++	void	(*dm_init)(_adapter *padapter);
++	void	(*dm_deinit)(_adapter *padapter);
++
++	/*** xmit section ***/
++	s32(*init_xmit_priv)(_adapter *padapter);
++	void	(*free_xmit_priv)(_adapter *padapter);
++	s32(*hal_xmit)(_adapter *padapter, struct xmit_frame *pxmitframe);
++	/*
++	 * mgnt_xmit should be implemented to run in interrupt context
++	 */
++	s32(*mgnt_xmit)(_adapter *padapter, struct xmit_frame *pmgntframe);
++	s32(*hal_xmitframe_enqueue)(_adapter *padapter, struct xmit_frame *pxmitframe);
++#ifdef CONFIG_XMIT_THREAD_MODE
++	s32(*xmit_thread_handler)(_adapter *padapter);
++#endif
++	void	(*run_thread)(_adapter *padapter);
++	void	(*cancel_thread)(_adapter *padapter);
++
++	/*** recv section ***/
++	s32(*init_recv_priv)(_adapter *padapter);
++	void	(*free_recv_priv)(_adapter *padapter);
++#ifdef CONFIG_RECV_THREAD_MODE
++	s32 (*recv_hdl)(_adapter *adapter);
++#endif
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
++	u32(*inirp_init)(_adapter *padapter);
++	u32(*inirp_deinit)(_adapter *padapter);
++#endif
++	/*** interrupt hdl section ***/
++	void	(*enable_interrupt)(_adapter *padapter);
++	void	(*disable_interrupt)(_adapter *padapter);
++	u8(*check_ips_status)(_adapter *padapter);
++#if defined(CONFIG_PCI_HCI)
++	s32(*interrupt_handler)(_adapter *padapter);
++	void (*unmap_beacon_icf)(_adapter *padapter);
++#endif
++
++#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
++	void	(*interrupt_handler)(_adapter *padapter, u16 pkt_len, u8 *pbuf);
++#endif
++
++#if defined(CONFIG_PCI_HCI)
++	void	(*irp_reset)(_adapter *padapter);
++#endif
++
++	/*** DM section ***/
++#ifdef CONFIG_RTW_SW_LED
++	void	(*InitSwLeds)(_adapter *padapter);
++	void	(*DeInitSwLeds)(_adapter *padapter);
++#endif
++	void	(*set_chnl_bw_handler)(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80);
++
++	void (*set_tx_power_level_handler)(_adapter *adapter, u8 channel);
++	void (*set_txpwr_done)(_adapter *adapter);
++	void (*set_tx_power_index_handler)(_adapter *adapter, u32 powerindex, enum rf_path rfpath, u8 rate);
++
++	u8 (*get_tx_power_index_handler)(_adapter *adapter, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate
++		, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch, struct txpwr_idx_comp *tic);
++	s8 (*get_txpwr_target_extra_bias)(_adapter *adapter, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch);
++
++	void	(*hal_dm_watchdog)(_adapter *padapter);
++
++	u8	(*set_hw_reg_handler)(_adapter *padapter, u8	variable, u8 *val);
++
++	void	(*GetHwRegHandler)(_adapter *padapter, u8	variable, u8 *val);
++
++
++
++	u8 (*get_hal_def_var_handler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
++
++	u8(*SetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
++
++	void	(*GetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2);
++	void	(*SetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet);
++
++	void	(*SetBeaconRelatedRegistersHandler)(_adapter *padapter);
++
++	u8(*interface_ps_func)(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);
++
++	u32(*read_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask);
++	void	(*write_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
++	u32 (*read_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask);
++	void	(*write_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
++#ifdef CONFIG_SYSON_INDIRECT_ACCESS
++	u32 (*read_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask);
++	void (*write_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
++#endif
++	void (*read_wmmedca_reg)(_adapter *padapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params);
++	
++#ifdef CONFIG_HOSTAPD_MLME
++	s32(*hostap_mgnt_xmit_entry)(_adapter *padapter, _pkt *pkt);
++#endif
++
++	void (*EfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState);
++	void (*BTEfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState);
++	void (*ReadEFuse)(_adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, BOOLEAN bPseudoTest);
++	void (*EFUSEGetEfuseDefinition)(_adapter *padapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest);
++	u16(*EfuseGetCurrentSize)(_adapter *padapter, u8 efuseType, BOOLEAN bPseudoTest);
++	int	(*Efuse_PgPacketRead)(_adapter *padapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
++	int	(*Efuse_PgPacketWrite)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
++	u8(*Efuse_WordEnableDataWrite)(_adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
++	BOOLEAN(*Efuse_PgPacketWrite_BT)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
++#if defined(CONFIG_RTL8710B)
++	BOOLEAN(*efuse_indirect_read4)(_adapter *padapter, u16 regaddr, u8 *value);
++#endif
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++	void (*sreset_init_value)(_adapter *padapter);
++	void (*sreset_reset_value)(_adapter *padapter);
++	void (*silentreset)(_adapter *padapter);
++	void (*sreset_xmit_status_check)(_adapter *padapter);
++	void (*sreset_linked_status_check)(_adapter *padapter);
++	u8(*sreset_get_wifi_status)(_adapter *padapter);
++	bool (*sreset_inprogress)(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_IOL
++	int (*IOL_exec_cmds_sync)(_adapter *padapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
++#endif
++
++	void (*hal_notch_filter)(_adapter *adapter, bool enable);
++#ifdef RTW_HALMAC
++	void (*hal_mac_c2h_handler)(_adapter *adapter, u8 *pbuf, u16 length);
++#else
++	s32(*c2h_handler)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
++#endif
++	void (*reqtxrpt)(_adapter *padapter, u8 macid);
++	s32(*fill_h2c_cmd)(PADAPTER, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
++	void (*fill_fake_txdesc)(PADAPTER, u8 *pDesc, u32 BufferLen,
++				 u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
++	s32(*fw_dl)(_adapter *adapter, u8 wowlan);
++#ifdef RTW_HALMAC
++	s32 (*fw_mem_dl)(_adapter *adapter, enum fw_mem mem);
++#endif
++
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_PCI_HCI)
++	void (*clear_interrupt)(_adapter *padapter);
++#endif
++	u8(*hal_get_tx_buff_rsvd_page_num)(_adapter *adapter, bool wowlan);
++#ifdef CONFIG_GPIO_API
++	void (*update_hisr_hsisr_ind)(PADAPTER padapter, u32 flag);
++	int (*hal_gpio_func_check)(_adapter *padapter, u8 gpio_num);
++	void (*hal_gpio_multi_func_reset)(_adapter *padapter, u8 gpio_num);
++#endif
++#ifdef CONFIG_FW_CORRECT_BCN
++	void (*fw_correct_bcn)(PADAPTER padapter);
++#endif
++
++#ifdef RTW_HALMAC
++	u8(*init_mac_register)(PADAPTER);
++	u8(*init_phy)(PADAPTER);
++#endif /* RTW_HALMAC */
++
++#ifdef CONFIG_PCI_HCI
++	void (*hal_set_l1ssbackdoor_handler)(_adapter *padapter, u8 enable);
++#endif
++
++#ifdef CONFIG_RFKILL_POLL
++	bool (*hal_radio_onoff_check)(_adapter *adapter, u8 *valid);
++#endif
++#ifdef CONFIG_PCI_TX_POLLING
++	void (*tx_poll_handler)(_adapter *adapter);
++#endif
++};
++
++typedef	enum _RT_EEPROM_TYPE {
++	EEPROM_93C46,
++	EEPROM_93C56,
++	EEPROM_BOOT_EFUSE,
++} RT_EEPROM_TYPE, *PRT_EEPROM_TYPE;
++
++
++
++#define RF_CHANGE_BY_INIT	0
++#define RF_CHANGE_BY_IPS	BIT28
++#define RF_CHANGE_BY_PS	BIT29
++#define RF_CHANGE_BY_HW	BIT30
++#define RF_CHANGE_BY_SW	BIT31
++
++typedef enum _HARDWARE_TYPE {
++	HARDWARE_TYPE_RTL8188EE,
++	HARDWARE_TYPE_RTL8188EU,
++	HARDWARE_TYPE_RTL8188ES,
++	/*	NEW_GENERATION_IC */
++	HARDWARE_TYPE_RTL8192EE,
++	HARDWARE_TYPE_RTL8192EU,
++	HARDWARE_TYPE_RTL8192ES,
++	HARDWARE_TYPE_RTL8812E,
++	HARDWARE_TYPE_RTL8812AU,
++	HARDWARE_TYPE_RTL8811AU,
++	HARDWARE_TYPE_RTL8821E,
++	HARDWARE_TYPE_RTL8821U,
++	HARDWARE_TYPE_RTL8821S,
++	HARDWARE_TYPE_RTL8723BE,
++	HARDWARE_TYPE_RTL8723BU,
++	HARDWARE_TYPE_RTL8723BS,
++	HARDWARE_TYPE_RTL8814AE,
++	HARDWARE_TYPE_RTL8814AU,
++	HARDWARE_TYPE_RTL8814AS,
++	HARDWARE_TYPE_RTL8821BE,
++	HARDWARE_TYPE_RTL8821BU,
++	HARDWARE_TYPE_RTL8821BS,
++	HARDWARE_TYPE_RTL8822BE,
++	HARDWARE_TYPE_RTL8822BU,
++	HARDWARE_TYPE_RTL8822BS,
++	HARDWARE_TYPE_RTL8703BE,
++	HARDWARE_TYPE_RTL8703BU,
++	HARDWARE_TYPE_RTL8703BS,
++	HARDWARE_TYPE_RTL8188FE,
++	HARDWARE_TYPE_RTL8188FU,
++	HARDWARE_TYPE_RTL8188FS,
++	HARDWARE_TYPE_RTL8188GTVU,
++	HARDWARE_TYPE_RTL8188GTVS,
++	HARDWARE_TYPE_RTL8723DE,
++	HARDWARE_TYPE_RTL8723DU,
++	HARDWARE_TYPE_RTL8723DS,
++	HARDWARE_TYPE_RTL8821CE,
++	HARDWARE_TYPE_RTL8821CU,
++	HARDWARE_TYPE_RTL8821CS,
++	HARDWARE_TYPE_RTL8710BU,
++	HARDWARE_TYPE_RTL8192FS,
++	HARDWARE_TYPE_RTL8192FU,
++	HARDWARE_TYPE_RTL8192FE,
++	HARDWARE_TYPE_RTL8822CE,
++	HARDWARE_TYPE_RTL8822CU,
++	HARDWARE_TYPE_RTL8822CS,
++	HARDWARE_TYPE_RTL8814BE,
++	HARDWARE_TYPE_RTL8814BU,
++	HARDWARE_TYPE_RTL8814BS,
++	HARDWARE_TYPE_MAX,
++} HARDWARE_TYPE;
++
++#define IS_NEW_GENERATION_IC(_Adapter)	(rtw_get_hw_type(_Adapter) >= HARDWARE_TYPE_RTL8192EE)
++/*
++ * RTL8188E Series
++ *   */
++#define IS_HARDWARE_TYPE_8188EE(_Adapter)	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EE)
++#define IS_HARDWARE_TYPE_8188EU(_Adapter)	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EU)
++#define IS_HARDWARE_TYPE_8188ES(_Adapter)	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188ES)
++#define	IS_HARDWARE_TYPE_8188E(_Adapter)	\
++	(IS_HARDWARE_TYPE_8188EE(_Adapter) || IS_HARDWARE_TYPE_8188EU(_Adapter) || IS_HARDWARE_TYPE_8188ES(_Adapter))
++
++/* RTL8812 Series */
++#define IS_HARDWARE_TYPE_8812E(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812E)
++#define IS_HARDWARE_TYPE_8812AU(_Adapter)	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812AU)
++#define IS_HARDWARE_TYPE_8812(_Adapter)			\
++	(IS_HARDWARE_TYPE_8812E(_Adapter) || IS_HARDWARE_TYPE_8812AU(_Adapter))
++
++/* RTL8821 Series */
++#define IS_HARDWARE_TYPE_8821E(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821E)
++#define IS_HARDWARE_TYPE_8811AU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU)
++#define IS_HARDWARE_TYPE_8821U(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821U || \
++		rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU)
++#define IS_HARDWARE_TYPE_8821S(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821S)
++#define IS_HARDWARE_TYPE_8821(_Adapter)			\
++	(IS_HARDWARE_TYPE_8821E(_Adapter) || IS_HARDWARE_TYPE_8821U(_Adapter) || IS_HARDWARE_TYPE_8821S(_Adapter))
++
++#define IS_HARDWARE_TYPE_JAGUAR(_Adapter)		\
++	(IS_HARDWARE_TYPE_8812(_Adapter) || IS_HARDWARE_TYPE_8821(_Adapter))
++
++/* RTL8192E Series */
++#define IS_HARDWARE_TYPE_8192EE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EE)
++#define IS_HARDWARE_TYPE_8192EU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EU)
++#define IS_HARDWARE_TYPE_8192ES(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192ES)
++
++#define IS_HARDWARE_TYPE_8192E(_Adapter)		\
++	(IS_HARDWARE_TYPE_8192EE(_Adapter) || IS_HARDWARE_TYPE_8192EU(_Adapter) || IS_HARDWARE_TYPE_8192ES(_Adapter))
++
++#define IS_HARDWARE_TYPE_8723BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BE)
++#define IS_HARDWARE_TYPE_8723BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BU)
++#define IS_HARDWARE_TYPE_8723BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BS)
++
++#define IS_HARDWARE_TYPE_8723B(_Adapter) \
++	(IS_HARDWARE_TYPE_8723BE(_Adapter) || IS_HARDWARE_TYPE_8723BU(_Adapter) || IS_HARDWARE_TYPE_8723BS(_Adapter))
++
++/* RTL8814A Series */
++#define IS_HARDWARE_TYPE_8814AE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AE)
++#define IS_HARDWARE_TYPE_8814AU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AU)
++#define IS_HARDWARE_TYPE_8814AS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AS)
++
++#define IS_HARDWARE_TYPE_8814A(_Adapter)		\
++	(IS_HARDWARE_TYPE_8814AE(_Adapter) || IS_HARDWARE_TYPE_8814AU(_Adapter) || IS_HARDWARE_TYPE_8814AS(_Adapter))
++
++/* RTL8703B Series */
++#define IS_HARDWARE_TYPE_8703BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BE)
++#define IS_HARDWARE_TYPE_8703BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BS)
++#define IS_HARDWARE_TYPE_8703BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BU)
++#define	IS_HARDWARE_TYPE_8703B(_Adapter)			\
++	(IS_HARDWARE_TYPE_8703BE(_Adapter) || IS_HARDWARE_TYPE_8703BU(_Adapter) || IS_HARDWARE_TYPE_8703BS(_Adapter))
++
++/* RTL8723D Series */
++#define IS_HARDWARE_TYPE_8723DE(_Adapter)\
++	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DE)
++#define IS_HARDWARE_TYPE_8723DS(_Adapter)\
++	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DS)
++#define IS_HARDWARE_TYPE_8723DU(_Adapter)\
++	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DU)
++#define	IS_HARDWARE_TYPE_8723D(_Adapter)\
++	(IS_HARDWARE_TYPE_8723DE(_Adapter) || \
++	 IS_HARDWARE_TYPE_8723DU(_Adapter) || \
++	 IS_HARDWARE_TYPE_8723DS(_Adapter))
++
++/* RTL8192F Series */
++#define IS_HARDWARE_TYPE_8192FS(_Adapter)\
++	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FS)
++#define IS_HARDWARE_TYPE_8192FU(_Adapter)\
++	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FU)	
++#define IS_HARDWARE_TYPE_8192FE(_Adapter)\
++	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FE)	
++#define	IS_HARDWARE_TYPE_8192F(_Adapter)\
++	(IS_HARDWARE_TYPE_8192FS(_Adapter) ||\
++	 IS_HARDWARE_TYPE_8192FU(_Adapter) ||\
++	 IS_HARDWARE_TYPE_8192FE(_Adapter))
++
++/* RTL8188F Series */
++#define IS_HARDWARE_TYPE_8188FE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FE)
++#define IS_HARDWARE_TYPE_8188FS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FS)
++#define IS_HARDWARE_TYPE_8188FU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FU)
++#define	IS_HARDWARE_TYPE_8188F(_Adapter)			\
++	(IS_HARDWARE_TYPE_8188FE(_Adapter) || IS_HARDWARE_TYPE_8188FU(_Adapter) || IS_HARDWARE_TYPE_8188FS(_Adapter))
++
++#define IS_HARDWARE_TYPE_8188GTVU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVU)
++#define IS_HARDWARE_TYPE_8188GTVS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVS)
++#define	IS_HARDWARE_TYPE_8188GTV(_Adapter)			\
++	(IS_HARDWARE_TYPE_8188GTVU(_Adapter) || IS_HARDWARE_TYPE_8188GTVS(_Adapter))
++
++/* RTL8710B Series */
++#define IS_HARDWARE_TYPE_8710BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8710BU)
++#define IS_HARDWARE_TYPE_8710B(_Adapter) (IS_HARDWARE_TYPE_8710BU(_Adapter))
++
++#define IS_HARDWARE_TYPE_8821BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BE)
++#define IS_HARDWARE_TYPE_8821BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BU)
++#define IS_HARDWARE_TYPE_8821BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BS)
++
++#define IS_HARDWARE_TYPE_8821B(_Adapter)		\
++	(IS_HARDWARE_TYPE_8821BE(_Adapter) || IS_HARDWARE_TYPE_8821BU(_Adapter) || IS_HARDWARE_TYPE_8821BS(_Adapter))
++
++#define IS_HARDWARE_TYPE_8822BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BE)
++#define IS_HARDWARE_TYPE_8822BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BU)
++#define IS_HARDWARE_TYPE_8822BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BS)
++#define IS_HARDWARE_TYPE_8822B(_Adapter)		\
++	(IS_HARDWARE_TYPE_8822BE(_Adapter) || IS_HARDWARE_TYPE_8822BU(_Adapter) || IS_HARDWARE_TYPE_8822BS(_Adapter))
++
++#define IS_HARDWARE_TYPE_8821CE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CE)
++#define IS_HARDWARE_TYPE_8821CU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CU)
++#define IS_HARDWARE_TYPE_8821CS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CS)
++#define IS_HARDWARE_TYPE_8821C(_Adapter)		\
++	(IS_HARDWARE_TYPE_8821CE(_Adapter) || IS_HARDWARE_TYPE_8821CU(_Adapter) || IS_HARDWARE_TYPE_8821CS(_Adapter))
++
++#define IS_HARDWARE_TYPE_8822CE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CE)
++#define IS_HARDWARE_TYPE_8822CU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CU)
++#define IS_HARDWARE_TYPE_8822CS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CS)
++#define IS_HARDWARE_TYPE_8822C(_Adapter)		\
++	(IS_HARDWARE_TYPE_8822CE(_Adapter) || IS_HARDWARE_TYPE_8822CU(_Adapter) || IS_HARDWARE_TYPE_8822CS(_Adapter))
++
++#define IS_HARDWARE_TYPE_8814BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BE)
++#define IS_HARDWARE_TYPE_8814BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BU)
++#define IS_HARDWARE_TYPE_8814BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BS)
++#define IS_HARDWARE_TYPE_8814B(_Adapter)		\
++		(IS_HARDWARE_TYPE_8814BE(_Adapter) || IS_HARDWARE_TYPE_8814BU(_Adapter) || IS_HARDWARE_TYPE_8814BS(_Adapter))
++
++#define IS_HARDWARE_TYPE_JAGUAR2(_Adapter)		\
++	(IS_HARDWARE_TYPE_8814A(_Adapter) || IS_HARDWARE_TYPE_8821B(_Adapter) || IS_HARDWARE_TYPE_8822B(_Adapter) || IS_HARDWARE_TYPE_8821C(_Adapter))
++
++#define IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter)		\
++	(IS_HARDWARE_TYPE_JAGUAR(_Adapter) || IS_HARDWARE_TYPE_JAGUAR2(_Adapter))
++
++#define IS_HARDWARE_TYPE_JAGUAR3(_Adapter)		\
++	(IS_HARDWARE_TYPE_8814B(_Adapter) || IS_HARDWARE_TYPE_8822C(_Adapter))
++
++#define IS_HARDWARE_TYPE_JAGUAR_ALL(_Adapter)		\
++	(IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter) || IS_HARDWARE_TYPE_JAGUAR3(_Adapter))
++
++
++typedef enum _wowlan_subcode {
++	WOWLAN_ENABLE			= 0,
++	WOWLAN_DISABLE			= 1,
++	WOWLAN_AP_ENABLE		= 2,
++	WOWLAN_AP_DISABLE		= 3,
++	WOWLAN_PATTERN_CLEAN		= 4
++} wowlan_subcode;
++
++struct wowlan_ioctl_param {
++	unsigned int subcode;
++	unsigned int subcode_value;
++	unsigned int wakeup_reason;
++};
++
++u8 rtw_hal_data_init(_adapter *padapter);
++void rtw_hal_data_deinit(_adapter *padapter);
++
++void rtw_hal_def_value_init(_adapter *padapter);
++
++void	rtw_hal_free_data(_adapter *padapter);
++
++void rtw_hal_dm_init(_adapter *padapter);
++void rtw_hal_dm_deinit(_adapter *padapter);
++#ifdef CONFIG_RTW_SW_LED
++void rtw_hal_sw_led_init(_adapter *padapter);
++void rtw_hal_sw_led_deinit(_adapter *padapter);
++#endif
++u32 rtw_hal_power_on(_adapter *padapter);
++void rtw_hal_power_off(_adapter *padapter);
++
++uint rtw_hal_init(_adapter *padapter);
++#ifdef CONFIG_NEW_NETDEV_HDL
++uint rtw_hal_iface_init(_adapter *adapter);
++#endif
++
++enum rf_type rtw_chip_rftype_to_hal_rftype(_adapter *adapter, u8 limit);
++void dump_hal_runtime_trx_mode(void *sel, _adapter *adapter);
++void dump_hal_trx_mode(void *sel, _adapter *adapter);
++u8 rtw_hal_rfpath_init(_adapter *adapter);
++u8 rtw_hal_trxnss_init(_adapter *adapter);
++
++uint rtw_hal_deinit(_adapter *padapter);
++void rtw_hal_stop(_adapter *padapter);
++u8 rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val);
++void rtw_hal_get_hwreg(PADAPTER padapter, u8 variable, u8 *val);
++
++void rtw_hal_chip_configure(_adapter *padapter);
++u8 rtw_hal_read_chip_info(_adapter *padapter);
++void rtw_hal_read_chip_version(_adapter *padapter);
++
++u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
++u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
++
++void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet);
++void	rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2);
++
++void rtw_hal_enable_interrupt(_adapter *padapter);
++void rtw_hal_disable_interrupt(_adapter *padapter);
++
++u8 rtw_hal_check_ips_status(_adapter *padapter);
++
++#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
++	u32	rtw_hal_inirp_init(_adapter *padapter);
++	u32	rtw_hal_inirp_deinit(_adapter *padapter);
++#endif
++
++#if defined(CONFIG_PCI_HCI)
++	void	rtw_hal_irp_reset(_adapter *padapter);
++void	rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data);
++u8	rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr);
++void	rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data);
++u16	rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr);
++u8	rtw_hal_pci_l1off_nic_support(_adapter *padapter);
++u8	rtw_hal_pci_l1off_capability(_adapter *padapter);
++#endif
++
++u8	rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);
++
++s32	rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++s32	rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
++s32	rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
++
++s32	rtw_hal_init_xmit_priv(_adapter *padapter);
++void	rtw_hal_free_xmit_priv(_adapter *padapter);
++
++s32	rtw_hal_init_recv_priv(_adapter *padapter);
++void	rtw_hal_free_recv_priv(_adapter *padapter);
++
++void rtw_hal_update_ra_mask(struct sta_info *psta);
++
++void	rtw_hal_start_thread(_adapter *padapter);
++void	rtw_hal_stop_thread(_adapter *padapter);
++
++void rtw_hal_bcn_related_reg_setting(_adapter *padapter);
++
++u32	rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask);
++void	rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
++u32	rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask);
++void	rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
++
++
++#define phy_query_bb_reg(Adapter, RegAddr, BitMask) rtw_hal_read_bbreg((Adapter), (RegAddr), (BitMask))
++#define phy_set_bb_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_bbreg((Adapter), (RegAddr), (BitMask), (Data))
++#define phy_query_rf_reg(Adapter, eRFPath, RegAddr, BitMask) rtw_hal_read_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask))
++#define phy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data) rtw_hal_write_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
++
++#ifdef CONFIG_SYSON_INDIRECT_ACCESS
++u32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask);
++void rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
++#define hal_query_syson_reg(Adapter, RegAddr, BitMask) rtw_hal_read_syson_reg((Adapter), (RegAddr), (BitMask))
++#define hal_set_syson_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_syson_reg((Adapter), (RegAddr), (BitMask), (Data))
++#endif
++
++#define phy_set_mac_reg	phy_set_bb_reg
++#define phy_query_mac_reg phy_query_bb_reg
++
++#if defined(CONFIG_PCI_HCI)
++	s32	rtw_hal_interrupt_handler(_adapter *padapter);
++	void	rtw_hal_unmap_beacon_icf(_adapter *padapter);
++#endif
++#if  defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
++	void	rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf);
++#endif
++
++void	rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80);
++void	rtw_hal_dm_watchdog(_adapter *padapter);
++void	rtw_hal_dm_watchdog_in_lps(_adapter *padapter);
++
++#ifdef CONFIG_HOSTAPD_MLME
++	s32	rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
++#endif
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++void rtw_hal_sreset_init(_adapter *padapter);
++void rtw_hal_sreset_reset(_adapter *padapter);
++void rtw_hal_sreset_reset_value(_adapter *padapter);
++void rtw_hal_sreset_xmit_status_check(_adapter *padapter);
++void rtw_hal_sreset_linked_status_check(_adapter *padapter);
++u8   rtw_hal_sreset_get_wifi_status(_adapter *padapter);
++bool rtw_hal_sreset_inprogress(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_IOL
++int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
++#endif
++
++#ifdef CONFIG_XMIT_THREAD_MODE
++s32 rtw_hal_xmit_thread_handler(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_RECV_THREAD_MODE
++s32 rtw_hal_recv_hdl(_adapter *adapter);
++#endif
++
++void rtw_hal_notch_filter(_adapter *adapter, bool enable);
++
++#ifdef CONFIG_FW_C2H_REG
++bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload);
++bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf);
++s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf);
++#endif
++
++#ifdef CONFIG_FW_C2H_PKT
++bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload);
++#endif
++
++s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
++#ifndef RTW_HALMAC
++s32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
++s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
++#endif
++
++s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter);
++
++s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid);
++s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid);
++s32 rtw_hal_macid_sleep_all_used(_adapter *adapter);
++s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter);
++s32 rtw_hal_macid_drop(_adapter *adapter, u8 macid);
++s32 rtw_hal_macid_undrop(_adapter *adapter, u8 macid);
++
++s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
++void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen,
++			      u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
++u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan);
++
++#ifdef CONFIG_GPIO_API
++void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag);
++int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num);
++void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num);
++#endif
++#ifdef CONFIG_FW_CORRECT_BCN
++void rtw_hal_fw_correct_bcn(_adapter *padapter);
++#endif
++s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan);
++
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++	void rtw_hal_clear_interrupt(_adapter *padapter);
++#endif
++
++void rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel);
++void rtw_hal_update_txpwr_level(_adapter *adapter);
++void rtw_hal_set_txpwr_done(_adapter *adapter);
++void rtw_hal_set_tx_power_index(_adapter *adapter, u32 powerindex
++	, enum rf_path rfpath, u8 rate);
++
++u8 rtw_hal_get_tx_power_index(_adapter *adapter, enum rf_path rfpath
++	, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch
++	, struct txpwr_idx_comp *tic);
++s8 rtw_hal_get_txpwr_target_extra_bias(_adapter *adapter, enum rf_path rfpath
++	, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch);
++
++u8 rtw_hal_ops_check(_adapter *padapter);
++
++#ifdef RTW_HALMAC
++	u8 rtw_hal_init_mac_register(PADAPTER);
++	u8 rtw_hal_init_phy(PADAPTER);
++s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem);
++#endif /* RTW_HALMAC */
++
++#ifdef CONFIG_RFKILL_POLL
++bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid);
++#endif
++
++#endif /* __HAL_INTF_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_pg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_pg.h
+new file mode 100755
+index 000000000..9de076932
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_pg.h
+@@ -0,0 +1,954 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __HAL_PG_H__
++#define __HAL_PG_H__
++
++#define PPG_BB_GAIN_2G_TX_OFFSET_MASK	0x0F
++#define PPG_BB_GAIN_2G_TXB_OFFSET_MASK	0xF0
++
++#define PPG_BB_GAIN_5G_TX_OFFSET_MASK	0x1F
++#define PPG_THERMAL_OFFSET_MASK			0x1F
++#define KFREE_BB_GAIN_2G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))
++#define KFREE_BB_GAIN_2G_TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg_v) >> 5) : (-((_ppg_v) >> 5))))
++#define KFREE_BB_GAIN_5G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))
++#define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))
++
++/* ****************************************************
++ *			EEPROM/Efuse PG Offset for 88EE/88EU/88ES
++ * **************************************************** */
++#define EEPROM_ChannelPlan_88E					0xB8
++#define EEPROM_XTAL_88E						0xB9
++#define EEPROM_THERMAL_METER_88E				0xBA
++#define EEPROM_IQK_LCK_88E						0xBB
++
++#define EEPROM_RF_BOARD_OPTION_88E			0xC1
++#define EEPROM_RF_FEATURE_OPTION_88E			0xC2
++#define EEPROM_RF_BT_SETTING_88E				0xC3
++#define EEPROM_VERSION_88E						0xC4
++#define EEPROM_CustomID_88E					0xC5
++#define EEPROM_RF_ANTENNA_OPT_88E			0xC9
++#define EEPROM_COUNTRY_CODE_88E				0xCB
++
++/* RTL88EE */
++#define EEPROM_MAC_ADDR_88EE					0xD0
++#define EEPROM_VID_88EE						0xD6
++#define EEPROM_DID_88EE						0xD8
++#define EEPROM_SVID_88EE						0xDA
++#define EEPROM_SMID_88EE						0xDC
++
++/* RTL88EU */
++#define EEPROM_MAC_ADDR_88EU					0xD7
++#define EEPROM_VID_88EU						0xD0
++#define EEPROM_PID_88EU						0xD2
++#define EEPROM_USB_OPTIONAL_FUNCTION0		0xD4 /* 8188EU, 8192EU, 8812AU is the same */
++#define EEPROM_USB_OPTIONAL_FUNCTION0_8811AU 0x104
++
++/* RTL88ES */
++#define EEPROM_MAC_ADDR_88ES					0x11A
++/* ****************************************************
++ *			EEPROM/Efuse PG Offset for 8192EE/8192EU/8192ES
++ * **************************************************** */
++#define GET_PG_KFREE_ON_8192E(_pg_m)			LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
++#define GET_PG_KFREE_THERMAL_K_ON_8192E(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
++
++#define PPG_BB_GAIN_2G_TXA_OFFSET_8192E	0x1F6
++#define PPG_THERMAL_OFFSET_8192E		0x1F5
++
++#define	EEPROM_ChannelPlan_8192E				0xB8
++#define	EEPROM_XTAL_8192E						0xB9
++#define	EEPROM_THERMAL_METER_8192E			0xBA
++#define	EEPROM_IQK_LCK_8192E					0xBB
++#define	EEPROM_2G_5G_PA_TYPE_8192E			0xBC
++#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8192E	0xBD
++#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8192E	0xBF
++
++#define	EEPROM_RF_BOARD_OPTION_8192E		0xC1
++#define	EEPROM_RF_FEATURE_OPTION_8192E		0xC2
++#define	EEPROM_RF_BT_SETTING_8192E			0xC3
++#define	EEPROM_VERSION_8192E					0xC4
++#define	EEPROM_CustomID_8192E				0xC5
++#define	EEPROM_TX_BBSWING_2G_8192E			0xC6
++#define	EEPROM_TX_BBSWING_5G_8192E			0xC7
++#define	EEPROM_TX_PWR_CALIBRATE_RATE_8192E	0xC8
++#define	EEPROM_RF_ANTENNA_OPT_8192E			0xC9
++#define	EEPROM_RFE_OPTION_8192E				0xCA
++#define	EEPROM_RFE_OPTION_8188E				0xCA
++#define EEPROM_COUNTRY_CODE_8192E			0xCB
++
++/* RTL8192EE */
++#define	EEPROM_MAC_ADDR_8192EE				0xD0
++#define	EEPROM_VID_8192EE						0xD6
++#define	EEPROM_DID_8192EE						0xD8
++#define	EEPROM_SVID_8192EE					0xDA
++#define	EEPROM_SMID_8192EE					0xDC
++
++/* RTL8192EU */
++#define	EEPROM_MAC_ADDR_8192EU				0xD7
++#define	EEPROM_VID_8192EU						0xD0
++#define	EEPROM_PID_8192EU						0xD2
++#define	EEPROM_PA_TYPE_8192EU		0xBC
++#define	EEPROM_LNA_TYPE_2G_8192EU	0xBD
++#define	EEPROM_LNA_TYPE_5G_8192EU	0xBF
++
++/* RTL8192ES */
++#define	EEPROM_MAC_ADDR_8192ES				0x11A
++/* ****************************************************
++ *			EEPROM/Efuse PG Offset for 8812AE/8812AU/8812AS
++ * *****************************************************/
++#define EEPROM_USB_MODE_8812					0x08
++
++#define EEPROM_ChannelPlan_8812				0xB8
++#define EEPROM_XTAL_8812						0xB9
++#define EEPROM_THERMAL_METER_8812			0xBA
++#define EEPROM_IQK_LCK_8812					0xBB
++#define EEPROM_2G_5G_PA_TYPE_8812			0xBC
++#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8812	0xBD
++#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8812	0xBF
++
++#define EEPROM_RF_BOARD_OPTION_8812			0xC1
++#define EEPROM_RF_FEATURE_OPTION_8812		0xC2
++#define EEPROM_RF_BT_SETTING_8812				0xC3
++#define EEPROM_VERSION_8812					0xC4
++#define EEPROM_CustomID_8812					0xC5
++#define EEPROM_TX_BBSWING_2G_8812			0xC6
++#define EEPROM_TX_BBSWING_5G_8812			0xC7
++#define EEPROM_TX_PWR_CALIBRATE_RATE_8812	0xC8
++#define EEPROM_RF_ANTENNA_OPT_8812			0xC9
++#define EEPROM_RFE_OPTION_8812				0xCA
++#define EEPROM_COUNTRY_CODE_8812			0xCB
++
++/* RTL8812AE */
++#define EEPROM_MAC_ADDR_8812AE				0xD0
++#define EEPROM_VID_8812AE						0xD6
++#define EEPROM_DID_8812AE						0xD8
++#define EEPROM_SVID_8812AE						0xDA
++#define EEPROM_SMID_8812AE					0xDC
++
++/* RTL8812AU */
++#define EEPROM_MAC_ADDR_8812AU				0xD7
++#define EEPROM_VID_8812AU						0xD0
++#define EEPROM_PID_8812AU						0xD2
++#define EEPROM_PA_TYPE_8812AU					0xBC
++#define EEPROM_LNA_TYPE_2G_8812AU			0xBD
++#define EEPROM_LNA_TYPE_5G_8812AU			0xBF
++
++/* RTL8814AU */
++#define	EEPROM_MAC_ADDR_8814AU				0xD8
++#define	EEPROM_VID_8814AU						0xD0
++#define	EEPROM_PID_8814AU						0xD2
++#define	EEPROM_PA_TYPE_8814AU				0xBC
++#define	EEPROM_LNA_TYPE_2G_8814AU			0xBD
++#define	EEPROM_LNA_TYPE_5G_8814AU			0xBF
++
++/* RTL8814AE */
++#define EEPROM_MAC_ADDR_8814AE				0xD0
++#define EEPROM_VID_8814AE						0xD6
++#define EEPROM_DID_8814AE						0xD8
++#define EEPROM_SVID_8814AE						0xDA
++#define EEPROM_SMID_8814AE					0xDC
++
++/* ****************************************************
++ *			EEPROM/Efuse PG Offset for 8814AU
++ * **************************************************** */
++#define GET_PG_KFREE_ON_8814A(_pg_m)			LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1)
++#define GET_PG_KFREE_THERMAL_K_ON_8814A(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
++#define GET_PG_TX_POWER_TRACKING_MODE_8814A(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 6, 2)
++
++#define KFREE_GAIN_DATA_LENGTH_8814A	22
++
++#define PPG_BB_GAIN_2G_TXBA_OFFSET_8814A	0x3EE
++
++#define PPG_THERMAL_OFFSET_8814A		0x3EF
++
++#define EEPROM_USB_MODE_8814A				0x0E
++#define EEPROM_ChannelPlan_8814				0xB8
++#define EEPROM_XTAL_8814					0xB9
++#define EEPROM_THERMAL_METER_8814			0xBA
++#define	EEPROM_IQK_LCK_8814					0xBB
++
++
++#define EEPROM_PA_TYPE_8814					0xBC
++#define EEPROM_LNA_TYPE_AB_2G_8814			0xBD
++#define	EEPROM_LNA_TYPE_CD_2G_8814			0xBE
++#define EEPROM_LNA_TYPE_AB_5G_8814			0xBF
++#define EEPROM_LNA_TYPE_CD_5G_8814			0xC0
++#define	EEPROM_RF_BOARD_OPTION_8814			0xC1
++#define	EEPROM_RF_BT_SETTING_8814			0xC3
++#define	EEPROM_VERSION_8814					0xC4
++#define	EEPROM_CustomID_8814				0xC5
++#define	EEPROM_TX_BBSWING_2G_8814			0xC6
++#define	EEPROM_TX_BBSWING_5G_8814			0xC7
++#define EEPROM_TRX_ANTENNA_OPTION_8814		0xC9
++#define	EEPROM_RFE_OPTION_8814				0xCA
++#define EEPROM_COUNTRY_CODE_8814			0xCB
++
++/*Extra Info for 8814A Initial Gain Fine Tune  suggested by Willis, JIRA: MP123*/
++#define	EEPROM_IG_OFFSET_4_AB_2G_8814A				0x120
++#define	EEPROM_IG_OFFSET_4_CD_2G_8814A				0x121
++#define	EEPROM_IG_OFFSET_4_AB_5GL_8814A				0x122
++#define	EEPROM_IG_OFFSET_4_CD_5GL_8814A				0x123
++#define	EEPROM_IG_OFFSET_4_AB_5GM_8814A				0x124
++#define	EEPROM_IG_OFFSET_4_CD_5GM_8814A				0x125
++#define	EEPROM_IG_OFFSET_4_AB_5GH_8814A				0x126
++#define	EEPROM_IG_OFFSET_4_CD_5GH_8814A				0x127
++
++/* ****************************************************
++ *			EEPROM/Efuse PG Offset for 8821AE/8821AU/8821AS
++ * **************************************************** */
++
++#define GET_PG_KFREE_ON_8821A(_pg_m)			LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1)
++#define GET_PG_KFREE_THERMAL_K_ON_8821A(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
++
++#define PPG_BB_GAIN_2G_TXA_OFFSET_8821A		0x1F6
++#define PPG_THERMAL_OFFSET_8821A			0x1F5
++#define PPG_BB_GAIN_5GLB1_TXA_OFFSET_8821A	0x1F4
++#define PPG_BB_GAIN_5GLB2_TXA_OFFSET_8821A	0x1F3
++#define PPG_BB_GAIN_5GMB1_TXA_OFFSET_8821A	0x1F2
++#define PPG_BB_GAIN_5GMB2_TXA_OFFSET_8821A	0x1F1
++#define PPG_BB_GAIN_5GHB_TXA_OFFSET_8821A	0x1F0
++
++#define EEPROM_ChannelPlan_8821				0xB8
++#define EEPROM_XTAL_8821						0xB9
++#define EEPROM_THERMAL_METER_8821			0xBA
++#define EEPROM_IQK_LCK_8821					0xBB
++
++
++#define EEPROM_RF_BOARD_OPTION_8821			0xC1
++#define EEPROM_RF_FEATURE_OPTION_8821		0xC2
++#define EEPROM_RF_BT_SETTING_8821				0xC3
++#define EEPROM_VERSION_8821					0xC4
++#define EEPROM_CustomID_8821					0xC5
++#define EEPROM_RF_ANTENNA_OPT_8821			0xC9
++
++/* RTL8821AE */
++#define EEPROM_MAC_ADDR_8821AE				0xD0
++#define EEPROM_VID_8821AE						0xD6
++#define EEPROM_DID_8821AE						0xD8
++#define EEPROM_SVID_8821AE						0xDA
++#define EEPROM_SMID_8821AE					0xDC
++
++/* RTL8821AU */
++#define EEPROM_PA_TYPE_8821AU					0xBC
++#define EEPROM_LNA_TYPE_8821AU				0xBF
++
++/* RTL8821AS */
++#define EEPROM_MAC_ADDR_8821AS				0x11A
++
++/* RTL8821AU */
++#define EEPROM_MAC_ADDR_8821AU				0x107
++#define EEPROM_VID_8821AU						0x100
++#define EEPROM_PID_8821AU						0x102
++
++
++/* ****************************************************
++ *			EEPROM/Efuse PG Offset for 8192 SE/SU
++ * **************************************************** */
++#define EEPROM_VID_92SE						0x0A
++#define EEPROM_DID_92SE						0x0C
++#define EEPROM_SVID_92SE						0x0E
++#define EEPROM_SMID_92SE						0x10
++
++#define EEPROM_MAC_ADDR_92S					0x12
++
++#define EEPROM_TSSI_A_92SE						0x74
++#define EEPROM_TSSI_B_92SE						0x75
++
++#define EEPROM_Version_92SE					0x7C
++
++
++#define EEPROM_VID_92SU						0x08
++#define EEPROM_PID_92SU						0x0A
++
++#define EEPROM_Version_92SU					0x50
++#define EEPROM_TSSI_A_92SU						0x6b
++#define EEPROM_TSSI_B_92SU						0x6c
++
++/* ====================================================
++	EEPROM/Efuse PG Offset for 8188FE/8188FU/8188FS
++   ====================================================
++ */
++
++#define GET_PG_KFREE_ON_8188F(_pg_m)			LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
++#define GET_PG_KFREE_THERMAL_K_ON_8188F(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
++
++#define PPG_BB_GAIN_2G_TXA_OFFSET_8188F	0xEE
++#define PPG_THERMAL_OFFSET_8188F		0xEF
++
++#define	EEPROM_ChannelPlan_8188F			0xB8
++#define	EEPROM_XTAL_8188F					0xB9
++#define	EEPROM_THERMAL_METER_8188F			0xBA
++#define	EEPROM_IQK_LCK_8188F				0xBB
++#define	EEPROM_2G_5G_PA_TYPE_8188F			0xBC
++#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8188F	0xBD
++#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8188F	0xBF
++
++#define	EEPROM_RF_BOARD_OPTION_8188F		0xC1
++#define	EEPROM_FEATURE_OPTION_8188F			0xC2
++#define	EEPROM_RF_BT_SETTING_8188F			0xC3
++#define	EEPROM_VERSION_8188F				0xC4
++#define	EEPROM_CustomID_8188F				0xC5
++#define	EEPROM_TX_BBSWING_2G_8188F			0xC6
++#define	EEPROM_TX_PWR_CALIBRATE_RATE_8188F	0xC8
++#define	EEPROM_RF_ANTENNA_OPT_8188F			0xC9
++#define	EEPROM_RFE_OPTION_8188F				0xCA
++#define EEPROM_COUNTRY_CODE_8188F			0xCB
++#define EEPROM_CUSTOMER_ID_8188F			0x7F
++#define EEPROM_SUBCUSTOMER_ID_8188F			0x59
++
++/* RTL8188FU */
++#define EEPROM_MAC_ADDR_8188FU				0xD7
++#define EEPROM_VID_8188FU					0xD0
++#define EEPROM_PID_8188FU					0xD2
++#define EEPROM_PA_TYPE_8188FU				0xBC
++#define EEPROM_LNA_TYPE_2G_8188FU			0xBD
++#define EEPROM_USB_OPTIONAL_FUNCTION0_8188FU 0xD4
++
++/* RTL8188FS */
++#define	EEPROM_MAC_ADDR_8188FS				0x11A
++#define EEPROM_Voltage_ADDR_8188F			0x8
++
++/* ====================================================
++	EEPROM/Efuse PG Offset for 8188GTV/8188GTVS
++   ====================================================
++ */
++
++#define GET_PG_KFREE_ON_8188GTV(_pg_m)				LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
++#define GET_PG_KFREE_THERMAL_K_ON_8188GTV(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
++
++#define PPG_BB_GAIN_2G_TXA_OFFSET_8188GTV	0xEE
++#define PPG_THERMAL_OFFSET_8188GTV			0xEF
++
++#define	EEPROM_ChannelPlan_8188GTV				0xB8
++#define	EEPROM_XTAL_8188GTV						0xB9
++#define	EEPROM_THERMAL_METER_8188GTV			0xBA
++#define	EEPROM_IQK_LCK_8188GTV					0xBB
++#define	EEPROM_2G_5G_PA_TYPE_8188GTV			0xBC
++#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8188GTV		0xBD
++#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8188GTV		0xBF
++
++#define	EEPROM_RF_BOARD_OPTION_8188GTV			0xC1
++#define	EEPROM_FEATURE_OPTION_8188GTV			0xC2
++#define	EEPROM_RF_BT_SETTING_8188GTV			0xC3
++#define	EEPROM_VERSION_8188GTV					0xC4
++#define	EEPROM_CustomID_8188GTV					0xC5
++#define	EEPROM_TX_BBSWING_2G_8188GTV			0xC6
++#define	EEPROM_TX_PWR_CALIBRATE_RATE_8188GTV	0xC8
++#define	EEPROM_RF_ANTENNA_OPT_8188GTV			0xC9
++#define	EEPROM_RFE_OPTION_8188GTV				0xCA
++#define EEPROM_COUNTRY_CODE_8188GTV				0xCB
++#define EEPROM_CUSTOMER_ID_8188GTV				0x7F
++#define EEPROM_SUBCUSTOMER_ID_8188GTV			0x59
++
++/* RTL8188GTVU */
++#define EEPROM_MAC_ADDR_8188GTVU				0xD7
++#define EEPROM_VID_8188GTVU						0xD0
++#define EEPROM_PID_8188GTVU						0xD2
++#define EEPROM_PA_TYPE_8188GTVU					0xBC
++#define EEPROM_LNA_TYPE_2G_8188GTVU				0xBD
++#define EEPROM_USB_OPTIONAL_FUNCTION0_8188GTVU	0xD4
++
++/* RTL8188GTVS */
++#define	EEPROM_MAC_ADDR_8188GTVS				0x11A
++#define EEPROM_Voltage_ADDR_8188GTV				0x8
++
++/* ****************************************************
++ *			EEPROM/Efuse PG Offset for 8723BE/8723BU/8723BS
++ * *****************************************************/
++#define	EEPROM_ChannelPlan_8723B				0xB8
++#define	EEPROM_XTAL_8723B						0xB9
++#define	EEPROM_THERMAL_METER_8723B			0xBA
++#define	EEPROM_IQK_LCK_8723B					0xBB
++#define	EEPROM_2G_5G_PA_TYPE_8723B			0xBC
++#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8723B	0xBD
++#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8723B	0xBF
++
++#define	EEPROM_RF_BOARD_OPTION_8723B		0xC1
++#define	EEPROM_FEATURE_OPTION_8723B			0xC2
++#define	EEPROM_RF_BT_SETTING_8723B			0xC3
++#define	EEPROM_VERSION_8723B					0xC4
++#define	EEPROM_CustomID_8723B				0xC5
++#define	EEPROM_TX_BBSWING_2G_8723B			0xC6
++#define	EEPROM_TX_PWR_CALIBRATE_RATE_8723B	0xC8
++#define	EEPROM_RF_ANTENNA_OPT_8723B		0xC9
++#define	EEPROM_RFE_OPTION_8723B				0xCA
++#define EEPROM_COUNTRY_CODE_8723B			0xCB
++
++/* RTL8723BE */
++#define EEPROM_MAC_ADDR_8723BE				0xD0
++#define EEPROM_VID_8723BE						0xD6
++#define EEPROM_DID_8723BE						0xD8
++#define EEPROM_SVID_8723BE						0xDA
++#define EEPROM_SMID_8723BE						0xDC
++
++/* RTL8723BU */
++#define EEPROM_MAC_ADDR_8723BU				0x107
++#define EEPROM_VID_8723BU						0x100
++#define EEPROM_PID_8723BU						0x102
++#define EEPROM_PA_TYPE_8723BU					0xBC
++#define EEPROM_LNA_TYPE_2G_8723BU				0xBD
++
++
++/* RTL8723BS */
++#define	EEPROM_MAC_ADDR_8723BS				0x11A
++#define EEPROM_Voltage_ADDR_8723B			0x8
++
++/* ****************************************************
++ *			EEPROM/Efuse PG Offset for 8703B
++ * **************************************************** */
++#define GET_PG_KFREE_ON_8703B(_pg_m)			LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
++#define GET_PG_KFREE_THERMAL_K_ON_8703B(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
++
++#define PPG_BB_GAIN_2G_TXA_OFFSET_8703B	0xEE
++#define PPG_THERMAL_OFFSET_8703B		0xEF
++
++#define	EEPROM_ChannelPlan_8703B				0xB8
++#define	EEPROM_XTAL_8703B					0xB9
++#define	EEPROM_THERMAL_METER_8703B			0xBA
++#define	EEPROM_IQK_LCK_8703B					0xBB
++#define	EEPROM_2G_5G_PA_TYPE_8703B			0xBC
++#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8703B	0xBD
++#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8703B	0xBF
++
++#define	EEPROM_RF_BOARD_OPTION_8703B		0xC1
++#define	EEPROM_FEATURE_OPTION_8703B			0xC2
++#define	EEPROM_RF_BT_SETTING_8703B			0xC3
++#define	EEPROM_VERSION_8703B					0xC4
++#define	EEPROM_CustomID_8703B					0xC5
++#define	EEPROM_TX_BBSWING_2G_8703B			0xC6
++#define	EEPROM_TX_PWR_CALIBRATE_RATE_8703B	0xC8
++#define	EEPROM_RF_ANTENNA_OPT_8703B		0xC9
++#define	EEPROM_RFE_OPTION_8703B				0xCA
++#define EEPROM_COUNTRY_CODE_8703B			0xCB
++
++/* RTL8703BU */
++#define EEPROM_MAC_ADDR_8703BU                          0x107
++#define EEPROM_VID_8703BU                               0x100
++#define EEPROM_PID_8703BU                               0x102
++#define EEPROM_USB_OPTIONAL_FUNCTION0_8703BU            0x104
++#define EEPROM_PA_TYPE_8703BU                           0xBC
++#define EEPROM_LNA_TYPE_2G_8703BU                       0xBD
++
++/* RTL8703BS */
++#define	EEPROM_MAC_ADDR_8703BS				0x11A
++#define	EEPROM_Voltage_ADDR_8703B			0x8
++
++/*
++ * ====================================================
++ *	EEPROM/Efuse PG Offset for 8822B
++ * ====================================================
++ */
++#define	EEPROM_ChannelPlan_8822B		0xB8
++#define	EEPROM_XTAL_8822B			0xB9
++#define	EEPROM_THERMAL_METER_8822B		0xBA
++#define	EEPROM_IQK_LCK_8822B			0xBB
++#define	EEPROM_2G_5G_PA_TYPE_8822B		0xBC
++/* PATH A & PATH B */
++#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B	0xBD
++/* PATH C & PATH D */
++#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8822B	0xBE
++/* PATH A & PATH B */
++#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B	0xBF
++/* PATH C & PATH D */
++#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8822B	0xC0
++
++#define	EEPROM_RF_BOARD_OPTION_8822B		0xC1
++#define	EEPROM_FEATURE_OPTION_8822B		0xC2
++#define	EEPROM_RF_BT_SETTING_8822B		0xC3
++#define	EEPROM_VERSION_8822B			0xC4
++#define	EEPROM_CustomID_8822B			0xC5
++#define	EEPROM_TX_BBSWING_2G_8822B		0xC6
++#define	EEPROM_TX_PWR_CALIBRATE_RATE_8822B	0xC8
++#define	EEPROM_RF_ANTENNA_OPT_8822B		0xC9
++#define	EEPROM_RFE_OPTION_8822B			0xCA
++#define EEPROM_COUNTRY_CODE_8822B		0xCB
++
++/* RTL8822BU */
++#define EEPROM_MAC_ADDR_8822BU			0x107
++#define EEPROM_VID_8822BU			0x100
++#define EEPROM_PID_8822BU			0x102
++#define EEPROM_USB_OPTIONAL_FUNCTION0_8822BU	0x104
++#define EEPROM_USB_MODE_8822BU			0x06
++
++/* RTL8822BS */
++#define	EEPROM_MAC_ADDR_8822BS			0x11A
++
++/* RTL8822BE */
++#define	EEPROM_MAC_ADDR_8822BE			0xD0
++/*
++ * ====================================================
++ *	EEPROM/Efuse PG Offset for 8821C
++ * ====================================================
++ */
++#define	EEPROM_CHANNEL_PLAN_8821C		0xB8
++#define	EEPROM_XTAL_8821C			0xB9
++#define	EEPROM_THERMAL_METER_8821C		0xBA
++#define	EEPROM_IQK_LCK_8821C			0xBB
++#define	EEPROM_2G_5G_PA_TYPE_8821C		0xBC
++/* PATH A & PATH B */
++#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8821C	0xBD
++/* PATH C & PATH D */
++#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8821C	0xBE
++/* PATH A & PATH B */
++#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8821C	0xBF
++/* PATH C & PATH D */
++#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8821C	0xC0
++
++#define	EEPROM_RF_BOARD_OPTION_8821C		0xC1
++#define	EEPROM_FEATURE_OPTION_8821C		0xC2
++#define	EEPROM_RF_BT_SETTING_8821C		0xC3
++#define	EEPROM_VERSION_8821C			0xC4
++#define	EEPROM_CUSTOMER_ID_8821C			0xC5
++#define	EEPROM_TX_BBSWING_2G_8821C		0xC6
++#define	EEPROM_TX_BBSWING_5G_8821C		0xC7
++#define	EEPROM_TX_PWR_CALIBRATE_RATE_8821C	0xC8
++#define	EEPROM_RF_ANTENNA_OPT_8821C		0xC9
++#define	EEPROM_RFE_OPTION_8821C			0xCA
++#define EEPROM_COUNTRY_CODE_8821C		0xCB
++
++/* RTL8821CU */
++#define EEPROM_MAC_ADDR_8821CU			0x107
++#define EEPROM_VID_8821CU					0x100
++#define EEPROM_PID_8821CU					0x102
++#define EEPROM_USB_OPTIONAL_FUNCTION0_8821CU	0x104
++#define EEPROM_USB_MODE_8821CU			0x06
++
++/* RTL8821CS */
++#define	EEPROM_MAC_ADDR_8821CS			0x11A
++
++/* RTL8821CE */
++#define	EEPROM_MAC_ADDR_8821CE			0xD0
++/* ****************************************************
++ *	EEPROM/Efuse PG Offset for 8723D
++ * **************************************************** */
++#define GET_PG_KFREE_ON_8723D(_pg_m)	\
++	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
++#define GET_PG_KFREE_THERMAL_K_ON_8723D(_pg_m)	\
++	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
++
++#define PPG_8723D_S1	0
++#define PPG_8723D_S0	1
++
++#define PPG_BB_GAIN_2G_TXA_OFFSET_8723D		0xEE
++#define PPG_BB_GAIN_2G_TX_OFFSET_8723D		0x1EE
++#define PPG_THERMAL_OFFSET_8723D		0xEF
++
++#define	EEPROM_ChannelPlan_8723D		0xB8
++#define	EEPROM_XTAL_8723D			0xB9
++#define	EEPROM_THERMAL_METER_8723D		0xBA
++#define	EEPROM_IQK_LCK_8723D			0xBB
++#define	EEPROM_2G_5G_PA_TYPE_8723D		0xBC
++#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8723D	0xBD
++#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8723D	0xBF
++
++#define	EEPROM_RF_BOARD_OPTION_8723D		0xC1
++#define	EEPROM_FEATURE_OPTION_8723D		0xC2
++#define	EEPROM_RF_BT_SETTING_8723D		0xC3
++#define	EEPROM_VERSION_8723D			0xC4
++#define	EEPROM_CustomID_8723D			0xC5
++#define	EEPROM_TX_BBSWING_2G_8723D		0xC6
++#define	EEPROM_TX_PWR_CALIBRATE_RATE_8723D	0xC8
++#define	EEPROM_RF_ANTENNA_OPT_8723D		0xC9
++#define	EEPROM_RFE_OPTION_8723D			0xCA
++#define EEPROM_COUNTRY_CODE_8723D		0xCB
++
++/* RTL8723DE */
++#define EEPROM_MAC_ADDR_8723DE              0xD0
++#define EEPROM_VID_8723DE                   0xD6
++#define EEPROM_DID_8723DE                   0xD8
++#define EEPROM_SVID_8723DE                  0xDA
++#define EEPROM_SMID_8723DE                  0xDC
++
++/* RTL8723DU */
++#define EEPROM_MAC_ADDR_8723DU                  0x107
++#define EEPROM_VID_8723DU                       0x100
++#define EEPROM_PID_8723DU                       0x102
++#define EEPROM_USB_OPTIONAL_FUNCTION0_8723DU    0x104
++
++/* RTL8723BS */
++#define	EEPROM_MAC_ADDR_8723DS			0x11A
++#define	EEPROM_Voltage_ADDR_8723D		0x8
++
++/*
++ * ====================================================
++ *	EEPROM/Efuse PG Offset for 8822C
++ * ====================================================
++ */
++#define	EEPROM_TX_PWR_INX_8822C			0x10
++#define	EEPROM_ChannelPlan_8822C		0xB8
++#define	EEPROM_XTAL_B9_8822C			0xB9
++#define	EEPROM_IQK_LCK_8822C			0xBB
++#define	EEPROM_2G_5G_PA_TYPE_8822C		0xBC
++/* PATH A & PATH B */
++#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822C	0xBD
++/* PATH C & PATH D */
++#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8822C	0xBE
++/* PATH A & PATH B */
++#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822C	0xBF
++/* PATH C & PATH D */
++#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8822C	0xC0
++
++#define	EEPROM_RF_BOARD_OPTION_8822C		0xC1
++#define	EEPROM_FEATURE_OPTION_8822C		0xC2
++#define	EEPROM_RF_BT_SETTING_8822C		0xC3
++#define	EEPROM_VERSION_8822C			0xC4
++#define	EEPROM_CustomID_8822C			0xC5
++#define	EEPROM_TX_BBSWING_2G_8822C		0xC6
++#define	EEPROM_TX_PWR_CALIBRATE_RATE_8822C	0xC8
++#define	EEPROM_RF_ANTENNA_OPT_8822C		0xC9
++#define	EEPROM_RFE_OPTION_8822C			0xCA
++#define EEPROM_COUNTRY_CODE_8822C		0xCB
++#define	EEPROM_THERMAL_METER_A_8822C		0xD0
++#define	EEPROM_THERMAL_METER_B_8822C		0xD1
++
++#define	EEPROM_XTAL_110_8822C			0x110
++#define	EEPROM_XTAL_111_8822C			0x111
++
++/* RTL8822CU */
++#define EEPROM_MAC_ADDR_8822CU			0x157
++#define EEPROM_VID_8822CU			0x100
++#define EEPROM_PID_8822CU			0x102
++#define EEPROM_USB_OPTIONAL_FUNCTION0_8822CU	0x104
++#define EEPROM_USB_MODE_8822CU			0x06
++
++/* RTL8822CS */
++#define	EEPROM_MAC_ADDR_8822CS			0x16A
++
++/* RTL8822CE */
++#define	EEPROM_MAC_ADDR_8822CE			0x120
++
++/* ****************************************************
++ *	EEPROM/Efuse PG Offset for 8192F
++ * **************************************************** */
++#define	EEPROM_ChannelPlan_8192F			0xB8
++#define	EEPROM_XTAL_8192F					0xB9
++#define	EEPROM_THERMAL_METER_8192F			0xBA
++#define	EEPROM_IQK_LCK_8192F				0xBB
++#define	EEPROM_2G_5G_PA_TYPE_8192F			0xBC
++#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8192F	0xBD
++#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8192F	0xBF
++
++#define	EEPROM_RF_BOARD_OPTION_8192F		0xC1
++#define	EEPROM_FEATURE_OPTION_8192F			0xC2
++#define	EEPROM_RF_BT_SETTING_8192F			0xC3
++#define	EEPROM_VERSION_8192F				0xC4
++#define	EEPROM_CustomID_8192F				0xC5
++#define	EEPROM_TX_BBSWING_2G_8192F			0xC6
++#define	EEPROM_TX_BBSWING_5G_8192F			0xC7
++#define	EEPROM_TX_PWR_CALIBRATE_RATE_8192F	0xC8
++#define	EEPROM_RF_ANTENNA_OPT_8192F			0xC9
++#define	EEPROM_RFE_OPTION_8192F				0xCA
++#define EEPROM_COUNTRY_CODE_8192F			0xCB
++/*RTL8192FS*/
++#define	EEPROM_MAC_ADDR_8192FS				0x11A
++#define EEPROM_Voltage_ADDR_8192F			0x8
++/* RTL8192FU */
++#define EEPROM_MAC_ADDR_8192FU					0x107
++#define EEPROM_VID_8192FU							0x100
++#define EEPROM_PID_8192FU							0x102
++#define EEPROM_USB_OPTIONAL_FUNCTION0_8192FU	0x104
++/* RTL8192FE */
++#define EEPROM_MAC_ADDR_8192FE					0xD0
++#define EEPROM_VID_8192FE							0xD6
++#define EEPROM_DID_8192FE							0xD8
++#define EEPROM_SVID_8192FE							0xDA
++#define EEPROM_SMID_8192FE						0xDC
++
++/* ****************************************************
++ *	EEPROM/Efuse PG Offset for 8710B
++ * **************************************************** */
++#define RTL_EEPROM_ID_8710B 					0x8195
++#define EEPROM_Default_ThermalMeter_8710B		0x1A
++
++#define	EEPROM_CHANNEL_PLAN_8710B			0xC8
++#define	EEPROM_XTAL_8710B					0xC9
++#define	EEPROM_THERMAL_METER_8710B			0xCA
++#define	EEPROM_IQK_LCK_8710B					0xCB
++#define	EEPROM_2G_5G_PA_TYPE_8710B			0xCC
++#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8710B	0xCD
++#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8710B	0xCF
++#define 	EEPROM_TX_KFREE_8710B				0xEE    //Physical  Efuse Address
++#define 	EEPROM_THERMAL_8710B				0xEF    //Physical  Efuse Address
++#define 	EEPROM_PACKAGE_TYPE_8710B			0xF8    //Physical  Efuse Address
++
++#define EEPROM_RF_BOARD_OPTION_8710B		0x131
++#define EEPROM_RF_FEATURE_OPTION_8710B		0x132
++#define EEPROM_RF_BT_SETTING_8710B			0x133
++#define EEPROM_VERSION_8710B					0x134
++#define EEPROM_CUSTOM_ID_8710B				0x135
++#define EEPROM_TX_BBSWING_2G_8710B			0x136
++#define EEPROM_TX_BBSWING_5G_8710B			0x137
++#define EEPROM_TX_PWR_CALIBRATE_RATE_8710B	0x138
++#define EEPROM_RF_ANTENNA_OPT_8710B			0x139
++#define EEPROM_RFE_OPTION_8710B				0x13A
++#define EEPROM_COUNTRY_CODE_8710B			0x13B
++#define EEPROM_COUNTRY_CODE_2_8710B			0x13C
++
++#define EEPROM_MAC_ADDR_8710B 				0x11A
++#define EEPROM_VID_8710BU						0x1C0
++#define EEPROM_PID_8710BU						0x1C2
++
++/* ****************************************************
++ *	EEPROM/Efuse PG Offset for 8814B
++ * **************************************************** */
++
++#define	EEPROM_USB_MODE_8814BU			0x06
++/* 0x10 ~ 0x63 = TX power area. */
++#define	EEPROM_TX_PWR_INX_8814B			0x10
++#define	EEPROM_ChannelPlan_8814B		0xB8
++#define	EEPROM_XTAL_8814B			0xB9
++#define	EEPROM_IQK_LCK_8814B			0xBB
++
++#define	EEPROM_RF_BOARD_OPTION_8814B		0xC1
++#define	EEPROM_RF_FEATURE_OPTION_8814B		0xC2
++#define	EEPROM_RF_BT_SETTING_8814B		0xC3
++#define	EEPROM_VERSION_8814B			0xC4
++#define	EEPROM_CustomID_8814B			0xC5
++#define	EEPROM_TX_BBSWING_2G_8814B		0xC6
++#define	EEPROM_TX_BBSWING_5G_8814B		0xC7
++#define	EEPROM_TX_PWR_CALIBRATE_RATE_8814B	0xC8
++#define	EEPROM_RF_ANTENNA_OPT_8814B		0xC9
++#define	EEPROM_RFE_OPTION_8814B			0xCA
++#define	EEPROM_COUNTRY_CODE_8814B		0xCB
++
++#define	EEPROM_THERMAL_METER_A_8814B		0xD0
++#define	EEPROM_THERMAL_METER_B_8814B		0xD1
++#define	EEPROM_THERMAL_METER_C_8814B		0xD2
++#define	EEPROM_THERMAL_METER_D_8814B		0xD3
++
++#define	EEPROM_MAC_ADDR_8814BE			0x120
++#define	EEPROM_VID_8814B			0x126
++#define	EEPROM_DID_8814B			0x128
++#define	EEPROM_SVID_8814B			0x12A
++#define	EEPROM_SMID_8814B			0x12C
++
++/* RTL8814BU */
++#define EEPROM_MAC_ADDR_8814BU			0x157
++#define EEPROM_VID_8814BU			0x150
++#define EEPROM_PID_8814BU			0x152
++#define EEPROM_USB_OPTIONAL_FUNCTION0_8814BU	0x154
++
++/* ****************************************************
++ *			EEPROM/Efuse Value Type
++ * **************************************************** */
++#define EETYPE_TX_PWR							0x0
++#define EETYPE_MAX_RFE_8192F					0x31
++/* ****************************************************
++ *			EEPROM/Efuse Default Value
++ * **************************************************** */
++#define EEPROM_CID_DEFAULT					0x0
++#define EEPROM_CID_DEFAULT_EXT				0xFF /* Reserved for Realtek */
++#define EEPROM_CID_TOSHIBA						0x4
++#define EEPROM_CID_CCX							0x10
++#define EEPROM_CID_QMI							0x0D
++#define EEPROM_CID_WHQL						0xFE
++
++#define EEPROM_CHANNEL_PLAN_FCC				0x0
++#define EEPROM_CHANNEL_PLAN_IC				0x1
++#define EEPROM_CHANNEL_PLAN_ETSI				0x2
++#define EEPROM_CHANNEL_PLAN_SPAIN			0x3
++#define EEPROM_CHANNEL_PLAN_FRANCE			0x4
++#define EEPROM_CHANNEL_PLAN_MKK				0x5
++#define EEPROM_CHANNEL_PLAN_MKK1				0x6
++#define EEPROM_CHANNEL_PLAN_ISRAEL			0x7
++#define EEPROM_CHANNEL_PLAN_TELEC			0x8
++#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN	0x9
++#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13	0xA
++#define EEPROM_CHANNEL_PLAN_NCC_TAIWAN		0xB
++#define EEPROM_CHANNEL_PLAN_CHIAN			0XC
++#define EEPROM_CHANNEL_PLAN_SINGAPORE_INDIA_MEXICO  0XD
++#define EEPROM_CHANNEL_PLAN_KOREA			0xE
++#define EEPROM_CHANNEL_PLAN_TURKEY	0xF
++#define EEPROM_CHANNEL_PLAN_JAPAN	0x10
++#define EEPROM_CHANNEL_PLAN_FCC_NO_DFS		0x11
++#define EEPROM_CHANNEL_PLAN_JAPAN_NO_DFS	0x12
++#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_5G	0x13
++#define EEPROM_CHANNEL_PLAN_TAIWAN_NO_DFS	0x14
++
++#define EEPROM_USB_OPTIONAL1					0xE
++#define EEPROM_CHANNEL_PLAN_BY_HW_MASK		0x80
++
++#define RTL_EEPROM_ID							0x8129
++#define EEPROM_Default_TSSI						0x0
++#define EEPROM_Default_BoardType				0x02
++#define EEPROM_Default_ThermalMeter			0x12
++#define EEPROM_Default_ThermalMeter_92SU		0x7
++#define EEPROM_Default_ThermalMeter_88E		0x18
++#define EEPROM_Default_ThermalMeter_8812		0x18
++#define	EEPROM_Default_ThermalMeter_8192E			0x1A
++#define	EEPROM_Default_ThermalMeter_8723B		0x18
++#define	EEPROM_Default_ThermalMeter_8703B		0x18
++#define	EEPROM_Default_ThermalMeter_8723D		0x18
++#define	EEPROM_Default_ThermalMeter_8188F		0x18
++#define	EEPROM_Default_ThermalMeter_8188GTV		0x18
++#define EEPROM_Default_ThermalMeter_8814A		0x18
++#define	EEPROM_Default_ThermalMeter_8192F		0x1A
++#define EEPROM_Default_ThermalMeter_8814B		0x20
++
++#define EEPROM_Default_CrystalCap				0x0
++#define EEPROM_Default_CrystalCap_8723A		0x20
++#define EEPROM_Default_CrystalCap_88E			0x20
++#define EEPROM_Default_CrystalCap_8812			0x20
++#define EEPROM_Default_CrystalCap_8814			0x20
++#define EEPROM_Default_CrystalCap_8192E			0x20
++#define EEPROM_Default_CrystalCap_8723B			0x20
++#define EEPROM_Default_CrystalCap_8703B			0x20
++#define EEPROM_Default_CrystalCap_8723D			0x20
++#define EEPROM_Default_CrystalCap_8188F			0x20
++#define EEPROM_Default_CrystalCap_8188GTV		0x20
++#define EEPROM_Default_CrystalCap_8192F			0x20
++#define EEPROM_Default_CrystalCap_B9_8822C		0x3F
++#define EEPROM_Default_CrystalCap_110_8822C		0x40
++#define EEPROM_Default_CrystalCap_111_8822C		0x40
++#define EEPROM_Default_CrystalCap_8814B			0x40
++#define EEPROM_Default_CrystalFreq				0x0
++#define EEPROM_Default_TxPowerLevel_92C		0x22
++#define EEPROM_Default_TxPowerLevel_2G			0x2C
++#define EEPROM_Default_TxPowerLevel_5G			0x22
++#define EEPROM_Default_TxPowerLevel			0x22
++#define EEPROM_Default_HT40_2SDiff				0x0
++#define EEPROM_Default_HT20_Diff				2
++#define EEPROM_Default_LegacyHTTxPowerDiff		0x3
++#define EEPROM_Default_LegacyHTTxPowerDiff_92C	0x3
++#define EEPROM_Default_LegacyHTTxPowerDiff_92D	0x4
++#define EEPROM_Default_HT40_PwrMaxOffset		0
++#define EEPROM_Default_HT20_PwrMaxOffset		0
++
++#define EEPROM_Default_PID						0x1234
++#define EEPROM_Default_VID						0x5678
++#define EEPROM_Default_CustomerID				0xAB
++#define EEPROM_Default_CustomerID_8188E		0x00
++#define EEPROM_Default_SubCustomerID			0xCD
++#define EEPROM_Default_Version					0
++
++#define EEPROM_Default_externalPA_C9		0x00
++#define EEPROM_Default_externalPA_CC		0xFF
++#define EEPROM_Default_internalPA_SP3T_C9	0xAA
++#define EEPROM_Default_internalPA_SP3T_CC	0xAF
++#define EEPROM_Default_internalPA_SPDT_C9	0xAA
++#ifdef CONFIG_PCI_HCI
++	#define EEPROM_Default_internalPA_SPDT_CC	0xA0
++#else
++	#define EEPROM_Default_internalPA_SPDT_CC	0xFA
++#endif
++#define EEPROM_Default_PAType						0
++#define EEPROM_Default_LNAType						0
++
++/* New EFUSE default value */
++#define EEPROM_DEFAULT_CHANNEL_PLAN		0x7F
++#define EEPROM_DEFAULT_BOARD_OPTION		0x00
++#define EEPROM_DEFAULT_RFE_OPTION_8192E 0xFF
++#define EEPROM_DEFAULT_RFE_OPTION_8188E 0xFF
++#define EEPROM_DEFAULT_RFE_OPTION		0x04
++#define EEPROM_DEFAULT_FEATURE_OPTION	0x00
++#define EEPROM_DEFAULT_BT_OPTION			0x10
++
++
++#define EEPROM_DEFAULT_TX_CALIBRATE_RATE	0x00
++
++/* PCIe related */
++#define	EEPROM_PCIE_DEV_CAP_01				0xE0 /* Express device capability in PCIe configuration space, i.e., map to offset 0x74 */
++#define	EEPROM_PCIE_DEV_CAP_02				0xE1 /* Express device capability in PCIe configuration space, i.e., map to offset 0x75 */
++
++
++/*
++ * For VHT series TX power by rate table.
++ * VHT TX power by rate off setArray =
++ * Band:-2G&5G = 0 / 1
++ * RF: at most 4*4 = ABCD=0/1/2/3
++ * CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11
++ *   */
++#define TX_PWR_BY_RATE_NUM_BAND			2
++#define TX_PWR_BY_RATE_NUM_RF			4
++#define TX_PWR_BY_RATE_NUM_RATE			84
++
++#define TXPWR_LMT_MAX_RF				4
++
++/* ----------------------------------------------------------------------------
++ * EEPROM/EFUSE data structure definition.
++ * ---------------------------------------------------------------------------- */
++
++/* For 88E new structure */
++
++/*
++2.4G:
++{
++{1,2},
++{3,4,5},
++{6,7,8},
++{9,10,11},
++{12,13},
++{14}
++}
++
++5G:
++{
++{36,38,40},
++{44,46,48},
++{52,54,56},
++{60,62,64},
++{100,102,104},
++{108,110,112},
++{116,118,120},
++{124,126,128},
++{132,134,136},
++{140,142,144},
++{149,151,153},
++{157,159,161},
++{173,175,177},
++}
++*/
++#define	MAX_RF_PATH				4
++#define RF_PATH_MAX				MAX_RF_PATH
++#define	MAX_CHNL_GROUP_24G		6
++#define	MAX_CHNL_GROUP_5G		14
++
++/* It must always set to 4, otherwise read efuse table sequence will be wrong. */
++#define	MAX_TX_COUNT				4
++
++typedef	enum _BT_Ant_NUM {
++	Ant_x2	= 0,
++	Ant_x1	= 1
++} BT_Ant_NUM, *PBT_Ant_NUM;
++
++typedef	enum _BT_CoType {
++	BT_2WIRE		= 0,
++	BT_ISSC_3WIRE	= 1,
++	BT_ACCEL		= 2,
++	BT_CSR_BC4		= 3,
++	BT_CSR_BC8		= 4,
++	BT_RTL8756		= 5,
++	BT_RTL8723A		= 6,
++	BT_RTL8821		= 7,
++	BT_RTL8723B		= 8,
++	BT_RTL8192E		= 9,
++	BT_RTL8814A		= 10,
++	BT_RTL8812A		= 11,
++	BT_RTL8703B		= 12,
++	BT_RTL8822B		= 13,
++	BT_RTL8723D		= 14,
++	BT_RTL8821C		= 15,
++	BT_RTL8192F		= 16,
++	BT_RTL8822C		= 17,
++	BT_RTL8814B		= 18,
++} BT_CoType, *PBT_CoType;
++
++typedef	enum _BT_RadioShared {
++	BT_Radio_Shared	= 0,
++	BT_Radio_Individual	= 1,
++} BT_RadioShared, *PBT_RadioShared;
++
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_phy.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_phy.h
+new file mode 100644
+index 000000000..35f901a49
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_phy.h
+@@ -0,0 +1,234 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL_PHY_H__
++#define __HAL_PHY_H__
++
++
++#if DISABLE_BB_RF
++	#define	HAL_FW_ENABLE				0
++	#define	HAL_MAC_ENABLE			0
++	#define	HAL_BB_ENABLE				0
++	#define	HAL_RF_ENABLE				0
++#else /* FPGA_PHY and ASIC */
++	#define	HAL_FW_ENABLE				1
++	#define	HAL_MAC_ENABLE			1
++	#define	HAL_BB_ENABLE				1
++	#define	HAL_RF_ENABLE				1
++#endif
++
++#define	RF6052_MAX_TX_PWR			0x3F
++#define	RF6052_MAX_REG_88E			0xFF
++#define	RF6052_MAX_REG_92C			0x7F
++
++#define	RF6052_MAX_REG	\
++	((RF6052_MAX_REG_88E > RF6052_MAX_REG_92C) ? RF6052_MAX_REG_88E : RF6052_MAX_REG_92C)
++
++#define GET_RF6052_REAL_MAX_REG(_Adapter)	\
++	(IS_HARDWARE_TYPE_8188E(_Adapter) ? RF6052_MAX_REG_88E : RF6052_MAX_REG_92C)
++
++#define	RF6052_MAX_PATH				2
++
++/*
++ * Antenna detection method, i.e., using single tone detection or RSSI reported from each antenna detected.
++ * Added by Roger, 2013.05.22.
++ *   */
++#define ANT_DETECT_BY_SINGLE_TONE	BIT0
++#define ANT_DETECT_BY_RSSI				BIT1
++#define IS_ANT_DETECT_SUPPORT_SINGLE_TONE(__Adapter)		((GET_HAL_DATA(__Adapter)->AntDetection) & ANT_DETECT_BY_SINGLE_TONE)
++#define IS_ANT_DETECT_SUPPORT_RSSI(__Adapter)		((GET_HAL_DATA(__Adapter)->AntDetection) & ANT_DETECT_BY_RSSI)
++
++
++/*--------------------------Define Parameters-------------------------------*/
++typedef	enum _RF_CHIP {
++	RF_CHIP_MIN = 0,	/* 0 */
++	RF_8225 = 1,			/* 1 11b/g RF for verification only */
++	RF_8256 = 2,			/* 2 11b/g/n */
++	RF_8258 = 3,			/* 3 11a/b/g/n RF */
++	RF_6052 = 4,			/* 4 11b/g/n RF */
++	RF_PSEUDO_11N = 5,	/* 5, It is a temporality RF. */
++	RF_CHIP_MAX
++} RF_CHIP_E, *PRF_CHIP_E;
++
++typedef enum _ANTENNA_PATH {
++	ANTENNA_NONE	= 0,
++	ANTENNA_D		= 1,
++	ANTENNA_C		= 2,
++	ANTENNA_CD	= 3,
++	ANTENNA_B		= 4,
++	ANTENNA_BD	= 5,
++	ANTENNA_BC	= 6,
++	ANTENNA_BCD	= 7,
++	ANTENNA_A		= 8,
++	ANTENNA_AD	= 9,
++	ANTENNA_AC	= 10,
++	ANTENNA_ACD	= 11,
++	ANTENNA_AB	= 12,
++	ANTENNA_ABD	= 13,
++	ANTENNA_ABC	= 14,
++	ANTENNA_ABCD	= 15
++} ANTENNA_PATH;
++
++typedef enum _RF_CONTENT {
++	radioa_txt = 0x1000,
++	radiob_txt = 0x1001,
++	radioc_txt = 0x1002,
++	radiod_txt = 0x1003
++} RF_CONTENT;
++
++typedef enum _BaseBand_Config_Type {
++	BaseBand_Config_PHY_REG = 0,			/* Radio Path A */
++	BaseBand_Config_AGC_TAB = 1,			/* Radio Path B */
++	BaseBand_Config_AGC_TAB_2G = 2,
++	BaseBand_Config_AGC_TAB_5G = 3,
++	BaseBand_Config_PHY_REG_PG
++} BaseBand_Config_Type, *PBaseBand_Config_Type;
++
++typedef enum _HW_BLOCK {
++	HW_BLOCK_MAC = 0,
++	HW_BLOCK_PHY0 = 1,
++	HW_BLOCK_PHY1 = 2,
++	HW_BLOCK_RF = 3,
++	HW_BLOCK_MAXIMUM = 4, /* Never use this */
++} HW_BLOCK_E, *PHW_BLOCK_E;
++
++typedef enum _WIRELESS_MODE {
++	WIRELESS_MODE_UNKNOWN = 0x00,
++	WIRELESS_MODE_A = 0x01,
++	WIRELESS_MODE_B = 0x02,
++	WIRELESS_MODE_G = 0x04,
++	WIRELESS_MODE_AUTO = 0x08,
++	WIRELESS_MODE_N_24G = 0x10,
++	WIRELESS_MODE_N_5G = 0x20,
++	WIRELESS_MODE_AC_5G = 0x40,
++	WIRELESS_MODE_AC_24G  = 0x80,
++	WIRELESS_MODE_AC_ONLY  = 0x100,
++} WIRELESS_MODE;
++
++typedef enum _SwChnlCmdID {
++	CmdID_End,
++	CmdID_SetTxPowerLevel,
++	CmdID_BBRegWrite10,
++	CmdID_WritePortUlong,
++	CmdID_WritePortUshort,
++	CmdID_WritePortUchar,
++	CmdID_RF_WriteReg,
++} SwChnlCmdID;
++
++typedef struct _SwChnlCmd {
++	SwChnlCmdID	CmdID;
++	u32				Para1;
++	u32				Para2;
++	u32				msDelay;
++} SwChnlCmd;
++
++typedef struct _R_ANTENNA_SELECT_OFDM {
++	u32			r_tx_antenna:4;
++	u32			r_ant_l:4;
++	u32			r_ant_non_ht:4;
++	u32			r_ant_ht1:4;
++	u32			r_ant_ht2:4;
++	u32			r_ant_ht_s1:4;
++	u32			r_ant_non_ht_s1:4;
++	u32			OFDM_TXSC:2;
++	u32			Reserved:2;
++} R_ANTENNA_SELECT_OFDM;
++
++typedef struct _R_ANTENNA_SELECT_CCK {
++	u8			r_cckrx_enable_2:2;
++	u8			r_cckrx_enable:2;
++	u8			r_ccktx_enable:4;
++} R_ANTENNA_SELECT_CCK;
++
++
++/*--------------------------Exported Function prototype---------------------*/
++u32
++PHY_CalculateBitShift(
++	u32 BitMask
++);
++
++#ifdef CONFIG_RF_SHADOW_RW
++typedef struct RF_Shadow_Compare_Map {
++	/* Shadow register value */
++	u32		Value;
++	/* Compare or not flag */
++	u8		Compare;
++	/* Record If it had ever modified unpredicted */
++	u8		ErrorOrNot;
++	/* Recorver Flag */
++	u8		Recorver;
++	/*  */
++	u8		Driver_Write;
++} RF_SHADOW_T;
++
++u32
++PHY_RFShadowRead(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				Offset);
++
++void
++PHY_RFShadowWrite(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				Offset,
++		u32				Data);
++
++BOOLEAN
++PHY_RFShadowCompare(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				Offset);
++
++void
++PHY_RFShadowRecorver(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				Offset);
++
++void
++PHY_RFShadowCompareAll(
++		PADAPTER		Adapter);
++
++void
++PHY_RFShadowRecorverAll(
++		PADAPTER		Adapter);
++
++void
++PHY_RFShadowCompareFlagSet(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				Offset,
++		u8				Type);
++
++void
++PHY_RFShadowRecorverFlagSet(
++		PADAPTER		Adapter,
++		enum rf_path		eRFPath,
++		u32				Offset,
++		u8				Type);
++
++void
++PHY_RFShadowCompareFlagSetAll(
++		PADAPTER		Adapter);
++
++void
++PHY_RFShadowRecorverFlagSetAll(
++		PADAPTER		Adapter);
++
++void
++PHY_RFShadowRefresh(
++		PADAPTER		Adapter);
++#endif /*#CONFIG_RF_SHADOW_RW*/
++#endif /* __HAL_COMMON_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_phy_reg.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_phy_reg.h
+new file mode 100644
+index 000000000..13d77ab41
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_phy_reg.h
+@@ -0,0 +1,270 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL_PHY_REG_H__
++#define __HAL_PHY_REG_H__
++
++/* for PutRFRegsetting & GetRFRegSetting BitMask*/
++#define		bRFRegOffsetMask	0xfffff
++
++/* alias for phydm coding style */
++#define REG_OFDM_0_XA_TX_IQ_IMBALANCE	rOFDM0_XATxIQImbalance
++#define REG_OFDM_0_ECCA_THRESHOLD		rOFDM0_ECCAThreshold
++#define REG_FPGA0_XB_LSSI_READ_BACK		rFPGA0_XB_LSSIReadBack
++#define REG_FPGA0_TX_GAIN_STAGE			rFPGA0_TxGainStage
++#define REG_OFDM_0_XA_AGC_CORE1			rOFDM0_XAAGCCore1
++#define REG_OFDM_0_XB_AGC_CORE1			rOFDM0_XBAGCCore1
++#define REG_A_TX_SCALE_JAGUAR			rA_TxScale_Jaguar
++#define REG_B_TX_SCALE_JAGUAR			rB_TxScale_Jaguar
++
++#define REG_FPGA0_XAB_RF_INTERFACE_SW	rFPGA0_XAB_RFInterfaceSW
++#define REG_FPGA0_XAB_RF_PARAMETER	rFPGA0_XAB_RFParameter
++#define REG_FPGA0_XA_HSSI_PARAMETER1	rFPGA0_XA_HSSIParameter1
++#define REG_FPGA0_XA_LSSI_PARAMETER	rFPGA0_XA_LSSIParameter
++#define REG_FPGA0_XA_RF_INTERFACE_OE	rFPGA0_XA_RFInterfaceOE
++#define REG_FPGA0_XB_HSSI_PARAMETER1	rFPGA0_XB_HSSIParameter1
++#define REG_FPGA0_XB_LSSI_PARAMETER	rFPGA0_XB_LSSIParameter
++#define REG_FPGA0_XB_LSSI_READ_BACK	rFPGA0_XB_LSSIReadBack
++#define REG_FPGA0_XB_RF_INTERFACE_OE	rFPGA0_XB_RFInterfaceOE
++#define REG_FPGA0_XCD_RF_INTERFACE_SW	rFPGA0_XCD_RFInterfaceSW
++#define REG_FPGA0_XCD_SWITCH_CONTROL	rFPGA0_XCD_SwitchControl
++#define REG_FPGA1_TX_BLOCK	rFPGA1_TxBlock
++#define REG_FPGA1_TX_INFO	rFPGA1_TxInfo
++#define REG_IQK_AGC_CONT	rIQK_AGC_Cont
++#define REG_IQK_AGC_PTS	rIQK_AGC_Pts
++#define REG_IQK_AGC_RSP	rIQK_AGC_Rsp
++#define REG_OFDM_0_AGC_RSSI_TABLE	rOFDM0_AGCRSSITable
++#define REG_OFDM_0_ECCA_THRESHOLD	rOFDM0_ECCAThreshold
++#define REG_OFDM_0_RX_IQ_EXT_ANTA	rOFDM0_RxIQExtAnta
++#define REG_OFDM_0_TR_MUX_PAR	rOFDM0_TRMuxPar
++#define REG_OFDM_0_TRX_PATH_ENABLE	rOFDM0_TRxPathEnable
++#define REG_OFDM_0_XA_AGC_CORE1	rOFDM0_XAAGCCore1
++#define REG_OFDM_0_XA_RX_IQ_IMBALANCE	rOFDM0_XARxIQImbalance
++#define REG_OFDM_0_XA_TX_IQ_IMBALANCE	rOFDM0_XATxIQImbalance
++#define REG_OFDM_0_XB_AGC_CORE1	rOFDM0_XBAGCCore1
++#define REG_OFDM_0_XB_RX_IQ_IMBALANCE	rOFDM0_XBRxIQImbalance
++#define REG_OFDM_0_XB_TX_IQ_IMBALANCE	rOFDM0_XBTxIQImbalance
++#define REG_OFDM_0_XC_TX_AFE	rOFDM0_XCTxAFE
++#define REG_OFDM_0_XD_TX_AFE	rOFDM0_XDTxAFE
++
++/*#define REG_A_CFO_LONG_DUMP_92E	rA_CfoLongDump_92E*/
++#define REG_A_CFO_LONG_DUMP_JAGUAR	rA_CfoLongDump_Jaguar
++/*#define REG_A_CFO_SHORT_DUMP_92E	rA_CfoShortDump_92E*/
++#define REG_A_CFO_SHORT_DUMP_JAGUAR	rA_CfoShortDump_Jaguar
++#define REG_A_RFE_PINMUX_JAGUAR	rA_RFE_Pinmux_Jaguar
++/*#define REG_A_RSSI_DUMP_92E	rA_RSSIDump_92E*/
++#define REG_A_RSSI_DUMP_JAGUAR	rA_RSSIDump_Jaguar
++/*#define REG_A_RX_SNR_DUMP_92E	rA_RXsnrDump_92E*/
++#define REG_A_RX_SNR_DUMP_JAGUAR	rA_RXsnrDump_Jaguar
++/*#define REG_A_TX_AGC	rA_TXAGC*/
++#define REG_A_TX_SCALE_JAGUAR	rA_TxScale_Jaguar
++#define REG_BW_INDICATION_JAGUAR	rBWIndication_Jaguar
++/*#define REG_B_BBSWING	rB_BBSWING*/
++/*#define REG_B_CFO_LONG_DUMP_92E	rB_CfoLongDump_92E*/
++#define REG_B_CFO_LONG_DUMP_JAGUAR	rB_CfoLongDump_Jaguar
++/*#define REG_B_CFO_SHORT_DUMP_92E	rB_CfoShortDump_92E*/
++#define REG_B_CFO_SHORT_DUMP_JAGUAR	rB_CfoShortDump_Jaguar
++/*#define REG_B_RSSI_DUMP_92E	rB_RSSIDump_92E*/
++#define REG_B_RSSI_DUMP_JAGUAR	rB_RSSIDump_Jaguar
++/*#define REG_B_RX_SNR_DUMP_92E	rB_RXsnrDump_92E*/
++#define REG_B_RX_SNR_DUMP_JAGUAR	rB_RXsnrDump_Jaguar
++/*#define REG_B_TX_AGC	rB_TXAGC*/
++#define REG_B_TX_SCALE_JAGUAR	rB_TxScale_Jaguar
++#define REG_BLUE_TOOTH	rBlue_Tooth
++#define REG_CCK_0_AFE_SETTING	rCCK0_AFESetting
++/*#define REG_C_BBSWING	rC_BBSWING*/
++/*#define REG_C_TX_AGC	rC_TXAGC*/
++#define REG_C_TX_SCALE_JAGUAR2	rC_TxScale_Jaguar2
++#define REG_CONFIG_ANT_A	rConfig_AntA
++#define REG_CONFIG_ANT_B	rConfig_AntB
++#define REG_CONFIG_PMPD_ANT_A	rConfig_Pmpd_AntA
++#define REG_CONFIG_PMPD_ANT_B	rConfig_Pmpd_AntB
++#define REG_DPDT_CONTROL	rDPDT_control
++/*#define REG_D_BBSWING	rD_BBSWING*/
++/*#define REG_D_TX_AGC	rD_TXAGC*/
++#define REG_D_TX_SCALE_JAGUAR2	rD_TxScale_Jaguar2
++#define REG_FPGA0_ANALOG_PARAMETER4	rFPGA0_AnalogParameter4
++#define REG_FPGA0_IQK	rFPGA0_IQK
++#define REG_FPGA0_PSD_FUNCTION	rFPGA0_PSDFunction
++#define REG_FPGA0_PSD_REPORT	rFPGA0_PSDReport
++#define REG_FPGA0_RFMOD	rFPGA0_RFMOD
++#define REG_FPGA0_TX_GAIN_STAGE	rFPGA0_TxGainStage
++#define REG_FPGA0_XAB_RF_INTERFACE_SW	rFPGA0_XAB_RFInterfaceSW
++#define REG_FPGA0_XAB_RF_PARAMETER	rFPGA0_XAB_RFParameter
++#define REG_FPGA0_XA_HSSI_PARAMETER1	rFPGA0_XA_HSSIParameter1
++#define REG_FPGA0_XA_LSSI_PARAMETER	rFPGA0_XA_LSSIParameter
++#define REG_FPGA0_XA_RF_INTERFACE_OE	rFPGA0_XA_RFInterfaceOE
++#define REG_FPGA0_XB_HSSI_PARAMETER1	rFPGA0_XB_HSSIParameter1
++#define REG_FPGA0_XB_LSSI_PARAMETER	rFPGA0_XB_LSSIParameter
++#define REG_FPGA0_XB_LSSI_READ_BACK	rFPGA0_XB_LSSIReadBack
++#define REG_FPGA0_XB_RF_INTERFACE_OE	rFPGA0_XB_RFInterfaceOE
++#define REG_FPGA0_XCD_RF_INTERFACE_SW	rFPGA0_XCD_RFInterfaceSW
++#define REG_FPGA0_XCD_SWITCH_CONTROL	rFPGA0_XCD_SwitchControl
++#define REG_FPGA1_TX_BLOCK	rFPGA1_TxBlock
++#define REG_FPGA1_TX_INFO	rFPGA1_TxInfo
++#define REG_IQK_AGC_CONT	rIQK_AGC_Cont
++#define REG_IQK_AGC_PTS	rIQK_AGC_Pts
++#define REG_IQK_AGC_RSP	rIQK_AGC_Rsp
++#define REG_OFDM_0_AGC_RSSI_TABLE	rOFDM0_AGCRSSITable
++#define REG_OFDM_0_ECCA_THRESHOLD	rOFDM0_ECCAThreshold
++#define REG_OFDM_0_RX_IQ_EXT_ANTA	rOFDM0_RxIQExtAnta
++#define REG_OFDM_0_TR_MUX_PAR	rOFDM0_TRMuxPar
++#define REG_OFDM_0_TRX_PATH_ENABLE	rOFDM0_TRxPathEnable
++#define REG_OFDM_0_XA_AGC_CORE1	rOFDM0_XAAGCCore1
++#define REG_OFDM_0_XA_RX_IQ_IMBALANCE	rOFDM0_XARxIQImbalance
++#define REG_OFDM_0_XA_TX_IQ_IMBALANCE	rOFDM0_XATxIQImbalance
++#define REG_OFDM_0_XB_AGC_CORE1	rOFDM0_XBAGCCore1
++#define REG_OFDM_0_XB_RX_IQ_IMBALANCE	rOFDM0_XBRxIQImbalance
++#define REG_OFDM_0_XB_TX_IQ_IMBALANCE	rOFDM0_XBTxIQImbalance
++#define REG_OFDM_0_XC_TX_AFE	rOFDM0_XCTxAFE
++#define REG_OFDM_0_XD_TX_AFE	rOFDM0_XDTxAFE
++#define REG_PMPD_ANAEN	rPMPD_ANAEN
++#define REG_PDP_ANT_A	rPdp_AntA
++#define REG_PDP_ANT_A_4	rPdp_AntA_4
++#define REG_PDP_ANT_B	rPdp_AntB
++#define REG_PDP_ANT_B_4	rPdp_AntB_4
++#define REG_PWED_TH_JAGUAR	rPwed_TH_Jaguar
++#define REG_RX_CCK	rRx_CCK
++#define REG_RX_IQK	rRx_IQK
++#define REG_RX_IQK_PI_A	rRx_IQK_PI_A
++#define REG_RX_IQK_PI_B	rRx_IQK_PI_B
++#define REG_RX_IQK_TONE_A	rRx_IQK_Tone_A
++#define REG_RX_IQK_TONE_B	rRx_IQK_Tone_B
++#define REG_RX_OFDM	rRx_OFDM
++#define REG_RX_POWER_AFTER_IQK_A_2	rRx_Power_After_IQK_A_2
++#define REG_RX_POWER_AFTER_IQK_B_2	rRx_Power_After_IQK_B_2
++#define REG_RX_POWER_BEFORE_IQK_A_2	rRx_Power_Before_IQK_A_2
++#define REG_RX_POWER_BEFORE_IQK_B_2	rRx_Power_Before_IQK_B_2
++#define REG_RX_TO_RX	rRx_TO_Rx
++#define REG_RX_WAIT_CCA	rRx_Wait_CCA
++#define REG_RX_WAIT_RIFS	rRx_Wait_RIFS
++#define REG_S0_S1_PATH_SWITCH	rS0S1_PathSwitch
++/*#define REG_S1_RXEVM_DUMP_92E	rS1_RXevmDump_92E*/
++#define REG_S1_RXEVM_DUMP_JAGUAR	rS1_RXevmDump_Jaguar
++/*#define REG_S2_RXEVM_DUMP_92E	rS2_RXevmDump_92E*/
++#define REG_S2_RXEVM_DUMP_JAGUAR	rS2_RXevmDump_Jaguar
++#define REG_SYM_WLBT_PAPE_SEL	rSYM_WLBT_PAPE_SEL
++#define REG_SINGLE_TONE_CONT_TX_JAGUAR	rSingleTone_ContTx_Jaguar
++#define REG_SLEEP	rSleep
++#define REG_STANDBY	rStandby
++#define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR	rTxAGC_A_CCK11_CCK1_JAguar
++#define REG_TX_AGC_A_CCK_1_MCS32	rTxAGC_A_CCK1_Mcs32
++#define REG_TX_AGC_A_MCS11_MCS8_JAGUAR	rTxAGC_A_MCS11_MCS8_JAguar
++#define REG_TX_AGC_A_MCS15_MCS12_JAGUAR	rTxAGC_A_MCS15_MCS12_JAguar
++#define REG_TX_AGC_A_MCS19_MCS16_JAGUAR	rTxAGC_A_MCS19_MCS16_JAguar
++#define REG_TX_AGC_A_MCS23_MCS20_JAGUAR	rTxAGC_A_MCS23_MCS20_JAguar
++#define REG_TX_AGC_A_MCS3_MCS0_JAGUAR	rTxAGC_A_MCS3_MCS0_JAguar
++#define REG_TX_AGC_A_MCS7_MCS4_JAGUAR	rTxAGC_A_MCS7_MCS4_JAguar
++#define REG_TX_AGC_A_MCS03_MCS00	rTxAGC_A_Mcs03_Mcs00
++#define REG_TX_AGC_A_MCS07_MCS04	rTxAGC_A_Mcs07_Mcs04
++#define REG_TX_AGC_A_MCS11_MCS08	rTxAGC_A_Mcs11_Mcs08
++#define REG_TX_AGC_A_MCS15_MCS12	rTxAGC_A_Mcs15_Mcs12
++#define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	rTxAGC_A_Nss1Index3_Nss1Index0_JAguar
++#define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	rTxAGC_A_Nss1Index7_Nss1Index4_JAguar
++#define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	rTxAGC_A_Nss2Index1_Nss1Index8_JAguar
++#define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	rTxAGC_A_Nss2Index5_Nss2Index2_JAguar
++#define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	rTxAGC_A_Nss2Index9_Nss2Index6_JAguar
++#define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	rTxAGC_A_Nss3Index3_Nss3Index0_JAguar
++#define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	rTxAGC_A_Nss3Index7_Nss3Index4_JAguar
++#define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	rTxAGC_A_Nss3Index9_Nss3Index8_JAguar
++#define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR	rTxAGC_A_Ofdm18_Ofdm6_JAguar
++#define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR	rTxAGC_A_Ofdm54_Ofdm24_JAguar
++#define REG_TX_AGC_A_RATE18_06	rTxAGC_A_Rate18_06
++#define REG_TX_AGC_A_RATE54_24	rTxAGC_A_Rate54_24
++#define REG_TX_AGC_B_CCK_11_A_CCK_2_11	rTxAGC_B_CCK11_A_CCK2_11
++#define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR	rTxAGC_B_CCK11_CCK1_JAguar
++#define REG_TX_AGC_B_CCK_1_55_MCS32	rTxAGC_B_CCK1_55_Mcs32
++#define REG_TX_AGC_B_MCS11_MCS8_JAGUAR	rTxAGC_B_MCS11_MCS8_JAguar
++#define REG_TX_AGC_B_MCS15_MCS12_JAGUAR	rTxAGC_B_MCS15_MCS12_JAguar
++#define REG_TX_AGC_B_MCS19_MCS16_JAGUAR	rTxAGC_B_MCS19_MCS16_JAguar
++#define REG_TX_AGC_B_MCS23_MCS20_JAGUAR	rTxAGC_B_MCS23_MCS20_JAguar
++#define REG_TX_AGC_B_MCS3_MCS0_JAGUAR	rTxAGC_B_MCS3_MCS0_JAguar
++#define REG_TX_AGC_B_MCS7_MCS4_JAGUAR	rTxAGC_B_MCS7_MCS4_JAguar
++#define REG_TX_AGC_B_MCS03_MCS00	rTxAGC_B_Mcs03_Mcs00
++#define REG_TX_AGC_B_MCS07_MCS04	rTxAGC_B_Mcs07_Mcs04
++#define REG_TX_AGC_B_MCS11_MCS08	rTxAGC_B_Mcs11_Mcs08
++#define REG_TX_AGC_B_MCS15_MCS12	rTxAGC_B_Mcs15_Mcs12
++#define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	rTxAGC_B_Nss1Index3_Nss1Index0_JAguar
++#define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	rTxAGC_B_Nss1Index7_Nss1Index4_JAguar
++#define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	rTxAGC_B_Nss2Index1_Nss1Index8_JAguar
++#define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	rTxAGC_B_Nss2Index5_Nss2Index2_JAguar
++#define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	rTxAGC_B_Nss2Index9_Nss2Index6_JAguar
++#define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	rTxAGC_B_Nss3Index3_Nss3Index0_JAguar
++#define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	rTxAGC_B_Nss3Index7_Nss3Index4_JAguar
++#define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	rTxAGC_B_Nss3Index9_Nss3Index8_JAguar
++#define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR	rTxAGC_B_Ofdm18_Ofdm6_JAguar
++#define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR	rTxAGC_B_Ofdm54_Ofdm24_JAguar
++#define REG_TX_AGC_B_RATE18_06	rTxAGC_B_Rate18_06
++#define REG_TX_AGC_B_RATE54_24	rTxAGC_B_Rate54_24
++#define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR	rTxAGC_C_CCK11_CCK1_JAguar
++#define REG_TX_AGC_C_MCS11_MCS8_JAGUAR	rTxAGC_C_MCS11_MCS8_JAguar
++#define REG_TX_AGC_C_MCS15_MCS12_JAGUAR	rTxAGC_C_MCS15_MCS12_JAguar
++#define REG_TX_AGC_C_MCS19_MCS16_JAGUAR	rTxAGC_C_MCS19_MCS16_JAguar
++#define REG_TX_AGC_C_MCS23_MCS20_JAGUAR	rTxAGC_C_MCS23_MCS20_JAguar
++#define REG_TX_AGC_C_MCS3_MCS0_JAGUAR	rTxAGC_C_MCS3_MCS0_JAguar
++#define REG_TX_AGC_C_MCS7_MCS4_JAGUAR	rTxAGC_C_MCS7_MCS4_JAguar
++#define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	rTxAGC_C_Nss1Index3_Nss1Index0_JAguar
++#define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	rTxAGC_C_Nss1Index7_Nss1Index4_JAguar
++#define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	rTxAGC_C_Nss2Index1_Nss1Index8_JAguar
++#define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	rTxAGC_C_Nss2Index5_Nss2Index2_JAguar
++#define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	rTxAGC_C_Nss2Index9_Nss2Index6_JAguar
++#define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	rTxAGC_C_Nss3Index3_Nss3Index0_JAguar
++#define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	rTxAGC_C_Nss3Index7_Nss3Index4_JAguar
++#define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	rTxAGC_C_Nss3Index9_Nss3Index8_JAguar
++#define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR	rTxAGC_C_Ofdm18_Ofdm6_JAguar
++#define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR	rTxAGC_C_Ofdm54_Ofdm24_JAguar
++#define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR	rTxAGC_D_CCK11_CCK1_JAguar
++#define REG_TX_AGC_D_MCS11_MCS8_JAGUAR	rTxAGC_D_MCS11_MCS8_JAguar
++#define REG_TX_AGC_D_MCS15_MCS12_JAGUAR	rTxAGC_D_MCS15_MCS12_JAguar
++#define REG_TX_AGC_D_MCS19_MCS16_JAGUAR	rTxAGC_D_MCS19_MCS16_JAguar
++#define REG_TX_AGC_D_MCS23_MCS20_JAGUAR	rTxAGC_D_MCS23_MCS20_JAguar
++#define REG_TX_AGC_D_MCS3_MCS0_JAGUAR	rTxAGC_D_MCS3_MCS0_JAguar
++#define REG_TX_AGC_D_MCS7_MCS4_JAGUAR	rTxAGC_D_MCS7_MCS4_JAguar
++#define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	rTxAGC_D_Nss1Index3_Nss1Index0_JAguar
++#define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	rTxAGC_D_Nss1Index7_Nss1Index4_JAguar
++#define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	rTxAGC_D_Nss2Index1_Nss1Index8_JAguar
++#define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	rTxAGC_D_Nss2Index5_Nss2Index2_JAguar
++#define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	rTxAGC_D_Nss2Index9_Nss2Index6_JAguar
++#define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	rTxAGC_D_Nss3Index3_Nss3Index0_JAguar
++#define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	rTxAGC_D_Nss3Index7_Nss3Index4_JAguar
++#define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	rTxAGC_D_Nss3Index9_Nss3Index8_JAguar
++#define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR	rTxAGC_D_Ofdm18_Ofdm6_JAguar
++#define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR	rTxAGC_D_Ofdm54_Ofdm24_JAguar
++#define REG_TX_PATH_JAGUAR	rTxPath_Jaguar
++#define REG_TX_CCK_BBON	rTx_CCK_BBON
++#define REG_TX_CCK_RFON	rTx_CCK_RFON
++#define REG_TX_IQK	rTx_IQK
++#define REG_TX_IQK_PI_A	rTx_IQK_PI_A
++#define REG_TX_IQK_PI_B	rTx_IQK_PI_B
++#define REG_TX_IQK_TONE_A	rTx_IQK_Tone_A
++#define REG_TX_IQK_TONE_B	rTx_IQK_Tone_B
++#define REG_TX_OFDM_BBON	rTx_OFDM_BBON
++#define REG_TX_OFDM_RFON	rTx_OFDM_RFON
++#define REG_TX_POWER_AFTER_IQK_A	rTx_Power_After_IQK_A
++#define REG_TX_POWER_AFTER_IQK_B	rTx_Power_After_IQK_B
++#define REG_TX_POWER_BEFORE_IQK_A	rTx_Power_Before_IQK_A
++#define REG_TX_POWER_BEFORE_IQK_B	rTx_Power_Before_IQK_B
++#define REG_TX_TO_RX	rTx_To_Rx
++#define REG_TX_TO_TX	rTx_To_Tx
++#define REG_APK	rAPK
++#define REG_ANTSEL_SW_JAGUAR	r_ANTSEL_SW_Jaguar
++
++#define rf_welut_jaguar	RF_WeLut_Jaguar
++#define rf_mode_table_addr	RF_ModeTableAddr
++#define rf_mode_table_data0	RF_ModeTableData0
++#define rf_mode_table_data1	RF_ModeTableData1
++
++#define RX_SMOOTH_FACTOR	Rx_Smooth_Factor
++
++#endif /* __HAL_PHY_REG_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_sdio.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_sdio.h
+new file mode 100644
+index 000000000..0b896fb1e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_sdio.h
+@@ -0,0 +1,84 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL_SDIO_H_
++#define __HAL_SDIO_H_
++
++#define ffaddr2deviceId(pdvobj, addr)	(pdvobj->Queue2Pipe[addr])
++
++#ifndef RTW_HALMAC
++extern const char *_sdio_tx_queue_str[];
++#define sdio_tx_queue_str(_page_idx) (_page_idx >= SDIO_MAX_TX_QUEUE ? "UNKNOWN" : _sdio_tx_queue_str[_page_idx])
++#endif
++
++u8 rtw_hal_sdio_max_txoqt_free_space(_adapter *padapter);
++u8 rtw_hal_sdio_query_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
++void rtw_hal_sdio_update_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
++void rtw_hal_set_sdio_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ, u8 div_num);
++u32 rtw_hal_get_sdio_tx_max_length(PADAPTER padapter, u8 queue_idx);
++bool sdio_power_on_check(PADAPTER padapter);
++
++#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
++#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) ||defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8723D)
++void rtw_hal_sdio_avail_page_threshold_init(_adapter *adapter);
++void rtw_hal_sdio_avail_page_threshold_en(_adapter *adapter, u8 qidx, u8 pg_num);
++#endif
++#endif /* CONFIG_SDIO_TX_ENABLE_AVAL_INT */
++
++#ifdef CONFIG_FW_C2H_REG
++void sd_c2h_hisr_hdl(_adapter *adapter);
++#endif
++
++#if defined(CONFIG_RTL8188F) || defined (CONFIG_RTL8188GTV) || defined (CONFIG_RTL8192F) || defined(CONFIG_RTL8723D)
++#define SDIO_LOCAL_CMD_ADDR(addr) ((SDIO_LOCAL_DEVICE_ID << 13) | ((addr) & SDIO_LOCAL_MSK))
++#endif
++
++#ifdef CONFIG_SDIO_CHK_HCI_RESUME
++bool sdio_chk_hci_resume(struct intf_hdl *pintfhdl);
++void sdio_chk_hci_suspend(struct intf_hdl *pintfhdl);
++#else
++#define sdio_chk_hci_resume(pintfhdl) _FALSE
++#define sdio_chk_hci_suspend(pintfhdl) do {} while (0)
++#endif /* CONFIG_SDIO_CHK_HCI_RESUME */
++
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++/* program indirect access register in sdio local to read/write page0 registers */
++s32 sdio_iread(PADAPTER padapter, u32 addr, u8 size, u8 *v);
++s32 sdio_iwrite(PADAPTER padapter, u32 addr, u8 size, u8 *v);
++u8 sdio_iread8(struct intf_hdl *pintfhdl, u32 addr);
++u16 sdio_iread16(struct intf_hdl *pintfhdl, u32 addr);
++u32 sdio_iread32(struct intf_hdl *pintfhdl, u32 addr);
++s32 sdio_iwrite8(struct intf_hdl *pintfhdl, u32 addr, u8 val);
++s32 sdio_iwrite16(struct intf_hdl *pintfhdl, u32 addr, u16 val);
++s32 sdio_iwrite32(struct intf_hdl *pintfhdl, u32 addr, u32 val);
++#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
++u32 cmd53_4byte_alignment(struct intf_hdl *pintfhdl, u32 addr);
++
++#ifndef CONFIG_SDIO_TX_TASKLET
++#ifdef SDIO_FREE_XMIT_BUF_SEMA
++void _rtw_sdio_free_xmitbuf_sema_up(struct xmit_priv *xmit);
++void _rtw_sdio_free_xmitbuf_sema_down(struct xmit_priv *xmit);
++#ifdef DBG_SDIO_FREE_XMIT_BUF_SEMA
++void dbg_rtw_sdio_free_xmitbuf_sema_up(struct xmit_priv *xmit, const char *caller);
++void dbg_rtw_sdio_free_xmitbuf_sema_down(struct xmit_priv *xmit, const char *caller);
++#define rtw_sdio_free_xmitbuf_sema_up(_xmit) dbg_rtw_sdio_free_xmitbuf_sema_up(_xmit, __func__)
++#define rtw_sdio_free_xmitbuf_sema_down(_xmit) dbg_rtw_sdio_free_xmitbuf_sema_down(_xmit, __func__)
++#else
++#define rtw_sdio_free_xmitbuf_sema_up(_xmit) _rtw_sdio_free_xmitbuf_sema_up(_xmit)
++#define rtw_sdio_free_xmitbuf_sema_down(_xmit) _rtw_sdio_free_xmitbuf_sema_down(_xmit)
++#endif /* DBG_SDIO_FREE_XMIT_BUF_SEMA */
++#endif /* SDIO_FREE_XMIT_BUF_SEMA */
++#endif /* !CONFIG_SDIO_TX_TASKLET */
++
++#endif /* __HAL_SDIO_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_sdio_coex.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_sdio_coex.h
+new file mode 100644
+index 000000000..ce41b9988
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/hal_sdio_coex.h
+@@ -0,0 +1,41 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __HAL_SDIO_COEX_H__
++#define __HAL_SDIO_COEX_H__
++
++#include <drv_types.h>
++
++#ifdef CONFIG_SDIO_MULTI_FUNCTION_COEX
++
++enum { /* for sdio multi-func. coex */
++	SDIO_MULTI_WIFI = 0,
++	SDIO_MULTI_BT,
++	SDIO_MULTI_NUM
++};
++
++bool ex_hal_sdio_multi_if_bus_available(PADAPTER adapter);
++
++#else
++
++#define ex_hal_sdio_multi_if_bus_available(adapter) TRUE
++
++#endif  /* CONFIG_SDIO_MULTI_FUNCTION_COEX */
++#endif  /* !__HAL_SDIO_COEX_H__ */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/ieee80211.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/ieee80211.h
+new file mode 100755
+index 000000000..21f07e63a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/ieee80211.h
+@@ -0,0 +1,2045 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __IEEE80211_H
++#define __IEEE80211_H
++
++#define MGMT_QUEUE_NUM 5
++
++#define ETH_ALEN	6
++#define ETH_TYPE_LEN		2
++#define PAYLOAD_TYPE_LEN	1
++
++#define NET80211_TU_TO_US	1024		/* unit:us */
++#define DEFAULT_BCN_INTERVAL 100 /* 100 ms */
++
++#ifdef CONFIG_AP_MODE
++
++#define RTL_IOCTL_HOSTAPD (SIOCIWFIRSTPRIV + 28)
++
++/* RTL871X_IOCTL_HOSTAPD ioctl() cmd: */
++enum {
++	RTL871X_HOSTAPD_FLUSH = 1,
++	RTL871X_HOSTAPD_ADD_STA = 2,
++	RTL871X_HOSTAPD_REMOVE_STA = 3,
++	RTL871X_HOSTAPD_GET_INFO_STA = 4,
++	/* REMOVED: PRISM2_HOSTAPD_RESET_TXEXC_STA = 5, */
++	RTL871X_HOSTAPD_GET_WPAIE_STA = 5,
++	RTL871X_SET_ENCRYPTION = 6,
++	RTL871X_GET_ENCRYPTION = 7,
++	RTL871X_HOSTAPD_SET_FLAGS_STA = 8,
++	RTL871X_HOSTAPD_GET_RID = 9,
++	RTL871X_HOSTAPD_SET_RID = 10,
++	RTL871X_HOSTAPD_SET_ASSOC_AP_ADDR = 11,
++	RTL871X_HOSTAPD_SET_GENERIC_ELEMENT = 12,
++	RTL871X_HOSTAPD_MLME = 13,
++	RTL871X_HOSTAPD_SCAN_REQ = 14,
++	RTL871X_HOSTAPD_STA_CLEAR_STATS = 15,
++	RTL871X_HOSTAPD_SET_BEACON = 16,
++	RTL871X_HOSTAPD_SET_WPS_BEACON = 17,
++	RTL871X_HOSTAPD_SET_WPS_PROBE_RESP = 18,
++	RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP = 19,
++	RTL871X_HOSTAPD_SET_HIDDEN_SSID = 20,
++	RTL871X_HOSTAPD_SET_MACADDR_ACL = 21,
++	RTL871X_HOSTAPD_ACL_ADD_STA = 22,
++	RTL871X_HOSTAPD_ACL_REMOVE_STA = 23,
++};
++
++/* STA flags */
++#define WLAN_STA_AUTH BIT(0)
++#define WLAN_STA_ASSOC BIT(1)
++#define WLAN_STA_PS BIT(2)
++#define WLAN_STA_TIM BIT(3)
++#define WLAN_STA_PERM BIT(4)
++#define WLAN_STA_AUTHORIZED BIT(5)
++#define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */
++#define WLAN_STA_SHORT_PREAMBLE BIT(7)
++#define WLAN_STA_PREAUTH BIT(8)
++#define WLAN_STA_WME BIT(9)
++#define WLAN_STA_MFP BIT(10)
++#define WLAN_STA_HT BIT(11)
++#define WLAN_STA_WPS BIT(12)
++#define WLAN_STA_MAYBE_WPS BIT(13)
++#define WLAN_STA_VHT BIT(14)
++#define WLAN_STA_WDS BIT(15)
++#define WLAN_STA_MULTI_AP BIT(16)
++#define WLAN_STA_NONERP BIT(31)
++
++#endif
++
++#define IEEE_CMD_SET_WPA_PARAM			1
++#define IEEE_CMD_SET_WPA_IE				2
++#define IEEE_CMD_SET_ENCRYPTION			3
++#define IEEE_CMD_MLME						4
++
++#define IEEE_PARAM_WPA_ENABLED				1
++#define IEEE_PARAM_TKIP_COUNTERMEASURES		2
++#define IEEE_PARAM_DROP_UNENCRYPTED			3
++#define IEEE_PARAM_PRIVACY_INVOKED			4
++#define IEEE_PARAM_AUTH_ALGS					5
++#define IEEE_PARAM_IEEE_802_1X				6
++#define IEEE_PARAM_WPAX_SELECT				7
++
++#define AUTH_ALG_OPEN_SYSTEM			0x1
++#define AUTH_ALG_SHARED_KEY			0x2
++#define AUTH_ALG_LEAP				0x00000004
++
++#define IEEE_MLME_STA_DEAUTH				1
++#define IEEE_MLME_STA_DISASSOC			2
++
++#define IEEE_CRYPT_ERR_UNKNOWN_ALG			2
++#define IEEE_CRYPT_ERR_UNKNOWN_ADDR			3
++#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED		4
++#define IEEE_CRYPT_ERR_KEY_SET_FAILED			5
++#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED		6
++#define IEEE_CRYPT_ERR_CARD_CONF_FAILED		7
++
++
++#define	IEEE_CRYPT_ALG_NAME_LEN			16
++
++#define WPA_CIPHER_NONE	BIT(0)
++#define WPA_CIPHER_WEP40	BIT(1)
++#define WPA_CIPHER_WEP104 BIT(2)
++#define WPA_CIPHER_TKIP	BIT(3)
++#define WPA_CIPHER_CCMP	BIT(4)
++#define WPA_CIPHER_GCMP	BIT(5)
++#define WPA_CIPHER_GCMP_256	BIT(6)
++#define WPA_CIPHER_CCMP_256	BIT(7)
++#define WPA_CIPHER_BIP_CMAC_128	BIT(8)
++#define WPA_CIPHER_BIP_GMAC_128	BIT(9)
++#define WPA_CIPHER_BIP_GMAC_256	BIT(10)
++#define WPA_CIPHER_BIP_CMAC_256	BIT(11)
++
++
++#define WPA_SELECTOR_LEN 4
++extern u8 RTW_WPA_OUI_TYPE[] ;
++extern u16 RTW_WPA_VERSION ;
++extern u8 WPA_AUTH_KEY_MGMT_NONE[];
++extern u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[];
++extern u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[];
++extern u8 WPA_CIPHER_SUITE_NONE[];
++extern u8 WPA_CIPHER_SUITE_WEP40[];
++extern u8 WPA_CIPHER_SUITE_TKIP[];
++extern u8 WPA_CIPHER_SUITE_WRAP[];
++extern u8 WPA_CIPHER_SUITE_CCMP[];
++extern u8 RSN_CIPHER_SUITE_GCMP[];
++extern u8 RSN_CIPHER_SUITE_GCMP_256[];
++extern u8 RSN_CIPHER_SUITE_CCMP_256[];
++extern u8 WPA_CIPHER_SUITE_WEP104[];
++
++
++#define RSN_HEADER_LEN 4
++#define RSN_SELECTOR_LEN 4
++
++extern u16 RSN_VERSION_BSD;
++extern u8 RSN_CIPHER_SUITE_NONE[];
++extern u8 RSN_CIPHER_SUITE_WEP40[];
++extern u8 RSN_CIPHER_SUITE_TKIP[];
++extern u8 RSN_CIPHER_SUITE_WRAP[];
++extern u8 RSN_CIPHER_SUITE_CCMP[];
++extern u8 RSN_CIPHER_SUITE_WEP104[];
++
++/* AKM suite type */
++extern u8 WLAN_AKM_8021X[];
++extern u8 WLAN_AKM_PSK[];
++extern u8 WLAN_AKM_FT_8021X[];
++extern u8 WLAN_AKM_FT_PSK[];
++extern u8 WLAN_AKM_8021X_SHA256[];
++extern u8 WLAN_AKM_PSK_SHA256[];
++extern u8 WLAN_AKM_TDLS[];
++extern u8 WLAN_AKM_SAE[];
++extern u8 WLAN_AKM_FT_OVER_SAE[];
++extern u8 WLAN_AKM_8021X_SUITE_B[];
++extern u8 WLAN_AKM_8021X_SUITE_B_192[];
++extern u8 WLAN_AKM_FILS_SHA256[];
++extern u8 WLAN_AKM_FILS_SHA384[];
++extern u8 WLAN_AKM_FT_FILS_SHA256[];
++extern u8 WLAN_AKM_FT_FILS_SHA384[];
++
++#define WLAN_AKM_TYPE_8021X BIT(0)
++#define WLAN_AKM_TYPE_PSK BIT(1)
++#define WLAN_AKM_TYPE_FT_8021X BIT(2)
++#define WLAN_AKM_TYPE_FT_PSK BIT(3)
++#define WLAN_AKM_TYPE_8021X_SHA256 BIT(4)
++#define WLAN_AKM_TYPE_PSK_SHA256 BIT(5)
++#define WLAN_AKM_TYPE_TDLS BIT(6)
++#define WLAN_AKM_TYPE_SAE BIT(7)
++#define WLAN_AKM_TYPE_FT_OVER_SAE BIT(8)
++#define WLAN_AKM_TYPE_8021X_SUITE_B BIT(9)
++#define WLAN_AKM_TYPE_8021X_SUITE_B_192 BIT(10)
++#define WLAN_AKM_TYPE_FILS_SHA256 BIT(11)
++#define WLAN_AKM_TYPE_FILS_SHA384 BIT(12)
++#define WLAN_AKM_TYPE_FT_FILS_SHA256 BIT(13)
++#define WLAN_AKM_TYPE_FT_FILS_SHA384 BIT(14)
++
++/* IEEE 802.11i */
++#define PMKID_LEN 16
++#define PMK_LEN 32
++#define PMK_LEN_SUITE_B_192 48
++#define PMK_LEN_MAX 48
++#define WPA_REPLAY_COUNTER_LEN 8
++#define WPA_NONCE_LEN 32
++#define WPA_KEY_RSC_LEN 8
++#define WPA_GMK_LEN 32
++#define WPA_GTK_MAX_LEN 32
++
++/* IEEE 802.11, 8.5.2 EAPOL-Key frames */
++#define WPA_KEY_INFO_TYPE_MASK ((u16) (BIT(0) | BIT(1) | BIT(2)))
++#define WPA_KEY_INFO_TYPE_AKM_DEFINED 0
++#define WPA_KEY_INFO_TYPE_HMAC_MD5_RC4 BIT(0)
++#define WPA_KEY_INFO_TYPE_HMAC_SHA1_AES BIT(1)
++#define WPA_KEY_INFO_TYPE_AES_128_CMAC 3
++#define WPA_KEY_INFO_KEY_TYPE BIT(3) /* 1 = Pairwise, 0 = Group key */
++/* bit4..5 is used in WPA, but is reserved in IEEE 802.11i/RSN */
++#define WPA_KEY_INFO_KEY_INDEX_MASK (BIT(4) | BIT(5))
++#define WPA_KEY_INFO_KEY_INDEX_SHIFT 4
++#define WPA_KEY_INFO_INSTALL BIT(6) /* pairwise */
++#define WPA_KEY_INFO_TXRX BIT(6) /* group */
++#define WPA_KEY_INFO_ACK BIT(7)
++#define WPA_KEY_INFO_MIC BIT(8)
++#define WPA_KEY_INFO_SECURE BIT(9)
++#define WPA_KEY_INFO_ERROR BIT(10)
++#define WPA_KEY_INFO_REQUEST BIT(11)
++#define WPA_KEY_INFO_ENCR_KEY_DATA BIT(12) /* IEEE 802.11i/RSN only */
++#define WPA_KEY_INFO_SMK_MESSAGE BIT(13)
++
++struct ieee802_1x_hdr {
++	u8 version;
++	u8 type;
++	u16 length;
++	/* followed by length octets of data */
++};
++
++struct wpa_eapol_key {
++	u8 type;
++	/* Note: key_info, key_length, and key_data_length are unaligned */
++	u8 key_info[2]; /* big endian */
++	u8 key_length[2]; /* big endian */
++	u8 replay_counter[WPA_REPLAY_COUNTER_LEN];
++	u8 key_nonce[WPA_NONCE_LEN];
++	u8 key_iv[16];
++	u8 key_rsc[WPA_KEY_RSC_LEN];
++	u8 key_id[8]; /* Reserved in IEEE 802.11i/RSN */
++	u8 key_mic[16];
++	u8 key_data_length[2]; /* big endian */
++	/* followed by key_data_length bytes of key_data */
++};
++
++typedef enum _RATEID_IDX_ {
++	RATEID_IDX_BGN_40M_2SS = 0,
++	RATEID_IDX_BGN_40M_1SS = 1,
++	RATEID_IDX_BGN_20M_2SS_BN = 2,
++	RATEID_IDX_BGN_20M_1SS_BN = 3,
++	RATEID_IDX_GN_N2SS = 4,
++	RATEID_IDX_GN_N1SS = 5,
++	RATEID_IDX_BG = 6,
++	RATEID_IDX_G = 7,
++	RATEID_IDX_B = 8,
++	RATEID_IDX_VHT_2SS = 9,
++	RATEID_IDX_VHT_1SS = 10,
++	RATEID_IDX_MIX1 = 11,
++	RATEID_IDX_MIX2 = 12,
++	RATEID_IDX_VHT_3SS = 13,
++	RATEID_IDX_BGN_3SS = 14,
++	RATEID_IDX_BGN_4SS = 15,
++	RATEID_IDX_VHT_4SS = 16,
++} RATEID_IDX, *PRATEID_IDX;
++
++typedef enum _RATR_TABLE_MODE {
++	RATR_INX_WIRELESS_NGB = 0,	/* BGN 40 Mhz 2SS 1SS */
++	RATR_INX_WIRELESS_NG = 1,		/* GN or N */
++	RATR_INX_WIRELESS_NB = 2,		/* BGN 20 Mhz 2SS 1SS  or BN */
++	RATR_INX_WIRELESS_N = 3,
++	RATR_INX_WIRELESS_GB = 4,
++	RATR_INX_WIRELESS_G = 5,
++	RATR_INX_WIRELESS_B = 6,
++	RATR_INX_WIRELESS_MC = 7,
++	RATR_INX_WIRELESS_AC_N = 8,
++} RATR_TABLE_MODE, *PRATR_TABLE_MODE;
++
++
++enum NETWORK_TYPE {
++	WIRELESS_INVALID = 0,
++	/* Sub-Element */
++	WIRELESS_11B = BIT(0), /* tx: cck only , rx: cck only, hw: cck */
++	WIRELESS_11G = BIT(1), /* tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm */
++	WIRELESS_11A = BIT(2), /* tx: ofdm only, rx: ofdm only, hw: ofdm only */
++	WIRELESS_11_24N = BIT(3), /* tx: MCS only, rx: MCS & cck, hw: MCS & cck */
++	WIRELESS_11_5N = BIT(4), /* tx: MCS only, rx: MCS & ofdm, hw: ofdm only */
++	WIRELESS_AUTO = BIT(5),
++	WIRELESS_11AC = BIT(6),
++
++	/* Combination */
++	/* Type for current wireless mode */
++	WIRELESS_11BG = (WIRELESS_11B | WIRELESS_11G), /* tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm */
++	WIRELESS_11G_24N = (WIRELESS_11G | WIRELESS_11_24N), /* tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm */
++	WIRELESS_11A_5N = (WIRELESS_11A | WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */
++	WIRELESS_11B_24N = (WIRELESS_11B | WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */
++	WIRELESS_11BG_24N = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */
++	WIRELESS_11_24AC = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11AC),
++	WIRELESS_11_5AC = (WIRELESS_11A | WIRELESS_11AC),
++
++
++	/* Type for registry default wireless mode */
++	WIRELESS_11AGN = (WIRELESS_11A | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */
++	WIRELESS_11ABGN = (WIRELESS_11A | WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N),
++	WIRELESS_MODE_24G = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N),
++	WIRELESS_MODE_5G = (WIRELESS_11A | WIRELESS_11_5N | WIRELESS_11AC),
++	WIRELESS_MODE_MAX = (WIRELESS_11A | WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N | WIRELESS_11AC),
++};
++
++#define SUPPORTED_24G_NETTYPE_MSK WIRELESS_MODE_24G
++#define SUPPORTED_5G_NETTYPE_MSK WIRELESS_MODE_5G
++
++#define IsLegacyOnly(NetType)  ((NetType) == ((NetType) & (WIRELESS_11BG | WIRELESS_11A)))
++
++#define IsSupported24G(NetType) ((NetType) & SUPPORTED_24G_NETTYPE_MSK ? _TRUE : _FALSE)
++#define is_supported_5g(NetType) ((NetType) & SUPPORTED_5G_NETTYPE_MSK ? _TRUE : _FALSE)
++
++#define IsEnableHWCCK(NetType) IsSupported24G(NetType)
++#define IsEnableHWOFDM(NetType) ((NetType) & (WIRELESS_11G | WIRELESS_11_24N | SUPPORTED_5G_NETTYPE_MSK) ? _TRUE : _FALSE)
++
++#define IsSupportedRxCCK(NetType) IsEnableHWCCK(NetType)
++#define IsSupportedRxOFDM(NetType) IsEnableHWOFDM(NetType)
++#define IsSupportedRxHT(NetType) IsEnableHWOFDM(NetType)
++
++#define IsSupportedTxCCK(NetType) ((NetType) & (WIRELESS_11B) ? _TRUE : _FALSE)
++#define IsSupportedTxOFDM(NetType) ((NetType) & (WIRELESS_11G | WIRELESS_11A) ? _TRUE : _FALSE)
++#define is_supported_ht(NetType) ((NetType) & (WIRELESS_11_24N | WIRELESS_11_5N) ? _TRUE : _FALSE)
++
++#define is_supported_vht(NetType) ((NetType) & (WIRELESS_11AC) ? _TRUE : _FALSE)
++
++
++
++
++
++typedef struct ieee_param {
++	u32 cmd;
++	u8 sta_addr[ETH_ALEN];
++	union {
++		struct {
++			u8 name;
++			u32 value;
++		} wpa_param;
++		struct {
++			u32 len;
++			u8 reserved[32];
++			u8 data[0];
++		} wpa_ie;
++		struct {
++			int command;
++			int reason_code;
++		} mlme;
++		struct {
++			u8 alg[IEEE_CRYPT_ALG_NAME_LEN];
++			u8 set_tx;
++			u32 err;
++			u8 idx;
++			u8 seq[8]; /* sequence counter (set: RX, get: TX) */
++			u16 key_len;
++			u8 key[0];
++		} crypt;
++#ifdef CONFIG_AP_MODE
++		struct {
++			u16 aid;
++			u16 capability;
++			int flags;
++			u8 tx_supp_rates[16];
++			struct rtw_ieee80211_ht_cap ht_cap;
++		} add_sta;
++		struct {
++			u8	reserved[2];/* for set max_num_sta */
++			u8	buf[0];
++		} bcn_ie;
++#endif
++
++	} u;
++} ieee_param;
++
++#ifdef CONFIG_AP_MODE
++typedef struct ieee_param_ex {
++	u32 cmd;
++	u8 sta_addr[ETH_ALEN];
++	u8 data[0];
++} ieee_param_ex;
++
++struct sta_data {
++	u16 aid;
++	u16 capability;
++	int flags;
++	u32 sta_set;
++	u8 tx_supp_rates[16];
++	u32 tx_supp_rates_len;
++	struct rtw_ieee80211_ht_cap ht_cap;
++	u64	rx_pkts;
++	u64	rx_bytes;
++	u64	rx_drops;
++	u64	tx_pkts;
++	u64	tx_bytes;
++	u64	tx_drops;
++};
++#endif
++
++
++#if WIRELESS_EXT < 17
++	#define IW_QUAL_QUAL_INVALID   0x10
++	#define IW_QUAL_LEVEL_INVALID  0x20
++	#define IW_QUAL_NOISE_INVALID  0x40
++	#define IW_QUAL_QUAL_UPDATED   0x1
++	#define IW_QUAL_LEVEL_UPDATED  0x2
++	#define IW_QUAL_NOISE_UPDATED  0x4
++#endif
++
++#define IEEE80211_DATA_LEN		2304
++/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section
++   6.2.1.1.2.
++
++   The figure in section 7.1.2 suggests a body size of up to 2312
++   bytes is allowed, which is a bit confusing, I suspect this
++   represents the 2304 bytes of real data, plus a possible 8 bytes of
++   WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */
++
++
++#define IEEE80211_HLEN			30
++#define IEEE80211_FRAME_LEN		(IEEE80211_DATA_LEN + IEEE80211_HLEN)
++
++
++/* this is stolen from ipw2200 driver */
++#define IEEE_IBSS_MAC_HASH_SIZE 31
++
++struct ieee_ibss_seq {
++	u8 mac[ETH_ALEN];
++	u16 seq_num;
++	u16 frag_num;
++	unsigned long packet_time;
++	_list	list;
++};
++
++#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
++
++struct rtw_ieee80211_hdr {
++	u16 frame_ctl;
++	u16 duration_id;
++	u8 addr1[ETH_ALEN];
++	u8 addr2[ETH_ALEN];
++	u8 addr3[ETH_ALEN];
++	u16 seq_ctl;
++	u8 addr4[ETH_ALEN];
++} __attribute__((packed));
++
++struct rtw_ieee80211_hdr_3addr {
++	u16 frame_ctl;
++	u16 duration_id;
++	u8 addr1[ETH_ALEN];
++	u8 addr2[ETH_ALEN];
++	u8 addr3[ETH_ALEN];
++	u16 seq_ctl;
++} __attribute__((packed));
++
++
++struct rtw_ieee80211_hdr_qos {
++	u16 frame_ctl;
++	u16 duration_id;
++	u8 addr1[ETH_ALEN];
++	u8 addr2[ETH_ALEN];
++	u8 addr3[ETH_ALEN];
++	u16 seq_ctl;
++	u8 addr4[ETH_ALEN];
++	u16	qc;
++}  __attribute__((packed));
++
++struct rtw_ieee80211_hdr_3addr_qos {
++	u16 frame_ctl;
++	u16 duration_id;
++	u8 addr1[ETH_ALEN];
++	u8 addr2[ETH_ALEN];
++	u8 addr3[ETH_ALEN];
++	u16 seq_ctl;
++	u16     qc;
++}  __attribute__((packed));
++
++struct eapol {
++	u8 snap[6];
++	u16 ethertype;
++	u8 version;
++	u8 type;
++	u16 length;
++} __attribute__((packed));
++
++struct rtw_ieee80211s_hdr {
++	u8 flags;
++	u8 ttl;
++	u32 seqnum;
++	u8 eaddr1[ETH_ALEN];
++	u8 eaddr2[ETH_ALEN];
++} __attribute__((packed));
++
++/**
++ * struct rtw_ieee80211_rann_ie
++ *
++ * This structure refers to "Root Announcement information element"
++ */
++ struct rtw_ieee80211_rann_ie {
++	u8 rann_flags;
++	u8 rann_hopcount;
++	u8 rann_ttl;
++	u8 rann_addr[ETH_ALEN];
++	u32 rann_seq;
++	u32 rann_interval;
++	u32 rann_metric;
++} __attribute__((packed));
++#endif
++
++enum eap_type {
++	EAP_PACKET = 0,
++	EAPOL_START,
++	EAPOL_LOGOFF,
++	EAPOL_KEY,
++	EAPOL_ENCAP_ASF_ALERT
++};
++
++#define IEEE80211_3ADDR_LEN 24
++#define IEEE80211_4ADDR_LEN 30
++#define IEEE80211_FCS_LEN    4
++
++#define MIN_FRAG_THRESHOLD     256U
++#define	MAX_FRAG_THRESHOLD     2346U
++
++/* Frame control field constants */
++#define RTW_IEEE80211_FCTL_VERS		0x0003
++#define RTW_IEEE80211_FCTL_FTYPE		0x000c
++#define RTW_IEEE80211_FCTL_STYPE		0x00f0
++#define RTW_IEEE80211_FCTL_TODS		0x0100
++#define RTW_IEEE80211_FCTL_FROMDS	0x0200
++#define RTW_IEEE80211_FCTL_MOREFRAGS	0x0400
++#define RTW_IEEE80211_FCTL_RETRY		0x0800
++#define RTW_IEEE80211_FCTL_PM		0x1000
++#define RTW_IEEE80211_FCTL_MOREDATA	0x2000
++#define RTW_IEEE80211_FCTL_PROTECTED	0x4000
++#define RTW_IEEE80211_FCTL_ORDER		0x8000
++#define RTW_IEEE80211_FCTL_CTL_EXT	0x0f00
++
++#define RTW_IEEE80211_FTYPE_MGMT		0x0000
++#define RTW_IEEE80211_FTYPE_CTL		0x0004
++#define RTW_IEEE80211_FTYPE_DATA		0x0008
++#define RTW_IEEE80211_FTYPE_EXT		0x000c
++
++/* management */
++#define RTW_IEEE80211_STYPE_ASSOC_REQ	0x0000
++#define RTW_IEEE80211_STYPE_ASSOC_RESP	0x0010
++#define RTW_IEEE80211_STYPE_REASSOC_REQ	0x0020
++#define RTW_IEEE80211_STYPE_REASSOC_RESP	0x0030
++#define RTW_IEEE80211_STYPE_PROBE_REQ	0x0040
++#define RTW_IEEE80211_STYPE_PROBE_RESP	0x0050
++#define RTW_IEEE80211_STYPE_BEACON		0x0080
++#define RTW_IEEE80211_STYPE_ATIM		0x0090
++#define RTW_IEEE80211_STYPE_DISASSOC	0x00A0
++#define RTW_IEEE80211_STYPE_AUTH		0x00B0
++#define RTW_IEEE80211_STYPE_DEAUTH		0x00C0
++#define RTW_IEEE80211_STYPE_ACTION		0x00D0
++
++/* control */
++#define RTW_IEEE80211_STYPE_CTL_EXT		0x0060
++#define RTW_IEEE80211_STYPE_BACK_REQ		0x0080
++#define RTW_IEEE80211_STYPE_BACK		0x0090
++#define RTW_IEEE80211_STYPE_PSPOLL		0x00A0
++#define RTW_IEEE80211_STYPE_RTS		0x00B0
++#define RTW_IEEE80211_STYPE_CTS		0x00C0
++#define RTW_IEEE80211_STYPE_ACK		0x00D0
++#define RTW_IEEE80211_STYPE_CFEND		0x00E0
++#define RTW_IEEE80211_STYPE_CFENDACK		0x00F0
++
++/* data */
++#define RTW_IEEE80211_STYPE_DATA		0x0000
++#define RTW_IEEE80211_STYPE_DATA_CFACK	0x0010
++#define RTW_IEEE80211_STYPE_DATA_CFPOLL	0x0020
++#define RTW_IEEE80211_STYPE_DATA_CFACKPOLL	0x0030
++#define RTW_IEEE80211_STYPE_NULLFUNC	0x0040
++#define RTW_IEEE80211_STYPE_CFACK		0x0050
++#define RTW_IEEE80211_STYPE_CFPOLL		0x0060
++#define RTW_IEEE80211_STYPE_CFACKPOLL	0x0070
++#define RTW_IEEE80211_STYPE_QOS_DATA		0x0080
++#define RTW_IEEE80211_STYPE_QOS_DATA_CFACK		0x0090
++#define RTW_IEEE80211_STYPE_QOS_DATA_CFPOLL		0x00A0
++#define RTW_IEEE80211_STYPE_QOS_DATA_CFACKPOLL	0x00B0
++#define RTW_IEEE80211_STYPE_QOS_NULLFUNC	0x00C0
++#define RTW_IEEE80211_STYPE_QOS_CFACK		0x00D0
++#define RTW_IEEE80211_STYPE_QOS_CFPOLL		0x00E0
++#define RTW_IEEE80211_STYPE_QOS_CFACKPOLL	0x00F0
++
++/* sequence control field */
++#define RTW_IEEE80211_SCTL_FRAG	0x000F
++#define RTW_IEEE80211_SCTL_SEQ	0xFFF0
++
++
++#define RTW_ERP_INFO_NON_ERP_PRESENT BIT(0)
++#define RTW_ERP_INFO_USE_PROTECTION BIT(1)
++#define RTW_ERP_INFO_BARKER_PREAMBLE_MODE BIT(2)
++
++/* QoS,QOS */
++#define NORMAL_ACK			0
++#define NO_ACK				1
++#define NON_EXPLICIT_ACK	2
++#define BLOCK_ACK			3
++
++#ifndef ETH_P_PAE
++	#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */
++#endif /* ETH_P_PAE */
++
++#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */
++
++#define ETH_P_ECONET	0x0018
++
++#ifndef ETH_P_80211_RAW
++	#define ETH_P_80211_RAW (ETH_P_ECONET + 1)
++#endif
++
++/* IEEE 802.11 defines */
++
++#define P80211_OUI_LEN 3
++
++#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
++
++struct ieee80211_snap_hdr {
++
++	u8    dsap;   /* always 0xAA */
++	u8    ssap;   /* always 0xAA */
++	u8    ctrl;   /* always 0x03 */
++	u8    oui[P80211_OUI_LEN];    /* organizational universal id */
++
++} __attribute__((packed));
++
++#endif
++
++#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
++
++#define WLAN_FC_GET_TYPE(fc) ((fc) & RTW_IEEE80211_FCTL_FTYPE)
++#define WLAN_FC_GET_STYPE(fc) ((fc) & RTW_IEEE80211_FCTL_STYPE)
++
++#define WLAN_QC_GET_TID(qc) ((qc) & 0x0f)
++
++#define WLAN_GET_SEQ_FRAG(seq) ((seq) & RTW_IEEE80211_SCTL_FRAG)
++#define WLAN_GET_SEQ_SEQ(seq)  ((seq) & RTW_IEEE80211_SCTL_SEQ)
++
++/* Authentication algorithms */
++#define WLAN_AUTH_OPEN 0
++#define WLAN_AUTH_SHARED_KEY 1
++#define WLAN_AUTH_SAE 3
++
++#define WLAN_AUTH_CHALLENGE_LEN 128
++
++#define WLAN_CAPABILITY_BSS (1<<0)
++#define WLAN_CAPABILITY_IBSS (1<<1)
++#define WLAN_CAPABILITY_CF_POLLABLE (1<<2)
++#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3)
++#define WLAN_CAPABILITY_PRIVACY (1<<4)
++#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5)
++#define WLAN_CAPABILITY_PBCC (1<<6)
++#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7)
++#define WLAN_CAPABILITY_SHORT_SLOT (1<<10)
++
++/* Status codes */
++#define WLAN_STATUS_SUCCESS 0
++#define WLAN_STATUS_UNSPECIFIED_FAILURE 1
++#define WLAN_STATUS_CAPS_UNSUPPORTED 10
++#define WLAN_STATUS_REASSOC_NO_ASSOC 11
++#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12
++#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13
++#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14
++#define WLAN_STATUS_CHALLENGE_FAIL 15
++#define WLAN_STATUS_AUTH_TIMEOUT 16
++#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17
++#define WLAN_STATUS_ASSOC_DENIED_RATES 18
++/* 802.11b */
++#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19
++#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20
++#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21
++
++/* Reason codes */
++#define WLAN_REASON_UNSPECIFIED 1
++#define WLAN_REASON_PREV_AUTH_NOT_VALID 2
++#define WLAN_REASON_DEAUTH_LEAVING 3
++#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4
++#define WLAN_REASON_DISASSOC_AP_BUSY 5
++#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6
++#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7
++#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8
++#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9
++#define WLAN_REASON_IEEE_802_1X_AUTH_FAILED 23
++#define WLAN_REASON_MESH_PEER_CANCELED 52
++#define WLAN_REASON_MESH_MAX_PEERS 53
++#define WLAN_REASON_MESH_CONFIG 54
++#define WLAN_REASON_MESH_CLOSE 55
++#define WLAN_REASON_MESH_MAX_RETRIES 56 
++#define WLAN_REASON_MESH_CONFIRM_TIMEOUT 57
++#define WLAN_REASON_MESH_INVALID_GTK 58
++#define WLAN_REASON_MESH_INCONSISTENT_PARAM 59
++#define WLAN_REASON_MESH_INVALID_SECURITY 60
++#define WLAN_REASON_MESH_PATH_NOPROXY 61
++#define WLAN_REASON_MESH_PATH_NOFORWARD 62
++#define WLAN_REASON_MESH_PATH_DEST_UNREACHABLE 63
++#define WLAN_REASON_MAC_EXISTS_IN_MBSS 64
++#define WLAN_REASON_MESH_CHAN_REGULATORY 65
++#define WLAN_REASON_MESH_CHAN 66
++#define WLAN_REASON_SA_QUERY_TIMEOUT 65532
++#define WLAN_REASON_ACTIVE_ROAM 65533
++#define WLAN_REASON_JOIN_WRONG_CHANNEL       65534
++#define WLAN_REASON_EXPIRATION_CHK 65535
++
++#define WLAN_REASON_IS_PRIVATE(reason) ( \
++	reason == WLAN_REASON_EXPIRATION_CHK \
++	|| reason == WLAN_REASON_JOIN_WRONG_CHANNEL \
++	|| reason == WLAN_REASON_ACTIVE_ROAM \
++	|| reason == WLAN_REASON_SA_QUERY_TIMEOUT \
++	)
++
++/* Information Element IDs */
++#define WLAN_EID_SSID 0
++#define WLAN_EID_SUPP_RATES 1
++#define WLAN_EID_FH_PARAMS 2
++#define WLAN_EID_DS_PARAMS 3
++#define WLAN_EID_CF_PARAMS 4
++#define WLAN_EID_TIM 5
++#define WLAN_EID_IBSS_PARAMS 6
++#define WLAN_EID_CHALLENGE 16
++/* EIDs defined by IEEE 802.11h - START */
++#define WLAN_EID_PWR_CONSTRAINT 32
++#define WLAN_EID_PWR_CAPABILITY 33
++#define WLAN_EID_TPC_REQUEST 34
++#define WLAN_EID_TPC_REPORT 35
++#define WLAN_EID_SUPPORTED_CHANNELS 36
++#define WLAN_EID_CHANNEL_SWITCH 37
++#define WLAN_EID_MEASURE_REQUEST 38
++#define WLAN_EID_MEASURE_REPORT 39
++#define WLAN_EID_QUITE 40
++#define WLAN_EID_IBSS_DFS 41
++/* EIDs defined by IEEE 802.11h - END */
++#define WLAN_EID_ERP_INFO 42
++#define WLAN_EID_HT_CAP 45
++#define WLAN_EID_RSN 48
++#define WLAN_EID_EXT_SUPP_RATES 50
++#define WLAN_EID_MOBILITY_DOMAIN 54
++#define WLAN_EID_FAST_BSS_TRANSITION 55
++#define WLAN_EID_TIMEOUT_INTERVAL 56
++#define WLAN_EID_RIC_DATA 57
++#define WLAN_EID_HT_OPERATION 61
++#define WLAN_EID_SECONDARY_CHANNEL_OFFSET 62
++#define WLAN_EID_20_40_BSS_COEXISTENCE 72
++#define WLAN_EID_20_40_BSS_INTOLERANT 73
++#define WLAN_EID_OVERLAPPING_BSS_SCAN_PARAMS 74
++#define WLAN_EID_MMIE 76
++#define WLAN_EID_MESH_CONFIG 113
++#define WLAN_EID_MESH_ID 114
++#define WLAN_EID_MPM 117
++#define	WLAN_EID_RANN 126
++#define	WLAN_EID_PREQ 130
++#define	WLAN_EID_PREP 131
++#define	WLAN_EID_PERR 132
++#define WLAN_EID_AMPE 139
++#define WLAN_EID_MIC 140
++#define WLAN_EID_VENDOR_SPECIFIC 221
++#define WLAN_EID_GENERIC (WLAN_EID_VENDOR_SPECIFIC)
++#define WLAN_EID_VHT_CAPABILITY 191
++#define WLAN_EID_VHT_OPERATION 192
++#define WLAN_EID_VHT_OP_MODE_NOTIFY 199
++#define WLAN_EID_EXTENSION 255
++#define WLAN_EID_EXT_OWE_DH_PARAM 32
++
++#define IEEE80211_MGMT_HDR_LEN 24
++#define IEEE80211_DATA_HDR3_LEN 24
++#define IEEE80211_DATA_HDR4_LEN 30
++
++
++#define IEEE80211_STATMASK_SIGNAL (1<<0)
++#define IEEE80211_STATMASK_RSSI (1<<1)
++#define IEEE80211_STATMASK_NOISE (1<<2)
++#define IEEE80211_STATMASK_RATE (1<<3)
++#define IEEE80211_STATMASK_WEMASK 0x7
++
++
++#define IEEE80211_CCK_MODULATION    (1<<0)
++#define IEEE80211_OFDM_MODULATION   (1<<1)
++
++#define IEEE80211_24GHZ_BAND     (1<<0)
++#define IEEE80211_52GHZ_BAND     (1<<1)
++
++#define IEEE80211_CCK_RATE_LEN		4
++#define IEEE80211_NUM_OFDM_RATESLEN	8
++
++
++
++#define IEEE80211_CCK_RATE_1MB		        0x02
++#define IEEE80211_CCK_RATE_2MB		        0x04
++#define IEEE80211_CCK_RATE_5MB		        0x0B
++#define IEEE80211_CCK_RATE_11MB		        0x16
++#define IEEE80211_OFDM_RATE_LEN		8
++#define IEEE80211_OFDM_RATE_6MB		        0x0C
++#define IEEE80211_OFDM_RATE_9MB		        0x12
++#define IEEE80211_OFDM_RATE_12MB		0x18
++#define IEEE80211_OFDM_RATE_18MB		0x24
++#define IEEE80211_OFDM_RATE_24MB		0x30
++#define IEEE80211_PBCC_RATE_22MB		0x2C
++#define IEEE80211_FREAK_RATE_22_5MB		0x2D
++#define IEEE80211_OFDM_RATE_36MB		0x48
++#define IEEE80211_OFDM_RATE_48MB		0x60
++#define IEEE80211_OFDM_RATE_54MB		0x6C
++#define IEEE80211_BASIC_RATE_MASK		0x80
++
++#define IEEE80211_CCK_RATE_1MB_MASK		(1<<0)
++#define IEEE80211_CCK_RATE_2MB_MASK		(1<<1)
++#define IEEE80211_CCK_RATE_5MB_MASK		(1<<2)
++#define IEEE80211_CCK_RATE_11MB_MASK		(1<<3)
++#define IEEE80211_OFDM_RATE_6MB_MASK		(1<<4)
++#define IEEE80211_OFDM_RATE_9MB_MASK		(1<<5)
++#define IEEE80211_OFDM_RATE_12MB_MASK		(1<<6)
++#define IEEE80211_OFDM_RATE_18MB_MASK		(1<<7)
++#define IEEE80211_OFDM_RATE_24MB_MASK		(1<<8)
++#define IEEE80211_OFDM_RATE_36MB_MASK		(1<<9)
++#define IEEE80211_OFDM_RATE_48MB_MASK		(1<<10)
++#define IEEE80211_OFDM_RATE_54MB_MASK		(1<<11)
++
++#define IEEE80211_CCK_RATES_MASK	        0x0000000F
++#define IEEE80211_CCK_BASIC_RATES_MASK	(IEEE80211_CCK_RATE_1MB_MASK | \
++		IEEE80211_CCK_RATE_2MB_MASK)
++#define IEEE80211_CCK_DEFAULT_RATES_MASK	(IEEE80211_CCK_BASIC_RATES_MASK | \
++		IEEE80211_CCK_RATE_5MB_MASK | \
++		IEEE80211_CCK_RATE_11MB_MASK)
++
++#define IEEE80211_OFDM_RATES_MASK		0x00000FF0
++#define IEEE80211_OFDM_BASIC_RATES_MASK	(IEEE80211_OFDM_RATE_6MB_MASK | \
++		IEEE80211_OFDM_RATE_12MB_MASK | \
++		IEEE80211_OFDM_RATE_24MB_MASK)
++#define IEEE80211_OFDM_DEFAULT_RATES_MASK	(IEEE80211_OFDM_BASIC_RATES_MASK | \
++		IEEE80211_OFDM_RATE_9MB_MASK  | \
++		IEEE80211_OFDM_RATE_18MB_MASK | \
++		IEEE80211_OFDM_RATE_36MB_MASK | \
++		IEEE80211_OFDM_RATE_48MB_MASK | \
++		IEEE80211_OFDM_RATE_54MB_MASK)
++#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \
++				      IEEE80211_CCK_DEFAULT_RATES_MASK)
++
++#define IEEE80211_NUM_OFDM_RATES	    8
++#define IEEE80211_NUM_CCK_RATES	            4
++#define IEEE80211_OFDM_SHIFT_MASK_A         4
++
++
++enum MGN_RATE {
++	MGN_1M		= 0x02,
++	MGN_2M		= 0x04,
++	MGN_5_5M	= 0x0B,
++	MGN_6M		= 0x0C,
++	MGN_9M		= 0x12,
++	MGN_11M	= 0x16,
++	MGN_12M	= 0x18,
++	MGN_18M	= 0x24,
++	MGN_24M	= 0x30,
++	MGN_36M	= 0x48,
++	MGN_48M	= 0x60,
++	MGN_54M	= 0x6C,
++	MGN_MCS32	= 0x7F,
++	MGN_MCS0,
++	MGN_MCS1,
++	MGN_MCS2,
++	MGN_MCS3,
++	MGN_MCS4,
++	MGN_MCS5,
++	MGN_MCS6,
++	MGN_MCS7,
++	MGN_MCS8,
++	MGN_MCS9,
++	MGN_MCS10,
++	MGN_MCS11,
++	MGN_MCS12,
++	MGN_MCS13,
++	MGN_MCS14,
++	MGN_MCS15,
++	MGN_MCS16,
++	MGN_MCS17,
++	MGN_MCS18,
++	MGN_MCS19,
++	MGN_MCS20,
++	MGN_MCS21,
++	MGN_MCS22,
++	MGN_MCS23,
++	MGN_MCS24,
++	MGN_MCS25,
++	MGN_MCS26,
++	MGN_MCS27,
++	MGN_MCS28,
++	MGN_MCS29,
++	MGN_MCS30,
++	MGN_MCS31,
++	MGN_VHT1SS_MCS0,
++	MGN_VHT1SS_MCS1,
++	MGN_VHT1SS_MCS2,
++	MGN_VHT1SS_MCS3,
++	MGN_VHT1SS_MCS4,
++	MGN_VHT1SS_MCS5,
++	MGN_VHT1SS_MCS6,
++	MGN_VHT1SS_MCS7,
++	MGN_VHT1SS_MCS8,
++	MGN_VHT1SS_MCS9,
++	MGN_VHT2SS_MCS0,
++	MGN_VHT2SS_MCS1,
++	MGN_VHT2SS_MCS2,
++	MGN_VHT2SS_MCS3,
++	MGN_VHT2SS_MCS4,
++	MGN_VHT2SS_MCS5,
++	MGN_VHT2SS_MCS6,
++	MGN_VHT2SS_MCS7,
++	MGN_VHT2SS_MCS8,
++	MGN_VHT2SS_MCS9,
++	MGN_VHT3SS_MCS0,
++	MGN_VHT3SS_MCS1,
++	MGN_VHT3SS_MCS2,
++	MGN_VHT3SS_MCS3,
++	MGN_VHT3SS_MCS4,
++	MGN_VHT3SS_MCS5,
++	MGN_VHT3SS_MCS6,
++	MGN_VHT3SS_MCS7,
++	MGN_VHT3SS_MCS8,
++	MGN_VHT3SS_MCS9,
++	MGN_VHT4SS_MCS0,
++	MGN_VHT4SS_MCS1,
++	MGN_VHT4SS_MCS2,
++	MGN_VHT4SS_MCS3,
++	MGN_VHT4SS_MCS4,
++	MGN_VHT4SS_MCS5,
++	MGN_VHT4SS_MCS6,
++	MGN_VHT4SS_MCS7,
++	MGN_VHT4SS_MCS8,
++	MGN_VHT4SS_MCS9,
++	MGN_UNKNOWN
++};
++
++#define IS_HT_RATE(_rate)	((_rate) >= MGN_MCS0 && (_rate) <= MGN_MCS31)
++#define IS_VHT_RATE(_rate)	((_rate) >= MGN_VHT1SS_MCS0 && (_rate) <= MGN_VHT4SS_MCS9)
++#define IS_CCK_RATE(_rate)	((_rate) == MGN_1M || (_rate) == MGN_2M || (_rate) == MGN_5_5M || (_rate) == MGN_11M)
++#define IS_OFDM_RATE(_rate)	((_rate) >= MGN_6M && (_rate) <= MGN_54M  && (_rate) != MGN_11M)
++
++#define IS_HT1SS_RATE(_rate) ((_rate) >= MGN_MCS0 && (_rate) <= MGN_MCS7)
++#define IS_HT2SS_RATE(_rate) ((_rate) >= MGN_MCS8 && (_rate) <= MGN_MCS15)
++#define IS_HT3SS_RATE(_rate) ((_rate) >= MGN_MCS16 && (_rate) <= MGN_MCS23)
++#define IS_HT4SS_RATE(_rate) ((_rate) >= MGN_MCS24 && (_rate) <= MGN_MCS31)
++
++#define IS_VHT1SS_RATE(_rate) ((_rate) >= MGN_VHT1SS_MCS0 && (_rate) <= MGN_VHT1SS_MCS9)
++#define IS_VHT2SS_RATE(_rate) ((_rate) >= MGN_VHT2SS_MCS0 && (_rate) <= MGN_VHT2SS_MCS9)
++#define IS_VHT3SS_RATE(_rate) ((_rate) >= MGN_VHT3SS_MCS0 && (_rate) <= MGN_VHT3SS_MCS9)
++#define IS_VHT4SS_RATE(_rate) ((_rate) >= MGN_VHT4SS_MCS0 && (_rate) <= MGN_VHT4SS_MCS9)
++
++#define IS_1T_RATE(_rate)	(IS_CCK_RATE((_rate)) || IS_OFDM_RATE((_rate)) || IS_HT1SS_RATE((_rate)) || IS_VHT1SS_RATE((_rate)))
++#define IS_2T_RATE(_rate)	(IS_HT2SS_RATE((_rate)) || IS_VHT2SS_RATE((_rate)))
++#define IS_3T_RATE(_rate)	(IS_HT3SS_RATE((_rate)) || IS_VHT3SS_RATE((_rate)))
++#define IS_4T_RATE(_rate)	(IS_HT4SS_RATE((_rate)) || IS_VHT4SS_RATE((_rate)))
++
++#define MGN_RATE_STR(_rate) \
++	(_rate == MGN_1M) ? "CCK_1M" : \
++	(_rate == MGN_2M) ? "CCK_2M" : \
++	(_rate == MGN_5_5M) ? "CCK_5.5M" : \
++	(_rate == MGN_11M) ? "CCK_11M" : \
++	(_rate == MGN_6M) ? "OFDM_6M" : \
++	(_rate == MGN_9M) ? "OFDM_9M" : \
++	(_rate == MGN_12M) ? "OFDM_12M" : \
++	(_rate == MGN_18M) ? "OFDM_18M" : \
++	(_rate == MGN_24M) ? "OFDM_24M" : \
++	(_rate == MGN_36M) ? "OFDM_36M" : \
++	(_rate == MGN_48M) ? "OFDM_48M" : \
++	(_rate == MGN_54M) ? "OFDM_54M" : \
++	(_rate == MGN_MCS32) ? "MCS32" : \
++	(_rate == MGN_MCS0) ? "MCS0" : \
++	(_rate == MGN_MCS1) ? "MCS1" : \
++	(_rate == MGN_MCS2) ? "MCS2" : \
++	(_rate == MGN_MCS3) ? "MCS3" : \
++	(_rate == MGN_MCS4) ? "MCS4" : \
++	(_rate == MGN_MCS5) ? "MCS5" : \
++	(_rate == MGN_MCS6) ? "MCS6" : \
++	(_rate == MGN_MCS7) ? "MCS7" : \
++	(_rate == MGN_MCS8) ? "MCS8" : \
++	(_rate == MGN_MCS9) ? "MCS9" : \
++	(_rate == MGN_MCS10) ? "MCS10" : \
++	(_rate == MGN_MCS11) ? "MCS11" : \
++	(_rate == MGN_MCS12) ? "MCS12" : \
++	(_rate == MGN_MCS13) ? "MCS13" : \
++	(_rate == MGN_MCS14) ? "MCS14" : \
++	(_rate == MGN_MCS15) ? "MCS15" : \
++	(_rate == MGN_MCS16) ? "MCS16" : \
++	(_rate == MGN_MCS17) ? "MCS17" : \
++	(_rate == MGN_MCS18) ? "MCS18" : \
++	(_rate == MGN_MCS19) ? "MCS19" : \
++	(_rate == MGN_MCS20) ? "MCS20" : \
++	(_rate == MGN_MCS21) ? "MCS21" : \
++	(_rate == MGN_MCS22) ? "MCS22" : \
++	(_rate == MGN_MCS23) ? "MCS23" : \
++	(_rate == MGN_MCS24) ? "MCS24" : \
++	(_rate == MGN_MCS25) ? "MCS25" : \
++	(_rate == MGN_MCS26) ? "MCS26" : \
++	(_rate == MGN_MCS27) ? "MCS27" : \
++	(_rate == MGN_MCS28) ? "MCS28" : \
++	(_rate == MGN_MCS29) ? "MCS29" : \
++	(_rate == MGN_MCS30) ? "MCS30" : \
++	(_rate == MGN_MCS31) ? "MCS31" : \
++	(_rate == MGN_VHT1SS_MCS0) ? "VHT1SMCS0" : \
++	(_rate == MGN_VHT1SS_MCS1) ? "VHT1SMCS1" : \
++	(_rate == MGN_VHT1SS_MCS2) ? "VHT1SMCS2" : \
++	(_rate == MGN_VHT1SS_MCS3) ? "VHT1SMCS3" : \
++	(_rate == MGN_VHT1SS_MCS4) ? "VHT1SMCS4" : \
++	(_rate == MGN_VHT1SS_MCS5) ? "VHT1SMCS5" : \
++	(_rate == MGN_VHT1SS_MCS6) ? "VHT1SMCS6" : \
++	(_rate == MGN_VHT1SS_MCS7) ? "VHT1SMCS7" : \
++	(_rate == MGN_VHT1SS_MCS8) ? "VHT1SMCS8" : \
++	(_rate == MGN_VHT1SS_MCS9) ? "VHT1SMCS9" : \
++	(_rate == MGN_VHT2SS_MCS0) ? "VHT2SMCS0" : \
++	(_rate == MGN_VHT2SS_MCS1) ? "VHT2SMCS1" : \
++	(_rate == MGN_VHT2SS_MCS2) ? "VHT2SMCS2" : \
++	(_rate == MGN_VHT2SS_MCS3) ? "VHT2SMCS3" : \
++	(_rate == MGN_VHT2SS_MCS4) ? "VHT2SMCS4" : \
++	(_rate == MGN_VHT2SS_MCS5) ? "VHT2SMCS5" : \
++	(_rate == MGN_VHT2SS_MCS6) ? "VHT2SMCS6" : \
++	(_rate == MGN_VHT2SS_MCS7) ? "VHT2SMCS7" : \
++	(_rate == MGN_VHT2SS_MCS8) ? "VHT2SMCS8" : \
++	(_rate == MGN_VHT2SS_MCS9) ? "VHT2SMCS9" : \
++	(_rate == MGN_VHT3SS_MCS0) ? "VHT3SMCS0" : \
++	(_rate == MGN_VHT3SS_MCS1) ? "VHT3SMCS1" : \
++	(_rate == MGN_VHT3SS_MCS2) ? "VHT3SMCS2" : \
++	(_rate == MGN_VHT3SS_MCS3) ? "VHT3SMCS3" : \
++	(_rate == MGN_VHT3SS_MCS4) ? "VHT3SMCS4" : \
++	(_rate == MGN_VHT3SS_MCS5) ? "VHT3SMCS5" : \
++	(_rate == MGN_VHT3SS_MCS6) ? "VHT3SMCS6" : \
++	(_rate == MGN_VHT3SS_MCS7) ? "VHT3SMCS7" : \
++	(_rate == MGN_VHT3SS_MCS8) ? "VHT3SMCS8" : \
++	(_rate == MGN_VHT3SS_MCS9) ? "VHT3SMCS9" : \
++	(_rate == MGN_VHT4SS_MCS0) ? "VHT4SMCS0" : \
++	(_rate == MGN_VHT4SS_MCS1) ? "VHT4SMCS1" : \
++	(_rate == MGN_VHT4SS_MCS2) ? "VHT4SMCS2" : \
++	(_rate == MGN_VHT4SS_MCS3) ? "VHT4SMCS3" : \
++	(_rate == MGN_VHT4SS_MCS4) ? "VHT4SMCS4" : \
++	(_rate == MGN_VHT4SS_MCS5) ? "VHT4SMCS5" : \
++	(_rate == MGN_VHT4SS_MCS6) ? "VHT4SMCS6" : \
++	(_rate == MGN_VHT4SS_MCS7) ? "VHT4SMCS7" : \
++	(_rate == MGN_VHT4SS_MCS8) ? "VHT4SMCS8" : \
++	(_rate == MGN_VHT4SS_MCS9) ? "VHT4SMCS9" : "UNKNOWN"
++
++typedef enum _RATE_SECTION {
++	CCK = 0,
++	OFDM = 1,
++	HT_MCS0_MCS7 = 2,
++	HT_MCS8_MCS15 = 3,
++	HT_MCS16_MCS23 = 4,
++	HT_MCS24_MCS31 = 5,
++	HT_1SS = HT_MCS0_MCS7,
++	HT_2SS = HT_MCS8_MCS15,
++	HT_3SS = HT_MCS16_MCS23,
++	HT_4SS = HT_MCS24_MCS31,
++	VHT_1SSMCS0_1SSMCS9 = 6,
++	VHT_2SSMCS0_2SSMCS9 = 7,
++	VHT_3SSMCS0_3SSMCS9 = 8,
++	VHT_4SSMCS0_4SSMCS9 = 9,
++	VHT_1SS = VHT_1SSMCS0_1SSMCS9,
++	VHT_2SS = VHT_2SSMCS0_2SSMCS9,
++	VHT_3SS = VHT_3SSMCS0_3SSMCS9,
++	VHT_4SS = VHT_4SSMCS0_4SSMCS9,
++	RATE_SECTION_NUM,
++} RATE_SECTION;
++
++RATE_SECTION mgn_rate_to_rs(enum MGN_RATE rate);
++
++const char *rate_section_str(u8 section);
++
++#define IS_CCK_RATE_SECTION(section) ((section) == CCK)
++#define IS_OFDM_RATE_SECTION(section) ((section) == OFDM)
++#define IS_HT_RATE_SECTION(section) ((section) >= HT_1SS && (section) <= HT_4SS)
++#define IS_VHT_RATE_SECTION(section) ((section) >= VHT_1SS && (section) <= VHT_4SS)
++
++#define IS_1T_RATE_SECTION(section) ((section) == CCK || (section) == OFDM || (section) == HT_1SS || (section) == VHT_1SS)
++#define IS_2T_RATE_SECTION(section) ((section) == HT_2SS || (section) == VHT_2SS)
++#define IS_3T_RATE_SECTION(section) ((section) == HT_3SS || (section) == VHT_3SS)
++#define IS_4T_RATE_SECTION(section) ((section) == HT_4SS || (section) == VHT_4SS)
++
++extern u8 mgn_rates_cck[];
++extern u8 mgn_rates_ofdm[];
++extern u8 mgn_rates_mcs0_7[];
++extern u8 mgn_rates_mcs8_15[];
++extern u8 mgn_rates_mcs16_23[];
++extern u8 mgn_rates_mcs24_31[];
++extern u8 mgn_rates_vht1ss[];
++extern u8 mgn_rates_vht2ss[];
++extern u8 mgn_rates_vht3ss[];
++extern u8 mgn_rates_vht4ss[];
++
++struct rate_section_ent {
++	u8 tx_num; /* value of RF_TX_NUM */
++	u8 rate_num;
++	u8 *rates;
++};
++
++extern struct rate_section_ent rates_by_sections[];
++
++#define rate_section_to_tx_num(section) (rates_by_sections[(section)].tx_num)
++#define rate_section_rate_num(section) (rates_by_sections[(section)].rate_num)
++
++/* NOTE: This data is for statistical purposes; not all hardware provides this
++ *       information for frames received.  Not setting these will not cause
++ *       any adverse affects. */
++struct ieee80211_rx_stats {
++	/* u32 mac_time[2]; */
++	s8 rssi;
++	u8 signal;
++	u8 noise;
++	u8 received_channel;
++	u16 rate; /* in 100 kbps */
++	/* u8 control; */
++	u8 mask;
++	u8 freq;
++	u16 len;
++};
++
++/* IEEE 802.11 requires that STA supports concurrent reception of at least
++ * three fragmented frames. This define can be increased to support more
++ * concurrent frames, but it should be noted that each entry can consume about
++ * 2 kB of RAM and increasing cache size will slow down frame reassembly. */
++#define IEEE80211_FRAG_CACHE_LEN 4
++
++struct ieee80211_frag_entry {
++	u32 first_frag_time;
++	uint seq;
++	uint last_frag;
++	uint qos;   /* jackson */
++	uint tid;	/* jackson */
++	struct sk_buff *skb;
++	u8 src_addr[ETH_ALEN];
++	u8 dst_addr[ETH_ALEN];
++};
++
++#ifndef PLATFORM_FREEBSD /* Baron BSD has already defined */
++struct ieee80211_stats {
++	uint tx_unicast_frames;
++	uint tx_multicast_frames;
++	uint tx_fragments;
++	uint tx_unicast_octets;
++	uint tx_multicast_octets;
++	uint tx_deferred_transmissions;
++	uint tx_single_retry_frames;
++	uint tx_multiple_retry_frames;
++	uint tx_retry_limit_exceeded;
++	uint tx_discards;
++	uint rx_unicast_frames;
++	uint rx_multicast_frames;
++	uint rx_fragments;
++	uint rx_unicast_octets;
++	uint rx_multicast_octets;
++	uint rx_fcs_errors;
++	uint rx_discards_no_buffer;
++	uint tx_discards_wrong_sa;
++	uint rx_discards_undecryptable;
++	uint rx_message_in_msg_fragments;
++	uint rx_message_in_bad_msg_fragments;
++};
++#endif /* PLATFORM_FREEBSD */
++struct ieee80211_softmac_stats {
++	uint rx_ass_ok;
++	uint rx_ass_err;
++	uint rx_probe_rq;
++	uint tx_probe_rs;
++	uint tx_beacons;
++	uint rx_auth_rq;
++	uint rx_auth_rs_ok;
++	uint rx_auth_rs_err;
++	uint tx_auth_rq;
++	uint no_auth_rs;
++	uint no_ass_rs;
++	uint tx_ass_rq;
++	uint rx_ass_rq;
++	uint tx_probe_rq;
++	uint reassoc;
++	uint swtxstop;
++	uint swtxawake;
++};
++
++#define SEC_KEY_1         (1<<0)
++#define SEC_KEY_2         (1<<1)
++#define SEC_KEY_3         (1<<2)
++#define SEC_KEY_4         (1<<3)
++#define SEC_ACTIVE_KEY    (1<<4)
++#define SEC_AUTH_MODE     (1<<5)
++#define SEC_UNICAST_GROUP (1<<6)
++#define SEC_LEVEL         (1<<7)
++#define SEC_ENABLED       (1<<8)
++
++#define SEC_LEVEL_0      0 /* None */
++#define SEC_LEVEL_1      1 /* WEP 40 and 104 bit */
++#define SEC_LEVEL_2      2 /* Level 1 + TKIP */
++#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */
++#define SEC_LEVEL_3      4 /* Level 2 + CCMP */
++
++#define WEP_KEYS 4
++#define WEP_KEY_LEN 13
++#define BIP_MAX_KEYID 5
++#define BIP_AAD_SIZE  20
++
++#if defined(PLATFORM_LINUX)
++struct ieee80211_security {
++	u16 active_key:2,
++	    enabled:1,
++	    auth_mode:2,
++	    auth_algo:4,
++	    unicast_uses_group:1;
++	u8 key_sizes[WEP_KEYS];
++	u8 keys[WEP_KEYS][WEP_KEY_LEN];
++	u8 level;
++	u16 flags;
++} __attribute__((packed));
++
++#endif
++
++/*
++
++ 802.11 data frame from AP
++
++      ,-------------------------------------------------------------------.
++Bytes |  2   |  2   |    6    |    6    |    6    |  2   | 0..2312 |   4  |
++      |------|------|---------|---------|---------|------|---------|------|
++Desc. | ctrl | dura |  DA/RA  |   TA    |    SA   | Sequ |  frame  |  fcs |
++      |      | tion | (BSSID) |         |         | ence |  data   |      |
++      `-------------------------------------------------------------------'
++
++Total: 28-2340 bytes
++
++*/
++
++struct ieee80211_header_data {
++	u16 frame_ctl;
++	u16 duration_id;
++	u8 addr1[6];
++	u8 addr2[6];
++	u8 addr3[6];
++	u16 seq_ctrl;
++};
++
++#define BEACON_PROBE_SSID_ID_POSITION 12
++
++/* Management Frame Information Element Types */
++#define MFIE_TYPE_SSID       0
++#define MFIE_TYPE_RATES      1
++#define MFIE_TYPE_FH_SET     2
++#define MFIE_TYPE_DS_SET     3
++#define MFIE_TYPE_CF_SET     4
++#define MFIE_TYPE_TIM        5
++#define MFIE_TYPE_IBSS_SET   6
++#define MFIE_TYPE_CHALLENGE  16
++#define MFIE_TYPE_ERP        42
++#define MFIE_TYPE_RSN	     48
++#define MFIE_TYPE_RATES_EX   50
++#define MFIE_TYPE_GENERIC    221
++
++#if defined(PLATFORM_LINUX)
++struct ieee80211_info_element_hdr {
++	u8 id;
++	u8 len;
++} __attribute__((packed));
++
++struct ieee80211_info_element {
++	u8 id;
++	u8 len;
++	u8 data[0];
++} __attribute__((packed));
++#endif
++
++
++/*
++ * These are the data types that can make up management packets
++ *
++	u16 auth_algorithm;
++	u16 auth_sequence;
++	u16 beacon_interval;
++	u16 capability;
++	u8 current_ap[ETH_ALEN];
++	u16 listen_interval;
++	struct {
++		u16 association_id:14, reserved:2;
++	} __attribute__ ((packed));
++	u32 time_stamp[2];
++	u16 reason;
++	u16 status;
++*/
++
++#define IEEE80211_DEFAULT_TX_ESSID "Penguin"
++#define IEEE80211_DEFAULT_BASIC_RATE 10
++
++
++#if defined(PLATFORM_LINUX)
++struct ieee80211_authentication {
++	struct ieee80211_header_data header;
++	u16 algorithm;
++	u16 transaction;
++	u16 status;
++	/* struct ieee80211_info_element_hdr info_element; */
++} __attribute__((packed));
++
++
++struct ieee80211_probe_response {
++	struct ieee80211_header_data header;
++	u32 time_stamp[2];
++	u16 beacon_interval;
++	u16 capability;
++	struct ieee80211_info_element info_element;
++} __attribute__((packed));
++
++struct ieee80211_probe_request {
++	struct ieee80211_header_data header;
++	/*struct ieee80211_info_element info_element;*/
++} __attribute__((packed));
++
++struct ieee80211_assoc_request_frame {
++	struct rtw_ieee80211_hdr_3addr header;
++	u16 capability;
++	u16 listen_interval;
++	/* u8 current_ap[ETH_ALEN]; */
++	struct ieee80211_info_element_hdr info_element;
++} __attribute__((packed));
++
++struct ieee80211_assoc_response_frame {
++	struct rtw_ieee80211_hdr_3addr header;
++	u16 capability;
++	u16 status;
++	u16 aid;
++	/*	struct ieee80211_info_element info_element;  supported rates  */
++} __attribute__((packed));
++#endif
++
++struct ieee80211_txb {
++	u8 nr_frags;
++	u8 encrypted;
++	u16 reserved;
++	u16 frag_size;
++	u16 payload_size;
++	struct sk_buff *fragments[0];
++};
++
++
++/* SWEEP TABLE ENTRIES NUMBER*/
++#define MAX_SWEEP_TAB_ENTRIES		  42
++#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET  7
++/* MAX_RATES_LENGTH needs to be 12.  The spec says 8, and many APs
++ * only use 8, and then use extended rates for the remaining supported
++ * rates.  Other APs, however, stick all of their supported rates on the
++ * main rates information element... */
++#define MAX_RATES_LENGTH                  ((u8)12)
++#define MAX_RATES_EX_LENGTH               ((u8)16)
++#define MAX_NETWORK_COUNT                  128
++#define IEEE80211_SOFTMAC_SCAN_TIME	  400
++/* (HZ / 2) */
++#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2)
++
++#define CRC_LENGTH                 4U
++
++#define MAX_WPA_IE_LEN (256)
++#define MAX_WPS_IE_LEN (512)
++#define MAX_OWE_IE_LEN (128)
++#define MAX_P2P_IE_LEN (256)
++#define MAX_WFD_IE_LEN (128)
++
++#define NETWORK_EMPTY_ESSID (1<<0)
++#define NETWORK_HAS_OFDM    (1<<1)
++#define NETWORK_HAS_CCK     (1<<2)
++
++#define IEEE80211_DTIM_MBCAST 4
++#define IEEE80211_DTIM_UCAST 2
++#define IEEE80211_DTIM_VALID 1
++#define IEEE80211_DTIM_INVALID 0
++
++#define IEEE80211_PS_DISABLED 0
++#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST
++#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST
++#define IW_ESSID_MAX_SIZE 32
++#if 0
++struct ieee80211_network {
++	/* These entries are used to identify a unique network */
++	u8 bssid[ETH_ALEN];
++	u8 channel;
++	/* Ensure null-terminated for any debug msgs */
++	u8 ssid[IW_ESSID_MAX_SIZE + 1];
++	u8 ssid_len;
++	u8	rssi;	/* relative signal strength */
++	u8	sq;		/* signal quality */
++
++	/* These are network statistics */
++	/* struct ieee80211_rx_stats stats; */
++	u16 capability;
++	u16	aid;
++	u8 rates[MAX_RATES_LENGTH];
++	u8 rates_len;
++	u8 rates_ex[MAX_RATES_EX_LENGTH];
++	u8 rates_ex_len;
++
++	u8 edca_parmsets[18];
++
++	u8 mode;
++	u8 flags;
++	u8 time_stamp[8];
++	u16 beacon_interval;
++	u16 listen_interval;
++	u16 atim_window;
++	u8 wpa_ie[MAX_WPA_IE_LEN];
++	size_t wpa_ie_len;
++	u8 rsn_ie[MAX_WPA_IE_LEN];
++	size_t rsn_ie_len;
++	u8 country[6];
++	u8 dtim_period;
++	u8 dtim_data;
++	u8 power_constraint;
++	u8 qosinfo;
++	u8 qbssload[5];
++	u8 network_type;
++	int join_res;
++	unsigned long	last_scanned;
++};
++#endif
++/*
++join_res:
++-1: authentication fail
++-2: association fail
++> 0: TID
++*/
++
++#ifndef PLATFORM_FREEBSD /* Baron BSD has already defined */
++
++enum ieee80211_state {
++
++	/* the card is not linked at all */
++	IEEE80211_NOLINK = 0,
++
++	/* IEEE80211_ASSOCIATING* are for BSS client mode
++	 * the driver shall not perform RX filtering unless
++	 * the state is LINKED.
++	 * The driver shall just check for the state LINKED and
++	 * defaults to NOLINK for ALL the other states (including
++	 * LINKED_SCANNING)
++	 */
++
++	/* the association procedure will start (wq scheduling)*/
++	IEEE80211_ASSOCIATING,
++	IEEE80211_ASSOCIATING_RETRY,
++
++	/* the association procedure is sending AUTH request*/
++	IEEE80211_ASSOCIATING_AUTHENTICATING,
++
++	/* the association procedure has successfully authentcated
++	 * and is sending association request
++	 */
++	IEEE80211_ASSOCIATING_AUTHENTICATED,
++
++	/* the link is ok. the card associated to a BSS or linked
++	 * to a ibss cell or acting as an AP and creating the bss
++	 */
++	IEEE80211_LINKED,
++
++	/* same as LINKED, but the driver shall apply RX filter
++	 * rules as we are in NO_LINK mode. As the card is still
++	 * logically linked, but it is doing a syncro site survey
++	 * then it will be back to LINKED state.
++	 */
++	IEEE80211_LINKED_SCANNING,
++
++};
++#endif /* PLATFORM_FREEBSD */
++
++#define DEFAULT_MAX_SCAN_AGE (15 * HZ)
++#define DEFAULT_FTS 2346
++#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
++#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5]
++#define MAC_SFMT "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx"
++#define MAC_SARG(x) ((u8*)(x)),((u8*)(x)) + 1,((u8*)(x)) + 2,((u8*)(x)) + 3,((u8*)(x)) + 4,((u8*)(x)) + 5
++#define IP_FMT "%d.%d.%d.%d"
++#define IP_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3]
++#define PORT_FMT "%u"
++#define PORT_ARG(x) ntohs(*((u16 *)(x)))
++
++#define is_multicast_mac_addr(Addr) ((((Addr[0]) & 0x01) == 0x01) && ((Addr[0]) != 0xff))
++#define is_broadcast_mac_addr(Addr) ((((Addr[0]) & 0xff) == 0xff) && (((Addr[1]) & 0xff) == 0xff) && \
++	(((Addr[2]) & 0xff) == 0xff) && (((Addr[3]) & 0xff) == 0xff) && (((Addr[4]) & 0xff) == 0xff) && \
++				     (((Addr[5]) & 0xff) == 0xff))
++#define is_zero_mac_addr(Addr)	((Addr[0] == 0x00) && (Addr[1] == 0x00) && (Addr[2] == 0x00) &&   \
++                (Addr[3] == 0x00) && (Addr[4] == 0x00) && (Addr[5] == 0x00))
++
++
++#define CFG_IEEE80211_RESERVE_FCS (1<<0)
++#define CFG_IEEE80211_COMPUTE_FCS (1<<1)
++
++typedef struct tx_pending_t {
++	int frag;
++	struct ieee80211_txb *txb;
++} tx_pending_t;
++
++
++
++#define TID_NUM	16
++
++#define IEEE_A            (1<<0)
++#define IEEE_B            (1<<1)
++#define IEEE_G            (1<<2)
++#define IEEE_MODE_MASK    (IEEE_A | IEEE_B | IEEE_G)
++
++/* Baron move to ieee80211.c */
++int ieee80211_is_empty_essid(const char *essid, int essid_len);
++int ieee80211_get_hdrlen(u16 fc);
++
++#if 0
++	/* Action frame categories (IEEE 802.11-2007, 7.3.1.11, Table 7-24) */
++	#define WLAN_ACTION_SPECTRUM_MGMT 0
++	#define WLAN_ACTION_QOS 1
++	#define WLAN_ACTION_DLS 2
++	#define WLAN_ACTION_BLOCK_ACK 3
++	#define WLAN_ACTION_RADIO_MEASUREMENT 5
++	#define WLAN_ACTION_FT 6
++	#define WLAN_ACTION_SA_QUERY 8
++	#define WLAN_ACTION_WMM 17
++#endif
++
++
++/* Action category code */
++enum rtw_ieee80211_category {
++	RTW_WLAN_CATEGORY_SPECTRUM_MGMT = 0,
++	RTW_WLAN_CATEGORY_QOS = 1,
++	RTW_WLAN_CATEGORY_DLS = 2,
++	RTW_WLAN_CATEGORY_BACK = 3,
++	RTW_WLAN_CATEGORY_PUBLIC = 4, /* IEEE 802.11 public action frames */
++	RTW_WLAN_CATEGORY_RADIO_MEAS = 5,
++	RTW_WLAN_CATEGORY_FT = 6,
++	RTW_WLAN_CATEGORY_HT = 7,
++	RTW_WLAN_CATEGORY_SA_QUERY = 8,
++	RTW_WLAN_CATEGORY_WNM = 10,
++	RTW_WLAN_CATEGORY_UNPROTECTED_WNM = 11, /* add for CONFIG_IEEE80211W, none 11w also can use */
++	RTW_WLAN_CATEGORY_TDLS = 12,
++	RTW_WLAN_CATEGORY_MESH = 13,
++	RTW_WLAN_CATEGORY_MULTIHOP = 14,
++	RTW_WLAN_CATEGORY_SELF_PROTECTED = 15,
++	RTW_WLAN_CATEGORY_WMM = 17,
++	RTW_WLAN_CATEGORY_VHT = 21,
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	RTW_WLAN_CATEGORY_TBTX = 25,
++#endif
++	RTW_WLAN_CATEGORY_P2P = 0x7f,/* P2P action frames */
++};
++
++#define CATEGORY_IS_GROUP_PRIVACY(cat) \
++	(cat == RTW_WLAN_CATEGORY_MESH || cat == RTW_WLAN_CATEGORY_MULTIHOP)
++
++#define CATEGORY_IS_NON_ROBUST(cat) \
++	(cat == RTW_WLAN_CATEGORY_PUBLIC \
++	|| cat == RTW_WLAN_CATEGORY_HT \
++	|| cat == RTW_WLAN_CATEGORY_UNPROTECTED_WNM \
++	|| cat == RTW_WLAN_CATEGORY_SELF_PROTECTED \
++	|| cat == RTW_WLAN_CATEGORY_VHT \
++	|| cat == RTW_WLAN_CATEGORY_P2P)
++
++#define CATEGORY_IS_ROBUST(cat) !CATEGORY_IS_NON_ROBUST(cat)
++
++/* SPECTRUM_MGMT action code */
++enum rtw_ieee80211_spectrum_mgmt_actioncode {
++	RTW_WLAN_ACTION_SPCT_MSR_REQ = 0,
++	RTW_WLAN_ACTION_SPCT_MSR_RPRT = 1,
++	RTW_WLAN_ACTION_SPCT_TPC_REQ = 2,
++	RTW_WLAN_ACTION_SPCT_TPC_RPRT = 3,
++	RTW_WLAN_ACTION_SPCT_CHL_SWITCH = 4,
++	RTW_WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,
++};
++
++/* SELF_PROTECTED action code */
++enum rtw_ieee80211_self_protected_actioncode {
++	RTW_ACT_SELF_PROTECTED_RSVD = 0,
++	RTW_ACT_SELF_PROTECTED_MESH_OPEN = 1,
++	RTW_ACT_SELF_PROTECTED_MESH_CONF = 2,
++	RTW_ACT_SELF_PROTECTED_MESH_CLOSE = 3,
++	RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM = 4,
++	RTW_ACT_SELF_PROTECTED_MESH_GK_ACK = 5,
++	RTW_ACT_SELF_PROTECTED_NUM,
++};
++
++/* MESH action code */
++enum rtw_ieee80211_mesh_actioncode {
++	RTW_ACT_MESH_LINK_METRIC_REPORT,
++	RTW_ACT_MESH_HWMP_PATH_SELECTION,
++	RTW_ACT_MESH_GATE_ANNOUNCEMENT,
++	RTW_ACT_MESH_CONGESTION_CONTROL_NOTIFICATION,
++	RTW_ACT_MESH_MCCA_SETUP_REQUEST,
++	RTW_ACT_MESH_MCCA_SETUP_REPLY,
++	RTW_ACT_MESH_MCCA_ADVERTISEMENT_REQUEST,
++	RTW_ACT_MESH_MCCA_ADVERTISEMENT,
++	RTW_ACT_MESH_MCCA_TEARDOWN,
++	RTW_ACT_MESH_TBTT_ADJUSTMENT_REQUEST,
++	RTW_ACT_MESH_TBTT_ADJUSTMENT_RESPONSE,
++};
++
++enum _PUBLIC_ACTION {
++	ACT_PUBLIC_BSSCOEXIST = 0, /* 20/40 BSS Coexistence */
++	ACT_PUBLIC_DSE_ENABLE = 1,
++	ACT_PUBLIC_DSE_DEENABLE = 2,
++	ACT_PUBLIC_DSE_REG_LOCATION = 3,
++	ACT_PUBLIC_EXT_CHL_SWITCH = 4,
++	ACT_PUBLIC_DSE_MSR_REQ = 5,
++	ACT_PUBLIC_DSE_MSR_RPRT = 6,
++	ACT_PUBLIC_MP = 7, /* Measurement Pilot */
++	ACT_PUBLIC_DSE_PWR_CONSTRAINT = 8,
++	ACT_PUBLIC_VENDOR = 9, /* for WIFI_DIRECT */
++	ACT_PUBLIC_GAS_INITIAL_REQ = 10,
++	ACT_PUBLIC_GAS_INITIAL_RSP = 11,
++	ACT_PUBLIC_GAS_COMEBACK_REQ = 12,
++	ACT_PUBLIC_GAS_COMEBACK_RSP = 13,
++	ACT_PUBLIC_TDLS_DISCOVERY_RSP = 14,
++	ACT_PUBLIC_LOCATION_TRACK = 15,
++	ACT_PUBLIC_MAX
++};
++
++#ifdef CONFIG_TDLS
++enum TDLS_ACTION_FIELD {
++	TDLS_SETUP_REQUEST = 0,
++	TDLS_SETUP_RESPONSE = 1,
++	TDLS_SETUP_CONFIRM = 2,
++	TDLS_TEARDOWN = 3,
++	TDLS_PEER_TRAFFIC_INDICATION = 4,
++	TDLS_CHANNEL_SWITCH_REQUEST = 5,
++	TDLS_CHANNEL_SWITCH_RESPONSE = 6,
++	TDLS_PEER_PSM_REQUEST = 7,
++	TDLS_PEER_PSM_RESPONSE = 8,
++	TDLS_PEER_TRAFFIC_RESPONSE = 9,
++	TDLS_DISCOVERY_REQUEST = 10,
++	TDLS_DISCOVERY_RESPONSE = 14,	/* it's used in public action frame */
++};
++
++#define	TUNNELED_PROBE_REQ	15
++#define	TUNNELED_PROBE_RSP	16
++#endif /* CONFIG_TDLS */
++
++/* BACK action code */
++enum rtw_ieee80211_back_actioncode {
++	RTW_WLAN_ACTION_ADDBA_REQ = 0,
++	RTW_WLAN_ACTION_ADDBA_RESP = 1,
++	RTW_WLAN_ACTION_DELBA = 2,
++};
++
++/* HT features action code */
++enum rtw_ieee80211_ht_actioncode {
++	RTW_WLAN_ACTION_HT_NOTI_CHNL_WIDTH = 0,
++	RTW_WLAN_ACTION_HT_SM_PS = 1,
++	RTW_WLAN_ACTION_HT_PSMP = 2,
++	RTW_WLAN_ACTION_HT_SET_PCO_PHASE = 3,
++	RTW_WLAN_ACTION_HT_CSI = 4,
++	RTW_WLAN_ACTION_HT_NON_COMPRESS_BEAMFORMING = 5,
++	RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING = 6,
++	RTW_WLAN_ACTION_HT_ASEL_FEEDBACK = 7,
++};
++
++/* BACK (block-ack) parties */
++enum rtw_ieee80211_back_parties {
++	RTW_WLAN_BACK_RECIPIENT = 0,
++	RTW_WLAN_BACK_INITIATOR = 1,
++	RTW_WLAN_BACK_TIMER = 2,
++};
++
++/*20/40 BSS Coexistence element */
++#define RTW_WLAN_20_40_BSS_COEX_INFO_REQ            BIT(0)
++#define RTW_WLAN_20_40_BSS_COEX_40MHZ_INTOL         BIT(1)
++#define RTW_WLAN_20_40_BSS_COEX_20MHZ_WIDTH_REQ     BIT(2)
++#define RTW_WLAN_20_40_BSS_COEX_OBSS_EXEMPT_REQ     BIT(3)
++#define RTW_WLAN_20_40_BSS_COEX_OBSS_EXEMPT_GRNT    BIT(4)
++
++/* VHT features action code */
++enum rtw_ieee80211_vht_actioncode {
++	RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING = 0,
++	RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT = 1,
++	RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION = 2,
++};
++
++#define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs)
++				* 00:50:F2 */
++#ifndef PLATFORM_FREEBSD /* Baron BSD has defined */
++	#define WME_OUI_TYPE 2
++#endif /* PLATFORM_FREEBSD */
++#define WME_OUI_SUBTYPE_INFORMATION_ELEMENT 0
++#define WME_OUI_SUBTYPE_PARAMETER_ELEMENT 1
++#define WME_OUI_SUBTYPE_TSPEC_ELEMENT 2
++#define WME_VERSION 1
++
++#define WME_ACTION_CODE_SETUP_REQUEST 0
++#define WME_ACTION_CODE_SETUP_RESPONSE 1
++#define WME_ACTION_CODE_TEARDOWN 2
++
++#define WME_SETUP_RESPONSE_STATUS_ADMISSION_ACCEPTED 0
++#define WME_SETUP_RESPONSE_STATUS_INVALID_PARAMETERS 1
++#define WME_SETUP_RESPONSE_STATUS_REFUSED 3
++
++#define WME_TSPEC_DIRECTION_UPLINK 0
++#define WME_TSPEC_DIRECTION_DOWNLINK 1
++#define WME_TSPEC_DIRECTION_BI_DIRECTIONAL 3
++
++
++#define OUI_BROADCOM 0x00904c /* Broadcom (Epigram) */
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++#define OUI_REALTEK	0x00e04c /* Realtek */
++#endif
++#define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */
++
++enum rtw_ieee80211_rann_flags {
++	RTW_RANN_FLAG_IS_GATE = 1 << 0,
++};
++
++/**
++ * enum rtw_ieee80211_preq_flags - mesh PREQ element flags
++ *
++ * @RTW_IEEE80211_PREQ_IS_GATE_FLAG: Gate Announcement subfield
++ * @RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG: proactive PREP subfield
++ */
++enum rtw_ieee80211_preq_flags {
++	RTW_IEEE80211_PREQ_IS_GATE_FLAG = 1 << 0,
++	RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG	= 1 << 2,
++};
++
++/**
++ * enum rtw_ieee80211_preq_target_flags - mesh PREQ element per target flags
++ *
++ * @RTW_IEEE80211_PREQ_TO_FLAG: target only subfield
++ * @RTW_IEEE80211_PREQ_USN_FLAG: unknown target HWMP sequence number subfield
++ */
++enum rtw_ieee80211_preq_target_flags {
++	RTW_IEEE80211_PREQ_TO_FLAG	= 1<<0,
++	RTW_IEEE80211_PREQ_USN_FLAG	= 1<<2,
++};
++
++/**
++ * enum rtw_ieee80211_root_mode_identifier - root mesh STA mode identifier
++ *
++ * These attribute are used by dot11MeshHWMPRootMode to set root mesh STA mode
++ *
++ * @RTW_IEEE80211_ROOTMODE_NO_ROOT: the mesh STA is not a root mesh STA (default)
++ * @RTW_IEEE80211_ROOTMODE_ROOT: the mesh STA is a root mesh STA if greater than
++ *	this value
++ * @RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP: the mesh STA is a root mesh STA supports
++ *	the proactive PREQ with proactive PREP subfield set to 0
++ * @RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP: the mesh STA is a root mesh STA
++ *	supports the proactive PREQ with proactive PREP subfield set to 1
++ * @RTW_IEEE80211_PROACTIVE_RANN: the mesh STA is a root mesh STA supports
++ *	the proactive RANN
++ */
++enum rtw_ieee80211_root_mode_identifier {
++	RTW_IEEE80211_ROOTMODE_NO_ROOT = 0,
++	RTW_IEEE80211_ROOTMODE_ROOT = 1,
++	RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP = 2,
++	RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP = 3,
++	RTW_IEEE80211_PROACTIVE_RANN = 4,
++};
++
++/**
++ * enum rtw_ieee80211_channel_flags - channel flags
++ *
++ * Channel flags set by the regulatory control code.
++ *
++ * @RTW_IEEE80211_CHAN_DISABLED: This channel is disabled.
++ * @RTW_IEEE80211_CHAN_PASSIVE_SCAN: Only passive scanning is permitted
++ *      on this channel.
++ * @RTW_IEEE80211_CHAN_NO_IBSS: IBSS is not allowed on this channel.
++ * @RTW_IEEE80211_CHAN_RADAR: Radar detection is required on this channel.
++ * @RTW_IEEE80211_CHAN_NO_HT40PLUS: extension channel above this channel
++ *      is not permitted.
++ * @RTW_IEEE80211_CHAN_NO_HT40MINUS: extension channel below this channel
++ *      is not permitted.
++ */
++enum rtw_ieee80211_channel_flags {
++	RTW_IEEE80211_CHAN_DISABLED         = 1 << 0,
++	RTW_IEEE80211_CHAN_PASSIVE_SCAN     = 1 << 1,
++	RTW_IEEE80211_CHAN_NO_IBSS          = 1 << 2,
++	RTW_IEEE80211_CHAN_RADAR            = 1 << 3,
++	RTW_IEEE80211_CHAN_NO_HT40PLUS      = 1 << 4,
++	RTW_IEEE80211_CHAN_NO_HT40MINUS     = 1 << 5,
++};
++
++#define RTW_IEEE80211_CHAN_NO_HT40 \
++	(RTW_IEEE80211_CHAN_NO_HT40PLUS | RTW_IEEE80211_CHAN_NO_HT40MINUS)
++
++/* Represent channel details, subset of ieee80211_channel */
++struct rtw_ieee80211_channel {
++	/* enum ieee80211_band band; */
++	/* u16 center_freq; */
++	u16 hw_value;
++	u32 flags;
++	/* int max_antenna_gain; */
++	/* int max_power; */
++	/* int max_reg_power; */
++	/* bool beacon_found; */
++	/* u32 orig_flags; */
++	/* int orig_mag; */
++	/* int orig_mpwr; */
++};
++
++#define CHAN_FMT \
++	/*"band:%d, "*/ \
++	/*"center_freq:%u, "*/ \
++	"hw_value:%u, " \
++	"flags:0x%08x" \
++	/*"max_antenna_gain:%d\n"*/ \
++	/*"max_power:%d\n"*/ \
++	/*"max_reg_power:%d\n"*/ \
++	/*"beacon_found:%u\n"*/ \
++	/*"orig_flags:0x%08x\n"*/ \
++	/*"orig_mag:%d\n"*/ \
++	/*"orig_mpwr:%d\n"*/
++
++#define CHAN_ARG(channel) \
++	/*(channel)->band*/ \
++	/*, (channel)->center_freq*/ \
++	(channel)->hw_value \
++	, (channel)->flags \
++	/*, (channel)->max_antenna_gain*/ \
++	/*, (channel)->max_power*/ \
++	/*, (channel)->max_reg_power*/ \
++	/*, (channel)->beacon_found*/ \
++	/*, (channel)->orig_flags*/ \
++	/*, (channel)->orig_mag*/ \
++	/*, (channel)->orig_mpwr*/ \
++
++/* Parsed Information Elements */
++struct rtw_ieee802_11_elems {
++	u8 *ssid;
++	u8 ssid_len;
++	u8 *supp_rates;
++	u8 supp_rates_len;
++	u8 *fh_params;
++	u8 fh_params_len;
++	u8 *ds_params;
++	u8 ds_params_len;
++	u8 *cf_params;
++	u8 cf_params_len;
++	u8 *tim;
++	u8 tim_len;
++	u8 *ibss_params;
++	u8 ibss_params_len;
++	u8 *challenge;
++	u8 challenge_len;
++	u8 *erp_info;
++	u8 erp_info_len;
++	u8 *ext_supp_rates;
++	u8 ext_supp_rates_len;
++	u8 *wpa_ie;
++	u8 wpa_ie_len;
++	u8 *rsn_ie;
++	u8 rsn_ie_len;
++	u8 *wme;
++	u8 wme_len;
++	u8 *wme_tspec;
++	u8 wme_tspec_len;
++	u8 *wps_ie;
++	u8 wps_ie_len;
++	u8 *power_cap;
++	u8 power_cap_len;
++	u8 *supp_channels;
++	u8 supp_channels_len;
++	u8 *mdie;
++	u8 mdie_len;
++	u8 *ftie;
++	u8 ftie_len;
++	u8 *timeout_int;
++	u8 timeout_int_len;
++	u8 *ht_capabilities;
++	u8 ht_capabilities_len;
++	u8 *ht_operation;
++	u8 ht_operation_len;
++	u8 *vendor_ht_cap;
++	u8 vendor_ht_cap_len;
++	u8 *vht_capabilities;
++	u8 vht_capabilities_len;
++	u8 *vht_operation;
++	u8 vht_operation_len;
++	u8 *vht_op_mode_notify;
++	u8 vht_op_mode_notify_len;
++	u8 *rm_en_cap;
++	u8 rm_en_cap_len;
++#ifdef CONFIG_RTW_MESH
++	u8 *preq;
++	u8 preq_len;
++	u8 *prep;
++	u8 prep_len;
++	u8 *perr;
++	u8 perr_len;
++	u8 *rann;
++	u8 rann_len;
++#endif
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	u8 *tbtx_cap;
++	u8 tbtx_cap_len;
++#endif
++};
++
++typedef enum { ParseOK = 0, ParseUnknown = 1, ParseFailed = -1 } ParseRes;
++
++ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len,
++				struct rtw_ieee802_11_elems *elems,
++				int show_errors);
++
++u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, unsigned int *frlen);
++u8 *rtw_set_ie(u8 *pbuf, sint index, uint len, const u8 *source, uint *frlen);
++
++enum secondary_ch_offset {
++	SCN = 0, /* no secondary channel */
++	SCA = 1, /* secondary channel above */
++	SCB = 3,  /* secondary channel below */
++};
++u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset);
++u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset);
++u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode, u8 new_ch, u8 ch_switch_cnt);
++u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset);
++u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, u8 flags, u16 reason, u16 precedence);
++
++u8 *rtw_get_ie(const u8 *pbuf, sint index, sint *len, sint limit);
++u8 rtw_update_rate_bymode(WLAN_BSSID_EX *pbss_network, u32 mode);
++
++u8 *rtw_get_ie_ex(const u8 *in_ie, uint in_len, u8 eid, const u8 *oui, u8 oui_len, u8 *ie, uint *ielen);
++int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len);
++
++void rtw_set_supported_rate(u8 *SupportedRates, uint mode) ;
++
++#define GET_RSN_CAP_MFP_OPTION(cap)	LE_BITS_TO_2BYTE(((u8 *)(cap)), 6, 2)
++
++#define MFP_NO			0
++#define MFP_INVALID		1
++#define MFP_OPTIONAL	2
++#define MFP_REQUIRED	3
++
++struct rsne_info {
++	u8 *gcs;
++	u16 pcs_cnt;
++	u8 *pcs_list;
++	u16 akm_cnt;
++	u8 *akm_list;
++	u8 *cap;
++	u16 pmkid_cnt;
++	u8 *pmkid_list;
++	u8 *gmcs;
++
++	u8 err;
++};
++int rtw_rsne_info_parse(const u8 *ie, uint ie_len, struct rsne_info *info);
++
++unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit);
++unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit);
++int rtw_get_wpa_cipher_suite(u8 *s);
++int rtw_get_rsn_cipher_suite(u8 *s);
++int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len);
++int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, u32 *akm);
++int rtw_parse_wpa2_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *gmcs, u32 *akm, u8 *mfp_opt);
++
++int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie, u16 *wpa_len);
++
++u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen);
++u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, enum bss_type frame_type);
++u8 *rtw_get_wps_ie(const u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen);
++u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_attr, u32 *len_attr);
++u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_content, uint *len_content);
++
++u8 *rtw_get_owe_ie(const u8 *in_ie, uint in_len, u8 *owe_ie, uint *owe_ielen);
++
++/**
++ * for_each_ie - iterate over continuous IEs
++ * @ie:
++ * @buf:
++ * @buf_len:
++ */
++#define for_each_ie(ie, buf, buf_len) \
++	for (ie = (void *)buf; (((u8 *)ie) - ((u8 *)buf) + 1) < buf_len; ie = (void *)(((u8 *)ie) + *(((u8 *)ie)+1) + 2))
++
++void dump_ies(void *sel, const u8 *buf, u32 buf_len);
++
++#ifdef CONFIG_80211N_HT
++#define HT_SC_OFFSET_MAX 4
++extern const char *const _ht_sc_offset_str[];
++#define ht_sc_offset_str(sc) (((sc) >= HT_SC_OFFSET_MAX) ? _ht_sc_offset_str[2] : _ht_sc_offset_str[(sc)])
++
++void dump_ht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len);
++#endif
++
++void dump_wps_ie(void *sel, const u8 *ie, u32 ie_len);
++
++void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht);
++
++void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht);
++
++bool rtw_is_chbw_grouped(u8 ch_a, u8 bw_a, u8 offset_a
++	, u8 ch_b, u8 bw_b, u8 offset_b);
++void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset
++	, u8 *g_ch, u8 *g_bw, u8 *g_offset);
++
++u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len);
++int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie);
++void dump_p2p_ie(void *sel, const u8 *ie, u32 ie_len);
++u8 *rtw_get_p2p_ie(const u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen);
++u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr);
++u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content);
++u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr);
++uint rtw_del_p2p_ie(u8 *ies, uint ies_len_ori, const char *msg);
++uint rtw_del_p2p_attr(u8 *ie, uint ielen_ori, u8 attr_id);
++u8 *rtw_bss_ex_get_p2p_ie(WLAN_BSSID_EX *bss_ex, u8 *p2p_ie, uint *p2p_ielen);
++void rtw_bss_ex_del_p2p_ie(WLAN_BSSID_EX *bss_ex);
++void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id);
++
++void dump_wfd_ie(void *sel, const u8 *ie, u32 ie_len);
++u8 *rtw_get_wfd_ie(const u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen);
++u8 *rtw_get_wfd_attr(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr);
++u8 *rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content);
++uint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg);
++uint rtw_del_wfd_attr(u8 *ie, uint ielen_ori, u8 attr_id);
++u8 *rtw_bss_ex_get_wfd_ie(WLAN_BSSID_EX *bss_ex, u8 *wfd_ie, uint *wfd_ielen);
++void rtw_bss_ex_del_wfd_ie(WLAN_BSSID_EX *bss_ex);
++void rtw_bss_ex_del_wfd_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id);
++
++#define MULTI_AP_SUB_ELEM_TYPE 0x06
++#define MULTI_AP_TEAR_DOWN BIT(4)
++#define MULTI_AP_FRONTHAUL_BSS BIT(5)
++#define MULTI_AP_BACKHAUL_BSS BIT(6)
++#define MULTI_AP_BACKHAUL_STA BIT(7)
++#ifdef CONFIG_RTW_MULTI_AP
++void dump_multi_ap_ie(void *sel, const u8 *ie, u32 ie_len);
++u8 rtw_get_multi_ap_ie_ext(const u8 *ies, int ies_len);
++u8 *rtw_set_multi_ap_ie_ext(u8 *pbuf, uint *frlen, u8 val);
++#endif
++
++uint	rtw_get_rateset_len(u8	*rateset);
++
++struct registry_priv;
++int rtw_generate_ie(struct registry_priv *pregistrypriv);
++
++int rtw_get_bit_value_from_ieee_value(u8 val);
++
++uint	rtw_is_cckrates_included(u8 *rate);
++
++uint	rtw_is_cckratesonly_included(u8 *rate);
++uint rtw_get_cckrate_size(u8 *rate,u32 rate_length);
++int rtw_check_network_type(unsigned char *rate, int ratelen, int channel);
++
++u8 rtw_check_invalid_mac_address(u8 *mac_addr, u8 check_local_bit);
++void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr);
++
++u16 rtw_ht_mcs_rate(u8 bw_40MHz, u8 short_GI, unsigned char *MCS_rate);
++u8	rtw_ht_mcsset_to_nss(u8 *supp_mcs_set);
++u32	rtw_ht_mcs_set_to_bitmap(u8 *mcs_set, u8 nss);
++
++int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8 *category, u8 *action);
++const char *action_public_str(u8 action);
++
++u8 key_2char2num(u8 hch, u8 lch);
++u8 str_2char2num(u8 hch, u8 lch);
++void macstr2num(u8 *dst, u8 *src);
++u8 convert_ip_addr(u8 hch, u8 mch, u8 lch);
++int wifirate2_ratetbl_inx(unsigned char rate);
++
++
++#endif /* IEEE80211_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/ieee80211_ext.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/ieee80211_ext.h
+new file mode 100644
+index 000000000..4965863c4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/ieee80211_ext.h
+@@ -0,0 +1,312 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __IEEE80211_EXT_H
++#define __IEEE80211_EXT_H
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++#define WMM_OUI_TYPE 2
++#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0
++#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1
++#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2
++#define WMM_VERSION 1
++
++#define WPA_PROTO_WPA BIT(0)
++#define WPA_PROTO_RSN BIT(1)
++
++#define WPA_KEY_MGMT_IEEE8021X BIT(0)
++#define WPA_KEY_MGMT_PSK BIT(1)
++#define WPA_KEY_MGMT_NONE BIT(2)
++#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3)
++#define WPA_KEY_MGMT_WPA_NONE BIT(4)
++
++
++#define WPA_CAPABILITY_PREAUTH BIT(0)
++#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6)
++#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9)
++
++
++#define PMKID_LEN 16
++
++
++#ifdef PLATFORM_LINUX
++struct wpa_ie_hdr {
++	u8 elem_id;
++	u8 len;
++	u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
++	u8 version[2]; /* little endian */
++} __attribute__((packed));
++
++struct rsn_ie_hdr {
++	u8 elem_id; /* WLAN_EID_RSN */
++	u8 len;
++	u8 version[2]; /* little endian */
++} __attribute__((packed));
++
++struct wme_ac_parameter {
++#if defined(CONFIG_LITTLE_ENDIAN)
++	/* byte 1 */
++	u8	aifsn:4,
++	     acm:1,
++	     aci:2,
++	     reserved:1;
++
++	/* byte 2 */
++	u8	eCWmin:4,
++	     eCWmax:4;
++#elif defined(CONFIG_BIG_ENDIAN)
++	/* byte 1 */
++	u8	reserved:1,
++	     aci:2,
++	     acm:1,
++	     aifsn:4;
++
++	/* byte 2 */
++	u8	eCWmax:4,
++	     eCWmin:4;
++#else
++#error	"Please fix <endian.h>"
++#endif
++
++	/* bytes 3 & 4 */
++	u16 txopLimit;
++} __attribute__((packed));
++
++struct wme_parameter_element {
++	/* required fields for WME version 1 */
++	u8 oui[3];
++	u8 oui_type;
++	u8 oui_subtype;
++	u8 version;
++	u8 acInfo;
++	u8 reserved;
++	struct wme_ac_parameter ac[4];
++
++} __attribute__((packed));
++
++#endif
++
++#define WPA_PUT_LE16(a, val)			\
++	do {					\
++		(a)[1] = ((u16) (val)) >> 8;	\
++		(a)[0] = ((u16) (val)) & 0xff;	\
++	} while (0)
++
++#define WPA_PUT_BE32(a, val)					\
++	do {							\
++		(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
++		(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
++		(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
++		(a)[3] = (u8) (((u32) (val)) & 0xff);		\
++	} while (0)
++
++#define WPA_PUT_LE32(a, val)					\
++	do {							\
++		(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
++		(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
++		(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
++		(a)[0] = (u8) (((u32) (val)) & 0xff);		\
++	} while (0)
++
++#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val))
++/* #define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val)) */
++
++
++
++/* Action category code */
++enum ieee80211_category {
++	WLAN_CATEGORY_SPECTRUM_MGMT = 0,
++	WLAN_CATEGORY_QOS = 1,
++	WLAN_CATEGORY_DLS = 2,
++	WLAN_CATEGORY_BACK = 3,
++	WLAN_CATEGORY_HT = 7,
++	WLAN_CATEGORY_WMM = 17,
++};
++
++/* SPECTRUM_MGMT action code */
++enum ieee80211_spectrum_mgmt_actioncode {
++	WLAN_ACTION_SPCT_MSR_REQ = 0,
++	WLAN_ACTION_SPCT_MSR_RPRT = 1,
++	WLAN_ACTION_SPCT_TPC_REQ = 2,
++	WLAN_ACTION_SPCT_TPC_RPRT = 3,
++	WLAN_ACTION_SPCT_CHL_SWITCH = 4,
++	WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,
++};
++
++/* BACK action code */
++enum ieee80211_back_actioncode {
++	WLAN_ACTION_ADDBA_REQ = 0,
++	WLAN_ACTION_ADDBA_RESP = 1,
++	WLAN_ACTION_DELBA = 2,
++};
++
++/* HT features action code */
++enum ieee80211_ht_actioncode {
++	WLAN_ACTION_NOTIFY_CH_WIDTH = 0,
++	WLAN_ACTION_SM_PS = 1,
++	WLAN_ACTION_PSPM = 2,
++	WLAN_ACTION_PCO_PHASE = 3,
++	WLAN_ACTION_MIMO_CSI_MX = 4,
++	WLAN_ACTION_MIMO_NONCP_BF = 5,
++	WLAN_ACTION_MIMP_CP_BF = 6,
++	WLAN_ACTION_ASEL_INDICATES_FB = 7,
++	WLAN_ACTION_HI_INFO_EXCHG = 8,
++};
++
++/* BACK (block-ack) parties */
++enum ieee80211_back_parties {
++	WLAN_BACK_RECIPIENT = 0,
++	WLAN_BACK_INITIATOR = 1,
++	WLAN_BACK_TIMER = 2,
++};
++
++#ifdef PLATFORM_LINUX
++
++struct ieee80211_mgmt {
++	u16 frame_control;
++	u16 duration;
++	u8 da[6];
++	u8 sa[6];
++	u8 bssid[6];
++	u16 seq_ctrl;
++	union {
++		struct {
++			u16 auth_alg;
++			u16 auth_transaction;
++			u16 status_code;
++			/* possibly followed by Challenge text */
++			u8 variable[0];
++		}  __attribute__((packed)) auth;
++		struct {
++			u16 reason_code;
++		}  __attribute__((packed)) deauth;
++		struct {
++			u16 capab_info;
++			u16 listen_interval;
++			/* followed by SSID and Supported rates */
++			u8 variable[0];
++		}  __attribute__((packed)) assoc_req;
++		struct {
++			u16 capab_info;
++			u16 status_code;
++			u16 aid;
++			/* followed by Supported rates */
++			u8 variable[0];
++		}  __attribute__((packed)) assoc_resp, reassoc_resp;
++		struct {
++			u16 capab_info;
++			u16 listen_interval;
++			u8 current_ap[6];
++			/* followed by SSID and Supported rates */
++			u8 variable[0];
++		}  __attribute__((packed)) reassoc_req;
++		struct {
++			u16 reason_code;
++		}  __attribute__((packed)) disassoc;
++		struct {
++			__le64 timestamp;
++			u16 beacon_int;
++			u16 capab_info;
++			/* followed by some of SSID, Supported rates,
++			 * FH Params, DS Params, CF Params, IBSS Params, TIM */
++			u8 variable[0];
++		}  __attribute__((packed)) beacon;
++		struct {
++			/* only variable items: SSID, Supported rates */
++			u8 variable[0];
++		}  __attribute__((packed)) probe_req;
++		struct {
++			__le64 timestamp;
++			u16 beacon_int;
++			u16 capab_info;
++			/* followed by some of SSID, Supported rates,
++			 * FH Params, DS Params, CF Params, IBSS Params */
++			u8 variable[0];
++		}  __attribute__((packed)) probe_resp;
++		struct {
++			u8 category;
++			union {
++				struct {
++					u8 action_code;
++					u8 dialog_token;
++					u8 status_code;
++					u8 variable[0];
++				}  __attribute__((packed)) wme_action;
++#if 0
++				struct {
++					u8 action_code;
++					u8 element_id;
++					u8 length;
++					struct ieee80211_channel_sw_ie sw_elem;
++				}  __attribute__((packed)) chan_switch;
++				struct {
++					u8 action_code;
++					u8 dialog_token;
++					u8 element_id;
++					u8 length;
++					struct ieee80211_msrment_ie msr_elem;
++				}  __attribute__((packed)) measurement;
++#endif
++				struct {
++					u8 action_code;
++					u8 dialog_token;
++					u16 capab;
++					u16 timeout;
++					u16 start_seq_num;
++				}  __attribute__((packed)) addba_req;
++				struct {
++					u8 action_code;
++					u8 dialog_token;
++					u16 status;
++					u16 capab;
++					u16 timeout;
++				}  __attribute__((packed)) addba_resp;
++				struct {
++					u8 action_code;
++					u16 params;
++					u16 reason_code;
++				}  __attribute__((packed)) delba;
++				struct {
++					u8 action_code;
++					/* capab_info for open and confirm,
++					 * reason for close
++					 */
++					u16 aux;
++					/* Followed in plink_confirm by status
++					 * code, AID and supported rates,
++					 * and directly by supported rates in
++					 * plink_open and plink_close
++					 */
++					u8 variable[0];
++				}  __attribute__((packed)) plink_action;
++				struct {
++					u8 action_code;
++					u8 variable[0];
++				}  __attribute__((packed)) mesh_action;
++			} __attribute__((packed)) u;
++		}  __attribute__((packed)) action;
++	} __attribute__((packed)) u;
++} __attribute__((packed));
++
++#endif
++
++/* mgmt header + 1 byte category code */
++#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u)
++
++
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/if_ether.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/if_ether.h
+new file mode 100644
+index 000000000..a3007c4ab
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/if_ether.h
+@@ -0,0 +1,106 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef _LINUX_IF_ETHER_H
++#define _LINUX_IF_ETHER_H
++
++/*
++ *	IEEE 802.3 Ethernet magic constants.  The frame sizes omit the preamble
++ *	and FCS/CRC (frame check sequence).
++ */
++
++#define ETH_ALEN	6		/* Octets in one ethernet addr	 */
++#define ETH_HLEN	14		/* Total octets in header.	 */
++#define ETH_ZLEN	60		/* Min. octets in frame sans FCS */
++#define ETH_DATA_LEN	1500		/* Max. octets in payload	 */
++#define ETH_FRAME_LEN	1514		/* Max. octets in frame sans FCS */
++
++/*
++ *	These are the defined Ethernet Protocol ID's.
++ */
++
++#define ETH_P_LOOP	0x0060		/* Ethernet Loopback packet	*/
++#define ETH_P_PUP	0x0200		/* Xerox PUP packet		*/
++#define ETH_P_PUPAT	0x0201		/* Xerox PUP Addr Trans packet	*/
++#define ETH_P_IP	0x0800		/* Internet Protocol packet	*/
++#define ETH_P_X25	0x0805		/* CCITT X.25			*/
++#define ETH_P_ARP	0x0806		/* Address Resolution packet	*/
++#define	ETH_P_BPQ	0x08FF		/* G8BPQ AX.25 Ethernet Packet	[ NOT AN OFFICIALLY REGISTERED ID ] */
++#define ETH_P_IEEEPUP	0x0a00		/* Xerox IEEE802.3 PUP packet */
++#define ETH_P_IEEEPUPAT	0x0a01		/* Xerox IEEE802.3 PUP Addr Trans packet */
++#define ETH_P_DEC       0x6000          /* DEC Assigned proto          */
++#define ETH_P_DNA_DL    0x6001          /* DEC DNA Dump/Load           */
++#define ETH_P_DNA_RC    0x6002          /* DEC DNA Remote Console      */
++#define ETH_P_DNA_RT    0x6003          /* DEC DNA Routing             */
++#define ETH_P_LAT       0x6004          /* DEC LAT                     */
++#define ETH_P_DIAG      0x6005          /* DEC Diagnostics             */
++#define ETH_P_CUST      0x6006          /* DEC Customer use            */
++#define ETH_P_SCA       0x6007          /* DEC Systems Comms Arch      */
++#define ETH_P_RARP      0x8035		/* Reverse Addr Res packet	*/
++#define ETH_P_ATALK	0x809B		/* Appletalk DDP		*/
++#define ETH_P_AARP	0x80F3		/* Appletalk AARP		*/
++#define ETH_P_8021Q	0x8100          /* 802.1Q VLAN Extended Header */
++#define ETH_P_IPX	0x8137		/* IPX over DIX			*/
++#define ETH_P_IPV6	0x86DD		/* IPv6 over bluebook		*/
++#define ETH_P_PPP_DISC	0x8863		/* PPPoE discovery messages    */
++#define ETH_P_PPP_SES	0x8864		/* PPPoE session messages	*/
++#define ETH_P_ATMMPOA	0x884c		/* MultiProtocol Over ATM	*/
++#define ETH_P_ATMFATE	0x8884		/* Frame-based ATM Transport
++					 * over Ethernet
++					 */
++
++/*
++ *	Non DIX types. Won't clash for 1500 types.
++ */
++
++#define ETH_P_802_3	0x0001		/* Dummy type for 802.3 frames */
++#define ETH_P_AX25	0x0002		/* Dummy protocol id for AX.25 */
++#define ETH_P_ALL	0x0003		/* Every packet (be careful!!!) */
++#define ETH_P_802_2	0x0004		/* 802.2 frames 		*/
++#define ETH_P_SNAP	0x0005		/* Internal only		*/
++#define ETH_P_DDCMP     0x0006          /* DEC DDCMP: Internal only    */
++#define ETH_P_WAN_PPP   0x0007          /* Dummy type for WAN PPP frames*/
++#define ETH_P_PPP_MP    0x0008          /* Dummy type for PPP MP frames */
++#define ETH_P_LOCALTALK 0x0009		/* Localtalk pseudo type 	*/
++#define ETH_P_PPPTALK	0x0010		/* Dummy type for Atalk over PPP*/
++#define ETH_P_TR_802_2	0x0011		/* 802.2 frames 		*/
++#define ETH_P_MOBITEX	0x0015		/* Mobitex (kaz@cafe.net)	*/
++#define ETH_P_CONTROL	0x0016		/* Card specific control frames */
++#define ETH_P_IRDA	0x0017		/* Linux-IrDA			*/
++#define ETH_P_ECONET	0x0018		/* Acorn Econet			*/
++
++/*
++ *	This is an Ethernet frame header.
++ */
++
++struct ethhdr {
++	unsigned char	h_dest[ETH_ALEN];	/* destination eth addr	*/
++	unsigned char	h_source[ETH_ALEN];	/* source ether addr	*/
++	unsigned short	h_proto;		/* packet type ID field	*/
++};
++
++struct _vlan {
++	unsigned short       h_vlan_TCI;                /* Encapsulates priority and VLAN ID */
++	unsigned short       h_vlan_encapsulated_proto;
++};
++
++
++
++#define get_vlan_id(pvlan) ((ntohs((unsigned short)pvlan->h_vlan_TCI)) & 0xfff)
++#define get_vlan_priority(pvlan) ((ntohs((unsigned short)pvlan->h_vlan_TCI))>>13)
++#define get_vlan_encap_proto(pvlan) (ntohs((unsigned short)pvlan->h_vlan_encapsulated_proto))
++
++
++#endif	/* _LINUX_IF_ETHER_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/ip.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/ip.h
+new file mode 100644
+index 000000000..4feb98fb0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/ip.h
+@@ -0,0 +1,135 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _LINUX_IP_H
++#define _LINUX_IP_H
++
++/* SOL_IP socket options */
++
++#define IPTOS_TOS_MASK		0x1E
++#define IPTOS_TOS(tos)		((tos)&IPTOS_TOS_MASK)
++#define	IPTOS_LOWDELAY		0x10
++#define	IPTOS_THROUGHPUT	0x08
++#define	IPTOS_RELIABILITY	0x04
++#define	IPTOS_MINCOST		0x02
++
++#define IPTOS_PREC_MASK		0xE0
++#define IPTOS_PREC(tos)		((tos)&IPTOS_PREC_MASK)
++#define IPTOS_PREC_NETCONTROL           0xe0
++#define IPTOS_PREC_INTERNETCONTROL      0xc0
++#define IPTOS_PREC_CRITIC_ECP           0xa0
++#define IPTOS_PREC_FLASHOVERRIDE        0x80
++#define IPTOS_PREC_FLASH                0x60
++#define IPTOS_PREC_IMMEDIATE            0x40
++#define IPTOS_PREC_PRIORITY             0x20
++#define IPTOS_PREC_ROUTINE              0x00
++
++
++/* IP options */
++#define IPOPT_COPY		0x80
++#define IPOPT_CLASS_MASK	0x60
++#define IPOPT_NUMBER_MASK	0x1f
++
++#define	IPOPT_COPIED(o)		((o)&IPOPT_COPY)
++#define	IPOPT_CLASS(o)		((o)&IPOPT_CLASS_MASK)
++#define	IPOPT_NUMBER(o)		((o)&IPOPT_NUMBER_MASK)
++
++#define	IPOPT_CONTROL		0x00
++#define	IPOPT_RESERVED1		0x20
++#define	IPOPT_MEASUREMENT	0x40
++#define	IPOPT_RESERVED2		0x60
++
++#define IPOPT_END	(0 | IPOPT_CONTROL)
++#define IPOPT_NOOP	(1 | IPOPT_CONTROL)
++#define IPOPT_SEC	(2 | IPOPT_CONTROL | IPOPT_COPY)
++#define IPOPT_LSRR	(3 | IPOPT_CONTROL | IPOPT_COPY)
++#define IPOPT_TIMESTAMP	(4 | IPOPT_MEASUREMENT)
++#define IPOPT_RR	(7 | IPOPT_CONTROL)
++#define IPOPT_SID	(8 | IPOPT_CONTROL | IPOPT_COPY)
++#define IPOPT_SSRR	(9 | IPOPT_CONTROL | IPOPT_COPY)
++#define IPOPT_RA	(20 | IPOPT_CONTROL | IPOPT_COPY)
++
++#define IPVERSION	4
++#define MAXTTL		255
++#define IPDEFTTL	64
++
++/* struct timestamp, struct route and MAX_ROUTES are removed.
++
++   REASONS: it is clear that nobody used them because:
++   - MAX_ROUTES value was wrong.
++   - "struct route" was wrong.
++   - "struct timestamp" had fatally misaligned bitfields and was completely unusable.
++ */
++
++#define IPOPT_OPTVAL 0
++#define IPOPT_OLEN   1
++#define IPOPT_OFFSET 2
++#define IPOPT_MINOFF 4
++#define MAX_IPOPTLEN 40
++#define IPOPT_NOP IPOPT_NOOP
++#define IPOPT_EOL IPOPT_END
++#define IPOPT_TS  IPOPT_TIMESTAMP
++
++#define	IPOPT_TS_TSONLY		0		/* timestamps only */
++#define	IPOPT_TS_TSANDADDR	1		/* timestamps and addresses */
++#define	IPOPT_TS_PRESPEC	3		/* specified modules only */
++
++#ifdef PLATFORM_LINUX
++
++struct ip_options {
++	__u32		faddr;				/* Saved first hop address */
++	unsigned char	optlen;
++	unsigned char srr;
++	unsigned char rr;
++	unsigned char ts;
++	unsigned char is_setbyuser:1,			/* Set by setsockopt?			*/
++		 is_data:1,			/* Options in __data, rather than skb	*/
++		 is_strictroute:1,		/* Strict source route			*/
++		 srr_is_hit:1,			/* Packet destination addr was our one	*/
++		 is_changed:1,			/* IP checksum more not valid		*/
++		 rr_needaddr:1,			/* Need to record addr of outgoing dev	*/
++		 ts_needtime:1,			/* Need to record timestamp		*/
++		 ts_needaddr:1;			/* Need to record addr of outgoing dev */
++	unsigned char router_alert;
++	unsigned char __pad1;
++	unsigned char __pad2;
++	unsigned char __data[0];
++};
++
++#define optlength(opt) (sizeof(struct ip_options) + opt->optlen)
++#endif
++
++struct iphdr {
++#if defined(__LITTLE_ENDIAN_BITFIELD)
++	__u8	ihl:4,
++		version:4;
++#elif defined (__BIG_ENDIAN_BITFIELD)
++	__u8	version:4,
++		ihl:4;
++#else
++#error	"Please fix <asm/byteorder.h>"
++#endif
++	__u8	tos;
++	__u16	tot_len;
++	__u16	id;
++	__u16	frag_off;
++	__u8	ttl;
++	__u8	protocol;
++	__u16	check;
++	__u32	saddr;
++	__u32	daddr;
++	/*The options start here. */
++};
++
++#endif	/* _LINUX_IP_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/linux/wireless.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/linux/wireless.h
+new file mode 100644
+index 000000000..c7f4a6c9b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/linux/wireless.h
+@@ -0,0 +1,87 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef _LINUX_WIRELESS_H
++#define _LINUX_WIRELESS_H
++
++/***************************** INCLUDES *****************************/
++
++#if 0
++	#include <linux/types.h>		/* for __u* and __s* typedefs */
++	#include <linux/socket.h>		/* for "struct sockaddr" et al	*/
++	#include <linux/if.h>			/* for IFNAMSIZ and co... */
++#else
++	#define __user
++	/* typedef uint16_t	__u16; */
++	#include <sys/socket.h>			/* for "struct sockaddr" et al	*/
++	#include <net/if.h>			/* for IFNAMSIZ and co... */
++#endif
++
++/****************************** TYPES ******************************/
++#ifdef CONFIG_COMPAT
++struct compat_iw_point {
++	compat_caddr_t pointer;
++	__u16 length;
++	__u16 flags;
++};
++#endif
++/* --------------------------- SUBTYPES --------------------------- */
++/*
++ *	For all data larger than 16 octets, we need to use a
++ *	pointer to memory allocated in user space.
++ */
++struct	iw_point {
++	void __user	*pointer;	/* Pointer to the data  (in user space) */
++	__u16		length;		/* number of fields or size in bytes */
++	__u16		flags;		/* Optional params */
++};
++
++
++/* ------------------------ IOCTL REQUEST ------------------------ */
++/*
++ * This structure defines the payload of an ioctl, and is used
++ * below.
++ *
++ * Note that this structure should fit on the memory footprint
++ * of iwreq (which is the same as ifreq), which mean a max size of
++ * 16 octets = 128 bits. Warning, pointers might be 64 bits wide...
++ * You should check this when increasing the structures defined
++ * above in this file...
++ */
++union	iwreq_data {
++	/* Config - generic */
++	char		name[IFNAMSIZ];
++	/* Name : used to verify the presence of  wireless extensions.
++	 * Name of the protocol/provider... */
++
++	struct iw_point	data;		/* Other large parameters */
++};
++
++/*
++ * The structure to exchange data for ioctl.
++ * This structure is the same as 'struct ifreq', but (re)defined for
++ * convenience...
++ * Do I need to remind you about structure size (32 octets) ?
++ */
++struct	iwreq {
++	union {
++		char	ifrn_name[IFNAMSIZ];	/* if name, e.g. "eth0" */
++	} ifr_ifrn;
++
++	/* Data part (defined just above) */
++	union	iwreq_data	u;
++};
++
++#endif	/* _LINUX_WIRELESS_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/mlme_osdep.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/mlme_osdep.h
+new file mode 100644
+index 000000000..131eb0925
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/mlme_osdep.h
+@@ -0,0 +1,25 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef	__MLME_OSDEP_H_
++#define __MLME_OSDEP_H_
++
++extern void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated);
++extern void rtw_os_indicate_connect(_adapter *adapter);
++void rtw_os_indicate_scan_done(_adapter *padapter, bool aborted);
++extern void rtw_report_sec_ie(_adapter *adapter, u8 authmode, u8 *sec_ie);
++
++void rtw_reset_securitypriv(_adapter *adapter);
++
++#endif /* _MLME_OSDEP_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/nic_spec.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/nic_spec.h
+new file mode 100644
+index 000000000..913ef9ba8
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/nic_spec.h
+@@ -0,0 +1,41 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++
++#ifndef __NIC_SPEC_H__
++#define __NIC_SPEC_H__
++
++#include <drv_conf.h>
++
++#define RTL8711_MCTRL_		(0x20000)
++#define RTL8711_UART_		(0x30000)
++#define RTL8711_TIMER_		(0x40000)
++#define RTL8711_FINT_		(0x50000)
++#define RTL8711_HINT_		(0x50000)
++#define RTL8711_GPIO_		(0x60000)
++#define RTL8711_WLANCTRL_	(0x200000)
++#define RTL8711_WLANFF_		(0xe00000)
++#define RTL8711_HCICTRL_	(0x600000)
++#define RTL8711_SYSCFG_		(0x620000)
++#define RTL8711_SYSCTRL_	(0x620000)
++#define RTL8711_MCCTRL_		(0x020000)
++
++
++#include <rtl8711_regdef.h>
++
++#include <rtl8711_bitdef.h>
++
++
++#endif /* __RTL8711_SPEC_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_intf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_intf.h
+new file mode 100644
+index 000000000..5a0f01186
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_intf.h
+@@ -0,0 +1,139 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __OSDEP_INTF_H_
++#define __OSDEP_INTF_H_
++
++
++struct intf_priv {
++
++	u8 *intf_dev;
++	u32	max_iosz;	/* USB2.0: 128, USB1.1: 64, SDIO:64 */
++	u32	max_xmitsz; /* USB2.0: unlimited, SDIO:512 */
++	u32	max_recvsz; /* USB2.0: unlimited, SDIO:512 */
++
++	volatile u8 *io_rwmem;
++	volatile u8 *allocated_io_rwmem;
++	u32	io_wsz; /* unit: 4bytes */
++	u32	io_rsz;/* unit: 4bytes */
++	u8 intf_status;
++
++	void (*_bus_io)(u8 *priv);
++
++	/*
++	Under Sync. IRP (SDIO/USB)
++	A protection mechanism is necessary for the io_rwmem(read/write protocol)
++
++	Under Async. IRP (SDIO/USB)
++	The protection mechanism is through the pending queue.
++	*/
++
++	_mutex ioctl_mutex;
++
++
++#ifdef PLATFORM_LINUX
++#ifdef CONFIG_USB_HCI
++	/* when in USB, IO is through interrupt in/out endpoints */
++	struct usb_device	*udev;
++	PURB	piorw_urb;
++	u8 io_irp_cnt;
++	u8 bio_irp_pending;
++	_sema io_retevt;
++	_timer	io_timer;
++	u8 bio_irp_timeout;
++	u8 bio_timer_cancel;
++#endif
++#endif
++
++};
++
++struct dvobj_priv *devobj_init(void);
++void devobj_deinit(struct dvobj_priv *pdvobj);
++
++u8 rtw_init_drv_sw(_adapter *padapter);
++u8 rtw_free_drv_sw(_adapter *padapter);
++u8 rtw_reset_drv_sw(_adapter *padapter);
++void rtw_dev_unload(PADAPTER padapter);
++
++u32 rtw_start_drv_threads(_adapter *padapter);
++void rtw_stop_drv_threads(_adapter *padapter);
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++void rtw_cancel_dynamic_chk_timer(_adapter *padapter);
++#endif
++void rtw_cancel_all_timer(_adapter *padapter);
++
++uint loadparam(_adapter *adapter);
++
++#ifdef PLATFORM_LINUX
++int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
++
++int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname);
++struct net_device *rtw_init_netdev(_adapter *padapter);
++
++void rtw_os_ndev_free(_adapter *adapter);
++int rtw_os_ndev_init(_adapter *adapter, const char *name);
++void rtw_os_ndev_deinit(_adapter *adapter);
++void rtw_os_ndev_unregister(_adapter *adapter);
++void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj);
++int rtw_os_ndevs_init(struct dvobj_priv *dvobj);
++void rtw_os_ndevs_deinit(struct dvobj_priv *dvobj);
++
++u16 rtw_os_recv_select_queue(u8 *msdu, enum rtw_rx_llc_hdl llc_hdl);
++
++int rtw_ndev_notifier_register(void);
++void rtw_ndev_notifier_unregister(void);
++void rtw_inetaddr_notifier_register(void);
++void rtw_inetaddr_notifier_unregister(void);
++
++#include "../os_dep/linux/rtw_proc.h"
++
++#ifdef CONFIG_IOCTL_CFG80211
++	#include "../os_dep/linux/ioctl_cfg80211.h"
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++u8 rtw_rtnl_lock_needed(struct dvobj_priv *dvobj);
++void rtw_set_rtnl_lock_holder(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl);
++
++#endif /* PLATFORM_LINUX */
++
++
++#ifdef PLATFORM_FREEBSD
++extern int rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
++#endif
++
++void rtw_ips_dev_unload(_adapter *padapter);
++
++#ifdef CONFIG_IPS
++int rtw_ips_pwr_up(_adapter *padapter);
++void rtw_ips_pwr_down(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_CONCURRENT_MODE
++struct _io_ops;
++struct dvobj_priv;
++_adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, void (*set_intf_ops)(_adapter *primary_padapter, struct _io_ops *pops));
++void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj);
++void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj);
++#endif
++
++void rtw_ndev_destructor(_nic_hdl ndev);
++#ifdef CONFIG_ARP_KEEP_ALIVE
++int rtw_gw_addr_query(_adapter *padapter);
++#endif
++
++int rtw_suspend_common(_adapter *padapter);
++int rtw_resume_common(_adapter *padapter);
++
++#endif /* _OSDEP_INTF_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_service.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_service.h
+new file mode 100644
+index 000000000..3efb2f0eb
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_service.h
+@@ -0,0 +1,825 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __OSDEP_SERVICE_H_
++#define __OSDEP_SERVICE_H_
++
++
++#define _FAIL					0
++#define _SUCCESS				1
++#define RTW_RX_HANDLED			2
++#define RTW_RFRAME_UNAVAIL		3
++#define RTW_RFRAME_PKT_UNAVAIL	4
++#define RTW_RBUF_UNAVAIL		5
++#define RTW_RBUF_PKT_UNAVAIL	6
++#define RTW_SDIO_READ_PORT_FAIL	7
++#define RTW_ALREADY				8
++#define RTW_RA_RESOLVING		9
++#define RTW_BMC_NO_NEED			10
++#define RTW_XBUF_UNAVAIL		11
++#define RTW_TX_BALANCE			12
++#define RTW_TX_WAIT_MORE_FRAME	13
++
++/* #define RTW_STATUS_TIMEDOUT -110 */
++
++#undef _TRUE
++#define _TRUE		1
++
++#undef _FALSE
++#define _FALSE		0
++
++
++#ifdef PLATFORM_FREEBSD
++	#include <osdep_service_bsd.h>
++#endif
++
++#ifdef PLATFORM_LINUX
++	#include <linux/version.h>
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0))
++	#include <linux/sched/signal.h>
++	#include <linux/sched/types.h>
++#endif
++	#include <osdep_service_linux.h>
++	#include <drv_types_linux.h>
++#endif
++
++#ifdef PLATFORM_OS_XP
++	#include <osdep_service_xp.h>
++	#include <drv_types_xp.h>
++#endif
++
++#ifdef PLATFORM_OS_CE
++	#include <osdep_service_ce.h>
++	#include <drv_types_ce.h>
++#endif
++
++/* #include <rtw_byteorder.h> */
++
++#ifndef BIT
++	#define BIT(x)	(1 << (x))
++#endif
++#ifndef BIT_ULL
++#define BIT_ULL(x)	(1ULL << (x))
++#endif
++
++#define CHECK_BIT(a, b) (!!((a) & (b)))
++
++#define BIT0	0x00000001
++#define BIT1	0x00000002
++#define BIT2	0x00000004
++#define BIT3	0x00000008
++#define BIT4	0x00000010
++#define BIT5	0x00000020
++#define BIT6	0x00000040
++#define BIT7	0x00000080
++#define BIT8	0x00000100
++#define BIT9	0x00000200
++#define BIT10	0x00000400
++#define BIT11	0x00000800
++#define BIT12	0x00001000
++#define BIT13	0x00002000
++#define BIT14	0x00004000
++#define BIT15	0x00008000
++#define BIT16	0x00010000
++#define BIT17	0x00020000
++#define BIT18	0x00040000
++#define BIT19	0x00080000
++#define BIT20	0x00100000
++#define BIT21	0x00200000
++#define BIT22	0x00400000
++#define BIT23	0x00800000
++#define BIT24	0x01000000
++#define BIT25	0x02000000
++#define BIT26	0x04000000
++#define BIT27	0x08000000
++#define BIT28	0x10000000
++#define BIT29	0x20000000
++#define BIT30	0x40000000
++#define BIT31	0x80000000
++#define BIT32	0x0100000000
++#define BIT33	0x0200000000
++#define BIT34	0x0400000000
++#define BIT35	0x0800000000
++#define BIT36	0x1000000000
++
++#ifndef GENMASK
++#define GENMASK(h, l) \
++	(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
++#endif
++
++extern int RTW_STATUS_CODE(int error_code);
++
++#ifndef RTK_DMP_PLATFORM
++	#define CONFIG_USE_VMALLOC
++#endif
++
++/* flags used for rtw_mstat_update() */
++enum mstat_f {
++	/* type: 0x00ff */
++	MSTAT_TYPE_VIR = 0x00,
++	MSTAT_TYPE_PHY = 0x01,
++	MSTAT_TYPE_SKB = 0x02,
++	MSTAT_TYPE_USB = 0x03,
++	MSTAT_TYPE_MAX = 0x04,
++
++	/* func: 0xff00 */
++	MSTAT_FUNC_UNSPECIFIED = 0x00 << 8,
++	MSTAT_FUNC_IO = 0x01 << 8,
++	MSTAT_FUNC_TX_IO = 0x02 << 8,
++	MSTAT_FUNC_RX_IO = 0x03 << 8,
++	MSTAT_FUNC_TX = 0x04 << 8,
++	MSTAT_FUNC_RX = 0x05 << 8,
++	MSTAT_FUNC_CFG_VENDOR = 0x06 << 8,
++	MSTAT_FUNC_MAX = 0x07 << 8,
++};
++
++#define mstat_tf_idx(flags) ((flags) & 0xff)
++#define mstat_ff_idx(flags) (((flags) & 0xff00) >> 8)
++
++typedef enum mstat_status {
++	MSTAT_ALLOC_SUCCESS = 0,
++	MSTAT_ALLOC_FAIL,
++	MSTAT_FREE
++} MSTAT_STATUS;
++
++#ifdef DBG_MEM_ALLOC
++void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz);
++void rtw_mstat_dump(void *sel);
++bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size);
++void *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
++void *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
++void dbg_rtw_vmfree(void *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line);
++void *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
++void *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
++void dbg_rtw_mfree(void *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line);
++
++struct sk_buff *dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, const int line);
++void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
++struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
++struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
++int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);
++#ifdef CONFIG_RTW_NAPI
++int dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);
++#ifdef CONFIG_RTW_GRO
++gro_result_t dbg_rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);
++#endif
++#endif /* CONFIG_RTW_NAPI */
++void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line);
++#ifdef CONFIG_USB_HCI
++void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, const int line);
++void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, const int line);
++#endif /* CONFIG_USB_HCI */
++
++#ifdef CONFIG_USE_VMALLOC
++#define rtw_vmalloc(sz)			dbg_rtw_vmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
++#define rtw_zvmalloc(sz)			dbg_rtw_zvmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
++#define rtw_vmfree(pbuf, sz)		dbg_rtw_vmfree((pbuf), (sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
++#define rtw_vmalloc_f(sz, mstat_f)			dbg_rtw_vmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
++#define rtw_zvmalloc_f(sz, mstat_f)		dbg_rtw_zvmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
++#define rtw_vmfree_f(pbuf, sz, mstat_f)	dbg_rtw_vmfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
++#else /* CONFIG_USE_VMALLOC */
++#define rtw_vmalloc(sz)			dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_zvmalloc(sz)			dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_vmfree(pbuf, sz)		dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_vmalloc_f(sz, mstat_f)			dbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_zvmalloc_f(sz, mstat_f)		dbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_vmfree_f(pbuf, sz, mstat_f)	dbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#endif /* CONFIG_USE_VMALLOC */
++#define rtw_malloc(sz)			dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_zmalloc(sz)			dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_mfree(pbuf, sz)		dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_malloc_f(sz, mstat_f)			dbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_zmalloc_f(sz, mstat_f)			dbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++#define rtw_mfree_f(pbuf, sz, mstat_f)		dbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
++
++#define rtw_skb_alloc(size)	dbg_rtw_skb_alloc((size), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#define rtw_skb_free(skb)	dbg_rtw_skb_free((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#define rtw_skb_alloc_f(size, mstat_f)	dbg_rtw_skb_alloc((size), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#define rtw_skb_free_f(skb, mstat_f)	dbg_rtw_skb_free((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#define rtw_skb_copy(skb)	dbg_rtw_skb_copy((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#define rtw_skb_clone(skb)	dbg_rtw_skb_clone((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#define rtw_skb_copy_f(skb, mstat_f)	dbg_rtw_skb_copy((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#define rtw_skb_clone_f(skb, mstat_f)	dbg_rtw_skb_clone((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#define rtw_netif_rx(ndev, skb)	dbg_rtw_netif_rx(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#ifdef CONFIG_RTW_NAPI
++#define rtw_netif_receive_skb(ndev, skb) dbg_rtw_netif_receive_skb(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#ifdef CONFIG_RTW_GRO
++#define rtw_napi_gro_receive(napi, skb) dbg_rtw_napi_gro_receive(napi, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#endif
++#endif /* CONFIG_RTW_NAPI */
++#define rtw_skb_queue_purge(sk_buff_head) dbg_rtw_skb_queue_purge(sk_buff_head, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#ifdef CONFIG_USB_HCI
++#define rtw_usb_buffer_alloc(dev, size, dma)		dbg_rtw_usb_buffer_alloc((dev), (size), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
++#define rtw_usb_buffer_free(dev, size, addr, dma)	dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
++#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f)			dbg_rtw_usb_buffer_alloc((dev), (size), (dma), ((mstat_f) & 0xff00) | MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
++#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f)	dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), ((mstat_f) & 0xff00) | MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
++#endif /* CONFIG_USB_HCI */
++
++#else /* DBG_MEM_ALLOC */
++#define rtw_mstat_update(flag, status, sz) do {} while (0)
++#define rtw_mstat_dump(sel) do {} while (0)
++#define match_mstat_sniff_rules(flags, size) _FALSE
++void *_rtw_vmalloc(u32 sz);
++void *_rtw_zvmalloc(u32 sz);
++void _rtw_vmfree(void *pbuf, u32 sz);
++void *_rtw_zmalloc(u32 sz);
++void *_rtw_malloc(u32 sz);
++void _rtw_mfree(void *pbuf, u32 sz);
++
++struct sk_buff *_rtw_skb_alloc(u32 sz);
++void _rtw_skb_free(struct sk_buff *skb);
++struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb);
++struct sk_buff *_rtw_skb_clone(struct sk_buff *skb);
++int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb);
++#ifdef CONFIG_RTW_NAPI
++int _rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb);
++#ifdef CONFIG_RTW_GRO
++gro_result_t _rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb);
++#endif
++#endif /* CONFIG_RTW_NAPI */
++void _rtw_skb_queue_purge(struct sk_buff_head *list);
++
++#ifdef CONFIG_USB_HCI
++void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma);
++void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma);
++#endif /* CONFIG_USB_HCI */
++
++#ifdef CONFIG_USE_VMALLOC
++#define rtw_vmalloc(sz)			_rtw_vmalloc((sz))
++#define rtw_zvmalloc(sz)			_rtw_zvmalloc((sz))
++#define rtw_vmfree(pbuf, sz)		_rtw_vmfree((pbuf), (sz))
++#define rtw_vmalloc_f(sz, mstat_f)			_rtw_vmalloc((sz))
++#define rtw_zvmalloc_f(sz, mstat_f)		_rtw_zvmalloc((sz))
++#define rtw_vmfree_f(pbuf, sz, mstat_f)	_rtw_vmfree((pbuf), (sz))
++#else /* CONFIG_USE_VMALLOC */
++#define rtw_vmalloc(sz)			_rtw_malloc((sz))
++#define rtw_zvmalloc(sz)			_rtw_zmalloc((sz))
++#define rtw_vmfree(pbuf, sz)		_rtw_mfree((pbuf), (sz))
++#define rtw_vmalloc_f(sz, mstat_f)			_rtw_malloc((sz))
++#define rtw_zvmalloc_f(sz, mstat_f)		_rtw_zmalloc((sz))
++#define rtw_vmfree_f(pbuf, sz, mstat_f)	_rtw_mfree((pbuf), (sz))
++#endif /* CONFIG_USE_VMALLOC */
++#define rtw_malloc(sz)			_rtw_malloc((sz))
++#define rtw_zmalloc(sz)			_rtw_zmalloc((sz))
++#define rtw_mfree(pbuf, sz)		_rtw_mfree((pbuf), (sz))
++#define rtw_malloc_f(sz, mstat_f)			_rtw_malloc((sz))
++#define rtw_zmalloc_f(sz, mstat_f)			_rtw_zmalloc((sz))
++#define rtw_mfree_f(pbuf, sz, mstat_f)		_rtw_mfree((pbuf), (sz))
++
++#define rtw_skb_alloc(size) _rtw_skb_alloc((size))
++#define rtw_skb_free(skb) _rtw_skb_free((skb))
++#define rtw_skb_alloc_f(size, mstat_f)	_rtw_skb_alloc((size))
++#define rtw_skb_free_f(skb, mstat_f)	_rtw_skb_free((skb))
++#define rtw_skb_copy(skb)	_rtw_skb_copy((skb))
++#define rtw_skb_clone(skb)	_rtw_skb_clone((skb))
++#define rtw_skb_copy_f(skb, mstat_f)	_rtw_skb_copy((skb))
++#define rtw_skb_clone_f(skb, mstat_f)	_rtw_skb_clone((skb))
++#define rtw_netif_rx(ndev, skb) _rtw_netif_rx(ndev, skb)
++#ifdef CONFIG_RTW_NAPI
++#define rtw_netif_receive_skb(ndev, skb) _rtw_netif_receive_skb(ndev, skb)
++#ifdef CONFIG_RTW_GRO
++#define rtw_napi_gro_receive(napi, skb) _rtw_napi_gro_receive(napi, skb)
++#endif
++#endif /* CONFIG_RTW_NAPI */
++#define rtw_skb_queue_purge(sk_buff_head) _rtw_skb_queue_purge(sk_buff_head)
++#ifdef CONFIG_USB_HCI
++#define rtw_usb_buffer_alloc(dev, size, dma) _rtw_usb_buffer_alloc((dev), (size), (dma))
++#define rtw_usb_buffer_free(dev, size, addr, dma) _rtw_usb_buffer_free((dev), (size), (addr), (dma))
++#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) _rtw_usb_buffer_alloc((dev), (size), (dma))
++#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) _rtw_usb_buffer_free((dev), (size), (addr), (dma))
++#endif /* CONFIG_USB_HCI */
++#endif /* DBG_MEM_ALLOC */
++
++extern void	*rtw_malloc2d(int h, int w, size_t size);
++extern void	rtw_mfree2d(void *pbuf, int h, int w, int size);
++
++void rtw_os_pkt_free(_pkt *pkt);
++_pkt *rtw_os_pkt_copy(_pkt *pkt);
++void *rtw_os_pkt_data(_pkt *pkt);
++u32 rtw_os_pkt_len(_pkt *pkt);
++
++extern void	_rtw_memcpy(void *dec, const void *sour, u32 sz);
++extern void _rtw_memmove(void *dst, const void *src, u32 sz);
++extern int	_rtw_memcmp(const void *dst, const void *src, u32 sz);
++extern int _rtw_memcmp2(const void *dst, const void *src, u32 sz);
++extern void	_rtw_memset(void *pbuf, int c, u32 sz);
++
++extern void	_rtw_init_listhead(_list *list);
++extern u32	rtw_is_list_empty(_list *phead);
++extern void	rtw_list_insert_head(_list *plist, _list *phead);
++extern void	rtw_list_insert_tail(_list *plist, _list *phead);
++void rtw_list_splice(_list *list, _list *head);
++void rtw_list_splice_init(_list *list, _list *head);
++void rtw_list_splice_tail(_list *list, _list *head);
++
++#ifndef PLATFORM_FREEBSD
++extern void	rtw_list_delete(_list *plist);
++#endif /* PLATFORM_FREEBSD */
++
++void rtw_hlist_head_init(rtw_hlist_head *h);
++void rtw_hlist_add_head(rtw_hlist_node *n, rtw_hlist_head *h);
++void rtw_hlist_del(rtw_hlist_node *n);
++void rtw_hlist_add_head_rcu(rtw_hlist_node *n, rtw_hlist_head *h);
++void rtw_hlist_del_rcu(rtw_hlist_node *n);
++
++extern void	_rtw_init_sema(_sema *sema, int init_val);
++extern void	_rtw_free_sema(_sema	*sema);
++extern void	_rtw_up_sema(_sema	*sema);
++extern u32	_rtw_down_sema(_sema *sema);
++extern void	_rtw_mutex_init(_mutex *pmutex);
++extern void	_rtw_mutex_free(_mutex *pmutex);
++#ifndef PLATFORM_FREEBSD
++extern void	_rtw_spinlock_init(_lock *plock);
++#endif /* PLATFORM_FREEBSD */
++extern void	_rtw_spinlock_free(_lock *plock);
++extern void	_rtw_spinlock(_lock	*plock);
++extern void	_rtw_spinunlock(_lock	*plock);
++extern void	_rtw_spinlock_ex(_lock	*plock);
++extern void	_rtw_spinunlock_ex(_lock	*plock);
++
++extern void	_rtw_init_queue(_queue *pqueue);
++extern void _rtw_deinit_queue(_queue *pqueue);
++extern u32	_rtw_queue_empty(_queue	*pqueue);
++extern u32	rtw_end_of_queue_search(_list *queue, _list *pelement);
++
++extern systime _rtw_get_current_time(void);
++extern u32	_rtw_systime_to_ms(systime stime);
++extern systime _rtw_ms_to_systime(u32 ms);
++extern systime _rtw_us_to_systime(u32 us);
++extern s32	_rtw_get_passing_time_ms(systime start);
++extern s32 _rtw_get_remaining_time_ms(systime end);
++extern s32	_rtw_get_time_interval_ms(systime start, systime end);
++extern bool _rtw_time_after(systime a, systime b);
++
++#ifdef DBG_SYSTIME
++#define rtw_get_current_time() ({systime __stime = _rtw_get_current_time(); __stime;})
++#define rtw_systime_to_ms(stime) ({u32 __ms = _rtw_systime_to_ms(stime); typecheck(systime, stime); __ms;})
++#define rtw_ms_to_systime(ms) ({systime __stime = _rtw_ms_to_systime(ms); __stime;})
++#define rtw_us_to_systime(us) ({systime __stime = _rtw_us_to_systime(us); __stime;})
++#define rtw_get_passing_time_ms(start) ({u32 __ms = _rtw_get_passing_time_ms(start); typecheck(systime, start); __ms;})
++#define rtw_get_remaining_time_ms(end) ({u32 __ms = _rtw_get_remaining_time_ms(end); typecheck(systime, end); __ms;})
++#define rtw_get_time_interval_ms(start, end) ({u32 __ms = _rtw_get_time_interval_ms(start, end); typecheck(systime, start); typecheck(systime, end); __ms;})
++#define rtw_time_after(a,b) ({bool __r = _rtw_time_after(a,b); typecheck(systime, a); typecheck(systime, b); __r;})
++#define rtw_time_before(a,b) ({bool __r = _rtw_time_after(b, a); typecheck(systime, a); typecheck(systime, b); __r;})
++#else
++#define rtw_get_current_time() _rtw_get_current_time()
++#define rtw_systime_to_ms(stime) _rtw_systime_to_ms(stime)
++#define rtw_ms_to_systime(ms) _rtw_ms_to_systime(ms)
++#define rtw_us_to_systime(us) _rtw_us_to_systime(us)
++#define rtw_get_passing_time_ms(start) _rtw_get_passing_time_ms(start)
++#define rtw_get_remaining_time_ms(end) _rtw_get_remaining_time_ms(end)
++#define rtw_get_time_interval_ms(start, end) _rtw_get_time_interval_ms(start, end)
++#define rtw_time_after(a,b) _rtw_time_after(a,b)
++#define rtw_time_before(a,b) _rtw_time_after(b,a)
++#endif
++
++extern void	rtw_sleep_schedulable(int ms);
++
++extern void	rtw_msleep_os(int ms);
++extern void	rtw_usleep_os(int us);
++
++extern u32	rtw_atoi(u8 *s);
++
++#ifdef DBG_DELAY_OS
++#define rtw_mdelay_os(ms) _rtw_mdelay_os((ms), __FUNCTION__, __LINE__)
++#define rtw_udelay_os(ms) _rtw_udelay_os((ms), __FUNCTION__, __LINE__)
++extern void _rtw_mdelay_os(int ms, const char *func, const int line);
++extern void _rtw_udelay_os(int us, const char *func, const int line);
++#else
++extern void	rtw_mdelay_os(int ms);
++extern void	rtw_udelay_os(int us);
++#endif
++
++extern void rtw_yield_os(void);
++
++
++extern void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx);
++
++
++__inline static unsigned char _cancel_timer_ex(_timer *ptimer)
++{
++	u8 bcancelled;
++
++	_cancel_timer(ptimer, &bcancelled);
++
++	return bcancelled;
++}
++
++static __inline void thread_enter(char *name)
++{
++#ifdef PLATFORM_LINUX
++	allow_signal(SIGTERM);
++#endif
++#ifdef PLATFORM_FREEBSD
++	printf("%s", "RTKTHREAD_enter");
++#endif
++}
++void thread_exit(_completion *comp);
++void _rtw_init_completion(_completion *comp);
++void _rtw_wait_for_comp_timeout(_completion *comp);
++void _rtw_wait_for_comp(_completion *comp);
++
++static inline bool rtw_thread_stop(_thread_hdl_ th)
++{
++#ifdef PLATFORM_LINUX
++	return kthread_stop(th);
++#endif
++}
++static inline void rtw_thread_wait_stop(void)
++{
++#ifdef PLATFORM_LINUX
++	#if 0
++	while (!kthread_should_stop())
++		rtw_msleep_os(10);
++	#else
++	set_current_state(TASK_INTERRUPTIBLE);
++	while (!kthread_should_stop()) {
++		schedule();
++		set_current_state(TASK_INTERRUPTIBLE);
++	}
++	__set_current_state(TASK_RUNNING);
++	#endif
++#endif
++}
++
++__inline static void flush_signals_thread(void)
++{
++#ifdef PLATFORM_LINUX
++	if (signal_pending(current))
++		flush_signals(current);
++#endif
++}
++
++__inline static _OS_STATUS res_to_status(sint res)
++{
++
++#if defined(PLATFORM_LINUX) || defined (PLATFORM_MPIXEL) || defined (PLATFORM_FREEBSD)
++	return res;
++#endif
++
++#ifdef PLATFORM_WINDOWS
++
++	if (res == _SUCCESS)
++		return NDIS_STATUS_SUCCESS;
++	else
++		return NDIS_STATUS_FAILURE;
++
++#endif
++
++}
++
++__inline static void rtw_dump_stack(void)
++{
++#ifdef PLATFORM_LINUX
++	dump_stack();
++#endif
++}
++
++#ifdef PLATFORM_LINUX
++#define rtw_warn_on(condition) WARN_ON(condition)
++#else
++#define rtw_warn_on(condition) do {} while (0)
++#endif
++
++__inline static int rtw_bug_check(void *parg1, void *parg2, void *parg3, void *parg4)
++{
++	int ret = _TRUE;
++
++#ifdef PLATFORM_WINDOWS
++	if (((uint)parg1) <= 0x7fffffff ||
++	    ((uint)parg2) <= 0x7fffffff ||
++	    ((uint)parg3) <= 0x7fffffff ||
++	    ((uint)parg4) <= 0x7fffffff) {
++		ret = _FALSE;
++		KeBugCheckEx(0x87110000, (ULONG_PTR)parg1, (ULONG_PTR)parg2, (ULONG_PTR)parg3, (ULONG_PTR)parg4);
++	}
++#endif
++
++	return ret;
++
++}
++#ifdef PLATFORM_LINUX
++#define RTW_DIV_ROUND_UP(n, d)	DIV_ROUND_UP(n, d)
++#else /* !PLATFORM_LINUX */
++#define RTW_DIV_ROUND_UP(n, d)	(((n) + (d - 1)) / d)
++#endif /* !PLATFORM_LINUX */
++
++#define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r))
++#define RND4(x)	(((x >> 2) + (((x & 3) == 0) ? 0 : 1)) << 2)
++
++__inline static u32 _RND4(u32 sz)
++{
++
++	u32	val;
++
++	val = ((sz >> 2) + ((sz & 3) ? 1 : 0)) << 2;
++
++	return val;
++
++}
++
++__inline static u32 _RND8(u32 sz)
++{
++
++	u32	val;
++
++	val = ((sz >> 3) + ((sz & 7) ? 1 : 0)) << 3;
++
++	return val;
++
++}
++
++__inline static u32 _RND128(u32 sz)
++{
++
++	u32	val;
++
++	val = ((sz >> 7) + ((sz & 127) ? 1 : 0)) << 7;
++
++	return val;
++
++}
++
++__inline static u32 _RND256(u32 sz)
++{
++
++	u32	val;
++
++	val = ((sz >> 8) + ((sz & 255) ? 1 : 0)) << 8;
++
++	return val;
++
++}
++
++__inline static u32 _RND512(u32 sz)
++{
++
++	u32	val;
++
++	val = ((sz >> 9) + ((sz & 511) ? 1 : 0)) << 9;
++
++	return val;
++
++}
++
++__inline static u32 bitshift(u32 bitmask)
++{
++	u32 i;
++
++	for (i = 0; i <= 31; i++)
++		if (((bitmask >> i) &  0x1) == 1)
++			break;
++
++	return i;
++}
++
++static inline int largest_bit(u32 bitmask)
++{
++	int i;
++
++	for (i = 31; i >= 0; i--)
++		if (bitmask & BIT(i))
++			break;
++
++	return i;
++}
++
++static inline int largest_bit_64(u64 bitmask)
++{
++	int i;
++
++	for (i = 63; i >= 0; i--)
++		if (bitmask & BIT_ULL(i))
++			break;
++
++	return i;
++}
++
++#define rtw_abs(a) (a < 0 ? -a : a)
++#define rtw_min(a, b) ((a > b) ? b : a)
++#define rtw_max(a, b) ((a > b) ? a : b)
++#define rtw_is_range_a_in_b(hi_a, lo_a, hi_b, lo_b) (((hi_a) <= (hi_b)) && ((lo_a) >= (lo_b)))
++#define rtw_is_range_overlap(hi_a, lo_a, hi_b, lo_b) (((hi_a) > (lo_b)) && ((lo_a) < (hi_b)))
++
++#ifndef MAC_FMT
++#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
++#endif
++#ifndef MAC_ARG
++#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5]
++#endif
++
++bool rtw_macaddr_is_larger(const u8 *a, const u8 *b);
++
++extern void rtw_suspend_lock_init(void);
++extern void rtw_suspend_lock_uninit(void);
++extern void rtw_lock_suspend(void);
++extern void rtw_unlock_suspend(void);
++extern void rtw_lock_suspend_timeout(u32 timeout_ms);
++extern void rtw_lock_traffic_suspend_timeout(u32 timeout_ms);
++extern void rtw_resume_lock_suspend(void);
++extern void rtw_resume_unlock_suspend(void);
++#ifdef CONFIG_AP_WOWLAN
++extern void rtw_softap_lock_suspend(void);
++extern void rtw_softap_unlock_suspend(void);
++#endif
++
++extern void rtw_set_bit(int nr, unsigned long *addr);
++extern void rtw_clear_bit(int nr, unsigned long *addr);
++extern int rtw_test_and_clear_bit(int nr, unsigned long *addr);
++
++extern void ATOMIC_SET(ATOMIC_T *v, int i);
++extern int ATOMIC_READ(ATOMIC_T *v);
++extern void ATOMIC_ADD(ATOMIC_T *v, int i);
++extern void ATOMIC_SUB(ATOMIC_T *v, int i);
++extern void ATOMIC_INC(ATOMIC_T *v);
++extern void ATOMIC_DEC(ATOMIC_T *v);
++extern int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i);
++extern int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i);
++extern int ATOMIC_INC_RETURN(ATOMIC_T *v);
++extern int ATOMIC_DEC_RETURN(ATOMIC_T *v);
++extern bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u);
++
++/* File operation APIs, just for linux now */
++extern int rtw_is_dir_readable(const char *path);
++extern int rtw_is_file_readable(const char *path);
++extern int rtw_is_file_readable_with_size(const char *path, u32 *sz);
++extern int rtw_readable_file_sz_chk(const char *path, u32 sz);
++extern int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz);
++extern int rtw_store_to_file(const char *path, u8 *buf, u32 sz);
++
++
++#ifndef PLATFORM_FREEBSD
++extern void rtw_free_netdev(struct net_device *netdev);
++#endif /* PLATFORM_FREEBSD */
++
++
++extern u64 rtw_modular64(u64 x, u64 y);
++extern u64 rtw_division64(u64 x, u64 y);
++extern u32 rtw_random32(void);
++
++/* Macros for handling unaligned memory accesses */
++
++#define RTW_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1]))
++#define RTW_PUT_BE16(a, val)			\
++	do {					\
++		(a)[0] = ((u16) (val)) >> 8;	\
++		(a)[1] = ((u16) (val)) & 0xff;	\
++	} while (0)
++
++#define RTW_GET_LE16(a) ((u16) (((a)[1] << 8) | (a)[0]))
++#define RTW_PUT_LE16(a, val)			\
++	do {					\
++		(a)[1] = ((u16) (val)) >> 8;	\
++		(a)[0] = ((u16) (val)) & 0xff;	\
++	} while (0)
++
++#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \
++			 ((u32) (a)[2]))
++#define RTW_PUT_BE24(a, val)					\
++	do {							\
++		(a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
++		(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
++		(a)[2] = (u8) (((u32) (val)) & 0xff);		\
++	} while (0)
++
++#define RTW_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \
++			 (((u32) (a)[2]) << 8) | ((u32) (a)[3]))
++#define RTW_PUT_BE32(a, val)					\
++	do {							\
++		(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
++		(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
++		(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
++		(a)[3] = (u8) (((u32) (val)) & 0xff);		\
++	} while (0)
++
++#define RTW_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \
++			 (((u32) (a)[1]) << 8) | ((u32) (a)[0]))
++#define RTW_PUT_LE32(a, val)					\
++	do {							\
++		(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
++		(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
++		(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
++		(a)[0] = (u8) (((u32) (val)) & 0xff);		\
++	} while (0)
++
++#define RTW_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \
++			 (((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \
++			 (((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \
++			 (((u64) (a)[6]) << 8) | ((u64) (a)[7]))
++#define RTW_PUT_BE64(a, val)				\
++	do {						\
++		(a)[0] = (u8) (((u64) (val)) >> 56);	\
++		(a)[1] = (u8) (((u64) (val)) >> 48);	\
++		(a)[2] = (u8) (((u64) (val)) >> 40);	\
++		(a)[3] = (u8) (((u64) (val)) >> 32);	\
++		(a)[4] = (u8) (((u64) (val)) >> 24);	\
++		(a)[5] = (u8) (((u64) (val)) >> 16);	\
++		(a)[6] = (u8) (((u64) (val)) >> 8);	\
++		(a)[7] = (u8) (((u64) (val)) & 0xff);	\
++	} while (0)
++
++#define RTW_GET_LE64(a) ((((u64) (a)[7]) << 56) | (((u64) (a)[6]) << 48) | \
++			 (((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \
++			 (((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \
++			 (((u64) (a)[1]) << 8) | ((u64) (a)[0]))
++#define RTW_PUT_LE64(a, val)					\
++	do {							\
++		(a)[7] = (u8) ((((u64) (val)) >> 56) & 0xff);	\
++		(a)[6] = (u8) ((((u64) (val)) >> 48) & 0xff);	\
++		(a)[5] = (u8) ((((u64) (val)) >> 40) & 0xff);	\
++		(a)[4] = (u8) ((((u64) (val)) >> 32) & 0xff);	\
++		(a)[3] = (u8) ((((u64) (val)) >> 24) & 0xff);	\
++		(a)[2] = (u8) ((((u64) (val)) >> 16) & 0xff);	\
++		(a)[1] = (u8) ((((u64) (val)) >> 8) & 0xff);	\
++		(a)[0] = (u8) (((u64) (val)) & 0xff);		\
++	} while (0)
++
++void rtw_buf_free(u8 **buf, u32 *buf_len);
++void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len);
++
++struct rtw_cbuf {
++	u32 write;
++	u32 read;
++	u32 size;
++	void *bufs[0];
++};
++
++bool rtw_cbuf_full(struct rtw_cbuf *cbuf);
++bool rtw_cbuf_empty(struct rtw_cbuf *cbuf);
++bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf);
++void *rtw_cbuf_pop(struct rtw_cbuf *cbuf);
++struct rtw_cbuf *rtw_cbuf_alloc(u32 size);
++void rtw_cbuf_free(struct rtw_cbuf *cbuf);
++
++struct map_seg_t {
++	u16 sa;
++	u16 len;
++	u8 *c;
++};
++
++struct map_t {
++	u16 len;
++	u16 seg_num;
++	u8 init_value;
++	struct map_seg_t *segs;
++};
++
++#define MAPSEG_ARRAY_ENT(_sa, _len, _c, arg...) \
++	{ .sa = _sa, .len = _len, .c = (u8[_len]){ _c, ##arg}, }
++
++#define MAPSEG_PTR_ENT(_sa, _len, _p) \
++	{ .sa = _sa, .len = _len, .c = _p, }
++
++#define MAP_ENT(_len, _seg_num, _init_v, _seg, arg...) \
++	{ .len = _len, .seg_num = _seg_num, .init_value = _init_v, .segs = (struct map_seg_t[_seg_num]){ _seg, ##arg}, }
++
++int map_readN(const struct map_t *map, u16 offset, u16 len, u8 *buf);
++u8 map_read8(const struct map_t *map, u16 offset);
++
++struct blacklist_ent {
++	_list list;
++	u8 addr[ETH_ALEN];
++	systime exp_time;
++};
++
++int rtw_blacklist_add(_queue *blist, const u8 *addr, u32 timeout_ms);
++int rtw_blacklist_del(_queue *blist, const u8 *addr);
++int rtw_blacklist_search(_queue *blist, const u8 *addr);
++void rtw_blacklist_flush(_queue *blist);
++void dump_blacklist(void *sel, _queue *blist, const char *title);
++
++/* String handler */
++
++BOOLEAN is_null(char c);
++BOOLEAN is_all_null(char *c, int len);
++BOOLEAN is_eol(char c);
++BOOLEAN is_space(char c);
++BOOLEAN IsHexDigit(char chTmp);
++BOOLEAN is_alpha(char chTmp);
++char alpha_to_upper(char c);
++
++int hex2num_i(char c);
++int hex2byte_i(const char *hex);
++int hexstr2bin(const char *hex, u8 *buf, size_t len);
++
++/*
++ * Write formatted output to sized buffer
++ */
++#ifdef PLATFORM_LINUX
++#define rtw_sprintf(buf, size, format, arg...)	snprintf(buf, size, format, ##arg)
++#else /* !PLATFORM_LINUX */
++#error "NOT DEFINE \"rtw_sprintf\"!!"
++#endif /* !PLATFORM_LINUX */
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_service_bsd.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_service_bsd.h
+new file mode 100644
+index 000000000..f8f15d6fd
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_service_bsd.h
+@@ -0,0 +1,757 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __OSDEP_BSD_SERVICE_H_
++#define __OSDEP_BSD_SERVICE_H_
++
++
++#include <sys/cdefs.h>
++#include <sys/types.h>
++#include <sys/systm.h>
++#include <sys/param.h>
++#include <sys/sockio.h>
++#include <sys/sysctl.h>
++#include <sys/lock.h>
++#include <sys/mutex.h>
++#include <sys/mbuf.h>
++#include <sys/kernel.h>
++#include <sys/socket.h>
++#include <sys/systm.h>
++#include <sys/malloc.h>
++#include <sys/module.h>
++#include <sys/bus.h>
++#include <sys/endian.h>
++#include <sys/kdb.h>
++#include <sys/kthread.h>
++#include <sys/malloc.h>
++#include <sys/time.h>
++#include <machine/atomic.h>
++#include <machine/bus.h>
++#include <machine/resource.h>
++#include <sys/rman.h>
++
++#include <net/bpf.h>
++#include <net/if.h>
++#include <net/if_arp.h>
++#include <net/ethernet.h>
++#include <net/if_dl.h>
++#include <net/if_media.h>
++#include <net/if_types.h>
++#include <net/route.h>
++
++
++#include <netinet/in.h>
++#include <netinet/in_systm.h>
++#include <netinet/in_var.h>
++#include <netinet/if_ether.h>
++#include <if_ether.h>
++
++#include <net80211/ieee80211_var.h>
++#include <net80211/ieee80211_regdomain.h>
++#include <net80211/ieee80211_radiotap.h>
++#include <net80211/ieee80211_ratectl.h>
++
++#include <dev/usb/usb.h>
++#include <dev/usb/usbdi.h>
++#include "usbdevs.h"
++
++#define	USB_DEBUG_VAR rum_debug
++#include <dev/usb/usb_debug.h>
++
++#if 1 //Baron porting from linux, it's all temp solution, needs to check again
++#include <sys/sema.h>
++#include <sys/pcpu.h> /* XXX for PCPU_GET */
++//	typedef struct 	semaphore _sema;
++	typedef struct 	sema _sema;
++//	typedef	spinlock_t	_lock;
++	typedef	struct mtx	_lock;
++	typedef struct mtx 		_mutex;
++	typedef struct rtw_timer_list _timer;
++	struct list_head {
++	struct list_head *next, *prev;
++	};
++	struct	__queue	{
++		struct	list_head	queue;	
++		_lock	lock;
++	};
++
++	typedef	struct mbuf _pkt;
++	typedef struct mbuf	_buffer;
++	
++	typedef struct	__queue	_queue;
++	typedef struct	list_head	_list;
++	typedef	int	_OS_STATUS;
++	//typedef u32	_irqL;
++	typedef unsigned long _irqL;
++	typedef	struct	ifnet * _nic_hdl;
++	
++	typedef pid_t		_thread_hdl_;
++//	typedef struct thread		_thread_hdl_;
++	typedef void		thread_return;
++	typedef void*	thread_context;
++
++	typedef void timer_hdl_return;
++	typedef void* timer_hdl_context;
++	typedef struct work_struct _workitem;
++	typedef struct task _tasklet;
++
++#define   KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
++/* emulate a modern version */
++#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 35)
++
++#define WIRELESS_EXT -1
++#define HZ hz
++#define spin_lock_irqsave mtx_lock_irqsave
++#define spin_lock_bh mtx_lock_irqsave
++#define mtx_lock_irqsave(lock, x) mtx_lock(lock)//{local_irq_save((x)); mtx_lock_spin((lock));}
++//#define IFT_RTW	0xf9 //ifnet allocate type for RTW
++#define free_netdev if_free
++#define LIST_CONTAINOR(ptr, type, member) \
++        ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
++#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n))
++/* 
++ * Linux timers are emulated using FreeBSD callout functions
++ * (and taskqueue functionality).
++ *
++ * Currently no timer stats functionality.
++ *
++ * See (linux_compat) processes.c
++ *
++ */
++struct rtw_timer_list {
++	struct callout callout;
++	void (*function)(void *);
++	void *arg;
++};
++
++struct workqueue_struct;
++struct work_struct;
++typedef void (*work_func_t)(struct work_struct *work);
++/* Values for the state of an item of work (work_struct) */
++typedef enum work_state {
++        WORK_STATE_UNSET = 0,
++        WORK_STATE_CALLOUT_PENDING = 1,
++        WORK_STATE_TASK_PENDING = 2,
++        WORK_STATE_WORK_CANCELLED = 3        
++} work_state_t;
++
++struct work_struct {
++        struct task task; /* FreeBSD task */
++        work_state_t state; /* the pending or otherwise state of work. */
++        work_func_t func;       
++};
++#define spin_unlock_irqrestore mtx_unlock_irqrestore
++#define spin_unlock_bh mtx_unlock_irqrestore
++#define mtx_unlock_irqrestore(lock,x)    mtx_unlock(lock);
++extern void	_rtw_spinlock_init(_lock *plock);
++
++//modify private structure to match freebsd
++#define BITS_PER_LONG 32
++union ktime {
++	s64	tv64;
++#if BITS_PER_LONG != 64 && !defined(CONFIG_KTIME_SCALAR)
++	struct {
++#ifdef __BIG_ENDIAN
++	s32	sec, nsec;
++#else
++	s32	nsec, sec;
++#endif
++	} tv;
++#endif
++};
++#define kmemcheck_bitfield_begin(name)
++#define kmemcheck_bitfield_end(name)
++#define CHECKSUM_NONE 0
++typedef unsigned char *sk_buff_data_t;
++typedef union ktime ktime_t;		/* Kill this */
++
++void rtw_mtx_lock(_lock *plock);
++	
++void rtw_mtx_unlock(_lock *plock);
++
++/** 
++ *	struct sk_buff - socket buffer
++ *	@next: Next buffer in list
++ *	@prev: Previous buffer in list
++ *	@sk: Socket we are owned by
++ *	@tstamp: Time we arrived
++ *	@dev: Device we arrived on/are leaving by
++ *	@transport_header: Transport layer header
++ *	@network_header: Network layer header
++ *	@mac_header: Link layer header
++ *	@_skb_refdst: destination entry (with norefcount bit)
++ *	@sp: the security path, used for xfrm
++ *	@cb: Control buffer. Free for use by every layer. Put private vars here
++ *	@len: Length of actual data
++ *	@data_len: Data length
++ *	@mac_len: Length of link layer header
++ *	@hdr_len: writable header length of cloned skb
++ *	@csum: Checksum (must include start/offset pair)
++ *	@csum_start: Offset from skb->head where checksumming should start
++ *	@csum_offset: Offset from csum_start where checksum should be stored
++ *	@local_df: allow local fragmentation
++ *	@cloned: Head may be cloned (check refcnt to be sure)
++ *	@nohdr: Payload reference only, must not modify header
++ *	@pkt_type: Packet class
++ *	@fclone: skbuff clone status
++ *	@ip_summed: Driver fed us an IP checksum
++ *	@priority: Packet queueing priority
++ *	@users: User count - see {datagram,tcp}.c
++ *	@protocol: Packet protocol from driver
++ *	@truesize: Buffer size 
++ *	@head: Head of buffer
++ *	@data: Data head pointer
++ *	@tail: Tail pointer
++ *	@end: End pointer
++ *	@destructor: Destruct function
++ *	@mark: Generic packet mark
++ *	@nfct: Associated connection, if any
++ *	@ipvs_property: skbuff is owned by ipvs
++ *	@peeked: this packet has been seen already, so stats have been
++ *		done for it, don't do them again
++ *	@nf_trace: netfilter packet trace flag
++ *	@nfctinfo: Relationship of this skb to the connection
++ *	@nfct_reasm: netfilter conntrack re-assembly pointer
++ *	@nf_bridge: Saved data about a bridged frame - see br_netfilter.c
++ *	@skb_iif: ifindex of device we arrived on
++ *	@rxhash: the packet hash computed on receive
++ *	@queue_mapping: Queue mapping for multiqueue devices
++ *	@tc_index: Traffic control index
++ *	@tc_verd: traffic control verdict
++ *	@ndisc_nodetype: router type (from link layer)
++ *	@dma_cookie: a cookie to one of several possible DMA operations
++ *		done by skb DMA functions
++ *	@secmark: security marking
++ *	@vlan_tci: vlan tag control information
++ */
++
++struct sk_buff {
++	/* These two members must be first. */
++	struct sk_buff		*next;
++	struct sk_buff		*prev;
++
++	ktime_t			tstamp;
++
++	struct sock		*sk;
++	//struct net_device	*dev;
++	struct ifnet *dev;
++
++	/*
++	 * This is the control buffer. It is free to use for every
++	 * layer. Please put your private variables there. If you
++	 * want to keep them across layers you have to do a skb_clone()
++	 * first. This is owned by whoever has the skb queued ATM.
++	 */
++	char			cb[48] __aligned(8);
++
++	unsigned long		_skb_refdst;
++#ifdef CONFIG_XFRM
++	struct	sec_path	*sp;
++#endif
++	unsigned int		len,
++				data_len;
++	u16			mac_len,
++				hdr_len;
++	union {
++		u32		csum;
++		struct {
++			u16	csum_start;
++			u16	csum_offset;
++		}smbol2;
++	}smbol1;
++	u32			priority;
++	kmemcheck_bitfield_begin(flags1);
++	u8			local_df:1,
++				cloned:1,
++				ip_summed:2,
++				nohdr:1,
++				nfctinfo:3;
++	u8			pkt_type:3,
++				fclone:2,
++				ipvs_property:1,
++				peeked:1,
++				nf_trace:1;
++	kmemcheck_bitfield_end(flags1);
++	u16			protocol;
++
++	void			(*destructor)(struct sk_buff *skb);
++#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE)
++	struct nf_conntrack	*nfct;
++	struct sk_buff		*nfct_reasm;
++#endif
++#ifdef CONFIG_BRIDGE_NETFILTER
++	struct nf_bridge_info	*nf_bridge;
++#endif
++
++	int			skb_iif;
++#ifdef CONFIG_NET_SCHED
++	u16			tc_index;	/* traffic control index */
++#ifdef CONFIG_NET_CLS_ACT
++	u16			tc_verd;	/* traffic control verdict */
++#endif
++#endif
++
++	u32			rxhash;
++
++	kmemcheck_bitfield_begin(flags2);
++	u16			queue_mapping:16;
++#ifdef CONFIG_IPV6_NDISC_NODETYPE
++	u8			ndisc_nodetype:2,
++				deliver_no_wcard:1;
++#else
++	u8			deliver_no_wcard:1;
++#endif
++	kmemcheck_bitfield_end(flags2);
++
++	/* 0/14 bit hole */
++
++#ifdef CONFIG_NET_DMA
++	dma_cookie_t		dma_cookie;
++#endif
++#ifdef CONFIG_NETWORK_SECMARK
++	u32			secmark;
++#endif
++	union {
++		u32		mark;
++		u32		dropcount;
++	}symbol3;
++
++	u16			vlan_tci;
++
++	sk_buff_data_t		transport_header;
++	sk_buff_data_t		network_header;
++	sk_buff_data_t		mac_header;
++	/* These elements must be at the end, see alloc_skb() for details.  */
++	sk_buff_data_t		tail;
++	sk_buff_data_t		end;
++	unsigned char		*head,
++				*data;
++	unsigned int		truesize;
++	atomic_t		users;
++};
++struct sk_buff_head {
++	/* These two members must be first. */
++	struct sk_buff	*next;
++	struct sk_buff	*prev;
++
++	u32		qlen;
++	_lock	lock;
++};
++#define skb_tail_pointer(skb)	skb->tail
++static inline unsigned char *skb_put(struct sk_buff *skb, unsigned int len)
++{
++	unsigned char *tmp = skb_tail_pointer(skb);
++	//SKB_LINEAR_ASSERT(skb);
++	skb->tail += len;
++	skb->len  += len;
++	return tmp;
++}
++
++static inline unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len)
++{
++	skb->len -= len;
++	if(skb->len < skb->data_len)
++		printf("%s(),%d,error!\n",__FUNCTION__,__LINE__);
++	return skb->data += len;
++}
++static inline unsigned char *skb_pull(struct sk_buff *skb, unsigned int len)
++{
++	#ifdef PLATFORM_FREEBSD
++	return __skb_pull(skb, len);
++	#else
++	return unlikely(len > skb->len) ? NULL : __skb_pull(skb, len);
++	#endif //PLATFORM_FREEBSD
++}
++static inline u32 skb_queue_len(const struct sk_buff_head *list_)
++{
++	return list_->qlen;
++}
++static inline void __skb_insert(struct sk_buff *newsk,
++				struct sk_buff *prev, struct sk_buff *next,
++				struct sk_buff_head *list)
++{
++	newsk->next = next;
++	newsk->prev = prev;
++	next->prev  = prev->next = newsk;
++	list->qlen++;
++}
++static inline void __skb_queue_before(struct sk_buff_head *list,
++				      struct sk_buff *next,
++				      struct sk_buff *newsk)
++{
++	__skb_insert(newsk, next->prev, next, list);
++}
++static inline void skb_queue_tail(struct sk_buff_head *list,
++				   struct sk_buff *newsk)
++{
++	mtx_lock(&list->lock);
++	__skb_queue_before(list, (struct sk_buff *)list, newsk);
++	mtx_unlock(&list->lock);
++}
++static inline struct sk_buff *skb_peek(struct sk_buff_head *list_)
++{
++	struct sk_buff *list = ((struct sk_buff *)list_)->next;
++	if (list == (struct sk_buff *)list_)
++		list = NULL;
++	return list;
++}
++static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list)
++{
++	struct sk_buff *next, *prev;
++
++	list->qlen--;
++	next	   = skb->next;
++	prev	   = skb->prev;
++	skb->next  = skb->prev = NULL;
++	next->prev = prev;
++	prev->next = next;
++}
++
++static inline struct sk_buff *skb_dequeue(struct sk_buff_head *list)
++{
++	mtx_lock(&list->lock);
++
++	struct sk_buff *skb = skb_peek(list);
++	if (skb)
++		__skb_unlink(skb, list);
++
++	mtx_unlock(&list->lock);
++
++	return skb;
++}
++static inline void skb_reserve(struct sk_buff *skb, int len)
++{
++	skb->data += len;
++	skb->tail += len;
++}
++static inline void __skb_queue_head_init(struct sk_buff_head *list)
++{
++	list->prev = list->next = (struct sk_buff *)list;
++	list->qlen = 0;
++}
++/*
++ * This function creates a split out lock class for each invocation;
++ * this is needed for now since a whole lot of users of the skb-queue
++ * infrastructure in drivers have different locking usage (in hardirq)
++ * than the networking core (in softirq only). In the long run either the
++ * network layer or drivers should need annotation to consolidate the
++ * main types of usage into 3 classes.
++ */
++static inline void skb_queue_head_init(struct sk_buff_head *list)
++{
++	_rtw_spinlock_init(&list->lock);
++	__skb_queue_head_init(list);
++}
++unsigned long copy_from_user(void *to, const void *from, unsigned long n);
++unsigned long copy_to_user(void *to, const void *from, unsigned long n);
++struct sk_buff * dev_alloc_skb(unsigned int size);
++struct sk_buff *skb_clone(const struct sk_buff *skb);
++void dev_kfree_skb_any(struct sk_buff *skb);
++#endif //Baron porting from linux, it's all temp solution, needs to check again
++
++
++#if 1 // kenny add Linux compatibility code for Linux USB driver
++#include <dev/usb/usb_compat_linux.h>
++
++#define __init		// __attribute ((constructor))
++#define __exit		// __attribute ((destructor))
++
++/*
++ * Definitions for module_init and module_exit macros.
++ *
++ * These macros will use the SYSINIT framework to call a specified
++ * function (with no arguments) on module loading or unloading.
++ * 
++ */
++
++void module_init_exit_wrapper(void *arg);
++
++#define module_init(initfn)                             \
++        SYSINIT(mod_init_ ## initfn,                    \
++                SI_SUB_KLD, SI_ORDER_FIRST,             \
++                module_init_exit_wrapper, initfn)
++
++#define module_exit(exitfn)                             \
++        SYSUNINIT(mod_exit_ ## exitfn,                  \
++                  SI_SUB_KLD, SI_ORDER_ANY,             \
++                  module_init_exit_wrapper, exitfn)
++
++/*
++ * The usb_register and usb_deregister functions are used to register
++ * usb drivers with the usb subsystem. 
++ */
++int usb_register(struct usb_driver *driver);
++int usb_deregister(struct usb_driver *driver);
++
++/*
++ * usb_get_dev and usb_put_dev - increment/decrement the reference count 
++ * of the usb device structure.
++ *
++ * Original body of usb_get_dev:
++ *
++ *       if (dev)
++ *               get_device(&dev->dev);
++ *       return dev;
++ *
++ * Reference counts are not currently used in this compatibility
++ * layer. So these functions will do nothing.
++ */
++static inline struct usb_device *
++usb_get_dev(struct usb_device *dev)
++{
++        return dev;
++}
++
++static inline void 
++usb_put_dev(struct usb_device *dev)
++{
++        return;
++}
++
++
++// rtw_usb_compat_linux
++int rtw_usb_submit_urb(struct urb *urb, uint16_t mem_flags);
++int rtw_usb_unlink_urb(struct urb *urb);
++int rtw_usb_clear_halt(struct usb_device *dev, struct usb_host_endpoint *uhe);
++int rtw_usb_control_msg(struct usb_device *dev, struct usb_host_endpoint *uhe,
++    uint8_t request, uint8_t requesttype,
++    uint16_t value, uint16_t index, void *data,
++    uint16_t size, usb_timeout_t timeout);
++int rtw_usb_set_interface(struct usb_device *dev, uint8_t iface_no, uint8_t alt_index);
++int rtw_usb_setup_endpoint(struct usb_device *dev,
++    struct usb_host_endpoint *uhe, usb_size_t bufsize);
++struct urb *rtw_usb_alloc_urb(uint16_t iso_packets, uint16_t mem_flags);
++struct usb_host_endpoint *rtw_usb_find_host_endpoint(struct usb_device *dev, uint8_t type, uint8_t ep);
++struct usb_host_interface *rtw_usb_altnum_to_altsetting(const struct usb_interface *intf, uint8_t alt_index);
++struct usb_interface *rtw_usb_ifnum_to_if(struct usb_device *dev, uint8_t iface_no);
++void *rtw_usbd_get_intfdata(struct usb_interface *intf);
++void rtw_usb_linux_register(void *arg);
++void rtw_usb_linux_deregister(void *arg);
++void rtw_usb_linux_free_device(struct usb_device *dev);
++void rtw_usb_free_urb(struct urb *urb);
++void rtw_usb_init_urb(struct urb *urb);
++void rtw_usb_kill_urb(struct urb *urb);
++void rtw_usb_set_intfdata(struct usb_interface *intf, void *data);
++void rtw_usb_fill_bulk_urb(struct urb *urb, struct usb_device *udev,
++    struct usb_host_endpoint *uhe, void *buf,
++    int length, usb_complete_t callback, void *arg);
++int rtw_usb_bulk_msg(struct usb_device *udev, struct usb_host_endpoint *uhe,
++    void *data, int len, uint16_t *pactlen, usb_timeout_t timeout);
++void *usb_get_intfdata(struct usb_interface *intf);
++int usb_linux_init_endpoints(struct usb_device *udev);
++
++
++
++typedef struct urb *  PURB;
++
++typedef unsigned gfp_t;
++#define __GFP_WAIT      ((gfp_t)0x10u)  /* Can wait and reschedule? */
++#define __GFP_HIGH      ((gfp_t)0x20u)  /* Should access emergency pools? */
++#define __GFP_IO        ((gfp_t)0x40u)  /* Can start physical IO? */
++#define __GFP_FS        ((gfp_t)0x80u)  /* Can call down to low-level FS? */
++#define __GFP_COLD      ((gfp_t)0x100u) /* Cache-cold page required */
++#define __GFP_NOWARN    ((gfp_t)0x200u) /* Suppress page allocation failure warning */
++#define __GFP_REPEAT    ((gfp_t)0x400u) /* Retry the allocation.  Might fail */
++#define __GFP_NOFAIL    ((gfp_t)0x800u) /* Retry for ever.  Cannot fail */
++#define __GFP_NORETRY   ((gfp_t)0x1000u)/* Do not retry.  Might fail */
++#define __GFP_NO_GROW   ((gfp_t)0x2000u)/* Slab internal usage */
++#define __GFP_COMP      ((gfp_t)0x4000u)/* Add compound page metadata */
++#define __GFP_ZERO      ((gfp_t)0x8000u)/* Return zeroed page on success */
++#define __GFP_NOMEMALLOC ((gfp_t)0x10000u) /* Don't use emergency reserves */
++#define __GFP_HARDWALL   ((gfp_t)0x20000u) /* Enforce hardwall cpuset memory allocs */
++
++/* This equals 0, but use constants in case they ever change */
++#define GFP_NOWAIT      (GFP_ATOMIC & ~__GFP_HIGH)
++/* GFP_ATOMIC means both !wait (__GFP_WAIT not set) and use emergency pool */
++#define GFP_ATOMIC      (__GFP_HIGH)
++#define GFP_NOIO        (__GFP_WAIT)
++#define GFP_NOFS        (__GFP_WAIT | __GFP_IO)
++#define GFP_KERNEL      (__GFP_WAIT | __GFP_IO | __GFP_FS)
++#define GFP_USER        (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL)
++#define GFP_HIGHUSER    (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL | \
++                         __GFP_HIGHMEM)
++
++
++#endif // kenny add Linux compatibility code for Linux USB
++
++__inline static _list *get_next(_list	*list)
++{
++	return list->next;
++}	
++
++__inline static _list	*get_list_head(_queue	*queue)
++{
++	return (&(queue->queue));
++}
++
++	
++#define LIST_CONTAINOR(ptr, type, member) \
++        ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))	
++
++        
++__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
++{
++	spin_lock_irqsave(plock, *pirqL);
++}
++
++__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
++{
++	spin_unlock_irqrestore(plock, *pirqL);
++}
++
++__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL)
++{
++	spin_lock_irqsave(plock, *pirqL);
++}
++
++__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL)
++{
++	spin_unlock_irqrestore(plock, *pirqL);
++}
++
++__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
++{
++	spin_lock_bh(plock, *pirqL);
++}
++
++__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
++{
++	spin_unlock_bh(plock, *pirqL);
++}
++
++__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
++{
++
++		mtx_lock(pmutex);
++
++}
++
++
++__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
++{
++
++		mtx_unlock(pmutex);
++
++}
++static inline void __list_del(struct list_head * prev, struct list_head * next)
++{
++	next->prev = prev;
++	prev->next = next;
++}
++static inline void INIT_LIST_HEAD(struct list_head *list)
++{
++	list->next = list;
++	list->prev = list;
++}
++__inline static void rtw_list_delete(_list *plist)
++{
++	__list_del(plist->prev, plist->next);
++	INIT_LIST_HEAD(plist);
++}
++
++static inline void timer_hdl(void *ctx)
++{
++	_timer *timer = (_timer *)ctx;
++
++	rtw_mtx_lock(NULL);
++	if (callout_pending(&timer->callout)) {
++		/* callout was reset */
++		rtw_mtx_unlock(NULL);
++		return;
++	}
++
++	if (!callout_active(&timer->callout)) {
++		/* callout was stopped */
++		rtw_mtx_unlock(NULL);
++		return;
++	}
++
++	callout_deactivate(&timer->callout);
++
++	timer->function(timer->arg);
++
++	rtw_mtx_unlock(NULL);
++}
++
++static inline void _init_timer(_timer *ptimer, _nic_hdl padapter, void *pfunc, void *cntx)
++{
++	ptimer->function = pfunc;
++	ptimer->arg = cntx;
++	callout_init(&ptimer->callout, CALLOUT_MPSAFE);
++}
++
++__inline static void _set_timer(_timer *ptimer,u32 delay_time)
++{	
++	if (ptimer->function && ptimer->arg) {
++		rtw_mtx_lock(NULL);
++		callout_reset(&ptimer->callout, delay_time, timer_hdl, ptimer);
++		rtw_mtx_unlock(NULL);
++	}
++}
++
++__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
++{
++	rtw_mtx_lock(NULL);
++	callout_drain(&ptimer->callout);
++	rtw_mtx_unlock(NULL);
++	*bcancelled = 1; /* assume an pending timer to be canceled */
++}
++
++__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
++{
++	printf("%s Not implement yet! \n",__FUNCTION__);
++}
++
++__inline static void _set_workitem(_workitem *pwork)
++{
++	printf("%s Not implement yet! \n",__FUNCTION__);
++//	schedule_work(pwork);
++}
++
++//
++// Global Mutex: can only be used at PASSIVE level.
++//
++
++#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter)                              \
++{                                                               \
++}
++
++#define RELEASE_GLOBAL_MUTEX(_MutexCounter)                              \
++{                                                               \
++}
++
++#define ATOMIC_INIT(i)  { (i) }
++
++static __inline void thread_enter(char *name);
++
++//Atomic integer operations
++typedef uint32_t ATOMIC_T ;
++
++#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc)
++
++#define rtw_free_netdev(netdev) if_free((netdev))
++
++#define NDEV_FMT "%s"
++#define NDEV_ARG(ndev) ""
++#define ADPT_FMT "%s"
++#define ADPT_ARG(adapter) ""
++#define FUNC_NDEV_FMT "%s"
++#define FUNC_NDEV_ARG(ndev) __func__
++#define FUNC_ADPT_FMT "%s"
++#define FUNC_ADPT_ARG(adapter) __func__
++
++#define STRUCT_PACKED
++
++#endif
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_service_ce.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_service_ce.h
+new file mode 100644
+index 000000000..2bf65ef47
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_service_ce.h
+@@ -0,0 +1,200 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __OSDEP_CE_SERVICE_H_
++#define __OSDEP_CE_SERVICE_H_
++
++
++#include <ndis.h>
++#include <ntddndis.h>
++
++#ifdef CONFIG_SDIO_HCI
++#include "SDCardDDK.h"
++#endif
++
++#ifdef CONFIG_USB_HCI
++#include <usbdi.h>
++#endif
++
++typedef HANDLE 	_sema;
++typedef	LIST_ENTRY	_list;
++typedef NDIS_STATUS _OS_STATUS;
++
++typedef NDIS_SPIN_LOCK	_lock;
++
++typedef HANDLE 		_rwlock; //Mutex
++
++typedef u32	_irqL;
++
++typedef NDIS_HANDLE  _nic_hdl;
++
++struct rtw_timer_list {
++	NDIS_MINIPORT_TIMER ndis_timer;
++	void (*function)(void *);
++	void *arg;
++};
++
++struct	__queue	{
++	LIST_ENTRY	queue;
++	_lock	lock;
++};
++
++typedef	NDIS_PACKET	_pkt;
++typedef NDIS_BUFFER	_buffer;
++typedef struct	__queue	_queue;
++
++typedef HANDLE 	_thread_hdl_;
++typedef DWORD thread_return;
++typedef void*	thread_context;
++typedef NDIS_WORK_ITEM _workitem;
++
++
++
++#define SEMA_UPBND	(0x7FFFFFFF)   //8192
++
++__inline static _list *get_prev(_list	*list)
++{
++	return list->Blink;
++}
++	
++__inline static _list *get_next(_list	*list)
++{
++	return list->Flink;
++}
++
++__inline static _list	*get_list_head(_queue	*queue)
++{
++	return (&(queue->queue));
++}
++
++#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
++
++__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
++{
++	NdisAcquireSpinLock(plock);
++}
++
++__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
++{
++	NdisReleaseSpinLock(plock);
++}
++
++__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
++{
++	NdisDprAcquireSpinLock(plock);	
++}
++
++__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
++{
++	NdisDprReleaseSpinLock(plock);	
++}
++
++
++__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
++{
++	WaitForSingleObject(*prwlock, INFINITE );
++
++}
++
++__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
++{
++	ReleaseMutex(*prwlock);
++}
++
++__inline static void rtw_list_delete(_list *plist)
++{
++	RemoveEntryList(plist);
++	InitializeListHead(plist);
++}
++
++static inline void timer_hdl(
++	IN PVOID SystemSpecific1,
++	IN PVOID FunctionContext,
++	IN PVOID SystemSpecific2,
++	IN PVOID SystemSpecific3)
++{
++	_timer *timer = (_timer *)FunctionContext;
++
++	timer->function(timer->arg);
++}
++
++static inline void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx)
++{
++	ptimer->function = pfunc;
++	ptimer->arg = cntx;
++	NdisMInitializeTimer(&ptimer->ndis_timer, nic_hdl, timer_hdl, ptimer);
++}
++
++static inline void _set_timer(_timer *ptimer, u32 delay_time)
++{
++	NdisMSetTimer(ptimer, delay_time);
++}
++
++static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled)
++{
++	NdisMCancelTimer(ptimer, bcancelled);
++}
++
++__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
++{
++
++	NdisInitializeWorkItem(pwork, pfunc, cntx);
++}
++
++__inline static void _set_workitem(_workitem *pwork)
++{
++	NdisScheduleWorkItem(pwork);
++}
++
++#define ATOMIC_INIT(i)  { (i) }
++
++//
++// Global Mutex: can only be used at PASSIVE level.
++//
++
++#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter)                              \
++{                                                               \
++    while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
++    {                                                           \
++        NdisInterlockedDecrement((PULONG)&(_MutexCounter));        \
++        NdisMSleep(10000);                          \
++    }                                                           \
++}
++
++#define RELEASE_GLOBAL_MUTEX(_MutexCounter)                              \
++{                                                               \
++    NdisInterlockedDecrement((PULONG)&(_MutexCounter));              \
++}
++
++// limitation of path length
++#define PATH_LENGTH_MAX MAX_PATH
++
++//Atomic integer operations
++#define ATOMIC_T LONG
++
++#define NDEV_FMT "%s"
++#define NDEV_ARG(ndev) ""
++#define ADPT_FMT "%s"
++#define ADPT_ARG(adapter) ""
++#define FUNC_NDEV_FMT "%s"
++#define FUNC_NDEV_ARG(ndev) __func__
++#define FUNC_ADPT_FMT "%s"
++#define FUNC_ADPT_ARG(adapter) __func__
++
++#define STRUCT_PACKED
++
++
++#endif
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_service_linux.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_service_linux.h
+new file mode 100644
+index 000000000..4fa1731ad
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_service_linux.h
+@@ -0,0 +1,550 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __OSDEP_LINUX_SERVICE_H_
++#define __OSDEP_LINUX_SERVICE_H_
++
++#include <linux/version.h>
++#include <linux/spinlock.h>
++#include <linux/compiler.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <linux/namei.h>
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 5))
++	#include <linux/kref.h>
++#endif
++/* #include <linux/smp_lock.h> */
++#include <linux/netdevice.h>
++#include <linux/inetdevice.h>
++#include <linux/skbuff.h>
++#include <linux/circ_buf.h>
++#include <asm/uaccess.h>
++#include <asm/byteorder.h>
++#include <asm/atomic.h>
++#include <asm/io.h>
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))
++	#include <asm/semaphore.h>
++#else
++	#include <linux/semaphore.h>
++#endif
++#include <linux/sem.h>
++#include <linux/sched.h>
++#include <linux/etherdevice.h>
++#include <linux/wireless.h>
++#include <net/iw_handler.h>
++#include <net/addrconf.h>
++#include <linux/if_arp.h>
++#include <linux/rtnetlink.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>	/* for struct tasklet_struct */
++#include <linux/ip.h>
++#include <linux/kthread.h>
++#include <linux/list.h>
++#include <linux/vmalloc.h>
++
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 5, 41))
++	#include <linux/tqueue.h>
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
++	#include <uapi/linux/limits.h>
++#else
++	#include <linux/limits.h>
++#endif
++
++#ifdef RTK_DMP_PLATFORM
++	#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12))
++		#include <linux/pageremap.h>
++	#endif
++	#include <asm/io.h>
++#endif
++
++#ifdef CONFIG_NET_RADIO
++	#define CONFIG_WIRELESS_EXT
++#endif
++
++/* Monitor mode */
++#include <net/ieee80211_radiotap.h>
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
++	#include <linux/ieee80211.h>
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25) && \
++	 LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29))
++	#define CONFIG_IEEE80211_HT_ADDT_INFO
++#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++	/*	#include <linux/ieee80211.h> */
++	#include <net/cfg80211.h>
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++
++#ifdef CONFIG_HAS_EARLYSUSPEND
++	#include <linux/earlysuspend.h>
++#endif /* CONFIG_HAS_EARLYSUSPEND */
++
++#ifdef CONFIG_EFUSE_CONFIG_FILE
++	#include <linux/fs.h>
++#endif
++
++#ifdef CONFIG_USB_HCI
++	#include <linux/usb.h>
++	#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 21))
++		#include <linux/usb_ch9.h>
++	#else
++		#include <linux/usb/ch9.h>
++	#endif
++#endif
++
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++	#include <net/sock.h>
++	#include <net/tcp.h>
++	#include <linux/udp.h>
++	#include <linux/in.h>
++	#include <linux/netlink.h>
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++
++#ifdef CONFIG_USB_HCI
++	typedef struct urb   *PURB;
++#endif
++
++#if defined(CONFIG_RTW_GRO) && (!defined(CONFIG_RTW_NAPI))
++
++	#error "Enable NAPI before enable GRO\n"
++
++#endif
++
++
++#if (KERNEL_VERSION(2, 6, 29) > LINUX_VERSION_CODE && defined(CONFIG_RTW_NAPI))
++
++	#undef CONFIG_RTW_NAPI
++	/*#warning "Linux Kernel version too old to support NAPI (should newer than 2.6.29)\n"*/
++
++#endif
++
++#if (KERNEL_VERSION(2, 6, 33) > LINUX_VERSION_CODE && defined(CONFIG_RTW_GRO))
++
++	#undef CONFIG_RTW_GRO
++	/*#warning "Linux Kernel version too old to support GRO(should newer than 2.6.33)\n"*/
++
++#endif
++
++typedef struct	semaphore _sema;
++typedef	spinlock_t	_lock;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
++	typedef struct mutex		_mutex;
++#else
++	typedef struct semaphore	_mutex;
++#endif
++struct rtw_timer_list {
++	struct timer_list timer;
++	void (*function)(void *);
++	void *arg;
++};
++
++typedef struct rtw_timer_list _timer;
++typedef struct completion _completion;
++
++struct	__queue	{
++	struct	list_head	queue;
++	_lock	lock;
++};
++
++typedef	struct sk_buff	_pkt;
++typedef unsigned char	_buffer;
++
++typedef struct	__queue	_queue;
++typedef struct	list_head	_list;
++
++/* hlist */
++typedef struct	hlist_head	rtw_hlist_head;
++typedef struct	hlist_node	rtw_hlist_node;
++
++/* RCU */
++typedef struct rcu_head rtw_rcu_head;
++#define rtw_rcu_dereference(p) rcu_dereference((p))
++#define rtw_rcu_dereference_protected(p, c) rcu_dereference_protected(p, c)
++#define rtw_rcu_assign_pointer(p, v) rcu_assign_pointer((p), (v))
++#define rtw_rcu_read_lock() rcu_read_lock()
++#define rtw_rcu_read_unlock() rcu_read_unlock()
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34))
++#define rtw_rcu_access_pointer(p) rcu_access_pointer(p)
++#endif
++
++/* rhashtable */
++#include "../os_dep/linux/rtw_rhashtable.h"
++
++typedef	int	_OS_STATUS;
++/* typedef u32	_irqL; */
++typedef unsigned long _irqL;
++typedef	struct	net_device *_nic_hdl;
++
++typedef void		*_thread_hdl_;
++typedef int		thread_return;
++typedef void	*thread_context;
++
++typedef void timer_hdl_return;
++typedef void *timer_hdl_context;
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
++	typedef struct work_struct _workitem;
++#else
++	typedef struct tq_struct _workitem;
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
++	#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
++#endif
++
++typedef unsigned long systime;
++typedef struct tasklet_struct _tasklet;
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22))
++/* Porting from linux kernel, for compatible with old kernel. */
++static inline unsigned char *skb_tail_pointer(const struct sk_buff *skb)
++{
++	return skb->tail;
++}
++
++static inline void skb_reset_tail_pointer(struct sk_buff *skb)
++{
++	skb->tail = skb->data;
++}
++
++static inline void skb_set_tail_pointer(struct sk_buff *skb, const int offset)
++{
++	skb->tail = skb->data + offset;
++}
++
++static inline unsigned char *skb_end_pointer(const struct sk_buff *skb)
++{
++	return skb->end;
++}
++#endif
++
++__inline static void rtw_list_delete(_list *plist)
++{
++	list_del_init(plist);
++}
++
++__inline static _list *get_next(_list	*list)
++{
++	return list->next;
++}
++
++#define LIST_CONTAINOR(ptr, type, member) \
++	((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
++
++#define rtw_list_first_entry(ptr, type, member) list_first_entry(ptr, type, member)
++
++#define rtw_hlist_for_each_entry(pos, head, member) hlist_for_each_entry(pos, head, member)
++#define rtw_hlist_for_each_safe(pos, n, head) hlist_for_each_safe(pos, n, head)
++#define rtw_hlist_entry(ptr, type, member) hlist_entry(ptr, type, member)
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, n, head, member)
++#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, head, member)
++#else
++#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, np, n, head, member)
++#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, node, head, member)
++#endif
++
++__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
++{
++	spin_lock_irqsave(plock, *pirqL);
++}
++
++__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
++{
++	spin_unlock_irqrestore(plock, *pirqL);
++}
++
++__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL)
++{
++	spin_lock_irqsave(plock, *pirqL);
++}
++
++__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL)
++{
++	spin_unlock_irqrestore(plock, *pirqL);
++}
++
++__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
++{
++	spin_lock_bh(plock);
++}
++
++__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
++{
++	spin_unlock_bh(plock);
++}
++
++__inline static void enter_critical_bh(_lock *plock)
++{
++	spin_lock_bh(plock);
++}
++
++__inline static void exit_critical_bh(_lock *plock)
++{
++	spin_unlock_bh(plock);
++}
++
++__inline static int _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
++{
++	int ret = 0;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
++	/* mutex_lock(pmutex); */
++	ret = mutex_lock_interruptible(pmutex);
++#else
++	ret = down_interruptible(pmutex);
++#endif
++	return ret;
++}
++
++
++__inline static int _enter_critical_mutex_lock(_mutex *pmutex, _irqL *pirqL)
++{
++	int ret = 0;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
++	mutex_lock(pmutex);
++#else
++	down(pmutex);
++#endif
++	return ret;
++}
++
++__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
++	mutex_unlock(pmutex);
++#else
++	up(pmutex);
++#endif
++}
++
++__inline static _list	*get_list_head(_queue	*queue)
++{
++	return &(queue->queue);
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
++static inline void timer_hdl(struct timer_list *in_timer)
++#else
++static inline void timer_hdl(unsigned long cntx)
++#endif
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
++	_timer *ptimer = from_timer(ptimer, in_timer, timer);
++#else
++	_timer *ptimer = (_timer *)cntx;
++#endif
++	ptimer->function(ptimer->arg);
++}
++
++__inline static void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx)
++{
++	ptimer->function = pfunc;
++	ptimer->arg = cntx;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
++	timer_setup(&ptimer->timer, timer_hdl, 0);
++#else
++	/* setup_timer(ptimer, pfunc,(u32)cntx);	 */
++	ptimer->timer.function = timer_hdl;
++	ptimer->timer.data = (unsigned long)ptimer;
++	init_timer(&ptimer->timer);
++#endif
++}
++
++__inline static void _set_timer(_timer *ptimer, u32 delay_time)
++{
++	mod_timer(&ptimer->timer , (jiffies + (delay_time * HZ / 1000)));
++}
++
++__inline static void _cancel_timer(_timer *ptimer, u8 *bcancelled)
++{
++	*bcancelled = del_timer_sync(&ptimer->timer) == 1 ? 1 : 0;
++}
++
++static inline void _init_workitem(_workitem *pwork, void *pfunc, void *cntx)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20))
++	INIT_WORK(pwork, pfunc);
++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
++	INIT_WORK(pwork, pfunc, pwork);
++#else
++	INIT_TQUEUE(pwork, pfunc, pwork);
++#endif
++}
++
++__inline static void _set_workitem(_workitem *pwork)
++{
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
++	schedule_work(pwork);
++#else
++	schedule_task(pwork);
++#endif
++}
++
++__inline static void _cancel_workitem_sync(_workitem *pwork)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22))
++	cancel_work_sync(pwork);
++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
++	flush_scheduled_work();
++#else
++	flush_scheduled_tasks();
++#endif
++}
++/*
++ * Global Mutex: can only be used at PASSIVE level.
++ *   */
++
++#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter)                              \
++	{                                                               \
++		while (atomic_inc_return((atomic_t *)&(_MutexCounter)) != 1) { \
++			atomic_dec((atomic_t *)&(_MutexCounter));        \
++			msleep(10);                          \
++		}                                                           \
++	}
++
++#define RELEASE_GLOBAL_MUTEX(_MutexCounter)                              \
++	{                                                               \
++		atomic_dec((atomic_t *)&(_MutexCounter));        \
++	}
++
++static inline int rtw_netif_queue_stopped(struct net_device *pnetdev)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	return (netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) &&
++		netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 1)) &&
++		netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 2)) &&
++		netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3)));
++#else
++	return netif_queue_stopped(pnetdev);
++#endif
++}
++
++static inline void rtw_netif_wake_queue(struct net_device *pnetdev)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	netif_tx_wake_all_queues(pnetdev);
++#else
++	netif_wake_queue(pnetdev);
++#endif
++}
++
++static inline void rtw_netif_start_queue(struct net_device *pnetdev)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	netif_tx_start_all_queues(pnetdev);
++#else
++	netif_start_queue(pnetdev);
++#endif
++}
++
++static inline void rtw_netif_stop_queue(struct net_device *pnetdev)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	netif_tx_stop_all_queues(pnetdev);
++#else
++	netif_stop_queue(pnetdev);
++#endif
++}
++static inline void rtw_netif_device_attach(struct net_device *pnetdev)
++{
++	netif_device_attach(pnetdev);
++}
++static inline void rtw_netif_device_detach(struct net_device *pnetdev)
++{
++	netif_device_detach(pnetdev);
++}
++static inline void rtw_netif_carrier_on(struct net_device *pnetdev)
++{
++	netif_carrier_on(pnetdev);
++}
++static inline void rtw_netif_carrier_off(struct net_device *pnetdev)
++{
++	netif_carrier_off(pnetdev);
++}
++
++static inline int rtw_merge_string(char *dst, int dst_len, const char *src1, const char *src2)
++{
++	int	len = 0;
++	len += snprintf(dst + len, dst_len - len, "%s", src1);
++	len += snprintf(dst + len, dst_len - len, "%s", src2);
++
++	return len;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
++	#define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)), (sig), 1)
++#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
++	#define rtw_signal_process(pid, sig) kill_proc((pid), (sig), 1)
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
++
++
++/* Suspend lock prevent system from going suspend */
++#ifdef CONFIG_WAKELOCK
++	#include <linux/wakelock.h>
++#elif defined(CONFIG_ANDROID_POWER)
++	#include <linux/android_power.h>
++#endif
++
++/* limitation of path length */
++#define PATH_LENGTH_MAX PATH_MAX
++
++/* Atomic integer operations */
++#define ATOMIC_T atomic_t
++
++#define rtw_netdev_priv(netdev) (((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv)
++
++#define NDEV_FMT "%s"
++#define NDEV_ARG(ndev) ndev->name
++#define ADPT_FMT "%s"
++#define ADPT_ARG(adapter) (adapter->pnetdev ? adapter->pnetdev->name : NULL)
++#define FUNC_NDEV_FMT "%s(%s)"
++#define FUNC_NDEV_ARG(ndev) __func__, ndev->name
++#define FUNC_ADPT_FMT "%s(%s)"
++#define FUNC_ADPT_ARG(adapter) __func__, (adapter->pnetdev ? adapter->pnetdev->name : NULL)
++
++struct rtw_netdev_priv_indicator {
++	void *priv;
++	u32 sizeof_priv;
++};
++struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv);
++extern struct net_device *rtw_alloc_etherdev(int sizeof_priv);
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
++#define rtw_get_same_net_ndev_by_name(ndev, name) dev_get_by_name(name)
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))
++#define rtw_get_same_net_ndev_by_name(ndev, name) dev_get_by_name(ndev->nd_net, name)
++#else
++#define rtw_get_same_net_ndev_by_name(ndev, name) dev_get_by_name(dev_net(ndev), name)
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
++#define rtw_get_bridge_ndev_by_name(name) dev_get_by_name(name)
++#else
++#define rtw_get_bridge_ndev_by_name(name) dev_get_by_name(&init_net, name)
++#endif
++
++#define STRUCT_PACKED __attribute__ ((packed))
++
++
++#endif /* __OSDEP_LINUX_SERVICE_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_service_xp.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_service_xp.h
+new file mode 100644
+index 000000000..57e6f314e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/osdep_service_xp.h
+@@ -0,0 +1,210 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __OSDEP_LINUX_SERVICE_H_
++#define __OSDEP_LINUX_SERVICE_H_
++
++	#include <ndis.h>
++	#include <ntddk.h>
++	#include <ntddndis.h>
++	#include <ntdef.h>
++
++#ifdef CONFIG_USB_HCI
++	#include <usb.h>
++	#include <usbioctl.h>
++	#include <usbdlib.h>
++#endif
++
++	typedef KSEMAPHORE 	_sema;
++	typedef	LIST_ENTRY	_list;
++	typedef NDIS_STATUS _OS_STATUS;
++	
++
++	typedef NDIS_SPIN_LOCK	_lock;
++
++	typedef KMUTEX 			_mutex;
++
++	typedef KIRQL	_irqL;
++
++	// USB_PIPE for WINCE , but handle can be use just integer under windows
++	typedef NDIS_HANDLE  _nic_hdl;
++
++	struct rtw_timer_list {
++		NDIS_MINIPORT_TIMER ndis_timer;
++		void (*function)(void *);
++		void *arg;
++	};
++
++	struct	__queue	{
++		LIST_ENTRY	queue;	
++		_lock	lock;
++	};
++
++	typedef	NDIS_PACKET	_pkt;
++	typedef NDIS_BUFFER	_buffer;
++	typedef struct	__queue	_queue;
++	
++	typedef PKTHREAD _thread_hdl_;
++	typedef void	thread_return;
++	typedef void* thread_context;
++
++	typedef NDIS_WORK_ITEM _workitem;
++
++
++	#define HZ			10000000
++	#define SEMA_UPBND	(0x7FFFFFFF)   //8192
++	
++__inline static _list *get_next(_list	*list)
++{
++	return list->Flink;
++}	
++
++__inline static _list	*get_list_head(_queue	*queue)
++{
++	return (&(queue->queue));
++}
++	
++
++#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
++     
++
++__inline static _enter_critical(_lock *plock, _irqL *pirqL)
++{
++	NdisAcquireSpinLock(plock);	
++}
++
++__inline static _exit_critical(_lock *plock, _irqL *pirqL)
++{
++	NdisReleaseSpinLock(plock);	
++}
++
++
++__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
++{
++	NdisDprAcquireSpinLock(plock);	
++}
++
++__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
++{
++	NdisDprReleaseSpinLock(plock);	
++}
++
++__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
++{
++	NdisDprAcquireSpinLock(plock);
++}
++
++__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
++{
++	NdisDprReleaseSpinLock(plock);
++}
++
++__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
++{
++	KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL);
++}
++
++
++__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
++{
++	KeReleaseMutex(pmutex, FALSE);
++}
++
++
++__inline static void rtw_list_delete(_list *plist)
++{
++	RemoveEntryList(plist);
++	InitializeListHead(plist);	
++}
++
++static inline void timer_hdl(
++	IN PVOID SystemSpecific1,
++	IN PVOID FunctionContext,
++	IN PVOID SystemSpecific2,
++	IN PVOID SystemSpecific3)
++{
++	_timer *timer = (_timer *)FunctionContext;
++
++	timer->function(timer->arg);
++}
++
++static inline void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx)
++{
++	ptimer->function = pfunc;
++	ptimer->arg = cntx;
++	NdisMInitializeTimer(&ptimer->ndis_timer, nic_hdl, timer_hdl, ptimer);
++}
++
++static inline void _set_timer(_timer *ptimer, u32 delay_time)
++{
++	NdisMSetTimer(ptimer, delay_time);
++}
++
++static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled)
++{
++	NdisMCancelTimer(ptimer, bcancelled);
++}
++
++__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
++{
++
++	NdisInitializeWorkItem(pwork, pfunc, cntx);
++}
++
++__inline static void _set_workitem(_workitem *pwork)
++{
++	NdisScheduleWorkItem(pwork);
++}
++
++
++#define ATOMIC_INIT(i)  { (i) }
++
++//
++// Global Mutex: can only be used at PASSIVE level.
++//
++
++#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter)                              \
++{                                                               \
++    while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
++    {                                                           \
++        NdisInterlockedDecrement((PULONG)&(_MutexCounter));        \
++        NdisMSleep(10000);                          \
++    }                                                           \
++}
++
++#define RELEASE_GLOBAL_MUTEX(_MutexCounter)                              \
++{                                                               \
++    NdisInterlockedDecrement((PULONG)&(_MutexCounter));              \
++}
++
++// limitation of path length
++#define PATH_LENGTH_MAX MAX_PATH
++
++//Atomic integer operations
++#define ATOMIC_T LONG
++
++
++#define NDEV_FMT "%s"
++#define NDEV_ARG(ndev) ""
++#define ADPT_FMT "%s"
++#define ADPT_ARG(adapter) ""
++#define FUNC_NDEV_FMT "%s"
++#define FUNC_NDEV_ARG(ndev) __func__
++#define FUNC_ADPT_FMT "%s"
++#define FUNC_ADPT_ARG(adapter) __func__
++
++#define STRUCT_PACKED
++
++#endif
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/pci_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/pci_hal.h
+new file mode 100644
+index 000000000..6eac311a1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/pci_hal.h
+@@ -0,0 +1,60 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __PCI_HAL_H__
++#define __PCI_HAL_H__
++
++#ifdef CONFIG_RTL8188E
++	void rtl8188ee_set_hal_ops(_adapter *padapter);
++#endif
++
++#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
++	void rtl8812ae_set_hal_ops(_adapter *padapter);
++#endif
++
++#if defined(CONFIG_RTL8192E)
++	void rtl8192ee_set_hal_ops(_adapter *padapter);
++#endif
++
++#if defined(CONFIG_RTL8192F)
++	void rtl8192fe_set_hal_ops(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_RTL8723B
++	void rtl8723be_set_hal_ops(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_RTL8723D
++	void rtl8723de_set_hal_ops(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_RTL8814A
++	void rtl8814ae_set_hal_ops(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_RTL8822B
++	void rtl8822be_set_hal_ops(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_RTL8822C
++	void rtl8822ce_set_hal_ops(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_RTL8814B
++	void rtl8814be_set_hal_ops(PADAPTER padapter);
++#endif
++
++u8 rtw_set_hal_ops(_adapter *padapter);
++
++#endif /* __PCIE_HAL_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/pci_ops.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/pci_ops.h
+new file mode 100644
+index 000000000..7b95fde04
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/pci_ops.h
+@@ -0,0 +1,116 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __PCI_OPS_H_
++#define __PCI_OPS_H_
++
++
++#ifdef CONFIG_RTL8188E
++	u32	rtl8188ee_init_desc_ring(_adapter *padapter);
++	u32	rtl8188ee_free_desc_ring(_adapter *padapter);
++	void	rtl8188ee_reset_desc_ring(_adapter *padapter);
++	int	rtl8188ee_interrupt(PADAPTER Adapter);
++	void	rtl8188ee_xmit_tasklet(void *priv);
++	void	rtl8188ee_recv_tasklet(void *priv);
++	void	rtl8188ee_prepare_bcn_tasklet(void *priv);
++	void	rtl8188ee_set_intf_ops(struct _io_ops	*pops);
++	void	rtw8188ee_unmap_beacon_icf(_adapter *padapter);
++#endif
++
++#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
++	u32	rtl8812ae_init_desc_ring(_adapter *padapter);
++	u32	rtl8812ae_free_desc_ring(_adapter *padapter);
++	void	rtl8812ae_reset_desc_ring(_adapter *padapter);
++	int	rtl8812ae_interrupt(PADAPTER Adapter);
++	void	rtl8812ae_xmit_tasklet(void *priv);
++	void	rtl8812ae_recv_tasklet(void *priv);
++	void	rtl8812ae_prepare_bcn_tasklet(void *priv);
++	void	rtl8812ae_set_intf_ops(struct _io_ops	*pops);
++	void	rtw8812ae_unmap_beacon_icf(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_RTL8192E
++	u32	rtl8192ee_init_desc_ring(_adapter *padapter);
++	u32	rtl8192ee_free_desc_ring(_adapter *padapter);
++	void	rtl8192ee_reset_desc_ring(_adapter *padapter);
++	void	rtl8192ee_recv_tasklet(void *priv);
++	void	rtl8192ee_prepare_bcn_tasklet(void *priv);
++	int	rtl8192ee_interrupt(PADAPTER Adapter);
++	void	rtl8192ee_set_intf_ops(struct _io_ops	*pops);
++	void	rtw8192ee_unmap_beacon_icf(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_RTL8192F
++	u32	rtl8192fe_init_desc_ring(_adapter *padapter);
++	u32	rtl8192fe_free_desc_ring(_adapter *padapter);
++	void	rtl8192fe_reset_desc_ring(_adapter *padapter);
++	int	rtl8192fe_interrupt(PADAPTER Adapter);
++	void	rtl8192fe_recv_tasklet(void *priv);
++	void	rtl8192fe_prepare_bcn_tasklet(void *priv);
++	void	rtl8192fe_set_intf_ops(struct _io_ops	*pops);
++	u8 check_tx_desc_resource(_adapter *padapter, int prio);
++	void	rtl8192fe_unmap_beacon_icf(PADAPTER Adapter);
++#endif
++
++#ifdef CONFIG_RTL8723B
++	u32	rtl8723be_init_desc_ring(_adapter *padapter);
++	u32	rtl8723be_free_desc_ring(_adapter *padapter);
++	void	rtl8723be_reset_desc_ring(_adapter *padapter);
++	int	rtl8723be_interrupt(PADAPTER Adapter);
++	void	rtl8723be_recv_tasklet(void *priv);
++	void	rtl8723be_prepare_bcn_tasklet(void *priv);
++	void	rtl8723be_set_intf_ops(struct _io_ops	*pops);
++	void	rtl8723be_unmap_beacon_icf(PADAPTER Adapter);
++#endif
++
++#ifdef CONFIG_RTL8723D
++	u32	rtl8723de_init_desc_ring(_adapter *padapter);
++	u32	rtl8723de_free_desc_ring(_adapter *padapter);
++	void	rtl8723de_reset_desc_ring(_adapter *padapter);
++	int	rtl8723de_interrupt(PADAPTER Adapter);
++	void	rtl8723de_recv_tasklet(void *priv);
++	void	rtl8723de_prepare_bcn_tasklet(void *priv);
++	void	rtl8723de_set_intf_ops(struct _io_ops	*pops);
++	u8 check_tx_desc_resource(_adapter *padapter, int prio);
++	void 	rtl8723de_unmap_beacon_icf(PADAPTER Adapter);
++#endif
++
++#ifdef CONFIG_RTL8814A
++	u32	rtl8814ae_init_desc_ring(_adapter *padapter);
++	u32	rtl8814ae_free_desc_ring(_adapter *padapter);
++	void	rtl8814ae_reset_desc_ring(_adapter *padapter);
++	int	rtl8814ae_interrupt(PADAPTER Adapter);
++	void	rtl8814ae_xmit_tasklet(void *priv);
++	void	rtl8814ae_recv_tasklet(void *priv);
++	void	rtl8814ae_prepare_bcn_tasklet(void *priv);
++	void	rtl8814ae_set_intf_ops(struct _io_ops	*pops);
++	void	rtl8814ae_unmap_beacon_icf(PADAPTER Adapter);
++#endif
++
++#ifdef CONFIG_RTL8822B
++	void rtl8822be_set_intf_ops(struct _io_ops *pops);
++#endif
++
++#ifdef CONFIG_RTL8821C
++	void rtl8821ce_set_intf_ops(struct _io_ops *pops);
++#endif
++
++#ifdef CONFIG_RTL8822C
++	void rtl8822ce_set_intf_ops(struct _io_ops *pops);
++#endif
++
++#ifdef CONFIG_RTL8814B
++	void rtl8814be_set_intf_ops(struct _io_ops *pops);
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/pci_osintf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/pci_osintf.h
+new file mode 100644
+index 000000000..3308ced51
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/pci_osintf.h
+@@ -0,0 +1,69 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __PCI_OSINTF_H
++#define __PCI_OSINTF_H
++
++#ifdef RTK_129X_PLATFORM
++#define PCIE_SLOT1_MEM_START	0x9804F000
++#define PCIE_SLOT1_MEM_LEN	0x1000
++#define PCIE_SLOT1_CTRL_START	0x9804EC00
++
++#define PCIE_SLOT2_MEM_START	0x9803C000
++#define PCIE_SLOT2_MEM_LEN	0x1000
++#define PCIE_SLOT2_CTRL_START	0x9803BC00
++
++#define PCIE_MASK_OFFSET	0x100 /* mask offset from CTRL_START */
++#define PCIE_TRANSLATE_OFFSET	0x104 /* translate offset from CTRL_START */
++#endif
++
++#define PCI_BC_CLK_REQ		BIT0
++#define PCI_BC_ASPM_L0s		BIT1
++#define PCI_BC_ASPM_L1		BIT2
++#define PCI_BC_ASPM_L1Off	BIT3
++//#define PCI_BC_ASPM_LTR	BIT4
++//#define PCI_BC_ASPM_OBFF	BIT5
++
++void	PlatformClearPciPMEStatus(PADAPTER Adapter);
++void	rtw_pci_aspm_config(_adapter *padapter);
++void	rtw_pci_aspm_config_l1off_general(_adapter *padapter, u8 eanble);
++#ifdef CONFIG_64BIT_DMA
++	u8	PlatformEnableDMA64(PADAPTER Adapter);
++#endif
++#ifdef CONFIG_PCI_DYNAMIC_ASPM
++void rtw_pci_set_aspm_lnkctl(_adapter *padapter, u8 mode);
++void rtw_pci_set_l1_latency(_adapter *padapter, u8 mode);
++
++static inline void rtw_pci_dynamic_aspm_set_mode(_adapter *padapter, u8 mode)
++{
++	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
++	struct pci_priv	*pcipriv = &(pdvobjpriv->pcipriv);
++
++	if (mode == pcipriv->aspm_mode)
++		return;
++
++	pcipriv->aspm_mode = mode;
++
++#ifdef CONFIG_PCI_DYNAMIC_ASPM_LINK_CTRL
++	rtw_pci_set_aspm_lnkctl(padapter, mode);
++#endif
++#ifdef CONFIG_PCI_DYNAMIC_ASPM_L1_LATENCY
++	rtw_pci_set_l1_latency(padapter, mode);
++#endif
++}
++#else
++#define rtw_pci_dynamic_aspm_set_mode(adapter, mode)
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/recv_osdep.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/recv_osdep.h
+new file mode 100644
+index 000000000..3ba4957d5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/recv_osdep.h
+@@ -0,0 +1,70 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RECV_OSDEP_H_
++#define __RECV_OSDEP_H_
++
++
++extern sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter);
++extern void _rtw_free_recv_priv(struct recv_priv *precvpriv);
++
++
++extern s32  rtw_recv_entry(union recv_frame *precv_frame);
++void rtw_rframe_set_os_pkt(union recv_frame *rframe);
++extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame);
++extern void rtw_recv_returnpacket(_nic_hdl cnxt, _pkt *preturnedpkt);
++
++#ifdef CONFIG_WIFI_MONITOR
++extern int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame);
++#endif /* CONFIG_WIFI_MONITOR */
++
++#ifdef CONFIG_HOSTAPD_MLME
++extern void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame);
++#endif
++
++struct sta_info;
++extern void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup);
++
++
++int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter);
++int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe);
++void rtw_os_recv_resource_free(struct recv_priv *precvpriv);
++
++
++int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 *pdata, _pkt *pskb);
++int rtw_os_recvframe_duplicate_skb(_adapter *padapter, union recv_frame *pcloneframe, _pkt *pskb);
++void rtw_os_free_recvframe(union recv_frame *precvframe);
++
++
++int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf);
++int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf);
++
++_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, const u8 *da, const u8 *sa
++	, u8 *msdu ,u16 msdu_len, enum rtw_rx_llc_hdl llc_hdl);
++void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, union recv_frame *rframe);
++
++void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf);
++
++#ifdef PLATFORM_LINUX
++#ifdef CONFIG_RTW_NAPI
++#include <linux/netdevice.h>	/* struct napi_struct */
++
++int rtw_recv_napi_poll(struct napi_struct *, int budget);
++#ifdef CONFIG_RTW_NAPI_DYNAMIC
++void dynamic_napi_th_chk (_adapter *adapter);
++#endif /* CONFIG_RTW_NAPI_DYNAMIC */
++#endif /* CONFIG_RTW_NAPI */
++#endif /* PLATFORM_LINUX */
++
++#endif /*  */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_cmd.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_cmd.h
+new file mode 100644
+index 000000000..aba0bec14
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_cmd.h
+@@ -0,0 +1,165 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8188E_CMD_H__
++#define __RTL8188E_CMD_H__
++
++#if 0
++enum cmd_msg_element_id {
++	NONE_CMDMSG_EID,
++	AP_OFFLOAD_EID = 0,
++	SET_PWRMODE_EID = 1,
++	JOINBSS_RPT_EID = 2,
++	RSVD_PAGE_EID = 3,
++	RSSI_4_EID = 4,
++	RSSI_SETTING_EID = 5,
++	MACID_CONFIG_EID = 6,
++	MACID_PS_MODE_EID = 7,
++	P2P_PS_OFFLOAD_EID = 8,
++	SELECTIVE_SUSPEND_ROF_CMD = 9,
++	P2P_PS_CTW_CMD_EID = 32,
++	MAX_CMDMSG_EID
++};
++#else
++typedef enum _RTL8188E_H2C_CMD_ID {
++	/* Class Common */
++	H2C_COM_RSVD_PAGE			= 0x00,
++	H2C_COM_MEDIA_STATUS_RPT	= 0x01,
++	H2C_COM_SCAN					= 0x02,
++	H2C_COM_KEEP_ALIVE			= 0x03,
++	H2C_COM_DISCNT_DECISION		= 0x04,
++#ifndef CONFIG_WOWLAN
++	H2C_COM_WWLAN				= 0x05,
++#endif
++	H2C_COM_INIT_OFFLOAD			= 0x06,
++	H2C_COM_REMOTE_WAKE_CTL	= 0x07,
++	H2C_COM_AP_OFFLOAD			= 0x08,
++	H2C_COM_BCN_RSVD_PAGE		= 0x09,
++	H2C_COM_PROB_RSP_RSVD_PAGE	= 0x0A,
++
++	/* Class PS */
++	H2C_PS_PWR_MODE				= 0x20,
++	H2C_PS_TUNE_PARA				= 0x21,
++	H2C_PS_TUNE_PARA_2			= 0x22,
++	H2C_PS_LPS_PARA				= 0x23,
++	H2C_PS_P2P_OFFLOAD			= 0x24,
++
++	/* Class DM */
++	H2C_DM_MACID_CFG				= 0x40,
++	H2C_DM_TXBF					= 0x41,
++	H2C_RSSI_REPORT				= 0x42,
++	/* Class BT */
++	H2C_BT_COEX_MASK				= 0x60,
++	H2C_BT_COEX_GPIO_MODE		= 0x61,
++	H2C_BT_DAC_SWING_VAL			= 0x62,
++	H2C_BT_PSD_RST				= 0x63,
++
++	/* Class Remote WakeUp */
++#ifdef CONFIG_WOWLAN
++	H2C_COM_WWLAN				= 0x80,
++	H2C_COM_REMOTE_WAKE_CTRL	= 0x81,
++	H2C_COM_AOAC_GLOBAL_INFO	= 0x82,
++	H2C_COM_AOAC_RSVD_PAGE		= 0x83,
++#endif
++
++	/* Class */
++	/* H2C_RESET_TSF				=0xc0, */
++} RTL8188E_H2C_CMD_ID;
++
++#endif
++
++
++struct cmd_msg_parm {
++	u8 eid; /* element id */
++	u8 sz; /* sz */
++	u8 buf[6];
++};
++
++enum {
++	PWRS
++};
++
++typedef struct _SETPWRMODE_PARM {
++	u8 Mode;/* 0:Active,1:LPS,2:WMMPS */
++	/* u8 RLBM:4; */ /* 0:Min,1:Max,2: User define */
++	u8 SmartPS_RLBM;/* LPS=0:PS_Poll,1:PS_Poll,2:NullData,WMM=0:PS_Poll,1:NullData */
++	u8 AwakeInterval;	/* unit: beacon interval */
++	u8 bAllQueueUAPSD;
++	u8 PwrState;/* AllON(0x0c),RFON(0x04),RFOFF(0x00) */
++} SETPWRMODE_PARM, *PSETPWRMODE_PARM;
++
++struct H2C_SS_RFOFF_PARAM {
++	u8 ROFOn; /* 1: on, 0:off */
++	u16 gpio_period; /* unit: 1024 us */
++} __attribute__((packed));
++
++
++typedef struct JOINBSSRPT_PARM_88E {
++	u8 OpMode;	/* RT_MEDIA_STATUS */
++#ifdef CONFIG_WOWLAN
++	u8 MacID;       /* MACID */
++#endif /* CONFIG_WOWLAN */
++} JOINBSSRPT_PARM_88E, *PJOINBSSRPT_PARM_88E;
++
++#if 0
++/* move to hal_com_h2c.h */
++typedef struct _RSVDPAGE_LOC_88E {
++	u8 LocProbeRsp;
++	u8 LocPsPoll;
++	u8 LocNullData;
++	u8 LocQosNull;
++	u8 LocBTQosNull;
++#ifdef CONFIG_WOWLAN
++	u8 LocRemoteCtrlInfo;
++	u8 LocArpRsp;
++	u8 LocNbrAdv;
++	u8 LocGTKRsp;
++	u8 LocGTKInfo;
++	u8 LocProbeReq;
++	u8 LocNetList;
++#endif /* CONFIG_WOWLAN	 */
++} RSVDPAGE_LOC_88E, *PRSVDPAGE_LOC_88E;
++#endif
++
++/* host message to firmware cmd */
++void rtl8188e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
++void rtl8188e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
++s32 FillH2CCmd_88E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
++/* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */
++u8 GetTxBufferRsvdPageNum8188E(_adapter *padapter, bool wowlan);
++
++
++#ifdef CONFIG_P2P
++	void rtl8188e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
++#endif /* CONFIG_P2P */
++
++/* #define H2C_8188E_RSVDPAGE_LOC_LEN      5 */
++/* #define H2C_8188E_AOAC_RSVDPAGE_LOC_LEN 7 */
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
++ * ---------------------------------------------------------------------------------------------------------
++ *   */
++#if 0
++	/* move to hal_com_h2c.h
++	* _RSVDPAGE_LOC_CMD_0x00 */
++	#define SET_8188E_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)     SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++	#define SET_8188E_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)            SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++	#define SET_8188E_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)     SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++	#define SET_8188E_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)     SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++	/*  AOAC_RSVDPAGE_LOC_0x83 */
++	#define SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value)        SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
++	#define SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value)                  SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#endif
++#endif/* __RTL8188E_CMD_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_dm.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_dm.h
+new file mode 100644
+index 000000000..457ae9bca
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_dm.h
+@@ -0,0 +1,27 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8188E_DM_H__
++#define __RTL8188E_DM_H__
++
++void rtl8188e_init_dm_priv(PADAPTER Adapter);
++void rtl8188e_deinit_dm_priv(PADAPTER Adapter);
++void rtl8188e_InitHalDm(PADAPTER Adapter);
++void rtl8188e_HalDmWatchDog(PADAPTER Adapter);
++
++/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */
++
++/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_hal.h
+new file mode 100644
+index 000000000..611cc73b7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_hal.h
+@@ -0,0 +1,316 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8188E_HAL_H__
++#define __RTL8188E_HAL_H__
++
++/* #include "hal_com.h" */
++#include "hal_data.h"
++
++/* include HAL Related header after HAL Related compiling flags */
++#include "rtl8188e_spec.h"
++#include "Hal8188EPhyReg.h"
++#include "Hal8188EPhyCfg.h"
++#include "rtl8188e_rf.h"
++#include "rtl8188e_dm.h"
++#include "rtl8188e_recv.h"
++#include "rtl8188e_xmit.h"
++#include "rtl8188e_cmd.h"
++#include "rtl8188e_led.h"
++#include "Hal8188EPwrSeq.h"
++#ifdef DBG_CONFIG_ERROR_DETECT
++	#include "rtl8188e_sreset.h"
++#endif
++
++/* --------------------------------------------------------------------- */
++/*		RTL8188E Power Configuration CMDs for USB/SDIO/PCIE interfaces */
++/* --------------------------------------------------------------------- */
++#define Rtl8188E_NIC_PWR_ON_FLOW				rtl8188E_power_on_flow
++#define Rtl8188E_NIC_RF_OFF_FLOW				rtl8188E_radio_off_flow
++#define Rtl8188E_NIC_DISABLE_FLOW				rtl8188E_card_disable_flow
++#define Rtl8188E_NIC_ENABLE_FLOW				rtl8188E_card_enable_flow
++#define Rtl8188E_NIC_SUSPEND_FLOW				rtl8188E_suspend_flow
++#define Rtl8188E_NIC_RESUME_FLOW				rtl8188E_resume_flow
++#define Rtl8188E_NIC_PDN_FLOW					rtl8188E_hwpdn_flow
++#define Rtl8188E_NIC_LPS_ENTER_FLOW			rtl8188E_enter_lps_flow
++#define Rtl8188E_NIC_LPS_LEAVE_FLOW			rtl8188E_leave_lps_flow
++
++
++#if 1 /* download firmware related data structure */
++#define MAX_FW_8188E_SIZE			0x8000 /* 32768, 32k / 16384, 16k */
++
++#define FW_8188E_SIZE				0x4000 /* 16384, 16k */
++#define FW_8188E_SIZE_2			0x8000 /* 32768, 32k */
++
++#define FW_8188E_START_ADDRESS	0x1000
++#define FW_8188E_END_ADDRESS		0x1FFF /* 0x5FFF */
++
++
++#define IS_FW_HEADER_EXIST_88E(_pFwHdr)	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x88E0)
++
++typedef struct _RT_FIRMWARE_8188E {
++	FIRMWARE_SOURCE	eFWSource;
++#ifdef CONFIG_EMBEDDED_FWIMG
++	u8			*szFwBuffer;
++#else
++	u8			szFwBuffer[MAX_FW_8188E_SIZE];
++#endif
++	u32			ulFwLength;
++} RT_FIRMWARE_8188E, *PRT_FIRMWARE_8188E;
++
++/*
++ * This structure must be cared byte-ordering
++ *   */
++
++typedef struct _RT_8188E_FIRMWARE_HDR {
++	/* 8-byte alinment required */
++
++	/* --- LONG WORD 0 ---- */
++	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
++	u8		Category;	/* AP/NIC and USB/PCI */
++	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
++	u16		Version;		/* FW Version */
++	u8		Subversion;	/* FW Subversion, default 0x00 */
++	u16		Rsvd1;
++
++
++	/* --- LONG WORD 1 ---- */
++	u8		Month;	/* Release time Month field */
++	u8		Date;	/* Release time Date field */
++	u8		Hour;	/* Release time Hour field */
++	u8		Minute;	/* Release time Minute field */
++	u16		RamCodeSize;	/* The size of RAM code */
++	u8		Foundry;
++	u8		Rsvd2;
++
++	/* --- LONG WORD 2 ---- */
++	u32		SvnIdx;	/* The SVN entry index */
++	u32		Rsvd3;
++
++	/* --- LONG WORD 3 ---- */
++	u32		Rsvd4;
++	u32		Rsvd5;
++} RT_8188E_FIRMWARE_HDR, *PRT_8188E_FIRMWARE_HDR;
++#endif /* download firmware related data structure */
++
++
++#define DRIVER_EARLY_INT_TIME_8188E			0x05
++#define BCN_DMA_ATIME_INT_TIME_8188E		0x02
++
++
++/* #define MAX_RX_DMA_BUFFER_SIZE_88E	      0x2400 */ /* 9k for 88E nornal chip , */ /* MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */
++#ifdef CONFIG_USB_HCI
++	#define RX_DMA_SIZE_88E(__Adapter) 0x2800
++#else
++	#define RX_DMA_SIZE_88E(__Adapter) ((!IS_VENDOR_8188E_I_CUT_SERIES(__Adapter))?0x2800:0x4000)
++#endif
++
++#ifdef CONFIG_WOWLAN
++	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
++#else
++	#define RESV_FMWF	0
++#endif
++
++#define RX_DMA_RESERVD_FW_FEATURE	0x200 /* for tx report (64*8) */
++
++#define MAX_RX_DMA_BUFFER_SIZE_88E(__Adapter) (RX_DMA_SIZE_88E(__Adapter)-RX_DMA_RESERVD_FW_FEATURE)
++
++#define MAX_TX_REPORT_BUFFER_SIZE			0x0400 /* 1k */
++
++#define PAGE_SIZE_TX_88E PAGE_SIZE_128
++/* Note: We will divide number of page equally for each queue other than public queue!
++ * 22k = 22528 bytes = 176 pages (@page =  128 bytes)
++ * BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_88E
++ * 1 ps-poll / 1 null-data /1 prob_rsp /1 QOS null-data = 4 pages */
++
++#define BCNQ_PAGE_NUM_88E		(MAX_BEACON_LEN / PAGE_SIZE_TX_88E + 4) /*0x09*/
++
++/* For WoWLan , more reserved page */
++#ifdef CONFIG_WOWLAN
++	/* 1 ArpRsp + 2 NbrAdv + 2 NDPInfo + 1 RCI + 1 AOAC = 7 pages */
++	#define WOWLAN_PAGE_NUM_88E	0x07
++#else
++	#define WOWLAN_PAGE_NUM_88E	0x00
++#endif
++
++/* Note:
++Tx FIFO Size : previous CUT:22K /I_CUT after:32KB
++Tx page Size : 128B
++Total page numbers : 176(0xB0) / 256(0x100)
++*/
++#ifdef CONFIG_USB_HCI
++	#define TOTAL_PAGE_NUMBER_88E(_Adapter) (0xB0 - 1)
++#else
++	#define TOTAL_PAGE_NUMBER_88E(_Adapter)	((IS_VENDOR_8188E_I_CUT_SERIES(_Adapter)?0x100:0xB0) - 1)/* must reserved 1 page for dma issue */
++#endif
++#define TX_TOTAL_PAGE_NUMBER_88E(_Adapter)	(TOTAL_PAGE_NUMBER_88E(_Adapter) - BCNQ_PAGE_NUM_88E - WOWLAN_PAGE_NUM_88E)
++#define TX_PAGE_BOUNDARY_88E(_Adapter)		(TX_TOTAL_PAGE_NUMBER_88E(_Adapter) + 1) /* beacon header start address */
++
++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_88E(_Adapter)	TX_TOTAL_PAGE_NUMBER_88E(_Adapter)
++#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E(_Adapter)		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_88E(_Adapter) + 1)
++
++/* For Normal Chip Setting
++ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723B */
++#define NORMAL_PAGE_NUM_HPQ_88E		0x0
++#define NORMAL_PAGE_NUM_LPQ_88E		0x09
++#define NORMAL_PAGE_NUM_NPQ_88E		0x0
++
++/* Note: For Normal Chip Setting, modify later */
++#define WMM_NORMAL_PAGE_NUM_HPQ_88E		0x29
++#define WMM_NORMAL_PAGE_NUM_LPQ_88E		0x1C
++#define WMM_NORMAL_PAGE_NUM_NPQ_88E		0x1C
++
++
++/* -------------------------------------------------------------------------
++ *	Chip specific
++ * ------------------------------------------------------------------------- */
++#define CHIP_BONDING_IDENTIFIER(_value)	(((_value)>>22) & 0x3)
++#define CHIP_BONDING_92C_1T2R	0x1
++#define CHIP_BONDING_88C_USB_MCARD	0x2
++#define CHIP_BONDING_88C_USB_HP	0x1
++
++/* -------------------------------------------------------------------------
++ *	Channel Plan
++ * ------------------------------------------------------------------------- */
++
++
++#define EFUSE_REAL_CONTENT_LEN		512
++#define EFUSE_MAP_LEN				128
++#define EFUSE_MAX_SECTION			16
++#define EFUSE_IC_ID_OFFSET			506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
++#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN)
++/*
++ * <Roger_Notes>
++ * To prevent out of boundary programming case,
++ * leave 1byte and program full section
++ * 9bytes + 1byt + 5bytes and pre 1byte.
++ * For worst case:
++ * | 1byte|----8bytes----|1byte|--5bytes--|
++ * |         |            Reserved(14bytes)	      |
++ *   */
++#define EFUSE_OOB_PROTECT_BYTES 		15	/* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
++
++#define		EFUSE_REAL_CONTENT_LEN_88E	256
++#define		EFUSE_MAP_LEN_88E		512
++#define		EFUSE_MAX_SECTION_88E		64
++#define		EFUSE_MAX_WORD_UNIT_88E		4
++#define		EFUSE_IC_ID_OFFSET_88E			506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
++#define		AVAILABLE_EFUSE_ADDR_88E(addr)	(addr < EFUSE_REAL_CONTENT_LEN_88E)
++/* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
++ * 9bytes + 1byt + 5bytes and pre 1byte.
++ * For worst case:
++ * | 2byte|----8bytes----|1byte|--7bytes--|  */ /* 92D */
++#define 		EFUSE_OOB_PROTECT_BYTES_88E	18	/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */
++#define		EFUSE_PROTECT_BYTES_BANK_88E	16
++
++
++/* ********************************************************
++ *			EFUSE for BT definition
++ * ******************************************************** */
++#define EFUSE_BT_REAL_CONTENT_LEN		1536	/* 512*3 */
++#define EFUSE_BT_MAP_LEN				1024	/* 1k bytes */
++#define EFUSE_BT_MAX_SECTION			128		/* 1024/8 */
++
++#define EFUSE_PROTECT_BYTES_BANK		16
++
++#define INCLUDE_MULTI_FUNC_BT(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
++#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
++
++/* #define IS_MULTI_FUNC_CHIP(_Adapter)	(((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */
++
++/* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */
++
++#ifdef CONFIG_PCI_HCI
++	/* according to the define in the rtw_xmit.h, rtw_recv.h */
++	#define TX_DESC_NUM_8188EE  TXDESC_NUM   /* 128 */
++	#ifdef CONFIG_CONCURRENT_MODE
++		/*#define BE_QUEUE_TX_DESC_NUM_8188EE  (TXDESC_NUM<<1)*/		/* 256 */
++		#define BE_QUEUE_TX_DESC_NUM_8188EE  ((TXDESC_NUM<<1)+(TXDESC_NUM>>1))    /* 320 */
++		/*#define BE_QUEUE_TX_DESC_NUM_8188EE  ((TXDESC_NUM<<1)+TXDESC_NUM)*/    /* 384 */
++	#else
++		#define BE_QUEUE_TX_DESC_NUM_8188EE  TXDESC_NUM /* 128 */
++		/*#define BE_QUEUE_TX_DESC_NUM_8188EE  (TXDESC_NUM+(TXDESC_NUM>>1)) */ /* 192 */
++	#endif
++
++	void InterruptRecognized8188EE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent);
++	void UpdateInterruptMask8188EE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
++#endif /* CONFIG_PCI_HCI */
++
++/* rtl8188e_hal_init.c */
++
++s32 rtl8188e_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
++void _8051Reset88E(PADAPTER padapter);
++void rtl8188e_InitializeFirmwareVars(PADAPTER padapter);
++
++
++s32 InitLLTTable(PADAPTER padapter, u8 txpktbuf_bndy);
++
++/* EFuse */
++u8 GetEEPROMSize8188E(PADAPTER padapter);
++void Hal_InitPGData88E(PADAPTER padapter);
++void Hal_EfuseParseIDCode88E(PADAPTER padapter, u8 *hwinfo);
++void Hal_ReadTxPowerInfo88E(PADAPTER padapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
++
++void Hal_EfuseParseEEPROMVer88E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void rtl8188e_EfuseParseChnlPlan(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseCustomerID88E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_ReadAntennaDiversity88E(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
++void Hal_ReadThermalMeter_88E(PADAPTER	Adapter, u8 *PROMContent, BOOLEAN	AutoloadFail);
++void Hal_EfuseParseXtal_8188E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseBoardType88E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_ReadPowerSavingMode88E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_ReadPAType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
++void Hal_ReadAmplifierType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
++void Hal_ReadRFEType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
++
++BOOLEAN HalDetectPwrDownMode88E(PADAPTER Adapter);
++
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++	void Hal_DetectWoWMode(PADAPTER pAdapter);
++#endif /* CONFIG_WOWLAN */
++
++
++#ifdef CONFIG_RF_POWER_TRIM
++	void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++#endif /*CONFIG_RF_POWER_TRIM*/
++
++
++void InitBeaconParameters_8188e(_adapter *adapter);
++void SetBeaconRelatedRegisters8188E(PADAPTER padapter);
++
++void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc);
++void init_hal_spec_8188e(_adapter *adapter);
++
++void rtl8188e_start_thread(_adapter *padapter);
++void rtl8188e_stop_thread(_adapter *padapter);
++
++void rtw_IOL_cmd_tx_pkt_buf_dump(ADAPTER *Adapter, int data_len);
++#ifdef CONFIG_IOL_EFUSE_PATCH
++	s32 rtl8188e_iol_efuse_patch(PADAPTER padapter);
++#endif/* CONFIG_IOL_EFUSE_PATCH */
++void _InitTransferPageSize(PADAPTER padapter);
++
++u8 SetHwReg8188E(PADAPTER padapter, u8 variable, u8 *val);
++void GetHwReg8188E(PADAPTER padapter, u8 variable, u8 *val);
++
++u8
++GetHalDefVar8188E(
++		PADAPTER				Adapter,
++		HAL_DEF_VARIABLE		eVariable,
++		void						*pValue
++);
++#ifdef CONFIG_GPIO_API
++int rtl8188e_GpioFuncCheck(PADAPTER adapter, u8 gpio_num);
++#endif
++#endif /* __RTL8188E_HAL_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_led.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_led.h
+new file mode 100644
+index 000000000..ef0546750
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_led.h
+@@ -0,0 +1,37 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8188E_LED_H__
++#define __RTL8188E_LED_H__
++
++#ifdef CONFIG_RTW_SW_LED
++
++/* ********************************************************************************
++ * Interface to manipulate LED objects.
++ * ******************************************************************************** */
++#ifdef CONFIG_USB_HCI
++	void rtl8188eu_InitSwLeds(PADAPTER padapter);
++	void rtl8188eu_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_PCI_HCI
++	void rtl8188ee_InitSwLeds(PADAPTER padapter);
++	void rtl8188ee_DeInitSwLeds(PADAPTER padapter);
++#endif
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	void rtl8188es_InitSwLeds(PADAPTER padapter);
++	void rtl8188es_DeInitSwLeds(PADAPTER padapter);
++#endif
++
++#endif
++#endif /*CONFIG_RTW_SW_LED*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_recv.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_recv.h
+new file mode 100644
+index 000000000..31058c1b1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_recv.h
+@@ -0,0 +1,156 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8188E_RECV_H__
++#define __RTL8188E_RECV_H__
++
++#define RECV_BLK_SZ 512
++#define RECV_BLK_CNT 16
++#define RECV_BLK_TH RECV_BLK_CNT
++
++#if defined(CONFIG_USB_HCI)
++	#ifndef MAX_RECVBUF_SZ
++		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
++			/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
++			/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
++			/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
++			#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
++			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
++		#else
++			#define MAX_RECVBUF_SZ (4000) /* about 4K */
++		#endif
++	#endif /* !MAX_RECVBUF_SZ */
++
++#elif defined(CONFIG_PCI_HCI)
++	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
++	/*	#define MAX_RECVBUF_SZ (9100) */
++	/* #else */
++	#define MAX_RECVBUF_SZ (4000) /* about 4K
++	* #endif */
++
++
++#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++
++	#define MAX_RECVBUF_SZ (10240)
++
++#endif
++
++/* Rx smooth factor */
++#define	Rx_Smooth_Factor (20)
++
++#define TX_RPT1_PKT_LEN 8
++
++typedef struct rxreport_8188e {
++	/* Offset 0 */
++	u32 pktlen:14;
++	u32 crc32:1;
++	u32 icverr:1;
++	u32 drvinfosize:4;
++	u32 security:3;
++	u32 qos:1;
++	u32 shift:2;
++	u32 physt:1;
++	u32 swdec:1;
++	u32 ls:1;
++	u32 fs:1;
++	u32 eor:1;
++	u32 own:1;
++
++	/* Offset 4 */
++	u32 macid:5;
++	u32 tid:4;
++	u32 hwrsvd:4;
++	u32 amsdu:1;
++	u32 paggr:1;
++	u32 faggr:1;
++	u32 a1fit:4;
++	u32 a2fit:4;
++	u32 pam:1;
++	u32 pwr:1;
++	u32 md:1;
++	u32 mf:1;
++	u32 type:2;
++	u32 mc:1;
++	u32 bc:1;
++
++	/* Offset 8 */
++	u32 seq:12;
++	u32 frag:4;
++	u32 nextpktlen:14;
++	u32 nextind:1;
++	u32 rsvd0831:1;
++
++	/* Offset 12 */
++	u32 rxmcs:6;
++	u32 rxht:1;
++	u32 gf:1;
++	u32 splcp:1;
++	u32 bw:1;
++	u32 htc:1;
++	u32 eosp:1;
++	u32 bssidfit:2;
++	u32 rpt_sel:2;
++	u32 rsvd1216:13;
++	u32 pattern_match:1;
++	u32 unicastwake:1;
++	u32 magicwake:1;
++
++	/* Offset 16 */
++	/*
++	u32 pattern0match:1;
++	u32 pattern1match:1;
++	u32 pattern2match:1;
++	u32 pattern3match:1;
++	u32 pattern4match:1;
++	u32 pattern5match:1;
++	u32 pattern6match:1;
++	u32 pattern7match:1;
++	u32 pattern8match:1;
++	u32 pattern9match:1;
++	u32 patternamatch:1;
++	u32 patternbmatch:1;
++	u32 patterncmatch:1;
++	u32 rsvd1613:19;
++	*/
++	u32 rsvd16;
++
++	/* Offset 20 */
++	u32 tsfl;
++
++	/* Offset 24 */
++	u32 bassn:12;
++	u32 bavld:1;
++	u32 rsvd2413:19;
++} RXREPORT, *PRXREPORT;
++
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	s32 rtl8188es_init_recv_priv(PADAPTER padapter);
++	void rtl8188es_free_recv_priv(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_USB_HCI
++	void rtl8188eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
++	s32 rtl8188eu_init_recv_priv(PADAPTER padapter);
++	void rtl8188eu_free_recv_priv(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	s32 rtl8188ee_init_recv_priv(PADAPTER padapter);
++	void rtl8188ee_free_recv_priv(PADAPTER padapter);
++#endif
++
++void rtl8188e_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *prxstat);
++
++#endif /* __RTL8188E_RECV_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_rf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_rf.h
+new file mode 100644
+index 000000000..8dc413e1d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_rf.h
+@@ -0,0 +1,27 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8188E_RF_H__
++#define __RTL8188E_RF_H__
++
++
++
++int	PHY_RF6052_Config8188E(PADAPTER		Adapter);
++void		rtl8188e_RF_ChangeTxPath(PADAPTER	Adapter,
++			u16		DataRate);
++void		rtl8188e_PHY_RF6052SetBandwidth(
++		PADAPTER				Adapter,
++		enum channel_width		Bandwidth);
++
++#endif/* __RTL8188E_RF_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_spec.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_spec.h
+new file mode 100644
+index 000000000..802659a5f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_spec.h
+@@ -0,0 +1,159 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8188E_SPEC_H__
++#define __RTL8188E_SPEC_H__
++
++
++/* ************************************************************
++ * 8188E Regsiter offset definition
++ * ************************************************************ */
++
++
++/* ************************************************************
++ *
++ * ************************************************************ */
++
++/* -----------------------------------------------------
++ *
++ *	0x0000h ~ 0x00FFh	System Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_BB_PAD_CTRL				0x0064
++#define REG_HMEBOX_E0					0x0088
++#define REG_HMEBOX_E1					0x008A
++#define REG_HMEBOX_E2					0x008C
++#define REG_HMEBOX_E3					0x008E
++#define REG_HMEBOX_EXT_0				0x01F0
++#define REG_HMEBOX_EXT_1				0x01F4
++#define REG_HMEBOX_EXT_2				0x01F8
++#define REG_HMEBOX_EXT_3				0x01FC
++#define REG_HIMR_88E					0x00B0 /* RTL8188E */
++#define REG_HISR_88E					0x00B4 /* RTL8188E */
++#define REG_HIMRE_88E					0x00B8 /* RTL8188E */
++#define REG_HISRE_88E					0x00BC /* RTL8188E */
++
++#define	REG_DBI_WDATA_8188E				0x0348	/* DBI Write data */
++#define	REG_DBI_RDATA_8188E				0x034C	/* DBI Read data */
++#define	REG_DBI_ADDR_8188E				0x0350	/* DBI Address */
++#define	REG_DBI_FLAG_8188E				0x0352	/* DBI Read/Write Flag */
++#define	REG_MDIO_WDATA_8188E				0x0354	/* MDIO for Write PCIE PHY */
++#define	REG_MDIO_RDATA_8188E				0x0356	/* MDIO for Reads PCIE PHY */
++#define	REG_MDIO_CTL_8188E				0x0358	/* MDIO for Control */
++
++#define REG_MACID_NO_LINK_0			0x0484
++#define REG_MACID_NO_LINK_1			0x0488
++#define REG_MACID_PAUSE_0			0x048c
++#define REG_MACID_PAUSE_1			0x0490
++
++/* -----------------------------------------------------
++ *
++ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_PKTBUF_DBG_ADDR			(REG_PKTBUF_DBG_CTRL)
++#define REG_RXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+2)
++#define REG_TXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+3)
++#define REG_WOWLAN_WAKE_REASON		REG_MCUTST_WOWLAN
++
++/* -----------------------------------------------------
++ *
++ *	0x0200h ~ 0x027Fh	TXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ *
++ *	0x0280h ~ 0x02FFh	RXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ *
++ *	0x0300h ~ 0x03FFh	PCIe
++ *
++ * ----------------------------------------------------- */
++#define REG_PCIE_HRPWM_8188E		0x0361	/* PCIe RPWM */
++#define REG_PCIE_HCPWM_8188E		0x0363	/* PCIe CPWM */
++
++/* -----------------------------------------------------
++ *
++ *	0x0400h ~ 0x047Fh	Protocol Configuration
++ *
++ * ----------------------------------------------------- */
++#ifdef CONFIG_WOWLAN
++	#define REG_TXPKTBUF_IV_LOW             0x01a4
++	#define REG_TXPKTBUF_IV_HIGH            0x01a8
++#endif
++
++/* -----------------------------------------------------
++ *
++ *	0x0500h ~ 0x05FFh	EDCA Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ *
++ *	0x0600h ~ 0x07FFh	WMAC Configuration
++ *
++ * ----------------------------------------------------- */
++#ifdef CONFIG_RF_POWER_TRIM
++	#define EEPROM_RF_GAIN_OFFSET			0xC1
++	#define EEPROM_RF_GAIN_VAL				0xF6
++	#define EEPROM_THERMAL_OFFSET			0xF5
++#endif /*CONFIG_RF_POWER_TRIM*/
++/* ----------------------------------------------------------------------------
++ * 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits)
++ * ----------------------------------------------------------------------------
++ * IOL config for REG_FDHM0(Reg0x88) */
++#define CMD_INIT_LLT					BIT0
++#define CMD_READ_EFUSE_MAP		BIT1
++#define CMD_EFUSE_PATCH			BIT2
++#define CMD_IOCONFIG				BIT3
++#define CMD_INIT_LLT_ERR			BIT4
++#define CMD_READ_EFUSE_MAP_ERR	BIT5
++#define CMD_EFUSE_PATCH_ERR		BIT6
++#define CMD_IOCONFIG_ERR			BIT7
++
++/* -----------------------------------------------------
++ *
++ *	Redifine register definition for compatibility
++ *
++ * ----------------------------------------------------- */
++
++/* TODO: use these definition when using REG_xxx naming rule.
++ * NOTE: DO NOT Remove these definition. Use later. */
++#define ISR_88E				REG_HISR_88E
++
++#ifdef CONFIG_PCI_HCI
++	/* #define IMR_RX_MASK		(IMR_ROK_88E|IMR_RDU_88E|IMR_RXFOVW_88E) */
++	#define IMR_TX_MASK			(IMR_VODOK_88E | IMR_VIDOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E | IMR_MGNTDOK_88E | IMR_HIGHDOK_88E | IMR_BCNDERR0_88E)
++
++	#ifdef CONFIG_CONCURRENT_MODE
++		#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E | IMR_BCNDMAINT_E_88E)
++	#else
++		#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E)
++	#endif
++
++	#define RT_AC_INT_MASKS	(IMR_VIDOK_88E | IMR_VODOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E)
++#endif
++
++/* ----------------------------------------------------------------------------
++ * 8192C EEPROM/EFUSE share register definition.
++ * ---------------------------------------------------------------------------- */
++
++#define EFUSE_ACCESS_ON			0x69	/* For RTL8723 only. */
++#define EFUSE_ACCESS_OFF			0x00	/* For RTL8723 only. */
++
++#endif /* __RTL8188E_SPEC_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_sreset.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_sreset.h
+new file mode 100644
+index 000000000..f4ec2d88c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_sreset.h
+@@ -0,0 +1,24 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8188E_SRESET_H_
++#define _RTL8188E_SRESET_H_
++
++#include <rtw_sreset.h>
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++	extern void rtl8188e_sreset_xmit_status_check(_adapter *padapter);
++	extern void rtl8188e_sreset_linked_status_check(_adapter *padapter);
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_xmit.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_xmit.h
+new file mode 100644
+index 000000000..c8f20169b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188e_xmit.h
+@@ -0,0 +1,293 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8188E_XMIT_H__
++#define __RTL8188E_XMIT_H__
++
++
++
++
++/* For 88e early mode */
++#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
++#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
++#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
++#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
++#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
++#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
++#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
++
++/*
++ * defined for TX DESC Operation
++ *   */
++
++#define MAX_TID (15)
++
++/* OFFSET 0 */
++#define OFFSET_SZ	0
++#define OFFSET_SHT	16
++#define BMC		BIT(24)
++#define LSG		BIT(26)
++#define FSG		BIT(27)
++#define OWN		BIT(31)
++
++
++/* OFFSET 4 */
++#define PKT_OFFSET_SZ		0
++#define QSEL_SHT			8
++#define RATE_ID_SHT			16
++#define NAVUSEHDR			BIT(20)
++#define SEC_TYPE_SHT		22
++#define PKT_OFFSET_SHT		26
++
++/* OFFSET 8 */
++#define AGG_EN				BIT(12)
++#define AGG_BK					BIT(16)
++#define AMPDU_DENSITY_SHT	20
++#define ANTSEL_A			BIT(24)
++#define ANTSEL_B			BIT(25)
++#define TX_ANT_CCK_SHT		26
++#define TX_ANTL_SHT			28
++#define TX_ANT_HT_SHT		30
++
++/* OFFSET 12 */
++#define SEQ_SHT				16
++#define EN_HWSEQ			BIT(31)
++
++/* OFFSET 16 */
++#define	QOS                          BIT(6)
++#define	HW_SSN				BIT(7)
++#define	USERATE			BIT(8)
++#define	DISDATAFB			BIT(10)
++#define   CTS_2_SELF			BIT(11)
++#define	RTS_EN				BIT(12)
++#define	HW_RTS_EN			BIT(13)
++#define	DATA_SHORT			BIT(24)
++#define	PWR_STATUS_SHT	15
++#define	DATA_SC_SHT		20
++#define	DATA_BW			BIT(25)
++
++/* OFFSET 20 */
++#define	RTY_LMT_EN			BIT(17)
++
++
++/* OFFSET 20 */
++#define SGI					BIT(6)
++#define USB_TXAGG_NUM_SHT	24
++
++typedef struct txdesc_88e {
++	/* Offset 0 */
++	u32 pktlen:16;
++	u32 offset:8;
++	u32 bmc:1;
++	u32 htc:1;
++	u32 ls:1;
++	u32 fs:1;
++	u32 linip:1;
++	u32 noacm:1;
++	u32 gf:1;
++	u32 own:1;
++
++	/* Offset 4 */
++	u32 macid:6;
++	u32 rsvd0406:2;
++	u32 qsel:5;
++	u32 rd_nav_ext:1;
++	u32 lsig_txop_en:1;
++	u32 pifs:1;
++	u32 rate_id:4;
++	u32 navusehdr:1;
++	u32 en_desc_id:1;
++	u32 sectype:2;
++	u32 rsvd0424:2;
++	u32 pkt_offset:5;	/* unit: 8 bytes */
++	u32 rsvd0431:1;
++
++	/* Offset 8 */
++	u32 rts_rc:6;
++	u32 data_rc:6;
++	u32 agg_en:1;
++	u32 rd_en:1;
++	u32 bar_rty_th:2;
++	u32 bk:1;
++	u32 morefrag:1;
++	u32 raw:1;
++	u32 ccx:1;
++	u32 ampdu_density:3;
++	u32 bt_null:1;
++	u32 ant_sel_a:1;
++	u32 ant_sel_b:1;
++	u32 tx_ant_cck:2;
++	u32 tx_antl:2;
++	u32 tx_ant_ht:2;
++
++	/* Offset 12 */
++	u32 nextheadpage:8;
++	u32 tailpage:8;
++	u32 seq:12;
++	u32 cpu_handle:1;
++	u32 tag1:1;
++	u32 trigger_int:1;
++	u32 hwseq_en:1;
++
++	/* Offset 16 */
++	u32 rtsrate:5;
++	u32 ap_dcfe:1;
++	u32 hwseq_sel:2;
++	u32 userate:1;
++	u32 disrtsfb:1;
++	u32 disdatafb:1;
++	u32 cts2self:1;
++	u32 rtsen:1;
++	u32 hw_rts_en:1;
++	u32 port_id:1;
++	u32 pwr_status:3;
++	u32 wait_dcts:1;
++	u32 cts2ap_en:1;
++	u32 data_sc:2;
++	u32 data_stbc:2;
++	u32 data_short:1;
++	u32 data_bw:1;
++	u32 rts_short:1;
++	u32 rts_bw:1;
++	u32 rts_sc:2;
++	u32 vcs_stbc:2;
++
++	/* Offset 20 */
++	u32 datarate:6;
++	u32 sgi:1;
++	u32 try_rate:1;
++	u32 data_ratefb_lmt:5;
++	u32 rts_ratefb_lmt:4;
++	u32 rty_lmt_en:1;
++	u32 data_rt_lmt:6;
++	u32 usb_txagg_num:8;
++
++	/* Offset 24 */
++	u32 txagg_a:5;
++	u32 txagg_b:5;
++	u32 use_max_len:1;
++	u32 max_agg_num:5;
++	u32 mcsg1_max_len:4;
++	u32 mcsg2_max_len:4;
++	u32 mcsg3_max_len:4;
++	u32 mcs7_sgi_max_len:4;
++
++	/* Offset 28 */
++	u32 checksum:16;	/* TxBuffSize(PCIe)/CheckSum(USB) */
++	u32 sw0:8; /* offset 30 */
++	u32 sw1:4;
++	u32 mcs15_sgi_max_len:4;
++} TXDESC_8188E, *PTXDESC_8188E;
++
++#define txdesc_set_ccx_sw_88e(txdesc, value) \
++	do { \
++		((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \
++		((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \
++	} while (0)
++
++struct txrpt_ccx_88e {
++	/* offset 0 */
++	u8 tag1:1;
++	u8 pkt_num:3;
++	u8 txdma_underflow:1;
++	u8 int_bt:1;
++	u8 int_tri:1;
++	u8 int_ccx:1;
++
++	/* offset 1 */
++	u8 mac_id:6;
++	u8 pkt_ok:1;
++	u8 bmc:1;
++
++	/* offset 2 */
++	u8 retry_cnt:6;
++	u8 lifetime_over:1;
++	u8 retry_over:1;
++
++	/* offset 3 */
++	u8 ccx_qtime0;
++	u8 ccx_qtime1;
++
++	/* offset 5 */
++	u8 final_data_rate;
++
++	/* offset 6 */
++	u8 sw1:4;
++	u8 qsel:4;
++
++	/* offset 7 */
++	u8 sw0;
++};
++
++#define txrpt_ccx_sw_88e(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8))
++#define txrpt_ccx_qtime_88e(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
++
++#define SET_TX_DESC_SEC_TYPE_8188E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
++
++void rtl8188e_fill_fake_txdesc(PADAPTER	padapter, u8 *pDesc, u32 BufferLen,
++			       u8 IsPsPoll, u8	IsBTQosNull, u8 bDataFrame);
++void rtl8188e_cal_txdesc_chksum(struct tx_desc	*ptxdesc);
++void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	s32 rtl8188es_init_xmit_priv(PADAPTER padapter);
++	void rtl8188es_free_xmit_priv(PADAPTER padapter);
++	s32 rtl8188es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8188es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	rtl8188es_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	thread_return rtl8188es_xmit_thread(thread_context context);
++	s32 rtl8188es_xmit_buf_handler(PADAPTER padapter);
++
++	#ifdef CONFIG_SDIO_TX_TASKLET
++		void rtl8188es_xmit_tasklet(void *priv);
++	#endif
++#endif
++
++#ifdef CONFIG_USB_HCI
++	s32 rtl8188eu_init_xmit_priv(PADAPTER padapter);
++	void rtl8188eu_free_xmit_priv(PADAPTER padapter);
++	s32 rtl8188eu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8188eu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	rtl8188eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8188eu_xmit_buf_handler(PADAPTER padapter);
++	void rtl8188eu_xmit_tasklet(void *priv);
++	s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	s32 rtl8188ee_init_xmit_priv(PADAPTER padapter);
++	void rtl8188ee_free_xmit_priv(PADAPTER padapter);
++	void	rtl8188ee_xmitframe_resume(_adapter *padapter);
++	s32 rtl8188ee_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8188ee_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	rtl8188ee_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	void rtl8188ee_xmit_tasklet(void *priv);
++#endif
++
++
++
++#ifdef CONFIG_TX_EARLY_MODE
++	void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++#endif
++
++#ifdef CONFIG_XMIT_ACK
++	void dump_txrpt_ccx_88e(void *buf);
++	void handle_txrpt_ccx_88e(_adapter *adapter, u8 *buf);
++#else
++	#define dump_txrpt_ccx_88e(buf) do {} while (0)
++	#define handle_txrpt_ccx_88e(adapter, buf) do {} while (0)
++#endif /* CONFIG_XMIT_ACK */
++
++void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
++#endif /* __RTL8188E_XMIT_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_cmd.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_cmd.h
+new file mode 100644
+index 000000000..a90a630c5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_cmd.h
+@@ -0,0 +1,206 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8188F_CMD_H__
++#define __RTL8188F_CMD_H__
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++enum h2c_cmd_8188F {
++	/* Common Class: 000 */
++	H2C_8188F_RSVD_PAGE = 0x00,
++	H2C_8188F_MEDIA_STATUS_RPT = 0x01,
++	H2C_8188F_SCAN_ENABLE = 0x02,
++	H2C_8188F_KEEP_ALIVE = 0x03,
++	H2C_8188F_DISCON_DECISION = 0x04,
++	H2C_8188F_PSD_OFFLOAD = 0x05,
++	H2C_8188F_AP_OFFLOAD = 0x08,
++	H2C_8188F_BCN_RSVDPAGE = 0x09,
++	H2C_8188F_PROBERSP_RSVDPAGE = 0x0A,
++	H2C_8188F_FCS_RSVDPAGE = 0x10,
++	H2C_8188F_FCS_INFO = 0x11,
++	H2C_8188F_AP_WOW_GPIO_CTRL = 0x13,
++
++	/* PoweSave Class: 001 */
++	H2C_8188F_SET_PWR_MODE = 0x20,
++	H2C_8188F_PS_TUNING_PARA = 0x21,
++	H2C_8188F_PS_TUNING_PARA2 = 0x22,
++	H2C_8188F_P2P_LPS_PARAM = 0x23,
++	H2C_8188F_P2P_PS_OFFLOAD = 0x24,
++	H2C_8188F_PS_SCAN_ENABLE = 0x25,
++	H2C_8188F_SAP_PS_ = 0x26,
++	H2C_8188F_INACTIVE_PS_ = 0x27, /* Inactive_PS */
++	H2C_8188F_FWLPS_IN_IPS_ = 0x28,
++
++	/* Dynamic Mechanism Class: 010 */
++	H2C_8188F_MACID_CFG = 0x40,
++	H2C_8188F_TXBF = 0x41,
++	H2C_8188F_RSSI_SETTING = 0x42,
++	H2C_8188F_AP_REQ_TXRPT = 0x43,
++	H2C_8188F_INIT_RATE_COLLECT = 0x44,
++	H2C_8188F_RA_PARA_ADJUST = 0x46,
++
++	/* BT Class: 011 */
++	H2C_8188F_B_TYPE_TDMA = 0x60,
++	H2C_8188F_BT_INFO = 0x61,
++	H2C_8188F_FORCE_BT_TXPWR = 0x62,
++	H2C_8188F_BT_IGNORE_WLANACT = 0x63,
++	H2C_8188F_DAC_SWING_VALUE = 0x64,
++	H2C_8188F_ANT_SEL_RSV = 0x65,
++	H2C_8188F_WL_OPMODE = 0x66,
++	H2C_8188F_BT_MP_OPER = 0x67,
++	H2C_8188F_BT_CONTROL = 0x68,
++	H2C_8188F_BT_WIFI_CTRL = 0x69,
++	H2C_8188F_BT_FW_PATCH = 0x6A,
++	H2C_8188F_BT_WLAN_CALIBRATION = 0x6D,
++
++	/* WOWLAN Class: 100 */
++	H2C_8188F_WOWLAN = 0x80,
++	H2C_8188F_REMOTE_WAKE_CTRL = 0x81,
++	H2C_8188F_AOAC_GLOBAL_INFO = 0x82,
++	H2C_8188F_AOAC_RSVD_PAGE = 0x83,
++	H2C_8188F_AOAC_RSVD_PAGE2 = 0x84,
++	H2C_8188F_D0_SCAN_OFFLOAD_CTRL = 0x85,
++	H2C_8188F_D0_SCAN_OFFLOAD_INFO = 0x86,
++	H2C_8188F_CHNL_SWITCH_OFFLOAD = 0x87,
++	H2C_8188F_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
++	H2C_8188F_P2P_OFFLOAD = 0x8B,
++
++	H2C_8188F_RESET_TSF = 0xC0,
++	H2C_8188F_MAXID,
++};
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
++ * ---------------------------------------------------------------------------------------------------------
++ * _RSVDPAGE_LOC_CMD_0x00 */
++#define SET_8188F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8188F_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_8188F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8188F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8188F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++/* _KEEP_ALIVE_CMD_0x03 */
++#define SET_8188F_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_8188F_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_8188F_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
++#define SET_8188F_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++
++/* _DISCONNECT_DECISION_CMD_0x04 */
++#define SET_8188F_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_8188F_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_8188F_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_8188F_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
++
++/* _PWR_MOD_CMD_0x20 */
++#define SET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8188F_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
++#define SET_8188F_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
++#define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8188F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
++#define SET_8188F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++#define GET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
++
++/* _PS_TUNE_PARAM_CMD_0x21 */
++#define SET_8188F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_8188F_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
++#define SET_8188F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
++#define SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++
++/* _MACID_CFG_CMD_0x40 */
++#define SET_8188F_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8188F_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
++#define SET_8188F_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
++#define SET_8188F_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
++#define SET_8188F_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
++#define SET_8188F_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
++#define SET_8188F_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
++#define SET_8188F_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
++#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
++#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
++#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
++
++/* _RSSI_SETTING_CMD_0x42 */
++#define SET_8188F_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8188F_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
++#define SET_8188F_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++
++/* _AP_REQ_TXRPT_CMD_0x43 */
++#define SET_8188F_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8188F_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++
++/* _FORCE_BT_TXPWR_CMD_0x62 */
++#define SET_8188F_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++
++/* _FORCE_BT_MP_OPER_CMD_0x67 */
++#define SET_8188F_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
++#define SET_8188F_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
++#define SET_8188F_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_8188F_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
++#define SET_8188F_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++#define SET_8188F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
++
++/* _BT_FW_PATCH_0x6A */
++#define SET_8188F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
++#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
++
++
++/* ---------------------------------------------------------------------------------------------------------
++ * -------------------------------------------    Structure    --------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    Function Statement     --------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++/* host message to firmware cmd */
++void rtl8188f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
++void rtl8188f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
++void rtl8188f_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
++/* s32 rtl8188f_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
++void rtl8188f_set_FwPsTuneParam_cmd(PADAPTER padapter);
++void rtl8188f_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);
++void rtl8188f_download_rsvd_page(PADAPTER padapter, u8 mstatus);
++#ifdef CONFIG_BT_COEXIST
++	void rtl8188f_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
++#endif /* CONFIG_BT_COEXIST */
++#ifdef CONFIG_P2P
++void rtl8188f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
++#endif /* CONFIG_P2P */
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_TDLS_CH_SW
++void rtl8188f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
++#endif
++#endif
++
++#ifdef CONFIG_P2P_WOWLAN
++void rtl8188f_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
++#endif
++
++void rtl8188f_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
++
++s32 FillH2CCmd8188F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
++u8 GetTxBufferRsvdPageNum8188F(_adapter *padapter, bool wowlan);
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_dm.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_dm.h
+new file mode 100644
+index 000000000..342ade9a5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_dm.h
+@@ -0,0 +1,39 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8188F_DM_H__
++#define __RTL8188F_DM_H__
++/* ************************************************************
++ * Description:
++ *
++ * This file is for 8188F dynamic mechanism only
++ *
++ *
++ * ************************************************************ */
++
++/* ************************************************************
++ * structure and define
++ * ************************************************************ */
++
++/* ************************************************************
++ * function prototype
++ * ************************************************************ */
++
++void rtl8188f_init_dm_priv(PADAPTER padapter);
++void rtl8188f_deinit_dm_priv(PADAPTER padapter);
++
++void rtl8188f_InitHalDm(PADAPTER padapter);
++void rtl8188f_HalDmWatchDog(PADAPTER padapter);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_hal.h
+new file mode 100644
+index 000000000..5db99a41e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_hal.h
+@@ -0,0 +1,260 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8188F_HAL_H__
++#define __RTL8188F_HAL_H__
++
++#include "hal_data.h"
++
++#include "rtl8188f_spec.h"
++#include "rtl8188f_rf.h"
++#include "rtl8188f_dm.h"
++#include "rtl8188f_recv.h"
++#include "rtl8188f_xmit.h"
++#include "rtl8188f_cmd.h"
++#include "rtl8188f_led.h"
++#include "Hal8188FPwrSeq.h"
++#include "Hal8188FPhyReg.h"
++#include "Hal8188FPhyCfg.h"
++#ifdef DBG_CONFIG_ERROR_DETECT
++#include "rtl8188f_sreset.h"
++#endif
++
++#define FW_8188F_SIZE			0x8000
++#define FW_8188F_START_ADDRESS	0x1000
++#define FW_8188F_END_ADDRESS		0x1FFF /* 0x5FFF */
++
++#define IS_FW_HEADER_EXIST_8188F(_pFwHdr)	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x88F0)
++
++typedef struct _RT_FIRMWARE {
++	FIRMWARE_SOURCE	eFWSource;
++#ifdef CONFIG_EMBEDDED_FWIMG
++	u8			*szFwBuffer;
++#else
++	u8			szFwBuffer[FW_8188F_SIZE];
++#endif
++	u32			ulFwLength;
++} RT_FIRMWARE_8188F, *PRT_FIRMWARE_8188F;
++
++/*
++ * This structure must be cared byte-ordering
++ *
++ * Added by tynli. 2009.12.04. */
++typedef struct _RT_8188F_FIRMWARE_HDR {
++	/* 8-byte alinment required */
++
++	/* --- LONG WORD 0 ---- */
++	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
++	u8		Category;	/* AP/NIC and USB/PCI */
++	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
++	u16		Version;		/* FW Version */
++	u16		Subversion;	/* FW Subversion, default 0x00 */
++
++	/* --- LONG WORD 1 ---- */
++	u8		Month;	/* Release time Month field */
++	u8		Date;	/* Release time Date field */
++	u8		Hour;	/* Release time Hour field */
++	u8		Minute;	/* Release time Minute field */
++	u16		RamCodeSize;	/* The size of RAM code */
++	u16		Rsvd2;
++
++	/* --- LONG WORD 2 ---- */
++	u32		SvnIdx;	/* The SVN entry index */
++	u32		Rsvd3;
++
++	/* --- LONG WORD 3 ---- */
++	u32		Rsvd4;
++	u32		Rsvd5;
++} RT_8188F_FIRMWARE_HDR, *PRT_8188F_FIRMWARE_HDR;
++
++#define DRIVER_EARLY_INT_TIME_8188F		0x05
++#define BCN_DMA_ATIME_INT_TIME_8188F		0x02
++
++/* for 8188F
++ * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
++#define PAGE_SIZE_TX_8188F			128
++#define PAGE_SIZE_RX_8188F			8
++
++#define RX_DMA_SIZE_8188F			0x4000	/* 16K */
++#ifdef CONFIG_FW_C2H_DEBUG
++	#define RX_DMA_RESERVED_SIZE_8188F	0x100	/* 256B, reserved for c2h debug message */
++#else
++	#define RX_DMA_RESERVED_SIZE_8188F	0x80	/* 128B, reserved for tx report */
++#endif
++
++#ifdef CONFIG_WOWLAN
++	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
++#else
++	#define RESV_FMWF	0
++#endif
++
++#define RX_DMA_BOUNDARY_8188F		(RX_DMA_SIZE_8188F - RX_DMA_RESERVED_SIZE_8188F - 1)
++
++/* Note: We will divide number of page equally for each queue other than public queue! */
++
++/* For General Reserved Page Number(Beacon Queue is reserved page)
++ * BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_8188F,
++ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1, CTS-2-SELF / LTE QoS Null */
++
++#define BCNQ_PAGE_NUM_8188F		(MAX_BEACON_LEN / PAGE_SIZE_TX_8188F + 6) /*0x08*/
++
++/* For WoWLan , more reserved page
++ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt:1 ,PNO: 6
++ * NS offload:2 NDP info: 1
++ */
++#ifdef CONFIG_WOWLAN
++	#define WOWLAN_PAGE_NUM_8188F	0x0b
++#else
++	#define WOWLAN_PAGE_NUM_8188F	0x00
++#endif
++
++#ifdef CONFIG_PNO_SUPPORT
++#undef WOWLAN_PAGE_NUM_8188F
++#define WOWLAN_PAGE_NUM_8188F	0x15
++#endif
++
++#ifdef CONFIG_AP_WOWLAN
++#define AP_WOWLAN_PAGE_NUM_8188F	0x02
++#endif
++
++#define TX_TOTAL_PAGE_NUMBER_8188F	(0xFF - BCNQ_PAGE_NUM_8188F - WOWLAN_PAGE_NUM_8188F)
++#define TX_PAGE_BOUNDARY_8188F		(TX_TOTAL_PAGE_NUMBER_8188F + 1)
++
++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F	TX_TOTAL_PAGE_NUMBER_8188F
++#define WMM_NORMAL_TX_PAGE_BOUNDARY_8188F		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F + 1)
++
++/* For Normal Chip Setting
++ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8188F */
++#define NORMAL_PAGE_NUM_HPQ_8188F		0x0C
++#define NORMAL_PAGE_NUM_LPQ_8188F		0x02
++#define NORMAL_PAGE_NUM_NPQ_8188F		0x02
++
++/* Note: For Normal Chip Setting, modify later */
++#define WMM_NORMAL_PAGE_NUM_HPQ_8188F		0x30
++#define WMM_NORMAL_PAGE_NUM_LPQ_8188F		0x20
++#define WMM_NORMAL_PAGE_NUM_NPQ_8188F		0x20
++
++
++#include "HalVerDef.h"
++#include "hal_com.h"
++
++#define EFUSE_OOB_PROTECT_BYTES (34 + 1)
++
++#define HAL_EFUSE_MEMORY
++
++#define HWSET_MAX_SIZE_8188F			512
++#define EFUSE_REAL_CONTENT_LEN_8188F	256
++#define EFUSE_MAP_LEN_8188F				512
++#define EFUSE_MAX_SECTION_8188F			(EFUSE_MAP_LEN_8188F / 8)
++
++#define EFUSE_IC_ID_OFFSET			506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
++#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8188F)
++
++#define EFUSE_ACCESS_ON			0x69	/* For RTL8188 only. */
++#define EFUSE_ACCESS_OFF			0x00	/* For RTL8188 only. */
++
++/* ********************************************************
++ *			EFUSE for BT definition
++ * ******************************************************** */
++#define EFUSE_BT_REAL_BANK_CONTENT_LEN	512
++#define EFUSE_BT_REAL_CONTENT_LEN		1536	/* 512*3 */
++#define EFUSE_BT_MAP_LEN				1024	/* 1k bytes */
++#define EFUSE_BT_MAX_SECTION			128		/* 1024/8 */
++
++#define EFUSE_PROTECT_BYTES_BANK		16
++
++#define INCLUDE_MULTI_FUNC_BT(_Adapter)		(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
++#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
++
++/* rtl8188a_hal_init.c */
++s32 rtl8188f_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
++void rtl8188f_FirmwareSelfReset(PADAPTER padapter);
++void rtl8188f_InitializeFirmwareVars(PADAPTER padapter);
++
++void rtl8188f_InitAntenna_Selection(PADAPTER padapter);
++void rtl8188f_DeinitAntenna_Selection(PADAPTER padapter);
++void rtl8188f_CheckAntenna_Selection(PADAPTER padapter);
++void rtl8188f_init_default_value(PADAPTER padapter);
++
++s32 rtl8188f_InitLLTTable(PADAPTER padapter);
++
++s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
++s32 CardDisableWithoutHWSM(PADAPTER padapter);
++
++/* EFuse */
++u8 GetEEPROMSize8188F(PADAPTER padapter);
++void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
++void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
++void Hal_EfuseParseTxPowerInfo_8188F(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
++/* void Hal_EfuseParseBTCoexistInfo_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); */
++void Hal_EfuseParseEEPROMVer_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseChnlPlan_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseCustomerID_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParsePowerSavingMode_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseAntennaDiversity_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseXtal_8188F(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
++void Hal_EfuseParseThermalMeter_8188F(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
++void Hal_EfuseParseKFreeData_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++
++#if 0 /* Do not need for rtl8188f */
++void Hal_EfuseParseVoltage_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
++#endif
++
++void rtl8188f_set_pll_ref_clk_sel(_adapter *adapter, u8 sel);
++
++void rtl8188f_set_hal_ops(struct hal_ops *pHalFunc);
++void init_hal_spec_8188f(_adapter *adapter);
++u8 SetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val);
++void GetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val);
++u8 SetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
++u8 GetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
++
++/* register */
++void rtl8188f_InitBeaconParameters(PADAPTER padapter);
++void rtl8188f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
++void	_InitBurstPktLen_8188FS(PADAPTER Adapter);
++void _8051Reset8188(PADAPTER padapter);
++#ifdef CONFIG_WOWLAN
++void Hal_DetectWoWMode(PADAPTER pAdapter);
++#endif /* CONFIG_WOWLAN */
++
++void rtl8188f_start_thread(_adapter *padapter);
++void rtl8188f_stop_thread(_adapter *padapter);
++
++#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
++	void rtl8188fs_init_checkbthang_workqueue(_adapter *adapter);
++	void rtl8188fs_free_checkbthang_workqueue(_adapter *adapter);
++	void rtl8188fs_cancle_checkbthang_workqueue(_adapter *adapter);
++	void rtl8188fs_hal_check_bt_hang(_adapter *adapter);
++#endif
++
++#ifdef CONFIG_GPIO_WAKEUP
++void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
++#endif
++
++#ifdef CONFIG_MP_INCLUDED
++int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
++#endif
++
++void CCX_FwC2HTxRpt_8188f(PADAPTER padapter, u8 *pdata, u8 len);
++
++u8 MRateToHwRate8188F(u8  rate);
++u8 HwRateToMRate8188F(u8	 rate);
++
++#ifdef CONFIG_PCI_HCI
++BOOLEAN	InterruptRecognized8188FE(PADAPTER Adapter);
++void	UpdateInterruptMask8188FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_led.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_led.h
+new file mode 100644
+index 000000000..ef5d1a776
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_led.h
+@@ -0,0 +1,45 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8188F_LED_H__
++#define __RTL8188F_LED_H__
++#ifdef CONFIG_RTW_SW_LED
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++
++/* ********************************************************************************
++ * Interface to manipulate LED objects.
++ * ******************************************************************************** */
++#ifdef CONFIG_USB_HCI
++void rtl8188fu_InitSwLeds(PADAPTER padapter);
++void rtl8188fu_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_SDIO_HCI
++void rtl8188fs_InitSwLeds(PADAPTER padapter);
++void rtl8188fs_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_GSPI_HCI
++void rtl8188fs_InitSwLeds(PADAPTER padapter);
++void rtl8188fs_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_PCI_HCI
++void rtl8188fe_InitSwLeds(PADAPTER padapter);
++void rtl8188fe_DeInitSwLeds(PADAPTER padapter);
++#endif
++
++#endif
++#endif/*CONFIG_RTW_SW_LED*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_recv.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_recv.h
+new file mode 100644
+index 000000000..ca065988a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_recv.h
+@@ -0,0 +1,65 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8188F_RECV_H__
++#define __RTL8188F_RECV_H__
++
++#if defined(CONFIG_USB_HCI)
++	#ifndef MAX_RECVBUF_SZ
++
++		#ifdef CONFIG_MINIMAL_MEMORY_USAGE
++			#define MAX_RECVBUF_SZ (4000) /* about 4K */
++		#else
++			#ifdef CONFIG_PLATFORM_MSTAR
++				#define MAX_RECVBUF_SZ (8192) /* 8K */
++			#elif defined(CONFIG_PLATFORM_HISILICON)
++				#define MAX_RECVBUF_SZ (16384) /* 16k */
++			#else
++				#define MAX_RECVBUF_SZ (32768) /* 32k */
++			#endif
++			/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
++			/* #define MAX_RECVBUF_SZ (10240)  */ /* 10K */
++			/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
++			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k		 */
++		#endif
++	#endif /* !MAX_RECVBUF_SZ */
++#elif defined(CONFIG_PCI_HCI)
++	#define MAX_RECVBUF_SZ (4000) /* about 4K */
++#elif defined(CONFIG_SDIO_HCI)
++	#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8188F + 1)
++#endif /* CONFIG_SDIO_HCI */
++
++/* Rx smooth factor */
++#define	Rx_Smooth_Factor (20)
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++s32 rtl8188fs_init_recv_priv(PADAPTER padapter);
++void rtl8188fs_free_recv_priv(PADAPTER padapter);
++s32 rtl8188fs_recv_hdl(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_USB_HCI
++int rtl8188fu_init_recv_priv(_adapter *padapter);
++void rtl8188fu_free_recv_priv(_adapter *padapter);
++void rtl8188fu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++s32 rtl8188fe_init_recv_priv(PADAPTER padapter);
++void rtl8188fe_free_recv_priv(PADAPTER padapter);
++#endif
++
++void rtl8188f_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
++
++#endif /* __RTL8188F_RECV_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_rf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_rf.h
+new file mode 100644
+index 000000000..a0338313b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_rf.h
+@@ -0,0 +1,25 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8188F_RF_H__
++#define __RTL8188F_RF_H__
++
++int	PHY_RF6052_Config8188F(PADAPTER		Adapter);
++
++void
++PHY_RF6052SetBandwidth8188F(
++		PADAPTER				Adapter,
++		enum channel_width		Bandwidth);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_spec.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_spec.h
+new file mode 100644
+index 000000000..d947ba800
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_spec.h
+@@ -0,0 +1,275 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8188F_SPEC_H__
++#define __RTL8188F_SPEC_H__
++
++#include <drv_conf.h>
++
++
++#define HAL_NAV_UPPER_UNIT_8188F		128		/* micro-second */
++
++/* -----------------------------------------------------
++ *
++ *	0x0000h ~ 0x00FFh	System Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_RSV_CTRL_8188F				0x001C	/* 3 Byte */
++#define REG_BT_WIFI_ANTENNA_SWITCH_8188F	0x0038
++#define REG_HSISR_8188F					0x005c
++#define REG_PAD_CTRL1_8188F		0x0064
++#define REG_AFE_CTRL_4_8188F		0x0078
++#define REG_HMEBOX_DBG_0_8188F	0x0088
++#define REG_HMEBOX_DBG_1_8188F	0x008A
++#define REG_HMEBOX_DBG_2_8188F	0x008C
++#define REG_HMEBOX_DBG_3_8188F	0x008E
++#define REG_HIMR0_8188F					0x00B0
++#define REG_HISR0_8188F					0x00B4
++#define REG_HIMR1_8188F					0x00B8
++#define REG_HISR1_8188F					0x00BC
++#define REG_PMC_DBG_CTRL2_8188F			0x00CC
++
++/* -----------------------------------------------------
++ *
++ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_C2HEVT_CMD_ID_8188F	0x01A0
++#define REG_C2HEVT_CMD_LEN_8188F	0x01AE
++#define REG_WOWLAN_WAKE_REASON 0x01C7
++#define REG_WOWLAN_GTK_DBG1	0x630
++#define REG_WOWLAN_GTK_DBG2	0x634
++
++#define REG_HMEBOX_EXT0_8188F			0x01F0
++#define REG_HMEBOX_EXT1_8188F			0x01F4
++#define REG_HMEBOX_EXT2_8188F			0x01F8
++#define REG_HMEBOX_EXT3_8188F			0x01FC
++
++/* -----------------------------------------------------
++ *
++ *	0x0200h ~ 0x027Fh	TXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ *
++ *	0x0280h ~ 0x02FFh	RXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_RXDMA_CONTROL_8188F		0x0286 /* Control the RX DMA. */
++#define REG_RXDMA_MODE_CTRL_8188F		0x0290
++
++/* -----------------------------------------------------
++ *
++ *	0x0300h ~ 0x03FFh	PCIe
++ *
++ * ----------------------------------------------------- */
++#define	REG_PCIE_CTRL_REG_8188F		0x0300
++#define	REG_INT_MIG_8188F				0x0304	/* Interrupt Migration */
++#define	REG_BCNQ_DESA_8188F			0x0308	/* TX Beacon Descriptor Address */
++#define	REG_HQ_DESA_8188F				0x0310	/* TX High Queue Descriptor Address */
++#define	REG_MGQ_DESA_8188F			0x0318	/* TX Manage Queue Descriptor Address */
++#define	REG_VOQ_DESA_8188F			0x0320	/* TX VO Queue Descriptor Address */
++#define	REG_VIQ_DESA_8188F				0x0328	/* TX VI Queue Descriptor Address */
++#define	REG_BEQ_DESA_8188F			0x0330	/* TX BE Queue Descriptor Address */
++#define	REG_BKQ_DESA_8188F			0x0338	/* TX BK Queue Descriptor Address */
++#define	REG_RX_DESA_8188F				0x0340	/* RX Queue	Descriptor Address */
++#define	REG_DBI_WDATA_8188F			0x0348	/* DBI Write Data */
++#define	REG_DBI_RDATA_8188F			0x034C	/* DBI Read Data */
++#define	REG_DBI_ADDR_8188F				0x0350	/* DBI Address */
++#define	REG_DBI_FLAG_8188F				0x0352	/* DBI Read/Write Flag */
++#define	REG_MDIO_WDATA_8188F		0x0354	/* MDIO for Write PCIE PHY */
++#define	REG_MDIO_RDATA_8188F			0x0356	/* MDIO for Reads PCIE PHY */
++#define	REG_MDIO_CTL_8188F			0x0358	/* MDIO for Control */
++#define	REG_DBG_SEL_8188F				0x0360	/* Debug Selection Register */
++#define	REG_PCIE_HRPWM_8188F			0x0361	/* PCIe RPWM */
++#define	REG_PCIE_HCPWM_8188F			0x0363	/* PCIe CPWM */
++#define	REG_PCIE_MULTIFET_CTRL_8188F	0x036A	/* PCIE Multi-Fethc Control */
++
++/* -----------------------------------------------------
++ *
++ *	0x0400h ~ 0x047Fh	Protocol Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_TXPKTBUF_BCNQ_BDNY_8188F	0x0424
++#define REG_TXPKTBUF_MGQ_BDNY_8188F	0x0425
++#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F	0x045D
++#ifdef CONFIG_WOWLAN
++#define REG_TXPKTBUF_IV_LOW             0x0484
++#define REG_TXPKTBUF_IV_HIGH            0x0488
++#endif
++#define REG_AMPDU_BURST_MODE_8188F	0x04BC
++
++/* -----------------------------------------------------
++ *
++ *	0x0500h ~ 0x05FFh	EDCA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_SECONDARY_CCA_CTRL_8188F	0x0577
++
++/* -----------------------------------------------------
++ *
++ *	0x0600h ~ 0x07FFh	WMAC Configuration
++ *
++ * ----------------------------------------------------- */
++
++
++/* ************************************************************
++ * SDIO Bus Specification
++ * ************************************************************ */
++
++/* -----------------------------------------------------
++ * SDIO CMD Address Mapping
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ * I/O bus domain (Host)
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ * SDIO register
++ * ----------------------------------------------------- */
++#define SDIO_REG_HIQ_FREEPG_8188F		0x0020
++#define SDIO_REG_MID_FREEPG_8188F		0x0022
++#define SDIO_REG_LOW_FREEPG_8188F		0x0024
++#define SDIO_REG_PUB_FREEPG_8188F		0x0026
++#define SDIO_REG_EXQ_FREEPG_8188F		0x0028
++#define SDIO_REG_AC_OQT_FREEPG_8188F	0x002A
++#define SDIO_REG_NOAC_OQT_FREEPG_8188F	0x002B
++
++#define SDIO_REG_HCPWM1_8188F			0x0038
++
++/* ****************************************************************************
++ *	8188 Regsiter Bit and Content definition
++ * **************************************************************************** */
++
++/* 2 HSISR
++ * interrupt mask which needs to clear */
++#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
++		HSISR_SPS_OCP_INT |\
++		HSISR_RON_INT |\
++		HSISR_PDNINT |\
++		HSISR_GPIO9_INT)
++
++/* -----------------------------------------------------
++ *
++ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
++ *
++ * ----------------------------------------------------- */
++
++
++/* -----------------------------------------------------
++ *
++ *	0x0200h ~ 0x027Fh	TXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ *
++ *	0x0280h ~ 0x02FFh	RXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++#define BIT_USB_RXDMA_AGG_EN	BIT(31)
++#define RXDMA_AGG_MODE_EN		BIT(1)
++
++#ifdef CONFIG_WOWLAN
++#define RXPKT_RELEASE_POLL		BIT(16)
++#define RXDMA_IDLE				BIT(17)
++#define RW_RELEASE_EN			BIT(18)
++#endif
++
++/* -----------------------------------------------------
++ *
++ *	0x0400h ~ 0x047Fh	Protocol Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* ----------------------------------------------------------------------------
++ * 8188F REG_CCK_CHECK						(offset 0x454)
++ * ---------------------------------------------------------------------------- */
++#define BIT_BCN_PORT_SEL		BIT(5)
++
++/* -----------------------------------------------------
++ *
++ *	0x0500h ~ 0x05FFh	EDCA Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ *
++ *	0x0600h ~ 0x07FFh	WMAC Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* ----------------------------------------------------------------------------
++ * 8195 IMR/ISR bits						(offset 0xB0,  8bits)
++ * ---------------------------------------------------------------------------- */
++#define	IMR_DISABLED_8188F					0
++/* IMR DW0(0x00B0-00B3) Bit 0-31 */
++#define	IMR_TIMER2_8188F					BIT(31)		/* Timeout interrupt 2 */
++#define	IMR_TIMER1_8188F					BIT(30)		/* Timeout interrupt 1	 */
++#define	IMR_PSTIMEOUT_8188F				BIT(29)		/* Power Save Time Out Interrupt */
++#define	IMR_GTINT4_8188F					BIT(28)		/* When GTIMER4 expires, this bit is set to 1	 */
++#define	IMR_GTINT3_8188F					BIT(27)		/* When GTIMER3 expires, this bit is set to 1	 */
++#define	IMR_TXBCN0ERR_8188F				BIT(26)		/* Transmit Beacon0 Error			 */
++#define	IMR_TXBCN0OK_8188F				BIT(25)		/* Transmit Beacon0 OK			 */
++#define	IMR_TSF_BIT32_TOGGLE_8188F		BIT(24)		/* TSF Timer BIT(32) toggle indication interrupt			 */
++#define	IMR_BCNDMAINT0_8188F				BIT(20)		/* Beacon DMA Interrupt 0			 */
++#define	IMR_BCNDERR0_8188F				BIT(16)		/* Beacon Queue DMA OK0			 */
++#define	IMR_HSISR_IND_ON_INT_8188F		BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
++#define	IMR_BCNDMAINT_E_8188F			BIT(14)		/* Beacon DMA Interrupt Extension for Win7			 */
++#define	IMR_ATIMEND_8188F				BIT(12)		/* CTWidnow End or ATIM Window End */
++#define	IMR_C2HCMD_8188F					BIT(10)		/* CPU to Host Command INT Status, Write 1 clear	 */
++#define	IMR_CPWM2_8188F					BIT(9)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
++#define	IMR_CPWM_8188F					BIT(8)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
++#define	IMR_HIGHDOK_8188F				BIT(7)			/* High Queue DMA OK	 */
++#define	IMR_MGNTDOK_8188F				BIT(6)			/* Management Queue DMA OK	 */
++#define	IMR_BKDOK_8188F					BIT(5)			/* AC_BK DMA OK		 */
++#define	IMR_BEDOK_8188F					BIT(4)			/* AC_BE DMA OK	 */
++#define	IMR_VIDOK_8188F					BIT(3)			/* AC_VI DMA OK		 */
++#define	IMR_VODOK_8188F					BIT(2)			/* AC_VO DMA OK	 */
++#define	IMR_RDU_8188F					BIT(1)			/* Rx Descriptor Unavailable	 */
++#define	IMR_ROK_8188F					BIT(0)			/* Receive DMA OK */
++
++/* IMR DW1(0x00B4-00B7) Bit 0-31 */
++#define	IMR_BCNDMAINT7_8188F				BIT(27)		/* Beacon DMA Interrupt 7 */
++#define	IMR_BCNDMAINT6_8188F				BIT(26)		/* Beacon DMA Interrupt 6 */
++#define	IMR_BCNDMAINT5_8188F				BIT(25)		/* Beacon DMA Interrupt 5 */
++#define	IMR_BCNDMAINT4_8188F				BIT(24)		/* Beacon DMA Interrupt 4 */
++#define	IMR_BCNDMAINT3_8188F				BIT(23)		/* Beacon DMA Interrupt 3 */
++#define	IMR_BCNDMAINT2_8188F				BIT(22)		/* Beacon DMA Interrupt 2 */
++#define	IMR_BCNDMAINT1_8188F				BIT(21)		/* Beacon DMA Interrupt 1 */
++#define	IMR_BCNDOK7_8188F					BIT(20)		/* Beacon Queue DMA OK Interrupt 7 */
++#define	IMR_BCNDOK6_8188F					BIT(19)		/* Beacon Queue DMA OK Interrupt 6 */
++#define	IMR_BCNDOK5_8188F					BIT(18)		/* Beacon Queue DMA OK Interrupt 5 */
++#define	IMR_BCNDOK4_8188F					BIT(17)		/* Beacon Queue DMA OK Interrupt 4 */
++#define	IMR_BCNDOK3_8188F					BIT(16)		/* Beacon Queue DMA OK Interrupt 3 */
++#define	IMR_BCNDOK2_8188F					BIT(15)		/* Beacon Queue DMA OK Interrupt 2 */
++#define	IMR_BCNDOK1_8188F					BIT(14)		/* Beacon Queue DMA OK Interrupt 1 */
++#define	IMR_ATIMEND_E_8188F				BIT(13)		/* ATIM Window End Extension for Win7 */
++#define	IMR_TXERR_8188F					BIT(11)		/* Tx Error Flag Interrupt Status, write 1 clear. */
++#define	IMR_RXERR_8188F					BIT(10)		/* Rx Error Flag INT Status, Write 1 clear */
++#define	IMR_TXFOVW_8188F					BIT(9)			/* Transmit FIFO Overflow */
++#define	IMR_RXFOVW_8188F					BIT(8)			/* Receive FIFO Overflow */
++
++#ifdef CONFIG_PCI_HCI
++/* #define IMR_RX_MASK		(IMR_ROK_8188F|IMR_RDU_8188F|IMR_RXFOVW_8188F) */
++#define IMR_TX_MASK			(IMR_VODOK_8188F | IMR_VIDOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F | IMR_MGNTDOK_8188F | IMR_HIGHDOK_8188F)
++
++#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8188F | IMR_TXBCN0OK_8188F | IMR_TXBCN0ERR_8188F | IMR_BCNDERR0_8188F)
++
++#define RT_AC_INT_MASKS	(IMR_VIDOK_8188F | IMR_VODOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F)
++#endif
++
++#endif /* __RTL8188F_SPEC_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_sreset.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_sreset.h
+new file mode 100644
+index 000000000..fe56567e7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_sreset.h
+@@ -0,0 +1,24 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8188F_SRESET_H_
++#define _RTL8188F_SRESET_H_
++
++#include <rtw_sreset.h>
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++extern void rtl8188f_sreset_xmit_status_check(_adapter *padapter);
++extern void rtl8188f_sreset_linked_status_check(_adapter *padapter);
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_xmit.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_xmit.h
+new file mode 100644
+index 000000000..57aaa6225
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8188f_xmit.h
+@@ -0,0 +1,334 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8188F_XMIT_H__
++#define __RTL8188F_XMIT_H__
++
++
++#define MAX_TID (15)
++
++
++#ifndef __INC_HAL8188FDESC_H
++#define __INC_HAL8188FDESC_H
++
++#define RX_STATUS_DESC_SIZE_8188F		24
++#define RX_DRV_INFO_SIZE_UNIT_8188F 8
++
++
++/* DWORD 0 */
++#define SET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
++#define SET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
++#define SET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
++
++#define GET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
++#define GET_RX_STATUS_DESC_CRC32_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
++#define GET_RX_STATUS_DESC_ICV_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
++#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
++#define GET_RX_STATUS_DESC_SECURITY_8188F(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
++#define GET_RX_STATUS_DESC_QOS_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
++#define GET_RX_STATUS_DESC_SHIFT_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
++#define GET_RX_STATUS_DESC_PHY_STATUS_8188F(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
++#define GET_RX_STATUS_DESC_SWDEC_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
++#define GET_RX_STATUS_DESC_LAST_SEG_8188F(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
++#define GET_RX_STATUS_DESC_FIRST_SEG_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
++#define GET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
++#define GET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
++
++/* DWORD 1 */
++#define GET_RX_STATUS_DESC_MACID_8188F(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
++#define GET_RX_STATUS_DESC_TID_8188F(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
++#define GET_RX_STATUS_DESC_AMSDU_8188F(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
++#define GET_RX_STATUS_DESC_RXID_MATCH_8188F(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
++#define GET_RX_STATUS_DESC_PAGGR_8188F(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
++#define GET_RX_STATUS_DESC_A1_FIT_8188F(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
++#define GET_RX_STATUS_DESC_CHKERR_8188F(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
++#define GET_RX_STATUS_DESC_IPVER_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
++#define GET_RX_STATUS_DESC_IS_TCPUDP__8188F(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
++#define GET_RX_STATUS_DESC_CHK_VLD_8188F(__pRxDesc)	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
++#define GET_RX_STATUS_DESC_PAM_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
++#define GET_RX_STATUS_DESC_PWR_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
++#define GET_RX_STATUS_DESC_MORE_DATA_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
++#define GET_RX_STATUS_DESC_MORE_FRAG_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
++#define GET_RX_STATUS_DESC_TYPE_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
++#define GET_RX_STATUS_DESC_MC_8188F(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
++#define GET_RX_STATUS_DESC_BC_8188F(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
++
++/* DWORD 2 */
++#define GET_RX_STATUS_DESC_SEQ_8188F(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
++#define GET_RX_STATUS_DESC_FRAG_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
++#define GET_RX_STATUS_DESC_RX_IS_QOS_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
++#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8188F(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
++#define GET_RX_STATUS_DESC_RPT_SEL_8188F(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
++
++/* DWORD 3 */
++#define GET_RX_STATUS_DESC_RX_RATE_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
++#define GET_RX_STATUS_DESC_HTC_8188F(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
++#define GET_RX_STATUS_DESC_EOSP_8188F(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
++#define GET_RX_STATUS_DESC_BSSID_FIT_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
++#ifdef CONFIG_USB_RX_AGGREGATION
++#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8188F(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
++#endif
++#define GET_RX_STATUS_DESC_PATTERN_MATCH_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
++#define GET_RX_STATUS_DESC_UNICAST_MATCH_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
++#define GET_RX_STATUS_DESC_MAGIC_MATCH_8188F(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
++
++/* DWORD 6 */
++#define GET_RX_STATUS_DESC_SPLCP_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
++#define GET_RX_STATUS_DESC_LDPC_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
++#define GET_RX_STATUS_DESC_STBC_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
++#define GET_RX_STATUS_DESC_BW_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
++
++/* DWORD 5 */
++#define GET_RX_STATUS_DESC_TSFL_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
++
++#define GET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
++#define GET_RX_STATUS_DESC_BUFF_ADDR64_8188F(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
++
++#define SET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
++
++
++/* Dword 0 */
++#define GET_TX_DESC_OWN_8188F(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
++
++#define SET_TX_DESC_PKT_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
++#define SET_TX_DESC_OFFSET_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
++#define SET_TX_DESC_BMC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
++#define SET_TX_DESC_HTC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
++#define SET_TX_DESC_LAST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
++#define SET_TX_DESC_FIRST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
++#define SET_TX_DESC_LINIP_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
++#define SET_TX_DESC_NO_ACM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
++#define SET_TX_DESC_GF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
++#define SET_TX_DESC_OWN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
++
++/* Dword 1 */
++#define SET_TX_DESC_MACID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
++#define SET_TX_DESC_QUEUE_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
++#define SET_TX_DESC_RDG_NAV_EXT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
++#define SET_TX_DESC_LSIG_TXOP_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
++#define SET_TX_DESC_PIFS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
++#define SET_TX_DESC_RATE_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
++#define SET_TX_DESC_EN_DESC_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
++#define SET_TX_DESC_SEC_TYPE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
++#define SET_TX_DESC_PKT_OFFSET_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
++
++
++/* Dword 2 */
++#define SET_TX_DESC_PAID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
++#define SET_TX_DESC_CCA_RTS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
++#define SET_TX_DESC_AGG_ENABLE_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
++#define SET_TX_DESC_RDG_ENABLE_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
++#define SET_TX_DESC_AGG_BREAK_8188F(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
++#define SET_TX_DESC_MORE_FRAG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
++#define SET_TX_DESC_RAW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
++#define SET_TX_DESC_SPE_RPT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
++#define SET_TX_DESC_AMPDU_DENSITY_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
++#define SET_TX_DESC_BT_INT_8188F(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
++#define SET_TX_DESC_GID_8188F(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
++
++
++/* Dword 3 */
++#define SET_TX_DESC_WHEADER_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
++#define SET_TX_DESC_CHK_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
++#define SET_TX_DESC_EARLY_MODE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
++#define SET_TX_DESC_HWSEQ_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
++#define SET_TX_DESC_USE_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
++#define SET_TX_DESC_DISABLE_RTS_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
++#define SET_TX_DESC_DISABLE_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
++#define SET_TX_DESC_CTS2SELF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
++#define SET_TX_DESC_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
++#define SET_TX_DESC_HW_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
++#define SET_TX_DESC_NAV_USE_HDR_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
++#define SET_TX_DESC_USE_MAX_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
++#define SET_TX_DESC_MAX_AGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
++#define SET_TX_DESC_NDPA_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
++#define SET_TX_DESC_AMPDU_MAX_TIME_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
++
++/* Dword 4 */
++#define SET_TX_DESC_TX_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
++#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
++#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
++#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
++#define SET_TX_DESC_DATA_RETRY_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
++#define SET_TX_DESC_RTS_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
++
++
++/* Dword 5 */
++#define SET_TX_DESC_DATA_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
++#define SET_TX_DESC_DATA_SHORT_8188F(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
++#define SET_TX_DESC_DATA_BW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
++#define SET_TX_DESC_DATA_LDPC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
++#define SET_TX_DESC_DATA_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
++#define SET_TX_DESC_CTROL_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
++#define SET_TX_DESC_RTS_SHORT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
++#define SET_TX_DESC_RTS_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
++
++
++/* Dword 6 */
++#define SET_TX_DESC_SW_DEFINE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
++#define SET_TX_DESC_MBSSID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
++#define SET_TX_DESC_ANTSEL_A_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
++#define SET_TX_DESC_ANTSEL_B_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
++#define SET_TX_DESC_ANTSEL_C_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
++#define SET_TX_DESC_ANTSEL_D_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
++
++/* Dword 7 */
++#ifdef CONFIG_PCI_HCI
++#define SET_TX_DESC_TX_BUFFER_SIZE_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++#endif
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
++#define SET_TX_DESC_TX_DESC_CHECKSUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++#endif
++#define SET_TX_DESC_USB_TXAGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
++#ifdef CONFIG_SDIO_HCI
++#define SET_TX_DESC_SDIO_TXSEQ_8188F(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
++#endif
++
++/* Dword 8 */
++#define SET_TX_DESC_HWSEQ_EN_8188F(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
++
++/* Dword 9 */
++#define SET_TX_DESC_SEQ_8188F(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
++
++/* Dword 10 */
++#define SET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
++#define GET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc)	LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
++
++/* Dword 11 */
++#define SET_TX_DESC_NEXT_DESC_ADDRESS_8188F(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
++
++
++#define SET_EARLYMODE_PKTNUM_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
++#define SET_EARLYMODE_LEN0_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
++#define SET_EARLYMODE_LEN1_1_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
++#define SET_EARLYMODE_LEN1_2_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
++#define SET_EARLYMODE_LEN2_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
++#define SET_EARLYMODE_LEN3_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
++
++#endif
++/* -----------------------------------------------------------
++ *
++ *	Rate
++ *
++ * -----------------------------------------------------------
++ * CCK Rates, TxHT = 0 */
++#define DESC8188F_RATE1M				0x00
++#define DESC8188F_RATE2M				0x01
++#define DESC8188F_RATE5_5M				0x02
++#define DESC8188F_RATE11M				0x03
++
++/* OFDM Rates, TxHT = 0 */
++#define DESC8188F_RATE6M				0x04
++#define DESC8188F_RATE9M				0x05
++#define DESC8188F_RATE12M				0x06
++#define DESC8188F_RATE18M				0x07
++#define DESC8188F_RATE24M				0x08
++#define DESC8188F_RATE36M				0x09
++#define DESC8188F_RATE48M				0x0a
++#define DESC8188F_RATE54M				0x0b
++
++/* MCS Rates, TxHT = 1 */
++#define DESC8188F_RATEMCS0				0x0c
++#define DESC8188F_RATEMCS1				0x0d
++#define DESC8188F_RATEMCS2				0x0e
++#define DESC8188F_RATEMCS3				0x0f
++#define DESC8188F_RATEMCS4				0x10
++#define DESC8188F_RATEMCS5				0x11
++#define DESC8188F_RATEMCS6				0x12
++#define DESC8188F_RATEMCS7				0x13
++#define DESC8188F_RATEMCS8				0x14
++#define DESC8188F_RATEMCS9				0x15
++#define DESC8188F_RATEMCS10		0x16
++#define DESC8188F_RATEMCS11		0x17
++#define DESC8188F_RATEMCS12		0x18
++#define DESC8188F_RATEMCS13		0x19
++#define DESC8188F_RATEMCS14		0x1a
++#define DESC8188F_RATEMCS15		0x1b
++#define DESC8188F_RATEVHTSS1MCS0		0x2c
++#define DESC8188F_RATEVHTSS1MCS1		0x2d
++#define DESC8188F_RATEVHTSS1MCS2		0x2e
++#define DESC8188F_RATEVHTSS1MCS3		0x2f
++#define DESC8188F_RATEVHTSS1MCS4		0x30
++#define DESC8188F_RATEVHTSS1MCS5		0x31
++#define DESC8188F_RATEVHTSS1MCS6		0x32
++#define DESC8188F_RATEVHTSS1MCS7		0x33
++#define DESC8188F_RATEVHTSS1MCS8		0x34
++#define DESC8188F_RATEVHTSS1MCS9		0x35
++#define DESC8188F_RATEVHTSS2MCS0		0x36
++#define DESC8188F_RATEVHTSS2MCS1		0x37
++#define DESC8188F_RATEVHTSS2MCS2		0x38
++#define DESC8188F_RATEVHTSS2MCS3		0x39
++#define DESC8188F_RATEVHTSS2MCS4		0x3a
++#define DESC8188F_RATEVHTSS2MCS5		0x3b
++#define DESC8188F_RATEVHTSS2MCS6		0x3c
++#define DESC8188F_RATEVHTSS2MCS7		0x3d
++#define DESC8188F_RATEVHTSS2MCS8		0x3e
++#define DESC8188F_RATEVHTSS2MCS9		0x3f
++
++
++#define	RX_HAL_IS_CCK_RATE_8188F(pDesc)\
++	(GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE1M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE2M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE5_5M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE11M)
++
++
++void rtl8188f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
++void rtl8188f_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
++void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++s32 rtl8188fs_init_xmit_priv(PADAPTER padapter);
++void rtl8188fs_free_xmit_priv(PADAPTER padapter);
++s32 rtl8188fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++s32 rtl8188fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++s32	rtl8188fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++s32 rtl8188fs_xmit_buf_handler(PADAPTER padapter);
++thread_return rtl8188fs_xmit_thread(thread_context context);
++#define hal_xmit_handler rtl8188fs_xmit_buf_handler
++#endif
++
++#ifdef CONFIG_USB_HCI
++#ifdef CONFIG_XMIT_THREAD_MODE
++s32 rtl8188fu_xmit_buf_handler(PADAPTER padapter);
++#define hal_xmit_handler rtl8188fu_xmit_buf_handler
++#endif
++
++s32 rtl8188fu_init_xmit_priv(PADAPTER padapter);
++void rtl8188fu_free_xmit_priv(PADAPTER padapter);
++s32 rtl8188fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++s32 rtl8188fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++s32	 rtl8188fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++/* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */
++void rtl8188fu_xmit_tasklet(void *priv);
++s32 rtl8188fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++s32 rtl8188fe_init_xmit_priv(PADAPTER padapter);
++void rtl8188fe_free_xmit_priv(PADAPTER padapter);
++struct xmit_buf *rtl8188fe_dequeue_xmitbuf(struct rtw_tx_ring *ring);
++void	rtl8188fe_xmitframe_resume(_adapter *padapter);
++s32 rtl8188fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++s32 rtl8188fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++s32	rtl8188fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++void rtl8188fe_xmit_tasklet(void *priv);
++#endif
++
++u8	BWMapping_8188F(PADAPTER Adapter, struct pkt_attrib *pattrib);
++u8	SCMapping_8188F(PADAPTER Adapter, struct pkt_attrib	*pattrib);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_cmd.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_cmd.h
+new file mode 100644
+index 000000000..5efdf997a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_cmd.h
+@@ -0,0 +1,147 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2012 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8192E_CMD_H__
++#define __RTL8192E_CMD_H__
++
++typedef enum _RTL8192E_H2C_CMD {
++	H2C_8192E_RSVDPAGE	= 0x00,
++	H2C_8192E_MSRRPT	= 0x01,
++	H2C_8192E_SCAN		= 0x02,
++	H2C_8192E_KEEP_ALIVE_CTRL = 0x03,
++	H2C_8192E_DISCONNECT_DECISION = 0x04,
++	H2C_8192E_INIT_OFFLOAD = 0x06,
++	H2C_8192E_AP_OFFLOAD = 0x08,
++	H2C_8192E_BCN_RSVDPAGE = 0x09,
++	H2C_8192E_PROBERSP_RSVDPAGE = 0x0a,
++
++	H2C_8192E_AP_WOW_GPIO_CTRL = 0x13,
++
++	H2C_8192E_SETPWRMODE = 0x20,
++	H2C_8192E_PS_TUNING_PARA = 0x21,
++	H2C_8192E_PS_TUNING_PARA2 = 0x22,
++	H2C_8192E_PS_LPS_PARA = 0x23,
++	H2C_8192E_P2P_PS_OFFLOAD = 0x24,
++	H2C_8192E_SAP_PS = 0x26,
++	H2C_8192E_RA_MASK = 0x40,
++	H2C_8192E_RSSI_REPORT = 0x42,
++	H2C_8192E_RA_PARA_ADJUST = 0x46,
++
++	H2C_8192E_WO_WLAN = 0x80,
++	H2C_8192E_REMOTE_WAKE_CTRL = 0x81,
++	H2C_8192E_AOAC_GLOBAL_INFO = 0x82,
++	H2C_8192E_AOAC_RSVDPAGE = 0x83,
++
++	/* Not defined in new 88E H2C CMD Format */
++	H2C_8192E_SELECTIVE_SUSPEND_ROF_CMD,
++	H2C_8192E_P2P_PS_MODE,
++	H2C_8192E_PSD_RESULT,
++	MAX_8192E_H2CCMD
++} RTL8192E_H2C_CMD;
++
++struct cmd_msg_parm {
++	u8 eid; /* element id */
++	u8 sz; /* sz */
++	u8 buf[6];
++};
++
++enum {
++	PWRS
++};
++
++typedef struct _SETPWRMODE_PARM {
++	u8 Mode;/* 0:Active,1:LPS,2:WMMPS */
++	/* u8 RLBM:4; */ /* 0:Min,1:Max,2: User define */
++	u8 SmartPS_RLBM;/* LPS=0:PS_Poll,1:PS_Poll,2:NullData,WMM=0:PS_Poll,1:NullData */
++	u8 AwakeInterval;	/* unit: beacon interval */
++	u8 bAllQueueUAPSD;
++	u8 PwrState;/* AllON(0x0c),RFON(0x04),RFOFF(0x00) */
++} SETPWRMODE_PARM, *PSETPWRMODE_PARM;
++
++struct H2C_SS_RFOFF_PARAM {
++	u8 ROFOn; /* 1: on, 0:off */
++	u16 gpio_period; /* unit: 1024 us */
++} __attribute__((packed));
++
++
++typedef struct JOINBSSRPT_PARM_92E {
++	u8 OpMode;	/* RT_MEDIA_STATUS */
++#ifdef CONFIG_WOWLAN
++	u8 MacID;       /* MACID */
++#endif /* CONFIG_WOWLAN */
++} JOINBSSRPT_PARM_92E, *PJOINBSSRPT_PARM_92E;
++
++/* move to hal_com_h2c.h
++typedef struct _RSVDPAGE_LOC_92E {
++	u8 LocProbeRsp;
++	u8 LocPsPoll;
++	u8 LocNullData;
++	u8 LocQosNull;
++	u8 LocBTQosNull;
++} RSVDPAGE_LOC_92E, *PRSVDPAGE_LOC_92E;
++*/
++
++
++/* _SETPWRMODE_PARM */
++#define SET_8192E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8192E_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
++#define SET_8192E_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
++#define SET_8192E_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8192E_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8192E_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
++#define SET_8192E_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++#define GET_8192E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)						LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
++
++/* _P2P_PS_OFFLOAD */
++#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_CTWINDOW_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
++#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_NOA0_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
++#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_NOA1_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
++#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
++
++
++/* host message to firmware cmd */
++void rtl8192e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
++void rtl8192e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
++s32 FillH2CCmd_8192E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
++u8 GetTxBufferRsvdPageNum8192E(_adapter *padapter, bool wowlan);
++/* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */
++s32 c2h_handler_8192e(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
++#ifdef CONFIG_BT_COEXIST
++	void rtl8192e_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
++#endif /* CONFIG_BT_COEXIST */
++#ifdef CONFIG_P2P_PS
++	void rtl8192e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
++#endif /* CONFIG_P2P */
++
++#ifdef CONFIG_TDLS
++	#ifdef CONFIG_TDLS_CH_SW
++		void rtl8192e_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
++	#endif
++#endif
++
++/* / TX Feedback Content */
++#define	USEC_UNIT_FOR_8192E_C2H_TX_RPT_QUEUE_TIME			256
++
++#define	GET_8192E_C2H_TX_RPT_QUEUE_SELECT(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 0, 5)
++#define	GET_8192E_C2H_TX_RPT_PKT_BROCAST(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 5, 1)
++#define	GET_8192E_C2H_TX_RPT_LIFE_TIME_OVER(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
++#define	GET_8192E_C2H_TX_RPT_RETRY_OVER(_Header)				LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
++#define	GET_8192E_C2H_TX_RPT_MAC_ID(_Header)					LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
++#define	GET_8192E_C2H_TX_RPT_DATA_RETRY_CNT(_Header)		LE_BITS_TO_1BYTE((_Header + 2), 0, 6)
++#define	GET_8192E_C2H_TX_RPT_QUEUE_TIME(_Header)				LE_BITS_TO_2BYTE((_Header + 3), 0, 16)	/* In unit of 256 microseconds. */
++#define	GET_8192E_C2H_TX_RPT_FINAL_DATA_RATE(_Header)		LE_BITS_TO_1BYTE((_Header + 5), 0, 8)
++
++#endif /* __RTL8192E_CMD_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_dm.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_dm.h
+new file mode 100644
+index 000000000..0a65a1be3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_dm.h
+@@ -0,0 +1,28 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2012 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8192E_DM_H__
++#define __RTL8192E_DM_H__
++
++
++void rtl8192e_init_dm_priv(PADAPTER Adapter);
++void rtl8192e_deinit_dm_priv(PADAPTER Adapter);
++void rtl8192e_InitHalDm(PADAPTER Adapter);
++void rtl8192e_HalDmWatchDog(PADAPTER Adapter);
++
++/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */
++
++/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_hal.h
+new file mode 100644
+index 000000000..417147dab
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_hal.h
+@@ -0,0 +1,330 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2012 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8192E_HAL_H__
++#define __RTL8192E_HAL_H__
++
++/* #include "hal_com.h" */
++
++#include "hal_data.h"
++
++/* include HAL Related header after HAL Related compiling flags */
++#include "rtl8192e_spec.h"
++#include "rtl8192e_rf.h"
++#include "rtl8192e_dm.h"
++#include "rtl8192e_recv.h"
++#include "rtl8192e_xmit.h"
++#include "rtl8192e_cmd.h"
++#include "rtl8192e_led.h"
++#include "Hal8192EPwrSeq.h"
++#include "Hal8192EPhyReg.h"
++#include "Hal8192EPhyCfg.h"
++
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++	#include "rtl8192e_sreset.h"
++#endif
++
++/* ---------------------------------------------------------------------
++ *		RTL8192E Power Configuration CMDs for PCIe interface
++ * --------------------------------------------------------------------- */
++#define Rtl8192E_NIC_PWR_ON_FLOW				rtl8192E_power_on_flow
++#define Rtl8192E_NIC_RF_OFF_FLOW				rtl8192E_radio_off_flow
++#define Rtl8192E_NIC_DISABLE_FLOW				rtl8192E_card_disable_flow
++#define Rtl8192E_NIC_ENABLE_FLOW				rtl8192E_card_enable_flow
++#define Rtl8192E_NIC_SUSPEND_FLOW				rtl8192E_suspend_flow
++#define Rtl8192E_NIC_RESUME_FLOW				rtl8192E_resume_flow
++#define Rtl8192E_NIC_PDN_FLOW					rtl8192E_hwpdn_flow
++#define Rtl8192E_NIC_LPS_ENTER_FLOW			rtl8192E_enter_lps_flow
++#define Rtl8192E_NIC_LPS_LEAVE_FLOW			rtl8192E_leave_lps_flow
++
++
++#if 1 /* download firmware related data structure */
++#define FW_SIZE_8192E			0x8000 /* Compatible with RTL8192e Maximal RAM code size 32k */
++#define FW_START_ADDRESS		0x1000
++#define FW_END_ADDRESS			0x5FFF
++
++
++#define IS_FW_HEADER_EXIST_8192E(_pFwHdr)	((GET_FIRMWARE_HDR_SIGNATURE_8192E(_pFwHdr) & 0xFFF0) == 0x92E0)
++
++
++
++typedef struct _RT_FIRMWARE_8192E {
++	FIRMWARE_SOURCE	eFWSource;
++#ifdef CONFIG_EMBEDDED_FWIMG
++	u8			*szFwBuffer;
++#else
++	u8			szFwBuffer[FW_SIZE_8192E];
++#endif
++	u32			ulFwLength;
++} RT_FIRMWARE_8192E, *PRT_FIRMWARE_8192E;
++
++/*
++ * This structure must be cared byte-ordering
++ *
++ * Added by tynli. 2009.12.04. */
++
++/* *****************************************************
++ *					Firmware Header(8-byte alinment required)
++ * *****************************************************
++ * --- LONG WORD 0 ---- */
++#define GET_FIRMWARE_HDR_SIGNATURE_8192E(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 0, 16) /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
++#define GET_FIRMWARE_HDR_CATEGORY_8192E(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */
++#define GET_FIRMWARE_HDR_FUNCTION_8192E(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
++#define GET_FIRMWARE_HDR_VERSION_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */
++#define GET_FIRMWARE_HDR_SUB_VER_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */
++#define GET_FIRMWARE_HDR_RSVD1_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8)
++
++/* --- LONG WORD 1 ---- */
++#define GET_FIRMWARE_HDR_MONTH_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 0, 8) /* Release time Month field */
++#define GET_FIRMWARE_HDR_DATE_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 8, 8) /* Release time Date field */
++#define GET_FIRMWARE_HDR_HOUR_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 16, 8)/* Release time Hour field */
++#define GET_FIRMWARE_HDR_MINUTE_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 24, 8)/* Release time Minute field */
++#define GET_FIRMWARE_HDR_ROMCODE_SIZE_8192E(__FwHdr)	LE_BITS_TO_4BYTE(__FwHdr+12, 0, 16)/* The size of RAM code */
++#define GET_FIRMWARE_HDR_RSVD2_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+12, 16, 16)
++
++/* --- LONG WORD 2 ---- */
++#define GET_FIRMWARE_HDR_SVN_IDX_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+16, 0, 32)/* The SVN entry index */
++#define GET_FIRMWARE_HDR_RSVD3_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+20, 0, 32)
++
++/* --- LONG WORD 3 ---- */
++#define GET_FIRMWARE_HDR_RSVD4_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+24, 0, 32)
++#define GET_FIRMWARE_HDR_RSVD5_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32)
++
++#endif /* download firmware related data structure */
++
++#define DRIVER_EARLY_INT_TIME_8192E		0x05
++#define BCN_DMA_ATIME_INT_TIME_8192E		0x02
++#define RX_DMA_SIZE_8192E					0x4000	/* 16K*/
++
++#ifdef CONFIG_WOWLAN
++	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
++#else
++	#define RESV_FMWF	0
++#endif
++
++#ifdef CONFIG_FW_C2H_DEBUG
++	#define RX_DMA_RESERVED_SIZE_8192E	0x100	/* 256B, reserved for c2h debug message*/
++#else
++	#define RX_DMA_RESERVED_SIZE_8192E	0x40	/* 64B, reserved for c2h event(16bytes) or ccx(8 Bytes)*/
++#endif
++#define MAX_RX_DMA_BUFFER_SIZE_8192E		(RX_DMA_SIZE_8192E-RX_DMA_RESERVED_SIZE_8192E)	/*RX 16K*/
++
++
++#define PAGE_SIZE_TX_92E	PAGE_SIZE_256
++
++/* For General Reserved Page Number(Beacon Queue is reserved page)
++ * if (CONFIG_2BCN_EN) Beacon:4, PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1
++ * Beacon: MAX_BEACON_LEN / PAGE_SIZE_TX_92E
++ * PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1,CTS-2-SELF / LTE QoS Null*/
++
++#define RSVD_PAGE_NUM_8192E		(MAX_BEACON_LEN / PAGE_SIZE_TX_92E + 6) /*0x08*/
++/* For WoWLan , more reserved page
++ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6
++ * NS offload: 2 NDP info: 1
++ */
++#ifdef CONFIG_WOWLAN
++	#define WOWLAN_PAGE_NUM_8192E	0x0b
++#else
++	#define WOWLAN_PAGE_NUM_8192E	0x00
++#endif
++
++#ifdef CONFIG_PNO_SUPPORT
++	#undef WOWLAN_PAGE_NUM_8192E
++	#define WOWLAN_PAGE_NUM_8192E	0x0d
++#endif
++
++/* Note:
++Tx FIFO Size : 64KB
++Tx page Size : 256B
++Total page numbers : 256(0x100)
++*/
++
++#define	TOTAL_RSVD_PAGE_NUMBER_8192E	(RSVD_PAGE_NUM_8192E + WOWLAN_PAGE_NUM_8192E)
++
++#define	TOTAL_PAGE_NUMBER_8192E	(0x100)
++#define	TX_TOTAL_PAGE_NUMBER_8192E	(TOTAL_PAGE_NUMBER_8192E - TOTAL_RSVD_PAGE_NUMBER_8192E)
++
++#define	TX_PAGE_BOUNDARY_8192E	(TX_TOTAL_PAGE_NUMBER_8192E) /* beacon header start address */
++
++
++#define RSVD_PKT_LEN_92E	(TOTAL_RSVD_PAGE_NUMBER_8192E * PAGE_SIZE_TX_92E)
++
++#define TX_PAGE_LOAD_FW_BOUNDARY_8192E		0x47 /* 0xA5 */
++#define TX_PAGE_BOUNDARY_WOWLAN_8192E		0xE0
++
++/* For Normal Chip Setting
++ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_92C */
++
++#define NORMAL_PAGE_NUM_HPQ_8192E			0x10
++#define NORMAL_PAGE_NUM_LPQ_8192E			0x10
++#define NORMAL_PAGE_NUM_NPQ_8192E			0x10
++#define NORMAL_PAGE_NUM_EPQ_8192E			0x00
++
++
++/* Note: For WMM Normal Chip Setting ,modify later */
++#define WMM_NORMAL_PAGE_NUM_HPQ_8192E		NORMAL_PAGE_NUM_HPQ_8192E
++#define WMM_NORMAL_PAGE_NUM_LPQ_8192E		NORMAL_PAGE_NUM_LPQ_8192E
++#define WMM_NORMAL_PAGE_NUM_NPQ_8192E		NORMAL_PAGE_NUM_NPQ_8192E
++
++
++/* -------------------------------------------------------------------------
++ *	Chip specific
++ * ------------------------------------------------------------------------- */
++
++/* pic buffer descriptor */
++#define RTL8192EE_SEG_NUM			TX_BUFFER_SEG_NUM
++#define TX_DESC_NUM_92E			128
++#define RX_DESC_NUM_92E			128
++
++/* -------------------------------------------------------------------------
++ *	Channel Plan
++ * ------------------------------------------------------------------------- */
++
++#define		HWSET_MAX_SIZE_8192E			512
++
++#define		EFUSE_REAL_CONTENT_LEN_8192E	512
++
++#define		EFUSE_MAP_LEN_8192E			512
++#define		EFUSE_MAX_SECTION_8192E		64
++#define		EFUSE_MAX_WORD_UNIT_8192E		4
++#define		EFUSE_IC_ID_OFFSET_8192E		506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
++#define		AVAILABLE_EFUSE_ADDR_8192E(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8192E)
++/*
++ * <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
++ * 9bytes + 1byt + 5bytes and pre 1byte.
++ * For worst case:
++ * | 1byte|----8bytes----|1byte|--5bytes--|
++ * |         |            Reserved(14bytes)	      |
++ *   */
++#define		EFUSE_OOB_PROTECT_BYTES_8192E 		15	/* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
++
++
++
++/* ********************************************************
++ *			EFUSE for BT definition
++ * ******************************************************** */
++#define		EFUSE_BT_REAL_BANK_CONTENT_LEN_8192E	512
++#define		EFUSE_BT_REAL_CONTENT_LEN_8192E			1024	/* 512*2 */
++#define		EFUSE_BT_MAP_LEN_8192E					1024	/* 1k bytes */
++#define		EFUSE_BT_MAX_SECTION_8192E				128		/* 1024/8 */
++
++#define		EFUSE_PROTECT_BYTES_BANK_8192E			16
++#define		EFUSE_MAX_BANK_8192E					3
++/* *********************************************************** */
++
++#define INCLUDE_MULTI_FUNC_BT(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
++#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
++
++/* #define IS_MULTI_FUNC_CHIP(_Adapter)	(((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */
++
++/* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */
++
++/* rtl8812_hal_init.c */
++void	_8051Reset8192E(PADAPTER padapter);
++s32	FirmwareDownload8192E(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw);
++void	InitializeFirmwareVars8192E(PADAPTER padapter);
++
++s32	InitLLTTable8192E(PADAPTER padapter, u8 txpktbuf_bndy);
++
++/* EFuse */
++u8	GetEEPROMSize8192E(PADAPTER padapter);
++void	hal_InitPGData_8192E(PADAPTER padapter, u8 *PROMContent);
++void	Hal_EfuseParseIDCode8192E(PADAPTER padapter, u8 *hwinfo);
++void	Hal_ReadPROMVersion8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void	Hal_ReadPowerSavingMode8192E(PADAPTER padapter, u8	*hwinfo, BOOLEAN	AutoLoadFail);
++void	Hal_ReadTxPowerInfo8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
++void	Hal_ReadBoardType8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void	Hal_ReadThermalMeter_8192E(PADAPTER	Adapter, u8 *PROMContent, BOOLEAN	AutoloadFail);
++void	Hal_ReadChannelPlan8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void	Hal_EfuseParseXtal_8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void	Hal_ReadAntennaDiversity8192E(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
++void	Hal_ReadPAType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
++void	Hal_ReadAmplifierType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
++void	Hal_ReadRFEType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
++void	Hal_EfuseParseBTCoexistInfo8192E(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void	Hal_EfuseParseKFreeData_8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++
++u8 Hal_CrystalAFEAdjust(_adapter *Adapter);
++
++BOOLEAN HalDetectPwrDownMode8192E(PADAPTER Adapter);
++
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++	void Hal_DetectWoWMode(PADAPTER pAdapter);
++#endif /* CONFIG_WOWLAN */
++
++/***********************************************************/
++/* RTL8192E-MAC Setting */
++void _InitQueueReservedPage_8192E(PADAPTER Adapter);
++void _InitQueuePriority_8192E(PADAPTER Adapter);
++void _InitTxBufferBoundary_8192E(PADAPTER Adapter, u8 txpktbuf_bndy);
++void _InitPageBoundary_8192E(PADAPTER Adapter);
++/* void _InitTransferPageSize_8192E(PADAPTER Adapter); */
++void _InitDriverInfoSize_8192E(PADAPTER Adapter, u8 drvInfoSize);
++void _InitRDGSetting_8192E(PADAPTER Adapter);
++void _InitID_8192E(PADAPTER Adapter);
++void _InitNetworkType_8192E(PADAPTER Adapter);
++void _InitWMACSetting_8192E(PADAPTER Adapter);
++void _InitAdaptiveCtrl_8192E(PADAPTER Adapter);
++void _InitEDCA_8192E(PADAPTER Adapter);
++void _InitRetryFunction_8192E(PADAPTER Adapter);
++void _BBTurnOnBlock_8192E(PADAPTER Adapter);
++void _InitBeaconParameters_8192E(PADAPTER Adapter);
++void _InitBeaconMaxError_8192E(
++		PADAPTER	Adapter,
++		BOOLEAN		InfraMode
++);
++void SetBeaconRelatedRegisters8192E(PADAPTER padapter);
++void hal_ReadRFType_8192E(PADAPTER	Adapter);
++/* RTL8192E-MAC Setting
++ ***********************************************************/
++
++u8 SetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val);
++void GetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val);
++u8
++SetHalDefVar8192E(
++		PADAPTER				Adapter,
++		HAL_DEF_VARIABLE		eVariable,
++		void						*pValue
++);
++u8
++GetHalDefVar8192E(
++		PADAPTER				Adapter,
++		HAL_DEF_VARIABLE		eVariable,
++		void						*pValue
++);
++
++void rtl8192e_set_hal_ops(struct hal_ops *pHalFunc);
++void init_hal_spec_8192e(_adapter *adapter);
++void rtl8192e_init_default_value(_adapter *padapter);
++
++void rtl8192e_start_thread(_adapter *padapter);
++void rtl8192e_stop_thread(_adapter *padapter);
++
++#ifdef CONFIG_PCI_HCI
++	BOOLEAN	InterruptRecognized8192EE(PADAPTER Adapter);
++	u16	get_txbd_rw_reg(u16 ff_hwaddr);
++#endif
++
++#ifdef CONFIG_SDIO_HCI
++	#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
++		void _init_available_page_threshold(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ);
++	#endif
++#endif
++
++#ifdef CONFIG_BT_COEXIST
++	void rtl8192e_combo_card_WifiOnlyHwInit(PADAPTER Adapter);
++#endif
++
++#endif /* __RTL8192E_HAL_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_led.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_led.h
+new file mode 100644
+index 000000000..3d795c405
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_led.h
+@@ -0,0 +1,36 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2012 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8192E_LED_H__
++#define __RTL8192E_LED_H__
++
++#ifdef CONFIG_RTW_SW_LED
++/* ********************************************************************************
++ * Interface to manipulate LED objects.
++ * ******************************************************************************** */
++#ifdef CONFIG_USB_HCI
++	void rtl8192eu_InitSwLeds(PADAPTER padapter);
++	void rtl8192eu_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_PCI_HCI
++	void rtl8192ee_InitSwLeds(PADAPTER padapter);
++	void rtl8192ee_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_SDIO_HCI
++	void rtl8192es_InitSwLeds(PADAPTER padapter);
++	void rtl8192es_DeInitSwLeds(PADAPTER padapter);
++#endif
++
++#endif
++#endif/*CONFIG_RTW_SW_LED*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_recv.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_recv.h
+new file mode 100644
+index 000000000..c19a98080
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_recv.h
+@@ -0,0 +1,175 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2012 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8192E_RECV_H__
++#define __RTL8192E_RECV_H__
++
++#if defined(CONFIG_USB_HCI)
++
++	#ifndef MAX_RECVBUF_SZ
++		#ifdef CONFIG_MINIMAL_MEMORY_USAGE
++			#define MAX_RECVBUF_SZ (4000) /* about 4K */
++		#else
++			#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
++				#define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/
++			#elif defined(CONFIG_PLATFORM_HISILICON)
++				#define MAX_RECVBUF_SZ (16384) /* 16k */
++			#else
++				#define MAX_RECVBUF_SZ (32768) /* 32k */
++			#endif
++			/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
++			/* #define MAX_RECVBUF_SZ (10240)  */ /* 10K */
++			/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
++			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k		 */
++			#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
++				#undef MAX_RECVBUF_SZ
++				#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
++			#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
++		#endif
++	#endif /* !MAX_RECVBUF_SZ */
++
++#elif defined(CONFIG_PCI_HCI)
++	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
++	/*	#define MAX_RECVBUF_SZ (9100) */
++	/* #else */
++	#define MAX_RECVBUF_SZ (4000) /* about 4K
++	* #endif */
++
++
++#elif defined(CONFIG_SDIO_HCI)
++
++	#define MAX_RECVBUF_SZ (16384)
++
++#endif
++
++
++/* Rx smooth factor */
++#define Rx_Smooth_Factor (20)
++
++/* *************
++ * [1] Rx Buffer Descriptor (for PCIE) buffer descriptor architecture
++ * DWORD 0 */
++#define SET_RX_BUFFER_DESC_DATA_LENGTH_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
++#define SET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
++#define SET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
++#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
++
++#define GET_RX_BUFFER_DESC_OWN_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
++#define GET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
++#define GET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
++#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
++
++
++/* DWORD 1 */
++#define SET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
++#define GET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 32)
++
++/* DWORD 2 */
++#define SET_RX_BUFFER_PHYSICAL_HIGH_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
++
++/* *************
++ * [2] Rx Descriptor
++ * DWORD 0 */
++#define GET_RX_STATUS_DESC_PKT_LEN_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
++#define GET_RX_STATUS_DESC_CRC32_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
++#define GET_RX_STATUS_DESC_ICVERR_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
++#define GET_RX_STATUS_DESC_DRVINFO_SIZE_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
++#define GET_RX_STATUS_DESC_SECURITY_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
++#define GET_RX_STATUS_DESC_QOS_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
++#define GET_RX_STATUS_DESC_SHIFT_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
++#define GET_RX_STATUS_DESC_PHY_STATUS_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
++#define GET_RX_STATUS_DESC_SWDEC_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
++#define GET_RX_STATUS_DESC_EOR_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
++#define GET_RX_STATUS_DESC_OWN_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
++
++
++#define SET_RX_STATUS_DESC_PKT_LEN_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
++#define SET_RX_STATUS_DESC_EOR_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
++#define SET_RX_STATUS_DESC_OWN_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
++
++/* DWORD 1 */
++#define GET_RX_STATUS_DESC_MACID_92E(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
++#define GET_RX_STATUS_DESC_TID_92E(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
++#define GET_RX_STATUS_DESC_MACID_VLD_92E(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 12, 1)
++#define GET_RX_STATUS_DESC_AMSDU_92E(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
++#define GET_RX_STATUS_DESC_RXID_MATCH_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
++#define GET_RX_STATUS_DESC_PAGGR_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 15, 1)
++#define GET_RX_STATUS_DESC_A1_FITS_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 16, 4)
++#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHKERR_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 20, 1)
++#define GET_RX_STATUS_DESC_TCPOFFLOAD_IPVER_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 21, 1)
++#define GET_RX_STATUS_DESC_TCPOFFLOAD_IS_TCPUDP_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 22, 1)
++#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHK_VLD_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 23, 1)
++#define GET_RX_STATUS_DESC_PAM_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 24, 1)
++#define GET_RX_STATUS_DESC_PWR_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 25, 1)
++#define GET_RX_STATUS_DESC_MORE_DATA_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 26, 1)
++#define GET_RX_STATUS_DESC_MORE_FRAG_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 27, 1)
++#define GET_RX_STATUS_DESC_TYPE_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 28, 2)
++#define GET_RX_STATUS_DESC_MC_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 30, 1)
++#define GET_RX_STATUS_DESC_BC_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 31, 1)
++
++/* DWORD 2 */
++#define GET_RX_STATUS_DESC_SEQ_92E(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
++#define GET_RX_STATUS_DESC_FRAG_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
++#define GET_RX_STATUS_DESC_RX_IS_QOS_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
++
++#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
++#define GET_RX_STATUS_DESC_HWRSVD_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 24, 4)
++#define GET_RX_STATUS_DESC_FCS_OK_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
++#define GET_RX_STATUS_DESC_RPT_SEL_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
++
++/* DWORD 3 */
++#define GET_RX_STATUS_DESC_RX_RATE_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
++#define GET_RX_STATUS_DESC_HTC_92E(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
++#define GET_RX_STATUS_DESC_EOSP_92E(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
++#define GET_RX_STATUS_DESC_BSSID_FIT_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
++#define GET_RX_STATUS_DESC_DMA_AGG_NUM_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
++
++#define GET_RX_STATUS_DESC_PATTERN_MATCH_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
++#define GET_RX_STATUS_DESC_UNICAST_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
++#define GET_RX_STATUS_DESC_MAGIC_WAKE_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
++
++/* DWORD 6 */
++#define GET_RX_STATUS_DESC_SPLCP_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
++#define GET_RX_STATUS_DESC_LDPC_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
++#define GET_RX_STATUS_DESC_STBC_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
++#define GET_RX_STATUS_DESC_BW_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
++
++
++/* DWORD 5 */
++#define GET_RX_STATUS_DESC_TSFL_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
++
++#define GET_RX_STATUS_DESC_BUFF_ADDR_92E(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
++#define GET_RX_STATUS_DESC_BUFF_ADDR64_92E(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
++
++
++#ifdef CONFIG_SDIO_HCI
++	s32 rtl8192es_init_recv_priv(PADAPTER padapter);
++	void rtl8192es_free_recv_priv(PADAPTER padapter);
++	s32 rtl8192es_recv_hdl(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_USB_HCI
++	void rtl8192eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
++	s32 rtl8192eu_init_recv_priv(PADAPTER padapter);
++	void rtl8192eu_free_recv_priv(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	s32 rtl8192ee_init_recv_priv(PADAPTER padapter);
++	void rtl8192ee_free_recv_priv(PADAPTER padapter);
++#endif
++
++void rtl8192e_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
++
++#endif /* __RTL8192E_RECV_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_rf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_rf.h
+new file mode 100644
+index 000000000..77dca747e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_rf.h
+@@ -0,0 +1,28 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2012 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8192E_RF_H__
++#define __RTL8192E_RF_H__
++
++void
++PHY_RF6052SetBandwidth8192E(
++		PADAPTER				Adapter,
++		enum channel_width		Bandwidth);
++
++
++int
++PHY_RF6052_Config_8192E(
++		PADAPTER	Adapter);
++
++#endif/* __RTL8192E_RF_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_spec.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_spec.h
+new file mode 100644
+index 000000000..c9b2b41e6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_spec.h
+@@ -0,0 +1,313 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2012 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8192E_SPEC_H__
++#define __RTL8192E_SPEC_H__
++
++#include <drv_conf.h>
++
++#define HAL_NAV_UPPER_UNIT_8192E		128		/* micro-second */
++
++/* ************************************************************
++ * 8192E Regsiter offset definition
++ * ************************************************************ */
++
++/* ************************************************************
++ *
++ * ************************************************************ */
++
++/* -----------------------------------------------------
++ *
++ *	0x0000h ~ 0x00FFh	System Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_SYS_SWR_CTRL1_8192E		0x0010	/* 1 Byte        */
++#define REG_SYS_SWR_CTRL2_8192E		0x0014	/* 1 Byte      */
++#define REG_AFE_CTRL1_8192E			0x0024
++#define REG_AFE_CTRL2_8192E			0x0028
++#define REG_AFE_CTRL3_8192E			0x002c
++
++#define REG_PAD_CTRL1_8192E			0x0064
++#define REG_SDIO_CTRL_8192E			0x0070
++#define REG_OPT_CTRL_8192E				0x0074
++#define REG_RF_B_CTRL_8192E			0x0076
++#define REG_AFE_CTRL4_8192E			0x0078
++#define REG_LDO_SWR_CTRL				0x007C
++#define REG_FW_DRV_MSG_8192E			0x0088
++#define REG_HMEBOX_E2_E3_8192E		0x008C
++#define REG_HIMR0_8192E				0x00B0
++#define REG_HISR0_8192E					0x00B4
++#define REG_HIMR1_8192E					0x00B8
++#define REG_HISR1_8192E					0x00BC
++
++#define REG_SYS_CFG1_8192E				0x00F0
++#define REG_SYS_CFG2_8192E				0x00FC
++/* -----------------------------------------------------
++ *
++ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_PKTBUF_DBG_ADDR			(REG_PKTBUF_DBG_CTRL)
++#define REG_RXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+2)
++#define REG_TXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+3)
++#define REG_WOWLAN_WAKE_REASON		REG_MCUTST_WOWLAN
++
++#define REG_RSVD3_8192E					0x0168
++#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
++#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
++#define REG_C2HEVT_CMD_LEN_88XX		0x01AE
++
++#define REG_HMEBOX_EXT0_8192E			0x01F0
++#define REG_HMEBOX_EXT1_8192E			0x01F4
++#define REG_HMEBOX_EXT2_8192E			0x01F8
++#define REG_HMEBOX_EXT3_8192E			0x01FC
++
++/* -----------------------------------------------------
++ *
++ *	0x0200h ~ 0x027Fh	TXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_DWBCN0_CTRL             0x0208
++#define REG_DWBCN1_CTRL             0x0228
++
++/* -----------------------------------------------------
++ *
++ *	0x0280h ~ 0x02FFh	RXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_RXDMA_8192E					0x0290
++#define REG_EARLY_MODE_CONTROL_8192E		0x02BC
++
++#define REG_RSVD5_8192E					0x02F0
++#define REG_RSVD6_8192E					0x02F4
++#define REG_RSVD7_8192E					0x02F8
++#define REG_RSVD8_8192E					0x02FC
++
++/* -----------------------------------------------------
++ *
++ *	0x0300h ~ 0x03FFh	PCIe
++ *
++ * ----------------------------------------------------- */
++#define	REG_PCIE_CTRL_REG_8192E			0x0300
++#define	REG_INT_MIG_8192E					0x0304	/* Interrupt Migration */
++#define	REG_BCNQ_TXBD_DESA_8192E		0x0308	/* TX Beacon Descriptor Address */
++#define	REG_MGQ_TXBD_DESA_8192E			0x0310	/* TX Manage Queue Descriptor Address */
++#define	REG_VOQ_TXBD_DESA_8192E			0x0318	/* TX VO Queue Descriptor Address */
++#define	REG_VIQ_TXBD_DESA_8192E			0x0320	/* TX VI Queue Descriptor Address */
++#define	REG_BEQ_TXBD_DESA_8192E			0x0328	/* TX BE Queue Descriptor Address */
++#define	REG_BKQ_TXBD_DESA_8192E			0x0330	/* TX BK Queue Descriptor Address */
++#define	REG_RXQ_RXBD_DESA_8192E			0x0338	/* RX Queue	Descriptor Address */
++#define	REG_HI0Q_TXBD_DESA_8192E			0x0340
++#define	REG_HI1Q_TXBD_DESA_8192E			0x0348
++#define	REG_HI2Q_TXBD_DESA_8192E			0x0350
++#define	REG_HI3Q_TXBD_DESA_8192E			0x0358
++#define	REG_HI4Q_TXBD_DESA_8192E			0x0360
++#define	REG_HI5Q_TXBD_DESA_8192E			0x0368
++#define	REG_HI6Q_TXBD_DESA_8192E			0x0370
++#define	REG_HI7Q_TXBD_DESA_8192E			0x0378
++#define	REG_MGQ_TXBD_NUM_8192E			0x0380
++#define	REG_RX_RXBD_NUM_8192E			0x0382
++#define	REG_VOQ_TXBD_NUM_8192E			0x0384
++#define	REG_VIQ_TXBD_NUM_8192E			0x0386
++#define	REG_BEQ_TXBD_NUM_8192E			0x0388
++#define	REG_BKQ_TXBD_NUM_8192E			0x038A
++#define	REG_HI0Q_TXBD_NUM_8192E			0x038C
++#define	REG_HI1Q_TXBD_NUM_8192E			0x038E
++#define	REG_HI2Q_TXBD_NUM_8192E			0x0390
++#define	REG_HI3Q_TXBD_NUM_8192E			0x0392
++#define	REG_HI4Q_TXBD_NUM_8192E			0x0394
++#define	REG_HI5Q_TXBD_NUM_8192E			0x0396
++#define	REG_HI6Q_TXBD_NUM_8192E			0x0398
++#define	REG_HI7Q_TXBD_NUM_8192E			0x039A
++#define	REG_TSFTIMER_HCI_8192E			0x039C
++
++/* Read Write Point */
++#define	REG_VOQ_TXBD_IDX_8192E			0x03A0
++#define	REG_VIQ_TXBD_IDX_8192E			0x03A4
++#define	REG_BEQ_TXBD_IDX_8192E			0x03A8
++#define	REG_BKQ_TXBD_IDX_8192E			0x03AC
++#define	REG_MGQ_TXBD_IDX_8192E			0x03B0
++#define	REG_RXQ_TXBD_IDX_8192E			0x03B4
++#define	REG_HI0Q_TXBD_IDX_8192E			0x03B8
++#define	REG_HI1Q_TXBD_IDX_8192E			0x03BC
++#define	REG_HI2Q_TXBD_IDX_8192E			0x03C0
++#define	REG_HI3Q_TXBD_IDX_8192E			0x03C4
++#define	REG_HI4Q_TXBD_IDX_8192E			0x03C8
++#define	REG_HI5Q_TXBD_IDX_8192E			0x03CC
++#define	REG_HI6Q_TXBD_IDX_8192E			0x03D0
++#define	REG_HI7Q_TXBD_IDX_8192E			0x03D4
++
++#define	REG_PCIE_HCPWM_8192EE			0x03D8 /* ?????? */
++#define	REG_PCIE_HRPWM_8192EE			0x03DC	/* PCIe RPWM */ /* ?????? */
++#define	REG_DBI_WDATA_V1_8192E			0x03E8
++#define	REG_DBI_RDATA_V1_8192E			0x03EC
++#define	REG_DBI_FLAG_V1_8192E				0x03F0
++#define	REG_MDIO_V1_8192E					0x3F4
++#define	REG_PCIE_MIX_CFG_8192E				0x3F8
++
++/* -----------------------------------------------------
++ *
++ *	0x0400h ~ 0x047Fh	Protocol Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_TXBF_CTRL_8192E				0x042C
++#define REG_ARFR0_8192E					0x0444
++#define REG_ARFR1_8192E					0x044C
++#define REG_CCK_CHECK_8192E				0x0454
++#define REG_AMPDU_MAX_TIME_8192E			0x0456
++#define REG_BCNQ1_BDNY_8192E				0x0457
++
++#define REG_AMPDU_MAX_LENGTH_8192E	0x0458
++#define REG_WMAC_LBK_BUF_HD_8192E			0x045D
++#define REG_NDPA_OPT_CTRL_8192E		0x045F
++#define REG_DATA_SC_8192E				0x0483
++#ifdef CONFIG_WOWLAN
++	#define REG_TXPKTBUF_IV_LOW             0x0484
++	#define REG_TXPKTBUF_IV_HIGH            0x0488
++#endif
++#define REG_ARFR2_8192E					0x048C
++#define REG_ARFR3_8192E					0x0494
++#define REG_TXRPT_START_OFFSET			0x04AC
++#define REG_AMPDU_BURST_MODE_8192E	0x04BC
++#define REG_HT_SINGLE_AMPDU_8192E		0x04C7
++#define REG_MACID_PKT_DROP0_8192E		0x04D0
++
++/* -----------------------------------------------------
++ *
++ *	0x0500h ~ 0x05FFh	EDCA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_CTWND_8192E					0x0572
++#define REG_SECONDARY_CCA_CTRL_8192E	0x0577
++#define REG_SCH_TXCMD_8192E			0x05F8
++
++/* -----------------------------------------------------
++ *
++ *	0x0600h ~ 0x07FFh	WMAC Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_MAC_CR_8192E				0x0600
++
++#define REG_MAC_TX_SM_STATE_8192E		0x06B4
++
++/* Power */
++#define REG_BFMER0_INFO_8192E			0x06E4
++#define REG_BFMER1_INFO_8192E			0x06EC
++#define REG_CSI_RPT_PARAM_BW20_8192E	0x06F4
++#define REG_CSI_RPT_PARAM_BW40_8192E	0x06F8
++#define REG_CSI_RPT_PARAM_BW80_8192E	0x06FC
++
++/* Hardware Port 2 */
++#define REG_BFMEE_SEL_8192E				0x0714
++#define REG_SND_PTCL_CTRL_8192E		0x0718
++
++
++/* -----------------------------------------------------
++ *
++ *	Redifine register definition for compatibility
++ *
++ * ----------------------------------------------------- */
++
++/* TODO: use these definition when using REG_xxx naming rule.
++ * NOTE: DO NOT Remove these definition. Use later. */
++#define	ISR_8192E							REG_HISR0_8192E
++
++/* ----------------------------------------------------------------------------
++ * 8192E IMR/ISR bits						(offset 0xB0,  8bits)
++ * ---------------------------------------------------------------------------- */
++#define	IMR_DISABLED_8192E					0
++/* IMR DW0(0x00B0-00B3) Bit 0-31 */
++#define	IMR_TIMER2_8192E					BIT(31)		/* Timeout interrupt 2 */
++#define	IMR_TIMER1_8192E					BIT(30)		/* Timeout interrupt 1	 */
++#define	IMR_PSTIMEOUT_8192E				BIT(29)		/* Power Save Time Out Interrupt */
++#define	IMR_GTINT4_8192E					BIT(28)		/* When GTIMER4 expires, this bit is set to 1	 */
++#define	IMR_GTINT3_8192E					BIT(27)		/* When GTIMER3 expires, this bit is set to 1	 */
++#define	IMR_TXBCN0ERR_8192E				BIT(26)		/* Transmit Beacon0 Error			 */
++#define	IMR_TXBCN0OK_8192E					BIT(25)		/* Transmit Beacon0 OK			 */
++#define	IMR_TSF_BIT32_TOGGLE_8192E		BIT(24)		/* TSF Timer BIT(32) toggle indication interrupt			 */
++#define	IMR_BCNDMAINT0_8192E				BIT(20)		/* Beacon DMA Interrupt 0			 */
++#define	IMR_BCNDERR0_8192E					BIT(16)		/* Beacon Queue DMA OK0			 */
++#define	IMR_HSISR_IND_ON_INT_8192E		BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
++#define	IMR_BCNDMAINT_E_8192E				BIT(14)		/* Beacon DMA Interrupt Extension for Win7			 */
++#define	IMR_ATIMEND_8192E					BIT(12)		/* CTWidnow End or ATIM Window End */
++#define	IMR_C2HCMD_8192E					BIT(10)		/* CPU to Host Command INT Status, Write 1 clear	 */
++#define	IMR_CPWM2_8192E					BIT(9)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
++#define	IMR_CPWM_8192E						BIT(8)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
++#define	IMR_HIGHDOK_8192E					BIT(7)			/* High Queue DMA OK	 */
++#define	IMR_MGNTDOK_8192E					BIT(6)			/* Management Queue DMA OK	 */
++#define	IMR_BKDOK_8192E					BIT(5)			/* AC_BK DMA OK		 */
++#define	IMR_BEDOK_8192E					BIT(4)			/* AC_BE DMA OK	 */
++#define	IMR_VIDOK_8192E					BIT(3)			/* AC_VI DMA OK		 */
++#define	IMR_VODOK_8192E					BIT(2)			/* AC_VO DMA OK	 */
++#define	IMR_RDU_8192E						BIT(1)			/* Rx Descriptor Unavailable	 */
++#define	IMR_ROK_8192E						BIT(0)			/* Receive DMA OK */
++
++/* IMR DW1(0x00B4-00B7) Bit 0-31 */
++#define	IMR_BCNDMAINT7_8192E				BIT(27)		/* Beacon DMA Interrupt 7 */
++#define	IMR_BCNDMAINT6_8192E				BIT(26)		/* Beacon DMA Interrupt 6 */
++#define	IMR_BCNDMAINT5_8192E				BIT(25)		/* Beacon DMA Interrupt 5 */
++#define	IMR_BCNDMAINT4_8192E				BIT(24)		/* Beacon DMA Interrupt 4 */
++#define	IMR_BCNDMAINT3_8192E				BIT(23)		/* Beacon DMA Interrupt 3 */
++#define	IMR_BCNDMAINT2_8192E				BIT(22)		/* Beacon DMA Interrupt 2 */
++#define	IMR_BCNDMAINT1_8192E				BIT(21)		/* Beacon DMA Interrupt 1 */
++#define	IMR_BCNDOK7_8192E					BIT(20)		/* Beacon Queue DMA OK Interrupt 7 */
++#define	IMR_BCNDOK6_8192E					BIT(19)		/* Beacon Queue DMA OK Interrupt 6 */
++#define	IMR_BCNDOK5_8192E					BIT(18)		/* Beacon Queue DMA OK Interrupt 5 */
++#define	IMR_BCNDOK4_8192E					BIT(17)		/* Beacon Queue DMA OK Interrupt 4 */
++#define	IMR_BCNDOK3_8192E					BIT(16)		/* Beacon Queue DMA OK Interrupt 3 */
++#define	IMR_BCNDOK2_8192E					BIT(15)		/* Beacon Queue DMA OK Interrupt 2 */
++#define	IMR_BCNDOK1_8192E					BIT(14)		/* Beacon Queue DMA OK Interrupt 1 */
++#define	IMR_ATIMEND_E_8192E				BIT(13)		/* ATIM Window End Extension for Win7 */
++#define	IMR_TXERR_8192E					BIT(11)		/* Tx Error Flag Interrupt Status, write 1 clear. */
++#define	IMR_RXERR_8192E					BIT(10)		/* Rx Error Flag INT Status, Write 1 clear */
++#define	IMR_TXFOVW_8192E					BIT(9)			/* Transmit FIFO Overflow */
++#define	IMR_RXFOVW_8192E					BIT(8)			/* Receive FIFO Overflow */
++
++/* ----------------------------------------------------------------------------
++ * 8192E Auto LLT bits						(offset 0x224,  8bits)
++ * ----------------------------------------------------------------------------
++ * 224 REG_AUTO_LLT
++ * move to hal_com_reg.h */
++
++/* ----------------------------------------------------------------------------
++ * 8192E Auto LLT bits						(offset 0x290,  32bits)
++ * ---------------------------------------------------------------------------- */
++#define BIT_DMA_MODE			BIT(1)
++#define BIT_USB_RXDMA_AGG_EN	BIT(31)
++
++/* ----------------------------------------------------------------------------
++ * 8192E REG_SYS_CFG1						(offset 0xF0,  32bits)
++ * ---------------------------------------------------------------------------- */
++#define BIT_SPSLDO_SEL			BIT(24)
++
++
++/* ----------------------------------------------------------------------------
++ * 8192E REG_CCK_CHECK						(offset 0x454,  8bits)
++ * ---------------------------------------------------------------------------- */
++#define BIT_BCN_PORT_SEL		BIT(5)
++
++/* ****************************************************************************
++ * Regsiter Bit and Content definition
++ * **************************************************************************** */
++
++/* 2 ACMHWCTRL 0x05C0 */
++#define	AcmHw_HwEn_8192E				BIT(0)
++#define	AcmHw_VoqEn_8192E				BIT(1)
++#define	AcmHw_ViqEn_8192E				BIT(2)
++#define	AcmHw_BeqEn_8192E				BIT(3)
++#define	AcmHw_VoqStatus_8192E			BIT(5)
++#define	AcmHw_ViqStatus_8192E			BIT(6)
++#define	AcmHw_BeqStatus_8192E			BIT(7)
++
++#endif /* __RTL8192E_SPEC_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_sreset.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_sreset.h
+new file mode 100644
+index 000000000..78109aea4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_sreset.h
+@@ -0,0 +1,24 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2012 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL88812A_SRESET_H_
++#define _RTL8812A_SRESET_H_
++
++#include <rtw_sreset.h>
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++	extern void rtl8192e_sreset_xmit_status_check(_adapter *padapter);
++	extern void rtl8192e_sreset_linked_status_check(_adapter *padapter);
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_xmit.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_xmit.h
+new file mode 100644
+index 000000000..d938e6f5e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192e_xmit.h
+@@ -0,0 +1,448 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2012 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8192E_XMIT_H__
++#define __RTL8192E_XMIT_H__
++
++typedef struct txdescriptor_8192e {
++	/* Offset 0 */
++	u32 pktlen:16;
++	u32 offset:8;
++	u32 bmc:1;
++	u32 htc:1;
++	u32 ls:1;
++	u32 fs:1;
++	u32 linip:1;
++	u32 noacm:1;
++	u32 gf:1;
++	u32 own:1;
++
++	/* Offset 4 */
++	u32 macid:6;
++	u32 rsvd0406:2;
++	u32 qsel:5;
++	u32 rd_nav_ext:1;
++	u32 lsig_txop_en:1;
++	u32 pifs:1;
++	u32 rate_id:4;
++	u32 navusehdr:1;
++	u32 en_desc_id:1;
++	u32 sectype:2;
++	u32 rsvd0424:2;
++	u32 pkt_offset:5;	/* unit: 8 bytes */
++	u32 rsvd0431:1;
++
++	/* Offset 8 */
++	u32 rts_rc:6;
++	u32 data_rc:6;
++	u32 agg_en:1;
++	u32 rd_en:1;
++	u32 bar_rty_th:2;
++	u32 bk:1;
++	u32 morefrag:1;
++	u32 raw:1;
++	u32 ccx:1;
++	u32 ampdu_density:3;
++	u32 bt_null:1;
++	u32 ant_sel_a:1;
++	u32 ant_sel_b:1;
++	u32 tx_ant_cck:2;
++	u32 tx_antl:2;
++	u32 tx_ant_ht:2;
++
++	/* Offset 12 */
++	u32 nextheadpage:8;
++	u32 tailpage:8;
++	u32 seq:12;
++	u32 cpu_handle:1;
++	u32 tag1:1;
++	u32 trigger_int:1;
++	u32 hwseq_en:1;
++
++	/* Offset 16 */
++	u32 rtsrate:5;
++	u32 ap_dcfe:1;
++	u32 hwseq_sel:2;
++	u32 userate:1;
++	u32 disrtsfb:1;
++	u32 disdatafb:1;
++	u32 cts2self:1;
++	u32 rtsen:1;
++	u32 hw_rts_en:1;
++	u32 port_id:1;
++	u32 pwr_status:3;
++	u32 wait_dcts:1;
++	u32 cts2ap_en:1;
++	u32 data_sc:2;
++	u32 data_stbc:2;
++	u32 data_short:1;
++	u32 data_bw:1;
++	u32 rts_short:1;
++	u32 rts_bw:1;
++	u32 rts_sc:2;
++	u32 vcs_stbc:2;
++
++	/* Offset 20 */
++	u32 datarate:6;
++	u32 sgi:1;
++	u32 try_rate:1;
++	u32 data_ratefb_lmt:5;
++	u32 rts_ratefb_lmt:4;
++	u32 rty_lmt_en:1;
++	u32 data_rt_lmt:6;
++	u32 usb_txagg_num:8;
++
++	/* Offset 24 */
++	u32 txagg_a:5;
++	u32 txagg_b:5;
++	u32 use_max_len:1;
++	u32 max_agg_num:5;
++	u32 mcsg1_max_len:4;
++	u32 mcsg2_max_len:4;
++	u32 mcsg3_max_len:4;
++	u32 mcs7_sgi_max_len:4;
++
++	/* Offset 28 */
++	u32 checksum:16;	/* TxBuffSize(PCIe)/CheckSum(USB) */
++	u32 mcsg4_max_len:4;
++	u32 mcsg5_max_len:4;
++	u32 mcsg6_max_len:4;
++	u32 mcs15_sgi_max_len:4;
++} TXDESC_8192E, *PTXDESC_8192E;
++
++
++
++/* For 88e early mode */
++#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
++#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
++#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
++#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
++#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
++#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
++#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
++
++/*
++ * defined for TX DESC Operation
++ *   */
++
++#define MAX_TID (15)
++
++/* OFFSET 0 */
++#define OFFSET_SZ	0
++#define OFFSET_SHT	16
++#define BMC		BIT(24)
++#define LSG		BIT(26)
++#define FSG		BIT(27)
++#define OWN		BIT(31)
++
++
++/* OFFSET 4 */
++#define PKT_OFFSET_SZ		0
++#define QSEL_SHT			8
++#define RATE_ID_SHT			16
++#define NAVUSEHDR			BIT(20)
++#define SEC_TYPE_SHT		22
++#define PKT_OFFSET_SHT		26
++
++/* OFFSET 8 */
++#define AGG_EN				BIT(12)
++#define AGG_BK					BIT(16)
++#define AMPDU_DENSITY_SHT	20
++#define ANTSEL_A			BIT(24)
++#define ANTSEL_B			BIT(25)
++#define TX_ANT_CCK_SHT		26
++#define TX_ANTL_SHT			28
++#define TX_ANT_HT_SHT		30
++
++/* OFFSET 12 */
++#define SEQ_SHT				16
++#define EN_HWSEQ			BIT(31)
++
++/* OFFSET 16 */
++#define	QOS                          BIT(6)
++#define	HW_SSN				BIT(7)
++#define	USERATE			BIT(8)
++#define	DISDATAFB			BIT(10)
++#define   CTS_2_SELF			BIT(11)
++#define	RTS_EN				BIT(12)
++#define	HW_RTS_EN			BIT(13)
++#define	DATA_SHORT			BIT(24)
++#define	PWR_STATUS_SHT	15
++#define	DATA_SC_SHT		20
++#define	DATA_BW			BIT(25)
++
++/* OFFSET 20 */
++#define	RTY_LMT_EN			BIT(17)
++
++
++/* OFFSET 20 */
++#define SGI					BIT(6)
++#define USB_TXAGG_NUM_SHT	24
++
++
++/* *****Tx Desc Buffer content */
++
++/* config element for each tx buffer
++ *
++#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 0, 16, __Valeu)
++#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 31, 1, __Valeu)
++#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+4, 0, 32, __Valeu)
++#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu)
++*/
++#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
++#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
++#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
++#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu)
++
++
++/* Dword 0 */
++#define SET_TX_BUFF_DESC_LEN_0_92E(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
++#define SET_TX_BUFF_DESC_PSB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
++#define SET_TX_BUFF_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
++/* Dword 1 */
++#define SET_TX_BUFF_DESC_ADDR_LOW_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
++#define GET_TX_DESC_TX_BUFFER_ADDRESS_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
++
++
++/* Dword 2 */
++#define SET_TX_BUFF_DESC_ADDR_HIGH_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 32, __Value)
++/* Dword 3, RESERVED */
++
++
++/* *****Tx Desc content
++ * Dword 0 */
++#define SET_TX_DESC_PKT_SIZE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
++#define SET_TX_DESC_OFFSET_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
++#define SET_TX_DESC_BMC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
++#define SET_TX_DESC_HTC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
++#define SET_TX_DESC_LAST_SEG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
++#define SET_TX_DESC_FIRST_SEG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
++#define SET_TX_DESC_LINIP_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
++#define SET_TX_DESC_NO_ACM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
++#define SET_TX_DESC_GF_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
++#define SET_TX_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
++#define GET_TX_DESC_OWN_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
++
++/* Dword 1 */
++#define SET_TX_DESC_MACID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
++#define SET_TX_DESC_QUEUE_SEL_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
++#define SET_TX_DESC_RDG_NAV_EXT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
++#define SET_TX_DESC_LSIG_TXOP_EN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
++#define SET_TX_DESC_PIFS_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
++#define SET_TX_DESC_RATE_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
++#define SET_TX_DESC_EN_DESC_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
++#define SET_TX_DESC_SEC_TYPE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
++#define SET_TX_DESC_PKT_OFFSET_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
++#define SET_TX_DESC_MORE_DATA_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
++#define SET_TX_DESC_TXOP_PS_CAP_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 30, 1, __Value)
++#define SET_TX_DESC_TXOP_PS_MODE_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 31, 1, __Value)
++
++
++/* Dword 2 */
++#define SET_TX_DESC_PAID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
++#define SET_TX_DESC_CCA_RTS_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
++#define SET_TX_DESC_AGG_ENABLE_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
++#define SET_TX_DESC_RDG_ENABLE_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
++#define SET_TX_DESC_NULL_0_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
++#define SET_TX_DESC_NULL_1_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
++#define SET_TX_DESC_BK_92E(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
++#define SET_TX_DESC_MORE_FRAG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
++#define SET_TX_DESC_RAW_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
++#define GET_TX_DESC_MORE_FRAG_92E(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc+8, 17, 1)
++#define SET_TX_DESC_SPE_RPT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
++#define SET_TX_DESC_AMPDU_DENSITY_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
++#define SET_TX_DESC_BT_NULL_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
++#define SET_TX_DESC_GID_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
++
++
++/* Dword 3 */
++#define SET_TX_DESC_WHEADER_LEN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
++#define SET_TX_DESC_CHK_EN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
++#define SET_TX_DESC_EARLY_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
++#define SET_TX_DESC_HWSEQ_SEL_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
++#define SET_TX_DESC_USE_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
++#define SET_TX_DESC_DISABLE_RTS_FB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
++#define SET_TX_DESC_DISABLE_FB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
++#define SET_TX_DESC_CTS2SELF_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
++#define SET_TX_DESC_RTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
++#define SET_TX_DESC_HW_RTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
++#define SET_TX_DESC_HW_PORT_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value)
++#define SET_TX_DESC_NAV_USE_HDR_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
++#define SET_TX_DESC_USE_MAX_LEN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
++#define SET_TX_DESC_MAX_AGG_NUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
++#define SET_TX_DESC_NDPA_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
++#define SET_TX_DESC_AMPDU_MAX_TIME_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
++
++/* Dword 4 */
++#define SET_TX_DESC_TX_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
++#define SET_TX_DESC_TRY_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
++#define SET_TX_DESC_DATA_RATE_FB_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
++#define SET_TX_DESC_RTS_RATE_FB_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
++#define SET_TX_DESC_RETRY_LIMIT_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
++#define SET_TX_DESC_DATA_RETRY_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
++#define SET_TX_DESC_RTS_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
++#define SET_TX_DESC_PCTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
++#define SET_TX_DESC_PCTS_MASK_IDX_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
++
++
++/* Dword 5 */
++#define SET_TX_DESC_DATA_SC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
++#define SET_TX_DESC_DATA_SHORT_92E(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
++#define SET_TX_DESC_DATA_BW_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
++#define SET_TX_DESC_DATA_LDPC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
++#define SET_TX_DESC_DATA_STBC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
++#define SET_TX_DESC_VCS_STBC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
++#define SET_TX_DESC_RTS_SHORT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
++#define SET_TX_DESC_RTS_SC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
++#define SET_TX_DESC_TX_ANT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value)
++#define SET_TX_DESC_TX_POWER_0_PSET_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
++
++/* Dword 6 */
++#define SET_TX_DESC_SW_DEFINE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
++#define SET_TX_DESC_MBSSID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
++#define SET_TX_DESC_ANTSEL_A_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
++#define SET_TX_DESC_ANTSEL_B_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
++#define SET_TX_DESC_ANTSEL_C_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
++#define SET_TX_DESC_ANTSEL_D_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
++
++/* Dword 7 */
++#ifdef CONFIG_PCI_HCI
++	#define SET_TX_DESC_TX_BUFFER_SIZE_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++#endif
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
++	#define SET_TX_DESC_TX_DESC_CHECKSUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++#endif
++#define SET_TX_DESC_USB_TXAGG_NUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
++
++
++/* #define SET_TX_DESC_HWSEQ_EN_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) */
++/* Dword 8 */
++
++#define SET_TX_DESC_RTS_RC_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
++#define SET_TX_DESC_BAR_RTY_TH_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
++#define SET_TX_DESC_DATA_RC_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
++#define SET_TX_DESC_EN_HWSEQ_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
++#define SET_TX_DESC_NEXT_HEAD_PAGE_92E(__pTxDesc, __Value)(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
++#define SET_TX_DESC_TAIL_PAGE_92E(__pTxDesc, __Value)(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
++
++/* Dword 9 */
++#define SET_TX_DESC_PADDING_LENGTH_92E(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
++#define SET_TX_DESC_TXBF_PATH_92E(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 11, 1, __Value)
++#define SET_TX_DESC_SEQ_92E(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
++#define SET_TX_DESC_FINAL_DATA_RATE_92E(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
++
++
++#define SET_EARLYMODE_PKTNUM_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
++#define SET_EARLYMODE_LEN0_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
++#define SET_EARLYMODE_LEN1_1_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
++#define SET_EARLYMODE_LEN1_2_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
++#define SET_EARLYMODE_LEN2_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,  __Value)
++#define SET_EARLYMODE_LEN3_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
++
++void rtl8192e_cal_txdesc_chksum(u8 *ptxdesc);
++
++#ifdef CONFIG_USB_HCI
++	s32 rtl8192eu_init_xmit_priv(PADAPTER padapter);
++	void rtl8192eu_free_xmit_priv(PADAPTER padapter);
++	s32 rtl8192eu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8192eu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	rtl8192eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8192eu_xmit_buf_handler(PADAPTER padapter);
++	#define hal_xmit_handler rtl8192eu_xmit_buf_handler
++	void rtl8192eu_xmit_tasklet(void *priv);
++	s32 rtl8192eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	s32 rtl8192ee_init_xmit_priv(PADAPTER padapter);
++	void rtl8192ee_free_xmit_priv(PADAPTER padapter);
++	struct xmit_buf *rtl8192ee_dequeue_xmitbuf(struct rtw_tx_ring *ring);
++	s32	rtl8192ee_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	void	rtl8192ee_xmitframe_resume(_adapter *padapter);
++	s32 rtl8192ee_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8192ee_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	void rtl8192ee_xmit_tasklet(void *priv);
++#endif
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	s32 rtl8192es_init_xmit_priv(PADAPTER padapter);
++	void rtl8192es_free_xmit_priv(PADAPTER padapter);
++
++	s32 rtl8192es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8192es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	rtl8192es_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	thread_return rtl8192es_xmit_thread(thread_context context);
++	s32 rtl8192es_xmit_buf_handler(PADAPTER padapter);
++
++	#ifdef CONFIG_SDIO_TX_TASKLET
++		void rtl8192es_xmit_tasklet(void *priv);
++	#endif
++#endif
++
++struct txrpt_ccx_92e {
++	/* offset 0 */
++	u8 tag1:1;
++	u8 pkt_num:3;
++	u8 txdma_underflow:1;
++	u8 int_bt:1;
++	u8 int_tri:1;
++	u8 int_ccx:1;
++
++	/* offset 1 */
++	u8 mac_id:6;
++	u8 pkt_ok:1;
++	u8 bmc:1;
++
++	/* offset 2 */
++	u8 retry_cnt:6;
++	u8 lifetime_over:1;
++	u8 retry_over:1;
++
++	/* offset 3 */
++	u8 ccx_qtime0;
++	u8 ccx_qtime1;
++
++	/* offset 5 */
++	u8 final_data_rate;
++
++	/* offset 6 */
++	u8 sw1:4;
++	u8 qsel:4;
++
++	/* offset 7 */
++	u8 sw0;
++};
++
++#ifdef CONFIG_TX_EARLY_MODE
++	void UpdateEarlyModeInfo8192E(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++#endif
++s32	rtl8192e_init_xmit_priv(_adapter *padapter);
++void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, u8 *ptxdesc);
++
++void rtl8192e_fill_fake_txdesc(PADAPTER	padapter, u8 *pDesc, u32 BufferLen,
++			       u8 IsPsPoll, u8	IsBTQosNull, u8 bDataFrame);
++void rtl8192e_cal_txdesc_chksum(u8 *ptxdesc);
++
++u8	BWMapping_92E(PADAPTER Adapter, struct pkt_attrib *pattrib);
++u8	SCMapping_92E(PADAPTER Adapter, struct pkt_attrib	*pattrib);
++void fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
++void fill_txdesc_vcs(struct pkt_attrib *pattrib, u8 *ptxdesc);
++void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
++void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
++
++void fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc);
++void rtl8192e_fixed_rate(_adapter *padapter, u8 *ptxdesc);
++
++#endif /* __RTL8192E_XMIT_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_cmd.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_cmd.h
+new file mode 100644
+index 000000000..69ee67420
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_cmd.h
+@@ -0,0 +1,194 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8192F_CMD_H__
++#define __RTL8192F_CMD_H__
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++enum h2c_cmd_8192F {
++	/* Common Class: 000 */
++	H2C_8192F_RSVD_PAGE = 0x00,
++	H2C_8192F_MEDIA_STATUS_RPT = 0x01,
++	H2C_8192F_SCAN_ENABLE = 0x02,
++	H2C_8192F_KEEP_ALIVE = 0x03,
++	H2C_8192F_DISCON_DECISION = 0x04,	
++	H2C_8192F_PSD_OFFLOAD = 0x05,	
++	H2C_8192F_AP_OFFLOAD = 0x08,	
++	H2C_8192F_BCN_RSVDPAGE = 0x09,	
++	H2C_8192F_PROBERSP_RSVDPAGE = 0x0A,	
++	H2C_8192F_FCS_RSVDPAGE = 0x10,	
++	H2C_8192F_FCS_INFO = 0x11,	
++	H2C_8192F_AP_WOW_GPIO_CTRL = 0x13,
++
++	/* PoweSave Class: 001 */
++	H2C_8192F_SET_PWR_MODE = 0x20,
++	H2C_8192F_PS_TUNING_PARA = 0x21,
++	H2C_8192F_PS_TUNING_PARA2 = 0x22,
++	H2C_8192F_P2P_LPS_PARAM = 0x23,	
++	H2C_8192F_P2P_PS_OFFLOAD = 0x24,	
++	H2C_8192F_PS_SCAN_ENABLE = 0x25,	
++	H2C_8192F_SAP_PS_ = 0x26,
++	H2C_8192F_INACTIVE_PS_ = 0x27,/* Inactive_PS */
++	H2C_8192F_FWLPS_IN_IPS_ = 0x28,
++
++	/* Dynamic Mechanism Class: 010 */
++	H2C_8192F_MACID_CFG = 0x40,	
++	H2C_8192F_TXBF = 0x41,	
++	H2C_8192F_RSSI_SETTING = 0x42,	
++	H2C_8192F_AP_REQ_TXRPT = 0x43,	
++	H2C_8192F_INIT_RATE_COLLECT = 0x44,	
++	H2C_8192F_RA_PARA_ADJUST = 0x46,
++
++	/* BT Class: 011 */
++	H2C_8192F_B_TYPE_TDMA = 0x60,
++	H2C_8192F_BT_INFO = 0x61,
++	H2C_8192F_FORCE_BT_TXPWR = 0x62,
++	H2C_8192F_BT_IGNORE_WLANACT = 0x63,
++	H2C_8192F_DAC_SWING_VALUE = 0x64,
++	H2C_8192F_ANT_SEL_RSV = 0x65,
++	H2C_8192F_WL_OPMODE = 0x66,
++	H2C_8192F_BT_MP_OPER = 0x67,
++	H2C_8192F_BT_CONTROL = 0x68,
++	H2C_8192F_BT_WIFI_CTRL = 0x69,
++	H2C_8192F_BT_FW_PATCH = 0x6A,
++	H2C_8192F_BT_WLAN_CALIBRATION = 0x6D,
++
++	/* WOWLAN Class: 100 */
++	H2C_8192F_WOWLAN = 0x80,
++	H2C_8192F_REMOTE_WAKE_CTRL = 0x81,
++	H2C_8192F_AOAC_GLOBAL_INFO = 0x82,	
++	H2C_8192F_AOAC_RSVD_PAGE = 0x83,	
++	H2C_8192F_AOAC_RSVD_PAGE2 = 0x84,
++	H2C_8192F_D0_SCAN_OFFLOAD_CTRL = 0x85,
++	H2C_8192F_D0_SCAN_OFFLOAD_INFO = 0x86,
++	H2C_8192F_CHNL_SWITCH_OFFLOAD = 0x87,
++	H2C_8192F_P2P_OFFLOAD_RSVD_PAGE = 0x8A,	
++	H2C_8192F_P2P_OFFLOAD = 0x8B,
++
++	H2C_8192F_RESET_TSF = 0xC0,
++	H2C_8192F_MAXID,
++};
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
++ * ---------------------------------------------------------------------------------------------------------
++ * _RSVDPAGE_LOC_CMD_0x00 */
++#define SET_8192F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8192F_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_8192F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8192F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8192F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++/*_MEDIA_STATUS_RPT_PARM_CMD_0x01*/
++#define SET_8192F_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
++/* _PWR_MOD_CMD_0x20 */
++#define SET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8192F_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
++#define SET_8192F_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
++#define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8192F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
++#define SET_8192F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++#define GET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
++
++/* _PS_TUNE_PARAM_CMD_0x21 */
++#define SET_8192F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_8192F_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
++#define SET_8192F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
++#define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++
++/* _MACID_CFG_CMD_0x40 */
++#define SET_8192F_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8192F_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
++#define SET_8192F_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
++#define SET_8192F_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
++#define SET_8192F_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
++#define SET_8192F_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
++#define SET_8192F_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
++#define SET_8192F_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
++#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
++#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
++#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
++
++/* _RSSI_SETTING_CMD_0x42 */
++#define SET_8192F_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8192F_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
++#define SET_8192F_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++
++/* _AP_REQ_TXRPT_CMD_0x43 */
++#define SET_8192F_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8192F_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++
++/* _FORCE_BT_TXPWR_CMD_0x62 */
++#define SET_8192F_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++
++/* _FORCE_BT_MP_OPER_CMD_0x67 */
++#define SET_8192F_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
++#define SET_8192F_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
++#define SET_8192F_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_8192F_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
++#define SET_8192F_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++#define SET_8192F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
++
++/* _BT_FW_PATCH_0x6A */
++#define SET_8192F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
++#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
++
++/* ---------------------------------------------------------------------------------------------------------
++ * -------------------------------------------    Structure    --------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    Function Statement     --------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++/* host message to firmware cmd */
++void rtl8192f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
++void rtl8192f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
++/* s32 rtl8192f__set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
++void rtl8192f_set_FwPsTuneParam_cmd(PADAPTER padapter);
++void rtl8192f_download_rsvd_page(PADAPTER padapter, u8 mstatus);
++#ifdef CONFIG_BT_COEXIST
++void rtl8192f_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
++#endif /* CONFIG_BT_COEXIST */
++#ifdef CONFIG_P2P
++void rtl8192f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
++#endif /* CONFIG_P2P */
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_TDLS_CH_SW
++void rtl8192f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
++#endif
++#endif
++
++#ifdef CONFIG_P2P_WOWLAN
++void rtl8192f_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
++#endif
++
++s32 FillH2CCmd8192F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
++u8 GetTxBufferRsvdPageNum8192F(_adapter *padapter, bool wowlan);
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_dm.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_dm.h
+new file mode 100644
+index 000000000..43e6396ab
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_dm.h
+@@ -0,0 +1,27 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2012 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8192F_DM_H__
++#define __RTL8192F_DM_H__
++
++void rtl8192f_init_dm_priv(PADAPTER Adapter);
++void rtl8192f_deinit_dm_priv(PADAPTER Adapter);
++void rtl8192f_InitHalDm(PADAPTER Adapter);
++void rtl8192f_HalDmWatchDog(PADAPTER Adapter);
++
++/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */
++
++/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_hal.h
+new file mode 100644
+index 000000000..73ee78502
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_hal.h
+@@ -0,0 +1,316 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8192F_HAL_H__
++#define __RTL8192F_HAL_H__
++
++#include "hal_data.h"
++
++#include "rtl8192f_spec.h"
++#include "rtl8192f_rf.h"
++#include "rtl8192f_dm.h"
++#include "rtl8192f_recv.h"
++#include "rtl8192f_xmit.h"
++#include "rtl8192f_cmd.h"
++#include "rtl8192f_led.h"
++#include "Hal8192FPwrSeq.h"
++#include "Hal8192FPhyReg.h"
++#include "Hal8192FPhyCfg.h"
++#ifdef DBG_CONFIG_ERROR_DETECT
++#include "rtl8192f_sreset.h"
++#endif
++#ifdef CONFIG_LPS_POFF
++	#include "rtl8192f_lps_poff.h"
++#endif
++
++#define FW_8192F_SIZE		0x8000
++#define FW_8192F_START_ADDRESS	0x4000
++#define FW_8192F_END_ADDRESS	0x5000 /* brian_zhang@realsil.com.cn */
++
++#define IS_FW_HEADER_EXIST_8192F(_pFwHdr)\
++	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x92F0)
++
++typedef struct _RT_FIRMWARE {
++	FIRMWARE_SOURCE	eFWSource;
++#ifdef CONFIG_EMBEDDED_FWIMG
++	u8			*szFwBuffer;
++#else
++	u8			szFwBuffer[FW_8192F_SIZE];
++#endif
++	u32			ulFwLength;
++} RT_FIRMWARE_8192F, *PRT_FIRMWARE_8192F;
++
++/*
++ * This structure must be cared byte-ordering
++ *
++ * Added by tynli. 2009.12.04. */
++typedef struct _RT_8192F_FIRMWARE_HDR {
++	/* 8-byte alinment required */
++
++	/* --- LONG WORD 0 ---- */
++	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
++	u8		Category;	/* AP/NIC and USB/PCI */
++	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
++	u16		Version;		/* FW Version */
++	u16		Subversion;	/* FW Subversion, default 0x00 */
++
++	/* --- LONG WORD 1 ---- */
++	u8		Month;	/* Release time Month field */
++	u8		Date;	/* Release time Date field */
++	u8		Hour;	/* Release time Hour field */
++	u8		Minute;	/* Release time Minute field */
++	u16		RamCodeSize;	/* The size of RAM code */
++	u16		Rsvd2;
++
++	/* --- LONG WORD 2 ---- */
++	u32		SvnIdx;	/* The SVN entry index */
++	u32		Rsvd3;
++
++	/* --- LONG WORD 3 ---- */
++	u32		Rsvd4;
++	u32		Rsvd5;
++} RT_8192F_FIRMWARE_HDR, *PRT_8192F_FIRMWARE_HDR;
++#define DRIVER_EARLY_INT_TIME_8192F		0x05
++#define BCN_DMA_ATIME_INT_TIME_8192F		0x02
++/* for 8192F
++ * TX 64K, RX 16K, Page size 256B for TX*/
++#define PAGE_SIZE_TX_8192F			256
++#define PAGE_SIZE_RX_8192F			8
++#define TX_DMA_SIZE_8192F			0x10000/* 64K(TX) */
++#define RX_DMA_SIZE_8192F			0x4000/* 16K(RX) */
++#ifdef CONFIG_WOWLAN
++	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
++#else
++	#define RESV_FMWF	0
++#endif
++
++#ifdef CONFIG_FW_C2H_DEBUG
++	#define RX_DMA_RESERVED_SIZE_8192F	0x100	/* 256B, reserved for c2h debug message */
++#else
++	#define RX_DMA_RESERVED_SIZE_8192F	0xc0	/* 192B, reserved for tx report 24*8=192*/
++#endif
++#define RX_DMA_BOUNDARY_8192F\
++	(RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F - 1)
++
++
++/* Note: We will divide number of page equally for each queue other than public queue! */
++
++/* For General Reserved Page Number(Beacon Queue is reserved page)
++ * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8192F
++ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
++#define BCNQ_PAGE_NUM_8192F		(MAX_BEACON_LEN/PAGE_SIZE_TX_8192F + 6) /*0x08*/
++
++
++/* For WoWLan , more reserved page
++ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6
++ * NS offload: 2 NDP info: 1
++ */
++#ifdef CONFIG_WOWLAN
++	/* 7 pages for wow rsvd page + 2 pages for pattern */
++	#define WOWLAN_PAGE_NUM_8192F	0x09
++#else
++	#define WOWLAN_PAGE_NUM_8192F	0x00
++#endif
++
++#ifdef CONFIG_PNO_SUPPORT
++	#undef WOWLAN_PAGE_NUM_8192F
++	#define WOWLAN_PAGE_NUM_8192F	0x15
++#endif
++
++#ifdef CONFIG_AP_WOWLAN
++	#define AP_WOWLAN_PAGE_NUM_8192F	0x02
++#endif
++
++#ifdef DBG_LA_MODE
++	#define LA_MODE_PAGE_NUM 0xE0
++#endif
++
++#define MAX_RX_DMA_BUFFER_SIZE_8192F	(RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F)
++
++#ifdef DBG_LA_MODE
++	#define TX_TOTAL_PAGE_NUMBER_8192F	(0xFF - LA_MODE_PAGE_NUM)
++#else
++	#define TX_TOTAL_PAGE_NUMBER_8192F	(0xFF - BCNQ_PAGE_NUM_8192F - WOWLAN_PAGE_NUM_8192F)
++#endif
++
++#define TX_PAGE_BOUNDARY_8192F		(TX_TOTAL_PAGE_NUMBER_8192F + 1)
++
++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8192F \
++	TX_TOTAL_PAGE_NUMBER_8192F
++#define WMM_NORMAL_TX_PAGE_BOUNDARY_8192F \
++	(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8192F + 1)
++
++/* For Normal Chip Setting
++ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8192F */
++#define NORMAL_PAGE_NUM_HPQ_8192F		0x8
++#define NORMAL_PAGE_NUM_LPQ_8192F		0x8
++#define NORMAL_PAGE_NUM_NPQ_8192F		0x8
++#define NORMAL_PAGE_NUM_EPQ_8192F		0x00
++
++/* Note: For Normal Chip Setting, modify later */
++#define WMM_NORMAL_PAGE_NUM_HPQ_8192F		0x30
++#define WMM_NORMAL_PAGE_NUM_LPQ_8192F		0x20
++#define WMM_NORMAL_PAGE_NUM_NPQ_8192F		0x20
++#define WMM_NORMAL_PAGE_NUM_EPQ_8192F		0x00
++
++
++#include "HalVerDef.h"
++#include "hal_com.h"
++
++#define EFUSE_OOB_PROTECT_BYTES 56 /*0x1C8~0x1FF*/
++
++#define HAL_EFUSE_MEMORY
++#define HWSET_MAX_SIZE_8192F                512
++#define EFUSE_REAL_CONTENT_LEN_8192F        512
++#define EFUSE_MAP_LEN_8192F                 512
++#define EFUSE_MAX_SECTION_8192F            64
++
++/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/
++#define EFUSE_IC_ID_OFFSET			506
++#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8192F)
++
++#define EFUSE_ACCESS_ON		0x69
++#define EFUSE_ACCESS_OFF	0x00
++
++/* ********************************************************
++ *			EFUSE for BT definition
++ * ******************************************************** */
++#define BANK_NUM			1
++#define EFUSE_BT_REAL_BANK_CONTENT_LEN	512
++#define EFUSE_BT_REAL_CONTENT_LEN	1536/*512 * 3 */
++/*	(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)*/
++#define EFUSE_BT_MAP_LEN		1024	/* 1k bytes */
++#define EFUSE_BT_MAX_SECTION		128 /* 1024/8 */
++#define EFUSE_PROTECT_BYTES_BANK	16
++
++typedef enum tag_Package_Definition {
++	PACKAGE_DEFAULT,
++	PACKAGE_QFN32,
++	PACKAGE_QFN40,
++	PACKAGE_QFN46
++} PACKAGE_TYPE_E;
++
++#define INCLUDE_MULTI_FUNC_BT(_Adapter) \
++	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
++#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \
++	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
++
++#ifdef CONFIG_FILE_FWIMG
++	extern char *rtw_fw_file_path;
++	extern char *rtw_fw_wow_file_path;
++	#ifdef CONFIG_MP_INCLUDED
++		extern char *rtw_fw_mp_bt_file_path;
++	#endif /* CONFIG_MP_INCLUDED */
++#endif /* CONFIG_FILE_FWIMG */
++
++/* rtl8192f_hal_init.c */
++s32 rtl8192f_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
++void rtl8192f_FirmwareSelfReset(PADAPTER padapter);
++void rtl8192f_InitializeFirmwareVars(PADAPTER padapter);
++
++void rtl8192f_InitAntenna_Selection(PADAPTER padapter);
++void rtl8192f_DeinitAntenna_Selection(PADAPTER padapter);
++void rtl8192f_CheckAntenna_Selection(PADAPTER padapter);
++void rtl8192f_init_default_value(PADAPTER padapter);
++
++s32 rtl8192f_InitLLTTable(PADAPTER padapter);
++
++s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
++s32 CardDisableWithoutHWSM(PADAPTER padapter);
++
++/* EFuse */
++u8 GetEEPROMSize8192F(PADAPTER padapter);
++void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
++void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
++void Hal_EfuseParseTxPowerInfo_8192F(PADAPTER padapter,
++					u8 *PROMContent, BOOLEAN AutoLoadFail);
++#ifdef CONFIG_BT_COEXIST
++void Hal_EfuseParseBTCoexistInfo_8192F(PADAPTER padapter,
++				       u8 *hwinfo, BOOLEAN AutoLoadFail);
++#endif /* CONFIG_BT_COEXIST */
++void Hal_EfuseParseEEPROMVer_8192F(PADAPTER padapter,
++				   u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseChnlPlan_8192F(PADAPTER padapter,
++				  u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseCustomerID_8192F(PADAPTER padapter,
++				    u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseAntennaDiversity_8192F(PADAPTER padapter,
++		u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseXtal_8192F(PADAPTER pAdapter,
++			      u8 *hwinfo, u8 AutoLoadFail);
++void Hal_EfuseParseThermalMeter_8192F(PADAPTER padapter,
++				      u8 *hwinfo, u8 AutoLoadFail);
++void Hal_EfuseParseVoltage_8192F(PADAPTER pAdapter,
++				 u8 *hwinfo, BOOLEAN	AutoLoadFail);
++void Hal_EfuseParseBoardType_8192F(PADAPTER Adapter,
++				   u8	*PROMContent, BOOLEAN AutoloadFail);
++u8	Hal_ReadRFEType_8192F(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
++void rtl8192f_set_hal_ops(struct hal_ops *pHalFunc);
++void init_hal_spec_8192f(_adapter *adapter);
++u8 SetHwReg8192F(PADAPTER padapter, u8 variable, u8 *val);
++void GetHwReg8192F(PADAPTER padapter, u8 variable, u8 *val);
++u8 SetHalDefVar8192F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
++u8 GetHalDefVar8192F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
++
++/* register */
++void rtl8192f_InitBeaconParameters(PADAPTER padapter);
++void rtl8192f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
++
++void _InitMacAPLLSetting_8192F(PADAPTER Adapter);
++void _8051Reset8192F(PADAPTER padapter);
++#ifdef CONFIG_WOWLAN
++	void Hal_DetectWoWMode(PADAPTER pAdapter);
++#endif /* CONFIG_WOWLAN */
++
++void rtl8192f_start_thread(_adapter *padapter);
++void rtl8192f_stop_thread(_adapter *padapter);
++
++#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
++	void rtl8192fs_init_checkbthang_workqueue(_adapter *adapter);
++	void rtl8192fs_free_checkbthang_workqueue(_adapter *adapter);
++	void rtl8192fs_cancle_checkbthang_workqueue(_adapter *adapter);
++	void rtl8192fs_hal_check_bt_hang(_adapter *adapter);
++#endif
++
++#ifdef CONFIG_GPIO_WAKEUP
++	void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
++#endif
++#ifdef CONFIG_MP_INCLUDED
++int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
++#endif
++void CCX_FwC2HTxRpt_8192f(PADAPTER padapter, u8 *pdata, u8 len);
++
++u8 MRateToHwRate8192F(u8 rate);
++u8 HwRateToMRate8192F(u8 rate);
++
++#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
++	void check_bt_status_work(void *data);
++#endif
++
++
++void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc);
++
++#ifdef CONFIG_AMPDU_PRETX_CD
++void rtl8192f_pretx_cd_config(_adapter *adapter);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	BOOLEAN	InterruptRecognized8192FE(PADAPTER Adapter);
++	void	UpdateInterruptMask8192FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
++	void InitMAC_TRXBD_8192FE(PADAPTER Adapter);
++
++	u16 get_txbd_rw_reg(u16 ff_hwaddr);
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_led.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_led.h
+new file mode 100644
+index 000000000..0dbb27cd0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_led.h
+@@ -0,0 +1,59 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8192F_LED_H__
++#define __RTL8192F_LED_H__
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++#ifdef CONFIG_RTW_SW_LED
++/* ********************************************************************************
++ * Interface to manipulate LED objects.
++ * ******************************************************************************** */
++#ifdef CONFIG_USB_HCI
++/** REG_LED_CFG (0x4C) **/
++/* LED0 GPIO Enable, 0: disable, 1: enable*/
++#define LED0_GPIO_ENABLE_8192FU (BIT21)
++/* LED0 Disabled for analog signal usage, 0:Enable (output mode), 1: disable (input mode) */
++#define LED0_DISABLE_ANALOGSIGNAL_8192FU (BIT7)
++/* LED0 software value, 0: turn off, 1:turn on */
++#define LED0_SW_VALUE_8192FU (BIT3)
++
++/** REG_GPIO_MUXCFG (0x40) **/
++/* Enable LED[1:0] for RFE CTRL[7:6], 0: BT, 1: Wi-Fi */
++#define ENABLE_LED0_AND_LED1_CTRL_BY_WIFI_8192FU (BIT3)
++
++/** REG_SW_GPIO_SHARE_CTRL_0 (0x1038) **/
++/* LED Output PIN Location, 0: GPIOA_0, 1:GPIOB_4*/
++#define LED_OUTPUT_PIN_LOCATION_8192FU (BIT16)
++
++u8 rtl8192fu_CfgLed0Hw(PADAPTER padapter);
++void rtl8192fu_InitSwLeds(PADAPTER padapter);
++void rtl8192fu_DeInitSwLeds(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_SDIO_HCI
++void rtl8192fs_InitSwLeds(PADAPTER padapter);
++void rtl8192fs_DeInitSwLeds(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++void rtl8192fe_InitSwLeds(PADAPTER padapter);
++void rtl8192fe_DeInitSwLeds(PADAPTER padapter);
++#endif
++#endif /*#ifdef CONFIG_RTW_SW_LED*/
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_recv.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_recv.h
+new file mode 100644
+index 000000000..9fb931a7f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_recv.h
+@@ -0,0 +1,107 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8192F_RECV_H__
++#define __RTL8192F_RECV_H__
++
++#define RECV_BLK_SZ 512
++#define RECV_BLK_CNT 16
++#define RECV_BLK_TH RECV_BLK_CNT
++
++#if defined(CONFIG_USB_HCI)
++
++	#ifndef MAX_RECVBUF_SZ
++		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
++			/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
++			/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
++			/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
++			#ifdef CONFIG_PLATFORM_MSTAR
++				#define MAX_RECVBUF_SZ (8192) /* 8K */
++			#else
++				#define MAX_RECVBUF_SZ (32768) /* 32k */
++			#endif
++			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
++		#else
++			#define MAX_RECVBUF_SZ (4000) /* about 4K */
++		#endif
++	#endif /* !MAX_RECVBUF_SZ */
++
++#elif defined(CONFIG_PCI_HCI)
++	#define MAX_RECVBUF_SZ (4000) /* about 4K */
++
++#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++
++	#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8192F + 1)
++
++#endif
++
++/* Rx smooth factor */
++#define	Rx_Smooth_Factor (20)
++
++#ifdef CONFIG_SDIO_HCI
++	#ifndef CONFIG_SDIO_RX_COPY
++		#undef MAX_RECVBUF_SZ
++		#define MAX_RECVBUF_SZ	(RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F)
++	#endif /* !CONFIG_SDIO_RX_COPY */
++#endif /* CONFIG_SDIO_HCI */
++
++/*-----------------------------------------------------------------*/
++/*	RTL8192F RX BUFFER DESC                                      */
++/*-----------------------------------------------------------------*/
++/*DWORD 0*/
++#define SET_RX_BUFFER_DESC_DATA_LENGTH_8192F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
++#define SET_RX_BUFFER_DESC_LS_8192F(__pRxStatusDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
++#define SET_RX_BUFFER_DESC_FS_8192F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
++#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8192F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
++
++#define GET_RX_BUFFER_DESC_OWN_8192F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
++#define GET_RX_BUFFER_DESC_LS_8192F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
++#define GET_RX_BUFFER_DESC_FS_8192F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
++#ifdef USING_RX_TAG
++	#define GET_RX_BUFFER_DESC_RX_TAG_8192F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13)
++#else
++	#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8192F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
++#endif
++
++/*DWORD 1*/
++#define SET_RX_BUFFER_PHYSICAL_LOW_8192F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
++
++/*DWORD 2*/
++#ifdef CONFIG_64BIT_DMA
++	#define SET_RX_BUFFER_PHYSICAL_HIGH_8192F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
++#else
++	#define SET_RX_BUFFER_PHYSICAL_HIGH_8192F(__pRxStatusDesc, __Value)
++#endif
++
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	s32 rtl8192fs_init_recv_priv(PADAPTER padapter);
++	void rtl8192fs_free_recv_priv(PADAPTER padapter);
++	s32 rtl8192fs_recv_hdl(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_USB_HCI
++	int rtl8192fu_init_recv_priv(_adapter *padapter);
++	void rtl8192fu_free_recv_priv(_adapter *padapter);
++	void rtl8192fu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	s32 rtl8192fe_init_recv_priv(_adapter *padapter);
++	void rtl8192fe_free_recv_priv(_adapter *padapter);
++#endif
++
++void rtl8192f_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
++
++#endif /* __RTL8192F_RECV_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_rf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_rf.h
+new file mode 100644
+index 000000000..b3016bb2f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_rf.h
+@@ -0,0 +1,88 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2012 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8192F_RF_H__
++#define __RTL8192F_RF_H__
++
++/*default*/
++/*#define CONFIG_8192F_DRV_DIS*/
++/*AP*/
++#define CONFIG_8192F_TYPE3_DRV_DIS
++#define CONFIG_8192F_TYPE4_DRV_DIS
++/*unused*/
++#define CONFIG_8192F_TYPE15_DRV_DIS
++#define CONFIG_8192F_TYPE16_DRV_DIS
++#define CONFIG_8192F_TYPE17_DRV_DIS
++#define CONFIG_8192F_TYPE18_DRV_DIS
++#define CONFIG_8192F_TYPE19_DRV_DIS
++#define CONFIG_8192F_TYPE20_DRV_DIS
++#define CONFIG_8192F_TYPE21_DRV_DIS
++#define CONFIG_8192F_TYPE22_DRV_DIS
++#define CONFIG_8192F_TYPE23_DRV_DIS
++#define CONFIG_8192F_TYPE24_DRV_DIS
++#define CONFIG_8192F_TYPE25_DRV_DIS
++#define CONFIG_8192F_TYPE26_DRV_DIS
++#define CONFIG_8192F_TYPE27_DRV_DIS
++#define CONFIG_8192F_TYPE28_DRV_DIS
++#define CONFIG_8192F_TYPE29_DRV_DIS
++#define CONFIG_8192F_TYPE30_DRV_DIS
++#define CONFIG_8192F_TYPE31_DRV_DIS
++
++
++#ifdef CONFIG_SDIO_HCI /**/
++/*usb*/
++#define CONFIG_8192F_TYPE1_DRV_DIS
++#define CONFIG_8192F_TYPE5_DRV_DIS
++#define CONFIG_8192F_TYPE10_DRV_DIS
++#define CONFIG_8192F_TYPE13_DRV_DIS
++#define CONFIG_8192F_TYPE14_DRV_DIS
++/*pcie*/
++#define CONFIG_8192F_TYPE0_DRV_DIS
++#define CONFIG_8192F_TYPE6_DRV_DIS
++#define CONFIG_8192F_TYPE7_DRV_DIS
++#define CONFIG_8192F_TYPE8_DRV_DIS
++#define CONFIG_8192F_TYPE9_DRV_DIS
++#define CONFIG_8192F_TYPE12_DRV_DIS
++#endif/*CONFIG_SDIO_HCI*/
++
++#ifdef CONFIG_USB_HCI
++/*sdio*/
++#define CONFIG_8192F_TYPE2_DRV_DIS
++#define CONFIG_8192F_TYPE11_DRV_DIS
++/*pcie*/
++#define CONFIG_8192F_TYPE0_DRV_DIS
++#define CONFIG_8192F_TYPE6_DRV_DIS
++#define CONFIG_8192F_TYPE7_DRV_DIS
++#define CONFIG_8192F_TYPE8_DRV_DIS
++#define CONFIG_8192F_TYPE9_DRV_DIS
++#define CONFIG_8192F_TYPE12_DRV_DIS
++#endif/*CONFIG_USB_HCI*/
++
++#ifdef CONFIG_PCI_HCI
++/*sdio*/
++#define CONFIG_8192F_TYPE2_DRV_DIS
++#define CONFIG_8192F_TYPE11_DRV_DIS
++/*usb*/
++#define CONFIG_8192F_TYPE1_DRV_DIS
++#define CONFIG_8192F_TYPE5_DRV_DIS
++#define CONFIG_8192F_TYPE10_DRV_DIS
++#define CONFIG_8192F_TYPE13_DRV_DIS
++#define CONFIG_8192F_TYPE14_DRV_DIS
++#endif/*CONFIG_PCI_HCI*/
++
++int PHY_RF6052_Config8192F(PADAPTER pdapter);
++
++void PHY_RF6052SetBandwidth8192F(PADAPTER Adapter, enum channel_width Bandwidth);
++
++#endif/* __RTL8192F_RF_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_spec.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_spec.h
+new file mode 100644
+index 000000000..b34d94483
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_spec.h
+@@ -0,0 +1,541 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8192F_SPEC_H__
++#define __RTL8192F_SPEC_H__
++
++#include <drv_conf.h>
++
++
++#define HAL_NAV_UPPER_UNIT_8192F		128		/* micro-second */
++
++/* -----------------------------------------------------
++ *
++ *	0x0000h ~ 0x00FFh	System Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_SYS_ISO_CTRL_8192F			0x0000	/* 2 Byte */
++#define REG_SYS_FUNC_EN_8192F			0x0002	/* 2 Byte */
++#define REG_APS_FSMCO_8192F			0x0004	/* 4 Byte */
++#define REG_SYS_CLKR_8192F				0x0008	/* 2 Byte */
++#define REG_9346CR_8192F				0x000A	/* 2 Byte */
++#define REG_EE_VPD_8192F				0x000C	/* 2 Byte */
++#define REG_AFE_MISC_8192F				0x0010	/* 1 Byte */
++#define REG_SPS0_CTRL_8192F				0x0011	/* 7 Byte */
++#define REG_SPS_OCP_CFG_8192F			0x0018	/* 4 Byte */
++#define REG_RSV_CTRL_8192F				0x001C	/* 3 Byte */
++#define REG_RF_CTRL_8192F				0x001F	/* 1 Byte */
++#define REG_LPLDO_CTRL_8192F			0x0023	/* 1 Byte */
++#define REG_AFE_XTAL_CTRL_8192F		0x0024	/* 4 Byte */
++#define REG_AFE_PLL_CTRL_8192F			0x0028	/* 4 Byte */
++#define REG_MAC_PLL_CTRL_EXT_8192F		0x002c	/* 4 Byte */
++#define REG_EFUSE_CTRL_8192F			0x0030
++#define REG_EFUSE_TEST_8192F			0x0034
++#define REG_PWR_DATA_8192F				0x0038
++#define REG_CAL_TIMER_8192F				0x003C
++#define REG_ACLK_MON_8192F				0x003E
++#define REG_GPIO_MUXCFG_8192F			0x0040
++#define REG_GPIO_IO_SEL_8192F			0x0042
++#define REG_MAC_PINMUX_CFG_8192F		0x0043
++#define REG_GPIO_PIN_CTRL_8192F			0x0044
++#define REG_GPIO_INTM_8192F				0x0048
++#define REG_LEDCFG0_8192F				0x004C
++#define REG_LEDCFG1_8192F				0x004D
++#define REG_LEDCFG2_8192F				0x004E
++#define REG_LEDCFG3_8192F				0x004F
++#define REG_FSIMR_8192F					0x0050
++#define REG_FSISR_8192F					0x0054
++#define REG_HSIMR_8192F					0x0058
++#define REG_HSISR_8192F					0x005c
++#define REG_GPIO_EXT_CTRL				0x0060
++#define REG_PAD_CTRL1_8192F		0x0064
++#define REG_MULTI_FUNC_CTRL_8192F		0x0068
++#define REG_GPIO_STATUS_8192F			0x006C
++#define REG_SDIO_CTRL_8192F				0x0070
++#define REG_OPT_CTRL_8192F				0x0074
++#define REG_AFE_CTRL_4_8192F		0x0078
++#define REG_MCUFWDL_8192F				0x0080
++#define REG_8051FW_CTRL_8192F			0x0080
++#define REG_HMEBOX_DBG_0_8192F	0x0088
++#define REG_HMEBOX_DBG_1_8192F	0x008A
++#define REG_HMEBOX_DBG_2_8192F	0x008C
++#define REG_HMEBOX_DBG_3_8192F	0x008E
++#define REG_WLLPS_CTRL		0x0090
++#define REG_HIMR0_8192F					0x00B0
++#define REG_HISR0_8192F				0x00B4
++#define REG_HIMR1_8192F					0x00B8
++#define REG_HISR1_8192F					0x00BC
++#define REG_PMC_DBG_CTRL2_8192F			0x00CC
++#define	REG_EFUSE_BURN_GNT_8192F		0x00CF
++#define REG_HPON_FSM_8192F				0x00EC
++#define REG_SYS_CFG1_8192F				0x00F0
++#define REG_SYS_CFG2_8192F				0x00FC
++#define REG_ROM_VERSION					0x00FD
++
++/* -----------------------------------------------------
++ *
++ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_CR_8192F						0x0100
++#define REG_PBP_8192F					0x0104
++#define REG_PKT_BUFF_ACCESS_CTRL_8192F	0x0106
++#define REG_TRXDMA_CTRL_8192F			0x010C
++#define REG_TRXFF_BNDY_8192F			0x0114
++#define REG_TRXFF_STATUS_8192F			0x0118
++#define REG_RXFF_PTR_8192F				0x011C
++#define REG_CPWM_8192F					0x012C
++#define REG_FWIMR_8192F					0x0130
++#define REG_FWISR_8192F					0x0134
++#define REG_FTIMR_8192F					0x0138
++#define REG_PKTBUF_DBG_CTRL_8192F		0x0140
++#define REG_RXPKTBUF_CTRL_8192F		0x0142
++#define REG_PKTBUF_DBG_DATA_L_8192F	0x0144
++#define REG_PKTBUF_DBG_DATA_H_8192F	0x0148
++
++#define REG_TC0_CTRL_8192F				0x0150
++#define REG_TC1_CTRL_8192F				0x0154
++#define REG_TC2_CTRL_8192F				0x0158
++#define REG_TC3_CTRL_8192F				0x015C
++#define REG_TC4_CTRL_8192F				0x0160
++#define REG_TCUNIT_BASE_8192F			0x0164
++#define REG_RSVD3_8192F					0x0168
++#define REG_C2HEVT_CMD_ID_8192F	0x01A0
++#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
++#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
++#define REG_C2HEVT_CMD_LEN_8192F        0x01AE
++#define REG_C2HEVT_CLEAR_8192F			0x01AF
++#define REG_TXBUF_WKCAM_OFFSET			0x01B1  /* RTL8192F */
++#define REG_MCUTST_1_8192F				0x01C0
++#define REG_WOWLAN_WAKE_REASON 0x01C7
++#define REG_FMETHR_8192F				0x01C8
++#define REG_HMETFR_8192F				0x01CC
++#define REG_HMEBOX_0_8192F				0x01D0
++#define REG_HMEBOX_1_8192F				0x01D4
++#define REG_HMEBOX_2_8192F				0x01D8
++#define REG_HMEBOX_3_8192F				0x01DC
++#define REG_LLT_INIT_8192F				0x01E0
++#define REG_HMEBOX_EXT0_8192F			0x01F0
++#define REG_HMEBOX_EXT1_8192F			0x01F4
++#define REG_HMEBOX_EXT2_8192F			0x01F8
++#define REG_HMEBOX_EXT3_8192F			0x01FC
++
++/* -----------------------------------------------------
++ *
++ *	0x0200h ~ 0x027Fh	TXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_RQPN_8192F					0x0200
++#define REG_FIFOPAGE_8192F				0x0204
++#define REG_DWBCN0_CTRL_8192F			REG_TDECTRL
++#define REG_TXDMA_OFFSET_CHK_8192F	0x020C
++#define REG_TXDMA_STATUS_8192F		0x0210
++#define REG_RQPN_NPQ_8192F			0x0214
++#define REG_DWBCN1_CTRL_8192F			0x0228
++#define REG_RQPN_EXQ1_EXQ2			0x0230
++#define REG_TQPNT3_V1_8192F			0x0234
++
++/* -----------------------------------------------------
++ *
++ *	0x0280h ~ 0x02FFh	RXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_RXDMA_AGG_PG_TH_8192F		0x0280
++#define REG_FW_UPD_RDPTR_8192F		0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
++#define REG_RXDMA_CONTROL_8192F		0x0286 /* Control the RX DMA. */
++#define REG_RXDMA_STATUS_8192F			0x0288
++#define REG_RXDMA_MODE_CTRL_8192F		0x0290
++#define REG_EARLY_MODE_CONTROL_8192F	0x02BC
++#define REG_RSVD5_8192F					0x02F0
++#define REG_RSVD6_8192F					0x02F4
++
++/* -----------------------------------------------------
++ *
++ *	0x0300h ~ 0x03FFh	PCIe
++ *
++ * ----------------------------------------------------- */
++#define	REG_PCIE_CTRL_REG_8192F		0x0300
++#define	REG_INT_MIG_8192F				0x0304	/* Interrupt Migration */
++#define	REG_BCNQ_TXBD_DESA_8192F		0x0308	/* TX Beacon Descriptor Address */
++#define	REG_MGQ_TXBD_DESA_8192F			0x0310	/* TX Manage Queue Descriptor Address */
++#define	REG_VOQ_TXBD_DESA_8192F			0x0318	/* TX VO Queue Descriptor Address */
++#define	REG_VIQ_TXBD_DESA_8192F			0x0320	/* TX VI Queue Descriptor Address */
++#define	REG_BEQ_TXBD_DESA_8192F			0x0328	/* TX BE Queue Descriptor Address */
++#define	REG_BKQ_TXBD_DESA_8192F			0x0330	/* TX BK Queue Descriptor Address */
++#define	REG_RXQ_RXBD_DESA_8192F			0x0338	/* RX Queue	Descriptor Address */
++#define REG_HI0Q_TXBD_DESA_8192F		0x0340
++#define REG_HI1Q_TXBD_DESA_8192F		0x0348
++#define REG_HI2Q_TXBD_DESA_8192F		0x0350
++#define REG_HI3Q_TXBD_DESA_8192F		0x0358
++#define REG_HI4Q_TXBD_DESA_8192F		0x0360
++#define REG_HI5Q_TXBD_DESA_8192F		0x0368
++#define REG_HI6Q_TXBD_DESA_8192F		0x0370
++#define REG_HI7Q_TXBD_DESA_8192F		0x0378
++#define	REG_MGQ_TXBD_NUM_8192F			0x0380
++#define	REG_RX_RXBD_NUM_8192F			0x0382
++#define	REG_VOQ_TXBD_NUM_8192F			0x0384
++#define	REG_VIQ_TXBD_NUM_8192F			0x0386
++#define	REG_BEQ_TXBD_NUM_8192F			0x0388
++#define	REG_BKQ_TXBD_NUM_8192F			0x038A
++#define	REG_HI0Q_TXBD_NUM_8192F			0x038C
++#define	REG_HI1Q_TXBD_NUM_8192F			0x038E
++#define	REG_HI2Q_TXBD_NUM_8192F			0x0390
++#define	REG_HI3Q_TXBD_NUM_8192F			0x0392
++#define	REG_HI4Q_TXBD_NUM_8192F			0x0394
++#define	REG_HI5Q_TXBD_NUM_8192F			0x0396
++#define	REG_HI6Q_TXBD_NUM_8192F			0x0398
++#define	REG_HI7Q_TXBD_NUM_8192F			0x039A
++#define	REG_TSFTIMER_HCI_8192F			0x039C
++#define	REG_BD_RW_PTR_CLR_8192F			0x039C
++
++/* Read Write Point */
++#define	REG_VOQ_TXBD_IDX_8192F			0x03A0
++#define	REG_VIQ_TXBD_IDX_8192F			0x03A4
++#define	REG_BEQ_TXBD_IDX_8192F			0x03A8
++#define	REG_BKQ_TXBD_IDX_8192F			0x03AC
++#define	REG_MGQ_TXBD_IDX_8192F			0x03B0
++#define	REG_RXQ_TXBD_IDX_8192F			0x03B4
++#define	REG_HI0Q_TXBD_IDX_8192F			0x03B8
++#define	REG_HI1Q_TXBD_IDX_8192F			0x03BC
++#define	REG_HI2Q_TXBD_IDX_8192F			0x03C0
++#define	REG_HI3Q_TXBD_IDX_8192F			0x03C4
++#define	REG_HI4Q_TXBD_IDX_8192F			0x03C8
++#define	REG_HI5Q_TXBD_IDX_8192F			0x03CC
++#define	REG_HI6Q_TXBD_IDX_8192F			0x03D0
++#define	REG_HI7Q_TXBD_IDX_8192F			0x03D4
++#define	REG_DBI_WDATA_V1_8192F			0x03E8
++#define	REG_DBI_RDATA_V1_8192F			0x03EC
++#define	REG_DBI_FLAG_V1_8192F			0x03F0
++#define REG_MDIO_V1_8192F			0x03F4
++#define REG_HCI_MIX_CFG_8192F			0x03FC
++#define REG_PCIE_HCPWM_8192FE				0x03D8
++#define REG_PCIE_HRPWM_8192FE				0x03DC
++#define REG_PCIE_MIX_CFG_8192F				0x03F8
++
++/* -----------------------------------------------------
++ *
++ *	0x0400h ~ 0x047Fh	Protocol Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_QUEUELIST_INFO0_8192F		0x0400
++#define REG_QUEUELIST_INFO1_8192F		0x0404
++#define REG_QUEUELIST_INFO2_8192F		0x0414
++#define REG_TXPKT_EMPTY_8192F			0x0418
++
++#define REG_FWHW_TXQ_CTRL_8192F		0x0420
++#define REG_HWSEQ_CTRL_8192F			0x0423
++#define REG_TXPKTBUF_BCNQ_BDNY_8192F	0x0424
++#define REG_TXPKTBUF_MGQ_BDNY_8192F	0x0425
++#define REG_LIFECTRL_CTRL_8192F			0x0426
++#define REG_MULTI_BCNQ_OFFSET_8192F	0x0427
++#define REG_SPEC_SIFS_8192F				0x0428
++#define REG_RL_8192F						0x042A
++#define REG_TXBF_CTRL_8192F				0x042C
++#define REG_DARFRC_8192F				0x0430
++#define REG_RARFRC_8192F				0x0438
++#define REG_RRSR_8192F					0x0440
++#define REG_ARFR0_8192F					0x0444
++#define REG_ARFR1_8192F					0x044C
++#define REG_CCK_CHECK_8192F				0x0454
++#define REG_AMPDU_MAX_TIME_8192F		0x0456
++#define REG_TXPKTBUF_BCNQ_BDNY1_8192F	0x0457
++
++#define REG_AMPDU_MAX_LENGTH_8192F	0x0458
++#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8192F	0x045D
++#define REG_NDPA_OPT_CTRL_8192F		0x045F
++#define REG_FAST_EDCA_CTRL_8192F		0x0460
++#define REG_RD_RESP_PKT_TH_8192F		0x0463
++#define REG_DATA_SC_8192F				0x0483
++#define REG_TXRPT_START_OFFSET		0x04AC
++#define REG_POWER_STAGE1_8192F		0x04B4
++#define REG_POWER_STAGE2_8192F		0x04B8
++#define REG_AMPDU_BURST_MODE_8192F	0x04BC
++#define REG_PKT_VO_VI_LIFE_TIME_8192F	0x04C0
++#define REG_PKT_BE_BK_LIFE_TIME_8192F	0x04C2
++#define REG_STBC_SETTING_8192F			0x04C4
++#define REG_HT_SINGLE_AMPDU_8192F		0x04C7
++#define REG_PROT_MODE_CTRL_8192F		0x04C8
++#define REG_MAX_AGGR_NUM_8192F		0x04CA
++#define REG_RTS_MAX_AGGR_NUM_8192F	0x04CB
++#define REG_BAR_MODE_CTRL_8192F		0x04CC
++#define REG_RA_TRY_RATE_AGG_LMT_8192F	0x04CF
++#define REG_MACID_PKT_DROP0_8192F		0x04D0
++#define REG_MACID_PKT_SLEEP_8192F		0x04D4
++#define REG_PRECNT_CTRL_8192F			0x04E5
++/* -----------------------------------------------------
++ *
++ *	0x0500h ~ 0x05FFh	EDCA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_EDCA_VO_PARAM_8192F		0x0500
++#define REG_EDCA_VI_PARAM_8192F		0x0504
++#define REG_EDCA_BE_PARAM_8192F		0x0508
++#define REG_EDCA_BK_PARAM_8192F		0x050C
++#define REG_BCNTCFG_8192F				0x0510
++#define REG_PIFS_8192F					0x0512
++#define REG_RDG_PIFS_8192F				0x0513
++#define REG_SIFS_CTX_8192F				0x0514
++#define REG_SIFS_TRX_8192F				0x0516
++#define REG_AGGR_BREAK_TIME_8192F		0x051A
++#define REG_SLOT_8192F					0x051B
++#define REG_TX_PTCL_CTRL_8192F			0x0520
++#define REG_TXPAUSE_8192F				0x0522
++#define REG_DIS_TXREQ_CLR_8192F		0x0523
++#define REG_RD_CTRL_8192F				0x0524
++/*
++ * Format for offset 540h-542h:
++ *	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
++ *	[7:4]:   Reserved.
++ *	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
++ *	[23:20]: Reserved
++ * Description:
++ *	              |
++ * |<--Setup--|--Hold------------>|
++ *	--------------|----------------------
++ * |
++ * TBTT
++ * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
++ * Described by Designer Tim and Bruce, 2011-01-14.
++ *   */
++#define REG_TBTT_PROHIBIT_8192F			0x0540
++#define REG_RD_NAV_NXT_8192F			0x0544
++#define REG_NAV_PROT_LEN_8192F			0x0546
++#define REG_BCN_CTRL_8192F				0x0550
++#define REG_BCN_CTRL_1_8192F			0x0551
++#define REG_MBID_NUM_8192F				0x0552
++#define REG_DUAL_TSF_RST_8192F			0x0553
++#define REG_BCN_INTERVAL_8192F			0x0554
++#define REG_DRVERLYINT_8192F			0x0558
++#define REG_BCNDMATIM_8192F			0x0559
++#define REG_ATIMWND_8192F				0x055A
++#define REG_USTIME_TSF_8192F			0x055C
++#define REG_BCN_MAX_ERR_8192F			0x055D
++#define REG_RXTSF_OFFSET_CCK_8192F		0x055E
++#define REG_RXTSF_OFFSET_OFDM_8192F	0x055F	
++#define REG_TSFTR_8192F					0x0560
++#define REG_CTWND_8192F					0x0572
++#define REG_SECONDARY_CCA_CTRL_8192F	0x0577
++#define REG_PSTIMER_8192F				0x0580
++#define REG_TIMER0_8192F				0x0584
++#define REG_TIMER1_8192F				0x0588
++#define REG_ACMHWCTRL_8192F			0x05C0
++#define REG_SCH_TXCMD_8192F			0x05F8
++
++/* -----------------------------------------------------
++ *
++ *	0x0600h ~ 0x07FFh	WMAC Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_MAC_CR_8192F				0x0600
++#define REG_TCR_8192F					0x0604
++#define REG_RCR_8192F					0x0608
++#define REG_RX_PKT_LIMIT_8192F			0x060C
++#define REG_RX_DLK_TIME_8192F			0x060D
++#define REG_RX_DRVINFO_SZ_8192F	0x060F
++
++#define REG_MACID_8192F					0x0610
++#define REG_BSSID_8192F					0x0618
++#define REG_MAR_8192F					0x0620
++#define REG_MBIDCAMCFG_8192F			0x0628
++
++
++#define REG_USTIME_EDCA_8192F			0x0638
++#define REG_MAC_SPEC_SIFS_8192F		0x063A
++#define REG_RESP_SIFP_CCK_8192F			0x063C
++#define REG_RESP_SIFS_OFDM_8192F		0x063E
++#define REG_ACKTO_8192F					0x0640
++#define REG_CTS2TO_8192F				0x0641
++#define REG_EIFS_8192F					0x0642
++
++#define REG_NAV_UPPER_8192F			0x0652	/* unit of 128*/
++#define REG_TRXPTCL_CTL_8192F			0x0668
++
++/* Security*/
++#define REG_CAMCMD_8192F				0x0670
++#define REG_CAMWRITE_8192F				0x0674
++#define REG_CAMREAD_8192F				0x0678
++#define REG_CAMDBG_8192F				0x067C
++#define REG_SECCFG_8192F				0x0680
++
++/* Power */
++#define REG_WOW_CTRL_8192F				0x0690
++#define REG_PS_RX_INFO_8192F			0x0692
++#define REG_UAPSD_TID_8192F				0x0693
++#define REG_WKFMCAM_CMD_8192F			0x0698
++#define REG_WKFMCAM_NUM_8192F			0x0698
++#define REG_WKFMCAM_RWD_8192F			0x069C
++#define REG_RXFLTMAP0_8192F				0x06A0
++#define REG_RXFLTMAP1_8192F				0x06A2
++#define REG_RXFLTMAP2_8192F				0x06A4
++#define REG_BCN_PSR_RPT_8192F			0x06A8
++#define REG_BT_COEX_TABLE_8192F		0x06C0
++#define REG_BFMER0_INFO_8192F			0x06E4
++#define REG_BFMER1_INFO_8192F			0x06EC
++#define REG_CSI_RPT_PARAM_BW20_8192F	0x06F4
++#define REG_CSI_RPT_PARAM_BW40_8192F	0x06F8
++#define REG_CSI_RPT_PARAM_BW80_8192F	0x06FC
++
++/* Hardware Port 2 */
++#define REG_MACID1_8192F				0x0700
++#define REG_BSSID1_8192F				0x0708
++#define REG_BFMEE_SEL_8192F				0x0714
++#define REG_SND_PTCL_CTRL_8192F		0x0718
++
++/* LTR */
++#define REG_LTR_CTRL_BASIC_8192F		0x07A4
++#define REG_LTR_IDLE_LATENCY_V1_8192F		0x0798
++#define REG_LTR_ACTIVE_LATENCY_V1_8192F	0x079C
++
++/* GPIO Control */
++#define REG_SW_GPIO_SHARE_CTRL_8192F_0	0x1038
++#define REG_SW_GPIO_SHARE_CTRL_8192F_1	0x103c
++#define REG_SW_GPIO_A_OUT_8192F			0x1040
++#define REG_SW_GPIO_A_OEN_8192F			0x1044
++
++/* ************************************************************
++ * SDIO Bus Specification
++ * ************************************************************ */
++
++/* -----------------------------------------------------
++ * SDIO CMD Address Mapping
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ * I/O bus domain (Host)
++ * ----------------------------------------------------- */
++/*SDIO Host Interrupt Mask Register */
++#define SDIO_HIMR_CRCERR_MSK			BIT(31)
++/* SDIO Host Interrupt Service Routine */
++#define SDIO_HISR_HEISR_IND_INT		BIT(28)
++#define SDIO_HISR_HSISR2_IND_INT		BIT(29)
++#define SDIO_HISR_HSISR3_IND_INT		BIT(30)
++#define SDIO_HISR_SDIO_CRCERR			BIT(31)
++/* -----------------------------------------------------
++ * SDIO register
++ * ----------------------------------------------------- */
++#define SDIO_REG_HCPWM1_8192F	0x038/* HCI Current Power Mode 1 */
++#define SDIO_REG_FREE_TXPG1_8192F		0x0020 /* Free Tx Buffer Page1*/
++#define SDIO_REG_FREE_TXPG2_8192F		0x0024 /* Free Tx Buffer Page1*/
++#define SDIO_REG_FREE_TXPG3_8192F		0x0028
++#define SDIO_REG_AC_OQT_FREEPG_8192F		0x002A
++#define SDIO_REG_NOAC_OQT_FREEPG_8192F		0x002B
++/* ****************************************************************************
++ *	8192F Regsiter Bit and Content definition
++ * **************************************************************************** */
++
++#define BIT_USB_RXDMA_AGG_EN	BIT(31)
++#define RXDMA_AGG_MODE_EN		BIT(1)
++
++#ifdef CONFIG_WOWLAN
++	#define RXPKT_RELEASE_POLL		BIT(16)
++	#define RXDMA_IDLE				BIT(17)
++	#define RW_RELEASE_EN			BIT(18)
++#endif
++
++#ifdef CONFIG_AMPDU_PRETX_CD
++/*#define BIT_ERRORHDL_INT			BIT(2)*/
++/*#define BIT_MACTX_ERR_3			BIT(4)*/
++#define BIT_PRE_TX_CMD_8192F		BIT(6)
++#define BIT_EN_PRECNT_8192F		BIT(11)
++#endif
++/* SDIO Host Interrupt Service Routine */
++#define SDIO_HISR_HEISR_IND_INT	BIT(28)
++#define SDIO_HISR_HSISR2_IND_INT	BIT(29)
++#define SDIO_HISR_HSISR3_IND_INT	BIT(30)
++#define SDIO_HISR_SDIO_CRCERR		BIT(31)
++
++/* PCIE Host Interrupt Mask Register (HIMR) */
++#ifdef CONFIG_PCI_HCI
++/* ----------------------------------------------------------------------------
++ *   * 8192F IMR/ISR bits							(offset 0xB0,  8bits)
++ *     * ---------------------------------------------------------------------------- */
++
++#define IMR_DISABLED_8192F					0
++/* IMR DW0(0x00B0-00B3) Bit 0-31 */
++#define IMR_TIMER2_8192F					BIT(31)         /* Timeout interrupt 2 */
++#define IMR_TIMER1_8192F					BIT(30)		/* Timeout interrupt 1 */
++#define IMR_PSTIMEOUT_8192F				BIT(29)		/* Power Save Time Out Interrupt */
++#define IMR_GTINT4_8192F					BIT(28)		/* When GTIMER4 expires, this bit is set to 1 */
++#define IMR_GTINT3_8192F					BIT(27)		/* When GTIMER3 expires, this bit is set to 1 */
++#define IMR_TXBCN0ERR_8192F				BIT(26)		/* Transmit Beacon0 Error */
++#define IMR_TXBCN0OK_8192F				BIT(25)		/* Transmit Beacon0 OK */
++#define IMR_TSF_BIT32_TOGGLE_8192F		BIT(24)		/* TSF Timer BIT32 toggle indication interrupt */
++#define IMR_BCNDMAINT0_8192F				BIT(20)		/* Beacon DMA Interrupt 0 */
++#define IMR_BCNDERR0_8192F				BIT(16)		/* Beacon Queue DMA OK0 */
++#define IMR_HSISR_IND_ON_INT_8192F		BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
++#define IMR_BCNDMAINT_E_8192F				BIT(14)		/* Beacon DMA Interrupt Extension for Win7 */
++#define IMR_ATIMEND_8192F					BIT(12)         /* CTWidnow End or ATIM Window End */
++#define IMR_C2HCMD_8192F					BIT(10)		/* CPU to Host Command INT status, Write 1 clear */
++#define IMR_CPWM2_8192F					BIT(9)          /* CPU power mode exchange INT status, Write 1 clear */
++#define IMR_CPWM_8192F						BIT(8)		/* CPU power mode exchange INT status, Write 1 clear */
++#define IMR_HIGHDOK_8192F					BIT(7)		/* High Queue DMA OK */
++#define IMR_MGNTDOK_8192F					BIT(6)		/* Management Queue DMA OK */
++#define IMR_BKDOK_8192F					BIT(5)		/* AC_BK DMA OK */
++#define IMR_BEDOK_8192F					BIT(4)		/* AC_BE DMA OK */
++#define IMR_VIDOK_8192F					BIT(3)		/* AC_VI DMA OK */
++#define IMR_VODOK_8192F					BIT(2)		/* AC_VO DMA OK */
++#define IMR_RDU_8192F						BIT(1)		/* Rx Descriptor Unavailable */
++#define IMR_ROK_8192F						BIT(0)		/* Receive DMA OK */
++
++/* IMR DW1(0x00B4-00B7) Bit 0-31 */
++#define IMR_MCUERR_8192F					BIT(28)
++#define IMR_BCNDMAINT7_8192F				BIT(27) 		/* Beacon DMA Interrupt 7 */
++#define IMR_BCNDMAINT6_8192F				BIT(26)		/* Beacon DMA Interrupt 6 */
++#define IMR_BCNDMAINT5_8192F				BIT(25)		/* Beacon DMA Interrupt 5 */
++#define IMR_BCNDMAINT4_8192F				BIT(24)		/* Beacon DMA Interrupt 4 */
++#define IMR_BCNDMAINT3_8192F				BIT(23)		/* Beacon DMA Interrupt 3 */
++#define IMR_BCNDMAINT2_8192F				BIT(22)		/* Beacon DMA Interrupt 2 */
++#define IMR_BCNDMAINT1_8192F 				BIT(21)		/* Beacon DMA Interrupt 1 */
++#define IMR_BCNDOK7_8192F 					BIT(20)		/* Beacon Queue DMA OK Interrup 7 */
++#define IMR_BCNDOK6_8192F					BIT(19) 		/* Beacon Queue DMA OK Interrup 6 */
++#define IMR_BCNDOK5_8192F					BIT(18)		/* Beacon Queue DMA OK Interrup 5 */
++#define IMR_BCNDOK4_8192F					BIT(17)		/* Beacon Queue DMA OK Interrup 4 */
++#define IMR_BCNDOK3_8192F					BIT(16)		/* Beacon Queue DMA OK Interrup 3 */
++#define IMR_BCNDOK2_8192F					BIT(15)		/* Beacon Queue DMA OK Interrup 2 */
++#define IMR_BCNDOK1_8192F					BIT(14)		/* Beacon Queue DMA OK Interrup 1 */
++#define IMR_ATIMEND_E_8192F				BIT(13)		/* ATIM Window End Extension for Win7 */
++#define IMR_TXERR_8192F					BIT(11)		/* Tx Error Flag Interrupt status, write 1 clear. */
++#define IMR_RXERR_8192F					BIT(10)		/* Rx Error Flag INT status, Write 1 clear */
++#define IMR_TXFOVW_8192F					BIT(9)		/* Transmit FIFO Overflow */
++#define IMR_RXFOVW_8192F 					BIT(8)		/* Receive FIFO Overflow */
++
++/* #define IMR_RX_MASK			(IMR_ROK_8192F|IMR_RDU_8192F|IMR_RXFOVW_8192F) */
++#define IMR_TX_MASK			(IMR_VODOK_8192F | IMR_VIDOK_8192F | IMR_BEDOK_8192F | IMR_BKDOK_8192F | IMR_MGNTDOK_8192F | IMR_HIGHDOK_8192F)
++#define RT_BCN_INT_MASKS		(IMR_BCNDMAINT0_8192F | IMR_TXBCN0OK_8192F | IMR_TXBCN0ERR_8192F | IMR_BCNDERR0_8192F)
++#define RT_AC_INT_MASKS		(IMR_VIDOK_8192F | IMR_VODOK_8192F | IMR_BEDOK_8192F | IMR_BKDOK_8192F)
++#endif /* CONFIG_PCI_HCI */
++
++/* 2 HSISR
++ * interrupt mask which needs to clear */
++#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
++		HSISR_SPS_OCP_INT |\
++		HSISR_RON_INT |\
++		HSISR_PDNINT |\
++		HSISR_GPIO9_INT)
++
++#define _TXDMA_HIQ_MAP_8192F(x)			(((x) & 0x7) << 19)
++#define _TXDMA_MGQ_MAP_8192F(x)			(((x) & 0x7) << 16)
++#define _TXDMA_BKQ_MAP_8192F(x)			(((x) & 0x7) << 13)
++#define _TXDMA_BEQ_MAP_8192F(x)			(((x) & 0x7) << 10)
++#define _TXDMA_VIQ_MAP_8192F(x)			(((x) & 0x7) << 7)
++#define _TXDMA_VOQ_MAP_8192F(x)			(((x) & 0x7) << 4)
++
++/*mac queue info*/
++#define QUEUE_TOTAL_NUM	20/*reg414h : 0~f ac queue 0x10~0x13MGQ HIQ BCNQ CMDQ*/
++#define QUEUE_ACQ_NUM		16 
++#define QUEUE_INDEX_MGQ		0x10
++#define QUEUE_INDEX_HIQ		0x11
++#define QUEUE_INDEX_BCNQ	0x12
++#define QUEUE_INDEX_CMDQ	0x13
++#endif /* __RTL8192F_SPEC_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_sreset.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_sreset.h
+new file mode 100644
+index 000000000..cf881c431
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_sreset.h
+@@ -0,0 +1,24 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8192F_SRESET_H_
++#define _RTL8192F_SRESET_H_
++
++#include <rtw_sreset.h>
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++	extern void rtl8192f_sreset_xmit_status_check(_adapter *padapter);
++	extern void rtl8192f_sreset_linked_status_check(_adapter *padapter);
++#endif /* DBG_CONFIG_ERROR_DETECT */
++#endif /* _RTL8192F_SRESET_H_ */
+\ No newline at end of file
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_xmit.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_xmit.h
+new file mode 100644
+index 000000000..97192399b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8192f_xmit.h
+@@ -0,0 +1,529 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8192F_XMIT_H__
++#define __RTL8192F_XMIT_H__
++
++
++#define MAX_TID (15)
++
++
++#ifndef __INC_HAL8192FDESC_H
++#define __INC_HAL8192FDESC_H
++
++#define RX_STATUS_DESC_SIZE_8192F		24
++#define RX_DRV_INFO_SIZE_UNIT_8192F 	8
++
++
++/* DWORD 0 */
++#define SET_RX_STATUS_DESC_PKT_LEN_8192F(__pRxStatusDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
++#define SET_RX_STATUS_DESC_EOR_8192F(__pRxStatusDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
++#define SET_RX_STATUS_DESC_OWN_8192F(__pRxStatusDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
++
++#define GET_RX_STATUS_DESC_PKT_LEN_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
++#define GET_RX_STATUS_DESC_CRC32_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
++#define GET_RX_STATUS_DESC_ICV_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
++#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
++#define GET_RX_STATUS_DESC_SECURITY_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
++#define GET_RX_STATUS_DESC_QOS_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
++#define GET_RX_STATUS_DESC_SHIFT_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
++#define GET_RX_STATUS_DESC_PHY_STATUS_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
++#define GET_RX_STATUS_DESC_SWDEC_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
++#define GET_RX_STATUS_DESC_EOR_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
++#define GET_RX_STATUS_DESC_OWN_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
++
++/* DWORD 1 */
++#define GET_RX_STATUS_DESC_MACID_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
++#define GET_RX_STATUS_DESC_TID_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
++#define GET_RX_STATUS_DESC_AMSDU_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
++#define GET_RX_STATUS_DESC_RXID_MATCH_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
++#define GET_RX_STATUS_DESC_PAGGR_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
++#define GET_RX_STATUS_DESC_A1_FIT_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
++#define GET_RX_STATUS_DESC_CHKERR_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
++#define GET_RX_STATUS_DESC_IPVER_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
++#define GET_RX_STATUS_DESC_IS_TCPUDP__8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
++#define GET_RX_STATUS_DESC_CHK_VLD_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
++#define GET_RX_STATUS_DESC_PAM_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
++#define GET_RX_STATUS_DESC_PWR_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
++#define GET_RX_STATUS_DESC_MORE_DATA_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
++#define GET_RX_STATUS_DESC_MORE_FRAG_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
++#define GET_RX_STATUS_DESC_TYPE_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
++#define GET_RX_STATUS_DESC_MC_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
++#define GET_RX_STATUS_DESC_BC_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
++
++/* DWORD 2 */
++#define GET_RX_STATUS_DESC_SEQ_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
++#define GET_RX_STATUS_DESC_FRAG_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
++#define GET_RX_STATUS_DESC_RX_IS_QOS_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
++#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
++#define GET_RX_STATUS_DESC_RPT_SEL_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
++#define GET_RX_STATUS_DESC_FCS_OK_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
++
++/* DWORD 3 */
++#define GET_RX_STATUS_DESC_RX_RATE_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
++#define GET_RX_STATUS_DESC_HTC_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
++#define GET_RX_STATUS_DESC_EOSP_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
++#define GET_RX_STATUS_DESC_BSSID_FIT_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
++#ifdef CONFIG_USB_RX_AGGREGATION
++#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
++#endif
++#define GET_RX_STATUS_DESC_PATTERN_MATCH_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
++#define GET_RX_STATUS_DESC_UNICAST_MATCH_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
++#define GET_RX_STATUS_DESC_MAGIC_MATCH_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
++
++/* DWORD 6 */
++#define GET_RX_STATUS_DESC_MATCH_ID_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7)
++
++/* DWORD 5 */
++#define GET_RX_STATUS_DESC_TSFL_8192F(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
++
++#define GET_RX_STATUS_DESC_BUFF_ADDR64_8192F(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
++
++
++
++/* Dword 0, rsvd: bit26, bit28 */
++#define GET_TX_DESC_OWN_8192F(__pTxDesc)\
++	LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
++
++#define SET_TX_DESC_PKT_SIZE_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
++#define SET_TX_DESC_OFFSET_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
++#define SET_TX_DESC_BMC_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
++#define SET_TX_DESC_HTC_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
++#define SET_TX_DESC_AMSDU_PAD_EN_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
++#define SET_TX_DESC_NO_ACM_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
++#define SET_TX_DESC_GF_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
++
++/* Dword 1 */
++#define SET_TX_DESC_MACID_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
++#define SET_TX_DESC_QUEUE_SEL_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
++#define SET_TX_DESC_RDG_NAV_EXT_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
++#define SET_TX_DESC_LSIG_TXOP_EN_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
++#define SET_TX_DESC_PIFS_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
++#define SET_TX_DESC_RATE_ID_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
++#define SET_TX_DESC_EN_DESC_ID_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
++#define SET_TX_DESC_SEC_TYPE_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
++#define SET_TX_DESC_PKT_OFFSET_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
++#define SET_TX_DESC_MORE_DATA_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
++
++/* Dword 2 ADD HW_DIG*/
++#define SET_TX_DESC_PAID_92F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value)
++#define SET_TX_DESC_CCA_RTS_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
++#define SET_TX_DESC_AGG_ENABLE_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
++#define SET_TX_DESC_RDG_ENABLE_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
++#define SET_TX_DESC_NULL0_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
++#define SET_TX_DESC_NULL1_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
++#define SET_TX_DESC_BK_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
++#define SET_TX_DESC_MORE_FRAG_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
++#define SET_TX_DESC_RAW_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
++#define SET_TX_DESC_CCX_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
++#define SET_TX_DESC_AMPDU_DENSITY_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
++#define SET_TX_DESC_BT_INT_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
++#define SET_TX_DESC_HW_DIG_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 7, __Value)
++
++/* Dword 3 */
++#define SET_TX_DESC_HWSEQ_SEL_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
++#define SET_TX_DESC_USE_RATE_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
++#define SET_TX_DESC_DISABLE_RTS_FB_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
++#define SET_TX_DESC_DISABLE_FB_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
++#define SET_TX_DESC_CTS2SELF_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
++#define SET_TX_DESC_RTS_ENABLE_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
++#define SET_TX_DESC_HW_RTS_ENABLE_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
++#define SET_TX_DESC_CHK_EN_92F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value)
++#define SET_TX_DESC_NAV_USE_HDR_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
++#define SET_TX_DESC_USE_MAX_LEN_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
++#define SET_TX_DESC_MAX_AGG_NUM_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
++#define SET_TX_DESC_NDPA_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
++#define SET_TX_DESC_AMPDU_MAX_TIME_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
++
++/* Dword 4 */
++#define SET_TX_DESC_TX_RATE_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
++#define SET_TX_DESC_TX_TRY_RATE_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
++#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
++#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
++#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
++#define SET_TX_DESC_DATA_RETRY_LIMIT_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
++#define SET_TX_DESC_RTS_RATE_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
++#define SET_TX_DESC_PCTS_EN_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
++#define SET_TX_DESC_PCTS_MASK_IDX_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
++
++/* Dword 5 */
++#define SET_TX_DESC_DATA_SC_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
++#define SET_TX_DESC_DATA_SHORT_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
++#define SET_TX_DESC_DATA_BW_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
++#define SET_TX_DESC_DATA_LDPC_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
++#define SET_TX_DESC_DATA_STBC_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
++#define SET_TX_DESC_RTS_STBC_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
++#define SET_TX_DESC_RTS_SHORT_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
++#define SET_TX_DESC_RTS_SC_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
++#define SET_TX_DESC_PORT_ID_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 21, 1, __Value)
++#define SET_TX_DESC_DROP_ID_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 22, 2, __Value)
++#define SET_TX_DESC_PATH_A_EN_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value)
++#define SET_TX_DESC_PATH_B_EN_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 25, 1, __Value)
++#define SET_TX_DESC_TXPWR_OF_SET_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
++
++/* Dword 6 */
++#define SET_TX_DESC_SW_DEFINE_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
++#define SET_TX_DESC_MBSSID_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
++#define SET_TX_DESC_RF_SEL_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
++
++/* Dword 7 */
++#ifdef CONFIG_PCI_HCI
++#define SET_TX_DESC_TX_BUFFER_SIZE_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++#endif
++
++#ifdef CONFIG_USB_HCI
++#define SET_TX_DESC_TX_DESC_CHECKSUM_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++#endif
++
++#ifdef CONFIG_SDIO_HCI
++#define SET_TX_DESC_TX_TIMESTAMP_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)
++#endif
++
++#define SET_TX_DESC_USB_TXAGG_NUM_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
++
++/* Dword 8 */
++#define SET_TX_DESC_RTS_RC_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
++#define SET_TX_DESC_BAR_RC_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
++#define SET_TX_DESC_DATA_RC_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
++#define SET_TX_DESC_HWSEQ_EN_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
++#define SET_TX_DESC_NEXTHEADPAGE_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
++#define SET_TX_DESC_TAILPAGE_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
++
++/* Dword 9 */
++#define SET_TX_DESC_PADDING_LEN_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
++#define SET_TX_DESC_SEQ_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
++#define SET_TX_DESC_FINAL_DATA_RATE_8192F(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
++
++
++#define SET_EARLYMODE_PKTNUM_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
++#define SET_EARLYMODE_LEN0_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
++#define SET_EARLYMODE_LEN1_1_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
++#define SET_EARLYMODE_LEN1_2_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
++#define SET_EARLYMODE_LEN2_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
++#define SET_EARLYMODE_LEN3_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
++
++
++/*-----------------------------------------------------------------*/
++/*	RTL8192F TX BUFFER DESC                                      */
++/*-----------------------------------------------------------------*/
++#ifdef CONFIG_64BIT_DMA
++	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)
++	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)
++	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)
++	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)
++#else
++	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
++	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
++	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
++	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu)	/* 64 BIT mode only */
++#endif
++/* ********************************************************* */
++
++/* 64 bits  -- 32 bits */
++/* =======     ======= */
++/* Dword 0     0 */
++#define SET_TX_BUFF_DESC_LEN_0_8192F(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
++#define SET_TX_BUFF_DESC_PSB_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
++#define SET_TX_BUFF_DESC_OWN_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
++
++/* Dword 1     1 */
++#define SET_TX_BUFF_DESC_ADDR_LOW_0_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
++#define GET_TX_BUFF_DESC_ADDR_LOW_0_8192F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
++/* Dword 2     NA */
++#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value)
++#ifdef CONFIG_64BIT_DMA
++	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)
++#else
++	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc) 0
++#endif
++/* Dword 3     NA */
++/* RESERVED 0 */
++/* Dword 4     2 */
++#define SET_TX_BUFF_DESC_LEN_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value)
++#define SET_TX_BUFF_DESC_AMSDU_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value)
++/* Dword 5     3 */
++#define SET_TX_BUFF_DESC_ADDR_LOW_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value)
++/* Dword 6     NA */
++#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value)
++/* Dword 7     NA */
++/*RESERVED 0 */
++/* Dword 8     4 */
++#define SET_TX_BUFF_DESC_LEN_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value)
++#define SET_TX_BUFF_DESC_AMSDU_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value)
++/* Dword 9     5 */
++#define SET_TX_BUFF_DESC_ADDR_LOW_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value)
++/* Dword 10    NA */
++#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value)
++/* Dword 11    NA */
++/*RESERVED 0 */
++/* Dword 12    6 */
++#define SET_TX_BUFF_DESC_LEN_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value)
++#define SET_TX_BUFF_DESC_AMSDU_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value)
++/* Dword 13    7 */
++#define SET_TX_BUFF_DESC_ADDR_LOW_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value)
++/* Dword 14    NA */
++#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value)
++/* Dword 15    NA */
++/*RESERVED 0 */
++
++
++#endif
++/* -----------------------------------------------------------
++ *
++ *	Rate
++ *
++ * -----------------------------------------------------------
++ * CCK Rates, TxHT = 0 */
++#define DESC8192F_RATE1M				0x00
++#define DESC8192F_RATE2M				0x01
++#define DESC8192F_RATE5_5M				0x02
++#define DESC8192F_RATE11M				0x03
++
++/* OFDM Rates, TxHT = 0 */
++#define DESC8192F_RATE6M				0x04
++#define DESC8192F_RATE9M				0x05
++#define DESC8192F_RATE12M				0x06
++#define DESC8192F_RATE18M				0x07
++#define DESC8192F_RATE24M				0x08
++#define DESC8192F_RATE36M				0x09
++#define DESC8192F_RATE48M				0x0a
++#define DESC8192F_RATE54M				0x0b
++
++/* MCS Rates, TxHT = 1 */
++#define DESC8192F_RATEMCS0				0x0c
++#define DESC8192F_RATEMCS1				0x0d
++#define DESC8192F_RATEMCS2				0x0e
++#define DESC8192F_RATEMCS3				0x0f
++#define DESC8192F_RATEMCS4				0x10
++#define DESC8192F_RATEMCS5				0x11
++#define DESC8192F_RATEMCS6				0x12
++#define DESC8192F_RATEMCS7				0x13
++#define DESC8192F_RATEMCS8				0x14
++#define DESC8192F_RATEMCS9				0x15
++#define DESC8192F_RATEMCS10		0x16
++#define DESC8192F_RATEMCS11		0x17
++#define DESC8192F_RATEMCS12		0x18
++#define DESC8192F_RATEMCS13		0x19
++#define DESC8192F_RATEMCS14		0x1a
++#define DESC8192F_RATEMCS15		0x1b
++#define DESC8192F_RATEVHTSS1MCS0		0x2c
++#define DESC8192F_RATEVHTSS1MCS1		0x2d
++#define DESC8192F_RATEVHTSS1MCS2		0x2e
++#define DESC8192F_RATEVHTSS1MCS3		0x2f
++#define DESC8192F_RATEVHTSS1MCS4		0x30
++#define DESC8192F_RATEVHTSS1MCS5		0x31
++#define DESC8192F_RATEVHTSS1MCS6		0x32
++#define DESC8192F_RATEVHTSS1MCS7		0x33
++#define DESC8192F_RATEVHTSS1MCS8		0x34
++#define DESC8192F_RATEVHTSS1MCS9		0x35
++#define DESC8192F_RATEVHTSS2MCS0		0x36
++#define DESC8192F_RATEVHTSS2MCS1		0x37
++#define DESC8192F_RATEVHTSS2MCS2		0x38
++#define DESC8192F_RATEVHTSS2MCS3		0x39
++#define DESC8192F_RATEVHTSS2MCS4		0x3a
++#define DESC8192F_RATEVHTSS2MCS5		0x3b
++#define DESC8192F_RATEVHTSS2MCS6		0x3c
++#define DESC8192F_RATEVHTSS2MCS7		0x3d
++#define DESC8192F_RATEVHTSS2MCS8		0x3e
++#define DESC8192F_RATEVHTSS2MCS9		0x3f
++
++
++#define	RX_HAL_IS_CCK_RATE_8192F(pDesc)\
++	(GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE1M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE2M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE5_5M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE11M)
++
++#ifdef CONFIG_TRX_BD_ARCH
++	struct tx_desc;
++#endif
++
++void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc);
++void rtl8192f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
++void rtl8192f_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
++void rtl8192f_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
++void rtl8192f_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
++void rtl8192f_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
++
++void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
++void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	s32 rtl8192fs_init_xmit_priv(PADAPTER padapter);
++	void rtl8192fs_free_xmit_priv(PADAPTER padapter);
++	s32 rtl8192fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8192fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	rtl8192fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8192fs_xmit_buf_handler(PADAPTER padapter);
++	thread_return rtl8192fs_xmit_thread(thread_context context);
++	#define hal_xmit_handler rtl8192fs_xmit_buf_handler
++#endif
++
++#ifdef CONFIG_USB_HCI
++	s32 rtl8192fu_init_xmit_priv(PADAPTER padapter);
++	void rtl8192fu_free_xmit_priv(PADAPTER padapter);
++	s32 rtl8192fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8192fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	 rtl8192fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8192fu_xmit_buf_handler(PADAPTER padapter);
++	#define hal_xmit_handler rtl8192fu_xmit_buf_handler
++	void rtl8192fu_xmit_tasklet(void *priv);
++	s32 rtl8192fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++	void _dbg_dump_tx_info(_adapter	*padapter,int frame_tag,struct tx_desc *ptxdesc);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	s32 rtl8192fe_init_xmit_priv(PADAPTER padapter);
++	void rtl8192fe_free_xmit_priv(PADAPTER padapter);
++	struct xmit_buf *rtl8192fe_dequeue_xmitbuf(struct rtw_tx_ring *ring);
++	void    rtl8192fe_xmitframe_resume(_adapter *padapter);
++	s32 rtl8192fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8192fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32     rtl8192fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	void rtl8192fe_xmit_tasklet(void *priv);
++#endif
++
++u8	BWMapping_8192F(PADAPTER Adapter, struct pkt_attrib *pattrib);
++u8	SCMapping_8192F(PADAPTER Adapter, struct pkt_attrib	*pattrib);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_cmd.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_cmd.h
+new file mode 100644
+index 000000000..0b2bd8359
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_cmd.h
+@@ -0,0 +1,205 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8703B_CMD_H__
++#define __RTL8703B_CMD_H__
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++enum h2c_cmd_8703B {
++	/* Common Class: 000 */
++	H2C_8703B_RSVD_PAGE = 0x00,
++	H2C_8703B_MEDIA_STATUS_RPT = 0x01,
++	H2C_8703B_SCAN_ENABLE = 0x02,
++	H2C_8703B_KEEP_ALIVE = 0x03,
++	H2C_8703B_DISCON_DECISION = 0x04,
++	H2C_8703B_PSD_OFFLOAD = 0x05,
++	H2C_8703B_AP_OFFLOAD = 0x08,
++	H2C_8703B_BCN_RSVDPAGE = 0x09,
++	H2C_8703B_PROBERSP_RSVDPAGE = 0x0A,
++	H2C_8703B_FCS_RSVDPAGE = 0x10,
++	H2C_8703B_FCS_INFO = 0x11,
++	H2C_8703B_AP_WOW_GPIO_CTRL = 0x13,
++
++	/* PoweSave Class: 001 */
++	H2C_8703B_SET_PWR_MODE = 0x20,
++	H2C_8703B_PS_TUNING_PARA = 0x21,
++	H2C_8703B_PS_TUNING_PARA2 = 0x22,
++	H2C_8703B_P2P_LPS_PARAM = 0x23,
++	H2C_8703B_P2P_PS_OFFLOAD = 0x24,
++	H2C_8703B_PS_SCAN_ENABLE = 0x25,
++	H2C_8703B_SAP_PS_ = 0x26,
++	H2C_8703B_INACTIVE_PS_ = 0x27, /* Inactive_PS */
++	H2C_8703B_FWLPS_IN_IPS_ = 0x28,
++
++	/* Dynamic Mechanism Class: 010 */
++	H2C_8703B_MACID_CFG = 0x40,
++	H2C_8703B_TXBF = 0x41,
++	H2C_8703B_RSSI_SETTING = 0x42,
++	H2C_8703B_AP_REQ_TXRPT = 0x43,
++	H2C_8703B_INIT_RATE_COLLECT = 0x44,
++	H2C_8703B_RA_PARA_ADJUST = 0x46,
++
++	/* BT Class: 011 */
++	H2C_8703B_B_TYPE_TDMA = 0x60,
++	H2C_8703B_BT_INFO = 0x61,
++	H2C_8703B_FORCE_BT_TXPWR = 0x62,
++	H2C_8703B_BT_IGNORE_WLANACT = 0x63,
++	H2C_8703B_DAC_SWING_VALUE = 0x64,
++	H2C_8703B_ANT_SEL_RSV = 0x65,
++	H2C_8703B_WL_OPMODE = 0x66,
++	H2C_8703B_BT_MP_OPER = 0x67,
++	H2C_8703B_BT_CONTROL = 0x68,
++	H2C_8703B_BT_WIFI_CTRL = 0x69,
++	H2C_8703B_BT_FW_PATCH = 0x6A,
++	H2C_8703B_BT_WLAN_CALIBRATION = 0x6D,
++
++	/* WOWLAN Class: 100 */
++	H2C_8703B_WOWLAN = 0x80,
++	H2C_8703B_REMOTE_WAKE_CTRL = 0x81,
++	H2C_8703B_AOAC_GLOBAL_INFO = 0x82,
++	H2C_8703B_AOAC_RSVD_PAGE = 0x83,
++	H2C_8703B_AOAC_RSVD_PAGE2 = 0x84,
++	H2C_8703B_D0_SCAN_OFFLOAD_CTRL = 0x85,
++	H2C_8703B_D0_SCAN_OFFLOAD_INFO = 0x86,
++	H2C_8703B_CHNL_SWITCH_OFFLOAD = 0x87,
++	H2C_8703B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
++	H2C_8703B_P2P_OFFLOAD = 0x8B,
++
++	H2C_8703B_RESET_TSF = 0xC0,
++	H2C_8703B_MAXID,
++};
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
++ * ---------------------------------------------------------------------------------------------------------
++ * _RSVDPAGE_LOC_CMD_0x00 */
++#define SET_8703B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8703B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_8703B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8703B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8703B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++/* _KEEP_ALIVE_CMD_0x03 */
++#define SET_8703B_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_8703B_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_8703B_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
++#define SET_8703B_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++
++/* _DISCONNECT_DECISION_CMD_0x04 */
++#define SET_8703B_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_8703B_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_8703B_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_8703B_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
++
++/* _PWR_MOD_CMD_0x20 */
++#define SET_8703B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8703B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
++#define SET_8703B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
++#define SET_8703B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8703B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8703B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
++#define SET_8703B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++#define GET_8703B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
++
++/* _PS_TUNE_PARAM_CMD_0x21 */
++#define SET_8703B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8703B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_8703B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
++#define SET_8703B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
++#define SET_8703B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++
++/* _MACID_CFG_CMD_0x40 */
++#define SET_8703B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8703B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
++#define SET_8703B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
++#define SET_8703B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
++#define SET_8703B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
++#define SET_8703B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
++#define SET_8703B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
++#define SET_8703B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
++#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
++#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
++#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
++
++/* _RSSI_SETTING_CMD_0x42 */
++#define SET_8703B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8703B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
++#define SET_8703B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++
++/* _AP_REQ_TXRPT_CMD_0x43 */
++#define SET_8703B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8703B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++
++/* _FORCE_BT_TXPWR_CMD_0x62 */
++#define SET_8703B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++
++/* _FORCE_BT_MP_OPER_CMD_0x67 */
++#define SET_8703B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
++#define SET_8703B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
++#define SET_8703B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_8703B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
++#define SET_8703B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++#define SET_8703B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
++
++/* _BT_FW_PATCH_0x6A */
++#define SET_8703B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
++#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
++
++/* ---------------------------------------------------------------------------------------------------------
++ * -------------------------------------------    Structure    --------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    Function Statement     --------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++/* host message to firmware cmd */
++void rtl8703b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
++void rtl8703b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
++void rtl8703b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
++/* s32 rtl8703b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
++void rtl8703b_set_FwPsTuneParam_cmd(PADAPTER padapter);
++void rtl8703b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);
++void rtl8703b_download_rsvd_page(PADAPTER padapter, u8 mstatus);
++#ifdef CONFIG_BT_COEXIST
++	void rtl8703b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
++#endif /* CONFIG_BT_COEXIST */
++#ifdef CONFIG_P2P
++	void rtl8703b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
++#endif /* CONFIG_P2P */
++
++#ifdef CONFIG_TDLS
++	#ifdef CONFIG_TDLS_CH_SW
++		void rtl8703b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
++	#endif
++#endif
++
++#ifdef CONFIG_P2P_WOWLAN
++	void rtl8703b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
++#endif
++
++void rtl8703b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
++
++s32 FillH2CCmd8703B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
++u8 GetTxBufferRsvdPageNum8703B(_adapter *padapter, bool wowlan);
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_dm.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_dm.h
+new file mode 100644
+index 000000000..912c7da07
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_dm.h
+@@ -0,0 +1,39 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8703B_DM_H__
++#define __RTL8703B_DM_H__
++/* ************************************************************
++ * Description:
++ *
++ * This file is for 8703B dynamic mechanism only
++ *
++ *
++ * ************************************************************ */
++
++/* ************************************************************
++ * structure and define
++ * ************************************************************ */
++
++/* ************************************************************
++ * function prototype
++ * ************************************************************ */
++
++void rtl8703b_init_dm_priv(PADAPTER padapter);
++void rtl8703b_deinit_dm_priv(PADAPTER padapter);
++
++void rtl8703b_InitHalDm(PADAPTER padapter);
++void rtl8703b_HalDmWatchDog(PADAPTER padapter);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_hal.h
+new file mode 100644
+index 000000000..4a83abf45
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_hal.h
+@@ -0,0 +1,266 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8703B_HAL_H__
++#define __RTL8703B_HAL_H__
++
++#include "hal_data.h"
++
++#include "rtl8703b_spec.h"
++#include "rtl8703b_rf.h"
++#include "rtl8703b_dm.h"
++#include "rtl8703b_recv.h"
++#include "rtl8703b_xmit.h"
++#include "rtl8703b_cmd.h"
++#include "rtl8703b_led.h"
++#include "Hal8703BPwrSeq.h"
++#include "Hal8703BPhyReg.h"
++#include "Hal8703BPhyCfg.h"
++#ifdef DBG_CONFIG_ERROR_DETECT
++	#include "rtl8703b_sreset.h"
++#endif
++
++#define FW_8703B_SIZE			0x8000
++#define FW_8703B_START_ADDRESS	0x1000
++#define FW_8703B_END_ADDRESS		0x1FFF /* 0x5FFF */
++
++#define IS_FW_HEADER_EXIST_8703B(_pFwHdr)	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x03B0)
++
++typedef struct _RT_FIRMWARE {
++	FIRMWARE_SOURCE	eFWSource;
++#ifdef CONFIG_EMBEDDED_FWIMG
++	u8			*szFwBuffer;
++#else
++	u8			szFwBuffer[FW_8703B_SIZE];
++#endif
++	u32			ulFwLength;
++} RT_FIRMWARE_8703B, *PRT_FIRMWARE_8703B;
++
++/*
++ * This structure must be cared byte-ordering
++ *
++ * Added by tynli. 2009.12.04. */
++typedef struct _RT_8703B_FIRMWARE_HDR {
++	/* 8-byte alinment required */
++
++	/* --- LONG WORD 0 ---- */
++	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
++	u8		Category;	/* AP/NIC and USB/PCI */
++	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
++	u16		Version;		/* FW Version */
++	u16		Subversion;	/* FW Subversion, default 0x00 */
++
++	/* --- LONG WORD 1 ---- */
++	u8		Month;	/* Release time Month field */
++	u8		Date;	/* Release time Date field */
++	u8		Hour;	/* Release time Hour field */
++	u8		Minute;	/* Release time Minute field */
++	u16		RamCodeSize;	/* The size of RAM code */
++	u16		Rsvd2;
++
++	/* --- LONG WORD 2 ---- */
++	u32		SvnIdx;	/* The SVN entry index */
++	u32		Rsvd3;
++
++	/* --- LONG WORD 3 ---- */
++	u32		Rsvd4;
++	u32		Rsvd5;
++} RT_8703B_FIRMWARE_HDR, *PRT_8703B_FIRMWARE_HDR;
++
++#define DRIVER_EARLY_INT_TIME_8703B		0x05
++#define BCN_DMA_ATIME_INT_TIME_8703B		0x02
++
++/* for 8703B
++ * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
++#define PAGE_SIZE_TX_8703B			128
++#define PAGE_SIZE_RX_8703B			8
++
++#define TX_DMA_SIZE_8703B			0x8000	/* 32K(TX) */
++#define RX_DMA_SIZE_8703B			0x4000	/* 16K(RX) */
++
++#ifdef CONFIG_WOWLAN
++	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
++#else
++	#define RESV_FMWF	0
++#endif
++
++#ifdef CONFIG_FW_C2H_DEBUG
++	#define RX_DMA_RESERVED_SIZE_8703B	0x100	/* 256B, reserved for c2h debug message */
++#else
++	#define RX_DMA_RESERVED_SIZE_8703B	0x80	/* 128B, reserved for tx report */
++#endif
++#define RX_DMA_BOUNDARY_8703B		(RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B - 1)
++
++
++/* Note: We will divide number of page equally for each queue other than public queue! */
++
++/* For General Reserved Page Number(Beacon Queue is reserved page)
++ * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8703B
++ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
++
++#define BCNQ_PAGE_NUM_8703B		(MAX_BEACON_LEN/PAGE_SIZE_TX_8703B + 6) /*0x08*/
++
++/* For WoWLan , more reserved page
++ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1 PNO: 6
++ * NS offload: 2NDP info: 1
++ */
++#ifdef CONFIG_WOWLAN
++	#define WOWLAN_PAGE_NUM_8703B	0x0b
++#else
++	#define WOWLAN_PAGE_NUM_8703B	0x00
++#endif
++
++#ifdef CONFIG_PNO_SUPPORT
++	#undef WOWLAN_PAGE_NUM_8703B
++	#define WOWLAN_PAGE_NUM_8703B	0x15
++#endif
++
++#ifdef CONFIG_AP_WOWLAN
++	#define AP_WOWLAN_PAGE_NUM_8703B	0x02
++#endif
++
++#define TX_TOTAL_PAGE_NUMBER_8703B	(0xFF - BCNQ_PAGE_NUM_8703B - WOWLAN_PAGE_NUM_8703B)
++#define TX_PAGE_BOUNDARY_8703B		(TX_TOTAL_PAGE_NUMBER_8703B + 1)
++
++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8703B	TX_TOTAL_PAGE_NUMBER_8703B
++#define WMM_NORMAL_TX_PAGE_BOUNDARY_8703B		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8703B + 1)
++
++/* For Normal Chip Setting
++ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8703B */
++#define NORMAL_PAGE_NUM_HPQ_8703B		0x0C
++#define NORMAL_PAGE_NUM_LPQ_8703B		0x02
++#define NORMAL_PAGE_NUM_NPQ_8703B		0x02
++
++/* Note: For Normal Chip Setting, modify later */
++#define WMM_NORMAL_PAGE_NUM_HPQ_8703B		0x30
++#define WMM_NORMAL_PAGE_NUM_LPQ_8703B		0x20
++#define WMM_NORMAL_PAGE_NUM_NPQ_8703B		0x20
++
++
++#include "HalVerDef.h"
++#include "hal_com.h"
++
++#define EFUSE_OOB_PROTECT_BYTES		15
++
++#define HAL_EFUSE_MEMORY
++
++#define HWSET_MAX_SIZE_8703B			256
++#define EFUSE_REAL_CONTENT_LEN_8703B		256
++#define EFUSE_MAP_LEN_8703B				512
++#define EFUSE_MAX_SECTION_8703B			64
++
++#define EFUSE_IC_ID_OFFSET			506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
++#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8703B)
++
++#define EFUSE_ACCESS_ON			0x69
++#define EFUSE_ACCESS_OFF			0x00
++
++/* ********************************************************
++ *			EFUSE for BT definition
++ * ******************************************************** */
++#define BANK_NUM		1
++#define EFUSE_BT_REAL_BANK_CONTENT_LEN	128
++#define EFUSE_BT_REAL_CONTENT_LEN		(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)
++#define EFUSE_BT_MAP_LEN				1024	/* 1k bytes */
++#define EFUSE_BT_MAX_SECTION			(EFUSE_BT_MAP_LEN / 8)
++#define EFUSE_PROTECT_BYTES_BANK		16
++
++typedef enum tag_Package_Definition {
++	PACKAGE_DEFAULT,
++	PACKAGE_QFN68,
++	PACKAGE_TFBGA90,
++	PACKAGE_TFBGA80,
++	PACKAGE_TFBGA79
++} PACKAGE_TYPE_E;
++
++#define INCLUDE_MULTI_FUNC_BT(_Adapter)		(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
++#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
++
++/* rtl8703b_hal_init.c */
++s32 rtl8703b_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
++void rtl8703b_FirmwareSelfReset(PADAPTER padapter);
++void rtl8703b_InitializeFirmwareVars(PADAPTER padapter);
++
++void rtl8703b_InitAntenna_Selection(PADAPTER padapter);
++void rtl8703b_DeinitAntenna_Selection(PADAPTER padapter);
++void rtl8703b_CheckAntenna_Selection(PADAPTER padapter);
++void rtl8703b_init_default_value(PADAPTER padapter);
++
++s32 rtl8703b_InitLLTTable(PADAPTER padapter);
++
++s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
++s32 CardDisableWithoutHWSM(PADAPTER padapter);
++
++/* EFuse */
++u8 GetEEPROMSize8703B(PADAPTER padapter);
++void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
++void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
++void Hal_EfuseParseTxPowerInfo_8703B(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseBTCoexistInfo_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseEEPROMVer_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseChnlPlan_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseCustomerID_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseAntennaDiversity_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseXtal_8703B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
++void Hal_EfuseParseThermalMeter_8703B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
++void Hal_EfuseParseVoltage_8703B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
++void Hal_EfuseParseBoardType_8703B(PADAPTER Adapter,	u8	*PROMContent, BOOLEAN AutoloadFail);
++
++void rtl8703b_set_hal_ops(struct hal_ops *pHalFunc);
++void init_hal_spec_8703b(_adapter *adapter);
++u8 SetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val);
++void GetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val);
++u8 SetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
++u8 GetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
++
++/* register */
++void rtl8703b_InitBeaconParameters(PADAPTER padapter);
++void rtl8703b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
++void	_InitBurstPktLen_8703BS(PADAPTER Adapter);
++void _InitLTECoex_8703BS(PADAPTER Adapter);
++void _InitMacAPLLSetting_8703B(PADAPTER Adapter);
++void _8051Reset8703(PADAPTER padapter);
++#ifdef CONFIG_WOWLAN
++	void Hal_DetectWoWMode(PADAPTER pAdapter);
++#endif /* CONFIG_WOWLAN */
++
++void rtl8703b_start_thread(_adapter *padapter);
++void rtl8703b_stop_thread(_adapter *padapter);
++
++#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
++	void rtl8703bs_init_checkbthang_workqueue(_adapter *adapter);
++	void rtl8703bs_free_checkbthang_workqueue(_adapter *adapter);
++	void rtl8703bs_cancle_checkbthang_workqueue(_adapter *adapter);
++	void rtl8703bs_hal_check_bt_hang(_adapter *adapter);
++#endif
++
++#ifdef CONFIG_GPIO_WAKEUP
++	void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
++#endif
++#ifdef CONFIG_MP_INCLUDED
++int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
++#endif
++void CCX_FwC2HTxRpt_8703b(PADAPTER padapter, u8 *pdata, u8 len);
++
++u8 MRateToHwRate8703B(u8  rate);
++u8 HwRateToMRate8703B(u8	 rate);
++
++void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++
++#ifdef CONFIG_PCI_HCI
++	BOOLEAN	InterruptRecognized8703BE(PADAPTER Adapter);
++	void	UpdateInterruptMask8703BE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_led.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_led.h
+new file mode 100644
+index 000000000..99e590d31
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_led.h
+@@ -0,0 +1,44 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8703B_LED_H__
++#define __RTL8703B_LED_H__
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++#ifdef CONFIG_RTW_SW_LED
++/* ********************************************************************************
++ * Interface to manipulate LED objects.
++ * ******************************************************************************** */
++#ifdef CONFIG_USB_HCI
++	void rtl8703bu_InitSwLeds(PADAPTER padapter);
++	void rtl8703bu_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_SDIO_HCI
++	void rtl8703bs_InitSwLeds(PADAPTER padapter);
++	void rtl8703bs_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_GSPI_HCI
++	void rtl8703bs_InitSwLeds(PADAPTER padapter);
++	void rtl8703bs_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_PCI_HCI
++	void rtl8703be_InitSwLeds(PADAPTER padapter);
++	void rtl8703be_DeInitSwLeds(PADAPTER padapter);
++#endif
++
++#endif/*CONFIG_RTW_SW_LED*/
++#endif /*__RTL8703B_LED_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_recv.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_recv.h
+new file mode 100644
+index 000000000..09672d238
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_recv.h
+@@ -0,0 +1,82 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8703B_RECV_H__
++#define __RTL8703B_RECV_H__
++
++#define RECV_BLK_SZ 512
++#define RECV_BLK_CNT 16
++#define RECV_BLK_TH RECV_BLK_CNT
++
++#if defined(CONFIG_USB_HCI)
++
++	#ifndef MAX_RECVBUF_SZ
++		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
++			/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
++			/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
++			/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
++			#ifdef CONFIG_PLATFORM_MSTAR
++				#define MAX_RECVBUF_SZ (8192) /* 8K */
++			#else
++				#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
++			#endif
++			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
++		#else
++			#define MAX_RECVBUF_SZ (4000) /* about 4K */
++		#endif
++	#endif /* !MAX_RECVBUF_SZ */
++
++#elif defined(CONFIG_PCI_HCI)
++	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
++	/*	#define MAX_RECVBUF_SZ (9100) */
++	/* #else */
++	#define MAX_RECVBUF_SZ (4000) /* about 4K
++	* #endif */
++
++
++#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++
++	#define MAX_RECVBUF_SZ (RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B)
++
++#endif
++
++/* Rx smooth factor */
++#define	Rx_Smooth_Factor (20)
++
++#ifdef CONFIG_SDIO_HCI
++	#ifndef CONFIG_SDIO_RX_COPY
++		#undef MAX_RECVBUF_SZ
++		#define MAX_RECVBUF_SZ	(RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B)
++	#endif /* !CONFIG_SDIO_RX_COPY */
++#endif /* CONFIG_SDIO_HCI */
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	s32 rtl8703bs_init_recv_priv(PADAPTER padapter);
++	void rtl8703bs_free_recv_priv(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_USB_HCI
++	int rtl8703bu_init_recv_priv(_adapter *padapter);
++	void rtl8703bu_free_recv_priv(_adapter *padapter);
++	void rtl8703bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	s32 rtl8703be_init_recv_priv(PADAPTER padapter);
++	void rtl8703be_free_recv_priv(PADAPTER padapter);
++#endif
++
++void rtl8703b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
++
++#endif /* __RTL8703B_RECV_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_rf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_rf.h
+new file mode 100644
+index 000000000..4148276bf
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_rf.h
+@@ -0,0 +1,25 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8703B_RF_H__
++#define __RTL8703B_RF_H__
++
++int	PHY_RF6052_Config8703B(PADAPTER		Adapter);
++
++void
++PHY_RF6052SetBandwidth8703B(
++		PADAPTER				Adapter,
++		enum channel_width		Bandwidth);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_spec.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_spec.h
+new file mode 100644
+index 000000000..633b23b1b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_spec.h
+@@ -0,0 +1,464 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8703B_SPEC_H__
++#define __RTL8703B_SPEC_H__
++
++#include <drv_conf.h>
++
++
++#define HAL_NAV_UPPER_UNIT_8703B		128		/* micro-second */
++
++/* -----------------------------------------------------
++ *
++ *	0x0000h ~ 0x00FFh	System Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_SYS_ISO_CTRL_8703B			0x0000	/* 2 Byte */
++#define REG_SYS_FUNC_EN_8703B			0x0002	/* 2 Byte */
++#define REG_APS_FSMCO_8703B			0x0004	/* 4 Byte */
++#define REG_SYS_CLKR_8703B				0x0008	/* 2 Byte */
++#define REG_9346CR_8703B				0x000A	/* 2 Byte */
++#define REG_EE_VPD_8703B				0x000C	/* 2 Byte */
++#define REG_AFE_MISC_8703B				0x0010	/* 1 Byte */
++#define REG_SPS0_CTRL_8703B				0x0011	/* 7 Byte */
++#define REG_SPS_OCP_CFG_8703B			0x0018	/* 4 Byte */
++#define REG_RSV_CTRL_8703B				0x001C	/* 3 Byte */
++#define REG_RF_CTRL_8703B				0x001F	/* 1 Byte */
++#define REG_LPLDO_CTRL_8703B			0x0023	/* 1 Byte */
++#define REG_AFE_XTAL_CTRL_8703B		0x0024	/* 4 Byte */
++#define REG_AFE_PLL_CTRL_8703B			0x0028	/* 4 Byte */
++#define REG_MAC_PLL_CTRL_EXT_8703B		0x002c	/* 4 Byte */
++#define REG_EFUSE_CTRL_8703B			0x0030
++#define REG_EFUSE_TEST_8703B			0x0034
++#define REG_PWR_DATA_8703B				0x0038
++#define REG_CAL_TIMER_8703B				0x003C
++#define REG_ACLK_MON_8703B				0x003E
++#define REG_GPIO_MUXCFG_8703B			0x0040
++#define REG_GPIO_IO_SEL_8703B			0x0042
++#define REG_MAC_PINMUX_CFG_8703B		0x0043
++#define REG_GPIO_PIN_CTRL_8703B			0x0044
++#define REG_GPIO_INTM_8703B				0x0048
++#define REG_LEDCFG0_8703B				0x004C
++#define REG_LEDCFG1_8703B				0x004D
++#define REG_LEDCFG2_8703B				0x004E
++#define REG_LEDCFG3_8703B				0x004F
++#define REG_FSIMR_8703B					0x0050
++#define REG_FSISR_8703B					0x0054
++#define REG_HSIMR_8703B					0x0058
++#define REG_HSISR_8703B					0x005c
++#define REG_GPIO_EXT_CTRL				0x0060
++#define REG_PAD_CTRL1_8703B		0x0064
++#define REG_MULTI_FUNC_CTRL_8703B		0x0068
++#define REG_GPIO_STATUS_8703B			0x006C
++#define REG_SDIO_CTRL_8703B				0x0070
++#define REG_OPT_CTRL_8703B				0x0074
++#define REG_AFE_CTRL_4_8703B		0x0078
++#define REG_MCUFWDL_8703B				0x0080
++#define REG_HMEBOX_DBG_0_8703B	0x0088
++#define REG_HMEBOX_DBG_1_8703B	0x008A
++#define REG_HMEBOX_DBG_2_8703B	0x008C
++#define REG_HMEBOX_DBG_3_8703B	0x008E
++#define REG_HIMR0_8703B					0x00B0
++#define REG_HISR0_8703B					0x00B4
++#define REG_HIMR1_8703B					0x00B8
++#define REG_HISR1_8703B					0x00BC
++#define REG_PMC_DBG_CTRL2_8703B			0x00CC
++#define	REG_EFUSE_BURN_GNT_8703B		0x00CF
++#define REG_HPON_FSM_8703B				0x00EC
++#define REG_SYS_CFG_8703B				0x00F0
++#define REG_SYS_CFG1_8703B				0x00FC
++#define REG_ROM_VERSION					0x00FD
++
++/* -----------------------------------------------------
++ *
++ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_C2HEVT_CMD_ID_8703B	0x01A0
++#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
++#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
++#define REG_C2HEVT_CMD_LEN_8703B        0x01AE
++#define REG_C2HEVT_CMD_LEN_88XX		REG_C2HEVT_CMD_LEN_8703B
++#define REG_C2HEVT_CLEAR_8703B			0x01AF
++#define REG_MCUTST_1_8703B				0x01C0
++#define REG_WOWLAN_WAKE_REASON 0x01C7
++#define REG_FMETHR_8703B				0x01C8
++#define REG_HMETFR_8703B				0x01CC
++#define REG_HMEBOX_0_8703B				0x01D0
++#define REG_HMEBOX_1_8703B				0x01D4
++#define REG_HMEBOX_2_8703B				0x01D8
++#define REG_HMEBOX_3_8703B				0x01DC
++#define REG_LLT_INIT_8703B				0x01E0
++#define REG_HMEBOX_EXT0_8703B			0x01F0
++#define REG_HMEBOX_EXT1_8703B			0x01F4
++#define REG_HMEBOX_EXT2_8703B			0x01F8
++#define REG_HMEBOX_EXT3_8703B			0x01FC
++
++/* -----------------------------------------------------
++ *
++ *	0x0200h ~ 0x027Fh	TXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_RQPN_8703B					0x0200
++#define REG_FIFOPAGE_8703B				0x0204
++#define REG_DWBCN0_CTRL_8703B			REG_TDECTRL
++#define REG_TXDMA_OFFSET_CHK_8703B	0x020C
++#define REG_TXDMA_STATUS_8703B		0x0210
++#define REG_RQPN_NPQ_8703B			0x0214
++#define REG_DWBCN1_CTRL_8703B			0x0228
++
++
++/* -----------------------------------------------------
++ *
++ *	0x0280h ~ 0x02FFh	RXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_RXDMA_AGG_PG_TH_8703B		0x0280
++#define REG_FW_UPD_RDPTR_8703B		0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
++#define REG_RXDMA_CONTROL_8703B		0x0286 /* Control the RX DMA. */
++#define REG_RXPKT_NUM_8703B			0x0287 /* The number of packets in RXPKTBUF.	 */
++#define REG_RXDMA_STATUS_8703B			0x0288
++#define REG_RXDMA_MODE_CTRL_8703B		0x0290
++#define REG_EARLY_MODE_CONTROL_8703B	0x02BC
++#define REG_RSVD5_8703B					0x02F0
++#define REG_RSVD6_8703B					0x02F4
++
++/* -----------------------------------------------------
++ *
++ *	0x0300h ~ 0x03FFh	PCIe
++ *
++ * ----------------------------------------------------- */
++#define	REG_PCIE_CTRL_REG_8703B		0x0300
++#define	REG_INT_MIG_8703B				0x0304	/* Interrupt Migration */
++#define	REG_BCNQ_DESA_8703B			0x0308	/* TX Beacon Descriptor Address */
++#define	REG_HQ_DESA_8703B				0x0310	/* TX High Queue Descriptor Address */
++#define	REG_MGQ_DESA_8703B			0x0318	/* TX Manage Queue Descriptor Address */
++#define	REG_VOQ_DESA_8703B			0x0320	/* TX VO Queue Descriptor Address */
++#define	REG_VIQ_DESA_8703B				0x0328	/* TX VI Queue Descriptor Address */
++#define	REG_BEQ_DESA_8703B			0x0330	/* TX BE Queue Descriptor Address */
++#define	REG_BKQ_DESA_8703B			0x0338	/* TX BK Queue Descriptor Address */
++#define	REG_RX_DESA_8703B				0x0340	/* RX Queue	Descriptor Address */
++#define	REG_DBI_WDATA_8703B			0x0348	/* DBI Write Data */
++#define	REG_DBI_RDATA_8703B			0x034C	/* DBI Read Data */
++#define	REG_DBI_ADDR_8703B				0x0350	/* DBI Address */
++#define	REG_DBI_FLAG_8703B				0x0352	/* DBI Read/Write Flag */
++#define	REG_MDIO_WDATA_8703B		0x0354	/* MDIO for Write PCIE PHY */
++#define	REG_MDIO_RDATA_8703B			0x0356	/* MDIO for Reads PCIE PHY */
++#define	REG_MDIO_CTL_8703B			0x0358	/* MDIO for Control */
++#define	REG_DBG_SEL_8703B				0x0360	/* Debug Selection Register */
++#define	REG_PCIE_HRPWM_8703B			0x0361	/* PCIe RPWM */
++#define	REG_PCIE_HCPWM_8703B			0x0363	/* PCIe CPWM */
++#define	REG_PCIE_MULTIFET_CTRL_8703B	0x036A	/* PCIE Multi-Fethc Control */
++
++/* -----------------------------------------------------
++ *
++ *	0x0400h ~ 0x047Fh	Protocol Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_VOQ_INFORMATION_8703B		0x0400
++#define REG_VIQ_INFORMATION_8703B		0x0404
++#define REG_BEQ_INFORMATION_8703B		0x0408
++#define REG_BKQ_INFORMATION_8703B		0x040C
++#define REG_MGQ_INFORMATION_8703B		0x0410
++#define REG_HGQ_INFORMATION_8703B		0x0414
++#define REG_BCNQ_INFORMATION_8703B	0x0418
++#define REG_TXPKT_EMPTY_8703B			0x041A
++
++#define REG_FWHW_TXQ_CTRL_8703B		0x0420
++#define REG_HWSEQ_CTRL_8703B			0x0423
++#define REG_TXPKTBUF_BCNQ_BDNY_8703B	0x0424
++#define REG_TXPKTBUF_MGQ_BDNY_8703B	0x0425
++#define REG_LIFECTRL_CTRL_8703B			0x0426
++#define REG_MULTI_BCNQ_OFFSET_8703B	0x0427
++#define REG_SPEC_SIFS_8703B				0x0428
++#define REG_RL_8703B						0x042A
++#define REG_TXBF_CTRL_8703B				0x042C
++#define REG_DARFRC_8703B				0x0430
++#define REG_RARFRC_8703B				0x0438
++#define REG_RRSR_8703B					0x0440
++#define REG_ARFR0_8703B					0x0444
++#define REG_ARFR1_8703B					0x044C
++#define REG_CCK_CHECK_8703B				0x0454
++#define REG_AMPDU_MAX_TIME_8703B		0x0456
++#define REG_TXPKTBUF_BCNQ_BDNY1_8703B	0x0457
++
++#define REG_AMPDU_MAX_LENGTH_8703B	0x0458
++#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8703B	0x045D
++#define REG_NDPA_OPT_CTRL_8703B		0x045F
++#define REG_FAST_EDCA_CTRL_8703B		0x0460
++#define REG_RD_RESP_PKT_TH_8703B		0x0463
++#define REG_DATA_SC_8703B				0x0483
++#ifdef CONFIG_WOWLAN
++	#define REG_TXPKTBUF_IV_LOW             0x0484
++	#define REG_TXPKTBUF_IV_HIGH            0x0488
++#endif
++#define REG_TXRPT_START_OFFSET		0x04AC
++#define REG_POWER_STAGE1_8703B		0x04B4
++#define REG_POWER_STAGE2_8703B		0x04B8
++#define REG_AMPDU_BURST_MODE_8703B	0x04BC
++#define REG_PKT_VO_VI_LIFE_TIME_8703B	0x04C0
++#define REG_PKT_BE_BK_LIFE_TIME_8703B	0x04C2
++#define REG_STBC_SETTING_8703B			0x04C4
++#define REG_HT_SINGLE_AMPDU_8703B		0x04C7
++#define REG_PROT_MODE_CTRL_8703B		0x04C8
++#define REG_MAX_AGGR_NUM_8703B		0x04CA
++#define REG_RTS_MAX_AGGR_NUM_8703B	0x04CB
++#define REG_BAR_MODE_CTRL_8703B		0x04CC
++#define REG_RA_TRY_RATE_AGG_LMT_8703B	0x04CF
++#define REG_MACID_PKT_DROP0_8703B		0x04D0
++#define REG_MACID_PKT_SLEEP_8703B		0x04D4
++
++/* -----------------------------------------------------
++ *
++ *	0x0500h ~ 0x05FFh	EDCA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_EDCA_VO_PARAM_8703B		0x0500
++#define REG_EDCA_VI_PARAM_8703B		0x0504
++#define REG_EDCA_BE_PARAM_8703B		0x0508
++#define REG_EDCA_BK_PARAM_8703B		0x050C
++#define REG_BCNTCFG_8703B				0x0510
++#define REG_PIFS_8703B					0x0512
++#define REG_RDG_PIFS_8703B				0x0513
++#define REG_SIFS_CTX_8703B				0x0514
++#define REG_SIFS_TRX_8703B				0x0516
++#define REG_AGGR_BREAK_TIME_8703B		0x051A
++#define REG_SLOT_8703B					0x051B
++#define REG_TX_PTCL_CTRL_8703B			0x0520
++#define REG_TXPAUSE_8703B				0x0522
++#define REG_DIS_TXREQ_CLR_8703B		0x0523
++#define REG_RD_CTRL_8703B				0x0524
++/*
++ * Format for offset 540h-542h:
++ *	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
++ *	[7:4]:   Reserved.
++ *	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
++ *	[23:20]: Reserved
++ * Description:
++ *	              |
++ * |<--Setup--|--Hold------------>|
++ *	--------------|----------------------
++ * |
++ * TBTT
++ * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
++ * Described by Designer Tim and Bruce, 2011-01-14.
++ *   */
++#define REG_TBTT_PROHIBIT_8703B			0x0540
++#define REG_RD_NAV_NXT_8703B			0x0544
++#define REG_NAV_PROT_LEN_8703B			0x0546
++#define REG_BCN_CTRL_8703B				0x0550
++#define REG_BCN_CTRL_1_8703B			0x0551
++#define REG_MBID_NUM_8703B				0x0552
++#define REG_DUAL_TSF_RST_8703B			0x0553
++#define REG_BCN_INTERVAL_8703B			0x0554
++#define REG_DRVERLYINT_8703B			0x0558
++#define REG_BCNDMATIM_8703B			0x0559
++#define REG_ATIMWND_8703B				0x055A
++#define REG_USTIME_TSF_8703B			0x055C
++#define REG_BCN_MAX_ERR_8703B			0x055D
++#define REG_RXTSF_OFFSET_CCK_8703B		0x055E
++#define REG_RXTSF_OFFSET_OFDM_8703B	0x055F
++#define REG_TSFTR_8703B					0x0560
++#define REG_CTWND_8703B					0x0572
++#define REG_SECONDARY_CCA_CTRL_8703B	0x0577
++#define REG_PSTIMER_8703B				0x0580
++#define REG_TIMER0_8703B				0x0584
++#define REG_TIMER1_8703B				0x0588
++#define REG_ACMHWCTRL_8703B			0x05C0
++#define REG_SCH_TXCMD_8703B			0x05F8
++
++/* -----------------------------------------------------
++ *
++ *	0x0600h ~ 0x07FFh	WMAC Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_MAC_CR_8703B				0x0600
++#define REG_TCR_8703B					0x0604
++#define REG_RCR_8703B					0x0608
++#define REG_RX_PKT_LIMIT_8703B			0x060C
++#define REG_RX_DLK_TIME_8703B			0x060D
++#define REG_RX_DRVINFO_SZ_8703B		0x060F
++
++#define REG_MACID_8703B					0x0610
++#define REG_BSSID_8703B					0x0618
++#define REG_MAR_8703B					0x0620
++#define REG_MBIDCAMCFG_8703B			0x0628
++#define REG_WOWLAN_GTK_DBG1	0x630
++#define REG_WOWLAN_GTK_DBG2	0x634
++
++#define REG_USTIME_EDCA_8703B			0x0638
++#define REG_MAC_SPEC_SIFS_8703B		0x063A
++#define REG_RESP_SIFP_CCK_8703B			0x063C
++#define REG_RESP_SIFS_OFDM_8703B		0x063E
++#define REG_ACKTO_8703B					0x0640
++#define REG_CTS2TO_8703B				0x0641
++#define REG_EIFS_8703B					0x0642
++
++#define REG_NAV_UPPER_8703B			0x0652	/* unit of 128 */
++#define REG_TRXPTCL_CTL_8703B			0x0668
++
++/* Security */
++#define REG_CAMCMD_8703B				0x0670
++#define REG_CAMWRITE_8703B				0x0674
++#define REG_CAMREAD_8703B				0x0678
++#define REG_CAMDBG_8703B				0x067C
++#define REG_SECCFG_8703B				0x0680
++
++/* Power */
++#define REG_WOW_CTRL_8703B				0x0690
++#define REG_PS_RX_INFO_8703B			0x0692
++#define REG_UAPSD_TID_8703B				0x0693
++#define REG_WKFMCAM_CMD_8703B			0x0698
++#define REG_WKFMCAM_NUM_8703B			0x0698
++#define REG_WKFMCAM_RWD_8703B			0x069C
++#define REG_RXFLTMAP0_8703B				0x06A0
++#define REG_RXFLTMAP1_8703B				0x06A2
++#define REG_RXFLTMAP2_8703B				0x06A4
++#define REG_BCN_PSR_RPT_8703B			0x06A8
++#define REG_BT_COEX_TABLE_8703B		0x06C0
++#define REG_BFMER0_INFO_8703B			0x06E4
++#define REG_BFMER1_INFO_8703B			0x06EC
++#define REG_CSI_RPT_PARAM_BW20_8703B	0x06F4
++#define REG_CSI_RPT_PARAM_BW40_8703B	0x06F8
++#define REG_CSI_RPT_PARAM_BW80_8703B	0x06FC
++
++/* Hardware Port 2 */
++#define REG_MACID1_8703B				0x0700
++#define REG_BSSID1_8703B				0x0708
++#define REG_BFMEE_SEL_8703B				0x0714
++#define REG_SND_PTCL_CTRL_8703B		0x0718
++
++/* LTE_COEX */
++#define REG_LTECOEX_CTRL			0x07C0
++#define REG_LTECOEX_WRITE_DATA		0x07C4
++#define REG_LTECOEX_READ_DATA		0x07C8
++#define REG_LTECOEX_PATH_CONTROL	0x70
++
++/* ************************************************************
++ * SDIO Bus Specification
++ * ************************************************************ */
++
++/* -----------------------------------------------------
++ * SDIO CMD Address Mapping
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ * I/O bus domain (Host)
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ * SDIO register
++ * ----------------------------------------------------- */
++#define SDIO_REG_HCPWM1_8703B	0x025 /* HCI Current Power Mode 1 */
++
++
++/* ****************************************************************************
++ *	8703 Regsiter Bit and Content definition
++ * **************************************************************************** */
++
++#define BIT_USB_RXDMA_AGG_EN	BIT(31)
++#define RXDMA_AGG_MODE_EN		BIT(1)
++
++#ifdef CONFIG_WOWLAN
++	#define RXPKT_RELEASE_POLL		BIT(16)
++	#define RXDMA_IDLE				BIT(17)
++	#define RW_RELEASE_EN			BIT(18)
++#endif
++
++/* 2 HSISR
++ * interrupt mask which needs to clear */
++#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
++		HSISR_SPS_OCP_INT |\
++		HSISR_RON_INT |\
++		HSISR_PDNINT |\
++		HSISR_GPIO9_INT)
++
++
++/* ----------------------------------------------------------------------------
++ * 8703B REG_CCK_CHECK						(offset 0x454)
++ * ---------------------------------------------------------------------------- */
++#define BIT_BCN_PORT_SEL		BIT(5)
++
++#ifdef CONFIG_RF_POWER_TRIM
++
++	#ifdef CONFIG_RTL8703B
++		#define EEPROM_RF_GAIN_OFFSET			0xC1
++	#endif
++
++	#define EEPROM_RF_GAIN_VAL				0x1F6
++#endif /*CONFIG_RF_POWER_TRIM*/
++
++
++/* ----------------------------------------------------------------------------
++ * 8195 IMR/ISR bits						(offset 0xB0,  8bits)
++ * ---------------------------------------------------------------------------- */
++#define	IMR_DISABLED_8703B					0
++/* IMR DW0(0x00B0-00B3) Bit 0-31 */
++#define	IMR_TIMER2_8703B					BIT(31)		/* Timeout interrupt 2 */
++#define	IMR_TIMER1_8703B					BIT(30)		/* Timeout interrupt 1	 */
++#define	IMR_PSTIMEOUT_8703B				BIT(29)		/* Power Save Time Out Interrupt */
++#define	IMR_GTINT4_8703B					BIT(28)		/* When GTIMER4 expires, this bit is set to 1	 */
++#define	IMR_GTINT3_8703B					BIT(27)		/* When GTIMER3 expires, this bit is set to 1	 */
++#define	IMR_TXBCN0ERR_8703B				BIT(26)		/* Transmit Beacon0 Error			 */
++#define	IMR_TXBCN0OK_8703B				BIT(25)		/* Transmit Beacon0 OK			 */
++#define	IMR_TSF_BIT32_TOGGLE_8703B		BIT(24)		/* TSF Timer BIT32 toggle indication interrupt			 */
++#define	IMR_BCNDMAINT0_8703B				BIT(20)		/* Beacon DMA Interrupt 0			 */
++#define	IMR_BCNDERR0_8703B				BIT(16)		/* Beacon Queue DMA OK0			 */
++#define	IMR_HSISR_IND_ON_INT_8703B		BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
++#define	IMR_BCNDMAINT_E_8703B			BIT(14)		/* Beacon DMA Interrupt Extension for Win7			 */
++#define	IMR_ATIMEND_8703B				BIT(12)		/* CTWidnow End or ATIM Window End */
++#define	IMR_C2HCMD_8703B					BIT(10)		/* CPU to Host Command INT Status, Write 1 clear	 */
++#define	IMR_CPWM2_8703B					BIT(9)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
++#define	IMR_CPWM_8703B					BIT(8)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
++#define	IMR_HIGHDOK_8703B				BIT(7)			/* High Queue DMA OK	 */
++#define	IMR_MGNTDOK_8703B				BIT(6)			/* Management Queue DMA OK	 */
++#define	IMR_BKDOK_8703B					BIT(5)			/* AC_BK DMA OK		 */
++#define	IMR_BEDOK_8703B					BIT(4)			/* AC_BE DMA OK	 */
++#define	IMR_VIDOK_8703B					BIT(3)			/* AC_VI DMA OK		 */
++#define	IMR_VODOK_8703B					BIT(2)			/* AC_VO DMA OK	 */
++#define	IMR_RDU_8703B					BIT(1)			/* Rx Descriptor Unavailable	 */
++#define	IMR_ROK_8703B					BIT(0)			/* Receive DMA OK */
++
++/* IMR DW1(0x00B4-00B7) Bit 0-31 */
++#define	IMR_BCNDMAINT7_8703B				BIT(27)		/* Beacon DMA Interrupt 7 */
++#define	IMR_BCNDMAINT6_8703B				BIT(26)		/* Beacon DMA Interrupt 6 */
++#define	IMR_BCNDMAINT5_8703B				BIT(25)		/* Beacon DMA Interrupt 5 */
++#define	IMR_BCNDMAINT4_8703B				BIT(24)		/* Beacon DMA Interrupt 4 */
++#define	IMR_BCNDMAINT3_8703B				BIT(23)		/* Beacon DMA Interrupt 3 */
++#define	IMR_BCNDMAINT2_8703B				BIT(22)		/* Beacon DMA Interrupt 2 */
++#define	IMR_BCNDMAINT1_8703B				BIT(21)		/* Beacon DMA Interrupt 1 */
++#define	IMR_BCNDOK7_8703B					BIT(20)		/* Beacon Queue DMA OK Interrupt 7 */
++#define	IMR_BCNDOK6_8703B					BIT(19)		/* Beacon Queue DMA OK Interrupt 6 */
++#define	IMR_BCNDOK5_8703B					BIT(18)		/* Beacon Queue DMA OK Interrupt 5 */
++#define	IMR_BCNDOK4_8703B					BIT(17)		/* Beacon Queue DMA OK Interrupt 4 */
++#define	IMR_BCNDOK3_8703B					BIT(16)		/* Beacon Queue DMA OK Interrupt 3 */
++#define	IMR_BCNDOK2_8703B					BIT(15)		/* Beacon Queue DMA OK Interrupt 2 */
++#define	IMR_BCNDOK1_8703B					BIT(14)		/* Beacon Queue DMA OK Interrupt 1 */
++#define	IMR_ATIMEND_E_8703B				BIT(13)		/* ATIM Window End Extension for Win7 */
++#define	IMR_TXERR_8703B					BIT(11)		/* Tx Error Flag Interrupt Status, write 1 clear. */
++#define	IMR_RXERR_8703B					BIT(10)		/* Rx Error Flag INT Status, Write 1 clear */
++#define	IMR_TXFOVW_8703B					BIT(9)			/* Transmit FIFO Overflow */
++#define	IMR_RXFOVW_8703B					BIT(8)			/* Receive FIFO Overflow */
++
++#ifdef CONFIG_PCI_HCI
++	/* #define IMR_RX_MASK		(IMR_ROK_8703B|IMR_RDU_8703B|IMR_RXFOVW_8703B) */
++	#define IMR_TX_MASK			(IMR_VODOK_8703B | IMR_VIDOK_8703B | IMR_BEDOK_8703B | IMR_BKDOK_8703B | IMR_MGNTDOK_8703B | IMR_HIGHDOK_8703B)
++
++	#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8703B | IMR_TXBCN0OK_8703B | IMR_TXBCN0ERR_8703B | IMR_BCNDERR0_8703B)
++
++	#define RT_AC_INT_MASKS	(IMR_VIDOK_8703B | IMR_VODOK_8703B | IMR_BEDOK_8703B | IMR_BKDOK_8703B)
++#endif
++
++#endif /* __RTL8703B_SPEC_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_sreset.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_sreset.h
+new file mode 100644
+index 000000000..5fe53cf41
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_sreset.h
+@@ -0,0 +1,24 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8703B_SRESET_H_
++#define _RTL8703B_SRESET_H_
++
++#include <rtw_sreset.h>
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++	extern void rtl8703b_sreset_xmit_status_check(_adapter *padapter);
++	extern void rtl8703b_sreset_linked_status_check(_adapter *padapter);
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_xmit.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_xmit.h
+new file mode 100644
+index 000000000..66d3149fc
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8703b_xmit.h
+@@ -0,0 +1,333 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8703B_XMIT_H__
++#define __RTL8703B_XMIT_H__
++
++
++#define MAX_TID (15)
++
++
++#ifndef __INC_HAL8703BDESC_H
++	#define __INC_HAL8703BDESC_H
++
++	#define RX_STATUS_DESC_SIZE_8703B		24
++	#define RX_DRV_INFO_SIZE_UNIT_8703B 8
++
++
++	/* DWORD 0 */
++	#define SET_RX_STATUS_DESC_PKT_LEN_8703B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
++	#define SET_RX_STATUS_DESC_EOR_8703B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
++	#define SET_RX_STATUS_DESC_OWN_8703B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
++
++	#define GET_RX_STATUS_DESC_PKT_LEN_8703B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
++	#define GET_RX_STATUS_DESC_CRC32_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
++	#define GET_RX_STATUS_DESC_ICV_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
++	#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
++	#define GET_RX_STATUS_DESC_SECURITY_8703B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
++	#define GET_RX_STATUS_DESC_QOS_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
++	#define GET_RX_STATUS_DESC_SHIFT_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
++	#define GET_RX_STATUS_DESC_PHY_STATUS_8703B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
++	#define GET_RX_STATUS_DESC_SWDEC_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
++	#define GET_RX_STATUS_DESC_LAST_SEG_8703B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
++	#define GET_RX_STATUS_DESC_FIRST_SEG_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
++	#define GET_RX_STATUS_DESC_EOR_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
++	#define GET_RX_STATUS_DESC_OWN_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
++
++	/* DWORD 1 */
++	#define GET_RX_STATUS_DESC_MACID_8703B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
++	#define GET_RX_STATUS_DESC_TID_8703B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
++	#define GET_RX_STATUS_DESC_AMSDU_8703B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
++	#define GET_RX_STATUS_DESC_RXID_MATCH_8703B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
++	#define GET_RX_STATUS_DESC_PAGGR_8703B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
++	#define GET_RX_STATUS_DESC_A1_FIT_8703B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
++	#define GET_RX_STATUS_DESC_CHKERR_8703B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
++	#define GET_RX_STATUS_DESC_IPVER_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
++	#define GET_RX_STATUS_DESC_IS_TCPUDP__8703B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
++	#define GET_RX_STATUS_DESC_CHK_VLD_8703B(__pRxDesc)	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
++	#define GET_RX_STATUS_DESC_PAM_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
++	#define GET_RX_STATUS_DESC_PWR_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
++	#define GET_RX_STATUS_DESC_MORE_DATA_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
++	#define GET_RX_STATUS_DESC_MORE_FRAG_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
++	#define GET_RX_STATUS_DESC_TYPE_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
++	#define GET_RX_STATUS_DESC_MC_8703B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
++	#define GET_RX_STATUS_DESC_BC_8703B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
++
++	/* DWORD 2 */
++	#define GET_RX_STATUS_DESC_SEQ_8703B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
++	#define GET_RX_STATUS_DESC_FRAG_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
++	#define GET_RX_STATUS_DESC_RX_IS_QOS_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
++	#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8703B(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
++	#define GET_RX_STATUS_DESC_RPT_SEL_8703B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
++
++	/* DWORD 3 */
++	#define GET_RX_STATUS_DESC_RX_RATE_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
++	#define GET_RX_STATUS_DESC_HTC_8703B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
++	#define GET_RX_STATUS_DESC_EOSP_8703B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
++	#define GET_RX_STATUS_DESC_BSSID_FIT_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
++	#ifdef CONFIG_USB_RX_AGGREGATION
++		#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8703B(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
++	#endif
++	#define GET_RX_STATUS_DESC_PATTERN_MATCH_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
++	#define GET_RX_STATUS_DESC_UNICAST_MATCH_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
++	#define GET_RX_STATUS_DESC_MAGIC_MATCH_8703B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
++
++	/* DWORD 6 */
++	#define GET_RX_STATUS_DESC_SPLCP_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
++	#define GET_RX_STATUS_DESC_LDPC_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
++	#define GET_RX_STATUS_DESC_STBC_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
++	#define GET_RX_STATUS_DESC_BW_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
++
++	/* DWORD 5 */
++	#define GET_RX_STATUS_DESC_TSFL_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
++
++	#define GET_RX_STATUS_DESC_BUFF_ADDR_8703B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
++	#define GET_RX_STATUS_DESC_BUFF_ADDR64_8703B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
++
++	#define SET_RX_STATUS_DESC_BUFF_ADDR_8703B(__pRxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
++
++
++	/* Dword 0 */
++	#define GET_TX_DESC_OWN_8703B(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
++
++	#define SET_TX_DESC_PKT_SIZE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
++	#define SET_TX_DESC_OFFSET_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
++	#define SET_TX_DESC_BMC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
++	#define SET_TX_DESC_HTC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
++	#define SET_TX_DESC_LAST_SEG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
++	#define SET_TX_DESC_FIRST_SEG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
++	#define SET_TX_DESC_LINIP_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
++	#define SET_TX_DESC_NO_ACM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
++	#define SET_TX_DESC_GF_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
++	#define SET_TX_DESC_OWN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
++
++	/* Dword 1 */
++	#define SET_TX_DESC_MACID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
++	#define SET_TX_DESC_QUEUE_SEL_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
++	#define SET_TX_DESC_RDG_NAV_EXT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
++	#define SET_TX_DESC_LSIG_TXOP_EN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
++	#define SET_TX_DESC_PIFS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
++	#define SET_TX_DESC_RATE_ID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
++	#define SET_TX_DESC_EN_DESC_ID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
++	#define SET_TX_DESC_SEC_TYPE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
++	#define SET_TX_DESC_PKT_OFFSET_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
++
++
++	/* Dword 2 */
++	#define SET_TX_DESC_PAID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
++	#define SET_TX_DESC_CCA_RTS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
++	#define SET_TX_DESC_AGG_ENABLE_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
++	#define SET_TX_DESC_RDG_ENABLE_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
++	#define SET_TX_DESC_AGG_BREAK_8703B(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
++	#define SET_TX_DESC_MORE_FRAG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
++	#define SET_TX_DESC_RAW_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
++	#define SET_TX_DESC_SPE_RPT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
++	#define SET_TX_DESC_AMPDU_DENSITY_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
++	#define SET_TX_DESC_BT_INT_8703B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
++	#define SET_TX_DESC_GID_8703B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
++
++
++	/* Dword 3 */
++	#define SET_TX_DESC_WHEADER_LEN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
++	#define SET_TX_DESC_CHK_EN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
++	#define SET_TX_DESC_EARLY_MODE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
++	#define SET_TX_DESC_HWSEQ_SEL_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
++	#define SET_TX_DESC_USE_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
++	#define SET_TX_DESC_DISABLE_RTS_FB_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
++	#define SET_TX_DESC_DISABLE_FB_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
++	#define SET_TX_DESC_CTS2SELF_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
++	#define SET_TX_DESC_RTS_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
++	#define SET_TX_DESC_HW_RTS_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
++	#define SET_TX_DESC_NAV_USE_HDR_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
++	#define SET_TX_DESC_USE_MAX_LEN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
++	#define SET_TX_DESC_MAX_AGG_NUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
++	#define SET_TX_DESC_NDPA_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
++	#define SET_TX_DESC_AMPDU_MAX_TIME_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
++
++	/* Dword 4 */
++	#define SET_TX_DESC_TX_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
++	#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
++	#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
++	#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
++	#define SET_TX_DESC_DATA_RETRY_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
++	#define SET_TX_DESC_RTS_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
++
++
++	/* Dword 5 */
++	#define SET_TX_DESC_DATA_SC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
++	#define SET_TX_DESC_DATA_SHORT_8703B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
++	#define SET_TX_DESC_DATA_BW_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
++	#define SET_TX_DESC_DATA_LDPC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
++	#define SET_TX_DESC_DATA_STBC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
++	#define SET_TX_DESC_CTROL_STBC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
++	#define SET_TX_DESC_RTS_SHORT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
++	#define SET_TX_DESC_RTS_SC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
++
++
++	/* Dword 6 */
++	#define SET_TX_DESC_SW_DEFINE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
++	#define SET_TX_DESC_MBSSID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
++	#define SET_TX_DESC_ANTSEL_A_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
++	#define SET_TX_DESC_ANTSEL_B_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
++	#define SET_TX_DESC_ANTSEL_C_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
++	#define SET_TX_DESC_ANTSEL_D_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
++
++	/* Dword 7 */
++	#ifdef CONFIG_PCI_HCI
++		#define SET_TX_DESC_TX_BUFFER_SIZE_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++	#endif /*CONFIG_PCI_HCI*/
++	#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
++		#define SET_TX_DESC_TX_DESC_CHECKSUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++	#endif
++	#define SET_TX_DESC_USB_TXAGG_NUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
++	#ifdef CONFIG_SDIO_HCI
++		#define SET_TX_DESC_SDIO_TXSEQ_8703B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
++	#endif
++
++	/* Dword 8 */
++	#define SET_TX_DESC_HWSEQ_EN_8703B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
++
++	/* Dword 9 */
++	#define SET_TX_DESC_SEQ_8703B(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
++
++	/* Dword 10 */
++	#define SET_TX_DESC_TX_BUFFER_ADDRESS_8703B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
++	#define GET_TX_DESC_TX_BUFFER_ADDRESS_8703B(__pTxDesc)	LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
++
++	/* Dword 11 */
++	#define SET_TX_DESC_NEXT_DESC_ADDRESS_8703B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
++
++
++	#define SET_EARLYMODE_PKTNUM_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
++	#define SET_EARLYMODE_LEN0_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
++	#define SET_EARLYMODE_LEN1_1_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
++	#define SET_EARLYMODE_LEN1_2_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
++	#define SET_EARLYMODE_LEN2_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
++	#define SET_EARLYMODE_LEN3_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
++
++#endif
++/* -----------------------------------------------------------
++ *
++ *	Rate
++ *
++ * -----------------------------------------------------------
++ * CCK Rates, TxHT = 0 */
++#define DESC8703B_RATE1M				0x00
++#define DESC8703B_RATE2M				0x01
++#define DESC8703B_RATE5_5M				0x02
++#define DESC8703B_RATE11M				0x03
++
++/* OFDM Rates, TxHT = 0 */
++#define DESC8703B_RATE6M				0x04
++#define DESC8703B_RATE9M				0x05
++#define DESC8703B_RATE12M				0x06
++#define DESC8703B_RATE18M				0x07
++#define DESC8703B_RATE24M				0x08
++#define DESC8703B_RATE36M				0x09
++#define DESC8703B_RATE48M				0x0a
++#define DESC8703B_RATE54M				0x0b
++
++/* MCS Rates, TxHT = 1 */
++#define DESC8703B_RATEMCS0				0x0c
++#define DESC8703B_RATEMCS1				0x0d
++#define DESC8703B_RATEMCS2				0x0e
++#define DESC8703B_RATEMCS3				0x0f
++#define DESC8703B_RATEMCS4				0x10
++#define DESC8703B_RATEMCS5				0x11
++#define DESC8703B_RATEMCS6				0x12
++#define DESC8703B_RATEMCS7				0x13
++#define DESC8703B_RATEMCS8				0x14
++#define DESC8703B_RATEMCS9				0x15
++#define DESC8703B_RATEMCS10		0x16
++#define DESC8703B_RATEMCS11		0x17
++#define DESC8703B_RATEMCS12		0x18
++#define DESC8703B_RATEMCS13		0x19
++#define DESC8703B_RATEMCS14		0x1a
++#define DESC8703B_RATEMCS15		0x1b
++#define DESC8703B_RATEVHTSS1MCS0		0x2c
++#define DESC8703B_RATEVHTSS1MCS1		0x2d
++#define DESC8703B_RATEVHTSS1MCS2		0x2e
++#define DESC8703B_RATEVHTSS1MCS3		0x2f
++#define DESC8703B_RATEVHTSS1MCS4		0x30
++#define DESC8703B_RATEVHTSS1MCS5		0x31
++#define DESC8703B_RATEVHTSS1MCS6		0x32
++#define DESC8703B_RATEVHTSS1MCS7		0x33
++#define DESC8703B_RATEVHTSS1MCS8		0x34
++#define DESC8703B_RATEVHTSS1MCS9		0x35
++#define DESC8703B_RATEVHTSS2MCS0		0x36
++#define DESC8703B_RATEVHTSS2MCS1		0x37
++#define DESC8703B_RATEVHTSS2MCS2		0x38
++#define DESC8703B_RATEVHTSS2MCS3		0x39
++#define DESC8703B_RATEVHTSS2MCS4		0x3a
++#define DESC8703B_RATEVHTSS2MCS5		0x3b
++#define DESC8703B_RATEVHTSS2MCS6		0x3c
++#define DESC8703B_RATEVHTSS2MCS7		0x3d
++#define DESC8703B_RATEVHTSS2MCS8		0x3e
++#define DESC8703B_RATEVHTSS2MCS9		0x3f
++
++
++#define	RX_HAL_IS_CCK_RATE_8703B(pDesc)\
++	(GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE1M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE2M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE5_5M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE11M)
++
++
++void rtl8703b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
++void rtl8703b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
++void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
++void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	s32 rtl8703bs_init_xmit_priv(PADAPTER padapter);
++	void rtl8703bs_free_xmit_priv(PADAPTER padapter);
++	s32 rtl8703bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8703bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	rtl8703bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8703bs_xmit_buf_handler(PADAPTER padapter);
++	thread_return rtl8703bs_xmit_thread(thread_context context);
++	#define hal_xmit_handler rtl8703bs_xmit_buf_handler
++#endif
++
++#ifdef CONFIG_USB_HCI
++	s32 rtl8703bu_xmit_buf_handler(PADAPTER padapter);
++	#define hal_xmit_handler rtl8703bu_xmit_buf_handler
++
++
++	s32 rtl8703bu_init_xmit_priv(PADAPTER padapter);
++	void rtl8703bu_free_xmit_priv(PADAPTER padapter);
++	s32 rtl8703bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8703bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	 rtl8703bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	/* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */
++	void rtl8703bu_xmit_tasklet(void *priv);
++	s32 rtl8703bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++	void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	s32 rtl8703be_init_xmit_priv(PADAPTER padapter);
++	void rtl8703be_free_xmit_priv(PADAPTER padapter);
++	struct xmit_buf *rtl8703be_dequeue_xmitbuf(struct rtw_tx_ring *ring);
++	void	rtl8703be_xmitframe_resume(_adapter *padapter);
++	s32 rtl8703be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8703be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	rtl8703be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	void rtl8703be_xmit_tasklet(void *priv);
++#endif
++
++u8	BWMapping_8703B(PADAPTER Adapter, struct pkt_attrib *pattrib);
++u8	SCMapping_8703B(PADAPTER Adapter, struct pkt_attrib	*pattrib);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_cmd.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_cmd.h
+new file mode 100644
+index 000000000..20d4ff908
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_cmd.h
+@@ -0,0 +1,175 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8710B_CMD_H__
++#define __RTL8710B_CMD_H__
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++enum h2c_cmd_8710B {
++	/* Common Class: 000 */
++	H2C_8710B_RSVD_PAGE = 0x00,
++	H2C_8710B_MEDIA_STATUS_RPT = 0x01,
++	H2C_8710B_SCAN_ENABLE = 0x02,
++	H2C_8710B_KEEP_ALIVE = 0x03,
++	H2C_8710B_DISCON_DECISION = 0x04,
++	H2C_8710B_PSD_OFFLOAD = 0x05,
++	H2C_8710B_AP_OFFLOAD = 0x08,
++	H2C_8710B_BCN_RSVDPAGE = 0x09,
++	H2C_8710B_PROBERSP_RSVDPAGE = 0x0A,
++	H2C_8710B_FCS_RSVDPAGE = 0x10,
++	H2C_8710B_FCS_INFO = 0x11,
++	H2C_8710B_AP_WOW_GPIO_CTRL = 0x13,
++
++	/* PoweSave Class: 001 */
++	H2C_8710B_SET_PWR_MODE = 0x20,
++	H2C_8710B_PS_TUNING_PARA = 0x21,
++	H2C_8710B_PS_TUNING_PARA2 = 0x22,
++	H2C_8710B_P2P_LPS_PARAM = 0x23,
++	H2C_8710B_P2P_PS_OFFLOAD = 0x24,
++	H2C_8710B_PS_SCAN_ENABLE = 0x25,
++	H2C_8710B_SAP_PS_ = 0x26,
++	H2C_8710B_INACTIVE_PS_ = 0x27, /* Inactive_PS */
++	H2C_8710B_FWLPS_IN_IPS_ = 0x28,
++
++	/* Dynamic Mechanism Class: 010 */
++	H2C_8710B_MACID_CFG = 0x40,
++	H2C_8710B_TXBF = 0x41,
++	H2C_8710B_RSSI_SETTING = 0x42,
++	H2C_8710B_AP_REQ_TXRPT = 0x43,
++	H2C_8710B_INIT_RATE_COLLECT = 0x44,
++	H2C_8710B_RA_PARA_ADJUST = 0x46,
++
++	/* WOWLAN Class: 100 */
++	H2C_8710B_WOWLAN = 0x80,
++	H2C_8710B_REMOTE_WAKE_CTRL = 0x81,
++	H2C_8710B_AOAC_GLOBAL_INFO = 0x82,
++	H2C_8710B_AOAC_RSVD_PAGE = 0x83,
++	H2C_8710B_AOAC_RSVD_PAGE2 = 0x84,
++	H2C_8710B_D0_SCAN_OFFLOAD_CTRL = 0x85,
++	H2C_8710B_D0_SCAN_OFFLOAD_INFO = 0x86,
++	H2C_8710B_CHNL_SWITCH_OFFLOAD = 0x87,
++	H2C_8710B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
++	H2C_8710B_P2P_OFFLOAD = 0x8B,
++
++	H2C_8710B_RESET_TSF = 0xC0,
++	H2C_8710B_MAXID,
++};
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
++ * ---------------------------------------------------------------------------------------------------------
++ * _RSVDPAGE_LOC_CMD_0x00 */
++#define SET_8710B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8710B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_8710B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8710B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8710B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++/* _PWR_MOD_CMD_0x20 */
++#define SET_8710B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8710B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
++#define SET_8710B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
++#define SET_8710B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8710B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8710B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
++#define SET_8710B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++#define GET_8710B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
++
++/* _PS_TUNE_PARAM_CMD_0x21 */
++#define SET_8710B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8710B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_8710B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
++#define SET_8710B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
++#define SET_8710B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++
++/* _MACID_CFG_CMD_0x40 */
++#define SET_8710B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8710B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
++#define SET_8710B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
++#define SET_8710B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
++#define SET_8710B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
++#define SET_8710B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
++#define SET_8710B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
++#define SET_8710B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
++#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
++#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
++#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
++
++/* _RSSI_SETTING_CMD_0x42 */
++#define SET_8710B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8710B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
++#define SET_8710B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++
++/* _AP_REQ_TXRPT_CMD_0x43 */
++#define SET_8710B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8710B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++
++/* _FORCE_BT_TXPWR_CMD_0x62 */
++#define SET_8710B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++
++/* _FORCE_BT_MP_OPER_CMD_0x67 */
++#define SET_8710B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
++#define SET_8710B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
++#define SET_8710B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_8710B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
++#define SET_8710B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++#define SET_8710B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
++
++/* _BT_FW_PATCH_0x6A */
++#define SET_8710B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
++#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
++
++/* ---------------------------------------------------------------------------------------------------------
++ * -------------------------------------------    Structure    --------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    Function Statement     --------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++/* host message to firmware cmd */
++void rtl8710b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
++void rtl8710b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
++/* s32 rtl8710b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
++void rtl8710b_set_FwPsTuneParam_cmd(PADAPTER padapter);
++void rtl8710b_download_rsvd_page(PADAPTER padapter, u8 mstatus);
++#ifdef CONFIG_BT_COEXIST
++	void rtl8710b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
++#endif /* CONFIG_BT_COEXIST */
++#ifdef CONFIG_P2P
++	void rtl8710b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
++#endif /* CONFIG_P2P */
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_TDLS_CH_SW
++void rtl8710b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
++#endif
++#endif
++
++#ifdef CONFIG_P2P_WOWLAN
++	void rtl8710b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
++#endif
++
++s32 FillH2CCmd8710B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
++u8 GetTxBufferRsvdPageNum8710B(_adapter *padapter, bool wowlan);
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_dm.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_dm.h
+new file mode 100644
+index 000000000..9a131ba05
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_dm.h
+@@ -0,0 +1,39 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8710B_DM_H__
++#define __RTL8710B_DM_H__
++/* ************************************************************
++ * Description:
++ *
++ * This file is for 8710B dynamic mechanism only
++ *
++ *
++ * ************************************************************ */
++
++/* ************************************************************
++ * structure and define
++ * ************************************************************ */
++
++/* ************************************************************
++ * function prototype
++ * ************************************************************ */
++
++void rtl8710b_init_dm_priv(PADAPTER padapter);
++void rtl8710b_deinit_dm_priv(PADAPTER padapter);
++
++void rtl8710b_InitHalDm(PADAPTER padapter);
++void rtl8710b_HalDmWatchDog(PADAPTER padapter);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_hal.h
+new file mode 100644
+index 000000000..332112b31
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_hal.h
+@@ -0,0 +1,277 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8710B_HAL_H__
++#define __RTL8710B_HAL_H__
++
++#include "hal_data.h"
++
++#include "rtl8710b_spec.h"
++#include "rtl8710b_rf.h"
++#include "rtl8710b_dm.h"
++#include "rtl8710b_recv.h"
++#include "rtl8710b_xmit.h"
++#include "rtl8710b_cmd.h"
++#include "rtl8710b_led.h"
++#include "Hal8710BPwrSeq.h"
++#include "Hal8710BPhyReg.h"
++#include "Hal8710BPhyCfg.h"
++#ifdef DBG_CONFIG_ERROR_DETECT
++	#include "rtl8710b_sreset.h"
++#endif
++#ifdef CONFIG_LPS_POFF
++	#include "rtl8710b_lps_poff.h"
++#endif
++
++#define FW_8710B_SIZE		0x8000
++#define FW_8710B_START_ADDRESS	0x1000
++#define FW_8710B_END_ADDRESS	0x1FFF /* 0x5FFF */
++
++typedef struct _RT_FIRMWARE {
++	FIRMWARE_SOURCE	eFWSource;
++#ifdef CONFIG_EMBEDDED_FWIMG
++	u8			*szFwBuffer;
++#else
++	u8			szFwBuffer[FW_8710B_SIZE];
++#endif
++	u32			ulFwLength;
++} RT_FIRMWARE_8710B, *PRT_FIRMWARE_8710B;
++
++/*
++ * This structure must be cared byte-ordering
++ *
++ * Added by tynli. 2009.12.04. */
++typedef struct _RT_8710B_FIRMWARE_HDR {
++	/* 8-byte alinment required */
++
++	/* --- LONG WORD 0 ---- */
++	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
++	u8		Category;	/* AP/NIC and USB/PCI */
++	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
++	u16		Version;		/* FW Version */
++	u16		Subversion;	/* FW Subversion, default 0x00 */
++
++	/* --- LONG WORD 1 ---- */
++	u8		Month;	/* Release time Month field */
++	u8		Date;	/* Release time Date field */
++	u8		Hour;	/* Release time Hour field */
++	u8		Minute;	/* Release time Minute field */
++	u16		RamCodeSize;	/* The size of RAM code */
++	u16		Rsvd2;
++
++	/* --- LONG WORD 2 ---- */
++	u32		SvnIdx;	/* The SVN entry index */
++	u32		Rsvd3;
++
++	/* --- LONG WORD 3 ---- */
++	u32		Rsvd4;
++	u32		Rsvd5;
++} RT_8710B_FIRMWARE_HDR, *PRT_8710B_FIRMWARE_HDR;
++
++#define DRIVER_EARLY_INT_TIME_8710B		0x05
++#define BCN_DMA_ATIME_INT_TIME_8710B		0x02
++
++/* for 8710B
++ * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
++#define PAGE_SIZE_TX_8710B			128
++#define PAGE_SIZE_RX_8710B			8
++
++#define TX_DMA_SIZE_8710B			0x8000	/* 32K(TX) */
++#define RX_DMA_SIZE_8710B			0x4000	/* 16K(RX) */
++
++#ifdef CONFIG_WOWLAN
++	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
++#else
++	#define RESV_FMWF	0
++#endif
++
++#ifdef CONFIG_FW_C2H_DEBUG
++	#define RX_DMA_RESERVED_SIZE_8710B	0x100	/* 256B, reserved for c2h debug message */
++#else
++	#define RX_DMA_RESERVED_SIZE_8710B	0x80	/* 128B, reserved for tx report */
++#endif
++#define RX_DMA_BOUNDARY_8710B\
++	(RX_DMA_SIZE_8710B - RX_DMA_RESERVED_SIZE_8710B - 1)
++
++
++/* Note: We will divide number of page equally for each queue other than public queue! */
++
++/* For General Reserved Page Number(Beacon Queue is reserved page)
++ * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8710B
++ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
++#define BCNQ_PAGE_NUM_8710B	(MAX_BEACON_LEN/PAGE_SIZE_TX_8710B + 6) /*0x08*/
++
++
++/* For WoWLan , more reserved page
++ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6
++ * NS offload: 2 NDP info: 1
++ */
++#ifdef CONFIG_WOWLAN
++	#define WOWLAN_PAGE_NUM_8710B	0x0b
++#else
++	#define WOWLAN_PAGE_NUM_8710B	0x00
++#endif
++
++#ifdef CONFIG_PNO_SUPPORT
++	#undef WOWLAN_PAGE_NUM_8710B
++	#define WOWLAN_PAGE_NUM_8710B	0x15
++#endif
++
++#ifdef CONFIG_AP_WOWLAN
++	#define AP_WOWLAN_PAGE_NUM_8710B	0x02
++#endif
++
++#define TX_TOTAL_PAGE_NUMBER_8710B\
++	(0xFF - BCNQ_PAGE_NUM_8710B -WOWLAN_PAGE_NUM_8710B)
++#define TX_PAGE_BOUNDARY_8710B		(TX_TOTAL_PAGE_NUMBER_8710B + 1)
++
++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8710B	TX_TOTAL_PAGE_NUMBER_8710B
++#define WMM_NORMAL_TX_PAGE_BOUNDARY_8710B\
++	(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8710B + 1)
++
++/* For Normal Chip Setting
++ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8710B */
++#define NORMAL_PAGE_NUM_HPQ_8710B		0x0C
++#define NORMAL_PAGE_NUM_LPQ_8710B		0x02
++#define NORMAL_PAGE_NUM_NPQ_8710B		0x02
++#define NORMAL_PAGE_NUM_EPQ_8710B		0x04
++
++/* Note: For Normal Chip Setting, modify later */
++#define WMM_NORMAL_PAGE_NUM_HPQ_8710B		0x30
++#define WMM_NORMAL_PAGE_NUM_LPQ_8710B		0x20
++#define WMM_NORMAL_PAGE_NUM_NPQ_8710B		0x20
++#define WMM_NORMAL_PAGE_NUM_EPQ_8710B		0x00
++
++
++#include "HalVerDef.h"
++#include "hal_com.h"
++
++#define EFUSE_OOB_PROTECT_BYTES (96 + 1)
++
++#define HAL_EFUSE_MEMORY
++#define HWSET_MAX_SIZE_8710B                512
++#define EFUSE_REAL_CONTENT_LEN_8710B        512
++#define EFUSE_MAP_LEN_8710B                 512
++#define EFUSE_MAX_SECTION_8710B             64
++
++/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/
++#define EFUSE_IC_ID_OFFSET			506
++#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8710B)
++
++#define EFUSE_ACCESS_ON	0x69
++#define EFUSE_ACCESS_OFF	0x00
++
++#define   PACKAGE_QFN32_S           0
++#define   PACKAGE_QFN48M_S        1    //definiton 8188GU Dongle Package, Efuse Physical Address 0xF8 = 0xFE
++#define   PACKAGE_QFN48_S  	       2
++#define   PACKAGE_QFN64_S  	       3     
++#define   PACKAGE_QFN32_U  		4    
++#define   PACKAGE_QFN48M_U  	5   //definiton 8188GU Dongle Package, Efuse Physical Address 0xF8 = 0xEE
++#define   PACKAGE_QFN48_U  		6 
++#define   PACKAGE_QFN68_U  		7
++
++typedef enum _PACKAGE_TYPE_E
++{
++    PACKAGE_DEFAULT,
++    PACKAGE_QFN68,
++    PACKAGE_TFBGA90,
++    PACKAGE_TFBGA80,
++    PACKAGE_TFBGA79
++}PACKAGE_TYPE_E;
++
++#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \
++	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
++
++#ifdef CONFIG_FILE_FWIMG
++	extern char *rtw_fw_file_path;
++	extern char *rtw_fw_wow_file_path;
++	#ifdef CONFIG_MP_INCLUDED
++		extern char *rtw_fw_mp_bt_file_path;
++	#endif /* CONFIG_MP_INCLUDED */
++#endif /* CONFIG_FILE_FWIMG */
++
++/* rtl8710b_hal_init.c */
++s32 rtl8710b_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
++void rtl8710b_FirmwareSelfReset(PADAPTER padapter);
++void rtl8710b_InitializeFirmwareVars(PADAPTER padapter);
++
++void rtl8710b_InitAntenna_Selection(PADAPTER padapter);
++void rtl8710b_DeinitAntenna_Selection(PADAPTER padapter);
++void rtl8710b_CheckAntenna_Selection(PADAPTER padapter);
++void rtl8710b_init_default_value(PADAPTER padapter);
++
++
++u32 indirect_read32_8710b(PADAPTER padapter, u32 regaddr);
++void indirect_write32_8710b(PADAPTER padapter, u32 regaddr, u32 data);
++u32 hal_query_syson_reg_8710b(PADAPTER padapter, u32 regaddr, u32 bitmask);
++void hal_set_syson_reg_8710b(PADAPTER padapter, u32 regaddr, u32 bitmask, u32 data);
++#define HAL_SetSYSOnReg hal_set_syson_reg_8710b
++
++
++/* EFuse */
++u8 GetEEPROMSize8710B(PADAPTER padapter);
++
++#if 0
++void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
++void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
++void Hal_EfuseParseTxPowerInfo_8710B(PADAPTER padapter,
++				     u8 *PROMContent, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseEEPROMVer_8710B(PADAPTER padapter,
++				   u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParsePackageType_8710B(PADAPTER pAdapter,
++				     u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseChnlPlan_8710B(PADAPTER padapter,
++				  u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseCustomerID_8710B(PADAPTER padapter,
++				    u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseAntennaDiversity_8710B(PADAPTER padapter,
++		u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseXtal_8710B(PADAPTER pAdapter,
++			      u8 *hwinfo, u8 AutoLoadFail);
++void Hal_EfuseParseThermalMeter_8710B(PADAPTER padapter,
++				      u8 *hwinfo, u8 AutoLoadFail);
++void Hal_EfuseParseBoardType_8710B(PADAPTER Adapter,
++				   u8	*PROMContent, BOOLEAN AutoloadFail);
++#endif
++
++void rtl8710b_set_hal_ops(struct hal_ops *pHalFunc);
++void init_hal_spec_8710b(_adapter *adapter);
++u8 SetHwReg8710B(PADAPTER padapter, u8 variable, u8 *val);
++void GetHwReg8710B(PADAPTER padapter, u8 variable, u8 *val);
++u8 SetHalDefVar8710B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
++u8 GetHalDefVar8710B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
++
++/* register */
++void rtl8710b_InitBeaconParameters(PADAPTER padapter);
++void rtl8710b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
++void _8051Reset8710(PADAPTER padapter);
++
++void rtl8710b_start_thread(_adapter *padapter);
++void rtl8710b_stop_thread(_adapter *padapter);
++
++#ifdef CONFIG_GPIO_WAKEUP
++	void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
++#endif
++
++void CCX_FwC2HTxRpt_8710b(PADAPTER padapter, u8 *pdata, u8 len);
++
++u8 MRateToHwRate8710B(u8 rate);
++u8 HwRateToMRate8710B(u8 rate);
++
++#ifdef CONFIG_USB_HCI
++	void rtl8710b_cal_txdesc_chksum(struct tx_desc *ptxdesc);
++#endif
++
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_led.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_led.h
+new file mode 100644
+index 000000000..8ca346d7a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_led.h
+@@ -0,0 +1,44 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8710B_LED_H__
++#define __RTL8710B_LED_H__
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++#ifdef CONFIG_RTW_SW_LED
++/* ********************************************************************************
++ * Interface to manipulate LED objects.
++ * ******************************************************************************** */
++#ifdef CONFIG_USB_HCI
++	void rtl8710bu_InitSwLeds(PADAPTER padapter);
++	void rtl8710bu_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_SDIO_HCI
++	void rtl8710bs_InitSwLeds(PADAPTER padapter);
++	void rtl8710bs_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_GSPI_HCI
++	void rtl8710bs_InitSwLeds(PADAPTER padapter);
++	void rtl8710bs_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_PCI_HCI
++	void rtl8710be_InitSwLeds(PADAPTER padapter);
++	void rtl8710be_DeInitSwLeds(PADAPTER padapter);
++#endif
++
++#endif /*#ifdef CONFIG_RTW_SW_LED*/
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_lps_poff.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_lps_poff.h
+new file mode 100644
+index 000000000..ea9c60e8f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_lps_poff.h
+@@ -0,0 +1,56 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/******************************************** CONST  ************************/
++#define NUM_OF_REGISTER_BANK	13
++#define NUM_OF_TOTAL_DWORD (NUM_OF_REGISTER_BANK * 64)
++#define TOTAL_LEN_FOR_HIOE ((NUM_OF_TOTAL_DWORD + 1) * 8)
++#define LPS_POFF_STATIC_FILE_LEN (TOTAL_LEN_FOR_HIOE + TXDESC_SIZE)
++#define LPS_POFF_DYNAMIC_FILE_LEN	(512 + TXDESC_SIZE)
++/******************************************** CONST  ************************/
++
++/******************************************** MACRO   ************************/
++/* HOIE Entry Definition */
++#define SET_HOIE_ENTRY_LOW_DATA(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE),	0, 16, __Value)
++#define SET_HOIE_ENTRY_HIGH_DATA(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE), 16, 16, __Value)
++#define SET_HOIE_ENTRY_MODE_SELECT(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 0, 1, __Value)
++#define SET_HOIE_ENTRY_ADDRESS(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 1, 14, __Value)
++#define SET_HOIE_ENTRY_BYTE_MASK(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 15, 4, __Value)
++#define SET_HOIE_ENTRY_IO_LOCK(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 19, 1, __Value)
++#define SET_HOIE_ENTRY_RD_EN(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 20, 1, __Value)
++#define SET_HOIE_ENTRY_WR_EN(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 21, 1, __Value)
++#define SET_HOIE_ENTRY_RAW_RW(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 22, 1, __Value)
++#define SET_HOIE_ENTRY_RAW(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 23, 1, __Value)
++#define SET_HOIE_ENTRY_IO_DELAY(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 24, 8, __Value)
++
++/*********************Function Definition*******************************************/
++void rtl8710b_lps_poff_init(PADAPTER padapter);
++void rtl8710b_lps_poff_deinit(PADAPTER padapter);
++bool rtl8710b_lps_poff_get_txbndy_status(PADAPTER padapter);
++void rtl8710b_lps_poff_h2c_ctrl(PADAPTER padapter, u8 enable);
++void rtl8710b_lps_poff_set_ps_mode(PADAPTER padapter, bool bEnterLPS);
++bool rtl8710b_lps_poff_get_status(PADAPTER padapter);
++void rtl8710b_lps_poff_wow(PADAPTER padapter);
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_recv.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_recv.h
+new file mode 100644
+index 000000000..ca0b8f8e7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_recv.h
+@@ -0,0 +1,81 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8710B_RECV_H__
++#define __RTL8710B_RECV_H__
++
++#define RECV_BLK_SZ 512
++#define RECV_BLK_CNT 16
++#define RECV_BLK_TH RECV_BLK_CNT
++
++#if defined(CONFIG_USB_HCI)
++	#ifndef MAX_RECVBUF_SZ
++		#ifdef CONFIG_MINIMAL_MEMORY_USAGE
++			#define MAX_RECVBUF_SZ (4000) /* about 4K */
++		#else
++			#ifdef CONFIG_PLATFORM_MSTAR
++				#define MAX_RECVBUF_SZ (8192) /* 8K */
++				#elif defined(CONFIG_PLATFORM_HISILICON)
++				#define MAX_RECVBUF_SZ (16384) /* 16k */
++			#else
++				#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
++				/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
++				/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
++				/* #define MAX_RECVBUF_SZ (10240)  */ /* 10K */
++				/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
++			#endif
++		#endif
++	#endif /* !MAX_RECVBUF_SZ */
++#endif
++
++/* Rx smooth factor */
++#define	Rx_Smooth_Factor (20)
++
++/*-----------------------------------------------------------------*/
++/*	RTL8710B RX BUFFER DESC                                      */
++/*-----------------------------------------------------------------*/
++/*DWORD 0*/
++#define SET_RX_BUFFER_DESC_DATA_LENGTH_8710B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
++#define SET_RX_BUFFER_DESC_LS_8710B(__pRxStatusDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
++#define SET_RX_BUFFER_DESC_FS_8710B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
++#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8710B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
++
++#define GET_RX_BUFFER_DESC_OWN_8710B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
++#define GET_RX_BUFFER_DESC_LS_8710B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
++#define GET_RX_BUFFER_DESC_FS_8710B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
++#ifdef USING_RX_TAG
++	#define GET_RX_BUFFER_DESC_RX_TAG_8710B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13)
++#else
++	#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8710B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
++#endif
++
++/*DWORD 1*/
++#define SET_RX_BUFFER_PHYSICAL_LOW_8710B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
++
++/*DWORD 2*/
++#ifdef CONFIG_64BIT_DMA
++	#define SET_RX_BUFFER_PHYSICAL_HIGH_8710B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
++#else
++	#define SET_RX_BUFFER_PHYSICAL_HIGH_8710B(__pRxStatusDesc, __Value)
++#endif
++
++#ifdef CONFIG_USB_HCI
++	int rtl8710bu_init_recv_priv(_adapter *padapter);
++	void rtl8710bu_free_recv_priv(_adapter *padapter);
++	void rtl8710bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
++#endif
++
++void rtl8710b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
++
++#endif /* __RTL8710B_RECV_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_rf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_rf.h
+new file mode 100644
+index 000000000..0b5cee616
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_rf.h
+@@ -0,0 +1,20 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8710B_RF_H__
++#define __RTL8710B_RF_H__
++
++int PHY_RF6052_Config8710B(PADAPTER pdapter);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_spec.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_spec.h
+new file mode 100644
+index 000000000..309c3eeb4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_spec.h
+@@ -0,0 +1,481 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8710B_SPEC_H__
++#define __RTL8710B_SPEC_H__
++
++#include <drv_conf.h>
++
++
++#define HAL_NAV_UPPER_UNIT_8710B		128		/* micro-second */
++
++/* -----------------------------------------------------
++ *
++ *	0x0000h ~ 0x00FFh	System Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_SYS_ISO_CTRL_8710B			0x0000	/* 2 Byte */
++#define REG_APS_FSMCO_8710B			0x0004	/* 4 Byte */
++#define REG_SYS_CLKR_8710B				0x0008	/* 2 Byte */
++#define REG_9346CR_8710B				0x000A	/* 2 Byte */
++#define REG_EE_VPD_8710B				0x000C	/* 2 Byte */
++#define REG_AFE_MISC_8710B				0x0010	/* 1 Byte */
++#define REG_SPS0_CTRL_8710B				0x0011	/* 7 Byte */
++#define REG_SPS_OCP_CFG_8710B			0x0018	/* 4 Byte */
++#define REG_RSV_CTRL_8710B				0x001C	/* 3 Byte */
++#define REG_RF_CTRL_8710B				0x001F	/* 1 Byte */
++#define REG_LPLDO_CTRL_8710B			0x0023	/* 1 Byte */
++#define REG_AFE_XTAL_CTRL_8710B		0x0024	/* 4 Byte */
++#define REG_AFE_PLL_CTRL_8710B			0x0028	/* 4 Byte */
++#define REG_MAC_PLL_CTRL_EXT_8710B		0x002c	/* 4 Byte */
++#define REG_EFUSE_CTRL_8710B			0x0030
++#define REG_EFUSE_TEST_8710B			0x0034
++#define REG_PWR_DATA_8710B				0x0038
++#define REG_CAL_TIMER_8710B				0x003C
++#define REG_ACLK_MON_8710B				0x003E
++#define REG_GPIO_MUXCFG_8710B			0x0040
++#define REG_GPIO_IO_SEL_8710B			0x0042
++#define REG_MAC_PINMUX_CFG_8710B		0x0043
++#define REG_GPIO_PIN_CTRL_8710B			0x0044
++#define REG_GPIO_INTM_8710B				0x0048
++#define REG_LEDCFG0_8710B				0x004C
++#define REG_LEDCFG1_8710B				0x004D
++#define REG_LEDCFG2_8710B				0x004E
++#define REG_LEDCFG3_8710B				0x004F
++#define REG_FSIMR_8710B					0x0050
++#define REG_FSISR_8710B					0x0054
++#define REG_HSIMR_8710B					0x0058
++#define REG_HSISR_8710B					0x005c
++#define REG_GPIO_EXT_CTRL				0x0060
++#define REG_PAD_CTRL1_8710B		0x0064
++#define REG_MULTI_FUNC_CTRL_8710B		0x0068
++#define REG_GPIO_STATUS_8710B			0x006C
++#define REG_SDIO_CTRL_8710B				0x0070
++#define REG_OPT_CTRL_8710B				0x0074
++#define REG_AFE_CTRL_4_8710B		0x0078
++#define REG_MCUFWDL_8710B				0x0080
++#define REG_8051FW_CTRL_8710B			0x0080
++#define REG_HMEBOX_DBG_0_8710B	0x0088
++#define REG_HMEBOX_DBG_1_8710B	0x008A
++#define REG_HMEBOX_DBG_2_8710B	0x008C
++#define REG_HMEBOX_DBG_3_8710B	0x008E
++#define REG_WLLPS_CTRL		0x0090
++
++#define REG_PMC_DBG_CTRL2_8710B			0x00CC
++#define	REG_EFUSE_BURN_GNT_8710B		0x00CF
++#define REG_HPON_FSM_8710B				0x00EC
++#define REG_SYS_CFG1_8710B				0x00F0
++#define REG_SYS_CFG_8710B				0x00FC
++#define REG_ROM_VERSION					0x00FD
++
++/* -----------------------------------------------------
++ *
++ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_C2HEVT_CMD_ID_8710B	0x01A0
++#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
++#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
++#define REG_C2HEVT_CMD_LEN_8710B        0x01AE
++#define REG_C2HEVT_CLEAR_8710B			0x01AF
++#define REG_MCUTST_1_8710B				0x01C0
++#define REG_WOWLAN_WAKE_REASON 0x01C7
++#define REG_FMETHR_8710B				0x01C8
++#define REG_HMETFR_8710B				0x01CC
++#define REG_HMEBOX_0_8710B				0x01D0
++#define REG_HMEBOX_1_8710B				0x01D4
++#define REG_HMEBOX_2_8710B				0x01D8
++#define REG_HMEBOX_3_8710B				0x01DC
++#define REG_LLT_INIT_8710B				0x01E0
++#define REG_HMEBOX_EXT0_8710B			0x01F0
++#define REG_HMEBOX_EXT1_8710B			0x01F4
++#define REG_HMEBOX_EXT2_8710B			0x01F8
++#define REG_HMEBOX_EXT3_8710B			0x01FC
++
++/* -----------------------------------------------------
++ *
++ *	0x0200h ~ 0x027Fh	TXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_RQPN_8710B					0x0200
++#define REG_FIFOPAGE_8710B				0x0204
++#define REG_DWBCN0_CTRL_8710B			REG_TDECTRL
++#define REG_TXDMA_OFFSET_CHK_8710B	0x020C
++#define REG_TXDMA_STATUS_8710B		0x0210
++#define REG_RQPN_NPQ_8710B			0x0214
++#define REG_DWBCN1_CTRL_8710B			0x0228
++
++
++/* -----------------------------------------------------
++ *
++ *	0x0280h ~ 0x02FFh	RXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_RXDMA_AGG_PG_TH_8710B		0x0280
++#define REG_FW_UPD_RDPTR_8710B		0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
++#define REG_RXDMA_CONTROL_8710B		0x0286 /* Control the RX DMA. */
++#define REG_RXDMA_STATUS_8710B			0x0288
++#define REG_RXDMA_MODE_CTRL_8710B		0x0290
++#define REG_EARLY_MODE_CONTROL_8710B	0x02BC
++#define REG_RSVD5_8710B					0x02F0
++#define REG_RSVD6_8710B					0x02F4
++
++/* -----------------------------------------------------
++ *
++ *	0x0300h ~ 0x03FFh	PCIe
++ *
++ * ----------------------------------------------------- */
++#define	REG_PCIE_CTRL_REG_8710B			0x0300
++#define	REG_INT_MIG_8710B				0x0304	/* Interrupt Migration */
++#define	REG_BCNQ_TXBD_DESA_8710B		0x0308	/* TX Beacon Descriptor Address */
++#define	REG_MGQ_TXBD_DESA_8710B			0x0310	/* TX Manage Queue Descriptor Address */
++#define	REG_VOQ_TXBD_DESA_8710B			0x0318	/* TX VO Queue Descriptor Address */
++#define	REG_VIQ_TXBD_DESA_8710B			0x0320	/* TX VI Queue Descriptor Address */
++#define	REG_BEQ_TXBD_DESA_8710B			0x0328	/* TX BE Queue Descriptor Address */
++#define	REG_BKQ_TXBD_DESA_8710B			0x0330	/* TX BK Queue Descriptor Address */
++#define	REG_RXQ_RXBD_DESA_8710B			0x0338	/* RX Queue	Descriptor Address */
++#define REG_HI0Q_TXBD_DESA_8710B		0x0340
++#define REG_HI1Q_TXBD_DESA_8710B		0x0348
++#define REG_HI2Q_TXBD_DESA_8710B		0x0350
++#define REG_HI3Q_TXBD_DESA_8710B		0x0358
++#define REG_HI4Q_TXBD_DESA_8710B		0x0360
++#define REG_HI5Q_TXBD_DESA_8710B		0x0368
++#define REG_HI6Q_TXBD_DESA_8710B		0x0370
++#define REG_HI7Q_TXBD_DESA_8710B		0x0378
++#define	REG_MGQ_TXBD_NUM_8710B			0x0380
++#define	REG_RX_RXBD_NUM_8710B			0x0382
++#define	REG_VOQ_TXBD_NUM_8710B			0x0384
++#define	REG_VIQ_TXBD_NUM_8710B			0x0386
++#define	REG_BEQ_TXBD_NUM_8710B			0x0388
++#define	REG_BKQ_TXBD_NUM_8710B			0x038A
++#define	REG_HI0Q_TXBD_NUM_8710B			0x038C
++#define	REG_HI1Q_TXBD_NUM_8710B			0x038E
++#define	REG_HI2Q_TXBD_NUM_8710B			0x0390
++#define	REG_HI3Q_TXBD_NUM_8710B			0x0392
++#define	REG_HI4Q_TXBD_NUM_8710B			0x0394
++#define	REG_HI5Q_TXBD_NUM_8710B			0x0396
++#define	REG_HI6Q_TXBD_NUM_8710B			0x0398
++#define	REG_HI7Q_TXBD_NUM_8710B			0x039A
++#define	REG_TSFTIMER_HCI_8710B			0x039C
++#define	REG_BD_RW_PTR_CLR_8710B			0x039C
++
++/* Read Write Point */
++#define	REG_VOQ_TXBD_IDX_8710B			0x03A0
++#define	REG_VIQ_TXBD_IDX_8710B			0x03A4
++#define	REG_BEQ_TXBD_IDX_8710B			0x03A8
++#define	REG_BKQ_TXBD_IDX_8710B			0x03AC
++#define	REG_MGQ_TXBD_IDX_8710B			0x03B0
++#define	REG_RXQ_TXBD_IDX_8710B			0x03B4
++#define	REG_HI0Q_TXBD_IDX_8710B			0x03B8
++#define	REG_HI1Q_TXBD_IDX_8710B			0x03BC
++#define	REG_HI2Q_TXBD_IDX_8710B			0x03C0
++#define	REG_HI3Q_TXBD_IDX_8710B			0x03C4
++#define	REG_HI4Q_TXBD_IDX_8710B			0x03C8
++#define	REG_HI5Q_TXBD_IDX_8710B			0x03CC
++#define	REG_HI6Q_TXBD_IDX_8710B			0x03D0
++#define	REG_HI7Q_TXBD_IDX_8710B			0x03D4
++
++#define	REG_PCIE_HCPWM_8710BE			0x03D8 /* ?????? */
++#define	REG_PCIE_HRPWM_8710BE			0x03DC	/* PCIe RPWM  ?????? */
++#define	REG_DBI_WDATA_V1_8710B			0x03E8
++#define	REG_DBI_RDATA_V1_8710B			0x03EC
++#define	REG_DBI_FLAG_V1_8710B			0x03F0
++#define REG_MDIO_V1_8710B				0x03F4
++#define REG_PCIE_MIX_CFG_8710B			0x03F8
++#define REG_HCI_MIX_CFG_8710B			0x03FC
++
++/* -----------------------------------------------------
++ *
++ *	0x0400h ~ 0x047Fh	Protocol Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_VOQ_INFORMATION_8710B		0x0400
++#define REG_VIQ_INFORMATION_8710B		0x0404
++#define REG_BEQ_INFORMATION_8710B		0x0408
++#define REG_BKQ_INFORMATION_8710B		0x040C
++#define REG_MGQ_INFORMATION_8710B		0x0410
++#define REG_HGQ_INFORMATION_8710B		0x0414
++#define REG_BCNQ_INFORMATION_8710B	0x0418
++#define REG_TXPKT_EMPTY_8710B			0x041A
++
++#define REG_FWHW_TXQ_CTRL_8710B		0x0420
++#define REG_HWSEQ_CTRL_8710B			0x0423
++#define REG_TXPKTBUF_BCNQ_BDNY_8710B	0x0424
++#define REG_TXPKTBUF_MGQ_BDNY_8710B	0x0425
++#define REG_LIFECTRL_CTRL_8710B			0x0426
++#define REG_MULTI_BCNQ_OFFSET_8710B	0x0427
++#define REG_SPEC_SIFS_8710B				0x0428
++#define REG_RL_8710B						0x042A
++#define REG_TXBF_CTRL_8710B				0x042C
++#define REG_DARFRC_8710B				0x0430
++#define REG_RARFRC_8710B				0x0438
++#define REG_RRSR_8710B					0x0440
++#define REG_ARFR0_8710B					0x0444
++#define REG_ARFR1_8710B					0x044C
++#define REG_CCK_CHECK_8710B				0x0454
++#define REG_AMPDU_MAX_TIME_8710B		0x0456
++#define REG_TXPKTBUF_BCNQ_BDNY1_8710B	0x0457
++
++#define REG_AMPDU_MAX_LENGTH_8710B	0x0458
++#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8710B	0x045D
++#define REG_NDPA_OPT_CTRL_8710B		0x045F
++#define REG_FAST_EDCA_CTRL_8710B		0x0460
++#define REG_RD_RESP_PKT_TH_8710B		0x0463
++#define REG_DATA_SC_8710B				0x0483
++#ifdef CONFIG_WOWLAN
++	#define REG_TXPKTBUF_IV_LOW             0x0484
++	#define REG_TXPKTBUF_IV_HIGH            0x0488
++#endif
++#define REG_TXRPT_START_OFFSET		0x04AC
++#define REG_POWER_STAGE1_8710B		0x04B4
++#define REG_POWER_STAGE2_8710B		0x04B8
++#define REG_AMPDU_BURST_MODE_8710B	0x04BC
++#define REG_PKT_VO_VI_LIFE_TIME_8710B	0x04C0
++#define REG_PKT_BE_BK_LIFE_TIME_8710B	0x04C2
++#define REG_STBC_SETTING_8710B			0x04C4
++#define REG_HT_SINGLE_AMPDU_8710B		0x04C7
++#define REG_PROT_MODE_CTRL_8710B		0x04C8
++#define REG_MAX_AGGR_NUM_8710B		0x04CA
++#define REG_RTS_MAX_AGGR_NUM_8710B	0x04CB
++#define REG_BAR_MODE_CTRL_8710B		0x04CC
++#define REG_RA_TRY_RATE_AGG_LMT_8710B	0x04CF
++#define REG_MACID_PKT_DROP0_8710B		0x04D0
++#define REG_MACID_PKT_SLEEP_8710B		0x04D4
++
++/* -----------------------------------------------------
++ *
++ *	0x0500h ~ 0x05FFh	EDCA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_EDCA_VO_PARAM_8710B		0x0500
++#define REG_EDCA_VI_PARAM_8710B		0x0504
++#define REG_EDCA_BE_PARAM_8710B		0x0508
++#define REG_EDCA_BK_PARAM_8710B		0x050C
++#define REG_BCNTCFG_8710B				0x0510
++#define REG_PIFS_8710B					0x0512
++#define REG_RDG_PIFS_8710B				0x0513
++#define REG_SIFS_CTX_8710B				0x0514
++#define REG_SIFS_TRX_8710B				0x0516
++#define REG_AGGR_BREAK_TIME_8710B		0x051A
++#define REG_SLOT_8710B					0x051B
++#define REG_TX_PTCL_CTRL_8710B			0x0520
++#define REG_TXPAUSE_8710B				0x0522
++#define REG_DIS_TXREQ_CLR_8710B		0x0523
++#define REG_RD_CTRL_8710B				0x0524
++/*
++ * Format for offset 540h-542h:
++ *	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
++ *	[7:4]:   Reserved.
++ *	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
++ *	[23:20]: Reserved
++ * Description:
++ *	              |
++ * |<--Setup--|--Hold------------>|
++ *	--------------|----------------------
++ * |
++ * TBTT
++ * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
++ * Described by Designer Tim and Bruce, 2011-01-14.
++ *   */
++#define REG_TBTT_PROHIBIT_8710B			0x0540
++#define REG_RD_NAV_NXT_8710B			0x0544
++#define REG_NAV_PROT_LEN_8710B			0x0546
++#define REG_BCN_CTRL_8710B				0x0550
++#define REG_BCN_CTRL_1_8710B			0x0551
++#define REG_MBID_NUM_8710B				0x0552
++#define REG_DUAL_TSF_RST_8710B			0x0553
++#define REG_BCN_INTERVAL_8710B			0x0554
++#define REG_DRVERLYINT_8710B			0x0558
++#define REG_BCNDMATIM_8710B			0x0559
++#define REG_ATIMWND_8710B				0x055A
++#define REG_USTIME_TSF_8710B			0x055C
++#define REG_BCN_MAX_ERR_8710B			0x055D
++#define REG_RXTSF_OFFSET_CCK_8710B		0x055E
++#define REG_RXTSF_OFFSET_OFDM_8710B	0x055F
++#define REG_TSFTR_8710B					0x0560
++#define REG_CTWND_8710B					0x0572
++#define REG_SECONDARY_CCA_CTRL_8710B	0x0577
++#define REG_PSTIMER_8710B				0x0580
++#define REG_TIMER0_8710B				0x0584
++#define REG_TIMER1_8710B				0x0588
++#define REG_ACMHWCTRL_8710B			0x05C0
++#define REG_SCH_TXCMD_8710B			0x05F8
++
++/* -----------------------------------------------------
++ *
++ *	0x0600h ~ 0x07FFh	WMAC Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_MAC_CR_8710B				0x0600
++#define REG_TCR_8710B					0x0604
++#define REG_RCR_8710B					0x0608
++#define REG_RX_PKT_LIMIT_8710B			0x060C
++#define REG_RX_DLK_TIME_8710B			0x060D
++#define REG_RX_DRVINFO_SZ_8710B		0x060F
++
++#define REG_MACID_8710B					0x0610
++#define REG_BSSID_8710B					0x0618
++#define REG_MAR_8710B					0x0620
++#define REG_MBIDCAMCFG_8710B			0x0628
++#define REG_WOWLAN_GTK_DBG1	0x630
++#define REG_WOWLAN_GTK_DBG2	0x634
++
++#define REG_USTIME_EDCA_8710B			0x0638
++#define REG_MAC_SPEC_SIFS_8710B		0x063A
++#define REG_RESP_SIFP_CCK_8710B			0x063C
++#define REG_RESP_SIFS_OFDM_8710B		0x063E
++#define REG_ACKTO_8710B					0x0640
++#define REG_CTS2TO_8710B				0x0641
++#define REG_EIFS_8710B					0x0642
++
++#define REG_NAV_UPPER_8710B			0x0652	/* unit of 128 */
++#define REG_TRXPTCL_CTL_8710B			0x0668
++
++/* Security */
++#define REG_CAMCMD_8710B				0x0670
++#define REG_CAMWRITE_8710B				0x0674
++#define REG_CAMREAD_8710B				0x0678
++#define REG_CAMDBG_8710B				0x067C
++#define REG_SECCFG_8710B				0x0680
++
++/* Power */
++#define REG_WOW_CTRL_8710B				0x0690
++#define REG_PS_RX_INFO_8710B			0x0692
++#define REG_UAPSD_TID_8710B				0x0693
++#define REG_WKFMCAM_CMD_8710B			0x0698
++#define REG_WKFMCAM_NUM_8710B			0x0698
++#define REG_WKFMCAM_RWD_8710B			0x069C
++#define REG_RXFLTMAP0_8710B				0x06A0
++#define REG_RXFLTMAP1_8710B				0x06A2
++#define REG_RXFLTMAP2_8710B				0x06A4
++#define REG_BCN_PSR_RPT_8710B			0x06A8
++#define REG_BT_COEX_TABLE_8710B		0x06C0
++#define REG_BFMER0_INFO_8710B			0x06E4
++#define REG_BFMER1_INFO_8710B			0x06EC
++#define REG_CSI_RPT_PARAM_BW20_8710B	0x06F4
++#define REG_CSI_RPT_PARAM_BW40_8710B	0x06F8
++#define REG_CSI_RPT_PARAM_BW80_8710B	0x06FC
++
++/* Hardware Port 2 */
++#define REG_MACID1_8710B				0x0700
++#define REG_BSSID1_8710B				0x0708
++#define REG_BFMEE_SEL_8710B				0x0714
++#define REG_SND_PTCL_CTRL_8710B		0x0718
++
++/* LTR */
++#define REG_LTR_CTRL_BASIC_8710B		0x07A4
++#define REG_LTR_IDLE_LATENCY_V1_8710B		0x0798
++#define REG_LTR_ACTIVE_LATENCY_V1_8710B		0x079C
++
++/* LTE_COEX */
++#define REG_LTECOEX_CTRL			0x07C0
++#define REG_LTECOEX_WRITE_DATA		0x07C4
++#define REG_LTECOEX_READ_DATA		0x07C8
++#define REG_LTECOEX_PATH_CONTROL	0x70
++
++/* Other */
++#define REG_USB_ACCESS_TIMEOUT 0xFE4C
++
++/* -----------------------------------------------------
++ * SYSON_REG_SPEC
++ * ----------------------------------------------------- */
++#define SYSON_REG_BASE_ADDR_8710B 0x40000000
++#define REG_SYS_XTAL_CTRL0	0x0060
++#define REG_SYS_SYSTEM_CFG0 0x1F0
++#define REG_SYS_SYSTEM_CFG1 0x1F4
++#define REG_SYS_SYSTEM_CFG2 0x1F8
++#define REG_SYS_EEPROM_CTRL0 0x0E0
++
++
++/* -----------------------------------------------------
++ * Indirect_R/W_SPEC
++ * ----------------------------------------------------- */
++#define NORMAL_REG_READ_OFFSET 0x83000000
++#define NORMAL_REG_WRITE_OFFSET 0x84000000
++#define EFUSE_READ_OFFSET 0x85000000
++#define EFUSE_WRITE_OFFSET 0x86000000
++
++
++/* -----------------------------------------------------
++ * PAGE0_WLANON_REG_SPEC
++ * ----------------------------------------------------- */
++#define PAGE0_OFFSET 0x0 // WLANON_PAGE0_REG needs to add an offset.
++
++
++
++/* ****************************************************************************
++ *	8723 Regsiter Bit and Content definition
++ * **************************************************************************** */
++ 
++ /* -----------------------------------------------------
++ * REG_SYS_SYSTEM_CFG0 
++ * ----------------------------------------------------- */
++#define BIT_RTL_ID_8710B BIT(16)
++
++#define BIT_MASK_CHIP_VER_8710B 0xf
++#define BIT_GET_CHIP_VER_8710B(x) ((x) & BIT_MASK_CHIP_VER_8710B)
++
++#define BIT_SHIFT_VENDOR_ID_8710B 4
++#define BIT_MASK_VENDOR_ID_8710B 0xf
++#define BIT_GET_VENDOR_ID_8710B(x) (((x) >> BIT_SHIFT_VENDOR_ID_8710B) & BIT_MASK_VENDOR_ID_8710B)
++
++ /* -----------------------------------------------------
++ * REG_SYS_SYSTEM_CFG1 
++ * ----------------------------------------------------- */
++#define BIT_SPSLDO_SEL_8710B BIT(25)
++
++ /* -----------------------------------------------------
++ * REG_SYS_SYSTEM_CFG2 
++ * ----------------------------------------------------- */
++#define BIT_MASK_RF_RL_ID_8710B 0xf
++#define BIT_GET_RF_RL_ID_8710B(x) ((x) & BIT_MASK_RF_RL_ID_8710B)
++
++ /* -----------------------------------------------------
++ * REG_SYS_SYSTEM_CFG2 
++ * ----------------------------------------------------- */
++#define BIT_EERPOMSEL_8710B BIT(4)
++#define BIT_AUTOLOAD_SUS_8710B BIT(5)
++
++
++ /* -----------------------------------------------------
++ * Other
++ * ----------------------------------------------------- */
++
++
++#define BIT_USB_RXDMA_AGG_EN	BIT(31)
++#define RXDMA_AGG_MODE_EN		BIT(1)
++
++#ifdef CONFIG_WOWLAN
++	#define RXPKT_RELEASE_POLL		BIT(16)
++	#define RXDMA_IDLE				BIT(17)
++	#define RW_RELEASE_EN			BIT(18)
++#endif
++
++/* 2 HSISR
++ * interrupt mask which needs to clear */
++#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
++		HSISR_SPS_OCP_INT |\
++		HSISR_RON_INT |\
++		HSISR_PDNINT |\
++		HSISR_GPIO9_INT)
++
++#ifdef CONFIG_RF_POWER_TRIM
++	#ifdef CONFIG_RTL8710B
++		#define EEPROM_RF_GAIN_OFFSET			0xC1
++	#endif
++
++	#define EEPROM_RF_GAIN_VAL				0x1F6
++#endif /*CONFIG_RF_POWER_TRIM*/
++
++#endif /* __RTL8710B_SPEC_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_sreset.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_sreset.h
+new file mode 100644
+index 000000000..ac5c64edd
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_sreset.h
+@@ -0,0 +1,24 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8710B_SRESET_H_
++#define _RTL8710B_SRESET_H_
++
++#include <rtw_sreset.h>
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++	extern void rtl8710b_sreset_xmit_status_check(_adapter *padapter);
++	extern void rtl8710b_sreset_linked_status_check(_adapter *padapter);
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_xmit.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_xmit.h
+new file mode 100644
+index 000000000..9262144d0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8710b_xmit.h
+@@ -0,0 +1,520 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8710B_XMIT_H__
++#define __RTL8710B_XMIT_H__
++
++
++#define MAX_TID (15)
++
++
++#ifndef __INC_HAL8710BDESC_H
++#define __INC_HAL8710BDESC_H
++
++#define RX_STATUS_DESC_SIZE_8710B		24
++#define RX_DRV_INFO_SIZE_UNIT_8710B 8
++
++
++/* DWORD 0 */
++#define SET_RX_STATUS_DESC_PKT_LEN_8710B(__pRxStatusDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
++#define SET_RX_STATUS_DESC_EOR_8710B(__pRxStatusDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
++#define SET_RX_STATUS_DESC_OWN_8710B(__pRxStatusDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
++
++#define GET_RX_STATUS_DESC_PKT_LEN_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
++#define GET_RX_STATUS_DESC_CRC32_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
++#define GET_RX_STATUS_DESC_ICV_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
++#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
++#define GET_RX_STATUS_DESC_SECURITY_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
++#define GET_RX_STATUS_DESC_QOS_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
++#define GET_RX_STATUS_DESC_SHIFT_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
++#define GET_RX_STATUS_DESC_PHY_STATUS_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
++#define GET_RX_STATUS_DESC_SWDEC_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
++#define GET_RX_STATUS_DESC_EOR_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
++#define GET_RX_STATUS_DESC_OWN_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
++
++/* DWORD 1 */
++#define GET_RX_STATUS_DESC_MACID_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
++#define GET_RX_STATUS_DESC_TID_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
++#define GET_RX_STATUS_DESC_AMSDU_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
++#define GET_RX_STATUS_DESC_RXID_MATCH_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
++#define GET_RX_STATUS_DESC_PAGGR_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
++#define GET_RX_STATUS_DESC_A1_FIT_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
++#define GET_RX_STATUS_DESC_CHKERR_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
++#define GET_RX_STATUS_DESC_IPVER_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
++#define GET_RX_STATUS_DESC_IS_TCPUDP__8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
++#define GET_RX_STATUS_DESC_CHK_VLD_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
++#define GET_RX_STATUS_DESC_PAM_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
++#define GET_RX_STATUS_DESC_PWR_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
++#define GET_RX_STATUS_DESC_MORE_DATA_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
++#define GET_RX_STATUS_DESC_MORE_FRAG_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
++#define GET_RX_STATUS_DESC_TYPE_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
++#define GET_RX_STATUS_DESC_MC_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
++#define GET_RX_STATUS_DESC_BC_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
++
++/* DWORD 2 */
++#define GET_RX_STATUS_DESC_SEQ_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
++#define GET_RX_STATUS_DESC_FRAG_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
++#define GET_RX_STATUS_DESC_RX_IS_QOS_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
++#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
++#define GET_RX_STATUS_DESC_RPT_SEL_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
++#define GET_RX_STATUS_DESC_FCS_OK_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
++
++/* DWORD 3 */
++#define GET_RX_STATUS_DESC_RX_RATE_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
++#define GET_RX_STATUS_DESC_HTC_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
++#define GET_RX_STATUS_DESC_EOSP_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
++#define GET_RX_STATUS_DESC_BSSID_FIT_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
++#ifdef CONFIG_USB_RX_AGGREGATION
++#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
++#endif
++#define GET_RX_STATUS_DESC_PATTERN_MATCH_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
++#define GET_RX_STATUS_DESC_UNICAST_MATCH_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
++#define GET_RX_STATUS_DESC_MAGIC_MATCH_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
++
++/* DWORD 6 */
++#define GET_RX_STATUS_DESC_MATCH_ID_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7)
++
++/* DWORD 5 */
++#define GET_RX_STATUS_DESC_TSFL_8710B(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
++
++#define GET_RX_STATUS_DESC_BUFF_ADDR_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
++#define GET_RX_STATUS_DESC_BUFF_ADDR64_8710B(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
++
++#define SET_RX_STATUS_DESC_BUFF_ADDR_8710B(__pRxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
++
++
++/* Dword 0, rsvd: bit26, bit28 */
++#define GET_TX_DESC_OWN_8710B(__pTxDesc)\
++	LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
++
++#define SET_TX_DESC_PKT_SIZE_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
++#define SET_TX_DESC_OFFSET_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
++#define SET_TX_DESC_BMC_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
++#define SET_TX_DESC_HTC_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
++#define SET_TX_DESC_AMSDU_PAD_EN_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
++#define SET_TX_DESC_NO_ACM_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
++#define SET_TX_DESC_GF_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
++
++/* Dword 1 */
++#define SET_TX_DESC_MACID_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
++#define SET_TX_DESC_QUEUE_SEL_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
++#define SET_TX_DESC_RDG_NAV_EXT_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
++#define SET_TX_DESC_LSIG_TXOP_EN_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
++#define SET_TX_DESC_PIFS_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
++#define SET_TX_DESC_RATE_ID_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
++#define SET_TX_DESC_EN_DESC_ID_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
++#define SET_TX_DESC_SEC_TYPE_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
++#define SET_TX_DESC_PKT_OFFSET_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
++#define SET_TX_DESC_MORE_DATA_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
++
++/* Dword 2  remove P_AID, G_ID field*/
++#define SET_TX_DESC_CCA_RTS_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
++#define SET_TX_DESC_AGG_ENABLE_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
++#define SET_TX_DESC_RDG_ENABLE_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
++#define SET_TX_DESC_NULL0_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
++#define SET_TX_DESC_NULL1_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
++#define SET_TX_DESC_BK_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
++#define SET_TX_DESC_MORE_FRAG_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
++#define SET_TX_DESC_RAW_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
++#define SET_TX_DESC_CCX_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
++#define SET_TX_DESC_AMPDU_DENSITY_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
++#define SET_TX_DESC_BT_INT_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
++#define SET_TX_DESC_FTM_EN_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 30, 1, __Value)
++
++/* Dword 3 */
++#define SET_TX_DESC_NAV_USE_HDR_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
++#define SET_TX_DESC_HWSEQ_SEL_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
++#define SET_TX_DESC_USE_RATE_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
++#define SET_TX_DESC_DISABLE_RTS_FB_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
++#define SET_TX_DESC_DISABLE_FB_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
++#define SET_TX_DESC_CTS2SELF_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
++#define SET_TX_DESC_RTS_ENABLE_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
++#define SET_TX_DESC_HW_RTS_ENABLE_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
++#define SET_TX_DESC_PORT_ID_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 2, __Value)
++#define SET_TX_DESC_USE_MAX_LEN_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
++#define SET_TX_DESC_MAX_AGG_NUM_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
++#define SET_TX_DESC_AMPDU_MAX_TIME_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
++
++/* Dword 4 */
++#define SET_TX_DESC_TX_RATE_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
++#define SET_TX_DESC_TX_TRY_RATE_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
++#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
++#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
++#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
++#define SET_TX_DESC_DATA_RETRY_LIMIT_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
++#define SET_TX_DESC_RTS_RATE_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
++#define SET_TX_DESC_PCTS_EN_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
++#define SET_TX_DESC_PCTS_MASK_IDX_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
++
++/* Dword 5 */
++#define SET_TX_DESC_DATA_SC_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
++#define SET_TX_DESC_DATA_SHORT_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
++#define SET_TX_DESC_DATA_BW_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
++#define SET_TX_DESC_DATA_STBC_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
++#define SET_TX_DESC_RTS_STBC_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
++#define SET_TX_DESC_RTS_SHORT_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
++#define SET_TX_DESC_RTS_SC_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
++#define SET_TX_DESC_PATH_A_EN_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value)
++#define SET_TX_DESC_TXPWR_OF_SET_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
++
++/* Dword 6 */
++#define SET_TX_DESC_SW_DEFINE_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
++#define SET_TX_DESC_MBSSID_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
++#define SET_TX_DESC_RF_SEL_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
++
++/* Dword 7 */
++#ifdef CONFIG_PCI_HCI
++#define SET_TX_DESC_TX_BUFFER_SIZE_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++#endif
++
++#ifdef CONFIG_USB_HCI
++#define SET_TX_DESC_TX_DESC_CHECKSUM_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++#endif
++
++#ifdef CONFIG_SDIO_HCI
++#define SET_TX_DESC_TX_TIMESTAMP_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)
++#endif
++
++#define SET_TX_DESC_USB_TXAGG_NUM_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
++
++/* Dword 8 */
++#define SET_TX_DESC_RTS_RC_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
++#define SET_TX_DESC_BAR_RC_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
++#define SET_TX_DESC_DATA_RC_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
++#define SET_TX_DESC_HWSEQ_EN_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
++#define SET_TX_DESC_NEXTHEADPAGE_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
++#define SET_TX_DESC_TAILPAGE_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
++
++/* Dword 9 */
++#define SET_TX_DESC_PADDING_LEN_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
++#define SET_TX_DESC_SEQ_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
++#define SET_TX_DESC_FINAL_DATA_RATE_8710B(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
++
++
++#define SET_EARLYMODE_PKTNUM_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
++#define SET_EARLYMODE_LEN0_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
++#define SET_EARLYMODE_LEN1_1_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
++#define SET_EARLYMODE_LEN1_2_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
++#define SET_EARLYMODE_LEN2_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
++#define SET_EARLYMODE_LEN3_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
++
++
++/*-----------------------------------------------------------------*/
++/*	RTL8710B TX BUFFER DESC                                      */
++/*-----------------------------------------------------------------*/
++#ifdef CONFIG_64BIT_DMA
++	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)
++	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)
++	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)
++	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)
++#else
++	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
++	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
++	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
++	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu)	/* 64 BIT mode only */
++#endif
++/* ********************************************************* */
++
++/* 64 bits  -- 32 bits */
++/* =======     ======= */
++/* Dword 0     0 */
++#define SET_TX_BUFF_DESC_LEN_0_8710B(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
++#define SET_TX_BUFF_DESC_PSB_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
++#define SET_TX_BUFF_DESC_OWN_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
++
++/* Dword 1     1 */
++#define SET_TX_BUFF_DESC_ADDR_LOW_0_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
++#define GET_TX_BUFF_DESC_ADDR_LOW_0_8710B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
++/* Dword 2     NA */
++#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value)
++#ifdef CONFIG_64BIT_DMA
++	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)
++#else
++	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc) 0
++#endif
++/* Dword 3     NA */
++/* RESERVED 0 */
++/* Dword 4     2 */
++#define SET_TX_BUFF_DESC_LEN_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value)
++#define SET_TX_BUFF_DESC_AMSDU_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value)
++/* Dword 5     3 */
++#define SET_TX_BUFF_DESC_ADDR_LOW_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value)
++/* Dword 6     NA */
++#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value)
++/* Dword 7     NA */
++/*RESERVED 0 */
++/* Dword 8     4 */
++#define SET_TX_BUFF_DESC_LEN_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value)
++#define SET_TX_BUFF_DESC_AMSDU_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value)
++/* Dword 9     5 */
++#define SET_TX_BUFF_DESC_ADDR_LOW_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value)
++/* Dword 10    NA */
++#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value)
++/* Dword 11    NA */
++/*RESERVED 0 */
++/* Dword 12    6 */
++#define SET_TX_BUFF_DESC_LEN_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value)
++#define SET_TX_BUFF_DESC_AMSDU_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value)
++/* Dword 13    7 */
++#define SET_TX_BUFF_DESC_ADDR_LOW_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value)
++/* Dword 14    NA */
++#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value)
++/* Dword 15    NA */
++/*RESERVED 0 */
++
++
++#endif
++/* -----------------------------------------------------------
++ *
++ *	Rate
++ *
++ * -----------------------------------------------------------
++ * CCK Rates, TxHT = 0 */
++#define DESC8710B_RATE1M				0x00
++#define DESC8710B_RATE2M				0x01
++#define DESC8710B_RATE5_5M				0x02
++#define DESC8710B_RATE11M				0x03
++
++/* OFDM Rates, TxHT = 0 */
++#define DESC8710B_RATE6M				0x04
++#define DESC8710B_RATE9M				0x05
++#define DESC8710B_RATE12M				0x06
++#define DESC8710B_RATE18M				0x07
++#define DESC8710B_RATE24M				0x08
++#define DESC8710B_RATE36M				0x09
++#define DESC8710B_RATE48M				0x0a
++#define DESC8710B_RATE54M				0x0b
++
++/* MCS Rates, TxHT = 1 */
++#define DESC8710B_RATEMCS0				0x0c
++#define DESC8710B_RATEMCS1				0x0d
++#define DESC8710B_RATEMCS2				0x0e
++#define DESC8710B_RATEMCS3				0x0f
++#define DESC8710B_RATEMCS4				0x10
++#define DESC8710B_RATEMCS5				0x11
++#define DESC8710B_RATEMCS6				0x12
++#define DESC8710B_RATEMCS7				0x13
++#define DESC8710B_RATEMCS8				0x14
++#define DESC8710B_RATEMCS9				0x15
++#define DESC8710B_RATEMCS10		0x16
++#define DESC8710B_RATEMCS11		0x17
++#define DESC8710B_RATEMCS12		0x18
++#define DESC8710B_RATEMCS13		0x19
++#define DESC8710B_RATEMCS14		0x1a
++#define DESC8710B_RATEMCS15		0x1b
++#define DESC8710B_RATEVHTSS1MCS0		0x2c
++#define DESC8710B_RATEVHTSS1MCS1		0x2d
++#define DESC8710B_RATEVHTSS1MCS2		0x2e
++#define DESC8710B_RATEVHTSS1MCS3		0x2f
++#define DESC8710B_RATEVHTSS1MCS4		0x30
++#define DESC8710B_RATEVHTSS1MCS5		0x31
++#define DESC8710B_RATEVHTSS1MCS6		0x32
++#define DESC8710B_RATEVHTSS1MCS7		0x33
++#define DESC8710B_RATEVHTSS1MCS8		0x34
++#define DESC8710B_RATEVHTSS1MCS9		0x35
++#define DESC8710B_RATEVHTSS2MCS0		0x36
++#define DESC8710B_RATEVHTSS2MCS1		0x37
++#define DESC8710B_RATEVHTSS2MCS2		0x38
++#define DESC8710B_RATEVHTSS2MCS3		0x39
++#define DESC8710B_RATEVHTSS2MCS4		0x3a
++#define DESC8710B_RATEVHTSS2MCS5		0x3b
++#define DESC8710B_RATEVHTSS2MCS6		0x3c
++#define DESC8710B_RATEVHTSS2MCS7		0x3d
++#define DESC8710B_RATEVHTSS2MCS8		0x3e
++#define DESC8710B_RATEVHTSS2MCS9		0x3f
++
++
++#define	RX_HAL_IS_CCK_RATE_8710B(pDesc)\
++	(GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE1M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE2M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE5_5M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE11M)
++
++#ifdef CONFIG_TRX_BD_ARCH
++	struct tx_desc;
++#endif
++
++void rtl8710b_cal_txdesc_chksum(struct tx_desc *ptxdesc);
++void rtl8710b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
++void rtl8710b_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
++void rtl8710b_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
++void rtl8710b_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
++void rtl8710b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
++
++void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
++void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	s32 rtl8710bs_init_xmit_priv(PADAPTER padapter);
++	void rtl8710bs_free_xmit_priv(PADAPTER padapter);
++	s32 rtl8710bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8710bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	rtl8710bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8710bs_xmit_buf_handler(PADAPTER padapter);
++	thread_return rtl8710bs_xmit_thread(thread_context context);
++	#define hal_xmit_handler rtl8710bs_xmit_buf_handler
++#endif
++
++#ifdef CONFIG_USB_HCI
++	s32 rtl8710bu_xmit_buf_handler(PADAPTER padapter);
++	#define hal_xmit_handler rtl8710bu_xmit_buf_handler
++	s32 rtl8710bu_init_xmit_priv(PADAPTER padapter);
++	void rtl8710bu_free_xmit_priv(PADAPTER padapter);
++	s32 rtl8710bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8710bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	 rtl8710bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	void rtl8710bu_xmit_tasklet(void *priv);
++	s32 rtl8710bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++	void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	s32 rtl8710be_init_xmit_priv(PADAPTER padapter);
++	void rtl8710be_free_xmit_priv(PADAPTER padapter);
++	struct xmit_buf *rtl8710be_dequeue_xmitbuf(struct rtw_tx_ring *ring);
++	void	rtl8710be_xmitframe_resume(_adapter *padapter);
++	s32 rtl8710be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8710be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	rtl8710be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	void rtl8710be_xmit_tasklet(void *priv);
++#endif
++
++u8	BWMapping_8710B(PADAPTER Adapter, struct pkt_attrib *pattrib);
++u8	SCMapping_8710B(PADAPTER Adapter, struct pkt_attrib	*pattrib);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_cmd.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_cmd.h
+new file mode 100644
+index 000000000..9da563337
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_cmd.h
+@@ -0,0 +1,205 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8723B_CMD_H__
++#define __RTL8723B_CMD_H__
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++enum h2c_cmd_8723B {
++	/* Common Class: 000 */
++	H2C_8723B_RSVD_PAGE = 0x00,
++	H2C_8723B_MEDIA_STATUS_RPT = 0x01,
++	H2C_8723B_SCAN_ENABLE = 0x02,
++	H2C_8723B_KEEP_ALIVE = 0x03,
++	H2C_8723B_DISCON_DECISION = 0x04,
++	H2C_8723B_PSD_OFFLOAD = 0x05,
++	H2C_8723B_AP_OFFLOAD = 0x08,
++	H2C_8723B_BCN_RSVDPAGE = 0x09,
++	H2C_8723B_PROBERSP_RSVDPAGE = 0x0A,
++	H2C_8723B_FCS_RSVDPAGE = 0x10,
++	H2C_8723B_FCS_INFO = 0x11,
++	H2C_8723B_AP_WOW_GPIO_CTRL = 0x13,
++
++	/* PoweSave Class: 001 */
++	H2C_8723B_SET_PWR_MODE = 0x20,
++	H2C_8723B_PS_TUNING_PARA = 0x21,
++	H2C_8723B_PS_TUNING_PARA2 = 0x22,
++	H2C_8723B_P2P_LPS_PARAM = 0x23,
++	H2C_8723B_P2P_PS_OFFLOAD = 0x24,
++	H2C_8723B_PS_SCAN_ENABLE = 0x25,
++	H2C_8723B_SAP_PS_ = 0x26,
++	H2C_8723B_INACTIVE_PS_ = 0x27, /* Inactive_PS */
++	H2C_8723B_FWLPS_IN_IPS_ = 0x28,
++
++	/* Dynamic Mechanism Class: 010 */
++	H2C_8723B_MACID_CFG = 0x40,
++	H2C_8723B_TXBF = 0x41,
++	H2C_8723B_RSSI_SETTING = 0x42,
++	H2C_8723B_AP_REQ_TXRPT = 0x43,
++	H2C_8723B_INIT_RATE_COLLECT = 0x44,
++	H2C_8723B_RA_PARA_ADJUST = 0x46,
++
++	/* BT Class: 011 */
++	H2C_8723B_B_TYPE_TDMA = 0x60,
++	H2C_8723B_BT_INFO = 0x61,
++	H2C_8723B_FORCE_BT_TXPWR = 0x62,
++	H2C_8723B_BT_IGNORE_WLANACT = 0x63,
++	H2C_8723B_DAC_SWING_VALUE = 0x64,
++	H2C_8723B_ANT_SEL_RSV = 0x65,
++	H2C_8723B_WL_OPMODE = 0x66,
++	H2C_8723B_BT_MP_OPER = 0x67,
++	H2C_8723B_BT_CONTROL = 0x68,
++	H2C_8723B_BT_WIFI_CTRL = 0x69,
++	H2C_8723B_BT_FW_PATCH = 0x6A,
++	H2C_8723B_BT_WLAN_CALIBRATION = 0x6D,
++
++	/* WOWLAN Class: 100 */
++	H2C_8723B_WOWLAN = 0x80,
++	H2C_8723B_REMOTE_WAKE_CTRL = 0x81,
++	H2C_8723B_AOAC_GLOBAL_INFO = 0x82,
++	H2C_8723B_AOAC_RSVD_PAGE = 0x83,
++	H2C_8723B_AOAC_RSVD_PAGE2 = 0x84,
++	H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85,
++	H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86,
++	H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87,
++	H2C_8723B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
++	H2C_8723B_P2P_OFFLOAD = 0x8B,
++
++	H2C_8723B_RESET_TSF = 0xC0,
++	H2C_8723B_MAXID,
++};
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
++ * ---------------------------------------------------------------------------------------------------------
++ * _RSVDPAGE_LOC_CMD_0x00 */
++#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_8723B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8723B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8723B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++/* _KEEP_ALIVE_CMD_0x03 */
++#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_8723B_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
++#define SET_8723B_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++
++/* _DISCONNECT_DECISION_CMD_0x04 */
++#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_8723B_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_8723B_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
++
++/* _PWR_MOD_CMD_0x20 */
++#define SET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8723B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
++#define SET_8723B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
++#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8723B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
++#define SET_8723B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++#define GET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
++
++/* _PS_TUNE_PARAM_CMD_0x21 */
++#define SET_8723B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8723B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_8723B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
++#define SET_8723B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
++#define SET_8723B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++
++/* _MACID_CFG_CMD_0x40 */
++#define SET_8723B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8723B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
++#define SET_8723B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
++#define SET_8723B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
++#define SET_8723B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
++#define SET_8723B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
++#define SET_8723B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
++#define SET_8723B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
++#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
++#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
++#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
++
++/* _RSSI_SETTING_CMD_0x42 */
++#define SET_8723B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8723B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
++#define SET_8723B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++
++/* _AP_REQ_TXRPT_CMD_0x43 */
++#define SET_8723B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8723B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++
++/* _FORCE_BT_TXPWR_CMD_0x62 */
++#define SET_8723B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++
++/* _FORCE_BT_MP_OPER_CMD_0x67 */
++#define SET_8723B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
++#define SET_8723B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
++#define SET_8723B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_8723B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
++#define SET_8723B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++#define SET_8723B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
++
++/* _BT_FW_PATCH_0x6A */
++#define SET_8723B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
++#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
++
++/* ---------------------------------------------------------------------------------------------------------
++ * -------------------------------------------    Structure    --------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    Function Statement     --------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++/* host message to firmware cmd */
++void rtl8723b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
++void rtl8723b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
++void rtl8723b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
++/* s32 rtl8723b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
++void rtl8723b_set_FwPsTuneParam_cmd(PADAPTER padapter);
++void rtl8723b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);
++void rtl8723b_download_rsvd_page(PADAPTER padapter, u8 mstatus);
++#ifdef CONFIG_BT_COEXIST
++	void rtl8723b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
++#endif /* CONFIG_BT_COEXIST */
++#ifdef CONFIG_P2P
++	void rtl8723b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
++#endif /* CONFIG_P2P */
++
++#ifdef CONFIG_TDLS
++	#ifdef CONFIG_TDLS_CH_SW
++		void rtl8723b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
++	#endif
++#endif
++
++#ifdef CONFIG_P2P_WOWLAN
++	void rtl8723b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
++#endif
++
++void rtl8723b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
++
++s32 FillH2CCmd8723B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
++u8 GetTxBufferRsvdPageNum8723B(_adapter *padapter, bool wowlan);
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_dm.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_dm.h
+new file mode 100644
+index 000000000..ea517175f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_dm.h
+@@ -0,0 +1,38 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8723B_DM_H__
++#define __RTL8723B_DM_H__
++/* ************************************************************
++ * Description:
++ *
++ * This file is for 8723B dynamic mechanism only
++ *
++ *
++ * ************************************************************ */
++
++/* ************************************************************
++ * structure and define
++ * ************************************************************ */
++
++/* ************************************************************
++ * function prototype
++ * ************************************************************ */
++
++void rtl8723b_init_dm_priv(PADAPTER padapter);
++void rtl8723b_deinit_dm_priv(PADAPTER padapter);
++
++void rtl8723b_InitHalDm(PADAPTER padapter);
++void rtl8723b_HalDmWatchDog(PADAPTER padapter);
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_hal.h
+new file mode 100755
+index 000000000..848350246
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_hal.h
+@@ -0,0 +1,274 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8723B_HAL_H__
++#define __RTL8723B_HAL_H__
++
++#include "hal_data.h"
++
++#include "rtl8723b_spec.h"
++#include "rtl8723b_rf.h"
++#include "rtl8723b_dm.h"
++#include "rtl8723b_recv.h"
++#include "rtl8723b_xmit.h"
++#include "rtl8723b_cmd.h"
++#include "rtl8723b_led.h"
++#include "Hal8723BPwrSeq.h"
++#include "Hal8723BPhyReg.h"
++#include "Hal8723BPhyCfg.h"
++#ifdef DBG_CONFIG_ERROR_DETECT
++	#include "rtl8723b_sreset.h"
++#endif
++
++#define FW_8723B_SIZE			0x8000
++#define FW_8723B_START_ADDRESS	0x1000
++#define FW_8723B_END_ADDRESS		0x1FFF /* 0x5FFF */
++
++#define IS_FW_HEADER_EXIST_8723B(_pFwHdr)	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x5300)
++
++typedef struct _RT_FIRMWARE {
++	FIRMWARE_SOURCE	eFWSource;
++#ifdef CONFIG_EMBEDDED_FWIMG
++	u8			*szFwBuffer;
++#else
++	u8			szFwBuffer[FW_8723B_SIZE];
++#endif
++	u32			ulFwLength;
++} RT_FIRMWARE_8723B, *PRT_FIRMWARE_8723B;
++
++/*
++ * This structure must be cared byte-ordering
++ *
++ * Added by tynli. 2009.12.04. */
++typedef struct _RT_8723B_FIRMWARE_HDR {
++	/* 8-byte alinment required */
++
++	/* --- LONG WORD 0 ---- */
++	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
++	u8		Category;	/* AP/NIC and USB/PCI */
++	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
++	u16		Version;		/* FW Version */
++	u16		Subversion;	/* FW Subversion, default 0x00 */
++
++	/* --- LONG WORD 1 ---- */
++	u8		Month;	/* Release time Month field */
++	u8		Date;	/* Release time Date field */
++	u8		Hour;	/* Release time Hour field */
++	u8		Minute;	/* Release time Minute field */
++	u16		RamCodeSize;	/* The size of RAM code */
++	u16		Rsvd2;
++
++	/* --- LONG WORD 2 ---- */
++	u32		SvnIdx;	/* The SVN entry index */
++	u32		Rsvd3;
++
++	/* --- LONG WORD 3 ---- */
++	u32		Rsvd4;
++	u32		Rsvd5;
++} RT_8723B_FIRMWARE_HDR, *PRT_8723B_FIRMWARE_HDR;
++
++#define DRIVER_EARLY_INT_TIME_8723B		0x05
++#define BCN_DMA_ATIME_INT_TIME_8723B		0x02
++
++/* for 8723B
++ * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
++#define PAGE_SIZE_TX_8723B			128
++#define PAGE_SIZE_RX_8723B			8
++
++#define TX_DMA_SIZE_8723B			0x8000	/* 32K(TX) */
++#define RX_DMA_SIZE_8723B			0x4000	/* 16K(RX) */
++
++#ifdef CONFIG_WOWLAN
++	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
++#else
++	#define RESV_FMWF	0
++#endif
++
++#ifdef CONFIG_FW_C2H_DEBUG
++	#define RX_DMA_RESERVED_SIZE_8723B	0x100	/* 256B, reserved for c2h debug message */
++#else
++	#define RX_DMA_RESERVED_SIZE_8723B	0x80	/* 128B, reserved for tx report */
++#endif
++#define RX_DMA_BOUNDARY_8723B		(RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B - 1)
++
++
++/* Note: We will divide number of page equally for each queue other than public queue! */
++
++/* For General Reserved Page Number(Beacon Queue is reserved page)
++ * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8723B
++ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
++#define BCNQ_PAGE_NUM_8723B		(MAX_BEACON_LEN / PAGE_SIZE_TX_8723B + 6) /*0x08*/
++
++
++/* For WoWLan , more reserved page
++ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6
++ * NS offload: 2 NDP info: 1
++ */
++#ifdef CONFIG_WOWLAN
++	#define WOWLAN_PAGE_NUM_8723B	0x0b
++#else
++	#define WOWLAN_PAGE_NUM_8723B	0x00
++#endif
++
++#ifdef CONFIG_PNO_SUPPORT
++	#undef WOWLAN_PAGE_NUM_8723B
++	#define WOWLAN_PAGE_NUM_8723B	0x15
++#endif
++
++#ifdef CONFIG_AP_WOWLAN
++	#define AP_WOWLAN_PAGE_NUM_8723B	0x02
++#endif
++
++#define TX_TOTAL_PAGE_NUMBER_8723B	(0xFF - BCNQ_PAGE_NUM_8723B - WOWLAN_PAGE_NUM_8723B)
++#define TX_PAGE_BOUNDARY_8723B		(TX_TOTAL_PAGE_NUMBER_8723B + 1)
++
++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723B	TX_TOTAL_PAGE_NUMBER_8723B
++#define WMM_NORMAL_TX_PAGE_BOUNDARY_8723B		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723B + 1)
++
++/* For Normal Chip Setting
++ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723B */
++#define NORMAL_PAGE_NUM_HPQ_8723B		0x0C
++#define NORMAL_PAGE_NUM_LPQ_8723B		0x02
++#define NORMAL_PAGE_NUM_NPQ_8723B		0x02
++#define NORMAL_PAGE_NUM_EPQ_8723B		0x04
++
++/* Note: For Normal Chip Setting, modify later */
++#define WMM_NORMAL_PAGE_NUM_HPQ_8723B		0x30
++#define WMM_NORMAL_PAGE_NUM_LPQ_8723B		0x20
++#define WMM_NORMAL_PAGE_NUM_NPQ_8723B		0x20
++#define WMM_NORMAL_PAGE_NUM_EPQ_8723B		0x00
++
++
++#include "HalVerDef.h"
++#include "hal_com.h"
++
++#define EFUSE_OOB_PROTECT_BYTES		15
++
++#define HAL_EFUSE_MEMORY
++
++#define HWSET_MAX_SIZE_8723B			512
++#define EFUSE_REAL_CONTENT_LEN_8723B		512
++#define EFUSE_MAP_LEN_8723B				512
++#define EFUSE_MAX_SECTION_8723B			64
++
++#define EFUSE_IC_ID_OFFSET			506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
++#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8723B)
++
++#define EFUSE_ACCESS_ON			0x69	/* For RTL8723 only. */
++#define EFUSE_ACCESS_OFF			0x00	/* For RTL8723 only. */
++
++/* ********************************************************
++ *			EFUSE for BT definition
++ * ******************************************************** */
++#define EFUSE_BT_REAL_BANK_CONTENT_LEN	512
++#define EFUSE_BT_REAL_CONTENT_LEN		1536	/* 512*3 */
++#define EFUSE_BT_MAP_LEN				1024	/* 1k bytes */
++#define EFUSE_BT_MAX_SECTION			128		/* 1024/8 */
++
++#define EFUSE_PROTECT_BYTES_BANK		16
++
++typedef enum tag_Package_Definition {
++	PACKAGE_DEFAULT,
++	PACKAGE_QFN68,
++	PACKAGE_TFBGA90,
++	PACKAGE_TFBGA80,
++	PACKAGE_TFBGA79
++} PACKAGE_TYPE_E;
++
++#define INCLUDE_MULTI_FUNC_BT(_Adapter)		(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
++#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
++
++/* rtl8723a_hal_init.c */
++s32 rtl8723b_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
++void rtl8723b_FirmwareSelfReset(PADAPTER padapter);
++void rtl8723b_InitializeFirmwareVars(PADAPTER padapter);
++
++void rtl8723b_InitAntenna_Selection(PADAPTER padapter);
++void rtl8723b_DeinitAntenna_Selection(PADAPTER padapter);
++void rtl8723b_CheckAntenna_Selection(PADAPTER padapter);
++void rtl8723b_init_default_value(PADAPTER padapter);
++
++s32 rtl8723b_InitLLTTable(PADAPTER padapter);
++
++s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
++s32 CardDisableWithoutHWSM(PADAPTER padapter);
++
++/* EFuse */
++u8 GetEEPROMSize8723B(PADAPTER padapter);
++void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
++void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
++void Hal_EfuseParseTxPowerInfo_8723B(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseBTCoexistInfo_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseEEPROMVer_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseChnlPlan_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseCustomerID_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseAntennaDiversity_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseXtal_8723B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
++void Hal_EfuseParseThermalMeter_8723B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
++void Hal_EfuseParsePackageType_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseVoltage_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
++void Hal_EfuseParseBoardType_8723B(PADAPTER Adapter,	u8	*PROMContent, BOOLEAN AutoloadFail);
++
++void rtl8723b_set_hal_ops(struct hal_ops *pHalFunc);
++void init_hal_spec_8723b(_adapter *adapter);
++u8 SetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val);
++void GetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val);
++u8 SetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
++u8 GetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
++
++/* register */
++void rtl8723b_InitBeaconParameters(PADAPTER padapter);
++void rtl8723b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
++void	_InitBurstPktLen_8723BS(PADAPTER Adapter);
++void _8051Reset8723(PADAPTER padapter);
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++	void Hal_DetectWoWMode(PADAPTER pAdapter);
++#endif /* CONFIG_WOWLAN */
++
++void rtl8723b_start_thread(_adapter *padapter);
++void rtl8723b_stop_thread(_adapter *padapter);
++
++#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
++	void rtl8723bs_init_checkbthang_workqueue(_adapter *adapter);
++	void rtl8723bs_free_checkbthang_workqueue(_adapter *adapter);
++	void rtl8723bs_cancle_checkbthang_workqueue(_adapter *adapter);
++	void rtl8723bs_hal_check_bt_hang(_adapter *adapter);
++#endif
++
++#ifdef CONFIG_GPIO_WAKEUP
++	void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
++#endif
++#ifdef CONFIG_MP_INCLUDED
++int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
++#endif
++void CCX_FwC2HTxRpt_8723b(PADAPTER padapter, u8 *pdata, u8 len);
++
++u8 MRateToHwRate8723B(u8  rate);
++u8 HwRateToMRate8723B(u8	 rate);
++
++#ifdef CONFIG_RF_POWER_TRIM
++	void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++#endif /*CONFIG_RF_POWER_TRIM*/
++
++#ifdef CONFIG_PCI_HCI
++	BOOLEAN	InterruptRecognized8723BE(PADAPTER Adapter);
++	void	UpdateInterruptMask8723BE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
++#endif
++
++#ifdef CONFIG_GPIO_API
++int rtl8723b_GpioFuncCheck(PADAPTER adapter, u8 gpio_num);
++void rtl8723b_GpioMultiFuncReset(PADAPTER adapter, u8 gpio_num);
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_led.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_led.h
+new file mode 100755
+index 000000000..6b772cceb
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_led.h
+@@ -0,0 +1,44 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8723B_LED_H__
++#define __RTL8723B_LED_H__
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++#ifdef CONFIG_RTW_SW_LED
++/* ********************************************************************************
++ * Interface to manipulate LED objects.
++ * ******************************************************************************** */
++#ifdef CONFIG_USB_HCI
++	void rtl8723bu_InitSwLeds(PADAPTER padapter);
++	void rtl8723bu_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_SDIO_HCI
++	void rtl8723bs_InitSwLeds(PADAPTER padapter);
++	void rtl8723bs_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_GSPI_HCI
++	void rtl8723bs_InitSwLeds(PADAPTER padapter);
++	void rtl8723bs_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_PCI_HCI
++	void rtl8723be_InitSwLeds(PADAPTER padapter);
++	void rtl8723be_DeInitSwLeds(PADAPTER padapter);
++#endif
++
++#endif
++#endif/*CONFIG_RTW_SW_LED*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_recv.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_recv.h
+new file mode 100755
+index 000000000..5e92713a5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_recv.h
+@@ -0,0 +1,82 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8723B_RECV_H__
++#define __RTL8723B_RECV_H__
++
++#define RECV_BLK_SZ 512
++#define RECV_BLK_CNT 16
++#define RECV_BLK_TH RECV_BLK_CNT
++
++#if defined(CONFIG_USB_HCI)
++
++	#ifndef MAX_RECVBUF_SZ
++		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
++			/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
++			/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
++			/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
++			#ifdef CONFIG_PLATFORM_MSTAR
++				#define MAX_RECVBUF_SZ (8192) /* 8K */
++			#else
++				#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
++			#endif
++			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
++		#else
++			#define MAX_RECVBUF_SZ (4000) /* about 4K */
++		#endif
++	#endif /* !MAX_RECVBUF_SZ */
++
++#elif defined(CONFIG_PCI_HCI)
++	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
++	/*	#define MAX_RECVBUF_SZ (9100) */
++	/* #else */
++	#define MAX_RECVBUF_SZ (4000) /* about 4K
++	* #endif */
++
++
++#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++
++	#define MAX_RECVBUF_SZ  (RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B)
++
++#endif
++
++/* Rx smooth factor */
++#define	Rx_Smooth_Factor (20)
++
++#ifdef CONFIG_SDIO_HCI
++	#ifndef CONFIG_SDIO_RX_COPY
++		#undef MAX_RECVBUF_SZ
++		#define MAX_RECVBUF_SZ	(RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B)
++	#endif /* !CONFIG_SDIO_RX_COPY */
++#endif /* CONFIG_SDIO_HCI */
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	s32 rtl8723bs_init_recv_priv(PADAPTER padapter);
++	void rtl8723bs_free_recv_priv(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_USB_HCI
++	int rtl8723bu_init_recv_priv(_adapter *padapter);
++	void rtl8723bu_free_recv_priv(_adapter *padapter);
++	void rtl8723bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	s32 rtl8723be_init_recv_priv(PADAPTER padapter);
++	void rtl8723be_free_recv_priv(PADAPTER padapter);
++#endif
++
++void rtl8723b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
++
++#endif /* __RTL8723B_RECV_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_rf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_rf.h
+new file mode 100644
+index 000000000..040c16647
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_rf.h
+@@ -0,0 +1,25 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8723B_RF_H__
++#define __RTL8723B_RF_H__
++
++int	PHY_RF6052_Config8723B(PADAPTER		Adapter);
++
++void
++PHY_RF6052SetBandwidth8723B(
++		PADAPTER				Adapter,
++		enum channel_width		Bandwidth);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_spec.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_spec.h
+new file mode 100755
+index 000000000..b0fb4aa41
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_spec.h
+@@ -0,0 +1,280 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8723B_SPEC_H__
++#define __RTL8723B_SPEC_H__
++
++#include <drv_conf.h>
++
++
++#define HAL_NAV_UPPER_UNIT_8723B		128		/* micro-second */
++
++/* -----------------------------------------------------
++ *
++ *	0x0000h ~ 0x00FFh	System Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_RSV_CTRL_8723B				0x001C	/* 3 Byte */
++#define REG_BT_WIFI_ANTENNA_SWITCH_8723B	0x0038
++#define REG_HSISR_8723B					0x005c
++#define REG_PAD_CTRL1_8723B		0x0064
++#define REG_AFE_CTRL_4_8723B		0x0078
++#define REG_HMEBOX_DBG_0_8723B	0x0088
++#define REG_HMEBOX_DBG_1_8723B	0x008A
++#define REG_HMEBOX_DBG_2_8723B	0x008C
++#define REG_HMEBOX_DBG_3_8723B	0x008E
++#define REG_HIMR0_8723B					0x00B0
++#define REG_HISR0_8723B					0x00B4
++#define REG_HIMR1_8723B					0x00B8
++#define REG_HISR1_8723B					0x00BC
++#define REG_PMC_DBG_CTRL2_8723B			0x00CC
++
++/* -----------------------------------------------------
++ *
++ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_C2HEVT_CMD_ID_8723B	0x01A0
++#define REG_C2HEVT_CMD_LEN_8723B	0x01AE
++#define REG_WOWLAN_WAKE_REASON 0x01C7
++#define REG_WOWLAN_GTK_DBG1	0x630
++#define REG_WOWLAN_GTK_DBG2	0x634
++
++#define REG_HMEBOX_EXT0_8723B			0x01F0
++#define REG_HMEBOX_EXT1_8723B			0x01F4
++#define REG_HMEBOX_EXT2_8723B			0x01F8
++#define REG_HMEBOX_EXT3_8723B			0x01FC
++
++/* -----------------------------------------------------
++ *
++ *	0x0200h ~ 0x027Fh	TXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ *
++ *	0x0280h ~ 0x02FFh	RXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_RXDMA_CONTROL_8723B		0x0286 /* Control the RX DMA. */
++#define REG_RXDMA_MODE_CTRL_8723B		0x0290
++
++/* -----------------------------------------------------
++ *
++ *	0x0300h ~ 0x03FFh	PCIe
++ *
++ * ----------------------------------------------------- */
++#define	REG_PCIE_CTRL_REG_8723B		0x0300
++#define	REG_INT_MIG_8723B				0x0304	/* Interrupt Migration */
++#define	REG_BCNQ_DESA_8723B			0x0308	/* TX Beacon Descriptor Address */
++#define	REG_HQ_DESA_8723B				0x0310	/* TX High Queue Descriptor Address */
++#define	REG_MGQ_DESA_8723B			0x0318	/* TX Manage Queue Descriptor Address */
++#define	REG_VOQ_DESA_8723B			0x0320	/* TX VO Queue Descriptor Address */
++#define	REG_VIQ_DESA_8723B				0x0328	/* TX VI Queue Descriptor Address */
++#define	REG_BEQ_DESA_8723B			0x0330	/* TX BE Queue Descriptor Address */
++#define	REG_BKQ_DESA_8723B			0x0338	/* TX BK Queue Descriptor Address */
++#define	REG_RX_DESA_8723B				0x0340	/* RX Queue	Descriptor Address */
++#define	REG_DBI_WDATA_8723B			0x0348	/* DBI Write Data */
++#define	REG_DBI_RDATA_8723B			0x034C	/* DBI Read Data */
++#define	REG_DBI_ADDR_8723B				0x0350	/* DBI Address */
++#define	REG_DBI_FLAG_8723B				0x0352	/* DBI Read/Write Flag */
++#define	REG_MDIO_WDATA_8723B		0x0354	/* MDIO for Write PCIE PHY */
++#define	REG_MDIO_RDATA_8723B			0x0356	/* MDIO for Reads PCIE PHY */
++#define	REG_MDIO_CTL_8723B			0x0358	/* MDIO for Control */
++#define	REG_DBG_SEL_8723B				0x0360	/* Debug Selection Register */
++#define	REG_PCIE_HRPWM_8723B			0x0361	/* PCIe RPWM */
++#define	REG_PCIE_HCPWM_8723B			0x0363	/* PCIe CPWM */
++#define	REG_PCIE_MULTIFET_CTRL_8723B	0x036A	/* PCIE Multi-Fethc Control */
++
++/* -----------------------------------------------------
++ *
++ *	0x0400h ~ 0x047Fh	Protocol Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_TXPKTBUF_BCNQ_BDNY_8723B	0x0424
++#define REG_TXPKTBUF_MGQ_BDNY_8723B	0x0425
++#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B	0x045D
++#ifdef CONFIG_WOWLAN
++	#define REG_TXPKTBUF_IV_LOW             0x0484
++	#define REG_TXPKTBUF_IV_HIGH            0x0488
++#endif
++#define REG_AMPDU_BURST_MODE_8723B	0x04BC
++
++/* -----------------------------------------------------
++ *
++ *	0x0500h ~ 0x05FFh	EDCA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_SECONDARY_CCA_CTRL_8723B	0x0577
++
++/* -----------------------------------------------------
++ *
++ *	0x0600h ~ 0x07FFh	WMAC Configuration
++ *
++ * ----------------------------------------------------- */
++
++
++/* ************************************************************
++ * SDIO Bus Specification
++ * ************************************************************ */
++
++/* -----------------------------------------------------
++ * SDIO CMD Address Mapping
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ * I/O bus domain (Host)
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ * SDIO register
++ * ----------------------------------------------------- */
++#define SDIO_REG_HCPWM1_8723B	0x025 /* HCI Current Power Mode 1 */
++
++
++/* ****************************************************************************
++ *	8723 Regsiter Bit and Content definition
++ * **************************************************************************** */
++
++/* 2 HSISR
++ * interrupt mask which needs to clear */
++#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
++		HSISR_SPS_OCP_INT |\
++		HSISR_RON_INT |\
++		HSISR_PDNINT |\
++		HSISR_GPIO9_INT)
++
++/* -----------------------------------------------------
++ *
++ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
++ *
++ * ----------------------------------------------------- */
++#undef IS_E_CUT
++#define IS_E_CUT(version)		FALSE
++#undef IS_F_CUT
++#define IS_F_CUT(version)		((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE)
++
++/* -----------------------------------------------------
++ *
++ *	0x0200h ~ 0x027Fh	TXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ *
++ *	0x0280h ~ 0x02FFh	RXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++#define BIT_USB_RXDMA_AGG_EN	BIT(31)
++#define RXDMA_AGG_MODE_EN		BIT(1)
++
++#ifdef CONFIG_WOWLAN
++	#define RXPKT_RELEASE_POLL		BIT(16)
++	#define RXDMA_IDLE				BIT(17)
++	#define RW_RELEASE_EN			BIT(18)
++#endif
++
++/* -----------------------------------------------------
++ *
++ *	0x0400h ~ 0x047Fh	Protocol Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* ----------------------------------------------------------------------------
++ * 8723B REG_CCK_CHECK						(offset 0x454)
++ * ---------------------------------------------------------------------------- */
++#define BIT_BCN_PORT_SEL		BIT(5)
++
++/* -----------------------------------------------------
++ *
++ *	0x0500h ~ 0x05FFh	EDCA Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ *
++ *	0x0600h ~ 0x07FFh	WMAC Configuration
++ *
++ * ----------------------------------------------------- */
++#ifdef CONFIG_RF_POWER_TRIM
++
++	#ifdef CONFIG_RTL8723B
++		#define EEPROM_RF_GAIN_OFFSET			0xC1
++	#endif
++
++	#define EEPROM_RF_GAIN_VAL				0x1F6
++#endif /*CONFIG_RF_POWER_TRIM*/
++
++
++/* ----------------------------------------------------------------------------
++ * 8195 IMR/ISR bits						(offset 0xB0,  8bits)
++ * ---------------------------------------------------------------------------- */
++#define	IMR_DISABLED_8723B					0
++/* IMR DW0(0x00B0-00B3) Bit 0-31 */
++#define	IMR_TIMER2_8723B					BIT(31)		/* Timeout interrupt 2 */
++#define	IMR_TIMER1_8723B					BIT(30)		/* Timeout interrupt 1	 */
++#define	IMR_PSTIMEOUT_8723B				BIT(29)		/* Power Save Time Out Interrupt */
++#define	IMR_GTINT4_8723B					BIT(28)		/* When GTIMER4 expires, this bit is set to 1	 */
++#define	IMR_GTINT3_8723B					BIT(27)		/* When GTIMER3 expires, this bit is set to 1	 */
++#define	IMR_TXBCN0ERR_8723B				BIT(26)		/* Transmit Beacon0 Error			 */
++#define	IMR_TXBCN0OK_8723B				BIT(25)		/* Transmit Beacon0 OK			 */
++#define	IMR_TSF_BIT32_TOGGLE_8723B		BIT(24)		/* TSF Timer BIT(32) toggle indication interrupt			 */
++#define	IMR_BCNDMAINT0_8723B				BIT(20)		/* Beacon DMA Interrupt 0			 */
++#define	IMR_BCNDERR0_8723B				BIT(16)		/* Beacon Queue DMA OK0			 */
++#define	IMR_HSISR_IND_ON_INT_8723B		BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
++#define	IMR_BCNDMAINT_E_8723B			BIT(14)		/* Beacon DMA Interrupt Extension for Win7			 */
++#define	IMR_ATIMEND_8723B				BIT(12)		/* CTWidnow End or ATIM Window End */
++#define	IMR_C2HCMD_8723B					BIT(10)		/* CPU to Host Command INT Status, Write 1 clear	 */
++#define	IMR_CPWM2_8723B					BIT(9)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
++#define	IMR_CPWM_8723B					BIT(8)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
++#define	IMR_HIGHDOK_8723B				BIT(7)			/* High Queue DMA OK	 */
++#define	IMR_MGNTDOK_8723B				BIT(6)			/* Management Queue DMA OK	 */
++#define	IMR_BKDOK_8723B					BIT(5)			/* AC_BK DMA OK		 */
++#define	IMR_BEDOK_8723B					BIT(4)			/* AC_BE DMA OK	 */
++#define	IMR_VIDOK_8723B					BIT(3)			/* AC_VI DMA OK		 */
++#define	IMR_VODOK_8723B					BIT(2)			/* AC_VO DMA OK	 */
++#define	IMR_RDU_8723B					BIT(1)			/* Rx Descriptor Unavailable	 */
++#define	IMR_ROK_8723B					BIT(0)			/* Receive DMA OK */
++
++/* IMR DW1(0x00B4-00B7) Bit 0-31 */
++#define	IMR_BCNDMAINT7_8723B				BIT(27)		/* Beacon DMA Interrupt 7 */
++#define	IMR_BCNDMAINT6_8723B				BIT(26)		/* Beacon DMA Interrupt 6 */
++#define	IMR_BCNDMAINT5_8723B				BIT(25)		/* Beacon DMA Interrupt 5 */
++#define	IMR_BCNDMAINT4_8723B				BIT(24)		/* Beacon DMA Interrupt 4 */
++#define	IMR_BCNDMAINT3_8723B				BIT(23)		/* Beacon DMA Interrupt 3 */
++#define	IMR_BCNDMAINT2_8723B				BIT(22)		/* Beacon DMA Interrupt 2 */
++#define	IMR_BCNDMAINT1_8723B				BIT(21)		/* Beacon DMA Interrupt 1 */
++#define	IMR_BCNDOK7_8723B					BIT(20)		/* Beacon Queue DMA OK Interrupt 7 */
++#define	IMR_BCNDOK6_8723B					BIT(19)		/* Beacon Queue DMA OK Interrupt 6 */
++#define	IMR_BCNDOK5_8723B					BIT(18)		/* Beacon Queue DMA OK Interrupt 5 */
++#define	IMR_BCNDOK4_8723B					BIT(17)		/* Beacon Queue DMA OK Interrupt 4 */
++#define	IMR_BCNDOK3_8723B					BIT(16)		/* Beacon Queue DMA OK Interrupt 3 */
++#define	IMR_BCNDOK2_8723B					BIT(15)		/* Beacon Queue DMA OK Interrupt 2 */
++#define	IMR_BCNDOK1_8723B					BIT(14)		/* Beacon Queue DMA OK Interrupt 1 */
++#define	IMR_ATIMEND_E_8723B				BIT(13)		/* ATIM Window End Extension for Win7 */
++#define	IMR_TXERR_8723B					BIT(11)		/* Tx Error Flag Interrupt Status, write 1 clear. */
++#define	IMR_RXERR_8723B					BIT(10)		/* Rx Error Flag INT Status, Write 1 clear */
++#define	IMR_TXFOVW_8723B					BIT(9)			/* Transmit FIFO Overflow */
++#define	IMR_RXFOVW_8723B					BIT(8)			/* Receive FIFO Overflow */
++
++#ifdef CONFIG_PCI_HCI
++	/* #define IMR_RX_MASK		(IMR_ROK_8723B|IMR_RDU_8723B|IMR_RXFOVW_8723B) */
++	#define IMR_TX_MASK			(IMR_VODOK_8723B | IMR_VIDOK_8723B | IMR_BEDOK_8723B | IMR_BKDOK_8723B | IMR_MGNTDOK_8723B | IMR_HIGHDOK_8723B)
++
++	#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8723B | IMR_TXBCN0OK_8723B | IMR_TXBCN0ERR_8723B | IMR_BCNDERR0_8723B)
++
++	#define RT_AC_INT_MASKS	(IMR_VIDOK_8723B | IMR_VODOK_8723B | IMR_BEDOK_8723B | IMR_BKDOK_8723B)
++#endif
++
++#endif /* __RTL8723B_SPEC_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_sreset.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_sreset.h
+new file mode 100644
+index 000000000..c97f2648a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_sreset.h
+@@ -0,0 +1,24 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8723B_SRESET_H_
++#define _RTL8723B_SRESET_H_
++
++#include <rtw_sreset.h>
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++	extern void rtl8723b_sreset_xmit_status_check(_adapter *padapter);
++	extern void rtl8723b_sreset_linked_status_check(_adapter *padapter);
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_xmit.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_xmit.h
+new file mode 100755
+index 000000000..a0d3f5ebd
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723b_xmit.h
+@@ -0,0 +1,333 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8723B_XMIT_H__
++#define __RTL8723B_XMIT_H__
++
++
++#define MAX_TID (15)
++
++
++#ifndef __INC_HAL8723BDESC_H
++	#define __INC_HAL8723BDESC_H
++
++	#define RX_STATUS_DESC_SIZE_8723B		24
++	#define RX_DRV_INFO_SIZE_UNIT_8723B 8
++
++
++	/* DWORD 0 */
++	#define SET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
++	#define SET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
++	#define SET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
++
++	#define GET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
++	#define GET_RX_STATUS_DESC_CRC32_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
++	#define GET_RX_STATUS_DESC_ICV_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
++	#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
++	#define GET_RX_STATUS_DESC_SECURITY_8723B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
++	#define GET_RX_STATUS_DESC_QOS_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
++	#define GET_RX_STATUS_DESC_SHIFT_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
++	#define GET_RX_STATUS_DESC_PHY_STATUS_8723B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
++	#define GET_RX_STATUS_DESC_SWDEC_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
++	#define GET_RX_STATUS_DESC_LAST_SEG_8723B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
++	#define GET_RX_STATUS_DESC_FIRST_SEG_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
++	#define GET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
++	#define GET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
++
++	/* DWORD 1 */
++	#define GET_RX_STATUS_DESC_MACID_8723B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
++	#define GET_RX_STATUS_DESC_TID_8723B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
++	#define GET_RX_STATUS_DESC_AMSDU_8723B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
++	#define GET_RX_STATUS_DESC_RXID_MATCH_8723B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
++	#define GET_RX_STATUS_DESC_PAGGR_8723B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
++	#define GET_RX_STATUS_DESC_A1_FIT_8723B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
++	#define GET_RX_STATUS_DESC_CHKERR_8723B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
++	#define GET_RX_STATUS_DESC_IPVER_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
++	#define GET_RX_STATUS_DESC_IS_TCPUDP__8723B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
++	#define GET_RX_STATUS_DESC_CHK_VLD_8723B(__pRxDesc)	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
++	#define GET_RX_STATUS_DESC_PAM_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
++	#define GET_RX_STATUS_DESC_PWR_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
++	#define GET_RX_STATUS_DESC_MORE_DATA_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
++	#define GET_RX_STATUS_DESC_MORE_FRAG_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
++	#define GET_RX_STATUS_DESC_TYPE_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
++	#define GET_RX_STATUS_DESC_MC_8723B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
++	#define GET_RX_STATUS_DESC_BC_8723B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
++
++	/* DWORD 2 */
++	#define GET_RX_STATUS_DESC_SEQ_8723B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
++	#define GET_RX_STATUS_DESC_FRAG_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
++	#define GET_RX_STATUS_DESC_RX_IS_QOS_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
++	#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723B(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
++	#define GET_RX_STATUS_DESC_RPT_SEL_8723B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
++
++	/* DWORD 3 */
++	#define GET_RX_STATUS_DESC_RX_RATE_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
++	#define GET_RX_STATUS_DESC_HTC_8723B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
++	#define GET_RX_STATUS_DESC_EOSP_8723B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
++	#define GET_RX_STATUS_DESC_BSSID_FIT_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
++	#ifdef CONFIG_USB_RX_AGGREGATION
++		#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8723B(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
++	#endif
++	#define GET_RX_STATUS_DESC_PATTERN_MATCH_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
++	#define GET_RX_STATUS_DESC_UNICAST_MATCH_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
++	#define GET_RX_STATUS_DESC_MAGIC_MATCH_8723B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
++
++	/* DWORD 6 */
++	#define GET_RX_STATUS_DESC_SPLCP_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
++	#define GET_RX_STATUS_DESC_LDPC_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
++	#define GET_RX_STATUS_DESC_STBC_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
++	#define GET_RX_STATUS_DESC_BW_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
++
++	/* DWORD 5 */
++	#define GET_RX_STATUS_DESC_TSFL_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
++
++	#define GET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
++	#define GET_RX_STATUS_DESC_BUFF_ADDR64_8723B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
++
++	#define SET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
++
++
++	/* Dword 0 */
++	#define GET_TX_DESC_OWN_8723B(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
++
++	#define SET_TX_DESC_PKT_SIZE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
++	#define SET_TX_DESC_OFFSET_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
++	#define SET_TX_DESC_BMC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
++	#define SET_TX_DESC_HTC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
++	#define SET_TX_DESC_LAST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
++	#define SET_TX_DESC_FIRST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
++	#define SET_TX_DESC_LINIP_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
++	#define SET_TX_DESC_NO_ACM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
++	#define SET_TX_DESC_GF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
++	#define SET_TX_DESC_OWN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
++
++	/* Dword 1 */
++	#define SET_TX_DESC_MACID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
++	#define SET_TX_DESC_QUEUE_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
++	#define SET_TX_DESC_RDG_NAV_EXT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
++	#define SET_TX_DESC_LSIG_TXOP_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
++	#define SET_TX_DESC_PIFS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
++	#define SET_TX_DESC_RATE_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
++	#define SET_TX_DESC_EN_DESC_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
++	#define SET_TX_DESC_SEC_TYPE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
++	#define SET_TX_DESC_PKT_OFFSET_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
++
++
++	/* Dword 2 */
++	#define SET_TX_DESC_PAID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
++	#define SET_TX_DESC_CCA_RTS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
++	#define SET_TX_DESC_AGG_ENABLE_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
++	#define SET_TX_DESC_RDG_ENABLE_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
++	#define SET_TX_DESC_AGG_BREAK_8723B(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
++	#define SET_TX_DESC_MORE_FRAG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
++	#define SET_TX_DESC_RAW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
++	#define SET_TX_DESC_SPE_RPT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
++	#define SET_TX_DESC_AMPDU_DENSITY_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
++	#define SET_TX_DESC_BT_INT_8723B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
++	#define SET_TX_DESC_GID_8723B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
++
++
++	/* Dword 3 */
++	#define SET_TX_DESC_WHEADER_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
++	#define SET_TX_DESC_CHK_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
++	#define SET_TX_DESC_EARLY_MODE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
++	#define SET_TX_DESC_HWSEQ_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
++	#define SET_TX_DESC_USE_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
++	#define SET_TX_DESC_DISABLE_RTS_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
++	#define SET_TX_DESC_DISABLE_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
++	#define SET_TX_DESC_CTS2SELF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
++	#define SET_TX_DESC_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
++	#define SET_TX_DESC_HW_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
++	#define SET_TX_DESC_NAV_USE_HDR_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
++	#define SET_TX_DESC_USE_MAX_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
++	#define SET_TX_DESC_MAX_AGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
++	#define SET_TX_DESC_NDPA_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
++	#define SET_TX_DESC_AMPDU_MAX_TIME_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
++
++	/* Dword 4 */
++	#define SET_TX_DESC_TX_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
++	#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
++	#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
++	#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
++	#define SET_TX_DESC_DATA_RETRY_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
++	#define SET_TX_DESC_RTS_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
++
++
++	/* Dword 5 */
++	#define SET_TX_DESC_DATA_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
++	#define SET_TX_DESC_DATA_SHORT_8723B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
++	#define SET_TX_DESC_DATA_BW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
++	#define SET_TX_DESC_DATA_LDPC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
++	#define SET_TX_DESC_DATA_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
++	#define SET_TX_DESC_CTROL_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
++	#define SET_TX_DESC_RTS_SHORT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
++	#define SET_TX_DESC_RTS_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
++
++
++	/* Dword 6 */
++	#define SET_TX_DESC_SW_DEFINE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
++	#define SET_TX_DESC_MBSSID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
++	#define SET_TX_DESC_ANTSEL_A_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
++	#define SET_TX_DESC_ANTSEL_B_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
++	#define SET_TX_DESC_ANTSEL_C_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
++	#define SET_TX_DESC_ANTSEL_D_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
++
++	/* Dword 7 */
++	#ifdef CONFIG_PCI_HCI
++		#define SET_TX_DESC_TX_BUFFER_SIZE_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++	#endif
++	#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
++		#define SET_TX_DESC_TX_DESC_CHECKSUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++	#endif
++	#define SET_TX_DESC_USB_TXAGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
++	#ifdef CONFIG_SDIO_HCI
++		#define SET_TX_DESC_SDIO_TXSEQ_8723B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
++	#endif
++
++	/* Dword 8 */
++	#define SET_TX_DESC_HWSEQ_EN_8723B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
++
++	/* Dword 9 */
++	#define SET_TX_DESC_SEQ_8723B(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
++
++	/* Dword 10 */
++	#define SET_TX_DESC_TX_BUFFER_ADDRESS_8723B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
++	#define GET_TX_DESC_TX_BUFFER_ADDRESS_8723B(__pTxDesc)	LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
++
++	/* Dword 11 */
++	#define SET_TX_DESC_NEXT_DESC_ADDRESS_8723B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
++
++
++	#define SET_EARLYMODE_PKTNUM_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
++	#define SET_EARLYMODE_LEN0_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
++	#define SET_EARLYMODE_LEN1_1_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
++	#define SET_EARLYMODE_LEN1_2_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
++	#define SET_EARLYMODE_LEN2_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
++	#define SET_EARLYMODE_LEN3_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
++
++#endif
++/* -----------------------------------------------------------
++ *
++ *	Rate
++ *
++ * -----------------------------------------------------------
++ * CCK Rates, TxHT = 0 */
++#define DESC8723B_RATE1M				0x00
++#define DESC8723B_RATE2M				0x01
++#define DESC8723B_RATE5_5M				0x02
++#define DESC8723B_RATE11M				0x03
++
++/* OFDM Rates, TxHT = 0 */
++#define DESC8723B_RATE6M				0x04
++#define DESC8723B_RATE9M				0x05
++#define DESC8723B_RATE12M				0x06
++#define DESC8723B_RATE18M				0x07
++#define DESC8723B_RATE24M				0x08
++#define DESC8723B_RATE36M				0x09
++#define DESC8723B_RATE48M				0x0a
++#define DESC8723B_RATE54M				0x0b
++
++/* MCS Rates, TxHT = 1 */
++#define DESC8723B_RATEMCS0				0x0c
++#define DESC8723B_RATEMCS1				0x0d
++#define DESC8723B_RATEMCS2				0x0e
++#define DESC8723B_RATEMCS3				0x0f
++#define DESC8723B_RATEMCS4				0x10
++#define DESC8723B_RATEMCS5				0x11
++#define DESC8723B_RATEMCS6				0x12
++#define DESC8723B_RATEMCS7				0x13
++#define DESC8723B_RATEMCS8				0x14
++#define DESC8723B_RATEMCS9				0x15
++#define DESC8723B_RATEMCS10		0x16
++#define DESC8723B_RATEMCS11		0x17
++#define DESC8723B_RATEMCS12		0x18
++#define DESC8723B_RATEMCS13		0x19
++#define DESC8723B_RATEMCS14		0x1a
++#define DESC8723B_RATEMCS15		0x1b
++#define DESC8723B_RATEVHTSS1MCS0		0x2c
++#define DESC8723B_RATEVHTSS1MCS1		0x2d
++#define DESC8723B_RATEVHTSS1MCS2		0x2e
++#define DESC8723B_RATEVHTSS1MCS3		0x2f
++#define DESC8723B_RATEVHTSS1MCS4		0x30
++#define DESC8723B_RATEVHTSS1MCS5		0x31
++#define DESC8723B_RATEVHTSS1MCS6		0x32
++#define DESC8723B_RATEVHTSS1MCS7		0x33
++#define DESC8723B_RATEVHTSS1MCS8		0x34
++#define DESC8723B_RATEVHTSS1MCS9		0x35
++#define DESC8723B_RATEVHTSS2MCS0		0x36
++#define DESC8723B_RATEVHTSS2MCS1		0x37
++#define DESC8723B_RATEVHTSS2MCS2		0x38
++#define DESC8723B_RATEVHTSS2MCS3		0x39
++#define DESC8723B_RATEVHTSS2MCS4		0x3a
++#define DESC8723B_RATEVHTSS2MCS5		0x3b
++#define DESC8723B_RATEVHTSS2MCS6		0x3c
++#define DESC8723B_RATEVHTSS2MCS7		0x3d
++#define DESC8723B_RATEVHTSS2MCS8		0x3e
++#define DESC8723B_RATEVHTSS2MCS9		0x3f
++
++
++#define	RX_HAL_IS_CCK_RATE_8723B(pDesc)\
++	(GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE1M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE2M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE5_5M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE11M)
++
++
++void rtl8723b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
++void rtl8723b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
++void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
++void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	s32 rtl8723bs_init_xmit_priv(PADAPTER padapter);
++	void rtl8723bs_free_xmit_priv(PADAPTER padapter);
++	s32 rtl8723bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8723bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	rtl8723bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8723bs_xmit_buf_handler(PADAPTER padapter);
++	thread_return rtl8723bs_xmit_thread(thread_context context);
++	#define hal_xmit_handler rtl8723bs_xmit_buf_handler
++#endif
++
++#ifdef CONFIG_USB_HCI
++	s32 rtl8723bu_xmit_buf_handler(PADAPTER padapter);
++	#define hal_xmit_handler rtl8723bu_xmit_buf_handler
++
++
++	s32 rtl8723bu_init_xmit_priv(PADAPTER padapter);
++	void rtl8723bu_free_xmit_priv(PADAPTER padapter);
++	s32 rtl8723bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8723bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	 rtl8723bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	/* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */
++	void rtl8723bu_xmit_tasklet(void *priv);
++	s32 rtl8723bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++	void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	s32 rtl8723be_init_xmit_priv(PADAPTER padapter);
++	void rtl8723be_free_xmit_priv(PADAPTER padapter);
++	struct xmit_buf *rtl8723be_dequeue_xmitbuf(struct rtw_tx_ring *ring);
++	void	rtl8723be_xmitframe_resume(_adapter *padapter);
++	s32 rtl8723be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8723be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	rtl8723be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	void rtl8723be_xmit_tasklet(void *priv);
++#endif
++
++u8	BWMapping_8723B(PADAPTER Adapter, struct pkt_attrib *pattrib);
++u8	SCMapping_8723B(PADAPTER Adapter, struct pkt_attrib	*pattrib);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_cmd.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_cmd.h
+new file mode 100644
+index 000000000..41c6cb9b0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_cmd.h
+@@ -0,0 +1,189 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8723D_CMD_H__
++#define __RTL8723D_CMD_H__
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++enum h2c_cmd_8723D {
++	/* Common Class: 000 */
++	H2C_8723D_RSVD_PAGE = 0x00,
++	H2C_8723D_MEDIA_STATUS_RPT = 0x01,
++	H2C_8723D_SCAN_ENABLE = 0x02,
++	H2C_8723D_KEEP_ALIVE = 0x03,
++	H2C_8723D_DISCON_DECISION = 0x04,
++	H2C_8723D_PSD_OFFLOAD = 0x05,
++	H2C_8723D_AP_OFFLOAD = 0x08,
++	H2C_8723D_BCN_RSVDPAGE = 0x09,
++	H2C_8723D_PROBERSP_RSVDPAGE = 0x0A,
++	H2C_8723D_FCS_RSVDPAGE = 0x10,
++	H2C_8723D_FCS_INFO = 0x11,
++	H2C_8723D_AP_WOW_GPIO_CTRL = 0x13,
++
++	/* PoweSave Class: 001 */
++	H2C_8723D_SET_PWR_MODE = 0x20,
++	H2C_8723D_PS_TUNING_PARA = 0x21,
++	H2C_8723D_PS_TUNING_PARA2 = 0x22,
++	H2C_8723D_P2P_LPS_PARAM = 0x23,
++	H2C_8723D_P2P_PS_OFFLOAD = 0x24,
++	H2C_8723D_PS_SCAN_ENABLE = 0x25,
++	H2C_8723D_SAP_PS_ = 0x26,
++	H2C_8723D_INACTIVE_PS_ = 0x27, /* Inactive_PS */
++	H2C_8723D_FWLPS_IN_IPS_ = 0x28,
++
++	/* Dynamic Mechanism Class: 010 */
++	H2C_8723D_MACID_CFG = 0x40,
++	H2C_8723D_TXBF = 0x41,
++	H2C_8723D_RSSI_SETTING = 0x42,
++	H2C_8723D_AP_REQ_TXRPT = 0x43,
++	H2C_8723D_INIT_RATE_COLLECT = 0x44,
++	H2C_8723D_RA_PARA_ADJUST = 0x46,
++
++	/* BT Class: 011 */
++	H2C_8723D_B_TYPE_TDMA = 0x60,
++	H2C_8723D_BT_INFO = 0x61,
++	H2C_8723D_FORCE_BT_TXPWR = 0x62,
++	H2C_8723D_BT_IGNORE_WLANACT = 0x63,
++	H2C_8723D_DAC_SWING_VALUE = 0x64,
++	H2C_8723D_ANT_SEL_RSV = 0x65,
++	H2C_8723D_WL_OPMODE = 0x66,
++	H2C_8723D_BT_MP_OPER = 0x67,
++	H2C_8723D_BT_CONTROL = 0x68,
++	H2C_8723D_BT_WIFI_CTRL = 0x69,
++	H2C_8723D_BT_FW_PATCH = 0x6A,
++	H2C_8723D_BT_WLAN_CALIBRATION = 0x6D,
++
++	/* WOWLAN Class: 100 */
++	H2C_8723D_WOWLAN = 0x80,
++	H2C_8723D_REMOTE_WAKE_CTRL = 0x81,
++	H2C_8723D_AOAC_GLOBAL_INFO = 0x82,
++	H2C_8723D_AOAC_RSVD_PAGE = 0x83,
++	H2C_8723D_AOAC_RSVD_PAGE2 = 0x84,
++	H2C_8723D_D0_SCAN_OFFLOAD_CTRL = 0x85,
++	H2C_8723D_D0_SCAN_OFFLOAD_INFO = 0x86,
++	H2C_8723D_CHNL_SWITCH_OFFLOAD = 0x87,
++	H2C_8723D_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
++	H2C_8723D_P2P_OFFLOAD = 0x8B,
++
++	H2C_8723D_RESET_TSF = 0xC0,
++	H2C_8723D_MAXID,
++};
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
++ * ---------------------------------------------------------------------------------------------------------
++ * _RSVDPAGE_LOC_CMD_0x00 */
++#define SET_8723D_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8723D_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_8723D_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8723D_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8723D_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++/* _PWR_MOD_CMD_0x20 */
++#define SET_8723D_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8723D_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
++#define SET_8723D_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
++#define SET_8723D_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8723D_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8723D_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
++#define SET_8723D_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++#define GET_8723D_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
++
++/* _PS_TUNE_PARAM_CMD_0x21 */
++#define SET_8723D_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8723D_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_8723D_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
++#define SET_8723D_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
++#define SET_8723D_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++
++/* _MACID_CFG_CMD_0x40 */
++#define SET_8723D_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8723D_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
++#define SET_8723D_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
++#define SET_8723D_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
++#define SET_8723D_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
++#define SET_8723D_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
++#define SET_8723D_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
++#define SET_8723D_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
++#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
++#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
++#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
++
++/* _RSSI_SETTING_CMD_0x42 */
++#define SET_8723D_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8723D_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
++#define SET_8723D_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++
++/* _AP_REQ_TXRPT_CMD_0x43 */
++#define SET_8723D_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8723D_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++
++/* _FORCE_BT_TXPWR_CMD_0x62 */
++#define SET_8723D_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++
++/* _FORCE_BT_MP_OPER_CMD_0x67 */
++#define SET_8723D_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
++#define SET_8723D_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
++#define SET_8723D_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
++#define SET_8723D_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
++#define SET_8723D_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
++#define SET_8723D_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
++
++/* _BT_FW_PATCH_0x6A */
++#define SET_8723D_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
++#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
++
++/* ---------------------------------------------------------------------------------------------------------
++ * -------------------------------------------    Structure    --------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++
++/* ---------------------------------------------------------------------------------------------------------
++ * ----------------------------------    Function Statement     --------------------------------------------------
++ * --------------------------------------------------------------------------------------------------------- */
++
++/* host message to firmware cmd */
++void rtl8723d_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
++void rtl8723d_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
++/* s32 rtl8723d_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
++void rtl8723d_set_FwPsTuneParam_cmd(PADAPTER padapter);
++void rtl8723d_download_rsvd_page(PADAPTER padapter, u8 mstatus);
++#ifdef CONFIG_BT_COEXIST
++	void rtl8723d_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
++#endif /* CONFIG_BT_COEXIST */
++#ifdef CONFIG_P2P
++	void rtl8723d_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
++#endif /* CONFIG_P2P */
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_TDLS_CH_SW
++void rtl8723d_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
++#endif
++#endif
++
++#ifdef CONFIG_P2P_WOWLAN
++	void rtl8723d_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
++#endif
++
++s32 FillH2CCmd8723D(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
++u8 GetTxBufferRsvdPageNum8723D(_adapter *padapter, bool wowlan);
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_dm.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_dm.h
+new file mode 100644
+index 000000000..0612f0620
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_dm.h
+@@ -0,0 +1,39 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8723D_DM_H__
++#define __RTL8723D_DM_H__
++/* ************************************************************
++ * Description:
++ *
++ * This file is for 8723D dynamic mechanism only
++ *
++ *
++ * ************************************************************ */
++
++/* ************************************************************
++ * structure and define
++ * ************************************************************ */
++
++/* ************************************************************
++ * function prototype
++ * ************************************************************ */
++
++void rtl8723d_init_dm_priv(PADAPTER padapter);
++void rtl8723d_deinit_dm_priv(PADAPTER padapter);
++
++void rtl8723d_InitHalDm(PADAPTER padapter);
++void rtl8723d_HalDmWatchDog(PADAPTER padapter);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_hal.h
+new file mode 100644
+index 000000000..d18e9abc9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_hal.h
+@@ -0,0 +1,303 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8723D_HAL_H__
++#define __RTL8723D_HAL_H__
++
++#include "hal_data.h"
++
++#include "rtl8723d_spec.h"
++#include "rtl8723d_rf.h"
++#include "rtl8723d_dm.h"
++#include "rtl8723d_recv.h"
++#include "rtl8723d_xmit.h"
++#include "rtl8723d_cmd.h"
++#include "rtl8723d_led.h"
++#include "Hal8723DPwrSeq.h"
++#include "Hal8723DPhyReg.h"
++#include "Hal8723DPhyCfg.h"
++#ifdef DBG_CONFIG_ERROR_DETECT
++	#include "rtl8723d_sreset.h"
++#endif
++#ifdef CONFIG_LPS_POFF
++	#include "rtl8723d_lps_poff.h"
++#endif
++
++#define FW_8723D_SIZE		0x8000
++#define FW_8723D_START_ADDRESS	0x1000
++#define FW_8723D_END_ADDRESS	0x1FFF /* 0x5FFF */
++
++#define IS_FW_HEADER_EXIST_8723D(_pFwHdr)\
++	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x23D0)
++
++typedef struct _RT_FIRMWARE {
++	FIRMWARE_SOURCE	eFWSource;
++#ifdef CONFIG_EMBEDDED_FWIMG
++	u8			*szFwBuffer;
++#else
++	u8			szFwBuffer[FW_8723D_SIZE];
++#endif
++	u32			ulFwLength;
++} RT_FIRMWARE_8723D, *PRT_FIRMWARE_8723D;
++
++/*
++ * This structure must be cared byte-ordering
++ *
++ * Added by tynli. 2009.12.04. */
++typedef struct _RT_8723D_FIRMWARE_HDR {
++	/* 8-byte alinment required */
++
++	/* --- LONG WORD 0 ---- */
++	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
++	u8		Category;	/* AP/NIC and USB/PCI */
++	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
++	u16		Version;		/* FW Version */
++	u16		Subversion;	/* FW Subversion, default 0x00 */
++
++	/* --- LONG WORD 1 ---- */
++	u8		Month;	/* Release time Month field */
++	u8		Date;	/* Release time Date field */
++	u8		Hour;	/* Release time Hour field */
++	u8		Minute;	/* Release time Minute field */
++	u16		RamCodeSize;	/* The size of RAM code */
++	u16		Rsvd2;
++
++	/* --- LONG WORD 2 ---- */
++	u32		SvnIdx;	/* The SVN entry index */
++	u32		Rsvd3;
++
++	/* --- LONG WORD 3 ---- */
++	u32		Rsvd4;
++	u32		Rsvd5;
++} RT_8723D_FIRMWARE_HDR, *PRT_8723D_FIRMWARE_HDR;
++
++#define DRIVER_EARLY_INT_TIME_8723D		0x05
++#define BCN_DMA_ATIME_INT_TIME_8723D		0x02
++
++/* for 8723D
++ * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
++#define PAGE_SIZE_TX_8723D			128
++#define PAGE_SIZE_RX_8723D			8
++
++#define TX_DMA_SIZE_8723D			0x8000	/* 32K(TX) */
++#define RX_DMA_SIZE_8723D			0x4000	/* 16K(RX) */
++
++#ifdef CONFIG_WOWLAN
++	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
++#else
++	#define RESV_FMWF	0
++#endif
++
++#ifdef CONFIG_FW_C2H_DEBUG
++	#define RX_DMA_RESERVED_SIZE_8723D	0x100	/* 256B, reserved for c2h debug message */
++#else
++	#define RX_DMA_RESERVED_SIZE_8723D	0x80	/* 128B, reserved for tx report */
++#endif
++#define RX_DMA_BOUNDARY_8723D\
++	(RX_DMA_SIZE_8723D - RX_DMA_RESERVED_SIZE_8723D - 1)
++
++
++/* Note: We will divide number of page equally for each queue other than public queue! */
++
++/* For General Reserved Page Number(Beacon Queue is reserved page)
++ * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8723D
++ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
++
++#define BCNQ_PAGE_NUM_8723D		(MAX_BEACON_LEN/PAGE_SIZE_TX_8723D + 6) /*0x08*/
++
++/* For WoWLan , more reserved page
++ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6
++ * NS offload: 2 NDP info: 1
++ */
++#ifdef CONFIG_WOWLAN
++	#define WOWLAN_PAGE_NUM_8723D	0x0b
++#else
++	#define WOWLAN_PAGE_NUM_8723D	0x00
++#endif
++
++#ifdef CONFIG_PNO_SUPPORT
++	#undef WOWLAN_PAGE_NUM_8723D
++	#define WOWLAN_PAGE_NUM_8723D	0x15
++#endif
++
++#ifdef CONFIG_AP_WOWLAN
++	#define AP_WOWLAN_PAGE_NUM_8723D	0x02
++#endif
++
++#define TX_TOTAL_PAGE_NUMBER_8723D\
++	(0xFF - BCNQ_PAGE_NUM_8723D - WOWLAN_PAGE_NUM_8723D)
++#define TX_PAGE_BOUNDARY_8723D		(TX_TOTAL_PAGE_NUMBER_8723D + 1)
++
++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723D	TX_TOTAL_PAGE_NUMBER_8723D
++#define WMM_NORMAL_TX_PAGE_BOUNDARY_8723D\
++	(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723D + 1)
++
++/* For Normal Chip Setting
++ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723D */
++#define NORMAL_PAGE_NUM_HPQ_8723D		0x0C
++#define NORMAL_PAGE_NUM_LPQ_8723D		0x02
++#define NORMAL_PAGE_NUM_NPQ_8723D		0x02
++#define NORMAL_PAGE_NUM_EPQ_8723D		0x04
++
++/* Note: For Normal Chip Setting, modify later */
++#define WMM_NORMAL_PAGE_NUM_HPQ_8723D		0x30
++#define WMM_NORMAL_PAGE_NUM_LPQ_8723D		0x20
++#define WMM_NORMAL_PAGE_NUM_NPQ_8723D		0x20
++#define WMM_NORMAL_PAGE_NUM_EPQ_8723D		0x00
++
++
++#include "HalVerDef.h"
++#include "hal_com.h"
++
++#define EFUSE_OOB_PROTECT_BYTES (96 + 1)
++
++#define HAL_EFUSE_MEMORY
++#define HWSET_MAX_SIZE_8723D                512
++#define EFUSE_REAL_CONTENT_LEN_8723D        512
++#define EFUSE_MAP_LEN_8723D                 512
++#define EFUSE_MAX_SECTION_8723D             64
++
++/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/
++#define EFUSE_IC_ID_OFFSET			506
++#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8723D)
++
++#define EFUSE_ACCESS_ON		0x69
++#define EFUSE_ACCESS_OFF	0x00
++
++/* ********************************************************
++ *			EFUSE for BT definition
++ * ******************************************************** */
++#define BANK_NUM			1
++#define EFUSE_BT_REAL_BANK_CONTENT_LEN	128
++#define EFUSE_BT_REAL_CONTENT_LEN	\
++	(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)
++#define EFUSE_BT_MAP_LEN		1024	/* 1k bytes */
++#define EFUSE_BT_MAX_SECTION		(EFUSE_BT_MAP_LEN / 8)
++#define EFUSE_PROTECT_BYTES_BANK	16
++
++typedef enum tag_Package_Definition {
++	PACKAGE_DEFAULT,
++	PACKAGE_QFN68,
++	PACKAGE_TFBGA90,
++	PACKAGE_TFBGA80,
++	PACKAGE_TFBGA79
++} PACKAGE_TYPE_E;
++
++#define INCLUDE_MULTI_FUNC_BT(_Adapter) \
++	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
++#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \
++	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
++
++#ifdef CONFIG_FILE_FWIMG
++	extern char *rtw_fw_file_path;
++	extern char *rtw_fw_wow_file_path;
++	#ifdef CONFIG_MP_INCLUDED
++		extern char *rtw_fw_mp_bt_file_path;
++	#endif /* CONFIG_MP_INCLUDED */
++#endif /* CONFIG_FILE_FWIMG */
++
++/* rtl8723d_hal_init.c */
++s32 rtl8723d_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
++void rtl8723d_FirmwareSelfReset(PADAPTER padapter);
++void rtl8723d_InitializeFirmwareVars(PADAPTER padapter);
++
++void rtl8723d_InitAntenna_Selection(PADAPTER padapter);
++void rtl8723d_DeinitAntenna_Selection(PADAPTER padapter);
++void rtl8723d_CheckAntenna_Selection(PADAPTER padapter);
++void rtl8723d_init_default_value(PADAPTER padapter);
++
++s32 rtl8723d_InitLLTTable(PADAPTER padapter);
++
++s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
++s32 CardDisableWithoutHWSM(PADAPTER padapter);
++
++/* EFuse */
++u8 GetEEPROMSize8723D(PADAPTER padapter);
++void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
++void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
++void Hal_EfuseParseTxPowerInfo_8723D(PADAPTER padapter,
++				     u8 *PROMContent, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseBTCoexistInfo_8723D(PADAPTER padapter,
++				       u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseEEPROMVer_8723D(PADAPTER padapter,
++				   u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseChnlPlan_8723D(PADAPTER padapter,
++				  u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseCustomerID_8723D(PADAPTER padapter,
++				    u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseAntennaDiversity_8723D(PADAPTER padapter,
++		u8 *hwinfo, BOOLEAN AutoLoadFail);
++void Hal_EfuseParseXtal_8723D(PADAPTER pAdapter,
++			      u8 *hwinfo, u8 AutoLoadFail);
++void Hal_EfuseParseThermalMeter_8723D(PADAPTER padapter,
++				      u8 *hwinfo, u8 AutoLoadFail);
++void Hal_EfuseParseVoltage_8723D(PADAPTER pAdapter,
++				 u8 *hwinfo, BOOLEAN	AutoLoadFail);
++void Hal_EfuseParseBoardType_8723D(PADAPTER Adapter,
++				   u8	*PROMContent, BOOLEAN AutoloadFail);
++
++void rtl8723d_set_hal_ops(struct hal_ops *pHalFunc);
++void init_hal_spec_8723d(_adapter *adapter);
++u8 SetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val);
++void GetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val);
++u8 SetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
++u8 GetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
++
++/* register */
++void rtl8723d_InitBeaconParameters(PADAPTER padapter);
++void rtl8723d_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
++void _InitMacAPLLSetting_8723D(PADAPTER Adapter);
++void _8051Reset8723(PADAPTER padapter);
++#ifdef CONFIG_WOWLAN
++	void Hal_DetectWoWMode(PADAPTER pAdapter);
++#endif /* CONFIG_WOWLAN */
++
++void rtl8723d_start_thread(_adapter *padapter);
++void rtl8723d_stop_thread(_adapter *padapter);
++
++#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
++	void rtl8723ds_init_checkbthang_workqueue(_adapter *adapter);
++	void rtl8723ds_free_checkbthang_workqueue(_adapter *adapter);
++	void rtl8723ds_cancle_checkbthang_workqueue(_adapter *adapter);
++	void rtl8723ds_hal_check_bt_hang(_adapter *adapter);
++#endif
++
++#ifdef CONFIG_GPIO_WAKEUP
++	void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
++#endif
++#ifdef CONFIG_MP_INCLUDED
++int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
++#endif
++void CCX_FwC2HTxRpt_8723d(PADAPTER padapter, u8 *pdata, u8 len);
++
++u8 MRateToHwRate8723D(u8 rate);
++u8 HwRateToMRate8723D(u8 rate);
++
++void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++
++#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
++	void check_bt_status_work(void *data);
++#endif
++
++#ifdef CONFIG_USB_HCI
++	void rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	BOOLEAN	InterruptRecognized8723DE(PADAPTER Adapter);
++	void	UpdateInterruptMask8723DE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
++	u16 get_txbd_rw_reg(u16 ff_hwaddr);
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_led.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_led.h
+new file mode 100644
+index 000000000..1905e8bed
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_led.h
+@@ -0,0 +1,44 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8723D_LED_H__
++#define __RTL8723D_LED_H__
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++
++#ifdef CONFIG_RTW_SW_LED
++/* ********************************************************************************
++ * Interface to manipulate LED objects.
++ * ******************************************************************************** */
++#ifdef CONFIG_USB_HCI
++	void rtl8723du_InitSwLeds(PADAPTER padapter);
++	void rtl8723du_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_SDIO_HCI
++	void rtl8723ds_InitSwLeds(PADAPTER padapter);
++	void rtl8723ds_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_GSPI_HCI
++	void rtl8723ds_InitSwLeds(PADAPTER padapter);
++	void rtl8723ds_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_PCI_HCI
++	void rtl8723de_InitSwLeds(PADAPTER padapter);
++	void rtl8723de_DeInitSwLeds(PADAPTER padapter);
++#endif
++
++#endif /*#ifdef CONFIG_RTW_SW_LED*/
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_lps_poff.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_lps_poff.h
+new file mode 100644
+index 000000000..138a0ca66
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_lps_poff.h
+@@ -0,0 +1,56 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++/******************************************** CONST  ************************/
++#define NUM_OF_REGISTER_BANK	13
++#define NUM_OF_TOTAL_DWORD (NUM_OF_REGISTER_BANK * 64)
++#define TOTAL_LEN_FOR_HIOE ((NUM_OF_TOTAL_DWORD + 1) * 8)
++#define LPS_POFF_STATIC_FILE_LEN (TOTAL_LEN_FOR_HIOE + TXDESC_SIZE)
++#define LPS_POFF_DYNAMIC_FILE_LEN	(512 + TXDESC_SIZE)
++/******************************************** CONST  ************************/
++
++/******************************************** MACRO   ************************/
++/* HOIE Entry Definition */
++#define SET_HOIE_ENTRY_LOW_DATA(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE),	0, 16, __Value)
++#define SET_HOIE_ENTRY_HIGH_DATA(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE), 16, 16, __Value)
++#define SET_HOIE_ENTRY_MODE_SELECT(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 0, 1, __Value)
++#define SET_HOIE_ENTRY_ADDRESS(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 1, 14, __Value)
++#define SET_HOIE_ENTRY_BYTE_MASK(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 15, 4, __Value)
++#define SET_HOIE_ENTRY_IO_LOCK(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 19, 1, __Value)
++#define SET_HOIE_ENTRY_RD_EN(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 20, 1, __Value)
++#define SET_HOIE_ENTRY_WR_EN(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 21, 1, __Value)
++#define SET_HOIE_ENTRY_RAW_RW(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 22, 1, __Value)
++#define SET_HOIE_ENTRY_RAW(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 23, 1, __Value)
++#define SET_HOIE_ENTRY_IO_DELAY(__pHOIE, __Value) \
++	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 24, 8, __Value)
++
++/*********************Function Definition*******************************************/
++void rtl8723d_lps_poff_init(PADAPTER padapter);
++void rtl8723d_lps_poff_deinit(PADAPTER padapter);
++bool rtl8723d_lps_poff_get_txbndy_status(PADAPTER padapter);
++void rtl8723d_lps_poff_h2c_ctrl(PADAPTER padapter, u8 enable);
++void rtl8723d_lps_poff_set_ps_mode(PADAPTER padapter, bool bEnterLPS);
++bool rtl8723d_lps_poff_get_status(PADAPTER padapter);
++void rtl8723d_lps_poff_wow(PADAPTER padapter);
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_recv.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_recv.h
+new file mode 100644
+index 000000000..f19ad6904
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_recv.h
+@@ -0,0 +1,112 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8723D_RECV_H__
++#define __RTL8723D_RECV_H__
++
++#define RECV_BLK_SZ 512
++#define RECV_BLK_CNT 16
++#define RECV_BLK_TH RECV_BLK_CNT
++
++#if defined(CONFIG_USB_HCI)
++
++	#ifndef MAX_RECVBUF_SZ
++		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
++			/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
++			/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
++			/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
++			#ifdef CONFIG_PLATFORM_MSTAR
++				#define MAX_RECVBUF_SZ (8192) /* 8K */
++			#else
++				#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
++			#endif
++			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
++		#else
++			#define MAX_RECVBUF_SZ (4000) /* about 4K */
++		#endif
++	#endif /* !MAX_RECVBUF_SZ */
++
++#elif defined(CONFIG_PCI_HCI)
++	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
++	/*	#define MAX_RECVBUF_SZ (9100) */
++	/* #else */
++	#define MAX_RECVBUF_SZ (4000) /* about 4K
++	* #endif */
++
++
++#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++
++	#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8723D + 1)
++
++#endif
++
++/* Rx smooth factor */
++#define	Rx_Smooth_Factor (20)
++
++#ifdef CONFIG_SDIO_HCI
++	#ifndef CONFIG_SDIO_RX_COPY
++		#undef MAX_RECVBUF_SZ
++		#define MAX_RECVBUF_SZ	(RX_DMA_SIZE_8723D - RX_DMA_RESERVED_SIZE_8723D)
++	#endif /* !CONFIG_SDIO_RX_COPY */
++#endif /* CONFIG_SDIO_HCI */
++
++/*-----------------------------------------------------------------*/
++/*	RTL8723D RX BUFFER DESC                                      */
++/*-----------------------------------------------------------------*/
++/*DWORD 0*/
++#define SET_RX_BUFFER_DESC_DATA_LENGTH_8723D(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
++#define SET_RX_BUFFER_DESC_LS_8723D(__pRxStatusDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
++#define SET_RX_BUFFER_DESC_FS_8723D(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
++#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8723D(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
++
++#define GET_RX_BUFFER_DESC_OWN_8723D(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
++#define GET_RX_BUFFER_DESC_LS_8723D(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
++#define GET_RX_BUFFER_DESC_FS_8723D(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
++#ifdef USING_RX_TAG
++	#define GET_RX_BUFFER_DESC_RX_TAG_8723D(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13)
++#else
++	#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8723D(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
++#endif
++
++/*DWORD 1*/
++#define SET_RX_BUFFER_PHYSICAL_LOW_8723D(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
++
++/*DWORD 2*/
++#ifdef CONFIG_64BIT_DMA
++	#define SET_RX_BUFFER_PHYSICAL_HIGH_8723D(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
++#else
++	#define SET_RX_BUFFER_PHYSICAL_HIGH_8723D(__pRxStatusDesc, __Value)
++#endif
++
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	s32 rtl8723ds_init_recv_priv(PADAPTER padapter);
++	void rtl8723ds_free_recv_priv(PADAPTER padapter);
++	s32 rtl8723ds_recv_hdl(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_USB_HCI
++	int rtl8723du_init_recv_priv(_adapter *padapter);
++	void rtl8723du_free_recv_priv(_adapter *padapter);
++	void rtl8723du_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	s32 rtl8723de_init_recv_priv(PADAPTER padapter);
++	void rtl8723de_free_recv_priv(PADAPTER padapter);
++#endif
++
++void rtl8723d_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
++
++#endif /* __RTL8723D_RECV_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_rf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_rf.h
+new file mode 100644
+index 000000000..4a0a7cfb8
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_rf.h
+@@ -0,0 +1,21 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8723D_RF_H__
++#define __RTL8723D_RF_H__
++
++int PHY_RF6052_Config8723D(PADAPTER pdapter);
++
++void PHY_RF6052SetBandwidth8723D(PADAPTER Adapter, enum channel_width Bandwidth);
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_spec.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_spec.h
+new file mode 100644
+index 000000000..5106b23b7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_spec.h
+@@ -0,0 +1,447 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8723D_SPEC_H__
++#define __RTL8723D_SPEC_H__
++
++#include <drv_conf.h>
++
++
++#define HAL_NAV_UPPER_UNIT_8723D		128		/* micro-second */
++
++/* -----------------------------------------------------
++ *
++ *	0x0000h ~ 0x00FFh	System Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_SYS_ISO_CTRL_8723D			0x0000	/* 2 Byte */
++#define REG_SYS_FUNC_EN_8723D			0x0002	/* 2 Byte */
++#define REG_APS_FSMCO_8723D			0x0004	/* 4 Byte */
++#define REG_SYS_CLKR_8723D				0x0008	/* 2 Byte */
++#define REG_9346CR_8723D				0x000A	/* 2 Byte */
++#define REG_EE_VPD_8723D				0x000C	/* 2 Byte */
++#define REG_AFE_MISC_8723D				0x0010	/* 1 Byte */
++#define REG_SPS0_CTRL_8723D				0x0011	/* 7 Byte */
++#define REG_SPS_OCP_CFG_8723D			0x0018	/* 4 Byte */
++#define REG_RSV_CTRL_8723D				0x001C	/* 3 Byte */
++#define REG_RF_CTRL_8723D				0x001F	/* 1 Byte */
++#define REG_LPLDO_CTRL_8723D			0x0023	/* 1 Byte */
++#define REG_AFE_XTAL_CTRL_8723D		0x0024	/* 4 Byte */
++#define REG_AFE_PLL_CTRL_8723D			0x0028	/* 4 Byte */
++#define REG_MAC_PLL_CTRL_EXT_8723D		0x002c	/* 4 Byte */
++#define REG_EFUSE_CTRL_8723D			0x0030
++#define REG_EFUSE_TEST_8723D			0x0034
++#define REG_PWR_DATA_8723D				0x0038
++#define REG_CAL_TIMER_8723D				0x003C
++#define REG_ACLK_MON_8723D				0x003E
++#define REG_GPIO_MUXCFG_8723D			0x0040
++#define REG_GPIO_IO_SEL_8723D			0x0042
++#define REG_MAC_PINMUX_CFG_8723D		0x0043
++#define REG_GPIO_PIN_CTRL_8723D			0x0044
++#define REG_GPIO_INTM_8723D				0x0048
++#define REG_LEDCFG0_8723D				0x004C
++#define REG_LEDCFG1_8723D				0x004D
++#define REG_LEDCFG2_8723D				0x004E
++#define REG_LEDCFG3_8723D				0x004F
++#define REG_FSIMR_8723D					0x0050
++#define REG_FSISR_8723D					0x0054
++#define REG_HSIMR_8723D					0x0058
++#define REG_HSISR_8723D					0x005c
++#define REG_GPIO_EXT_CTRL				0x0060
++#define REG_PAD_CTRL1_8723D		0x0064
++#define REG_MULTI_FUNC_CTRL_8723D		0x0068
++#define REG_GPIO_STATUS_8723D			0x006C
++#define REG_SDIO_CTRL_8723D				0x0070
++#define REG_OPT_CTRL_8723D				0x0074
++#define REG_AFE_CTRL_4_8723D		0x0078
++#define REG_MCUFWDL_8723D				0x0080
++#define REG_8051FW_CTRL_8723D			0x0080
++#define REG_HMEBOX_DBG_0_8723D	0x0088
++#define REG_HMEBOX_DBG_1_8723D	0x008A
++#define REG_HMEBOX_DBG_2_8723D	0x008C
++#define REG_HMEBOX_DBG_3_8723D	0x008E
++#define REG_WLLPS_CTRL		0x0090
++#define REG_HIMR0_8723D					0x00B0
++#define REG_HISR0_8723D					0x00B4
++#define REG_HIMR1_8723D					0x00B8
++#define REG_HISR1_8723D					0x00BC
++#define REG_PMC_DBG_CTRL2_8723D			0x00CC
++#define	REG_EFUSE_BURN_GNT_8723D		0x00CF
++#define REG_HPON_FSM_8723D				0x00EC
++#define REG_SYS_CFG1_8723D				0x00F0
++#define REG_SYS_CFG_8723D				0x00FC
++#define REG_ROM_VERSION					0x00FD
++
++/* -----------------------------------------------------
++ *
++ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_C2HEVT_CMD_ID_8723D	0x01A0
++#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
++#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
++#define REG_C2HEVT_CMD_LEN_8723D        0x01AE
++#define REG_C2HEVT_CLEAR_8723D			0x01AF
++#define REG_MCUTST_1_8723D				0x01C0
++#define REG_WOWLAN_WAKE_REASON 0x01C7
++#define REG_FMETHR_8723D				0x01C8
++#define REG_HMETFR_8723D				0x01CC
++#define REG_HMEBOX_0_8723D				0x01D0
++#define REG_HMEBOX_1_8723D				0x01D4
++#define REG_HMEBOX_2_8723D				0x01D8
++#define REG_HMEBOX_3_8723D				0x01DC
++#define REG_LLT_INIT_8723D				0x01E0
++#define REG_HMEBOX_EXT0_8723D			0x01F0
++#define REG_HMEBOX_EXT1_8723D			0x01F4
++#define REG_HMEBOX_EXT2_8723D			0x01F8
++#define REG_HMEBOX_EXT3_8723D			0x01FC
++
++/* -----------------------------------------------------
++ *
++ *	0x0200h ~ 0x027Fh	TXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_RQPN_8723D					0x0200
++#define REG_FIFOPAGE_8723D				0x0204
++#define REG_DWBCN0_CTRL_8723D			REG_TDECTRL
++#define REG_TXDMA_OFFSET_CHK_8723D	0x020C
++#define REG_TXDMA_STATUS_8723D		0x0210
++#define REG_RQPN_NPQ_8723D			0x0214
++#define REG_DWBCN1_CTRL_8723D			0x0228
++
++
++/* -----------------------------------------------------
++ *
++ *	0x0280h ~ 0x02FFh	RXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_RXDMA_AGG_PG_TH_8723D		0x0280
++#define REG_FW_UPD_RDPTR_8723D		0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
++#define REG_RXDMA_CONTROL_8723D		0x0286 /* Control the RX DMA. */
++#define REG_RXDMA_STATUS_8723D			0x0288
++#define REG_RXDMA_MODE_CTRL_8723D		0x0290
++#define REG_EARLY_MODE_CONTROL_8723D	0x02BC
++#define REG_RSVD5_8723D					0x02F0
++#define REG_RSVD6_8723D					0x02F4
++
++/* -----------------------------------------------------
++ *
++ *	0x0300h ~ 0x03FFh	PCIe
++ *
++ * ----------------------------------------------------- */
++#define	REG_PCIE_CTRL_REG_8723D			0x0300
++#define	REG_INT_MIG_8723D				0x0304	/* Interrupt Migration */
++#define	REG_BCNQ_TXBD_DESA_8723D		0x0308	/* TX Beacon Descriptor Address */
++#define	REG_MGQ_TXBD_DESA_8723D			0x0310	/* TX Manage Queue Descriptor Address */
++#define	REG_VOQ_TXBD_DESA_8723D			0x0318	/* TX VO Queue Descriptor Address */
++#define	REG_VIQ_TXBD_DESA_8723D			0x0320	/* TX VI Queue Descriptor Address */
++#define	REG_BEQ_TXBD_DESA_8723D			0x0328	/* TX BE Queue Descriptor Address */
++#define	REG_BKQ_TXBD_DESA_8723D			0x0330	/* TX BK Queue Descriptor Address */
++#define	REG_RXQ_RXBD_DESA_8723D			0x0338	/* RX Queue	Descriptor Address */
++#define REG_HI0Q_TXBD_DESA_8723D		0x0340
++#define REG_HI1Q_TXBD_DESA_8723D		0x0348
++#define REG_HI2Q_TXBD_DESA_8723D		0x0350
++#define REG_HI3Q_TXBD_DESA_8723D		0x0358
++#define REG_HI4Q_TXBD_DESA_8723D		0x0360
++#define REG_HI5Q_TXBD_DESA_8723D		0x0368
++#define REG_HI6Q_TXBD_DESA_8723D		0x0370
++#define REG_HI7Q_TXBD_DESA_8723D		0x0378
++#define	REG_MGQ_TXBD_NUM_8723D			0x0380
++#define	REG_RX_RXBD_NUM_8723D			0x0382
++#define	REG_VOQ_TXBD_NUM_8723D			0x0384
++#define	REG_VIQ_TXBD_NUM_8723D			0x0386
++#define	REG_BEQ_TXBD_NUM_8723D			0x0388
++#define	REG_BKQ_TXBD_NUM_8723D			0x038A
++#define	REG_HI0Q_TXBD_NUM_8723D			0x038C
++#define	REG_HI1Q_TXBD_NUM_8723D			0x038E
++#define	REG_HI2Q_TXBD_NUM_8723D			0x0390
++#define	REG_HI3Q_TXBD_NUM_8723D			0x0392
++#define	REG_HI4Q_TXBD_NUM_8723D			0x0394
++#define	REG_HI5Q_TXBD_NUM_8723D			0x0396
++#define	REG_HI6Q_TXBD_NUM_8723D			0x0398
++#define	REG_HI7Q_TXBD_NUM_8723D			0x039A
++#define	REG_TSFTIMER_HCI_8723D			0x039C
++#define	REG_BD_RW_PTR_CLR_8723D			0x039C
++
++/* Read Write Point */
++#define	REG_VOQ_TXBD_IDX_8723D			0x03A0
++#define	REG_VIQ_TXBD_IDX_8723D			0x03A4
++#define	REG_BEQ_TXBD_IDX_8723D			0x03A8
++#define	REG_BKQ_TXBD_IDX_8723D			0x03AC
++#define	REG_MGQ_TXBD_IDX_8723D			0x03B0
++#define	REG_RXQ_TXBD_IDX_8723D			0x03B4
++#define	REG_HI0Q_TXBD_IDX_8723D			0x03B8
++#define	REG_HI1Q_TXBD_IDX_8723D			0x03BC
++#define	REG_HI2Q_TXBD_IDX_8723D			0x03C0
++#define	REG_HI3Q_TXBD_IDX_8723D			0x03C4
++#define	REG_HI4Q_TXBD_IDX_8723D			0x03C8
++#define	REG_HI5Q_TXBD_IDX_8723D			0x03CC
++#define	REG_HI6Q_TXBD_IDX_8723D			0x03D0
++#define	REG_HI7Q_TXBD_IDX_8723D			0x03D4
++
++#define	REG_PCIE_HCPWM_8723DE			0x03D8 /* ?????? */
++#define	REG_PCIE_HRPWM_8723DE			0x03DC	/* PCIe RPWM  ?????? */
++#define	REG_DBI_WDATA_V1_8723D			0x03E8
++#define	REG_DBI_RDATA_V1_8723D			0x03EC
++#define	REG_DBI_FLAG_V1_8723D			0x03F0
++#define REG_MDIO_V1_8723D				0x03F4
++#define REG_PCIE_MIX_CFG_8723D			0x03F8
++#define REG_HCI_MIX_CFG_8723D			0x03FC
++
++/* -----------------------------------------------------
++ *
++ *	0x0400h ~ 0x047Fh	Protocol Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_VOQ_INFORMATION_8723D		0x0400
++#define REG_VIQ_INFORMATION_8723D		0x0404
++#define REG_BEQ_INFORMATION_8723D		0x0408
++#define REG_BKQ_INFORMATION_8723D		0x040C
++#define REG_MGQ_INFORMATION_8723D		0x0410
++#define REG_HGQ_INFORMATION_8723D		0x0414
++#define REG_BCNQ_INFORMATION_8723D	0x0418
++#define REG_TXPKT_EMPTY_8723D			0x041A
++
++#define REG_FWHW_TXQ_CTRL_8723D		0x0420
++#define REG_HWSEQ_CTRL_8723D			0x0423
++#define REG_TXPKTBUF_BCNQ_BDNY_8723D	0x0424
++#define REG_TXPKTBUF_MGQ_BDNY_8723D	0x0425
++#define REG_LIFECTRL_CTRL_8723D			0x0426
++#define REG_MULTI_BCNQ_OFFSET_8723D	0x0427
++#define REG_SPEC_SIFS_8723D				0x0428
++#define REG_RL_8723D						0x042A
++#define REG_TXBF_CTRL_8723D				0x042C
++#define REG_DARFRC_8723D				0x0430
++#define REG_RARFRC_8723D				0x0438
++#define REG_RRSR_8723D					0x0440
++#define REG_ARFR0_8723D					0x0444
++#define REG_ARFR1_8723D					0x044C
++#define REG_CCK_CHECK_8723D				0x0454
++#define REG_AMPDU_MAX_TIME_8723D		0x0456
++#define REG_TXPKTBUF_BCNQ_BDNY1_8723D	0x0457
++
++#define REG_AMPDU_MAX_LENGTH_8723D	0x0458
++#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723D	0x045D
++#define REG_NDPA_OPT_CTRL_8723D		0x045F
++#define REG_FAST_EDCA_CTRL_8723D		0x0460
++#define REG_RD_RESP_PKT_TH_8723D		0x0463
++#define REG_DATA_SC_8723D				0x0483
++#ifdef CONFIG_WOWLAN
++	#define REG_TXPKTBUF_IV_LOW             0x0484
++	#define REG_TXPKTBUF_IV_HIGH            0x0488
++#endif
++#define REG_TXRPT_START_OFFSET		0x04AC
++#define REG_POWER_STAGE1_8723D		0x04B4
++#define REG_POWER_STAGE2_8723D		0x04B8
++#define REG_AMPDU_BURST_MODE_8723D	0x04BC
++#define REG_PKT_VO_VI_LIFE_TIME_8723D	0x04C0
++#define REG_PKT_BE_BK_LIFE_TIME_8723D	0x04C2
++#define REG_STBC_SETTING_8723D			0x04C4
++#define REG_HT_SINGLE_AMPDU_8723D		0x04C7
++#define REG_PROT_MODE_CTRL_8723D		0x04C8
++#define REG_MAX_AGGR_NUM_8723D		0x04CA
++#define REG_RTS_MAX_AGGR_NUM_8723D	0x04CB
++#define REG_BAR_MODE_CTRL_8723D		0x04CC
++#define REG_RA_TRY_RATE_AGG_LMT_8723D	0x04CF
++#define REG_MACID_PKT_DROP0_8723D		0x04D0
++#define REG_MACID_PKT_SLEEP_8723D		0x04D4
++
++/* -----------------------------------------------------
++ *
++ *	0x0500h ~ 0x05FFh	EDCA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_EDCA_VO_PARAM_8723D		0x0500
++#define REG_EDCA_VI_PARAM_8723D		0x0504
++#define REG_EDCA_BE_PARAM_8723D		0x0508
++#define REG_EDCA_BK_PARAM_8723D		0x050C
++#define REG_BCNTCFG_8723D				0x0510
++#define REG_PIFS_8723D					0x0512
++#define REG_RDG_PIFS_8723D				0x0513
++#define REG_SIFS_CTX_8723D				0x0514
++#define REG_SIFS_TRX_8723D				0x0516
++#define REG_AGGR_BREAK_TIME_8723D		0x051A
++#define REG_SLOT_8723D					0x051B
++#define REG_TX_PTCL_CTRL_8723D			0x0520
++#define REG_TXPAUSE_8723D				0x0522
++#define REG_DIS_TXREQ_CLR_8723D		0x0523
++#define REG_RD_CTRL_8723D				0x0524
++/*
++ * Format for offset 540h-542h:
++ *	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
++ *	[7:4]:   Reserved.
++ *	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
++ *	[23:20]: Reserved
++ * Description:
++ *	              |
++ * |<--Setup--|--Hold------------>|
++ *	--------------|----------------------
++ * |
++ * TBTT
++ * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
++ * Described by Designer Tim and Bruce, 2011-01-14.
++ *   */
++#define REG_TBTT_PROHIBIT_8723D			0x0540
++#define REG_RD_NAV_NXT_8723D			0x0544
++#define REG_NAV_PROT_LEN_8723D			0x0546
++#define REG_BCN_CTRL_8723D				0x0550
++#define REG_BCN_CTRL_1_8723D			0x0551
++#define REG_MBID_NUM_8723D				0x0552
++#define REG_DUAL_TSF_RST_8723D			0x0553
++#define REG_BCN_INTERVAL_8723D			0x0554
++#define REG_DRVERLYINT_8723D			0x0558
++#define REG_BCNDMATIM_8723D			0x0559
++#define REG_ATIMWND_8723D				0x055A
++#define REG_USTIME_TSF_8723D			0x055C
++#define REG_BCN_MAX_ERR_8723D			0x055D
++#define REG_RXTSF_OFFSET_CCK_8723D		0x055E
++#define REG_RXTSF_OFFSET_OFDM_8723D	0x055F
++#define REG_TSFTR_8723D					0x0560
++#define REG_CTWND_8723D					0x0572
++#define REG_SECONDARY_CCA_CTRL_8723D	0x0577
++#define REG_PSTIMER_8723D				0x0580
++#define REG_TIMER0_8723D				0x0584
++#define REG_TIMER1_8723D				0x0588
++#define REG_ACMHWCTRL_8723D			0x05C0
++#define REG_SCH_TXCMD_8723D			0x05F8
++
++/* -----------------------------------------------------
++ *
++ *	0x0600h ~ 0x07FFh	WMAC Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_MAC_CR_8723D				0x0600
++#define REG_TCR_8723D					0x0604
++#define REG_RCR_8723D					0x0608
++#define REG_RX_PKT_LIMIT_8723D			0x060C
++#define REG_RX_DLK_TIME_8723D			0x060D
++#define REG_RX_DRVINFO_SZ_8723D		0x060F
++
++#define REG_MACID_8723D					0x0610
++#define REG_BSSID_8723D					0x0618
++#define REG_MAR_8723D					0x0620
++#define REG_MBIDCAMCFG_8723D			0x0628
++#define REG_WOWLAN_GTK_DBG1	0x630
++#define REG_WOWLAN_GTK_DBG2	0x634
++
++#define REG_USTIME_EDCA_8723D			0x0638
++#define REG_MAC_SPEC_SIFS_8723D		0x063A
++#define REG_RESP_SIFP_CCK_8723D			0x063C
++#define REG_RESP_SIFS_OFDM_8723D		0x063E
++#define REG_ACKTO_8723D					0x0640
++#define REG_CTS2TO_8723D				0x0641
++#define REG_EIFS_8723D					0x0642
++
++#define REG_NAV_UPPER_8723D			0x0652	/* unit of 128 */
++#define REG_TRXPTCL_CTL_8723D			0x0668
++
++/* Security */
++#define REG_CAMCMD_8723D				0x0670
++#define REG_CAMWRITE_8723D				0x0674
++#define REG_CAMREAD_8723D				0x0678
++#define REG_CAMDBG_8723D				0x067C
++#define REG_SECCFG_8723D				0x0680
++
++/* Power */
++#define REG_WOW_CTRL_8723D				0x0690
++#define REG_PS_RX_INFO_8723D			0x0692
++#define REG_UAPSD_TID_8723D				0x0693
++#define REG_WKFMCAM_CMD_8723D			0x0698
++#define REG_WKFMCAM_NUM_8723D			0x0698
++#define REG_WKFMCAM_RWD_8723D			0x069C
++#define REG_RXFLTMAP0_8723D				0x06A0
++#define REG_RXFLTMAP1_8723D				0x06A2
++#define REG_RXFLTMAP2_8723D				0x06A4
++#define REG_BCN_PSR_RPT_8723D			0x06A8
++#define REG_BT_COEX_TABLE_8723D		0x06C0
++#define REG_BFMER0_INFO_8723D			0x06E4
++#define REG_BFMER1_INFO_8723D			0x06EC
++#define REG_CSI_RPT_PARAM_BW20_8723D	0x06F4
++#define REG_CSI_RPT_PARAM_BW40_8723D	0x06F8
++#define REG_CSI_RPT_PARAM_BW80_8723D	0x06FC
++
++/* Hardware Port 2 */
++#define REG_MACID1_8723D				0x0700
++#define REG_BSSID1_8723D				0x0708
++#define REG_BFMEE_SEL_8723D				0x0714
++#define REG_SND_PTCL_CTRL_8723D		0x0718
++
++/* LTR */
++#define REG_LTR_CTRL_BASIC_8723D		0x07A4
++#define REG_LTR_IDLE_LATENCY_V1_8723D		0x0798
++#define REG_LTR_ACTIVE_LATENCY_V1_8723D		0x079C
++
++/* LTE_COEX */
++#define REG_LTECOEX_CTRL			0x07C0
++#define REG_LTECOEX_WRITE_DATA		0x07C4
++#define REG_LTECOEX_READ_DATA		0x07C8
++#define REG_LTECOEX_PATH_CONTROL	0x70
++
++/* ************************************************************
++ * SDIO Bus Specification
++ * ************************************************************ */
++
++/* -----------------------------------------------------
++ * SDIO CMD Address Mapping
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ * I/O bus domain (Host)
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ * SDIO register
++ * ----------------------------------------------------- */
++#define SDIO_REG_HCPWM1_8723D	0x025 /* HCI Current Power Mode 1 */
++
++
++/* ****************************************************************************
++ *	8723 Regsiter Bit and Content definition
++ * **************************************************************************** */
++
++#define BIT_USB_RXDMA_AGG_EN	BIT(31)
++#define RXDMA_AGG_MODE_EN		BIT(1)
++
++#ifdef CONFIG_WOWLAN
++	#define RXPKT_RELEASE_POLL		BIT(16)
++	#define RXDMA_IDLE				BIT(17)
++	#define RW_RELEASE_EN			BIT(18)
++#endif
++
++/* 2 HSISR
++ * interrupt mask which needs to clear */
++#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
++		HSISR_SPS_OCP_INT |\
++		HSISR_RON_INT |\
++		HSISR_PDNINT |\
++		HSISR_GPIO9_INT)
++
++#ifdef CONFIG_RF_POWER_TRIM
++	#ifdef CONFIG_RTL8723D
++		#define EEPROM_RF_GAIN_OFFSET			0xC1
++	#endif
++
++	#define EEPROM_RF_GAIN_VAL				0x1F6
++#endif /*CONFIG_RF_POWER_TRIM*/
++
++#ifdef CONFIG_PCI_HCI
++	/* #define IMR_RX_MASK		(IMR_ROK_8723D|IMR_RDU_8723D|IMR_RXFOVW_8723D) */
++	#define IMR_TX_MASK			(IMR_VODOK_8723D | IMR_VIDOK_8723D | IMR_BEDOK_8723D | IMR_BKDOK_8723D | IMR_MGNTDOK_8723D | IMR_HIGHDOK_8723D)
++
++	#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8723D | IMR_TXBCN0OK_8723D | IMR_TXBCN0ERR_8723D | IMR_BCNDERR0_8723D)
++
++	#define RT_AC_INT_MASKS	(IMR_VIDOK_8723D | IMR_VODOK_8723D | IMR_BEDOK_8723D | IMR_BKDOK_8723D)
++#endif
++
++#endif /* __RTL8723D_SPEC_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_sreset.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_sreset.h
+new file mode 100644
+index 000000000..db75dba73
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_sreset.h
+@@ -0,0 +1,24 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8723D_SRESET_H_
++#define _RTL8723D_SRESET_H_
++
++#include <rtw_sreset.h>
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++	extern void rtl8723d_sreset_xmit_status_check(_adapter *padapter);
++	extern void rtl8723d_sreset_linked_status_check(_adapter *padapter);
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_xmit.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_xmit.h
+new file mode 100644
+index 000000000..fc3dd396f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8723d_xmit.h
+@@ -0,0 +1,521 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8723D_XMIT_H__
++#define __RTL8723D_XMIT_H__
++
++
++#define MAX_TID (15)
++
++
++#ifndef __INC_HAL8723DDESC_H
++#define __INC_HAL8723DDESC_H
++
++#define RX_STATUS_DESC_SIZE_8723D		24
++#define RX_DRV_INFO_SIZE_UNIT_8723D 8
++
++
++/* DWORD 0 */
++#define SET_RX_STATUS_DESC_PKT_LEN_8723D(__pRxStatusDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
++#define SET_RX_STATUS_DESC_EOR_8723D(__pRxStatusDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
++#define SET_RX_STATUS_DESC_OWN_8723D(__pRxStatusDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
++
++#define GET_RX_STATUS_DESC_PKT_LEN_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
++#define GET_RX_STATUS_DESC_CRC32_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
++#define GET_RX_STATUS_DESC_ICV_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
++#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
++#define GET_RX_STATUS_DESC_SECURITY_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
++#define GET_RX_STATUS_DESC_QOS_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
++#define GET_RX_STATUS_DESC_SHIFT_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
++#define GET_RX_STATUS_DESC_PHY_STATUS_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
++#define GET_RX_STATUS_DESC_SWDEC_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
++#define GET_RX_STATUS_DESC_EOR_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
++#define GET_RX_STATUS_DESC_OWN_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
++
++/* DWORD 1 */
++#define GET_RX_STATUS_DESC_MACID_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
++#define GET_RX_STATUS_DESC_TID_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
++#define GET_RX_STATUS_DESC_AMSDU_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
++#define GET_RX_STATUS_DESC_RXID_MATCH_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
++#define GET_RX_STATUS_DESC_PAGGR_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
++#define GET_RX_STATUS_DESC_A1_FIT_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
++#define GET_RX_STATUS_DESC_CHKERR_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
++#define GET_RX_STATUS_DESC_IPVER_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
++#define GET_RX_STATUS_DESC_IS_TCPUDP__8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
++#define GET_RX_STATUS_DESC_CHK_VLD_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
++#define GET_RX_STATUS_DESC_PAM_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
++#define GET_RX_STATUS_DESC_PWR_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
++#define GET_RX_STATUS_DESC_MORE_DATA_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
++#define GET_RX_STATUS_DESC_MORE_FRAG_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
++#define GET_RX_STATUS_DESC_TYPE_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
++#define GET_RX_STATUS_DESC_MC_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
++#define GET_RX_STATUS_DESC_BC_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
++
++/* DWORD 2 */
++#define GET_RX_STATUS_DESC_SEQ_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
++#define GET_RX_STATUS_DESC_FRAG_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
++#define GET_RX_STATUS_DESC_RX_IS_QOS_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
++#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
++#define GET_RX_STATUS_DESC_RPT_SEL_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
++#define GET_RX_STATUS_DESC_FCS_OK_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
++
++/* DWORD 3 */
++#define GET_RX_STATUS_DESC_RX_RATE_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
++#define GET_RX_STATUS_DESC_HTC_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
++#define GET_RX_STATUS_DESC_EOSP_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
++#define GET_RX_STATUS_DESC_BSSID_FIT_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
++#ifdef CONFIG_USB_RX_AGGREGATION
++#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
++#endif
++#define GET_RX_STATUS_DESC_PATTERN_MATCH_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
++#define GET_RX_STATUS_DESC_UNICAST_MATCH_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
++#define GET_RX_STATUS_DESC_MAGIC_MATCH_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
++
++/* DWORD 6 */
++#define GET_RX_STATUS_DESC_MATCH_ID_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7)
++
++/* DWORD 5 */
++#define GET_RX_STATUS_DESC_TSFL_8723D(__pRxStatusDesc) \
++	LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
++
++#define GET_RX_STATUS_DESC_BUFF_ADDR_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
++#define GET_RX_STATUS_DESC_BUFF_ADDR64_8723D(__pRxDesc) \
++	LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
++
++#define SET_RX_STATUS_DESC_BUFF_ADDR_8723D(__pRxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
++
++
++/* Dword 0, rsvd: bit26, bit28 */
++#define GET_TX_DESC_OWN_8723D(__pTxDesc)\
++	LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
++
++#define SET_TX_DESC_PKT_SIZE_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
++#define SET_TX_DESC_OFFSET_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
++#define SET_TX_DESC_BMC_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
++#define SET_TX_DESC_HTC_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
++#define SET_TX_DESC_AMSDU_PAD_EN_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
++#define SET_TX_DESC_NO_ACM_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
++#define SET_TX_DESC_GF_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
++
++/* Dword 1 */
++#define SET_TX_DESC_MACID_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
++#define SET_TX_DESC_QUEUE_SEL_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
++#define SET_TX_DESC_RDG_NAV_EXT_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
++#define SET_TX_DESC_LSIG_TXOP_EN_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
++#define SET_TX_DESC_PIFS_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
++#define SET_TX_DESC_RATE_ID_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
++#define SET_TX_DESC_EN_DESC_ID_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
++#define SET_TX_DESC_SEC_TYPE_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
++#define SET_TX_DESC_PKT_OFFSET_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
++#define SET_TX_DESC_MORE_DATA_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
++
++/* Dword 2  remove P_AID, G_ID field*/
++#define SET_TX_DESC_CCA_RTS_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
++#define SET_TX_DESC_AGG_ENABLE_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
++#define SET_TX_DESC_RDG_ENABLE_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
++#define SET_TX_DESC_NULL0_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
++#define SET_TX_DESC_NULL1_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
++#define SET_TX_DESC_BK_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
++#define SET_TX_DESC_MORE_FRAG_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
++#define SET_TX_DESC_RAW_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
++#define SET_TX_DESC_CCX_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
++#define SET_TX_DESC_AMPDU_DENSITY_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
++#define SET_TX_DESC_BT_INT_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
++#define SET_TX_DESC_FTM_EN_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 30, 1, __Value)
++
++/* Dword 3 */
++#define SET_TX_DESC_HWSEQ_SEL_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
++#define SET_TX_DESC_USE_RATE_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
++#define SET_TX_DESC_DISABLE_RTS_FB_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
++#define SET_TX_DESC_DISABLE_FB_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
++#define SET_TX_DESC_CTS2SELF_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
++#define SET_TX_DESC_RTS_ENABLE_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
++#define SET_TX_DESC_HW_RTS_ENABLE_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
++#define SET_TX_DESC_PORT_ID_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 2, __Value)
++#define SET_TX_DESC_NAV_USE_HDR_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
++#define SET_TX_DESC_USE_MAX_LEN_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
++#define SET_TX_DESC_MAX_AGG_NUM_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
++#define SET_TX_DESC_AMPDU_MAX_TIME_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
++
++/* Dword 4 */
++#define SET_TX_DESC_TX_RATE_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
++#define SET_TX_DESC_TX_TRY_RATE_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
++#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
++#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
++#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
++#define SET_TX_DESC_DATA_RETRY_LIMIT_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
++#define SET_TX_DESC_RTS_RATE_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
++#define SET_TX_DESC_PCTS_EN_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
++#define SET_TX_DESC_PCTS_MASK_IDX_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
++
++/* Dword 5 */
++#define SET_TX_DESC_DATA_SC_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
++#define SET_TX_DESC_DATA_SHORT_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
++#define SET_TX_DESC_DATA_BW_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
++#define SET_TX_DESC_DATA_STBC_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
++#define SET_TX_DESC_RTS_STBC_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
++#define SET_TX_DESC_RTS_SHORT_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
++#define SET_TX_DESC_RTS_SC_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
++#define SET_TX_DESC_PATH_A_EN_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value)
++#define SET_TX_DESC_TXPWR_OF_SET_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
++
++/* Dword 6 */
++#define SET_TX_DESC_SW_DEFINE_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
++#define SET_TX_DESC_MBSSID_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
++#define SET_TX_DESC_RF_SEL_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
++
++/* Dword 7 */
++#ifdef CONFIG_PCI_HCI
++#define SET_TX_DESC_TX_BUFFER_SIZE_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++#endif
++
++#ifdef CONFIG_USB_HCI
++#define SET_TX_DESC_TX_DESC_CHECKSUM_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++#endif
++
++#ifdef CONFIG_SDIO_HCI
++#define SET_TX_DESC_TX_TIMESTAMP_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)
++#endif
++
++#define SET_TX_DESC_USB_TXAGG_NUM_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
++
++/* Dword 8 */
++#define SET_TX_DESC_RTS_RC_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
++#define SET_TX_DESC_BAR_RC_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
++#define SET_TX_DESC_DATA_RC_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
++#define SET_TX_DESC_HWSEQ_EN_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
++#define SET_TX_DESC_NEXTHEADPAGE_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
++#define SET_TX_DESC_TAILPAGE_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
++
++/* Dword 9 */
++#define SET_TX_DESC_PADDING_LEN_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
++#define SET_TX_DESC_SEQ_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
++#define SET_TX_DESC_FINAL_DATA_RATE_8723D(__pTxDesc, __Value) \
++	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
++
++
++#define SET_EARLYMODE_PKTNUM_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
++#define SET_EARLYMODE_LEN0_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
++#define SET_EARLYMODE_LEN1_1_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
++#define SET_EARLYMODE_LEN1_2_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
++#define SET_EARLYMODE_LEN2_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
++#define SET_EARLYMODE_LEN3_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
++
++
++/*-----------------------------------------------------------------*/
++/*	RTL8723D TX BUFFER DESC                                      */
++/*-----------------------------------------------------------------*/
++#ifdef CONFIG_64BIT_DMA
++	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)
++	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)
++	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)
++	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)
++#else
++	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
++	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
++	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
++	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu)	/* 64 BIT mode only */
++#endif
++/* ********************************************************* */
++
++/* 64 bits  -- 32 bits */
++/* =======     ======= */
++/* Dword 0     0 */
++#define SET_TX_BUFF_DESC_LEN_0_8723D(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
++#define SET_TX_BUFF_DESC_PSB_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
++#define SET_TX_BUFF_DESC_OWN_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
++
++/* Dword 1     1 */
++#define SET_TX_BUFF_DESC_ADDR_LOW_0_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
++#define GET_TX_BUFF_DESC_ADDR_LOW_0_8723D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
++/* Dword 2     NA */
++#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value)
++#ifdef CONFIG_64BIT_DMA
++	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)
++#else
++	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc) 0
++#endif
++/* Dword 3     NA */
++/* RESERVED 0 */
++/* Dword 4     2 */
++#define SET_TX_BUFF_DESC_LEN_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value)
++#define SET_TX_BUFF_DESC_AMSDU_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value)
++/* Dword 5     3 */
++#define SET_TX_BUFF_DESC_ADDR_LOW_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value)
++/* Dword 6     NA */
++#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value)
++/* Dword 7     NA */
++/*RESERVED 0 */
++/* Dword 8     4 */
++#define SET_TX_BUFF_DESC_LEN_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value)
++#define SET_TX_BUFF_DESC_AMSDU_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value)
++/* Dword 9     5 */
++#define SET_TX_BUFF_DESC_ADDR_LOW_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value)
++/* Dword 10    NA */
++#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value)
++/* Dword 11    NA */
++/*RESERVED 0 */
++/* Dword 12    6 */
++#define SET_TX_BUFF_DESC_LEN_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value)
++#define SET_TX_BUFF_DESC_AMSDU_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value)
++/* Dword 13    7 */
++#define SET_TX_BUFF_DESC_ADDR_LOW_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value)
++/* Dword 14    NA */
++#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value)
++/* Dword 15    NA */
++/*RESERVED 0 */
++
++
++#endif
++/* -----------------------------------------------------------
++ *
++ *	Rate
++ *
++ * -----------------------------------------------------------
++ * CCK Rates, TxHT = 0 */
++#define DESC8723D_RATE1M				0x00
++#define DESC8723D_RATE2M				0x01
++#define DESC8723D_RATE5_5M				0x02
++#define DESC8723D_RATE11M				0x03
++
++/* OFDM Rates, TxHT = 0 */
++#define DESC8723D_RATE6M				0x04
++#define DESC8723D_RATE9M				0x05
++#define DESC8723D_RATE12M				0x06
++#define DESC8723D_RATE18M				0x07
++#define DESC8723D_RATE24M				0x08
++#define DESC8723D_RATE36M				0x09
++#define DESC8723D_RATE48M				0x0a
++#define DESC8723D_RATE54M				0x0b
++
++/* MCS Rates, TxHT = 1 */
++#define DESC8723D_RATEMCS0				0x0c
++#define DESC8723D_RATEMCS1				0x0d
++#define DESC8723D_RATEMCS2				0x0e
++#define DESC8723D_RATEMCS3				0x0f
++#define DESC8723D_RATEMCS4				0x10
++#define DESC8723D_RATEMCS5				0x11
++#define DESC8723D_RATEMCS6				0x12
++#define DESC8723D_RATEMCS7				0x13
++#define DESC8723D_RATEMCS8				0x14
++#define DESC8723D_RATEMCS9				0x15
++#define DESC8723D_RATEMCS10		0x16
++#define DESC8723D_RATEMCS11		0x17
++#define DESC8723D_RATEMCS12		0x18
++#define DESC8723D_RATEMCS13		0x19
++#define DESC8723D_RATEMCS14		0x1a
++#define DESC8723D_RATEMCS15		0x1b
++#define DESC8723D_RATEVHTSS1MCS0		0x2c
++#define DESC8723D_RATEVHTSS1MCS1		0x2d
++#define DESC8723D_RATEVHTSS1MCS2		0x2e
++#define DESC8723D_RATEVHTSS1MCS3		0x2f
++#define DESC8723D_RATEVHTSS1MCS4		0x30
++#define DESC8723D_RATEVHTSS1MCS5		0x31
++#define DESC8723D_RATEVHTSS1MCS6		0x32
++#define DESC8723D_RATEVHTSS1MCS7		0x33
++#define DESC8723D_RATEVHTSS1MCS8		0x34
++#define DESC8723D_RATEVHTSS1MCS9		0x35
++#define DESC8723D_RATEVHTSS2MCS0		0x36
++#define DESC8723D_RATEVHTSS2MCS1		0x37
++#define DESC8723D_RATEVHTSS2MCS2		0x38
++#define DESC8723D_RATEVHTSS2MCS3		0x39
++#define DESC8723D_RATEVHTSS2MCS4		0x3a
++#define DESC8723D_RATEVHTSS2MCS5		0x3b
++#define DESC8723D_RATEVHTSS2MCS6		0x3c
++#define DESC8723D_RATEVHTSS2MCS7		0x3d
++#define DESC8723D_RATEVHTSS2MCS8		0x3e
++#define DESC8723D_RATEVHTSS2MCS9		0x3f
++
++
++#define	RX_HAL_IS_CCK_RATE_8723D(pDesc)\
++	(GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE1M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE2M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE5_5M || \
++	 GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE11M)
++
++#ifdef CONFIG_TRX_BD_ARCH
++	struct tx_desc;
++#endif
++
++void rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc);
++void rtl8723d_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
++void rtl8723d_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
++void rtl8723d_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
++void rtl8723d_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
++void rtl8723d_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
++
++void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
++void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	s32 rtl8723ds_init_xmit_priv(PADAPTER padapter);
++	void rtl8723ds_free_xmit_priv(PADAPTER padapter);
++	s32 rtl8723ds_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8723ds_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	rtl8723ds_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8723ds_xmit_buf_handler(PADAPTER padapter);
++	thread_return rtl8723ds_xmit_thread(thread_context context);
++	#define hal_xmit_handler rtl8723ds_xmit_buf_handler
++#endif
++
++#ifdef CONFIG_USB_HCI
++	s32 rtl8723du_xmit_buf_handler(PADAPTER padapter);
++	#define hal_xmit_handler rtl8723du_xmit_buf_handler
++	s32 rtl8723du_init_xmit_priv(PADAPTER padapter);
++	void rtl8723du_free_xmit_priv(PADAPTER padapter);
++	s32 rtl8723du_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8723du_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	 rtl8723du_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	void rtl8723du_xmit_tasklet(void *priv);
++	s32 rtl8723du_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++	void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	s32 rtl8723de_init_xmit_priv(PADAPTER padapter);
++	void rtl8723de_free_xmit_priv(PADAPTER padapter);
++	struct xmit_buf *rtl8723de_dequeue_xmitbuf(struct rtw_tx_ring *ring);
++	void	rtl8723de_xmitframe_resume(_adapter *padapter);
++	s32 rtl8723de_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8723de_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	rtl8723de_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	void rtl8723de_xmit_tasklet(void *priv);
++#endif
++
++u8	BWMapping_8723D(PADAPTER Adapter, struct pkt_attrib *pattrib);
++u8	SCMapping_8723D(PADAPTER Adapter, struct pkt_attrib	*pattrib);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_cmd.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_cmd.h
+new file mode 100644
+index 000000000..a89a62806
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_cmd.h
+@@ -0,0 +1,158 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8812A_CMD_H__
++#define __RTL8812A_CMD_H__
++
++typedef enum _RTL8812_H2C_CMD {
++	H2C_8812_RSVDPAGE = 0,
++	H2C_8812_MSRRPT = 1,
++	H2C_8812_SCAN = 2,
++	H2C_8812_KEEP_ALIVE_CTRL = 3,
++	H2C_8812_DISCONNECT_DECISION = 4,
++
++	H2C_8812_INIT_OFFLOAD = 6,
++	H2C_8812_AP_OFFLOAD = 8,
++	H2C_8812_BCN_RSVDPAGE = 9,
++	H2C_8812_PROBERSP_RSVDPAGE = 10,
++
++	H2C_8812_SETPWRMODE = 0x20,
++	H2C_8812_PS_TUNING_PARA = 0x21,
++	H2C_8812_PS_TUNING_PARA2 = 0x22,
++	H2C_8812_PS_LPS_PARA = 0x23,
++	H2C_8812_P2P_PS_OFFLOAD = 0x24,
++	H2C_8812_INACTIVE_PS = 0x27,
++	H2C_8812_RA_MASK = 0x40,
++	H2C_8812_TxBF = 0x41,
++	H2C_8812_RSSI_REPORT = 0x42,
++	H2C_8812_IQ_CALIBRATION = 0x45,
++	H2C_8812_RA_PARA_ADJUST = 0x46,
++
++	H2C_8812_BT_FW_PATCH = 0x6a,
++
++	H2C_8812_WO_WLAN = 0x80,
++	H2C_8812_REMOTE_WAKE_CTRL = 0x81,
++	H2C_8812_AOAC_GLOBAL_INFO = 0x82,
++	H2C_8812_AOAC_RSVDPAGE = 0x83,
++	H2C_8812_FW_SWCHANNL = 0x87,
++
++	H2C_8812_TSF_RESET = 0xC0,
++
++	MAX_8812_H2CCMD
++} RTL8812_H2C_CMD;
++
++struct cmd_msg_parm {
++	u8 eid; /* element id */
++	u8 sz; /* sz */
++	u8 buf[6];
++};
++
++enum {
++	PWRS
++};
++
++struct H2C_SS_RFOFF_PARAM {
++	u8 ROFOn; /* 1: on, 0:off */
++	u16 gpio_period; /* unit: 1024 us */
++} __attribute__((packed));
++
++
++
++/* _RSVDPAGE_LOC_CMD0 */
++#define SET_8812_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8812_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_8812_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8812_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8812_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++/* _SETPWRMODE_PARM */
++#define SET_8812_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8812_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
++#define SET_8812_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
++#define SET_8812_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8812_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8812_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
++#define SET_8812_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++#define GET_8812_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)							LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
++
++/* _P2P_PS_OFFLOAD */
++#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ENABLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_CTWINDOW_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
++#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_NOA0_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
++#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_NOA1_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
++#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
++#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
++
++
++void	set_ra_ldpc_8812(struct cmn_sta_info *cmn_sta_info, BOOLEAN bLDPC);
++
++/* host message to firmware cmd */
++s32 fill_h2c_cmd_8812(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
++void rtl8812_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode);
++void rtl8812_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
++u8 rtl8812_set_rssi_cmd(PADAPTER padapter, u8 *param);
++void rtl8812_set_wowlan_cmd(_adapter *padapter, u8 enable);
++u8 GetTxBufferRsvdPageNum8812(_adapter *padapter, bool wowlan);
++
++#ifdef CONFIG_BT_COEXIST
++void rtl8812a_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
++#endif /* CONFIG_BT_COEXIST */
++#ifdef CONFIG_P2P_PS
++void rtl8812_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
++#endif /* CONFIG_P2P */
++
++#ifdef CONFIG_FWLPS_IN_IPS
++void rtl8812_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
++#endif
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_TDLS_CH_SW
++void rtl8812_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
++#endif
++#endif
++
++/* ------------------------------------
++ * C2H format
++ * ------------------------------------ */
++
++/* TX Beamforming */
++#define GET_8812_C2H_TXBF_ORIGINATE(_Header)			LE_BITS_TO_1BYTE(_Header, 0, 8)
++#define GET_8812_C2H_TXBF_MACID(_Header)				LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
++
++
++
++/* / TX Feedback Content */
++#define	USEC_UNIT_FOR_8812_C2H_TX_RPT_QUEUE_TIME			256
++
++#define	GET_8812_C2H_TX_RPT_QUEUE_SELECT(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 0, 5)
++#define	GET_8812_C2H_TX_RPT_PKT_BROCAST(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 5, 1)
++#define	GET_8812_C2H_TX_RPT_LIFE_TIME_OVER(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
++#define	GET_8812_C2H_TX_RPT_RETRY_OVER(_Header)				LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
++#define	GET_8812_C2H_TX_RPT_MAC_ID(_Header)					LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
++#define	GET_8812_C2H_TX_RPT_DATA_RETRY_CNT(_Header)		LE_BITS_TO_1BYTE((_Header + 2), 0, 6)
++#define	GET_8812_C2H_TX_RPT_QUEUE_TIME(_Header)				LE_BITS_TO_2BYTE((_Header + 3), 0, 16)	/* In unit of 256 microseconds. */
++#define	GET_8812_C2H_TX_RPT_FINAL_DATA_RATE(_Header)		LE_BITS_TO_1BYTE((_Header + 5), 0, 8)
++
++/* BT_FW_PATCH */
++#define SET_8812_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
++#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+4, 0, 8, __Value)
++#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+5, 0, 8, __Value)
++
++s32 c2h_handler_8812a(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
++
++#endif/* __RTL8812A_CMD_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_dm.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_dm.h
+new file mode 100644
+index 000000000..21a9abaa6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_dm.h
+@@ -0,0 +1,27 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8812A_DM_H__
++#define __RTL8812A_DM_H__
++
++void rtl8812_init_dm_priv(PADAPTER Adapter);
++void rtl8812_deinit_dm_priv(PADAPTER Adapter);
++void rtl8812_InitHalDm(PADAPTER Adapter);
++void rtl8812_HalDmWatchDog(PADAPTER Adapter);
++
++/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */
++
++/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_hal.h
+new file mode 100644
+index 000000000..3082c67c9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_hal.h
+@@ -0,0 +1,369 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8812A_HAL_H__
++#define __RTL8812A_HAL_H__
++
++/* #include "hal_com.h" */
++#include "hal_data.h"
++
++/* include HAL Related header after HAL Related compiling flags */
++#include "rtl8812a_spec.h"
++#include "rtl8812a_rf.h"
++#include "rtl8812a_dm.h"
++#include "rtl8812a_recv.h"
++#include "rtl8812a_xmit.h"
++#include "rtl8812a_cmd.h"
++#include "rtl8812a_led.h"
++#include "Hal8812PwrSeq.h"
++#include "Hal8821APwrSeq.h" /* for 8821A/8811A */
++#include "Hal8812PhyReg.h"
++#include "Hal8812PhyCfg.h"
++#ifdef DBG_CONFIG_ERROR_DETECT
++#include "rtl8812a_sreset.h"
++#endif
++
++/* ---------------------------------------------------------------------
++ *		RTL8812 Power Configuration CMDs for PCIe interface
++ * --------------------------------------------------------------------- */
++#define Rtl8812_NIC_PWR_ON_FLOW				rtl8812_power_on_flow
++#define Rtl8812_NIC_RF_OFF_FLOW				rtl8812_radio_off_flow
++#define Rtl8812_NIC_DISABLE_FLOW				rtl8812_card_disable_flow
++#define Rtl8812_NIC_ENABLE_FLOW				rtl8812_card_enable_flow
++#define Rtl8812_NIC_SUSPEND_FLOW				rtl8812_suspend_flow
++#define Rtl8812_NIC_RESUME_FLOW				rtl8812_resume_flow
++#define Rtl8812_NIC_PDN_FLOW					rtl8812_hwpdn_flow
++#define Rtl8812_NIC_LPS_ENTER_FLOW			rtl8812_enter_lps_flow
++#define Rtl8812_NIC_LPS_LEAVE_FLOW				rtl8812_leave_lps_flow
++
++/* ---------------------------------------------------------------------
++ *		RTL8821 Power Configuration CMDs for PCIe interface
++ * --------------------------------------------------------------------- */
++#define Rtl8821A_NIC_PWR_ON_FLOW				rtl8821A_power_on_flow
++#define Rtl8821A_NIC_RF_OFF_FLOW				rtl8821A_radio_off_flow
++#define Rtl8821A_NIC_DISABLE_FLOW				rtl8821A_card_disable_flow
++#define Rtl8821A_NIC_ENABLE_FLOW				rtl8821A_card_enable_flow
++#define Rtl8821A_NIC_SUSPEND_FLOW				rtl8821A_suspend_flow
++#define Rtl8821A_NIC_RESUME_FLOW				rtl8821A_resume_flow
++#define Rtl8821A_NIC_PDN_FLOW					rtl8821A_hwpdn_flow
++#define Rtl8821A_NIC_LPS_ENTER_FLOW			rtl8821A_enter_lps_flow
++#define Rtl8821A_NIC_LPS_LEAVE_FLOW			rtl8821A_leave_lps_flow
++
++
++#if 1 /* download firmware related data structure */
++#define FW_SIZE_8812			0x8000 /* Compatible with RTL8723 Maximal RAM code size 24K.   modified to 32k, TO compatible with 92d maximal fw size 32k */
++#define FW_START_ADDRESS		0x1000
++#define FW_END_ADDRESS		0x5FFF
++
++
++
++typedef struct _RT_FIRMWARE_8812 {
++	FIRMWARE_SOURCE	eFWSource;
++#ifdef CONFIG_EMBEDDED_FWIMG
++	u8			*szFwBuffer;
++#else
++	u8			szFwBuffer[FW_SIZE_8812];
++#endif
++	u32			ulFwLength;
++} RT_FIRMWARE_8812, *PRT_FIRMWARE_8812;
++
++/*
++ * This structure must be cared byte-ordering
++ *
++ * Added by tynli. 2009.12.04. */
++#define IS_FW_HEADER_EXIST_8812(_pFwHdr)	((GET_FIRMWARE_HDR_SIGNATURE_8812(_pFwHdr) & 0xFFF0) == 0x9500)
++
++#define IS_FW_HEADER_EXIST_8821(_pFwHdr)	((GET_FIRMWARE_HDR_SIGNATURE_8812(_pFwHdr) & 0xFFF0) == 0x2100)
++/* *****************************************************
++ *					Firmware Header(8-byte alinment required)
++ * *****************************************************
++ * --- LONG WORD 0 ---- */
++#define GET_FIRMWARE_HDR_SIGNATURE_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 0, 16) /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
++#define GET_FIRMWARE_HDR_CATEGORY_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */
++#define GET_FIRMWARE_HDR_FUNCTION_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
++#define GET_FIRMWARE_HDR_VERSION_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */
++#define GET_FIRMWARE_HDR_SUB_VER_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */
++#define GET_FIRMWARE_HDR_RSVD1_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8)
++
++/* --- LONG WORD 1 ---- */
++#define GET_FIRMWARE_HDR_MONTH_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 0, 8) /* Release time Month field */
++#define GET_FIRMWARE_HDR_DATE_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 8, 8) /* Release time Date field */
++#define GET_FIRMWARE_HDR_HOUR_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 16, 8)/* Release time Hour field */
++#define GET_FIRMWARE_HDR_MINUTE_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+8, 24, 8)/* Release time Minute field */
++#define GET_FIRMWARE_HDR_ROMCODE_SIZE_8812(__FwHdr)	LE_BITS_TO_4BYTE(__FwHdr+12, 0, 16)/* The size of RAM code */
++#define GET_FIRMWARE_HDR_RSVD2_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+12, 16, 16)
++
++/* --- LONG WORD 2 ---- */
++#define GET_FIRMWARE_HDR_SVN_IDX_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+16, 0, 32)/* The SVN entry index */
++#define GET_FIRMWARE_HDR_RSVD3_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+20, 0, 32)
++
++/* --- LONG WORD 3 ---- */
++#define GET_FIRMWARE_HDR_RSVD4_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+24, 0, 32)
++#define GET_FIRMWARE_HDR_RSVD5_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32)
++
++#endif /* download firmware related data structure */
++
++
++#define DRIVER_EARLY_INT_TIME_8812		0x05
++#define BCN_DMA_ATIME_INT_TIME_8812		0x02
++
++/* for 8812
++ * TX 128K, RX 16K, Page size 512B for TX, 128B for RX */
++#define MAX_RX_DMA_BUFFER_SIZE_8812	0x3E80 /* RX 16K */
++
++#ifdef CONFIG_WOWLAN
++	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
++#else
++	#define RESV_FMWF	0
++#endif
++
++#ifdef CONFIG_FW_C2H_DEBUG
++	#define RX_DMA_RESERVED_SIZE_8812	0x100	/* 256B, reserved for c2h debug message */
++#else
++	#define RX_DMA_RESERVED_SIZE_8812	0x0	/* 0B */
++#endif
++#define RX_DMA_BOUNDARY_8812		(MAX_RX_DMA_BUFFER_SIZE_8812 - RX_DMA_RESERVED_SIZE_8812 - 1)
++
++#define PAGE_SIZE_TX_8812A PAGE_SIZE_512
++
++/* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8812A
++ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
++#define BCNQ_PAGE_NUM_8812		(MAX_BEACON_LEN / PAGE_SIZE_TX_8812A + 6) /*0x07*/
++
++/* For WoWLan , more reserved page
++ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, AOAC rpt: 1,PNO: 6
++ * NS offload: 1 NDP info: 1
++ */
++#ifdef CONFIG_WOWLAN
++	#define WOWLAN_PAGE_NUM_8812	0x08
++#else
++	#define WOWLAN_PAGE_NUM_8812	0x00
++#endif
++
++
++#ifdef CONFIG_BEAMFORMER_FW_NDPA
++	#define FW_NDPA_PAGE_NUM	0x02
++#else
++	#define FW_NDPA_PAGE_NUM	0x00
++#endif
++
++#ifdef DBG_FW_DEBUG_MSG_PKT
++	#define FW_DBG_MSG_PKT_PAGE_NUM_8812	0x01
++#else
++	#define FW_DBG_MSG_PKT_PAGE_NUM_8812	0x00
++#endif /*DBG_FW_DEBUG_MSG_PKT*/
++
++#define TX_TOTAL_PAGE_NUMBER_8812	(0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812 - FW_NDPA_PAGE_NUM - FW_DBG_MSG_PKT_PAGE_NUM_8812)
++#define TX_PAGE_BOUNDARY_8812			(TX_TOTAL_PAGE_NUMBER_8812 + 1)
++
++#define TX_PAGE_BOUNDARY_WOWLAN_8812		(0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812 + 1)
++
++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8812	TX_TOTAL_PAGE_NUMBER_8812
++#define WMM_NORMAL_TX_PAGE_BOUNDARY_8812		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8812 + 1)
++
++/* For Normal Chip Setting
++ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8812 */
++#define NORMAL_PAGE_NUM_LPQ_8812				0x10
++#define NORMAL_PAGE_NUM_HPQ_8812			0x10
++#define NORMAL_PAGE_NUM_NPQ_8812			0x00
++
++#define WMM_NORMAL_PAGE_NUM_HPQ_8812		0x30
++#define WMM_NORMAL_PAGE_NUM_LPQ_8812		0x20
++#define WMM_NORMAL_PAGE_NUM_NPQ_8812		0x20
++
++
++/* for 8821A
++ * TX 64K, RX 16K, Page size 256B for TX, 128B for RX */
++#define PAGE_SIZE_TX_8821A					256
++#define PAGE_SIZE_RX_8821A					128
++
++#define MAX_RX_DMA_BUFFER_SIZE_8821			0x3E80 /* RX 16K */
++
++#ifdef CONFIG_FW_C2H_DEBUG
++	#define RX_DMA_RESERVED_SIZE_8821	0x100	/* 256B, reserved for c2h debug message */
++#else
++	#define RX_DMA_RESERVED_SIZE_8821	0x0	/* 0B */
++#endif
++#define RX_DMA_BOUNDARY_8821		(MAX_RX_DMA_BUFFER_SIZE_8821 - RX_DMA_RESERVED_SIZE_8821 - 1)
++
++/* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8821A
++ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
++
++#define BCNQ_PAGE_NUM_8821		(MAX_BEACON_LEN / PAGE_SIZE_TX_8821A + 6) /*0x08*/
++
++
++/* For WoWLan , more reserved page
++ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, PNO: 6 */
++#ifdef CONFIG_WOWLAN
++	#define WOWLAN_PAGE_NUM_8821	0x06
++#else
++	#define WOWLAN_PAGE_NUM_8821	0x00
++#endif
++
++#define TX_TOTAL_PAGE_NUMBER_8821	(0xFF - BCNQ_PAGE_NUM_8821 - WOWLAN_PAGE_NUM_8821)
++#define TX_PAGE_BOUNDARY_8821				(TX_TOTAL_PAGE_NUMBER_8821 + 1)
++/* #define TX_PAGE_BOUNDARY_WOWLAN_8821		0xE0 */
++
++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8821	TX_TOTAL_PAGE_NUMBER_8821
++#define WMM_NORMAL_TX_PAGE_BOUNDARY_8821		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8821 + 1)
++
++
++/* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */
++#define NORMAL_PAGE_NUM_LPQ_8821			0x08/* 0x10 */
++#define NORMAL_PAGE_NUM_HPQ_8821		0x08/* 0x10 */
++#define NORMAL_PAGE_NUM_NPQ_8821		0x00
++#define NORMAL_PAGE_NUM_EPQ_8821			0x04
++
++#define WMM_NORMAL_PAGE_NUM_HPQ_8821		0x30
++#define WMM_NORMAL_PAGE_NUM_LPQ_8821		0x20
++#define WMM_NORMAL_PAGE_NUM_NPQ_8821		0x20
++#define WMM_NORMAL_PAGE_NUM_EPQ_8821		0x00
++
++#define MCC_NORMAL_PAGE_NUM_HPQ_8821		0x10
++#define MCC_NORMAL_PAGE_NUM_LPQ_8821		0x10
++#define MCC_NORMAL_PAGE_NUM_NPQ_8821		0x10
++
++#define	EFUSE_HIDDEN_812AU					0
++#define	EFUSE_HIDDEN_812AU_VS				1
++#define	EFUSE_HIDDEN_812AU_VL				2
++#define	EFUSE_HIDDEN_812AU_VN				3
++
++#if 0
++#define EFUSE_REAL_CONTENT_LEN_JAGUAR		1024
++#define HWSET_MAX_SIZE_JAGUAR					1024
++#else
++#define EFUSE_REAL_CONTENT_LEN_JAGUAR		512
++#define HWSET_MAX_SIZE_JAGUAR					512
++#endif
++
++#define EFUSE_MAX_BANK_8812A					2
++#define EFUSE_MAP_LEN_JAGUAR					512
++#define EFUSE_MAX_SECTION_JAGUAR				64
++#define EFUSE_MAX_WORD_UNIT_JAGUAR			4
++#define EFUSE_IC_ID_OFFSET_JAGUAR				506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
++#define AVAILABLE_EFUSE_ADDR_8812(addr)	(addr < EFUSE_REAL_CONTENT_LEN_JAGUAR)
++/* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
++ * 9bytes + 1byt + 5bytes and pre 1byte.
++ * For worst case:
++ * | 2byte|----8bytes----|1byte|--7bytes--|  */ /* 92D */
++#define EFUSE_OOB_PROTECT_BYTES_JAGUAR		18	/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */
++#define EFUSE_PROTECT_BYTES_BANK_JAGUAR		16
++
++#define INCLUDE_MULTI_FUNC_BT(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
++#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
++
++/* #define IS_MULTI_FUNC_CHIP(_Adapter)	(((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */
++
++/* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */
++#define HAL_EFUSE_MEMORY
++
++/* ********************************************************
++ *			EFUSE for BT definition
++ * ******************************************************** */
++#define BANK_NUM			2
++#define EFUSE_BT_REAL_BANK_CONTENT_LEN	512
++#define EFUSE_BT_REAL_CONTENT_LEN	\
++	(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)
++#define EFUSE_BT_MAP_LEN		1024	/* 1k bytes */
++#define EFUSE_BT_MAX_SECTION		(EFUSE_BT_MAP_LEN / 8)
++#define EFUSE_PROTECT_BYTES_BANK	16
++
++#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_BT_REAL_CONTENT_LEN)
++
++#ifdef CONFIG_FILE_FWIMG
++extern char *rtw_fw_file_path;
++#ifdef CONFIG_WOWLAN
++extern char *rtw_fw_wow_file_path;
++#endif
++#ifdef CONFIG_MP_INCLUDED
++extern char *rtw_fw_mp_bt_file_path;
++#endif
++#endif
++
++
++/* rtl8812_hal_init.c */
++void	_8051Reset8812(PADAPTER padapter);
++s32	FirmwareDownload8812(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw);
++void	InitializeFirmwareVars8812(PADAPTER padapter);
++
++s32	_LLTWrite_8812A(PADAPTER Adapter, u32 address, u32 data);
++s32	InitLLTTable8812A(PADAPTER padapter, u8 txpktbuf_bndy);
++void InitRDGSetting8812A(PADAPTER padapter);
++
++void CheckAutoloadState8812A(PADAPTER padapter);
++
++/* EFuse */
++u8	GetEEPROMSize8812A(PADAPTER padapter);
++void InitPGData8812A(PADAPTER padapter);
++void	Hal_EfuseParseIDCode8812A(PADAPTER padapter, u8 *hwinfo);
++void	Hal_ReadPROMVersion8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void	Hal_ReadTxPowerInfo8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
++void	Hal_ReadBoardType8812A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void	Hal_ReadThermalMeter_8812A(PADAPTER	Adapter, u8 *PROMContent, BOOLEAN	AutoloadFail);
++void	Hal_ReadChannelPlan8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void	Hal_EfuseParseXtal_8812A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void	Hal_ReadAntennaDiversity8812A(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
++void	Hal_ReadAmplifierType_8812A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
++void	Hal_ReadPAType_8821A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
++void	Hal_ReadRFEType_8812A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
++void	Hal_EfuseParseBTCoexistInfo8812A(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void	hal_ReadUsbType_8812AU(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
++#ifdef CONFIG_MP_INCLUDED
++int	FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
++#endif
++void	Hal_ReadRemoteWakeup_8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++
++BOOLEAN HalDetectPwrDownMode8812(PADAPTER Adapter);
++void Hal_EfuseParseKFreeData_8821A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
++
++#ifdef CONFIG_WOWLAN
++void Hal_DetectWoWMode(PADAPTER pAdapter);
++#endif /* CONFIG_WOWLAN */
++
++void _InitBeaconParameters_8812A(PADAPTER padapter);
++void SetBeaconRelatedRegisters8812A(PADAPTER padapter);
++
++void ReadRFType8812A(PADAPTER padapter);
++void InitDefaultValue8821A(PADAPTER padapter);
++
++u8 SetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval);
++void GetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval);
++u8 SetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
++u8 GetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
++void rtl8812_set_hal_ops(struct hal_ops *pHalFunc);
++void init_hal_spec_8812a(_adapter *adapter);
++void init_hal_spec_8821a(_adapter *adapter);
++
++u32 upload_txpktbuf_8812au(_adapter *adapter, u8 *buf, u32 buflen);
++
++void rtl8812_start_thread(PADAPTER padapter);
++void rtl8812_stop_thread(PADAPTER padapter);
++
++#ifdef CONFIG_PCI_HCI
++BOOLEAN	InterruptRecognized8812AE(PADAPTER Adapter);
++void	UpdateInterruptMask8812AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
++void	InitTRXDescHwAddress8812AE(PADAPTER Adapter);
++#endif
++
++#ifdef CONFIG_BT_COEXIST
++void rtl8812a_combo_card_WifiOnlyHwInit(PADAPTER Adapter);
++#endif
++
++void
++Hal_PatchwithJaguar_8812(
++		PADAPTER				Adapter,
++		RT_MEDIA_STATUS		MediaStatus
++);
++
++#endif /* __RTL8188E_HAL_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_led.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_led.h
+new file mode 100644
+index 000000000..30c676e52
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_led.h
+@@ -0,0 +1,41 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8812A_LED_H__
++#define __RTL8812A_LED_H__
++#ifdef CONFIG_RTW_LED
++#ifdef CONFIG_RTW_SW_LED
++/* ********************************************************************************
++ * Interface to manipulate LED objects.
++ * ******************************************************************************** */
++#ifdef CONFIG_USB_HCI
++void rtl8812au_InitSwLeds(PADAPTER padapter);
++void rtl8812au_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_PCI_HCI
++void rtl8812ae_InitSwLeds(PADAPTER padapter);
++void rtl8812ae_DeInitSwLeds(PADAPTER padapter);
++#endif
++#ifdef CONFIG_SDIO_HCI
++void rtl8821as_InitSwLeds(PADAPTER padapter);
++void rtl8821as_DeInitSwLeds(PADAPTER padapter);
++#endif
++#endif/*CONFIG_RTW_SW_LED*/
++#endif/*#ifdef CONFIG_RTW_LED*/
++
++#ifdef CONFIG_SDIO_HCI
++void rtl8821as_init_led_circuit(PADAPTER adapter);
++#endif
++
++#endif /*__RTL8812A_LED_H__*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_recv.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_recv.h
+new file mode 100644
+index 000000000..5fa06e512
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_recv.h
+@@ -0,0 +1,149 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8812A_RECV_H__
++#define __RTL8812A_RECV_H__
++
++#if defined(CONFIG_USB_HCI)
++
++	#ifndef MAX_RECVBUF_SZ
++		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
++			#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
++				#define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/
++			#else
++				#define MAX_RECVBUF_SZ (32768)  /*32k*/
++			#endif
++			/* #define MAX_RECVBUF_SZ (24576) */ /* 24k */
++			/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
++			/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
++			/* #define MAX_RECVBUF_SZ (15360) */ /* 15k < 16k */
++			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
++			#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
++				#undef MAX_RECVBUF_SZ
++				#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
++			#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
++		#else
++			#define MAX_RECVBUF_SZ (4000) /* about 4K */
++		#endif
++	#endif /* !MAX_RECVBUF_SZ */
++
++#elif defined(CONFIG_PCI_HCI)
++	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
++	/*	#define MAX_RECVBUF_SZ (9100) */
++	/* #else */
++	#define MAX_RECVBUF_SZ (4000) /* about 4K
++	* #endif */
++
++
++#elif defined(CONFIG_SDIO_HCI)
++
++	#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8821 + 1)
++
++#endif
++
++
++/* Rx smooth factor */
++#define Rx_Smooth_Factor (20)
++
++/* DWORD 0 */
++#define SET_RX_STATUS_DESC_PKT_LEN_8812(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
++#define SET_RX_STATUS_DESC_EOR_8812(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
++#define SET_RX_STATUS_DESC_OWN_8812(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
++
++#define GET_RX_STATUS_DESC_PKT_LEN_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
++#define GET_RX_STATUS_DESC_CRC32_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
++#define GET_RX_STATUS_DESC_ICV_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
++#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8812(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
++#define GET_RX_STATUS_DESC_SECURITY_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
++#define GET_RX_STATUS_DESC_QOS_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
++#define GET_RX_STATUS_DESC_SHIFT_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
++#define GET_RX_STATUS_DESC_PHY_STATUS_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
++#define GET_RX_STATUS_DESC_SWDEC_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
++#define GET_RX_STATUS_DESC_LAST_SEG_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
++#define GET_RX_STATUS_DESC_FIRST_SEG_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
++#define GET_RX_STATUS_DESC_EOR_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
++#define GET_RX_STATUS_DESC_OWN_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
++
++/* DWORD 1 */
++#define GET_RX_STATUS_DESC_MACID_8812(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
++#define GET_RX_STATUS_DESC_TID_8812(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
++#define GET_RX_STATUS_DESC_AMSDU_8812(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
++#define GET_RX_STATUS_DESC_RXID_MATCH_8812(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
++#define GET_RX_STATUS_DESC_PAGGR_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
++#define GET_RX_STATUS_DESC_A1_FIT_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
++#define GET_RX_STATUS_DESC_CHKERR_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
++#define GET_RX_STATUS_DESC_IPVER_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
++#define GET_RX_STATUS_DESC_IS_TCPUDP__8812(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
++#define GET_RX_STATUS_DESC_CHK_VLD_8812(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
++#define GET_RX_STATUS_DESC_PAM_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
++#define GET_RX_STATUS_DESC_PWR_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
++#define GET_RX_STATUS_DESC_MORE_DATA_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
++#define GET_RX_STATUS_DESC_MORE_FRAG_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
++#define GET_RX_STATUS_DESC_TYPE_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
++#define GET_RX_STATUS_DESC_MC_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
++#define GET_RX_STATUS_DESC_BC_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
++
++/* DWORD 2 */
++#define GET_RX_STATUS_DESC_SEQ_8812(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
++#define GET_RX_STATUS_DESC_FRAG_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
++#define GET_RX_STATUS_DESC_RX_IS_QOS_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
++#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8812(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
++#define GET_RX_STATUS_DESC_RPT_SEL_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
++
++/* DWORD 3 */
++#define GET_RX_STATUS_DESC_RX_RATE_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
++#define GET_RX_STATUS_DESC_HTC_8812(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
++#define GET_RX_STATUS_DESC_EOSP_8812(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
++#define GET_RX_STATUS_DESC_BSSID_FIT_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
++#ifdef CONFIG_USB_RX_AGGREGATION
++#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8812(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
++#endif
++#define GET_RX_STATUS_DESC_PATTERN_MATCH_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
++#define GET_RX_STATUS_DESC_UNICAST_MATCH_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
++#define GET_RX_STATUS_DESC_MAGIC_MATCH_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
++
++/* DWORD 6 */
++#define GET_RX_STATUS_DESC_SPLCP_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
++#define GET_RX_STATUS_DESC_LDPC_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
++#define GET_RX_STATUS_DESC_STBC_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
++#define GET_RX_STATUS_DESC_BW_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
++
++/* DWORD 5 */
++#define GET_RX_STATUS_DESC_TSFL_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
++
++#define GET_RX_STATUS_DESC_BUFF_ADDR_8812(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
++#define GET_RX_STATUS_DESC_BUFF_ADDR64_8812(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
++
++#define SET_RX_STATUS_DESC_BUFF_ADDR_8812(__pRxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
++
++
++#ifdef CONFIG_SDIO_HCI
++s32 InitRecvPriv8821AS(PADAPTER padapter);
++void FreeRecvPriv8821AS(PADAPTER padapter);
++#endif /* CONFIG_SDIO_HCI */
++
++#ifdef CONFIG_USB_HCI
++void rtl8812au_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
++s32 rtl8812au_init_recv_priv(PADAPTER padapter);
++void rtl8812au_free_recv_priv(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++s32 rtl8812ae_init_recv_priv(PADAPTER padapter);
++void rtl8812ae_free_recv_priv(PADAPTER padapter);
++#endif
++
++void rtl8812_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
++
++#endif /* __RTL8812A_RECV_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_rf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_rf.h
+new file mode 100644
+index 000000000..c5d9aaee3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_rf.h
+@@ -0,0 +1,28 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8812A_RF_H__
++#define __RTL8812A_RF_H__
++
++void
++PHY_RF6052SetBandwidth8812(
++		PADAPTER				Adapter,
++		enum channel_width		Bandwidth);
++
++
++int
++PHY_RF6052_Config_8812(
++		PADAPTER	Adapter);
++
++#endif/* __RTL8188E_RF_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_spec.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_spec.h
+new file mode 100644
+index 000000000..37ba24722
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_spec.h
+@@ -0,0 +1,263 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8812A_SPEC_H__
++#define __RTL8812A_SPEC_H__
++
++#include <drv_conf.h>
++
++
++/* ************************************************************
++* 8812 Regsiter offset definition
++* ************************************************************ */
++
++/* ************************************************************
++*
++* ************************************************************ */
++
++/* -----------------------------------------------------
++*
++*	0x0000h ~ 0x00FFh	System Configuration
++*
++* ----------------------------------------------------- */
++#define REG_SYS_CLKR_8812A				0x0008
++#define REG_AFE_PLL_CTRL_8812A		0x0028
++#define REG_HSIMR_8812					0x0058
++#define REG_HSISR_8812					0x005c
++#define REG_GPIO_EXT_CTRL				0x0060
++#define REG_GPIO_STATUS_8812			0x006C
++#define REG_SDIO_CTRL_8812				0x0070
++#define REG_OPT_CTRL_8812				0x0074
++#define REG_RF_B_CTRL_8812				0x0076
++#define REG_FW_DRV_MSG_8812			0x0088
++#define REG_HMEBOX_E2_E3_8812			0x008C
++#define REG_HIMR0_8812					0x00B0
++#define REG_HISR0_8812					0x00B4
++#define REG_HIMR1_8812					0x00B8
++#define REG_HISR1_8812					0x00BC
++#define REG_EFUSE_BURN_GNT_8812		0x00CF
++#define REG_SYS_CFG1_8812				0x00FC
++
++/* -----------------------------------------------------
++*
++*	0x0100h ~ 0x01FFh	MACTOP General Configuration
++*
++* ----------------------------------------------------- */
++#define REG_CR_8812A					0x100
++#define REG_PKTBUF_DBG_ADDR			(REG_PKTBUF_DBG_CTRL)
++#define REG_RXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+2)
++#define REG_TXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+3)
++#define REG_WOWLAN_WAKE_REASON			REG_MCUTST_WOWLAN
++
++#define REG_RSVD3_8812					0x0168
++#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
++#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
++#define REG_C2HEVT_CMD_LEN_88XX		0x01AE
++
++#define REG_HMEBOX_EXT0_8812			0x01F0
++#define REG_HMEBOX_EXT1_8812			0x01F4
++#define REG_HMEBOX_EXT2_8812			0x01F8
++#define REG_HMEBOX_EXT3_8812			0x01FC
++
++/* -----------------------------------------------------
++*
++*	0x0200h ~ 0x027Fh	TXDMA Configuration
++*
++* ----------------------------------------------------- */
++#define REG_DWBCN0_CTRL_8812				REG_TDECTRL
++#define REG_DWBCN1_CTRL_8812				0x0228
++
++/* -----------------------------------------------------
++*
++*	0x0280h ~ 0x02FFh	RXDMA Configuration
++*
++* ----------------------------------------------------- */
++#define REG_TDECTRL_8812A				0x0208
++#define REG_RXDMA_CONTROL_8812A		0x0286		/*Control the RX DMA.*/
++#define REG_RXDMA_PRO_8812			0x0290
++#define REG_EARLY_MODE_CONTROL_8812	0x02BC
++#define REG_RSVD5_8812					0x02F0
++#define REG_RSVD6_8812					0x02F4
++#define REG_RSVD7_8812					0x02F8
++#define REG_RSVD8_8812					0x02FC
++
++
++/* -----------------------------------------------------
++*
++*	0x0300h ~ 0x03FFh	PCIe
++*
++* ----------------------------------------------------- */
++#define	REG_PCIE_CTRL_REG_8812A			0x0300
++#define	REG_DBI_WDATA_8812			0x0348	/* DBI Write Data */
++#define	REG_DBI_RDATA_8812			0x034C	/* DBI Read Data */
++#define	REG_DBI_ADDR_8812			0x0350	/* DBI Address */
++#define	REG_DBI_FLAG_8812			0x0352	/* DBI Read/Write Flag */
++#define	REG_MDIO_WDATA_8812			0x0354	/* MDIO for Write PCIE PHY */
++#define	REG_MDIO_RDATA_8812			0x0356	/* MDIO for Reads PCIE PHY */
++#define	REG_MDIO_CTL_8812			0x0358	/* MDIO for Control */
++#define REG_PCIE_HRPWM_8812A			0x0361  /* PCIe RPWM */
++#define REG_PCIE_HCPWM_8812A			0x0363  /* PCIe CPWM */
++
++#define	REG_PCIE_MULTIFET_CTRL_8812	0x036A	/* PCIE Multi-Fethc Control */
++
++/* -----------------------------------------------------
++*
++*	0x0400h ~ 0x047Fh	Protocol Configuration
++*
++* ----------------------------------------------------- */
++#define REG_TXPKT_EMPTY_8812A			0x041A
++#define REG_FWHW_TXQ_CTRL_8812A		0x0420
++#define REG_TXBF_CTRL_8812A			0x042C
++#define REG_ARFR0_8812					0x0444
++#define REG_ARFR1_8812					0x044C
++#define REG_CCK_CHECK_8812				0x0454
++#define REG_AMPDU_MAX_TIME_8812		0x0456
++#define REG_TXPKTBUF_BCNQ_BDNY1_8812	0x0457
++
++#define REG_AMPDU_MAX_LENGTH_8812	0x0458
++#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8812	0x045D
++#define REG_NDPA_OPT_CTRL_8812A		0x045F
++#define REG_DATA_SC_8812				0x0483
++#ifdef CONFIG_WOWLAN
++#define REG_TXPKTBUF_IV_LOW             0x0484
++#define REG_TXPKTBUF_IV_HIGH            0x0488
++#endif
++#define REG_ARFR2_8812					0x048C
++#define REG_ARFR3_8812					0x0494
++#define REG_TXRPT_START_OFFSET		0x04AC
++#define REG_AMPDU_BURST_MODE_8812	0x04BC
++#define REG_HT_SINGLE_AMPDU_8812		0x04C7
++#define REG_MACID_PKT_DROP0_8812		0x04D0
++
++/* -----------------------------------------------------
++*
++*	0x0500h ~ 0x05FFh	EDCA Configuration
++*
++* ----------------------------------------------------- */
++#define REG_TXPAUSE_8812A				0x0522
++#define REG_CTWND_8812					0x0572
++#define REG_SECONDARY_CCA_CTRL_8812	0x0577
++#define REG_SCH_TXCMD_8812A			0x05F8
++
++/* -----------------------------------------------------
++*
++*	0x0600h ~ 0x07FFh	WMAC Configuration
++*
++* ----------------------------------------------------- */
++#define REG_MAC_CR_8812				0x0600
++
++#define REG_MAC_TX_SM_STATE_8812		0x06B4
++
++/* Power */
++#define REG_BFMER0_INFO_8812A			0x06E4
++#define REG_BFMER1_INFO_8812A			0x06EC
++#define REG_CSI_RPT_PARAM_BW20_8812A	0x06F4
++#define REG_CSI_RPT_PARAM_BW40_8812A	0x06F8
++#define REG_CSI_RPT_PARAM_BW80_8812A	0x06FC
++
++/* Hardware Port 2 */
++#define REG_BFMEE_SEL_8812A			0x0714
++#define REG_SND_PTCL_CTRL_8812A		0x0718
++
++
++/* -----------------------------------------------------
++*
++*	Redifine register definition for compatibility
++*
++* ----------------------------------------------------- */
++
++/* TODO: use these definition when using REG_xxx naming rule.
++* NOTE: DO NOT Remove these definition. Use later. */
++#define	ISR_8812							REG_HISR0_8812
++
++/* ----------------------------------------------------------------------------
++* 8195 IMR/ISR bits						(offset 0xB0,  8bits)
++* ---------------------------------------------------------------------------- */
++#define	IMR_DISABLED_8812					0
++/* IMR DW0(0x00B0-00B3) Bit 0-31 */
++#define	IMR_TIMER2_8812					BIT31		/* Timeout interrupt 2 */
++#define	IMR_TIMER1_8812					BIT30		/* Timeout interrupt 1	 */
++#define	IMR_PSTIMEOUT_8812				BIT29		/* Power Save Time Out Interrupt */
++#define	IMR_GTINT4_8812					BIT28		/* When GTIMER4 expires, this bit is set to 1	 */
++#define	IMR_GTINT3_8812					BIT27		/* When GTIMER3 expires, this bit is set to 1	 */
++#define	IMR_TXBCN0ERR_8812				BIT26		/* Transmit Beacon0 Error			 */
++#define	IMR_TXBCN0OK_8812					BIT25		/* Transmit Beacon0 OK			 */
++#define	IMR_TSF_BIT32_TOGGLE_8812		BIT24		/* TSF Timer BIT32 toggle indication interrupt			 */
++#define	IMR_BCNDMAINT0_8812				BIT20		/* Beacon DMA Interrupt 0			 */
++#define	IMR_BCNDERR0_8812					BIT16		/* Beacon Queue DMA OK0			 */
++#define	IMR_HSISR_IND_ON_INT_8812		BIT15		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
++#define	IMR_BCNDMAINT_E_8812				BIT14		/* Beacon DMA Interrupt Extension for Win7			 */
++#define	IMR_ATIMEND_8812					BIT12		/* CTWidnow End or ATIM Window End */
++#define	IMR_C2HCMD_8812					BIT10		/* CPU to Host Command INT Status, Write 1 clear	 */
++#define	IMR_CPWM2_8812					BIT9			/* CPU power Mode exchange INT Status, Write 1 clear	 */
++#define	IMR_CPWM_8812						BIT8			/* CPU power Mode exchange INT Status, Write 1 clear	 */
++#define	IMR_HIGHDOK_8812					BIT7			/* High Queue DMA OK	 */
++#define	IMR_MGNTDOK_8812					BIT6			/* Management Queue DMA OK	 */
++#define	IMR_BKDOK_8812					BIT5			/* AC_BK DMA OK		 */
++#define	IMR_BEDOK_8812					BIT4			/* AC_BE DMA OK	 */
++#define	IMR_VIDOK_8812					BIT3			/* AC_VI DMA OK		 */
++#define	IMR_VODOK_8812					BIT2			/* AC_VO DMA OK	 */
++#define	IMR_RDU_8812						BIT1			/* Rx Descriptor Unavailable	 */
++#define	IMR_ROK_8812						BIT0			/* Receive DMA OK */
++
++/* IMR DW1(0x00B4-00B7) Bit 0-31 */
++#define	IMR_BCNDMAINT7_8812				BIT27		/* Beacon DMA Interrupt 7 */
++#define	IMR_BCNDMAINT6_8812				BIT26		/* Beacon DMA Interrupt 6 */
++#define	IMR_BCNDMAINT5_8812				BIT25		/* Beacon DMA Interrupt 5 */
++#define	IMR_BCNDMAINT4_8812				BIT24		/* Beacon DMA Interrupt 4 */
++#define	IMR_BCNDMAINT3_8812				BIT23		/* Beacon DMA Interrupt 3 */
++#define	IMR_BCNDMAINT2_8812				BIT22		/* Beacon DMA Interrupt 2 */
++#define	IMR_BCNDMAINT1_8812				BIT21		/* Beacon DMA Interrupt 1 */
++#define	IMR_BCNDOK7_8812					BIT20		/* Beacon Queue DMA OK Interrup 7 */
++#define	IMR_BCNDOK6_8812					BIT19		/* Beacon Queue DMA OK Interrup 6 */
++#define	IMR_BCNDOK5_8812					BIT18		/* Beacon Queue DMA OK Interrup 5 */
++#define	IMR_BCNDOK4_8812					BIT17		/* Beacon Queue DMA OK Interrup 4 */
++#define	IMR_BCNDOK3_8812					BIT16		/* Beacon Queue DMA OK Interrup 3 */
++#define	IMR_BCNDOK2_8812					BIT15		/* Beacon Queue DMA OK Interrup 2 */
++#define	IMR_BCNDOK1_8812					BIT14		/* Beacon Queue DMA OK Interrup 1 */
++#define	IMR_ATIMEND_E_8812				BIT13		/* ATIM Window End Extension for Win7 */
++#define	IMR_TXERR_8812					BIT11		/* Tx Error Flag Interrupt Status, write 1 clear. */
++#define	IMR_RXERR_8812					BIT10		/* Rx Error Flag INT Status, Write 1 clear */
++#define	IMR_TXFOVW_8812					BIT9			/* Transmit FIFO Overflow */
++#define	IMR_RXFOVW_8812					BIT8			/* Receive FIFO Overflow */
++
++
++#ifdef CONFIG_PCI_HCI
++/* #define IMR_RX_MASK		(IMR_ROK_8812|IMR_RDU_8812|IMR_RXFOVW_8812) */
++#define IMR_TX_MASK			(IMR_VODOK_8812 | IMR_VIDOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812 | IMR_MGNTDOK_8812 | IMR_HIGHDOK_8812)
++
++#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8812 | IMR_TXBCN0OK_8812 | IMR_TXBCN0ERR_8812 | IMR_BCNDERR0_8812)
++
++#define RT_AC_INT_MASKS	(IMR_VIDOK_8812 | IMR_VODOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812)
++#endif
++
++
++/* ****************************************************************************
++* Regsiter Bit and Content definition
++* **************************************************************************** */
++
++/* 2 ACMHWCTRL 0x05C0 */
++#define	AcmHw_HwEn_8812				BIT(0)
++#define	AcmHw_VoqEn_8812				BIT(1)
++#define	AcmHw_ViqEn_8812				BIT(2)
++#define	AcmHw_BeqEn_8812				BIT(3)
++#define	AcmHw_VoqStatus_8812			BIT(5)
++#define	AcmHw_ViqStatus_8812			BIT(6)
++#define	AcmHw_BeqStatus_8812			BIT(7)
++
++#endif /* __RTL8812A_SPEC_H__ */
++
++#ifdef CONFIG_RTL8821A
++#include "rtl8821a_spec.h"
++#endif /* CONFIG_RTL8821A */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_sreset.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_sreset.h
+new file mode 100644
+index 000000000..d4bbd5867
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_sreset.h
+@@ -0,0 +1,24 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL88812A_SRESET_H_
++#define _RTL8812A_SRESET_H_
++
++#include <rtw_sreset.h>
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++extern void rtl8812_sreset_xmit_status_check(_adapter *padapter);
++extern void rtl8812_sreset_linked_status_check(_adapter *padapter);
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_xmit.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_xmit.h
+new file mode 100644
+index 000000000..0d9496419
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8812a_xmit.h
+@@ -0,0 +1,365 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8812A_XMIT_H__
++#define __RTL8812A_XMIT_H__
++
++
++/* For 88e early mode */
++#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
++#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
++#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
++#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
++#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
++#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
++#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
++
++/*
++ * defined for TX DESC Operation
++ *   */
++
++#define MAX_TID (15)
++
++/* OFFSET 0 */
++#define OFFSET_SZ	0
++#define OFFSET_SHT	16
++#define BMC			BIT(24)
++#define LSG			BIT(26)
++#define FSG			BIT(27)
++#define OWN		BIT(31)
++
++
++/* OFFSET 4 */
++#define PKT_OFFSET_SZ		0
++#define QSEL_SHT			8
++#define RATE_ID_SHT			16
++#define NAVUSEHDR			BIT(20)
++#define SEC_TYPE_SHT		22
++#define PKT_OFFSET_SHT		26
++
++/* OFFSET 8 */
++#define AGG_EN				BIT(12)
++#define AGG_BK				BIT(16)
++#define AMPDU_DENSITY_SHT	20
++#define ANTSEL_A			BIT(24)
++#define ANTSEL_B			BIT(25)
++#define TX_ANT_CCK_SHT		26
++#define TX_ANTL_SHT			28
++#define TX_ANT_HT_SHT		30
++
++/* OFFSET 12 */
++#define SEQ_SHT				16
++#define EN_HWSEQ			BIT(31)
++
++/* OFFSET 16 */
++#define QOS					BIT(6)
++#define	HW_SSN				BIT(7)
++#define USERATE				BIT(8)
++#define DISDATAFB			BIT(10)
++#define CTS_2_SELF			BIT(11)
++#define	RTS_EN				BIT(12)
++#define	HW_RTS_EN			BIT(13)
++#define DATA_SHORT			BIT(24)
++#define PWR_STATUS_SHT	15
++#define DATA_SC_SHT		20
++#define DATA_BW				BIT(25)
++
++/* OFFSET 20 */
++#define	RTY_LMT_EN			BIT(17)
++
++/* OFFSET 20 */
++#define SGI					BIT(6)
++#define USB_TXAGG_NUM_SHT	24
++
++typedef struct txdescriptor_8812 {
++	/* Offset 0 */
++	u32 pktlen:16;
++	u32 offset:8;
++	u32 bmc:1;
++	u32 htc:1;
++	u32 ls:1;
++	u32 fs:1;
++	u32 linip:1;
++	u32 noacm:1;
++	u32 gf:1;
++	u32 own:1;
++
++	/* Offset 4 */
++	u32 macid:6;
++	u32 rsvd0406:2;
++	u32 qsel:5;
++	u32 rd_nav_ext:1;
++	u32 lsig_txop_en:1;
++	u32 pifs:1;
++	u32 rate_id:4;
++	u32 navusehdr:1;
++	u32 en_desc_id:1;
++	u32 sectype:2;
++	u32 rsvd0424:2;
++	u32 pkt_offset:5;	/* unit: 8 bytes */
++	u32 rsvd0431:1;
++
++	/* Offset 8 */
++	u32 rts_rc:6;
++	u32 data_rc:6;
++	u32 agg_en:1;
++	u32 rd_en:1;
++	u32 bar_rty_th:2;
++	u32 bk:1;
++	u32 morefrag:1;
++	u32 raw:1;
++	u32 ccx:1;
++	u32 ampdu_density:3;
++	u32 bt_null:1;
++	u32 ant_sel_a:1;
++	u32 ant_sel_b:1;
++	u32 tx_ant_cck:2;
++	u32 tx_antl:2;
++	u32 tx_ant_ht:2;
++
++	/* Offset 12 */
++	u32 nextheadpage:8;
++	u32 tailpage:8;
++	u32 seq:12;
++	u32 cpu_handle:1;
++	u32 tag1:1;
++	u32 trigger_int:1;
++	u32 hwseq_en:1;
++
++	/* Offset 16 */
++	u32 rtsrate:5;
++	u32 ap_dcfe:1;
++	u32 hwseq_sel:2;
++	u32 userate:1;
++	u32 disrtsfb:1;
++	u32 disdatafb:1;
++	u32 cts2self:1;
++	u32 rtsen:1;
++	u32 hw_rts_en:1;
++	u32 port_id:1;
++	u32 pwr_status:3;
++	u32 wait_dcts:1;
++	u32 cts2ap_en:1;
++	u32 data_sc:2;
++	u32 data_stbc:2;
++	u32 data_short:1;
++	u32 data_bw:1;
++	u32 rts_short:1;
++	u32 rts_bw:1;
++	u32 rts_sc:2;
++	u32 vcs_stbc:2;
++
++	/* Offset 20 */
++	u32 datarate:6;
++	u32 sgi:1;
++	u32 try_rate:1;
++	u32 data_ratefb_lmt:5;
++	u32 rts_ratefb_lmt:4;
++	u32 rty_lmt_en:1;
++	u32 data_rt_lmt:6;
++	u32 usb_txagg_num:8;
++
++	/* Offset 24 */
++	u32 txagg_a:5;
++	u32 txagg_b:5;
++	u32 use_max_len:1;
++	u32 max_agg_num:5;
++	u32 mcsg1_max_len:4;
++	u32 mcsg2_max_len:4;
++	u32 mcsg3_max_len:4;
++	u32 mcs7_sgi_max_len:4;
++
++	/* Offset 28 */
++	u32 checksum:16;	/* TxBuffSize(PCIe)/CheckSum(USB) */
++	u32 mcsg4_max_len:4;
++	u32 mcsg5_max_len:4;
++	u32 mcsg6_max_len:4;
++	u32 mcs15_sgi_max_len:4;
++
++	/* Offset 32 */
++	u32 rsvd32;
++
++	/* Offset 36 */
++	u32 rsvd36;
++} TXDESC_8812, *PTXDESC_8812;
++
++
++/* Dword 0 */
++#define GET_TX_DESC_OWN_8812(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
++#define SET_TX_DESC_PKT_SIZE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
++#define SET_TX_DESC_OFFSET_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
++#define SET_TX_DESC_BMC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
++#define SET_TX_DESC_HTC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
++#define SET_TX_DESC_LAST_SEG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
++#define SET_TX_DESC_FIRST_SEG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
++#define SET_TX_DESC_LINIP_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
++#define SET_TX_DESC_NO_ACM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
++#define SET_TX_DESC_GF_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
++#define SET_TX_DESC_OWN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
++
++/* Dword 1 */
++#define SET_TX_DESC_MACID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
++#define SET_TX_DESC_QUEUE_SEL_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
++#define SET_TX_DESC_RDG_NAV_EXT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
++#define SET_TX_DESC_LSIG_TXOP_EN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
++#define SET_TX_DESC_PIFS_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
++#define SET_TX_DESC_RATE_ID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
++#define SET_TX_DESC_EN_DESC_ID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
++#define SET_TX_DESC_SEC_TYPE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
++#define SET_TX_DESC_PKT_OFFSET_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
++
++/* Dword 2 */
++#define SET_TX_DESC_PAID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
++#define SET_TX_DESC_CCA_RTS_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
++#define SET_TX_DESC_AGG_ENABLE_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
++#define SET_TX_DESC_RDG_ENABLE_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
++#define SET_TX_DESC_AGG_BREAK_8812(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
++#define SET_TX_DESC_MORE_FRAG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
++#define SET_TX_DESC_RAW_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
++#define SET_TX_DESC_SPE_RPT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
++#define SET_TX_DESC_AMPDU_DENSITY_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
++#define SET_TX_DESC_BT_INT_8812(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
++#define SET_TX_DESC_GID_8812(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
++
++/* Dword 3 */
++#define SET_TX_DESC_WHEADER_LEN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
++#define SET_TX_DESC_CHK_EN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
++#define SET_TX_DESC_EARLY_MODE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
++#define SET_TX_DESC_HWSEQ_SEL_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
++#define SET_TX_DESC_USE_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
++#define SET_TX_DESC_DISABLE_RTS_FB_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
++#define SET_TX_DESC_DISABLE_FB_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
++#define SET_TX_DESC_CTS2SELF_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
++#define SET_TX_DESC_RTS_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
++#define SET_TX_DESC_HW_RTS_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
++#define SET_TX_DESC_NAV_USE_HDR_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
++#define SET_TX_DESC_USE_MAX_LEN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
++#define SET_TX_DESC_MAX_AGG_NUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
++#define SET_TX_DESC_NDPA_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
++#define SET_TX_DESC_AMPDU_MAX_TIME_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
++
++/* Dword 4 */
++#define SET_TX_DESC_TX_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
++#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
++#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
++#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
++#define SET_TX_DESC_DATA_RETRY_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
++#define SET_TX_DESC_RTS_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
++
++/* Dword 5 */
++#define SET_TX_DESC_DATA_SC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
++#define SET_TX_DESC_DATA_SHORT_8812(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
++#define SET_TX_DESC_DATA_BW_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
++#define SET_TX_DESC_DATA_LDPC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
++#define SET_TX_DESC_DATA_STBC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
++#define SET_TX_DESC_CTROL_STBC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
++#define SET_TX_DESC_RTS_SHORT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
++#define SET_TX_DESC_RTS_SC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
++#define SET_TX_DESC_TX_ANT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value)
++
++/* Dword 6 */
++#define SET_TX_DESC_SW_DEFINE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
++#define SET_TX_DESC_ANTSEL_A_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
++#define SET_TX_DESC_ANTSEL_B_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
++#define SET_TX_DESC_ANTSEL_C_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
++#define SET_TX_DESC_ANTSEL_D_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
++#define SET_TX_DESC_MBSSID_8821(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
++
++/* Dword 7 */
++#define SET_TX_DESC_TX_BUFFER_SIZE_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++#define SET_TX_DESC_TX_DESC_CHECKSUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++#define SET_TX_DESC_USB_TXAGG_NUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
++#ifdef CONFIG_SDIO_HCI
++#define SET_TX_DESC_SDIO_TXSEQ_8812(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
++#endif
++
++/* Dword 8 */
++#define SET_TX_DESC_HWSEQ_EN_8812(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
++
++/* Dword 9 */
++#define SET_TX_DESC_SEQ_8812(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
++
++/* Dword 10 */
++#define SET_TX_DESC_TX_BUFFER_ADDRESS_8812(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
++#define GET_TX_DESC_TX_BUFFER_ADDRESS_8812(__pTxDesc)	LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
++
++/* Dword 11 */
++#define SET_TX_DESC_NEXT_DESC_ADDRESS_8812(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
++
++
++#define SET_EARLYMODE_PKTNUM_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
++#define SET_EARLYMODE_LEN0_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
++#define SET_EARLYMODE_LEN1_1_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
++#define SET_EARLYMODE_LEN1_2_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
++#define SET_EARLYMODE_LEN2_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,  __Value)
++#define SET_EARLYMODE_LEN3_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
++
++#ifdef CONFIG_TX_EARLY_MODE
++	#define USB_DUMMY_OFFSET		2
++#else
++	#define USB_DUMMY_OFFSET		1
++#endif
++#define USB_DUMMY_LENGTH		(USB_DUMMY_OFFSET * PACKET_OFFSET_SZ)
++
++
++void rtl8812a_cal_txdesc_chksum(u8 *ptxdesc);
++void rtl8812a_fill_fake_txdesc(PADAPTER	padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8	IsBTQosNull, u8 bDataFrame);
++void rtl8812a_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc);
++void rtl8812a_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
++void rtl8812a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
++void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
++void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
++
++#ifdef CONFIG_USB_HCI
++s32 rtl8812au_init_xmit_priv(PADAPTER padapter);
++void rtl8812au_free_xmit_priv(PADAPTER padapter);
++s32 rtl8812au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++s32 rtl8812au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++s32	 rtl8812au_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++s32 rtl8812au_xmit_buf_handler(PADAPTER padapter);
++void rtl8812au_xmit_tasklet(void *priv);
++s32 rtl8812au_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++s32 rtl8812ae_init_xmit_priv(PADAPTER padapter);
++void rtl8812ae_free_xmit_priv(PADAPTER padapter);
++struct xmit_buf *rtl8812ae_dequeue_xmitbuf(struct rtw_tx_ring *ring);
++void	rtl8812ae_xmitframe_resume(_adapter *padapter);
++s32 rtl8812ae_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++s32 rtl8812ae_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++s32	rtl8812ae_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++void rtl8812ae_xmit_tasklet(void *priv);
++
++#ifdef CONFIG_XMIT_THREAD_MODE
++s32 rtl8812ae_xmit_buf_handler(_adapter *padapter);
++#endif
++
++#endif
++
++#ifdef CONFIG_TX_EARLY_MODE
++void UpdateEarlyModeInfo8812(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++#endif
++
++void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, u8 *ptxdesc);
++
++u8	BWMapping_8812(PADAPTER Adapter, struct pkt_attrib *pattrib);
++
++u8	SCMapping_8812(PADAPTER Adapter, struct pkt_attrib	*pattrib);
++
++#endif /* __RTL8812_XMIT_H__ */
++
++#ifdef CONFIG_RTL8821A
++#include "rtl8821a_xmit.h"
++#endif /* CONFIG_RTL8821A */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_cmd.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_cmd.h
+new file mode 100755
+index 000000000..c546a03c1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_cmd.h
+@@ -0,0 +1,166 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8814A_CMD_H__
++#define __RTL8814A_CMD_H__
++#include "hal_com_h2c.h"
++
++/* _RSVDPAGE_LOC_CMD0 */
++#define SET_8814A_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8814A_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_8814A_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8814A_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8814A_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++/* _SETPWRMODE_PARM */
++#define SET_8814A_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8814A_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
++#define SET_8814A_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
++#define SET_8814A_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8814A_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_8814A_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
++#define SET_8814A_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++#define GET_8814A_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
++
++
++/* _WoWLAN PARAM_CMD5 */
++#define SET_8814A_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_8814A_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_8814A_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
++#define SET_8814A_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
++#define SET_8814A_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
++#define SET_8814A_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
++#define SET_8814A_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
++#define SET_8814A_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
++#define SET_8814A_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_8814A_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++
++
++/* WLANINFO_PARM */
++#define SET_8814A_H2CCMD_WLANINFO_PARM_OPMODE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8814A_H2CCMD_WLANINFO_PARM_CHANNEL(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_8814A_H2CCMD_WLANINFO_PARM_BW40MHZ(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++
++/* _REMOTE_WAKEUP_CMD7 */
++#define SET_8814A_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_8814A_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_8814A_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
++#define SET_8814A_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
++
++
++/* _AP_OFFLOAD_CMD8 */
++#define SET_8814A_H2CCMD_AP_OFFLOAD_ON(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8814A_H2CCMD_AP_OFFLOAD_HIDDEN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_8814A_H2CCMD_AP_OFFLOAD_DENYANY(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_8814A_H2CCMD_AP_OFFLOAD_WAKEUP_EVT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++
++/* _PWR_MOD_CMD20 */
++#define SET_88E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_88E_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
++#define SET_88E_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
++#define SET_88E_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
++#define SET_88E_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
++#define SET_88E_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
++
++/*	AP_REQ_TXREP_CMD 0x43	*/
++#define SET_8814A_H2CCMD_TXREP_PARM_STA1(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
++#define SET_8814A_H2CCMD_TXREP_PARM_STA2(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++#define SET_8814A_H2CCMD_TXREP_PARM_RTY(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value)
++
++/*		C2H_AP_REQ_TXRPT		*/
++#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_MACID1(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 0, 8)
++#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_TXOK1(_Header)			LE_BITS_TO_2BYTE((_Header + 1), 0, 16)
++#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_TXFAIL1(_Header)			LE_BITS_TO_2BYTE((_Header + 3), 0, 16)
++#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_INIRATE1(_Header)		LE_BITS_TO_1BYTE((_Header + 5), 0, 8)
++#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_MACID2(_Header)			LE_BITS_TO_1BYTE((_Header + 6), 0, 8)
++#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_TXOK2(_Header)			LE_BITS_TO_2BYTE((_Header + 7), 0, 16)
++#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_TXFAIL2(_Header)			LE_BITS_TO_2BYTE((_Header + 9), 0, 16)
++#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_INIRATE2(_Header)		LE_BITS_TO_1BYTE((_Header + 11), 0, 8)
++
++/*		C2H_SPC_STAT			*/
++#define	GET_8814A_C2H_SPC_STAT_IDX(_Header)						LE_BITS_TO_1BYTE((_Header + 0), 0, 8)
++	/*	Tip :TYPE_A data3 is msb and data0 is lsb	*/
++#define	GET_8814A_C2H_SPC_STAT_TYPEA_RETRY(_Header)				LE_BITS_TO_4BYTE((_Header + 1), 0, 32)
++#define	GET_8814A_C2H_SPC_STAT_TYPEB_PKT1(_Header)				LE_BITS_TO_2BYTE((_Header + 1), 0, 16)
++#define	GET_8814A_C2H_SPC_STAT_TYPEB_RETRY1(_Header)			LE_BITS_TO_2BYTE((_Header + 3), 0, 16)
++#define	GET_8814A_C2H_SPC_STAT_TYPEB_PKT2(_Header)				LE_BITS_TO_2BYTE((_Header + 5), 0, 16)
++#define	GET_8814A_C2H_SPC_STAT_TYPEB_RETRY2(_Header)			LE_BITS_TO_2BYTE((_Header + 7), 0, 16)
++
++/*BCNHWSEQ*/
++#define SET_8814A_H2CCMD_BCNHWSEQ_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 1, __Value)
++#define SET_8814A_H2CCMD_BCNHWSEQ_BCN_NUMBER(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd), 1, 3, __Value)
++#define SET_8814A_H2CCMD_BCNHWSEQ_HWSEQ(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd), 6, 1, __Value)
++#define SET_8814A_H2CCMD_BCNHWSEQ_EXHWSEQ(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd), 7, 1, __Value)
++#define SET_8814A_H2CCMD_BCNHWSEQ_PAGE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
++void rtl8814_fw_update_beacon_cmd(_adapter *padapter);
++
++/* TX Beamforming */
++#define GET_8814A_C2H_TXBF_ORIGINATE(_Header)			LE_BITS_TO_1BYTE(_Header, 0, 8)
++#define GET_8814A_C2H_TXBF_MACID(_Header)				LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
++
++
++
++/* / TX Feedback Content */
++#define	USEC_UNIT_FOR_8814A_C2H_TX_RPT_QUEUE_TIME			256
++
++#define	GET_8814A_C2H_TX_RPT_QUEUE_SELECT(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 0, 5)
++#define	GET_8814A_C2H_TX_RPT_PKT_BROCAST(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 5, 1)
++#define	GET_8814A_C2H_TX_RPT_LIFE_TIME_OVER(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
++#define	GET_8814A_C2H_TX_RPT_RETRY_OVER(_Header)				LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
++#define	GET_8814A_C2H_TX_RPT_MAC_ID(_Header)					LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
++#define	GET_8814A_C2H_TX_RPT_DATA_RETRY_CNT(_Header)		LE_BITS_TO_1BYTE((_Header + 2), 0, 6)
++#define	GET_8814A_C2H_TX_RPT_QUEUE_TIME(_Header)				LE_BITS_TO_2BYTE((_Header + 3), 0, 16)	/* In unit of 256 microseconds. */
++#define	GET_8814A_C2H_TX_RPT_FINAL_DATA_RATE(_Header)		LE_BITS_TO_1BYTE((_Header + 5), 0, 8)
++
++
++/* _P2P_PS_OFFLOAD */
++#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_ENABLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
++#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
++#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_CTWINDOW_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
++#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_NOA0_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
++#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_NOA1_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
++#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
++#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
++
++s32 FillH2CCmd_8814(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
++void rtl8814_set_wowlan_cmd(_adapter *padapter, u8 enable);
++void rtl8814_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
++void rtl8814_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode);
++u8 GetTxBufferRsvdPageNum8814(_adapter *padapter, bool wowlan);
++void rtl8814_req_txrpt_cmd(PADAPTER padapter, u8 macid);
++
++#ifdef CONFIG_TDLS
++	#ifdef CONFIG_TDLS_CH_SW
++		void rtl8814_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
++	#endif
++#endif
++void rtl8814a_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
++
++void
++Set_RA_LDPC_8814(
++	struct sta_info	*psta,
++	BOOLEAN			bLDPC
++);
++
++s32 c2h_handler_8814a(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
++
++#ifdef CONFIG_BT_COEXIST
++void rtl8814a_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
++#endif /* CONFIG_BT_COEXIST */
++#ifdef CONFIG_P2P_PS
++	void rtl8814_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
++#endif /* CONFIG_P2P */
++
++#endif/* __RTL8814A_CMD_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_dm.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_dm.h
+new file mode 100644
+index 000000000..9762c1b41
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_dm.h
+@@ -0,0 +1,23 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8814A_DM_H__
++#define __RTL8814A_DM_H__
++
++void rtl8814_init_dm_priv(PADAPTER Adapter);
++void rtl8814_deinit_dm_priv(PADAPTER Adapter);
++void rtl8814_InitHalDm(PADAPTER Adapter);
++void rtl8814_HalDmWatchDog(PADAPTER Adapter);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_hal.h
+new file mode 100755
+index 000000000..fb11eb716
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_hal.h
+@@ -0,0 +1,329 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8814A_HAL_H__
++#define __RTL8814A_HAL_H__
++
++/* #include "hal_com.h" */
++#include "hal_data.h"
++
++/* include HAL Related header after HAL Related compiling flags */
++#include "rtl8814a_spec.h"
++#include "rtl8814a_rf.h"
++#include "rtl8814a_dm.h"
++#include "rtl8814a_recv.h"
++#include "rtl8814a_xmit.h"
++#include "rtl8814a_cmd.h"
++#include "rtl8814a_led.h"
++#include "Hal8814PwrSeq.h"
++#include "Hal8814PhyReg.h"
++#include "Hal8814PhyCfg.h"
++#ifdef DBG_CONFIG_ERROR_DETECT
++	#include "rtl8814a_sreset.h"
++#endif /* DBG_CONFIG_ERROR_DETECT */
++
++enum {
++	VOLTAGE_V25						= 0x03,
++	LDOE25_SHIFT					= 28 ,
++};
++/* max. iram is 64k , max dmen is 32k. Total = 96k = 0x18000*/
++#define FW_SIZE							0x18000
++#define FW_START_ADDRESS   0x1000
++typedef struct _RT_FIRMWARE_8814 {
++	FIRMWARE_SOURCE	eFWSource;
++#ifdef CONFIG_EMBEDDED_FWIMG
++	u8			*szFwBuffer;
++#else
++	u8			szFwBuffer[FW_SIZE];
++#endif
++	u32			ulFwLength;
++} RT_FIRMWARE_8814, *PRT_FIRMWARE_8814;
++
++#define PAGE_SIZE_TX_8814	PAGE_SIZE_128
++/* BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_8814
++ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
++
++#define BCNQ_PAGE_NUM_8814		(MAX_BEACON_LEN / PAGE_SIZE_TX_8814 + 6) /*0x08*/
++
++#define Rtl8814A_NIC_PWR_ON_FLOW				rtl8814A_power_on_flow
++#define Rtl8814A_NIC_RF_OFF_FLOW				rtl8814A_radio_off_flow
++#define Rtl8814A_NIC_DISABLE_FLOW				rtl8814A_card_disable_flow
++#define Rtl8814A_NIC_ENABLE_FLOW				rtl8814A_card_enable_flow
++#define Rtl8814A_NIC_SUSPEND_FLOW				rtl8814A_suspend_flow
++#define Rtl8814A_NIC_RESUME_FLOW				rtl8814A_resume_flow
++#define Rtl8814A_NIC_PDN_FLOW					rtl8814A_hwpdn_flow
++#define Rtl8814A_NIC_LPS_ENTER_FLOW			rtl8814A_enter_lps_flow
++#define Rtl8814A_NIC_LPS_LEAVE_FLOW			rtl8814A_leave_lps_flow
++
++/* *****************************************************
++ *				New	Firmware Header(8-byte alinment required)
++ * *****************************************************
++ * --- LONG WORD 0 ---- */
++#define GET_FIRMWARE_HDR_SIGNATURE_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 0, 16)
++#define GET_FIRMWARE_HDR_CATEGORY_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */
++#define GET_FIRMWARE_HDR_FUNCTION_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
++#define GET_FIRMWARE_HDR_VERSION_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */
++#define GET_FIRMWARE_HDR_SUB_VER_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */
++#define GET_FIRMWARE_HDR_SUB_IDX_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8) /* FW Subversion Index */
++
++/* --- LONG WORD 1 ---- */
++#define GET_FIRMWARE_HDR_SVN_IDX_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 0, 32)/* The SVN entry index */
++#define GET_FIRMWARE_HDR_RSVD1_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+12, 0, 32)
++
++/* --- LONG WORD 2 ---- */
++#define GET_FIRMWARE_HDR_MONTH_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+16, 0, 8) /* Release time Month field */
++#define GET_FIRMWARE_HDR_DATE_3081(__FwHdr)				LE_BITS_TO_4BYTE(__FwHdr+16, 8, 8) /* Release time Date field */
++#define GET_FIRMWARE_HDR_HOUR_3081(__FwHdr)				LE_BITS_TO_4BYTE(__FwHdr+16, 16, 8)/* Release time Hour field */
++#define GET_FIRMWARE_HDR_MINUTE_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+16, 24, 8)/* Release time Minute field */
++#define GET_FIRMWARE_HDR_YEAR_3081(__FwHdr)				LE_BITS_TO_4BYTE(__FwHdr+20, 0, 16)/* Release time Year field */
++#define GET_FIRMWARE_HDR_FOUNDRY_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+20, 16, 8)/* Release time Foundry field */
++#define GET_FIRMWARE_HDR_RSVD2_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+20, 24, 8)
++
++/* --- LONG WORD 3 ---- */
++#define GET_FIRMWARE_HDR_MEM_UASGE_DL_FROM_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+24, 0, 1)
++#define GET_FIRMWARE_HDR_MEM_UASGE_BOOT_FROM_3081(__FwHdr)	LE_BITS_TO_4BYTE(__FwHdr+24, 1, 1)
++#define GET_FIRMWARE_HDR_MEM_UASGE_BOOT_LOADER_3081(__FwHdr)LE_BITS_TO_4BYTE(__FwHdr+24, 2, 1)
++#define GET_FIRMWARE_HDR_MEM_UASGE_IRAM_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+24, 3, 1)
++#define GET_FIRMWARE_HDR_MEM_UASGE_ERAM_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+24, 4, 1)
++#define GET_FIRMWARE_HDR_MEM_UASGE_RSVD4_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+24, 5, 3)
++#define GET_FIRMWARE_HDR_RSVD3_3081(__FwHdr)					LE_BITS_TO_4BYTE(__FwHdr+24, 8, 8)
++#define GET_FIRMWARE_HDR_BOOT_LOADER_SZ_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+24, 16, 16)
++#define GET_FIRMWARE_HDR_RSVD5_3081(__FwHdr)					LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32)
++
++/* --- LONG WORD 4 ---- */
++#define GET_FIRMWARE_HDR_TOTAL_DMEM_SZ_3081(__FwHdr)	LE_BITS_TO_4BYTE(__FwHdr+36, 0, 32)
++#define GET_FIRMWARE_HDR_FW_CFG_SZ_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+36, 0, 16)
++#define GET_FIRMWARE_HDR_FW_ATTR_SZ_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+36, 16, 16)
++
++/* --- LONG WORD 5 ---- */
++#define GET_FIRMWARE_HDR_IROM_3081(__FwHdr)				LE_BITS_TO_4BYTE(__FwHdr+40, 0, 32)
++#define GET_FIRMWARE_HDR_EROM_3081(__FwHdr)				LE_BITS_TO_4BYTE(__FwHdr+44, 0, 32)
++
++/* --- LONG WORD 6 ---- */
++#define GET_FIRMWARE_HDR_IRAM_SZ_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+48, 0, 32)
++#define GET_FIRMWARE_HDR_ERAM_SZ_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+52, 0, 32)
++
++/* --- LONG WORD 7 ---- */
++#define GET_FIRMWARE_HDR_RSVD6_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+56, 0, 32)
++#define GET_FIRMWARE_HDR_RSVD7_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+60, 0, 32)
++
++
++
++/*
++ * 2013/08/16 MH MOve from SDIO.h for common use.
++ *   */
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
++	#define TRX_SHARE_MODE_8814A				0	/* TRX Buffer Share Index */
++	#define BASIC_RXFF_SIZE_8814A				24576/* Basic RXFF Size is 24K = 24*1024 Unit: Byte */
++	#define TRX_SHARE_BUFF_UNIT_8814A			65536/* TRX Share Buffer unit Size 64K = 64*1024 Unit: Byte */
++	#define TRX_SHARE_BUFF_UNIT_PAGE_8814A	(TRX_SHARE_BUFF_UNIT_8814A/PAGE_SIZE_8814A)/* 512 Pages */
++
++	/* Origin: */
++	#define  HPQ_PGNUM_8814A					0x20	/* High Queue */
++	#define  LPQ_PGNUM_8814A					0x20	/* Low Queue */
++	#define  NPQ_PGNUM_8814A					0x20	/* Normal Queue */
++	#define  EPQ_PGNUM_8814A					0x20	/* Extra Queue */
++
++#else	/*  #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) */
++
++	#define  HPQ_PGNUM_8814A		20
++	#define  NPQ_PGNUM_8814A		20
++	#define  LPQ_PGNUM_8814A		20 /* 1972 */
++	#define  EPQ_PGNUM_8814A		20
++	#define  BCQ_PGNUM_8814A		32
++
++#endif /* #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) */
++
++#ifdef CONFIG_WOWLAN
++	#define WOWLAN_PAGE_NUM_8814	0x06
++#else
++	#define WOWLAN_PAGE_NUM_8814	0x00
++#endif
++
++#define PAGE_SIZE_8814A						128/* TXFF Page Size, Unit: Byte */
++#define MAX_RX_DMA_BUFFER_SIZE_8814A		0x5C00	/* BASIC_RXFF_SIZE_8814A + TRX_SHARE_MODE_8814A * TRX_SHARE_BUFF_UNIT_8814A */ /* Basic RXFF Size + ShareBuffer Size */
++#define TX_PAGE_BOUNDARY_8814A			TXPKT_PGNUM_8814A	/* Need to enlarge boundary, by KaiYuan */
++#define TX_PAGE_BOUNDARY_WOWLAN_8814A	TXPKT_PGNUM_8814A	/* TODO: 20130415 KaiYuan Check this value later */
++
++#ifdef CONFIG_FW_C2H_DEBUG
++	#define RX_DMA_RESERVED_SIZE_8814A	0x100	/* 256B, reserved for c2h debug message */
++#else
++	#define RX_DMA_RESERVED_SIZE_8814A	0x0	/* 0B */
++#endif
++#define RX_DMA_BOUNDARY_8814A		(MAX_RX_DMA_BUFFER_SIZE_8814A - RX_DMA_RESERVED_SIZE_8814A - 1)
++
++#define  TOTAL_PGNUM_8814A		2048
++#define  TXPKT_PGNUM_8814A		(2048 - BCNQ_PAGE_NUM_8814-WOWLAN_PAGE_NUM_8814)
++#define  PUB_PGNUM_8814A		(TXPKT_PGNUM_8814A-HPQ_PGNUM_8814A-NPQ_PGNUM_8814A-LPQ_PGNUM_8814A-EPQ_PGNUM_8814A)
++
++/* Note: For WMM Normal Chip Setting ,modify later */
++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8814A	TX_PAGE_BOUNDARY_8814A
++#define WMM_NORMAL_TX_PAGE_BOUNDARY_8814A		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8814A + 1)
++
++#define DRIVER_EARLY_INT_TIME_8814		0x05
++#define BCN_DMA_ATIME_INT_TIME_8814		0x02
++
++
++#define MAX_PAGE_SIZE			4096	/* @ page : 4k bytes */
++
++#define EFUSE_MAX_SECTION_JAGUAR				64
++
++#define	HWSET_MAX_SIZE_8814A			512
++
++#define	EFUSE_REAL_CONTENT_LEN_8814A	1024
++#define	EFUSE_MAX_BANK_8814A		2
++
++#define	EFUSE_MAP_LEN_8814A			512
++#define	EFUSE_MAX_SECTION_8814A		64
++#define	EFUSE_MAX_WORD_UNIT_8814A		4
++#define	EFUSE_PROTECT_BYTES_BANK_8814A		16
++
++#define	EFUSE_IC_ID_OFFSET_8814A		506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
++#define AVAILABLE_EFUSE_ADDR_8814A(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8814A)
++
++/*-------------------------------------------------------------------------
++Chip specific
++-------------------------------------------------------------------------*/
++
++/* pic buffer descriptor */
++#if 1 /* according to the define in the rtw_xmit.h, rtw_recv.h */
++	#define RTL8814AE_SEG_NUM  TX_BUFFER_SEG_NUM /* 0:2 seg, 1: 4 seg, 2: 8 seg */
++	#define TX_DESC_NUM_8814A  TX_BD_NUM   /* 128 */
++	#define RX_DESC_NUM_8814A  PCI_MAX_RX_COUNT /* 128 */
++	#ifdef CONFIG_CONCURRENT_MODE
++		#define BE_QUEUE_TX_DESC_NUM_8814A  (TX_BD_NUM<<1)    /* 256 */
++	#else
++		#define BE_QUEUE_TX_DESC_NUM_8814A  (TX_BD_NUM+(TX_BD_NUM>>1)) /* 192 */
++	#endif
++#else
++	#define RTL8814AE_SEG_NUM  TX_BUFFER_SEG_NUM /* 0:2 seg, 1: 4 seg, 2: 8 seg */
++	#define TX_DESC_NUM_8814A  128 /* 1024//2048 change by ylb 20130624 */
++	#define RX_DESC_NUM_8814A  128 /* 1024 //512 change by ylb 20130624 */
++#endif
++
++/* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
++ * 9bytes + 1byt + 5bytes and pre 1byte.
++ * For worst case:
++ * | 1byte|----8bytes----|1byte|--5bytes--|
++ * |         |            Reserved(14bytes)	      |
++ *   */
++#define	EFUSE_OOB_PROTECT_BYTES		15	/* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
++
++#ifdef CONFIG_FILE_FWIMG
++extern char *rtw_fw_file_path;
++#ifdef CONFIG_WOWLAN
++extern char *rtw_fw_wow_file_path;
++#endif
++#ifdef CONFIG_MP_INCLUDED
++extern char *rtw_fw_mp_bt_file_path;
++#endif /* CONFIG_MP_INCLUDED */
++#endif /* CONFIG_FILE_FWIMG */
++
++/* rtl8814_hal_init.c */
++s32 FirmwareDownload8814A(PADAPTER	Adapter, BOOLEAN bUsedWoWLANFw);
++void	InitializeFirmwareVars8814(PADAPTER padapter);
++
++void
++Hal_InitEfuseVars_8814A(
++		PADAPTER	Adapter
++);
++
++s32 InitLLTTable8814A(
++		PADAPTER	Adapter
++);
++
++
++void InitRDGSetting8814A(PADAPTER padapter);
++
++/* void CheckAutoloadState8812A(PADAPTER padapter); */
++
++/* EFuse */
++u8	GetEEPROMSize8814A(PADAPTER padapter);
++void hal_InitPGData_8814A(
++		PADAPTER padapter,
++		u8 *PROMContent
++);
++
++void	hal_ReadPROMVersion8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void	hal_ReadTxPowerInfo8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
++void	hal_ReadBoardType8814A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void	hal_ReadThermalMeter_8814A(PADAPTER	Adapter, u8 *PROMContent, BOOLEAN	AutoloadFail);
++void	hal_ReadChannelPlan8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void	hal_EfuseParseXtal_8814A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++void	hal_ReadAntennaDiversity8814A(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
++void	hal_Read_TRX_antenna_8814A(PADAPTER	Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
++void hal_ReadAmplifierType_8814A(
++		PADAPTER		Adapter
++);
++void hal_ReadPAType_8814A(
++		PADAPTER	Adapter,
++		u8			*PROMContent,
++		BOOLEAN		AutoloadFail,
++		u8		*pPAType,
++		u8		*pLNAType
++);
++
++void hal_GetRxGainOffset_8814A(
++	PADAPTER	Adapter,
++	u8 			*PROMContent,
++	BOOLEAN		AutoloadFail
++);
++void Hal_EfuseParseKFreeData_8814A(
++			PADAPTER		Adapter,
++			u8				*PROMContent,
++			BOOLEAN			AutoloadFail);
++void	hal_ReadRFEType_8814A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
++void	hal_EfuseParseBTCoexistInfo8814A(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++
++/* void	hal_ReadUsbType_8812AU(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
++ * int	FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); */
++void	hal_ReadRemoteWakeup_8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
++u8	MgntQuery_NssTxRate(u16 Rate);
++
++/* BOOLEAN HalDetectPwrDownMode8812(PADAPTER Adapter); */
++
++#ifdef CONFIG_WOWLAN
++	void Hal_DetectWoWMode(PADAPTER pAdapter);
++#endif /* CONFIG_WOWLAN */
++
++void _InitBeaconParameters_8814A(PADAPTER padapter);
++void SetBeaconRelatedRegisters8814A(PADAPTER padapter);
++
++void ReadRFType8814A(PADAPTER padapter);
++void InitDefaultValue8814A(PADAPTER padapter);
++
++u8 SetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval);
++void GetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval);
++u8 SetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
++u8 GetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
++void rtl8814_set_hal_ops(struct hal_ops *pHalFunc);
++void init_hal_spec_8814a(_adapter *adapter);
++
++void rtl8814_start_thread(PADAPTER padapter);
++void rtl8814_stop_thread(PADAPTER padapter);
++
++
++#ifdef CONFIG_PCI_HCI
++	BOOLEAN	InterruptRecognized8814AE(PADAPTER Adapter);
++	void	UpdateInterruptMask8814AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
++	void	InitMAC_TRXBD_8814AE(PADAPTER Adapter);
++	void rtl8814ae_reset_desc_ring(_adapter *padapter);
++	u16	get_txbd_rw_reg(u16 ff_hwaddr);
++#endif
++
++#ifdef CONFIG_BT_COEXIST
++	void rtl8814a_combo_card_WifiOnlyHwInit(PADAPTER Adapter);
++#endif
++
++#endif /* __RTL8188E_HAL_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_led.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_led.h
+new file mode 100644
+index 000000000..cc457921e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_led.h
+@@ -0,0 +1,36 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8814A_LED_H__
++#define __RTL8814A_LED_H__
++
++#ifdef CONFIG_RTW_SW_LED
++/* ********************************************************************************
++ * Interface to manipulate LED objects.
++ * ******************************************************************************** */
++#ifdef CONFIG_USB_HCI
++	void rtl8814au_InitSwLeds(PADAPTER padapter);
++	void rtl8814au_DeInitSwLeds(PADAPTER padapter);
++#endif /* CONFIG_USB_HCI */
++#ifdef CONFIG_PCI_HCI
++	void rtl8814ae_InitSwLeds(PADAPTER padapter);
++	void rtl8814ae_DeInitSwLeds(PADAPTER padapter);
++#endif /* CONFIG_PCI_HCI */
++#ifdef CONFIG_SDIO_HCI
++	void rtl8814s_InitSwLeds(PADAPTER padapter);
++	void rtl8814s_DeInitSwLeds(PADAPTER padapter);
++#endif /* CONFIG_SDIO_HCI */
++
++#endif /* __RTL8814A_LED_H__ */
++#endif /*CONFIG_RTW_SW_LED*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_recv.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_recv.h
+new file mode 100755
+index 000000000..68da63331
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_recv.h
+@@ -0,0 +1,182 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8814A_RECV_H__
++#define __RTL8814A_RECV_H__
++
++#if defined(CONFIG_USB_HCI)
++
++	#ifndef MAX_RECVBUF_SZ
++		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
++			#ifdef CONFIG_PLATFORM_MSTAR
++				#define MAX_RECVBUF_SZ (8192) /* 8K */
++			#else
++				#define MAX_RECVBUF_SZ (32768) /* 32k */
++			#endif
++			/* #define MAX_RECVBUF_SZ (24576) */ /* 24k */
++			/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
++			/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
++			/* #define MAX_RECVBUF_SZ (15360) */ /* 15k < 16k */
++			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
++		#else
++			#define MAX_RECVBUF_SZ (4000) /* about 4K */
++		#endif
++	#endif /* !MAX_RECVBUF_SZ */
++
++#elif defined(CONFIG_PCI_HCI)
++	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
++	/*	#define MAX_RECVBUF_SZ (9100) */
++	/* #else */
++	#define MAX_RECVBUF_SZ (4000) /* about 4K
++	* #endif */
++
++
++#elif defined(CONFIG_SDIO_HCI)
++	#if 0
++		/* temp solution */
++		#ifdef CONFIG_SDIO_RX_COPY
++			#define MAX_RECVBUF_SZ (10240)
++		#else /*  !CONFIG_SDIO_RX_COPY */
++			#define MAX_RECVBUF_SZ	MAX_RX_DMA_BUFFER_SIZE_8821
++		#endif /*  !CONFIG_SDIO_RX_COPY */
++	#endif
++#endif
++
++
++/* RX buffer descriptor */
++/* DWORD 0 */
++#define SET_RX_BUFFER_DESC_DATA_LENGTH_8814A(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
++#define SET_RX_BUFFER_DESC_LS_8814A(__pRxStatusDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 14, 1, __Value)
++#define SET_RX_BUFFER_DESC_FS_8814A(__pRxStatusDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
++#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8814A(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 16, __Value)
++
++#define GET_RX_BUFFER_DESC_OWN_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
++#define GET_RX_BUFFER_DESC_LS_8814A(__pRxStatusDesc)							LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
++#define GET_RX_BUFFER_DESC_FS_8814A(__pRxStatusDesc)							LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
++#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
++
++/* DWORD 1 */
++#define SET_RX_BUFFER_PHYSICAL_LOW_8814A(__pRxStatusDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
++#define GET_RX_BUFFER_PHYSICAL_LOW_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 32)
++
++/* DWORD 2 */
++#define SET_RX_BUFFER_PHYSICAL_HIGH_8814A(__pRxStatusDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
++
++/* DWORD 3*/ /* RESERVED */
++
++
++#if 0
++	/* =============
++	* RX Info
++	* ============== */
++#endif
++/* DWORD 0 */
++#define SET_RX_STATUS_DESC_PKT_LEN_8814A(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
++#define SET_RX_STATUS_DESC_EOR_8814A(__pRxStatusDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
++#define SET_RX_STATUS_DESC_OWN_8814AE(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
++
++#define GET_RX_STATUS_DESC_PKT_LEN_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
++#define GET_RX_STATUS_DESC_CRC32_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
++#define GET_RX_STATUS_DESC_ICV_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
++#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
++#define GET_RX_STATUS_DESC_SECURITY_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
++#define GET_RX_STATUS_DESC_QOS_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
++#define GET_RX_STATUS_DESC_SHIFT_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
++#define GET_RX_STATUS_DESC_PHY_STATUS_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
++#define GET_RX_STATUS_DESC_SWDEC_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
++#define GET_RX_STATUS_DESC_LAST_SEG_8814AE(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
++#define GET_RX_STATUS_DESC_EOR_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
++
++/* DWORD 1 */
++#define GET_RX_STATUS_DESC_MACID_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 7)
++#define GET_RX_STATUS_DESC_EXT_SECTYPE_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 7, 1)/* 20130415 KaiYuan add for 8814 */
++#define GET_RX_STATUS_DESC_TID_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 8, 4)
++#define GET_RX_STATUS_DESC_MACID_VLD_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 12, 1)
++#define GET_RX_STATUS_DESC_AMSDU_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 13, 1)
++#define GET_RX_STATUS_DESC_RXID_MATCH_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 14, 1)
++#define GET_RX_STATUS_DESC_PAGGR_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 15, 1)
++#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHKERR_8814A(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 20, 1)
++#define GET_RX_STATUS_DESC_TCPOFFLOAD_IPVER_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 21, 1)
++#define GET_RX_STATUS_DESC_TCPOFFLOAD_IS_TCPUDP_8814A(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 22, 1)
++#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHK_VLD_8814A(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 23, 1)
++#define GET_RX_STATUS_DESC_PAM_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 24, 1)
++#define GET_RX_STATUS_DESC_PWR_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 25, 1)
++#define GET_RX_STATUS_DESC_MORE_DATA_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 26, 1)
++#define GET_RX_STATUS_DESC_MORE_FRAG_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 27, 1)
++#define GET_RX_STATUS_DESC_TYPE_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 28, 2)
++#define GET_RX_STATUS_DESC_FIRST_SEG_8814AE(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
++#define GET_RX_STATUS_DESC_EOR_8814AE(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
++#define GET_RX_STATUS_DESC_MC_8814A(__pRxStatusDesc)							LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 30, 1)
++#define GET_RX_STATUS_DESC_BC_8814A(__pRxStatusDesc)							LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 31, 1)
++
++/* DWORD 2 */
++#define GET_RX_STATUS_DESC_SEQ_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
++#define GET_RX_STATUS_DESC_FRAG_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
++#ifdef CONFIG_USB_RX_AGGREGATION
++	#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 8)
++#else
++	#define GET_RX_STATUS_DESC_RX_IS_QOS_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
++#endif
++#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
++#define GET_RX_STATUS_DESC_HWRSVD_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 24, 4)
++#define GET_RX_STATUS_C2H_8814A(__pRxStatusDesc)								LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
++#define GET_RX_STATUS_DESC_FCS_OK_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
++
++/* DWORD 3 */
++#define GET_RX_STATUS_DESC_RX_RATE_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
++#define GET_RX_STATUS_DESC_BSSID_FIT_H_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 7, 3)/* 20130415 KaiYuan add for 8814 */
++#define GET_RX_STATUS_DESC_HTC_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
++#define GET_RX_STATUS_DESC_EOSP_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
++#define GET_RX_STATUS_DESC_BSSID_FIT_L_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
++#define GET_RX_STATUS_DESC_DMA_AGG_NUM_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)/* 20130415 KaiYuan Check if it exist anymore */
++#define GET_RX_STATUS_DESC_PATTERN_MATCH_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 29, 1)
++#define GET_RX_STATUS_DESC_UNICAST_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 30, 1)
++#define GET_RX_STATUS_DESC_MAGIC_WAKE_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 31, 1)
++
++/* DWORD 4 */
++#define GET_RX_STATUS_DESC_PATTERN_IDX_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 0, 8)
++#define GET_RX_STATUS_DESC_RX_EOF_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 8, 1)
++#define GET_RX_STATUS_DESC_RX_SCRAMBLER_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 9, 7)
++#define GET_RX_STATUS_DESC_RX_PRE_NDP_VLD_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 16, 1)
++#define GET_RX_STATUS_DESC_A1_FIT_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 24, 5)
++
++
++/* DWORD 5 */
++#define GET_RX_STATUS_DESC_TSFL_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
++
++
++/* Rx smooth factor */
++#define Rx_Smooth_Factor (20)
++
++#ifdef CONFIG_USB_HCI
++	s32 rtl8814au_init_recv_priv(PADAPTER padapter);
++	void rtl8814au_free_recv_priv(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	s32 rtl8814ae_init_recv_priv(PADAPTER padapter);
++	void rtl8814ae_free_recv_priv(PADAPTER padapter);
++#endif
++
++#if 0
++	/* temp solution */
++	#ifdef CONFIG_SDIO_HCI
++		s32 InitRecvPriv8821AS(PADAPTER padapter);
++		void FreeRecvPriv8821AS(PADAPTER padapter);
++	#endif /*  CONFIG_SDIO_HCI */
++#endif
++
++void rtl8814_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
++
++#endif /* __RTL8814A_RECV_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_rf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_rf.h
+new file mode 100644
+index 000000000..9bb099c92
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_rf.h
+@@ -0,0 +1,28 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8814A_RF_H__
++#define __RTL8814A_RF_H__
++
++void
++PHY_RF6052SetBandwidth8814A(
++		PADAPTER				Adapter,
++		enum channel_width		Bandwidth);
++
++
++int
++PHY_RF6052_Config_8814A(
++		PADAPTER	Adapter);
++
++#endif/* __RTL8188E_RF_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_spec.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_spec.h
+new file mode 100755
+index 000000000..0e8763f0a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_spec.h
+@@ -0,0 +1,654 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8814A_SPEC_H__
++#define __RTL8814A_SPEC_H__
++
++#include <drv_conf.h>
++
++
++/* ************************************************************
++ *
++ * ************************************************************ */
++
++/* -----------------------------------------------------
++ *
++ *	0x0000h ~ 0x00FFh	System Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_SYS_ISO_CTRL_8814A			0x0000	/* 2 Byte */
++#define REG_SYS_FUNC_EN_8814A			0x0002	/* 2 Byte */
++#define REG_SYS_PW_CTRL_8814A			0x0004	/* 4 Byte        */
++#define REG_SYS_CLKR_8814A				0x0008	/* 2 Byte */
++#define REG_SYS_EEPROM_CTRL_8814A		0x000A	/* 2 Byte        */
++#define REG_EE_VPD_8814A				0x000C	/* 2 Byte */
++#define REG_SYS_SWR_CTRL1_8814A			0x0010	/* 1 Byte */
++#define REG_SPS0_CTRL_8814A				0x0011	/* 7 Byte */
++#define REG_SYS_SWR_CTRL3_8814A			0x0018	/* 4 Byte */
++#define REG_RSV_CTRL_8814A				0x001C	/* 3 Byte */
++#define REG_RF_CTRL0_8814A				0x001F	/* 1 Byte */
++#define REG_RF_CTRL1_8814A				0x0020	/* 1 Byte */
++#define REG_RF_CTRL2_8814A				0x0021	/* 1 Byte */
++#define REG_LPLDO_CTRL_8814A			0x0023	/* 1 Byte */
++#define REG_AFE_CTRL1_8814A				0x0024	/* 4 Byte        */
++#define REG_AFE_CTRL2_8814A				0x0028	/* 4 Byte        */
++#define REG_AFE_CTRL3_8814A				0x002c	/* 4 Byte  */
++#define REG_EFUSE_CTRL_8814A			0x0030
++#define REG_LDO_EFUSE_CTRL_8814A		0x0034
++#define REG_PWR_DATA_8814A				0x0038
++#define REG_CAL_TIMER_8814A				0x003C
++#define REG_ACLK_MON_8814A				0x003E
++#define REG_GPIO_MUXCFG_8814A			0x0040
++#define REG_GPIO_IO_SEL_8814A			0x0042
++#define REG_MAC_PINMUX_CFG_8814A		0x0043
++#define REG_GPIO_PIN_CTRL_8814A			0x0044
++#define REG_GPIO_INTM_8814A				0x0048
++#define REG_LEDCFG0_8814A				0x004C
++#define REG_LEDCFG1_8814A				0x004D
++#define REG_LEDCFG2_8814A				0x004E
++#define REG_LEDCFG3_8814A				0x004F
++#define REG_FSIMR_8814A					0x0050
++#define REG_FSISR_8814A					0x0054
++#define REG_HSIMR_8814A					0x0058
++#define REG_HSISR_8814A					0x005c
++#define REG_GPIO_EXT_CTRL_8814A			0x0060
++#define REG_GPIO_STATUS_8814A			0x006C
++#define REG_SDIO_CTRL_8814A				0x0070
++#define REG_HCI_OPT_CTRL_8814A			0x0074
++#define REG_RF_CTRL3_8814A				0x0076	/* 1 Byte */
++#define REG_AFE_CTRL4_8814A				0x0078
++#define REG_8051FW_CTRL_8814A			0x0080
++#define REG_HIMR0_8814A					0x00B0
++#define REG_HISR0_8814A					0x00B4
++#define REG_HIMR1_8814A					0x00B8
++#define REG_HISR1_8814A					0x00BC
++#define REG_SYS_CFG1_8814A				0x00F0
++#define REG_SYS_CFG2_8814A				0x00FC
++#define REG_SYS_CFG3_8814A				0x1000
++
++/* -----------------------------------------------------
++ *
++ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_CR_8814A						0x0100
++#define REG_PBP_8814A					0x0104
++#define REG_PKT_BUFF_ACCESS_CTRL_8814A	0x0106
++#define REG_TRXDMA_CTRL_8814A			0x010C
++#define REG_TRXFF_BNDY_8814A			0x0114
++#define REG_TRXFF_STATUS_8814A			0x0118
++#define REG_RXFF_PTR_8814A				0x011C
++#define REG_CPWM_8814A					0x012F
++#define REG_FWIMR_8814A					0x0130
++#define REG_FWISR_8814A					0x0134
++#define REG_FTIMR_8814A					0x0138
++#define REG_PKTBUF_DBG_CTRL_8814A		0x0140
++#define REG_RXPKTBUF_CTRL_8814A		0x0142
++#define REG_PKTBUF_DBG_DATA_L_8814A	0x0144
++#define REG_PKTBUF_DBG_DATA_H_8814A	0x0148
++
++#define REG_WOWLAN_WAKE_REASON			REG_MCUTST_WOWLAN
++
++#define REG_TC0_CTRL_8814A				0x0150
++#define REG_TC1_CTRL_8814A				0x0154
++#define REG_TC2_CTRL_8814A				0x0158
++#define REG_TC3_CTRL_8814A				0x015C
++#define REG_TC4_CTRL_8814A				0x0160
++#define REG_TCUNIT_BASE_8814A			0x0164
++#define REG_RSVD3_8814A					0x0168
++#define REG_C2HEVT_MSG_NORMAL_8814A	0x01A0
++#define REG_C2HEVT_CLEAR_8814A			0x01AF
++#define REG_MCUTST_1_8814A				0x01C0
++#define REG_MCUTST_WOWLAN_8814A		0x01C7
++#define REG_FMETHR_8814A				0x01C8
++#define REG_HMETFR_8814A				0x01CC
++#define REG_HMEBOX_0_8814A				0x01D0
++#define REG_HMEBOX_1_8814A				0x01D4
++#define REG_HMEBOX_2_8814A				0x01D8
++#define REG_HMEBOX_3_8814A				0x01DC
++#define REG_LLT_INIT_8814A				0x01E0
++#define REG_LLT_ADDR_8814A				0x01E4 /* 20130415 KaiYuan add for 8814 */
++#define REG_HMEBOX_EXT0_8814A			0x01F0
++#define REG_HMEBOX_EXT1_8814A			0x01F4
++#define REG_HMEBOX_EXT2_8814A			0x01F8
++#define REG_HMEBOX_EXT3_8814A			0x01FC
++
++/* -----------------------------------------------------
++ *
++ *	0x0200h ~ 0x027Fh	TXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_FIFOPAGE_CTRL_1_8814A			0x0200
++#define REG_FIFOPAGE_CTRL_2_8814A		0x0204
++#define REG_AUTO_LLT_8814A					0x0208
++#define REG_TXDMA_OFFSET_CHK_8814A	0x020C
++#define REG_TXDMA_STATUS_8814A			0x0210
++#define REG_RQPN_NPQ_8814A				0x0214
++#define REG_TQPNT1_8814A					0x0218
++#define REG_TQPNT2_8814A					0x021C
++#define REG_TQPNT3_8814A					0x0220
++#define REG_TQPNT4_8814A					0x0224
++#define REG_RQPN_CTRL_1_8814A				0x0228
++#define REG_RQPN_CTRL_2_8814A				0x022C
++#define REG_FIFOPAGE_INFO_1_8814A			0x0230
++#define REG_FIFOPAGE_INFO_2_8814A			0x0234
++#define REG_FIFOPAGE_INFO_3_8814A			0x0238
++#define REG_FIFOPAGE_INFO_4_8814A			0x023C
++#define REG_FIFOPAGE_INFO_5_8814A			0x0240
++
++
++/* -----------------------------------------------------
++ *
++ *	0x0280h ~ 0x02FFh	RXDMA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_RXDMA_AGG_PG_TH_8814A		0x0280
++#define REG_RXPKT_NUM_8814A				0x0284 /* The number of packets in RXPKTBUF. */
++#define REG_RXDMA_CONTROL_8814A			0x0286 /* ?????? Control the RX DMA. */
++#define REG_RXDMA_STATUS_8814A			0x0288
++#define REG_RXDMA_MODE_8814A				0x0290 /* ?????? */
++#define REG_EARLY_MODE_CONTROL_8814A	0x02BC /* ?????? */
++#define REG_RSVD5_8814A					0x02F0 /* ?????? */
++
++
++/* -----------------------------------------------------
++ *
++ *	0x0300h ~ 0x03FFh	PCIe
++ *
++ * ----------------------------------------------------- */
++#define	REG_PCIE_CTRL_REG_8814A			0x0300
++#define	REG_INT_MIG_8814A				0x0304	/* Interrupt Migration */
++#define	REG_BCNQ_TXBD_DESA_8814A		0x0308	/* TX Beacon Descriptor Address */
++#define	REG_MGQ_TXBD_DESA_8814A			0x0310	/* TX Manage Queue Descriptor Address */
++#define	REG_VOQ_TXBD_DESA_8814A			0x0318	/* TX VO Queue Descriptor Address */
++#define	REG_VIQ_TXBD_DESA_8814A			0x0320	/* TX VI Queue Descriptor Address */
++#define	REG_BEQ_TXBD_DESA_8814A			0x0328	/* TX BE Queue Descriptor Address */
++#define	REG_BKQ_TXBD_DESA_8814A			0x0330	/* TX BK Queue Descriptor Address */
++#define	REG_RXQ_RXBD_DESA_8814A			0x0338	/* RX Queue	Descriptor Address */
++#define REG_HI0Q_TXBD_DESA_8814A		0x0340
++#define REG_HI1Q_TXBD_DESA_8814A		0x0348
++#define REG_HI2Q_TXBD_DESA_8814A		0x0350
++#define REG_HI3Q_TXBD_DESA_8814A		0x0358
++#define REG_HI4Q_TXBD_DESA_8814A		0x0360
++#define REG_HI5Q_TXBD_DESA_8814A		0x0368
++#define REG_HI6Q_TXBD_DESA_8814A		0x0370
++#define REG_HI7Q_TXBD_DESA_8814A		0x0378
++#define	REG_MGQ_TXBD_NUM_8814A			0x0380
++#define	REG_RX_RXBD_NUM_8814A			0x0382
++#define	REG_VOQ_TXBD_NUM_8814A			0x0384
++#define	REG_VIQ_TXBD_NUM_8814A			0x0386
++#define	REG_BEQ_TXBD_NUM_8814A			0x0388
++#define	REG_BKQ_TXBD_NUM_8814A			0x038A
++#define	REG_HI0Q_TXBD_NUM_8814A			0x038C
++#define	REG_HI1Q_TXBD_NUM_8814A			0x038E
++#define	REG_HI2Q_TXBD_NUM_8814A			0x0390
++#define	REG_HI3Q_TXBD_NUM_8814A			0x0392
++#define	REG_HI4Q_TXBD_NUM_8814A			0x0394
++#define	REG_HI5Q_TXBD_NUM_8814A			0x0396
++#define	REG_HI6Q_TXBD_NUM_8814A			0x0398
++#define	REG_HI7Q_TXBD_NUM_8814A			0x039A
++#define	REG_TSFTIMER_HCI_8814A			0x039C
++
++/* Read Write Point */
++#define	REG_VOQ_TXBD_IDX_8814A			0x03A0
++#define	REG_VIQ_TXBD_IDX_8814A			0x03A4
++#define	REG_BEQ_TXBD_IDX_8814A			0x03A8
++#define	REG_BKQ_TXBD_IDX_8814A			0x03AC
++#define	REG_MGQ_TXBD_IDX_8814A			0x03B0
++#define	REG_RXQ_TXBD_IDX_8814A			0x03B4
++#define	REG_HI0Q_TXBD_IDX_8814A			0x03B8
++#define	REG_HI1Q_TXBD_IDX_8814A			0x03BC
++#define	REG_HI2Q_TXBD_IDX_8814A			0x03C0
++#define	REG_HI3Q_TXBD_IDX_8814A			0x03C4
++#define	REG_HI4Q_TXBD_IDX_8814A			0x03C8
++#define	REG_HI5Q_TXBD_IDX_8814A			0x03CC
++#define	REG_HI6Q_TXBD_IDX_8814A			0x03D0
++#define	REG_HI7Q_TXBD_IDX_8814A			0x03D4
++#define REG_DBG_SEL_V1_8814A				0x03D8
++#define REG_PCIE_HRPWM1_V1_8814A			0x03D9
++#define REG_PCIE_HCPWM1_V1_8814A			0x03DA
++#define REG_PCIE_CTRL2_8814A				0x03DB
++#define REG_PCIE_HRPWM2_V1_8814A			0x03DC
++#define REG_PCIE_HCPWM2_V1_8814A			0x03DE
++#define REG_PCIE_H2C_MSG_V1_8814A		0x03E0
++#define REG_PCIE_C2H_MSG_V1_8814A		0x03E4
++#define REG_DBI_WDATA_V1_8814A			0x03E8
++#define REG_DBI_RDATA_V1_8814A			0x03EC
++#define REG_DBI_FLAG_V1_8814A				0x03F0
++#define REG_MDIO_V1_8814A					0x03F4
++#define REG_PCIE_MIX_CFG_8814A			0x03F8
++#define REG_DBG_8814A						0x03FC
++/* -----------------------------------------------------
++ *
++ *	0x0400h ~ 0x047Fh	Protocol Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_VOQ_INFORMATION_8814A		0x0400
++#define REG_VIQ_INFORMATION_8814A		0x0404
++#define REG_BEQ_INFORMATION_8814A		0x0408
++#define REG_BKQ_INFORMATION_8814A		0x040C
++#define REG_MGQ_INFORMATION_8814A		0x0410
++#define REG_HGQ_INFORMATION_8814A		0x0414
++#define REG_BCNQ_INFORMATION_8814A	0x0418
++#define REG_TXPKT_EMPTY_8814A			0x041A
++#define REG_CPU_MGQ_INFORMATION_8814A	0x041C
++#define REG_FWHW_TXQ_CTRL_8814A		0x0420
++#define REG_HWSEQ_CTRL_8814A			0x0423
++#define REG_TXPKTBUF_BCNQ_BDNY_8814A	0x0424
++/* #define REG_MGQ_BDNY_8814A				0x0425 */
++#define REG_LIFETIME_EN_8814A				0x0426
++/* #define REG_FW_FREE_TAIL_8814A			0x0427 */
++#define REG_SPEC_SIFS_8814A				0x0428
++#define REG_RETRY_LIMIT_8814A				0x042A
++#define REG_TXBF_CTRL_8814A				0x042C
++#define REG_DARFRC_8814A				0x0430
++#define REG_RARFRC_8814A				0x0438
++#define REG_RRSR_8814A					0x0440
++#define REG_ARFR0_8814A					0x0444
++#define REG_ARFR1_8814A					0x044C
++#define REG_CCK_CHECK_8814A				0x0454
++#define REG_AMPDU_MAX_TIME_8814A			0x0455
++#define REG_TXPKTBUF_BCNQ1_BDNY_8814A	0x0456
++#define REG_AMPDU_MAX_LENGTH_8814A	0x0458
++#define REG_ACQ_STOP_8814A				0x045C
++#define REG_NDPA_RATE_8814A				0x045D
++#define REG_TX_HANG_CTRL_8814A			0x045E
++#define REG_NDPA_OPT_CTRL_8814A		0x045F
++#define REG_FAST_EDCA_CTRL_8814A		0x0460
++#define REG_RD_RESP_PKT_TH_8814A		0x0463
++#define REG_CMDQ_INFO_8814A				0x0464
++#define REG_Q4_INFO_8814A					0x0468
++#define REG_Q5_INFO_8814A					0x046C
++#define REG_Q6_INFO_8814A					0x0470
++#define REG_Q7_INFO_8814A					0x0474
++#define REG_WMAC_LBK_BUF_HD_8814A		0x0478
++#define REG_MGQ_PGBNDY_8814A				0x047A
++#define REG_INIRTS_RATE_SEL_8814A			0x0480
++#define REG_BASIC_CFEND_RATE_8814A		0x0481
++#define REG_STBC_CFEND_RATE_8814A		0x0482
++#define REG_DATA_SC_8814A					0x0483
++#define REG_MACID_SLEEP3_8814A			0x0484
++#define REG_MACID_SLEEP1_8814A			0x0488
++#ifdef CONFIG_WOWLAN
++	#define REG_TXPKTBUF_IV_LOW				0x0484
++	#define REG_TXPKTBUF_IV_HIGH			0x0488
++#endif /* CONFIG_WOWLAN */
++#define REG_ARFR2_8814A					0x048C
++#define REG_ARFR3_8814A					0x0494
++#define REG_ARFR4_8814A					0x049C
++#define REG_ARFR5_8814A					0x04A4
++#define REG_TXRPT_START_OFFSET_8814A		0x04AC
++#define REG_TRYING_CNT_TH_8814A			0x04B0
++#define REG_POWER_STAGE1_8814A		0x04B4
++#define REG_POWER_STAGE2_8814A		0x04B8
++#define REG_SW_AMPDU_BURST_MODE_CTRL_8814A	0x04BC
++#define REG_PKT_LIFE_TIME_8814A			0x04C0
++#define REG_PKT_BE_BK_LIFE_TIME_8814A		0x04C2 /* ?????? */
++#define REG_STBC_SETTING_8814A			0x04C4
++#define REG_STBC_8814A						0x04C5
++#define REG_QUEUE_CTRL_8814A				0x04C6
++#define REG_SINGLE_AMPDU_CTRL_8814A		0x04C7
++#define REG_PROT_MODE_CTRL_8814A		0x04C8
++#define REG_MAX_AGGR_NUM_8814A		0x04CA
++#define REG_RTS_MAX_AGGR_NUM_8814A	0x04CB
++#define REG_BAR_MODE_CTRL_8814A		0x04CC
++#define REG_RA_TRY_RATE_AGG_LMT_8814A	0x04CF
++#define REG_MACID_SLEEP2_8814A			0x04D0
++#define REG_MACID_SLEEP0_8814A			0x04D4
++#define REG_HW_SEQ0_8814A				0x04D8
++#define REG_HW_SEQ1_8814A				0x04DA
++#define REG_HW_SEQ2_8814A				0x04DC
++#define REG_HW_SEQ3_8814A				0x04DE
++#define REG_NULL_PKT_STATUS_8814A			0x04E0
++#define REG_PTCL_ERR_STATUS_8814A			0x04E2
++#define REG_DROP_PKT_NUM_8814A			0x04EC
++#define REG_PTCL_TX_RPT_8814A				0x04F0
++#define REG_Dummy_8814A					0x04FC
++
++
++/* -----------------------------------------------------
++ *
++ *	0x0500h ~ 0x05FFh	EDCA Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_EDCA_VO_PARAM_8814A			0x0500
++#define REG_EDCA_VI_PARAM_8814A			0x0504
++#define REG_EDCA_BE_PARAM_8814A			0x0508
++#define REG_EDCA_BK_PARAM_8814A			0x050C
++#define REG_BCNTCFG_8814A					0x0510
++#define REG_PIFS_8814A						0x0512
++#define REG_RDG_PIFS_8814A					0x0513
++#define REG_SIFS_CTX_8814A					0x0514
++#define REG_SIFS_TRX_8814A					0x0516
++#define REG_AGGR_BREAK_TIME_8814A			0x051A
++#define REG_SLOT_8814A						0x051B
++#define REG_TX_PTCL_CTRL_8814A				0x0520
++#define REG_TXPAUSE_8814A					0x0522
++#define REG_DIS_TXREQ_CLR_8814A			0x0523
++#define REG_RD_CTRL_8814A					0x0524
++/*
++ * Format for offset 540h-542h:
++ *	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
++ *	[7:4]:   Reserved.
++ *	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
++ *	[23:20]: Reserved
++ * Description:
++ *	              |
++ * |<--Setup--|--Hold------------>|
++ *	--------------|----------------------
++ * |
++ * TBTT
++ * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
++ * Described by Designer Tim and Bruce, 2011-01-14.
++ *   */
++#define REG_TBTT_PROHIBIT_8814A			0x0540
++#define REG_RD_NAV_NXT_8814A				0x0544
++#define REG_NAV_PROT_LEN_8814A			0x0546
++#define REG_BCN_CTRL_8814A					0x0550
++#define REG_BCN_CTRL_1_8814A				0x0551
++#define REG_MBID_NUM_8814A				0x0552
++#define REG_DUAL_TSF_RST_8814A				0x0553
++#define REG_MBSSID_BCN_SPACE_8814A		0x0554
++#define REG_DRVERLYINT_8814A				0x0558
++#define REG_BCNDMATIM_8814A				0x0559
++#define REG_ATIMWND_8814A					0x055A
++#define REG_USTIME_TSF_8814A				0x055C
++#define REG_BCN_MAX_ERR_8814A				0x055D
++#define REG_RXTSF_OFFSET_CCK_8814A		0x055E
++#define REG_RXTSF_OFFSET_OFDM_8814A		0x055F
++#define REG_TSFTR_8814A						0x0560
++#define REG_CTWND_8814A					0x0572
++#define REG_SECONDARY_CCA_CTRL_8814A		0x0577 /* ?????? */
++#define REG_PSTIMER_8814A					0x0580
++#define REG_TIMER0_8814A					0x0584
++#define REG_TIMER1_8814A					0x0588
++#define REG_BCN_PREDL_ITV_8814A			0x058F	/* Pre download beacon interval */
++#define REG_ACMHWCTRL_8814A				0x05C0
++#define REG_P2P_RST_8814A				0x05F0
++
++/* -----------------------------------------------------
++ *
++ *	0x0600h ~ 0x07FFh	WMAC Configuration
++ *
++ * ----------------------------------------------------- */
++#define REG_MAC_CR_8814A					0x0600
++#define REG_TCR_8814A						0x0604
++#define REG_RCR_8814A						0x0608
++#define REG_RX_PKT_LIMIT_8814A				0x060C
++#define REG_RX_DLK_TIME_8814A				0x060D
++#define REG_RX_DRVINFO_SZ_8814A			0x060F
++
++#define REG_MACID_8814A					0x0610
++#define REG_BSSID_8814A						0x0618
++#define REG_MAR_8814A						0x0620
++#define REG_MBIDCAMCFG_8814A				0x0628
++
++#define REG_USTIME_EDCA_8814A				0x0638
++#define REG_MAC_SPEC_SIFS_8814A			0x063A
++#define REG_RESP_SIFP_CCK_8814A			0x063C
++#define REG_RESP_SIFS_OFDM_8814A			0x063E
++#define REG_ACKTO_8814A					0x0640
++#define REG_CTS2TO_8814A					0x0641
++#define REG_EIFS_8814A						0x0642
++
++#define	REG_NAV_UPPER_8814A				0x0652	/* unit of 128 */
++#define REG_TRXPTCL_CTL_8814A				0x0668
++
++/* Security */
++#define REG_CAMCMD_8814A					0x0670
++#define REG_CAMWRITE_8814A				0x0674
++#define REG_CAMREAD_8814A					0x0678
++#define REG_CAMDBG_8814A					0x067C
++#define REG_SECCFG_8814A					0x0680
++
++/* Power */
++#define REG_WOW_CTRL_8814A				0x0690
++#define REG_PS_RX_INFO_8814A				0x0692
++#define REG_UAPSD_TID_8814A				0x0693
++#define REG_WKFMCAM_NUM_8814A			0x0698
++#define REG_RXFLTMAP0_8814A				0x06A0
++#define REG_RXFLTMAP1_8814A				0x06A2
++#define REG_RXFLTMAP2_8814A				0x06A4
++#define REG_BCN_PSR_RPT_8814A				0x06A8
++#define REG_BT_COEX_TABLE_8814A			0x06C0
++#define REG_TX_DATA_RSP_RATE_8814A		0x06DE
++#define REG_ASSOCIATED_BFMER0_INFO_8814A	0x06E4
++#define REG_ASSOCIATED_BFMER1_INFO_8814A	0x06EC
++#define REG_CSI_RPT_PARAM_BW20_8814A		0x06F4
++#define REG_CSI_RPT_PARAM_BW40_8814A		0x06F8
++#define REG_CSI_RPT_PARAM_BW80_8814A		0x06FC
++
++/* Hardware Port 2 */
++#define REG_MACID1_8814A					0x0700
++#define REG_BSSID1_8814A					0x0708
++/* Hardware Port 3 */
++#define REG_MACID2_8814A					0x1620
++#define REG_BSSID2_8814A					0x1628
++/* Hardware Port 4 */
++#define REG_MACID3_8814A					0x1630
++#define REG_BSSID3_8814A					0x1638
++/* Hardware Port 5 */
++#define REG_MACID4_8814A					0x1640
++#define REG_BSSID4_8814A					0x1648
++
++#define REG_ASSOCIATED_BFMEE_SEL_8814A	0x0714
++#define REG_SND_PTCL_CTRL_8814A			0x0718
++#define REG_IQ_DUMP_8814A					0x07C0
++
++#define REG_CPU_DMEM_CON_8814A			0x1080
++
++/**** page 19 ****/
++/* TX BeamForming */
++#define	REG_BB_TXBF_ANT_SET_BF1				0x19ac
++#define	REG_BB_TXBF_ANT_SET_BF0				0x19b4
++
++/*	0x1200h ~ 0x12FFh	DDMA CTRL
++ *
++ * ----------------------------------------------------- */
++#define REG_DDMA_CH0SA                   0x1200
++#define REG_DDMA_CH0DA                   0x1204
++#define REG_DDMA_CH0CTRL                0x1208
++#define REG_DDMA_CH1SA                   0x1210
++#define REG_DDMA_CH1DA	0x1214
++#define REG_DDMA_CH1CTRL                0x1218
++#define REG_DDMA_CH2SA                   0x1220
++#define REG_DDMA_CH2DA                   0x1224
++#define REG_DDMA_CH2CTRL                0x1228
++#define REG_DDMA_CH3SA                   0x1230
++#define REG_DDMA_CH3DA                   0x1234
++#define REG_DDMA_CH3CTRL                0x1238
++#define REG_DDMA_CH4SA                   0x1240
++#define REG_DDMA_CH4DA                   0x1244
++#define REG_DDMA_CH4CTRL                0x1248
++#define REG_DDMA_CH5SA                   0x1250
++#define REG_DDMA_CH5DA                   0x1254
++#define REG_DDMA_CH5CTRL                0x1258
++#define REG_DDMA_INT_MSK                0x12E0
++#define REG_DDMA_CHSTATUS              0x12E8
++#define REG_DDMA_CHKSUM                 0x12F0
++#define REG_DDMA_MONITER                0x12FC
++
++#define REG_Q0_Q1_INFO_8814A		0x1400
++#define REG_Q2_Q3_INFO_8814A		0x1404
++#define REG_Q4_Q5_INFO_8814A		0x1408
++#define REG_Q6_Q7_INFO_8814A		0x140C
++#define REG_MGQ_HIQ_INFO_8814A	0x1410
++#define REG_CMDQ_BCNQ_INFO_8814A	0x1414
++
++#define REG_MACID_DROP0_8814A 0x1450
++#define REG_MACID_DROP1_8814A 0x1454
++#define REG_MACID_DROP2_8814A 0x1458
++#define REG_MACID_DROP3_8814A 0x145C
++
++
++#define DDMA_LEN_MASK		0x0001FFFF
++#define FW_CHKSUM_DUMMY_SZ		8
++#define DDMA_CH_CHKSUM_CNT		BIT(24)
++#define DDMA_RST_CHKSUM_STS		BIT(25)
++#define DDMA_MODE_BLOCK_CPU		BIT(26)
++#define DDMA_CHKSUM_FAIL			BIT(27)
++#define DDMA_DA_W_DISABLE			BIT(28)
++#define DDMA_CHKSUM_EN			BIT(29)
++#define DDMA_CH_OWN	BIT(31)
++
++
++/* 3081 FWDL */
++#define FWDL_EN                 BIT0
++#define IMEM_BOOT_DL_RDY        BIT1
++#define IMEM_BOOT_CHKSUM_FAIL   BIT2
++#define IMEM_DL_RDY             BIT3
++#define IMEM_CHKSUM_OK        BIT4
++#define DMEM_DL_RDY             BIT5
++#define DMEM_CHKSUM_OK        BIT6
++#define EMEM_DL_RDY             BIT7
++#define EMEM_CHKSUM_FAIL        BIT8
++#define EMEM_TXBUF_DL_RDY       BIT9
++#define EMEM_TXBUF_CHKSUM_FAIL  BIT10
++#define CPU_CLK_SWITCH_BUSY     BIT11
++#define CPU_CLK_SEL             (BIT12 | BIT13)
++#define FWDL_OK                 BIT14
++#define FW_INIT_RDY             BIT15
++#define R_EN_BOOT_FLASH         BIT20
++
++#define OCPBASE_IMEM_3081        0x00000000
++#define OCPBASE_DMEM_3081        0x00200000
++#define OCPBASE_RPTBUF_3081      0x18660000
++#define OCPBASE_RXBUF2_3081      0x18680000
++#define OCPBASE_RXBUF_3081       0x18700000
++#define OCPBASE_TXBUF_3081       0x18780000
++
++
++#define REG_FAST_EDCA_VOVI_SETTING_8814A 0x1448
++#define REG_FAST_EDCA_BEBK_SETTING_8814A 0x144C
++
++
++/* -----------------------------------------------------
++ *   */
++
++
++/* -----------------------------------------------------
++ *
++ *	Redifine 8192C register definition for compatibility
++ *
++ * ----------------------------------------------------- */
++
++/* TODO: use these definition when using REG_xxx naming rule.
++ * NOTE: DO NOT Remove these definition. Use later. */
++#define	EFUSE_CTRL_8814A					REG_EFUSE_CTRL_8814A		/* E-Fuse Control. */
++#define	EFUSE_TEST_8814A					REG_LDO_EFUSE_CTRL_8814A		/* E-Fuse Test. */
++#define	MSR_8814A							(REG_CR_8814A + 2)		/* Media Status register */
++#define	ISR_8814A							REG_HISR0_8814A
++#define	TSFR_8814A							REG_TSFTR_8814A			/* Timing Sync Function Timer Register. */
++
++#define PBP_8814A							REG_PBP_8814A
++
++/* Redifine MACID register, to compatible prior ICs. */
++#define	IDR0_8814A							REG_MACID_8814A			/* MAC ID Register, Offset 0x0050-0x0053 */
++#define	IDR4_8814A							(REG_MACID_8814A + 4)	/* MAC ID Register, Offset 0x0054-0x0055 */
++
++
++/*
++ * 9. Security Control Registers	(Offset: )
++ *   */
++#define	RWCAM_8814A						REG_CAMCMD_8814A		/*  8190 Data Sheet is called CAMcmd */
++#define	WCAMI_8814A						REG_CAMWRITE_8814A		/* Software write CAM input content */
++#define	RCAMO_8814A						REG_CAMREAD_8814A		/* Software read/write CAM config */
++#define	CAMDBG_8814A						REG_CAMDBG_8814A
++#define	SECR_8814A							REG_SECCFG_8814A		/* Security Configuration Register */
++
++
++/* ----------------------------------------------------------------------------
++ * 8195 IMR/ISR bits						(offset 0xB0,  8bits)
++ * ---------------------------------------------------------------------------- */
++#define	IMR_DISABLED_8814A					0
++/* IMR DW0(0x00B0-00B3) Bit 0-31 */
++#define	IMR_TIMER2_8814A					BIT31		/* Timeout interrupt 2 */
++#define	IMR_TIMER1_8814A					BIT30		/* Timeout interrupt 1	 */
++#define	IMR_PSTIMEOUT_8814A				BIT29		/* Power Save Time Out Interrupt */
++#define	IMR_GTINT4_8814A					BIT28		/* When GTIMER4 expires, this bit is set to 1	 */
++#define	IMR_GTINT3_8814A					BIT27		/* When GTIMER3 expires, this bit is set to 1	 */
++#define	IMR_TXBCN0ERR_8814A				BIT26		/* Transmit Beacon0 Error			 */
++#define	IMR_TXBCN0OK_8814A					BIT25		/* Transmit Beacon0 OK			 */
++#define	IMR_TSF_BIT32_TOGGLE_8814A		BIT24		/* TSF Timer BIT32 toggle indication interrupt			 */
++#define	IMR_BCNDMAINT0_8814A				BIT20		/* Beacon DMA Interrupt 0			 */
++#define	IMR_BCNDERR0_8814A					BIT16		/* Beacon Queue DMA OK0			 */
++#define	IMR_HSISR_IND_ON_INT_8814A		BIT15		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
++#define	IMR_BCNDMAINT_E_8814A				BIT14		/* Beacon DMA Interrupt Extension for Win7			 */
++#define	IMR_ATIMEND_8814A					BIT12		/* CTWidnow End or ATIM Window End */
++#define	IMR_C2HCMD_8814A					BIT10		/* CPU to Host Command INT Status, Write 1 clear	 */
++#define	IMR_CPWM2_8814A					BIT9			/* CPU power Mode exchange INT Status, Write 1 clear	 */
++#define	IMR_CPWM_8814A						BIT8			/* CPU power Mode exchange INT Status, Write 1 clear	 */
++#define	IMR_HIGHDOK_8814A					BIT7			/* High Queue DMA OK	 */
++#define	IMR_MGNTDOK_8814A					BIT6			/* Management Queue DMA OK	 */
++#define	IMR_BKDOK_8814A					BIT5			/* AC_BK DMA OK		 */
++#define	IMR_BEDOK_8814A					BIT4			/* AC_BE DMA OK	 */
++#define	IMR_VIDOK_8814A					BIT3			/* AC_VI DMA OK		 */
++#define	IMR_VODOK_8814A					BIT2			/* AC_VO DMA OK	 */
++#define	IMR_RDU_8814A						BIT1			/* Rx Descriptor Unavailable	 */
++#define	IMR_ROK_8814A						BIT0			/* Receive DMA OK */
++
++/* IMR DW1(0x00B4-00B7) Bit 0-31 */
++#define	IMR_MCUERR_8814A						BIT28		/* Beacon DMA Interrupt 7 */
++#define	IMR_BCNDMAINT7_8814A				BIT27		/* Beacon DMA Interrupt 7 */
++#define	IMR_BCNDMAINT6_8814A				BIT26		/* Beacon DMA Interrupt 6 */
++#define	IMR_BCNDMAINT5_8814A				BIT25		/* Beacon DMA Interrupt 5 */
++#define	IMR_BCNDMAINT4_8814A				BIT24		/* Beacon DMA Interrupt 4 */
++#define	IMR_BCNDMAINT3_8814A				BIT23		/* Beacon DMA Interrupt 3 */
++#define	IMR_BCNDMAINT2_8814A				BIT22		/* Beacon DMA Interrupt 2 */
++#define	IMR_BCNDMAINT1_8814A				BIT21		/* Beacon DMA Interrupt 1 */
++#define	IMR_BCNDOK7_8814A					BIT20		/* Beacon Queue DMA OK Interrup 7 */
++#define	IMR_BCNDOK6_8814A					BIT19		/* Beacon Queue DMA OK Interrup 6 */
++#define	IMR_BCNDOK5_8814A					BIT18		/* Beacon Queue DMA OK Interrup 5 */
++#define	IMR_BCNDOK4_8814A					BIT17		/* Beacon Queue DMA OK Interrup 4 */
++#define	IMR_BCNDOK3_8814A					BIT16		/* Beacon Queue DMA OK Interrup 3 */
++#define	IMR_BCNDOK2_8814A					BIT15		/* Beacon Queue DMA OK Interrup 2 */
++#define	IMR_BCNDOK1_8814A					BIT14		/* Beacon Queue DMA OK Interrup 1 */
++#define	IMR_ATIMEND_E_8814A				BIT13		/* ATIM Window End Extension for Win7 */
++#define	IMR_TXERR_8814A					BIT11		/* Tx Error Flag Interrupt Status, write 1 clear. */
++#define	IMR_RXERR_8814A					BIT10		/* Rx Error Flag INT Status, Write 1 clear */
++#define	IMR_TXFOVW_8814A					BIT9			/* Transmit FIFO Overflow */
++#define	IMR_RXFOVW_8814A					BIT8			/* Receive FIFO Overflow */
++
++
++#ifdef CONFIG_PCI_HCI
++	#define IMR_TX_MASK			(IMR_VODOK_8814A | IMR_VIDOK_8814A | IMR_BEDOK_8814A | IMR_BKDOK_8814A | IMR_MGNTDOK_8814A | IMR_HIGHDOK_8814A)
++
++	#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8814A | IMR_TXBCN0OK_8814A | IMR_TXBCN0ERR_8814A | IMR_BCNDERR0_8814A)
++
++	#define RT_AC_INT_MASKS	(IMR_VIDOK_8814A | IMR_VODOK_8814A | IMR_BEDOK_8814A | IMR_BKDOK_8814A)
++#endif
++
++
++/*===================================================================
++=====================================================================
++Here the register defines are for 92C. When the define is as same with 92C,
++we will use the 92C's define for the consistency
++So the following defines for 92C is not entire!!!!!!
++=====================================================================
++=====================================================================*/
++
++
++/* -----------------------------------------------------
++ *
++ *	0xFE00h ~ 0xFE55h	USB Configuration
++ *
++ * ----------------------------------------------------- */
++
++/* 2 Special Option */
++#define USB_AGG_EN_8814A			BIT(7)
++#define REG_USB_HRPWM_U3			0xF052
++
++#define LAST_ENTRY_OF_TX_PKT_BUFFER_8814A       (2048-1)	/* 20130415 KaiYuan add for 8814 */
++
++#endif /* __RTL8814A_SPEC_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_sreset.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_sreset.h
+new file mode 100644
+index 000000000..d65cb98a5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_sreset.h
+@@ -0,0 +1,24 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL88814A_SRESET_H_
++#define _RTL8814A_SRESET_H_
++
++#include <rtw_sreset.h>
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++	extern void rtl8814_sreset_xmit_status_check(_adapter *padapter);
++	extern void rtl8814_sreset_linked_status_check(_adapter *padapter);
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_xmit.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_xmit.h
+new file mode 100755
+index 000000000..95a82063f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814a_xmit.h
+@@ -0,0 +1,309 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8814A_XMIT_H__
++#define __RTL8814A_XMIT_H__
++
++typedef struct txdescriptor_8814 {
++	/* Offset 0 */
++	u32 pktlen:16;
++	u32 offset:8;
++	u32 bmc:1;
++	u32 htc:1;
++	u32 ls:1;
++} TXDESC_8814, *PTXDESC_8814;
++
++
++#define OFFSET_SZ	0
++#define OFFSET_SHT	16
++
++
++
++#ifdef CONFIG_SDIO_HCI
++	#define SET_TX_DESC_SDIO_TXSEQ_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
++#endif /* CONFIG_SDIO_HCI */
++
++/* -----------------------------------------------------------------
++ *	RTL8814A TX BUFFER DESC
++ * -----------------------------------------------------------------
++ *
++- Each TXBD has 4 segment.
++ -- For 32 bit, each segment is 8 bytes.
++ -- For 64 bit, each segment is 16 bytes.
++*/
++#if 0
++	#if 1 /* 32 bit */
++		#define SET_TX_EXTBUFF_DESC_LEN_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*8), 0, 16, __Value)
++		#define SET_TX_EXTBUFF_DESC_ADDR_LOW_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*8)+4, 0, 32, __Value)
++	#else /* 64 bit */
++		#define SET_TX_EXTBUFF_DESC_LEN_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*16), 0, 16, __Value)
++		#define SET_TX_EXTBUFF_DESC_ADDR_LOW_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*16)+4, 0, 32, __Value)
++	#endif
++	#define SET_TX_EXTBUFF_DESC_ADDR_HIGH_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*16)+8, 0, 32, __Value)
++#endif
++/*c2h-DWORD 2*/
++#define GET_RX_STATUS_DESC_RPT_SEL_8814A(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+8, 28, 1)
++
++/* *********************************************************
++ * for Txfilldescroptor8814Ae, fill the desc content. */
++#if 1 /* 32 bit */
++	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*8), 0, 16, __Valeu)
++	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*8), 31, 1, __Valeu)
++	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*8)+4, 0, 32, __Valeu)
++#else /* 64 bit */
++	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)
++	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)
++	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)
++#endif
++#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)
++
++/* ********************************************************* */
++
++/* TX buffer
++ * *************
++ * Dword 0 */
++#define SET_TX_BUFF_DESC_LEN_0_8814A(__pTxDesc, __Valeu)			SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Valeu)
++#define SET_TX_BUFF_DESC_PSB_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
++#define SET_TX_BUFF_DESC_OWN_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
++#define GET_TX_BUFF_DESC_OWN_8814A(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
++
++/* Dword 1 */
++#define SET_TX_BUFF_DESC_ADDR_LOW_0_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
++#define GET_TX_BUFF_DESC_ADDR_LOW_0_8814A(__pTxDesc)			LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
++/* Dword 2 */
++#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 32, __Value)
++#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8814A(__pTxDesc)			LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)
++/* Dword 3 */ /* RESERVED 0 */
++
++#if 0 /* 64 bit */
++	/* Dword 4 */
++	#define SET_TX_BUFF_DESC_LEN_1_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 16, __Value)
++	#define SET_TX_BUFF_DESC_AMSDU_1_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 31, 1, __Value)
++	/* Dword 5 */
++	#define SET_TX_BUFF_DESC_ADDR_LOW_1_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 32, __Value)
++	/* Dword 6 */
++	#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 32, __Value)
++	/* Dword 7 */ /* RESERVED 0 */
++	/* Dword 8 */
++	#define SET_TX_BUFF_DESC_LEN_2_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 16, __Value)
++	#define SET_TX_BUFF_DESC_AMSDU_2_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 31, 1, __Value)
++	/* Dword 9 */
++	#define SET_TX_BUFF_DESC_ADDR_LOW_2_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 32, __Value)
++	/* Dword 10 */
++	#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
++	/* Dword 11 */ /* RESERVED 0 */
++	/* Dword 12 */
++	#define SET_TX_BUFF_DESC_LEN_3_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 16, __Value)
++	#define SET_TX_BUFF_DESC_AMSDU_3_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 31, 1, __Value)
++	/* Dword 13 */
++	#define SET_TX_BUFF_DESC_ADDR_LOW_3_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+52, 0, 32, __Value)
++	/* Dword 14 */
++	#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+56, 0, 32, __Value)
++	/* Dword 15 */ /* RESERVED 0 */
++#endif
++
++/* *****Desc content
++ * TX Info
++ * *************
++ * Dword 0 */
++#define SET_TX_DESC_PKT_SIZE_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
++#define GET_TX_DESC_PKT_SIZE_8814A(__pTxDesc)									LE_BITS_TO_4BYTE(__pTxDesc, 0, 16)
++#define SET_TX_DESC_OFFSET_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
++#define GET_TX_DESC_OFFSET_8814A(__pTxDesc)									LE_BITS_TO_4BYTE(__pTxDesc, 16, 8)
++#define SET_TX_DESC_BMC_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
++#define SET_TX_DESC_HTC_8814A(__pTxDesc, __Value)								SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
++#define SET_TX_DESC_LAST_SEG_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
++#define SET_TX_DESC_LINIP_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
++#define SET_TX_DESC_AMSDU_PAD_EN_8814A(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
++#define SET_TX_DESC_NO_ACM_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
++#define SET_TX_DESC_GF_8814A(__pTxDesc, __Value)								SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
++#define SET_TX_DESC_DISQSELSEQ_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
++
++/* Dword 1 */
++#define SET_TX_DESC_MACID_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
++#define SET_TX_DESC_QUEUE_SEL_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
++#define SET_TX_DESC_RDG_NAV_EXT_8814A(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
++#define SET_TX_DESC_LSIG_TXOP_EN_8814A(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
++#define SET_TX_DESC_PIFS_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
++#define SET_TX_DESC_RATE_ID_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
++#define SET_TX_DESC_EN_DESC_ID_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
++#define SET_TX_DESC_SEC_TYPE_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
++#define SET_TX_DESC_PKT_OFFSET_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
++#define SET_TX_DESC_MORE_DATA_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
++#define SET_TX_DESC_TXOP_PS_CAP_8814A(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 30, 1, __Value)
++#define SET_TX_DESC_TXOP_PS_MODE_8814A(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 31, 1, __Value)
++
++
++/* Dword 2 */
++#define SET_TX_DESC_PAID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
++#define SET_TX_DESC_CCA_RTS_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
++#define SET_TX_DESC_AGG_ENABLE_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
++#define SET_TX_DESC_RDG_ENABLE_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
++#define SET_TX_DESC_NULL_0_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
++#define SET_TX_DESC_NULL_1_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
++#define SET_TX_DESC_BK_8814A(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
++#define SET_TX_DESC_MORE_FRAG_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
++#define GET_TX_DESC_MORE_FRAG_8814A(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc+8, 17, 1)
++#define SET_TX_DESC_RAW_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
++#define SET_TX_DESC_SPE_RPT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
++#define SET_TX_DESC_AMPDU_DENSITY_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
++#define SET_TX_DESC_BT_NULL_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
++#define SET_TX_DESC_GID_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
++#define SET_TX_DESC_HW_AES_IV_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 31, 1, __Value)
++
++
++/* Dword 3 */
++#define SET_TX_DESC_WHEADER_LEN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 5, __Value)
++#define SET_TX_DESC_EARLY_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
++#define SET_TX_DESC_HW_SSN_SEL_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
++#define SET_TX_DESC_USE_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
++#define SET_TX_DESC_DISABLE_RTS_FB_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
++#define SET_TX_DESC_DISABLE_FB_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
++#define SET_TX_DESC_CTS2SELF_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
++#define SET_TX_DESC_RTS_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
++#define SET_TX_DESC_HW_RTS_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
++#define SET_TX_DESC_CHECK_EN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value)
++#define SET_TX_DESC_NAV_USE_HDR_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
++#define SET_TX_DESC_USE_MAX_LEN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
++#define SET_TX_DESC_MAX_AGG_NUM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
++#define SET_TX_DESC_NDPA_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
++#define SET_TX_DESC_AMPDU_MAX_TIME_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
++
++/* Dword 4 */
++#define SET_TX_DESC_TX_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
++#define SET_TX_DESC_TRY_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
++#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
++#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
++#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
++#define SET_TX_DESC_DATA_RETRY_LIMIT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
++#define SET_TX_DESC_RTS_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
++#define SET_TX_DESC_PCTS_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
++#define SET_TX_DESC_PCTS_MASK_IDX_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
++
++
++/* Dword 5 */
++#define SET_TX_DESC_DATA_SC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
++#define SET_TX_DESC_DATA_SHORT_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
++#define SET_TX_DESC_DATA_BW_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
++#define SET_TX_DESC_DATA_LDPC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
++#define SET_TX_DESC_DATA_STBC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
++#define SET_TX_DESC_CTROL_STBC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
++#define SET_TX_DESC_RTS_SHORT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
++#define SET_TX_DESC_RTS_SC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
++#define SET_TX_DESC_SIGNALING_TA_PKT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 17, 1, __Value)
++#define SET_TX_DESC_PORT_ID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 21, 3, __Value)/* 20130415 KaiYuan add for 8814 */
++#define SET_TX_DESC_TX_ANT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value)
++#define SET_TX_DESC_TX_POWER_OFFSET_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
++
++/* Dword 6 */
++#define SET_TX_DESC_SW_DEFINE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
++#define SET_TX_DESC_MBSSID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
++#define SET_TX_DESC_ANTSEL_A_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
++#define SET_TX_DESC_ANTSEL_B_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
++#define SET_TX_DESC_ANT_MAPA_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 2, __Value)
++#define SET_TX_DESC_ANT_MAPB_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 24, 2, __Value)
++#define SET_TX_DESC_ANT_MAPC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 26, 2, __Value)
++#define SET_TX_DESC_ANT_MAPD_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 28, 2, __Value)
++
++
++/* Dword 7 */
++#ifdef CONFIG_PCI_HCI
++	#define SET_TX_DESC_TX_BUFFER_SIZE_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++#endif
++#if defined(CONFIG_SDIO_HCI)|| defined(CONFIG_USB_HCI)
++	#define SET_TX_DESC_TX_DESC_CHECKSUM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
++#endif
++#define SET_TX_DESC_NTX_MAP_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 20, 4, __Value)
++#define SET_TX_DESC_USB_TXAGG_NUM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
++
++
++/* Dword 8 */
++#define SET_TX_DESC_RTS_RC_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
++#define SET_TX_DESC_BAR_RTY_TH_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
++#define SET_TX_DESC_DATA_RC_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
++#define SET_TX_DESC_EN_HWEXSEQ_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 14, 1, __Value)
++#define SET_TX_DESC_HWSEQ_EN_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
++#if defined(CONFIG_PCI_HCI)|| defined(CONFIG_USB_HCI)
++	#define SET_TX_DESC_NEXT_HEAD_PAGE_L_8814A(__pTxDesc, __Value)(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
++#endif
++#ifdef CONFIG_SDIO_HCI
++	#define SET_TX_DESC_SDIO_SEQ_8814A(__pTxDesc, __Value)(__pTxDesc, __Value) 			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value) /* 20130415 KaiYuan add for 8814AS */
++#endif
++#define SET_TX_DESC_TAIL_PAGE_L_8814A(__pTxDesc, __Value)(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
++
++/* Dword 9 */
++#define SET_TX_DESC_PADDING_LENGTH_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
++#define SET_TX_DESC_TXBF_PATH_8814A(__pTxDesc, __Value)								SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 11, 1, __Value)
++#define SET_TX_DESC_SEQ_8814A(__pTxDesc, __Value)										SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
++#define SET_TX_DESC_NEXT_HEAD_PAGE_H_8814A(__pTxDesc, __Value)(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 4, __Value)
++#define SET_TX_DESC_TAIL_PAGE_H_8814A(__pTxDesc, __Value)(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 28, 4, __Value)
++
++
++
++#define SET_EARLYMODE_PKTNUM_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
++#define SET_EARLYMODE_LEN0_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
++#define SET_EARLYMODE_LEN1_1_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
++#define SET_EARLYMODE_LEN1_2_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
++#define SET_EARLYMODE_LEN2_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,  __Value)
++#define SET_EARLYMODE_LEN3_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
++
++
++void rtl8814a_cal_txdesc_chksum(u8 *ptxdesc);
++void rtl8814a_fill_fake_txdesc(PADAPTER	padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8	IsBTQosNull, u8 bDataFrame);
++void rtl8814a_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc);
++void rtl8814a_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
++void rtl8814a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
++void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
++void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
++
++#ifdef CONFIG_USB_HCI
++	s32 rtl8814au_init_xmit_priv(PADAPTER padapter);
++	void rtl8814au_free_xmit_priv(PADAPTER padapter);
++	s32 rtl8814au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8814au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	 rtl8814au_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8814au_xmit_buf_handler(PADAPTER padapter);
++	void rtl8814au_xmit_tasklet(void *priv);
++	s32 rtl8814au_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++#endif /* CONFIG_USB_HCI */
++
++#ifdef CONFIG_PCI_HCI
++	s32 rtl8814ae_init_xmit_priv(PADAPTER padapter);
++	void rtl8814ae_free_xmit_priv(PADAPTER padapter);
++	struct xmit_buf *rtl8814ae_dequeue_xmitbuf(struct rtw_tx_ring *ring);
++	void rtl8814ae_xmitframe_resume(_adapter *padapter);
++	s32 rtl8814ae_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++	s32 rtl8814ae_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++	s32	rtl8814ae_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++	void rtl8814ae_xmit_tasklet(void *priv);
++#ifdef CONFIG_XMIT_THREAD_MODE
++	s32 rtl8814ae_xmit_buf_handler(_adapter *padapter);
++#endif
++#endif
++
++void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, u8 *ptxdesc);
++u8
++SCMapping_8814(
++		PADAPTER		Adapter,
++		struct pkt_attrib	*pattrib
++);
++
++u8
++BWMapping_8814(
++		PADAPTER		Adapter,
++		struct pkt_attrib	*pattrib
++);
++
++
++#endif /* __RTL8814_XMIT_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814b_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814b_hal.h
+new file mode 100755
+index 000000000..301d1a054
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814b_hal.h
+@@ -0,0 +1,239 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2015 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8814B_HAL_H_
++#define _RTL8814B_HAL_H_
++
++#include <osdep_service.h>		/* BIT(x) */
++#include <drv_types.h>			/* PADAPTER */
++#include "../hal/halmac/halmac_api.h"	/* MAC REG definition */
++
++
++#ifdef CONFIG_SUPPORT_TRX_SHARED
++#define MAX_RECVBUF_SZ		46080	/* 45KB, TX: (256-64)KB */
++#else /* !CONFIG_SUPPORT_TRX_SHARED */
++#define MAX_RECVBUF_SZ		24576	/* 24KB, TX: 256KB */
++#endif /* !CONFIG_SUPPORT_TRX_SHARED */
++
++#if 0
++/*
++ * MAC Register definition
++ */
++#define REG_AFE_XTAL_CTRL	REG_AFE_CTRL1_8814B	/* hal_com.c & phydm */
++#define REG_AFE_PLL_CTRL	REG_AFE_CTRL2_8814B	/* hal_com.c & phydm */
++#define REG_MAC_PHY_CTRL	REG_AFE_CTRL3_8814B	/* phydm only */
++#endif
++#define REG_LEDCFG0		REG_LED_CFG_8814B	/* rtw_mp.c */
++#if 0
++#define MSR			(REG_CR_8814B + 2)	/* rtw_mp.c & hal_com.c */
++#define MSR1			REG_CR_EXT_8814B	/* rtw_mp.c & hal_com.c */
++#endif
++#define REG_C2HEVT_MSG_NORMAL	0x1A0			/* hal_com.c */
++#if 0
++#define REG_C2HEVT_CLEAR	0x1AF			/* hal_com.c */
++
++#define REG_GPIO_PIN_CTRL_2		REG_GPIO_EXT_CTRL_8814B		/* hal_com.c */
++#endif
++#define REG_WKFMCAM_NUM		REG_WKFMCAM_CMD_8814B	/* hal_com.c: WOWLAN */
++#define REG_WOWLAN_WAKE_REASON	0x01C7 /* hal_com.c: WOWLAN */
++#define REG_RXPKTBUF_CTRL	(REG_PKTBUF_DBG_CTRL_8814B + 2)	/* hal_com.c: WOWLAN */
++#define REG_RXPKT_NUM		REG_RXDMA_CTRL_8814B	/* hal_com.c: WOWLAN */
++
++/* RXERR_RPT, for rtw_mp.c */
++#define RXERR_TYPE_OFDM_PPDU		0
++#define RXERR_TYPE_OFDM_FALSE_ALARM	2
++#define RXERR_TYPE_OFDM_MPDU_OK		0
++#define RXERR_TYPE_OFDM_MPDU_FAIL	1
++#define RXERR_TYPE_CCK_PPDU		3
++#define RXERR_TYPE_CCK_FALSE_ALARM	5
++#define RXERR_TYPE_CCK_MPDU_OK		3
++#define RXERR_TYPE_CCK_MPDU_FAIL	4
++#define RXERR_TYPE_HT_PPDU		8
++#define RXERR_TYPE_HT_FALSE_ALARM	9
++#define RXERR_TYPE_HT_MPDU_TOTAL	6
++#define RXERR_TYPE_HT_MPDU_OK		6
++#define RXERR_TYPE_HT_MPDU_FAIL		7
++#define RXERR_TYPE_RX_FULL_DROP		10
++
++#define RXERR_COUNTER_MASK		BIT_MASK_RPT_COUNTER_8814B
++#define RXERR_RPT_RST			BIT_RXERR_RPT_RST_8814B
++#define _RXERR_RPT_SEL(type)		(BIT_RXERR_RPT_SEL_V1_3_0_8814B(type) \
++					| ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8814B : 0))
++
++/* hal_com.c:rtw_lps_state_chk() */
++#define BIT_PWRBIT_OW_EN		BIT_WMAC_TCRPWRMGT_HWDATA_EN_8814B
++
++/*
++ * BB Register definition
++ */
++#define rPMAC_Reset			0x100	/* hal_mp.c */
++
++#define	rFPGA0_RFMOD			0x800
++#define rFPGA0_TxInfo			0x804
++#define rOFDMCCKEN_Jaguar		0x808	/* hal_mp.c */
++#define rFPGA0_TxGainStage		0x80C	/* phydm only */
++#define rFPGA0_XA_HSSIParameter1	0x820	/* hal_mp.c */
++#define rFPGA0_XA_HSSIParameter2	0x824	/* hal_mp.c */
++#define rFPGA0_XB_HSSIParameter1	0x828	/* hal_mp.c */
++#define rFPGA0_XB_HSSIParameter2	0x82C	/* hal_mp.c */
++#define rTxAGC_B_Rate18_06		0x830
++#define rTxAGC_B_Rate54_24		0x834
++#define rTxAGC_B_CCK1_55_Mcs32		0x838
++#define rCCAonSec_Jaguar		0x838	/* hal_mp.c */
++#define rTxAGC_B_Mcs03_Mcs00		0x83C
++#define rTxAGC_B_Mcs07_Mcs04		0x848
++#define rTxAGC_B_Mcs11_Mcs08		0x84C
++#define rFPGA0_XA_RFInterfaceOE		0x860
++#define rFPGA0_XB_RFInterfaceOE		0x864
++#define rTxAGC_B_Mcs15_Mcs12		0x868
++#define rTxAGC_B_CCK11_A_CCK2_11	0x86C
++#define rFPGA0_XAB_RFInterfaceSW	0x870
++#define rFPGA0_XAB_RFParameter		0x878
++#define rFPGA0_AnalogParameter4		0x88C	/* hal_mp.c & phydm */
++#define rFPGA0_XB_LSSIReadBack		0x8A4	/* phydm */
++#define rHSSIRead_Jaguar		0x8B0	/* RF read addr (rtl8814b_phy.c) */
++
++#define	rC_TxScale_Jaguar2		0x181C  /* Pah_C TX scaling factor (hal_mp.c) */
++#define	rC_IGI_Jaguar2			0x1850	/* Initial Gain for path-C (hal_mp.c) */
++
++#define rFPGA1_TxInfo			0x90C	/* hal_mp.c */
++#define rSingleTone_ContTx_Jaguar	0x914	/* hal_mp.c */
++/* TX BeamForming */
++#define REG_BB_TX_PATH_SEL_1_8814B	0x93C	/* rtl8814b_phy.c */
++#define REG_BB_TX_PATH_SEL_2_8814B	0x940	/* rtl8814b_phy.c */
++
++/* TX BeamForming */
++#define REG_BB_TXBF_ANT_SET_BF1_8814B	0x19AC	/* rtl8814b_phy.c */
++#define REG_BB_TXBF_ANT_SET_BF0_8814B	0x19B4	/* rtl8814b_phy.c */
++
++#define rCCK0_System			0xA00
++#define rCCK0_AFESetting		0xA04
++
++#define rCCK0_DSPParameter2		0xA1C
++#define rCCK0_TxFilter1			0xA20
++#define rCCK0_TxFilter2			0xA24
++#define rCCK0_DebugPort			0xA28
++#define rCCK0_FalseAlarmReport		0xA2C
++
++#define	rD_TxScale_Jaguar2		0x1A1C  /* Path_D TX scaling factor (hal_mp.c) */
++#define	rD_IGI_Jaguar2			0x1A50	/* Initial Gain for path-D (hal_mp.c) */
++
++#define rOFDM0_TRxPathEnable		0xC04
++#define rOFDM0_TRMuxPar			0xC08
++#define rA_TxScale_Jaguar		0xC1C	/* Pah_A TX scaling factor (hal_mp.c) */
++#define rOFDM0_RxDetector1		0xC30	/* rtw_mp.c */
++#define rOFDM0_ECCAThreshold		0xC4C	/* phydm only */
++#define rOFDM0_XAAGCCore1		0xC50	/* phydm only */
++#define rA_IGI_Jaguar			0xC50	/* Initial Gain for path-A (hal_mp.c) */
++#define rOFDM0_XBAGCCore1		0xC58	/* phydm only */
++#define rOFDM0_XATxIQImbalance		0xC80	/* phydm only */
++#define rA_LSSIWrite_Jaguar		0xC90	/* RF write addr, LSSI Parameter (rtl8814b_phy.c) */
++
++#define rOFDM1_LSTF			0xD00
++#define rOFDM1_TRxPathEnable		0xD04	/* hal_mp.c */
++#define rA_PIRead_Jaguar		0xD04	/* RF readback with PI (rtl8814b_phy.c) */
++#define rA_SIRead_Jaguar		0xD08	/* RF readback with SI (rtl8814b_phy.c) */
++#define rB_PIRead_Jaguar		0xD44	/* RF readback with PI (rtl8814b_phy.c) */
++#define rB_SIRead_Jaguar		0xD48	/* RF readback with SI (rtl8814b_phy.c) */
++
++#define rTxAGC_A_Rate18_06		0xE00
++#define rTxAGC_A_Rate54_24		0xE04
++#define rTxAGC_A_CCK1_Mcs32		0xE08
++#define rTxAGC_A_Mcs03_Mcs00		0xE10
++#define rTxAGC_A_Mcs07_Mcs04		0xE14
++#define rTxAGC_A_Mcs11_Mcs08		0xE18
++#define rTxAGC_A_Mcs15_Mcs12		0xE1C
++#define rB_TxScale_Jaguar		0xE1C	/* Path_B TX scaling factor (hal_mp.c) */
++#define rB_IGI_Jaguar			0xE50	/* Initial Gain for path-B (hal_mp.c) */
++#define rB_LSSIWrite_Jaguar		0xE90	/* RF write addr, LSSI Parameter (rtl8814b_phy.c) */
++/* RFE */
++#define rA_RFE_Pinmux_Jaguar	0xCB0	/* hal_mp.c */
++#define	rB_RFE_Pinmux_Jaguar	0xEB0	/* Path_B RFE control pinmux */
++#define	rA_RFE_Inv_Jaguar		0xCB4	/* Path_A RFE cotrol */  
++#define	rB_RFE_Inv_Jaguar		0xEB4	/* Path_B RFE control */
++#define	rA_RFE_Jaguar			0xCB8 	/* Path_A RFE cotrol */  
++#define	rB_RFE_Jaguar			0xEB8	/* Path_B RFE control */
++#define	rA_RFE_Inverse_Jaguar	0xCBC	/* Path_A RFE control inverse */
++#define	rB_RFE_Inverse_Jaguar	0xEBC	/* Path_B RFE control inverse */
++#define	r_ANTSEL_SW_Jaguar		0x900	/* ANTSEL SW Control */
++#define	bMask_RFEInv_Jaguar	0x3FF00000
++#define	bMask_AntselPathFollow_Jaguar 0x00030000
++
++#define		rC_RFE_Pinmux_Jaguar	0x18B4	/* Path_C RFE cotrol pinmux*/
++#define		rD_RFE_Pinmux_Jaguar	0x1AB4	/* Path_D RFE cotrol pinmux*/
++#define		rA_RFE_Sel_Jaguar2		0x1990
++
++/* Page1(0x100) */
++#define bBBResetB			0x100
++
++/* Page8(0x800) */
++#define bCCKEn				0x1000000
++#define bOFDMEn				0x2000000
++/* Reg 0x80C rFPGA0_TxGainStage */
++#define bXBTxAGC			0xF00
++#define bXCTxAGC			0xF000
++#define bXDTxAGC			0xF0000
++
++/* PageA(0xA00) */
++#define bCCKBBMode			0x3
++
++#define bCCKScramble			0x8
++#define bCCKTxRate			0x3000
++
++/* General */
++#define bMaskByte0		0xFF		/* mp, rtw_odm.c & phydm */
++#define bMaskByte1		0xFF00		/* hal_mp.c & phydm */
++#define bMaskByte2		0xFF0000	/* hal_mp.c & phydm */
++#define bMaskByte3		0xFF000000	/* hal_mp.c & phydm */
++#define bMaskHWord		0xFFFF0000	/* hal_com.c, rtw_mp.c */
++#define bMaskLWord		0x0000FFFF	/* mp, hal_com.c & phydm */
++#define bMaskDWord		0xFFFFFFFF	/* mp, hal, rtw_odm.c & phydm */
++
++#define bEnable			0x1		/* hal_mp.c, rtw_mp.c */
++#define bDisable		0x0		/* rtw_mp.c */
++
++#define MAX_STALL_TIME		50		/* unit: us, hal_com_phycfg.c */
++
++#define Rx_Smooth_Factor	20		/* phydm only */
++
++/*
++ * RF Register definition
++ */
++#define RF_AC			0x00
++#define RF_AC_Jaguar		0x00	/* hal_mp.c */
++#define RF_CHNLBW		0x18	/* rtl8814b_phy.c */
++#define RF_ModeTableAddr	0x30	/* rtl8814b_phy.c */
++#define RF_ModeTableData0	0x31	/* rtl8814b_phy.c */
++#define RF_ModeTableData1	0x32	/* rtl8814b_phy.c */
++#define RF_0x52			0x52
++#define RF_WeLut_Jaguar		0xEF	/* rtl8814b_phy.c */
++
++/* General Functions */
++void rtl8814b_init_hal_spec(PADAPTER);				/* hal/hal_com.c */
++
++#ifdef CONFIG_MP_INCLUDED
++/* MP Functions */
++#include <rtw_mp.h>		/* struct mp_priv */
++void rtl8814b_prepare_mp_txdesc(PADAPTER, struct mp_priv *);	/* rtw_mp.c */
++void rtl8814b_mp_config_rfpath(PADAPTER);			/* hal_mp.c */
++#endif
++void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus);
++
++#ifdef CONFIG_USB_HCI
++#include <rtl8814bu_hal.h>
++#elif defined(CONFIG_PCI_HCI)
++#include <rtl8814be_hal.h>
++#endif
++
++#endif /* _RTL8814B_HAL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814be_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814be_hal.h
+new file mode 100644
+index 000000000..3e124cae6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814be_hal.h
+@@ -0,0 +1,30 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2015 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8814BE_HAL_H_
++#define _RTL8814BE_HAL_H_
++
++#include <drv_types.h>		/* PADAPTER */
++
++#define RT_BCN_INT_MASKS	(BIT_BCNDMAINT0_MSK_8814B |	\
++				 BIT_TXBCN0OK_MSK_8814B |	\
++				 BIT_TXBCN0ERR_MSK_8814B |	\
++				 BIT_BCNDERR0_MSK_8814B)
++
++/* rtl8814be_ops.c */
++void UpdateInterruptMask8814BE(PADAPTER, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
++u16 get_txbd_rw_reg(u16 q_idx);
++
++
++#endif /* _RTL8814BE_HAL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814bu_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814bu_hal.h
+new file mode 100755
+index 000000000..aa5cef998
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8814bu_hal.h
+@@ -0,0 +1,61 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2015 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8814BU_HAL_H_
++#define _RTL8814BU_HAL_H_
++
++#ifdef CONFIG_USB_HCI
++	#include <drv_types.h>		/* PADAPTER */
++
++	#ifdef CONFIG_USB_HCI
++		#ifdef USB_PACKET_OFFSET_SZ
++			#define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ)
++		#else
++			#define PACKET_OFFSET_SZ (8)
++		#endif
++		#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)
++	#endif
++
++	/* undefine MAX_RECVBUF_SZ from rtl8822c_hal.h  */
++	#ifdef MAX_RECVBUF_SZ
++		#undef MAX_RECVBUF_SZ
++	#endif
++
++	/* recv_buffer must be large than usb agg size */
++	#ifndef MAX_RECVBUF_SZ
++		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
++			#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
++				#define MAX_RECVBUF_SZ (15360) /* 15k */
++				#elif defined(CONFIG_PLATFORM_HISILICON)
++				/* use 16k to workaround for HISILICON platform */
++				#define MAX_RECVBUF_SZ (16384)
++			#else
++				#define MAX_RECVBUF_SZ (32768)
++			#endif
++		#else
++			#define MAX_RECVBUF_SZ (4000)
++		#endif
++	#endif /* !MAX_RECVBUF_SZ */
++
++	/* rtl8814bu_ops.c */
++	void rtl8814bu_set_hal_ops(PADAPTER padapter);
++	void rtl8814bu_set_hw_type(struct dvobj_priv *pdvobj);
++
++	/* rtl8814bu_io.c */
++	void rtl8814bu_set_intf_ops(struct _io_ops *pops);
++
++#endif /* CONFIG_USB_HCI */
++
++
++#endif /* _RTL8814BU_HAL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821a_spec.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821a_spec.h
+new file mode 100644
+index 000000000..1379ffc3c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821a_spec.h
+@@ -0,0 +1,90 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8821A_SPEC_H__
++#define __RTL8821A_SPEC_H__
++
++#include <drv_conf.h>
++/* This file should based on "hal_com_reg.h" */
++#include <hal_com_reg.h>
++/* Because 8812a and 8821a is the same serial,
++ * most of 8821a register definitions are the same as 8812a. */
++#include <rtl8812a_spec.h>
++
++
++/* ************************************************************
++ * 8821A Regsiter offset definition
++ * ************************************************************ */
++
++/* ************************************************************
++ * MAC register
++ * ************************************************************ */
++
++/* -----------------------------------------------------
++ *	0x0000h ~ 0x00FFh	System Configuration
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
++ * ----------------------------------------------------- */
++#define REG_WOWLAN_WAKE_REASON          REG_MCUTST_WOWLAN
++
++/* -----------------------------------------------------
++ *	0x0200h ~ 0x027Fh	TXDMA Configuration
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ *	0x0280h ~ 0x02FFh	RXDMA Configuration
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ *	0x0300h ~ 0x03FFh	PCIe
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ *	0x0400h ~ 0x047Fh	Protocol Configuration
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ *	0x0500h ~ 0x05FFh	EDCA Configuration
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ *	0x0600h ~ 0x07FFh	WMAC Configuration
++ * ----------------------------------------------------- */
++
++
++/* ************************************************************
++ * SDIO Bus Specification
++ * ************************************************************ */
++
++/* -----------------------------------------------------
++ * SDIO CMD Address Mapping
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ * I/O bus domain (Host)
++ * ----------------------------------------------------- */
++
++/* -----------------------------------------------------
++ * SDIO register
++ * ----------------------------------------------------- */
++#define SDIO_REG_FREE_TXPG2		0x024
++#define SDIO_REG_HCPWM1_8821A	0x025
++
++/* ************************************************************
++ * Regsiter Bit and Content definition
++ * ************************************************************ */
++
++#endif /* __RTL8821A_SPEC_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821a_xmit.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821a_xmit.h
+new file mode 100644
+index 000000000..5d973cdc7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821a_xmit.h
+@@ -0,0 +1,173 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8821A_XMIT_H__
++#define __RTL8821A_XMIT_H__
++
++#include <drv_types.h>
++
++typedef struct txdescriptor_8821a {
++	/* Offset 0 */
++	u32 pktlen:16;
++	u32 offset:8;
++	u32 bmc:1;
++	u32 htc:1;
++	u32 rsvd0026:1;
++	u32 rsvd0027:1;
++	u32 linip:1;
++	u32 noacm:1;
++	u32 gf:1;
++	u32 rsvd0031:1;
++
++	/* Offset 4 */
++	u32 macid:7;
++	u32 rsvd0407:1;
++	u32 qsel:5;
++	u32 rdg_nav_ext:1;
++	u32 lsig_txop_en:1;
++	u32 pifs:1;
++	u32 rate_id:5;
++	u32 en_desc_id:1;
++	u32 sectype:2;
++	u32 pkt_offset:5; /* unit: 8 bytes */
++	u32 moredata:1;
++	u32 txop_ps_cap:1;
++	u32 txop_ps_mode:1;
++
++	/* Offset 8 */
++	u32 p_aid:9;
++	u32 rsvd0809:1;
++	u32 cca_rts:2;
++	u32 agg_en:1;
++	u32 rdg_en:1;
++	u32 null_0:1;
++	u32 null_1:1;
++	u32 bk:1;
++	u32 morefrag:1;
++	u32 raw:1;
++	u32 spe_rpt:1;
++	u32 ampdu_density:3;
++	u32 bt_null:1;
++	u32 g_id:6;
++	u32 rsvd0830:2;
++
++	/* Offset 12 */
++	u32 wheader_len:4;
++	u32 chk_en:1;
++	u32 early_rate:1;
++	u32 hw_ssn_sel:2;
++	u32 userate:1;
++	u32 disrtsfb:1;
++	u32 disdatafb:1;
++	u32 cts2self:1;
++	u32 rtsen:1;
++	u32 hw_rts_en:1;
++	u32 port_id:1;
++	u32 navusehdr:1;
++	u32 use_max_len:1;
++	u32 max_agg_num:5;
++	u32 ndpa:2;
++	u32 ampdu_max_time:8;
++
++	/* Offset 16 */
++	u32 datarate:7;
++	u32 try_rate:1;
++	u32 data_ratefb_lmt:5;
++	u32 rts_ratefb_lmt:4;
++	u32 rty_lmt_en:1;
++	u32 data_rt_lmt:6;
++	u32 rtsrate:5;
++	u32 pcts_en:1;
++	u32 pcts_mask_idx:2;
++
++	/* Offset 20 */
++	u32 data_sc:4;
++	u32 data_short:1;
++	u32 data_bw:2;
++	u32 data_ldpc:1;
++	u32 data_stbc:2;
++	u32 vcs_stbc:2;
++	u32 rts_short:1;
++	u32 rts_sc:4;
++	u32 rsvd2016:7;
++	u32 tx_ant:4;
++	u32 txpwr_offset:3;
++	u32 rsvd2031:1;
++
++	/* Offset 24 */
++	u32 sw_define:12;
++	u32 mbssid:4;
++	u32 antsel_A:3;
++	u32 antsel_B:3;
++	u32 antsel_C:3;
++	u32 antsel_D:3;
++	u32 rsvd2428:4;
++
++	/* Offset 28 */
++	u32 checksum:16;
++	u32 rsvd2816:8;
++	u32 usb_txagg_num:8;
++
++	/* Offset 32 */
++	u32 rts_rc:6;
++	u32 bar_rty_th:2;
++	u32 data_rc:6;
++	u32 rsvd3214:1;
++	u32 en_hwseq:1;
++	u32 nextneadpage:8;
++	u32 tailpage:8;
++
++	/* Offset 36 */
++	u32 padding_len:11;
++	u32 txbf_path:1;
++	u32 seq:12;
++	u32 final_data_rate:8;
++} TXDESC_8821A, *PTXDESC_8821A;
++
++#ifdef CONFIG_SDIO_HCI
++s32 InitXmitPriv8821AS(PADAPTER padapter);
++void FreeXmitPriv8821AS(PADAPTER padapter);
++s32 XmitBufHandler8821AS(PADAPTER padapter);
++s32 MgntXmit8821AS(PADAPTER padapter, struct xmit_frame *pmgntframe);
++s32	HalXmitNoLock8821AS(PADAPTER padapter, struct xmit_frame *pxmitframe);
++s32 HalXmit8821AS(PADAPTER padapter, struct xmit_frame *pxmitframe);
++#ifndef CONFIG_SDIO_TX_TASKLET
++thread_return XmitThread8821AS(thread_context context);
++#endif /* !CONFIG_SDIO_TX_TASKLET */
++#endif /* CONFIG_SDIO_HCI */
++
++#if 0
++#ifdef CONFIG_USB_HCI
++s32 rtl8821au_init_xmit_priv(PADAPTER padapter);
++void rtl8821au_free_xmit_priv(PADAPTER padapter);
++s32 rtl8821au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++s32 rtl8821au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++s32 rtl8821au_hal_xmitframe_enqueue(PADAPTER padapter, struct xmit_frame *pxmitframe);
++s32 rtl8821au_xmit_buf_handler(PADAPTER padapter);
++void rtl8821au_xmit_tasklet(void *priv);
++s32 rtl8821au_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++#endif /* CONFIG_USB_HCI */
++
++#ifdef CONFIG_PCI_HCI
++s32 rtl8821e_init_xmit_priv(PADAPTER padapter);
++void rtl8821e_free_xmit_priv(PADAPTER padapter);
++struct xmit_buf *rtl8821e_dequeue_xmitbuf(struct rtw_tx_ring *ring);
++void rtl8821e_xmitframe_resume(PADAPTER padapter);
++s32 rtl8821e_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
++s32 rtl8821e_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
++void rtl8821e_xmit_tasklet(void *priv);
++#endif /* CONFIG_PCI_HCI */
++#endif
++
++#endif /* __RTL8821_XMIT_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821c_dm.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821c_dm.h
+new file mode 100644
+index 000000000..b1e4fe608
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821c_dm.h
+@@ -0,0 +1,23 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8812C_DM_H__
++#define __RTL8812C_DM_H__
++
++void rtl8821c_phy_init_dm_priv(PADAPTER);
++void rtl8821c_phy_deinit_dm_priv(PADAPTER);
++void rtl8821c_phy_init_haldm(PADAPTER);
++void rtl8821c_phy_haldm_watchdog(PADAPTER);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821c_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821c_hal.h
+new file mode 100644
+index 000000000..41d222ef3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821c_hal.h
+@@ -0,0 +1,84 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8821C_HAL_H_
++#define _RTL8821C_HAL_H_
++
++#include <osdep_service.h>		/* BIT(x) */
++#include "../hal/halmac/halmac_api.h"	/* MAC REG definition */
++#include "hal_data.h"
++#include "rtl8821c_spec.h"
++#include "../hal/rtl8821c/hal8821c_fw.h"
++
++#ifdef CONFIG_USB_HCI
++#include <rtl8821cu_hal.h>
++#endif
++#ifdef CONFIG_SDIO_HCI
++#include <rtl8821cs_hal.h>
++#endif
++#ifdef CONFIG_PCI_HCI
++#include <rtl8821ce_hal.h>
++#endif
++
++#ifdef CONFIG_SUPPORT_TRX_SHARED
++#define FIFO_BLOCK_SIZE		32768 /*@Block size = 32K*/
++#define RX_FIFO_EXPANDING	(1 * FIFO_BLOCK_SIZE)
++#else
++#define RX_FIFO_EXPANDING	0
++#endif
++
++
++#if defined(CONFIG_USB_HCI)
++
++	#ifndef MAX_RECVBUF_SZ
++		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
++			/* 8821C - RX FIFO :16K ,for RX agg DMA mode = 16K, Rx agg USB mode could large than 16k*/
++			/* #define MAX_RECVBUF_SZ		(16384 + RX_FIFO_EXPANDING)*/
++			/* For Max throughput issue , need to use USB AGG mode to replace DMA AGG mode*/
++			#define MAX_RECVBUF_SZ (32768)
++
++			/*#define MAX_RECVBUF_SZ_8821C (24576)*/ /* 24k*/
++			/*#define MAX_RECVBUF_SZ_8821C (20480)*/ /*20K*/
++			/*#define MAX_RECVBUF_SZ_8821C (10240) */ /*10K*/
++			/*#define MAX_RECVBUF_SZ_8821C (15360)*/ /*15k < 16k*/
++			/*#define MAX_RECVBUF_SZ_8821C (8192+1024)*/ /* 8K+1k*/
++		#else
++			#define MAX_RECVBUF_SZ (4096 + RX_FIFO_EXPANDING) /* about 4K */
++		#endif
++	#endif/* !MAX_RECVBUF_SZ*/
++
++#elif defined(CONFIG_PCI_HCI)
++	/*#ifndef CONFIG_MINIMAL_MEMORY_USAGE
++	#define MAX_RECVBUF_SZ (9100)
++	#else*/
++	#define MAX_RECVBUF_SZ (4096 + RX_FIFO_EXPANDING) /* about 4K */
++	/*#endif*/
++
++#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	#define MAX_RECVBUF_SZ	(16384 + RX_FIFO_EXPANDING)
++#endif
++
++void init_hal_spec_rtl8821c(PADAPTER);
++/* MP Functions */
++#ifdef CONFIG_MP_INCLUDED
++void rtl8821c_prepare_mp_txdesc(PADAPTER, struct mp_priv *);	/* rtw_mp.c */
++void rtl8821c_mp_config_rfpath(PADAPTER);			/* hal_mp.c */
++#endif
++void rtl8821c_dl_rsvd_page(PADAPTER adapter, u8 mstatus);
++
++#ifdef CONFIG_PCI_HCI
++u16 get_txbd_rw_reg(u16 q_idx);
++#endif
++
++#endif /* _RTL8821C_HAL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821c_spec.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821c_spec.h
+new file mode 100644
+index 000000000..949f349b6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821c_spec.h
+@@ -0,0 +1,202 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTL8821C_SPEC_H__
++#define __RTL8821C_SPEC_H__
++
++#define EFUSE_MAP_SIZE		HALMAC_EFUSE_SIZE_8821C
++
++/*
++ * MAC Register definition
++ */
++#define REG_AFE_XTAL_CTRL			REG_AFE_CTRL1_8821C	/* hal_com.c & phydm */
++#define REG_AFE_PLL_CTRL			REG_AFE_CTRL2_8821C	/* hal_com.c & phydm */
++#define REG_MAC_PHY_CTRL			REG_AFE_CTRL3_8821C	/* phydm only */
++#define REG_LEDCFG0					REG_LED_CFG_8821C	/* rtw_mp.c */
++#define MSR							(REG_CR_8821C + 2)	/* rtw_mp.c */
++#define MSR1						REG_CR_EXT_8821C	/* rtw_mp.c & hal_com.c */
++#define REG_C2HEVT_MSG_NORMAL		0x1A0			/* hal_com.c */
++#define REG_C2HEVT_CLEAR			0x1AF			/* hal_com.c */
++#define REG_BCN_CTRL_1				REG_BCN_CTRL_CLINT0_8821C/* hal_com.c */
++
++#define REG_WOWLAN_WAKE_REASON	0x01C7
++#define REG_GPIO_PIN_CTRL_2			REG_GPIO_EXT_CTRL_8821C
++
++/* RXERR_RPT, for rtw_mp.c */
++#define RXERR_TYPE_OFDM_PPDU		0
++#define RXERR_TYPE_OFDM_FALSE_ALARM	2
++#define RXERR_TYPE_OFDM_MPDU_OK		0
++#define RXERR_TYPE_OFDM_MPDU_FAIL	1
++#define RXERR_TYPE_CCK_PPDU		3
++#define RXERR_TYPE_CCK_FALSE_ALARM	5
++#define RXERR_TYPE_CCK_MPDU_OK		3
++#define RXERR_TYPE_CCK_MPDU_FAIL	4
++#define RXERR_TYPE_HT_PPDU		8
++#define RXERR_TYPE_HT_FALSE_ALARM	9
++#define RXERR_TYPE_HT_MPDU_TOTAL	6
++#define RXERR_TYPE_HT_MPDU_OK		6
++#define RXERR_TYPE_HT_MPDU_FAIL		7
++#define RXERR_TYPE_RX_FULL_DROP		10
++
++#define RXERR_COUNTER_MASK		BIT_MASK_RPT_COUNTER_8821C
++#define RXERR_RPT_RST			BIT_RXERR_RPT_RST_8821C
++#define _RXERR_RPT_SEL(type)		(BIT_RXERR_RPT_SEL_V1_3_0_8821C(type) \
++		| ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8821C : 0))
++
++/*
++ * BB Register definition
++ */
++#define rPMAC_Reset				0x100	/* hal_mp.c */
++
++#define rFPGA0_RFMOD				0x800
++#define rFPGA0_TxInfo				0x804
++#define rOFDMCCKEN_Jaguar		0x808	/* hal_mp.c */
++#define rFPGA0_TxGainStage		0x80C	/* phydm only */
++#define rFPGA0_XA_HSSIParameter1	0x820	/* hal_mp.c */
++#define rFPGA0_XA_HSSIParameter2	0x824	/* hal_mp.c */
++#define rFPGA0_XB_HSSIParameter1	0x828	/* hal_mp.c */
++#define rFPGA0_XB_HSSIParameter2	0x82C	/* hal_mp.c */
++#define rTxAGC_B_Rate18_06		0x830
++#define rTxAGC_B_Rate54_24		0x834
++#define rTxAGC_B_CCK1_55_Mcs32	0x838
++#define rCCAonSec_Jaguar			0x838	/* hal_mp.c */
++#define rTxAGC_B_Mcs03_Mcs00		0x83C
++#define rTxAGC_B_Mcs07_Mcs04		0x848
++#define rTxAGC_B_Mcs11_Mcs08		0x84C
++#define rFPGA0_XA_RFInterfaceOE		0x860
++#define rFPGA0_XB_RFInterfaceOE		0x864
++#define rTxAGC_B_Mcs15_Mcs12		0x868
++#define rTxAGC_B_CCK11_A_CCK2_11	0x86C
++#define rFPGA0_XAB_RFInterfaceSW		0x870
++#define rFPGA0_XAB_RFParameter		0x878
++#define rFPGA0_AnalogParameter4		0x88C	/* hal_mp.c & phydm */
++#define rFPGA0_XB_LSSIReadBack		0x8A4	/* phydm */
++#define rHSSIRead_Jaguar				0x8B0	/* RF read addr (rtl8821c_phy.c) */
++
++#define	rC_TxScale_Jaguar2			0x181C  /* Pah_C TX scaling factor (hal_mp.c) */
++#define	rC_IGI_Jaguar2				0x1850	/* Initial Gain for path-C (hal_mp.c) */
++
++#define rFPGA1_TxInfo					0x90C	/* hal_mp.c */
++#define rSingleTone_ContTx_Jaguar		0x914	/* hal_mp.c */
++
++#define rCCK0_System					0xA00
++#define rCCK0_AFESetting				0xA04
++
++#define rCCK0_DSPParameter2			0xA1C
++#define rCCK0_TxFilter1				0xA20
++#define rCCK0_TxFilter2				0xA24
++#define rCCK0_DebugPort				0xA28
++#define rCCK0_FalseAlarmReport		0xA2C
++
++#define	rD_TxScale_Jaguar2			0x1A1C  /* Path_D TX scaling factor (hal_mp.c) */
++#define	rD_IGI_Jaguar2				0x1A50	/* Initial Gain for path-D (hal_mp.c) */
++
++#define rOFDM0_TRxPathEnable			0xC04
++#define rOFDM0_TRMuxPar				0xC08
++#define rA_TxScale_Jaguar				0xC1C	/* Pah_A TX scaling factor (hal_mp.c) */
++#define rOFDM0_RxDetector1			0xC30	/* rtw_mp.c */
++#define rOFDM0_ECCAThreshold			0xC4C	/* phydm only */
++#define rOFDM0_XAAGCCore1			0xC50	/* phydm only */
++#define rA_IGI_Jaguar					0xC50	/* Initial Gain for path-A (hal_mp.c) */
++#define rOFDM0_XBAGCCore1			0xC58	/* phydm only */
++#define rOFDM0_XATxIQImbalance		0xC80	/* phydm only */
++#define rA_LSSIWrite_Jaguar			0xC90	/* RF write addr, LSSI Parameter (rtl8821c_phy.c) */
++/* RFE */
++#define rA_RFE_Pinmux_Jaguar	0xCB0	/* hal_mp.c */
++#define	rB_RFE_Pinmux_Jaguar	0xEB0	/* Path_B RFE control pinmux */
++#define	rA_RFE_Inv_Jaguar		0xCB4	/* Path_A RFE cotrol */  
++#define	rB_RFE_Inv_Jaguar		0xEB4	/* Path_B RFE control */
++#define	rA_RFE_Jaguar			0xCB8 	/* Path_A RFE cotrol */  
++#define	rB_RFE_Jaguar			0xEB8	/* Path_B RFE control */
++#define	rA_RFE_Inverse_Jaguar	0xCBC	/* Path_A RFE control inverse */
++#define	rB_RFE_Inverse_Jaguar	0xEBC	/* Path_B RFE control inverse */
++#define	r_ANTSEL_SW_Jaguar		0x900	/* ANTSEL SW Control */
++#define	bMask_RFEInv_Jaguar	0x3FF00000
++#define	bMask_AntselPathFollow_Jaguar 0x00030000   
++
++#define rOFDM1_LSTF					0xD00
++#define rOFDM1_TRxPathEnable			0xD04	/* hal_mp.c */
++#define rA_PIRead_Jaguar				0xD04	/* RF readback with PI (rtl8821c_phy.c) */
++#define rA_SIRead_Jaguar				0xD08	/* RF readback with SI (rtl8821c_phy.c) */
++#define rB_PIRead_Jaguar				0xD44	/* RF readback with PI (rtl8821c_phy.c) */
++#define rB_SIRead_Jaguar				0xD48	/* RF readback with SI (rtl8821c_phy.c) */
++
++#define rTxAGC_A_Rate18_06			0xE00
++#define rTxAGC_A_Rate54_24			0xE04
++#define rTxAGC_A_CCK1_Mcs32			0xE08
++#define rTxAGC_A_Mcs03_Mcs00		0xE10
++#define rTxAGC_A_Mcs07_Mcs04		0xE14
++#define rTxAGC_A_Mcs11_Mcs08		0xE18
++#define rTxAGC_A_Mcs15_Mcs12		0xE1C
++#define rB_TxScale_Jaguar				0xE1C	/* Path_B TX scaling factor (hal_mp.c) */
++#define rB_IGI_Jaguar					0xE50	/* Initial Gain for path-B (hal_mp.c) */
++#define rB_LSSIWrite_Jaguar			0xE90	/* RF write addr, LSSI Parameter (rtl8821c_phy.c) */
++
++/* Page1(0x100) */
++#define bBBResetB					0x100
++
++/* Page8(0x800) */
++#define bCCKEn						0x1000000
++#define bOFDMEn						0x2000000
++/* Reg 0x80C rFPGA0_TxGainStage */
++#define bXBTxAGC						0xF00
++#define bXCTxAGC						0xF000
++#define bXDTxAGC						0xF0000
++
++/* PageA(0xA00) */
++#define bCCKBBMode					0x3
++
++#define bCCKScramble					0x8
++#define bCCKTxRate					0x3000
++
++/* General */
++#define bMaskByte0		0xFF		/* mp, rtw_odm.c & phydm */
++#define bMaskByte1		0xFF00		/* hal_mp.c & phydm */
++#define bMaskByte2		0xFF0000	/* hal_mp.c & phydm */
++#define bMaskByte3		0xFF000000	/* hal_mp.c & phydm */
++#define bMaskHWord		0xFFFF0000	/* hal_com.c, rtw_mp.c */
++#define bMaskLWord		0x0000FFFF	/* mp, hal_com.c & phydm */
++#define bMaskDWord		0xFFFFFFFF	/* mp, hal, rtw_odm.c & phydm */
++
++#define bEnable			0x1		/* hal_mp.c, rtw_mp.c */
++#define bDisable			0x0		/* rtw_mp.c */
++
++#define MAX_STALL_TIME		50		/* unit: us, hal_com_phycfg.c */
++
++#define Rx_Smooth_Factor		20		/* phydm only */
++
++/*
++ * RF Register definition
++ */
++#define RF_AC			0x00
++#define RF_AC_Jaguar		0x00	/* hal_mp.c */
++#define RF_CHNLBW		0x18	/* rtl8821c_phy.c */
++#define RF_0x52			0x52
++
++struct hw_port_reg {
++	u32 net_type;	/*reg_offset*/
++	u8 net_type_shift;
++	u32 macaddr;		/*reg_offset*/
++	u32 bssid;		/*reg_offset*/
++	u32 bcn_ctl;			/*reg_offset*/
++	u32 tsf_rst;			/*reg_offset*/
++	u8 tsf_rst_bit;
++	u32 bcn_space;		/*reg_offset*/
++	u8 bcn_space_shift;
++	u16 bcn_space_mask;
++	u32	ps_aid;			/*reg_offset*/
++	u32	ta;				/*reg_offset*/
++};
++
++#endif /* __RTL8192E_SPEC_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821ce_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821ce_hal.h
+new file mode 100755
+index 000000000..426002a30
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821ce_hal.h
+@@ -0,0 +1,23 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8821CE_HAL_H_
++#define _RTL8821CE_HAL_H_
++
++#include <drv_types.h>		/* PADAPTER */
++
++/* rtl8821ce_ops.c */
++void rtl8821ce_set_hal_ops(PADAPTER);
++
++#endif /* _RTL8821CE_HAL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821cs_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821cs_hal.h
+new file mode 100644
+index 000000000..ceecc15f9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821cs_hal.h
+@@ -0,0 +1,23 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8821CS_HAL_H_
++#define _RTL8821CS_HAL_H_
++
++#include <drv_types.h>		/* PADAPTER */
++
++/* rtl8821cs_ops.c */
++u8 rtl8821cs_set_hal_ops(PADAPTER);
++
++#endif /* _RTL8821CS_HAL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821cu_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821cu_hal.h
+new file mode 100644
+index 000000000..aec437224
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8821cu_hal.h
+@@ -0,0 +1,24 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8821CU_HAL_H_
++#define _RTL8821CU_HAL_H_
++
++#include <drv_types.h>		/* PADAPTER */
++
++/* rtl8821cu_ops.c */
++u8 rtl8821cu_set_hal_ops(PADAPTER);
++void rtl8821cu_set_hw_type(struct dvobj_priv *pdvobj);
++
++#endif /* _RTL8821CU_HAL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822b_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822b_hal.h
+new file mode 100644
+index 000000000..68ad97041
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822b_hal.h
+@@ -0,0 +1,234 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2015 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8822B_HAL_H_
++#define _RTL8822B_HAL_H_
++
++#include <osdep_service.h>		/* BIT(x) */
++#include <drv_types.h>			/* PADAPTER */
++#include "../hal/halmac/halmac_api.h"	/* MAC REG definition */
++
++
++#ifdef CONFIG_SUPPORT_TRX_SHARED
++#define MAX_RECVBUF_SZ		46080	/* 45KB, TX: (256-64)KB */
++#else /* !CONFIG_SUPPORT_TRX_SHARED */
++#ifdef CONFIG_PCI_HCI
++#define MAX_RECVBUF_SZ		12288	/* 12KB */
++#else
++#define MAX_RECVBUF_SZ		24576	/* 24KB, TX: 256KB */
++#endif /* !CONFIG_PCI_HCI */
++#endif /* !CONFIG_SUPPORT_TRX_SHARED */
++
++/*
++ * MAC Register definition
++ */
++#define REG_AFE_XTAL_CTRL	REG_AFE_CTRL1_8822B	/* hal_com.c & phydm */
++#define REG_AFE_PLL_CTRL	REG_AFE_CTRL2_8822B	/* hal_com.c & phydm */
++#define REG_MAC_PHY_CTRL	REG_AFE_CTRL3_8822B	/* phydm only */
++#define REG_LEDCFG0		REG_LED_CFG_8822B	/* rtw_mp.c */
++#define MSR			(REG_CR_8822B + 2)	/* rtw_mp.c & hal_com.c */
++#define MSR1			REG_CR_EXT_8822B	/* rtw_mp.c & hal_com.c */
++#define REG_C2HEVT_MSG_NORMAL	0x1A0			/* hal_com.c */
++#define REG_C2HEVT_CLEAR	0x1AF			/* hal_com.c */
++#define REG_BCN_CTRL_1		REG_BCN_CTRL_CLINT0_8822B	/* hal_com.c */
++
++#define REG_WOWLAN_WAKE_REASON	0x01C7 /* hal_com.c */
++#define REG_GPIO_PIN_CTRL_2		REG_GPIO_EXT_CTRL_8822B		/* hal_com.c */
++
++/* RXERR_RPT, for rtw_mp.c */
++#define RXERR_TYPE_OFDM_PPDU		0
++#define RXERR_TYPE_OFDM_FALSE_ALARM	2
++#define RXERR_TYPE_OFDM_MPDU_OK		0
++#define RXERR_TYPE_OFDM_MPDU_FAIL	1
++#define RXERR_TYPE_CCK_PPDU		3
++#define RXERR_TYPE_CCK_FALSE_ALARM	5
++#define RXERR_TYPE_CCK_MPDU_OK		3
++#define RXERR_TYPE_CCK_MPDU_FAIL	4
++#define RXERR_TYPE_HT_PPDU		8
++#define RXERR_TYPE_HT_FALSE_ALARM	9
++#define RXERR_TYPE_HT_MPDU_TOTAL	6
++#define RXERR_TYPE_HT_MPDU_OK		6
++#define RXERR_TYPE_HT_MPDU_FAIL		7
++#define RXERR_TYPE_RX_FULL_DROP		10
++
++#define RXERR_COUNTER_MASK		BIT_MASK_RPT_COUNTER_8822B
++#define RXERR_RPT_RST			BIT_RXERR_RPT_RST_8822B
++#define _RXERR_RPT_SEL(type)		(BIT_RXERR_RPT_SEL_V1_3_0_8822B(type) \
++					| ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8822B : 0))
++
++/*
++ * BB Register definition
++ */
++#define rPMAC_Reset			0x100	/* hal_mp.c */
++
++#define	rFPGA0_RFMOD			0x800
++#define rFPGA0_TxInfo			0x804
++#define rOFDMCCKEN_Jaguar		0x808	/* hal_mp.c */
++#define rFPGA0_TxGainStage		0x80C	/* phydm only */
++#define rFPGA0_XA_HSSIParameter1	0x820	/* hal_mp.c */
++#define rFPGA0_XA_HSSIParameter2	0x824	/* hal_mp.c */
++#define rFPGA0_XB_HSSIParameter1	0x828	/* hal_mp.c */
++#define rFPGA0_XB_HSSIParameter2	0x82C	/* hal_mp.c */
++#define rTxAGC_B_Rate18_06		0x830
++#define rTxAGC_B_Rate54_24		0x834
++#define rTxAGC_B_CCK1_55_Mcs32		0x838
++#define rCCAonSec_Jaguar		0x838	/* hal_mp.c */
++#define rTxAGC_B_Mcs03_Mcs00		0x83C
++#define rTxAGC_B_Mcs07_Mcs04		0x848
++#define rTxAGC_B_Mcs11_Mcs08		0x84C
++#define rFPGA0_XA_RFInterfaceOE		0x860
++#define rFPGA0_XB_RFInterfaceOE		0x864
++#define rTxAGC_B_Mcs15_Mcs12		0x868
++#define rTxAGC_B_CCK11_A_CCK2_11	0x86C
++#define rFPGA0_XAB_RFInterfaceSW	0x870
++#define rFPGA0_XAB_RFParameter		0x878
++#define rFPGA0_AnalogParameter4		0x88C	/* hal_mp.c & phydm */
++#define rFPGA0_XB_LSSIReadBack		0x8A4	/* phydm */
++#define rHSSIRead_Jaguar		0x8B0	/* RF read addr (rtl8822b_phy.c) */
++
++#define	rC_TxScale_Jaguar2		0x181C  /* Pah_C TX scaling factor (hal_mp.c) */
++#define	rC_IGI_Jaguar2			0x1850	/* Initial Gain for path-C (hal_mp.c) */
++
++#define rFPGA1_TxInfo			0x90C	/* hal_mp.c */
++#define rSingleTone_ContTx_Jaguar	0x914	/* hal_mp.c */
++/* TX BeamForming */
++#define REG_BB_TX_PATH_SEL_1_8822B	0x93C	/* rtl8822b_phy.c */
++#define REG_BB_TX_PATH_SEL_2_8822B	0x940	/* rtl8822b_phy.c */
++
++/* TX BeamForming */
++#define REG_BB_TXBF_ANT_SET_BF1_8822B	0x19AC	/* rtl8822b_phy.c */
++#define REG_BB_TXBF_ANT_SET_BF0_8822B	0x19B4	/* rtl8822b_phy.c */
++
++#define rCCK0_System			0xA00
++#define rCCK0_AFESetting		0xA04
++
++#define rCCK0_DSPParameter2		0xA1C
++#define rCCK0_TxFilter1			0xA20
++#define rCCK0_TxFilter2			0xA24
++#define rCCK0_DebugPort			0xA28
++#define rCCK0_FalseAlarmReport		0xA2C
++
++#define	rD_TxScale_Jaguar2		0x1A1C  /* Path_D TX scaling factor (hal_mp.c) */
++#define	rD_IGI_Jaguar2			0x1A50	/* Initial Gain for path-D (hal_mp.c) */
++
++#define rOFDM0_TRxPathEnable		0xC04
++#define rOFDM0_TRMuxPar			0xC08
++#define rA_TxScale_Jaguar		0xC1C	/* Pah_A TX scaling factor (hal_mp.c) */
++#define rOFDM0_RxDetector1		0xC30	/* rtw_mp.c */
++#define rOFDM0_ECCAThreshold		0xC4C	/* phydm only */
++#define rOFDM0_XAAGCCore1		0xC50	/* phydm only */
++#define rA_IGI_Jaguar			0xC50	/* Initial Gain for path-A (hal_mp.c) */
++#define rOFDM0_XBAGCCore1		0xC58	/* phydm only */
++#define rOFDM0_XATxIQImbalance		0xC80	/* phydm only */
++#define rA_LSSIWrite_Jaguar		0xC90	/* RF write addr, LSSI Parameter (rtl8822b_phy.c) */
++
++#define rOFDM1_LSTF			0xD00
++#define rOFDM1_TRxPathEnable		0xD04	/* hal_mp.c */
++#define rA_PIRead_Jaguar		0xD04	/* RF readback with PI (rtl8822b_phy.c) */
++#define rA_SIRead_Jaguar		0xD08	/* RF readback with SI (rtl8822b_phy.c) */
++#define rB_PIRead_Jaguar		0xD44	/* RF readback with PI (rtl8822b_phy.c) */
++#define rB_SIRead_Jaguar		0xD48	/* RF readback with SI (rtl8822b_phy.c) */
++
++#define rTxAGC_A_Rate18_06		0xE00
++#define rTxAGC_A_Rate54_24		0xE04
++#define rTxAGC_A_CCK1_Mcs32		0xE08
++#define rTxAGC_A_Mcs03_Mcs00		0xE10
++#define rTxAGC_A_Mcs07_Mcs04		0xE14
++#define rTxAGC_A_Mcs11_Mcs08		0xE18
++#define rTxAGC_A_Mcs15_Mcs12		0xE1C
++#define rB_TxScale_Jaguar		0xE1C	/* Path_B TX scaling factor (hal_mp.c) */
++#define rB_IGI_Jaguar			0xE50	/* Initial Gain for path-B (hal_mp.c) */
++#define rB_LSSIWrite_Jaguar		0xE90	/* RF write addr, LSSI Parameter (rtl8822b_phy.c) */
++/* RFE */
++#define rA_RFE_Pinmux_Jaguar	0xCB0	/* hal_mp.c */
++#define	rB_RFE_Pinmux_Jaguar	0xEB0	/* Path_B RFE control pinmux */
++#define	rA_RFE_Inv_Jaguar		0xCB4	/* Path_A RFE cotrol */  
++#define	rB_RFE_Inv_Jaguar		0xEB4	/* Path_B RFE control */
++#define	rA_RFE_Jaguar			0xCB8 	/* Path_A RFE cotrol */  
++#define	rB_RFE_Jaguar			0xEB8	/* Path_B RFE control */
++#define	rA_RFE_Inverse_Jaguar	0xCBC	/* Path_A RFE control inverse */
++#define	rB_RFE_Inverse_Jaguar	0xEBC	/* Path_B RFE control inverse */
++#define	r_ANTSEL_SW_Jaguar		0x900	/* ANTSEL SW Control */
++#define	bMask_RFEInv_Jaguar	0x3FF00000
++#define	bMask_AntselPathFollow_Jaguar 0x00030000
++
++#define		rC_RFE_Pinmux_Jaguar	0x18B4	/* Path_C RFE cotrol pinmux*/
++#define		rD_RFE_Pinmux_Jaguar	0x1AB4	/* Path_D RFE cotrol pinmux*/
++#define		rA_RFE_Sel_Jaguar2		0x1990
++
++/* Page1(0x100) */
++#define bBBResetB			0x100
++
++/* Page8(0x800) */
++#define bCCKEn				0x1000000
++#define bOFDMEn				0x2000000
++/* Reg 0x80C rFPGA0_TxGainStage */
++#define bXBTxAGC			0xF00
++#define bXCTxAGC			0xF000
++#define bXDTxAGC			0xF0000
++
++/* PageA(0xA00) */
++#define bCCKBBMode			0x3
++
++#define bCCKScramble			0x8
++#define bCCKTxRate			0x3000
++
++/* General */
++#define bMaskByte0		0xFF		/* mp, rtw_odm.c & phydm */
++#define bMaskByte1		0xFF00		/* hal_mp.c & phydm */
++#define bMaskByte2		0xFF0000	/* hal_mp.c & phydm */
++#define bMaskByte3		0xFF000000	/* hal_mp.c & phydm */
++#define bMaskHWord		0xFFFF0000	/* hal_com.c, rtw_mp.c */
++#define bMaskLWord		0x0000FFFF	/* mp, hal_com.c & phydm */
++#define bMaskDWord		0xFFFFFFFF	/* mp, hal, rtw_odm.c & phydm */
++
++#define bEnable			0x1		/* hal_mp.c, rtw_mp.c */
++#define bDisable		0x0		/* rtw_mp.c */
++
++#define MAX_STALL_TIME		50		/* unit: us, hal_com_phycfg.c */
++
++#define Rx_Smooth_Factor	20		/* phydm only */
++
++/*
++ * RF Register definition
++ */
++#define RF_AC			0x00
++#define RF_AC_Jaguar		0x00	/* hal_mp.c */
++#define RF_CHNLBW		0x18	/* rtl8822b_phy.c */
++#define RF_ModeTableAddr	0x30	/* rtl8822b_phy.c */
++#define RF_ModeTableData0	0x31	/* rtl8822b_phy.c */
++#define RF_ModeTableData1	0x32	/* rtl8822b_phy.c */
++#define RF_0x52			0x52
++#define RF_WeLut_Jaguar		0xEF	/* rtl8822b_phy.c */
++
++/* General Functions */
++void rtl8822b_init_hal_spec(PADAPTER);				/* hal/hal_com.c */
++
++#ifdef CONFIG_MP_INCLUDED
++/* MP Functions */
++#include <rtw_mp.h>		/* struct mp_priv */
++void rtl8822b_prepare_mp_txdesc(PADAPTER, struct mp_priv *);	/* rtw_mp.c */
++void rtl8822b_mp_config_rfpath(PADAPTER);			/* hal_mp.c */
++#endif
++void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus);
++
++#ifdef CONFIG_USB_HCI
++#include <rtl8822bu_hal.h>
++#elif defined(CONFIG_SDIO_HCI)
++#include <rtl8822bs_hal.h>
++#elif defined(CONFIG_PCI_HCI)
++#include <rtl8822be_hal.h>
++#endif
++
++#endif /* _RTL8822B_HAL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822be_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822be_hal.h
+new file mode 100755
+index 000000000..a81445fa1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822be_hal.h
+@@ -0,0 +1,27 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2015 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8822BE_HAL_H_
++#define _RTL8822BE_HAL_H_
++
++#include <drv_types.h>		/* PADAPTER */
++
++#define RT_BCN_INT_MASKS	(BIT20 | BIT25 | BIT26 | BIT16)
++
++/* rtl8822be_ops.c */
++void UpdateInterruptMask8822BE(PADAPTER, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
++u16 get_txbd_rw_reg(u16 q_idx);
++
++
++#endif /* _RTL8822BE_HAL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822bs_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822bs_hal.h
+new file mode 100644
+index 000000000..ffaddee09
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822bs_hal.h
+@@ -0,0 +1,31 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2015 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8822BS_HAL_H_
++#define _RTL8822BS_HAL_H_
++
++#include <drv_types.h>		/* PADAPTER */
++
++/* rtl8822bs_ops.c */
++void rtl8822bs_set_hal_ops(PADAPTER);
++
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++void rtl8822bs_disable_interrupt_but_cpwm2(PADAPTER adapter);
++#endif
++
++/* rtl8822bs_xmit.c */
++s32 rtl8822bs_dequeue_writeport(PADAPTER);
++#define _dequeue_writeport(a)	rtl8822bs_dequeue_writeport(a)
++
++#endif /* _RTL8822BS_HAL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822bu_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822bu_hal.h
+new file mode 100644
+index 000000000..a35773f12
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822bu_hal.h
+@@ -0,0 +1,61 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2015 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8822BU_HAL_H_
++#define _RTL8822BU_HAL_H_
++
++#ifdef CONFIG_USB_HCI
++	#include <drv_types.h>		/* PADAPTER */
++
++	#ifdef CONFIG_USB_HCI
++		#ifdef USB_PACKET_OFFSET_SZ
++			#define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ)
++		#else
++			#define PACKET_OFFSET_SZ (8)
++		#endif
++		#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)
++	#endif
++
++	/* undefine MAX_RECVBUF_SZ from rtl8822b_hal.h  */
++	#ifdef MAX_RECVBUF_SZ
++		#undef MAX_RECVBUF_SZ
++	#endif
++
++	/* recv_buffer must be large than usb agg size */
++	#ifndef MAX_RECVBUF_SZ
++		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
++			#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
++				#define MAX_RECVBUF_SZ (15360) /* 15k */
++				#elif defined(CONFIG_PLATFORM_HISILICON)
++				/* use 16k to workaround for HISILICON platform */
++				#define MAX_RECVBUF_SZ (16384)
++			#else
++				#define MAX_RECVBUF_SZ (32768)
++			#endif
++		#else
++			#define MAX_RECVBUF_SZ (4000)
++		#endif
++	#endif /* !MAX_RECVBUF_SZ */
++
++	/* rtl8822bu_ops.c */
++	void rtl8822bu_set_hal_ops(PADAPTER padapter);
++	void rtl8822bu_set_hw_type(struct dvobj_priv *pdvobj);
++
++	/* rtl8822bu_io.c */
++	void rtl8822bu_set_intf_ops(struct _io_ops *pops);
++
++#endif /* CONFIG_USB_HCI */
++
++
++#endif /* _RTL8822BU_HAL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822c_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822c_hal.h
+new file mode 100755
+index 000000000..0230d934f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822c_hal.h
+@@ -0,0 +1,246 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2015 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8822C_HAL_H_
++#define _RTL8822C_HAL_H_
++
++#include <osdep_service.h>		/* BIT(x) */
++#include <drv_types.h>			/* PADAPTER */
++#include "../hal/halmac/halmac_api.h"	/* MAC REG definition */
++
++#ifdef CONFIG_SUPPORT_TRX_SHARED
++#define DEF_RECVBUF_SZ		24576	/* RX 24K */
++#if (DFT_TRX_SHARE_MODE == 1)
++#define RX_FIFO_EXPANDING 40960	/* RX= 24K+40K=64K , TX=256K-40K=216K */
++#elif (DFT_TRX_SHARE_MODE == 2)
++#define RX_FIFO_EXPANDING 65536	/* RX= 24K+40K+24=88K , TX=256K-40K-24K=192K */
++#elif (DFT_TRX_SHARE_MODE ==3)
++#define RX_FIFO_EXPANDING 106496	/* RX= 24K+40K+24+40K=128K , TX=256K-40K-24K-40K=152K */
++#elif (DFT_TRX_SHARE_MODE ==4)
++#define RX_FIFO_EXPANDING 131072	/* RX= 24K+40K+24+40K+24K=128K , TX=256K-40K-24K-40K-24K=128K */
++#else
++#define RX_FIFO_EXPANDING 0
++#endif
++#define MAX_RECVBUF_SZ	(DEF_RECVBUF_SZ + RX_FIFO_EXPANDING)	
++#else /* !CONFIG_SUPPORT_TRX_SHARED */
++#ifdef CONFIG_PCI_HCI
++#define MAX_RECVBUF_SZ		12288	/* 12KB */
++#else
++#define MAX_RECVBUF_SZ		24576	/* 24KB, TX: 256KB */
++#endif /* !CONFIG_PCI_HCI */
++#endif /* !CONFIG_SUPPORT_TRX_SHARED */
++
++/*
++ * MAC Register definition
++ */
++#define REG_AFE_XTAL_CTRL	REG_AFE_CTRL1_8822C	/* hal_com.c & phydm */
++#define REG_LEDCFG0		REG_LED_CFG_8822C	/* rtw_mp.c */
++#define MSR			(REG_CR_8822C + 2)	/* rtw_mp.c & hal_com.c */
++#define MSR1			REG_CR_EXT_8822C	/* rtw_mp.c & hal_com.c */
++#define REG_C2HEVT_MSG_NORMAL	0x1A0			/* hal_com.c */
++#define REG_C2HEVT_CLEAR	0x1AF			/* hal_com.c */
++#define REG_BCN_CTRL_1		REG_BCN_CTRL_CLINT0_8822C	/* hal_com.c */
++
++#define REG_WOWLAN_WAKE_REASON	0x01C7 /* hal_com.c */
++#define REG_GPIO_PIN_CTRL_2		REG_GPIO_EXT_CTRL_8822C		/* hal_com.c */
++
++/* RXERR_RPT, for rtw_mp.c */
++#define RXERR_TYPE_OFDM_PPDU		0
++#define RXERR_TYPE_OFDM_FALSE_ALARM	2
++#define RXERR_TYPE_OFDM_MPDU_OK		0
++#define RXERR_TYPE_OFDM_MPDU_FAIL	1
++#define RXERR_TYPE_CCK_PPDU		3
++#define RXERR_TYPE_CCK_FALSE_ALARM	5
++#define RXERR_TYPE_CCK_MPDU_OK		3
++#define RXERR_TYPE_CCK_MPDU_FAIL	4
++#define RXERR_TYPE_HT_PPDU		8
++#define RXERR_TYPE_HT_FALSE_ALARM	9
++#define RXERR_TYPE_HT_MPDU_TOTAL	6
++#define RXERR_TYPE_HT_MPDU_OK		6
++#define RXERR_TYPE_HT_MPDU_FAIL		7
++#define RXERR_TYPE_RX_FULL_DROP		10
++
++#define RXERR_COUNTER_MASK		BIT_MASK_RPT_COUNTER_8822C
++#define RXERR_RPT_RST			BIT_RXERR_RPT_RST_8822C
++#define _RXERR_RPT_SEL(type)		(BIT_RXERR_RPT_SEL_V1_3_0_8822C(type) \
++					| ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8822C : 0))
++
++/*
++ * BB Register definition
++ */
++#define rPMAC_Reset			0x100	/* hal_mp.c */
++
++#define	rFPGA0_RFMOD			0x800
++#define rFPGA0_TxInfo			0x804
++#define rOFDMCCKEN_Jaguar		0x808	/* hal_mp.c */
++#define rFPGA0_TxGainStage		0x80C	/* phydm only */
++#define rFPGA0_XA_HSSIParameter1	0x820	/* hal_mp.c */
++#define rFPGA0_XA_HSSIParameter2	0x824	/* hal_mp.c */
++#define rFPGA0_XB_HSSIParameter1	0x828	/* hal_mp.c */
++#define rFPGA0_XB_HSSIParameter2	0x82C	/* hal_mp.c */
++#define rTxAGC_B_Rate18_06		0x830
++#define rTxAGC_B_Rate54_24		0x834
++#define rTxAGC_B_CCK1_55_Mcs32		0x838
++#define rCCAonSec_Jaguar		0x838	/* hal_mp.c */
++#define rTxAGC_B_Mcs03_Mcs00		0x83C
++#define rTxAGC_B_Mcs07_Mcs04		0x848
++#define rTxAGC_B_Mcs11_Mcs08		0x84C
++#define rFPGA0_XA_RFInterfaceOE		0x860
++#define rFPGA0_XB_RFInterfaceOE		0x864
++#define rTxAGC_B_Mcs15_Mcs12		0x868
++#define rTxAGC_B_CCK11_A_CCK2_11	0x86C
++#define rFPGA0_XAB_RFInterfaceSW	0x870
++#define rFPGA0_XAB_RFParameter		0x878
++#define rFPGA0_AnalogParameter4		0x88C	/* hal_mp.c & phydm */
++#define rFPGA0_XB_LSSIReadBack		0x8A4	/* phydm */
++#define rHSSIRead_Jaguar		0x8B0	/* RF read addr (rtl8822c_phy.c) */
++
++#define	rC_TxScale_Jaguar2		0x181C  /* Pah_C TX scaling factor (hal_mp.c) */
++#define	rC_IGI_Jaguar2			0x1850	/* Initial Gain for path-C (hal_mp.c) */
++
++#define rFPGA1_TxInfo			0x90C	/* hal_mp.c */
++#define rSingleTone_ContTx_Jaguar	0x914	/* hal_mp.c */
++/* TX BeamForming */
++#define REG_BB_TX_PATH_SEL_1_8822C	0x93C	/* rtl8822c_phy.c */
++#define REG_BB_TX_PATH_SEL_2_8822C	0x940	/* rtl8822c_phy.c */
++
++/* TX BeamForming */
++#define REG_BB_TXBF_ANT_SET_BF1_8822C	0x19AC	/* rtl8822c_phy.c */
++#define REG_BB_TXBF_ANT_SET_BF0_8822C	0x19B4	/* rtl8822c_phy.c */
++
++#define rCCK0_System			0xA00
++#define rCCK0_AFESetting		0xA04
++
++#define rCCK0_DSPParameter2		0xA1C
++#define rCCK0_TxFilter1			0xA20
++#define rCCK0_TxFilter2			0xA24
++#define rCCK0_DebugPort			0xA28
++#define rCCK0_FalseAlarmReport		0xA2C
++
++#define	rD_TxScale_Jaguar2		0x1A1C  /* Path_D TX scaling factor (hal_mp.c) */
++#define	rD_IGI_Jaguar2			0x1A50	/* Initial Gain for path-D (hal_mp.c) */
++
++#define rOFDM0_TRxPathEnable		0xC04
++#define rOFDM0_TRMuxPar			0xC08
++#define rA_TxScale_Jaguar		0xC1C	/* Pah_A TX scaling factor (hal_mp.c) */
++#define rOFDM0_RxDetector1		0xC30	/* rtw_mp.c */
++#define rOFDM0_ECCAThreshold		0xC4C	/* phydm only */
++#define rOFDM0_XAAGCCore1		0xC50	/* phydm only */
++#define rA_IGI_Jaguar			0xC50	/* Initial Gain for path-A (hal_mp.c) */
++#define rOFDM0_XBAGCCore1		0xC58	/* phydm only */
++#define rOFDM0_XATxIQImbalance		0xC80	/* phydm only */
++#define rA_LSSIWrite_Jaguar		0xC90	/* RF write addr, LSSI Parameter (rtl8822b_phy.c) */
++
++#define rOFDM1_LSTF			0xD00
++#define rOFDM1_TRxPathEnable		0xD04	/* hal_mp.c */
++#define rA_PIRead_Jaguar		0xD04	/* RF readback with PI (rtl8822c_phy.c) */
++#define rA_SIRead_Jaguar		0xD08	/* RF readback with SI (rtl8822c_phy.c) */
++#define rB_PIRead_Jaguar		0xD44	/* RF readback with PI (rtl8822c_phy.c) */
++#define rB_SIRead_Jaguar		0xD48	/* RF readback with SI (rtl8822c_phy.c) */
++
++#define rTxAGC_A_Rate18_06		0xE00
++#define rTxAGC_A_Rate54_24		0xE04
++#define rTxAGC_A_CCK1_Mcs32		0xE08
++#define rTxAGC_A_Mcs03_Mcs00		0xE10
++#define rTxAGC_A_Mcs07_Mcs04		0xE14
++#define rTxAGC_A_Mcs11_Mcs08		0xE18
++#define rTxAGC_A_Mcs15_Mcs12		0xE1C
++#define rB_TxScale_Jaguar		0xE1C	/* Path_B TX scaling factor (hal_mp.c) */
++#define rB_IGI_Jaguar			0xE50	/* Initial Gain for path-B (hal_mp.c) */
++#define rB_LSSIWrite_Jaguar		0xE90	/* RF write addr, LSSI Parameter (rtl8822b_phy.c) */
++/* RFE */
++#define rA_RFE_Pinmux_Jaguar	0xCB0	/* hal_mp.c */
++#define	rB_RFE_Pinmux_Jaguar	0xEB0	/* Path_B RFE control pinmux */
++#define	rA_RFE_Inv_Jaguar		0xCB4	/* Path_A RFE cotrol */  
++#define	rB_RFE_Inv_Jaguar		0xEB4	/* Path_B RFE control */
++#define	rA_RFE_Jaguar			0xCB8 	/* Path_A RFE cotrol */  
++#define	rB_RFE_Jaguar			0xEB8	/* Path_B RFE control */
++#define	rA_RFE_Inverse_Jaguar	0xCBC	/* Path_A RFE control inverse */
++#define	rB_RFE_Inverse_Jaguar	0xEBC	/* Path_B RFE control inverse */
++#define	r_ANTSEL_SW_Jaguar		0x900	/* ANTSEL SW Control */
++#define	bMask_RFEInv_Jaguar	0x3FF00000
++#define	bMask_AntselPathFollow_Jaguar 0x00030000
++
++#define		rC_RFE_Pinmux_Jaguar	0x18B4	/* Path_C RFE cotrol pinmux*/
++#define		rD_RFE_Pinmux_Jaguar	0x1AB4	/* Path_D RFE cotrol pinmux*/
++#define		rA_RFE_Sel_Jaguar2		0x1990
++
++/* Page1(0x100) */
++#define bBBResetB			0x100
++
++/* Page8(0x800) */
++#define bCCKEn				0x1000000
++#define bOFDMEn				0x2000000
++/* Reg 0x80C rFPGA0_TxGainStage */
++#define bXBTxAGC			0xF00
++#define bXCTxAGC			0xF000
++#define bXDTxAGC			0xF0000
++
++/* PageA(0xA00) */
++#define bCCKBBMode			0x3
++
++#define bCCKScramble			0x8
++#define bCCKTxRate			0x3000
++
++/* General */
++#define bMaskByte0		0xFF		/* mp, rtw_odm.c & phydm */
++#define bMaskByte1		0xFF00		/* hal_mp.c & phydm */
++#define bMaskByte2		0xFF0000	/* hal_mp.c & phydm */
++#define bMaskByte3		0xFF000000	/* hal_mp.c & phydm */
++#define bMaskHWord		0xFFFF0000	/* hal_com.c, rtw_mp.c */
++#define bMaskLWord		0x0000FFFF	/* mp, hal_com.c & phydm */
++#define bMaskDWord		0xFFFFFFFF	/* mp, hal, rtw_odm.c & phydm */
++
++#define bEnable			0x1		/* hal_mp.c, rtw_mp.c */
++#define bDisable		0x0		/* rtw_mp.c */
++
++#define MAX_STALL_TIME		50		/* unit: us, hal_com_phycfg.c */
++
++#define Rx_Smooth_Factor	20		/* phydm only */
++
++/*
++ * RF Register definition
++ */
++#define RF_AC			0x00
++#define RF_AC_Jaguar		0x00	/* hal_mp.c */
++#define RF_CHNLBW		0x18	/* rtl8822c_phy.c */
++#define RF_ModeTableAddr	0x30	/* rtl8822c_phy.c */
++#define RF_ModeTableData0	0x31	/* rtl8822c_phy.c */
++#define RF_ModeTableData1	0x32	/* rtl8822c_phy.c */
++#define RF_0x52			0x52
++#define RF_WeLut_Jaguar		0xEF	/* rtl8822c_phy.c */
++
++/* rtw_lps_state_chk()@hal_com.c */
++#define BIT_PWRBIT_OW_EN	BIT_WMAC_TCRPWRMGT_HWDATA_EN_8822C 
++
++/* General Functions */
++void rtl8822c_init_hal_spec(PADAPTER);				/* hal/hal_com.c */
++
++#ifdef CONFIG_MP_INCLUDED
++/* MP Functions */
++#include <rtw_mp.h>		/* struct mp_priv */
++void rtl8822c_prepare_mp_txdesc(PADAPTER, struct mp_priv *);	/* rtw_mp.c */
++void rtl8822c_mp_config_rfpath(PADAPTER);			/* hal_mp.c */
++#endif
++void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus);
++
++#ifdef CONFIG_USB_HCI
++#include <rtl8822cu_hal.h>
++#elif defined(CONFIG_SDIO_HCI)
++#include <rtl8822cs_hal.h>
++#elif defined(CONFIG_PCI_HCI)
++#include <rtl8822ce_hal.h>
++#endif
++
++#endif /* _RTL8822C_HAL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822ce_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822ce_hal.h
+new file mode 100755
+index 000000000..f56566e05
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822ce_hal.h
+@@ -0,0 +1,27 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2015 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8822CE_HAL_H_
++#define _RTL8822CE_HAL_H_
++
++#include <drv_types.h>		/* PADAPTER */
++
++#define RT_BCN_INT_MASKS	(BIT20 | BIT25 | BIT26 | BIT16)
++
++/* rtl8822ce_ops.c */
++void UpdateInterruptMask8822CE(PADAPTER, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
++u16 get_txbd_rw_reg(u16 q_idx);
++
++
++#endif /* _RTL8822CE_HAL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822cs_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822cs_hal.h
+new file mode 100755
+index 000000000..3e54b2a65
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822cs_hal.h
+@@ -0,0 +1,31 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2015 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8822CS_HAL_H_
++#define _RTL8822CS_HAL_H_
++
++#include <drv_types.h>		/* PADAPTER */
++
++/* rtl8822cs_ops.c */
++void rtl8822cs_set_hal_ops(PADAPTER);
++
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++void rtl8822cs_disable_interrupt_but_cpwm2(PADAPTER adapter);
++#endif
++
++/* rtl8822cs_xmit.c */
++s32 rtl8822cs_dequeue_writeport(PADAPTER);
++#define _dequeue_writeport(a)	rtl8822cs_dequeue_writeport(a)
++
++#endif /* _RTL8822CS_HAL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822cu_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822cu_hal.h
+new file mode 100755
+index 000000000..ba2e36e56
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtl8822cu_hal.h
+@@ -0,0 +1,61 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2015 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL8822CU_HAL_H_
++#define _RTL8822CU_HAL_H_
++
++#ifdef CONFIG_USB_HCI
++	#include <drv_types.h>		/* PADAPTER */
++
++	#ifdef CONFIG_USB_HCI
++		#ifdef USB_PACKET_OFFSET_SZ
++			#define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ)
++		#else
++			#define PACKET_OFFSET_SZ (8)
++		#endif
++		#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)
++	#endif
++
++	/* undefine MAX_RECVBUF_SZ from rtl8822c_hal.h  */
++	#ifdef MAX_RECVBUF_SZ
++		#undef MAX_RECVBUF_SZ
++	#endif
++
++	/* recv_buffer must be large than usb agg size */
++	#ifndef MAX_RECVBUF_SZ
++		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
++			#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
++				#define MAX_RECVBUF_SZ (15360) /* 15k */
++				#elif defined(CONFIG_PLATFORM_HISILICON)
++				/* use 16k to workaround for HISILICON platform */
++				#define MAX_RECVBUF_SZ (16384)
++			#else
++				#define MAX_RECVBUF_SZ (32768)
++			#endif
++		#else
++			#define MAX_RECVBUF_SZ (4000)
++		#endif
++	#endif /* !MAX_RECVBUF_SZ */
++
++	/* rtl8822cu_ops.c */
++	void rtl8822cu_set_hal_ops(PADAPTER padapter);
++	void rtl8822cu_set_hw_type(struct dvobj_priv *pdvobj);
++
++	/* rtl8822cu_io.c */
++	void rtl8822cu_set_intf_ops(struct _io_ops *pops);
++
++#endif /* CONFIG_USB_HCI */
++
++
++#endif /* _RTL8822CU_HAL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_android.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_android.h
+new file mode 100644
+index 000000000..9bb8e32f5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_android.h
+@@ -0,0 +1,117 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __RTW_ANDROID_H__
++#define __RTW_ANDROID_H__
++
++enum ANDROID_WIFI_CMD {
++	ANDROID_WIFI_CMD_START,
++	ANDROID_WIFI_CMD_STOP,
++	ANDROID_WIFI_CMD_SCAN_ACTIVE,
++	ANDROID_WIFI_CMD_SCAN_PASSIVE,
++	ANDROID_WIFI_CMD_RSSI,
++	ANDROID_WIFI_CMD_LINKSPEED,
++	ANDROID_WIFI_CMD_RXFILTER_START,
++	ANDROID_WIFI_CMD_RXFILTER_STOP,
++	ANDROID_WIFI_CMD_RXFILTER_ADD,
++	ANDROID_WIFI_CMD_RXFILTER_REMOVE,
++	ANDROID_WIFI_CMD_BTCOEXSCAN_START,
++	ANDROID_WIFI_CMD_BTCOEXSCAN_STOP,
++	ANDROID_WIFI_CMD_BTCOEXMODE,
++	ANDROID_WIFI_CMD_SETSUSPENDMODE,
++	ANDROID_WIFI_CMD_SETSUSPENDOPT,
++	ANDROID_WIFI_CMD_P2P_DEV_ADDR,
++	ANDROID_WIFI_CMD_SETFWPATH,
++	ANDROID_WIFI_CMD_SETBAND,
++	ANDROID_WIFI_CMD_GETBAND,
++	ANDROID_WIFI_CMD_COUNTRY,
++	ANDROID_WIFI_CMD_P2P_SET_NOA,
++	ANDROID_WIFI_CMD_P2P_GET_NOA,
++	ANDROID_WIFI_CMD_P2P_SET_PS,
++	ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE,
++
++	ANDROID_WIFI_CMD_MIRACAST,
++
++#ifdef CONFIG_PNO_SUPPORT
++	ANDROID_WIFI_CMD_PNOSSIDCLR_SET,
++	ANDROID_WIFI_CMD_PNOSETUP_SET,
++	ANDROID_WIFI_CMD_PNOENABLE_SET,
++	ANDROID_WIFI_CMD_PNODEBUG_SET,
++#endif
++
++	ANDROID_WIFI_CMD_MACADDR,
++
++	ANDROID_WIFI_CMD_BLOCK_SCAN,
++	ANDROID_WIFI_CMD_BLOCK,
++
++	ANDROID_WIFI_CMD_WFD_ENABLE,
++	ANDROID_WIFI_CMD_WFD_DISABLE,
++
++	ANDROID_WIFI_CMD_WFD_SET_TCPPORT,
++	ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT,
++	ANDROID_WIFI_CMD_WFD_SET_DEVTYPE,
++	ANDROID_WIFI_CMD_CHANGE_DTIM,
++	ANDROID_WIFI_CMD_HOSTAPD_SET_MACADDR_ACL,
++	ANDROID_WIFI_CMD_HOSTAPD_ACL_ADD_STA,
++	ANDROID_WIFI_CMD_HOSTAPD_ACL_REMOVE_STA,
++#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))
++	ANDROID_WIFI_CMD_GTK_REKEY_OFFLOAD,
++#endif /* CONFIG_GTK_OL */
++	ANDROID_WIFI_CMD_P2P_DISABLE,
++	ANDROID_WIFI_CMD_SET_AEK,
++	ANDROID_WIFI_CMD_EXT_AUTH_STATUS,
++	ANDROID_WIFI_CMD_DRIVERVERSION,
++	ANDROID_WIFI_CMD_MAX
++};
++
++int rtw_android_cmdstr_to_num(char *cmdstr);
++int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd);
++
++#if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++int rtw_android_pno_enable(struct net_device *net, int pno_enable);
++int rtw_android_cfg80211_pno_setup(struct net_device *net,
++		   struct cfg80211_ssid *ssid, int n_ssids, int interval);
++#endif
++
++#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC)
++int rtw_android_wifictrl_func_add(void);
++void rtw_android_wifictrl_func_del(void);
++void *wl_android_prealloc(int section, unsigned long size);
++
++int wifi_get_irq_number(unsigned long *irq_flags_ptr);
++int wifi_set_power(int on, unsigned long msec);
++int wifi_get_mac_addr(unsigned char *buf);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
++void *wifi_get_country_code(char *ccode, u32 flags);
++#else /* Linux kernel < 3.18 */
++void *wifi_get_country_code(char *ccode);
++#endif /* Linux kernel < 3.18 */
++#else
++static inline int rtw_android_wifictrl_func_add(void)
++{
++	return 0;
++}
++static inline void rtw_android_wifictrl_func_del(void) {}
++#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */
++
++#ifdef CONFIG_GPIO_WAKEUP
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++int wifi_configure_gpio(void);
++#endif /* CONFIG_PLATFORM_INTEL_BYT */
++void wifi_free_gpio(unsigned int gpio);
++#endif /* CONFIG_GPIO_WAKEUP */
++
++
++#endif /* __RTW_ANDROID_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ap.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ap.h
+new file mode 100644
+index 000000000..ae272e6eb
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ap.h
+@@ -0,0 +1,143 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_AP_H_
++#define __RTW_AP_H_
++
++
++#ifdef CONFIG_AP_MODE
++
++/* external function */
++extern void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta);
++extern void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta);
++
++
++void init_mlme_ap_info(_adapter *padapter);
++void free_mlme_ap_info(_adapter *padapter);
++u8 rtw_set_tim_ie(u8 dtim_cnt, u8 dtim_period
++	, const u8 *tim_bmp, u8 tim_bmp_len, u8 *tim_ie);
++/* void update_BCNTIM(_adapter *padapter); */
++void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len);
++void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index);
++void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, u8 flags, const char *tag);
++#define update_beacon(adapter, ie_id, oui, tx, flags) _update_beacon((adapter), (ie_id), (oui), (tx), (flags), __func__)
++/*update_beacon - (flags) can set to normal enqueue (0) and RTW_CMDF_WAIT_ACK enqueue. 
++ (flags) = RTW_CMDF_DIRECTLY  is not currently implemented, it will do normal enqueue.*/
++
++void rtw_ap_update_sta_ra_info(_adapter *padapter, struct sta_info *psta);
++
++void expire_timeout_chk(_adapter *padapter);
++void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta);
++void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter);
++void start_bss_network(_adapter *padapter, struct createbss_parm *parm);
++int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf,  int len);
++void rtw_ap_restore_network(_adapter *padapter);
++
++#if CONFIG_RTW_MACADDR_ACL
++void rtw_macaddr_acl_init(_adapter *adapter, u8 period);
++void rtw_macaddr_acl_deinit(_adapter *adapter, u8 period);
++void rtw_macaddr_acl_clear(_adapter *adapter, u8 period);
++void rtw_set_macaddr_acl(_adapter *adapter, u8 period, int mode);
++int rtw_acl_add_sta(_adapter *adapter, u8 period, const u8 *addr);
++int rtw_acl_remove_sta(_adapter *adapter, u8 period, const u8 *addr);
++#endif /* CONFIG_RTW_MACADDR_ACL */
++
++u8 rtw_ap_set_sta_key(_adapter *adapter, const u8 *addr, u8 alg, const u8 *key, u8 keyid, u8 gk);
++u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta);
++int rtw_ap_set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid);
++int rtw_ap_set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid, u8 set_tx);
++
++#ifdef CONFIG_NATIVEAP_MLME
++void associated_clients_update(_adapter *padapter, u8 updated, u32 sta_info_type);
++void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta);
++u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta);
++void sta_info_update(_adapter *padapter, struct sta_info *psta);
++void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta);
++u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue);
++int rtw_sta_flush(_adapter *padapter, bool enqueue);
++int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset);
++void start_ap_mode(_adapter *padapter);
++void stop_ap_mode(_adapter *padapter);
++#endif
++
++void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset);
++u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp
++	, s16 req_ch, s8 req_bw, s8 req_offset, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow);
++
++#ifdef CONFIG_AUTO_AP_MODE
++void rtw_auto_ap_rx_msg_dump(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_pos);
++extern void rtw_start_auto_ap(_adapter *adapter);
++#endif /* CONFIG_AUTO_AP_MODE */
++
++void rtw_ap_parse_sta_capability(_adapter *adapter, struct sta_info *sta, u8 *cap);
++u16 rtw_ap_parse_sta_supported_rates(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len);
++u16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems);
++void rtw_ap_parse_sta_wmm_ie(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len);
++void rtw_ap_parse_sta_ht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems);
++void rtw_ap_parse_sta_vht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems);
++void rtw_ap_parse_sta_multi_ap_ie(_adapter *adapter, struct sta_info *sta, u8 *ies, int ies_len);
++
++/* b2u flags */
++#define RTW_AP_B2U_ALL		BIT0
++#define RTW_AP_B2U_GA_UCAST	BIT1 /* WDS group addressed unicast frame, forward only */
++#define RTW_AP_B2U_BCAST	BIT2
++#define RTW_AP_B2U_IP_MCAST	BIT3
++
++#define rtw_ap_src_b2u_policy_chk(flags, da) ( \
++	(flags & RTW_AP_B2U_ALL) \
++	|| ((flags & RTW_AP_B2U_BCAST) && is_broadcast_mac_addr(da)) \
++	|| ((flags & RTW_AP_B2U_IP_MCAST) && (IP_MCAST_MAC(da) || ICMPV6_MCAST_MAC(da))) \
++	)
++
++#define rtw_ap_fwd_b2u_policy_chk(flags, da, gaucst) ( \
++	(flags & RTW_AP_B2U_ALL) \
++	|| ((flags & RTW_AP_B2U_GA_UCAST) && gaucst) \
++	|| ((flags & RTW_AP_B2U_BCAST) && is_broadcast_mac_addr(da)) \
++	|| ((flags & RTW_AP_B2U_IP_MCAST) && (IP_MCAST_MAC(da) || ICMPV6_MCAST_MAC(da))) \
++	)
++
++void dump_ap_b2u_flags(void *sel, _adapter *adapter);
++
++int rtw_ap_addr_resolve(_adapter *adapter, u16 os_qid, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list);
++int rtw_ap_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta);
++int rtw_ap_rx_msdu_act_check(union recv_frame *rframe
++	, const u8 *da, const u8 *sa
++	, u8 *msdu, enum rtw_rx_llc_hdl llc_hdl
++	, struct xmit_frame **fwd_frame, _list *b2u_list);
++
++void update_bmc_sta(_adapter *padapter);
++
++#ifdef CONFIG_BMC_TX_RATE_SELECT
++void rtw_update_bmc_sta_tx_rate(_adapter *adapter);
++#endif
++
++void rtw_process_ht_action_smps(_adapter *padapter, u8 *ta, u8 ctrl_field);
++void rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_len);
++#ifdef CONFIG_80211N_HT
++int rtw_ht_operation_update(_adapter *padapter);
++#endif /* CONFIG_80211N_HT */
++u8 rtw_ap_sta_states_check(_adapter *adapter);
++
++#ifdef CONFIG_FW_HANDLE_TXBCN
++#define rtw_ap_get_nums(adapter)	(adapter_to_dvobj(adapter)->nr_ap_if)
++bool rtw_ap_nums_check(_adapter *adapter);
++#endif
++
++#ifdef CONFIG_SWTIMER_BASED_TXBCN
++void tx_beacon_handlder(struct dvobj_priv *pdvobj);
++void tx_beacon_timer_handlder(void *ctx);
++#endif /*CONFIG_SWTIMER_BASED_TXBCN*/
++
++#endif /* end of CONFIG_AP_MODE */
++#endif /*__RTW_AP_H_*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_beamforming.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_beamforming.h
+new file mode 100644
+index 000000000..4c7f006e8
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_beamforming.h
+@@ -0,0 +1,297 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_BEAMFORMING_H_
++#define __RTW_BEAMFORMING_H_
++
++#ifdef CONFIG_BEAMFORMING
++
++#ifdef RTW_BEAMFORMING_VERSION_2
++#define MAX_NUM_BEAMFORMEE_SU	2
++#define MAX_NUM_BEAMFORMER_SU	2
++#define MAX_NUM_BEAMFORMEE_MU	6
++#define MAX_NUM_BEAMFORMER_MU	1
++
++#define MAX_BEAMFORMEE_ENTRY_NUM	(MAX_NUM_BEAMFORMEE_SU + MAX_NUM_BEAMFORMEE_MU)
++#define MAX_BEAMFORMER_ENTRY_NUM	(MAX_NUM_BEAMFORMER_SU + MAX_NUM_BEAMFORMER_MU)
++
++/* <Note> Need to be defined by IC */
++#define SU_SOUNDING_TIMEOUT	5	/* unit: ms */
++#define MU_SOUNDING_TIMEOUT	8	/* unit: ms */
++
++#define GET_BEAMFORM_INFO(adapter)	(&GET_HAL_DATA(adapter)->beamforming_info)
++#define GetInitSoundCnt(_SoundPeriod, _MinSoundPeriod)	((_SoundPeriod)/(_MinSoundPeriod))
++
++enum BEAMFORMING_CTRL_TYPE {
++	BEAMFORMING_CTRL_ENTER = 0,
++	BEAMFORMING_CTRL_LEAVE = 1,
++	BEAMFORMING_CTRL_START_PERIOD = 2,
++	BEAMFORMING_CTRL_END_PERIOD = 3,
++	BEAMFORMING_CTRL_SOUNDING_FAIL = 4,
++	BEAMFORMING_CTRL_SOUNDING_CLK = 5,
++	BEAMFORMING_CTRL_SET_GID_TABLE = 6,
++	BEAMFORMING_CTRL_SET_CSI_REPORT = 7,
++};
++
++enum _BEAMFORMING_STATE {
++	BEAMFORMING_STATE_IDLE,
++	BEAMFORMING_STATE_START,
++	BEAMFORMING_STATE_END,
++};
++
++/*
++ * typedef BEAMFORMING_CAP for phydm
++ */
++typedef enum beamforming_cap {
++	BEAMFORMING_CAP_NONE = 0x0,
++	BEAMFORMER_CAP_HT_EXPLICIT = 0x1,
++	BEAMFORMEE_CAP_HT_EXPLICIT = 0x2,
++	BEAMFORMER_CAP_VHT_SU = 0x4,			/* Self has er Cap, because Reg er  & peer ee */
++	BEAMFORMEE_CAP_VHT_SU = 0x8, 			/* Self has ee Cap, because Reg ee & peer er */
++	BEAMFORMER_CAP_VHT_MU = 0x10,			/* Self has er Cap, because Reg er & peer ee */
++	BEAMFORMEE_CAP_VHT_MU = 0x20,			/* Self has ee Cap, because Reg ee & peer er */
++	BEAMFORMER_CAP = 0x40,
++	BEAMFORMEE_CAP = 0x80,
++} BEAMFORMING_CAP;
++
++enum _BEAMFORM_ENTRY_HW_STATE {
++	BEAMFORM_ENTRY_HW_STATE_NONE,
++	BEAMFORM_ENTRY_HW_STATE_ADD_INIT,
++	BEAMFORM_ENTRY_HW_STATE_ADDING,
++	BEAMFORM_ENTRY_HW_STATE_ADDED,
++	BEAMFORM_ENTRY_HW_STATE_DELETE_INIT,
++	BEAMFORM_ENTRY_HW_STATE_DELETING,
++	BEAMFORM_ENTRY_HW_STATE_MAX
++};
++
++/* The sounding state is recorded by BFer. */
++enum _SOUNDING_STATE {
++	SOUNDING_STATE_NONE		= 0,
++	SOUNDING_STATE_INIT		= 1,
++	SOUNDING_STATE_SU_START		= 2,
++	SOUNDING_STATE_SU_SOUNDDOWN	= 3,
++	SOUNDING_STATE_MU_START		= 4,
++	SOUNDING_STATE_MU_SOUNDDOWN	= 5,
++	SOUNDING_STATE_SOUNDING_TIMEOUT	= 6,
++	SOUNDING_STATE_MAX
++};
++
++struct beamformee_entry {
++	u8 used;	/* _TRUE/_FALSE */
++	u8 txbf;
++	u8 sounding;
++	/* Used to construct AID field of NDPA packet */
++	u16 aid;
++	/* Used to Set Reg42C in IBSS mode */
++	u16 mac_id;
++	/* Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC */
++	u16 p_aid;
++	u8 g_id;
++	/* Used to fill Reg6E4 to fill Mac address of CSI report frame */
++	u8 mac_addr[ETH_ALEN];
++	/* Sounding BandWidth */
++	enum channel_width sound_bw;
++	u16 sound_period;
++
++	enum beamforming_cap cap;
++	enum _BEAMFORM_ENTRY_HW_STATE state;
++
++	/* The BFee need to be sounded when count to zero */
++	u8 SoundCnt;
++	u8 bCandidateSoundingPeer;
++	u8 bSoundingTimeout;
++	u8 bDeleteSounding;
++	/* Get the result through throughput and Tx rate from BB API */
++	u8 bApplySounding;
++
++	/* information for sounding judgement */
++	systime tx_timestamp;
++	u64 tx_bytes;
++
++	u16 LogStatusFailCnt:5;	/* 0~21 */
++	u16 DefaultCSICnt:5; /* 0~21 */
++	u8 CSIMatrix[327];
++	u16 CSIMatrixLen;
++
++	u8 NumofSoundingDim;
++
++	u8 comp_steering_num_of_bfer;
++
++
++	/* SU-MIMO */
++	u8 su_reg_index;
++
++	/* MU-MIMO */
++	u8 mu_reg_index;
++	u8 gid_valid[8];
++	u8 user_position[16];
++
++	/* For 8822B C-cut workaround */
++	/* If the flag set to _TRUE, do not sound this STA */
++	u8 bSuspendSUCap;
++};
++
++struct beamformer_entry {
++	u8 used;
++	/* p_aid of BFer entry is probably not used */
++	/* Used to fill Reg42C & Reg714 to compare with p_aid of Tx DESC */
++	u16 p_aid;
++	u8 g_id;
++	u8 mac_addr[ETH_ALEN];
++
++	enum beamforming_cap cap;
++	enum _BEAMFORM_ENTRY_HW_STATE state;
++
++	u8 NumofSoundingDim;
++
++	/* SU-MIMO */
++	u8 su_reg_index;
++
++	/* MU-MIMO */
++	u8 gid_valid[8];
++	u8 user_position[16];
++	u16 aid;
++};
++
++struct sounding_info {
++	u8 su_sounding_list[MAX_NUM_BEAMFORMEE_SU];
++	u8 mu_sounding_list[MAX_NUM_BEAMFORMEE_MU];
++
++	enum _SOUNDING_STATE state;
++	/*
++	 * su_bfee_curidx is index for beamforming_info.bfee_entry[]
++	 * range: 0~MAX_BEAMFORMEE_ENTRY_NUM
++	 */
++	u8 su_bfee_curidx;
++	u8 candidate_mu_bfee_cnt;
++
++	/* For sounding schedule maintenance */
++	u16 min_sounding_period;
++	/* Get from sounding list */
++	/* Ex: SU STA1, SU STA2, MU STA(1~n) => the value will be 2+1=3 */
++	u8 sound_remain_cnt_per_period;
++};
++
++struct _RT_CSI_INFO{
++	u8 Nc;
++	u8 Nr;
++	u8 Ng;
++	u8 CodeBook;
++	u8 ChnlWidth;
++	u8 bVHT;
++};
++
++struct beamforming_info {
++	enum beamforming_cap beamforming_cap;
++	enum _BEAMFORMING_STATE beamforming_state;
++	struct beamformee_entry bfee_entry[MAX_BEAMFORMEE_ENTRY_NUM];
++	struct beamformer_entry bfer_entry[MAX_BEAMFORMER_ENTRY_NUM];
++	u8 sounding_sequence;
++	u8 beamformee_su_cnt;
++	u8 beamformer_su_cnt;
++	u32 beamformee_su_reg_maping;
++	u32 beamformer_su_reg_maping;
++	/* For MU-MINO */
++	u8 beamformee_mu_cnt;
++	u8 beamformer_mu_cnt;
++	u32 beamformee_mu_reg_maping;
++	u8 first_mu_bfee_index;
++	u8 mu_bfer_curidx;
++	u8 cur_csi_rpt_rate;
++
++	struct sounding_info sounding_info;
++	/* schedule regular timer for sounding */
++	_timer sounding_timer;
++	/* moniter if soudning too long */
++	_timer sounding_timeout_timer;
++
++	/* For HW configuration */
++	u8 SetHalBFEnterOnDemandCnt;
++	u8 SetHalBFLeaveOnDemandCnt;
++	u8 SetHalSoundownOnDemandCnt;
++	u8 bSetBFHwConfigInProgess;
++
++	/*
++	 * Target CSI report info.
++	 * Keep the first SU CSI report info for 8822B HW bug workaround.
++	 */
++	u8 bEnableSUTxBFWorkAround;
++	struct _RT_CSI_INFO TargetCSIInfo;
++	/* Only peform sounding to the first SU BFee */
++	struct beamformee_entry *TargetSUBFee;
++
++	/* For debug */
++	s8 sounding_running;
++};
++
++enum beamforming_cap rtw_bf_bfee_get_entry_cap_by_macid(void *mlmepriv, u8 mac_id);
++struct beamformer_entry *rtw_bf_bfer_get_entry_by_addr(PADAPTER, u8 *ra);
++struct beamformee_entry *rtw_bf_bfee_get_entry_by_addr(PADAPTER, u8 *ra);
++void rtw_bf_get_ndpa_packet(PADAPTER, union recv_frame *);
++u32 rtw_bf_get_report_packet(PADAPTER, union recv_frame *);
++u8 rtw_bf_send_vht_gid_mgnt_packet(PADAPTER, u8 *ra, u8 *gid, u8 *position);
++void rtw_bf_get_vht_gid_mgnt_packet(PADAPTER, union recv_frame *);
++void rtw_bf_init(PADAPTER);
++void rtw_bf_cmd_hdl(PADAPTER, u8 type, u8 *pbuf);
++u8 rtw_bf_cmd(PADAPTER, s32 type, u8 *pbuf, s32 size, u8 enqueue);
++void rtw_bf_update_attrib(PADAPTER, struct pkt_attrib *, struct sta_info *);
++void rtw_bf_c2h_handler(PADAPTER, u8 id, u8 *buf, u8 buf_len);
++void rtw_bf_update_traffic(PADAPTER);
++
++/* Compatible with old function name, only for using outside rtw_beamforming.c */
++#define beamforming_get_entry_beam_cap_by_mac_id	rtw_bf_bfee_get_entry_cap_by_macid
++#define rtw_beamforming_get_ndpa_frame			rtw_bf_get_ndpa_packet
++#define rtw_beamforming_get_report_frame			rtw_bf_get_report_packet
++#define rtw_beamforming_get_vht_gid_mgnt_frame		rtw_bf_get_vht_gid_mgnt_packet
++#define beamforming_wk_hdl				rtw_bf_cmd_hdl
++#define beamforming_wk_cmd				rtw_bf_cmd
++#define update_attrib_txbf_info				rtw_bf_update_attrib
++
++#define HT_BF_CAP(adapter) ((adapter)->mlmepriv.htpriv.beamform_cap)
++#define VHT_BF_CAP(adapter) ((adapter)->mlmepriv.vhtpriv.beamform_cap)
++
++#define IS_HT_BEAMFORMEE(adapter) \
++		(HT_BF_CAP(adapter) & \
++		(BEAMFORMING_HT_BEAMFORMEE_ENABLE))
++
++#define IS_VHT_BEAMFORMEE(adapter) \
++		(VHT_BF_CAP(adapter) & \
++		(BEAMFORMING_VHT_BEAMFORMEE_ENABLE | \
++		 BEAMFORMING_VHT_MU_MIMO_STA_ENABLE))
++
++#define IS_BEAMFORMEE(adapter) (IS_HT_BEAMFORMEE(adapter) | \
++				IS_VHT_BEAMFORMEE(adapter))
++
++#else /* !RTW_BEAMFORMING_VERSION_2 */
++/*PHYDM_BF - (BEAMFORMING_SUPPORT == 1)*/
++enum BEAMFORMING_CTRL_TYPE {
++	BEAMFORMING_CTRL_ENTER = 0,
++	BEAMFORMING_CTRL_LEAVE = 1,
++	BEAMFORMING_CTRL_START_PERIOD = 2,
++	BEAMFORMING_CTRL_END_PERIOD = 3,
++	BEAMFORMING_CTRL_SOUNDING_FAIL = 4,
++	BEAMFORMING_CTRL_SOUNDING_CLK = 5,
++};
++u32	rtw_beamforming_get_report_frame(PADAPTER	 Adapter, union recv_frame *precv_frame);
++void	rtw_beamforming_get_ndpa_frame(PADAPTER	 Adapter, union recv_frame *precv_frame);
++
++void	beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf);
++u8	beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enqueue);
++void update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta);
++
++#endif /* !RTW_BEAMFORMING_VERSION_2 */
++
++#endif /*#ifdef CONFIG_BEAMFORMING */
++
++#endif /*__RTW_BEAMFORMING_H_*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_br_ext.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_br_ext.h
+new file mode 100644
+index 000000000..54ba75ea1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_br_ext.h
+@@ -0,0 +1,69 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTW_BR_EXT_H_
++#define _RTW_BR_EXT_H_
++
++#if 1	/* rtw_wifi_driver */
++#define CL_IPV6_PASS	1
++#define MACADDRLEN		6
++#define _DEBUG_ERR		RTW_INFO
++#define _DEBUG_INFO		/* RTW_INFO */
++#define DEBUG_WARN		RTW_INFO
++#define DEBUG_INFO		/* RTW_INFO */
++#define DEBUG_ERR		RTW_INFO
++/* #define GET_MY_HWADDR		((GET_MIB(priv))->dot11OperationEntry.hwaddr) */
++#define GET_MY_HWADDR(padapter)		(adapter_mac_addr(padapter))
++#endif /* rtw_wifi_driver */
++
++#define NAT25_HASH_BITS		4
++#define NAT25_HASH_SIZE		(1 << NAT25_HASH_BITS)
++#define NAT25_AGEING_TIME	300
++
++#ifdef CL_IPV6_PASS
++	#define MAX_NETWORK_ADDR_LEN	17
++#else
++	#define MAX_NETWORK_ADDR_LEN	11
++#endif
++
++struct nat25_network_db_entry {
++	struct nat25_network_db_entry	*next_hash;
++	struct nat25_network_db_entry	**pprev_hash;
++	atomic_t						use_count;
++	unsigned char					macAddr[6];
++	unsigned long					ageing_timer;
++	unsigned char				networkAddr[MAX_NETWORK_ADDR_LEN];
++};
++
++enum NAT25_METHOD {
++	NAT25_MIN,
++	NAT25_CHECK,
++	NAT25_INSERT,
++	NAT25_LOOKUP,
++	NAT25_PARSE,
++	NAT25_MAX
++};
++
++struct br_ext_info {
++	unsigned int	nat25_disable;
++	unsigned int	macclone_enable;
++	unsigned int	dhcp_bcst_disable;
++	int		addPPPoETag;		/* 1: Add PPPoE relay-SID, 0: disable */
++	unsigned char	nat25_dmzMac[MACADDRLEN];
++	unsigned int	nat25sc_disable;
++};
++
++void nat25_db_cleanup(_adapter *priv);
++
++#endif /* _RTW_BR_EXT_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_bt_mp.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_bt_mp.h
+new file mode 100644
+index 000000000..93af3c8f0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_bt_mp.h
+@@ -0,0 +1,288 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __RTW_BT_MP_H
++#define __RTW_BT_MP_H
++
++
++#if (MP_DRIVER == 1)
++
++#pragma pack(1)
++
++/* definition for BT_UP_OP_BT_READY */
++#define	MP_BT_NOT_READY						0
++#define	MP_BT_READY							1
++
++/* definition for BT_UP_OP_BT_SET_MODE */
++typedef enum _MP_BT_MODE {
++	MP_BT_MODE_RF_TXRX_TEST_MODE							= 0,
++	MP_BT_MODE_BT20_DUT_TEST_MODE							= 1,
++	MP_BT_MODE_BT40_DIRECT_TEST_MODE						= 2,
++	MP_BT_MODE_CONNECT_TEST_MODE							= 3,
++	MP_BT_MODE_MAX
++} MP_BT_MODE, *PMP_BT_MODE;
++
++
++/* definition for BT_UP_OP_BT_SET_TX_RX_PARAMETER */
++typedef struct _BT_TXRX_PARAMETERS {
++	u8		txrxChannel;
++	u32		txrxTxPktCnt;
++	u8		txrxTxPktInterval;
++	u8		txrxPayloadType;
++	u8		txrxPktType;
++	u16		txrxPayloadLen;
++	u32		txrxPktHeader;
++	u8		txrxWhitenCoeff;
++	u8		txrxBdaddr[6];
++	u8		txrxTxGainIndex;
++} BT_TXRX_PARAMETERS, *PBT_TXRX_PARAMETERS;
++
++/* txrxPktType */
++typedef enum _MP_BT_PKT_TYPE {
++	MP_BT_PKT_DH1							= 0,
++	MP_BT_PKT_DH3							= 1,
++	MP_BT_PKT_DH5							= 2,
++	MP_BT_PKT_2DH1							= 3,
++	MP_BT_PKT_2DH3							= 4,
++	MP_BT_PKT_2DH5							= 5,
++	MP_BT_PKT_3DH1							= 6,
++	MP_BT_PKT_3DH3							= 7,
++	MP_BT_PKT_3DH5							= 8,
++	MP_BT_PKT_LE							= 9,
++	MP_BT_PKT_MAX
++} MP_BT_PKT_TYPE, *PMP_BT_PKT_TYPE;
++/* txrxPayloadType */
++typedef enum _MP_BT_PAYLOAD_TYPE {
++	MP_BT_PAYLOAD_01010101					= 0,
++	MP_BT_PAYLOAD_ALL_1						= 1,
++	MP_BT_PAYLOAD_ALL_0						= 2,
++	MP_BT_PAYLOAD_11110000					= 3,
++	MP_BT_PAYLOAD_PRBS9						= 4,
++	MP_BT_PAYLOAD_MAX						= 8,
++} MP_BT_PAYLOAD_TYPE, *PMP_BT_PAYLOAD_TYPE;
++
++
++/* definition for BT_UP_OP_BT_TEST_CTRL */
++typedef enum _MP_BT_TEST_CTRL {
++	MP_BT_TEST_STOP_ALL_TESTS						= 0,
++	MP_BT_TEST_START_RX_TEST						= 1,
++	MP_BT_TEST_START_PACKET_TX_TEST					= 2,
++	MP_BT_TEST_START_CONTINUOUS_TX_TEST			= 3,
++	MP_BT_TEST_START_INQUIRY_SCAN_TEST				= 4,
++	MP_BT_TEST_START_PAGE_SCAN_TEST					= 5,
++	MP_BT_TEST_START_INQUIRY_PAGE_SCAN_TEST			= 6,
++	MP_BT_TEST_START_LEGACY_CONNECT_TEST			= 7,
++	MP_BT_TEST_START_LE_CONNECT_TEST_INITIATOR		= 8,
++	MP_BT_TEST_START_LE_CONNECT_TEST_ADVERTISER	= 9,
++	MP_BT_TEST_MAX
++} MP_BT_TEST_CTRL, *PMP_BT_TEST_CTRL;
++
++
++typedef enum _RTL_EXT_C2H_EVT {
++	EXT_C2H_WIFI_FW_ACTIVE_RSP = 0,
++	EXT_C2H_TRIG_BY_BT_FW = 1,
++	MAX_EXT_C2HEVENT
++} RTL_EXT_C2H_EVT;
++
++/* OP codes definition between the user layer and driver */
++typedef enum _BT_CTRL_OPCODE_UPPER {
++	BT_UP_OP_BT_READY										= 0x00,
++	BT_UP_OP_BT_SET_MODE									= 0x01,
++	BT_UP_OP_BT_SET_TX_RX_PARAMETER						= 0x02,
++	BT_UP_OP_BT_SET_GENERAL								= 0x03,
++	BT_UP_OP_BT_GET_GENERAL								= 0x04,
++	BT_UP_OP_BT_TEST_CTRL									= 0x05,
++	BT_UP_OP_TEST_BT										= 0x06,
++	BT_UP_OP_MAX
++} BT_CTRL_OPCODE_UPPER, *PBT_CTRL_OPCODE_UPPER;
++
++
++typedef enum _BT_SET_GENERAL {
++	BT_GSET_REG											= 0x00,
++	BT_GSET_RESET											= 0x01,
++	BT_GSET_TARGET_BD_ADDR									= 0x02,
++	BT_GSET_TX_PWR_FINETUNE								= 0x03,
++	BT_SET_TRACKING_INTERVAL								= 0x04,
++	BT_SET_THERMAL_METER									= 0x05,
++	BT_ENABLE_CFO_TRACKING									= 0x06,
++	BT_GSET_UPDATE_BT_PATCH								= 0x07,
++	BT_GSET_MAX
++} BT_SET_GENERAL, *PBT_SET_GENERAL;
++
++typedef enum _BT_GET_GENERAL {
++	BT_GGET_REG											= 0x00,
++	BT_GGET_STATUS											= 0x01,
++	BT_GGET_REPORT											= 0x02,
++	BT_GGET_AFH_MAP										= 0x03,
++	BT_GGET_AFH_STATUS										= 0x04,
++	BT_GGET_MAX
++} BT_GET_GENERAL, *PBT_GET_GENERAL;
++
++/* definition for BT_UP_OP_BT_SET_GENERAL */
++typedef enum _BT_REG_TYPE {
++	BT_REG_RF								= 0,
++	BT_REG_MODEM							= 1,
++	BT_REG_BLUEWIZE						= 2,
++	BT_REG_VENDOR							= 3,
++	BT_REG_LE								= 4,
++	BT_REG_MAX
++} BT_REG_TYPE, *PBT_REG_TYPE;
++
++/* definition for BT_LO_OP_GET_AFH_MAP */
++typedef enum _BT_AFH_MAP_TYPE {
++	BT_AFH_MAP_RESULT						= 0,
++	BT_AFH_MAP_WIFI_PSD_ONLY				= 1,
++	BT_AFH_MAP_WIFI_CH_BW_ONLY				= 2,
++	BT_AFH_MAP_BT_PSD_ONLY					= 3,
++	BT_AFH_MAP_HOST_CLASSIFICATION_ONLY	= 4,
++	BT_AFH_MAP_MAX
++} BT_AFH_MAP_TYPE, *PBT_AFH_MAP_TYPE;
++
++/* definition for BT_UP_OP_BT_GET_GENERAL */
++typedef enum _BT_REPORT_TYPE {
++	BT_REPORT_RX_PACKET_CNT				= 0,
++	BT_REPORT_RX_ERROR_BITS				= 1,
++	BT_REPORT_RSSI							= 2,
++	BT_REPORT_CFO_HDR_QUALITY				= 3,
++	BT_REPORT_CONNECT_TARGET_BD_ADDR		= 4,
++	BT_REPORT_MAX
++} BT_REPORT_TYPE, *PBT_REPORT_TYPE;
++
++void
++MPTBT_Test(
++		PADAPTER	Adapter,
++		u8		opCode,
++		u8		byte1,
++		u8		byte2,
++		u8		byte3
++);
++
++uint
++MPTBT_SendOidBT(
++		PADAPTER		pAdapter,
++		void				*InformationBuffer,
++		u32				InformationBufferLength,
++		u32 				*BytesRead,
++		u32 				*BytesNeeded
++);
++
++void
++MPTBT_FwC2hBtMpCtrl(
++	PADAPTER	Adapter,
++	u8 			*tmpBuf,
++	u8			length
++);
++
++void MPh2c_timeout_handle(void *FunctionContext);
++
++void mptbt_BtControlProcess(
++	PADAPTER	Adapter,
++	void			*pInBuf
++);
++
++#define	BT_H2C_MAX_RETRY								1
++#define	BT_MAX_C2H_LEN								20
++
++typedef struct _BT_REQ_CMD {
++	u8       opCodeVer;
++	u8       OpCode;
++	u16      paraLength;
++	u8       pParamStart[100];
++} BT_REQ_CMD, *PBT_REQ_CMD;
++
++typedef struct _BT_RSP_CMD {
++	u16      status;
++	u16      paraLength;
++	u8       pParamStart[100];
++} BT_RSP_CMD, *PBT_RSP_CMD;
++
++
++typedef struct _BT_H2C {
++	u8	opCodeVer:4;
++	u8	reqNum:4;
++	u8	opCode;
++	u8	buf[100];
++} BT_H2C, *PBT_H2C;
++
++
++
++typedef struct _BT_EXT_C2H {
++	u8	extendId;
++	u8	statusCode:4;
++	u8	retLen:4;
++	u8	opCodeVer:4;
++	u8	reqNum:4;
++	u8	buf[100];
++} BT_EXT_C2H, *PBT_EXT_C2H;
++
++
++typedef enum _BT_OPCODE_STATUS {
++	BT_OP_STATUS_SUCCESS									= 0x00, /* Success */
++	BT_OP_STATUS_VERSION_MISMATCH							= 0x01,
++	BT_OP_STATUS_UNKNOWN_OPCODE								= 0x02,
++	BT_OP_STATUS_ERROR_PARAMETER							= 0x03,
++	BT_OP_STATUS_MAX
++} BT_OPCODE_STATUS, *PBT_OPCODE_STATUS;
++
++
++
++/* OP codes definition between driver and bt fw */
++typedef enum _BT_CTRL_OPCODE_LOWER {
++	BT_LO_OP_GET_BT_VERSION									= 0x00,
++	BT_LO_OP_RESET												= 0x01,
++	BT_LO_OP_TEST_CTRL											= 0x02,
++	BT_LO_OP_SET_BT_MODE										= 0x03,
++	BT_LO_OP_SET_CHNL_TX_GAIN									= 0x04,
++	BT_LO_OP_SET_PKT_TYPE_LEN									= 0x05,
++	BT_LO_OP_SET_PKT_CNT_L_PL_TYPE								= 0x06,
++	BT_LO_OP_SET_PKT_CNT_H_PKT_INTV							= 0x07,
++	BT_LO_OP_SET_PKT_HEADER									= 0x08,
++	BT_LO_OP_SET_WHITENCOEFF									= 0x09,
++	BT_LO_OP_SET_BD_ADDR_L										= 0x0a,
++	BT_LO_OP_SET_BD_ADDR_H										= 0x0b,
++	BT_LO_OP_WRITE_REG_ADDR									= 0x0c,
++	BT_LO_OP_WRITE_REG_VALUE									= 0x0d,
++	BT_LO_OP_GET_BT_STATUS										= 0x0e,
++	BT_LO_OP_GET_BD_ADDR_L										= 0x0f,
++	BT_LO_OP_GET_BD_ADDR_H										= 0x10,
++	BT_LO_OP_READ_REG											= 0x11,
++	BT_LO_OP_SET_TARGET_BD_ADDR_L								= 0x12,
++	BT_LO_OP_SET_TARGET_BD_ADDR_H								= 0x13,
++	BT_LO_OP_SET_TX_POWER_CALIBRATION							= 0x14,
++	BT_LO_OP_GET_RX_PKT_CNT_L									= 0x15,
++	BT_LO_OP_GET_RX_PKT_CNT_H									= 0x16,
++	BT_LO_OP_GET_RX_ERROR_BITS_L								= 0x17,
++	BT_LO_OP_GET_RX_ERROR_BITS_H								= 0x18,
++	BT_LO_OP_GET_RSSI											= 0x19,
++	BT_LO_OP_GET_CFO_HDR_QUALITY_L								= 0x1a,
++	BT_LO_OP_GET_CFO_HDR_QUALITY_H								= 0x1b,
++	BT_LO_OP_GET_TARGET_BD_ADDR_L								= 0x1c,
++	BT_LO_OP_GET_TARGET_BD_ADDR_H								= 0x1d,
++	BT_LO_OP_GET_AFH_MAP_L										= 0x1e,
++	BT_LO_OP_GET_AFH_MAP_M										= 0x1f,
++	BT_LO_OP_GET_AFH_MAP_H										= 0x20,
++	BT_LO_OP_GET_AFH_STATUS									= 0x21,
++	BT_LO_OP_SET_TRACKING_INTERVAL								= 0x22,
++	BT_LO_OP_SET_THERMAL_METER									= 0x23,
++	BT_LO_OP_ENABLE_CFO_TRACKING								= 0x24,
++	BT_LO_OP_MAX
++} BT_CTRL_OPCODE_LOWER, *PBT_CTRL_OPCODE_LOWER;
++
++
++
++
++#endif  /* #if(MP_DRIVER == 1) */
++
++#endif /*  #ifndef __INC_MPT_BT_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_btcoex.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_btcoex.h
+new file mode 100644
+index 000000000..cd37ee5c7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_btcoex.h
+@@ -0,0 +1,460 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifdef CONFIG_BT_COEXIST
++
++#ifndef __RTW_BTCOEX_H__
++#define __RTW_BTCOEX_H__
++
++#include <drv_types.h>
++
++/* For H2C: H2C_BT_MP_OPER. Return status definition to the user layer */
++typedef enum _BT_CTRL_STATUS {
++	BT_STATUS_SUCCESS								= 0x00, /* Success */
++	BT_STATUS_BT_OP_SUCCESS							= 0x01, /* bt fw op execution success */
++	BT_STATUS_H2C_SUCCESS							= 0x02, /* H2c success */
++	BT_STATUS_H2C_FAIL								= 0x03, /* H2c fail */
++	BT_STATUS_H2C_LENGTH_EXCEEDED					= 0x04, /* H2c command length exceeded */
++	BT_STATUS_H2C_TIMTOUT							= 0x05, /* H2c timeout */
++	BT_STATUS_H2C_BT_NO_RSP							= 0x06, /* H2c sent, bt no rsp */
++	BT_STATUS_C2H_SUCCESS							= 0x07, /* C2h success */
++	BT_STATUS_C2H_REQNUM_MISMATCH					= 0x08, /* bt fw wrong rsp */
++	BT_STATUS_OPCODE_U_VERSION_MISMATCH				= 0x08, /* Upper layer OP code version mismatch. */
++	BT_STATUS_OPCODE_L_VERSION_MISMATCH				= 0x0a, /* Lower layer OP code version mismatch. */
++	BT_STATUS_UNKNOWN_OPCODE_U						= 0x0b, /* Unknown Upper layer OP code */
++	BT_STATUS_UNKNOWN_OPCODE_L						= 0x0c, /* Unknown Lower layer OP code */
++	BT_STATUS_PARAMETER_FORMAT_ERROR_U				= 0x0d, /* Wrong parameters sent by upper layer. */
++	BT_STATUS_PARAMETER_FORMAT_ERROR_L				= 0x0e, /* bt fw parameter format is not consistency */
++	BT_STATUS_PARAMETER_OUT_OF_RANGE_U				= 0x0f, /* uppery layer parameter value is out of range */
++	BT_STATUS_PARAMETER_OUT_OF_RANGE_L				= 0x10, /* bt fw parameter value is out of range */
++	BT_STATUS_UNKNOWN_STATUS_L						= 0x11, /* bt returned an defined status code */
++	BT_STATUS_UNKNOWN_STATUS_H						= 0x12, /* driver need to do error handle or not handle-well. */
++	BT_STATUS_WRONG_LEVEL							= 0x13, /* should be under passive level */
++	BT_STATUS_NOT_IMPLEMENT						= 0x14, /* op code not implemented yet */
++	BT_STATUS_BT_STACK_OP_SUCCESS					= 0x15, /* bt stack op execution success */
++	BT_STATUS_BT_STACK_NOT_SUPPORT					= 0x16, /* stack version not support this. */
++	BT_STATUS_BT_STACK_SEND_HCI_EVENT_FAIL			= 0x17, /* send hci event fail */
++	BT_STATUS_BT_STACK_NOT_BIND						= 0x18, /* stack not bind wifi driver */
++	BT_STATUS_BT_STACK_NO_RSP						= 0x19, /* stack doesn't have any rsp. */
++	BT_STATUS_MAX
++} BT_CTRL_STATUS, *PBT_CTRL_STATUS;
++
++typedef enum _BTCOEX_SUSPEND_STATE {
++	BTCOEX_SUSPEND_STATE_RESUME					= 0x0,
++	BTCOEX_SUSPEND_STATE_SUSPEND				= 0x1,
++	BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT		= 0x2,
++	BTCOEX_SUSPEND_STATE_MAX
++} BTCOEX_SUSPEND_STATE, *PBTCOEX_SUSPEND_STATE;
++
++#define SET_BT_MP_OPER_RET(OpCode, StatusCode)						((OpCode << 8) | StatusCode)
++#define GET_OP_CODE_FROM_BT_MP_OPER_RET(RetCode)					((RetCode & 0xF0) >> 8)
++#define GET_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode)				(RetCode & 0x0F)
++#define CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode, StatusCode)	(GET_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode) == StatusCode)
++
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++
++#define NETLINK_USER 31
++#define CONNECT_PORT 30000
++#define CONNECT_PORT_BT 30001
++#define KERNEL_SOCKET_OK 0x01
++#define NETLINK_SOCKET_OK 0x02
++
++#define OTHER 0
++#define RX_ATTEND_ACK 1
++#define RX_LEAVE_ACK 2
++#define RX_BT_LEAVE 3
++#define RX_INVITE_REQ 4
++#define RX_ATTEND_REQ 5
++#define RX_INVITE_RSP 6
++
++#define invite_req "INVITE_REQ"
++#define invite_rsp "INVITE_RSP"
++#define attend_req "ATTEND_REQ"
++#define attend_ack "ATTEND_ACK"
++#define wifi_leave "WIFI_LEAVE"
++#define leave_ack "LEAVE_ACK"
++#define bt_leave "BT_LEAVE"
++
++#define BT_INFO_NOTIFY_CMD 0x0106
++#define BT_INFO_LEN 8
++
++typedef struct _HCI_LINK_INFO {
++	u16					ConnectHandle;
++	u8					IncomingTrafficMode;
++	u8					OutgoingTrafficMode;
++	u8					BTProfile;
++	u8					BTCoreSpec;
++	s8					BT_RSSI;
++	u8					TrafficProfile;
++	u8					linkRole;
++} HCI_LINK_INFO, *PHCI_LINK_INFO;
++
++#define	MAX_BT_ACL_LINK_NUM				8
++
++typedef struct _HCI_EXT_CONFIG {
++	HCI_LINK_INFO				aclLink[MAX_BT_ACL_LINK_NUM];
++	u8					btOperationCode;
++	u16					CurrentConnectHandle;
++	u8					CurrentIncomingTrafficMode;
++	u8					CurrentOutgoingTrafficMode;
++
++	u8					NumberOfACL;
++	u8					NumberOfSCO;
++	u8					CurrentBTStatus;
++	u16					HCIExtensionVer;
++
++	BOOLEAN					bEnableWifiScanNotify;
++} HCI_EXT_CONFIG, *PHCI_EXT_CONFIG;
++
++typedef struct _HCI_PHY_LINK_BSS_INFO {
++	u16						bdCap;			/* capability information */
++
++	/* Qos related. Added by Annie, 2005-11-01. */
++	/* BSS_QOS						BssQos;		 */
++
++} HCI_PHY_LINK_BSS_INFO, *PHCI_PHY_LINK_BSS_INFO;
++
++typedef enum _BT_CONNECT_TYPE {
++	BT_CONNECT_AUTH_REQ								= 0x00,
++	BT_CONNECT_AUTH_RSP								= 0x01,
++	BT_CONNECT_ASOC_REQ								= 0x02,
++	BT_CONNECT_ASOC_RSP								= 0x03,
++	BT_DISCONNECT										= 0x04
++} BT_CONNECT_TYPE, *PBT_CONNECT_TYPE;
++
++
++typedef struct _PACKET_IRP_HCIEVENT_DATA {
++	u8		EventCode;
++	u8		Length; /* total cmd length = extension event length+1(extension event code length) */
++	u8		Data[1]; /* byte1 is extension event code */
++} rtw_HCI_event;
++
++
++struct btinfo_8761ATV {
++	u8 cid;
++	u8 len;
++
++	u8 bConnection:1;
++	u8 bSCOeSCO:1;
++	u8 bInQPage:1;
++	u8 bACLBusy:1;
++	u8 bSCOBusy:1;
++	u8 bHID:1;
++	u8 bA2DP:1;
++	u8 bFTP:1;
++
++	u8 retry_cnt:4;
++	u8 rsvd_34:1;
++	u8 bPage:1;
++	u8 TRxMask:1;
++	u8 Sniff_attempt:1;
++
++	u8 rssi;
++
++	u8 A2dp_rate:1;
++	u8 ReInit:1;
++	u8 MaxPower:1;
++	u8 bEnIgnoreWlanAct:1;
++	u8 TxPowerLow:1;
++	u8 TxPowerHigh:1;
++	u8 eSCO_SCO:1;
++	u8 Master_Slave:1;
++
++	u8 ACL_TRx_TP_low;
++	u8 ACL_TRx_TP_high;
++};
++
++#define HCIOPCODE(_OCF, _OGF)     ((_OGF)<<10|(_OCF))
++#define HCIOPCODELOW(_OCF, _OGF)	(u8)(HCIOPCODE(_OCF, _OGF) & 0x00ff)
++#define HCIOPCODEHIGHT(_OCF, _OGF) (u8)(HCIOPCODE(_OCF, _OGF)>>8)
++#define HCI_OGF(opCode)  (unsigned char)((0xFC00 & (opCode)) >> 10)
++#define HCI_OCF(opCode)  (0x3FF & (opCode))
++
++
++typedef enum _HCI_STATUS {
++	HCI_STATUS_SUCCESS										= 0x00, /* Success */
++	HCI_STATUS_UNKNOW_HCI_CMD								= 0x01, /* Unknown HCI Command */
++	HCI_STATUS_UNKNOW_CONNECT_ID							= 0X02, /* Unknown Connection Identifier */
++	HCI_STATUS_HW_FAIL										= 0X03, /* Hardware Failure */
++	HCI_STATUS_PAGE_TIMEOUT									= 0X04, /* Page Timeout */
++	HCI_STATUS_AUTH_FAIL										= 0X05, /* Authentication Failure */
++	HCI_STATUS_PIN_OR_KEY_MISSING							= 0X06, /* PIN or Key Missing */
++	HCI_STATUS_MEM_CAP_EXCEED								= 0X07, /* Memory Capacity Exceeded */
++	HCI_STATUS_CONNECT_TIMEOUT								= 0X08, /* Connection Timeout */
++	HCI_STATUS_CONNECT_LIMIT									= 0X09, /* Connection Limit Exceeded */
++	HCI_STATUS_SYN_CONNECT_LIMIT								= 0X0a, /* Synchronous Connection Limit To A Device Exceeded */
++	HCI_STATUS_ACL_CONNECT_EXISTS							= 0X0b, /* ACL Connection Already Exists */
++	HCI_STATUS_CMD_DISALLOW									= 0X0c, /* Command Disallowed */
++	HCI_STATUS_CONNECT_RJT_LIMIT_RESOURCE					= 0X0d, /* Connection Rejected due to Limited Resources */
++	HCI_STATUS_CONNECT_RJT_SEC_REASON						= 0X0e, /* Connection Rejected Due To Security Reasons */
++	HCI_STATUS_CONNECT_RJT_UNACCEPT_BD_ADDR				= 0X0f, /* Connection Rejected due to Unacceptable BD_ADDR */
++	HCI_STATUS_CONNECT_ACCEPT_TIMEOUT						= 0X10, /* Connection Accept Timeout Exceeded */
++	HCI_STATUS_UNSUPPORT_FEATURE_PARA_VALUE				= 0X11, /* Unsupported Feature or Parameter Value */
++	HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE					= 0X12, /* Invalid HCI Command Parameters */
++	HCI_STATUS_REMOTE_USER_TERMINATE_CONNECT				= 0X13, /* Remote User Terminated Connection */
++	HCI_STATUS_REMOTE_DEV_TERMINATE_LOW_RESOURCE			= 0X14, /* Remote Device Terminated Connection due to Low Resources */
++	HCI_STATUS_REMOTE_DEV_TERMINATE_CONNECT_POWER_OFF	= 0X15, /* Remote Device Terminated Connection due to Power Off */
++	HCI_STATUS_CONNECT_TERMINATE_LOCAL_HOST				= 0X16, /* Connection Terminated By Local Host */
++	HCI_STATUS_REPEATE_ATTEMPT								= 0X17, /* Repeated Attempts */
++	HCI_STATUS_PAIR_NOT_ALLOW								= 0X18, /* Pairing Not Allowed */
++	HCI_STATUS_UNKNOW_LMP_PDU								= 0X19, /* Unknown LMP PDU */
++	HCI_STATUS_UNSUPPORT_REMOTE_LMP_FEATURE				= 0X1a, /* Unsupported Remote Feature / Unsupported LMP Feature */
++	HCI_STATUS_SOC_OFFSET_REJECT								= 0X1b, /* SCO Offset Rejected */
++	HCI_STATUS_SOC_INTERVAL_REJECT							= 0X1c, /* SCO Interval Rejected */
++	HCI_STATUS_SOC_AIR_MODE_REJECT							= 0X1d, /* SCO Air Mode Rejected */
++	HCI_STATUS_INVALID_LMP_PARA								= 0X1e, /* Invalid LMP Parameters */
++	HCI_STATUS_UNSPECIFIC_ERROR								= 0X1f, /* Unspecified Error */
++	HCI_STATUS_UNSUPPORT_LMP_PARA_VALUE					= 0X20, /* Unsupported LMP Parameter Value */
++	HCI_STATUS_ROLE_CHANGE_NOT_ALLOW						= 0X21, /* Role Change Not Allowed */
++	HCI_STATUS_LMP_RESPONSE_TIMEOUT							= 0X22, /* LMP Response Timeout */
++	HCI_STATUS_LMP_ERROR_TRANSACTION_COLLISION				= 0X23, /* LMP Error Transaction Collision */
++	HCI_STATUS_LMP_PDU_NOT_ALLOW							= 0X24, /* LMP PDU Not Allowed */
++	HCI_STATUS_ENCRYPTION_MODE_NOT_ALLOW					= 0X25, /* Encryption Mode Not Acceptable */
++	HCI_STATUS_LINK_KEY_CAN_NOT_CHANGE						= 0X26, /* Link Key Can Not be Changed */
++	HCI_STATUS_REQUEST_QOS_NOT_SUPPORT						= 0X27, /* Requested QoS Not Supported */
++	HCI_STATUS_INSTANT_PASSED								= 0X28, /* Instant Passed */
++	HCI_STATUS_PAIRING_UNIT_KEY_NOT_SUPPORT					= 0X29, /* Pairing With Unit Key Not Supported */
++	HCI_STATUS_DIFFERENT_TRANSACTION_COLLISION				= 0X2a, /* Different Transaction Collision */
++	HCI_STATUS_RESERVE_1										= 0X2b, /* Reserved */
++	HCI_STATUS_QOS_UNACCEPT_PARA							= 0X2c, /* QoS Unacceptable Parameter */
++	HCI_STATUS_QOS_REJECT										= 0X2d, /* QoS Rejected */
++	HCI_STATUS_CHNL_CLASSIFICATION_NOT_SUPPORT				= 0X2e, /* Channel Classification Not Supported */
++	HCI_STATUS_INSUFFICIENT_SECURITY							= 0X2f, /* Insufficient Security */
++	HCI_STATUS_PARA_OUT_OF_RANGE							= 0x30, /* Parameter Out Of Mandatory Range */
++	HCI_STATUS_RESERVE_2										= 0X31, /* Reserved */
++	HCI_STATUS_ROLE_SWITCH_PENDING							= 0X32, /* Role Switch Pending */
++	HCI_STATUS_RESERVE_3										= 0X33, /* Reserved */
++	HCI_STATUS_RESERVE_SOLT_VIOLATION						= 0X34, /* Reserved Slot Violation */
++	HCI_STATUS_ROLE_SWITCH_FAIL								= 0X35, /* Role Switch Failed */
++	HCI_STATUS_EXTEND_INQUIRY_RSP_TOO_LARGE				= 0X36, /* Extended Inquiry Response Too Large */
++	HCI_STATUS_SEC_SIMPLE_PAIRING_NOT_SUPPORT				= 0X37, /* Secure Simple Pairing Not Supported By Host. */
++	HCI_STATUS_HOST_BUSY_PAIRING								= 0X38, /* Host Busy - Pairing */
++	HCI_STATUS_CONNECT_REJ_NOT_SUIT_CHNL_FOUND			= 0X39, /* Connection Rejected due to No Suitable Channel Found */
++	HCI_STATUS_CONTROLLER_BUSY								= 0X3a /* CONTROLLER BUSY */
++} RTW_HCI_STATUS;
++
++#define HCI_EVENT_COMMAND_COMPLETE					0x0e
++
++#define OGF_EXTENSION									0X3f
++typedef enum HCI_EXTENSION_COMMANDS {
++	HCI_SET_ACL_LINK_DATA_FLOW_MODE				= 0x0010,
++	HCI_SET_ACL_LINK_STATUS							= 0x0020,
++	HCI_SET_SCO_LINK_STATUS							= 0x0030,
++	HCI_SET_RSSI_VALUE								= 0x0040,
++	HCI_SET_CURRENT_BLUETOOTH_STATUS				= 0x0041,
++
++	/* The following is for RTK8723 */
++	HCI_EXTENSION_VERSION_NOTIFY					= 0x0100,
++	HCI_LINK_STATUS_NOTIFY							= 0x0101,
++	HCI_BT_OPERATION_NOTIFY							= 0x0102,
++	HCI_ENABLE_WIFI_SCAN_NOTIFY						= 0x0103,
++	HCI_QUERY_RF_STATUS								= 0x0104,
++	HCI_BT_ABNORMAL_NOTIFY							= 0x0105,
++	HCI_BT_INFO_NOTIFY								= 0x0106,
++	HCI_BT_COEX_NOTIFY								= 0x0107,
++	HCI_BT_PATCH_VERSION_NOTIFY						= 0x0108,
++	HCI_BT_AFH_MAP_NOTIFY							= 0x0109,
++	HCI_BT_REGISTER_VALUE_NOTIFY					= 0x010a,
++
++	/* The following is for IVT */
++	HCI_WIFI_CURRENT_CHANNEL						= 0x0300,
++	HCI_WIFI_CURRENT_BANDWIDTH						= 0x0301,
++	HCI_WIFI_CONNECTION_STATUS						= 0x0302
++} RTW_HCI_EXT_CMD;
++
++#define HCI_EVENT_EXTENSION_RTK						0xfe
++typedef enum HCI_EXTENSION_EVENT_RTK {
++	HCI_EVENT_EXT_WIFI_SCAN_NOTIFY								= 0x01,
++	HCI_EVENT_EXT_WIFI_RF_STATUS_NOTIFY						= 0x02,
++	HCI_EVENT_EXT_BT_INFO_CONTROL								= 0x03,
++	HCI_EVENT_EXT_BT_COEX_CONTROL								= 0x04
++} RTW_HCI_EXT_EVENT;
++
++typedef enum _BT_TRAFFIC_MODE {
++	BT_MOTOR_EXT_BE		= 0x00, /* Best Effort. Default. for HCRP, PAN, SDP, RFCOMM-based profiles like FTP,OPP, SPP, DUN, etc. */
++	BT_MOTOR_EXT_GUL		= 0x01, /* Guaranteed Latency. This type of traffic is used e.g. for HID and AVRCP. */
++	BT_MOTOR_EXT_GUB		= 0X02, /* Guaranteed Bandwidth. */
++	BT_MOTOR_EXT_GULB	= 0X03  /* Guaranteed Latency and Bandwidth. for A2DP and VDP. */
++} BT_TRAFFIC_MODE;
++
++typedef enum _BT_TRAFFIC_MODE_PROFILE {
++	BT_PROFILE_NONE,
++	BT_PROFILE_A2DP,
++	BT_PROFILE_PAN	,
++	BT_PROFILE_HID,
++	BT_PROFILE_SCO
++} BT_TRAFFIC_MODE_PROFILE;
++
++typedef enum _HCI_EXT_BT_OPERATION {
++	HCI_BT_OP_NONE				= 0x0,
++	HCI_BT_OP_INQUIRY_START		= 0x1,
++	HCI_BT_OP_INQUIRY_FINISH		= 0x2,
++	HCI_BT_OP_PAGING_START		= 0x3,
++	HCI_BT_OP_PAGING_SUCCESS		= 0x4,
++	HCI_BT_OP_PAGING_UNSUCCESS	= 0x5,
++	HCI_BT_OP_PAIRING_START		= 0x6,
++	HCI_BT_OP_PAIRING_FINISH		= 0x7,
++	HCI_BT_OP_BT_DEV_ENABLE		= 0x8,
++	HCI_BT_OP_BT_DEV_DISABLE		= 0x9,
++	HCI_BT_OP_MAX
++} HCI_EXT_BT_OPERATION, *PHCI_EXT_BT_OPERATION;
++
++typedef struct _BT_MGNT {
++	BOOLEAN				bBTConnectInProgress;
++	BOOLEAN				bLogLinkInProgress;
++	BOOLEAN				bPhyLinkInProgress;
++	BOOLEAN				bPhyLinkInProgressStartLL;
++	u8				BtCurrentPhyLinkhandle;
++	u16				BtCurrentLogLinkhandle;
++	u8				CurrentConnectEntryNum;
++	u8				DisconnectEntryNum;
++	u8				CurrentBTConnectionCnt;
++	BT_CONNECT_TYPE		BTCurrentConnectType;
++	BT_CONNECT_TYPE		BTReceiveConnectPkt;
++	u8				BTAuthCount;
++	u8				BTAsocCount;
++	BOOLEAN				bStartSendSupervisionPkt;
++	BOOLEAN				BtOperationOn;
++	BOOLEAN				BTNeedAMPStatusChg;
++	BOOLEAN				JoinerNeedSendAuth;
++	HCI_PHY_LINK_BSS_INFO	bssDesc;
++	HCI_EXT_CONFIG		ExtConfig;
++	BOOLEAN				bNeedNotifyAMPNoCap;
++	BOOLEAN				bCreateSpportQos;
++	BOOLEAN				bSupportProfile;
++	u8				BTChannel;
++	BOOLEAN				CheckChnlIsSuit;
++	BOOLEAN				bBtScan;
++	BOOLEAN				btLogoTest;
++	BOOLEAN				bRfStatusNotified;
++	BOOLEAN				bBtRsvedPageDownload;
++} BT_MGNT, *PBT_MGNT;
++
++struct bt_coex_info {
++	/* For Kernel Socket */
++	struct socket *udpsock;
++	struct sockaddr_in wifi_sockaddr; /*wifi socket*/
++	struct sockaddr_in bt_sockaddr;/* BT socket */
++	struct sock *sk_store;/*back up socket for UDP RX int*/
++
++	/* store which socket is OK */
++	u8 sock_open;
++
++	u8 BT_attend;
++	u8 is_exist; /* socket exist */
++	BT_MGNT BtMgnt;
++	struct workqueue_struct *btcoex_wq;
++	struct delayed_work recvmsg_work;
++};
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++
++#define	PACKET_NORMAL			0
++#define	PACKET_DHCP				1
++#define	PACKET_ARP				2
++#define	PACKET_EAPOL			3
++
++void rtw_btcoex_Initialize(PADAPTER);
++void rtw_btcoex_PowerOnSetting(PADAPTER padapter);
++void rtw_btcoex_AntInfoSetting(PADAPTER padapter);
++void rtw_btcoex_PowerOffSetting(PADAPTER padapter);
++void rtw_btcoex_PreLoadFirmware(PADAPTER padapter);
++void rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly);
++void rtw_btcoex_IpsNotify(PADAPTER, u8 type);
++void rtw_btcoex_LpsNotify(PADAPTER, u8 type);
++void rtw_btcoex_ScanNotify(PADAPTER, u8 type);
++void rtw_btcoex_MediaStatusNotify(PADAPTER, u8 mediaStatus);
++void rtw_btcoex_SpecialPacketNotify(PADAPTER, u8 pktType);
++void rtw_btcoex_IQKNotify(PADAPTER padapter, u8 state);
++void rtw_btcoex_BtInfoNotify(PADAPTER, u8 length, u8 *tmpBuf);
++void rtw_btcoex_BtMpRptNotify(PADAPTER, u8 length, u8 *tmpBuf);
++void rtw_btcoex_SuspendNotify(PADAPTER, u8 state);
++void rtw_btcoex_HaltNotify(PADAPTER);
++void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type);
++void rtw_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length);
++void rtw_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id);
++void rtw_btcoex_SwitchBtTRxMask(PADAPTER);
++void rtw_btcoex_Switch(PADAPTER, u8 enable);
++u8 rtw_btcoex_IsBtDisabled(PADAPTER);
++void rtw_btcoex_Handler(PADAPTER);
++s32 rtw_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter);
++s32 rtw_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER);
++u32 rtw_btcoex_GetAMPDUSize(PADAPTER);
++void rtw_btcoex_SetManualControl(PADAPTER, u8 bmanual);
++u8 rtw_btcoex_1Ant(PADAPTER);
++u8 rtw_btcoex_IsBtControlLps(PADAPTER);
++u8 rtw_btcoex_IsLpsOn(PADAPTER);
++u8 rtw_btcoex_RpwmVal(PADAPTER);
++u8 rtw_btcoex_LpsVal(PADAPTER);
++u32 rtw_btcoex_GetRaMask(PADAPTER);
++u8 rtw_btcoex_query_reduced_wl_pwr_lvl(PADAPTER padapter);
++void rtw_btcoex_set_reduced_wl_pwr_lvl(PADAPTER padapter, u8 val);
++void rtw_btcoex_do_reduce_wl_pwr_lvl(PADAPTER padapter);
++void rtw_btcoex_RecordPwrMode(PADAPTER, u8 *pCmdBuf, u8 cmdLen);
++void rtw_btcoex_DisplayBtCoexInfo(PADAPTER, u8 *pbuf, u32 bufsize);
++void rtw_btcoex_SetDBG(PADAPTER, u32 *pDbgModule);
++u32 rtw_btcoex_GetDBG(PADAPTER, u8 *pStrBuf, u32 bufSize);
++u8 rtw_btcoex_IncreaseScanDeviceNum(PADAPTER);
++u8 rtw_btcoex_IsBtLinkExist(PADAPTER);
++void rtw_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON);
++
++#ifdef CONFIG_RF4CE_COEXIST
++void rtw_btcoex_SetRf4ceLinkState(PADAPTER padapter, u8 state);
++u8 rtw_btcoex_GetRf4ceLinkState(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++void rtw_btcoex_SetBtPatchVersion(PADAPTER padapter, u16 btHciVer, u16 btPatchVer);
++void rtw_btcoex_SetHciVersion(PADAPTER  padapter, u16 hciVersion);
++void rtw_btcoex_StackUpdateProfileInfo(void);
++void rtw_btcoex_init_socket(_adapter *padapter);
++void rtw_btcoex_close_socket(_adapter *padapter);
++void rtw_btcoex_dump_tx_msg(u8 *tx_msg, u8 len, u8 *msg_name);
++u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool force);
++u8 rtw_btcoex_create_kernel_socket(_adapter *padapter);
++void rtw_btcoex_close_kernel_socket(_adapter *padapter);
++void rtw_btcoex_recvmsgbysocket(void *data);
++u16 rtw_btcoex_parse_recv_data(u8 *msg, u8 msg_size);
++u8 rtw_btcoex_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length);
++void rtw_btcoex_parse_hci_cmd(_adapter *padapter, u8 *cmd, u16 len);
++void rtw_btcoex_SendEventExtBtCoexControl(PADAPTER Adapter, u8 bNeedDbgRsp, u8 dataLen, void *pData);
++void rtw_btcoex_SendEventExtBtInfoControl(PADAPTER Adapter, u8 dataLen, void *pData);
++void rtw_btcoex_SendScanNotify(PADAPTER padapter, u8 scanType);
++#define BT_SendEventExtBtCoexControl(Adapter, bNeedDbgRsp, dataLen, pData) rtw_btcoex_SendEventExtBtCoexControl(Adapter, bNeedDbgRsp, dataLen, pData)
++#define BT_SendEventExtBtInfoControl(Adapter, dataLen, pData) rtw_btcoex_SendEventExtBtInfoControl(Adapter, dataLen, pData)
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++u16 rtw_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data);
++u16 rtw_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val);
++u8 rtw_btcoex_get_reduce_wl_txpwr(PADAPTER padapter);
++u8 rtw_btcoex_get_bt_coexist(PADAPTER padapter);
++u8 rtw_btcoex_get_chip_type(PADAPTER padapter);
++u8 rtw_btcoex_get_pg_ant_num(PADAPTER padapter);
++u8 rtw_btcoex_get_pg_single_ant_path(PADAPTER padapter);
++u8 rtw_btcoex_get_pg_rfe_type(PADAPTER padapter);
++u8 rtw_btcoex_is_tfbga_package_type(PADAPTER padapter);
++u8 rtw_btcoex_get_ant_div_cfg(PADAPTER padapter);
++u16 rtw_btcoex_btset_testmode(PADAPTER padapter, u8 type);
++
++/* ==================================================
++ * Below Functions are called by BT-Coex
++ * ================================================== */
++void rtw_btcoex_rx_ampdu_apply(PADAPTER padapter);
++void rtw_btcoex_LPS_Enter(PADAPTER padapter);
++u8 rtw_btcoex_LPS_Leave(PADAPTER padapter);
++
++#endif /* __RTW_BTCOEX_H__ */
++#endif /* CONFIG_BT_COEXIST */
++
++void rtw_btcoex_set_ant_info(PADAPTER padapter);
++void rtw_btcoex_connect_notify(PADAPTER, u8 join_type);
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_btcoex_wifionly.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_btcoex_wifionly.h
+new file mode 100644
+index 000000000..93087ebe0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_btcoex_wifionly.h
+@@ -0,0 +1,24 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_BTCOEX_WIFIONLY_H__
++#define __RTW_BTCOEX_WIFIONLY_H__
++
++void rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter);
++void rtw_btcoex_wifionly_scan_notify(PADAPTER padapter);
++void rtw_btcoex_wifionly_connect_notify(PADAPTER padapter);
++void rtw_btcoex_wifionly_hw_config(PADAPTER padapter);
++void rtw_btcoex_wifionly_initialize(PADAPTER padapter);
++void rtw_btcoex_wifionly_AntInfoSetting(PADAPTER padapter);
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_byteorder.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_byteorder.h
+new file mode 100644
+index 000000000..8e6bb7a6d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_byteorder.h
+@@ -0,0 +1,33 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTL871X_BYTEORDER_H_
++#define _RTL871X_BYTEORDER_H_
++
++
++#if defined(CONFIG_LITTLE_ENDIAN) && defined (CONFIG_BIG_ENDIAN)
++	#error "Shall be CONFIG_LITTLE_ENDIAN or CONFIG_BIG_ENDIAN, but not both!\n"
++#endif
++
++#if defined(CONFIG_LITTLE_ENDIAN)
++	#ifndef CONFIG_PLATFORM_MSTAR389
++		#include <byteorder/little_endian.h>
++	#endif
++#elif defined (CONFIG_BIG_ENDIAN)
++	#include <byteorder/big_endian.h>
++#else
++	#  error "Must be LITTLE/BIG Endian Host"
++#endif
++
++#endif /* _RTL871X_BYTEORDER_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_cmd.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_cmd.h
+new file mode 100644
+index 000000000..d7e87b926
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_cmd.h
+@@ -0,0 +1,778 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_CMD_H_
++#define __RTW_CMD_H_
++
++
++#define C2H_MEM_SZ (16*1024)
++
++#define FREE_CMDOBJ_SZ	128
++
++#define MAX_CMDSZ	1536
++#define MAX_RSPSZ	512
++#define MAX_EVTSZ	1024
++
++#define CMDBUFF_ALIGN_SZ 512
++
++struct cmd_obj {
++	_adapter *padapter;
++	u16	cmdcode;
++	u8	res;
++	u8	*parmbuf;
++	u32	cmdsz;
++	u8	*rsp;
++	u32	rspsz;
++	struct submit_ctx *sctx;
++	u8 no_io;
++	/* _sema 	cmd_sem; */
++	_list	list;
++};
++
++/* cmd flags */
++enum {
++	RTW_CMDF_DIRECTLY = BIT0,
++	RTW_CMDF_WAIT_ACK = BIT1,
++};
++
++struct cmd_priv {
++	_sema	cmd_queue_sema;
++	/* _sema	cmd_done_sema; */
++	_sema	start_cmdthread_sema;
++
++	_queue	cmd_queue;
++	u8	cmd_seq;
++	u8	*cmd_buf;	/* shall be non-paged, and 4 bytes aligned */
++	u8	*cmd_allocated_buf;
++	u8	*rsp_buf;	/* shall be non-paged, and 4 bytes aligned		 */
++	u8	*rsp_allocated_buf;
++	u32	cmd_issued_cnt;
++	u32	cmd_done_cnt;
++	u32	rsp_cnt;
++	ATOMIC_T cmdthd_running;
++	/* u8 cmdthd_running; */
++
++	_adapter *padapter;
++	_mutex sctx_mutex;
++};
++
++#ifdef CONFIG_EVENT_THREAD_MODE
++struct evt_obj {
++	u16	evtcode;
++	u8	res;
++	u8	*parmbuf;
++	u32	evtsz;
++	_list	list;
++};
++#endif
++
++struct	evt_priv {
++#ifdef CONFIG_EVENT_THREAD_MODE
++	_sema	evt_notify;
++
++	_queue	evt_queue;
++#endif
++
++#ifdef CONFIG_FW_C2H_REG
++	#define CONFIG_C2H_WK
++#endif
++
++#ifdef CONFIG_C2H_WK
++	_workitem c2h_wk;
++	bool c2h_wk_alive;
++	struct rtw_cbuf *c2h_queue;
++	#define C2H_QUEUE_MAX_LEN 10
++#endif
++
++#ifdef CONFIG_H2CLBK
++	_sema	lbkevt_done;
++	u8	lbkevt_limit;
++	u8	lbkevt_num;
++	u8	*cmdevt_parm;
++#endif
++	ATOMIC_T event_seq;
++	u8	*evt_buf;	/* shall be non-paged, and 4 bytes aligned		 */
++	u8	*evt_allocated_buf;
++	u32	evt_done_cnt;
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	u8	*c2h_mem;
++	u8	*allocated_c2h_mem;
++#endif
++
++};
++
++#define init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code) \
++	do {\
++		_rtw_init_listhead(&pcmd->list);\
++		pcmd->cmdcode = code;\
++		pcmd->parmbuf = (u8 *)(pparm);\
++		pcmd->cmdsz = sizeof (*pparm);\
++		pcmd->rsp = NULL;\
++		pcmd->rspsz = 0;\
++	} while (0)
++
++#define init_h2fwcmd_w_parm_no_parm_rsp(pcmd, code) \
++	do {\
++		_rtw_init_listhead(&pcmd->list);\
++		pcmd->cmdcode = code;\
++		pcmd->parmbuf = NULL;\
++		pcmd->cmdsz = 0;\
++		pcmd->rsp = NULL;\
++		pcmd->rspsz = 0;\
++	} while (0)
++
++struct P2P_PS_Offload_t {
++	u8 Offload_En:1;
++	u8 role:1; /* 1: Owner, 0: Client */
++	u8 CTWindow_En:1;
++	u8 NoA0_En:1;
++	u8 NoA1_En:1;
++	u8 AllStaSleep:1; /* Only valid in Owner */
++	u8 discovery:1;
++	u8 rsvd:1;
++#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
++	u8 p2p_macid:7;
++	u8 disable_close_rf:1; /*1: not close RF but just pause p2p_macid when NoA duration*/
++#endif /* CONFIG_P2P_PS_NOA_USE_MACID_SLEEP */
++};
++
++struct P2P_PS_CTWPeriod_t {
++	u8 CTWPeriod;	/* TU */
++};
++
++#ifdef CONFIG_P2P_WOWLAN
++
++struct P2P_WoWlan_Offload_t {
++	u8 Disconnect_Wkup_Drv:1;
++	u8 role:2;
++	u8 Wps_Config[2];
++};
++
++#endif /* CONFIG_P2P_WOWLAN */
++
++extern u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *obj);
++extern struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv);
++extern void rtw_free_cmd_obj(struct cmd_obj *pcmd);
++
++#ifdef CONFIG_EVENT_THREAD_MODE
++extern u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj);
++extern struct evt_obj *rtw_dequeue_evt(_queue *queue);
++extern void rtw_free_evt_obj(struct evt_obj *pcmd);
++#endif
++
++void rtw_stop_cmd_thread(_adapter *adapter);
++thread_return rtw_cmd_thread(thread_context context);
++
++extern u32 rtw_init_cmd_priv(struct cmd_priv *pcmdpriv);
++extern void rtw_free_cmd_priv(struct cmd_priv *pcmdpriv);
++
++extern u32 rtw_init_evt_priv(struct evt_priv *pevtpriv);
++extern void rtw_free_evt_priv(struct evt_priv *pevtpriv);
++extern void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv);
++extern void rtw_evt_notify_isr(struct evt_priv *pevtpriv);
++#ifdef CONFIG_P2P
++u8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType);
++
++#ifdef CONFIG_IOCTL_CFG80211
++struct p2p_roch_parm {
++	u64 cookie;
++	struct wireless_dev *wdev;
++	struct ieee80211_channel ch;
++	enum nl80211_channel_type ch_type;
++	unsigned int duration;
++};
++
++u8 p2p_roch_cmd(_adapter *adapter
++	, u64 cookie, struct wireless_dev *wdev
++	, struct ieee80211_channel *ch, enum nl80211_channel_type ch_type
++	, unsigned int duration
++	, u8 flags
++);
++u8 p2p_cancel_roch_cmd(_adapter *adapter, u64 cookie, struct wireless_dev *wdev, u8 flags);
++
++#endif /* CONFIG_IOCTL_CFG80211 */
++#endif /* CONFIG_P2P */
++
++#ifdef CONFIG_IOCTL_CFG80211 
++u8 rtw_mgnt_tx_cmd(_adapter *adapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack, u8 flags);
++struct mgnt_tx_parm {
++	u8 tx_ch;
++	u8 no_cck;
++	const u8 *buf;
++	size_t len;
++	int wait_ack;
++};
++#endif
++
++enum rtw_drvextra_cmd_id {
++	NONE_WK_CID,
++	STA_MSTATUS_RPT_WK_CID,
++	DYNAMIC_CHK_WK_CID,
++	DM_CTRL_WK_CID,
++	PBC_POLLING_WK_CID,
++	POWER_SAVING_CTRL_WK_CID,/* IPS,AUTOSuspend */
++	LPS_CTRL_WK_CID,
++	ANT_SELECT_WK_CID,
++	P2P_PS_WK_CID,
++	P2P_PROTO_WK_CID,
++	CHECK_HIQ_WK_CID,/* for softap mode, check hi queue if empty */
++	C2H_WK_CID,
++	RTP_TIMER_CFG_WK_CID,
++	RESET_SECURITYPRIV, /* add for CONFIG_IEEE80211W, none 11w also can use */
++	FREE_ASSOC_RESOURCES, /* add for CONFIG_IEEE80211W, none 11w also can use */
++	DM_IN_LPS_WK_CID,
++	DM_RA_MSK_WK_CID, /* add for STA update RAMask when bandwith change. */
++	BEAMFORMING_WK_CID,
++	LPS_CHANGE_DTIM_CID,
++	BTINFO_WK_CID,
++	BTC_REDUCE_WL_TXPWR_CID,
++	DFS_RADAR_DETECT_WK_CID,
++	DFS_RADAR_DETECT_EN_DEC_WK_CID,
++	SESSION_TRACKER_WK_CID,
++	EN_HW_UPDATE_TSF_WK_CID,
++	PERIOD_TSF_UPDATE_END_WK_CID,
++	TEST_H2C_CID,
++	MP_CMD_WK_CID,
++	CUSTOMER_STR_WK_CID,
++#ifdef CONFIG_RTW_REPEATER_SON
++	RSON_SCAN_WK_CID,
++#endif
++	MGNT_TX_WK_CID,
++	REQ_PER_CMD_WK_CID,
++	SSMPS_WK_CID,
++#ifdef CONFIG_CTRL_TXSS_BY_TP
++	TXSS_WK_CID,
++#endif
++	AC_PARM_CMD_WK_CID,
++#ifdef CONFIG_AP_MODE
++	STOP_AP_WK_CID,
++#endif
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	TBTX_CONTROL_TX_WK_CID,
++#endif
++	MAX_WK_CID
++};
++
++enum LPS_CTRL_TYPE {
++	LPS_CTRL_SCAN = 0,
++	LPS_CTRL_JOINBSS = 1,
++	LPS_CTRL_CONNECT = 2,
++	LPS_CTRL_DISCONNECT = 3,
++	LPS_CTRL_SPECIAL_PACKET = 4,
++	LPS_CTRL_LEAVE = 5,
++	LPS_CTRL_TRAFFIC_BUSY = 6,
++	LPS_CTRL_TX_TRAFFIC_LEAVE = 7,
++	LPS_CTRL_RX_TRAFFIC_LEAVE = 8,
++	LPS_CTRL_ENTER = 9,
++	LPS_CTRL_LEAVE_CFG80211_PWRMGMT = 10,
++	LPS_CTRL_LEAVE_SET_OPTION = 11,
++};
++
++enum STAKEY_TYPE {
++	GROUP_KEY		= 0,
++	UNICAST_KEY		= 1,
++	TDLS_KEY		= 2,
++};
++
++enum RFINTFS {
++	SWSI,
++	HWSI,
++	HWPI,
++};
++
++
++/*
++Caller Mode: Infra, Ad-Hoc
++
++Notes: To join the specified bss
++
++Command Event Mode
++
++*/
++struct joinbss_parm {
++	WLAN_BSSID_EX network;
++};
++
++/*
++Caller Mode: Infra, Ad-HoC(C)
++
++Notes: To disconnect the current associated BSS
++
++Command Mode
++
++*/
++struct disconnect_parm {
++	u32 deauth_timeout_ms;
++};
++
++/*
++Caller Mode: AP, Ad-HoC(M)
++
++Notes: To create a BSS
++
++Command Mode
++*/
++struct createbss_parm {
++	bool adhoc;
++
++	/* used by AP/Mesh mode now */
++	u8 ifbmp;
++	u8 excl_ifbmp;
++	s16 req_ch;
++	s8 req_bw;
++	s8 req_offset;
++};
++
++
++struct	setopmode_parm {
++	u8	mode;
++	u8	rsvd[3];
++};
++
++/*
++Caller Mode: AP, Ad-HoC, Infra
++
++Notes: To ask RTL8711 performing site-survey
++
++Command-Event Mode
++
++*/
++
++#define RTW_SSID_SCAN_AMOUNT 9 /* for WEXT_CSCAN_AMOUNT 9 */
++#define RTW_CHANNEL_SCAN_AMOUNT (14+37)
++struct sitesurvey_parm {
++	sint scan_mode;	/* active: 1, passive: 0 */
++	/* sint bsslimit;	// 1 ~ 48 */
++	u8 ssid_num;
++	u8 ch_num;
++	NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT];
++	struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT];
++
++	u32 token; 	/* 80211k use it to identify caller */
++	u16 duration;	/* 0: use default, otherwise: channel scan time */
++	u8 igi;		/* 0: use defalut */
++	u8 bw;		/* 0: use default */
++
++	bool acs; /* aim to trigger channel selection when scan done */
++};
++
++/*
++Caller Mode: Any
++
++Notes: To set the auth type of RTL8711. open/shared/802.1x
++
++Command Mode
++
++*/
++struct setauth_parm {
++	u8 mode;  /* 0: legacy open, 1: legacy shared 2: 802.1x */
++	u8 _1x;   /* 0: PSK, 1: TLS */
++	u8 rsvd[2];
++};
++
++/*
++Caller Mode: Infra
++
++a. algorithm: wep40, wep104, tkip & aes
++b. keytype: grp key/unicast key
++c. key contents
++
++when shared key ==> keyid is the camid
++when 802.1x ==> keyid [0:1] ==> grp key
++when 802.1x ==> keyid > 2 ==> unicast key
++
++*/
++struct setkey_parm {
++	u8	algorithm;	/* encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 */
++	u8	keyid;
++	u8	set_tx;		/* 1: main tx key for wep. 0: other key. */
++	u8	key[32];	/* this could be 40 or 104 */
++};
++
++/*
++When in AP or Ad-Hoc mode, this is used to
++allocate an sw/hw entry for a newly associated sta.
++
++Command
++
++when shared key ==> algorithm/keyid
++
++*/
++struct set_stakey_parm {
++	u8 addr[ETH_ALEN];
++	u8 algorithm;
++	u8 keyid;
++	u8 key[32];
++	u8 gk;
++};
++
++struct set_stakey_rsp {
++	u8	addr[ETH_ALEN];
++	u8	keyid;
++	u8	rsvd;
++};
++
++struct Tx_Beacon_param {
++	WLAN_BSSID_EX network;
++};
++
++/*
++	Notes: This command is used for H2C/C2H loopback testing
++
++	mac[0] == 0
++	==> CMD mode, return H2C_SUCCESS.
++	The following condition must be ture under CMD mode
++		mac[1] == mac[4], mac[2] == mac[3], mac[0]=mac[5]= 0;
++		s0 == 0x1234, s1 == 0xabcd, w0 == 0x78563412, w1 == 0x5aa5def7;
++		s2 == (b1 << 8 | b0);
++
++	mac[0] == 1
++	==> CMD_RSP mode, return H2C_SUCCESS_RSP
++
++	The rsp layout shall be:
++	rsp:			parm:
++		mac[0]  =   mac[5];
++		mac[1]  =   mac[4];
++		mac[2]  =   mac[3];
++		mac[3]  =   mac[2];
++		mac[4]  =   mac[1];
++		mac[5]  =   mac[0];
++		s0		=   s1;
++		s1		=   swap16(s0);
++		w0		=	swap32(w1);
++		b0		=	b1
++		s2		=	s0 + s1
++		b1		=	b0
++		w1		=	w0
++
++	mac[0] ==	2
++	==> CMD_EVENT mode, return	H2C_SUCCESS
++	The event layout shall be:
++	event:			parm:
++		mac[0]  =   mac[5];
++		mac[1]  =   mac[4];
++		mac[2]  =   event's sequence number, starting from 1 to parm's marc[3]
++		mac[3]  =   mac[2];
++		mac[4]  =   mac[1];
++		mac[5]  =   mac[0];
++		s0		=   swap16(s0) - event.mac[2];
++		s1		=   s1 + event.mac[2];
++		w0		=	swap32(w0);
++		b0		=	b1
++		s2		=	s0 + event.mac[2]
++		b1		=	b0
++		w1		=	swap32(w1) - event.mac[2];
++
++		parm->mac[3] is the total event counts that host requested.
++
++
++	event will be the same with the cmd's param.
++
++*/
++
++#ifdef CONFIG_H2CLBK
++
++struct seth2clbk_parm {
++	u8 mac[6];
++	u16	s0;
++	u16	s1;
++	u32	w0;
++	u8	b0;
++	u16  s2;
++	u8	b1;
++	u32	w1;
++};
++
++struct geth2clbk_parm {
++	u32 rsv;
++};
++
++struct geth2clbk_rsp {
++	u8	mac[6];
++	u16	s0;
++	u16	s1;
++	u32	w0;
++	u8	b0;
++	u16	s2;
++	u8	b1;
++	u32	w1;
++};
++
++#endif	/* CONFIG_H2CLBK */
++
++/* CMD param Formart for driver extra cmd handler */
++struct drvextra_cmd_parm {
++	int ec_id; /* extra cmd id */
++	int type; /* Can use this field as the type id or command size */
++	int size; /* buffer size */
++	unsigned char *pbuf;
++};
++
++/*------------------- Below are used for RF/BB tunning ---------------------*/
++struct addBaReq_parm {
++	unsigned int tid;
++	u8	addr[ETH_ALEN];
++};
++
++struct addBaRsp_parm {
++	unsigned int tid;
++	unsigned int start_seq;
++	u8 addr[ETH_ALEN];
++	u8 status;
++	u8 size;
++};
++
++struct set_ch_parm {
++	u8 ch;
++	u8 bw;
++	u8 ch_offset;
++};
++
++struct SetChannelPlan_param {
++	const struct country_chplan *country_ent;
++	u8 channel_plan;
++};
++
++struct LedBlink_param {
++	void *pLed;
++};
++
++struct TDLSoption_param {
++	u8 addr[ETH_ALEN];
++	u8 option;
++};
++
++struct RunInThread_param {
++	void (*func)(void *);
++	void *context;
++};
++
++
++#define GEN_CMD_CODE(cmd)	cmd ## _CMD_
++
++
++/*
++
++Result:
++0x00: success
++0x01: sucess, and check Response.
++0x02: cmd ignored due to duplicated sequcne number
++0x03: cmd dropped due to invalid cmd code
++0x04: reserved.
++
++*/
++
++#define H2C_RSP_OFFSET			512
++
++#define H2C_SUCCESS			0x00
++#define H2C_SUCCESS_RSP			0x01
++#define H2C_DUPLICATED			0x02
++#define H2C_DROPPED			0x03
++#define H2C_PARAMETERS_ERROR		0x04
++#define H2C_REJECTED			0x05
++#define H2C_CMD_OVERFLOW		0x06
++#define H2C_RESERVED			0x07
++#define H2C_ENQ_HEAD			0x08
++#define H2C_ENQ_HEAD_FAIL		0x09
++#define H2C_CMD_FAIL			0x0A
++
++void rtw_init_sitesurvey_parm(_adapter *padapter, struct sitesurvey_parm *pparm);
++u8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm);
++u8 rtw_create_ibss_cmd(_adapter *adapter, int flags);
++u8 rtw_startbss_cmd(_adapter *adapter, int flags);
++
++#define REQ_CH_NONE		-1
++#define REQ_CH_INT_INFO	-2
++#define REQ_BW_NONE		-1
++#define REQ_BW_ORI		-2
++#define REQ_OFFSET_NONE	-1
++
++u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags
++	, u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset);
++
++struct sta_info;
++extern u8 rtw_setstakey_cmd(_adapter  *padapter, struct sta_info *sta, u8 key_type, bool enqueue);
++extern u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue);
++
++extern u8 rtw_joinbss_cmd(_adapter  *padapter, struct wlan_network *pnetwork);
++u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags);
++#ifdef CONFIG_AP_MODE
++u8 rtw_stop_ap_cmd(_adapter *adapter, u8 flags);
++#endif
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++u8 rtw_tx_control_cmd(_adapter *adapter);
++#endif
++extern u8 rtw_setopmode_cmd(_adapter  *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags);
++
++extern u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr);
++extern u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u16 start_seq);
++/* add for CONFIG_IEEE80211W, none 11w also can use */
++extern u8 rtw_reset_securitypriv_cmd(_adapter *padapter);
++extern u8 rtw_free_assoc_resources_cmd(_adapter *padapter, u8 lock_scanned_queue, int flags);
++extern u8 rtw_dynamic_chk_wk_cmd(_adapter *adapter);
++
++u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 flags);
++u8 rtw_lps_ctrl_leave_set_level_cmd(_adapter *adapter, u8 lps_level, u8 flags);
++#ifdef CONFIG_LPS_1T1R
++u8 rtw_lps_ctrl_leave_set_1t1r_cmd(_adapter *adapter, u8 lps_1t1r, u8 flags);
++#endif
++u8 rtw_dm_in_lps_wk_cmd(_adapter *padapter);
++u8 rtw_lps_change_dtim_cmd(_adapter *padapter, u8 dtim);
++
++#if (RATE_ADAPTIVE_SUPPORT == 1)
++u8 rtw_rpt_timer_cfg_cmd(_adapter *padapter, u16 minRptTime);
++#endif
++
++#ifdef CONFIG_ANTENNA_DIVERSITY
++extern  u8 rtw_antenna_select_cmd(_adapter *padapter, u8 antenna, u8 enqueue);
++#endif
++
++u8 rtw_dm_ra_mask_wk_cmd(_adapter *padapter, u8 *psta);
++
++extern u8 rtw_ps_cmd(_adapter *padapter);
++
++#if CONFIG_DFS
++void rtw_dfs_ch_switch_hdl(struct dvobj_priv *dvobj);
++#endif
++
++#ifdef CONFIG_AP_MODE
++u8 rtw_chk_hi_queue_cmd(_adapter *padapter);
++#ifdef CONFIG_DFS_MASTER
++u8 rtw_dfs_rd_cmd(_adapter *adapter, bool enqueue);
++void rtw_dfs_rd_timer_hdl(void *ctx);
++void rtw_dfs_rd_en_decision(_adapter *adapter, u8 mlme_act, u8 excl_ifbmp);
++u8 rtw_dfs_rd_en_decision_cmd(_adapter *adapter);
++#endif /* CONFIG_DFS_MASTER */
++#endif /* CONFIG_AP_MODE */
++
++#ifdef CONFIG_BT_COEXIST
++u8 rtw_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length);
++u8 rtw_btc_reduce_wl_txpwr_cmd(_adapter *adapter, u32 val);
++#endif
++
++u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len);
++
++u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter);
++u8 rtw_periodic_tsf_update_end_cmd(_adapter *adapter);
++
++u8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags);
++
++u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 swconfig);
++u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, u8 swconfig);
++
++extern u8 rtw_led_blink_cmd(_adapter *padapter, void *pLed);
++extern u8 rtw_set_csa_cmd(_adapter *adapter);
++extern u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option);
++
++u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags);
++
++#ifdef CONFIG_RTW_CUSTOMER_STR
++u8 rtw_customer_str_req_cmd(_adapter *adapter);
++u8 rtw_customer_str_write_cmd(_adapter *adapter, const u8 *cstr);
++#endif
++
++#ifdef CONFIG_FW_C2H_REG
++u8 rtw_c2h_reg_wk_cmd(_adapter *adapter, u8 *c2h_evt);
++#endif
++#ifdef CONFIG_FW_C2H_PKT
++u8 rtw_c2h_packet_wk_cmd(_adapter *adapter, u8 *c2h_evt, u16 length);
++#endif
++
++#ifdef CONFIG_RTW_REPEATER_SON
++#define RSON_SCAN_PROCESS		10
++#define RSON_SCAN_DISABLE		11
++u8 rtw_rson_scan_wk_cmd(_adapter *adapter, int op);
++#endif
++
++u8 rtw_run_in_thread_cmd(_adapter *adapter, void (*func)(void *), void *context);
++u8 rtw_run_in_thread_cmd_wait(_adapter *adapter, void (*func)(void *), void *context, s32 timeout_ms);
++
++struct ssmps_cmd_parm {
++	struct sta_info *sta;
++	u8 smps;
++};
++u8 rtw_ssmps_wk_cmd(_adapter *adapter, struct sta_info *sta, u8 smps, u8 enqueue);
++
++u8 session_tracker_chk_cmd(_adapter *adapter, struct sta_info *sta);
++u8 session_tracker_add_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);
++u8 session_tracker_del_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);
++
++u8 set_txq_params_cmd(_adapter *adapter, u32 ac_parm, u8 ac_type);
++
++#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW)
++u8 rtw_req_per_cmd(_adapter * adapter);
++#endif
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++u8 rtw_tbtx_chk_cmd(_adapter *adapter);
++u8 rtw_tbtx_token_dispatch_cmd(_adapter *adapter);
++#endif
++#ifdef CONFIG_CTRL_TXSS_BY_TP
++struct txss_cmd_parm {
++	struct sta_info *sta;
++	bool tx_1ss;
++};
++
++void rtw_ctrl_txss_update_mimo_type(_adapter *adapter, struct sta_info *sta);
++u8 rtw_ctrl_txss(_adapter *adapter, struct sta_info *sta, bool tx_1ss);
++void rtw_ctrl_tx_ss_by_tp(_adapter *adapter, u8 from_timer);
++
++#ifdef DBG_CTRL_TXSS
++void dbg_ctrl_txss(_adapter *adapter, bool tx_1ss);
++#endif
++#endif
++
++u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf);
++
++extern void rtw_survey_cmd_callback(_adapter  *padapter, struct cmd_obj *pcmd);
++extern void rtw_disassoc_cmd_callback(_adapter  *padapter, struct cmd_obj *pcmd);
++extern void rtw_joinbss_cmd_callback(_adapter  *padapter, struct cmd_obj *pcmd);
++void rtw_create_ibss_post_hdl(_adapter *padapter, int status);
++extern void rtw_readtssi_cmdrsp_callback(_adapter	*padapter,  struct cmd_obj *pcmd);
++
++extern void rtw_setstaKey_cmdrsp_callback(_adapter  *padapter,  struct cmd_obj *pcmd);
++extern void rtw_getrttbl_cmdrsp_callback(_adapter  *padapter,  struct cmd_obj *pcmd);
++
++enum rtw_cmd_id {
++	CMD_JOINBSS, /*0*/
++	CMD_DISCONNECT, /*1*/
++	CMD_CREATE_BSS,/*2*/
++	CMD_SET_OPMODE, /*3*/
++	CMD_SITE_SURVEY, /*4*/
++	CMD_SET_AUTH, /*5*/
++	CMD_SET_KEY, /*6*/
++	CMD_SET_STAKEY, /*7*/
++	CMD_ADD_BAREQ, /*8*/
++	CMD_SET_CHANNEL, /*9*/
++	CMD_TX_BEACON, /*10*/
++	CMD_SET_MLME_EVT, /*11*/
++	CMD_SET_DRV_EXTRA, /*12*/
++	CMD_SET_CHANPLAN, /*13*/
++	CMD_LEDBLINK, /*14*/
++	CMD_SET_CHANSWITCH, /*15*/
++	CMD_TDLS, /*16*/
++	CMD_CHK_BMCSLEEPQ,  /*17*/
++	CMD_RUN_INTHREAD, /*18*/
++	CMD_ADD_BARSP, /*19*/
++	CMD_RM_POST_EVENT, /*20*/
++	CMD_SET_MESH_PLINK_STATE, /* 21 */
++	CMD_ID_MAX
++};
++
++#define CMD_FMT "cmd=%d,%d,%d"
++#define CMD_ARG(cmd) \
++	(cmd)->cmdcode, \
++	(cmd)->cmdcode == CMD_SET_DRV_EXTRA ? ((struct drvextra_cmd_parm *)(cmd)->parmbuf)->ec_id : ((cmd)->cmdcode == CMD_SET_MLME_EVT ? ((struct rtw_evt_header *)(cmd)->parmbuf)->id : 0), \
++	(cmd)->cmdcode == CMD_SET_DRV_EXTRA ? ((struct drvextra_cmd_parm *)(cmd)->parmbuf)->type : 0
++
++#endif /* _CMD_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_debug.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_debug.h
+new file mode 100755
+index 000000000..87ce4a5ce
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_debug.h
+@@ -0,0 +1,700 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_DEBUG_H__
++#define __RTW_DEBUG_H__
++
++/* driver log level*/
++enum {
++	_DRV_NONE_ = 0,
++	_DRV_ALWAYS_ = 1,
++	_DRV_ERR_ = 2,
++	_DRV_WARNING_ = 3,
++	_DRV_INFO_ = 4,
++	_DRV_DEBUG_ = 5,
++	_DRV_MAX_ = 6
++};
++
++#define DRIVER_PREFIX "RTW: "
++
++#ifdef PLATFORM_OS_CE
++extern void rtl871x_cedbg(const char *fmt, ...);
++#endif
++
++#ifdef PLATFORM_WINDOWS
++	#define RTW_PRINT do {} while (0)
++	#define RTW_ERR do {} while (0)
++	#define RTW_WARN do {} while (0)
++	#define RTW_INFO do {} while (0)
++	#define RTW_DBG do {} while (0)
++	#define RTW_PRINT_SEL do {} while (0)
++	#define _RTW_PRINT do {} while (0)
++	#define _RTW_ERR do {} while (0)
++	#define _RTW_WARN do {} while (0)
++	#define _RTW_INFO do {} while (0)
++	#define _RTW_DBG do {} while (0)
++	#define _RTW_PRINT_SEL do {} while (0)
++#else
++	#define RTW_PRINT(x, ...) do {} while (0)
++	#define RTW_ERR(x, ...) do {} while (0)
++	#define RTW_WARN(x,...) do {} while (0)
++	#define RTW_INFO(x,...) do {} while (0)
++	#define RTW_DBG(x,...) do {} while (0)
++	#define RTW_PRINT_SEL(x,...) do {} while (0)
++	#define _RTW_PRINT(x, ...) do {} while (0)
++	#define _RTW_ERR(x, ...) do {} while (0)
++	#define _RTW_WARN(x,...) do {} while (0)
++	#define _RTW_INFO(x,...) do {} while (0)
++	#define _RTW_DBG(x,...) do {} while (0)
++	#define _RTW_PRINT_SEL(x,...) do {} while (0)
++#endif
++
++#define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0)
++#define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0)
++#define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0)
++
++#define RTW_DBG_EXPR(EXPR) do {} while (0)
++
++#define RTW_DBGDUMP 0 /* 'stream' for _dbgdump */
++
++
++
++#undef _dbgdump
++#undef _seqdump
++
++#if defined(PLATFORM_WINDOWS) && defined(PLATFORM_OS_XP)
++	#define _dbgdump DbgPrint
++	#define KERN_CONT
++	#define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg)
++#elif defined(PLATFORM_WINDOWS) && defined(PLATFORM_OS_CE)
++	#define _dbgdump rtl871x_cedbg
++	#define KERN_CONT
++	#define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg)
++#elif defined PLATFORM_LINUX
++	#define _dbgdump printk
++	#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
++	#define KERN_CONT
++	#endif
++	#define _seqdump seq_printf
++#elif defined PLATFORM_FREEBSD
++	#define _dbgdump printf
++	#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
++	#define KERN_CONT
++	#endif
++	#define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg)
++#endif
++
++void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring,
++								bool _idx_show, const u8 *_hexdata, int _hexdatalen);
++
++#ifdef CONFIG_RTW_DEBUG
++
++#ifndef _OS_INTFS_C_
++extern uint rtw_drv_log_level;
++#endif
++
++#if defined(_dbgdump)
++
++#ifdef PLATFORM_LINUX
++#ifdef DBG_THREAD_PID
++#define T_PID_FMT	"(%5u) "
++#define T_PID_ARG	current->pid
++#else /* !DBG_THREAD_PID */
++#define T_PID_FMT	"%s"
++#define T_PID_ARG	""
++#endif /* !DBG_THREAD_PID */
++
++#ifdef DBG_CPU_INFO
++#define CPU_INFO_FMT	"[%u] "
++#define CPU_INFO_ARG	get_cpu()
++#else /* !DBG_CPU_INFO */
++#define CPU_INFO_FMT	"%s"
++#define CPU_INFO_ARG	""
++#endif /* !DBG_CPU_INFO */
++
++/* Extra information in prefix */
++#define EX_INFO_FMT	T_PID_FMT CPU_INFO_FMT
++#define EX_INFO_ARG	T_PID_ARG, CPU_INFO_ARG
++#else /* !PLATFORM_LINUX */
++#define EX_INFO_FMT	"%s"
++#define EX_INFO_ARG	""
++#endif /* !PLATFORM_LINUX */
++
++#define DBG_PREFIX	EX_INFO_FMT DRIVER_PREFIX
++#define DBG_PREFIX_ARG	EX_INFO_ARG
++
++/* with driver-defined prefix */
++#undef RTW_PRINT
++#define RTW_PRINT(fmt, arg...)     \
++	do {\
++		if (_DRV_ALWAYS_ <= rtw_drv_log_level) {\
++			_dbgdump(DBG_PREFIX fmt, DBG_PREFIX_ARG, ##arg);\
++		} \
++	} while (0)
++
++#undef RTW_ERR
++#define RTW_ERR(fmt, arg...)     \
++	do {\
++		if (_DRV_ERR_ <= rtw_drv_log_level) {\
++			_dbgdump(DBG_PREFIX "ERROR " fmt, \
++				 DBG_PREFIX_ARG, ##arg);\
++		} \
++	} while (0)
++
++
++#undef RTW_WARN
++#define RTW_WARN(fmt, arg...)     \
++	do {\
++		if (_DRV_WARNING_ <= rtw_drv_log_level) {\
++			_dbgdump(DBG_PREFIX "WARN " fmt, \
++				 DBG_PREFIX_ARG, ##arg);\
++		} \
++	} while (0)
++
++#undef RTW_INFO
++#define RTW_INFO(fmt, arg...)     \
++	do {\
++		if (_DRV_INFO_ <= rtw_drv_log_level) {\
++			_dbgdump(DBG_PREFIX fmt, DBG_PREFIX_ARG, ##arg);\
++		} \
++	} while (0)
++
++
++#undef RTW_DBG
++#define RTW_DBG(fmt, arg...)     \
++	do {\
++		if (_DRV_DEBUG_ <= rtw_drv_log_level) {\
++			_dbgdump(DBG_PREFIX fmt, DBG_PREFIX_ARG, ##arg);\
++		} \
++	} while (0)
++
++#undef RTW_INFO_DUMP
++#define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen)	\
++	RTW_BUF_DUMP_SEL(_DRV_INFO_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen)
++
++#undef RTW_DBG_DUMP
++#define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen)	\
++	RTW_BUF_DUMP_SEL(_DRV_DEBUG_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen)
++
++
++#undef RTW_PRINT_DUMP
++#define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen)	\
++	RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen)
++
++/* without driver-defined prefix */
++#undef _RTW_PRINT
++#define _RTW_PRINT(fmt, arg...)     \
++	do {\
++		if (_DRV_ALWAYS_ <= rtw_drv_log_level) {\
++			_dbgdump(KERN_CONT fmt, ##arg);\
++		} \
++	} while (0)
++
++#undef _RTW_ERR
++#define _RTW_ERR(fmt, arg...)     \
++	do {\
++		if (_DRV_ERR_ <= rtw_drv_log_level) {\
++			_dbgdump(KERN_CONT fmt, ##arg);\
++		} \
++	} while (0)
++
++
++#undef _RTW_WARN
++#define _RTW_WARN(fmt, arg...)     \
++	do {\
++		if (_DRV_WARNING_ <= rtw_drv_log_level) {\
++			_dbgdump(KERN_CONT fmt, ##arg);\
++		} \
++	} while (0)
++
++#undef _RTW_INFO
++#define _RTW_INFO(fmt, arg...)     \
++	do {\
++		if (_DRV_INFO_ <= rtw_drv_log_level) {\
++			_dbgdump(KERN_CONT fmt, ##arg);\
++		} \
++	} while (0)
++
++#undef _RTW_DBG
++#define _RTW_DBG(fmt, arg...)     \
++	do {\
++		if (_DRV_DEBUG_ <= rtw_drv_log_level) {\
++			_dbgdump(KERN_CONT fmt, ##arg);\
++		} \
++	} while (0)
++
++
++/* other debug APIs */
++#undef RTW_DBG_EXPR
++#define RTW_DBG_EXPR(EXPR) do { if (_DRV_DEBUG_ <= rtw_drv_log_level) EXPR; } while (0)
++
++#endif /* defined(_dbgdump) */
++#endif /* CONFIG_RTW_DEBUG */
++
++
++#if defined(_seqdump)
++/* dump message to selected 'stream' with driver-defined prefix */
++#undef RTW_PRINT_SEL
++#define RTW_PRINT_SEL(sel, fmt, arg...) \
++	do {\
++		if (sel == RTW_DBGDUMP)\
++			RTW_PRINT(fmt, ##arg); \
++		else {\
++			_seqdump(sel, fmt, ##arg) /*rtw_warn_on(1)*/; \
++		} \
++	} while (0)
++
++/* dump message to selected 'stream' */
++#undef _RTW_PRINT_SEL
++#define _RTW_PRINT_SEL(sel, fmt, arg...) \
++	do {\
++		if (sel == RTW_DBGDUMP)\
++			_RTW_PRINT(fmt, ##arg); \
++		else {\
++			_seqdump(sel, fmt, ##arg) /*rtw_warn_on(1)*/; \
++		} \
++	} while (0)
++
++/* dump message to selected 'stream' */
++#undef RTW_DUMP_SEL
++#define RTW_DUMP_SEL(sel, _HexData, _HexDataLen) \
++	RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, sel, NULL, _FALSE, _HexData, _HexDataLen)
++
++#define RTW_MAP_DUMP_SEL(sel, _TitleString, _HexData, _HexDataLen) \
++	RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, sel, _TitleString, _TRUE, _HexData, _HexDataLen)
++#endif /* defined(_seqdump) */
++
++
++#ifdef CONFIG_DBG_COUNTER
++	#define DBG_COUNTER(counter) counter++
++#else
++	#define DBG_COUNTER(counter)
++#endif
++
++void dump_drv_version(void *sel);
++void dump_log_level(void *sel);
++void dump_drv_cfg(void *sel);
++
++#ifdef CONFIG_SDIO_HCI
++void sd_f0_reg_dump(void *sel, _adapter *adapter);
++void sdio_local_reg_dump(void *sel, _adapter *adapter);
++#endif /* CONFIG_SDIO_HCI */
++
++void mac_reg_dump(void *sel, _adapter *adapter);
++void bb_reg_dump(void *sel, _adapter *adapter);
++void bb_reg_dump_ex(void *sel, _adapter *adapter);
++void rf_reg_dump(void *sel, _adapter *adapter);
++
++void rtw_sink_rtp_seq_dbg(_adapter *adapter, u8 *ehdr_pos);
++
++struct sta_info;
++void sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta);
++
++struct dvobj_priv;
++void dump_tx_rate_bmp(void *sel, struct dvobj_priv *dvobj);
++void dump_adapters_status(void *sel, struct dvobj_priv *dvobj);
++
++struct sec_cam_ent;
++void dump_sec_cam_ent(void *sel, struct sec_cam_ent *ent, int id);
++void dump_sec_cam_ent_title(void *sel, u8 has_id);
++void dump_sec_cam(void *sel, _adapter *adapter);
++void dump_sec_cam_cache(void *sel, _adapter *adapter);
++
++bool rtw_fwdl_test_trigger_chksum_fail(void);
++bool rtw_fwdl_test_trigger_wintint_rdy_fail(void);
++bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void);
++u32 rtw_get_wait_hiq_empty_ms(void);
++void rtw_sta_linking_test_set_start(void);
++bool rtw_sta_linking_test_wait_done(void);
++bool rtw_sta_linking_test_force_fail(void);
++#ifdef CONFIG_AP_MODE
++u16 rtw_ap_linking_test_force_auth_fail(void);
++u16 rtw_ap_linking_test_force_asoc_fail(void);
++#endif
++
++#ifdef CONFIG_PROC_DEBUG
++ssize_t proc_set_write_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_read_reg(struct seq_file *m, void *v);
++ssize_t proc_set_read_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++int proc_get_fwstate(struct seq_file *m, void *v);
++int proc_get_sec_info(struct seq_file *m, void *v);
++int proc_get_mlmext_state(struct seq_file *m, void *v);
++#ifdef CONFIG_LAYER2_ROAMING
++int proc_get_roam_flags(struct seq_file *m, void *v);
++ssize_t proc_set_roam_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_roam_param(struct seq_file *m, void *v);
++ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++ssize_t proc_set_roam_tgt_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif /* CONFIG_LAYER2_ROAMING */
++int proc_get_qos_option(struct seq_file *m, void *v);
++int proc_get_ht_option(struct seq_file *m, void *v);
++int proc_get_rf_info(struct seq_file *m, void *v);
++int proc_get_scan_param(struct seq_file *m, void *v);
++ssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_scan_abort(struct seq_file *m, void *v);
++#ifdef CONFIG_RTW_REPEATER_SON
++int proc_get_rson_data(struct seq_file *m, void *v);
++ssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif
++int proc_get_survey_info(struct seq_file *m, void *v);
++ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_ap_info(struct seq_file *m, void *v);
++#ifdef ROKU_PRIVATE
++int proc_get_infra_ap(struct seq_file *m, void *v);
++#endif /* ROKU_PRIVATE */
++ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_trx_info(struct seq_file *m, void *v);
++ssize_t proc_set_tx_power_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_tx_power_offset(struct seq_file *m, void *v);
++int proc_get_rate_ctl(struct seq_file *m, void *v);
++int proc_get_wifi_spec(struct seq_file *m, void *v);
++ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_bw_ctl(struct seq_file *m, void *v);
++ssize_t proc_set_bw_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#ifdef DBG_RX_COUNTER_DUMP
++int proc_get_rx_cnt_dump(struct seq_file *m, void *v);
++ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif
++
++#ifdef CONFIG_AP_MODE
++int proc_get_bmc_tx_rate(struct seq_file *m, void *v);
++ssize_t proc_set_bmc_tx_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif /*CONFIG_AP_MODE*/
++
++int proc_get_ps_dbg_info(struct seq_file *m, void *v);
++ssize_t proc_set_ps_dbg_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++ssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#ifdef CONFIG_AP_MODE
++ssize_t proc_set_ap_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif
++
++int proc_get_rx_stat(struct seq_file *m, void *v);
++int proc_get_tx_stat(struct seq_file *m, void *v);
++#ifdef CONFIG_AP_MODE
++int proc_get_all_sta_info(struct seq_file *m, void *v);
++#endif /* CONFIG_AP_MODE */
++
++#ifdef DBG_MEMORY_LEAK
++int proc_get_malloc_cnt(struct seq_file *m, void *v);
++#endif /* DBG_MEMORY_LEAK */
++
++#ifdef CONFIG_FIND_BEST_CHANNEL
++int proc_get_best_channel(struct seq_file *m, void *v);
++ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif /* CONFIG_FIND_BEST_CHANNEL */
++
++int proc_get_trx_info_debug(struct seq_file *m, void *v);
++
++#ifdef CONFIG_HUAWEI_PROC
++int proc_get_huawei_trx_info(struct seq_file *m, void *v);
++#endif
++
++int proc_get_rx_signal(struct seq_file *m, void *v);
++ssize_t proc_set_rx_signal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_hw_status(struct seq_file *m, void *v);
++ssize_t proc_set_hw_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_mac_rptbuf(struct seq_file *m, void *v);
++
++#ifdef CONFIG_80211N_HT
++int proc_get_ht_enable(struct seq_file *m, void *v);
++ssize_t proc_set_ht_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++int proc_get_bw_mode(struct seq_file *m, void *v);
++ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++int proc_get_ampdu_enable(struct seq_file *m, void *v);
++ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++void dump_regsty_rx_ampdu_size_limit(void *sel, _adapter *adapter);
++int proc_get_rx_ampdu(struct seq_file *m, void *v);
++ssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++void rtw_dump_dft_phy_cap(void *sel, _adapter *adapter);
++void rtw_get_dft_phy_cap(void *sel, _adapter *adapter);
++void rtw_dump_drv_phy_cap(void *sel, _adapter *adapter);
++
++int proc_get_rx_stbc(struct seq_file *m, void *v);
++ssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_stbc_cap(struct seq_file *m, void *v);
++ssize_t proc_set_stbc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_ldpc_cap(struct seq_file *m, void *v);
++ssize_t proc_set_ldpc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#ifdef CONFIG_BEAMFORMING
++int proc_get_txbf_cap(struct seq_file *m, void *v);
++ssize_t proc_set_txbf_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif
++#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
++int proc_get_tx_aval_th(struct seq_file *m, void *v);
++ssize_t proc_set_tx_aval_th(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif /*CONFIG_SDIO_TX_ENABLE_AVAL_INT*/
++int proc_get_rx_ampdu_factor(struct seq_file *m, void *v);
++ssize_t proc_set_rx_ampdu_factor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++int proc_get_tx_max_agg_num(struct seq_file *m, void *v);
++ssize_t proc_set_tx_max_agg_num(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++int proc_get_rx_ampdu_density(struct seq_file *m, void *v);
++ssize_t proc_set_rx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++int proc_get_tx_ampdu_density(struct seq_file *m, void *v);
++ssize_t proc_set_tx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++int proc_get_tx_quick_addba_req(struct seq_file *m, void *v);
++ssize_t proc_set_tx_quick_addba_req(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#ifdef CONFIG_TX_AMSDU
++int proc_get_tx_amsdu(struct seq_file *m, void *v);
++ssize_t proc_set_tx_amsdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_tx_amsdu_rate(struct seq_file *m, void *v);
++ssize_t proc_set_tx_amsdu_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif
++#endif /* CONFIG_80211N_HT */
++
++ssize_t proc_set_dyn_rrsr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_dyn_rrsr(struct seq_file *m, void *v);
++
++int proc_get_en_fwps(struct seq_file *m, void *v);
++ssize_t proc_set_en_fwps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++#if 0
++int proc_get_two_path_rssi(struct seq_file *m, void *v);
++int proc_get_rssi_disp(struct seq_file *m, void *v);
++ssize_t proc_set_rssi_disp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif
++
++#ifdef CONFIG_BT_COEXIST
++int proc_get_btcoex_dbg(struct seq_file *m, void *v);
++ssize_t proc_set_btcoex_dbg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_btcoex_info(struct seq_file *m, void *v);
++#ifdef CONFIG_RF4CE_COEXIST
++int proc_get_rf4ce_state(struct seq_file *m, void *v);
++ssize_t proc_set_rf4ce_state(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif
++#endif /* CONFIG_BT_COEXIST */
++
++#if defined(DBG_CONFIG_ERROR_DETECT)
++int proc_get_sreset(struct seq_file *m, void *v);
++ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif /* DBG_CONFIG_ERROR_DETECT */
++
++int proc_get_odm_adaptivity(struct seq_file *m, void *v);
++ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++#ifdef CONFIG_DBG_COUNTER
++int proc_get_rx_logs(struct seq_file *m, void *v);
++int proc_get_tx_logs(struct seq_file *m, void *v);
++int proc_get_int_logs(struct seq_file *m, void *v);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++int proc_get_rx_ring(struct seq_file *m, void *v);
++int proc_get_tx_ring(struct seq_file *m, void *v);
++int proc_get_pci_aspm(struct seq_file *m, void *v);
++int proc_get_pci_conf_space(struct seq_file *m, void *v);
++ssize_t proc_set_pci_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++int proc_get_pci_bridge_conf_space(struct seq_file *m, void *v);
++ssize_t proc_set_pci_bridge_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++
++#ifdef DBG_TXBD_DESC_DUMP
++int proc_get_tx_ring_ext(struct seq_file *m, void *v);
++ssize_t proc_set_tx_ring_ext(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif
++#endif
++
++#ifdef CONFIG_WOWLAN
++int proc_get_wow_enable(struct seq_file *m, void *v);
++ssize_t proc_set_wow_enable(struct file *file, const char __user *buffer,
++		size_t count, loff_t *pos, void *data);
++int proc_get_pattern_info(struct seq_file *m, void *v);
++ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer,
++		size_t count, loff_t *pos, void *data);
++int proc_get_wakeup_event(struct seq_file *m, void *v);
++ssize_t proc_set_wakeup_event(struct file *file, const char __user *buffer,
++		size_t count, loff_t *pos, void *data);
++int proc_get_wakeup_reason(struct seq_file *m, void *v);
++#endif
++
++#ifdef CONFIG_GPIO_WAKEUP
++int proc_get_wowlan_gpio_info(struct seq_file *m, void *v);
++ssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer,
++		size_t count, loff_t *pos, void *data);
++#endif /*CONFIG_GPIO_WAKEUP*/
++
++#ifdef CONFIG_P2P_WOWLAN
++int proc_get_p2p_wowlan_info(struct seq_file *m, void *v);
++#endif /* CONFIG_P2P_WOWLAN */
++
++int proc_get_new_bcn_max(struct seq_file *m, void *v);
++ssize_t proc_set_new_bcn_max(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++#ifdef CONFIG_POWER_SAVING
++int proc_get_ps_info(struct seq_file *m, void *v);
++ssize_t proc_set_ps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#ifdef CONFIG_WMMPS_STA	
++int proc_get_wmmps_info(struct seq_file *m, void *v);
++ssize_t proc_set_wmmps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif /* CONFIG_WMMPS_STA */
++#endif /* CONFIG_POWER_SAVING */
++
++#ifdef CONFIG_TDLS
++int proc_get_tdls_enable(struct seq_file *m, void *v);
++ssize_t proc_set_tdls_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_tdls_info(struct seq_file *m, void *v);
++#endif
++
++int proc_get_monitor(struct seq_file *m, void *v);
++ssize_t proc_set_monitor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++#ifdef RTW_SIMPLE_CONFIG
++int proc_get_simple_config(struct seq_file *m, void *v);
++ssize_t proc_set_simple_config(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif
++
++#ifdef DBG_XMIT_BLOCK
++int proc_get_xmit_block(struct seq_file *m, void *v);
++ssize_t proc_set_xmit_block(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif
++
++#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
++int proc_get_rtkm_info(struct seq_file *m, void *v);
++#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
++
++#ifdef CONFIG_IEEE80211W
++ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_tx_sa_query(struct seq_file *m, void *v);
++ssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_tx_deauth(struct seq_file *m, void *v);
++ssize_t proc_set_tx_auth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_tx_auth(struct seq_file *m, void *v);
++#endif /* CONFIG_IEEE80211W */
++
++#endif /* CONFIG_PROC_DEBUG */
++
++int proc_get_efuse_map(struct seq_file *m, void *v);
++ssize_t proc_set_efuse_map(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
++int proc_get_pathb_phase(struct seq_file *m, void *v);
++ssize_t proc_set_pathb_phase(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif
++
++#ifdef CONFIG_MCC_MODE
++int proc_get_mcc_info(struct seq_file *m, void *v);
++ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++ssize_t proc_set_mcc_duration(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++ssize_t proc_set_mcc_phydm_offload_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif
++ssize_t proc_set_mcc_single_tx_criteria(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++ssize_t proc_set_mcc_ap_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++ssize_t proc_set_mcc_ap_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++ssize_t proc_set_mcc_ap_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++ssize_t proc_set_mcc_sta_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++ssize_t proc_set_mcc_sta_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++ssize_t proc_set_mcc_sta_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_mcc_policy_table(struct seq_file *m, void *v);
++#endif /* CONFIG_MCC_MODE */
++
++int proc_get_ack_timeout(struct seq_file *m, void *v);
++ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++int proc_get_fw_offload(struct seq_file *m, void *v);
++ssize_t proc_set_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++#ifdef CONFIG_FW_HANDLE_TXBCN
++ssize_t proc_set_fw_tbtt_rpt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_fw_tbtt_rpt(struct seq_file *m, void *v);
++#endif
++
++#ifdef CONFIG_DBG_RF_CAL
++int proc_get_iqk_info(struct seq_file *m, void *v);
++ssize_t proc_set_iqk(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_lck_info(struct seq_file *m, void *v);
++ssize_t proc_set_lck(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++#endif /*CONFIG_DBG_RF_CAL*/
++
++#ifdef CONFIG_CTRL_TXSS_BY_TP
++ssize_t proc_set_txss_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_txss_tp(struct seq_file *m, void *v);
++#ifdef DBG_CTRL_TXSS
++ssize_t proc_set_txss_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_txss_ctrl(struct seq_file *m, void *v);
++#endif
++#endif
++
++#ifdef CONFIG_LPS_CHK_BY_TP
++ssize_t proc_set_lps_chk_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_lps_chk_tp(struct seq_file *m, void *v);
++#endif
++
++#ifdef CONFIG_SUPPORT_STATIC_SMPS
++ssize_t proc_set_smps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++int proc_get_smps(struct seq_file *m, void *v);
++#endif
++
++int proc_get_defs_param(struct seq_file *m, void *v);
++ssize_t proc_set_defs_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++
++#define _drv_always_		1
++#define _drv_emerg_			2
++#define _drv_alert_			3
++#define _drv_crit_			4
++#define _drv_err_			5
++#define _drv_warning_		6
++#define _drv_notice_		7
++#define _drv_info_			8
++#define _drv_dump_			9
++#define _drv_debug_			10
++
++#define _module_rtl871x_xmit_c_		BIT(0)
++#define _module_xmit_osdep_c_		BIT(1)
++#define _module_rtl871x_recv_c_		BIT(2)
++#define _module_recv_osdep_c_		BIT(3)
++#define _module_rtl871x_mlme_c_		BIT(4)
++#define _module_mlme_osdep_c_		BIT(5)
++#define _module_rtl871x_sta_mgt_c_		BIT(6)
++#define _module_rtl871x_cmd_c_			BIT(7)
++#define _module_cmd_osdep_c_		BIT(8)
++#define _module_rtl871x_io_c_				BIT(9)
++#define _module_io_osdep_c_		BIT(10)
++#define _module_os_intfs_c_			BIT(11)
++#define _module_rtl871x_security_c_		BIT(12)
++#define _module_rtl871x_eeprom_c_			BIT(13)
++#define _module_hal_init_c_		BIT(14)
++#define _module_hci_hal_init_c_		BIT(15)
++#define _module_rtl871x_ioctl_c_		BIT(16)
++#define _module_rtl871x_ioctl_set_c_		BIT(17)
++#define _module_rtl871x_ioctl_query_c_	BIT(18)
++#define _module_rtl871x_pwrctrl_c_			BIT(19)
++#define _module_hci_intfs_c_			BIT(20)
++#define _module_hci_ops_c_			BIT(21)
++#define _module_osdep_service_c_			BIT(22)
++#define _module_mp_			BIT(23)
++#define _module_hci_ops_os_c_			BIT(24)
++#define _module_rtl871x_ioctl_os_c		BIT(25)
++#define _module_rtl8712_cmd_c_		BIT(26)
++/* #define _module_efuse_			BIT(27) */
++#define	_module_rtl8192c_xmit_c_ BIT(28)
++#define _module_hal_xmit_c_	BIT(28)
++#define _module_efuse_			BIT(29)
++#define _module_rtl8712_recv_c_		BIT(30)
++#define _module_rtl8712_led_c_		BIT(31)
++
++#endif /* __RTW_DEBUG_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_eeprom.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_eeprom.h
+new file mode 100644
+index 000000000..62304d577
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_eeprom.h
+@@ -0,0 +1,116 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_EEPROM_H__
++#define __RTW_EEPROM_H__
++
++
++#define	RTL8712_EEPROM_ID			0x8712
++/* #define	EEPROM_MAX_SIZE			256 */
++
++#define	HWSET_MAX_SIZE_128		128
++#define	HWSET_MAX_SIZE_256		256
++#define	HWSET_MAX_SIZE_512		512
++#define HWSET_MAX_SIZE_1024		1024
++
++#define	EEPROM_MAX_SIZE			HWSET_MAX_SIZE_1024
++
++#define	CLOCK_RATE					50			/* 100us		 */
++
++/* - EEPROM opcodes */
++#define EEPROM_READ_OPCODE		06
++#define EEPROM_WRITE_OPCODE		05
++#define EEPROM_ERASE_OPCODE		07
++#define EEPROM_EWEN_OPCODE		19      /* Erase/write enable */
++#define EEPROM_EWDS_OPCODE		16      /* Erase/write disable */
++
++/* Country codes */
++#define USA							0x555320
++#define EUROPE						0x1 /* temp, should be provided later	 */
++#define JAPAN						0x2 /* temp, should be provided later */
++
++/*
++ * Customer ID, note that:
++ * This variable is initiailzed through EEPROM or registry,
++ * however, its definition may be different with that in EEPROM for
++ * EEPROM size consideration. So, we have to perform proper translation between them.
++ * Besides, CustomerID of registry has precedence of that of EEPROM.
++ * defined below. 060703, by rcnjko.
++ *   */
++typedef enum _RT_CUSTOMER_ID {
++	RT_CID_DEFAULT = 0,
++	RT_CID_8187_ALPHA0 = 1,
++	RT_CID_8187_SERCOMM_PS = 2,
++	RT_CID_8187_HW_LED = 3,
++	RT_CID_8187_NETGEAR = 4,
++	RT_CID_WHQL = 5,
++	RT_CID_819x_CAMEO  = 6,
++	RT_CID_819x_RUNTOP = 7,
++	RT_CID_819x_Senao = 8,
++	RT_CID_TOSHIBA = 9,	/* Merge by Jacken, 2008/01/31. */
++	RT_CID_819x_Netcore = 10,
++	RT_CID_Nettronix = 11,
++	RT_CID_DLINK = 12,
++	RT_CID_PRONET = 13,
++	RT_CID_COREGA = 14,
++	RT_CID_CHINA_MOBILE = 15,
++	RT_CID_819x_ALPHA = 16,
++	RT_CID_819x_Sitecom = 17,
++	RT_CID_CCX = 18, /* It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17. */
++	RT_CID_819X_LENOVO = 19,
++	RT_CID_819x_QMI = 20,
++	RT_CID_819x_Edimax_Belkin = 21,
++	RT_CID_819x_Sercomm_Belkin = 22,
++	RT_CID_819x_CAMEO1 = 23,
++	RT_CID_819x_MSI = 24,
++	RT_CID_819X_ACER = 25,
++	RT_CID_819x_AzWave_ASUS = 26,
++	RT_CID_819x_AzWave = 27, /* For AzWave in PCIe, The ID is AzWave use and not only Asus */
++	RT_CID_819x_HP = 28,
++	RT_CID_819x_WNC_COREGA = 29,
++	RT_CID_819x_Arcadyan_Belkin = 30,
++	RT_CID_819x_SAMSUNG = 31,
++	RT_CID_819x_CLEVO = 32,
++	RT_CID_819x_DELL = 33,
++	RT_CID_819x_PRONETS = 34,
++	RT_CID_819x_Edimax_ASUS = 35,
++	RT_CID_NETGEAR = 36,
++	RT_CID_PLANEX = 37,
++	RT_CID_CC_C = 38,
++	RT_CID_819x_Xavi = 39,
++	RT_CID_LENOVO_CHINA = 40,
++	RT_CID_INTEL_CHINA = 41,
++	RT_CID_TPLINK_HPWR = 42,
++	RT_CID_819x_Sercomm_Netgear = 43,
++	RT_CID_819x_ALPHA_Dlink = 44,/* add by ylb 20121012 for customer led for alpha */
++	RT_CID_WNC_NEC = 45,/* add by page for NEC */
++	RT_CID_DNI_BUFFALO = 46,/* add by page for NEC */
++} RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
++
++extern void eeprom_write16(_adapter *padapter, u16 reg, u16 data);
++extern u16 eeprom_read16(_adapter *padapter, u16 reg);
++extern void read_eeprom_content(_adapter *padapter);
++extern void eeprom_read_sz(_adapter *padapter, u16 reg, u8 *data, u32 sz);
++
++extern void read_eeprom_content_by_attrib(_adapter	*padapter);
++
++#ifdef PLATFORM_LINUX
++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
++extern int isAdaptorInfoFileValid(void);
++extern int storeAdaptorInfoFile(char *path, u8 *efuse_data);
++extern int retriveAdaptorInfoFile(char *path, u8 *efuse_data);
++#endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */
++#endif /* PLATFORM_LINUX */
++
++#endif /* __RTL871X_EEPROM_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_efuse.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_efuse.h
+new file mode 100644
+index 000000000..cf0840c3b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_efuse.h
+@@ -0,0 +1,277 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_EFUSE_H__
++#define __RTW_EFUSE_H__
++
++
++#define	EFUSE_ERROE_HANDLE		1
++
++#define	PG_STATE_HEADER		0x01
++#define	PG_STATE_WORD_0		0x02
++#define	PG_STATE_WORD_1		0x04
++#define	PG_STATE_WORD_2		0x08
++#define	PG_STATE_WORD_3		0x10
++#define	PG_STATE_DATA			0x20
++
++#define	PG_SWBYTE_H			0x01
++#define	PG_SWBYTE_L			0x02
++
++#define	PGPKT_DATA_SIZE		8
++
++#define	EFUSE_WIFI				0
++#define	EFUSE_BT				1
++
++enum _EFUSE_DEF_TYPE {
++	TYPE_EFUSE_MAX_SECTION				= 0,
++	TYPE_EFUSE_REAL_CONTENT_LEN			= 1,
++	TYPE_AVAILABLE_EFUSE_BYTES_BANK		= 2,
++	TYPE_AVAILABLE_EFUSE_BYTES_TOTAL	= 3,
++	TYPE_EFUSE_MAP_LEN					= 4,
++	TYPE_EFUSE_PROTECT_BYTES_BANK		= 5,
++	TYPE_EFUSE_CONTENT_LEN_BANK			= 6,
++};
++
++#define		EFUSE_MAX_MAP_LEN		1024
++
++#define		EFUSE_MAX_HW_SIZE		1024
++#define		EFUSE_MAX_SECTION_BASE	16
++#define		EFUSE_MAX_SECTION_NUM	128
++#define		EFUSE_MAX_BANK_SIZE		512
++
++/*RTL8822B 8821C BT EFUSE Define 1 BANK 128 size logical map 1024*/
++#ifdef RTW_HALMAC
++#define BANK_NUM		1
++#define EFUSE_BT_REAL_BANK_CONTENT_LEN	128
++#define EFUSE_BT_REAL_CONTENT_LEN		(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)
++#define EFUSE_BT_MAP_LEN				1024	/* 1k bytes */
++#define EFUSE_BT_MAX_SECTION			(EFUSE_BT_MAP_LEN / 8)
++#ifdef CONFIG_RTL8822C
++#define EFUSE_PROTECT_BYTES_BANK		54
++#else
++#define EFUSE_PROTECT_BYTES_BANK		16
++#endif
++#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK)
++#endif
++
++#define EXT_HEADER(header) ((header & 0x1F) == 0x0F)
++#define ALL_WORDS_DISABLED(wde)	((wde & 0x0F) == 0x0F)
++#define GET_HDR_OFFSET_2_0(header) ((header & 0xE0) >> 5)
++
++#define		EFUSE_REPEAT_THRESHOLD_			3
++
++#define IS_MASKED_MP(ic, txt, offset) (EFUSE_IsAddressMasked_MP_##ic##txt(offset))
++#define IS_MASKED_TC(ic, txt, offset) (EFUSE_IsAddressMasked_TC_##ic##txt(offset))
++#define GET_MASK_ARRAY_LEN_MP(ic, txt) (EFUSE_GetArrayLen_MP_##ic##txt())
++#define GET_MASK_ARRAY_LEN_TC(ic, txt) (EFUSE_GetArrayLen_TC_##ic##txt())
++#define GET_MASK_ARRAY_MP(ic, txt, offset) (EFUSE_GetMaskArray_MP_##ic##txt(offset))
++#define GET_MASK_ARRAY_TC(ic, txt, offset) (EFUSE_GetMaskArray_TC_##ic##txt(offset))
++
++
++#define IS_MASKED(ic, txt, offset) (IS_MASKED_MP(ic, txt, offset))
++#define GET_MASK_ARRAY_LEN(ic, txt) (GET_MASK_ARRAY_LEN_MP(ic, txt))
++#define GET_MASK_ARRAY(ic, txt, out) do { GET_MASK_ARRAY_MP(ic, txt, out); } while (0)
++
++#ifdef CONFIG_BT_EFUSE_MASK
++#define IS_BT_MASKED_MP(ic, txt, offset) (EFUSE_IsBTAddressMasked_MP_##ic##txt(offset))
++#define GET_BT_MASK_ARRAY_LEN_MP(ic, txt) (EFUSE_GetBTArrayLen_MP_##ic##txt())
++#define GET_BT_MASK_ARRAY_LEN_TC(ic, txt) (EFUSE_GetBTArrayLen_TC_##ic##txt())
++#define GET_BT_MASK_ARRAY_MP(ic, txt, offset) (EFUSE_GetBTMaskArray_MP_##ic##txt(offset))
++
++#define IS_BT_MASKED(ic, txt, offset) (IS_BT_MASKED_MP(ic,txt, offset))
++#define GET_BT_MASK_ARRAY(ic, txt, out) do { GET_BT_MASK_ARRAY_MP(ic,txt, out); } while(0)
++#define GET_BT_MASK_ARRAY_LEN(ic, txt) (GET_BT_MASK_ARRAY_LEN_MP(ic,txt))
++#endif
++
++/* *********************************************
++ *	The following is for BT Efuse definition
++ * ********************************************* */
++#define		EFUSE_BT_MAX_MAP_LEN		1024
++#define		EFUSE_MAX_BANK			4
++#define		EFUSE_MAX_BT_BANK		(EFUSE_MAX_BANK-1)
++/* *********************************************
++ *--------------------------Define Parameters-------------------------------*/
++#define		EFUSE_MAX_WORD_UNIT			4
++
++/*------------------------------Define structure----------------------------*/
++typedef struct PG_PKT_STRUCT_A {
++	u8 offset;
++	u8 word_en;
++	u8 data[8];
++	u8 word_cnts;
++} PGPKT_STRUCT, *PPGPKT_STRUCT;
++
++typedef enum {
++	ERR_SUCCESS = 0,
++	ERR_DRIVER_FAILURE,
++	ERR_IO_FAILURE,
++	ERR_WI_TIMEOUT,
++	ERR_WI_BUSY,
++	ERR_BAD_FORMAT,
++	ERR_INVALID_DATA,
++	ERR_NOT_ENOUGH_SPACE,
++	ERR_WRITE_PROTECT,
++	ERR_READ_BACK_FAIL,
++	ERR_OUT_OF_RANGE
++} ERROR_CODE;
++
++/*------------------------------Define structure----------------------------*/
++typedef struct _EFUSE_HAL {
++	u8	fakeEfuseBank;
++	u32	fakeEfuseUsedBytes;
++	u8	fakeEfuseContent[EFUSE_MAX_HW_SIZE];
++	u8	fakeEfuseInitMap[EFUSE_MAX_MAP_LEN];
++	u8	fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN];
++	u32	EfuseUsedBytes;
++	u8	EfuseUsedPercentage;
++
++	u16	BTEfuseUsedBytes;
++	u8	BTEfuseUsedPercentage;
++	u8	BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
++	u8	BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN];
++	u8	BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN];
++
++	u16	fakeBTEfuseUsedBytes;
++	u8	fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
++	u8	fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN];
++	u8	fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN];
++
++	/* EFUSE Configuration, initialized in HAL_CmnInitPGData(). */
++	const u16  MaxSecNum_WiFi;
++	const u16  MaxSecNum_BT;
++	const u16  WordUnit;
++	const u16  PhysicalLen_WiFi;
++	const u16  PhysicalLen_BT;
++	const u16  LogicalLen_WiFi;
++	const u16  LogicalLen_BT;
++	const u16  BankSize;
++	const u16  TotalBankNum;
++	const u16  BankNum_WiFi;
++	const u16  BankNum_BT;
++	const u16  OOBProtectBytes;
++	const u16  ProtectBytes;
++	const u16  BankAvailBytes;
++	const u16  TotalAvailBytes_WiFi;
++	const u16  TotalAvailBytes_BT;
++	const u16  HeaderRetry;
++	const u16  DataRetry;
++
++	ERROR_CODE	  Status;
++
++} EFUSE_HAL, *PEFUSE_HAL;
++
++extern u8 maskfileBuffer[64];
++extern u8 btmaskfileBuffer[64];
++
++/*------------------------Export global variable----------------------------*/
++extern u8 fakeEfuseBank;
++extern u32 fakeEfuseUsedBytes;
++extern u8 fakeEfuseContent[];
++extern u8 fakeEfuseInitMap[];
++extern u8 fakeEfuseModifiedMap[];
++
++extern u32 BTEfuseUsedBytes;
++extern u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
++extern u8 BTEfuseInitMap[];
++extern u8 BTEfuseModifiedMap[];
++
++extern u32 fakeBTEfuseUsedBytes;
++extern u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
++extern u8 fakeBTEfuseInitMap[];
++extern u8 fakeBTEfuseModifiedMap[];
++/*------------------------Export global variable----------------------------*/
++#define		MAX_SEGMENT_SIZE			200
++#define		MAX_SEGMENT_NUM			200
++#define		MAX_BUF_SIZE				(MAX_SEGMENT_SIZE*MAX_SEGMENT_NUM)
++#define		TMP_BUF_SIZE				100
++#define		rtprintf					dcmd_Store_Return_Buf
++
++u8	efuse_bt_GetCurrentSize(PADAPTER padapter, u16 *size);
++u16	efuse_bt_GetMaxSize(PADAPTER padapter);
++u16 efuse_GetavailableSize(PADAPTER adapter);
++
++u8	efuse_GetCurrentSize(PADAPTER padapter, u16 *size);
++u16	efuse_GetMaxSize(PADAPTER padapter);
++u8	rtw_efuse_access(PADAPTER padapter, u8 bRead, u16 start_addr, u16 cnts, u8 *data);
++u8	rtw_efuse_bt_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data);
++
++u8	rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
++u8	rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
++u8	rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
++u8	rtw_BT_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
++u8	rtw_BT_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
++#ifdef CONFIG_RTL8822C
++void	rtw_pre_bt_efuse(PADAPTER padapter);
++#endif
++u16	Efuse_GetCurrentSize(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest);
++u8	Efuse_CalculateWordCnts(u8 word_en);
++void	ReadEFuseByte(PADAPTER Adapter, u16 _offset, u8 *pbuf, BOOLEAN bPseudoTest) ;
++void	EFUSE_GetEfuseDefinition(PADAPTER pAdapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest);
++u8	efuse_OneByteRead(PADAPTER pAdapter, u16 addr, u8 *data, BOOLEAN	 bPseudoTest);
++#define efuse_onebyte_read(adapter, addr, data, pseudo_test) efuse_OneByteRead((adapter), (addr), (data), (pseudo_test))
++
++u8	efuse_OneByteWrite(PADAPTER pAdapter, u16 addr, u8 data, BOOLEAN	 bPseudoTest);
++
++void	BTEfuse_PowerSwitch(PADAPTER pAdapter, u8	bWrite, u8	 PwrState);
++void	Efuse_PowerSwitch(PADAPTER pAdapter, u8	bWrite, u8	 PwrState);
++int	Efuse_PgPacketRead(PADAPTER pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
++int	Efuse_PgPacketWrite(PADAPTER pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
++void	efuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata);
++u8	Efuse_WordEnableDataWrite(PADAPTER pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
++void	EFUSE_ShadowMapUpdate(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest);
++void	EFUSE_ShadowRead(PADAPTER pAdapter, u8 Type, u16 Offset, u32 *Value);
++#define efuse_logical_map_read(adapter, type, offset, value) EFUSE_ShadowRead((adapter), (type), (offset), (value))
++
++BOOLEAN rtw_file_efuse_IsMasked(PADAPTER pAdapter, u16 Offset, u8 *maskbuf);
++BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset);
++
++void	hal_ReadEFuse_BT_logic_map(
++	PADAPTER	padapter,
++	u16			_offset,
++	u16			_size_byte,
++	u8			*pbuf
++);
++u8	EfusePgPacketWrite_BT(
++	PADAPTER	pAdapter,
++	u8			offset,
++	u8			word_en,
++	u8			*pData,
++	u8			bPseudoTest);
++
++u16 rtw_get_bt_efuse_mask_arraylen(PADAPTER pAdapter);
++void rtw_bt_efuse_mask_array(PADAPTER pAdapter, u8 *pArray);
++u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter);
++void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray);
++void rtw_efuse_analyze(PADAPTER	padapter, u8 Type, u8 Fake);
++
++#define MAC_HIDDEN_MAX_BW_NUM 8
++extern const u8 _mac_hidden_max_bw_to_hal_bw_cap[];
++#define mac_hidden_max_bw_to_hal_bw_cap(max_bw) (((max_bw) >= MAC_HIDDEN_MAX_BW_NUM) ? 0 : _mac_hidden_max_bw_to_hal_bw_cap[(max_bw)])
++
++#define MAC_HIDDEN_PROTOCOL_NUM 4
++extern const u8 _mac_hidden_proto_to_hal_proto_cap[];
++#define mac_hidden_proto_to_hal_proto_cap(proto) (((proto) >= MAC_HIDDEN_PROTOCOL_NUM) ? 0 : _mac_hidden_proto_to_hal_proto_cap[(proto)])
++
++u8 mac_hidden_wl_func_to_hal_wl_func(u8 func);
++
++#ifdef PLATFORM_LINUX
++u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepath, u8 *buf, u32 len);
++u8 rtw_efuse_file_store(PADAPTER padapter, u8 *filepath, u8 *buf, u32 len);
++#ifdef CONFIG_EFUSE_CONFIG_FILE
++u32 rtw_read_efuse_from_file(const char *path, u8 *buf, int map_size);
++u32 rtw_read_macaddr_from_file(const char *path, u8 *buf);
++#endif /* CONFIG_EFUSE_CONFIG_FILE */
++#endif /* PLATFORM_LINUX */
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_event.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_event.h
+new file mode 100644
+index 000000000..12d7c7092
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_event.h
+@@ -0,0 +1,94 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTW_EVENT_H_
++#define _RTW_EVENT_H_
++
++#ifdef CONFIG_H2CLBK
++	#include <h2clbk.h>
++#endif
++
++/*
++Used to report a bss has been scanned
++
++*/
++struct survey_event	{
++	WLAN_BSSID_EX bss;
++};
++
++/*
++Used to report that the requested site survey has been done.
++
++bss_cnt indicates the number of bss that has been reported.
++
++
++*/
++struct surveydone_event {
++	unsigned int	bss_cnt;
++	bool acs; /* aim to trigger channel selection */
++};
++
++/*
++Used to report the link result of joinning the given bss
++
++
++join_res:
++-1: authentication fail
++-2: association fail
++> 0: TID
++
++*/
++struct joinbss_event {
++	struct	wlan_network	network;
++};
++
++/*
++Used to report a given STA has joinned the created BSS.
++It is used in AP/Ad-HoC(M) mode.
++
++
++*/
++struct stassoc_event {
++	unsigned char macaddr[6];
++};
++
++struct stadel_event {
++	unsigned char macaddr[6];
++	unsigned char rsvd[2]; /* for reason */
++	unsigned char locally_generated;
++	int mac_id;
++};
++
++struct wmm_event {
++	unsigned char wmm;
++};
++
++#ifdef CONFIG_H2CLBK
++struct c2hlbk_event {
++	unsigned char mac[6];
++	unsigned short	s0;
++	unsigned short	s1;
++	unsigned int	w0;
++	unsigned char	b0;
++	unsigned short  s2;
++	unsigned char	b1;
++	unsigned int	w1;
++};
++#endif/* CONFIG_H2CLBK */
++
++struct rtw_event {
++	u32 parmsize;
++	void (*event_callback)(_adapter *dev, u8 *pbuf);
++};
++#endif /* _WLANEVENT_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ft.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ft.h
+new file mode 100755
+index 000000000..025f19e67
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ft.h
+@@ -0,0 +1,183 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __RTW_FT_H_
++#define __RTW_FT_H_
++
++enum rtw_ieee80211_ft_actioncode {
++	RTW_WLAN_ACTION_FT_RESV,
++	RTW_WLAN_ACTION_FT_REQ,
++	RTW_WLAN_ACTION_FT_RSP,
++	RTW_WLAN_ACTION_FT_CONF,
++	RTW_WLAN_ACTION_FT_ACK,
++	RTW_WLAN_ACTION_FT_MAX,
++};
++
++enum _rtw_ft_sta_status {
++	RTW_FT_UNASSOCIATED_STA = 0,
++	RTW_FT_AUTHENTICATING_STA,
++	RTW_FT_AUTHENTICATED_STA,
++	RTW_FT_ASSOCIATING_STA,
++	RTW_FT_ASSOCIATED_STA,
++	RTW_FT_REQUESTING_STA,
++	RTW_FT_REQUESTED_STA,
++	RTW_FT_CONFIRMED_STA,
++	RTW_FT_UNSPECIFIED_STA
++};
++
++#define RTW_FT_ACTION_REQ_LMT	4
++
++#define RTW_FT_MAX_IE_SZ	256
++
++#define rtw_ft_chk_status(a, s) \
++	((a)->mlmepriv.ft_roam.ft_status == (s))
++
++#define rtw_ft_roam_status(a, s)	\
++	((rtw_to_roam(a) > 0) && rtw_ft_chk_status(a, s))
++
++#define rtw_ft_authed_sta(a)	\
++	((rtw_ft_chk_status(a, RTW_FT_AUTHENTICATED_STA)) ||	\
++	(rtw_ft_chk_status(a, RTW_FT_ASSOCIATING_STA)) ||	\
++	(rtw_ft_chk_status(a, RTW_FT_ASSOCIATED_STA)))
++
++#define rtw_ft_set_status(a, s) \
++	do { \
++		((a)->mlmepriv.ft_roam.ft_status = (s)); \
++	} while (0)
++
++#define rtw_ft_lock_set_status(a, s, irq) \
++	do { \
++		_enter_critical_bh(&(a)->mlmepriv.lock, ((_irqL *)(irq)));	\
++		((a)->mlmepriv.ft_roam.ft_status = (s));	\
++		_exit_critical_bh(&(a)->mlmepriv.lock, ((_irqL *)(irq)));	\
++	} while (0)
++
++#define rtw_ft_reset_status(a) \
++	do { \
++		((a)->mlmepriv.ft_roam.ft_status = RTW_FT_UNASSOCIATED_STA); \
++	} while (0)
++
++enum rtw_ft_capability {
++	RTW_FT_EN = BIT0,
++	RTW_FT_OTD_EN = BIT1,
++	RTW_FT_PEER_EN = BIT2,
++	RTW_FT_PEER_OTD_EN = BIT3,
++	RTW_FT_BTM_ROAM = BIT4,
++	RTW_FT_TEST_RSSI_ROAM = BIT7,
++};
++
++#define rtw_ft_chk_flags(a, f) \
++	((a)->mlmepriv.ft_roam.ft_flags & (f))
++
++#define rtw_ft_set_flags(a, f) \
++	do { \
++		((a)->mlmepriv.ft_roam.ft_flags |= (f)); \
++	} while (0)
++
++#define rtw_ft_clr_flags(a, f) \
++	do { \
++		((a)->mlmepriv.ft_roam.ft_flags &= ~(f)); \
++	} while (0)
++
++#define rtw_ft_roam(a)	\
++	((rtw_to_roam(a) > 0) && rtw_ft_chk_flags(a, RTW_FT_PEER_EN))
++	
++#define rtw_ft_valid_akm(a, t)	\
++	((rtw_ft_chk_flags(a, RTW_FT_EN)) && \
++	(((t) == 3) || ((t) == 4)))
++
++#define rtw_ft_roam_expired(a, r)	\
++	((rtw_chk_roam_flags(a, RTW_ROAM_ON_EXPIRED)) \
++	&& (r == WLAN_REASON_ACTIVE_ROAM))
++
++#define rtw_ft_otd_roam_en(a)	\
++	((rtw_ft_chk_flags(a, RTW_FT_OTD_EN))	\
++	&& ((a)->mlmepriv.ft_roam.ft_roam_on_expired == _FALSE)	\
++	&& ((a)->mlmepriv.ft_roam.ft_cap & 0x01))
++	
++#define rtw_ft_otd_roam(a) \
++	rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN)
++
++#define rtw_ft_valid_otd_candidate(a, p)	\
++	((rtw_ft_chk_flags(a, RTW_FT_OTD_EN)) 	\
++	&& ((rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN)	\
++	&& ((*((p)+4) & 0x01) == 0))	\
++	|| ((rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN) == 0)	\
++	&& (*((p)+4) & 0x01))))
++
++struct ft_roam_info {
++	u16	mdid;
++	u8	ft_cap;	
++	/*b0: FT over DS, b1: Resource Req Protocol Cap, b2~b7: Reserved*/
++	u8	updated_ft_ies[RTW_FT_MAX_IE_SZ];
++	u16	updated_ft_ies_len;
++	u8	ft_action[RTW_FT_MAX_IE_SZ];
++	u16	ft_action_len;
++	struct cfg80211_ft_event_params ft_event;
++	u8	ft_roam_on_expired;
++	u8	ft_flags;
++	u32 ft_status;
++	u32 ft_req_retry_cnt;
++	bool ft_updated_bcn;	
++};
++
++void rtw_ft_info_init(struct ft_roam_info *pft);
++
++int rtw_ft_proc_flags_get(struct seq_file *m, void *v);
++
++ssize_t rtw_ft_proc_flags_set(struct file *file, const char __user *buffer,
++	size_t count, loff_t *pos, void *data);
++
++u8 rtw_ft_chk_roaming_candidate(
++	_adapter *padapter, struct wlan_network *competitor);
++
++void rtw_ft_update_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork);
++
++void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf);
++
++void rtw_ft_validate_akm_type(_adapter  *padapter,
++	struct wlan_network *pnetwork);
++
++void rtw_ft_update_bcn(_adapter *padapter, union recv_frame *precv_frame);
++
++void rtw_ft_start_clnt_join(_adapter *padapter);
++
++u8 rtw_ft_update_rsnie(
++	_adapter *padapter, u8 bwrite, 
++	struct pkt_attrib *pattrib, u8 **pframe);
++
++void rtw_ft_build_auth_req_ies(_adapter *padapter, 
++	struct pkt_attrib *pattrib, u8 **pframe);
++
++void rtw_ft_build_assoc_req_ies(_adapter *padapter, 
++	u8 is_reassoc, struct pkt_attrib *pattrib, u8 **pframe);
++
++u8 rtw_ft_update_auth_rsp_ies(_adapter *padapter, u8 *pframe, u32 len);
++
++void rtw_ft_start_roam(_adapter *padapter, u8 *pTargetAddr);
++
++void rtw_ft_issue_action_req(_adapter *padapter, u8 *pTargetAddr);
++
++void rtw_ft_report_evt(_adapter *padapter);
++
++void rtw_ft_report_reassoc_evt(_adapter *padapter, u8 *pMacAddr);
++
++void rtw_ft_link_timer_hdl(void *ctx);
++
++void rtw_ft_roam_timer_hdl(void *ctx);
++
++void rtw_ft_roam_status_reset(_adapter *padapter);
++
++#endif /* __RTW_FT_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ht.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ht.h
+new file mode 100644
+index 000000000..8237bbe76
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ht.h
+@@ -0,0 +1,217 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTW_HT_H_
++#define _RTW_HT_H_
++
++#define HT_CAP_IE_LEN 26
++#define HT_OP_IE_LEN 22
++
++struct ht_priv {
++	u8	ht_option;
++	u8	ampdu_enable;/* for enable Tx A-MPDU */
++	u8	tx_amsdu_enable;/* for enable Tx A-MSDU */
++	u8	bss_coexist;/* for 20/40 Bss coexist */
++
++	/* u8	baddbareq_issued[16]; */
++	u32	tx_amsdu_maxlen; /* 1: 8k, 0:4k ; default:8k, for tx */
++	u32	rx_ampdu_maxlen; /* for rx reordering ctrl win_sz, updated when join_callback. */
++
++	u8	rx_ampdu_min_spacing;
++
++	u8	ch_offset;/* PRIME_CHNL_OFFSET */
++	u8	sgi_20m;
++	u8	sgi_40m;
++
++	/* for processing Tx A-MPDU */
++	u8	agg_enable_bitmap;
++	/* u8	ADDBA_retry_count; */
++	u8	candidate_tid_bitmap;
++
++	u8	ldpc_cap;
++	u8	stbc_cap;
++	u8	beamform_cap;
++	u8	smps_cap; /*spatial multiplexing power save mode. 0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/
++
++	u8 op_present:1; /* ht_op is present */
++
++	struct rtw_ieee80211_ht_cap ht_cap;
++	u8 ht_op[HT_OP_IE_LEN];
++
++};
++
++#ifdef ROKU_PRIVATE
++struct ht_priv_infra_ap {
++
++	/*Infra mode, only store AP's info , not intersection of STA and AP*/
++	u8	channel_width_infra_ap;
++	u8	sgi_20m_infra_ap;
++	u8	sgi_40m_infra_ap;
++	u8	ldpc_cap_infra_ap;
++	u8	stbc_cap_infra_ap;
++	u8	MCS_set_infra_ap[16];
++	u8	Rx_ss_infra_ap;
++	u16	rx_highest_data_rate_infra_ap;
++};
++#endif /* ROKU_PRIVATE */
++
++typedef enum AGGRE_SIZE {
++	HT_AGG_SIZE_8K = 0,
++	HT_AGG_SIZE_16K = 1,
++	HT_AGG_SIZE_32K = 2,
++	HT_AGG_SIZE_64K = 3,
++	VHT_AGG_SIZE_128K = 4,
++	VHT_AGG_SIZE_256K = 5,
++	VHT_AGG_SIZE_512K = 6,
++	VHT_AGG_SIZE_1024K = 7,
++} AGGRE_SIZE_E, *PAGGRE_SIZE_E;
++
++#define	LDPC_HT_ENABLE_RX			BIT0
++#define	LDPC_HT_ENABLE_TX			BIT1
++#define	LDPC_HT_TEST_TX_ENABLE		BIT2
++#define	LDPC_HT_CAP_TX				BIT3
++
++#define	STBC_HT_ENABLE_RX			BIT0
++#define	STBC_HT_ENABLE_TX			BIT1
++#define	STBC_HT_TEST_TX_ENABLE		BIT2
++#define	STBC_HT_CAP_TX				BIT3
++
++/* ------------------------------------------------------------
++ * The HT Control field
++ * ------------------------------------------------------------ */
++#define SET_HT_CTRL_CSI_STEERING(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+2, 6, 2, _val)
++#define SET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+3, 0, 1, _val)
++#define GET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+3, 0, 1)
++
++/* 20/40 BSS Coexist */
++#define SET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 1, _val)
++#define GET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 1)
++
++/* HT Capabilities Info field */
++#define HT_CAP_ELE_CAP_INFO(_pEleStart)					((u8 *)(_pEleStart))
++#define GET_HT_CAP_ELE_LDPC_CAP(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 1)
++#define GET_HT_CAP_ELE_CHL_WIDTH(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 1, 1)
++#define GET_HT_CAP_ELE_SM_PS(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 2, 2)
++#define GET_HT_CAP_ELE_GREENFIELD(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 4, 1)
++#define GET_HT_CAP_ELE_SHORT_GI20M(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 5, 1)
++#define GET_HT_CAP_ELE_SHORT_GI40M(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 6, 1)
++#define GET_HT_CAP_ELE_TX_STBC(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 7, 1)
++#define GET_HT_CAP_ELE_RX_STBC(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 0, 2)
++#define GET_HT_CAP_ELE_DELAYED_BA(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 2, 1)
++#define GET_HT_CAP_ELE_MAX_AMSDU_LENGTH(_pEleStart)		LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 3, 1)
++#define GET_HT_CAP_ELE_DSSS_CCK_40M(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 4, 1)
++#define GET_HT_CAP_ELE_FORTY_INTOLERANT(_pEleStart)		LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 6, 1)
++#define GET_HT_CAP_ELE_LSIG_TXOP_PROTECT(_pEleStart)	LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 7, 1)
++
++#define SET_HT_CAP_ELE_LDPC_CAP(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 1, _val)
++#define SET_HT_CAP_ELE_CHL_WIDTH(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 1, 1, _val)
++#define SET_HT_CAP_ELE_SM_PS(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 2, 2, _val)
++#define SET_HT_CAP_ELE_GREENFIELD(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 4, 1, _val)
++#define SET_HT_CAP_ELE_SHORT_GI20M(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 5, 1, _val)
++#define SET_HT_CAP_ELE_SHORT_GI40M(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 6, 1, _val)
++#define SET_HT_CAP_ELE_TX_STBC(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 7, 1, _val)
++#define SET_HT_CAP_ELE_RX_STBC(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2, _val)
++#define SET_HT_CAP_ELE_DELAYED_BA(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1, _val)
++#define SET_HT_CAP_ELE_MAX_AMSDU_LENGTH(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1, _val)
++#define SET_HT_CAP_ELE_DSSS_CCK_40M(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 4, 1, _val)
++#define SET_HT_CAP_ELE_FORTY_INTOLERANT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 6, 1, _val)
++#define SET_HT_CAP_ELE_LSIG_TXOP_PROTECT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 7, 1, _val)
++
++/* A-MPDU Parameters field */
++#define HT_CAP_ELE_AMPDU_PARA(_pEleStart)				(((u8 *)(_pEleStart))+2)
++#define GET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(_pEleStart)	LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+2, 0, 2)
++#define GET_HT_CAP_ELE_MIN_MPDU_S_SPACE(_pEleStart)		LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+2, 2, 3)
++
++#define HT_AMPDU_PARA_FMT "%02x " \
++	"MAX AMPDU len:%u bytes, MIN MPDU Start Spacing:%u"
++
++#define HT_AMPDU_PARA_ARG(x) \
++	*((u8 *)(x)) \
++	, (1 << (13+GET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(((u8 *)x)-2)))-1 \
++	, GET_HT_CAP_ELE_MIN_MPDU_S_SPACE(((u8 *)x)-2)
++
++#define SET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2, _val)
++#define SET_HT_CAP_ELE_MIN_MPDU_S_SPACE(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 3, _val)
++
++/* Supported MCS Set field */
++#define HT_CAP_ELE_SUP_MCS_SET(_pEleStart)				(((u8 *)(_pEleStart))+3)
++#define HT_CAP_ELE_RX_MCS_MAP(_pEleStart)				HT_CAP_ELE_SUP_MCS_SET(_pEleStart)
++#define GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(_pEleStart)	LE_BITS_TO_2BYTE(((u8 *)(_pEleStart))+13, 0, 10)
++#define GET_HT_CAP_ELE_TX_MCS_DEF(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 0, 1)
++#define GET_HT_CAP_ELE_TRX_MCS_NEQ(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 1, 1)
++#define GET_HT_CAP_ELE_TX_MAX_SS(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 2, 2)
++#define GET_HT_CAP_ELE_TX_UEQM(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 4, 1)
++
++#define HT_RX_MCS_BMP_FMT "%02x %02x %02x %02x %02x%02x%02x%02x%02x%02x"
++#define HT_RX_MCS_BMP_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \
++	((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9]
++
++#define HT_SUP_MCS_SET_FMT HT_RX_MCS_BMP_FMT \
++	/* "\n%02x%02x%02x%02x%02x%02x" */\
++	" %uMbps %s%s%s"
++#define HT_SUP_MCS_SET_ARG(x) HT_RX_MCS_BMP_ARG(x) \
++	/*,((u8 *)(x))[10], ((u8 *)(x))[11], ((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15] */\
++	, GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(((u8 *)x)-3) \
++	, GET_HT_CAP_ELE_TX_MCS_DEF(((u8 *)x)-3) ? "TX_MCS_DEF " : "" \
++	, GET_HT_CAP_ELE_TRX_MCS_NEQ(((u8 *)x)-3) ? "TRX_MCS_NEQ " : "" \
++	, GET_HT_CAP_ELE_TX_UEQM(((u8 *)x)-3) ? "TX_UEQM " : ""
++
++/* TXBF Capabilities */
++#define SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(_pEleStart, _val)				SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 3, 1, ((u8)_val))
++#define SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(_pEleStart, _val)				SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 4, 1, ((u8)_val))
++#define SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart, _val)	SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 10, 1, ((u8)_val))
++#define SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart, _val)	SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 15, 2, ((u8)_val))
++#define SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart, _val)	SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 23, 2, ((u8)_val))
++#define SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(_pEleStart, _val)	SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 27, 2, ((u8)_val))
++
++
++#define GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart)			LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 10, 1)
++#define GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart)			LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 15, 2)
++#define GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart)		LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 23, 2)
++#define GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(_pEleStart)		LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 27, 2)
++
++/* HT Operation element */
++
++#define GET_HT_OP_ELE_PRI_CHL(_pEleStart)					LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 8)
++#define SET_HT_OP_ELE_PRI_CHL(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 8, _val)
++
++/* HT Operation Info field */
++#define HT_OP_ELE_OP_INFO(_pEleStart)						(((u8 *)(_pEleStart)) + 1)
++#define GET_HT_OP_ELE_2ND_CHL_OFFSET(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2)
++#define GET_HT_OP_ELE_STA_CHL_WIDTH(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1)
++#define GET_HT_OP_ELE_RIFS_MODE(_pEleStart)					LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1)
++#define GET_HT_OP_ELE_HT_PROTECT(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2)
++#define GET_HT_OP_ELE_NON_GREEN_PRESENT(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 1)
++#define GET_HT_OP_ELE_OBSS_NON_HT_PRESENT(_pEleStart)		LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 4, 1)
++#define GET_HT_OP_ELE_DUAL_BEACON(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 4, 6, 1)
++#define GET_HT_OP_ELE_DUAL_CTS(_pEleStart)					LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 4, 7, 1)
++#define GET_HT_OP_ELE_STBC_BEACON(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 0, 1)
++#define GET_HT_OP_ELE_LSIG_TXOP_PROTECT(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 1, 1)
++#define GET_HT_OP_ELE_PCO_ACTIVE(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 2, 1)
++#define GET_HT_OP_ELE_PCO_PHASE(_pEleStart)					LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 3, 1)
++
++#define SET_HT_OP_ELE_2ND_CHL_OFFSET(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2, _val)
++#define SET_HT_OP_ELE_STA_CHL_WIDTH(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1, _val)
++#define SET_HT_OP_ELE_RIFS_MODE(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1, _val)
++#define SET_HT_OP_ELE_HT_PROTECT(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2, _val)
++#define SET_HT_OP_ELE_NON_GREEN_PRESENT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 1, _val)
++#define SET_HT_OP_ELE_OBSS_NON_HT_PRESENT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 4, 1, _val)
++#define SET_HT_OP_ELE_DUAL_BEACON(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 4, 6, 1, _val)
++#define SET_HT_OP_ELE_DUAL_CTS(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 4, 7, 1, _val)
++#define SET_HT_OP_ELE_STBC_BEACON(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 0, 1, _val)
++#define SET_HT_OP_ELE_LSIG_TXOP_PROTECT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 1, 1, _val)
++#define SET_HT_OP_ELE_PCO_ACTIVE(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 2, 1, _val)
++#define SET_HT_OP_ELE_PCO_PHASE(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 3, 1, _val)
++
++#endif /* _RTL871X_HT_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_io.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_io.h
+new file mode 100644
+index 000000000..50291e1b8
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_io.h
+@@ -0,0 +1,526 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef _RTW_IO_H_
++#define _RTW_IO_H_
++
++#define NUM_IOREQ		8
++
++#ifdef PLATFORM_LINUX
++	#define MAX_PROT_SZ	(64-16)
++#endif
++
++#define _IOREADY			0
++#define _IO_WAIT_COMPLETE   1
++#define _IO_WAIT_RSP        2
++
++/* IO COMMAND TYPE */
++#define _IOSZ_MASK_		(0x7F)
++#define _IO_WRITE_		BIT(7)
++#define _IO_FIXED_		BIT(8)
++#define _IO_BURST_		BIT(9)
++#define _IO_BYTE_		BIT(10)
++#define _IO_HW_			BIT(11)
++#define _IO_WORD_		BIT(12)
++#define _IO_SYNC_		BIT(13)
++#define _IO_CMDMASK_	(0x1F80)
++
++
++/*
++	For prompt mode accessing, caller shall free io_req
++	Otherwise, io_handler will free io_req
++*/
++
++
++
++/* IO STATUS TYPE */
++#define _IO_ERR_		BIT(2)
++#define _IO_SUCCESS_	BIT(1)
++#define _IO_DONE_		BIT(0)
++
++
++#define IO_RD32			(_IO_SYNC_ | _IO_WORD_)
++#define IO_RD16			(_IO_SYNC_ | _IO_HW_)
++#define IO_RD8			(_IO_SYNC_ | _IO_BYTE_)
++
++#define IO_RD32_ASYNC	(_IO_WORD_)
++#define IO_RD16_ASYNC	(_IO_HW_)
++#define IO_RD8_ASYNC	(_IO_BYTE_)
++
++#define IO_WR32			(_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_)
++#define IO_WR16			(_IO_WRITE_ | _IO_SYNC_ | _IO_HW_)
++#define IO_WR8			(_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_)
++
++#define IO_WR32_ASYNC	(_IO_WRITE_ | _IO_WORD_)
++#define IO_WR16_ASYNC	(_IO_WRITE_ | _IO_HW_)
++#define IO_WR8_ASYNC	(_IO_WRITE_ | _IO_BYTE_)
++
++/*
++
++	Only Sync. burst accessing is provided.
++
++*/
++
++#define IO_WR_BURST(x)		(_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_))
++#define IO_RD_BURST(x)		(_IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_))
++
++
++
++/* below is for the intf_option bit defition... */
++
++#define _INTF_ASYNC_	BIT(0)	/* support async io */
++
++struct intf_priv;
++struct intf_hdl;
++struct io_queue;
++
++struct _io_ops {
++	u8(*_read8)(struct intf_hdl *pintfhdl, u32 addr);
++	u16(*_read16)(struct intf_hdl *pintfhdl, u32 addr);
++	u32(*_read32)(struct intf_hdl *pintfhdl, u32 addr);
++
++	int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
++	int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
++	int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
++	int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);
++
++	int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
++	int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
++	int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
++
++	void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++	void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++
++	void (*_sync_irp_protocol_rw)(struct io_queue *pio_q);
++
++	u32(*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
++
++	u32(*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++	u32(*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
++
++	u32(*_write_scsi)(struct intf_hdl *pintfhdl, u32 cnt, u8 *pmem);
++
++	void (*_read_port_cancel)(struct intf_hdl *pintfhdl);
++	void (*_write_port_cancel)(struct intf_hdl *pintfhdl);
++
++#ifdef CONFIG_SDIO_HCI
++	u8(*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr);
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++	u8(*_sd_iread8)(struct intf_hdl *pintfhdl, u32 addr);
++	u16(*_sd_iread16)(struct intf_hdl *pintfhdl, u32 addr);
++	u32(*_sd_iread32)(struct intf_hdl *pintfhdl, u32 addr);
++	int (*_sd_iwrite8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
++	int (*_sd_iwrite16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
++	int (*_sd_iwrite32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
++#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
++#endif
++
++};
++
++struct io_req {
++	_list	list;
++	u32	addr;
++	volatile u32	val;
++	u32	command;
++	u32	status;
++	u8	*pbuf;
++	_sema	sema;
++	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt);
++	u8 *cnxt;
++};
++
++struct	intf_hdl {
++	_adapter *padapter;
++	struct dvobj_priv *pintf_dev;/*	pointer to &(padapter->dvobjpriv); */
++	struct _io_ops	io_ops;
++};
++
++struct reg_protocol_rd {
++
++#ifdef CONFIG_LITTLE_ENDIAN
++
++	/* DW1 */
++	u32		NumOfTrans:4;
++	u32		Reserved1:4;
++	u32		Reserved2:24;
++	/* DW2 */
++	u32		ByteCount:7;
++	u32		WriteEnable:1;		/* 0:read, 1:write */
++	u32		FixOrContinuous:1;	/* 0:continuous, 1: Fix */
++	u32		BurstMode:1;
++	u32		Byte1Access:1;
++	u32		Byte2Access:1;
++	u32		Byte4Access:1;
++	u32		Reserved3:3;
++	u32		Reserved4:16;
++	/* DW3 */
++	u32		BusAddress;
++	/* DW4 */
++	/* u32		Value; */
++#else
++
++
++	/* DW1 */
++	u32 Reserved1:4;
++	u32 NumOfTrans:4;
++
++	u32 Reserved2:24;
++
++	/* DW2 */
++	u32 WriteEnable:1;
++	u32 ByteCount:7;
++
++
++	u32 Reserved3:3;
++	u32 Byte4Access:1;
++
++	u32 Byte2Access:1;
++	u32 Byte1Access:1;
++	u32 BurstMode:1;
++	u32 FixOrContinuous:1;
++
++	u32 Reserved4:16;
++
++	/* DW3 */
++	u32		BusAddress;
++
++	/* DW4 */
++	/* u32		Value; */
++
++#endif
++
++};
++
++
++struct reg_protocol_wt {
++
++
++#ifdef CONFIG_LITTLE_ENDIAN
++
++	/* DW1 */
++	u32		NumOfTrans:4;
++	u32		Reserved1:4;
++	u32		Reserved2:24;
++	/* DW2 */
++	u32		ByteCount:7;
++	u32		WriteEnable:1;		/* 0:read, 1:write */
++	u32		FixOrContinuous:1;	/* 0:continuous, 1: Fix */
++	u32		BurstMode:1;
++	u32		Byte1Access:1;
++	u32		Byte2Access:1;
++	u32		Byte4Access:1;
++	u32		Reserved3:3;
++	u32		Reserved4:16;
++	/* DW3 */
++	u32		BusAddress;
++	/* DW4 */
++	u32		Value;
++
++#else
++	/* DW1 */
++	u32 Reserved1:4;
++	u32 NumOfTrans:4;
++
++	u32 Reserved2:24;
++
++	/* DW2 */
++	u32 WriteEnable:1;
++	u32 ByteCount:7;
++
++	u32 Reserved3:3;
++	u32 Byte4Access:1;
++
++	u32 Byte2Access:1;
++	u32 Byte1Access:1;
++	u32 BurstMode:1;
++	u32 FixOrContinuous:1;
++
++	u32 Reserved4:16;
++
++	/* DW3 */
++	u32		BusAddress;
++
++	/* DW4 */
++	u32		Value;
++
++#endif
++
++};
++#ifdef CONFIG_PCI_HCI
++#define MAX_CONTINUAL_IO_ERR 4
++#endif
++
++#ifdef CONFIG_USB_HCI
++#define MAX_CONTINUAL_IO_ERR 4
++#endif
++
++#ifdef CONFIG_SDIO_HCI
++#define SD_IO_TRY_CNT (8)
++#define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT
++#endif
++
++#ifdef CONFIG_GSPI_HCI
++#define SD_IO_TRY_CNT (8)
++#define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT
++#endif
++
++
++int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj);
++void rtw_reset_continual_io_error(struct dvobj_priv *dvobj);
++
++/*
++Below is the data structure used by _io_handler
++
++*/
++
++struct io_queue {
++	_lock	lock;
++	_list	free_ioreqs;
++	_list		pending;		/* The io_req list that will be served in the single protocol read/write.	 */
++	_list		processing;
++	u8	*free_ioreqs_buf; /* 4-byte aligned */
++	u8	*pallocated_free_ioreqs_buf;
++	struct	intf_hdl	intf;
++};
++
++struct io_priv {
++
++	_adapter *padapter;
++
++	struct intf_hdl intf;
++
++};
++
++extern uint ioreq_flush(_adapter *adapter, struct io_queue *ioqueue);
++extern void sync_ioreq_enqueue(struct io_req *preq, struct io_queue *ioqueue);
++extern uint sync_ioreq_flush(_adapter *adapter, struct io_queue *ioqueue);
++
++
++extern uint free_ioreq(struct io_req *preq, struct io_queue *pio_queue);
++extern struct io_req *alloc_ioreq(struct io_queue *pio_q);
++
++extern uint register_intf_hdl(u8 *dev, struct intf_hdl *pintfhdl);
++extern void unregister_intf_hdl(struct intf_hdl *pintfhdl);
++
++extern void _rtw_attrib_read(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++extern void _rtw_attrib_write(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++
++extern u8 _rtw_read8(_adapter *adapter, u32 addr);
++extern u16 _rtw_read16(_adapter *adapter, u32 addr);
++extern u32 _rtw_read32(_adapter *adapter, u32 addr);
++extern void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++extern void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++extern void _rtw_read_port_cancel(_adapter *adapter);
++
++
++extern int _rtw_write8(_adapter *adapter, u32 addr, u8 val);
++extern int _rtw_write16(_adapter *adapter, u32 addr, u16 val);
++extern int _rtw_write32(_adapter *adapter, u32 addr, u32 val);
++extern int _rtw_writeN(_adapter *adapter, u32 addr, u32 length, u8 *pdata);
++
++#ifdef CONFIG_SDIO_HCI
++u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr);
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++u8 _rtw_sd_iread8(_adapter *adapter, u32 addr);
++u16 _rtw_sd_iread16(_adapter *adapter, u32 addr);
++u32 _rtw_sd_iread32(_adapter *adapter, u32 addr);
++int _rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val);
++int _rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val);
++int _rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val);
++#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
++#endif /* CONFIG_SDIO_HCI */
++
++extern int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val);
++extern int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val);
++extern int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val);
++
++extern void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++extern u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms);
++extern void _rtw_write_port_cancel(_adapter *adapter);
++
++#ifdef DBG_IO
++u32 match_read_sniff(_adapter *adapter, u32 addr, u16 len, u32 val);
++u32 match_write_sniff(_adapter *adapter, u32 addr, u16 len, u32 val);
++bool match_rf_read_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask);
++bool match_rf_write_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask);
++
++void dbg_rtw_reg_read_monitor(_adapter *adapter, u32 addr, u32 len, u32 val, const char *caller, const int line);
++void dbg_rtw_reg_write_monitor(_adapter *adapter, u32 addr, u32 len, u32 val, const char *caller, const int line);
++
++extern u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line);
++extern u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line);
++extern u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line);
++
++extern int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line);
++extern int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line);
++extern int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line);
++extern int dbg_rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *data, const char *caller, const int line);
++
++#ifdef CONFIG_SDIO_HCI
++u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line);
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++u8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line);
++u16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line);
++u32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line);
++int dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line);
++int dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line);
++int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line);
++#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
++#endif /* CONFIG_SDIO_HCI */
++
++#define rtw_read8(adapter, addr) dbg_rtw_read8((adapter), (addr), __FUNCTION__, __LINE__)
++#define rtw_read16(adapter, addr) dbg_rtw_read16((adapter), (addr), __FUNCTION__, __LINE__)
++#define rtw_read32(adapter, addr) dbg_rtw_read32((adapter), (addr), __FUNCTION__, __LINE__)
++#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem))
++#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem))
++#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter))
++
++#define  rtw_write8(adapter, addr, val) dbg_rtw_write8((adapter), (addr), (val), __FUNCTION__, __LINE__)
++#define  rtw_write16(adapter, addr, val) dbg_rtw_write16((adapter), (addr), (val), __FUNCTION__, __LINE__)
++#define  rtw_write32(adapter, addr, val) dbg_rtw_write32((adapter), (addr), (val), __FUNCTION__, __LINE__)
++#define  rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN((adapter), (addr), (length), (data), __FUNCTION__, __LINE__)
++
++#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val))
++#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val))
++#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val))
++
++#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), addr, cnt, mem)
++#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port(adapter, addr, cnt, mem)
++#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms))
++#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel(adapter)
++
++#ifdef CONFIG_SDIO_HCI
++#define rtw_sd_f0_read8(adapter, addr) dbg_rtw_sd_f0_read8((adapter), (addr), __func__, __LINE__)
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++#define rtw_sd_iread8(adapter, addr) dbg_rtw_sd_iread8((adapter), (addr), __func__, __LINE__)
++#define rtw_sd_iread16(adapter, addr) dbg_rtw_sd_iread16((adapter), (addr), __func__, __LINE__)
++#define rtw_sd_iread32(adapter, addr) dbg_rtw_sd_iread32((adapter), (addr), __func__, __LINE__)
++#define rtw_sd_iwrite8(adapter, addr, val) dbg_rtw_sd_iwrite8((adapter), (addr), (val), __func__, __LINE__)
++#define rtw_sd_iwrite16(adapter, addr, val) dbg_rtw_sd_iwrite16((adapter), (addr), (val), __func__, __LINE__)
++#define rtw_sd_iwrite32(adapter, addr, val) dbg_rtw_sd_iwrite32((adapter), (addr), (val), __func__, __LINE__)
++#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
++#endif /* CONFIG_SDIO_HCI */
++
++#else /* DBG_IO */
++#define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr))
++#define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr))
++#define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr))
++#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem))
++#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem))
++#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter))
++
++#define  rtw_write8(adapter, addr, val) _rtw_write8((adapter), (addr), (val))
++#define  rtw_write16(adapter, addr, val) _rtw_write16((adapter), (addr), (val))
++#define  rtw_write32(adapter, addr, val) _rtw_write32((adapter), (addr), (val))
++#define  rtw_writeN(adapter, addr, length, data) _rtw_writeN((adapter), (addr), (length), (data))
++
++#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val))
++#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val))
++#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val))
++
++#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), (addr), (cnt), (mem))
++#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port((adapter), (addr), (cnt), (mem))
++#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms))
++#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel((adapter))
++
++#ifdef CONFIG_SDIO_HCI
++#define rtw_sd_f0_read8(adapter, addr) _rtw_sd_f0_read8((adapter), (addr))
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++#define rtw_sd_iread8(adapter, addr) _rtw_sd_iread8((adapter), (addr))
++#define rtw_sd_iread16(adapter, addr) _rtw_sd_iread16((adapter), (addr))
++#define rtw_sd_iread32(adapter, addr) _rtw_sd_iread32((adapter), (addr))
++#define rtw_sd_iwrite8(adapter, addr, val) _rtw_sd_iwrite8((adapter), (addr), (val))
++#define rtw_sd_iwrite16(adapter, addr, val) _rtw_sd_iwrite16((adapter), (addr), (val))
++#define rtw_sd_iwrite32(adapter, addr, val) _rtw_sd_iwrite32((adapter), (addr), (val))
++#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
++#endif /* CONFIG_SDIO_HCI */
++
++#endif /* DBG_IO */
++
++extern void rtw_write_scsi(_adapter *adapter, u32 cnt, u8 *pmem);
++
++/* ioreq */
++extern void ioreq_read8(_adapter *adapter, u32 addr, u8 *pval);
++extern void ioreq_read16(_adapter *adapter, u32 addr, u16 *pval);
++extern void ioreq_read32(_adapter *adapter, u32 addr, u32 *pval);
++extern void ioreq_write8(_adapter *adapter, u32 addr, u8 val);
++extern void ioreq_write16(_adapter *adapter, u32 addr, u16 val);
++extern void ioreq_write32(_adapter *adapter, u32 addr, u32 val);
++
++
++extern uint async_read8(_adapter *adapter, u32 addr, u8 *pbuff,
++	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
++extern uint async_read16(_adapter *adapter, u32 addr,  u8 *pbuff,
++	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
++extern uint async_read32(_adapter *adapter, u32 addr,  u8 *pbuff,
++	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
++
++extern void async_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++extern void async_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++
++extern void async_write8(_adapter *adapter, u32 addr, u8 val,
++	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
++extern void async_write16(_adapter *adapter, u32 addr, u16 val,
++	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
++extern void async_write32(_adapter *adapter, u32 addr, u32 val,
++	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
++
++extern void async_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++extern void async_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
++
++
++int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter, struct _io_ops *pops));
++
++
++extern uint alloc_io_queue(_adapter *adapter);
++extern void free_io_queue(_adapter *adapter);
++extern void async_bus_io(struct io_queue *pio_q);
++extern void bus_sync_io(struct io_queue *pio_q);
++extern u32 _ioreq2rwmem(struct io_queue *pio_q);
++
++/*
++#define RTL_R8(reg)		rtw_read8(padapter, reg)
++#define RTL_R16(reg)            rtw_read16(padapter, reg)
++#define RTL_R32(reg)            rtw_read32(padapter, reg)
++#define RTL_W8(reg, val8)       rtw_write8(padapter, reg, val8)
++#define RTL_W16(reg, val16)     rtw_write16(padapter, reg, val16)
++#define RTL_W32(reg, val32)     rtw_write32(padapter, reg, val32)
++*/
++
++/*
++#define RTL_W8_ASYNC(reg, val8) rtw_write32_async(padapter, reg, val8)
++#define RTL_W16_ASYNC(reg, val16) rtw_write32_async(padapter, reg, val16)
++#define RTL_W32_ASYNC(reg, val32) rtw_write32_async(padapter, reg, val32)
++
++#define RTL_WRITE_BB(reg, val32)	phy_SetUsbBBReg(padapter, reg, val32)
++#define RTL_READ_BB(reg)	phy_QueryUsbBBReg(padapter, reg)
++*/
++
++#define PlatformEFIOWrite1Byte(_a, _b, _c)		\
++	rtw_write8(_a, _b, _c)
++#define PlatformEFIOWrite2Byte(_a, _b, _c)		\
++	rtw_write16(_a, _b, _c)
++#define PlatformEFIOWrite4Byte(_a, _b, _c)		\
++	rtw_write32(_a, _b, _c)
++
++#define PlatformEFIORead1Byte(_a, _b)		\
++	rtw_read8(_a, _b)
++#define PlatformEFIORead2Byte(_a, _b)		\
++	rtw_read16(_a, _b)
++#define PlatformEFIORead4Byte(_a, _b)		\
++	rtw_read32(_a, _b)
++
++#endif /* _RTL8711_IO_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ioctl.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ioctl.h
+new file mode 100644
+index 000000000..1143d9710
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ioctl.h
+@@ -0,0 +1,47 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTW_IOCTL_H_
++#define _RTW_IOCTL_H_
++
++enum oid_type {
++	QUERY_OID,
++	SET_OID
++};
++
++struct oid_par_priv {
++	void		*adapter_context;
++	NDIS_OID	oid;
++	void		*information_buf;
++	u32		information_buf_len;
++	u32		*bytes_rw;
++	u32		*bytes_needed;
++	enum oid_type	type_of_oid;
++	u32		dbg;
++};
++
++#if defined(PLATFORM_LINUX) && defined(CONFIG_WIRELESS_EXT)
++extern struct iw_handler_def  rtw_handlers_def;
++#endif
++
++extern void rtw_request_wps_pbc_event(_adapter *padapter);
++
++#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
++extern int rtw_vendor_ie_get_raw_data(struct net_device *, u32, char *, u32);
++extern int rtw_vendor_ie_get_data(struct net_device*, int , char*);
++extern int rtw_vendor_ie_get(struct net_device *, struct iw_request_info *, union iwreq_data *, char *);
++extern int rtw_vendor_ie_set(struct net_device*, struct iw_request_info*, union iwreq_data*, char*);
++#endif
++
++#endif /*  #ifndef __INC_CEINFO_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ioctl_query.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ioctl_query.h
+new file mode 100644
+index 000000000..7badcddfb
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ioctl_query.h
+@@ -0,0 +1,19 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTW_IOCTL_QUERY_H_
++#define _RTW_IOCTL_QUERY_H_
++
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ioctl_set.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ioctl_set.h
+new file mode 100644
+index 000000000..82b4c182d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_ioctl_set.h
+@@ -0,0 +1,40 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_IOCTL_SET_H_
++#define __RTW_IOCTL_SET_H_
++
++u8 rtw_set_802_11_authentication_mode(_adapter *pdapter, NDIS_802_11_AUTHENTICATION_MODE authmode);
++u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid);
++u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep);
++u8 rtw_set_802_11_disassociate(_adapter *padapter);
++u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm);
++#ifdef CONFIG_RTW_ACS
++u8 rtw_set_acs_sitesurvey(_adapter *adapter);
++#endif
++u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags);
++u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid);
++u8 rtw_set_802_11_connect(_adapter *padapter,
++			  u8 *bssid, NDIS_802_11_SSID *ssid, u16 ch);
++
++u8 rtw_validate_bssid(u8 *bssid);
++u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid);
++
++u16 rtw_get_cur_max_rate(_adapter *adapter);
++int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode);
++int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan);
++int rtw_set_country(_adapter *adapter, const char *country_code);
++int rtw_set_band(_adapter *adapter, u8 band);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_iol.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_iol.h
+new file mode 100644
+index 000000000..fa35a59c7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_iol.h
+@@ -0,0 +1,131 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_IOL_H_
++#define __RTW_IOL_H_
++
++
++struct xmit_frame	*rtw_IOL_accquire_xmit_frame(ADAPTER *adapter);
++int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len);
++int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary);
++int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
++bool rtw_IOL_applied(ADAPTER *adapter);
++int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us);
++int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms);
++int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame);
++
++
++#ifdef CONFIG_IOL_NEW_GENERATION
++#define IOREG_CMD_END_LEN	4
++
++struct ioreg_cfg {
++	u8	length;
++	u8	cmd_id;
++	u16	address;
++	u32	data;
++	u32  mask;
++};
++enum ioreg_cmd {
++	IOREG_CMD_LLT			= 0x01,
++	IOREG_CMD_REFUSE		= 0x02,
++	IOREG_CMD_EFUSE_PATH = 0x03,
++	IOREG_CMD_WB_REG		= 0x04,
++	IOREG_CMD_WW_REG	= 0x05,
++	IOREG_CMD_WD_REG	= 0x06,
++	IOREG_CMD_W_RF		= 0x07,
++	IOREG_CMD_DELAY_US	= 0x10,
++	IOREG_CMD_DELAY_MS	= 0x11,
++	IOREG_CMD_END		= 0xFF,
++};
++void read_efuse_from_txpktbuf(ADAPTER *adapter, int bcnhead, u8 *content, u16 *size);
++
++int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask);
++int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask);
++int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask);
++int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask);
++#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value, mask) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value), (mask))
++#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value, mask) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), (mask))
++#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value, mask) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), (mask))
++#define rtw_IOL_append_WRF_cmd(xmit_frame, rf_path, addr, value, mask) _rtw_IOL_append_WRF_cmd((xmit_frame), (rf_path), (addr), (value), (mask))
++
++u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame);
++void  rtw_IOL_cmd_buf_dump(ADAPTER *Adapter, int buf_len, u8 *pbuf);
++
++#ifdef CONFIG_IOL_IOREG_CFG_DBG
++struct cmd_cmp {
++	u16 addr;
++	u32 value;
++};
++#endif
++
++#else /* CONFIG_IOL_NEW_GENERATION */
++
++typedef struct _io_offload_cmd {
++	u8 rsvd0;
++	u8 cmd;
++	u16 address;
++	u32 value;
++} IO_OFFLOAD_CMD, IOL_CMD;
++
++#define IOL_CMD_LLT			0x00
++/* #define IOL_CMD_R_EFUSE	0x01 */
++#define IOL_CMD_WB_REG		0x02
++#define IOL_CMD_WW_REG	0x03
++#define IOL_CMD_WD_REG		0x04
++/* #define IOL_CMD_W_RF		0x05 */
++#define IOL_CMD_DELAY_US	0x80
++#define IOL_CMD_DELAY_MS	0x81
++/* #define IOL_CMD_DELAY_S	0x82 */
++#define IOL_CMD_END			0x83
++
++/*****************************************************
++CMD					Address			Value
++(B1)					(B2/B3:H/L addr)	(B4:B7 : MSB:LSB)
++******************************************************
++IOL_CMD_LLT			-				B7: PGBNDY
++IOL_CMD_R_EFUSE	-				-
++IOL_CMD_WB_REG		0x0~0xFFFF		B7
++IOL_CMD_WW_REG	0x0~0xFFFF		B6~B7
++IOL_CMD_WD_REG	0x0~0xFFFF		B4~B7
++IOL_CMD_W_RF		RF Reg			B5~B7
++IOL_CMD_DELAY_US	-				B6~B7
++IOL_CMD_DELAY_MS	-				B6~B7
++IOL_CMD_DELAY_S	-				B6~B7
++IOL_CMD_END		-				-
++******************************************************/
++int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value);
++int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value);
++int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value);
++
++
++int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms);
++int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms);
++
++#ifdef DBG_IO
++int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line);
++int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line);
++int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line);
++#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
++#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
++#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
++#else
++#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value))
++#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value))
++#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value))
++#endif /* DBG_IO */
++#endif /* CONFIG_IOL_NEW_GENERATION */
++
++
++
++#endif /* __RTW_IOL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mbo.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mbo.h
+new file mode 100755
+index 000000000..9524cb6c6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mbo.h
+@@ -0,0 +1,114 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __RTW_MBO_H_
++#define __RTW_MBO_H_
++
++#define rtw_mbo_wifi_logo_test(a)	((a->registrypriv.wifi_spec) == 1)
++
++#define rtw_mbo_set_ext_cap_internw(_pEleStart, _val) \
++	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+3, 7, 1, _val)
++
++#define rtw_mbo_wnm_notification_req(c, a) \
++	(((c) == RTW_WLAN_CATEGORY_WNM) &&	\
++	(((a) == RTW_WLAN_ACTION_WNM_NOTIF_REQ)))
++
++/* IEEE Std 802.11-2016 Table 9-46 - Status codes */
++#define RTW_ASSOC_DENIED_NO_MORE_STAS	17
++#define RTW_ASSOC_REFUSED_TEMPORARILY	30
++
++/* MBO-OCE Information Element */
++#define RTW_MBO_EID		WLAN_EID_VENDOR_SPECIFIC
++#define RTW_MBO_OUI		0x506F9A
++#define RTW_MBO_OUI_TYPE	0x16
++
++/* Non-preferred Channel Report */
++#define RTW_MBO_ATTR_NPREF_CH_RPT_ID	0x2
++/* Cellular Data Capabilities */
++#define RTW_MBO_ATTR_CELL_DATA_CAP_ID	0x3
++/* Association Disallowed */
++#define RTW_MBO_ATTR_ASSOC_DISABLED_ID	0x4
++/* Transition Reason Code */
++#define RTW_MBO_ATTR_TRANS_RES_ID		0x6
++/* Transition Rejection Reason Code */
++#define RTW_MBO_ATTR_TRANS_REJ_ID		0x7
++/* Association Retry Delay */
++#define RTW_MBO_ATTR_TASSOC_RETRY_ID	0x8
++
++#define RTW_MBO_MAX_CH_LIST_NUM MAX_CHANNEL_NUM
++
++#define RTW_MBO_MAX_CH_RPT_NUM 32
++
++struct npref_ch {
++	u8 op_class;
++	u8 chs[RTW_MBO_MAX_CH_LIST_NUM];
++	size_t nm_of_ch;
++	u8 preference;
++	u8 reason;
++};
++
++struct npref_ch_rtp {
++	struct npref_ch ch_rpt[RTW_MBO_MAX_CH_RPT_NUM];
++	size_t nm_of_rpt;
++};
++
++void rtw_mbo_build_cell_data_cap_attr(
++	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib);
++
++void rtw_mbo_update_ie_data(
++	_adapter *padapter, u8 *pie, u32 ie_len);
++	
++void rtw_mbo_build_supp_op_class_elem(
++	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib);
++
++void rtw_mbo_build_npref_ch_rpt_attr(
++	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib);
++
++void rtw_mbo_build_trans_reject_reason_attr(
++	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib, u8 *pres);
++
++u8 rtw_mbo_disallowed_network(struct wlan_network *pnetwork);
++
++void rtw_mbo_build_exented_cap(
++	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib);
++
++ssize_t rtw_mbo_proc_non_pref_chans_set(
++	struct file *pfile, const char __user *buffer, 
++	size_t count, loff_t *pos, void *pdata);
++
++int rtw_mbo_proc_non_pref_chans_get(
++	struct seq_file *m, void *v);
++
++ssize_t rtw_mbo_proc_cell_data_set(
++	struct file *pfile, const char __user *buffer,
++	size_t count, loff_t *pos, void *pdata);
++
++int rtw_mbo_proc_cell_data_get(
++	struct seq_file *m, void *v);
++
++void rtw_mbo_wnm_notification_parsing(
++	_adapter *padapter, const u8 *pdata, size_t data_len);
++
++void rtw_mbo_build_wnm_notification(
++	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib);
++
++void rtw_mbo_build_probe_req_ies(
++	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib);
++
++void rtw_mbo_build_assoc_req_ies(
++	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib);
++
++#endif /* __RTW_MBO_H_ */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mcc.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mcc.h
+new file mode 100644
+index 000000000..5d2198b03
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mcc.h
+@@ -0,0 +1,315 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2015 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifdef CONFIG_MCC_MODE
++
++#ifndef _RTW_MCC_H_
++#define _RTW_MCC_H_
++
++#include <drv_types.h> /* PADAPTER */
++
++#define MCC_STATUS_PROCESS_MCC_START_SETTING BIT0
++#define MCC_STATUS_PROCESS_MCC_STOP_SETTING BIT1
++#define MCC_STATUS_NEED_MCC BIT2
++#define MCC_STATUS_DOING_MCC BIT3
++
++
++#define MCC_SWCH_FW_EARLY_TIME 10 /* ms */
++#define MCC_EXPIRE_TIME 50 /* ms */
++#define MCC_TOLERANCE_TIME 2 /* 2*2 = 4s */
++#define MCC_UPDATE_PARAMETER_THRESHOLD 5 /* ms */
++
++#define MCC_ROLE_STA_GC_MGMT_QUEUE_MACID 0
++#define MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID 1
++
++/* Lower for stop, Higher for start */
++#define MCC_SETCMD_STATUS_STOP_DISCONNECT 0x0
++#define MCC_SETCMD_STATUS_STOP_SCAN_START 0x1
++#define MCC_SETCMD_STATUS_START_CONNECT 0x80
++#define MCC_SETCMD_STATUS_START_SCAN_DONE 0x81
++
++/*
++* depenad platform or customer requirement(TP unit:Mbps),
++* must be provided by PM or sales or product document
++* too large value means not to limit tx bytes (current for ap mode)
++* NOTE: following values ref from test results
++*/
++#define MCC_AP_BW20_TARGET_TX_TP (300)
++#define MCC_AP_BW40_TARGET_TX_TP (300)
++#define MCC_AP_BW80_TARGET_TX_TP (300)
++#define MCC_STA_BW20_TARGET_TX_TP (35)
++#define MCC_STA_BW40_TARGET_TX_TP (70)
++#define MCC_STA_BW80_TARGET_TX_TP (140)
++#define MCC_SINGLE_TX_CRITERIA 5 /* Mbps */
++
++#define MAX_MCC_NUM 2
++#ifdef CONFIG_RTL8822C
++#define DBG_MCC_REG_NUM 3
++#else
++#define DBG_MCC_REG_NUM 4
++#endif
++#define DBG_MCC_RF_REG_NUM 1
++
++#define MCC_STOP(adapter) (adapter->mcc_adapterpriv.mcc_tx_stop)
++#define MCC_EN(adapter) (adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc)
++#define adapter_to_mccobjpriv(adapter) (&(adapter_to_dvobj(adapter)->mcc_objpriv))
++#define SET_MCC_EN_FLAG(adapter, flag)\
++	do { \
++		adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc = (flag); \
++	} while (0)
++#define SET_MCC_DURATION(adapter, val)\
++	do { \
++		adapter_to_dvobj(adapter)->mcc_objpriv.duration = (val); \
++	} while (0)
++#define SET_MCC_RUNTIME_DURATION(adapter, flag)\
++	do { \
++		adapter_to_dvobj(adapter)->mcc_objpriv.enable_runtime_duration = (flag); \
++	} while (0)
++
++#define SET_MCC_PHYDM_OFFLOAD(adapter, flag)\
++	do { \
++		adapter_to_dvobj(adapter)->mcc_objpriv.mcc_phydm_offload = (flag); \
++	} while (0)
++
++#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++enum mcc_cfg_phydm_ops {
++	MCC_CFG_PHYDM_OFFLOAD = 0,
++	MCC_CFG_PHYDM_RF_CH,
++	MCC_CFG_PHYDM_ADD_CLIENT,
++	MCC_CFG_PHYDM_REMOVE_CLIENT,
++	MCC_CFG_PHYDM_START,
++	MCC_CFG_PHYDM_STOP,
++	MCC_CFG_PHYDM_DUMP,
++	MCC_CFG_PHYDM_MAX,
++};
++#endif
++
++enum rtw_mcc_cmd_id {
++	MCC_CMD_WK_CID = 0,
++	MCC_SET_DURATION_WK_CID,
++	MCC_GET_DBG_REG_WK_CID,
++	#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++	MCC_SET_PHYDM_OFFLOAD_WK_CID,
++	#endif
++};
++
++/* Represent Channel Tx Null setting */
++enum mcc_channel_tx_null {
++	MCC_ENABLE_TX_NULL = 0,
++	MCC_DISABLE_TX_NULL = 1,
++};
++
++/* Represent C2H Report setting */
++enum mcc_c2h_report {
++	MCC_C2H_REPORT_DISABLE = 0,
++	MCC_C2H_REPORT_FAIL_STATUS = 1,
++	MCC_C2H_REPORT_ALL_STATUS = 2,
++};
++
++/* Represent Channel Scan */
++enum mcc_channel_scan {
++	MCC_CHIDX = 0,
++	MCC_SCANCH_RSVD_LOC = 1,
++};
++
++/* Represent FW status report of channel switch */
++enum mcc_status_rpt {
++	MCC_RPT_SUCCESS = 0,
++	MCC_RPT_TXNULL_FAIL = 1,
++	MCC_RPT_STOPMCC = 2,
++	MCC_RPT_READY = 3,
++	MCC_RPT_SWICH_CHANNEL_NOTIFY = 7,
++	MCC_RPT_UPDATE_NOA_START_TIME = 8,
++	MCC_RPT_TSF = 9,
++	MCC_RPT_MAX,
++};
++
++enum mcc_role {
++	MCC_ROLE_STA = 0,
++	MCC_ROLE_AP = 1,
++	MCC_ROLE_GC = 2,
++	MCC_ROLE_GO = 3,
++	MCC_ROLE_MAX,
++};
++
++struct mcc_iqk_backup {
++	u16 TX_X;
++	u16 TX_Y;
++	u16 RX_X;
++	u16 RX_Y;
++};
++
++enum mcc_duration_setting {
++	MCC_DURATION_MAPPING = 0,
++	MCC_DURATION_DIRECET = 1,
++};
++
++enum mcc_sched_mode {
++	MCC_FAIR_SCHEDULE = 0,
++	MCC_FAVOR_STA = 1,
++	MCC_FAVOR_P2P = 2,
++};
++
++/*  mcc data for adapter */
++struct mcc_adapter_priv {
++	u8 order;		/* FW document, softap/AP must be 0 */
++	enum mcc_role role;			/* MCC role(AP,STA,GO,GC) */
++	u8 mcc_duration; /* channel stay period, UNIT:1TU */
++
++	/* flow control */
++	u8 mcc_tx_stop;				/* check if tp stop or not */
++	u8 mcc_tp_limit;				/* check if tp limit or not */
++	u32 mcc_target_tx_bytes_to_port;		/* customer require  */
++	u32 mcc_tx_bytes_to_port;	/* already tx to tx fifo (write port) */
++
++	/* data from kernel to check if enqueue data or netif stop queue */
++	u32 mcc_tp;
++	u64 mcc_tx_bytes_from_kernel;
++	u64 mcc_last_tx_bytes_from_kernel;
++
++	/* Backup IQK value for MCC */
++	struct mcc_iqk_backup mcc_iqk_arr[MAX_RF_PATH];
++
++	/* mgmt queue macid to avoid RA issue */
++	u8 mgmt_queue_macid;
++
++	/* set macid bitmap to let fw know which macid should be tx pause */
++	/* all interface share total 16 macid */
++	u16 mcc_macid_bitmap;
++
++	/* use for NoA start time (unit: mircoseconds) */
++	u32 noa_start_time;
++
++	u8 p2p_go_noa_ie[MAX_P2P_IE_LEN];
++	u32 p2p_go_noa_ie_len;
++	u64 tsf;
++#ifdef CONFIG_TDLS
++	u8 backup_tdls_en;
++#endif /* CONFIG_TDLS */
++
++	u8 null_early;
++	u8 null_rty_num;
++};
++
++struct mcc_obj_priv {
++	u8 en_mcc; /* enable MCC or not */
++	u8 duration; /* store duration(%) from registry, for primary adapter */
++	u8 interval;
++	u8 start_time;
++	u8 mcc_c2h_status;
++	u8 cur_mcc_success_cnt; /* used for check mcc switch channel success */
++	u8 prev_mcc_success_cnt; /* used for check mcc switch channel success */
++	u8 mcc_tolerance_time; /* used for detect mcc switch channel success */
++	u8 mcc_loc_rsvd_paga[MAX_MCC_NUM];  /* mcc rsvd page */
++	u8 mcc_status; /* mcc status stop or start .... */
++	u8 policy_index;
++	u8 mcc_stop_threshold;
++	u8 current_order;
++	u8 last_tsfdiff;
++	systime mcc_launch_time; /* mcc launch time, used for starting detect mcc switch channel success */
++	_mutex mcc_mutex;
++	_lock mcc_lock;
++	PADAPTER iface[MAX_MCC_NUM]; /* by order, use for mcc parameter cmd */
++	struct submit_ctx mcc_sctx;
++	struct submit_ctx mcc_tsf_req_sctx;
++	_mutex mcc_tsf_req_mutex;
++	u8 mcc_tsf_req_sctx_order; /* record current order for mcc_tsf_req_sctx */
++#ifdef CONFIG_MCC_MODE_V2
++	u8 mcc_iqk_value_rsvd_page[3];
++#endif /* CONFIG_MCC_MODE_V2 */
++	u8 mcc_pwr_idx_rsvd_page[MAX_MCC_NUM];
++	u8 enable_runtime_duration;
++	/* for LG */
++	u8 mchan_sched_mode;
++
++	_mutex mcc_dbg_reg_mutex;
++	u32 dbg_reg[DBG_MCC_REG_NUM];
++	u32 dbg_reg_val[DBG_MCC_REG_NUM];
++	u32 dbg_rf_reg[DBG_MCC_RF_REG_NUM];
++	u32 dbg_rf_reg_val[DBG_MCC_RF_REG_NUM][MAX_RF_PATH];
++	u8 mcc_phydm_offload;
++};
++
++/* backup IQK val */
++void rtw_hal_mcc_restore_iqk_val(PADAPTER padapter);
++
++/* check mcc status */
++u8 rtw_hal_check_mcc_status(PADAPTER padapter, u8 mcc_status);
++
++/* set mcc status */
++void rtw_hal_set_mcc_status(PADAPTER padapter, u8 mcc_status);
++
++/* clear mcc status */
++void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status);
++
++/* dl mcc rsvd page */
++u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index
++	, u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num);
++
++/* handle C2H */
++void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf);
++
++/* switch channel successfully or not */
++void rtw_hal_mcc_sw_status_check(PADAPTER padapter);
++
++/* change some scan flags under site survey */
++u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset);
++
++/* record data kernel TX to driver to check MCC concurrent TX  */
++void rtw_hal_mcc_calc_tx_bytes_from_kernel(PADAPTER padapter, u32 len);
++
++/* record data to port to let driver do flow ctrl  */
++void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len);
++
++/* check stop write port or not  */
++u8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter);
++
++u8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter);
++
++u8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter);
++
++u8 rtw_hal_set_mcc_setting_start_bss_network(PADAPTER padapter, u8 chbw_grouped);
++
++u8 rtw_hal_set_mcc_setting_disconnect(PADAPTER padapter);
++
++u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter);
++
++u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset, u8 chbw_allow);
++
++void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj);
++
++void update_mcc_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib);
++
++u8 rtw_hal_mcc_link_status_chk(_adapter *padapter, const char *msg);
++
++void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode);
++
++u8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len);
++
++void rtw_hal_dump_mcc_policy_table(void *sel);
++
++void rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add);
++
++void rtw_hal_mcc_process_noa(PADAPTER padapter);
++
++void rtw_hal_mcc_parameter_init(PADAPTER padapter);
++
++u8 rtw_mcc_cmd_hdl(PADAPTER adapter, u8 type, const u8 *val);
++
++u8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val);
++#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++u8 rtw_set_mcc_phydm_offload_enable_cmd(PADAPTER adapter, u8 enable, u8 enqueue);
++#endif /* CONFIG_MCC_PHYDM_OFFLOAD */
++#endif /* _RTW_MCC_H_ */
++#endif /* CONFIG_MCC_MODE */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mem.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mem.h
+new file mode 100644
+index 000000000..5b61fb16a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mem.h
+@@ -0,0 +1,41 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_MEM_H__
++#define __RTW_MEM_H__
++
++#include <drv_conf.h>
++#include <basic_types.h>
++#include <osdep_service.h>
++
++#ifdef CONFIG_SDIO_HCI
++#define MAX_RTKM_RECVBUF_SZ		MAX_RECVBUF_SZ
++#define MAX_RTKM_NR_PREALLOC_RECV_SKB	NR_RECVBUFF
++#else /* !CONFIG_SDIO_HCI */
++#ifdef CONFIG_PLATFORM_MSTAR_HIGH
++	#define MAX_RTKM_RECVBUF_SZ (31744) /* 31k */
++#else
++	#define MAX_RTKM_RECVBUF_SZ (15360) /* 15k */
++#endif /* CONFIG_PLATFORM_MSTAR_HIGH */
++#define MAX_RTKM_NR_PREALLOC_RECV_SKB 16
++#endif /* !CONFIG_SDIO_HCI */
++
++u16 rtw_rtkm_get_buff_size(void);
++u8 rtw_rtkm_get_nr_recv_skb(void);
++struct u8 *rtw_alloc_revcbuf_premem(void);
++struct sk_buff *rtw_alloc_skb_premem(u16 in_size);
++int rtw_free_skb_premem(struct sk_buff *pskb);
++
++
++#endif /* __RTW_MEM_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mi.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mi.h
+new file mode 100644
+index 000000000..4edc9f894
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mi.h
+@@ -0,0 +1,310 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_MI_H_
++#define __RTW_MI_H_
++
++void rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw);
++u8 rtw_mi_stayin_union_ch_chk(_adapter *adapter);
++u8 rtw_mi_stayin_union_band_chk(_adapter *adapter);
++
++int rtw_mi_get_ch_setting_union_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, u8 *ch, u8 *bw, u8 *offset);
++int rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset);
++int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset);
++
++struct mi_state {
++	u8 sta_num;			/* WIFI_STATION_STATE */
++	u8 ld_sta_num;		/* WIFI_STATION_STATE && WIFI_ASOC_STATE */
++	u8 lg_sta_num;		/* WIFI_STATION_STATE && WIFI_UNDER_LINKING */
++#ifdef CONFIG_TDLS
++	u8 ld_tdls_num;		/* adapter.tdlsinfo.link_established */
++#endif
++#ifdef CONFIG_AP_MODE
++	u8 ap_num;			/* WIFI_AP_STATE && WIFI_ASOC_STATE */
++	u8 starting_ap_num;	/*WIFI_FW_AP_STATE*/
++	u8 ld_ap_num;		/* WIFI_AP_STATE && WIFI_ASOC_STATE && asoc_sta_count > 2 */
++#endif
++	u8 adhoc_num;		/* (WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) && WIFI_ASOC_STATE */
++	u8 ld_adhoc_num;	/* (WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) && WIFI_ASOC_STATE && asoc_sta_count > 2 */
++#ifdef CONFIG_RTW_MESH
++	u8 mesh_num;		/* WIFI_MESH_STATE &&  WIFI_ASOC_STATE */
++	u8 ld_mesh_num;		/* WIFI_MESH_STATE &&  WIFI_ASOC_STATE && asoc_sta_count > 2 */
++#endif
++	u8 scan_num;		/* WIFI_UNDER_SURVEY */
++	u8 scan_enter_num;	/* WIFI_UNDER_SURVEY && !SCAN_DISABLE && !SCAN_BACK_OP */
++	u8 uwps_num;		/* WIFI_UNDER_WPS */
++#ifdef CONFIG_IOCTL_CFG80211
++	#ifdef CONFIG_P2P
++	u8 roch_num;
++	#endif
++	u8 mgmt_tx_num;
++#endif
++#ifdef CONFIG_P2P
++	u8 p2p_device_num;
++	u8 p2p_gc;
++	u8 p2p_go;
++#endif
++	u8 union_ch;
++	u8 union_bw;
++	u8 union_offset;
++};
++
++#define MSTATE_STA_NUM(_mstate)			((_mstate)->sta_num)
++#define MSTATE_STA_LD_NUM(_mstate)		((_mstate)->ld_sta_num)
++#define MSTATE_STA_LG_NUM(_mstate)		((_mstate)->lg_sta_num)
++
++#ifdef CONFIG_TDLS
++#define MSTATE_TDLS_LD_NUM(_mstate)		((_mstate)->ld_tdls_num)
++#else
++#define MSTATE_TDLS_LD_NUM(_mstate)		0
++#endif
++
++#ifdef CONFIG_AP_MODE
++#define MSTATE_AP_NUM(_mstate)			((_mstate)->ap_num)
++#define MSTATE_AP_STARTING_NUM(_mstate)	((_mstate)->starting_ap_num)
++#define MSTATE_AP_LD_NUM(_mstate)		((_mstate)->ld_ap_num)
++#else
++#define MSTATE_AP_NUM(_mstate)			0
++#define MSTATE_AP_STARTING_NUM(_mstate) 0
++#define MSTATE_AP_LD_NUM(_mstate)		0
++#endif
++
++#define MSTATE_ADHOC_NUM(_mstate)		((_mstate)->adhoc_num)
++#define MSTATE_ADHOC_LD_NUM(_mstate)	((_mstate)->ld_adhoc_num)
++
++#ifdef CONFIG_RTW_MESH
++#define MSTATE_MESH_NUM(_mstate)		((_mstate)->mesh_num)
++#define MSTATE_MESH_LD_NUM(_mstate)		((_mstate)->ld_mesh_num)
++#else
++#define MSTATE_MESH_NUM(_mstate)		0
++#define MSTATE_MESH_LD_NUM(_mstate)		0
++#endif
++
++#define MSTATE_SCAN_NUM(_mstate)		((_mstate)->scan_num)
++#define MSTATE_SCAN_ENTER_NUM(_mstate)	((_mstate)->scan_enter_num)
++#define MSTATE_WPS_NUM(_mstate)			((_mstate)->uwps_num)
++
++#if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P)
++#define MSTATE_ROCH_NUM(_mstate)		((_mstate)->roch_num)
++#else
++#define MSTATE_ROCH_NUM(_mstate)		0
++#endif
++
++#ifdef CONFIG_P2P
++#define MSTATE_P2P_DV_NUM(_mstate)		((_mstate)->p2p_device_num)
++#define MSTATE_P2P_GC_NUM(_mstate)		((_mstate)->p2p_gc)
++#define MSTATE_P2P_GO_NUM(_mstate)		((_mstate)->p2p_go)
++#else
++#define MSTATE_P2P_DV_NUM(_mstate)		0
++#define MSTATE_P2P_GC_NUM(_mstate)		0
++#define MSTATE_P2P_GO_NUM(_mstate)		0
++#endif
++
++#if defined(CONFIG_IOCTL_CFG80211)
++#define MSTATE_MGMT_TX_NUM(_mstate)		((_mstate)->mgmt_tx_num)
++#else
++#define MSTATE_MGMT_TX_NUM(_mstate)		0
++#endif
++
++#define MSTATE_U_CH(_mstate)			((_mstate)->union_ch)
++#define MSTATE_U_BW(_mstate)			((_mstate)->union_bw)
++#define MSTATE_U_OFFSET(_mstate)		((_mstate)->union_offset)
++
++#define rtw_mi_get_union_chan(adapter)	adapter_to_dvobj(adapter)->iface_state.union_ch
++#define rtw_mi_get_union_bw(adapter)		adapter_to_dvobj(adapter)->iface_state.union_bw
++#define rtw_mi_get_union_offset(adapter)	adapter_to_dvobj(adapter)->iface_state.union_offset
++
++#define rtw_mi_get_assoced_sta_num(adapter)	DEV_STA_LD_NUM(adapter_to_dvobj(adapter))
++#define rtw_mi_get_ap_num(adapter)			DEV_AP_NUM(adapter_to_dvobj(adapter))
++#define rtw_mi_get_mesh_num(adapter)		DEV_MESH_NUM(adapter_to_dvobj(adapter))
++u8 rtw_mi_get_assoc_if_num(_adapter *adapter);
++
++/* For now, not return union_ch/bw/offset */
++void rtw_mi_status_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, struct mi_state *mstate);
++void rtw_mi_status(_adapter *adapter, struct mi_state *mstate);
++void rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate);
++void rtw_mi_status_no_others(_adapter *adapter, struct mi_state *mstate);
++
++/* For now, not handle union_ch/bw/offset */
++void rtw_mi_status_merge(struct mi_state *d, struct mi_state *a);
++
++void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state);
++
++u8 rtw_mi_netif_stop_queue(_adapter *padapter);
++u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter);
++
++u8 rtw_mi_netif_wake_queue(_adapter *padapter);
++u8 rtw_mi_buddy_netif_wake_queue(_adapter *padapter);
++
++u8 rtw_mi_netif_carrier_on(_adapter *padapter);
++u8 rtw_mi_buddy_netif_carrier_on(_adapter *padapter);
++u8 rtw_mi_netif_carrier_off(_adapter *padapter);
++u8 rtw_mi_buddy_netif_carrier_off(_adapter *padapter);
++
++u8 rtw_mi_netif_caroff_qstop(_adapter *padapter);
++u8 rtw_mi_buddy_netif_caroff_qstop(_adapter *padapter);
++u8 rtw_mi_netif_caron_qstart(_adapter *padapter);
++u8 rtw_mi_buddy_netif_caron_qstart(_adapter *padapter);
++
++void rtw_mi_scan_abort(_adapter *adapter, bool bwait);
++void rtw_mi_buddy_scan_abort(_adapter *adapter, bool bwait);
++u32 rtw_mi_start_drv_threads(_adapter *adapter);
++u32 rtw_mi_buddy_start_drv_threads(_adapter *adapter);
++void rtw_mi_stop_drv_threads(_adapter *adapter);
++void rtw_mi_buddy_stop_drv_threads(_adapter *adapter);
++void rtw_mi_cancel_all_timer(_adapter *adapter);
++void rtw_mi_buddy_cancel_all_timer(_adapter *adapter);
++void rtw_mi_reset_drv_sw(_adapter *adapter);
++void rtw_mi_buddy_reset_drv_sw(_adapter *adapter);
++
++extern void rtw_intf_start(_adapter *adapter);
++extern void rtw_intf_stop(_adapter *adapter);
++void rtw_mi_intf_start(_adapter *adapter);
++void rtw_mi_buddy_intf_start(_adapter *adapter);
++void rtw_mi_intf_stop(_adapter *adapter);
++void rtw_mi_buddy_intf_stop(_adapter *adapter);
++
++#ifdef CONFIG_NEW_NETDEV_HDL
++u8 rtw_mi_hal_iface_init(_adapter *padapter);
++#endif
++void rtw_mi_suspend_free_assoc_resource(_adapter *adapter);
++void rtw_mi_buddy_suspend_free_assoc_resource(_adapter *adapter);
++
++#ifdef CONFIG_SET_SCAN_DENY_TIMER
++void rtw_mi_set_scan_deny(_adapter *adapter, u32 ms);
++void rtw_mi_buddy_set_scan_deny(_adapter *adapter, u32 ms);
++#else
++#define rtw_mi_set_scan_deny(adapter, ms) do {} while (0)
++#define rtw_mi_buddy_set_scan_deny(adapter, ms) do {} while (0)
++#endif
++
++u8 rtw_mi_is_scan_deny(_adapter *adapter);
++u8 rtw_mi_buddy_is_scan_deny(_adapter *adapter);
++
++void rtw_mi_beacon_update(_adapter *padapter);
++void rtw_mi_buddy_beacon_update(_adapter *padapter);
++
++#ifndef CONFIG_MI_WITH_MBSSID_CAM
++void rtw_mi_hal_dump_macaddr(void *sel, _adapter *padapter);
++void rtw_mi_buddy_hal_dump_macaddr(void *sel, _adapter *padapter);
++#endif
++
++#ifdef CONFIG_PCI_HCI
++void rtw_mi_xmit_tasklet_schedule(_adapter *padapter);
++void rtw_mi_buddy_xmit_tasklet_schedule(_adapter *padapter);
++#endif
++
++u8 rtw_mi_busy_traffic_check(_adapter *padapter);
++u8 rtw_mi_buddy_busy_traffic_check(_adapter *padapter);
++
++u8 rtw_mi_check_mlmeinfo_state(_adapter *padapter, u32 state);
++u8 rtw_mi_buddy_check_mlmeinfo_state(_adapter *padapter, u32 state);
++
++u8 rtw_mi_check_fwstate(_adapter *padapter, sint state);
++u8 rtw_mi_buddy_check_fwstate(_adapter *padapter, sint state);
++enum {
++	MI_LINKED,
++	MI_ASSOC,
++	MI_UNDER_WPS,
++	MI_AP_MODE,
++	MI_AP_ASSOC,
++	MI_ADHOC,
++	MI_ADHOC_ASSOC,
++	MI_MESH,
++	MI_MESH_ASSOC,
++	MI_STA_NOLINK, /* this is misleading, but not used now */
++	MI_STA_LINKED,
++	MI_STA_LINKING,
++};
++u8 rtw_mi_check_status(_adapter *adapter, u8 type);
++
++void dump_dvobj_mi_status(void *sel, const char *fun_name, _adapter *adapter);
++#ifdef DBG_IFACE_STATUS
++#define DBG_IFACE_STATUS_DUMP(adapter)	dump_dvobj_mi_status(RTW_DBGDUMP, __func__, adapter)
++#endif
++void dump_mi_status(void *sel, struct dvobj_priv *dvobj);
++
++u8 rtw_mi_traffic_statistics(_adapter *padapter);
++u8 rtw_mi_check_miracast_enabled(_adapter *padapter);
++
++#ifdef CONFIG_XMIT_THREAD_MODE
++u8 rtw_mi_check_pending_xmitbuf(_adapter *padapter);
++u8 rtw_mi_buddy_check_pending_xmitbuf(_adapter *padapter);
++#endif
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++#ifdef CONFIG_RTL8822B
++	#include <rtl8822b_hal.h>
++#elif defined(CONFIG_RTL8822C)
++	#include <rtl8822c_hal.h>
++#else
++	extern s32 _dequeue_writeport(PADAPTER padapter);
++#endif
++u8 rtw_mi_dequeue_writeport(_adapter *padapter);
++u8 rtw_mi_buddy_dequeue_writeport(_adapter *padapter);
++#endif
++
++void rtw_mi_adapter_reset(_adapter *padapter);
++void rtw_mi_buddy_adapter_reset(_adapter *padapter);
++
++u8 rtw_mi_dynamic_check_timer_handlder(_adapter *padapter);
++u8 rtw_mi_buddy_dynamic_check_timer_handlder(_adapter *padapter);
++
++extern void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter);
++u8 rtw_mi_dynamic_chk_wk_hdl(_adapter *padapter);
++u8 rtw_mi_buddy_dynamic_chk_wk_hdl(_adapter *padapter);
++
++u8 rtw_mi_os_xmit_schedule(_adapter *padapter);
++u8 rtw_mi_buddy_os_xmit_schedule(_adapter *padapter);
++
++u8 rtw_mi_report_survey_event(_adapter *padapter, union recv_frame *precv_frame);
++u8 rtw_mi_buddy_report_survey_event(_adapter *padapter, union recv_frame *precv_frame);
++
++extern void sreset_start_adapter(_adapter *padapter);
++extern void sreset_stop_adapter(_adapter *padapter);
++u8 rtw_mi_sreset_adapter_hdl(_adapter *padapter, u8 bstart);
++u8 rtw_mi_buddy_sreset_adapter_hdl(_adapter *padapter, u8 bstart);
++#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE)
++void rtw_mi_ap_info_restore(_adapter *adapter);
++#endif
++
++u8 rtw_mi_tx_beacon_hdl(_adapter *padapter);
++u8 rtw_mi_buddy_tx_beacon_hdl(_adapter *padapter);
++
++u8 rtw_mi_set_tx_beacon_cmd(_adapter *padapter);
++u8 rtw_mi_buddy_set_tx_beacon_cmd(_adapter *padapter);
++
++#ifdef CONFIG_P2P
++u8 rtw_mi_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state);
++u8 rtw_mi_buddy_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state);
++u8 rtw_mi_stay_in_p2p_mode(_adapter *padapter);
++u8 rtw_mi_buddy_stay_in_p2p_mode(_adapter *padapter);
++#endif
++
++_adapter *rtw_get_iface_by_id(_adapter *padapter, u8 iface_id);
++_adapter *rtw_get_iface_by_macddr(_adapter *padapter, const u8 *mac_addr);
++_adapter *rtw_get_iface_by_hwport(_adapter *padapter, u8 hw_port);
++
++void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvframe, u8 *pphy_status);
++
++#ifdef CONFIG_PCI_HCI
++/*API be create temporary for MI, caller is interrupt-handler, PCIE's interrupt handler cannot apply to multi-AP*/
++_adapter *rtw_mi_get_ap_adapter(_adapter *padapter);
++#endif
++
++u8 rtw_mi_get_ld_sta_ifbmp(_adapter *adapter);
++u8 rtw_mi_get_ap_mesh_ifbmp(_adapter *adapter);
++void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b);
++
++#endif /*__RTW_MI_H_*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mlme.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mlme.h
+new file mode 100755
+index 000000000..3e66080a1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mlme.h
+@@ -0,0 +1,1199 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_MLME_H_
++#define __RTW_MLME_H_
++
++
++#define	MAX_BSS_CNT	128
++/* #define   MAX_JOIN_TIMEOUT	2000 */
++/* #define   MAX_JOIN_TIMEOUT	2500 */
++#define   MAX_JOIN_TIMEOUT	6500
++
++/*	Commented by Albert 20101105
++ *	Increase the scanning timeout because of increasing the SURVEY_TO value. */
++#define	SCANQUEUE_LIFETIME 20000 /* 20sec, unit:msec */
++
++/*pmlmepriv->fw_state*/
++#define WIFI_NULL_STATE				0x00000000
++#define WIFI_ASOC_STATE				0x00000001 /* Linked */
++#define WIFI_REASOC_STATE			0x00000002
++#define WIFI_SLEEP_STATE			0x00000004
++#define WIFI_STATION_STATE			0x00000008
++#define WIFI_AP_STATE				0x00000010
++#define WIFI_ADHOC_STATE			0x00000020
++#define WIFI_ADHOC_MASTER_STATE		0x00000040
++#define WIFI_UNDER_LINKING			0x00000080
++#define WIFI_UNDER_WPS				0x00000100
++#define WIFI_MESH_STATE				0x00000200
++#define WIFI_STA_ALIVE_CHK_STATE		0x00000400
++#define WIFI_UNDER_SURVEY			0x00000800 /* under site surveying */
++/*#define WIFI_UNDEFINED_STATE			0x00001000*/
++/*#define WIFI_UNDEFINED_STATE			0x00002000*/
++/*#define WIFI_UNDEFINED_STATE			0x00004000*/
++/*#define WIFI_UNDEFINED_STATE			0x00008000*/
++#define WIFI_MP_STATE				0x00010000
++/*#define WIFI_UNDEFINED_STATE			0x00020000*/
++/*#define WIFI_UNDEFINED_STATE			0x00040000*/
++/*#define WIFI_UNDEFINED_STATE			0x00080000*/
++/*#define WIFI_UNDEFINED_STATE			0x00100000*/
++/*#define WIFI_UNDEFINED_STATE			0x00200000*/ 
++/*#define WIFI_UNDEFINED_STATE			0x00400000*/
++#define WIFI_OP_CH_SWITCHING			0x00800000
++#define WIFI_UNDER_KEY_HANDSHAKE		0x01000000
++/*#define WIFI_UNDEFINED_STATE			0x02000000*/
++/*#define WIFI_UNDEFINED_STATE			0x04000000*/
++/*#define WIFI_UNDEFINED_STATE			0x08000000*/
++/*#define WIFI_UNDEFINED_STATE			0x10000000*/
++/*#define WIFI_UNDEFINED_STATE			0x20000000*/
++/*#define WIFI_UNDEFINED_STATE			0x40000000*/
++#define WIFI_MONITOR_STATE			0x80000000
++
++
++#define MIRACAST_DISABLED	0
++#define MIRACAST_SOURCE		BIT0
++#define MIRACAST_SINK		BIT1
++
++#define MIRACAST_MODE_REVERSE(mode) \
++	((((mode) & MIRACAST_SOURCE) ? MIRACAST_SINK : 0) | (((mode) & MIRACAST_SINK) ? MIRACAST_SOURCE : 0))
++
++bool is_miracast_enabled(_adapter *adapter);
++bool rtw_chk_miracast_mode(_adapter *adapter, u8 mode);
++const char *get_miracast_mode_str(int mode);
++void rtw_wfd_st_switch(struct sta_info *sta, bool on);
++
++#define MLME_STATE(adapter) get_fwstate(&((adapter)->mlmepriv))
++#define CHK_MLME_STATE(adapter, state) check_fwstate(&((adapter)->mlmepriv), (state))
++
++#define MLME_IS_NULL(adapter) CHK_MLME_STATE(adapter, WIFI_NULL_STATE)
++#define MLME_IS_STA(adapter) CHK_MLME_STATE(adapter, WIFI_STATION_STATE)
++#define MLME_IS_AP(adapter) CHK_MLME_STATE(adapter, WIFI_AP_STATE)
++#define MLME_IS_ADHOC(adapter) CHK_MLME_STATE(adapter, WIFI_ADHOC_STATE)
++#define MLME_IS_ADHOC_MASTER(adapter) CHK_MLME_STATE(adapter, WIFI_ADHOC_MASTER_STATE)
++#define MLME_IS_MESH(adapter) CHK_MLME_STATE(adapter, WIFI_MESH_STATE)
++#define MLME_IS_MONITOR(adapter) CHK_MLME_STATE(adapter, WIFI_MONITOR_STATE)
++#define MLME_IS_MP(adapter) CHK_MLME_STATE(adapter, WIFI_MP_STATE)
++#ifdef CONFIG_P2P
++	#define MLME_IS_PD(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_DEVICE)
++	#define MLME_IS_GC(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_CLIENT)
++	#define MLME_IS_GO(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_GO)
++#else /* !CONFIG_P2P */
++	#define MLME_IS_PD(adapter) 0
++	#define MLME_IS_GC(adapter) 0
++	#define MLME_IS_GO(adapter) 0
++#endif /* !CONFIG_P2P */
++
++#define MLME_IS_MSRC(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SOURCE)
++#define MLME_IS_MSINK(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SINK)
++
++#define MLME_IS_SCAN(adapter) CHK_MLME_STATE(adapter, WIFI_UNDER_SURVEY)
++#define MLME_IS_LINKING(adapter) CHK_MLME_STATE(adapter, WIFI_UNDER_LINKING)
++#define MLME_IS_ASOC(adapter) CHK_MLME_STATE(adapter, WIFI_ASOC_STATE)
++#define MLME_IS_OPCH_SW(adapter) CHK_MLME_STATE(adapter, WIFI_OP_CH_SWITCHING)
++#define MLME_IS_WPS(adapter) CHK_MLME_STATE(adapter, WIFI_UNDER_WPS)
++
++#if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P)
++#define MLME_IS_ROCH(adapter) (rtw_cfg80211_get_is_roch(adapter) == _TRUE)
++#else
++#define MLME_IS_ROCH(adapter) 0
++#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++#define MLME_IS_MGMT_TX(adapter) rtw_cfg80211_get_is_mgmt_tx(adapter)
++#else
++#define MLME_IS_MGMT_TX(adapter) 0
++#endif
++
++#define MLME_STATE_FMT "%s%s%s%s%s%s%s%s%s%s%s%s"
++#define MLME_STATE_ARG(adapter) \
++	MLME_IS_STA((adapter)) ? (MLME_IS_GC((adapter)) ? " GC" : " STA") : \
++	MLME_IS_AP((adapter)) ? (MLME_IS_GO((adapter)) ? " GO" : " AP") : \
++	MLME_IS_ADHOC((adapter)) ? " ADHOC" : \
++	MLME_IS_ADHOC_MASTER((adapter)) ? " ADHOC_M" : \
++	MLME_IS_MESH((adapter)) ? " MESH" : \
++	MLME_IS_MONITOR((adapter)) ? " MONITOR" : \
++	MLME_IS_MP((adapter)) ? " MP" : "", \
++	MLME_IS_PD((adapter)) ? " PD" : "", \
++	MLME_IS_MSRC((adapter)) ? " MSRC" : "", \
++	MLME_IS_MSINK((adapter)) ? " MSINK" : "", \
++	MLME_IS_SCAN((adapter)) ? " SCAN" : "", \
++	MLME_IS_LINKING((adapter)) ? " LINKING" : "", \
++	MLME_IS_ASOC((adapter)) ? " ASOC" : "", \
++	MLME_IS_OPCH_SW((adapter)) ? " OPCH_SW" : "", \
++	MLME_IS_WPS((adapter)) ? " WPS" : "", \
++	MLME_IS_ROCH((adapter)) ? " ROCH" : "", \
++	MLME_IS_MGMT_TX((adapter)) ? " MGMT_TX" : "", \
++	(MLME_STATE((adapter)) & WIFI_SLEEP_STATE) ? " SLEEP" : ""
++
++enum {
++	MLME_ACTION_UNKNOWN,
++	MLME_ACTION_NONE,
++	MLME_SCAN_ENABLE, /* WIFI_UNDER_SURVEY */
++	MLME_SCAN_ENTER, /* WIFI_UNDER_SURVEY && !SCAN_DISABLE && !SCAN_BACK_OP */
++	MLME_SCAN_DONE, /*  WIFI_UNDER_SURVEY && (SCAN_DISABLE || SCAN_BACK_OP) */
++	MLME_SCAN_DISABLE, /* WIFI_UNDER_SURVEY is going to be cleared */
++	MLME_STA_CONNECTING,
++	MLME_STA_CONNECTED,
++	MLME_STA_DISCONNECTED,
++	MLME_TDLS_LINKED,
++	MLME_TDLS_NOLINK,
++	MLME_AP_STARTED,
++	MLME_AP_STOPPED,
++	MLME_ADHOC_STARTED,
++	MLME_ADHOC_STOPPED,
++	MLME_MESH_STARTED,
++	MLME_MESH_STOPPED,
++	MLME_OPCH_SWITCH,
++};
++
++enum dot11AuthAlgrthmNum {
++	dot11AuthAlgrthm_Open = 0,
++	dot11AuthAlgrthm_Shared,
++	dot11AuthAlgrthm_8021X,
++	dot11AuthAlgrthm_Auto,
++	dot11AuthAlgrthm_WAPI,
++	dot11AuthAlgrthm_MaxNum
++};
++
++/**
++ * enum mlme_auth_type - AuthenticationType
++ *
++ * @MLME_AUTHTYPE_OPEN_SYSTEM: Open System authentication
++ * @MLME_AUTHTYPE_SHARED_KEY: Shared Key authentication (WEP only)
++ * @MLME_AUTHTYPE_FT: Fast BSS Transition (IEEE 802.11r)
++ * @MLME_AUTHTYPE_NETWORK_EAP: Network EAP (some Cisco APs and mainly LEAP)
++ * @MLME_AUTHTYPE_SAE: Simultaneous authentication of equals
++ * @MLME_AUTHTYPE_FILS_SK: Fast Initial Link Setup shared key
++ * @MLME_AUTHTYPE_FILS_SK_PFS: Fast Initial Link Setup shared key with PFS
++ * @MLME_AUTHTYPE_FILS_PK: Fast Initial Link Setup public key
++ * @__MLME_AUTHTYPE_NUM: internal
++ * @MLME_AUTHTYPE_MAX: maximum valid auth algorithm
++ * @MLME_AUTHTYPE_AUTOMATIC: determine automatically (if necessary by trying
++ *      multiple times); this is invalid in netlink -- leave out the attribute
++ *      for this on CONNECT commands.
++ */
++enum mlme_auth_type {
++	MLME_AUTHTYPE_OPEN_SYSTEM,
++	MLME_AUTHTYPE_SHARED_KEY,
++	MLME_AUTHTYPE_FT,
++	MLME_AUTHTYPE_NETWORK_EAP,
++	MLME_AUTHTYPE_SAE,
++	MLME_AUTHTYPE_FILS_SK,
++	MLME_AUTHTYPE_FILS_SK_PFS,
++	MLME_AUTHTYPE_FILS_PK,
++
++	/* keep last */
++	__MLME_AUTHTYPE_NUM,
++	MLME_AUTHTYPE_MAX = __MLME_AUTHTYPE_NUM - 1,
++	MLME_AUTHTYPE_AUTOMATIC
++};
++
++/* Scan type including active and passive scan. */
++typedef enum _RT_SCAN_TYPE {
++	SCAN_PASSIVE,
++	SCAN_ACTIVE,
++	SCAN_MIX,
++} RT_SCAN_TYPE, *PRT_SCAN_TYPE;
++
++#define WIFI_FREQUENCY_BAND_AUTO 0
++#define WIFI_FREQUENCY_BAND_5GHZ 1
++#define WIFI_FREQUENCY_BAND_2GHZ 2
++
++#define rtw_band_valid(band) ((band) <= WIFI_FREQUENCY_BAND_2GHZ)
++
++enum DriverInterface {
++	DRIVER_WEXT =  1,
++	DRIVER_CFG80211 = 2
++};
++
++enum SCAN_RESULT_TYPE {
++	SCAN_RESULT_P2P_ONLY = 0,		/*	Will return all the P2P devices. */
++	SCAN_RESULT_ALL = 1,			/*	Will return all the scanned device, include AP. */
++	SCAN_RESULT_WFD_TYPE = 2		/*	Will just return the correct WFD device. */
++									/*	If this device is Miracast sink device, it will just return all the Miracast source devices. */
++};
++
++/*
++
++there are several "locks" in mlme_priv,
++since mlme_priv is a shared resource between many threads,
++like ISR/Call-Back functions, the OID handlers, and even timer functions.
++
++
++Each _queue has its own locks, already.
++Other items are protected by mlme_priv.lock.
++
++To avoid possible dead lock, any thread trying to modifiying mlme_priv
++SHALL not lock up more than one locks at a time!
++
++*/
++
++
++#define traffic_threshold	10
++#define	traffic_scan_period	500
++
++typedef struct _RT_LINK_DETECT_T {
++	u32				NumTxOkInPeriod;
++	u32				NumRxOkInPeriod;
++	u32				NumRxUnicastOkInPeriod;
++	BOOLEAN			bBusyTraffic;
++	BOOLEAN			bTxBusyTraffic;
++	BOOLEAN			bRxBusyTraffic;
++	BOOLEAN			bHigherBusyTraffic; /* For interrupt migration purpose. */
++	BOOLEAN			bHigherBusyRxTraffic; /* We may disable Tx interrupt according as Rx traffic. */
++	BOOLEAN			bHigherBusyTxTraffic; /* We may disable Tx interrupt according as Tx traffic. */
++	/* u8 TrafficBusyState; */
++	u8 TrafficTransitionCount;
++	u32 LowPowerTransitionCount;
++} RT_LINK_DETECT_T, *PRT_LINK_DETECT_T;
++
++struct profile_info {
++	u8	ssidlen;
++	u8	ssid[WLAN_SSID_MAXLEN];
++	u8	peermac[ETH_ALEN];
++};
++
++struct tx_invite_req_info {
++	u8					token;
++	u8					benable;
++	u8					go_ssid[WLAN_SSID_MAXLEN];
++	u8					ssidlen;
++	u8					go_bssid[ETH_ALEN];
++	u8					peer_macaddr[ETH_ALEN];
++	u8					operating_ch;	/*	This information will be set by using the p2p_set op_ch=x */
++	u8					peer_ch;		/*	The listen channel for peer P2P device */
++
++};
++
++struct tx_invite_resp_info {
++	u8					token;	/*	Used to record the dialog token of p2p invitation request frame. */
++};
++
++#ifdef CONFIG_WFD
++
++struct wifi_display_info {
++	u16							wfd_enable;			/*	Eanble/Disable the WFD function. */
++	u16							init_rtsp_ctrlport;	/* init value of rtsp_ctrlport when WFD enable */
++	u16							rtsp_ctrlport;		/* TCP port number at which the this WFD device listens for RTSP messages, 0 when WFD disable */
++	u16							tdls_rtsp_ctrlport;	/* rtsp_ctrlport used by tdls, will sync when rtsp_ctrlport is changed by user */
++	u16							peer_rtsp_ctrlport;	/*	TCP port number at which the peer WFD device listens for RTSP messages */
++													/*	This filed should be filled when receiving the gropu negotiation request */
++
++	u8							peer_session_avail;	/*	WFD session is available or not for the peer wfd device. */
++													/*	This variable will be set when sending the provisioning discovery request to peer WFD device. */
++													/*	And this variable will be reset when it is read by using the iwpriv p2p_get wfd_sa command. */
++	u8							ip_address[4];
++	u8							peer_ip_address[4];
++	u8							wfd_pc;				/*	WFD preferred connection */
++													/*	0 -> Prefer to use the P2P for WFD connection on peer side. */
++													/*	1 -> Prefer to use the TDLS for WFD connection on peer side. */
++
++	u8							wfd_device_type;	/*	WFD Device Type */
++													/*	0 -> WFD Source Device */
++													/*	1 -> WFD Primary Sink Device */
++	enum	SCAN_RESULT_TYPE	scan_result_type;	/*	Used when P2P is enable. This parameter will impact the scan result. */
++	u8 op_wfd_mode;
++	u8 stack_wfd_mode;
++};
++#endif /* CONFIG_WFD */
++
++struct tx_provdisc_req_info {
++	u16					wps_config_method_request;	/*	Used when sending the provisioning request frame */
++	u16					peer_channel_num[2];		/*	The channel number which the receiver stands. */
++	NDIS_802_11_SSID	ssid;
++	u8					peerDevAddr[ETH_ALEN];		/*	Peer device address */
++	u8					peerIFAddr[ETH_ALEN];		/*	Peer interface address */
++	u8					benable;					/*	This provision discovery request frame is trigger to send or not */
++};
++
++struct rx_provdisc_req_info {	/* When peer device issue prov_disc_req first, we should store the following informations */
++	u8					peerDevAddr[ETH_ALEN];		/*	Peer device address */
++	u8					strconfig_method_desc_of_prov_disc_req[4];	/*	description for the config method located in the provisioning discovery request frame.	 */
++																	/*	The UI must know this information to know which config method the remote p2p device is requiring. */
++};
++
++struct tx_nego_req_info {
++	u16					peer_channel_num[2];		/*	The channel number which the receiver stands. */
++	u8					peerDevAddr[ETH_ALEN];		/*	Peer device address */
++	u8					benable;					/*	This negoitation request frame is trigger to send or not */
++	u8					peer_ch;					/*	The listen channel for peer P2P device */
++};
++
++struct group_id_info {
++	u8					go_device_addr[ETH_ALEN];	/*	The GO's device address of this P2P group */
++	u8					ssid[WLAN_SSID_MAXLEN];		/*	The SSID of this P2P group */
++};
++
++struct scan_limit_info {
++	u8					scan_op_ch_only;			/*	When this flag is set, the driver should just scan the operation channel */
++#ifndef CONFIG_P2P_OP_CHK_SOCIAL_CH
++	u8					operation_ch[2];				/*	Store the operation channel of invitation request frame */
++#else
++	u8					operation_ch[5];				/*	Store additional channel 1,6,11  for Android 4.2 IOT & Nexus 4 */
++#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
++};
++
++#ifdef CONFIG_IOCTL_CFG80211
++struct cfg80211_wifidirect_info {
++	_timer					remain_on_ch_timer;
++	u8						restore_channel;
++	struct ieee80211_channel	remain_on_ch_channel;
++	enum nl80211_channel_type	remain_on_ch_type;
++	ATOMIC_T ro_ch_cookie_gen;
++	u64 remain_on_ch_cookie;
++	bool is_ro_ch;
++	struct wireless_dev *ro_ch_wdev;
++	systime last_ro_ch_time; /* this will be updated at the beginning and end of ro_ch */
++};
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++#ifdef CONFIG_P2P_WOWLAN
++
++enum P2P_WOWLAN_RECV_FRAME_TYPE {
++	P2P_WOWLAN_RECV_NEGO_REQ = 0,
++	P2P_WOWLAN_RECV_INVITE_REQ = 1,
++	P2P_WOWLAN_RECV_PROVISION_REQ = 2,
++};
++
++struct p2p_wowlan_info {
++
++	u8						is_trigger;
++	enum P2P_WOWLAN_RECV_FRAME_TYPE	wowlan_recv_frame_type;
++	u8						wowlan_peer_addr[ETH_ALEN];
++	u16						wowlan_peer_wpsconfig;
++	u8						wowlan_peer_is_persistent;
++	u8						wowlan_peer_invitation_type;
++};
++
++#endif /* CONFIG_P2P_WOWLAN */
++
++struct wifidirect_info {
++	_adapter				*padapter;
++	_timer					find_phase_timer;
++	_timer					restore_p2p_state_timer;
++
++	/*	Used to do the scanning. After confirming the peer is availalble, the driver transmits the P2P frame to peer. */
++	_timer					pre_tx_scan_timer;
++	_timer					reset_ch_sitesurvey;
++	_timer					reset_ch_sitesurvey2;	/*	Just for resetting the scan limit function by using p2p nego */
++#ifdef CONFIG_CONCURRENT_MODE
++	/*	Used to switch the channel between legacy AP and listen state. */
++	_timer					ap_p2p_switch_timer;
++#endif
++	struct tx_provdisc_req_info	tx_prov_disc_info;
++	struct rx_provdisc_req_info rx_prov_disc_info;
++	struct tx_invite_req_info	invitereq_info;
++	struct profile_info			profileinfo[P2P_MAX_PERSISTENT_GROUP_NUM];	/*	Store the profile information of persistent group */
++	struct tx_invite_resp_info	inviteresp_info;
++	struct tx_nego_req_info	nego_req_info;
++	struct group_id_info		groupid_info;	/*	Store the group id information when doing the group negotiation handshake. */
++	struct scan_limit_info		rx_invitereq_info;	/*	Used for get the limit scan channel from the Invitation procedure */
++	struct scan_limit_info		p2p_info;		/*	Used for get the limit scan channel from the P2P negotiation handshake */
++#ifdef CONFIG_WFD
++	struct wifi_display_info		*wfd_info;
++#endif
++
++#ifdef CONFIG_P2P_WOWLAN
++	struct p2p_wowlan_info		p2p_wow_info;
++#endif /* CONFIG_P2P_WOWLAN */
++
++	enum P2P_ROLE			role;
++	enum P2P_STATE			pre_p2p_state;
++	enum P2P_STATE			p2p_state;
++	u8						device_addr[ETH_ALEN];	/*	The device address should be the mac address of this device. */
++	u8						interface_addr[ETH_ALEN];
++	u8						social_chan[4];
++	u8						listen_channel;
++	u8						operating_channel;
++	u8						listen_dwell;		/*	This value should be between 1 and 3 */
++	u8						support_rate[8];
++	u8						p2p_wildcard_ssid[P2P_WILDCARD_SSID_LEN];
++	u8						intent;		/*	should only include the intent value. */
++	u8						p2p_peer_interface_addr[ETH_ALEN];
++	u8						p2p_peer_device_addr[ETH_ALEN];
++	u8						peer_intent;	/*	Included the intent value and tie breaker value. */
++	u8						device_name[WPS_MAX_DEVICE_NAME_LEN];	/*	Device name for displaying on searching device screen */
++	u16						device_name_len;
++	u8						profileindex;	/*	Used to point to the index of profileinfo array */
++	u8						peer_operating_ch;
++	u8						find_phase_state_exchange_cnt;
++	u16						device_password_id_for_nego;	/*	The device password ID for group negotation */
++	u8						negotiation_dialog_token;
++	u8						nego_ssid[WLAN_SSID_MAXLEN];	/*	SSID information for group negotitation */
++	u8						nego_ssidlen;
++	u8						p2p_group_ssid[WLAN_SSID_MAXLEN];
++	u8						p2p_group_ssid_len;
++	u8						persistent_supported;		/*	Flag to know the persistent function should be supported or not. */
++														/*	In the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI. */
++														/*	0: disable */
++														/*	1: enable */
++	u8						session_available;			/*	Flag to set the WFD session available to enable or disable "by Sigma" */
++														/*	In the Sigma test, the Sigma will disable the session available by using the sta_preset CAPI. */
++														/*	0: disable */
++														/*	1: enable */
++
++	u8						wfd_tdls_enable;			/*	Flag to enable or disable the TDLS by WFD Sigma */
++														/*	0: disable */
++														/*	1: enable */
++	u8						wfd_tdls_weaksec;			/*	Flag to enable or disable the weak security function for TDLS by WFD Sigma */
++														/*	0: disable */
++														/*	In this case, the driver can't issue the tdsl setup request frame. */
++														/*	1: enable */
++														/*	In this case, the driver can issue the tdls setup request frame */
++														/*	even the current security is weak security. */
++
++	enum	P2P_WPSINFO		ui_got_wps_info;			/*	This field will store the WPS value (PIN value or PBC) that UI had got from the user. */
++	u16						supported_wps_cm;			/*	This field describes the WPS config method which this driver supported. */
++														/*	The value should be the combination of config method defined in page104 of WPS v2.0 spec.	 */
++	u8						external_uuid;				/* UUID flag */
++	u8						uuid[16];					/* UUID */
++	uint						channel_list_attr_len;	/*	This field will contain the length of body of P2P Channel List attribute of group negotitation response frame. */
++	u8						channel_list_attr[100];		/*	This field will contain the body of P2P Channel List attribute of group negotitation response frame. */
++														/*	We will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame. */
++	u8						driver_interface;			/*	Indicate DRIVER_WEXT or DRIVER_CFG80211 */
++
++#ifdef CONFIG_CONCURRENT_MODE
++	u16						ext_listen_interval;	/*	The interval to be available with legacy AP (ms) */
++	u16						ext_listen_period;	/*	The time period to be available for P2P listen state (ms) */
++#ifdef CONFIG_IOCTL_CFG80211
++	u32						min_home_dur;			/* min duration for traffic, home_time */
++	u32						max_away_dur;			/* max acceptable away duration, home_away_time */
++#endif /* CONFIG_IOCTL_CFG80211 */
++#endif
++#ifdef CONFIG_P2P_PS
++	enum P2P_PS_MODE		p2p_ps_mode; /* indicate p2p ps mode */
++	enum P2P_PS_STATE		p2p_ps_state; /* indicate p2p ps state */
++	u8						noa_index; /* Identifies and instance of Notice of Absence timing. */
++	u8						ctwindow; /* Client traffic window. A period of time in TU after TBTT. */
++	u8						opp_ps; /* opportunistic power save. */
++	u8						noa_num; /* number of NoA descriptor in P2P IE. */
++	u8						noa_count[P2P_MAX_NOA_NUM]; /* Count for owner, Type of client. */
++	u32						noa_duration[P2P_MAX_NOA_NUM]; /* Max duration for owner, preferred or min acceptable duration for client. */
++	u32						noa_interval[P2P_MAX_NOA_NUM]; /* Length of interval for owner, preferred or max acceptable interval of client. */
++	u32						noa_start_time[P2P_MAX_NOA_NUM]; /* schedule expressed in terms of the lower 4 bytes of the TSF timer. */
++#endif /* CONFIG_P2P_PS */
++};
++
++struct tdls_ss_record {	/* signal strength record */
++	u8		macaddr[ETH_ALEN];
++	u8		RxPWDBAll;
++	u8		is_tdls_sta;	/* _TRUE: direct link sta, _FALSE: else */
++};
++
++struct tdls_temp_mgmt {
++	u8	initiator;	/* 0: None, 1: we initiate, 2: peer initiate */
++	u8	peer_addr[ETH_ALEN];
++};
++
++#ifdef CONFIG_TDLS_CH_SW
++struct tdls_ch_switch {
++	u32	ch_sw_state;
++	ATOMIC_T	chsw_on;
++	u8	addr[ETH_ALEN];
++	u8	off_ch_num;
++	u8	ch_offset;
++	u32	cur_time;
++	u8	delay_switch_back;
++	u8	dump_stack;
++	struct submit_ctx	chsw_sctx;
++};
++#endif
++
++struct tdls_info {
++	u8					ap_prohibited;
++	u8					ch_switch_prohibited;
++	u8					link_established;
++	u8					sta_cnt;
++	u8					sta_maximum;	/* 1:tdls sta is equal (NUM_STA-1), reach max direct link number; 0: else; */
++	struct tdls_ss_record	ss_record;
++#ifdef CONFIG_TDLS_CH_SW
++	struct tdls_ch_switch	chsw_info;
++#endif
++
++	u8					ch_sensing;
++	u8					cur_channel;
++	u8					collect_pkt_num[MAX_CHANNEL_NUM];
++	_lock				cmd_lock;
++	_lock				hdl_lock;
++	u8					watchdog_count;
++	u8					dev_discovered;		/* WFD_TDLS: for sigma test */
++
++	/* Let wpa_supplicant to setup*/
++	u8					driver_setup;
++#ifdef CONFIG_WFD
++	struct wifi_display_info		*wfd_info;
++#endif
++
++	struct submit_ctx	*tdls_sctx;
++};
++
++struct tdls_txmgmt {
++	u8 peer[ETH_ALEN];
++	u8 action_code;
++	u8 dialog_token;
++	u16 status_code;
++	u8 *buf;
++	size_t len;
++};
++
++/* used for mlme_priv.roam_flags */
++enum {
++	RTW_ROAM_ON_EXPIRED = BIT0,
++	RTW_ROAM_ON_RESUME = BIT1,
++	RTW_ROAM_ACTIVE = BIT2,
++};
++
++
++struct mlme_priv {
++
++	_lock	lock;
++	sint	fw_state;	/* shall we protect this variable? maybe not necessarily... */
++	u8	to_join; /* flag */
++	u16 join_status;
++#ifdef CONFIG_LAYER2_ROAMING
++	u8 to_roam; /* roaming trying times */
++	struct wlan_network *roam_network; /* the target of active roam */
++	u8 roam_flags;
++	u8 roam_rssi_diff_th; /* rssi difference threshold for active scan candidate selection */
++	u32 roam_scan_int; 		/* scan interval for active roam (Unit:2 second)*/
++	u32 roam_scanr_exp_ms; /* scan result expire time in ms  for roam */
++	u8 roam_tgt_addr[ETH_ALEN]; /* request to roam to speicific target without other consideration */
++	u8 roam_rssi_threshold;
++	systime last_roaming;
++	bool need_to_roam;
++#endif
++
++	u32 defs_lmt_sta;
++	u32 defs_lmt_time;
++
++	u8	*nic_hdl;
++	u32	max_bss_cnt;		/*	The size of scan queue	*/
++	_list		*pscanned;
++	_queue	free_bss_pool;
++	_queue	scanned_queue;
++	u8		*free_bss_buf;
++	u32	num_of_scanned;
++
++	NDIS_802_11_SSID	assoc_ssid;
++	u8	assoc_bssid[6];
++	u16	assoc_ch;		/* 0 reserved for no specific channel */
++
++	struct wlan_network	cur_network;
++	struct wlan_network *cur_network_scanned;
++
++	/* bcn check info */
++	struct beacon_keys cur_beacon_keys; /* save current beacon keys */
++#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
++	struct beacon_keys new_beacon_keys; /* save new beacon keys */
++	u8 new_beacon_cnts; /* if new_beacon_cnts >= threshold, ap beacon is changed */
++#endif
++
++#ifdef CONFIG_ARP_KEEP_ALIVE
++	/* for arp offload keep alive */
++	u8 bGetGateway;
++	u8	GetGatewayTryCnt;
++	u8	gw_mac_addr[ETH_ALEN];
++	u8	gw_ip[4];
++#endif
++
++	/* uint wireless_mode; no used, remove it */
++
++	u32	auto_scan_int_ms;
++
++	_timer assoc_timer;
++
++	uint assoc_by_bssid;
++	uint assoc_by_rssi;
++
++	_timer scan_to_timer; /* driver itself handles scan_timeout status. */
++	systime scan_start_time; /* used to evaluate the time spent in scanning */
++
++#ifdef CONFIG_SET_SCAN_DENY_TIMER
++	_timer set_scan_deny_timer;
++	ATOMIC_T set_scan_deny; /* 0: allowed, 1: deny */
++#endif
++	u8 wpa_phase;/*wpa_phase after wps finished*/
++
++	struct qos_priv qospriv;
++
++#ifdef CONFIG_80211N_HT
++
++	/* Number of non-HT AP/stations */
++	int num_sta_no_ht;
++
++	/* Number of HT AP/stations 20 MHz */
++	/* int num_sta_ht_20mhz; */
++
++
++	int num_FortyMHzIntolerant;
++
++	struct ht_priv	htpriv;
++
++#endif
++
++#ifdef CONFIG_80211AC_VHT
++	struct vht_priv	vhtpriv;
++#ifdef ROKU_PRIVATE
++	/*infra mode, used to store AP's info*/
++	struct vht_priv_infra_ap vhtpriv_infra_ap;
++#endif /* ROKU_PRIVATE */
++#endif
++
++#ifdef ROKU_PRIVATE
++	struct ht_priv_infra_ap htpriv_infra_ap;
++#endif /* ROKU_PRIVATE */
++
++#ifdef CONFIG_RTW_80211R
++	struct ft_roam_info ft_roam;
++#endif
++#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
++	struct roam_nb_info nb_info;
++	u8 ch_cnt;
++#endif
++
++	RT_LINK_DETECT_T	LinkDetectInfo;
++
++	u8	acm_mask; /* for wmm acm mask */
++	RT_SCAN_TYPE	scan_mode; /* active: 1, passive: 0 */
++
++	u8 *wps_probe_req_ie;
++	u32 wps_probe_req_ie_len;
++
++	u8 ext_capab_ie_data[8];/*currently for ap mode only*/
++	u8 ext_capab_ie_len;
++
++#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
++	/* Number of associated Non-ERP stations (i.e., stations using 802.11b
++	 * in 802.11g BSS) */
++	int num_sta_non_erp;
++
++	/* Number of associated stations that do not support Short Slot Time */
++	int num_sta_no_short_slot_time;
++
++	/* Number of associated stations that do not support Short Preamble */
++	int num_sta_no_short_preamble;
++
++	ATOMIC_T olbc; /* Overlapping Legacy BSS Condition (Legacy b/g)*/
++
++	/* Number of HT associated stations that do not support greenfield */
++	int num_sta_ht_no_gf;
++
++	/* Number of associated non-HT stations */
++	/* int num_sta_no_ht; */
++
++	/* Number of HT associated stations 20 MHz */
++	int num_sta_ht_20mhz;
++
++	/* number of associated stations 40MHz intolerant */
++	int num_sta_40mhz_intolerant;
++
++	/* Overlapping BSS information */
++	ATOMIC_T olbc_ht;
++
++#ifdef CONFIG_80211N_HT
++	int ht_20mhz_width_req;
++	int ht_intolerant_ch_reported;
++	u16 ht_op_mode;
++	u8 sw_to_20mhz; /*switch to 20Mhz BW*/
++#endif /* CONFIG_80211N_HT */
++
++#ifdef CONFIG_RTW_80211R
++	u8 *auth_rsp;
++	u32 auth_rsp_len;
++#endif
++	u8 *assoc_req;
++	u32 assoc_req_len;
++
++	u8 *assoc_rsp;
++	u32 assoc_rsp_len;
++
++	/* u8 *wps_probe_req_ie; */
++	/* u32 wps_probe_req_ie_len; */
++
++	u8 *wps_beacon_ie;
++	u32 wps_beacon_ie_len;
++
++	u8 *wps_probe_resp_ie;
++	u32 wps_probe_resp_ie_len;
++
++	u8 *wps_assoc_resp_ie;
++	u32 wps_assoc_resp_ie_len;
++
++	u8 *p2p_beacon_ie;
++	u32 p2p_beacon_ie_len;
++
++	u8 *p2p_probe_req_ie;
++	u32 p2p_probe_req_ie_len;
++
++	u8 *p2p_probe_resp_ie;
++	u32 p2p_probe_resp_ie_len;
++
++	u8 *p2p_go_probe_resp_ie;		/* for GO */
++	u32 p2p_go_probe_resp_ie_len;	/* for GO */
++
++	u8 *p2p_assoc_req_ie;
++	u32 p2p_assoc_req_ie_len;
++
++	u8 *p2p_assoc_resp_ie;
++	u32 p2p_assoc_resp_ie_len;
++
++	_lock	bcn_update_lock;
++	u8		update_bcn;
++
++	u8 ori_ch;
++	u8 ori_bw;
++	u8 ori_offset;
++	#ifdef CONFIG_80211AC_VHT
++	u8 ori_vht_en;
++	#endif
++
++	u8 ap_isolate;
++#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
++
++#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)
++	u8 *wfd_beacon_ie;
++	u32 wfd_beacon_ie_len;
++
++	u8 *wfd_probe_req_ie;
++	u32 wfd_probe_req_ie_len;
++
++	u8 *wfd_probe_resp_ie;
++	u32 wfd_probe_resp_ie_len;
++
++	u8 *wfd_go_probe_resp_ie;		/* for GO */
++	u32 wfd_go_probe_resp_ie_len;	/* for GO */
++
++	u8 *wfd_assoc_req_ie;
++	u32 wfd_assoc_req_ie_len;
++
++	u8 *wfd_assoc_resp_ie;
++	u32 wfd_assoc_resp_ie_len;
++#endif
++
++#ifdef CONFIG_RTW_MBO
++	u8 *pcell_data_cap_ie;
++	u32 cell_data_cap_len;
++#endif
++
++#ifdef RTK_DMP_PLATFORM
++	/* DMP kobject_hotplug function  signal need in passive level */
++	_workitem	Linkup_workitem;
++	_workitem	Linkdown_workitem;
++#endif
++
++#ifdef RTW_BUSY_DENY_SCAN
++	systime lastscantime;
++#endif
++
++#ifdef CONFIG_CONCURRENT_MODE
++	u8	scanning_via_buddy_intf;
++#endif
++
++#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
++	u32 vendor_ie_mask[WLAN_MAX_VENDOR_IE_NUM];
++	u8 vendor_ie[WLAN_MAX_VENDOR_IE_NUM][WLAN_MAX_VENDOR_IE_LEN];
++	u32 vendor_ielen[WLAN_MAX_VENDOR_IE_NUM];
++#endif
++};
++
++#define mlme_set_scan_to_timer(mlme, ms) \
++	do { \
++		/* RTW_INFO("%s set_scan_to_timer(%p, %d)\n", __FUNCTION__, (mlme), (ms)); */ \
++		_set_timer(&(mlme)->scan_to_timer, (ms)); \
++	} while (0)
++
++#define rtw_mlme_set_auto_scan_int(adapter, ms) \
++	do { \
++		adapter->mlmepriv.auto_scan_int_ms = ms; \
++	} while (0)
++
++#define RTW_AUTO_SCAN_REASON_UNSPECIFIED		0
++#define RTW_AUTO_SCAN_REASON_2040_BSS			BIT0
++#define RTW_AUTO_SCAN_REASON_ACS				BIT1
++#define RTW_AUTO_SCAN_REASON_ROAM				BIT2
++#define RTW_AUTO_SCAN_REASON_MESH_OFFCH_CAND	BIT3
++
++void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason);
++
++#ifdef CONFIG_AP_MODE
++
++struct hostapd_priv {
++	_adapter *padapter;
++
++#ifdef CONFIG_HOSTAPD_MLME
++	struct net_device *pmgnt_netdev;
++	struct usb_anchor anchored;
++#endif
++
++};
++
++extern int hostapd_mode_init(_adapter *padapter);
++extern void hostapd_mode_unload(_adapter *padapter);
++#endif
++
++
++extern void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status);
++extern void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf);
++extern void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf);
++extern void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf);
++extern void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf);
++extern void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf);
++void rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id);
++void rtw_sta_mstatus_report(_adapter *adapter);
++extern void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf);
++#ifdef CONFIG_IEEE80211W
++void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf);
++#endif /* CONFIG_IEEE80211W */
++
++thread_return event_thread(thread_context context);
++
++extern void rtw_free_network_queue(_adapter *adapter, u8 isfreeall);
++extern int rtw_init_mlme_priv(_adapter *adapter);/* (struct mlme_priv *pmlmepriv); */
++
++extern void rtw_free_mlme_priv(struct mlme_priv *pmlmepriv);
++
++
++extern sint rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv);
++extern sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint keyid, u8 set_tx, bool enqueue);
++extern sint rtw_set_auth(_adapter *adapter, struct security_priv *psecuritypriv);
++
++__inline static u8 *get_bssid(struct mlme_priv *pmlmepriv)
++{
++	/* if sta_mode:pmlmepriv->cur_network.network.MacAddress=> bssid */
++	/* if adhoc_mode:pmlmepriv->cur_network.network.MacAddress=> ibss mac address */
++	return pmlmepriv->cur_network.network.MacAddress;
++}
++
++__inline static sint check_fwstate(struct mlme_priv *pmlmepriv, sint state)
++{
++	if ((state == WIFI_NULL_STATE) &&
++		(pmlmepriv->fw_state == WIFI_NULL_STATE))
++		return _TRUE;
++
++	if (pmlmepriv->fw_state & state)
++		return _TRUE;
++
++	return _FALSE;
++}
++
++__inline static sint get_fwstate(struct mlme_priv *pmlmepriv)
++{
++	return pmlmepriv->fw_state;
++}
++
++/*
++ * No Limit on the calling context,
++ * therefore set it to be the critical section...
++ *
++ * ### NOTE:#### (!!!!)
++ * MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock
++ */
++extern void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state);
++
++static inline void set_fwstate(struct mlme_priv *pmlmepriv, sint state)
++{
++	pmlmepriv->fw_state |= state;
++	rtw_mi_update_iface_status(pmlmepriv, state);
++}
++static inline void init_fwstate(struct mlme_priv *pmlmepriv, sint state)
++{
++	pmlmepriv->fw_state = state;
++	rtw_mi_update_iface_status(pmlmepriv, state);
++}
++
++static inline void _clr_fwstate_(struct mlme_priv *pmlmepriv, sint state)
++{
++	pmlmepriv->fw_state &= ~state;
++	rtw_mi_update_iface_status(pmlmepriv, state);
++}
++
++/*
++ * No Limit on the calling context,
++ * therefore set it to be the critical section...
++ */
++static inline void clr_fwstate(struct mlme_priv *pmlmepriv, sint state)
++{
++	_irqL irqL;
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++	_clr_fwstate_(pmlmepriv, state);
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++}
++
++static inline void up_scanned_network(struct mlme_priv *pmlmepriv)
++{
++	_irqL irqL;
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++	pmlmepriv->num_of_scanned++;
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++}
++u8 rtw_is_adapter_up(_adapter *padapter);
++
++__inline static void down_scanned_network(struct mlme_priv *pmlmepriv)
++{
++	_irqL irqL;
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++	pmlmepriv->num_of_scanned--;
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++}
++
++__inline static void set_scanned_network_val(struct mlme_priv *pmlmepriv, sint val)
++{
++	_irqL irqL;
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++	pmlmepriv->num_of_scanned = val;
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++}
++
++extern u16 rtw_get_capability(WLAN_BSSID_EX *bss);
++extern bool rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target);
++extern void rtw_disconnect_hdl_under_linked(_adapter *adapter, struct sta_info *psta, u8 free_assoc);
++extern void rtw_generate_random_ibss(u8 *pibss);
++struct wlan_network *_rtw_find_network(_queue *scanned_queue, const u8 *addr);
++struct wlan_network *rtw_find_network(_queue *scanned_queue, const u8 *addr);
++extern struct wlan_network *rtw_get_oldest_wlan_network(_queue *scanned_queue);
++struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network);
++struct wlan_network *rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network);
++
++extern void rtw_free_assoc_resources(_adapter *adapter, u8 lock_scanned_queue);
++extern void rtw_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated);
++extern void rtw_indicate_connect(_adapter *adapter);
++void rtw_indicate_scan_done(_adapter *padapter, bool aborted);
++
++void rtw_drv_scan_by_self(_adapter *padapter, u8 reason);
++void rtw_scan_wait_completed(_adapter *adapter);
++u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms);
++void rtw_scan_abort_no_wait(_adapter *adapter);
++void rtw_scan_abort(_adapter *adapter);
++u32 rtw_join_abort_timeout(_adapter *adapter, u32 timeout_ms);
++
++int rtw_cached_pmkid(_adapter *Adapter, u8 *bssid);
++int rtw_rsn_sync_pmkid(_adapter *adapter, u8 *ie, uint ie_len, int i_ent);
++
++extern int rtw_restruct_sec_ie(_adapter *adapter, u8 *out_ie);
++#ifdef CONFIG_WMMPS_STA
++void rtw_uapsd_use_default_setting(_adapter *padapter);
++bool rtw_is_wmmps_mode(_adapter *padapter);
++#endif /* CONFIG_WMMPS_STA */
++extern int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len);
++extern void rtw_init_registrypriv_dev_network(_adapter *adapter);
++
++extern void rtw_update_registrypriv_dev_network(_adapter *adapter);
++
++extern void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter);
++
++extern void rtw_join_timeout_handler(void *ctx);
++extern void rtw_scan_timeout_handler(void *ctx);
++
++extern void rtw_dynamic_check_timer_handlder(void *ctx);
++extern void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter);
++
++enum {
++	SS_DENY_MP_MODE,
++	SS_DENY_RSON_SCANING,
++	SS_DENY_BLOCK_SCAN,
++	SS_DENY_BY_DRV,
++	SS_DENY_SELF_AP_UNDER_WPS,
++	SS_DENY_SELF_AP_UNDER_LINKING,
++	SS_DENY_SELF_AP_UNDER_SURVEY,
++	/*SS_DENY_SELF_STA_UNDER_WPS,*/
++	SS_DENY_SELF_STA_UNDER_LINKING,
++	SS_DENY_SELF_STA_UNDER_SURVEY,
++	SS_DENY_BUDDY_UNDER_LINK_WPS,
++	SS_DENY_BUDDY_UNDER_SURVEY,
++	SS_DENY_BUSY_TRAFFIC,
++	SS_ALLOW,
++#ifdef DBG_LA_MODE
++	SS_DENY_LA_MODE,
++#endif
++	SS_DENY_ADAPTIVITY,
++};
++
++u8 _rtw_sitesurvey_condition_check(const char *caller, _adapter *adapter, bool check_sc_interval);
++#define rtw_sitesurvey_condition_check(adapter, check_sc_interval) _rtw_sitesurvey_condition_check(__func__, adapter, check_sc_interval)
++
++#ifdef CONFIG_SET_SCAN_DENY_TIMER
++bool rtw_is_scan_deny(_adapter *adapter);
++void rtw_clear_scan_deny(_adapter *adapter);
++void rtw_set_scan_deny_timer_hdl(void *ctx);
++void rtw_set_scan_deny(_adapter *adapter, u32 ms);
++#else
++#define rtw_is_scan_deny(adapter) _FALSE
++#define rtw_clear_scan_deny(adapter) do {} while (0)
++#define rtw_set_scan_deny(adapter, ms) do {} while (0)
++#endif
++
++void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv);
++
++#define MLME_BEACON_IE			0
++#define MLME_PROBE_REQ_IE		1
++#define MLME_PROBE_RESP_IE		2
++#define MLME_GO_PROBE_RESP_IE	3
++#define MLME_ASSOC_REQ_IE		4
++#define MLME_ASSOC_RESP_IE		5
++
++#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)
++int rtw_mlme_update_wfd_ie_data(struct mlme_priv *mlme, u8 type, u8 *ie, u32 ie_len);
++#endif
++
++
++/* extern struct wlan_network* _rtw_dequeue_network(_queue *queue); */
++
++extern struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv);
++
++
++extern void _rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 isfreeall);
++extern void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork);
++
++extern void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall);
++
++extern sint rtw_if_up(_adapter *padapter);
++
++sint rtw_linked_check(_adapter *padapter);
++
++u8 *rtw_get_capability_from_ie(u8 *ie);
++u8 *rtw_get_timestampe_from_ie(u8 *ie);
++u8 *rtw_get_beacon_interval_from_ie(u8 *ie);
++
++
++void rtw_joinbss_reset(_adapter *padapter);
++
++#ifdef CONFIG_80211N_HT
++void	rtw_ht_use_default_setting(_adapter *padapter);
++void rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len);
++unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel);
++void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel);
++void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe, u8 issue_when_busy);
++void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len);
++#endif
++
++int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork);
++int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature);
++
++#ifdef CONFIG_LAYER2_ROAMING
++#define rtw_roam_flags(adapter) ((adapter)->mlmepriv.roam_flags)
++#define rtw_chk_roam_flags(adapter, flags) ((adapter)->mlmepriv.roam_flags & flags)
++#define rtw_clr_roam_flags(adapter, flags) \
++	do { \
++		((adapter)->mlmepriv.roam_flags &= ~flags); \
++	} while (0)
++
++#define rtw_set_roam_flags(adapter, flags) \
++	do { \
++		((adapter)->mlmepriv.roam_flags |= flags); \
++	} while (0)
++
++#define rtw_assign_roam_flags(adapter, flags) \
++	do { \
++		((adapter)->mlmepriv.roam_flags = flags); \
++	} while (0)
++
++void _rtw_roaming(_adapter *adapter, struct wlan_network *tgt_network);
++void rtw_roaming(_adapter *adapter, struct wlan_network *tgt_network);
++void rtw_set_to_roam(_adapter *adapter, u8 to_roam);
++u8 rtw_dec_to_roam(_adapter *adapter);
++u8 rtw_to_roam(_adapter *adapter);
++int rtw_select_roaming_candidate(struct mlme_priv *pmlmepriv);
++#else
++#define rtw_roam_flags(adapter) 0
++#define rtw_chk_roam_flags(adapter, flags) 0
++#define rtw_clr_roam_flags(adapter, flags) do {} while (0)
++#define rtw_set_roam_flags(adapter, flags) do {} while (0)
++#define rtw_assign_roam_flags(adapter, flags) do {} while (0)
++#define _rtw_roaming(adapter, tgt_network) do {} while (0)
++#define rtw_roaming(adapter, tgt_network) do {} while (0)
++#define rtw_set_to_roam(adapter, to_roam) do {} while (0)
++#define rtw_dec_to_roam(adapter) 0
++#define rtw_to_roam(adapter) 0
++#define rtw_select_roaming_candidate(mlme) _FAIL
++#endif /* CONFIG_LAYER2_ROAMING */
++
++bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset);
++
++struct sta_media_status_rpt_cmd_parm {
++	struct sta_info *sta;
++	bool connected;
++};
++
++void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool connected);
++u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected);
++void rtw_sta_media_status_rpt_cmd_hdl(_adapter *adapter, struct sta_media_status_rpt_cmd_parm *parm);
++void rtw_sta_traffic_info(void *sel, _adapter *adapter);
++
++#define GET_ARP_HTYPE(_arp)	BE_BITS_TO_2BYTE(((u8 *)(_arp)) + 0, 0, 16)
++#define GET_ARP_PTYPE(_arp)	BE_BITS_TO_2BYTE(((u8 *)(_arp)) + 2, 0, 16)
++#define GET_ARP_HLEN(_arp)	BE_BITS_TO_1BYTE(((u8 *)(_arp)) + 4, 0, 8)
++#define GET_ARP_PLEN(_arp)	BE_BITS_TO_1BYTE(((u8 *)(_arp)) + 5, 0, 8)
++#define GET_ARP_OPER(_arp)	BE_BITS_TO_2BYTE(((u8 *)(_arp)) + 6, 0, 16)
++
++#define SET_ARP_HTYPE(_arp, _val)	SET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 0, 0, 16, _val)
++#define SET_ARP_PTYPE(_arp, _val)	SET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 2, 0, 16, _val)
++#define SET_ARP_HLEN(_arp, _val)	SET_BITS_TO_BE_1BYTE(((u8 *)(_arp)) + 4, 0, 8, _val)
++#define SET_ARP_PLEN(_arp, _val)	SET_BITS_TO_BE_1BYTE(((u8 *)(_arp)) + 5, 0, 8, _val)
++#define SET_ARP_OPER(_arp, _val)	SET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 6, 0, 16, _val)
++
++#define ARP_SHA(_arp, _hlen, _plen)	(((u8 *)(_arp)) + 8)
++#define ARP_SPA(_arp, _hlen, _plen)	(((u8 *)(_arp)) + 8 + (_hlen))
++#define ARP_THA(_arp, _hlen, _plen)	(((u8 *)(_arp)) + 8 + (_hlen) + (_plen))
++#define ARP_TPA(_arp, _hlen, _plen)	(((u8 *)(_arp)) + 8 + 2 * (_hlen) + (_plen))
++
++#define ARP_SENDER_MAC_ADDR(_arp)	ARP_SHA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)
++#define ARP_SENDER_IP_ADDR(_arp)	ARP_SPA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)
++#define ARP_TARGET_MAC_ADDR(_arp)	ARP_THA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)
++#define ARP_TARGET_IP_ADDR(_arp)	ARP_TPA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)
++
++#define GET_ARP_SENDER_MAC_ADDR(_arp, _val)	_rtw_memcpy(_val, ARP_SENDER_MAC_ADDR(_arp), ETH_ALEN)
++#define GET_ARP_SENDER_IP_ADDR(_arp, _val)	_rtw_memcpy(_val, ARP_SENDER_IP_ADDR(_arp), RTW_IP_ADDR_LEN)
++#define GET_ARP_TARGET_MAC_ADDR(_arp, _val)	_rtw_memcpy(_val, ARP_TARGET_MAC_ADDR(_arp), ETH_ALEN)
++#define GET_ARP_TARGET_IP_ADDR(_arp, _val)	_rtw_memcpy(_val, ARP_TARGET_IP_ADDR(_arp), RTW_IP_ADDR_LEN)
++
++#define SET_ARP_SENDER_MAC_ADDR(_arp, _val)	_rtw_memcpy(ARP_SENDER_MAC_ADDR(_arp), _val, ETH_ALEN)
++#define SET_ARP_SENDER_IP_ADDR(_arp, _val)	_rtw_memcpy(ARP_SENDER_IP_ADDR(_arp), _val, RTW_IP_ADDR_LEN)
++#define SET_ARP_TARGET_MAC_ADDR(_arp, _val)	_rtw_memcpy(ARP_TARGET_MAC_ADDR(_arp), _val, ETH_ALEN)
++#define SET_ARP_TARGET_IP_ADDR(_arp, _val)	_rtw_memcpy(ARP_TARGET_IP_ADDR(_arp), _val, RTW_IP_ADDR_LEN)
++
++void dump_arp_pkt(void *sel, u8 *da, u8 *sa, u8 *arp, bool tx);
++
++#define IPV4_SRC(_iphdr)			(((u8 *)(_iphdr)) + 12)
++#define IPV4_DST(_iphdr)			(((u8 *)(_iphdr)) + 16)
++#define GET_IPV4_IHL(_iphdr)		BE_BITS_TO_1BYTE(((u8 *)(_iphdr)) + 0, 0, 4)
++#define GET_IPV4_PROTOCOL(_iphdr)	BE_BITS_TO_1BYTE(((u8 *)(_iphdr)) + 9, 0, 8)
++#define GET_IPV4_SRC(_iphdr)		BE_BITS_TO_4BYTE(((u8 *)(_iphdr)) + 12, 0, 32)
++#define GET_IPV4_DST(_iphdr)		BE_BITS_TO_4BYTE(((u8 *)(_iphdr)) + 16, 0, 32)
++
++#define GET_UDP_SRC(_udphdr)			BE_BITS_TO_2BYTE(((u8 *)(_udphdr)) + 0, 0, 16)
++#define GET_UDP_DST(_udphdr)			BE_BITS_TO_2BYTE(((u8 *)(_udphdr)) + 2, 0, 16)
++#define GET_UDP_SIG1(_udphdr)			BE_BITS_TO_1BYTE(((u8 *)(_udphdr)) + 8, 0, 8)
++#define GET_UDP_SIG2(_udphdr)			BE_BITS_TO_1BYTE(((u8 *)(_udphdr)) + 23, 0, 8)
++
++#define TCP_SRC(_tcphdr)				(((u8 *)(_tcphdr)) + 0)
++#define TCP_DST(_tcphdr)				(((u8 *)(_tcphdr)) + 2)
++#define GET_TCP_SRC(_tcphdr)			BE_BITS_TO_2BYTE(((u8 *)(_tcphdr)) + 0, 0, 16)
++#define GET_TCP_DST(_tcphdr)			BE_BITS_TO_2BYTE(((u8 *)(_tcphdr)) + 2, 0, 16)
++#define GET_TCP_SEQ(_tcphdr)			BE_BITS_TO_4BYTE(((u8 *)(_tcphdr)) + 4, 0, 32)
++#define GET_TCP_ACK_SEQ(_tcphdr)		BE_BITS_TO_4BYTE(((u8 *)(_tcphdr)) + 8, 0, 32)
++#define GET_TCP_DOFF(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 12, 4, 4)
++#define GET_TCP_FIN(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 0, 1)
++#define GET_TCP_SYN(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 1, 1)
++#define GET_TCP_RST(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 2, 1)
++#define GET_TCP_PSH(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 3, 1)
++#define GET_TCP_ACK(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 4, 1)
++#define GET_TCP_URG(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 5, 1)
++#define GET_TCP_ECE(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 6, 1)
++#define GET_TCP_CWR(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 7, 1)
++
++#endif /* __RTL871X_MLME_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mlme_ext.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mlme_ext.h
+new file mode 100755
+index 000000000..544c1951d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mlme_ext.h
+@@ -0,0 +1,1179 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_MLME_EXT_H_
++#define __RTW_MLME_EXT_H_
++
++
++/*	Commented by Albert 20101105
++ *	Increase the SURVEY_TO value from 100 to 150  ( 100ms to 150ms )
++ *	The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request.
++ *	So, this driver tried to extend the dwell time for each scanning channel.
++ *	This will increase the chance to receive the probe response from SoftAP. */
++#define SURVEY_TO		(100)
++
++#define REAUTH_TO		(300) /* (50) */
++#define REASSOC_TO		(300) /* (50) */
++/* #define DISCONNECT_TO	(3000) */
++#define ADDBA_TO			(2000)
++
++#define LINKED_TO (1) /* unit:2 sec, 1x2 = 2 sec */
++
++#define REAUTH_LIMIT	(4)
++#define REASSOC_LIMIT	(4)
++#define READDBA_LIMIT	(2)
++
++#ifdef CONFIG_GSPI_HCI
++	#define ROAMING_LIMIT	5
++#else
++	#define ROAMING_LIMIT	8
++#endif
++
++/*net_type, pmlmeinfo->state*/
++#define _HW_STATE_NOLINK_	0x00
++#define _HW_STATE_ADHOC_	0x01
++#define _HW_STATE_STATION_	0x02
++#define _HW_STATE_AP_		0x03
++#define _HW_STATE_MONITOR_	0x04
++
++#define	WIFI_FW_NULL_STATE		_HW_STATE_NOLINK_
++#define	WIFI_FW_STATION_STATE		_HW_STATE_STATION_
++#define	WIFI_FW_AP_STATE		_HW_STATE_AP_
++#define	WIFI_FW_ADHOC_STATE		_HW_STATE_ADHOC_
++
++#define	WIFI_FW_PRE_LINK		0x00000800
++#define	WIFI_FW_AUTH_NULL		0x00000100
++#define	WIFI_FW_AUTH_STATE		0x00000200
++#define	WIFI_FW_AUTH_SUCCESS		0x00000400
++
++#define	WIFI_FW_ASSOC_STATE		0x00002000
++#define	WIFI_FW_ASSOC_SUCCESS		0x00004000
++
++#define	WIFI_FW_LINKING_STATE		(WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE | WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE)
++
++
++#define		_1M_RATE_	0
++#define		_2M_RATE_	1
++#define		_5M_RATE_	2
++#define		_11M_RATE_	3
++#define		_6M_RATE_	4
++#define		_9M_RATE_	5
++#define		_12M_RATE_	6
++#define		_18M_RATE_	7
++#define		_24M_RATE_	8
++#define		_36M_RATE_	9
++#define		_48M_RATE_	10
++#define		_54M_RATE_	11
++
++/********************************************************
++MCS rate definitions
++*********************************************************/
++#define MCS_RATE_1R	(0x000000ff)
++#define MCS_RATE_2R	(0x0000ffff)
++#define MCS_RATE_3R	(0x00ffffff)
++#define MCS_RATE_4R	(0xffffffff)
++#define MCS_RATE_2R_13TO15_OFF	(0x00001fff)
++
++
++extern unsigned char RTW_WPA_OUI[];
++extern unsigned char WMM_OUI[];
++extern unsigned char WPS_OUI[];
++extern unsigned char WFD_OUI[];
++extern unsigned char P2P_OUI[];
++extern unsigned char MULTI_AP_OUI[];
++
++extern unsigned char WMM_INFO_OUI[];
++extern unsigned char WMM_PARA_OUI[];
++
++typedef struct _RT_CHANNEL_PLAN {
++	unsigned char	Channel[MAX_CHANNEL_NUM];
++	unsigned char	Len;
++} RT_CHANNEL_PLAN, *PRT_CHANNEL_PLAN;
++
++typedef enum _HT_IOT_PEER {
++	HT_IOT_PEER_UNKNOWN			= 0,
++	HT_IOT_PEER_REALTEK			= 1,
++	HT_IOT_PEER_REALTEK_92SE		= 2,
++	HT_IOT_PEER_BROADCOM		= 3,
++	HT_IOT_PEER_RALINK			= 4,
++	HT_IOT_PEER_ATHEROS			= 5,
++	HT_IOT_PEER_CISCO				= 6,
++	HT_IOT_PEER_MERU				= 7,
++	HT_IOT_PEER_MARVELL			= 8,
++	HT_IOT_PEER_REALTEK_SOFTAP 	= 9,/* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */
++	HT_IOT_PEER_SELF_SOFTAP 		= 10, /* Self is SoftAP */
++	HT_IOT_PEER_AIRGO				= 11,
++	HT_IOT_PEER_INTEL				= 12,
++	HT_IOT_PEER_RTK_APCLIENT		= 13,
++	HT_IOT_PEER_REALTEK_81XX		= 14,
++	HT_IOT_PEER_REALTEK_WOW		= 15,
++	HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 16,
++	HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 17,
++	HT_IOT_PEER_MAX				= 18
++} HT_IOT_PEER_E, *PHTIOT_PEER_E;
++
++
++typedef enum _RT_HT_INF0_CAP {
++	RT_HT_CAP_USE_TURBO_AGGR = 0x01,
++	RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
++	RT_HT_CAP_USE_AMPDU = 0x04,
++	RT_HT_CAP_USE_WOW = 0x8,
++	RT_HT_CAP_USE_SOFTAP = 0x10,
++	RT_HT_CAP_USE_92SE = 0x20,
++	RT_HT_CAP_USE_88C_92C = 0x40,
++	RT_HT_CAP_USE_AP_CLIENT_MODE = 0x80,	/* AP team request to reserve this bit, by Emily */
++} RT_HT_INF0_CAPBILITY, *PRT_HT_INF0_CAPBILITY;
++
++typedef enum _RT_HT_INF1_CAP {
++	RT_HT_CAP_USE_VIDEO_CLIENT = 0x01,
++	RT_HT_CAP_USE_JAGUAR_BCUT = 0x02,
++	RT_HT_CAP_USE_JAGUAR_CCUT = 0x04,
++} RT_HT_INF1_CAPBILITY, *PRT_HT_INF1_CAPBILITY;
++
++struct mlme_handler {
++	unsigned int   num;
++	char *str;
++	unsigned int (*func)(_adapter *padapter, union recv_frame *precv_frame);
++};
++
++struct action_handler {
++	unsigned int   num;
++	char *str;
++	unsigned int (*func)(_adapter *padapter, union recv_frame *precv_frame);
++};
++
++enum SCAN_STATE {
++	SCAN_DISABLE = 0,
++	SCAN_START = 1,
++	SCAN_PS_ANNC_WAIT = 2,
++	SCAN_ENTER = 3,
++	SCAN_PROCESS = 4,
++
++	/* backop */
++	SCAN_BACKING_OP = 5,
++	SCAN_BACK_OP = 6,
++	SCAN_LEAVING_OP = 7,
++	SCAN_LEAVE_OP = 8,
++
++	/* SW antenna diversity (before linked) */
++	SCAN_SW_ANTDIV_BL = 9,
++
++	/* legacy p2p */
++	SCAN_TO_P2P_LISTEN = 10,
++	SCAN_P2P_LISTEN = 11,
++
++	SCAN_COMPLETE = 12,
++	SCAN_STATE_MAX,
++};
++
++const char *scan_state_str(u8 state);
++
++enum ss_backop_flag {
++	SS_BACKOP_EN = BIT0, /* backop when linked */
++	SS_BACKOP_EN_NL = BIT1, /* backop even when no linked */
++
++	SS_BACKOP_PS_ANNC = BIT4,
++	SS_BACKOP_TX_RESUME = BIT5,
++};
++
++struct ss_res {
++	u8 state;
++	u8 next_state; /* will set to state on next cmd hdl */
++	int	bss_cnt;
++	int	channel_idx;
++	u8 force_ssid_scan;
++	int	scan_mode;
++	u16 scan_ch_ms;
++	u32 scan_timeout_ms;
++	u8 rx_ampdu_accept;
++	u8 rx_ampdu_size;
++	u8 igi_scan;
++	u8 igi_before_scan; /* used for restoring IGI value without enable DIG & FA_CNT */
++#ifdef CONFIG_SCAN_BACKOP
++	u8 backop_flags_sta; /* policy for station mode*/
++	#ifdef CONFIG_AP_MODE
++	u8 backop_flags_ap; /* policy for ap mode */
++	#endif
++	#ifdef CONFIG_RTW_MESH
++	u8 backop_flags_mesh; /* policy for mesh mode */
++	#endif
++	u8 backop_flags; /* per backop runtime decision */
++	u8 scan_cnt;
++	u8 scan_cnt_max;
++	systime backop_time; /* the start time of backop */
++	u16 backop_ms;
++#endif
++#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)
++	u8 is_sw_antdiv_bl_scan;
++#endif
++	u8 ssid_num;
++	u8 ch_num;
++	NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT];
++	struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT];
++
++	u32 token; 	/* 0: use to identify caller */
++	u16 duration;	/* 0: use default */
++	u8 igi;		/* 0: use defalut */
++	u8 bw;		/* 0: use default */
++
++	bool acs; /* aim to trigger channel selection when scan done */
++};
++
++#ifdef CONFIG_TDLS
++enum TDLS_option {
++	TDLS_ESTABLISHED = 1,
++	TDLS_ISSUE_PTI,
++	TDLS_CH_SW_RESP,
++	TDLS_CH_SW_PREPARE,
++	TDLS_CH_SW_START,
++	TDLS_CH_SW_TO_OFF_CHNL,
++	TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED,
++	TDLS_CH_SW_TO_BASE_CHNL,
++	TDLS_CH_SW_END_TO_BASE_CHNL,
++	TDLS_CH_SW_END,
++	TDLS_RS_RCR,
++	TDLS_TEARDOWN_STA,
++	TDLS_TEARDOWN_STA_NO_WAIT,
++	TDLS_TEARDOWN_STA_LOCALLY,
++	TDLS_TEARDOWN_STA_LOCALLY_POST,
++	maxTDLS,
++};
++
++#endif /* CONFIG_TDLS */
++
++/*
++ * Usage:
++ * When one iface acted as AP mode and the other iface is STA mode and scanning,
++ * it should switch back to AP's operating channel periodically.
++ * Parameters info:
++ * When the driver scanned RTW_SCAN_NUM_OF_CH channels, it would switch back to AP's operating channel for
++ * RTW_BACK_OP_CH_MS milliseconds.
++ * Example:
++ * For chip supports 2.4G + 5GHz and AP mode is operating in channel 1,
++ * RTW_SCAN_NUM_OF_CH is 8, RTW_BACK_OP_CH_MS is 300
++ * When it's STA mode gets set_scan command,
++ * it would
++ * 1. Doing the scan on channel 1.2.3.4.5.6.7.8
++ * 2. Back to channel 1 for 300 milliseconds
++ * 3. Go through doing site survey on channel 9.10.11.36.40.44.48.52
++ * 4. Back to channel 1 for 300 milliseconds
++ * 5. ... and so on, till survey done.
++ */
++#if defined(CONFIG_ATMEL_RC_PATCH)
++	#define RTW_SCAN_NUM_OF_CH 2
++	#define RTW_BACK_OP_CH_MS 200
++#else
++	#define RTW_SCAN_NUM_OF_CH 3
++	#define RTW_BACK_OP_CH_MS 400
++#endif
++
++#define RTW_IP_ADDR_LEN 4
++#define RTW_IPv6_ADDR_LEN 16
++
++struct mlme_ext_info {
++	u32	state;
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++	u8	hw_media_state;
++#endif
++	u32	reauth_count;
++	u32	reassoc_count;
++	u32	link_count;
++	u32	auth_seq;
++	u32	auth_algo;	/* 802.11 auth, could be open, shared, auto */
++	u16 auth_status;
++	u32	authModeToggle;
++	u32	enc_algo;/* encrypt algorithm; */
++	u32	key_index;	/* this is only valid for legendary wep, 0~3 for key id. */
++	u32	iv;
++	u8	chg_txt[128];
++	u16	aid;
++	u16	bcn_interval;
++	u16	capability;
++	u8	assoc_AP_vendor;
++	u8	slotTime;
++	u8	preamble_mode;
++	u8	WMM_enable;
++	u8	ERP_enable;
++	u8	ERP_IE;
++	u8	HT_enable;
++	u8	HT_caps_enable;
++	u8	HT_info_enable;
++	u8	HT_protection;
++	u8	turboMode_cts2self;
++	u8	turboMode_rtsen;
++	u8	SM_PS;
++	u8	agg_enable_bitmap;
++	u8	ADDBA_retry_count;
++	u8	candidate_tid_bitmap;
++	u8	dialogToken;
++	/* Accept ADDBA Request */
++	BOOLEAN bAcceptAddbaReq;
++	u8	bwmode_updated;
++	u8	hidden_ssid_mode;
++	u8	VHT_enable;
++
++	u8 ip_addr[RTW_IP_ADDR_LEN];
++	u8 ip6_addr[RTW_IPv6_ADDR_LEN];
++
++	struct ADDBA_request		ADDBA_req;
++	struct WMM_para_element	WMM_param;
++	struct HT_caps_element	HT_caps;
++	struct HT_info_element		HT_info;
++	WLAN_BSSID_EX			network;/* join network or bss_network, if in ap mode, it is the same to cur_network.network */
++#ifdef ROKU_PRIVATE
++	/*infra mode, store supported rates from AssocRsp*/
++	NDIS_802_11_RATES_EX	SupportedRates_infra_ap;
++	u8 ht_vht_received;/*ht_vht_received used to show debug msg BIT(0):HT BIT(1):VHT */
++#endif /* ROKU_PRIVATE */
++};
++
++/* The channel information about this channel including joining, scanning, and power constraints. */
++typedef struct _RT_CHANNEL_INFO {
++	u8				ChannelNum;		/* The channel number. */
++	RT_SCAN_TYPE	ScanType;		/* Scan type such as passive or active scan. */
++	bool dfs;
++	/* u16				ScanPeriod;		 */ /* Listen time in millisecond in this channel. */
++	/* s32				MaxTxPwrDbm;	 */ /* Max allowed tx power. */
++	/* u32				ExInfo;			 */ /* Extended Information for this channel. */
++#ifdef CONFIG_FIND_BEST_CHANNEL
++	u32				rx_count;
++#endif
++#if CONFIG_IEEE80211_BAND_5GHZ && CONFIG_DFS
++	#ifdef CONFIG_DFS_MASTER
++	systime non_ocp_end_time;
++	#endif
++#endif
++	u8 hidden_bss_cnt; /* per scan count */
++} RT_CHANNEL_INFO, *PRT_CHANNEL_INFO;
++
++#define CAC_TIME_MS (60*1000)
++#define CAC_TIME_CE_MS (10*60*1000)
++#define NON_OCP_TIME_MS (30*60*1000)
++
++#if CONFIG_TXPWR_LIMIT
++void rtw_txpwr_init_regd(struct rf_ctl_t *rfctl);
++#endif
++void rtw_rfctl_init(_adapter *adapter);
++void rtw_rfctl_deinit(_adapter *adapter);
++
++u8 rtw_rfctl_get_dfs_domain(struct rf_ctl_t *rfctl);
++u8 rtw_rfctl_dfs_domain_unknown(struct rf_ctl_t *rfctl);
++
++#ifdef CONFIG_DFS_MASTER
++struct rf_ctl_t;
++#define CH_IS_NON_OCP(rt_ch_info) (rtw_time_after((rt_ch_info)->non_ocp_end_time, rtw_get_current_time()))
++bool rtw_is_cac_reset_needed(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset);
++bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset);
++bool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl);
++bool rtw_rfctl_is_tx_blocked_by_ch_waiting(struct rf_ctl_t *rfctl);
++bool rtw_chset_is_chbw_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset);
++bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch);
++void rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset);
++void rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms);
++u32 rtw_get_ch_waiting_ms(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms);
++void rtw_reset_cac(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset);
++u32 rtw_force_stop_cac(struct rf_ctl_t *rfctl, u32 timeout_ms);
++#else
++#define CH_IS_NON_OCP(rt_ch_info) 0
++#define rtw_chset_is_chbw_non_ocp(ch_set, ch, bw, offset) _FALSE
++#define rtw_chset_is_ch_non_ocp(ch_set, ch) _FALSE
++#define rtw_rfctl_is_tx_blocked_by_ch_waiting(rfctl) _FALSE
++#endif
++
++enum {
++	RTW_CHF_2G = BIT0,
++	RTW_CHF_5G = BIT1,
++	RTW_CHF_DFS = BIT2,
++	RTW_CHF_LONG_CAC = BIT3,
++	RTW_CHF_NON_DFS = BIT4,
++	RTW_CHF_NON_LONG_CAC = BIT5,
++	RTW_CHF_NON_OCP = BIT6,
++};
++
++bool rtw_choose_shortest_waiting_ch(struct rf_ctl_t *rfctl, u8 sel_ch, u8 max_bw
++	, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset
++	, u8 d_flags, u8 cur_ch, bool by_int_info, u8 mesh_only);
++
++void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set);
++void dump_cur_chset(void *sel, struct rf_ctl_t *rfctl);
++
++int rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch);
++u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset
++	, bool allow_primary_passive, bool allow_passive);
++void rtw_chset_sync_chbw(RT_CHANNEL_INFO *ch_set, u8 *req_ch, u8 *req_bw, u8 *req_offset
++	, u8 *g_ch, u8 *g_bw, u8 *g_offset, bool allow_primary_passive, bool allow_passive);
++
++bool rtw_mlme_band_check(_adapter *adapter, const u32 ch);
++
++
++enum {
++	BAND_24G = BIT0,
++	BAND_5G = BIT1,
++};
++void RTW_SET_SCAN_BAND_SKIP(_adapter *padapter, int skip_band);
++void RTW_CLR_SCAN_BAND_SKIP(_adapter *padapter, int skip_band);
++int RTW_GET_SCAN_BAND_SKIP(_adapter *padapter);
++
++bool rtw_mlme_ignore_chan(_adapter *adapter, const u32 ch);
++
++/* P2P_MAX_REG_CLASSES - Maximum number of regulatory classes */
++#define P2P_MAX_REG_CLASSES 10
++
++/* P2P_MAX_REG_CLASS_CHANNELS - Maximum number of channels per regulatory class */
++#define P2P_MAX_REG_CLASS_CHANNELS 20
++
++/* struct p2p_channels - List of supported channels */
++struct p2p_channels {
++	/* struct p2p_reg_class - Supported regulatory class */
++	struct p2p_reg_class {
++		/* reg_class - Regulatory class (IEEE 802.11-2007, Annex J) */
++		u8 reg_class;
++
++		/* channel - Supported channels */
++		u8 channel[P2P_MAX_REG_CLASS_CHANNELS];
++
++		/* channels - Number of channel entries in use */
++		size_t channels;
++	} reg_class[P2P_MAX_REG_CLASSES];
++
++	/* reg_classes - Number of reg_class entries in use */
++	size_t reg_classes;
++};
++
++struct p2p_oper_class_map {
++	enum hw_mode {IEEE80211G, IEEE80211A} mode;
++	u8 op_class;
++	u8 min_chan;
++	u8 max_chan;
++	u8 inc;
++	enum { BW20, BW40PLUS, BW40MINUS } bw;
++};
++
++struct mlme_ext_priv {
++	_adapter	*padapter;
++	u8	mlmeext_init;
++	ATOMIC_T		event_seq;
++	u16	mgnt_seq;
++#ifdef CONFIG_IEEE80211W
++	u16	sa_query_seq;
++#endif
++	/* struct fw_priv 	fwpriv; */
++
++	unsigned char	cur_channel;
++	unsigned char	cur_bwmode;
++	unsigned char	cur_ch_offset;/* PRIME_CHNL_OFFSET */
++	unsigned char	cur_wireless_mode;	/* NETWORK_TYPE */
++
++	unsigned char	basicrate[NumRates];
++	unsigned char	datarate[NumRates];
++#ifdef CONFIG_80211N_HT
++	unsigned char default_supported_mcs_set[16];
++#endif
++
++	struct ss_res		sitesurvey_res;
++	struct mlme_ext_info	mlmext_info;/* for sta/adhoc mode, including current scanning/connecting/connected related info.
++                                                      * for ap mode, network includes ap's cap_info */
++	_timer		survey_timer;
++	_timer		link_timer;
++
++#ifdef CONFIG_RTW_REPEATER_SON
++	_timer		rson_scan_timer;
++#endif
++#ifdef CONFIG_RTW_80211R
++	_timer		ft_link_timer;
++	_timer		ft_roam_timer;
++#endif
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	_timer		tbtx_xmit_timer;
++	_timer		tbtx_token_dispatch_timer;
++#endif
++
++	systime last_scan_time;
++	u8	scan_abort;
++	u8 join_abort;
++	u8	tx_rate; /* TXRATE when USERATE is set. */
++
++	u32	retry; /* retry for issue probereq */
++
++	u64 TSFValue;
++	u32 bcn_cnt;
++	u32 last_bcn_cnt;
++	u8 cur_bcn_cnt;/*2s*/
++	u8 dtim;/*DTIM Period*/
++#ifdef DBG_RX_BCN
++	u8 tim[4];
++#endif
++#ifdef CONFIG_BCN_RECV_TIME
++	u16 bcn_rx_time;
++#endif
++#ifdef CONFIG_AP_MODE
++	unsigned char bstart_bss;
++#endif
++
++#ifdef CONFIG_80211D
++	u8 update_channel_plan_by_ap_done;
++#endif
++	/* recv_decache check for Action_public frame */
++	u8 action_public_dialog_token;
++	u16	 action_public_rxseq;
++
++	/* #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
++	u8 active_keep_alive_check;
++	/* #endif */
++#ifdef DBG_FIXED_CHAN
++	u8 fixed_chan;
++#endif
++
++	u8 tsf_update_required:1;
++	u8 en_hw_update_tsf:1; /* set hw sync bcn tsf register or not */
++	systime tsf_update_pause_stime;
++	u8 tsf_update_pause_factor; /* num of bcn intervals to stay TSF update pause status */
++	u8 tsf_update_restore_factor; /* num of bcn interval to stay TSF update restore status */
++#ifdef CONFIG_SUPPORT_STATIC_SMPS
++	u8 ssmps_en;
++	u16 ssmps_tx_tp_th;/*Mbps*/
++	u16 ssmps_rx_tp_th;/*Mbps*/
++	#ifdef DBG_STATIC_SMPS
++	u8 ssmps_test;
++	u8 ssmps_test_en;
++	#endif
++#endif
++#ifdef CONFIG_CTRL_TXSS_BY_TP
++	u8 txss_ctrl_en;
++	u16 txss_tp_th;/*Mbps*/
++	u8 txss_tp_chk_cnt;/*unit 2s*/
++	bool txss_1ss;
++	u8 txss_momi_type_bk;
++#endif
++};
++
++struct support_rate_handler {
++	u8 rate;
++	bool basic;
++	bool existence;
++};
++
++static inline u8 check_mlmeinfo_state(struct mlme_ext_priv *plmeext, sint state)
++{
++	if ((plmeext->mlmext_info.state & 0x03) == state)
++		return _TRUE;
++
++	return _FALSE;
++}
++
++void sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state);
++
++#define mlmeext_msr(mlmeext) ((mlmeext)->mlmext_info.state & 0x03)
++#define mlmeext_scan_state(mlmeext) ((mlmeext)->sitesurvey_res.state)
++#define mlmeext_scan_state_str(mlmeext) scan_state_str((mlmeext)->sitesurvey_res.state)
++#define mlmeext_chk_scan_state(mlmeext, _state) ((mlmeext)->sitesurvey_res.state == (_state))
++#define mlmeext_set_scan_state(mlmeext, _state) \
++	do { \
++		((mlmeext)->sitesurvey_res.state = (_state)); \
++		((mlmeext)->sitesurvey_res.next_state = (_state)); \
++		rtw_mi_update_iface_status(&((container_of(mlmeext, _adapter, mlmeextpriv)->mlmepriv)), 0); \
++		/* RTW_INFO("set_scan_state:%s\n", scan_state_str(_state)); */ \
++		sitesurvey_set_offch_state(container_of(mlmeext, _adapter, mlmeextpriv), _state); \
++	} while (0)
++
++#define mlmeext_scan_next_state(mlmeext) ((mlmeext)->sitesurvey_res.next_state)
++#define mlmeext_set_scan_next_state(mlmeext, _state) \
++	do { \
++		((mlmeext)->sitesurvey_res.next_state = (_state)); \
++		/* RTW_INFO("set_scan_next_state:%s\n", scan_state_str(_state)); */ \
++	} while (0)
++
++#ifdef CONFIG_SCAN_BACKOP
++#define mlmeext_scan_backop_flags(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags)
++#define mlmeext_chk_scan_backop_flags(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags & (flags))
++#define mlmeext_assign_scan_backop_flags(mlmeext, flags) \
++	do { \
++		((mlmeext)->sitesurvey_res.backop_flags = (flags)); \
++		RTW_INFO("assign_scan_backop_flags:0x%02x\n", (mlmeext)->sitesurvey_res.backop_flags); \
++	} while (0)
++
++#define mlmeext_scan_backop_flags_sta(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_sta)
++#define mlmeext_chk_scan_backop_flags_sta(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_sta & (flags))
++#define mlmeext_assign_scan_backop_flags_sta(mlmeext, flags) \
++	do { \
++		((mlmeext)->sitesurvey_res.backop_flags_sta = (flags)); \
++	} while (0)
++#else
++#define mlmeext_scan_backop_flags(mlmeext) (0)
++#define mlmeext_chk_scan_backop_flags(mlmeext, flags) (0)
++#define mlmeext_assign_scan_backop_flags(mlmeext, flags) do {} while (0)
++
++#define mlmeext_scan_backop_flags_sta(mlmeext) (0)
++#define mlmeext_chk_scan_backop_flags_sta(mlmeext, flags) (0)
++#define mlmeext_assign_scan_backop_flags_sta(mlmeext, flags) do {} while (0)
++#endif /* CONFIG_SCAN_BACKOP */
++
++#if defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE)
++#define mlmeext_scan_backop_flags_ap(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_ap)
++#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_ap & (flags))
++#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) \
++	do { \
++		((mlmeext)->sitesurvey_res.backop_flags_ap = (flags)); \
++	} while (0)
++#else
++#define mlmeext_scan_backop_flags_ap(mlmeext) (0)
++#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) (0)
++#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) do {} while (0)
++#endif /* defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE) */
++
++#if defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_RTW_MESH)
++#define mlmeext_scan_backop_flags_mesh(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_mesh)
++#define mlmeext_chk_scan_backop_flags_mesh(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_mesh & (flags))
++#define mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags) \
++	do { \
++		((mlmeext)->sitesurvey_res.backop_flags_mesh = (flags)); \
++	} while (0)
++#else
++#define mlmeext_scan_backop_flags_mesh(mlmeext) (0)
++#define mlmeext_chk_scan_backop_flags_mesh(mlmeext, flags) (0)
++#define mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags) do {} while (0)
++#endif /* defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_RTW_MESH) */
++
++u32 rtw_scan_timeout_decision(_adapter *padapter);
++
++void init_mlme_default_rate_set(_adapter *padapter);
++int init_mlme_ext_priv(_adapter *padapter);
++int init_hw_mlme_ext(_adapter *padapter);
++void free_mlme_ext_priv(struct mlme_ext_priv *pmlmeext);
++extern struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv);
++struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv);
++
++/* void fill_fwpriv(_adapter * padapter, struct fw_priv *pfwpriv); */
++u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen);
++void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len);
++void set_mcs_rate_by_mask(u8 *mcs_set, u32 mask);
++void UpdateBrateTbl(_adapter *padapter, u8 *mBratesOS);
++void UpdateBrateTblForSoftAP(u8 *bssrateset, u32 bssratelen);
++void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch);
++
++void Set_MSR(_adapter *padapter, u8 type);
++
++void rtw_set_external_auth_status(_adapter *padapter, const void *data, int len);
++
++u8 rtw_get_oper_ch(_adapter *adapter);
++void rtw_set_oper_ch(_adapter *adapter, u8 ch);
++u8 rtw_get_oper_bw(_adapter *adapter);
++void rtw_set_oper_bw(_adapter *adapter, u8 bw);
++u8 rtw_get_oper_choffset(_adapter *adapter);
++void rtw_set_oper_choffset(_adapter *adapter, u8 offset);
++systime rtw_get_on_oper_ch_time(_adapter *adapter);
++systime rtw_get_on_cur_ch_time(_adapter *adapter);
++
++void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode);
++
++unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval);
++
++void _clear_cam_entry(_adapter *padapter, u8 entry);
++void write_cam_from_cache(_adapter *adapter, u8 id);
++void rtw_sec_cam_swap(_adapter *adapter, u8 cam_id_a, u8 cam_id_b);
++void rtw_clean_dk_section(_adapter *adapter);
++void rtw_clean_hw_dk_cam(_adapter *adapter);
++
++/* modify both HW and cache */
++void write_cam(_adapter *padapter, u8 id, u16 ctrl, u8 *mac, u8 *key);
++void clear_cam_entry(_adapter *padapter, u8 id);
++
++/* modify cache only */
++void write_cam_cache(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key);
++void clear_cam_cache(_adapter *adapter, u8 id);
++
++void invalidate_cam_all(_adapter *padapter);
++
++void flush_all_cam_entry(_adapter *padapter);
++
++BOOLEAN IsLegal5GChannel(PADAPTER Adapter, u8 channel);
++
++void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType);
++u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid);
++void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, _adapter *padapter, bool update_ie);
++
++u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork);
++u16 get_beacon_interval(WLAN_BSSID_EX *bss);
++
++int is_client_associated_to_ap(_adapter *padapter);
++int is_client_associated_to_ibss(_adapter *padapter);
++int is_IBSS_empty(_adapter *padapter);
++
++unsigned char check_assoc_AP(u8 *pframe, uint len);
++void get_assoc_AP_Vendor(char *vendor, u8 assoc_AP_vendor);
++#ifdef CONFIG_RTS_FULL_BW
++void rtw_parse_sta_vendor_ie_8812(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len);
++#endif/*CONFIG_RTS_FULL_BW*/
++#ifdef CONFIG_80211AC_VHT
++void get_vht_bf_cap(u8 *pframe, uint len, struct vht_bf_cap *bf_cap);
++#endif
++
++int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs	pIE);
++#ifdef CONFIG_WFD
++void rtw_process_wfd_ie(_adapter *adapter, u8 *ie, u8 ie_len, const char *tag);
++void rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag);
++#endif
++void WMMOnAssocRsp(_adapter *padapter);
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++u8 rtw_is_tbtx_capabilty(u8 *p, u8 len);
++#endif
++
++void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
++#ifdef ROKU_PRIVATE
++void HT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
++#endif
++void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
++void HTOnAssocRsp(_adapter *padapter);
++
++#ifdef ROKU_PRIVATE
++void Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
++void Extended_Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
++#endif
++
++void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
++void VCS_update(_adapter *padapter, struct sta_info *psta);
++void	update_ldpc_stbc_cap(struct sta_info *psta);
++
++bool rtw_validate_value(u16 EID, u8 *p, u16 len);
++bool is_hidden_ssid(char *ssid, int len);
++bool hidden_ssid_ap(WLAN_BSSID_EX *snetwork);
++void rtw_absorb_ssid_ifneed(_adapter *padapter, WLAN_BSSID_EX *bssid, u8 *pframe);
++
++int rtw_get_bcn_keys(_adapter *adapter, u8 *whdr, u32 flen, struct beacon_keys *bcn_keys);
++int rtw_get_bcn_keys_from_bss(WLAN_BSSID_EX *bss, struct beacon_keys *bcn_keys);
++int rtw_update_bcn_keys_of_network(struct wlan_network *network);
++
++int validate_beacon_len(u8 *pframe, uint len);
++void rtw_dump_bcn_keys(void *sel, struct beacon_keys *recv_beacon);
++bool rtw_bcn_key_compare(struct beacon_keys *cur, struct beacon_keys *recv);
++int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len);
++void update_beacon_info(_adapter *padapter, u8 *pframe, uint len, struct sta_info *psta);
++#if CONFIG_DFS
++void process_csa_ie(_adapter *padapter, u8 *ies, uint ies_len);
++#endif
++void update_capinfo(PADAPTER Adapter, u16 updateCap);
++void update_wireless_mode(_adapter *padapter);
++void update_tx_basic_rate(_adapter *padapter, u8 modulation);
++void update_sta_basic_rate(struct sta_info *psta, u8 wireless_mode);
++int rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num);
++
++/* for sta/adhoc mode */
++void update_sta_info(_adapter *padapter, struct sta_info *psta);
++unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz);
++unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz);
++void Update_RA_Entry(_adapter *padapter, struct sta_info *psta);
++void set_sta_rate(_adapter *padapter, struct sta_info *psta);
++
++unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, u8 locally_generated);
++
++unsigned char get_highest_rate_idx(u64 mask);
++unsigned char get_lowest_rate_idx_ex(u64 mask, int start_bit);
++#define get_lowest_rate_idx(mask) get_lowest_rate_idx_ex(mask, 0)
++
++int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode);
++unsigned int is_ap_in_tkip(_adapter *padapter);
++unsigned int is_ap_in_wep(_adapter *padapter);
++unsigned int should_forbid_n_rate(_adapter *padapter);
++
++void parsing_eapol_packet(_adapter *padapter, u8 *key_payload, struct sta_info *psta, u8 trx_type);
++
++bool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap);
++void _rtw_camctl_set_flags(_adapter *adapter, u32 flags);
++void rtw_camctl_set_flags(_adapter *adapter, u32 flags);
++void _rtw_camctl_clr_flags(_adapter *adapter, u32 flags);
++void rtw_camctl_clr_flags(_adapter *adapter, u32 flags);
++bool _rtw_camctl_chk_flags(_adapter *adapter, u32 flags);
++
++struct sec_cam_bmp;
++void dump_sec_cam_map(void *sel, struct sec_cam_bmp *map, u8 max_num);
++void rtw_sec_cam_map_set(struct sec_cam_bmp *map, u8 id);
++void rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map);
++
++bool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id);
++bool rtw_camid_is_gk(_adapter *adapter, u8 cam_id);
++s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk);
++s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, u8 gk, bool ext_sec, bool *used);
++void rtw_camid_free(_adapter *adapter, u8 cam_id);
++u8 rtw_get_sec_camid(_adapter *adapter, u8 max_bk_key_num, u8 *sec_key_id);
++
++struct macid_bmp;
++struct macid_ctl_t;
++bool _rtw_macid_ctl_chk_cap(_adapter *adapter, u8 cap);
++void dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num);
++bool rtw_macid_is_set(struct macid_bmp *map, u8 id);
++void rtw_macid_map_clr(struct macid_bmp *map, u8 id);
++bool rtw_macid_is_used(struct macid_ctl_t *macid_ctl, u8 id);
++bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id);
++u8 rtw_macid_get_iface_bmp(struct macid_ctl_t *macid_ctl, u8 id);
++bool rtw_macid_is_iface_shared(struct macid_ctl_t *macid_ctl, u8 id);
++bool rtw_macid_is_iface_specific(struct macid_ctl_t *macid_ctl, u8 id, _adapter *adapter);
++s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id);
++void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta);
++void rtw_release_macid(_adapter *padapter, struct sta_info *psta);
++u8 rtw_search_max_mac_id(_adapter *padapter);
++u8 rtw_macid_ctl_set_h2c_msr(struct macid_ctl_t *macid_ctl, u8 id, u8 h2c_msr);
++void rtw_macid_ctl_set_bw(struct macid_ctl_t *macid_ctl, u8 id, u8 bw);
++void rtw_macid_ctl_set_vht_en(struct macid_ctl_t *macid_ctl, u8 id, u8 en);
++void rtw_macid_ctl_set_rate_bmp0(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp);
++void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp);
++#ifdef CONFIG_PROTSEL_MACSLEEP
++void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 reg_ctrl, u16 reg_info);
++void rtw_macid_ctl_init_drop_reg(struct macid_ctl_t *macid_ctl, u16 reg_ctrl, u16 reg_info);
++#else
++void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3);
++void rtw_macid_ctl_init_drop_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3);
++#endif
++void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl);
++void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl);
++u8 rtw_iface_bcmc_id_get(_adapter *padapter);
++void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id);
++#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE)
++void rtw_iface_bcmc_sec_cam_map_restore(_adapter *adapter);
++#endif
++bool rtw_bmp_is_set(const u8 *bmp, u8 bmp_len, u8 id);
++void rtw_bmp_set(u8 *bmp, u8 bmp_len, u8 id);
++void rtw_bmp_clear(u8 *bmp, u8 bmp_len, u8 id);
++bool rtw_bmp_not_empty(const u8 *bmp, u8 bmp_len);
++bool rtw_bmp_not_empty_exclude_bit0(const u8 *bmp, u8 bmp_len);
++
++#ifdef CONFIG_AP_MODE
++bool rtw_tim_map_is_set(_adapter *padapter, const u8 *map, u8 id);
++void rtw_tim_map_set(_adapter *padapter, u8 *map, u8 id);
++void rtw_tim_map_clear(_adapter *padapter, u8 *map, u8 id);
++bool rtw_tim_map_anyone_be_set(_adapter *padapter, const u8 *map);
++bool rtw_tim_map_anyone_be_set_exclude_aid0(_adapter *padapter, const u8 *map);
++#endif /* CONFIG_AP_MODE */
++
++u32 report_join_res(_adapter *padapter, int aid_res, u16 status);
++void report_survey_event(_adapter *padapter, union recv_frame *precv_frame);
++void report_surveydone_event(_adapter *padapter, bool acs);
++u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, bool enqueue, u8 locally_generated);
++void report_add_sta_event(_adapter *padapter, unsigned char *MacAddr);
++bool rtw_port_switch_chk(_adapter *adapter);
++void report_wmm_edca_update(_adapter *padapter);
++
++void beacon_timing_control(_adapter *padapter);
++u8 chk_bmc_sleepq_cmd(_adapter *padapter);
++extern u8 set_tx_beacon_cmd(_adapter *padapter, u8 flags);
++unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame);
++void update_mgnt_tx_rate(_adapter *padapter, u8 rate);
++void update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib);
++void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib);
++void update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntframe);
++void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe);
++s32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms);
++s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntframe);
++s32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms);
++
++#ifdef CONFIG_P2P
++int get_reg_classes_full_count(struct p2p_channels *channel_list);
++void issue_probersp_p2p(_adapter *padapter, unsigned char *da);
++void issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8 *pdev_raddr);
++void issue_p2p_GO_request(_adapter *padapter, u8 *raddr);
++void issue_probereq_p2p(_adapter *padapter, u8 *da);
++int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms);
++void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken, u8 success);
++void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr);
++#endif /* CONFIG_P2P */
++void issue_beacon(_adapter *padapter, int timeout_ms);
++void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq);
++void _issue_assocreq(_adapter *padapter, u8 is_assoc);
++void issue_assocreq(_adapter *padapter);
++void issue_reassocreq(_adapter *padapter);
++void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type);
++void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status);
++void issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da);
++s32 issue_probereq_ex(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int try_cnt, int wait_ms);
++int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms);
++int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int try_cnt, int wait_ms);
++int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason);
++int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt, int wait_ms);
++void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset);
++void issue_addba_req(_adapter *adapter, unsigned char *ra, u8 tid);
++void issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size);
++u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size, int try_cnt, int wait_ms);
++void issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator);
++int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator, int try_cnt, int wait_ms);
++void issue_action_BSSCoexistPacket(_adapter *padapter);
++
++#ifdef CONFIG_IEEE80211W
++void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid, u8 key_type);
++int issue_deauth_11w(_adapter *padapter, unsigned char *da, unsigned short reason, u8 key_type);
++#endif /* CONFIG_IEEE80211W */
++int issue_action_SM_PS(_adapter *padapter ,  unsigned char *raddr , u8 NewMimoPsMode);
++int issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 NewMimoPsMode, int try_cnt, int wait_ms);
++
++unsigned int send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid, u8 force);
++unsigned int send_delba_sta_tid_wait_ack(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid, u8 force);
++
++unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr);
++unsigned int send_beacon(_adapter *padapter);
++
++void start_clnt_assoc(_adapter *padapter);
++void start_clnt_auth(_adapter *padapter);
++void start_clnt_join(_adapter *padapter);
++void start_create_ibss(_adapter *padapter);
++
++unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame);
++
++unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame);
++#ifdef CONFIG_RTW_WNM
++unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe);
++#endif
++
++#define RX_AMPDU_ACCEPT_INVALID 0xFF
++#define RX_AMPDU_SIZE_INVALID 0xFF
++
++enum rx_ampdu_reason {
++	RX_AMPDU_DRV_FIXED = 1,
++	RX_AMPDU_BTCOEX = 2, /* not used, because BTCOEX has its own variable management */
++	RX_AMPDU_DRV_SCAN = 3,
++};
++u8 rtw_rx_ampdu_size(_adapter *adapter);
++bool rtw_rx_ampdu_is_accept(_adapter *adapter);
++bool rtw_rx_ampdu_set_size(_adapter *adapter, u8 size, u8 reason);
++bool rtw_rx_ampdu_set_accept(_adapter *adapter, u8 accept, u8 reason);
++u8 rx_ampdu_apply_sta_tid(_adapter *adapter, struct sta_info *sta, u8 tid, u8 accept, u8 size);
++u8 rx_ampdu_size_sta_limit(_adapter *adapter, struct sta_info *sta);
++u8 rx_ampdu_apply_sta(_adapter *adapter, struct sta_info *sta, u8 accept, u8 size);
++u16 rtw_rx_ampdu_apply(_adapter *adapter);
++
++unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame);
++#ifdef CONFIG_IEEE80211W
++unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame);
++#endif /* CONFIG_IEEE80211W */
++unsigned int on_action_rm(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame);
++unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame);
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++unsigned int OnAction_tbtx_token(_adapter *padapter, union recv_frame *precv_frame);
++#endif
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++void rtw_issue_action_token_req(_adapter *padapter, struct sta_info *pstat);
++void rtw_issue_action_token_rel(_adapter *padapter);
++#endif
++
++void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res);
++void mlmeext_sta_del_event_callback(_adapter *padapter);
++void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta);
++
++int rtw_get_rx_chk_limit(_adapter *adapter);
++void rtw_set_rx_chk_limit(_adapter *adapter, int limit);
++void linked_status_chk(_adapter *padapter, u8 from_timer);
++
++#define rtw_get_bcn_cnt(adapter)	(adapter->mlmeextpriv.cur_bcn_cnt)
++#define rtw_get_bcn_dtim_period(adapter)	(adapter->mlmeextpriv.dtim)
++void rtw_collect_bcn_info(_adapter *adapter);
++
++void _linked_info_dump(_adapter *padapter);
++
++void survey_timer_hdl(void *ctx);
++#ifdef CONFIG_RTW_REPEATER_SON
++void rson_timer_hdl(void *ctx);
++#endif
++void link_timer_hdl(void *ctx);
++void addba_timer_hdl(void *ctx);
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++void rtw_tbtx_xmit_timer_hdl(void *ctx);
++void rtw_tbtx_token_dispatch_timer_hdl(void *ctx);
++#endif
++#ifdef CONFIG_IEEE80211W
++void sa_query_timer_hdl(void *ctx);
++#endif /* CONFIG_IEEE80211W */
++#if 0
++void reauth_timer_hdl(_adapter *padapter);
++void reassoc_timer_hdl(_adapter *padapter);
++#endif
++
++#define set_survey_timer(mlmeext, ms) \
++	do { \
++		/*RTW_INFO("%s set_survey_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \
++		_set_timer(&(mlmeext)->survey_timer, (ms)); \
++	} while (0)
++
++#define set_link_timer(mlmeext, ms) \
++	do { \
++		/*RTW_INFO("%s set_link_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \
++		_set_timer(&(mlmeext)->link_timer, (ms)); \
++	} while (0)
++
++bool rtw_is_cck_rate(u8 rate);
++bool rtw_is_ofdm_rate(u8 rate);
++bool rtw_is_basic_rate_cck(u8 rate);
++bool rtw_is_basic_rate_ofdm(u8 rate);
++bool rtw_is_basic_rate_mix(u8 rate);
++
++extern int cckrates_included(unsigned char *rate, int ratelen);
++extern int cckratesonly_included(unsigned char *rate, int ratelen);
++
++extern void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr);
++
++extern void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len);
++extern void correct_TSF(_adapter *padapter, u8 mlme_state);
++#ifdef CONFIG_BCN_RECV_TIME
++void rtw_rx_bcn_time_update(_adapter *adapter, uint bcn_len, u8 data_rate);
++#endif
++extern u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer);
++
++void rtw_process_bar_frame(_adapter *padapter, union recv_frame *precv_frame);
++void rtw_join_done_chk_ch(_adapter *padapter, int join_res);
++
++int rtw_chk_start_clnt_join(_adapter *padapter, u8 *ch, u8 *bw, u8 *offset);
++
++#ifdef RTW_BUSY_DENY_SCAN
++#ifndef BUSY_TRAFFIC_SCAN_DENY_PERIOD
++#ifdef CONFIG_RTW_ANDROID
++#ifdef CONFIG_PLATFORM_ARM_SUN8I
++	#define BUSY_TRAFFIC_SCAN_DENY_PERIOD	8000
++#else
++	#define BUSY_TRAFFIC_SCAN_DENY_PERIOD	12000
++#endif
++#else /* !CONFIG_ANDROID */
++#define BUSY_TRAFFIC_SCAN_DENY_PERIOD	16000
++#endif /* !CONFIG_ANDROID */
++#endif /* !BUSY_TRAFFIC_SCAN_DENY_PERIOD */
++#endif /* RTW_BUSY_DENY_SCAN */
++
++void rtw_leave_opch(_adapter *adapter);
++void rtw_back_opch(_adapter *adapter);
++
++u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf);
++u8 disconnect_hdl(_adapter *padapter, u8 *pbuf);
++u8 createbss_hdl(_adapter *padapter, u8 *pbuf);
++#ifdef CONFIG_AP_MODE
++u8 stop_ap_hdl(_adapter *adapter);
++#endif
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++u8 tx_control_hdl(_adapter *adapter);
++#endif
++u8 setopmode_hdl(_adapter *padapter, u8 *pbuf);
++u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf);
++u8 setauth_hdl(_adapter *padapter, u8 *pbuf);
++u8 setkey_hdl(_adapter *padapter, u8 *pbuf);
++u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf);
++u8 set_assocsta_hdl(_adapter *padapter, u8 *pbuf);
++u8 del_assocsta_hdl(_adapter *padapter, u8 *pbuf);
++u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf);
++u8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf);
++
++void rtw_ap_wep_pk_setting(_adapter *adapter, struct sta_info *psta);
++
++u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf);
++u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf);
++u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf);
++u8 rtw_set_chbw_hdl(_adapter *padapter, u8 *pbuf);
++u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf);
++u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf);
++u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf);	/* Kurt: Handling DFS channel switch announcement ie. */
++u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf);
++u8 run_in_thread_hdl(_adapter *padapter, u8 *pbuf);
++
++int rtw_sae_preprocess(_adapter *adapter, const u8 *buf, u32 len, u8 tx);
++
++#define GEN_MLME_EXT_HANDLER(cmd, callback)	{cmd, callback},
++
++struct rtw_cmd {
++	u8(*cmd_hdl)(_adapter *padapter, u8 *pbuf);
++	void (*callback)(_adapter  *padapter, struct cmd_obj *cmd);
++};
++
++#ifdef _RTW_CMD_C_
++#ifdef CONFIG_RTW_MESH
++extern u8 rtw_mesh_set_plink_state_cmd_hdl(_adapter *adapter, u8 *parmbuf);
++#else
++u8 rtw_mesh_set_plink_state_cmd_hdl(_adapter *adapter, u8 *parmbuf) { return H2C_CMD_FAIL; };
++#endif
++
++struct rtw_cmd wlancmds[] = {
++	GEN_MLME_EXT_HANDLER(join_cmd_hdl, rtw_joinbss_cmd_callback) /*CMD_JOINBSS*/
++	GEN_MLME_EXT_HANDLER(disconnect_hdl, rtw_disassoc_cmd_callback) /*CMD_DISCONNECT*/
++	GEN_MLME_EXT_HANDLER(createbss_hdl, NULL) /*CMD_CREATE_BSS*/
++	GEN_MLME_EXT_HANDLER(setopmode_hdl, NULL) /*CMD_SET_OPMODE*/
++	GEN_MLME_EXT_HANDLER(sitesurvey_cmd_hdl, rtw_survey_cmd_callback) /*CMD_SITE_SURVEY*/
++	GEN_MLME_EXT_HANDLER(setauth_hdl, NULL) /*CMD_SET_AUTH*/
++	GEN_MLME_EXT_HANDLER(setkey_hdl, NULL) /*CMD_SET_KEY*/
++	GEN_MLME_EXT_HANDLER(set_stakey_hdl, rtw_setstaKey_cmdrsp_callback) /*CMD_SET_STAKEY*/
++	GEN_MLME_EXT_HANDLER(add_ba_hdl, NULL) /*CMD_ADD_BAREQ*/
++	GEN_MLME_EXT_HANDLER(rtw_set_chbw_hdl, NULL) /*CMD_SET_CHANNEL*/
++	GEN_MLME_EXT_HANDLER(tx_beacon_hdl, NULL) /*CMD_TX_BEACON*/
++	GEN_MLME_EXT_HANDLER(mlme_evt_hdl, NULL) /*CMD_SET_MLME_EVT*/
++	GEN_MLME_EXT_HANDLER(rtw_drvextra_cmd_hdl, NULL) /*CMD_SET_DRV_EXTRA*/
++	GEN_MLME_EXT_HANDLER(set_chplan_hdl, NULL) /*CMD_SET_CHANPLAN*/
++	GEN_MLME_EXT_HANDLER(led_blink_hdl, NULL) /*CMD_LEDBLINK*/
++	GEN_MLME_EXT_HANDLER(set_csa_hdl, NULL) /*CMD_SET_CHANSWITCH*/
++	GEN_MLME_EXT_HANDLER(tdls_hdl, NULL) /*CMD_TDLS*/
++	GEN_MLME_EXT_HANDLER(chk_bmc_sleepq_hdl, NULL) /*CMD_CHK_BMCSLEEPQ*/
++	GEN_MLME_EXT_HANDLER(run_in_thread_hdl, NULL) /*CMD_RUN_INTHREAD*/
++	GEN_MLME_EXT_HANDLER(add_ba_rsp_hdl, NULL) /*CMD_ADD_BARSP*/
++	GEN_MLME_EXT_HANDLER(rm_post_event_hdl, NULL) /*CMD_RM_POST_EVENT*/
++	GEN_MLME_EXT_HANDLER(rtw_mesh_set_plink_state_cmd_hdl, NULL) /*CMD_SET_MESH_PLINK_STATE*/
++};
++#endif
++
++struct rtw_evt_header {
++	u8 id;
++	u8 seq;
++	u16 len;
++};
++
++enum rtw_event_id {
++	EVT_SURVEY, /*0*/
++	EVT_SURVEY_DONE, /*1*/
++	EVT_JOINBSS, /*2*/
++	EVT_ADD_STA, /*3*/
++	EVT_DEL_STA, /*4*/
++	EVT_WMM_UPDATE, /*5*/
++#ifdef CONFIG_IEEE80211W
++	EVT_TIMEOUT_STA, /*6*/
++#endif /* CONFIG_IEEE80211W */
++#ifdef CONFIG_RTW_80211R
++	EVT_FT_REASSOC, /*7*/
++#endif
++	EVT_ID_MAX
++};
++#ifdef _RTW_MLME_EXT_C_
++static struct rtw_event wlanevents[] = {
++	{sizeof(struct survey_event), &rtw_survey_event_callback}, /*EVT_SURVEY*/
++	{sizeof(struct surveydone_event), &rtw_surveydone_event_callback}, /*EVT_SURVEY_DONE*/
++	{sizeof(struct joinbss_event), &rtw_joinbss_event_callback}, /*EVT_JOINBSS*/
++	{sizeof(struct stassoc_event), &rtw_stassoc_event_callback}, /*EVT_ADD_STA*/
++	{sizeof(struct stadel_event), &rtw_stadel_event_callback}, /*EVT_DEL_STA*/
++	{sizeof(struct wmm_event), &rtw_wmm_event_callback}, /*EVT_WMM_UPDATE*/
++	#ifdef CONFIG_IEEE80211W
++	{sizeof(struct stadel_event), &rtw_sta_timeout_event_callback}, /*EVT_TIMEOUT_STA*/
++	#endif /* CONFIG_IEEE80211W */
++	#ifdef CONFIG_RTW_80211R
++	{sizeof(struct stassoc_event), &rtw_ft_reassoc_event_callback}, /*EVT_FT_REASSOC*/
++	#endif
++};
++#endif/* _RTW_MLME_EXT_C_ */
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mp.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mp.h
+new file mode 100644
+index 000000000..1e30648d4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mp.h
+@@ -0,0 +1,937 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTW_MP_H_
++#define _RTW_MP_H_
++
++#define RTWPRIV_VER_INFO	1
++
++#define MAX_MP_XMITBUF_SZ	2048
++#define NR_MP_XMITFRAME		8
++#define MP_READ_REG_MAX_OFFSET 0x4FFF
++
++struct mp_xmit_frame {
++	_list	list;
++
++	struct pkt_attrib attrib;
++
++	_pkt *pkt;
++
++	int frame_tag;
++
++	_adapter *padapter;
++
++#ifdef CONFIG_USB_HCI
++
++	/* insert urb, irp, and irpcnt info below... */
++	/* max frag_cnt = 8 */
++	u8 *mem_addr;
++	u32 sz[8];
++	u8 bpending[8];
++	sint ac_tag[8];
++	sint last[8];
++	uint irpcnt;
++	uint fragcnt;
++#endif /* CONFIG_USB_HCI */
++
++	uint mem[(MAX_MP_XMITBUF_SZ >> 2)];
++};
++
++struct mp_wiparam {
++	u32 bcompleted;
++	u32 act_type;
++	u32 io_offset;
++	u32 io_value;
++};
++
++typedef void(*wi_act_func)(void *padapter);
++
++struct mp_tx {
++	u8 stop;
++	u32 count, sended;
++	u8 payload;
++	struct pkt_attrib attrib;
++	/* struct tx_desc desc; */
++	/* u8 resvdtx[7]; */
++	u8 desc[TXDESC_SIZE];
++	u8 *pallocated_buf;
++	u8 *buf;
++	u32 buf_size, write_size;
++	_thread_hdl_ PktTxThread;
++};
++
++#define MP_MAX_LINES		1000
++#define MP_MAX_LINES_BYTES	256
++
++
++typedef struct _RT_PMAC_PKT_INFO {
++	u8			MCS;
++	u8			Nss;
++	u8			Nsts;
++	u32			N_sym;
++	u8			SIGA2B3;
++} RT_PMAC_PKT_INFO, *PRT_PMAC_PKT_INFO;
++
++typedef struct _RT_PMAC_TX_INFO {
++	u8			bEnPMacTx:1;		/* 0: Disable PMac 1: Enable PMac */
++	u8			Mode:3;				/* 0: Packet TX 3:Continuous TX */
++	u8			Ntx:4;				/* 0-7 */
++	u8			TX_RATE;			/* MPT_RATE_E */
++	u8			TX_RATE_HEX;
++	u8			TX_SC;
++	u8			bSGI:1;
++	u8			bSPreamble:1;
++	u8			bSTBC:1;
++	u8			bLDPC:1;
++	u8			NDP_sound:1;
++	u8			BandWidth:3;		/* 0: 20 1:40 2:80Mhz */
++	u8			m_STBC;			/* bSTBC + 1 */
++	u16			PacketPeriod;
++	u32		PacketCount;
++	u32		PacketLength;
++	u8			PacketPattern;
++	u16			SFD;
++	u8			SignalField;
++	u8			ServiceField;
++	u16			LENGTH;
++	u8			CRC16[2];
++	u8			LSIG[3];
++	u8			HT_SIG[6];
++	u8			VHT_SIG_A[6];
++	u8			VHT_SIG_B[4];
++	u8			VHT_SIG_B_CRC;
++	u8			VHT_Delimiter[4];
++	u8			MacAddress[6];
++} RT_PMAC_TX_INFO, *PRT_PMAC_TX_INFO;
++
++
++typedef void (*MPT_WORK_ITEM_HANDLER)(void *Adapter);
++typedef struct _MPT_CONTEXT {
++	/* Indicate if we have started Mass Production Test. */
++	BOOLEAN			bMassProdTest;
++
++	/* Indicate if the driver is unloading or unloaded. */
++	BOOLEAN			bMptDrvUnload;
++
++	_sema			MPh2c_Sema;
++	_timer			MPh2c_timeout_timer;
++	/* Event used to sync H2c for BT control */
++
++	BOOLEAN		MptH2cRspEvent;
++	BOOLEAN		MptBtC2hEvent;
++	BOOLEAN		bMPh2c_timeout;
++
++	/* 8190 PCI does not support NDIS_WORK_ITEM. */
++	/* Work Item for Mass Production Test. */
++	/* NDIS_WORK_ITEM	MptWorkItem;
++	*	RT_WORK_ITEM		MptWorkItem; */
++	/* Event used to sync the case unloading driver and MptWorkItem is still in progress.
++	*	NDIS_EVENT		MptWorkItemEvent; */
++	/* To protect the following variables.
++	*	NDIS_SPIN_LOCK		MptWorkItemSpinLock; */
++	/* Indicate a MptWorkItem is scheduled and not yet finished. */
++	BOOLEAN			bMptWorkItemInProgress;
++	/* An instance which implements function and context of MptWorkItem. */
++	MPT_WORK_ITEM_HANDLER	CurrMptAct;
++
++	/* 1=Start, 0=Stop from UI. */
++	u32			MptTestStart;
++	/* _TEST_MODE, defined in MPT_Req2.h */
++	u32			MptTestItem;
++	/* Variable needed in each implementation of CurrMptAct. */
++	u32			MptActType;	/* Type of action performed in CurrMptAct. */
++	/* The Offset of IO operation is depend of MptActType. */
++	u32			MptIoOffset;
++	/* The Value of IO operation is depend of MptActType. */
++	u32			MptIoValue;
++	/* The RfPath of IO operation is depend of MptActType. */
++
++	u32			mpt_rf_path;
++
++
++	WIRELESS_MODE		MptWirelessModeToSw;	/* Wireless mode to switch. */
++	u8			MptChannelToSw;	/* Channel to switch. */
++	u8			MptInitGainToSet;	/* Initial gain to set. */
++	/* u32			bMptAntennaA;		 */ /* TRUE if we want to use antenna A. */
++	u32			MptBandWidth;		/* bandwidth to switch. */
++
++	u32			mpt_rate_index;/* rate index. */
++
++	/* Register value kept for Single Carrier Tx test. */
++	u8			btMpCckTxPower;
++	/* Register value kept for Single Carrier Tx test. */
++	u8			btMpOfdmTxPower;
++	/* For MP Tx Power index */
++	u8			TxPwrLevel[4];	/* rf-A, rf-B*/
++	u32			RegTxPwrLimit;
++	/* Content of RCR Regsiter for Mass Production Test. */
++	u32			MptRCR;
++	/* TRUE if we only receive packets with specific pattern. */
++	BOOLEAN			bMptFilterPattern;
++	/* Rx OK count, statistics used in Mass Production Test. */
++	u32			MptRxOkCnt;
++	/* Rx CRC32 error count, statistics used in Mass Production Test. */
++	u32			MptRxCrcErrCnt;
++
++	BOOLEAN			bCckContTx;	/* TRUE if we are in CCK Continuous Tx test. */
++	BOOLEAN			bOfdmContTx;	/* TRUE if we are in OFDM Continuous Tx test. */
++		/* TRUE if we have start Continuous Tx test. */
++	BOOLEAN			is_start_cont_tx;
++
++	/* TRUE if we are in Single Carrier Tx test. */
++	BOOLEAN			bSingleCarrier;
++	/* TRUE if we are in Carrier Suppression Tx Test. */
++
++	BOOLEAN			is_carrier_suppression;
++
++	/* TRUE if we are in Single Tone Tx test. */
++
++	BOOLEAN			is_single_tone;
++
++
++	/* ACK counter asked by K.Y.. */
++	BOOLEAN			bMptEnableAckCounter;
++	u32			MptAckCounter;
++
++	/* SD3 Willis For 8192S to save 1T/2T RF table for ACUT	Only fro ACUT delete later ~~~! */
++	/* s8		BufOfLines[2][MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; */
++	/* s8			BufOfLines[2][MP_MAX_LINES][MP_MAX_LINES_BYTES]; */
++	/* s32			RfReadLine[2]; */
++
++	u8		APK_bound[2];	/* for APK	path A/path B */
++	BOOLEAN		bMptIndexEven;
++
++	u8		backup0xc50;
++	u8		backup0xc58;
++	u8		backup0xc30;
++	u8		backup0x52_RF_A;
++	u8		backup0x52_RF_B;
++
++	u32			backup0x58_RF_A;
++	u32			backup0x58_RF_B;
++
++	u8			h2cReqNum;
++	u8			c2hBuf[32];
++
++	u8          btInBuf[100];
++	u32			mptOutLen;
++	u8          mptOutBuf[100];
++	RT_PMAC_TX_INFO	PMacTxInfo;
++	RT_PMAC_PKT_INFO	PMacPktInfo;
++	u8 HWTxmode;
++
++	BOOLEAN			bldpc;
++	BOOLEAN			bstbc;
++} MPT_CONTEXT, *PMPT_CONTEXT;
++/* #endif */
++
++
++/* #define RTPRIV_IOCTL_MP					( SIOCIWFIRSTPRIV + 0x17) */
++enum {
++	WRITE_REG = 1,
++	READ_REG,
++	WRITE_RF,
++	READ_RF,
++	MP_START,
++	MP_STOP,
++	MP_RATE,
++	MP_CHANNEL,
++	MP_CHL_OFFSET,
++	MP_BANDWIDTH,
++	MP_TXPOWER,
++	MP_ANT_TX,
++	MP_ANT_RX,
++	MP_CTX,
++	MP_QUERY,
++	MP_ARX,
++	MP_PSD,
++	MP_PWRTRK,
++	MP_THER,
++	MP_IOCTL,
++	EFUSE_GET,
++	EFUSE_SET,
++	MP_RESET_STATS,
++	MP_DUMP,
++	MP_PHYPARA,
++	MP_SetRFPathSwh,
++	MP_QueryDrvStats,
++	CTA_TEST,
++	MP_DISABLE_BT_COEXIST,
++	MP_PwrCtlDM,
++	MP_GETVER,
++	MP_MON,
++	EFUSE_BT_MASK,
++	EFUSE_MASK,
++	EFUSE_FILE,
++	EFUSE_FILE_STORE,
++	MP_TX,
++	MP_RX,
++	MP_IQK,
++	MP_LCK,
++	MP_HW_TX_MODE,
++	MP_GET_TXPOWER_INX,
++	MP_CUSTOMER_STR,
++	MP_PWRLMT,
++	MP_PWRBYRATE,
++	BT_EFUSE_FILE,
++	MP_SetBT,
++	MP_SWRFPath,
++	MP_LINK,
++	MP_DPK_TRK,
++	MP_DPK,
++	MP_GET_TSSIDE,
++	MP_SET_TSSIDE,
++	MP_NULL,
++#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
++	VENDOR_IE_SET ,
++	VENDOR_IE_GET ,
++#endif
++#ifdef CONFIG_WOWLAN
++	MP_WOW_ENABLE,
++	MP_WOW_SET_PATTERN,
++#endif
++#ifdef CONFIG_AP_WOWLAN
++	MP_AP_WOW_ENABLE,
++#endif
++	MP_SD_IREAD,
++	MP_SD_IWRITE,
++};
++
++struct mp_priv {
++	_adapter *papdater;
++
++	/* Testing Flag */
++	u32 mode;/* 0 for normal type packet, 1 for loopback packet (16bytes TXCMD) */
++
++	u32 prev_fw_state;
++
++	/* OID cmd handler */
++	struct mp_wiparam workparam;
++	/*	u8 act_in_progress; */
++
++	/* Tx Section */
++	u8 TID;
++	u32 tx_pktcount;
++	u32 pktInterval;
++	u32 pktLength;
++	struct mp_tx tx;
++
++	/* Rx Section */
++	u32 rx_bssidpktcount;
++	u32 rx_pktcount;
++	u32 rx_pktcount_filter_out;
++	u32 rx_crcerrpktcount;
++	u32 rx_pktloss;
++	BOOLEAN  rx_bindicatePkt;
++	struct recv_stat rxstat;
++	BOOLEAN brx_filter_beacon;
++
++	/* RF/BB relative */
++	u8 channel;
++	u8 bandwidth;
++	u8 prime_channel_offset;
++	u8 txpoweridx;
++	u8 rateidx;
++	u32 preamble;
++	/*	u8 modem; */
++	u32 CrystalCap;
++	/*	u32 curr_crystalcap; */
++
++	u16 antenna_tx;
++	u16 antenna_rx;
++	/*	u8 curr_rfpath; */
++
++	u8 check_mp_pkt;
++
++	u8 bSetTxPower;
++	/*	uint ForcedDataRate; */
++	u8 mp_dm;
++	u8 mac_filter[ETH_ALEN];
++	u8 bmac_filter;
++
++	/* RF PATH Setting for WLG WLA BTG BT */
++	u8 rf_path_cfg;
++
++	struct wlan_network mp_network;
++	NDIS_802_11_MAC_ADDRESS network_macaddr;
++
++	u8 *pallocated_mp_xmitframe_buf;
++	u8 *pmp_xmtframe_buf;
++	_queue free_mp_xmitqueue;
++	u32 free_mp_xmitframe_cnt;
++	BOOLEAN bSetRxBssid;
++	BOOLEAN bTxBufCkFail;
++	BOOLEAN bRTWSmbCfg;
++	BOOLEAN bloopback;
++	BOOLEAN bloadefusemap;
++	BOOLEAN bloadBTefusemap;
++	BOOLEAN bprocess_mp_mode;
++
++	MPT_CONTEXT	mpt_ctx;
++
++	u8		*TXradomBuffer;
++	u8		CureFuseBTCoex;
++    u8		mplink_buf[2048];
++    u32		mplink_rx_len;
++	BOOLEAN mplink_brx;
++	BOOLEAN mplink_btx;
++
++	bool tssitrk_on;
++};
++
++typedef struct _IOCMD_STRUCT_ {
++	u8	cmdclass;
++	u16	value;
++	u8	index;
++} IOCMD_STRUCT;
++
++struct rf_reg_param {
++	u32 path;
++	u32 offset;
++	u32 value;
++};
++
++struct bb_reg_param {
++	u32 offset;
++	u32 value;
++};
++
++typedef struct _MP_FIRMWARE {
++	FIRMWARE_SOURCE eFWSource;
++#ifdef CONFIG_EMBEDDED_FWIMG
++	u8		*szFwBuffer;
++#else
++	u8			szFwBuffer[0x8000];
++#endif
++	u32		ulFwLength;
++} RT_MP_FIRMWARE, *PRT_MP_FIRMWARE;
++
++
++
++
++/* *********************************************************************** */
++
++#define LOWER	_TRUE
++#define RAISE	_FALSE
++
++/* Hardware Registers */
++#if 0
++#if 0
++#define IOCMD_CTRL_REG			0x102502C0
++#define IOCMD_DATA_REG			0x102502C4
++#else
++#define IOCMD_CTRL_REG			0x10250370
++#define IOCMD_DATA_REG			0x10250374
++#endif
++
++#define IOCMD_GET_THERMAL_METER		0xFD000028
++
++#define IOCMD_CLASS_BB_RF		0xF0
++#define IOCMD_BB_READ_IDX		0x00
++#define IOCMD_BB_WRITE_IDX		0x01
++#define IOCMD_RF_READ_IDX		0x02
++#define IOCMD_RF_WRIT_IDX		0x03
++#endif
++#define BB_REG_BASE_ADDR		0x800
++
++/* MP variables */
++#if 0
++#define _2MAC_MODE_	0
++#define _LOOPBOOK_MODE_	1
++#endif
++typedef enum _MP_MODE_ {
++	MP_OFF,
++	MP_ON,
++	MP_ERR,
++	MP_CONTINUOUS_TX,
++	MP_SINGLE_CARRIER_TX,
++	MP_CARRIER_SUPPRISSION_TX,
++	MP_SINGLE_TONE_TX,
++	MP_PACKET_TX,
++	MP_PACKET_RX
++} MP_MODE;
++
++typedef enum _TEST_MODE {
++	TEST_NONE                 ,
++	PACKETS_TX                ,
++	PACKETS_RX                ,
++	CONTINUOUS_TX             ,
++	OFDM_Single_Tone_TX       ,
++	CCK_Carrier_Suppression_TX
++} TEST_MODE;
++
++
++typedef enum _MPT_BANDWIDTH {
++	MPT_BW_20MHZ = 0,
++	MPT_BW_40MHZ_DUPLICATE = 1,
++	MPT_BW_40MHZ_ABOVE = 2,
++	MPT_BW_40MHZ_BELOW = 3,
++	MPT_BW_40MHZ = 4,
++	MPT_BW_80MHZ = 5,
++	MPT_BW_80MHZ_20_ABOVE = 6,
++	MPT_BW_80MHZ_20_BELOW = 7,
++	MPT_BW_80MHZ_20_BOTTOM = 8,
++	MPT_BW_80MHZ_20_TOP = 9,
++	MPT_BW_80MHZ_40_ABOVE = 10,
++	MPT_BW_80MHZ_40_BELOW = 11,
++} MPT_BANDWIDTHE, *PMPT_BANDWIDTH;
++
++#define MAX_RF_PATH_NUMS	RF_PATH_MAX
++
++
++extern u8 mpdatarate[NumRates];
++
++/* MP set force data rate base on the definition. */
++typedef enum _MPT_RATE_INDEX {
++	/* CCK rate. */
++	MPT_RATE_1M = 1 ,	/* 0 */
++	MPT_RATE_2M,
++	MPT_RATE_55M,
++	MPT_RATE_11M,	/* 3 */
++
++	/* OFDM rate. */
++	MPT_RATE_6M,	/* 4 */
++	MPT_RATE_9M,
++	MPT_RATE_12M,
++	MPT_RATE_18M,
++	MPT_RATE_24M,
++	MPT_RATE_36M,
++	MPT_RATE_48M,
++	MPT_RATE_54M,	/* 11 */
++
++	/* HT rate. */
++	MPT_RATE_MCS0,	/* 12 */
++	MPT_RATE_MCS1,
++	MPT_RATE_MCS2,
++	MPT_RATE_MCS3,
++	MPT_RATE_MCS4,
++	MPT_RATE_MCS5,
++	MPT_RATE_MCS6,
++	MPT_RATE_MCS7,	/* 19 */
++	MPT_RATE_MCS8,
++	MPT_RATE_MCS9,
++	MPT_RATE_MCS10,
++	MPT_RATE_MCS11,
++	MPT_RATE_MCS12,
++	MPT_RATE_MCS13,
++	MPT_RATE_MCS14,
++	MPT_RATE_MCS15,	/* 27 */
++	MPT_RATE_MCS16,
++	MPT_RATE_MCS17, /*  #29 */
++	MPT_RATE_MCS18,
++	MPT_RATE_MCS19,
++	MPT_RATE_MCS20,
++	MPT_RATE_MCS21,
++	MPT_RATE_MCS22, /*  #34 */
++	MPT_RATE_MCS23,
++	MPT_RATE_MCS24,
++	MPT_RATE_MCS25,
++	MPT_RATE_MCS26,
++	MPT_RATE_MCS27, /*  #39 */
++	MPT_RATE_MCS28, /*  #40 */
++	MPT_RATE_MCS29, /*  #41 */
++	MPT_RATE_MCS30, /*  #42 */
++	MPT_RATE_MCS31, /*  #43 */
++	/* VHT rate. Total: 20*/
++	MPT_RATE_VHT1SS_MCS0 = 100,/*  #44*/
++	MPT_RATE_VHT1SS_MCS1, /*  # */
++	MPT_RATE_VHT1SS_MCS2,
++	MPT_RATE_VHT1SS_MCS3,
++	MPT_RATE_VHT1SS_MCS4,
++	MPT_RATE_VHT1SS_MCS5,
++	MPT_RATE_VHT1SS_MCS6, /*  # */
++	MPT_RATE_VHT1SS_MCS7,
++	MPT_RATE_VHT1SS_MCS8,
++	MPT_RATE_VHT1SS_MCS9, /* #53 */
++	MPT_RATE_VHT2SS_MCS0, /* #54 */
++	MPT_RATE_VHT2SS_MCS1,
++	MPT_RATE_VHT2SS_MCS2,
++	MPT_RATE_VHT2SS_MCS3,
++	MPT_RATE_VHT2SS_MCS4,
++	MPT_RATE_VHT2SS_MCS5,
++	MPT_RATE_VHT2SS_MCS6,
++	MPT_RATE_VHT2SS_MCS7,
++	MPT_RATE_VHT2SS_MCS8,
++	MPT_RATE_VHT2SS_MCS9, /* #63 */
++	MPT_RATE_VHT3SS_MCS0,
++	MPT_RATE_VHT3SS_MCS1,
++	MPT_RATE_VHT3SS_MCS2,
++	MPT_RATE_VHT3SS_MCS3,
++	MPT_RATE_VHT3SS_MCS4,
++	MPT_RATE_VHT3SS_MCS5,
++	MPT_RATE_VHT3SS_MCS6, /*  #126 */
++	MPT_RATE_VHT3SS_MCS7,
++	MPT_RATE_VHT3SS_MCS8,
++	MPT_RATE_VHT3SS_MCS9,
++	MPT_RATE_VHT4SS_MCS0,
++	MPT_RATE_VHT4SS_MCS1, /*  #131 */
++	MPT_RATE_VHT4SS_MCS2,
++	MPT_RATE_VHT4SS_MCS3,
++	MPT_RATE_VHT4SS_MCS4,
++	MPT_RATE_VHT4SS_MCS5,
++	MPT_RATE_VHT4SS_MCS6, /*  #136 */
++	MPT_RATE_VHT4SS_MCS7,
++	MPT_RATE_VHT4SS_MCS8,
++	MPT_RATE_VHT4SS_MCS9,
++	MPT_RATE_LAST
++} MPT_RATE_E, *PMPT_RATE_E;
++
++#define MAX_TX_PWR_INDEX_N_MODE 64	/* 0x3F */
++
++#define MPT_IS_CCK_RATE(_value)		(MPT_RATE_1M <= _value && _value <= MPT_RATE_11M)
++#define MPT_IS_OFDM_RATE(_value)	(MPT_RATE_6M <= _value && _value <= MPT_RATE_54M)
++#define MPT_IS_HT_RATE(_value)		(MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS31)
++#define MPT_IS_HT_1S_RATE(_value)	(MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS7)
++#define MPT_IS_HT_2S_RATE(_value)	(MPT_RATE_MCS8 <= _value && _value <= MPT_RATE_MCS15)
++#define MPT_IS_HT_3S_RATE(_value)	(MPT_RATE_MCS16 <= _value && _value <= MPT_RATE_MCS23)
++#define MPT_IS_HT_4S_RATE(_value)	(MPT_RATE_MCS24 <= _value && _value <= MPT_RATE_MCS31)
++
++#define MPT_IS_VHT_RATE(_value)		(MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9)
++#define MPT_IS_VHT_1S_RATE(_value)	(MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT1SS_MCS9)
++#define MPT_IS_VHT_2S_RATE(_value)	(MPT_RATE_VHT2SS_MCS0 <= _value && _value <= MPT_RATE_VHT2SS_MCS9)
++#define MPT_IS_VHT_3S_RATE(_value)	(MPT_RATE_VHT3SS_MCS0 <= _value && _value <= MPT_RATE_VHT3SS_MCS9)
++#define MPT_IS_VHT_4S_RATE(_value)	(MPT_RATE_VHT4SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9)
++
++#define MPT_IS_2SS_RATE(_rate) ((MPT_RATE_MCS8 <= _rate && _rate <= MPT_RATE_MCS15) || \
++	(MPT_RATE_VHT2SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT2SS_MCS9))
++#define MPT_IS_3SS_RATE(_rate) ((MPT_RATE_MCS16 <= _rate && _rate <= MPT_RATE_MCS23) || \
++	(MPT_RATE_VHT3SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT3SS_MCS9))
++#define MPT_IS_4SS_RATE(_rate) ((MPT_RATE_MCS24 <= _rate && _rate <= MPT_RATE_MCS31) || \
++	(MPT_RATE_VHT4SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT4SS_MCS9))
++
++typedef enum _POWER_MODE_ {
++	POWER_LOW = 0,
++	POWER_NORMAL
++} POWER_MODE;
++
++/* The following enumeration is used to define the value of Reg0xD00[30:28] or JaguarReg0x914[18:16]. */
++typedef enum _OFDM_TX_MODE {
++	OFDM_ALL_OFF		= 0,
++	OFDM_ContinuousTx	= 1,
++	OFDM_SingleCarrier	= 2,
++	OFDM_SingleTone	= 4,
++} OFDM_TX_MODE;
++
++
++#define RX_PKT_BROADCAST	1
++#define RX_PKT_DEST_ADDR	2
++#define RX_PKT_PHY_MATCH	3
++
++typedef enum _ENCRY_CTRL_STATE_ {
++	HW_CONTROL,		/* hw encryption& decryption */
++	SW_CONTROL,		/* sw encryption& decryption */
++	HW_ENCRY_SW_DECRY,	/* hw encryption & sw decryption */
++	SW_ENCRY_HW_DECRY	/* sw encryption & hw decryption */
++} ENCRY_CTRL_STATE;
++
++typedef enum	_MPT_TXPWR_DEF {
++	MPT_CCK,
++	MPT_OFDM, /* L and HT OFDM */
++	MPT_OFDM_AND_HT,
++	MPT_HT,
++	MPT_VHT
++} MPT_TXPWR_DEF;
++
++
++#define IS_MPT_HT_RATE(_rate)			(_rate >= MPT_RATE_MCS0 && _rate <= MPT_RATE_MCS31)
++#define IS_MPT_VHT_RATE(_rate)			(_rate >= MPT_RATE_VHT1SS_MCS0 && _rate <= MPT_RATE_VHT4SS_MCS9)
++#define IS_MPT_CCK_RATE(_rate)			(_rate >= MPT_RATE_1M && _rate <= MPT_RATE_11M)
++#define IS_MPT_OFDM_RATE(_rate)			(_rate >= MPT_RATE_6M && _rate <= MPT_RATE_54M)
++
++typedef enum _mp_tx_pkt_payload{
++	MP_TX_Payload_00 = 0,
++	MP_TX_Payload_a5,
++	MP_TX_Payload_5a,
++	MP_TX_Payload_ff,
++	MP_TX_Payload_prbs9,
++	MP_TX_Payload_default_random
++} mp_tx_pkt_payload;
++
++/*************************************************************************/
++#if 0
++extern struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv);
++extern int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe);
++#endif
++
++extern s32 init_mp_priv(PADAPTER padapter);
++extern void free_mp_priv(struct mp_priv *pmp_priv);
++extern s32 MPT_InitializeAdapter(PADAPTER padapter, u8 Channel);
++extern void MPT_DeInitAdapter(PADAPTER padapter);
++extern s32 mp_start_test(PADAPTER padapter);
++extern void mp_stop_test(PADAPTER padapter);
++
++extern u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask);
++extern void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val);
++
++extern u32 read_macreg(_adapter *padapter, u32 addr, u32 sz);
++extern void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz);
++extern u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask);
++extern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val);
++extern u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr);
++extern void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val);
++#ifdef CONFIG_ANTENNA_DIVERSITY
++u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain);
++#endif
++void	SetChannel(PADAPTER pAdapter);
++void	SetBandwidth(PADAPTER pAdapter);
++int	SetTxPower(PADAPTER pAdapter);
++void	SetAntenna(PADAPTER pAdapter);
++void	SetDataRate(PADAPTER pAdapter);
++void	SetAntenna(PADAPTER pAdapter);
++s32	SetThermalMeter(PADAPTER pAdapter, u8 target_ther);
++void	GetThermalMeter(PADAPTER pAdapter, u8 rfpath ,u8 *value);
++void	SetContinuousTx(PADAPTER pAdapter, u8 bStart);
++void	SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart);
++void	SetSingleToneTx(PADAPTER pAdapter, u8 bStart);
++void	SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart);
++void	PhySetTxPowerLevel(PADAPTER pAdapter);
++void	fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc);
++void	SetPacketTx(PADAPTER padapter);
++void	SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB);
++void	ResetPhyRxPktCount(PADAPTER pAdapter);
++u32	GetPhyRxPktReceived(PADAPTER pAdapter);
++u32	GetPhyRxPktCRC32Error(PADAPTER pAdapter);
++s32	SetPowerTracking(PADAPTER padapter, u8 enable);
++void	GetPowerTracking(PADAPTER padapter, u8 *enable);
++u32	mp_query_psd(PADAPTER pAdapter, u8 *data);
++void	rtw_mp_trigger_iqk(PADAPTER padapter);
++void	rtw_mp_trigger_lck(PADAPTER padapter);
++void	rtw_mp_trigger_dpk(PADAPTER padapter);
++u8 rtw_mp_mode_check(PADAPTER padapter);
++bool rtw_is_mp_tssitrk_on(_adapter *adapter);
++
++void hal_mpt_SwitchRfSetting(PADAPTER pAdapter);
++s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable);
++void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable);
++void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14);
++void hal_mpt_SetChannel(PADAPTER pAdapter);
++void hal_mpt_SetBandwidth(PADAPTER pAdapter);
++void hal_mpt_SetTxPower(PADAPTER pAdapter);
++void hal_mpt_SetDataRate(PADAPTER pAdapter);
++void hal_mpt_SetAntenna(PADAPTER pAdapter);
++s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther);
++void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter);
++u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path);
++void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value);
++void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart);
++void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart);
++void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart);
++void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart);
++u8 mpt_ProSetPMacTx(PADAPTER	Adapter);
++void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain);
++void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate);
++u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter);
++u32 mpt_ProQueryCalTxPower(PADAPTER	pAdapter, u8 RfPath);
++void MPT_PwrCtlDM(PADAPTER padapter, u32 trk_type);
++u8 mpt_to_mgnt_rate(u32	MptRateIdx);
++u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr);
++u32 mp_join(PADAPTER padapter, u8 mode);
++u32 hal_mpt_query_phytxok(PADAPTER	pAdapter);
++u32 mpt_get_tx_power_finalabs_val(PADAPTER	padapter, u8 rf_path);
++void mpt_trigger_tssi_tracking(PADAPTER pAdapter, u8 rf_path);
++
++
++void
++PMAC_Get_Pkt_Param(
++	PRT_PMAC_TX_INFO	pPMacTxInfo,
++	PRT_PMAC_PKT_INFO	pPMacPktInfo
++);
++void
++CCK_generator(
++	PRT_PMAC_TX_INFO	pPMacTxInfo,
++	PRT_PMAC_PKT_INFO	pPMacPktInfo
++);
++void
++PMAC_Nsym_generator(
++	PRT_PMAC_TX_INFO	pPMacTxInfo,
++	PRT_PMAC_PKT_INFO	pPMacPktInfo
++);
++void
++L_SIG_generator(
++	u32	N_SYM,		/* Max: 750*/
++	PRT_PMAC_TX_INFO	pPMacTxInfo,
++	PRT_PMAC_PKT_INFO	pPMacPktInfo
++);
++
++void HT_SIG_generator(
++	PRT_PMAC_TX_INFO	pPMacTxInfo,
++	PRT_PMAC_PKT_INFO	pPMacPktInfo);
++
++void VHT_SIG_A_generator(
++	PRT_PMAC_TX_INFO	pPMacTxInfo,
++	PRT_PMAC_PKT_INFO	pPMacPktInfo);
++
++void VHT_SIG_B_generator(
++	PRT_PMAC_TX_INFO	pPMacTxInfo);
++
++void VHT_Delimiter_generator(
++	PRT_PMAC_TX_INFO	pPMacTxInfo);
++
++
++int rtw_mp_write_reg(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_read_reg(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_write_rf(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_read_rf(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_start(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_stop(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_rate(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_channel(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_ch_offset(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_bandwidth(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_txpower_index(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_txpower(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_txpower(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_ant_tx(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_ant_rx(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_set_ctx_destAddr(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_ctx(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_disable_bt_coexist(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra);
++int rtw_mp_disable_bt_coexist(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra);
++int rtw_mp_arx(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_trx_query(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_pwrtrk(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_psd(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_thermal(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_reset_stats(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_dump(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_phypara(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_SetRFPath(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_switch_rf_path(struct net_device *dev,
++			struct iw_request_info *info,
++			struct iw_point *wrqu, char *extra);
++int rtw_mp_link(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_QueryDrv(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra);
++int rtw_mp_PwrCtlDM(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_getver(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra);
++int rtw_mp_mon(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra);
++int rtw_mp_pwrlmt(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra);
++int rtw_mp_pwrbyrate(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra);
++int rtw_mp_dpk_track(struct net_device *dev,
++			struct iw_request_info *info,
++			union iwreq_data *wrqu, char *extra);
++int rtw_mp_dpk(struct net_device *dev,
++			struct iw_request_info *info,
++			union iwreq_data *wrqu, char *extra);
++int rtw_efuse_mask_file(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra);
++int rtw_bt_efuse_mask_file(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra);
++int rtw_efuse_file_map(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra);
++int rtw_efuse_file_map_store(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra);
++int rtw_bt_efuse_file_map(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra);
++int rtw_mp_SetBT(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra);
++int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra);
++int rtw_mp_tx(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra);
++int rtw_mp_rx(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra);
++int rtw_mp_hwtx(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra);
++u8 HwRateToMPTRate(u8 rate);
++int rtw_mp_iqk(struct net_device *dev,
++		 struct iw_request_info *info,
++		 struct iw_point *wrqu, char *extra);
++int rtw_mp_lck(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_get_tsside(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++int rtw_mp_set_tsside(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra);
++#endif /* _RTW_MP_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mp_phy_regdef.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mp_phy_regdef.h
+new file mode 100644
+index 000000000..be627800e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_mp_phy_regdef.h
+@@ -0,0 +1,1094 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*****************************************************************************
++ *
++ * Module:	__RTW_MP_PHY_REGDEF_H_
++ *
++ *
++ * Note:	1. Define PMAC/BB register map
++ *			2. Define RF register map
++ *			3. PMAC/BB register bit mask.
++ *			4. RF reg bit mask.
++ *			5. Other BB/RF relative definition.
++ *
++ *
++ * Export:	Constants, macro, functions(API), global variables(None).
++ *
++ * Abbrev:
++ *
++ * History:
++ *	Data			Who		Remark
++ *	08/07/2007	MHC		1. Porting from 9x series PHYCFG.h.
++ *						2. Reorganize code architecture.
++ *	09/25/2008	MH		1. Add RL6052 register definition
++ *
++ *****************************************************************************/
++#ifndef __RTW_MP_PHY_REGDEF_H_
++#define __RTW_MP_PHY_REGDEF_H_
++
++
++/*--------------------------Define Parameters-------------------------------*/
++
++/* ************************************************************
++ * 8192S Regsiter offset definition
++ * ************************************************************ */
++
++/*
++ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
++ * 3. RF register 0x00-2E
++ * 4. Bit Mask for BB/RF register
++ * 5. Other defintion for BB/RF R/W
++ *   */
++
++
++/*
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 1. Page1(0x100)
++ *   */
++#define		rPMAC_Reset					0x100
++#define		rPMAC_TxStart					0x104
++#define		rPMAC_TxLegacySIG				0x108
++#define		rPMAC_TxHTSIG1				0x10c
++#define		rPMAC_TxHTSIG2				0x110
++#define		rPMAC_PHYDebug				0x114
++#define		rPMAC_TxPacketNum				0x118
++#define		rPMAC_TxIdle					0x11c
++#define		rPMAC_TxMACHeader0			0x120
++#define		rPMAC_TxMACHeader1			0x124
++#define		rPMAC_TxMACHeader2			0x128
++#define		rPMAC_TxMACHeader3			0x12c
++#define		rPMAC_TxMACHeader4			0x130
++#define		rPMAC_TxMACHeader5			0x134
++#define		rPMAC_TxDataType				0x138
++#define		rPMAC_TxRandomSeed			0x13c
++#define		rPMAC_CCKPLCPPreamble			0x140
++#define		rPMAC_CCKPLCPHeader			0x144
++#define		rPMAC_CCKCRC16				0x148
++#define		rPMAC_OFDMRxCRC32OK			0x170
++#define		rPMAC_OFDMRxCRC32Er			0x174
++#define		rPMAC_OFDMRxParityEr			0x178
++#define		rPMAC_OFDMRxCRC8Er			0x17c
++#define		rPMAC_CCKCRxRC16Er			0x180
++#define		rPMAC_CCKCRxRC32Er			0x184
++#define		rPMAC_CCKCRxRC32OK			0x188
++#define		rPMAC_TxStatus					0x18c
++
++/*
++ * 2. Page2(0x200)
++ *
++ * The following two definition are only used for USB interface.
++ * #define		RF_BB_CMD_ADDR				0x02c0 */	/* RF/BB read/write command address.
++ * #define		RF_BB_CMD_DATA				0x02c4 */	/* RF/BB read/write command data. */
++
++/*
++ * 3. Page8(0x800)
++ *   */
++#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
++
++#define		rFPGA0_TxInfo				0x804	/* Status report?? */
++#define		rFPGA0_PSDFunction			0x808
++
++#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
++
++#define		rFPGA0_RFTiming1			0x810	/* Useless now */
++#define		rFPGA0_RFTiming2			0x814
++/* #define rFPGA0_XC_RFTiming		0x818 */
++/* #define rFPGA0_XD_RFTiming		0x81c */
++
++#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
++#define		rFPGA0_XA_HSSIParameter2		0x824
++#define		rFPGA0_XB_HSSIParameter1		0x828
++#define		rFPGA0_XB_HSSIParameter2		0x82c
++#define		rFPGA0_XC_HSSIParameter1		0x830
++#define		rFPGA0_XC_HSSIParameter2		0x834
++#define		rFPGA0_XD_HSSIParameter1		0x838
++#define		rFPGA0_XD_HSSIParameter2		0x83c
++#define		rFPGA0_XA_LSSIParameter		0x840
++#define		rFPGA0_XB_LSSIParameter		0x844
++#define		rFPGA0_XC_LSSIParameter		0x848
++#define		rFPGA0_XD_LSSIParameter		0x84c
++
++#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
++#define		rFPGA0_RFSleepUpParameter		0x854
++
++#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
++#define		rFPGA0_XCD_SwitchControl		0x85c
++
++#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
++#define		rFPGA0_XB_RFInterfaceOE		0x864
++#define		rFPGA0_XC_RFInterfaceOE		0x868
++#define		rFPGA0_XD_RFInterfaceOE		0x86c
++
++#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
++#define		rFPGA0_XCD_RFInterfaceSW		0x874
++
++#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
++#define		rFPGA0_XCD_RFParameter		0x87c
++
++#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
++#define		rFPGA0_AnalogParameter2		0x884
++#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
++#define		rFPGA0_AnalogParameter4		0x88c
++
++#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
++#define		rFPGA0_XB_LSSIReadBack		0x8a4
++#define		rFPGA0_XC_LSSIReadBack		0x8a8
++#define		rFPGA0_XD_LSSIReadBack		0x8ac
++
++#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
++#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
++#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
++
++/*
++ * 4. Page9(0x900)
++ *   */
++#define		rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
++
++#define		rFPGA1_TxBlock				0x904	/* Useless now */
++#define		rFPGA1_DebugSelect			0x908	/* Useless now */
++#define		rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
++#define	rS0S1_PathSwitch			0x948
++
++/*
++ * 5. PageA(0xA00)
++ *
++ * Set Control channel to upper or lower. These settings are required only for 40MHz */
++#define		rCCK0_System				0xa00
++
++#define		rCCK0_AFESetting			0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
++#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
++
++#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
++#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
++
++#define		rCCK0_RxHP					0xa14
++
++#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
++#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
++
++#define		rCCK0_TxFilter1				0xa20
++#define		rCCK0_TxFilter2				0xa24
++#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
++#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
++#define		rCCK0_TRSSIReport		0xa50
++#define		rCCK0_RxReport            		0xa54  /* 0xa57 */
++#define		rCCK0_FACounterLower      	0xa5c  /* 0xa5b */
++#define		rCCK0_FACounterUpper      	0xa58  /* 0xa5c */
++
++/*
++ * 6. PageC(0xC00)
++ *   */
++#define		rOFDM0_LSTF				0xc00
++
++#define		rOFDM0_TRxPathEnable		0xc04
++#define		rOFDM0_TRMuxPar			0xc08
++#define		rOFDM0_TRSWIsolation		0xc0c
++
++#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
++#define		rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
++#define		rOFDM0_XBRxAFE		0xc18
++#define		rOFDM0_XBRxIQImbalance	0xc1c
++#define		rOFDM0_XCRxAFE		0xc20
++#define		rOFDM0_XCRxIQImbalance	0xc24
++#define		rOFDM0_XDRxAFE		0xc28
++#define		rOFDM0_XDRxIQImbalance	0xc2c
++
++#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
++#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
++#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
++#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
++
++#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
++#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
++#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
++#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
++
++#define		rOFDM0_XAAGCCore1			0xc50	/* DIG  */
++#define		rOFDM0_XAAGCCore2			0xc54
++#define		rOFDM0_XBAGCCore1			0xc58
++#define		rOFDM0_XBAGCCore2			0xc5c
++#define		rOFDM0_XCAGCCore1			0xc60
++#define		rOFDM0_XCAGCCore2			0xc64
++#define		rOFDM0_XDAGCCore1			0xc68
++#define		rOFDM0_XDAGCCore2			0xc6c
++
++#define		rOFDM0_AGCParameter1			0xc70
++#define		rOFDM0_AGCParameter2			0xc74
++#define		rOFDM0_AGCRSSITable			0xc78
++#define		rOFDM0_HTSTFAGC				0xc7c
++
++#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
++#define		rOFDM0_XATxAFE				0xc84
++#define		rOFDM0_XBTxIQImbalance		0xc88
++#define		rOFDM0_XBTxAFE				0xc8c
++#define		rOFDM0_XCTxIQImbalance		0xc90
++#define		rOFDM0_XCTxAFE			0xc94
++#define		rOFDM0_XDTxIQImbalance		0xc98
++#define		rOFDM0_XDTxAFE				0xc9c
++#define		rOFDM0_RxIQExtAnta			0xca0
++
++#define		rOFDM0_RxHPParameter			0xce0
++#define		rOFDM0_TxPseudoNoiseWgt		0xce4
++#define		rOFDM0_FrameSync				0xcf0
++#define		rOFDM0_DFSReport				0xcf4
++#define		rOFDM0_TxCoeff1				0xca4
++#define		rOFDM0_TxCoeff2				0xca8
++#define		rOFDM0_TxCoeff3				0xcac
++#define		rOFDM0_TxCoeff4				0xcb0
++#define		rOFDM0_TxCoeff5				0xcb4
++#define		rOFDM0_TxCoeff6				0xcb8
++
++
++/*
++ * 7. PageD(0xD00)
++ *   */
++#define		rOFDM1_LSTF					0xd00
++#define		rOFDM1_TRxPathEnable			0xd04
++
++#define		rOFDM1_CFO						0xd08	/* No setting now */
++#define		rOFDM1_CSI1					0xd10
++#define		rOFDM1_SBD						0xd14
++#define		rOFDM1_CSI2					0xd18
++#define		rOFDM1_CFOTracking			0xd2c
++#define		rOFDM1_TRxMesaure1			0xd34
++#define		rOFDM1_IntfDet					0xd3c
++#define		rOFDM1_PseudoNoiseStateAB		0xd50
++#define		rOFDM1_PseudoNoiseStateCD		0xd54
++#define		rOFDM1_RxPseudoNoiseWgt		0xd58
++
++#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
++#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
++#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
++
++#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
++#define		rOFDM_ShortCFOCD				0xdb0
++#define		rOFDM_LongCFOAB				0xdb4
++#define		rOFDM_LongCFOCD				0xdb8
++#define		rOFDM_TailCFOAB				0xdbc
++#define		rOFDM_TailCFOCD				0xdc0
++#define		rOFDM_PWMeasure1		0xdc4
++#define		rOFDM_PWMeasure2		0xdc8
++#define		rOFDM_BWReport				0xdcc
++#define		rOFDM_AGCReport				0xdd0
++#define		rOFDM_RxSNR					0xdd4
++#define		rOFDM_RxEVMCSI				0xdd8
++#define		rOFDM_SIGReport				0xddc
++
++
++/*
++ * 8. PageE(0xE00)
++ *   */
++#define		rTxAGC_Rate18_06				0xe00
++#define		rTxAGC_Rate54_24				0xe04
++#define		rTxAGC_CCK_Mcs32				0xe08
++#define		rTxAGC_Mcs03_Mcs00			0xe10
++#define		rTxAGC_Mcs07_Mcs04			0xe14
++#define		rTxAGC_Mcs11_Mcs08			0xe18
++#define		rTxAGC_Mcs15_Mcs12			0xe1c
++
++/* Analog- control in RX_WAIT_CCA : REG: EE0 [Analog- Power & Control Register] */
++#define		rRx_Wait_CCCA					0xe70
++#define		rAnapar_Ctrl_BB					0xee0
++
++/*
++ * 7. RF Register 0x00-0x2E (RF 8256)
++ * RF-0222D 0x00-3F
++ *
++ * Zebra1 */
++#define RTL92SE_FPGA_VERIFY 0
++#define		rZebra1_HSSIEnable				0x0	/* Useless now */
++#define		rZebra1_TRxEnable1				0x1
++#define		rZebra1_TRxEnable2				0x2
++#define		rZebra1_AGC					0x4
++#define		rZebra1_ChargePump			0x5
++/* #if (RTL92SE_FPGA_VERIFY == 1) */
++#define		rZebra1_Channel				0x7	/* RF channel switch
++ * #else */
++
++/* #endif */
++#define		rZebra1_TxGain					0x8	/* Useless now */
++#define		rZebra1_TxLPF					0x9
++#define		rZebra1_RxLPF					0xb
++#define		rZebra1_RxHPFCorner			0xc
++
++/* Zebra4 */
++#define		rGlobalCtrl						0	/* Useless now */
++#define		rRTL8256_TxLPF					19
++#define		rRTL8256_RxLPF					11
++
++/* RTL8258 */
++#define		rRTL8258_TxLPF					0x11	/* Useless now */
++#define		rRTL8258_RxLPF					0x13
++#define		rRTL8258_RSSILPF				0xa
++
++/*
++ * RL6052 Register definition
++ *   */
++#define		RF_AC						0x00	/*  */
++
++#define		RF_IQADJ_G1				0x01	/*  */
++#define		RF_IQADJ_G2				0x02	/*  */
++#define		RF_POW_TRSW				0x05	/*  */
++
++#define		RF_GAIN_RX					0x06	/*  */
++#define		RF_GAIN_TX					0x07	/*  */
++
++#define		RF_TXM_IDAC				0x08	/*  */
++#define		RF_BS_IQGEN				0x0F	/*  */
++
++#define		RF_MODE1					0x10	/*  */
++#define		RF_MODE2					0x11	/*  */
++
++#define		RF_RX_AGC_HP				0x12	/*  */
++#define		RF_TX_AGC					0x13	/*  */
++#define		RF_BIAS						0x14	/*  */
++#define		RF_IPA						0x15	/*  */
++#define		RF_TXBIAS					0x16
++#define		RF_POW_ABILITY			0x17	/*  */
++#define		RF_MODE_AG				0x18	/*  */
++#define		rRfChannel					0x18	/* RF channel and BW switch */
++#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
++#define		RF_TOP						0x19	/*  */
++
++#define		RF_RX_G1					0x1A	/*  */
++#define		RF_RX_G2					0x1B	/*  */
++
++#define		RF_RX_BB2					0x1C	/*  */
++#define		RF_RX_BB1					0x1D	/*  */
++
++#define		RF_RCK1					0x1E	/*  */
++#define		RF_RCK2					0x1F	/*  */
++
++#define		RF_TX_G1					0x20	/*  */
++#define		RF_TX_G2					0x21	/*  */
++#define		RF_TX_G3					0x22	/*  */
++
++#define		RF_TX_BB1					0x23	/*  */
++
++#define		RF_T_METER					0x24	/*  */
++
++#define		RF_SYN_G1					0x25	/* RF TX Power control */
++#define		RF_SYN_G2					0x26	/* RF TX Power control */
++#define		RF_SYN_G3					0x27	/* RF TX Power control */
++#define		RF_SYN_G4					0x28	/* RF TX Power control */
++#define		RF_SYN_G5					0x29	/* RF TX Power control */
++#define		RF_SYN_G6					0x2A	/* RF TX Power control */
++#define		RF_SYN_G7					0x2B	/* RF TX Power control */
++#define		RF_SYN_G8					0x2C	/* RF TX Power control */
++
++#define		RF_RCK_OS					0x30	/* RF TX PA control */
++
++#define		RF_TXPA_G1					0x31	/* RF TX PA control */
++#define		RF_TXPA_G2					0x32	/* RF TX PA control */
++#define		RF_TXPA_G3					0x33	/* RF TX PA control */
++
++/*
++ * Bit Mask
++ *
++ * 1. Page1(0x100) */
++#define		bBBResetB						0x100	/* Useless now? */
++#define		bGlobalResetB					0x200
++#define		bOFDMTxStart					0x4
++#define		bCCKTxStart						0x8
++#define		bCRC32Debug					0x100
++#define		bPMACLoopback					0x10
++#define		bTxLSIG							0xffffff
++#define		bOFDMTxRate					0xf
++#define		bOFDMTxReserved				0x10
++#define		bOFDMTxLength					0x1ffe0
++#define		bOFDMTxParity					0x20000
++#define		bTxHTSIG1						0xffffff
++#define		bTxHTMCSRate					0x7f
++#define		bTxHTBW						0x80
++#define		bTxHTLength					0xffff00
++#define		bTxHTSIG2						0xffffff
++#define		bTxHTSmoothing					0x1
++#define		bTxHTSounding					0x2
++#define		bTxHTReserved					0x4
++#define		bTxHTAggreation				0x8
++#define		bTxHTSTBC						0x30
++#define		bTxHTAdvanceCoding			0x40
++#define		bTxHTShortGI					0x80
++#define		bTxHTNumberHT_LTF			0x300
++#define		bTxHTCRC8						0x3fc00
++#define		bCounterReset					0x10000
++#define		bNumOfOFDMTx					0xffff
++#define		bNumOfCCKTx					0xffff0000
++#define		bTxIdleInterval					0xffff
++#define		bOFDMService					0xffff0000
++#define		bTxMACHeader					0xffffffff
++#define		bTxDataInit						0xff
++#define		bTxHTMode						0x100
++#define		bTxDataType					0x30000
++#define		bTxRandomSeed					0xffffffff
++#define		bCCKTxPreamble					0x1
++#define		bCCKTxSFD						0xffff0000
++#define		bCCKTxSIG						0xff
++#define		bCCKTxService					0xff00
++#define		bCCKLengthExt					0x8000
++#define		bCCKTxLength					0xffff0000
++#define		bCCKTxCRC16					0xffff
++#define		bCCKTxStatus					0x1
++#define		bOFDMTxStatus					0x2
++
++#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
++
++/* 2. Page8(0x800) */
++#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
++#define		bJapanMode						0x2
++#define		bCCKTxSC						0x30
++#define		bCCKEn							0x1000000
++#define		bOFDMEn						0x2000000
++
++#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
++#define		bOFDMTxDACPhase		0x40000
++#define		bXATxAGC			0x3f
++
++#define		bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
++#define		bXCTxAGC			0xf000
++#define		bXDTxAGC			0xf0000
++
++#define		bPAStart                  			0xf0000000	/* Useless now */
++#define		bTRStart			0x00f00000
++#define		bRFStart			0x0000f000
++#define		bBBStart			0x000000f0
++#define		bBBCCKStart		0x0000000f
++#define		bPAEnd                    			0xf          /* Reg0x814 */
++#define		bTREnd			0x0f000000
++#define		bRFEnd			0x000f0000
++#define		bCCAMask                  			0x000000f0   /* T2R */
++#define		bR2RCCAMask		0x00000f00
++#define		bHSSI_R2TDelay		0xf8000000
++#define		bHSSI_T2RDelay		0xf80000
++#define		bContTxHSSI               		0x400     /* chane gain at continue Tx */
++#define		bIGFromCCK		0x200
++#define		bAGCAddress		0x3f
++#define		bRxHPTx			0x7000
++#define		bRxHPT2R			0x38000
++#define		bRxHPCCKIni		0xc0000
++#define		bAGCTxCode		0xc00000
++#define		bAGCRxCode		0x300000
++
++#define		b3WireDataLength          		0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
++#define		b3WireAddressLength		0x400
++
++#define		b3WireRFPowerDown         		0x1	/* Useless now
++ * #define bHWSISelect		0x8 */
++#define		b5GPAPEPolarity		0x40000000
++#define		b2GPAPEPolarity		0x80000000
++#define		bRFSW_TxDefaultAnt		0x3
++#define		bRFSW_TxOptionAnt		0x30
++#define		bRFSW_RxDefaultAnt		0x300
++#define		bRFSW_RxOptionAnt		0x3000
++#define		bRFSI_3WireData		0x1
++#define		bRFSI_3WireClock		0x2
++#define		bRFSI_3WireLoad		0x4
++#define		bRFSI_3WireRW		0x8
++#define		bRFSI_3Wire			0xf
++
++#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
++
++#define		bRFSI_TRSW                		0x20	/* Useless now */
++#define		bRFSI_TRSWB		0x40
++#define		bRFSI_ANTSW		0x100
++#define		bRFSI_ANTSWB		0x200
++#define		bRFSI_PAPE			0x400
++#define		bRFSI_PAPE5G		0x800
++#define		bBandSelect			0x1
++#define		bHTSIG2_GI			0x80
++#define		bHTSIG2_Smoothing		0x01
++#define		bHTSIG2_Sounding		0x02
++#define		bHTSIG2_Aggreaton		0x08
++#define		bHTSIG2_STBC		0x30
++#define		bHTSIG2_AdvCoding		0x40
++#define		bHTSIG2_NumOfHTLTF	0x300
++#define		bHTSIG2_CRC8		0x3fc
++#define		bHTSIG1_MCS		0x7f
++#define		bHTSIG1_BandWidth		0x80
++#define		bHTSIG1_HTLength		0xffff
++#define		bLSIG_Rate			0xf
++#define		bLSIG_Reserved		0x10
++#define		bLSIG_Length		0x1fffe
++#define		bLSIG_Parity			0x20
++#define		bCCKRxPhase		0x4
++#if (RTL92SE_FPGA_VERIFY == 1)
++	#define		bLSSIReadAddress          		0x3f000000   /* LSSI "Read" Address	 */ /* Reg 0x824 rFPGA0_XA_HSSIParameter2 */
++#else
++	#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
++#endif
++#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
++#if (RTL92SE_FPGA_VERIFY == 1)
++	#define		bLSSIReadBackData         		0xfff		/* Reg 0x8a0 rFPGA0_XA_LSSIReadBack */
++#else
++	#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
++#endif
++#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
++#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
++#define		bRegulator0Standby		0x1
++#define		bRegulatorPLLStandby		0x2
++#define		bRegulator1Standby		0x4
++#define		bPLLPowerUp		0x8
++#define		bDPLLPowerUp		0x10
++#define		bDA10PowerUp		0x20
++#define		bAD7PowerUp		0x200
++#define		bDA6PowerUp		0x2000
++#define		bXtalPowerUp		0x4000
++#define		b40MDClkPowerUP		0x8000
++#define		bDA6DebugMode		0x20000
++#define		bDA6Swing			0x380000
++
++#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
++
++#define		b80MClkDelay              		0x18000000	/* Useless */
++#define		bAFEWatchDogEnable		0x20000000
++
++#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
++#define		bXtalCap23			0x3
++#define		bXtalCap92x					0x0f000000
++#define		bXtalCap			0x0f000000
++
++#define		bIntDifClkEnable          		0x400	/* Useless */
++#define		bExtSigClkEnable		0x800
++#define		bBandgapMbiasPowerUp	0x10000
++#define		bAD11SHGain		0xc0000
++#define		bAD11InputRange		0x700000
++#define		bAD11OPCurrent		0x3800000
++#define		bIPathLoopback		0x4000000
++#define		bQPathLoopback		0x8000000
++#define		bAFELoopback		0x10000000
++#define		bDA10Swing		0x7e0
++#define		bDA10Reverse		0x800
++#define		bDAClkSource		0x1000
++#define		bAD7InputRange		0x6000
++#define		bAD7Gain			0x38000
++#define		bAD7OutputCMMode		0x40000
++#define		bAD7InputCMMode		0x380000
++#define		bAD7Current			0xc00000
++#define		bRegulatorAdjust		0x7000000
++#define		bAD11PowerUpAtTx		0x1
++#define		bDA10PSAtTx		0x10
++#define		bAD11PowerUpAtRx		0x100
++#define		bDA10PSAtRx		0x1000
++#define		bCCKRxAGCFormat		0x200
++#define		bPSDFFTSamplepPoint		0xc000
++#define		bPSDAverageNum		0x3000
++#define		bIQPathControl		0xc00
++#define		bPSDFreq			0x3ff
++#define		bPSDAntennaPath		0x30
++#define		bPSDIQSwitch		0x40
++#define		bPSDRxTrigger		0x400000
++#define		bPSDTxTrigger		0x80000000
++#define		bPSDSineToneScale		0x7f000000
++#define		bPSDReport			0xffff
++
++/* 3. Page9(0x900) */
++#define		bOFDMTxSC                 		0x30000000	/* Useless */
++#define		bCCKTxOn			0x1
++#define		bOFDMTxOn		0x2
++#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
++#define		bDebugItem                		0xff   /* reset debug page and LWord */
++#define		bAntL			0x10
++#define		bAntNonHT				0x100
++#define		bAntHT1			0x1000
++#define		bAntHT2			0x10000
++#define		bAntHT1S1			0x100000
++#define		bAntNonHTS1		0x1000000
++
++/* 4. PageA(0xA00) */
++#define		bCCKBBMode                		0x3	/* Useless */
++#define		bCCKTxPowerSaving		0x80
++#define		bCCKRxPowerSaving		0x40
++
++#define		bCCKSideBand              		0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
++
++#define		bCCKScramble              		0x8	/* Useless */
++#define		bCCKAntDiversity			0x8000
++#define		bCCKCarrierRecovery		0x4000
++#define		bCCKTxRate			0x3000
++#define		bCCKDCCancel		0x0800
++#define		bCCKISICancel		0x0400
++#define		bCCKMatchFilter		0x0200
++#define		bCCKEqualizer		0x0100
++#define		bCCKPreambleDetect		0x800000
++#define		bCCKFastFalseCCA		0x400000
++#define		bCCKChEstStart		0x300000
++#define		bCCKCCACount		0x080000
++#define		bCCKcs_lim			0x070000
++#define		bCCKBistMode		0x80000000
++#define		bCCKCCAMask		0x40000000
++#define		bCCKTxDACPhase		0x4
++#define		bCCKRxADCPhase         	   	0x20000000   /* r_rx_clk */
++#define		bCCKr_cp_mode0		0x0100
++#define		bCCKTxDCOffset		0xf0
++#define		bCCKRxDCOffset		0xf
++#define		bCCKCCAMode		0xc000
++#define		bCCKFalseCS_lim		0x3f00
++#define		bCCKCS_ratio		0xc00000
++#define		bCCKCorgBit_sel		0x300000
++#define		bCCKPD_lim			0x0f0000
++#define		bCCKNewCCA		0x80000000
++#define		bCCKRxHPofIG		0x8000
++#define		bCCKRxIG			0x7f00
++#define		bCCKLNAPolarity		0x800000
++#define		bCCKRx1stGain		0x7f0000
++#define		bCCKRFExtend              		0x20000000 /* CCK Rx Iinital gain polarity */
++#define		bCCKRxAGCSatLevel		0x1f000000
++#define		bCCKRxAGCSatCount		0xe0
++#define		bCCKRxRFSettle            		0x1f       /* AGCsamp_dly */
++#define		bCCKFixedRxAGC		0x8000
++/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
++#define		bCCKAntennaPolarity		0x2000
++#define		bCCKTxFilterType		0x0c00
++#define		bCCKRxAGCReportType		0x0300
++#define		bCCKRxDAGCEn		0x80000000
++#define		bCCKRxDAGCPeriod		0x20000000
++#define		bCCKRxDAGCSatLevel		0x1f000000
++#define		bCCKTimingRecovery		0x800000
++#define		bCCKTxC0			0x3f0000
++#define		bCCKTxC1			0x3f000000
++#define		bCCKTxC2			0x3f
++#define		bCCKTxC3			0x3f00
++#define		bCCKTxC4			0x3f0000
++#define		bCCKTxC5			0x3f000000
++#define		bCCKTxC6			0x3f
++#define		bCCKTxC7			0x3f00
++#define		bCCKDebugPort		0xff0000
++#define		bCCKDACDebug		0x0f000000
++#define		bCCKFalseAlarmEnable		0x8000
++#define		bCCKFalseAlarmRead		0x4000
++#define		bCCKTRSSI			0x7f
++#define		bCCKRxAGCReport		0xfe
++#define		bCCKRxReport_AntSel		0x80000000
++#define		bCCKRxReport_MFOff		0x40000000
++#define		bCCKRxRxReport_SQLoss	0x20000000
++#define		bCCKRxReport_Pktloss		0x10000000
++#define		bCCKRxReport_Lockedbit	0x08000000
++#define		bCCKRxReport_RateError	0x04000000
++#define		bCCKRxReport_RxRate		0x03000000
++#define		bCCKRxFACounterLower	0xff
++#define		bCCKRxFACounterUpper	0xff000000
++#define		bCCKRxHPAGCStart		0xe000
++#define		bCCKRxHPAGCFinal		0x1c00
++#define		bCCKRxFalseAlarmEnable	0x8000
++#define		bCCKFACounterFreeze		0x4000
++#define		bCCKTxPathSel		0x10000000
++#define		bCCKDefaultRxPath		0xc000000
++#define		bCCKOptionRxPath		0x3000000
++
++/* 5. PageC(0xC00) */
++#define		bNumOfSTF                			0x3	/* Useless */
++#define		bShift_L			0xc0
++#define		bGI_TH			0xc
++#define		bRxPathA			0x1
++#define		bRxPathB			0x2
++#define		bRxPathC			0x4
++#define		bRxPathD			0x8
++#define		bTxPathA			0x1
++#define		bTxPathB			0x2
++#define		bTxPathC			0x4
++#define		bTxPathD			0x8
++#define		bTRSSIFreq			0x200
++#define		bADCBackoff			0x3000
++#define		bDFIRBackoff			0xc000
++#define		bTRSSILatchPhase		0x10000
++#define		bRxIDCOffset			0xff
++#define		bRxQDCOffset			0xff00
++#define		bRxDFIRMode		0x1800000
++#define		bRxDCNFType		0xe000000
++#define		bRXIQImb_A			0x3ff
++#define		bRXIQImb_B			0xfc00
++#define		bRXIQImb_C			0x3f0000
++#define		bRXIQImb_D			0xffc00000
++#define		bDC_dc_Notch		0x60000
++#define		bRxNBINotch			0x1f000000
++#define		bPD_TH			0xf
++#define		bPD_TH_Opt2		0xc000
++#define		bPWED_TH			0x700
++#define		bIfMF_Win_L			0x800
++#define		bPD_Option			0x1000
++#define		bMF_Win_L			0xe000
++#define		bBW_Search_L		0x30000
++#define		bwin_enh_L			0xc0000
++#define		bBW_TH			0x700000
++#define		bED_TH2			0x3800000
++#define		bBW_option			0x4000000
++#define		bRatio_TH			0x18000000
++#define		bWindow_L			0xe0000000
++#define		bSBD_Option			0x1
++#define		bFrame_TH			0x1c
++#define		bFS_Option			0x60
++#define		bDC_Slope_check		0x80
++#define		bFGuard_Counter_DC_L		0xe00
++#define		bFrame_Weight_Short		0x7000
++#define		bSub_Tune			0xe00000
++#define		bFrame_DC_Length		0xe000000
++#define		bSBD_start_offset		0x30000000
++#define		bFrame_TH_2		0x7
++#define		bFrame_GI2_TH		0x38
++#define		bGI2_Sync_en		0x40
++#define		bSarch_Short_Early		0x300
++#define		bSarch_Short_Late		0xc00
++#define		bSarch_GI2_Late		0x70000
++#define		bCFOAntSum		0x1
++#define		bCFOAcc			0x2
++#define		bCFOStartOffset		0xc
++#define		bCFOLookBack		0x70
++#define		bCFOSumWeight		0x80
++#define		bDAGCEnable			0x10000
++#define		bTXIQImb_A			0x3ff
++#define		bTXIQImb_B			0xfc00
++#define		bTXIQImb_C			0x3f0000
++#define		bTXIQImb_D			0xffc00000
++#define		bTxIDCOffset			0xff
++#define		bTxQDCOffset			0xff00
++#define		bTxDFIRMode		0x10000
++#define		bTxPesudoNoiseOn		0x4000000
++#define		bTxPesudoNoise_A		0xff
++#define		bTxPesudoNoise_B		0xff00
++#define		bTxPesudoNoise_C		0xff0000
++#define		bTxPesudoNoise_D		0xff000000
++#define		bCCADropOption		0x20000
++#define		bCCADropThres		0xfff00000
++#define		bEDCCA_H			0xf
++#define		bEDCCA_L			0xf0
++#define		bLambda_ED               0x300
++#define		bRxInitialGain           0x7f
++#define		bRxAntDivEn              0x80
++#define		bRxAGCAddressForLNA      0x7f00
++#define		bRxHighPowerFlow         0x8000
++#define		bRxAGCFreezeThres        0xc0000
++#define		bRxFreezeStep_AGC1       0x300000
++#define		bRxFreezeStep_AGC2       0xc00000
++#define		bRxFreezeStep_AGC3       0x3000000
++#define		bRxFreezeStep_AGC0       0xc000000
++#define		bRxRssi_Cmp_En           0x10000000
++#define		bRxQuickAGCEn            0x20000000
++#define		bRxAGCFreezeThresMode    0x40000000
++#define		bRxOverFlowCheckType     0x80000000
++#define		bRxAGCShift              0x7f
++#define		bTRSW_Tri_Only           0x80
++#define		bPowerThres              0x300
++#define		bRxAGCEn                 0x1
++#define		bRxAGCTogetherEn         0x2
++#define		bRxAGCMin                0x4
++#define		bRxHP_Ini                0x7
++#define		bRxHP_TRLNA              0x70
++#define		bRxHP_RSSI               0x700
++#define		bRxHP_BBP1               0x7000
++#define		bRxHP_BBP2               0x70000
++#define		bRxHP_BBP3               0x700000
++#define		bRSSI_H                  0x7f0000     /* the threshold for high power */
++#define		bRSSI_Gen                0x7f000000   /* the threshold for ant diversity */
++#define		bRxSettle_TRSW           0x7
++#define		bRxSettle_LNA            0x38
++#define		bRxSettle_RSSI           0x1c0
++#define		bRxSettle_BBP            0xe00
++#define		bRxSettle_RxHP           0x7000
++#define		bRxSettle_AntSW_RSSI     0x38000
++#define		bRxSettle_AntSW          0xc0000
++#define		bRxProcessTime_DAGC      0x300000
++#define		bRxSettle_HSSI           0x400000
++#define		bRxProcessTime_BBPPW     0x800000
++#define		bRxAntennaPowerShift     0x3000000
++#define		bRSSITableSelect         0xc000000
++#define		bRxHP_Final              0x7000000
++#define		bRxHTSettle_BBP          0x7
++#define		bRxHTSettle_HSSI         0x8
++#define		bRxHTSettle_RxHP         0x70
++#define		bRxHTSettle_BBPPW        0x80
++#define		bRxHTSettle_Idle         0x300
++#define		bRxHTSettle_Reserved     0x1c00
++#define		bRxHTRxHPEn              0x8000
++#define		bRxHTAGCFreezeThres      0x30000
++#define		bRxHTAGCTogetherEn       0x40000
++#define		bRxHTAGCMin              0x80000
++#define		bRxHTAGCEn               0x100000
++#define		bRxHTDAGCEn              0x200000
++#define		bRxHTRxHP_BBP            0x1c00000
++#define		bRxHTRxHP_Final          0xe0000000
++#define		bRxPWRatioTH             0x3
++#define		bRxPWRatioEn             0x4
++#define		bRxMFHold                0x3800
++#define		bRxPD_Delay_TH1          0x38
++#define		bRxPD_Delay_TH2          0x1c0
++#define		bRxPD_DC_COUNT_MAX       0x600
++/* #define bRxMF_Hold               0x3800 */
++#define		bRxPD_Delay_TH           0x8000
++#define		bRxProcess_Delay         0xf0000
++#define		bRxSearchrange_GI2_Early 0x700000
++#define		bRxFrame_Guard_Counter_L 0x3800000
++#define		bRxSGI_Guard_L           0xc000000
++#define		bRxSGI_Search_L          0x30000000
++#define		bRxSGI_TH                0xc0000000
++#define		bDFSCnt0                 0xff
++#define		bDFSCnt1                 0xff00
++#define		bDFSFlag                 0xf0000
++#define		bMFWeightSum             0x300000
++#define		bMinIdxTH                0x7f000000
++#define		bDAFormat                0x40000
++#define		bTxChEmuEnable           0x01000000
++#define		bTRSWIsolation_A         0x7f
++#define		bTRSWIsolation_B         0x7f00
++#define		bTRSWIsolation_C         0x7f0000
++#define		bTRSWIsolation_D         0x7f000000
++#define		bExtLNAGain              0x7c00
++
++/* 6. PageE(0xE00) */
++#define		bSTBCEn                  0x4	/* Useless */
++#define		bAntennaMapping          0x10
++#define		bNss                     0x20
++#define		bCFOAntSumD              0x200
++#define		bPHYCounterReset         0x8000000
++#define		bCFOReportGet            0x4000000
++#define		bOFDMContinueTx          0x10000000
++#define		bOFDMSingleCarrier       0x20000000
++#define		bOFDMSingleTone          0x40000000
++/* #define bRxPath1                 0x01 */
++/* #define bRxPath2                 0x02 */
++/* #define bRxPath3                 0x04 */
++/* #define bRxPath4                 0x08 */
++/* #define bTxPath1                 0x10 */
++/* #define bTxPath2                 0x20 */
++#define		bHTDetect                0x100
++#define		bCFOEn                   0x10000
++#define		bCFOValue                0xfff00000
++#define		bSigTone_Re              0x3f
++#define		bSigTone_Im              0x7f00
++#define		bCounter_CCA             0xffff
++#define		bCounter_ParityFail      0xffff0000
++#define		bCounter_RateIllegal     0xffff
++#define		bCounter_CRC8Fail        0xffff0000
++#define		bCounter_MCSNoSupport    0xffff
++#define		bCounter_FastSync        0xffff
++#define		bShortCFO                0xfff
++#define		bShortCFOTLength         12   /* total */
++#define		bShortCFOFLength         11   /* fraction */
++#define		bLongCFO                 0x7ff
++#define		bLongCFOTLength          11
++#define		bLongCFOFLength          11
++#define		bTailCFO                 0x1fff
++#define		bTailCFOTLength          13
++#define		bTailCFOFLength          12
++#define		bmax_en_pwdB             0xffff
++#define		bCC_power_dB             0xffff0000
++#define		bnoise_pwdB              0xffff
++#define		bPowerMeasTLength        10
++#define		bPowerMeasFLength        3
++#define		bRx_HT_BW                0x1
++#define		bRxSC                    0x6
++#define		bRx_HT                   0x8
++#define		bNB_intf_det_on          0x1
++#define		bIntf_win_len_cfg        0x30
++#define		bNB_Intf_TH_cfg          0x1c0
++#define		bRFGain                  0x3f
++#define		bTableSel                0x40
++#define		bTRSW                    0x80
++#define		bRxSNR_A                 0xff
++#define		bRxSNR_B                 0xff00
++#define		bRxSNR_C                 0xff0000
++#define		bRxSNR_D                 0xff000000
++#define		bSNREVMTLength           8
++#define		bSNREVMFLength           1
++#define		bCSI1st                  0xff
++#define		bCSI2nd                  0xff00
++#define		bRxEVM1st                0xff0000
++#define		bRxEVM2nd                0xff000000
++#define		bSIGEVM                  0xff
++#define		bPWDB                    0xff00
++#define		bSGIEN                   0x10000
++
++#define		bSFactorQAM1             0xf	/* Useless */
++#define		bSFactorQAM2             0xf0
++#define		bSFactorQAM3             0xf00
++#define		bSFactorQAM4             0xf000
++#define		bSFactorQAM5             0xf0000
++#define		bSFactorQAM6             0xf0000
++#define		bSFactorQAM7             0xf00000
++#define		bSFactorQAM8             0xf000000
++#define		bSFactorQAM9             0xf0000000
++#define		bCSIScheme               0x100000
++
++#define		bNoiseLvlTopSet          0x3	/* Useless */
++#define		bChSmooth                0x4
++#define		bChSmoothCfg1            0x38
++#define		bChSmoothCfg2            0x1c0
++#define		bChSmoothCfg3            0xe00
++#define		bChSmoothCfg4            0x7000
++#define		bMRCMode                 0x800000
++#define		bTHEVMCfg                0x7000000
++
++#define		bLoopFitType             0x1	/* Useless */
++#define		bUpdCFO                  0x40
++#define		bUpdCFOOffData           0x80
++#define		bAdvUpdCFO               0x100
++#define		bAdvTimeCtrl             0x800
++#define		bUpdClko                 0x1000
++#define		bFC                      0x6000
++#define		bTrackingMode            0x8000
++#define		bPhCmpEnable             0x10000
++#define		bUpdClkoLTF              0x20000
++#define		bComChCFO                0x40000
++#define		bCSIEstiMode             0x80000
++#define		bAdvUpdEqz               0x100000
++#define		bUChCfg                  0x7000000
++#define		bUpdEqz                  0x8000000
++
++#define		bTxAGCRate18_06			0x7f7f7f7f	/* Useless */
++#define		bTxAGCRate54_24			0x7f7f7f7f
++#define		bTxAGCRateMCS32			0x7f
++#define		bTxAGCRateCCK			0x7f00
++#define		bTxAGCRateMCS3_MCS0		0x7f7f7f7f
++#define		bTxAGCRateMCS7_MCS4		0x7f7f7f7f
++#define		bTxAGCRateMCS11_MCS8	0x7f7f7f7f
++#define		bTxAGCRateMCS15_MCS12	0x7f7f7f7f
++
++/* Rx Pseduo noise */
++#define		bRxPesudoNoiseOn         0x20000000	/* Useless */
++#define		bRxPesudoNoise_A         0xff
++#define		bRxPesudoNoise_B         0xff00
++#define		bRxPesudoNoise_C         0xff0000
++#define		bRxPesudoNoise_D         0xff000000
++#define		bPesudoNoiseState_A      0xffff
++#define		bPesudoNoiseState_B      0xffff0000
++#define		bPesudoNoiseState_C      0xffff
++#define		bPesudoNoiseState_D      0xffff0000
++
++/* 7. RF Register
++ * Zebra1 */
++#define		bZebra1_HSSIEnable        0x8		/* Useless */
++#define		bZebra1_TRxControl        0xc00
++#define		bZebra1_TRxGainSetting    0x07f
++#define		bZebra1_RxCorner          0xc00
++#define		bZebra1_TxChargePump      0x38
++#define		bZebra1_RxChargePump      0x7
++#define		bZebra1_ChannelNum        0xf80
++#define		bZebra1_TxLPFBW           0x400
++#define		bZebra1_RxLPFBW           0x600
++
++/* Zebra4 */
++#define		bRTL8256RegModeCtrl1      0x100	/* Useless */
++#define		bRTL8256RegModeCtrl0      0x40
++#define		bRTL8256_TxLPFBW          0x18
++#define		bRTL8256_RxLPFBW          0x600
++
++/* RTL8258 */
++#define		bRTL8258_TxLPFBW          0xc	/* Useless */
++#define		bRTL8258_RxLPFBW          0xc00
++#define		bRTL8258_RSSILPFBW        0xc0
++
++
++/*
++ * Other Definition
++ *   */
++
++/* byte endable for sb_write */
++#define		bByte0                    0x1	/* Useless */
++#define		bByte1                    0x2
++#define		bByte2                    0x4
++#define		bByte3                    0x8
++#define		bWord0                    0x3
++#define		bWord1                    0xc
++#define		bDWord                    0xf
++
++/* for PutRegsetting & GetRegSetting BitMask */
++#define		bMaskByte0		0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
++#define		bMaskByte1		0xff00
++#define		bMaskByte2		0xff0000
++#define		bMaskByte3		0xff000000
++#define		bMaskHWord	0xffff0000
++#define		bMaskLWord		0x0000ffff
++#define		bMaskDWord	0xffffffff
++#define		bMaskH4Bits		0xf0000000
++#define		bMaskH3Bytes	0xffffff00
++#define		bMaskOFDM_D	0xffc00000
++#define		bMaskCCK		0x3f3f3f3f
++#define		bMask12Bits		0xfff
++
++/* for PutRFRegsetting & GetRFRegSetting BitMask */
++#if (RTL92SE_FPGA_VERIFY == 1)
++/* #define		bMask12Bits               0xfff */	/* RF Reg mask bits */
++/* #define		bMask20Bits               0xfff */	/* RF Reg mask bits T65 RF */
++#define		bRFRegOffsetMask	0xfff
++#else
++/* #define		bMask12Bits               0xfffff */	/* RF Reg mask bits */
++/* #define		bMask20Bits               0xfffff */	/* RF Reg mask bits T65 RF */
++#define		bRFRegOffsetMask	0xfffff
++#endif
++#define		bEnable                   0x1	/* Useless */
++#define		bDisable                  0x0
++
++#define		LeftAntenna               0x0	/* Useless */
++#define		RightAntenna              0x1
++
++#define		tCheckTxStatus            500   /* 500ms */ /* Useless */
++#define		tUpdateRxCounter          100   /* 100ms */
++
++#define		rateCCK     0	/* Useless */
++#define		rateOFDM    1
++#define		rateHT      2
++
++/* define Register-End */
++#define		bPMAC_End                 0x1ff	/* Useless */
++#define		bFPGAPHY0_End             0x8ff
++#define		bFPGAPHY1_End             0x9ff
++#define		bCCKPHY0_End              0xaff
++#define		bOFDMPHY0_End             0xcff
++#define		bOFDMPHY1_End             0xdff
++
++/* define max debug item in each debug page
++ * #define bMaxItem_FPGA_PHY0        0x9
++ * #define bMaxItem_FPGA_PHY1        0x3
++ * #define bMaxItem_PHY_11B          0x16
++ * #define bMaxItem_OFDM_PHY0        0x29
++ * #define bMaxItem_OFDM_PHY1        0x0 */
++
++#define		bPMACControl	0x0		/* Useless */
++#define		bWMACControl	0x1
++#define		bWNICControl	0x2
++
++#if 0
++#define		ANTENNA_A	0x1	/* Useless */
++#define		ANTENNA_B	0x2
++#define		ANTENNA_AB	0x3	/* ANTENNA_A | ANTENNA_B */
++
++#define		ANTENNA_C	0x4
++#define		ANTENNA_D	0x8
++#endif
++
++#define RCR_AAP			BIT(0)				/* accept all physical address */
++#define RCR_APM			BIT(1)				/* accept physical match */
++#define RCR_AM			BIT(2)				/* accept multicast */
++#define RCR_AB			BIT(3)				/* accept broadcast */
++#define RCR_ACRC32		BIT(5)				/* accept error packet */
++#define RCR_9356SEL		BIT(6)
++#define RCR_AICV		BIT(9)				/* Accept ICV error packet */
++#define RCR_RXFTH0		(BIT(13) | BIT(14) | BIT(15))	/* Rx FIFO threshold */
++#define RCR_ADF			BIT(18)				/* Accept Data(frame type) frame */
++#define RCR_ACF			BIT(19)				/* Accept control frame */
++#define RCR_AMF			BIT(20)				/* Accept management frame */
++#define RCR_ADD3		BIT(21)
++#define RCR_APWRMGT		BIT(22)				/* Accept power management packet */
++#define RCR_CBSSID		BIT(23)				/* Accept BSSID match packet */
++#define RCR_ENMARP		BIT(28)				/* enable mac auto reset phy */
++#define RCR_EnCS1		BIT(29)				/* enable carrier sense method 1 */
++#define RCR_EnCS2		BIT(30)				/* enable carrier sense method 2 */
++#define RCR_OnlyErlPkt		BIT(31)				/* Rx Early mode is performed for packet size greater than 1536 */
++
++/*--------------------------Define Parameters-------------------------------*/
++
++
++#endif /* __INC_HAL8192SPHYREG_H */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_odm.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_odm.h
+new file mode 100644
+index 000000000..a6e242e99
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_odm.h
+@@ -0,0 +1,102 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_ODM_H__
++#define __RTW_ODM_H__
++
++#include <drv_types.h>
++#include "../hal/phydm/phydm_types.h"
++/*
++* This file provides utilities/wrappers for rtw driver to use ODM
++*/
++typedef enum _HAL_PHYDM_OPS {
++	HAL_PHYDM_DIS_ALL_FUNC,
++	HAL_PHYDM_FUNC_SET,
++	HAL_PHYDM_FUNC_CLR,
++	HAL_PHYDM_ABILITY_BK,
++	HAL_PHYDM_ABILITY_RESTORE,
++	HAL_PHYDM_ABILITY_SET,
++	HAL_PHYDM_ABILITY_GET,
++} HAL_PHYDM_OPS;
++
++
++#define DYNAMIC_FUNC_DISABLE		(0x0)
++	u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability);
++
++#define rtw_phydm_func_disable_all(adapter)	\
++		rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0)
++
++#ifdef CONFIG_RTW_ACS
++#define rtw_phydm_func_for_offchannel(adapter) \
++		do { \
++			rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \
++			if (rtw_odm_adaptivity_needed(adapter)) \
++				rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \
++			if (IS_ACS_ENABLE(adapter))\
++				rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ENV_MONITOR); \
++		} while (0)
++#else
++#define rtw_phydm_func_for_offchannel(adapter) \
++		do { \
++			rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \
++			if (rtw_odm_adaptivity_needed(adapter)) \
++				rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \
++		} while (0)
++#endif
++
++#define rtw_phydm_func_clr(adapter, ability)	\
++		rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_CLR, ability)
++
++#define rtw_phydm_ability_backup(adapter)	\
++		rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_BK, 0)
++
++#define rtw_phydm_ability_restore(adapter)	\
++		rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_RESTORE, 0)
++
++
++static inline u32 rtw_phydm_ability_get(_adapter *adapter)
++{
++	return rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_GET, 0);
++}
++
++
++void rtw_odm_init_ic_type(_adapter *adapter);
++
++void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter);
++
++bool rtw_odm_adaptivity_needed(_adapter *adapter);
++void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter);
++void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff);
++void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter);
++void rtw_odm_acquirespinlock(_adapter *adapter,	enum rt_spinlock_type type);
++void rtw_odm_releasespinlock(_adapter *adapter,	enum rt_spinlock_type type);
++
++struct dm_struct;
++s16 rtw_odm_get_tx_power_mbm(struct dm_struct *dm, u8 rfpath, u8 rate, u8 bw, u8 cch);
++
++#ifdef CONFIG_DFS_MASTER
++void rtw_odm_radar_detect_reset(_adapter *adapter);
++void rtw_odm_radar_detect_disable(_adapter *adapter);
++void rtw_odm_radar_detect_enable(_adapter *adapter);
++BOOLEAN rtw_odm_radar_detect(_adapter *adapter);
++u8 rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv *dvobj);
++#endif /* CONFIG_DFS_MASTER */
++
++void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys);
++
++#if defined(CONFIG_RTL8822C) && defined(CONFIG_LPS_PG)
++void odm_lps_pg_debug_8822c(void *dm_void);
++#endif
++
++#endif /* __RTW_ODM_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_p2p.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_p2p.h
+new file mode 100644
+index 000000000..1f985ad1b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_p2p.h
+@@ -0,0 +1,169 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_P2P_H_
++#define __RTW_P2P_H_
++
++
++u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 *pssid, u8 ussidlen, u8 *pdev_raddr);
++u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code);
++u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++#ifdef CONFIG_WFD
++int rtw_init_wifi_display_info(_adapter *padapter);
++void rtw_wfd_enable(_adapter *adapter, bool on);
++void rtw_wfd_set_ctrl_port(_adapter *adapter, u16 port);
++void rtw_tdls_wfd_enable(_adapter *adapter, bool on);
++
++u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled);
++u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
++
++u32 rtw_append_beacon_wfd_ie(_adapter *adapter, u8 *pbuf);
++u32 rtw_append_probe_req_wfd_ie(_adapter *adapter, u8 *pbuf);
++u32 rtw_append_probe_resp_wfd_ie(_adapter *adapter, u8 *pbuf);
++u32 rtw_append_assoc_req_wfd_ie(_adapter *adapter, u8 *pbuf);
++u32 rtw_append_assoc_resp_wfd_ie(_adapter *adapter, u8 *pbuf);
++#endif /*CONFIG_WFD */
++
++void rtw_xframe_chk_wfd_ie(struct xmit_frame *xframe);
++
++u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
++u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta);
++u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
++u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
++u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo,  u8 *pframe, uint len);
++u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo,  u8 *pframe);
++u8 process_p2p_group_negotation_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
++u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
++u8 process_p2p_group_negotation_confirm(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
++u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
++int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength);
++
++s32 p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf);
++
++#ifdef CONFIG_P2P_PS
++void	process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength);
++void	p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state);
++u8	p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue);
++#endif /* CONFIG_P2P_PS */
++
++#ifdef CONFIG_IOCTL_CFG80211
++u8 roch_stay_in_cur_chan(_adapter *padapter);
++void rtw_init_cfg80211_wifidirect_info(_adapter	*padapter);
++int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx);
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++void reset_global_wifidirect_info(_adapter *padapter);
++void rtw_init_wifidirect_timers(_adapter *padapter);
++void rtw_init_wifidirect_addrs(_adapter *padapter, u8 *dev_addr, u8 *iface_addr);
++void init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role);
++int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role);
++
++static inline void _rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)
++{
++	if (wdinfo->p2p_state != state) {
++		/* wdinfo->pre_p2p_state = wdinfo->p2p_state; */
++		wdinfo->p2p_state = state;
++	}
++}
++static inline void _rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)
++{
++	if (wdinfo->pre_p2p_state != state)
++		wdinfo->pre_p2p_state = state;
++}
++#if 0
++static inline void _rtw_p2p_restore_state(struct wifidirect_info *wdinfo)
++{
++	if (wdinfo->pre_p2p_state != -1) {
++		wdinfo->p2p_state = wdinfo->pre_p2p_state;
++		wdinfo->pre_p2p_state = -1;
++	}
++}
++#endif
++void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role);
++
++static inline int _rtw_p2p_state(struct wifidirect_info *wdinfo)
++{
++	return wdinfo->p2p_state;
++}
++static inline int _rtw_p2p_pre_state(struct wifidirect_info *wdinfo)
++{
++	return wdinfo->pre_p2p_state;
++}
++static inline int _rtw_p2p_role(struct wifidirect_info *wdinfo)
++{
++	return wdinfo->role;
++}
++static inline bool _rtw_p2p_chk_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)
++{
++	return wdinfo->p2p_state == state;
++}
++static inline bool _rtw_p2p_chk_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role)
++{
++	return wdinfo->role == role;
++}
++
++#ifdef CONFIG_DBG_P2P
++void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line);
++void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line);
++/* void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line); */
++void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line);
++#define rtw_p2p_set_state(wdinfo, state) dbg_rtw_p2p_set_state(wdinfo, state, __FUNCTION__, __LINE__)
++#define rtw_p2p_set_pre_state(wdinfo, state) dbg_rtw_p2p_set_pre_state(wdinfo, state, __FUNCTION__, __LINE__)
++#define rtw_p2p_set_role(wdinfo, role) dbg_rtw_p2p_set_role(wdinfo, role, __FUNCTION__, __LINE__)
++/* #define rtw_p2p_restore_state(wdinfo) dbg_rtw_p2p_restore_state(wdinfo, __FUNCTION__, __LINE__) */
++#else /* CONFIG_DBG_P2P */
++#define rtw_p2p_set_state(wdinfo, state) _rtw_p2p_set_state(wdinfo, state)
++#define rtw_p2p_set_pre_state(wdinfo, state) _rtw_p2p_set_pre_state(wdinfo, state)
++#define rtw_p2p_set_role(wdinfo, role) _rtw_p2p_set_role(wdinfo, role)
++/* #define rtw_p2p_restore_state(wdinfo) _rtw_p2p_restore_state(wdinfo) */
++#endif /* CONFIG_DBG_P2P */
++
++#define rtw_p2p_state(wdinfo) _rtw_p2p_state(wdinfo)
++#define rtw_p2p_pre_state(wdinfo) _rtw_p2p_pre_state(wdinfo)
++#define rtw_p2p_role(wdinfo) _rtw_p2p_role(wdinfo)
++#define rtw_p2p_chk_state(wdinfo, state) _rtw_p2p_chk_state(wdinfo, state)
++#define rtw_p2p_chk_role(wdinfo, role) _rtw_p2p_chk_role(wdinfo, role)
++
++#define rtw_p2p_findphase_ex_set(wdinfo, value) \
++	(wdinfo)->find_phase_state_exchange_cnt = (value)
++
++#ifdef CONFIG_P2P
++/* is this find phase exchange for social channel scan? */
++#define rtw_p2p_findphase_ex_is_social(wdinfo)   \
++	(wdinfo)->find_phase_state_exchange_cnt >= P2P_FINDPHASE_EX_SOCIAL_FIRST
++
++/* should we need find phase exchange anymore? */
++#define rtw_p2p_findphase_ex_is_needed(wdinfo) \
++	((wdinfo)->find_phase_state_exchange_cnt < P2P_FINDPHASE_EX_MAX && \
++	 (wdinfo)->find_phase_state_exchange_cnt != P2P_FINDPHASE_EX_NONE && \
++	 !(wdinfo)->rx_invitereq_info.scan_op_ch_only && \
++	 !(wdinfo)->p2p_info.scan_op_ch_only)
++#else
++#define rtw_p2p_findphase_ex_is_social(wdinfo) 0
++#define rtw_p2p_findphase_ex_is_needed(wdinfo) 0
++#endif /* CONFIG_P2P */
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_pwrctrl.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_pwrctrl.h
+new file mode 100644
+index 000000000..eb1aa3953
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_pwrctrl.h
+@@ -0,0 +1,625 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_PWRCTRL_H_
++#define __RTW_PWRCTRL_H_
++
++
++#define FW_PWR0	0
++#define FW_PWR1	1
++#define FW_PWR2	2
++#define FW_PWR3	3
++
++
++#define HW_PWR0	7
++#define HW_PWR1	6
++#define HW_PWR2	2
++#define HW_PWR3	0
++#define HW_PWR4	8
++
++#define FW_PWRMSK	0x7
++
++
++#define XMIT_ALIVE	BIT(0)
++#define RECV_ALIVE	BIT(1)
++#define CMD_ALIVE	BIT(2)
++#define EVT_ALIVE	BIT(3)
++#ifdef CONFIG_BT_COEXIST
++#define BTCOEX_ALIVE	BIT(4)
++#endif /* CONFIG_BT_COEXIST */
++#define LPS_ALIVE	BIT(5)
++
++#ifdef CONFIG_WOWLAN
++	#ifdef CONFIG_PLATFORM_ANDROID_INTEL_X86
++		/* TCP/ICMP/UDP multicast with specific IP addr */
++		#define DEFAULT_PATTERN_NUM 4
++	#else
++		/* TCP/ICMP */
++		#define DEFAULT_PATTERN_NUM 3
++	#endif
++
++#ifdef CONFIG_WOW_PATTERN_HW_CAM	/* Frame Mask Cam number for pattern match */
++#define MAX_WKFM_CAM_NUM	12
++#else
++#define MAX_WKFM_CAM_NUM	16
++#endif
++
++#define MAX_WKFM_SIZE	16 /* (16 bytes for WKFM bit mask, 16*8 = 128 bits) */
++#define MAX_WKFM_PATTERN_SIZE	128
++
++/*
++ * MAX_WKFM_PATTERN_STR_LEN : the max. length of wow pattern string
++ *	e.g. echo 00:01:02:...:7f > /proc/net/rtl88x2bu/wlan0/wow_pattern_info
++ *	- each byte of pattern is represented as 2-bytes ascii : MAX_WKFM_PATTERN_SIZE * 2
++ *	- the number of common ':' in pattern string : MAX_WKFM_PATTERN_SIZE - 1
++ *	- 1 byte '\n'(0x0a) is generated at the end when we use echo command
++ *	so total max. length is (MAX_WKFM_PATTERN_SIZE * 3)
++ */
++#define MAX_WKFM_PATTERN_STR_LEN (MAX_WKFM_PATTERN_SIZE * 3)
++
++#define WKFMCAM_ADDR_NUM 6
++#define WKFMCAM_SIZE 24 /* each entry need 6*4 bytes */
++enum pattern_type {
++	PATTERN_BROADCAST = 0,
++	PATTERN_MULTICAST,
++	PATTERN_UNICAST,
++	PATTERN_VALID,
++	PATTERN_INVALID,
++};
++
++typedef struct rtl_priv_pattern {
++	int len;
++	char content[MAX_WKFM_PATTERN_SIZE];
++	char mask[MAX_WKFM_SIZE];
++} rtl_priv_pattern_t;
++
++#endif /* CONFIG_WOWLAN */
++
++enum Power_Mgnt {
++	PS_MODE_ACTIVE	= 0	,
++	PS_MODE_MIN			,
++	PS_MODE_MAX			,
++	PS_MODE_DTIM			,	/* PS_MODE_SELF_DEFINED */
++	PS_MODE_VOIP			,
++	PS_MODE_UAPSD_WMM	,
++	PS_MODE_UAPSD			,
++	PS_MODE_IBSS			,
++	PS_MODE_WWLAN		,
++	PM_Radio_Off			,
++	PM_Card_Disable		,
++	PS_MODE_NUM,
++};
++
++enum lps_level {
++	LPS_NORMAL = 0,
++	LPS_LCLK,
++	LPS_PG,
++	LPS_LEVEL_MAX,
++};
++
++#ifdef CONFIG_PNO_SUPPORT
++#define MAX_PNO_LIST_COUNT 16
++#define MAX_SCAN_LIST_COUNT 14	/* 2.4G only */
++#define MAX_HIDDEN_AP 8		/* 8 hidden AP */
++#endif
++
++/*
++	BIT[2:0] = HW state
++	BIT[3] = Protocol PS state,   0: register active state , 1: register sleep state
++	BIT[4] = sub-state
++*/
++
++#define PS_DPS				BIT(0)
++#define PS_LCLK				(PS_DPS)
++#define PS_RF_OFF			BIT(1)
++#define PS_ALL_ON			BIT(2)
++#define PS_ST_ACTIVE		BIT(3)
++
++#define PS_ISR_ENABLE		BIT(4)
++#define PS_IMR_ENABLE		BIT(5)
++#define PS_ACK				BIT(6)
++#define PS_TOGGLE			BIT(7)
++
++#define PS_STATE_MASK		(0x0F)
++#define PS_STATE_HW_MASK	(0x07)
++#define PS_SEQ_MASK			(0xc0)
++
++#define PS_STATE(x)		(PS_STATE_MASK & (x))
++#define PS_STATE_HW(x)	(PS_STATE_HW_MASK & (x))
++#define PS_SEQ(x)		(PS_SEQ_MASK & (x))
++
++#define PS_STATE_S0		(PS_DPS)
++#define PS_STATE_S1		(PS_LCLK)
++#define PS_STATE_S2		(PS_RF_OFF)
++#define PS_STATE_S3		(PS_ALL_ON)
++#define PS_STATE_S4		((PS_ST_ACTIVE) | (PS_ALL_ON))
++
++
++#define PS_IS_RF_ON(x)	((x) & (PS_ALL_ON))
++#define PS_IS_ACTIVE(x)	((x) & (PS_ST_ACTIVE))
++#define CLR_PS_STATE(x)	((x) = ((x) & (0xF0)))
++
++
++struct reportpwrstate_parm {
++	unsigned char mode;
++	unsigned char state; /* the CPWM value */
++	unsigned short rsvd;
++};
++
++
++typedef _sema _pwrlock;
++
++
++__inline static void _init_pwrlock(_pwrlock *plock)
++{
++	_rtw_init_sema(plock, 1);
++}
++
++__inline static void _free_pwrlock(_pwrlock *plock)
++{
++	_rtw_free_sema(plock);
++}
++
++
++__inline static void _enter_pwrlock(_pwrlock *plock)
++{
++	_rtw_down_sema(plock);
++}
++
++
++__inline static void _exit_pwrlock(_pwrlock *plock)
++{
++	_rtw_up_sema(plock);
++}
++
++#define LPS_DELAY_MS	1000 /* 1 sec */
++
++#define EXE_PWR_NONE	0x01
++#define EXE_PWR_IPS		0x02
++#define EXE_PWR_LPS		0x04
++
++/* RF state. */
++typedef enum _rt_rf_power_state {
++	rf_on,		/* RF is on after RFSleep or RFOff */
++	rf_sleep,	/* 802.11 Power Save mode */
++	rf_off,		/* HW/SW Radio OFF or Inactive Power Save */
++	/* =====Add the new RF state above this line===== */
++	rf_max
++} rt_rf_power_state;
++
++/* ASPM OSC Control bit, added by Roger, 2013.03.29. */
++#define	RT_PCI_ASPM_OSC_IGNORE		0	 /* PCI ASPM ignore OSC control in default */
++#define	RT_PCI_ASPM_OSC_ENABLE		BIT0 /* PCI ASPM controlled by OS according to ACPI Spec 5.0 */
++#define	RT_PCI_ASPM_OSC_DISABLE		BIT1 /* PCI ASPM controlled by driver or BIOS, i.e., force enable ASPM */
++
++
++enum _PS_BBRegBackup_ {
++	PSBBREG_RF0 = 0,
++	PSBBREG_RF1,
++	PSBBREG_RF2,
++	PSBBREG_AFE0,
++	PSBBREG_TOTALCNT
++};
++
++enum { /* for ips_mode */
++	IPS_NONE = 0,
++	IPS_NORMAL,
++	IPS_LEVEL_2,
++	IPS_NUM
++};
++
++/* Design for pwrctrl_priv.ips_deny, 32 bits for 32 reasons at most */
++typedef enum _PS_DENY_REASON {
++	PS_DENY_DRV_INITIAL = 0,
++	PS_DENY_SCAN,
++	PS_DENY_JOIN,
++	PS_DENY_DISCONNECT,
++	PS_DENY_SUSPEND,
++	PS_DENY_IOCTL,
++	PS_DENY_MGNT_TX,
++	PS_DENY_MONITOR_MODE,
++	PS_DENY_BEAMFORMING,		/* Beamforming */
++	PS_DENY_DRV_REMOVE = 30,
++	PS_DENY_OTHERS = 31
++} PS_DENY_REASON;
++
++#ifdef CONFIG_PNO_SUPPORT
++typedef struct pno_nlo_info {
++	u32 fast_scan_period;				/* Fast scan period */
++	u8	ssid_num;				/* number of entry */
++	u8	hidden_ssid_num;
++	u32	slow_scan_period;			/* slow scan period */
++	u32	fast_scan_iterations;			/* Fast scan iterations */
++	u8	ssid_length[MAX_PNO_LIST_COUNT];	/* SSID Length Array */
++	u8	ssid_cipher_info[MAX_PNO_LIST_COUNT];	/* Cipher information for security */
++	u8	ssid_channel_info[MAX_PNO_LIST_COUNT];	/* channel information */
++	u8	loc_probe_req[MAX_HIDDEN_AP];		/* loc_probeReq */
++} pno_nlo_info_t;
++
++typedef struct pno_ssid {
++	u32		SSID_len;
++	u8		SSID[32];
++} pno_ssid_t;
++
++typedef struct pno_ssid_list {
++	pno_ssid_t	node[MAX_PNO_LIST_COUNT];
++} pno_ssid_list_t;
++
++typedef struct pno_scan_channel_info {
++	u8	channel;
++	u8	tx_power;
++	u8	timeout;
++	u8	active;				/* set 1 means active scan, or pasivite scan. */
++} pno_scan_channel_info_t;
++
++typedef struct pno_scan_info {
++	u8	enableRFE;			/* Enable RFE */
++	u8	period_scan_time;		/* exclusive with fast_scan_period and slow_scan_period */
++	u8	periodScan;			/* exclusive with fast_scan_period and slow_scan_period */
++	u8	orig_80_offset;			/* original channel 80 offset */
++	u8	orig_40_offset;			/* original channel 40 offset */
++	u8	orig_bw;			/* original bandwidth */
++	u8	orig_ch;			/* original channel */
++	u8	channel_num;			/* number of channel */
++	u64	rfe_type;			/* rfe_type && 0x00000000000000ff */
++	pno_scan_channel_info_t ssid_channel_info[MAX_SCAN_LIST_COUNT];
++} pno_scan_info_t;
++#endif /* CONFIG_PNO_SUPPORT */
++
++#ifdef CONFIG_LPS_POFF
++/* Driver context for LPS 32K Close IO Power */
++typedef struct lps_poff_info {
++	bool	bEn;
++	u8	*pStaticFile;
++	u8	*pDynamicFile;
++	u32	ConfFileOffset;
++	u32	tx_bndy_static;
++	u32	tx_bndy_dynamic;
++	u16	ConfLenForPTK;
++	u16	ConfLenForGTK;
++	ATOMIC_T bEnterPOFF;
++	ATOMIC_T bTxBoundInProgress;
++	ATOMIC_T bSetPOFFParm;
++} lps_poff_info_t;
++#endif /*CONFIG_LPS_POFF*/
++
++struct aoac_report {
++	u8 iv[8];
++	u8 replay_counter_eapol_key[8];
++	u8 group_key[32];
++	u8 key_index;
++	u8 security_type;
++	u8 wow_pattern_idx;
++	u8 version_info;
++	u8 rekey_ok:1;
++	u8 dummy:7;
++	u8 reserved[3];
++	u8 rxptk_iv[8];
++	u8 rxgtk_iv[4][8];
++};
++
++struct rsvd_page_cache_t;
++
++struct pwrctrl_priv {
++	_pwrlock	lock;
++	_pwrlock	check_32k_lock;
++	volatile u8 rpwm; /* requested power state for fw */
++	volatile u8 cpwm; /* fw current power state. updated when 1. read from HCPWM 2. driver lowers power level */
++	volatile u8 tog; /* toggling */
++	volatile u8 cpwm_tog; /* toggling */
++	u8 rpwm_retry;
++
++	u8	pwr_mode;
++	u8	smart_ps;
++	u8	bcn_ant_mode;
++	u8	dtim;
++#ifdef CONFIG_LPS_CHK_BY_TP
++	u8	lps_chk_by_tp;
++	u16	lps_tx_tp_th;/*Mbps*/
++	u16	lps_rx_tp_th;/*Mbps*/
++	u16	lps_bi_tp_th;/*Mbps*//*TRX TP*/
++	int	lps_chk_cnt_th;
++	int	lps_chk_cnt;
++	u32	lps_tx_pkts;
++	u32	lps_rx_pkts;
++
++#endif
++
++#ifdef CONFIG_WMMPS_STA
++	u8 wmm_smart_ps;
++#endif /* CONFIG_WMMPS_STA */	
++
++	u32	alives;
++	_workitem cpwm_event;
++	_workitem dma_event; /*for handle un-synchronized tx dma*/
++#ifdef CONFIG_LPS_RPWM_TIMER
++	u8 brpwmtimeout;
++	_workitem rpwmtimeoutwi;
++	_timer pwr_rpwm_timer;
++#endif /* CONFIG_LPS_RPWM_TIMER */
++	u8	bpower_saving; /* for LPS/IPS */
++
++	u8	b_hw_radio_off;
++	u8	reg_rfoff;
++	u8	reg_pdnmode; /* powerdown mode */
++	u32	rfoff_reason;
++
++	uint	ips_enter_cnts;
++	uint	ips_leave_cnts;
++	uint	lps_enter_cnts;
++	uint	lps_leave_cnts;
++
++	u8	ips_mode;
++	u8	ips_org_mode;
++	u8	ips_mode_req; /* used to accept the mode setting request, will update to ipsmode later */
++	uint bips_processing;
++	systime ips_deny_time; /* will deny IPS when system time is smaller than this */
++	u8 pre_ips_type;/* 0: default flow, 1: carddisbale flow */
++
++	/* ps_deny: if 0, power save is free to go; otherwise deny all kinds of power save. */
++	/* Use PS_DENY_REASON to decide reason. */
++	/* Don't access this variable directly without control function, */
++	/* and this variable should be protected by lock. */
++	u32 ps_deny;
++
++	u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */
++
++	u8 fw_psmode_iface_id;
++	u8	bLeisurePs;
++	u8	LpsIdleCount;
++	u8	power_mgnt;
++	u8	org_power_mgnt;
++	u8	bFwCurrentInPSMode;
++	systime	lps_deny_time; /* will deny LPS when system time is smaller than this */
++	s32		pnp_current_pwr_state;
++	u8		pnp_bstop_trx;
++	u8		bInSuspend;
++#ifdef CONFIG_BT_COEXIST
++	u8		bAutoResume;
++	u8		autopm_cnt;
++#endif
++	u8		bSupportRemoteWakeup;
++	u8		wowlan_wake_reason;
++	u8		wowlan_last_wake_reason;
++	u8		wowlan_ap_mode;
++	u8		wowlan_mode;
++	u8		wowlan_p2p_mode;
++	u8		wowlan_pno_enable;
++	u8		wowlan_in_resume;
++
++#ifdef CONFIG_GPIO_WAKEUP
++	u8		is_high_active;
++	u8		wowlan_gpio_index;
++	u8		wowlan_gpio_output_state;
++#endif /* CONFIG_GPIO_WAKEUP */
++	u8		hst2dev_high_active;
++#ifdef CONFIG_WOWLAN
++	bool		default_patterns_en;
++#ifdef CONFIG_IPV6
++	u8		wowlan_ns_offload_en;
++#endif /*CONFIG_IPV6*/
++	u8		wowlan_txpause_status;
++	u8		wowlan_pattern_idx;
++	u64		wowlan_fw_iv;
++	struct rtl_priv_pattern	patterns[MAX_WKFM_CAM_NUM];
++#ifdef CONFIG_PNO_SUPPORT
++	u8		pno_inited;
++	pno_nlo_info_t	*pnlo_info;
++	pno_scan_info_t	*pscan_info;
++	pno_ssid_list_t	*pno_ssid_list;
++#endif /* CONFIG_PNO_SUPPORT */
++#ifdef CONFIG_WOW_PATTERN_HW_CAM
++	_mutex	wowlan_pattern_cam_mutex;
++#endif
++	u8		wowlan_aoac_rpt_loc;
++	struct aoac_report wowlan_aoac_rpt;
++	u8		wowlan_power_mgmt;
++	u8		wowlan_lps_level;
++	#ifdef CONFIG_LPS_1T1R
++	u8		wowlan_lps_1t1r;
++	#endif
++#endif /* CONFIG_WOWLAN */
++	_timer	pwr_state_check_timer;
++	int		pwr_state_check_interval;
++	u8		pwr_state_check_cnts;
++
++
++	rt_rf_power_state	rf_pwrstate;/* cur power state, only for IPS */
++	/* rt_rf_power_state	current_rfpwrstate; */
++	rt_rf_power_state	change_rfpwrstate;
++
++	u8		bHWPowerdown; /* power down mode selection. 0:radio off, 1:power down */
++	u8		bHWPwrPindetect; /* come from registrypriv.hwpwrp_detect. enable power down function. 0:disable, 1:enable */
++	u8		bkeepfwalive;
++	u8		brfoffbyhw;
++	unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
++
++#ifdef CONFIG_RESUME_IN_WORKQUEUE
++	struct workqueue_struct *rtw_workqueue;
++	_workitem resume_work;
++#endif
++
++#ifdef CONFIG_HAS_EARLYSUSPEND
++	struct early_suspend early_suspend;
++	u8 do_late_resume;
++#endif /* CONFIG_HAS_EARLYSUSPEND */
++
++#ifdef CONFIG_ANDROID_POWER
++	android_early_suspend_t early_suspend;
++	u8 do_late_resume;
++#endif
++
++#ifdef CONFIG_LPS_POFF
++	lps_poff_info_t	*plps_poff_info;
++#endif
++	u8 lps_level_bk;
++	u8 lps_level; /*LPS_NORMAL,LPA_CG,LPS_PG*/
++#ifdef CONFIG_LPS_1T1R
++	u8 lps_1t1r_bk;
++	u8 lps_1t1r;
++#endif
++#ifdef CONFIG_LPS_PG
++	struct rsvd_page_cache_t lpspg_info;
++#ifdef CONFIG_RTL8822C
++	struct rsvd_page_cache_t lpspg_dpk_info;
++	struct rsvd_page_cache_t lpspg_iqk_info;
++#endif
++#endif
++	u8 current_lps_hw_port_id;
++
++#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
++	systime radio_on_start_time;
++	systime pwr_saving_start_time;
++	u32 pwr_saving_time;
++	u32 on_time;
++	u32 tx_time;
++	u32 rx_time;
++#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
++
++#ifdef CONFIG_LPS_ACK
++	struct submit_ctx lps_ack_sctx;
++	s8 lps_ack_status;
++	_mutex lps_ack_mutex;
++#endif /* CONFIG_LPS_ACK */
++};
++
++#define rtw_get_ips_mode_req(pwrctl) \
++	(pwrctl)->ips_mode_req
++
++#define rtw_ips_mode_req(pwrctl, ips_mode) \
++	(pwrctl)->ips_mode_req = (ips_mode)
++
++#define RTW_PWR_STATE_CHK_INTERVAL 2000
++
++#define _rtw_set_pwr_state_check_timer(pwrctl, ms) \
++	do { \
++		/*RTW_INFO("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctl), (ms));*/ \
++		_set_timer(&(pwrctl)->pwr_state_check_timer, (ms)); \
++	} while (0)
++
++#define rtw_set_pwr_state_check_timer(pwrctl) \
++	_rtw_set_pwr_state_check_timer((pwrctl), (pwrctl)->pwr_state_check_interval)
++
++extern void rtw_init_pwrctrl_priv(_adapter *adapter);
++extern void rtw_free_pwrctrl_priv(_adapter *adapter);
++
++#ifdef CONFIG_LPS_LCLK
++s32 rtw_register_task_alive(PADAPTER, u32 task);
++void rtw_unregister_task_alive(PADAPTER, u32 task);
++extern s32 rtw_register_tx_alive(PADAPTER padapter);
++extern void rtw_unregister_tx_alive(PADAPTER padapter);
++extern s32 rtw_register_rx_alive(PADAPTER padapter);
++extern void rtw_unregister_rx_alive(PADAPTER padapter);
++extern s32 rtw_register_cmd_alive(PADAPTER padapter);
++extern void rtw_unregister_cmd_alive(PADAPTER padapter);
++extern s32 rtw_register_evt_alive(PADAPTER padapter);
++extern void rtw_unregister_evt_alive(PADAPTER padapter);
++extern void cpwm_int_hdl(PADAPTER padapter, struct reportpwrstate_parm *preportpwrstate);
++extern void LPS_Leave_check(PADAPTER padapter);
++#endif
++
++extern void LeaveAllPowerSaveMode(PADAPTER Adapter);
++extern void LeaveAllPowerSaveModeDirect(PADAPTER Adapter);
++#ifdef CONFIG_IPS
++void _ips_enter(_adapter *padapter);
++void ips_enter(_adapter *padapter);
++int _ips_leave(_adapter *padapter);
++int ips_leave(_adapter *padapter);
++#endif
++
++void rtw_ps_processor(_adapter *padapter);
++
++#ifdef SUPPORT_HW_RFOFF_DETECTED
++rt_rf_power_state RfOnOffDetect(PADAPTER pAdapter);
++#endif
++
++
++#ifdef DBG_CHECK_FW_PS_STATE
++int rtw_fw_ps_state(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_LPS
++extern const char * const LPS_CTRL_PHYDM;
++void LPS_Enter(PADAPTER padapter, const char *msg);
++void LPS_Leave(PADAPTER padapter, const char *msg);
++void rtw_exec_lps(_adapter *padapter, u8 ps_mode);
++void rtw_lps_rfon_ctrl(_adapter *padapter, u8 rfon_ctrl);
++#ifdef CONFIG_CHECK_LEAVE_LPS
++#ifdef CONFIG_LPS_CHK_BY_TP
++void traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info *sta);
++#endif
++void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets);
++#endif /*CONFIG_CHECK_LEAVE_LPS*/
++void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg);
++void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable);
++u8 rtw_set_rpwm(_adapter *padapter, u8 val8);
++#ifdef CONFIG_WOWLAN
++void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en);
++#endif /* CONFIG_WOWLAN */
++#endif /* CONFIG_LPS */
++
++#ifdef CONFIG_RESUME_IN_WORKQUEUE
++void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv);
++#endif /* CONFIG_RESUME_IN_WORKQUEUE */
++
++#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
++bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv);
++bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv);
++void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable);
++void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv);
++void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv);
++#else
++#define rtw_is_earlysuspend_registered(pwrpriv) _FALSE
++#define rtw_is_do_late_resume(pwrpriv) _FALSE
++#define rtw_set_do_late_resume(pwrpriv, enable) do {} while (0)
++#define rtw_register_early_suspend(pwrpriv) do {} while (0)
++#define rtw_unregister_early_suspend(pwrpriv) do {} while (0)
++#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */
++
++u8 rtw_interface_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);
++void rtw_set_ips_deny(_adapter *padapter, u32 ms);
++int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller);
++#define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__)
++#define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) _rtw_pwr_wakeup(adapter, ips_deffer_ms, __FUNCTION__)
++int rtw_pm_set_ips(_adapter *padapter, u8 mode);
++int rtw_pm_set_lps(_adapter *padapter, u8 mode);
++int rtw_pm_set_lps_level(_adapter *padapter, u8 level);
++#ifdef CONFIG_LPS_1T1R
++int rtw_pm_set_lps_1t1r(_adapter *padapter, u8 en);
++#endif
++void rtw_set_lps_deny(_adapter *adapter, u32 ms);
++#ifdef CONFIG_WOWLAN
++int rtw_pm_set_wow_lps(_adapter *padapter, u8 mode);
++int rtw_pm_set_wow_lps_level(_adapter *padapter, u8 level);
++#ifdef CONFIG_LPS_1T1R
++int rtw_pm_set_wow_lps_1t1r(_adapter *padapter, u8 en);
++#endif
++#endif /* CONFIG_WOWLAN */
++
++void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason);
++void rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason);
++u32 rtw_ps_deny_get(PADAPTER padapter);
++
++#if defined(CONFIG_WOWLAN)
++void rtw_get_current_ip_address(PADAPTER padapter, u8 *pcurrentip);
++void rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr);
++bool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern,
++				int *pattern_len, char *bit_mask);
++void rtw_wow_pattern_sw_reset(_adapter *adapter);
++u8 rtw_set_default_pattern(_adapter *adapter);
++void rtw_wow_pattern_sw_dump(_adapter *adapter);
++#endif /* CONFIG_WOWLAN */
++void rtw_ssmps_enter(_adapter *adapter, struct sta_info *sta);
++void rtw_ssmps_leave(_adapter *adapter, struct sta_info *sta);
++#endif /* __RTL871X_PWRCTRL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_qos.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_qos.h
+new file mode 100644
+index 000000000..8e1d013e1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_qos.h
+@@ -0,0 +1,66 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++
++#ifndef _RTW_QOS_H_
++#define _RTW_QOS_H_
++
++#define DRV_CFG_UAPSD_VO 	BIT0
++#define DRV_CFG_UAPSD_VI 	BIT1
++#define DRV_CFG_UAPSD_BK 	BIT2
++#define DRV_CFG_UAPSD_BE 	BIT3
++
++#define WMM_IE_UAPSD_VO 	BIT0
++#define WMM_IE_UAPSD_VI 	BIT1
++#define WMM_IE_UAPSD_BK 	BIT2
++#define WMM_IE_UAPSD_BE 	BIT3
++
++#define WMM_TID0 	BIT0
++#define WMM_TID1 	BIT1
++#define WMM_TID2 	BIT2
++#define WMM_TID3 	BIT3
++#define WMM_TID4 	BIT4
++#define WMM_TID5 	BIT5
++#define WMM_TID6 	BIT6
++#define WMM_TID7 	BIT7
++
++#define AP_SUPPORTED_UAPSD BIT7
++/* TC = Traffic Category,  TID0~7 represents TC */
++#define BIT_MASK_TID_TC 0xff
++/* TS = Traffic Stream,  TID8~15 represents TS */
++#define BIT_MASK_TID_TS 0xff00
++#define ALL_TID_TC_SUPPORTED_UAPSD 0xff
++
++struct	qos_priv	{
++
++	unsigned int	  qos_option;	/* bit mask option: u-apsd, s-apsd, ts, block ack...		 */
++
++#ifdef CONFIG_WMMPS_STA
++	/* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */
++	u8 uapsd_max_sp_len;
++	/* declare uapsd_tid as a bitmap for the uapsd setting of TID 0~15 */
++	u16 uapsd_tid;
++	/* declare uapsd_tid_delivery_enabled as a bitmap for the delivery-enabled setting of TID 0~7 */
++	u8 uapsd_tid_delivery_enabled;
++	/* declare uapsd_tid_trigger_enabled as a bitmap for the trigger-enabled setting of TID 0~7 */
++	u8 uapsd_tid_trigger_enabled;
++	/* declare uapsd_ap_supported to record whether the connected ap  supports uapsd or not */
++	u8 uapsd_ap_supported;
++#endif /* CONFIG_WMMPS_STA */	
++
++};
++
++
++#endif /* _RTL871X_QOS_H_ */
+\ No newline at end of file
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_recv.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_recv.h
+new file mode 100644
+index 000000000..d3b03d7dd
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_recv.h
+@@ -0,0 +1,835 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTW_RECV_H_
++#define _RTW_RECV_H_
++
++#define RTW_RX_MSDU_ACT_NONE		0
++#define RTW_RX_MSDU_ACT_INDICATE	BIT0
++#define RTW_RX_MSDU_ACT_FORWARD		BIT1
++
++#ifdef CONFIG_SINGLE_RECV_BUF
++	#define NR_RECVBUFF (1)
++#else
++	#if defined(CONFIG_GSPI_HCI)
++		#define NR_RECVBUFF (32)
++	#elif defined(CONFIG_SDIO_HCI)
++		#define NR_RECVBUFF (8)
++	#else
++		#define NR_RECVBUFF (8)
++	#endif
++#endif /* CONFIG_SINGLE_RECV_BUF */
++#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
++	#define NR_PREALLOC_RECV_SKB (rtw_rtkm_get_nr_recv_skb()>>1)
++#else /*!CONFIG_PREALLOC_RX_SKB_BUFFER */
++	#define NR_PREALLOC_RECV_SKB 8
++#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
++
++#ifdef CONFIG_RTW_NAPI
++	#define RTL_NAPI_WEIGHT (32)
++#endif
++
++
++#if defined(CONFIG_RTL8821C) && defined(CONFIG_SDIO_HCI) && defined(CONFIG_RECV_THREAD_MODE)
++	#ifdef NR_RECVBUFF
++	#undef NR_RECVBUFF
++	#define NR_RECVBUFF (32)
++	#endif
++#endif
++
++#define NR_RECVFRAME 256
++
++#define RXFRAME_ALIGN	8
++#define RXFRAME_ALIGN_SZ	(1<<RXFRAME_ALIGN)
++
++#define DRVINFO_SZ	4 /* unit is 8bytes */
++
++#define MAX_RXFRAME_CNT	512
++#define MAX_RX_NUMBLKS		(32)
++#define RECVFRAME_HDR_ALIGN 128
++#define MAX_CONTINUAL_NORXPACKET_COUNT 4    /*  In MAX_CONTINUAL_NORXPACKET_COUNT*2 sec  , no rx traffict would issue DELBA*/
++
++#define PHY_RSSI_SLID_WIN_MAX				100
++#define PHY_LINKQUALITY_SLID_WIN_MAX		20
++
++
++#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
++
++#define RX_MPDU_QUEUE				0
++#define RX_CMD_QUEUE				1
++#define RX_MAX_QUEUE				2
++
++#define MAX_SUBFRAME_COUNT	64
++/* Bridge-Tunnel header (for EtherTypes ETH_P_AARP and ETH_P_IPX) */
++extern u8 rtw_bridge_tunnel_header[];
++extern u8 rtw_rfc1042_header[];
++
++enum addba_rsp_ack_state {
++	RTW_RECV_ACK_OR_TIMEOUT,
++};
++
++/* for Rx reordering buffer control */
++struct recv_reorder_ctrl {
++	_adapter	*padapter;
++	u8 tid;
++	u8 enable;
++	u16 indicate_seq;/* =wstart_b, init_value=0xffff */
++	u16 wend_b;
++	u8 wsize_b;
++	u8 ampdu_size;
++	_queue pending_recvframe_queue;
++	_timer reordering_ctrl_timer;
++	u8 bReorderWaiting;
++	unsigned long rec_abba_rsp_ack;
++};
++
++struct	stainfo_rxcache	{
++	u16	tid_rxseq[16];
++	u8 iv[16][8];
++	u8 last_tid;
++#if 0
++	unsigned short	tid0_rxseq;
++	unsigned short	tid1_rxseq;
++	unsigned short	tid2_rxseq;
++	unsigned short	tid3_rxseq;
++	unsigned short	tid4_rxseq;
++	unsigned short	tid5_rxseq;
++	unsigned short	tid6_rxseq;
++	unsigned short	tid7_rxseq;
++	unsigned short	tid8_rxseq;
++	unsigned short	tid9_rxseq;
++	unsigned short	tid10_rxseq;
++	unsigned short	tid11_rxseq;
++	unsigned short	tid12_rxseq;
++	unsigned short	tid13_rxseq;
++	unsigned short	tid14_rxseq;
++	unsigned short	tid15_rxseq;
++#endif
++};
++
++
++struct smooth_rssi_data {
++	u32	elements[100];	/* array to store values */
++	u32	index;			/* index to current array to store */
++	u32	total_num;		/* num of valid elements */
++	u32	total_val;		/* sum of valid elements */
++};
++
++struct signal_stat {
++	u8	update_req;		/* used to indicate */
++	u8	avg_val;		/* avg of valid elements */
++	u32	total_num;		/* num of valid elements */
++	u32	total_val;		/* sum of valid elements	 */
++};
++
++struct rx_raw_rssi {
++	u8 data_rate;
++	u8 pwdball;
++	s8 pwr_all;
++
++	u8 mimo_signal_strength[4];/* in 0~100 index */
++	u8 mimo_signal_quality[4];
++
++	s8 ofdm_pwr[4];
++	u8 ofdm_snr[4];
++};
++
++
++#include "cmn_info/rtw_sta_info.h"
++
++struct rx_pkt_attrib	{
++	u16	pkt_len;
++	u8	physt;
++	u8	drvinfo_sz;
++	u8	shift_sz;
++	u8	hdrlen; /* the WLAN Header Len */
++	u8	to_fr_ds;
++	u8	amsdu;
++	u8	qos;
++	u8	priority;
++	u8	pw_save;
++	u8	mdata;
++	u16	seq_num;
++	u8	frag_num;
++	u8	mfrag;
++	u8	order;
++	u8	privacy; /* in frame_ctrl field */
++	u8	bdecrypted;
++	u8	encrypt; /* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */
++	u8	iv_len;
++	u8	icv_len;
++	u8	crc_err;
++	u8	icv_err;
++
++	u8	dst[ETH_ALEN];
++	u8	src[ETH_ALEN];
++	u8	ta[ETH_ALEN];
++	u8	ra[ETH_ALEN];
++	u8	bssid[ETH_ALEN];
++#ifdef CONFIG_RTW_MESH
++	u8	msa[ETH_ALEN]; /* mesh sa */
++	u8	mda[ETH_ALEN]; /* mesh da */
++	u8 mesh_ctrl_present;
++	u8	mesh_ctrl_len; /* length of mesh control field */
++#endif
++
++	u8	ack_policy;
++
++	u8	key_index;
++
++	u8	data_rate;
++	u8 ch; /* RX channel */
++	u8	bw;
++	u8	stbc;
++	u8	ldpc;
++	u8	sgi;
++	u8	pkt_rpt_type;
++	u32	MacIDValidEntry[2];	/* 64 bits present 64 entry. */
++	u8	ampdu;
++	u8	ppdu_cnt;
++	u8	ampdu_eof;
++	u32 	free_cnt;		/* free run counter */
++	struct phydm_phyinfo_struct phy_info;
++#ifdef CONFIG_WIFI_MONITOR
++	u8 moif[16];
++#endif
++
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
++	/* checksum offload realted varaiables */
++	u8 csum_valid;		/* Checksum valid, 0: not check, 1: checked */
++	u8 csum_err;		/* Checksum Error occurs */
++#endif /* CONFIG_TCP_CSUM_OFFLOAD_RX */
++};
++
++#ifdef CONFIG_RTW_MESH
++#define RATTRIB_GET_MCTRL_LEN(rattrib) ((rattrib)->mesh_ctrl_len)
++#else
++#define RATTRIB_GET_MCTRL_LEN(rattrib) 0
++#endif
++
++/* These definition is used for Rx packet reordering. */
++#define SN_LESS(a, b)		(((a-b) & 0x800) != 0)
++#define SN_EQUAL(a, b)	(a == b)
++/* #define REORDER_WIN_SIZE	128 */
++/* #define REORDER_ENTRY_NUM	128 */
++#define REORDER_WAIT_TIME	(50) /* (ms) */
++
++#if defined(CONFIG_PLATFORM_RTK390X) && defined(CONFIG_USB_HCI)
++	#define RECVBUFF_ALIGN_SZ 32
++#else
++	#define RECVBUFF_ALIGN_SZ 8
++#endif
++
++#ifdef CONFIG_TRX_BD_ARCH
++	#define RX_WIFI_INFO_SIZE	24
++#elif (defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)) && defined(CONFIG_PCI_HCI)
++	#define RXBD_SIZE	sizeof(struct recv_stat)
++#endif
++
++#define RXDESC_SIZE	24
++#define RXDESC_OFFSET RXDESC_SIZE
++
++#ifdef CONFIG_TRX_BD_ARCH
++struct rx_buf_desc {
++	/* RX has exactly one segment */
++#ifdef CONFIG_64BIT_DMA
++	unsigned int dword[4];
++#else
++	unsigned int dword[2];
++#endif
++};
++
++struct recv_stat {
++	unsigned int rxdw[8];
++};
++#else
++struct recv_stat {
++	unsigned int rxdw0;
++
++	unsigned int rxdw1;
++
++#if !((defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)) && defined(CONFIG_PCI_HCI))  /* exclude 8192ee, 8814ae, 8822be, 8821ce */
++	unsigned int rxdw2;
++
++	unsigned int rxdw3;
++#endif
++
++#ifndef BUF_DESC_ARCH
++	unsigned int rxdw4;
++
++	unsigned int rxdw5;
++
++#ifdef CONFIG_PCI_HCI
++	unsigned int rxdw6;
++
++	unsigned int rxdw7;
++#endif
++#endif /* if BUF_DESC_ARCH is defined, rx_buf_desc occupy 4 double words */
++};
++#endif
++
++#define EOR BIT(30)
++
++#ifdef CONFIG_PCI_HCI
++#define PCI_MAX_RX_QUEUE		1/* MSDU packet queue, Rx Command Queue */
++#define PCI_MAX_RX_COUNT		128
++#ifdef CONFIG_TRX_BD_ARCH
++#define RX_BD_NUM				PCI_MAX_RX_COUNT	/* alias */
++#endif
++
++struct rtw_rx_ring {
++#ifdef CONFIG_TRX_BD_ARCH
++	struct rx_buf_desc	*buf_desc;
++#else
++	struct recv_stat	*desc;
++#endif
++	dma_addr_t		dma;
++	unsigned int		idx;
++	struct sk_buff	*rx_buf[PCI_MAX_RX_COUNT];
++};
++#endif
++
++
++
++/*
++accesser of recv_priv: rtw_recv_entry(dispatch / passive level); recv_thread(passive) ; returnpkt(dispatch)
++; halt(passive) ;
++
++using enter_critical section to protect
++*/
++
++#ifndef DBG_RX_BH_TRACKING
++#define DBG_RX_BH_TRACKING 0
++#endif
++
++struct recv_priv {
++	_lock	lock;
++
++#ifdef CONFIG_RECV_THREAD_MODE
++	_sema	recv_sema;
++
++#endif
++
++	/* _queue	blk_strms[MAX_RX_NUMBLKS];    */ /* keeping the block ack frame until return ack */
++	_queue	free_recv_queue;
++	_queue	recv_pending_queue;
++	_queue	uc_swdec_pending_queue;
++
++
++	u8 *pallocated_frame_buf;
++	u8 *precv_frame_buf;
++
++	uint free_recvframe_cnt;
++
++	#if DBG_RX_BH_TRACKING
++	u32 rx_bh_stage;
++	u32 rx_bh_buf_dq_cnt;
++	void *rx_bh_lbuf;
++	void *rx_bh_cbuf;
++	void *rx_bh_cbuf_data;
++	u32 rx_bh_cbuf_dlen;
++	u32 rx_bh_cbuf_pos;
++	void *rx_bh_cframe;
++	#endif
++
++	_adapter	*adapter;
++
++	u32 is_any_non_be_pkts;
++
++	u64	rx_bytes;
++	u64	rx_pkts;
++	u64	rx_drop;
++
++	u64 dbg_rx_drop_count;
++	u64 dbg_rx_ampdu_drop_count;
++	u64 dbg_rx_ampdu_forced_indicate_count;
++	u64 dbg_rx_ampdu_loss_count;
++	u64 dbg_rx_dup_mgt_frame_drop_count;
++	u64 dbg_rx_ampdu_window_shift_cnt;
++	u64 dbg_rx_conflic_mac_addr_cnt;
++
++	uint  rx_icv_err;
++	uint  rx_largepacket_crcerr;
++	uint  rx_smallpacket_crcerr;
++	uint  rx_middlepacket_crcerr;
++
++#ifdef CONFIG_USB_HCI
++	/* u8 *pallocated_urb_buf; */
++	_sema allrxreturnevt;
++	uint	ff_hwaddr;
++	ATOMIC_T	rx_pending_cnt;
++
++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
++#ifdef PLATFORM_LINUX
++	PURB	int_in_urb;
++#endif
++
++	u8	*int_in_buf;
++#endif /* CONFIG_USB_INTERRUPT_IN_PIPE */
++
++#endif
++#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
++	_tasklet irq_prepare_beacon_tasklet;
++	_tasklet recv_tasklet;
++
++	struct sk_buff_head free_recv_skb_queue;
++	struct sk_buff_head rx_skb_queue;
++#ifdef CONFIG_RTW_NAPI
++		struct sk_buff_head rx_napi_skb_queue;
++#endif 
++#ifdef CONFIG_RX_INDICATE_QUEUE
++	_tasklet rx_indicate_tasklet;
++	struct ifqueue rx_indicate_queue;
++#endif /* CONFIG_RX_INDICATE_QUEUE */
++
++#endif /* defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD) */
++
++	u8 *pallocated_recv_buf;
++	u8 *precv_buf;    /* 4 alignment */
++	_queue	free_recv_buf_queue;
++	u32	free_recv_buf_queue_cnt;
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_USB_HCI)
++	_queue	recv_buf_pending_queue;
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	/* Rx */
++	struct rtw_rx_ring	rx_ring[PCI_MAX_RX_QUEUE];
++	int rxringcount;	/* size should be PCI_MAX_RX_QUEUE */
++	u32	rxbuffersize;
++#endif
++
++	/* For display the phy informatiom */
++	u8 is_signal_dbg;	/* for debug */
++	u8 signal_strength_dbg;	/* for debug */
++
++	u8 signal_strength;
++	u8 signal_qual;
++	s8 rssi;	/* translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength); */
++	struct rx_raw_rssi raw_rssi_info;
++	/* s8 rxpwdb;	 */
++	/* int RxSNRdB[2]; */
++	/* s8 RxRssi[2]; */
++	/* int FalseAlmCnt_all; */
++
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++	_timer signal_stat_timer;
++	u32 signal_stat_sampling_interval;
++	/* u32 signal_stat_converging_constant; */
++	struct signal_stat signal_qual_data;
++	struct signal_stat signal_strength_data;
++#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
++	struct smooth_rssi_data signal_qual_data;
++	struct smooth_rssi_data signal_strength_data;
++#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
++	u16 sink_udpport, pre_rtp_rxseq, cur_rtp_rxseq;
++
++	BOOLEAN store_law_data_flag;
++};
++
++#define RX_BH_STG_UNKNOWN		0
++#define RX_BH_STG_HDL_ENTER		1
++#define RX_BH_STG_HDL_EXIT		2
++#define RX_BH_STG_NEW_BUF		3
++#define RX_BH_STG_NEW_FRAME		4
++#define RX_BH_STG_NORMAL_RX		5
++#define RX_BH_STG_NORMAL_RX_END	6
++#define RX_BH_STG_C2H			7
++#define RX_BH_STG_C2H_END		8
++
++#if DBG_RX_BH_TRACKING
++void rx_bh_tk_set_stage(struct recv_priv *recv, u32 s);
++void rx_bh_tk_set_buf(struct recv_priv *recv, void *buf, void *data, u32 dlen);
++void rx_bh_tk_set_buf_pos(struct recv_priv *recv, void *pos);
++void rx_bh_tk_set_frame(struct recv_priv *recv, void *frame);
++void dump_rx_bh_tk(void *sel, struct recv_priv *recv);
++#else
++#define rx_bh_tk_set_stage(recv, s) do {} while (0)
++#define rx_bh_tk_set_buf(recv, buf, data, dlen) do {} while (0)
++#define rx_bh_tk_set_buf_pos(recv, pos) do {} while (0)
++#define rx_bh_tk_set_frame(recv, frame) do {} while (0)
++#define dump_rx_bh_tk(sel, recv) do {} while (0)
++#endif
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++#define rtw_set_signal_stat_timer(recvpriv) _set_timer(&(recvpriv)->signal_stat_timer, (recvpriv)->signal_stat_sampling_interval)
++#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
++
++struct sta_recv_priv {
++
++	_lock	lock;
++	sint	option;
++
++	/* _queue	blk_strms[MAX_RX_NUMBLKS]; */
++	_queue defrag_q;	 /* keeping the fragment frame until defrag */
++
++	struct	stainfo_rxcache rxcache;
++	u16	bmc_tid_rxseq[16];
++	u16	nonqos_rxseq;
++	u16	nonqos_bmc_rxseq;
++
++	/* uint	sta_rx_bytes; */
++	/* uint	sta_rx_pkts; */
++	/* uint	sta_rx_fail; */
++
++};
++
++
++struct recv_buf {
++	_list list;
++
++	_lock recvbuf_lock;
++
++	u32	ref_cnt;
++
++	PADAPTER adapter;
++
++	u8	*pbuf;
++	u8	*pallocated_buf;
++
++	u32	len;
++	u8	*phead;
++	u8	*pdata;
++	u8	*ptail;
++	u8	*pend;
++
++#ifdef CONFIG_USB_HCI
++	PURB	purb;
++	dma_addr_t dma_transfer_addr;	/* (in) dma addr for transfer_buffer */
++	u32 alloc_sz;
++
++	u8  irp_pending;
++	int  transfer_len;
++#endif
++
++#if defined(PLATFORM_LINUX)
++	_pkt *pskb;
++#elif defined(PLATFORM_FREEBSD) /* skb solution */
++	struct sk_buff *pskb;
++#endif
++};
++
++
++/*
++	head  ----->
++
++		data  ----->
++
++			payload
++
++		tail  ----->
++
++
++	end   ----->
++
++	len = (unsigned int )(tail - data);
++
++*/
++struct recv_frame_hdr {
++	_list	list;
++	_pkt *pkt;
++
++	_adapter  *adapter;
++
++	u8 fragcnt;
++
++	int frame_tag;
++
++	struct rx_pkt_attrib attrib;
++
++	uint  len;
++	u8 *rx_head;
++	u8 *rx_data;
++	u8 *rx_tail;
++	u8 *rx_end;
++
++	void *precvbuf;
++
++
++	/*  */
++	struct sta_info *psta;
++
++	/* for A-MPDU Rx reordering buffer control */
++	struct recv_reorder_ctrl *preorder_ctrl;
++
++#ifdef CONFIG_WAPI_SUPPORT
++	u8 UserPriority;
++	u8 WapiTempPN[16];
++	u8 WapiSrcAddr[6];
++	u8 bWapiCheckPNInDecrypt;
++	u8 bIsWaiPacket;
++#endif
++
++};
++
++
++union recv_frame {
++
++	union {
++		_list list;
++		struct recv_frame_hdr hdr;
++		uint mem[RECVFRAME_HDR_ALIGN >> 2];
++	} u;
++
++	/* uint mem[MAX_RXSZ>>2]; */
++
++};
++
++enum rtw_rx_llc_hdl {
++	RTW_RX_LLC_KEEP		= 0,
++	RTW_RX_LLC_REMOVE	= 1,
++	RTW_RX_LLC_VLAN		= 2,
++};
++
++bool rtw_rframe_del_wfd_ie(union recv_frame *rframe, u8 ies_offset);
++
++typedef enum _RX_PACKET_TYPE {
++	NORMAL_RX,/* Normal rx packet */
++	TX_REPORT1,/* CCX */
++	TX_REPORT2,/* TX RPT */
++	HIS_REPORT,/* USB HISR RPT */
++	C2H_PACKET
++} RX_PACKET_TYPE, *PRX_PACKET_TYPE;
++
++extern union recv_frame *_rtw_alloc_recvframe(_queue *pfree_recv_queue);   /* get a free recv_frame from pfree_recv_queue */
++extern union recv_frame *rtw_alloc_recvframe(_queue *pfree_recv_queue);   /* get a free recv_frame from pfree_recv_queue */
++extern void rtw_init_recvframe(union recv_frame *precvframe , struct recv_priv *precvpriv);
++extern int	 rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue);
++
++#define rtw_dequeue_recvframe(queue) rtw_alloc_recvframe(queue)
++extern int _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue);
++extern int rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue);
++
++extern void rtw_free_recvframe_queue(_queue *pframequeue,  _queue *pfree_recv_queue);
++u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter);
++
++sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue);
++sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue);
++struct recv_buf *rtw_dequeue_recvbuf(_queue *queue);
++
++void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta);
++void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta);
++
++#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
++void rtw_reordering_ctrl_timeout_handler(void *pcontext);
++#endif
++
++void rx_query_phy_status(union recv_frame *rframe, u8 *phy_stat);
++int rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index);
++void rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index);
++
++#ifdef CONFIG_RECV_THREAD_MODE
++thread_return rtw_recv_thread(thread_context context);
++#endif
++
++__inline static u8 *get_rxmem(union recv_frame *precvframe)
++{
++	/* always return rx_head... */
++	if (precvframe == NULL)
++		return NULL;
++
++	return precvframe->u.hdr.rx_head;
++}
++
++__inline static u8 *get_rx_status(union recv_frame *precvframe)
++{
++
++	return get_rxmem(precvframe);
++
++}
++
++__inline static u8 *get_recvframe_data(union recv_frame *precvframe)
++{
++
++	/* alwasy return rx_data */
++	if (precvframe == NULL)
++		return NULL;
++
++	return precvframe->u.hdr.rx_data;
++
++}
++
++__inline static u8 *recvframe_push(union recv_frame *precvframe, sint sz)
++{
++	/* append data before rx_data */
++
++	/* add data to the start of recv_frame
++	*
++	*      This function extends the used data area of the recv_frame at the buffer
++	*      start. rx_data must be still larger than rx_head, after pushing.
++	*/
++
++	if (precvframe == NULL)
++		return NULL;
++
++
++	precvframe->u.hdr.rx_data -= sz ;
++	if (precvframe->u.hdr.rx_data < precvframe->u.hdr.rx_head) {
++		precvframe->u.hdr.rx_data += sz ;
++		return NULL;
++	}
++
++	precvframe->u.hdr.len += sz;
++
++	return precvframe->u.hdr.rx_data;
++
++}
++
++
++__inline static u8 *recvframe_pull(union recv_frame *precvframe, sint sz)
++{
++	/* rx_data += sz; move rx_data sz bytes  hereafter */
++
++	/* used for extract sz bytes from rx_data, update rx_data and return the updated rx_data to the caller */
++
++
++	if (precvframe == NULL)
++		return NULL;
++
++
++	precvframe->u.hdr.rx_data += sz;
++
++	if (precvframe->u.hdr.rx_data > precvframe->u.hdr.rx_tail) {
++		precvframe->u.hdr.rx_data -= sz;
++		return NULL;
++	}
++
++	precvframe->u.hdr.len -= sz;
++
++	return precvframe->u.hdr.rx_data;
++
++}
++
++__inline static u8 *recvframe_put(union recv_frame *precvframe, sint sz)
++{
++	/* rx_tai += sz; move rx_tail sz bytes  hereafter */
++
++	/* used for append sz bytes from ptr to rx_tail, update rx_tail and return the updated rx_tail to the caller */
++	/* after putting, rx_tail must be still larger than rx_end. */
++	unsigned char *prev_rx_tail;
++
++	/* RTW_INFO("recvframe_put: len=%d\n", sz); */
++
++	if (precvframe == NULL)
++		return NULL;
++
++	prev_rx_tail = precvframe->u.hdr.rx_tail;
++
++	precvframe->u.hdr.rx_tail += sz;
++
++	if (precvframe->u.hdr.rx_tail > precvframe->u.hdr.rx_end) {
++		precvframe->u.hdr.rx_tail -= sz;
++		return NULL;
++	}
++
++	precvframe->u.hdr.len += sz;
++
++	return precvframe->u.hdr.rx_tail;
++
++}
++
++
++
++__inline static u8 *recvframe_pull_tail(union recv_frame *precvframe, sint sz)
++{
++	/* rmv data from rx_tail (by yitsen) */
++
++	/* used for extract sz bytes from rx_end, update rx_end and return the updated rx_end to the caller */
++	/* after pulling, rx_end must be still larger than rx_data. */
++
++	if (precvframe == NULL)
++		return NULL;
++
++	precvframe->u.hdr.rx_tail -= sz;
++
++	if (precvframe->u.hdr.rx_tail < precvframe->u.hdr.rx_data) {
++		precvframe->u.hdr.rx_tail += sz;
++		return NULL;
++	}
++
++	precvframe->u.hdr.len -= sz;
++
++	return precvframe->u.hdr.rx_tail;
++
++}
++
++__inline static union recv_frame *rxmem_to_recvframe(u8 *rxmem)
++{
++	/* due to the design of 2048 bytes alignment of recv_frame, we can reference the union recv_frame */
++	/* from any given member of recv_frame. */
++	/* rxmem indicates the any member/address in recv_frame */
++
++	return (union recv_frame *)(((SIZE_PTR)rxmem >> RXFRAME_ALIGN) << RXFRAME_ALIGN);
++
++}
++
++__inline static union recv_frame *pkt_to_recvframe(_pkt *pkt)
++{
++
++	u8 *buf_star;
++	union recv_frame *precv_frame;
++	precv_frame = rxmem_to_recvframe((unsigned char *)buf_star);
++
++	return precv_frame;
++}
++
++__inline static u8 *pkt_to_recvmem(_pkt *pkt)
++{
++	/* return the rx_head */
++
++	union recv_frame *precv_frame = pkt_to_recvframe(pkt);
++
++	return	precv_frame->u.hdr.rx_head;
++
++}
++
++__inline static u8 *pkt_to_recvdata(_pkt *pkt)
++{
++	/* return the rx_data */
++
++	union recv_frame *precv_frame = pkt_to_recvframe(pkt);
++
++	return	precv_frame->u.hdr.rx_data;
++
++}
++
++
++__inline static sint get_recvframe_len(union recv_frame *precvframe)
++{
++	return precvframe->u.hdr.len;
++}
++
++
++__inline static s32 translate_percentage_to_dbm(u32 SignalStrengthIndex)
++{
++	s32	SignalPower; /* in dBm. */
++
++	/* Translate to dBm (x=y-100) */
++	SignalPower = SignalStrengthIndex - 100;
++	return SignalPower;
++}
++
++struct sta_info;
++
++extern void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv);
++
++extern void  mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame);
++
++u8 adapter_allow_bmc_data_rx(_adapter *adapter);
++s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status);
++void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_rf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_rf.h
+new file mode 100644
+index 000000000..999a91872
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_rf.h
+@@ -0,0 +1,306 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef	__RTW_RF_H_
++#define __RTW_RF_H_
++
++#define NumRates	(13)
++#define	B_MODE_RATE_NUM	(4)
++#define	G_MODE_RATE_NUM	(8)
++#define	G_MODE_BASIC_RATE_NUM	(3)
++/* slot time for 11g */
++#define SHORT_SLOT_TIME					9
++#define NON_SHORT_SLOT_TIME				20
++
++#define CENTER_CH_2G_40M_NUM	9
++#define CENTER_CH_2G_NUM		14
++#define CENTER_CH_5G_20M_NUM	28	/* 20M center channels */
++#define CENTER_CH_5G_40M_NUM	14	/* 40M center channels */
++#define CENTER_CH_5G_80M_NUM	7	/* 80M center channels */
++#define CENTER_CH_5G_160M_NUM	3	/* 160M center channels */
++#define CENTER_CH_5G_ALL_NUM	(CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM + CENTER_CH_5G_80M_NUM)
++
++#define	MAX_CHANNEL_NUM_2G	CENTER_CH_2G_NUM
++#define	MAX_CHANNEL_NUM_5G	CENTER_CH_5G_20M_NUM
++#define	MAX_CHANNEL_NUM		(MAX_CHANNEL_NUM_2G + MAX_CHANNEL_NUM_5G)
++
++extern u8 center_ch_2g[CENTER_CH_2G_NUM];
++extern u8 center_ch_2g_40m[CENTER_CH_2G_40M_NUM];
++
++u8 center_chs_2g_num(u8 bw);
++u8 center_chs_2g(u8 bw, u8 id);
++
++extern u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM];
++extern u8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM];
++extern u8 center_ch_5g_20m_40m[CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM];
++extern u8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM];
++extern u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM];
++
++u8 center_chs_5g_num(u8 bw);
++u8 center_chs_5g(u8 bw, u8 id);
++
++u8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset);
++u8 rtw_get_scch_by_cch_opch(u8 cch, u8 bw, u8 opch);
++
++u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num);
++
++u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset);
++u8 rtw_get_center_ch(u8 ch, u8 bw, u8 offset);
++
++u8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group);
++
++typedef enum _CAPABILITY {
++	cESS			= 0x0001,
++	cIBSS			= 0x0002,
++	cPollable		= 0x0004,
++	cPollReq			= 0x0008,
++	cPrivacy		= 0x0010,
++	cShortPreamble	= 0x0020,
++	cPBCC			= 0x0040,
++	cChannelAgility	= 0x0080,
++	cSpectrumMgnt	= 0x0100,
++	cQos			= 0x0200,	/* For HCCA, use with CF-Pollable and CF-PollReq */
++	cShortSlotTime	= 0x0400,
++	cAPSD			= 0x0800,
++	cRM				= 0x1000,	/* RRM (Radio Request Measurement) */
++	cDSSS_OFDM	= 0x2000,
++	cDelayedBA		= 0x4000,
++	cImmediateBA	= 0x8000,
++} CAPABILITY, *PCAPABILITY;
++
++enum	_REG_PREAMBLE_MODE {
++	PREAMBLE_LONG	= 1,
++	PREAMBLE_AUTO	= 2,
++	PREAMBLE_SHORT	= 3,
++};
++
++#define rf_path_char(path) (((path) >= RF_PATH_MAX) ? 'X' : 'A' + (path))
++
++/* Bandwidth Offset */
++#define HAL_PRIME_CHNL_OFFSET_DONT_CARE	0
++#define HAL_PRIME_CHNL_OFFSET_LOWER	1
++#define HAL_PRIME_CHNL_OFFSET_UPPER	2
++
++typedef enum _BAND_TYPE {
++	BAND_ON_2_4G = 0,
++	BAND_ON_5G = 1,
++	BAND_MAX,
++} BAND_TYPE, *PBAND_TYPE;
++
++#ifdef CONFIG_NARROWBAND_SUPPORTING
++enum nb_config {
++	RTW_NB_CONFIG_NONE		= 0,
++	RTW_NB_CONFIG_WIDTH_5	= 5,
++	RTW_NB_CONFIG_WIDTH_10	= 6,
++};
++#endif
++
++extern const char *const _band_str[];
++#define band_str(band) (((band) >= BAND_MAX) ? _band_str[BAND_MAX] : _band_str[(band)])
++
++extern const u8 _band_to_band_cap[];
++#define band_to_band_cap(band) (((band) >= BAND_MAX) ? _band_to_band_cap[BAND_MAX] : _band_to_band_cap[(band)])
++
++
++extern const char *const _ch_width_str[];
++#define ch_width_str(bw) (((bw) < CHANNEL_WIDTH_MAX) ? _ch_width_str[(bw)] : "CHANNEL_WIDTH_MAX")
++
++extern const u8 _ch_width_to_bw_cap[];
++#define ch_width_to_bw_cap(bw) (((bw) < CHANNEL_WIDTH_MAX) ? _ch_width_to_bw_cap[(bw)] : 0)
++
++enum opc_bw {
++	OPC_BW20		= 0,
++	OPC_BW40PLUS	= 1,
++	OPC_BW40MINUS	= 2,
++	OPC_BW80		= 3,
++	OPC_BW160		= 4,
++	OPC_BW80P80		= 5,
++	OPC_BW_NUM,
++};
++
++extern const char *const _opc_bw_str[OPC_BW_NUM];
++#define opc_bw_str(bw) (((bw) < OPC_BW_NUM) ? _opc_bw_str[(bw)] : "N/A")
++
++extern const u8 _opc_bw_to_ch_width[OPC_BW_NUM];
++#define opc_bw_to_ch_width(bw) (((bw) < OPC_BW_NUM) ? _opc_bw_to_ch_width[(bw)] : CHANNEL_WIDTH_MAX)
++
++struct op_class_map {
++	u8 op_class;
++	BAND_TYPE band;
++	enum opc_bw bw;
++	u32 ch_bmp;
++};
++
++#define RTW_GLOBAL_OP_CLASS_NUM 19
++
++void dump_global_op_class(void *sel);
++
++u8 rtw_get_op_class_by_chbw(u8 ch, u8 bw, u8 offset);
++u8 rtw_get_bw_offset_by_op_class_ch(u8 op_class, u8 ch, u8 *bw, u8 *offset);
++
++struct _RT_CHANNEL_INFO;
++u8 init_op_class_ch_bmp(_adapter *adapter, struct _RT_CHANNEL_INFO *chset, u32 op_class_ch_bmp[]);
++struct rf_ctl_t;
++void dump_cap_spt_op_class_ch(void *sel, struct rf_ctl_t *rfctl, bool negtive);
++void dump_cur_spt_op_class_ch(void *sel, struct rf_ctl_t *rfctl, bool negtive);
++
++/*
++ * Represent Extention Channel Offset in HT Capabilities
++ * This is available only in 40Mhz mode.
++ *   */
++typedef enum _EXTCHNL_OFFSET {
++	EXTCHNL_OFFSET_NO_EXT = 0,
++	EXTCHNL_OFFSET_UPPER = 1,
++	EXTCHNL_OFFSET_NO_DEF = 2,
++	EXTCHNL_OFFSET_LOWER = 3,
++} EXTCHNL_OFFSET, *PEXTCHNL_OFFSET;
++
++typedef enum _VHT_DATA_SC {
++	VHT_DATA_SC_DONOT_CARE = 0,
++	VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
++	VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
++	VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
++	VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
++	VHT_DATA_SC_20_RECV1 = 5,
++	VHT_DATA_SC_20_RECV2 = 6,
++	VHT_DATA_SC_20_RECV3 = 7,
++	VHT_DATA_SC_20_RECV4 = 8,
++	VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
++	VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
++} VHT_DATA_SC, *PVHT_DATA_SC_E;
++
++typedef enum _PROTECTION_MODE {
++	PROTECTION_MODE_AUTO = 0,
++	PROTECTION_MODE_FORCE_ENABLE = 1,
++	PROTECTION_MODE_FORCE_DISABLE = 2,
++} PROTECTION_MODE, *PPROTECTION_MODE;
++
++#define RF_TYPE_VALID(rf_type) (rf_type < RF_TYPE_MAX)
++
++extern const u8 _rf_type_to_rf_tx_cnt[];
++#define rf_type_to_rf_tx_cnt(rf_type) (RF_TYPE_VALID(rf_type) ? _rf_type_to_rf_tx_cnt[rf_type] : 0)
++
++extern const u8 _rf_type_to_rf_rx_cnt[];
++#define rf_type_to_rf_rx_cnt(rf_type) (RF_TYPE_VALID(rf_type) ? _rf_type_to_rf_rx_cnt[rf_type] : 0)
++
++extern const char *const _rf_type_to_rfpath_str[];
++#define rf_type_to_rfpath_str(rf_type) (RF_TYPE_VALID(rf_type) ? _rf_type_to_rfpath_str[rf_type] : "UNKNOWN")
++
++void rf_type_to_default_trx_bmp(enum rf_type rf, enum bb_path *tx, enum bb_path *rx);
++
++enum rf_type trx_num_to_rf_type(u8 tx_num, u8 rx_num);
++enum rf_type trx_bmp_to_rf_type(u8 tx_bmp, u8 rx_bmp);
++bool rf_type_is_a_in_b(enum rf_type a, enum rf_type b);
++u8 rtw_restrict_trx_path_bmp_by_trx_num_lmt(u8 trx_path_bmp, u8 tx_num_lmt, u8 rx_num_lmt, u8 *tx_num, u8 *rx_num);
++u8 rtw_restrict_trx_path_bmp_by_rftype(u8 trx_path_bmp, enum rf_type type, u8 *tx_num, u8 *rx_num);
++void tx_path_nss_set_default(enum bb_path txpath_nss[], u8 txpath_num_nss[], u8 txpath);
++void tx_path_nss_set_full_tx(enum bb_path txpath_nss[], u8 txpath_num_nss[], u8 txpath);
++
++int rtw_ch2freq(int chan);
++int rtw_freq2ch(int freq);
++bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo);
++
++struct rf_ctl_t;
++
++typedef enum _REGULATION_TXPWR_LMT {
++	TXPWR_LMT_NONE = 0, /* no limit */
++	TXPWR_LMT_FCC = 1,
++	TXPWR_LMT_MKK = 2,
++	TXPWR_LMT_ETSI = 3,
++	TXPWR_LMT_IC = 4,
++	TXPWR_LMT_KCC = 5,
++	TXPWR_LMT_ACMA = 6,
++	TXPWR_LMT_CHILE = 7,
++	TXPWR_LMT_UKRAINE = 8,
++	TXPWR_LMT_MEXICO = 9,
++	TXPWR_LMT_CN = 10,
++	TXPWR_LMT_WW, /* smallest of all available limit, keep last */
++} REGULATION_TXPWR_LMT;
++
++extern const char *const _regd_str[];
++#define regd_str(regd) (((regd) > TXPWR_LMT_WW) ? _regd_str[TXPWR_LMT_WW] : _regd_str[(regd)])
++
++void txpwr_idx_get_dbm_str(s8 idx, u8 txgi_max, u8 txgi_pdbm, SIZE_T cwidth, char dbm_str[], u8 dbm_str_len);
++
++#define MBM_PDBM 100
++#define UNSPECIFIED_MBM 32767 /* maximum of s16 */
++
++void txpwr_mbm_get_dbm_str(s16 mbm, SIZE_T cwidth, char dbm_str[], u8 dbm_str_len);
++s16 mb_of_ntx(u8 ntx);
++
++#if CONFIG_TXPWR_LIMIT
++struct regd_exc_ent {
++	_list list;
++	char country[2];
++	u8 domain;
++	char regd_name[0];
++};
++
++void dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl);
++void rtw_regd_exc_add_with_nlen(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name, u32 nlen);
++void rtw_regd_exc_add(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name);
++struct regd_exc_ent *_rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain);
++struct regd_exc_ent *rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain);
++void rtw_regd_exc_list_free(struct rf_ctl_t *rfctl);
++
++void dump_txpwr_lmt(void *sel, _adapter *adapter);
++void rtw_txpwr_lmt_add_with_nlen(struct rf_ctl_t *rfctl, const char *regd_name, u32 nlen
++	, u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt);
++void rtw_txpwr_lmt_add(struct rf_ctl_t *rfctl, const char *regd_name
++	, u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt);
++struct txpwr_lmt_ent *_rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name);
++struct txpwr_lmt_ent *rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name);
++void rtw_txpwr_lmt_list_free(struct rf_ctl_t *rfctl);
++#endif /* CONFIG_TXPWR_LIMIT */
++
++#define BB_GAIN_2G 0
++#if CONFIG_IEEE80211_BAND_5GHZ
++#define BB_GAIN_5GLB1 1
++#define BB_GAIN_5GLB2 2
++#define BB_GAIN_5GMB1 3
++#define BB_GAIN_5GMB2 4
++#define BB_GAIN_5GHB 5
++#endif
++
++#if CONFIG_IEEE80211_BAND_5GHZ
++#define BB_GAIN_NUM 6
++#else
++#define BB_GAIN_NUM 1
++#endif
++
++int rtw_ch_to_bb_gain_sel(int ch);
++void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset);
++void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch);
++
++/* only check channel ranges */
++#define rtw_is_2g_ch(ch) (ch >= 1 && ch <= 14)
++#define rtw_is_5g_ch(ch) ((ch) >= 36 && (ch) <= 177)
++#define rtw_is_same_band(a, b) \
++	((rtw_is_2g_ch(a) && rtw_is_2g_ch(b)) \
++	|| (rtw_is_5g_ch(a) && rtw_is_5g_ch(b)))
++
++#define rtw_is_5g_band1(ch) ((ch) >= 36 && (ch) <= 48)
++#define rtw_is_5g_band2(ch) ((ch) >= 52 && (ch) <= 64)
++#define rtw_is_5g_band3(ch) ((ch) >= 100 && (ch) <= 144)
++#define rtw_is_5g_band4(ch) ((ch) >= 149 && (ch) <= 177)
++#define rtw_is_same_5g_band(a, b) \
++	((rtw_is_5g_band1(a) && rtw_is_5g_band1(b)) \
++	|| (rtw_is_5g_band2(a) && rtw_is_5g_band2(b)) \
++	|| (rtw_is_5g_band3(a) && rtw_is_5g_band3(b)) \
++	|| (rtw_is_5g_band4(a) && rtw_is_5g_band4(b)))
++
++bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region);
++bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region);
++
++#endif /* _RTL8711_RF_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_rm.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_rm.h
+new file mode 100644
+index 000000000..9efcf1307
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_rm.h
+@@ -0,0 +1,88 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __RTW_RM_H_
++#define __RTW_RM_H_
++
++u8 rm_post_event_hdl(_adapter *padapter, u8 *pbuf);
++
++#define RM_TIMER_NUM 		32
++#define RM_ALL_MEAS		BIT(1)
++#define RM_ID_FOR_ALL(aid)	((aid<<16)|RM_ALL_MEAS)
++
++#define RM_CAP_ARG(x) ((u8 *)(x))[4], ((u8 *)(x))[3], ((u8 *)(x))[2], ((u8 *)(x))[1], ((u8 *)(x))[0]
++#define RM_CAP_FMT "%02x %02x%02x %02x%02x"
++
++/* remember to modify rm_event_name() when adding new event */
++enum RM_EV_ID {
++	RM_EV_state_in,
++	RM_EV_busy_timer_expire,
++	RM_EV_delay_timer_expire,
++	RM_EV_meas_timer_expire,
++	RM_EV_retry_timer_expire,
++	RM_EV_repeat_delay_expire,
++	RM_EV_request_timer_expire,
++	RM_EV_wait_report,
++	RM_EV_start_meas,
++	RM_EV_survey_done,
++	RM_EV_recv_rep,
++	RM_EV_cancel,
++	RM_EV_state_out,
++	RM_EV_max
++};
++
++struct rm_event {
++	u32 rmid;
++	enum RM_EV_ID evid;
++	_list list;
++};
++
++#ifdef CONFIG_RTW_80211K
++
++struct rm_clock {
++	struct rm_obj *prm;
++	ATOMIC_T counter;
++	enum RM_EV_ID evid;
++};
++
++struct rm_priv {
++	u8 enable;
++	_queue ev_queue;
++	_queue rm_queue;
++	_timer rm_timer;
++
++	struct rm_clock clock[RM_TIMER_NUM];
++	u8 rm_en_cap_def[5];
++	u8 rm_en_cap_assoc[5];
++
++	/* rm debug */
++	void *prm_sel;
++};
++
++int rtw_init_rm(_adapter *padapter);
++int rtw_free_rm_priv(_adapter *padapter);
++
++unsigned int rm_on_action(_adapter *padapter, union recv_frame *precv_frame);
++void RM_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
++void rtw_ap_parse_sta_rm_en_cap(_adapter *padapter,
++	struct sta_info *psta, struct rtw_ieee802_11_elems *elems);
++
++int rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid);
++void rm_handler(_adapter *padapter, struct rm_event *pev);
++
++u8 rm_add_nb_req(_adapter *padapter, struct sta_info *psta);
++
++#endif /*CONFIG_RTW_80211K */
++#endif /* __RTW_RM_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_rm_fsm.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_rm_fsm.h
+new file mode 100644
+index 000000000..f99aa0190
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_rm_fsm.h
+@@ -0,0 +1,396 @@
++
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __RTW_RM_FSM_H_
++#define __RTW_RM_FSM_H_
++
++#ifdef CONFIG_RTW_80211K
++
++#define RM_SUPPORT_IWPRIV_DBG	1
++#define RM_MORE_DBG_MSG		0
++
++#define DBG_BCN_REQ_DETAIL	0
++#define DBG_BCN_REQ_WILDCARD	0
++#define DBG_BCN_REQ_SSID	0
++#define DBG_BCN_REQ_SSID_NAME	"RealKungFu"
++
++#define RM_REQ_TIMEOUT		10000	/* 10 seconds */
++#define RM_MEAS_TIMEOUT		10000	/* 10 seconds */
++#define RM_REPT_SCAN_INTVL	5000	/*  5 seconds */
++#define RM_REPT_POLL_INTVL	2000	/*  2 seconds */
++#define RM_COND_INTVL		2000	/*  2 seconds */
++#define RM_SCAN_DENY_TIMES	10
++#define RM_BUSY_TRAFFIC_TIMES	10
++#define RM_WAIT_BUSY_TIMEOUT	1000	/*  1 seconds */
++
++#define MEAS_REQ_MOD_PARALLEL	BIT(0)
++#define MEAS_REQ_MOD_ENABLE	BIT(1)
++#define MEAS_REQ_MOD_REQUEST	BIT(2)
++#define MEAS_REQ_MOD_REPORT	BIT(3)
++#define MEAS_REQ_MOD_DUR_MAND	BIT(4)
++
++#define MEAS_REP_MOD_LATE	BIT(0)
++#define MEAS_REP_MOD_INCAP	BIT(1)
++#define MEAS_REP_MOD_REFUSE	BIT(2)
++
++#define RM_MASTER		BIT(0)	/* STA who issue meas_req */
++#define RM_SLAVE		0	/* STA who do measurement */
++
++#define CLOCK_UNIT		10	/* ms */
++#define RTW_MAX_NB_RPT_IE_NUM	16
++
++#define RM_GET_AID(rmid)	((rmid&0xffff0000)>>16)
++#define RM_IS_ID_FOR_ALL(rmid)	(rmid&RM_ALL_MEAS)
++
++#define	MAX_OP_CHANNEL_SET_NUM	11
++typedef struct _RT_OPERATING_CLASS {
++	int	global_op_class;
++	int	Len;
++	u16	Channel[MAX_OP_CHANNEL_SET_NUM];
++} RT_OPERATING_CLASS, *PRT_OPERATING_CLASS;
++
++/* IEEE 802.11-2012 Table 8-59 Measurement Type definitions
++*  for measurement request
++*  modify rm_meas_type_req_name() when adding new type
++*/
++enum meas_type_of_req {
++	basic_req,	/* spectrum measurement */
++	cca_req,
++	rpi_histo_req,
++	ch_load_req,
++	noise_histo_req,
++	bcn_req,
++	frame_req,
++	sta_statis_req,
++	lci_req,
++	meas_type_req_max,
++};
++
++/* IEEE 802.11-2012 Table 8-81 Measurement Type definitions
++*  for measurement report
++*  modify rm_type_rep_name() when adding new type
++*/
++enum meas_type_of_rep {
++	basic_rep,	/* spectrum measurement */
++	cca_rep,
++	rpi_histo_rep,
++	ch_load_rep,	/* radio measurement */
++	noise_histo_rep,
++	bcn_rep,
++	frame_rep,
++	sta_statis_rep,	/* Radio measurement and WNM */
++	lci_rep,
++	meas_type_rep_max
++};
++
++/*
++* Beacon request
++*/
++/* IEEE 802.11-2012 Table 8-64 Measurement mode for Beacon Request element */
++enum bcn_req_meas_mode {
++	bcn_req_passive,
++	bcn_req_active,
++	bcn_req_bcn_table
++};
++
++/* IEEE 802.11-2012 Table 8-65 optional subelement IDs for Beacon Request */
++enum bcn_req_opt_sub_id{
++	bcn_req_ssid = 0,		/* len 0-32 */
++	bcn_req_rep_info = 1,		/* len 2 */
++	bcn_req_rep_detail = 2,		/* len 1 */
++	bcn_req_req = 10,		/* len 0-237 */
++	bcn_req_ac_ch_rep = 51		/* len 1-237 */
++};
++
++/* IEEE 802.11-2012 Table 8-66 Reporting condition of Beacon Report */
++enum bcn_rep_cound_id{
++	bcn_rep_cond_immediately,	/* default */
++	bcn_req_cond_rcpi_greater,
++	bcn_req_cond_rcpi_less,
++	bcn_req_cond_rsni_greater,
++	bcn_req_cond_rsni_less,
++	bcn_req_cond_max
++};
++
++struct opt_rep_info {
++	u8 cond;
++	u8 threshold;
++};
++
++#define BCN_REQ_OPT_MAX_NUM		16
++struct bcn_req_opt {
++	/* all req cmd id */
++	u8 opt_id[BCN_REQ_OPT_MAX_NUM];
++	u8 opt_id_num;
++	u8 rep_detail;
++	NDIS_802_11_SSID ssid;
++
++	/* bcn report condition */
++	struct opt_rep_info rep_cond;
++
++	/* 0:default(Report to be issued after each measurement) */
++	u8 *req_start;	/*id : 10 request;start  */
++	u8 req_len;	/*id : 10 request;length */
++};
++
++/*
++* channel load
++*/
++/* IEEE 802.11-2012 Table 8-60 optional subelement IDs for channel load request */
++enum ch_load_opt_sub_id{
++	ch_load_rsvd,
++	ch_load_rep_info
++};
++
++/* IEEE 802.11-2012 Table 8-61 Reporting condition for channel load Report */
++enum ch_load_cound_id{
++	ch_load_cond_immediately,	/* default */
++	ch_load_cond_anpi_equal_greater,
++	ch_load_cond_anpi_equal_less,
++	ch_load_cond_max
++};
++
++/*
++* Noise histogram
++*/
++/* IEEE 802.11-2012 Table 8-62 optional subelement IDs for noise histogram */
++enum noise_histo_opt_sub_id{
++	noise_histo_rsvd,
++	noise_histo_rep_info
++};
++
++/* IEEE 802.11-2012 Table 8-63 Reporting condition for noise historgarm Report */
++enum noise_histo_cound_id{
++	noise_histo_cond_immediately,	/* default */
++	noise_histo_cond_anpi_equal_greater,
++	noise_histo_cond_anpi_equal_less,
++	noise_histo_cond_max
++};
++
++struct meas_req_opt {
++	/* report condition */
++	struct opt_rep_info rep_cond;
++};
++
++/*
++* State machine
++*/
++
++enum RM_STATE {
++	RM_ST_IDLE,
++	RM_ST_DO_MEAS,
++	RM_ST_WAIT_MEAS,
++	RM_ST_SEND_REPORT,
++	RM_ST_RECV_REPORT,
++	RM_ST_END,
++	RM_ST_MAX
++};
++
++struct rm_meas_req {
++	u8 category;
++	u8 action_code;		/* T8-206  */
++	u8 diag_token;
++	u16 rpt;
++
++	u8 e_id;
++	u8 len;
++	u8 m_token;
++	u8 m_mode;		/* req:F8-105, rep:F8-141 */
++	u8 m_type;		/* T8-59 */
++	u8 op_class;
++	u8 ch_num;
++	u16 rand_intvl;		/* units of TU */
++	u16 meas_dur;		/* units of TU */
++
++	u8 bssid[6];		/* for bcn_req */
++
++	u8 *pssid;
++	u8 *opt_s_elem_start;
++	int opt_s_elem_len;
++
++	s8 tx_pwr_used;		/* for link measurement */
++	s8 tx_pwr_max;		/* for link measurement */
++
++	union {
++		struct bcn_req_opt bcn;
++		struct meas_req_opt clm;
++		struct meas_req_opt nhm;
++	}opt;
++
++	struct rtw_ieee80211_channel ch_set[MAX_OP_CHANNEL_SET_NUM];
++	u8 ch_set_ch_amount;
++	s8 rx_pwr;		/* in dBm */
++	u8 rx_bw;
++	u8 rx_rate;
++	u8 rx_rsni;
++};
++
++struct rm_meas_rep {
++	u8 category;
++	u8 action_code;		/* T8-206  */
++	u8 diag_token;
++
++	u8 e_id;		/* T8-54, 38 request; 39 report */
++	u8 len;
++	u8 m_token;
++	u8 m_mode;		/* req:F8-105, rep:F8-141 */
++	u8 m_type;		/* T8-59 */
++	u8 op_class;
++	u8 ch_num;
++
++	u8 ch_load;
++	u8 anpi;
++	u8 ipi[11];
++
++	u16 rpt;
++	u8 bssid[6];		/* for bcn_req */
++};
++
++#define MAX_BUF_NUM	128
++struct data_buf {
++	u8 *pbuf;
++	u16 len;
++};
++
++struct rm_obj {
++
++	/* aid << 16 
++		|diag_token << 8
++		|B(1) 1/0:All_AID/UNIC
++		|B(0) 1/0:RM_MASTER/RM_SLAVE */
++	u32 rmid;
++
++	enum RM_STATE state;
++	struct rm_meas_req q;
++	struct rm_meas_rep p;
++	struct sta_info *psta;
++	struct rm_clock *pclock;
++
++	/* meas report */
++	u64 meas_start_time;
++	u64 meas_end_time;
++	int wait_busy;
++	u8 poll_mode;
++	u8 free_run_counter_valid; /* valid:_SUCCESS/invalid:_FAIL */
++
++	struct data_buf buf[MAX_BUF_NUM];
++
++	_list list;
++};
++
++/*
++* Measurement
++*/
++struct opt_subelement {
++	u8 id;
++	u8 length;
++	u8 *data;
++};
++
++/* 802.11-2012 Table 8-206 Radio Measurment Action field */
++enum rm_action_code {
++	RM_ACT_RADIO_MEAS_REQ,
++	RM_ACT_RADIO_MEAS_REP,
++	RM_ACT_LINK_MEAS_REQ,
++	RM_ACT_LINK_MEAS_REP,
++	RM_ACT_NB_REP_REQ,	/* 4 */
++	RM_ACT_NB_REP_RESP,
++	RM_ACT_RESV,
++	RM_ACT_MAX
++};
++
++/* 802.11-2012 Table 8-119 RM Enabled Capabilities definition */
++enum rm_cap_en {
++	RM_LINK_MEAS_CAP_EN,
++	RM_NB_REP_CAP_EN,		/* neighbor report */
++	RM_PARAL_MEAS_CAP_EN,		/* parallel report */
++	RM_REPEAT_MEAS_CAP_EN,
++	RM_BCN_PASSIVE_MEAS_CAP_EN,
++	RM_BCN_ACTIVE_MEAS_CAP_EN,
++	RM_BCN_TABLE_MEAS_CAP_EN,
++	RM_BCN_MEAS_REP_COND_CAP_EN,	/* conditions */
++
++	RM_FRAME_MEAS_CAP_EN,
++	RM_CH_LOAD_CAP_EN,
++	RM_NOISE_HISTO_CAP_EN,		/* noise historgram */
++	RM_STATIS_MEAS_CAP_EN,		/* statistics */
++	RM_LCI_MEAS_CAP_EN,		/* 12 */
++	RM_LCI_AMIMUTH_CAP_EN,
++	RM_TRANS_STREAM_CAT_MEAS_CAP_EN,
++	RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN,
++
++	RM_AP_CH_REP_CAP_EN,
++	RM_RM_MIB_CAP_EN,
++	RM_OP_CH_MAX_MEAS_DUR0,		/* 18-20 */
++	RM_OP_CH_MAX_MEAS_DUR1,
++	RM_OP_CH_MAX_MEAS_DUR2,
++	RM_NONOP_CH_MAX_MEAS_DUR0,	/* 21-23 */
++	RM_NONOP_CH_MAX_MEAS_DUR1,
++	RM_NONOP_CH_MAX_MEAS_DUR2,
++
++	RM_MEAS_PILOT_CAP0,		/* 24-26 */
++	RM_MEAS_PILOT_CAP1,
++	RM_MEAS_PILOT_CAP2,
++	RM_MEAS_PILOT_TRANS_INFO_CAP_EN,
++	RM_NB_REP_TSF_OFFSET_CAP_EN,
++	RM_RCPI_MEAS_CAP_EN,		/* 29 */
++	RM_RSNI_MEAS_CAP_EN,
++	RM_BSS_AVG_ACCESS_DELAY_CAP_EN,
++
++	RM_AVALB_ADMIS_CAPACITY_CAP_EN,
++	RM_ANT_CAP_EN,
++	RM_RSVD,			/* 34-39 */
++	RM_MAX
++};
++
++char *rm_state_name(enum RM_STATE state);
++char *rm_event_name(enum RM_EV_ID evid);
++char *rm_type_req_name(u8 meas_type);
++int _rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid);
++int rm_enqueue_rmobj(_adapter *padapter, struct rm_obj *obj, bool to_head);
++
++void rm_free_rmobj(struct rm_obj *prm);
++struct rm_obj *rm_alloc_rmobj(_adapter *padapter);
++struct rm_obj *rm_get_rmobj(_adapter *padapter, u32 rmid);
++struct sta_info *rm_get_psta(_adapter *padapter, u32 rmid);
++
++int retrieve_radio_meas_result(struct rm_obj *prm);
++int rm_radio_meas_report_cond(struct rm_obj *prm);
++int rm_recv_radio_mens_req(_adapter *padapter,
++	union recv_frame *precv_frame,struct sta_info *psta);
++int rm_recv_radio_mens_rep(_adapter *padapter,
++	union recv_frame *precv_frame, struct sta_info *psta);
++int rm_recv_link_mens_req(_adapter *padapter,
++	union recv_frame *precv_frame,struct sta_info *psta);
++int rm_recv_link_mens_rep(_adapter *padapter,
++	union recv_frame *precv_frame, struct sta_info *psta);
++int rm_radio_mens_nb_rep(_adapter *padapter,
++	union recv_frame *precv_frame, struct sta_info *psta);
++int issue_null_reply(struct rm_obj *prm);
++int issue_beacon_rep(struct rm_obj *prm);
++int issue_nb_req(struct rm_obj *prm);
++int issue_radio_meas_req(struct rm_obj *prm);
++int issue_radio_meas_rep(struct rm_obj *prm);
++int issue_link_meas_req(struct rm_obj *prm);
++int issue_link_meas_rep(struct rm_obj *prm);
++
++void rm_set_rep_mode(struct rm_obj *prm, u8 mode);
++
++int ready_for_scan(struct rm_obj *prm);
++int rm_sitesurvey(struct rm_obj *prm);
++
++#endif /*CONFIG_RTW_80211K*/
++#endif /*__RTW_RM_FSM_H_*/
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_rm_util.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_rm_util.h
+new file mode 100644
+index 000000000..b4b886748
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_rm_util.h
+@@ -0,0 +1,42 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef _RTW_RM_UTIL_H_
++#define _RTW_RM_UTIL_H_
++/*
++ * define the following channels as the max channels in each channel plan.
++ * 2G, total 14 chnls
++ * {1,2,3,4,5,6,7,8,9,10,11,12,13,14}
++ * 5G, total 25 chnls
++ * {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,144,149,153,157,161,165}
++ */
++#ifndef MAX
++#define MAX(x, y) (((x) > (y)) ? (x) : (y))
++#endif
++
++u8 rm_get_oper_class_via_ch(u8 ch);
++u8 rm_get_ch_set( struct rtw_ieee80211_channel *pch_set, u8 op_class, u8 ch_num);
++u8 rm_get_bcn_rsni(struct rm_obj *prm, struct wlan_network *pnetwork);
++u8 rm_get_bcn_rcpi(struct rm_obj *prm, struct wlan_network *pnetwork);
++u8 rm_get_frame_rsni(struct rm_obj *prm, union recv_frame *pframe);
++u8 translate_percentage_to_rcpi(u32 SignalStrengthIndex);
++u8 translate_dbm_to_rcpi(s8 SignalPower);
++int is_wildcard_bssid(u8 *bssid);
++
++int rm_get_path_a_max_tx_power(_adapter *adapter, s8 *path_a);
++int rm_get_tx_power(PADAPTER adapter, enum rf_path path, enum MGN_RATE rate, s8 *pwr);
++int rm_get_rx_sensitivity(PADAPTER adapter, enum channel_width bw, enum MGN_RATE rate, s8 *pwr);
++
++#endif /* _RTW_RM_UTIL_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_rson.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_rson.h
+new file mode 100644
+index 000000000..6996738b0
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_rson.h
+@@ -0,0 +1,61 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++#ifndef __RTW_RSON_H_
++#define __RTW_RSON_H_
++
++
++#define RTW_RSON_VER						1
++
++#define RTW_RSON_SCORE_NOTSUP			0x0
++#define RTW_RSON_SCORE_NOTCNNT			0x1
++#define RTW_RSON_SCORE_MAX				0xFF
++#define RTW_RSON_HC_NOTREADY			0xFF
++#define RTW_RSON_HC_ROOT				0x0
++#define RTW_RSON_ALLOWCONNECT			0x1
++#define RTW_RSON_DENYCONNECT			0x0
++
++
++
++/*	for rtw self-origanization spec 1	*/
++struct rtw_rson_struct {
++	u8 ver;
++	u32 id;
++	u8 hopcnt;
++	u8 connectible;
++	u8 loading;
++	u8 res[16];
++} __attribute__((__packed__));
++
++void init_rtw_rson_data(struct dvobj_priv *dvobj);
++void rtw_rson_get_property_str(_adapter *padapter, char *rson_data_str);
++int rtw_rson_set_property(_adapter *padapter, char *field, char *value);
++int rtw_rson_choose(struct wlan_network **candidate, struct wlan_network *competitor);
++int rtw_get_rson_struct(WLAN_BSSID_EX *bssid, struct  rtw_rson_struct *rson_data);
++u8 rtw_cal_rson_score(struct rtw_rson_struct *cand_rson_data, NDIS_802_11_RSSI  Rssi);
++void rtw_rson_handle_ie(WLAN_BSSID_EX *bssid, u8 ie_offset);
++u32 rtw_rson_append_ie(_adapter *padapter, unsigned char *pframe, u32 *len);
++void rtw_rson_do_disconnect(_adapter *padapter);
++void rtw_rson_join_done(_adapter *padapter);
++int rtw_rson_isupdate_roamcan(struct mlme_priv *mlme, struct wlan_network **candidate, struct wlan_network *competitor);
++void rtw_rson_show_survey_info(struct seq_file *m, _list *plist, _list *phead);
++u8 rtw_rson_ap_check_sta(_adapter *padapter, u8 *pframe, uint pkt_len, unsigned short ie_offset);
++u8 rtw_rson_scan_wk_cmd(_adapter *padapter, int op);
++void rtw_rson_scan_cmd_hdl(_adapter *padapter, int op);
++#endif /* __RTW_RSON_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_sdio.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_sdio.h
+new file mode 100644
+index 000000000..7490b5481
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_sdio.h
+@@ -0,0 +1,26 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2015 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTW_SDIO_H_
++#define _RTW_SDIO_H_
++
++#include <drv_types.h>		/* struct dvobj_priv and etc. */
++
++u8 rtw_sdio_read_cmd52(struct dvobj_priv *, u32 addr, void *buf, size_t len);
++u8 rtw_sdio_read_cmd53(struct dvobj_priv *, u32 addr, void *buf, size_t len);
++u8 rtw_sdio_write_cmd52(struct dvobj_priv *, u32 addr, void *buf, size_t len);
++u8 rtw_sdio_write_cmd53(struct dvobj_priv *, u32 addr, void *buf, size_t len);
++u8 rtw_sdio_f0_read(struct dvobj_priv *, u32 addr, void *buf, size_t len);
++
++#endif /* _RTW_SDIO_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_security.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_security.h
+new file mode 100644
+index 000000000..c26c8cf41
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_security.h
+@@ -0,0 +1,421 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_SECURITY_H_
++#define __RTW_SECURITY_H_
++
++enum security_type {
++	/* TYPE */
++	_NO_PRIVACY_	= 0x00,
++	_WEP40_		= 0x01,
++	_TKIP_		= 0x02,
++	_TKIP_WTMIC_	= 0x03,
++	_AES_		= 0x04,
++	_WEP104_	= 0x05,
++	_SMS4_		= 0x06,
++	_GCMP_		= 0x07,
++	_SEC_TYPE_MAX_,
++
++	/* EXT_SECTYPE=1 */
++	_SEC_TYPE_256_	= 0x10,
++	_CCMP_256_	= (_AES_ | _SEC_TYPE_256_),
++	_GCMP_256_	= (_GCMP_ | _SEC_TYPE_256_),
++
++#ifdef CONFIG_IEEE80211W
++	/* EXT_SECTYPE=0, MGNT=1, GK=0/1, KEYID=00/01 */
++	_SEC_TYPE_BIT_	= 0x20,
++	_BIP_CMAC_128_	= (_SEC_TYPE_BIT_),
++	_BIP_GMAC_128_	= (_SEC_TYPE_BIT_ + 1),
++	_BIP_GMAC_256_	= (_SEC_TYPE_BIT_ + 2),
++	/* EXT_SECTYPE=1, MGNT=1, GK=1, KEYID=00/01 */
++	_BIP_CMAC_256_	= (_SEC_TYPE_BIT_ + 3),
++	_BIP_MAX_,
++#endif
++};
++
++/* 802.11W use wrong key */
++#define IEEE80211W_RIGHT_KEY	0x0
++#define IEEE80211W_WRONG_KEY	0x1
++#define IEEE80211W_NO_KEY		0x2
++
++#define CCMPH_2_PN(ch)	((ch) & 0x000000000000ffff) \
++			| (((ch) & 0xffffffff00000000) >> 16)
++
++#define is_wep_enc(alg) (((alg) == _WEP40_) || ((alg) == _WEP104_))
++
++const char *security_type_str(u8 value);
++#ifdef CONFIG_IEEE80211W
++u32 security_type_bip_to_gmcs(enum security_type type);
++#endif
++
++#define _WPA_IE_ID_	0xdd
++#define _WPA2_IE_ID_	0x30
++
++#define RTW_KEK_LEN 16
++#define RTW_KCK_LEN 16
++#define RTW_TKIP_MIC_LEN 8
++#define RTW_REPLAY_CTR_LEN 8
++
++#define INVALID_SEC_MAC_CAM_ID	0xFF
++
++typedef enum {
++	ENCRYP_PROTOCOL_OPENSYS,   /* open system */
++	ENCRYP_PROTOCOL_WEP,       /* WEP */
++	ENCRYP_PROTOCOL_WPA,       /* WPA */
++	ENCRYP_PROTOCOL_WPA2,      /* WPA2 */
++	ENCRYP_PROTOCOL_WAPI,      /* WAPI: Not support in this version */
++	ENCRYP_PROTOCOL_MAX
++} ENCRYP_PROTOCOL_E;
++
++
++#ifndef Ndis802_11AuthModeWPA2
++#define Ndis802_11AuthModeWPA2 (Ndis802_11AuthModeWPANone + 1)
++#endif
++
++#ifndef Ndis802_11AuthModeWPA2PSK
++#define Ndis802_11AuthModeWPA2PSK (Ndis802_11AuthModeWPANone + 2)
++#endif
++
++union pn48	{
++
++	u64	val;
++
++#ifdef CONFIG_LITTLE_ENDIAN
++
++struct {
++	u8 TSC0;
++	u8 TSC1;
++	u8 TSC2;
++	u8 TSC3;
++	u8 TSC4;
++	u8 TSC5;
++	u8 TSC6;
++	u8 TSC7;
++} _byte_;
++
++#elif defined(CONFIG_BIG_ENDIAN)
++
++struct {
++	u8 TSC7;
++	u8 TSC6;
++	u8 TSC5;
++	u8 TSC4;
++	u8 TSC3;
++	u8 TSC2;
++	u8 TSC1;
++	u8 TSC0;
++} _byte_;
++
++#endif
++
++};
++
++union Keytype {
++	u8 skey[32];
++};
++
++typedef struct _RT_PMKID_LIST {
++	u8						bUsed;
++	u8						Bssid[6];
++	u8						PMKID[16];
++	u8						SsidBuf[33];
++	u8						*ssid_octet;
++	u16						ssid_length;
++} RT_PMKID_LIST, *PRT_PMKID_LIST;
++
++
++struct security_priv {
++	u32	  dot11AuthAlgrthm;		/* 802.11 auth, could be open, shared, 8021x and authswitch */
++	u32	  dot11PrivacyAlgrthm;	/* This specify the privacy for shared auth. algorithm. */
++
++	/* WEP */
++	u32	  dot11PrivacyKeyIndex;	/* this is only valid for legendary wep, 0~3 for key id. (tx key index) */
++	union Keytype dot11DefKey[6];			/* this is only valid for def. key	 */
++	u32	dot11DefKeylen[6];
++	u8	dot11Def_camid[6];
++	u8 	key_mask; /* use to restore wep key after hal_init */
++
++	u32 dot118021XGrpPrivacy;	/* This specify the privacy algthm. used for Grp key */
++	u32	dot118021XGrpKeyid;		/* key id used for Grp Key ( tx key index) */
++	union Keytype	dot118021XGrpKey[6];	/* 802.1x Group Key, for inx0 and inx1	 */
++	union Keytype	dot118021XGrptxmickey[6];
++	union Keytype	dot118021XGrprxmickey[6];
++	union pn48		dot11Grptxpn;			/* PN48 used for Grp Key xmit. */
++	union pn48		dot11Grprxpn;			/* PN48 used for Grp Key recv. */
++	u8				iv_seq[4][8];
++#ifdef CONFIG_IEEE80211W
++	enum security_type dot11wCipher;
++	u32	dot11wBIPKeyid;						/* key id used for BIP Key ( tx key index) */
++	union Keytype	dot11wBIPKey[6];		/* BIP Key, for index4 and index5 */
++	union pn48		dot11wBIPtxpn;			/* PN48 used for BIP xmit. */
++	union pn48		dot11wBIPrxpn;			/* PN48 used for BIP recv. */
++#endif /* CONFIG_IEEE80211W */
++#ifdef CONFIG_AP_MODE
++	/* extend security capabilities for AP_MODE */
++	unsigned int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */
++	unsigned int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */
++	unsigned int wpa_group_cipher;
++	unsigned int wpa2_group_cipher;
++	unsigned int wpa_pairwise_cipher;
++	unsigned int wpa2_pairwise_cipher;
++	unsigned int akmp; /* An authentication and key management protocol */
++	u8 mfp_opt;
++#endif
++	u8	dot118021x_bmc_cam_id;
++	/*IEEE802.11-2012 Std. Table 8-101 AKM Suite Selectors*/
++	u32	rsn_akm_suite_type;
++
++	u8 wps_ie[MAX_WPS_IE_LEN];/* added in assoc req */
++	int wps_ie_len;
++
++	u8 owe_ie[MAX_OWE_IE_LEN];/* added in assoc req */
++	int owe_ie_len;
++
++	u8	binstallGrpkey;
++#ifdef CONFIG_GTK_OL
++	u8	binstallKCK_KEK;
++#endif /* CONFIG_GTK_OL */
++#ifdef CONFIG_IEEE80211W
++	u8	binstallBIPkey;
++#endif /* CONFIG_IEEE80211W */
++	u8	busetkipkey;
++	u8	bcheck_grpkey;
++	u8	bgrpkey_handshake;
++
++	u8	auth_alg;
++	u8	auth_type;
++	u8	extauth_status;
++	/* u8	packet_cnt; */ /* unused, removed */
++
++	s32	sw_encrypt;/* from registry_priv */
++	s32	sw_decrypt;/* from registry_priv */
++
++	s32 	hw_decrypted;/* if the rx packets is hw_decrypted==_FALSE, it means the hw has not been ready. */
++
++
++	/* keeps the auth_type & enc_status from upper layer ioctl(wpa_supplicant or wzc) */
++	u32 ndisauthtype;	/* NDIS_802_11_AUTHENTICATION_MODE */
++	u32 ndisencryptstatus;	/* NDIS_802_11_ENCRYPTION_STATUS */
++
++	NDIS_802_11_WEP ndiswep;
++
++	u8 assoc_info[600];
++	u8 szofcapability[256]; /* for wpa2 usage */
++	u8 oidassociation[512]; /* for wpa/wpa2 usage */
++	u8 authenticator_ie[256];  /* store ap security information element */
++	u8 supplicant_ie[256];  /* store sta security information element */
++
++
++	/* for tkip countermeasure */
++	systime last_mic_err_time;
++	u8	btkip_countermeasure;
++	u8	btkip_wait_report;
++	systime btkip_countermeasure_time;
++
++	/* --------------------------------------------------------------------------- */
++	/* For WPA2 Pre-Authentication. */
++	/* --------------------------------------------------------------------------- */
++	/* u8				RegEnablePreAuth;				 */ /* Default value: Pre-Authentication enabled or not, from registry "EnablePreAuth". Added by Annie, 2005-11-01. */
++	/* u8				EnablePreAuthentication;			 */ /* Current Value: Pre-Authentication enabled or not. */
++	RT_PMKID_LIST		PMKIDList[NUM_PMKID_CACHE];	/* Renamed from PreAuthKey[NUM_PRE_AUTH_KEY]. Annie, 2006-10-13. */
++	u8				PMKIDIndex;
++	/* u32				PMKIDCount;						 */ /* Added by Annie, 2006-10-13. */
++	/* u8				szCapability[256];				 */ /* For WPA2-PSK using zero-config, by Annie, 2005-09-20. */
++
++	u8 bWepDefaultKeyIdxSet;
++
++#define DBG_SW_SEC_CNT
++#ifdef DBG_SW_SEC_CNT
++	u64 wep_sw_enc_cnt_bc;
++	u64 wep_sw_enc_cnt_mc;
++	u64 wep_sw_enc_cnt_uc;
++	u64 wep_sw_dec_cnt_bc;
++	u64 wep_sw_dec_cnt_mc;
++	u64 wep_sw_dec_cnt_uc;
++
++	u64 tkip_sw_enc_cnt_bc;
++	u64 tkip_sw_enc_cnt_mc;
++	u64 tkip_sw_enc_cnt_uc;
++	u64 tkip_sw_dec_cnt_bc;
++	u64 tkip_sw_dec_cnt_mc;
++	u64 tkip_sw_dec_cnt_uc;
++
++	u64 aes_sw_enc_cnt_bc;
++	u64 aes_sw_enc_cnt_mc;
++	u64 aes_sw_enc_cnt_uc;
++	u64 aes_sw_dec_cnt_bc;
++	u64 aes_sw_dec_cnt_mc;
++	u64 aes_sw_dec_cnt_uc;
++
++	u64 gcmp_sw_enc_cnt_bc;
++	u64 gcmp_sw_enc_cnt_mc;
++	u64 gcmp_sw_enc_cnt_uc;
++	u64 gcmp_sw_dec_cnt_bc;
++	u64 gcmp_sw_dec_cnt_mc;
++	u64 gcmp_sw_dec_cnt_uc;
++#endif /* DBG_SW_SEC_CNT */
++};
++
++#ifdef CONFIG_IEEE80211W
++#define SEC_IS_BIP_KEY_INSTALLED(sec) ((sec)->binstallBIPkey)
++#else
++#define SEC_IS_BIP_KEY_INSTALLED(sec) _FALSE
++#endif
++
++#define GET_ENCRY_ALGO(psecuritypriv, psta, encry_algo, bmcst)\
++	do {\
++		switch (psecuritypriv->dot11AuthAlgrthm) {\
++		case dot11AuthAlgrthm_Open:\
++		case dot11AuthAlgrthm_Shared:\
++		case dot11AuthAlgrthm_Auto:\
++			encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\
++			break;\
++		case dot11AuthAlgrthm_8021X:\
++			if (bmcst)\
++				encry_algo = (u8)psecuritypriv->dot118021XGrpPrivacy;\
++			else\
++				encry_algo = (u8) psta->dot118021XPrivacy;\
++			break;\
++		case dot11AuthAlgrthm_WAPI:\
++			encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\
++			break;\
++		} \
++	} while (0)
++
++#define _AES_IV_LEN_ 8
++
++#define SET_ICE_IV_LEN(iv_len, icv_len, encrypt)\
++	do {\
++		switch (encrypt) {\
++		case _WEP40_:\
++		case _WEP104_:\
++			iv_len = 4;\
++			icv_len = 4;\
++			break;\
++		case _TKIP_:\
++			iv_len = 8;\
++			icv_len = 4;\
++			break;\
++		case _AES_:\
++			iv_len = 8;\
++			icv_len = 8;\
++			break;\
++		case _GCMP_:\
++		case _GCMP_256_:\
++			iv_len = 8;\
++			icv_len = 16;\
++			break;\
++		case _CCMP_256_:\
++			iv_len = 8;\
++			icv_len = 16;\
++			break;\
++		case _SMS4_:\
++			iv_len = 18;\
++			icv_len = 16;\
++			break;\
++		default:\
++			iv_len = 0;\
++			icv_len = 0;\
++			break;\
++		} \
++	} while (0)
++
++
++#define GET_TKIP_PN(iv, dot11txpn)\
++	do {\
++		dot11txpn._byte_.TSC0 = iv[2];\
++		dot11txpn._byte_.TSC1 = iv[0];\
++		dot11txpn._byte_.TSC2 = iv[4];\
++		dot11txpn._byte_.TSC3 = iv[5];\
++		dot11txpn._byte_.TSC4 = iv[6];\
++		dot11txpn._byte_.TSC5 = iv[7];\
++	} while (0)
++
++
++#define ROL32(A, n)	(((A) << (n)) | (((A)>>(32-(n)))  & ((1UL << (n)) - 1)))
++#define ROR32(A, n)	ROL32((A), 32-(n))
++
++struct mic_data {
++	u32  K0, K1;         /* Key */
++	u32  L, R;           /* Current state */
++	u32  M;              /* Message accumulator (single word) */
++	u32     nBytesInM;      /*  # bytes in M */
++};
++
++void rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key);
++void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b);
++void rtw_secmicappend(struct mic_data *pmicdata, u8 *src, u32 nBytes);
++void rtw_secgetmic(struct mic_data *pmicdata, u8 *dst);
++
++void rtw_seccalctkipmic(
++	u8 *key,
++	u8 *header,
++	u8 *data,
++	u32 data_len,
++	u8 *Miccode,
++	u8   priority);
++
++u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe);
++u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe);
++void rtw_wep_encrypt(_adapter *padapter, u8  *pxmitframe);
++
++u32 rtw_aes_decrypt(_adapter *padapter, u8  *precvframe);
++u32 rtw_tkip_decrypt(_adapter *padapter, u8  *precvframe);
++void rtw_wep_decrypt(_adapter *padapter, u8  *precvframe);
++
++u32 rtw_gcmp_encrypt(_adapter *padapter, u8 *pxmitframe);
++u32 rtw_gcmp_decrypt(_adapter *padapter, u8 *precvframe);
++
++#ifdef CONFIG_RTW_MESH_AEK
++int rtw_aes_siv_encrypt(const u8 *key, size_t key_len,
++	const u8 *pw, size_t pwlen, size_t num_elem,
++	const u8 *addr[], const size_t *len, u8 *out);
++int rtw_aes_siv_decrypt(const u8 *key, size_t key_len,
++	const u8 *iv_crypt, size_t iv_c_len, size_t num_elem,
++	const u8 *addr[], const size_t *len, u8 *out);
++#endif /* CONFIG_RTW_MESH_AEK */
++
++#ifdef CONFIG_IEEE80211W
++u8 rtw_calculate_bip_mic(enum security_type gmcs, u8 *whdr_pos, s32 len,
++	const u8 *key, const u8 *data, size_t data_len, u8 *mic);
++u32 rtw_bip_verify(enum security_type gmcs, u16 pkt_len,
++	u8 *whdr_pos, sint flen, const u8 *key, u16 keyid, u64 *ipn);
++#endif
++#ifdef CONFIG_TDLS
++void wpa_tdls_generate_tpk(_adapter *padapter, void *sta);
++int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq,
++			u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie,
++			u8 *mic);
++int wpa_tdls_teardown_ftie_mic(u8 *kck, u8 *lnkid, u16 reason,
++			u8 dialog_token, u8 trans_seq, u8 *ftie, u8 *mic);
++int tdls_verify_mic(u8 *kck, u8 trans_seq,
++			u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie);
++#endif /* CONFIG_TDLS */
++
++void rtw_sec_restore_wep_key(_adapter *adapter);
++u8 rtw_handle_tkip_countermeasure(_adapter *adapter, const char *caller);
++
++#ifdef CONFIG_WOWLAN
++u16 rtw_calc_crc(u8  *pdata, int length);
++#endif /*CONFIG_WOWLAN*/
++
++#define rtw_sec_chk_auth_alg(a, s) \
++	((a)->securitypriv.auth_alg == (s))
++
++#define rtw_sec_chk_auth_type(a, s) \
++	((a)->securitypriv.auth_type == (s))
++
++#endif /* __RTL871X_SECURITY_H_ */
++
++u32 rtw_calc_crc32(u8 *data, size_t len);
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_sreset.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_sreset.h
+new file mode 100644
+index 000000000..1fd999a9d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_sreset.h
+@@ -0,0 +1,66 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTW_SRESET_H_
++#define _RTW_SRESET_H_
++
++/* #include <drv_types.h> */
++
++enum {
++	SRESET_TGP_NULL = 0,
++	SRESET_TGP_XMIT_STATUS = 1,
++	SRESET_TGP_LINK_STATUS = 2,
++	SRESET_TGP_INFO = 99,
++};
++
++struct sreset_priv {
++	_mutex	silentreset_mutex;
++	u8	silent_reset_inprogress;
++	u8	Wifi_Error_Status;
++	systime last_tx_time;
++	systime last_tx_complete_time;
++
++	s32 dbg_trigger_point;
++	u64 self_dect_tx_cnt;
++	u64 self_dect_rx_cnt;
++	u64 self_dect_fw_cnt;
++	u64 tx_dma_status_cnt;
++	u64 rx_dma_status_cnt;
++	u8 rx_cnt;
++	u8 self_dect_fw;
++	u8 self_dect_case;
++	u16 last_mac_rxff_ptr;
++	u8 dbg_sreset_ctrl;
++};
++
++
++
++#define	WIFI_STATUS_SUCCESS		0
++#define	USB_VEN_REQ_CMD_FAIL	BIT0
++#define	USB_READ_PORT_FAIL		BIT1
++#define	USB_WRITE_PORT_FAIL		BIT2
++#define	WIFI_MAC_TXDMA_ERROR	BIT3
++#define   WIFI_TX_HANG				BIT4
++#define	WIFI_RX_HANG				BIT5
++#define	WIFI_IF_NOT_EXIST			BIT6
++
++void sreset_init_value(_adapter *padapter);
++void sreset_reset_value(_adapter *padapter);
++u8 sreset_get_wifi_status(_adapter *padapter);
++void sreset_set_wifi_error_status(_adapter *padapter, u32 status);
++void sreset_set_trigger_point(_adapter *padapter, s32 tgp);
++bool sreset_inprogress(_adapter *padapter);
++void sreset_reset(_adapter *padapter);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_swcrypto.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_swcrypto.h
+new file mode 100644
+index 000000000..b00878ea8
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_swcrypto.h
+@@ -0,0 +1,49 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __RTW_SWCRYPTO_H_
++#define __RTW_SWCRYPTO_H_
++
++#define NEW_CRYPTO 1
++
++int _rtw_ccmp_encrypt(u8 *key, u32 key_len, uint hdrlen, u8 *frame, uint plen);
++int _rtw_ccmp_decrypt(u8 *key, u32 key_len, uint hdrlen, u8 *frame, uint plen);
++
++int _rtw_gcmp_encrypt(u8 *key, u32 key_len, uint hdrlen, u8 *frame, uint plen);
++int _rtw_gcmp_decrypt(u8 *key, u32 key_len, uint hdrlen, u8 *frame, uint plen);
++
++#ifdef CONFIG_RTW_MESH_AEK
++int _aes_siv_encrypt(const u8 *key, size_t key_len,
++	const u8 *pw, size_t pwlen,
++	size_t num_elem, const u8 *addr[], const size_t *len, u8 *out);
++int _aes_siv_decrypt(const u8 *key, size_t key_len,
++	const u8 *iv_crypt, size_t iv_c_len,
++	size_t num_elem, const u8 *addr[], const size_t *len, u8 *out);
++#endif
++
++#if defined(CONFIG_IEEE80211W) | defined(CONFIG_TDLS)
++u8 _bip_ccmp_protect(const u8 *key, size_t key_len,
++	const u8 *data, size_t data_len, u8 *mic);
++u8 _bip_gcmp_protect(u8 *whdr_pos, size_t len,
++	const u8 *key, size_t key_len,
++	const u8 *data, size_t data_len, u8 *mic);
++#endif /* CONFIG_IEEE80211W */
++
++#ifdef CONFIG_TDLS
++void _tdls_generate_tpk(void *sta, const u8 *own_addr, const u8 *bssid);
++#endif /* CONFIG_TDLS */
++
++#endif /* __RTW_SWCRYPTO_H_ */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_tdls.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_tdls.h
+new file mode 100644
+index 000000000..5c23e4ea4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_tdls.h
+@@ -0,0 +1,185 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_TDLS_H_
++#define __RTW_TDLS_H_
++
++
++#ifdef CONFIG_TDLS
++/* TDLS STA state */
++
++
++/* TDLS Diect Link Establishment */
++#define	TDLS_STATE_NONE				0x00000000		/* Default state */
++#define	TDLS_INITIATOR_STATE		BIT(28)			/* 0x10000000 */
++#define	TDLS_RESPONDER_STATE		BIT(29)			/* 0x20000000 */
++#define	TDLS_LINKED_STATE			BIT(30)			/* 0x40000000 */
++/* TDLS PU Buffer STA */
++#define	TDLS_WAIT_PTR_STATE			BIT(24)			/* 0x01000000 */	/* Waiting peer's TDLS_PEER_TRAFFIC_RESPONSE frame */
++/* TDLS Check ALive */
++#define	TDLS_ALIVE_STATE			BIT(20)			/* 0x00100000 */	/* Check if peer sta is alived. */
++/* TDLS Channel Switch */
++#define	TDLS_CH_SWITCH_PREPARE_STATE	BIT(15)			/* 0x00008000 */
++#define	TDLS_CH_SWITCH_ON_STATE			BIT(16)			/* 0x00010000 */
++#define	TDLS_PEER_AT_OFF_STATE			BIT(17)			/* 0x00020000 */	/* Could send pkt on target ch */
++#define	TDLS_CH_SW_INITIATOR_STATE		BIT(18)			/* 0x00040000 */	/* Avoid duplicated or unconditional ch. switch rsp. */
++#define	TDLS_WAIT_CH_RSP_STATE			BIT(19)			/* 0x00080000 */	/* Wait Ch. response as we are TDLS channel switch initiator */
++
++
++#define	TDLS_TPK_RESEND_COUNT			86400	/*Unit: seconds */
++#define	TDLS_CH_SWITCH_TIME				15
++#define	TDLS_CH_SWITCH_TIMEOUT			30
++#define	TDLS_CH_SWITCH_OPER_OFFLOAD_TIMEOUT	10
++#define	TDLS_SIGNAL_THRESH			0x20
++#define	TDLS_WATCHDOG_PERIOD		10	/* Periodically sending tdls discovery request in TDLS_WATCHDOG_PERIOD * 2 sec */
++#define	TDLS_HANDSHAKE_TIME			3000
++#define	TDLS_PTI_TIME				7000
++
++#define TDLS_CH_SW_STAY_ON_BASE_CHNL_TIMEOUT	20		/* ms */
++#define TDLS_CH_SW_MONITOR_TIMEOUT				2000	/*ms */
++
++#define TDLS_MIC_LEN 16
++#define WPA_NONCE_LEN 32
++#define TDLS_TIMEOUT_LEN 4
++
++enum TDLS_CH_SW_CHNL {
++	TDLS_CH_SW_BASE_CHNL = 0,
++	TDLS_CH_SW_OFF_CHNL
++};
++
++#define TDLS_MIC_CTRL_LEN 2
++#define TDLS_FTIE_DATA_LEN (TDLS_MIC_CTRL_LEN + TDLS_MIC_LEN + \
++							WPA_NONCE_LEN + WPA_NONCE_LEN)
++struct wpa_tdls_ftie {
++	u8 ie_type; /* FTIE */
++	u8 ie_len;
++	union {
++		struct {
++			u8 mic_ctrl[TDLS_MIC_CTRL_LEN];
++			u8 mic[TDLS_MIC_LEN];
++			u8 Anonce[WPA_NONCE_LEN]; /* Responder Nonce in TDLS */
++			u8 Snonce[WPA_NONCE_LEN]; /* Initiator Nonce in TDLS */
++		};
++		struct {
++			u8 data[TDLS_FTIE_DATA_LEN];
++		};
++	};
++	/* followed by optional elements */
++} ;
++
++struct wpa_tdls_lnkid {
++	u8 ie_type; /* Link Identifier IE */
++	u8 ie_len;
++	u8 bssid[ETH_ALEN];
++	u8 init_sta[ETH_ALEN];
++	u8 resp_sta[ETH_ALEN];
++} ;
++
++static u8 TDLS_RSNIE[20] = {	0x01, 0x00,	/* Version shall be set to 1 */
++				0x00, 0x0f, 0xac, 0x07,	/* Group sipher suite */
++				0x01, 0x00,	/* Pairwise cipher suite count */
++	0x00, 0x0f, 0xac, 0x04,	/* Pairwise cipher suite list; CCMP only */
++				0x01, 0x00,	/* AKM suite count */
++				0x00, 0x0f, 0xac, 0x07,	/* TPK Handshake */
++				0x0c, 0x02,
++				/* PMKID shall not be present */
++			   };
++
++static u8 TDLS_WMMIE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00};	/* Qos info all set zero */
++
++static u8 TDLS_WMM_PARAM_IE[] = {0x00, 0x00, 0x03, 0xa4, 0x00, 0x00, 0x27, 0xa4, 0x00, 0x00, 0x42, 0x43, 0x5e, 0x00, 0x62, 0x32, 0x2f, 0x00};
++
++static u8 TDLS_EXT_CAPIE[] = {0x00, 0x00, 0x00, 0x50, 0x20, 0x00, 0x00, 0x00};	/* bit(28), bit(30), bit(37) */
++
++/* SRC: Supported Regulatory Classes */
++static u8 TDLS_SRC[] = { 0x01, 0x01, 0x02, 0x03, 0x04, 0x0c, 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1d, 0x1e, 0x20, 0x21 };
++
++int check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len);
++int check_ap_tdls_ch_switching_prohibited(u8 *pframe, u8 pkt_len);
++
++void rtw_set_tdls_enable(_adapter *padapter, u8 enable);
++u8 rtw_is_tdls_enabled(_adapter *padapter);
++u8 rtw_is_tdls_sta_existed(_adapter *padapter);
++u8 rtw_tdls_is_setup_allowed(_adapter *padapter);
++#ifdef CONFIG_TDLS_CH_SW
++u8 rtw_tdls_is_chsw_allowed(_adapter *padapter);
++#endif
++
++void rtw_tdls_set_link_established(_adapter *adapter, bool en);
++void rtw_reset_tdls_info(_adapter *padapter);
++int rtw_init_tdls_info(_adapter *padapter);
++void rtw_free_tdls_info(struct tdls_info *ptdlsinfo);
++void rtw_free_all_tdls_sta(_adapter *padapter, u8 enqueue_cmd);
++void rtw_enable_tdls_func(_adapter *padapter);
++void rtw_disable_tdls_func(_adapter *padapter, u8 enqueue_cmd);
++int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms);
++void rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta);
++void	rtw_cancel_tdls_timer(struct sta_info *psta);
++void rtw_tdls_teardown_pre_hdl(_adapter *padapter, struct sta_info *psta);
++void rtw_tdls_teardown_post_hdl(_adapter *padapter, struct sta_info *psta, u8 enqueue_cmd);
++
++#ifdef CONFIG_TDLS_CH_SW
++void rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable);
++void rtw_tdls_ch_sw_back_to_base_chnl(_adapter *padapter);
++s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_type, u8 channel, u8 channel_offset, u16 bwmode, u16 ch_switch_time);
++void rtw_tdls_chsw_oper_done(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_WFD
++int issue_tunneled_probe_req(_adapter *padapter);
++int issue_tunneled_probe_rsp(_adapter *padapter, union recv_frame *precv_frame);
++#endif /* CONFIG_WFD */
++int issue_tdls_dis_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt);
++int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack);
++int issue_tdls_setup_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt);
++int issue_tdls_setup_cfm(_adapter *padapter, struct tdls_txmgmt *ptxmgmt);
++int issue_tdls_dis_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 privacy);
++int issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait_ack);
++int issue_tdls_peer_traffic_rsp(_adapter *padapter, struct sta_info *psta, struct tdls_txmgmt *ptxmgmt);
++int issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *psta);
++#ifdef CONFIG_TDLS_CH_SW
++int issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta);
++int issue_tdls_ch_switch_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack);
++#endif
++sint On_TDLS_Dis_Rsp(_adapter *adapter, union recv_frame *precv_frame);
++sint On_TDLS_Setup_Req(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
++int On_TDLS_Setup_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
++int On_TDLS_Setup_Cfm(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
++int On_TDLS_Dis_Req(_adapter *adapter, union recv_frame *precv_frame);
++int On_TDLS_Teardown(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
++int On_TDLS_Peer_Traffic_Indication(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
++int On_TDLS_Peer_Traffic_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
++#ifdef CONFIG_TDLS_CH_SW
++sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
++sint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
++void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
++void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
++#endif
++void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
++void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
++void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
++void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
++void rtw_build_tdls_dis_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt);
++void rtw_build_tdls_dis_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, u8 privacy);
++void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
++void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
++void rtw_build_tunneled_probe_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe);
++void rtw_build_tunneled_probe_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe);
++
++int rtw_tdls_is_driver_setup(_adapter *padapter);
++void rtw_tdls_set_key(_adapter *padapter, struct sta_info *ptdls_sta);
++const char *rtw_tdls_action_txt(enum TDLS_ACTION_FIELD action);
++#endif /* CONFIG_TDLS */
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_version.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_version.h
+new file mode 100644
+index 000000000..beef4a2a9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_version.h
+@@ -0,0 +1,2 @@
++#define DRIVERVERSION	"v5.10.1-20-g5af20e016.20200310_beta"
++#define BTCOEXVERSION	"COEX20200103-3535"
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_vht.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_vht.h
+new file mode 100644
+index 000000000..93253b622
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_vht.h
+@@ -0,0 +1,181 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTW_VHT_H_
++#define _RTW_VHT_H_
++
++#define VHT_CAP_IE_LEN 12
++#define VHT_OP_IE_LEN 5
++
++#define	LDPC_VHT_ENABLE_RX			BIT0
++#define	LDPC_VHT_ENABLE_TX			BIT1
++#define	LDPC_VHT_TEST_TX_ENABLE		BIT2
++#define	LDPC_VHT_CAP_TX				BIT3
++
++#define	STBC_VHT_ENABLE_RX			BIT0
++#define	STBC_VHT_ENABLE_TX			BIT1
++#define	STBC_VHT_TEST_TX_ENABLE		BIT2
++#define	STBC_VHT_CAP_TX				BIT3
++
++/* VHT capability info */
++#define SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val)
++#define SET_VHT_CAPABILITY_ELE_CHL_WIDTH(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart, 2, 2, _val)
++#define SET_VHT_CAPABILITY_ELE_RX_LDPC(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart, 4, 1, _val)
++#define SET_VHT_CAPABILITY_ELE_SHORT_GI80M(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE(_pEleStart, 5, 1, _val)
++#define SET_VHT_CAPABILITY_ELE_SHORT_GI160M(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE(_pEleStart, 6, 1, _val)
++#define SET_VHT_CAPABILITY_ELE_TX_STBC(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE(_pEleStart, 7, 1, _val)
++#define SET_VHT_CAPABILITY_ELE_RX_STBC(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 0, 3, _val)
++#define SET_VHT_CAPABILITY_ELE_SU_BFER(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 3, 1, _val)
++#define SET_VHT_CAPABILITY_ELE_SU_BFEE(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 4, 1, _val)
++#define SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 5, 3, _val)
++#define SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 0, 3, _val)
++
++#define SET_VHT_CAPABILITY_ELE_MU_BFER(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 3, 1, _val)
++#define SET_VHT_CAPABILITY_ELE_MU_BFEE(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 4, 1, _val)
++#define SET_VHT_CAPABILITY_ELE_TXOP_PS(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 5, 1, _val)
++#define SET_VHT_CAPABILITY_ELE_HTC_VHT(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 6, 1, _val)
++#define SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(_pEleStart, _val)		SET_BITS_TO_LE_2BYTE((_pEleStart)+2, 7, 3, _val) /* B23~B25 */
++#define SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 2, 2, _val)
++#define SET_VHT_CAPABILITY_ELE_MCS_RX_MAP(_pEleStart, _val)				SET_BITS_TO_LE_2BYTE((_pEleStart)+4, 0, 16, _val)   /* B0~B15 indicate Rx MCS MAP, we write 0 to indicate MCS0~7. by page */
++#define SET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(_pEleStart, _val)				SET_BITS_TO_LE_2BYTE((_pEleStart)+6, 0, 13, _val)
++#define SET_VHT_CAPABILITY_ELE_MCS_TX_MAP(_pEleStart, _val)				SET_BITS_TO_LE_2BYTE((_pEleStart)+8, 0, 16, _val)   /* B0~B15 indicate Tx MCS MAP, we write 0 to indicate MCS0~7. by page */
++#define SET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(_pEleStart, _val)				SET_BITS_TO_LE_2BYTE((_pEleStart)+10, 0, 13, _val)
++
++
++#define GET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(_pEleStart)			LE_BITS_TO_1BYTE(_pEleStart, 0, 2)
++#define GET_VHT_CAPABILITY_ELE_CHL_WIDTH(_pEleStart)				LE_BITS_TO_1BYTE(_pEleStart, 2, 2)
++#define GET_VHT_CAPABILITY_ELE_RX_LDPC(_pEleStart)			LE_BITS_TO_1BYTE(_pEleStart, 4, 1)
++#define GET_VHT_CAPABILITY_ELE_SHORT_GI80M(_pEleStart)				LE_BITS_TO_1BYTE(_pEleStart, 5, 1)
++#define GET_VHT_CAPABILITY_ELE_SHORT_GI160M(_pEleStart)				LE_BITS_TO_1BYTE(_pEleStart, 6, 1)
++#define GET_VHT_CAPABILITY_ELE_TX_STBC(_pEleStart)				LE_BITS_TO_1BYTE(_pEleStart, 7, 1)
++#define GET_VHT_CAPABILITY_ELE_RX_STBC(_pEleStart)				LE_BITS_TO_1BYTE((_pEleStart)+1, 0, 3)
++#define GET_VHT_CAPABILITY_ELE_SU_BFER(_pEleStart)					LE_BITS_TO_1BYTE((_pEleStart)+1, 3, 1)
++#define GET_VHT_CAPABILITY_ELE_SU_BFEE(_pEleStart)					LE_BITS_TO_1BYTE((_pEleStart)+1, 4, 1)
++/*phydm-beamforming*/
++#define GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(_pEleStart)	LE_BITS_TO_2BYTE((_pEleStart)+1, 5, 3)
++#define GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(_pEleStart)	LE_BITS_TO_2BYTE((_pEleStart)+2, 0, 3)
++#define GET_VHT_CAPABILITY_ELE_MU_BFER(_pEleStart)				LE_BITS_TO_1BYTE((_pEleStart)+2, 3, 1)
++#define GET_VHT_CAPABILITY_ELE_MU_BFEE(_pEleStart)				LE_BITS_TO_1BYTE((_pEleStart)+2, 4, 1)
++#define GET_VHT_CAPABILITY_ELE_TXOP_PS(_pEleStart)				LE_BITS_TO_1BYTE((_pEleStart)+2, 5, 1)
++#define GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(_pEleStart)	LE_BITS_TO_2BYTE((_pEleStart)+2, 7, 3)
++#define GET_VHT_CAPABILITY_ELE_RX_MCS(_pEleStart)					       ((_pEleStart)+4)
++#define GET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(_pEleStart)			LE_BITS_TO_2BYTE((_pEleStart)+6, 0, 13)
++#define GET_VHT_CAPABILITY_ELE_TX_MCS(_pEleStart)					       ((_pEleStart)+8)
++#define GET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(_pEleStart)			LE_BITS_TO_2BYTE((_pEleStart)+10, 0, 13)
++
++
++/* VHT Operation Information Element */
++#define SET_VHT_OPERATION_ELE_CHL_WIDTH(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 8, _val)
++#define SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart+1, 0, 8, _val)
++#define SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart+2, 0, 8, _val)
++#define SET_VHT_OPERATION_ELE_BASIC_MCS_SET(_pEleStart, _val)			SET_BITS_TO_LE_2BYTE((_pEleStart)+3, 0, 16, _val)
++
++#define GET_VHT_OPERATION_ELE_CHL_WIDTH(_pEleStart)		LE_BITS_TO_1BYTE(_pEleStart, 0, 8)
++#define GET_VHT_OPERATION_ELE_CENTER_FREQ1(_pEleStart)	LE_BITS_TO_1BYTE((_pEleStart)+1, 0, 8)
++#define GET_VHT_OPERATION_ELE_CENTER_FREQ2(_pEleStart)     LE_BITS_TO_1BYTE((_pEleStart)+2, 0, 8)
++
++/* VHT Operating Mode */
++#define SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val)
++#define SET_VHT_OPERATING_MODE_FIELD_RX_NSS(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart, 4, 3, _val)
++#define SET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(_pEleStart, 7, 1, _val)
++#define GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(_pEleStart)			LE_BITS_TO_1BYTE(_pEleStart, 0, 2)
++#define GET_VHT_OPERATING_MODE_FIELD_RX_NSS(_pEleStart)				LE_BITS_TO_1BYTE(_pEleStart, 4, 3)
++#define GET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(_pEleStart)		LE_BITS_TO_1BYTE(_pEleStart, 7, 1)
++
++#define SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE((_pEleStart)+7, 6, 1, _val)
++#define GET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(_pEleStart)				LE_BITS_TO_1BYTE((_pEleStart)+7, 6, 1)
++
++#define VHT_MAX_MPDU_LEN_MAX 3
++extern const u16 _vht_max_mpdu_len[];
++#define vht_max_mpdu_len(val) (((val) >= VHT_MAX_MPDU_LEN_MAX) ? _vht_max_mpdu_len[VHT_MAX_MPDU_LEN_MAX] : _vht_max_mpdu_len[(val)])
++
++#define VHT_SUP_CH_WIDTH_SET_MAX 3
++extern const u8 _vht_sup_ch_width_set_to_bw_cap[];
++#define vht_sup_ch_width_set_to_bw_cap(set) (((set) >= VHT_SUP_CH_WIDTH_SET_MAX) ? _vht_sup_ch_width_set_to_bw_cap[VHT_SUP_CH_WIDTH_SET_MAX] : _vht_sup_ch_width_set_to_bw_cap[(set)])
++extern const char *const _vht_sup_ch_width_set_str[];
++#define vht_sup_ch_width_set_str(set) (((set) >= VHT_SUP_CH_WIDTH_SET_MAX) ? _vht_sup_ch_width_set_str[VHT_SUP_CH_WIDTH_SET_MAX] : _vht_sup_ch_width_set_str[(set)])
++
++#define VHT_MAX_AMPDU_LEN(f) ((1 << (13 + f)) - 1)
++void dump_vht_cap_ie(void *sel, const u8 *ie, u32 ie_len);
++
++#define VHT_OP_CH_WIDTH_MAX 4
++extern const char *const _vht_op_ch_width_str[];
++#define vht_op_ch_width_str(ch_width) (((ch_width) >= VHT_OP_CH_WIDTH_MAX) ? _vht_op_ch_width_str[VHT_OP_CH_WIDTH_MAX] : _vht_op_ch_width_str[(ch_width)])
++
++void dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len);
++
++struct vht_bf_cap {
++	u8 is_mu_bfer;
++	u8 su_sound_dim;
++};
++
++struct vht_priv {
++	u8	vht_option;
++
++	u8	ldpc_cap;
++	u8	stbc_cap;
++	u16	beamform_cap;
++	struct	vht_bf_cap ap_bf_cap;
++
++	u8	sgi_80m;/* short GI */
++	u8	ampdu_len;
++
++	u8	vht_highest_rate;
++	u8	vht_mcs_map[2];
++
++	u8 op_present:1; /* vht_op is present */
++	u8 notify_present:1; /* vht_op_mode_notify is present */
++
++	u8 vht_cap[32];
++	u8 vht_op[VHT_OP_IE_LEN];
++	u8 vht_op_mode_notify;
++};
++
++#ifdef ROKU_PRIVATE
++struct vht_priv_infra_ap {
++
++	/* Infra mode, only store for AP's info, not intersection of STA and AP*/
++	u8	ldpc_cap_infra_ap;
++	u8	stbc_cap_infra_ap;
++	u16	beamform_cap_infra_ap;
++	u8	vht_mcs_map_infra_ap[2];
++	u8	vht_mcs_map_tx_infra_ap[2];
++	u8	channel_width_infra_ap;
++	u8	number_of_streams_infra_ap;
++};
++#endif /* ROKU_PRIVATE */
++
++u8	rtw_get_vht_highest_rate(u8 *pvht_mcs_map);
++u16	rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate);
++u64	rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss);
++void	rtw_vht_use_default_setting(_adapter *padapter);
++u32	rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel);
++u32	rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw);
++u32	rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf);
++void	update_sta_vht_info_apmode(_adapter *padapter, void *psta);
++void	update_hw_vht_param(_adapter *padapter);
++void	VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
++#ifdef ROKU_PRIVATE
++void	VHT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
++#endif /* ROKU_PRIVATE */
++void	VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
++void	rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, void *sta);
++u32	rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len);
++void	VHTOnAssocRsp(_adapter *padapter);
++u8	rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map);
++void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map);
++void rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pcur_network);
++void rtw_vht_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pcur_network);
++void rtw_check_for_vht20(_adapter *adapter, u8 *ies, int ies_len);
++#endif /* _RTW_VHT_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_wapi.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_wapi.h
+new file mode 100644
+index 000000000..512bb7f30
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_wapi.h
+@@ -0,0 +1,230 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_WAPI_H
++#define __INC_WAPI_H
++
++
++#define CONFIG_WAPI_SW_SMS4
++#define WAPI_DEBUG
++
++#define SMS4_MIC_LEN                16
++#define WAPI_EXT_LEN                18
++#define MAX_WAPI_IE_LEN		    256
++#define sMacHdrLng				24		/* octets in data header, no WEP */
++
++#ifdef WAPI_DEBUG
++
++/* WAPI trace debug */
++extern u32 wapi_debug_component;
++
++static inline void dump_buf(u8 *buf, u32 len)
++{
++	u32 i;
++	printk("-----------------Len %d----------------\n", len);
++	for (i = 0; i < len; i++)
++		printk("%2.2x-", *(buf + i));
++	printk("\n");
++}
++
++#define WAPI_TRACE(component, x, args...) \
++	do { if (wapi_debug_component & (component)) \
++			printk(KERN_DEBUG "WAPI" ":" x "" , \
++			       ##args);\
++	} while (0);
++
++#define WAPI_DATA(component, x, buf, len) \
++	do { if (wapi_debug_component & (component)) { \
++			printk("%s:\n", x);\
++			dump_buf((buf), (len)); } \
++	} while (0);
++
++#define RT_ASSERT_RET(_Exp)								\
++	if (!(_Exp)) {									\
++		printk("RTWLAN: ");					\
++		printk("Assertion failed! %s,%s, line=%d\n", \
++		       #_Exp, __FUNCTION__, __LINE__);          \
++		return;						\
++	}
++#define RT_ASSERT_RET_VALUE(_Exp, Ret)								\
++	if (!(_Exp)) {									\
++		printk("RTWLAN: ");					\
++		printk("Assertion failed! %s,%s, line=%d\n", \
++		       #_Exp, __FUNCTION__, __LINE__);          \
++		return Ret;						\
++	}
++
++#else
++#define RT_ASSERT_RET(_Exp) do {} while (0)
++#define RT_ASSERT_RET_VALUE(_Exp, Ret) do {} while (0)
++#define WAPI_TRACE(component, x, args...) do {} while (0)
++#define WAPI_DATA(component, x, buf, len) do {} while (0)
++#endif
++
++
++enum WAPI_DEBUG {
++	WAPI_INIT				= 1,
++	WAPI_API				= 1 << 1,
++	WAPI_TX				= 1 << 2,
++	WAPI_RX				= 1 << 3,
++	WAPI_MLME				= 1 << 4,
++	WAPI_IOCTL				= 1 << 5,
++	WAPI_ERR			= 1 << 31
++};
++
++#define			WAPI_MAX_BKID_NUM				4
++#define			WAPI_MAX_STAINFO_NUM			4
++#define			WAPI_CAM_ENTRY_NUM			14	/* 28/2 = 14 */
++
++typedef struct  _RT_WAPI_BKID {
++	struct list_head	list;
++	u8				bkid[16];
++} RT_WAPI_BKID, *PRT_WAPI_BKID;
++
++typedef struct  _RT_WAPI_KEY {
++	u8			dataKey[16];
++	u8			micKey[16];
++	u8			keyId;
++	bool			bSet;
++	bool             bTxEnable;
++} RT_WAPI_KEY, *PRT_WAPI_KEY;
++
++typedef enum _RT_WAPI_PACKET_TYPE {
++	WAPI_NONE = 0,
++	WAPI_PREAUTHENTICATE = 1,
++	WAPI_STAKEY_REQUEST = 2,
++	WAPI_AUTHENTICATE_ACTIVE = 3,
++	WAPI_ACCESS_AUTHENTICATE_REQUEST = 4,
++	WAPI_ACCESS_AUTHENTICATE_RESPONSE = 5,
++	WAPI_CERTIFICATE_AUTHENTICATE_REQUEST = 6,
++	WAPI_CERTIFICATE_AUTHENTICATE_RESPONSE = 7,
++	WAPI_USK_REQUEST = 8,
++	WAPI_USK_RESPONSE = 9,
++	WAPI_USK_CONFIRM = 10,
++	WAPI_MSK_NOTIFICATION = 11,
++	WAPI_MSK_RESPONSE = 12
++} RT_WAPI_PACKET_TYPE;
++
++typedef struct	_RT_WAPI_STA_INFO {
++	struct list_head		list;
++	u8					PeerMacAddr[6];
++	RT_WAPI_KEY		      wapiUsk;
++	RT_WAPI_KEY		      wapiUskUpdate;
++	RT_WAPI_KEY		      wapiMsk;
++	RT_WAPI_KEY		      wapiMskUpdate;
++	u8					lastRxUnicastPN[16];
++	u8					lastTxUnicastPN[16];
++	u8					lastRxMulticastPN[16];
++	u8					lastRxUnicastPNBEQueue[16];
++	u8					lastRxUnicastPNBKQueue[16];
++	u8					lastRxUnicastPNVIQueue[16];
++	u8					lastRxUnicastPNVOQueue[16];
++	bool					bSetkeyOk;
++	bool					bAuthenticateInProgress;
++	bool					bAuthenticatorInUpdata;
++} RT_WAPI_STA_INFO, *PRT_WAPI_STA_INFO;
++
++/* Added for HW wapi en/decryption */
++typedef struct _RT_WAPI_CAM_ENTRY {
++	/* RT_LIST_ENTRY		list; */
++	u8			IsUsed;
++	u8			entry_idx;/* for cam entry */
++	u8			keyidx;	/* 0 or 1,new or old key */
++	u8			PeerMacAddr[6];
++	u8			type;	/* should be 110,wapi */
++} RT_WAPI_CAM_ENTRY, *PRT_WAPI_CAM_ENTRY;
++
++typedef struct _RT_WAPI_T {
++	/* BKID */
++	RT_WAPI_BKID		wapiBKID[WAPI_MAX_BKID_NUM];
++	struct list_head		wapiBKIDIdleList;
++	struct list_head		wapiBKIDStoreList;
++	/* Key for Tx Multicast/Broadcast */
++	RT_WAPI_KEY		      wapiTxMsk;
++
++	/* sec related */
++	u8				lastTxMulticastPN[16];
++	/* STA list */
++	RT_WAPI_STA_INFO	wapiSta[WAPI_MAX_STAINFO_NUM];
++	struct list_head		wapiSTAIdleList;
++	struct list_head		wapiSTAUsedList;
++	/*  */
++	bool				bWapiEnable;
++
++	/* store WAPI IE */
++	u8				wapiIE[256];
++	u8				wapiIELength;
++	bool				bWapiPSK;
++	/* last sequece number for wai packet */
++	u16				wapiSeqnumAndFragNum;
++	int extra_prefix_len;
++	int extra_postfix_len;
++
++	RT_WAPI_CAM_ENTRY	wapiCamEntry[WAPI_CAM_ENTRY_NUM];
++} RT_WAPI_T, *PRT_WAPI_T;
++
++typedef struct _WLAN_HEADER_WAPI_EXTENSION {
++	u8      KeyIdx;
++	u8      Reserved;
++	u8      PN[16];
++} WLAN_HEADER_WAPI_EXTENSION, *PWLAN_HEADER_WAPI_EXTENSION;
++
++u32 WapiComparePN(u8 *PN1, u8 *PN2);
++
++
++void rtw_wapi_init(_adapter *padapter);
++
++void rtw_wapi_free(_adapter *padapter);
++
++void rtw_wapi_disable_tx(_adapter *padapter);
++
++u8 rtw_wapi_is_wai_packet(_adapter *padapter, u8 *pkt_data);
++
++void rtw_wapi_update_info(_adapter *padapter, union recv_frame *precv_frame);
++
++u8 rtw_wapi_check_for_drop(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_ops);
++
++void rtw_build_probe_resp_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib);
++
++void rtw_build_beacon_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib);
++
++void rtw_build_assoc_req_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib);
++
++void rtw_wapi_on_assoc_ok(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
++
++void rtw_wapi_return_one_sta_info(_adapter *padapter, u8 *MacAddr);
++
++void rtw_wapi_return_all_sta_info(_adapter *padapter);
++
++void rtw_wapi_clear_cam_entry(_adapter *padapter, u8 *pMacAddr);
++
++void rtw_wapi_clear_all_cam_entry(_adapter *padapter);
++
++void rtw_wapi_set_key(_adapter *padapter, RT_WAPI_KEY *pWapiKey, RT_WAPI_STA_INFO *pWapiSta, u8 bGroupKey, u8 bUseDefaultKey);
++
++int rtw_wapi_create_event_send(_adapter *padapter, u8 EventId, u8 *MacAddr, u8 *Buff, u16 BufLen);
++
++u32	rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe);
++
++u32	rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe);
++
++void rtw_wapi_get_iv(_adapter *padapter, u8 *pRA, u8 *IV);
++
++u8 WapiIncreasePN(u8 *PN, u8 AddCount);
++
++bool rtw_wapi_drop_for_key_absent(_adapter *padapter, u8 *pRA);
++
++void rtw_wapi_set_set_encryption(_adapter *padapter, struct ieee_param *param);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_wnm.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_wnm.h
+new file mode 100755
+index 000000000..4eb07b364
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_wnm.h
+@@ -0,0 +1,169 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __RTW_WNM_H_
++#define __RTW_WNM_H_
++
++#define RTW_RRM_NB_RPT_EN		BIT(1)
++#define RTW_MAX_NB_RPT_NUM	8
++
++#define rtw_roam_busy_scan(a, nb)	\
++	(((a)->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE) && \
++	(((a)->mlmepriv.ch_cnt) < ((nb)->nb_rpt_ch_list_num)))
++
++#define rtw_wnm_btm_preference_cap(a) \
++	((a)->mlmepriv.nb_info.preference_en == _TRUE)
++
++#define rtw_wnm_btm_roam_triggered(a) \
++	(((a)->mlmepriv.nb_info.preference_en == _TRUE) \
++	&& (rtw_ft_chk_flags((a), RTW_FT_BTM_ROAM))	\
++	)
++
++#define rtw_wnm_btm_diff_bss(a) \
++	((rtw_wnm_btm_preference_cap(a)) && \
++	(is_zero_mac_addr((a)->mlmepriv.nb_info.roam_target_addr) == _FALSE) && \
++	(_rtw_memcmp((a)->mlmepriv.nb_info.roam_target_addr,\
++		(a)->mlmepriv.cur_network.network.MacAddress, ETH_ALEN) == _FALSE))
++
++#define rtw_wnm_btm_roam_candidate(a, c) \
++	((rtw_wnm_btm_preference_cap(a)) && \
++	(is_zero_mac_addr((a)->mlmepriv.nb_info.roam_target_addr) == _FALSE) && \
++	(_rtw_memcmp((a)->mlmepriv.nb_info.roam_target_addr,\
++		(c)->network.MacAddress, ETH_ALEN)))
++
++#define rtw_wnm_set_ext_cap_btm(_pEleStart, _val) \
++	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+2, 3, 1, _val)
++
++#define wnm_btm_bss_term_inc(p) (*((u8 *)((p)+3)) & BSS_TERMINATION_INCLUDED)
++
++#define wnm_btm_ess_disassoc_im(p) (*((u8 *)((p)+3)) & ESS_DISASSOC_IMMINENT)
++
++#define wnm_btm_dialog_token(p) (*((u8 *)((p)+2)))
++
++#define wnm_btm_req_mode(p) (*((u8 *)((p)+3)))
++
++#define wnm_btm_disassoc_timer(p) (*((u16 *)((p)+4)))
++
++#define wnm_btm_valid_interval(p) (*((u8 *)((p)+6)))
++
++#define wnm_btm_term_duration_offset(p) ((p)+7)
++
++#define RTW_WLAN_ACTION_WNM_NB_RPT_ELEM	0x34
++
++enum rtw_ieee80211_wnm_actioncode {
++	RTW_WLAN_ACTION_WNM_BTM_QUERY = 6,
++	RTW_WLAN_ACTION_WNM_BTM_REQ = 7,
++	RTW_WLAN_ACTION_WNM_BTM_RSP = 8,
++	RTW_WLAN_ACTION_WNM_NOTIF_REQ = 26,
++	RTW_WLAN_ACTION_WNM_NOTIF_RSP = 27,	
++};
++
++/*IEEE Std 80211k Figure 7-95b Neighbor Report element format*/
++struct nb_rpt_hdr {
++	u8 id; /*0x34: Neighbor Report Element ID*/
++	u8 len;
++	u8 bssid[ETH_ALEN];
++	u32 bss_info;
++	u8 reg_class;
++	u8 ch_num;
++	u8 phy_type;	
++};
++
++/*IEEE Std 80211v, Figure 7-9 BSS Termination Duration subelement field format */
++struct btm_term_duration {
++	u8 id;
++	u8 len;
++	u64 tsf;		/* value of the TSF counter when BSS termination will occur in the future */
++	u16 duration;		/* number of minutes for which the BSS is not present*/
++};
++
++/*IEEE Std 80211v, Figure 7-10 BSS Transition Management Request frame body format */
++struct btm_req_hdr {
++	u8 dialog_token;
++	u8 req_mode;
++	/* number of TBTTs until the AP sends a Disassociation frame to this STA */
++	u16 disassoc_timer;
++	/* number of TBTTs until the BSS transition candidate list is no longer valid */
++	u8 validity_interval;
++	struct btm_term_duration term_duration;
++};
++
++struct btm_rpt_cache {
++	u8 dialog_token;
++	u8 req_mode;
++	u16 disassoc_timer;
++	u8 validity_interval;
++	struct btm_term_duration term_duration;
++
++	/* from BTM req */
++	u32 validity_time;
++	u32 disassoc_time;
++	
++	systime req_stime;
++};
++
++/*IEEE Std 80211v,  Table 7-43b Optional Subelement IDs for Neighbor Report*/
++/* BSS Transition Candidate Preference */
++#define WNM_BTM_CAND_PREF_SUBEID 0x03
++
++/* BSS Termination Duration */
++#define WNM_BTM_TERM_DUR_SUBEID		0x04
++
++struct wnm_btm_cant {
++	struct nb_rpt_hdr nb_rpt;
++	u8 preference;	/* BSS Transition Candidate Preference */
++};
++
++enum rtw_btm_req_mod {
++	PREFERRED_CANDIDATE_LIST_INCLUDED = BIT0,
++	ABRIDGED = BIT1,
++	DISASSOC_IMMINENT = BIT2,
++	BSS_TERMINATION_INCLUDED = BIT3,
++	ESS_DISASSOC_IMMINENT = BIT4,
++};
++
++struct roam_nb_info {
++	struct nb_rpt_hdr nb_rpt[RTW_MAX_NB_RPT_NUM];
++	struct rtw_ieee80211_channel nb_rpt_ch_list[RTW_MAX_NB_RPT_NUM];
++	struct btm_rpt_cache btm_cache;
++	bool	nb_rpt_valid;
++	u8	nb_rpt_ch_list_num;
++	u8 preference_en;
++	u8 roam_target_addr[ETH_ALEN];
++	u32	last_nb_rpt_entries;
++	u8 nb_rpt_is_same;
++	s8 disassoc_waiting;
++	_timer roam_scan_timer;
++	_timer disassoc_chk_timer;	
++};
++
++u8 rtw_wnm_btm_reassoc_req(_adapter *padapter);
++void rtw_wnm_roam_scan_hdl(void *ctx);
++void rtw_wnm_disassoc_chk_hdl(void *ctx);
++u8 rtw_wnm_try_btm_roam_imnt(_adapter *padapter);
++void rtw_wnm_process_btm_req(_adapter *padapter,  u8* pframe, u32 frame_len);
++void rtw_wnm_reset_btm_candidate(struct roam_nb_info *pnb);
++void rtw_wnm_reset_btm_state(_adapter *padapter);
++void rtw_wnm_reset_btm_cache(_adapter *padapter);
++void rtw_wnm_issue_action(_adapter *padapter, u8 action, u8 reason, u8 dialog);
++void rtw_wnm_update_reassoc_req_ie(_adapter *padapter);
++
++void rtw_roam_nb_info_init(_adapter *padapter);
++u8 rtw_roam_nb_scan_list_set(
++	_adapter *padapter, struct sitesurvey_parm *pparm);
++u32 rtw_wnm_btm_candidates_survey(_adapter *padapter, 
++	u8* pframe, u32 elem_len, u8 is_preference);
++#endif /* __RTW_WNM_H_ */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_xmit.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_xmit.h
+new file mode 100644
+index 000000000..b0f845ae3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/rtw_xmit.h
+@@ -0,0 +1,1085 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _RTW_XMIT_H_
++#define _RTW_XMIT_H_
++
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	#ifdef CONFIG_TX_AGGREGATION
++		#ifdef CONFIG_RTL8822C
++			#ifdef CONFIG_SDIO_TX_FORMAT_DUMMY_AUTO
++				#define MAX_XMITBUF_SZ	(51200)
++			#else
++				#define MAX_XMITBUF_SZ	(32764)
++			#endif
++		#else
++			#define MAX_XMITBUF_SZ	(20480)	/* 20k */
++		#endif
++		/* #define SDIO_TX_AGG_MAX	5 */
++	#else
++		#define MAX_XMITBUF_SZ (1664)
++		#define SDIO_TX_AGG_MAX	1
++	#endif
++
++	#if defined CONFIG_SDIO_HCI
++		#define NR_XMITBUFF	(16)
++		#define SDIO_TX_DIV_NUM (2)
++	#endif
++	#if defined(CONFIG_GSPI_HCI)
++		#define NR_XMITBUFF	(128)
++	#endif
++
++#elif defined (CONFIG_USB_HCI)
++
++	#ifdef CONFIG_USB_TX_AGGREGATION
++		#if defined(CONFIG_PLATFORM_ARM_SUNxI) || defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) || defined(CONFIG_PLATFORM_ARM_SUN8I) || defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)
++			#define MAX_XMITBUF_SZ (12288)  /* 12k 1536*8 */
++		#elif defined (CONFIG_PLATFORM_MSTAR)
++			#define MAX_XMITBUF_SZ	7680	/* 7.5k */
++		#else
++			#define MAX_XMITBUF_SZ	(20480)	/* 20k */
++		#endif
++	#else
++		#define MAX_XMITBUF_SZ	(2048)
++	#endif
++
++	#ifdef CONFIG_SINGLE_XMIT_BUF
++		#define NR_XMITBUFF	(1)
++	#else
++		#define NR_XMITBUFF	(4)
++	#endif /* CONFIG_SINGLE_XMIT_BUF */
++#elif defined (CONFIG_PCI_HCI)
++#ifdef CONFIG_TX_AMSDU
++	#define MAX_XMITBUF_SZ	(3500)
++#else
++	#define MAX_XMITBUF_SZ	(1664)
++#endif
++#ifdef CONFIG_PCI_TX_POLLING
++	#define NR_XMITBUFF	(256)
++#else
++	#define NR_XMITBUFF	(128)
++#endif
++#endif
++
++
++#ifdef CONFIG_PCI_HCI
++	#define XMITBUF_ALIGN_SZ 4
++#else
++	#ifdef USB_XMITBUF_ALIGN_SZ
++		#define XMITBUF_ALIGN_SZ (USB_XMITBUF_ALIGN_SZ)
++	#else
++		#define XMITBUF_ALIGN_SZ 512
++	#endif
++#endif
++
++
++/* xmit extension buff defination */
++#define MAX_XMIT_EXTBUF_SZ	(1536)
++
++#ifdef CONFIG_SINGLE_XMIT_BUF
++	#define NR_XMIT_EXTBUFF	(1)
++#else
++	#define NR_XMIT_EXTBUFF	(32)
++#endif
++
++#ifdef CONFIG_RTL8812A
++	#define MAX_CMDBUF_SZ	(512 * 18)
++#elif defined(CONFIG_RTL8723D) && defined(CONFIG_LPS_POFF)
++	#define MAX_CMDBUF_SZ	(128*70) /*(8960)*/
++#else
++	#define MAX_CMDBUF_SZ	(5120)	/* (4096) */
++#endif
++
++#define MAX_BEACON_LEN	512
++
++#define MAX_NUMBLKS		(1)
++
++#define XMIT_VO_QUEUE (0)
++#define XMIT_VI_QUEUE (1)
++#define XMIT_BE_QUEUE (2)
++#define XMIT_BK_QUEUE (3)
++
++#define VO_QUEUE_INX		0
++#define VI_QUEUE_INX		1
++#define BE_QUEUE_INX		2
++#define BK_QUEUE_INX		3
++#define BCN_QUEUE_INX		4
++#define MGT_QUEUE_INX		5
++#define HIGH_QUEUE_INX		6
++#define TXCMD_QUEUE_INX	7
++
++#define HW_QUEUE_ENTRY	8
++
++#ifdef CONFIG_PCI_HCI
++	#ifdef CONFIG_TRX_BD_ARCH
++		#define TX_BD_NUM			(128+1)	/* +1 result from ring buffer */
++	#else
++		#define TXDESC_NUM			128
++	#endif
++#endif
++
++#define WEP_IV(pattrib_iv, dot11txpn, keyidx)\
++	do {\
++		dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0 : (dot11txpn.val + 1);\
++		pattrib_iv[0] = dot11txpn._byte_.TSC0;\
++		pattrib_iv[1] = dot11txpn._byte_.TSC1;\
++		pattrib_iv[2] = dot11txpn._byte_.TSC2;\
++		pattrib_iv[3] = ((keyidx & 0x3)<<6);\
++	} while (0)
++
++
++#define TKIP_IV(pattrib_iv, dot11txpn, keyidx)\
++	do {\
++		dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\
++		pattrib_iv[0] = dot11txpn._byte_.TSC1;\
++		pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\
++		pattrib_iv[2] = dot11txpn._byte_.TSC0;\
++		pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\
++		pattrib_iv[4] = dot11txpn._byte_.TSC2;\
++		pattrib_iv[5] = dot11txpn._byte_.TSC3;\
++		pattrib_iv[6] = dot11txpn._byte_.TSC4;\
++		pattrib_iv[7] = dot11txpn._byte_.TSC5;\
++	} while (0)
++
++#define AES_IV(pattrib_iv, dot11txpn, keyidx)\
++	do {\
++		dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\
++		pattrib_iv[0] = dot11txpn._byte_.TSC0;\
++		pattrib_iv[1] = dot11txpn._byte_.TSC1;\
++		pattrib_iv[2] = 0;\
++		pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\
++		pattrib_iv[4] = dot11txpn._byte_.TSC2;\
++		pattrib_iv[5] = dot11txpn._byte_.TSC3;\
++		pattrib_iv[6] = dot11txpn._byte_.TSC4;\
++		pattrib_iv[7] = dot11txpn._byte_.TSC5;\
++	} while (0)
++
++#define GCMP_IV(a, b, c) AES_IV(a, b, c)
++
++/* Check if AMPDU Tx is supported or not. If it is supported,
++* it need to check "amsdu in ampdu" is supported or not.
++* (ampdu_en, amsdu_ampdu_en) =
++* (0, x) : AMPDU is not enable, but AMSDU is valid to send.
++* (1, 0) : AMPDU is enable, AMSDU in AMPDU is not enable. So, AMSDU is not valid to send.
++* (1, 1) : AMPDU and AMSDU in AMPDU are enable. So, AMSDU is valid to send.
++*/
++#define IS_AMSDU_AMPDU_NOT_VALID(pattrib)\
++	 ((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE))
++
++#define IS_AMSDU_AMPDU_VALID(pattrib)\
++	 !((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE))
++
++#define HWXMIT_ENTRY	4
++
++/* For Buffer Descriptor ring architecture */
++#if defined(BUF_DESC_ARCH) || defined(CONFIG_TRX_BD_ARCH)
++	#if defined(CONFIG_RTL8192E)
++		#define TX_BUFFER_SEG_NUM	1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */
++	#elif defined(CONFIG_RTL8814A)
++		#define TX_BUFFER_SEG_NUM	1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */
++	#else
++		#define TX_BUFFER_SEG_NUM	1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */
++	#endif
++#endif
++
++#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) ||\
++	defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8192E) ||\
++	defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8703B) ||\
++	defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) ||\
++	defined(CONFIG_RTL8710B) || defined(CONFIG_RTL8192F)
++	#define TXDESC_SIZE 40
++#elif defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)
++	#define TXDESC_SIZE 48		/* HALMAC_TX_DESC_SIZE_8822B */
++#elif defined(CONFIG_RTL8821C)
++	#define TXDESC_SIZE 48		/* HALMAC_TX_DESC_SIZE_8821C */
++#elif defined(CONFIG_RTL8814B)
++	#define TXDESC_SIZE (16 + 32)
++#else
++	#define TXDESC_SIZE 32 /* old IC (ex: 8188E) */
++#endif
++
++#ifdef CONFIG_TX_EARLY_MODE
++	#define EARLY_MODE_INFO_SIZE	8
++#endif
++
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	#define TXDESC_OFFSET TXDESC_SIZE
++#endif
++
++#ifdef CONFIG_USB_HCI
++	#ifdef USB_PACKET_OFFSET_SZ
++		#define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ)
++	#else
++		#define PACKET_OFFSET_SZ (8)
++	#endif
++	#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	#if defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_TRX_BD_ARCH)
++		/* this section is defined for buffer descriptor ring architecture */
++		#define TX_WIFI_INFO_SIZE (TXDESC_SIZE) /* it may add 802.11 hdr or others... */
++		/* tx desc and payload are in the same buf */
++		#define TXDESC_OFFSET (TX_WIFI_INFO_SIZE)
++	#else
++		/* tx desc and payload are NOT in the same buf */
++		#define TXDESC_OFFSET (0)
++		/* 8188ee/8723be/8812ae/8821ae has extra PCI DMA info in tx desc */
++		#define TX_DESC_NEXT_DESC_OFFSET	(TXDESC_SIZE + 8)
++	#endif
++#endif /* CONFIG_PCI_HCI */
++
++enum TXDESC_SC {
++	SC_DONT_CARE = 0x00,
++	SC_UPPER = 0x01,
++	SC_LOWER = 0x02,
++	SC_DUPLICATE = 0x03
++};
++
++#ifdef CONFIG_PCI_HCI
++	#ifndef CONFIG_TRX_BD_ARCH	/* CONFIG_TRX_BD_ARCH doesn't need this */
++		#define TXDESC_64_BYTES
++	#endif
++#elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8723B) \
++	|| defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) \
++	|| defined(CONFIG_RTL8192F)
++	#define TXDESC_40_BYTES
++#endif
++
++#ifdef CONFIG_TRX_BD_ARCH
++struct tx_buf_desc {
++#ifdef CONFIG_64BIT_DMA
++#define TX_BUFFER_SEG_SIZE	4	/* in unit of DWORD */
++#else
++#define TX_BUFFER_SEG_SIZE	2	/* in unit of DWORD */
++#endif
++	unsigned int dword[TX_BUFFER_SEG_SIZE * (2 << TX_BUFFER_SEG_NUM)];
++} __packed;
++#elif (defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)) && defined(CONFIG_PCI_HCI) /* 8192ee or 8814ae */
++/* 8192EE_TODO */
++struct tx_desc {
++	unsigned int txdw0;
++	unsigned int txdw1;
++	unsigned int txdw2;
++	unsigned int txdw3;
++	unsigned int txdw4;
++	unsigned int txdw5;
++	unsigned int txdw6;
++	unsigned int txdw7;
++};
++#else
++struct tx_desc {
++	unsigned int txdw0;
++	unsigned int txdw1;
++	unsigned int txdw2;
++	unsigned int txdw3;
++	unsigned int txdw4;
++	unsigned int txdw5;
++	unsigned int txdw6;
++	unsigned int txdw7;
++
++#if defined(TXDESC_40_BYTES) || defined(TXDESC_64_BYTES)
++	unsigned int txdw8;
++	unsigned int txdw9;
++#endif /* TXDESC_40_BYTES */
++
++#ifdef TXDESC_64_BYTES
++	unsigned int txdw10;
++	unsigned int txdw11;
++
++	/* 2008/05/15 MH Because PCIE HW memory R/W 4K limit. And now,  our descriptor */
++	/* size is 40 bytes. If you use more than 102 descriptor( 103*40>4096), HW will execute */
++	/* memoryR/W CRC error. And then all DMA fetch will fail. We must decrease descriptor */
++	/* number or enlarge descriptor size as 64 bytes. */
++	unsigned int txdw12;
++	unsigned int txdw13;
++	unsigned int txdw14;
++	unsigned int txdw15;
++#endif
++};
++#endif
++
++#ifndef CONFIG_TRX_BD_ARCH
++union txdesc {
++	struct tx_desc txdesc;
++	unsigned int value[TXDESC_SIZE >> 2];
++};
++#endif
++
++#ifdef CONFIG_PCI_HCI
++#define PCI_MAX_TX_QUEUE_COUNT	8	/* == HW_QUEUE_ENTRY */
++
++struct rtw_tx_ring {
++	unsigned char	qid;
++#ifdef CONFIG_TRX_BD_ARCH
++	struct tx_buf_desc	*buf_desc;
++#else
++	struct tx_desc	*desc;
++#endif
++	dma_addr_t	dma;
++	unsigned int	idx;
++	unsigned int	entries;
++	_queue		queue;
++	u32		qlen;
++#ifdef CONFIG_TRX_BD_ARCH
++	u16		hw_rp_cache;
++#endif
++};
++
++#ifdef DBG_TXBD_DESC_DUMP
++
++#define TX_BAK_FRMAE_CNT	10
++#define TX_BAK_DESC_LEN	48	/* byte */
++#define TX_BAK_DATA_LEN		30	/* byte */
++
++struct rtw_tx_desc_backup {
++	int tx_bak_rp;
++	int tx_bak_wp;
++	u8 tx_bak_desc[TX_BAK_DESC_LEN];
++	u8 tx_bak_data_hdr[TX_BAK_DATA_LEN];
++	u8 tx_desc_size;
++};
++#endif
++#endif
++
++struct	hw_xmit	{
++	/* _lock xmit_lock; */
++	/* _list	pending; */
++	_queue *sta_queue;
++	/* struct hw_txqueue *phwtxqueue; */
++	/* sint	txcmdcnt; */
++	int	accnt;
++};
++
++#if 0
++struct pkt_attrib {
++	u8	type;
++	u8	subtype;
++	u8	bswenc;
++	u8	dhcp_pkt;
++	u16	ether_type;
++	int	pktlen;		/* the original 802.3 pkt raw_data len (not include ether_hdr data) */
++	int	pkt_hdrlen;	/* the original 802.3 pkt header len */
++	int	hdrlen;		/* the WLAN Header Len */
++	int	nr_frags;
++	int	last_txcmdsz;
++	int	encrypt;	/* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */
++	u8	iv[8];
++	int	iv_len;
++	u8	icv[8];
++	int	icv_len;
++	int	priority;
++	int	ack_policy;
++	int	mac_id;
++	int	vcs_mode;	/* virtual carrier sense method */
++
++	u8	dst[ETH_ALEN];
++	u8	src[ETH_ALEN];
++	u8	ta[ETH_ALEN];
++	u8	ra[ETH_ALEN];
++
++	u8	key_idx;
++
++	u8	qos_en;
++	u8	ht_en;
++	u8	raid;/* rate adpative id */
++	u8	bwmode;
++	u8	ch_offset;/* PRIME_CHNL_OFFSET */
++	u8	sgi;/* short GI */
++	u8	ampdu_en;/* tx ampdu enable */
++	u8	mdata;/* more data bit */
++	u8	eosp;
++
++	u8	triggered;/* for ap mode handling Power Saving sta */
++
++	u32	qsel;
++	u16	seqnum;
++
++	struct sta_info *psta;
++};
++#else
++/* reduce size */
++struct pkt_attrib {
++	u8	type;
++	u8	subtype;
++	u8	bswenc;
++	u8	dhcp_pkt;
++	u16	ether_type;
++	u16	seqnum;
++	u8	hw_ssn_sel;	/* for HW_SEQ0,1,2,3 */
++	u16	pkt_hdrlen;	/* the original 802.3 pkt header len */
++	u16	hdrlen;		/* the WLAN Header Len */
++	u32	pktlen;		/* the original 802.3 pkt raw_data len (not include ether_hdr data) */
++	u32	last_txcmdsz;
++	u8	nr_frags;
++	u8	encrypt;	/* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */
++	u8	bmc_camid;
++	u8	iv_len;
++	u8	icv_len;
++	u8	iv[18];
++	u8	icv[16];
++	u8	priority;
++	u8	ack_policy;
++	u8	mac_id;
++	u8	vcs_mode;	/* virtual carrier sense method */
++	u8	dst[ETH_ALEN];
++	u8	src[ETH_ALEN];
++	u8	ta[ETH_ALEN];
++	u8	ra[ETH_ALEN];
++#ifdef CONFIG_RTW_WDS
++	u8	wds;
++#endif
++#ifdef CONFIG_RTW_MESH
++	u8	mda[ETH_ALEN];	/* mesh da */
++	u8	msa[ETH_ALEN];	/* mesh sa */
++	u8	meshctrl_len;	/* Length of Mesh Control field */
++	u8	mesh_frame_mode;
++	#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++	u8 mb2u;
++	#endif
++	u8 mfwd_ttl;
++	u32 mseq;
++#endif
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
++	u8	hw_csum;
++#endif
++	u8	key_idx;
++	u8	qos_en;
++	u8	ht_en;
++	u8	raid;/* rate adpative id */
++	u8	bwmode;
++	u8	ch_offset;/* PRIME_CHNL_OFFSET */
++	u8	sgi;/* short GI */
++	u8	ampdu_en;/* tx ampdu enable */
++	u8	ampdu_spacing; /* ampdu_min_spacing for peer sta's rx */
++	u8	amsdu;
++	u8	amsdu_ampdu_en;/* tx amsdu in ampdu enable */
++	u8	mdata;/* more data bit */
++	u8	pctrl;/* per packet txdesc control enable */
++	u8	triggered;/* for ap mode handling Power Saving sta */
++	u8	qsel;
++	u8	order;/* order bit */
++	u8	eosp;
++	u8	rate;
++	u8	intel_proxim;
++	u8	retry_ctrl;
++	u8   mbssid;
++	u8	ldpc;
++	u8	stbc;
++#ifdef CONFIG_WMMPS_STA
++	u8	trigger_frame;
++#endif /* CONFIG_WMMPS_STA */
++	
++	struct sta_info *psta;
++
++	u8 rtsen;
++	u8 cts2self;
++	union Keytype	dot11tkiptxmickey;
++	/* union Keytype	dot11tkiprxmickey; */
++	union Keytype	dot118021x_UncstKey;
++
++#ifdef CONFIG_TDLS
++	u8 direct_link;
++	struct sta_info *ptdls_sta;
++#endif /* CONFIG_TDLS */
++	u8 key_type;
++
++	u8 icmp_pkt;
++	u8 hipriority_pkt; /* high priority packet */
++
++#ifdef CONFIG_BEAMFORMING
++	u16 txbf_p_aid;/*beamforming Partial_AID*/
++	u16 txbf_g_id;/*beamforming Group ID*/
++
++	/*
++	 * 2'b00: Unicast NDPA
++	 * 2'b01: Broadcast NDPA
++	 * 2'b10: Beamforming Report Poll
++	 * 2'b11: Final Beamforming Report Poll
++	 */
++	u8 bf_pkt_type;
++#endif
++
++};
++#endif
++
++#ifdef CONFIG_RTW_WDS
++#define XATTRIB_GET_WDS(xattrib) ((xattrib)->wds)
++#else
++#define XATTRIB_GET_WDS(xattrib) 0
++#endif
++
++#ifdef CONFIG_RTW_MESH
++#define XATTRIB_GET_MCTRL_LEN(xattrib) ((xattrib)->meshctrl_len)
++#else
++#define XATTRIB_GET_MCTRL_LEN(xattrib) 0
++#endif
++
++#ifdef CONFIG_TX_AMSDU
++enum {
++	RTW_AMSDU_TIMER_UNSET = 0,
++	RTW_AMSDU_TIMER_SETTING,
++	RTW_AMSDU_TIMER_TIMEOUT,
++};
++#endif
++
++#define WLANHDR_OFFSET	64
++
++#define NULL_FRAMETAG		(0x0)
++#define DATA_FRAMETAG		0x01
++#define L2_FRAMETAG		0x02
++#define MGNT_FRAMETAG		0x03
++#define AMSDU_FRAMETAG	0x04
++
++#define EII_FRAMETAG		0x05
++#define IEEE8023_FRAMETAG  0x06
++
++#define MP_FRAMETAG		0x07
++
++#define TXAGG_FRAMETAG	0x08
++
++enum {
++	XMITBUF_DATA = 0,
++	XMITBUF_MGNT = 1,
++	XMITBUF_CMD = 2,
++};
++
++bool rtw_xmit_ac_blocked(_adapter *adapter);
++
++struct  submit_ctx {
++	systime submit_time; /* */
++	u32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */
++	int status; /* status for operation */
++#ifdef PLATFORM_LINUX
++	struct completion done;
++#endif
++};
++
++enum {
++	RTW_SCTX_SUBMITTED = -1,
++	RTW_SCTX_DONE_SUCCESS = 0,
++	RTW_SCTX_DONE_UNKNOWN,
++	RTW_SCTX_DONE_TIMEOUT,
++	RTW_SCTX_DONE_BUF_ALLOC,
++	RTW_SCTX_DONE_BUF_FREE,
++	RTW_SCTX_DONE_WRITE_PORT_ERR,
++	RTW_SCTX_DONE_TX_DESC_NA,
++	RTW_SCTX_DONE_TX_DENY,
++	RTW_SCTX_DONE_CCX_PKT_FAIL,
++	RTW_SCTX_DONE_DRV_STOP,
++	RTW_SCTX_DONE_DEV_REMOVE,
++	RTW_SCTX_DONE_CMD_ERROR,
++	RTW_SCTX_DONE_CMD_DROP,
++	RTX_SCTX_CSTR_WAIT_RPT2,
++};
++
++
++void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms);
++int rtw_sctx_wait(struct submit_ctx *sctx, const char *msg);
++void rtw_sctx_done_err(struct submit_ctx **sctx, int status);
++void rtw_sctx_done(struct submit_ctx **sctx);
++
++struct xmit_buf {
++	_list	list;
++
++	_adapter *padapter;
++
++	u8 *pallocated_buf;
++
++	u8 *pbuf;
++
++	void *priv_data;
++
++	u16 buf_tag; /* 0: Normal xmitbuf, 1: extension xmitbuf, 2:cmd xmitbuf */
++	u16 flags;
++	u32 alloc_sz;
++
++	u32  len;
++
++	struct submit_ctx *sctx;
++
++#ifdef CONFIG_USB_HCI
++
++	/* u32 sz[8]; */
++	u32	ff_hwaddr;
++#ifdef RTW_HALMAC
++	u8 bulkout_id; /* for halmac */
++#endif /* RTW_HALMAC */
++
++	PURB	pxmit_urb[8];
++	dma_addr_t dma_transfer_addr;	/* (in) dma addr for transfer_buffer */
++
++	u8 bpending[8];
++
++	sint last[8];
++
++#endif
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	u8 *phead;
++	u8 *pdata;
++	u8 *ptail;
++	u8 *pend;
++	u32 ff_hwaddr;
++	u8	pg_num;
++	u8	agg_num;
++#endif
++
++#ifdef CONFIG_PCI_HCI
++#ifdef CONFIG_TRX_BD_ARCH
++	/*struct tx_buf_desc *buf_desc;*/
++#else
++	struct tx_desc *desc;
++#endif
++#endif
++
++#if defined(DBG_XMIT_BUF) || defined(DBG_XMIT_BUF_EXT)
++	u8 no;
++#endif
++
++};
++
++
++struct xmit_frame {
++	_list	list;
++
++	struct pkt_attrib attrib;
++
++	u16 os_qid;
++	_pkt *pkt;
++
++	int	frame_tag;
++
++	_adapter *padapter;
++
++	u8	*buf_addr;
++
++	struct xmit_buf *pxmitbuf;
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	u8	pg_num;
++	u8	agg_num;
++#endif
++
++#ifdef CONFIG_USB_HCI
++#ifdef CONFIG_USB_TX_AGGREGATION
++	u8	agg_num;
++#endif
++	s8	pkt_offset;
++#endif
++
++#ifdef CONFIG_XMIT_ACK
++	u8 ack_report;
++#endif
++
++	u8 *alloc_addr; /* the actual address this xmitframe allocated */
++	u8 ext_tag; /* 0:data, 1:mgmt */
++
++};
++
++struct tx_servq {
++	_list	tx_pending;
++	_queue	sta_pending;
++	int qcnt;
++};
++
++
++struct sta_xmit_priv {
++	_lock	lock;
++	sint	option;
++	sint	apsd_setting;	/* When bit mask is on, the associated edca queue supports APSD. */
++
++
++	/* struct tx_servq blk_q[MAX_NUMBLKS]; */
++	struct tx_servq	be_q;			/* priority == 0,3 */
++	struct tx_servq	bk_q;			/* priority == 1,2 */
++	struct tx_servq	vi_q;			/* priority == 4,5 */
++	struct tx_servq	vo_q;			/* priority == 6,7 */
++	_list	legacy_dz;
++	_list  apsd;
++
++	u16 txseq_tid[16];
++
++	/* uint	sta_tx_bytes; */
++	/* u64	sta_tx_pkts; */
++	/* uint	sta_tx_fail; */
++
++
++};
++
++
++struct	hw_txqueue	{
++	volatile sint	head;
++	volatile sint	tail;
++	volatile sint 	free_sz;	/* in units of 64 bytes */
++	volatile sint      free_cmdsz;
++	volatile sint	 txsz[8];
++	uint	ff_hwaddr;
++	uint	cmd_hwaddr;
++	sint	ac_tag;
++};
++
++struct agg_pkt_info {
++	u16 offset;
++	u16 pkt_len;
++};
++
++enum cmdbuf_type {
++	CMDBUF_BEACON = 0x00,
++	CMDBUF_RSVD,
++	CMDBUF_MAX
++};
++
++u8 rtw_get_hwseq_no(_adapter *padapter);
++
++struct	xmit_priv	{
++
++	_lock	lock;
++
++	_sema	xmit_sema;
++
++	/* _queue	blk_strms[MAX_NUMBLKS]; */
++	_queue	be_pending;
++	_queue	bk_pending;
++	_queue	vi_pending;
++	_queue	vo_pending;
++	_queue	bm_pending;
++
++	/* _queue	legacy_dz_queue; */
++	/* _queue	apsd_queue; */
++
++	u8 *pallocated_frame_buf;
++	u8 *pxmit_frame_buf;
++	uint free_xmitframe_cnt;
++	_queue	free_xmit_queue;
++
++	/* uint mapping_addr; */
++	/* uint pkt_sz; */
++
++	u8 *xframe_ext_alloc_addr;
++	u8 *xframe_ext;
++	uint free_xframe_ext_cnt;
++	_queue free_xframe_ext_queue;
++
++	/* struct	hw_txqueue	be_txqueue; */
++	/* struct	hw_txqueue	bk_txqueue; */
++	/* struct	hw_txqueue	vi_txqueue; */
++	/* struct	hw_txqueue	vo_txqueue; */
++	/* struct	hw_txqueue	bmc_txqueue; */
++
++	uint	frag_len;
++
++	_adapter	*adapter;
++
++	u8   vcs_setting;
++	u8	vcs;
++	u8	vcs_type;
++	/* u16  rts_thresh; */
++
++	u64	tx_bytes;
++	u64	tx_pkts;
++	u64	tx_drop;
++	u64	last_tx_pkts;
++
++	struct hw_xmit *hwxmits;
++	u8	hwxmit_entry;
++
++	u8	wmm_para_seq[4];/* sequence for wmm ac parameter strength from large to small. it's value is 0->vo, 1->vi, 2->be, 3->bk. */
++
++#ifdef CONFIG_USB_HCI
++	_sema	tx_retevt;/* all tx return event; */
++	u8		txirp_cnt;
++
++	_tasklet xmit_tasklet;
++
++	/* per AC pending irp */
++	int beq_cnt;
++	int bkq_cnt;
++	int viq_cnt;
++	int voq_cnt;
++
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	/* Tx */
++	struct rtw_tx_ring	tx_ring[PCI_MAX_TX_QUEUE_COUNT];
++	int	txringcount[PCI_MAX_TX_QUEUE_COUNT];
++	u8 	beaconDMAing;		/* flag of indicating beacon is transmiting to HW by DMA */
++	_tasklet xmit_tasklet;
++#endif
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++#ifdef CONFIG_SDIO_TX_TASKLET
++	_tasklet xmit_tasklet;
++#else
++	_thread_hdl_	SdioXmitThread;
++	_sema		SdioXmitSema;
++	#ifdef SDIO_FREE_XMIT_BUF_SEMA
++	_sema		sdio_free_xmitbuf_sema;
++	#endif
++#endif /* CONFIG_SDIO_TX_TASKLET */
++#endif /* CONFIG_SDIO_HCI */
++
++	_queue free_xmitbuf_queue;
++	_queue pending_xmitbuf_queue;
++	u8 *pallocated_xmitbuf;
++	u8 *pxmitbuf;
++	uint free_xmitbuf_cnt;
++
++	_queue free_xmit_extbuf_queue;
++	u8 *pallocated_xmit_extbuf;
++	u8 *pxmit_extbuf;
++	uint free_xmit_extbuf_cnt;
++
++	struct xmit_buf	pcmd_xmitbuf[CMDBUF_MAX];
++	u8   hw_ssn_seq_no;/* mapping to REG_HW_SEQ 0,1,2,3 */
++	u16	nqos_ssn;
++#ifdef CONFIG_TX_EARLY_MODE
++
++#ifdef CONFIG_SDIO_HCI
++#define MAX_AGG_PKT_NUM 20
++#else
++#define MAX_AGG_PKT_NUM 256 /* Max tx ampdu coounts		 */
++#endif
++
++	struct agg_pkt_info agg_pkt[MAX_AGG_PKT_NUM];
++#endif
++
++#ifdef CONFIG_XMIT_ACK
++	int	ack_tx;
++	_mutex ack_tx_mutex;
++	struct submit_ctx ack_tx_ops;
++	u8 seq_no;
++#endif
++
++#ifdef CONFIG_TX_AMSDU
++	_timer amsdu_vo_timer;
++	u8 amsdu_vo_timeout;
++
++	_timer amsdu_vi_timer;
++	u8 amsdu_vi_timeout;
++
++	_timer amsdu_be_timer;
++	u8 amsdu_be_timeout;
++
++	_timer amsdu_bk_timer;
++	u8 amsdu_bk_timeout;
++
++	u32 amsdu_debug_set_timer;
++	u32 amsdu_debug_timeout;
++	u32 amsdu_debug_coalesce_one;
++	u32 amsdu_debug_coalesce_two;
++
++#endif
++#ifdef DBG_TXBD_DESC_DUMP
++	BOOLEAN	 dump_txbd_desc;
++#endif
++#ifdef CONFIG_PCI_TX_POLLING
++	_timer tx_poll_timer;
++#endif
++	_lock lock_sctx;
++
++};
++
++extern struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv,
++		enum cmdbuf_type buf_type);
++#define rtw_alloc_cmdxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_RSVD)
++#if defined(CONFIG_RTL8192E) && defined(CONFIG_PCI_HCI)
++extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8192ee(struct xmit_priv *pxmitpriv,
++		enum cmdbuf_type buf_type);
++#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8192ee(p, CMDBUF_BEACON)
++#elif defined(CONFIG_RTL8822B) && defined(CONFIG_PCI_HCI)
++extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8822be(struct xmit_priv *pxmitpriv,
++		enum cmdbuf_type buf_type);
++#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8822be(p, CMDBUF_BEACON)
++#elif defined(CONFIG_RTL8822C) && defined(CONFIG_PCI_HCI)
++extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8822ce(struct xmit_priv *pxmitpriv,
++		enum cmdbuf_type buf_type);
++#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8822ce(p, CMDBUF_BEACON)
++#elif defined(CONFIG_RTL8821C) && defined(CONFIG_PCI_HCI)
++extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8821ce(struct xmit_priv *pxmitpriv,
++		enum cmdbuf_type buf_type);
++#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8821ce(p, CMDBUF_BEACON)
++#elif defined(CONFIG_RTL8192F) && defined(CONFIG_PCI_HCI)
++extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8192fe(struct xmit_priv *pxmitpriv,
++		enum cmdbuf_type buf_type);
++#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8192fe(p, CMDBUF_BEACON)
++#elif defined(CONFIG_RTL8812A) && defined(CONFIG_PCI_HCI)
++extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8812ae(struct xmit_priv *pxmitpriv,
++		enum cmdbuf_type buf_type);
++#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8812ae(p, CMDBUF_BEACON)
++#elif defined(CONFIG_RTL8723D) && defined(CONFIG_PCI_HCI)
++extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8723de(struct xmit_priv *pxmitpriv,
++		enum cmdbuf_type buf_type);
++#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8723de(p, CMDBUF_BEACON)
++#elif defined(CONFIG_RTL8723B) && defined(CONFIG_PCI_HCI)
++extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8723be(struct xmit_priv *pxmitpriv,
++		enum cmdbuf_type buf_type);
++#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8723be(p, CMDBUF_BEACON)
++#elif defined(CONFIG_RTL8814A) && defined(CONFIG_PCI_HCI)
++extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8814ae(struct xmit_priv *pxmitpriv,
++		enum cmdbuf_type buf_type);
++#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8814ae(p, CMDBUF_BEACON)
++#elif defined(CONFIG_RTL8814B) && defined(CONFIG_PCI_HCI)
++extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8814be(struct xmit_priv *pxmitpriv,
++		enum cmdbuf_type buf_type);
++#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8814be(p, CMDBUF_BEACON)
++#else
++#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_BEACON)
++#endif
++
++extern struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv);
++extern s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++
++extern struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv);
++extern s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++
++void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz);
++extern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len);
++
++extern s32 rtw_make_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib);
++extern s32 rtw_put_snap(u8 *data, u16 h_proto);
++
++extern struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv, u16 os_qid);
++struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv);
++struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv);
++extern s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe);
++extern void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue);
++struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac);
++extern s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
++extern struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry);
++
++extern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe);
++extern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib);
++#define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue(&f->attrib)
++extern s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe);
++#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
++extern s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe);
++#endif
++#ifdef CONFIG_TDLS
++extern struct tdls_txmgmt *ptxmgmt;
++s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt);
++s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib);
++#endif
++s32 _rtw_init_hw_txqueue(struct hw_txqueue *phw_txqueue, u8 ac_tag);
++void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv);
++
++
++s32 rtw_txframes_pending(_adapter *padapter);
++s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib);
++void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry);
++
++
++s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter);
++void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv);
++
++
++void rtw_alloc_hwxmits(_adapter *padapter);
++void rtw_free_hwxmits(_adapter *padapter);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
++s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev);
++#endif
++void rtw_xmit_dequeue_callback(_workitem *work);
++void rtw_xmit_queue_set(struct sta_info *sta);
++void rtw_xmit_queue_clear(struct sta_info *sta);
++s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, _pkt *pkt);
++s32 rtw_xmit(_adapter *padapter, _pkt **pkt, u16 os_qid);
++bool xmitframe_hiq_filter(struct xmit_frame *xmitframe);
++#if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS)
++sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe);
++void stop_sta_xmit(_adapter *padapter, struct sta_info *psta);
++void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta);
++void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta);
++#endif
++
++u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta);
++
++void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj);
++u8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw);
++u8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw);
++s16 rtw_adapter_get_oper_txpwr_max_mbm(_adapter *adapter);
++s16 rtw_get_oper_txpwr_max_mbm(struct dvobj_priv *dvobj);
++
++u8 query_ra_short_GI(struct sta_info *psta, u8 bw);
++
++u8	qos_acm(u8 acm_mask, u8 priority);
++
++#ifdef CONFIG_XMIT_THREAD_MODE
++void	enqueue_pending_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++void enqueue_pending_xmitbuf_to_head(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
++struct xmit_buf	*dequeue_pending_xmitbuf(struct xmit_priv *pxmitpriv);
++struct xmit_buf	*select_and_dequeue_pending_xmitbuf(_adapter *padapter);
++sint	check_pending_xmitbuf(struct xmit_priv *pxmitpriv);
++thread_return	rtw_xmit_thread(thread_context context);
++#endif
++
++#ifdef CONFIG_TX_AMSDU
++extern void rtw_amsdu_vo_timeout_handler(void *FunctionContext);
++extern void rtw_amsdu_vi_timeout_handler(void *FunctionContext);
++extern void rtw_amsdu_be_timeout_handler(void *FunctionContext);
++extern void rtw_amsdu_bk_timeout_handler(void *FunctionContext);
++
++extern u8 rtw_amsdu_get_timer_status(_adapter *padapter, u8 priority);
++extern void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status);
++extern void rtw_amsdu_set_timer(_adapter *padapter, u8 priority);
++extern void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority);
++
++extern s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue);	
++extern s32 check_amsdu(struct xmit_frame *pxmitframe);
++extern s32 check_amsdu_tx_support(_adapter *padapter);
++extern struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame);
++#endif
++
++#ifdef DBG_TXBD_DESC_DUMP
++void rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 desc_size, u8 hwq);
++void rtw_tx_desc_backup_reset(void);
++u8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup **pbak);
++#endif
++
++#ifdef CONFIG_PCI_TX_POLLING
++void rtw_tx_poll_init(_adapter *padapter);
++void rtw_tx_poll_timeout_handler(void *FunctionContext);
++void rtw_tx_poll_timer_set(_adapter *padapter, u32 delay);
++void rtw_tx_poll_timer_cancel(_adapter *padapter);
++#endif
++
++u32	rtw_get_ff_hwaddr(struct xmit_frame	*pxmitframe);
++
++#ifdef CONFIG_XMIT_ACK
++int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms);
++void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status);
++#endif /* CONFIG_XMIT_ACK */
++
++enum XMIT_BLOCK_REASON {
++	XMIT_BLOCK_NONE = 0,
++	XMIT_BLOCK_REDLMEM = BIT0, /*LPS-PG*/
++	XMIT_BLOCK_SUSPEND = BIT1, /*WOW*/
++	XMIT_BLOCK_MAX = 0xFF,
++};
++void rtw_init_xmit_block(_adapter *padapter);
++void rtw_deinit_xmit_block(_adapter *padapter);
++
++#ifdef DBG_XMIT_BLOCK
++void dump_xmit_block(void *sel, _adapter *padapter);
++#endif
++void rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason);
++void rtw_clr_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason);
++bool rtw_is_xmit_blocked(_adapter *padapter);
++
++/* include after declaring struct xmit_buf, in order to avoid warning */
++#include <xmit_osdep.h>
++
++#endif /* _RTL871X_XMIT_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_hal.h
+new file mode 100644
+index 000000000..6e49835a4
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_hal.h
+@@ -0,0 +1,57 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __SDIO_HAL_H__
++#define __SDIO_HAL_H__
++
++void sd_int_dpc(PADAPTER padapter);
++u8 rtw_set_hal_ops(_adapter *padapter);
++
++#ifdef CONFIG_RTL8188E
++void rtl8188es_set_hal_ops(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_RTL8723B
++void rtl8723bs_set_hal_ops(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_RTL8821A
++void rtl8821as_set_hal_ops(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_RTL8192E
++void rtl8192es_set_hal_ops(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_RTL8703B
++void rtl8703bs_set_hal_ops(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_RTL8723D
++void rtl8723ds_set_hal_ops(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_RTL8188F
++void rtl8188fs_set_hal_ops(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_RTL8188GTV
++void rtl8188gtvs_set_hal_ops(PADAPTER padapter);
++#endif
++
++#ifdef CONFIG_RTL8192F
++void rtl8192fs_set_hal_ops(PADAPTER padapter);
++#endif
++
++#endif /* __SDIO_HAL_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_ops.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_ops.h
+new file mode 100644
+index 000000000..29f795dc3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_ops.h
+@@ -0,0 +1,206 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __SDIO_OPS_H__
++#define __SDIO_OPS_H__
++
++
++/* Follow mac team suggestion, default I/O fail return value is 0xFF */
++#define SDIO_ERR_VAL8	0xFF
++#define SDIO_ERR_VAL16	0xFFFF
++#define SDIO_ERR_VAL32	0xFFFFFFFF
++
++#ifdef PLATFORM_LINUX
++#include <sdio_ops_linux.h>
++#endif
++
++extern void sdio_set_intf_ops(_adapter *padapter, struct _io_ops *pops);
++void dump_sdio_card_info(void *sel, struct dvobj_priv *dvobj);
++
++u32 sdio_init(struct dvobj_priv *dvobj);
++void sdio_deinit(struct dvobj_priv *dvobj);
++int sdio_alloc_irq(struct dvobj_priv *dvobj);
++void sdio_free_irq(struct dvobj_priv *dvobj);
++u8 sdio_get_num_of_func(struct dvobj_priv *dvobj);
++
++#if 0
++extern void sdio_func1cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem);
++extern void sdio_func1cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem);
++#endif
++extern u8 SdioLocalCmd52Read1Byte(PADAPTER padapter, u32 addr);
++extern void SdioLocalCmd52Write1Byte(PADAPTER padapter, u32 addr, u8 v);
++extern s32 _sdio_local_read(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf);
++extern s32 sdio_local_read(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf);
++extern s32 _sdio_local_write(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf);
++extern s32 sdio_local_write(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf);
++
++u32 _sdio_read32(PADAPTER padapter, u32 addr);
++s32 _sdio_write32(PADAPTER padapter, u32 addr, u32 val);
++
++extern void sd_int_hdl(PADAPTER padapter);
++extern u8 CheckIPSStatus(PADAPTER padapter);
++
++#ifdef CONFIG_RTL8188E
++extern void InitInterrupt8188ESdio(PADAPTER padapter);
++extern void EnableInterrupt8188ESdio(PADAPTER padapter);
++extern void DisableInterrupt8188ESdio(PADAPTER padapter);
++extern void UpdateInterruptMask8188ESdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);
++extern u8 HalQueryTxBufferStatus8189ESdio(PADAPTER padapter);
++extern u8 HalQueryTxOQTBufferStatus8189ESdio(PADAPTER padapter);
++extern void ClearInterrupt8188ESdio(PADAPTER padapter);
++#endif /* CONFIG_RTL8188E */
++
++#ifdef CONFIG_RTL8821A
++extern void InitInterrupt8821AS(PADAPTER padapter);
++extern void EnableInterrupt8821AS(PADAPTER padapter);
++extern void DisableInterrupt8821AS(PADAPTER padapter);
++extern u8 HalQueryTxBufferStatus8821AS(PADAPTER padapter);
++extern u8 HalQueryTxOQTBufferStatus8821ASdio(PADAPTER padapter);
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++void ClearInterrupt8821AS(PADAPTER padapter);
++#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */
++#endif /* CONFIG_RTL8821A */
++
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++#if defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)
++u8 rtw_hal_enable_cpwm2(_adapter *adapter);
++#endif
++extern u8 RecvOnePkt(PADAPTER padapter);
++#endif /* CONFIG_WOWLAN */
++#ifdef CONFIG_RTL8723B
++extern void InitInterrupt8723BSdio(PADAPTER padapter);
++extern void InitSysInterrupt8723BSdio(PADAPTER padapter);
++extern void EnableInterrupt8723BSdio(PADAPTER padapter);
++extern void DisableInterrupt8723BSdio(PADAPTER padapter);
++extern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter);
++extern u8 HalQueryTxOQTBufferStatus8723BSdio(PADAPTER padapter);
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++extern void DisableInterruptButCpwm28723BSdio(PADAPTER padapter);
++extern void ClearInterrupt8723BSdio(PADAPTER padapter);
++#endif /* CONFIG_WOWLAN */
++#endif
++
++
++#ifdef CONFIG_RTL8192E
++extern void InitInterrupt8192ESdio(PADAPTER padapter);
++extern void EnableInterrupt8192ESdio(PADAPTER padapter);
++extern void DisableInterrupt8192ESdio(PADAPTER padapter);
++extern void UpdateInterruptMask8192ESdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);
++extern u8 HalQueryTxBufferStatus8192ESdio(PADAPTER padapter);
++extern u8 HalQueryTxOQTBufferStatus8192ESdio(PADAPTER padapter);
++extern void ClearInterrupt8192ESdio(PADAPTER padapter);
++#endif /* CONFIG_RTL8192E */
++
++#ifdef CONFIG_RTL8703B
++extern void InitInterrupt8703BSdio(PADAPTER padapter);
++extern void InitSysInterrupt8703BSdio(PADAPTER padapter);
++extern void EnableInterrupt8703BSdio(PADAPTER padapter);
++extern void DisableInterrupt8703BSdio(PADAPTER padapter);
++extern u8 HalQueryTxBufferStatus8703BSdio(PADAPTER padapter);
++extern u8 HalQueryTxOQTBufferStatus8703BSdio(PADAPTER padapter);
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++extern void DisableInterruptButCpwm28703BSdio(PADAPTER padapter);
++extern void ClearInterrupt8703BSdio(PADAPTER padapter);
++#endif /* CONFIG_WOWLAN */
++#endif
++
++#ifdef CONFIG_RTL8723D
++extern void InitInterrupt8723DSdio(PADAPTER padapter);
++extern void InitSysInterrupt8723DSdio(PADAPTER padapter);
++extern void EnableInterrupt8723DSdio(PADAPTER padapter);
++extern void DisableInterrupt8723DSdio(PADAPTER padapter);
++extern u8 HalQueryTxBufferStatus8723DSdio(PADAPTER padapter);
++extern u8 HalQueryTxOQTBufferStatus8723DSdio(PADAPTER padapter);
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++extern void DisableInterruptButCpwm28723dSdio(PADAPTER padapter);
++extern void ClearInterrupt8723DSdio(PADAPTER padapter);
++#endif /* CONFIG_WOWLAN */
++#endif
++
++#ifdef CONFIG_RTL8192F
++extern void InitInterrupt8192FSdio(PADAPTER padapter);
++extern void InitSysInterrupt8192FSdio(PADAPTER padapter);
++extern void EnableInterrupt8192FSdio(PADAPTER padapter);
++extern void DisableInterrupt8192FSdio(PADAPTER padapter);
++extern void UpdateInterruptMask8192FSdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);
++extern u8 HalQueryTxBufferStatus8192FSdio(PADAPTER padapter);
++extern u8 HalQueryTxOQTBufferStatus8192FSdio(PADAPTER padapter);
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++extern void DisableInterruptButCpwm2192fSdio(PADAPTER padapter);
++extern void ClearInterrupt8192FSdio(PADAPTER padapter);
++#endif /* CONFIG_WOWLAN */
++#endif
++
++#ifdef CONFIG_RTL8188F
++extern void InitInterrupt8188FSdio(PADAPTER padapter);
++extern void InitSysInterrupt8188FSdio(PADAPTER padapter);
++extern void EnableInterrupt8188FSdio(PADAPTER padapter);
++extern void DisableInterrupt8188FSdio(PADAPTER padapter);
++extern u8 HalQueryTxBufferStatus8188FSdio(PADAPTER padapter);
++extern u8 HalQueryTxOQTBufferStatus8188FSdio(PADAPTER padapter);
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++extern void DisableInterruptButCpwm28188FSdio(PADAPTER padapter);
++extern void ClearInterrupt8188FSdio(PADAPTER padapter);
++#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */
++#endif
++
++#ifdef CONFIG_RTL8188GTV
++extern void InitInterrupt8188GTVSdio(PADAPTER padapter);
++extern void InitSysInterrupt8188GTVSdio(PADAPTER padapter);
++extern void EnableInterrupt8188GTVSdio(PADAPTER padapter);
++extern void DisableInterrupt8188GTVSdio(PADAPTER padapter);
++extern u8 HalQueryTxBufferStatus8188GTVSdio(PADAPTER padapter);
++extern u8 HalQueryTxOQTBufferStatus8188GTVSdio(PADAPTER padapter);
++#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
++extern void DisableInterruptButCpwm28188GTVSdio(PADAPTER padapter);
++extern void ClearInterrupt8188GTVSdio(PADAPTER padapter);
++#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */
++#endif
++
++/**
++ * rtw_sdio_get_block_size() - Get block size of SDIO transfer
++ * @d		struct dvobj_priv*
++ *
++ * The unit of return value is byte.
++ */
++static inline u32 rtw_sdio_get_block_size(struct dvobj_priv *d)
++{
++	return d->intf_data.block_transfer_len;
++}
++
++/**
++ * rtw_sdio_cmd53_align_size() - Align size to one CMD53 could complete
++ * @d		struct dvobj_priv*
++ * @len		length to align
++ *
++ * Adjust len to align block size, and the new size could be transfered by one
++ * CMD53.
++ * If len < block size, it would keep original value, otherwise the value
++ * would be rounded up by block size.
++ *
++ * Return adjusted length.
++ */
++static inline size_t rtw_sdio_cmd53_align_size(struct dvobj_priv *d, size_t len)
++{
++	u32 blk_sz;
++
++
++	blk_sz = rtw_sdio_get_block_size(d);
++	if (len <= blk_sz)
++		return len;
++
++	return _RND(len, blk_sz);
++}
++
++#endif /* !__SDIO_OPS_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_ops_ce.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_ops_ce.h
+new file mode 100644
+index 000000000..d542cb7ea
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_ops_ce.h
+@@ -0,0 +1,49 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _SDIO_OPS_WINCE_H_
++#define _SDIO_OPS_WINCE_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <osdep_intf.h>
++
++
++#ifdef PLATFORM_OS_CE
++
++
++extern u8 sdbus_cmd52r_ce(struct intf_priv *pintfpriv, u32 addr);
++
++
++extern void sdbus_cmd52w_ce(struct intf_priv *pintfpriv, u32 addr, u8 val8);
++
++
++uint sdbus_read_blocks_to_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
++
++extern uint sdbus_read_bytes_to_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
++
++
++extern uint sdbus_write_blocks_from_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf, u8 async);
++
++extern uint sdbus_write_bytes_from_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
++extern u8 sdbus_func1cmd52r_ce(struct intf_priv *pintfpriv, u32 addr);
++extern void sdbus_func1cmd52w_ce(struct intf_priv *pintfpriv, u32 addr, u8 val8);
++extern uint sdbus_read_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata);
++extern uint sdbus_write_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata);
++extern void sdio_read_int(_adapter *padapter, u32 addr, u8 sz, void *pdata);
++
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_ops_linux.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_ops_linux.h
+new file mode 100644
+index 000000000..4bbd8fe7f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_ops_linux.h
+@@ -0,0 +1,58 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __SDIO_OPS_LINUX_H__
++#define __SDIO_OPS_LINUX_H__
++
++#ifndef RTW_HALMAC
++u8 sd_f0_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
++void sd_f0_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err);
++
++s32 _sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata);
++s32 _sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata);
++s32 sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata);
++s32 sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata);
++
++u8 _sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
++u8 sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
++u16 sd_read16(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
++u32 _sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
++u32 sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
++void sd_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err);
++void sd_write16(struct intf_hdl *pintfhdl, u32 addr, u16 v, s32 *err);
++void _sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err);
++void sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err);
++#endif /* RTW_HALMAC */
++
++bool rtw_is_sdio30(_adapter *adapter);
++
++/* The unit of return value is Hz */
++static inline u32 rtw_sdio_get_clock(struct dvobj_priv *d)
++{
++	return d->intf_data.clock;
++}
++
++s32 _sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata);
++s32 sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata);
++s32 _sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata);
++s32 sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata);
++
++void rtw_sdio_set_irq_thd(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl);
++int __must_check rtw_sdio_raw_read(struct dvobj_priv *d, unsigned int addr,
++				void *buf, size_t len, bool fixed);
++int __must_check rtw_sdio_raw_write(struct dvobj_priv *d, unsigned int addr,
++				void *buf, size_t len, bool fixed);
++
++#endif /* __SDIO_OPS_LINUX_H__ */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_ops_xp.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_ops_xp.h
+new file mode 100644
+index 000000000..d3d8764d3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_ops_xp.h
+@@ -0,0 +1,49 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _SDIO_OPS_XP_H_
++#define _SDIO_OPS_XP_H_
++
++#include <drv_conf.h>
++#include <osdep_service.h>
++#include <drv_types.h>
++#include <osdep_intf.h>
++
++
++#ifdef PLATFORM_OS_XP
++
++
++extern u8 sdbus_cmd52r_xp(struct intf_priv *pintfpriv, u32 addr);
++
++
++extern void sdbus_cmd52w_xp(struct intf_priv *pintfpriv, u32 addr, u8 val8);
++
++
++uint sdbus_read_blocks_to_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
++
++extern uint sdbus_read_bytes_to_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
++
++
++extern uint sdbus_write_blocks_from_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf, u8 async);
++
++extern uint sdbus_write_bytes_from_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
++extern u8 sdbus_func1cmd52r_xp(struct intf_priv *pintfpriv, u32 addr);
++extern void sdbus_func1cmd52w_xp(struct intf_priv *pintfpriv, u32 addr, u8 val8);
++extern uint sdbus_read_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata);
++extern uint sdbus_write_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata);
++extern void sdio_read_int(_adapter *padapter, u32 addr, u8 sz, void *pdata);
++
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_osintf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_osintf.h
+new file mode 100644
+index 000000000..a94e65679
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sdio_osintf.h
+@@ -0,0 +1,19 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __SDIO_OSINTF_H__
++#define __SDIO_OSINTF_H__
++
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sta_info.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sta_info.h
+new file mode 100644
+index 000000000..ac2869c52
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/sta_info.h
+@@ -0,0 +1,771 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __STA_INFO_H_
++#define __STA_INFO_H_
++
++#include <cmn_info/rtw_sta_info.h>
++
++#define IBSS_START_MAC_ID	2
++#define NUM_STA MACID_NUM_SW_LIMIT
++
++#ifndef CONFIG_RTW_MACADDR_ACL
++	#define CONFIG_RTW_MACADDR_ACL 1
++#endif
++
++#ifndef CONFIG_RTW_PRE_LINK_STA
++	#define CONFIG_RTW_PRE_LINK_STA 0
++#endif
++
++#define NUM_ACL 16
++
++#define RTW_ACL_PERIOD_DEV 0
++#define RTW_ACL_PERIOD_BSS 1
++#define RTW_ACL_PERIOD_NUM 2
++
++#define RTW_ACL_MODE_DISABLED				0
++#define RTW_ACL_MODE_ACCEPT_UNLESS_LISTED	1
++#define RTW_ACL_MODE_DENY_UNLESS_LISTED		2
++#define RTW_ACL_MODE_MAX					3
++
++#if CONFIG_RTW_MACADDR_ACL
++extern const char *const _acl_period_str[RTW_ACL_PERIOD_NUM];
++#define acl_period_str(mode) (((mode) >= RTW_ACL_PERIOD_NUM) ? "INVALID" : _acl_period_str[(mode)])
++extern const char *const _acl_mode_str[RTW_ACL_MODE_MAX];
++#define acl_mode_str(mode) (((mode) >= RTW_ACL_MODE_MAX) ? "INVALID" : _acl_mode_str[(mode)])
++#endif
++
++#ifndef RTW_PRE_LINK_STA_NUM
++	#define RTW_PRE_LINK_STA_NUM 8
++#endif
++
++struct pre_link_sta_node_t {
++	u8 valid;
++	u8 addr[ETH_ALEN];
++};
++
++struct pre_link_sta_ctl_t {
++	_lock lock;
++	u8 num;
++	struct pre_link_sta_node_t node[RTW_PRE_LINK_STA_NUM];
++};
++
++#ifdef CONFIG_TDLS
++#define MAX_ALLOWED_TDLS_STA_NUM	4
++#endif
++
++enum sta_info_update_type {
++	STA_INFO_UPDATE_NONE = 0,
++	STA_INFO_UPDATE_BW = BIT(0),
++	STA_INFO_UPDATE_RATE = BIT(1),
++	STA_INFO_UPDATE_PROTECTION_MODE = BIT(2),
++	STA_INFO_UPDATE_CAP = BIT(3),
++	STA_INFO_UPDATE_HT_CAP = BIT(4),
++	STA_INFO_UPDATE_VHT_CAP = BIT(5),
++	STA_INFO_UPDATE_ALL = STA_INFO_UPDATE_BW
++			      | STA_INFO_UPDATE_RATE
++			      | STA_INFO_UPDATE_PROTECTION_MODE
++			      | STA_INFO_UPDATE_CAP
++			      | STA_INFO_UPDATE_HT_CAP
++			      | STA_INFO_UPDATE_VHT_CAP,
++	STA_INFO_UPDATE_MAX
++};
++
++struct rtw_wlan_acl_node {
++	_list		        list;
++	u8       addr[ETH_ALEN];
++	u8       valid;
++};
++
++struct wlan_acl_pool {
++	int mode;
++	int num;
++	struct rtw_wlan_acl_node aclnode[NUM_ACL];
++	_queue	acl_node_q;
++};
++
++struct	stainfo_stats	{
++	systime last_rx_time;
++
++	u64 rx_mgnt_pkts;
++	u64 rx_beacon_pkts;
++	u64 rx_probereq_pkts;
++	u64 rx_probersp_pkts; /* unicast to self */
++	u64 rx_probersp_bm_pkts;
++	u64 rx_probersp_uo_pkts; /* unicast to others */
++	u64 rx_ctrl_pkts;
++	u64 rx_data_pkts;
++	u64 rx_data_bc_pkts;
++	u64 rx_data_mc_pkts;
++	u64 rx_data_qos_pkts[TID_NUM]; /* unicast only */
++
++	u64	last_rx_mgnt_pkts;
++	u64 last_rx_beacon_pkts;
++	u64 last_rx_probereq_pkts;
++	u64 last_rx_probersp_pkts; /* unicast to self */
++	u64 last_rx_probersp_bm_pkts;
++	u64 last_rx_probersp_uo_pkts; /* unicast to others */
++	u64	last_rx_ctrl_pkts;
++	u64	last_rx_data_pkts;
++	u64 last_rx_data_bc_pkts;
++	u64 last_rx_data_mc_pkts;
++	u64 last_rx_data_qos_pkts[TID_NUM]; /* unicast only */
++
++#ifdef CONFIG_TDLS
++	u64 rx_tdls_disc_rsp_pkts;
++	u64 last_rx_tdls_disc_rsp_pkts;
++#endif
++
++	u64	rx_bytes;
++	u64	rx_bc_bytes;
++	u64	rx_mc_bytes;
++	u64	last_rx_bytes;
++	u64 last_rx_bc_bytes;
++	u64 last_rx_mc_bytes;
++	u64	rx_drops; /* TBD */
++	u32 rx_tp_kbits;
++	u32 smooth_rx_tp_kbits;
++
++	u64	tx_pkts;
++	u64	last_tx_pkts;
++
++	u64	tx_bytes;
++	u64	last_tx_bytes;
++	u64 tx_drops; /* TBD */
++	u32 tx_tp_kbits;
++	u32 smooth_tx_tp_kbits;
++
++#ifdef CONFIG_LPS_CHK_BY_TP
++	u64 acc_tx_bytes;
++	u64 acc_rx_bytes;
++#endif
++
++	/* unicast only */
++	u64 last_rx_data_uc_pkts; /* For Read & Clear requirement in proc_get_rx_stat() */
++	u32 duplicate_cnt;	/* Read & Clear, in proc_get_rx_stat() */
++	u32 rxratecnt[128];	/* Read & Clear, in proc_get_rx_stat() */
++	u32 tx_ok_cnt;		/* Read & Clear, in proc_get_tx_stat() */
++	u32 tx_fail_cnt;	/* Read & Clear, in proc_get_tx_stat() */
++	u32 tx_retry_cnt;	/* Read & Clear, in proc_get_tx_stat() */
++#ifdef CONFIG_RTW_MESH
++	u32 rx_hwmp_pkts;
++	u32 last_rx_hwmp_pkts;
++#endif
++};
++
++#ifndef DBG_SESSION_TRACKER
++#define DBG_SESSION_TRACKER 0
++#endif
++
++/* session tracker status */
++#define ST_STATUS_NONE		0
++#define ST_STATUS_CHECK		BIT0
++#define ST_STATUS_ESTABLISH	BIT1
++#define ST_STATUS_EXPIRE	BIT2
++
++#define ST_EXPIRE_MS (10 * 1000)
++
++struct session_tracker {
++	_list list; /* session_tracker_queue */
++	u32 local_naddr;
++	u16 local_port;
++	u32 remote_naddr;
++	u16 remote_port;
++	systime set_time;
++	u8 status;
++};
++
++/* session tracker cmd */
++#define ST_CMD_ADD 0
++#define ST_CMD_DEL 1
++#define ST_CMD_CHK 2
++
++struct st_cmd_parm {
++	u8 cmd;
++	struct sta_info *sta;
++	u32 local_naddr; /* TODO: IPV6 */
++	u16 local_port;
++	u32 remote_naddr; /* TODO: IPV6 */
++	u16 remote_port;
++};
++
++typedef bool (*st_match_rule)(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);
++
++struct st_register {
++	u8 s_proto;
++	st_match_rule rule;
++};
++
++#define SESSION_TRACKER_REG_ID_WFD 0
++#define SESSION_TRACKER_REG_ID_NUM 1
++
++struct st_ctl_t {
++	struct st_register reg[SESSION_TRACKER_REG_ID_NUM];
++	_queue tracker_q;
++};
++
++void rtw_st_ctl_init(struct st_ctl_t *st_ctl);
++void rtw_st_ctl_deinit(struct st_ctl_t *st_ctl);
++void rtw_st_ctl_register(struct st_ctl_t *st_ctl, u8 st_reg_id, struct st_register *reg);
++void rtw_st_ctl_unregister(struct st_ctl_t *st_ctl, u8 st_reg_id);
++bool rtw_st_ctl_chk_reg_s_proto(struct st_ctl_t *st_ctl, u8 s_proto);
++bool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);
++void rtw_st_ctl_rx(struct sta_info *sta, u8 *ehdr_pos);
++void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl);
++
++#ifdef CONFIG_TDLS
++struct TDLS_PeerKey {
++	u8 kck[16]; /* TPK-KCK */
++	u8 tk[16]; /* TPK-TK; only CCMP will be used */
++} ;
++#endif /* CONFIG_TDLS */
++
++#ifdef DBG_RX_DFRAME_RAW_DATA
++struct sta_recv_dframe_info {
++
++	u8 sta_data_rate;
++	u8 sta_sgi;
++	u8 sta_bw_mode;
++	s8 sta_mimo_signal_strength[4];
++	s8 sta_RxPwr[4];
++	u8 sta_ofdm_snr[4];
++};
++#endif
++
++#ifdef CONFIG_RTW_MESH
++struct mesh_plink_ent;
++struct rtw_ewma_err_rate {
++	unsigned long internal;
++};
++
++/* Mesh airtime link metrics parameters */
++struct rtw_atlm_param {
++	struct rtw_ewma_err_rate err_rate; /* Now is PACKET error rate */
++	u16 data_rate; /* The unit is 100Kbps */
++	u16 total_pkt;
++	u16 overhead; /* Channel access overhead */
++};
++#endif
++
++struct sta_info {
++
++	_lock	lock;
++	_list	list; /* free_sta_queue */
++	_list	hash_list; /* sta_hash */
++	/* _list asoc_list; */ /* 20061114 */
++	/* _list sleep_list; */ /* sleep_q */
++	/* _list wakeup_list; */ /* wakeup_q */
++	_adapter *padapter;
++	struct cmn_sta_info cmn;
++
++	struct sta_xmit_priv sta_xmitpriv;
++	struct sta_recv_priv sta_recvpriv;
++
++#ifdef DBG_RX_DFRAME_RAW_DATA
++	struct sta_recv_dframe_info  sta_dframe_info;
++	struct sta_recv_dframe_info  sta_dframe_info_bmc;
++#endif
++	_queue sleep_q;
++	unsigned int sleepq_len;
++
++	uint state;
++	uint qos_option;
++	u16 hwseq;
++
++#ifdef CONFIG_RTW_80211K
++	u8 rm_en_cap[5];
++	u8 rm_diag_token;
++#endif /* CONFIG_RTW_80211K */
++
++	uint	ieee8021x_blocked;	/* 0: allowed, 1:blocked */
++	uint	dot118021XPrivacy; /* aes, tkip... */
++	union Keytype	dot11tkiptxmickey;
++	union Keytype	dot11tkiprxmickey;
++	union Keytype	dot118021x_UncstKey;
++	union pn48		dot11txpn;			/* PN48 used for Unicast xmit */
++	union pn48		dot11rxpn;			/* PN48 used for Unicast recv. */
++#ifdef CONFIG_RTW_MESH
++	/* peer's GTK, RX only */
++	u8 group_privacy;
++	u8 gtk_bmp;
++	union Keytype gtk;
++	union pn48 gtk_pn;
++	#ifdef CONFIG_IEEE80211W
++	/* peer's IGTK, RX only */
++	enum security_type dot11wCipher;
++	u8 igtk_bmp;
++	u8 igtk_id;
++	union Keytype igtk;
++	union pn48 igtk_pn;
++	#endif /* CONFIG_IEEE80211W */
++#endif /* CONFIG_RTW_MESH */
++#ifdef CONFIG_GTK_OL
++	u8 kek[RTW_KEK_LEN];
++	u8 kck[RTW_KCK_LEN];
++	u8 replay_ctr[RTW_REPLAY_CTR_LEN];
++#endif /* CONFIG_GTK_OL */
++#ifdef CONFIG_IEEE80211W
++	_timer dot11w_expire_timer;
++#endif /* CONFIG_IEEE80211W */
++
++	u8	bssrateset[16];
++	u32	bssratelen;
++
++	u8	cts2self;
++	u8	rtsen;
++
++	u8	init_rate;
++	u8	wireless_mode;	/* NETWORK_TYPE */
++
++	struct stainfo_stats sta_stats;
++
++#ifdef CONFIG_TDLS
++	u32	tdls_sta_state;
++	u8	SNonce[32];
++	u8	ANonce[32];
++	u32	TDLS_PeerKey_Lifetime;
++	u32	TPK_count;
++	_timer	TPK_timer;
++	struct TDLS_PeerKey	tpk;
++#ifdef CONFIG_TDLS_CH_SW
++	u16	ch_switch_time;
++	u16	ch_switch_timeout;
++	/* u8	option; */
++	_timer	ch_sw_timer;
++	_timer	delay_timer;
++	_timer	stay_on_base_chnl_timer;
++	_timer	ch_sw_monitor_timer;
++#endif
++	_timer handshake_timer;
++	u8 alive_count;
++	_timer	pti_timer;
++	u8	TDLS_RSNIE[20];	/* Save peer's RSNIE, used for sending TDLS_SETUP_RSP */
++#endif /* CONFIG_TDLS */
++
++	/* for A-MPDU TX, ADDBA timeout check	 */
++	_timer addba_retry_timer;
++
++	/* for A-MPDU Rx reordering buffer control */
++	struct recv_reorder_ctrl recvreorder_ctrl[TID_NUM];
++	ATOMIC_T continual_no_rx_packet[TID_NUM];
++	/* for A-MPDU Tx */
++	/* unsigned char		ampdu_txen_bitmap; */
++	u16	BA_starting_seqctrl[16];
++
++
++#ifdef CONFIG_80211N_HT
++	struct ht_priv	htpriv;
++#endif
++
++#ifdef CONFIG_80211AC_VHT
++	struct vht_priv	vhtpriv;
++#endif
++
++	/* Notes:	 */
++	/* STA_Mode: */
++	/* curr_network(mlme_priv/security_priv/qos/ht) + sta_info: (STA & AP) CAP/INFO	 */
++	/* scan_q: AP CAP/INFO */
++
++	/* AP_Mode: */
++	/* curr_network(mlme_priv/security_priv/qos/ht) : AP CAP/INFO */
++	/* sta_info: (AP & STA) CAP/INFO */
++
++	unsigned int expire_to;
++
++#ifdef CONFIG_AP_MODE
++
++	_list asoc_list;
++	_list auth_list;
++
++	unsigned int auth_seq;
++	unsigned int authalg;
++	unsigned char chg_txt[128];
++
++	u16 capability;
++	int flags;
++
++	int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */
++	int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */
++	int wpa_group_cipher;
++	int wpa2_group_cipher;
++	int wpa_pairwise_cipher;
++	int wpa2_pairwise_cipher;
++
++	u32 akm_suite_type;
++
++	u8 bpairwise_key_installed;
++#ifdef CONFIG_RTW_80211R
++	u8 ft_pairwise_key_installed;
++#endif
++
++#ifdef CONFIG_NATIVEAP_MLME
++	u8 wpa_ie[32];
++
++	u8 nonerp_set;
++	u8 no_short_slot_time_set;
++	u8 no_short_preamble_set;
++	u8 no_ht_gf_set;
++	u8 no_ht_set;
++	u8 ht_20mhz_set;
++	u8 ht_40mhz_intolerant;
++#endif /* CONFIG_NATIVEAP_MLME */
++
++#ifdef CONFIG_ATMEL_RC_PATCH
++	u8 flag_atmel_rc;
++#endif
++
++	u8 qos_info;
++
++	u8 max_sp_len;
++	u8 uapsd_bk;/* BIT(0): Delivery enabled, BIT(1): Trigger enabled */
++	u8 uapsd_be;
++	u8 uapsd_vi;
++	u8 uapsd_vo;
++
++	u8 has_legacy_ac;
++	unsigned int sleepq_ac_len;
++
++#ifdef CONFIG_P2P
++	/* p2p priv data */
++	u8 is_p2p_device;
++	u8 p2p_status_code;
++
++	/* p2p client info */
++	u8 dev_addr[ETH_ALEN];
++	/* u8 iface_addr[ETH_ALEN]; */ /* = hwaddr[ETH_ALEN] */
++	u8 dev_cap;
++	u16 config_methods;
++	u8 primary_dev_type[8];
++	u8 num_of_secdev_type;
++	u8 secdev_types_list[32];/* 32/8 == 4; */
++	u16 dev_name_len;
++	u8 dev_name[32];
++#endif /* CONFIG_P2P */
++
++#ifdef CONFIG_WFD
++	u8 op_wfd_mode;
++#endif
++
++#if !defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && defined(CONFIG_80211N_HT)
++	u8 under_exist_checking;
++#endif
++
++	u8 keep_alive_trycnt;
++
++#ifdef CONFIG_AUTO_AP_MODE
++	u8 isrc; /* this device is rc */
++	u16 pid; /* pairing id */
++#endif
++
++#endif /* CONFIG_AP_MODE	 */
++
++#ifdef CONFIG_RTW_MESH
++	struct mesh_plink_ent *plink;
++
++	u8 local_mps;
++	u8 peer_mps;
++	u8 nonpeer_mps;
++
++	struct rtw_atlm_param metrics;
++	/* The reference for nexthop_lookup */
++	BOOLEAN alive;
++#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++	u8 *pauth_frame;
++	u32 auth_len;
++	u8 *passoc_req;
++	u32 assoc_req_len;
++#endif
++
++	u8		IOTPeer;			/* Enum value.	HT_IOT_PEER_E */
++#ifdef CONFIG_LPS_PG
++	u8		lps_pg_rssi_lv;
++#endif
++
++	/* To store the sequence number of received management frame */
++	u16 RxMgmtFrameSeqNum;
++
++	struct st_ctl_t st_ctl;
++	u8 max_agg_num_minimal_record; /*keep minimal tx desc max_agg_num setting*/
++	u8 curr_rx_rate;
++	u8 curr_rx_rate_bmc;
++#ifdef CONFIG_RTS_FULL_BW
++	bool vendor_8812;
++#endif
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	u8 tbtx_enable;			/* Does this sta_info support & enable TBTX function? */
++//	u8 tbtx_timeslot;		/* This sta_info belong to which time slot.	*/
++#endif
++
++	/*
++	 * Vaiables for queuing TX pkt a short period of time
++	 * to wait something ready.
++	 */
++	u8 tx_q_enable;
++	struct __queue tx_queue;
++	_workitem tx_q_work;
++};
++
++#ifdef CONFIG_RTW_MESH
++#define STA_SET_MESH_PLINK(sta, link) (sta)->plink = link
++#else
++#define STA_SET_MESH_PLINK(sta, link) do {} while (0)
++#endif
++
++#define sta_tx_pkts(sta) \
++	(sta->sta_stats.tx_pkts)
++
++#define sta_last_tx_pkts(sta) \
++	(sta->sta_stats.last_tx_pkts)
++
++#define sta_rx_pkts(sta) \
++	(sta->sta_stats.rx_mgnt_pkts \
++	 + sta->sta_stats.rx_ctrl_pkts \
++	 + sta->sta_stats.rx_data_pkts)
++
++#define sta_last_rx_pkts(sta) \
++	(sta->sta_stats.last_rx_mgnt_pkts \
++	 + sta->sta_stats.last_rx_ctrl_pkts \
++	 + sta->sta_stats.last_rx_data_pkts)
++
++#define sta_rx_data_pkts(sta) (sta->sta_stats.rx_data_pkts)
++#define sta_last_rx_data_pkts(sta) (sta->sta_stats.last_rx_data_pkts)
++
++#define sta_rx_data_uc_pkts(sta) (sta->sta_stats.rx_data_pkts - sta->sta_stats.rx_data_bc_pkts - sta->sta_stats.rx_data_mc_pkts)
++#define sta_last_rx_data_uc_pkts(sta) (sta->sta_stats.last_rx_data_pkts - sta->sta_stats.last_rx_data_bc_pkts - sta->sta_stats.last_rx_data_mc_pkts)
++
++#define sta_rx_data_qos_pkts(sta, i) \
++	(sta->sta_stats.rx_data_qos_pkts[i])
++
++#define sta_last_rx_data_qos_pkts(sta, i) \
++	(sta->sta_stats.last_rx_data_qos_pkts[i])
++
++#define sta_rx_mgnt_pkts(sta) \
++	(sta->sta_stats.rx_mgnt_pkts)
++
++#define sta_last_rx_mgnt_pkts(sta) \
++	(sta->sta_stats.last_rx_mgnt_pkts)
++
++#define sta_rx_beacon_pkts(sta) \
++	(sta->sta_stats.rx_beacon_pkts)
++
++#define sta_last_rx_beacon_pkts(sta) \
++	(sta->sta_stats.last_rx_beacon_pkts)
++
++#define sta_rx_probereq_pkts(sta) \
++	(sta->sta_stats.rx_probereq_pkts)
++
++#define sta_last_rx_probereq_pkts(sta) \
++	(sta->sta_stats.last_rx_probereq_pkts)
++
++#define sta_rx_probersp_pkts(sta) \
++	(sta->sta_stats.rx_probersp_pkts)
++
++#define sta_last_rx_probersp_pkts(sta) \
++	(sta->sta_stats.last_rx_probersp_pkts)
++
++#define sta_rx_probersp_bm_pkts(sta) \
++	(sta->sta_stats.rx_probersp_bm_pkts)
++
++#define sta_last_rx_probersp_bm_pkts(sta) \
++	(sta->sta_stats.last_rx_probersp_bm_pkts)
++
++#define sta_rx_probersp_uo_pkts(sta) \
++	(sta->sta_stats.rx_probersp_uo_pkts)
++
++#define sta_last_rx_probersp_uo_pkts(sta) \
++	(sta->sta_stats.last_rx_probersp_uo_pkts)
++
++#ifdef CONFIG_RTW_MESH
++#define update_last_rx_hwmp_pkts(sta) \
++	do { \
++		sta->sta_stats.last_rx_hwmp_pkts = sta->sta_stats.rx_hwmp_pkts; \
++	} while(0)
++#else
++#define update_last_rx_hwmp_pkts(sta) do {} while(0)
++#endif
++
++#define sta_update_last_rx_pkts(sta) \
++	do { \
++		int __i; \
++		\
++		sta->sta_stats.last_rx_mgnt_pkts = sta->sta_stats.rx_mgnt_pkts; \
++		sta->sta_stats.last_rx_beacon_pkts = sta->sta_stats.rx_beacon_pkts; \
++		sta->sta_stats.last_rx_probereq_pkts = sta->sta_stats.rx_probereq_pkts; \
++		sta->sta_stats.last_rx_probersp_pkts = sta->sta_stats.rx_probersp_pkts; \
++		sta->sta_stats.last_rx_probersp_bm_pkts = sta->sta_stats.rx_probersp_bm_pkts; \
++		sta->sta_stats.last_rx_probersp_uo_pkts = sta->sta_stats.rx_probersp_uo_pkts; \
++		sta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \
++		update_last_rx_hwmp_pkts(sta); \
++		\
++		sta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \
++		sta->sta_stats.last_rx_data_bc_pkts = sta->sta_stats.rx_data_bc_pkts; \
++		sta->sta_stats.last_rx_data_mc_pkts = sta->sta_stats.rx_data_mc_pkts; \
++		for (__i = 0; __i < TID_NUM; __i++) \
++			sta->sta_stats.last_rx_data_qos_pkts[__i] = sta->sta_stats.rx_data_qos_pkts[__i]; \
++	} while (0)
++
++#define STA_RX_PKTS_ARG(sta) \
++	sta->sta_stats.rx_mgnt_pkts \
++	, sta->sta_stats.rx_ctrl_pkts \
++	, sta->sta_stats.rx_data_pkts
++
++#define STA_LAST_RX_PKTS_ARG(sta) \
++	sta->sta_stats.last_rx_mgnt_pkts \
++	, sta->sta_stats.last_rx_ctrl_pkts \
++	, sta->sta_stats.last_rx_data_pkts
++
++#define STA_RX_PKTS_DIFF_ARG(sta) \
++	sta->sta_stats.rx_mgnt_pkts - sta->sta_stats.last_rx_mgnt_pkts \
++	, sta->sta_stats.rx_ctrl_pkts - sta->sta_stats.last_rx_ctrl_pkts \
++	, sta->sta_stats.rx_data_pkts - sta->sta_stats.last_rx_data_pkts
++
++#define STA_PKTS_FMT "(m:%llu, c:%llu, d:%llu)"
++
++#define sta_rx_uc_bytes(sta) (sta->sta_stats.rx_bytes - sta->sta_stats.rx_bc_bytes - sta->sta_stats.rx_mc_bytes)
++#define sta_last_rx_uc_bytes(sta) (sta->sta_stats.last_rx_bytes - sta->sta_stats.last_rx_bc_bytes - sta->sta_stats.last_rx_mc_bytes)
++
++#ifdef CONFIG_WFD
++#define STA_OP_WFD_MODE(sta) (sta)->op_wfd_mode
++#define STA_SET_OP_WFD_MODE(sta, mode) (sta)->op_wfd_mode = (mode)
++#else
++#define STA_OP_WFD_MODE(sta) 0
++#define STA_SET_OP_WFD_MODE(sta, mode) do {} while (0)
++#endif
++
++#define AID_BMP_LEN(max_aid) ((max_aid + 1) / 8 + (((max_aid + 1) % 8) ? 1 : 0))
++
++struct	sta_priv {
++
++	u8 *pallocated_stainfo_buf;
++	u8 *pstainfo_buf;
++	_queue	free_sta_queue;
++
++	_lock sta_hash_lock;
++	_list   sta_hash[NUM_STA];
++	int asoc_sta_count;
++	_queue sleep_q;
++	_queue wakeup_q;
++
++	_adapter *padapter;
++
++	u32 adhoc_expire_to;
++
++	int rx_chk_limit;
++
++#ifdef CONFIG_AP_MODE
++	_list asoc_list;
++	_list auth_list;
++	_lock asoc_list_lock;
++	_lock auth_list_lock;
++	u8 asoc_list_cnt;
++	u8 auth_list_cnt;
++
++	unsigned int auth_to;  /* sec, time to expire in authenticating. */
++	unsigned int assoc_to; /* sec, time to expire before associating. */
++	unsigned int expire_to; /* sec , time to expire after associated. */
++
++	/*
++	* pointers to STA info; based on allocated AID or NULL if AID free
++	* AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1
++	*/
++	struct sta_info **sta_aid;
++	u16 max_aid;
++	u16 started_aid; /* started AID for allocation search */
++	bool rr_aid; /* round robin AID allocation, will modify started_aid */
++	u8 aid_bmp_len; /* in byte */
++	u8 *sta_dz_bitmap;
++	u8 *tim_bitmap;
++
++	u16 max_num_sta;
++
++#if CONFIG_RTW_MACADDR_ACL
++	struct wlan_acl_pool acl_list[RTW_ACL_PERIOD_NUM];
++#endif
++
++	#if CONFIG_RTW_PRE_LINK_STA
++	struct pre_link_sta_ctl_t pre_link_sta_ctl;
++	#endif
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	u8 tbtx_asoc_list_cnt;
++	struct sta_info *token_holder[NR_MAXSTA_INSLOT];
++	struct sta_info *last_token_holder;
++	ATOMIC_T nr_token_keeper;
++#endif
++#endif /* CONFIG_AP_MODE */
++
++#ifdef CONFIG_ATMEL_RC_PATCH
++	u8 atmel_rc_pattern[6];
++#endif
++	u8 c2h_sta_mac[ETH_ALEN];
++	u8 c2h_adapter_id;
++	struct submit_ctx *gotc2h;
++};
++
++
++__inline static u32 wifi_mac_hash(const u8 *mac)
++{
++	u32 x;
++
++	x = mac[0];
++	x = (x << 2) ^ mac[1];
++	x = (x << 2) ^ mac[2];
++	x = (x << 2) ^ mac[3];
++	x = (x << 2) ^ mac[4];
++	x = (x << 2) ^ mac[5];
++
++	x ^= x >> 8;
++	x  = x & (NUM_STA - 1);
++
++	return x;
++}
++
++
++extern u32	_rtw_init_sta_priv(struct sta_priv *pstapriv);
++extern u32	_rtw_free_sta_priv(struct sta_priv *pstapriv);
++
++#define stainfo_offset_valid(offset) (offset < NUM_STA && offset >= 0)
++int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta);
++struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset);
++
++extern struct sta_info *rtw_alloc_stainfo(struct	sta_priv *pstapriv, const u8 *hwaddr);
++extern u32	rtw_free_stainfo(_adapter *padapter , struct sta_info *psta);
++extern void rtw_free_all_stainfo(_adapter *padapter);
++extern struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr);
++extern u32 rtw_init_bcmc_stainfo(_adapter *padapter);
++extern struct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter);
++
++#ifdef CONFIG_AP_MODE
++u16 rtw_aid_alloc(_adapter *adapter, struct sta_info *sta);
++void dump_aid_status(void *sel, _adapter *adapter);
++#endif
++
++#if CONFIG_RTW_MACADDR_ACL
++extern u8 rtw_access_ctrl(_adapter *adapter, const u8 *mac_addr);
++void dump_macaddr_acl(void *sel, _adapter *adapter);
++#endif
++
++bool rtw_is_pre_link_sta(struct sta_priv *stapriv, u8 *addr);
++#if CONFIG_RTW_PRE_LINK_STA
++struct sta_info *rtw_pre_link_sta_add(struct sta_priv *stapriv, u8 *hwaddr);
++void rtw_pre_link_sta_del(struct sta_priv *stapriv, u8 *hwaddr);
++void rtw_pre_link_sta_ctl_reset(struct sta_priv *stapriv);
++void rtw_pre_link_sta_ctl_init(struct sta_priv *stapriv);
++void rtw_pre_link_sta_ctl_deinit(struct sta_priv *stapriv);
++void dump_pre_link_sta_ctl(void *sel, struct sta_priv *stapriv);
++#endif /* CONFIG_RTW_PRE_LINK_STA */
++
++#endif /* _STA_INFO_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/usb_hal.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/usb_hal.h
+new file mode 100644
+index 000000000..2d7776f06
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/usb_hal.h
+@@ -0,0 +1,71 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __USB_HAL_H__
++#define __USB_HAL_H__
++
++int usb_init_recv_priv(_adapter *padapter, u16 ini_in_buf_sz);
++void usb_free_recv_priv(_adapter *padapter, u16 ini_in_buf_sz);
++#ifdef CONFIG_FW_C2H_REG
++void usb_c2h_hisr_hdl(_adapter *adapter, u8 *buf);
++#endif
++
++u8 rtw_set_hal_ops(_adapter *padapter);
++
++#ifdef CONFIG_RTL8188E
++void rtl8188eu_set_hal_ops(_adapter *padapter);
++#endif
++
++#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
++void rtl8812au_set_hal_ops(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_RTL8192E
++void rtl8192eu_set_hal_ops(_adapter *padapter);
++#endif
++
++
++#ifdef CONFIG_RTL8723B
++void rtl8723bu_set_hal_ops(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_RTL8814A
++void rtl8814au_set_hal_ops(_adapter *padapter);
++#endif /* CONFIG_RTL8814A */
++
++#ifdef CONFIG_RTL8188F
++void rtl8188fu_set_hal_ops(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_RTL8188GTV
++void rtl8188gtvu_set_hal_ops(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_RTL8703B
++void rtl8703bu_set_hal_ops(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_RTL8723D
++void rtl8723du_set_hal_ops(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_RTL8710B
++void rtl8710bu_set_hal_ops(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_RTL8192F
++void rtl8192fu_set_hal_ops(_adapter *padapter);
++#endif /* CONFIG_RTL8192F */
++
++#endif /* __USB_HAL_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/usb_ops.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/usb_ops.h
+new file mode 100644
+index 000000000..6d5435d65
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/usb_ops.h
+@@ -0,0 +1,153 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __USB_OPS_H_
++#define __USB_OPS_H_
++
++
++#define REALTEK_USB_VENQT_READ		0xC0
++#define REALTEK_USB_VENQT_WRITE	0x40
++#define REALTEK_USB_VENQT_CMD_REQ	0x05
++#define REALTEK_USB_VENQT_CMD_IDX	0x00
++#define REALTEK_USB_IN_INT_EP_IDX	1
++
++enum {
++	VENDOR_WRITE = 0x00,
++	VENDOR_READ = 0x01,
++};
++#define ALIGNMENT_UNIT				16
++#define MAX_VENDOR_REQ_CMD_SIZE	254		/* 8188cu SIE Support */
++#define MAX_USB_IO_CTL_SIZE		(MAX_VENDOR_REQ_CMD_SIZE + ALIGNMENT_UNIT)
++
++#ifdef PLATFORM_LINUX
++#include <usb_ops_linux.h>
++#endif /* PLATFORM_LINUX */
++
++#ifdef CONFIG_RTL8188E
++void rtl8188eu_set_hw_type(struct dvobj_priv *pdvobj);
++#ifdef CONFIG_SUPPORT_USB_INT
++void interrupt_handler_8188eu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
++#endif
++#endif
++
++#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
++void rtl8812au_set_hw_type(struct dvobj_priv *pdvobj);
++#ifdef CONFIG_SUPPORT_USB_INT
++void interrupt_handler_8812au(_adapter *padapter, u16 pkt_len, u8 *pbuf);
++#endif
++#endif
++
++#ifdef CONFIG_RTL8814A
++void rtl8814au_set_hw_type(struct dvobj_priv *pdvobj);
++#ifdef CONFIG_SUPPORT_USB_INT
++void interrupt_handler_8814au(_adapter *padapter, u16 pkt_len, u8 *pbuf);
++#endif
++#endif /* CONFIG_RTL8814 */
++
++#ifdef CONFIG_RTL8192E
++void rtl8192eu_set_hw_type(struct dvobj_priv *pdvobj);
++#ifdef CONFIG_SUPPORT_USB_INT
++void interrupt_handler_8192eu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
++#endif
++
++#endif
++
++#ifdef CONFIG_RTL8188F
++void rtl8188fu_set_hw_type(struct dvobj_priv *pdvobj);
++#ifdef CONFIG_SUPPORT_USB_INT
++void interrupt_handler_8188fu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
++#endif
++#endif
++
++#ifdef CONFIG_RTL8188GTV
++void rtl8188gtvu_set_hw_type(struct dvobj_priv *pdvobj);
++#ifdef CONFIG_SUPPORT_USB_INT
++void interrupt_handler_8188gtvu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
++#endif
++#endif
++
++#ifdef CONFIG_RTL8723B
++void rtl8723bu_set_hw_type(struct dvobj_priv *pdvobj);
++#ifdef CONFIG_SUPPORT_USB_INT
++void interrupt_handler_8723bu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
++#endif
++#endif
++
++#ifdef CONFIG_RTL8703B
++void rtl8703bu_set_hw_type(struct dvobj_priv *pdvobj);
++#ifdef CONFIG_SUPPORT_USB_INT
++void interrupt_handler_8703bu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
++#endif /* CONFIG_SUPPORT_USB_INT */
++#endif /* CONFIG_RTL8703B */
++
++void usb_set_intf_ops(_adapter *padapter, struct _io_ops *pops);
++
++#ifdef CONFIG_RTL8723D
++void rtl8723du_set_hw_type(struct dvobj_priv *pdvobj);
++void rtl8723du_set_intf_ops(struct _io_ops *pops);
++void rtl8723du_recv_tasklet(void *priv);
++void rtl8723du_xmit_tasklet(void *priv);
++#ifdef CONFIG_SUPPORT_USB_INT
++void interrupt_handler_8723du(_adapter *padapter, u16 pkt_len, u8 *pbuf);
++#endif /* CONFIG_SUPPORT_USB_INT */
++#endif /* CONFIG_RTL8723D */
++
++#ifdef CONFIG_RTL8710B
++void rtl8710bu_set_hw_type(struct dvobj_priv *pdvobj);
++void rtl8710bu_set_intf_ops(struct _io_ops *pops);
++void rtl8710bu_recv_tasklet(void *priv);
++void rtl8710bu_xmit_tasklet(void *priv);
++#ifdef CONFIG_SUPPORT_USB_INT
++void interrupt_handler_8710bu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
++#endif /* CONFIG_SUPPORT_USB_INT */
++#endif /* CONFIG_RTL8710B */
++
++#ifdef CONFIG_RTL8192F
++void rtl8192fu_set_hw_type(struct dvobj_priv *pdvobj);
++void rtl8192fu_xmit_tasklet(void *priv);
++#ifdef CONFIG_SUPPORT_USB_INT
++void rtl8192fu_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf);
++#endif /* CONFIG_SUPPORT_USB_INT */
++#endif /* CONFIG_RTL8192F */
++
++enum RTW_USB_SPEED {
++	RTW_USB_SPEED_UNKNOWN	= 0,
++	RTW_USB_SPEED_1_1	= 1,
++	RTW_USB_SPEED_2		= 2,
++	RTW_USB_SPEED_3		= 3,
++};
++
++#define IS_FULL_SPEED_USB(Adapter)	(adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_1_1)
++#define IS_HIGH_SPEED_USB(Adapter)	(adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_2)
++#define IS_SUPER_SPEED_USB(Adapter)	(adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_3)
++
++#define USB_SUPER_SPEED_BULK_SIZE	1024	/* usb 3.0 */
++#define USB_HIGH_SPEED_BULK_SIZE	512		/* usb 2.0 */
++#define USB_FULL_SPEED_BULK_SIZE	64		/* usb 1.1 */
++
++static inline u8 rtw_usb_bulk_size_boundary(_adapter *padapter, int buf_len)
++{
++	u8 rst = _TRUE;
++
++	if (IS_SUPER_SPEED_USB(padapter))
++		rst = (0 == (buf_len) % USB_SUPER_SPEED_BULK_SIZE) ? _TRUE : _FALSE;
++	else if (IS_HIGH_SPEED_USB(padapter))
++		rst = (0 == (buf_len) % USB_HIGH_SPEED_BULK_SIZE) ? _TRUE : _FALSE;
++	else
++		rst = (0 == (buf_len) % USB_FULL_SPEED_BULK_SIZE) ? _TRUE : _FALSE;
++	return rst;
++}
++
++
++#endif /* __USB_OPS_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/usb_ops_linux.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/usb_ops_linux.h
+new file mode 100644
+index 000000000..bf59ca0fa
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/usb_ops_linux.h
+@@ -0,0 +1,98 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __USB_OPS_LINUX_H__
++#define __USB_OPS_LINUX_H__
++
++#define VENDOR_CMD_MAX_DATA_LEN	254
++#define FW_START_ADDRESS	0x1000
++
++#define RTW_USB_CONTROL_MSG_TIMEOUT_TEST	10/* ms */
++#define RTW_USB_CONTROL_MSG_TIMEOUT	500/* ms */
++
++#define RECV_BULK_IN_ADDR		0x80/* assign by drv, not real address */
++#define RECV_INT_IN_ADDR		0x81/* assign by drv, not real address */
++
++#define INTERRUPT_MSG_FORMAT_LEN 60
++
++#if defined(CONFIG_VENDOR_REQ_RETRY) && defined(CONFIG_USB_VENDOR_REQ_MUTEX)
++	/* vendor req retry should be in the situation when each vendor req is atomically submitted from others */
++	#define MAX_USBCTRL_VENDORREQ_TIMES	10
++#else
++	#define MAX_USBCTRL_VENDORREQ_TIMES	1
++#endif
++
++#define RTW_USB_BULKOUT_TIMEOUT	5000/* ms */
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18))
++#define _usbctrl_vendorreq_async_callback(urb, regs)	_usbctrl_vendorreq_async_callback(urb)
++#define usb_bulkout_zero_complete(purb, regs)	usb_bulkout_zero_complete(purb)
++#define usb_write_mem_complete(purb, regs)	usb_write_mem_complete(purb)
++#define usb_write_port_complete(purb, regs)	usb_write_port_complete(purb)
++#define usb_read_port_complete(purb, regs)	usb_read_port_complete(purb)
++#define usb_read_interrupt_complete(purb, regs)	usb_read_interrupt_complete(purb)
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 12))
++#define rtw_usb_control_msg(dev, pipe, request, requesttype, value, index, data, size, timeout_ms) \
++	usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), (data), (size), (timeout_ms))
++#define rtw_usb_bulk_msg(usb_dev, pipe, data, len, actual_length, timeout_ms) \
++	usb_bulk_msg((usb_dev), (pipe), (data), (len), (actual_length), (timeout_ms))
++#else
++#define rtw_usb_control_msg(dev, pipe, request, requesttype, value, index, data, size, timeout_ms) \
++	usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), (data), (size), \
++		((timeout_ms) == 0) || ((timeout_ms) * HZ / 1000 > 0) ? ((timeout_ms) * HZ / 1000) : 1)
++#define rtw_usb_bulk_msg(usb_dev, pipe, data, len, actual_length, timeout_ms) \
++	usb_bulk_msg((usb_dev), (pipe), (data), (len), (actual_length), \
++		((timeout_ms) == 0) || ((timeout_ms) * HZ / 1000 > 0) ? ((timeout_ms) * HZ / 1000) : 1)
++#endif
++
++
++#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
++int usb_async_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val);
++int usb_async_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val);
++int usb_async_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val);
++#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */
++
++unsigned int ffaddr2pipehdl(struct dvobj_priv *pdvobj, u32 addr);
++
++void usb_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem);
++void usb_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem);
++
++void usb_read_port_cancel(struct intf_hdl *pintfhdl);
++
++u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem);
++void usb_write_port_cancel(struct intf_hdl *pintfhdl);
++
++int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype);
++#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
++int _usbctrl_vendorreq_async_write(struct usb_device *udev, u8 request,
++		u16 value, u16 index, void *pdata, u16 len, u8 requesttype);
++#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */
++
++u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr);
++u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr);
++u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr);
++int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val);
++int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val);
++int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val);
++int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);
++u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem);
++void usb_recv_tasklet(void *priv);
++
++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
++void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs);
++u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr);
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/usb_osintf.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/usb_osintf.h
+new file mode 100644
+index 000000000..48495b492
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/usb_osintf.h
+@@ -0,0 +1,26 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __USB_OSINTF_H
++#define __USB_OSINTF_H
++
++#include <usb_vendor_req.h>
++
++#define USBD_HALTED(Status) ((u32)(Status) >> 30 == 3)
++
++
++u8 usbvendorrequest(struct dvobj_priv *pdvobjpriv, RT_USB_BREQUEST brequest, RT_USB_WVALUE wvalue, u8 windex, void *data, u8 datalen, u8 isdirectionin);
++
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/usb_vendor_req.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/usb_vendor_req.h
+new file mode 100644
+index 000000000..3e2587863
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/usb_vendor_req.h
+@@ -0,0 +1,56 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _USB_VENDOR_REQUEST_H_
++#define _USB_VENDOR_REQUEST_H_
++
++/* 4	Set/Get Register related wIndex/Data */
++#define	RT_USB_RESET_MASK_OFF		0
++#define	RT_USB_RESET_MASK_ON		1
++#define	RT_USB_SLEEP_MASK_OFF		0
++#define	RT_USB_SLEEP_MASK_ON		1
++#define	RT_USB_LDO_ON				1
++#define	RT_USB_LDO_OFF				0
++
++/* 4	Set/Get SYSCLK related	wValue or Data */
++#define	RT_USB_SYSCLK_32KHZ		0
++#define	RT_USB_SYSCLK_40MHZ		1
++#define	RT_USB_SYSCLK_60MHZ		2
++
++
++typedef enum _RT_USB_BREQUEST {
++	RT_USB_SET_REGISTER		= 1,
++	RT_USB_SET_SYSCLK		= 2,
++	RT_USB_GET_SYSCLK		= 3,
++	RT_USB_GET_REGISTER		= 4
++} RT_USB_BREQUEST;
++
++
++typedef enum _RT_USB_WVALUE {
++	RT_USB_RESET_MASK	=	1,
++	RT_USB_SLEEP_MASK	=	2,
++	RT_USB_USB_HRCPWM	=	3,
++	RT_USB_LDO			=	4,
++	RT_USB_BOOT_TYPE	=	5
++} RT_USB_WVALUE;
++
++
++#if 0
++BOOLEAN usbvendorrequest(PCE_USB_DEVICE	CEdevice, RT_USB_BREQUEST bRequest, RT_USB_WVALUE wValue, u8 wIndex, void *Data, u8 DataLength, BOOLEAN isDirectionIn);
++BOOLEAN CEusbGetStatusRequest(PCE_USB_DEVICE CEdevice, u16 Op, u16 Index, void *Data);
++BOOLEAN CEusbFeatureRequest(PCE_USB_DEVICE CEdevice, u16 Op, u16 FeatureSelector, u16 Index);
++BOOLEAN CEusbGetDescriptorRequest(PCE_USB_DEVICE CEdevice, short urbLength, u8 DescriptorType, u8 Index, u16 LanguageId, void *TransferBuffer, u32 TransferBufferLength);
++#endif
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/wifi.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/wifi.h
+new file mode 100644
+index 000000000..82f69476d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/wifi.h
+@@ -0,0 +1,1357 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _WIFI_H_
++#define _WIFI_H_
++
++
++#ifndef BIT
++#define BIT(x)	(1 << (x))
++#endif
++#ifndef BIT_ULL
++#define BIT_ULL(x)	(1ULL << (x))
++#endif
++
++
++#define WLAN_ETHHDR_LEN		14
++#define WLAN_ETHADDR_LEN	6
++#define WLAN_IEEE_OUI_LEN	3
++#define WLAN_ADDR_LEN		6
++#define WLAN_CRC_LEN		4
++#define WLAN_BSSID_LEN		6
++#define WLAN_BSS_TS_LEN		8
++#define WLAN_HDR_A3_LEN		24
++#define WLAN_HDR_A4_LEN		30
++#define WLAN_HDR_A3_QOS_LEN	26
++#define WLAN_HDR_A4_QOS_LEN	32
++#define WLAN_SSID_MAXLEN	32
++#define WLAN_DATA_MAXLEN	2312
++
++#define WLAN_A3_PN_OFFSET	24
++#define WLAN_A4_PN_OFFSET	30
++
++#define WLAN_MIN_ETHFRM_LEN	60
++#define WLAN_MAX_ETHFRM_LEN	1514
++#define WLAN_ETHHDR_LEN		14
++#define WLAN_WMM_LEN		24
++#define VENDOR_NAME_LEN		20
++
++#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
++#define WLAN_MAX_VENDOR_IE_LEN 255
++#define WLAN_MAX_VENDOR_IE_NUM 5
++#define WIFI_BEACON_VENDOR_IE_BIT BIT(0)
++#define WIFI_PROBEREQ_VENDOR_IE_BIT BIT(1)
++#define WIFI_PROBERESP_VENDOR_IE_BIT BIT(2)
++#define WIFI_ASSOCREQ_VENDOR_IE_BIT BIT(3)
++#define WIFI_ASSOCRESP_VENDOR_IE_BIT BIT(4)
++#ifdef CONFIG_P2P
++#define WIFI_P2P_PROBEREQ_VENDOR_IE_BIT BIT(5)
++#define WIFI_P2P_PROBERESP_VENDOR_IE_BIT BIT(6)
++#define WLAN_MAX_VENDOR_IE_MASK_MAX 7
++#else
++#define WLAN_MAX_VENDOR_IE_MASK_MAX 5
++#endif
++#endif
++
++#define P80211CAPTURE_VERSION	0x80211001
++
++/* This value is tested by WiFi 11n Test Plan 5.2.3.
++ * This test verifies the WLAN NIC can update the NAV through sending the CTS with large duration. */
++#define	WiFiNavUpperUs				30000	/* 30 ms */
++
++#ifdef GREEN_HILL
++#pragma pack(1)
++#endif
++
++enum WIFI_FRAME_TYPE {
++	WIFI_MGT_TYPE  =	(0),
++	WIFI_CTRL_TYPE =	(BIT(2)),
++	WIFI_DATA_TYPE =	(BIT(3)),
++	WIFI_QOS_DATA_TYPE	= (BIT(7) | BIT(3)),	/* !< QoS Data	 */
++};
++
++enum WIFI_FRAME_SUBTYPE {
++
++	/* below is for mgt frame */
++	WIFI_ASSOCREQ       = (0 | WIFI_MGT_TYPE),
++	WIFI_ASSOCRSP       = (BIT(4) | WIFI_MGT_TYPE),
++	WIFI_REASSOCREQ     = (BIT(5) | WIFI_MGT_TYPE),
++	WIFI_REASSOCRSP     = (BIT(5) | BIT(4) | WIFI_MGT_TYPE),
++	WIFI_PROBEREQ       = (BIT(6) | WIFI_MGT_TYPE),
++	WIFI_PROBERSP       = (BIT(6) | BIT(4) | WIFI_MGT_TYPE),
++	WIFI_BEACON         = (BIT(7) | WIFI_MGT_TYPE),
++	WIFI_ATIM           = (BIT(7) | BIT(4) | WIFI_MGT_TYPE),
++	WIFI_DISASSOC       = (BIT(7) | BIT(5) | WIFI_MGT_TYPE),
++	WIFI_AUTH           = (BIT(7) | BIT(5) | BIT(4) | WIFI_MGT_TYPE),
++	WIFI_DEAUTH         = (BIT(7) | BIT(6) | WIFI_MGT_TYPE),
++	WIFI_ACTION         = (BIT(7) | BIT(6) | BIT(4) | WIFI_MGT_TYPE),
++	WIFI_ACTION_NOACK = (BIT(7) | BIT(6) | BIT(5) | WIFI_MGT_TYPE),
++
++	/* below is for control frame */
++	WIFI_BF_REPORT_POLL = (BIT(6) | WIFI_CTRL_TYPE),
++	WIFI_NDPA         = (BIT(6) | BIT(4) | WIFI_CTRL_TYPE),
++	WIFI_BAR            = (BIT(7) | WIFI_CTRL_TYPE),
++	WIFI_PSPOLL         = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE),
++	WIFI_RTS            = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE),
++	WIFI_CTS            = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE),
++	WIFI_ACK            = (BIT(7) | BIT(6) | BIT(4) | WIFI_CTRL_TYPE),
++	WIFI_CFEND          = (BIT(7) | BIT(6) | BIT(5) | WIFI_CTRL_TYPE),
++	WIFI_CFEND_CFACK    = (BIT(7) | BIT(6) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE),
++
++	/* below is for data frame */
++	WIFI_DATA           = (0 | WIFI_DATA_TYPE),
++	WIFI_DATA_CFACK     = (BIT(4) | WIFI_DATA_TYPE),
++	WIFI_DATA_CFPOLL    = (BIT(5) | WIFI_DATA_TYPE),
++	WIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | WIFI_DATA_TYPE),
++	WIFI_DATA_NULL      = (BIT(6) | WIFI_DATA_TYPE),
++	WIFI_CF_ACK         = (BIT(6) | BIT(4) | WIFI_DATA_TYPE),
++	WIFI_CF_POLL        = (BIT(6) | BIT(5) | WIFI_DATA_TYPE),
++	WIFI_CF_ACKPOLL     = (BIT(6) | BIT(5) | BIT(4) | WIFI_DATA_TYPE),
++	WIFI_QOS_DATA_NULL	= (BIT(6) | WIFI_QOS_DATA_TYPE),
++};
++
++enum WIFI_REASON_CODE	{
++	_RSON_RESERVED_					= 0,
++	_RSON_UNSPECIFIED_				= 1,
++	_RSON_AUTH_NO_LONGER_VALID_		= 2,
++	_RSON_DEAUTH_STA_LEAVING_		= 3,
++	_RSON_INACTIVITY_				= 4,
++	_RSON_UNABLE_HANDLE_			= 5,
++	_RSON_CLS2_						= 6,
++	_RSON_CLS3_						= 7,
++	_RSON_DISAOC_STA_LEAVING_		= 8,
++	_RSON_ASOC_NOT_AUTH_			= 9,
++
++	/* WPA reason */
++	_RSON_INVALID_IE_				= 13,
++	_RSON_MIC_FAILURE_				= 14,
++	_RSON_4WAY_HNDSHK_TIMEOUT_		= 15,
++	_RSON_GROUP_KEY_UPDATE_TIMEOUT_	= 16,
++	_RSON_DIFF_IE_					= 17,
++	_RSON_MLTCST_CIPHER_NOT_VALID_	= 18,
++	_RSON_UNICST_CIPHER_NOT_VALID_	= 19,
++	_RSON_AKMP_NOT_VALID_			= 20,
++	_RSON_UNSUPPORT_RSNE_VER_		= 21,
++	_RSON_INVALID_RSNE_CAP_			= 22,
++	_RSON_IEEE_802DOT1X_AUTH_FAIL_	= 23,
++
++	/* belowing are Realtek definition */
++	_RSON_PMK_NOT_AVAILABLE_		= 24,
++	_RSON_TDLS_TEAR_TOOFAR_			= 25,
++	_RSON_TDLS_TEAR_UN_RSN_			= 26,
++};
++
++/* Reason codes (IEEE 802.11-2007, 7.3.1.7, Table 7-22) */
++#if 0
++#define WLAN_REASON_UNSPECIFIED 1
++#define WLAN_REASON_PREV_AUTH_NOT_VALID 2
++#define WLAN_REASON_DEAUTH_LEAVING 3
++#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4
++#define WLAN_REASON_DISASSOC_AP_BUSY 5
++#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6
++#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7
++#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8
++#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9
++#endif
++/* IEEE 802.11h */
++#define WLAN_REASON_PWR_CAPABILITY_NOT_VALID 10
++#define WLAN_REASON_SUPPORTED_CHANNEL_NOT_VALID 11
++#if 0
++/* IEEE 802.11i */
++#define WLAN_REASON_INVALID_IE 13
++#define WLAN_REASON_MICHAEL_MIC_FAILURE 14
++#define WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT 15
++#define WLAN_REASON_GROUP_KEY_UPDATE_TIMEOUT 16
++#define WLAN_REASON_IE_IN_4WAY_DIFFERS 17
++#define WLAN_REASON_GROUP_CIPHER_NOT_VALID 18
++#define WLAN_REASON_PAIRWISE_CIPHER_NOT_VALID 19
++#define WLAN_REASON_AKMP_NOT_VALID 20
++#define WLAN_REASON_UNSUPPORTED_RSN_IE_VERSION 21
++#define WLAN_REASON_INVALID_RSN_IE_CAPAB 22
++#define WLAN_REASON_IEEE_802_1X_AUTH_FAILED 23
++#define WLAN_REASON_CIPHER_SUITE_REJECTED 24
++#endif
++
++enum WIFI_STATUS_CODE {
++	_STATS_SUCCESSFUL_			= 0,
++	_STATS_FAILURE_				= 1,
++	_STATS_SEC_DISABLED_			= 5,
++	_STATS_NOT_IN_SAME_BSS_		= 7,
++	_STATS_CAP_FAIL_			= 10,
++	_STATS_NO_ASOC_				= 11,
++	_STATS_OTHER_				= 12,
++	_STATS_NO_SUPP_ALG_			= 13,
++	_STATS_OUT_OF_AUTH_SEQ_		= 14,
++	_STATS_CHALLENGE_FAIL_		= 15,
++	_STATS_AUTH_TIMEOUT_		= 16,
++	_STATS_UNABLE_HANDLE_STA_	= 17,
++	_STATS_RATE_FAIL_			= 18,
++	_STATS_REFUSED_TEMPORARILY_ = 30,
++	_STATS_DECLINE_REQ_			= 37,
++	_STATS_INVALID_PARAMETERS_	= 38,
++	_STATS_INVALID_RSNIE_			= 72,
++};
++
++/* Status codes (IEEE 802.11-2007, 7.3.1.9, Table 7-23) */
++#if 0
++#define WLAN_STATUS_SUCCESS 0
++#define WLAN_STATUS_UNSPECIFIED_FAILURE 1
++#define WLAN_STATUS_CAPS_UNSUPPORTED 10
++#define WLAN_STATUS_REASSOC_NO_ASSOC 11
++#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12
++#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13
++#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14
++#define WLAN_STATUS_CHALLENGE_FAIL 15
++#define WLAN_STATUS_AUTH_TIMEOUT 16
++#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17
++#define WLAN_STATUS_ASSOC_DENIED_RATES 18
++#endif
++/* entended */
++/* IEEE 802.11b */
++#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19
++#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20
++#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21
++/* IEEE 802.11h */
++#define WLAN_STATUS_SPEC_MGMT_REQUIRED 22
++#define WLAN_STATUS_PWR_CAPABILITY_NOT_VALID 23
++#define WLAN_STATUS_SUPPORTED_CHANNEL_NOT_VALID 24
++/* IEEE 802.11g */
++#define WLAN_STATUS_ASSOC_DENIED_NO_SHORT_SLOT_TIME 25
++#define WLAN_STATUS_ASSOC_DENIED_NO_ER_PBCC 26
++#define WLAN_STATUS_ASSOC_DENIED_NO_DSSS_OFDM 27
++/* IEEE 802.11w */
++#define WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY 30
++#define WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION 31
++/* IEEE 802.11i */
++#define WLAN_STATUS_INVALID_IE 40
++#define WLAN_STATUS_GROUP_CIPHER_NOT_VALID 41
++#define WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID 42
++#define WLAN_STATUS_AKMP_NOT_VALID 43
++#define WLAN_STATUS_UNSUPPORTED_RSN_IE_VERSION 44
++#define WLAN_STATUS_INVALID_RSN_IE_CAPAB 45
++#define WLAN_STATUS_CIPHER_REJECTED_PER_POLICY 46
++#define WLAN_STATUS_TS_NOT_CREATED 47
++#define WLAN_STATUS_DIRECT_LINK_NOT_ALLOWED 48
++#define WLAN_STATUS_DEST_STA_NOT_PRESENT 49
++#define WLAN_STATUS_DEST_STA_NOT_QOS_STA 50
++#define WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE 51
++/* IEEE 802.11r */
++#define WLAN_STATUS_INVALID_FT_ACTION_FRAME_COUNT 52
++#define WLAN_STATUS_INVALID_PMKID 53
++#define WLAN_STATUS_INVALID_MDIE 54
++#define WLAN_STATUS_INVALID_FTIE 55
++
++
++enum WIFI_REG_DOMAIN {
++	DOMAIN_FCC		= 1,
++	DOMAIN_IC		= 2,
++	DOMAIN_ETSI		= 3,
++	DOMAIN_SPAIN	= 4,
++	DOMAIN_FRANCE	= 5,
++	DOMAIN_MKK		= 6,
++	DOMAIN_ISRAEL	= 7,
++	DOMAIN_MKK1		= 8,
++	DOMAIN_MKK2		= 9,
++	DOMAIN_MKK3		= 10,
++	DOMAIN_MAX
++};
++
++#define _TO_DS_		BIT(8)
++#define _FROM_DS_	BIT(9)
++#define _MORE_FRAG_	BIT(10)
++#define _RETRY_		BIT(11)
++#define _PWRMGT_	BIT(12)
++#define _MORE_DATA_	BIT(13)
++#define _PRIVACY_	BIT(14)
++#define _ORDER_			BIT(15)
++
++#define SetToDs(pbuf)	\
++	do	{	\
++		*(unsigned short *)(pbuf) |= cpu_to_le16(_TO_DS_); \
++	} while (0)
++
++#define GetToDs(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_TO_DS_)) != 0)
++
++#define ClearToDs(pbuf)	\
++	do	{	\
++		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_TO_DS_)); \
++	} while (0)
++
++#define SetFrDs(pbuf)	\
++	do	{	\
++		*(unsigned short *)(pbuf) |= cpu_to_le16(_FROM_DS_); \
++	} while (0)
++
++#define GetFrDs(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_FROM_DS_)) != 0)
++
++#define ClearFrDs(pbuf)	\
++	do	{	\
++		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_FROM_DS_)); \
++	} while (0)
++
++#define get_tofr_ds(pframe)	((GetToDs(pframe) << 1) | GetFrDs(pframe))
++
++
++#define SetMFrag(pbuf)	\
++	do	{	\
++		*(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_FRAG_); \
++	} while (0)
++
++#define GetMFrag(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_FRAG_)) != 0)
++
++#define ClearMFrag(pbuf)	\
++	do	{	\
++		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_FRAG_)); \
++	} while (0)
++
++#define SetRetry(pbuf)	\
++	do	{	\
++		*(unsigned short *)(pbuf) |= cpu_to_le16(_RETRY_); \
++	} while (0)
++
++#define GetRetry(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_RETRY_)) != 0)
++
++#define ClearRetry(pbuf)	\
++	do	{	\
++		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_RETRY_)); \
++	} while (0)
++
++#define SetPwrMgt(pbuf)	\
++	do	{	\
++		*(unsigned short *)(pbuf) |= cpu_to_le16(_PWRMGT_); \
++	} while (0)
++
++#define GetPwrMgt(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_PWRMGT_)) != 0)
++
++#define ClearPwrMgt(pbuf)	\
++	do	{	\
++		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_PWRMGT_)); \
++	} while (0)
++
++#define SetMData(pbuf)	\
++	do	{	\
++		*(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_DATA_); \
++	} while (0)
++
++#define GetMData(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_DATA_)) != 0)
++
++#define ClearMData(pbuf)	\
++	do	{	\
++		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_DATA_)); \
++	} while (0)
++
++#define SetPrivacy(pbuf)	\
++	do	{	\
++		*(unsigned short *)(pbuf) |= cpu_to_le16(_PRIVACY_); \
++	} while (0)
++
++#define GetPrivacy(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_PRIVACY_)) != 0)
++
++#define ClearPrivacy(pbuf)	\
++	do	{	\
++		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_PRIVACY_)); \
++	} while (0)
++
++
++#define GetOrder(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0)
++
++#define GetFrameType(pbuf)	(le16_to_cpu(*(unsigned short *)(pbuf)) & (BIT(3) | BIT(2)))
++
++#define SetFrameType(pbuf, type)	\
++	do {	\
++		*(unsigned short *)(pbuf) &= __constant_cpu_to_le16(~(BIT(3) | BIT(2))); \
++		*(unsigned short *)(pbuf) |= __constant_cpu_to_le16(type); \
++	} while (0)
++
++#define get_frame_sub_type(pbuf)	(cpu_to_le16(*(unsigned short *)(pbuf)) & (BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2)))
++
++
++#define set_frame_sub_type(pbuf, type) \
++	do {    \
++		*(unsigned short *)(pbuf) &= cpu_to_le16(~(BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))); \
++		*(unsigned short *)(pbuf) |= cpu_to_le16(type); \
++	} while (0)
++
++
++#define GetSequence(pbuf)	(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) >> 4)
++
++#define GetFragNum(pbuf)	(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & 0x0f)
++
++#define GetTupleCache(pbuf)	(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)))
++
++#define SetFragNum(pbuf, num) \
++	do {    \
++		*(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \
++			((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu(~(0x000f))) | \
++				cpu_to_le16(0x0f & (num));     \
++	} while (0)
++
++#define SetSeqNum(pbuf, num) \
++	do {    \
++		*(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \
++			((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu((unsigned short)~0xfff0)) | \
++			le16_to_cpu((unsigned short)(0xfff0 & (num << 4))); \
++	} while (0)
++
++#define set_duration(pbuf, dur) \
++	do {    \
++		*(unsigned short *)((SIZE_PTR)(pbuf) + 2) = cpu_to_le16(0xffff & (dur)); \
++	} while (0)
++
++
++/* QoS control field */
++#define SetPriority(qc, tid)	SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 0, 4, tid)
++#define SetEOSP(qc, eosp)		SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 4, 1, eosp)
++#define SetAckpolicy(qc, ack)	SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 5, 2, ack)
++#define SetAMsdu(qc, amsdu)		SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 7, 1, amsdu)
++
++#define GetPriority(qc)		LE_BITS_TO_2BYTE(((u8 *)(qc)), 0, 4)
++#define GetEOSP(qc)			LE_BITS_TO_2BYTE(((u8 *)(qc)), 4, 1)
++#define GetAckpolicy(qc)	LE_BITS_TO_2BYTE(((u8 *)(qc)), 5, 2)
++#define GetAMsdu(qc)		LE_BITS_TO_2BYTE(((u8 *)(qc)), 7, 1)
++
++/* QoS control field (MSTA only) */
++#define set_mctrl_present(qc, p)	SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 8, 1, p)
++#define set_mps_lv(qc, lv)			SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 9, 1, lv)
++#define set_rspi(qc, rspi)			SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 10, 1, rspi)
++
++#define get_mctrl_present(qc)	LE_BITS_TO_2BYTE(((u8 *)(qc)), 8, 1)
++#define get_mps_lv(qc)			LE_BITS_TO_2BYTE(((u8 *)(qc)), 9, 1)
++#define get_rspi(qc)			LE_BITS_TO_2BYTE(((u8 *)(qc)), 10, 1)
++
++
++#define GetAid(pbuf)	(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 2)) & 0x3fff)
++
++#define GetTid(pbuf)	(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + (((GetToDs(pbuf)<<1) | GetFrDs(pbuf)) == 3 ? 30 : 24))) & 0x000f)
++
++#define GetAddr1Ptr(pbuf)	((unsigned char *)((SIZE_PTR)(pbuf) + 4))
++
++#define get_addr2_ptr(pbuf)	((unsigned char *)((SIZE_PTR)(pbuf) + 10))
++
++#define GetAddr3Ptr(pbuf)	((unsigned char *)((SIZE_PTR)(pbuf) + 16))
++
++#define GetAddr4Ptr(pbuf)	((unsigned char *)((SIZE_PTR)(pbuf) + 24))
++
++
++#define MacAddr_isBcst(addr) \
++	(\
++	 ((addr[0] == 0xff) && (addr[1] == 0xff) && \
++	  (addr[2] == 0xff) && (addr[3] == 0xff) && \
++	  (addr[4] == 0xff) && (addr[5] == 0xff)) ? _TRUE : _FALSE \
++	)
++
++__inline static int IS_MCAST(const u8 *da)
++{
++	if ((*da) & 0x01)
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++__inline static unsigned char *get_ra(unsigned char *pframe)
++{
++	unsigned char	*ra;
++	ra = GetAddr1Ptr(pframe);
++	return ra;
++}
++__inline static unsigned char *get_ta(unsigned char *pframe)
++{
++	unsigned char	*ta;
++	ta = get_addr2_ptr(pframe);
++	return ta;
++}
++
++/* can't apply to mesh mode */
++__inline static unsigned char *get_da(unsigned char *pframe)
++{
++	unsigned char	*da;
++	unsigned int	to_fr_ds	= (GetToDs(pframe) << 1) | GetFrDs(pframe);
++
++	switch (to_fr_ds) {
++	case 0x00:	/* ToDs=0, FromDs=0 */
++		da = GetAddr1Ptr(pframe);
++		break;
++	case 0x01:	/* ToDs=0, FromDs=1 */
++		da = GetAddr1Ptr(pframe);
++		break;
++	case 0x02:	/* ToDs=1, FromDs=0 */
++		da = GetAddr3Ptr(pframe);
++		break;
++	default:	/* ToDs=1, FromDs=1 */
++		da = GetAddr3Ptr(pframe);
++		break;
++	}
++
++	return da;
++}
++
++/* can't apply to mesh mode */
++__inline static unsigned char *get_sa(unsigned char *pframe)
++{
++	unsigned char	*sa;
++	unsigned int	to_fr_ds	= (GetToDs(pframe) << 1) | GetFrDs(pframe);
++
++	switch (to_fr_ds) {
++	case 0x00:	/* ToDs=0, FromDs=0 */
++		sa = get_addr2_ptr(pframe);
++		break;
++	case 0x01:	/* ToDs=0, FromDs=1 */
++		sa = GetAddr3Ptr(pframe);
++		break;
++	case 0x02:	/* ToDs=1, FromDs=0 */
++		sa = get_addr2_ptr(pframe);
++		break;
++	default:	/* ToDs=1, FromDs=1 */
++		sa = GetAddr4Ptr(pframe);
++		break;
++	}
++
++	return sa;
++}
++
++/* can't apply to mesh mode */
++__inline static unsigned char *get_hdr_bssid(unsigned char *pframe)
++{
++	unsigned char	*sa = NULL;
++	unsigned int	to_fr_ds	= (GetToDs(pframe) << 1) | GetFrDs(pframe);
++
++	switch (to_fr_ds) {
++	case 0x00:	/* ToDs=0, FromDs=0 */
++		sa = GetAddr3Ptr(pframe);
++		break;
++	case 0x01:	/* ToDs=0, FromDs=1 */
++		sa = get_addr2_ptr(pframe);
++		break;
++	case 0x02:	/* ToDs=1, FromDs=0 */
++		sa = GetAddr1Ptr(pframe);
++		break;
++	case 0x03:	/* ToDs=1, FromDs=1 */
++		sa = GetAddr1Ptr(pframe);
++		break;
++	}
++
++	return sa;
++}
++
++
++__inline static int IsFrameTypeCtrl(unsigned char *pframe)
++{
++	if (WIFI_CTRL_TYPE == GetFrameType(pframe))
++		return _TRUE;
++	else
++		return _FALSE;
++}
++static inline int IsFrameTypeMgnt(unsigned char *pframe)
++{
++	if (GetFrameType(pframe) == WIFI_MGT_TYPE)
++		return _TRUE;
++	else
++		return _FALSE;
++}
++static inline int IsFrameTypeData(unsigned char *pframe)
++{
++	if (GetFrameType(pframe) == WIFI_DATA_TYPE)
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++
++/*-----------------------------------------------------------------------------
++			Below is for the security related definition
++------------------------------------------------------------------------------*/
++#define _RESERVED_FRAME_TYPE_	0
++#define _SKB_FRAME_TYPE_		2
++#define _PRE_ALLOCMEM_			1
++#define _PRE_ALLOCHDR_			3
++#define _PRE_ALLOCLLCHDR_		4
++#define _PRE_ALLOCICVHDR_		5
++#define _PRE_ALLOCMICHDR_		6
++
++#define _SIFSTIME_				((priv->pmib->dot11BssType.net_work_type&WIRELESS_11A) ? 16 : 10)
++#define _ACKCTSLNG_				14	/* 14 bytes long, including crclng */
++#define _CRCLNG_				4
++
++#define _ASOCREQ_IE_OFFSET_		4	/* excluding wlan_hdr */
++#define	_ASOCRSP_IE_OFFSET_		6
++#define _REASOCREQ_IE_OFFSET_	10
++#define _REASOCRSP_IE_OFFSET_	6
++#define _PROBEREQ_IE_OFFSET_	0
++#define	_PROBERSP_IE_OFFSET_	12
++#define _AUTH_IE_OFFSET_		6
++#define _DEAUTH_IE_OFFSET_		0
++#define _BEACON_IE_OFFSET_		12
++#define _PUBLIC_ACTION_IE_OFFSET_	8
++
++#define _FIXED_IE_LENGTH_			_BEACON_IE_OFFSET_
++
++#define _SSID_IE_				0
++#define _SUPPORTEDRATES_IE_	1
++#define _DSSET_IE_				3
++#define _TIM_IE_					5
++#define _IBSS_PARA_IE_			6
++#define _COUNTRY_IE_			7
++#define _CHLGETXT_IE_			16
++#define _SUPPORTED_CH_IE_		36
++#define _CH_SWTICH_ANNOUNCE_	37	/* Secondary Channel Offset */
++#define	_MEAS_REQ_IE_		38
++#define	_MEAS_RSP_IE_		39
++#define _RSN_IE_2_				48
++#define _SSN_IE_1_					221
++#define _ERPINFO_IE_			42
++#define _EXT_SUPPORTEDRATES_IE_	50
++
++#define _HT_CAPABILITY_IE_			45
++#define _MDIE_					54
++#define _FTIE_					55
++#define _TIMEOUT_ITVL_IE_			56
++#define _SRC_IE_				59
++#define _HT_EXTRA_INFO_IE_			61
++#define _HT_ADD_INFO_IE_			61 /* _HT_EXTRA_INFO_IE_ */
++#define _WAPI_IE_				68
++#define _EID_RRM_EN_CAP_IE_			70
++
++
++/* #define EID_BSSCoexistence			72 */ /* 20/40 BSS Coexistence
++ * #define EID_BSSIntolerantChlReport	73 */
++#define _RIC_Descriptor_IE_			75
++#ifdef CONFIG_IEEE80211W
++#define _MME_IE_					76 /* 802.11w Management MIC element */
++#endif /* CONFIG_IEEE80211W */
++#define _LINK_ID_IE_					101
++#define _CH_SWITCH_TIMING_		104
++#define _PTI_BUFFER_STATUS_		106
++#define _EXT_CAP_IE_				127
++#define _VENDOR_SPECIFIC_IE_		221
++
++#define	_RESERVED47_				47
++
++typedef	enum _ELEMENT_ID {
++	EID_SsId					= 0, /* service set identifier (0:32) */
++	EID_SupRates				= 1, /* supported rates (1:8) */
++	EID_FHParms				= 2, /* FH parameter set (5) */
++	EID_DSParms				= 3, /* DS parameter set (1) */
++	EID_CFParms				= 4, /* CF parameter set (6) */
++	EID_Tim						= 5, /* Traffic Information Map (4:254) */
++	EID_IbssParms				= 6, /* IBSS parameter set (2) */
++	EID_Country					= 7, /* */
++
++	/* Form 7.3.2: Information elements in 802.11E/D13.0, page 46. */
++	EID_QBSSLoad				= 11,
++	EID_EDCAParms				= 12,
++	EID_TSpec					= 13,
++	EID_TClass					= 14,
++	EID_Schedule				= 15,
++	/*  */
++
++	EID_Ctext					= 16, /* challenge text*/
++	EID_POWER_CONSTRAINT		= 32, /* Power Constraint*/
++
++	/* vivi for WIFITest, 802.11h AP, 20100427 */
++	/* 2010/12/26 MH The definition we can declare always!! */
++	EID_PowerCap				= 33,
++	EID_TPC				= 35,
++	EID_SupportedChannels		= 36,
++	EID_ChlSwitchAnnounce		= 37,
++
++	EID_MeasureRequest			= 38, /* Measurement Request */
++	EID_MeasureReport			= 39, /* Measurement Report */
++
++	EID_ERPInfo				= 42,
++
++	/* Form 7.3.2: Information elements in 802.11E/D13.0, page 46. */
++	EID_TSDelay				= 43,
++	EID_TCLASProc				= 44,
++	EID_HTCapability			= 45,
++	EID_QoSCap					= 46,
++	/*  */
++
++	EID_WPA2					= 48,
++	EID_ExtSupRates			= 50,
++
++	EID_FTIE					= 55, /* Defined in 802.11r */
++	EID_Timeout				= 56, /* Defined in 802.11r */
++
++	EID_SupRegulatory			= 59, /* Supported Requlatory Classes 802.11y */
++	EID_HTInfo					= 61,
++	EID_SecondaryChnlOffset		= 62,
++
++	EID_BSSCoexistence			= 72, /* 20/40 BSS Coexistence */
++	EID_BSSIntolerantChlReport	= 73,
++	EID_OBSS					= 74, /* Overlapping BSS Scan Parameters */
++
++	EID_LinkIdentifier			= 101, /* Defined in 802.11z */
++	EID_WakeupSchedule		= 102, /* Defined in 802.11z */
++	EID_ChnlSwitchTimeing		= 104, /* Defined in 802.11z */
++	EID_PTIControl				= 105, /* Defined in 802.11z */
++	EID_PUBufferStatus			= 106, /* Defined in 802.11z */
++
++	EID_EXTCapability			= 127, /* Extended Capabilities */
++	/* From S19:Aironet IE and S21:AP IP address IE in CCX v1.13, p16 and p18. */
++	EID_Aironet					= 133, /* 0x85: Aironet Element for Cisco CCX */
++	EID_CiscoIP					= 149, /* 0x95: IP Address IE for Cisco CCX */
++
++	EID_CellPwr					= 150, /* 0x96: Cell Power Limit IE. Ref. 0x96. */
++
++	EID_CCKM					= 156,
++
++	EID_Vendor					= 221, /* 0xDD: Vendor Specific */
++
++	EID_WAPI					= 68,
++	EID_VHTCapability 			= 191, /* Based on 802.11ac D2.0 */
++	EID_VHTOperation 			= 192, /* Based on 802.11ac D2.0 */
++	EID_AID						= 197, /* Based on 802.11ac D4.0 */
++	EID_OpModeNotification		= 199, /* Based on 802.11ac D3.0 */
++} ELEMENT_ID, *PELEMENT_ID;
++
++/* ---------------------------------------------------------------------------
++					Below is the fixed elements...
++-----------------------------------------------------------------------------*/
++#define _AUTH_ALGM_NUM_			2
++#define _AUTH_SEQ_NUM_			2
++#define _BEACON_ITERVAL_		2
++#define _CAPABILITY_			2
++#define _CURRENT_APADDR_		6
++#define _LISTEN_INTERVAL_		2
++#define _RSON_CODE_				2
++#define _ASOC_ID_				2
++#define _STATUS_CODE_			2
++#define _TIMESTAMP_				8
++
++#define AUTH_ODD_TO				0
++#define AUTH_EVEN_TO			1
++
++#define WLAN_ETHCONV_ENCAP		1
++#define WLAN_ETHCONV_RFC1042	2
++#define WLAN_ETHCONV_8021h		3
++
++#define cap_ESS BIT(0)
++#define cap_IBSS BIT(1)
++#define cap_CFPollable BIT(2)
++#define cap_CFRequest BIT(3)
++#define cap_Privacy BIT(4)
++#define cap_ShortPremble BIT(5)
++#define cap_PBCC	BIT(6)
++#define cap_ChAgility	BIT(7)
++#define cap_SpecMgmt	BIT(8)
++#define cap_QoS	BIT(9)
++#define cap_ShortSlot	BIT(10)
++
++/*-----------------------------------------------------------------------------
++				Below is the definition for 802.11i / 802.1x
++------------------------------------------------------------------------------*/
++#define _IEEE8021X_MGT_			1		/* WPA */
++#define _IEEE8021X_PSK_			2		/* WPA with pre-shared key */
++
++#if 0
++#define _NO_PRIVACY_			0
++#define _WEP_40_PRIVACY_		1
++#define _TKIP_PRIVACY_			2
++#define _WRAP_PRIVACY_			3
++#define _CCMP_PRIVACY_			4
++#define _WEP_104_PRIVACY_		5
++#define _WEP_WPA_MIXED_PRIVACY_ 6	/*  WEP + WPA */
++#endif
++
++#define _MME_IE_LENGTH_  26
++
++/*-----------------------------------------------------------------------------
++				Below is the definition for WMM
++------------------------------------------------------------------------------*/
++#define _WMM_IE_Length_				7  /* for WMM STA */
++
++
++/*-----------------------------------------------------------------------------
++				Below is the definition for 802.11n
++------------------------------------------------------------------------------*/
++
++/* #ifdef CONFIG_80211N_HT */
++
++#define set_order_bit(pbuf)	\
++		do	{	\
++			*(unsigned short *)(pbuf) |= cpu_to_le16(_ORDER_); \
++		} while (0)
++
++
++
++#define GetOrderBit(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0)
++
++#define ACT_CAT_VENDOR				0x7F/* 127 */
++
++/**
++ * struct rtw_ieee80211_bar - HT Block Ack Request
++ *
++ * This structure refers to "HT BlockAckReq" as
++ * described in 802.11n draft section 7.2.1.7.1
++ */
++#if defined(PLATFORM_LINUX)
++struct rtw_ieee80211_bar {
++	unsigned short frame_control;
++	unsigned short duration;
++	unsigned char ra[6];
++	unsigned char ta[6];
++	unsigned short control;
++	unsigned short start_seq_num;
++} __attribute__((packed));
++#endif
++
++/* 802.11 BAR control masks */
++#define IEEE80211_BAR_CTRL_ACK_POLICY_NORMAL     0x0000
++#define IEEE80211_BAR_CTRL_CBMTID_COMPRESSED_BA  0x0004
++
++
++#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
++
++
++
++/**
++* struct rtw_ieee80211_ht_cap - HT capabilities
++*
++* This structure refers to "HT capabilities element" as
++* described in 802.11n draft section 7.3.2.52
++*/
++
++struct rtw_ieee80211_ht_cap {
++	unsigned short	cap_info;
++	unsigned char	ampdu_params_info;
++	unsigned char	supp_mcs_set[16];
++	unsigned short	extended_ht_cap_info;
++	unsigned int		tx_BF_cap_info;
++	unsigned char	       antenna_selection_info;
++} __attribute__((packed));
++
++/**
++ * struct rtw_ieee80211_ht_cap - HT additional information
++ *
++ * This structure refers to "HT information element" as
++ * described in 802.11n draft section 7.3.2.53
++ */
++#ifndef CONFIG_IEEE80211_HT_ADDT_INFO
++struct ieee80211_ht_addt_info {
++	unsigned char	control_chan;
++	unsigned char		ht_param;
++	unsigned short	operation_mode;
++	unsigned short	stbc_param;
++	unsigned char		basic_set[16];
++} __attribute__((packed));
++#endif
++
++struct HT_caps_element {
++	union {
++		struct {
++			unsigned short	HT_caps_info;
++			unsigned char	AMPDU_para;
++			unsigned char	MCS_rate[16];
++			unsigned short	HT_ext_caps;
++			unsigned int	Beamforming_caps;
++			unsigned char	ASEL_caps;
++		} HT_cap_element;
++		unsigned char HT_cap[26];
++	} u;
++} __attribute__((packed));
++
++struct HT_info_element {
++	unsigned char	primary_channel;
++	unsigned char	infos[5];
++	unsigned char	MCS_rate[16];
++}  __attribute__((packed));
++
++struct AC_param {
++	unsigned char		ACI_AIFSN;
++	unsigned char		CW;
++	unsigned short	TXOP_limit;
++}  __attribute__((packed));
++
++struct WMM_para_element {
++	unsigned char		QoS_info;
++	unsigned char		reserved;
++	struct AC_param	ac_param[4];
++}  __attribute__((packed));
++
++struct ADDBA_request {
++	unsigned char		dialog_token;
++	unsigned short	BA_para_set;
++	unsigned short	BA_timeout_value;
++	unsigned short	BA_starting_seqctrl;
++}  __attribute__((packed));
++
++
++
++#endif
++
++
++typedef enum _HT_CAP_AMPDU_FACTOR {
++	MAX_AMPDU_FACTOR_8K		= 0,
++	MAX_AMPDU_FACTOR_16K	= 1,
++	MAX_AMPDU_FACTOR_32K	= 2,
++	MAX_AMPDU_FACTOR_64K	= 3,
++} HT_CAP_AMPDU_FACTOR;
++
++typedef enum _VHT_CAP_AMPDU_FACTOR {
++	MAX_AMPDU_FACTOR_128K = 4,
++	MAX_AMPDU_FACTOR_256K = 5,
++	MAX_AMPDU_FACTOR_512K = 6,
++	MAX_AMPDU_FACTOR_1M = 7,
++} VHT_CAP_AMPDU_FACTOR;
++
++
++typedef enum _HT_CAP_AMPDU_DENSITY {
++	AMPDU_DENSITY_VALUE_0 = 0 , /* For no restriction */
++	AMPDU_DENSITY_VALUE_1 = 1 , /* For 1/4 us */
++	AMPDU_DENSITY_VALUE_2 = 2 , /* For 1/2 us */
++	AMPDU_DENSITY_VALUE_3 = 3 , /* For 1 us */
++	AMPDU_DENSITY_VALUE_4 = 4 , /* For 2 us */
++	AMPDU_DENSITY_VALUE_5 = 5 , /* For 4 us */
++	AMPDU_DENSITY_VALUE_6 = 6 , /* For 8 us */
++	AMPDU_DENSITY_VALUE_7 = 7 , /* For 16 us */
++} HT_CAP_AMPDU_DENSITY;
++
++/* 802.11n HT capabilities masks */
++#define IEEE80211_HT_CAP_LDPC_CODING		0x0001
++#define IEEE80211_HT_CAP_SUP_WIDTH		0x0002
++#define IEEE80211_HT_CAP_SM_PS			0x000C
++#define IEEE80211_HT_CAP_GRN_FLD		0x0010
++#define IEEE80211_HT_CAP_SGI_20			0x0020
++#define IEEE80211_HT_CAP_SGI_40			0x0040
++#define IEEE80211_HT_CAP_TX_STBC			0x0080
++#define IEEE80211_HT_CAP_RX_STBC_1R		0x0100
++#define IEEE80211_HT_CAP_RX_STBC_2R		0x0200
++#define IEEE80211_HT_CAP_RX_STBC_3R		0x0300
++#define IEEE80211_HT_CAP_DELAY_BA		0x0400
++#define IEEE80211_HT_CAP_MAX_AMSDU		0x0800
++#define IEEE80211_HT_CAP_DSSSCCK40		0x1000
++#define RTW_IEEE80211_HT_CAP_40MHZ_INTOLERANT	((u16) BIT(14))
++/* 802.11n HT capability AMPDU settings */
++#define IEEE80211_HT_CAP_AMPDU_FACTOR		0x03
++#define IEEE80211_HT_CAP_AMPDU_DENSITY		0x1C
++/* 802.11n HT capability MSC set */
++#define IEEE80211_SUPP_MCS_SET_UEQM		4
++#define IEEE80211_HT_CAP_MAX_STREAMS		4
++#define IEEE80211_SUPP_MCS_SET_LEN		10
++/* maximum streams the spec allows */
++#define IEEE80211_HT_CAP_MCS_TX_DEFINED		0x01
++#define IEEE80211_HT_CAP_MCS_TX_RX_DIFF		0x02
++#define IEEE80211_HT_CAP_MCS_TX_STREAMS		0x0C
++#define IEEE80211_HT_CAP_MCS_TX_UEQM		0x10
++/* 802.11n HT capability TXBF capability */
++#define IEEE80211_HT_CAP_TXBF_RX_NDP		0x00000008
++#define IEEE80211_HT_CAP_TXBF_TX_NDP		0x00000010
++#define IEEE80211_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP	0x00000400
++
++/* 802.11n HT IE masks */
++#define IEEE80211_HT_IE_CHA_SEC_OFFSET		0x03
++#define IEEE80211_HT_IE_CHA_SEC_NONE		0x00
++#define IEEE80211_HT_IE_CHA_SEC_ABOVE		0x01
++#define IEEE80211_HT_IE_CHA_SEC_BELOW		0x03
++#define IEEE80211_HT_IE_CHA_WIDTH		0x04
++#define IEEE80211_HT_IE_HT_PROTECTION		0x0003
++#define IEEE80211_HT_IE_NON_GF_STA_PRSNT	0x0004
++#define IEEE80211_HT_IE_NON_HT_STA_PRSNT	0x0010
++
++/* block-ack parameters */
++#define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002
++#define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C
++#define RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFC0
++#define IEEE80211_DELBA_PARAM_TID_MASK 0xF000
++#define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800
++
++/*
++ * A-PMDU buffer sizes
++ * According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2)
++ */
++#define IEEE80211_MIN_AMPDU_BUF 0x8
++#define IEEE80211_MAX_AMPDU_BUF_HT 0x40
++
++
++/* Spatial Multiplexing Power Save Modes */
++#define WLAN_HT_CAP_SM_PS_STATIC		0
++#define WLAN_HT_CAP_SM_PS_DYNAMIC	1
++#define WLAN_HT_CAP_SM_PS_INVALID	2
++#define WLAN_HT_CAP_SM_PS_DISABLED	3
++
++
++#define OP_MODE_PURE                    0
++#define OP_MODE_MAY_BE_LEGACY_STAS      1
++#define OP_MODE_20MHZ_HT_STA_ASSOCED    2
++#define OP_MODE_MIXED                   3
++
++#define HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK	((u8) BIT(0) | BIT(1))
++#define HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE		((u8) BIT(0))
++#define HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW		((u8) BIT(0) | BIT(1))
++#define HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH		((u8) BIT(2))
++#define HT_INFO_HT_PARAM_RIFS_MODE			((u8) BIT(3))
++#define HT_INFO_HT_PARAM_CTRL_ACCESS_ONLY		((u8) BIT(4))
++#define HT_INFO_HT_PARAM_SRV_INTERVAL_GRANULARITY	((u8) BIT(5))
++
++#define HT_INFO_OPERATION_MODE_OP_MODE_MASK	\
++	((u16) (0x0001 | 0x0002))
++#define HT_INFO_OPERATION_MODE_OP_MODE_OFFSET		0
++#define HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT	((u8) BIT(2))
++#define HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT	((u8) BIT(3))
++#define HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT	((u8) BIT(4))
++
++#define HT_INFO_STBC_PARAM_DUAL_BEACON			((u16) BIT(6))
++#define HT_INFO_STBC_PARAM_DUAL_STBC_PROTECT		((u16) BIT(7))
++#define HT_INFO_STBC_PARAM_SECONDARY_BCN		((u16) BIT(8))
++#define HT_INFO_STBC_PARAM_LSIG_TXOP_PROTECT_ALLOWED	((u16) BIT(9))
++#define HT_INFO_STBC_PARAM_PCO_ACTIVE			((u16) BIT(10))
++#define HT_INFO_STBC_PARAM_PCO_PHASE			((u16) BIT(11))
++
++
++
++/* #endif */
++
++/*	===============WPS Section=============== */
++/*	For WPSv1.0 */
++#define WPSOUI							0x0050f204
++/*	WPS attribute ID */
++#define WPS_ATTR_VER1					0x104A
++#define WPS_ATTR_SIMPLE_CONF_STATE	0x1044
++#define WPS_ATTR_RESP_TYPE			0x103B
++#define WPS_ATTR_UUID_E				0x1047
++#define WPS_ATTR_MANUFACTURER		0x1021
++#define WPS_ATTR_MODEL_NAME			0x1023
++#define WPS_ATTR_MODEL_NUMBER		0x1024
++#define WPS_ATTR_SERIAL_NUMBER		0x1042
++#define WPS_ATTR_PRIMARY_DEV_TYPE	0x1054
++#define WPS_ATTR_SEC_DEV_TYPE_LIST	0x1055
++#define WPS_ATTR_DEVICE_NAME			0x1011
++#define WPS_ATTR_CONF_METHOD			0x1008
++#define WPS_ATTR_RF_BANDS				0x103C
++#define WPS_ATTR_DEVICE_PWID			0x1012
++#define WPS_ATTR_REQUEST_TYPE			0x103A
++#define WPS_ATTR_ASSOCIATION_STATE	0x1002
++#define WPS_ATTR_CONFIG_ERROR			0x1009
++#define WPS_ATTR_VENDOR_EXT			0x1049
++#define WPS_ATTR_SELECTED_REGISTRAR	0x1041
++
++/*	Value of WPS attribute "WPS_ATTR_DEVICE_NAME */
++#define WPS_MAX_DEVICE_NAME_LEN		32
++
++/*	Value of WPS Request Type Attribute */
++#define WPS_REQ_TYPE_ENROLLEE_INFO_ONLY			0x00
++#define WPS_REQ_TYPE_ENROLLEE_OPEN_8021X		0x01
++#define WPS_REQ_TYPE_REGISTRAR					0x02
++#define WPS_REQ_TYPE_WLAN_MANAGER_REGISTRAR	0x03
++
++/*	Value of WPS Response Type Attribute */
++#define WPS_RESPONSE_TYPE_INFO_ONLY	0x00
++#define WPS_RESPONSE_TYPE_8021X		0x01
++#define WPS_RESPONSE_TYPE_REGISTRAR	0x02
++#define WPS_RESPONSE_TYPE_AP			0x03
++
++/*	Value of WPS WiFi Simple Configuration State Attribute */
++#define WPS_WSC_STATE_NOT_CONFIG	0x01
++#define WPS_WSC_STATE_CONFIG			0x02
++
++/*	Value of WPS Version Attribute */
++#define WPS_VERSION_1					0x10
++
++/*	Value of WPS Configuration Method Attribute */
++#define WPS_CONFIG_METHOD_FLASH		0x0001
++#define WPS_CONFIG_METHOD_ETHERNET	0x0002
++#define WPS_CONFIG_METHOD_LABEL		0x0004
++#define WPS_CONFIG_METHOD_DISPLAY	0x0008
++#define WPS_CONFIG_METHOD_E_NFC		0x0010
++#define WPS_CONFIG_METHOD_I_NFC		0x0020
++#define WPS_CONFIG_METHOD_NFC		0x0040
++#define WPS_CONFIG_METHOD_PBC		0x0080
++#define WPS_CONFIG_METHOD_KEYPAD	0x0100
++#define WPS_CONFIG_METHOD_VPBC		0x0280
++#define WPS_CONFIG_METHOD_PPBC		0x0480
++#define WPS_CONFIG_METHOD_VDISPLAY	0x2008
++#define WPS_CONFIG_METHOD_PDISPLAY	0x4008
++
++/*	Value of Category ID of WPS Primary Device Type Attribute */
++#define WPS_PDT_CID_DISPLAYS			0x0007
++#define WPS_PDT_CID_MULIT_MEDIA		0x0008
++#define WPS_PDT_CID_RTK_WIDI			WPS_PDT_CID_MULIT_MEDIA
++
++/*	Value of Sub Category ID of WPS Primary Device Type Attribute */
++#define WPS_PDT_SCID_MEDIA_SERVER	0x0005
++#define WPS_PDT_SCID_RTK_DMP			WPS_PDT_SCID_MEDIA_SERVER
++
++/*	Value of Device Password ID */
++#define WPS_DPID_PIN					0x0000
++#define WPS_DPID_USER_SPEC			0x0001
++#define WPS_DPID_MACHINE_SPEC			0x0002
++#define WPS_DPID_REKEY					0x0003
++#define WPS_DPID_PBC					0x0004
++#define WPS_DPID_REGISTRAR_SPEC		0x0005
++
++/*	Value of WPS RF Bands Attribute */
++#define WPS_RF_BANDS_2_4_GHZ		0x01
++#define WPS_RF_BANDS_5_GHZ		0x02
++
++/*	Value of WPS Association State Attribute */
++#define WPS_ASSOC_STATE_NOT_ASSOCIATED			0x00
++#define WPS_ASSOC_STATE_CONNECTION_SUCCESS		0x01
++#define WPS_ASSOC_STATE_CONFIGURATION_FAILURE	0x02
++#define WPS_ASSOC_STATE_ASSOCIATION_FAILURE		0x03
++#define WPS_ASSOC_STATE_IP_FAILURE				0x04
++
++/*	=====================P2P Section===================== */
++/*	For P2P */
++#define	P2POUI							0x506F9A09
++
++/*	P2P Attribute ID */
++#define	P2P_ATTR_STATUS					0x00
++#define	P2P_ATTR_MINOR_REASON_CODE		0x01
++#define	P2P_ATTR_CAPABILITY				0x02
++#define	P2P_ATTR_DEVICE_ID				0x03
++#define	P2P_ATTR_GO_INTENT				0x04
++#define	P2P_ATTR_CONF_TIMEOUT			0x05
++#define	P2P_ATTR_LISTEN_CH				0x06
++#define	P2P_ATTR_GROUP_BSSID				0x07
++#define	P2P_ATTR_EX_LISTEN_TIMING		0x08
++#define	P2P_ATTR_INTENDED_IF_ADDR		0x09
++#define	P2P_ATTR_MANAGEABILITY			0x0A
++#define	P2P_ATTR_CH_LIST					0x0B
++#define	P2P_ATTR_NOA						0x0C
++#define	P2P_ATTR_DEVICE_INFO				0x0D
++#define	P2P_ATTR_GROUP_INFO				0x0E
++#define	P2P_ATTR_GROUP_ID					0x0F
++#define	P2P_ATTR_INTERFACE				0x10
++#define	P2P_ATTR_OPERATING_CH			0x11
++#define	P2P_ATTR_INVITATION_FLAGS		0x12
++
++/*	Value of Status Attribute */
++#define	P2P_STATUS_SUCCESS						0x00
++#define	P2P_STATUS_FAIL_INFO_UNAVAILABLE		0x01
++#define	P2P_STATUS_FAIL_INCOMPATIBLE_PARAM		0x02
++#define	P2P_STATUS_FAIL_LIMIT_REACHED			0x03
++#define	P2P_STATUS_FAIL_INVALID_PARAM			0x04
++#define	P2P_STATUS_FAIL_REQUEST_UNABLE			0x05
++#define	P2P_STATUS_FAIL_PREVOUS_PROTO_ERR		0x06
++#define	P2P_STATUS_FAIL_NO_COMMON_CH			0x07
++#define	P2P_STATUS_FAIL_UNKNOWN_P2PGROUP		0x08
++#define	P2P_STATUS_FAIL_BOTH_GOINTENT_15		0x09
++#define	P2P_STATUS_FAIL_INCOMPATIBLE_PROVSION	0x0A
++#define	P2P_STATUS_FAIL_USER_REJECT				0x0B
++
++/*	Value of Inviation Flags Attribute */
++#define	P2P_INVITATION_FLAGS_PERSISTENT			BIT(0)
++
++#define	DMP_P2P_DEVCAP_SUPPORT	(P2P_DEVCAP_SERVICE_DISCOVERY | \
++				 P2P_DEVCAP_CLIENT_DISCOVERABILITY | \
++				 P2P_DEVCAP_CONCURRENT_OPERATION | \
++				 P2P_DEVCAP_INVITATION_PROC)
++
++#define	DMP_P2P_GRPCAP_SUPPORT	(P2P_GRPCAP_INTRABSS)
++
++/*	Value of Device Capability Bitmap */
++#define	P2P_DEVCAP_SERVICE_DISCOVERY		BIT(0)
++#define	P2P_DEVCAP_CLIENT_DISCOVERABILITY	BIT(1)
++#define	P2P_DEVCAP_CONCURRENT_OPERATION	BIT(2)
++#define	P2P_DEVCAP_INFRA_MANAGED			BIT(3)
++#define	P2P_DEVCAP_DEVICE_LIMIT				BIT(4)
++#define	P2P_DEVCAP_INVITATION_PROC			BIT(5)
++
++/*	Value of Group Capability Bitmap */
++#define	P2P_GRPCAP_GO							BIT(0)
++#define	P2P_GRPCAP_PERSISTENT_GROUP			BIT(1)
++#define	P2P_GRPCAP_GROUP_LIMIT				BIT(2)
++#define	P2P_GRPCAP_INTRABSS					BIT(3)
++#define	P2P_GRPCAP_CROSS_CONN				BIT(4)
++#define	P2P_GRPCAP_PERSISTENT_RECONN		BIT(5)
++#define	P2P_GRPCAP_GROUP_FORMATION			BIT(6)
++
++/*	P2P Public Action Frame ( Management Frame ) */
++#define	P2P_PUB_ACTION_ACTION				0x09
++
++/*	P2P Public Action Frame Type */
++#define	P2P_GO_NEGO_REQ						0
++#define	P2P_GO_NEGO_RESP						1
++#define	P2P_GO_NEGO_CONF						2
++#define	P2P_INVIT_REQ							3
++#define	P2P_INVIT_RESP							4
++#define	P2P_DEVDISC_REQ						5
++#define	P2P_DEVDISC_RESP						6
++#define	P2P_PROVISION_DISC_REQ				7
++#define	P2P_PROVISION_DISC_RESP				8
++
++/*	P2P Action Frame Type */
++#define	P2P_NOTICE_OF_ABSENCE	0
++#define	P2P_PRESENCE_REQUEST		1
++#define	P2P_PRESENCE_RESPONSE	2
++#define	P2P_GO_DISC_REQUEST		3
++
++
++#define	P2P_MAX_PERSISTENT_GROUP_NUM		10
++
++#define	P2P_PROVISIONING_SCAN_CNT			3
++
++#define	P2P_WILDCARD_SSID_LEN				7
++
++#define	P2P_FINDPHASE_EX_NONE				0	/* default value, used when: (1)p2p disabed or (2)p2p enabled but only do 1 scan phase */
++#define	P2P_FINDPHASE_EX_FULL				1	/* used when p2p enabled and want to do 1 scan phase and P2P_FINDPHASE_EX_MAX-1 find phase */
++#define	P2P_FINDPHASE_EX_SOCIAL_FIRST		(P2P_FINDPHASE_EX_FULL+1)
++#define	P2P_FINDPHASE_EX_MAX					4
++#define	P2P_FINDPHASE_EX_SOCIAL_LAST		P2P_FINDPHASE_EX_MAX
++
++#define	P2P_PROVISION_TIMEOUT				5000	/*	5 seconds timeout for sending the provision discovery request */
++#define	P2P_CONCURRENT_PROVISION_TIMEOUT	3000	/*	3 seconds timeout for sending the provision discovery request under concurrent mode */
++#define	P2P_GO_NEGO_TIMEOUT					5000	/*	5 seconds timeout for receiving the group negotation response */
++#define	P2P_CONCURRENT_GO_NEGO_TIMEOUT		3000	/*	3 seconds timeout for sending the negotiation request under concurrent mode */
++#define	P2P_TX_PRESCAN_TIMEOUT				100		/*	100ms */
++#define	P2P_INVITE_TIMEOUT					5000	/*	5 seconds timeout for sending the invitation request */
++#define	P2P_CONCURRENT_INVITE_TIMEOUT		3000	/*	3 seconds timeout for sending the invitation request under concurrent mode */
++#define	P2P_RESET_SCAN_CH						25000	/*	25 seconds timeout to reset the scan channel (based on channel plan) */
++#define	P2P_MAX_INTENT						15
++
++#define	P2P_MAX_NOA_NUM						2
++
++/*	WPS Configuration Method */
++#define	WPS_CM_NONE							0x0000
++#define	WPS_CM_LABEL							0x0004
++#define	WPS_CM_DISPLYA						0x0008
++#define	WPS_CM_EXTERNAL_NFC_TOKEN			0x0010
++#define	WPS_CM_INTEGRATED_NFC_TOKEN		0x0020
++#define	WPS_CM_NFC_INTERFACE					0x0040
++#define	WPS_CM_PUSH_BUTTON					0x0080
++#define	WPS_CM_KEYPAD						0x0100
++#define	WPS_CM_SW_PUHS_BUTTON				0x0280
++#define	WPS_CM_HW_PUHS_BUTTON				0x0480
++#define	WPS_CM_SW_DISPLAY_PIN				0x2008
++#define	WPS_CM_LCD_DISPLAY_PIN				0x4008
++
++enum P2P_ROLE {
++	P2P_ROLE_DISABLE = 0,
++	P2P_ROLE_DEVICE = 1,
++	P2P_ROLE_CLIENT = 2,
++	P2P_ROLE_GO = 3
++};
++
++enum P2P_STATE {
++	P2P_STATE_NONE = 0,							/*	P2P disable */
++	P2P_STATE_IDLE = 1,								/*	P2P had enabled and do nothing ,  buddy adapters is linked */
++	P2P_STATE_LISTEN = 2,							/*	In pure listen state */
++	P2P_STATE_SCAN = 3,							/*	In scan phase */
++	P2P_STATE_FIND_PHASE_LISTEN = 4,				/*	In the listen state of find phase */
++	P2P_STATE_FIND_PHASE_SEARCH = 5,				/*	In the search state of find phase */
++	P2P_STATE_TX_PROVISION_DIS_REQ = 6,			/*	In P2P provisioning discovery */
++	P2P_STATE_RX_PROVISION_DIS_RSP = 7,
++	P2P_STATE_RX_PROVISION_DIS_REQ = 8,
++	P2P_STATE_GONEGO_ING = 9,						/*	Doing the group owner negoitation handshake */
++	P2P_STATE_GONEGO_OK = 10,						/*	finish the group negoitation handshake with success */
++	P2P_STATE_GONEGO_FAIL = 11,					/*	finish the group negoitation handshake with failure */
++	P2P_STATE_RECV_INVITE_REQ_MATCH = 12,		/*	receiving the P2P Inviation request and match with the profile. */
++	P2P_STATE_PROVISIONING_ING = 13,				/*	Doing the P2P WPS */
++	P2P_STATE_PROVISIONING_DONE = 14,			/*	Finish the P2P WPS */
++	P2P_STATE_TX_INVITE_REQ = 15,					/*	Transmit the P2P Invitation request */
++	P2P_STATE_RX_INVITE_RESP_OK = 16,				/*	Receiving the P2P Invitation response */
++	P2P_STATE_RECV_INVITE_REQ_DISMATCH = 17,	/*	receiving the P2P Inviation request and dismatch with the profile. */
++	P2P_STATE_RECV_INVITE_REQ_GO = 18,			/*	receiving the P2P Inviation request and this wifi is GO. */
++	P2P_STATE_RECV_INVITE_REQ_JOIN = 19,			/*	receiving the P2P Inviation request to join an existing P2P Group. */
++	P2P_STATE_RX_INVITE_RESP_FAIL = 20,			/*	recveing the P2P Inviation response with failure */
++	P2P_STATE_RX_INFOR_NOREADY = 21,			/* receiving p2p negoitation response with information is not available */
++	P2P_STATE_TX_INFOR_NOREADY = 22,			/* sending p2p negoitation response with information is not available */
++};
++
++enum P2P_WPSINFO {
++	P2P_NO_WPSINFO						= 0,
++	P2P_GOT_WPSINFO_PEER_DISPLAY_PIN	= 1,
++	P2P_GOT_WPSINFO_SELF_DISPLAY_PIN	= 2,
++	P2P_GOT_WPSINFO_PBC					= 3,
++};
++
++#define	P2P_PRIVATE_IOCTL_SET_LEN		64
++
++enum P2P_PROTO_WK_ID {
++	P2P_FIND_PHASE_WK = 0,
++	P2P_RESTORE_STATE_WK = 1,
++	P2P_PRE_TX_PROVDISC_PROCESS_WK = 2,
++	P2P_PRE_TX_NEGOREQ_PROCESS_WK = 3,
++	P2P_PRE_TX_INVITEREQ_PROCESS_WK = 4,
++	P2P_AP_P2P_CH_SWITCH_PROCESS_WK = 5,
++	P2P_RO_CH_WK = 6,
++	P2P_CANCEL_RO_CH_WK = 7,
++};
++
++#ifdef CONFIG_P2P_PS
++enum P2P_PS_STATE {
++	P2P_PS_DISABLE = 0,
++	P2P_PS_ENABLE = 1,
++	P2P_PS_SCAN = 2,
++	P2P_PS_SCAN_DONE = 3,
++	P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
++};
++
++enum P2P_PS_MODE {
++	P2P_PS_NONE = 0,
++	P2P_PS_CTWINDOW = 1,
++	P2P_PS_NOA	 = 2,
++	P2P_PS_MIX = 3, /* CTWindow and NoA */
++};
++#endif /* CONFIG_P2P_PS */
++
++/*	=====================WFD Section=====================
++ *	For Wi-Fi Display */
++#define	WFD_ATTR_DEVICE_INFO			0x00
++#define	WFD_ATTR_ASSOC_BSSID			0x01
++#define	WFD_ATTR_COUPLED_SINK_INFO	0x06
++#define	WFD_ATTR_LOCAL_IP_ADDR		0x08
++#define	WFD_ATTR_SESSION_INFO		0x09
++#define	WFD_ATTR_ALTER_MAC			0x0a
++
++/*	For WFD Device Information Attribute */
++#define	WFD_DEVINFO_SOURCE					0x0000
++#define	WFD_DEVINFO_PSINK					0x0001
++#define	WFD_DEVINFO_SSINK					0x0002
++#define	WFD_DEVINFO_DUAL					0x0003
++
++#define	WFD_DEVINFO_SESSION_AVAIL			0x0010
++#define	WFD_DEVINFO_WSD						0x0040
++#define	WFD_DEVINFO_PC_TDLS					0x0080
++#define	WFD_DEVINFO_HDCP_SUPPORT			0x0100
++
++#define IP_MCAST_MAC(mac)		((mac[0] == 0x01) && (mac[1] == 0x00) && (mac[2] == 0x5e))
++#define ICMPV6_MCAST_MAC(mac)	((mac[0] == 0x33) && (mac[1] == 0x33) && (mac[2] != 0xff))
++
++#ifdef CONFIG_IOCTL_CFG80211
++/* Regulatroy Domain */
++struct regd_pair_mapping {
++	u16 reg_dmnenum;
++	u16 reg_5ghz_ctl;
++	u16 reg_2ghz_ctl;
++};
++
++struct rtw_regulatory {
++	char alpha2[2];
++	u16 country_code;
++	u16 max_power_level;
++	u32 tp_scale;
++	u16 current_rd;
++	u16 current_rd_ext;
++	int16_t power_limit;
++	struct regd_pair_mapping *regpair;
++};
++#endif
++
++#ifdef CONFIG_WAPI_SUPPORT
++#ifndef IW_AUTH_WAPI_VERSION_1
++#define IW_AUTH_WAPI_VERSION_1		0x00000008
++#endif
++#ifndef IW_AUTH_KEY_MGMT_WAPI_PSK
++#define IW_AUTH_KEY_MGMT_WAPI_PSK	0x04
++#endif
++#ifndef IW_AUTH_WAPI_ENABLED
++#define IW_AUTH_WAPI_ENABLED		0x20
++#endif
++#ifndef IW_ENCODE_ALG_SM4
++#define IW_ENCODE_ALG_SM4			0x20
++#endif
++#endif
++
++#endif /* _WIFI_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/wlan_bssdef.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/wlan_bssdef.h
+new file mode 100644
+index 000000000..c8f3229b9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/wlan_bssdef.h
+@@ -0,0 +1,327 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __WLAN_BSSDEF_H__
++#define __WLAN_BSSDEF_H__
++
++
++#define MAX_IE_SZ	768
++
++
++#ifdef PLATFORM_LINUX
++
++#define NDIS_802_11_LENGTH_SSID         32
++#define NDIS_802_11_LENGTH_RATES        8
++#define NDIS_802_11_LENGTH_RATES_EX     16
++
++typedef unsigned char   NDIS_802_11_MAC_ADDRESS[ETH_ALEN];
++typedef long    		NDIS_802_11_RSSI;           /* in dBm */
++typedef unsigned char   NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES];        /* Set of 8 data rates */
++typedef unsigned char   NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX];  /* Set of 16 data rates */
++
++typedef struct _NDIS_802_11_SSID {
++	u32  SsidLength;
++	u8  Ssid[32];
++} NDIS_802_11_SSID, *PNDIS_802_11_SSID;
++
++/*
++	FW will only save the channel number in DSConfig.
++	ODI Handler will convert the channel number to freq. number.
++*/
++typedef struct _NDIS_802_11_CONFIGURATION {
++	u32           Length;             /* Length of structure */
++	u32           BeaconPeriod;       /* units are Kusec */
++	u32           ATIMWindow;         /* units are Kusec */
++	u32           DSConfig;           /* channel number */
++} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION;
++
++typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE {
++	Ndis802_11IBSS,
++	Ndis802_11Infrastructure,
++	Ndis802_11AutoUnknown,
++	Ndis802_11InfrastructureMax,     /* Not a real value, defined as upper bound */
++	Ndis802_11APMode,
++	Ndis802_11Monitor,
++	Ndis802_11_mesh,
++} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE;
++
++typedef struct _NDIS_802_11_FIXED_IEs {
++	u8  Timestamp[8];
++	u16  BeaconInterval;
++	u16  Capabilities;
++} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs;
++
++typedef struct _NDIS_802_11_VARIABLE_IEs {
++	u8  ElementID;
++	u8  Length;
++	u8  data[1];
++} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs;
++
++typedef enum _NDIS_802_11_AUTHENTICATION_MODE {
++	Ndis802_11AuthModeOpen,
++	Ndis802_11AuthModeShared,
++	Ndis802_11AuthModeAutoSwitch,
++	Ndis802_11AuthModeWPA,
++	Ndis802_11AuthModeWPAPSK,
++	Ndis802_11AuthModeWPANone,
++	Ndis802_11AuthModeWAPI,
++	Ndis802_11AuthModeMax               /* Not a real mode, defined as upper bound */
++} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE;
++
++typedef enum _NDIS_802_11_WEP_STATUS {
++	Ndis802_11WEPEnabled,
++	Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled,
++	Ndis802_11WEPDisabled,
++	Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled,
++	Ndis802_11WEPKeyAbsent,
++	Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent,
++	Ndis802_11WEPNotSupported,
++	Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported,
++	Ndis802_11Encryption2Enabled,
++	Ndis802_11Encryption2KeyAbsent,
++	Ndis802_11Encryption3Enabled,
++	Ndis802_11Encryption3KeyAbsent,
++	Ndis802_11_EncrypteionWAPI
++} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS,
++NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS;
++
++typedef struct _NDIS_802_11_WEP {
++	u32     Length;        /* Length of this structure */
++	u32     KeyIndex;      /* 0 is the per-client key, 1-N are the global keys */
++	u32     KeyLength;     /* length of key in bytes */
++	u8     KeyMaterial[16];/* variable length depending on above field */
++} NDIS_802_11_WEP, *PNDIS_802_11_WEP;
++
++#endif /* end of #ifdef PLATFORM_LINUX */
++
++#ifdef PLATFORM_FREEBSD
++
++#define NDIS_802_11_LENGTH_SSID         32
++#define NDIS_802_11_LENGTH_RATES        8
++#define NDIS_802_11_LENGTH_RATES_EX     16
++
++typedef unsigned char   NDIS_802_11_MAC_ADDRESS[ETH_ALEN];
++typedef long    		NDIS_802_11_RSSI;           /* in dBm */
++typedef unsigned char   NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES];        /* Set of 8 data rates */
++typedef unsigned char   NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX];  /* Set of 16 data rates */
++
++
++typedef struct _NDIS_802_11_SSID {
++	u32  SsidLength;
++	u8  Ssid[32];
++} NDIS_802_11_SSID, *PNDIS_802_11_SSID;
++
++/*
++	FW will only save the channel number in DSConfig.
++	ODI Handler will convert the channel number to freq. number.
++*/
++typedef struct _NDIS_802_11_CONFIGURATION {
++	u32           Length;             /* Length of structure */
++	u32           BeaconPeriod;       /* units are Kusec */
++	u32           ATIMWindow;         /* units are Kusec */
++	u32           DSConfig;           /* channel number */
++} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION;
++
++typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE {
++	Ndis802_11IBSS,
++	Ndis802_11Infrastructure,
++	Ndis802_11AutoUnknown,
++	Ndis802_11InfrastructureMax,     /* Not a real value, defined as upper bound */
++	Ndis802_11APMode
++} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE;
++
++typedef struct _NDIS_802_11_FIXED_IEs {
++	u8  Timestamp[8];
++	u16  BeaconInterval;
++	u16  Capabilities;
++} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs;
++
++typedef struct _NDIS_802_11_VARIABLE_IEs {
++	u8  ElementID;
++	u8  Length;
++	u8  data[1];
++} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs;
++
++typedef enum _NDIS_802_11_AUTHENTICATION_MODE {
++	Ndis802_11AuthModeOpen,
++	Ndis802_11AuthModeShared,
++	Ndis802_11AuthModeAutoSwitch,
++	Ndis802_11AuthModeWPA,
++	Ndis802_11AuthModeWPAPSK,
++	Ndis802_11AuthModeWPANone,
++	Ndis802_11AuthModeMax               /* Not a real mode, defined as upper bound */
++} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE;
++
++typedef enum _NDIS_802_11_WEP_STATUS {
++	Ndis802_11WEPEnabled,
++	Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled,
++	Ndis802_11WEPDisabled,
++	Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled,
++	Ndis802_11WEPKeyAbsent,
++	Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent,
++	Ndis802_11WEPNotSupported,
++	Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported,
++	Ndis802_11Encryption2Enabled,
++	Ndis802_11Encryption2KeyAbsent,
++	Ndis802_11Encryption3Enabled,
++	Ndis802_11Encryption3KeyAbsent
++} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS,
++NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS;
++
++
++typedef struct _NDIS_802_11_WEP {
++	u32     Length;        /* Length of this structure */
++	u32     KeyIndex;      /* 0 is the per-client key, 1-N are the global keys */
++	u32     KeyLength;     /* length of key in bytes */
++	u8     KeyMaterial[16];/* variable length depending on above field */
++} NDIS_802_11_WEP, *PNDIS_802_11_WEP;
++
++#endif /* PLATFORM_FREEBSD */
++
++#ifndef Ndis802_11APMode
++#define Ndis802_11APMode (Ndis802_11InfrastructureMax+1)
++#endif
++
++typedef struct _WLAN_PHY_INFO {
++	u8	SignalStrength;/* (in percentage) */
++	u8	SignalQuality;/* (in percentage) */
++	u8	Optimum_antenna;  /* for Antenna diversity */
++	u8	is_cck_rate;	/* 1:cck_rate */
++	s8	rx_snr[4];
++#ifdef CONFIG_RTW_80211K
++	u32	free_cnt; 	/* freerun counter */
++	u8	rm_en_cap[5];
++#endif
++} WLAN_PHY_INFO, *PWLAN_PHY_INFO;
++
++typedef struct _WLAN_BCN_INFO {
++	/* these infor get from rtw_get_encrypt_info when
++	 *	 * translate scan to UI */
++	u8 encryp_protocol;/* ENCRYP_PROTOCOL_E: OPEN/WEP/WPA/WPA2/WAPI */
++	int group_cipher; /* WPA/WPA2 group cipher */
++	int pairwise_cipher;/* //WPA/WPA2/WEP pairwise cipher */
++	int is_8021x;
++
++	/* bwmode 20/40 and ch_offset UP/LOW */
++	unsigned short	ht_cap_info;
++	unsigned char	ht_info_infos_0;
++} WLAN_BCN_INFO, *PWLAN_BCN_INFO;
++
++enum bss_type {
++	BSS_TYPE_UNDEF,
++	BSS_TYPE_PROB_REQ = 1,
++	BSS_TYPE_BCN = 2,
++	BSS_TYPE_PROB_RSP = 3,
++};
++
++/* temporally add #pragma pack for structure alignment issue of
++*   WLAN_BSSID_EX and get_WLAN_BSSID_EX_sz()
++*/
++typedef struct _WLAN_BSSID_EX {
++	u32  Length;
++	NDIS_802_11_MAC_ADDRESS  MacAddress;
++	u8  Reserved[2];/* [0]: IS beacon frame , bss_type*/
++	NDIS_802_11_SSID  Ssid;
++	NDIS_802_11_SSID  mesh_id;
++	u32  Privacy;
++	NDIS_802_11_RSSI  Rssi;/* (in dBM,raw data ,get from PHY) */
++	NDIS_802_11_CONFIGURATION  Configuration;
++	NDIS_802_11_NETWORK_INFRASTRUCTURE  InfrastructureMode;
++	NDIS_802_11_RATES_EX  SupportedRates;
++	WLAN_PHY_INFO	PhyInfo;
++	u32  IELength;
++	u8  IEs[MAX_IE_SZ];	/* (timestamp, beacon interval, and capability information) */
++}
++__attribute__((packed)) WLAN_BSSID_EX, *PWLAN_BSSID_EX;
++
++#define BSS_EX_IES(bss_ex) ((bss_ex)->IEs)
++#define BSS_EX_IES_LEN(bss_ex) ((bss_ex)->IELength)
++#define BSS_EX_FIXED_IE_OFFSET(bss_ex) ((bss_ex)->Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12)
++#define BSS_EX_TLV_IES(bss_ex) (BSS_EX_IES((bss_ex)) + BSS_EX_FIXED_IE_OFFSET((bss_ex)))
++#define BSS_EX_TLV_IES_LEN(bss_ex) (BSS_EX_IES_LEN((bss_ex)) - BSS_EX_FIXED_IE_OFFSET((bss_ex)))
++
++__inline  static uint get_WLAN_BSSID_EX_sz(WLAN_BSSID_EX *bss)
++{
++	return sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + bss->IELength;
++}
++
++struct beacon_keys {
++	u8 ssid[IW_ESSID_MAX_SIZE];
++	u32 ssid_len;
++	u8 ch;
++	u8 bw;
++	u8 offset;
++	u8 proto_cap; /* PROTO_CAP_XXX */
++	u8 rate_set[12];
++	u8 rate_num;
++	int encryp_protocol;
++	int pairwise_cipher;
++	int group_cipher;
++	u32 akm;
++};
++
++struct	wlan_network {
++	_list	list;
++	int	network_type;	/* refer to ieee80211.h for WIRELESS_11A/B/G */
++	int	fixed;			/* set to fixed when not to be removed as site-surveying */
++	systime last_scanned; /* timestamp for the network */
++	systime last_non_hidden_ssid_ap;
++#ifdef CONFIG_RTW_MESH
++#if CONFIG_RTW_MESH_ACNODE_PREVENT
++	systime acnode_stime;
++	systime acnode_notify_etime;
++#endif
++#endif
++	int	aid;			/* will only be valid when a BSS is joinned. */
++	int	join_res;
++	struct beacon_keys bcn_keys;
++	bool bcn_keys_valid;
++	WLAN_BSSID_EX	network; /* must be the last item */
++};
++
++enum VRTL_CARRIER_SENSE {
++	DISABLE_VCS,
++	ENABLE_VCS,
++	AUTO_VCS
++};
++
++enum VCS_TYPE {
++	NONE_VCS,
++	RTS_CTS,
++	CTS_TO_SELF
++};
++
++
++
++
++#define PWR_CAM 0
++#define PWR_MINPS 1
++#define PWR_MAXPS 2
++#define PWR_UAPSD 3
++#define PWR_VOIP 4
++
++
++enum UAPSD_MAX_SP {
++	NO_LIMIT,
++	TWO_MSDU,
++	FOUR_MSDU,
++	SIX_MSDU
++};
++
++
++/* john */
++#define NUM_PRE_AUTH_KEY 16
++#define NUM_PMKID_CACHE NUM_PRE_AUTH_KEY
++
++#endif /* #ifndef WLAN_BSSDEF_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/xmit_osdep.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/xmit_osdep.h
+new file mode 100644
+index 000000000..9bf9c93d5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/include/xmit_osdep.h
+@@ -0,0 +1,96 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __XMIT_OSDEP_H_
++#define __XMIT_OSDEP_H_
++
++
++struct pkt_file {
++	_pkt *pkt;
++	SIZE_T pkt_len;	 /* the remainder length of the open_file */
++	_buffer *cur_buffer;
++	u8 *buf_start;
++	u8 *cur_addr;
++	SIZE_T buf_len;
++};
++
++#ifdef PLATFORM_WINDOWS
++
++#ifdef PLATFORM_OS_XP
++#ifdef CONFIG_USB_HCI
++#include <usb.h>
++#include <usbdlib.h>
++#include <usbioctl.h>
++#endif
++#endif
++
++#ifdef CONFIG_GSPI_HCI
++	#define NR_XMITFRAME     64
++#else
++	#define NR_XMITFRAME     128
++#endif
++
++#define ETH_ALEN	6
++
++extern NDIS_STATUS rtw_xmit_entry(
++	_nic_hdl		cnxt,
++	NDIS_PACKET		*pkt,
++	u32				flags
++);
++
++#endif /* PLATFORM_WINDOWS */
++
++#ifdef PLATFORM_FREEBSD
++#define NR_XMITFRAME	256
++extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev);
++extern void rtw_xmit_entry_wrap(struct ifnet *pifp);
++#endif /* PLATFORM_FREEBSD */
++
++#ifdef PLATFORM_LINUX
++
++#define NR_XMITFRAME	256
++
++struct xmit_priv;
++struct pkt_attrib;
++struct sta_xmit_priv;
++struct xmit_frame;
++struct xmit_buf;
++
++extern int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev);
++extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev);
++
++#endif /* PLATFORM_LINUX */
++
++void rtw_os_xmit_schedule(_adapter *padapter);
++
++int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 alloc_sz, u8 flag);
++void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 free_sz, u8 flag);
++
++extern void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib);
++
++extern uint rtw_remainder_len(struct pkt_file *pfile);
++extern void _rtw_open_pktfile(_pkt *pkt, struct pkt_file *pfile);
++extern uint _rtw_pktfile_read(struct pkt_file *pfile, u8 *rmem, uint rlen);
++extern sint rtw_endofpktfile(struct pkt_file *pfile);
++
++extern void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt);
++extern void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe);
++
++void rtw_os_check_wakup_queue(_adapter *adapter, u16 os_qid);
++bool rtw_os_check_stop_queue(_adapter *adapter, u16 os_qid);
++void rtw_os_wake_queue_at_free_stainfo(_adapter *padapter, int *qcnt_freed);
++
++void dump_os_queue(void *sel, _adapter *padapter);
++
++#endif /* __XMIT_OSDEP_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/custom_gpio_linux.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/custom_gpio_linux.c
+new file mode 100644
+index 000000000..34fe17494
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/custom_gpio_linux.c
+@@ -0,0 +1,377 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#include "drv_types.h"
++
++#ifdef CONFIG_PLATFORM_SPRD
++
++/* gspi func & GPIO define */
++#include <mach/gpio.h>/* 0915 */
++#include <mach/board.h>
++
++#if !(defined ANDROID_2X)
++
++#ifdef CONFIG_RTL8188E
++#include <mach/regulator.h>
++#include <linux/regulator/consumer.h>
++#endif /* CONFIG_RTL8188E */
++
++#ifndef GPIO_WIFI_POWER
++#define GPIO_WIFI_POWER -1
++#endif /* !GPIO_WIFI_POWER */
++
++#ifndef GPIO_WIFI_RESET
++#define GPIO_WIFI_RESET -1
++#endif /* !GPIO_WIFI_RESET */
++
++#ifndef GPIO_WIFI_PWDN
++#define GPIO_WIFI_PWDN -1
++#endif /* !GPIO_WIFI_RESET */
++#ifdef CONFIG_GSPI_HCI
++extern unsigned int oob_irq;
++#endif /* CONFIG_GSPI_HCI */
++
++#ifdef CONFIG_SDIO_HCI
++extern int rtw_mp_mode;
++#else /* !CONFIG_SDIO_HCI */
++#endif /* !CONFIG_SDIO_HCI */
++
++int rtw_wifi_gpio_init(void)
++{
++#ifdef CONFIG_GSPI_HCI
++	if (GPIO_WIFI_IRQ > 0) {
++		gpio_request(GPIO_WIFI_IRQ, "oob_irq");
++		gpio_direction_input(GPIO_WIFI_IRQ);
++
++		oob_irq = gpio_to_irq(GPIO_WIFI_IRQ);
++
++		RTW_INFO("%s oob_irq:%d\n", __func__, oob_irq);
++	}
++#endif
++	if (GPIO_WIFI_RESET > 0)
++		gpio_request(GPIO_WIFI_RESET , "wifi_rst");
++	if (GPIO_WIFI_POWER > 0)
++		gpio_request(GPIO_WIFI_POWER, "wifi_power");
++
++#ifdef CONFIG_SDIO_HCI
++#if (defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1)
++	if (rtw_mp_mode == 1) {
++		RTW_INFO("%s GPIO_BT_RESET pin special for mp_test\n", __func__);
++		if (GPIO_BT_RESET > 0)
++			gpio_request(GPIO_BT_RESET , "bt_rst");
++	}
++#endif
++#endif
++	return 0;
++}
++
++int rtw_wifi_gpio_deinit(void)
++{
++#ifdef CONFIG_GSPI_HCI
++	if (GPIO_WIFI_IRQ > 0)
++		gpio_free(GPIO_WIFI_IRQ);
++#endif
++	if (GPIO_WIFI_RESET > 0)
++		gpio_free(GPIO_WIFI_RESET);
++	if (GPIO_WIFI_POWER > 0)
++		gpio_free(GPIO_WIFI_POWER);
++
++#ifdef CONFIG_SDIO_HCI
++#if (defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1)
++	if (rtw_mp_mode == 1) {
++		RTW_INFO("%s GPIO_BT_RESET pin special for mp_test\n", __func__);
++		if (GPIO_BT_RESET > 0)
++			gpio_free(GPIO_BT_RESET);
++	}
++#endif
++#endif
++	return 0;
++}
++
++/* Customer function to control hw specific wlan gpios */
++void rtw_wifi_gpio_wlan_ctrl(int onoff)
++{
++	switch (onoff) {
++	case WLAN_PWDN_OFF:
++		RTW_INFO("%s: call customer specific GPIO(%d) to set wifi power down pin to 0\n",
++			 __FUNCTION__, GPIO_WIFI_RESET);
++
++#ifndef CONFIG_DONT_BUS_SCAN
++		if (GPIO_WIFI_RESET > 0)
++			gpio_direction_output(GPIO_WIFI_RESET , 0);
++#endif
++		break;
++
++	case WLAN_PWDN_ON:
++		RTW_INFO("%s: callc customer specific GPIO(%d) to set wifi power down pin to 1\n",
++			 __FUNCTION__, GPIO_WIFI_RESET);
++
++		if (GPIO_WIFI_RESET > 0)
++			gpio_direction_output(GPIO_WIFI_RESET , 1);
++		break;
++
++	case WLAN_POWER_OFF:
++		break;
++
++	case WLAN_POWER_ON:
++		break;
++#ifdef CONFIG_SDIO_HCI
++#if (defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1)
++	case WLAN_BT_PWDN_OFF:
++		if (rtw_mp_mode == 1) {
++			RTW_INFO("%s: call customer specific GPIO to set wifi power down pin to 0\n",
++				 __FUNCTION__);
++			if (GPIO_BT_RESET > 0)
++				gpio_direction_output(GPIO_BT_RESET , 0);
++		}
++		break;
++
++	case WLAN_BT_PWDN_ON:
++		if (rtw_mp_mode == 1) {
++			RTW_INFO("%s: callc customer specific GPIO to set wifi power down pin to 1 %x\n",
++				 __FUNCTION__, GPIO_BT_RESET);
++
++			if (GPIO_BT_RESET > 0)
++				gpio_direction_output(GPIO_BT_RESET , 1);
++		}
++		break;
++#endif
++#endif
++	}
++}
++
++#else /* ANDROID_2X */
++
++#include <mach/ldo.h>
++
++#ifdef CONFIG_RTL8188E
++extern int sprd_3rdparty_gpio_wifi_power;
++#endif
++extern int sprd_3rdparty_gpio_wifi_pwd;
++#if  defined(CONFIG_RTL8723B)
++extern int sprd_3rdparty_gpio_bt_reset;
++#endif
++
++int rtw_wifi_gpio_init(void)
++{
++#if defined(CONFIG_RTL8723B)
++	if (sprd_3rdparty_gpio_bt_reset > 0)
++		gpio_direction_output(sprd_3rdparty_gpio_bt_reset, 1);
++#endif
++
++	return 0;
++}
++
++int rtw_wifi_gpio_deinit(void)
++{
++	return 0;
++}
++
++/* Customer function to control hw specific wlan gpios */
++void rtw_wifi_gpio_wlan_ctrl(int onoff)
++{
++	switch (onoff) {
++	case WLAN_PWDN_OFF:
++		RTW_INFO("%s: call customer specific GPIO to set wifi power down pin to 0\n",
++			 __FUNCTION__);
++		if (sprd_3rdparty_gpio_wifi_pwd > 0)
++			gpio_set_value(sprd_3rdparty_gpio_wifi_pwd, 0);
++
++		if (sprd_3rdparty_gpio_wifi_pwd == 60) {
++			RTW_INFO("%s: turn off VSIM2 2.8V\n", __func__);
++			LDO_TurnOffLDO(LDO_LDO_SIM2);
++		}
++		break;
++
++	case WLAN_PWDN_ON:
++		RTW_INFO("%s: callc customer specific GPIO to set wifi power down pin to 1\n",
++			 __FUNCTION__);
++		if (sprd_3rdparty_gpio_wifi_pwd == 60) {
++			RTW_INFO("%s: turn on VSIM2 2.8V\n", __func__);
++			LDO_SetVoltLevel(LDO_LDO_SIM2, LDO_VOLT_LEVEL0);
++			LDO_TurnOnLDO(LDO_LDO_SIM2);
++		}
++		if (sprd_3rdparty_gpio_wifi_pwd > 0)
++			gpio_set_value(sprd_3rdparty_gpio_wifi_pwd, 1);
++		break;
++
++	case WLAN_POWER_OFF:
++#ifdef CONFIG_RTL8188E
++#ifdef CONFIG_WIF1_LDO
++		RTW_INFO("%s: turn off VDD-WIFI0 1.2V\n", __FUNCTION__);
++		LDO_TurnOffLDO(LDO_LDO_WIF1);
++#endif /* CONFIG_WIF1_LDO */
++
++		RTW_INFO("%s: turn off VDD-WIFI0 3.3V\n", __FUNCTION__);
++		LDO_TurnOffLDO(LDO_LDO_WIF0);
++
++		RTW_INFO("%s: call customer specific GPIO(%d) to turn off wifi power\n",
++			 __FUNCTION__, sprd_3rdparty_gpio_wifi_power);
++		if (sprd_3rdparty_gpio_wifi_power != 65535)
++			gpio_set_value(sprd_3rdparty_gpio_wifi_power, 0);
++#endif
++		break;
++
++	case WLAN_POWER_ON:
++#ifdef CONFIG_RTL8188E
++		RTW_INFO("%s: call customer specific GPIO(%d) to turn on wifi power\n",
++			 __FUNCTION__, sprd_3rdparty_gpio_wifi_power);
++		if (sprd_3rdparty_gpio_wifi_power != 65535)
++			gpio_set_value(sprd_3rdparty_gpio_wifi_power, 1);
++
++		RTW_INFO("%s: turn on VDD-WIFI0 3.3V\n", __FUNCTION__);
++		LDO_TurnOnLDO(LDO_LDO_WIF0);
++		LDO_SetVoltLevel(LDO_LDO_WIF0, LDO_VOLT_LEVEL1);
++
++#ifdef CONFIG_WIF1_LDO
++		RTW_INFO("%s: turn on VDD-WIFI1 1.2V\n", __func__);
++		LDO_TurnOnLDO(LDO_LDO_WIF1);
++		LDO_SetVoltLevel(LDO_LDO_WIF1, LDO_VOLT_LEVEL3);
++#endif /* CONFIG_WIF1_LDO */
++#endif
++		break;
++
++	case WLAN_BT_PWDN_OFF:
++		RTW_INFO("%s: call customer specific GPIO to set bt power down pin to 0\n",
++			 __FUNCTION__);
++#if defined(CONFIG_RTL8723B)
++		if (sprd_3rdparty_gpio_bt_reset > 0)
++			gpio_set_value(sprd_3rdparty_gpio_bt_reset, 0);
++#endif
++		break;
++
++	case WLAN_BT_PWDN_ON:
++		RTW_INFO("%s: callc customer specific GPIO to set bt power down pin to 1\n",
++			 __FUNCTION__);
++#if defined(CONFIG_RTL8723B)
++		if (sprd_3rdparty_gpio_bt_reset > 0)
++			gpio_set_value(sprd_3rdparty_gpio_bt_reset, 1);
++#endif
++		break;
++	}
++}
++#endif /* ANDROID_2X */
++
++#elif defined(CONFIG_PLATFORM_ARM_RK3066)
++#include <mach/iomux.h>
++
++#define GPIO_WIFI_IRQ		RK30_PIN2_PC2
++extern unsigned int oob_irq;
++int rtw_wifi_gpio_init(void)
++{
++#ifdef CONFIG_GSPI_HCI
++	if (GPIO_WIFI_IRQ > 0) {
++		rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME, GPIO2C_GPIO2C2);/* jacky_test */
++		gpio_request(GPIO_WIFI_IRQ, "oob_irq");
++		gpio_direction_input(GPIO_WIFI_IRQ);
++
++		oob_irq = gpio_to_irq(GPIO_WIFI_IRQ);
++
++		RTW_INFO("%s oob_irq:%d\n", __func__, oob_irq);
++	}
++#endif
++	return 0;
++}
++
++
++int rtw_wifi_gpio_deinit(void)
++{
++#ifdef CONFIG_GSPI_HCI
++	if (GPIO_WIFI_IRQ > 0)
++		gpio_free(GPIO_WIFI_IRQ);
++#endif
++	return 0;
++}
++
++void rtw_wifi_gpio_wlan_ctrl(int onoff)
++{
++}
++
++#ifdef CONFIG_GPIO_API
++/* this is a demo for extending GPIO pin[7] as interrupt mode */
++struct net_device *rtl_net;
++extern int rtw_register_gpio_interrupt(struct net_device *netdev, int gpio_num, void(*callback)(u8 level));
++extern int rtw_disable_gpio_interrupt(struct net_device *netdev, int gpio_num);
++void gpio_int(u8 is_high)
++{
++	RTW_INFO("%s level=%d\n", __func__, is_high);
++}
++int register_net_gpio_init(void)
++{
++	rtl_net = dev_get_by_name(&init_net, "wlan0");
++	if (!rtl_net) {
++		RTW_PRINT("rtl_net init fail!\n");
++		return -1;
++	}
++	return rtw_register_gpio_interrupt(rtl_net, 7, gpio_int);
++}
++int unregister_net_gpio_init(void)
++{
++	rtl_net = dev_get_by_name(&init_net, "wlan0");
++	if (!rtl_net) {
++		RTW_PRINT("rtl_net init fail!\n");
++		return -1;
++	}
++	return rtw_disable_gpio_interrupt(rtl_net, 7);
++}
++#endif
++
++#else
++
++/************************************************/
++/*          ingenic wlan setting                */
++/************************************************/
++
++extern int ingenic_sdio_wlan_power_onoff(int onoff, int flag);
++#define RESET  0
++#define NORMAL 1
++
++static int poweroff_num = 0;
++static int poweron_num = 0;
++
++int rtw_wifi_gpio_init(void)
++{
++	return 0;
++}
++
++void rtw_wifi_gpio_wlan_ctrl(int onoff)
++{
++	switch (onoff) {
++	case 0:
++		if(poweroff_num){
++			printk(("=========== WLAN placed in RESET OFF========\n"));
++			ingenic_sdio_wlan_power_onoff(onoff, RESET);
++		}else{
++			printk(("=========== WLAN placed in NOMAL OFF ========\n"));
++			poweroff_num = 1;
++			ingenic_sdio_wlan_power_onoff(onoff, NORMAL);
++		}
++		mdelay(100);
++		break;
++	case 1:
++		if(poweron_num){
++			printk(("=========== WLAN placed in RESET ON  ========\n"));
++			ingenic_sdio_wlan_power_onoff(onoff, RESET);
++		}else{
++			printk(("=========== WLAN placed in NOMAL ON========\n"));
++			poweron_num = 1;
++			ingenic_sdio_wlan_power_onoff(onoff, NORMAL);
++		}
++		break;
++	}
++	return 0;
++}
++
++
++#endif /* CONFIG_PLATFORM_SPRD */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/ioctl_cfg80211.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/ioctl_cfg80211.c
+new file mode 100755
+index 000000000..a80504159
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/ioctl_cfg80211.c
+@@ -0,0 +1,10775 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define  _IOCTL_CFG80211_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++#ifdef CONFIG_IOCTL_CFG80211
++
++#ifndef DBG_RTW_CFG80211_STA_PARAM
++#define DBG_RTW_CFG80211_STA_PARAM 0
++#endif
++
++#ifndef DBG_RTW_CFG80211_MESH_CONF
++#define DBG_RTW_CFG80211_MESH_CONF 0
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
++#define STATION_INFO_INACTIVE_TIME	BIT(NL80211_STA_INFO_INACTIVE_TIME)
++#define STATION_INFO_LLID			BIT(NL80211_STA_INFO_LLID)
++#define STATION_INFO_PLID			BIT(NL80211_STA_INFO_PLID)
++#define STATION_INFO_PLINK_STATE	BIT(NL80211_STA_INFO_PLINK_STATE)
++#define STATION_INFO_SIGNAL			BIT(NL80211_STA_INFO_SIGNAL)
++#define STATION_INFO_TX_BITRATE		BIT(NL80211_STA_INFO_TX_BITRATE)
++#define STATION_INFO_RX_PACKETS		BIT(NL80211_STA_INFO_RX_PACKETS)
++#define STATION_INFO_TX_PACKETS		BIT(NL80211_STA_INFO_TX_PACKETS)
++#define STATION_INFO_TX_FAILED		BIT(NL80211_STA_INFO_TX_FAILED)
++#define STATION_INFO_LOCAL_PM		BIT(NL80211_STA_INFO_LOCAL_PM)
++#define STATION_INFO_PEER_PM		BIT(NL80211_STA_INFO_PEER_PM)
++#define STATION_INFO_NONPEER_PM		BIT(NL80211_STA_INFO_NONPEER_PM)
++#define STATION_INFO_ASSOC_REQ_IES	0
++#endif /* Linux kernel >= 4.0.0 */
++
++#define RTW_MAX_MGMT_TX_CNT (8)
++#define RTW_MAX_MGMT_TX_MS_GAS (500)
++
++#define RTW_SCAN_IE_LEN_MAX      2304
++#define RTW_MAX_REMAIN_ON_CHANNEL_DURATION 5000 /* ms */
++#define RTW_MAX_NUM_PMKIDS 4
++
++#define RTW_CH_MAX_2G_CHANNEL               14      /* Max channel in 2G band */
++
++#ifdef CONFIG_WAPI_SUPPORT
++
++#ifndef WLAN_CIPHER_SUITE_SMS4
++#define WLAN_CIPHER_SUITE_SMS4          0x00147201
++#endif
++
++#ifndef WLAN_AKM_SUITE_WAPI_PSK
++#define WLAN_AKM_SUITE_WAPI_PSK         0x000FAC04
++#endif
++
++#ifndef WLAN_AKM_SUITE_WAPI_CERT
++#define WLAN_AKM_SUITE_WAPI_CERT        0x000FAC12
++#endif
++
++#ifndef NL80211_WAPI_VERSION_1
++#define NL80211_WAPI_VERSION_1          (1 << 2)
++#endif
++
++#endif /* CONFIG_WAPI_SUPPORT */
++
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 11, 12))
++#ifdef CONFIG_RTW_80211R
++#define WLAN_AKM_SUITE_FT_8021X		0x000FAC03
++#define WLAN_AKM_SUITE_FT_PSK			0x000FAC04
++#endif
++#endif
++
++#define WIFI_CIPHER_SUITE_GCMP		0x000FAC08
++#define WIFI_CIPHER_SUITE_GCMP_256	0x000FAC09
++#define WIFI_CIPHER_SUITE_CCMP_256	0x000FAC0A
++#define WIFI_CIPHER_SUITE_BIP_GMAC_128	0x000FAC0B
++#define WIFI_CIPHER_SUITE_BIP_GMAC_256	0x000FAC0C
++#define WIFI_CIPHER_SUITE_BIP_CMAC_256	0x000FAC0D
++
++/*
++ * If customer need, defining this flag will make driver 
++ * always return -EBUSY at the condition of scan deny.
++ */
++/* #define CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY */
++
++static const u32 rtw_cipher_suites[] = {
++	WLAN_CIPHER_SUITE_WEP40,
++	WLAN_CIPHER_SUITE_WEP104,
++	WLAN_CIPHER_SUITE_TKIP,
++	WLAN_CIPHER_SUITE_CCMP,
++#ifdef CONFIG_WAPI_SUPPORT
++	WLAN_CIPHER_SUITE_SMS4,
++#endif /* CONFIG_WAPI_SUPPORT */
++#ifdef CONFIG_IEEE80211W
++	WLAN_CIPHER_SUITE_AES_CMAC,
++	WIFI_CIPHER_SUITE_GCMP,
++	WIFI_CIPHER_SUITE_GCMP_256,
++	WIFI_CIPHER_SUITE_CCMP_256,
++	WIFI_CIPHER_SUITE_BIP_GMAC_128,
++	WIFI_CIPHER_SUITE_BIP_GMAC_256,
++	WIFI_CIPHER_SUITE_BIP_CMAC_256,
++#endif /* CONFIG_IEEE80211W */
++};
++
++#define RATETAB_ENT(_rate, _rateid, _flags) \
++	{								\
++		.bitrate	= (_rate),				\
++		.hw_value	= (_rateid),				\
++		.flags		= (_flags),				\
++	}
++
++#define CHAN2G(_channel, _freq, _flags) {			\
++		.band			= NL80211_BAND_2GHZ,		\
++		.center_freq		= (_freq),			\
++		.hw_value		= (_channel),			\
++		.flags			= (_flags),			\
++		.max_antenna_gain	= 0,				\
++		.max_power		= 30,				\
++	}
++
++#define CHAN5G(_channel, _flags) {				\
++		.band			= NL80211_BAND_5GHZ,		\
++		.center_freq		= 5000 + (5 * (_channel)),	\
++		.hw_value		= (_channel),			\
++		.flags			= (_flags),			\
++		.max_antenna_gain	= 0,				\
++		.max_power		= 30,				\
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++/* if wowlan is not supported, kernel generate a disconnect at each suspend
++ * cf: /net/wireless/sysfs.c, so register a stub wowlan.
++ * Moreover wowlan has to be enabled via a the nl80211_set_wowlan callback.
++ * (from user space, e.g. iw phy0 wowlan enable)
++ */
++static const struct wiphy_wowlan_support wowlan_stub = {
++	.flags = WIPHY_WOWLAN_ANY,
++	.n_patterns = 0,
++	.pattern_max_len = 0,
++	.pattern_min_len = 0,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
++	.max_pkt_offset = 0,
++#endif
++};
++#endif
++
++static struct ieee80211_rate rtw_rates[] = {
++	RATETAB_ENT(10,  0x1,   0),
++	RATETAB_ENT(20,  0x2,   0),
++	RATETAB_ENT(55,  0x4,   0),
++	RATETAB_ENT(110, 0x8,   0),
++	RATETAB_ENT(60,  0x10,  0),
++	RATETAB_ENT(90,  0x20,  0),
++	RATETAB_ENT(120, 0x40,  0),
++	RATETAB_ENT(180, 0x80,  0),
++	RATETAB_ENT(240, 0x100, 0),
++	RATETAB_ENT(360, 0x200, 0),
++	RATETAB_ENT(480, 0x400, 0),
++	RATETAB_ENT(540, 0x800, 0),
++};
++
++#define rtw_a_rates		(rtw_rates + 4)
++#define RTW_A_RATES_NUM	8
++#define rtw_g_rates		(rtw_rates + 0)
++#define RTW_G_RATES_NUM	12
++
++/* from center_ch_2g */
++static struct ieee80211_channel rtw_2ghz_channels[MAX_CHANNEL_NUM_2G] = {
++	CHAN2G(1, 2412, 0),
++	CHAN2G(2, 2417, 0),
++	CHAN2G(3, 2422, 0),
++	CHAN2G(4, 2427, 0),
++	CHAN2G(5, 2432, 0),
++	CHAN2G(6, 2437, 0),
++	CHAN2G(7, 2442, 0),
++	CHAN2G(8, 2447, 0),
++	CHAN2G(9, 2452, 0),
++	CHAN2G(10, 2457, 0),
++	CHAN2G(11, 2462, 0),
++	CHAN2G(12, 2467, 0),
++	CHAN2G(13, 2472, 0),
++	CHAN2G(14, 2484, 0),
++};
++
++/* from center_ch_5g_20m */
++static struct ieee80211_channel rtw_5ghz_a_channels[MAX_CHANNEL_NUM_5G] = {
++	CHAN5G(36, 0),	CHAN5G(40, 0),	CHAN5G(44, 0),	CHAN5G(48, 0),
++
++	CHAN5G(52, 0),	CHAN5G(56, 0),	CHAN5G(60, 0),	CHAN5G(64, 0),
++
++	CHAN5G(100, 0),	CHAN5G(104, 0),	CHAN5G(108, 0),	CHAN5G(112, 0),
++	CHAN5G(116, 0),	CHAN5G(120, 0),	CHAN5G(124, 0),	CHAN5G(128, 0),
++	CHAN5G(132, 0),	CHAN5G(136, 0),	CHAN5G(140, 0),	CHAN5G(144, 0),
++
++	CHAN5G(149, 0),	CHAN5G(153, 0),	CHAN5G(157, 0),	CHAN5G(161, 0),
++	CHAN5G(165, 0),	CHAN5G(169, 0),	CHAN5G(173, 0),	CHAN5G(177, 0),
++};
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++static u8 rtw_chbw_to_cfg80211_chan_def(struct wiphy *wiphy, struct cfg80211_chan_def *chdef, u8 ch, u8 bw, u8 offset, u8 ht)
++{
++	int freq, cfreq;
++	struct ieee80211_channel *chan;
++	u8 ret = _FAIL;
++
++	freq = rtw_ch2freq(ch);
++	if (!freq)
++		goto exit;
++
++	cfreq = rtw_get_center_ch(ch, bw, offset);
++	if (!cfreq)
++		goto exit;
++	cfreq = rtw_ch2freq(cfreq);
++	if (!cfreq)
++		goto exit;
++
++	chan = ieee80211_get_channel(wiphy, freq);
++	if (!chan)
++		goto exit;
++
++	if (bw == CHANNEL_WIDTH_20) 
++		chdef->width = ht ? NL80211_CHAN_WIDTH_20 : NL80211_CHAN_WIDTH_20_NOHT;
++	else if (bw == CHANNEL_WIDTH_40)
++		chdef->width = NL80211_CHAN_WIDTH_40;
++	else if (bw == CHANNEL_WIDTH_80)
++		chdef->width = NL80211_CHAN_WIDTH_80;
++	else if (bw == CHANNEL_WIDTH_160)
++		chdef->width = NL80211_CHAN_WIDTH_160;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++	else if (bw == CHANNEL_WIDTH_5)
++		chdef->width = NL80211_CHAN_WIDTH_5;
++	else if (bw == CHANNEL_WIDTH_10)
++		chdef->width = NL80211_CHAN_WIDTH_10;
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) */
++	else {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	chdef->chan = chan;
++	chdef->center_freq1 = cfreq;
++	chdef->center_freq2 = 0;
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++
++#ifdef CONFIG_RTW_MESH
++static const char *nl80211_chan_width_str(enum nl80211_chan_width cwidth)
++{
++	switch (cwidth) {
++	case NL80211_CHAN_WIDTH_20_NOHT:
++		return "20_NOHT";
++	case NL80211_CHAN_WIDTH_20:
++		return "20";
++	case NL80211_CHAN_WIDTH_40:
++		return "40";
++	case NL80211_CHAN_WIDTH_80:
++		return "80";
++	case NL80211_CHAN_WIDTH_80P80:
++		return "80+80";
++	case NL80211_CHAN_WIDTH_160:
++		return "160";
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++	case NL80211_CHAN_WIDTH_5:
++		return "5";
++	case NL80211_CHAN_WIDTH_10:
++		return "10";
++#endif
++	default:
++		return "INVALID";
++	};
++}
++
++static void rtw_get_chbw_from_cfg80211_chan_def(struct cfg80211_chan_def *chdef, u8 *ht, u8 *ch, u8 *bw, u8 *offset)
++{
++	int pri_freq;
++	struct ieee80211_channel *chan = chdef->chan;
++
++	pri_freq = rtw_ch2freq(chan->hw_value);
++	if (!pri_freq) {
++		RTW_INFO("invalid channel:%d\n", chan->hw_value);
++		rtw_warn_on(1);
++		*ch = 0;
++		return;
++	}		
++
++	switch (chdef->width) {
++	case NL80211_CHAN_WIDTH_20_NOHT:
++		*ht = 0;
++		*bw = CHANNEL_WIDTH_20;
++		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		*ch = chan->hw_value;
++		break;
++	case NL80211_CHAN_WIDTH_20:
++		*ht = 1;
++		*bw = CHANNEL_WIDTH_20;
++		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		*ch = chan->hw_value;
++		break;
++	case NL80211_CHAN_WIDTH_40:
++		*ht = 1;
++		*bw = CHANNEL_WIDTH_40;
++		*offset = pri_freq > chdef->center_freq1 ? HAL_PRIME_CHNL_OFFSET_UPPER : HAL_PRIME_CHNL_OFFSET_LOWER;
++		if (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset))
++			*ch = chan->hw_value;
++		break;
++	case NL80211_CHAN_WIDTH_80:
++		*ht = 1;
++		*bw = CHANNEL_WIDTH_80;
++		if (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset))
++			*ch = chan->hw_value;
++		break;
++	case NL80211_CHAN_WIDTH_160:
++		*ht = 1;
++		*bw = CHANNEL_WIDTH_160;
++		if (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset))
++			*ch = chan->hw_value;
++		break;
++	case NL80211_CHAN_WIDTH_80P80:
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++	case NL80211_CHAN_WIDTH_5:
++	case NL80211_CHAN_WIDTH_10:
++	#endif
++	default:
++		*ht = 0;
++		*bw = CHANNEL_WIDTH_20;
++		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		RTW_INFO("unsupported cwidth:%s\n", nl80211_chan_width_str(chdef->width));
++		rtw_warn_on(1);
++	};
++}
++#endif /* CONFIG_RTW_MESH */
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
++static const char *nl80211_channel_type_str(enum nl80211_channel_type ctype)
++{
++	switch (ctype) {
++	case NL80211_CHAN_NO_HT:
++		return "NO_HT";
++	case NL80211_CHAN_HT20:
++		return "HT20";
++	case NL80211_CHAN_HT40MINUS:
++		return "HT40-";
++	case NL80211_CHAN_HT40PLUS:
++		return "HT40+";
++	default:
++		return "INVALID";
++	};
++}
++
++static enum nl80211_channel_type rtw_chbw_to_nl80211_channel_type(u8 ch, u8 bw, u8 offset, u8 ht)
++{
++	rtw_warn_on(!ht && (bw >= CHANNEL_WIDTH_40 || offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE));
++
++	if (!ht)
++		return NL80211_CHAN_NO_HT;
++	if (bw >= CHANNEL_WIDTH_40) {
++		if (offset == HAL_PRIME_CHNL_OFFSET_UPPER)
++			return NL80211_CHAN_HT40MINUS;
++		else if (offset == HAL_PRIME_CHNL_OFFSET_LOWER)
++			return NL80211_CHAN_HT40PLUS;
++		else
++			rtw_warn_on(1);
++	}
++	return NL80211_CHAN_HT20;
++}
++
++static void rtw_get_chbw_from_nl80211_channel_type(struct ieee80211_channel *chan, enum nl80211_channel_type ctype, u8 *ht, u8 *ch, u8 *bw, u8 *offset)
++{
++	int pri_freq;
++
++	pri_freq = rtw_ch2freq(chan->hw_value);
++	if (!pri_freq) {
++		RTW_INFO("invalid channel:%d\n", chan->hw_value);
++		rtw_warn_on(1);
++		*ch = 0;
++		return;
++	}
++	*ch = chan->hw_value;
++
++	switch (ctype) {
++	case NL80211_CHAN_NO_HT:
++		*ht = 0;
++		*bw = CHANNEL_WIDTH_20;
++		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		break;
++	case NL80211_CHAN_HT20:
++		*ht = 1;
++		*bw = CHANNEL_WIDTH_20;
++		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		break;
++	case NL80211_CHAN_HT40MINUS:
++		*ht = 1;
++		*bw = CHANNEL_WIDTH_40;
++		*offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++		break;
++	case NL80211_CHAN_HT40PLUS:
++		*ht = 1;
++		*bw = CHANNEL_WIDTH_40;
++		*offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++		break;
++	default:
++		*ht = 0;
++		*bw = CHANNEL_WIDTH_20;
++		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		RTW_INFO("unsupported ctype:%s\n", nl80211_channel_type_str(ctype));
++		rtw_warn_on(1);
++	};
++}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++bool rtw_cfg80211_allow_ch_switch_notify(_adapter *adapter)
++{
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0))
++	if ((!MLME_IS_AP(adapter))
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0))
++		&& (!MLME_IS_ADHOC(adapter))
++		&& (!MLME_IS_ADHOC_MASTER(adapter))
++		&& (!MLME_IS_MESH(adapter))
++#elif defined(CONFIG_RTW_MESH)
++		&& (!MLME_IS_MESH(adapter))
++#endif
++		)
++		return 0;
++#endif
++	return 1;
++}
++
++u8 rtw_cfg80211_ch_switch_notify(_adapter *adapter, u8 ch, u8 bw, u8 offset,
++	u8 ht, bool started)
++{
++	struct wiphy *wiphy = adapter_to_wiphy(adapter);
++	u8 ret = _SUCCESS;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	struct cfg80211_chan_def chdef;
++
++	ret = rtw_chbw_to_cfg80211_chan_def(wiphy, &chdef, ch, bw, offset, ht);
++	if (ret != _SUCCESS)
++		goto exit;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++	if (started) {
++		cfg80211_ch_switch_started_notify(adapter->pnetdev, &chdef, 0);
++		goto exit;
++	}
++#endif
++
++	if (!rtw_cfg80211_allow_ch_switch_notify(adapter))
++		goto exit;
++
++	cfg80211_ch_switch_notify(adapter->pnetdev, &chdef);
++
++#else
++	int freq = rtw_ch2freq(ch);
++	enum nl80211_channel_type ctype;
++
++	if (!rtw_cfg80211_allow_ch_switch_notify(adapter))
++		goto exit;
++
++	if (!freq) {
++		ret = _FAIL;
++		goto exit;
++	}
++
++	ctype = rtw_chbw_to_nl80211_channel_type(ch, bw, offset, ht);
++	cfg80211_ch_switch_notify(adapter->pnetdev, freq, ctype);
++#endif
++
++exit:
++	return ret;
++}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) */
++
++void rtw_2g_channels_init(struct ieee80211_channel *channels)
++{
++	_rtw_memcpy((void *)channels, (void *)rtw_2ghz_channels, sizeof(rtw_2ghz_channels));
++}
++
++void rtw_5g_channels_init(struct ieee80211_channel *channels)
++{
++	_rtw_memcpy((void *)channels, (void *)rtw_5ghz_a_channels, sizeof(rtw_5ghz_a_channels));
++}
++
++void rtw_2g_rates_init(struct ieee80211_rate *rates)
++{
++	_rtw_memcpy(rates, rtw_g_rates,
++		sizeof(struct ieee80211_rate) * RTW_G_RATES_NUM
++	);
++}
++
++void rtw_5g_rates_init(struct ieee80211_rate *rates)
++{
++	_rtw_memcpy(rates, rtw_a_rates,
++		sizeof(struct ieee80211_rate) * RTW_A_RATES_NUM
++	);
++}
++
++struct ieee80211_supported_band *rtw_spt_band_alloc(BAND_TYPE band)
++{
++	struct ieee80211_supported_band *spt_band = NULL;
++	int n_channels, n_bitrates;
++
++	if (band == BAND_ON_2_4G) {
++		n_channels = MAX_CHANNEL_NUM_2G;
++		n_bitrates = RTW_G_RATES_NUM;
++	} else if (band == BAND_ON_5G) {
++		n_channels = MAX_CHANNEL_NUM_5G;
++		n_bitrates = RTW_A_RATES_NUM;
++	} else
++		goto exit;
++
++	spt_band = (struct ieee80211_supported_band *)rtw_zmalloc(
++		sizeof(struct ieee80211_supported_band)
++		+ sizeof(struct ieee80211_channel) * n_channels
++		+ sizeof(struct ieee80211_rate) * n_bitrates
++	);
++	if (!spt_band)
++		goto exit;
++
++	spt_band->channels = (struct ieee80211_channel *)(((u8 *)spt_band) + sizeof(struct ieee80211_supported_band));
++	spt_band->bitrates = (struct ieee80211_rate *)(((u8 *)spt_band->channels) + sizeof(struct ieee80211_channel) * n_channels);
++	spt_band->band = rtw_band_to_nl80211_band(band);
++	spt_band->n_channels = n_channels;
++	spt_band->n_bitrates = n_bitrates;
++
++	if (band == BAND_ON_2_4G) {
++		rtw_2g_channels_init(spt_band->channels);
++		rtw_2g_rates_init(spt_band->bitrates);
++	} else if (band == BAND_ON_5G) {
++		rtw_5g_channels_init(spt_band->channels);
++		rtw_5g_rates_init(spt_band->bitrates);
++	}
++
++	/* spt_band.ht_cap */
++
++exit:
++
++	return spt_band;
++}
++
++void rtw_spt_band_free(struct ieee80211_supported_band *spt_band)
++{
++	u32 size = 0;
++
++	if (!spt_band)
++		return;
++
++	if (spt_band->band == NL80211_BAND_2GHZ) {
++		size = sizeof(struct ieee80211_supported_band)
++			+ sizeof(struct ieee80211_channel) * MAX_CHANNEL_NUM_2G
++			+ sizeof(struct ieee80211_rate) * RTW_G_RATES_NUM;
++	} else if (spt_band->band == NL80211_BAND_5GHZ) {
++		size = sizeof(struct ieee80211_supported_band)
++			+ sizeof(struct ieee80211_channel) * MAX_CHANNEL_NUM_5G
++			+ sizeof(struct ieee80211_rate) * RTW_A_RATES_NUM;
++	} else {
++
++	}
++	rtw_mfree((u8 *)spt_band, size);
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++static const struct ieee80211_txrx_stypes
++	rtw_cfg80211_default_mgmt_stypes[NUM_NL80211_IFTYPES] = {
++	[NL80211_IFTYPE_ADHOC] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ACTION >> 4)
++	},
++	[NL80211_IFTYPE_STATION] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
++		BIT(IEEE80211_STYPE_AUTH >> 4) |
++		BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
++	},
++	[NL80211_IFTYPE_AP] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
++		BIT(IEEE80211_STYPE_DISASSOC >> 4) |
++		BIT(IEEE80211_STYPE_AUTH >> 4) |
++		BIT(IEEE80211_STYPE_DEAUTH >> 4) |
++		BIT(IEEE80211_STYPE_ACTION >> 4)
++	},
++	[NL80211_IFTYPE_AP_VLAN] = {
++		/* copy AP */
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
++		BIT(IEEE80211_STYPE_DISASSOC >> 4) |
++		BIT(IEEE80211_STYPE_AUTH >> 4) |
++		BIT(IEEE80211_STYPE_DEAUTH >> 4) |
++		BIT(IEEE80211_STYPE_ACTION >> 4)
++	},
++	[NL80211_IFTYPE_P2P_CLIENT] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
++		BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
++	},
++	[NL80211_IFTYPE_P2P_GO] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
++		BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
++		BIT(IEEE80211_STYPE_DISASSOC >> 4) |
++		BIT(IEEE80211_STYPE_AUTH >> 4) |
++		BIT(IEEE80211_STYPE_DEAUTH >> 4) |
++		BIT(IEEE80211_STYPE_ACTION >> 4)
++	},
++#if defined(RTW_DEDICATED_P2P_DEVICE)
++	[NL80211_IFTYPE_P2P_DEVICE] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
++			BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
++	},
++#endif
++#if defined(CONFIG_RTW_MESH)
++	[NL80211_IFTYPE_MESH_POINT] = {
++		.tx = 0xffff,
++		.rx = BIT(IEEE80211_STYPE_ACTION >> 4)
++			| BIT(IEEE80211_STYPE_AUTH >> 4)
++	},
++#endif
++
++};
++#endif
++
++NDIS_802_11_NETWORK_INFRASTRUCTURE nl80211_iftype_to_rtw_network_type(enum nl80211_iftype type)
++{
++	switch (type) {
++	case NL80211_IFTYPE_ADHOC:
++		return Ndis802_11IBSS;
++
++	#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
++	case NL80211_IFTYPE_P2P_CLIENT:
++	#endif
++	case NL80211_IFTYPE_STATION:
++		return Ndis802_11Infrastructure;
++
++#ifdef CONFIG_AP_MODE
++	#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
++	case NL80211_IFTYPE_P2P_GO:
++	#endif
++	case NL80211_IFTYPE_AP:
++		return Ndis802_11APMode;
++#endif
++
++#ifdef CONFIG_RTW_MESH
++	case NL80211_IFTYPE_MESH_POINT:
++		return Ndis802_11_mesh;
++#endif
++
++#ifdef CONFIG_WIFI_MONITOR
++	case NL80211_IFTYPE_MONITOR:
++		return Ndis802_11Monitor;
++#endif /* CONFIG_WIFI_MONITOR */
++
++	default:
++		return Ndis802_11InfrastructureMax;
++	}
++}
++
++u32 nl80211_iftype_to_rtw_mlme_state(enum nl80211_iftype type)
++{
++	switch (type) {
++	case NL80211_IFTYPE_ADHOC:
++		return WIFI_ADHOC_STATE;
++
++	#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
++	case NL80211_IFTYPE_P2P_CLIENT:
++	#endif
++	case NL80211_IFTYPE_STATION:
++		return WIFI_STATION_STATE;
++
++#ifdef CONFIG_AP_MODE
++	#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
++	case NL80211_IFTYPE_P2P_GO:
++	#endif
++	case NL80211_IFTYPE_AP:
++		return WIFI_AP_STATE;
++#endif
++
++#ifdef CONFIG_RTW_MESH
++	case NL80211_IFTYPE_MESH_POINT:
++		return WIFI_MESH_STATE;
++#endif
++
++	case NL80211_IFTYPE_MONITOR:
++		return WIFI_MONITOR_STATE;
++
++	default:
++		return WIFI_NULL_STATE;
++	}
++}
++
++static int rtw_cfg80211_sync_iftype(_adapter *adapter)
++{
++	struct wireless_dev *rtw_wdev = adapter->rtw_wdev;
++
++	if (!(nl80211_iftype_to_rtw_mlme_state(rtw_wdev->iftype) & MLME_STATE(adapter))) {
++		/* iftype and mlme state is not syc */
++		NDIS_802_11_NETWORK_INFRASTRUCTURE network_type;
++
++		network_type = nl80211_iftype_to_rtw_network_type(rtw_wdev->iftype);
++		if (network_type != Ndis802_11InfrastructureMax) {
++			if (rtw_pwr_wakeup(adapter) == _FAIL) {
++				RTW_WARN(FUNC_ADPT_FMT" call rtw_pwr_wakeup fail\n", FUNC_ADPT_ARG(adapter));
++				return _FAIL;
++			}
++
++			rtw_set_802_11_infrastructure_mode(adapter, network_type, 0);
++			rtw_setopmode_cmd(adapter, network_type, RTW_CMDF_WAIT_ACK);
++		} else {
++			rtw_warn_on(1);
++			RTW_WARN(FUNC_ADPT_FMT" iftype:%u is not support\n", FUNC_ADPT_ARG(adapter), rtw_wdev->iftype);
++			return _FAIL;
++		}
++	}
++
++	return _SUCCESS;
++}
++
++static u64 rtw_get_systime_us(void)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0))
++	return ktime_to_us(ktime_get_boottime());
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39))
++	struct timespec ts;
++	get_monotonic_boottime(&ts);
++	return ((u64)ts.tv_sec * 1000000) + ts.tv_nsec / 1000;
++#else
++	struct timeval tv;
++	do_gettimeofday(&tv);
++	return ((u64)tv.tv_sec * 1000000) + tv.tv_usec;
++#endif
++}
++
++/* Try to remove non target BSS's SR to reduce PBC overlap rate */
++static int rtw_cfg80211_clear_wps_sr_of_non_target_bss(_adapter *padapter, struct wlan_network *pnetwork, struct cfg80211_ssid *req_ssid)
++{
++	int ret = 0;
++	u8 *psr = NULL, sr = 0;
++	NDIS_802_11_SSID *pssid = &pnetwork->network.Ssid;
++	u32 wpsielen = 0;
++	u8 *wpsie = NULL;
++
++	if (pssid->SsidLength == req_ssid->ssid_len
++		&& _rtw_memcmp(pssid->Ssid, req_ssid->ssid, req_ssid->ssid_len) == _TRUE)
++		goto exit;
++
++	wpsie = rtw_get_wps_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_
++		, pnetwork->network.IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen);
++	if (wpsie && wpsielen > 0)
++		psr = rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_SELECTED_REGISTRAR, &sr, NULL);
++
++	if (psr && sr) {
++		if (0)
++			RTW_INFO("clear sr of non target bss:%s("MAC_FMT")\n"
++				, pssid->Ssid, MAC_ARG(pnetwork->network.MacAddress));
++		*psr = 0; /* clear sr */
++		ret = 1;
++	}
++
++exit:
++	return ret;
++}
++
++#define MAX_BSSINFO_LEN 1000
++struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork)
++{
++	struct ieee80211_channel *notify_channel;
++	struct cfg80211_bss *bss = NULL;
++	/* struct ieee80211_supported_band *band;       */
++	u16 channel;
++	u32 freq;
++	u64 notify_timestamp;
++	u16 notify_capability;
++	u16 notify_interval;
++	u8 *notify_ie;
++	size_t notify_ielen;
++	s32 notify_signal;
++	/* u8 buf[MAX_BSSINFO_LEN]; */
++
++	u8 *pbuf;
++	size_t buf_size = MAX_BSSINFO_LEN;
++	size_t len, bssinf_len = 0;
++	struct rtw_ieee80211_hdr *pwlanhdr;
++	unsigned short *fctrl;
++	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++
++	struct wireless_dev *wdev = padapter->rtw_wdev;
++	struct wiphy *wiphy = wdev->wiphy;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++	pbuf = rtw_zmalloc(buf_size);
++	if (pbuf == NULL) {
++		RTW_INFO("%s pbuf allocate failed  !!\n", __FUNCTION__);
++		return bss;
++	}
++
++	/* RTW_INFO("%s\n", __func__); */
++
++	bssinf_len = pnetwork->network.IELength + sizeof(struct rtw_ieee80211_hdr_3addr);
++	if (bssinf_len > buf_size) {
++		RTW_INFO("%s IE Length too long > %zu byte\n", __FUNCTION__, buf_size);
++		goto exit;
++	}
++
++#ifndef CONFIG_WAPI_SUPPORT
++	{
++		u16 wapi_len = 0;
++
++		if (rtw_get_wapi_ie(pnetwork->network.IEs, pnetwork->network.IELength, NULL, &wapi_len) > 0) {
++			if (wapi_len > 0) {
++				RTW_INFO("%s, no support wapi!\n", __FUNCTION__);
++				goto exit;
++			}
++		}
++	}
++#endif /* !CONFIG_WAPI_SUPPORT */
++
++	channel = pnetwork->network.Configuration.DSConfig;
++	freq = rtw_ch2freq(channel);
++	notify_channel = ieee80211_get_channel(wiphy, freq);
++
++	if (0)
++		notify_timestamp = le64_to_cpu(*(u64 *)rtw_get_timestampe_from_ie(pnetwork->network.IEs));
++	else
++		notify_timestamp = rtw_get_systime_us();
++
++	notify_interval = le16_to_cpu(*(u16 *)rtw_get_beacon_interval_from_ie(pnetwork->network.IEs));
++	notify_capability = le16_to_cpu(*(u16 *)rtw_get_capability_from_ie(pnetwork->network.IEs));
++
++	notify_ie = pnetwork->network.IEs + _FIXED_IE_LENGTH_;
++	notify_ielen = pnetwork->network.IELength - _FIXED_IE_LENGTH_;
++
++	/* We've set wiphy's signal_type as CFG80211_SIGNAL_TYPE_MBM: signal strength in mBm (100*dBm) */
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE &&
++		is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) {
++		notify_signal = 100 * translate_percentage_to_dbm(padapter->recvpriv.signal_strength); /* dbm */
++	} else {
++		notify_signal = 100 * translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength); /* dbm */
++	}
++
++#if 0
++	RTW_INFO("bssid: "MAC_FMT"\n", MAC_ARG(pnetwork->network.MacAddress));
++	RTW_INFO("Channel: %d(%d)\n", channel, freq);
++	RTW_INFO("Capability: %X\n", notify_capability);
++	RTW_INFO("Beacon interval: %d\n", notify_interval);
++	RTW_INFO("Signal: %d\n", notify_signal);
++	RTW_INFO("notify_timestamp: %llu\n", notify_timestamp);
++#endif
++
++	/* pbuf = buf; */
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pbuf;
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
++	/* pmlmeext->mgnt_seq++; */
++
++	if (pnetwork->network.Reserved[0] == BSS_TYPE_BCN) { /* WIFI_BEACON */
++		_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
++		set_frame_sub_type(pbuf, WIFI_BEACON);
++	} else {
++		_rtw_memcpy(pwlanhdr->addr1, adapter_mac_addr(padapter), ETH_ALEN);
++		set_frame_sub_type(pbuf, WIFI_PROBERSP);
++	}
++
++	_rtw_memcpy(pwlanhdr->addr2, pnetwork->network.MacAddress, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, pnetwork->network.MacAddress, ETH_ALEN);
++
++
++	/* pbuf += sizeof(struct rtw_ieee80211_hdr_3addr); */
++	len = sizeof(struct rtw_ieee80211_hdr_3addr);
++	_rtw_memcpy((pbuf + len), pnetwork->network.IEs, pnetwork->network.IELength);
++	*((u64 *)(pbuf + len)) = cpu_to_le64(notify_timestamp);
++
++	len += pnetwork->network.IELength;
++
++	#if defined(CONFIG_P2P) && 0
++	if(rtw_get_p2p_ie(pnetwork->network.IEs+12, pnetwork->network.IELength-12, NULL, NULL))
++		RTW_INFO("%s, got p2p_ie\n", __func__);
++	#endif
++
++#if 1
++	bss = cfg80211_inform_bss_frame(wiphy, notify_channel, (struct ieee80211_mgmt *)pbuf,
++					len, notify_signal, GFP_ATOMIC);
++#else
++
++	bss = cfg80211_inform_bss(wiphy, notify_channel, (const u8 *)pnetwork->network.MacAddress,
++		notify_timestamp, notify_capability, notify_interval, notify_ie,
++		notify_ielen, notify_signal, GFP_ATOMIC/*GFP_KERNEL*/);
++#endif
++
++	if (unlikely(!bss)) {
++		RTW_INFO(FUNC_ADPT_FMT" bss NULL\n", FUNC_ADPT_ARG(padapter));
++		goto exit;
++	}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 38))
++#ifndef COMPAT_KERNEL_RELEASE
++	/* patch for cfg80211, update beacon ies to information_elements */
++	if (pnetwork->network.Reserved[0] == BSS_TYPE_BCN) { /* WIFI_BEACON */
++
++		if (bss->len_information_elements != bss->len_beacon_ies) {
++			bss->information_elements = bss->beacon_ies;
++			bss->len_information_elements =  bss->len_beacon_ies;
++		}
++	}
++#endif /* COMPAT_KERNEL_RELEASE */
++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 38) */
++
++#if 0
++	{
++		if (bss->information_elements == bss->proberesp_ies) {
++			if (bss->len_information_elements !=  bss->len_proberesp_ies)
++				RTW_INFO("error!, len_information_elements != bss->len_proberesp_ies\n");
++		} else if (bss->len_information_elements <  bss->len_beacon_ies) {
++			bss->information_elements = bss->beacon_ies;
++			bss->len_information_elements =  bss->len_beacon_ies;
++		}
++	}
++#endif
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
++	cfg80211_put_bss(wiphy, bss);
++#else
++	cfg80211_put_bss(bss);
++#endif
++
++exit:
++	if (pbuf)
++		rtw_mfree(pbuf, buf_size);
++	return bss;
++
++}
++
++/*
++	Check the given bss is valid by kernel API cfg80211_get_bss()
++	@padapter : the given adapter
++
++	return _TRUE if bss is valid,  _FALSE for not found.
++*/
++int rtw_cfg80211_check_bss(_adapter *padapter)
++{
++	WLAN_BSSID_EX  *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network);
++	struct cfg80211_bss *bss = NULL;
++	struct ieee80211_channel *notify_channel = NULL;
++	u32 freq;
++
++	if (!(pnetwork) || !(padapter->rtw_wdev))
++		return _FALSE;
++
++	freq = rtw_ch2freq(pnetwork->Configuration.DSConfig);
++	notify_channel = ieee80211_get_channel(padapter->rtw_wdev->wiphy, freq);
++	bss = cfg80211_get_bss(padapter->rtw_wdev->wiphy, notify_channel,
++			pnetwork->MacAddress, pnetwork->Ssid.Ssid,
++			pnetwork->Ssid.SsidLength,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
++			pnetwork->InfrastructureMode == Ndis802_11Infrastructure?IEEE80211_BSS_TYPE_ESS:IEEE80211_BSS_TYPE_IBSS,
++			IEEE80211_PRIVACY(pnetwork->Privacy));
++#else
++			pnetwork->InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS, pnetwork->InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS);
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
++	cfg80211_put_bss(padapter->rtw_wdev->wiphy, bss);
++#else
++	cfg80211_put_bss(bss);
++#endif
++
++	return bss != NULL;
++}
++
++void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter)
++{
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct wlan_network  *cur_network = &(pmlmepriv->cur_network);
++	struct wireless_dev *pwdev = padapter->rtw_wdev;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))
++	struct wiphy *wiphy = pwdev->wiphy;
++	int freq = 2412;
++	struct ieee80211_channel *notify_channel;
++#endif
++
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++	if (pwdev->iftype != NL80211_IFTYPE_ADHOC)
++		return;
++
++	if (!rtw_cfg80211_check_bss(padapter)) {
++		WLAN_BSSID_EX  *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network);
++		struct wlan_network *scanned = pmlmepriv->cur_network_scanned;
++
++		if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) {
++
++			_rtw_memcpy(&cur_network->network, pnetwork, sizeof(WLAN_BSSID_EX));
++			if (cur_network) {
++				if (!rtw_cfg80211_inform_bss(padapter, cur_network))
++					RTW_INFO(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter));
++				else
++					RTW_INFO(FUNC_ADPT_FMT" inform success !!\n", FUNC_ADPT_ARG(padapter));
++			} else {
++				RTW_INFO("cur_network is not exist!!!\n");
++				return ;
++			}
++		} else {
++			if (scanned == NULL)
++				rtw_warn_on(1);
++
++			if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE
++				&& _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE
++			) {
++				if (!rtw_cfg80211_inform_bss(padapter, scanned))
++					RTW_INFO(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter));
++				else {
++					/* RTW_INFO(FUNC_ADPT_FMT" inform success !!\n", FUNC_ADPT_ARG(padapter)); */
++				}
++			} else {
++				RTW_INFO("scanned & pnetwork compare fail\n");
++				rtw_warn_on(1);
++			}
++		}
++
++		if (!rtw_cfg80211_check_bss(padapter))
++			RTW_PRINT(FUNC_ADPT_FMT" BSS not found !!\n", FUNC_ADPT_ARG(padapter));
++	}
++	/* notify cfg80211 that device joined an IBSS */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))
++	freq = rtw_ch2freq(cur_network->network.Configuration.DSConfig);
++	if (1)
++		RTW_INFO("chan: %d, freq: %d\n", cur_network->network.Configuration.DSConfig, freq);
++	notify_channel = ieee80211_get_channel(wiphy, freq);
++	cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, notify_channel, GFP_ATOMIC);
++#else
++	cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, GFP_ATOMIC);
++#endif
++}
++
++void rtw_cfg80211_indicate_connect(_adapter *padapter)
++{
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct wlan_network  *cur_network = &(pmlmepriv->cur_network);
++	struct wireless_dev *pwdev = padapter->rtw_wdev;
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++	_irqL irqL;
++#ifdef CONFIG_P2P
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++#endif
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)
++	struct cfg80211_roam_info roam_info ={};
++#endif
++
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++	if (pwdev->iftype != NL80211_IFTYPE_STATION
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++		&& pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT
++		#endif
++	)
++		return;
++
++	if (!MLME_IS_STA(padapter))
++		return;
++
++#ifdef CONFIG_P2P
++	if (pwdinfo->driver_interface == DRIVER_CFG80211) {
++		#if !RTW_P2P_GROUP_INTERFACE
++		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
++			rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++			rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
++			rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
++			RTW_INFO("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo));
++		}
++		#endif
++	}
++#endif /* CONFIG_P2P */
++
++	if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE) {
++		WLAN_BSSID_EX  *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network);
++		struct wlan_network *scanned = pmlmepriv->cur_network_scanned;
++
++		/* RTW_INFO(FUNC_ADPT_FMT" BSS not found\n", FUNC_ADPT_ARG(padapter)); */
++
++		if (scanned == NULL) {
++			rtw_warn_on(1);
++			goto check_bss;
++		}
++
++		if (_rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE
++			&& _rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE
++		) {
++			if (!rtw_cfg80211_inform_bss(padapter, scanned))
++				RTW_INFO(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter));
++			else {
++				/* RTW_INFO(FUNC_ADPT_FMT" inform success !!\n", FUNC_ADPT_ARG(padapter)); */
++			}
++		} else {
++			RTW_INFO("scanned: %s("MAC_FMT"), cur: %s("MAC_FMT")\n",
++				scanned->network.Ssid.Ssid, MAC_ARG(scanned->network.MacAddress),
++				pnetwork->Ssid.Ssid, MAC_ARG(pnetwork->MacAddress)
++			);
++			rtw_warn_on(1);
++		}
++	}
++
++check_bss:
++	if (!rtw_cfg80211_check_bss(padapter))
++		RTW_PRINT(FUNC_ADPT_FMT" BSS not found !!\n", FUNC_ADPT_ARG(padapter));
++
++	_enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
++
++	if (rtw_to_roam(padapter) > 0) {
++		#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE)
++		struct wiphy *wiphy = pwdev->wiphy;
++		struct ieee80211_channel *notify_channel;
++		u32 freq;
++		u16 channel = cur_network->network.Configuration.DSConfig;
++
++		freq = rtw_ch2freq(channel);
++		notify_channel = ieee80211_get_channel(wiphy, freq);
++		#endif
++
++		#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)
++		roam_info.bssid = cur_network->network.MacAddress;
++		roam_info.req_ie = pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2;
++		roam_info.req_ie_len = pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2;
++		roam_info.resp_ie = pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6;
++		roam_info.resp_ie_len = pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6;
++
++		cfg80211_roamed(padapter->pnetdev, &roam_info, GFP_ATOMIC);
++		#else
++		cfg80211_roamed(padapter->pnetdev
++			#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE)
++			, notify_channel
++			#endif
++			, cur_network->network.MacAddress
++			, pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2
++			, pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2
++			, pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6
++			, pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6
++			, GFP_ATOMIC);
++		#endif /*LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)*/
++
++		RTW_INFO(FUNC_ADPT_FMT" call cfg80211_roamed\n", FUNC_ADPT_ARG(padapter));
++
++#ifdef CONFIG_RTW_80211R
++		if (rtw_ft_roam(padapter))
++			rtw_ft_set_status(padapter, RTW_FT_ASSOCIATED_STA);
++#endif
++	} else {
++		#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE)
++		RTW_INFO("pwdev->sme_state(b)=%d\n", pwdev->sme_state);
++		#endif
++
++		if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE)
++			rtw_cfg80211_connect_result(pwdev, cur_network->network.MacAddress
++				, pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2
++				, pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2
++				, pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6
++				, pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6
++				, WLAN_STATUS_SUCCESS, GFP_ATOMIC);
++		#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE)
++		RTW_INFO("pwdev->sme_state(a)=%d\n", pwdev->sme_state);
++		#endif
++	}
++
++	rtw_wdev_free_connect_req(pwdev_priv);
++
++	_exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
++}
++
++void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated)
++{
++	struct wireless_dev *pwdev = padapter->rtw_wdev;
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++	_irqL irqL;
++#ifdef CONFIG_P2P
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++#endif
++
++	RTW_INFO(FUNC_ADPT_FMT" ,reason = %d\n", FUNC_ADPT_ARG(padapter), reason);
++
++	/*always replace privated definitions with wifi reserved value 0*/
++	if (WLAN_REASON_IS_PRIVATE(reason))
++		reason = 0;
++
++	if (pwdev->iftype != NL80211_IFTYPE_STATION
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++		&& pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT
++		#endif
++	)
++		return;
++
++	if (!MLME_IS_STA(padapter))
++		return;
++
++#ifdef CONFIG_P2P
++	if (pwdinfo->driver_interface == DRIVER_CFG80211) {
++		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
++			rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
++
++			#if RTW_P2P_GROUP_INTERFACE
++			#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++			if (pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT)
++			#endif
++			#endif
++				rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++
++			RTW_INFO("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo));
++		}
++	}
++#endif /* CONFIG_P2P */
++
++	_enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
++
++	if (padapter->ndev_unregistering || !rtw_wdev_not_indic_disco(pwdev_priv)) {
++		#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE)
++		RTW_INFO("pwdev->sme_state(b)=%d\n", pwdev->sme_state);
++
++		if (pwdev->sme_state == CFG80211_SME_CONNECTING) {
++			RTW_INFO(FUNC_ADPT_FMT" call cfg80211_connect_result, reason:%d\n", FUNC_ADPT_ARG(padapter), reason);
++			rtw_cfg80211_connect_result(pwdev, NULL, NULL, 0, NULL, 0,
++				reason?reason:WLAN_STATUS_UNSPECIFIED_FAILURE,
++				GFP_ATOMIC);
++		} else if (pwdev->sme_state == CFG80211_SME_CONNECTED) {
++			RTW_INFO(FUNC_ADPT_FMT" call cfg80211_disconnected, reason:%d\n", FUNC_ADPT_ARG(padapter), reason);
++			rtw_cfg80211_disconnected(pwdev, reason, NULL, 0, locally_generated, GFP_ATOMIC);
++		}
++
++		RTW_INFO("pwdev->sme_state(a)=%d\n", pwdev->sme_state);
++		#else
++		if (pwdev_priv->connect_req) {
++			RTW_INFO(FUNC_ADPT_FMT" call cfg80211_connect_result, reason:%d\n", FUNC_ADPT_ARG(padapter), reason);
++			rtw_cfg80211_connect_result(pwdev, NULL, NULL, 0, NULL, 0,
++				reason?reason:WLAN_STATUS_UNSPECIFIED_FAILURE,
++				GFP_ATOMIC);
++		} else {
++			RTW_INFO(FUNC_ADPT_FMT" call cfg80211_disconnected, reason:%d\n", FUNC_ADPT_ARG(padapter), reason);
++			rtw_cfg80211_disconnected(pwdev, reason, NULL, 0, locally_generated, GFP_ATOMIC);
++		}
++		#endif
++	}
++
++	rtw_wdev_free_connect_req(pwdev_priv);
++
++	_exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
++}
++
++
++#ifdef CONFIG_AP_MODE
++static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_param *param)
++{
++	int ret = 0;
++	u32 wep_key_idx, wep_key_len;
++	struct sta_info *psta = NULL, *pbcmc_sta = NULL;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct security_priv *psecuritypriv = &(padapter->securitypriv);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	param->u.crypt.err = 0;
++	param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0';
++
++	if (is_broadcast_mac_addr(param->sta_addr)) {
++		if (param->u.crypt.idx >= WEP_KEYS
++			#ifdef CONFIG_IEEE80211W
++			&& param->u.crypt.idx > BIP_MAX_KEYID
++			#endif
++		) {
++			ret = -EINVAL;
++			goto exit;
++		}
++	} else {
++		psta = rtw_get_stainfo(pstapriv, param->sta_addr);
++		if (!psta) {
++			ret = -EINVAL;
++			RTW_INFO(FUNC_ADPT_FMT", sta "MAC_FMT" not found\n"
++				, FUNC_ADPT_ARG(padapter), MAC_ARG(param->sta_addr));
++			goto exit;
++		}
++	}
++
++	if (strcmp(param->u.crypt.alg, "none") == 0 && (psta == NULL)) {
++		/* todo:clear default encryption keys */
++
++		RTW_INFO("clear default encryption keys, keyid=%d\n", param->u.crypt.idx);
++
++		goto exit;
++	}
++
++
++	if (strcmp(param->u.crypt.alg, "WEP") == 0 && (psta == NULL)) {
++		RTW_INFO("r871x_set_encryption, crypt.alg = WEP\n");
++
++		wep_key_idx = param->u.crypt.idx;
++		wep_key_len = param->u.crypt.key_len;
++
++		RTW_INFO("r871x_set_encryption, wep_key_idx=%d, len=%d\n", wep_key_idx, wep_key_len);
++
++		if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) {
++			ret = -EINVAL;
++			goto exit;
++		}
++
++		if (wep_key_len > 0)
++			wep_key_len = wep_key_len <= 5 ? 5 : 13;
++
++		if (psecuritypriv->bWepDefaultKeyIdxSet == 0) {
++			/* wep default key has not been set, so use this key index as default key. */
++
++			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
++			psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
++			psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
++			psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
++
++			if (wep_key_len == 13) {
++				psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
++				psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
++			}
++
++			psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;
++		}
++
++		_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len);
++
++		psecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len;
++
++		rtw_ap_set_wep_key(padapter, param->u.crypt.key, wep_key_len, wep_key_idx, 1);
++
++		goto exit;
++
++	}
++
++	if (!psta) { /* group key */
++		if (param->u.crypt.set_tx == 0) { /* group key, TX only */
++			if (strcmp(param->u.crypt.alg, "WEP") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set WEP TX GTK idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++				psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
++				if (param->u.crypt.key_len == 13)
++					psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
++
++			} else if (strcmp(param->u.crypt.alg, "TKIP") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set TKIP TX GTK idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++				psecuritypriv->dot118021XGrpPrivacy = _TKIP_;
++				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++				/* set mic key */
++				_rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);
++				_rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);
++				psecuritypriv->busetkipkey = _TRUE;
++
++			} else if (strcmp(param->u.crypt.alg, "CCMP") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set CCMP TX GTK idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++				psecuritypriv->dot118021XGrpPrivacy = _AES_;
++				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++
++			} else if (strcmp(param->u.crypt.alg, "GCMP") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set GCMP TX GTK idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++				psecuritypriv->dot118021XGrpPrivacy = _GCMP_;
++				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,
++					param->u.crypt.key,
++					(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++
++			} else if (strcmp(param->u.crypt.alg, "GCMP_256") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set GCMP_256 TX GTK idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++				psecuritypriv->dot118021XGrpPrivacy = _GCMP_256_;
++				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,
++					param->u.crypt.key,
++					(param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len));
++
++			} else if (strcmp(param->u.crypt.alg, "CCMP_256") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set CCMP_256 TX GTK idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++				psecuritypriv->dot118021XGrpPrivacy = _CCMP_256_;
++				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,
++					param->u.crypt.key,
++					(param->u.crypt.key_len > 32 ? 32: param->u.crypt.key_len));
++
++			#ifdef CONFIG_IEEE80211W
++			} else if (strcmp(param->u.crypt.alg, "BIP") == 0) {
++				psecuritypriv->dot11wCipher = _BIP_CMAC_128_;
++				RTW_INFO(FUNC_ADPT_FMT" set TX CMAC-128 IGTK idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++				_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++				padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx;
++				psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq);
++				padapter->securitypriv.binstallBIPkey = _TRUE;
++				goto exit;
++			} else if (strcmp(param->u.crypt.alg, "BIP_GMAC_128") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set TX GMAC-128 IGTK idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++				psecuritypriv->dot11wCipher = _BIP_GMAC_128_;
++				_rtw_memcpy(psecuritypriv->dot11wBIPKey[param->u.crypt.idx].skey,
++					param->u.crypt.key, param->u.crypt.key_len);
++				psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
++				psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq);
++				psecuritypriv->binstallBIPkey = _TRUE;
++				goto exit;
++			} else if (strcmp(param->u.crypt.alg, "BIP_GMAC_256") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set TX GMAC-256 IGTK idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++				psecuritypriv->dot11wCipher = _BIP_GMAC_256_;
++				_rtw_memcpy(psecuritypriv->dot11wBIPKey[param->u.crypt.idx].skey,
++					param->u.crypt.key, param->u.crypt.key_len);
++				padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx;
++				psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq);
++				padapter->securitypriv.binstallBIPkey = _TRUE;
++				goto exit;
++			} else if (strcmp(param->u.crypt.alg, "BIP_CMAC_256") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set TX CMAC-256 IGTK idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++				psecuritypriv->dot11wCipher = _BIP_CMAC_256_;
++				_rtw_memcpy(psecuritypriv->dot11wBIPKey[param->u.crypt.idx].skey,
++					param->u.crypt.key, param->u.crypt.key_len);
++				psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
++				psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq);
++				psecuritypriv->binstallBIPkey = _TRUE;
++				goto exit;
++			#endif /* CONFIG_IEEE80211W */
++
++			} else if (strcmp(param->u.crypt.alg, "none") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" clear group key, idx:%u\n"
++					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx);
++				psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
++			} else {
++				RTW_WARN(FUNC_ADPT_FMT" set group key, not support\n"
++					, FUNC_ADPT_ARG(padapter));
++				goto exit;
++			}
++
++			psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx;
++			pbcmc_sta = rtw_get_bcmc_stainfo(padapter);
++			if (pbcmc_sta) {
++				pbcmc_sta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
++				pbcmc_sta->ieee8021x_blocked = _FALSE;
++				pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy			 */
++			}
++			psecuritypriv->binstallGrpkey = _TRUE;
++			psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */
++
++			rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx);
++		}
++
++		goto exit;
++
++	}
++
++	if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) { /* psk/802_1x */
++		if (param->u.crypt.set_tx == 1) {
++			/* pairwise key */
++			if (param->u.crypt.key_len == 32)
++				_rtw_memcpy(psta->dot118021x_UncstKey.skey,
++						param->u.crypt.key,
++						(param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len));
++			else
++				_rtw_memcpy(psta->dot118021x_UncstKey.skey,
++						param->u.crypt.key,
++						(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++
++			if (strcmp(param->u.crypt.alg, "WEP") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set WEP PTK of "MAC_FMT" idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++					, param->u.crypt.idx, param->u.crypt.key_len);
++				psta->dot118021XPrivacy = _WEP40_;
++				if (param->u.crypt.key_len == 13)
++					psta->dot118021XPrivacy = _WEP104_;
++
++			} else if (strcmp(param->u.crypt.alg, "TKIP") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set TKIP PTK of "MAC_FMT" idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++					, param->u.crypt.idx, param->u.crypt.key_len);
++				psta->dot118021XPrivacy = _TKIP_;
++				/* set mic key */
++				_rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);
++				_rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);
++				psecuritypriv->busetkipkey = _TRUE;
++
++			} else if (strcmp(param->u.crypt.alg, "CCMP") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set CCMP PTK of "MAC_FMT" idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++					, param->u.crypt.idx, param->u.crypt.key_len);
++				psta->dot118021XPrivacy = _AES_;
++
++			} else if (strcmp(param->u.crypt.alg, "GCMP") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set GCMP PTK of "MAC_FMT" idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++					, param->u.crypt.idx, param->u.crypt.key_len);
++				psta->dot118021XPrivacy = _GCMP_;
++
++			} else if (strcmp(param->u.crypt.alg, "GCMP_256") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set GCMP_256 PTK of "MAC_FMT" idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++					, param->u.crypt.idx, param->u.crypt.key_len);
++				psta->dot118021XPrivacy = _GCMP_256_;
++
++			} else if (strcmp(param->u.crypt.alg, "CCMP_256") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set CCMP_256 PTK of "MAC_FMT" idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++					, param->u.crypt.idx, param->u.crypt.key_len);
++				psta->dot118021XPrivacy = _CCMP_256_;
++
++			} else if (strcmp(param->u.crypt.alg, "none") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" clear pairwise key of "MAC_FMT" idx:%u\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++					, param->u.crypt.idx);
++				psta->dot118021XPrivacy = _NO_PRIVACY_;
++			} else {
++				RTW_WARN(FUNC_ADPT_FMT" set pairwise key of "MAC_FMT", not support\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
++				goto exit;
++			}
++
++			psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
++			psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq);
++			psta->ieee8021x_blocked = _FALSE;
++
++			if (psta->dot118021XPrivacy != _NO_PRIVACY_) {
++				psta->bpairwise_key_installed = _TRUE;
++
++				/* WPA2 key-handshake has completed */
++				if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK)
++					psta->state &= (~WIFI_UNDER_KEY_HANDSHAKE);
++			}
++
++			rtw_ap_set_pairwise_key(padapter, psta);
++		} else {
++			/* peer's group key, RX only */
++			#ifdef CONFIG_RTW_MESH
++			if (strcmp(param->u.crypt.alg, "CCMP") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set CCMP GTK of "MAC_FMT", idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++					, param->u.crypt.idx, param->u.crypt.key_len);
++				psta->group_privacy = _AES_;
++				_rtw_memcpy(psta->gtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++				psta->gtk_bmp |= BIT(param->u.crypt.idx);
++				psta->gtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
++
++			} else if (strcmp(param->u.crypt.alg, "GCMP") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set GCMP GTK of "MAC_FMT", idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++					, param->u.crypt.idx, param->u.crypt.key_len);
++				psta->group_privacy = _GCMP_;
++				_rtw_memcpy(psta->gtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++				psta->gtk_bmp |= BIT(param->u.crypt.idx);
++				psta->gtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
++
++			} else if (strcmp(param->u.crypt.alg, "CCMP_256") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set CCMP_256 GTK of "MAC_FMT", idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++					, param->u.crypt.idx, param->u.crypt.key_len);
++				psta->group_privacy = _CCMP_256_;
++				_rtw_memcpy(psta->gtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len));
++				psta->gtk_bmp |= BIT(param->u.crypt.idx);
++				psta->gtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
++
++			} else if (strcmp(param->u.crypt.alg, "GCMP_256") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set GCMP_256 GTK of "MAC_FMT", idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++					, param->u.crypt.idx, param->u.crypt.key_len);
++				psta->group_privacy = _GCMP_256_;
++				_rtw_memcpy(psta->gtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len));
++				psta->gtk_bmp |= BIT(param->u.crypt.idx);
++				psta->gtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
++
++			#ifdef CONFIG_IEEE80211W
++			} else if (strcmp(param->u.crypt.alg, "BIP") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set CMAC-128 IGTK of "MAC_FMT", idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++					, param->u.crypt.idx, param->u.crypt.key_len);
++				psta->dot11wCipher = _BIP_CMAC_128_;
++				_rtw_memcpy(psta->igtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++				psta->igtk_bmp |= BIT(param->u.crypt.idx);
++				psta->igtk_id = param->u.crypt.idx;
++				psta->igtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
++				goto exit;
++
++			} else if (strcmp(param->u.crypt.alg, "BIP_GMAC_128") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set GMAC-128 IGTK of "MAC_FMT", idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++					, param->u.crypt.idx, param->u.crypt.key_len);
++				psta->dot11wCipher = _BIP_GMAC_128_;
++				_rtw_memcpy(psta->igtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++				psta->igtk_bmp |= BIT(param->u.crypt.idx);
++				psta->igtk_id = param->u.crypt.idx;
++				psta->igtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
++				goto exit;
++
++			} else if (strcmp(param->u.crypt.alg, "BIP_CMAC_256") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set CMAC-256 IGTK of "MAC_FMT", idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++					, param->u.crypt.idx, param->u.crypt.key_len);
++				psta->dot11wCipher = _BIP_CMAC_256_;
++				_rtw_memcpy(psta->igtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len));
++				psta->igtk_bmp |= BIT(param->u.crypt.idx);
++				psta->igtk_id = param->u.crypt.idx;
++				psta->igtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
++				goto exit;
++
++			} else if (strcmp(param->u.crypt.alg, "BIP_GMAC_256") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set GMAC-256 IGTK of "MAC_FMT", idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++					, param->u.crypt.idx, param->u.crypt.key_len);
++				psta->dot11wCipher = _BIP_GMAC_256_;
++				_rtw_memcpy(psta->igtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len));
++				psta->igtk_bmp |= BIT(param->u.crypt.idx);
++				psta->igtk_id = param->u.crypt.idx;
++				psta->igtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
++				goto exit;
++			#endif /* CONFIG_IEEE80211W */
++
++			} else if (strcmp(param->u.crypt.alg, "none") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" clear group key of "MAC_FMT", idx:%u\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++					, param->u.crypt.idx);
++				psta->group_privacy = _NO_PRIVACY_;
++				psta->gtk_bmp &= ~BIT(param->u.crypt.idx);
++			} else
++			#endif /* CONFIG_RTW_MESH */
++			{
++				RTW_WARN(FUNC_ADPT_FMT" set group key of "MAC_FMT", not support\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
++				goto exit;
++			}
++
++			#ifdef CONFIG_RTW_MESH
++			rtw_ap_set_sta_key(padapter, psta->cmn.mac_addr, psta->group_privacy
++				, param->u.crypt.key, param->u.crypt.idx, 1);
++			#endif
++		}
++
++	}
++
++exit:
++	return ret;
++}
++#endif /* CONFIG_AP_MODE */
++
++static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param *param)
++{
++	int ret = 0;
++	u32 wep_key_idx, wep_key_len;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++#ifdef CONFIG_P2P
++	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++#endif /* CONFIG_P2P */
++
++	RTW_INFO("%s\n", __func__);
++
++	param->u.crypt.err = 0;
++	param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0';
++
++	if (is_broadcast_mac_addr(param->sta_addr)) {
++		if (param->u.crypt.idx >= WEP_KEYS
++			#ifdef CONFIG_IEEE80211W
++			&& param->u.crypt.idx > BIP_MAX_KEYID
++			#endif
++		) {
++			ret = -EINVAL;
++			goto exit;
++		}
++	} else {
++#ifdef CONFIG_WAPI_SUPPORT
++		if (strcmp(param->u.crypt.alg, "SMS4"))
++#endif
++		{
++			ret = -EINVAL;
++			goto exit;
++		}
++	}
++
++	if (strcmp(param->u.crypt.alg, "WEP") == 0) {
++		RTW_INFO("wpa_set_encryption, crypt.alg = WEP\n");
++
++		wep_key_idx = param->u.crypt.idx;
++		wep_key_len = param->u.crypt.key_len;
++
++		if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) {
++			ret = -EINVAL;
++			goto exit;
++		}
++
++		if (psecuritypriv->bWepDefaultKeyIdxSet == 0) {
++			/* wep default key has not been set, so use this key index as default key. */
++
++			wep_key_len = wep_key_len <= 5 ? 5 : 13;
++
++			psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
++			psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
++			psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
++
++			if (wep_key_len == 13) {
++				psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
++				psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
++			}
++
++			psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;
++		}
++
++		_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len);
++
++		psecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len;
++
++		rtw_set_key(padapter, psecuritypriv, wep_key_idx, 0, _TRUE);
++
++		goto exit;
++	}
++
++	if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { /* 802_1x */
++		struct sta_info *psta, *pbcmc_sta;
++		struct sta_priv *pstapriv = &padapter->stapriv;
++
++		/* RTW_INFO("%s, : dot11AuthAlgrthm == dot11AuthAlgrthm_8021X\n", __func__); */
++
++		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) { /* sta mode */
++#ifdef CONFIG_RTW_80211R
++			if (rtw_ft_roam(padapter))
++				psta = rtw_get_stainfo(pstapriv, pmlmepriv->assoc_bssid);
++			else
++#endif
++				psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
++			if (psta == NULL) {
++				/* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */
++				RTW_INFO("%s, : Obtain Sta_info fail\n", __func__);
++			} else {
++				/* Jeff: don't disable ieee8021x_blocked while clearing key */
++				if (strcmp(param->u.crypt.alg, "none") != 0)
++					psta->ieee8021x_blocked = _FALSE;
++
++				if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) ||
++				    (padapter->securitypriv.ndisencryptstatus ==  Ndis802_11Encryption3Enabled))
++					psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
++
++				if (param->u.crypt.set_tx == 1) { /* pairwise key */
++					RTW_INFO(FUNC_ADPT_FMT" set %s PTK idx:%u, len:%u\n"
++						, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);
++
++					if (strcmp(param->u.crypt.alg, "GCMP_256") == 0
++						|| strcmp(param->u.crypt.alg, "CCMP_256") == 0) {
++						_rtw_memcpy(psta->dot118021x_UncstKey.skey,
++							param->u.crypt.key,
++							((param->u.crypt.key_len > 32) ?
++								32 : param->u.crypt.key_len));
++					} else
++						_rtw_memcpy(psta->dot118021x_UncstKey.skey,
++							param->u.crypt.key,
++							(param->u.crypt.key_len > 16 ?
++								16 : param->u.crypt.key_len));
++
++					if (strcmp(param->u.crypt.alg, "TKIP") == 0) { /* set mic key */
++						_rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);
++						_rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);
++						padapter->securitypriv.busetkipkey = _FALSE;
++					}
++					psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
++					psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq);
++					psta->bpairwise_key_installed = _TRUE;
++					#ifdef CONFIG_RTW_80211R
++					psta->ft_pairwise_key_installed = _TRUE;
++					#endif
++					rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _TRUE);
++
++				} else { /* group key */
++					if (strcmp(param->u.crypt.alg, "TKIP") == 0
++						|| strcmp(param->u.crypt.alg, "CCMP") == 0
++						|| strcmp(param->u.crypt.alg, "GCMP") == 0) {
++						RTW_INFO(FUNC_ADPT_FMT" set %s GTK idx:%u, len:%u\n"
++							, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);
++						_rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey,
++							param->u.crypt.key,
++							(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++						_rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);
++						_rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);
++						padapter->securitypriv.binstallGrpkey = _TRUE;
++						if (param->u.crypt.idx < 4) 
++							_rtw_memcpy(padapter->securitypriv.iv_seq[param->u.crypt.idx], param->u.crypt.seq, 8);							
++						padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx;
++						rtw_set_key(padapter, &padapter->securitypriv, param->u.crypt.idx, 1, _TRUE);
++					} else if (strcmp(param->u.crypt.alg, "GCMP_256") == 0
++						|| strcmp(param->u.crypt.alg, "CCMP_256") == 0) {
++						RTW_INFO(FUNC_ADPT_FMT" set %s GTK idx:%u, len:%u\n"
++							, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);
++						_rtw_memcpy(
++							padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey,
++							param->u.crypt.key,
++							(param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len));
++						padapter->securitypriv.binstallGrpkey = _TRUE;
++						padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx;
++						rtw_set_key(padapter, &padapter->securitypriv, param->u.crypt.idx, 1, _TRUE);
++					#ifdef CONFIG_IEEE80211W
++					} else if (strcmp(param->u.crypt.alg, "BIP") == 0) {
++						psecuritypriv->dot11wCipher = _BIP_CMAC_128_;
++						RTW_INFO(FUNC_ADPT_FMT" set CMAC-128 IGTK idx:%u, len:%u\n"
++							, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++						_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey,
++							param->u.crypt.key,
++							(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++						psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
++						psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq);
++						psecuritypriv->binstallBIPkey = _TRUE;
++					} else if (strcmp(param->u.crypt.alg, "BIP_GMAC_128") == 0) {
++						psecuritypriv->dot11wCipher = _BIP_GMAC_128_;
++						RTW_INFO(FUNC_ADPT_FMT" set GMAC-128 IGTK idx:%u, len:%u\n"
++							, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++						_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey,
++							param->u.crypt.key,
++							(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++						psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
++						psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq);
++						psecuritypriv->binstallBIPkey = _TRUE;
++					} else if (strcmp(param->u.crypt.alg, "BIP_GMAC_256") == 0) {
++						psecuritypriv->dot11wCipher = _BIP_GMAC_256_;
++						RTW_INFO(FUNC_ADPT_FMT" set GMAC-256 IGTK idx:%u, len:%u\n"
++							, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++						_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey,
++							param->u.crypt.key,
++							(param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len));
++						psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
++						psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq);
++						psecuritypriv->binstallBIPkey = _TRUE;
++					} else if (strcmp(param->u.crypt.alg, "BIP_CMAC_256") == 0) {
++						psecuritypriv->dot11wCipher = _BIP_CMAC_256_;
++						RTW_INFO(FUNC_ADPT_FMT" set CMAC-256 IGTK idx:%u, len:%u\n"
++							, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++						_rtw_memcpy(psecuritypriv->dot11wBIPKey[param->u.crypt.idx].skey,
++							param->u.crypt.key, param->u.crypt.key_len);
++						psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
++						psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq);
++						psecuritypriv->binstallBIPkey = _TRUE;
++					#endif /* CONFIG_IEEE80211W */
++
++					}
++
++#ifdef CONFIG_P2P
++					if (pwdinfo->driver_interface == DRIVER_CFG80211) {
++						if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))
++							rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE);
++					}
++#endif /* CONFIG_P2P */
++
++					/* WPA/WPA2 key-handshake has completed */
++					clr_fwstate(pmlmepriv, WIFI_UNDER_KEY_HANDSHAKE);
++
++				}
++			}
++
++			pbcmc_sta = rtw_get_bcmc_stainfo(padapter);
++			if (pbcmc_sta == NULL) {
++				/* DEBUG_ERR( ("Set OID_802_11_ADD_KEY: bcmc stainfo is null\n")); */
++			} else {
++				/* Jeff: don't disable ieee8021x_blocked while clearing key */
++				if (strcmp(param->u.crypt.alg, "none") != 0)
++					pbcmc_sta->ieee8021x_blocked = _FALSE;
++
++				if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) ||
++				    (padapter->securitypriv.ndisencryptstatus ==  Ndis802_11Encryption3Enabled))
++					pbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
++			}
++		} else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) { /* adhoc mode */
++		}
++	}
++
++	#ifdef CONFIG_WAPI_SUPPORT
++	if (strcmp(param->u.crypt.alg, "SMS4") == 0)
++		rtw_wapi_set_set_encryption(padapter, param);
++	#endif
++
++exit:
++
++	RTW_INFO("%s, ret=%d\n", __func__, ret);
++
++
++	return ret;
++}
++
++static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev
++	, u8 key_index
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++	, bool pairwise
++#endif
++	, const u8 *mac_addr, struct key_params *params)
++{
++	char *alg_name;
++	u32 param_len;
++	struct ieee_param *param = NULL;
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct wireless_dev *rtw_wdev = padapter->rtw_wdev;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++#ifdef CONFIG_TDLS
++	struct sta_info *ptdls_sta;
++#endif /* CONFIG_TDLS */
++
++	if (mac_addr)
++		RTW_INFO(FUNC_NDEV_FMT" adding key for %pM\n", FUNC_NDEV_ARG(ndev), mac_addr);
++	RTW_INFO(FUNC_NDEV_FMT" cipher=0x%x\n", FUNC_NDEV_ARG(ndev), params->cipher);
++	RTW_INFO(FUNC_NDEV_FMT" key_len=%d, key_index=%d\n", FUNC_NDEV_ARG(ndev), params->key_len, key_index);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++	RTW_INFO(FUNC_NDEV_FMT" pairwise=%d\n", FUNC_NDEV_ARG(ndev), pairwise);
++#endif
++
++	if (rtw_cfg80211_sync_iftype(padapter) != _SUCCESS) {
++		ret = -ENOTSUPP;
++		goto addkey_end;
++	}
++
++	param_len = sizeof(struct ieee_param) + params->key_len;
++	param = rtw_malloc(param_len);
++	if (param == NULL)
++		return -1;
++
++	_rtw_memset(param, 0, param_len);
++
++	param->cmd = IEEE_CMD_SET_ENCRYPTION;
++	_rtw_memset(param->sta_addr, 0xff, ETH_ALEN);
++
++	switch (params->cipher) {
++	case IW_AUTH_CIPHER_NONE:
++		/* todo: remove key */
++		/* remove = 1;	 */
++		alg_name = "none";
++		break;
++	case WLAN_CIPHER_SUITE_WEP40:
++	case WLAN_CIPHER_SUITE_WEP104:
++		alg_name = "WEP";
++		break;
++	case WLAN_CIPHER_SUITE_TKIP:
++		alg_name = "TKIP";
++		break;
++	case WLAN_CIPHER_SUITE_CCMP:
++		alg_name = "CCMP";
++		break;
++	case WIFI_CIPHER_SUITE_GCMP:
++		alg_name = "GCMP";
++		break;
++	case WIFI_CIPHER_SUITE_GCMP_256:
++		alg_name = "GCMP_256";
++		break;
++	case WIFI_CIPHER_SUITE_CCMP_256:
++		alg_name = "CCMP_256";
++		break;
++#ifdef CONFIG_IEEE80211W
++	case WLAN_CIPHER_SUITE_AES_CMAC:
++		alg_name = "BIP";
++		break;
++	case WIFI_CIPHER_SUITE_BIP_GMAC_128:
++		alg_name = "BIP_GMAC_128";
++		break;
++	case WIFI_CIPHER_SUITE_BIP_GMAC_256:
++		alg_name = "BIP_GMAC_256";
++		break;
++	case WIFI_CIPHER_SUITE_BIP_CMAC_256:
++		alg_name = "BIP_CMAC_256";
++		break;
++#endif /* CONFIG_IEEE80211W */
++#ifdef CONFIG_WAPI_SUPPORT
++	case WLAN_CIPHER_SUITE_SMS4:
++		alg_name = "SMS4";
++		if (pairwise == NL80211_KEYTYPE_PAIRWISE) {
++			if (key_index != 0 && key_index != 1) {
++				ret = -ENOTSUPP;
++				goto addkey_end;
++			}
++			_rtw_memcpy((void *)param->sta_addr, (void *)mac_addr, ETH_ALEN);
++		} else
++			RTW_INFO("mac_addr is null\n");
++		RTW_INFO("rtw_wx_set_enc_ext: SMS4 case\n");
++		break;
++#endif
++
++	default:
++		ret = -ENOTSUPP;
++		goto addkey_end;
++	}
++
++	strncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN);
++
++
++	if (!mac_addr || is_broadcast_ether_addr(mac_addr)
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++		|| !pairwise
++		#endif
++	) {
++		param->u.crypt.set_tx = 0; /* for wpa/wpa2 group key */
++	} else {
++		param->u.crypt.set_tx = 1; /* for wpa/wpa2 pairwise key */
++	}
++
++	param->u.crypt.idx = key_index;
++
++	if (params->seq_len && params->seq) {
++		_rtw_memcpy(param->u.crypt.seq, (u8 *)params->seq, params->seq_len);
++		RTW_INFO(FUNC_NDEV_FMT" seq_len:%u, seq:0x%llx\n", FUNC_NDEV_ARG(ndev)
++			, params->seq_len, RTW_GET_LE64(param->u.crypt.seq));
++	}
++
++	if (params->key_len && params->key) {
++		param->u.crypt.key_len = params->key_len;
++		_rtw_memcpy(param->u.crypt.key, (u8 *)params->key, params->key_len);
++	}
++
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
++#ifdef CONFIG_TDLS
++		if (rtw_tdls_is_driver_setup(padapter) == _FALSE && mac_addr) {
++			ptdls_sta = rtw_get_stainfo(&padapter->stapriv, (void *)mac_addr);
++			if (ptdls_sta != NULL && ptdls_sta->tdls_sta_state) {
++				_rtw_memcpy(ptdls_sta->tpk.tk, params->key, params->key_len);
++				rtw_tdls_set_key(padapter, ptdls_sta);
++				goto addkey_end;
++			}
++		}
++#endif /* CONFIG_TDLS */
++		ret = rtw_cfg80211_set_encryption(ndev, param);
++	} else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
++#ifdef CONFIG_AP_MODE
++		if (mac_addr)
++			_rtw_memcpy(param->sta_addr, (void *)mac_addr, ETH_ALEN);
++
++		ret = rtw_cfg80211_ap_set_encryption(ndev, param);
++#endif
++	} else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE
++		|| check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE
++	) {
++		/* RTW_INFO("@@@@@@@@@@ fw_state=0x%x, iftype=%d\n", pmlmepriv->fw_state, rtw_wdev->iftype); */
++		ret = rtw_cfg80211_set_encryption(ndev, param);
++	} else
++		RTW_INFO("error! fw_state=0x%x, iftype=%d\n", pmlmepriv->fw_state, rtw_wdev->iftype);
++
++
++addkey_end:
++	if (param)
++		rtw_mfree(param, param_len);
++
++	return ret;
++
++}
++
++static int cfg80211_rtw_get_key(struct wiphy *wiphy, struct net_device *ndev
++	, u8 keyid
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++	, bool pairwise
++#endif
++	, const u8 *mac_addr, void *cookie
++	, void (*callback)(void *cookie, struct key_params *))
++{
++#define GET_KEY_PARAM_FMT_S " keyid=%d"
++#define GET_KEY_PARAM_ARG_S , keyid
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++	#define GET_KEY_PARAM_FMT_2_6_37 ", pairwise=%d"
++	#define GET_KEY_PARAM_ARG_2_6_37 , pairwise
++#else
++	#define GET_KEY_PARAM_FMT_2_6_37 ""
++	#define GET_KEY_PARAM_ARG_2_6_37
++#endif
++#define GET_KEY_PARAM_FMT_E ", addr=%pM"
++#define GET_KEY_PARAM_ARG_E , mac_addr
++
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct security_priv *sec = &adapter->securitypriv;
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct sta_info *sta = NULL;
++	u32 cipher = _NO_PRIVACY_;
++	union Keytype *key = NULL;
++	u8 key_len = 0;
++	u64 *pn = NULL;
++	u8 pn_len = 0;
++	u8 pn_val[8] = {0};
++
++	struct key_params params;
++	int ret = -ENOENT;
++
++	if (keyid >= WEP_KEYS
++		#ifdef CONFIG_IEEE80211W
++		&& keyid > BIP_MAX_KEYID
++		#endif
++	)
++		goto exit;
++
++	if (!mac_addr || is_broadcast_ether_addr(mac_addr)
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++		|| (MLME_IS_STA(adapter) && !pairwise)
++		#endif
++	) {	
++		/* WEP key, TX GTK/IGTK, RX GTK/IGTK(for STA mode) */
++		if (is_wep_enc(sec->dot118021XGrpPrivacy)) {
++			if (keyid >= WEP_KEYS)
++				goto exit;
++			if (!(sec->key_mask & BIT(keyid)))
++				goto exit;
++			cipher = sec->dot118021XGrpPrivacy;
++			key = &sec->dot11DefKey[keyid];
++		} else {
++			if (keyid < WEP_KEYS) {
++				if (sec->binstallGrpkey != _TRUE)
++					goto exit;
++				cipher = sec->dot118021XGrpPrivacy;
++				key = &sec->dot118021XGrpKey[keyid];
++				sta = rtw_get_bcmc_stainfo(adapter);
++				if (sta)
++					pn = &sta->dot11txpn.val;
++			#ifdef CONFIG_IEEE80211W
++			} else if (keyid <= BIP_MAX_KEYID) {
++				if (SEC_IS_BIP_KEY_INSTALLED(sec) != _TRUE)
++					goto exit;
++				cipher = sec->dot11wCipher;
++				key = &sec->dot11wBIPKey[keyid];
++				pn = &sec->dot11wBIPtxpn.val;
++			#endif
++			}
++		}
++	} else {
++		/* Pairwise key, RX GTK/IGTK for specific peer */
++		sta = rtw_get_stainfo(stapriv, mac_addr);
++		if (!sta)
++			goto exit;
++
++		if (keyid < WEP_KEYS && pairwise) {
++			if (sta->bpairwise_key_installed != _TRUE)
++				goto exit;
++			cipher = sta->dot118021XPrivacy;
++			key = &sta->dot118021x_UncstKey;
++		#ifdef CONFIG_RTW_MESH
++		} else if (keyid < WEP_KEYS && !pairwise) {
++			if (!(sta->gtk_bmp & BIT(keyid)))
++				goto exit;
++			cipher = sta->group_privacy;
++			key = &sta->gtk;
++		#ifdef CONFIG_IEEE80211W
++		} else if (keyid <= BIP_MAX_KEYID && !pairwise) {
++			if (!(sta->igtk_bmp & BIT(keyid)))
++				goto exit;
++			cipher = sta->dot11wCipher;
++			key = &sta->igtk;
++			pn = &sta->igtk_pn.val;
++		#endif
++		#endif /* CONFIG_RTW_MESH */
++		}
++	}
++
++	if (!key)
++		goto exit;
++
++	if (cipher == _WEP40_) {
++		cipher = WLAN_CIPHER_SUITE_WEP40;
++		key_len = sec->dot11DefKeylen[keyid];
++	} else if (cipher == _WEP104_) {
++		cipher = WLAN_CIPHER_SUITE_WEP104;
++		key_len = sec->dot11DefKeylen[keyid];
++	} else if (cipher == _TKIP_ || cipher == _TKIP_WTMIC_) {
++		cipher = WLAN_CIPHER_SUITE_TKIP;
++		key_len = 16;
++	} else if (cipher == _AES_) {
++		cipher = WLAN_CIPHER_SUITE_CCMP;
++		key_len = 16;
++#ifdef CONFIG_WAPI_SUPPORT
++	} else if (cipher == _SMS4_) {
++		cipher = WLAN_CIPHER_SUITE_SMS4;
++		key_len = 16;
++#endif
++	} else if (cipher == _GCMP_) {
++		cipher = WIFI_CIPHER_SUITE_GCMP;
++		key_len = 16;
++	} else if (cipher == _CCMP_256_) {
++		cipher = WIFI_CIPHER_SUITE_CCMP_256;
++		key_len = 32;
++	} else if (cipher == _GCMP_256_) {
++		cipher = WIFI_CIPHER_SUITE_GCMP_256;
++		key_len = 32;
++	#ifdef CONFIG_IEEE80211W
++	} else if (cipher == _BIP_CMAC_128_) {
++		cipher = WLAN_CIPHER_SUITE_AES_CMAC;
++		key_len = 16;
++	} else if (cipher == _BIP_GMAC_128_) {
++		cipher = WIFI_CIPHER_SUITE_BIP_GMAC_128;
++		key_len = 16;
++	} else if (cipher == _BIP_GMAC_256_) {
++		cipher = WIFI_CIPHER_SUITE_BIP_GMAC_256;
++		key_len = 32;
++	} else if (cipher == _BIP_CMAC_256_) {
++		cipher = WIFI_CIPHER_SUITE_BIP_CMAC_256;
++		key_len = 32;
++	#endif
++	} else {
++		RTW_WARN(FUNC_NDEV_FMT" unknown cipher:%u\n", FUNC_NDEV_ARG(ndev), cipher);
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (pn) {
++		*((u64 *)pn_val) = cpu_to_le64(*pn);
++		pn_len = 6;
++	}
++
++	ret = 0;
++	
++exit:
++	RTW_INFO(FUNC_NDEV_FMT
++		GET_KEY_PARAM_FMT_S
++		GET_KEY_PARAM_FMT_2_6_37
++		GET_KEY_PARAM_FMT_E
++		" ret %d\n", FUNC_NDEV_ARG(ndev)
++		GET_KEY_PARAM_ARG_S
++		GET_KEY_PARAM_ARG_2_6_37
++		GET_KEY_PARAM_ARG_E
++		, ret);
++	if (pn)
++		RTW_INFO(FUNC_NDEV_FMT " seq:0x%llx\n", FUNC_NDEV_ARG(ndev), *pn);
++
++	if (ret == 0) {
++		_rtw_memset(&params, 0, sizeof(params));
++
++		params.cipher = cipher;
++		params.key = key->skey;
++		params.key_len = key_len;
++		if (pn) {
++			params.seq = pn_val;
++			params.seq_len = pn_len;
++		}
++
++		callback(cookie, &params);
++	}
++
++	return ret;
++}
++
++static int cfg80211_rtw_del_key(struct wiphy *wiphy, struct net_device *ndev,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++				u8 key_index, bool pairwise, const u8 *mac_addr)
++#else	/* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */
++				u8 key_index, const u8 *mac_addr)
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++
++	RTW_INFO(FUNC_NDEV_FMT" key_index=%d, addr=%pM\n", FUNC_NDEV_ARG(ndev), key_index, mac_addr);
++
++	if (key_index == psecuritypriv->dot11PrivacyKeyIndex) {
++		/* clear the flag of wep default key set. */
++		psecuritypriv->bWepDefaultKeyIdxSet = 0;
++	}
++
++	return 0;
++}
++
++static int cfg80211_rtw_set_default_key(struct wiphy *wiphy,
++	struct net_device *ndev, u8 key_index
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
++	, bool unicast, bool multicast
++	#endif
++)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++
++#define SET_DEF_KEY_PARAM_FMT " key_index=%d"
++#define SET_DEF_KEY_PARAM_ARG , key_index
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
++	#define SET_DEF_KEY_PARAM_FMT_2_6_38 ", unicast=%d, multicast=%d"
++	#define SET_DEF_KEY_PARAM_ARG_2_6_38 , unicast, multicast
++#else
++	#define SET_DEF_KEY_PARAM_FMT_2_6_38 ""
++	#define SET_DEF_KEY_PARAM_ARG_2_6_38
++#endif
++
++	RTW_INFO(FUNC_NDEV_FMT
++		SET_DEF_KEY_PARAM_FMT
++		SET_DEF_KEY_PARAM_FMT_2_6_38
++		"\n", FUNC_NDEV_ARG(ndev)
++		SET_DEF_KEY_PARAM_ARG
++		SET_DEF_KEY_PARAM_ARG_2_6_38
++	);
++
++	if ((key_index < WEP_KEYS) && ((psecuritypriv->dot11PrivacyAlgrthm == _WEP40_) || (psecuritypriv->dot11PrivacyAlgrthm == _WEP104_))) { /* set wep default key */
++		psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
++
++		psecuritypriv->dot11PrivacyKeyIndex = key_index;
++
++		psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
++		psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
++		if (psecuritypriv->dot11DefKeylen[key_index] == 13) {
++			psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
++			psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
++		}
++
++		psecuritypriv->bWepDefaultKeyIdxSet = 1; /* set the flag to represent that wep default key has been set */
++	}
++
++	return 0;
++
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30))
++int cfg80211_rtw_set_default_mgmt_key(struct wiphy *wiphy,
++	struct net_device *ndev, u8 key_index)
++{
++#define SET_DEF_KEY_PARAM_FMT " key_index=%d"
++#define SET_DEF_KEY_PARAM_ARG , key_index
++
++	RTW_INFO(FUNC_NDEV_FMT
++		SET_DEF_KEY_PARAM_FMT
++		"\n", FUNC_NDEV_ARG(ndev)
++		SET_DEF_KEY_PARAM_ARG
++	);
++
++	return 0;
++}
++#endif
++
++#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
++static int cfg80211_rtw_set_rekey_data(struct wiphy *wiphy,
++	struct net_device *ndev,
++	struct cfg80211_gtk_rekey_data *data)
++{
++	/*int i;*/
++	struct sta_info *psta;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct mlme_priv   *pmlmepriv = &padapter->mlmepriv;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct security_priv *psecuritypriv = &(padapter->securitypriv);
++
++	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
++	if (psta == NULL) {
++		RTW_INFO("%s, : Obtain Sta_info fail\n", __func__);
++		return -1;
++	}
++
++	_rtw_memcpy(psta->kek, data->kek, NL80211_KEK_LEN);
++	/*printk("\ncfg80211_rtw_set_rekey_data KEK:");
++	for(i=0;i<NL80211_KEK_LEN; i++)
++		printk(" %02x ", psta->kek[i]);*/
++	_rtw_memcpy(psta->kck, data->kck, NL80211_KCK_LEN);
++	/*printk("\ncfg80211_rtw_set_rekey_data KCK:");
++	for(i=0;i<NL80211_KCK_LEN; i++)
++		printk(" %02x ", psta->kck[i]);*/
++	_rtw_memcpy(psta->replay_ctr, data->replay_ctr, NL80211_REPLAY_CTR_LEN);
++	psecuritypriv->binstallKCK_KEK = _TRUE;
++	/*printk("\nREPLAY_CTR: ");
++	for(i=0;i<RTW_REPLAY_CTR_LEN; i++)
++		printk(" %02x ", psta->replay_ctr[i]);*/
++
++	return 0;
++}
++#endif /*CONFIG_GTK_OL*/
++
++#ifdef CONFIG_RTW_MESH
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++static enum nl80211_mesh_power_mode rtw_mesh_ps_to_nl80211_mesh_power_mode(u8 ps)
++{
++	if (ps == RTW_MESH_PS_UNKNOWN)
++		return NL80211_MESH_POWER_UNKNOWN;
++	if (ps == RTW_MESH_PS_ACTIVE)
++		return NL80211_MESH_POWER_ACTIVE;
++	if (ps == RTW_MESH_PS_LSLEEP)
++		return NL80211_MESH_POWER_LIGHT_SLEEP;
++	if (ps == RTW_MESH_PS_DSLEEP)
++		return NL80211_MESH_POWER_DEEP_SLEEP;
++
++	rtw_warn_on(1);
++	return NL80211_MESH_POWER_UNKNOWN;
++}
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++enum nl80211_plink_state rtw_plink_state_to_nl80211_plink_state(u8 plink_state)
++{
++	if (plink_state == RTW_MESH_PLINK_UNKNOWN)
++		return NUM_NL80211_PLINK_STATES;
++	if (plink_state == RTW_MESH_PLINK_LISTEN)
++		return NL80211_PLINK_LISTEN;
++	if (plink_state == RTW_MESH_PLINK_OPN_SNT)
++		return NL80211_PLINK_OPN_SNT;
++	if (plink_state == RTW_MESH_PLINK_OPN_RCVD)
++		return NL80211_PLINK_OPN_RCVD;
++	if (plink_state == RTW_MESH_PLINK_CNF_RCVD)
++		return NL80211_PLINK_CNF_RCVD;
++	if (plink_state == RTW_MESH_PLINK_ESTAB)
++		return NL80211_PLINK_ESTAB;
++	if (plink_state == RTW_MESH_PLINK_HOLDING)
++		return NL80211_PLINK_HOLDING;
++	if (plink_state == RTW_MESH_PLINK_BLOCKED)
++		return NL80211_PLINK_BLOCKED;
++
++	rtw_warn_on(1);
++	return NUM_NL80211_PLINK_STATES;
++}
++
++u8 nl80211_plink_state_to_rtw_plink_state(enum nl80211_plink_state plink_state)
++{
++	if (plink_state == NL80211_PLINK_LISTEN)
++		return RTW_MESH_PLINK_LISTEN;
++	if (plink_state == NL80211_PLINK_OPN_SNT)
++		return RTW_MESH_PLINK_OPN_SNT;
++	if (plink_state == NL80211_PLINK_OPN_RCVD)
++		return RTW_MESH_PLINK_OPN_RCVD;
++	if (plink_state == NL80211_PLINK_CNF_RCVD)
++		return RTW_MESH_PLINK_CNF_RCVD;
++	if (plink_state == NL80211_PLINK_ESTAB)
++		return RTW_MESH_PLINK_ESTAB;
++	if (plink_state == NL80211_PLINK_HOLDING)
++		return RTW_MESH_PLINK_HOLDING;
++	if (plink_state == NL80211_PLINK_BLOCKED)
++		return RTW_MESH_PLINK_BLOCKED;
++
++	rtw_warn_on(1);
++	return RTW_MESH_PLINK_UNKNOWN;
++}
++#endif
++
++static void rtw_cfg80211_fill_mesh_only_sta_info(struct mesh_plink_ent *plink, struct sta_info *sta, struct station_info *sinfo)
++{
++	sinfo->filled |= STATION_INFO_LLID;
++	sinfo->llid = plink->llid;
++	sinfo->filled |= STATION_INFO_PLID;
++	sinfo->plid = plink->plid;
++	sinfo->filled |= STATION_INFO_PLINK_STATE;
++	sinfo->plink_state = rtw_plink_state_to_nl80211_plink_state(plink->plink_state);
++	if (!sta && plink->scanned) {
++		sinfo->filled |= STATION_INFO_SIGNAL;
++		sinfo->signal = translate_percentage_to_dbm(plink->scanned->network.PhyInfo.SignalStrength);
++		sinfo->filled |= STATION_INFO_INACTIVE_TIME;
++		if (plink->plink_state == RTW_MESH_PLINK_UNKNOWN)
++			sinfo->inactive_time = 0 - 1;
++		else
++			sinfo->inactive_time = rtw_get_passing_time_ms(plink->scanned->last_scanned);
++	}
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++	if (sta) {
++		sinfo->filled |= STATION_INFO_LOCAL_PM;
++		sinfo->local_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->local_mps);
++		sinfo->filled |= STATION_INFO_PEER_PM;
++		sinfo->peer_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->peer_mps);
++		sinfo->filled |= STATION_INFO_NONPEER_PM;
++		sinfo->nonpeer_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->nonpeer_mps);
++	}
++#endif
++}
++#endif /* CONFIG_RTW_MESH */
++
++static int cfg80211_rtw_get_station(struct wiphy *wiphy,
++	struct net_device *ndev,
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
++	u8 *mac,
++#else
++	const u8 *mac,
++#endif
++	struct station_info *sinfo)
++{
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct sta_info *psta = NULL;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++#ifdef CONFIG_RTW_MESH
++	struct mesh_plink_ent *plink = NULL;
++#endif
++
++	sinfo->filled = 0;
++
++	if (!mac) {
++		RTW_INFO(FUNC_NDEV_FMT" mac==%p\n", FUNC_NDEV_ARG(ndev), mac);
++		ret = -ENOENT;
++		goto exit;
++	}
++
++	psta = rtw_get_stainfo(pstapriv, mac);
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(padapter)) {
++		if (psta)
++			plink = psta->plink;
++		if (!plink)
++			plink = rtw_mesh_plink_get(padapter, mac);
++	}
++#endif /* CONFIG_RTW_MESH */
++
++	if ((!MLME_IS_MESH(padapter) && !psta)
++		#ifdef CONFIG_RTW_MESH
++		|| (MLME_IS_MESH(padapter) && !plink)
++		#endif
++	) {
++		RTW_INFO(FUNC_NDEV_FMT" no sta info for mac="MAC_FMT"\n"
++			, FUNC_NDEV_ARG(ndev), MAC_ARG(mac));
++		ret = -ENOENT;
++		goto exit;
++	}
++
++#ifdef CONFIG_DEBUG_CFG80211
++	RTW_INFO(FUNC_NDEV_FMT" mac="MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(mac));
++#endif
++
++	/* for infra./P2PClient mode */
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
++		&& check_fwstate(pmlmepriv, WIFI_ASOC_STATE)
++	) {
++		struct wlan_network  *cur_network = &(pmlmepriv->cur_network);
++
++		if (_rtw_memcmp((u8 *)mac, cur_network->network.MacAddress, ETH_ALEN) == _FALSE) {
++			RTW_INFO("%s, mismatch bssid="MAC_FMT"\n", __func__, MAC_ARG(cur_network->network.MacAddress));
++			ret = -ENOENT;
++			goto exit;
++		}
++
++		sinfo->filled |= STATION_INFO_SIGNAL;
++		sinfo->signal = translate_percentage_to_dbm(padapter->recvpriv.signal_strength);
++
++		sinfo->filled |= STATION_INFO_TX_BITRATE;
++		sinfo->txrate.legacy = rtw_get_cur_max_rate(padapter);
++	}
++
++	if (psta) {
++		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE
++			|| check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE
++		) {
++			sinfo->filled |= STATION_INFO_SIGNAL;
++			sinfo->signal = translate_percentage_to_dbm(psta->cmn.rssi_stat.rssi);
++		}
++		sinfo->filled |= STATION_INFO_INACTIVE_TIME;
++		sinfo->inactive_time = rtw_get_passing_time_ms(psta->sta_stats.last_rx_time);
++		sinfo->filled |= STATION_INFO_RX_PACKETS;
++		sinfo->rx_packets = sta_rx_data_pkts(psta);
++		sinfo->filled |= STATION_INFO_TX_PACKETS;
++		sinfo->tx_packets = psta->sta_stats.tx_pkts;
++		sinfo->filled |= STATION_INFO_TX_FAILED;
++		sinfo->tx_failed = psta->sta_stats.tx_fail_cnt;
++	}
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(padapter))
++		rtw_cfg80211_fill_mesh_only_sta_info(plink, psta, sinfo);
++#endif
++
++exit:
++	return ret;
++}
++
++extern int netdev_open(struct net_device *pnetdev);
++
++#if 0
++enum nl80211_iftype {
++	NL80211_IFTYPE_UNSPECIFIED,
++	NL80211_IFTYPE_ADHOC, /* 1 */
++	NL80211_IFTYPE_STATION, /* 2 */
++	NL80211_IFTYPE_AP, /* 3 */
++	NL80211_IFTYPE_AP_VLAN,
++	NL80211_IFTYPE_WDS,
++	NL80211_IFTYPE_MONITOR, /* 6 */
++	NL80211_IFTYPE_MESH_POINT,
++	NL80211_IFTYPE_P2P_CLIENT, /* 8 */
++	NL80211_IFTYPE_P2P_GO, /* 9 */
++	/* keep last */
++	NUM_NL80211_IFTYPES,
++	NL80211_IFTYPE_MAX = NUM_NL80211_IFTYPES - 1
++};
++#endif
++static int cfg80211_rtw_change_iface(struct wiphy *wiphy,
++				     struct net_device *ndev,
++				     enum nl80211_iftype type,
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
++				     u32 *flags,
++#endif
++				     struct vif_params *params)
++{
++	enum nl80211_iftype old_type;
++	NDIS_802_11_NETWORK_INFRASTRUCTURE networkType;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct wireless_dev *rtw_wdev = padapter->rtw_wdev;
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++#ifdef CONFIG_P2P
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++#endif
++#ifdef CONFIG_MONITOR_MODE_XMIT
++	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++#endif
++	int ret = 0;
++	u8 change = _FALSE;
++
++	RTW_INFO(FUNC_NDEV_FMT" type=%d, hw_port:%d\n", FUNC_NDEV_ARG(ndev), type, padapter->hw_port);
++
++	if (adapter_to_dvobj(padapter)->processing_dev_remove == _TRUE) {
++		ret = -EPERM;
++		goto exit;
++	}
++
++
++	RTW_INFO(FUNC_NDEV_FMT" call netdev_open\n", FUNC_NDEV_ARG(ndev));
++	if (netdev_open(ndev) != 0) {
++		RTW_INFO(FUNC_NDEV_FMT" call netdev_open fail\n", FUNC_NDEV_ARG(ndev));
++		ret = -EPERM;
++		goto exit;
++	}
++
++
++	if (_FAIL == rtw_pwr_wakeup(padapter)) {
++		RTW_INFO(FUNC_NDEV_FMT" call rtw_pwr_wakeup fail\n", FUNC_NDEV_ARG(ndev));
++		ret = -EPERM;
++		goto exit;
++	}
++
++	old_type = rtw_wdev->iftype;
++	RTW_INFO(FUNC_NDEV_FMT" old_iftype=%d, new_iftype=%d\n",
++		FUNC_NDEV_ARG(ndev), old_type, type);
++
++	if (old_type != type) {
++		change = _TRUE;
++		pmlmeext->action_public_rxseq = 0xffff;
++		pmlmeext->action_public_dialog_token = 0xff;
++	}
++
++	/* initial default type */
++	ndev->type = ARPHRD_ETHER;
++
++	/*
++	 * Disable Power Save in moniter mode,
++	 * and enable it after leaving moniter mode.
++	 */
++	if (type == NL80211_IFTYPE_MONITOR) {
++		rtw_ps_deny(padapter, PS_DENY_MONITOR_MODE);
++		LeaveAllPowerSaveMode(padapter);
++	} else if (old_type == NL80211_IFTYPE_MONITOR) {
++		/* driver in moniter mode in last time */
++		rtw_ps_deny_cancel(padapter, PS_DENY_MONITOR_MODE);
++	}
++
++	switch (type) {
++	case NL80211_IFTYPE_ADHOC:
++		networkType = Ndis802_11IBSS;
++		break;
++
++	case NL80211_IFTYPE_STATION:
++		networkType = Ndis802_11Infrastructure;
++		#ifdef CONFIG_P2P
++		if (change && pwdinfo->driver_interface == DRIVER_CFG80211) {
++			#if !RTW_P2P_GROUP_INTERFACE
++			if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)
++				|| rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)
++			) {
++				/* it means remove GC/GO and change mode from GC/GO to station(P2P DEVICE) */
++				rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
++			}
++			#endif
++		}
++		#endif /* CONFIG_P2P */
++		break;
++
++	case NL80211_IFTYPE_AP:
++		networkType = Ndis802_11APMode;
++		#ifdef CONFIG_P2P
++		if (change && pwdinfo->driver_interface == DRIVER_CFG80211) {
++			#if !RTW_P2P_GROUP_INTERFACE
++			if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
++				/* it means P2P Group created, we will be GO and change mode from  P2P DEVICE to AP(GO) */
++				rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++			}
++			#endif
++		}
++		#endif /* CONFIG_P2P */
++		break;
++
++#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
++	case NL80211_IFTYPE_P2P_CLIENT:
++		networkType = Ndis802_11Infrastructure;
++		if (change && pwdinfo->driver_interface == DRIVER_CFG80211) {
++			if (!rtw_p2p_enable(padapter, P2P_ROLE_CLIENT)) {
++				ret = -EOPNOTSUPP;
++				goto exit;
++			}
++		}
++		break;
++
++	case NL80211_IFTYPE_P2P_GO:
++		networkType = Ndis802_11APMode;
++		if (change && pwdinfo->driver_interface == DRIVER_CFG80211) {
++			if (!rtw_p2p_enable(padapter, P2P_ROLE_GO)) {
++				ret = -EOPNOTSUPP;
++				goto exit;
++			}
++		}
++		break;
++#endif /* defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) */
++
++#ifdef CONFIG_RTW_MESH
++	case NL80211_IFTYPE_MESH_POINT:
++		networkType = Ndis802_11_mesh;
++		break;
++#endif
++
++#ifdef CONFIG_WIFI_MONITOR
++	case NL80211_IFTYPE_MONITOR:
++		networkType = Ndis802_11Monitor;
++
++#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
++		ndev->type = ARPHRD_IEEE80211; /* IEEE 802.11 : 801 */
++#else
++		ndev->type = ARPHRD_IEEE80211_RADIOTAP; /* IEEE 802.11 + radiotap header : 803 */
++#endif
++		break;
++#endif /* CONFIG_WIFI_MONITOR */
++	default:
++		ret = -EOPNOTSUPP;
++		goto exit;
++	}
++
++	rtw_wdev->iftype = type;
++
++	if (rtw_set_802_11_infrastructure_mode(padapter, networkType, 0) == _FALSE) {
++		rtw_wdev->iftype = old_type;
++		ret = -EPERM;
++		goto exit;
++	}
++
++	rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK);
++#ifdef CONFIG_MONITOR_MODE_XMIT
++	if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE)
++		rtw_indicate_connect(padapter);
++#endif
++
++	#if defined(CONFIG_RTW_WDS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33))
++	if (params->use_4addr != -1) {
++		RTW_INFO(FUNC_NDEV_FMT" use_4addr=%d\n"
++			, FUNC_NDEV_ARG(ndev), params->use_4addr);
++		adapter_set_use_wds(padapter, params->use_4addr);
++	}
++	#endif
++
++exit:
++
++	RTW_INFO(FUNC_NDEV_FMT" ret:%d\n", FUNC_NDEV_ARG(ndev), ret);
++	return ret;
++}
++
++void rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted)
++{
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
++	_irqL	irqL;
++
++#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE)
++	struct cfg80211_scan_info info;
++
++	memset(&info, 0, sizeof(info));
++	info.aborted = aborted;
++#endif
++
++	_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
++	if (pwdev_priv->scan_request != NULL) {
++		#ifdef CONFIG_DEBUG_CFG80211
++		RTW_INFO("%s with scan req\n", __FUNCTION__);
++		#endif
++
++		/* avoid WARN_ON(request != wiphy_to_dev(request->wiphy)->scan_req); */
++		if (pwdev_priv->scan_request->wiphy != pwdev_priv->rtw_wdev->wiphy)
++			RTW_INFO("error wiphy compare\n");
++		else
++#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE)
++			cfg80211_scan_done(pwdev_priv->scan_request, &info);
++#else
++			cfg80211_scan_done(pwdev_priv->scan_request, aborted);
++#endif
++
++		pwdev_priv->scan_request = NULL;
++	} else {
++		#ifdef CONFIG_DEBUG_CFG80211
++		RTW_INFO("%s without scan req\n", __FUNCTION__);
++		#endif
++	}
++	_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
++}
++
++u32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms)
++{
++	struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter);
++	u8 empty = _FALSE;
++	systime start;
++	u32 pass_ms;
++
++	start = rtw_get_current_time();
++
++	while (rtw_get_passing_time_ms(start) <= timeout_ms) {
++
++		if (RTW_CANNOT_RUN(adapter))
++			break;
++
++		if (!wdev_priv->scan_request) {
++			empty = _TRUE;
++			break;
++		}
++
++		rtw_msleep_os(10);
++	}
++
++	pass_ms = rtw_get_passing_time_ms(start);
++
++	if (empty == _FALSE && pass_ms > timeout_ms)
++		RTW_PRINT(FUNC_ADPT_FMT" pass_ms:%u, timeout\n"
++			, FUNC_ADPT_ARG(adapter), pass_ms);
++
++	return pass_ms;
++}
++
++void rtw_cfg80211_unlink_bss(_adapter *padapter, struct wlan_network *pnetwork)
++{
++	struct wireless_dev *pwdev = padapter->rtw_wdev;
++	struct wiphy *wiphy = pwdev->wiphy;
++	struct cfg80211_bss *bss = NULL;
++	WLAN_BSSID_EX select_network = pnetwork->network;
++
++	bss = cfg80211_get_bss(wiphy, NULL/*notify_channel*/,
++		select_network.MacAddress, select_network.Ssid.Ssid,
++		select_network.Ssid.SsidLength,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
++		select_network.InfrastructureMode == Ndis802_11Infrastructure?IEEE80211_BSS_TYPE_ESS:IEEE80211_BSS_TYPE_IBSS,
++		IEEE80211_PRIVACY(select_network.Privacy));
++#else
++		select_network.InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS,
++		select_network.InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS);
++#endif
++
++	if (bss) {
++		cfg80211_unlink_bss(wiphy, bss);
++		RTW_INFO("%s(): cfg80211_unlink %s!!\n", __func__, select_network.Ssid.Ssid);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
++		cfg80211_put_bss(padapter->rtw_wdev->wiphy, bss);
++#else
++		cfg80211_put_bss(bss);
++#endif
++	}
++	return;
++}
++
++/* if target wps scan ongoing, target_ssid is filled */
++int rtw_cfg80211_is_target_wps_scan(struct cfg80211_scan_request *scan_req, struct cfg80211_ssid *target_ssid)
++{
++	int ret = 0;
++
++	if (scan_req->n_ssids != 1
++		|| scan_req->ssids[0].ssid_len == 0
++		|| scan_req->n_channels != 1
++	)
++		goto exit;
++
++	/* under target WPS scan */
++	_rtw_memcpy(target_ssid, scan_req->ssids, sizeof(struct cfg80211_ssid));
++	ret = 1;
++
++exit:
++	return ret;
++}
++
++static void _rtw_cfg80211_surveydone_event_callback(_adapter *padapter, struct cfg80211_scan_request *scan_req)
++{
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	RT_CHANNEL_INFO *chset = rfctl->channel_set;
++	_irqL	irqL;
++	_list					*plist, *phead;
++	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	_queue				*queue	= &(pmlmepriv->scanned_queue);
++	struct	wlan_network	*pnetwork = NULL;
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++	struct cfg80211_ssid target_ssid;
++	u8 target_wps_scan = 0;
++	u8 ch;
++
++#ifdef CONFIG_DEBUG_CFG80211
++	RTW_INFO("%s\n", __func__);
++#endif
++
++	if (scan_req)
++		target_wps_scan = rtw_cfg80211_is_target_wps_scan(scan_req, &target_ssid);
++	else {
++		_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
++		if (pwdev_priv->scan_request != NULL)
++			target_wps_scan = rtw_cfg80211_is_target_wps_scan(pwdev_priv->scan_request, &target_ssid);
++		_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
++	}
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++
++	while (1) {
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++		ch = pnetwork->network.Configuration.DSConfig;
++
++		/* report network only if the current channel set contains the channel to which this network belongs */
++		if (rtw_chset_search_ch(chset, ch) >= 0
++			&& rtw_mlme_band_check(padapter, ch) == _TRUE
++			&& _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))
++			&& (!IS_DFS_SLAVE_WITH_RD(rfctl)
++				|| rtw_rfctl_dfs_domain_unknown(rfctl)
++				|| !rtw_chset_is_ch_non_ocp(chset, ch))
++		) {
++			if (target_wps_scan)
++				rtw_cfg80211_clear_wps_sr_of_non_target_bss(padapter, pnetwork, &target_ssid);
++			rtw_cfg80211_inform_bss(padapter, pnetwork);
++		}
++#if 0
++		/* check ralink testbed RSN IE length */
++		{
++			if (_rtw_memcmp(pnetwork->network.Ssid.Ssid, "Ralink_11n_AP", 13)) {
++				uint ie_len = 0;
++				u8 *p = NULL;
++				p = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_));
++				RTW_INFO("ie_len=%d\n", ie_len);
++			}
++		}
++#endif
++		plist = get_next(plist);
++
++	}
++
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++}
++
++inline void rtw_cfg80211_surveydone_event_callback(_adapter *padapter)
++{
++	_rtw_cfg80211_surveydone_event_callback(padapter, NULL);
++}
++
++static int rtw_cfg80211_set_probe_req_wpsp2pie(_adapter *padapter, char *buf, int len)
++{
++	int ret = 0;
++	uint wps_ielen = 0;
++	u8 *wps_ie;
++	u32	p2p_ielen = 0;
++	u8 *p2p_ie;
++	u32	wfd_ielen = 0;
++	u8 *wfd_ie;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++#ifdef CONFIG_DEBUG_CFG80211
++	RTW_INFO("%s, ielen=%d\n", __func__, len);
++#endif
++
++	if (len > 0) {
++		wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen);
++		if (wps_ie) {
++			#ifdef CONFIG_DEBUG_CFG80211
++			RTW_INFO("probe_req_wps_ielen=%d\n", wps_ielen);
++			#endif
++
++			if (pmlmepriv->wps_probe_req_ie) {
++				u32 free_len = pmlmepriv->wps_probe_req_ie_len;
++				pmlmepriv->wps_probe_req_ie_len = 0;
++				rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len);
++				pmlmepriv->wps_probe_req_ie = NULL;
++			}
++
++			pmlmepriv->wps_probe_req_ie = rtw_malloc(wps_ielen);
++			if (pmlmepriv->wps_probe_req_ie == NULL) {
++				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++				return -EINVAL;
++
++			}
++			_rtw_memcpy(pmlmepriv->wps_probe_req_ie, wps_ie, wps_ielen);
++			pmlmepriv->wps_probe_req_ie_len = wps_ielen;
++		}
++
++		/* buf += wps_ielen; */
++		/* len -= wps_ielen; */
++
++		#ifdef CONFIG_P2P
++		p2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen);
++		if (p2p_ie) {
++			struct wifidirect_info *wdinfo = &padapter->wdinfo;
++			u32 attr_contentlen = 0;
++			u8 listen_ch_attr[5];
++
++			#ifdef CONFIG_DEBUG_CFG80211
++			RTW_INFO("probe_req_p2p_ielen=%d\n", p2p_ielen);
++			#endif
++
++			if (pmlmepriv->p2p_probe_req_ie) {
++				u32 free_len = pmlmepriv->p2p_probe_req_ie_len;
++				pmlmepriv->p2p_probe_req_ie_len = 0;
++				rtw_mfree(pmlmepriv->p2p_probe_req_ie, free_len);
++				pmlmepriv->p2p_probe_req_ie = NULL;
++			}
++
++			pmlmepriv->p2p_probe_req_ie = rtw_malloc(p2p_ielen);
++			if (pmlmepriv->p2p_probe_req_ie == NULL) {
++				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++				return -EINVAL;
++
++			}
++			_rtw_memcpy(pmlmepriv->p2p_probe_req_ie, p2p_ie, p2p_ielen);
++			pmlmepriv->p2p_probe_req_ie_len = p2p_ielen;
++
++			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, (u8 *)listen_ch_attr, (uint *) &attr_contentlen)
++				&& attr_contentlen == 5) {
++				if (wdinfo->listen_channel !=  listen_ch_attr[4]) {
++					RTW_INFO(FUNC_ADPT_FMT" listen channel - country:%c%c%c, class:%u, ch:%u\n",
++						FUNC_ADPT_ARG(padapter), listen_ch_attr[0], listen_ch_attr[1], listen_ch_attr[2],
++						listen_ch_attr[3], listen_ch_attr[4]);
++					wdinfo->listen_channel = listen_ch_attr[4];
++				}
++			}
++		}
++		#endif /* CONFIG_P2P */
++
++		#ifdef CONFIG_WFD
++		wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen);
++		if (wfd_ie) {
++			#ifdef CONFIG_DEBUG_CFG80211
++			RTW_INFO("probe_req_wfd_ielen=%d\n", wfd_ielen);
++			#endif
++
++			if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_PROBE_REQ_IE, wfd_ie, wfd_ielen) != _SUCCESS)
++				return -EINVAL;
++		}
++		#endif /* CONFIG_WFD */
++
++		#ifdef CONFIG_RTW_MBO
++		rtw_mbo_update_ie_data(padapter, buf, len);
++		#endif
++	}
++
++	return ret;
++
++}
++
++#ifdef CONFIG_CONCURRENT_MODE
++u8 rtw_cfg80211_scan_via_buddy(_adapter *padapter, struct cfg80211_scan_request *request)
++{
++	int i;
++	u8 ret = _FALSE;
++	_adapter *iface = NULL;
++	_irqL	irqL;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		struct mlme_priv *buddy_mlmepriv;
++		struct rtw_wdev_priv *buddy_wdev_priv;
++
++		iface = dvobj->padapters[i];
++		if (iface == NULL)
++			continue;
++
++		if (iface == padapter)
++			continue;
++
++		if (rtw_is_adapter_up(iface) == _FALSE)
++			continue;
++
++		buddy_mlmepriv = &iface->mlmepriv;
++		if (!check_fwstate(buddy_mlmepriv, WIFI_UNDER_SURVEY))
++			continue;
++
++		buddy_wdev_priv = adapter_wdev_data(iface);
++		_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
++		_enter_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL);
++		if (buddy_wdev_priv->scan_request) {
++			pmlmepriv->scanning_via_buddy_intf = _TRUE;
++			_enter_critical_bh(&pmlmepriv->lock, &irqL);
++			set_fwstate(pmlmepriv, WIFI_UNDER_SURVEY);
++			_exit_critical_bh(&pmlmepriv->lock, &irqL);
++			pwdev_priv->scan_request = request;
++			ret = _TRUE;
++		}
++		_exit_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL);
++		_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
++
++		if (ret == _TRUE)
++			goto exit;
++	}
++
++exit:
++	return ret;
++}
++
++void rtw_cfg80211_indicate_scan_done_for_buddy(_adapter *padapter, bool bscan_aborted)
++{
++	int i;
++	_adapter *iface = NULL;
++	_irqL	irqL;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct mlme_priv *mlmepriv;
++	struct rtw_wdev_priv *wdev_priv;
++	bool indicate_buddy_scan;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if ((iface) && rtw_is_adapter_up(iface)) {
++
++			if (iface == padapter)
++				continue;
++
++			mlmepriv = &(iface->mlmepriv);
++			wdev_priv = adapter_wdev_data(iface);
++
++			indicate_buddy_scan = _FALSE;
++			_enter_critical_bh(&wdev_priv->scan_req_lock, &irqL);
++			if (mlmepriv->scanning_via_buddy_intf == _TRUE) {
++				mlmepriv->scanning_via_buddy_intf = _FALSE;
++				clr_fwstate(mlmepriv, WIFI_UNDER_SURVEY);
++				if (wdev_priv->scan_request)
++					indicate_buddy_scan = _TRUE;
++			}
++			_exit_critical_bh(&wdev_priv->scan_req_lock, &irqL);
++
++			if (indicate_buddy_scan == _TRUE) {
++				rtw_cfg80211_surveydone_event_callback(iface);
++				rtw_indicate_scan_done(iface, bscan_aborted);
++			}
++
++		}
++	}
++}
++#endif /* CONFIG_CONCURRENT_MODE */
++
++static int cfg80211_rtw_scan(struct wiphy *wiphy
++	#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++	, struct net_device *ndev
++	#endif
++	, struct cfg80211_scan_request *request)
++{
++	int i;
++	u8 _status = _FALSE;
++	int ret = 0;
++	struct sitesurvey_parm parm;
++	_irqL	irqL;
++	u8 survey_times = 3;
++	u8 survey_times_for_one_ch = 6;
++	struct cfg80211_ssid *ssids = request->ssids;
++	int social_channel = 0, j = 0;
++	bool need_indicate_scan_done = _FALSE;
++	bool ps_denied = _FALSE;
++	u8 ssc_chk;
++	_adapter *padapter;
++	struct wireless_dev *wdev;
++	struct rtw_wdev_priv *pwdev_priv;
++	struct mlme_priv *pmlmepriv = NULL;
++#ifdef CONFIG_P2P
++	struct wifidirect_info *pwdinfo;
++#endif /* CONFIG_P2P */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	wdev = request->wdev;
++	#if defined(RTW_DEDICATED_P2P_DEVICE)
++	if (wdev == wiphy_to_pd_wdev(wiphy))
++		padapter = wiphy_to_adapter(wiphy);
++	else
++	#endif
++	if (wdev_to_ndev(wdev))
++		padapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));
++	else {
++		ret = -EINVAL;
++		goto exit;
++	}
++#else
++	if (ndev == NULL) {
++		ret = -EINVAL;
++		goto exit;
++	}
++	padapter = (_adapter *)rtw_netdev_priv(ndev);
++	wdev = ndev_to_wdev(ndev);
++#endif
++
++	pwdev_priv = adapter_wdev_data(padapter);
++	pmlmepriv = &padapter->mlmepriv;
++#ifdef CONFIG_P2P
++	pwdinfo = &(padapter->wdinfo);
++#endif /* CONFIG_P2P */
++
++	RTW_INFO(FUNC_ADPT_FMT"%s\n", FUNC_ADPT_ARG(padapter)
++		, wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : "");
++
++#if 1
++	ssc_chk = rtw_sitesurvey_condition_check(padapter, _TRUE);
++
++	if (ssc_chk == SS_DENY_MP_MODE)
++		goto bypass_p2p_chk;
++#ifdef DBG_LA_MODE
++	if (ssc_chk == SS_DENY_LA_MODE)
++		goto bypass_p2p_chk;
++#endif
++#ifdef CONFIG_P2P
++	if (pwdinfo->driver_interface == DRIVER_CFG80211) {
++		if (request->n_ssids && ssids
++			&& _rtw_memcmp(ssids[0].ssid, "DIRECT-", 7)
++			&& rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL)
++		) {
++			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
++				if (!rtw_p2p_enable(padapter, P2P_ROLE_DEVICE)) {
++					ret = -EOPNOTSUPP;
++					goto exit;
++				}
++			} else {
++				rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++				#ifdef CONFIG_DEBUG_CFG80211
++				RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));
++				#endif
++			}
++			rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
++
++			if (request->n_channels == 3 &&
++				request->channels[0]->hw_value == 1 &&
++				request->channels[1]->hw_value == 6 &&
++				request->channels[2]->hw_value == 11
++			)
++				social_channel = 1;
++		}
++	}
++#endif /*CONFIG_P2P*/
++
++	if (request->ie && request->ie_len > 0)
++		rtw_cfg80211_set_probe_req_wpsp2pie(padapter, (u8 *)request->ie, request->ie_len);
++
++bypass_p2p_chk:
++
++	switch (ssc_chk) {
++		case SS_ALLOW :
++			break;
++
++		case SS_DENY_MP_MODE:
++			ret = -EPERM;
++			goto exit;
++		#ifdef DBG_LA_MODE
++		case SS_DENY_LA_MODE:
++			ret = -EPERM;
++			goto exit;
++		#endif
++		#ifdef CONFIG_RTW_REPEATER_SON
++		case SS_DENY_RSON_SCANING :
++		#endif
++		case SS_DENY_BLOCK_SCAN :
++		case SS_DENY_SELF_AP_UNDER_WPS :
++		case SS_DENY_SELF_AP_UNDER_LINKING :
++		case SS_DENY_SELF_AP_UNDER_SURVEY :
++		case SS_DENY_SELF_STA_UNDER_SURVEY :
++		#ifdef CONFIG_CONCURRENT_MODE
++		case SS_DENY_BUDDY_UNDER_LINK_WPS :
++		#endif
++		case SS_DENY_BUSY_TRAFFIC :
++		case SS_DENY_ADAPTIVITY:
++			need_indicate_scan_done = _TRUE;
++			goto check_need_indicate_scan_done;
++
++		case SS_DENY_BY_DRV :
++			#ifdef CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY
++			ret = -EBUSY;
++			goto exit;
++			#else
++			need_indicate_scan_done = _TRUE;
++			goto check_need_indicate_scan_done;
++			#endif
++			break;
++
++		case SS_DENY_SELF_STA_UNDER_LINKING :
++			ret = -EBUSY;
++			goto check_need_indicate_scan_done;
++
++		#ifdef CONFIG_CONCURRENT_MODE
++		case SS_DENY_BUDDY_UNDER_SURVEY :
++			{
++				bool scan_via_buddy = rtw_cfg80211_scan_via_buddy(padapter, request);
++
++				if (scan_via_buddy == _FALSE)
++					need_indicate_scan_done = _TRUE;
++
++				goto check_need_indicate_scan_done;
++			}
++		#endif
++
++		default :
++			RTW_ERR("site survey check code (%d) unknown\n", ssc_chk);
++			need_indicate_scan_done = _TRUE;
++			goto check_need_indicate_scan_done;
++	}
++
++	rtw_ps_deny(padapter, PS_DENY_SCAN);
++	ps_denied = _TRUE;
++	if (_FAIL == rtw_pwr_wakeup(padapter)) {
++		need_indicate_scan_done = _TRUE;
++		goto check_need_indicate_scan_done;
++	}
++
++#else
++
++
++#ifdef CONFIG_MP_INCLUDED
++	if (rtw_mp_mode_check(padapter)) {
++		RTW_INFO("MP mode block Scan request\n");
++		ret = -EPERM;
++		goto exit;
++	}
++#endif
++
++#ifdef CONFIG_P2P
++	if (pwdinfo->driver_interface == DRIVER_CFG80211) {
++		if (request->n_ssids && ssids
++			&& _rtw_memcmp(ssids[0].ssid, "DIRECT-", 7)
++			&& rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL)
++		) {
++			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++				rtw_p2p_enable(padapter, P2P_ROLE_DEVICE);
++			else {
++				rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++				#ifdef CONFIG_DEBUG_CFG80211
++				RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));
++				#endif
++			}
++			rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
++
++			if (request->n_channels == 3 &&
++				request->channels[0]->hw_value == 1 &&
++				request->channels[1]->hw_value == 6 &&
++				request->channels[2]->hw_value == 11
++			)
++				social_channel = 1;
++		}
++	}
++#endif /*CONFIG_P2P*/
++
++	if (request->ie && request->ie_len > 0)
++		rtw_cfg80211_set_probe_req_wpsp2pie(padapter, (u8 *)request->ie, request->ie_len);
++
++#ifdef CONFIG_RTW_REPEATER_SON
++	if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) {
++		RTW_INFO(FUNC_ADPT_FMT" blocking scan for under rson scanning process\n", FUNC_ADPT_ARG(padapter));
++		need_indicate_scan_done = _TRUE;
++		goto check_need_indicate_scan_done;
++	}
++#endif
++
++	if (adapter_wdev_data(padapter)->block_scan == _TRUE) {
++		RTW_INFO(FUNC_ADPT_FMT" wdev_priv.block_scan is set\n", FUNC_ADPT_ARG(padapter));
++		need_indicate_scan_done = _TRUE;
++		goto check_need_indicate_scan_done;
++	}
++
++	rtw_ps_deny(padapter, PS_DENY_SCAN);
++	ps_denied = _TRUE;
++	if (_FAIL == rtw_pwr_wakeup(padapter)) {
++		need_indicate_scan_done = _TRUE;
++		goto check_need_indicate_scan_done;
++	}
++
++	if (rtw_is_scan_deny(padapter)) {
++		RTW_INFO(FUNC_ADPT_FMT	": scan deny\n", FUNC_ADPT_ARG(padapter));
++#ifdef CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY
++		ret = -EBUSY;
++		goto exit;
++#else
++		need_indicate_scan_done = _TRUE;
++		goto check_need_indicate_scan_done;
++#endif
++	}
++
++	/* check fw state*/
++	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
++
++#ifdef CONFIG_DEBUG_CFG80211
++		RTW_INFO(FUNC_ADPT_FMT" under WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter));
++#endif
++
++		if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS | WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING) == _TRUE) {
++			RTW_INFO("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state);
++
++			if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS))
++				RTW_INFO("AP mode process WPS\n");
++
++			need_indicate_scan_done = _TRUE;
++			goto check_need_indicate_scan_done;
++		}
++	}
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE) {
++		RTW_INFO("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state);
++		need_indicate_scan_done = _TRUE;
++		goto check_need_indicate_scan_done;
++	} else if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) {
++		RTW_INFO("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state);
++		ret = -EBUSY;
++		goto check_need_indicate_scan_done;
++	}
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)) {
++		RTW_INFO("%s exit due to buddy_intf's mlme state under linking or wps\n", __func__);
++		need_indicate_scan_done = _TRUE;
++		goto check_need_indicate_scan_done;
++
++	} else if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_SURVEY)) {
++		bool scan_via_buddy = rtw_cfg80211_scan_via_buddy(padapter, request);
++
++		if (scan_via_buddy == _FALSE)
++			need_indicate_scan_done = _TRUE;
++
++		goto check_need_indicate_scan_done;
++	}
++#endif /* CONFIG_CONCURRENT_MODE */
++
++#ifdef RTW_BUSY_DENY_SCAN
++	/*
++	 * busy traffic check
++	 * Rules:
++	 * 1. If (scan interval <= BUSY_TRAFFIC_SCAN_DENY_PERIOD) always allow
++	 *    scan, otherwise goto rule 2.
++	 * 2. Deny scan if any interface is busy, otherwise allow scan.
++	 */
++	if (pmlmepriv->lastscantime
++	    && (rtw_get_passing_time_ms(pmlmepriv->lastscantime) >
++		registry_par->scan_interval_thr)
++	    && rtw_mi_busy_traffic_check(padapter)) {
++		RTW_WARN(FUNC_ADPT_FMT ": scan abort!! BusyTraffic\n",
++			 FUNC_ADPT_ARG(padapter));
++ 		need_indicate_scan_done = _TRUE;
++		goto check_need_indicate_scan_done;
++	}
++#endif /* RTW_BUSY_DENY_SCAN */
++#endif
++
++#ifdef CONFIG_P2P
++	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) {
++		rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);
++
++		if (social_channel == 0)
++			rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);
++		else
++			rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_SOCIAL_LAST);
++	}
++#endif /* CONFIG_P2P */
++
++	rtw_init_sitesurvey_parm(padapter, &parm);
++
++	/* parsing request ssids, n_ssids */
++	for (i = 0; i < request->n_ssids && ssids && i < RTW_SSID_SCAN_AMOUNT; i++) {
++		#ifdef CONFIG_DEBUG_CFG80211
++		RTW_INFO("ssid=%s, len=%d\n", ssids[i].ssid, ssids[i].ssid_len);
++		#endif
++		_rtw_memcpy(&parm.ssid[i].Ssid, ssids[i].ssid, ssids[i].ssid_len);
++		parm.ssid[i].SsidLength = ssids[i].ssid_len;
++	}
++	parm.ssid_num = i;
++
++	/* no ssid entry, set the scan type as passvie */
++	if (request->n_ssids == 0)
++		parm.scan_mode = SCAN_PASSIVE;
++
++	/* parsing channels, n_channels */
++	for (i = 0; i < request->n_channels && i < RTW_CHANNEL_SCAN_AMOUNT; i++) {
++		#ifdef CONFIG_DEBUG_CFG80211
++		RTW_INFO(FUNC_ADPT_FMT CHAN_FMT"\n", FUNC_ADPT_ARG(padapter), CHAN_ARG(request->channels[i]));
++		#endif
++		parm.ch[i].hw_value = request->channels[i]->hw_value;
++		parm.ch[i].flags = request->channels[i]->flags;
++	}
++	parm.ch_num = i;
++
++	if (request->n_channels == 1) {
++		for (i = 1; i < survey_times_for_one_ch; i++)
++			_rtw_memcpy(&parm.ch[i], &parm.ch[0], sizeof(struct rtw_ieee80211_channel));
++		parm.ch_num = survey_times_for_one_ch;
++	} else if (request->n_channels <= 4) {
++		for (j = request->n_channels - 1; j >= 0; j--)
++			for (i = 0; i < survey_times; i++)
++				_rtw_memcpy(&parm.ch[j * survey_times + i], &parm.ch[j], sizeof(struct rtw_ieee80211_channel));
++		parm.ch_num = survey_times * request->n_channels;
++	}
++
++	_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++	_status = rtw_sitesurvey_cmd(padapter, &parm);
++	if (_status == _SUCCESS)
++		pwdev_priv->scan_request = request;
++	else
++		ret = -1;
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++	_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
++
++check_need_indicate_scan_done:
++	if (_TRUE == need_indicate_scan_done) {
++#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE)
++		struct cfg80211_scan_info info;
++
++		memset(&info, 0, sizeof(info));
++		info.aborted = 0;
++#endif
++		/* the process time of scan results must be over at least 1ms in the newly Android */
++		rtw_msleep_os(1); 
++
++		_rtw_cfg80211_surveydone_event_callback(padapter, request);
++#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE)
++		cfg80211_scan_done(request, &info);
++#else
++		cfg80211_scan_done(request, 0);
++#endif
++	}
++
++	if (ps_denied == _TRUE)
++		rtw_ps_deny_cancel(padapter, PS_DENY_SCAN);
++
++exit:
++#ifdef RTW_BUSY_DENY_SCAN
++	if (pmlmepriv)
++		pmlmepriv->lastscantime = rtw_get_current_time();
++#endif
++
++	return ret;
++}
++
++static int cfg80211_rtw_set_wiphy_params(struct wiphy *wiphy, u32 changed)
++{
++#if 0
++	struct iwm_priv *iwm = wiphy_to_iwm(wiphy);
++
++	if (changed & WIPHY_PARAM_RTS_THRESHOLD &&
++	    (iwm->conf.rts_threshold != wiphy->rts_threshold)) {
++		int ret;
++
++		iwm->conf.rts_threshold = wiphy->rts_threshold;
++
++		ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX,
++				CFG_RTS_THRESHOLD,
++				iwm->conf.rts_threshold);
++		if (ret < 0)
++			return ret;
++	}
++
++	if (changed & WIPHY_PARAM_FRAG_THRESHOLD &&
++	    (iwm->conf.frag_threshold != wiphy->frag_threshold)) {
++		int ret;
++
++		iwm->conf.frag_threshold = wiphy->frag_threshold;
++
++		ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_FA_CFG_FIX,
++				CFG_FRAG_THRESHOLD,
++				iwm->conf.frag_threshold);
++		if (ret < 0)
++			return ret;
++	}
++#endif
++	RTW_INFO("%s\n", __func__);
++	return 0;
++}
++
++
++
++static int rtw_cfg80211_set_wpa_version(struct security_priv *psecuritypriv, u32 wpa_version)
++{
++	RTW_INFO("%s, wpa_version=%d\n", __func__, wpa_version);
++
++	if (!wpa_version) {
++		psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;
++		return 0;
++	}
++
++
++	if (wpa_version & (NL80211_WPA_VERSION_1 | NL80211_WPA_VERSION_2))
++		psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPAPSK;
++
++#if 0
++	if (wpa_version & NL80211_WPA_VERSION_2)
++		psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK;
++#endif
++
++	#ifdef CONFIG_WAPI_SUPPORT
++	if (wpa_version & NL80211_WAPI_VERSION_1)
++		psecuritypriv->ndisauthtype = Ndis802_11AuthModeWAPI;
++	#endif
++
++	return 0;
++
++}
++
++static int rtw_cfg80211_set_auth_type(struct security_priv *psecuritypriv,
++		enum nl80211_auth_type sme_auth_type)
++{
++	RTW_INFO("%s, nl80211_auth_type=%d\n", __func__, sme_auth_type);
++
++	if (NL80211_AUTHTYPE_MAX <= (int)MLME_AUTHTYPE_SAE) {
++		if (MLME_AUTHTYPE_SAE == psecuritypriv->auth_type) {
++			/* This case pre handle in
++			 * rtw_check_connect_sae_compat()
++			 */
++			psecuritypriv->auth_alg = WLAN_AUTH_SAE;
++			return 0;
++		}
++	} else if (sme_auth_type == (int)MLME_AUTHTYPE_SAE) {
++		psecuritypriv->auth_type = MLME_AUTHTYPE_SAE;
++		psecuritypriv->auth_alg = WLAN_AUTH_SAE;
++		return 0;
++	}
++
++	psecuritypriv->auth_type = sme_auth_type;
++
++	switch (sme_auth_type) {
++	case NL80211_AUTHTYPE_AUTOMATIC:
++
++		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
++
++		break;
++	case NL80211_AUTHTYPE_OPEN_SYSTEM:
++
++		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
++
++		if (psecuritypriv->ndisauthtype > Ndis802_11AuthModeWPA)
++			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
++
++#ifdef CONFIG_WAPI_SUPPORT
++		if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWAPI)
++			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;
++#endif
++
++		break;
++	case NL80211_AUTHTYPE_SHARED_KEY:
++
++		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Shared;
++
++		psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
++
++
++		break;
++	default:
++		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
++		/* return -ENOTSUPP; */
++	}
++
++	return 0;
++
++}
++
++static int rtw_cfg80211_set_cipher(struct security_priv *psecuritypriv, u32 cipher, bool ucast)
++{
++	u32 ndisencryptstatus = Ndis802_11EncryptionDisabled;
++
++	u32 *profile_cipher = ucast ? &psecuritypriv->dot11PrivacyAlgrthm :
++		&psecuritypriv->dot118021XGrpPrivacy;
++
++	RTW_INFO("%s, ucast=%d, cipher=0x%x\n", __func__, ucast, cipher);
++
++
++	if (!cipher) {
++		*profile_cipher = _NO_PRIVACY_;
++		psecuritypriv->ndisencryptstatus = ndisencryptstatus;
++		return 0;
++	}
++
++	switch (cipher) {
++	case IW_AUTH_CIPHER_NONE:
++		*profile_cipher = _NO_PRIVACY_;
++		ndisencryptstatus = Ndis802_11EncryptionDisabled;
++#ifdef CONFIG_WAPI_SUPPORT
++		if (psecuritypriv->dot11PrivacyAlgrthm == _SMS4_)
++			*profile_cipher = _SMS4_;
++#endif
++		break;
++	case WLAN_CIPHER_SUITE_WEP40:
++		*profile_cipher = _WEP40_;
++		ndisencryptstatus = Ndis802_11Encryption1Enabled;
++		break;
++	case WLAN_CIPHER_SUITE_WEP104:
++		*profile_cipher = _WEP104_;
++		ndisencryptstatus = Ndis802_11Encryption1Enabled;
++		break;
++	case WLAN_CIPHER_SUITE_TKIP:
++		*profile_cipher = _TKIP_;
++		ndisencryptstatus = Ndis802_11Encryption2Enabled;
++		break;
++	case WLAN_CIPHER_SUITE_CCMP:
++		*profile_cipher = _AES_;
++		ndisencryptstatus = Ndis802_11Encryption3Enabled;
++		break;
++	case WIFI_CIPHER_SUITE_GCMP:
++		*profile_cipher = _GCMP_;
++		ndisencryptstatus = Ndis802_11Encryption3Enabled;
++		break;
++	case WIFI_CIPHER_SUITE_GCMP_256:
++		*profile_cipher = _GCMP_256_;
++		ndisencryptstatus = Ndis802_11Encryption3Enabled;
++		break;
++	case WIFI_CIPHER_SUITE_CCMP_256:
++		*profile_cipher = _CCMP_256_;
++		ndisencryptstatus = Ndis802_11Encryption3Enabled;
++		break;
++#ifdef CONFIG_WAPI_SUPPORT
++	case WLAN_CIPHER_SUITE_SMS4:
++		*profile_cipher = _SMS4_;
++		ndisencryptstatus = Ndis802_11_EncrypteionWAPI;
++		break;
++#endif
++	default:
++		RTW_INFO("Unsupported cipher: 0x%x\n", cipher);
++		return -ENOTSUPP;
++	}
++
++	if (ucast) {
++		psecuritypriv->ndisencryptstatus = ndisencryptstatus;
++
++		/* if(psecuritypriv->dot11PrivacyAlgrthm >= _AES_) */
++		/*	psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK; */
++	}
++
++	return 0;
++}
++
++static int rtw_cfg80211_set_key_mgt(struct security_priv *psecuritypriv, u32 key_mgt)
++{
++	RTW_INFO("%s, key_mgt=0x%x\n", __func__, key_mgt);
++
++	if (key_mgt == WLAN_AKM_SUITE_8021X) {
++		/* *auth_type = UMAC_AUTH_TYPE_8021X; */
++		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
++		psecuritypriv->rsn_akm_suite_type = 1;
++	} else if (key_mgt == WLAN_AKM_SUITE_PSK) {
++		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
++		psecuritypriv->rsn_akm_suite_type = 2;
++	}
++#ifdef CONFIG_WAPI_SUPPORT
++	else if (key_mgt == WLAN_AKM_SUITE_WAPI_PSK)
++		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;
++	else if (key_mgt == WLAN_AKM_SUITE_WAPI_CERT)
++		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;
++#endif
++#ifdef CONFIG_RTW_80211R
++	else if (key_mgt == WLAN_AKM_SUITE_FT_8021X) {
++		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
++		psecuritypriv->rsn_akm_suite_type = 3;
++	} else if (key_mgt == WLAN_AKM_SUITE_FT_PSK) {
++		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
++		psecuritypriv->rsn_akm_suite_type = 4;
++	}
++#endif
++	else if (key_mgt == WLAN_AKM_SUITE_SAE) { 
++		psecuritypriv->rsn_akm_suite_type = 8; 
++	} else {
++		RTW_INFO("Invalid key mgt: 0x%x\n", key_mgt);
++		/* return -EINVAL; */
++	}
++
++	return 0;
++}
++
++static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen)
++{
++	u8 *buf = NULL, *pos = NULL;
++	int group_cipher = 0, pairwise_cipher = 0;
++	u8 mfp_opt = MFP_NO;
++	int ret = 0;
++	int wpa_ielen = 0;
++	int wpa2_ielen = 0;
++	u8 *pwpa, *pwpa2;
++	u8 null_addr[] = {0, 0, 0, 0, 0, 0};
++
++	if (pie == NULL || !ielen) {
++		/* Treat this as normal case, but need to clear WIFI_UNDER_WPS */
++		_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
++		goto exit;
++	}
++
++	if (ielen > MAX_WPA_IE_LEN + MAX_WPS_IE_LEN + MAX_P2P_IE_LEN) {
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	buf = rtw_zmalloc(ielen);
++	if (buf == NULL) {
++		ret =  -ENOMEM;
++		goto exit;
++	}
++
++	_rtw_memcpy(buf, pie , ielen);
++
++	RTW_INFO("set wpa_ie(length:%zu):\n", ielen);
++	RTW_INFO_DUMP(NULL, buf, ielen);
++
++	pos = buf;
++	if (ielen < RSN_HEADER_LEN) {
++		ret  = -1;
++		goto exit;
++	}
++
++	pwpa = rtw_get_wpa_ie(buf, &wpa_ielen, ielen);
++	if (pwpa && wpa_ielen > 0) {
++		if (rtw_parse_wpa_ie(pwpa, wpa_ielen + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {
++			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
++			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK;
++			_rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa[0], wpa_ielen + 2);
++
++			RTW_INFO("got wpa_ie, wpa_ielen:%u\n", wpa_ielen);
++		}
++	}
++
++	pwpa2 = rtw_get_wpa2_ie(buf, &wpa2_ielen, ielen);
++	if (pwpa2 && wpa2_ielen > 0) {
++		if (rtw_parse_wpa2_ie(pwpa2, wpa2_ielen + 2, &group_cipher, &pairwise_cipher, NULL, NULL, &mfp_opt) == _SUCCESS) {
++			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
++			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK;
++			_rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa2[0], wpa2_ielen + 2);
++
++			RTW_INFO("got wpa2_ie, wpa2_ielen:%u\n", wpa2_ielen);
++		}
++	}
++
++	if (group_cipher == 0)
++		group_cipher = WPA_CIPHER_NONE;
++	if (pairwise_cipher == 0)
++		pairwise_cipher = WPA_CIPHER_NONE;
++
++	switch (group_cipher) {
++	case WPA_CIPHER_NONE:
++		padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
++		break;
++	case WPA_CIPHER_WEP40:
++		padapter->securitypriv.dot118021XGrpPrivacy = _WEP40_;
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++		break;
++	case WPA_CIPHER_TKIP:
++		padapter->securitypriv.dot118021XGrpPrivacy = _TKIP_;
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
++		break;
++	case WPA_CIPHER_CCMP:
++		padapter->securitypriv.dot118021XGrpPrivacy = _AES_;
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
++		break;
++	case WPA_CIPHER_GCMP:
++		padapter->securitypriv.dot118021XGrpPrivacy = _GCMP_;
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
++		break;
++	case WPA_CIPHER_GCMP_256:
++		padapter->securitypriv.dot118021XGrpPrivacy = _GCMP_256_;
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
++		break;
++	case WPA_CIPHER_CCMP_256:
++		padapter->securitypriv.dot118021XGrpPrivacy = _CCMP_256_;
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
++		break;
++	case WPA_CIPHER_WEP104:
++		padapter->securitypriv.dot118021XGrpPrivacy = _WEP104_;
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++		break;
++	}
++
++	switch (pairwise_cipher) {
++	case WPA_CIPHER_NONE:
++		padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
++		break;
++	case WPA_CIPHER_WEP40:
++		padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_;
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++		break;
++	case WPA_CIPHER_TKIP:
++		padapter->securitypriv.dot11PrivacyAlgrthm = _TKIP_;
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
++		break;
++	case WPA_CIPHER_CCMP:
++		padapter->securitypriv.dot11PrivacyAlgrthm = _AES_;
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
++		break;
++	case WPA_CIPHER_GCMP:
++		padapter->securitypriv.dot11PrivacyAlgrthm = _GCMP_;
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
++		break;
++	case WPA_CIPHER_GCMP_256:
++		padapter->securitypriv.dot11PrivacyAlgrthm = _GCMP_256_;
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
++		break;
++	case WPA_CIPHER_CCMP_256:
++		padapter->securitypriv.dot11PrivacyAlgrthm = _CCMP_256_;
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
++		break;
++	case WPA_CIPHER_WEP104:
++		padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++		break;
++	}
++
++	if (mfp_opt == MFP_INVALID) {
++		RTW_INFO(FUNC_ADPT_FMT" invalid MFP setting\n", FUNC_ADPT_ARG(padapter));
++		ret = -EINVAL;
++		goto exit;
++	}
++	padapter->securitypriv.mfp_opt = mfp_opt;
++
++	{/* handle wps_ie */
++		uint wps_ielen;
++		u8 *wps_ie;
++
++		wps_ie = rtw_get_wps_ie(buf, ielen, NULL, &wps_ielen);
++		if (wps_ie && wps_ielen > 0) {
++			RTW_INFO("got wps_ie, wps_ielen:%u\n", wps_ielen);
++			padapter->securitypriv.wps_ie_len = wps_ielen < MAX_WPS_IE_LEN ? wps_ielen : MAX_WPS_IE_LEN;
++			_rtw_memcpy(padapter->securitypriv.wps_ie, wps_ie, padapter->securitypriv.wps_ie_len);
++			set_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS);
++		} else
++			_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
++	}
++
++	{/* handle owe_ie */
++		uint owe_ielen;
++		u8 *owe_ie;
++
++		owe_ie = rtw_get_owe_ie(buf, ielen, NULL, &owe_ielen);
++		if (owe_ie && owe_ielen > 0) {
++			RTW_INFO("got owe_ie, owe_ielen:%u\n", owe_ielen);
++			padapter->securitypriv.owe_ie_len = owe_ielen < MAX_OWE_IE_LEN ? owe_ielen : MAX_OWE_IE_LEN;
++			_rtw_memcpy(padapter->securitypriv.owe_ie, owe_ie, padapter->securitypriv.owe_ie_len);
++		}
++	}
++
++	#ifdef CONFIG_P2P
++	{/* check p2p_ie for assoc req; */
++		uint p2p_ielen = 0;
++		u8 *p2p_ie;
++		struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++		p2p_ie = rtw_get_p2p_ie(buf, ielen, NULL, &p2p_ielen);
++		if (p2p_ie) {
++			#ifdef CONFIG_DEBUG_CFG80211
++			RTW_INFO("%s p2p_assoc_req_ielen=%d\n", __FUNCTION__, p2p_ielen);
++			#endif
++
++			if (pmlmepriv->p2p_assoc_req_ie) {
++				u32 free_len = pmlmepriv->p2p_assoc_req_ie_len;
++				pmlmepriv->p2p_assoc_req_ie_len = 0;
++				rtw_mfree(pmlmepriv->p2p_assoc_req_ie, free_len);
++				pmlmepriv->p2p_assoc_req_ie = NULL;
++			}
++
++			pmlmepriv->p2p_assoc_req_ie = rtw_malloc(p2p_ielen);
++			if (pmlmepriv->p2p_assoc_req_ie == NULL) {
++				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++				goto exit;
++			}
++			_rtw_memcpy(pmlmepriv->p2p_assoc_req_ie, p2p_ie, p2p_ielen);
++			pmlmepriv->p2p_assoc_req_ie_len = p2p_ielen;
++		}
++	}
++	#endif /* CONFIG_P2P */
++
++	#ifdef CONFIG_WFD
++	{
++		uint wfd_ielen = 0;
++		u8 *wfd_ie;
++		struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++		wfd_ie = rtw_get_wfd_ie(buf, ielen, NULL, &wfd_ielen);
++		if (wfd_ie) {
++			#ifdef CONFIG_DEBUG_CFG80211
++			RTW_INFO("%s wfd_assoc_req_ielen=%d\n", __FUNCTION__, wfd_ielen);
++			#endif
++
++			if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_ASSOC_REQ_IE, wfd_ie, wfd_ielen) != _SUCCESS)
++				goto exit;
++		}
++	}
++	#endif /* CONFIG_WFD */
++
++	#ifdef CONFIG_RTW_MULTI_AP
++	padapter->multi_ap = rtw_get_multi_ap_ie_ext(buf, ielen) & MULTI_AP_BACKHAUL_STA;
++	if (padapter->multi_ap)
++		adapter_set_use_wds(padapter, 1);
++	#endif
++
++	/* TKIP and AES disallow multicast packets until installing group key */
++	if (padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_
++		|| padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_
++		|| padapter->securitypriv.dot11PrivacyAlgrthm == _AES_
++		|| padapter->securitypriv.dot11PrivacyAlgrthm == _GCMP_
++		|| padapter->securitypriv.dot11PrivacyAlgrthm == _GCMP_256_
++		|| padapter->securitypriv.dot11PrivacyAlgrthm == _CCMP_256_)
++		/* WPS open need to enable multicast */
++		/* || check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE) */
++		rtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr);
++
++
++exit:
++	if (buf)
++		rtw_mfree(buf, ielen);
++	if (ret)
++		_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
++
++	return ret;
++}
++
++static int cfg80211_rtw_join_ibss(struct wiphy *wiphy, struct net_device *ndev,
++				  struct cfg80211_ibss_params *params)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	NDIS_802_11_SSID ndis_ssid;
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	struct cfg80211_chan_def *pch_def;
++#endif
++	struct ieee80211_channel *pch;
++	int ret = 0;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	pch_def = (struct cfg80211_chan_def *)(&params->chandef);
++	pch = (struct ieee80211_channel *) pch_def->chan;
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
++	pch = (struct ieee80211_channel *)(params->channel);
++#endif
++
++	if (!params->ssid || !params->ssid_len) {
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	if (params->ssid_len > IW_ESSID_MAX_SIZE) {
++		ret = -E2BIG;
++		goto exit;
++	}
++
++	rtw_ps_deny(padapter, PS_DENY_JOIN);
++	if (_FAIL == rtw_pwr_wakeup(padapter)) {
++		ret = -EPERM;
++		goto cancel_ps_deny;
++	}
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING)) {
++		RTW_INFO("%s, but buddy_intf is under linking\n", __FUNCTION__);
++		ret = -EINVAL;
++		goto cancel_ps_deny;
++	}
++	rtw_mi_buddy_scan_abort(padapter, _TRUE); /* OR rtw_mi_scan_abort(padapter, _TRUE);*/
++#endif /*CONFIG_CONCURRENT_MODE*/
++
++
++	_rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID));
++	ndis_ssid.SsidLength = params->ssid_len;
++	_rtw_memcpy(ndis_ssid.Ssid, (u8 *)params->ssid, params->ssid_len);
++
++	/* RTW_INFO("ssid=%s, len=%zu\n", ndis_ssid.Ssid, params->ssid_len); */
++
++	psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled;
++	psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
++	psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
++	psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
++	psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;
++
++	ret = rtw_cfg80211_set_auth_type(psecuritypriv, NL80211_AUTHTYPE_OPEN_SYSTEM);
++	rtw_set_802_11_authentication_mode(padapter, psecuritypriv->ndisauthtype);
++
++	RTW_INFO("%s: center_freq = %d\n", __func__, pch->center_freq);
++	pmlmeext->cur_channel = rtw_freq2ch(pch->center_freq);
++
++	if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) {
++		ret = -1;
++		goto cancel_ps_deny;
++	}
++
++cancel_ps_deny:
++	rtw_ps_deny_cancel(padapter, PS_DENY_JOIN);
++exit:
++	return ret;
++}
++
++static int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *ndev)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct wireless_dev *rtw_wdev = padapter->rtw_wdev;
++	enum nl80211_iftype old_type;
++	int ret = 0;
++
++	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)
++	rtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 1);
++#endif
++
++	old_type = rtw_wdev->iftype;
++
++	rtw_set_to_roam(padapter, 0);
++
++	if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) {
++		rtw_scan_abort(padapter);
++		LeaveAllPowerSaveMode(padapter);
++
++		rtw_wdev->iftype = NL80211_IFTYPE_STATION;
++
++		if (rtw_set_802_11_infrastructure_mode(padapter, Ndis802_11Infrastructure, 0) == _FALSE) {
++			rtw_wdev->iftype = old_type;
++			ret = -EPERM;
++			goto leave_ibss;
++		}
++		rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK);
++	}
++
++leave_ibss:
++#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)
++	rtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 0);
++#endif
++
++	return 0;
++}
++
++bool rtw_cfg80211_is_connect_requested(_adapter *adapter)
++{
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
++	_irqL irqL;
++	bool requested;
++
++	_enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
++	requested = pwdev_priv->connect_req ? 1 : 0;
++	_exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
++
++	return requested;
++}
++
++static int _rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++
++
++	/* if(check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) */
++	{
++		rtw_scan_abort(padapter);
++		rtw_join_abort_timeout(padapter, 300);
++		LeaveAllPowerSaveMode(padapter);
++		rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK);
++#ifdef CONFIG_RTW_REPEATER_SON
++		rtw_rson_do_disconnect(padapter);
++#endif
++		RTW_INFO("%s...call rtw_indicate_disconnect\n", __func__);
++
++		rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK);
++
++		/* indicate locally_generated = 0 when suspend */
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0))
++		rtw_indicate_disconnect(padapter, 0, wiphy->dev.power.is_prepared ? _FALSE : _TRUE);
++		#else
++		/*
++		* for kernel < 4.2, DISCONNECT event is hardcoded with
++		* NL80211_ATTR_DISCONNECTED_BY_AP=1 in NL80211 layer
++		* no need to judge if under suspend
++		*/
++		rtw_indicate_disconnect(padapter, 0, _TRUE);
++		#endif
++
++		rtw_pwr_wakeup(padapter);
++	}
++	return 0;
++}
++
++#if (KERNEL_VERSION(4, 17, 0) > LINUX_VERSION_CODE)
++static bool rtw_check_connect_sae_compat(struct cfg80211_connect_params *sme)
++{
++	struct rtw_ieee802_11_elems elems;
++	struct rsne_info info;
++	u8 AKM_SUITE_SAE[] = { 0x00, 0x0f, 0xac, 8 };
++	int i;
++
++	if (sme->auth_type != (int)MLME_AUTHTYPE_SHARED_KEY)
++		return false;
++
++	if (rtw_ieee802_11_parse_elems((u8 *)sme->ie, sme->ie_len, &elems, 0)
++	    == ParseFailed)
++		return false;
++
++	if (!elems.rsn_ie)
++		return false;
++
++	if (rtw_rsne_info_parse(elems.rsn_ie - 2, elems.rsn_ie_len + 2, &info) == _FAIL)
++		return false;
++
++	for (i = 0; i < info.akm_cnt; i++)
++		if (memcmp(info.akm_list + i * RSN_SELECTOR_LEN,
++			   AKM_SUITE_SAE, RSN_SELECTOR_LEN) == 0)
++			return true;
++
++	return false;
++}
++#else
++#define rtw_check_connect_sae_compat(sme)	false
++#endif
++
++static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev,
++				struct cfg80211_connect_params *sme)
++{
++	int ret = 0;
++	NDIS_802_11_AUTHENTICATION_MODE authmode;
++	NDIS_802_11_SSID ndis_ssid;
++	/* u8 matched_by_bssid=_FALSE; */
++	/* u8 matched_by_ssid=_FALSE; */
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	_irqL irqL;
++
++#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT)
++	rtw_wdev_set_not_indic_disco(pwdev_priv, 1);
++#endif
++
++	RTW_INFO("=>"FUNC_NDEV_FMT" - Start to Connection\n", FUNC_NDEV_ARG(ndev));
++	RTW_INFO("privacy=%d, key=%p, key_len=%d, key_idx=%d, auth_type=%d\n",
++		sme->privacy, sme->key, sme->key_len, sme->key_idx, sme->auth_type);
++
++	if (rtw_check_connect_sae_compat(sme)) {
++		sme->auth_type = MLME_AUTHTYPE_SAE;
++		psecuritypriv->auth_type = MLME_AUTHTYPE_SAE;
++		psecuritypriv->auth_alg = WLAN_AUTH_SAE;
++		RTW_INFO("%s set sme->auth_type for SAE compat\n", __FUNCTION__);
++	}
++
++	if (pwdev_priv->block == _TRUE) {
++		ret = -EBUSY;
++		RTW_INFO("%s wdev_priv.block is set\n", __FUNCTION__);
++		goto exit;
++	}
++
++       if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_UNDER_LINKING) == _TRUE) {
++
++		_rtw_disconnect(wiphy, ndev);
++		RTW_INFO("%s disconnect before connecting! fw_state=0x%x\n",
++			__FUNCTION__, pmlmepriv->fw_state);
++	}
++
++#ifdef CONFIG_PLATFORM_MSTAR_SCAN_BEFORE_CONNECT
++	printk("MStar Android!\n");
++	if (pwdev_priv->bandroid_scan == _FALSE) {
++#ifdef CONFIG_P2P
++		struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++#endif /* CONFIG_P2P */
++		{
++			ret = -EBUSY;
++			printk("Android hasn't attached yet!\n");
++			goto exit;
++		}
++	}
++#endif
++
++	if (!sme->ssid || !sme->ssid_len) {
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	if (sme->ssid_len > IW_ESSID_MAX_SIZE) {
++		ret = -E2BIG;
++		goto exit;
++	}
++
++	rtw_ps_deny(padapter, PS_DENY_JOIN);
++	if (_FAIL == rtw_pwr_wakeup(padapter)) {
++		ret = -EPERM;
++		goto cancel_ps_deny;
++	}
++
++	rtw_mi_scan_abort(padapter, _TRUE);
++
++	rtw_join_abort_timeout(padapter, 300);
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING)) {
++		ret = -EINVAL;
++		goto cancel_ps_deny;
++	}
++#endif
++
++	_rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID));
++	ndis_ssid.SsidLength = sme->ssid_len;
++	_rtw_memcpy(ndis_ssid.Ssid, (u8 *)sme->ssid, sme->ssid_len);
++
++	RTW_INFO("ssid=%s, len=%zu\n", ndis_ssid.Ssid, sme->ssid_len);
++
++
++	if (sme->bssid)
++		RTW_INFO("bssid="MAC_FMT"\n", MAC_ARG(sme->bssid));
++
++
++	psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled;
++	psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
++	psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
++	psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
++	psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;
++	psecuritypriv->auth_alg = WLAN_AUTH_OPEN;
++	psecuritypriv->extauth_status = WLAN_STATUS_UNSPECIFIED_FAILURE;
++
++#ifdef CONFIG_WAPI_SUPPORT
++	padapter->wapiInfo.bWapiEnable = false;
++#endif
++
++	ret = rtw_cfg80211_set_wpa_version(psecuritypriv, sme->crypto.wpa_versions);
++	if (ret < 0)
++		goto cancel_ps_deny;
++
++#ifdef CONFIG_WAPI_SUPPORT
++	if (sme->crypto.wpa_versions & NL80211_WAPI_VERSION_1) {
++		padapter->wapiInfo.bWapiEnable = true;
++		padapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN;
++		padapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN;
++	}
++#endif
++
++	ret = rtw_cfg80211_set_auth_type(psecuritypriv, sme->auth_type);
++
++#ifdef CONFIG_WAPI_SUPPORT
++	if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_WAPI)
++		padapter->mlmeextpriv.mlmext_info.auth_algo = psecuritypriv->dot11AuthAlgrthm;
++#endif
++
++
++	if (ret < 0)
++		goto cancel_ps_deny;
++
++	RTW_INFO("%s, ie_len=%zu\n", __func__, sme->ie_len);
++
++	ret = rtw_cfg80211_set_wpa_ie(padapter, (u8 *)sme->ie, sme->ie_len);
++	if (ret < 0)
++		goto cancel_ps_deny;
++
++	if (sme->crypto.n_ciphers_pairwise) {
++		ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.ciphers_pairwise[0], _TRUE);
++		if (ret < 0)
++			goto cancel_ps_deny;
++	}
++
++	/* For WEP Shared auth */
++	if (sme->key_len > 0 && sme->key) {
++		u32 wep_key_idx, wep_key_len, wep_total_len;
++		NDIS_802_11_WEP	*pwep = NULL;
++		RTW_INFO("%s(): Shared/Auto WEP\n", __FUNCTION__);
++
++		wep_key_idx = sme->key_idx;
++		wep_key_len = sme->key_len;
++
++		if (sme->key_idx > WEP_KEYS) {
++			ret = -EINVAL;
++			goto cancel_ps_deny;
++		}
++
++		if (wep_key_len > 0) {
++			wep_key_len = wep_key_len <= 5 ? 5 : 13;
++			wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial);
++			pwep = (NDIS_802_11_WEP *) rtw_malloc(wep_total_len);
++			if (pwep == NULL) {
++				RTW_INFO(" wpa_set_encryption: pwep allocate fail !!!\n");
++				ret = -ENOMEM;
++				goto cancel_ps_deny;
++			}
++
++			_rtw_memset(pwep, 0, wep_total_len);
++
++			pwep->KeyLength = wep_key_len;
++			pwep->Length = wep_total_len;
++
++			if (wep_key_len == 13) {
++				padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;
++				padapter->securitypriv.dot118021XGrpPrivacy = _WEP104_;
++			}
++		} else {
++			ret = -EINVAL;
++			goto cancel_ps_deny;
++		}
++
++		pwep->KeyIndex = wep_key_idx;
++		pwep->KeyIndex |= 0x80000000;
++
++		_rtw_memcpy(pwep->KeyMaterial, (void *)sme->key, pwep->KeyLength);
++
++		if (rtw_set_802_11_add_wep(padapter, pwep) == (u8)_FAIL)
++			ret = -EOPNOTSUPP ;
++
++		if (pwep)
++			rtw_mfree((u8 *)pwep, wep_total_len);
++
++		if (ret < 0)
++			goto cancel_ps_deny;
++	}
++
++	ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.cipher_group, _FALSE);
++	if (ret < 0)
++		return ret;
++
++	if (sme->crypto.n_akm_suites) {
++		ret = rtw_cfg80211_set_key_mgt(psecuritypriv, sme->crypto.akm_suites[0]);
++		if (ret < 0)
++			goto cancel_ps_deny;
++	}
++#ifdef CONFIG_8011R
++	else {
++		/*It could be a connection without RSN IEs*/
++		psecuritypriv->rsn_akm_suite_type = 0;
++	}
++#endif
++
++#ifdef CONFIG_WAPI_SUPPORT
++	if (sme->crypto.akm_suites[0] == WLAN_AKM_SUITE_WAPI_PSK)
++		padapter->wapiInfo.bWapiPSK = true;
++	else if (sme->crypto.akm_suites[0] == WLAN_AKM_SUITE_WAPI_CERT)
++		padapter->wapiInfo.bWapiPSK = false;
++#endif
++
++	authmode = psecuritypriv->ndisauthtype;
++	rtw_set_802_11_authentication_mode(padapter, authmode);
++
++	/* rtw_set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */
++
++#ifdef CONFIG_RTW_MBO
++	rtw_mbo_update_ie_data(padapter, (u8 *)sme->ie, sme->ie_len);
++#endif
++
++	if (rtw_set_802_11_connect(padapter, (u8 *)sme->bssid, &ndis_ssid, \
++			sme->channel ? sme->channel->hw_value : 0) == _FALSE) {
++		ret = -1;
++		goto cancel_ps_deny;
++	}
++
++
++	_enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
++
++	if (pwdev_priv->connect_req) {
++		rtw_wdev_free_connect_req(pwdev_priv);
++		RTW_INFO(FUNC_NDEV_FMT" free existing connect_req\n", FUNC_NDEV_ARG(ndev));
++	}
++
++	pwdev_priv->connect_req = (struct cfg80211_connect_params *)rtw_malloc(sizeof(*pwdev_priv->connect_req));
++	if (pwdev_priv->connect_req)
++		_rtw_memcpy(pwdev_priv->connect_req, sme, sizeof(*pwdev_priv->connect_req));
++	else
++		RTW_WARN(FUNC_NDEV_FMT" alloc connect_req fail\n", FUNC_NDEV_ARG(ndev));
++
++	_exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
++
++	RTW_INFO("set ssid:dot11AuthAlgrthm=%d, dot11PrivacyAlgrthm=%d, dot118021XGrpPrivacy=%d\n", psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm,
++		psecuritypriv->dot118021XGrpPrivacy);
++
++cancel_ps_deny:
++	rtw_ps_deny_cancel(padapter, PS_DENY_JOIN);
++
++exit:
++	RTW_INFO("<=%s, ret %d\n", __FUNCTION__, ret);
++
++#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT)
++	rtw_wdev_set_not_indic_disco(pwdev_priv, 0);
++#endif
++
++	return ret;
++}
++
++static int cfg80211_rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev,
++				   u16 reason_code)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++
++	RTW_INFO(FUNC_NDEV_FMT" - Start to Disconnect\n", FUNC_NDEV_ARG(ndev));
++
++#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++	if (!wiphy->dev.power.is_prepared)
++	#endif
++		rtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 1);
++#endif
++
++	rtw_set_to_roam(padapter, 0);
++
++	/* if(check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) */
++	{
++		_rtw_disconnect(wiphy, ndev);
++	}
++
++#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)
++	rtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 0);
++#endif
++
++	RTW_INFO(FUNC_NDEV_FMT" return 0\n", FUNC_NDEV_ARG(ndev));
++	return 0;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
++static const char *nl80211_tx_power_setting_str(int type)
++{
++	switch (type) {
++	case NL80211_TX_POWER_AUTOMATIC:
++		return "AUTO";
++	case NL80211_TX_POWER_LIMITED:
++		return "LIMIT";
++	case NL80211_TX_POWER_FIXED:
++		return "FIX";
++	default:
++		return "UNKNOWN";
++	};
++}
++
++static int cfg80211_rtw_set_txpower(struct wiphy *wiphy,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	struct wireless_dev *wdev,
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) || defined(COMPAT_KERNEL_RELEASE)
++	enum nl80211_tx_power_setting type, int mbm)
++#else
++	enum tx_power_setting type, int dbm)
++#endif
++{
++#if !((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) || defined(COMPAT_KERNEL_RELEASE))
++	int mbm = dbm * 100;
++#endif
++	struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy);
++	_adapter *adapter = wiphy_to_adapter(wiphy);
++	int ret = -EOPNOTSUPP;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	if (wdev) {
++		RTW_WARN(FUNC_WIPHY_FMT" wdev specific control is not supported\n", FUNC_WIPHY_ARG(wiphy));
++		goto exit;
++	}
++#endif
++
++	RTW_INFO(FUNC_WIPHY_FMT" type:%s(%u) mbm:%d\n", FUNC_WIPHY_ARG(wiphy)
++		, nl80211_tx_power_setting_str(type), type, mbm);
++
++	switch (type) {
++	case NL80211_TX_POWER_AUTOMATIC:
++		wiphy_data->txpwr_total_lmt_mbm = UNSPECIFIED_MBM;
++		wiphy_data->txpwr_total_target_mbm = UNSPECIFIED_MBM;
++		ret = 0;
++		break;
++	case NL80211_TX_POWER_LIMITED:
++		if (!phy_is_txpwr_user_mbm_valid(adapter, mbm)) {
++			RTW_WARN(FUNC_WIPHY_FMT" mbm:%d not support\n", FUNC_WIPHY_ARG(wiphy), mbm);
++			goto exit;
++		}
++		wiphy_data->txpwr_total_lmt_mbm = mbm;
++		wiphy_data->txpwr_total_target_mbm = UNSPECIFIED_MBM;
++		ret = 0;
++		break;
++	case NL80211_TX_POWER_FIXED:
++		if (!phy_is_txpwr_user_mbm_valid(adapter, mbm)) {
++			RTW_WARN(FUNC_WIPHY_FMT" mbm:%d not support\n", FUNC_WIPHY_ARG(wiphy), mbm);
++			goto exit;
++		}
++		wiphy_data->txpwr_total_lmt_mbm = UNSPECIFIED_MBM;
++		wiphy_data->txpwr_total_target_mbm = mbm;
++		ret = 0;
++		break;
++	default:
++		RTW_WARN(FUNC_WIPHY_FMT" unknown type:%d\n", FUNC_WIPHY_ARG(wiphy), type);
++	}
++
++	if (ret == 0)
++		rtw_run_in_thread_cmd_wait(adapter, ((void *)(rtw_hal_update_txpwr_level)), adapter, 2000);
++
++exit:
++	return ret;
++}
++
++static int cfg80211_rtw_get_txpower(struct wiphy *wiphy,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	struct wireless_dev *wdev,
++#endif
++	int *dbm)
++{
++	struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);
++	s16 mbm;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	if (wdev && wdev_to_ndev(wdev)) {
++		_adapter *adapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));
++		mbm = rtw_adapter_get_oper_txpwr_max_mbm(adapter);
++		RTW_INFO(FUNC_ADPT_FMT" total max: %d mbm\n", FUNC_ADPT_ARG(adapter), mbm);
++	} else
++#endif
++	{
++		mbm = rtw_get_oper_txpwr_max_mbm(dvobj);
++		RTW_INFO(FUNC_WIPHY_FMT" total max: %d mbm\n", FUNC_WIPHY_ARG(wiphy), mbm);
++	}
++
++	*dbm = mbm / MBM_PDBM;
++
++	return 0;
++}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31)) */
++
++inline bool rtw_cfg80211_pwr_mgmt(_adapter *adapter)
++{
++	struct rtw_wdev_priv *rtw_wdev_priv = adapter_wdev_data(adapter);
++	return rtw_wdev_priv->power_mgmt;
++}
++
++static int cfg80211_rtw_set_power_mgmt(struct wiphy *wiphy,
++				       struct net_device *ndev,
++				       bool enabled, int timeout)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct rtw_wdev_priv *rtw_wdev_priv = adapter_wdev_data(padapter);
++
++	RTW_INFO(FUNC_NDEV_FMT" enabled:%u, timeout:%d\n", FUNC_NDEV_ARG(ndev),
++		enabled, timeout);
++
++	rtw_wdev_priv->power_mgmt = enabled;
++
++#ifdef CONFIG_LPS
++	if (!enabled)
++		rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE_CFG80211_PWRMGMT, 0);
++#endif
++
++	return 0;
++}
++
++static void _rtw_set_pmksa(struct net_device *ndev,
++	u8 *bssid, u8 *pmkid)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	u8 index, blInserted = _FALSE;
++
++	/* overwrite PMKID */
++	for (index = 0 ; index < NUM_PMKID_CACHE; index++) {
++		if (_rtw_memcmp(psecuritypriv->PMKIDList[index].Bssid, bssid, ETH_ALEN) == _TRUE) {
++			/* BSSID is matched, the same AP => rewrite with new PMKID. */
++			RTW_INFO("BSSID("MAC_FMT") exists in the PMKList.\n", MAC_ARG(bssid));
++
++			_rtw_memcpy(psecuritypriv->PMKIDList[index].PMKID, pmkid, WLAN_PMKID_LEN);
++			psecuritypriv->PMKIDList[index].bUsed = _TRUE;
++			psecuritypriv->PMKIDIndex = index + 1;
++			blInserted = _TRUE;
++			break;
++		}
++	}
++
++	if (!blInserted) {
++		/* Find a new entry */
++		RTW_INFO("Use the new entry index = %d for this PMKID.\n",
++			psecuritypriv->PMKIDIndex);
++
++		_rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, bssid, ETH_ALEN);
++		_rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, pmkid, WLAN_PMKID_LEN);
++
++		psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].bUsed = _TRUE;
++		psecuritypriv->PMKIDIndex++ ;
++		if (psecuritypriv->PMKIDIndex == 16)
++			psecuritypriv->PMKIDIndex = 0;
++	}
++}
++
++static int cfg80211_rtw_set_pmksa(struct wiphy *wiphy,
++				  struct net_device *ndev,
++				  struct cfg80211_pmksa *pmksa)
++{
++	u8	index, blInserted = _FALSE;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct mlme_priv *mlme = &padapter->mlmepriv;
++	struct security_priv	*psecuritypriv = &padapter->securitypriv;
++	u8	strZeroMacAddress[ETH_ALEN] = { 0x00 };
++	bool sae_auth = rtw_sec_chk_auth_type(padapter, MLME_AUTHTYPE_SAE);
++
++	RTW_INFO(FUNC_NDEV_FMT" "MAC_FMT" "KEY_FMT"\n", FUNC_NDEV_ARG(ndev)
++		, MAC_ARG(pmksa->bssid), KEY_ARG(pmksa->pmkid));
++
++	if (_rtw_memcmp((u8 *)pmksa->bssid, strZeroMacAddress, ETH_ALEN) == _TRUE)
++		return -EINVAL;
++
++	if (check_fwstate(mlme, WIFI_ASOC_STATE) == _FALSE && !sae_auth) {
++		RTW_INFO(FUNC_NDEV_FMT" not set pmksa cause not in linked state\n", FUNC_NDEV_ARG(ndev));
++		return -EINVAL;
++	}
++
++	_rtw_set_pmksa(ndev, (u8 *)pmksa->bssid, (u8 *)pmksa->pmkid);
++
++	if (sae_auth &&
++		(psecuritypriv->extauth_status == WLAN_STATUS_SUCCESS)) {
++		RTW_PRINT("SAE: auth success, start assoc\n");
++		start_clnt_assoc(padapter);
++	}
++
++	return 0;
++}
++
++static int cfg80211_rtw_del_pmksa(struct wiphy *wiphy,
++				  struct net_device *ndev,
++				  struct cfg80211_pmksa *pmksa)
++{
++	u8	index, bMatched = _FALSE;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct security_priv	*psecuritypriv = &padapter->securitypriv;
++
++	RTW_INFO(FUNC_NDEV_FMT" "MAC_FMT" "KEY_FMT"\n", FUNC_NDEV_ARG(ndev)
++		, MAC_ARG(pmksa->bssid), KEY_ARG(pmksa->pmkid));
++
++	for (index = 0 ; index < NUM_PMKID_CACHE; index++) {
++		if (_rtw_memcmp(psecuritypriv->PMKIDList[index].Bssid, (u8 *)pmksa->bssid, ETH_ALEN) == _TRUE) {
++			/* BSSID is matched, the same AP => Remove this PMKID information and reset it. */
++			_rtw_memset(psecuritypriv->PMKIDList[index].Bssid, 0x00, ETH_ALEN);
++			_rtw_memset(psecuritypriv->PMKIDList[index].PMKID, 0x00, WLAN_PMKID_LEN);
++			psecuritypriv->PMKIDList[index].bUsed = _FALSE;
++			bMatched = _TRUE;
++			RTW_INFO(FUNC_NDEV_FMT" clear id:%hhu\n", FUNC_NDEV_ARG(ndev), index);
++			break;
++		}
++	}
++
++	if (_FALSE == bMatched) {
++		RTW_INFO(FUNC_NDEV_FMT" do not have matched BSSID\n"
++			, FUNC_NDEV_ARG(ndev));
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int cfg80211_rtw_flush_pmksa(struct wiphy *wiphy,
++				    struct net_device *ndev)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct security_priv	*psecuritypriv = &padapter->securitypriv;
++
++	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++	_rtw_memset(&psecuritypriv->PMKIDList[0], 0x00, sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);
++	psecuritypriv->PMKIDIndex = 0;
++
++	return 0;
++}
++
++#ifdef CONFIG_AP_MODE
++void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len)
++{
++#if !defined(RTW_USE_CFG80211_STA_EVENT) && !defined(COMPAT_KERNEL_RELEASE)
++	s32 freq;
++	int channel;
++	struct wireless_dev *pwdev = padapter->rtw_wdev;
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++#endif
++	struct net_device *ndev = padapter->pnetdev;
++
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE)
++	{
++		struct station_info sinfo;
++		u8 ie_offset;
++		if (get_frame_sub_type(pmgmt_frame) == WIFI_ASSOCREQ)
++			ie_offset = _ASOCREQ_IE_OFFSET_;
++		else /* WIFI_REASSOCREQ */
++			ie_offset = _REASOCREQ_IE_OFFSET_;
++
++		memset(&sinfo, 0, sizeof(sinfo));
++		sinfo.filled = STATION_INFO_ASSOC_REQ_IES;
++		sinfo.assoc_req_ies = pmgmt_frame + WLAN_HDR_A3_LEN + ie_offset;
++		sinfo.assoc_req_ies_len = frame_len - WLAN_HDR_A3_LEN - ie_offset;
++		cfg80211_new_sta(ndev, get_addr2_ptr(pmgmt_frame), &sinfo, GFP_ATOMIC);
++	}
++#else /* defined(RTW_USE_CFG80211_STA_EVENT) */
++	channel = pmlmeext->cur_channel;
++	freq = rtw_ch2freq(channel);
++
++	#ifdef COMPAT_KERNEL_RELEASE
++	rtw_cfg80211_rx_mgmt(pwdev, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC);
++	#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
++	rtw_cfg80211_rx_mgmt(pwdev, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC);
++	#else /* COMPAT_KERNEL_RELEASE */
++	{
++		/* to avoid WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION)  when calling cfg80211_send_rx_assoc() */
++		#ifndef CONFIG_PLATFORM_MSTAR
++		pwdev->iftype = NL80211_IFTYPE_STATION;
++		#endif /* CONFIG_PLATFORM_MSTAR */
++		RTW_INFO("iftype=%d before call cfg80211_send_rx_assoc()\n", pwdev->iftype);
++		rtw_cfg80211_send_rx_assoc(padapter, NULL, pmgmt_frame, frame_len);
++		RTW_INFO("iftype=%d after call cfg80211_send_rx_assoc()\n", pwdev->iftype);
++		pwdev->iftype = NL80211_IFTYPE_AP;
++		/* cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); */
++	}
++	#endif /* COMPAT_KERNEL_RELEASE */
++#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */
++
++}
++
++void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, const u8 *da, unsigned short reason)
++{
++#if !defined(RTW_USE_CFG80211_STA_EVENT) && !defined(COMPAT_KERNEL_RELEASE)
++	s32 freq;
++	int channel;
++	u8 *pmgmt_frame;
++	uint frame_len;
++	struct rtw_ieee80211_hdr *pwlanhdr;
++	unsigned short *fctrl;
++	u8 mgmt_buf[128] = {0};
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct wireless_dev *wdev = padapter->rtw_wdev;
++#endif
++	struct net_device *ndev = padapter->pnetdev;
++
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE)
++	cfg80211_del_sta(ndev, da, GFP_ATOMIC);
++#else /* defined(RTW_USE_CFG80211_STA_EVENT) */
++	channel = pmlmeext->cur_channel;
++	freq = rtw_ch2freq(channel);
++
++	pmgmt_frame = mgmt_buf;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pmgmt_frame;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, da, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pmgmt_frame, WIFI_DEAUTH);
++
++	pmgmt_frame += sizeof(struct rtw_ieee80211_hdr_3addr);
++	frame_len = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	reason = cpu_to_le16(reason);
++	pmgmt_frame = rtw_set_fixed_ie(pmgmt_frame, _RSON_CODE_ , (unsigned char *)&reason, &frame_len);
++
++	#ifdef COMPAT_KERNEL_RELEASE
++	rtw_cfg80211_rx_mgmt(wdev, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC);
++	#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
++	rtw_cfg80211_rx_mgmt(wdev, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC);
++	#else /* COMPAT_KERNEL_RELEASE */
++	cfg80211_send_disassoc(padapter->pnetdev, mgmt_buf, frame_len);
++	/* cfg80211_rx_action(padapter->pnetdev, freq, mgmt_buf, frame_len, GFP_ATOMIC); */
++	#endif /* COMPAT_KERNEL_RELEASE */
++#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */
++}
++
++static int rtw_cfg80211_monitor_if_open(struct net_device *ndev)
++{
++	int ret = 0;
++
++	RTW_INFO("%s\n", __func__);
++
++	return ret;
++}
++
++static int rtw_cfg80211_monitor_if_close(struct net_device *ndev)
++{
++	int ret = 0;
++
++	RTW_INFO("%s\n", __func__);
++
++	return ret;
++}
++
++static int rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struct net_device *ndev)
++{
++	int ret = 0;
++	int rtap_len;
++	int qos_len = 0;
++	int dot11_hdr_len = 24;
++	int snap_len = 6;
++	unsigned char *pdata;
++	u16 frame_ctl;
++	unsigned char src_mac_addr[ETH_ALEN];
++	unsigned char dst_mac_addr[ETH_ALEN];
++	struct rtw_ieee80211_hdr *dot11_hdr;
++	struct ieee80211_radiotap_header *rtap_hdr;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++#ifdef CONFIG_DFS_MASTER
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++#endif
++
++	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++	rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize);
++
++	if (IS_CH_WAITING(rfctl)) {
++		#ifdef CONFIG_DFS_MASTER
++		if (rtw_rfctl_overlap_radar_detect_ch(rfctl))
++			goto fail;
++		#endif
++	}
++
++	if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header)))
++		goto fail;
++
++	rtap_hdr = (struct ieee80211_radiotap_header *)skb->data;
++	if (unlikely(rtap_hdr->it_version))
++		goto fail;
++
++	rtap_len = ieee80211_get_radiotap_len(skb->data);
++	if (unlikely(skb->len < rtap_len))
++		goto fail;
++
++	if (rtap_len != 14) {
++		RTW_INFO("radiotap len (should be 14): %d\n", rtap_len);
++		goto fail;
++	}
++
++	/* Skip the ratio tap header */
++	skb_pull(skb, rtap_len);
++
++	dot11_hdr = (struct rtw_ieee80211_hdr *)skb->data;
++	frame_ctl = le16_to_cpu(dot11_hdr->frame_ctl);
++	/* Check if the QoS bit is set */
++	if ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) {
++		/* Check if this ia a Wireless Distribution System (WDS) frame
++		 * which has 4 MAC addresses
++		 */
++		if (dot11_hdr->frame_ctl & 0x0080)
++			qos_len = 2;
++		if ((dot11_hdr->frame_ctl & 0x0300) == 0x0300)
++			dot11_hdr_len += 6;
++
++		memcpy(dst_mac_addr, dot11_hdr->addr1, sizeof(dst_mac_addr));
++		memcpy(src_mac_addr, dot11_hdr->addr2, sizeof(src_mac_addr));
++
++		/* Skip the 802.11 header, QoS (if any) and SNAP, but leave spaces for
++		 * for two MAC addresses
++		 */
++		skb_pull(skb, dot11_hdr_len + qos_len + snap_len - sizeof(src_mac_addr) * 2);
++		pdata = (unsigned char *)skb->data;
++		memcpy(pdata, dst_mac_addr, sizeof(dst_mac_addr));
++		memcpy(pdata + sizeof(dst_mac_addr), src_mac_addr, sizeof(src_mac_addr));
++
++		RTW_INFO("should be eapol packet\n");
++
++		/* Use the real net device to transmit the packet */
++		ret = _rtw_xmit_entry(skb, padapter->pnetdev);
++
++		return ret;
++
++	} else if ((frame_ctl & (RTW_IEEE80211_FCTL_FTYPE | RTW_IEEE80211_FCTL_STYPE))
++		== (RTW_IEEE80211_FTYPE_MGMT | RTW_IEEE80211_STYPE_ACTION)
++	) {
++		/* only for action frames */
++		struct xmit_frame		*pmgntframe;
++		struct pkt_attrib	*pattrib;
++		unsigned char	*pframe;
++		/* u8 category, action, OUI_Subtype, dialogToken=0; */
++		/* unsigned char	*frame_body; */
++		struct rtw_ieee80211_hdr *pwlanhdr;
++		struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
++		struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++		u8 *buf = skb->data;
++		u32 len = skb->len;
++		u8 category, action;
++		int type = -1;
++
++		if (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) {
++			RTW_INFO(FUNC_NDEV_FMT" frame_control:0x%x\n", FUNC_NDEV_ARG(ndev),
++				le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl));
++			goto fail;
++		}
++
++		RTW_INFO("RTW_Tx:da="MAC_FMT" via "FUNC_NDEV_FMT"\n",
++			MAC_ARG(GetAddr1Ptr(buf)), FUNC_NDEV_ARG(ndev));
++		#ifdef CONFIG_P2P
++		type = rtw_p2p_check_frames(padapter, buf, len, _TRUE);
++		if (type >= 0)
++			goto dump;
++		#endif
++		if (category == RTW_WLAN_CATEGORY_PUBLIC)
++			RTW_INFO("RTW_Tx:%s\n", action_public_str(action));
++		else
++			RTW_INFO("RTW_Tx:category(%u), action(%u)\n", category, action);
++#ifdef CONFIG_P2P
++dump:
++#endif
++		/* starting alloc mgmt frame to dump it */
++		pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++		if (pmgntframe == NULL)
++			goto fail;
++
++		/* update attribute */
++		pattrib = &pmgntframe->attrib;
++		update_mgntframe_attrib(padapter, pattrib);
++		pattrib->retry_ctrl = _FALSE;
++
++		_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++		pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++
++		_rtw_memcpy(pframe, (void *)buf, len);
++		pattrib->pktlen = len;
++
++#ifdef CONFIG_P2P
++		if (type >= 0)
++			rtw_xframe_chk_wfd_ie(pmgntframe);
++#endif /* CONFIG_P2P */
++
++		pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++		/* update seq number */
++		pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
++		pattrib->seqnum = pmlmeext->mgnt_seq;
++		pmlmeext->mgnt_seq++;
++
++
++		pattrib->last_txcmdsz = pattrib->pktlen;
++
++		dump_mgntframe(padapter, pmgntframe);
++
++	} else
++		RTW_INFO("frame_ctl=0x%x\n", frame_ctl & (RTW_IEEE80211_FCTL_FTYPE | RTW_IEEE80211_FCTL_STYPE));
++
++
++fail:
++
++	rtw_skb_free(skb);
++
++	return 0;
++
++}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0))
++static void rtw_cfg80211_monitor_if_set_multicast_list(struct net_device *ndev)
++{
++	RTW_INFO("%s\n", __func__);
++}
++#endif
++static int rtw_cfg80211_monitor_if_set_mac_address(struct net_device *ndev, void *addr)
++{
++	int ret = 0;
++
++	RTW_INFO("%s\n", __func__);
++
++	return ret;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
++static const struct net_device_ops rtw_cfg80211_monitor_if_ops = {
++	.ndo_open = rtw_cfg80211_monitor_if_open,
++	.ndo_stop = rtw_cfg80211_monitor_if_close,
++	.ndo_start_xmit = rtw_cfg80211_monitor_if_xmit_entry,
++	#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0))
++	.ndo_set_multicast_list = rtw_cfg80211_monitor_if_set_multicast_list,
++	#endif
++	.ndo_set_mac_address = rtw_cfg80211_monitor_if_set_mac_address,
++};
++#endif
++
++static int rtw_cfg80211_add_monitor_if(_adapter *padapter, char *name, struct net_device **ndev)
++{
++	int ret = 0;
++	struct net_device *mon_ndev = NULL;
++	struct wireless_dev *mon_wdev = NULL;
++	struct rtw_netdev_priv_indicator *pnpi;
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++
++	if (!name) {
++		RTW_INFO(FUNC_ADPT_FMT" without specific name\n", FUNC_ADPT_ARG(padapter));
++		ret = -EINVAL;
++		goto out;
++	}
++
++	if (pwdev_priv->pmon_ndev) {
++		RTW_INFO(FUNC_ADPT_FMT" monitor interface exist: "NDEV_FMT"\n",
++			FUNC_ADPT_ARG(padapter), NDEV_ARG(pwdev_priv->pmon_ndev));
++		ret = -EBUSY;
++		goto out;
++	}
++
++	mon_ndev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator));
++	if (!mon_ndev) {
++		RTW_INFO(FUNC_ADPT_FMT" allocate ndev fail\n", FUNC_ADPT_ARG(padapter));
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	mon_ndev->type = ARPHRD_IEEE80211_RADIOTAP;
++	strncpy(mon_ndev->name, name, IFNAMSIZ);
++	mon_ndev->name[IFNAMSIZ - 1] = 0;
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(4, 11, 8))
++	mon_ndev->priv_destructor = rtw_ndev_destructor;
++#else
++	mon_ndev->destructor = rtw_ndev_destructor;
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
++	mon_ndev->netdev_ops = &rtw_cfg80211_monitor_if_ops;
++#else
++	mon_ndev->open = rtw_cfg80211_monitor_if_open;
++	mon_ndev->stop = rtw_cfg80211_monitor_if_close;
++	mon_ndev->hard_start_xmit = rtw_cfg80211_monitor_if_xmit_entry;
++	mon_ndev->set_mac_address = rtw_cfg80211_monitor_if_set_mac_address;
++#endif
++
++	pnpi = netdev_priv(mon_ndev);
++	pnpi->priv = padapter;
++	pnpi->sizeof_priv = sizeof(_adapter);
++
++	/*  wdev */
++	mon_wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev));
++	if (!mon_wdev) {
++		RTW_INFO(FUNC_ADPT_FMT" allocate mon_wdev fail\n", FUNC_ADPT_ARG(padapter));
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	mon_wdev->wiphy = padapter->rtw_wdev->wiphy;
++	mon_wdev->netdev = mon_ndev;
++	mon_wdev->iftype = NL80211_IFTYPE_MONITOR;
++	mon_ndev->ieee80211_ptr = mon_wdev;
++
++	ret = register_netdevice(mon_ndev);
++	if (ret)
++		goto out;
++
++	*ndev = pwdev_priv->pmon_ndev = mon_ndev;
++	_rtw_memcpy(pwdev_priv->ifname_mon, name, IFNAMSIZ + 1);
++
++out:
++	if (ret && mon_wdev) {
++		rtw_mfree((u8 *)mon_wdev, sizeof(struct wireless_dev));
++		mon_wdev = NULL;
++	}
++
++	if (ret && mon_ndev) {
++		free_netdev(mon_ndev);
++		*ndev = mon_ndev = NULL;
++	}
++
++	return ret;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++static struct wireless_dev *
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
++static struct net_device *
++#else
++static int
++#endif
++	cfg80211_rtw_add_virtual_intf(
++		struct wiphy *wiphy,
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
++		const char *name,
++		#else
++		char *name,
++		#endif
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
++		unsigned char name_assign_type,
++		#endif
++		enum nl80211_iftype type,
++		#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
++		u32 *flags,
++		#endif
++		struct vif_params *params)
++{
++	int ret = 0;
++	struct wireless_dev *wdev = NULL;
++	struct net_device *ndev = NULL;
++	_adapter *padapter;
++	struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);
++
++	rtw_set_rtnl_lock_holder(dvobj, current);
++
++	RTW_INFO(FUNC_WIPHY_FMT" name:%s, type:%d\n", FUNC_WIPHY_ARG(wiphy), name, type);
++
++	switch (type) {
++	case NL80211_IFTYPE_MONITOR:
++		padapter = wiphy_to_adapter(wiphy); /* TODO: get ap iface ? */
++		ret = rtw_cfg80211_add_monitor_if(padapter, (char *)name, &ndev);
++		if (ret == 0)
++			wdev = ndev->ieee80211_ptr;
++		break;
++
++#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
++	case NL80211_IFTYPE_P2P_CLIENT:
++	case NL80211_IFTYPE_P2P_GO:
++#endif
++	case NL80211_IFTYPE_STATION:
++	case NL80211_IFTYPE_AP:
++#ifdef CONFIG_RTW_MESH
++	case NL80211_IFTYPE_MESH_POINT:
++#endif
++		padapter = dvobj_get_unregisterd_adapter(dvobj);
++		if (!padapter) {
++			RTW_WARN("adapter pool empty!\n");
++			ret = -ENODEV;
++			break;
++		}
++
++		#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_P2P)
++		#if defined(CONFIG_P2P) && ((KERNEL_VERSION(2, 6, 37) <= LINUX_VERSION_CODE) || defined(COMPAT_KERNEL_RELEASE))
++		if ((type == NL80211_IFTYPE_P2P_CLIENT || type == NL80211_IFTYPE_P2P_GO) && (padapter->iface_id != padapter->registrypriv.sel_p2p_iface)) {
++			RTW_ERR("%s, iface_id:%d is not P2P interface!\n", __func__, padapter->iface_id);
++			ret = -EOPNOTSUPP;
++			break;
++		}
++		#endif
++		#endif
++
++		if (rtw_os_ndev_init(padapter, name) != _SUCCESS) {
++			RTW_WARN("ndev init fail!\n");
++			ret = -ENODEV;
++			break;
++		}
++		#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
++		if (type == NL80211_IFTYPE_P2P_CLIENT || type == NL80211_IFTYPE_P2P_GO)
++			rtw_p2p_enable(padapter, P2P_ROLE_DEVICE);
++		#endif
++		ndev = padapter->pnetdev;
++		wdev = ndev->ieee80211_ptr;
++		break;
++
++#if defined(CONFIG_P2P) && defined(RTW_DEDICATED_P2P_DEVICE)
++	case NL80211_IFTYPE_P2P_DEVICE:
++		ret = rtw_pd_iface_alloc(wiphy, name, &wdev);
++		break;
++#endif
++
++	case NL80211_IFTYPE_ADHOC:
++	case NL80211_IFTYPE_AP_VLAN:
++	case NL80211_IFTYPE_WDS:
++	default:
++		ret = -ENODEV;
++		RTW_INFO("Unsupported interface type\n");
++		break;
++	}
++
++	if (ndev)
++		RTW_INFO(FUNC_WIPHY_FMT" ndev:%p, ret:%d\n", FUNC_WIPHY_ARG(wiphy), ndev, ret);
++	else
++		RTW_INFO(FUNC_WIPHY_FMT" wdev:%p, ret:%d\n", FUNC_WIPHY_ARG(wiphy), wdev, ret);
++
++	rtw_set_rtnl_lock_holder(dvobj, NULL);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	return wdev ? wdev : ERR_PTR(ret);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
++	return ndev ? ndev : ERR_PTR(ret);
++#else
++	return ret;
++#endif
++}
++
++static int cfg80211_rtw_del_virtual_intf(struct wiphy *wiphy,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	struct wireless_dev *wdev
++#else
++	struct net_device *ndev
++#endif
++)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	struct net_device *ndev = wdev_to_ndev(wdev);
++#endif
++	int ret = 0;
++	struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);
++	_adapter *adapter;
++	struct rtw_wdev_priv *pwdev_priv;
++
++	rtw_set_rtnl_lock_holder(dvobj, current);
++
++	if (ndev) {
++		adapter = (_adapter *)rtw_netdev_priv(ndev);
++		pwdev_priv = adapter_wdev_data(adapter);
++
++		if (ndev == pwdev_priv->pmon_ndev) {
++			unregister_netdevice(ndev);
++			pwdev_priv->pmon_ndev = NULL;
++			pwdev_priv->ifname_mon[0] = '\0';
++			RTW_INFO(FUNC_NDEV_FMT" remove monitor ndev\n", FUNC_NDEV_ARG(ndev));
++		} else {
++			RTW_INFO(FUNC_NDEV_FMT" unregister ndev\n", FUNC_NDEV_ARG(ndev));
++			rtw_os_ndev_unregister(adapter);
++		}
++	} else
++#if defined(CONFIG_P2P) && defined(RTW_DEDICATED_P2P_DEVICE)
++	if (wdev->iftype == NL80211_IFTYPE_P2P_DEVICE) {
++		if (wdev == wiphy_to_pd_wdev(wiphy))
++			rtw_pd_iface_free(wiphy);
++		else {
++			RTW_ERR(FUNC_WIPHY_FMT" unknown P2P Device wdev:%p\n", FUNC_WIPHY_ARG(wiphy), wdev);
++			rtw_warn_on(1);
++		}
++	} else
++#endif
++	{
++		ret = -EINVAL;
++		goto exit;
++	}
++
++exit:
++	rtw_set_rtnl_lock_holder(dvobj, NULL);
++	return ret;
++}
++
++static int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, const u8 *tail, size_t tail_len)
++{
++	int ret = 0;
++	u8 *pbuf = NULL;
++	uint len, wps_ielen = 0;
++	uint p2p_ielen = 0;
++	u8 got_p2p_ie = _FALSE;
++	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++	/* struct sta_priv *pstapriv = &padapter->stapriv; */
++
++
++	RTW_INFO("%s beacon_head_len=%zu, beacon_tail_len=%zu\n", __FUNCTION__, head_len, tail_len);
++
++
++	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++		return -EINVAL;
++
++	if (head_len < 24)
++		return -EINVAL;
++
++	#ifdef CONFIG_FW_HANDLE_TXBCN
++	if (!rtw_ap_nums_check(adapter)) {
++		RTW_ERR(FUNC_ADPT_FMT"failed, con't support over %d BCN\n", FUNC_ADPT_ARG(adapter), CONFIG_LIMITED_AP_NUM);
++		return -EINVAL;
++	}
++	#endif /*CONFIG_FW_HANDLE_TXBCN*/
++
++	pbuf = rtw_zmalloc(head_len + tail_len);
++	if (!pbuf) {
++		ret = -ENOMEM;
++		goto exit;
++	}
++
++
++	/* _rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2); */
++
++	/* if((pstapriv->max_num_sta>NUM_STA) || (pstapriv->max_num_sta<=0)) */
++	/*	pstapriv->max_num_sta = NUM_STA; */
++
++
++	_rtw_memcpy(pbuf, (void *)head + 24, head_len - 24); /* 24=beacon header len. */
++	_rtw_memcpy(pbuf + head_len - 24, (void *)tail, tail_len);
++
++	len = head_len + tail_len - 24;
++
++	/* check wps ie if inclued */
++	if (rtw_get_wps_ie(pbuf + _FIXED_IE_LENGTH_, len - _FIXED_IE_LENGTH_, NULL, &wps_ielen))
++		RTW_INFO("add bcn, wps_ielen=%d\n", wps_ielen);
++
++#ifdef CONFIG_P2P
++	if (adapter->wdinfo.driver_interface == DRIVER_CFG80211) {
++		/* check p2p if enable */
++		if (rtw_get_p2p_ie(pbuf + _FIXED_IE_LENGTH_, len - _FIXED_IE_LENGTH_, NULL, &p2p_ielen)) {
++			struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
++
++			RTW_INFO("got p2p_ie, len=%d\n", p2p_ielen);
++
++			got_p2p_ie = _TRUE;
++
++			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
++
++				if (rtw_p2p_enable(adapter, P2P_ROLE_GO)) {
++					RTW_INFO("Enable P2P function for the first time\n");
++					adapter->stapriv.expire_to = 3; /* 3x2 = 6 sec in p2p mode */
++				} else {
++					ret = -EOPNOTSUPP;
++					goto exit;
++				}
++			} else {
++				RTW_INFO("enter GO Mode, p2p_ielen=%d\n", p2p_ielen);
++
++				rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
++				rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
++				pwdinfo->intent = 15;
++			}
++		}
++	}
++#endif /* CONFIG_P2P */
++
++	/* pbss_network->IEs will not include p2p_ie, wfd ie */
++	rtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, P2P_OUI, 4);
++	rtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, WFD_OUI, 4);
++
++	if (rtw_check_beacon_data(adapter, pbuf,  len) == _SUCCESS) {
++#ifdef CONFIG_P2P
++		/* check p2p if enable */
++		if (got_p2p_ie == _TRUE) {
++			struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++			struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
++			pwdinfo->operating_channel = pmlmeext->cur_channel;
++		}
++#endif /* CONFIG_P2P */
++		ret = 0;
++	} else
++		ret = -EINVAL;
++
++exit:
++	if (pbuf)
++		rtw_mfree(pbuf, head_len + tail_len);
++
++	return ret;
++}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE)
++static int cfg80211_rtw_add_beacon(struct wiphy *wiphy, struct net_device *ndev,
++		struct beacon_parameters *info)
++{
++	int ret = 0;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
++
++	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++	if (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) {
++		ret = -ENOTSUPP;
++		goto exit;
++	}
++	rtw_mi_scan_abort(adapter, _TRUE);
++	rtw_mi_buddy_set_scan_deny(adapter, 300);
++	ret = rtw_add_beacon(adapter, info->head, info->head_len, info->tail, info->tail_len);
++
++exit:
++	return ret;
++}
++
++static int cfg80211_rtw_set_beacon(struct wiphy *wiphy, struct net_device *ndev,
++		struct beacon_parameters *info)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
++
++	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++	pmlmeext->bstart_bss = _TRUE;
++
++	cfg80211_rtw_add_beacon(wiphy, ndev, info);
++
++	return 0;
++}
++
++static int	cfg80211_rtw_del_beacon(struct wiphy *wiphy, struct net_device *ndev)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
++
++	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++	rtw_stop_ap_cmd(adapter, RTW_CMDF_WAIT_ACK);
++	return 0;
++}
++#else
++static int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev,
++		struct cfg80211_ap_settings *settings)
++{
++	int ret = 0;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
++
++	RTW_INFO(FUNC_NDEV_FMT" hidden_ssid:%d, auth_type:%d\n", FUNC_NDEV_ARG(ndev),
++		settings->hidden_ssid, settings->auth_type);
++
++	if (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) {
++		ret = -ENOTSUPP;
++		goto exit;
++	}
++
++	/* Kernel < v5.x, the auth_type set as NL80211_AUTHTYPE_AUTOMATIC. if
++	 * the AKM SAE in the RSN IE, we have to update the auth_type for SAE in
++	 * rtw_check_beacon_data().
++	 *
++	 * we only update auth_type when rtw_check_beacon_data()
++	 */
++	/* rtw_cfg80211_set_auth_type(&adapter->securitypriv, settings->auth_type); */
++
++	rtw_mi_scan_abort(adapter, _TRUE);
++	rtw_mi_buddy_set_scan_deny(adapter, 300);
++
++	adapter->mlmeextpriv.mlmext_info.hidden_ssid_mode = settings->hidden_ssid;
++	ret = rtw_add_beacon(adapter, settings->beacon.head, settings->beacon.head_len,
++		settings->beacon.tail, settings->beacon.tail_len);
++
++	if (settings->ssid && settings->ssid_len) {
++		WLAN_BSSID_EX *pbss_network = &adapter->mlmepriv.cur_network.network;
++		WLAN_BSSID_EX *pbss_network_ext = &adapter->mlmeextpriv.mlmext_info.network;
++
++		if (0)
++			RTW_INFO(FUNC_ADPT_FMT" ssid:(%s,%zu), from ie:(%s,%d)\n", FUNC_ADPT_ARG(adapter),
++				settings->ssid, settings->ssid_len,
++				pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength);
++
++		_rtw_memcpy(pbss_network->Ssid.Ssid, (void *)settings->ssid, settings->ssid_len);
++		pbss_network->Ssid.SsidLength = settings->ssid_len;
++		_rtw_memcpy(pbss_network_ext->Ssid.Ssid, (void *)settings->ssid, settings->ssid_len);
++		pbss_network_ext->Ssid.SsidLength = settings->ssid_len;
++
++		if (0)
++			RTW_INFO(FUNC_ADPT_FMT" after ssid:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter),
++				pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength,
++				pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength);
++	}
++
++exit:
++	return ret;
++}
++
++static int cfg80211_rtw_change_beacon(struct wiphy *wiphy, struct net_device *ndev,
++		struct cfg80211_beacon_data *info)
++{
++	int ret = 0;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
++
++	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++	ret = rtw_add_beacon(adapter, info->head, info->head_len, info->tail, info->tail_len);
++
++	return ret;
++}
++
++static int cfg80211_rtw_stop_ap(struct wiphy *wiphy, struct net_device *ndev)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
++
++	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++	rtw_stop_ap_cmd(adapter, RTW_CMDF_WAIT_ACK);
++	return 0;
++}
++#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) */
++
++#if CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++static int cfg80211_rtw_set_mac_acl(struct wiphy *wiphy, struct net_device *ndev,
++		const struct cfg80211_acl_data *params)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
++	u8 acl_mode = RTW_ACL_MODE_DISABLED;
++	int ret = -1;
++	int i;
++
++	if (!params) {
++		RTW_WARN(FUNC_ADPT_FMT" params NULL\n", FUNC_ADPT_ARG(adapter));
++		rtw_macaddr_acl_clear(adapter, RTW_ACL_PERIOD_BSS);
++		goto exit;
++	}
++
++	RTW_INFO(FUNC_ADPT_FMT" acl_policy:%d, entry_num:%d\n"
++		, FUNC_ADPT_ARG(adapter), params->acl_policy, params->n_acl_entries);
++
++	if (params->acl_policy == NL80211_ACL_POLICY_ACCEPT_UNLESS_LISTED)
++		acl_mode = RTW_ACL_MODE_ACCEPT_UNLESS_LISTED;
++	else if (params->acl_policy == NL80211_ACL_POLICY_DENY_UNLESS_LISTED)
++		acl_mode = RTW_ACL_MODE_DENY_UNLESS_LISTED;
++
++	rtw_macaddr_acl_clear(adapter, RTW_ACL_PERIOD_BSS);
++
++	rtw_set_macaddr_acl(adapter, RTW_ACL_PERIOD_BSS, acl_mode);
++
++	for (i = 0; i < params->n_acl_entries; i++)
++		rtw_acl_add_sta(adapter, RTW_ACL_PERIOD_BSS, params->mac_addrs[i].addr);
++
++	ret = 0;
++
++exit:
++	return ret;
++}
++#endif /* CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) */
++
++const char *_nl80211_sta_flags_str[] = {
++	"INVALID",
++	"AUTHORIZED",
++	"SHORT_PREAMBLE",
++	"WME",
++	"MFP",
++	"AUTHENTICATED",
++	"TDLS_PEER",
++	"ASSOCIATED",
++};
++
++#define nl80211_sta_flags_str(_f) ((_f <= NL80211_STA_FLAG_MAX) ? _nl80211_sta_flags_str[_f] : _nl80211_sta_flags_str[0])
++
++const char *_nl80211_plink_state_str[] = {
++	"LISTEN",
++	"OPN_SNT",
++	"OPN_RCVD",
++	"CNF_RCVD",
++	"ESTAB",
++	"HOLDING",
++	"BLOCKED",
++	"UNKNOWN",
++};
++
++#define nl80211_plink_state_str(_s) ((_s < NUM_NL80211_PLINK_STATES) ? _nl80211_plink_state_str[_s] : _nl80211_plink_state_str[NUM_NL80211_PLINK_STATES])
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))
++#define NL80211_PLINK_ACTION_NO_ACTION PLINK_ACTION_INVALID
++#define NL80211_PLINK_ACTION_OPEN PLINK_ACTION_OPEN
++#define NL80211_PLINK_ACTION_BLOCK PLINK_ACTION_BLOCK
++#define NUM_NL80211_PLINK_ACTIONS 3
++#endif
++
++const char *_nl80211_plink_actions_str[] = {
++	"NO_ACTION",
++	"OPEN",
++	"BLOCK",
++	"UNKNOWN",
++};
++
++#define nl80211_plink_actions_str(_a) ((_a < NUM_NL80211_PLINK_ACTIONS) ? _nl80211_plink_actions_str[_a] : _nl80211_plink_actions_str[NUM_NL80211_PLINK_ACTIONS])
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++const char *_nl80211_mesh_power_mode_str[] = {
++	"UNKNOWN",
++	"ACTIVE",
++	"LIGHT_SLEEP",
++	"DEEP_SLEEP",
++};
++
++#define nl80211_mesh_power_mode_str(_p) ((_p <= NL80211_MESH_POWER_MAX) ? _nl80211_mesh_power_mode_str[_p] : _nl80211_mesh_power_mode_str[0])
++#endif
++
++void dump_station_parameters(void *sel, struct wiphy *wiphy, const struct station_parameters *params)
++{
++#if DBG_RTW_CFG80211_STA_PARAM
++	if (params->supported_rates_len) {
++		#define SUPP_RATES_BUF_LEN (3 * RTW_G_RATES_NUM + 1)
++		int i;
++		char supp_rates_buf[SUPP_RATES_BUF_LEN] = {0};
++		u8 cnt = 0;
++
++		rtw_warn_on(params->supported_rates_len > RTW_G_RATES_NUM);
++
++		for (i = 0; i < params->supported_rates_len; i++) {
++			if (i >= RTW_G_RATES_NUM)
++				break;
++			cnt += snprintf(supp_rates_buf + cnt, SUPP_RATES_BUF_LEN - cnt -1
++				, "%02X ", params->supported_rates[i]);
++			if (cnt >= SUPP_RATES_BUF_LEN - 1)
++				break;
++		}
++
++		RTW_PRINT_SEL(sel, "supported_rates:%s\n", supp_rates_buf);
++	}
++
++	if (params->vlan)
++		RTW_PRINT_SEL(sel, "vlan:"NDEV_FMT"\n", NDEV_ARG(params->vlan));
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
++	if (params->sta_flags_mask) {
++		#define STA_FLAGS_BUF_LEN 128
++		int i = 0;
++		char sta_flags_buf[STA_FLAGS_BUF_LEN] = {0};
++		u8 cnt = 0;
++
++		for (i = 1; i <= NL80211_STA_FLAG_MAX; i++) {
++			if (params->sta_flags_mask & BIT(i)) {
++				cnt += snprintf(sta_flags_buf + cnt, STA_FLAGS_BUF_LEN - cnt -1, "%s=%u "
++					, nl80211_sta_flags_str(i), (params->sta_flags_set & BIT(i)) ? 1 : 0);
++				if (cnt >= STA_FLAGS_BUF_LEN - 1)
++					break;
++			}
++		}
++
++		RTW_PRINT_SEL(sel, "sta_flags:%s\n", sta_flags_buf);
++	}
++#else
++	u32 station_flags;
++	#error "TBD\n"
++#endif
++
++	if (params->listen_interval != -1)
++		RTW_PRINT_SEL(sel, "listen_interval:%d\n", params->listen_interval);
++
++	if (params->aid)
++		RTW_PRINT_SEL(sel, "aid:%u\n", params->aid);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
++	if (params->peer_aid)
++		RTW_PRINT_SEL(sel, "peer_aid:%u\n", params->peer_aid);
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26))
++	if (params->plink_action != NL80211_PLINK_ACTION_NO_ACTION)
++		RTW_PRINT_SEL(sel, "plink_action:%s\n", nl80211_plink_actions_str(params->plink_action));
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
++	if (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE)
++	#endif
++		RTW_PRINT_SEL(sel, "plink_state:%s\n"
++			, nl80211_plink_state_str(params->plink_state));
++#endif
++
++#if 0 /* TODO */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28))
++	const struct ieee80211_ht_cap *ht_capa;
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	const struct ieee80211_vht_cap *vht_capa;
++#endif
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	if (params->sta_modify_mask & STATION_PARAM_APPLY_UAPSD)
++		RTW_PRINT_SEL(sel, "uapsd_queues:0x%02x\n", params->uapsd_queues);
++	if (params->max_sp)
++		RTW_PRINT_SEL(sel, "max_sp:%u\n", params->max_sp);
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++	if (params->local_pm != NL80211_MESH_POWER_UNKNOWN) {
++		RTW_PRINT_SEL(sel, "local_pm:%s\n"
++			, nl80211_mesh_power_mode_str(params->local_pm));
++	}
++
++	if (params->sta_modify_mask & STATION_PARAM_APPLY_CAPABILITY)
++		RTW_PRINT_SEL(sel, "capability:0x%04x\n", params->capability);
++
++#if 0 /* TODO */
++	const u8 *ext_capab;
++	u8 ext_capab_len;
++#endif
++#endif
++
++#if 0 /* TODO */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0))
++	const u8 *supported_channels;
++	u8 supported_channels_len;
++	const u8 *supported_oper_classes;
++	u8 supported_oper_classes_len;
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
++	u8 opmode_notif;
++	bool opmode_notif_used;
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))
++	int support_p2p_ps;
++#endif
++#endif
++#endif /* DBG_RTW_CFG80211_STA_PARAM */
++}
++
++static int	cfg80211_rtw_add_station(struct wiphy *wiphy, struct net_device *ndev,
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
++	u8 *mac,
++#else
++	const u8 *mac,
++#endif
++	struct station_parameters *params)
++{
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++#if defined(CONFIG_TDLS) || defined(CONFIG_RTW_MESH)
++	struct sta_priv *pstapriv = &padapter->stapriv;
++#endif
++#ifdef CONFIG_TDLS
++	struct sta_info *psta;
++#endif /* CONFIG_TDLS */
++
++	RTW_INFO(FUNC_NDEV_FMT" mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(mac));
++
++#if CONFIG_RTW_MACADDR_ACL
++	if (rtw_access_ctrl(padapter, mac) == _FALSE) {
++		RTW_INFO(FUNC_NDEV_FMT" deny by macaddr ACL\n", FUNC_NDEV_ARG(ndev));
++		ret = -EINVAL;
++		goto exit;
++	}
++#endif
++
++	dump_station_parameters(RTW_DBGDUMP, wiphy, params);
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(padapter)) {
++		struct rtw_mesh_cfg *mcfg = &padapter->mesh_cfg;
++		struct rtw_mesh_info *minfo = &padapter->mesh_info;
++		struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
++		struct mesh_plink_ent *plink = NULL;
++		struct wlan_network *scanned = NULL;
++		bool acnode = 0;
++		u8 add_new_sta = 0, probe_req = 0;
++		_irqL irqL;
++
++		if (params->plink_state != NL80211_PLINK_LISTEN) {
++			RTW_WARN(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(ndev), nl80211_plink_state_str(params->plink_state));
++			rtw_warn_on(1);
++		}
++		if (!params->aid || params->aid > pstapriv->max_aid) {
++			RTW_WARN(FUNC_NDEV_FMT" invalid aid:%u\n", FUNC_NDEV_ARG(ndev), params->aid);
++			rtw_warn_on(1);
++			ret = -EINVAL;
++			goto exit;
++		}
++
++		_enter_critical_bh(&(plink_ctl->lock), &irqL);
++
++		plink = _rtw_mesh_plink_get(padapter, mac);
++		if (plink)
++			goto release_plink_ctl;
++
++		#if CONFIG_RTW_MESH_PEER_BLACKLIST
++		if (rtw_mesh_peer_blacklist_search(padapter, mac)) {
++			RTW_INFO(FUNC_NDEV_FMT" deny by peer blacklist\n"
++				, FUNC_NDEV_ARG(ndev));
++			ret = -EINVAL;
++			goto release_plink_ctl;
++		}
++		#endif
++
++		scanned = rtw_find_network(&padapter->mlmepriv.scanned_queue, mac);
++		if (!scanned
++			|| rtw_get_passing_time_ms(scanned->last_scanned) >= mcfg->peer_sel_policy.scanr_exp_ms
++		) {
++			if (!scanned)
++				RTW_INFO(FUNC_NDEV_FMT" corresponding network not found\n", FUNC_NDEV_ARG(ndev));
++			else
++				RTW_INFO(FUNC_NDEV_FMT" corresponding network too old\n", FUNC_NDEV_ARG(ndev));
++
++			if (adapter_to_rfctl(padapter)->offch_state == OFFCHS_NONE)
++				probe_req = 1;
++
++			ret = -EINVAL;
++			goto release_plink_ctl;
++		}
++
++		#if CONFIG_RTW_MESH_ACNODE_PREVENT
++		if (plink_ctl->acnode_rsvd)
++			acnode = rtw_mesh_scanned_is_acnode_confirmed(padapter, scanned);
++		#endif
++
++		/* wpa_supplicant's auto peer will initiate peering when candidate peer is reported without max_peer_links consideration */
++		if (plink_ctl->num >= mcfg->max_peer_links + acnode ? 1 : 0) {
++			RTW_INFO(FUNC_NDEV_FMT" exceed max_peer_links:%u%s\n"
++				, FUNC_NDEV_ARG(ndev), mcfg->max_peer_links, acnode ? " acn" : "");
++			ret = -EINVAL;
++			goto release_plink_ctl;
++		}
++
++		if (!rtw_bss_is_candidate_mesh_peer(padapter, &scanned->network, 1, 1)) {
++			RTW_WARN(FUNC_NDEV_FMT" corresponding network is not candidate with same ch\n"
++				, FUNC_NDEV_ARG(ndev));
++			ret = -EINVAL;
++			goto release_plink_ctl;
++		}
++
++		#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++		if (!rtw_mesh_cto_mgate_network_filter(padapter, scanned)) {
++			RTW_INFO(FUNC_NDEV_FMT" peer filtered out by cto_mgate check\n"
++				, FUNC_NDEV_ARG(ndev));
++			ret = -EINVAL;
++			goto release_plink_ctl;
++		}
++		#endif
++
++		if (_rtw_mesh_plink_add(padapter, mac) == _SUCCESS) {
++			/* hook corresponding network in scan queue */
++			plink = _rtw_mesh_plink_get(padapter, mac);
++			plink->aid = params->aid;
++			plink->scanned = scanned;
++
++			#if CONFIG_RTW_MESH_ACNODE_PREVENT
++			if (acnode) {
++				RTW_INFO(FUNC_ADPT_FMT" acnode "MAC_FMT"\n"
++				, FUNC_ADPT_ARG(padapter), MAC_ARG(scanned->network.MacAddress));
++			}
++			#endif
++
++			add_new_sta = 1;
++		} else {
++			RTW_WARN(FUNC_NDEV_FMT" rtw_mesh_plink_add not success\n"
++				, FUNC_NDEV_ARG(ndev));
++			ret = -EINVAL;
++		}
++release_plink_ctl:
++		_exit_critical_bh(&(plink_ctl->lock), &irqL);
++
++		if (probe_req)
++			issue_probereq(padapter, &padapter->mlmepriv.cur_network.network.mesh_id, mac);
++
++		if (add_new_sta) {
++			struct station_info sinfo;
++
++			#ifdef CONFIG_DFS_MASTER
++			if (IS_UNDER_CAC(adapter_to_rfctl(padapter)))
++				rtw_force_stop_cac(adapter_to_rfctl(padapter), 300);
++			#endif
++
++			/* indicate new sta */
++			_rtw_memset(&sinfo, 0, sizeof(sinfo));
++			cfg80211_new_sta(ndev, mac, &sinfo, GFP_ATOMIC);
++		}
++		goto exit;
++	}
++#endif /* CONFIG_RTW_MESH */
++
++#ifdef CONFIG_TDLS
++	psta = rtw_get_stainfo(pstapriv, (u8 *)mac);
++	if (psta == NULL) {
++		psta = rtw_alloc_stainfo(pstapriv, (u8 *)mac);
++		if (psta == NULL) {
++			RTW_INFO("[%s] Alloc station for "MAC_FMT" fail\n", __FUNCTION__, MAC_ARG(mac));
++			ret = -EOPNOTSUPP;
++			goto exit;
++		}
++	}
++#endif /* CONFIG_TDLS */
++
++exit:
++	return ret;
++}
++
++static int	cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev,
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
++	u8 *mac
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0))
++	const u8 *mac
++#else
++	struct station_del_parameters *params
++#endif
++)
++{
++	int ret = 0;
++	_irqL irqL;
++	_list	*phead, *plist;
++	u8 updated = _FALSE;
++	const u8 *target_mac;
++	struct sta_info *psta = NULL;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0))
++	target_mac = mac;
++#else
++	target_mac = params->mac;
++#endif
++
++	RTW_INFO("+"FUNC_NDEV_FMT" mac=%pM\n", FUNC_NDEV_ARG(ndev), target_mac);
++
++	if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE | WIFI_MESH_STATE)) != _TRUE) {
++		RTW_INFO("%s, fw_state != FW_LINKED|WIFI_AP_STATE|WIFI_MESH_STATE\n", __func__);
++		return -EINVAL;
++	}
++
++
++	if (!target_mac) {
++		RTW_INFO("flush all sta, and cam_entry\n");
++
++		flush_all_cam_entry(padapter);	/* clear CAM */
++
++#ifdef CONFIG_AP_MODE
++		ret = rtw_sta_flush(padapter, _TRUE);
++#endif
++		return ret;
++	}
++
++
++	RTW_INFO("free sta macaddr =" MAC_FMT "\n", MAC_ARG(target_mac));
++
++	if (target_mac[0] == 0xff && target_mac[1] == 0xff &&
++	    target_mac[2] == 0xff && target_mac[3] == 0xff &&
++	    target_mac[4] == 0xff && target_mac[5] == 0xff)
++		return -EINVAL;
++
++
++	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++	phead = &pstapriv->asoc_list;
++	plist = get_next(phead);
++
++	/* check asoc_queue */
++	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++
++		plist = get_next(plist);
++
++		if (_rtw_memcmp((u8 *)target_mac, psta->cmn.mac_addr, ETH_ALEN)) {
++			if (psta->dot8021xalg == 1 && psta->bpairwise_key_installed == _FALSE) {
++				RTW_INFO("%s, sta's dot8021xalg = 1 and key_installed = _FALSE\n", __func__);
++
++				if (MLME_IS_AP(padapter)) {
++					rtw_list_delete(&psta->asoc_list);
++					pstapriv->asoc_list_cnt--;
++					#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++					if (psta->tbtx_enable)
++						pstapriv->tbtx_asoc_list_cnt--;
++					#endif
++					STA_SET_MESH_PLINK(psta, NULL);
++
++					ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_IEEE_802_1X_AUTH_FAILED, _TRUE);
++					psta = NULL;
++					break;
++				}
++			} else {
++				RTW_INFO("free psta=%p, aid=%d\n", psta, psta->cmn.aid);
++
++				rtw_list_delete(&psta->asoc_list);
++				pstapriv->asoc_list_cnt--;
++				#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++				if (psta->tbtx_enable)
++					pstapriv->tbtx_asoc_list_cnt--;
++				#endif
++				STA_SET_MESH_PLINK(psta, NULL);
++
++				/* _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); */
++				if (MLME_IS_AP(padapter))
++					updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE);
++				else
++					updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _TRUE);
++				/* _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); */
++
++				psta = NULL;
++
++				break;
++			}
++
++		}
++
++	}
++
++	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++	associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(padapter))
++		rtw_mesh_plink_del(padapter, target_mac);
++#endif
++
++	RTW_INFO("-"FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++	return ret;
++
++}
++
++static int	cfg80211_rtw_change_station(struct wiphy *wiphy, struct net_device *ndev,
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
++	u8 *mac,
++#else
++	const u8 *mac,
++#endif
++	struct station_parameters *params)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
++	int ret = 0;
++
++	RTW_INFO(FUNC_ADPT_FMT" mac:"MAC_FMT"\n", FUNC_ADPT_ARG(adapter), MAC_ARG(mac));
++
++	dump_station_parameters(RTW_DBGDUMP, wiphy, params);
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(adapter)) {
++		enum cfg80211_station_type sta_type = CFG80211_STA_MESH_PEER_USER;
++		u8 plink_state = nl80211_plink_state_to_rtw_plink_state(params->plink_state);
++
++		ret = cfg80211_check_station_change(wiphy, params, sta_type);
++		if (ret) {
++			RTW_INFO("cfg80211_check_station_change return %d\n", ret);
++			goto exit;
++		}
++
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
++		if (!(params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE))
++			goto exit;
++		#endif
++
++		if (rtw_mesh_set_plink_state_cmd(adapter, mac, plink_state) != _SUCCESS)
++			ret = -ENOENT;
++	}
++
++exit:
++#endif /* CONFIG_RTW_MESH */
++
++	if (ret)
++		RTW_INFO(FUNC_ADPT_FMT" mac:"MAC_FMT" ret:%d\n", FUNC_ADPT_ARG(adapter), MAC_ARG(mac), ret);
++	return ret;
++}
++
++struct sta_info *rtw_sta_info_get_by_idx(struct sta_priv *pstapriv, const int idx, u8 *asoc_list_num)
++{
++	_list	*phead, *plist;
++	struct sta_info *psta = NULL;
++	int i = 0;
++
++	phead = &pstapriv->asoc_list;
++	plist = get_next(phead);
++
++	/* check asoc_queue */
++	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++		if (idx == i)
++			psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
++		plist = get_next(plist);
++		i++;
++	}
++
++	if (asoc_list_num)
++		*asoc_list_num = i;
++
++	return psta;
++}
++
++static int	cfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *ndev,
++		int idx, u8 *mac, struct station_info *sinfo)
++{
++#define DBG_DUMP_STATION 0
++
++	int ret = 0;
++	_irqL irqL;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct sta_info *psta = NULL;
++#ifdef CONFIG_RTW_MESH
++	struct mesh_plink_ent *plink = NULL;
++#endif
++	u8 asoc_list_num;
++
++	if (DBG_DUMP_STATION)
++		RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++	psta = rtw_sta_info_get_by_idx(pstapriv, idx, &asoc_list_num);
++	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(padapter)) {
++		if (psta)
++			plink = psta->plink;
++		if (!plink)
++			plink = rtw_mesh_plink_get_no_estab_by_idx(padapter, idx - asoc_list_num);
++	}
++#endif /* CONFIG_RTW_MESH */
++
++	if ((!MLME_IS_MESH(padapter) && !psta)
++		#ifdef CONFIG_RTW_MESH
++		|| (MLME_IS_MESH(padapter) && !plink)
++		#endif
++	) {
++		if (DBG_DUMP_STATION)
++			RTW_INFO(FUNC_NDEV_FMT" end with idx:%d\n", FUNC_NDEV_ARG(ndev), idx);
++		ret = -ENOENT;
++		goto exit;
++	}
++
++	if (psta)
++		_rtw_memcpy(mac, psta->cmn.mac_addr, ETH_ALEN);
++	#ifdef CONFIG_RTW_MESH
++	else
++		_rtw_memcpy(mac, plink->addr, ETH_ALEN);
++	#endif
++	
++	sinfo->filled = 0;
++
++	if (psta) {
++		sinfo->filled |= STATION_INFO_SIGNAL;
++		sinfo->signal = translate_percentage_to_dbm(psta->cmn.rssi_stat.rssi);
++		sinfo->filled |= STATION_INFO_INACTIVE_TIME;
++		sinfo->inactive_time = rtw_get_passing_time_ms(psta->sta_stats.last_rx_time);
++	}
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(padapter))
++		rtw_cfg80211_fill_mesh_only_sta_info(plink, psta, sinfo);
++#endif
++
++exit:
++	return ret;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28))
++static int	cfg80211_rtw_change_bss(struct wiphy *wiphy, struct net_device *ndev,
++		struct bss_parameters *params)
++{
++	_adapter *adapter = rtw_netdev_priv(ndev);
++
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
++
++if (0) {
++	if (params->use_cts_prot != -1)
++		RTW_INFO("use_cts_prot=%d\n", params->use_cts_prot);
++	if (params->use_short_preamble != -1)
++		RTW_INFO("use_short_preamble=%d\n", params->use_short_preamble);
++	if (params->use_short_slot_time != -1)
++		RTW_INFO("use_short_slot_time=%d\n", params->use_short_slot_time);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
++	if (params->basic_rates && params->basic_rates_len) {
++		RTW_INFO("basic_rates_len=%d\n", params->basic_rates_len);
++		RTW_INFO_DUMP("basic_rates=", params->basic_rates, params->basic_rates_len);
++	}
++#endif
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	if (params->ap_isolate != -1) {
++		RTW_INFO("ap_isolate=%d\n", params->ap_isolate);
++		adapter->mlmepriv.ap_isolate = params->ap_isolate ? 1 : 0;
++	}
++#endif
++
++if (0) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
++	if (params->ht_opmode != -1)
++		RTW_INFO("ht_opmode=0x%04x\n", params->ht_opmode);
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	if (params->p2p_ctwindow != -1)
++		RTW_INFO("p2p_ctwindow=%d\n", params->p2p_ctwindow);
++	if (params->p2p_opp_ps != -1)
++		RTW_INFO("p2p_opp_ps=%d\n", params->p2p_opp_ps);
++#endif
++}
++	return 0;
++}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
++static int	cfg80211_rtw_set_txq_params(struct wiphy *wiphy
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	, struct net_device *ndev
++#endif
++	, struct ieee80211_txq_params *params)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	_adapter *padapter = rtw_netdev_priv(ndev);
++#else
++	_adapter *padapter = wiphy_to_adapter(wiphy);
++#endif
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	u8	ac, AIFS, ECWMin, ECWMax, aSifsTime;
++	u16	TXOP;
++	u8	shift_count = 0;
++	u32	acParm;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++	ac = params->ac;
++#else
++	ac = params->queue;
++#endif
++
++	switch (ac) {
++	case NL80211_TXQ_Q_VO:
++		ac = XMIT_VO_QUEUE;
++		break;
++
++	case NL80211_TXQ_Q_VI:
++		ac = XMIT_VI_QUEUE;
++		break;
++
++	case NL80211_TXQ_Q_BE:
++		ac = XMIT_BE_QUEUE;
++		break;
++
++	case NL80211_TXQ_Q_BK:
++		ac = XMIT_BK_QUEUE;
++		break;
++
++	default:
++		break;
++	}
++
++#if 0
++	RTW_INFO("ac=%d\n", ac);
++	RTW_INFO("txop=%u\n", params->txop);
++	RTW_INFO("cwmin=%u\n", params->cwmin);
++	RTW_INFO("cwmax=%u\n", params->cwmax);
++	RTW_INFO("aifs=%u\n", params->aifs);
++#endif
++
++	if (is_supported_5g(pmlmeext->cur_wireless_mode) ||
++	    (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
++		aSifsTime = 16;
++	else
++		aSifsTime = 10;
++
++	AIFS = params->aifs * pmlmeinfo->slotTime + aSifsTime;
++
++	while ((params->cwmin + 1) >> shift_count != 1) {
++		shift_count++;
++		if (shift_count == 15)
++			break;
++	}
++
++	ECWMin = shift_count;
++
++	shift_count = 0;
++	while ((params->cwmax + 1) >> shift_count != 1) {
++		shift_count++;
++		if (shift_count == 15)
++			break;
++	}
++
++	ECWMax = shift_count;
++
++	TXOP = le16_to_cpu(params->txop);
++
++	acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
++
++	set_txq_params_cmd(padapter, acParm, ac);
++
++	return 0;
++}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) */
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++static int	cfg80211_rtw_set_channel(struct wiphy *wiphy
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	, struct net_device *ndev
++	#endif
++	, struct ieee80211_channel *chan, enum nl80211_channel_type channel_type)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++#else
++	_adapter *padapter = wiphy_to_adapter(wiphy);
++#endif
++	int chan_target = (u8) ieee80211_frequency_to_channel(chan->center_freq);
++	int chan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++	int chan_width = CHANNEL_WIDTH_20;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++#endif
++
++	switch (channel_type) {
++	case NL80211_CHAN_NO_HT:
++	case NL80211_CHAN_HT20:
++		chan_width = CHANNEL_WIDTH_20;
++		chan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		break;
++	case NL80211_CHAN_HT40MINUS:
++		chan_width = CHANNEL_WIDTH_40;
++		chan_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++		break;
++	case NL80211_CHAN_HT40PLUS:
++		chan_width = CHANNEL_WIDTH_40;
++		chan_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++		break;
++	default:
++		chan_width = CHANNEL_WIDTH_20;
++		chan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		break;
++	}
++
++	RTW_INFO(FUNC_ADPT_FMT" ch:%d bw:%d, offset:%d\n"
++		, FUNC_ADPT_ARG(padapter), chan_target, chan_width, chan_offset);
++
++	rtw_set_chbw_cmd(padapter, chan_target, chan_width, chan_offset, RTW_CMDF_WAIT_ACK);
++
++	return 0;
++}
++#endif /*#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))*/
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++static void rtw_get_chbwoff_from_cfg80211_chan_def(
++	struct cfg80211_chan_def *chandef,
++	u8 *ht, u8 *ch, u8 *bw, u8 *offset)
++{
++	struct ieee80211_channel *chan = chandef->chan;
++
++	*ch = chan->hw_value;
++	*ht = 1;
++
++	switch (chandef->width) {
++	case NL80211_CHAN_WIDTH_20_NOHT:
++		*ht = 0;
++		/* passthrought */
++	case NL80211_CHAN_WIDTH_20:
++		*bw = CHANNEL_WIDTH_20;
++		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		break;
++	case NL80211_CHAN_WIDTH_40:
++		*bw = CHANNEL_WIDTH_40;
++		*offset = (chandef->center_freq1 > chan->center_freq) ?
++			HAL_PRIME_CHNL_OFFSET_LOWER : HAL_PRIME_CHNL_OFFSET_UPPER;
++		break;
++	case NL80211_CHAN_WIDTH_80:
++		*bw = CHANNEL_WIDTH_80;
++		*offset = (chandef->center_freq1 > chan->center_freq) ?
++			HAL_PRIME_CHNL_OFFSET_LOWER : HAL_PRIME_CHNL_OFFSET_UPPER;
++		break;
++	case NL80211_CHAN_WIDTH_160:
++		*bw = CHANNEL_WIDTH_160;
++		*offset = (chandef->center_freq1 > chan->center_freq) ?
++			HAL_PRIME_CHNL_OFFSET_LOWER : HAL_PRIME_CHNL_OFFSET_UPPER;
++		break;
++	case NL80211_CHAN_WIDTH_80P80:
++		*bw = CHANNEL_WIDTH_80_80;
++		*offset = (chandef->center_freq1 > chan->center_freq) ?
++			HAL_PRIME_CHNL_OFFSET_LOWER : HAL_PRIME_CHNL_OFFSET_UPPER;
++		break;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++	case NL80211_CHAN_WIDTH_5:
++		*bw = CHANNEL_WIDTH_5;
++		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		break;
++	case NL80211_CHAN_WIDTH_10:
++		*bw = CHANNEL_WIDTH_10;
++		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		break;
++#endif
++	default:
++		*ht = 0;
++		*bw = CHANNEL_WIDTH_20;
++		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		RTW_INFO("unsupported cwidth:%u\n", chandef->width);
++		rtw_warn_on(1);
++	};
++}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) */
++
++static int cfg80211_rtw_set_monitor_channel(struct wiphy *wiphy
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	, struct cfg80211_chan_def *chandef
++#else
++	, struct ieee80211_channel *chan
++	, enum nl80211_channel_type channel_type
++#endif
++	)
++{
++	_adapter *padapter = wiphy_to_adapter(wiphy);
++	u8 target_channal, target_offset, target_width, ht_option;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++#ifdef CONFIG_DEBUG_CFG80211
++	RTW_INFO("center_freq %u Mhz ch %u width %u freq1 %u freq2 %u\n"
++		, chandef->chan->center_freq
++		, chandef->chan->hw_value
++		, chandef->width
++		, chandef->center_freq1
++		, chandef->center_freq2);
++#endif /* CONFIG_DEBUG_CFG80211 */
++
++	rtw_get_chbwoff_from_cfg80211_chan_def(chandef,
++		&ht_option, &target_channal, &target_width, &target_offset);
++#else
++#ifdef CONFIG_DEBUG_CFG80211
++	RTW_INFO("center_freq %u Mhz ch %u channel_type %u\n"
++		, chan->center_freq
++		, chan->hw_value
++		, channel_type);
++#endif /* CONFIG_DEBUG_CFG80211 */
++
++	rtw_get_chbw_from_nl80211_channel_type(chan, channel_type,
++		&ht_option, &target_channal, &target_width, &target_offset);
++#endif
++	RTW_INFO(FUNC_ADPT_FMT" ch:%d bw:%d, offset:%d\n",
++		FUNC_ADPT_ARG(padapter), target_channal,
++		target_width, target_offset);
++
++	rtw_set_chbw_cmd(padapter, target_channal, target_width,
++		target_offset, RTW_CMDF_WAIT_ACK);
++
++	return 0;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++static int cfg80211_rtw_get_channel(struct wiphy *wiphy,
++	struct wireless_dev *wdev,
++	struct cfg80211_chan_def *chandef)
++{
++	_adapter *padapter = wiphy_to_adapter(wiphy);
++	struct mlme_ext_priv *mlmeext = &(padapter->mlmeextpriv);
++	u8 ht_option = 0;
++	u8 report = 0;
++	int retval = 1;
++
++	if (MLME_IS_ASOC(padapter)) {
++#ifdef CONFIG_80211N_HT
++		ht_option = padapter->mlmepriv.htpriv.ht_option;
++#endif /* CONFIG_80211N_HT */
++		report = 1;
++	} else if (MLME_IS_MONITOR(padapter)) {
++		/* monitor mode always set to HT
++		   we don't support sniffer No HT */
++		ht_option = 1;
++		report = 1;
++	}
++
++	if (report) {
++		rtw_chbw_to_cfg80211_chan_def(wiphy, chandef,
++			mlmeext->cur_channel, mlmeext->cur_bwmode,
++			mlmeext->cur_ch_offset, ht_option);
++		retval = 0;
++	}
++
++	return retval;
++}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) */
++
++/*
++static int	cfg80211_rtw_auth(struct wiphy *wiphy, struct net_device *ndev,
++		struct cfg80211_auth_request *req)
++{
++	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++	return 0;
++}
++
++static int	cfg80211_rtw_assoc(struct wiphy *wiphy, struct net_device *ndev,
++		struct cfg80211_assoc_request *req)
++{
++	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++	return 0;
++}
++*/
++#endif /* CONFIG_AP_MODE */
++
++void rtw_cfg80211_external_auth_request(_adapter *padapter, union recv_frame *rframe)
++{
++	struct rtw_external_auth_params params;
++	struct wireless_dev *wdev = padapter->rtw_wdev;
++	struct net_device *netdev = wdev_to_ndev(wdev);
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++	u8 frame[256] = { 0 };
++	uint frame_len = 24;
++	s32 freq = 0;
++
++	/* rframe, in this case is null point */
++
++	freq = rtw_ch2freq(pmlmeext->cur_channel);
++
++#if (KERNEL_VERSION(4, 17, 0) <= LINUX_VERSION_CODE)
++	params.action = EXTERNAL_AUTH_START;
++	_rtw_memcpy(params.bssid, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
++	params.ssid.ssid_len = pmlmeinfo->network.Ssid.SsidLength;
++	_rtw_memcpy(params.ssid.ssid, pmlmeinfo->network.Ssid.Ssid,
++		pmlmeinfo->network.Ssid.SsidLength);
++	params.key_mgmt_suite = 0x8ac0f00;
++
++	cfg80211_external_auth_request(netdev,
++		(struct cfg80211_external_auth_params *)&params, GFP_ATOMIC);
++#elif (KERNEL_VERSION(2, 6, 37) <= LINUX_VERSION_CODE)
++	set_frame_sub_type(frame, WIFI_AUTH);
++
++	_rtw_memcpy(frame + 4, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
++	_rtw_memcpy(frame + 10, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(frame + 16, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
++	RTW_PUT_LE32((frame + 18), 0x8ac0f00);
++
++	if (pmlmeinfo->network.Ssid.SsidLength) {
++		*(frame + 23) = pmlmeinfo->network.Ssid.SsidLength;
++		_rtw_memcpy(frame + 24, pmlmeinfo->network.Ssid.Ssid,
++			pmlmeinfo->network.Ssid.SsidLength);
++		frame_len = 24 + pmlmeinfo->network.Ssid.SsidLength;
++	}
++	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
++#endif
++}
++
++void rtw_cfg80211_rx_probe_request(_adapter *adapter, union recv_frame *rframe)
++{
++	struct wireless_dev *wdev = adapter->rtw_wdev;
++	u8 *frame = get_recvframe_data(rframe);
++	uint frame_len = rframe->u.hdr.len;
++	s32 freq;
++	u8 ch, sch = rtw_get_oper_ch(adapter);
++
++	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
++	freq = rtw_ch2freq(ch);
++
++#ifdef CONFIG_DEBUG_CFG80211
++	RTW_INFO("RTW_Rx: probe request, ch=%d(%d), ta="MAC_FMT"\n"
++		, ch, sch, MAC_ARG(get_addr2_ptr(frame)));
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
++	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
++#else
++	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
++#endif
++}
++
++void rtw_cfg80211_rx_action_p2p(_adapter *adapter, union recv_frame *rframe)
++{
++	struct wireless_dev *wdev = adapter->rtw_wdev;
++	u8 *frame = get_recvframe_data(rframe);
++	uint frame_len = rframe->u.hdr.len;
++	s32 freq;
++	u8 ch, sch = rtw_get_oper_ch(adapter);
++	u8 category, action;
++	int type;
++
++	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
++	freq = rtw_ch2freq(ch);
++
++	RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n"
++		, ch, sch, MAC_ARG(get_addr2_ptr(frame)));
++#ifdef CONFIG_P2P
++	type = rtw_p2p_check_frames(adapter, frame, frame_len, _FALSE);
++	if (type >= 0)
++		goto indicate;
++#endif
++	rtw_action_frame_parse(frame, frame_len, &category, &action);
++	RTW_INFO("RTW_Rx:category(%u), action(%u)\n", category, action);
++#ifdef CONFIG_P2P
++indicate:
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
++#else
++	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
++#endif
++}
++
++void rtw_cfg80211_rx_p2p_action_public(_adapter *adapter, union recv_frame *rframe)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct wireless_dev *wdev = adapter->rtw_wdev;
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
++	u8 *frame = get_recvframe_data(rframe);
++	uint frame_len = rframe->u.hdr.len;
++	s32 freq;
++	u8 ch, sch = rtw_get_oper_ch(adapter);
++	u8 category, action;
++	int type;
++
++	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
++	freq = rtw_ch2freq(ch);
++
++	RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n"
++		, ch, sch, MAC_ARG(get_addr2_ptr(frame)));
++	#ifdef CONFIG_P2P
++	type = rtw_p2p_check_frames(adapter, frame, frame_len, _FALSE);
++	if (type >= 0) {
++		switch (type) {
++		case P2P_GO_NEGO_CONF:
++			if (0) {
++				RTW_INFO(FUNC_ADPT_FMT" Nego confirm. state=%u, status=%u, iaddr="MAC_FMT"\n"
++					, FUNC_ADPT_ARG(adapter), pwdev_priv->nego_info.state, pwdev_priv->nego_info.status
++					, MAC_ARG(pwdev_priv->nego_info.iface_addr));
++			}
++			if (pwdev_priv->nego_info.state == 2
++				&& pwdev_priv->nego_info.status == 0
++				&& rtw_check_invalid_mac_address(pwdev_priv->nego_info.iface_addr, _FALSE) == _FALSE
++			) {
++				_adapter *intended_iface = dvobj_get_adapter_by_addr(dvobj, pwdev_priv->nego_info.iface_addr);
++
++				if (intended_iface) {
++					RTW_INFO(FUNC_ADPT_FMT" Nego confirm. Allow only "ADPT_FMT" to scan for 2000 ms\n"
++						, FUNC_ADPT_ARG(adapter), ADPT_ARG(intended_iface));
++					/* allow only intended_iface to do scan for 2000 ms */
++					rtw_mi_set_scan_deny(adapter, 2000);
++					rtw_clear_scan_deny(intended_iface);
++				}
++			}
++			break;
++		case P2P_PROVISION_DISC_RESP:
++		case P2P_INVIT_RESP:
++			rtw_clear_scan_deny(adapter);
++			#if !RTW_P2P_GROUP_INTERFACE
++			rtw_mi_buddy_set_scan_deny(adapter, 2000);
++			#endif
++			break;
++		}
++		goto indicate;
++	}
++	#endif
++	rtw_action_frame_parse(frame, frame_len, &category, &action);
++	RTW_INFO("RTW_Rx:category(%u), action(%u)\n", category, action);
++#ifdef CONFIG_P2P
++indicate:
++#endif
++	#if defined(RTW_DEDICATED_P2P_DEVICE)
++	if (rtw_cfg80211_redirect_pd_wdev(dvobj_to_wiphy(dvobj), get_ra(frame), &wdev))
++		if (0)
++			RTW_INFO("redirect to pd_wdev:%p\n", wdev);
++	#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
++#else
++	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
++#endif
++}
++
++void rtw_cfg80211_rx_action(_adapter *adapter, union recv_frame *rframe, const char *msg)
++{
++	struct wireless_dev *wdev = adapter->rtw_wdev;
++	u8 *frame = get_recvframe_data(rframe);
++	uint frame_len = rframe->u.hdr.len;
++	s32 freq;
++	u8 ch, sch = rtw_get_oper_ch(adapter);
++	u8 category, action;
++	int type = -1;
++
++	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
++	freq = rtw_ch2freq(ch);
++
++	RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n"
++		, ch, sch, MAC_ARG(get_addr2_ptr(frame)));
++
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(adapter)) {
++		type = rtw_mesh_check_frames_rx(adapter, frame, frame_len);
++		if (type >= 0)
++			goto indicate;
++	}
++#endif
++	rtw_action_frame_parse(frame, frame_len, &category, &action);
++	if (category == RTW_WLAN_CATEGORY_PUBLIC) {
++		if (action == ACT_PUBLIC_GAS_INITIAL_REQ) {
++			rtw_mi_set_scan_deny(adapter, 200);
++			rtw_mi_scan_abort(adapter, _FALSE); /*rtw_scan_abort_no_wait*/
++		}
++	}
++#ifdef CONFIG_RTW_MESH
++indicate:
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
++#else
++	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
++#endif
++
++	if (type == -1) {
++		if (msg)
++			RTW_INFO("RTW_Rx:%s\n", msg);
++		else
++			RTW_INFO("RTW_Rx:category(%u), action(%u)\n", category, action);
++	}
++}
++
++#ifdef CONFIG_RTW_80211K
++void rtw_cfg80211_rx_rrm_action(_adapter *adapter, union recv_frame *rframe)
++{
++	struct wireless_dev *wdev = adapter->rtw_wdev;
++	u8 *frame = get_recvframe_data(rframe);
++	uint frame_len = rframe->u.hdr.len;
++	s32 freq;
++	u8 ch, sch = rtw_get_oper_ch(adapter);
++
++	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
++	freq = rtw_ch2freq(ch);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
++#else
++	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
++#endif
++	RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n"
++		, ch, sch, MAC_ARG(get_addr2_ptr(frame)));
++}
++#endif /* CONFIG_RTW_80211K */
++
++void rtw_cfg80211_rx_mframe(_adapter *adapter, union recv_frame *rframe, const char *msg)
++{
++	struct wireless_dev *wdev = adapter->rtw_wdev;
++	u8 *frame = get_recvframe_data(rframe);
++	uint frame_len = rframe->u.hdr.len;
++	s32 freq;
++	u8 ch, sch = rtw_get_oper_ch(adapter);
++
++	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
++	freq = rtw_ch2freq(ch);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
++#else
++	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
++#endif
++
++	RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n", ch, sch, MAC_ARG(get_addr2_ptr(frame)));
++	if (!rtw_sae_preprocess(adapter, frame, frame_len, _FALSE)) {
++		if (msg)
++			RTW_INFO("RTW_Rx:%s\n", msg);
++		else
++			RTW_INFO("RTW_Rx:frame_control:0x%02x\n", le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)rframe)->frame_ctl));
++	}
++}
++
++#ifdef CONFIG_P2P
++void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len)
++{
++	u16	wps_devicepassword_id = 0x0000;
++	uint	wps_devicepassword_id_len = 0;
++	u8			wpsie[255] = { 0x00 }, p2p_ie[255] = { 0x00 };
++	uint			p2p_ielen = 0;
++	uint			wpsielen = 0;
++	u32	devinfo_contentlen = 0;
++	u8	devinfo_content[64] = { 0x00 };
++	u16	capability = 0;
++	uint capability_len = 0;
++
++	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
++	u8			action = P2P_PUB_ACTION_ACTION;
++	u8			dialogToken = 1;
++	u32			p2poui = cpu_to_be32(P2POUI);
++	u8			oui_subtype = P2P_PROVISION_DISC_REQ;
++	u32			p2pielen = 0;
++#ifdef CONFIG_WFD
++	u32					wfdielen = 0;
++#endif
++
++	struct xmit_frame			*pmgntframe;
++	struct pkt_attrib			*pattrib;
++	unsigned char					*pframe;
++	struct rtw_ieee80211_hdr	*pwlanhdr;
++	unsigned short				*fctrl;
++	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++	u8 *frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr));
++	size_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr);
++
++
++	RTW_INFO("[%s] In\n", __FUNCTION__);
++
++	/* prepare for building provision_request frame	 */
++	_rtw_memcpy(pwdinfo->tx_prov_disc_info.peerIFAddr, GetAddr1Ptr(buf), ETH_ALEN);
++	_rtw_memcpy(pwdinfo->tx_prov_disc_info.peerDevAddr, GetAddr1Ptr(buf), ETH_ALEN);
++
++	pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON;
++
++	rtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen);
++	rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8 *) &wps_devicepassword_id, &wps_devicepassword_id_len);
++	wps_devicepassword_id = be16_to_cpu(wps_devicepassword_id);
++
++	switch (wps_devicepassword_id) {
++	case WPS_DPID_PIN:
++		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL;
++		break;
++	case WPS_DPID_USER_SPEC:
++		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA;
++		break;
++	case WPS_DPID_MACHINE_SPEC:
++		break;
++	case WPS_DPID_REKEY:
++		break;
++	case WPS_DPID_PBC:
++		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON;
++		break;
++	case WPS_DPID_REGISTRAR_SPEC:
++		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD;
++		break;
++	default:
++		break;
++	}
++
++
++	if (rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, p2p_ie, &p2p_ielen)) {
++
++		rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, devinfo_content, &devinfo_contentlen);
++		rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&capability, &capability_len);
++
++	}
++
++
++	/* start to build provision_request frame	 */
++	_rtw_memset(wpsie, 0, sizeof(wpsie));
++	_rtw_memset(p2p_ie, 0, sizeof(p2p_ie));
++	p2p_ielen = 0;
++
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL)
++		return;
++
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	fctrl = &(pwlanhdr->frame_ctl);
++	*(fctrl) = 0;
++
++	_rtw_memcpy(pwlanhdr->addr1, pwdinfo->tx_prov_disc_info.peerDevAddr, ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pwlanhdr->addr3, pwdinfo->tx_prov_disc_info.peerDevAddr, ETH_ALEN);
++
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++	set_frame_sub_type(pframe, WIFI_ACTION);
++
++	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
++	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
++
++	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
++	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
++
++
++	/* build_prov_disc_request_p2p_ie	 */
++	/*	P2P OUI */
++	p2pielen = 0;
++	p2p_ie[p2pielen++] = 0x50;
++	p2p_ie[p2pielen++] = 0x6F;
++	p2p_ie[p2pielen++] = 0x9A;
++	p2p_ie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
++
++	/*	Commented by Albert 20110301 */
++	/*	According to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes */
++	/*	1. P2P Capability */
++	/*	2. Device Info */
++	/*	3. Group ID ( When joining an operating P2P Group ) */
++
++	/*	P2P Capability ATTR */
++	/*	Type:	 */
++	p2p_ie[p2pielen++] = P2P_ATTR_CAPABILITY;
++
++	/*	Length: */
++	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); */
++	RTW_PUT_LE16(p2p_ie + p2pielen, 0x0002);
++	p2pielen += 2;
++
++	/*	Value: */
++	/*	Device Capability Bitmap, 1 byte */
++	/*	Group Capability Bitmap, 1 byte */
++	_rtw_memcpy(p2p_ie + p2pielen, &capability, 2);
++	p2pielen += 2;
++
++
++	/*	Device Info ATTR */
++	/*	Type: */
++	p2p_ie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
++
++	/*	Length: */
++	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
++	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
++	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); */
++	RTW_PUT_LE16(p2p_ie + p2pielen, devinfo_contentlen);
++	p2pielen += 2;
++
++	/*	Value: */
++	_rtw_memcpy(p2p_ie + p2pielen, devinfo_content, devinfo_contentlen);
++	p2pielen += devinfo_contentlen;
++
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2p_ie, &p2p_ielen);
++	/* p2pielen = build_prov_disc_request_p2p_ie( pwdinfo, pframe, NULL, 0, pwdinfo->tx_prov_disc_info.peerDevAddr); */
++	/* pframe += p2pielen; */
++	pattrib->pktlen += p2p_ielen;
++
++	wpsielen = 0;
++	/*	WPS OUI */
++	*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
++	wpsielen += 4;
++
++	/*	WPS version */
++	/*	Type: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
++	wpsielen += 2;
++
++	/*	Length: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
++	wpsielen += 2;
++
++	/*	Value: */
++	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
++
++	/*	Config Method */
++	/*	Type: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);
++	wpsielen += 2;
++
++	/*	Length: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
++	wpsielen += 2;
++
++	/*	Value: */
++	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->tx_prov_disc_info.wps_config_method_request);
++	wpsielen += 2;
++
++	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
++
++
++#ifdef CONFIG_WFD
++	wfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe);
++	pframe += wfdielen;
++	pattrib->pktlen += wfdielen;
++#endif
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	/* dump_mgntframe(padapter, pmgntframe); */
++	if (dump_mgntframe_and_wait_ack(padapter, pmgntframe) != _SUCCESS)
++		RTW_INFO("%s, ack to\n", __func__);
++
++	#if 0
++	if(wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC) {
++		RTW_INFO("waiting for p2p peer key-in PIN CODE\n");
++		rtw_msleep_os(15000); /* 15 sec for key in PIN CODE, workaround for GS2 before issuing Nego Req. */
++	}
++	#endif
++
++}
++
++#ifdef CONFIG_RTW_80211R
++static s32 cfg80211_rtw_update_ft_ies(struct wiphy *wiphy,
++	struct net_device *ndev,
++	struct cfg80211_update_ft_ies_params *ftie)
++{
++	_adapter *padapter = NULL;
++	struct mlme_priv *pmlmepriv = NULL;
++	struct ft_roam_info *pft_roam = NULL;
++	_irqL irqL;
++	u8 *p;
++	u8 *pie = NULL;
++	u32 ie_len = 0;
++
++	if (ndev == NULL)
++		return  -EINVAL;
++
++	padapter = (_adapter *)rtw_netdev_priv(ndev);
++	pmlmepriv = &(padapter->mlmepriv);
++	pft_roam = &(pmlmepriv->ft_roam);
++
++	p = (u8 *)ftie->ie;
++	if (ftie->ie_len <= sizeof(pft_roam->updated_ft_ies)) {
++		_enter_critical_bh(&pmlmepriv->lock, &irqL);
++		_rtw_memcpy(pft_roam->updated_ft_ies, ftie->ie, ftie->ie_len);
++		pft_roam->updated_ft_ies_len = ftie->ie_len;
++		_exit_critical_bh(&pmlmepriv->lock, &irqL);
++	} else {
++		RTW_ERR("FTIEs parsing fail!\n");
++		return -EINVAL;
++	}
++
++	if (rtw_ft_roam_status(padapter, RTW_FT_AUTHENTICATED_STA)) {
++		RTW_PRINT("auth success, start reassoc\n");
++		rtw_ft_lock_set_status(padapter, RTW_FT_ASSOCIATING_STA, &irqL);
++		start_clnt_assoc(padapter);
++	}
++
++	return 0;
++}
++#endif
++
++inline void rtw_cfg80211_set_is_roch(_adapter *adapter, bool val)
++{
++	adapter->cfg80211_wdinfo.is_ro_ch = val;
++	rtw_mi_update_iface_status(&(adapter->mlmepriv), 0);
++}
++
++inline bool rtw_cfg80211_get_is_roch(_adapter *adapter)
++{
++	return adapter->cfg80211_wdinfo.is_ro_ch;
++}
++
++inline bool rtw_cfg80211_is_ro_ch_once(_adapter *adapter)
++{
++	return adapter->cfg80211_wdinfo.last_ro_ch_time ? 1 : 0;
++}
++
++inline void rtw_cfg80211_set_last_ro_ch_time(_adapter *adapter)
++{
++	adapter->cfg80211_wdinfo.last_ro_ch_time = rtw_get_current_time();
++
++	if (!adapter->cfg80211_wdinfo.last_ro_ch_time)
++		adapter->cfg80211_wdinfo.last_ro_ch_time++;
++}
++
++inline s32 rtw_cfg80211_get_last_ro_ch_passing_ms(_adapter *adapter)
++{
++	return rtw_get_passing_time_ms(adapter->cfg80211_wdinfo.last_ro_ch_time);
++}
++
++static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	struct wireless_dev *wdev,
++#else
++	struct net_device *ndev,
++#endif
++	struct ieee80211_channel *channel,
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
++	enum nl80211_channel_type channel_type,
++#endif
++	unsigned int duration, u64 *cookie)
++{
++	s32 err = 0;
++	u8 remain_ch = (u8) ieee80211_frequency_to_channel(channel->center_freq);
++	_adapter *padapter = NULL;
++	struct rtw_wdev_priv *pwdev_priv;
++	struct wifidirect_info *pwdinfo;
++	struct cfg80211_wifidirect_info *pcfg80211_wdinfo;
++#ifdef CONFIG_CONCURRENT_MODE
++	u8 is_p2p_find = _FALSE;
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	#if defined(RTW_DEDICATED_P2P_DEVICE)
++	if (wdev == wiphy_to_pd_wdev(wiphy))
++		padapter = wiphy_to_adapter(wiphy);
++	else
++	#endif
++	if (wdev_to_ndev(wdev))
++		padapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));
++	else {
++		err = -EINVAL;
++		goto exit;
++	}
++#else
++	struct wireless_dev *wdev;
++
++	if (ndev == NULL) {
++		err = -EINVAL;
++		goto exit;
++	}
++	padapter = (_adapter *)rtw_netdev_priv(ndev);
++	wdev = ndev_to_wdev(ndev);
++#endif
++
++	pwdev_priv = adapter_wdev_data(padapter);
++	pwdinfo = &padapter->wdinfo;
++	pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;
++#ifdef CONFIG_CONCURRENT_MODE
++	is_p2p_find = (duration < (pwdinfo->ext_listen_interval)) ? _TRUE : _FALSE;
++#endif
++
++	*cookie = ATOMIC_INC_RETURN(&pcfg80211_wdinfo->ro_ch_cookie_gen);
++
++	RTW_INFO(FUNC_ADPT_FMT"%s ch:%u duration:%d, cookie:0x%llx\n"
++		, FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : ""
++		, remain_ch, duration, *cookie);
++
++	if (rtw_chset_search_ch(adapter_to_chset(padapter), remain_ch) < 0) {
++		RTW_WARN(FUNC_ADPT_FMT" invalid ch:%u\n", FUNC_ADPT_ARG(padapter), remain_ch);
++		err = -EFAULT;
++		goto exit;
++	}
++
++#ifdef CONFIG_MP_INCLUDED
++	if (rtw_mp_mode_check(padapter)) {
++		RTW_INFO("MP mode block remain_on_channel request\n");
++		err = -EFAULT;
++		goto exit;
++	}
++#endif
++
++	if (_FAIL == rtw_pwr_wakeup(padapter)) {
++		err = -EFAULT;
++		goto exit;
++	}
++
++	rtw_scan_abort(padapter);
++#ifdef CONFIG_CONCURRENT_MODE
++	/*don't scan_abort during p2p_listen.*/
++	if (is_p2p_find)
++		rtw_mi_buddy_scan_abort(padapter, _TRUE);
++#endif /*CONFIG_CONCURRENT_MODE*/
++
++	if (rtw_cfg80211_get_is_roch(padapter) == _TRUE) {
++		_cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer);
++		p2p_cancel_roch_cmd(padapter, 0, NULL, RTW_CMDF_WAIT_ACK);
++	}
++
++	/* if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) */
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
++		#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_P2P)
++		&& ((padapter->iface_id == padapter->registrypriv.sel_p2p_iface))
++		#endif
++	) {
++		rtw_p2p_enable(padapter, P2P_ROLE_DEVICE);
++		padapter->wdinfo.listen_channel = remain_ch;
++		RTW_INFO(FUNC_ADPT_FMT" init listen_channel %u\n"
++			, FUNC_ADPT_ARG(padapter), padapter->wdinfo.listen_channel);
++	} else if (rtw_p2p_chk_state(pwdinfo , P2P_STATE_LISTEN)
++		&& (time_after_eq(rtw_get_current_time(), pwdev_priv->probe_resp_ie_update_time)
++			&& rtw_get_passing_time_ms(pwdev_priv->probe_resp_ie_update_time) < 50)
++	) {
++		if (padapter->wdinfo.listen_channel != remain_ch) {
++			padapter->wdinfo.listen_channel = remain_ch;
++			RTW_INFO(FUNC_ADPT_FMT" update listen_channel %u\n"
++				, FUNC_ADPT_ARG(padapter), padapter->wdinfo.listen_channel);
++		}
++	} else {
++		rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++#ifdef CONFIG_DEBUG_CFG80211
++		RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));
++#endif
++	}
++
++	rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
++
++	#ifdef RTW_ROCH_DURATION_ENLARGE
++	if (duration < 400)
++		duration = duration * 3; /* extend from exper */
++	#endif
++
++#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE)
++	if (rtw_mi_check_status(padapter, MI_LINKED)) {
++		if (is_p2p_find) /* p2p_find , duration<1000 */
++			duration = duration + pwdinfo->ext_listen_interval;
++	}
++#endif /*defined (RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE) */
++
++	rtw_cfg80211_set_is_roch(padapter, _TRUE);
++	pcfg80211_wdinfo->ro_ch_wdev = wdev;
++	pcfg80211_wdinfo->remain_on_ch_cookie = *cookie;
++	rtw_cfg80211_set_last_ro_ch_time(padapter);
++	_rtw_memcpy(&pcfg80211_wdinfo->remain_on_ch_channel, channel, sizeof(struct ieee80211_channel));
++	#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
++	pcfg80211_wdinfo->remain_on_ch_type = channel_type;
++	#endif
++	pcfg80211_wdinfo->restore_channel = rtw_get_oper_ch(padapter);
++
++	p2p_roch_cmd(padapter, *cookie, wdev, channel, pcfg80211_wdinfo->remain_on_ch_type,
++		duration, RTW_CMDF_WAIT_ACK);
++
++	rtw_cfg80211_ready_on_channel(wdev, *cookie, channel, channel_type, duration, GFP_KERNEL);
++exit:
++	return err;
++}
++
++static s32 cfg80211_rtw_cancel_remain_on_channel(struct wiphy *wiphy,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	struct wireless_dev *wdev,
++#else
++	struct net_device *ndev,
++#endif
++	u64 cookie)
++{
++	s32 err = 0;
++	_adapter *padapter;
++	struct rtw_wdev_priv *pwdev_priv;
++	struct wifidirect_info *pwdinfo;
++	struct cfg80211_wifidirect_info *pcfg80211_wdinfo;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	#if defined(RTW_DEDICATED_P2P_DEVICE)
++	if (wdev == wiphy_to_pd_wdev(wiphy))
++		padapter = wiphy_to_adapter(wiphy);
++	else
++	#endif
++	if (wdev_to_ndev(wdev))
++		padapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));
++	else {
++		err = -EINVAL;
++		goto exit;
++	}
++#else
++	struct wireless_dev *wdev;
++
++	if (ndev == NULL) {
++		err = -EINVAL;
++		goto exit;
++	}
++	padapter = (_adapter *)rtw_netdev_priv(ndev);
++	wdev = ndev_to_wdev(ndev);
++#endif
++
++	pwdev_priv = adapter_wdev_data(padapter);
++	pwdinfo = &padapter->wdinfo;
++	pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;
++
++	RTW_INFO(FUNC_ADPT_FMT"%s cookie:0x%llx\n"
++		, FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : ""
++		, cookie);
++
++	if (rtw_cfg80211_get_is_roch(padapter) == _TRUE) {
++		_cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer);
++		p2p_cancel_roch_cmd(padapter, cookie, wdev, RTW_CMDF_WAIT_ACK);
++	}
++
++exit:
++	return err;
++}
++
++inline int rtw_cfg80211_iface_has_p2p_group_cap(_adapter *adapter)
++{
++#if RTW_P2P_GROUP_INTERFACE
++	if (is_primary_adapter(adapter))
++		return 0;
++#endif
++	return 1;
++}
++
++inline int rtw_cfg80211_is_p2p_scan(_adapter *adapter)
++{
++#if RTW_P2P_GROUP_INTERFACE
++	if (rtw_cfg80211_iface_has_p2p_group_cap(adapter))
++#endif
++	{
++		struct wifidirect_info *wdinfo = &adapter->wdinfo;
++
++		return rtw_p2p_chk_state(wdinfo, P2P_STATE_SCAN)
++			|| rtw_p2p_chk_state(wdinfo, P2P_STATE_FIND_PHASE_SEARCH);
++	}
++
++#if RTW_P2P_GROUP_INTERFACE
++	#if defined(RTW_DEDICATED_P2P_DEVICE)
++	if (wiphy_to_pd_wdev(adapter_to_wiphy(adapter))) /* pd_wdev exist */
++		return rtw_cfg80211_is_scan_by_pd_wdev(adapter);
++	#endif
++	{
++		/*
++		* For 2 RTW_P2P_GROUP_INTERFACE cases:
++		* 1. RTW_DEDICATED_P2P_DEVICE defined but upper layer don't use pd_wdev or
++		* 2. RTW_DEDICATED_P2P_DEVICE not defined
++		*/
++		struct rtw_wdev_priv *wdev_data = adapter_wdev_data(adapter);
++		_irqL irqL;
++		int is_p2p_scan = 0;
++
++		_enter_critical_bh(&wdev_data->scan_req_lock, &irqL);
++		if (wdev_data->scan_request
++			&& wdev_data->scan_request->n_ssids
++			&& wdev_data->scan_request->ssids
++			&& wdev_data->scan_request->ie
++		) {
++			if (_rtw_memcmp(wdev_data->scan_request->ssids[0].ssid, "DIRECT-", 7)
++				&& rtw_get_p2p_ie((u8 *)wdev_data->scan_request->ie, wdev_data->scan_request->ie_len, NULL, NULL))
++				is_p2p_scan = 1;
++		}
++		_exit_critical_bh(&wdev_data->scan_req_lock, &irqL);
++
++		return is_p2p_scan;
++	}
++#endif
++}
++
++#if defined(RTW_DEDICATED_P2P_DEVICE)
++int rtw_pd_iface_alloc(struct wiphy *wiphy, const char *name, struct wireless_dev **pd_wdev)
++{
++	struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy);
++	struct wireless_dev *wdev = NULL;
++	struct rtw_netdev_priv_indicator *npi;
++	_adapter *primary_adpt = wiphy_to_adapter(wiphy);
++	int ret = 0;
++
++	if (wiphy_data->pd_wdev) {
++		RTW_WARN(FUNC_WIPHY_FMT" pd_wdev already exists\n", FUNC_WIPHY_ARG(wiphy));
++		ret = -EBUSY;
++		goto exit;
++	}
++
++	wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev));
++	if (!wdev) {
++		RTW_WARN(FUNC_WIPHY_FMT" allocate wdev fail\n", FUNC_WIPHY_ARG(wiphy));
++		ret = -ENOMEM;
++		goto exit;
++	}
++
++	wdev->wiphy = wiphy;
++	wdev->iftype = NL80211_IFTYPE_P2P_DEVICE;
++	_rtw_memcpy(wdev->address, adapter_mac_addr(primary_adpt), ETH_ALEN);
++
++	wiphy_data->pd_wdev = wdev;
++	*pd_wdev = wdev;
++
++	RTW_INFO(FUNC_WIPHY_FMT" pd_wdev:%p, addr="MAC_FMT" added\n"
++		, FUNC_WIPHY_ARG(wiphy), wdev, MAC_ARG(wdev_address(wdev)));
++
++exit:
++	if (ret && wdev) {
++		rtw_mfree((u8 *)wdev, sizeof(struct wireless_dev));
++		wdev = NULL;
++	}
++
++	return ret;
++}
++
++void rtw_pd_iface_free(struct wiphy *wiphy)
++{
++	struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);
++	struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy);
++	u8 rtnl_lock_needed;
++
++	if (!wiphy_data->pd_wdev)
++		goto exit;
++
++	RTW_INFO(FUNC_WIPHY_FMT" pd_wdev:%p, addr="MAC_FMT"\n"
++		, FUNC_WIPHY_ARG(wiphy), wiphy_data->pd_wdev
++		, MAC_ARG(wdev_address(wiphy_data->pd_wdev)));
++
++	rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj);
++	if (rtnl_lock_needed)
++		rtnl_lock();
++	cfg80211_unregister_wdev(wiphy_data->pd_wdev);
++	if (rtnl_lock_needed)
++		rtnl_unlock();
++
++	rtw_mfree((u8 *)wiphy_data->pd_wdev, sizeof(struct wireless_dev));
++	wiphy_data->pd_wdev = NULL;
++
++exit:
++	return;
++}
++
++static int cfg80211_rtw_start_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev)
++{
++	_adapter *adapter = wiphy_to_adapter(wiphy);
++
++	RTW_INFO(FUNC_WIPHY_FMT" wdev=%p\n", FUNC_WIPHY_ARG(wiphy), wdev);
++
++	rtw_p2p_enable(adapter, P2P_ROLE_DEVICE);
++	return 0;
++}
++
++static void cfg80211_rtw_stop_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev)
++{
++	_adapter *adapter = wiphy_to_adapter(wiphy);
++
++	RTW_INFO(FUNC_WIPHY_FMT" wdev=%p\n", FUNC_WIPHY_ARG(wiphy), wdev);
++
++	if (rtw_cfg80211_is_p2p_scan(adapter))
++		rtw_scan_abort(adapter);
++
++	rtw_p2p_enable(adapter, P2P_ROLE_DISABLE);
++}
++
++inline int rtw_cfg80211_redirect_pd_wdev(struct wiphy *wiphy, u8 *ra, struct wireless_dev **wdev)
++{
++	struct wireless_dev *pd_wdev = wiphy_to_pd_wdev(wiphy);
++
++	if (pd_wdev && pd_wdev != *wdev
++		&& _rtw_memcmp(wdev_address(pd_wdev), ra, ETH_ALEN) == _TRUE
++	) {
++		*wdev = pd_wdev;
++		return 1;
++	}
++	return 0;
++}
++
++inline int rtw_cfg80211_is_scan_by_pd_wdev(_adapter *adapter)
++{
++	struct wiphy *wiphy = adapter_to_wiphy(adapter);
++	struct rtw_wdev_priv *wdev_data = adapter_wdev_data(adapter);
++	struct wireless_dev *wdev = NULL;
++	_irqL irqL;
++
++	_enter_critical_bh(&wdev_data->scan_req_lock, &irqL);
++	if (wdev_data->scan_request)
++		wdev = wdev_data->scan_request->wdev;
++	_exit_critical_bh(&wdev_data->scan_req_lock, &irqL);
++
++	if (wdev && wdev == wiphy_to_pd_wdev(wiphy))
++		return 1;
++
++	return 0;
++}
++#endif /* RTW_DEDICATED_P2P_DEVICE */
++#endif /* CONFIG_P2P */
++
++inline void rtw_cfg80211_set_is_mgmt_tx(_adapter *adapter, u8 val)
++{
++	struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter);
++
++	wdev_priv->is_mgmt_tx = val;
++	rtw_mi_update_iface_status(&(adapter->mlmepriv), 0);
++}
++
++inline u8 rtw_cfg80211_get_is_mgmt_tx(_adapter *adapter)
++{
++	struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter);
++
++	return wdev_priv->is_mgmt_tx;
++}
++
++static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack)
++{
++	struct xmit_frame	*pmgntframe;
++	struct pkt_attrib	*pattrib;
++	unsigned char	*pframe;
++	int ret = _FAIL;
++	bool ack = _TRUE;
++	struct rtw_ieee80211_hdr *pwlanhdr;
++#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++#endif
++	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	u8 u_ch = rtw_mi_get_union_chan(padapter);
++	u8 leave_op = 0;
++#ifdef CONFIG_P2P
++	struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;
++	#ifdef CONFIG_CONCURRENT_MODE
++	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++	#endif
++#endif
++
++	rtw_cfg80211_set_is_mgmt_tx(padapter, 1);
++
++#ifdef CONFIG_BT_COEXIST
++	rtw_btcoex_ScanNotify(padapter, _TRUE);
++#endif
++
++#ifdef CONFIG_P2P
++	if (rtw_cfg80211_get_is_roch(padapter) == _TRUE) {
++		#ifdef CONFIG_CONCURRENT_MODE
++		if (!check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) {
++			RTW_INFO("%s, extend ro ch time\n", __func__);
++			_set_timer(&padapter->cfg80211_wdinfo.remain_on_ch_timer, pwdinfo->ext_listen_period);
++		}
++		#endif /* CONFIG_CONCURRENT_MODE */
++	}
++#endif /* CONFIG_P2P */
++
++#ifdef CONFIG_MCC_MODE
++	if (MCC_EN(padapter)) {
++		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
++			/* don't set channel, issue frame directly */
++			goto issue_mgmt_frame;
++	}
++#endif /* CONFIG_MCC_MODE */
++
++	if (rtw_mi_check_status(padapter, MI_LINKED)
++		&& tx_ch != u_ch
++	) {
++		rtw_leave_opch(padapter);
++		leave_op = 1;
++	}
++
++	if (tx_ch != rtw_get_oper_ch(padapter))
++		set_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++#ifdef CONFIG_MCC_MODE
++issue_mgmt_frame:
++#endif
++	/* starting alloc mgmt frame to dump it */
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL) {
++		/* ret = -ENOMEM; */
++		ret = _FAIL;
++		goto exit;
++	}
++
++	/* update attribute */
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++
++	if (no_cck && IS_CCK_RATE(pattrib->rate)) {
++		/* force OFDM 6M rate*/
++		pattrib->rate = MGN_6M;
++		pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G);
++	}
++
++	pattrib->retry_ctrl = _FALSE;
++
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++
++	_rtw_memcpy(pframe, (void *)buf, len);
++	pattrib->pktlen = len;
++
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++	/* update seq number */
++	pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
++	pattrib->seqnum = pmlmeext->mgnt_seq;
++	pmlmeext->mgnt_seq++;
++
++#ifdef CONFIG_P2P
++	rtw_xframe_chk_wfd_ie(pmgntframe);
++#endif /* CONFIG_P2P */
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++
++	if (wait_ack) {
++		if (dump_mgntframe_and_wait_ack(padapter, pmgntframe) != _SUCCESS) {
++			ack = _FALSE;
++			ret = _FAIL;
++
++#ifdef CONFIG_DEBUG_CFG80211
++			RTW_INFO("%s, ack == _FAIL\n", __func__);
++#endif
++		} else {
++
++#ifdef CONFIG_XMIT_ACK
++			if (!MLME_IS_MESH(padapter)) /* TODO: remove this sleep for all mode */
++				rtw_msleep_os(50);
++#endif
++#ifdef CONFIG_DEBUG_CFG80211
++			RTW_INFO("%s, ack=%d, ok!\n", __func__, ack);
++#endif
++			ret = _SUCCESS;
++		}
++	} else {
++		dump_mgntframe(padapter, pmgntframe);
++		ret = _SUCCESS;
++	}
++
++exit:
++	#ifdef CONFIG_P2P
++	if (rtw_cfg80211_get_is_roch(padapter)
++		&& !roch_stay_in_cur_chan(padapter)
++		&& pcfg80211_wdinfo->remain_on_ch_channel.hw_value != u_ch
++	) {
++		/* roch is ongoing, switch back to rch */
++		if (pcfg80211_wdinfo->remain_on_ch_channel.hw_value != tx_ch)
++			set_channel_bwmode(padapter, pcfg80211_wdinfo->remain_on_ch_channel.hw_value
++				, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++	} else
++	#endif
++	if (leave_op) {
++		if (rtw_mi_check_status(padapter, MI_LINKED)) {
++			u8 u_bw = rtw_mi_get_union_bw(padapter);
++			u8 u_offset = rtw_mi_get_union_offset(padapter);
++
++			set_channel_bwmode(padapter, u_ch, u_offset, u_bw);
++		}
++		rtw_back_opch(padapter);
++	}
++
++	rtw_cfg80211_set_is_mgmt_tx(padapter, 0);
++
++#ifdef CONFIG_BT_COEXIST
++	rtw_btcoex_ScanNotify(padapter, _FALSE);
++#endif
++
++#ifdef CONFIG_DEBUG_CFG80211
++	RTW_INFO("%s, ret=%d\n", __func__, ret);
++#endif
++
++	return ret;
++
++}
++
++u8 rtw_mgnt_tx_handler(_adapter *adapter, u8 *buf)
++{
++	u8 rst = H2C_CMD_FAIL;
++	struct mgnt_tx_parm *mgnt_parm = (struct mgnt_tx_parm *)buf;
++
++	if (_cfg80211_rtw_mgmt_tx(adapter, mgnt_parm->tx_ch, mgnt_parm->no_cck,
++		mgnt_parm->buf, mgnt_parm->len, mgnt_parm->wait_ack) == _SUCCESS)
++		rst = H2C_SUCCESS;
++
++	return rst;
++}
++
++static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	struct wireless_dev *wdev,
++#else
++	struct net_device *ndev,
++#endif
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) || defined(COMPAT_KERNEL_RELEASE)
++	struct ieee80211_channel *chan,
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
++	bool offchan,
++	#endif
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
++	enum nl80211_channel_type channel_type,
++	#endif
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
++	bool channel_type_valid,
++	#endif
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
++	unsigned int wait,
++	#endif
++	const u8 *buf, size_t len,
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	bool no_cck,
++	#endif
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
++	bool dont_wait_for_ack,
++	#endif
++#else
++	struct cfg80211_mgmt_tx_params *params,
++#endif
++	u64 *cookie)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(COMPAT_KERNEL_RELEASE)
++	struct ieee80211_channel *chan = params->chan;
++	const u8 *buf = params->buf;
++	size_t len = params->len;
++	bool no_cck = params->no_cck;
++#endif
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0))
++	bool no_cck = 0;
++#endif
++	int ret = 0;
++	u8 tx_ret;
++	int wait_ack = 1;
++	const u8 *dump_buf = buf;
++	size_t dump_len = len;
++	u32 dump_limit = RTW_MAX_MGMT_TX_CNT;
++	u32 dump_cnt = 0;
++	u32 sleep_ms = 0;
++	u32 retry_guarantee_ms = 0;
++	bool ack = _TRUE;
++	u8 tx_ch;
++	u8 category, action;
++	u8 frame_styp;
++#ifdef CONFIG_P2P
++	u8 is_p2p = 0;
++#endif
++	int type = (-1);
++	systime start = rtw_get_current_time();
++	_adapter *padapter;
++	struct dvobj_priv *dvobj;
++	struct rtw_wdev_priv *pwdev_priv;
++	struct rf_ctl_t *rfctl;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	#if defined(RTW_DEDICATED_P2P_DEVICE)
++	if (wdev == wiphy_to_pd_wdev(wiphy))
++		padapter = wiphy_to_adapter(wiphy);
++	else
++	#endif
++	if (wdev_to_ndev(wdev))
++		padapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));
++	else {
++		ret = -EINVAL;
++		goto exit;
++	}
++#else
++	struct wireless_dev *wdev;
++
++	if (ndev == NULL) {
++		ret = -EINVAL;
++		goto exit;
++	}
++	padapter = (_adapter *)rtw_netdev_priv(ndev);
++	wdev = ndev_to_wdev(ndev);
++#endif
++
++	if (chan == NULL) {
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	rfctl = adapter_to_rfctl(padapter);
++	tx_ch = (u8)ieee80211_frequency_to_channel(chan->center_freq);
++	if (IS_CH_WAITING(rfctl)) {
++		#ifdef CONFIG_DFS_MASTER
++		if (_rtw_rfctl_overlap_radar_detect_ch(rfctl, tx_ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE)) {
++			ret = -EINVAL;
++			goto exit;
++		}
++		#endif
++	}
++
++	dvobj = adapter_to_dvobj(padapter);
++	pwdev_priv = adapter_wdev_data(padapter);
++
++	/* cookie generation */
++	*cookie = pwdev_priv->mgmt_tx_cookie++;
++
++#ifdef CONFIG_DEBUG_CFG80211
++	RTW_INFO(FUNC_ADPT_FMT"%s len=%zu, ch=%d"
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
++		", ch_type=%d"
++		#endif
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
++		", channel_type_valid=%d"
++		#endif
++		"\n", FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : ""
++		, len, tx_ch
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
++		, channel_type
++		#endif
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
++		, channel_type_valid
++		#endif
++	);
++#endif /* CONFIG_DEBUG_CFG80211 */
++
++	/* indicate ack before issue frame to avoid racing with rsp frame */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++	rtw_cfg80211_mgmt_tx_status(wdev, *cookie, buf, len, ack, GFP_KERNEL);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 36))
++	cfg80211_action_tx_status(ndev, *cookie, buf, len, ack, GFP_KERNEL);
++#endif
++
++	frame_styp = le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl) & IEEE80211_FCTL_STYPE;
++	if (IEEE80211_STYPE_PROBE_RESP == frame_styp) {
++#ifdef CONFIG_DEBUG_CFG80211
++		RTW_INFO("RTW_Tx: probe_resp tx_ch=%d, no_cck=%u, da="MAC_FMT"\n", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf)));
++#endif /* CONFIG_DEBUG_CFG80211 */
++		wait_ack = 0;
++		goto dump;
++	}
++	else if (frame_styp == RTW_IEEE80211_STYPE_AUTH) {
++		int retval = 0;
++
++		RTW_INFO("RTW_Tx:tx_ch=%d, no_cck=%u, da="MAC_FMT"\n", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf)));
++
++		retval = rtw_sae_preprocess(padapter, buf, len, _TRUE);
++		if (retval == 2)
++			goto exit;
++		if (retval == 0)
++			RTW_INFO("RTW_Tx:AUTH\n");
++		dump_limit = 1;
++		goto dump;
++	}
++
++	if (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) {
++		RTW_INFO(FUNC_ADPT_FMT" frame_control:0x%02x\n", FUNC_ADPT_ARG(padapter),
++			le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl));
++		goto exit;
++	}
++
++	RTW_INFO("RTW_Tx:tx_ch=%d, no_cck=%u, da="MAC_FMT"\n", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf)));
++#ifdef CONFIG_P2P
++	type = rtw_p2p_check_frames(padapter, buf, len, _TRUE);
++	if (type >= 0) {
++		is_p2p = 1;
++		no_cck = 1; /* force no CCK for P2P frames */
++		goto dump;
++	}
++#endif
++#ifdef CONFIG_RTW_MESH
++	if (MLME_IS_MESH(padapter)) {
++		type = rtw_mesh_check_frames_tx(padapter, &dump_buf, &dump_len);
++		if (type >= 0) {
++			dump_limit = 1;
++			goto dump;
++		}
++	}
++#endif
++	if (category == RTW_WLAN_CATEGORY_PUBLIC) {
++		RTW_INFO("RTW_Tx:%s\n", action_public_str(action));
++		switch (action) {
++		case ACT_PUBLIC_GAS_INITIAL_REQ:
++		case ACT_PUBLIC_GAS_INITIAL_RSP:
++			sleep_ms = 50;
++			retry_guarantee_ms = RTW_MAX_MGMT_TX_MS_GAS;
++			break;
++		}
++	}
++#ifdef CONFIG_RTW_80211K
++	else if (category == RTW_WLAN_CATEGORY_RADIO_MEAS)
++		RTW_INFO("RTW_Tx: RRM Action\n");
++#endif
++	else
++		RTW_INFO("RTW_Tx:category(%u), action(%u)\n", category, action);
++
++dump:
++
++	rtw_ps_deny(padapter, PS_DENY_MGNT_TX);
++	if (_FAIL == rtw_pwr_wakeup(padapter)) {
++		ret = -EFAULT;
++		goto cancel_ps_deny;
++	}
++
++	while (1) {
++		dump_cnt++;
++
++		rtw_mi_set_scan_deny(padapter, 1000);
++		rtw_mi_scan_abort(padapter, _TRUE);
++		tx_ret = rtw_mgnt_tx_cmd(padapter, tx_ch, no_cck, dump_buf, dump_len, wait_ack, RTW_CMDF_WAIT_ACK);
++		if (tx_ret == _SUCCESS
++			|| (dump_cnt >= dump_limit && rtw_get_passing_time_ms(start) >= retry_guarantee_ms))
++			break;
++
++		if (sleep_ms > 0)
++			rtw_msleep_os(sleep_ms);
++	}
++
++	if (tx_ret != _SUCCESS || dump_cnt > 1) {
++		RTW_INFO(FUNC_ADPT_FMT" %s (%d/%d) in %d ms\n", FUNC_ADPT_ARG(padapter),
++			tx_ret == _SUCCESS ? "OK" : "FAIL", dump_cnt, dump_limit, rtw_get_passing_time_ms(start));
++	}
++
++#ifdef CONFIG_P2P
++	if (is_p2p) {
++		switch (type) {
++		case P2P_GO_NEGO_CONF:
++			if (0) {
++				RTW_INFO(FUNC_ADPT_FMT" Nego confirm. state=%u, status=%u, iaddr="MAC_FMT"\n"
++					, FUNC_ADPT_ARG(padapter), pwdev_priv->nego_info.state, pwdev_priv->nego_info.status
++					, MAC_ARG(pwdev_priv->nego_info.iface_addr));
++			}
++			if (pwdev_priv->nego_info.state == 2
++				&& pwdev_priv->nego_info.status == 0
++				&& rtw_check_invalid_mac_address(pwdev_priv->nego_info.iface_addr, _FALSE) == _FALSE
++			) {
++				_adapter *intended_iface = dvobj_get_adapter_by_addr(dvobj, pwdev_priv->nego_info.iface_addr);
++
++				if (intended_iface) {
++					RTW_INFO(FUNC_ADPT_FMT" Nego confirm. Allow only "ADPT_FMT" to scan for 2000 ms\n"
++						, FUNC_ADPT_ARG(padapter), ADPT_ARG(intended_iface));
++					/* allow only intended_iface to do scan for 2000 ms */
++					rtw_mi_set_scan_deny(padapter, 2000);
++					rtw_clear_scan_deny(intended_iface);
++				}
++			}
++			break;
++		case P2P_INVIT_RESP:
++			if (pwdev_priv->invit_info.flags & BIT(0)
++				&& pwdev_priv->invit_info.status == 0
++			) {
++				rtw_clear_scan_deny(padapter);
++				RTW_INFO(FUNC_ADPT_FMT" agree with invitation of persistent group\n",
++					FUNC_ADPT_ARG(padapter));
++				#if !RTW_P2P_GROUP_INTERFACE
++				rtw_mi_buddy_set_scan_deny(padapter, 5000);
++				#endif
++				rtw_pwr_wakeup_ex(padapter, 5000);
++			}
++			break;
++		}
++	}
++#endif /* CONFIG_P2P */
++
++cancel_ps_deny:
++	rtw_ps_deny_cancel(padapter, PS_DENY_MGNT_TX);
++
++	if (dump_buf != buf)
++		rtw_mfree((u8 *)dump_buf, dump_len);
++exit:
++	return ret;
++}
++
++static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	struct wireless_dev *wdev,
++#else
++	struct net_device *ndev,
++#endif
++	u16 frame_type, bool reg)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	struct net_device *ndev = wdev_to_ndev(wdev);
++#endif
++	_adapter *adapter;
++
++	struct rtw_wdev_priv *pwdev_priv;
++
++	if (ndev == NULL)
++		goto exit;
++
++	adapter = (_adapter *)rtw_netdev_priv(ndev);
++	pwdev_priv = adapter_wdev_data(adapter);
++
++#ifdef CONFIG_DEBUG_CFG80211
++	RTW_INFO(FUNC_ADPT_FMT" frame_type:%x, reg:%d\n", FUNC_ADPT_ARG(adapter),
++		frame_type, reg);
++#endif
++
++	switch (frame_type) {
++	case IEEE80211_STYPE_AUTH: /* 0x00B0 */
++		if (reg > 0)
++			SET_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_AUTH, reg);
++		else
++			CLR_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_AUTH, reg);
++		break;
++#ifdef not_yet
++	case IEEE80211_STYPE_PROBE_REQ: /* 0x0040 */
++		if (reg > 0)
++			SET_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_PROBE_REQ, reg);
++		else
++			CLR_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_PROBE_REQ, reg);
++		break;
++	case IEEE80211_STYPE_ACTION: /* 0x00D0 */
++		if (reg > 0)
++			SET_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_ACTION, reg);
++		else
++			CLR_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_ACTION, reg);
++		break;
++#endif
++	default:
++		break;
++	}
++
++exit:
++	return;
++}
++
++#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy,
++	struct net_device *ndev,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++	const u8 *peer,
++#else
++	u8 *peer,
++#endif
++	u8 action_code,
++	u8 dialog_token,
++	u16 status_code,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))
++	u32 peer_capability,
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0))
++	bool initiator,
++#endif
++	const u8 *buf,
++	size_t len)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &pmlmeext->mlmext_info;
++	int ret = 0;
++	struct tdls_txmgmt txmgmt;
++
++	if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) {
++		RTW_INFO("Discard tdls action:%d, since hal doesn't support tdls\n", action_code);
++		goto discard;
++	}
++
++	if (rtw_is_tdls_enabled(padapter) == _FALSE) {
++		RTW_INFO("TDLS is not enabled\n");
++		goto discard;
++	}
++
++	if (rtw_tdls_is_driver_setup(padapter)) {
++		RTW_INFO("Discard tdls action:%d, let driver to set up direct link\n", action_code);
++		goto discard;
++	}
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++	_rtw_memcpy(txmgmt.peer, peer, ETH_ALEN);
++	txmgmt.action_code = action_code;
++	txmgmt.dialog_token = dialog_token;
++	txmgmt.status_code = status_code;
++	txmgmt.len = len;
++	txmgmt.buf = (u8 *)rtw_malloc(txmgmt.len);
++	if (txmgmt.buf == NULL) {
++		ret = -ENOMEM;
++		goto bad;
++	}
++	_rtw_memcpy(txmgmt.buf, (void *)buf, txmgmt.len);
++
++	/* Debug purpose */
++#if 1
++	RTW_INFO("%s %d\n", __FUNCTION__, __LINE__);
++	RTW_INFO("peer:"MAC_FMT", action code:%d, dialog:%d, status code:%d\n",
++		MAC_ARG(txmgmt.peer), txmgmt.action_code,
++		txmgmt.dialog_token, txmgmt.status_code);
++	if (txmgmt.len > 0) {
++		int i = 0;
++		for (; i < len; i++)
++			printk("%02x ", *(txmgmt.buf + i));
++		RTW_INFO("len:%d\n", (u32)txmgmt.len);
++	}
++#endif
++
++	switch (txmgmt.action_code) {
++	case TDLS_SETUP_REQUEST:
++		issue_tdls_setup_req(padapter, &txmgmt, _TRUE);
++		break;
++	case TDLS_SETUP_RESPONSE:
++		issue_tdls_setup_rsp(padapter, &txmgmt);
++		break;
++	case TDLS_SETUP_CONFIRM:
++		issue_tdls_setup_cfm(padapter, &txmgmt);
++		break;
++	case TDLS_TEARDOWN:
++		issue_tdls_teardown(padapter, &txmgmt, _TRUE);
++		break;
++	case TDLS_DISCOVERY_REQUEST:
++		issue_tdls_dis_req(padapter, &txmgmt);
++		break;
++	case TDLS_DISCOVERY_RESPONSE:
++		issue_tdls_dis_rsp(padapter, &txmgmt, pmlmeinfo->enc_algo ? _TRUE : _FALSE);
++		break;
++	}
++
++bad:
++	if (txmgmt.buf)
++		rtw_mfree(txmgmt.buf, txmgmt.len);
++
++discard:
++	return ret;
++}
++
++static int cfg80211_rtw_tdls_oper(struct wiphy *wiphy,
++	struct net_device *ndev,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++	const u8 *peer,
++#else
++	u8 *peer,
++#endif
++	enum nl80211_tdls_operation oper)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++	struct tdls_txmgmt	txmgmt;
++	struct sta_info *ptdls_sta = NULL;
++
++	RTW_INFO(FUNC_NDEV_FMT", nl80211_tdls_operation:%d\n", FUNC_NDEV_ARG(ndev), oper);
++
++	if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) {
++		RTW_INFO("Discard tdls oper:%d, since hal doesn't support tdls\n", oper);
++		return 0;
++	}
++
++	if (rtw_is_tdls_enabled(padapter) == _FALSE) {
++		RTW_INFO("TDLS is not enabled\n");
++		return 0;
++	}
++
++#ifdef CONFIG_LPS
++	rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0);
++#endif /* CONFIG_LPS */
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++	if (peer)
++		_rtw_memcpy(txmgmt.peer, peer, ETH_ALEN);
++
++	if (rtw_tdls_is_driver_setup(padapter)) {
++		/* these two cases are done by driver itself */
++		if (oper == NL80211_TDLS_ENABLE_LINK || oper == NL80211_TDLS_DISABLE_LINK)
++			return 0;
++	}
++
++	switch (oper) {
++	case NL80211_TDLS_DISCOVERY_REQ:
++		issue_tdls_dis_req(padapter, &txmgmt);
++		break;
++	case NL80211_TDLS_SETUP:
++#ifdef CONFIG_WFD
++		if (_AES_ != padapter->securitypriv.dot11PrivacyAlgrthm) {
++			if (padapter->wdinfo.wfd_tdls_weaksec == _TRUE)
++				issue_tdls_setup_req(padapter, &txmgmt, _TRUE);
++			else
++				RTW_INFO("[%s] Current link is not AES, SKIP sending the tdls setup request!!\n", __FUNCTION__);
++		} else
++#endif /* CONFIG_WFD */
++		{
++			issue_tdls_setup_req(padapter, &txmgmt, _TRUE);
++		}
++		break;
++	case NL80211_TDLS_TEARDOWN:
++		ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), txmgmt.peer);
++		if (ptdls_sta != NULL) {
++			txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;
++			issue_tdls_teardown(padapter, &txmgmt, _TRUE);
++		} else
++			RTW_INFO("TDLS peer not found\n");
++		break;
++	case NL80211_TDLS_ENABLE_LINK:
++		RTW_INFO(FUNC_NDEV_FMT", NL80211_TDLS_ENABLE_LINK;mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(peer));
++		ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer);
++		if (ptdls_sta != NULL) {
++			rtw_tdls_set_link_established(padapter, _TRUE);
++			ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE;
++			ptdls_sta->state |= WIFI_ASOC_STATE;
++			rtw_tdls_cmd(padapter, txmgmt.peer, TDLS_ESTABLISHED);
++		}
++		break;
++	case NL80211_TDLS_DISABLE_LINK:
++		RTW_INFO(FUNC_NDEV_FMT", NL80211_TDLS_DISABLE_LINK;mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(peer));
++		ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer);
++		if (ptdls_sta != NULL) {
++			rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
++			rtw_tdls_cmd(padapter, (u8 *)peer, TDLS_TEARDOWN_STA_LOCALLY_POST);
++		}
++		break;
++	}
++	return 0;
++}
++#endif /* CONFIG_TDLS */
++
++#if defined(CONFIG_RTW_MESH) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
++
++#if DBG_RTW_CFG80211_MESH_CONF
++#define LEGACY_RATES_STR_LEN (RTW_G_RATES_NUM * 5 + 1)
++int get_legacy_rates_str(struct wiphy *wiphy, enum nl80211_band band, u32 mask, char *buf)
++{
++	int i;
++	int cnt = 0;
++
++	for (i = 0; i < wiphy->bands[band]->n_bitrates; i++) {
++		if (mask & BIT(i)) {
++			cnt += snprintf(buf + cnt, LEGACY_RATES_STR_LEN - cnt -1, "%d.%d "
++				, wiphy->bands[band]->bitrates[i].bitrate / 10
++				, wiphy->bands[band]->bitrates[i].bitrate % 10);
++			if (cnt >= LEGACY_RATES_STR_LEN - 1)
++				break;
++		}
++	}
++
++	return cnt;
++}
++
++void dump_mesh_setup(void *sel, struct wiphy *wiphy, const struct mesh_setup *setup)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	struct cfg80211_chan_def *chdef = (struct cfg80211_chan_def *)(&setup->chandef);
++#endif
++	struct ieee80211_channel *chan;
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	chan = (struct ieee80211_channel *)chdef->chan;
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	chan = (struct ieee80211_channel *)setup->channel;
++#endif
++
++	RTW_PRINT_SEL(sel, "mesh_id:\"%s\", len:%u\n", setup->mesh_id, setup->mesh_id_len);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++	RTW_PRINT_SEL(sel, "sync_method:%u\n", setup->sync_method);
++#endif
++	RTW_PRINT_SEL(sel, "path_sel_proto:%u, path_metric:%u\n", setup->path_sel_proto, setup->path_metric);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++	RTW_PRINT_SEL(sel, "auth_id:%u\n", setup->auth_id);
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	if (setup->ie && setup->ie_len) {
++		RTW_PRINT_SEL(sel, "ie:%p, len:%u\n", setup->ie, setup->ie_len);
++		dump_ies(RTW_DBGDUMP, setup->ie, setup->ie_len);
++	}
++#else
++	if (setup->vendor_ie && setup->vendor_ie_len) {
++		RTW_PRINT_SEL(sel, "ie:%p, len:%u\n", setup->vendor_ie, setup->vendor_ie_len);
++		dump_ies(RTW_DBGDUMP, setup->vendor_ie, setup->vendor_ie_len);
++	}
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	RTW_PRINT_SEL(sel, "is_authenticated:%d, is_secure:%d\n", setup->is_authenticated, setup->is_secure);
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
++	RTW_PRINT_SEL(sel, "user_mpm:%d\n", setup->user_mpm);
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++	RTW_PRINT_SEL(sel, "dtim_period:%u, beacon_interval:%u\n", setup->dtim_period, setup->beacon_interval);
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	RTW_PRINT_SEL(sel, "center_freq:%u, ch:%u, width:%s, cfreq1:%u, cfreq2:%u\n"
++		, chan->center_freq, chan->hw_value, nl80211_chan_width_str(chdef->width), chdef->center_freq1, chdef->center_freq2);
++#else
++	RTW_PRINT_SEL(sel, "center_freq:%u, ch:%u, channel_type:%s\n"
++		, chan->center_freq, chan->hw_value, nl80211_channel_type_str(setup->channel_type));
++#endif
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
++	if (setup->mcast_rate[chan->band]) {
++		RTW_PRINT_SEL(sel, "mcast_rate:%d.%d\n"
++			, wiphy->bands[chan->band]->bitrates[setup->mcast_rate[chan->band] - 1].bitrate / 10
++			, wiphy->bands[chan->band]->bitrates[setup->mcast_rate[chan->band] - 1].bitrate % 10
++		);
++	}
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++	if (setup->basic_rates) {
++		char buf[LEGACY_RATES_STR_LEN] = {0};
++
++		get_legacy_rates_str(wiphy, chan->band, setup->basic_rates, buf);
++		RTW_PRINT_SEL(sel, "basic_rates:%s\n", buf);
++	}
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0))
++	if (setup->beacon_rate.control[chan->band].legacy) {
++		char buf[LEGACY_RATES_STR_LEN] = {0};
++
++		get_legacy_rates_str(wiphy, chan->band, setup->beacon_rate.control[chan->band].legacy, buf);
++		RTW_PRINT_SEL(sel, "beacon_rate.legacy:%s\n", buf);
++	}
++	if (*((u32 *)&(setup->beacon_rate.control[chan->band].ht_mcs[0]))
++		|| *((u32 *)&(setup->beacon_rate.control[chan->band].ht_mcs[4]))
++		|| *((u16 *)&(setup->beacon_rate.control[chan->band].ht_mcs[8]))
++	) {
++		RTW_PRINT_SEL(sel, "beacon_rate.ht_mcs:"HT_RX_MCS_BMP_FMT"\n"
++			, HT_RX_MCS_BMP_ARG(setup->beacon_rate.control[chan->band].ht_mcs));
++	}
++
++	if (setup->beacon_rate.control[chan->band].vht_mcs[0]
++		|| setup->beacon_rate.control[chan->band].vht_mcs[1]
++		|| setup->beacon_rate.control[chan->band].vht_mcs[2]
++		|| setup->beacon_rate.control[chan->band].vht_mcs[3]
++	) {
++		int i;
++
++		for (i = 0; i < 4; i++) {/* parsing up to 4SS */
++			u16 mcs_mask = setup->beacon_rate.control[chan->band].vht_mcs[i];
++
++			RTW_PRINT_SEL(sel, "beacon_rate.vht_mcs[%d]:%s\n", i
++				, mcs_mask == 0x00FF ? "0~7" : mcs_mask == 0x01FF ? "0~8" : mcs_mask == 0x03FF ? "0~9" : "invalid");
++		}
++	}
++
++	if (setup->beacon_rate.control[chan->band].gi) {
++		RTW_PRINT_SEL(sel, "beacon_rate.gi:%s\n"
++			, setup->beacon_rate.control[chan->band].gi == NL80211_TXRATE_FORCE_SGI ? "SGI" :
++				setup->beacon_rate.control[chan->band].gi == NL80211_TXRATE_FORCE_LGI ? "LGI" : "invalid"
++		);
++	}
++#endif
++}
++
++void dump_mesh_config(void *sel, const struct mesh_config *conf)
++{
++	RTW_PRINT_SEL(sel, "dot11MeshRetryTimeout:%u\n", conf->dot11MeshRetryTimeout);
++	RTW_PRINT_SEL(sel, "dot11MeshConfirmTimeout:%u\n", conf->dot11MeshConfirmTimeout);
++	RTW_PRINT_SEL(sel, "dot11MeshHoldingTimeout:%u\n", conf->dot11MeshHoldingTimeout);
++	RTW_PRINT_SEL(sel, "dot11MeshMaxPeerLinks:%u\n", conf->dot11MeshMaxPeerLinks);
++	RTW_PRINT_SEL(sel, "dot11MeshMaxRetries:%u\n", conf->dot11MeshMaxRetries);
++	RTW_PRINT_SEL(sel, "dot11MeshTTL:%u\n", conf->dot11MeshTTL);
++	RTW_PRINT_SEL(sel, "element_ttl:%u\n", conf->element_ttl);
++	RTW_PRINT_SEL(sel, "auto_open_plinks:%d\n", conf->auto_open_plinks);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++	RTW_PRINT_SEL(sel, "dot11MeshNbrOffsetMaxNeighbor:%u\n", conf->dot11MeshNbrOffsetMaxNeighbor);
++#endif
++
++	RTW_PRINT_SEL(sel, "dot11MeshHWMPmaxPREQretries:%u\n", conf->dot11MeshHWMPmaxPREQretries);
++	RTW_PRINT_SEL(sel, "path_refresh_time:%u\n", conf->path_refresh_time);
++	RTW_PRINT_SEL(sel, "min_discovery_timeout:%u\n", conf->min_discovery_timeout);
++	RTW_PRINT_SEL(sel, "dot11MeshHWMPactivePathTimeout:%u\n", conf->dot11MeshHWMPactivePathTimeout);
++	RTW_PRINT_SEL(sel, "dot11MeshHWMPpreqMinInterval:%u\n", conf->dot11MeshHWMPpreqMinInterval);	
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
++	RTW_PRINT_SEL(sel, "dot11MeshHWMPperrMinInterval:%u\n", conf->dot11MeshHWMPperrMinInterval);
++#endif
++	RTW_PRINT_SEL(sel, "dot11MeshHWMPnetDiameterTraversalTime:%u\n", conf->dot11MeshHWMPnetDiameterTraversalTime);
++	RTW_PRINT_SEL(sel, "dot11MeshHWMPRootMode:%u\n", conf->dot11MeshHWMPRootMode);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	RTW_PRINT_SEL(sel, "dot11MeshHWMPRannInterval:%u\n", conf->dot11MeshHWMPRannInterval);
++	RTW_PRINT_SEL(sel, "dot11MeshGateAnnouncementProtocol:%d\n", conf->dot11MeshGateAnnouncementProtocol);
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
++	RTW_PRINT_SEL(sel, "dot11MeshForwarding:%d\n", conf->dot11MeshForwarding);
++	RTW_PRINT_SEL(sel, "rssi_threshold:%d\n", conf->rssi_threshold);
++#endif
++	
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++	RTW_PRINT_SEL(sel, "ht_opmode:0x%04x\n", conf->ht_opmode);
++#endif
++	
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	RTW_PRINT_SEL(sel, "dot11MeshHWMPactivePathToRootTimeout:%u\n", conf->dot11MeshHWMPactivePathToRootTimeout);
++	RTW_PRINT_SEL(sel, "dot11MeshHWMProotInterval:%u\n", conf->dot11MeshHWMProotInterval);
++	RTW_PRINT_SEL(sel, "dot11MeshHWMPconfirmationInterval:%u\n", conf->dot11MeshHWMPconfirmationInterval);
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++	RTW_PRINT_SEL(sel, "power_mode:%s\n", nl80211_mesh_power_mode_str(conf->power_mode));
++	RTW_PRINT_SEL(sel, "dot11MeshAwakeWindowDuration:%u\n", conf->dot11MeshAwakeWindowDuration);
++#endif
++	
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++	RTW_PRINT_SEL(sel, "plink_timeout:%u\n", conf->plink_timeout);
++#endif
++}
++#endif /* DBG_RTW_CFG80211_MESH_CONF */
++
++static void rtw_cfg80211_mesh_info_set_profile(struct rtw_mesh_info *minfo, const struct mesh_setup *setup)
++{
++	_rtw_memcpy(minfo->mesh_id, setup->mesh_id, setup->mesh_id_len);
++	minfo->mesh_id_len = setup->mesh_id_len;
++	minfo->mesh_pp_id = setup->path_sel_proto;
++	minfo->mesh_pm_id = setup->path_metric;
++	minfo->mesh_cc_id = 0;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++	minfo->mesh_sp_id = setup->sync_method;
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++	minfo->mesh_auth_id = setup->auth_id;
++#else
++	if (setup->is_authenticated) {
++		u8 *rsn_ie;
++		sint rsn_ie_len;
++		struct rsne_info info;
++		u8 *akm;
++		u8 AKM_SUITE_SAE[4] = {0x00, 0x0F, 0xAC, 0x08};
++
++		rsn_ie = rtw_get_ie(setup->ie, WLAN_EID_RSN, &rsn_ie_len, setup->ie_len);
++		if (!rsn_ie || !rsn_ie_len) {
++			rtw_warn_on(1);
++			return;
++		}
++
++		if (rtw_rsne_info_parse(rsn_ie, rsn_ie_len + 2, &info) != _SUCCESS) {
++			rtw_warn_on(1);
++			return;
++		}
++
++		if (!info.akm_list || !info.akm_cnt) {
++			rtw_warn_on(1);
++			return;
++		}
++
++		akm = info.akm_list;
++		while (akm < info.akm_list + info.akm_cnt * 4) {
++			if (_rtw_memcmp(akm, AKM_SUITE_SAE, 4) == _TRUE) {
++				minfo->mesh_auth_id = 0x01;
++				break;
++			}
++		}
++
++		if (!minfo->mesh_auth_id) {
++			rtw_warn_on(1);
++			return;
++		}
++	}
++#endif
++}
++
++static inline bool chk_mesh_attr(enum nl80211_meshconf_params parm, u32 mask)
++{
++	return (mask >> (parm - 1)) & 0x1;
++}
++
++static void rtw_cfg80211_mesh_cfg_set(_adapter *adapter, const struct mesh_config *conf, u32 mask)
++{
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++
++#if 0 /* driver MPM */
++	if (chk_mesh_attr(NL80211_MESHCONF_RETRY_TIMEOUT, mask));
++	if (chk_mesh_attr(NL80211_MESHCONF_CONFIRM_TIMEOUT, mask));
++	if (chk_mesh_attr(NL80211_MESHCONF_HOLDING_TIMEOUT, mask));
++	if (chk_mesh_attr(NL80211_MESHCONF_MAX_PEER_LINKS, mask));
++	if (chk_mesh_attr(NL80211_MESHCONF_MAX_RETRIES, mask));
++#endif
++
++	if (chk_mesh_attr(NL80211_MESHCONF_TTL, mask))
++		mcfg->dot11MeshTTL = conf->dot11MeshTTL;
++	if (chk_mesh_attr(NL80211_MESHCONF_ELEMENT_TTL, mask))
++		mcfg->element_ttl = conf->element_ttl;
++
++#if 0 /* driver MPM */
++	if (chk_mesh_attr(NL80211_MESHCONF_AUTO_OPEN_PLINKS, mask));
++#endif
++
++#if 0 /* TBD: synchronization */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++	if (chk_mesh_attr(NL80211_MESHCONF_SYNC_OFFSET_MAX_NEIGHBOR, mask));
++#endif
++#endif
++
++	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_MAX_PREQ_RETRIES, mask))
++		mcfg->dot11MeshHWMPmaxPREQretries = conf->dot11MeshHWMPmaxPREQretries;
++	if (chk_mesh_attr(NL80211_MESHCONF_PATH_REFRESH_TIME, mask))
++		mcfg->path_refresh_time = conf->path_refresh_time;
++	if (chk_mesh_attr(NL80211_MESHCONF_MIN_DISCOVERY_TIMEOUT, mask))
++		mcfg->min_discovery_timeout = conf->min_discovery_timeout;
++	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT, mask))
++		mcfg->dot11MeshHWMPactivePathTimeout = conf->dot11MeshHWMPactivePathTimeout;
++	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PREQ_MIN_INTERVAL, mask))
++		mcfg->dot11MeshHWMPpreqMinInterval = conf->dot11MeshHWMPpreqMinInterval;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
++	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PERR_MIN_INTERVAL, mask))
++		mcfg->dot11MeshHWMPperrMinInterval = conf->dot11MeshHWMPperrMinInterval;
++#endif
++	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_NET_DIAM_TRVS_TIME, mask))
++		mcfg->dot11MeshHWMPnetDiameterTraversalTime = conf->dot11MeshHWMPnetDiameterTraversalTime;
++
++	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ROOTMODE, mask))
++		mcfg->dot11MeshHWMPRootMode = conf->dot11MeshHWMPRootMode;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	if (chk_mesh_attr(NL80211_MESHCONF_GATE_ANNOUNCEMENTS, mask))
++		mcfg->dot11MeshGateAnnouncementProtocol = conf->dot11MeshGateAnnouncementProtocol;
++	/* our current gate annc implementation rides on root annc with gate annc bit in PREQ flags */
++	if (mcfg->dot11MeshGateAnnouncementProtocol
++		&& mcfg->dot11MeshHWMPRootMode <= RTW_IEEE80211_ROOTMODE_ROOT
++	) {
++		mcfg->dot11MeshHWMPRootMode = RTW_IEEE80211_PROACTIVE_RANN;
++		RTW_INFO(ADPT_FMT" enable PROACTIVE_RANN becaue gate annc is needed\n", ADPT_ARG(adapter));
++	}
++	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_RANN_INTERVAL, mask))
++		mcfg->dot11MeshHWMPRannInterval = conf->dot11MeshHWMPRannInterval;
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
++	if (chk_mesh_attr(NL80211_MESHCONF_FORWARDING, mask))
++		mcfg->dot11MeshForwarding = conf->dot11MeshForwarding;
++
++	if (chk_mesh_attr(NL80211_MESHCONF_RSSI_THRESHOLD, mask))
++		mcfg->rssi_threshold = conf->rssi_threshold;
++#endif
++
++#if 0 /* controlled by driver */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++	if (chk_mesh_attr(NL80211_MESHCONF_HT_OPMODE, mask));
++#endif
++#endif
++	
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PATH_TO_ROOT_TIMEOUT, mask))
++		mcfg->dot11MeshHWMPactivePathToRootTimeout = conf->dot11MeshHWMPactivePathToRootTimeout;
++	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ROOT_INTERVAL, mask))
++		mcfg->dot11MeshHWMProotInterval = conf->dot11MeshHWMProotInterval;
++	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_CONFIRMATION_INTERVAL, mask))
++		mcfg->dot11MeshHWMPconfirmationInterval = conf->dot11MeshHWMPconfirmationInterval;	
++#endif
++
++#if 0 /* TBD */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++	if (chk_mesh_attr(NL80211_MESHCONF_POWER_MODE, mask));
++	if (chk_mesh_attr(NL80211_MESHCONF_AWAKE_WINDOW, mask));
++#endif
++#endif
++
++#if 0 /* driver MPM */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++	if (chk_mesh_attr(NL80211_MESHCONF_PLINK_TIMEOUT, mask));
++#endif
++#endif
++}
++
++u8 *rtw_cfg80211_construct_mesh_beacon_ies(struct wiphy *wiphy, _adapter *adapter
++	, const struct mesh_config *conf, const struct mesh_setup *setup
++	, uint *ies_len)
++{
++	struct rtw_mesh_info *minfo = &adapter->mesh_info;
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	struct cfg80211_chan_def *chdef = (struct cfg80211_chan_def *)(&setup->chandef);
++#endif
++	struct ieee80211_channel *chan;
++	u8 ch, bw, offset;
++#endif
++	uint len;
++	u8 n_bitrates;
++	u8 ht = 0;
++	u8 vht = 0;
++	u8 *rsn_ie = NULL;
++	sint rsn_ie_len = 0;
++	u8 *ies = NULL, *c;
++	u8 supported_rates[RTW_G_RATES_NUM] = {0};
++	int i;
++
++	*ies_len = 0;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	chan = (struct ieee80211_channel *)chdef->chan;
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	chan = (struct ieee80211_channel *)setup->channel;
++#endif
++
++	n_bitrates = wiphy->bands[chan->band]->n_bitrates;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	rtw_get_chbw_from_cfg80211_chan_def(chdef, &ht, &ch, &bw, &offset);
++#else
++	rtw_get_chbw_from_nl80211_channel_type(chan, setup->channel_type, &ht, &ch, &bw, &offset);
++#endif
++	if (!ch)
++		goto exit;
++	
++#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	vht = ht && ch > 14 && bw >= CHANNEL_WIDTH_80; /* VHT40/VHT20? */
++#endif
++
++	RTW_INFO(FUNC_ADPT_FMT" => ch:%u,%u,%u, ht:%u, vht:%u\n"
++		, FUNC_ADPT_ARG(adapter), ch, bw, offset, ht, vht);
++#endif
++
++	rsn_ie = rtw_get_ie(setup->ie, WLAN_EID_RSN, &rsn_ie_len, setup->ie_len);
++	if (rsn_ie && !rsn_ie_len) {
++		rtw_warn_on(1);
++		rsn_ie = NULL;
++	}
++
++	len = _BEACON_IE_OFFSET_
++		+ 2 /* 0-length SSID */
++		+ (n_bitrates >= 8 ? 8 : n_bitrates) + 2 /* Supported Rates */
++		+ 3 /* DS parameter set */
++		+ 6 /* TIM  */
++		+ (n_bitrates > 8 ? n_bitrates - 8 + 2 : 0) /* Extended Supported Rates */
++		+ (rsn_ie ? rsn_ie_len + 2 : 0) /* RSN */
++		#if defined(CONFIG_80211N_HT)
++		+ (ht ? HT_CAP_IE_LEN + 2 + HT_OP_IE_LEN + 2 : 0) /* HT */
++		#endif
++		#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++		+ (vht ? VHT_CAP_IE_LEN + 2 + VHT_OP_IE_LEN + 2 : 0) /* VHT */
++		#endif
++		+ minfo->mesh_id_len + 2 /* Mesh ID */
++		+ 9 /* Mesh configuration */
++		;
++
++	ies = rtw_zmalloc(len);
++	if (!ies)
++		goto exit;
++
++	/* timestamp */
++	c = ies + 8;
++
++	/* beacon interval */
++	RTW_PUT_LE16(c , setup->beacon_interval);
++	c += 2;
++
++	/* capability */
++	if (rsn_ie)
++		*((u16 *)c) |= cpu_to_le16(cap_Privacy);
++	c += 2;
++
++	/* SSID */
++	c = rtw_set_ie(c, WLAN_EID_SSID, 0, NULL, NULL);
++
++	/* Supported Rates */
++	for (i = 0; i < n_bitrates; i++) {
++		supported_rates[i] = wiphy->bands[chan->band]->bitrates[i].bitrate / 5;
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++		if (setup->basic_rates & BIT(i))
++		#else
++		if (rtw_is_basic_rate_mix(supported_rates[i]))
++		#endif
++			supported_rates[i] |= IEEE80211_BASIC_RATE_MASK;
++	}
++	c = rtw_set_ie(c, WLAN_EID_SUPP_RATES, (n_bitrates >= 8 ? 8 : n_bitrates), supported_rates, NULL);
++
++	/* DS parameter set */
++	c = rtw_set_ie(c, WLAN_EID_DS_PARAMS, 1, &ch, NULL);
++
++	/* TIM */
++	*c = WLAN_EID_TIM;
++	*(c + 1) = 4;
++	c += 6;
++	//c = rtw_set_ie(c, _TIM_IE_, 4, NULL, NULL);
++
++	/* Extended Supported Rates */
++	if (n_bitrates > 8)
++		c = rtw_set_ie(c, WLAN_EID_EXT_SUPP_RATES, n_bitrates - 8, supported_rates + 8, NULL);
++
++	/* RSN */
++	if (rsn_ie)
++		c = rtw_set_ie(c, WLAN_EID_RSN, rsn_ie_len, rsn_ie + 2, NULL);
++
++#if defined(CONFIG_80211N_HT)
++	if (ht) {
++		struct ieee80211_sta_ht_cap *sta_ht_cap = &wiphy->bands[chan->band]->ht_cap;
++		u8 ht_cap[HT_CAP_IE_LEN];
++		u8 ht_op[HT_OP_IE_LEN];
++
++		_rtw_memset(ht_cap, 0, HT_CAP_IE_LEN);
++		_rtw_memset(ht_op, 0, HT_OP_IE_LEN);
++
++		/* WLAN_EID_HT_CAP */
++		RTW_PUT_LE16(HT_CAP_ELE_CAP_INFO(ht_cap), sta_ht_cap->cap);
++		SET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(ht_cap, sta_ht_cap->ampdu_factor);
++		SET_HT_CAP_ELE_MIN_MPDU_S_SPACE(ht_cap, sta_ht_cap->ampdu_density);
++		_rtw_memcpy(HT_CAP_ELE_SUP_MCS_SET(ht_cap), &sta_ht_cap->mcs, 16);
++		c = rtw_set_ie(c, WLAN_EID_HT_CAP, HT_CAP_IE_LEN, ht_cap, NULL);
++
++		/* WLAN_EID_HT_OPERATION */
++		SET_HT_OP_ELE_PRI_CHL(ht_op, ch);
++		switch (offset) {
++		case HAL_PRIME_CHNL_OFFSET_LOWER:
++			SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCA);
++			break;
++		case HAL_PRIME_CHNL_OFFSET_UPPER:
++			SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCB);
++			break;
++		case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
++		default:
++			SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCN);
++			break;
++		}
++		if (bw >= CHANNEL_WIDTH_40)
++			SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op, 1);
++		else
++			SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op, 0);
++		c = rtw_set_ie(c, WLAN_EID_HT_OPERATION, HT_OP_IE_LEN, ht_op, NULL);
++	}
++#endif /* defined(CONFIG_80211N_HT) */
++
++#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	if (vht) {
++		struct ieee80211_sta_vht_cap *sta_vht_cap = &wiphy->bands[chan->band]->vht_cap;
++		u8 vht_cap[VHT_CAP_IE_LEN];
++		u8 vht_op[VHT_OP_IE_LEN];
++		u8 cch = rtw_get_center_ch(ch, bw, offset);
++
++		_rtw_memset(vht_op, 0, VHT_OP_IE_LEN);
++
++		/* WLAN_EID_VHT_CAPABILITY */
++		_rtw_memcpy(vht_cap, &sta_vht_cap->cap, 4);
++		_rtw_memcpy(vht_cap + 4, &sta_vht_cap->vht_mcs, 8);
++		c = rtw_set_ie(c, WLAN_EID_VHT_CAPABILITY, VHT_CAP_IE_LEN, vht_cap, NULL);
++
++		/* WLAN_EID_VHT_OPERATION */
++		if (bw < CHANNEL_WIDTH_80) {
++			SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op, 0);
++			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op, 0);
++			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op, 0);
++		} else if (bw == CHANNEL_WIDTH_80) {
++			SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op, 1);
++			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op, cch);
++			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op, 0);
++		} else {
++			RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(adapter), bw);
++			rtw_warn_on(1);
++			rtw_mfree(ies, len);
++			goto exit;
++		}
++
++		/* Hard code 1 stream, MCS0-7 is a min Basic VHT MCS rates */
++		vht_op[3] = 0xfc;
++		vht_op[4] = 0xff;
++		c = rtw_set_ie(c, WLAN_EID_VHT_OPERATION, VHT_OP_IE_LEN, vht_op, NULL);
++	}
++#endif /* defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) */
++
++	/* Mesh ID */
++	c = rtw_set_ie_mesh_id(c, NULL, minfo->mesh_id, minfo->mesh_id_len);
++
++	/* Mesh configuration */
++	c = rtw_set_ie_mesh_config(c, NULL
++		, minfo->mesh_pp_id
++		, minfo->mesh_pm_id
++		, minfo->mesh_cc_id
++		, minfo->mesh_sp_id
++		, minfo->mesh_auth_id
++		, 0, 0, 0
++		, 1
++		, 0, 0
++		, mcfg->dot11MeshForwarding
++		, 0, 0, 0
++	);
++
++#if DBG_RTW_CFG80211_MESH_CONF
++	RTW_INFO(FUNC_ADPT_FMT" ies_len:%u\n", FUNC_ADPT_ARG(adapter), len);
++	dump_ies(RTW_DBGDUMP, ies + _BEACON_IE_OFFSET_, len - _BEACON_IE_OFFSET_);
++#endif
++
++exit:
++	if (ies)
++		*ies_len = len;
++	return ies;
++}
++
++static int cfg80211_rtw_get_mesh_config(struct wiphy *wiphy, struct net_device *dev
++	, struct mesh_config *conf)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rtw_mesh_cfg *mesh_cfg = &adapter->mesh_cfg;
++	int ret = 0;
++
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
++
++	/* driver MPM */
++	conf->dot11MeshRetryTimeout = 0;
++	conf->dot11MeshConfirmTimeout = 0;
++	conf->dot11MeshHoldingTimeout = 0;
++	conf->dot11MeshMaxPeerLinks = mesh_cfg->max_peer_links;
++	conf->dot11MeshMaxRetries = 0;
++
++	conf->dot11MeshTTL = mesh_cfg->dot11MeshTTL;
++	conf->element_ttl = mesh_cfg->element_ttl;
++
++	/* driver MPM */
++	conf->auto_open_plinks = 0;
++
++	/* TBD: synchronization */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++	conf->dot11MeshNbrOffsetMaxNeighbor = 0;
++#endif
++
++	conf->dot11MeshHWMPmaxPREQretries = mesh_cfg->dot11MeshHWMPmaxPREQretries;
++	conf->path_refresh_time = mesh_cfg->path_refresh_time;
++	conf->min_discovery_timeout = mesh_cfg->min_discovery_timeout;
++	conf->dot11MeshHWMPactivePathTimeout = mesh_cfg->dot11MeshHWMPactivePathTimeout;
++	conf->dot11MeshHWMPpreqMinInterval = mesh_cfg->dot11MeshHWMPpreqMinInterval;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
++	conf->dot11MeshHWMPperrMinInterval = mesh_cfg->dot11MeshHWMPperrMinInterval;
++#endif
++	conf->dot11MeshHWMPnetDiameterTraversalTime = mesh_cfg->dot11MeshHWMPnetDiameterTraversalTime;
++	conf->dot11MeshHWMPRootMode = mesh_cfg->dot11MeshHWMPRootMode;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	conf->dot11MeshHWMPRannInterval = mesh_cfg->dot11MeshHWMPRannInterval;
++#endif
++	conf->dot11MeshGateAnnouncementProtocol = mesh_cfg->dot11MeshGateAnnouncementProtocol;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
++	conf->dot11MeshForwarding = mesh_cfg->dot11MeshForwarding;
++	conf->rssi_threshold = mesh_cfg->rssi_threshold;
++#endif
++
++	/* TBD */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++	conf->ht_opmode = 0xffff;
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	conf->dot11MeshHWMPactivePathToRootTimeout = mesh_cfg->dot11MeshHWMPactivePathToRootTimeout;
++	conf->dot11MeshHWMProotInterval = mesh_cfg->dot11MeshHWMProotInterval;
++	conf->dot11MeshHWMPconfirmationInterval = mesh_cfg->dot11MeshHWMPconfirmationInterval;
++#endif
++
++	/* TBD: power save */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++	conf->power_mode = NL80211_MESH_POWER_ACTIVE;
++	conf->dot11MeshAwakeWindowDuration = 0;
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++	conf->plink_timeout = mesh_cfg->plink_timeout;
++#endif
++
++	return ret;
++}
++
++static void rtw_mbss_info_change_notify(_adapter *adapter, bool minfo_changed, bool need_work)
++{
++	if (need_work)
++		rtw_mesh_work(&adapter->mesh_work);
++}
++
++static int cfg80211_rtw_update_mesh_config(struct wiphy *wiphy, struct net_device *dev
++	, u32 mask, const struct mesh_config *nconf)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	int ret = 0;
++	bool minfo_changed = _FALSE, need_work = _FALSE;
++
++	RTW_INFO(FUNC_ADPT_FMT" mask:0x%08x\n", FUNC_ADPT_ARG(adapter), mask);
++
++	rtw_cfg80211_mesh_cfg_set(adapter, nconf, mask);
++	update_beacon(adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE, 0);
++#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER
++	if (rtw_mesh_cto_mgate_required(adapter))
++		rtw_netif_carrier_off(adapter->pnetdev);
++	else
++		rtw_netif_carrier_on(adapter->pnetdev);
++#endif
++	need_work = rtw_ieee80211_mesh_root_setup(adapter);
++
++	rtw_mbss_info_change_notify(adapter, minfo_changed, need_work);
++
++	return ret;
++}
++
++static int cfg80211_rtw_join_mesh(struct wiphy *wiphy, struct net_device *dev,
++	const struct mesh_config *conf, const struct mesh_setup *setup)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	u8 *ies = NULL;
++	uint ies_len;
++	int ret = 0;
++
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
++
++#if DBG_RTW_CFG80211_MESH_CONF
++	RTW_INFO(FUNC_ADPT_FMT" mesh_setup:\n", FUNC_ADPT_ARG(adapter));
++	dump_mesh_setup(RTW_DBGDUMP, wiphy, setup);
++	RTW_INFO(FUNC_ADPT_FMT" mesh_config:\n", FUNC_ADPT_ARG(adapter));
++	dump_mesh_config(RTW_DBGDUMP, conf);
++#endif
++
++	if (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) {
++		ret = -ENOTSUPP;
++		goto exit;
++	}
++
++	/* initialization */
++	rtw_mesh_init_mesh_info(adapter);
++
++	/* apply cfg80211 settings*/
++	rtw_cfg80211_mesh_info_set_profile(&adapter->mesh_info, setup);
++	rtw_cfg80211_mesh_cfg_set(adapter, conf, 0xFFFFFFFF);
++
++	/* apply cfg80211 settings (join only) */
++	rtw_mesh_cfg_init_max_peer_links(adapter, conf->dot11MeshMaxPeerLinks);
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++	rtw_mesh_cfg_init_plink_timeout(adapter, conf->plink_timeout);
++	#endif
++
++	rtw_ieee80211_mesh_root_setup(adapter);
++
++	ies = rtw_cfg80211_construct_mesh_beacon_ies(wiphy, adapter, conf, setup, &ies_len);
++	if (!ies) {
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	/* start mbss */
++	if (rtw_check_beacon_data(adapter, ies,  ies_len) != _SUCCESS) {
++		ret = -EINVAL;
++		goto exit;
++	}
++	
++	rtw_mesh_work(&adapter->mesh_work);
++
++exit:
++	if (ies)
++		rtw_mfree(ies, ies_len);
++	if (ret)
++		rtw_mesh_deinit_mesh_info(adapter);
++
++	return ret;
++}
++
++static int cfg80211_rtw_leave_mesh(struct wiphy *wiphy, struct net_device *dev)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	int ret = 0;
++
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
++
++	rtw_mesh_deinit_mesh_info(adapter);
++
++	rtw_stop_ap_cmd(adapter, RTW_CMDF_WAIT_ACK);
++
++	return ret;
++}
++
++static int cfg80211_rtw_add_mpath(struct wiphy *wiphy, struct net_device *dev
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++	, const u8 *dst, const u8 *next_hop
++	#else
++	, u8 *dst, u8 *next_hop
++	#endif
++)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct sta_info *sta;
++	struct rtw_mesh_path *mpath;
++	int ret = 0;
++
++	rtw_rcu_read_lock();
++
++	sta = rtw_get_stainfo(stapriv, next_hop);
++	if (!sta) {
++		ret = -ENOENT;
++		goto exit;
++	}
++
++	mpath = rtw_mesh_path_add(adapter, dst);
++	if (!mpath) {
++		ret = -ENOENT;
++		goto exit;
++	}
++
++	rtw_mesh_path_fix_nexthop(mpath, sta);
++
++exit:
++	rtw_rcu_read_unlock();
++
++	return ret;
++}
++
++static int cfg80211_rtw_del_mpath(struct wiphy *wiphy, struct net_device *dev
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++	, const u8 *dst
++	#else
++	, u8 *dst
++	#endif
++)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	int ret = 0;
++
++	if (dst) {
++		if (rtw_mesh_path_del(adapter, dst)) {
++			ret = -ENOENT;
++			goto exit;
++		}
++	} else {
++		rtw_mesh_path_flush_by_iface(adapter);
++	}	
++
++exit:
++	return ret;
++}
++
++static int cfg80211_rtw_change_mpath(struct wiphy *wiphy, struct net_device *dev
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
++	, const u8 *dst, const u8 *next_hop
++	#else
++	, u8 *dst, u8 *next_hop
++	#endif
++)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct sta_priv *stapriv = &adapter->stapriv;
++	struct sta_info *sta;
++	struct rtw_mesh_path *mpath;
++	int ret = 0;
++
++	rtw_rcu_read_lock();
++
++	sta = rtw_get_stainfo(stapriv, next_hop);
++	if (!sta) {
++		ret = -ENOENT;
++		goto exit;
++	}
++
++	mpath = rtw_mesh_path_lookup(adapter, dst);
++	if (!mpath) {
++		ret = -ENOENT;
++		goto exit;
++	}
++
++	rtw_mesh_path_fix_nexthop(mpath, sta);
++
++exit:
++	rtw_rcu_read_unlock();
++
++	return ret;
++}
++
++static void rtw_cfg80211_mpath_set_pinfo(struct rtw_mesh_path *mpath, u8 *next_hop, struct mpath_info *pinfo)
++{
++	struct sta_info *next_hop_sta = rtw_rcu_dereference(mpath->next_hop);
++
++	if (next_hop_sta)
++		_rtw_memcpy(next_hop, next_hop_sta->cmn.mac_addr, ETH_ALEN);
++	else
++		_rtw_memset(next_hop, 0, ETH_ALEN);
++
++	_rtw_memset(pinfo, 0, sizeof(*pinfo));
++
++	pinfo->generation = mpath->adapter->mesh_info.mesh_paths_generation;
++
++	pinfo->filled = 0
++		| MPATH_INFO_FRAME_QLEN
++		| MPATH_INFO_SN
++		| MPATH_INFO_METRIC
++		| MPATH_INFO_EXPTIME
++		| MPATH_INFO_DISCOVERY_TIMEOUT
++		| MPATH_INFO_DISCOVERY_RETRIES
++		| MPATH_INFO_FLAGS
++		;
++
++	pinfo->frame_qlen = mpath->frame_queue_len;
++	pinfo->sn = mpath->sn;
++	pinfo->metric = mpath->metric;
++	if (rtw_time_after(mpath->exp_time, rtw_get_current_time()))
++		pinfo->exptime = rtw_get_remaining_time_ms(mpath->exp_time);
++	pinfo->discovery_timeout = rtw_systime_to_ms(mpath->discovery_timeout);
++	pinfo->discovery_retries = mpath->discovery_retries;
++	if (mpath->flags & RTW_MESH_PATH_ACTIVE)
++		pinfo->flags |= NL80211_MPATH_FLAG_ACTIVE;
++	if (mpath->flags & RTW_MESH_PATH_RESOLVING)
++		pinfo->flags |= NL80211_MPATH_FLAG_RESOLVING;
++	if (mpath->flags & RTW_MESH_PATH_SN_VALID)
++		pinfo->flags |= NL80211_MPATH_FLAG_SN_VALID;
++	if (mpath->flags & RTW_MESH_PATH_FIXED)
++		pinfo->flags |= NL80211_MPATH_FLAG_FIXED;
++	if (mpath->flags & RTW_MESH_PATH_RESOLVED)
++		pinfo->flags |= NL80211_MPATH_FLAG_RESOLVED;
++}
++
++static int cfg80211_rtw_get_mpath(struct wiphy *wiphy, struct net_device *dev, u8 *dst, u8 *next_hop, struct mpath_info *pinfo)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rtw_mesh_path *mpath;
++	int ret = 0;
++
++	rtw_rcu_read_lock();
++
++	mpath = rtw_mesh_path_lookup(adapter, dst);
++	if (!mpath) {
++		ret = -ENOENT;
++		goto exit;
++	}
++
++	rtw_cfg80211_mpath_set_pinfo(mpath, next_hop, pinfo);
++
++exit:
++	rtw_rcu_read_unlock();
++
++	return ret;
++}
++
++static int cfg80211_rtw_dump_mpath(struct wiphy *wiphy, struct net_device *dev, int idx, u8 *dst, u8 *next_hop, struct mpath_info *pinfo)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rtw_mesh_path *mpath;
++	int ret = 0;
++
++	rtw_rcu_read_lock();
++
++	mpath = rtw_mesh_path_lookup_by_idx(adapter, idx);
++	if (!mpath) {
++		ret = -ENOENT;
++		goto exit;
++	}
++
++	_rtw_memcpy(dst, mpath->dst, ETH_ALEN);
++	rtw_cfg80211_mpath_set_pinfo(mpath, next_hop, pinfo);
++
++exit:
++	rtw_rcu_read_unlock();
++
++	return ret;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++static void rtw_cfg80211_mpp_set_pinfo(struct rtw_mesh_path *mpath, u8 *mpp, struct mpath_info *pinfo)
++{
++	_rtw_memcpy(mpp, mpath->mpp, ETH_ALEN);
++
++	_rtw_memset(pinfo, 0, sizeof(*pinfo));
++	pinfo->generation = mpath->adapter->mesh_info.mpp_paths_generation;
++}
++
++static int cfg80211_rtw_get_mpp(struct wiphy *wiphy, struct net_device *dev, u8 *dst, u8 *mpp, struct mpath_info *pinfo)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rtw_mesh_path *mpath;
++	int ret = 0;
++
++	rtw_rcu_read_lock();
++
++	mpath = rtw_mpp_path_lookup(adapter, dst);
++	if (!mpath) {
++		ret = -ENOENT;
++		goto exit;
++	}
++
++	rtw_cfg80211_mpp_set_pinfo(mpath, mpp, pinfo);
++
++exit:
++	rtw_rcu_read_unlock();
++
++	return ret;
++}
++
++static int cfg80211_rtw_dump_mpp(struct wiphy *wiphy, struct net_device *dev, int idx, u8 *dst, u8 *mpp, struct mpath_info *pinfo)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rtw_mesh_path *mpath;
++	int ret = 0;
++
++	rtw_rcu_read_lock();
++
++	mpath = rtw_mpp_path_lookup_by_idx(adapter, idx);
++	if (!mpath) {
++		ret = -ENOENT;
++		goto exit;
++	}
++
++	_rtw_memcpy(dst, mpath->dst, ETH_ALEN);
++	rtw_cfg80211_mpp_set_pinfo(mpath, mpp, pinfo);
++
++exit:
++	rtw_rcu_read_unlock();
++
++	return ret;
++}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) */
++
++#endif /* defined(CONFIG_RTW_MESH) */
++
++#if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++static int cfg80211_rtw_sched_scan_start(struct wiphy *wiphy,
++		struct net_device *dev,
++		struct cfg80211_sched_scan_request *request)
++{
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	struct cfg80211_ssid *ssids;
++	int n_ssids = 0;
++	int interval = 0;
++	int i = 0;
++	u8 ret;
++
++	if (padapter->bup == _FALSE) {
++		RTW_INFO("%s: net device is down.\n", __func__);
++		return -EIO;
++	}
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE ||
++		check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE  ||
++		check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) {
++		RTW_INFO("%s: device is busy.\n", __func__);
++		rtw_scan_abort(padapter);
++	}
++
++	if (request == NULL) {
++		RTW_INFO("%s: invalid cfg80211_requests parameters.\n", __func__);
++		return -EINVAL;
++	}
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)
++	interval = request->scan_plans->interval;
++#else
++	interval = request->interval;
++#endif
++	n_ssids = request->n_match_sets;
++	ssids = (struct cfg80211_ssid *)rtw_zmalloc(n_ssids * sizeof(struct cfg80211_ssid));
++	if(ssids == NULL) {
++		RTW_ERR("Fail to allocate ssids for PNO\n");
++		return -ENOMEM;
++	}
++	for (i=0;i<request->n_match_sets;i++) {
++			ssids[i].ssid_len = request->match_sets[i].ssid.ssid_len;
++			memcpy(ssids[i].ssid, request->match_sets[i].ssid.ssid,
++					request->match_sets[i].ssid.ssid_len);
++	}
++#else
++	interval = request->interval;
++	n_ssids = request->n_ssids;
++	ssids = request->ssids;
++#endif
++ret = rtw_android_cfg80211_pno_setup(dev, ssids,
++			n_ssids, interval);
++	if (ret < 0) {
++		RTW_INFO("%s ret: %d\n", __func__, ret);
++		goto exit;
++	}
++
++	ret = rtw_android_pno_enable(dev, _TRUE);
++	if (ret < 0) {
++		RTW_INFO("%s ret: %d\n", __func__, ret);
++		goto exit;
++	}
++exit:
++	return ret;
++}
++
++static int cfg80211_rtw_sched_scan_stop(struct wiphy *wiphy,
++		struct net_device *dev)
++{
++	return rtw_android_pno_enable(dev, _FALSE);
++}
++
++int	cfg80211_rtw_suspend(struct wiphy *wiphy, struct cfg80211_wowlan *wow) {
++	RTW_DBG("==> %s\n",__func__);
++	RTW_DBG("<== %s\n",__func__);
++	return 0;
++}
++
++int	cfg80211_rtw_resume(struct wiphy *wiphy) {
++
++	_adapter *padapter;
++	struct pwrctrl_priv *pwrpriv;
++	struct mlme_priv *pmlmepriv;
++	padapter = wiphy_to_adapter(wiphy);
++	pwrpriv = adapter_to_pwrctl(padapter);
++	pmlmepriv = &padapter->mlmepriv;
++	struct sitesurvey_parm parm;
++	int i, len;
++
++
++	RTW_DBG("==> %s\n",__func__);
++	if (pwrpriv->wowlan_last_wake_reason == RX_PNO) {
++
++		struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++		_irqL irqL;
++		int PNOWakeupScanWaitCnt = 0;
++
++		rtw_cfg80211_disconnected(padapter->rtw_wdev, 0, NULL, 0, 1, GFP_ATOMIC);
++
++		rtw_init_sitesurvey_parm(padapter, &parm);
++		for (i=0;i<pwrpriv->pnlo_info->ssid_num && i < RTW_SSID_SCAN_AMOUNT; i++) {
++			len = pwrpriv->pno_ssid_list->node[i].SSID_len;
++			_rtw_memcpy(&parm.ssid[i].Ssid, pwrpriv->pno_ssid_list->node[i].SSID, len);
++			parm.ssid[i].SsidLength = len;
++		}
++		parm.ssid_num = pwrpriv->pnlo_info->ssid_num;
++
++		_enter_critical_bh(&pmlmepriv->lock, &irqL);
++		//This modification fix PNO wakeup reconnect issue with hidden SSID AP.
++		//rtw_sitesurvey_cmd(padapter, NULL);
++		rtw_sitesurvey_cmd(padapter, &parm);
++		_exit_critical_bh(&pmlmepriv->lock, &irqL);
++		
++		for (PNOWakeupScanWaitCnt = 0; PNOWakeupScanWaitCnt < 10; PNOWakeupScanWaitCnt++) {
++			if(check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _FALSE)
++				break;
++			rtw_msleep_os(1000);
++		}
++		
++		_enter_critical_bh(&pmlmepriv->lock, &irqL);
++		cfg80211_sched_scan_results(padapter->rtw_wdev->wiphy);
++		_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++	}
++	RTW_DBG("<== %s\n",__func__);
++	return 0;
++	
++}
++#endif /* CONFIG_PNO_SUPPORT */
++
++static int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *ndev, char *buf, int len)
++{
++	int ret = 0;
++	uint wps_ielen = 0;
++	u8 *wps_ie;
++	u32	p2p_ielen = 0;
++	u8 wps_oui[8] = {0x0, 0x50, 0xf2, 0x04};
++	u8 *p2p_ie;
++	u32	wfd_ielen = 0;
++	u8 *wfd_ie;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++
++	RTW_INFO(FUNC_NDEV_FMT" ielen=%d\n", FUNC_NDEV_ARG(ndev), len);
++
++	if (len > 0) {
++		wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen);
++		if (wps_ie) {
++			#ifdef CONFIG_DEBUG_CFG80211
++			RTW_INFO("bcn_wps_ielen=%d\n", wps_ielen);
++			#endif
++
++			if (pmlmepriv->wps_beacon_ie) {
++				u32 free_len = pmlmepriv->wps_beacon_ie_len;
++				pmlmepriv->wps_beacon_ie_len = 0;
++				rtw_mfree(pmlmepriv->wps_beacon_ie, free_len);
++				pmlmepriv->wps_beacon_ie = NULL;
++			}
++
++			pmlmepriv->wps_beacon_ie = rtw_malloc(wps_ielen);
++			if (pmlmepriv->wps_beacon_ie == NULL) {
++				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++				return -EINVAL;
++
++			}
++
++			_rtw_memcpy(pmlmepriv->wps_beacon_ie, wps_ie, wps_ielen);
++			pmlmepriv->wps_beacon_ie_len = wps_ielen;
++
++			update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE, RTW_CMDF_WAIT_ACK);
++
++		}
++
++		/* buf += wps_ielen; */
++		/* len -= wps_ielen; */
++
++		#ifdef CONFIG_P2P
++		p2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen);
++		if (p2p_ie) {
++			#ifdef CONFIG_DEBUG_CFG80211
++			RTW_INFO("bcn_p2p_ielen=%d\n", p2p_ielen);
++			#endif
++
++			if (pmlmepriv->p2p_beacon_ie) {
++				u32 free_len = pmlmepriv->p2p_beacon_ie_len;
++				pmlmepriv->p2p_beacon_ie_len = 0;
++				rtw_mfree(pmlmepriv->p2p_beacon_ie, free_len);
++				pmlmepriv->p2p_beacon_ie = NULL;
++			}
++
++			pmlmepriv->p2p_beacon_ie = rtw_malloc(p2p_ielen);
++			if (pmlmepriv->p2p_beacon_ie == NULL) {
++				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++				return -EINVAL;
++
++			}
++
++			_rtw_memcpy(pmlmepriv->p2p_beacon_ie, p2p_ie, p2p_ielen);
++			pmlmepriv->p2p_beacon_ie_len = p2p_ielen;
++
++		}
++		#endif /* CONFIG_P2P */
++
++
++		#ifdef CONFIG_WFD
++		wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen);
++		if (wfd_ie) {
++			#ifdef CONFIG_DEBUG_CFG80211
++			RTW_INFO("bcn_wfd_ielen=%d\n", wfd_ielen);
++			#endif
++
++			if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_BEACON_IE, wfd_ie, wfd_ielen) != _SUCCESS)
++				return -EINVAL;
++		}
++		#endif /* CONFIG_WFD */
++
++		pmlmeext->bstart_bss = _TRUE;
++
++	}
++
++	return ret;
++
++}
++
++static int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *buf, int len)
++{
++	int ret = 0;
++	uint wps_ielen = 0;
++	u8 *wps_ie;
++	u32	p2p_ielen = 0;
++	u8 *p2p_ie;
++	u32	wfd_ielen = 0;
++	u8 *wfd_ie;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++#ifdef CONFIG_DEBUG_CFG80211
++	RTW_INFO("%s, ielen=%d\n", __func__, len);
++#endif
++
++	if (len > 0) {
++		wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen);
++		if (wps_ie) {
++			uint	attr_contentlen = 0;
++			u16	uconfig_method, *puconfig_method = NULL;
++
++			#ifdef CONFIG_DEBUG_CFG80211
++			RTW_INFO("probe_resp_wps_ielen=%d\n", wps_ielen);
++			#endif
++
++			if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
++				u8 sr = 0;
++				rtw_get_wps_attr_content(wps_ie,  wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);
++
++				if (sr != 0)
++					RTW_INFO("%s, got sr\n", __func__);
++				else {
++					RTW_INFO("GO mode process WPS under site-survey,  sr no set\n");
++					return ret;
++				}
++			}
++
++			if (pmlmepriv->wps_probe_resp_ie) {
++				u32 free_len = pmlmepriv->wps_probe_resp_ie_len;
++				pmlmepriv->wps_probe_resp_ie_len = 0;
++				rtw_mfree(pmlmepriv->wps_probe_resp_ie, free_len);
++				pmlmepriv->wps_probe_resp_ie = NULL;
++			}
++
++			pmlmepriv->wps_probe_resp_ie = rtw_malloc(wps_ielen);
++			if (pmlmepriv->wps_probe_resp_ie == NULL) {
++				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++				return -EINVAL;
++
++			}
++
++			/* add PUSH_BUTTON config_method by driver self in wpsie of probe_resp at GO Mode */
++			puconfig_method = (u16 *)rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_CONF_METHOD , NULL, &attr_contentlen);
++			if (puconfig_method != NULL) {
++				/* struct registry_priv *pregistrypriv = &padapter->registrypriv; */
++				struct wireless_dev *wdev = padapter->rtw_wdev;
++
++				#ifdef CONFIG_DEBUG_CFG80211
++				/* printk("config_method in wpsie of probe_resp = 0x%x\n", be16_to_cpu(*puconfig_method)); */
++				#endif
++
++				#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++				/* for WIFI-DIRECT LOGO 4.2.2, AUTO GO can't set PUSH_BUTTON flags */
++				if (wdev->iftype == NL80211_IFTYPE_P2P_GO) {
++					uconfig_method = WPS_CM_PUSH_BUTTON;
++					uconfig_method = cpu_to_be16(uconfig_method);
++
++					*puconfig_method &= ~uconfig_method;
++				}
++				#endif
++			}
++
++			_rtw_memcpy(pmlmepriv->wps_probe_resp_ie, wps_ie, wps_ielen);
++			pmlmepriv->wps_probe_resp_ie_len = wps_ielen;
++
++		}
++
++		/* buf += wps_ielen; */
++		/* len -= wps_ielen; */
++
++		#ifdef CONFIG_P2P
++		p2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen);
++		if (p2p_ie) {
++			u8 is_GO = _FALSE;
++			u32 attr_contentlen = 0;
++			u16 cap_attr = 0;
++
++			#ifdef CONFIG_DEBUG_CFG80211
++			RTW_INFO("probe_resp_p2p_ielen=%d\n", p2p_ielen);
++			#endif
++
++			/* Check P2P Capability ATTR */
++			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *) &attr_contentlen)) {
++				u8 grp_cap = 0;
++				/* RTW_INFO( "[%s] Got P2P Capability Attr!!\n", __FUNCTION__ ); */
++				cap_attr = le16_to_cpu(cap_attr);
++				grp_cap = (u8)((cap_attr >> 8) & 0xff);
++
++				is_GO = (grp_cap & BIT(0)) ? _TRUE : _FALSE;
++
++				if (is_GO)
++					RTW_INFO("Got P2P Capability Attr, grp_cap=0x%x, is_GO\n", grp_cap);
++			}
++
++
++			if (is_GO == _FALSE) {
++				if (pmlmepriv->p2p_probe_resp_ie) {
++					u32 free_len = pmlmepriv->p2p_probe_resp_ie_len;
++					pmlmepriv->p2p_probe_resp_ie_len = 0;
++					rtw_mfree(pmlmepriv->p2p_probe_resp_ie, free_len);
++					pmlmepriv->p2p_probe_resp_ie = NULL;
++				}
++
++				pmlmepriv->p2p_probe_resp_ie = rtw_malloc(p2p_ielen);
++				if (pmlmepriv->p2p_probe_resp_ie == NULL) {
++					RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++					return -EINVAL;
++
++				}
++				_rtw_memcpy(pmlmepriv->p2p_probe_resp_ie, p2p_ie, p2p_ielen);
++				pmlmepriv->p2p_probe_resp_ie_len = p2p_ielen;
++			} else {
++				if (pmlmepriv->p2p_go_probe_resp_ie) {
++					u32 free_len = pmlmepriv->p2p_go_probe_resp_ie_len;
++					pmlmepriv->p2p_go_probe_resp_ie_len = 0;
++					rtw_mfree(pmlmepriv->p2p_go_probe_resp_ie, free_len);
++					pmlmepriv->p2p_go_probe_resp_ie = NULL;
++				}
++
++				pmlmepriv->p2p_go_probe_resp_ie = rtw_malloc(p2p_ielen);
++				if (pmlmepriv->p2p_go_probe_resp_ie == NULL) {
++					RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++					return -EINVAL;
++
++				}
++				_rtw_memcpy(pmlmepriv->p2p_go_probe_resp_ie, p2p_ie, p2p_ielen);
++				pmlmepriv->p2p_go_probe_resp_ie_len = p2p_ielen;
++			}
++
++		}
++		#endif /* CONFIG_P2P */
++
++
++		#ifdef CONFIG_WFD
++		wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen);
++		#ifdef CONFIG_DEBUG_CFG80211
++		RTW_INFO("probe_resp_wfd_ielen=%d\n", wfd_ielen);
++		#endif
++
++		if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_PROBE_RESP_IE, wfd_ie, wfd_ielen) != _SUCCESS)
++			return -EINVAL;
++		#endif /* CONFIG_WFD */
++
++	}
++
++	return ret;
++
++}
++
++static int rtw_cfg80211_set_assoc_resp_wpsp2pie(struct net_device *net, char *buf, int len)
++{
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	u8 *ie;
++	u32 ie_len;
++
++	RTW_INFO("%s, ielen=%d\n", __func__, len);
++
++	if (len <= 0)
++		goto exit;
++
++	ie = rtw_get_wps_ie(buf, len, NULL, &ie_len);
++	if (ie && ie_len) {
++		if (pmlmepriv->wps_assoc_resp_ie) {
++			u32 free_len = pmlmepriv->wps_assoc_resp_ie_len;
++
++			pmlmepriv->wps_assoc_resp_ie_len = 0;
++			rtw_mfree(pmlmepriv->wps_assoc_resp_ie, free_len);
++			pmlmepriv->wps_assoc_resp_ie = NULL;
++		}
++
++		pmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len);
++		if (pmlmepriv->wps_assoc_resp_ie == NULL) {
++			RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++			return -EINVAL;
++		}
++		_rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, ie, ie_len);
++		pmlmepriv->wps_assoc_resp_ie_len = ie_len;
++	}
++
++	ie = rtw_get_p2p_ie(buf, len, NULL, &ie_len);
++	if (ie && ie_len) {
++		if (pmlmepriv->p2p_assoc_resp_ie) {
++			u32 free_len = pmlmepriv->p2p_assoc_resp_ie_len;
++
++			pmlmepriv->p2p_assoc_resp_ie_len = 0;
++			rtw_mfree(pmlmepriv->p2p_assoc_resp_ie, free_len);
++			pmlmepriv->p2p_assoc_resp_ie = NULL;
++		}
++
++		pmlmepriv->p2p_assoc_resp_ie = rtw_malloc(ie_len);
++		if (pmlmepriv->p2p_assoc_resp_ie == NULL) {
++			RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++			return -EINVAL;
++		}
++		_rtw_memcpy(pmlmepriv->p2p_assoc_resp_ie, ie, ie_len);
++		pmlmepriv->p2p_assoc_resp_ie_len = ie_len;
++	}
++
++#ifdef CONFIG_WFD
++	ie = rtw_get_wfd_ie(buf, len, NULL, &ie_len);
++	if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_ASSOC_RESP_IE, ie, ie_len) != _SUCCESS)
++		return -EINVAL;
++#endif
++
++exit:
++	return ret;
++}
++
++int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len,
++	int type)
++{
++	int ret = 0;
++	uint wps_ielen = 0;
++	u32	p2p_ielen = 0;
++
++#ifdef CONFIG_DEBUG_CFG80211
++	RTW_INFO("%s, ielen=%d\n", __func__, len);
++#endif
++
++	if ((rtw_get_wps_ie(buf, len, NULL, &wps_ielen) && (wps_ielen > 0))
++		#ifdef CONFIG_P2P
++		|| (rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen) && (p2p_ielen > 0))
++		#endif
++	) {
++		if (net != NULL) {
++			switch (type) {
++			case 0x1: /* BEACON */
++				ret = rtw_cfg80211_set_beacon_wpsp2pie(net, buf, len);
++				break;
++			case 0x2: /* PROBE_RESP */
++				ret = rtw_cfg80211_set_probe_resp_wpsp2pie(net, buf, len);
++				#ifdef CONFIG_P2P
++				if (ret == 0)
++					adapter_wdev_data((_adapter *)rtw_netdev_priv(net))->probe_resp_ie_update_time = rtw_get_current_time();
++				#endif
++				break;
++			case 0x4: /* ASSOC_RESP */
++				ret = rtw_cfg80211_set_assoc_resp_wpsp2pie(net, buf, len);
++				break;
++			}
++		}
++	}
++
++	return ret;
++
++}
++
++#ifdef CONFIG_80211N_HT
++static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter
++	, struct ieee80211_sta_ht_cap *ht_cap, BAND_TYPE band, u8 rf_type)
++{
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
++	u8 stbc_rx_enable = _FALSE;
++
++	rtw_ht_use_default_setting(padapter);
++
++	/* RX LDPC */
++	if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX))
++		ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
++
++	/* TX STBC */
++	if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX))
++		ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC;
++
++	/* RX STBC */
++	if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) {
++		/*rtw_rx_stbc 0: disable, bit(0):enable 2.4g, bit(1):enable 5g*/
++		if (band == BAND_ON_2_4G)
++			stbc_rx_enable = (pregistrypriv->rx_stbc & BIT(0)) ? _TRUE : _FALSE;
++		if (band == BAND_ON_5G)
++			stbc_rx_enable = (pregistrypriv->rx_stbc & BIT(1)) ? _TRUE : _FALSE;
++
++		if (stbc_rx_enable) {
++			switch (rf_type) {
++			case RF_1T1R:
++				ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/*RX STBC One spatial stream*/
++				break;
++
++			case RF_2T2R:
++			case RF_1T2R:
++				ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/* Only one spatial-stream STBC RX is supported */
++				break;
++			case RF_3T3R:
++			case RF_3T4R:
++			case RF_4T4R:
++				ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/* Only one spatial-stream STBC RX is supported */
++				break;
++			default:
++				RTW_INFO("[warning] rf_type %d is not expected\n", rf_type);
++				break;
++			}
++		}
++	}
++}
++
++static void rtw_cfg80211_init_ht_capab(_adapter *padapter
++	, struct ieee80211_sta_ht_cap *ht_cap, BAND_TYPE band, u8 rf_type)
++{
++	struct registry_priv *regsty = &padapter->registrypriv;
++	u8 rx_nss = 0;
++
++	if (!regsty->ht_enable || !is_supported_ht(regsty->wireless_mode))
++		return;
++
++	ht_cap->ht_supported = 1;
++
++	ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
++				IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20 |
++				IEEE80211_HT_CAP_DSSSCCK40 | IEEE80211_HT_CAP_MAX_AMSDU;
++	rtw_cfg80211_init_ht_capab_ex(padapter, ht_cap, band, rf_type);
++
++	/*
++	 *Maximum length of AMPDU that the STA can receive.
++	 *Length = 2 ^ (13 + max_ampdu_length_exp) - 1 (octets)
++	 */
++	ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
++
++	/*Minimum MPDU start spacing , */
++	ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
++
++	ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
++
++	rx_nss = GET_HAL_RX_NSS(padapter);
++	switch (rx_nss) {
++	case 1:
++		ht_cap->mcs.rx_mask[0] = 0xFF;
++		break;
++	case 2:
++		ht_cap->mcs.rx_mask[0] = 0xFF;
++		ht_cap->mcs.rx_mask[1] = 0xFF;
++		break;
++	case 3:
++		ht_cap->mcs.rx_mask[0] = 0xFF;
++		ht_cap->mcs.rx_mask[1] = 0xFF;
++		ht_cap->mcs.rx_mask[2] = 0xFF;
++		break;
++	case 4:
++		ht_cap->mcs.rx_mask[0] = 0xFF;
++		ht_cap->mcs.rx_mask[1] = 0xFF;
++		ht_cap->mcs.rx_mask[2] = 0xFF;
++		ht_cap->mcs.rx_mask[3] = 0xFF;
++		break;
++	default:
++		rtw_warn_on(1);
++		RTW_INFO("%s, error rf_type=%d, rx_nss=%d\n", __func__, rf_type, rx_nss);
++	};
++
++	ht_cap->mcs.rx_highest = cpu_to_le16(
++		rtw_ht_mcs_rate(hal_is_bw_support(padapter, CHANNEL_WIDTH_40)
++			, hal_is_bw_support(padapter, CHANNEL_WIDTH_40) ? ht_cap->cap & IEEE80211_HT_CAP_SGI_40 : ht_cap->cap & IEEE80211_HT_CAP_SGI_20
++			, ht_cap->mcs.rx_mask) / 10);
++}
++#endif /* CONFIG_80211N_HT */
++
++#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++static void rtw_cfg80211_init_vht_capab(_adapter *padapter
++	, struct ieee80211_sta_vht_cap *sta_vht_cap, BAND_TYPE band, u8 rf_type)
++{
++	struct registry_priv *regsty = &padapter->registrypriv;
++	u8 vht_cap_ie[2 + 12] = {0};
++
++	if (!REGSTY_IS_11AC_ENABLE(regsty) || !is_supported_vht(regsty->wireless_mode))
++		return;
++
++	rtw_vht_use_default_setting(padapter);
++	rtw_build_vht_cap_ie(padapter, vht_cap_ie);
++
++	sta_vht_cap->vht_supported = 1;
++
++	_rtw_memcpy(&sta_vht_cap->cap, vht_cap_ie + 2, 4);
++	_rtw_memcpy(&sta_vht_cap->vht_mcs, vht_cap_ie + 2 + 4, 8);
++}
++#endif /* defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) */
++
++void rtw_cfg80211_init_wdev_data(_adapter *padapter)
++{
++#ifdef CONFIG_CONCURRENT_MODE
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++
++	ATOMIC_SET(&pwdev_priv->switch_ch_to, 1);
++#endif
++}
++
++void rtw_cfg80211_init_wiphy(_adapter *padapter)
++{
++	u8 rf_type;
++	struct ieee80211_supported_band *band;
++	struct wireless_dev *pwdev = padapter->rtw_wdev;
++	struct wiphy *wiphy = pwdev->wiphy;
++
++	rf_type = GET_HAL_RFPATH(padapter);
++	RTW_INFO("%s:rf_type=%d\n", __func__, rf_type);
++
++	if (IsSupported24G(padapter->registrypriv.wireless_mode)) {
++		band = wiphy->bands[NL80211_BAND_2GHZ];
++		if (band) {
++			#if defined(CONFIG_80211N_HT)
++			rtw_cfg80211_init_ht_capab(padapter, &band->ht_cap, BAND_ON_2_4G, rf_type);
++			#endif
++		}
++	}
++#if CONFIG_IEEE80211_BAND_5GHZ
++	if (is_supported_5g(padapter->registrypriv.wireless_mode)) {
++		band = wiphy->bands[NL80211_BAND_5GHZ];
++		if (band) {
++			#if defined(CONFIG_80211N_HT)
++			rtw_cfg80211_init_ht_capab(padapter, &band->ht_cap, BAND_ON_5G, rf_type);
++			#endif
++			#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++			rtw_cfg80211_init_vht_capab(padapter, &band->vht_cap, BAND_ON_5G, rf_type);
++			#endif
++		}
++	}
++#endif
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) && defined(RTW_SINGLE_WIPHY) && (CONFIG_IFACE_NUMBER >= 2)
++struct ieee80211_iface_limit rtw_limits[] = {
++	{
++		.max = CONFIG_IFACE_NUMBER,
++		.types = BIT(NL80211_IFTYPE_STATION)
++			#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
++			| BIT(NL80211_IFTYPE_P2P_CLIENT)
++			#endif
++	},
++	#ifdef CONFIG_AP_MODE
++	{
++		.max = rtw_min(CONFIG_IFACE_NUMBER, CONFIG_LIMITED_AP_NUM),
++		.types = BIT(NL80211_IFTYPE_AP)
++			#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
++			| BIT(NL80211_IFTYPE_P2P_GO)
++			#endif
++	},
++	#endif
++	#if defined(RTW_DEDICATED_P2P_DEVICE)
++	{
++		.max = 1,
++		.types = BIT(NL80211_IFTYPE_P2P_DEVICE)
++	},
++	#endif
++	#if defined(CONFIG_RTW_MESH)
++	{
++		.max = 1,
++		.types = BIT(NL80211_IFTYPE_MESH_POINT)
++	},
++	#endif
++};
++
++struct ieee80211_iface_combination rtw_combinations[] = {
++	{
++		.limits = rtw_limits,
++		.n_limits = ARRAY_SIZE(rtw_limits),
++		#if defined(RTW_DEDICATED_P2P_DEVICE)
++		.max_interfaces = CONFIG_IFACE_NUMBER + 1,
++		#else
++		.max_interfaces = CONFIG_IFACE_NUMBER,
++		#endif
++		.num_different_channels = 1,
++	},
++};
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) */
++
++static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
++
++	/* copy mac_addr to wiphy */
++	_rtw_memcpy(wiphy->perm_addr, adapter_mac_addr(adapter), ETH_ALEN);
++
++	wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
++
++	wiphy->max_scan_ssids = RTW_SSID_SCAN_AMOUNT;
++	wiphy->max_scan_ie_len = RTW_SCAN_IE_LEN_MAX;
++	wiphy->max_num_pmkids = RTW_MAX_NUM_PMKIDS;
++
++#if CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++	wiphy->max_acl_mac_addrs = NUM_ACL;
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
++	wiphy->max_remain_on_channel_duration = RTW_MAX_REMAIN_ON_CHANNEL_DURATION;
++#endif
++
++	wiphy->interface_modes =	BIT(NL80211_IFTYPE_STATION)
++								| BIT(NL80211_IFTYPE_ADHOC)
++#ifdef CONFIG_AP_MODE
++								| BIT(NL80211_IFTYPE_AP)
++								#ifdef CONFIG_WIFI_MONITOR
++								| BIT(NL80211_IFTYPE_MONITOR)
++								#endif
++#endif
++#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
++								| BIT(NL80211_IFTYPE_P2P_CLIENT)
++								| BIT(NL80211_IFTYPE_P2P_GO)
++								#if defined(RTW_DEDICATED_P2P_DEVICE)
++								| BIT(NL80211_IFTYPE_P2P_DEVICE)
++								#endif
++#endif
++#ifdef CONFIG_RTW_MESH
++								| BIT(NL80211_IFTYPE_MESH_POINT) /* 2.6.26 */
++#endif
++								;
++
++#if !defined(RTW_SINGLE_WIPHY) && defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_P2P)
++	if (adapter->iface_id != adapter->registrypriv.sel_p2p_iface) {
++		wiphy->interface_modes &= ~(BIT(NL80211_IFTYPE_P2P_GO) | BIT(NL80211_IFTYPE_P2P_CLIENT));
++		RTW_INFO("%s iface_id:%d- don't set p2p capability\n", __func__, adapter->iface_id);
++	}
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++#ifdef CONFIG_AP_MODE
++	wiphy->mgmt_stypes = rtw_cfg80211_default_mgmt_stypes;
++#endif /* CONFIG_AP_MODE */
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	#ifdef CONFIG_WIFI_MONITOR
++	wiphy->software_iftypes |= BIT(NL80211_IFTYPE_MONITOR);
++	#endif
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) && defined(RTW_SINGLE_WIPHY) && (CONFIG_IFACE_NUMBER >= 2)
++	wiphy->iface_combinations = rtw_combinations;
++	wiphy->n_iface_combinations = ARRAY_SIZE(rtw_combinations);
++#endif
++
++	wiphy->cipher_suites = rtw_cipher_suites;
++
++	/* Todo refine */
++	if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_EXTRA_SEC))
++		wiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites);
++	else {
++#ifdef CONFIG_IEEE80211W
++		/* remove hardware not support cipher */
++		wiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites) - 6;
++#else
++		wiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites);
++#endif
++	}
++
++	if (IsSupported24G(adapter->registrypriv.wireless_mode))
++		wiphy->bands[NL80211_BAND_2GHZ] = rtw_spt_band_alloc(BAND_ON_2_4G);
++
++#if CONFIG_IEEE80211_BAND_5GHZ
++	if (is_supported_5g(adapter->registrypriv.wireless_mode))
++		wiphy->bands[NL80211_BAND_5GHZ] = rtw_spt_band_alloc(BAND_ON_5G);
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38) && LINUX_VERSION_CODE < KERNEL_VERSION(3, 0, 0))
++	wiphy->flags |= WIPHY_FLAG_SUPPORTS_SEPARATE_DEFAULT_KEYS;
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
++	wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
++	wiphy->flags |= WIPHY_FLAG_HAVE_AP_SME;
++	/* remove WIPHY_FLAG_OFFCHAN_TX, because we not support this feature */
++	/* wiphy->flags |= WIPHY_FLAG_OFFCHAN_TX | WIPHY_FLAG_HAVE_AP_SME; */
++#endif
++
++#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) && \
++			   LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
++	wiphy->flags |= WIPHY_FLAG_SUPPORTS_SCHED_SCAN;
++#ifdef CONFIG_PNO_SUPPORT
++	wiphy->max_sched_scan_ssids = MAX_PNO_LIST_COUNT;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)
++	wiphy->max_match_sets = MAX_PNO_LIST_COUNT;
++#endif
++#endif
++#endif
++
++#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0))
++	wiphy->wowlan = wowlan_stub;
++#else
++	wiphy->wowlan = &wowlan_stub;
++#endif
++#endif
++
++#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
++#ifndef CONFIG_TDLS_DRIVER_SETUP
++	wiphy->flags |= WIPHY_FLAG_TDLS_EXTERNAL_SETUP;	/* Driver handles key exchange */
++	wiphy->flags |= NL80211_ATTR_HT_CAPABILITY;
++#endif /* CONFIG_TDLS_DRIVER_SETUP */
++#endif /* CONFIG_TDLS */
++
++	if (regsty->power_mgnt != PS_MODE_ACTIVE)
++		wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT;
++	else
++		wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	/* wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM; */
++#endif
++
++#ifdef CONFIG_RTW_WDS
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33))
++	wiphy->flags |= WIPHY_FLAG_4ADDR_AP;
++	wiphy->flags |= WIPHY_FLAG_4ADDR_STATION;
++	#endif
++#endif
++
++#ifdef CONFIG_RTW_MESH
++	wiphy->flags |= 0
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
++		| WIPHY_FLAG_IBSS_RSN
++		#endif
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++		| WIPHY_FLAG_MESH_AUTH
++		#endif
++		;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
++	wiphy->features |= 0
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
++		| NL80211_FEATURE_USERSPACE_MPM
++		#endif
++		;
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) */
++#endif /* CONFIG_RTW_MESH */
++
++#if defined(CONFIG_RTW_80211K) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 6, 0))
++	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_RRM);
++#endif
++
++#if (KERNEL_VERSION(3, 8, 0) <= LINUX_VERSION_CODE)
++	wiphy->features |= NL80211_FEATURE_SAE;
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++#ifdef CONFIG_WIFI_MONITOR
++	/* Currently only for Monitor debugging */
++	wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
++#endif
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) */
++}
++
++#ifdef CONFIG_RFKILL_POLL
++void rtw_cfg80211_init_rfkill(struct wiphy *wiphy)
++{
++	wiphy_rfkill_set_hw_state(wiphy, 0);
++	wiphy_rfkill_start_polling(wiphy);
++}
++
++void rtw_cfg80211_deinit_rfkill(struct wiphy *wiphy)
++{
++	wiphy_rfkill_stop_polling(wiphy);
++}
++
++static void cfg80211_rtw_rfkill_poll(struct wiphy *wiphy)
++{
++	_adapter *padapter = NULL;
++	bool blocked = _FALSE;
++	u8 valid = 0;
++
++	padapter = wiphy_to_adapter(wiphy);
++
++	if (adapter_to_dvobj(padapter)->processing_dev_remove == _TRUE) {
++		/*RTW_INFO("cfg80211_rtw_rfkill_poll: device is removed!\n");*/
++		return;
++	}
++
++	blocked = rtw_hal_rfkill_poll(padapter, &valid);
++	/*RTW_INFO("cfg80211_rtw_rfkill_poll: valid=%d, blocked=%d\n",
++			valid, blocked);*/
++
++	if (valid)
++		wiphy_rfkill_set_hw_state(wiphy, blocked);
++}
++#endif
++
++#if defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33))
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))
++#define SURVEY_INFO_TIME			SURVEY_INFO_CHANNEL_TIME
++#define SURVEY_INFO_TIME_BUSY		SURVEY_INFO_CHANNEL_TIME_BUSY
++#define SURVEY_INFO_TIME_EXT_BUSY	SURVEY_INFO_CHANNEL_TIME_EXT_BUSY
++#define SURVEY_INFO_TIME_RX			SURVEY_INFO_CHANNEL_TIME_RX
++#define SURVEY_INFO_TIME_TX			SURVEY_INFO_CHANNEL_TIME_TX
++#endif
++
++#ifdef CONFIG_FIND_BEST_CHANNEL
++static void rtw_cfg80211_set_survey_info_with_find_best_channel(struct wiphy *wiphy
++	, struct net_device *netdev, int idx, struct survey_info *info)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	RT_CHANNEL_INFO *ch_set = rfctl->channel_set;
++	u8 ch_num = rfctl->max_chan_nums;
++	u32 total_rx_cnt = 0;
++	int i;
++
++	s8 noise = -50;		/*channel noise in dBm. This and all following fields are optional */
++	u64 time = 100;		/*amount of time in ms the radio was turn on (on the channel)*/
++	u64 time_busy = 0;	/*amount of time the primary channel was sensed busy*/
++
++	info->filled  = SURVEY_INFO_NOISE_DBM
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
++		| SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY
++		#endif
++		;
++
++	for (i = 0; i < ch_num; i++)
++		total_rx_cnt += ch_set[i].rx_count;
++
++	time_busy = ch_set[idx].rx_count * time / total_rx_cnt;
++	noise += ch_set[idx].rx_count * 50 / total_rx_cnt;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
++	#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))
++	info->channel_time = time;
++	info->channel_time_busy = time_busy;
++	#else
++	info->time = time;
++	info->time_busy = time_busy;
++	#endif
++#endif
++	info->noise = noise;
++
++	/* reset if final channel is got */
++	if (idx == ch_num - 1) {
++		for (i = 0; i < ch_num; i++)
++			ch_set[i].rx_count = 0;
++	}
++}
++#endif /* CONFIG_FIND_BEST_CHANNEL */
++
++#if defined(CONFIG_RTW_ACS) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
++static void rtw_cfg80211_set_survey_info_with_clm(PADAPTER padapter, int idx, struct survey_info *pinfo)
++{
++	s8 noise = -50;			/*channel noise in dBm. This and all following fields are optional */
++	u64 time = SURVEY_TO;	/*amount of time in ms the radio was turn on (on the channel)*/
++	u64 time_busy = 0;		/*amount of time the primary channel was sensed busy*/
++	u8 chan = (u8)idx;
++
++	if ((idx < 0) || (pinfo == NULL))
++		return;
++
++	pinfo->filled  = SURVEY_INFO_NOISE_DBM
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
++		| SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY
++		#endif
++		;
++
++	time_busy = rtw_acs_get_clm_ratio_by_ch_idx(padapter, chan);
++	noise = rtw_noise_query_by_chan_idx(padapter, chan);
++	/* RTW_INFO("%s: ch-idx:%d time=%llu(ms), time_busy=%llu(ms), noise=%d(dbm)\n", __func__, idx, time, time_busy, noise); */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
++	#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))
++	pinfo->channel_time = time;
++	pinfo->channel_time_busy = time_busy;
++	#else
++	pinfo->time = time;
++	pinfo->time_busy = time_busy;
++	#endif
++#endif
++	pinfo->noise = noise;
++}
++#endif
++
++int rtw_hostapd_acs_dump_survey(struct wiphy *wiphy, struct net_device *netdev, int idx, struct survey_info *info)
++{
++	PADAPTER padapter = (_adapter *)rtw_netdev_priv(netdev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	RT_CHANNEL_INFO *pch_set = rfctl->channel_set;
++	u8 max_chan_nums = rfctl->max_chan_nums;
++	u32 freq = 0;
++	u8 ret = 0;
++	u16 channel = 0;
++
++	if (!netdev || !info) {
++		RTW_INFO("%s: invial parameters.\n", __func__);
++		return -EINVAL;
++	}
++
++	_rtw_memset(info, 0, sizeof(struct survey_info));
++	if (padapter->bup == _FALSE) {
++		RTW_INFO("%s: net device is down.\n", __func__);
++		return -EIO;
++	}
++
++	if (idx >= max_chan_nums)
++		return -ENOENT;
++
++	channel = pch_set[idx].ChannelNum;
++	freq = rtw_ch2freq(channel);
++	info->channel = ieee80211_get_channel(wiphy, freq);
++	/* RTW_INFO("%s: channel %d, freq %d\n", __func__, channel, freq); */
++
++	if (!info->channel)
++		return -EINVAL;
++
++	if (info->channel->flags == IEEE80211_CHAN_DISABLED)
++		return ret;
++
++#ifdef CONFIG_FIND_BEST_CHANNEL
++	rtw_cfg80211_set_survey_info_with_find_best_channel(wiphy, netdev, idx, info);
++#elif defined(CONFIG_RTW_ACS) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
++	rtw_cfg80211_set_survey_info_with_clm(padapter, idx, info);
++#else
++	RTW_ERR("%s: unknown acs operation!\n", __func__); 
++#endif
++
++	return ret;
++}
++#endif /* defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33)) */
++
++#if (KERNEL_VERSION(4, 17, 0) <= LINUX_VERSION_CODE)
++int cfg80211_rtw_external_auth(struct wiphy *wiphy, struct net_device *dev,
++	struct cfg80211_external_auth_params *params)
++{
++	PADAPTER padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(dev));
++
++	rtw_cfg80211_external_auth_status(wiphy, dev,
++		(struct rtw_external_auth_params *)params);
++
++	return 0;
++}
++#endif
++
++void rtw_cfg80211_external_auth_status(struct wiphy *wiphy, struct net_device *dev,
++	struct rtw_external_auth_params *params)
++{
++	PADAPTER padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct sta_info	*psta = NULL;
++	u8 *buf = NULL;
++	u32 len = 0;
++	_irqL irqL;
++
++	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(dev));
++
++	RTW_INFO("SAE: action: %u, status: %u\n", params->action, params->status);
++	if (params->status == WLAN_STATUS_SUCCESS) {
++		RTW_INFO("bssid: "MAC_FMT"\n", MAC_ARG(params->bssid));
++		RTW_INFO("SSID: [%s]\n",
++			((params->ssid.ssid_len == 0) ? "" : (char *)params->ssid.ssid));
++		RTW_INFO("suite: 0x%08x\n", params->key_mgmt_suite);
++	}
++
++	psta = rtw_get_stainfo(pstapriv, params->bssid);
++	if (psta && (params->status == WLAN_STATUS_SUCCESS)) {
++		/* AP mode */
++		RTW_INFO("station match\n");
++
++		psta->state &= ~WIFI_FW_AUTH_NULL;
++		psta->state |= WIFI_FW_AUTH_SUCCESS;
++		psta->expire_to = padapter->stapriv.assoc_to;
++
++		/* ToDo: Kernel v5.1 pmkid is pointer */
++		/* RTW_INFO_DUMP("PMKID:", params->pmkid, PMKID_LEN); */
++		_rtw_set_pmksa(dev, params->bssid, params->pmkid);
++
++		_enter_critical_bh(&psta->lock, &irqL);
++		if ((psta->auth_len != 0) && (psta->pauth_frame != NULL)) {
++			buf =  rtw_zmalloc(psta->auth_len);
++			if (buf) {
++				_rtw_memcpy(buf, psta->pauth_frame, psta->auth_len);
++				len = psta->auth_len;
++			}
++
++			rtw_mfree(psta->pauth_frame, psta->auth_len);
++			psta->pauth_frame = NULL;
++			psta->auth_len = 0;
++		}
++		_exit_critical_bh(&psta->lock, &irqL);
++
++		if (buf) {
++			struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++			/* send the SAE auth Confirm */
++
++			rtw_ps_deny(padapter, PS_DENY_MGNT_TX);
++			if (_SUCCESS == rtw_pwr_wakeup(padapter)) {
++				rtw_mi_set_scan_deny(padapter, 1000);
++				rtw_mi_scan_abort(padapter, _TRUE);
++
++				RTW_INFO("SAE: Tx auth Confirm\n");
++				rtw_mgnt_tx_cmd(padapter, pmlmeext->cur_channel, 1, buf, len, 0, RTW_CMDF_DIRECTLY);
++
++			}
++			rtw_ps_deny_cancel(padapter, PS_DENY_MGNT_TX);
++
++			rtw_mfree(buf, len);
++			buf = NULL;
++			len = 0;
++		}
++	} else {
++		/* STA mode */
++		psecuritypriv->extauth_status = params->status;
++	}
++}
++
++static struct cfg80211_ops rtw_cfg80211_ops = {
++	.change_virtual_intf = cfg80211_rtw_change_iface,
++	.add_key = cfg80211_rtw_add_key,
++	.get_key = cfg80211_rtw_get_key,
++	.del_key = cfg80211_rtw_del_key,
++	.set_default_key = cfg80211_rtw_set_default_key,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30))
++	.set_default_mgmt_key = cfg80211_rtw_set_default_mgmt_key,
++#endif
++#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
++	.set_rekey_data = cfg80211_rtw_set_rekey_data,
++#endif /*CONFIG_GTK_OL*/
++	.get_station = cfg80211_rtw_get_station,
++	.scan = cfg80211_rtw_scan,
++	.set_wiphy_params = cfg80211_rtw_set_wiphy_params,
++	.connect = cfg80211_rtw_connect,
++	.disconnect = cfg80211_rtw_disconnect,
++	.join_ibss = cfg80211_rtw_join_ibss,
++	.leave_ibss = cfg80211_rtw_leave_ibss,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
++	.set_tx_power = cfg80211_rtw_set_txpower,
++	.get_tx_power = cfg80211_rtw_get_txpower,
++#endif
++	.set_power_mgmt = cfg80211_rtw_set_power_mgmt,
++	.set_pmksa = cfg80211_rtw_set_pmksa,
++	.del_pmksa = cfg80211_rtw_del_pmksa,
++	.flush_pmksa = cfg80211_rtw_flush_pmksa,
++
++#ifdef CONFIG_AP_MODE
++	.add_virtual_intf = cfg80211_rtw_add_virtual_intf,
++	.del_virtual_intf = cfg80211_rtw_del_virtual_intf,
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE)
++	.add_beacon = cfg80211_rtw_add_beacon,
++	.set_beacon = cfg80211_rtw_set_beacon,
++	.del_beacon = cfg80211_rtw_del_beacon,
++#else
++	.start_ap = cfg80211_rtw_start_ap,
++	.change_beacon = cfg80211_rtw_change_beacon,
++	.stop_ap = cfg80211_rtw_stop_ap,
++#endif
++
++#if CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
++	.set_mac_acl = cfg80211_rtw_set_mac_acl,
++#endif
++
++	.add_station = cfg80211_rtw_add_station,
++	.del_station = cfg80211_rtw_del_station,
++	.change_station = cfg80211_rtw_change_station,
++	.dump_station = cfg80211_rtw_dump_station,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28))
++	.change_bss = cfg80211_rtw_change_bss,
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
++	.set_txq_params = cfg80211_rtw_set_txq_params,
++#endif
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++	.set_channel = cfg80211_rtw_set_channel,
++#endif
++	/* .auth = cfg80211_rtw_auth, */
++	/* .assoc = cfg80211_rtw_assoc,	 */
++#endif /* CONFIG_AP_MODE */
++
++#if defined(CONFIG_RTW_MESH) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
++	.get_mesh_config = cfg80211_rtw_get_mesh_config,
++	.update_mesh_config = cfg80211_rtw_update_mesh_config,
++	.join_mesh = cfg80211_rtw_join_mesh,
++	.leave_mesh = cfg80211_rtw_leave_mesh,
++	.add_mpath = cfg80211_rtw_add_mpath,
++	.del_mpath = cfg80211_rtw_del_mpath,
++	.change_mpath = cfg80211_rtw_change_mpath,
++	.get_mpath = cfg80211_rtw_get_mpath,
++	.dump_mpath = cfg80211_rtw_dump_mpath,
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++	.get_mpp = cfg80211_rtw_get_mpp,
++	.dump_mpp = cfg80211_rtw_dump_mpp,
++	#endif
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++	.set_monitor_channel = cfg80211_rtw_set_monitor_channel,
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	.get_channel = cfg80211_rtw_get_channel,
++#endif
++
++#ifdef CONFIG_P2P
++	.remain_on_channel = cfg80211_rtw_remain_on_channel,
++	.cancel_remain_on_channel = cfg80211_rtw_cancel_remain_on_channel,
++	#if defined(RTW_DEDICATED_P2P_DEVICE)
++	.start_p2p_device = cfg80211_rtw_start_p2p_device,
++	.stop_p2p_device = cfg80211_rtw_stop_p2p_device,
++	#endif
++#endif /* CONFIG_P2P */
++
++#ifdef CONFIG_RTW_80211R
++	.update_ft_ies = cfg80211_rtw_update_ft_ies,
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
++	.mgmt_tx = cfg80211_rtw_mgmt_tx,
++	.mgmt_frame_register = cfg80211_rtw_mgmt_frame_register,
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++	.action = cfg80211_rtw_mgmt_tx,
++#endif
++
++#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
++	.tdls_mgmt = cfg80211_rtw_tdls_mgmt,
++	.tdls_oper = cfg80211_rtw_tdls_oper,
++#endif /* CONFIG_TDLS */
++
++#if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++	.sched_scan_start = cfg80211_rtw_sched_scan_start,
++	.sched_scan_stop = cfg80211_rtw_sched_scan_stop,
++	.suspend = cfg80211_rtw_suspend,
++	.resume = cfg80211_rtw_resume,
++#endif /* CONFIG_PNO_SUPPORT */
++#ifdef CONFIG_RFKILL_POLL
++	.rfkill_poll = cfg80211_rtw_rfkill_poll,
++#endif
++#if defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33))
++	.dump_survey = rtw_hostapd_acs_dump_survey,
++#endif
++#if (KERNEL_VERSION(4, 17, 0) <= LINUX_VERSION_CODE)
++	.external_auth = cfg80211_rtw_external_auth,
++#endif
++};
++
++struct wiphy *rtw_wiphy_alloc(_adapter *padapter, struct device *dev)
++{
++	struct wiphy *wiphy;
++	struct rtw_wiphy_data *wiphy_data;
++
++	/* wiphy */
++	wiphy = wiphy_new(&rtw_cfg80211_ops, sizeof(struct rtw_wiphy_data));
++	if (!wiphy) {
++		RTW_INFO("Couldn't allocate wiphy device\n");
++		goto exit;
++	}
++	set_wiphy_dev(wiphy, dev);
++
++	/* wiphy_data */
++	wiphy_data = rtw_wiphy_priv(wiphy);
++	wiphy_data->dvobj = adapter_to_dvobj(padapter);
++#ifndef RTW_SINGLE_WIPHY
++	wiphy_data->adapter = padapter;
++#endif
++	wiphy_data->txpwr_total_lmt_mbm = UNSPECIFIED_MBM;
++	wiphy_data->txpwr_total_target_mbm = UNSPECIFIED_MBM;
++
++	rtw_cfg80211_preinit_wiphy(padapter, wiphy);
++
++	RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy));
++
++exit:
++	return wiphy;
++}
++
++void rtw_wiphy_free(struct wiphy *wiphy)
++{
++	if (!wiphy)
++		return;
++
++	RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy));
++
++	if (wiphy->bands[NL80211_BAND_2GHZ]) {
++		rtw_spt_band_free(wiphy->bands[NL80211_BAND_2GHZ]);
++		wiphy->bands[NL80211_BAND_2GHZ] = NULL;
++	}
++	if (wiphy->bands[NL80211_BAND_5GHZ]) {
++		rtw_spt_band_free(wiphy->bands[NL80211_BAND_5GHZ]);
++		wiphy->bands[NL80211_BAND_5GHZ] = NULL;
++	}
++
++	wiphy_free(wiphy);
++}
++
++int rtw_wiphy_register(struct wiphy *wiphy)
++{
++	RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy));
++
++#if ( ((LINUX_VERSION_CODE < KERNEL_VERSION(5, 3, 0)) &&  \
++        LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) \
++     || defined(RTW_VENDOR_EXT_SUPPORT) )
++	rtw_cfgvendor_attach(wiphy);
++#endif
++
++	rtw_regd_init(wiphy);
++
++	return wiphy_register(wiphy);
++}
++
++void rtw_wiphy_unregister(struct wiphy *wiphy)
++{
++	RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy));
++
++#if ( ((LINUX_VERSION_CODE < KERNEL_VERSION(5, 3, 0)) &&  \
++        LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) \
++     || defined(RTW_VENDOR_EXT_SUPPORT) )
++	rtw_cfgvendor_detach(wiphy);
++#endif
++
++	#if defined(RTW_DEDICATED_P2P_DEVICE)
++	rtw_pd_iface_free(wiphy);
++	#endif
++
++	return wiphy_unregister(wiphy);
++}
++
++int rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy)
++{
++	int ret = 0;
++	struct net_device *pnetdev = padapter->pnetdev;
++	struct wireless_dev *wdev;
++	struct rtw_wdev_priv *pwdev_priv;
++
++	RTW_INFO("%s(padapter=%p)\n", __func__, padapter);
++
++	/*  wdev */
++	wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev));
++	if (!wdev) {
++		RTW_INFO("Couldn't allocate wireless device\n");
++		ret = -ENOMEM;
++		goto exit;
++	}
++	wdev->wiphy = wiphy;
++	wdev->netdev = pnetdev;
++	wdev->iftype = NL80211_IFTYPE_STATION;
++	padapter->rtw_wdev = wdev;
++	pnetdev->ieee80211_ptr = wdev;
++
++	/* init pwdev_priv */
++	pwdev_priv = adapter_wdev_data(padapter);
++	pwdev_priv->rtw_wdev = wdev;
++	pwdev_priv->pmon_ndev = NULL;
++	pwdev_priv->ifname_mon[0] = '\0';
++	pwdev_priv->padapter = padapter;
++	pwdev_priv->scan_request = NULL;
++	_rtw_spinlock_init(&pwdev_priv->scan_req_lock);
++	pwdev_priv->connect_req = NULL;
++	_rtw_spinlock_init(&pwdev_priv->connect_req_lock);
++
++	pwdev_priv->p2p_enabled = _FALSE;
++	pwdev_priv->probe_resp_ie_update_time = rtw_get_current_time();
++	pwdev_priv->provdisc_req_issued = _FALSE;
++	rtw_wdev_invit_info_init(&pwdev_priv->invit_info);
++	rtw_wdev_nego_info_init(&pwdev_priv->nego_info);
++
++	pwdev_priv->bandroid_scan = _FALSE;
++
++	if (padapter->registrypriv.power_mgnt != PS_MODE_ACTIVE)
++		pwdev_priv->power_mgmt = _TRUE;
++	else
++		pwdev_priv->power_mgmt = _FALSE;
++
++	_rtw_mutex_init(&pwdev_priv->roch_mutex);
++
++#ifdef CONFIG_CONCURRENT_MODE
++	ATOMIC_SET(&pwdev_priv->switch_ch_to, 1);
++#endif
++
++#ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
++        pwdev_priv->rssi_monitor_enable = 0;
++        pwdev_priv->rssi_monitor_max = 0;
++        pwdev_priv->rssi_monitor_min = 0;
++#endif
++
++
++exit:
++	return ret;
++}
++
++void rtw_wdev_free(struct wireless_dev *wdev)
++{
++	if (!wdev)
++		return;
++
++	RTW_INFO("%s(wdev=%p)\n", __func__, wdev);
++
++	if (wdev_to_ndev(wdev)) {
++		_adapter *adapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));
++		struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter);
++		_irqL irqL;
++
++		_rtw_spinlock_free(&wdev_priv->scan_req_lock);
++
++		_enter_critical_bh(&wdev_priv->connect_req_lock, &irqL);
++		rtw_wdev_free_connect_req(wdev_priv);
++		_exit_critical_bh(&wdev_priv->connect_req_lock, &irqL);
++		_rtw_spinlock_free(&wdev_priv->connect_req_lock);
++
++		_rtw_mutex_free(&wdev_priv->roch_mutex);
++	}
++
++	rtw_mfree((u8 *)wdev, sizeof(struct wireless_dev));
++}
++
++void rtw_wdev_unregister(struct wireless_dev *wdev)
++{
++	struct net_device *ndev;
++	_adapter *adapter;
++	struct rtw_wdev_priv *pwdev_priv;
++
++	if (!wdev)
++		return;
++
++	RTW_INFO("%s(wdev=%p)\n", __func__, wdev);
++
++	ndev = wdev_to_ndev(wdev);
++	if (!ndev)
++		return;
++
++	adapter = (_adapter *)rtw_netdev_priv(ndev);
++	pwdev_priv = adapter_wdev_data(adapter);
++
++	rtw_cfg80211_indicate_scan_done(adapter, _TRUE);
++
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) || defined(COMPAT_KERNEL_RELEASE)
++	if (wdev->current_bss) {
++		RTW_INFO(FUNC_ADPT_FMT" clear current_bss by cfg80211_disconnected\n", FUNC_ADPT_ARG(adapter));
++		rtw_cfg80211_indicate_disconnect(adapter, 0, 1);
++	}
++	#endif
++
++	if (pwdev_priv->pmon_ndev) {
++		RTW_INFO("%s, unregister monitor interface\n", __func__);
++		unregister_netdev(pwdev_priv->pmon_ndev);
++	}
++}
++
++int rtw_cfg80211_ndev_res_alloc(_adapter *adapter)
++{
++	int ret = _FAIL;
++
++#if !defined(RTW_SINGLE_WIPHY)
++	struct wiphy *wiphy;
++	struct device *dev = dvobj_to_dev(adapter_to_dvobj(adapter));
++
++	wiphy = rtw_wiphy_alloc(adapter, dev);
++	if (wiphy == NULL)
++		goto exit;
++
++	adapter->wiphy = wiphy;
++#endif
++
++	if (rtw_wdev_alloc(adapter, adapter_to_wiphy(adapter)) == 0)
++		ret = _SUCCESS;
++
++#if !defined(RTW_SINGLE_WIPHY)
++	if (ret != _SUCCESS) {
++		rtw_wiphy_free(wiphy);
++		adapter->wiphy = NULL;
++	}
++
++exit:
++#endif
++
++	return ret;
++}
++
++void rtw_cfg80211_ndev_res_free(_adapter *adapter)
++{
++	rtw_wdev_free(adapter->rtw_wdev);
++	adapter->rtw_wdev = NULL;
++#if !defined(RTW_SINGLE_WIPHY)
++	rtw_wiphy_free(adapter_to_wiphy(adapter));
++	adapter->wiphy = NULL;
++#endif
++}
++
++
++int rtw_cfg80211_ndev_res_register(_adapter *adapter)
++{
++#if !defined(RTW_SINGLE_WIPHY)
++	int ret = _FAIL;
++
++	if (rtw_wiphy_register(adapter_to_wiphy(adapter)) < 0) {
++		RTW_INFO("%s rtw_wiphy_register fail for if%d\n", __func__, (adapter->iface_id + 1));
++		goto exit;
++	}
++
++	#ifdef CONFIG_RFKILL_POLL
++	rtw_cfg80211_init_rfkill(adapter_to_wiphy(adapter));
++	#endif
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++#else
++	return _SUCCESS;
++#endif
++}
++
++void rtw_cfg80211_ndev_res_unregister(_adapter *adapter)
++{
++	rtw_wdev_unregister(adapter->rtw_wdev);
++}
++
++int rtw_cfg80211_dev_res_alloc(struct dvobj_priv *dvobj)
++{
++	int ret = _FAIL;
++
++#if defined(RTW_SINGLE_WIPHY)
++	struct wiphy *wiphy;
++	struct device *dev = dvobj_to_dev(dvobj);
++
++	wiphy = rtw_wiphy_alloc(dvobj_get_primary_adapter(dvobj), dev);
++	if (wiphy == NULL)
++		return ret;
++
++	dvobj->wiphy = wiphy;
++#endif
++
++	ret = _SUCCESS;
++	return ret;
++}
++
++void rtw_cfg80211_dev_res_free(struct dvobj_priv *dvobj)
++{
++#if defined(RTW_SINGLE_WIPHY)
++	rtw_wiphy_free(dvobj_to_wiphy(dvobj));
++	dvobj->wiphy = NULL;
++#endif
++}
++
++int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj)
++{
++	int ret = _FAIL;
++
++#if defined(RTW_SINGLE_WIPHY)
++	if (rtw_wiphy_register(dvobj_to_wiphy(dvobj)) != 0)
++		return ret;
++
++#ifdef CONFIG_RFKILL_POLL
++	rtw_cfg80211_init_rfkill(dvobj_to_wiphy(dvobj));
++#endif
++#endif
++
++	ret = _SUCCESS;
++
++	return ret;
++}
++
++void rtw_cfg80211_dev_res_unregister(struct dvobj_priv *dvobj)
++{
++#if defined(RTW_SINGLE_WIPHY)
++#ifdef CONFIG_RFKILL_POLL
++	rtw_cfg80211_deinit_rfkill(dvobj_to_wiphy(dvobj));
++#endif
++	rtw_wiphy_unregister(dvobj_to_wiphy(dvobj));
++#endif
++}
++
++s16 rtw_cfg80211_dev_get_total_txpwr_lmt_mbm(struct dvobj_priv *dvobj)
++{
++	struct rtw_wiphy_data *wiphy_data;
++	s16 mbm = UNSPECIFIED_MBM;
++
++	/* TODO: input radio index to choose corresponding wiphy(s) */
++
++#if defined(RTW_SINGLE_WIPHY)
++	wiphy_data = rtw_wiphy_priv(dvobj_to_wiphy(dvobj));
++	mbm = wiphy_data->txpwr_total_lmt_mbm;
++#else
++	struct wiphy *wiphy;
++	int i;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		if (!dvobj->padapters[i])
++			continue;
++		wiphy = dvobj->padapters[i]->wiphy;
++		if (!wiphy)
++			continue;
++		wiphy_data = rtw_wiphy_priv(wiphy);
++		if (wiphy_data->txpwr_total_lmt_mbm == UNSPECIFIED_MBM)
++			continue;
++		if (mbm > wiphy_data->txpwr_total_lmt_mbm)
++			mbm = wiphy_data->txpwr_total_lmt_mbm;
++	}
++#endif
++
++	return mbm;
++}
++
++s16 rtw_cfg80211_dev_get_total_txpwr_target_mbm(struct dvobj_priv *dvobj)
++{
++	struct rtw_wiphy_data *wiphy_data;
++	s16 mbm = UNSPECIFIED_MBM;
++
++	/* TODO: input radio index to choose corresponding wiphy(s) */
++
++#if defined(RTW_SINGLE_WIPHY)
++	wiphy_data = rtw_wiphy_priv(dvobj_to_wiphy(dvobj));
++	mbm = wiphy_data->txpwr_total_target_mbm;
++#else
++	struct wiphy *wiphy;
++	int i;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		if (!dvobj->padapters[i])
++			continue;
++		wiphy = dvobj->padapters[i]->wiphy;
++		if (!wiphy)
++			continue;
++		wiphy_data = rtw_wiphy_priv(wiphy);
++		if (wiphy_data->txpwr_total_target_mbm == UNSPECIFIED_MBM)
++			continue;
++		if (mbm > wiphy_data->txpwr_total_target_mbm)
++			mbm = wiphy_data->txpwr_total_target_mbm;
++	}
++#endif
++
++	return mbm;
++}
++#endif /* CONFIG_IOCTL_CFG80211 */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/ioctl_cfg80211.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/ioctl_cfg80211.h
+new file mode 100644
+index 000000000..4457e16c2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/ioctl_cfg80211.h
+@@ -0,0 +1,442 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __IOCTL_CFG80211_H__
++#define __IOCTL_CFG80211_H__
++
++#define RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT		BIT0
++#define RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT	BIT1
++
++#ifndef RTW_CFG80211_BLOCK_STA_DISCON_EVENT
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0))
++#define RTW_CFG80211_BLOCK_STA_DISCON_EVENT (RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT)
++#else
++#define RTW_CFG80211_BLOCK_STA_DISCON_EVENT (RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT | RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)
++#endif
++#endif
++
++#if defined(RTW_USE_CFG80211_STA_EVENT)
++	#undef CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
++#endif
++
++#ifndef RTW_P2P_GROUP_INTERFACE
++	#define RTW_P2P_GROUP_INTERFACE 0
++#endif
++
++/*
++* (RTW_P2P_GROUP_INTERFACE, RTW_DEDICATED_P2P_DEVICE)
++* (0, 0): wlan0 + p2p0(PD+PG)
++* (1, 0): wlan0(with PD) + dynamic PGs
++* (1, 1): wlan0 (with dynamic PD wdev) + dynamic PGs
++*/
++
++#if RTW_P2P_GROUP_INTERFACE
++	#ifndef CONFIG_RTW_DYNAMIC_NDEV
++		#define CONFIG_RTW_DYNAMIC_NDEV
++	#endif
++	#ifndef RTW_SINGLE_WIPHY
++		#define RTW_SINGLE_WIPHY
++	#endif
++	#ifndef CONFIG_RADIO_WORK
++		#define CONFIG_RADIO_WORK
++	#endif
++	#ifndef RTW_DEDICATED_P2P_DEVICE
++		#define RTW_DEDICATED_P2P_DEVICE
++	#endif
++#endif
++
++#ifndef CONFIG_RADIO_WORK
++#define RTW_ROCH_DURATION_ENLARGE
++#define RTW_ROCH_BACK_OP
++#endif
++
++#if !defined(CONFIG_P2P) && RTW_P2P_GROUP_INTERFACE
++	#error "RTW_P2P_GROUP_INTERFACE can't be enabled when CONFIG_P2P is disabled\n"
++#endif
++
++#if !RTW_P2P_GROUP_INTERFACE && defined(RTW_DEDICATED_P2P_DEVICE)
++	#error "RTW_DEDICATED_P2P_DEVICE can't be enabled when RTW_P2P_GROUP_INTERFACE is disabled\n"
++#endif
++
++#if defined(RTW_DEDICATED_P2P_DEVICE) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0))
++	#error "RTW_DEDICATED_P2P_DEVICE can't be enabled when kernel < 3.7.0\n"
++#endif
++
++#ifdef CONFIG_RTW_MESH
++	#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))
++		#error "CONFIG_RTW_MESH can't be enabled when kernel < 3.10.0\n"
++	#endif
++#endif
++
++struct rtw_wdev_invit_info {
++	u8 state; /* 0: req, 1:rep */
++	u8 peer_mac[ETH_ALEN];
++	u8 group_bssid[ETH_ALEN];
++	u8 active;
++	u8 token;
++	u8 flags;
++	u8 status;
++	u8 req_op_ch;
++	u8 rsp_op_ch;
++};
++
++#define rtw_wdev_invit_info_init(invit_info) \
++	do { \
++		(invit_info)->state = 0xff; \
++		_rtw_memset((invit_info)->peer_mac, 0, ETH_ALEN); \
++		_rtw_memset((invit_info)->group_bssid, 0, ETH_ALEN); \
++		(invit_info)->active = 0xff; \
++		(invit_info)->token = 0; \
++		(invit_info)->flags = 0x00; \
++		(invit_info)->status = 0xff; \
++		(invit_info)->req_op_ch = 0; \
++		(invit_info)->rsp_op_ch = 0; \
++	} while (0)
++
++struct rtw_wdev_nego_info {
++	u8 state; /* 0: req, 1:rep, 2:conf */
++	u8 iface_addr[ETH_ALEN];
++	u8 peer_mac[ETH_ALEN];
++	u8 peer_iface_addr[ETH_ALEN];
++	u8 active;
++	u8 token;
++	u8 status;
++	u8 req_intent;
++	u8 req_op_ch;
++	u8 req_listen_ch;
++	u8 rsp_intent;
++	u8 rsp_op_ch;
++	u8 conf_op_ch;
++};
++
++#define rtw_wdev_nego_info_init(nego_info) \
++	do { \
++		(nego_info)->state = 0xff; \
++		_rtw_memset((nego_info)->iface_addr, 0, ETH_ALEN); \
++		_rtw_memset((nego_info)->peer_mac, 0, ETH_ALEN); \
++		_rtw_memset((nego_info)->peer_iface_addr, 0, ETH_ALEN); \
++		(nego_info)->active = 0xff; \
++		(nego_info)->token = 0; \
++		(nego_info)->status = 0xff; \
++		(nego_info)->req_intent = 0xff; \
++		(nego_info)->req_op_ch = 0; \
++		(nego_info)->req_listen_ch = 0; \
++		(nego_info)->rsp_intent = 0xff; \
++		(nego_info)->rsp_op_ch = 0; \
++		(nego_info)->conf_op_ch = 0; \
++	} while (0)
++
++struct rtw_wdev_priv {
++	struct wireless_dev *rtw_wdev;
++
++	_adapter *padapter;
++
++	#if RTW_CFG80211_BLOCK_STA_DISCON_EVENT
++	u8 not_indic_disco;
++	#endif
++
++	struct cfg80211_scan_request *scan_request;
++	_lock scan_req_lock;
++
++	struct cfg80211_connect_params *connect_req;
++	_lock connect_req_lock;
++
++	struct net_device *pmon_ndev;/* for monitor interface */
++	char ifname_mon[IFNAMSIZ + 1]; /* interface name for monitor interface */
++
++	u8 p2p_enabled;
++	systime probe_resp_ie_update_time;
++
++	u8 provdisc_req_issued;
++
++	struct rtw_wdev_invit_info invit_info;
++	struct rtw_wdev_nego_info nego_info;
++
++	u8 bandroid_scan;
++	bool block;
++	bool block_scan;
++	bool power_mgmt;
++
++	/* report mgmt_frame registered */
++	u16 report_mgmt;
++
++	u8 is_mgmt_tx;
++	u16 mgmt_tx_cookie;
++
++	_mutex roch_mutex;
++
++#ifdef CONFIG_CONCURRENT_MODE
++	ATOMIC_T switch_ch_to;
++#endif
++
++#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++	u8 pno_mac_addr[ETH_ALEN];
++	u16 pno_scan_seq_num;
++#endif
++
++#ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
++        s8 rssi_monitor_max;
++        s8 rssi_monitor_min;
++        u8 rssi_monitor_enable;
++#endif
++
++};
++
++enum external_auth_action {
++	EXTERNAL_AUTH_START,
++	EXTERNAL_AUTH_ABORT,
++};
++
++struct rtw_external_auth_params {
++	enum external_auth_action action;
++	u8 bssid[ETH_ALEN]__aligned(2);
++	struct cfg80211_ssid ssid;
++	unsigned int key_mgmt_suite;
++	u16 status;
++	u8 pmkid[PMKID_LEN];
++};
++
++bool rtw_cfg80211_is_connect_requested(_adapter *adapter);
++
++#if RTW_CFG80211_BLOCK_STA_DISCON_EVENT
++#define rtw_wdev_not_indic_disco(rtw_wdev_data) ((rtw_wdev_data)->not_indic_disco)
++#define rtw_wdev_set_not_indic_disco(rtw_wdev_data, val) do { (rtw_wdev_data)->not_indic_disco = (val); } while (0)
++#else
++#define rtw_wdev_not_indic_disco(rtw_wdev_data) 0
++#define rtw_wdev_set_not_indic_disco(rtw_wdev_data, val) do {} while (0)
++#endif
++
++#define rtw_wdev_free_connect_req(rtw_wdev_data) \
++	do { \
++		if ((rtw_wdev_data)->connect_req) { \
++			rtw_mfree((u8 *)(rtw_wdev_data)->connect_req, sizeof(*(rtw_wdev_data)->connect_req)); \
++			(rtw_wdev_data)->connect_req = NULL; \
++		} \
++	} while (0)
++
++#define wdev_to_ndev(w) ((w)->netdev)
++#define wdev_to_wiphy(w) ((w)->wiphy)
++#define ndev_to_wdev(n) ((n)->ieee80211_ptr)
++
++struct rtw_wiphy_data {
++	struct dvobj_priv *dvobj;
++
++#ifndef RTW_SINGLE_WIPHY
++	_adapter *adapter;
++#endif
++
++#if defined(RTW_DEDICATED_P2P_DEVICE)
++	struct wireless_dev *pd_wdev; /* P2P device wdev */
++#endif
++
++	s16 txpwr_total_lmt_mbm;
++	s16 txpwr_total_target_mbm;
++};
++
++#define rtw_wiphy_priv(wiphy) ((struct rtw_wiphy_data *)wiphy_priv(wiphy))
++#define wiphy_to_dvobj(wiphy) (((struct rtw_wiphy_data *)wiphy_priv(wiphy))->dvobj)
++#ifdef RTW_SINGLE_WIPHY
++#define wiphy_to_adapter(wiphy) (dvobj_get_primary_adapter(wiphy_to_dvobj(wiphy)))
++#else
++#define wiphy_to_adapter(wiphy) (((struct rtw_wiphy_data *)wiphy_priv(wiphy))->adapter)
++#endif
++
++#if defined(RTW_DEDICATED_P2P_DEVICE)
++#define wiphy_to_pd_wdev(wiphy) (rtw_wiphy_priv(wiphy)->pd_wdev)
++#else
++#define wiphy_to_pd_wdev(wiphy) NULL
++#endif
++
++#define WIPHY_FMT "%s"
++#define WIPHY_ARG(wiphy) wiphy_name(wiphy)
++#define FUNC_WIPHY_FMT "%s("WIPHY_FMT")"
++#define FUNC_WIPHY_ARG(wiphy) __func__, WIPHY_ARG(wiphy)
++
++#define SET_CFG80211_REPORT_MGMT(w, t, v) (w->report_mgmt |= BIT(t >> 4))
++#define CLR_CFG80211_REPORT_MGMT(w, t, v) (w->report_mgmt &= (~BIT(t >> 4)))
++#define GET_CFG80211_REPORT_MGMT(w, t) ((w->report_mgmt & BIT(t >> 4)) > 0)
++
++struct wiphy *rtw_wiphy_alloc(_adapter *padapter, struct device *dev);
++void rtw_wiphy_free(struct wiphy *wiphy);
++int rtw_wiphy_register(struct wiphy *wiphy);
++void rtw_wiphy_unregister(struct wiphy *wiphy);
++
++int rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy);
++void rtw_wdev_free(struct wireless_dev *wdev);
++void rtw_wdev_unregister(struct wireless_dev *wdev);
++
++int rtw_cfg80211_ndev_res_alloc(_adapter *adapter);
++void rtw_cfg80211_ndev_res_free(_adapter *adapter);
++int rtw_cfg80211_ndev_res_register(_adapter *adapter);
++void rtw_cfg80211_ndev_res_unregister(_adapter *adapter);
++
++int rtw_cfg80211_dev_res_alloc(struct dvobj_priv *dvobj);
++void rtw_cfg80211_dev_res_free(struct dvobj_priv *dvobj);
++int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj);
++void rtw_cfg80211_dev_res_unregister(struct dvobj_priv *dvobj);
++s16 rtw_cfg80211_dev_get_total_txpwr_lmt_mbm(struct dvobj_priv *dvobj);
++s16 rtw_cfg80211_dev_get_total_txpwr_target_mbm(struct dvobj_priv *dvobj);
++
++void rtw_cfg80211_init_wdev_data(_adapter *padapter);
++void rtw_cfg80211_init_wiphy(_adapter *padapter);
++
++void rtw_cfg80211_unlink_bss(_adapter *padapter, struct wlan_network *pnetwork);
++void rtw_cfg80211_surveydone_event_callback(_adapter *padapter);
++struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork);
++int rtw_cfg80211_check_bss(_adapter *padapter);
++void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter);
++void rtw_cfg80211_indicate_connect(_adapter *padapter);
++void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated);
++void rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted);
++u32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms);
++
++#ifdef CONFIG_CONCURRENT_MODE
++u8 rtw_cfg80211_scan_via_buddy(_adapter *padapter, struct cfg80211_scan_request *request);
++void rtw_cfg80211_indicate_scan_done_for_buddy(_adapter *padapter, bool bscan_aborted);
++#endif
++
++#ifdef CONFIG_AP_MODE
++void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
++void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, const u8 *da, unsigned short reason);
++#endif /* CONFIG_AP_MODE */
++
++#ifdef CONFIG_P2P
++void rtw_cfg80211_set_is_roch(_adapter *adapter, bool val);
++bool rtw_cfg80211_get_is_roch(_adapter *adapter);
++bool rtw_cfg80211_is_ro_ch_once(_adapter *adapter);
++void rtw_cfg80211_set_last_ro_ch_time(_adapter *adapter);
++s32 rtw_cfg80211_get_last_ro_ch_passing_ms(_adapter *adapter);
++
++int rtw_cfg80211_iface_has_p2p_group_cap(_adapter *adapter);
++int rtw_cfg80211_is_p2p_scan(_adapter *adapter);
++#if defined(RTW_DEDICATED_P2P_DEVICE)
++int rtw_cfg80211_redirect_pd_wdev(struct wiphy *wiphy, u8 *ra, struct wireless_dev **wdev);
++int rtw_cfg80211_is_scan_by_pd_wdev(_adapter *adapter);
++int rtw_pd_iface_alloc(struct wiphy *wiphy, const char *name, struct wireless_dev **pd_wdev);
++void rtw_pd_iface_free(struct wiphy *wiphy);
++#endif
++#endif /* CONFIG_P2P */
++
++void rtw_cfg80211_set_is_mgmt_tx(_adapter *adapter, u8 val);
++u8 rtw_cfg80211_get_is_mgmt_tx(_adapter *adapter);
++u8 rtw_mgnt_tx_handler(_adapter *adapter, u8 *buf);
++
++void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len);
++
++void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, union recv_frame *rframe);
++void rtw_cfg80211_rx_action_p2p(_adapter *padapter, union recv_frame *rframe);
++void rtw_cfg80211_rx_action(_adapter *adapter, union recv_frame *rframe, const char *msg);
++void rtw_cfg80211_rx_mframe(_adapter *adapter, union recv_frame *rframe, const char *msg);
++void rtw_cfg80211_rx_probe_request(_adapter *padapter, union recv_frame *rframe);
++
++void rtw_cfg80211_external_auth_request(_adapter *padapter, union recv_frame *rframe);
++void rtw_cfg80211_external_auth_status(struct wiphy *wiphy, struct net_device *dev,
++	struct rtw_external_auth_params *params);
++
++int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type);
++
++bool rtw_cfg80211_pwr_mgmt(_adapter *adapter);
++#ifdef CONFIG_RTW_80211K
++void rtw_cfg80211_rx_rrm_action(_adapter *adapter, union recv_frame *rframe);
++#endif
++
++#ifdef CONFIG_RFKILL_POLL
++void rtw_cfg80211_init_rfkill(struct wiphy *wiphy);
++void rtw_cfg80211_deinit_rfkill(struct wiphy *wiphy);
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0))  && !defined(COMPAT_KERNEL_RELEASE)
++#define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev_to_ndev(wdev), freq, buf, len, gfp)
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++#define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev_to_ndev(wdev), freq, sig_dbm, buf, len, gfp)
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 12, 0))
++#define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp)
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3 , 18 , 0))
++#define rtw_cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , gfp) cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , 0 , gfp)
++#else
++#define rtw_cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , gfp) cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , 0)
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0))  && !defined(COMPAT_KERNEL_RELEASE)
++#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, buf, len)
++#else
++#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, bss, buf, len)
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++#define rtw_cfg80211_mgmt_tx_status(wdev, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status(wdev_to_ndev(wdev), cookie, buf, len, ack, gfp)
++#else
++#define rtw_cfg80211_mgmt_tx_status(wdev, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status(wdev, cookie, buf, len, ack, gfp)
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
++#define rtw_cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp)  cfg80211_ready_on_channel(wdev_to_ndev(wdev), cookie, chan, channel_type, duration, gfp)
++#define rtw_cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired(wdev_to_ndev(wdev), cookie, chan, chan_type, gfp)
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
++#define rtw_cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp)  cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp)
++#define rtw_cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp)
++#else
++#define rtw_cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp)  cfg80211_ready_on_channel(wdev, cookie, chan, duration, gfp)
++#define rtw_cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired(wdev, cookie, chan, gfp)
++#endif
++
++#define rtw_cfg80211_connect_result(wdev, bssid, req_ie, req_ie_len, resp_ie, resp_ie_len, status, gfp) cfg80211_connect_result(wdev_to_ndev(wdev), bssid, req_ie, req_ie_len, resp_ie, resp_ie_len, status, gfp)
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0))
++#define rtw_cfg80211_disconnected(wdev, reason, ie, ie_len, locally_generated, gfp) cfg80211_disconnected(wdev_to_ndev(wdev), reason, ie, ie_len, gfp)
++#else
++#define rtw_cfg80211_disconnected(wdev, reason, ie, ie_len, locally_generated, gfp) cfg80211_disconnected(wdev_to_ndev(wdev), reason, ie, ie_len, locally_generated, gfp)
++#endif
++
++#ifdef CONFIG_RTW_80211R
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
++#define rtw_cfg80211_ft_event(adapter, parm)  cfg80211_ft_event((adapter)->pnetdev, parm)
++#else
++	#error "Cannot support FT for KERNEL_VERSION < 3.10\n"
++#endif
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0))
++#define rtw_cfg80211_notify_new_peer_candidate(wdev, addr, ie, ie_len, sig_dbm, gfp) cfg80211_notify_new_peer_candidate(wdev_to_ndev(wdev), addr, ie, ie_len, sig_dbm, gfp)
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
++#define rtw_cfg80211_notify_new_peer_candidate(wdev, addr, ie, ie_len, sig_dbm, gfp) cfg80211_notify_new_peer_candidate(wdev_to_ndev(wdev), addr, ie, ie_len, gfp)
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
++u8 rtw_cfg80211_ch_switch_notify(_adapter *adapter, u8 ch, u8 bw, u8 offset, u8 ht, bool started);
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0))
++#define NL80211_BAND_2GHZ IEEE80211_BAND_2GHZ
++#define NL80211_BAND_5GHZ IEEE80211_BAND_5GHZ
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
++#define NL80211_BAND_60GHZ IEEE80211_BAND_60GHZ
++#endif
++#define NUM_NL80211_BANDS IEEE80211_NUM_BANDS
++#endif
++
++#define rtw_band_to_nl80211_band(band) \
++	(band == BAND_ON_2_4G) ? NL80211_BAND_2GHZ : \
++	(band == BAND_ON_5G) ? NL80211_BAND_5GHZ : NUM_NL80211_BANDS
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36))
++#define NL80211_TX_POWER_AUTOMATIC	TX_POWER_AUTOMATIC
++#define NL80211_TX_POWER_LIMITED	TX_POWER_LIMITED
++#define NL80211_TX_POWER_FIXED		TX_POWER_FIXED
++#endif
++
++#include "wifi_regd.h"
++#include "rtw_cfgvendor.h"
++
++#endif /* __IOCTL_CFG80211_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/ioctl_linux.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/ioctl_linux.c
+new file mode 100644
+index 000000000..9cf092a1a
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/ioctl_linux.c
+@@ -0,0 +1,12920 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _IOCTL_LINUX_C_
++
++#include <drv_types.h>
++#include <rtw_mp.h>
++#include "../../hal/phydm/phydm_precomp.h"
++#ifdef RTW_HALMAC
++#include "../../hal/hal_halmac.h"
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27))
++#define  iwe_stream_add_event(a, b, c, d, e)  iwe_stream_add_event(b, c, d, e)
++#define  iwe_stream_add_point(a, b, c, d, e)  iwe_stream_add_point(b, c, d, e)
++#endif
++
++#ifdef CONFIG_80211N_HT
++extern int rtw_ht_enable;
++#endif
++
++
++#define RTL_IOCTL_WPA_SUPPLICANT	(SIOCIWFIRSTPRIV+30)
++
++#define SCAN_ITEM_SIZE 768
++#define MAX_CUSTOM_LEN 64
++#define RATE_COUNT 4
++#define MAX_SCAN_BUFFER_LEN 65535
++
++#ifdef CONFIG_GLOBAL_UI_PID
++extern int ui_pid[3];
++#endif
++
++/* combo scan */
++#define WEXT_CSCAN_AMOUNT 9
++#define WEXT_CSCAN_BUF_LEN		360
++#define WEXT_CSCAN_HEADER		"CSCAN S\x01\x00\x00S\x00"
++#define WEXT_CSCAN_HEADER_SIZE		12
++#define WEXT_CSCAN_SSID_SECTION		'S'
++#define WEXT_CSCAN_CHANNEL_SECTION	'C'
++#define WEXT_CSCAN_NPROBE_SECTION	'N'
++#define WEXT_CSCAN_ACTV_DWELL_SECTION	'A'
++#define WEXT_CSCAN_PASV_DWELL_SECTION	'P'
++#define WEXT_CSCAN_HOME_DWELL_SECTION	'H'
++#define WEXT_CSCAN_TYPE_SECTION		'T'
++
++
++extern u8 key_2char2num(u8 hch, u8 lch);
++extern u8 str_2char2num(u8 hch, u8 lch);
++extern void macstr2num(u8 *dst, u8 *src);
++extern u8 convert_ip_addr(u8 hch, u8 mch, u8 lch);
++
++u32 rtw_rates[] = {1000000, 2000000, 5500000, 11000000,
++	6000000, 9000000, 12000000, 18000000, 24000000, 36000000, 48000000, 54000000};
++
++/**
++ * hwaddr_aton - Convert ASCII string to MAC address
++ * @txt: MAC address as a string (e.g., "00:11:22:33:44:55")
++ * @addr: Buffer for the MAC address (ETH_ALEN = 6 bytes)
++ * Returns: 0 on success, -1 on failure (e.g., string not a MAC address)
++ */
++static int hwaddr_aton_i(const char *txt, u8 *addr)
++{
++	int i;
++
++	for (i = 0; i < 6; i++) {
++		int a, b;
++
++		a = hex2num_i(*txt++);
++		if (a < 0)
++			return -1;
++		b = hex2num_i(*txt++);
++		if (b < 0)
++			return -1;
++		*addr++ = (a << 4) | b;
++		if (i < 5 && *txt++ != ':')
++			return -1;
++	}
++
++	return 0;
++}
++#ifdef CONFIG_RTW_ANDROID
++static void indicate_wx_custom_event(_adapter *padapter, char *msg)
++{
++	u8 *buff;
++	union iwreq_data wrqu;
++
++	if (strlen(msg) > IW_CUSTOM_MAX) {
++		RTW_INFO("%s strlen(msg):%zu > IW_CUSTOM_MAX:%u\n", __FUNCTION__ , strlen(msg), IW_CUSTOM_MAX);
++		return;
++	}
++
++	buff = rtw_zmalloc(IW_CUSTOM_MAX + 1);
++	if (!buff)
++		return;
++
++	_rtw_memcpy(buff, msg, strlen(msg));
++
++	_rtw_memset(&wrqu, 0, sizeof(wrqu));
++	wrqu.data.length = strlen(msg);
++
++	RTW_INFO("%s %s\n", __FUNCTION__, buff);
++#ifndef CONFIG_IOCTL_CFG80211
++	wireless_send_event(padapter->pnetdev, IWEVCUSTOM, &wrqu, buff);
++#endif
++
++	rtw_mfree(buff, IW_CUSTOM_MAX + 1);
++
++}
++#endif
++
++#if 0
++static void request_wps_pbc_event(_adapter *padapter)
++{
++	u8 *buff, *p;
++	union iwreq_data wrqu;
++
++
++	buff = rtw_malloc(IW_CUSTOM_MAX);
++	if (!buff)
++		return;
++
++	_rtw_memset(buff, 0, IW_CUSTOM_MAX);
++
++	p = buff;
++
++	p += sprintf(p, "WPS_PBC_START.request=TRUE");
++
++	_rtw_memset(&wrqu, 0, sizeof(wrqu));
++
++	wrqu.data.length = p - buff;
++
++	wrqu.data.length = (wrqu.data.length < IW_CUSTOM_MAX) ? wrqu.data.length : IW_CUSTOM_MAX;
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++#ifndef CONFIG_IOCTL_CFG80211
++	wireless_send_event(padapter->pnetdev, IWEVCUSTOM, &wrqu, buff);
++#endif
++
++	if (buff)
++		rtw_mfree(buff, IW_CUSTOM_MAX);
++
++}
++#endif
++
++#ifdef CONFIG_SUPPORT_HW_WPS_PBC
++void rtw_request_wps_pbc_event(_adapter *padapter)
++{
++#ifdef RTK_DMP_PLATFORM
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12))
++	kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_NET_PBC);
++#else
++	kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_NET_PBC);
++#endif
++#else
++
++	if (padapter->pid[0] == 0) {
++		/*	0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver. */
++		return;
++	}
++
++	rtw_signal_process(padapter->pid[0], SIGUSR1);
++
++#endif
++
++	rtw_led_control(padapter, LED_CTL_START_WPS_BOTTON);
++}
++#endif/* #ifdef CONFIG_SUPPORT_HW_WPS_PBC */
++
++void indicate_wx_scan_complete_event(_adapter *padapter)
++{
++	union iwreq_data wrqu;
++
++	_rtw_memset(&wrqu, 0, sizeof(union iwreq_data));
++
++	/* RTW_INFO("+rtw_indicate_wx_scan_complete_event\n"); */
++#ifndef CONFIG_IOCTL_CFG80211
++	wireless_send_event(padapter->pnetdev, SIOCGIWSCAN, &wrqu, NULL);
++#endif
++}
++
++
++void rtw_indicate_wx_assoc_event(_adapter *padapter)
++{
++	union iwreq_data wrqu;
++	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
++
++	_rtw_memset(&wrqu, 0, sizeof(union iwreq_data));
++
++	wrqu.ap_addr.sa_family = ARPHRD_ETHER;
++
++	if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)
++		_rtw_memcpy(wrqu.ap_addr.sa_data, pnetwork->MacAddress, ETH_ALEN);
++	else
++		_rtw_memcpy(wrqu.ap_addr.sa_data, pmlmepriv->cur_network.network.MacAddress, ETH_ALEN);
++
++	RTW_PRINT("assoc success\n");
++#ifndef CONFIG_IOCTL_CFG80211
++	wireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL);
++#endif
++}
++
++void rtw_indicate_wx_disassoc_event(_adapter *padapter)
++{
++	union iwreq_data wrqu;
++
++	_rtw_memset(&wrqu, 0, sizeof(union iwreq_data));
++
++	wrqu.ap_addr.sa_family = ARPHRD_ETHER;
++	_rtw_memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN);
++
++#ifndef CONFIG_IOCTL_CFG80211
++	RTW_PRINT("indicate disassoc\n");
++	wireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL);
++#endif
++}
++
++/*
++uint	rtw_is_cckrates_included(u8 *rate)
++{
++		u32	i = 0;
++
++		while(rate[i]!=0)
++		{
++			if  (  (((rate[i]) & 0x7f) == 2)	|| (((rate[i]) & 0x7f) == 4) ||
++			(((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) == 22) )
++			return _TRUE;
++			i++;
++		}
++
++		return _FALSE;
++}
++
++uint	rtw_is_cckratesonly_included(u8 *rate)
++{
++	u32 i = 0;
++
++	while(rate[i]!=0)
++	{
++			if  (  (((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) &&
++				(((rate[i]) & 0x7f) != 11)  && (((rate[i]) & 0x7f) != 22) )
++			return _FALSE;
++			i++;
++	}
++
++	return _TRUE;
++}
++*/
++
++static int search_p2p_wfd_ie(_adapter *padapter,
++		struct iw_request_info *info, struct wlan_network *pnetwork,
++		char *start, char *stop)
++{
++#ifdef CONFIG_P2P
++	struct wifidirect_info	*pwdinfo = &padapter->wdinfo;
++#ifdef CONFIG_WFD
++	if (SCAN_RESULT_ALL == pwdinfo->wfd_info->scan_result_type) {
++
++	} else if ((SCAN_RESULT_P2P_ONLY == pwdinfo->wfd_info->scan_result_type) ||
++		(SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type))
++#endif /* CONFIG_WFD */
++	{
++		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
++			u32	blnGotP2PIE = _FALSE;
++
++			/*	User is doing the P2P device discovery */
++			/*	The prefix of SSID should be "DIRECT-" and the IE should contains the P2P IE. */
++			/*	If not, the driver should ignore this AP and go to the next AP. */
++
++			/*	Verifying the SSID */
++			if (_rtw_memcmp(pnetwork->network.Ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN)) {
++				u32	p2pielen = 0;
++
++				/*	Verifying the P2P IE */
++				if (rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen))
++					blnGotP2PIE = _TRUE;
++			}
++
++			if (blnGotP2PIE == _FALSE)
++				return _FALSE;
++
++		}
++	}
++
++#ifdef CONFIG_WFD
++	if (SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type) {
++		u32	blnGotWFD = _FALSE;
++		u8 *wfd_ie;
++		uint wfd_ielen = 0;
++
++		wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen);
++		if (wfd_ie) {
++			u8 *wfd_devinfo;
++			uint wfd_devlen;
++
++			wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen);
++			if (wfd_devinfo) {
++				if (pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_PSINK) {
++					/*	the first two bits will indicate the WFD device type */
++					if ((wfd_devinfo[1] & 0x03) == WFD_DEVINFO_SOURCE) {
++						/*	If this device is Miracast PSink device, the scan reuslt should just provide the Miracast source. */
++						blnGotWFD = _TRUE;
++					}
++				} else if (pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_SOURCE) {
++					/*	the first two bits will indicate the WFD device type */
++					if ((wfd_devinfo[1] & 0x03) == WFD_DEVINFO_PSINK) {
++						/*	If this device is Miracast source device, the scan reuslt should just provide the Miracast PSink. */
++						/*	Todo: How about the SSink?! */
++						blnGotWFD = _TRUE;
++					}
++				}
++			}
++		}
++
++		if (blnGotWFD == _FALSE)
++			return _FALSE;
++	}
++#endif /* CONFIG_WFD */
++
++#endif /* CONFIG_P2P */
++	return _TRUE;
++}
++static inline char *iwe_stream_mac_addr_proess(_adapter *padapter,
++		struct iw_request_info *info, struct wlan_network *pnetwork,
++		char *start, char *stop, struct iw_event *iwe)
++{
++	/*  AP MAC address */
++	iwe->cmd = SIOCGIWAP;
++	iwe->u.ap_addr.sa_family = ARPHRD_ETHER;
++
++	_rtw_memcpy(iwe->u.ap_addr.sa_data, pnetwork->network.MacAddress, ETH_ALEN);
++	start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_ADDR_LEN);
++	return start;
++}
++static inline char *iwe_stream_essid_proess(_adapter *padapter,
++		struct iw_request_info *info, struct wlan_network *pnetwork,
++		char *start, char *stop, struct iw_event *iwe)
++{
++
++	/* Add the ESSID */
++	iwe->cmd = SIOCGIWESSID;
++	iwe->u.data.flags = 1;
++	iwe->u.data.length = min((u16)pnetwork->network.Ssid.SsidLength, (u16)32);
++	start = iwe_stream_add_point(info, start, stop, iwe, pnetwork->network.Ssid.Ssid);
++	return start;
++}
++
++static inline char *iwe_stream_chan_process(_adapter *padapter,
++		struct iw_request_info *info, struct wlan_network *pnetwork,
++		char *start, char *stop, struct iw_event *iwe)
++{
++	if (pnetwork->network.Configuration.DSConfig < 1 /*|| pnetwork->network.Configuration.DSConfig>14*/)
++		pnetwork->network.Configuration.DSConfig = 1;
++
++	/* Add frequency/channel */
++	iwe->cmd = SIOCGIWFREQ;
++	iwe->u.freq.m = rtw_ch2freq(pnetwork->network.Configuration.DSConfig) * 100000;
++	iwe->u.freq.e = 1;
++	iwe->u.freq.i = pnetwork->network.Configuration.DSConfig;
++	start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_FREQ_LEN);
++	return start;
++}
++static inline char *iwe_stream_mode_process(_adapter *padapter,
++		struct iw_request_info *info, struct wlan_network *pnetwork,
++		char *start, char *stop, struct iw_event *iwe, u16 cap)
++{
++	/* Add mode */
++	if (cap & (WLAN_CAPABILITY_IBSS | WLAN_CAPABILITY_BSS)) {
++		iwe->cmd = SIOCGIWMODE;
++		if (cap & WLAN_CAPABILITY_BSS)
++			iwe->u.mode = IW_MODE_MASTER;
++		else
++			iwe->u.mode = IW_MODE_ADHOC;
++
++		start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_UINT_LEN);
++	}
++	return start;
++}
++static inline char *iwe_stream_encryption_process(_adapter *padapter,
++		struct iw_request_info *info, struct wlan_network *pnetwork,
++		char *start, char *stop, struct iw_event *iwe, u16 cap)
++{
++
++	/* Add encryption capability */
++	iwe->cmd = SIOCGIWENCODE;
++	if (cap & WLAN_CAPABILITY_PRIVACY)
++		iwe->u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
++	else
++		iwe->u.data.flags = IW_ENCODE_DISABLED;
++	iwe->u.data.length = 0;
++	start = iwe_stream_add_point(info, start, stop, iwe, pnetwork->network.Ssid.Ssid);
++	return start;
++
++}
++
++static inline char *iwe_stream_protocol_process(_adapter *padapter,
++		struct iw_request_info *info, struct wlan_network *pnetwork,
++		char *start, char *stop, struct iw_event *iwe)
++{
++	u16 ht_cap = _FALSE, vht_cap = _FALSE;
++	u32 ht_ielen = 0, vht_ielen = 0;
++	char *p;
++	u8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); /* Probe Request	 */
++
++#ifdef CONFIG_80211N_HT
++	/* parsing HT_CAP_IE	 */
++	if(padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode)) {
++		p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - ie_offset);
++		if (p && ht_ielen > 0)
++			ht_cap = _TRUE;
++	}
++#endif
++
++#ifdef CONFIG_80211AC_VHT
++	/* parsing VHT_CAP_IE */
++	if(padapter->registrypriv.wireless_mode & WIRELESS_11AC) {
++		p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset);
++		if (p && vht_ielen > 0)
++			vht_cap = _TRUE;
++	}
++#endif
++	/* Add the protocol name */
++	iwe->cmd = SIOCGIWNAME;
++	if ((rtw_is_cckratesonly_included((u8 *)&pnetwork->network.SupportedRates)) == _TRUE) {
++		if (ht_cap == _TRUE)
++			snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11bn");
++		else
++			snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11b");
++	} else if ((rtw_is_cckrates_included((u8 *)&pnetwork->network.SupportedRates)) == _TRUE) {
++		if (ht_cap == _TRUE)
++			snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11bgn");
++		else
++			snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11bg");
++	} else {
++		if (pnetwork->network.Configuration.DSConfig > 14) {
++			#ifdef CONFIG_80211AC_VHT
++			if (vht_cap == _TRUE)
++				snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11AC");
++			else
++			#endif
++			{
++				if (ht_cap == _TRUE)
++					snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11an");
++				else
++					snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11a");
++			}
++		} else {
++			if (ht_cap == _TRUE)
++				snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11gn");
++			else
++				snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11g");
++		}
++	}
++	start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_CHAR_LEN);
++	return start;
++}
++
++static inline char *iwe_stream_rate_process(_adapter *padapter,
++		struct iw_request_info *info, struct wlan_network *pnetwork,
++		char *start, char *stop, struct iw_event *iwe)
++{
++	u32 ht_ielen = 0, vht_ielen = 0;
++	char *p;
++	u16 max_rate = 0, rate, ht_cap = _FALSE, vht_cap = _FALSE;
++	u32 i = 0;
++	u8 bw_40MHz = 0, short_GI = 0, bw_160MHz = 0, vht_highest_rate = 0;
++	u16 mcs_rate = 0, vht_data_rate = 0;
++	char custom[MAX_CUSTOM_LEN] = {0};
++	u8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); /* Probe Request	 */
++
++	/* parsing HT_CAP_IE	 */
++	if(is_supported_ht(padapter->registrypriv.wireless_mode)) {
++		p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - ie_offset);
++		if (p && ht_ielen > 0) {
++			struct rtw_ieee80211_ht_cap *pht_capie;
++			ht_cap = _TRUE;
++			pht_capie = (struct rtw_ieee80211_ht_cap *)(p + 2);
++			_rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2);
++			bw_40MHz = (pht_capie->cap_info & IEEE80211_HT_CAP_SUP_WIDTH) ? 1 : 0;
++			short_GI = (pht_capie->cap_info & (IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40)) ? 1 : 0;
++		}
++	}
++#ifdef CONFIG_80211AC_VHT
++	/* parsing VHT_CAP_IE */
++	if(padapter->registrypriv.wireless_mode & WIRELESS_11AC){
++		p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset);
++		if (p && vht_ielen > 0) {
++			u8	mcs_map[2];
++
++			vht_cap = _TRUE;
++			bw_160MHz = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p + 2);
++			if (bw_160MHz)
++				short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI160M(p + 2);
++			else
++				short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI80M(p + 2);
++
++			_rtw_memcpy(mcs_map, GET_VHT_CAPABILITY_ELE_TX_MCS(p + 2), 2);
++
++			vht_highest_rate = rtw_get_vht_highest_rate(mcs_map);
++			vht_data_rate = rtw_vht_mcs_to_data_rate(CHANNEL_WIDTH_80, short_GI, vht_highest_rate);
++		}
++	}
++#endif
++
++	/*Add basic and extended rates */
++	p = custom;
++	p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), " Rates (Mb/s): ");
++	while (pnetwork->network.SupportedRates[i] != 0) {
++		rate = pnetwork->network.SupportedRates[i] & 0x7F;
++		if (rate > max_rate)
++			max_rate = rate;
++		p += snprintf(p, MAX_CUSTOM_LEN - (p - custom),
++			      "%d%s ", rate >> 1, (rate & 1) ? ".5" : "");
++		i++;
++	}
++#ifdef CONFIG_80211AC_VHT
++	if (vht_cap == _TRUE)
++		max_rate = vht_data_rate;
++	else
++#endif
++		if (ht_cap == _TRUE) {
++			if (mcs_rate & 0x8000) /* MCS15 */
++				max_rate = (bw_40MHz) ? ((short_GI) ? 300 : 270) : ((short_GI) ? 144 : 130);
++
++			else if (mcs_rate & 0x0080) /* MCS7 */
++				max_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65);
++			else { /* default MCS7 */
++				/* RTW_INFO("wx_get_scan, mcs_rate_bitmap=0x%x\n", mcs_rate); */
++				max_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65);
++			}
++
++			max_rate = max_rate * 2; /* Mbps/2;		 */
++		}
++
++	iwe->cmd = SIOCGIWRATE;
++	iwe->u.bitrate.fixed = iwe->u.bitrate.disabled = 0;
++	iwe->u.bitrate.value = max_rate * 500000;
++	start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_PARAM_LEN);
++	return start ;
++}
++
++static inline char *iwe_stream_wpa_wpa2_process(_adapter *padapter,
++		struct iw_request_info *info, struct wlan_network *pnetwork,
++		char *start, char *stop, struct iw_event *iwe)
++{
++	int buf_size = MAX_WPA_IE_LEN * 2;
++	/* u8 pbuf[buf_size]={0};	 */
++	u8 *pbuf = rtw_zmalloc(buf_size);
++
++	u8 wpa_ie[255] = {0}, rsn_ie[255] = {0};
++	u16 i, wpa_len = 0, rsn_len = 0;
++	u8 *p;
++	sint out_len = 0;
++
++
++	if (pbuf) {
++		p = pbuf;
++
++		/* parsing WPA/WPA2 IE */
++		if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ) { /* Probe Request */
++			out_len = rtw_get_sec_ie(pnetwork->network.IEs , pnetwork->network.IELength, rsn_ie, &rsn_len, wpa_ie, &wpa_len);
++
++			if (wpa_len > 0) {
++
++				_rtw_memset(pbuf, 0, buf_size);
++				p += sprintf(p, "wpa_ie=");
++				for (i = 0; i < wpa_len; i++)
++					p += sprintf(p, "%02x", wpa_ie[i]);
++
++				if (wpa_len > 100) {
++					printk("-----------------Len %d----------------\n", wpa_len);
++					for (i = 0; i < wpa_len; i++)
++						printk("%02x ", wpa_ie[i]);
++					printk("\n");
++					printk("-----------------Len %d----------------\n", wpa_len);
++				}
++
++				_rtw_memset(iwe, 0, sizeof(*iwe));
++				iwe->cmd = IWEVCUSTOM;
++				iwe->u.data.length = strlen(pbuf);
++				start = iwe_stream_add_point(info, start, stop, iwe, pbuf);
++
++				_rtw_memset(iwe, 0, sizeof(*iwe));
++				iwe->cmd = IWEVGENIE;
++				iwe->u.data.length = wpa_len;
++				start = iwe_stream_add_point(info, start, stop, iwe, wpa_ie);
++			}
++			if (rsn_len > 0) {
++
++				_rtw_memset(pbuf, 0, buf_size);
++				p += sprintf(p, "rsn_ie=");
++				for (i = 0; i < rsn_len; i++)
++					p += sprintf(p, "%02x", rsn_ie[i]);
++				_rtw_memset(iwe, 0, sizeof(*iwe));
++				iwe->cmd = IWEVCUSTOM;
++				iwe->u.data.length = strlen(pbuf);
++				start = iwe_stream_add_point(info, start, stop, iwe, pbuf);
++
++				_rtw_memset(iwe, 0, sizeof(*iwe));
++				iwe->cmd = IWEVGENIE;
++				iwe->u.data.length = rsn_len;
++				start = iwe_stream_add_point(info, start, stop, iwe, rsn_ie);
++			}
++		}
++
++		rtw_mfree(pbuf, buf_size);
++	}
++	return start;
++}
++
++static inline char *iwe_stream_wps_process(_adapter *padapter,
++		struct iw_request_info *info, struct wlan_network *pnetwork,
++		char *start, char *stop, struct iw_event *iwe)
++{
++	/* parsing WPS IE */
++	uint cnt = 0, total_ielen;
++	u8 *wpsie_ptr = NULL;
++	uint wps_ielen = 0;
++	u8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12);
++
++	u8 *ie_ptr = pnetwork->network.IEs + ie_offset;
++	total_ielen = pnetwork->network.IELength - ie_offset;
++
++	if (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ) { /* Probe Request */
++		ie_ptr = pnetwork->network.IEs;
++		total_ielen = pnetwork->network.IELength;
++	} else { /* Beacon or Probe Respones */
++		ie_ptr = pnetwork->network.IEs + _FIXED_IE_LENGTH_;
++		total_ielen = pnetwork->network.IELength - _FIXED_IE_LENGTH_;
++	}
++	while (cnt < total_ielen) {
++		if (rtw_is_wps_ie(&ie_ptr[cnt], &wps_ielen) && (wps_ielen > 2)) {
++			wpsie_ptr = &ie_ptr[cnt];
++			iwe->cmd = IWEVGENIE;
++			iwe->u.data.length = (u16)wps_ielen;
++			start = iwe_stream_add_point(info, start, stop, iwe, wpsie_ptr);
++		}
++		cnt += ie_ptr[cnt + 1] + 2; /* goto next */
++	}
++	return start;
++}
++
++static inline char *iwe_stream_wapi_process(_adapter *padapter,
++		struct iw_request_info *info, struct wlan_network *pnetwork,
++		char *start, char *stop, struct iw_event *iwe)
++{
++#ifdef CONFIG_WAPI_SUPPORT
++	char *p;
++
++	if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ) { /* Probe Request */
++		sint out_len_wapi = 0;
++		/* here use static for stack size */
++		static u8 buf_wapi[MAX_WAPI_IE_LEN * 2] = {0};
++		static u8 wapi_ie[MAX_WAPI_IE_LEN] = {0};
++		u16 wapi_len = 0;
++		u16  i;
++
++		out_len_wapi = rtw_get_wapi_ie(pnetwork->network.IEs , pnetwork->network.IELength, wapi_ie, &wapi_len);
++
++		RTW_INFO("rtw_wx_get_scan: %s ", pnetwork->network.Ssid.Ssid);
++		RTW_INFO("rtw_wx_get_scan: ssid = %d ", wapi_len);
++
++
++		if (wapi_len > 0) {
++			p = buf_wapi;
++			/* _rtw_memset(buf_wapi, 0, MAX_WAPI_IE_LEN*2); */
++			p += sprintf(p, "wapi_ie=");
++			for (i = 0; i < wapi_len; i++)
++				p += sprintf(p, "%02x", wapi_ie[i]);
++
++			_rtw_memset(iwe, 0, sizeof(*iwe));
++			iwe->cmd = IWEVCUSTOM;
++			iwe->u.data.length = strlen(buf_wapi);
++			start = iwe_stream_add_point(info, start, stop, iwe, buf_wapi);
++
++			_rtw_memset(iwe, 0, sizeof(*iwe));
++			iwe->cmd = IWEVGENIE;
++			iwe->u.data.length = wapi_len;
++			start = iwe_stream_add_point(info, start, stop, iwe, wapi_ie);
++		}
++	}
++#endif/* #ifdef CONFIG_WAPI_SUPPORT */
++	return start;
++}
++
++static inline char   *iwe_stream_rssi_process(_adapter *padapter,
++		struct iw_request_info *info, struct wlan_network *pnetwork,
++		char *start, char *stop, struct iw_event *iwe)
++{
++	u8 ss, sq;
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++	s16 noise = 0;
++#endif
++
++	/* Add quality statistics */
++	iwe->cmd = IWEVQUAL;
++	iwe->u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++			      | IW_QUAL_NOISE_UPDATED
++#else
++			      | IW_QUAL_NOISE_INVALID
++#endif
++#ifdef CONFIG_SIGNAL_DISPLAY_DBM
++			      | IW_QUAL_DBM
++#endif
++			      ;
++
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE &&
++	    is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) {
++		ss = padapter->recvpriv.signal_strength;
++		sq = padapter->recvpriv.signal_qual;
++	} else {
++		ss = pnetwork->network.PhyInfo.SignalStrength;
++		sq = pnetwork->network.PhyInfo.SignalQuality;
++	}
++
++
++#ifdef CONFIG_SIGNAL_DISPLAY_DBM
++	iwe->u.qual.level = (u8) translate_percentage_to_dbm(ss); /* dbm */
++#else
++	iwe->u.qual.level = (u8)ss; /* % */
++#endif
++
++	iwe->u.qual.qual = (u8)sq;   /* signal quality */
++
++#ifdef CONFIG_PLATFORM_ROCKCHIPS
++	iwe->u.qual.noise = -100; /* noise level suggest by zhf@rockchips */
++#else
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++	if (IS_NM_ENABLE(padapter)) {
++		noise = rtw_noise_query_by_chan_num(padapter, pnetwork->network.Configuration.DSConfig);
++		#ifndef CONFIG_SIGNAL_DISPLAY_DBM
++		noise = translate_dbm_to_percentage(noise);/*percentage*/
++		#endif
++		iwe->u.qual.noise = noise;
++	}
++#else
++	iwe->u.qual.noise = 0; /* noise level */
++#endif
++#endif /* CONFIG_PLATFORM_ROCKCHIPS */
++
++	/* RTW_INFO("iqual=%d, ilevel=%d, inoise=%d, iupdated=%d\n", iwe.u.qual.qual, iwe.u.qual.level , iwe.u.qual.noise, iwe.u.qual.updated); */
++
++	start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_QUAL_LEN);
++	return start;
++}
++
++static inline char   *iwe_stream_net_rsv_process(_adapter *padapter,
++		struct iw_request_info *info, struct wlan_network *pnetwork,
++		char *start, char *stop, struct iw_event *iwe)
++{
++	u8 buf[32] = {0};
++	u8 *p, *pos;
++	p = buf;
++	pos = pnetwork->network.Reserved;
++
++	p += sprintf(p, "fm=%02X%02X", pos[1], pos[0]);
++	_rtw_memset(iwe, 0, sizeof(*iwe));
++	iwe->cmd = IWEVCUSTOM;
++	iwe->u.data.length = strlen(buf);
++	start = iwe_stream_add_point(info, start, stop, iwe, buf);
++	return start;
++}
++
++static char *translate_scan(_adapter *padapter,
++		struct iw_request_info *info, struct wlan_network *pnetwork,
++		char *start, char *stop)
++{
++	struct iw_event iwe;
++	u16 cap = 0;
++	_rtw_memset(&iwe, 0, sizeof(iwe));
++
++	if (_FALSE == search_p2p_wfd_ie(padapter, info, pnetwork, start, stop))
++		return start;
++
++	start = iwe_stream_mac_addr_proess(padapter, info, pnetwork, start, stop, &iwe);
++	start = iwe_stream_essid_proess(padapter, info, pnetwork, start, stop, &iwe);
++	start = iwe_stream_protocol_process(padapter, info, pnetwork, start, stop, &iwe);
++	if (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ) /* Probe Request */
++		cap = 0;
++	else {
++		_rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2);
++		cap = le16_to_cpu(cap);
++	}
++
++	start = iwe_stream_mode_process(padapter, info, pnetwork, start, stop, &iwe, cap);
++	start = iwe_stream_chan_process(padapter, info, pnetwork, start, stop, &iwe);
++	start = iwe_stream_encryption_process(padapter, info, pnetwork, start, stop, &iwe, cap);
++	start = iwe_stream_rate_process(padapter, info, pnetwork, start, stop, &iwe);
++	start = iwe_stream_wpa_wpa2_process(padapter, info, pnetwork, start, stop, &iwe);
++	start = iwe_stream_wps_process(padapter, info, pnetwork, start, stop, &iwe);
++	start = iwe_stream_wapi_process(padapter, info, pnetwork, start, stop, &iwe);
++	start = iwe_stream_rssi_process(padapter, info, pnetwork, start, stop, &iwe);
++	start = iwe_stream_net_rsv_process(padapter, info, pnetwork, start, stop, &iwe);
++
++	return start;
++}
++
++static int wpa_set_auth_algs(struct net_device *dev, u32 value)
++{
++	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
++	int ret = 0;
++
++	if ((value & AUTH_ALG_SHARED_KEY) && (value & AUTH_ALG_OPEN_SYSTEM)) {
++		RTW_INFO("wpa_set_auth_algs, AUTH_ALG_SHARED_KEY and  AUTH_ALG_OPEN_SYSTEM [value:0x%x]\n", value);
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++		padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch;
++		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
++	} else if (value & AUTH_ALG_SHARED_KEY) {
++		RTW_INFO("wpa_set_auth_algs, AUTH_ALG_SHARED_KEY  [value:0x%x]\n", value);
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++
++#ifdef CONFIG_PLATFORM_MT53XX
++		padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch;
++		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
++#else
++		padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeShared;
++		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Shared;
++#endif
++	} else if (value & AUTH_ALG_OPEN_SYSTEM) {
++		RTW_INFO("wpa_set_auth_algs, AUTH_ALG_OPEN_SYSTEM\n");
++		/* padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; */
++		if (padapter->securitypriv.ndisauthtype < Ndis802_11AuthModeWPAPSK) {
++#ifdef CONFIG_PLATFORM_MT53XX
++			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch;
++			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
++#else
++			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;
++			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
++#endif
++		}
++
++	} else if (value & AUTH_ALG_LEAP)
++		RTW_INFO("wpa_set_auth_algs, AUTH_ALG_LEAP\n");
++	else {
++		RTW_INFO("wpa_set_auth_algs, error!\n");
++		ret = -EINVAL;
++	}
++
++	return ret;
++
++}
++
++static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len)
++{
++	int ret = 0;
++	u32 wep_key_idx, wep_key_len;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++#ifdef CONFIG_P2P
++	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++#endif /* CONFIG_P2P */
++
++
++	param->u.crypt.err = 0;
++	param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0';
++
++	if (param_len < (u32)((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) {
++		ret =  -EINVAL;
++		goto exit;
++	}
++
++	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
++	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
++	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) {
++
++		if (param->u.crypt.idx >= WEP_KEYS
++#ifdef CONFIG_IEEE80211W
++		    && param->u.crypt.idx > BIP_MAX_KEYID
++#endif /* CONFIG_IEEE80211W */
++		   ) {
++			ret = -EINVAL;
++			goto exit;
++		}
++	} else {
++#ifdef CONFIG_WAPI_SUPPORT
++		if (strcmp(param->u.crypt.alg, "SMS4"))
++#endif
++		{
++			ret = -EINVAL;
++			goto exit;
++		}
++	}
++
++	if (strcmp(param->u.crypt.alg, "WEP") == 0) {
++		RTW_INFO("wpa_set_encryption, crypt.alg = WEP\n");
++
++		wep_key_idx = param->u.crypt.idx;
++		wep_key_len = param->u.crypt.key_len;
++
++		if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) {
++			ret = -EINVAL;
++			goto exit;
++		}
++
++		if (psecuritypriv->bWepDefaultKeyIdxSet == 0) {
++			/* wep default key has not been set, so use this key index as default key.*/
++
++			wep_key_len = wep_key_len <= 5 ? 5 : 13;
++
++			psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
++			psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
++			psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
++
++			if (wep_key_len == 13) {
++				psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
++				psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
++			}
++
++			psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;
++		}
++
++		_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len);
++
++		psecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len;
++
++		psecuritypriv->key_mask |= BIT(wep_key_idx);
++
++		padapter->mlmeextpriv.mlmext_info.key_index = wep_key_idx;
++		goto exit;
++	}
++
++	if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { /* 802_1x */
++		struct sta_info *psta, *pbcmc_sta;
++		struct sta_priv *pstapriv = &padapter->stapriv;
++
++		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) { /* sta mode */
++			psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
++			if (psta == NULL) {
++				/* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */
++			} else {
++				/* Jeff: don't disable ieee8021x_blocked while clearing key */
++				if (strcmp(param->u.crypt.alg, "none") != 0)
++					psta->ieee8021x_blocked = _FALSE;
++
++				if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) ||
++				    (padapter->securitypriv.ndisencryptstatus ==  Ndis802_11Encryption3Enabled))
++					psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
++
++				if (param->u.crypt.set_tx == 1) { /* pairwise key */
++					RTW_INFO(FUNC_ADPT_FMT" set %s PTK idx:%u, len:%u\n"
++						, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);
++					_rtw_memcpy(psta->dot118021x_UncstKey.skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++					if (strcmp(param->u.crypt.alg, "TKIP") == 0) { /* set mic key */
++						_rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);
++						_rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);
++						padapter->securitypriv.busetkipkey = _FALSE;
++					}
++					psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
++					psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq);
++					psta->bpairwise_key_installed = _TRUE;
++					rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _TRUE);
++
++				} else { /* group key */
++					if (strcmp(param->u.crypt.alg, "TKIP") == 0 || strcmp(param->u.crypt.alg, "CCMP") == 0) {
++						RTW_INFO(FUNC_ADPT_FMT" set %s GTK idx:%u, len:%u\n"
++							, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);
++						_rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key,
++							(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++						/* only TKIP group key need to install this */
++						if (param->u.crypt.key_len > 16) {
++							_rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);
++							_rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);
++						}
++						padapter->securitypriv.binstallGrpkey = _TRUE;
++						if (param->u.crypt.idx < 4)
++							_rtw_memcpy(padapter->securitypriv.iv_seq[param->u.crypt.idx], param->u.crypt.seq, 8);
++						padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx;
++						rtw_set_key(padapter, &padapter->securitypriv, param->u.crypt.idx, 1, _TRUE);
++
++					#ifdef CONFIG_IEEE80211W
++					} else if (strcmp(param->u.crypt.alg, "BIP") == 0) {
++						RTW_INFO(FUNC_ADPT_FMT" set IGTK idx:%u, len:%u\n"
++							, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++						_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey,  param->u.crypt.key,
++							(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++						psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
++						psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq);
++						psecuritypriv->binstallBIPkey = _TRUE;
++					#endif /* CONFIG_IEEE80211W */
++
++					}
++
++#ifdef CONFIG_P2P
++					if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))
++						rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE);
++#endif /* CONFIG_P2P */
++
++					/* WPA/WPA2 key-handshake has completed */
++					clr_fwstate(pmlmepriv, WIFI_UNDER_KEY_HANDSHAKE);
++				}
++			}
++
++			pbcmc_sta = rtw_get_bcmc_stainfo(padapter);
++			if (pbcmc_sta == NULL) {
++				/* DEBUG_ERR( ("Set OID_802_11_ADD_KEY: bcmc stainfo is null\n")); */
++			} else {
++				/* Jeff: don't disable ieee8021x_blocked while clearing key */
++				if (strcmp(param->u.crypt.alg, "none") != 0)
++					pbcmc_sta->ieee8021x_blocked = _FALSE;
++
++				if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) ||
++				    (padapter->securitypriv.ndisencryptstatus ==  Ndis802_11Encryption3Enabled))
++					pbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
++			}
++		} else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) { /* adhoc mode */
++		}
++	}
++
++#ifdef CONFIG_WAPI_SUPPORT
++	if (strcmp(param->u.crypt.alg, "SMS4") == 0)
++		rtw_wapi_set_set_encryption(padapter, param);
++#endif
++
++exit:
++
++
++	return ret;
++}
++
++static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen)
++{
++	u8 *buf = NULL, *pos = NULL;
++	int group_cipher = 0, pairwise_cipher = 0;
++	u8 mfp_opt = MFP_NO;
++	int ret = 0;
++	u8 null_addr[] = {0, 0, 0, 0, 0, 0};
++#ifdef CONFIG_P2P
++	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++#endif /* CONFIG_P2P */
++
++	if ((ielen > MAX_WPA_IE_LEN) || (pie == NULL)) {
++		_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
++		if (pie == NULL)
++			return ret;
++		else
++			return -EINVAL;
++	}
++
++	if (ielen) {
++		buf = rtw_zmalloc(ielen);
++		if (buf == NULL) {
++			ret =  -ENOMEM;
++			goto exit;
++		}
++
++		_rtw_memcpy(buf, pie , ielen);
++
++		/* dump */
++		{
++			int i;
++			RTW_INFO("\n wpa_ie(length:%d):\n", ielen);
++			for (i = 0; i < ielen; i = i + 8)
++				RTW_INFO("0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x\n", buf[i], buf[i + 1], buf[i + 2], buf[i + 3], buf[i + 4], buf[i + 5], buf[i + 6], buf[i + 7]);
++		}
++
++		pos = buf;
++		if (ielen < RSN_HEADER_LEN) {
++			ret  = -1;
++			goto exit;
++		}
++
++		if (rtw_parse_wpa_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {
++			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
++			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK;
++			_rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen);
++		}
++
++		if (rtw_parse_wpa2_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL, NULL, &mfp_opt) == _SUCCESS) {
++			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
++			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK;
++			_rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen);
++		}
++
++		if (group_cipher == 0)
++			group_cipher = WPA_CIPHER_NONE;
++		if (pairwise_cipher == 0)
++			pairwise_cipher = WPA_CIPHER_NONE;
++
++		switch (group_cipher) {
++		case WPA_CIPHER_NONE:
++			padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
++			padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
++			break;
++		case WPA_CIPHER_WEP40:
++			padapter->securitypriv.dot118021XGrpPrivacy = _WEP40_;
++			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++			break;
++		case WPA_CIPHER_TKIP:
++			padapter->securitypriv.dot118021XGrpPrivacy = _TKIP_;
++			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
++			break;
++		case WPA_CIPHER_CCMP:
++			padapter->securitypriv.dot118021XGrpPrivacy = _AES_;
++			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
++			break;
++		case WPA_CIPHER_WEP104:
++			padapter->securitypriv.dot118021XGrpPrivacy = _WEP104_;
++			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++			break;
++		}
++
++		switch (pairwise_cipher) {
++		case WPA_CIPHER_NONE:
++			padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
++			padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
++			break;
++		case WPA_CIPHER_WEP40:
++			padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_;
++			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++			break;
++		case WPA_CIPHER_TKIP:
++			padapter->securitypriv.dot11PrivacyAlgrthm = _TKIP_;
++			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
++			break;
++		case WPA_CIPHER_CCMP:
++			padapter->securitypriv.dot11PrivacyAlgrthm = _AES_;
++			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
++			break;
++		case WPA_CIPHER_WEP104:
++			padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;
++			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++			break;
++		}
++
++		if (mfp_opt == MFP_INVALID) {
++			RTW_INFO(FUNC_ADPT_FMT" invalid MFP setting\n", FUNC_ADPT_ARG(padapter));
++			ret = -EINVAL;
++			goto exit;
++		}
++		padapter->securitypriv.mfp_opt = mfp_opt;
++
++		_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
++		{/* set wps_ie	 */
++			u16 cnt = 0;
++			u8 eid, wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};
++
++			while (cnt < ielen) {
++				eid = buf[cnt];
++
++				if ((eid == _VENDOR_SPECIFIC_IE_) && (_rtw_memcmp(&buf[cnt + 2], wps_oui, 4) == _TRUE)) {
++					RTW_INFO("SET WPS_IE\n");
++
++					padapter->securitypriv.wps_ie_len = ((buf[cnt + 1] + 2) < MAX_WPS_IE_LEN) ? (buf[cnt + 1] + 2) : MAX_WPS_IE_LEN;
++
++					_rtw_memcpy(padapter->securitypriv.wps_ie, &buf[cnt], padapter->securitypriv.wps_ie_len);
++
++					set_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS);
++
++#ifdef CONFIG_P2P
++					if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK))
++						rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_ING);
++#endif /* CONFIG_P2P */
++					cnt += buf[cnt + 1] + 2;
++
++					break;
++				} else {
++					cnt += buf[cnt + 1] + 2; /* goto next	 */
++				}
++			}
++		}
++
++		#ifdef CONFIG_RTW_MULTI_AP
++		padapter->multi_ap = rtw_get_multi_ap_ie_ext(buf, ielen) & MULTI_AP_BACKHAUL_STA;
++		if (padapter->multi_ap)
++			adapter_set_use_wds(padapter, 1);
++		#endif
++	}
++
++	/* TKIP and AES disallow multicast packets until installing group key */
++	if (padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_
++	    || padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_
++	    || padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)
++		/* WPS open need to enable multicast
++		 * || check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE) */
++		rtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr);
++
++
++exit:
++
++	if (buf)
++		rtw_mfree(buf, ielen);
++
++	return ret;
++}
++
++static int rtw_wx_get_name(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u32 ht_ielen = 0;
++	char *p;
++	u8 ht_cap = _FALSE, vht_cap = _FALSE;
++	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	WLAN_BSSID_EX  *pcur_bss = &pmlmepriv->cur_network.network;
++	NDIS_802_11_RATES_EX *prates = NULL;
++
++
++
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE) {
++		/* parsing HT_CAP_IE */
++		if( is_supported_ht(padapter->registrypriv.wireless_mode)&&(padapter->registrypriv.ht_enable)) {
++			p = rtw_get_ie(&pcur_bss->IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pcur_bss->IELength - 12);
++			if (p && ht_ielen > 0 )
++				ht_cap = _TRUE;
++		}
++#ifdef CONFIG_80211AC_VHT
++		if ((padapter->registrypriv.wireless_mode & WIRELESS_11AC) &&
++			(pmlmepriv->vhtpriv.vht_option == _TRUE))
++			vht_cap = _TRUE;
++#endif
++
++		prates = &pcur_bss->SupportedRates;
++		if (rtw_is_cckratesonly_included((u8 *)prates) == _TRUE) {
++			if (ht_cap == _TRUE)
++				snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bn");
++			else
++				snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11b");
++		} else if ((rtw_is_cckrates_included((u8 *)prates)) == _TRUE) {
++			if (ht_cap == _TRUE)
++				snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bgn");
++			else {
++				if(padapter->registrypriv.wireless_mode & WIRELESS_11G)
++					snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bg");
++				else
++					snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11b");
++			}
++		} else {
++			if (pcur_bss->Configuration.DSConfig > 14) {
++#ifdef CONFIG_80211AC_VHT
++				if (vht_cap == _TRUE)
++					snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11AC");
++				else
++#endif
++				{
++					if (ht_cap == _TRUE)
++						snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11an");
++					else
++						snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11a");
++				}
++			} else {
++				if (ht_cap == _TRUE)
++					snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11gn");
++				else
++					snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g");
++			}
++		}
++	} else {
++		/* prates = &padapter->registrypriv.dev_network.SupportedRates; */
++		/* snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g"); */
++		snprintf(wrqu->name, IFNAMSIZ, "unassociated");
++	}
++
++
++	return 0;
++}
++
++static int rtw_wx_set_freq(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra)
++{
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	int exp = 1, freq = 0, div = 0;
++
++	rtw_ps_deny(padapter, PS_DENY_IOCTL);
++	if (rtw_pwr_wakeup(padapter) == _FALSE)
++		goto exit;
++	if (wrqu->freq.m <= 1000) {
++		if (wrqu->freq.flags == IW_FREQ_AUTO) {
++			if (rtw_chset_search_ch(adapter_to_chset(padapter), wrqu->freq.m) > 0) {
++				padapter->mlmeextpriv.cur_channel = wrqu->freq.m;
++				RTW_INFO("%s: channel is auto, set to channel %d\n", __func__, wrqu->freq.m);
++			} else {
++				padapter->mlmeextpriv.cur_channel = 1;
++				RTW_INFO("%s: channel is auto, Channel Plan don't match just set to channel 1\n", __func__);
++			}
++		} else {
++			padapter->mlmeextpriv.cur_channel = wrqu->freq.m;
++			RTW_INFO("%s: set to channel %d\n", __func__, padapter->mlmeextpriv.cur_channel);
++		}
++	} else {
++		while (wrqu->freq.e) {
++			exp *= 10;
++			wrqu->freq.e--;
++		}
++
++		freq = wrqu->freq.m;
++
++		while (!(freq % 10)) {
++			freq /= 10;
++			exp *= 10;
++		}
++
++		/* freq unit is MHz here */
++		div = 1000000 / exp;
++
++		if (div)
++			freq /= div;
++		else {
++			div = exp / 1000000;
++			freq *= div;
++		}
++
++		/* If freq is invalid, rtw_freq2ch() will return channel 1 */
++		padapter->mlmeextpriv.cur_channel = rtw_freq2ch(freq);
++		RTW_INFO("%s: set to channel %d\n", __func__, padapter->mlmeextpriv.cur_channel);
++	}
++	set_channel_bwmode(padapter, padapter->mlmeextpriv.cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++exit:
++	rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
++
++	return 0;
++}
++
++static int rtw_wx_get_freq(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	WLAN_BSSID_EX  *pcur_bss = &pmlmepriv->cur_network.network;
++
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE && check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE) {
++
++		wrqu->freq.m = rtw_ch2freq(pcur_bss->Configuration.DSConfig) * 100000;
++		wrqu->freq.e = 1;
++		wrqu->freq.i = pcur_bss->Configuration.DSConfig;
++
++	} else {
++		wrqu->freq.m = rtw_ch2freq(padapter->mlmeextpriv.cur_channel) * 100000;
++		wrqu->freq.e = 1;
++		wrqu->freq.i = padapter->mlmeextpriv.cur_channel;
++	}
++
++	return 0;
++}
++
++static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a,
++			   union iwreq_data *wrqu, char *b)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	NDIS_802_11_NETWORK_INFRASTRUCTURE networkType ;
++	int ret = 0;
++
++
++	if (_FAIL == rtw_pwr_wakeup(padapter)) {
++		ret = -EPERM;
++		goto exit;
++	}
++
++	if (!rtw_is_hw_init_completed(padapter)) {
++		ret = -EPERM;
++		goto exit;
++	}
++
++	/* initial default type */
++	dev->type = ARPHRD_ETHER;
++
++	if (wrqu->mode != IW_MODE_MONITOR) {
++		rtw_ps_deny_cancel(padapter, PS_DENY_MONITOR_MODE);
++	}
++
++	switch (wrqu->mode) {
++#ifdef CONFIG_WIFI_MONITOR
++	case IW_MODE_MONITOR:
++		networkType = Ndis802_11Monitor;
++
++		rtw_ps_deny(padapter, PS_DENY_MONITOR_MODE);
++		LeaveAllPowerSaveMode(padapter);
++
++#if 0
++		dev->type = ARPHRD_IEEE80211; /* IEEE 802.11 : 801 */
++#endif
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
++		dev->type = ARPHRD_IEEE80211_RADIOTAP; /* IEEE 802.11 + radiotap header : 803 */
++		RTW_INFO("set_mode = IW_MODE_MONITOR\n");
++#else
++		RTW_INFO("kernel version < 2.6.24 not support IW_MODE_MONITOR\n");
++#endif
++		break;
++#endif /* CONFIG_WIFI_MONITOR */
++	case IW_MODE_AUTO:
++		networkType = Ndis802_11AutoUnknown;
++		RTW_INFO("set_mode = IW_MODE_AUTO\n");
++		break;
++	case IW_MODE_ADHOC:
++		networkType = Ndis802_11IBSS;
++		RTW_INFO("set_mode = IW_MODE_ADHOC\n");
++		break;
++	case IW_MODE_MASTER:
++		networkType = Ndis802_11APMode;
++		RTW_INFO("set_mode = IW_MODE_MASTER\n");
++		break;
++	case IW_MODE_INFRA:
++		networkType = Ndis802_11Infrastructure;
++		RTW_INFO("set_mode = IW_MODE_INFRA\n");
++		break;
++
++	default:
++		ret = -EINVAL;;
++		goto exit;
++	}
++
++	if (rtw_set_802_11_infrastructure_mode(padapter, networkType, 0) == _FALSE) {
++
++		ret = -EPERM;
++		goto exit;
++
++	}
++
++	rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK);
++
++	if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE)
++		rtw_indicate_connect(padapter);
++
++exit:
++
++
++	return ret;
++
++}
++
++static int rtw_wx_get_mode(struct net_device *dev, struct iw_request_info *a,
++			   union iwreq_data *wrqu, char *b)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++
++
++
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
++		wrqu->mode = IW_MODE_INFRA;
++	else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
++		 (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
++
++		wrqu->mode = IW_MODE_ADHOC;
++	else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
++		wrqu->mode = IW_MODE_MASTER;
++	else if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE)
++		wrqu->mode = IW_MODE_MONITOR;
++	else
++		wrqu->mode = IW_MODE_AUTO;
++
++
++	return 0;
++
++}
++
++
++static int rtw_wx_set_pmkid(struct net_device *dev,
++			    struct iw_request_info *a,
++			    union iwreq_data *wrqu, char *extra)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u8          j, blInserted = _FALSE;
++	int         intReturn = _FALSE;
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	struct iw_pmksa  *pPMK = (struct iw_pmksa *) extra;
++	u8     strZeroMacAddress[ETH_ALEN] = { 0x00 };
++	u8     strIssueBssid[ETH_ALEN] = { 0x00 };
++
++#if 0
++	struct iw_pmksa {
++		__u32   cmd;
++		struct sockaddr bssid;
++		__u8    pmkid[IW_PMKID_LEN];   /* IW_PMKID_LEN=16 */
++	}
++	There are the BSSID information in the bssid.sa_data array.
++	If cmd is IW_PMKSA_FLUSH, it means the wpa_suppplicant wants to clear all the PMKID information.
++	If cmd is IW_PMKSA_ADD, it means the wpa_supplicant wants to add a PMKID / BSSID to driver.
++	If cmd is IW_PMKSA_REMOVE, it means the wpa_supplicant wants to remove a PMKID / BSSID from driver.
++#endif
++
++	_rtw_memcpy(strIssueBssid, pPMK->bssid.sa_data, ETH_ALEN);
++	if (pPMK->cmd == IW_PMKSA_ADD) {
++		RTW_INFO("[rtw_wx_set_pmkid] IW_PMKSA_ADD!\n");
++		if (_rtw_memcmp(strIssueBssid, strZeroMacAddress, ETH_ALEN) == _TRUE)
++			return intReturn ;
++		else
++			intReturn = _TRUE;
++		blInserted = _FALSE;
++
++		/* overwrite PMKID */
++		for (j = 0 ; j < NUM_PMKID_CACHE; j++) {
++			if (_rtw_memcmp(psecuritypriv->PMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) == _TRUE) {
++				/* BSSID is matched, the same AP => rewrite with new PMKID. */
++
++				RTW_INFO("[rtw_wx_set_pmkid] BSSID exists in the PMKList.\n");
++
++				_rtw_memcpy(psecuritypriv->PMKIDList[j].PMKID, pPMK->pmkid, IW_PMKID_LEN);
++				psecuritypriv->PMKIDList[j].bUsed = _TRUE;
++				psecuritypriv->PMKIDIndex = j + 1;
++				blInserted = _TRUE;
++				break;
++			}
++		}
++
++		if (!blInserted) {
++			/* Find a new entry */
++			RTW_INFO("[rtw_wx_set_pmkid] Use the new entry index = %d for this PMKID.\n",
++				 psecuritypriv->PMKIDIndex);
++
++			_rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, strIssueBssid, ETH_ALEN);
++			_rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, pPMK->pmkid, IW_PMKID_LEN);
++
++			psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].bUsed = _TRUE;
++			psecuritypriv->PMKIDIndex++ ;
++			if (psecuritypriv->PMKIDIndex == 16)
++				psecuritypriv->PMKIDIndex = 0;
++		}
++	} else if (pPMK->cmd == IW_PMKSA_REMOVE) {
++		RTW_INFO("[rtw_wx_set_pmkid] IW_PMKSA_REMOVE!\n");
++		intReturn = _TRUE;
++		for (j = 0 ; j < NUM_PMKID_CACHE; j++) {
++			if (_rtw_memcmp(psecuritypriv->PMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) == _TRUE) {
++				/* BSSID is matched, the same AP => Remove this PMKID information and reset it. */
++				_rtw_memset(psecuritypriv->PMKIDList[j].Bssid, 0x00, ETH_ALEN);
++				psecuritypriv->PMKIDList[j].bUsed = _FALSE;
++				break;
++			}
++		}
++	} else if (pPMK->cmd == IW_PMKSA_FLUSH) {
++		RTW_INFO("[rtw_wx_set_pmkid] IW_PMKSA_FLUSH!\n");
++		_rtw_memset(&psecuritypriv->PMKIDList[0], 0x00, sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);
++		psecuritypriv->PMKIDIndex = 0;
++		intReturn = _TRUE;
++	}
++	return intReturn ;
++}
++
++static int rtw_wx_get_sens(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra)
++{
++#ifdef CONFIG_PLATFORM_ROCKCHIPS
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++	/*
++	*  20110311 Commented by Jeff
++	*  For rockchip platform's wpa_driver_wext_get_rssi
++	*/
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++		/* wrqu->sens.value=-padapter->recvpriv.signal_strength; */
++		wrqu->sens.value = -padapter->recvpriv.rssi;
++		/* RTW_INFO("%s: %d\n", __FUNCTION__, wrqu->sens.value); */
++		wrqu->sens.fixed = 0; /* no auto select */
++	} else
++#endif
++	{
++		wrqu->sens.value = 0;
++		wrqu->sens.fixed = 0;	/* no auto select */
++		wrqu->sens.disabled = 1;
++	}
++	return 0;
++}
++
++static int rtw_wx_get_range(struct net_device *dev,
++			    struct iw_request_info *info,
++			    union iwreq_data *wrqu, char *extra)
++{
++	struct iw_range *range = (struct iw_range *)extra;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	u16 val;
++	int i;
++
++
++
++	wrqu->data.length = sizeof(*range);
++	_rtw_memset(range, 0, sizeof(*range));
++
++	/* Let's try to keep this struct in the same order as in
++	 * linux/include/wireless.h
++	 */
++
++	/* TODO: See what values we can set, and remove the ones we can't
++	 * set, or fill them with some default data.
++	 */
++
++	/* ~5 Mb/s real (802.11b) */
++	range->throughput = 5 * 1000 * 1000;
++
++	/* TODO: Not used in 802.11b?
++	*	range->min_nwid;	 Minimal NWID we are able to set  */
++	/* TODO: Not used in 802.11b?
++	*	range->max_nwid;	 Maximal NWID we are able to set  */
++
++	/* Old Frequency (backward compat - moved lower ) */
++	/*	range->old_num_channels;
++	 *	range->old_num_frequency;
++	 * 	range->old_freq[6];  Filler to keep "version" at the same offset  */
++
++	/* signal level threshold range */
++
++	/* Quality of link & SNR stuff */
++	/* Quality range (link, level, noise)
++	 * If the quality is absolute, it will be in the range [0 ; max_qual],
++	 * if the quality is dBm, it will be in the range [max_qual ; 0].
++	 * Don't forget that we use 8 bit arithmetics...
++	 *
++	 * If percentage range is 0~100
++	 * Signal strength dbm range logical is -100 ~ 0
++	 * but usually value is -90 ~ -20
++	 */
++	range->max_qual.qual = 100;
++#ifdef CONFIG_SIGNAL_DISPLAY_DBM
++	range->max_qual.level = (u8)-100;
++	range->max_qual.noise = (u8)-100;
++	range->max_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */
++	range->max_qual.updated |= IW_QUAL_DBM;
++#else /* !CONFIG_SIGNAL_DISPLAY_DBM */
++	/* percent values between 0 and 100. */
++	range->max_qual.level = 100;
++	range->max_qual.noise = 100;
++	range->max_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */
++#endif /* !CONFIG_SIGNAL_DISPLAY_DBM */
++
++	/* This should contain the average/typical values of the quality
++	 * indicator. This should be the threshold between a "good" and
++	 * a "bad" link (example : monitor going from green to orange).
++	 * Currently, user space apps like quality monitors don't have any
++	 * way to calibrate the measurement. With this, they can split
++	 * the range between 0 and max_qual in different quality level
++	 * (using a geometric subdivision centered on the average).
++	 * I expect that people doing the user space apps will feedback
++	 * us on which value we need to put in each driver... */
++	range->avg_qual.qual = 92; /* > 8% missed beacons is 'bad' */
++#ifdef CONFIG_SIGNAL_DISPLAY_DBM
++	/* TODO: Find real 'good' to 'bad' threshold value for RSSI */
++	range->avg_qual.level = (u8)-70;
++	range->avg_qual.noise = 0;
++	range->avg_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */
++	range->avg_qual.updated |= IW_QUAL_DBM;
++#else /* !CONFIG_SIGNAL_DISPLAY_DBM */
++	/* TODO: Find real 'good' to 'bad' threshol value for RSSI */
++	range->avg_qual.level = 30;
++	range->avg_qual.noise = 100;
++	range->avg_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */
++#endif /* !CONFIG_SIGNAL_DISPLAY_DBM */
++
++	range->num_bitrates = RATE_COUNT;
++
++	for (i = 0; i < RATE_COUNT && i < IW_MAX_BITRATES; i++)
++		range->bitrate[i] = rtw_rates[i];
++
++	range->min_frag = MIN_FRAG_THRESHOLD;
++	range->max_frag = MAX_FRAG_THRESHOLD;
++
++	range->pm_capa = 0;
++
++	range->we_version_compiled = WIRELESS_EXT;
++	range->we_version_source = 16;
++
++	/*	range->retry_capa;	 What retry options are supported
++	 *	range->retry_flags;	 How to decode max/min retry limit
++	 *	range->r_time_flags;	 How to decode max/min retry life
++	 *	range->min_retry;	 Minimal number of retries
++	 *	range->max_retry;	 Maximal number of retries
++	 *	range->min_r_time;	 Minimal retry lifetime
++	 *	range->max_r_time;	 Maximal retry lifetime  */
++
++	for (i = 0, val = 0; i < rfctl->max_chan_nums; i++) {
++
++		/* Include only legal frequencies for some countries */
++		if (rfctl->channel_set[i].ChannelNum != 0) {
++			range->freq[val].i = rfctl->channel_set[i].ChannelNum;
++			range->freq[val].m = rtw_ch2freq(rfctl->channel_set[i].ChannelNum) * 100000;
++			range->freq[val].e = 1;
++			val++;
++		}
++
++		if (val == IW_MAX_FREQUENCIES)
++			break;
++	}
++
++	range->num_channels = val;
++	range->num_frequency = val;
++
++	/* Commented by Albert 2009/10/13
++	 * The following code will proivde the security capability to network manager.
++	 * If the driver doesn't provide this capability to network manager,
++	 * the WPA/WPA2 routers can't be choosen in the network manager. */
++
++	/*
++	#define IW_SCAN_CAPA_NONE		0x00
++	#define IW_SCAN_CAPA_ESSID		0x01
++	#define IW_SCAN_CAPA_BSSID		0x02
++	#define IW_SCAN_CAPA_CHANNEL	0x04
++	#define IW_SCAN_CAPA_MODE		0x08
++	#define IW_SCAN_CAPA_RATE		0x10
++	#define IW_SCAN_CAPA_TYPE		0x20
++	#define IW_SCAN_CAPA_TIME		0x40
++	*/
++
++#if WIRELESS_EXT > 17
++	range->enc_capa = IW_ENC_CAPA_WPA | IW_ENC_CAPA_WPA2 |
++			  IW_ENC_CAPA_CIPHER_TKIP | IW_ENC_CAPA_CIPHER_CCMP;
++#endif
++
++#ifdef IW_SCAN_CAPA_ESSID /* WIRELESS_EXT > 21 */
++	range->scan_capa = IW_SCAN_CAPA_ESSID | IW_SCAN_CAPA_TYPE | IW_SCAN_CAPA_BSSID |
++		   IW_SCAN_CAPA_CHANNEL | IW_SCAN_CAPA_MODE | IW_SCAN_CAPA_RATE;
++#endif
++
++
++
++	return 0;
++
++}
++
++/* set bssid flow
++ * s1. rtw_set_802_11_infrastructure_mode()
++ * s2. rtw_set_802_11_authentication_mode()
++ * s3. set_802_11_encryption_mode()
++ * s4. rtw_set_802_11_bssid() */
++static int rtw_wx_set_wap(struct net_device *dev,
++			  struct iw_request_info *info,
++			  union iwreq_data *awrq,
++			  char *extra)
++{
++	_irqL	irqL;
++	uint ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct sockaddr *temp = (struct sockaddr *)awrq;
++	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	_list	*phead;
++	u8 *dst_bssid, *src_bssid;
++	_queue	*queue	= &(pmlmepriv->scanned_queue);
++	struct	wlan_network	*pnetwork = NULL;
++	NDIS_802_11_AUTHENTICATION_MODE	authmode;
++
++	/*
++	#ifdef CONFIG_CONCURRENT_MODE
++		if(padapter->adapter_type > PRIMARY_IFACE)
++		{
++			ret = -EINVAL;
++			goto exit;
++		}
++	#endif
++	*/
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING) == _TRUE) {
++		RTW_INFO("set bssid, but buddy_intf is under scanning or linking\n");
++
++		ret = -EINVAL;
++
++		goto exit;
++	}
++#endif
++
++	rtw_ps_deny(padapter, PS_DENY_JOIN);
++	if (_FAIL == rtw_pwr_wakeup(padapter)) {
++		ret = -1;
++		goto cancel_ps_deny;
++	}
++
++	if (!padapter->bup) {
++		ret = -1;
++		goto cancel_ps_deny;
++	}
++
++
++	if (temp->sa_family != ARPHRD_ETHER) {
++		ret = -EINVAL;
++		goto cancel_ps_deny;
++	}
++
++	authmode = padapter->securitypriv.ndisauthtype;
++	_enter_critical_bh(&queue->lock, &irqL);
++	phead = get_list_head(queue);
++	pmlmepriv->pscanned = get_next(phead);
++
++	while (1) {
++
++		if ((rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) == _TRUE) {
++#if 0
++			ret = -EINVAL;
++			goto cancel_ps_deny;
++
++			if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {
++				rtw_set_802_11_bssid(padapter, temp->sa_data);
++				goto cancel_ps_deny;
++			} else {
++				ret = -EINVAL;
++				goto cancel_ps_deny;
++			}
++#endif
++
++			break;
++		}
++
++		pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);
++
++		pmlmepriv->pscanned = get_next(pmlmepriv->pscanned);
++
++		dst_bssid = pnetwork->network.MacAddress;
++
++		src_bssid = temp->sa_data;
++
++		if ((_rtw_memcmp(dst_bssid, src_bssid, ETH_ALEN)) == _TRUE) {
++			if (!rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode, 0)) {
++				ret = -1;
++				_exit_critical_bh(&queue->lock, &irqL);
++				goto cancel_ps_deny;
++			}
++
++			break;
++		}
++
++	}
++	_exit_critical_bh(&queue->lock, &irqL);
++
++	rtw_set_802_11_authentication_mode(padapter, authmode);
++	/* set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */
++	if (rtw_set_802_11_bssid(padapter, temp->sa_data) == _FALSE) {
++		ret = -1;
++		goto cancel_ps_deny;
++	}
++
++cancel_ps_deny:
++	rtw_ps_deny_cancel(padapter, PS_DENY_JOIN);
++
++#ifdef CONFIG_CONCURRENT_MODE
++exit:
++#endif
++	return ret;
++}
++
++static int rtw_wx_get_wap(struct net_device *dev,
++			  struct iw_request_info *info,
++			  union iwreq_data *wrqu, char *extra)
++{
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	WLAN_BSSID_EX  *pcur_bss = &pmlmepriv->cur_network.network;
++
++	wrqu->ap_addr.sa_family = ARPHRD_ETHER;
++
++	_rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN);
++
++
++
++	if (((check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) == _TRUE) ||
++	    ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) ||
++	    ((check_fwstate(pmlmepriv, WIFI_AP_STATE)) == _TRUE))
++
++		_rtw_memcpy(wrqu->ap_addr.sa_data, pcur_bss->MacAddress, ETH_ALEN);
++	else
++		_rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN);
++
++
++	return 0;
++
++}
++
++static int rtw_wx_set_mlme(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra)
++{
++#if 0
++	/* SIOCSIWMLME data */
++	struct	iw_mlme {
++		__u16		cmd; /* IW_MLME_* */
++		__u16		reason_code;
++		struct sockaddr	addr;
++	};
++#endif
++
++	int ret = 0;
++	u16 reason;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct iw_mlme *mlme = (struct iw_mlme *) extra;
++
++
++	if (mlme == NULL)
++		return -1;
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	reason = cpu_to_le16(mlme->reason_code);
++
++
++	RTW_INFO("%s, cmd=%d, reason=%d\n", __FUNCTION__, mlme->cmd, reason);
++
++
++	switch (mlme->cmd) {
++	case IW_MLME_DEAUTH:
++		if (!rtw_set_802_11_disassociate(padapter))
++			ret = -1;
++		break;
++
++	case IW_MLME_DISASSOC:
++		if (!rtw_set_802_11_disassociate(padapter))
++			ret = -1;
++
++		break;
++
++	default:
++		return -EOPNOTSUPP;
++	}
++#ifdef CONFIG_RTW_REPEATER_SON
++	rtw_rson_do_disconnect(padapter);
++#endif
++	return ret;
++}
++
++static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a,
++			   union iwreq_data *wrqu, char *extra)
++{
++	u8 _status = _FALSE;
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	/*struct mlme_priv *pmlmepriv = &padapter->mlmepriv;*/
++	struct sitesurvey_parm parm;
++	u8 ssc_chk;
++#ifdef CONFIG_P2P
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++#endif /* CONFIG_P2P */
++
++#ifdef DBG_IOCTL
++	RTW_INFO("DBG_IOCTL %s:%d\n", __FUNCTION__, __LINE__);
++#endif
++
++#if 1
++	ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
++
++	#ifdef CONFIG_DOSCAN_IN_BUSYTRAFFIC
++	if ((ssc_chk != SS_ALLOW) && (ssc_chk != SS_DENY_BUSY_TRAFFIC))
++	#else
++	/* When Busy Traffic, driver do not site survey. So driver return success. */
++	/* wpa_supplicant will not issue SIOCSIWSCAN cmd again after scan timeout. */
++	/* modify by thomas 2011-02-22. */
++	if (ssc_chk != SS_ALLOW)
++	#endif
++	{
++		if (ssc_chk == SS_DENY_MP_MODE)
++			ret = -EPERM;
++		#ifdef DBG_LA_MODE
++		else if (ssc_chk == SS_DENY_LA_MODE)
++			ret = -EPERM;
++		#endif
++		else
++			indicate_wx_scan_complete_event(padapter);
++
++		goto exit;
++	} else
++		RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++	rtw_ps_deny(padapter, PS_DENY_SCAN);
++	if (_FAIL == rtw_pwr_wakeup(padapter)) {
++		ret = -1;
++		goto cancel_ps_deny;
++	}
++	if (!rtw_is_adapter_up(padapter)) {
++		ret = -1;
++		goto cancel_ps_deny;
++	}
++#else
++
++#ifdef CONFIG_MP_INCLUDED
++	if (rtw_mp_mode_check(padapter)) {
++		RTW_INFO("MP mode block Scan request\n");
++		ret = -EPERM;
++		goto exit;
++	}
++#endif
++	if (rtw_is_scan_deny(padapter)) {
++		indicate_wx_scan_complete_event(padapter);
++		goto exit;
++	}
++
++	rtw_ps_deny(padapter, PS_DENY_SCAN);
++	if (_FAIL == rtw_pwr_wakeup(padapter)) {
++		ret = -1;
++		goto cancel_ps_deny;
++	}
++
++	if (!rtw_is_adapter_up(padapter)) {
++		ret = -1;
++		goto cancel_ps_deny;
++	}
++
++#ifndef CONFIG_DOSCAN_IN_BUSYTRAFFIC
++	/* When Busy Traffic, driver do not site survey. So driver return success. */
++	/* wpa_supplicant will not issue SIOCSIWSCAN cmd again after scan timeout. */
++	/* modify by thomas 2011-02-22. */
++	if (rtw_mi_busy_traffic_check(padapter)) {
++		indicate_wx_scan_complete_event(padapter);
++		goto cancel_ps_deny;
++	}
++#endif
++#ifdef CONFIG_RTW_REPEATER_SON
++	if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) {
++		RTW_INFO(FUNC_ADPT_FMT" blocking scan for under rson scanning process\n", FUNC_ADPT_ARG(padapter));
++		indicate_wx_scan_complete_event(padapter);
++		goto cancel_ps_deny;
++	}
++#endif
++	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
++		RTW_INFO("AP mode process WPS\n");
++		indicate_wx_scan_complete_event(padapter);
++		goto cancel_ps_deny;
++	}
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING) == _TRUE) {
++		indicate_wx_scan_complete_event(padapter);
++		goto cancel_ps_deny;
++	}
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_buddy_check_fwstate(padapter,
++		       WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING | WIFI_UNDER_WPS)) {
++
++		indicate_wx_scan_complete_event(padapter);
++		goto cancel_ps_deny;
++	}
++#endif
++#endif
++
++#ifdef CONFIG_P2P
++	if (pwdinfo->p2p_state != P2P_STATE_NONE) {
++		rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++		rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);
++		rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_FULL);
++		rtw_free_network_queue(padapter, _TRUE);
++	}
++#endif /* CONFIG_P2P */
++
++#if WIRELESS_EXT >= 17
++	if (wrqu->data.length == sizeof(struct iw_scan_req)) {
++		struct iw_scan_req *req = (struct iw_scan_req *)extra;
++
++		if (wrqu->data.flags & IW_SCAN_THIS_ESSID) {
++			int len = min((int)req->essid_len, IW_ESSID_MAX_SIZE);
++
++			rtw_init_sitesurvey_parm(padapter, &parm);
++			_rtw_memcpy(&parm.ssid[0].Ssid, &req->essid, len);
++			parm.ssid[0].SsidLength = len;
++			parm.ssid_num = 1;
++
++			RTW_INFO("IW_SCAN_THIS_ESSID, ssid=%s, len=%d\n", req->essid, req->essid_len);
++
++			_status = rtw_set_802_11_bssid_list_scan(padapter, &parm);
++
++		} else if (req->scan_type == IW_SCAN_TYPE_PASSIVE)
++			RTW_INFO("rtw_wx_set_scan, req->scan_type == IW_SCAN_TYPE_PASSIVE\n");
++
++	} else
++#endif
++
++		if (wrqu->data.length >= WEXT_CSCAN_HEADER_SIZE
++		    && _rtw_memcmp(extra, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE
++		   ) {
++			int len = wrqu->data.length - WEXT_CSCAN_HEADER_SIZE;
++			char *pos = extra + WEXT_CSCAN_HEADER_SIZE;
++			char section;
++			char sec_len;
++			int ssid_index = 0;
++
++			/* RTW_INFO("%s COMBO_SCAN header is recognized\n", __FUNCTION__); */
++			rtw_init_sitesurvey_parm(padapter, &parm);
++
++			while (len >= 1) {
++				section = *(pos++);
++				len -= 1;
++
++				switch (section) {
++				case WEXT_CSCAN_SSID_SECTION:
++					/* RTW_INFO("WEXT_CSCAN_SSID_SECTION\n"); */
++					if (len < 1) {
++						len = 0;
++						break;
++					}
++
++					sec_len = *(pos++);
++					len -= 1;
++
++					if (sec_len > 0 && sec_len <= len) {
++
++						parm.ssid[ssid_index].SsidLength = sec_len;
++						_rtw_memcpy(&parm.ssid[ssid_index].Ssid, pos, sec_len);
++
++						/* RTW_INFO("%s COMBO_SCAN with specific parm.ssid:%s, %d\n", __FUNCTION__ */
++						/*	, parm.ssid[ssid_index].Ssid, parm.ssid[ssid_index].SsidLength); */
++						ssid_index++;
++					}
++
++					pos += sec_len;
++					len -= sec_len;
++					break;
++
++
++				case WEXT_CSCAN_CHANNEL_SECTION:
++					/* RTW_INFO("WEXT_CSCAN_CHANNEL_SECTION\n"); */
++					pos += 1;
++					len -= 1;
++					break;
++				case WEXT_CSCAN_ACTV_DWELL_SECTION:
++					/* RTW_INFO("WEXT_CSCAN_ACTV_DWELL_SECTION\n"); */
++					pos += 2;
++					len -= 2;
++					break;
++				case WEXT_CSCAN_PASV_DWELL_SECTION:
++					/* RTW_INFO("WEXT_CSCAN_PASV_DWELL_SECTION\n"); */
++					pos += 2;
++					len -= 2;
++					break;
++				case WEXT_CSCAN_HOME_DWELL_SECTION:
++					/* RTW_INFO("WEXT_CSCAN_HOME_DWELL_SECTION\n"); */
++					pos += 2;
++					len -= 2;
++					break;
++				case WEXT_CSCAN_TYPE_SECTION:
++					/* RTW_INFO("WEXT_CSCAN_TYPE_SECTION\n"); */
++					pos += 1;
++					len -= 1;
++					break;
++#if 0
++				case WEXT_CSCAN_NPROBE_SECTION:
++					RTW_INFO("WEXT_CSCAN_NPROBE_SECTION\n");
++					break;
++#endif
++
++				default:
++					/* RTW_INFO("Unknown CSCAN section %c\n", section); */
++					len = 0; /* stop parsing */
++				}
++				/* RTW_INFO("len:%d\n", len); */
++
++			}
++			parm.ssid_num = ssid_index;
++
++			/* jeff: it has still some scan paramater to parse, we only do this now... */
++			_status = rtw_set_802_11_bssid_list_scan(padapter, &parm);
++
++		} else
++
++			_status = rtw_set_802_11_bssid_list_scan(padapter, NULL);
++
++	if (_status == _FALSE)
++		ret = -1;
++
++cancel_ps_deny:
++	rtw_ps_deny_cancel(padapter, PS_DENY_SCAN);
++
++exit:
++#ifdef DBG_IOCTL
++	RTW_INFO("DBG_IOCTL %s:%d return %d\n", __FUNCTION__, __LINE__, ret);
++#endif
++
++	return ret;
++}
++
++static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a,
++			   union iwreq_data *wrqu, char *extra)
++{
++	_irqL	irqL;
++	_list					*plist, *phead;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	RT_CHANNEL_INFO *chset = rfctl->channel_set;
++	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	_queue				*queue	= &(pmlmepriv->scanned_queue);
++	struct	wlan_network	*pnetwork = NULL;
++	char *ev = extra;
++	char *stop = ev + wrqu->data.length;
++	u32 ret = 0;
++	u32 wait_for_surveydone;
++	sint wait_status;
++	u8 ch;
++
++#ifdef CONFIG_P2P
++	struct	wifidirect_info	*pwdinfo = &padapter->wdinfo;
++#endif /* CONFIG_P2P */
++
++
++#ifdef DBG_IOCTL
++	RTW_INFO("DBG_IOCTL %s:%d\n", __FUNCTION__, __LINE__);
++#endif
++
++	if (adapter_to_pwrctl(padapter)->brfoffbyhw && rtw_is_drv_stopped(padapter)) {
++		ret = -EINVAL;
++		goto exit;
++	}
++
++#ifdef CONFIG_P2P
++	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
++		wait_for_surveydone = 200;
++	else {
++		/*	P2P is disabled */
++		wait_for_surveydone = 100;
++	}
++#else
++	{
++		wait_for_surveydone = 100;
++	}
++#endif /* CONFIG_P2P */
++
++#if 1 /* Wireless Extension use EAGAIN to try */
++	wait_status = WIFI_UNDER_SURVEY
++#ifndef CONFIG_RTW_ANDROID
++		      | WIFI_UNDER_LINKING
++#endif
++		      ;
++
++	while (check_fwstate(pmlmepriv, wait_status) == _TRUE)
++		return -EAGAIN;
++#else
++	wait_status = WIFI_UNDER_SURVEY
++#ifndef CONFIG_RTW_ANDROID
++		      | WIFI_UNDER_LINKING
++#endif
++		      ;
++
++	while (check_fwstate(pmlmepriv, wait_status) == _TRUE) {
++		rtw_msleep_os(30);
++		cnt++;
++		if (cnt > wait_for_surveydone)
++			break;
++	}
++#endif
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++
++	while (1) {
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		if ((stop - ev) < SCAN_ITEM_SIZE) {
++			if(wrqu->data.length == MAX_SCAN_BUFFER_LEN){ /*max buffer len defined by iwlist*/
++				ret = 0;
++				RTW_INFO("%s: Scan results incomplete\n", __FUNCTION__);
++				break;
++			}
++			ret = -E2BIG;
++			break;
++		}
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++		ch = pnetwork->network.Configuration.DSConfig;
++
++		/* report network only if the current channel set contains the channel to which this network belongs */
++		if (rtw_chset_search_ch(chset, ch) >= 0
++			&& rtw_mlme_band_check(padapter, ch) == _TRUE
++			&& _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))
++			&& (!IS_DFS_SLAVE_WITH_RD(rfctl)
++				|| rtw_rfctl_dfs_domain_unknown(rfctl)
++				|| !rtw_chset_is_ch_non_ocp(chset, ch))
++		)
++			ev = translate_scan(padapter, a, pnetwork, ev, stop);
++
++		plist = get_next(plist);
++
++	}
++
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	wrqu->data.length = ev - extra;
++	wrqu->data.flags = 0;
++
++exit:
++
++
++#ifdef DBG_IOCTL
++	RTW_INFO("DBG_IOCTL %s:%d return %d\n", __FUNCTION__, __LINE__, ret);
++#endif
++
++	return ret ;
++
++}
++
++/* set ssid flow
++ * s1. rtw_set_802_11_infrastructure_mode()
++ * s2. set_802_11_authenticaion_mode()
++ * s3. set_802_11_encryption_mode()
++ * s4. rtw_set_802_11_ssid() */
++static int rtw_wx_set_essid(struct net_device *dev,
++			    struct iw_request_info *a,
++			    union iwreq_data *wrqu, char *extra)
++{
++	_irqL irqL;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	_queue *queue = &pmlmepriv->scanned_queue;
++	_list *phead;
++	struct wlan_network *pnetwork = NULL;
++	NDIS_802_11_AUTHENTICATION_MODE authmode;
++	NDIS_802_11_SSID ndis_ssid;
++	u8 *dst_ssid, *src_ssid;
++
++	uint ret = 0, len;
++
++
++#ifdef DBG_IOCTL
++	RTW_INFO("DBG_IOCTL %s:%d\n", __FUNCTION__, __LINE__);
++#endif
++#ifdef CONFIG_WEXT_DONT_JOIN_BYSSID
++	RTW_INFO("%s: CONFIG_WEXT_DONT_JOIN_BYSSID be defined!! only allow bssid joining\n", __func__);
++	return -EPERM;
++#endif
++
++#if WIRELESS_EXT <= 20
++	if ((wrqu->essid.length - 1) > IW_ESSID_MAX_SIZE) {
++#else
++	if (wrqu->essid.length > IW_ESSID_MAX_SIZE) {
++#endif
++		ret = -E2BIG;
++		goto exit;
++	}
++
++
++
++	rtw_ps_deny(padapter, PS_DENY_JOIN);
++	if (_FAIL == rtw_pwr_wakeup(padapter)) {
++		ret = -1;
++		goto cancel_ps_deny;
++	}
++
++	if (!padapter->bup) {
++		ret = -1;
++		goto cancel_ps_deny;
++	}
++
++	if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
++		ret = -1;
++		goto cancel_ps_deny;
++	}
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING)) {
++		RTW_INFO("set ssid, but buddy_intf is under scanning or linking\n");
++		ret = -EINVAL;
++		goto cancel_ps_deny;
++	}
++#endif
++	authmode = padapter->securitypriv.ndisauthtype;
++	RTW_INFO("=>%s\n", __FUNCTION__);
++	if (wrqu->essid.flags && wrqu->essid.length) {
++		/* Commented by Albert 20100519 */
++		/* We got the codes in "set_info" function of iwconfig source code. */
++		/*	========================================= */
++		/*	wrq.u.essid.length = strlen(essid) + 1; */
++		/*	if(we_kernel_version > 20) */
++		/*		wrq.u.essid.length--; */
++		/*	========================================= */
++		/*	That means, if the WIRELESS_EXT less than or equal to 20, the correct ssid len should subtract 1. */
++#if WIRELESS_EXT <= 20
++		len = ((wrqu->essid.length - 1) < IW_ESSID_MAX_SIZE) ? (wrqu->essid.length - 1) : IW_ESSID_MAX_SIZE;
++#else
++		len = (wrqu->essid.length < IW_ESSID_MAX_SIZE) ? wrqu->essid.length : IW_ESSID_MAX_SIZE;
++#endif
++
++		if (wrqu->essid.length != 33)
++			RTW_INFO("ssid=%s, len=%d\n", extra, wrqu->essid.length);
++
++		_rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID));
++		ndis_ssid.SsidLength = len;
++		_rtw_memcpy(ndis_ssid.Ssid, extra, len);
++		src_ssid = ndis_ssid.Ssid;
++
++		_enter_critical_bh(&queue->lock, &irqL);
++		phead = get_list_head(queue);
++		pmlmepriv->pscanned = get_next(phead);
++
++		while (1) {
++			if (rtw_end_of_queue_search(phead, pmlmepriv->pscanned) == _TRUE) {
++#if 0
++				if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {
++					rtw_set_802_11_ssid(padapter, &ndis_ssid);
++
++					goto cancel_ps_deny;
++				} else {
++					ret = -EINVAL;
++					goto cancel_ps_deny;
++				}
++#endif
++
++				break;
++			}
++
++			pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);
++
++			pmlmepriv->pscanned = get_next(pmlmepriv->pscanned);
++
++			dst_ssid = pnetwork->network.Ssid.Ssid;
++
++
++			if ((_rtw_memcmp(dst_ssid, src_ssid, ndis_ssid.SsidLength) == _TRUE) &&
++			    (pnetwork->network.Ssid.SsidLength == ndis_ssid.SsidLength)) {
++
++				if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {
++					if (pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode)
++						continue;
++				}
++
++				if (rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode, 0) == _FALSE) {
++					ret = -1;
++					_exit_critical_bh(&queue->lock, &irqL);
++					goto cancel_ps_deny;
++				}
++
++				break;
++			}
++		}
++		_exit_critical_bh(&queue->lock, &irqL);
++		rtw_set_802_11_authentication_mode(padapter, authmode);
++		/* set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */
++		if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) {
++			ret = -1;
++			goto cancel_ps_deny;
++		}
++	}
++
++cancel_ps_deny:
++	rtw_ps_deny_cancel(padapter, PS_DENY_JOIN);
++
++exit:
++	RTW_INFO("<=%s, ret %d\n", __FUNCTION__, ret);
++
++#ifdef DBG_IOCTL
++	RTW_INFO("DBG_IOCTL %s:%d return %d\n", __FUNCTION__, __LINE__, ret);
++#endif
++
++
++	return ret;
++}
++
++static int rtw_wx_get_essid(struct net_device *dev,
++			    struct iw_request_info *a,
++			    union iwreq_data *wrqu, char *extra)
++{
++	u32 len, ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	WLAN_BSSID_EX  *pcur_bss = &pmlmepriv->cur_network.network;
++
++
++
++	if ((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) ||
++	    (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
++		len = pcur_bss->Ssid.SsidLength;
++
++		wrqu->essid.length = len;
++
++		_rtw_memcpy(extra, pcur_bss->Ssid.Ssid, len);
++
++		wrqu->essid.flags = 1;
++	} else {
++		ret = -1;
++		goto exit;
++	}
++
++exit:
++
++
++	return ret;
++
++}
++
++static int rtw_wx_set_rate(struct net_device *dev,
++			   struct iw_request_info *a,
++			   union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++#if 0
++	int i;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u8	datarates[NumRates];
++	u32	target_rate = wrqu->bitrate.value;
++	u32	fixed = wrqu->bitrate.fixed;
++	u32	ratevalue = 0;
++	u8 mpdatarate[NumRates] = {11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0xff};
++
++
++
++	if (target_rate == -1) {
++		ratevalue = 11;
++		goto set_rate;
++	}
++	target_rate = target_rate / 100000;
++
++	switch (target_rate) {
++	case 10:
++		ratevalue = 0;
++		break;
++	case 20:
++		ratevalue = 1;
++		break;
++	case 55:
++		ratevalue = 2;
++		break;
++	case 60:
++		ratevalue = 3;
++		break;
++	case 90:
++		ratevalue = 4;
++		break;
++	case 110:
++		ratevalue = 5;
++		break;
++	case 120:
++		ratevalue = 6;
++		break;
++	case 180:
++		ratevalue = 7;
++		break;
++	case 240:
++		ratevalue = 8;
++		break;
++	case 360:
++		ratevalue = 9;
++		break;
++	case 480:
++		ratevalue = 10;
++		break;
++	case 540:
++		ratevalue = 11;
++		break;
++	default:
++		ratevalue = 11;
++		break;
++	}
++
++set_rate:
++
++	for (i = 0; i < NumRates; i++) {
++		if (ratevalue == mpdatarate[i]) {
++			datarates[i] = mpdatarate[i];
++			if (fixed == 0)
++				break;
++		} else
++			datarates[i] = 0xff;
++
++	}
++
++	if (rtw_setdatarate_cmd(padapter, datarates) != _SUCCESS) {
++		ret = -1;
++	}
++
++#endif
++	return ret;
++}
++
++static int rtw_wx_get_rate(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra)
++{
++	u16 max_rate = 0;
++
++	max_rate = rtw_get_cur_max_rate((_adapter *)rtw_netdev_priv(dev));
++
++	if (max_rate == 0)
++		return -EPERM;
++
++	wrqu->bitrate.fixed = 0;	/* no auto select */
++	wrqu->bitrate.value = max_rate * 100000;
++
++	return 0;
++}
++
++static int rtw_wx_set_rts(struct net_device *dev,
++			  struct iw_request_info *info,
++			  union iwreq_data *wrqu, char *extra)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++
++	if (wrqu->rts.disabled)
++		padapter->registrypriv.rts_thresh = 2347;
++	else {
++		if (wrqu->rts.value < 0 ||
++		    wrqu->rts.value > 2347)
++			return -EINVAL;
++
++		padapter->registrypriv.rts_thresh = wrqu->rts.value;
++	}
++
++	RTW_INFO("%s, rts_thresh=%d\n", __func__, padapter->registrypriv.rts_thresh);
++
++
++	return 0;
++
++}
++
++static int rtw_wx_get_rts(struct net_device *dev,
++			  struct iw_request_info *info,
++			  union iwreq_data *wrqu, char *extra)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++
++	RTW_INFO("%s, rts_thresh=%d\n", __func__, padapter->registrypriv.rts_thresh);
++
++	wrqu->rts.value = padapter->registrypriv.rts_thresh;
++	wrqu->rts.fixed = 0;	/* no auto select */
++	/* wrqu->rts.disabled = (wrqu->rts.value == DEFAULT_RTS_THRESHOLD); */
++
++
++	return 0;
++}
++
++static int rtw_wx_set_frag(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++
++	if (wrqu->frag.disabled)
++		padapter->xmitpriv.frag_len = MAX_FRAG_THRESHOLD;
++	else {
++		if (wrqu->frag.value < MIN_FRAG_THRESHOLD ||
++		    wrqu->frag.value > MAX_FRAG_THRESHOLD)
++			return -EINVAL;
++
++		padapter->xmitpriv.frag_len = wrqu->frag.value & ~0x1;
++	}
++
++	RTW_INFO("%s, frag_len=%d\n", __func__, padapter->xmitpriv.frag_len);
++
++
++	return 0;
++
++}
++
++static int rtw_wx_get_frag(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++
++	RTW_INFO("%s, frag_len=%d\n", __func__, padapter->xmitpriv.frag_len);
++
++	wrqu->frag.value = padapter->xmitpriv.frag_len;
++	wrqu->frag.fixed = 0;	/* no auto select */
++	/* wrqu->frag.disabled = (wrqu->frag.value == DEFAULT_FRAG_THRESHOLD); */
++
++
++	return 0;
++}
++
++static int rtw_wx_get_retry(struct net_device *dev,
++			    struct iw_request_info *info,
++			    union iwreq_data *wrqu, char *extra)
++{
++	/* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */
++
++
++	wrqu->retry.value = 7;
++	wrqu->retry.fixed = 0;	/* no auto select */
++	wrqu->retry.disabled = 1;
++
++	return 0;
++
++}
++
++#if 0
++	#define IW_ENCODE_INDEX		0x00FF	/* Token index (if needed) */
++	#define IW_ENCODE_FLAGS		0xFF00	/* Flags defined below */
++	#define IW_ENCODE_MODE		0xF000	/* Modes defined below */
++	#define IW_ENCODE_DISABLED	0x8000	/* Encoding disabled */
++	#define IW_ENCODE_ENABLED	0x0000	/* Encoding enabled */
++	#define IW_ENCODE_RESTRICTED	0x4000	/* Refuse non-encoded packets */
++	#define IW_ENCODE_OPEN		0x2000	/* Accept non-encoded packets */
++	#define IW_ENCODE_NOKEY		0x0800  /* Key is write only, so not present */
++	#define IW_ENCODE_TEMP		0x0400  /* Temporary key */
++	/*
++	iwconfig wlan0 key on->flags = 0x6001->maybe it means auto
++	iwconfig wlan0 key off->flags = 0x8800
++	iwconfig wlan0 key open->flags = 0x2800
++	iwconfig wlan0 key open 1234567890->flags = 0x2000
++	iwconfig wlan0 key restricted->flags = 0x4800
++	iwconfig wlan0 key open [3] 1234567890->flags = 0x2003
++	iwconfig wlan0 key restricted [2] 1234567890->flags = 0x4002
++	iwconfig wlan0 key open [3] -> flags = 0x2803
++	iwconfig wlan0 key restricted [2] -> flags = 0x4802
++	*/
++#endif
++
++static int rtw_wx_set_enc(struct net_device *dev,
++			  struct iw_request_info *info,
++			  union iwreq_data *wrqu, char *keybuf)
++{
++	u32 key, ret = 0;
++	u32 keyindex_provided;
++	NDIS_802_11_WEP	 wep;
++	NDIS_802_11_AUTHENTICATION_MODE authmode;
++
++	struct iw_point *erq = &(wrqu->encoding);
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	RTW_INFO("+rtw_wx_set_enc, flags=0x%x\n", erq->flags);
++
++	_rtw_memset(&wep, 0, sizeof(NDIS_802_11_WEP));
++
++	key = erq->flags & IW_ENCODE_INDEX;
++
++
++	if (erq->flags & IW_ENCODE_DISABLED) {
++		RTW_INFO("EncryptionDisabled\n");
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
++		padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
++		padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
++		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
++		authmode = Ndis802_11AuthModeOpen;
++		padapter->securitypriv.ndisauthtype = authmode;
++
++		goto exit;
++	}
++
++	if (key) {
++		if (key > WEP_KEYS)
++			return -EINVAL;
++		key--;
++		keyindex_provided = 1;
++	} else {
++		keyindex_provided = 0;
++		key = padapter->securitypriv.dot11PrivacyKeyIndex;
++		RTW_INFO("rtw_wx_set_enc, key=%d\n", key);
++	}
++
++	/* set authentication mode	 */
++	if (erq->flags & IW_ENCODE_OPEN) {
++		RTW_INFO("rtw_wx_set_enc():IW_ENCODE_OPEN\n");
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;/* Ndis802_11EncryptionDisabled; */
++
++#ifdef CONFIG_PLATFORM_MT53XX
++		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
++#else
++		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
++#endif
++
++		padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
++		padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
++		authmode = Ndis802_11AuthModeOpen;
++		padapter->securitypriv.ndisauthtype = authmode;
++	} else if (erq->flags & IW_ENCODE_RESTRICTED) {
++		RTW_INFO("rtw_wx_set_enc():IW_ENCODE_RESTRICTED\n");
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
++
++#ifdef CONFIG_PLATFORM_MT53XX
++		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
++#else
++		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Shared;
++#endif
++
++		padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_;
++		padapter->securitypriv.dot118021XGrpPrivacy = _WEP40_;
++		authmode = Ndis802_11AuthModeShared;
++		padapter->securitypriv.ndisauthtype = authmode;
++	} else {
++		RTW_INFO("rtw_wx_set_enc():erq->flags=0x%x\n", erq->flags);
++
++		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;/* Ndis802_11EncryptionDisabled; */
++		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
++		padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
++		padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
++		authmode = Ndis802_11AuthModeOpen;
++		padapter->securitypriv.ndisauthtype = authmode;
++	}
++
++	wep.KeyIndex = key;
++	if (erq->length > 0) {
++		wep.KeyLength = erq->length <= 5 ? 5 : 13;
++
++		wep.Length = wep.KeyLength + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial);
++	} else {
++		wep.KeyLength = 0 ;
++
++		if (keyindex_provided == 1) { /* set key_id only, no given KeyMaterial(erq->length==0). */
++			padapter->securitypriv.dot11PrivacyKeyIndex = key;
++
++			RTW_INFO("(keyindex_provided == 1), keyid=%d, key_len=%d\n", key, padapter->securitypriv.dot11DefKeylen[key]);
++
++			switch (padapter->securitypriv.dot11DefKeylen[key]) {
++			case 5:
++				padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_;
++				break;
++			case 13:
++				padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;
++				break;
++			default:
++				padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
++				break;
++			}
++
++			goto exit;
++
++		}
++
++	}
++
++	wep.KeyIndex |= 0x80000000;
++
++	_rtw_memcpy(wep.KeyMaterial, keybuf, wep.KeyLength);
++
++	if (rtw_set_802_11_add_wep(padapter, &wep) == _FALSE) {
++		if (rf_on == pwrpriv->rf_pwrstate)
++			ret = -EOPNOTSUPP;
++		goto exit;
++	}
++
++exit:
++
++
++	return ret;
++
++}
++
++static int rtw_wx_get_enc(struct net_device *dev,
++			  struct iw_request_info *info,
++			  union iwreq_data *wrqu, char *keybuf)
++{
++	uint key, ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct iw_point *erq = &(wrqu->encoding);
++	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++
++
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) != _TRUE) {
++		if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE) {
++			erq->length = 0;
++			erq->flags |= IW_ENCODE_DISABLED;
++			return 0;
++		}
++	}
++
++
++	key = erq->flags & IW_ENCODE_INDEX;
++
++	if (key) {
++		if (key > WEP_KEYS)
++			return -EINVAL;
++		key--;
++	} else
++		key = padapter->securitypriv.dot11PrivacyKeyIndex;
++
++	erq->flags = key + 1;
++
++	/* if(padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen) */
++	/* { */
++	/* erq->flags |= IW_ENCODE_OPEN; */
++	/* }	  */
++
++	switch (padapter->securitypriv.ndisencryptstatus) {
++	case Ndis802_11EncryptionNotSupported:
++	case Ndis802_11EncryptionDisabled:
++
++		erq->length = 0;
++		erq->flags |= IW_ENCODE_DISABLED;
++
++		break;
++
++	case Ndis802_11Encryption1Enabled:
++
++		erq->length = padapter->securitypriv.dot11DefKeylen[key];
++
++		if (erq->length) {
++			_rtw_memcpy(keybuf, padapter->securitypriv.dot11DefKey[key].skey, padapter->securitypriv.dot11DefKeylen[key]);
++
++			erq->flags |= IW_ENCODE_ENABLED;
++
++			if (padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen)
++				erq->flags |= IW_ENCODE_OPEN;
++			else if (padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeShared)
++				erq->flags |= IW_ENCODE_RESTRICTED;
++		} else {
++			erq->length = 0;
++			erq->flags |= IW_ENCODE_DISABLED;
++		}
++
++		break;
++
++	case Ndis802_11Encryption2Enabled:
++	case Ndis802_11Encryption3Enabled:
++
++		erq->length = 16;
++		erq->flags |= (IW_ENCODE_ENABLED | IW_ENCODE_OPEN | IW_ENCODE_NOKEY);
++
++		break;
++
++	default:
++		erq->length = 0;
++		erq->flags |= IW_ENCODE_DISABLED;
++
++		break;
++
++	}
++
++
++	return ret;
++
++}
++
++static int rtw_wx_get_power(struct net_device *dev,
++			    struct iw_request_info *info,
++			    union iwreq_data *wrqu, char *extra)
++{
++	/* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */
++
++	wrqu->power.value = 0;
++	wrqu->power.fixed = 0;	/* no auto select */
++	wrqu->power.disabled = 1;
++
++	return 0;
++
++}
++
++static int rtw_wx_set_gen_ie(struct net_device *dev,
++			     struct iw_request_info *info,
++			     union iwreq_data *wrqu, char *extra)
++{
++	int ret;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	ret = rtw_set_wpa_ie(padapter, extra, wrqu->data.length);
++
++	return ret;
++}
++
++static int rtw_wx_set_auth(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct iw_param *param = (struct iw_param *)&(wrqu->param);
++#ifdef CONFIG_WAPI_SUPPORT
++#ifndef CONFIG_IOCTL_CFG80211
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	u32 value = param->value;
++#endif
++#endif
++	int ret = 0;
++
++	switch (param->flags & IW_AUTH_INDEX) {
++
++	case IW_AUTH_WPA_VERSION:
++#ifdef CONFIG_WAPI_SUPPORT
++#ifndef CONFIG_IOCTL_CFG80211
++		padapter->wapiInfo.bWapiEnable = false;
++		if (value == IW_AUTH_WAPI_VERSION_1) {
++			padapter->wapiInfo.bWapiEnable = true;
++			psecuritypriv->dot11PrivacyAlgrthm = _SMS4_;
++			psecuritypriv->dot118021XGrpPrivacy = _SMS4_;
++			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;
++			pmlmeinfo->auth_algo = psecuritypriv->dot11AuthAlgrthm;
++			padapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN;
++			padapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN;
++		}
++#endif
++#endif
++		break;
++	case IW_AUTH_CIPHER_PAIRWISE:
++
++		break;
++	case IW_AUTH_CIPHER_GROUP:
++
++		break;
++	case IW_AUTH_KEY_MGMT:
++#ifdef CONFIG_WAPI_SUPPORT
++#ifndef CONFIG_IOCTL_CFG80211
++		RTW_INFO("rtw_wx_set_auth: IW_AUTH_KEY_MGMT case\n");
++		if (value == IW_AUTH_KEY_MGMT_WAPI_PSK)
++			padapter->wapiInfo.bWapiPSK = true;
++		else
++			padapter->wapiInfo.bWapiPSK = false;
++		RTW_INFO("rtw_wx_set_auth: IW_AUTH_KEY_MGMT bwapipsk %d\n", padapter->wapiInfo.bWapiPSK);
++#endif
++#endif
++		/*
++		 *  ??? does not use these parameters
++		 */
++		break;
++
++	case IW_AUTH_TKIP_COUNTERMEASURES: {
++		if (param->value) {
++			/* wpa_supplicant is enabling the tkip countermeasure. */
++			padapter->securitypriv.btkip_countermeasure = _TRUE;
++		} else {
++			/* wpa_supplicant is disabling the tkip countermeasure. */
++			padapter->securitypriv.btkip_countermeasure = _FALSE;
++		}
++		break;
++	}
++	case IW_AUTH_DROP_UNENCRYPTED: {
++		/* HACK:
++		 *
++		 * wpa_supplicant calls set_wpa_enabled when the driver
++		 * is loaded and unloaded, regardless of if WPA is being
++		 * used.  No other calls are made which can be used to
++		 * determine if encryption will be used or not prior to
++		 * association being expected.  If encryption is not being
++		 * used, drop_unencrypted is set to false, else true -- we
++		 * can use this to determine if the CAP_PRIVACY_ON bit should
++		 * be set.
++		 */
++
++		if (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption1Enabled) {
++			break;/* it means init value, or using wep, ndisencryptstatus = Ndis802_11Encryption1Enabled, */
++			/* then it needn't reset it; */
++		}
++
++		if (param->value) {
++			padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
++			padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
++			padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
++			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
++			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;
++		}
++
++		break;
++	}
++
++	case IW_AUTH_80211_AUTH_ALG:
++
++#if defined(CONFIG_RTW_ANDROID) || 1
++		/*
++		 *  It's the starting point of a link layer connection using wpa_supplicant
++		*/
++		if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) {
++			LeaveAllPowerSaveMode(padapter);
++			rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK);
++			RTW_INFO("%s...call rtw_indicate_disconnect\n ", __FUNCTION__);
++			rtw_indicate_disconnect(padapter, 0, _FALSE);
++			rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK);
++		}
++#endif
++
++
++		ret = wpa_set_auth_algs(dev, (u32)param->value);
++
++		break;
++
++	case IW_AUTH_WPA_ENABLED:
++
++		/* if(param->value) */
++		/* padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; */ /* 802.1x */
++		/* else */
++		/* padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; */ /* open system */
++
++		/* _disassociate(priv); */
++
++		break;
++
++	case IW_AUTH_RX_UNENCRYPTED_EAPOL:
++		/* ieee->ieee802_1x = param->value; */
++		break;
++
++	case IW_AUTH_PRIVACY_INVOKED:
++		/* ieee->privacy_invoked = param->value; */
++		break;
++
++#ifdef CONFIG_WAPI_SUPPORT
++#ifndef CONFIG_IOCTL_CFG80211
++	case IW_AUTH_WAPI_ENABLED:
++		break;
++#endif
++#endif
++
++	default:
++		return -EOPNOTSUPP;
++
++	}
++
++	return ret;
++
++}
++
++static int rtw_wx_set_enc_ext(struct net_device *dev,
++			      struct iw_request_info *info,
++			      union iwreq_data *wrqu, char *extra)
++{
++	char *alg_name;
++	u32 param_len;
++	struct ieee_param *param = NULL;
++	struct iw_point *pencoding = &wrqu->encoding;
++	struct iw_encode_ext *pext = (struct iw_encode_ext *)extra;
++	int ret = 0;
++
++	param_len = sizeof(struct ieee_param) + pext->key_len;
++	param = (struct ieee_param *)rtw_malloc(param_len);
++	if (param == NULL)
++		return -1;
++
++	_rtw_memset(param, 0, param_len);
++
++	param->cmd = IEEE_CMD_SET_ENCRYPTION;
++	_rtw_memset(param->sta_addr, 0xff, ETH_ALEN);
++
++
++	switch (pext->alg) {
++	case IW_ENCODE_ALG_NONE:
++		/* todo: remove key */
++		/* remove = 1;	 */
++		alg_name = "none";
++		break;
++	case IW_ENCODE_ALG_WEP:
++		alg_name = "WEP";
++		break;
++	case IW_ENCODE_ALG_TKIP:
++		alg_name = "TKIP";
++		break;
++	case IW_ENCODE_ALG_CCMP:
++		alg_name = "CCMP";
++		break;
++#ifdef CONFIG_IEEE80211W
++	case IW_ENCODE_ALG_AES_CMAC:
++		alg_name = "BIP";
++		break;
++#endif /* CONFIG_IEEE80211W */
++#ifdef CONFIG_WAPI_SUPPORT
++#ifndef CONFIG_IOCTL_CFG80211
++	case IW_ENCODE_ALG_SM4:
++		alg_name = "SMS4";
++		_rtw_memcpy(param->sta_addr, pext->addr.sa_data, ETH_ALEN);
++		RTW_INFO("rtw_wx_set_enc_ext: SMS4 case\n");
++		break;
++#endif
++#endif
++	default:
++		ret = -1;
++		goto exit;
++	}
++
++	strncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN);
++
++	if (pext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY)
++		param->u.crypt.set_tx = 1;
++
++	/* cliW: WEP does not have group key
++	 * just not checking GROUP key setting
++	 */
++	if ((pext->alg != IW_ENCODE_ALG_WEP) &&
++	    ((pext->ext_flags & IW_ENCODE_EXT_GROUP_KEY)
++#ifdef CONFIG_IEEE80211W
++	     || (pext->ext_flags & IW_ENCODE_ALG_AES_CMAC)
++#endif /* CONFIG_IEEE80211W */
++	    ))
++		param->u.crypt.set_tx = 0;
++
++	param->u.crypt.idx = (pencoding->flags & 0x00FF) - 1 ;
++
++	if (pext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) {
++#ifdef CONFIG_WAPI_SUPPORT
++#ifndef CONFIG_IOCTL_CFG80211
++		if (pext->alg == IW_ENCODE_ALG_SM4)
++			_rtw_memcpy(param->u.crypt.seq, pext->rx_seq, 16);
++		else
++#endif /* CONFIG_IOCTL_CFG80211 */
++#endif /* CONFIG_WAPI_SUPPORT */
++			_rtw_memcpy(param->u.crypt.seq, pext->rx_seq, 8);
++	}
++
++	if (pext->key_len) {
++		param->u.crypt.key_len = pext->key_len;
++		/* _rtw_memcpy(param + 1, pext + 1, pext->key_len); */
++		_rtw_memcpy(param->u.crypt.key, pext + 1, pext->key_len);
++	}
++
++	if (pencoding->flags & IW_ENCODE_DISABLED) {
++		/* todo: remove key */
++		/* remove = 1; */
++	}
++
++	ret =  wpa_set_encryption(dev, param, param_len);
++
++exit:
++	if (param)
++		rtw_mfree((u8 *)param, param_len);
++
++	return ret;
++}
++
++
++static int rtw_wx_get_nick(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra)
++{
++	/* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */
++	/* struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); */
++	/* struct security_priv *psecuritypriv = &padapter->securitypriv; */
++
++	if (extra) {
++		wrqu->data.length = 14;
++		wrqu->data.flags = 1;
++		_rtw_memcpy(extra, "<WIFI@REALTEK>", 14);
++	}
++
++	/* rtw_signal_process(pid, SIGUSR1); */ /* for test */
++
++	/* dump debug info here	 */
++#if 0
++	u32 dot11AuthAlgrthm;		/*  802.11 auth, could be open, shared, and 8021x */
++	u32 dot11PrivacyAlgrthm;	/*  This specify the privacy for shared auth. algorithm. */
++	u32 dot118021XGrpPrivacy;	/*  This specify the privacy algthm. used for Grp key */
++	u32 ndisauthtype;
++	u32 ndisencryptstatus;
++#endif
++
++	/* RTW_INFO("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n",  */
++	/*		psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, */
++	/*		psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); */
++
++	/* RTW_INFO("enc_alg=0x%x\n", psecuritypriv->dot11PrivacyAlgrthm); */
++	/* RTW_INFO("auth_type=0x%x\n", psecuritypriv->ndisauthtype); */
++	/* RTW_INFO("enc_type=0x%x\n", psecuritypriv->ndisencryptstatus); */
++
++#if 0
++	RTW_INFO("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210));
++	RTW_INFO("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608));
++	RTW_INFO("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280));
++	RTW_INFO("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284));
++	RTW_INFO("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288));
++
++	RTW_INFO("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664));
++
++
++	RTW_INFO("\n");
++
++	RTW_INFO("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430));
++	RTW_INFO("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438));
++
++	RTW_INFO("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440));
++
++	RTW_INFO("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458));
++
++	RTW_INFO("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484));
++	RTW_INFO("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488));
++
++	RTW_INFO("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444));
++	RTW_INFO("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448));
++	RTW_INFO("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c));
++	RTW_INFO("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450));
++#endif
++
++	return 0;
++
++}
++
++static int rtw_wx_read32(struct net_device *dev,
++			 struct iw_request_info *info,
++			 union iwreq_data *wrqu, char *extra)
++{
++	PADAPTER padapter;
++	struct iw_point *p;
++	u16 len;
++	u32 addr;
++	u32 data32;
++	u32 bytes;
++	u8 *ptmp;
++	int ret;
++
++
++	ret = 0;
++	padapter = (PADAPTER)rtw_netdev_priv(dev);
++	p = &wrqu->data;
++	len = p->length;
++	if (0 == len)
++		return -EINVAL;
++
++	ptmp = (u8 *)rtw_malloc(len);
++	if (NULL == ptmp)
++		return -ENOMEM;
++
++	if (copy_from_user(ptmp, p->pointer, len)) {
++		ret = -EFAULT;
++		goto exit;
++	}
++
++	bytes = 0;
++	addr = 0;
++	sscanf(ptmp, "%d,%x", &bytes, &addr);
++
++	switch (bytes) {
++	case 1:
++		data32 = rtw_read8(padapter, addr);
++		sprintf(extra, "0x%02X", data32);
++		break;
++	case 2:
++		data32 = rtw_read16(padapter, addr);
++		sprintf(extra, "0x%04X", data32);
++		break;
++	case 4:
++		data32 = rtw_read32(padapter, addr);
++		sprintf(extra, "0x%08X", data32);
++		break;
++
++	#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_SDIO_INDIRECT_ACCESS) && defined(DBG_SDIO_INDIRECT_ACCESS)
++	case 11:
++		data32 = rtw_sd_iread8(padapter, addr);
++		sprintf(extra, "0x%02X", data32);
++		break;
++	case 12:
++		data32 = rtw_sd_iread16(padapter, addr);
++		sprintf(extra, "0x%04X", data32);
++		break;
++	case 14:
++		data32 = rtw_sd_iread32(padapter, addr);
++		sprintf(extra, "0x%08X", data32);
++		break;
++	#endif
++	default:
++		RTW_INFO("%s: usage> read [bytes],[address(hex)]\n", __func__);
++		ret = -EINVAL;
++		goto exit;
++	}
++	RTW_INFO("%s: addr=0x%08X data=%s\n", __func__, addr, extra);
++
++exit:
++	rtw_mfree(ptmp, len);
++
++	return 0;
++}
++
++static int rtw_wx_write32(struct net_device *dev,
++			  struct iw_request_info *info,
++			  union iwreq_data *wrqu, char *extra)
++{
++	PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev);
++
++	u32 addr;
++	u32 data32;
++	u32 bytes;
++
++
++	bytes = 0;
++	addr = 0;
++	data32 = 0;
++	sscanf(extra, "%d,%x,%x", &bytes, &addr, &data32);
++
++	switch (bytes) {
++	case 1:
++		rtw_write8(padapter, addr, (u8)data32);
++		RTW_INFO("%s: addr=0x%08X data=0x%02X\n", __func__, addr, (u8)data32);
++		break;
++	case 2:
++		rtw_write16(padapter, addr, (u16)data32);
++		RTW_INFO("%s: addr=0x%08X data=0x%04X\n", __func__, addr, (u16)data32);
++		break;
++	case 4:
++		rtw_write32(padapter, addr, data32);
++		RTW_INFO("%s: addr=0x%08X data=0x%08X\n", __func__, addr, data32);
++		break;
++	default:
++		RTW_INFO("%s: usage> write [bytes],[address(hex)],[data(hex)]\n", __func__);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int rtw_wx_read_rf(struct net_device *dev,
++			  struct iw_request_info *info,
++			  union iwreq_data *wrqu, char *extra)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u32 path, addr, data32;
++
++
++	path = *(u32 *)extra;
++	addr = *((u32 *)extra + 1);
++	data32 = rtw_hal_read_rfreg(padapter, path, addr, 0xFFFFF);
++	/*	RTW_INFO("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32); */
++	/*
++	 * IMPORTANT!!
++	 * Only when wireless private ioctl is at odd order,
++	 * "extra" would be copied to user space.
++	 */
++	sprintf(extra, "0x%05x", data32);
++
++	return 0;
++}
++
++static int rtw_wx_write_rf(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u32 path, addr, data32;
++
++
++	path = *(u32 *)extra;
++	addr = *((u32 *)extra + 1);
++	data32 = *((u32 *)extra + 2);
++	/*	RTW_INFO("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32); */
++	rtw_hal_write_rfreg(padapter, path, addr, 0xFFFFF, data32);
++
++	return 0;
++}
++
++static int rtw_wx_priv_null(struct net_device *dev, struct iw_request_info *a,
++			    union iwreq_data *wrqu, char *b)
++{
++	return -1;
++}
++
++#ifdef CONFIG_RTW_80211K
++extern void rm_dbg_cmd(_adapter *padapter, char *s);
++static int rtw_wx_priv_rrm(struct net_device *dev, struct iw_request_info *a,
++			    union iwreq_data *wrqu, char *b)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u32 path, addr, data32;
++
++
++	rm_dbg_cmd(padapter, b);
++	wrqu->data.length = strlen(b);
++
++	return 0;
++}
++#endif
++
++static int dummy(struct net_device *dev, struct iw_request_info *a,
++		 union iwreq_data *wrqu, char *b)
++{
++	/* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);	 */
++	/* struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); */
++
++	/* RTW_INFO("cmd_code=%x, fwstate=0x%x\n", a->cmd, get_fwstate(pmlmepriv)); */
++
++	return -1;
++
++}
++
++static int rtw_wx_set_channel_plan(struct net_device *dev,
++				   struct iw_request_info *info,
++				   union iwreq_data *wrqu, char *extra)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u8 channel_plan_req = (u8)(*((int *)wrqu));
++
++	if (_SUCCESS != rtw_set_channel_plan(padapter, channel_plan_req))
++		return -EPERM;
++
++	return 0;
++}
++
++static int rtw_wx_set_mtk_wps_probe_ie(struct net_device *dev,
++				       struct iw_request_info *a,
++				       union iwreq_data *wrqu, char *b)
++{
++#ifdef CONFIG_PLATFORM_MT53XX
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++#endif
++	return 0;
++}
++
++static int rtw_wx_get_sensitivity(struct net_device *dev,
++				  struct iw_request_info *info,
++				  union iwreq_data *wrqu, char *buf)
++{
++#ifdef CONFIG_PLATFORM_MT53XX
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	/*	Modified by Albert 20110914 */
++	/*	This is in dbm format for MTK platform. */
++	wrqu->qual.level = padapter->recvpriv.rssi;
++	RTW_INFO(" level = %u\n",  wrqu->qual.level);
++#endif
++	return 0;
++}
++
++static int rtw_wx_set_mtk_wps_ie(struct net_device *dev,
++				 struct iw_request_info *info,
++				 union iwreq_data *wrqu, char *extra)
++{
++#ifdef CONFIG_PLATFORM_MT53XX
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	return rtw_set_wpa_ie(padapter, wrqu->data.pointer, wrqu->data.length);
++#else
++	return 0;
++#endif
++}
++
++#ifdef MP_IOCTL_HDL
++static void rtw_dbg_mode_hdl(_adapter *padapter, u32 id, u8 *pdata, u32 len)
++{
++	pRW_Reg	RegRWStruct;
++	struct rf_reg_param *prfreg;
++	u8 path;
++	u8 offset;
++	u32 value;
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	switch (id) {
++	case GEN_MP_IOCTL_SUBCODE(MP_START):
++		RTW_INFO("871x_driver is only for normal mode, can't enter mp mode\n");
++		break;
++	case GEN_MP_IOCTL_SUBCODE(READ_REG):
++		RegRWStruct = (pRW_Reg)pdata;
++		switch (RegRWStruct->width) {
++		case 1:
++			RegRWStruct->value = rtw_read8(padapter, RegRWStruct->offset);
++			break;
++		case 2:
++			RegRWStruct->value = rtw_read16(padapter, RegRWStruct->offset);
++			break;
++		case 4:
++			RegRWStruct->value = rtw_read32(padapter, RegRWStruct->offset);
++			break;
++		default:
++			break;
++		}
++
++		break;
++	case GEN_MP_IOCTL_SUBCODE(WRITE_REG):
++		RegRWStruct = (pRW_Reg)pdata;
++		switch (RegRWStruct->width) {
++		case 1:
++			rtw_write8(padapter, RegRWStruct->offset, (u8)RegRWStruct->value);
++			break;
++		case 2:
++			rtw_write16(padapter, RegRWStruct->offset, (u16)RegRWStruct->value);
++			break;
++		case 4:
++			rtw_write32(padapter, RegRWStruct->offset, (u32)RegRWStruct->value);
++			break;
++		default:
++			break;
++		}
++
++		break;
++	case GEN_MP_IOCTL_SUBCODE(READ_RF_REG):
++
++		prfreg = (struct rf_reg_param *)pdata;
++
++		path = (u8)prfreg->path;
++		offset = (u8)prfreg->offset;
++
++		value = rtw_hal_read_rfreg(padapter, path, offset, 0xffffffff);
++
++		prfreg->value = value;
++
++		break;
++	case GEN_MP_IOCTL_SUBCODE(WRITE_RF_REG):
++
++		prfreg = (struct rf_reg_param *)pdata;
++
++		path = (u8)prfreg->path;
++		offset = (u8)prfreg->offset;
++		value = prfreg->value;
++
++		rtw_hal_write_rfreg(padapter, path, offset, 0xffffffff, value);
++
++		break;
++	case GEN_MP_IOCTL_SUBCODE(TRIGGER_GPIO):
++		RTW_INFO("==> trigger gpio 0\n");
++		rtw_hal_set_hwreg(padapter, HW_VAR_TRIGGER_GPIO_0, 0);
++		break;
++#ifdef CONFIG_BT_COEXIST
++	case GEN_MP_IOCTL_SUBCODE(SET_DM_BT):
++		RTW_INFO("==> set dm_bt_coexist:%x\n", *(u8 *)pdata);
++		rtw_hal_set_hwreg(padapter, HW_VAR_BT_SET_COEXIST, pdata);
++		break;
++	case GEN_MP_IOCTL_SUBCODE(DEL_BA):
++		RTW_INFO("==> delete ba:%x\n", *(u8 *)pdata);
++		rtw_hal_set_hwreg(padapter, HW_VAR_BT_ISSUE_DELBA, pdata);
++		break;
++#endif
++#ifdef DBG_CONFIG_ERROR_DETECT
++	case GEN_MP_IOCTL_SUBCODE(GET_WIFI_STATUS):
++		*pdata = rtw_hal_sreset_get_wifi_status(padapter);
++		break;
++#endif
++
++	default:
++		break;
++	}
++
++}
++static int rtw_mp_ioctl_hdl(struct net_device *dev, struct iw_request_info *info,
++			    union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++	u32 BytesRead, BytesWritten, BytesNeeded;
++	struct oid_par_priv	oid_par;
++	struct mp_ioctl_handler	*phandler;
++	struct mp_ioctl_param	*poidparam;
++	uint status = 0;
++	u16 len;
++	u8 *pparmbuf = NULL, bset;
++	PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev);
++	struct iw_point *p = &wrqu->data;
++
++	/* RTW_INFO("+rtw_mp_ioctl_hdl\n"); */
++
++	/* mutex_lock(&ioctl_mutex); */
++
++	if ((!p->length) || (!p->pointer)) {
++		ret = -EINVAL;
++		goto _rtw_mp_ioctl_hdl_exit;
++	}
++
++	pparmbuf = NULL;
++	bset = (u8)(p->flags & 0xFFFF);
++	len = p->length;
++	pparmbuf = (u8 *)rtw_malloc(len);
++	if (pparmbuf == NULL) {
++		ret = -ENOMEM;
++		goto _rtw_mp_ioctl_hdl_exit;
++	}
++
++	if (copy_from_user(pparmbuf, p->pointer, len)) {
++		ret = -EFAULT;
++		goto _rtw_mp_ioctl_hdl_exit;
++	}
++
++	poidparam = (struct mp_ioctl_param *)pparmbuf;
++
++	if (poidparam->subcode >= MAX_MP_IOCTL_SUBCODE) {
++		ret = -EINVAL;
++		goto _rtw_mp_ioctl_hdl_exit;
++	}
++
++	/* RTW_INFO("%s: %d\n", __func__, poidparam->subcode); */
++#ifdef CONFIG_MP_INCLUDED
++	if (padapter->registrypriv.mp_mode == 1) {
++		phandler = mp_ioctl_hdl + poidparam->subcode;
++
++		if ((phandler->paramsize != 0) && (poidparam->len < phandler->paramsize)) {
++			ret = -EINVAL;
++			goto _rtw_mp_ioctl_hdl_exit;
++		}
++
++		if (phandler->handler) {
++			oid_par.adapter_context = padapter;
++			oid_par.oid = phandler->oid;
++			oid_par.information_buf = poidparam->data;
++			oid_par.information_buf_len = poidparam->len;
++			oid_par.dbg = 0;
++
++			BytesWritten = 0;
++			BytesNeeded = 0;
++
++			if (bset) {
++				oid_par.bytes_rw = &BytesRead;
++				oid_par.bytes_needed = &BytesNeeded;
++				oid_par.type_of_oid = SET_OID;
++			} else {
++				oid_par.bytes_rw = &BytesWritten;
++				oid_par.bytes_needed = &BytesNeeded;
++				oid_par.type_of_oid = QUERY_OID;
++			}
++
++			status = phandler->handler(&oid_par);
++
++			/* todo:check status, BytesNeeded, etc. */
++		} else {
++			RTW_INFO("rtw_mp_ioctl_hdl(): err!, subcode=%d, oid=%d, handler=%p\n",
++				poidparam->subcode, phandler->oid, phandler->handler);
++			ret = -EFAULT;
++			goto _rtw_mp_ioctl_hdl_exit;
++		}
++	} else
++#endif
++	{
++		rtw_dbg_mode_hdl(padapter, poidparam->subcode, poidparam->data, poidparam->len);
++	}
++
++	if (bset == 0x00) {/* query info */
++		if (copy_to_user(p->pointer, pparmbuf, len))
++			ret = -EFAULT;
++	}
++
++	if (status) {
++		ret = -EFAULT;
++		goto _rtw_mp_ioctl_hdl_exit;
++	}
++
++_rtw_mp_ioctl_hdl_exit:
++
++	if (pparmbuf)
++		rtw_mfree(pparmbuf, len);
++
++	/* mutex_unlock(&ioctl_mutex); */
++
++	return ret;
++}
++#endif /*MP_IOCTL_HDL*/
++static int rtw_get_ap_info(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++	u32 cnt = 0, wpa_ielen;
++	_irqL	irqL;
++	_list	*plist, *phead;
++	unsigned char *pbuf;
++	u8 bssid[ETH_ALEN];
++	char data[32];
++	struct wlan_network *pnetwork = NULL;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	_queue *queue = &(pmlmepriv->scanned_queue);
++	struct iw_point *pdata = &wrqu->data;
++
++	RTW_INFO("+rtw_get_aplist_info\n");
++
++	if (rtw_is_drv_stopped(padapter) || (pdata == NULL)) {
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	while ((check_fwstate(pmlmepriv, (WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING))) == _TRUE) {
++		rtw_msleep_os(30);
++		cnt++;
++		if (cnt > 100)
++			break;
++	}
++
++
++	/* pdata->length = 0; */ /* ?	 */
++	pdata->flags = 0;
++	if (pdata->length >= 32) {
++		if (copy_from_user(data, pdata->pointer, 32)) {
++			ret = -EINVAL;
++			goto exit;
++		}
++	} else {
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++
++	while (1) {
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++		/* if(hwaddr_aton_i(pdata->pointer, bssid)) */
++		if (hwaddr_aton_i(data, bssid)) {
++			RTW_INFO("Invalid BSSID '%s'.\n", (u8 *)data);
++			_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++			return -EINVAL;
++		}
++
++
++		if (_rtw_memcmp(bssid, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE) { /* BSSID match, then check if supporting wpa/wpa2 */
++			RTW_INFO("BSSID:" MAC_FMT "\n", MAC_ARG(bssid));
++
++			pbuf = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12);
++			if (pbuf && (wpa_ielen > 0)) {
++				pdata->flags = 1;
++				break;
++			}
++
++			pbuf = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12);
++			if (pbuf && (wpa_ielen > 0)) {
++				pdata->flags = 2;
++				break;
++			}
++
++		}
++
++		plist = get_next(plist);
++
++	}
++
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	if (pdata->length >= 34) {
++		if (copy_to_user((u8 *)pdata->pointer + 32, (u8 *)&pdata->flags, 1)) {
++			ret = -EINVAL;
++			goto exit;
++		}
++	}
++
++exit:
++
++	return ret;
++
++}
++
++static int rtw_set_pid(struct net_device *dev,
++		       struct iw_request_info *info,
++		       union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter *padapter = rtw_netdev_priv(dev);
++	int *pdata = (int *)wrqu;
++	int selector;
++
++	if (rtw_is_drv_stopped(padapter) || (pdata == NULL)) {
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	selector = *pdata;
++	if (selector < 3 && selector >= 0) {
++		padapter->pid[selector] = *(pdata + 1);
++#ifdef CONFIG_GLOBAL_UI_PID
++		ui_pid[selector] = *(pdata + 1);
++#endif
++		RTW_INFO("%s set pid[%d]=%d\n", __FUNCTION__, selector , padapter->pid[selector]);
++	} else
++		RTW_INFO("%s selector %d error\n", __FUNCTION__, selector);
++
++exit:
++
++	return ret;
++
++}
++
++static int rtw_wps_start(struct net_device *dev,
++			 struct iw_request_info *info,
++			 union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct iw_point *pdata = &wrqu->data;
++	u32   u32wps_start = 0;
++	unsigned int uintRet = 0;
++
++	if (RTW_CANNOT_RUN(padapter) || (NULL == pdata)) {
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	uintRet = copy_from_user((void *) &u32wps_start, pdata->pointer, 4);
++	if (u32wps_start == 0)
++		u32wps_start = *extra;
++
++	RTW_INFO("[%s] wps_start = %d\n", __FUNCTION__, u32wps_start);
++
++	if (u32wps_start == 1)   /* WPS Start */
++		rtw_led_control(padapter, LED_CTL_START_WPS);
++	else if (u32wps_start == 2)   /* WPS Stop because of wps success */
++		rtw_led_control(padapter, LED_CTL_STOP_WPS);
++	else if (u32wps_start == 3)   /* WPS Stop because of wps fail */
++		rtw_led_control(padapter, LED_CTL_STOP_WPS_FAIL);
++
++exit:
++
++	return ret;
++
++}
++
++#ifdef CONFIG_P2P
++static int rtw_wext_p2p_enable(struct net_device *dev,
++			       struct iw_request_info *info,
++			       union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	enum P2P_ROLE init_role = P2P_ROLE_DISABLE;
++
++	if (*extra == '0')
++		init_role = P2P_ROLE_DISABLE;
++	else if (*extra == '1')
++		init_role = P2P_ROLE_DEVICE;
++	else if (*extra == '2')
++		init_role = P2P_ROLE_CLIENT;
++	else if (*extra == '3')
++		init_role = P2P_ROLE_GO;
++
++	if (_FAIL == rtw_p2p_enable(padapter, init_role)) {
++		ret = -EFAULT;
++		goto exit;
++	}
++
++	/* set channel/bandwidth */
++	if (init_role != P2P_ROLE_DISABLE) {
++		u8 channel, ch_offset;
++		u16 bwmode;
++
++		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN)) {
++			/*	Stay at the listen state and wait for discovery. */
++			channel = pwdinfo->listen_channel;
++			pwdinfo->operating_channel = pwdinfo->listen_channel;
++			ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++			bwmode = CHANNEL_WIDTH_20;
++		}
++#ifdef CONFIG_CONCURRENT_MODE
++		else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) {
++
++			_set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_interval);
++
++			channel = rtw_mi_get_union_chan(padapter);
++			ch_offset = rtw_mi_get_union_offset(padapter);
++			bwmode = rtw_mi_get_union_bw(padapter);
++
++			pwdinfo->operating_channel = channel;
++		}
++#endif
++		else {
++			pwdinfo->operating_channel = pmlmeext->cur_channel;
++
++			channel = pwdinfo->operating_channel;
++			ch_offset = pmlmeext->cur_ch_offset;
++			bwmode = pmlmeext->cur_bwmode;
++		}
++
++		set_channel_bwmode(padapter, channel, ch_offset, bwmode);
++	}
++
++exit:
++	return ret;
++
++}
++
++static int rtw_p2p_set_go_nego_ssid(struct net_device *dev,
++				    struct iw_request_info *info,
++				    union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++
++	RTW_INFO("[%s] ssid = %s, len = %zu\n", __FUNCTION__, extra, strlen(extra));
++	_rtw_memcpy(pwdinfo->nego_ssid, extra, strlen(extra));
++	pwdinfo->nego_ssidlen = strlen(extra);
++
++	return ret;
++
++}
++
++
++static int rtw_p2p_set_intent(struct net_device *dev,
++			      struct iw_request_info *info,
++			      union iwreq_data *wrqu, char *extra)
++{
++	int							ret = 0;
++	_adapter						*padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info			*pwdinfo = &(padapter->wdinfo);
++	u8							intent = pwdinfo->intent;
++
++	extra[wrqu->data.length] = 0x00;
++
++	intent = rtw_atoi(extra);
++
++	if (intent <= 15)
++		pwdinfo->intent = intent;
++	else
++		ret = -1;
++
++	RTW_INFO("[%s] intent = %d\n", __FUNCTION__, intent);
++
++	return ret;
++
++}
++
++static int rtw_p2p_set_listen_ch(struct net_device *dev,
++				 struct iw_request_info *info,
++				 union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++	u8	listen_ch = pwdinfo->listen_channel;	/*	Listen channel number */
++
++	extra[wrqu->data.length] = 0x00;
++	listen_ch = rtw_atoi(extra);
++
++	if ((listen_ch == 1) || (listen_ch == 6) || (listen_ch == 11)) {
++		pwdinfo->listen_channel = listen_ch;
++		set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++	} else
++		ret = -1;
++
++	RTW_INFO("[%s] listen_ch = %d\n", __FUNCTION__, pwdinfo->listen_channel);
++
++	return ret;
++
++}
++
++static int rtw_p2p_set_op_ch(struct net_device *dev,
++			     struct iw_request_info *info,
++			     union iwreq_data *wrqu, char *extra)
++{
++	/*	Commented by Albert 20110524
++	 *	This function is used to set the operating channel if the driver will become the group owner */
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++	u8	op_ch = pwdinfo->operating_channel;	/*	Operating channel number */
++
++	extra[wrqu->data.length] = 0x00;
++
++	op_ch = (u8) rtw_atoi(extra);
++	if (op_ch > 0)
++		pwdinfo->operating_channel = op_ch;
++	else
++		ret = -1;
++
++	RTW_INFO("[%s] op_ch = %d\n", __FUNCTION__, pwdinfo->operating_channel);
++
++	return ret;
++
++}
++
++
++static int rtw_p2p_profilefound(struct net_device *dev,
++				struct iw_request_info *info,
++				union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++
++	/*	Comment by Albert 2010/10/13 */
++	/*	Input data format: */
++	/*	Ex:  0 */
++	/*	Ex:  1XX:XX:XX:XX:XX:XXYYSSID */
++	/*	0 => Reflush the profile record list. */
++	/*	1 => Add the profile list */
++	/*	XX:XX:XX:XX:XX:XX => peer's MAC Address ( ex: 00:E0:4C:00:00:01 ) */
++	/*	YY => SSID Length */
++	/*	SSID => SSID for persistence group */
++
++	RTW_INFO("[%s] In value = %s, len = %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
++
++
++	/*	The upper application should pass the SSID to driver by using this rtw_p2p_profilefound function. */
++	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
++		if (extra[0] == '0') {
++			/*	Remove all the profile information of wifidirect_info structure. */
++			_rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM);
++			pwdinfo->profileindex = 0;
++		} else {
++			if (pwdinfo->profileindex >= P2P_MAX_PERSISTENT_GROUP_NUM)
++				ret = -1;
++			else {
++				int jj, kk;
++
++				/*	Add this profile information into pwdinfo->profileinfo */
++				/*	Ex:  1XX:XX:XX:XX:XX:XXYYSSID */
++				for (jj = 0, kk = 1; jj < ETH_ALEN; jj++, kk += 3)
++					pwdinfo->profileinfo[pwdinfo->profileindex].peermac[jj] = key_2char2num(extra[kk], extra[kk + 1]);
++
++				/* pwdinfo->profileinfo[pwdinfo->profileindex].ssidlen = ( extra[18] - '0' ) * 10 + ( extra[19] - '0' ); */
++				/* _rtw_memcpy( pwdinfo->profileinfo[pwdinfo->profileindex].ssid, &extra[20], pwdinfo->profileinfo[pwdinfo->profileindex].ssidlen ); */
++				pwdinfo->profileindex++;
++			}
++		}
++	}
++
++	return ret;
++
++}
++
++static int rtw_p2p_setDN(struct net_device *dev,
++			 struct iw_request_info *info,
++			 union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++
++
++	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
++	_rtw_memset(pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN);
++	_rtw_memcpy(pwdinfo->device_name, extra, wrqu->data.length - 1);
++	pwdinfo->device_name_len = wrqu->data.length - 1;
++
++	return ret;
++
++}
++
++
++static int rtw_p2p_get_status(struct net_device *dev,
++			      struct iw_request_info *info,
++			      union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++	if (padapter->bShowGetP2PState) {
++		RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
++			pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2],
++			pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);
++	}
++
++	/*	Commented by Albert 2010/10/12 */
++	/*	Because of the output size limitation, I had removed the "Role" information. */
++	/*	About the "Role" information, we will use the new private IOCTL to get the "Role" information. */
++	sprintf(extra, "\n\nStatus=%.2d\n", rtw_p2p_state(pwdinfo));
++	wrqu->data.length = strlen(extra);
++
++	return ret;
++
++}
++
++/*	Commented by Albert 20110520
++ *	This function will return the config method description
++ *	This config method description will show us which config method the remote P2P device is intented to use
++ *	by sending the provisioning discovery request frame. */
++
++static int rtw_p2p_get_req_cm(struct net_device *dev,
++			      struct iw_request_info *info,
++			      union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++	sprintf(extra, "\n\nCM=%s\n", pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req);
++	wrqu->data.length = strlen(extra);
++	return ret;
++
++}
++
++
++static int rtw_p2p_get_role(struct net_device *dev,
++			    struct iw_request_info *info,
++			    union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++	RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
++		pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2],
++		pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);
++
++	sprintf(extra, "\n\nRole=%.2d\n", rtw_p2p_role(pwdinfo));
++	wrqu->data.length = strlen(extra);
++	return ret;
++
++}
++
++
++static int rtw_p2p_get_peer_ifaddr(struct net_device *dev,
++				   struct iw_request_info *info,
++				   union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++
++	RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
++		pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2],
++		pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);
++
++	sprintf(extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X",
++		pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2],
++		pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);
++	wrqu->data.length = strlen(extra);
++	return ret;
++
++}
++
++static int rtw_p2p_get_peer_devaddr(struct net_device *dev,
++				    struct iw_request_info *info,
++				    union iwreq_data *wrqu, char *extra)
++
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++	RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
++		pwdinfo->rx_prov_disc_info.peerDevAddr[0], pwdinfo->rx_prov_disc_info.peerDevAddr[1],
++		pwdinfo->rx_prov_disc_info.peerDevAddr[2], pwdinfo->rx_prov_disc_info.peerDevAddr[3],
++		pwdinfo->rx_prov_disc_info.peerDevAddr[4], pwdinfo->rx_prov_disc_info.peerDevAddr[5]);
++	sprintf(extra, "\n%.2X%.2X%.2X%.2X%.2X%.2X",
++		pwdinfo->rx_prov_disc_info.peerDevAddr[0], pwdinfo->rx_prov_disc_info.peerDevAddr[1],
++		pwdinfo->rx_prov_disc_info.peerDevAddr[2], pwdinfo->rx_prov_disc_info.peerDevAddr[3],
++		pwdinfo->rx_prov_disc_info.peerDevAddr[4], pwdinfo->rx_prov_disc_info.peerDevAddr[5]);
++	wrqu->data.length = strlen(extra);
++	return ret;
++
++}
++
++static int rtw_p2p_get_peer_devaddr_by_invitation(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra)
++
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++	RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
++		pwdinfo->p2p_peer_device_addr[0], pwdinfo->p2p_peer_device_addr[1],
++		pwdinfo->p2p_peer_device_addr[2], pwdinfo->p2p_peer_device_addr[3],
++		pwdinfo->p2p_peer_device_addr[4], pwdinfo->p2p_peer_device_addr[5]);
++	sprintf(extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X",
++		pwdinfo->p2p_peer_device_addr[0], pwdinfo->p2p_peer_device_addr[1],
++		pwdinfo->p2p_peer_device_addr[2], pwdinfo->p2p_peer_device_addr[3],
++		pwdinfo->p2p_peer_device_addr[4], pwdinfo->p2p_peer_device_addr[5]);
++	wrqu->data.length = strlen(extra);
++	return ret;
++
++}
++
++static int rtw_p2p_get_groupid(struct net_device *dev,
++			       struct iw_request_info *info,
++			       union iwreq_data *wrqu, char *extra)
++
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++	sprintf(extra, "\n%.2X:%.2X:%.2X:%.2X:%.2X:%.2X %s",
++		pwdinfo->groupid_info.go_device_addr[0], pwdinfo->groupid_info.go_device_addr[1],
++		pwdinfo->groupid_info.go_device_addr[2], pwdinfo->groupid_info.go_device_addr[3],
++		pwdinfo->groupid_info.go_device_addr[4], pwdinfo->groupid_info.go_device_addr[5],
++		pwdinfo->groupid_info.ssid);
++	wrqu->data.length = strlen(extra);
++	return ret;
++
++}
++
++static int rtw_p2p_get_op_ch(struct net_device *dev,
++			     struct iw_request_info *info,
++			     union iwreq_data *wrqu, char *extra)
++
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++
++	RTW_INFO("[%s] Op_ch = %02x\n", __FUNCTION__, pwdinfo->operating_channel);
++
++	sprintf(extra, "\n\nOp_ch=%.2d\n", pwdinfo->operating_channel);
++	wrqu->data.length = strlen(extra);
++	return ret;
++
++}
++
++static int rtw_p2p_get_wps_configmethod(struct net_device *dev,
++					struct iw_request_info *info,
++			union iwreq_data *wrqu, char *extra, char *subcmd)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u8 peerMAC[ETH_ALEN] = { 0x00 };
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	_irqL irqL;
++	_list *plist, *phead;
++	_queue *queue = &(pmlmepriv->scanned_queue);
++	struct wlan_network *pnetwork = NULL;
++	u8 blnMatch = 0;
++	u16	attr_content = 0;
++	uint attr_contentlen = 0;
++	u8	attr_content_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };
++
++	/*	Commented by Albert 20110727 */
++	/*	The input data is the MAC address which the application wants to know its WPS config method. */
++	/*	After knowing its WPS config method, the application can decide the config method for provisioning discovery. */
++	/*	Format: iwpriv wlanx p2p_get_wpsCM 00:E0:4C:00:00:05 */
++
++	RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd);
++
++	macstr2num(peerMAC, subcmd);
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++
++	while (1) {
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
++			u8 *wpsie;
++			uint	wpsie_len = 0;
++
++			/*	The mac address is matched. */
++
++			wpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]);
++			if (wpsie) {
++				rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_CONF_METHOD, (u8 *)&attr_content, &attr_contentlen);
++				if (attr_contentlen) {
++					attr_content = be16_to_cpu(attr_content);
++					sprintf(attr_content_str, "\n\nM=%.4d", attr_content);
++					blnMatch = 1;
++				}
++			}
++
++			break;
++		}
++
++		plist = get_next(plist);
++
++	}
++
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	if (!blnMatch)
++		sprintf(attr_content_str, "\n\nM=0000");
++
++	wrqu->data.length = strlen(attr_content_str);
++	_rtw_memcpy(extra, attr_content_str, wrqu->data.length);
++
++	return ret;
++
++}
++
++#ifdef CONFIG_WFD
++static int rtw_p2p_get_peer_wfd_port(struct net_device *dev,
++				     struct iw_request_info *info,
++				     union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++	RTW_INFO("[%s] p2p_state = %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo));
++
++	sprintf(extra, "\n\nPort=%d\n", pwdinfo->wfd_info->peer_rtsp_ctrlport);
++	RTW_INFO("[%s] remote port = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_rtsp_ctrlport);
++
++	wrqu->data.length = strlen(extra);
++	return ret;
++
++}
++
++static int rtw_p2p_get_peer_wfd_preferred_connection(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++	sprintf(extra, "\n\nwfd_pc=%d\n", pwdinfo->wfd_info->wfd_pc);
++	RTW_INFO("[%s] wfd_pc = %d\n", __FUNCTION__, pwdinfo->wfd_info->wfd_pc);
++
++	wrqu->data.length = strlen(extra);
++	pwdinfo->wfd_info->wfd_pc = _FALSE;	/*	Reset the WFD preferred connection to P2P */
++	return ret;
++
++}
++
++static int rtw_p2p_get_peer_wfd_session_available(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++	sprintf(extra, "\n\nwfd_sa=%d\n", pwdinfo->wfd_info->peer_session_avail);
++	RTW_INFO("[%s] wfd_sa = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_session_avail);
++
++	wrqu->data.length = strlen(extra);
++	pwdinfo->wfd_info->peer_session_avail = _TRUE;	/*	Reset the WFD session available */
++	return ret;
++
++}
++#endif /* CONFIG_WFD */
++
++static int rtw_p2p_get_go_device_address(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra, char *subcmd)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u8 peerMAC[ETH_ALEN] = { 0x00 };
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	_irqL irqL;
++	_list *plist, *phead;
++	_queue *queue	= &(pmlmepriv->scanned_queue);
++	struct wlan_network *pnetwork = NULL;
++	u8 blnMatch = 0;
++	u8 *p2pie;
++	uint p2pielen = 0, attr_contentlen = 0;
++	u8 attr_content[100] = { 0x00 };
++	u8 go_devadd_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };
++
++	/*	Commented by Albert 20121209 */
++	/*	The input data is the GO's interface address which the application wants to know its device address. */
++	/*	Format: iwpriv wlanx p2p_get2 go_devadd=00:E0:4C:00:00:05 */
++
++	RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd);
++
++	macstr2num(peerMAC, subcmd);
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++
++	while (1) {
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
++			/*	Commented by Albert 2011/05/18 */
++			/*	Match the device address located in the P2P IE */
++			/*	This is for the case that the P2P device address is not the same as the P2P interface address. */
++
++			p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);
++			if (p2pie) {
++				while (p2pie) {
++					/*	The P2P Device ID attribute is included in the Beacon frame. */
++					/*	The P2P Device Info attribute is included in the probe response frame. */
++
++					_rtw_memset(attr_content, 0x00, 100);
++					if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) {
++						/*	Handle the P2P Device ID attribute of Beacon first */
++						blnMatch = 1;
++						break;
++
++					} else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) {
++						/*	Handle the P2P Device Info attribute of probe response */
++						blnMatch = 1;
++						break;
++					}
++
++					/* Get the next P2P IE */
++					p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen);
++				}
++			}
++		}
++
++		plist = get_next(plist);
++
++	}
++
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	if (!blnMatch)
++		sprintf(go_devadd_str, "\n\ndev_add=NULL");
++	else {
++		sprintf(go_devadd_str, "\n\ndev_add=%.2X:%.2X:%.2X:%.2X:%.2X:%.2X",
++			attr_content[0], attr_content[1], attr_content[2], attr_content[3], attr_content[4], attr_content[5]);
++	}
++
++	wrqu->data.length = strlen(go_devadd_str);
++	_rtw_memcpy(extra, go_devadd_str, wrqu->data.length);
++
++	return ret;
++
++}
++
++static int rtw_p2p_get_device_type(struct net_device *dev,
++				   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra, char *subcmd)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u8 peerMAC[ETH_ALEN] = { 0x00 };
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	_irqL irqL;
++	_list *plist, *phead;
++	_queue *queue = &(pmlmepriv->scanned_queue);
++	struct wlan_network *pnetwork = NULL;
++	u8 blnMatch = 0;
++	u8 dev_type[8] = { 0x00 };
++	uint dev_type_len = 0;
++	u8 dev_type_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };    /* +9 is for the str "dev_type=", we have to clear it at wrqu->data.pointer */
++
++	/*	Commented by Albert 20121209 */
++	/*	The input data is the MAC address which the application wants to know its device type. */
++	/*	Such user interface could know the device type. */
++	/*	Format: iwpriv wlanx p2p_get2 dev_type=00:E0:4C:00:00:05 */
++
++	RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd);
++
++	macstr2num(peerMAC, subcmd);
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++
++	while (1) {
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
++			u8 *wpsie;
++			uint	wpsie_len = 0;
++
++			/*	The mac address is matched. */
++
++			wpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]);
++			if (wpsie) {
++				rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_PRIMARY_DEV_TYPE, dev_type, &dev_type_len);
++				if (dev_type_len) {
++					u16	type = 0;
++
++					_rtw_memcpy(&type, dev_type, 2);
++					type = be16_to_cpu(type);
++					sprintf(dev_type_str, "\n\nN=%.2d", type);
++					blnMatch = 1;
++				}
++			}
++			break;
++		}
++
++		plist = get_next(plist);
++
++	}
++
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	if (!blnMatch)
++		sprintf(dev_type_str, "\n\nN=00");
++
++	wrqu->data.length = strlen(dev_type_str);
++	_rtw_memcpy(extra, dev_type_str, wrqu->data.length);
++
++	return ret;
++
++}
++
++static int rtw_p2p_get_device_name(struct net_device *dev,
++				   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra, char *subcmd)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u8 peerMAC[ETH_ALEN] = { 0x00 };
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	_irqL irqL;
++	_list *plist, *phead;
++	_queue *queue = &(pmlmepriv->scanned_queue);
++	struct wlan_network *pnetwork = NULL;
++	u8 blnMatch = 0;
++	u8 dev_name[WPS_MAX_DEVICE_NAME_LEN] = { 0x00 };
++	uint dev_len = 0;
++	u8 dev_name_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };
++
++	/*	Commented by Albert 20121225 */
++	/*	The input data is the MAC address which the application wants to know its device name. */
++	/*	Such user interface could show peer device's device name instead of ssid. */
++	/*	Format: iwpriv wlanx p2p_get2 devN=00:E0:4C:00:00:05 */
++
++	RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd);
++
++	macstr2num(peerMAC, subcmd);
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++
++	while (1) {
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
++			u8 *wpsie;
++			uint	wpsie_len = 0;
++
++			/*	The mac address is matched. */
++
++			wpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]);
++			if (wpsie) {
++				rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_DEVICE_NAME, dev_name, &dev_len);
++				if (dev_len) {
++					sprintf(dev_name_str, "\n\nN=%s", dev_name);
++					blnMatch = 1;
++				}
++			}
++			break;
++		}
++
++		plist = get_next(plist);
++
++	}
++
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	if (!blnMatch)
++		sprintf(dev_name_str, "\n\nN=0000");
++
++	wrqu->data.length = strlen(dev_name_str);
++	_rtw_memcpy(extra, dev_name_str, wrqu->data.length);
++
++	return ret;
++
++}
++
++static int rtw_p2p_get_invitation_procedure(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra, char *subcmd)
++{
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u8 peerMAC[ETH_ALEN] = { 0x00 };
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	_irqL irqL;
++	_list *plist, *phead;
++	_queue *queue	= &(pmlmepriv->scanned_queue);
++	struct wlan_network *pnetwork = NULL;
++	u8 blnMatch = 0;
++	u8 *p2pie;
++	uint p2pielen = 0, attr_contentlen = 0;
++	u8 attr_content[2] = { 0x00 };
++	u8 inv_proc_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };
++
++	/*	Commented by Ouden 20121226 */
++	/*	The application wants to know P2P initation procedure is support or not. */
++	/*	Format: iwpriv wlanx p2p_get2 InvProc=00:E0:4C:00:00:05 */
++
++	RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd);
++
++	macstr2num(peerMAC, subcmd);
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++
++	while (1) {
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
++			/*	Commented by Albert 20121226 */
++			/*	Match the device address located in the P2P IE */
++			/*	This is for the case that the P2P device address is not the same as the P2P interface address. */
++
++			p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);
++			if (p2pie) {
++				while (p2pie) {
++					/* _rtw_memset( attr_content, 0x00, 2); */
++					if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_CAPABILITY, attr_content, &attr_contentlen)) {
++						/*	Handle the P2P capability attribute */
++						blnMatch = 1;
++						break;
++
++					}
++
++					/* Get the next P2P IE */
++					p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen);
++				}
++			}
++		}
++
++		plist = get_next(plist);
++
++	}
++
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	if (!blnMatch)
++		sprintf(inv_proc_str, "\nIP=-1");
++	else {
++		if ((attr_content[0] & 0x20) == 0x20)
++			sprintf(inv_proc_str, "\nIP=1");
++		else
++			sprintf(inv_proc_str, "\nIP=0");
++	}
++
++	wrqu->data.length = strlen(inv_proc_str);
++	_rtw_memcpy(extra, inv_proc_str, wrqu->data.length);
++
++	return ret;
++
++}
++
++static int rtw_p2p_connect(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter				*padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++	u8					peerMAC[ETH_ALEN] = { 0x00 };
++	int					jj, kk;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	_irqL				irqL;
++	_list					*plist, *phead;
++	_queue				*queue	= &(pmlmepriv->scanned_queue);
++	struct	wlan_network	*pnetwork = NULL;
++	uint					uintPeerChannel = 0;
++
++	/*	Commented by Albert 20110304 */
++	/*	The input data contains two informations. */
++	/*	1. First information is the MAC address which wants to formate with */
++	/*	2. Second information is the WPS PINCode or "pbc" string for push button method */
++	/*	Format: 00:E0:4C:00:00:05 */
++	/*	Format: 00:E0:4C:00:00:05 */
++
++	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
++
++	if (pwdinfo->p2p_state == P2P_STATE_NONE) {
++		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
++		return ret;
++	}
++
++	if (pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO)
++		return -1;
++
++	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
++		peerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]);
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++
++	while (1) {
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
++			if (pnetwork->network.Configuration.DSConfig != 0)
++				uintPeerChannel = pnetwork->network.Configuration.DSConfig;
++			else if (pwdinfo->nego_req_info.peer_ch != 0)
++				uintPeerChannel = pnetwork->network.Configuration.DSConfig = pwdinfo->nego_req_info.peer_ch;
++			else {
++				/* Unexpected case */
++				uintPeerChannel = 0;
++				RTW_INFO("%s  uintPeerChannel = 0\n", __func__);
++			}
++			break;
++		}
++
++		plist = get_next(plist);
++
++	}
++
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	if (uintPeerChannel) {
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_check_status(padapter, MI_LINKED))
++			_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);
++#endif /* CONFIG_CONCURRENT_MODE */
++
++		_rtw_memset(&pwdinfo->nego_req_info, 0x00, sizeof(struct tx_nego_req_info));
++		_rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info));
++
++		pwdinfo->nego_req_info.peer_channel_num[0] = uintPeerChannel;
++		_rtw_memcpy(pwdinfo->nego_req_info.peerDevAddr, pnetwork->network.MacAddress, ETH_ALEN);
++		pwdinfo->nego_req_info.benable = _TRUE;
++
++		_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
++		if (rtw_p2p_state(pwdinfo) != P2P_STATE_GONEGO_OK) {
++			/*	Restore to the listen state if the current p2p state is not nego OK */
++			rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
++		}
++
++		rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING);
++
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_check_status(padapter, MI_LINKED)) {
++			u8 union_ch = rtw_mi_get_union_chan(padapter);
++			u8 union_bw = rtw_mi_get_union_bw(padapter);
++			u8 union_offset = rtw_mi_get_union_offset(padapter);
++
++			set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
++			rtw_leave_opch(padapter);
++		}
++#endif /* CONFIG_CONCURRENT_MODE */
++
++		RTW_INFO("[%s] Start PreTx Procedure!\n", __FUNCTION__);
++		_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_check_status(padapter, MI_LINKED))
++			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_GO_NEGO_TIMEOUT);
++		else
++			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT);
++#else
++		_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT);
++#endif /* CONFIG_CONCURRENT_MODE		 */
++
++	} else {
++		RTW_INFO("[%s] Not Found in Scanning Queue~\n", __FUNCTION__);
++		ret = -1;
++	}
++
++	return ret;
++}
++
++static int rtw_p2p_invite_req(struct net_device *dev,
++			      struct iw_request_info *info,
++			      union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter					*padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info		*pwdinfo = &(padapter->wdinfo);
++	int						jj, kk;
++	struct mlme_priv			*pmlmepriv = &padapter->mlmepriv;
++	_list						*plist, *phead;
++	_queue					*queue	= &(pmlmepriv->scanned_queue);
++	struct	wlan_network		*pnetwork = NULL;
++	uint						uintPeerChannel = 0;
++	u8						attr_content[50] = { 0x00 };
++	u8						*p2pie;
++	uint						p2pielen = 0, attr_contentlen = 0;
++	_irqL					irqL;
++	struct tx_invite_req_info	*pinvite_req_info = &pwdinfo->invitereq_info;
++
++	/*	Commented by Albert 20120321 */
++	/*	The input data contains two informations. */
++	/*	1. First information is the P2P device address which you want to send to.	 */
++	/*	2. Second information is the group id which combines with GO's mac address, space and GO's ssid. */
++	/*	Command line sample: iwpriv wlan0 p2p_set invite="00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy" */
++	/*	Format: 00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy */
++
++	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
++
++	if (wrqu->data.length <=  37) {
++		RTW_INFO("[%s] Wrong format!\n", __FUNCTION__);
++		return ret;
++	}
++
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
++		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
++		return ret;
++	} else {
++		/*	Reset the content of struct tx_invite_req_info */
++		pinvite_req_info->benable = _FALSE;
++		_rtw_memset(pinvite_req_info->go_bssid, 0x00, ETH_ALEN);
++		_rtw_memset(pinvite_req_info->go_ssid, 0x00, WLAN_SSID_MAXLEN);
++		pinvite_req_info->ssidlen = 0x00;
++		pinvite_req_info->operating_ch = pwdinfo->operating_channel;
++		_rtw_memset(pinvite_req_info->peer_macaddr, 0x00, ETH_ALEN);
++		pinvite_req_info->token = 3;
++	}
++
++	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
++		pinvite_req_info->peer_macaddr[jj] = key_2char2num(extra[kk], extra[kk + 1]);
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++
++	while (1) {
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++		/*	Commented by Albert 2011/05/18 */
++		/*	Match the device address located in the P2P IE */
++		/*	This is for the case that the P2P device address is not the same as the P2P interface address. */
++
++		p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);
++		if (p2pie) {
++			/*	The P2P Device ID attribute is included in the Beacon frame. */
++			/*	The P2P Device Info attribute is included in the probe response frame. */
++
++			if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) {
++				/*	Handle the P2P Device ID attribute of Beacon first */
++				if (_rtw_memcmp(attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN)) {
++					uintPeerChannel = pnetwork->network.Configuration.DSConfig;
++					break;
++				}
++			} else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) {
++				/*	Handle the P2P Device Info attribute of probe response */
++				if (_rtw_memcmp(attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN)) {
++					uintPeerChannel = pnetwork->network.Configuration.DSConfig;
++					break;
++				}
++			}
++
++		}
++
++		plist = get_next(plist);
++
++	}
++
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++#ifdef CONFIG_WFD
++	if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST) && uintPeerChannel) {
++		struct wifi_display_info *pwfd_info = pwdinfo->wfd_info;
++		u8 *wfd_ie;
++		uint wfd_ielen = 0;
++
++		wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen);
++		if (wfd_ie) {
++			u8 *wfd_devinfo;
++			uint wfd_devlen;
++
++			RTW_INFO("[%s] Found WFD IE!\n", __FUNCTION__);
++			wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen);
++			if (wfd_devinfo) {
++				u16	wfd_devinfo_field = 0;
++
++				/*	Commented by Albert 20120319 */
++				/*	The first two bytes are the WFD device information field of WFD device information subelement. */
++				/*	In big endian format. */
++				wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo);
++				if (wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL)
++					pwfd_info->peer_session_avail = _TRUE;
++				else
++					pwfd_info->peer_session_avail = _FALSE;
++			}
++		}
++
++		if (_FALSE == pwfd_info->peer_session_avail) {
++			RTW_INFO("[%s] WFD Session not avaiable!\n", __FUNCTION__);
++			goto exit;
++		}
++	}
++#endif /* CONFIG_WFD */
++
++	if (uintPeerChannel) {
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_check_status(padapter, MI_LINKED))
++			_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);
++#endif /* CONFIG_CONCURRENT_MODE */
++
++		/*	Store the GO's bssid */
++		for (jj = 0, kk = 18; jj < ETH_ALEN; jj++, kk += 3)
++			pinvite_req_info->go_bssid[jj] = key_2char2num(extra[kk], extra[kk + 1]);
++
++		/*	Store the GO's ssid */
++		pinvite_req_info->ssidlen = wrqu->data.length - 36;
++		_rtw_memcpy(pinvite_req_info->go_ssid, &extra[36], (u32) pinvite_req_info->ssidlen);
++		pinvite_req_info->benable = _TRUE;
++		pinvite_req_info->peer_ch = uintPeerChannel;
++
++		rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++		rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INVITE_REQ);
++
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_check_status(padapter, MI_LINKED)) {
++			u8 union_ch = rtw_mi_get_union_chan(padapter);
++			u8 union_bw = rtw_mi_get_union_bw(padapter);
++			u8 union_offset = rtw_mi_get_union_offset(padapter);
++
++			set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
++			rtw_leave_opch(padapter);
++
++		} else
++			set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++#else
++		set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++#endif/*CONFIG_CONCURRENT_MODE*/
++
++		_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
++
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_check_status(padapter, MI_LINKED))
++			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_INVITE_TIMEOUT);
++		else
++			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_INVITE_TIMEOUT);
++#else
++		_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_INVITE_TIMEOUT);
++#endif /* CONFIG_CONCURRENT_MODE		 */
++
++
++	} else
++		RTW_INFO("[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__);
++exit:
++
++	return ret;
++
++}
++
++static int rtw_p2p_set_persistent(struct net_device *dev,
++				  struct iw_request_info *info,
++				  union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter					*padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info		*pwdinfo = &(padapter->wdinfo);
++
++	/*	Commented by Albert 20120328 */
++	/*	The input data is 0 or 1 */
++	/*	0: disable persistent group functionality */
++	/*	1: enable persistent group founctionality */
++
++	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
++
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
++		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
++		return ret;
++	} else {
++		if (extra[0] == '0')	/*	Disable the persistent group function. */
++			pwdinfo->persistent_supported = _FALSE;
++		else if (extra[0] == '1')	/*	Enable the persistent group function. */
++			pwdinfo->persistent_supported = _TRUE;
++		else
++			pwdinfo->persistent_supported = _FALSE;
++	}
++	printk("[%s] persistent_supported = %d\n", __FUNCTION__, pwdinfo->persistent_supported);
++
++	return ret;
++
++}
++
++static int uuid_str2bin(const char *str, u8 *bin)
++{
++	const char *pos;
++	u8 *opos;
++
++	pos = str;
++	opos = bin;
++
++	if (hexstr2bin(pos, opos, 4))
++		return -1;
++	pos += 8;
++	opos += 4;
++
++	if (*pos++ != '-' || hexstr2bin(pos, opos, 2))
++		return -1;
++	pos += 4;
++	opos += 2;
++
++	if (*pos++ != '-' || hexstr2bin(pos, opos, 2))
++		return -1;
++	pos += 4;
++	opos += 2;
++
++	if (*pos++ != '-' || hexstr2bin(pos, opos, 2))
++		return -1;
++	pos += 4;
++	opos += 2;
++
++	if (*pos++ != '-' || hexstr2bin(pos, opos, 6))
++		return -1;
++
++	return 0;
++}
++
++static int rtw_p2p_set_wps_uuid(struct net_device *dev,
++				struct iw_request_info *info,
++				union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter				*padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info			*pwdinfo = &(padapter->wdinfo);
++
++	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
++
++	if ((36 == strlen(extra)) && (uuid_str2bin(extra, pwdinfo->uuid) == 0))
++		pwdinfo->external_uuid = 1;
++	else {
++		pwdinfo->external_uuid = 0;
++		ret = -EINVAL;
++	}
++
++	return ret;
++
++}
++#ifdef CONFIG_WFD
++static int rtw_p2p_set_pc(struct net_device *dev,
++			  struct iw_request_info *info,
++			  union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter				*padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++	u8					peerMAC[ETH_ALEN] = { 0x00 };
++	int					jj, kk;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	_list					*plist, *phead;
++	_queue				*queue	= &(pmlmepriv->scanned_queue);
++	struct	wlan_network	*pnetwork = NULL;
++	u8					attr_content[50] = { 0x00 };
++	u8 *p2pie;
++	uint					p2pielen = 0, attr_contentlen = 0;
++	_irqL				irqL;
++	uint					uintPeerChannel = 0;
++
++	struct wifi_display_info	*pwfd_info = pwdinfo->wfd_info;
++
++	/*	Commented by Albert 20120512 */
++	/*	1. Input information is the MAC address which wants to know the Preferred Connection bit (PC bit) */
++	/*	Format: 00:E0:4C:00:00:05 */
++
++	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
++
++	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
++		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
++		return ret;
++	}
++
++	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
++		peerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]);
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++
++	while (1) {
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++		/*	Commented by Albert 2011/05/18 */
++		/*	Match the device address located in the P2P IE */
++		/*	This is for the case that the P2P device address is not the same as the P2P interface address. */
++
++		p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);
++		if (p2pie) {
++			/*	The P2P Device ID attribute is included in the Beacon frame. */
++			/*	The P2P Device Info attribute is included in the probe response frame. */
++			printk("[%s] Got P2P IE\n", __FUNCTION__);
++			if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) {
++				/*	Handle the P2P Device ID attribute of Beacon first */
++				printk("[%s] P2P_ATTR_DEVICE_ID\n", __FUNCTION__);
++				if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) {
++					uintPeerChannel = pnetwork->network.Configuration.DSConfig;
++					break;
++				}
++			} else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) {
++				/*	Handle the P2P Device Info attribute of probe response */
++				printk("[%s] P2P_ATTR_DEVICE_INFO\n", __FUNCTION__);
++				if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) {
++					uintPeerChannel = pnetwork->network.Configuration.DSConfig;
++					break;
++				}
++			}
++
++		}
++
++		plist = get_next(plist);
++
++	}
++
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++	printk("[%s] channel = %d\n", __FUNCTION__, uintPeerChannel);
++
++	if (uintPeerChannel) {
++		u8 *wfd_ie;
++		uint wfd_ielen = 0;
++
++		wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen);
++		if (wfd_ie) {
++			u8 *wfd_devinfo;
++			uint wfd_devlen;
++
++			RTW_INFO("[%s] Found WFD IE!\n", __FUNCTION__);
++			wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen);
++			if (wfd_devinfo) {
++				u16	wfd_devinfo_field = 0;
++
++				/*	Commented by Albert 20120319 */
++				/*	The first two bytes are the WFD device information field of WFD device information subelement. */
++				/*	In big endian format. */
++				wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo);
++				if (wfd_devinfo_field & WFD_DEVINFO_PC_TDLS)
++					pwfd_info->wfd_pc = _TRUE;
++				else
++					pwfd_info->wfd_pc = _FALSE;
++			}
++		}
++	} else
++		RTW_INFO("[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__);
++
++	return ret;
++
++}
++
++static int rtw_p2p_set_wfd_device_type(struct net_device *dev,
++				       struct iw_request_info *info,
++				       union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter					*padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info		*pwdinfo = &(padapter->wdinfo);
++	struct wifi_display_info		*pwfd_info = pwdinfo->wfd_info;
++
++	/*	Commented by Albert 20120328 */
++	/*	The input data is 0 or 1 */
++	/*	0: specify to Miracast source device */
++	/*	1 or others: specify to Miracast sink device (display device) */
++
++	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
++
++	if (extra[0] == '0')	/*	Set to Miracast source device. */
++		pwfd_info->wfd_device_type = WFD_DEVINFO_SOURCE;
++	else					/*	Set to Miracast sink device. */
++		pwfd_info->wfd_device_type = WFD_DEVINFO_PSINK;
++
++	return ret;
++
++}
++
++static int rtw_p2p_set_wfd_enable(struct net_device *dev,
++				  struct iw_request_info *info,
++				  union iwreq_data *wrqu, char *extra)
++{
++	/*	Commented by Kurt 20121206
++	 *	This function is used to set wfd enabled */
++
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++
++	if (*extra == '0')
++		rtw_wfd_enable(padapter, 0);
++	else if (*extra == '1')
++		rtw_wfd_enable(padapter, 1);
++
++	RTW_INFO("[%s] wfd_enable = %d\n", __FUNCTION__, pwdinfo->wfd_info->wfd_enable);
++
++	return ret;
++
++}
++
++static int rtw_p2p_set_driver_iface(struct net_device *dev,
++				    struct iw_request_info *info,
++				    union iwreq_data *wrqu, char *extra)
++{
++	/*	Commented by Kurt 20121206
++	 *	This function is used to set driver iface is WEXT or CFG80211 */
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++
++	if (*extra == '1') {
++		pwdinfo->driver_interface = DRIVER_WEXT;
++		RTW_INFO("[%s] driver_interface = WEXT\n", __FUNCTION__);
++	} else if (*extra == '2') {
++		pwdinfo->driver_interface = DRIVER_CFG80211;
++		RTW_INFO("[%s] driver_interface = CFG80211\n", __FUNCTION__);
++	}
++
++	return ret;
++
++}
++
++/*	To set the WFD session available to enable or disable */
++static int rtw_p2p_set_sa(struct net_device *dev,
++			  struct iw_request_info *info,
++			  union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter					*padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info		*pwdinfo = &(padapter->wdinfo);
++
++	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
++
++	if (0) {
++		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
++		return ret;
++	} else {
++		if (extra[0] == '0')	/*	Disable the session available. */
++			pwdinfo->session_available = _FALSE;
++		else if (extra[0] == '1')	/*	Enable the session available. */
++			pwdinfo->session_available = _TRUE;
++		else
++			pwdinfo->session_available = _FALSE;
++	}
++	printk("[%s] session available = %d\n", __FUNCTION__, pwdinfo->session_available);
++
++	return ret;
++
++}
++#endif /* CONFIG_WFD */
++
++static int rtw_p2p_prov_disc(struct net_device *dev,
++			     struct iw_request_info *info,
++			     union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++	_adapter				*padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++	u8					peerMAC[ETH_ALEN] = { 0x00 };
++	int					jj, kk;
++	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
++	_list					*plist, *phead;
++	_queue				*queue	= &(pmlmepriv->scanned_queue);
++	struct	wlan_network	*pnetwork = NULL;
++	uint					uintPeerChannel = 0;
++	u8					attr_content[100] = { 0x00 };
++	u8 *p2pie;
++	uint					p2pielen = 0, attr_contentlen = 0;
++	_irqL				irqL;
++
++	/*	Commented by Albert 20110301 */
++	/*	The input data contains two informations. */
++	/*	1. First information is the MAC address which wants to issue the provisioning discovery request frame. */
++	/*	2. Second information is the WPS configuration method which wants to discovery */
++	/*	Format: 00:E0:4C:00:00:05_display */
++	/*	Format: 00:E0:4C:00:00:05_keypad */
++	/*	Format: 00:E0:4C:00:00:05_pbc */
++	/*	Format: 00:E0:4C:00:00:05_label */
++
++	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
++
++	if (pwdinfo->p2p_state == P2P_STATE_NONE) {
++		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
++		return ret;
++	} else {
++		/*	Reset the content of struct tx_provdisc_req_info excluded the wps_config_method_request. */
++		_rtw_memset(pwdinfo->tx_prov_disc_info.peerDevAddr, 0x00, ETH_ALEN);
++		_rtw_memset(pwdinfo->tx_prov_disc_info.peerIFAddr, 0x00, ETH_ALEN);
++		_rtw_memset(&pwdinfo->tx_prov_disc_info.ssid, 0x00, sizeof(NDIS_802_11_SSID));
++		pwdinfo->tx_prov_disc_info.peer_channel_num[0] = 0;
++		pwdinfo->tx_prov_disc_info.peer_channel_num[1] = 0;
++		pwdinfo->tx_prov_disc_info.benable = _FALSE;
++	}
++
++	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
++		peerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]);
++
++	if (_rtw_memcmp(&extra[18], "display", 7))
++		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA;
++	else if (_rtw_memcmp(&extra[18], "keypad", 7))
++		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD;
++	else if (_rtw_memcmp(&extra[18], "pbc", 3))
++		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON;
++	else if (_rtw_memcmp(&extra[18], "label", 5))
++		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL;
++	else {
++		RTW_INFO("[%s] Unknown WPS config methodn", __FUNCTION__);
++		return ret ;
++	}
++
++	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	phead = get_list_head(queue);
++	plist = get_next(phead);
++
++	while (1) {
++		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++			break;
++
++		if (uintPeerChannel != 0)
++			break;
++
++		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++
++		/*	Commented by Albert 2011/05/18 */
++		/*	Match the device address located in the P2P IE */
++		/*	This is for the case that the P2P device address is not the same as the P2P interface address. */
++
++		p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);
++		if (p2pie) {
++			while (p2pie) {
++				/*	The P2P Device ID attribute is included in the Beacon frame. */
++				/*	The P2P Device Info attribute is included in the probe response frame. */
++
++				if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) {
++					/*	Handle the P2P Device ID attribute of Beacon first */
++					if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) {
++						uintPeerChannel = pnetwork->network.Configuration.DSConfig;
++						break;
++					}
++				} else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) {
++					/*	Handle the P2P Device Info attribute of probe response */
++					if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) {
++						uintPeerChannel = pnetwork->network.Configuration.DSConfig;
++						break;
++					}
++				}
++
++				/* Get the next P2P IE */
++				p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen);
++			}
++
++		}
++
++		plist = get_next(plist);
++
++	}
++
++	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++
++	if (uintPeerChannel) {
++#ifdef CONFIG_WFD
++		if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
++			struct wifi_display_info *pwfd_info = pwdinfo->wfd_info;
++			u8 *wfd_ie;
++			uint wfd_ielen = 0;
++
++			wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen);
++			if (wfd_ie) {
++				u8 *wfd_devinfo;
++				uint wfd_devlen;
++
++				RTW_INFO("[%s] Found WFD IE!\n", __FUNCTION__);
++				wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen);
++				if (wfd_devinfo) {
++					u16	wfd_devinfo_field = 0;
++
++					/*	Commented by Albert 20120319 */
++					/*	The first two bytes are the WFD device information field of WFD device information subelement. */
++					/*	In big endian format. */
++					wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo);
++					if (wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL)
++						pwfd_info->peer_session_avail = _TRUE;
++					else
++						pwfd_info->peer_session_avail = _FALSE;
++				}
++			}
++
++			if (_FALSE == pwfd_info->peer_session_avail) {
++				RTW_INFO("[%s] WFD Session not avaiable!\n", __FUNCTION__);
++				goto exit;
++			}
++		}
++#endif /* CONFIG_WFD */
++
++		RTW_INFO("[%s] peer channel: %d!\n", __FUNCTION__, uintPeerChannel);
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_check_status(padapter, MI_LINKED))
++			_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);
++#endif /* CONFIG_CONCURRENT_MODE */
++		_rtw_memcpy(pwdinfo->tx_prov_disc_info.peerIFAddr, pnetwork->network.MacAddress, ETH_ALEN);
++		_rtw_memcpy(pwdinfo->tx_prov_disc_info.peerDevAddr, peerMAC, ETH_ALEN);
++		pwdinfo->tx_prov_disc_info.peer_channel_num[0] = (u16) uintPeerChannel;
++		pwdinfo->tx_prov_disc_info.benable = _TRUE;
++		rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
++		rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ);
++
++		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT))
++			_rtw_memcpy(&pwdinfo->tx_prov_disc_info.ssid, &pnetwork->network.Ssid, sizeof(NDIS_802_11_SSID));
++		else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
++			_rtw_memcpy(pwdinfo->tx_prov_disc_info.ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN);
++			pwdinfo->tx_prov_disc_info.ssid.SsidLength = P2P_WILDCARD_SSID_LEN;
++		}
++
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_check_status(padapter, MI_LINKED)) {
++			u8 union_ch = rtw_mi_get_union_chan(padapter);
++			u8 union_bw = rtw_mi_get_union_bw(padapter);
++			u8 union_offset = rtw_mi_get_union_offset(padapter);
++
++			set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
++			rtw_leave_opch(padapter);
++
++		} else
++			set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++#else
++		set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
++#endif
++
++		_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
++
++#ifdef CONFIG_CONCURRENT_MODE
++		if (rtw_mi_check_status(padapter, MI_LINKED))
++			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_PROVISION_TIMEOUT);
++		else
++			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT);
++#else
++		_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT);
++#endif /* CONFIG_CONCURRENT_MODE		 */
++
++	} else {
++		RTW_INFO("[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__);
++	}
++exit:
++
++	return ret;
++
++}
++
++/*	Added by Albert 20110328
++ *	This function is used to inform the driver the user had specified the pin code value or pbc
++ *	to application. */
++
++static int rtw_p2p_got_wpsinfo(struct net_device *dev,
++			       struct iw_request_info *info,
++			       union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++	_adapter				*padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
++
++
++	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
++	/*	Added by Albert 20110328 */
++	/*	if the input data is P2P_NO_WPSINFO -> reset the wpsinfo */
++	/*	if the input data is P2P_GOT_WPSINFO_PEER_DISPLAY_PIN -> the utility just input the PIN code got from the peer P2P device. */
++	/*	if the input data is P2P_GOT_WPSINFO_SELF_DISPLAY_PIN -> the utility just got the PIN code from itself. */
++	/*	if the input data is P2P_GOT_WPSINFO_PBC -> the utility just determine to use the PBC */
++
++	if (*extra == '0')
++		pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO;
++	else if (*extra == '1')
++		pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PEER_DISPLAY_PIN;
++	else if (*extra == '2')
++		pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_SELF_DISPLAY_PIN;
++	else if (*extra == '3')
++		pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PBC;
++	else
++		pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO;
++
++	return ret;
++
++}
++
++#endif /* CONFIG_P2P */
++
++static int rtw_p2p_set(struct net_device *dev,
++		       struct iw_request_info *info,
++		       union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++#ifdef CONFIG_P2P
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_INFO("[%s] extra = %s\n", __FUNCTION__, extra);
++
++	if (_rtw_memcmp(extra, "enable=", 7))
++		rtw_wext_p2p_enable(dev, info, wrqu, &extra[7]);
++	else if (_rtw_memcmp(extra, "setDN=", 6)) {
++		wrqu->data.length -= 6;
++		rtw_p2p_setDN(dev, info, wrqu, &extra[6]);
++	} else if (_rtw_memcmp(extra, "profilefound=", 13)) {
++		wrqu->data.length -= 13;
++		rtw_p2p_profilefound(dev, info, wrqu, &extra[13]);
++	} else if (_rtw_memcmp(extra, "prov_disc=", 10)) {
++		wrqu->data.length -= 10;
++		rtw_p2p_prov_disc(dev, info, wrqu, &extra[10]);
++	} else if (_rtw_memcmp(extra, "nego=", 5)) {
++		wrqu->data.length -= 5;
++		rtw_p2p_connect(dev, info, wrqu, &extra[5]);
++	} else if (_rtw_memcmp(extra, "intent=", 7)) {
++		/*	Commented by Albert 2011/03/23 */
++		/*	The wrqu->data.length will include the null character */
++		/*	So, we will decrease 7 + 1 */
++		wrqu->data.length -= 8;
++		rtw_p2p_set_intent(dev, info, wrqu, &extra[7]);
++	} else if (_rtw_memcmp(extra, "ssid=", 5)) {
++		wrqu->data.length -= 5;
++		rtw_p2p_set_go_nego_ssid(dev, info, wrqu, &extra[5]);
++	} else if (_rtw_memcmp(extra, "got_wpsinfo=", 12)) {
++		wrqu->data.length -= 12;
++		rtw_p2p_got_wpsinfo(dev, info, wrqu, &extra[12]);
++	} else if (_rtw_memcmp(extra, "listen_ch=", 10)) {
++		/*	Commented by Albert 2011/05/24 */
++		/*	The wrqu->data.length will include the null character */
++		/*	So, we will decrease (10 + 1)	 */
++		wrqu->data.length -= 11;
++		rtw_p2p_set_listen_ch(dev, info, wrqu, &extra[10]);
++	} else if (_rtw_memcmp(extra, "op_ch=", 6)) {
++		/*	Commented by Albert 2011/05/24 */
++		/*	The wrqu->data.length will include the null character */
++		/*	So, we will decrease (6 + 1)	 */
++		wrqu->data.length -= 7;
++		rtw_p2p_set_op_ch(dev, info, wrqu, &extra[6]);
++	} else if (_rtw_memcmp(extra, "invite=", 7)) {
++		wrqu->data.length -= 8;
++		rtw_p2p_invite_req(dev, info, wrqu, &extra[7]);
++	} else if (_rtw_memcmp(extra, "persistent=", 11)) {
++		wrqu->data.length -= 11;
++		rtw_p2p_set_persistent(dev, info, wrqu, &extra[11]);
++	} else if (_rtw_memcmp(extra, "uuid=", 5)) {
++		wrqu->data.length -= 5;
++		ret = rtw_p2p_set_wps_uuid(dev, info, wrqu, &extra[5]);
++	}
++
++#ifdef CONFIG_WFD
++	if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
++		if (_rtw_memcmp(extra, "sa=", 3)) {
++			/* sa: WFD Session Available information */
++			wrqu->data.length -= 3;
++			rtw_p2p_set_sa(dev, info, wrqu, &extra[3]);
++		} else if (_rtw_memcmp(extra, "pc=", 3)) {
++			/* pc: WFD Preferred Connection */
++			wrqu->data.length -= 3;
++			rtw_p2p_set_pc(dev, info, wrqu, &extra[3]);
++		} else if (_rtw_memcmp(extra, "wfd_type=", 9)) {
++			wrqu->data.length -= 9;
++			rtw_p2p_set_wfd_device_type(dev, info, wrqu, &extra[9]);
++		} else if (_rtw_memcmp(extra, "wfd_enable=", 11)) {
++			wrqu->data.length -= 11;
++			rtw_p2p_set_wfd_enable(dev, info, wrqu, &extra[11]);
++		} else if (_rtw_memcmp(extra, "driver_iface=", 13)) {
++			wrqu->data.length -= 13;
++			rtw_p2p_set_driver_iface(dev, info, wrqu, &extra[13]);
++		}
++	}
++#endif /* CONFIG_WFD */
++
++#endif /* CONFIG_P2P */
++
++	return ret;
++
++}
++
++static int rtw_p2p_get(struct net_device *dev,
++		       struct iw_request_info *info,
++		       union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++#ifdef CONFIG_P2P
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (padapter->bShowGetP2PState)
++		RTW_INFO("[%s] extra = %s\n", __FUNCTION__, (char *) wrqu->data.pointer);
++
++	if (_rtw_memcmp(wrqu->data.pointer, "status", 6))
++		rtw_p2p_get_status(dev, info, wrqu, extra);
++	else if (_rtw_memcmp(wrqu->data.pointer, "role", 4))
++		rtw_p2p_get_role(dev, info, wrqu, extra);
++	else if (_rtw_memcmp(wrqu->data.pointer, "peer_ifa", 8))
++		rtw_p2p_get_peer_ifaddr(dev, info, wrqu, extra);
++	else if (_rtw_memcmp(wrqu->data.pointer, "req_cm", 6))
++		rtw_p2p_get_req_cm(dev, info, wrqu, extra);
++	else if (_rtw_memcmp(wrqu->data.pointer, "peer_deva", 9)) {
++		/*	Get the P2P device address when receiving the provision discovery request frame. */
++		rtw_p2p_get_peer_devaddr(dev, info, wrqu, extra);
++	} else if (_rtw_memcmp(wrqu->data.pointer, "group_id", 8))
++		rtw_p2p_get_groupid(dev, info, wrqu, extra);
++	else if (_rtw_memcmp(wrqu->data.pointer, "inv_peer_deva", 13)) {
++		/*	Get the P2P device address when receiving the P2P Invitation request frame. */
++		rtw_p2p_get_peer_devaddr_by_invitation(dev, info, wrqu, extra);
++	} else if (_rtw_memcmp(wrqu->data.pointer, "op_ch", 5))
++		rtw_p2p_get_op_ch(dev, info, wrqu, extra);
++
++#ifdef CONFIG_WFD
++	if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
++		if (_rtw_memcmp(wrqu->data.pointer, "peer_port", 9))
++			rtw_p2p_get_peer_wfd_port(dev, info, wrqu, extra);
++		else if (_rtw_memcmp(wrqu->data.pointer, "wfd_sa", 6))
++			rtw_p2p_get_peer_wfd_session_available(dev, info, wrqu, extra);
++		else if (_rtw_memcmp(wrqu->data.pointer, "wfd_pc", 6))
++			rtw_p2p_get_peer_wfd_preferred_connection(dev, info, wrqu, extra);
++	}
++#endif /* CONFIG_WFD */
++
++#endif /* CONFIG_P2P */
++
++	return ret;
++
++}
++
++static int rtw_p2p_get2(struct net_device *dev,
++			struct iw_request_info *info,
++			union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++
++#ifdef CONFIG_P2P
++
++	int length = wrqu->data.length;
++	char *buffer = (u8 *)rtw_malloc(length);
++
++	if (buffer == NULL) {
++		ret = -ENOMEM;
++		goto bad;
++	}
++
++	if (copy_from_user(buffer, wrqu->data.pointer, wrqu->data.length)) {
++		ret = -EFAULT;
++		goto bad;
++	}
++
++	RTW_INFO("[%s] buffer = %s\n", __FUNCTION__, buffer);
++
++	if (_rtw_memcmp(buffer, "wpsCM=", 6))
++		ret = rtw_p2p_get_wps_configmethod(dev, info, wrqu, extra, &buffer[6]);
++	else if (_rtw_memcmp(buffer, "devN=", 5))
++		ret = rtw_p2p_get_device_name(dev, info, wrqu, extra, &buffer[5]);
++	else if (_rtw_memcmp(buffer, "dev_type=", 9))
++		ret = rtw_p2p_get_device_type(dev, info, wrqu, extra, &buffer[9]);
++	else if (_rtw_memcmp(buffer, "go_devadd=", 10))
++		ret = rtw_p2p_get_go_device_address(dev, info, wrqu, extra, &buffer[10]);
++	else if (_rtw_memcmp(buffer, "InvProc=", 8))
++		ret = rtw_p2p_get_invitation_procedure(dev, info, wrqu, extra, &buffer[8]);
++	else {
++		snprintf(extra, sizeof("Command not found."), "Command not found.");
++		wrqu->data.length = strlen(extra);
++	}
++
++bad:
++	if (buffer)
++		rtw_mfree(buffer, length);
++
++#endif /* CONFIG_P2P */
++
++	return ret;
++
++}
++
++#ifdef CONFIG_MP_INCLUDED
++static int rtw_cta_test_start(struct net_device *dev,
++			      struct iw_request_info *info,
++			      union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++	_adapter	*padapter = (_adapter *)rtw_netdev_priv(dev);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
++
++	RTW_INFO("%s %s\n", __func__, extra);
++	if (!strcmp(extra, "1"))
++		hal_data->in_cta_test = 1;
++	else
++		hal_data->in_cta_test = 0;
++
++	rtw_hal_rcr_set_chk_bssid(padapter, MLME_ACTION_NONE);
++
++	return ret;
++}
++#endif
++extern int rtw_change_ifname(_adapter *padapter, const char *ifname);
++static int rtw_rereg_nd_name(struct net_device *dev,
++			     struct iw_request_info *info,
++			     union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++	_adapter *padapter = rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	struct rereg_nd_name_data *rereg_priv = &padapter->rereg_nd_name_priv;
++	char new_ifname[IFNAMSIZ];
++
++	if (rereg_priv->old_ifname[0] == 0) {
++		char *reg_ifname;
++#ifdef CONFIG_CONCURRENT_MODE
++		if (padapter->isprimary)
++			reg_ifname = padapter->registrypriv.ifname;
++		else
++#endif
++			reg_ifname = padapter->registrypriv.if2name;
++
++		strncpy(rereg_priv->old_ifname, reg_ifname, IFNAMSIZ);
++		rereg_priv->old_ifname[IFNAMSIZ - 1] = 0;
++	}
++
++	/* RTW_INFO("%s wrqu->data.length:%d\n", __FUNCTION__, wrqu->data.length); */
++	if (wrqu->data.length > IFNAMSIZ)
++		return -EFAULT;
++
++	if (copy_from_user(new_ifname, wrqu->data.pointer, IFNAMSIZ))
++		return -EFAULT;
++
++	if (0 == strcmp(rereg_priv->old_ifname, new_ifname))
++		return ret;
++
++	RTW_INFO("%s new_ifname:%s\n", __FUNCTION__, new_ifname);
++	rtw_set_rtnl_lock_holder(dvobj, current);
++	ret = rtw_change_ifname(padapter, new_ifname);
++	rtw_set_rtnl_lock_holder(dvobj, NULL);
++	if (0 != ret)
++		goto exit;
++
++	if (_rtw_memcmp(rereg_priv->old_ifname, "disable%d", 9) == _TRUE) {
++		/* rtw_ips_mode_req(&padapter->pwrctrlpriv, rereg_priv->old_ips_mode); */
++	}
++
++	strncpy(rereg_priv->old_ifname, new_ifname, IFNAMSIZ);
++	rereg_priv->old_ifname[IFNAMSIZ - 1] = 0;
++
++	if (_rtw_memcmp(new_ifname, "disable%d", 9) == _TRUE) {
++
++		RTW_INFO("%s disable\n", __FUNCTION__);
++		/* free network queue for Android's timming issue */
++		rtw_free_network_queue(padapter, _TRUE);
++
++		/* the interface is being "disabled", we can do deeper IPS */
++		/* rereg_priv->old_ips_mode = rtw_get_ips_mode_req(&padapter->pwrctrlpriv); */
++		/* rtw_ips_mode_req(&padapter->pwrctrlpriv, IPS_NORMAL); */
++	}
++exit:
++	return ret;
++
++}
++
++#ifdef CONFIG_IOL
++#include <rtw_iol.h>
++#endif
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++#include "../../hal/hal_dm_acs.h"
++#endif
++#ifdef DBG_CMD_QUEUE
++u8 dump_cmd_id = 0;
++#endif
++
++static int rtw_dbg_port(struct net_device *dev,
++			struct iw_request_info *info,
++			union iwreq_data *wrqu, char *extra)
++{
++	_irqL irqL;
++	int ret = 0;
++	u8 major_cmd, minor_cmd;
++	u16 arg;
++	u32 extra_arg, *pdata, val32;
++	struct sta_info *psta;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++
++
++	pdata = (u32 *)&wrqu->data;
++
++	val32 = *pdata;
++	arg = (u16)(val32 & 0x0000ffff);
++	major_cmd = (u8)(val32 >> 24);
++	minor_cmd = (u8)((val32 >> 16) & 0x00ff);
++
++	extra_arg = *(pdata + 1);
++
++	switch (major_cmd) {
++	case 0x70: /* read_reg */
++		switch (minor_cmd) {
++		case 1:
++			RTW_INFO("rtw_read8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg));
++			break;
++		case 2:
++			RTW_INFO("rtw_read16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg));
++			break;
++		case 4:
++			RTW_INFO("rtw_read32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg));
++			break;
++		}
++		break;
++	case 0x71: /* write_reg */
++		switch (minor_cmd) {
++		case 1:
++			rtw_write8(padapter, arg, extra_arg);
++			RTW_INFO("rtw_write8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg));
++			break;
++		case 2:
++			rtw_write16(padapter, arg, extra_arg);
++			RTW_INFO("rtw_write16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg));
++			break;
++		case 4:
++			rtw_write32(padapter, arg, extra_arg);
++			RTW_INFO("rtw_write32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg));
++			break;
++		}
++		break;
++	case 0x72: /* read_bb */
++		RTW_INFO("read_bbreg(0x%x)=0x%x\n", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff));
++		break;
++	case 0x73: /* write_bb */
++		rtw_hal_write_bbreg(padapter, arg, 0xffffffff, extra_arg);
++		RTW_INFO("write_bbreg(0x%x)=0x%x\n", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff));
++		break;
++	case 0x74: /* read_rf */
++		RTW_INFO("read RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n", minor_cmd, arg, rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff));
++		break;
++	case 0x75: /* write_rf */
++		rtw_hal_write_rfreg(padapter, minor_cmd, arg, 0xffffffff, extra_arg);
++		RTW_INFO("write RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n", minor_cmd, arg, rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff));
++		break;
++
++	case 0x76:
++		switch (minor_cmd) {
++		case 0x00: /* normal mode, */
++			padapter->recvpriv.is_signal_dbg = 0;
++			break;
++		case 0x01: /* dbg mode */
++			padapter->recvpriv.is_signal_dbg = 1;
++			extra_arg = extra_arg > 100 ? 100 : extra_arg;
++			padapter->recvpriv.signal_strength_dbg = extra_arg;
++			break;
++		}
++		break;
++	case 0x78: /* IOL test */
++		switch (minor_cmd) {
++		#ifdef CONFIG_IOL
++		case 0x04: { /* LLT table initialization test */
++			u8 page_boundary = 0xf9;
++			{
++				struct xmit_frame	*xmit_frame;
++
++				xmit_frame = rtw_IOL_accquire_xmit_frame(padapter);
++				if (xmit_frame == NULL) {
++					ret = -ENOMEM;
++					break;
++				}
++
++				rtw_IOL_append_LLT_cmd(xmit_frame, page_boundary);
++
++
++				if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 500, 0))
++					ret = -EPERM;
++			}
++		}
++			break;
++		case 0x05: { /* blink LED test */
++			u16 reg = 0x4c;
++			u32 blink_num = 50;
++			u32 blink_delay_ms = 200;
++			int i;
++
++			{
++				struct xmit_frame	*xmit_frame;
++
++				xmit_frame = rtw_IOL_accquire_xmit_frame(padapter);
++				if (xmit_frame == NULL) {
++					ret = -ENOMEM;
++					break;
++				}
++
++				for (i = 0; i < blink_num; i++) {
++					#ifdef CONFIG_IOL_NEW_GENERATION
++					rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x00, 0xff);
++					rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);
++					rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x08, 0xff);
++					rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);
++					#else
++					rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x00);
++					rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);
++					rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x08);
++					rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);
++					#endif
++				}
++				if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, (blink_delay_ms * blink_num * 2) + 200, 0))
++					ret = -EPERM;
++			}
++		}
++			break;
++
++		case 0x06: { /* continuous wirte byte test */
++			u16 reg = arg;
++			u16 start_value = 0;
++			u32 write_num = extra_arg;
++			int i;
++			u8 final;
++
++			{
++				struct xmit_frame	*xmit_frame;
++
++				xmit_frame = rtw_IOL_accquire_xmit_frame(padapter);
++				if (xmit_frame == NULL) {
++					ret = -ENOMEM;
++					break;
++				}
++
++				for (i = 0; i < write_num; i++) {
++					#ifdef CONFIG_IOL_NEW_GENERATION
++					rtw_IOL_append_WB_cmd(xmit_frame, reg, i + start_value, 0xFF);
++					#else
++					rtw_IOL_append_WB_cmd(xmit_frame, reg, i + start_value);
++					#endif
++				}
++				if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0))
++					ret = -EPERM;
++			}
++
++			final = rtw_read8(padapter, reg);
++			if (start_value + write_num - 1 == final)
++				RTW_INFO("continuous IOL_CMD_WB_REG to 0x%x %u times Success, start:%u, final:%u\n", reg, write_num, start_value, final);
++			else
++				RTW_INFO("continuous IOL_CMD_WB_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final);
++		}
++			break;
++
++		case 0x07: { /* continuous wirte word test */
++			u16 reg = arg;
++			u16 start_value = 200;
++			u32 write_num = extra_arg;
++
++			int i;
++			u16 final;
++
++			{
++				struct xmit_frame	*xmit_frame;
++
++				xmit_frame = rtw_IOL_accquire_xmit_frame(padapter);
++				if (xmit_frame == NULL) {
++					ret = -ENOMEM;
++					break;
++				}
++
++				for (i = 0; i < write_num; i++) {
++					#ifdef CONFIG_IOL_NEW_GENERATION
++					rtw_IOL_append_WW_cmd(xmit_frame, reg, i + start_value, 0xFFFF);
++					#else
++					rtw_IOL_append_WW_cmd(xmit_frame, reg, i + start_value);
++					#endif
++				}
++				if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0))
++					ret = -EPERM;
++			}
++
++			final = rtw_read16(padapter, reg);
++			if (start_value + write_num - 1 == final)
++				RTW_INFO("continuous IOL_CMD_WW_REG to 0x%x %u times Success, start:%u, final:%u\n", reg, write_num, start_value, final);
++			else
++				RTW_INFO("continuous IOL_CMD_WW_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final);
++		}
++			break;
++
++		case 0x08: { /* continuous wirte dword test */
++			u16 reg = arg;
++			u32 start_value = 0x110000c7;
++			u32 write_num = extra_arg;
++
++			int i;
++			u32 final;
++
++			{
++				struct xmit_frame	*xmit_frame;
++
++				xmit_frame = rtw_IOL_accquire_xmit_frame(padapter);
++				if (xmit_frame == NULL) {
++					ret = -ENOMEM;
++					break;
++				}
++
++				for (i = 0; i < write_num; i++) {
++					#ifdef CONFIG_IOL_NEW_GENERATION
++					rtw_IOL_append_WD_cmd(xmit_frame, reg, i + start_value, 0xFFFFFFFF);
++					#else
++					rtw_IOL_append_WD_cmd(xmit_frame, reg, i + start_value);
++					#endif
++				}
++				if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0))
++					ret = -EPERM;
++
++			}
++
++			final = rtw_read32(padapter, reg);
++			if (start_value + write_num - 1 == final)
++				RTW_INFO("continuous IOL_CMD_WD_REG to 0x%x %u times Success, start:%u, final:%u\n", reg, write_num, start_value, final);
++			else
++				RTW_INFO("continuous IOL_CMD_WD_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final);
++		}
++			break;
++		#endif /* CONFIG_IOL */
++		}
++		break;
++	case 0x79: {
++		/*
++		* dbg 0x79000000 [value], set RESP_TXAGC to + value, value:0~15
++		* dbg 0x79010000 [value], set RESP_TXAGC to - value, value:0~15
++		*/
++		u8 value =  extra_arg & 0x0f;
++		u8 sign = minor_cmd;
++		u16 write_value = 0;
++
++		RTW_INFO("%s set RESP_TXAGC to %s %u\n", __func__, sign ? "minus" : "plus", value);
++
++		if (sign)
++			value = value | 0x10;
++
++		write_value = value | (value << 5);
++		rtw_write16(padapter, 0x6d9, write_value);
++	}
++		break;
++	case 0x7a:
++		receive_disconnect(padapter, pmlmeinfo->network.MacAddress
++				   , WLAN_REASON_EXPIRATION_CHK, _FALSE);
++		break;
++	case 0x7F:
++		switch (minor_cmd) {
++		case 0x0:
++			RTW_INFO("fwstate=0x%x\n", get_fwstate(pmlmepriv));
++			break;
++		case 0x01:
++			RTW_INFO("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n",
++				psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm,
++				psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus);
++			break;
++		case 0x03:
++			RTW_INFO("qos_option=%d\n", pmlmepriv->qospriv.qos_option);
++#ifdef CONFIG_80211N_HT
++			RTW_INFO("ht_option=%d\n", pmlmepriv->htpriv.ht_option);
++#endif /* CONFIG_80211N_HT */
++			break;
++		case 0x04:
++			RTW_INFO("cur_ch=%d\n", pmlmeext->cur_channel);
++			RTW_INFO("cur_bw=%d\n", pmlmeext->cur_bwmode);
++			RTW_INFO("cur_ch_off=%d\n", pmlmeext->cur_ch_offset);
++
++			RTW_INFO("oper_ch=%d\n", rtw_get_oper_ch(padapter));
++			RTW_INFO("oper_bw=%d\n", rtw_get_oper_bw(padapter));
++			RTW_INFO("oper_ch_offet=%d\n", rtw_get_oper_choffset(padapter));
++
++			break;
++		case 0x05:
++			psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
++			if (psta) {
++				RTW_INFO("SSID=%s\n", cur_network->network.Ssid.Ssid);
++				RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
++				RTW_INFO("cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
++				RTW_INFO("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self);
++				RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n",
++					psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);
++#ifdef CONFIG_80211N_HT
++				RTW_INFO("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
++				RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n"
++					, psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m);
++				RTW_INFO("ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
++				RTW_INFO("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
++#endif /* CONFIG_80211N_HT */
++
++				sta_rx_reorder_ctl_dump(RTW_DBGDUMP, psta);
++			} else
++				RTW_INFO("can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress));
++			break;
++		case 0x06: {
++				u64 tsf = 0;
++
++				tsf = rtw_hal_get_tsftr_by_port(padapter, extra_arg);
++				RTW_INFO(" PORT-%d TSF :%21lld\n", extra_arg, tsf);
++		}
++			break;
++		case 0x07:
++			RTW_INFO("bSurpriseRemoved=%s, bDriverStopped=%s\n"
++				, rtw_is_surprise_removed(padapter) ? "True" : "False"
++				, rtw_is_drv_stopped(padapter) ? "True" : "False");
++			break;
++		case 0x08: {
++			struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++			struct recv_priv  *precvpriv = &padapter->recvpriv;
++
++			RTW_INFO("free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d"
++				", free_xmit_extbuf_cnt=%d, free_xframe_ext_cnt=%d"
++				 ", free_recvframe_cnt=%d\n",
++				pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt,
++				pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt,
++				 precvpriv->free_recvframe_cnt);
++#ifdef CONFIG_USB_HCI
++			RTW_INFO("rx_urb_pending_cn=%d\n", ATOMIC_READ(&(precvpriv->rx_pending_cnt)));
++#endif
++		}
++			break;
++		case 0x09: {
++			int i;
++			_list	*plist, *phead;
++
++#ifdef CONFIG_AP_MODE
++			RTW_INFO_DUMP("sta_dz_bitmap:", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);
++			RTW_INFO_DUMP("tim_bitmap:", pstapriv->tim_bitmap, pstapriv->aid_bmp_len);
++#endif
++			_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++			for (i = 0; i < NUM_STA; i++) {
++				phead = &(pstapriv->sta_hash[i]);
++				plist = get_next(phead);
++
++				while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++					psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++
++					plist = get_next(plist);
++
++					if (extra_arg == psta->cmn.aid) {
++						RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
++						RTW_INFO("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self);
++						RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n",
++							psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);
++#ifdef CONFIG_80211N_HT
++						RTW_INFO("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
++						RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n",
++							psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m,
++							psta->htpriv.sgi_40m);
++						RTW_INFO("ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
++						RTW_INFO("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
++#endif /* CONFIG_80211N_HT */
++
++#ifdef CONFIG_AP_MODE
++						RTW_INFO("capability=0x%x\n", psta->capability);
++						RTW_INFO("flags=0x%x\n", psta->flags);
++						RTW_INFO("wpa_psk=0x%x\n", psta->wpa_psk);
++						RTW_INFO("wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher);
++						RTW_INFO("wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher);
++						RTW_INFO("qos_info=0x%x\n", psta->qos_info);
++#endif
++						RTW_INFO("dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy);
++
++						sta_rx_reorder_ctl_dump(RTW_DBGDUMP, psta);
++					}
++
++				}
++			}
++
++			_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++		}
++			break;
++
++		case 0x0b: { /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */
++			/* u8 driver_vcs_en; */ /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */
++			/* u8 driver_vcs_type; */ /* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */
++
++			if (arg == 0) {
++				RTW_INFO("disable driver ctrl vcs\n");
++				padapter->driver_vcs_en = 0;
++			} else if (arg == 1) {
++				RTW_INFO("enable driver ctrl vcs = %d\n", extra_arg);
++				padapter->driver_vcs_en = 1;
++
++				if (extra_arg > 2)
++					padapter->driver_vcs_type = 1;
++				else
++					padapter->driver_vcs_type = extra_arg;
++			}
++		}
++			break;
++		case 0x0c: { /* dump rx/tx packet */
++			if (arg == 0) {
++				RTW_INFO("dump rx packet (%d)\n", extra_arg);
++				/* pHalData->bDumpRxPkt =extra_arg;						 */
++				rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_RXPKT, &(extra_arg));
++			} else if (arg == 1) {
++				RTW_INFO("dump tx packet (%d)\n", extra_arg);
++				rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(extra_arg));
++			}
++		}
++			break;
++		case 0x0e: {
++			if (arg == 0) {
++				RTW_INFO("disable driver ctrl rx_ampdu_factor\n");
++				padapter->driver_rx_ampdu_factor = 0xFF;
++			} else if (arg == 1) {
++
++				RTW_INFO("enable driver ctrl rx_ampdu_factor = %d\n", extra_arg);
++
++				if (extra_arg > 0x03)
++					padapter->driver_rx_ampdu_factor = 0xFF;
++				else
++					padapter->driver_rx_ampdu_factor = extra_arg;
++			}
++		}
++			break;
++		#ifdef DBG_CONFIG_ERROR_DETECT
++		case 0x0f: {
++			if (extra_arg == 0) {
++				RTW_INFO("###### silent reset test.......#####\n");
++				rtw_hal_sreset_reset(padapter);
++			} else {
++				HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++				struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++				psrtpriv->dbg_trigger_point = extra_arg;
++			}
++
++		}
++			break;
++		case 0x15: {
++			struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++			RTW_INFO("==>silent resete cnts:%d\n", pwrpriv->ips_enter_cnts);
++		}
++			break;
++
++		#endif
++
++		case 0x10: /* driver version display */
++			dump_drv_version(RTW_DBGDUMP);
++			break;
++		case 0x11: { /* dump linked status */
++			int pre_mode;
++			pre_mode = padapter->bLinkInfoDump;
++			/* linked_info_dump(padapter,extra_arg); */
++			if (extra_arg == 1 || (extra_arg == 0 && pre_mode == 1)) /* not consider pwr_saving 0: */
++				padapter->bLinkInfoDump = extra_arg;
++
++			else if ((extra_arg == 2) || (extra_arg == 0 && pre_mode == 2)) { /* consider power_saving */
++				/* RTW_INFO("linked_info_dump =%s\n", (padapter->bLinkInfoDump)?"enable":"disable") */
++				linked_info_dump(padapter, extra_arg);
++			}
++
++
++
++		}
++			break;
++#ifdef CONFIG_80211N_HT
++		case 0x12: { /* set rx_stbc */
++			struct registry_priv	*pregpriv = &padapter->registrypriv;
++			/* 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, 0x3: enable both 2.4g and 5g */
++			/* default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ */
++			if (pregpriv && (extra_arg == 0 || extra_arg == 1 || extra_arg == 2 || extra_arg == 3)) {
++				pregpriv->rx_stbc = extra_arg;
++				RTW_INFO("set rx_stbc=%d\n", pregpriv->rx_stbc);
++			} else
++				RTW_INFO("get rx_stbc=%d\n", pregpriv->rx_stbc);
++
++		}
++			break;
++		case 0x13: { /* set ampdu_enable */
++			struct registry_priv	*pregpriv = &padapter->registrypriv;
++			/* 0: disable, 0x1:enable */
++			if (pregpriv && extra_arg < 2) {
++				pregpriv->ampdu_enable = extra_arg;
++				RTW_INFO("set ampdu_enable=%d\n", pregpriv->ampdu_enable);
++			} else
++				RTW_INFO("get ampdu_enable=%d\n", pregpriv->ampdu_enable);
++
++		}
++			break;
++#endif
++		case 0x14: { /* get wifi_spec */
++			struct registry_priv	*pregpriv = &padapter->registrypriv;
++			RTW_INFO("get wifi_spec=%d\n", pregpriv->wifi_spec);
++
++		}
++			break;
++
++#ifdef DBG_FIXED_CHAN
++		case 0x17: {
++			struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++			printk("===>  Fixed channel to %d\n", extra_arg);
++			pmlmeext->fixed_chan = extra_arg;
++
++		}
++			break;
++#endif
++#ifdef CONFIG_80211N_HT
++		case 0x19: {
++			struct registry_priv	*pregistrypriv = &padapter->registrypriv;
++			/* extra_arg : */
++			/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, */
++			/* BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */
++			if (arg == 0) {
++				RTW_INFO("driver disable LDPC\n");
++				pregistrypriv->ldpc_cap = 0x00;
++			} else if (arg == 1) {
++				RTW_INFO("driver set LDPC cap = 0x%x\n", extra_arg);
++				pregistrypriv->ldpc_cap = (u8)(extra_arg & 0x33);
++			}
++		}
++			break;
++		case 0x1a: {
++			struct registry_priv	*pregistrypriv = &padapter->registrypriv;
++			/* extra_arg : */
++			/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, */
++			/* BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */
++			if (arg == 0) {
++				RTW_INFO("driver disable STBC\n");
++				pregistrypriv->stbc_cap = 0x00;
++			} else if (arg == 1) {
++				RTW_INFO("driver set STBC cap = 0x%x\n", extra_arg);
++				pregistrypriv->stbc_cap = (u8)(extra_arg & 0x33);
++			}
++		}
++			break;
++#endif /* CONFIG_80211N_HT */
++		case 0x1b: {
++			struct registry_priv	*pregistrypriv = &padapter->registrypriv;
++
++			if (arg == 0) {
++				RTW_INFO("disable driver ctrl max_rx_rate, reset to default_rate_set\n");
++				init_mlme_default_rate_set(padapter);
++#ifdef CONFIG_80211N_HT
++				pregistrypriv->ht_enable = (u8)rtw_ht_enable;
++#endif /* CONFIG_80211N_HT */
++			} else if (arg == 1) {
++
++				int i;
++				u8 max_rx_rate;
++
++				RTW_INFO("enable driver ctrl max_rx_rate = 0x%x\n", extra_arg);
++
++				max_rx_rate = (u8)extra_arg;
++
++				if (max_rx_rate < 0xc) { /* max_rx_rate < MSC0->B or G -> disable HT */
++#ifdef CONFIG_80211N_HT
++					pregistrypriv->ht_enable = 0;
++#endif /* CONFIG_80211N_HT */
++					for (i = 0; i < NumRates; i++) {
++						if (pmlmeext->datarate[i] > max_rx_rate)
++							pmlmeext->datarate[i] = 0xff;
++					}
++
++				}
++#ifdef CONFIG_80211N_HT
++				else if (max_rx_rate < 0x1c) { /* mcs0~mcs15 */
++					u32 mcs_bitmap = 0x0;
++
++					for (i = 0; i < ((max_rx_rate + 1) - 0xc); i++)
++						mcs_bitmap |= BIT(i);
++
++					set_mcs_rate_by_mask(pmlmeext->default_supported_mcs_set, mcs_bitmap);
++				}
++#endif /* CONFIG_80211N_HT							 */
++			}
++		}
++			break;
++		case 0x1c: { /* enable/disable driver control AMPDU Density for peer sta's rx */
++			if (arg == 0) {
++				RTW_INFO("disable driver ctrl ampdu density\n");
++				padapter->driver_ampdu_spacing = 0xFF;
++			} else if (arg == 1) {
++
++				RTW_INFO("enable driver ctrl ampdu density = %d\n", extra_arg);
++
++				if (extra_arg > 0x07)
++					padapter->driver_ampdu_spacing = 0xFF;
++				else
++					padapter->driver_ampdu_spacing = extra_arg;
++			}
++		}
++			break;
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++		case 0x1e: {
++			RTW_INFO("===========================================\n");
++			rtw_noise_measure_curchan(padapter);
++			RTW_INFO("===========================================\n");
++		}
++			break;
++#endif
++
++
++#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_SDIO_INDIRECT_ACCESS) && defined(DBG_SDIO_INDIRECT_ACCESS)
++		case 0x1f:
++			{
++				int i, j = 0, test_cnts = 0;
++				static u8 test_code = 0x5A;
++				static u32 data_misatch_cnt = 0, d_acc_err_cnt = 0;
++
++				u32 d_data, i_data;
++				u32 imr;
++
++				test_cnts = extra_arg;
++				for (i = 0; i < test_cnts; i++) {
++					if (RTW_CANNOT_IO(padapter))
++						break;
++
++					rtw_write8(padapter, 0x07, test_code);
++
++					d_data = rtw_read32(padapter, 0x04);
++					imr =  rtw_read32(padapter, 0x10250014);
++					rtw_write32(padapter, 0x10250014, 0);
++					rtw_msleep_os(50);
++
++					i_data = rtw_sd_iread32(padapter, 0x04);
++
++					rtw_write32(padapter, 0x10250014, imr);
++
++					if (d_data != i_data) {
++						data_misatch_cnt++;
++						RTW_ERR("d_data :0x%08x, i_data : 0x%08x\n", d_data, i_data);
++					}
++
++					if (test_code != (i_data >> 24)) {
++						d_acc_err_cnt++;
++						rtw_write8(padapter, 0x07, 0xAA);
++						RTW_ERR("test_code :0x%02x, i_data : 0x%08x\n", test_code, i_data);
++					}
++					if ((j++) == 100) {
++						rtw_msleep_os(2000);
++						RTW_INFO(" Indirect access testing..........%d/%d\n", i, test_cnts);
++						j = 0;
++					}
++
++					test_code = ~test_code;
++					rtw_msleep_os(50);
++				}
++				RTW_INFO("========Indirect access test=========\n");
++				RTW_INFO(" test_cnts = %d\n", test_cnts);
++				RTW_INFO(" direct & indirect read32 data missatch cnts = %d\n", data_misatch_cnt);
++				RTW_INFO(" indirect rdata is not equal to wdata cnts = %d\n", d_acc_err_cnt);
++				RTW_INFO("========Indirect access test=========\n\n");
++				data_misatch_cnt = d_acc_err_cnt = 0;
++
++			}
++			break;
++#endif
++		case 0x20:
++			{
++				if (arg == 0xAA) {
++					u8 page_offset, page_num;
++
++					page_offset = (u8)(extra_arg >> 16);
++					page_num = (u8)(extra_arg & 0xFF);
++					rtw_dump_rsvd_page(RTW_DBGDUMP, padapter, page_offset, page_num);
++				}
++#ifdef CONFIG_SUPPORT_FIFO_DUMP
++				else {
++					u8 fifo_sel;
++					u32 addr, size;
++
++					fifo_sel = (u8)(arg & 0x0F);
++					addr = (extra_arg >> 16) & 0xFFFF;
++					size = extra_arg & 0xFFFF;
++					rtw_dump_fifo(RTW_DBGDUMP, padapter, fifo_sel, addr, size);
++				}
++#endif
++			}
++			break;
++
++		case 0x23: {
++			RTW_INFO("turn %s the bNotifyChannelChange Variable\n", (extra_arg == 1) ? "on" : "off");
++			padapter->bNotifyChannelChange = extra_arg;
++			break;
++		}
++		case 0x24: {
++#ifdef CONFIG_P2P
++			RTW_INFO("turn %s the bShowGetP2PState Variable\n", (extra_arg == 1) ? "on" : "off");
++			padapter->bShowGetP2PState = extra_arg;
++#endif /* CONFIG_P2P */
++			break;
++		}
++#ifdef CONFIG_GPIO_API
++		case 0x25: { /* Get GPIO register */
++			/*
++			* dbg 0x7f250000 [gpio_num], Get gpio value, gpio_num:0~7
++			*/
++
++			u8 value;
++			RTW_INFO("Read GPIO Value  extra_arg = %d\n", extra_arg);
++			value = rtw_hal_get_gpio(padapter, extra_arg);
++			RTW_INFO("Read GPIO Value = %d\n", value);
++			break;
++		}
++		case 0x26: { /* Set GPIO direction */
++
++			/* dbg 0x7f26000x [y], Set gpio direction,
++			* x: gpio_num,4~7  y: indicate direction, 0~1
++			*/
++
++			int value;
++			RTW_INFO("Set GPIO Direction! arg = %d ,extra_arg=%d\n", arg , extra_arg);
++			value = rtw_hal_config_gpio(padapter, arg, extra_arg);
++			RTW_INFO("Set GPIO Direction %s\n", (value == -1) ? "Fail!!!" : "Success");
++			break;
++		}
++		case 0x27: { /* Set GPIO output direction value */
++			/*
++			* dbg 0x7f27000x [y], Set gpio output direction value,
++			* x: gpio_num,4~7  y: indicate direction, 0~1
++			*/
++
++			int value;
++			RTW_INFO("Set GPIO Value! arg = %d ,extra_arg=%d\n", arg , extra_arg);
++			value = rtw_hal_set_gpio_output_value(padapter, arg, extra_arg);
++			RTW_INFO("Set GPIO Value %s\n", (value == -1) ? "Fail!!!" : "Success");
++			break;
++		}
++#endif
++#ifdef DBG_CMD_QUEUE
++		case 0x28: {
++			dump_cmd_id = extra_arg;
++			RTW_INFO("dump_cmd_id:%d\n", dump_cmd_id);
++		}
++			break;
++#endif /* DBG_CMD_QUEUE */
++		case 0xaa: {
++			if ((extra_arg & 0x7F) > 0x3F)
++				extra_arg = 0xFF;
++			RTW_INFO("chang data rate to :0x%02x\n", extra_arg);
++			padapter->fix_rate = extra_arg;
++		}
++			break;
++		case 0xdd: { /* registers dump , 0 for mac reg,1 for bb reg, 2 for rf reg */
++			if (extra_arg == 0)
++				mac_reg_dump(RTW_DBGDUMP, padapter);
++			else if (extra_arg == 1)
++				bb_reg_dump(RTW_DBGDUMP, padapter);
++			else if (extra_arg == 2)
++				rf_reg_dump(RTW_DBGDUMP, padapter);
++			else if (extra_arg == 11)
++				bb_reg_dump_ex(RTW_DBGDUMP, padapter);
++		}
++			break;
++
++		case 0xee: {
++			RTW_INFO(" === please control /proc  to trun on/off PHYDM func ===\n");
++		}
++			break;
++
++		case 0xfd:
++			rtw_write8(padapter, 0xc50, arg);
++			RTW_INFO("wr(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50));
++			rtw_write8(padapter, 0xc58, arg);
++			RTW_INFO("wr(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58));
++			break;
++		case 0xfe:
++			RTW_INFO("rd(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50));
++			RTW_INFO("rd(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58));
++			break;
++		case 0xff: {
++			RTW_INFO("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210));
++			RTW_INFO("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608));
++			RTW_INFO("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280));
++			RTW_INFO("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284));
++			RTW_INFO("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288));
++
++			RTW_INFO("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664));
++
++
++			RTW_INFO("\n");
++
++			RTW_INFO("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430));
++			RTW_INFO("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438));
++
++			RTW_INFO("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440));
++
++			RTW_INFO("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458));
++
++			RTW_INFO("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484));
++			RTW_INFO("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488));
++
++			RTW_INFO("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444));
++			RTW_INFO("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448));
++			RTW_INFO("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c));
++			RTW_INFO("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450));
++		}
++			break;
++		}
++		break;
++	default:
++		RTW_INFO("error dbg cmd!\n");
++		break;
++	}
++
++
++	return ret;
++
++}
++
++static int wpa_set_param(struct net_device *dev, u8 name, u32 value)
++{
++	uint ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	switch (name) {
++	case IEEE_PARAM_WPA_ENABLED:
++
++		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; /* 802.1x */
++
++		/* ret = ieee80211_wpa_enable(ieee, value); */
++
++		switch ((value) & 0xff) {
++		case 1: /* WPA */
++			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK; /* WPA_PSK */
++			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
++			break;
++		case 2: /* WPA2 */
++			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK; /* WPA2_PSK */
++			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
++			break;
++		}
++
++
++		break;
++
++	case IEEE_PARAM_TKIP_COUNTERMEASURES:
++		/* ieee->tkip_countermeasures=value; */
++		break;
++
++	case IEEE_PARAM_DROP_UNENCRYPTED: {
++		/* HACK:
++		 *
++		 * wpa_supplicant calls set_wpa_enabled when the driver
++		 * is loaded and unloaded, regardless of if WPA is being
++		 * used.  No other calls are made which can be used to
++		 * determine if encryption will be used or not prior to
++		 * association being expected.  If encryption is not being
++		 * used, drop_unencrypted is set to false, else true -- we
++		 * can use this to determine if the CAP_PRIVACY_ON bit should
++		 * be set.
++		 */
++
++#if 0
++		struct ieee80211_security sec = {
++			.flags = SEC_ENABLED,
++			.enabled = value,
++		};
++		ieee->drop_unencrypted = value;
++		/* We only change SEC_LEVEL for open mode. Others
++		 * are set by ipw_wpa_set_encryption.
++		 */
++		if (!value) {
++			sec.flags |= SEC_LEVEL;
++			sec.level = SEC_LEVEL_0;
++		} else {
++			sec.flags |= SEC_LEVEL;
++			sec.level = SEC_LEVEL_1;
++		}
++		if (ieee->set_security)
++			ieee->set_security(ieee->dev, &sec);
++#endif
++		break;
++
++	}
++	case IEEE_PARAM_PRIVACY_INVOKED:
++
++		/* ieee->privacy_invoked=value; */
++
++		break;
++
++	case IEEE_PARAM_AUTH_ALGS:
++
++		ret = wpa_set_auth_algs(dev, value);
++
++		break;
++
++	case IEEE_PARAM_IEEE_802_1X:
++
++		/* ieee->ieee802_1x=value;		 */
++
++		break;
++
++	case IEEE_PARAM_WPAX_SELECT:
++
++		/* added for WPA2 mixed mode */
++		/*RTW_WARN("------------------------>wpax value = %x\n", value);*/
++		/*
++		spin_lock_irqsave(&ieee->wpax_suitlist_lock,flags);
++		ieee->wpax_type_set = 1;
++		ieee->wpax_type_notify = value;
++		spin_unlock_irqrestore(&ieee->wpax_suitlist_lock,flags);
++		*/
++
++		break;
++
++	default:
++
++
++
++		ret = -EOPNOTSUPP;
++
++
++		break;
++
++	}
++
++	return ret;
++
++}
++
++static int wpa_mlme(struct net_device *dev, u32 command, u32 reason)
++{
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	switch (command) {
++	case IEEE_MLME_STA_DEAUTH:
++
++		if (!rtw_set_802_11_disassociate(padapter))
++			ret = -1;
++
++		break;
++
++	case IEEE_MLME_STA_DISASSOC:
++
++		if (!rtw_set_802_11_disassociate(padapter))
++			ret = -1;
++
++		break;
++
++	default:
++		ret = -EOPNOTSUPP;
++		break;
++	}
++#ifdef CONFIG_RTW_REPEATER_SON
++	rtw_rson_do_disconnect(padapter);
++#endif
++	return ret;
++
++}
++
++static int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p)
++{
++	struct ieee_param *param;
++	uint ret = 0;
++
++	/* down(&ieee->wx_sem);	 */
++
++	if (p->length < sizeof(struct ieee_param) || !p->pointer) {
++		ret = -EINVAL;
++		goto out;
++	}
++
++	param = (struct ieee_param *)rtw_malloc(p->length);
++	if (param == NULL) {
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	if (copy_from_user(param, p->pointer, p->length)) {
++		rtw_mfree((u8 *)param, p->length);
++		ret = -EFAULT;
++		goto out;
++	}
++
++	switch (param->cmd) {
++
++	case IEEE_CMD_SET_WPA_PARAM:
++		ret = wpa_set_param(dev, param->u.wpa_param.name, param->u.wpa_param.value);
++		break;
++
++	case IEEE_CMD_SET_WPA_IE:
++		/* ret = wpa_set_wpa_ie(dev, param, p->length); */
++		ret =  rtw_set_wpa_ie((_adapter *)rtw_netdev_priv(dev), (char *)param->u.wpa_ie.data, (u16)param->u.wpa_ie.len);
++		break;
++
++	case IEEE_CMD_SET_ENCRYPTION:
++		ret = wpa_set_encryption(dev, param, p->length);
++		break;
++
++	case IEEE_CMD_MLME:
++		ret = wpa_mlme(dev, param->u.mlme.command, param->u.mlme.reason_code);
++		break;
++
++	default:
++		RTW_INFO("Unknown WPA supplicant request: %d\n", param->cmd);
++		ret = -EOPNOTSUPP;
++		break;
++
++	}
++
++	if (ret == 0 && copy_to_user(p->pointer, param, p->length))
++		ret = -EFAULT;
++
++	rtw_mfree((u8 *)param, p->length);
++
++out:
++
++	/* up(&ieee->wx_sem); */
++
++	return ret;
++
++}
++
++#ifdef CONFIG_AP_MODE
++static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len)
++{
++	int ret = 0;
++	u32 wep_key_idx, wep_key_len, wep_total_len;
++	NDIS_802_11_WEP	*pwep = NULL;
++	struct sta_info *psta = NULL, *pbcmc_sta = NULL;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct security_priv *psecuritypriv = &(padapter->securitypriv);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	param->u.crypt.err = 0;
++	param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0';
++
++	/* sizeof(struct ieee_param) = 64 bytes; */
++	/* if (param_len !=  (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) */
++	if (param_len !=  sizeof(struct ieee_param) + param->u.crypt.key_len) {
++		ret =  -EINVAL;
++		goto exit;
++	}
++
++	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
++	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
++	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) {
++		if (param->u.crypt.idx >= WEP_KEYS
++#ifdef CONFIG_IEEE80211W
++		    && param->u.crypt.idx > BIP_MAX_KEYID
++#endif /* CONFIG_IEEE80211W */
++		   ) {
++			ret = -EINVAL;
++			goto exit;
++		}
++	} else {
++		psta = rtw_get_stainfo(pstapriv, param->sta_addr);
++		if (!psta) {
++			/* ret = -EINVAL; */
++			RTW_INFO("rtw_set_encryption(), sta has already been removed or never been added\n");
++			goto exit;
++		}
++	}
++
++	if (strcmp(param->u.crypt.alg, "none") == 0 && (psta == NULL)) {
++		/* todo:clear default encryption keys */
++
++		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
++		psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled;
++		psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
++		psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
++
++		RTW_INFO("clear default encryption keys, keyid=%d\n", param->u.crypt.idx);
++
++		goto exit;
++	}
++
++
++	if (strcmp(param->u.crypt.alg, "WEP") == 0 && (psta == NULL)) {
++		RTW_INFO("r871x_set_encryption, crypt.alg = WEP\n");
++
++		wep_key_idx = param->u.crypt.idx;
++		wep_key_len = param->u.crypt.key_len;
++
++		RTW_INFO("r871x_set_encryption, wep_key_idx=%d, len=%d\n", wep_key_idx, wep_key_len);
++
++		if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) {
++			ret = -EINVAL;
++			goto exit;
++		}
++
++
++		if (wep_key_len > 0) {
++			wep_key_len = wep_key_len <= 5 ? 5 : 13;
++			wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial);
++			pwep = (NDIS_802_11_WEP *)rtw_malloc(wep_total_len);
++			if (pwep == NULL) {
++				RTW_INFO(" r871x_set_encryption: pwep allocate fail !!!\n");
++				goto exit;
++			}
++
++			_rtw_memset(pwep, 0, wep_total_len);
++
++			pwep->KeyLength = wep_key_len;
++			pwep->Length = wep_total_len;
++
++		}
++
++		pwep->KeyIndex = wep_key_idx;
++
++		_rtw_memcpy(pwep->KeyMaterial,  param->u.crypt.key, pwep->KeyLength);
++
++		if (param->u.crypt.set_tx) {
++			RTW_INFO("wep, set_tx=1\n");
++
++			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
++			psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
++			psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
++			psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
++
++			if (pwep->KeyLength == 13) {
++				psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
++				psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
++			}
++
++
++			psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;
++
++			_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength);
++
++			psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength;
++
++			rtw_ap_set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx, 1);
++		} else {
++			RTW_INFO("wep, set_tx=0\n");
++
++			/* don't update "psecuritypriv->dot11PrivacyAlgrthm" and  */
++			/* "psecuritypriv->dot11PrivacyKeyIndex=keyid", but can rtw_set_key to cam */
++
++			_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength);
++
++			psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength;
++
++			rtw_ap_set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx, 0);
++		}
++
++		goto exit;
++
++	}
++
++
++	if (!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) /*  */ { /* group key */
++		if (param->u.crypt.set_tx == 1) {
++			if (strcmp(param->u.crypt.alg, "WEP") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set WEP TX GTK idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++				psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
++				if (param->u.crypt.key_len == 13)
++					psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
++
++			} else if (strcmp(param->u.crypt.alg, "TKIP") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set TKIP TX GTK idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++				psecuritypriv->dot118021XGrpPrivacy = _TKIP_;
++				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++				/* set mic key */
++				_rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);
++				_rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);
++				psecuritypriv->busetkipkey = _TRUE;
++
++			} else if (strcmp(param->u.crypt.alg, "CCMP") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set CCMP TX GTK idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++				psecuritypriv->dot118021XGrpPrivacy = _AES_;
++				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++
++			#ifdef CONFIG_IEEE80211W
++			} else if (strcmp(param->u.crypt.alg, "BIP") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" set TX IGTK idx:%u, len:%u\n"
++					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
++				_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++				psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
++				psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq);
++				psecuritypriv->binstallBIPkey = _TRUE;
++				goto exit;
++			#endif /* CONFIG_IEEE80211W */
++
++			} else if (strcmp(param->u.crypt.alg, "none") == 0) {
++				RTW_INFO(FUNC_ADPT_FMT" clear group key, idx:%u\n"
++					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx);
++				psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
++			} else {
++				RTW_WARN(FUNC_ADPT_FMT" set group key, not support\n"
++					, FUNC_ADPT_ARG(padapter));
++				goto exit;
++			}
++
++			psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx;
++			pbcmc_sta = rtw_get_bcmc_stainfo(padapter);
++			if (pbcmc_sta) {
++				pbcmc_sta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
++				pbcmc_sta->ieee8021x_blocked = _FALSE;
++				pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy			 */
++			}
++			psecuritypriv->binstallGrpkey = _TRUE;
++			psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */
++
++			rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx);
++		}
++
++		goto exit;
++
++	}
++
++	if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) { /* psk/802_1x */
++		if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
++			if (param->u.crypt.set_tx == 1) {
++				_rtw_memcpy(psta->dot118021x_UncstKey.skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
++
++				if (strcmp(param->u.crypt.alg, "WEP") == 0) {
++					RTW_INFO(FUNC_ADPT_FMT" set WEP PTK of "MAC_FMT" idx:%u, len:%u\n"
++						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++						, param->u.crypt.idx, param->u.crypt.key_len);
++					psta->dot118021XPrivacy = _WEP40_;
++					if (param->u.crypt.key_len == 13)
++						psta->dot118021XPrivacy = _WEP104_;
++
++				} else if (strcmp(param->u.crypt.alg, "TKIP") == 0) {
++					RTW_INFO(FUNC_ADPT_FMT" set TKIP PTK of "MAC_FMT" idx:%u, len:%u\n"
++						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++						, param->u.crypt.idx, param->u.crypt.key_len);
++					psta->dot118021XPrivacy = _TKIP_;
++					/* set mic key */
++					_rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);
++					_rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);
++					psecuritypriv->busetkipkey = _TRUE;
++
++				} else if (strcmp(param->u.crypt.alg, "CCMP") == 0) {
++					RTW_INFO(FUNC_ADPT_FMT" set CCMP PTK of "MAC_FMT" idx:%u, len:%u\n"
++						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++						, param->u.crypt.idx, param->u.crypt.key_len);
++					psta->dot118021XPrivacy = _AES_;
++
++				} else if (strcmp(param->u.crypt.alg, "none") == 0) {
++					RTW_INFO(FUNC_ADPT_FMT" clear pairwise key of "MAC_FMT" idx:%u\n"
++						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
++						, param->u.crypt.idx);
++					psta->dot118021XPrivacy = _NO_PRIVACY_;
++
++				} else {
++					RTW_WARN(FUNC_ADPT_FMT" set pairwise key of "MAC_FMT", not support\n"
++						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
++					goto exit;
++				}
++
++				psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
++				psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq);
++				psta->ieee8021x_blocked = _FALSE;
++
++				if (psta->dot118021XPrivacy != _NO_PRIVACY_) {
++					psta->bpairwise_key_installed = _TRUE;
++
++					/* WPA2 key-handshake has completed */
++					if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK)
++						psta->state &= (~WIFI_UNDER_KEY_HANDSHAKE);
++				}
++
++				rtw_ap_set_pairwise_key(padapter, psta);
++			} else {
++				RTW_WARN(FUNC_ADPT_FMT" set group key of "MAC_FMT", not support\n"
++					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
++				goto exit;
++			}
++
++		}
++
++	}
++
++exit:
++
++	if (pwep)
++		rtw_mfree((u8 *)pwep, wep_total_len);
++
++	return ret;
++
++}
++
++static int rtw_set_beacon(struct net_device *dev, struct ieee_param *param, int len)
++{
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	unsigned char *pbuf = param->u.bcn_ie.buf;
++
++
++	RTW_INFO("%s, len=%d\n", __FUNCTION__, len);
++
++	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++		return -EINVAL;
++
++	_rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2);
++
++	if ((pstapriv->max_num_sta > NUM_STA) || (pstapriv->max_num_sta <= 0))
++		pstapriv->max_num_sta = NUM_STA;
++
++
++	if (rtw_check_beacon_data(padapter, pbuf, (len - 12 - 2)) == _SUCCESS) /* 12 = param header, 2:no packed */
++		ret = 0;
++	else
++		ret = -EINVAL;
++
++
++	return ret;
++
++}
++
++static int rtw_hostapd_sta_flush(struct net_device *dev)
++{
++	/* _irqL irqL; */
++	/* _list	*phead, *plist; */
++	int ret = 0;
++	/* struct sta_info *psta = NULL; */
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	/* struct sta_priv *pstapriv = &padapter->stapriv; */
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	flush_all_cam_entry(padapter);	/* clear CAM */
++#ifdef CONFIG_AP_MODE
++	ret = rtw_sta_flush(padapter, _TRUE);
++#endif
++	return ret;
++
++}
++
++static int rtw_add_sta(struct net_device *dev, struct ieee_param *param)
++{
++	int ret = 0;
++	struct sta_info *psta = NULL;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++
++	RTW_INFO("rtw_add_sta(aid=%d)=" MAC_FMT "\n", param->u.add_sta.aid, MAC_ARG(param->sta_addr));
++
++	if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE)) != _TRUE)
++		return -EINVAL;
++
++	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
++	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
++	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
++		return -EINVAL;
++
++#if 0
++	psta = rtw_get_stainfo(pstapriv, param->sta_addr);
++	if (psta) {
++		RTW_INFO("rtw_add_sta(), free has been added psta=%p\n", psta);
++		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
++		rtw_free_stainfo(padapter,  psta);
++		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
++
++		psta = NULL;
++	}
++#endif
++	/* psta = rtw_alloc_stainfo(pstapriv, param->sta_addr); */
++	psta = rtw_get_stainfo(pstapriv, param->sta_addr);
++	if (psta) {
++		int flags = param->u.add_sta.flags;
++
++		/* RTW_INFO("rtw_add_sta(), init sta's variables, psta=%p\n", psta); */
++
++		psta->cmn.aid = param->u.add_sta.aid;/* aid=1~2007 */
++
++		_rtw_memcpy(psta->bssrateset, param->u.add_sta.tx_supp_rates, 16);
++
++
++		/* check wmm cap. */
++		if (WLAN_STA_WME & flags)
++			psta->qos_option = 1;
++		else
++			psta->qos_option = 0;
++
++		if (pmlmepriv->qospriv.qos_option == 0)
++			psta->qos_option = 0;
++
++
++#ifdef CONFIG_80211N_HT
++		/* chec 802.11n ht cap. */
++		if (padapter->registrypriv.ht_enable &&
++			is_supported_ht(padapter->registrypriv.wireless_mode) &&
++			(WLAN_STA_HT & flags)) {
++			psta->htpriv.ht_option = _TRUE;
++			psta->qos_option = 1;
++			_rtw_memcpy((void *)&psta->htpriv.ht_cap, (void *)&param->u.add_sta.ht_cap, sizeof(struct rtw_ieee80211_ht_cap));
++		} else
++			psta->htpriv.ht_option = _FALSE;
++
++		if (pmlmepriv->htpriv.ht_option == _FALSE)
++			psta->htpriv.ht_option = _FALSE;
++
++#endif
++
++
++		update_sta_info_apmode(padapter, psta);
++
++
++	} else
++		ret = -ENOMEM;
++
++	return ret;
++
++}
++
++static int rtw_del_sta(struct net_device *dev, struct ieee_param *param)
++{
++	_irqL irqL;
++	int ret = 0;
++	struct sta_info *psta = NULL;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++
++	RTW_INFO("rtw_del_sta=" MAC_FMT "\n", MAC_ARG(param->sta_addr));
++
++	if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE)) != _TRUE)
++		return -EINVAL;
++
++	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
++	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
++	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
++		return -EINVAL;
++
++	psta = rtw_get_stainfo(pstapriv, param->sta_addr);
++	if (psta) {
++		u8 updated = _FALSE;
++
++		/* RTW_INFO("free psta=%p, aid=%d\n", psta, psta->cmn.aid); */
++
++		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++		if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
++			rtw_list_delete(&psta->asoc_list);
++			pstapriv->asoc_list_cnt--;
++			#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++			if (psta->tbtx_enable)
++				pstapriv->tbtx_asoc_list_cnt--;
++			#endif
++			updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _TRUE);
++
++		}
++		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
++
++		associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
++
++		psta = NULL;
++
++	} else {
++		RTW_INFO("rtw_del_sta(), sta has already been removed or never been added\n");
++
++		/* ret = -1; */
++	}
++
++
++	return ret;
++
++}
++
++static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *param, int len)
++{
++	int ret = 0;
++	struct sta_info *psta = NULL;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct ieee_param_ex *param_ex = (struct ieee_param_ex *)param;
++	struct sta_data *psta_data = (struct sta_data *)param_ex->data;
++
++	RTW_INFO("rtw_ioctl_get_sta_info, sta_addr: " MAC_FMT "\n", MAC_ARG(param_ex->sta_addr));
++
++	if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE)) != _TRUE)
++		return -EINVAL;
++
++	if (param_ex->sta_addr[0] == 0xff && param_ex->sta_addr[1] == 0xff &&
++	    param_ex->sta_addr[2] == 0xff && param_ex->sta_addr[3] == 0xff &&
++	    param_ex->sta_addr[4] == 0xff && param_ex->sta_addr[5] == 0xff)
++		return -EINVAL;
++
++	psta = rtw_get_stainfo(pstapriv, param_ex->sta_addr);
++	if (psta) {
++#if 0
++		struct {
++			u16 aid;
++			u16 capability;
++			int flags;
++			u32 sta_set;
++			u8 tx_supp_rates[16];
++			u32 tx_supp_rates_len;
++			struct rtw_ieee80211_ht_cap ht_cap;
++			u64	rx_pkts;
++			u64	rx_bytes;
++			u64	rx_drops;
++			u64	tx_pkts;
++			u64	tx_bytes;
++			u64	tx_drops;
++		} get_sta;
++#endif
++		psta_data->aid = (u16)psta->cmn.aid;
++		psta_data->capability = psta->capability;
++		psta_data->flags = psta->flags;
++
++		/*
++				nonerp_set : BIT(0)
++				no_short_slot_time_set : BIT(1)
++				no_short_preamble_set : BIT(2)
++				no_ht_gf_set : BIT(3)
++				no_ht_set : BIT(4)
++				ht_20mhz_set : BIT(5)
++		*/
++
++		psta_data->sta_set = ((psta->nonerp_set) |
++				      (psta->no_short_slot_time_set << 1) |
++				      (psta->no_short_preamble_set << 2) |
++				      (psta->no_ht_gf_set << 3) |
++				      (psta->no_ht_set << 4) |
++				      (psta->ht_20mhz_set << 5));
++
++		psta_data->tx_supp_rates_len =  psta->bssratelen;
++		_rtw_memcpy(psta_data->tx_supp_rates, psta->bssrateset, psta->bssratelen);
++#ifdef CONFIG_80211N_HT
++		if(padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode))
++			_rtw_memcpy(&psta_data->ht_cap, &psta->htpriv.ht_cap, sizeof(struct rtw_ieee80211_ht_cap));
++#endif /* CONFIG_80211N_HT */
++		psta_data->rx_pkts = psta->sta_stats.rx_data_pkts;
++		psta_data->rx_bytes = psta->sta_stats.rx_bytes;
++		psta_data->rx_drops = psta->sta_stats.rx_drops;
++
++		psta_data->tx_pkts = psta->sta_stats.tx_pkts;
++		psta_data->tx_bytes = psta->sta_stats.tx_bytes;
++		psta_data->tx_drops = psta->sta_stats.tx_drops;
++
++
++	} else
++		ret = -1;
++
++	return ret;
++
++}
++
++static int rtw_get_sta_wpaie(struct net_device *dev, struct ieee_param *param)
++{
++	int ret = 0;
++	struct sta_info *psta = NULL;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++
++	RTW_INFO("rtw_get_sta_wpaie, sta_addr: " MAC_FMT "\n", MAC_ARG(param->sta_addr));
++
++	if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE)) != _TRUE)
++		return -EINVAL;
++
++	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
++	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
++	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
++		return -EINVAL;
++
++	psta = rtw_get_stainfo(pstapriv, param->sta_addr);
++	if (psta) {
++		if ((psta->wpa_ie[0] == WLAN_EID_RSN) || (psta->wpa_ie[0] == WLAN_EID_GENERIC)) {
++			int wpa_ie_len;
++			int copy_len;
++
++			wpa_ie_len = psta->wpa_ie[1];
++
++			copy_len = ((wpa_ie_len + 2) > sizeof(psta->wpa_ie)) ? (sizeof(psta->wpa_ie)) : (wpa_ie_len + 2);
++
++			param->u.wpa_ie.len = copy_len;
++
++			_rtw_memcpy(param->u.wpa_ie.reserved, psta->wpa_ie, copy_len);
++		} else {
++			/* ret = -1; */
++			RTW_INFO("sta's wpa_ie is NONE\n");
++		}
++	} else
++		ret = -1;
++
++	return ret;
++
++}
++
++static int rtw_set_wps_beacon(struct net_device *dev, struct ieee_param *param, int len)
++{
++	int ret = 0;
++	unsigned char wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
++	int ie_len;
++
++	RTW_INFO("%s, len=%d\n", __FUNCTION__, len);
++
++	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++		return -EINVAL;
++
++	ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */
++
++
++	if (pmlmepriv->wps_beacon_ie) {
++		rtw_mfree(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len);
++		pmlmepriv->wps_beacon_ie = NULL;
++	}
++
++	if (ie_len > 0) {
++		pmlmepriv->wps_beacon_ie = rtw_malloc(ie_len);
++		pmlmepriv->wps_beacon_ie_len = ie_len;
++		if (pmlmepriv->wps_beacon_ie == NULL) {
++			RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++			return -EINVAL;
++		}
++
++		_rtw_memcpy(pmlmepriv->wps_beacon_ie, param->u.bcn_ie.buf, ie_len);
++
++		update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE, 0);
++
++		pmlmeext->bstart_bss = _TRUE;
++
++	}
++
++
++	return ret;
++
++}
++
++static int rtw_set_wps_probe_resp(struct net_device *dev, struct ieee_param *param, int len)
++{
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	int ie_len;
++
++	RTW_INFO("%s, len=%d\n", __FUNCTION__, len);
++
++	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++		return -EINVAL;
++
++	ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */
++
++
++	if (pmlmepriv->wps_probe_resp_ie) {
++		rtw_mfree(pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len);
++		pmlmepriv->wps_probe_resp_ie = NULL;
++	}
++
++	if (ie_len > 0) {
++		pmlmepriv->wps_probe_resp_ie = rtw_malloc(ie_len);
++		pmlmepriv->wps_probe_resp_ie_len = ie_len;
++		if (pmlmepriv->wps_probe_resp_ie == NULL) {
++			RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++			return -EINVAL;
++		}
++		_rtw_memcpy(pmlmepriv->wps_probe_resp_ie, param->u.bcn_ie.buf, ie_len);
++	}
++
++
++	return ret;
++
++}
++
++static int rtw_set_wps_assoc_resp(struct net_device *dev, struct ieee_param *param, int len)
++{
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	int ie_len;
++
++	RTW_INFO("%s, len=%d\n", __FUNCTION__, len);
++
++	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++		return -EINVAL;
++
++	ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */
++
++
++	if (pmlmepriv->wps_assoc_resp_ie) {
++		rtw_mfree(pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len);
++		pmlmepriv->wps_assoc_resp_ie = NULL;
++	}
++
++	if (ie_len > 0) {
++		pmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len);
++		pmlmepriv->wps_assoc_resp_ie_len = ie_len;
++		if (pmlmepriv->wps_assoc_resp_ie == NULL) {
++			RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++			return -EINVAL;
++		}
++
++		_rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, param->u.bcn_ie.buf, ie_len);
++	}
++
++
++	return ret;
++
++}
++
++static int rtw_set_hidden_ssid(struct net_device *dev, struct ieee_param *param, int len)
++{
++	int ret = 0;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *mlmepriv = &(adapter->mlmepriv);
++	struct mlme_ext_priv	*mlmeext = &(adapter->mlmeextpriv);
++	struct mlme_ext_info	*mlmeinfo = &(mlmeext->mlmext_info);
++	int ie_len;
++	u8 *ssid_ie;
++	char ssid[NDIS_802_11_LENGTH_SSID + 1];
++	sint ssid_len = 0;
++	u8 ignore_broadcast_ssid;
++
++	if (check_fwstate(mlmepriv, WIFI_AP_STATE) != _TRUE)
++		return -EPERM;
++
++	if (param->u.bcn_ie.reserved[0] != 0xea)
++		return -EINVAL;
++
++	mlmeinfo->hidden_ssid_mode = ignore_broadcast_ssid = param->u.bcn_ie.reserved[1];
++
++	ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */
++	ssid_ie = rtw_get_ie(param->u.bcn_ie.buf,  WLAN_EID_SSID, &ssid_len, ie_len);
++
++	if (ssid_ie && ssid_len > 0 && ssid_len <= NDIS_802_11_LENGTH_SSID) {
++		WLAN_BSSID_EX *pbss_network = &mlmepriv->cur_network.network;
++		WLAN_BSSID_EX *pbss_network_ext = &mlmeinfo->network;
++
++		_rtw_memcpy(ssid, ssid_ie + 2, ssid_len);
++		ssid[ssid_len] = 0x0;
++
++		if (0)
++			RTW_INFO(FUNC_ADPT_FMT" ssid:(%s,%d), from ie:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter),
++				ssid, ssid_len,
++				pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength,
++				pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength);
++
++		_rtw_memcpy(pbss_network->Ssid.Ssid, (void *)ssid, ssid_len);
++		pbss_network->Ssid.SsidLength = ssid_len;
++		_rtw_memcpy(pbss_network_ext->Ssid.Ssid, (void *)ssid, ssid_len);
++		pbss_network_ext->Ssid.SsidLength = ssid_len;
++
++		if (0)
++			RTW_INFO(FUNC_ADPT_FMT" after ssid:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter),
++				pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength,
++				pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength);
++	}
++
++	RTW_INFO(FUNC_ADPT_FMT" ignore_broadcast_ssid:%d, %s,%d\n", FUNC_ADPT_ARG(adapter),
++		ignore_broadcast_ssid, ssid, ssid_len);
++
++	return ret;
++}
++
++#if CONFIG_RTW_MACADDR_ACL
++static int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *param, int len)
++{
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++		return -EINVAL;
++
++	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
++	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
++	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
++		return -EINVAL;
++
++	ret = rtw_acl_remove_sta(padapter, RTW_ACL_PERIOD_BSS, param->sta_addr);
++
++	return ret;
++
++}
++
++static int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *param, int len)
++{
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++		return -EINVAL;
++
++	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
++	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
++	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
++		return -EINVAL;
++
++	ret = rtw_acl_add_sta(padapter, RTW_ACL_PERIOD_BSS, param->sta_addr);
++
++	return ret;
++
++}
++
++static int rtw_ioctl_set_macaddr_acl(struct net_device *dev, struct ieee_param *param, int len)
++{
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
++		return -EINVAL;
++
++	rtw_set_macaddr_acl(padapter, RTW_ACL_PERIOD_BSS, param->u.mlme.command);
++
++	return ret;
++}
++#endif /* CONFIG_RTW_MACADDR_ACL */
++
++static int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p)
++{
++	struct ieee_param *param;
++	int ret = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	/* RTW_INFO("%s\n", __FUNCTION__); */
++
++	/*
++	* this function is expect to call in master mode, which allows no power saving
++	* so, we just check hw_init_completed
++	*/
++
++	if (!rtw_is_hw_init_completed(padapter)) {
++		ret = -EPERM;
++		goto out;
++	}
++
++
++	/* if (p->length < sizeof(struct ieee_param) || !p->pointer){ */
++	if (!p->pointer) {
++		ret = -EINVAL;
++		goto out;
++	}
++
++	param = (struct ieee_param *)rtw_malloc(p->length);
++	if (param == NULL) {
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	if (copy_from_user(param, p->pointer, p->length)) {
++		rtw_mfree((u8 *)param, p->length);
++		ret = -EFAULT;
++		goto out;
++	}
++
++	/* RTW_INFO("%s, cmd=%d\n", __FUNCTION__, param->cmd); */
++
++	switch (param->cmd) {
++	case RTL871X_HOSTAPD_FLUSH:
++
++		ret = rtw_hostapd_sta_flush(dev);
++
++		break;
++
++	case RTL871X_HOSTAPD_ADD_STA:
++
++		ret = rtw_add_sta(dev, param);
++
++		break;
++
++	case RTL871X_HOSTAPD_REMOVE_STA:
++
++		ret = rtw_del_sta(dev, param);
++
++		break;
++
++	case RTL871X_HOSTAPD_SET_BEACON:
++
++		ret = rtw_set_beacon(dev, param, p->length);
++
++		break;
++
++	case RTL871X_SET_ENCRYPTION:
++
++		ret = rtw_set_encryption(dev, param, p->length);
++
++		break;
++
++	case RTL871X_HOSTAPD_GET_WPAIE_STA:
++
++		ret = rtw_get_sta_wpaie(dev, param);
++
++		break;
++
++	case RTL871X_HOSTAPD_SET_WPS_BEACON:
++
++		ret = rtw_set_wps_beacon(dev, param, p->length);
++
++		break;
++
++	case RTL871X_HOSTAPD_SET_WPS_PROBE_RESP:
++
++		ret = rtw_set_wps_probe_resp(dev, param, p->length);
++
++		break;
++
++	case RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP:
++
++		ret = rtw_set_wps_assoc_resp(dev, param, p->length);
++
++		break;
++
++	case RTL871X_HOSTAPD_SET_HIDDEN_SSID:
++
++		ret = rtw_set_hidden_ssid(dev, param, p->length);
++
++		break;
++
++	case RTL871X_HOSTAPD_GET_INFO_STA:
++
++		ret = rtw_ioctl_get_sta_data(dev, param, p->length);
++
++		break;
++
++#if CONFIG_RTW_MACADDR_ACL
++	case RTL871X_HOSTAPD_SET_MACADDR_ACL:
++		ret = rtw_ioctl_set_macaddr_acl(dev, param, p->length);
++		break;
++	case RTL871X_HOSTAPD_ACL_ADD_STA:
++		ret = rtw_ioctl_acl_add_sta(dev, param, p->length);
++		break;
++	case RTL871X_HOSTAPD_ACL_REMOVE_STA:
++		ret = rtw_ioctl_acl_remove_sta(dev, param, p->length);
++		break;
++#endif /* CONFIG_RTW_MACADDR_ACL */
++
++	default:
++		RTW_INFO("Unknown hostapd request: %d\n", param->cmd);
++		ret = -EOPNOTSUPP;
++		break;
++
++	}
++
++	if (ret == 0 && copy_to_user(p->pointer, param, p->length))
++		ret = -EFAULT;
++
++
++	rtw_mfree((u8 *)param, p->length);
++
++out:
++
++	return ret;
++
++}
++#endif
++
++static int rtw_wx_set_priv(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *awrq,
++			   char *extra)
++{
++
++#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
++	char *ext_dbg;
++#endif
++
++	int ret = 0;
++	int len = 0;
++	char *ext;
++#ifdef CONFIG_RTW_ANDROID
++	int i;
++#endif
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct iw_point *dwrq = (struct iw_point *)awrq;
++
++	if (dwrq->length == 0)
++		return -EFAULT;
++
++	len = dwrq->length;
++	ext = rtw_vmalloc(len);
++	if (!ext)
++		return -ENOMEM;
++
++	if (copy_from_user(ext, dwrq->pointer, len)) {
++		rtw_vmfree(ext, len);
++		return -EFAULT;
++	}
++
++
++
++#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
++	ext_dbg = rtw_vmalloc(len);
++	if (!ext_dbg) {
++		rtw_vmfree(ext, len);
++		return -ENOMEM;
++	}
++
++	_rtw_memcpy(ext_dbg, ext, len);
++#endif
++
++	/* added for wps2.0 @20110524 */
++	if (dwrq->flags == 0x8766 && len > 8) {
++		u32 cp_sz;
++		struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++		u8 *probereq_wpsie = ext;
++		int probereq_wpsie_len = len;
++		u8 wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};
++
++		if ((_VENDOR_SPECIFIC_IE_ == probereq_wpsie[0]) &&
++		    (_rtw_memcmp(&probereq_wpsie[2], wps_oui, 4) == _TRUE)) {
++			cp_sz = probereq_wpsie_len > MAX_WPS_IE_LEN ? MAX_WPS_IE_LEN : probereq_wpsie_len;
++
++			if (pmlmepriv->wps_probe_req_ie) {
++				u32 free_len = pmlmepriv->wps_probe_req_ie_len;
++				pmlmepriv->wps_probe_req_ie_len = 0;
++				rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len);
++				pmlmepriv->wps_probe_req_ie = NULL;
++			}
++
++			pmlmepriv->wps_probe_req_ie = rtw_malloc(cp_sz);
++			if (pmlmepriv->wps_probe_req_ie == NULL) {
++				printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
++				ret =  -EINVAL;
++				goto FREE_EXT;
++
++			}
++
++			_rtw_memcpy(pmlmepriv->wps_probe_req_ie, probereq_wpsie, cp_sz);
++			pmlmepriv->wps_probe_req_ie_len = cp_sz;
++
++		}
++
++		goto FREE_EXT;
++
++	}
++
++	if (len >= WEXT_CSCAN_HEADER_SIZE
++		&& _rtw_memcmp(ext, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE
++	) {
++		ret = rtw_wx_set_scan(dev, info, awrq, ext);
++		goto FREE_EXT;
++	}
++
++#ifdef CONFIG_RTW_ANDROID
++	/* RTW_INFO("rtw_wx_set_priv: %s req=%s\n", dev->name, ext); */
++
++	i = rtw_android_cmdstr_to_num(ext);
++
++	switch (i) {
++	case ANDROID_WIFI_CMD_START:
++		indicate_wx_custom_event(padapter, "START");
++		break;
++	case ANDROID_WIFI_CMD_STOP:
++		indicate_wx_custom_event(padapter, "STOP");
++		break;
++	case ANDROID_WIFI_CMD_RSSI: {
++		struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++		struct	wlan_network	*pcur_network = &pmlmepriv->cur_network;
++
++		if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
++			sprintf(ext, "%s rssi %d", pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi);
++		else
++			sprintf(ext, "OK");
++	}
++		break;
++	case ANDROID_WIFI_CMD_LINKSPEED: {
++		u16 mbps = rtw_get_cur_max_rate(padapter) / 10;
++		sprintf(ext, "LINKSPEED %d", mbps);
++	}
++		break;
++	case ANDROID_WIFI_CMD_MACADDR:
++		sprintf(ext, "MACADDR = " MAC_FMT, MAC_ARG(dev->dev_addr));
++		break;
++	case ANDROID_WIFI_CMD_SCAN_ACTIVE: {
++		/* rtw_set_scan_mode(padapter, SCAN_ACTIVE); */
++		sprintf(ext, "OK");
++	}
++		break;
++	case ANDROID_WIFI_CMD_SCAN_PASSIVE: {
++		/* rtw_set_scan_mode(padapter, SCAN_PASSIVE); */
++		sprintf(ext, "OK");
++	}
++		break;
++
++	case ANDROID_WIFI_CMD_COUNTRY: {
++		char country_code[10];
++		sscanf(ext, "%*s %s", country_code);
++		rtw_set_country(padapter, country_code);
++		sprintf(ext, "OK");
++	}
++		break;
++	default:
++		#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
++		RTW_INFO("%s: %s unknowned req=%s\n", __FUNCTION__,
++			dev->name, ext_dbg);
++		#endif
++
++		sprintf(ext, "OK");
++
++	}
++
++	if (copy_to_user(dwrq->pointer, ext, min(dwrq->length, (u16)(strlen(ext) + 1))))
++		ret = -EFAULT;
++
++#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
++	RTW_INFO("%s: %s req=%s rep=%s dwrq->length=%d, strlen(ext)+1=%d\n", __FUNCTION__,
++		dev->name, ext_dbg , ext, dwrq->length, (u16)(strlen(ext) + 1));
++#endif
++#endif /* end of CONFIG_ANDROID */
++
++
++FREE_EXT:
++
++	rtw_vmfree(ext, len);
++	#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
++	rtw_vmfree(ext_dbg, len);
++	#endif
++
++	/* RTW_INFO("rtw_wx_set_priv: (SIOCSIWPRIV) %s ret=%d\n",  */
++	/*		dev->name, ret); */
++
++	return ret;
++
++}
++#ifdef CONFIG_WOWLAN
++static int rtw_wowlan_ctrl(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wowlan_ioctl_param poidparam;
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	int ret = 0;
++	systime start_time = rtw_get_current_time();
++	poidparam.subcode = 0;
++
++	RTW_INFO("+rtw_wowlan_ctrl: %s\n", extra);
++
++	if (!check_fwstate(pmlmepriv, WIFI_ASOC_STATE) &&
++		check_fwstate(pmlmepriv, WIFI_STATION_STATE) &&
++		!WOWLAN_IS_STA_MIX_MODE(padapter)) {
++#ifdef CONFIG_PNO_SUPPORT
++		pwrctrlpriv->wowlan_pno_enable = _TRUE;
++#else
++		RTW_INFO("[%s] WARNING: Please Connect With AP First!!\n", __func__);
++		goto _rtw_wowlan_ctrl_exit_free;
++#endif /* CONFIG_PNO_SUPPORT */
++	}
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY))
++		rtw_scan_abort(padapter);
++
++	if (_rtw_memcmp(extra, "enable", 6))
++
++
++		rtw_suspend_common(padapter);
++
++	else if (_rtw_memcmp(extra, "disable", 7)) {
++#ifdef CONFIG_USB_HCI
++		RTW_ENABLE_FUNC(padapter, DF_RX_BIT);
++		RTW_ENABLE_FUNC(padapter, DF_TX_BIT);
++#endif
++		rtw_resume_common(padapter);
++
++#ifdef CONFIG_PNO_SUPPORT
++		pwrctrlpriv->wowlan_pno_enable = _FALSE;
++#endif /* CONFIG_PNO_SUPPORT */
++
++	} else {
++		RTW_INFO("[%s] Invalid Parameter.\n", __func__);
++		goto _rtw_wowlan_ctrl_exit_free;
++	}
++	/* mutex_lock(&ioctl_mutex); */
++_rtw_wowlan_ctrl_exit_free:
++	RTW_INFO("-rtw_wowlan_ctrl( subcode = %d)\n", poidparam.subcode);
++	RTW_PRINT("%s in %d ms\n", __func__,
++		  rtw_get_passing_time_ms(start_time));
++	return ret;
++}
++
++/*
++ * IP filter This pattern if for a frame containing a ip packet:
++ * AA:AA:AA:AA:AA:AA:BB:BB:BB:BB:BB:BB:CC:CC:DD:-:-:-:-:-:-:-:-:EE:-:-:FF:FF:FF:FF:GG:GG:GG:GG:HH:HH:II:II
++ *
++ * A: Ethernet destination address
++ * B: Ethernet source address
++ * C: Ethernet protocol type
++ * D: IP header VER+Hlen, use: 0x45 (4 is for ver 4, 5 is for len 20)
++ * E: IP protocol
++ * F: IP source address ( 192.168.0.4: C0:A8:00:2C )
++ * G: IP destination address ( 192.168.0.4: C0:A8:00:2C )
++ * H: Source port (1024: 04:00)
++ * I: Destination port (1024: 04:00)
++ */
++
++static int rtw_wowlan_set_pattern(struct net_device *dev,
++				  struct iw_request_info *info,
++				  union iwreq_data *wrqu, char *extra)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct wowlan_ioctl_param poidparam;
++	int ret = 0;
++	u8 input[wrqu->data.length];
++	u8 index = 0;
++
++	poidparam.subcode = 0;
++
++	if (!check_fwstate(pmlmepriv, WIFI_ASOC_STATE) &&
++	    check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
++		ret = -EFAULT;
++		RTW_INFO("Please Connect With AP First!!\n");
++		goto _rtw_wowlan_set_pattern_exit;
++	}
++
++	if (wrqu->data.length <= 0) {
++		ret = -EFAULT;
++		RTW_INFO("ERROR: parameter length <= 0\n");
++		goto _rtw_wowlan_set_pattern_exit;
++	} else {
++		/* set pattern */
++		if (copy_from_user(input,
++				   wrqu->data.pointer, wrqu->data.length))
++			return -EFAULT;
++		/* leave PS first */
++		rtw_ps_deny(padapter, PS_DENY_IOCTL);
++		LeaveAllPowerSaveModeDirect(padapter);
++		if (strncmp(input, "pattern=", 8) == 0) {
++			if (pwrpriv->wowlan_pattern_idx >= MAX_WKFM_CAM_NUM) {
++				RTW_INFO("WARNING: priv-pattern is full(idx: %d)\n",
++					 pwrpriv->wowlan_pattern_idx);
++				RTW_INFO("WARNING: please clean priv-pattern first\n");
++				ret = -EINVAL;
++				goto _rtw_wowlan_set_pattern_exit;
++			} else {
++				index = pwrpriv->wowlan_pattern_idx;
++				ret = rtw_wowlan_parser_pattern_cmd(input,
++					    pwrpriv->patterns[index].content,
++					    &pwrpriv->patterns[index].len,
++					    pwrpriv->patterns[index].mask);
++
++				if (ret == _TRUE)
++					pwrpriv->wowlan_pattern_idx++;
++			}
++		} else if (strncmp(input, "clean", 5) == 0) {
++			poidparam.subcode = WOWLAN_PATTERN_CLEAN;
++			rtw_hal_set_hwreg(padapter,
++					  HW_VAR_WOWLAN, (u8 *)&poidparam);
++		} else if (strncmp(input, "show", 4) == 0) {
++			rtw_wow_pattern_cam_dump(padapter);
++			rtw_wow_pattern_sw_dump(padapter);
++		} else {
++			RTW_INFO("ERROR: incorrect parameter!\n");
++			ret = -EINVAL;
++		}
++		rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
++	}
++_rtw_wowlan_set_pattern_exit:
++	return ret;
++}
++#endif /* CONFIG_WOWLAN */
++
++#ifdef CONFIG_AP_WOWLAN
++static int rtw_ap_wowlan_ctrl(struct net_device *dev,
++			      struct iw_request_info *info,
++			      union iwreq_data *wrqu, char *extra)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct wowlan_ioctl_param poidparam;
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct sta_info	*psta = NULL;
++	int ret = 0;
++	systime start_time = rtw_get_current_time();
++	poidparam.subcode = 0;
++
++	RTW_INFO("+rtw_ap_wowlan_ctrl: %s\n", extra);
++
++	if (!check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
++		RTW_INFO("[%s] It is not AP mode!!\n", __func__);
++		goto _rtw_ap_wowlan_ctrl_exit_free;
++	}
++
++	if (_rtw_memcmp(extra, "enable", 6)) {
++
++		pwrctrlpriv->wowlan_ap_mode = _TRUE;
++
++		rtw_suspend_common(padapter);
++	} else if (_rtw_memcmp(extra, "disable", 7)) {
++#ifdef CONFIG_USB_HCI
++		RTW_ENABLE_FUNC(padapter, DF_RX_BIT);
++		RTW_ENABLE_FUNC(padapter, DF_TX_BIT);
++#endif
++		rtw_resume_common(padapter);
++	} else {
++		RTW_INFO("[%s] Invalid Parameter.\n", __func__);
++		goto _rtw_ap_wowlan_ctrl_exit_free;
++	}
++	/* mutex_lock(&ioctl_mutex); */
++_rtw_ap_wowlan_ctrl_exit_free:
++	RTW_INFO("-rtw_ap_wowlan_ctrl( subcode = %d)\n", poidparam.subcode);
++	RTW_PRINT("%s in %d ms\n", __func__,
++		  rtw_get_passing_time_ms(start_time));
++_rtw_ap_wowlan_ctrl_exit:
++	return ret;
++}
++#endif /* CONFIG_AP_WOWLAN */
++
++static int rtw_pm_set(struct net_device *dev,
++		      struct iw_request_info *info,
++		      union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++	unsigned	mode = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_INFO("[%s] extra = %s\n", __FUNCTION__, extra);
++
++	if (_rtw_memcmp(extra, "lps=", 4)) {
++		sscanf(extra + 4, "%u", &mode);
++		ret = rtw_pm_set_lps(padapter, mode);
++	} else if (_rtw_memcmp(extra, "ips=", 4)) {
++		sscanf(extra + 4, "%u", &mode);
++		ret = rtw_pm_set_ips(padapter, mode);
++	} else if (_rtw_memcmp(extra, "lps_level=", 10)) {
++		if (sscanf(extra + 10, "%u", &mode) > 0)
++			ret = rtw_pm_set_lps_level(padapter, mode);
++#ifdef CONFIG_LPS_1T1R
++	} else if (_rtw_memcmp(extra, "lps_1t1r=", 9)) {
++		if (sscanf(extra + 9, "%u", &mode) > 0)
++			ret = rtw_pm_set_lps_1t1r(padapter, mode);
++#endif
++	}
++#ifdef CONFIG_WOWLAN
++	else if (_rtw_memcmp(extra, "wow_lps=", 8)) {
++		sscanf(extra + 8, "%u", &mode);
++		ret = rtw_pm_set_wow_lps(padapter, mode);
++	} else if (_rtw_memcmp(extra, "wow_lps_level=", 14)) {
++		if (sscanf(extra + 14, "%u", &mode) > 0)
++			ret = rtw_pm_set_wow_lps_level(padapter, mode);
++	#ifdef CONFIG_LPS_1T1R
++	} else if (_rtw_memcmp(extra, "wow_lps_1t1r=", 13)) {
++		if (sscanf(extra + 13, "%u", &mode) > 0)
++			ret = rtw_pm_set_wow_lps_1t1r(padapter, mode);
++	#endif
++	}
++#endif /* CONFIG_WOWLAN */
++	else
++		ret = -EINVAL;
++
++	return ret;
++}
++#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
++
++int rtw_vendor_ie_get_raw_data(struct net_device *dev, u32 vendor_ie_num,
++							   char *extra, u32 length)
++{
++	int j;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	u32 vendor_ie_mask = 0;
++	char *pstring;
++
++	if (vendor_ie_num >= WLAN_MAX_VENDOR_IE_NUM) {
++		RTW_INFO("[%s] only support %d vendor ie\n", __func__ ,
++				 WLAN_MAX_VENDOR_IE_NUM);
++		return -EFAULT;
++	}
++
++	if (pmlmepriv->vendor_ielen[vendor_ie_num] == 0) {
++		RTW_INFO("[%s]  Fail, vendor_ie_num: %d is not set\n", __func__,
++				 vendor_ie_num);
++		return -EFAULT;
++	}
++
++	if (length < 2 * pmlmepriv->vendor_ielen[vendor_ie_num] + 5) {
++		RTW_INFO("[%s]  Fail, buffer size is too small\n", __func__);
++		return -EFAULT;
++	}
++
++	vendor_ie_mask = pmlmepriv->vendor_ie_mask[vendor_ie_num];
++	_rtw_memset(extra, 0, length);
++
++	pstring = extra;
++	pstring += sprintf(pstring, "%d,%x,", vendor_ie_num, vendor_ie_mask);
++
++	for (j = 0; j < pmlmepriv->vendor_ielen[vendor_ie_num]; j++)
++		pstring += sprintf(pstring, "%02x", pmlmepriv->vendor_ie[vendor_ie_num][j]);
++
++	length = pstring - extra;
++	return length;
++}
++
++int rtw_vendor_ie_get_data(struct net_device *dev, int vendor_ie_num, char *extra)
++{
++	int j;
++	char *pstring;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	u32 vendor_ie_mask = 0;
++	__u16 length = 0;
++
++	vendor_ie_mask = pmlmepriv->vendor_ie_mask[vendor_ie_num];
++	pstring = extra;
++	pstring += sprintf(pstring , "\nVendor IE num %d , Mask:%x " , vendor_ie_num , vendor_ie_mask);
++
++	if (vendor_ie_mask & WIFI_BEACON_VENDOR_IE_BIT)
++		pstring += sprintf(pstring , "[Beacon]");
++	if (vendor_ie_mask & WIFI_PROBEREQ_VENDOR_IE_BIT)
++		pstring += sprintf(pstring , "[Probe Req]");
++	if (vendor_ie_mask & WIFI_PROBERESP_VENDOR_IE_BIT)
++		pstring += sprintf(pstring , "[Probe Resp]");
++	if (vendor_ie_mask & WIFI_ASSOCREQ_VENDOR_IE_BIT)
++		pstring += sprintf(pstring , "[Assoc Req]");
++	if (vendor_ie_mask & WIFI_ASSOCRESP_VENDOR_IE_BIT)
++		pstring += sprintf(pstring , "[Assoc Resp]");
++#ifdef CONFIG_P2P
++	if (vendor_ie_mask & WIFI_P2P_PROBEREQ_VENDOR_IE_BIT)
++		pstring += sprintf(pstring , "[P2P_Probe Req]");
++	if (vendor_ie_mask & WIFI_P2P_PROBERESP_VENDOR_IE_BIT)
++		pstring += sprintf(pstring , "[P2P_Probe Resp]");
++#endif
++
++	pstring += sprintf(pstring , "\nVendor IE:\n");
++	for (j = 0 ; j < pmlmepriv->vendor_ielen[vendor_ie_num]  ; j++)
++		pstring += sprintf(pstring , "%02x" , pmlmepriv->vendor_ie[vendor_ie_num][j]);
++
++	length = pstring - extra;
++	return length;
++
++}
++
++int rtw_vendor_ie_get(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0, vendor_ie_num = 0, cmdlen;
++	struct iw_point *p;
++	u8 *ptmp;
++
++	p = &wrqu->data;
++	cmdlen = p->length;
++	if (0 == cmdlen)
++		return -EINVAL;
++
++	ptmp = (u8 *)rtw_malloc(cmdlen);
++	if (NULL == ptmp)
++		return -ENOMEM;
++
++	if (copy_from_user(ptmp, p->pointer, cmdlen)) {
++		ret = -EFAULT;
++		goto exit;
++	}
++	ret = sscanf(ptmp , "%d", &vendor_ie_num);
++	if (vendor_ie_num > WLAN_MAX_VENDOR_IE_NUM - 1) {
++		ret = -EFAULT;
++		goto exit;
++	}
++
++	wrqu->data.length = rtw_vendor_ie_get_data(dev, vendor_ie_num, extra);
++
++exit:
++	rtw_mfree(ptmp, cmdlen);
++
++	return 0;
++}
++
++int rtw_vendor_ie_set(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0, i , len = 0 , totoal_ie_len = 0 , total_ie_len_byte = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++	u32 vendor_ie_mask = 0;
++	u32 vendor_ie_num = 0;
++	u32 vendor_ie_mask_max = BIT(WLAN_MAX_VENDOR_IE_MASK_MAX) - 1;
++	u32 id, elen;
++
++	ret = sscanf(extra, "%d,%x,%*s", &vendor_ie_num , &vendor_ie_mask);
++	if (strrchr(extra , ','))
++		extra = strrchr(extra , ',') + 1;
++	else
++		return -EINVAL;
++	totoal_ie_len = strlen(extra);
++	RTW_INFO("[%s] vendor_ie_num = %d , vendor_ie_mask = 0x%x , vendor_ie = %s , len = %d\n", __func__ , vendor_ie_num , vendor_ie_mask , extra  , totoal_ie_len);
++
++	if (vendor_ie_num  > WLAN_MAX_VENDOR_IE_NUM - 1) {
++		RTW_INFO("[%s] Fail, only support %d vendor ie\n", __func__ , WLAN_MAX_VENDOR_IE_NUM);
++		return -EFAULT;
++	}
++
++	if (totoal_ie_len > WLAN_MAX_VENDOR_IE_LEN) {
++		RTW_INFO("[%s] Fail , not support ie length extend %d\n", __func__ , WLAN_MAX_VENDOR_IE_LEN);
++		return -EFAULT;
++	}
++
++	if (vendor_ie_mask > vendor_ie_mask_max) {
++		RTW_INFO("[%s] Fail, not support vendor_ie_mask more than 0x%x\n", __func__ , vendor_ie_mask_max);
++		return -EFAULT;
++	}
++
++	if (vendor_ie_mask == 0) {
++		RTW_INFO("[%s] Clear vendor_ie_num %d group\n", __func__ , vendor_ie_num);
++		goto _clear_path;
++	}
++
++	if (totoal_ie_len % 2 != 0) {
++		RTW_INFO("[%s]  Fail , IE length = %zu is odd\n" , __func__ , strlen(extra));
++		return -EFAULT;
++	}
++
++	if (totoal_ie_len > 0) {
++		for (i = 0  ; i < strlen(extra) ; i += 2) {
++			pmlmepriv->vendor_ie[vendor_ie_num][len] = key_2char2num(extra[i] , extra[i + 1]);
++			if (len == 0) {
++				id = pmlmepriv->vendor_ie[vendor_ie_num][len];
++				if (id != WLAN_EID_VENDOR_SPECIFIC) {
++					RTW_INFO("[%s] Fail , VENDOR SPECIFIC IE ID \"%x\" was not correct\n", __func__ , id);
++					goto _clear_path;
++				}
++			} else if (len == 1) {
++				total_ie_len_byte = (totoal_ie_len / 2) - 2;
++				elen = pmlmepriv->vendor_ie[vendor_ie_num][len];
++				if (elen != total_ie_len_byte) {
++					RTW_INFO("[%s] Fail , Input IE length = \"%d\"(hex:%x) bytes , not match input total IE context length \"%d\" bytes\n", __func__ , elen , elen ,
++						 total_ie_len_byte);
++					goto _clear_path;
++				}
++			}
++			len++;
++		}
++		pmlmepriv->vendor_ielen[vendor_ie_num] = len;
++	} else
++		pmlmepriv->vendor_ielen[vendor_ie_num] = 0;
++
++
++
++	if (vendor_ie_mask & WIFI_BEACON_VENDOR_IE_BIT)
++		RTW_INFO("[%s] Beacon append vendor ie\n", __func__);
++	if (vendor_ie_mask & WIFI_PROBEREQ_VENDOR_IE_BIT)
++		RTW_INFO("[%s] Probe Req append vendor ie\n", __func__);
++	if (vendor_ie_mask & WIFI_PROBERESP_VENDOR_IE_BIT)
++		RTW_INFO("[%s] Probe Resp append vendor ie\n", __func__);
++	if (vendor_ie_mask & WIFI_ASSOCREQ_VENDOR_IE_BIT)
++		RTW_INFO("[%s] Assoc Req append vendor ie\n", __func__);
++	if (vendor_ie_mask & WIFI_ASSOCRESP_VENDOR_IE_BIT)
++		RTW_INFO("[%s] Assoc Resp append vendor ie\n", __func__);
++#ifdef CONFIG_P2P
++	if (vendor_ie_mask & WIFI_P2P_PROBEREQ_VENDOR_IE_BIT)
++		RTW_INFO("[%s] P2P Probe Req append vendor ie\n", __func__);
++	if (vendor_ie_mask & WIFI_P2P_PROBERESP_VENDOR_IE_BIT)
++		RTW_INFO("[%s] P2P Probe Resp append vendor ie\n", __func__);
++#endif
++
++	pmlmepriv->vendor_ie_mask[vendor_ie_num] = vendor_ie_mask;
++
++	return ret;
++
++_clear_path:
++	_rtw_memset(pmlmepriv->vendor_ie[vendor_ie_num] , 0 , sizeof(u32) * WLAN_MAX_VENDOR_IE_LEN);
++	pmlmepriv->vendor_ielen[vendor_ie_num] = 0;
++	pmlmepriv->vendor_ie_mask[vendor_ie_num] = 0;
++	return -EFAULT;
++}
++#endif
++
++static int rtw_mp_efuse_get(struct net_device *dev,
++			    struct iw_request_info *info,
++			    union iwreq_data *wdata, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	PEFUSE_HAL pEfuseHal;
++	struct iw_point *wrqu;
++
++	u8 ips_mode = IPS_NUM; /* init invalid value */
++	u8 lps_mode = PS_MODE_NUM; /* init invalid value */
++	struct pwrctrl_priv *pwrctrlpriv ;
++	u8 *data = NULL;
++	u8 *rawdata = NULL;
++	char *pch, *ptmp, *token, *tmp[3] = {0x00, 0x00, 0x00};
++	u16 i = 0, j = 0, mapLen = 0, addr = 0, cnts = 0;
++	u16 max_available_len = 0, raw_cursize = 0, raw_maxsize = 0;
++	u16 mask_len;
++	u8 mask_buf[64] = "";
++	int err;
++	char *pextra = NULL;
++#ifdef CONFIG_IOL
++	u8 org_fw_iol = padapter->registrypriv.fw_iol;/* 0:Disable, 1:enable, 2:by usb speed */
++#endif
++
++	wrqu = (struct iw_point *)wdata;
++	pwrctrlpriv = adapter_to_pwrctl(padapter);
++	pEfuseHal = &pHalData->EfuseHal;
++
++	err = 0;
++	data = rtw_zmalloc(EFUSE_BT_MAX_MAP_LEN);
++	if (data == NULL) {
++		err = -ENOMEM;
++		goto exit;
++	}
++	rawdata = rtw_zmalloc(EFUSE_BT_MAX_MAP_LEN);
++	if (rawdata == NULL) {
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	if (copy_from_user(extra, wrqu->pointer, wrqu->length)) {
++		err = -EFAULT;
++		goto exit;
++	}
++
++	*(extra + wrqu->length) = '\0';
++
++#ifdef CONFIG_LPS
++	lps_mode = pwrctrlpriv->power_mgnt;/* keep org value */
++	rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
++#endif
++
++#ifdef CONFIG_IPS
++	ips_mode = pwrctrlpriv->ips_mode;/* keep org value */
++	rtw_pm_set_ips(padapter, IPS_NONE);
++#endif
++
++	pch = extra;
++	RTW_INFO("%s: in=%s\n", __FUNCTION__, extra);
++
++	i = 0;
++	/* mac 16 "00e04c871200" rmap,00,2 */
++	while ((token = strsep(&pch, ",")) != NULL) {
++		if (i > 2)
++			break;
++		tmp[i] = token;
++		i++;
++	}
++#ifdef CONFIG_IOL
++	padapter->registrypriv.fw_iol = 0;/* 0:Disable, 1:enable, 2:by usb speed */
++#endif
++
++	if (strcmp(tmp[0], "status") == 0) {
++		sprintf(extra, "Load File efuse=%s,Load File MAC=%s"
++			, pHalData->efuse_file_status == EFUSE_FILE_FAILED ? "FAIL" : "OK"
++			, pHalData->macaddr_file_status == MACADDR_FILE_FAILED ? "FAIL" : "OK"
++		       );
++		goto exit;
++	} else if (strcmp(tmp[0], "drvmap") == 0) {
++		static u8 drvmaporder = 0;
++		u8 *efuse;
++		u32 shift, cnt;
++		u32 blksz = 0x200; /* The size of one time show, default 512 */
++		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);
++
++		efuse = pHalData->efuse_eeprom_data;
++
++		shift = blksz * drvmaporder;
++		efuse += shift;
++		cnt = mapLen - shift;
++
++		if (cnt > blksz) {
++			cnt = blksz;
++			drvmaporder++;
++		} else
++			drvmaporder = 0;
++
++		sprintf(extra, "\n");
++		for (i = 0; i < cnt; i += 16) {
++			pextra = extra + strlen(extra);
++			pextra += sprintf(pextra, "0x%02x\t", shift + i);
++			for (j = 0; j < 8; j++)
++				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
++			pextra += sprintf(pextra, "\t");
++			for (; j < 16; j++)
++				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
++			pextra += sprintf(pextra, "\n");
++		}
++		if ((shift + cnt) < mapLen)
++			pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen);
++
++	} else if (strcmp(tmp[0], "realmap") == 0) {
++		static u8 order = 0;
++		u8 *efuse;
++		u32 shift, cnt;
++		u32 blksz = 0x200; /* The size of one time show, default 512 */
++
++		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapLen, _FALSE);
++		efuse = pEfuseHal->fakeEfuseInitMap;
++		if (rtw_efuse_mask_map_read(padapter, 0, mapLen, efuse) == _FAIL) {
++			RTW_INFO("%s: read realmap Fail!!\n", __FUNCTION__);
++			err = -EFAULT;
++			goto exit;
++		}
++
++#if 0
++		RTW_INFO("OFFSET\tVALUE(hex)\n");
++		for (i = 0; i < mapLen; i += 16) {
++			RTW_INFO("0x%02x\t", i);
++			for (j = 0; j < 8; j++)
++				RTW_INFO("%02X ", efuse[i + j]);
++			RTW_INFO("\t");
++			for (; j < 16; j++)
++				RTW_INFO("%02X ", efuse[i + j]);
++			RTW_INFO("\n");
++		}
++		RTW_INFO("\n");
++#endif
++
++		shift = blksz * order;
++		efuse += shift;
++		cnt = mapLen - shift;
++		if (cnt > blksz) {
++			cnt = blksz;
++			order++;
++		} else
++			order = 0;
++
++		sprintf(extra, "\n");
++		for (i = 0; i < cnt; i += 16) {
++			pextra = extra + strlen(extra);
++			pextra += sprintf(pextra, "0x%02x\t", shift + i);
++			for (j = 0; j < 8; j++)
++				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
++			pextra += sprintf(pextra, "\t");
++			for (; j < 16; j++)
++				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
++			pextra += sprintf(pextra, "\n");
++		}
++		if ((shift + cnt) < mapLen)
++			pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen);
++	} else if (strcmp(tmp[0], "rmap") == 0) {
++		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
++			RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__);
++			err = -EINVAL;
++			goto exit;
++		}
++
++		/* rmap addr cnts */
++		addr = simple_strtoul(tmp[1], &ptmp, 16);
++		RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr);
++
++		cnts = simple_strtoul(tmp[2], &ptmp, 10);
++		if (cnts == 0) {
++			RTW_INFO("%s: rmap Fail!! cnts error!\n", __FUNCTION__);
++			err = -EINVAL;
++			goto exit;
++		}
++		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
++
++		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&max_available_len, _FALSE);
++		if ((addr + cnts) > max_available_len) {
++			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
++			err = -EINVAL;
++			goto exit;
++		}
++
++		if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) {
++			RTW_INFO("%s: rtw_efuse_mask_map_read error!\n", __func__);
++			err = -EFAULT;
++			goto exit;
++		}
++
++		/*		RTW_INFO("%s: data={", __FUNCTION__); */
++		*extra = 0;
++		pextra = extra;
++		for (i = 0; i < cnts; i++) {
++			/*			RTW_INFO("0x%02x ", data[i]); */
++			pextra += sprintf(pextra, "0x%02X ", data[i]);
++		}
++		/*		RTW_INFO("}\n"); */
++	} else if (strcmp(tmp[0], "realraw") == 0) {
++		static u8 raw_order = 0;
++		u32 shift, cnt;
++		u32 blksz = 0x200; /* The size of one time show, default 512 */
++
++		addr = 0;
++		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN , (void *)&mapLen, _FALSE);
++		RTW_INFO("Real content len = %d\n",mapLen );
++
++		if (rtw_efuse_access(padapter, _FALSE, addr, mapLen, rawdata) == _FAIL) {
++			RTW_INFO("%s: rtw_efuse_access Fail!!\n", __func__);
++			err = -EFAULT;
++			goto exit;
++		}
++
++		_rtw_memset(extra, '\0', strlen(extra));
++
++		shift = blksz * raw_order;
++		rawdata += shift;
++		cnt = mapLen - shift;
++		if (cnt > blksz) {
++			cnt = blksz;
++			raw_order++;
++		} else
++			raw_order = 0;
++
++		sprintf(extra, "\n");
++		for (i = 0; i < cnt; i += 16) {
++			pextra = extra + strlen(extra);
++			pextra += sprintf(pextra, "0x%02x\t", shift + i);
++			for (j = 0; j < 8; j++)
++				pextra += sprintf(pextra, "%02X ", rawdata[i + j]);
++			pextra += sprintf(pextra, "\t");
++			for (; j < 16; j++)
++				pextra += sprintf(pextra, "%02X ", rawdata[i + j]);
++			pextra += sprintf(pextra, "\n");
++		}
++		if ((shift + cnt) < mapLen)
++			pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen);
++
++	} else if (strcmp(tmp[0], "btrealraw") == 0) {
++		static u8 bt_raw_order = 0;
++		u32 shift, cnt;
++		u32 blksz = 0x200; /* The size of one time show, default 512 */
++
++		addr = 0;
++		EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_REAL_CONTENT_LEN, (void *)&mapLen, _FALSE);
++		RTW_INFO("Real content len = %d\n", mapLen);
++#ifdef RTW_HALMAC
++		if (rtw_efuse_bt_access(padapter, _FALSE, 0, mapLen, rawdata) == _FAIL) {
++			RTW_INFO("%s: rtw_efuse_access Fail!!\n", __func__);
++			err = -EFAULT;
++			goto exit;
++		}
++#else
++		rtw_write8(padapter, 0x35, 0x1);
++
++		if (rtw_efuse_access(padapter, _FALSE, addr, mapLen, rawdata) == _FAIL) {
++			RTW_INFO("%s: rtw_efuse_access Fail!!\n", __func__);
++			err = -EFAULT;
++			goto exit;
++		}
++#endif
++		_rtw_memset(extra, '\0', strlen(extra));
++
++		shift = blksz * bt_raw_order;
++		rawdata += shift;
++		cnt = mapLen - shift;
++		if (cnt > blksz) {
++			cnt = blksz;
++			bt_raw_order++;
++		} else
++			bt_raw_order = 0;
++
++		sprintf(extra, "\n");
++		for (i = 0; i < cnt; i += 16) {
++			pextra = extra + strlen(extra);
++			pextra += sprintf(pextra, "0x%02x\t", shift + i);
++			for (j = 0; j < 8; j++)
++				pextra += sprintf(pextra, "%02X ", rawdata[i + j]);
++			pextra += sprintf(pextra, "\t");
++			for (; j < 16; j++)
++				pextra += sprintf(pextra, "%02X ", rawdata[i + j]);
++			pextra += sprintf(pextra, "\n");
++		}
++		if ((shift + cnt) < mapLen)
++			pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen);
++
++	} else if (strcmp(tmp[0], "mac") == 0) {
++		if (hal_efuse_macaddr_offset(padapter) == -1) {
++			err = -EFAULT;
++			goto exit;
++		}
++
++		addr = hal_efuse_macaddr_offset(padapter);
++		cnts = 6;
++
++		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);
++		if ((addr + cnts) > max_available_len) {
++			RTW_INFO("%s: addr(0x%02x)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
++			err = -EFAULT;
++			goto exit;
++		}
++
++		if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) {
++			RTW_INFO("%s: rtw_efuse_mask_map_read error!\n", __func__);
++			err = -EFAULT;
++			goto exit;
++		}
++
++		/*		RTW_INFO("%s: MAC address={", __FUNCTION__); */
++		*extra = 0;
++		pextra = extra;
++		for (i = 0; i < cnts; i++) {
++			/*			RTW_INFO("%02X", data[i]); */
++			pextra += sprintf(pextra, "%02X", data[i]);
++			if (i != (cnts - 1)) {
++				/*				RTW_INFO(":"); */
++				pextra += sprintf(pextra, ":");
++			}
++		}
++		/*		RTW_INFO("}\n"); */
++	} else if (strcmp(tmp[0], "vidpid") == 0) {
++#ifdef CONFIG_RTL8188E
++#ifdef CONFIG_USB_HCI
++		addr = EEPROM_VID_88EU;
++#endif
++#ifdef CONFIG_PCI_HCI
++		addr = EEPROM_VID_88EE;
++#endif
++#endif /* CONFIG_RTL8188E */
++
++#ifdef CONFIG_RTL8192E
++#ifdef CONFIG_USB_HCI
++		addr = EEPROM_VID_8192EU;
++#endif
++#ifdef CONFIG_PCI_HCI
++		addr = EEPROM_VID_8192EE;
++#endif
++#endif /* CONFIG_RTL8192E */
++#ifdef CONFIG_RTL8723B
++		addr = EEPROM_VID_8723BU;
++#endif /* CONFIG_RTL8192E */
++
++#ifdef CONFIG_RTL8188F
++		addr = EEPROM_VID_8188FU;
++#endif /* CONFIG_RTL8188F */
++
++#ifdef CONFIG_RTL8188GTV
++		addr = EEPROM_VID_8188GTVU;
++#endif
++
++#ifdef CONFIG_RTL8703B
++#ifdef CONFIG_USB_HCI
++		addr = EEPROM_VID_8703BU;
++#endif
++#endif /* CONFIG_RTL8703B */
++
++#ifdef CONFIG_RTL8723D
++#ifdef CONFIG_USB_HCI
++		addr = EEPROM_VID_8723DU;
++#endif /* CONFIG_USB_HCI */
++#endif /* CONFIG_RTL8723D */
++
++		cnts = 4;
++
++		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);
++		if ((addr + cnts) > max_available_len) {
++			RTW_INFO("%s: addr(0x%02x)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
++			err = -EFAULT;
++			goto exit;
++		}
++		if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) {
++			RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__);
++			err = -EFAULT;
++			goto exit;
++		}
++
++		/*		RTW_INFO("%s: {VID,PID}={", __FUNCTION__); */
++		*extra = 0;
++		pextra = extra;
++		for (i = 0; i < cnts; i++) {
++			/*			RTW_INFO("0x%02x", data[i]); */
++			pextra += sprintf(pextra, "0x%02X", data[i]);
++			if (i != (cnts - 1)) {
++				/*				RTW_INFO(","); */
++				pextra += sprintf(pextra, ",");
++			}
++		}
++		/*		RTW_INFO("}\n"); */
++	} else if (strcmp(tmp[0], "ableraw") == 0) {
++#ifdef RTW_HALMAC
++		raw_maxsize = efuse_GetavailableSize(padapter);
++#else
++		efuse_GetCurrentSize(padapter, &raw_cursize);
++		raw_maxsize = efuse_GetMaxSize(padapter);
++#endif
++		sprintf(extra, "[available raw size]= %d bytes\n", raw_maxsize - raw_cursize);
++	} else if (strcmp(tmp[0], "btableraw") == 0) {
++		efuse_bt_GetCurrentSize(padapter, &raw_cursize);
++		raw_maxsize = efuse_bt_GetMaxSize(padapter);
++		sprintf(extra, "[available raw size]= %d bytes\n", raw_maxsize - raw_cursize);
++	} else if (strcmp(tmp[0], "btfmap") == 0) {
++
++		BTEfuse_PowerSwitch(padapter, 1, _TRUE);
++
++		mapLen = EFUSE_BT_MAX_MAP_LEN;
++		if (rtw_BT_efuse_map_read(padapter, 0, mapLen, pEfuseHal->BTEfuseInitMap) == _FAIL) {
++			RTW_INFO("%s: rtw_BT_efuse_map_read Fail!!\n", __FUNCTION__);
++			err = -EFAULT;
++			goto exit;
++		}
++
++		/*		RTW_INFO("OFFSET\tVALUE(hex)\n"); */
++		sprintf(extra, "\n");
++		for (i = 0; i < 512; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */
++			/*			RTW_INFO("0x%03x\t", i); */
++			pextra = extra + strlen(extra);
++			pextra += sprintf(pextra, "0x%03x\t", i);
++			for (j = 0; j < 8; j++) {
++				/*				RTW_INFO("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); */
++				pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]);
++			}
++			/*			RTW_INFO("\t"); */
++			pextra += sprintf(pextra, "\t");
++			for (; j < 16; j++) {
++				/*				RTW_INFO("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); */
++				pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]);
++			}
++			/*			RTW_INFO("\n"); */
++			pextra += sprintf(pextra, "\n");
++		}
++		/*		RTW_INFO("\n"); */
++	} else if (strcmp(tmp[0], "btbmap") == 0) {
++		BTEfuse_PowerSwitch(padapter, 1, _TRUE);
++
++		mapLen = EFUSE_BT_MAX_MAP_LEN;
++		if (rtw_BT_efuse_map_read(padapter, 0, mapLen, pEfuseHal->BTEfuseInitMap) == _FAIL) {
++			RTW_INFO("%s: rtw_BT_efuse_map_read Fail!!\n", __FUNCTION__);
++			err = -EFAULT;
++			goto exit;
++		}
++
++		/*		RTW_INFO("OFFSET\tVALUE(hex)\n"); */
++		sprintf(extra, "\n");
++		for (i = 512; i < 1024 ; i += 16) {
++			/*			RTW_INFO("0x%03x\t", i); */
++			pextra = extra + strlen(extra);
++			pextra += sprintf(pextra, "0x%03x\t", i);
++			for (j = 0; j < 8; j++) {
++				/*				RTW_INFO("%02X ", data[i+j]); */
++				pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]);
++			}
++			/*			RTW_INFO("\t"); */
++			pextra += sprintf(pextra, "\t");
++			for (; j < 16; j++) {
++				/*				RTW_INFO("%02X ", data[i+j]); */
++				pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]);
++			}
++			/*			RTW_INFO("\n"); */
++			pextra += sprintf(pextra, "\n");
++		}
++		/*		RTW_INFO("\n"); */
++	} else if (strcmp(tmp[0], "btrmap") == 0) {
++		u8 BTStatus;
++
++		rtw_write8(padapter, 0xa3, 0x05); /* For 8723AB ,8821S ? */
++		BTStatus = rtw_read8(padapter, 0xa0);
++
++		RTW_INFO("%s: Check 0xa0 BT Status =0x%x\n", __FUNCTION__, BTStatus);
++		if (BTStatus != 0x04) {
++			sprintf(extra, "BT Status not Active ,can't to read BT eFuse\n");
++			goto exit;
++		}
++
++		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
++			err = -EINVAL;
++			goto exit;
++		}
++
++		BTEfuse_PowerSwitch(padapter, 1, _TRUE);
++
++		/* rmap addr cnts */
++		addr = simple_strtoul(tmp[1], &ptmp, 16);
++		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
++
++		cnts = simple_strtoul(tmp[2], &ptmp, 10);
++		if (cnts == 0) {
++			RTW_INFO("%s: btrmap Fail!! cnts error!\n", __FUNCTION__);
++			err = -EINVAL;
++			goto exit;
++		}
++		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
++#ifndef RTW_HALMAC
++		EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);
++		if ((addr + cnts) > max_available_len) {
++			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
++			err = -EFAULT;
++			goto exit;
++		}
++#endif
++		if (rtw_BT_efuse_map_read(padapter, addr, cnts, data) == _FAIL) {
++			RTW_INFO("%s: rtw_BT_efuse_map_read error!!\n", __FUNCTION__);
++			err = -EFAULT;
++			goto exit;
++		}
++
++		*extra = 0;
++		pextra = extra;
++		/*		RTW_INFO("%s: bt efuse data={", __FUNCTION__); */
++		for (i = 0; i < cnts; i++) {
++			/*			RTW_INFO("0x%02x ", data[i]); */
++			pextra += sprintf(pextra, " 0x%02X ", data[i]);
++		}
++		/*		RTW_INFO("}\n"); */
++		RTW_INFO(FUNC_ADPT_FMT ": BT MAC=[%s]\n", FUNC_ADPT_ARG(padapter), extra);
++	} else if (strcmp(tmp[0], "btffake") == 0) {
++		/*		RTW_INFO("OFFSET\tVALUE(hex)\n"); */
++		sprintf(extra, "\n");
++		for (i = 0; i < 512; i += 16) {
++			/*			RTW_INFO("0x%03x\t", i); */
++			pextra = extra + strlen(extra);
++			pextra += sprintf(pextra, "0x%03x\t", i);
++			for (j = 0; j < 8; j++) {
++				/*				RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */
++				pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]);
++			}
++			/*			RTW_INFO("\t"); */
++			pextra += sprintf(pextra, "\t");
++			for (; j < 16; j++) {
++				/*				RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */
++				pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]);
++			}
++			/*			RTW_INFO("\n"); */
++			pextra += sprintf(pextra, "\n");
++		}
++		/*		RTW_INFO("\n"); */
++	} else if (strcmp(tmp[0], "btbfake") == 0) {
++		/*		RTW_INFO("OFFSET\tVALUE(hex)\n"); */
++		sprintf(extra, "\n");
++		for (i = 512; i < 1024; i += 16) {
++			/*			RTW_INFO("0x%03x\t", i); */
++			pextra = extra + strlen(extra);
++			pextra += sprintf(pextra, "0x%03x\t", i);
++			for (j = 0; j < 8; j++) {
++				/*				RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */
++				pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]);
++			}
++			/*			RTW_INFO("\t"); */
++			pextra += sprintf(pextra, "\t");
++			for (; j < 16; j++) {
++				/*				RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */
++				pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]);
++			}
++			/*			RTW_INFO("\n"); */
++			pextra += sprintf(pextra, "\n");
++		}
++		/*		RTW_INFO("\n"); */
++	} else if (strcmp(tmp[0], "wlrfkmap") == 0) {
++		static u8 fk_order = 0;
++		u8 *efuse;
++		u32 shift, cnt;
++		u32 blksz = 0x200; /* The size of one time show, default 512 */
++
++		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapLen, _FALSE);
++		efuse = pEfuseHal->fakeEfuseModifiedMap;
++
++		shift = blksz * fk_order;
++		efuse += shift;
++		cnt = mapLen - shift;
++		if (cnt > blksz) {
++			cnt = blksz;
++			fk_order++;
++		} else
++			fk_order = 0;
++
++		sprintf(extra, "\n");
++		for (i = 0; i < cnt; i += 16) {
++			pextra = extra + strlen(extra);
++			pextra += sprintf(pextra, "0x%02x\t", shift + i);
++			for (j = 0; j < 8; j++)
++				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
++			pextra += sprintf(pextra, "\t");
++			for (; j < 16; j++)
++				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
++			pextra += sprintf(pextra, "\n");
++		}
++		if ((shift + cnt) < mapLen)
++			pextra += sprintf(pextra, "\t...more\n");
++
++	} else if (strcmp(tmp[0], "wlrfkrmap") == 0) {
++		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
++			RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__);
++			err = -EINVAL;
++			goto exit;
++		}
++		/* rmap addr cnts */
++		addr = simple_strtoul(tmp[1], &ptmp, 16);
++		RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr);
++
++		cnts = simple_strtoul(tmp[2], &ptmp, 10);
++		if (cnts == 0) {
++			RTW_INFO("%s: rmap Fail!! cnts error!\n", __FUNCTION__);
++			err = -EINVAL;
++			goto exit;
++		}
++		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
++
++		/*		RTW_INFO("%s: data={", __FUNCTION__); */
++		*extra = 0;
++		pextra = extra;
++		for (i = 0; i < cnts; i++) {
++			RTW_INFO("wlrfkrmap = 0x%02x\n", pEfuseHal->fakeEfuseModifiedMap[addr + i]);
++			pextra += sprintf(pextra, "0x%02X ", pEfuseHal->fakeEfuseModifiedMap[addr+i]);
++		}
++	} else if (strcmp(tmp[0], "btrfkrmap") == 0) {
++		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
++			RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__);
++			err = -EINVAL;
++			goto exit;
++		}
++		/* rmap addr cnts */
++		addr = simple_strtoul(tmp[1], &ptmp, 16);
++		RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr);
++
++		cnts = simple_strtoul(tmp[2], &ptmp, 10);
++		if (cnts == 0) {
++			RTW_INFO("%s: rmap Fail!! cnts error!\n", __FUNCTION__);
++			err = -EINVAL;
++			goto exit;
++		}
++		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
++
++		/*		RTW_INFO("%s: data={", __FUNCTION__); */
++		*extra = 0;
++		pextra = extra;
++		for (i = 0; i < cnts; i++) {
++			RTW_INFO("wlrfkrmap = 0x%02x\n", pEfuseHal->fakeBTEfuseModifiedMap[addr + i]);
++			pextra += sprintf(pextra, "0x%02X ", pEfuseHal->fakeBTEfuseModifiedMap[addr+i]);
++		}
++	} else if (strcmp(tmp[0], "mask") == 0) {
++		*extra = 0;
++		mask_len = sizeof(u8) * rtw_get_efuse_mask_arraylen(padapter);
++		rtw_efuse_mask_array(padapter, mask_buf);
++
++		if (padapter->registrypriv.bFileMaskEfuse == _TRUE)
++			_rtw_memcpy(mask_buf, maskfileBuffer, mask_len);
++
++		sprintf(extra, "\n");
++		pextra = extra + strlen(extra);
++		for (i = 0; i < mask_len; i++)
++			pextra += sprintf(pextra, "0x%02X\n", mask_buf[i]);
++
++	} else if (strcmp(tmp[0], "btmask") == 0) {
++		*extra = 0;
++		mask_len = sizeof(u8) * rtw_get_bt_efuse_mask_arraylen(padapter);
++		rtw_bt_efuse_mask_array(padapter, mask_buf);
++
++		if (padapter->registrypriv.bBTFileMaskEfuse == _TRUE)
++			_rtw_memcpy(mask_buf, btmaskfileBuffer, mask_len);
++
++		sprintf(extra, "\n");
++		pextra = extra + strlen(extra);
++		for (i = 0; i < mask_len; i++)
++			pextra += sprintf(pextra, "0x%02X\n", mask_buf[i]);
++
++	} else
++		sprintf(extra, "Command not found!");
++
++exit:
++	if (data)
++		rtw_mfree(data, EFUSE_BT_MAX_MAP_LEN);
++	if (rawdata)
++		rtw_mfree(rawdata, EFUSE_BT_MAX_MAP_LEN);
++	if (!err)
++		wrqu->length = strlen(extra);
++
++	if (padapter->registrypriv.mp_mode == 0) {
++#ifdef CONFIG_IPS
++		rtw_pm_set_ips(padapter, ips_mode);
++#endif /* CONFIG_IPS */
++
++#ifdef CONFIG_LPS
++		rtw_pm_set_lps(padapter, lps_mode);
++#endif /* CONFIG_LPS */
++	}
++
++#ifdef CONFIG_IOL
++	padapter->registrypriv.fw_iol = org_fw_iol;/* 0:Disable, 1:enable, 2:by usb speed */
++#endif
++	return err;
++}
++
++
++#ifdef CONFIG_MP_INCLUDED
++static int rtw_mp_efuse_set(struct net_device *dev,
++			    struct iw_request_info *info,
++			    union iwreq_data *wdata, char *extra)
++{
++	struct iw_point *wrqu;
++	PADAPTER padapter;
++	struct pwrctrl_priv *pwrctrlpriv ;
++	PHAL_DATA_TYPE pHalData;
++	PEFUSE_HAL pEfuseHal;
++	struct hal_ops *pHalFunc;
++	struct mp_priv *pmp_priv;
++
++	u8 ips_mode = IPS_NUM; /* init invalid value */
++	u8 lps_mode = PS_MODE_NUM; /* init invalid value */
++	u32 i = 0, j = 0, jj, kk;
++	u8 *setdata = NULL;
++	u8 *ShadowMapBT = NULL;
++	u8 *ShadowMapWiFi = NULL;
++	u8 *setrawdata = NULL;
++	char *pch, *ptmp, *token, *tmp[3] = {0x00, 0x00, 0x00};
++	u16 addr = 0xFF, cnts = 0, BTStatus = 0 , max_available_len = 0;
++	u16 wifimaplen;
++	int err;
++	boolean bcmpchk = _TRUE;
++
++
++	wrqu = (struct iw_point *)wdata;
++	padapter = rtw_netdev_priv(dev);
++	pwrctrlpriv = adapter_to_pwrctl(padapter);
++	pHalData = GET_HAL_DATA(padapter);
++	pEfuseHal = &pHalData->EfuseHal;
++	pHalFunc = &padapter->hal_func;
++	pmp_priv = &padapter->mppriv;
++
++	err = 0;
++
++	if (copy_from_user(extra, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++#ifdef CONFIG_RTL8822C
++	rtw_pre_bt_efuse(padapter);
++#endif
++	*(extra + wrqu->length) = '\0';
++
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&wifimaplen, _FALSE);
++
++	setdata = rtw_zmalloc(1024);
++	if (setdata == NULL) {
++		err = -ENOMEM;
++		goto exit;
++	}
++	ShadowMapBT = rtw_malloc(EFUSE_BT_MAX_MAP_LEN);
++	if (ShadowMapBT == NULL) {
++		err = -ENOMEM;
++		goto exit;
++	}
++	ShadowMapWiFi = rtw_malloc(wifimaplen);
++	if (ShadowMapWiFi == NULL) {
++		err = -ENOMEM;
++		goto exit;
++	}
++	setrawdata = rtw_malloc(EFUSE_MAX_SIZE);
++	if (setrawdata == NULL) {
++		err = -ENOMEM;
++		goto exit;
++	}
++
++#ifdef CONFIG_LPS
++	lps_mode = pwrctrlpriv->power_mgnt;/* keep org value */
++	rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
++#endif
++
++#ifdef CONFIG_IPS
++	ips_mode = pwrctrlpriv->ips_mode;/* keep org value */
++	rtw_pm_set_ips(padapter, IPS_NONE);
++#endif
++
++	pch = extra;
++	RTW_INFO("%s: in=%s\n", __FUNCTION__, extra);
++
++	i = 0;
++	while ((token = strsep(&pch, ",")) != NULL) {
++		if (i > 2)
++			break;
++		tmp[i] = token;
++		i++;
++	}
++
++	/* tmp[0],[1],[2] */
++	/* wmap,addr,00e04c871200 */
++	if (strcmp(tmp[0], "wmap") == 0) {
++		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
++			err = -EINVAL;
++			goto exit;
++		}
++
++#ifndef RTW_HALMAC
++		/* unknown bug workaround, need to fix later */
++		addr = 0x1ff;
++		rtw_write8(padapter, EFUSE_CTRL + 1, (addr & 0xff));
++		rtw_msleep_os(10);
++		rtw_write8(padapter, EFUSE_CTRL + 2, ((addr >> 8) & 0x03));
++		rtw_msleep_os(10);
++		rtw_write8(padapter, EFUSE_CTRL + 3, 0x72);
++		rtw_msleep_os(10);
++		rtw_read8(padapter, EFUSE_CTRL);
++#endif /* RTW_HALMAC */
++
++		addr = simple_strtoul(tmp[1], &ptmp, 16);
++		addr &= 0xFFF;
++
++		cnts = strlen(tmp[2]);
++		if (cnts % 2) {
++			err = -EINVAL;
++			goto exit;
++		}
++		cnts /= 2;
++		if (cnts == 0) {
++			err = -EINVAL;
++			goto exit;
++		}
++
++		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
++		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
++		RTW_INFO("%s: map data=%s\n", __FUNCTION__, tmp[2]);
++
++		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
++			setdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
++
++		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);
++
++		if ((addr + cnts) > max_available_len) {
++			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
++			err = -EFAULT;
++			goto exit;
++		}
++
++		if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) {
++			RTW_INFO("%s: rtw_efuse_map_write error!!\n", __FUNCTION__);
++			err = -EFAULT;
++			goto exit;
++		}
++		*extra = 0;
++		RTW_INFO("%s: after rtw_efuse_map_write to _rtw_memcmp\n", __func__);
++		if (rtw_efuse_mask_map_read(padapter, addr, cnts, ShadowMapWiFi) == _SUCCESS) {
++			if (_rtw_memcmp((void *)ShadowMapWiFi , (void *)setdata, cnts)) {
++				RTW_INFO("%s: WiFi write map afterf compare success\n", __FUNCTION__);
++				sprintf(extra, "WiFi write map compare OK\n");
++				err = 0;
++				goto exit;
++			} else {
++				sprintf(extra, "WiFi write map compare FAIL\n");
++				RTW_INFO("%s: WiFi write map compare Fail\n", __FUNCTION__);
++				err = 0;
++				goto exit;
++			}
++		}
++	} else if (strcmp(tmp[0], "wraw") == 0) {
++		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
++			err = -EINVAL;
++			goto exit;
++		}
++
++		addr = simple_strtoul(tmp[1], &ptmp, 16);
++		addr &= 0xFFF;
++
++		cnts = strlen(tmp[2]);
++		if (cnts % 2) {
++			err = -EINVAL;
++			goto exit;
++		}
++		cnts /= 2;
++		if (cnts == 0) {
++			err = -EINVAL;
++			goto exit;
++		}
++
++		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
++		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
++		RTW_INFO("%s: raw data=%s\n", __FUNCTION__, tmp[2]);
++
++		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
++			setrawdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
++
++		if (rtw_efuse_access(padapter, _TRUE, addr, cnts, setrawdata) == _FAIL) {
++			RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__);
++			err = -EFAULT;
++			goto exit;
++		}
++	} else if (strcmp(tmp[0], "btwraw") == 0) {
++		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
++			err = -EINVAL;
++			goto exit;
++		}
++
++		addr = simple_strtoul(tmp[1], &ptmp, 16);
++		addr &= 0xFFF;
++
++		cnts = strlen(tmp[2]);
++		if (cnts % 2) {
++			err = -EINVAL;
++			goto exit;
++		}
++		cnts /= 2;
++		if (cnts == 0) {
++			err = -EINVAL;
++			goto exit;
++		}
++
++		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
++		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
++		RTW_INFO("%s: raw data=%s\n", __FUNCTION__, tmp[2]);
++
++		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
++			setrawdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
++#ifdef RTW_HALMAC
++		if (rtw_efuse_bt_access(padapter, _TRUE, addr, cnts, setrawdata) == _FAIL) {
++			RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__);
++			err = -EFAULT;
++			goto exit;
++		}
++#else
++		rtw_write8(padapter, 0x35, 1); /* switch bank 1 (BT)*/
++		if (rtw_efuse_access(padapter, _TRUE, addr, cnts, setrawdata) == _FAIL) {
++			RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__);
++			rtw_write8(padapter, 0x35, 0); /* switch bank 0 (WiFi)*/
++			err = -EFAULT;
++			goto exit;
++		}
++		rtw_write8(padapter, 0x35, 0); /* switch bank 0 (WiFi)*/
++#endif
++	} else if (strcmp(tmp[0], "mac") == 0) {
++		if (tmp[1] == NULL) {
++			err = -EINVAL;
++			goto exit;
++		}
++
++		/* mac,00e04c871200 */
++
++		if (hal_efuse_macaddr_offset(padapter) == -1) {
++			err = -EFAULT;
++			goto exit;
++		}
++
++		addr = hal_efuse_macaddr_offset(padapter);
++		cnts = strlen(tmp[1]);
++		if (cnts % 2) {
++			err = -EINVAL;
++			goto exit;
++		}
++		cnts /= 2;
++		if (cnts == 0) {
++			err = -EINVAL;
++			goto exit;
++		}
++		if (cnts > 6) {
++			RTW_INFO("%s: error data for mac addr=\"%s\"\n", __FUNCTION__, tmp[1]);
++			err = -EFAULT;
++			goto exit;
++		}
++
++		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
++		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
++		RTW_INFO("%s: MAC address=%s\n", __FUNCTION__, tmp[1]);
++
++		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
++			setdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
++
++		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);
++
++		if ((addr + cnts) > max_available_len) {
++			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
++			err = -EFAULT;
++			goto exit;
++		}
++
++		if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) {
++			RTW_INFO("%s: rtw_efuse_map_write error!!\n", __FUNCTION__);
++			err = -EFAULT;
++			goto exit;
++		}
++	} else if (strcmp(tmp[0], "vidpid") == 0) {
++		if (tmp[1] == NULL) {
++			err = -EINVAL;
++			goto exit;
++		}
++
++		/* pidvid,da0b7881		 */
++#ifdef CONFIG_RTL8188E
++#ifdef CONFIG_USB_HCI
++		addr = EEPROM_VID_88EU;
++#endif
++#ifdef CONFIG_PCI_HCI
++		addr = EEPROM_VID_88EE;
++#endif
++#endif /* CONFIG_RTL8188E */
++
++#ifdef CONFIG_RTL8192E
++#ifdef CONFIG_USB_HCI
++		addr = EEPROM_VID_8192EU;
++#endif
++#ifdef CONFIG_PCI_HCI
++		addr = EEPROM_VID_8192EE;
++#endif
++#endif /* CONFIG_RTL8188E */
++
++#ifdef CONFIG_RTL8723B
++		addr = EEPROM_VID_8723BU;
++#endif
++
++#ifdef CONFIG_RTL8188F
++		addr = EEPROM_VID_8188FU;
++#endif
++
++#ifdef CONFIG_RTL8188GTV
++		addr = EEPROM_VID_8188GTVU;
++#endif
++
++#ifdef CONFIG_RTL8703B
++#ifdef CONFIG_USB_HCI
++		addr = EEPROM_VID_8703BU;
++#endif /* CONFIG_USB_HCI */
++#endif /* CONFIG_RTL8703B */
++
++#ifdef CONFIG_RTL8723D
++#ifdef CONFIG_USB_HCI
++		addr = EEPROM_VID_8723DU;
++#endif /* CONFIG_USB_HCI */
++#endif /* CONFIG_RTL8723D */
++
++		cnts = strlen(tmp[1]);
++		if (cnts % 2) {
++			err = -EINVAL;
++			goto exit;
++		}
++		cnts /= 2;
++		if (cnts == 0) {
++			err = -EINVAL;
++			goto exit;
++		}
++
++		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
++		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
++		RTW_INFO("%s: VID/PID=%s\n", __FUNCTION__, tmp[1]);
++
++		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
++			setdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
++
++		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);
++		if ((addr + cnts) > max_available_len) {
++			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
++			err = -EFAULT;
++			goto exit;
++		}
++
++		if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) {
++			RTW_INFO("%s: rtw_efuse_map_write error!!\n", __FUNCTION__);
++			err = -EFAULT;
++			goto exit;
++		}
++	} else if (strcmp(tmp[0], "wldumpfake") == 0) {
++		if (wifimaplen > EFUSE_MAX_MAP_LEN)
++			cnts = EFUSE_MAX_MAP_LEN;
++		else
++			cnts = wifimaplen;
++		if (rtw_efuse_mask_map_read(padapter, 0, cnts, pEfuseHal->fakeEfuseModifiedMap) == _SUCCESS)
++			RTW_INFO("%s: WiFi hw efuse dump to Fake map success\n", __func__);
++		else {
++			RTW_INFO("%s: WiFi hw efuse dump to Fake map Fail\n", __func__);
++			err = -EFAULT;
++		}
++	} else if (strcmp(tmp[0], "btwmap") == 0) {
++		rtw_write8(padapter, 0xa3, 0x05); /* For 8723AB ,8821S ? */
++		BTStatus = rtw_read8(padapter, 0xa0);
++		RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __FUNCTION__, BTStatus);
++		if (BTStatus != 0x04) {
++			sprintf(extra, "BT Status not Active ,can't do Write\n");
++			goto exit;
++		}
++
++		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
++			err = -EINVAL;
++			goto exit;
++		}
++
++#ifndef RTW_HALMAC
++		BTEfuse_PowerSwitch(padapter, 1, _TRUE);
++		addr = 0x1ff;
++		rtw_write8(padapter, EFUSE_CTRL + 1, (addr & 0xff));
++		rtw_msleep_os(10);
++		rtw_write8(padapter, EFUSE_CTRL + 2, ((addr >> 8) & 0x03));
++		rtw_msleep_os(10);
++		rtw_write8(padapter, EFUSE_CTRL + 3, 0x72);
++		rtw_msleep_os(10);
++		rtw_read8(padapter, EFUSE_CTRL);
++		BTEfuse_PowerSwitch(padapter, 1, _FALSE);
++#endif /* RTW_HALMAC */
++
++		addr = simple_strtoul(tmp[1], &ptmp, 16);
++		addr &= 0xFFF;
++
++		cnts = strlen(tmp[2]);
++		if (cnts % 2) {
++			err = -EINVAL;
++			goto exit;
++		}
++		cnts /= 2;
++		if (cnts == 0) {
++			err = -EINVAL;
++			goto exit;
++		}
++
++		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
++		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
++		RTW_INFO("%s: BT data=%s\n", __FUNCTION__, tmp[2]);
++
++		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
++			setdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
++#ifndef RTW_HALMAC
++		EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);
++		if ((addr + cnts) > max_available_len) {
++			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
++			err = -EFAULT;
++			goto exit;
++		}
++#endif
++		if (rtw_BT_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) {
++			RTW_INFO("%s: rtw_BT_efuse_map_write error!!\n", __FUNCTION__);
++			sprintf(extra, "BT write FAIL !!!\n");
++			err = -EFAULT;
++			goto exit;
++		}
++		*extra = 0;
++		RTW_INFO("%s: after rtw_BT_efuse_map_write to _rtw_memcmp\n", __FUNCTION__);
++		if ((rtw_BT_efuse_map_read(padapter, addr, cnts, ShadowMapBT) == _SUCCESS)) {
++			if (_rtw_memcmp((void *)ShadowMapBT , (void *)setdata, cnts)) {
++				RTW_INFO("%s: BT write map compare OK BTStatus=0x%x\n", __FUNCTION__, BTStatus);
++				sprintf(extra, "BT write map compare OK");
++				err = 0;
++				goto exit;
++			} else {
++				sprintf(extra, "BT write map compare FAIL");
++				RTW_INFO("%s: BT write map compare FAIL BTStatus=0x%x\n", __FUNCTION__, BTStatus);
++				err = 0;
++				goto exit;
++			}
++		}
++	} else if (strcmp(tmp[0], "btwfake") == 0) {
++		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
++			err = -EINVAL;
++			goto exit;
++		}
++		if (pmp_priv->bprocess_mp_mode != _TRUE) {
++			RTW_INFO("%s: btwfake not to be exec, please first to mp_start\n", __FUNCTION__);
++			sprintf(extra, "Error, btwfake cant to be exec, please first to mp_start !!!!\n");
++			err = 0;
++			goto exit;
++		}
++		addr = simple_strtoul(tmp[1], &ptmp, 16);
++		addr &= 0xFFF;
++
++		cnts = strlen(tmp[2]);
++		if (cnts % 2) {
++			err = -EINVAL;
++			goto exit;
++		}
++		cnts /= 2;
++		if (cnts == 0) {
++			err = -EINVAL;
++			goto exit;
++		}
++
++		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
++		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
++		RTW_INFO("%s: BT tmp data=%s\n", __FUNCTION__, tmp[2]);
++
++		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
++			pEfuseHal->fakeBTEfuseModifiedMap[addr + jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
++	} else if (strcmp(tmp[0], "btdumpfake") == 0) {
++		if (rtw_BT_efuse_map_read(padapter, 0, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _SUCCESS)
++			RTW_INFO("%s: BT read all map success\n", __FUNCTION__);
++		else {
++			RTW_INFO("%s: BT read all map Fail!\n", __FUNCTION__);
++			err = -EFAULT;
++		}
++	} else if (strcmp(tmp[0], "btfk2map") == 0) {
++
++		if (padapter->registrypriv.bBTFileMaskEfuse != _TRUE && pmp_priv->bloadBTefusemap == _TRUE) {
++			RTW_INFO("%s: File BT eFuse mask file not to be loaded\n", __FUNCTION__);
++			sprintf(extra, "Not load BT eFuse mask file yet, Please advance to use [ efuse_bt_mask ], now remove the Adapter.!!!!\n");
++			rtw_set_surprise_removed(padapter);
++			err = 0;
++			goto exit;
++		}
++
++		rtw_write8(padapter, 0xa3, 0x05);
++		BTStatus = rtw_read8(padapter, 0xa0);
++		RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __FUNCTION__, BTStatus);
++		if (BTStatus != 0x04) {
++			sprintf(extra, "BT Status not Active Write FAIL\n");
++			goto exit;
++		}
++		if (pmp_priv->bprocess_mp_mode != _TRUE) {
++			RTW_INFO("%s: btfk2map not to be exec, please first to mp_start\n", __FUNCTION__);
++			sprintf(extra, "Error, btfk2map cant to be exec, please first to mp_start !!!!\n");
++			err = 0;
++			goto exit;
++		}
++#ifndef RTW_HALMAC
++		BTEfuse_PowerSwitch(padapter, 1, _TRUE);
++		addr = 0x1ff;
++		rtw_write8(padapter, EFUSE_CTRL + 1, (addr & 0xff));
++		rtw_msleep_os(10);
++		rtw_write8(padapter, EFUSE_CTRL + 2, ((addr >> 8) & 0x03));
++		rtw_msleep_os(10);
++		rtw_write8(padapter, EFUSE_CTRL + 3, 0x72);
++		rtw_msleep_os(10);
++		rtw_read8(padapter, EFUSE_CTRL);
++		BTEfuse_PowerSwitch(padapter, 1, _FALSE);
++#endif /* RTW_HALMAC */
++		_rtw_memcpy(pEfuseHal->BTEfuseModifiedMap, pEfuseHal->fakeBTEfuseModifiedMap, EFUSE_BT_MAX_MAP_LEN);
++
++		if (rtw_BT_efuse_map_write(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _FAIL) {
++			RTW_INFO("%s: rtw_BT_efuse_map_write error!\n", __FUNCTION__);
++			sprintf(extra, "BT write FAIL !!!\n");
++			err = -EFAULT;
++			goto exit;
++		}
++
++		RTW_INFO("pEfuseHal->fakeBTEfuseModifiedMap OFFSET\tVALUE(hex)\n");
++		for (i = 0; i < EFUSE_BT_MAX_MAP_LEN; i += 16) {
++			printk("0x%02x\t", i);
++			for (j = 0; j < 8; j++)
++				printk("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i + j]);
++			printk("\t");
++
++			for (; j < 16; j++)
++				printk("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i + j]);
++			printk("\n");
++		}
++		printk("\n");
++#if 1
++		err = -EFAULT;
++		RTW_INFO("%s: rtw_BT_efuse_map_read _rtw_memcmp\n", __FUNCTION__);
++		if ((rtw_BT_efuse_map_read(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseInitMap) == _SUCCESS)) {
++			if (_rtw_memcmp((void *)pEfuseHal->fakeBTEfuseModifiedMap, (void *)pEfuseHal->fakeBTEfuseInitMap, EFUSE_BT_MAX_MAP_LEN)) {
++				sprintf(extra, "BT write map compare OK");
++				RTW_INFO("%s: BT write map afterf compare success BTStatus=0x%x\n", __FUNCTION__, BTStatus);
++				err = 0;
++				goto exit;
++			} else {
++				sprintf(extra, "BT write map compare FAIL");
++				if (rtw_BT_efuse_map_write(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _FAIL)
++					RTW_INFO("%s: rtw_BT_efuse_map_write compare error,retry = %d!\n", __FUNCTION__, i);
++
++				if (rtw_BT_efuse_map_read(padapter, EFUSE_BT, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseInitMap) == _SUCCESS) {
++					RTW_INFO("pEfuseHal->fakeBTEfuseInitMap OFFSET\tVALUE(hex)\n");
++
++					for (i = 0; i < EFUSE_BT_MAX_MAP_LEN; i += 16) {
++						printk("0x%02x\t", i);
++						for (j = 0; j < 8; j++)
++							printk("%02X ", pEfuseHal->fakeBTEfuseInitMap[i + j]);
++						printk("\t");
++						for (; j < 16; j++)
++							printk("%02X ", pEfuseHal->fakeBTEfuseInitMap[i + j]);
++						printk("\n");
++					}
++					printk("\n");
++				}
++				RTW_INFO("%s: BT write map afterf compare not match to write efuse try write Map again , BTStatus=0x%x\n", __FUNCTION__, BTStatus);
++				goto exit;
++			}
++		}
++#endif
++
++	} else if (strcmp(tmp[0], "wlfk2map") == 0) {
++		*extra = 0;
++
++		if (padapter->registrypriv.bFileMaskEfuse != _TRUE && pmp_priv->bloadefusemap == _TRUE) {
++			RTW_INFO("%s: File eFuse mask file not to be loaded\n", __FUNCTION__);
++			sprintf(extra, "Not load eFuse mask file yet, Please use the efuse_mask CMD, now remove the interface !!!!\n");
++			rtw_set_surprise_removed(padapter);
++			err = 0;
++			goto exit;
++		}
++
++		if (pmp_priv->bprocess_mp_mode != _TRUE) {
++			RTW_INFO("%s: wlfk2map not to be exec, please first to mp_start\n", __FUNCTION__);
++			sprintf(extra, "Error, wlfk2map cant to be exec, please first to mp_start !!!!\n");
++			err = 0;
++			goto exit;
++		}
++		if (wifimaplen > EFUSE_MAX_MAP_LEN)
++			cnts = EFUSE_MAX_MAP_LEN;
++		else
++			cnts = wifimaplen;
++		if (rtw_efuse_map_write(padapter, 0x00, cnts, pEfuseHal->fakeEfuseModifiedMap) == _FAIL) {
++			RTW_INFO("%s: rtw_efuse_map_write fakeEfuseModifiedMap error!\n", __FUNCTION__);
++			err = -EFAULT;
++			goto exit;
++		}
++
++		if (rtw_efuse_mask_map_read(padapter, 0x00, wifimaplen, ShadowMapWiFi) == _SUCCESS) {
++			addr = 0x00;
++			err = _TRUE;
++
++			for (i = 0; i < cnts; i++) {
++				if (padapter->registrypriv.boffefusemask == 0) {
++					if (padapter->registrypriv.bFileMaskEfuse == _TRUE) {
++						if (rtw_file_efuse_IsMasked(padapter, addr + i, maskfileBuffer) == _TRUE)	/*use file efuse mask. */
++							bcmpchk = _FALSE;
++					} else {
++						if (efuse_IsMasked(padapter, addr + i) == _TRUE)
++							bcmpchk = _FALSE;
++					}
++				}
++
++				if (bcmpchk == _TRUE) {
++					RTW_INFO("compare readMapWiFi[0x%02x] = %x, ModifiedMap = %x\n", addr + i, ShadowMapWiFi[ addr + i], pEfuseHal->fakeEfuseModifiedMap[addr + i]);
++					if (_rtw_memcmp((void *) &ShadowMapWiFi[addr + i], (void *)&pEfuseHal->fakeEfuseModifiedMap[addr + i], 1) == _FALSE){
++						err = _FALSE;
++						break;
++					}
++				}
++				bcmpchk = _TRUE;
++			}
++		}
++
++		if (err) {
++			RTW_INFO("%s: WiFi write map afterf compare OK\n", __FUNCTION__);
++			sprintf(extra, "WiFi write map compare OK\n");
++			err = 0;
++			goto exit;
++		} else {
++			sprintf(extra, "WiFi write map compare FAIL\n");
++			RTW_INFO("%s: WiFi write map compare Fail\n", __FUNCTION__);
++			err = 0;
++			goto exit;
++		}
++	} else if (strcmp(tmp[0], "wlwfake") == 0) {
++		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
++			err = -EINVAL;
++			goto exit;
++		}
++		if (pmp_priv->bprocess_mp_mode != _TRUE) {
++			RTW_INFO("%s: wlwfake not to be exec, please first to mp_start\n", __FUNCTION__);
++			sprintf(extra, "Error, wlwfake cant to be exec, please first to mp_start !!!!\n");
++			err = 0;
++			goto exit;
++		}
++		addr = simple_strtoul(tmp[1], &ptmp, 16);
++		addr &= 0xFFF;
++
++		cnts = strlen(tmp[2]);
++		if (cnts % 2) {
++			err = -EINVAL;
++			goto exit;
++		}
++		cnts /= 2;
++		if (cnts == 0) {
++			err = -EINVAL;
++			goto exit;
++		}
++
++		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
++		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
++		RTW_INFO("%s: map tmp data=%s\n", __FUNCTION__, tmp[2]);
++
++		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
++			pEfuseHal->fakeEfuseModifiedMap[addr + jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
++		_rtw_memset(extra, '\0', strlen(extra));
++		sprintf(extra, "wlwfake OK\n");
++
++	}
++	else if (strcmp(tmp[0], "wfakemac") == 0) {
++		if (tmp[1] == NULL) {
++			err = -EINVAL;
++			goto exit;
++		}
++		if (pmp_priv->bprocess_mp_mode != _TRUE) {
++			RTW_INFO("%s: wfakemac not to be exec, please first to mp_start\n", __FUNCTION__);
++			sprintf(extra, "Error, wfakemac cant to be exec, please first to mp_start !!!!\n");
++			err = 0;
++			goto exit;
++		}
++		/* wfakemac,00e04c871200 */
++		if (hal_efuse_macaddr_offset(padapter) == -1) {
++			err = -EFAULT;
++			goto exit;
++		}
++
++		addr = hal_efuse_macaddr_offset(padapter);
++		cnts = strlen(tmp[1]);
++		if (cnts % 2) {
++			err = -EINVAL;
++			goto exit;
++		}
++		cnts /= 2;
++		if (cnts == 0) {
++			err = -EINVAL;
++			goto exit;
++		}
++		if (cnts > 6) {
++			RTW_INFO("%s: error data for mac addr=\"%s\"\n", __FUNCTION__, tmp[1]);
++			err = -EFAULT;
++			goto exit;
++		}
++
++		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
++		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
++		RTW_INFO("%s: MAC address=%s\n", __FUNCTION__, tmp[1]);
++
++		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
++			if ((addr + jj) < EFUSE_MAX_MAP_LEN)
++				pEfuseHal->fakeEfuseModifiedMap[addr + jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
++
++		_rtw_memset(extra, '\0', strlen(extra));
++		sprintf(extra, "write mac addr to fake map OK\n");
++	} else if(strcmp(tmp[0], "update") == 0) {
++		RTW_INFO("To Use new eFuse map\n");
++		/*step read efuse/eeprom data and get mac_addr*/
++		rtw_hal_read_chip_info(padapter);
++		/* set mac addr*/
++		rtw_macaddr_cfg(adapter_mac_addr(padapter), get_hal_mac_addr(padapter));
++		_rtw_memcpy(padapter->pnetdev->dev_addr, get_hal_mac_addr(padapter), ETH_ALEN); /* set mac addr to net_device */
++
++#ifdef CONFIG_P2P
++		rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));
++#endif
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++		rtw_hal_change_macaddr_mbid(padapter, adapter_mac_addr(padapter));
++#else
++		rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */
++#endif
++		/*pHalFunc->hal_deinit(padapter);*/
++		if (pHalFunc->hal_init(padapter) == _FAIL) {
++			err = -EINVAL;
++			goto exit;
++		}
++		pHalData->current_channel = 0;
++		pHalData->current_channel_bw = CHANNEL_WIDTH_MAX;
++		pHalData->current_band_type = BAND_MAX;
++
++		_rtw_memset(extra, '\0', strlen(extra));
++		sprintf(extra, "eFuse Update OK\n");
++	} else if (strcmp(tmp[0], "analyze") == 0) {
++
++		rtw_efuse_analyze(padapter, EFUSE_WIFI, 0);
++		_rtw_memset(extra, '\0', strlen(extra));
++		sprintf(extra, "eFuse Analyze OK,please to check kernel log\n");
++	}
++exit:
++	if (setdata)
++		rtw_mfree(setdata, 1024);
++	if (ShadowMapBT)
++		rtw_mfree(ShadowMapBT, EFUSE_BT_MAX_MAP_LEN);
++	if (ShadowMapWiFi)
++		rtw_mfree(ShadowMapWiFi, wifimaplen);
++	if (setrawdata)
++		rtw_mfree(setrawdata, EFUSE_MAX_SIZE);
++
++	wrqu->length = strlen(extra);
++
++	if (padapter->registrypriv.mp_mode == 0) {
++#ifdef CONFIG_IPS
++		rtw_pm_set_ips(padapter, ips_mode);
++#endif /* CONFIG_IPS */
++
++#ifdef CONFIG_LPS
++		rtw_pm_set_lps(padapter, lps_mode);
++#endif /* CONFIG_LPS */
++	}
++
++	return err;
++}
++
++#ifdef CONFIG_RTW_CUSTOMER_STR
++static int rtw_mp_customer_str(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	union iwreq_data *wrqu, char *extra)
++{
++	_adapter *adapter = rtw_netdev_priv(dev);
++	u32 len;
++	u8 *pbuf = NULL, *pch;
++	char *ptmp;
++	u8 param[RTW_CUSTOMER_STR_LEN];
++	u8 count = 0;
++	u8 tmp;
++	u8 i;
++	u32 pos;
++	u8 ret;
++	u8 read = 0;
++
++	if (adapter->registrypriv.mp_mode != 1
++		|| !adapter->registrypriv.mp_customer_str)
++		return -EFAULT;
++
++	len = wrqu->data.length + 1;
++
++	pbuf = (u8 *)rtw_zmalloc(len);
++	if (pbuf == NULL) {
++		RTW_WARN("%s: no memory!\n", __func__);
++		return -ENOMEM;
++	}
++
++	if (copy_from_user(pbuf, wrqu->data.pointer, wrqu->data.length)) {
++		rtw_mfree(pbuf, len);
++		RTW_WARN("%s: copy from user fail!\n", __func__);
++		return -EFAULT;
++	}
++	RTW_INFO("%s: string=\"%s\"\n", __func__, pbuf);
++
++	ptmp = (char *)pbuf;
++	pch = strsep(&ptmp, ",");
++	if ((pch == NULL) || (strlen(pch) == 0)) {
++		rtw_mfree(pbuf, len);
++		RTW_INFO("%s: parameter error(no cmd)!\n", __func__);
++		return -EFAULT;
++	}
++
++	_rtw_memset(param, 0xFF, RTW_CUSTOMER_STR_LEN);
++
++	if (strcmp(pch, "read") == 0) {
++		read = 1;
++		ret = rtw_hal_customer_str_read(adapter, param);
++
++	} else if (strcmp(pch, "write") == 0) {
++		do {
++			pch = strsep(&ptmp, ":");
++			if ((pch == NULL) || (strlen(pch) == 0))
++				break;
++			if (strlen(pch) != 2
++				|| IsHexDigit(*pch) == _FALSE
++				|| IsHexDigit(*(pch + 1)) == _FALSE
++				|| sscanf(pch, "%hhx", &tmp) != 1
++			) {
++				RTW_WARN("%s: invalid 8-bit hex!\n", __func__);
++				rtw_mfree(pbuf, len);
++				return -EFAULT;
++			}
++
++			param[count++] = tmp;
++
++		} while (count < RTW_CUSTOMER_STR_LEN);
++
++		if (count == 0) {
++			rtw_mfree(pbuf, len);
++			RTW_WARN("%s: no input!\n", __func__);
++			return -EFAULT;
++		}
++		ret = rtw_hal_customer_str_write(adapter, param);
++	} else {
++		rtw_mfree(pbuf, len);
++		RTW_INFO("%s: parameter error(unknown cmd)!\n", __func__);
++		return -EFAULT;
++	}
++
++	pos = sprintf(extra, "%s: ", read ? "read" : "write");
++	if (read == 0 || ret == _SUCCESS) {
++		for (i = 0; i < RTW_CUSTOMER_STR_LEN; i++)
++			pos += sprintf(extra + pos, "%02x:", param[i]);
++		extra[pos] = 0;
++		pos--;
++	}
++	pos += sprintf(extra + pos, " %s", ret == _SUCCESS ? "OK" : "FAIL");
++
++	wrqu->data.length = strlen(extra) + 1;
++
++	rtw_mfree(pbuf, len);
++	return 0;
++}
++#endif /* CONFIG_RTW_CUSTOMER_STR */
++
++static int rtw_priv_mp_set(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wdata, char *extra)
++{
++
++	struct iw_point *wrqu = (struct iw_point *)wdata;
++	u32 subcmd = wrqu->flags;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	int status = 0;
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (!is_primary_adapter(padapter)) {
++		RTW_INFO("MP mode only primary Adapter support\n");
++		return -EIO;
++	}
++#endif
++
++	RTW_INFO("%s mutx in %d\n", __func__, subcmd);
++	_enter_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL);
++	switch (subcmd) {
++	case CTA_TEST:
++		RTW_INFO("set CTA_TEST\n");
++		status = rtw_cta_test_start(dev, info, wdata, extra);
++		break;
++	case MP_DISABLE_BT_COEXIST:
++		RTW_INFO("set case MP_DISABLE_BT_COEXIST\n");
++		status = rtw_mp_disable_bt_coexist(dev, info, wdata, extra);
++		break;
++	case MP_IQK:
++		RTW_INFO("set MP_IQK\n");
++		status = rtw_mp_iqk(dev, info, wrqu, extra);
++		break;
++	case MP_LCK:
++		RTW_INFO("set MP_LCK\n");
++		status = rtw_mp_lck(dev, info, wrqu, extra);
++	break;
++
++	default:
++		status = -EIO;
++	}
++	_exit_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL);
++	RTW_INFO("%s mutx done %d\n", __func__, subcmd);
++
++	return status;
++}
++
++static int rtw_priv_mp_get(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wdata, char *extra)
++{
++
++	struct iw_point *wrqu = (struct iw_point *)wdata;
++	u32 subcmd = wrqu->flags;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	int status = 0;
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (!is_primary_adapter(padapter)) {
++		RTW_INFO("MP mode only primary Adapter support\n");
++		return -EIO;
++	}
++#endif
++
++	RTW_INFO("%s mutx in %d\n", __func__, subcmd);
++	_enter_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL);
++
++	switch (subcmd) {
++	case MP_START:
++		RTW_INFO("set case mp_start\n");
++		status = rtw_mp_start(dev, info, wrqu, extra);
++		break;
++	case MP_STOP:
++		RTW_INFO("set case mp_stop\n");
++		status = rtw_mp_stop(dev, info, wrqu, extra);
++		break;
++	case MP_BANDWIDTH:
++		RTW_INFO("set case mp_bandwidth\n");
++		status = rtw_mp_bandwidth(dev, info, wrqu, extra);
++		break;
++	case MP_RESET_STATS:
++		RTW_INFO("set case MP_RESET_STATS\n");
++		status = rtw_mp_reset_stats(dev, info, wrqu, extra);
++		break;
++	case MP_SetRFPathSwh:
++		RTW_INFO("set MP_SetRFPathSwitch\n");
++		status = rtw_mp_SetRFPath(dev, info, wrqu, extra);
++		break;
++	case WRITE_REG:
++		status = rtw_mp_write_reg(dev, info, wrqu, extra);
++		break;
++	case WRITE_RF:
++		status = rtw_mp_write_rf(dev, info, wrqu, extra);
++		break;
++	case MP_PHYPARA:
++		RTW_INFO("mp_get  MP_PHYPARA\n");
++		status = rtw_mp_phypara(dev, info, wrqu, extra);
++		break;
++	case MP_CHANNEL:
++		RTW_INFO("set case mp_channel\n");
++		status = rtw_mp_channel(dev , info, wrqu, extra);
++		break;
++	case  MP_CHL_OFFSET:
++		RTW_INFO("set case mp_ch_offset\n");
++		status = rtw_mp_ch_offset(dev , info, wrqu, extra);
++		break;
++	case READ_REG:
++		RTW_INFO("mp_get  READ_REG\n");
++		status = rtw_mp_read_reg(dev, info, wrqu, extra);
++		break;
++	case READ_RF:
++		RTW_INFO("mp_get  READ_RF\n");
++		status = rtw_mp_read_rf(dev, info, wrqu, extra);
++		break;
++	case MP_RATE:
++		RTW_INFO("set case mp_rate\n");
++		status = rtw_mp_rate(dev, info, wrqu, extra);
++		break;
++	case MP_TXPOWER:
++		RTW_INFO("set case MP_TXPOWER\n");
++		status = rtw_mp_txpower(dev, info, wrqu, extra);
++		break;
++	case MP_ANT_TX:
++		RTW_INFO("set case MP_ANT_TX\n");
++		status = rtw_mp_ant_tx(dev, info, wrqu, extra);
++		break;
++	case MP_ANT_RX:
++		RTW_INFO("set case MP_ANT_RX\n");
++		status = rtw_mp_ant_rx(dev, info, wrqu, extra);
++		break;
++	case MP_QUERY:
++		status = rtw_mp_trx_query(dev, info, wrqu, extra);
++		break;
++	case MP_CTX:
++		RTW_INFO("set case MP_CTX\n");
++		status = rtw_mp_ctx(dev, info, wrqu, extra);
++		break;
++	case MP_ARX:
++		RTW_INFO("set case MP_ARX\n");
++		status = rtw_mp_arx(dev, info, wrqu, extra);
++		break;
++	case MP_DUMP:
++		RTW_INFO("set case MP_DUMP\n");
++		status = rtw_mp_dump(dev, info, wrqu, extra);
++		break;
++	case MP_PSD:
++		RTW_INFO("set case MP_PSD\n");
++		status = rtw_mp_psd(dev, info, wrqu, extra);
++		break;
++	case MP_THER:
++		RTW_INFO("set case MP_THER\n");
++		status = rtw_mp_thermal(dev, info, wrqu, extra);
++		break;
++	case MP_PwrCtlDM:
++		RTW_INFO("set MP_PwrCtlDM\n");
++		status = rtw_mp_PwrCtlDM(dev, info, wrqu, extra);
++		break;
++	case MP_QueryDrvStats:
++		RTW_INFO("mp_get MP_QueryDrvStats\n");
++		status = rtw_mp_QueryDrv(dev, info, wdata, extra);
++		break;
++	case MP_PWRTRK:
++		RTW_INFO("set case MP_PWRTRK\n");
++		status = rtw_mp_pwrtrk(dev, info, wrqu, extra);
++		break;
++	case MP_SET_TSSIDE:
++		RTW_INFO("set case MP_TSSI_DE\n");
++		status = rtw_mp_set_tsside(dev, info, wrqu, extra);
++		break;
++#ifdef CONFIG_MP_INCLUDED
++	case EFUSE_SET:
++		RTW_INFO("set case efuse set\n");
++		status = rtw_mp_efuse_set(dev, info, wdata, extra);
++		break;
++#endif
++	case EFUSE_GET:
++		RTW_INFO("efuse get EFUSE_GET\n");
++		status = rtw_mp_efuse_get(dev, info, wdata, extra);
++		break;
++	case MP_GET_TXPOWER_INX:
++		RTW_INFO("mp_get MP_GET_TXPOWER_INX\n");
++		status = rtw_mp_txpower_index(dev, info, wrqu, extra);
++		break;
++	case MP_GETVER:
++		RTW_INFO("mp_get MP_GETVER\n");
++		status = rtw_mp_getver(dev, info, wdata, extra);
++		break;
++	case MP_MON:
++		RTW_INFO("mp_get MP_MON\n");
++		status = rtw_mp_mon(dev, info, wdata, extra);
++		break;
++	case EFUSE_BT_MASK:
++		RTW_INFO("mp_get EFUSE_BT_MASK\n");
++		status = rtw_bt_efuse_mask_file(dev, info, wdata, extra);
++		break;
++	case EFUSE_MASK:
++		RTW_INFO("mp_get EFUSE_MASK\n");
++		status = rtw_efuse_mask_file(dev, info, wdata, extra);
++		break;
++	case EFUSE_FILE:
++		RTW_INFO("mp_get EFUSE_FILE\n");
++		status = rtw_efuse_file_map(dev, info, wdata, extra);
++		break;
++	case EFUSE_FILE_STORE:
++		RTW_INFO("mp_get EFUSE_FILE_STORE\n");
++		status = rtw_efuse_file_map_store(dev, info, wdata, extra);
++		break;
++	case MP_TX:
++		RTW_INFO("mp_get MP_TX\n");
++		status = rtw_mp_tx(dev, info, wdata, extra);
++		break;
++	case MP_RX:
++		RTW_INFO("mp_get MP_RX\n");
++		status = rtw_mp_rx(dev, info, wdata, extra);
++		break;
++	case MP_HW_TX_MODE:
++		RTW_INFO("mp_get MP_HW_TX_MODE\n");
++		status = rtw_mp_hwtx(dev, info, wdata, extra);
++		break;
++	case MP_GET_TSSIDE:
++		RTW_INFO("mp_get TSSI_DE\n");
++		status = rtw_mp_get_tsside(dev, info, wrqu, extra);
++		break;
++#ifdef CONFIG_RTW_CUSTOMER_STR
++	case MP_CUSTOMER_STR:
++		RTW_INFO("customer str\n");
++		status = rtw_mp_customer_str(dev, info, wdata, extra);
++		break;
++#endif
++	case MP_PWRLMT:
++		RTW_INFO("mp_get MP_SETPWRLMT\n");
++		status = rtw_mp_pwrlmt(dev, info, wdata, extra);
++		break;
++	case MP_PWRBYRATE:
++		RTW_INFO("mp_get MP_SETPWRBYRATE\n");
++		status = rtw_mp_pwrbyrate(dev, info, wdata, extra);
++		break;
++	case  BT_EFUSE_FILE:
++		RTW_INFO("mp_get BT EFUSE_FILE\n");
++		status = rtw_bt_efuse_file_map(dev, info, wdata, extra);
++		break;
++	case MP_SWRFPath:
++		RTW_INFO("mp_get MP_SWRFPath\n");
++		status = rtw_mp_switch_rf_path(dev, info, wrqu, extra);
++		break;
++	case MP_LINK:
++		RTW_INFO("mp_get MP_LINK\n");
++		status = rtw_mp_link(dev, info, wrqu, extra);
++		break;
++	case MP_DPK_TRK:
++		RTW_INFO("mp_get MP_DPK_TRK\n");
++		status = rtw_mp_dpk_track(dev, info, wdata, extra);
++		break;
++	case MP_DPK:
++		RTW_INFO("set MP_DPK\n");
++		status = rtw_mp_dpk(dev, info, wdata, extra);
++		break;
++	default:
++		status = -EIO;
++	}
++
++	_exit_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL);
++	RTW_INFO("%s mutx done_%d\n", __func__, subcmd);
++
++	return status;
++}
++#endif /*#if defined(CONFIG_MP_INCLUDED)*/
++
++
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++#define DBG_MP_SDIO_INDIRECT_ACCESS 1
++static int rtw_mp_sd_iread(struct net_device *dev
++			   , struct iw_request_info *info
++			   , struct iw_point *wrqu
++			   , char *extra)
++{
++	char input[16];
++	u8 width;
++	unsigned long addr;
++	u32 ret = 0;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++
++	if (wrqu->length > 16) {
++		RTW_INFO(FUNC_ADPT_FMT" wrqu->length:%d\n", FUNC_ADPT_ARG(padapter), wrqu->length);
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	if (copy_from_user(input, wrqu->pointer, wrqu->length)) {
++		RTW_INFO(FUNC_ADPT_FMT" copy_from_user fail\n", FUNC_ADPT_ARG(padapter));
++		ret = -EFAULT;
++		goto exit;
++	}
++
++	_rtw_memset(extra, 0, wrqu->length);
++
++	if (sscanf(input, "%hhu,%lx", &width, &addr) != 2) {
++		RTW_INFO(FUNC_ADPT_FMT" sscanf fail\n", FUNC_ADPT_ARG(padapter));
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	if (addr > 0x3FFF) {
++		RTW_INFO(FUNC_ADPT_FMT" addr:0x%lx\n", FUNC_ADPT_ARG(padapter), addr);
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	if (DBG_MP_SDIO_INDIRECT_ACCESS)
++		RTW_INFO(FUNC_ADPT_FMT" width:%u, addr:0x%lx\n", FUNC_ADPT_ARG(padapter), width, addr);
++
++	switch (width) {
++	case 1:
++		sprintf(extra, "0x%02x", rtw_sd_iread8(padapter, addr));
++		wrqu->length = strlen(extra);
++		break;
++	case 2:
++		sprintf(extra, "0x%04x", rtw_sd_iread16(padapter, addr));
++		wrqu->length = strlen(extra);
++		break;
++	case 4:
++		sprintf(extra, "0x%08x", rtw_sd_iread32(padapter, addr));
++		wrqu->length = strlen(extra);
++		break;
++	default:
++		wrqu->length = 0;
++		ret = -EINVAL;
++		break;
++	}
++
++exit:
++	return ret;
++}
++
++static int rtw_mp_sd_iwrite(struct net_device *dev
++			    , struct iw_request_info *info
++			    , struct iw_point *wrqu
++			    , char *extra)
++{
++	char width;
++	unsigned long addr, data;
++	int ret = 0;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	char input[32];
++
++	if (wrqu->length > 32) {
++		RTW_INFO(FUNC_ADPT_FMT" wrqu->length:%d\n", FUNC_ADPT_ARG(padapter), wrqu->length);
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	if (copy_from_user(input, wrqu->pointer, wrqu->length)) {
++		RTW_INFO(FUNC_ADPT_FMT" copy_from_user fail\n", FUNC_ADPT_ARG(padapter));
++		ret = -EFAULT;
++		goto exit;
++	}
++
++	_rtw_memset(extra, 0, wrqu->length);
++
++	if (sscanf(input, "%hhu,%lx,%lx", &width, &addr, &data) != 3) {
++		RTW_INFO(FUNC_ADPT_FMT" sscanf fail\n", FUNC_ADPT_ARG(padapter));
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	if (addr > 0x3FFF) {
++		RTW_INFO(FUNC_ADPT_FMT" addr:0x%lx\n", FUNC_ADPT_ARG(padapter), addr);
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	if (DBG_MP_SDIO_INDIRECT_ACCESS)
++		RTW_INFO(FUNC_ADPT_FMT" width:%u, addr:0x%lx, data:0x%lx\n", FUNC_ADPT_ARG(padapter), width, addr, data);
++
++	switch (width) {
++	case 1:
++		if (data > 0xFF) {
++			ret = -EINVAL;
++			break;
++		}
++		rtw_sd_iwrite8(padapter, addr, data);
++		break;
++	case 2:
++		if (data > 0xFFFF) {
++			ret = -EINVAL;
++			break;
++		}
++		rtw_sd_iwrite16(padapter, addr, data);
++		break;
++	case 4:
++		rtw_sd_iwrite32(padapter, addr, data);
++		break;
++	default:
++		wrqu->length = 0;
++		ret = -EINVAL;
++		break;
++	}
++
++exit:
++	return ret;
++}
++#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
++
++static int rtw_priv_set(struct net_device *dev,
++			struct iw_request_info *info,
++			union iwreq_data *wdata, char *extra)
++{
++	struct iw_point *wrqu = (struct iw_point *)wdata;
++	u32 subcmd = wrqu->flags;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++
++	if (padapter == NULL)
++		return -ENETDOWN;
++
++	if (padapter->bup == _FALSE) {
++		RTW_INFO(" %s fail =>(padapter->bup == _FALSE )\n", __FUNCTION__);
++		return -ENETDOWN;
++	}
++
++	if (RTW_CANNOT_RUN(padapter)) {
++		RTW_INFO("%s fail =>(bSurpriseRemoved == _TRUE) || ( bDriverStopped == _TRUE)\n", __func__);
++		return -ENETDOWN;
++	}
++
++	if (extra == NULL) {
++		wrqu->length = 0;
++		return -EIO;
++	}
++
++	if (subcmd < MP_NULL) {
++#ifdef CONFIG_MP_INCLUDED
++		rtw_priv_mp_set(dev, info, wdata, extra);
++#endif
++		return 0;
++	}
++
++	switch (subcmd) {
++#ifdef CONFIG_WOWLAN
++	case MP_WOW_ENABLE:
++		RTW_INFO("set case MP_WOW_ENABLE: %s\n", extra);
++
++		rtw_wowlan_ctrl(dev, info, wdata, extra);
++		break;
++	case MP_WOW_SET_PATTERN:
++		RTW_INFO("set case MP_WOW_SET_PATTERN: %s\n", extra);
++		rtw_wowlan_set_pattern(dev, info, wdata, extra);
++		break;
++#endif
++#ifdef CONFIG_AP_WOWLAN
++	case MP_AP_WOW_ENABLE:
++		RTW_INFO("set case MP_AP_WOW_ENABLE: %s\n", extra);
++		rtw_ap_wowlan_ctrl(dev, info, wdata, extra);
++		break;
++#endif
++#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
++	case VENDOR_IE_SET:
++		RTW_INFO("set case VENDOR_IE_SET\n");
++		rtw_vendor_ie_set(dev , info , wdata , extra);
++		break;
++#endif
++	default:
++		return -EIO;
++	}
++
++	return 0;
++}
++
++
++static int rtw_priv_get(struct net_device *dev,
++			struct iw_request_info *info,
++			union iwreq_data *wdata, char *extra)
++{
++	struct iw_point *wrqu = (struct iw_point *)wdata;
++	u32 subcmd = wrqu->flags;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct dm_struct	*p_dm = &pHalData->odmpriv;
++	struct dm_rf_calibration_struct	*p_rf_calibrate_info = &(p_dm->rf_calibrate_info);
++	struct dm_iqk_info	*p_iqk_info = &p_dm->IQK_info;
++	u32 i = 100;
++
++
++	if (padapter->bup == _FALSE) {
++		RTW_INFO(" %s fail =>(padapter->bup == _FALSE )\n", __FUNCTION__);
++		return -ENETDOWN;
++	}
++
++	if (RTW_CANNOT_RUN(padapter)) {
++		RTW_INFO("%s fail =>(padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)\n", __func__);
++		return -ENETDOWN;
++	}
++
++	if (extra == NULL) {
++		wrqu->length = 0;
++		return -EIO;
++	}
++
++	if (subcmd < MP_NULL) {
++#ifdef CONFIG_MP_INCLUDED
++		while (i > 1) {
++			if (p_rf_calibrate_info->is_iqk_in_progress) {
++				rtw_msleep_os(10);
++			} else {
++				p_iqk_info->rfk_forbidden = _TRUE;
++				break;
++			}
++			i--;
++		}
++		if (subcmd == MP_CHANNEL || subcmd == MP_BANDWIDTH || subcmd == MP_START || subcmd == MP_DPK)
++			p_iqk_info->rfk_forbidden = _FALSE;
++		rtw_priv_mp_get(dev, info, wdata, extra);
++		rtw_msleep_os(10); /* delay 5ms for sending pkt before exit adb shell operation */
++		p_iqk_info->rfk_forbidden = _FALSE;
++#endif
++	} else {
++			switch (subcmd) {
++#if defined(CONFIG_RTL8723B)
++			case MP_SetBT:
++				RTW_INFO("set MP_SetBT\n");
++				rtw_mp_SetBT(dev, info, wdata, extra);
++				break;
++#endif
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++			case MP_SD_IREAD:
++				rtw_mp_sd_iread(dev, info, wrqu, extra);
++				break;
++			case MP_SD_IWRITE:
++				rtw_mp_sd_iwrite(dev, info, wrqu, extra);
++				break;
++#endif
++#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
++			case VENDOR_IE_GET:
++				RTW_INFO("get case VENDOR_IE_GET\n");
++				rtw_vendor_ie_get(dev , info , wdata , extra);
++				break;
++#endif
++			default:
++				return -EIO;
++			}
++		}
++
++	return 0;
++}
++
++
++#ifdef CONFIG_TDLS
++static int rtw_wx_tdls_wfd_enable(struct net_device *dev,
++				  struct iw_request_info *info,
++				  union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++
++#ifdef CONFIG_WFD
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
++
++	if (extra[0] == '0')
++		rtw_tdls_wfd_enable(padapter, 0);
++	else
++		rtw_tdls_wfd_enable(padapter, 1);
++
++#endif /* CONFIG_WFD */
++
++	return ret;
++}
++
++static int rtw_tdls_weaksec(struct net_device *dev,
++			    struct iw_request_info *info,
++			    union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++
++	u8 i, j;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
++
++	if (extra[0] == '0')
++		padapter->wdinfo.wfd_tdls_weaksec = 0;
++	else
++		padapter->wdinfo.wfd_tdls_weaksec = 1;
++
++#endif /* CONFIG_TDLS */
++
++	return ret;
++}
++
++
++static int rtw_tdls_enable(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
++
++	if (extra[0] == '0')
++		rtw_disable_tdls_func(padapter, _TRUE);
++	else if (extra[0] == '1')
++		rtw_enable_tdls_func(padapter);
++#endif /* CONFIG_TDLS */
++
++	return ret;
++}
++
++static int rtw_tdls_setup(struct net_device *dev,
++			  struct iw_request_info *info,
++			  union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++#ifdef CONFIG_TDLS
++	u8 i, j;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct tdls_txmgmt txmgmt;
++#ifdef CONFIG_WFD
++	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
++#endif /* CONFIG_WFD */
++
++	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
++
++	if (wrqu->data.length - 1 != 17) {
++		RTW_INFO("[%s] length:%d != 17\n", __FUNCTION__, (wrqu->data.length - 1));
++		return ret;
++	}
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++	for (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)
++		txmgmt.peer[i] = key_2char2num(*(extra + j), *(extra + j + 1));
++
++#ifdef CONFIG_WFD
++	if (_AES_ != padapter->securitypriv.dot11PrivacyAlgrthm) {
++		/* Weak Security situation with AP. */
++		if (0 == pwdinfo->wfd_tdls_weaksec)	{
++			/* Can't send the tdls setup request out!! */
++			RTW_INFO("[%s] Current link is not AES, "
++				"SKIP sending the tdls setup request!!\n", __FUNCTION__);
++		} else
++			issue_tdls_setup_req(padapter, &txmgmt, _TRUE);
++	} else
++#endif /* CONFIG_WFD */
++	{
++		issue_tdls_setup_req(padapter, &txmgmt, _TRUE);
++	}
++#endif /* CONFIG_TDLS */
++
++	return ret;
++}
++
++static int rtw_tdls_teardown(struct net_device *dev,
++			     struct iw_request_info *info,
++			     union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++
++	u8 i, j;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct sta_info *ptdls_sta = NULL;
++	struct tdls_txmgmt txmgmt;
++
++	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
++
++	if (wrqu->data.length - 1 != 17 && wrqu->data.length - 1 != 19) {
++		RTW_INFO("[%s] length:%d != 17 or 19\n",
++			 __FUNCTION__, (wrqu->data.length - 1));
++		return ret;
++	}
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++	for (i = 0, j = 0; i < ETH_ALEN; i++, j += 3)
++		txmgmt.peer[i] = key_2char2num(*(extra + j), *(extra + j + 1));
++
++	ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), txmgmt.peer);
++
++	if (ptdls_sta != NULL) {
++		txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;
++		if (wrqu->data.length - 1 == 19)
++			issue_tdls_teardown(padapter, &txmgmt, _FALSE);
++		else
++			issue_tdls_teardown(padapter, &txmgmt, _TRUE);
++	} else
++		RTW_INFO("TDLS peer not found\n");
++#endif /* CONFIG_TDLS */
++
++	return ret;
++}
++
++static int rtw_tdls_discovery(struct net_device *dev,
++			      struct iw_request_info *info,
++			      union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct tdls_txmgmt	txmgmt;
++	int i = 0, j = 0;
++
++	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++	for (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)
++		txmgmt.peer[i] = key_2char2num(*(extra + j), *(extra + j + 1));
++
++	issue_tdls_dis_req(padapter, &txmgmt);
++
++#endif /* CONFIG_TDLS */
++
++	return ret;
++}
++
++static int rtw_tdls_ch_switch(struct net_device *dev,
++			      struct iw_request_info *info,
++			      union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_TDLS_CH_SW
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
++	u8 i, j;
++	struct sta_info *ptdls_sta = NULL;
++	u8 take_care_iqk;
++
++	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
++
++	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
++		RTW_INFO("TDLS channel switch is not allowed\n");
++		return ret;
++	}
++
++	for (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)
++		pchsw_info->addr[i] = key_2char2num(*(extra + j), *(extra + j + 1));
++
++	ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pchsw_info->addr);
++	if (ptdls_sta == NULL)
++		return ret;
++
++	pchsw_info->ch_sw_state |= TDLS_CH_SW_INITIATOR_STATE;
++
++	if (ptdls_sta != NULL) {
++		if (pchsw_info->off_ch_num == 0)
++			pchsw_info->off_ch_num = 11;
++	} else
++		RTW_INFO("TDLS peer not found\n");
++
++	rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
++
++	rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
++	if (take_care_iqk == _TRUE) {
++		u8 central_chnl;
++		u8 bw_mode;
++
++		bw_mode = (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20;
++		central_chnl = rtw_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset);
++		if (rtw_hal_ch_sw_iqk_info_search(padapter, central_chnl, bw_mode) >= 0)
++			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);
++		else
++			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_PREPARE);
++	} else
++		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);
++
++	/* issue_tdls_ch_switch_req(padapter, ptdls_sta); */
++	/* RTW_INFO("issue tdls ch switch req\n"); */
++
++#endif /* CONFIG_TDLS_CH_SW */
++#endif /* CONFIG_TDLS */
++
++	return ret;
++}
++
++static int rtw_tdls_ch_switch_off(struct net_device *dev,
++				  struct iw_request_info *info,
++				  union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_TDLS_CH_SW
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
++	u8 i, j, mac_addr[ETH_ALEN];
++	struct sta_info *ptdls_sta = NULL;
++	struct tdls_txmgmt txmgmt;
++
++	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
++
++	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
++
++	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
++		RTW_INFO("TDLS channel switch is not allowed\n");
++		return ret;
++	}
++
++	if (wrqu->data.length >= 17) {
++		for (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)
++			mac_addr[i] = key_2char2num(*(extra + j), *(extra + j + 1));
++		ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr);
++	}
++
++	if (ptdls_sta == NULL)
++		return ret;
++
++	rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL);
++
++	pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE |
++				     TDLS_CH_SWITCH_ON_STATE |
++				     TDLS_PEER_AT_OFF_STATE);
++	_rtw_memset(pchsw_info->addr, 0x00, ETH_ALEN);
++
++	ptdls_sta->ch_switch_time = 0;
++	ptdls_sta->ch_switch_timeout = 0;
++	_cancel_timer_ex(&ptdls_sta->ch_sw_timer);
++	_cancel_timer_ex(&ptdls_sta->delay_timer);
++	_cancel_timer_ex(&ptdls_sta->stay_on_base_chnl_timer);
++	_cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer);
++
++	rtw_pm_set_lps(padapter, PS_MODE_MAX);
++#endif /* CONFIG_TDLS_CH_SW */
++#endif /* CONFIG_TDLS */
++
++	return ret;
++}
++
++static int rtw_tdls_dump_ch(struct net_device *dev,
++			    struct iw_request_info *info,
++			    union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_TDLS_CH_SW
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++
++	RTW_INFO("[%s] dump_stack:%s\n", __FUNCTION__, extra);
++
++	extra[wrqu->data.length] = 0x00;
++	ptdlsinfo->chsw_info.dump_stack = rtw_atoi(extra);
++
++	return ret;
++
++#endif
++#endif /* CONFIG_TDLS */
++
++	return ret;
++}
++
++static int rtw_tdls_off_ch_num(struct net_device *dev,
++			       struct iw_request_info *info,
++			       union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_TDLS_CH_SW
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++
++	RTW_INFO("[%s] off_ch_num:%s\n", __FUNCTION__, extra);
++
++	extra[wrqu->data.length] = 0x00;
++	ptdlsinfo->chsw_info.off_ch_num = rtw_atoi(extra);
++
++	return ret;
++
++#endif
++#endif /* CONFIG_TDLS */
++
++	return ret;
++}
++
++static int rtw_tdls_ch_offset(struct net_device *dev,
++			      struct iw_request_info *info,
++			      union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_TDLS_CH_SW
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++
++	RTW_INFO("[%s] ch_offset:%s\n", __FUNCTION__, extra);
++
++	extra[wrqu->data.length] = 0x00;
++	switch (rtw_atoi(extra)) {
++	case SCA:
++		ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++		break;
++
++	case SCB:
++		ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++		break;
++
++	default:
++		ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++		break;
++	}
++
++	return ret;
++
++#endif
++#endif /* CONFIG_TDLS */
++
++	return ret;
++}
++
++static int rtw_tdls_pson(struct net_device *dev,
++			 struct iw_request_info *info,
++			 union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u8 i, j, mac_addr[ETH_ALEN];
++	struct sta_info *ptdls_sta = NULL;
++
++	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
++
++	for (i = 0, j = 0; i < ETH_ALEN; i++, j += 3)
++		mac_addr[i] = key_2char2num(*(extra + j), *(extra + j + 1));
++
++	ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr);
++
++	issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 1, 3, 500);
++
++#endif /* CONFIG_TDLS */
++
++	return ret;
++}
++
++static int rtw_tdls_psoff(struct net_device *dev,
++			  struct iw_request_info *info,
++			  union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u8 i, j, mac_addr[ETH_ALEN];
++	struct sta_info *ptdls_sta = NULL;
++
++	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
++
++	for (i = 0, j = 0; i < ETH_ALEN; i++, j += 3)
++		mac_addr[i] = key_2char2num(*(extra + j), *(extra + j + 1));
++
++	ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr);
++
++	if (ptdls_sta)
++		issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 3, 500);
++
++#endif /* CONFIG_TDLS */
++
++	return ret;
++}
++
++static int rtw_tdls_setip(struct net_device *dev,
++			  struct iw_request_info *info,
++			  union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_WFD
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++	struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info;
++	u8 i = 0, j = 0, k = 0, tag = 0;
++
++	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
++
++	while (i < 4) {
++		for (j = 0; j < 4; j++) {
++			if (*(extra + j + tag) == '.' || *(extra + j + tag) == '\0') {
++				if (j == 1)
++					pwfd_info->ip_address[i] = convert_ip_addr('0', '0', *(extra + (j - 1) + tag));
++				if (j == 2)
++					pwfd_info->ip_address[i] = convert_ip_addr('0', *(extra + (j - 2) + tag), *(extra + (j - 1) + tag));
++				if (j == 3)
++					pwfd_info->ip_address[i] = convert_ip_addr(*(extra + (j - 3) + tag), *(extra + (j - 2) + tag), *(extra + (j - 1) + tag));
++
++				tag += j + 1;
++				break;
++			}
++		}
++		i++;
++	}
++
++	RTW_INFO("[%s] Set IP = %u.%u.%u.%u\n", __FUNCTION__,
++		 ptdlsinfo->wfd_info->ip_address[0],
++		 ptdlsinfo->wfd_info->ip_address[1],
++		 ptdlsinfo->wfd_info->ip_address[2],
++		 ptdlsinfo->wfd_info->ip_address[3]);
++
++#endif /* CONFIG_WFD */
++#endif /* CONFIG_TDLS */
++
++	return ret;
++}
++
++static int rtw_tdls_getip(struct net_device *dev,
++			  struct iw_request_info *info,
++			  union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_WFD
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++	struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info;
++
++	RTW_INFO("[%s]\n", __FUNCTION__);
++
++	sprintf(extra, "\n\n%u.%u.%u.%u\n",
++		pwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1],
++		pwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3]);
++
++	RTW_INFO("[%s] IP=%u.%u.%u.%u\n", __FUNCTION__,
++		 pwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1],
++		 pwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3]);
++
++	wrqu->data.length = strlen(extra);
++
++#endif /* CONFIG_WFD */
++#endif /* CONFIG_TDLS */
++
++	return ret;
++}
++
++static int rtw_tdls_getport(struct net_device *dev,
++			    struct iw_request_info *info,
++			    union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_WFD
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++	struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info;
++
++	RTW_INFO("[%s]\n", __FUNCTION__);
++
++	sprintf(extra, "\n\n%d\n", pwfd_info->peer_rtsp_ctrlport);
++	RTW_INFO("[%s] remote port = %d\n",
++		 __FUNCTION__, pwfd_info->peer_rtsp_ctrlport);
++
++	wrqu->data.length = strlen(extra);
++
++#endif /* CONFIG_WFD */
++#endif /* CONFIG_TDLS */
++
++	return ret;
++
++}
++
++/* WFDTDLS, for sigma test */
++static int rtw_tdls_dis_result(struct net_device *dev,
++			       struct iw_request_info *info,
++			       union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++#ifdef CONFIG_WFD
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++
++	RTW_INFO("[%s]\n", __FUNCTION__);
++
++	if (ptdlsinfo->dev_discovered == _TRUE) {
++		sprintf(extra, "\n\nDis=1\n");
++		ptdlsinfo->dev_discovered = _FALSE;
++	}
++
++	wrqu->data.length = strlen(extra);
++
++#endif /* CONFIG_WFD */
++#endif /* CONFIG_TDLS */
++
++	return ret;
++
++}
++
++/* WFDTDLS, for sigma test */
++static int rtw_wfd_tdls_status(struct net_device *dev,
++			       struct iw_request_info *info,
++			       union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
++
++	RTW_INFO("[%s]\n", __FUNCTION__);
++
++	sprintf(extra, "\nlink_established:%d\n"
++		"sta_cnt:%d\n"
++		"sta_maximum:%d\n"
++		"cur_channel:%d\n"
++		"tdls_enable:%d"
++#ifdef CONFIG_TDLS_CH_SW
++		"ch_sw_state:%08x\n"
++		"chsw_on:%d\n"
++		"off_ch_num:%d\n"
++		"cur_time:%d\n"
++		"ch_offset:%d\n"
++		"delay_swtich_back:%d"
++#endif
++		,
++		ptdlsinfo->link_established, ptdlsinfo->sta_cnt,
++		ptdlsinfo->sta_maximum, ptdlsinfo->cur_channel,
++		rtw_is_tdls_enabled(padapter)
++#ifdef CONFIG_TDLS_CH_SW
++		,
++		ptdlsinfo->chsw_info.ch_sw_state,
++		ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on),
++		ptdlsinfo->chsw_info.off_ch_num,
++		ptdlsinfo->chsw_info.cur_time,
++		ptdlsinfo->chsw_info.ch_offset,
++		ptdlsinfo->chsw_info.delay_switch_back
++#endif
++	       );
++
++	wrqu->data.length = strlen(extra);
++
++#endif /* CONFIG_TDLS */
++
++	return ret;
++
++}
++
++static int rtw_tdls_getsta(struct net_device *dev,
++			   struct iw_request_info *info,
++			   union iwreq_data *wrqu, char *extra)
++{
++
++	int ret = 0;
++#ifdef CONFIG_TDLS
++	u8 i, j;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	u8 addr[ETH_ALEN] = {0};
++	char charmac[17];
++	struct sta_info *ptdls_sta = NULL;
++
++	RTW_INFO("[%s] %s %d\n", __FUNCTION__,
++		 (char *)wrqu->data.pointer, wrqu->data.length - 1);
++
++	if (copy_from_user(charmac, wrqu->data.pointer + 9, 17)) {
++		ret = -EFAULT;
++		goto exit;
++	}
++
++	RTW_INFO("[%s] %d, charmac:%s\n", __FUNCTION__, __LINE__, charmac);
++	for (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)
++		addr[i] = key_2char2num(*(charmac + j), *(charmac + j + 1));
++
++	RTW_INFO("[%s] %d, charmac:%s, addr:"MAC_FMT"\n",
++		 __FUNCTION__, __LINE__, charmac, MAC_ARG(addr));
++	ptdls_sta = rtw_get_stainfo(&padapter->stapriv, addr);
++	if (ptdls_sta) {
++		sprintf(extra, "\n\ntdls_sta_state=0x%08x\n", ptdls_sta->tdls_sta_state);
++		RTW_INFO("\n\ntdls_sta_state=%d\n", ptdls_sta->tdls_sta_state);
++	} else {
++		sprintf(extra, "\n\nNot found this sta\n");
++		RTW_INFO("\n\nNot found this sta\n");
++	}
++	wrqu->data.length = strlen(extra);
++
++exit:
++#endif /* CONFIG_TDLS */
++	return ret;
++
++}
++
++static int rtw_tdls_get_best_ch(struct net_device *dev,
++				struct iw_request_info *info,
++				union iwreq_data *wrqu, char *extra)
++{
++#ifdef CONFIG_FIND_BEST_CHANNEL
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++	u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0;
++
++	for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {
++		if (rfctl->channel_set[i].ChannelNum == 1)
++			index_24G = i;
++		if (rfctl->channel_set[i].ChannelNum == 36)
++			index_5G = i;
++	}
++
++	for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {
++		/* 2.4G */
++		if (rfctl->channel_set[i].ChannelNum == 6 || rfctl->channel_set[i].ChannelNum == 11) {
++			if (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_24G].rx_count) {
++				index_24G = i;
++				best_channel_24G = rfctl->channel_set[i].ChannelNum;
++			}
++		}
++
++		/* 5G */
++		if (rfctl->channel_set[i].ChannelNum >= 36
++		    && rfctl->channel_set[i].ChannelNum < 140) {
++			/* Find primary channel */
++			if (((rfctl->channel_set[i].ChannelNum - 36) % 8 == 0)
++			    && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {
++				index_5G = i;
++				best_channel_5G = rfctl->channel_set[i].ChannelNum;
++			}
++		}
++
++		if (rfctl->channel_set[i].ChannelNum >= 149
++		    && rfctl->channel_set[i].ChannelNum < 165) {
++			/* Find primary channel */
++			if (((rfctl->channel_set[i].ChannelNum - 149) % 8 == 0)
++			    && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {
++				index_5G = i;
++				best_channel_5G = rfctl->channel_set[i].ChannelNum;
++			}
++		}
++#if 1 /* debug */
++		RTW_INFO("The rx cnt of channel %3d = %d\n",
++			 rfctl->channel_set[i].ChannelNum,
++			 rfctl->channel_set[i].rx_count);
++#endif
++	}
++
++	sprintf(extra, "\nbest_channel_24G = %d\n", best_channel_24G);
++	RTW_INFO("best_channel_24G = %d\n", best_channel_24G);
++
++	if (index_5G != 0) {
++		sprintf(extra, "best_channel_5G = %d\n", best_channel_5G);
++		RTW_INFO("best_channel_5G = %d\n", best_channel_5G);
++	}
++
++	wrqu->data.length = strlen(extra);
++
++#endif
++
++	return 0;
++
++}
++#endif /*#ifdef CONFIG_TDLS*/
++static int rtw_tdls(struct net_device *dev,
++		    struct iw_request_info *info,
++		    union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_INFO("[%s] extra = %s\n", __FUNCTION__, extra);
++
++	if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) {
++		RTW_INFO("Discard tdls oper since hal doesn't support tdls\n");
++		return 0;
++	}
++
++	if (rtw_is_tdls_enabled(padapter) == _FALSE) {
++		RTW_INFO("TDLS is not enabled\n");
++		return 0;
++	}
++
++	/* WFD Sigma will use the tdls enable command to let the driver know we want to test the tdls now! */
++
++	if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
++		if (_rtw_memcmp(extra, "wfdenable=", 10)) {
++			wrqu->data.length -= 10;
++			rtw_wx_tdls_wfd_enable(dev, info, wrqu, &extra[10]);
++			return ret;
++		}
++	}
++
++	if (_rtw_memcmp(extra, "weaksec=", 8)) {
++		wrqu->data.length -= 8;
++		rtw_tdls_weaksec(dev, info, wrqu, &extra[8]);
++		return ret;
++	} else if (_rtw_memcmp(extra, "tdlsenable=", 11)) {
++		wrqu->data.length -= 11;
++		rtw_tdls_enable(dev, info, wrqu, &extra[11]);
++		return ret;
++	}
++
++	if (_rtw_memcmp(extra, "setup=", 6)) {
++		wrqu->data.length -= 6;
++		rtw_tdls_setup(dev, info, wrqu, &extra[6]);
++	} else if (_rtw_memcmp(extra, "tear=", 5)) {
++		wrqu->data.length -= 5;
++		rtw_tdls_teardown(dev, info, wrqu, &extra[5]);
++	} else if (_rtw_memcmp(extra, "dis=", 4)) {
++		wrqu->data.length -= 4;
++		rtw_tdls_discovery(dev, info, wrqu, &extra[4]);
++	} else if (_rtw_memcmp(extra, "swoff=", 6)) {
++		wrqu->data.length -= 6;
++		rtw_tdls_ch_switch_off(dev, info, wrqu, &extra[6]);
++	} else if (_rtw_memcmp(extra, "sw=", 3)) {
++		wrqu->data.length -= 3;
++		rtw_tdls_ch_switch(dev, info, wrqu, &extra[3]);
++	} else if (_rtw_memcmp(extra, "dumpstack=", 10)) {
++		wrqu->data.length -= 10;
++		rtw_tdls_dump_ch(dev, info, wrqu, &extra[10]);
++	} else if (_rtw_memcmp(extra, "offchnum=", 9)) {
++		wrqu->data.length -= 9;
++		rtw_tdls_off_ch_num(dev, info, wrqu, &extra[9]);
++	} else if (_rtw_memcmp(extra, "choffset=", 9)) {
++		wrqu->data.length -= 9;
++		rtw_tdls_ch_offset(dev, info, wrqu, &extra[9]);
++	} else if (_rtw_memcmp(extra, "pson=", 5)) {
++		wrqu->data.length -= 5;
++		rtw_tdls_pson(dev, info, wrqu, &extra[5]);
++	} else if (_rtw_memcmp(extra, "psoff=", 6)) {
++		wrqu->data.length -= 6;
++		rtw_tdls_psoff(dev, info, wrqu, &extra[6]);
++	}
++
++#ifdef CONFIG_WFD
++	if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
++		if (_rtw_memcmp(extra, "setip=", 6)) {
++			wrqu->data.length -= 6;
++			rtw_tdls_setip(dev, info, wrqu, &extra[6]);
++		} else if (_rtw_memcmp(extra, "tprobe=", 6))
++			issue_tunneled_probe_req((_adapter *)rtw_netdev_priv(dev));
++	}
++#endif /* CONFIG_WFD */
++
++#endif /* CONFIG_TDLS */
++
++	return ret;
++}
++
++
++static int rtw_tdls_get(struct net_device *dev,
++			struct iw_request_info *info,
++			union iwreq_data *wrqu, char *extra)
++{
++	int ret = 0;
++
++#ifdef CONFIG_TDLS
++
++	RTW_INFO("[%s] extra = %s\n", __FUNCTION__, (char *) wrqu->data.pointer);
++
++	if (_rtw_memcmp(wrqu->data.pointer, "ip", 2))
++		rtw_tdls_getip(dev, info, wrqu, extra);
++	else if (_rtw_memcmp(wrqu->data.pointer, "port", 4))
++		rtw_tdls_getport(dev, info, wrqu, extra);
++	/* WFDTDLS, for sigma test */
++	else if (_rtw_memcmp(wrqu->data.pointer, "dis", 3))
++		rtw_tdls_dis_result(dev, info, wrqu, extra);
++	else if (_rtw_memcmp(wrqu->data.pointer, "status", 6))
++		rtw_wfd_tdls_status(dev, info, wrqu, extra);
++	else if (_rtw_memcmp(wrqu->data.pointer, "tdls_sta=", 9))
++		rtw_tdls_getsta(dev, info, wrqu, extra);
++	else if (_rtw_memcmp(wrqu->data.pointer, "best_ch", 7))
++		rtw_tdls_get_best_ch(dev, info, wrqu, extra);
++#endif /* CONFIG_TDLS */
++
++	return ret;
++}
++
++#ifdef CONFIG_MAC_LOOPBACK_DRIVER
++
++#if defined(CONFIG_RTL8188E)
++#include <rtl8188e_hal.h>
++extern void rtl8188e_cal_txdesc_chksum(struct tx_desc *ptxdesc);
++#define cal_txdesc_chksum rtl8188e_cal_txdesc_chksum
++#ifdef CONFIG_SDIO_HCI || defined(CONFIG_GSPI_HCI)
++extern void rtl8188es_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf);
++#define fill_default_txdesc rtl8188es_fill_default_txdesc
++#endif /* CONFIG_SDIO_HCI */
++#endif /* CONFIG_RTL8188E */
++#if defined(CONFIG_RTL8723B)
++extern void rtl8723b_cal_txdesc_chksum(struct tx_desc *ptxdesc);
++#define cal_txdesc_chksum rtl8723b_cal_txdesc_chksum
++extern void rtl8723b_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf);
++#define fill_default_txdesc rtl8723b_fill_default_txdesc
++#endif /* CONFIG_RTL8723B */
++
++#if defined(CONFIG_RTL8703B)
++/* extern void rtl8703b_cal_txdesc_chksum(struct tx_desc *ptxdesc); */
++#define cal_txdesc_chksum rtl8703b_cal_txdesc_chksum
++/* extern void rtl8703b_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); */
++#define fill_default_txdesc rtl8703b_fill_default_txdesc
++#endif /* CONFIG_RTL8703B */
++
++#if defined(CONFIG_RTL8723D)
++/* extern void rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc); */
++#define cal_txdesc_chksum rtl8723d_cal_txdesc_chksum
++/* extern void rtl8723d_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); */
++#define fill_default_txdesc rtl8723d_fill_default_txdesc
++#endif /* CONFIG_RTL8723D */
++
++#if defined(CONFIG_RTL8710B)
++#define cal_txdesc_chksum rtl8710b_cal_txdesc_chksum
++#define fill_default_txdesc rtl8710b_fill_default_txdesc
++#endif /* CONFIG_RTL8710B */
++
++#if defined(CONFIG_RTL8192E)
++extern void rtl8192e_cal_txdesc_chksum(struct tx_desc *ptxdesc);
++#define cal_txdesc_chksum rtl8192e_cal_txdesc_chksum
++#ifdef CONFIG_SDIO_HCI || defined(CONFIG_GSPI_HCI)
++extern void rtl8192es_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf);
++#define fill_default_txdesc rtl8192es_fill_default_txdesc
++#endif /* CONFIG_SDIO_HCI */
++#endif /* CONFIG_RTL8192E */
++
++#if defined(CONFIG_RTL8192F)
++/* extern void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc); */
++#define cal_txdesc_chksum rtl8192f_cal_txdesc_chksum
++/* extern void rtl8192f_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); */
++#define fill_default_txdesc rtl8192f_fill_default_txdesc
++#endif /* CONFIG_RTL8192F */
++
++static s32 initLoopback(PADAPTER padapter)
++{
++	PLOOPBACKDATA ploopback;
++
++
++	if (padapter->ploopback == NULL) {
++		ploopback = (PLOOPBACKDATA)rtw_zmalloc(sizeof(LOOPBACKDATA));
++		if (ploopback == NULL)
++			return -ENOMEM;
++
++		_rtw_init_sema(&ploopback->sema, 0);
++		ploopback->bstop = _TRUE;
++		ploopback->cnt = 0;
++		ploopback->size = 300;
++		_rtw_memset(ploopback->msg, 0, sizeof(ploopback->msg));
++
++		padapter->ploopback = ploopback;
++	}
++
++	return 0;
++}
++
++static void freeLoopback(PADAPTER padapter)
++{
++	PLOOPBACKDATA ploopback;
++
++
++	ploopback = padapter->ploopback;
++	if (ploopback) {
++		rtw_mfree((u8 *)ploopback, sizeof(LOOPBACKDATA));
++		padapter->ploopback = NULL;
++	}
++}
++
++static s32 initpseudoadhoc(PADAPTER padapter)
++{
++	NDIS_802_11_NETWORK_INFRASTRUCTURE networkType;
++	s32 err;
++
++	networkType = Ndis802_11IBSS;
++	err = rtw_set_802_11_infrastructure_mode(padapter, networkType, 0);
++	if (err == _FALSE)
++		return _FAIL;
++
++	err = rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK);
++	if (err == _FAIL)
++		return _FAIL;
++
++	return _SUCCESS;
++}
++
++static s32 createpseudoadhoc(PADAPTER padapter)
++{
++	NDIS_802_11_AUTHENTICATION_MODE authmode;
++	struct mlme_priv *pmlmepriv;
++	NDIS_802_11_SSID *passoc_ssid;
++	WLAN_BSSID_EX *pdev_network;
++	u8 *pibss;
++	u8 ssid[] = "pseduo_ad-hoc";
++	s32 err;
++	_irqL irqL;
++
++
++	pmlmepriv = &padapter->mlmepriv;
++
++	authmode = Ndis802_11AuthModeOpen;
++	err = rtw_set_802_11_authentication_mode(padapter, authmode);
++	if (err == _FALSE)
++		return _FAIL;
++
++	passoc_ssid = &pmlmepriv->assoc_ssid;
++	_rtw_memset(passoc_ssid, 0, sizeof(NDIS_802_11_SSID));
++	passoc_ssid->SsidLength = sizeof(ssid) - 1;
++	_rtw_memcpy(passoc_ssid->Ssid, ssid, passoc_ssid->SsidLength);
++
++	pdev_network = &padapter->registrypriv.dev_network;
++	pibss = padapter->registrypriv.dev_network.MacAddress;
++	_rtw_memcpy(&pdev_network->Ssid, passoc_ssid, sizeof(NDIS_802_11_SSID));
++
++	rtw_update_registrypriv_dev_network(padapter);
++	rtw_generate_random_ibss(pibss);
++
++	_enter_critical_bh(&pmlmepriv->lock, &irqL);
++	/*pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;*/
++	init_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
++
++	_exit_critical_bh(&pmlmepriv->lock, &irqL);
++
++#if 0
++	err = rtw_create_ibss_cmd(padapter, 0);
++	if (err == _FAIL)
++		return _FAIL;
++#else
++	{
++		struct wlan_network *pcur_network;
++		struct sta_info *psta;
++
++		/* 3  create a new psta */
++		pcur_network = &pmlmepriv->cur_network;
++
++		/* clear psta in the cur_network, if any */
++		psta = rtw_get_stainfo(&padapter->stapriv, pcur_network->network.MacAddress);
++		if (psta)
++			rtw_free_stainfo(padapter, psta);
++
++		psta = rtw_alloc_stainfo(&padapter->stapriv, pibss);
++		if (psta == NULL)
++			return _FAIL;
++
++		/* 3  join psudo AdHoc */
++		pcur_network->join_res = 1;
++		pcur_network->aid = psta->cmn.aid = 1;
++		_rtw_memcpy(&pcur_network->network, pdev_network, get_WLAN_BSSID_EX_sz(pdev_network));
++
++		/* set msr to WIFI_FW_ADHOC_STATE */
++		padapter->hw_port = HW_PORT0;
++		Set_MSR(padapter, WIFI_FW_ADHOC_STATE);
++
++	}
++#endif
++
++	return _SUCCESS;
++}
++
++static struct xmit_frame *createloopbackpkt(PADAPTER padapter, u32 size)
++{
++	struct xmit_priv *pxmitpriv;
++	struct xmit_frame *pframe;
++	struct xmit_buf *pxmitbuf;
++	struct pkt_attrib *pattrib;
++	struct tx_desc *desc;
++	u8 *pkt_start, *pkt_end, *ptr;
++	struct rtw_ieee80211_hdr *hdr;
++	s32 bmcast;
++	_irqL irqL;
++
++
++	if ((TXDESC_SIZE + WLANHDR_OFFSET + size) > MAX_XMITBUF_SZ)
++		return NULL;
++
++	pxmitpriv = &padapter->xmitpriv;
++	pframe = NULL;
++
++	/* 2 1. allocate xmit frame */
++	pframe = rtw_alloc_xmitframe(pxmitpriv, 0);
++	if (pframe == NULL)
++		return NULL;
++	pframe->padapter = padapter;
++
++	/* 2 2. allocate xmit buffer */
++	_enter_critical_bh(&pxmitpriv->lock, &irqL);
++	pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
++	_exit_critical_bh(&pxmitpriv->lock, &irqL);
++	if (pxmitbuf == NULL) {
++		rtw_free_xmitframe(pxmitpriv, pframe);
++		return NULL;
++	}
++
++	pframe->pxmitbuf = pxmitbuf;
++	pframe->buf_addr = pxmitbuf->pbuf;
++	pxmitbuf->priv_data = pframe;
++
++	/* 2 3. update_attrib() */
++	pattrib = &pframe->attrib;
++
++	/* init xmitframe attribute */
++	_rtw_memset(pattrib, 0, sizeof(struct pkt_attrib));
++
++	pattrib->ether_type = 0x8723;
++	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
++	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
++	_rtw_memset(pattrib->dst, 0xFF, ETH_ALEN);
++	_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
++
++	/*	pattrib->dhcp_pkt = 0;
++	 *	pattrib->pktlen = 0; */
++	pattrib->ack_policy = 0;
++	/*	pattrib->pkt_hdrlen = ETH_HLEN; */
++	pattrib->hdrlen = WLAN_HDR_A3_LEN;
++	pattrib->subtype = WIFI_DATA;
++	pattrib->priority = 0;
++	pattrib->qsel = pattrib->priority;
++	/*	do_queue_select(padapter, pattrib); */
++	pattrib->nr_frags = 1;
++	pattrib->encrypt = 0;
++	pattrib->bswenc = _FALSE;
++	pattrib->qos_en = _FALSE;
++
++	bmcast = IS_MCAST(pattrib->ra);
++	if (bmcast)
++		pattrib->psta = rtw_get_bcmc_stainfo(padapter);
++	else
++		pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
++
++	pattrib->mac_id = pattrib->psta->cmn.mac_id;
++	pattrib->pktlen = size;
++	pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen;
++
++	/* 2 4. fill TX descriptor */
++	desc = (struct tx_desc *)pframe->buf_addr;
++	_rtw_memset(desc, 0, TXDESC_SIZE);
++
++	fill_default_txdesc(pframe, (u8 *)desc);
++
++	/* Hw set sequence number */
++	((PTXDESC)desc)->hwseq_en = 0; /* HWSEQ_EN, 0:disable, 1:enable
++ * ((PTXDESC)desc)->hwseq_sel = 0;  */ /* HWSEQ_SEL */
++
++	((PTXDESC)desc)->disdatafb = 1;
++
++	/* convert to little endian */
++	desc->txdw0 = cpu_to_le32(desc->txdw0);
++	desc->txdw1 = cpu_to_le32(desc->txdw1);
++	desc->txdw2 = cpu_to_le32(desc->txdw2);
++	desc->txdw3 = cpu_to_le32(desc->txdw3);
++	desc->txdw4 = cpu_to_le32(desc->txdw4);
++	desc->txdw5 = cpu_to_le32(desc->txdw5);
++	desc->txdw6 = cpu_to_le32(desc->txdw6);
++	desc->txdw7 = cpu_to_le32(desc->txdw7);
++#ifdef CONFIG_PCI_HCI
++	desc->txdw8 = cpu_to_le32(desc->txdw8);
++	desc->txdw9 = cpu_to_le32(desc->txdw9);
++	desc->txdw10 = cpu_to_le32(desc->txdw10);
++	desc->txdw11 = cpu_to_le32(desc->txdw11);
++	desc->txdw12 = cpu_to_le32(desc->txdw12);
++	desc->txdw13 = cpu_to_le32(desc->txdw13);
++	desc->txdw14 = cpu_to_le32(desc->txdw14);
++	desc->txdw15 = cpu_to_le32(desc->txdw15);
++#endif
++
++	cal_txdesc_chksum(desc);
++
++	/* 2 5. coalesce */
++	pkt_start = pframe->buf_addr + TXDESC_SIZE;
++	pkt_end = pkt_start + pattrib->last_txcmdsz;
++
++	/* 3 5.1. make wlan header, make_wlanhdr() */
++	hdr = (struct rtw_ieee80211_hdr *)pkt_start;
++	set_frame_sub_type(&hdr->frame_ctl, pattrib->subtype);
++	_rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); /* DA */
++	_rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); /* SA */
++	_rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); /* RA, BSSID */
++
++	/* 3 5.2. make payload */
++	ptr = pkt_start + pattrib->hdrlen;
++	get_random_bytes(ptr, pkt_end - ptr);
++
++	pxmitbuf->len = TXDESC_SIZE + pattrib->last_txcmdsz;
++	pxmitbuf->ptail += pxmitbuf->len;
++
++	return pframe;
++}
++
++static void freeloopbackpkt(PADAPTER padapter, struct xmit_frame *pframe)
++{
++	struct xmit_priv *pxmitpriv;
++	struct xmit_buf *pxmitbuf;
++
++
++	pxmitpriv = &padapter->xmitpriv;
++	pxmitbuf = pframe->pxmitbuf;
++
++	rtw_free_xmitframe(pxmitpriv, pframe);
++	rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
++}
++
++static void printdata(u8 *pbuf, u32 len)
++{
++	u32 i, val;
++
++
++	for (i = 0; (i + 4) <= len; i += 4) {
++		printk("%08X", *(u32 *)(pbuf + i));
++		if ((i + 4) & 0x1F)
++			printk(" ");
++		else
++			printk("\n");
++	}
++
++	if (i < len) {
++#ifdef CONFIG_BIG_ENDIAN
++		for (; i < len, i++)
++			printk("%02X", pbuf + i);
++#else /* CONFIG_LITTLE_ENDIAN */
++#if 0
++		val = 0;
++		_rtw_memcpy(&val, pbuf + i, len - i);
++		printk("%8X", val);
++#else
++		u8 str[9];
++		u8 n;
++		val = 0;
++		n = len - i;
++		_rtw_memcpy(&val, pbuf + i, n);
++		sprintf(str, "%08X", val);
++		n = (4 - n) * 2;
++		printk("%8s", str + n);
++#endif
++#endif /* CONFIG_LITTLE_ENDIAN */
++	}
++	printk("\n");
++}
++
++static u8 pktcmp(PADAPTER padapter, u8 *txbuf, u32 txsz, u8 *rxbuf, u32 rxsz)
++{
++	PHAL_DATA_TYPE phal;
++	struct recv_stat *prxstat;
++	struct recv_stat report;
++	PRXREPORT prxreport;
++	u32 drvinfosize;
++	u32 rxpktsize;
++	u8 fcssize;
++	u8 ret = _FALSE;
++
++	prxstat = (struct recv_stat *)rxbuf;
++	report.rxdw0 = le32_to_cpu(prxstat->rxdw0);
++	report.rxdw1 = le32_to_cpu(prxstat->rxdw1);
++	report.rxdw2 = le32_to_cpu(prxstat->rxdw2);
++	report.rxdw3 = le32_to_cpu(prxstat->rxdw3);
++	report.rxdw4 = le32_to_cpu(prxstat->rxdw4);
++	report.rxdw5 = le32_to_cpu(prxstat->rxdw5);
++
++	prxreport = (PRXREPORT)&report;
++	drvinfosize = prxreport->drvinfosize << 3;
++	rxpktsize = prxreport->pktlen;
++
++	phal = GET_HAL_DATA(padapter);
++	if (rtw_hal_rcr_check(padapter, RCR_APPFCS))
++		fcssize = IEEE80211_FCS_LEN;
++	else
++		fcssize = 0;
++
++	if ((txsz - TXDESC_SIZE) != (rxpktsize - fcssize)) {
++		RTW_INFO("%s: ERROR! size not match tx/rx=%d/%d !\n",
++			 __func__, txsz - TXDESC_SIZE, rxpktsize - fcssize);
++		ret = _FALSE;
++	} else {
++		ret = _rtw_memcmp(txbuf + TXDESC_SIZE, \
++				  rxbuf + RXDESC_SIZE + drvinfosize, \
++				  txsz - TXDESC_SIZE);
++		if (ret == _FALSE)
++			RTW_INFO("%s: ERROR! pkt content mismatch!\n", __func__);
++	}
++
++	if (ret == _FALSE) {
++		RTW_INFO("\n%s: TX PKT total=%d, desc=%d, content=%d\n",
++			 __func__, txsz, TXDESC_SIZE, txsz - TXDESC_SIZE);
++		RTW_INFO("%s: TX DESC size=%d\n", __func__, TXDESC_SIZE);
++		printdata(txbuf, TXDESC_SIZE);
++		RTW_INFO("%s: TX content size=%d\n", __func__, txsz - TXDESC_SIZE);
++		printdata(txbuf + TXDESC_SIZE, txsz - TXDESC_SIZE);
++
++		RTW_INFO("\n%s: RX PKT read=%d offset=%d(%d,%d) content=%d\n",
++			__func__, rxsz, RXDESC_SIZE + drvinfosize, RXDESC_SIZE, drvinfosize, rxpktsize);
++		if (rxpktsize != 0) {
++			RTW_INFO("%s: RX DESC size=%d\n", __func__, RXDESC_SIZE);
++			printdata(rxbuf, RXDESC_SIZE);
++			RTW_INFO("%s: RX drvinfo size=%d\n", __func__, drvinfosize);
++			printdata(rxbuf + RXDESC_SIZE, drvinfosize);
++			RTW_INFO("%s: RX content size=%d\n", __func__, rxpktsize);
++			printdata(rxbuf + RXDESC_SIZE + drvinfosize, rxpktsize);
++		} else {
++			RTW_INFO("%s: RX data size=%d\n", __func__, rxsz);
++			printdata(rxbuf, rxsz);
++		}
++	}
++
++	return ret;
++}
++
++thread_return lbk_thread(thread_context context)
++{
++	s32 err;
++	PADAPTER padapter;
++	PLOOPBACKDATA ploopback;
++	struct xmit_frame *pxmitframe;
++	u32 cnt, ok, fail, headerlen;
++	u32 pktsize;
++	u32 ff_hwaddr;
++
++
++	padapter = (PADAPTER)context;
++	ploopback = padapter->ploopback;
++	if (ploopback == NULL)
++		return -1;
++	cnt = 0;
++	ok = 0;
++	fail = 0;
++
++	daemonize("%s", "RTW_LBK_THREAD");
++	allow_signal(SIGTERM);
++
++	do {
++		if (ploopback->size == 0) {
++			get_random_bytes(&pktsize, 4);
++			pktsize = (pktsize % 1535) + 1; /* 1~1535 */
++		} else
++			pktsize = ploopback->size;
++
++		pxmitframe = createloopbackpkt(padapter, pktsize);
++		if (pxmitframe == NULL) {
++			sprintf(ploopback->msg, "loopback FAIL! 3. create Packet FAIL!");
++			break;
++		}
++
++		ploopback->txsize = TXDESC_SIZE + pxmitframe->attrib.last_txcmdsz;
++		_rtw_memcpy(ploopback->txbuf, pxmitframe->buf_addr, ploopback->txsize);
++		ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);
++		cnt++;
++		RTW_INFO("%s: wirte port cnt=%d size=%d\n", __func__, cnt, ploopback->txsize);
++		pxmitframe->pxmitbuf->pdata = ploopback->txbuf;
++		rtw_write_port(padapter, ff_hwaddr, ploopback->txsize, (u8 *)pxmitframe->pxmitbuf);
++
++		/* wait for rx pkt */
++		_rtw_down_sema(&ploopback->sema);
++
++		err = pktcmp(padapter, ploopback->txbuf, ploopback->txsize, ploopback->rxbuf, ploopback->rxsize);
++		if (err == _TRUE)
++			ok++;
++		else
++			fail++;
++
++		ploopback->txsize = 0;
++		_rtw_memset(ploopback->txbuf, 0, 0x8000);
++		ploopback->rxsize = 0;
++		_rtw_memset(ploopback->rxbuf, 0, 0x8000);
++
++		freeloopbackpkt(padapter, pxmitframe);
++		pxmitframe = NULL;
++
++		flush_signals_thread();
++
++		if ((ploopback->bstop == _TRUE) ||
++		    ((ploopback->cnt != 0) && (ploopback->cnt == cnt))) {
++			u32 ok_rate, fail_rate, all;
++			all = cnt;
++			ok_rate = (ok * 100) / all;
++			fail_rate = (fail * 100) / all;
++			sprintf(ploopback->msg, \
++				"loopback result: ok=%d%%(%d/%d),error=%d%%(%d/%d)", \
++				ok_rate, ok, all, fail_rate, fail, all);
++			break;
++		}
++	} while (1);
++
++	ploopback->bstop = _TRUE;
++
++	thread_exit(NULL);
++	return 0;
++}
++
++static void loopbackTest(PADAPTER padapter, u32 cnt, u32 size, u8 *pmsg)
++{
++	PLOOPBACKDATA ploopback;
++	u32 len;
++	s32 err;
++
++
++	ploopback = padapter->ploopback;
++
++	if (ploopback) {
++		if (ploopback->bstop == _FALSE) {
++			ploopback->bstop = _TRUE;
++			_rtw_up_sema(&ploopback->sema);
++		}
++		len = 0;
++		do {
++			len = strlen(ploopback->msg);
++			if (len)
++				break;
++			rtw_msleep_os(1);
++		} while (1);
++		_rtw_memcpy(pmsg, ploopback->msg, len + 1);
++		freeLoopback(padapter);
++
++		return;
++	}
++
++	/* disable dynamic algorithm	 */
++	rtw_phydm_ability_backup(padapter);
++	rtw_phydm_func_disable_all(padapter);
++
++	/* create pseudo ad-hoc connection */
++	err = initpseudoadhoc(padapter);
++	if (err == _FAIL) {
++		sprintf(pmsg, "loopback FAIL! 1.1 init ad-hoc FAIL!");
++		return;
++	}
++
++	err = createpseudoadhoc(padapter);
++	if (err == _FAIL) {
++		sprintf(pmsg, "loopback FAIL! 1.2 create ad-hoc master FAIL!");
++		return;
++	}
++
++	err = initLoopback(padapter);
++	if (err) {
++		sprintf(pmsg, "loopback FAIL! 2. init FAIL! error code=%d", err);
++		return;
++	}
++
++	ploopback = padapter->ploopback;
++
++	ploopback->bstop = _FALSE;
++	ploopback->cnt = cnt;
++	ploopback->size = size;
++	ploopback->lbkthread = kthread_run(lbk_thread, padapter, "RTW_LBK_THREAD");
++	if (IS_ERR(padapter->lbkthread)) {
++		freeLoopback(padapter);
++		ploopback->lbkthread = NULL;
++		sprintf(pmsg, "loopback start FAIL! cnt=%d", cnt);
++		return;
++	}
++
++	sprintf(pmsg, "loopback start! cnt=%d", cnt);
++}
++#endif /* CONFIG_MAC_LOOPBACK_DRIVER */
++
++static int rtw_test(
++	struct net_device *dev,
++	struct iw_request_info *info,
++	union iwreq_data *wrqu, char *extra)
++{
++	u32 len;
++	u8 *pbuf, *pch;
++	char *ptmp;
++	u8 *delim = ",";
++	PADAPTER padapter = rtw_netdev_priv(dev);
++
++
++	RTW_INFO("+%s\n", __func__);
++	len = wrqu->data.length;
++
++	pbuf = (u8 *)rtw_zmalloc(len + 1);
++	if (pbuf == NULL) {
++		RTW_INFO("%s: no memory!\n", __func__);
++		return -ENOMEM;
++	}
++
++	if (copy_from_user(pbuf, wrqu->data.pointer, len)) {
++		rtw_mfree(pbuf, len + 1);
++		RTW_INFO("%s: copy from user fail!\n", __func__);
++		return -EFAULT;
++	}
++
++	pbuf[len] = '\0';
++
++	RTW_INFO("%s: string=\"%s\"\n", __func__, pbuf);
++
++	ptmp = (char *)pbuf;
++	pch = strsep(&ptmp, delim);
++	if ((pch == NULL) || (strlen(pch) == 0)) {
++		rtw_mfree(pbuf, len);
++		RTW_INFO("%s: parameter error(level 1)!\n", __func__);
++		return -EFAULT;
++	}
++
++#ifdef CONFIG_MAC_LOOPBACK_DRIVER
++	if (strcmp(pch, "loopback") == 0) {
++		s32 cnt = 0;
++		u32 size = 64;
++
++		pch = strsep(&ptmp, delim);
++		if ((pch == NULL) || (strlen(pch) == 0)) {
++			rtw_mfree(pbuf, len);
++			RTW_INFO("%s: parameter error(level 2)!\n", __func__);
++			return -EFAULT;
++		}
++
++		sscanf(pch, "%d", &cnt);
++		RTW_INFO("%s: loopback cnt=%d\n", __func__, cnt);
++
++		pch = strsep(&ptmp, delim);
++		if ((pch == NULL) || (strlen(pch) == 0)) {
++			rtw_mfree(pbuf, len);
++			RTW_INFO("%s: parameter error(level 2)!\n", __func__);
++			return -EFAULT;
++		}
++
++		sscanf(pch, "%d", &size);
++		RTW_INFO("%s: loopback size=%d\n", __func__, size);
++
++		loopbackTest(padapter, cnt, size, extra);
++		wrqu->data.length = strlen(extra) + 1;
++
++		goto free_buf;
++	}
++#endif
++
++
++#ifdef CONFIG_BT_COEXIST
++	if (strcmp(pch, "bton") == 0) {
++		rtw_btcoex_SetManualControl(padapter, _FALSE);
++		goto free_buf;
++	} else if (strcmp(pch, "btoff") == 0) {
++		rtw_btcoex_SetManualControl(padapter, _TRUE);
++		goto free_buf;
++	}
++#endif
++
++	if (strcmp(pch, "h2c") == 0) {
++		u8 param[8];
++		u8 count = 0;
++		u32 tmp;
++		u8 i;
++		u32 pos;
++		u8 ret;
++
++		do {
++			pch = strsep(&ptmp, delim);
++			if ((pch == NULL) || (strlen(pch) == 0))
++				break;
++
++			sscanf(pch, "%x", &tmp);
++			param[count++] = (u8)tmp;
++		} while (count < 8);
++
++		if (count == 0) {
++			rtw_mfree(pbuf, len);
++			RTW_INFO("%s: parameter error(level 2)!\n", __func__);
++			return -EFAULT;
++		}
++
++		ret = rtw_test_h2c_cmd(padapter, param, count);
++
++		pos = sprintf(extra, "H2C ID=0x%02x content=", param[0]);
++		for (i = 1; i < count; i++)
++			pos += sprintf(extra + pos, "%02x,", param[i]);
++		extra[pos] = 0;
++		pos--;
++		pos += sprintf(extra + pos, " %s", ret == _FAIL ? "FAIL" : "OK");
++
++		wrqu->data.length = strlen(extra) + 1;
++
++		goto free_buf;
++	}
++
++free_buf:
++	rtw_mfree(pbuf, len);
++	return 0;
++}
++
++static iw_handler rtw_handlers[] = {
++	NULL,					/* SIOCSIWCOMMIT */
++	rtw_wx_get_name,		/* SIOCGIWNAME */
++	dummy,					/* SIOCSIWNWID */
++	dummy,					/* SIOCGIWNWID */
++	rtw_wx_set_freq,		/* SIOCSIWFREQ */
++	rtw_wx_get_freq,		/* SIOCGIWFREQ */
++	rtw_wx_set_mode,		/* SIOCSIWMODE */
++	rtw_wx_get_mode,		/* SIOCGIWMODE */
++	dummy,					/* SIOCSIWSENS */
++	rtw_wx_get_sens,		/* SIOCGIWSENS */
++	NULL,					/* SIOCSIWRANGE */
++	rtw_wx_get_range,		/* SIOCGIWRANGE */
++	rtw_wx_set_priv,		/* SIOCSIWPRIV */
++	NULL,					/* SIOCGIWPRIV */
++	NULL,					/* SIOCSIWSTATS */
++	NULL,					/* SIOCGIWSTATS */
++	dummy,					/* SIOCSIWSPY */
++	dummy,					/* SIOCGIWSPY */
++	NULL,					/* SIOCGIWTHRSPY */
++	NULL,					/* SIOCWIWTHRSPY */
++	rtw_wx_set_wap,		/* SIOCSIWAP */
++	rtw_wx_get_wap,		/* SIOCGIWAP */
++	rtw_wx_set_mlme,		/* request MLME operation; uses struct iw_mlme */
++	dummy,					/* SIOCGIWAPLIST -- depricated */
++	rtw_wx_set_scan,		/* SIOCSIWSCAN */
++	rtw_wx_get_scan,		/* SIOCGIWSCAN */
++	rtw_wx_set_essid,		/* SIOCSIWESSID */
++	rtw_wx_get_essid,		/* SIOCGIWESSID */
++	dummy,					/* SIOCSIWNICKN */
++	rtw_wx_get_nick,		/* SIOCGIWNICKN */
++	NULL,					/* -- hole -- */
++	NULL,					/* -- hole -- */
++	rtw_wx_set_rate,		/* SIOCSIWRATE */
++	rtw_wx_get_rate,		/* SIOCGIWRATE */
++	rtw_wx_set_rts,			/* SIOCSIWRTS */
++	rtw_wx_get_rts,			/* SIOCGIWRTS */
++	rtw_wx_set_frag,		/* SIOCSIWFRAG */
++	rtw_wx_get_frag,		/* SIOCGIWFRAG */
++	dummy,					/* SIOCSIWTXPOW */
++	dummy,					/* SIOCGIWTXPOW */
++	dummy,					/* SIOCSIWRETRY */
++	rtw_wx_get_retry,		/* SIOCGIWRETRY */
++	rtw_wx_set_enc,			/* SIOCSIWENCODE */
++	rtw_wx_get_enc,			/* SIOCGIWENCODE */
++	dummy,					/* SIOCSIWPOWER */
++	rtw_wx_get_power,		/* SIOCGIWPOWER */
++	NULL,					/*---hole---*/
++	NULL,					/*---hole---*/
++	rtw_wx_set_gen_ie,		/* SIOCSIWGENIE */
++	NULL,					/* SIOCGWGENIE */
++	rtw_wx_set_auth,		/* SIOCSIWAUTH */
++	NULL,					/* SIOCGIWAUTH */
++	rtw_wx_set_enc_ext,		/* SIOCSIWENCODEEXT */
++	NULL,					/* SIOCGIWENCODEEXT */
++	rtw_wx_set_pmkid,		/* SIOCSIWPMKSA */
++	NULL,					/*---hole---*/
++};
++
++
++static const struct iw_priv_args rtw_private_args[] = {
++	{
++		SIOCIWFIRSTPRIV + 0x0,
++		IW_PRIV_TYPE_CHAR | 0x7FF, 0, "write"
++	},
++	{
++		SIOCIWFIRSTPRIV + 0x1,
++		IW_PRIV_TYPE_CHAR | 0x7FF,
++		IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, "read"
++	},
++	{
++		SIOCIWFIRSTPRIV + 0x2, 0, 0, "driver_ext"
++	},
++	{
++		SIOCIWFIRSTPRIV + 0x3, 0, 0, "mp_ioctl"
++	},
++	{
++		SIOCIWFIRSTPRIV + 0x4,
++		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "apinfo"
++	},
++	{
++		SIOCIWFIRSTPRIV + 0x5,
++		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "setpid"
++	},
++	{
++		SIOCIWFIRSTPRIV + 0x6,
++		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_start"
++	},
++	/* for PLATFORM_MT53XX	 */
++	{
++		SIOCIWFIRSTPRIV + 0x7,
++		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "get_sensitivity"
++	},
++	{
++		SIOCIWFIRSTPRIV + 0x8,
++		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_prob_req_ie"
++	},
++	{
++		SIOCIWFIRSTPRIV + 0x9,
++		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_assoc_req_ie"
++	},
++
++	/* for RTK_DMP_PLATFORM	 */
++	{
++		SIOCIWFIRSTPRIV + 0xA,
++		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "channel_plan"
++	},
++
++	{
++		SIOCIWFIRSTPRIV + 0xB,
++		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "dbg"
++	},
++	{
++		SIOCIWFIRSTPRIV + 0xC,
++		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 3, 0, "rfw"
++	},
++	{
++		SIOCIWFIRSTPRIV + 0xD,
++		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, "rfr"
++	},
++#if 0
++	{
++		SIOCIWFIRSTPRIV + 0xE, 0, 0, "wowlan_ctrl"
++	},
++#endif
++	{
++		SIOCIWFIRSTPRIV + 0x10,
++		IW_PRIV_TYPE_CHAR | 1024, 0, "p2p_set"
++	},
++	{
++		SIOCIWFIRSTPRIV + 0x11,
++		IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "p2p_get"
++	},
++	{
++		SIOCIWFIRSTPRIV + 0x12, 0, 0, "NULL"
++	},
++	{
++		SIOCIWFIRSTPRIV + 0x13,
++		IW_PRIV_TYPE_CHAR | 64, IW_PRIV_TYPE_CHAR | 64 , "p2p_get2"
++	},
++	{
++		SIOCIWFIRSTPRIV + 0x14,
++		IW_PRIV_TYPE_CHAR  | 64, 0, "tdls"
++	},
++	{
++		SIOCIWFIRSTPRIV + 0x15,
++		IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | 1024 , "tdls_get"
++	},
++	{
++		SIOCIWFIRSTPRIV + 0x16,
++		IW_PRIV_TYPE_CHAR | 64, 0, "pm_set"
++	},
++#ifdef CONFIG_RTW_80211K
++	{
++		SIOCIWFIRSTPRIV + 0x17,
++		IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | 1024 , "rrm"
++	},
++#else
++	{SIOCIWFIRSTPRIV + 0x17, IW_PRIV_TYPE_CHAR | 1024 , 0 , "NULL"},
++#endif
++	{SIOCIWFIRSTPRIV + 0x18, IW_PRIV_TYPE_CHAR | IFNAMSIZ , 0 , "rereg_nd_name"},
++#ifdef CONFIG_MP_INCLUDED
++	{SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0,  "NULL"},
++	{SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "NULL"},
++#else
++	{SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0,  "NULL"},
++	{SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get"},
++#endif
++	{
++		SIOCIWFIRSTPRIV + 0x1D,
++		IW_PRIV_TYPE_CHAR | 40, IW_PRIV_TYPE_CHAR | 0x7FF, "test"
++	},
++
++	{ SIOCIWFIRSTPRIV + 0x0E, IW_PRIV_TYPE_CHAR | 1024, 0 , ""},  /* set  */
++	{ SIOCIWFIRSTPRIV + 0x0F, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , ""},/* get
++ * --- sub-ioctls definitions --- */
++
++#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
++	{ VENDOR_IE_SET, IW_PRIV_TYPE_CHAR | 1024 , 0 , "vendor_ie_set" },
++	{ VENDOR_IE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "vendor_ie_get" },
++#endif
++#if defined(CONFIG_RTL8723B)
++	{ MP_SetBT, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_setbt" },
++	{ MP_DISABLE_BT_COEXIST, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_disa_btcoex"},
++#endif
++#ifdef CONFIG_WOWLAN
++	{ MP_WOW_ENABLE , IW_PRIV_TYPE_CHAR | 1024, 0, "wow_mode" },
++	{ MP_WOW_SET_PATTERN , IW_PRIV_TYPE_CHAR | 1024, 0, "wow_set_pattern" },
++#endif
++#ifdef CONFIG_AP_WOWLAN
++	{ MP_AP_WOW_ENABLE , IW_PRIV_TYPE_CHAR | 1024, 0, "ap_wow_mode" }, /* set  */
++#endif
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++	{ MP_SD_IREAD, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "sd_iread" },
++	{ MP_SD_IWRITE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "sd_iwrite" },
++#endif
++};
++
++
++static const struct iw_priv_args rtw_mp_private_args[] = {
++	/* --- sub-ioctls definitions --- */
++#ifdef CONFIG_MP_INCLUDED
++	{ MP_START , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_start" },
++	{ MP_PHYPARA, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_phypara" },
++	{ MP_STOP , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_stop" },
++	{ MP_CHANNEL , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_channel" },
++	{ MP_CHL_OFFSET , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ch_offset" },
++	{ MP_BANDWIDTH , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_bandwidth"},
++	{ MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" },
++	{ MP_RESET_STATS , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_reset_stats"},
++	{ MP_QUERY , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "mp_query"},
++	{ READ_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_reg" },
++	{ MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" },
++	{ READ_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_rf" },
++	{ MP_PSD , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_psd"},
++	{ MP_DUMP, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dump" },
++	{ MP_TXPOWER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_txpower"},
++	{ MP_ANT_TX , IW_PRIV_TYPE_CHAR | 1024,  IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_tx"},
++	{ MP_ANT_RX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_rx"},
++	{ WRITE_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_reg" },
++	{ WRITE_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_rf" },
++	{ MP_CTX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ctx"},
++	{ MP_ARX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_arx"},
++	{ MP_THER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ther"},
++	{ EFUSE_SET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_set" },
++	{ EFUSE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get" },
++	{ MP_PWRTRK , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrtrk"},
++	{ MP_QueryDrvStats, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_drvquery" },
++	{ MP_IOCTL, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_ioctl"},
++	{ MP_SetRFPathSwh, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_setrfpath" },
++	{ MP_PwrCtlDM, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrctldm" },
++	{ MP_GET_TXPOWER_INX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_get_txpower" },
++	{ MP_GETVER, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_priv_ver" },
++	{ MP_MON, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_mon" },
++	{ EFUSE_BT_MASK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_bt_mask" },
++	{ EFUSE_MASK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_mask" },
++	{ EFUSE_FILE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_file" },
++	{ EFUSE_FILE_STORE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_store" },
++	{ MP_TX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_tx" },
++	{ MP_RX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rx" },
++	{ MP_HW_TX_MODE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_hxtx" },
++	{ MP_PWRLMT, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrlmt" },
++	{ MP_PWRBYRATE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrbyrate" },
++	{ CTA_TEST, IW_PRIV_TYPE_CHAR | 1024, 0, "cta_test"},
++	{ MP_IQK, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_iqk"},
++	{ MP_LCK, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_lck"},
++	{ BT_EFUSE_FILE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "bt_efuse_file" },
++	{ MP_SWRFPath, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_swrfpath" },
++	{ MP_LINK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_link" },
++	{ MP_DPK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dpk"},
++	{ MP_DPK_TRK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dpk_trk" },
++	{ MP_GET_TSSIDE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_get_tsside" },
++	{ MP_SET_TSSIDE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_set_tsside" },
++#ifdef CONFIG_RTW_CUSTOMER_STR
++	{ MP_CUSTOMER_STR, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "customer_str" },
++#endif
++
++#endif /* CONFIG_MP_INCLUDED */
++};
++
++static iw_handler rtw_private_handler[] = {
++	rtw_wx_write32,					/* 0x00 */
++	rtw_wx_read32,					/* 0x01 */
++	NULL,					/* 0x02 */
++#ifdef MP_IOCTL_HDL
++	rtw_mp_ioctl_hdl,				/* 0x03 */
++#else
++	rtw_wx_priv_null,
++#endif
++	/* for MM DTV platform */
++	rtw_get_ap_info,					/* 0x04 */
++
++	rtw_set_pid,						/* 0x05 */
++	rtw_wps_start,					/* 0x06 */
++
++	/* for PLATFORM_MT53XX */
++	rtw_wx_get_sensitivity,			/* 0x07 */
++	rtw_wx_set_mtk_wps_probe_ie,	/* 0x08 */
++	rtw_wx_set_mtk_wps_ie,			/* 0x09 */
++
++	/* for RTK_DMP_PLATFORM
++	 * Set Channel depend on the country code */
++	rtw_wx_set_channel_plan,		/* 0x0A */
++
++	rtw_dbg_port,					/* 0x0B */
++	rtw_wx_write_rf,					/* 0x0C */
++	rtw_wx_read_rf,					/* 0x0D */
++
++	rtw_priv_set,					/*0x0E*/
++	rtw_priv_get,					/*0x0F*/
++
++	rtw_p2p_set,					/* 0x10 */
++	rtw_p2p_get,					/* 0x11 */
++	NULL,							/* 0x12 */
++	rtw_p2p_get2,					/* 0x13 */
++
++	rtw_tdls,						/* 0x14 */
++	rtw_tdls_get,					/* 0x15 */
++
++	rtw_pm_set,						/* 0x16 */
++#ifdef CONFIG_RTW_80211K
++	rtw_wx_priv_rrm,				/* 0x17 */
++#else
++	rtw_wx_priv_null,				/* 0x17 */
++#endif
++	rtw_rereg_nd_name,				/* 0x18 */
++	rtw_wx_priv_null,				/* 0x19 */
++#ifdef CONFIG_MP_INCLUDED
++	rtw_wx_priv_null,				/* 0x1A */
++	rtw_wx_priv_null,				/* 0x1B */
++#else
++	rtw_wx_priv_null,				/* 0x1A */
++	rtw_mp_efuse_get,				/* 0x1B */
++#endif
++	NULL,							/* 0x1C is reserved for hostapd */
++	rtw_test,						/* 0x1D */
++};
++
++#if WIRELESS_EXT >= 17
++static struct iw_statistics *rtw_get_wireless_stats(struct net_device *dev)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct iw_statistics *piwstats = &padapter->iwstats;
++	int tmp_level = 0;
++	int tmp_qual = 0;
++	int tmp_noise = 0;
++
++	if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) != _TRUE) {
++		piwstats->qual.qual = 0;
++		piwstats->qual.level = 0;
++		piwstats->qual.noise = 0;
++		/* RTW_INFO("No link  level:%d, qual:%d, noise:%d\n", tmp_level, tmp_qual, tmp_noise); */
++	} else {
++#ifdef CONFIG_SIGNAL_DISPLAY_DBM
++		tmp_level = translate_percentage_to_dbm(padapter->recvpriv.signal_strength);
++#else
++		tmp_level = padapter->recvpriv.signal_strength;
++#endif
++
++		tmp_qual = padapter->recvpriv.signal_qual;
++		#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++		if (IS_NM_ENABLE(padapter)) {
++			tmp_noise = rtw_noise_measure_curchan(padapter);
++			#ifndef CONFIG_SIGNAL_DISPLAY_DBM
++			tmp_noise = translate_dbm_to_percentage(tmp_noise);/*percentage*/
++			#endif
++		}
++		#endif
++		/* RTW_INFO("level:%d, qual:%d, noise:%d, rssi (%d)\n", tmp_level, tmp_qual, tmp_noise,padapter->recvpriv.rssi); */
++
++		piwstats->qual.level = tmp_level;
++		piwstats->qual.qual = tmp_qual;
++		piwstats->qual.noise = tmp_noise;
++	}
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 14))
++	piwstats->qual.updated = IW_QUAL_ALL_UPDATED ;/* |IW_QUAL_DBM; */
++#else
++#ifdef RTK_DMP_PLATFORM
++	/* IW_QUAL_DBM= 0x8, if driver use this flag, wireless extension will show value of dbm. */
++	/* remove this flag for show percentage 0~100 */
++	piwstats->qual.updated = 0x07;
++#else
++	piwstats->qual.updated = 0x0f;
++#endif
++#endif
++
++#ifdef CONFIG_SIGNAL_DISPLAY_DBM
++	piwstats->qual.updated = piwstats->qual.updated | IW_QUAL_DBM;
++#endif
++
++	return &padapter->iwstats;
++}
++#endif
++
++#ifdef CONFIG_WIRELESS_EXT
++struct iw_handler_def rtw_handlers_def = {
++	.standard = rtw_handlers,
++	.num_standard = sizeof(rtw_handlers) / sizeof(iw_handler),
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33)) || defined(CONFIG_WEXT_PRIV)
++	.private = rtw_private_handler,
++	.private_args = (struct iw_priv_args *)rtw_private_args,
++	.num_private = sizeof(rtw_private_handler) / sizeof(iw_handler),
++	.num_private_args = sizeof(rtw_private_args) / sizeof(struct iw_priv_args),
++#endif
++#if WIRELESS_EXT >= 17
++	.get_wireless_stats = rtw_get_wireless_stats,
++#endif
++};
++#endif
++
++/* copy from net/wireless/wext.c start
++ * ----------------------------------------------------------------
++ *
++ * Calculate size of private arguments
++ */
++static const char iw_priv_type_size[] = {
++	0,                              /* IW_PRIV_TYPE_NONE */
++	1,                              /* IW_PRIV_TYPE_BYTE */
++	1,                              /* IW_PRIV_TYPE_CHAR */
++	0,                              /* Not defined */
++	sizeof(__u32),                  /* IW_PRIV_TYPE_INT */
++	sizeof(struct iw_freq),         /* IW_PRIV_TYPE_FLOAT */
++	sizeof(struct sockaddr),        /* IW_PRIV_TYPE_ADDR */
++	0,                              /* Not defined */
++};
++
++static int get_priv_size(__u16 args)
++{
++	int num = args & IW_PRIV_SIZE_MASK;
++	int type = (args & IW_PRIV_TYPE_MASK) >> 12;
++
++	return num * iw_priv_type_size[type];
++}
++/* copy from net/wireless/wext.c end */
++
++
++static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq_data)
++{
++	int err = 0;
++	u8 *input = NULL;
++	u32 input_len = 0;
++	const char delim[] = " ";
++	u8 *output = NULL;
++	u32 output_len = 0;
++	u32 count = 0;
++	u8 *buffer = NULL;
++	u32 buffer_len = 0;
++	char *ptr = NULL;
++	u8 cmdname[17] = {0}; /* IFNAMSIZ+1 */
++	u32 cmdlen;
++	s32 len;
++	u8 *extra = NULL;
++	u32 extra_size = 0;
++
++	s32 k;
++	const iw_handler *priv;		/* Private ioctl */
++	const struct iw_priv_args *priv_args;	/* Private ioctl description */
++	const struct iw_priv_args *mp_priv_args;	/*MP Private ioctl description */
++	const struct iw_priv_args *sel_priv_args;	/*Selected Private ioctl description */
++	u32 num_priv;				/* Number of ioctl */
++	u32 num_priv_args;			/* Number of descriptions */
++	u32 num_mp_priv_args;			/*Number of MP descriptions */
++	u32 num_sel_priv_args;			/*Number of Selected descriptions */
++	iw_handler handler;
++	int temp;
++	int subcmd = 0;				/* sub-ioctl index */
++	int offset = 0;				/* Space for sub-ioctl index */
++
++	union iwreq_data wdata;
++
++	_rtw_memcpy(&wdata, wrq_data, sizeof(wdata));
++
++	input_len = wdata.data.length;
++	if (!input_len)
++		return -EINVAL;
++	input = rtw_zmalloc(input_len);
++
++	if (input == NULL) {
++		err = -EOPNOTSUPP;
++		goto exit;
++	}
++
++	if (copy_from_user(input, wdata.data.pointer, input_len)) {
++		err = -EFAULT;
++		goto exit;
++	}
++	input[input_len - 1] = '\0';
++	ptr = input;
++	len = input_len;
++
++	sscanf(ptr, "%16s", cmdname);
++	cmdlen = strlen(cmdname);
++	RTW_DBG("%s: cmd=%s\n", __func__, cmdname);
++
++	/* skip command string */
++	if (cmdlen > 0)
++		cmdlen += 1; /* skip one space */
++	ptr += cmdlen;
++	len -= cmdlen;
++	RTW_DBG("%s: parameters=%s\n", __func__, ptr);
++
++	priv = rtw_private_handler;
++	priv_args = rtw_private_args;
++	mp_priv_args = rtw_mp_private_args;
++	num_priv = sizeof(rtw_private_handler) / sizeof(iw_handler);
++	num_priv_args = sizeof(rtw_private_args) / sizeof(struct iw_priv_args);
++	num_mp_priv_args = sizeof(rtw_mp_private_args) / sizeof(struct iw_priv_args);
++
++	if (num_priv_args == 0) {
++		err = -EOPNOTSUPP;
++		goto exit;
++	}
++
++	/* Search the correct ioctl */
++	k = -1;
++	sel_priv_args = priv_args;
++	num_sel_priv_args = num_priv_args;
++	while
++	((++k < num_sel_priv_args) && strcmp(sel_priv_args[k].name, cmdname))
++		;
++
++	/* If not found... */
++	if (k == num_sel_priv_args) {
++		k = -1;
++		sel_priv_args = mp_priv_args;
++		num_sel_priv_args = num_mp_priv_args;
++		while
++		((++k < num_sel_priv_args) && strcmp(sel_priv_args[k].name, cmdname))
++			;
++
++		if (k == num_sel_priv_args) {
++			err = -EOPNOTSUPP;
++			goto exit;
++		}
++	}
++
++	/* Watch out for sub-ioctls ! */
++	if (sel_priv_args[k].cmd < SIOCDEVPRIVATE) {
++		int j = -1;
++
++		/* Find the matching *real* ioctl */
++		while ((++j < num_priv_args) && ((priv_args[j].name[0] != '\0') ||
++			 (priv_args[j].set_args != sel_priv_args[k].set_args) ||
++			 (priv_args[j].get_args != sel_priv_args[k].get_args)))
++			;
++
++		/* If not found... */
++		if (j == num_priv_args) {
++			err = -EINVAL;
++			goto exit;
++		}
++
++		/* Save sub-ioctl number */
++		subcmd = sel_priv_args[k].cmd;
++		/* Reserve one int (simplify alignment issues) */
++		offset = sizeof(__u32);
++		/* Use real ioctl definition from now on */
++		k = j;
++	}
++
++	buffer = rtw_zmalloc(4096);
++	if (NULL == buffer) {
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	if (k >= num_priv_args) {
++		err = -EINVAL;
++		goto exit;
++	}
++
++	/* If we have to set some data */
++	if ((priv_args[k].set_args & IW_PRIV_TYPE_MASK) &&
++	    (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) {
++		u8 *str;
++
++		switch (priv_args[k].set_args & IW_PRIV_TYPE_MASK) {
++		case IW_PRIV_TYPE_BYTE:
++			/* Fetch args */
++			count = 0;
++			do {
++				str = strsep(&ptr, delim);
++				if (NULL == str)
++					break;
++				sscanf(str, "%i", &temp);
++				buffer[count++] = (u8)temp;
++			} while (1);
++			buffer_len = count;
++
++			/* Number of args to fetch */
++			wdata.data.length = count;
++			if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK))
++				wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK;
++
++			break;
++
++		case IW_PRIV_TYPE_INT:
++			/* Fetch args */
++			count = 0;
++			do {
++				str = strsep(&ptr, delim);
++				if (NULL == str)
++					break;
++				sscanf(str, "%i", &temp);
++				((s32 *)buffer)[count++] = (s32)temp;
++			} while (1);
++			buffer_len = count * sizeof(s32);
++
++			/* Number of args to fetch */
++			wdata.data.length = count;
++			if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK))
++				wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK;
++
++			break;
++
++		case IW_PRIV_TYPE_CHAR:
++			if (len > 0) {
++				/* Size of the string to fetch */
++				wdata.data.length = len;
++				if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK))
++					wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK;
++
++				/* Fetch string */
++				_rtw_memcpy(buffer, ptr, wdata.data.length);
++			} else {
++				wdata.data.length = 1;
++				buffer[0] = '\0';
++			}
++			buffer_len = wdata.data.length;
++			break;
++
++		default:
++			RTW_INFO("%s: Not yet implemented...\n", __func__);
++			err = -1;
++			goto exit;
++		}
++
++		if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) &&
++		    (wdata.data.length != (priv_args[k].set_args & IW_PRIV_SIZE_MASK))) {
++			RTW_INFO("%s: The command %s needs exactly %d argument(s)...\n",
++				__func__, cmdname, priv_args[k].set_args & IW_PRIV_SIZE_MASK);
++			err = -EINVAL;
++			goto exit;
++		}
++	}   /* if args to set */
++	else
++		wdata.data.length = 0L;
++
++	/* Those two tests are important. They define how the driver
++	* will have to handle the data */
++	if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) &&
++	    ((get_priv_size(priv_args[k].set_args) + offset) <= IFNAMSIZ)) {
++		/* First case : all SET args fit within wrq */
++		if (offset)
++			wdata.mode = subcmd;
++		_rtw_memcpy(wdata.name + offset, buffer, IFNAMSIZ - offset);
++	} else {
++		if ((priv_args[k].set_args == 0) &&
++		    (priv_args[k].get_args & IW_PRIV_SIZE_FIXED) &&
++		    (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ)) {
++			/* Second case : no SET args, GET args fit within wrq */
++			if (offset)
++				wdata.mode = subcmd;
++		} else {
++			/* Third case : args won't fit in wrq, or variable number of args */
++			if (copy_to_user(wdata.data.pointer, buffer, buffer_len)) {
++				err = -EFAULT;
++				goto exit;
++			}
++			wdata.data.flags = subcmd;
++		}
++	}
++
++	rtw_mfree(input, input_len);
++	input = NULL;
++
++	extra_size = 0;
++	if (IW_IS_SET(priv_args[k].cmd)) {
++		/* Size of set arguments */
++		extra_size = get_priv_size(priv_args[k].set_args);
++
++		/* Does it fits in iwr ? */
++		if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) &&
++		    ((extra_size + offset) <= IFNAMSIZ))
++			extra_size = 0;
++	} else {
++		/* Size of get arguments */
++		extra_size = get_priv_size(priv_args[k].get_args);
++
++		/* Does it fits in iwr ? */
++		if ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) &&
++		    (extra_size <= IFNAMSIZ))
++			extra_size = 0;
++	}
++
++	if (extra_size == 0) {
++		extra = (u8 *)&wdata;
++		rtw_mfree(buffer, 4096);
++		buffer = NULL;
++	} else
++		extra = buffer;
++
++	handler = priv[priv_args[k].cmd - SIOCIWFIRSTPRIV];
++	err = handler(dev, NULL, &wdata, extra);
++
++	/* If we have to get some data */
++	if ((priv_args[k].get_args & IW_PRIV_TYPE_MASK) &&
++	    (priv_args[k].get_args & IW_PRIV_SIZE_MASK)) {
++		int j;
++		int n = 0;	/* number of args */
++		u8 str[20] = {0};
++
++		/* Check where is the returned data */
++		if ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) &&
++		    (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ))
++			n = priv_args[k].get_args & IW_PRIV_SIZE_MASK;
++		else
++			n = wdata.data.length;
++
++		output = rtw_zmalloc(4096);
++		if (NULL == output) {
++			err =  -ENOMEM;
++			goto exit;
++		}
++
++		switch (priv_args[k].get_args & IW_PRIV_TYPE_MASK) {
++		case IW_PRIV_TYPE_BYTE:
++			/* Display args */
++			for (j = 0; j < n; j++) {
++				sprintf(str, "%d  ", extra[j]);
++				len = strlen(str);
++				output_len = strlen(output);
++				if ((output_len + len + 1) > 4096) {
++					err = -E2BIG;
++					goto exit;
++				}
++				_rtw_memcpy(output + output_len, str, len);
++			}
++			break;
++
++		case IW_PRIV_TYPE_INT:
++			/* Display args */
++			for (j = 0; j < n; j++) {
++				sprintf(str, "%d  ", ((__s32 *)extra)[j]);
++				len = strlen(str);
++				output_len = strlen(output);
++				if ((output_len + len + 1) > 4096) {
++					err = -E2BIG;
++					goto exit;
++				}
++				_rtw_memcpy(output + output_len, str, len);
++			}
++			break;
++
++		case IW_PRIV_TYPE_CHAR:
++			/* Display args */
++			_rtw_memcpy(output, extra, n);
++			break;
++
++		default:
++			RTW_INFO("%s: Not yet implemented...\n", __func__);
++			err = -1;
++			goto exit;
++		}
++
++		output_len = strlen(output) + 1;
++		wrq_data->data.length = output_len;
++		if (copy_to_user(wrq_data->data.pointer, output, output_len)) {
++			err = -EFAULT;
++			goto exit;
++		}
++	}   /* if args to set */
++	else
++		wrq_data->data.length = 0;
++
++exit:
++	if (input)
++		rtw_mfree(input, input_len);
++	if (buffer)
++		rtw_mfree(buffer, 4096);
++	if (output)
++		rtw_mfree(output, 4096);
++
++	return err;
++}
++
++#ifdef CONFIG_COMPAT
++static int rtw_ioctl_compat_wext_private(struct net_device *dev, struct ifreq *rq)
++{
++	struct compat_iw_point iwp_compat;
++	union iwreq_data wrq_data;
++	int err = 0;
++	RTW_DBG("%s:...\n", __func__);
++	if (copy_from_user(&iwp_compat, rq->ifr_ifru.ifru_data, sizeof(struct compat_iw_point)))
++		return -EFAULT;
++
++	wrq_data.data.pointer = compat_ptr(iwp_compat.pointer);
++	wrq_data.data.length = iwp_compat.length;
++	wrq_data.data.flags = iwp_compat.flags;
++
++	err = _rtw_ioctl_wext_private(dev, &wrq_data);
++
++	iwp_compat.pointer = ptr_to_compat(wrq_data.data.pointer);
++	iwp_compat.length = wrq_data.data.length;
++	iwp_compat.flags = wrq_data.data.flags;
++	if (copy_to_user(rq->ifr_ifru.ifru_data, &iwp_compat, sizeof(struct compat_iw_point)))
++		return -EFAULT;
++
++	return err;
++}
++#endif /* CONFIG_COMPAT */
++
++static int rtw_ioctl_standard_wext_private(struct net_device *dev, struct ifreq *rq)
++{
++	struct iw_point *iwp;
++	union iwreq_data wrq_data;
++	int err = 0;
++	iwp = &wrq_data.data;
++	RTW_DBG("%s:...\n", __func__);
++	if (copy_from_user(iwp, rq->ifr_ifru.ifru_data, sizeof(struct iw_point)))
++		return -EFAULT;
++
++	err = _rtw_ioctl_wext_private(dev, &wrq_data);
++
++	if (copy_to_user(rq->ifr_ifru.ifru_data, iwp, sizeof(struct iw_point)))
++		return -EFAULT;
++
++	return err;
++}
++
++static int rtw_ioctl_wext_private(struct net_device *dev, struct ifreq *rq)
++{
++#ifdef CONFIG_COMPAT
++#if (KERNEL_VERSION(4, 6, 0) > LINUX_VERSION_CODE)
++	if (is_compat_task())
++#else
++	if (in_compat_syscall())
++#endif
++		return rtw_ioctl_compat_wext_private(dev, rq);
++	else
++#endif /* CONFIG_COMPAT */
++		return rtw_ioctl_standard_wext_private(dev, rq);
++}
++
++int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
++{
++	struct iwreq *wrq = (struct iwreq *)rq;
++	int ret = 0;
++
++	switch (cmd) {
++	case RTL_IOCTL_WPA_SUPPLICANT:
++		ret = wpa_supplicant_ioctl(dev, &wrq->u.data);
++		break;
++#ifdef CONFIG_AP_MODE
++	case RTL_IOCTL_HOSTAPD:
++		ret = rtw_hostapd_ioctl(dev, &wrq->u.data);
++		break;
++#ifdef CONFIG_WIRELESS_EXT
++	case SIOCSIWMODE:
++		ret = rtw_wx_set_mode(dev, NULL, &wrq->u, NULL);
++		break;
++#endif
++#endif /* CONFIG_AP_MODE */
++	case SIOCDEVPRIVATE:
++		ret = rtw_ioctl_wext_private(dev, rq);
++		break;
++	case (SIOCDEVPRIVATE+1):
++		ret = rtw_android_priv_cmd(dev, rq, cmd);
++		break;
++	default:
++		ret = -EOPNOTSUPP;
++		break;
++	}
++
++	return ret;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/ioctl_mp.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/ioctl_mp.c
+new file mode 100644
+index 000000000..cf5ca7622
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/ioctl_mp.c
+@@ -0,0 +1,3393 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#if defined(CONFIG_MP_INCLUDED)
++
++#include <drv_types.h>
++#include <rtw_mp.h>
++#include "../../hal/phydm/phydm_precomp.h"
++#include <linux/ctype.h>
++
++
++#if defined(CONFIG_RTL8723B)
++	#include <rtw_bt_mp.h>
++#endif
++
++/*
++ * Input Format: %s,%d,%d
++ *	%s is width, could be
++ *		"b" for 1 byte
++ *		"w" for WORD (2 bytes)
++ *		"dw" for DWORD (4 bytes)
++ *	1st %d is address(offset)
++ *	2st %d is data to write
++ */
++int rtw_mp_write_reg(struct net_device *dev,
++		     struct iw_request_info *info,
++		     struct iw_point *wrqu, char *extra)
++{
++	char *pch, *pnext;
++	char *width_str;
++	char width;
++	u32 addr, data;
++	int ret;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	char input[wrqu->length + 1];
++
++	_rtw_memset(input, 0, sizeof(input));
++
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	input[wrqu->length] = '\0';
++
++	_rtw_memset(extra, 0, wrqu->length);
++
++	pch = input;
++
++	pnext = strpbrk(pch, " ,.-");
++	if (pnext == NULL)
++		return -EINVAL;
++	*pnext = 0;
++	width_str = pch;
++
++	pch = pnext + 1;
++	pnext = strpbrk(pch, " ,.-");
++	if (pnext == NULL)
++		return -EINVAL;
++	*pnext = 0;
++	/*addr = simple_strtoul(pch, &ptmp, 16);
++	_rtw_memset(buf, '\0', sizeof(buf));
++	_rtw_memcpy(buf, pch, pnext-pch);
++	ret = kstrtoul(buf, 16, &addr);*/
++	ret = sscanf(pch, "%x", &addr);
++
++	pch = pnext + 1;
++	pnext = strpbrk(pch, " ,.-");
++	if ((pch - input) >= wrqu->length)
++		return -EINVAL;
++	/*data = simple_strtoul(pch, &ptmp, 16);*/
++	ret = sscanf(pch, "%x", &data);
++	RTW_INFO("data=%x,addr=%x\n", (u32)data, (u32)addr);
++	ret = 0;
++	width = width_str[0];
++	switch (width) {
++	case 'b':
++		/* 1 byte*/
++		if (data > 0xFF) {
++			ret = -EINVAL;
++			break;
++		}
++		rtw_write8(padapter, addr, data);
++		break;
++	case 'w':
++		/* 2 bytes*/
++		if (data > 0xFFFF) {
++			ret = -EINVAL;
++			break;
++		}
++		rtw_write16(padapter, addr, data);
++		break;
++	case 'd':
++		/* 4 bytes*/
++		rtw_write32(padapter, addr, data);
++		break;
++	default:
++		ret = -EINVAL;
++		break;
++	}
++
++	return ret;
++}
++
++
++/*
++ * Input Format: %s,%d
++ *	%s is width, could be
++ *		"b" for 1 byte
++ *		"w" for WORD (2 bytes)
++ *		"dw" for DWORD (4 bytes)
++ *	%d is address(offset)
++ *
++ * Return:
++ *	%d for data readed
++ */
++int rtw_mp_read_reg(struct net_device *dev,
++		    struct iw_request_info *info,
++		    struct iw_point *wrqu, char *extra)
++{
++	char input[wrqu->length + 1];
++	char *pch, *pnext;
++	char *width_str;
++	char width;
++	char data[20], tmp[20];
++	u32 addr = 0, strtout = 0;
++	u32 i = 0, j = 0, ret = 0, data32 = 0;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	char *pextra = extra;
++
++	if (wrqu->length > 128)
++		return -EFAULT;
++
++	_rtw_memset(input, 0, sizeof(input));
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	input[wrqu->length] = '\0';
++	_rtw_memset(extra, 0, wrqu->length);
++	_rtw_memset(data, '\0', sizeof(data));
++	_rtw_memset(tmp, '\0', sizeof(tmp));
++	pch = input;
++	pnext = strpbrk(pch, " ,.-");
++	if (pnext == NULL)
++		return -EINVAL;
++	*pnext = 0;
++	width_str = pch;
++
++	pch = pnext + 1;
++
++	ret = sscanf(pch, "%x", &addr);
++	if (addr > MP_READ_REG_MAX_OFFSET)
++		return -EINVAL;
++
++	ret = 0;
++	width = width_str[0];
++
++	switch (width) {
++	case 'b':
++		data32 = rtw_read8(padapter, addr);
++		RTW_INFO("%x\n", data32);
++		sprintf(extra, "%d", data32);
++		wrqu->length = strlen(extra);
++		break;
++	case 'w':
++		/* 2 bytes*/
++		sprintf(data, "%04x\n", rtw_read16(padapter, addr));
++
++		for (i = 0 ; i <= strlen(data) ; i++) {
++			if (i % 2 == 0) {
++				tmp[j] = ' ';
++				j++;
++			}
++			if (data[i] != '\0')
++				tmp[j] = data[i];
++
++			j++;
++		}
++		pch = tmp;
++		RTW_INFO("pch=%s", pch);
++
++		while (*pch != '\0') {
++			pnext = strpbrk(pch, " ");
++			if (!pnext || ((pnext - tmp) > 4))
++				break;
++
++			pnext++;
++			if (*pnext != '\0') {
++				/*strtout = simple_strtoul(pnext , &ptmp, 16);*/
++				ret = sscanf(pnext, "%x", &strtout);
++				pextra += sprintf(pextra, " %d", strtout);
++			} else
++				break;
++			pch = pnext;
++		}
++		wrqu->length = strlen(extra);
++		break;
++	case 'd':
++		/* 4 bytes */
++		sprintf(data, "%08x", rtw_read32(padapter, addr));
++		/*add read data format blank*/
++		for (i = 0 ; i <= strlen(data) ; i++) {
++			if (i % 2 == 0) {
++				tmp[j] = ' ';
++				j++;
++			}
++			if (data[i] != '\0')
++				tmp[j] = data[i];
++
++			j++;
++		}
++		pch = tmp;
++		RTW_INFO("pch=%s", pch);
++
++		while (*pch != '\0') {
++			pnext = strpbrk(pch, " ");
++			if (!pnext)
++				break;
++
++			pnext++;
++			if (*pnext != '\0') {
++				ret = sscanf(pnext, "%x", &strtout);
++				pextra += sprintf(pextra, " %d", strtout);
++			} else
++				break;
++			pch = pnext;
++		}
++		wrqu->length = strlen(extra);
++		break;
++
++	default:
++		wrqu->length = 0;
++		ret = -EINVAL;
++		break;
++	}
++
++	return ret;
++}
++
++
++/*
++ * Input Format: %d,%x,%x
++ *	%d is RF path, should be smaller than MAX_RF_PATH_NUMS
++ *	1st %x is address(offset)
++ *	2st %x is data to write
++ */
++int rtw_mp_write_rf(struct net_device *dev,
++		    struct iw_request_info *info,
++		    struct iw_point *wrqu, char *extra)
++{
++	u32 path, addr, data;
++	int ret;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++	char input[wrqu->length];
++
++
++	_rtw_memset(input, 0, wrqu->length);
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++
++	ret = sscanf(input, "%d,%x,%x", &path, &addr, &data);
++	if (ret < 3)
++		return -EINVAL;
++
++	if (path >= hal_spec->rf_reg_path_num)
++		return -EINVAL;
++	if (addr > 0xFF)
++		return -EINVAL;
++	if (data > 0xFFFFF)
++		return -EINVAL;
++
++	_rtw_memset(extra, 0, wrqu->length);
++
++	write_rfreg(padapter, path, addr, data);
++
++	sprintf(extra, "write_rf completed\n");
++	wrqu->length = strlen(extra);
++
++	return 0;
++}
++
++
++/*
++ * Input Format: %d,%x
++ *	%d is RF path, should be smaller than MAX_RF_PATH_NUMS
++ *	%x is address(offset)
++ *
++ * Return:
++ *	%d for data readed
++ */
++int rtw_mp_read_rf(struct net_device *dev,
++		   struct iw_request_info *info,
++		   struct iw_point *wrqu, char *extra)
++{
++	char input[wrqu->length];
++	char *pch, *pnext;
++	char data[20], tmp[20];
++	u32 path, addr, strtou;
++	u32 ret, i = 0 , j = 0;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++	char *pextra = extra;
++
++	if (wrqu->length > 128)
++		return -EFAULT;
++	_rtw_memset(input, 0, wrqu->length);
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	ret = sscanf(input, "%d,%x", &path, &addr);
++	if (ret < 2)
++		return -EINVAL;
++
++	if (path >= hal_spec->rf_reg_path_num)
++		return -EINVAL;
++
++	if (addr > MP_READ_REG_MAX_OFFSET)
++		return -EINVAL;
++
++	_rtw_memset(extra, 0, wrqu->length);
++
++	sprintf(data, "%08x", read_rfreg(padapter, path, addr));
++	/*add read data format blank*/
++	for (i = 0 ; i <= strlen(data) ; i++) {
++		if (i % 2 == 0) {
++			tmp[j] = ' ';
++			j++;
++		}
++		tmp[j] = data[i];
++		j++;
++	}
++	pch = tmp;
++	RTW_INFO("pch=%s", pch);
++
++	while (*pch != '\0') {
++		pnext = strpbrk(pch, " ");
++		if (!pnext)
++			break;
++		pnext++;
++		if (*pnext != '\0') {
++			/*strtou =simple_strtoul(pnext , &ptmp, 16);*/
++			ret = sscanf(pnext, "%x", &strtou);
++			pextra += sprintf(pextra, " %d", strtou);
++		} else
++			break;
++		pch = pnext;
++	}
++	wrqu->length = strlen(extra);
++
++	return 0;
++}
++
++
++int rtw_mp_start(struct net_device *dev,
++		 struct iw_request_info *info,
++		 struct iw_point *wrqu, char *extra)
++{
++	int ret = 0;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	struct mp_priv *pmppriv = &padapter->mppriv;
++
++	rtw_pm_set_ips(padapter, IPS_NONE);
++	LeaveAllPowerSaveMode(padapter);
++
++	pmppriv->bprocess_mp_mode = _TRUE;
++
++	if (rtw_mi_check_fwstate(padapter, WIFI_UNDER_SURVEY)) {
++		rtw_mi_buddy_set_scan_deny(padapter, 5000);
++		rtw_mi_scan_abort(padapter, _TRUE);
++	}
++
++	rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);
++
++	if (rtw_mp_cmd(padapter, MP_START, RTW_CMDF_WAIT_ACK) != _SUCCESS)
++		ret = -EPERM;
++
++	_rtw_memset(extra, 0, wrqu->length);
++	sprintf(extra, "mp_start %s\n", ret == 0 ? "ok" : "fail");
++	wrqu->length = strlen(extra);
++
++	return ret;
++}
++
++
++
++int rtw_mp_stop(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra)
++{
++	int ret = 0;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	struct mp_priv *pmppriv = &padapter->mppriv;
++
++	if (pmppriv->mode != MP_ON)
++		return -EPERM;
++
++	if (rtw_mp_cmd(padapter, MP_STOP, RTW_CMDF_WAIT_ACK) != _SUCCESS)
++		ret = -EPERM;
++
++	pmppriv->bprocess_mp_mode = _FALSE;
++	_rtw_memset(extra, 0, wrqu->length);
++	sprintf(extra, "mp_stop %s\n", ret == 0 ? "ok" : "fail");
++	wrqu->length = strlen(extra);
++
++	return ret;
++}
++
++
++int rtw_mp_rate(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra)
++{
++	u32 rate = MPT_RATE_1M;
++	u8 err = 0;
++	u8		input[wrqu->length + 1];
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	PMPT_CONTEXT		pMptCtx = &(padapter->mppriv.mpt_ctx);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++	struct	mp_priv	*pmppriv = &padapter->mppriv;
++
++	_rtw_memset(input, 0, sizeof(input));
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	input[wrqu->length] = '\0';
++	rate = rtw_mpRateParseFunc(padapter, input);
++	pmppriv->rateidx = rate;
++
++	if (rate == 0 && strcmp(input, "1M") != 0) {
++		rate = rtw_atoi(input);
++		if (rate <= MGN_VHT4SS_MCS9)
++			pmppriv->rateidx = MRateToHwRate(rate);
++		/*if (rate <= 0x7f)
++			rate = wifirate2_ratetbl_inx((u8)rate);
++		else if (rate < 0xC8)
++			rate = (rate - 0x79 + MPT_RATE_MCS0);
++		HT  rate 0x80(MCS0)  ~ 0x8F(MCS15) ~ 0x9F(MCS31) 128~159
++		VHT1SS~2SS rate 0xA0 (VHT1SS_MCS0 44) ~ 0xB3 (VHT2SS_MCS9 #63) 160~179
++		VHT rate 0xB4 (VHT3SS_MCS0 64) ~ 0xC7 (VHT2SS_MCS9 #83) 180~199
++		else
++		VHT rate 0x90(VHT1SS_MCS0) ~ 0x99(VHT1SS_MCS9) 144~153
++		rate =(rate - MPT_RATE_VHT1SS_MCS0);
++		*/
++	}
++
++	_rtw_memset(extra, 0, wrqu->length);
++
++	if (pmppriv->rateidx > DESC_RATEVHTSS4MCS9) {
++		sprintf(extra, "Set %s Error" , input);
++		return -EINVAL;
++	}
++
++	if (hal_spec->tx_nss_num < 2 && MPT_IS_2SS_RATE(HwRateToMPTRate(pmppriv->rateidx)))
++		err = 1;
++	if (hal_spec->tx_nss_num < 3 && MPT_IS_3SS_RATE(HwRateToMPTRate(pmppriv->rateidx)))
++		err = 1;
++	if (hal_spec->tx_nss_num < 4 && MPT_IS_4SS_RATE(HwRateToMPTRate(pmppriv->rateidx)))
++		err = 1;
++	if (!is_supported_vht(padapter->registrypriv.wireless_mode) && MPT_IS_VHT_RATE(HwRateToMPTRate(pmppriv->rateidx)))
++		err = 1;
++	if (!is_supported_ht(padapter->registrypriv.wireless_mode) && MPT_IS_HT_RATE(HwRateToMPTRate(pmppriv->rateidx)))
++		err = 1;
++
++	if (err == 1) {
++		sprintf(extra, "Set data rate to %s Error" , input);
++		pmppriv->rateidx = 0;
++	} else {
++		sprintf(extra, "Set data rate to %s index %d" , input, pmppriv->rateidx);
++		RTW_INFO("%s: %s rate index=%d\n", __func__, input, pmppriv->rateidx);
++		pMptCtx->mpt_rate_index = HwRateToMPTRate(pmppriv->rateidx);
++		SetDataRate(padapter);
++	}
++	wrqu->length = strlen(extra);
++	return err;
++}
++
++int rtw_mp_channel(struct net_device *dev,
++		   struct iw_request_info *info,
++		   struct iw_point *wrqu, char *extra)
++{
++
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
++	u8		input[wrqu->length + 1];
++	u32	channel = 1;
++
++	_rtw_memset(input, 0, sizeof(input));
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	input[wrqu->length] = '\0';
++	channel = rtw_atoi(input);
++	/*RTW_INFO("%s: channel=%d\n", __func__, channel);*/
++	_rtw_memset(extra, 0, wrqu->length);
++	sprintf(extra, "Change channel %d to channel %d", padapter->mppriv.channel , channel);
++	padapter->mppriv.channel = channel;
++	rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);
++	SetChannel(padapter);
++	pHalData->current_channel = channel;
++
++	wrqu->length = strlen(extra);
++	return 0;
++}
++
++
++int rtw_mp_ch_offset(struct net_device *dev,
++		   struct iw_request_info *info,
++		   struct iw_point *wrqu, char *extra)
++{
++
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	u8		input[wrqu->length + 1];
++	u32	ch_offset = 0;
++	char *pch;
++
++	_rtw_memset(input, 0, sizeof(input));
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	input[wrqu->length] = '\0';
++	ch_offset = rtw_atoi(input);
++	/*RTW_INFO("%s: channel=%d\n", __func__, channel);*/
++	_rtw_memset(extra, 0, wrqu->length);
++	pch = extra;
++	pch += sprintf(pch, "Change prime channel offset %d to %d", padapter->mppriv.prime_channel_offset , ch_offset);
++	padapter->mppriv.prime_channel_offset = ch_offset;
++	SetChannel(padapter);
++
++	wrqu->length = strlen(extra);
++	return 0;
++}
++
++
++int rtw_mp_bandwidth(struct net_device *dev,
++		     struct iw_request_info *info,
++		     struct iw_point *wrqu, char *extra)
++{
++	u32 bandwidth = 0, sg = 0;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
++	u8		input[wrqu->length];
++
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	if (sscanf(input, "40M=%d,shortGI=%d", &bandwidth, &sg) > 0)
++		RTW_INFO("%s: bw=%d sg=%d\n", __func__, bandwidth , sg);
++
++	if (bandwidth == 1 && hal_chk_bw_cap(padapter, BW_CAP_40M))
++		bandwidth = CHANNEL_WIDTH_40;
++	else if (bandwidth == 2 && hal_chk_bw_cap(padapter, BW_CAP_80M))
++		bandwidth = CHANNEL_WIDTH_80;
++	else
++		bandwidth = CHANNEL_WIDTH_20;
++
++	padapter->mppriv.bandwidth = (u8)bandwidth;
++	padapter->mppriv.preamble = sg;
++	_rtw_memset(extra, 0, wrqu->length);
++	sprintf(extra, "Change BW %d to BW %d\n", pHalData->current_channel_bw , bandwidth);
++	rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);
++	SetBandwidth(padapter);
++	pHalData->current_channel_bw = bandwidth;
++
++	wrqu->length = strlen(extra);
++
++	return 0;
++}
++
++
++int rtw_mp_txpower_index(struct net_device *dev,
++			 struct iw_request_info *info,
++			 struct iw_point *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++ 	HAL_DATA_TYPE	*phal_data	= GET_HAL_DATA(padapter);
++	char input[wrqu->length + 1];
++	u32 rfpath = 0 ;
++	u32 txpower_inx = 0, tarpowerdbm = 0;
++	char *pextra = extra;
++
++	if (wrqu->length > 128)
++		return -EFAULT;
++
++	_rtw_memset(input, 0, sizeof(input));
++
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	input[wrqu->length] = '\0';
++	_rtw_memset(extra, 0, strlen(extra));
++
++	if (wrqu->length == 2) {
++		if (input[0] != '\0' ) {
++			rfpath = rtw_atoi(input);
++			txpower_inx = mpt_ProQueryCalTxPower(padapter, rfpath);
++		}
++		pextra += sprintf(pextra, " %d\n", txpower_inx);
++		tarpowerdbm = mpt_get_tx_power_finalabs_val(padapter, rfpath);
++		if (tarpowerdbm > 0)
++			pextra += sprintf(pextra, "\t\t dBm:%d", tarpowerdbm);
++	} else {
++		if (phal_data->ant_path == 1)
++			rfpath = 1;
++		else
++			rfpath = 0;
++
++		txpower_inx = mpt_ProQueryCalTxPower(padapter, rfpath);
++		pextra += sprintf(pextra, "patha=%d", txpower_inx);
++		if (phal_data->rf_type > RF_1T2R) {
++			txpower_inx = mpt_ProQueryCalTxPower(padapter, 1);
++			pextra += sprintf(pextra, ",pathb=%d", txpower_inx);
++		}
++		if (phal_data->rf_type > RF_2T4R) {
++			txpower_inx = mpt_ProQueryCalTxPower(padapter, 2);
++			pextra += sprintf(pextra, ",pathc=%d", txpower_inx);
++		}
++		if (phal_data->rf_type > RF_3T4R) {
++			txpower_inx = mpt_ProQueryCalTxPower(padapter, 3);
++			pextra += sprintf(pextra, ",pathd=%d", txpower_inx);
++		}
++
++		tarpowerdbm = mpt_get_tx_power_finalabs_val(padapter, rfpath);
++		pextra += sprintf(pextra, "\n\t\t\tpatha dBm=%d", tarpowerdbm);
++		if (phal_data->rf_type > RF_1T2R) {
++			tarpowerdbm = mpt_get_tx_power_finalabs_val(padapter, 1);
++			pextra += sprintf(pextra, ",pathb dBm=%d", tarpowerdbm);
++		}
++		if (phal_data->rf_type > RF_2T4R) {
++			tarpowerdbm = mpt_get_tx_power_finalabs_val(padapter, 2);
++			pextra += sprintf(pextra, ",pathc dBm=%d", tarpowerdbm);
++		}
++		if (phal_data->rf_type > RF_3T4R) {
++			tarpowerdbm = mpt_get_tx_power_finalabs_val(padapter, 3);
++			pextra += sprintf(pextra, ",pathd dBm=%d", tarpowerdbm);
++		}
++	}
++	wrqu->length = strlen(extra);
++
++	return 0;
++}
++
++
++int rtw_mp_txpower(struct net_device *dev,
++		   struct iw_request_info *info,
++		   struct iw_point *wrqu, char *extra)
++{
++	u32 idx_a = 0, idx_b = 0, idx_c = 0, idx_d = 0;
++	int MsetPower = 1;
++	u8		input[wrqu->length];
++	u8 res = 0;
++
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	PMPT_CONTEXT		pMptCtx = &(padapter->mppriv.mpt_ctx);
++
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	MsetPower = strncmp(input, "off", 3);
++	if (MsetPower == 0) {
++		padapter->mppriv.bSetTxPower = 0;
++		sprintf(extra, "MP Set power off");
++	} else {
++			res = sscanf(input, "patha=%d,pathb=%d,pathc=%d,pathd=%d", &idx_a, &idx_b, &idx_c, &idx_d);
++			if (res < 1) {
++				if(isdigit(input[0])){
++					idx_a = rtw_atoi(input);
++					RTW_INFO("direct set RF Path A Power =%d\n", idx_a);
++				} else
++					RTW_INFO("Invalid format on %s !, Get patha=%d,pathb=%d,pathc=%d,pathd=%d\n", input , idx_a , idx_b , idx_c , idx_d);
++			}
++		if (res > 0 || idx_a !=0)
++			sprintf(extra, "Set power level path_A:%d path_B:%d path_C:%d path_D:%d", idx_a , idx_b , idx_c , idx_d);
++		else
++			sprintf(extra, "Invalid format on string :%s ", input);
++
++		padapter->mppriv.txpoweridx = (u8)idx_a;
++
++		pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)idx_a;
++		pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)idx_b;
++		pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)idx_c;
++		pMptCtx->TxPwrLevel[RF_PATH_D]  = (u8)idx_d;
++		padapter->mppriv.bSetTxPower = 1;
++
++		SetTxPower(padapter);
++	}
++
++	wrqu->length = strlen(extra);
++	return 0;
++}
++
++
++int rtw_mp_ant_tx(struct net_device *dev,
++		  struct iw_request_info *info,
++		  struct iw_point *wrqu, char *extra)
++{
++	u8 i;
++	u8		input[wrqu->length + 1];
++	u16 antenna = 0;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	_rtw_memset(input, 0, sizeof(input));
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	input[wrqu->length] = '\0';
++	sprintf(extra, "switch Tx antenna to %s", input);
++
++	for (i = 0; i < strlen(input); i++) {
++		switch (input[i]) {
++		case 'a':
++			antenna |= ANTENNA_A;
++			break;
++		case 'b':
++			antenna |= ANTENNA_B;
++			break;
++		case 'c':
++			antenna |= ANTENNA_C;
++			break;
++		case 'd':
++			antenna |= ANTENNA_D;
++			break;
++		}
++	}
++	/*antenna |= BIT(extra[i]-'a');*/
++	RTW_INFO("%s: antenna=0x%x\n", __func__, antenna);
++	padapter->mppriv.antenna_tx = antenna;
++
++	/*RTW_INFO("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_tx);*/
++	pHalData->antenna_tx_path = antenna;
++	if (IS_HARDWARE_TYPE_8822C(padapter) && padapter->mppriv.antenna_tx == ANTENNA_B) {
++		if (padapter->mppriv.antenna_rx == ANTENNA_A || padapter->mppriv.antenna_rx == ANTENNA_B) {
++			padapter->mppriv.antenna_rx = ANTENNA_AB;
++			pHalData->AntennaRxPath = ANTENNA_AB;
++			RTW_INFO("%s:8822C Tx-B Rx Ant to AB\n", __func__);
++		}
++	}
++	SetAntenna(padapter);
++
++	wrqu->length = strlen(extra);
++	return 0;
++}
++
++
++int rtw_mp_ant_rx(struct net_device *dev,
++		  struct iw_request_info *info,
++		  struct iw_point *wrqu, char *extra)
++{
++	u8 i;
++	u16 antenna = 0;
++	u8		input[wrqu->length + 1];
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	_rtw_memset(input, 0, sizeof(input));
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	input[wrqu->length] = '\0';
++	/*RTW_INFO("%s: input=%s\n", __func__, input);*/
++	_rtw_memset(extra, 0, wrqu->length);
++
++	sprintf(extra, "switch Rx antenna to %s", input);
++
++	for (i = 0; i < strlen(input); i++) {
++		switch (input[i]) {
++		case 'a':
++			antenna |= ANTENNA_A;
++			break;
++		case 'b':
++			antenna |= ANTENNA_B;
++			break;
++		case 'c':
++			antenna |= ANTENNA_C;
++			break;
++		case 'd':
++			antenna |= ANTENNA_D;
++			break;
++		}
++	}
++
++	RTW_INFO("%s: antenna=0x%x\n", __func__, antenna);
++
++	padapter->mppriv.antenna_rx = antenna;
++	pHalData->AntennaRxPath = antenna;
++	/*RTW_INFO("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_rx);*/
++	SetAntenna(padapter);
++	wrqu->length = strlen(extra);
++
++	return 0;
++}
++
++
++int rtw_set_ctx_destAddr(struct net_device *dev,
++			 struct iw_request_info *info,
++			 struct iw_point *wrqu, char *extra)
++{
++	int jj, kk = 0;
++
++	struct pkt_attrib *pattrib;
++	struct mp_priv *pmp_priv;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++
++	pmp_priv = &padapter->mppriv;
++	pattrib = &pmp_priv->tx.attrib;
++
++	if (strlen(extra) < 5)
++		return _FAIL;
++
++	RTW_INFO("%s: in=%s\n", __func__, extra);
++	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
++		pattrib->dst[jj] = key_2char2num(extra[kk], extra[kk + 1]);
++
++	RTW_INFO("pattrib->dst:%x %x %x %x %x %x\n", pattrib->dst[0], pattrib->dst[1], pattrib->dst[2], pattrib->dst[3], pattrib->dst[4], pattrib->dst[5]);
++	return 0;
++}
++
++
++
++int rtw_mp_ctx(struct net_device *dev,
++	       struct iw_request_info *info,
++	       struct iw_point *wrqu, char *extra)
++{
++	u32 pkTx = 1;
++	int countPkTx = 1, cotuTx = 1, CarrSprTx = 1, scTx = 1, sgleTx = 1, stop = 1, payload = 1;
++	u32 bStartTest = 1;
++	u32 count = 0, pktinterval = 0, pktlen = 0;
++	u8 status;
++	struct mp_priv *pmp_priv;
++	struct pkt_attrib *pattrib;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	pmp_priv = &padapter->mppriv;
++	pattrib = &pmp_priv->tx.attrib;
++
++	if (padapter->registrypriv.mp_mode != 1 ) {
++		sprintf(extra, "Error: can't tx ,not in MP mode. \n");
++		wrqu->length = strlen(extra);
++		return 0;
++	}
++
++	if (copy_from_user(extra, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	*(extra + wrqu->length) = '\0';
++	RTW_INFO("%s: in=%s\n", __func__, extra);
++#ifdef CONFIG_CONCURRENT_MODE
++	if (!is_primary_adapter(padapter)) {
++		sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n");
++		wrqu->length = strlen(extra);
++		return 0;
++	}
++#endif
++	countPkTx = strncmp(extra, "count=", 5); /* strncmp TRUE is 0*/
++	cotuTx = strncmp(extra, "background", 20);
++	CarrSprTx = strncmp(extra, "background,cs", 20);
++	scTx = strncmp(extra, "background,sc", 20);
++	sgleTx = strncmp(extra, "background,stone", 20);
++	pkTx = strncmp(extra, "background,pkt", 20);
++	stop = strncmp(extra, "stop", 4);
++	payload = strncmp(extra, "payload=", 8);
++
++	if (sscanf(extra, "count=%d,pkt", &count) > 0)
++		RTW_INFO("count= %d\n", count);
++	if (sscanf(extra, "pktinterval=%d", &pktinterval) > 0)
++		RTW_INFO("pktinterval= %d\n", pktinterval);
++	if (sscanf(extra, "pktlen=%d", &pktlen) > 0)
++		RTW_INFO("pktlen= %d\n", pktlen);
++
++	if (payload == 0) {
++			payload = MP_TX_Payload_default_random;
++			if (strncmp(extra, "payload=prbs9", 14) == 0) {
++				payload = MP_TX_Payload_prbs9;
++				sprintf(extra, "config payload PRBS9\n");
++			} else {
++				if (sscanf(extra, "payload=%x", &payload) > 0){
++					RTW_INFO("payload= %x\n", payload);
++					sprintf(extra, "config payload setting = %x\n"
++									"1. input payload=[]:\n		"
++									"[0]: 00, [1]: A5, [2]: 5A, [3]: FF, [4]: PRBS-9, [5]: Random\n"
++									"2. specified a hex payload: payload=0xee\n", payload);
++				 }
++			}
++			pmp_priv->tx.payload = payload;
++			wrqu->length = strlen(extra);
++			return 0;
++	}
++
++	if (_rtw_memcmp(extra, "destmac=", 8)) {
++		wrqu->length -= 8;
++		rtw_set_ctx_destAddr(dev, info, wrqu, &extra[8]);
++		sprintf(extra, "Set dest mac OK !\n");
++		return 0;
++	}
++	/*RTW_INFO("%s: count=%d countPkTx=%d cotuTx=%d CarrSprTx=%d scTx=%d sgleTx=%d pkTx=%d stop=%d\n", __func__, count, countPkTx, cotuTx, CarrSprTx, pkTx, sgleTx, scTx, stop);*/
++	_rtw_memset(extra, '\0', strlen(extra));
++
++	if (pktinterval != 0) {
++		sprintf(extra, "Pkt Interval = %d", pktinterval);
++		padapter->mppriv.pktInterval = pktinterval;
++		wrqu->length = strlen(extra);
++		return 0;
++
++	} else if (pktlen != 0) {
++		sprintf(extra, "Pkt len = %d", pktlen);
++		pattrib->pktlen = pktlen;
++		wrqu->length = strlen(extra);
++		return 0;
++
++	} else if (stop == 0) {
++		struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
++		_queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue;
++		_queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue;
++
++		u32 i = 0;
++		bStartTest = 0; /* To set Stop*/
++		pmp_priv->tx.stop = 1;
++		sprintf(extra, "Stop continuous Tx");
++		odm_write_dig(&pHalData->odmpriv, 0x20);
++		do {
++			if (pxmitpriv->free_xmitframe_cnt == NR_XMITFRAME && pxmitpriv->free_xmitbuf_cnt == NR_XMITBUFF)
++				break;
++			else {
++				i++;
++				RTW_INFO("%s:wait queue_empty %d!!\n", __func__, i);
++				rtw_msleep_os(10);
++			}
++		} while (i < 1000);
++	} else {
++		bStartTest = 1;
++		odm_write_dig(&pHalData->odmpriv, 0x3f);
++		if (IS_HARDWARE_TYPE_8822C(padapter) && pmp_priv->antenna_tx == ANTENNA_B) {
++			if (pmp_priv->antenna_rx == ANTENNA_A || pmp_priv->antenna_rx == ANTENNA_B) {
++				pmp_priv->antenna_rx = ANTENNA_AB;
++				pHalData->AntennaRxPath = ANTENNA_AB;
++				RTW_INFO("%s:8822C Tx-B Rx Ant to AB\n", __func__);
++				SetAntenna(padapter);
++			}
++		}
++		if (pmp_priv->mode != MP_ON) {
++			if (pmp_priv->tx.stop != 1) {
++				RTW_INFO("%s:Error MP_MODE %d != ON\n", __func__, pmp_priv->mode);
++				return	-EFAULT;
++			}
++		}
++	}
++
++	pmp_priv->tx.count = count;
++
++	if (pkTx == 0 || countPkTx == 0)
++		pmp_priv->mode = MP_PACKET_TX;
++	if (sgleTx == 0)
++		pmp_priv->mode = MP_SINGLE_TONE_TX;
++	if (cotuTx == 0)
++		pmp_priv->mode = MP_CONTINUOUS_TX;
++	if (CarrSprTx == 0)
++		pmp_priv->mode = MP_CARRIER_SUPPRISSION_TX;
++	if (scTx == 0)
++		pmp_priv->mode = MP_SINGLE_CARRIER_TX;
++
++	status = rtw_mp_pretx_proc(padapter, bStartTest, extra);
++
++	if (stop == 0)
++		pmp_priv->mode = MP_ON;
++
++	wrqu->length = strlen(extra);
++	return status;
++}
++
++
++
++int rtw_mp_disable_bt_coexist(struct net_device *dev,
++			      struct iw_request_info *info,
++			      union iwreq_data *wrqu, char *extra)
++{
++#ifdef CONFIG_BT_COEXIST
++	PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev);
++
++#endif
++	u8 input[wrqu->data.length + 1];
++	u32 bt_coexist;
++
++	_rtw_memset(input, 0, sizeof(input));
++
++	if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length))
++		return -EFAULT;
++
++	input[wrqu->data.length] = '\0';
++
++	bt_coexist = rtw_atoi(input);
++
++	if (bt_coexist == 0) {
++		RTW_INFO("Set OID_RT_SET_DISABLE_BT_COEXIST: disable BT_COEXIST\n");
++#ifdef CONFIG_BT_COEXIST
++		rtw_btcoex_HaltNotify(padapter);
++		rtw_btcoex_SetManualControl(padapter, _TRUE);
++		/* Force to switch Antenna to WiFi*/
++		rtw_write16(padapter, 0x870, 0x300);
++		rtw_write16(padapter, 0x860, 0x110);
++#endif
++		/* CONFIG_BT_COEXIST */
++	} else {
++#ifdef CONFIG_BT_COEXIST
++		rtw_btcoex_SetManualControl(padapter, _FALSE);
++#endif
++	}
++
++	return 0;
++}
++
++
++int rtw_mp_arx(struct net_device *dev,
++	       struct iw_request_info *info,
++	       struct iw_point *wrqu, char *extra)
++{
++	int bStartRx = 0, bStopRx = 0, bQueryPhy = 0, bQueryMac = 0, bSetBssid = 0, bSetRxframe = 0;
++	int bmac_filter = 0, bmon = 0, bSmpCfg = 0;
++	u8		input[wrqu->length];
++	char *pch, *token, *tmp[2] = {0x00, 0x00};
++	u32 i = 0, jj = 0, kk = 0, cnts = 0, ret;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	struct mp_priv *pmppriv = &padapter->mppriv;
++	struct dbg_rx_counter rx_counter;
++
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	RTW_INFO("%s: %s\n", __func__, input);
++#ifdef CONFIG_CONCURRENT_MODE
++	if (!is_primary_adapter(padapter)) {
++		sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n");
++		wrqu->length = strlen(extra);
++		return 0;
++	}
++#endif
++	bStartRx = (strncmp(input, "start", 5) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
++	bStopRx = (strncmp(input, "stop", 5) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
++	bQueryPhy = (strncmp(input, "phy", 3) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
++	bQueryMac = (strncmp(input, "mac", 3) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
++	bSetBssid = (strncmp(input, "setbssid=", 8) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
++	bSetRxframe = (strncmp(input, "frametype", 9) == 0) ? 1 : 0;
++	/*bfilter_init = (strncmp(input, "filter_init",11)==0)?1:0;*/
++	bmac_filter = (strncmp(input, "accept_mac", 10) == 0) ? 1 : 0;
++	bmon = (strncmp(input, "mon=", 4) == 0) ? 1 : 0;
++	bSmpCfg = (strncmp(input , "smpcfg=" , 7) == 0) ? 1 : 0;
++	pmppriv->bloopback = (strncmp(input, "loopbk", 6) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
++
++	if (bSetBssid == 1) {
++		pch = input;
++		while ((token = strsep(&pch, "=")) != NULL) {
++			if (i > 1)
++				break;
++			tmp[i] = token;
++			i++;
++		}
++		if ((tmp[0] != NULL) && (tmp[1] != NULL)) {
++			cnts = strlen(tmp[1]) / 2;
++			if (cnts < 1)
++				return -EFAULT;
++			RTW_INFO("%s: cnts=%d\n", __func__, cnts);
++			RTW_INFO("%s: data=%s\n", __func__, tmp[1]);
++			for (jj = 0, kk = 0; jj < cnts ; jj++, kk += 2) {
++				pmppriv->network_macaddr[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
++				RTW_INFO("network_macaddr[%d]=%x\n", jj, pmppriv->network_macaddr[jj]);
++			}
++		} else
++			return -EFAULT;
++
++		pmppriv->bSetRxBssid = _TRUE;
++	}
++	if (bSetRxframe) {
++		if (strncmp(input, "frametype beacon", 16) == 0)
++			pmppriv->brx_filter_beacon = _TRUE;
++		else
++			pmppriv->brx_filter_beacon = _FALSE;
++	}
++
++	if (bmac_filter) {
++		pmppriv->bmac_filter = bmac_filter;
++		pch = input;
++		while ((token = strsep(&pch, "=")) != NULL) {
++			if (i > 1)
++				break;
++			tmp[i] = token;
++			i++;
++		}
++		if ((tmp[0] != NULL) && (tmp[1] != NULL)) {
++			cnts = strlen(tmp[1]) / 2;
++			if (cnts < 1)
++				return -EFAULT;
++			RTW_INFO("%s: cnts=%d\n", __func__, cnts);
++			RTW_INFO("%s: data=%s\n", __func__, tmp[1]);
++			for (jj = 0, kk = 0; jj < cnts ; jj++, kk += 2) {
++				pmppriv->mac_filter[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
++				RTW_INFO("%s mac_filter[%d]=%x\n", __func__, jj, pmppriv->mac_filter[jj]);
++			}
++		} else
++			return -EFAULT;
++
++	}
++
++	if (bStartRx) {
++		sprintf(extra, "start");
++		SetPacketRx(padapter, bStartRx, _FALSE);
++	} else if (bStopRx) {
++		SetPacketRx(padapter, bStartRx, _FALSE);
++		pmppriv->bmac_filter = _FALSE;
++		pmppriv->bSetRxBssid = _FALSE;
++		sprintf(extra, "Received packet OK:%d CRC error:%d ,Filter out:%d", padapter->mppriv.rx_pktcount, padapter->mppriv.rx_crcerrpktcount, padapter->mppriv.rx_pktcount_filter_out);
++	} else if (bQueryPhy) {
++		_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
++		rtw_dump_phy_rx_counters(padapter, &rx_counter);
++
++		RTW_INFO("%s: OFDM_FA =%d\n", __func__, rx_counter.rx_ofdm_fa);
++		RTW_INFO("%s: CCK_FA =%d\n", __func__, rx_counter.rx_cck_fa);
++		sprintf(extra, "Phy Received packet OK:%d CRC error:%d FA Counter: %d", rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_cck_fa + rx_counter.rx_ofdm_fa);
++
++
++	} else if (bQueryMac) {
++		_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
++		rtw_dump_mac_rx_counters(padapter, &rx_counter);
++		sprintf(extra, "Mac Received packet OK: %d , CRC error: %d , Drop Packets: %d\n",
++			rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_pkt_drop);
++
++	}
++
++	if (bmon == 1) {
++		ret = sscanf(input, "mon=%d", &bmon);
++
++		if (bmon == 1) {
++			pmppriv->rx_bindicatePkt = _TRUE;
++			sprintf(extra, "Indicating Receive Packet to network start\n");
++		} else {
++			pmppriv->rx_bindicatePkt = _FALSE;
++			sprintf(extra, "Indicating Receive Packet to network Stop\n");
++		}
++	}
++	if (bSmpCfg == 1) {
++		ret = sscanf(input, "smpcfg=%d", &bSmpCfg);
++
++		if (bSmpCfg == 1) {
++			pmppriv->bRTWSmbCfg = _TRUE;
++			sprintf(extra , "Indicate By Simple Config Format\n");
++			SetPacketRx(padapter, _TRUE, _TRUE);
++		} else {
++			pmppriv->bRTWSmbCfg = _FALSE;
++			sprintf(extra , "Indicate By Normal Format\n");
++			SetPacketRx(padapter, _TRUE, _FALSE);
++		}
++	}
++
++	if (pmppriv->bloopback == _TRUE) {
++		sprintf(extra , "Enter MAC LoopBack mode\n");
++#if defined(CONFIG_RTL8814B)
++		/* 1. No adhoc, 2. Enable short cut */
++		rtw_write32(padapter, 0x100, 0x0B000EFF);
++#else
++		rtw_write32(padapter, 0x100, 0x0B0106FF);
++#endif
++		RTW_INFO("0x100 :0x%x", rtw_read32(padapter, 0x100));
++		rtw_write16(padapter, 0x608, 0x30c);
++		RTW_INFO("0x608 :0x%x", rtw_read32(padapter, 0x608));
++	}
++
++	wrqu->length = strlen(extra) + 1;
++
++	return 0;
++}
++
++
++int rtw_mp_trx_query(struct net_device *dev,
++		     struct iw_request_info *info,
++		     struct iw_point *wrqu, char *extra)
++{
++	u32 txok, txfail, rxok, rxfail, rxfilterout;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	PMPT_CONTEXT	pMptCtx		=	&(padapter->mppriv.mpt_ctx);
++	RT_PMAC_TX_INFO	PMacTxInfo	=	pMptCtx->PMacTxInfo;
++
++	if (PMacTxInfo.bEnPMacTx == TRUE)
++		txok = hal_mpt_query_phytxok(padapter);
++	else
++		txok = padapter->mppriv.tx.sended;
++
++	txfail = 0;
++	rxok = padapter->mppriv.rx_pktcount;
++	rxfail = padapter->mppriv.rx_crcerrpktcount;
++	rxfilterout = padapter->mppriv.rx_pktcount_filter_out;
++
++	_rtw_memset(extra, '\0', 128);
++
++	sprintf(extra, "Tx OK:%d, Tx Fail:%d, Rx OK:%d, CRC error:%d ,Rx Filter out:%d\n", txok, txfail, rxok, rxfail, rxfilterout);
++
++	wrqu->length = strlen(extra) + 1;
++
++	return 0;
++}
++
++
++int rtw_mp_pwrtrk(struct net_device *dev,
++		  struct iw_request_info *info,
++		  struct iw_point *wrqu, char *extra)
++{
++	u8 enable;
++	u32 thermal;
++	s32 ret;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	u8		input[wrqu->length];
++
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	_rtw_memset(extra, 0, wrqu->length);
++
++	enable = 1;
++	if (wrqu->length > 1) {
++		/* not empty string*/
++		if (strncmp(input, "stop", 4) == 0) {
++			enable = 0;
++			sprintf(extra, "mp tx power tracking stop");
++		} else if (sscanf(input, "ther=%d", &thermal) == 1) {
++			ret = SetThermalMeter(padapter, (u8)thermal);
++			if (ret == _FAIL)
++				return -EPERM;
++			sprintf(extra, "mp tx power tracking start,target value=%d ok", thermal);
++		} else
++			return -EINVAL;
++	}
++
++	ret = SetPowerTracking(padapter, enable);
++	if (ret == _FAIL)
++		return -EPERM;
++
++	wrqu->length = strlen(extra);
++
++	return 0;
++}
++
++
++
++int rtw_mp_psd(struct net_device *dev,
++	       struct iw_request_info *info,
++	       struct iw_point *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	u8		input[wrqu->length + 1];
++
++	_rtw_memset(input, 0, sizeof(input));
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	input[wrqu->length] = '\0';
++	strcpy(extra, input);
++
++	wrqu->length = mp_query_psd(padapter, extra);
++
++	return 0;
++}
++
++
++int rtw_mp_thermal(struct net_device *dev,
++		   struct iw_request_info *info,
++		   struct iw_point *wrqu, char *extra)
++{
++	u8 val[4] = {0};
++	u8 ret = 0;
++	u16 ther_path_addr[4] = {0};
++	u16 cnt = 1;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++	int rfpath = RF_PATH_A;
++
++#ifdef CONFIG_RTL8188E
++	ther_path_addr[0] = EEPROM_THERMAL_METER_88E;
++#endif
++#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
++	ther_path_addr[0] = EEPROM_THERMAL_METER_8812;
++#endif
++#ifdef CONFIG_RTL8192E
++	ther_path_addr[0] = EEPROM_THERMAL_METER_8192E;
++#endif
++#ifdef CONFIG_RTL8192F
++	ther_path_addr[0] = EEPROM_THERMAL_METER_8192F;
++#endif
++#ifdef CONFIG_RTL8723B
++	ther_path_addr[0] = EEPROM_THERMAL_METER_8723B;
++#endif
++#ifdef CONFIG_RTL8703B
++	ther_path_addr[0] = EEPROM_THERMAL_METER_8703B;
++#endif
++#ifdef CONFIG_RTL8723D
++	ther_path_addr[0] = EEPROM_THERMAL_METER_8723D;
++#endif
++#ifdef CONFIG_RTL8188F
++	ther_path_addr[0] = EEPROM_THERMAL_METER_8188F;
++#endif
++#ifdef CONFIG_RTL8188GTV
++	ther_path_addr[0] = EEPROM_THERMAL_METER_8188GTV;
++#endif
++#ifdef CONFIG_RTL8822B
++	ther_path_addr[0] = EEPROM_THERMAL_METER_8822B;
++#endif
++#ifdef CONFIG_RTL8821C
++	ther_path_addr[0] = EEPROM_THERMAL_METER_8821C;
++#endif
++#ifdef CONFIG_RTL8710B
++	ther_path_addr[0] = EEPROM_THERMAL_METER_8710B;
++#endif
++#ifdef CONFIG_RTL8822C
++	ther_path_addr[0]  = EEPROM_THERMAL_METER_A_8822C;
++	ther_path_addr[1]  = EEPROM_THERMAL_METER_B_8822C;
++#endif
++#ifdef CONFIG_RTL8814B
++	ther_path_addr[0] = EEPROM_THERMAL_METER_A_8814B;
++	ther_path_addr[1] = EEPROM_THERMAL_METER_B_8814B;
++	ther_path_addr[2] = EEPROM_THERMAL_METER_C_8814B;
++	ther_path_addr[3] = EEPROM_THERMAL_METER_D_8814B;
++#endif
++
++	if (copy_from_user(extra, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	if ((strncmp(extra, "write", 6) == 0)) {
++		int i;
++		u16 raw_cursize = 0, raw_maxsize = 0;
++#ifdef RTW_HALMAC
++		raw_maxsize = efuse_GetavailableSize(padapter);
++#else
++		efuse_GetCurrentSize(padapter, &raw_cursize);
++		raw_maxsize = efuse_GetMaxSize(padapter);
++#endif
++		RTW_INFO("[eFuse available raw size]= %d bytes\n", raw_maxsize - raw_cursize);
++		if (2 > raw_maxsize - raw_cursize) {
++			RTW_INFO("no available efuse!\n");
++			return -EFAULT;
++		}
++
++		for (i = 0; i < hal_spec->rf_reg_path_num; i++) {
++				GetThermalMeter(padapter, i , &val[i]);
++				if (ther_path_addr[i] != 0 && val[i] != 0) {
++					if (rtw_efuse_map_write(padapter, ther_path_addr[i], cnt, &val[i]) == _FAIL) {
++						RTW_INFO("Error efuse write thermal addr 0x%x ,val = 0x%x\n", ther_path_addr[i], val[i]);
++						return -EFAULT;
++					}
++				} else {
++						RTW_INFO("Error efuse write thermal Null addr,val \n");
++						return -EFAULT;
++				}
++		}
++		_rtw_memset(extra, 0, wrqu->length);
++		sprintf(extra, " efuse write ok :%d", val[0]);
++	} else {
++		ret = sscanf(extra, "%d", &rfpath);
++		if (ret < 1) {
++			rfpath = RF_PATH_A;
++			RTW_INFO("default thermal of path(%d)\n", rfpath);
++		}
++		if (rfpath >= hal_spec->rf_reg_path_num)
++			return -EINVAL;
++
++		RTW_INFO("read thermal of path(%d)\n", rfpath);
++		GetThermalMeter(padapter, rfpath, &val[0]);
++
++		_rtw_memset(extra, 0, wrqu->length);
++		sprintf(extra, "%d", val[0]);
++	}
++	wrqu->length = strlen(extra);
++
++	return 0;
++}
++
++
++
++int rtw_mp_reset_stats(struct net_device *dev,
++		       struct iw_request_info *info,
++		       struct iw_point *wrqu, char *extra)
++{
++	struct mp_priv *pmp_priv;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++
++	pmp_priv = &padapter->mppriv;
++
++	pmp_priv->tx.sended = 0;
++	pmp_priv->tx_pktcount = 0;
++	pmp_priv->rx_pktcount = 0;
++	pmp_priv->rx_pktcount_filter_out = 0;
++	pmp_priv->rx_crcerrpktcount = 0;
++
++	rtw_reset_phy_rx_counters(padapter);
++	rtw_reset_mac_rx_counters(padapter);
++
++	_rtw_memset(extra, 0, wrqu->length);
++	sprintf(extra, "mp_reset_stats ok\n");
++	wrqu->length = strlen(extra);
++
++	return 0;
++}
++
++
++int rtw_mp_dump(struct net_device *dev,
++		struct iw_request_info *info,
++		struct iw_point *wrqu, char *extra)
++{
++	struct mp_priv *pmp_priv;
++	u8		input[wrqu->length];
++	PADAPTER padapter = rtw_netdev_priv(dev);
++
++	pmp_priv = &padapter->mppriv;
++
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	if (strncmp(input, "all", 4) == 0) {
++		mac_reg_dump(RTW_DBGDUMP, padapter);
++		bb_reg_dump(RTW_DBGDUMP, padapter);
++		rf_reg_dump(RTW_DBGDUMP, padapter);
++	}
++	return 0;
++}
++
++
++int rtw_mp_phypara(struct net_device *dev,
++		   struct iw_request_info *info,
++		   struct iw_point *wrqu, char *extra)
++{
++
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
++	char	input[wrqu->length];
++	u32		invalxcap = 0, ret = 0, bwrite_xcap = 0, hwxtaladdr = 0;
++	u16		pgval;
++
++
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	RTW_INFO("%s:priv in=%s\n", __func__, input);
++	bwrite_xcap = (strncmp(input, "write_xcap=", 11) == 0) ? 1 : 0;
++
++	if (bwrite_xcap == 1) {
++		ret = sscanf(input, "write_xcap=%d", &invalxcap);
++		invalxcap = invalxcap & 0x7f; /* xtal bit 0 ~6 */
++		RTW_INFO("get crystal_cap %d\n", invalxcap);
++
++		if (IS_HARDWARE_TYPE_8822C(padapter) && ret == 1) {
++			hwxtaladdr = 0x110;
++			pgval = invalxcap | 0x80; /* reserved default bit7 on */
++			pgval = pgval | pgval << 8; /* xtal xi/xo efuse 0x110 0x111 */
++
++			RTW_INFO("Get crystal_cap 0x%x\n", pgval);
++			if (rtw_efuse_map_write(padapter, hwxtaladdr, 2, (u8*)&pgval) == _FAIL) {
++					RTW_INFO("%s: rtw_efuse_map_write xcap error!!\n", __func__);
++					sprintf(extra, "write xcap pgdata fail");
++					ret = -EFAULT;
++			} else
++					sprintf(extra, "write xcap pgdata ok");
++
++		}
++	} else {
++		ret = sscanf(input, "xcap=%d", &invalxcap);
++
++		if (ret == 1) {
++			pHalData->crystal_cap = (u8)invalxcap;
++			RTW_INFO("%s:crystal_cap=%d\n", __func__, pHalData->crystal_cap);
++
++			if (rtw_phydm_set_crystal_cap(padapter, pHalData->crystal_cap) == _FALSE) {
++				RTW_ERR("set crystal_cap failed\n");
++				rtw_warn_on(1);
++			}
++			sprintf(extra, "Set xcap=%d", invalxcap);
++		}
++	}
++
++	wrqu->length = strlen(extra) + 1;
++	return ret;
++}
++
++
++int rtw_mp_SetRFPath(struct net_device *dev,
++		     struct iw_request_info *info,
++		     struct iw_point *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	char	input[wrqu->length];
++	int		bMain = 1, bTurnoff = 1;
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	u8 ret = _TRUE;
++#endif
++
++	RTW_INFO("%s:iwpriv in=%s\n", __func__, input);
++
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	bMain = strncmp(input, "1", 2); /* strncmp TRUE is 0*/
++	bTurnoff = strncmp(input, "0", 3); /* strncmp TRUE is 0*/
++
++	_rtw_memset(extra, 0, wrqu->length);
++#ifdef CONFIG_ANTENNA_DIVERSITY
++	if (bMain == 0)
++		ret = rtw_mp_set_antdiv(padapter, _TRUE);
++	else
++		ret = rtw_mp_set_antdiv(padapter, _FALSE);
++	if (ret == _FALSE)
++		RTW_INFO("%s:ANTENNA_DIVERSITY FAIL\n", __func__);
++#endif
++
++	if (bMain == 0) {
++		MP_PHY_SetRFPathSwitch(padapter, _TRUE);
++		RTW_INFO("%s:PHY_SetRFPathSwitch=TRUE\n", __func__);
++		sprintf(extra, "mp_setrfpath Main\n");
++
++	} else if (bTurnoff == 0) {
++		MP_PHY_SetRFPathSwitch(padapter, _FALSE);
++		RTW_INFO("%s:PHY_SetRFPathSwitch=FALSE\n", __func__);
++		sprintf(extra, "mp_setrfpath Aux\n");
++	} else {
++		bMain = MP_PHY_QueryRFPathSwitch(padapter);
++		RTW_INFO("%s:Query RF Path = %s\n", __func__, (bMain ? "Main":"Aux"));
++		sprintf(extra, "RF Path %s\n" , (bMain ? "1":"0"));
++	}
++
++	wrqu->length = strlen(extra);
++
++	return 0;
++}
++
++
++int rtw_mp_switch_rf_path(struct net_device *dev,
++			struct iw_request_info *info,
++			struct iw_point *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	struct mp_priv *pmp_priv;
++	char	input[wrqu->length];
++	char *pch;
++	int		bwlg = 1, bwla = 1, btg = 1, bbt=1;
++	u8 ret = 0;
++
++
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	pmp_priv = &padapter->mppriv;
++
++	RTW_INFO("%s: in=%s\n", __func__, input);
++
++	_rtw_memset(extra, '\0', wrqu->length);
++	pch = extra;
++#ifdef CONFIG_RTL8821C /* only support for 8821c wlg/wla/btg/bt RF switch path */
++	if ((strncmp(input, "WLG", 3) == 0) || (strncmp(input, "1", 1) == 0)) {
++		pmp_priv->rf_path_cfg = SWITCH_TO_WLG;
++		pch += sprintf(pch, "switch rf path WLG\n");
++
++	} else if ((strncmp(input, "WLA", 3) == 0) || (strncmp(input, "2", 1) == 0)) {
++		pmp_priv->rf_path_cfg = SWITCH_TO_WLA;
++		pch += sprintf(pch, "switch rf path WLA\n");
++
++	} else if ((strncmp(input, "BTG", 3) == 0) || (strncmp(input, "0", 1) == 0)) {
++		pmp_priv->rf_path_cfg = SWITCH_TO_BTG;
++		pch += sprintf(pch, "switch rf path BTG\n");
++
++	} else if ((strncmp(input, "BT", 3) == 0) || (strncmp(input, "3", 1) == 0)) {
++		pmp_priv->rf_path_cfg = SWITCH_TO_BT;
++		pch += sprintf(pch, "switch rf path BT\n");
++	} else {
++		pmp_priv->rf_path_cfg = SWITCH_TO_WLG;
++		pch += sprintf(pch, "Error input, default set WLG\n");
++		return -EFAULT;
++	}
++
++	mp_phy_switch_rf_path_set(padapter, &pmp_priv->rf_path_cfg);
++#endif
++	wrqu->length = strlen(extra);
++
++	return ret;
++
++}
++int rtw_mp_QueryDrv(struct net_device *dev,
++		    struct iw_request_info *info,
++		    union iwreq_data *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	char	input[wrqu->data.length];
++	int	qAutoLoad = 1;
++
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++
++	if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length))
++		return -EFAULT;
++	RTW_INFO("%s:iwpriv in=%s\n", __func__, input);
++
++	qAutoLoad = strncmp(input, "autoload", 8); /* strncmp TRUE is 0*/
++
++	if (qAutoLoad == 0) {
++		RTW_INFO("%s:qAutoLoad\n", __func__);
++
++		if (pHalData->bautoload_fail_flag)
++			sprintf(extra, "fail");
++		else
++			sprintf(extra, "ok");
++	}
++	wrqu->data.length = strlen(extra) + 1;
++	return 0;
++}
++
++
++int rtw_mp_PwrCtlDM(struct net_device *dev,
++		    struct iw_request_info *info,
++		    struct iw_point *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	u8		input[wrqu->length];
++	u8		pwrtrk_state = 0;
++	u8		pwtk_type[5][25] = {"Thermal tracking off","Thermal tracking on",
++					"TSSI tracking off","TSSI tracking on","TSSI calibration"};
++
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	input[wrqu->length - 1] = '\0';
++	RTW_INFO("%s: in=%s\n", __func__, input);
++
++	if (wrqu->length == 2) {
++		if(input[0] >= '0' && input[0] <= '4') {
++			pwrtrk_state = rtw_atoi(input);
++			MPT_PwrCtlDM(padapter, pwrtrk_state);
++			sprintf(extra, "PwrCtlDM start %s\n" , pwtk_type[pwrtrk_state]);
++		} else {
++			sprintf(extra, "Error unknown number ! Please check your input number\n"
++				" 0 : Thermal tracking off\n 1 : Thermal tracking on\n 2 : TSSI tracking off\n"
++				" 3 : TSSI tracking on\n 4 : TSSI calibration\n");
++		}
++		wrqu->length = strlen(extra);
++
++		return 0;
++	}
++	if (strncmp(input, "start", 5) == 0 || strncmp(input, "thertrk on", 10) == 0) {/* strncmp TRUE is 0*/
++		pwrtrk_state = 1;
++		sprintf(extra, "PwrCtlDM start %s\n" , pwtk_type[pwrtrk_state]);
++	} else if (strncmp(input, "thertrk off", 11) == 0 || strncmp(input, "stop", 5) == 0) {
++		pwrtrk_state = 0;
++		sprintf(extra, "PwrCtlDM stop %s\n" , pwtk_type[pwrtrk_state]);
++	} else if (strncmp(input, "tssitrk off", 11) == 0){
++		pwrtrk_state = 2;
++		sprintf(extra, "PwrCtlDM stop %s\n" , pwtk_type[pwrtrk_state]);
++	} else if (strncmp(input, "tssitrk on", 10) == 0){
++		pwrtrk_state = 3;
++		sprintf(extra, "PwrCtlDM start %s\n" , pwtk_type[pwrtrk_state]);
++	} else if (strncmp(input, "tssik", 5) == 0){
++		pwrtrk_state = 4;
++		sprintf(extra, "PwrCtlDM start %s\n" , pwtk_type[pwrtrk_state]);
++	} else {
++		sprintf(extra, "Error input !!!\n"
++			" thertrk off : Thermal tracking off\n thertrk on : Thermal tracking on\n"
++			" tssitrk off : TSSI tracking off\n tssitrk on : TSSI tracking on\n tssik : TSSI calibration\n\n"
++			" 0 : Thermal tracking off\n 1 : Thermal tracking on\n 2 : TSSI tracking off\n"
++			" 3 : TSSI tracking on\n 4 : TSSI calibration\n");
++		wrqu->length = strlen(extra);
++		return 0;
++	}
++
++	MPT_PwrCtlDM(padapter, pwrtrk_state);
++	wrqu->length = strlen(extra);
++
++	return 0;
++}
++
++int rtw_mp_iqk(struct net_device *dev,
++		 struct iw_request_info *info,
++		 struct iw_point *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++
++	rtw_mp_trigger_iqk(padapter);
++
++	return 0;
++}
++
++int rtw_mp_lck(struct net_device *dev,
++		 struct iw_request_info *info,
++		 struct iw_point *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++
++	rtw_mp_trigger_lck(padapter);
++
++	return 0;
++}
++
++int rtw_mp_dpk(struct net_device *dev,
++			struct iw_request_info *info,
++			union iwreq_data *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++	char *pch;
++
++	u8 ips_mode = IPS_NUM; /* init invalid value */
++	u8 lps_mode = PS_MODE_NUM; /* init invalid value */
++
++	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
++		return -EFAULT;
++
++	*(extra + wrqu->data.length) = '\0';
++	pch = extra;
++
++	if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) {
++			pDM_Odm->dpk_info.is_dpk_enable = 0;
++			halrf_dpk_enable_disable(pDM_Odm);
++			pch += sprintf(pch, "set dpk off\n");
++
++	} else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) {
++			pDM_Odm->dpk_info.is_dpk_enable = 1;
++			halrf_dpk_enable_disable(pDM_Odm);
++			pch += sprintf(pch, "set dpk on\n");
++	} else	{
++#ifdef CONFIG_LPS
++			lps_mode = pwrctrlpriv->power_mgnt;/* keep org value */
++			rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
++#endif
++#ifdef CONFIG_IPS
++			ips_mode = pwrctrlpriv->ips_mode;/* keep org value */
++			rtw_pm_set_ips(padapter, IPS_NONE);
++#endif
++			rtw_mp_trigger_dpk(padapter);
++	if (padapter->registrypriv.mp_mode == 0) {
++#ifdef CONFIG_IPS
++			rtw_pm_set_ips(padapter, ips_mode);
++#endif /* CONFIG_IPS */
++
++#ifdef CONFIG_LPS
++			rtw_pm_set_lps(padapter, lps_mode);
++#endif /* CONFIG_LPS */
++	}
++			pch += sprintf(pch, "set dpk trigger\n");
++	}
++
++	wrqu->data.length = strlen(extra);
++
++	return 0;
++}
++
++int rtw_mp_get_tsside(struct net_device *dev,
++			 struct iw_request_info *info,
++			 struct iw_point *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++ 	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
++	char input[wrqu->length + 1];
++	u8 rfpath;
++	u32 tssi_de;
++
++	if (wrqu->length > 128)
++		return -EFAULT;
++
++	_rtw_memset(input, 0, sizeof(input));
++
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	input[wrqu->length] = '\0';
++
++	if (wrqu->length == 2) {
++		rfpath = rtw_atoi(input);
++		if (rfpath >= 0 && rfpath <= 3) {
++			tssi_de = halrf_tssi_get_de(pDM_Odm, rfpath);
++			if (rfpath == 0)
++				sprintf(extra, "patha=%d", tssi_de);
++			else if (rfpath == 1)
++				sprintf(extra, "pathb=%d", tssi_de);
++			else if (rfpath == 2)
++				sprintf(extra, "pathc=%d", tssi_de);
++			else if (rfpath == 3)
++				sprintf(extra, "pathd=%d", tssi_de);
++		} else
++			sprintf(extra, "Invalid command format, please indicate RF path 0/1/2/3");
++	} else
++		sprintf(extra, "Invalid command format, please indicate RF path 0/1/2/3");
++
++	wrqu->length = strlen(extra);
++
++	return 0;
++}
++
++int rtw_mp_set_tsside(struct net_device *dev,
++		   struct iw_request_info *info,
++		   struct iw_point *wrqu, char *extra)
++{
++	u32 tsside_a = 0, tsside_b = 0, tsside_c = 0, tsside_d = 0;
++	char input[wrqu->length];
++
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
++
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	if (sscanf(input, "patha=%d", &tsside_a) == 1) {
++		sprintf(extra, "Set TSSI DE path_A: %d", tsside_a);
++		halrf_tssi_set_de_for_tx_verify(pDM_Odm, tsside_a, RF_PATH_A);
++		mpt_trigger_tssi_tracking(padapter, RF_PATH_A);
++
++	} else if (sscanf(input, "pathb=%d", &tsside_b) == 1) {
++		sprintf(extra, "Set TSSI DE path_B: %d", tsside_b);
++		halrf_tssi_set_de_for_tx_verify(pDM_Odm, tsside_b, RF_PATH_B);
++		mpt_trigger_tssi_tracking(padapter, RF_PATH_B);
++
++	} else if (sscanf(input, "pathc=%d", &tsside_c) == 1) {
++		sprintf(extra, "Set TSSI DE path_C: %d", tsside_c);
++		halrf_tssi_set_de_for_tx_verify(pDM_Odm, tsside_c, RF_PATH_C);
++		mpt_trigger_tssi_tracking(padapter, RF_PATH_C);
++
++	} else if (sscanf(input, "pathd=%d", &tsside_d) == 1) {
++		sprintf(extra, "Set TSSI DE path_D: %d", tsside_d);
++		halrf_tssi_set_de_for_tx_verify(pDM_Odm, tsside_d, RF_PATH_D);
++		mpt_trigger_tssi_tracking(padapter, RF_PATH_D);
++
++	} else
++		sprintf(extra, "Invalid command format, please input TSSI DE value within patha/b/c/d=xyz");
++
++	wrqu->length = strlen(extra);
++
++	return 0;
++}
++
++int rtw_mp_getver(struct net_device *dev,
++		  struct iw_request_info *info,
++		  union iwreq_data *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	struct mp_priv *pmp_priv;
++
++	pmp_priv = &padapter->mppriv;
++
++	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
++		return -EFAULT;
++
++	sprintf(extra, "rtwpriv=%d\n", RTWPRIV_VER_INFO);
++	wrqu->data.length = strlen(extra);
++	return 0;
++}
++
++
++int rtw_mp_mon(struct net_device *dev,
++	       struct iw_request_info *info,
++	       union iwreq_data *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct hal_ops *pHalFunc = &padapter->hal_func;
++	NDIS_802_11_NETWORK_INFRASTRUCTURE networkType;
++	int bstart = 1, bstop = 1;
++
++	networkType = Ndis802_11Infrastructure;
++	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
++		return -EFAULT;
++
++	*(extra + wrqu->data.length) = '\0';
++	rtw_pm_set_ips(padapter, IPS_NONE);
++	LeaveAllPowerSaveMode(padapter);
++
++#ifdef CONFIG_MP_INCLUDED
++	if (init_mp_priv(padapter) == _FAIL)
++		RTW_INFO("%s: initialize MP private data Fail!\n", __func__);
++	padapter->mppriv.channel = 6;
++
++	bstart = strncmp(extra, "start", 5); /* strncmp TRUE is 0*/
++	bstop = strncmp(extra, "stop", 4); /* strncmp TRUE is 0*/
++	if (bstart == 0) {
++		mp_join(padapter, WIFI_FW_ADHOC_STATE);
++		SetPacketRx(padapter, _TRUE, _FALSE);
++		SetChannel(padapter);
++		pmp_priv->rx_bindicatePkt = _TRUE;
++		pmp_priv->bRTWSmbCfg = _TRUE;
++		sprintf(extra, "monitor mode start\n");
++	} else if (bstop == 0) {
++		SetPacketRx(padapter, _FALSE, _FALSE);
++		pmp_priv->rx_bindicatePkt = _FALSE;
++		pmp_priv->bRTWSmbCfg = _FALSE;
++		padapter->registrypriv.mp_mode = 1;
++		pHalFunc->hal_deinit(padapter);
++		padapter->registrypriv.mp_mode = 0;
++		pHalFunc->hal_init(padapter);
++		/*rtw_disassoc_cmd(padapter, 0, 0);*/
++		if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++			rtw_disassoc_cmd(padapter, 500, 0);
++			rtw_indicate_disconnect(padapter, 0, _FALSE);
++			/*rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);*/
++		}
++		rtw_pm_set_ips(padapter, IPS_NORMAL);
++		sprintf(extra, "monitor mode Stop\n");
++	}
++#endif
++	wrqu->data.length = strlen(extra);
++	return 0;
++}
++
++int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra)
++{
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++	char *pextra = extra;
++
++	switch (pmp_priv->mode) {
++
++	case MP_PACKET_TX:
++		if (bStartTest == 0) {
++			pmp_priv->tx.stop = 1;
++			pmp_priv->mode = MP_ON;
++			#ifdef CONFIG_RTL8822B
++			rtw_write8(padapter, 0x838, 0x61);
++			#endif
++			sprintf(extra, "Stop continuous Tx");
++		} else if (pmp_priv->tx.stop == 1) {
++			pextra = extra + strlen(extra);
++			pextra += sprintf(pextra, "\nStart continuous DA=ffffffffffff len=1500 count=%u\n", pmp_priv->tx.count);
++			pmp_priv->tx.stop = 0;
++			#ifdef CONFIG_RTL8822B
++			rtw_write8(padapter, 0x838, 0x6d);
++			#endif
++			SetPacketTx(padapter);
++		} else
++			return -EFAULT;
++		return 0;
++	case MP_SINGLE_TONE_TX:
++		if (bStartTest != 0)
++			strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.");
++		SetSingleToneTx(padapter, (u8)bStartTest);
++		break;
++	case MP_CONTINUOUS_TX:
++		if (bStartTest != 0)
++			strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.");
++		SetContinuousTx(padapter, (u8)bStartTest);
++		break;
++	case MP_CARRIER_SUPPRISSION_TX:
++		if (bStartTest != 0) {
++			if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_11M)
++				strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.");
++			else
++				strcat(extra, "\nSpecify carrier suppression but not CCK rate");
++		}
++		SetCarrierSuppressionTx(padapter, (u8)bStartTest);
++		break;
++	case MP_SINGLE_CARRIER_TX:
++		if (bStartTest != 0)
++			strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.");
++		SetSingleCarrierTx(padapter, (u8)bStartTest);
++		break;
++
++	default:
++		sprintf(extra, "Error! Continuous-Tx is not on-going.");
++		return -EFAULT;
++	}
++
++	if (bStartTest == 1 && pmp_priv->mode != MP_ON) {
++		struct mp_priv *pmp_priv = &padapter->mppriv;
++
++		if (pmp_priv->tx.stop == 0) {
++			pmp_priv->tx.stop = 1;
++			rtw_msleep_os(5);
++		}
++#ifdef CONFIG_80211N_HT
++		if(padapter->registrypriv.ht_enable &&
++			is_supported_ht(padapter->registrypriv.wireless_mode))
++			pmp_priv->tx.attrib.ht_en = 1;
++#endif
++		pmp_priv->tx.stop = 0;
++		pmp_priv->tx.count = 1;
++		SetPacketTx(padapter);
++	} else
++		pmp_priv->mode = MP_ON;
++
++#if defined(CONFIG_RTL8812A)
++	if (IS_HARDWARE_TYPE_8812AU(padapter)) {
++		/* <20130425, Kordan> Turn off OFDM Rx to prevent from CCA causing Tx hang.*/
++		if (pmp_priv->mode == MP_PACKET_TX)
++			phy_set_bb_reg(padapter, rCCAonSec_Jaguar, BIT3, 1);
++		else
++			phy_set_bb_reg(padapter, rCCAonSec_Jaguar, BIT3, 0);
++	}
++#endif
++
++	return 0;
++}
++
++
++int rtw_mp_tx(struct net_device *dev,
++	      struct iw_request_info *info,
++	      union iwreq_data *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++	PMPT_CONTEXT		pMptCtx = &(padapter->mppriv.mpt_ctx);
++	char *pextra = extra;
++	u32 bandwidth = 0, sg = 0, channel = 6, txpower = 40, rate = 108, ant = 0, txmode = 1, count = 0;
++	u8 bStartTest = 1, status = 0;
++#ifdef CONFIG_MP_VHT_HW_TX_MODE
++	u8 Idx = 0, tmpU1B;
++#endif
++	u16 antenna = 0;
++
++	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
++		return -EFAULT;
++	RTW_INFO("extra = %s\n", extra);
++#ifdef CONFIG_CONCURRENT_MODE
++	if (!is_primary_adapter(padapter)) {
++		sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n");
++		wrqu->data.length = strlen(extra);
++		return 0;
++	}
++#endif
++
++	if (strncmp(extra, "stop", 3) == 0) {
++		bStartTest = 0; /* To set Stop*/
++		pmp_priv->tx.stop = 1;
++		sprintf(extra, "Stop continuous Tx");
++		status = rtw_mp_pretx_proc(padapter, bStartTest, extra);
++		wrqu->data.length = strlen(extra);
++		return status;
++	} else if (strncmp(extra, "count", 5) == 0) {
++		if (sscanf(extra, "count=%d", &count) < 1)
++			RTW_INFO("Got Count=%d]\n", count);
++		pmp_priv->tx.count = count;
++		return 0;
++	} else if (strncmp(extra, "setting", 7) == 0) {
++		_rtw_memset(extra, 0, wrqu->data.length);
++		pextra += sprintf(pextra, "Current Setting :\n Channel:%d", pmp_priv->channel);
++		pextra += sprintf(pextra, "\n Bandwidth:%d", pmp_priv->bandwidth);
++		pextra += sprintf(pextra, "\n Rate index:%d", pmp_priv->rateidx);
++		pextra += sprintf(pextra, "\n TxPower index:%d", pmp_priv->txpoweridx);
++		pextra += sprintf(pextra, "\n Antenna TxPath:%d", pmp_priv->antenna_tx);
++		pextra += sprintf(pextra, "\n Antenna RxPath:%d", pmp_priv->antenna_rx);
++		pextra += sprintf(pextra, "\n MP Mode:%d", pmp_priv->mode);
++		wrqu->data.length = strlen(extra);
++		return 0;
++#ifdef CONFIG_MP_VHT_HW_TX_MODE
++	} else if (strncmp(extra, "pmact", 5) == 0) {
++		if (strncmp(extra, "pmact=", 6) == 0) {
++			_rtw_memset(&pMptCtx->PMacTxInfo, 0, sizeof(pMptCtx->PMacTxInfo));
++			if (strncmp(extra, "pmact=start", 11) == 0) {
++				pMptCtx->PMacTxInfo.bEnPMacTx = _TRUE;
++				sprintf(extra, "Set PMac Tx Mode start\n");
++			} else {
++				pMptCtx->PMacTxInfo.bEnPMacTx = _FALSE;
++				sprintf(extra, "Set PMac Tx Mode Stop\n");
++			}
++			if (pMptCtx->bldpc == TRUE)
++				pMptCtx->PMacTxInfo.bLDPC = _TRUE;
++
++			if (pMptCtx->bstbc == TRUE)
++				pMptCtx->PMacTxInfo.bSTBC = _TRUE;
++
++			pMptCtx->PMacTxInfo.bSPreamble = pmp_priv->preamble;
++			pMptCtx->PMacTxInfo.bSGI = pmp_priv->preamble;
++			pMptCtx->PMacTxInfo.BandWidth = pmp_priv->bandwidth;
++			pMptCtx->PMacTxInfo.TX_RATE = HwRateToMPTRate(pmp_priv->rateidx);
++
++			pMptCtx->PMacTxInfo.Mode = pMptCtx->HWTxmode;
++
++			pMptCtx->PMacTxInfo.NDP_sound = FALSE;/*(Adapter.PacketType == NDP_PKT)?TRUE:FALSE;*/
++
++			if (padapter->mppriv.pktInterval == 0)
++				pMptCtx->PMacTxInfo.PacketPeriod = 100;
++			else
++				pMptCtx->PMacTxInfo.PacketPeriod = padapter->mppriv.pktInterval;
++
++			if (padapter->mppriv.pktLength < 1000)
++				pMptCtx->PMacTxInfo.PacketLength = 1000;
++			else
++				pMptCtx->PMacTxInfo.PacketLength = padapter->mppriv.pktLength;
++
++			pMptCtx->PMacTxInfo.PacketPattern  = rtw_random32() % 0xFF;
++
++			if (padapter->mppriv.tx_pktcount != 0)
++				pMptCtx->PMacTxInfo.PacketCount = padapter->mppriv.tx_pktcount;
++
++			pMptCtx->PMacTxInfo.Ntx = 0;
++			for (Idx = 16; Idx < 20; Idx++) {
++				tmpU1B = (padapter->mppriv.antenna_tx >> Idx) & 1;
++				if (tmpU1B)
++					pMptCtx->PMacTxInfo.Ntx++;
++			}
++
++			_rtw_memset(pMptCtx->PMacTxInfo.MacAddress, 0xFF, ETH_ALEN);
++
++			PMAC_Get_Pkt_Param(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
++
++			if (MPT_IS_CCK_RATE(pMptCtx->PMacTxInfo.TX_RATE))
++
++				CCK_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
++			else {
++				PMAC_Nsym_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
++				/* 24 BIT*/
++				L_SIG_generator(pMptCtx->PMacPktInfo.N_sym, &pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
++			}
++			/*	48BIT*/
++			if (MPT_IS_HT_RATE(pMptCtx->PMacTxInfo.TX_RATE))
++				HT_SIG_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
++			else if (MPT_IS_VHT_RATE(pMptCtx->PMacTxInfo.TX_RATE)) {
++				/*	48BIT*/
++				VHT_SIG_A_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
++
++				/*	26/27/29 BIT  & CRC 8 BIT*/
++				VHT_SIG_B_generator(&pMptCtx->PMacTxInfo);
++
++				/* 32 BIT*/
++				VHT_Delimiter_generator(&pMptCtx->PMacTxInfo);
++			}
++
++			mpt_ProSetPMacTx(padapter);
++
++		} else if (strncmp(extra, "pmact,mode=", 11) == 0) {
++			int txmode = 0;
++
++			if (sscanf(extra, "pmact,mode=%d", &txmode) > 0) {
++				if (txmode == 1) {
++					pMptCtx->HWTxmode = CONTINUOUS_TX;
++					sprintf(extra, "\t Config HW Tx mode = CONTINUOUS_TX\n");
++				} else if (txmode == 2) {
++					pMptCtx->HWTxmode = OFDM_Single_Tone_TX;
++					sprintf(extra, "\t Config HW Tx mode = OFDM_Single_Tone_TX\n");
++				} else {
++					pMptCtx->HWTxmode = PACKETS_TX;
++					sprintf(extra, "\t Config HW Tx mode = PACKETS_TX\n");
++				}
++			} else {
++				pMptCtx->HWTxmode = PACKETS_TX;
++				sprintf(extra, "\t Config HW Tx mode=\n 0 = PACKETS_TX\n 1 = CONTINUOUS_TX\n 2 = OFDM_Single_Tone_TX");
++			}
++		} else if (strncmp(extra, "pmact,", 6) == 0) {
++			int PacketPeriod = 0, PacketLength = 0, PacketCout = 0;
++			int bldpc = 0, bstbc = 0;
++
++			if (sscanf(extra, "pmact,period=%d", &PacketPeriod) > 0) {
++				padapter->mppriv.pktInterval = PacketPeriod;
++				RTW_INFO("PacketPeriod=%d\n", padapter->mppriv.pktInterval);
++				sprintf(extra, "PacketPeriod [1~255]= %d\n", padapter->mppriv.pktInterval);
++
++			} else if (sscanf(extra, "pmact,length=%d", &PacketLength) > 0) {
++				padapter->mppriv.pktLength = PacketLength;
++				RTW_INFO("PacketPeriod=%d\n", padapter->mppriv.pktLength);
++				sprintf(extra, "PacketLength[~65535]=%d\n", padapter->mppriv.pktLength);
++
++			} else if (sscanf(extra, "pmact,count=%d", &PacketCout) > 0) {
++				padapter->mppriv.tx_pktcount = PacketCout;
++				RTW_INFO("Packet Cout =%d\n", padapter->mppriv.tx_pktcount);
++				sprintf(extra, "Packet Cout =%d\n", padapter->mppriv.tx_pktcount);
++
++			} else if (sscanf(extra, "pmact,ldpc=%d", &bldpc) > 0) {
++				pMptCtx->bldpc = bldpc;
++				RTW_INFO("Set LDPC =%d\n", pMptCtx->bldpc);
++				sprintf(extra, "Set LDPC =%d\n", pMptCtx->bldpc);
++
++			} else if (sscanf(extra, "pmact,stbc=%d", &bstbc) > 0) {
++				pMptCtx->bstbc = bstbc;
++				RTW_INFO("Set STBC =%d\n", pMptCtx->bstbc);
++				sprintf(extra, "Set STBC =%d\n", pMptCtx->bstbc);
++			} else
++				sprintf(extra, "\n period={1~255}\n length={1000~65535}\n count={0~}\n ldpc={0/1}\n stbc={0/1}");
++
++		}
++
++		wrqu->data.length = strlen(extra);
++		return 0;
++#endif
++	} else {
++
++		if (sscanf(extra, "ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d", &channel, &bandwidth, &rate, &txpower, &ant, &txmode) < 6) {
++			RTW_INFO("Invalid format [ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d]\n", channel, bandwidth, rate, txpower, ant, txmode);
++			_rtw_memset(extra, 0, wrqu->data.length);
++			pextra += sprintf(pextra, "\n Please input correct format as bleow:\n");
++			pextra += sprintf(pextra, "\t ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d\n", channel, bandwidth, rate, txpower, ant, txmode);
++			pextra += sprintf(pextra, "\n [ ch : BGN = <1~14> , A or AC = <36~165> ]");
++			pextra += sprintf(pextra, "\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]");
++			pextra += sprintf(pextra, "\n [ rate :	CCK: 1 2 5.5 11M X 2 = < 2 4 11 22 >]");
++			pextra += sprintf(pextra, "\n [		OFDM: 6 9 12 18 24 36 48 54M X 2 = < 12 18 24 36 48 72 96 108>");
++			pextra += sprintf(pextra, "\n [		HT 1S2SS MCS0 ~ MCS15 : < [MCS0]=128 ~ [MCS7]=135 ~ [MCS15]=143 >");
++			pextra += sprintf(pextra, "\n [		HT 3SS MCS16 ~ MCS32 : < [MCS16]=144 ~ [MCS23]=151 ~ [MCS32]=159 >");
++			pextra += sprintf(pextra, "\n [		VHT 1SS MCS0 ~ MCS9 : < [MCS0]=160 ~ [MCS9]=169 >");
++			pextra += sprintf(pextra, "\n [ txpower : 1~63 power index");
++			pextra += sprintf(pextra, "\n [ ant : <A = 1, B = 2, C = 4, D = 8> ,2T ex: AB=3 BC=6 CD=12");
++			pextra += sprintf(pextra, "\n [ txmode : < 0 = CONTINUOUS_TX, 1 = PACKET_TX, 2 = SINGLE_TONE_TX, 3 = CARRIER_SUPPRISSION_TX, 4 = SINGLE_CARRIER_TX>\n");
++			wrqu->data.length = strlen(extra);
++			return status;
++
++		} else {
++			char *pextra = extra;
++			RTW_INFO("Got format [ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d]\n", channel, bandwidth, rate, txpower, ant, txmode);
++			_rtw_memset(extra, 0, wrqu->data.length);
++			sprintf(extra, "Change Current channel %d to channel %d", padapter->mppriv.channel , channel);
++			padapter->mppriv.channel = channel;
++			SetChannel(padapter);
++			pHalData->current_channel = channel;
++
++			if (bandwidth == 1)
++				bandwidth = CHANNEL_WIDTH_40;
++			else if (bandwidth == 2)
++				bandwidth = CHANNEL_WIDTH_80;
++			pextra = extra + strlen(pextra);
++			pextra += sprintf(pextra, "\nChange Current Bandwidth %d to Bandwidth %d", padapter->mppriv.bandwidth, bandwidth);
++			padapter->mppriv.bandwidth = (u8)bandwidth;
++			padapter->mppriv.preamble = sg;
++			SetBandwidth(padapter);
++			pHalData->current_channel_bw = bandwidth;
++
++			pextra += sprintf(pextra, "\nSet power level :%d", txpower);
++			padapter->mppriv.txpoweridx = (u8)txpower;
++			pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)txpower;
++			pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)txpower;
++			pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)txpower;
++			pMptCtx->TxPwrLevel[RF_PATH_D]  = (u8)txpower;
++			SetTxPower(padapter);
++
++			RTW_INFO("%s: bw=%d sg=%d\n", __func__, bandwidth, sg);
++
++			if (rate <= 0x7f)
++				rate = wifirate2_ratetbl_inx((u8)rate);
++			else if (rate < 0xC8)
++				rate = (rate - 0x80 + MPT_RATE_MCS0);
++			/*HT  rate 0x80(MCS0)  ~ 0x8F(MCS15) ~ 0x9F(MCS31) 128~159
++			VHT1SS~2SS rate 0xA0 (VHT1SS_MCS0 44) ~ 0xB3 (VHT2SS_MCS9 #63) 160~179
++			VHT rate 0xB4 (VHT3SS_MCS0 64) ~ 0xC7 (VHT2SS_MCS9 #83) 180~199
++			else
++			VHT rate 0x90(VHT1SS_MCS0) ~ 0x99(VHT1SS_MCS9) 144~153
++			rate =(rate - MPT_RATE_VHT1SS_MCS0);
++			*/
++			RTW_INFO("%s: rate index=%d\n", __func__, rate);
++			if (rate >= MPT_RATE_LAST)
++				return -EINVAL;
++			pextra += sprintf(pextra, "\nSet data rate to %d index %d", padapter->mppriv.rateidx, rate);
++
++			padapter->mppriv.rateidx = rate;
++			pMptCtx->mpt_rate_index = rate;
++			SetDataRate(padapter);
++
++			pextra += sprintf(pextra, "\nSet Antenna Path :%d", ant);
++			switch (ant) {
++			case 1:
++				antenna = ANTENNA_A;
++				break;
++			case 2:
++				antenna = ANTENNA_B;
++				break;
++			case 4:
++				antenna = ANTENNA_C;
++				break;
++			case 8:
++				antenna = ANTENNA_D;
++				break;
++			case 3:
++				antenna = ANTENNA_AB;
++				break;
++			case 5:
++				antenna = ANTENNA_AC;
++				break;
++			case 9:
++				antenna = ANTENNA_AD;
++				break;
++			case 6:
++				antenna = ANTENNA_BC;
++				break;
++			case 10:
++				antenna = ANTENNA_BD;
++				break;
++			case 12:
++				antenna = ANTENNA_CD;
++				break;
++			case 7:
++				antenna = ANTENNA_ABC;
++				break;
++			case 14:
++				antenna = ANTENNA_BCD;
++				break;
++			case 11:
++				antenna = ANTENNA_ABD;
++				break;
++			case 15:
++				antenna = ANTENNA_ABCD;
++				break;
++			}
++			RTW_INFO("%s: antenna=0x%x\n", __func__, antenna);
++			padapter->mppriv.antenna_tx = antenna;
++			padapter->mppriv.antenna_rx = antenna;
++			pHalData->antenna_tx_path = antenna;
++			SetAntenna(padapter);
++
++			if (txmode == 0)
++				pmp_priv->mode = MP_CONTINUOUS_TX;
++			else if (txmode == 1) {
++				pmp_priv->mode = MP_PACKET_TX;
++				pmp_priv->tx.count = count;
++			} else if (txmode == 2)
++				pmp_priv->mode = MP_SINGLE_TONE_TX;
++			else if (txmode == 3)
++				pmp_priv->mode = MP_CARRIER_SUPPRISSION_TX;
++			else if (txmode == 4)
++				pmp_priv->mode = MP_SINGLE_CARRIER_TX;
++
++			status = rtw_mp_pretx_proc(padapter, bStartTest, extra);
++		}
++
++	}
++
++	wrqu->data.length = strlen(extra);
++	return status;
++}
++
++
++int rtw_mp_rx(struct net_device *dev,
++	      struct iw_request_info *info,
++	      union iwreq_data *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++	char *pextra = extra;
++	u32 bandwidth = 0, sg = 0, channel = 6, ant = 0;
++	u16 antenna = 0;
++	u8 bStartRx = 0;
++
++	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
++		return -EFAULT;
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (!is_primary_adapter(padapter)) {
++		sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n");
++		wrqu->data.length = strlen(extra);
++		return 0;
++	}
++#endif
++
++	if (strncmp(extra, "stop", 4) == 0) {
++		_rtw_memset(extra, 0, wrqu->data.length);
++		SetPacketRx(padapter, bStartRx, _FALSE);
++		pmp_priv->bmac_filter = _FALSE;
++		sprintf(extra, "Received packet OK:%d CRC error:%d ,Filter out:%d", padapter->mppriv.rx_pktcount, padapter->mppriv.rx_crcerrpktcount, padapter->mppriv.rx_pktcount_filter_out);
++		wrqu->data.length = strlen(extra);
++		return 0;
++
++	} else if (sscanf(extra, "ch=%d,bw=%d,ant=%d", &channel, &bandwidth, &ant) < 3) {
++		RTW_INFO("Invalid format [ch=%d,bw=%d,ant=%d]\n", channel, bandwidth, ant);
++		_rtw_memset(extra, 0, wrqu->data.length);
++		pextra += sprintf(pextra, "\n Please input correct format as bleow:\n");
++		pextra += sprintf(pextra, "\t ch=%d,bw=%d,ant=%d\n", channel, bandwidth, ant);
++		pextra += sprintf(pextra, "\n [ ch : BGN = <1~14> , A or AC = <36~165> ]");
++		pextra += sprintf(pextra, "\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]");
++		pextra += sprintf(pextra, "\n [ ant : <A = 1, B = 2, C = 4, D = 8> ,2T ex: AB=3 BC=6 CD=12");
++		wrqu->data.length = strlen(extra);
++		return 0;
++
++	} else {
++		char *pextra = extra;
++		bStartRx = 1;
++		RTW_INFO("Got format [ch=%d,bw=%d,ant=%d]\n", channel, bandwidth, ant);
++		_rtw_memset(extra, 0, wrqu->data.length);
++		sprintf(extra, "Change Current channel %d to channel %d", padapter->mppriv.channel , channel);
++		padapter->mppriv.channel = channel;
++		SetChannel(padapter);
++		pHalData->current_channel = channel;
++
++		if (bandwidth == 1)
++			bandwidth = CHANNEL_WIDTH_40;
++		else if (bandwidth == 2)
++			bandwidth = CHANNEL_WIDTH_80;
++		pextra = extra + strlen(extra);
++		pextra += sprintf(pextra, "\nChange Current Bandwidth %d to Bandwidth %d", padapter->mppriv.bandwidth, bandwidth);
++		padapter->mppriv.bandwidth = (u8)bandwidth;
++		padapter->mppriv.preamble = sg;
++		SetBandwidth(padapter);
++		pHalData->current_channel_bw = bandwidth;
++
++		pextra += sprintf(pextra, "\nSet Antenna Path :%d", ant);
++		switch (ant) {
++		case 1:
++			antenna = ANTENNA_A;
++			break;
++		case 2:
++			antenna = ANTENNA_B;
++			break;
++		case 4:
++			antenna = ANTENNA_C;
++			break;
++		case 8:
++			antenna = ANTENNA_D;
++			break;
++		case 3:
++			antenna = ANTENNA_AB;
++			break;
++		case 5:
++			antenna = ANTENNA_AC;
++			break;
++		case 9:
++			antenna = ANTENNA_AD;
++			break;
++		case 6:
++			antenna = ANTENNA_BC;
++			break;
++		case 10:
++			antenna = ANTENNA_BD;
++			break;
++		case 12:
++			antenna = ANTENNA_CD;
++			break;
++		case 7:
++			antenna = ANTENNA_ABC;
++			break;
++		case 14:
++			antenna = ANTENNA_BCD;
++			break;
++		case 11:
++			antenna = ANTENNA_ABD;
++			break;
++		case 15:
++			antenna = ANTENNA_ABCD;
++			break;
++		}
++		RTW_INFO("%s: antenna=0x%x\n", __func__, antenna);
++		padapter->mppriv.antenna_tx = antenna;
++		padapter->mppriv.antenna_rx = antenna;
++		pHalData->antenna_tx_path = antenna;
++		SetAntenna(padapter);
++
++		strcat(extra, "\nstart Rx");
++		SetPacketRx(padapter, bStartRx, _FALSE);
++	}
++	wrqu->data.length = strlen(extra);
++	return 0;
++}
++
++
++int rtw_mp_hwtx(struct net_device *dev,
++		struct iw_request_info *info,
++		union iwreq_data *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++	PMPT_CONTEXT		pMptCtx = &(padapter->mppriv.mpt_ctx);
++	char *pch;
++
++#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
++	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
++		return -EFAULT;
++	*(extra + wrqu->data.length) = '\0';
++
++	_rtw_memset(&pMptCtx->PMacTxInfo, 0, sizeof(RT_PMAC_TX_INFO));
++	_rtw_memcpy((void *)&pMptCtx->PMacTxInfo, (void *)extra, sizeof(RT_PMAC_TX_INFO));
++	_rtw_memset(extra, 0, wrqu->data.length);
++	pch = extra;
++
++	if (pMptCtx->PMacTxInfo.bEnPMacTx == 1 && pmp_priv->mode != MP_ON) {
++		pch += sprintf(pch, "MP Tx Running, Please Set PMac Tx Mode Stop\n");
++		RTW_INFO("Error !!! MP Tx Running, Please Set PMac Tx Mode Stop\n");
++	} else {
++		RTW_INFO("To set MAC Tx mode\n");
++		if (mpt_ProSetPMacTx(padapter))
++			pch += sprintf(pch, "Set PMac Tx Mode OK\n");
++		else
++			pch += sprintf(pch, "Set PMac Tx Mode Error\n");
++	}
++	wrqu->data.length = strlen(extra);
++#endif
++	return 0;
++
++}
++
++int rtw_mp_pwrlmt(struct net_device *dev,
++			struct iw_request_info *info,
++			union iwreq_data *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	struct registry_priv  *registry_par = &padapter->registrypriv;
++	char *pch;
++
++	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
++		return -EFAULT;
++
++	*(extra + wrqu->data.length) = '\0';
++	pch = extra;
++
++#if CONFIG_TXPWR_LIMIT
++	if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) {
++		padapter->registrypriv.RegEnableTxPowerLimit = 0;
++		pch += sprintf(pch, "Turn off Power Limit\n");
++
++	} else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) {
++		padapter->registrypriv.RegEnableTxPowerLimit = 1;
++		pch += sprintf(pch, "Turn on Power Limit\n");
++
++	} else
++#endif
++		pch += sprintf(pch, "Get Power Limit Status:%s\n", (registry_par->RegEnableTxPowerLimit == 1) ? "ON" : "OFF");
++
++
++	wrqu->data.length = strlen(extra);
++	return 0;
++}
++
++int rtw_mp_pwrbyrate(struct net_device *dev,
++			struct iw_request_info *info,
++			union iwreq_data *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++
++	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
++		return -EFAULT;
++
++	*(extra + wrqu->data.length) = '\0';
++	if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) {
++		padapter->registrypriv.RegEnableTxPowerByRate = 0;
++		sprintf(extra, "Turn off Tx Power by Rate\n");
++
++	} else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) {
++		padapter->registrypriv.RegEnableTxPowerByRate = 1;
++		sprintf(extra, "Turn On Tx Power by Rate\n");
++
++	} else {
++		sprintf(extra, "Get Power by Rate Status:%s\n", (padapter->registrypriv.RegEnableTxPowerByRate == 1) ? "ON" : "OFF");
++	}
++
++	wrqu->data.length = strlen(extra);
++	return 0;
++}
++
++
++int rtw_mp_dpk_track(struct net_device *dev,
++			struct iw_request_info *info,
++			union iwreq_data *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
++	char *pch;
++
++	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
++		return -EFAULT;
++
++	*(extra + wrqu->data.length) = '\0';
++	pch = extra;
++
++	if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) {
++		halrf_set_dpk_track(pDM_Odm, FALSE);
++		pch += sprintf(pch, "set dpk track off\n");
++
++	} else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) {
++		halrf_set_dpk_track(pDM_Odm, TRUE);
++		pch += sprintf(pch, "set dpk track on\n");
++	}
++
++	wrqu->data.length = strlen(extra);
++	return 0;
++}
++
++
++int rtw_bt_efuse_mask_file(struct net_device *dev,
++			struct iw_request_info *info,
++			union iwreq_data *wrqu, char *extra)
++{
++	char *rtw_efuse_mask_file_path;
++	u8	*pch;
++	char	*ptmp, tmp;
++	u8 Status;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++
++	_rtw_memset(btmaskfileBuffer, 0x00, sizeof(btmaskfileBuffer));
++
++	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
++		return -EFAULT;
++
++	*(extra + wrqu->data.length) = '\0';
++	ptmp = extra;
++
++	if (strncmp(extra, "data,", 5) == 0) {
++		u8	count = 0;
++		u8	i = 0;
++
++		pch = strsep(&ptmp, ",");
++
++		if ((pch == NULL) || (strlen(pch) == 0)) {
++			RTW_INFO("%s: parameter error(no cmd)!\n", __func__);
++			return -EFAULT;
++		}
++
++		do {
++			pch = strsep(&ptmp, ":");
++			if ((pch == NULL) || (strlen(pch) == 0))
++				break;
++			if (strlen(pch) != 2
++				|| IsHexDigit(*pch) == _FALSE
++				|| IsHexDigit(*(pch + 1)) == _FALSE
++				|| sscanf(pch, "%hhx", &tmp) != 1
++			) {
++				RTW_INFO("%s: invalid 8-bit hex! input format: data,01:23:45:67:89:ab:cd:ef...\n", __func__);
++				return -EFAULT;
++			}
++			btmaskfileBuffer[count++] = tmp;
++
++		 } while (count < 64);
++
++		_rtw_memset(extra, '\0' , strlen(extra));
++
++		for (i = 0; i < count; i++)
++			ptmp += sprintf(ptmp, "%02x:", btmaskfileBuffer[i]);
++
++		padapter->registrypriv.bBTFileMaskEfuse = _TRUE;
++
++		ptmp += sprintf(ptmp, "\nLoad BT Efuse Mask data %d hex ok\n", count);
++		wrqu->data.length = strlen(extra);
++		return 0;
++	}
++	rtw_efuse_mask_file_path = extra;
++
++	if (rtw_is_file_readable(rtw_efuse_mask_file_path) == _TRUE) {
++		RTW_INFO("%s do rtw_is_file_readable = %s! ,sizeof BT maskfileBuffer %zu\n", __func__, rtw_efuse_mask_file_path, sizeof(btmaskfileBuffer));
++		Status = rtw_efuse_file_read(padapter, rtw_efuse_mask_file_path, btmaskfileBuffer, sizeof(btmaskfileBuffer));
++		_rtw_memset(extra, '\0' , strlen(extra));
++		if (Status == _TRUE) {
++			padapter->registrypriv.bBTFileMaskEfuse = _TRUE;
++			ptmp += sprintf(ptmp, "BT efuse mask file read OK\n");
++		} else {
++			padapter->registrypriv.bBTFileMaskEfuse = _FALSE;
++			ptmp += sprintf(ptmp, "read BT efuse mask file FAIL\n");
++			RTW_INFO("%s rtw_efuse_file_read BT mask fail!\n", __func__);
++		}
++	} else {
++		padapter->registrypriv.bBTFileMaskEfuse = _FALSE;
++		ptmp += sprintf(ptmp, "BT efuse mask file readable FAIL\n");
++		RTW_INFO("%s rtw_is_file_readable BT Mask file fail!\n", __func__);
++	}
++	wrqu->data.length = strlen(extra);
++	return 0;
++}
++
++
++int rtw_efuse_mask_file(struct net_device *dev,
++			struct iw_request_info *info,
++			union iwreq_data *wrqu, char *extra)
++{
++	char *rtw_efuse_mask_file_path;
++	u8 Status;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++
++	_rtw_memset(maskfileBuffer, 0x00, sizeof(maskfileBuffer));
++
++	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
++		return -EFAULT;
++
++	*(extra + wrqu->data.length) = '\0';
++	if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) {
++		padapter->registrypriv.boffefusemask = 1;
++		sprintf(extra, "Turn off Efuse Mask\n");
++		wrqu->data.length = strlen(extra);
++		return 0;
++	}
++	if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) {
++		padapter->registrypriv.boffefusemask = 0;
++		sprintf(extra, "Turn on Efuse Mask\n");
++		wrqu->data.length = strlen(extra);
++		return 0;
++	}
++	if (strncmp(extra, "data,", 5) == 0) {
++		u8	*pch;
++		char	*ptmp, tmp;
++		u8	count = 0;
++		u8	i = 0;
++
++		ptmp = extra;
++		pch = strsep(&ptmp, ",");
++
++		if ((pch == NULL) || (strlen(pch) == 0)) {
++			RTW_INFO("%s: parameter error(no cmd)!\n", __func__);
++			return -EFAULT;
++		}
++
++		do {
++			pch = strsep(&ptmp, ":");
++			if ((pch == NULL) || (strlen(pch) == 0))
++				break;
++			if (strlen(pch) != 2
++				|| IsHexDigit(*pch) == _FALSE
++				|| IsHexDigit(*(pch + 1)) == _FALSE
++				|| sscanf(pch, "%hhx", &tmp) != 1
++			) {
++				RTW_INFO("%s: invalid 8-bit hex! input format: data,01:23:45:67:89:ab:cd:ef...\n", __func__);
++				return -EFAULT;
++			}
++			maskfileBuffer[count++] = tmp;
++
++		} while (count < 64);
++
++		_rtw_memset(extra, '\0' , strlen(extra));
++
++		for (i = 0; i < count; i++)
++			ptmp += sprintf(ptmp, "%02x:", maskfileBuffer[i]);
++
++		padapter->registrypriv.bFileMaskEfuse = _TRUE;
++
++		sprintf(ptmp, "\nLoad Efuse Mask data %d hex ok\n", count);
++		wrqu->data.length = strlen(extra);
++		return 0;
++	}
++	rtw_efuse_mask_file_path = extra;
++
++	if (rtw_is_file_readable(rtw_efuse_mask_file_path) == _TRUE) {
++		RTW_INFO("%s do rtw_efuse_mask_file_read = %s! ,sizeof maskfileBuffer %zu\n", __func__, rtw_efuse_mask_file_path, sizeof(maskfileBuffer));
++		Status = rtw_efuse_file_read(padapter, rtw_efuse_mask_file_path, maskfileBuffer, sizeof(maskfileBuffer));
++		if (Status == _TRUE) {
++			padapter->registrypriv.bFileMaskEfuse = _TRUE;
++			sprintf(extra, "efuse mask file read OK\n");
++		} else {
++			padapter->registrypriv.bFileMaskEfuse = _FALSE;
++			sprintf(extra, "read efuse mask file FAIL\n");
++			RTW_INFO("%s rtw_efuse_file_read mask fail!\n", __func__);
++		}
++	} else {
++		padapter->registrypriv.bFileMaskEfuse = _FALSE;
++		sprintf(extra, "efuse mask file readable FAIL\n");
++		RTW_INFO("%s rtw_is_file_readable fail!\n", __func__);
++	}
++	wrqu->data.length = strlen(extra);
++	return 0;
++}
++
++
++int rtw_efuse_file_map(struct net_device *dev,
++		       struct iw_request_info *info,
++		       union iwreq_data *wrqu, char *extra)
++{
++	char *rtw_efuse_file_map_path;
++	u8 Status;
++	PEFUSE_HAL pEfuseHal;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++
++	pEfuseHal = &pHalData->EfuseHal;
++	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
++		return -EFAULT;
++
++	rtw_efuse_file_map_path = extra;
++
++	_rtw_memset(pEfuseHal->fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);
++
++	if (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) {
++		RTW_INFO("%s do rtw_efuse_mask_file_read = %s!\n", __func__, rtw_efuse_file_map_path);
++		Status = rtw_efuse_file_read(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeEfuseModifiedMap, sizeof(pEfuseHal->fakeEfuseModifiedMap));
++		if (Status == _TRUE) {
++			pmp_priv->bloadefusemap = _TRUE;
++			sprintf(extra, "efuse file file_read OK\n");
++		} else {
++			pmp_priv->bloadefusemap = _FALSE;
++			sprintf(extra, "efuse file file_read FAIL\n");
++		}
++	} else {
++		sprintf(extra, "efuse file readable FAIL\n");
++		RTW_INFO("%s rtw_is_file_readable fail!\n", __func__);
++	}
++	wrqu->data.length = strlen(extra);
++	return 0;
++}
++
++
++int rtw_efuse_file_map_store(struct net_device *dev,
++				struct iw_request_info *info,
++				union iwreq_data *wrqu, char *extra)
++{
++	char *rtw_efuse_file_map_path;
++	u8 Status;
++	u16 mapLen;
++	PEFUSE_HAL pEfuseHal;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++
++	pEfuseHal = &pHalData->EfuseHal;
++	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
++		return -EFAULT;
++
++	rtw_efuse_file_map_path = extra;
++	RTW_INFO("%s rtw_is_file_readable! %s\n", __func__, rtw_efuse_file_map_path);
++
++	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapLen, _FALSE);
++
++	if (mapLen != 0) {
++		RTW_INFO("%s, efuse store path = %s! mapLen = %d\n", __func__, rtw_efuse_file_map_path, mapLen);
++		Status = rtw_efuse_file_store(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeEfuseModifiedMap, mapLen);
++		if (Status) {
++			sprintf(extra, "efuse file restore OK\n");
++		} else {
++			sprintf(extra, "efuse file restore FAIL\n");
++		}
++	} else {
++		sprintf(extra, "efuse file readable FAIL\n");
++		RTW_INFO("%s rtw_is_file_readable fail! map Len %d\n", __func__, mapLen);
++	}
++
++	wrqu->data.length = strlen(extra);
++	return 0;
++}
++
++int rtw_bt_efuse_file_map(struct net_device *dev,
++				struct iw_request_info *info,
++				union iwreq_data *wrqu, char *extra)
++{
++	char *rtw_efuse_file_map_path;
++	u8 Status;
++	PEFUSE_HAL pEfuseHal;
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++	struct mp_priv *pmp_priv = &padapter->mppriv;
++
++	pEfuseHal = &pHalData->EfuseHal;
++	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
++		return -EFAULT;
++
++	rtw_efuse_file_map_path = extra;
++
++	_rtw_memset(pEfuseHal->fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
++
++	if (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) {
++		RTW_INFO("%s do rtw_efuse_mask_file_read = %s!\n", __func__, rtw_efuse_file_map_path);
++		Status = rtw_efuse_file_read(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeBTEfuseModifiedMap, sizeof(pEfuseHal->fakeBTEfuseModifiedMap));
++		if (Status == _TRUE) {
++			pmp_priv->bloadBTefusemap = _TRUE;
++			sprintf(extra, "BT efuse file file_read OK\n");
++		} else {
++			pmp_priv->bloadBTefusemap = _FALSE;
++			sprintf(extra, "BT efuse file file_read FAIL\n");
++		}
++	} else {
++		sprintf(extra, "BT efuse file readable FAIL\n");
++		RTW_INFO("%s rtw_is_file_readable fail!\n", __func__);
++	}
++	wrqu->data.length = strlen(extra);
++	return 0;
++}
++
++
++static inline void dump_buf(u8 *buf, u32 len)
++{
++	u32 i;
++
++	RTW_INFO("-----------------Len %d----------------\n", len);
++	for (i = 0; i < len; i++)
++		RTW_INFO("%2.2x-", *(buf + i));
++	RTW_INFO("\n");
++}
++
++int rtw_mp_link(struct net_device *dev,
++			struct iw_request_info *info,
++			struct iw_point *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	struct mp_priv *pmp_priv;
++	char	input[wrqu->length];
++	int		bgetrxdata = 0, btxdata = 0, bsetbt = 0;
++	u8 err = 0;
++	u32 i = 0, datalen = 0,jj, kk, waittime = 0;
++	u16 val = 0x00, ret = 0;
++	char *pextra = NULL;
++	u8 *setdata = NULL;
++	char *pch, *ptmp, *token, *tmp[4] = {0x00, 0x00, 0x00};
++
++	pmp_priv = &padapter->mppriv;
++
++	if (copy_from_user(input, wrqu->pointer, wrqu->length))
++		return -EFAULT;
++
++	_rtw_memset(extra, 0, wrqu->length);
++
++	RTW_INFO("%s: in=%s\n", __func__, input);
++
++	bgetrxdata =  (strncmp(input, "rxdata", 6) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
++	btxdata =  (strncmp(input, "txdata", 6) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
++	bsetbt =  (strncmp(input, "setbt", 5) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
++
++	if (bgetrxdata) {
++		RTW_INFO("%s: in= 1 \n", __func__);
++		if (pmp_priv->mplink_brx == _TRUE) {
++			pch = extra;
++				while (waittime < 100 && pmp_priv->mplink_brx == _FALSE) {
++						if (pmp_priv->mplink_brx == _FALSE)
++							rtw_msleep_os(10);
++						else
++							break;
++						waittime++;
++				}
++				if (pmp_priv->mplink_brx == _TRUE) {
++					pch += sprintf(pch, "\n");
++
++					for (i = 0; i < pmp_priv->mplink_rx_len; i ++) {
++						pch += sprintf(pch, "%02x:", pmp_priv->mplink_buf[i]);
++					}
++					_rtw_memset(pmp_priv->mplink_buf, '\0' , sizeof(pmp_priv->mplink_buf));
++					pmp_priv->mplink_brx = _FALSE;
++				}
++		}
++	} else if (btxdata) {
++		struct pkt_attrib *pattrib;
++
++		pch = input;
++		setdata = rtw_zmalloc(1024);
++		if (setdata == NULL) {
++			err = -ENOMEM;
++			goto exit;
++		}
++
++		i = 0;
++		while ((token = strsep(&pch, ",")) != NULL) {
++			if (i > 2)
++				break;
++			tmp[i] = token;
++			i++;
++		}
++
++		/* tmp[0],[1],[2] */
++		/* txdata,00e04c871200........... */
++		if (strcmp(tmp[0], "txdata") == 0) {
++			if ((tmp[1] == NULL)) {
++				err = -EINVAL;
++				goto exit;
++			}
++		}
++
++		datalen = strlen(tmp[1]);
++		if (datalen % 2) {
++			err = -EINVAL;
++			goto exit;
++		}
++		datalen /= 2;
++		if (datalen == 0) {
++			err = -EINVAL;
++			goto exit;
++		}
++
++		RTW_INFO("%s: data len=%d\n", __FUNCTION__, datalen);
++		RTW_INFO("%s: tx data=%s\n", __FUNCTION__, tmp[1]);
++
++		for (jj = 0, kk = 0; jj < datalen; jj++, kk += 2)
++			setdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
++
++		dump_buf(setdata, datalen);
++		_rtw_memset(pmp_priv->mplink_buf, '\0' , sizeof(pmp_priv->mplink_buf));
++		_rtw_memcpy(pmp_priv->mplink_buf, setdata, datalen);
++
++		pattrib = &pmp_priv->tx.attrib;
++		pattrib->pktlen = datalen;
++		pmp_priv->tx.count = 1;
++		pmp_priv->tx.stop = 0;
++		pmp_priv->mplink_btx = _TRUE;
++		SetPacketTx(padapter);
++		pmp_priv->mode = MP_PACKET_TX;
++
++	} else if (bsetbt) {
++
++#ifdef CONFIG_BT_COEXIST
++		pch = input;
++		i = 0;
++
++		while ((token = strsep(&pch, ",")) != NULL) {
++			if (i > 3)
++				break;
++			tmp[i] = token;
++			i++;
++		}
++
++		if (tmp[1] == NULL) {
++			err = -EINVAL;
++			goto exit;
++		}
++
++		if (strcmp(tmp[1], "scbd") == 0) {
++			u16 org_val = 0x8002, pre_val, read_score_board_val;
++			u8 state;
++
++			pre_val = (rtw_read16(padapter,(0xaa))) & 0x7fff;
++
++			if (tmp[2] != NULL) {
++				state = simple_strtoul(tmp[2], &ptmp, 10);
++
++				if (state)
++						org_val = org_val | BIT6;
++				else
++						org_val = org_val & (~BIT6);
++
++				if (org_val != pre_val) {
++					pre_val = org_val;
++					rtw_write16(padapter, 0xaa, org_val);
++					RTW_INFO("%s,setbt scbd write org_val = 0x%x , pre_val = 0x%x\n", __func__, org_val, pre_val);
++				} else {
++					RTW_INFO("%s,setbt scbd org_val = 0x%x ,pre_val = 0x%x\n", __func__, org_val, pre_val);
++				}
++			} else {
++					read_score_board_val = (rtw_read16(padapter,(0xaa))) & 0x7fff;
++					RTW_INFO("%s,read_score_board_val = 0x%x\n", __func__, read_score_board_val);
++			}
++			goto exit;
++
++		} else if (strcmp(tmp[1], "testmode") == 0) {
++
++			if (tmp[2] == NULL) {
++				err = -EINVAL;
++				goto exit;
++			}
++
++			val = simple_strtoul(tmp[2], &ptmp, 16);
++			RTW_INFO("get tmp, type  %s, val =0x%x!\n", tmp[1], val);
++
++			if (tmp[2] != NULL) {
++				_rtw_memset(extra, 0, wrqu->length);
++				pch = extra;
++				ret = rtw_btcoex_btset_testmode(padapter, val);
++				if (!CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS)) {
++					RTW_INFO("%s: BT_OP fail = 0x%x!\n", __FUNCTION__, val);
++					pch += sprintf(pch, "BT_OP fail  0x%x!\n", val);
++				} else
++					pch += sprintf(pch, "Set BT_OP 0x%x done!\n", val);
++			}
++
++		}
++#endif /* CONFIG_BT_COEXIST */
++	}
++
++exit:
++	if (setdata)
++		rtw_mfree(setdata, 1024);
++
++	wrqu->length = strlen(extra);
++	return err;
++
++}
++
++#if defined(CONFIG_RTL8723B)
++int rtw_mp_SetBT(struct net_device *dev,
++		 struct iw_request_info *info,
++		 union iwreq_data *wrqu, char *extra)
++{
++	PADAPTER padapter = rtw_netdev_priv(dev);
++	struct hal_ops *pHalFunc = &padapter->hal_func;
++	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
++
++	BT_REQ_CMD	BtReq;
++	PMPT_CONTEXT	pMptCtx = &(padapter->mppriv.mpt_ctx);
++	PBT_RSP_CMD	pBtRsp = (PBT_RSP_CMD)&pMptCtx->mptOutBuf[0];
++	char	input[128];
++	char *pch, *ptmp, *token, *tmp[2] = {0x00, 0x00};
++	u8 setdata[100];
++	u8 resetbt = 0x00;
++	u8 tempval, BTStatus;
++	u8 H2cSetbtmac[6];
++	u8 u1H2CBtMpOperParm[4] = {0x01};
++	int testmode = 1, ready = 1, trxparam = 1, setgen = 1, getgen = 1, testctrl = 1, testbt = 1, readtherm = 1, setbtmac = 1;
++	u32 i = 0, ii = 0, jj = 0, kk = 0, cnts = 0, status = 0;
++	PRT_MP_FIRMWARE pBTFirmware = NULL;
++
++	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
++		return -EFAULT;
++
++	*(extra + wrqu->data.length) = '\0';
++	pch = extra;
++
++	if (strlen(extra) < 1)
++		return -EFAULT;
++
++	RTW_INFO("%s:iwpriv in=%s\n", __func__, extra);
++	ready = strncmp(extra, "ready", 5);
++	testmode = strncmp(extra, "testmode", 8); /* strncmp TRUE is 0*/
++	trxparam = strncmp(extra, "trxparam", 8);
++	setgen = strncmp(extra, "setgen", 6);
++	getgen = strncmp(extra, "getgen", 6);
++	testctrl = strncmp(extra, "testctrl", 8);
++	testbt = strncmp(extra, "testbt", 6);
++	readtherm = strncmp(extra, "readtherm", 9);
++	setbtmac = strncmp(extra, "setbtmac", 8);
++
++	if (strncmp(extra, "dlbt", 4) == 0) {
++		pHalData->LastHMEBoxNum = 0;
++		pHalData->bBTFWReady = _FALSE;
++		rtw_write8(padapter, 0xa3, 0x05);
++		BTStatus = rtw_read8(padapter, 0xa0);
++		RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __func__, BTStatus);
++		if (BTStatus != 0x04) {
++			pch += sprintf(pch, "BT Status not Active DLFW FAIL\n");
++			goto exit;
++		}
++
++		tempval = rtw_read8(padapter, 0x6B);
++		tempval |= BIT7;
++		rtw_write8(padapter, 0x6B, tempval);
++
++		/* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay*/
++		/* So don't write 0x6A[14]=1 and 0x6A[15]=0 together!*/
++		rtw_usleep_os(100);
++		/* disable BT power cut*/
++		/* 0x6A[14] = 0*/
++		tempval = rtw_read8(padapter, 0x6B);
++		tempval &= ~BIT6;
++		rtw_write8(padapter, 0x6B, tempval);
++		rtw_usleep_os(100);
++		MPT_PwrCtlDM(padapter, 0);
++		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004));
++		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF));
++		rtw_msleep_os(600);
++		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010));
++		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB));
++		rtw_msleep_os(1200);
++		pBTFirmware = (PRT_MP_FIRMWARE)rtw_zmalloc(sizeof(RT_MP_FIRMWARE));
++		if (pBTFirmware == NULL)
++			goto exit;
++		pHalData->bBTFWReady = _FALSE;
++		FirmwareDownloadBT(padapter, pBTFirmware);
++		if (pBTFirmware)
++			rtw_mfree((u8 *)pBTFirmware, sizeof(RT_MP_FIRMWARE));
++
++		RTW_INFO("Wait for FirmwareDownloadBT fw boot!\n");
++		rtw_msleep_os(2000);
++		_rtw_memset(extra, '\0', wrqu->data.length);
++		BtReq.opCodeVer = 1;
++		BtReq.OpCode = 0;
++		BtReq.paraLength = 0;
++		mptbt_BtControlProcess(padapter, &BtReq);
++		rtw_msleep_os(100);
++
++		RTW_INFO("FirmwareDownloadBT ready = 0x%x 0x%x", pMptCtx->mptOutBuf[4], pMptCtx->mptOutBuf[5]);
++		if ((pMptCtx->mptOutBuf[4] == 0x00) && (pMptCtx->mptOutBuf[5] == 0x00)) {
++
++			if (padapter->mppriv.bTxBufCkFail == _TRUE)
++				pch += sprintf(pch, "check TxBuf Fail.\n");
++			else
++				pch += sprintf(pch, "download FW Fail.\n");
++		} else {
++			pch += sprintf(pch, "download FW OK.\n");
++			goto exit;
++		}
++		goto exit;
++	}
++	if (strncmp(extra, "dlfw", 4) == 0) {
++		pHalData->LastHMEBoxNum = 0;
++		pHalData->bBTFWReady = _FALSE;
++		rtw_write8(padapter, 0xa3, 0x05);
++		BTStatus = rtw_read8(padapter, 0xa0);
++		RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __func__, BTStatus);
++		if (BTStatus != 0x04) {
++			pch += sprintf(pch, "BT Status not Active DLFW FAIL\n");
++			goto exit;
++		}
++
++		tempval = rtw_read8(padapter, 0x6B);
++		tempval |= BIT7;
++		rtw_write8(padapter, 0x6B, tempval);
++
++		/* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay*/
++		/* So don't write 0x6A[14]=1 and 0x6A[15]=0 together!*/
++		rtw_usleep_os(100);
++		/* disable BT power cut*/
++		/* 0x6A[14] = 0*/
++		tempval = rtw_read8(padapter, 0x6B);
++		tempval &= ~BIT6;
++		rtw_write8(padapter, 0x6B, tempval);
++		rtw_usleep_os(100);
++
++		MPT_PwrCtlDM(padapter, 0);
++		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004));
++		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF));
++		rtw_msleep_os(600);
++		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010));
++		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB));
++		rtw_msleep_os(1200);
++
++#if defined(CONFIG_PLATFORM_SPRD) && (MP_DRIVER == 1)
++		/* Pull up BT reset pin.*/
++		RTW_INFO("%s: pull up BT reset pin when bt start mp test\n", __func__);
++		rtw_wifi_gpio_wlan_ctrl(WLAN_BT_PWDN_ON);
++#endif
++		RTW_INFO(" FirmwareDownload!\n");
++
++#if defined(CONFIG_RTL8723B)
++		status = rtl8723b_FirmwareDownload(padapter, _FALSE);
++#endif
++		RTW_INFO("Wait for FirmwareDownloadBT fw boot!\n");
++		rtw_msleep_os(1000);
++#ifdef CONFIG_BT_COEXIST
++		rtw_btcoex_HaltNotify(padapter);
++		RTW_INFO("SetBT btcoex HaltNotify !\n");
++		/*hal_btcoex1ant_SetAntPath(padapter);*/
++		rtw_btcoex_SetManualControl(padapter, _TRUE);
++#endif
++		_rtw_memset(extra, '\0', wrqu->data.length);
++		BtReq.opCodeVer = 1;
++		BtReq.OpCode = 0;
++		BtReq.paraLength = 0;
++		mptbt_BtControlProcess(padapter, &BtReq);
++		rtw_msleep_os(200);
++
++		RTW_INFO("FirmwareDownloadBT ready = 0x%x 0x%x", pMptCtx->mptOutBuf[4], pMptCtx->mptOutBuf[5]);
++		if ((pMptCtx->mptOutBuf[4] == 0x00) && (pMptCtx->mptOutBuf[5] == 0x00)) {
++			if (padapter->mppriv.bTxBufCkFail == _TRUE)
++				pch += sprintf(pch, "check TxBuf Fail.\n");
++			else
++				pch += sprintf(pch, "download FW Fail.\n");
++		} else {
++#ifdef CONFIG_BT_COEXIST
++			rtw_btcoex_SwitchBtTRxMask(padapter);
++#endif
++			rtw_msleep_os(200);
++			pch += sprintf(pch, "download FW OK.\n");
++			goto exit;
++		}
++		goto exit;
++	}
++
++	if (strncmp(extra, "down", 4) == 0) {
++		RTW_INFO("SetBT down for to hal_init !\n");
++#ifdef CONFIG_BT_COEXIST
++		rtw_btcoex_SetManualControl(padapter, _FALSE);
++		rtw_btcoex_Initialize(padapter);
++#endif
++		pHalFunc->read_adapter_info(padapter);
++		pHalFunc->hal_deinit(padapter);
++		pHalFunc->hal_init(padapter);
++		rtw_pm_set_ips(padapter, IPS_NONE);
++		LeaveAllPowerSaveMode(padapter);
++		MPT_PwrCtlDM(padapter, 0);
++		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004));
++		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF));
++		rtw_msleep_os(600);
++		/*rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a)& 0xFFFFFFFE));*/
++		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010));
++		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB));
++		rtw_msleep_os(1200);
++		goto exit;
++	}
++	if (strncmp(extra, "disable", 7) == 0) {
++		RTW_INFO("SetBT disable !\n");
++		rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a) & 0xFFFFFFFB));
++		rtw_msleep_os(500);
++		goto exit;
++	}
++	if (strncmp(extra, "enable", 6) == 0) {
++		RTW_INFO("SetBT enable !\n");
++		rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a) | 0x00000004));
++		rtw_msleep_os(500);
++		goto exit;
++	}
++	if (strncmp(extra, "h2c", 3) == 0) {
++		RTW_INFO("SetBT h2c !\n");
++		pHalData->bBTFWReady = _TRUE;
++		rtw_hal_fill_h2c_cmd(padapter, 0x63, 1, u1H2CBtMpOperParm);
++		goto exit;
++	}
++	if (strncmp(extra, "2ant", 4) == 0) {
++		RTW_INFO("Set BT 2ant use!\n");
++		phy_set_mac_reg(padapter, 0x67, BIT5, 0x1);
++		rtw_write32(padapter, 0x948, 0000);
++
++		goto exit;
++	}
++
++	if (ready != 0 && testmode != 0 && trxparam != 0 && setgen != 0 && getgen != 0 && testctrl != 0 && testbt != 0 && readtherm != 0 && setbtmac != 0)
++		return -EFAULT;
++
++	if (testbt == 0) {
++		BtReq.opCodeVer = 1;
++		BtReq.OpCode = 6;
++		BtReq.paraLength = cnts / 2;
++		goto todo;
++	}
++	if (ready == 0) {
++		BtReq.opCodeVer = 1;
++		BtReq.OpCode = 0;
++		BtReq.paraLength = 0;
++		goto todo;
++	}
++
++	i = 0;
++	while ((token = strsep(&pch, ",")) != NULL) {
++		if (i > 1)
++			break;
++		tmp[i] = token;
++		i++;
++	}
++
++	if ((tmp[0] != NULL) && (tmp[1] != NULL)) {
++		cnts = strlen(tmp[1]);
++		if (cnts < 1)
++			return -EFAULT;
++
++		RTW_INFO("%s: cnts=%d\n", __func__, cnts);
++		RTW_INFO("%s: data=%s\n", __func__, tmp[1]);
++
++		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) {
++			BtReq.pParamStart[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
++			/*			RTW_INFO("BtReq.pParamStart[%d]=0x%02x\n", jj, BtReq.pParamStart[jj]);*/
++		}
++	} else
++		return -EFAULT;
++
++	if (testmode == 0) {
++		BtReq.opCodeVer = 1;
++		BtReq.OpCode = 1;
++		BtReq.paraLength = 1;
++	}
++	if (trxparam == 0) {
++		BtReq.opCodeVer = 1;
++		BtReq.OpCode = 2;
++		BtReq.paraLength = cnts / 2;
++	}
++	if (setgen == 0) {
++		RTW_INFO("%s: BT_SET_GENERAL\n", __func__);
++		BtReq.opCodeVer = 1;
++		BtReq.OpCode = 3;/*BT_SET_GENERAL	3*/
++		BtReq.paraLength = cnts / 2;
++	}
++	if (getgen == 0) {
++		RTW_INFO("%s: BT_GET_GENERAL\n", __func__);
++		BtReq.opCodeVer = 1;
++		BtReq.OpCode = 4;/*BT_GET_GENERAL	4*/
++		BtReq.paraLength = cnts / 2;
++	}
++	if (readtherm == 0) {
++		RTW_INFO("%s: BT_GET_GENERAL\n", __func__);
++		BtReq.opCodeVer = 1;
++		BtReq.OpCode = 4;/*BT_GET_GENERAL	4*/
++		BtReq.paraLength = cnts / 2;
++	}
++
++	if (testctrl == 0) {
++		RTW_INFO("%s: BT_TEST_CTRL\n", __func__);
++		BtReq.opCodeVer = 1;
++		BtReq.OpCode = 5;/*BT_TEST_CTRL	5*/
++		BtReq.paraLength = cnts / 2;
++	}
++
++	RTW_INFO("%s: Req opCodeVer=%d OpCode=%d paraLength=%d\n",
++		 __func__, BtReq.opCodeVer, BtReq.OpCode, BtReq.paraLength);
++
++	if (BtReq.paraLength < 1)
++		goto todo;
++	for (i = 0; i < BtReq.paraLength; i++) {
++		RTW_INFO("%s: BtReq.pParamStart[%d] = 0x%02x\n",
++			 __func__, i, BtReq.pParamStart[i]);
++	}
++
++todo:
++	_rtw_memset(extra, '\0', wrqu->data.length);
++
++	if (pHalData->bBTFWReady == _FALSE) {
++		pch += sprintf(pch, "BTFWReady = FALSE.\n");
++		goto exit;
++	}
++
++	mptbt_BtControlProcess(padapter, &BtReq);
++
++	if (readtherm == 0) {
++		pch += sprintf(pch, "BT thermal=");
++		for (i = 4; i < pMptCtx->mptOutLen; i++) {
++			if ((pMptCtx->mptOutBuf[i] == 0x00) && (pMptCtx->mptOutBuf[i + 1] == 0x00))
++				goto exit;
++
++			pch += sprintf(pch, " %d ", (pMptCtx->mptOutBuf[i] & 0x1f));
++		}
++	} else {
++		for (i = 4; i < pMptCtx->mptOutLen; i++)
++			pch += sprintf(pch, " 0x%x ", pMptCtx->mptOutBuf[i]);
++	}
++
++exit:
++	wrqu->data.length = strlen(extra) + 1;
++	RTW_INFO("-%s: output len=%d data=%s\n", __func__, wrqu->data.length, extra);
++
++	return status;
++}
++
++#endif /*#ifdef CONFIG_RTL8723B*/
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/mlme_linux.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/mlme_linux.c
+new file mode 100644
+index 000000000..6fd24e8e2
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/mlme_linux.c
+@@ -0,0 +1,444 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++
++#define _MLME_OSDEP_C_
++
++#include <drv_types.h>
++
++
++#ifdef RTK_DMP_PLATFORM
++void Linkup_workitem_callback(struct work_struct *work)
++{
++	struct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkup_workitem);
++	_adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv);
++
++
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12))
++	kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKUP);
++#else
++	kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKUP);
++#endif
++
++}
++
++void Linkdown_workitem_callback(struct work_struct *work)
++{
++	struct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkdown_workitem);
++	_adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv);
++
++
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12))
++	kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKDOWN);
++#else
++	kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKDOWN);
++#endif
++
++}
++#endif
++
++extern void rtw_indicate_wx_assoc_event(_adapter *padapter);
++extern void rtw_indicate_wx_disassoc_event(_adapter *padapter);
++
++void rtw_os_indicate_connect(_adapter *adapter)
++{
++	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
++	    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
++		rtw_cfg80211_ibss_indicate_connect(adapter);
++	else
++		rtw_cfg80211_indicate_connect(adapter);
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++	rtw_indicate_wx_assoc_event(adapter);
++
++#ifdef CONFIG_RTW_MESH
++#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER
++	if (!rtw_mesh_cto_mgate_required(adapter))
++#endif
++#endif
++		rtw_netif_carrier_on(adapter->pnetdev);
++
++	if (adapter->pid[2] != 0)
++		rtw_signal_process(adapter->pid[2], SIGALRM);
++
++#ifdef RTK_DMP_PLATFORM
++	_set_workitem(&adapter->mlmepriv.Linkup_workitem);
++#endif
++
++
++}
++
++extern void indicate_wx_scan_complete_event(_adapter *padapter);
++void rtw_os_indicate_scan_done(_adapter *padapter, bool aborted)
++{
++#ifdef CONFIG_IOCTL_CFG80211
++	rtw_cfg80211_indicate_scan_done(padapter, aborted);
++#endif
++	indicate_wx_scan_complete_event(padapter);
++}
++
++static RT_PMKID_LIST   backupPMKIDList[NUM_PMKID_CACHE];
++void rtw_reset_securitypriv(_adapter *adapter)
++{
++	u8	backupPMKIDIndex = 0;
++	u8	backupTKIPCountermeasure = 0x00;
++	u32	backupTKIPcountermeasure_time = 0;
++	/* add for CONFIG_IEEE80211W, none 11w also can use */
++	_irqL irqL;
++
++	_enter_critical_bh(&adapter->security_key_mutex, &irqL);
++
++	if (adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { /* 802.1x */
++		u8 backup_sw_encrypt, backup_sw_decrypt;
++
++		backup_sw_encrypt = adapter->securitypriv.sw_encrypt;
++		backup_sw_decrypt = adapter->securitypriv.sw_decrypt;
++
++		/* Added by Albert 2009/02/18 */
++		/* We have to backup the PMK information for WiFi PMK Caching test item. */
++		/*  */
++		/* Backup the btkip_countermeasure information. */
++		/* When the countermeasure is trigger, the driver have to disconnect with AP for 60 seconds. */
++
++		_rtw_memset(&backupPMKIDList[0], 0x00, sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);
++
++		_rtw_memcpy(&backupPMKIDList[0], &adapter->securitypriv.PMKIDList[0], sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);
++		backupPMKIDIndex = adapter->securitypriv.PMKIDIndex;
++		backupTKIPCountermeasure = adapter->securitypriv.btkip_countermeasure;
++		backupTKIPcountermeasure_time = adapter->securitypriv.btkip_countermeasure_time;
++		_rtw_memset((unsigned char *)&adapter->securitypriv, 0, sizeof(struct security_priv));
++
++		/* Added by Albert 2009/02/18 */
++		/* Restore the PMK information to securitypriv structure for the following connection. */
++		_rtw_memcpy(&adapter->securitypriv.PMKIDList[0], &backupPMKIDList[0], sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);
++		adapter->securitypriv.PMKIDIndex = backupPMKIDIndex;
++		adapter->securitypriv.btkip_countermeasure = backupTKIPCountermeasure;
++		adapter->securitypriv.btkip_countermeasure_time = backupTKIPcountermeasure_time;
++
++		adapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;
++		adapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled;
++
++		adapter->securitypriv.extauth_status = WLAN_STATUS_UNSPECIFIED_FAILURE;
++
++		adapter->securitypriv.sw_encrypt = backup_sw_encrypt;
++		adapter->securitypriv.sw_decrypt = backup_sw_decrypt;
++
++	} else { /* reset values in securitypriv */
++		/* if(adapter->mlmepriv.fw_state & WIFI_STATION_STATE) */
++		/* { */
++		struct security_priv *psec_priv = &adapter->securitypriv;
++
++		psec_priv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
++		psec_priv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
++		psec_priv->dot11PrivacyKeyIndex = 0;
++
++		psec_priv->dot118021XGrpPrivacy = _NO_PRIVACY_;
++		psec_priv->dot118021XGrpKeyid = 1;
++
++		psec_priv->ndisauthtype = Ndis802_11AuthModeOpen;
++		psec_priv->ndisencryptstatus = Ndis802_11WEPDisabled;
++		/* } */
++
++		psec_priv->extauth_status = WLAN_STATUS_UNSPECIFIED_FAILURE;
++	}
++	/* add for CONFIG_IEEE80211W, none 11w also can use */
++	_exit_critical_bh(&adapter->security_key_mutex, &irqL);
++
++	RTW_INFO(FUNC_ADPT_FMT" - End to Disconnect\n", FUNC_ADPT_ARG(adapter));
++}
++
++void rtw_os_indicate_disconnect(_adapter *adapter,  u16 reason, u8 locally_generated)
++{
++	/* RT_PMKID_LIST   backupPMKIDList[NUM_PMKID_CACHE]; */
++
++
++	rtw_netif_carrier_off(adapter->pnetdev); /* Do it first for tx broadcast pkt after disconnection issue! */
++
++#ifdef CONFIG_IOCTL_CFG80211
++	rtw_cfg80211_indicate_disconnect(adapter,  reason, locally_generated);
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++	rtw_indicate_wx_disassoc_event(adapter);
++
++#ifdef RTK_DMP_PLATFORM
++	_set_workitem(&adapter->mlmepriv.Linkdown_workitem);
++#endif
++	/* modify for CONFIG_IEEE80211W, none 11w also can use the same command */
++	rtw_reset_securitypriv_cmd(adapter);
++
++
++}
++
++void rtw_report_sec_ie(_adapter *adapter, u8 authmode, u8 *sec_ie)
++{
++	uint	len;
++	u8	*buff, *p, i;
++	union iwreq_data wrqu;
++
++
++
++	buff = NULL;
++	if (authmode == _WPA_IE_ID_) {
++
++		buff = rtw_zmalloc(IW_CUSTOM_MAX);
++		if (NULL == buff) {
++			RTW_INFO(FUNC_ADPT_FMT ": alloc memory FAIL!!\n",
++				 FUNC_ADPT_ARG(adapter));
++			return;
++		}
++		p = buff;
++
++		p += sprintf(p, "ASSOCINFO(ReqIEs=");
++
++		len = sec_ie[1] + 2;
++		len = (len < IW_CUSTOM_MAX) ? len : IW_CUSTOM_MAX;
++
++		for (i = 0; i < len; i++)
++			p += sprintf(p, "%02x", sec_ie[i]);
++
++		p += sprintf(p, ")");
++
++		_rtw_memset(&wrqu, 0, sizeof(wrqu));
++
++		wrqu.data.length = p - buff;
++
++		wrqu.data.length = (wrqu.data.length < IW_CUSTOM_MAX) ? wrqu.data.length : IW_CUSTOM_MAX;
++
++#ifndef CONFIG_IOCTL_CFG80211
++		wireless_send_event(adapter->pnetdev, IWEVCUSTOM, &wrqu, buff);
++#endif
++
++		rtw_mfree(buff, IW_CUSTOM_MAX);
++	}
++
++
++}
++
++#ifdef CONFIG_AP_MODE
++
++void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta)
++{
++	union iwreq_data wrqu;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++
++	if (psta == NULL)
++		return;
++
++	if (psta->cmn.aid > pstapriv->max_aid)
++		return;
++
++	if (pstapriv->sta_aid[psta->cmn.aid - 1] != psta)
++		return;
++
++
++	wrqu.addr.sa_family = ARPHRD_ETHER;
++
++	_rtw_memcpy(wrqu.addr.sa_data, psta->cmn.mac_addr, ETH_ALEN);
++
++	RTW_INFO("+rtw_indicate_sta_assoc_event\n");
++
++#ifndef CONFIG_IOCTL_CFG80211
++	wireless_send_event(padapter->pnetdev, IWEVREGISTERED, &wrqu, NULL);
++#endif
++
++}
++
++void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta)
++{
++	union iwreq_data wrqu;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++
++	if (psta == NULL)
++		return;
++
++	if (psta->cmn.aid > pstapriv->max_aid)
++		return;
++
++	if (pstapriv->sta_aid[psta->cmn.aid - 1] != psta)
++		return;
++
++
++	wrqu.addr.sa_family = ARPHRD_ETHER;
++
++	_rtw_memcpy(wrqu.addr.sa_data, psta->cmn.mac_addr, ETH_ALEN);
++
++	RTW_INFO("+rtw_indicate_sta_disassoc_event\n");
++
++#ifndef CONFIG_IOCTL_CFG80211
++	wireless_send_event(padapter->pnetdev, IWEVEXPIRED, &wrqu, NULL);
++#endif
++
++}
++
++
++#ifdef CONFIG_HOSTAPD_MLME
++
++static int mgnt_xmit_entry(struct sk_buff *skb, struct net_device *pnetdev)
++{
++	struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev);
++	_adapter *padapter = (_adapter *)phostapdpriv->padapter;
++
++	/* RTW_INFO("%s\n", __FUNCTION__); */
++
++	return rtw_hal_hostap_mgnt_xmit_entry(padapter, skb);
++}
++
++static int mgnt_netdev_open(struct net_device *pnetdev)
++{
++	struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev);
++
++	RTW_INFO("mgnt_netdev_open: MAC Address:" MAC_FMT "\n", MAC_ARG(pnetdev->dev_addr));
++
++
++	init_usb_anchor(&phostapdpriv->anchored);
++
++	rtw_netif_wake_queue(pnetdev);
++
++	rtw_netif_carrier_on(pnetdev);
++
++	/* rtw_write16(phostapdpriv->padapter, 0x0116, 0x0100); */ /* only excluding beacon */
++
++	return 0;
++}
++static int mgnt_netdev_close(struct net_device *pnetdev)
++{
++	struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev);
++
++	RTW_INFO("%s\n", __FUNCTION__);
++
++	usb_kill_anchored_urbs(&phostapdpriv->anchored);
++
++	rtw_netif_carrier_off(pnetdev);
++
++	rtw_netif_stop_queue(pnetdev);
++
++	/* rtw_write16(phostapdpriv->padapter, 0x0116, 0x3f3f); */
++
++	return 0;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
++static const struct net_device_ops rtl871x_mgnt_netdev_ops = {
++	.ndo_open = mgnt_netdev_open,
++	.ndo_stop = mgnt_netdev_close,
++	.ndo_start_xmit = mgnt_xmit_entry,
++	#if 0
++	.ndo_set_mac_address = r871x_net_set_mac_address,
++	.ndo_get_stats = r871x_net_get_stats,
++	.ndo_do_ioctl = r871x_mp_ioctl,
++	#endif
++};
++#endif
++
++int hostapd_mode_init(_adapter *padapter)
++{
++	unsigned char mac[ETH_ALEN];
++	struct hostapd_priv *phostapdpriv;
++	struct net_device *pnetdev;
++
++	pnetdev = rtw_alloc_etherdev(sizeof(struct hostapd_priv));
++	if (!pnetdev)
++		return -ENOMEM;
++
++	/* SET_MODULE_OWNER(pnetdev); */
++	ether_setup(pnetdev);
++
++	/* pnetdev->type = ARPHRD_IEEE80211; */
++
++	phostapdpriv = rtw_netdev_priv(pnetdev);
++	phostapdpriv->pmgnt_netdev = pnetdev;
++	phostapdpriv->padapter = padapter;
++	padapter->phostapdpriv = phostapdpriv;
++
++	/* pnetdev->init = NULL; */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
++
++	RTW_INFO("register rtl871x_mgnt_netdev_ops to netdev_ops\n");
++
++	pnetdev->netdev_ops = &rtl871x_mgnt_netdev_ops;
++
++#else
++
++	pnetdev->open = mgnt_netdev_open;
++
++	pnetdev->stop = mgnt_netdev_close;
++
++	pnetdev->hard_start_xmit = mgnt_xmit_entry;
++
++	/* pnetdev->set_mac_address = r871x_net_set_mac_address; */
++
++	/* pnetdev->get_stats = r871x_net_get_stats; */
++
++	/* pnetdev->do_ioctl = r871x_mp_ioctl; */
++
++#endif
++
++	pnetdev->watchdog_timeo = HZ; /* 1 second timeout */
++
++	/* pnetdev->wireless_handlers = NULL; */
++
++
++
++
++	if (dev_alloc_name(pnetdev, "mgnt.wlan%d") < 0)
++		RTW_INFO("hostapd_mode_init(): dev_alloc_name, fail!\n");
++
++
++	/* SET_NETDEV_DEV(pnetdev, pintfpriv->udev); */
++
++
++	mac[0] = 0x00;
++	mac[1] = 0xe0;
++	mac[2] = 0x4c;
++	mac[3] = 0x87;
++	mac[4] = 0x11;
++	mac[5] = 0x12;
++
++	_rtw_memcpy(pnetdev->dev_addr, mac, ETH_ALEN);
++
++
++	rtw_netif_carrier_off(pnetdev);
++
++
++	/* Tell the network stack we exist */
++	if (register_netdev(pnetdev) != 0) {
++		RTW_INFO("hostapd_mode_init(): register_netdev fail!\n");
++
++		if (pnetdev)
++			rtw_free_netdev(pnetdev);
++	}
++
++	return 0;
++
++}
++
++void hostapd_mode_unload(_adapter *padapter)
++{
++	struct hostapd_priv *phostapdpriv = padapter->phostapdpriv;
++	struct net_device *pnetdev = phostapdpriv->pmgnt_netdev;
++
++	unregister_netdev(pnetdev);
++	rtw_free_netdev(pnetdev);
++
++}
++
++#endif
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/os_intfs.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/os_intfs.c
+new file mode 100755
+index 000000000..dc24c8c0e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/os_intfs.c
+@@ -0,0 +1,5646 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _OS_INTFS_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Realtek Wireless Lan Driver");
++MODULE_AUTHOR("Realtek Semiconductor Corp.");
++MODULE_VERSION(DRIVERVERSION);
++
++/* module param defaults */
++int rtw_chip_version = 0x00;
++int rtw_rfintfs = HWPI;
++int rtw_lbkmode = 0;/* RTL8712_AIR_TRX; */
++#ifdef DBG_LA_MODE
++int rtw_la_mode_en=0;
++module_param(rtw_la_mode_en, int, 0644);
++#endif
++int rtw_network_mode = Ndis802_11IBSS;/* Ndis802_11Infrastructure; */ /* infra, ad-hoc, auto */
++/* NDIS_802_11_SSID	ssid; */
++int rtw_channel = 1;/* ad-hoc support requirement */
++int rtw_wireless_mode = WIRELESS_MODE_MAX;
++module_param(rtw_wireless_mode, int, 0644);
++int rtw_vrtl_carrier_sense = AUTO_VCS;
++int rtw_vcs_type = RTS_CTS;
++int rtw_rts_thresh = 2347;
++int rtw_frag_thresh = 2346;
++int rtw_preamble = PREAMBLE_LONG;/* long, short, auto */
++int rtw_scan_mode = 1;/* active, passive */
++/* int smart_ps = 1; */
++#ifdef CONFIG_POWER_SAVING
++	/* IPS configuration */
++	int rtw_ips_mode = RTW_IPS_MODE;
++
++	/* LPS configuration */
++/* RTW_LPS_MODE=0:disable, 1:LPS , 2:LPS with clock gating, 3: power gating */
++#if (RTW_LPS_MODE > 0)
++	int rtw_power_mgnt = PS_MODE_MAX;
++
++	#ifdef CONFIG_USB_HCI
++		int rtw_lps_level = LPS_NORMAL; /*USB default LPS level*/
++	#else /*SDIO,PCIE*/
++		int rtw_lps_level = (RTW_LPS_MODE - 1);
++	#endif/*CONFIG_USB_HCI*/
++#else
++	int rtw_power_mgnt = PS_MODE_ACTIVE;
++	int rtw_lps_level = LPS_NORMAL;
++#endif
++
++	int rtw_lps_chk_by_tp = 1;
++
++	/* WOW LPS configuration */
++#ifdef CONFIG_WOWLAN
++/* RTW_WOW_LPS_MODE=0:disable, 1:LPS , 2:LPS with clock gating, 3: power gating */
++#if (RTW_WOW_LPS_MODE > 0)
++	int rtw_wow_power_mgnt = PS_MODE_MAX;
++	int rtw_wow_lps_level = (RTW_WOW_LPS_MODE - 1);
++#else
++	int rtw_wow_power_mgnt = PS_MODE_ACTIVE;
++	int rtw_wow_lps_level = LPS_NORMAL;
++#endif	
++#endif /* CONFIG_WOWLAN */
++
++#else /* !CONFIG_POWER_SAVING */
++	int rtw_ips_mode = IPS_NONE;
++	int rtw_power_mgnt = PS_MODE_ACTIVE;
++	int rtw_lps_level = LPS_NORMAL;
++	int rtw_lps_chk_by_tp = 0;
++#ifdef CONFIG_WOWLAN
++	int rtw_wow_power_mgnt = PS_MODE_ACTIVE;
++	int rtw_wow_lps_level = LPS_NORMAL;
++#endif /* CONFIG_WOWLAN */
++#endif /* CONFIG_POWER_SAVING */
++
++#ifdef CONFIG_NARROWBAND_SUPPORTING
++int rtw_nb_config = CONFIG_NB_VALUE;
++module_param(rtw_nb_config, int, 0644);
++MODULE_PARM_DESC(rtw_nb_config, "5M/10M/Normal bandwidth configuration");
++#endif
++
++module_param(rtw_ips_mode, int, 0644);
++MODULE_PARM_DESC(rtw_ips_mode, "The default IPS mode");
++
++module_param(rtw_lps_level, int, 0644);
++MODULE_PARM_DESC(rtw_lps_level, "The default LPS level");
++
++#ifdef CONFIG_LPS_1T1R
++int rtw_lps_1t1r = RTW_LPS_1T1R;
++module_param(rtw_lps_1t1r, int, 0644);
++MODULE_PARM_DESC(rtw_lps_1t1r, "The default LPS 1T1R setting");
++#endif
++
++module_param(rtw_lps_chk_by_tp, int, 0644);
++
++#ifdef CONFIG_WOWLAN
++module_param(rtw_wow_power_mgnt, int, 0644);
++MODULE_PARM_DESC(rtw_wow_power_mgnt, "The default WOW LPS mode");
++module_param(rtw_wow_lps_level, int, 0644);
++MODULE_PARM_DESC(rtw_wow_lps_level, "The default WOW LPS level");
++#ifdef CONFIG_LPS_1T1R
++int rtw_wow_lps_1t1r = RTW_WOW_LPS_1T1R;
++module_param(rtw_wow_lps_1t1r, int, 0644);
++MODULE_PARM_DESC(rtw_wow_lps_1t1r, "The default WOW LPS 1T1R setting");
++#endif
++#endif /* CONFIG_WOWLAN */
++
++/* LPS: 
++ * rtw_smart_ps = 0 => TX: pwr bit = 1, RX: PS_Poll
++ * rtw_smart_ps = 1 => TX: pwr bit = 0, RX: PS_Poll
++ * rtw_smart_ps = 2 => TX: pwr bit = 0, RX: NullData with pwr bit = 0
++*/
++int rtw_smart_ps = 2;
++
++int rtw_max_bss_cnt = 0;
++module_param(rtw_max_bss_cnt, int, 0644);
++#ifdef CONFIG_WMMPS_STA	
++/* WMMPS: 
++ * rtw_smart_ps = 0 => Only for fw test
++ * rtw_smart_ps = 1 => Refer to Beacon's TIM Bitmap
++ * rtw_smart_ps = 2 => Don't refer to Beacon's TIM Bitmap
++*/
++int rtw_wmm_smart_ps = 2;
++#endif /* CONFIG_WMMPS_STA */
++
++int rtw_check_fw_ps = 1;
++
++#ifdef CONFIG_TX_EARLY_MODE
++int rtw_early_mode = 1;
++#endif
++
++int rtw_usb_rxagg_mode = 2;/* RX_AGG_DMA=1, RX_AGG_USB=2 */
++module_param(rtw_usb_rxagg_mode, int, 0644);
++
++int rtw_dynamic_agg_enable = 1;
++module_param(rtw_dynamic_agg_enable, int, 0644);
++
++/* set log level when inserting driver module, default log level is _DRV_INFO_ = 4,
++* please refer to "How_to_set_driver_debug_log_level.doc" to set the available level.
++*/
++#ifdef CONFIG_RTW_DEBUG
++#ifdef RTW_LOG_LEVEL
++	uint rtw_drv_log_level = (uint)RTW_LOG_LEVEL; /* from Makefile */
++#else
++	uint rtw_drv_log_level = _DRV_INFO_;
++#endif
++module_param(rtw_drv_log_level, uint, 0644);
++MODULE_PARM_DESC(rtw_drv_log_level, "set log level when insert driver module, default log level is _DRV_INFO_ = 4");
++#endif
++int rtw_radio_enable = 1;
++int rtw_long_retry_lmt = 7;
++int rtw_short_retry_lmt = 7;
++int rtw_busy_thresh = 40;
++/* int qos_enable = 0; */ /* * */
++int rtw_ack_policy = NORMAL_ACK;
++
++int rtw_mp_mode = 0;
++
++#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)
++uint rtw_mp_customer_str = 0;
++module_param(rtw_mp_customer_str, uint, 0644);
++MODULE_PARM_DESC(rtw_mp_customer_str, "Whether or not to enable customer str support on MP mode");
++#endif
++
++int rtw_software_encrypt = 0;
++int rtw_software_decrypt = 0;
++
++int rtw_acm_method = 0;/* 0:By SW 1:By HW. */
++
++int rtw_wmm_enable = 1;/* default is set to enable the wmm. */
++
++#ifdef CONFIG_WMMPS_STA
++/* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */
++/* 0: NO_LIMIT, 1: TWO_MSDU, 2: FOUR_MSDU, 3: SIX_MSDU */
++int rtw_uapsd_max_sp = NO_LIMIT;
++/* BIT0: AC_VO UAPSD, BIT1: AC_VI UAPSD, BIT2: AC_BK UAPSD, BIT3: AC_BE UAPSD */
++int rtw_uapsd_ac_enable = 0x0;
++#endif /* CONFIG_WMMPS_STA */
++
++#if defined(CONFIG_RTL8814A)
++	int rtw_pwrtrim_enable = 2; /* disable kfree , rename to power trim disable */
++#elif defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)
++	/*PHYDM API, must enable by default*/
++	int rtw_pwrtrim_enable = 1;
++#else
++	int rtw_pwrtrim_enable = 0; /* Default Enalbe  power trim by efuse config */
++#endif
++
++#if CONFIG_TX_AC_LIFETIME
++uint rtw_tx_aclt_flags = CONFIG_TX_ACLT_FLAGS;
++module_param(rtw_tx_aclt_flags, uint, 0644);
++MODULE_PARM_DESC(rtw_tx_aclt_flags, "device TX AC queue packet lifetime control flags");
++
++static uint rtw_tx_aclt_conf_default[3] = CONFIG_TX_ACLT_CONF_DEFAULT;
++static uint rtw_tx_aclt_conf_default_num = 0;
++module_param_array(rtw_tx_aclt_conf_default, uint, &rtw_tx_aclt_conf_default_num, 0644);
++MODULE_PARM_DESC(rtw_tx_aclt_conf_default, "device TX AC queue lifetime config for default status");
++
++#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++static uint rtw_tx_aclt_conf_ap_m2u[3] = CONFIG_TX_ACLT_CONF_AP_M2U;
++static uint rtw_tx_aclt_conf_ap_m2u_num = 0;
++module_param_array(rtw_tx_aclt_conf_ap_m2u, uint, &rtw_tx_aclt_conf_ap_m2u_num, 0644);
++MODULE_PARM_DESC(rtw_tx_aclt_conf_ap_m2u, "device TX AC queue lifetime config for AP mode M2U status");
++#endif
++
++#ifdef CONFIG_RTW_MESH
++static uint rtw_tx_aclt_conf_mesh[3] = CONFIG_TX_ACLT_CONF_MESH;
++static uint rtw_tx_aclt_conf_mesh_num = 0;
++module_param_array(rtw_tx_aclt_conf_mesh, uint, &rtw_tx_aclt_conf_mesh_num, 0644);
++MODULE_PARM_DESC(rtw_tx_aclt_conf_mesh, "device TX AC queue lifetime config for MESH status");
++#endif
++#endif /* CONFIG_TX_AC_LIFETIME */
++
++uint rtw_tx_bw_mode = 0x21;
++module_param(rtw_tx_bw_mode, uint, 0644);
++MODULE_PARM_DESC(rtw_tx_bw_mode, "The max tx bw for 2.4G and 5G. format is the same as rtw_bw_mode");
++
++#ifdef CONFIG_FW_HANDLE_TXBCN
++uint rtw_tbtt_rpt = 0;	/*ROOT AP - BIT0, VAP1 - BIT1, VAP2 - BIT2, VAP3 - VAP3, FW report TBTT INT by C2H*/
++module_param(rtw_tbtt_rpt, uint, 0644);
++#endif
++
++#ifdef CONFIG_80211N_HT
++int rtw_ht_enable = 1;
++/* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz, 4: 80+80MHz
++* 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7
++* 0x21 means enable 2.4G 40MHz & 5G 80MHz */
++#ifdef CONFIG_RTW_CUSTOMIZE_BWMODE
++int rtw_bw_mode = CONFIG_RTW_CUSTOMIZE_BWMODE;
++#else
++int rtw_bw_mode = 0x21;
++#endif
++int rtw_ampdu_enable = 1;/* for enable tx_ampdu , */ /* 0: disable, 0x1:enable */
++int rtw_rx_stbc = 1;/* 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ */
++#if (defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8814B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)) && defined(CONFIG_PCI_HCI)
++int rtw_rx_ampdu_amsdu = 2;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */
++#elif ((defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)) && defined(CONFIG_SDIO_HCI))
++int rtw_rx_ampdu_amsdu = 1;
++#else
++int rtw_rx_ampdu_amsdu;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */
++#endif
++/*
++* 2: Follow the AMSDU filed in ADDBA Resp. (Deault)
++* 0: Force the AMSDU filed in ADDBA Resp. to be disabled.
++* 1: Force the AMSDU filed in ADDBA Resp. to be enabled.
++*/
++int rtw_tx_ampdu_amsdu = 2;
++
++int rtw_quick_addba_req = 0;
++
++static uint rtw_rx_ampdu_sz_limit_1ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS;
++static uint rtw_rx_ampdu_sz_limit_1ss_num = 0;
++module_param_array(rtw_rx_ampdu_sz_limit_1ss, uint, &rtw_rx_ampdu_sz_limit_1ss_num, 0644);
++MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_1ss, "RX AMPDU size limit for 1SS link of each BW, 0xFF: no limitation");
++
++static uint rtw_rx_ampdu_sz_limit_2ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS;
++static uint rtw_rx_ampdu_sz_limit_2ss_num = 0;
++module_param_array(rtw_rx_ampdu_sz_limit_2ss, uint, &rtw_rx_ampdu_sz_limit_2ss_num, 0644);
++MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_2ss, "RX AMPDU size limit for 2SS link of each BW, 0xFF: no limitation");
++
++static uint rtw_rx_ampdu_sz_limit_3ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS;
++static uint rtw_rx_ampdu_sz_limit_3ss_num = 0;
++module_param_array(rtw_rx_ampdu_sz_limit_3ss, uint, &rtw_rx_ampdu_sz_limit_3ss_num, 0644);
++MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_3ss, "RX AMPDU size limit for 3SS link of each BW, 0xFF: no limitation");
++
++static uint rtw_rx_ampdu_sz_limit_4ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS;
++static uint rtw_rx_ampdu_sz_limit_4ss_num = 0;
++module_param_array(rtw_rx_ampdu_sz_limit_4ss, uint, &rtw_rx_ampdu_sz_limit_4ss_num, 0644);
++MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_4ss, "RX AMPDU size limit for 4SS link of each BW, 0xFF: no limitation");
++
++/* Short GI support Bit Map
++* BIT0 - 20MHz, 0: non-support, 1: support
++* BIT1 - 40MHz, 0: non-support, 1: support
++* BIT2 - 80MHz, 0: non-support, 1: support
++* BIT3 - 160MHz, 0: non-support, 1: support */
++int rtw_short_gi = 0xf;
++/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */
++int rtw_ldpc_cap = 0x33;
++/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */
++int rtw_stbc_cap = 0x13;
++
++/*
++* BIT0: Enable VHT SU Beamformer
++* BIT1: Enable VHT SU Beamformee
++* BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer
++* BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee
++* BIT4: Enable HT Beamformer
++* BIT5: Enable HT Beamformee
++*/
++int rtw_beamform_cap = BIT(1) | BIT(3);
++int rtw_bfer_rf_number = 0; /*BeamformerCapRfNum Rf path number, 0 for auto, others for manual*/
++int rtw_bfee_rf_number = 0; /*BeamformeeCapRfNum  Rf path number, 0 for auto, others for manual*/
++
++#endif /* CONFIG_80211N_HT */
++
++#ifdef CONFIG_80211AC_VHT
++int rtw_vht_enable = 1; /* 0:disable, 1:enable, 2:force auto enable */
++module_param(rtw_vht_enable, int, 0644);
++
++int rtw_ampdu_factor = 7;
++
++uint rtw_vht_rx_mcs_map = 0xaaaa;
++module_param(rtw_vht_rx_mcs_map, uint, 0644);
++MODULE_PARM_DESC(rtw_vht_rx_mcs_map, "VHT RX MCS map");
++#endif /* CONFIG_80211AC_VHT */
++
++int rtw_lowrate_two_xmit = 1;/* Use 2 path Tx to transmit MCS0~7 and legacy mode */
++
++
++/* 0: not check in watch dog, 1: check in watch dog  */
++int rtw_check_hw_status = 0;
++
++int rtw_low_power = 0;
++int rtw_wifi_spec = 0;
++
++
++int rtw_trx_path_bmp = 0x00;
++module_param(rtw_trx_path_bmp, int, 0644); /* [7:4]TX path bmp, [0:3]RX path bmp, 0: not specified */
++
++#ifdef CONFIG_SPECIAL_RF_PATH /* configure Nss/xTxR IC to 1ss/1T1R */
++int rtw_tx_path_lmt = 1;
++int rtw_rx_path_lmt = 1;
++int rtw_tx_nss = 1;
++int rtw_rx_nss = 1;
++#elif defined(CONFIG_CUSTOMER01_SMART_ANTENNA)
++int rtw_tx_path_lmt = 2;
++int rtw_rx_path_lmt = 2;
++int rtw_tx_nss = 1;
++int rtw_rx_nss = 1;
++#else
++int rtw_tx_path_lmt = 0;
++int rtw_rx_path_lmt = 0;
++int rtw_tx_nss = 0;
++int rtw_rx_nss = 0;
++#endif
++module_param(rtw_tx_path_lmt, int, 0644); /* limit of TX path number, 0: not specified */
++module_param(rtw_rx_path_lmt, int, 0644); /* limit of RX path number, 0: not specified */
++module_param(rtw_tx_nss, int, 0644);
++module_param(rtw_rx_nss, int, 0644);
++
++char rtw_country_unspecified[] = {0xFF, 0xFF, 0x00};
++char *rtw_country_code = rtw_country_unspecified;
++module_param(rtw_country_code, charp, 0644);
++MODULE_PARM_DESC(rtw_country_code, "The default country code (in alpha2)");
++
++int rtw_channel_plan = CONFIG_RTW_CHPLAN;
++module_param(rtw_channel_plan, int, 0644);
++MODULE_PARM_DESC(rtw_channel_plan, "The default chplan ID when rtw_alpha2 is not specified or valid");
++
++static uint rtw_excl_chs[MAX_CHANNEL_NUM] = CONFIG_RTW_EXCL_CHS;
++static int rtw_excl_chs_num = 0;
++module_param_array(rtw_excl_chs, uint, &rtw_excl_chs_num, 0644);
++MODULE_PARM_DESC(rtw_excl_chs, "exclusive channel array");
++
++/*if concurrent softap + p2p(GO) is needed, this param lets p2p response full channel list.
++But Softap must be SHUT DOWN once P2P decide to set up connection and become a GO.*/
++#ifdef CONFIG_FULL_CH_IN_P2P_HANDSHAKE
++	int rtw_full_ch_in_p2p_handshake = 1; /* reply full channel list*/
++#else
++	int rtw_full_ch_in_p2p_handshake = 0; /* reply only softap channel*/
++#endif
++
++#ifdef CONFIG_BT_COEXIST
++int rtw_btcoex_enable = 2;
++module_param(rtw_btcoex_enable, int, 0644);
++MODULE_PARM_DESC(rtw_btcoex_enable, "BT co-existence on/off, 0:off, 1:on, 2:by efuse");
++
++int rtw_ant_num = 0;
++module_param(rtw_ant_num, int, 0644);
++MODULE_PARM_DESC(rtw_ant_num, "Antenna number setting, 0:by efuse");
++
++int rtw_bt_iso = 2;/* 0:Low, 1:High, 2:From Efuse */
++int rtw_bt_sco = 3;/* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy, 5.OtherBusy */
++int rtw_bt_ampdu = 1 ; /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
++#endif /* CONFIG_BT_COEXIST */
++
++int rtw_AcceptAddbaReq = _TRUE;/* 0:Reject AP's Add BA req, 1:Accept AP's Add BA req. */
++
++int rtw_antdiv_cfg = 2; /* 0:OFF , 1:ON, 2:decide by Efuse config */
++int rtw_antdiv_type = 0
++	; /* 0:decide by efuse  1: for 88EE, 1Tx and 1RxCG are diversity.(2 Ant with SPDT), 2:  for 88EE, 1Tx and 2Rx are diversity.( 2 Ant, Tx and RxCG are both on aux port, RxCS is on main port ), 3: for 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */
++
++int rtw_drv_ant_band_switch = 1; /* 0:OFF , 1:ON, Driver control antenna band switch*/
++
++int rtw_single_ant_path; /*0:main ant , 1:aux ant , Fixed single antenna path, default main ant*/
++
++/* 0: doesn't switch, 1: switch from usb2.0 to usb 3.0 2: switch from usb3.0 to usb 2.0 */
++int rtw_switch_usb_mode = 0;
++
++#ifdef CONFIG_USB_AUTOSUSPEND
++int rtw_enusbss = 1;/* 0:disable,1:enable */
++#else
++int rtw_enusbss = 0;/* 0:disable,1:enable */
++#endif
++
++int rtw_hwpdn_mode = 2; /* 0:disable,1:enable,2: by EFUSE config */
++
++#ifdef CONFIG_HW_PWRP_DETECTION
++int rtw_hwpwrp_detect = 1;
++#else
++int rtw_hwpwrp_detect = 0; /* HW power  ping detect 0:disable , 1:enable */
++#endif
++
++#ifdef CONFIG_USB_HCI
++int rtw_hw_wps_pbc = 1;
++#else
++int rtw_hw_wps_pbc = 0;
++#endif
++
++#ifdef CONFIG_80211D
++int rtw_80211d = 0;
++#endif
++
++#ifdef CONFIG_PCI_ASPM
++/* CLK_REQ:BIT0 L0s:BIT1 ASPM_L1:BIT2 L1Off:BIT3*/
++int	rtw_pci_aspm_enable = 0x5;
++#else
++int	rtw_pci_aspm_enable;
++#endif
++
++/*
++ * BIT [15:12] mask of ps mode
++ * BIT [11:8] val of ps mode
++ * BIT [7:4] mask of perf mode
++ * BIT [3:0] val of perf mode
++ *
++ * L0s:BIT[+0] L1:BIT[+1]
++ *
++ * 0x0030: change value only if perf mode
++ * 0x3300: change value only if ps mode
++ * 0x3330: change value in both perf and ps mode
++ */
++#ifdef CONFIG_PCI_DYNAMIC_ASPM
++#ifdef CONFIG_PCI_ASPM
++int rtw_pci_dynamic_aspm_linkctrl = 0x3330;
++#else
++int rtw_pci_dynamic_aspm_linkctrl = 0x0030;
++#endif
++#else
++int rtw_pci_dynamic_aspm_linkctrl = 0x0000;
++#endif
++module_param(rtw_pci_dynamic_aspm_linkctrl, int, 0644);
++
++#ifdef CONFIG_QOS_OPTIMIZATION
++int rtw_qos_opt_enable = 1; /* 0: disable,1:enable */
++#else
++int rtw_qos_opt_enable = 0; /* 0: disable,1:enable */
++#endif
++module_param(rtw_qos_opt_enable, int, 0644);
++
++#ifdef CONFIG_RTW_ACS
++int rtw_acs_auto_scan = 0; /*0:disable, 1:enable*/
++module_param(rtw_acs_auto_scan, int, 0644);
++
++int rtw_acs = 1;
++module_param(rtw_acs, int, 0644);
++#endif
++
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++int rtw_nm = 1;/*noise monitor*/
++module_param(rtw_nm, int, 0644);
++#endif
++
++char *ifname = "wlan%d";
++module_param(ifname, charp, 0644);
++MODULE_PARM_DESC(ifname, "The default name to allocate for first interface");
++
++#ifdef CONFIG_PLATFORM_ANDROID
++	char *if2name = "p2p%d";
++#else /* CONFIG_PLATFORM_ANDROID */
++	char *if2name = "wlan%d";
++#endif /* CONFIG_PLATFORM_ANDROID */
++module_param(if2name, charp, 0644);
++MODULE_PARM_DESC(if2name, "The default name to allocate for second interface");
++
++char *rtw_initmac = 0;  /* temp mac address if users want to use instead of the mac address in Efuse */
++
++#ifdef CONFIG_CONCURRENT_MODE
++
++	#if (CONFIG_IFACE_NUMBER > 2)
++		int rtw_virtual_iface_num = CONFIG_IFACE_NUMBER - 1;
++		module_param(rtw_virtual_iface_num, int, 0644);
++	#else
++		int rtw_virtual_iface_num = 1;
++	#endif
++
++#ifdef CONFIG_P2P
++	int rtw_sel_p2p_iface = IFACE_ID1;
++
++	module_param(rtw_sel_p2p_iface, int, 0644);
++
++#endif
++
++#endif
++
++#ifdef CONFIG_AP_MODE
++u8 rtw_bmc_tx_rate = MGN_UNKNOWN;
++
++#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++int rtw_ap_src_b2u_flags = CONFIG_RTW_AP_SRC_B2U_FLAGS;
++module_param(rtw_ap_src_b2u_flags, int, 0644);
++
++int rtw_ap_fwd_b2u_flags = CONFIG_RTW_AP_FWD_B2U_FLAGS;
++module_param(rtw_ap_fwd_b2u_flags, int, 0644);
++#endif /* CONFIG_RTW_AP_DATA_BMC_TO_UC */
++#endif /* CONFIG_AP_MODE */
++
++#ifdef CONFIG_RTW_MESH
++#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++int rtw_msrc_b2u_flags = CONFIG_RTW_MSRC_B2U_FLAGS;
++module_param(rtw_msrc_b2u_flags, int, 0644);
++
++int rtw_mfwd_b2u_flags = CONFIG_RTW_MFWD_B2U_FLAGS;
++module_param(rtw_mfwd_b2u_flags, int, 0644);
++#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */
++#endif /* CONFIG_RTW_MESH */
++
++#ifdef RTW_WOW_STA_MIX
++int rtw_wowlan_sta_mix_mode = 1;
++#else
++int rtw_wowlan_sta_mix_mode = 0;
++#endif
++module_param(rtw_wowlan_sta_mix_mode, int, 0644);
++module_param(rtw_pwrtrim_enable, int, 0644);
++module_param(rtw_initmac, charp, 0644);
++module_param(rtw_chip_version, int, 0644);
++module_param(rtw_rfintfs, int, 0644);
++module_param(rtw_lbkmode, int, 0644);
++module_param(rtw_network_mode, int, 0644);
++module_param(rtw_channel, int, 0644);
++module_param(rtw_mp_mode, int, 0644);
++module_param(rtw_wmm_enable, int, 0644);
++#ifdef CONFIG_WMMPS_STA
++module_param(rtw_uapsd_max_sp, int, 0644);
++module_param(rtw_uapsd_ac_enable, int, 0644);
++module_param(rtw_wmm_smart_ps, int, 0644);
++#endif /* CONFIG_WMMPS_STA */
++module_param(rtw_vrtl_carrier_sense, int, 0644);
++module_param(rtw_vcs_type, int, 0644);
++module_param(rtw_busy_thresh, int, 0644);
++
++#ifdef CONFIG_80211N_HT
++module_param(rtw_ht_enable, int, 0644);
++module_param(rtw_bw_mode, int, 0644);
++module_param(rtw_ampdu_enable, int, 0644);
++module_param(rtw_rx_stbc, int, 0644);
++module_param(rtw_rx_ampdu_amsdu, int, 0644);
++module_param(rtw_tx_ampdu_amsdu, int, 0644);
++module_param(rtw_quick_addba_req, int, 0644);
++#endif /* CONFIG_80211N_HT */
++
++#ifdef CONFIG_BEAMFORMING
++module_param(rtw_beamform_cap, int, 0644);
++#endif
++module_param(rtw_lowrate_two_xmit, int, 0644);
++
++module_param(rtw_power_mgnt, int, 0644);
++module_param(rtw_smart_ps, int, 0644);
++module_param(rtw_low_power, int, 0644);
++module_param(rtw_wifi_spec, int, 0644);
++
++module_param(rtw_full_ch_in_p2p_handshake, int, 0644);
++module_param(rtw_antdiv_cfg, int, 0644);
++module_param(rtw_antdiv_type, int, 0644);
++
++module_param(rtw_drv_ant_band_switch, int, 0644);
++module_param(rtw_single_ant_path, int, 0644);
++
++module_param(rtw_switch_usb_mode, int, 0644);
++
++module_param(rtw_enusbss, int, 0644);
++module_param(rtw_hwpdn_mode, int, 0644);
++module_param(rtw_hwpwrp_detect, int, 0644);
++
++module_param(rtw_hw_wps_pbc, int, 0644);
++module_param(rtw_check_hw_status, int, 0644);
++
++#ifdef CONFIG_PCI_HCI
++module_param(rtw_pci_aspm_enable, int, 0644);
++#endif
++
++#ifdef CONFIG_TX_EARLY_MODE
++module_param(rtw_early_mode, int, 0644);
++#endif
++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
++char *rtw_adaptor_info_caching_file_path = "/data/misc/wifi/rtw_cache";
++module_param(rtw_adaptor_info_caching_file_path, charp, 0644);
++MODULE_PARM_DESC(rtw_adaptor_info_caching_file_path, "The path of adapter info cache file");
++#endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */
++
++#ifdef CONFIG_LAYER2_ROAMING
++uint rtw_max_roaming_times = 2;
++module_param(rtw_max_roaming_times, uint, 0644);
++MODULE_PARM_DESC(rtw_max_roaming_times, "The max roaming times to try");
++#endif /* CONFIG_LAYER2_ROAMING */
++
++#ifdef CONFIG_IOL
++int rtw_fw_iol = 1;
++module_param(rtw_fw_iol, int, 0644);
++MODULE_PARM_DESC(rtw_fw_iol, "FW IOL. 0:Disable, 1:enable, 2:by usb speed");
++#endif /* CONFIG_IOL */
++
++#ifdef CONFIG_FILE_FWIMG
++char *rtw_fw_file_path = "/system/etc/firmware/rtlwifi/FW_NIC.BIN";
++module_param(rtw_fw_file_path, charp, 0644);
++MODULE_PARM_DESC(rtw_fw_file_path, "The path of fw image");
++
++char *rtw_fw_wow_file_path = "/system/etc/firmware/rtlwifi/FW_WoWLAN.BIN";
++module_param(rtw_fw_wow_file_path, charp, 0644);
++MODULE_PARM_DESC(rtw_fw_wow_file_path, "The path of fw for Wake on Wireless image");
++
++#ifdef CONFIG_MP_INCLUDED
++char *rtw_fw_mp_bt_file_path = "";
++module_param(rtw_fw_mp_bt_file_path, charp, 0644);
++MODULE_PARM_DESC(rtw_fw_mp_bt_file_path, "The path of fw for MP-BT image");
++#endif /* CONFIG_MP_INCLUDED */
++#endif /* CONFIG_FILE_FWIMG */
++
++#ifdef CONFIG_80211D
++module_param(rtw_80211d, int, 0644);
++MODULE_PARM_DESC(rtw_80211d, "Enable 802.11d mechanism");
++#endif
++
++#ifdef CONFIG_ADVANCE_OTA
++/*	BIT(0): OTA continuous rotated test within low RSSI,1R CCA in path B
++	BIT(1) & BIT(2): OTA continuous rotated test with low high RSSI */
++/* Experimental environment: shielding room with half of absorber and 2~3 rotation per minute */
++int rtw_advnace_ota;
++module_param(rtw_advnace_ota, int, 0644);
++#endif
++
++uint rtw_notch_filter = RTW_NOTCH_FILTER;
++module_param(rtw_notch_filter, uint, 0644);
++MODULE_PARM_DESC(rtw_notch_filter, "0:Disable, 1:Enable, 2:Enable only for P2P");
++
++uint rtw_hiq_filter = CONFIG_RTW_HIQ_FILTER;
++module_param(rtw_hiq_filter, uint, 0644);
++MODULE_PARM_DESC(rtw_hiq_filter, "0:allow all, 1:allow special, 2:deny all");
++
++uint rtw_adaptivity_en = CONFIG_RTW_ADAPTIVITY_EN;
++module_param(rtw_adaptivity_en, uint, 0644);
++MODULE_PARM_DESC(rtw_adaptivity_en, "0:disable, 1:enable");
++
++uint rtw_adaptivity_mode = CONFIG_RTW_ADAPTIVITY_MODE;
++module_param(rtw_adaptivity_mode, uint, 0644);
++MODULE_PARM_DESC(rtw_adaptivity_mode, "0:normal, 1:carrier sense");
++
++int rtw_adaptivity_th_l2h_ini = CONFIG_RTW_ADAPTIVITY_TH_L2H_INI;
++module_param(rtw_adaptivity_th_l2h_ini, int, 0644);
++MODULE_PARM_DESC(rtw_adaptivity_th_l2h_ini, "th_l2h_ini for Adaptivity");
++
++int rtw_adaptivity_th_edcca_hl_diff = CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF;
++module_param(rtw_adaptivity_th_edcca_hl_diff, int, 0644);
++MODULE_PARM_DESC(rtw_adaptivity_th_edcca_hl_diff, "th_edcca_hl_diff for Adaptivity");
++
++#ifdef CONFIG_DFS_MASTER
++uint rtw_dfs_region_domain = CONFIG_RTW_DFS_REGION_DOMAIN;
++module_param(rtw_dfs_region_domain, uint, 0644);
++MODULE_PARM_DESC(rtw_dfs_region_domain, "0:UNKNOWN, 1:FCC, 2:MKK, 3:ETSI");
++#endif
++
++uint rtw_amplifier_type_2g = CONFIG_RTW_AMPLIFIER_TYPE_2G;
++module_param(rtw_amplifier_type_2g, uint, 0644);
++MODULE_PARM_DESC(rtw_amplifier_type_2g, "BIT3:2G ext-PA, BIT4:2G ext-LNA");
++
++uint rtw_amplifier_type_5g = CONFIG_RTW_AMPLIFIER_TYPE_5G;
++module_param(rtw_amplifier_type_5g, uint, 0644);
++MODULE_PARM_DESC(rtw_amplifier_type_5g, "BIT6:5G ext-PA, BIT7:5G ext-LNA");
++
++uint rtw_RFE_type = CONFIG_RTW_RFE_TYPE;
++module_param(rtw_RFE_type, uint, 0644);
++MODULE_PARM_DESC(rtw_RFE_type, "default init value:64");
++
++uint rtw_powertracking_type = 64;
++module_param(rtw_powertracking_type, uint, 0644);
++MODULE_PARM_DESC(rtw_powertracking_type, "default init value:64");
++
++uint rtw_GLNA_type = CONFIG_RTW_GLNA_TYPE;
++module_param(rtw_GLNA_type, uint, 0644);
++MODULE_PARM_DESC(rtw_GLNA_type, "default init value:0");
++
++uint rtw_TxBBSwing_2G = 0xFF;
++module_param(rtw_TxBBSwing_2G, uint, 0644);
++MODULE_PARM_DESC(rtw_TxBBSwing_2G, "default init value:0xFF");
++
++uint rtw_TxBBSwing_5G = 0xFF;
++module_param(rtw_TxBBSwing_5G, uint, 0644);
++MODULE_PARM_DESC(rtw_TxBBSwing_5G, "default init value:0xFF");
++
++uint rtw_OffEfuseMask = 0;
++module_param(rtw_OffEfuseMask, uint, 0644);
++MODULE_PARM_DESC(rtw_OffEfuseMask, "default open Efuse Mask value:0");
++
++uint rtw_FileMaskEfuse = 0;
++module_param(rtw_FileMaskEfuse, uint, 0644);
++MODULE_PARM_DESC(rtw_FileMaskEfuse, "default drv Mask Efuse value:0");
++
++uint rtw_rxgain_offset_2g = 0;
++module_param(rtw_rxgain_offset_2g, uint, 0644);
++MODULE_PARM_DESC(rtw_rxgain_offset_2g, "default RF Gain 2G Offset value:0");
++
++uint rtw_rxgain_offset_5gl = 0;
++module_param(rtw_rxgain_offset_5gl, uint, 0644);
++MODULE_PARM_DESC(rtw_rxgain_offset_5gl, "default RF Gain 5GL Offset value:0");
++
++uint rtw_rxgain_offset_5gm = 0;
++module_param(rtw_rxgain_offset_5gm, uint, 0644);
++MODULE_PARM_DESC(rtw_rxgain_offset_5gm, "default RF Gain 5GM Offset value:0");
++
++uint rtw_rxgain_offset_5gh = 0;
++module_param(rtw_rxgain_offset_5gh, uint, 0644);
++MODULE_PARM_DESC(rtw_rxgain_offset_5gm, "default RF Gain 5GL Offset value:0");
++
++uint rtw_pll_ref_clk_sel = CONFIG_RTW_PLL_REF_CLK_SEL;
++module_param(rtw_pll_ref_clk_sel, uint, 0644);
++MODULE_PARM_DESC(rtw_pll_ref_clk_sel, "force pll_ref_clk_sel, 0xF:use autoload value");
++
++int rtw_tx_pwr_by_rate = CONFIG_TXPWR_BY_RATE_EN;
++module_param(rtw_tx_pwr_by_rate, int, 0644);
++MODULE_PARM_DESC(rtw_tx_pwr_by_rate, "0:Disable, 1:Enable, 2: Depend on efuse");
++
++#if CONFIG_TXPWR_LIMIT
++int rtw_tx_pwr_lmt_enable = CONFIG_TXPWR_LIMIT_EN;
++module_param(rtw_tx_pwr_lmt_enable, int, 0644);
++MODULE_PARM_DESC(rtw_tx_pwr_lmt_enable, "0:Disable, 1:Enable, 2: Depend on efuse");
++#endif
++
++static int rtw_target_tx_pwr_2g_a[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_A;
++static int rtw_target_tx_pwr_2g_a_num = 0;
++module_param_array(rtw_target_tx_pwr_2g_a, int, &rtw_target_tx_pwr_2g_a_num, 0644);
++MODULE_PARM_DESC(rtw_target_tx_pwr_2g_a, "2.4G target tx power (unit:dBm) of RF path A for each rate section, should match the real calibrate power, -1: undefined");
++
++static int rtw_target_tx_pwr_2g_b[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_B;
++static int rtw_target_tx_pwr_2g_b_num = 0;
++module_param_array(rtw_target_tx_pwr_2g_b, int, &rtw_target_tx_pwr_2g_b_num, 0644);
++MODULE_PARM_DESC(rtw_target_tx_pwr_2g_b, "2.4G target tx power (unit:dBm) of RF path B for each rate section, should match the real calibrate power, -1: undefined");
++
++static int rtw_target_tx_pwr_2g_c[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_C;
++static int rtw_target_tx_pwr_2g_c_num = 0;
++module_param_array(rtw_target_tx_pwr_2g_c, int, &rtw_target_tx_pwr_2g_c_num, 0644);
++MODULE_PARM_DESC(rtw_target_tx_pwr_2g_c, "2.4G target tx power (unit:dBm) of RF path C for each rate section, should match the real calibrate power, -1: undefined");
++
++static int rtw_target_tx_pwr_2g_d[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_D;
++static int rtw_target_tx_pwr_2g_d_num = 0;
++module_param_array(rtw_target_tx_pwr_2g_d, int, &rtw_target_tx_pwr_2g_d_num, 0644);
++MODULE_PARM_DESC(rtw_target_tx_pwr_2g_d, "2.4G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined");
++
++#if CONFIG_IEEE80211_BAND_5GHZ
++static int rtw_target_tx_pwr_5g_a[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_A;
++static int rtw_target_tx_pwr_5g_a_num = 0;
++module_param_array(rtw_target_tx_pwr_5g_a, int, &rtw_target_tx_pwr_5g_a_num, 0644);
++MODULE_PARM_DESC(rtw_target_tx_pwr_5g_a, "5G target tx power (unit:dBm) of RF path A for each rate section, should match the real calibrate power, -1: undefined");
++
++static int rtw_target_tx_pwr_5g_b[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_B;
++static int rtw_target_tx_pwr_5g_b_num = 0;
++module_param_array(rtw_target_tx_pwr_5g_b, int, &rtw_target_tx_pwr_5g_b_num, 0644);
++MODULE_PARM_DESC(rtw_target_tx_pwr_5g_b, "5G target tx power (unit:dBm) of RF path B for each rate section, should match the real calibrate power, -1: undefined");
++
++static int rtw_target_tx_pwr_5g_c[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_C;
++static int rtw_target_tx_pwr_5g_c_num = 0;
++module_param_array(rtw_target_tx_pwr_5g_c, int, &rtw_target_tx_pwr_5g_c_num, 0644);
++MODULE_PARM_DESC(rtw_target_tx_pwr_5g_c, "5G target tx power (unit:dBm) of RF path C for each rate section, should match the real calibrate power, -1: undefined");
++
++static int rtw_target_tx_pwr_5g_d[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_D;
++static int rtw_target_tx_pwr_5g_d_num = 0;
++module_param_array(rtw_target_tx_pwr_5g_d, int, &rtw_target_tx_pwr_5g_d_num, 0644);
++MODULE_PARM_DESC(rtw_target_tx_pwr_5g_d, "5G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined");
++#endif /* CONFIG_IEEE80211_BAND_5GHZ */
++
++#ifdef CONFIG_RTW_TX_NPATH_EN
++/*0:disable ,1: 2path*/
++int rtw_tx_npath_enable = 1;
++module_param(rtw_tx_npath_enable, int, 0644);
++MODULE_PARM_DESC(rtw_tx_npath_enable, "0:Disable, 1:TX-2PATH");
++#endif
++
++#ifdef CONFIG_RTW_PATH_DIV
++/*0:disable ,1: path diversity*/
++int rtw_path_div_enable = 1;
++module_param(rtw_path_div_enable, int, 0644);
++MODULE_PARM_DESC(rtw_path_div_enable, "0:Disable, 1:Enable path diversity");
++#endif
++
++
++int rtw_tsf_update_pause_factor = CONFIG_TSF_UPDATE_PAUSE_FACTOR;
++module_param(rtw_tsf_update_pause_factor, int, 0644);
++MODULE_PARM_DESC(rtw_tsf_update_pause_factor, "num of bcn intervals to stay TSF update pause status");
++
++int rtw_tsf_update_restore_factor = CONFIG_TSF_UPDATE_RESTORE_FACTOR;
++module_param(rtw_tsf_update_restore_factor, int, 0644);
++MODULE_PARM_DESC(rtw_tsf_update_restore_factor, "num of bcn intervals to stay TSF update restore status");
++
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++char *rtw_phy_file_path = REALTEK_CONFIG_PATH;
++module_param(rtw_phy_file_path, charp, 0644);
++MODULE_PARM_DESC(rtw_phy_file_path, "The path of phy parameter");
++/* PHY FILE Bit Map
++* BIT0 - MAC,				0: non-support, 1: support
++* BIT1 - BB,					0: non-support, 1: support
++* BIT2 - BB_PG,				0: non-support, 1: support
++* BIT3 - BB_MP,				0: non-support, 1: support
++* BIT4 - RF,					0: non-support, 1: support
++* BIT5 - RF_TXPWR_TRACK,	0: non-support, 1: support
++* BIT6 - RF_TXPWR_LMT,		0: non-support, 1: support */
++int rtw_load_phy_file = (BIT2 | BIT6);
++module_param(rtw_load_phy_file, int, 0644);
++MODULE_PARM_DESC(rtw_load_phy_file, "PHY File Bit Map");
++int rtw_decrypt_phy_file = 0;
++module_param(rtw_decrypt_phy_file, int, 0644);
++MODULE_PARM_DESC(rtw_decrypt_phy_file, "Enable Decrypt PHY File");
++#endif
++
++#ifdef CONFIG_SUPPORT_TRX_SHARED
++#ifdef DFT_TRX_SHARE_MODE
++int rtw_trx_share_mode = DFT_TRX_SHARE_MODE;
++#else
++int rtw_trx_share_mode = 0;
++#endif
++module_param(rtw_trx_share_mode, int, 0644);
++MODULE_PARM_DESC(rtw_trx_share_mode, "TRx FIFO Shared");
++#endif
++
++#ifdef CONFIG_DYNAMIC_SOML
++uint rtw_dynamic_soml_en = 1;
++module_param(rtw_dynamic_soml_en, int, 0644);
++MODULE_PARM_DESC(rtw_dynamic_soml_en, "0: disable, 1: enable with default param, 2: enable with specified param.");
++
++uint rtw_dynamic_soml_train_num = 0;
++module_param(rtw_dynamic_soml_train_num, int, 0644);
++MODULE_PARM_DESC(rtw_dynamic_soml_train_num, "SOML training number");
++
++uint rtw_dynamic_soml_interval = 0;
++module_param(rtw_dynamic_soml_interval, int, 0644);
++MODULE_PARM_DESC(rtw_dynamic_soml_interval, "SOML training interval");
++
++uint rtw_dynamic_soml_period = 0;
++module_param(rtw_dynamic_soml_period, int, 0644);
++MODULE_PARM_DESC(rtw_dynamic_soml_period, "SOML training period");
++
++uint rtw_dynamic_soml_delay = 0;
++module_param(rtw_dynamic_soml_delay, int, 0644);
++MODULE_PARM_DESC(rtw_dynamic_soml_delay, "SOML training delay");
++#endif
++
++uint rtw_phydm_ability = 0xffffffff;
++module_param(rtw_phydm_ability, uint, 0644);
++
++uint rtw_halrf_ability = 0xffffffff;
++module_param(rtw_halrf_ability, uint, 0644);
++
++#ifdef CONFIG_RTW_MESH
++uint rtw_peer_alive_based_preq = 1;
++module_param(rtw_peer_alive_based_preq, uint, 0644);
++MODULE_PARM_DESC(rtw_peer_alive_based_preq,
++	"On demand PREQ will reference peer alive status. 0: Off, 1: On");
++#endif
++
++int _netdev_open(struct net_device *pnetdev);
++int netdev_open(struct net_device *pnetdev);
++static int netdev_close(struct net_device *pnetdev);
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++extern int rtw_sdio_set_power(int on);
++#endif /* CONFIG_PLATFORM_INTEL_BYT */
++
++#ifdef CONFIG_MCC_MODE
++/* enable MCC mode or not */
++int rtw_en_mcc = 1;
++/* can referece following value before insmod driver */
++int rtw_mcc_ap_bw20_target_tx_tp = MCC_AP_BW20_TARGET_TX_TP;
++int rtw_mcc_ap_bw40_target_tx_tp = MCC_AP_BW40_TARGET_TX_TP;
++int rtw_mcc_ap_bw80_target_tx_tp = MCC_AP_BW80_TARGET_TX_TP;
++int rtw_mcc_sta_bw20_target_tx_tp = MCC_STA_BW20_TARGET_TX_TP;
++int rtw_mcc_sta_bw40_target_tx_tp = MCC_STA_BW40_TARGET_TX_TP;
++int rtw_mcc_sta_bw80_target_tx_tp = MCC_STA_BW80_TARGET_TX_TP;
++int rtw_mcc_single_tx_cri = MCC_SINGLE_TX_CRITERIA;
++int rtw_mcc_policy_table_idx = 0;
++int rtw_mcc_duration = 0;
++int rtw_mcc_enable_runtime_duration = 1;
++#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++int rtw_mcc_phydm_offload = 1;
++#else
++int rtw_mcc_phydm_offload = 0;
++#endif
++module_param(rtw_en_mcc, int, 0644);
++module_param(rtw_mcc_single_tx_cri, int, 0644);
++module_param(rtw_mcc_ap_bw20_target_tx_tp, int, 0644);
++module_param(rtw_mcc_ap_bw40_target_tx_tp, int, 0644);
++module_param(rtw_mcc_ap_bw80_target_tx_tp, int, 0644);
++module_param(rtw_mcc_sta_bw20_target_tx_tp, int, 0644);
++module_param(rtw_mcc_sta_bw40_target_tx_tp, int, 0644);
++module_param(rtw_mcc_sta_bw80_target_tx_tp, int, 0644);
++module_param(rtw_mcc_policy_table_idx, int, 0644);
++module_param(rtw_mcc_duration, int, 0644);
++module_param(rtw_mcc_phydm_offload, int, 0644);
++#endif /*CONFIG_MCC_MODE */
++
++#ifdef CONFIG_RTW_NAPI
++/*following setting should define NAPI in Makefile
++enable napi only = 1, disable napi = 0*/
++int rtw_en_napi = 1;
++module_param(rtw_en_napi, int, 0644);
++#ifdef CONFIG_RTW_NAPI_DYNAMIC
++int rtw_napi_threshold = 100; /* unit: Mbps */
++module_param(rtw_napi_threshold, int, 0644);
++#endif /* CONFIG_RTW_NAPI_DYNAMIC */
++#ifdef CONFIG_RTW_GRO
++/*following setting should define GRO in Makefile
++enable gro = 1, disable gro = 0*/
++int rtw_en_gro = 1;
++module_param(rtw_en_gro, int, 0644);
++#endif /* CONFIG_RTW_GRO */
++#endif /* CONFIG_RTW_NAPI */
++
++#ifdef RTW_IQK_FW_OFFLOAD
++int rtw_iqk_fw_offload = 1;
++#else
++int rtw_iqk_fw_offload;
++#endif /* RTW_IQK_FW_OFFLOAD */
++module_param(rtw_iqk_fw_offload, int, 0644);
++
++#ifdef RTW_CHANNEL_SWITCH_OFFLOAD
++int rtw_ch_switch_offload = 0;
++#else
++int rtw_ch_switch_offload;
++#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
++module_param(rtw_ch_switch_offload, int, 0644);
++
++#ifdef CONFIG_TDLS
++int rtw_en_tdls = 1;
++module_param(rtw_en_tdls, int, 0644);
++#endif
++
++#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
++int rtw_fw_param_init = 1;
++module_param(rtw_fw_param_init, int, 0644);
++#endif
++
++#ifdef CONFIG_TDMADIG
++int rtw_tdmadig_en = 1;
++/*
++1:MODE_PERFORMANCE
++2:MODE_COVERAGE
++*/
++int rtw_tdmadig_mode = 1;
++int rtw_dynamic_tdmadig = 0;
++module_param(rtw_tdmadig_en, int, 0644);
++module_param(rtw_tdmadig_mode, int, 0644);
++module_param(rtw_dynamic_tdmadig, int, 0644);
++#endif/*CONFIG_TDMADIG*/
++
++/*dynamic RRSR default enable*/
++int rtw_en_dyn_rrsr = 1;
++int rtw_rrsr_value = 0xFFFFFFFF;
++module_param(rtw_en_dyn_rrsr, int, 0644);
++module_param(rtw_rrsr_value, int, 0644);
++
++#ifdef CONFIG_WOWLAN
++/*
++ * 0: disable, 1: enable
++ */
++uint rtw_wow_enable = 1;
++module_param(rtw_wow_enable, uint, 0644);
++/*
++ * bit[0]: magic packet wake up
++ * bit[1]: unucast packet(HW/FW unuicast)
++ * bit[2]: deauth wake up
++ */
++uint rtw_wakeup_event = RTW_WAKEUP_EVENT;
++module_param(rtw_wakeup_event, uint, 0644);
++/*
++ * 0: common WOWLAN
++ * bit[0]: disable BB RF
++ * bit[1]: For wireless remote controller with or without connection
++ */
++uint rtw_suspend_type = RTW_SUSPEND_TYPE;
++module_param(rtw_suspend_type, uint, 0644);
++#endif
++
++#ifdef RTW_BUSY_DENY_SCAN
++uint rtw_scan_interval_thr = BUSY_TRAFFIC_SCAN_DENY_PERIOD;
++module_param(rtw_scan_interval_thr, uint, 0644);
++MODULE_PARM_DESC(rtw_scan_interval_thr, "Threshold used to judge if scan " \
++		 "request comes from scan UI, unit is ms.");
++#endif /* RTW_BUSY_DENY_SCAN */
++
++#ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY
++uint rtw_8822c_xcap_overwrite = 1;
++module_param(rtw_8822c_xcap_overwrite, uint, 0644);
++#endif
++
++#if CONFIG_TX_AC_LIFETIME
++static void rtw_regsty_load_tx_ac_lifetime(struct registry_priv *regsty)
++{
++	int i, j;
++	struct tx_aclt_conf_t *conf;
++	uint *parm;
++
++	regsty->tx_aclt_flags = (u8)rtw_tx_aclt_flags;
++
++	for (i = 0; i < TX_ACLT_CONF_NUM; i++) {
++		conf = &regsty->tx_aclt_confs[i];
++		if (i == TX_ACLT_CONF_DEFAULT)
++			parm = rtw_tx_aclt_conf_default;
++		#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++		else if (i == TX_ACLT_CONF_AP_M2U)
++			parm = rtw_tx_aclt_conf_ap_m2u;
++		#endif
++		#ifdef CONFIG_RTW_MESH
++		else if (i == TX_ACLT_CONF_MESH)
++			parm = rtw_tx_aclt_conf_mesh;
++		#endif
++		else
++			parm = NULL;
++
++		if (parm) {
++			conf->en = parm[0] & 0xF;
++			conf->vo_vi = parm[1];
++			conf->be_bk = parm[2];
++		}	
++	}
++}
++#endif
++
++void rtw_regsty_load_target_tx_power(struct registry_priv *regsty)
++{
++	int path, rs;
++	int *target_tx_pwr;
++
++	for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
++		if (path == RF_PATH_A)
++			target_tx_pwr = rtw_target_tx_pwr_2g_a;
++		else if (path == RF_PATH_B)
++			target_tx_pwr = rtw_target_tx_pwr_2g_b;
++		else if (path == RF_PATH_C)
++			target_tx_pwr = rtw_target_tx_pwr_2g_c;
++		else if (path == RF_PATH_D)
++			target_tx_pwr = rtw_target_tx_pwr_2g_d;
++
++		for (rs = CCK; rs < RATE_SECTION_NUM; rs++)
++			regsty->target_tx_pwr_2g[path][rs] = target_tx_pwr[rs];
++	}
++
++#if CONFIG_IEEE80211_BAND_5GHZ
++	for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
++		if (path == RF_PATH_A)
++			target_tx_pwr = rtw_target_tx_pwr_5g_a;
++		else if (path == RF_PATH_B)
++			target_tx_pwr = rtw_target_tx_pwr_5g_b;
++		else if (path == RF_PATH_C)
++			target_tx_pwr = rtw_target_tx_pwr_5g_c;
++		else if (path == RF_PATH_D)
++			target_tx_pwr = rtw_target_tx_pwr_5g_d;
++
++		for (rs = OFDM; rs < RATE_SECTION_NUM; rs++)
++			regsty->target_tx_pwr_5g[path][rs - 1] = target_tx_pwr[rs - 1];
++	}
++#endif /* CONFIG_IEEE80211_BAND_5GHZ */
++}
++
++inline void rtw_regsty_load_excl_chs(struct registry_priv *regsty)
++{
++	int i;
++	int ch_num = 0;
++
++	for (i = 0; i < MAX_CHANNEL_NUM; i++)
++		if (((u8)rtw_excl_chs[i]) != 0)
++			regsty->excl_chs[ch_num++] = (u8)rtw_excl_chs[i];
++
++	if (ch_num < MAX_CHANNEL_NUM)
++		regsty->excl_chs[ch_num] = 0;
++}
++
++#ifdef CONFIG_80211N_HT
++inline void rtw_regsty_init_rx_ampdu_sz_limit(struct registry_priv *regsty)
++{
++	int i, j;
++	uint *sz_limit;
++
++	for (i = 0; i < 4; i++) {
++		if (i == 0)
++			sz_limit = rtw_rx_ampdu_sz_limit_1ss;
++		else if (i == 1)
++			sz_limit = rtw_rx_ampdu_sz_limit_2ss;
++		else if (i == 2)
++			sz_limit = rtw_rx_ampdu_sz_limit_3ss;
++		else if (i == 3)
++			sz_limit = rtw_rx_ampdu_sz_limit_4ss;
++
++		for (j = 0; j < 4; j++)
++			regsty->rx_ampdu_sz_limit_by_nss_bw[i][j] = sz_limit[j];
++	}
++}
++#endif /* CONFIG_80211N_HT */
++
++uint loadparam(_adapter *padapter)
++{
++	uint status = _SUCCESS;
++	struct registry_priv  *registry_par = &padapter->registrypriv;
++
++
++#ifdef CONFIG_RTW_DEBUG
++	if (rtw_drv_log_level >= _DRV_MAX_)
++		rtw_drv_log_level = _DRV_DEBUG_;
++#endif
++
++	registry_par->chip_version = (u8)rtw_chip_version;
++	registry_par->rfintfs = (u8)rtw_rfintfs;
++	registry_par->lbkmode = (u8)rtw_lbkmode;
++	/* registry_par->hci = (u8)hci; */
++	registry_par->network_mode  = (u8)rtw_network_mode;
++
++	_rtw_memcpy(registry_par->ssid.Ssid, "ANY", 3);
++	registry_par->ssid.SsidLength = 3;
++
++	registry_par->channel = (u8)rtw_channel;
++#ifdef CONFIG_NARROWBAND_SUPPORTING
++	if (rtw_nb_config != RTW_NB_CONFIG_NONE)
++		rtw_wireless_mode &= ~WIRELESS_11B;
++#endif
++	registry_par->wireless_mode = (u8)rtw_wireless_mode;
++
++	if (IsSupported24G(registry_par->wireless_mode) && (!is_supported_5g(registry_par->wireless_mode))
++	    && (registry_par->channel > 14))
++		registry_par->channel = 1;
++	else if (is_supported_5g(registry_par->wireless_mode) && (!IsSupported24G(registry_par->wireless_mode))
++		 && (registry_par->channel <= 14))
++		registry_par->channel = 36;
++
++	registry_par->vrtl_carrier_sense = (u8)rtw_vrtl_carrier_sense ;
++	registry_par->vcs_type = (u8)rtw_vcs_type;
++	registry_par->rts_thresh = (u16)rtw_rts_thresh;
++	registry_par->frag_thresh = (u16)rtw_frag_thresh;
++	registry_par->preamble = (u8)rtw_preamble;
++	registry_par->scan_mode = (u8)rtw_scan_mode;
++	registry_par->smart_ps = (u8)rtw_smart_ps;
++	registry_par->check_fw_ps = (u8)rtw_check_fw_ps;
++	#ifdef CONFIG_TDMADIG
++		registry_par->tdmadig_en = (u8)rtw_tdmadig_en;
++		registry_par->tdmadig_mode = (u8)rtw_tdmadig_mode;
++		registry_par->tdmadig_dynamic = (u8) rtw_dynamic_tdmadig;
++		registry_par->power_mgnt = PS_MODE_ACTIVE;
++		registry_par->ips_mode = IPS_NONE;
++	#else
++		registry_par->power_mgnt = (u8)rtw_power_mgnt;
++		registry_par->ips_mode = (u8)rtw_ips_mode;
++	#endif/*CONFIG_TDMADIG*/
++	registry_par->lps_level = (u8)rtw_lps_level;
++	registry_par->en_dyn_rrsr = (u8)rtw_en_dyn_rrsr;
++	registry_par->set_rrsr_value = (u32)rtw_rrsr_value;
++#ifdef CONFIG_LPS_1T1R
++	registry_par->lps_1t1r = (u8)(rtw_lps_1t1r ? 1 : 0);
++#endif
++	registry_par->lps_chk_by_tp = (u8)rtw_lps_chk_by_tp;
++#ifdef CONFIG_WOWLAN
++	registry_par->wow_power_mgnt = (u8)rtw_wow_power_mgnt;
++	registry_par->wow_lps_level = (u8)rtw_wow_lps_level;
++	#ifdef CONFIG_LPS_1T1R
++	registry_par->wow_lps_1t1r = (u8)(rtw_wow_lps_1t1r ? 1 : 0);
++	#endif
++#endif /* CONFIG_WOWLAN */
++	registry_par->radio_enable = (u8)rtw_radio_enable;
++	registry_par->long_retry_lmt = (u8)rtw_long_retry_lmt;
++	registry_par->short_retry_lmt = (u8)rtw_short_retry_lmt;
++	registry_par->busy_thresh = (u16)rtw_busy_thresh;
++	registry_par->max_bss_cnt = (u16)rtw_max_bss_cnt;
++	/* registry_par->qos_enable = (u8)rtw_qos_enable; */
++	registry_par->ack_policy = (u8)rtw_ack_policy;
++	registry_par->mp_mode = (u8)rtw_mp_mode;
++#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)
++	registry_par->mp_customer_str = (u8)rtw_mp_customer_str;
++#endif
++	registry_par->software_encrypt = (u8)rtw_software_encrypt;
++	registry_par->software_decrypt = (u8)rtw_software_decrypt;
++
++	registry_par->acm_method = (u8)rtw_acm_method;
++	registry_par->usb_rxagg_mode = (u8)rtw_usb_rxagg_mode;
++	registry_par->dynamic_agg_enable = (u8)rtw_dynamic_agg_enable;
++
++	/* WMM */
++	registry_par->wmm_enable = (u8)rtw_wmm_enable;
++
++#ifdef CONFIG_WMMPS_STA
++	/* UAPSD */
++	registry_par->uapsd_max_sp_len= (u8)rtw_uapsd_max_sp;
++	registry_par->uapsd_ac_enable = (u8)rtw_uapsd_ac_enable;
++	registry_par->wmm_smart_ps = (u8)rtw_wmm_smart_ps;
++#endif /* CONFIG_WMMPS_STA */
++
++	registry_par->RegPwrTrimEnable = (u8)rtw_pwrtrim_enable;
++
++#if CONFIG_TX_AC_LIFETIME
++	rtw_regsty_load_tx_ac_lifetime(registry_par);
++#endif
++
++	registry_par->tx_bw_mode = (u8)rtw_tx_bw_mode;
++
++#ifdef CONFIG_80211N_HT
++	registry_par->ht_enable = (u8)rtw_ht_enable;
++	if (registry_par->ht_enable && is_supported_ht(registry_par->wireless_mode)) {
++#ifdef CONFIG_NARROWBAND_SUPPORTING
++	if (rtw_nb_config != RTW_NB_CONFIG_NONE)
++		rtw_bw_mode = 0;
++#endif
++		registry_par->bw_mode = (u8)rtw_bw_mode;
++		registry_par->ampdu_enable = (u8)rtw_ampdu_enable;
++		registry_par->rx_stbc = (u8)rtw_rx_stbc;
++		registry_par->rx_ampdu_amsdu = (u8)rtw_rx_ampdu_amsdu;
++		registry_par->tx_ampdu_amsdu = (u8)rtw_tx_ampdu_amsdu;
++		registry_par->tx_quick_addba_req = (u8)rtw_quick_addba_req;
++		registry_par->short_gi = (u8)rtw_short_gi;
++		registry_par->ldpc_cap = (u8)rtw_ldpc_cap;
++#if defined(CONFIG_CUSTOMER01_SMART_ANTENNA)
++		rtw_stbc_cap = 0x0;
++#endif
++#ifdef CONFIG_RTW_TX_NPATH_EN
++		registry_par->tx_npath = (u8)rtw_tx_npath_enable;
++#endif
++#ifdef CONFIG_RTW_PATH_DIV
++		registry_par->path_div = (u8)rtw_path_div_enable;
++#endif
++		registry_par->stbc_cap = (u8)rtw_stbc_cap;
++		registry_par->beamform_cap = (u8)rtw_beamform_cap;
++		registry_par->beamformer_rf_num = (u8)rtw_bfer_rf_number;
++		registry_par->beamformee_rf_num = (u8)rtw_bfee_rf_number;
++		rtw_regsty_init_rx_ampdu_sz_limit(registry_par);
++	}
++#endif
++#ifdef DBG_LA_MODE
++	registry_par->la_mode_en = (u8)rtw_la_mode_en;
++#endif
++#ifdef CONFIG_NARROWBAND_SUPPORTING
++	registry_par->rtw_nb_config = (u8)rtw_nb_config;
++#endif
++
++#ifdef CONFIG_80211AC_VHT
++	registry_par->vht_enable = (u8)rtw_vht_enable;
++	registry_par->ampdu_factor = (u8)rtw_ampdu_factor;
++	registry_par->vht_rx_mcs_map[0] = (u8)(rtw_vht_rx_mcs_map & 0xFF);
++	registry_par->vht_rx_mcs_map[1] = (u8)((rtw_vht_rx_mcs_map & 0xFF00) >> 8);
++#endif
++
++#ifdef CONFIG_TX_EARLY_MODE
++	registry_par->early_mode = (u8)rtw_early_mode;
++#endif
++	registry_par->lowrate_two_xmit = (u8)rtw_lowrate_two_xmit;
++	registry_par->trx_path_bmp = (u8)rtw_trx_path_bmp;
++	registry_par->tx_path_lmt = (u8)rtw_tx_path_lmt;
++	registry_par->rx_path_lmt = (u8)rtw_rx_path_lmt;
++	registry_par->tx_nss = (u8)rtw_tx_nss;
++	registry_par->rx_nss = (u8)rtw_rx_nss;
++	registry_par->low_power = (u8)rtw_low_power;
++
++	registry_par->check_hw_status = (u8)rtw_check_hw_status;
++
++	registry_par->wifi_spec = (u8)rtw_wifi_spec;
++
++	if (strlen(rtw_country_code) != 2
++		|| is_alpha(rtw_country_code[0]) == _FALSE
++		|| is_alpha(rtw_country_code[1]) == _FALSE
++	) {
++		if (rtw_country_code != rtw_country_unspecified)
++			RTW_ERR("%s discard rtw_country_code not in alpha2\n", __func__);
++		_rtw_memset(registry_par->alpha2, 0xFF, 2);
++	} else
++		_rtw_memcpy(registry_par->alpha2, rtw_country_code, 2);
++
++	registry_par->channel_plan = (u8)rtw_channel_plan;
++	rtw_regsty_load_excl_chs(registry_par);
++
++	registry_par->full_ch_in_p2p_handshake = (u8)rtw_full_ch_in_p2p_handshake;
++#ifdef CONFIG_BT_COEXIST
++	registry_par->btcoex = (u8)rtw_btcoex_enable;
++	registry_par->bt_iso = (u8)rtw_bt_iso;
++	registry_par->bt_sco = (u8)rtw_bt_sco;
++	registry_par->bt_ampdu = (u8)rtw_bt_ampdu;
++	registry_par->ant_num = (u8)rtw_ant_num;
++	registry_par->single_ant_path = (u8) rtw_single_ant_path;
++#endif
++
++	registry_par->bAcceptAddbaReq = (u8)rtw_AcceptAddbaReq;
++
++	registry_par->antdiv_cfg = (u8)rtw_antdiv_cfg;
++	registry_par->antdiv_type = (u8)rtw_antdiv_type;
++
++	registry_par->drv_ant_band_switch = (u8) rtw_drv_ant_band_switch;
++
++	registry_par->switch_usb_mode = (u8)rtw_switch_usb_mode;
++#ifdef SUPPORT_HW_RFOFF_DETECTED
++	registry_par->hwpdn_mode = (u8)rtw_hwpdn_mode;/* 0:disable,1:enable,2:by EFUSE config */
++	registry_par->hwpwrp_detect = (u8)rtw_hwpwrp_detect;/* 0:disable,1:enable */
++#endif
++
++	registry_par->hw_wps_pbc = (u8)rtw_hw_wps_pbc;
++
++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
++	snprintf(registry_par->adaptor_info_caching_file_path, PATH_LENGTH_MAX, "%s", rtw_adaptor_info_caching_file_path);
++	registry_par->adaptor_info_caching_file_path[PATH_LENGTH_MAX - 1] = 0;
++#endif
++
++#ifdef CONFIG_LAYER2_ROAMING
++	registry_par->max_roaming_times = (u8)rtw_max_roaming_times;
++#endif
++
++#ifdef CONFIG_IOL
++	registry_par->fw_iol = rtw_fw_iol;
++#endif
++
++#ifdef CONFIG_80211D
++	registry_par->enable80211d = (u8)rtw_80211d;
++#endif
++
++	snprintf(registry_par->ifname, 16, "%s", ifname);
++	snprintf(registry_par->if2name, 16, "%s", if2name);
++
++	registry_par->notch_filter = (u8)rtw_notch_filter;
++
++#ifdef CONFIG_CONCURRENT_MODE
++	registry_par->virtual_iface_num = (u8)rtw_virtual_iface_num;
++#ifdef CONFIG_P2P
++	registry_par->sel_p2p_iface = (u8)rtw_sel_p2p_iface;
++	RTW_INFO("%s, Select P2P interface: iface_id:%d\n", __func__, registry_par->sel_p2p_iface);
++#endif
++#endif
++	registry_par->pll_ref_clk_sel = (u8)rtw_pll_ref_clk_sel;
++
++#if CONFIG_TXPWR_LIMIT
++	registry_par->RegEnableTxPowerLimit = (u8)rtw_tx_pwr_lmt_enable;
++#endif
++	registry_par->RegEnableTxPowerByRate = (u8)rtw_tx_pwr_by_rate;
++
++	rtw_regsty_load_target_tx_power(registry_par);
++
++	registry_par->tsf_update_pause_factor = (u8)rtw_tsf_update_pause_factor;
++	registry_par->tsf_update_restore_factor = (u8)rtw_tsf_update_restore_factor;
++
++	registry_par->TxBBSwing_2G = (s8)rtw_TxBBSwing_2G;
++	registry_par->TxBBSwing_5G = (s8)rtw_TxBBSwing_5G;
++	registry_par->bEn_RFE = 1;
++	registry_par->RFE_Type = (u8)rtw_RFE_type;
++	registry_par->PowerTracking_Type = (u8)rtw_powertracking_type;
++	registry_par->AmplifierType_2G = (u8)rtw_amplifier_type_2g;
++	registry_par->AmplifierType_5G = (u8)rtw_amplifier_type_5g;
++	registry_par->GLNA_Type = (u8)rtw_GLNA_type;
++#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++	registry_par->load_phy_file = (u8)rtw_load_phy_file;
++	registry_par->RegDecryptCustomFile = (u8)rtw_decrypt_phy_file;
++#endif
++	registry_par->qos_opt_enable = (u8)rtw_qos_opt_enable;
++
++	registry_par->hiq_filter = (u8)rtw_hiq_filter;
++
++	registry_par->adaptivity_en = (u8)rtw_adaptivity_en;
++	registry_par->adaptivity_mode = (u8)rtw_adaptivity_mode;
++	registry_par->adaptivity_th_l2h_ini = (s8)rtw_adaptivity_th_l2h_ini;
++	registry_par->adaptivity_th_edcca_hl_diff = (s8)rtw_adaptivity_th_edcca_hl_diff;
++
++#ifdef CONFIG_DYNAMIC_SOML
++	registry_par->dyn_soml_en = (u8)rtw_dynamic_soml_en;
++	registry_par->dyn_soml_train_num = (u8)rtw_dynamic_soml_train_num;
++	registry_par->dyn_soml_interval = (u8)rtw_dynamic_soml_interval;
++	registry_par->dyn_soml_period = (u8)rtw_dynamic_soml_period;
++	registry_par->dyn_soml_delay = (u8)rtw_dynamic_soml_delay;
++#endif
++
++	registry_par->boffefusemask = (u8)rtw_OffEfuseMask;
++	registry_par->bFileMaskEfuse = (u8)rtw_FileMaskEfuse;
++	registry_par->bBTFileMaskEfuse = (u8)rtw_FileMaskEfuse;
++
++#ifdef CONFIG_RTW_ACS
++	registry_par->acs_mode = (u8)rtw_acs;
++	registry_par->acs_auto_scan = (u8)rtw_acs_auto_scan;
++#endif
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++	registry_par->nm_mode = (u8)rtw_nm;
++#endif
++	registry_par->reg_rxgain_offset_2g = (u32) rtw_rxgain_offset_2g;
++	registry_par->reg_rxgain_offset_5gl = (u32) rtw_rxgain_offset_5gl;
++	registry_par->reg_rxgain_offset_5gm = (u32) rtw_rxgain_offset_5gm;
++	registry_par->reg_rxgain_offset_5gh = (u32) rtw_rxgain_offset_5gh;
++
++#ifdef CONFIG_DFS_MASTER
++	registry_par->dfs_region_domain = (u8)rtw_dfs_region_domain;
++#endif
++
++#ifdef CONFIG_MCC_MODE
++	registry_par->en_mcc = (u8)rtw_en_mcc;
++	registry_par->rtw_mcc_ap_bw20_target_tx_tp = (u32)rtw_mcc_ap_bw20_target_tx_tp;
++	registry_par->rtw_mcc_ap_bw40_target_tx_tp = (u32)rtw_mcc_ap_bw40_target_tx_tp;
++	registry_par->rtw_mcc_ap_bw80_target_tx_tp = (u32)rtw_mcc_ap_bw80_target_tx_tp;
++	registry_par->rtw_mcc_sta_bw20_target_tx_tp = (u32)rtw_mcc_sta_bw20_target_tx_tp;
++	registry_par->rtw_mcc_sta_bw40_target_tx_tp = (u32)rtw_mcc_sta_bw40_target_tx_tp;
++	registry_par->rtw_mcc_sta_bw80_target_tx_tp = (u32)rtw_mcc_sta_bw80_target_tx_tp;
++	registry_par->rtw_mcc_single_tx_cri = (u32)rtw_mcc_single_tx_cri;
++	registry_par->rtw_mcc_policy_table_idx = rtw_mcc_policy_table_idx;
++	registry_par->rtw_mcc_duration = (u8)rtw_mcc_duration;
++	registry_par->rtw_mcc_enable_runtime_duration = rtw_mcc_enable_runtime_duration;
++	registry_par->rtw_mcc_phydm_offload = rtw_mcc_phydm_offload;
++#endif /*CONFIG_MCC_MODE */
++
++#ifdef CONFIG_WOWLAN
++	registry_par->wowlan_enable = rtw_wow_enable;
++	registry_par->wakeup_event = rtw_wakeup_event;
++	registry_par->suspend_type = rtw_suspend_type;
++#endif
++
++#ifdef CONFIG_SUPPORT_TRX_SHARED
++	registry_par->trx_share_mode = rtw_trx_share_mode;
++#endif
++	registry_par->wowlan_sta_mix_mode = rtw_wowlan_sta_mix_mode;
++
++#ifdef CONFIG_PCI_HCI
++	registry_par->pci_aspm_config = rtw_pci_aspm_enable;
++	registry_par->pci_dynamic_aspm_linkctrl = rtw_pci_dynamic_aspm_linkctrl;
++#endif
++
++#ifdef CONFIG_RTW_NAPI
++	registry_par->en_napi = (u8)rtw_en_napi;
++#ifdef CONFIG_RTW_NAPI_DYNAMIC
++	registry_par->napi_threshold = (u32)rtw_napi_threshold;
++#endif /* CONFIG_RTW_NAPI_DYNAMIC */
++#ifdef CONFIG_RTW_GRO
++	registry_par->en_gro = (u8)rtw_en_gro;
++	if (!registry_par->en_napi && registry_par->en_gro) {
++		registry_par->en_gro = 0;
++		RTW_WARN("Disable GRO because NAPI is not enabled\n");
++	}
++#endif /* CONFIG_RTW_GRO */
++#endif /* CONFIG_RTW_NAPI */
++
++	registry_par->iqk_fw_offload = (u8)rtw_iqk_fw_offload;
++	registry_par->ch_switch_offload = (u8)rtw_ch_switch_offload;
++
++#ifdef CONFIG_TDLS
++	registry_par->en_tdls = rtw_en_tdls;
++#endif
++
++#ifdef CONFIG_ADVANCE_OTA
++	registry_par->adv_ota = rtw_advnace_ota;
++#endif
++#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
++	registry_par->fw_param_init = rtw_fw_param_init;
++#endif
++#ifdef CONFIG_AP_MODE
++	registry_par->bmc_tx_rate = rtw_bmc_tx_rate;
++	#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++	registry_par->ap_src_b2u_flags = rtw_ap_src_b2u_flags;
++	registry_par->ap_fwd_b2u_flags = rtw_ap_fwd_b2u_flags;
++	#endif
++#endif /* CONFIG_AP_MODE */
++
++#ifdef CONFIG_RTW_MESH
++	#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++	registry_par->msrc_b2u_flags = rtw_msrc_b2u_flags;
++	registry_par->mfwd_b2u_flags = rtw_mfwd_b2u_flags;
++	#endif
++#endif /* CONFIG_RTW_MESH */
++
++#ifdef CONFIG_FW_HANDLE_TXBCN
++	registry_par->fw_tbtt_rpt = rtw_tbtt_rpt;
++#endif
++	registry_par->phydm_ability = rtw_phydm_ability;
++	registry_par->halrf_ability = rtw_halrf_ability;
++#ifdef CONFIG_RTW_MESH
++	registry_par->peer_alive_based_preq = rtw_peer_alive_based_preq;
++#endif
++
++#ifdef RTW_BUSY_DENY_SCAN
++	registry_par->scan_interval_thr = rtw_scan_interval_thr;
++#endif
++
++#ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY
++	registry_par->rtw_8822c_xcap_overwrite = (u8)rtw_8822c_xcap_overwrite;
++#endif
++
++	return status;
++}
++
++/**
++ * rtw_net_set_mac_address
++ * This callback function is used for the Media Access Control address
++ * of each net_device needs to be changed.
++ *
++ * Arguments:
++ * @pnetdev: net_device pointer.
++ * @addr: new MAC address.
++ *
++ * Return:
++ * ret = 0: Permit to change net_device's MAC address.
++ * ret = -1 (Default): Operation not permitted.
++ *
++ * Auther: Arvin Liu
++ * Date: 2015/05/29
++ */
++static int rtw_net_set_mac_address(struct net_device *pnetdev, void *addr)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct sockaddr *sa = (struct sockaddr *)addr;
++	int ret = -1;
++
++	/* only the net_device is in down state to permit modifying mac addr */
++	if ((pnetdev->flags & IFF_UP) == _TRUE) {
++		RTW_INFO(FUNC_ADPT_FMT": The net_device's is not in down state\n"
++			 , FUNC_ADPT_ARG(padapter));
++
++		return ret;
++	}
++
++	/* if the net_device is linked, it's not permit to modify mac addr */
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) ||
++	    check_fwstate(pmlmepriv, WIFI_ASOC_STATE) ||
++	    check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)) {
++		RTW_INFO(FUNC_ADPT_FMT": The net_device's is not idle currently\n"
++			 , FUNC_ADPT_ARG(padapter));
++
++		return ret;
++	}
++
++	/* check whether the input mac address is valid to permit modifying mac addr */
++	if (rtw_check_invalid_mac_address(sa->sa_data, _FALSE) == _TRUE) {
++		RTW_INFO(FUNC_ADPT_FMT": Invalid Mac Addr for "MAC_FMT"\n"
++			 , FUNC_ADPT_ARG(padapter), MAC_ARG(sa->sa_data));
++
++		return ret;
++	}
++
++	_rtw_memcpy(adapter_mac_addr(padapter), sa->sa_data, ETH_ALEN); /* set mac addr to adapter */
++	_rtw_memcpy(pnetdev->dev_addr, sa->sa_data, ETH_ALEN); /* set mac addr to net_device */
++
++#if 0
++	if (rtw_is_hw_init_completed(padapter)) {
++		rtw_ps_deny(padapter, PS_DENY_IOCTL);
++		LeaveAllPowerSaveModeDirect(padapter); /* leave PS mode for guaranteeing to access hw register successfully */
++
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++		rtw_hal_change_macaddr_mbid(padapter, sa->sa_data);
++#else
++		rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, sa->sa_data); /* set mac addr to mac register */
++#endif
++
++		rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
++	}
++#else
++	rtw_ps_deny(padapter, PS_DENY_IOCTL);
++	LeaveAllPowerSaveModeDirect(padapter); /* leave PS mode for guaranteeing to access hw register successfully */
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++	rtw_hal_change_macaddr_mbid(padapter, sa->sa_data);
++#else
++	rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, sa->sa_data); /* set mac addr to mac register */
++#endif
++	rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
++#endif
++
++	RTW_INFO(FUNC_ADPT_FMT": Set Mac Addr to "MAC_FMT" Successfully\n"
++		 , FUNC_ADPT_ARG(padapter), MAC_ARG(sa->sa_data));
++
++	ret = 0;
++
++	return ret;
++}
++
++static struct net_device_stats *rtw_net_get_stats(struct net_device *pnetdev)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
++	struct recv_priv *precvpriv = &(padapter->recvpriv);
++
++	padapter->stats.tx_packets = pxmitpriv->tx_pkts;/* pxmitpriv->tx_pkts++; */
++	padapter->stats.rx_packets = precvpriv->rx_pkts;/* precvpriv->rx_pkts++; */
++	padapter->stats.tx_dropped = pxmitpriv->tx_drop;
++	padapter->stats.rx_dropped = precvpriv->rx_drop;
++	padapter->stats.tx_bytes = pxmitpriv->tx_bytes;
++	padapter->stats.rx_bytes = precvpriv->rx_bytes;
++
++	return &padapter->stats;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++/*
++ * AC to queue mapping
++ *
++ * AC_VO -> queue 0
++ * AC_VI -> queue 1
++ * AC_BE -> queue 2
++ * AC_BK -> queue 3
++ */
++static const u16 rtw_1d_to_queue[8] = { 2, 3, 3, 2, 1, 1, 0, 0 };
++
++/* Given a data frame determine the 802.1p/1d tag to use. */
++unsigned int rtw_classify8021d(struct sk_buff *skb)
++{
++	unsigned int dscp;
++
++	/* skb->priority values from 256->263 are magic values to
++	 * directly indicate a specific 802.1d priority.  This is used
++	 * to allow 802.1d priority to be passed directly in from VLAN
++	 * tags, etc.
++	 */
++	if (skb->priority >= 256 && skb->priority <= 263)
++		return skb->priority - 256;
++
++	switch (skb->protocol) {
++	case htons(ETH_P_IP):
++		dscp = ip_hdr(skb)->tos & 0xfc;
++		break;
++	default:
++		return 0;
++	}
++
++	return dscp >> 5;
++}
++
++
++static u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)
++	#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0)
++	, struct net_device *sb_dev
++	#else
++	, void *accel_priv
++	#endif
++	#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0)))
++	, select_queue_fallback_t fallback
++	#endif
++#endif
++)
++{
++	_adapter	*padapter = rtw_netdev_priv(dev);
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++	skb->priority = rtw_classify8021d(skb);
++
++	if (pmlmepriv->acm_mask != 0)
++		skb->priority = qos_acm(pmlmepriv->acm_mask, skb->priority);
++
++	return rtw_1d_to_queue[skb->priority];
++}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) */
++
++u16 rtw_os_recv_select_queue(u8 *msdu, enum rtw_rx_llc_hdl llc_hdl)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	u32 priority = 0;
++
++	if (llc_hdl == RTW_RX_LLC_REMOVE) {
++		u16 eth_type = RTW_GET_BE16(msdu + SNAP_SIZE);
++
++		if (eth_type == ETH_P_IP) {
++			struct iphdr *iphdr = (struct iphdr *)(msdu + SNAP_SIZE + 2);
++			unsigned int dscp = iphdr->tos & 0xfc;
++
++			priority = dscp >> 5;
++		}
++	}
++
++	return rtw_1d_to_queue[priority];
++#else
++	return 0;
++#endif
++}
++
++static u8 is_rtw_ndev(struct net_device *ndev)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
++	return ndev->netdev_ops
++		&& ndev->netdev_ops->ndo_do_ioctl
++		&& ndev->netdev_ops->ndo_do_ioctl == rtw_ioctl;
++#else
++	return ndev->do_ioctl
++		&& ndev->do_ioctl == rtw_ioctl;
++#endif
++}
++
++static int rtw_ndev_notifier_call(struct notifier_block *nb, unsigned long state, void *ptr)
++{
++	struct net_device *ndev;
++
++	if (ptr == NULL)
++		return NOTIFY_DONE;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
++	ndev = netdev_notifier_info_to_dev(ptr);
++#else
++	ndev = ptr;
++#endif
++
++	if (ndev == NULL)
++		return NOTIFY_DONE;
++
++	if (!is_rtw_ndev(ndev))
++		return NOTIFY_DONE;
++
++	RTW_INFO(FUNC_NDEV_FMT" state:%lu\n", FUNC_NDEV_ARG(ndev), state);
++
++	switch (state) {
++	case NETDEV_CHANGENAME:
++		rtw_adapter_proc_replace(ndev);
++		break;
++	#ifdef CONFIG_NEW_NETDEV_HDL
++	case NETDEV_PRE_UP :
++		{
++			_adapter *adapter = rtw_netdev_priv(ndev);
++
++			rtw_pwr_wakeup(adapter);
++		}
++		break;
++	#endif
++	}
++
++	return NOTIFY_DONE;
++}
++
++static struct notifier_block rtw_ndev_notifier = {
++	.notifier_call = rtw_ndev_notifier_call,
++};
++
++int rtw_ndev_notifier_register(void)
++{
++	return register_netdevice_notifier(&rtw_ndev_notifier);
++}
++
++void rtw_ndev_notifier_unregister(void)
++{
++	unregister_netdevice_notifier(&rtw_ndev_notifier);
++}
++
++int rtw_ndev_init(struct net_device *dev)
++{
++	_adapter *adapter = rtw_netdev_priv(dev);
++
++	RTW_PRINT(FUNC_ADPT_FMT" if%d mac_addr="MAC_FMT"\n"
++		, FUNC_ADPT_ARG(adapter), (adapter->iface_id + 1), MAC_ARG(dev->dev_addr));
++	strncpy(adapter->old_ifname, dev->name, IFNAMSIZ);
++	adapter->old_ifname[IFNAMSIZ - 1] = '\0';
++	rtw_adapter_proc_init(dev);
++
++	return 0;
++}
++
++void rtw_ndev_uninit(struct net_device *dev)
++{
++	_adapter *adapter = rtw_netdev_priv(dev);
++
++	RTW_PRINT(FUNC_ADPT_FMT" if%d\n"
++		  , FUNC_ADPT_ARG(adapter), (adapter->iface_id + 1));
++	rtw_adapter_proc_deinit(dev);
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
++static const struct net_device_ops rtw_netdev_ops = {
++	.ndo_init = rtw_ndev_init,
++	.ndo_uninit = rtw_ndev_uninit,
++	.ndo_open = netdev_open,
++	.ndo_stop = netdev_close,
++	.ndo_start_xmit = rtw_xmit_entry,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	.ndo_select_queue	= rtw_select_queue,
++#endif
++	.ndo_set_mac_address = rtw_net_set_mac_address,
++	.ndo_get_stats = rtw_net_get_stats,
++	.ndo_do_ioctl = rtw_ioctl,
++};
++#endif
++
++int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname)
++{
++#ifdef CONFIG_EASY_REPLACEMENT
++	_adapter *padapter = rtw_netdev_priv(pnetdev);
++	struct net_device	*TargetNetdev = NULL;
++	_adapter			*TargetAdapter = NULL;
++
++	if (padapter->bDongle == 1) {
++		TargetNetdev = rtw_get_same_net_ndev_by_name(pnetdev, "wlan0");
++		if (TargetNetdev) {
++			RTW_INFO("Force onboard module driver disappear !!!\n");
++			TargetAdapter = rtw_netdev_priv(TargetNetdev);
++			TargetAdapter->DriverState = DRIVER_DISAPPEAR;
++
++			padapter->pid[0] = TargetAdapter->pid[0];
++			padapter->pid[1] = TargetAdapter->pid[1];
++			padapter->pid[2] = TargetAdapter->pid[2];
++
++			dev_put(TargetNetdev);
++			unregister_netdev(TargetNetdev);
++
++			padapter->DriverState = DRIVER_REPLACE_DONGLE;
++		}
++	}
++#endif /* CONFIG_EASY_REPLACEMENT */
++
++	if (dev_alloc_name(pnetdev, ifname) < 0)
++		RTW_ERR("dev_alloc_name, fail!\n");
++
++	rtw_netif_carrier_off(pnetdev);
++	/* rtw_netif_stop_queue(pnetdev); */
++
++	return 0;
++}
++
++void rtw_hook_if_ops(struct net_device *ndev)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
++	ndev->netdev_ops = &rtw_netdev_ops;
++#else
++	ndev->init = rtw_ndev_init;
++	ndev->uninit = rtw_ndev_uninit;
++	ndev->open = netdev_open;
++	ndev->stop = netdev_close;
++	ndev->hard_start_xmit = rtw_xmit_entry;
++	ndev->set_mac_address = rtw_net_set_mac_address;
++	ndev->get_stats = rtw_net_get_stats;
++	ndev->do_ioctl = rtw_ioctl;
++#endif
++}
++
++#ifdef CONFIG_CONCURRENT_MODE
++static void rtw_hook_vir_if_ops(struct net_device *ndev);
++#endif
++struct net_device *rtw_init_netdev(_adapter *old_padapter)
++{
++	_adapter *padapter;
++	struct net_device *pnetdev;
++
++	if (old_padapter != NULL) {
++		rtw_os_ndev_free(old_padapter);
++		pnetdev = rtw_alloc_etherdev_with_old_priv(sizeof(_adapter), (void *)old_padapter);
++	} else
++		pnetdev = rtw_alloc_etherdev(sizeof(_adapter));
++
++	if (!pnetdev)
++		return NULL;
++
++	padapter = rtw_netdev_priv(pnetdev);
++	padapter->pnetdev = pnetdev;
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)
++	SET_MODULE_OWNER(pnetdev);
++#endif
++
++	rtw_hook_if_ops(pnetdev);
++#ifdef CONFIG_CONCURRENT_MODE
++	if (!is_primary_adapter(padapter))
++		rtw_hook_vir_if_ops(pnetdev);
++#endif /* CONFIG_CONCURRENT_MODE */
++
++
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
++        pnetdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)
++        pnetdev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
++#endif
++#endif
++
++#ifdef CONFIG_RTW_NETIF_SG
++        pnetdev->features |= NETIF_F_SG;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)
++        pnetdev->hw_features |= NETIF_F_SG;
++#endif
++#endif
++
++	if ((pnetdev->features & NETIF_F_SG) && (pnetdev->features & NETIF_F_IP_CSUM)) {
++		pnetdev->features |= (NETIF_F_TSO | NETIF_F_GSO);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)
++		pnetdev->hw_features |= (NETIF_F_TSO | NETIF_F_GSO);
++#endif
++	}
++	/* pnetdev->tx_timeout = NULL; */
++	pnetdev->watchdog_timeo = HZ * 3; /* 3 second timeout */
++
++#ifdef CONFIG_WIRELESS_EXT
++	pnetdev->wireless_handlers = (struct iw_handler_def *)&rtw_handlers_def;
++#endif
++
++#ifdef WIRELESS_SPY
++	/* priv->wireless_data.spy_data = &priv->spy_data; */
++	/* pnetdev->wireless_data = &priv->wireless_data; */
++#endif
++
++	return pnetdev;
++}
++
++int rtw_os_ndev_alloc(_adapter *adapter)
++{
++	int ret = _FAIL;
++	struct net_device *ndev = NULL;
++
++	ndev = rtw_init_netdev(adapter);
++	if (ndev == NULL) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)
++	SET_NETDEV_DEV(ndev, dvobj_to_dev(adapter_to_dvobj(adapter)));
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	if (adapter_to_dvobj(adapter)->bdma64)
++		ndev->features |= NETIF_F_HIGHDMA;
++	ndev->irq = adapter_to_dvobj(adapter)->irq;
++#endif
++
++#if defined(CONFIG_IOCTL_CFG80211)
++	if (rtw_cfg80211_ndev_res_alloc(adapter) != _SUCCESS) {
++		rtw_warn_on(1);
++	} else
++#endif
++	ret = _SUCCESS;
++
++	if (ret != _SUCCESS && ndev)
++		rtw_free_netdev(ndev);
++exit:
++	return ret;
++}
++
++void rtw_os_ndev_free(_adapter *adapter)
++{
++#if defined(CONFIG_IOCTL_CFG80211)
++	rtw_cfg80211_ndev_res_free(adapter);
++#endif
++
++	/* free the old_pnetdev */
++	if (adapter->rereg_nd_name_priv.old_pnetdev) {
++		rtw_free_netdev(adapter->rereg_nd_name_priv.old_pnetdev);
++		adapter->rereg_nd_name_priv.old_pnetdev = NULL;
++	}
++
++	if (adapter->pnetdev) {
++		rtw_free_netdev(adapter->pnetdev);
++		adapter->pnetdev = NULL;
++	}
++}
++
++/* For ethtool +++ */
++#ifdef CONFIG_IOCTL_CFG80211
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 8))
++static void rtw_ethtool_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
++{
++	struct wireless_dev *wdev = NULL;
++	_adapter *padapter = NULL;
++	HAL_DATA_TYPE *hal_data = NULL;
++
++	wdev = dev->ieee80211_ptr;
++	if (wdev) {
++		strlcpy(info->driver, wiphy_dev(wdev->wiphy)->driver->name,
++			sizeof(info->driver));
++	} else {
++		strlcpy(info->driver, "N/A", sizeof(info->driver));
++	}
++
++	strlcpy(info->version, DRIVERVERSION, sizeof(info->version));
++
++	padapter = (_adapter *)rtw_netdev_priv(dev);
++	if (padapter) {
++		hal_data = GET_HAL_DATA(padapter);
++	}
++
++	if (hal_data) {
++		scnprintf(info->fw_version, sizeof(info->fw_version), "%d.%d",
++			  hal_data->firmware_version, hal_data->firmware_sub_version);
++	} else {
++		strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
++	}
++
++	strlcpy(info->bus_info, dev_name(wiphy_dev(wdev->wiphy)),
++		sizeof(info->bus_info));
++}
++
++static const char rtw_ethtool_gstrings_sta_stats[][ETH_GSTRING_LEN] = {
++	"rx_packets", "rx_bytes", "rx_dropped",
++	"tx_packets", "tx_bytes", "tx_dropped",
++};
++
++#define RTW_ETHTOOL_STATS_LEN	ARRAY_SIZE(rtw_ethtool_gstrings_sta_stats)
++
++static int rtw_ethtool_get_sset_count(struct net_device *dev, int sset)
++{
++	int rv = 0;
++
++	if (sset == ETH_SS_STATS)
++		rv += RTW_ETHTOOL_STATS_LEN;
++
++	if (rv == 0)
++		return -EOPNOTSUPP;
++
++	return rv;
++}
++
++static void rtw_ethtool_get_strings(struct net_device *dev, u32 sset, u8 *data)
++{
++	int sz_sta_stats = 0;
++
++	if (sset == ETH_SS_STATS) {
++		sz_sta_stats = sizeof(rtw_ethtool_gstrings_sta_stats);
++		memcpy(data, rtw_ethtool_gstrings_sta_stats, sz_sta_stats);
++	}
++}
++
++static void rtw_ethtool_get_stats(struct net_device *dev,
++				  struct ethtool_stats *stats,
++				  u64 *data)
++{
++	int i = 0;
++	_adapter *padapter = NULL;
++	struct xmit_priv *pxmitpriv = NULL;
++	struct recv_priv *precvpriv = NULL;
++
++	memset(data, 0, sizeof(u64) * RTW_ETHTOOL_STATS_LEN);
++	
++	padapter = (_adapter *)rtw_netdev_priv(dev);
++	if (padapter) {
++		pxmitpriv = &(padapter->xmitpriv);
++		precvpriv = &(padapter->recvpriv);
++
++		data[i++] = precvpriv->rx_pkts;
++		data[i++] = precvpriv->rx_bytes;
++		data[i++] = precvpriv->rx_drop;
++
++		data[i++] = pxmitpriv->tx_pkts;
++		data[i++] = pxmitpriv->tx_bytes;
++		data[i++] = pxmitpriv->tx_drop;
++	} else {
++		data[i++] = 0;
++		data[i++] = 0;
++		data[i++] = 0;
++
++		data[i++] = 0;
++		data[i++] = 0;
++		data[i++] = 0;
++	}
++}
++
++static const struct ethtool_ops rtw_ethtool_ops = {
++	.get_drvinfo = rtw_ethtool_get_drvinfo,
++	.get_link = ethtool_op_get_link,
++	.get_strings = rtw_ethtool_get_strings,
++	.get_ethtool_stats = rtw_ethtool_get_stats,
++	.get_sset_count = rtw_ethtool_get_sset_count,
++};
++#endif // LINUX_VERSION_CODE >= 3.7.8 
++#endif /* CONFIG_IOCTL_CFG80211 */
++/* For ethtool --- */
++
++int rtw_os_ndev_register(_adapter *adapter, const char *name)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	int ret = _SUCCESS;
++	struct net_device *ndev = adapter->pnetdev;
++	u8 rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj);
++
++#ifdef CONFIG_RTW_NAPI
++	netif_napi_add(ndev, &adapter->napi, rtw_recv_napi_poll, RTL_NAPI_WEIGHT);
++#endif /* CONFIG_RTW_NAPI */
++
++#if defined(CONFIG_IOCTL_CFG80211)
++	if (rtw_cfg80211_ndev_res_register(adapter) != _SUCCESS) {
++		rtw_warn_on(1);
++		ret = _FAIL;
++		goto exit;
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 8))
++	netdev_set_default_ethtool_ops(ndev, &rtw_ethtool_ops);
++#endif /* LINUX_VERSION_CODE >= 3.7.8 */
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) && defined(CONFIG_PCI_HCI)
++	ndev->gro_flush_timeout = 100000;
++#endif
++	/* alloc netdev name */
++	rtw_init_netdev_name(ndev, name);
++
++	_rtw_memcpy(ndev->dev_addr, adapter_mac_addr(adapter), ETH_ALEN);
++
++	/* Tell the network stack we exist */
++
++	if (rtnl_lock_needed)
++		ret = (register_netdev(ndev) == 0) ? _SUCCESS : _FAIL;
++	else
++		ret = (register_netdevice(ndev) == 0) ? _SUCCESS : _FAIL;
++
++	if (ret == _SUCCESS)
++		adapter->registered = 1;
++	else
++		RTW_INFO(FUNC_NDEV_FMT" if%d Failed!\n", FUNC_NDEV_ARG(ndev), (adapter->iface_id + 1));
++
++#if defined(CONFIG_IOCTL_CFG80211)
++	if (ret != _SUCCESS) {
++		rtw_cfg80211_ndev_res_unregister(adapter);
++		#if !defined(RTW_SINGLE_WIPHY)
++		rtw_wiphy_unregister(adapter_to_wiphy(adapter));
++		#endif
++	}
++#endif
++
++#if defined(CONFIG_IOCTL_CFG80211)
++exit:
++#endif
++#ifdef CONFIG_RTW_NAPI
++	if (ret != _SUCCESS)
++		netif_napi_del(&adapter->napi);
++#endif /* CONFIG_RTW_NAPI */
++
++	return ret;
++}
++
++void rtw_os_ndev_unregister(_adapter *adapter)
++{
++	struct net_device *netdev = NULL;
++
++	if (adapter == NULL || adapter->registered == 0)
++		return;
++
++	adapter->ndev_unregistering = 1;
++
++	netdev = adapter->pnetdev;
++
++#if defined(CONFIG_IOCTL_CFG80211)
++	rtw_cfg80211_ndev_res_unregister(adapter);
++#endif
++
++	if ((adapter->DriverState != DRIVER_DISAPPEAR) && netdev) {
++		struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++		u8 rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj);
++
++		if (rtnl_lock_needed)
++			unregister_netdev(netdev);
++		else
++			unregister_netdevice(netdev);
++	}
++
++#if defined(CONFIG_IOCTL_CFG80211) && !defined(RTW_SINGLE_WIPHY)
++#ifdef CONFIG_RFKILL_POLL
++	rtw_cfg80211_deinit_rfkill(adapter_to_wiphy(adapter));
++#endif
++	rtw_wiphy_unregister(adapter_to_wiphy(adapter));
++#endif
++
++#ifdef CONFIG_RTW_NAPI
++	if (adapter->napi_state == NAPI_ENABLE) {
++		napi_disable(&adapter->napi);
++		adapter->napi_state = NAPI_DISABLE;
++	}
++	netif_napi_del(&adapter->napi);
++#endif /* CONFIG_RTW_NAPI */
++
++	adapter->registered = 0;
++	adapter->ndev_unregistering = 0;
++}
++
++/**
++ * rtw_os_ndev_init - Allocate and register OS layer net device and relating structures for @adapter
++ * @adapter: the adapter on which this function applies
++ * @name: the requesting net device name
++ *
++ * Returns:
++ * _SUCCESS or _FAIL
++ */
++int rtw_os_ndev_init(_adapter *adapter, const char *name)
++{
++	int ret = _FAIL;
++
++	if (rtw_os_ndev_alloc(adapter) != _SUCCESS)
++		goto exit;
++
++	if (rtw_os_ndev_register(adapter, name) != _SUCCESS)
++		goto os_ndev_free;
++
++	ret = _SUCCESS;
++
++os_ndev_free:
++	if (ret != _SUCCESS)
++		rtw_os_ndev_free(adapter);
++exit:
++	return ret;
++}
++
++/**
++ * rtw_os_ndev_deinit - Unregister and free OS layer net device and relating structures for @adapter
++ * @adapter: the adapter on which this function applies
++ */
++void rtw_os_ndev_deinit(_adapter *adapter)
++{
++	rtw_os_ndev_unregister(adapter);
++	rtw_os_ndev_free(adapter);
++}
++
++int rtw_os_ndevs_alloc(struct dvobj_priv *dvobj)
++{
++	int i, status = _SUCCESS;
++	_adapter *adapter;
++
++#if defined(CONFIG_IOCTL_CFG80211)
++	if (rtw_cfg80211_dev_res_alloc(dvobj) != _SUCCESS) {
++		rtw_warn_on(1);
++		return _FAIL;
++	}
++#endif
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++
++		if (i >= CONFIG_IFACE_NUMBER) {
++			RTW_ERR("%s %d >= CONFIG_IFACE_NUMBER(%d)\n", __func__, i, CONFIG_IFACE_NUMBER);
++			rtw_warn_on(1);
++			continue;
++		}
++
++		adapter = dvobj->padapters[i];
++		if (adapter && !adapter->pnetdev) {
++
++			#ifdef CONFIG_RTW_DYNAMIC_NDEV
++			if (!is_primary_adapter(adapter))
++				continue;
++			#endif
++
++			status = rtw_os_ndev_alloc(adapter);
++			if (status != _SUCCESS) {
++				rtw_warn_on(1);
++				break;
++			}
++		}
++	}
++
++	if (status != _SUCCESS) {
++		for (; i >= 0; i--) {
++			adapter = dvobj->padapters[i];
++			if (adapter && adapter->pnetdev)
++				rtw_os_ndev_free(adapter);
++		}
++	}
++
++#if defined(CONFIG_IOCTL_CFG80211)
++	if (status != _SUCCESS)
++		rtw_cfg80211_dev_res_free(dvobj);
++#endif
++
++	return status;
++}
++
++void rtw_os_ndevs_free(struct dvobj_priv *dvobj)
++{
++	int i;
++	_adapter *adapter = NULL;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++
++		if (i >= CONFIG_IFACE_NUMBER) {
++			RTW_ERR("%s %d >= CONFIG_IFACE_NUMBER(%d)\n", __func__, i, CONFIG_IFACE_NUMBER);
++			rtw_warn_on(1);
++			continue;
++		}
++
++		adapter = dvobj->padapters[i];
++
++		if (adapter == NULL)
++			continue;
++
++		rtw_os_ndev_free(adapter);
++	}
++
++#if defined(CONFIG_IOCTL_CFG80211)
++	rtw_cfg80211_dev_res_free(dvobj);
++#endif
++}
++
++u32 rtw_start_drv_threads(_adapter *padapter)
++{
++	u32 _status = _SUCCESS;
++
++	RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(padapter));
++
++#ifdef CONFIG_XMIT_THREAD_MODE
++#if defined(CONFIG_SDIO_HCI)
++	if (is_primary_adapter(padapter))
++#endif
++	{
++		if (padapter->xmitThread == NULL) {
++			RTW_INFO(FUNC_ADPT_FMT " start RTW_XMIT_THREAD\n", FUNC_ADPT_ARG(padapter));
++			padapter->xmitThread = kthread_run(rtw_xmit_thread, padapter, "RTW_XMIT_THREAD");
++			if (IS_ERR(padapter->xmitThread)) {
++				padapter->xmitThread = NULL;
++				_status = _FAIL;
++			}
++		}
++	}
++#endif /* #ifdef CONFIG_XMIT_THREAD_MODE */
++
++#ifdef CONFIG_RECV_THREAD_MODE
++	if (is_primary_adapter(padapter)) {
++		if (padapter->recvThread == NULL) {
++			RTW_INFO(FUNC_ADPT_FMT " start RTW_RECV_THREAD\n", FUNC_ADPT_ARG(padapter));
++			padapter->recvThread = kthread_run(rtw_recv_thread, padapter, "RTW_RECV_THREAD");
++			if (IS_ERR(padapter->recvThread)) {
++				padapter->recvThread = NULL;
++				_status = _FAIL;
++			}
++		}
++	}
++#endif
++
++	if (is_primary_adapter(padapter)) {
++		if (padapter->cmdThread == NULL) {
++			RTW_INFO(FUNC_ADPT_FMT " start RTW_CMD_THREAD\n", FUNC_ADPT_ARG(padapter));
++			padapter->cmdThread = kthread_run(rtw_cmd_thread, padapter, "RTW_CMD_THREAD");
++			if (IS_ERR(padapter->cmdThread)) {
++				padapter->cmdThread = NULL;
++				_status = _FAIL;
++			}
++			else
++				_rtw_down_sema(&padapter->cmdpriv.start_cmdthread_sema); /* wait for cmd_thread to run */
++		}
++	}
++
++
++#ifdef CONFIG_EVENT_THREAD_MODE
++	if (padapter->evtThread == NULL) {
++		RTW_INFO(FUNC_ADPT_FMT " start RTW_EVENT_THREAD\n", FUNC_ADPT_ARG(padapter));
++		padapter->evtThread = kthread_run(event_thread, padapter, "RTW_EVENT_THREAD");
++		if (IS_ERR(padapter->evtThread)) {
++			padapter->evtThread = NULL;
++			_status = _FAIL;
++		}
++	}
++#endif
++
++	rtw_hal_start_thread(padapter);
++	return _status;
++
++}
++
++void rtw_stop_drv_threads(_adapter *padapter)
++{
++	RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(padapter));
++	if (is_primary_adapter(padapter))
++		rtw_stop_cmd_thread(padapter);
++
++#ifdef CONFIG_EVENT_THREAD_MODE
++	if (padapter->evtThread) {
++		_rtw_up_sema(&padapter->evtpriv.evt_notify);
++		rtw_thread_stop(padapter->evtThread);
++		padapter->evtThread = NULL;
++	}
++#endif
++
++#ifdef CONFIG_XMIT_THREAD_MODE
++	/* Below is to termindate tx_thread... */
++#if defined(CONFIG_SDIO_HCI)
++	/* Only wake-up primary adapter */
++	if (is_primary_adapter(padapter))
++#endif  /*SDIO_HCI */
++	{
++		if (padapter->xmitThread) {
++			_rtw_up_sema(&padapter->xmitpriv.xmit_sema);
++			rtw_thread_stop(padapter->xmitThread);
++			padapter->xmitThread = NULL;
++		}
++	}
++#endif
++
++#ifdef CONFIG_RECV_THREAD_MODE
++	if (is_primary_adapter(padapter) && padapter->recvThread) {
++		/* Below is to termindate rx_thread... */
++		_rtw_up_sema(&padapter->recvpriv.recv_sema);
++		rtw_thread_stop(padapter->recvThread);
++		padapter->recvThread = NULL;
++	}
++#endif
++
++	rtw_hal_stop_thread(padapter);
++}
++
++u8 rtw_init_default_value(_adapter *padapter)
++{
++	u8 ret  = _SUCCESS;
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
++	struct security_priv *psecuritypriv = &padapter->securitypriv;
++
++	/* xmit_priv */
++	pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense;
++	pxmitpriv->vcs = pregistrypriv->vcs_type;
++	pxmitpriv->vcs_type = pregistrypriv->vcs_type;
++	/* pxmitpriv->rts_thresh = pregistrypriv->rts_thresh; */
++	pxmitpriv->frag_len = pregistrypriv->frag_thresh;
++
++	/* security_priv */
++	/* rtw_get_encrypt_decrypt_from_registrypriv(padapter); */
++	psecuritypriv->binstallGrpkey = _FAIL;
++#ifdef CONFIG_GTK_OL
++	psecuritypriv->binstallKCK_KEK = _FAIL;
++#endif /* CONFIG_GTK_OL */
++	psecuritypriv->sw_encrypt = pregistrypriv->software_encrypt;
++	psecuritypriv->sw_decrypt = pregistrypriv->software_decrypt;
++
++	psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
++	psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
++
++	psecuritypriv->dot11PrivacyKeyIndex = 0;
++
++	psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
++	psecuritypriv->dot118021XGrpKeyid = 1;
++
++	psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;
++	psecuritypriv->ndisencryptstatus = Ndis802_11WEPDisabled;
++	psecuritypriv->dot118021x_bmc_cam_id = INVALID_SEC_MAC_CAM_ID;
++
++
++	/* pwrctrl_priv */
++
++
++	/* registry_priv */
++	rtw_init_registrypriv_dev_network(padapter);
++	rtw_update_registrypriv_dev_network(padapter);
++
++
++	/* hal_priv */
++	rtw_hal_def_value_init(padapter);
++
++#ifdef CONFIG_MCC_MODE
++	/* MCC parameter */
++	rtw_hal_mcc_parameter_init(padapter);
++#endif /* CONFIG_MCC_MODE */
++
++	/* misc. */
++	RTW_ENABLE_FUNC(padapter, DF_RX_BIT);
++	RTW_ENABLE_FUNC(padapter, DF_TX_BIT);
++	padapter->bLinkInfoDump = 0;
++	padapter->bNotifyChannelChange = _FALSE;
++#ifdef CONFIG_P2P
++	padapter->bShowGetP2PState = 1;
++#endif
++
++	/* for debug purpose */
++	padapter->fix_rate = 0xFF;
++	padapter->data_fb = 0;
++	padapter->fix_bw = 0xFF;
++	padapter->power_offset = 0;
++	padapter->rsvd_page_offset = 0;
++	padapter->rsvd_page_num = 0;
++#ifdef CONFIG_AP_MODE
++	padapter->bmc_tx_rate = pregistrypriv->bmc_tx_rate;
++	#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++	padapter->b2u_flags_ap_src = pregistrypriv->ap_src_b2u_flags;
++	padapter->b2u_flags_ap_fwd = pregistrypriv->ap_fwd_b2u_flags;
++	#endif
++#endif
++	padapter->driver_tx_bw_mode = pregistrypriv->tx_bw_mode;
++
++	padapter->driver_ampdu_spacing = 0xFF;
++	padapter->driver_rx_ampdu_factor =  0xFF;
++	padapter->driver_rx_ampdu_spacing = 0xFF;
++	padapter->fix_rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID;
++	padapter->fix_rx_ampdu_size = RX_AMPDU_SIZE_INVALID;
++#ifdef CONFIG_TX_AMSDU
++	padapter->tx_amsdu = 2;
++	padapter->tx_amsdu_rate = 400;
++#endif
++	padapter->driver_tx_max_agg_num = 0xFF;
++#ifdef DBG_RX_COUNTER_DUMP
++	padapter->dump_rx_cnt_mode = 0;
++	padapter->drv_rx_cnt_ok = 0;
++	padapter->drv_rx_cnt_crcerror = 0;
++	padapter->drv_rx_cnt_drop = 0;
++#endif
++#ifdef CONFIG_RTW_NAPI
++	padapter->napi_state = NAPI_DISABLE;
++#endif
++
++#ifdef CONFIG_RTW_ACS
++	if (pregistrypriv->acs_mode)
++		rtw_acs_start(padapter);
++	else
++		rtw_acs_stop(padapter);
++#endif
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++	if (pregistrypriv->nm_mode)
++		rtw_nm_enable(padapter);
++	else
++		rtw_nm_disable(padapter);
++#endif
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
++	ATOMIC_SET(&padapter->tbtx_tx_pause, _FALSE);
++	ATOMIC_SET(&padapter->tbtx_remove_tx_pause, _FALSE);
++	padapter->tbtx_capability = _TRUE;
++#endif
++
++	return ret;
++}
++#ifdef CONFIG_CLIENT_PORT_CFG
++extern void rtw_clt_port_init(struct clt_port_t  *cltp);
++extern void rtw_clt_port_deinit(struct clt_port_t  *cltp);
++#endif
++
++struct dvobj_priv *devobj_init(void)
++{
++	struct dvobj_priv *pdvobj = NULL;
++
++	pdvobj = (struct dvobj_priv *)rtw_zmalloc(sizeof(*pdvobj));
++	if (pdvobj == NULL)
++		return NULL;
++
++	_rtw_mutex_init(&pdvobj->hw_init_mutex);
++	_rtw_mutex_init(&pdvobj->h2c_fwcmd_mutex);
++	_rtw_mutex_init(&pdvobj->setch_mutex);
++	_rtw_mutex_init(&pdvobj->setbw_mutex);
++	_rtw_mutex_init(&pdvobj->rf_read_reg_mutex);
++	_rtw_mutex_init(&pdvobj->ioctrl_mutex);
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++	_rtw_mutex_init(&pdvobj->sd_indirect_access_mutex);
++#endif
++#ifdef CONFIG_SYSON_INDIRECT_ACCESS
++	_rtw_mutex_init(&pdvobj->syson_indirect_access_mutex);
++#endif
++#ifdef CONFIG_RTW_CUSTOMER_STR
++	_rtw_mutex_init(&pdvobj->customer_str_mutex);
++	_rtw_memset(pdvobj->customer_str, 0xFF, RTW_CUSTOMER_STR_LEN);
++#endif
++#ifdef CONFIG_PROTSEL_PORT
++	_rtw_mutex_init(&pdvobj->protsel_port.mutex);
++#endif
++#ifdef CONFIG_PROTSEL_ATIMDTIM
++	_rtw_mutex_init(&pdvobj->protsel_atimdtim.mutex);
++#endif
++#ifdef CONFIG_PROTSEL_MACSLEEP
++	_rtw_mutex_init(&pdvobj->protsel_macsleep.mutex);
++#endif
++
++	pdvobj->processing_dev_remove = _FALSE;
++
++	ATOMIC_SET(&pdvobj->disable_func, 0);
++
++	rtw_macid_ctl_init(&pdvobj->macid_ctl);
++#ifdef CONFIG_CLIENT_PORT_CFG
++	rtw_clt_port_init(&pdvobj->clt_port);
++#endif
++	_rtw_spinlock_init(&pdvobj->cam_ctl.lock);
++	_rtw_mutex_init(&pdvobj->cam_ctl.sec_cam_access_mutex);
++#if defined(RTK_129X_PLATFORM) && defined(CONFIG_PCI_HCI)
++	_rtw_spinlock_init(&pdvobj->io_reg_lock);
++#endif
++#ifdef CONFIG_MBSSID_CAM
++	rtw_mbid_cam_init(pdvobj);
++#endif
++
++#ifdef CONFIG_AP_MODE
++	#ifdef CONFIG_SUPPORT_MULTI_BCN
++	pdvobj->nr_ap_if = 0;
++	pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL; /* default value is equal to the default beacon_interval (100ms) */
++	_rtw_init_queue(&pdvobj->ap_if_q);
++	pdvobj->vap_map = 0;
++	#endif /*CONFIG_SUPPORT_MULTI_BCN*/
++	#ifdef CONFIG_SWTIMER_BASED_TXBCN
++	rtw_init_timer(&(pdvobj->txbcn_timer), NULL, tx_beacon_timer_handlder, pdvobj);
++	#endif
++#endif
++
++	rtw_init_timer(&(pdvobj->dynamic_chk_timer), NULL, rtw_dynamic_check_timer_handlder, pdvobj);
++	rtw_init_timer(&(pdvobj->periodic_tsf_update_end_timer), NULL, rtw_hal_periodic_tsf_update_end_timer_hdl, pdvobj);
++
++#ifdef CONFIG_MCC_MODE
++	_rtw_mutex_init(&(pdvobj->mcc_objpriv.mcc_mutex));
++	_rtw_mutex_init(&(pdvobj->mcc_objpriv.mcc_tsf_req_mutex));
++	_rtw_mutex_init(&(pdvobj->mcc_objpriv.mcc_dbg_reg_mutex));
++	_rtw_spinlock_init(&pdvobj->mcc_objpriv.mcc_lock);
++#endif /* CONFIG_MCC_MODE */
++
++#ifdef CONFIG_RTW_NAPI_DYNAMIC
++	pdvobj->en_napi_dynamic = 0;
++#endif /* CONFIG_RTW_NAPI_DYNAMIC */
++
++
++#ifdef CONFIG_RTW_TPT_MODE
++	pdvobj->tpt_mode = 0;
++	pdvobj->edca_be_ul = 0x5ea42b;
++	pdvobj->edca_be_dl = 0x00a42b;
++#endif 
++	pdvobj->scan_deny = _FALSE;
++
++	return pdvobj;
++
++}
++
++void devobj_deinit(struct dvobj_priv *pdvobj)
++{
++	if (!pdvobj)
++		return;
++
++	/* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */
++#if defined(CONFIG_IOCTL_CFG80211)
++	rtw_cfg80211_dev_res_free(pdvobj);
++#endif
++
++#ifdef CONFIG_MCC_MODE
++	_rtw_mutex_free(&(pdvobj->mcc_objpriv.mcc_mutex));
++	_rtw_mutex_free(&(pdvobj->mcc_objpriv.mcc_tsf_req_mutex));
++	_rtw_mutex_free(&(pdvobj->mcc_objpriv.mcc_dbg_reg_mutex));
++	_rtw_spinlock_free(&pdvobj->mcc_objpriv.mcc_lock);
++#endif /* CONFIG_MCC_MODE */
++
++	_rtw_mutex_free(&pdvobj->hw_init_mutex);
++	_rtw_mutex_free(&pdvobj->h2c_fwcmd_mutex);
++
++#ifdef CONFIG_RTW_CUSTOMER_STR
++	_rtw_mutex_free(&pdvobj->customer_str_mutex);
++#endif
++#ifdef CONFIG_PROTSEL_PORT
++	_rtw_mutex_free(&pdvobj->protsel_port.mutex);
++#endif
++#ifdef CONFIG_PROTSEL_ATIMDTIM
++	_rtw_mutex_free(&pdvobj->protsel_atimdtim.mutex);
++#endif
++#ifdef CONFIG_PROTSEL_MACSLEEP
++	_rtw_mutex_free(&pdvobj->protsel_macsleep.mutex);
++#endif
++
++	_rtw_mutex_free(&pdvobj->setch_mutex);
++	_rtw_mutex_free(&pdvobj->setbw_mutex);
++	_rtw_mutex_free(&pdvobj->rf_read_reg_mutex);
++	_rtw_mutex_free(&pdvobj->ioctrl_mutex);
++#ifdef CONFIG_SDIO_INDIRECT_ACCESS
++	_rtw_mutex_free(&pdvobj->sd_indirect_access_mutex);
++#endif
++#ifdef CONFIG_SYSON_INDIRECT_ACCESS
++	_rtw_mutex_free(&pdvobj->syson_indirect_access_mutex);
++#endif
++
++	rtw_macid_ctl_deinit(&pdvobj->macid_ctl);
++#ifdef CONFIG_CLIENT_PORT_CFG
++	rtw_clt_port_deinit(&pdvobj->clt_port);
++#endif
++
++	_rtw_spinlock_free(&pdvobj->cam_ctl.lock);
++	_rtw_mutex_free(&pdvobj->cam_ctl.sec_cam_access_mutex);
++
++#if defined(RTK_129X_PLATFORM) && defined(CONFIG_PCI_HCI)
++	_rtw_spinlock_free(&pdvobj->io_reg_lock);
++#endif
++#ifdef CONFIG_MBSSID_CAM
++	rtw_mbid_cam_deinit(pdvobj);
++#endif
++#ifdef CONFIG_SUPPORT_MULTI_BCN
++	_rtw_spinlock_free(&(pdvobj->ap_if_q.lock));
++#endif
++	rtw_mfree((u8 *)pdvobj, sizeof(*pdvobj));
++}
++
++inline u8 rtw_rtnl_lock_needed(struct dvobj_priv *dvobj)
++{
++	if (dvobj->rtnl_lock_holder && dvobj->rtnl_lock_holder == current)
++		return 0;
++	return 1;
++}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))
++static inline int rtnl_is_locked(void)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 17))
++	if (unlikely(rtnl_trylock())) {
++		rtnl_unlock();
++#else
++	if (unlikely(down_trylock(&rtnl_sem) == 0)) {
++		up(&rtnl_sem);
++#endif
++		return 0;
++	}
++	return 1;
++}
++#endif
++
++inline void rtw_set_rtnl_lock_holder(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl)
++{
++	rtw_warn_on(!rtnl_is_locked());
++
++	if (!thd_hdl || rtnl_is_locked())
++		dvobj->rtnl_lock_holder = thd_hdl;
++
++	if (dvobj->rtnl_lock_holder && 0)
++		RTW_INFO("rtnl_lock_holder: %s:%d\n", current->comm, current->pid);
++}
++
++u8 rtw_reset_drv_sw(_adapter *padapter)
++{
++	u8	ret8 = _SUCCESS;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++
++	/* hal_priv */
++	rtw_hal_def_value_init(padapter);
++
++	RTW_ENABLE_FUNC(padapter, DF_RX_BIT);
++	RTW_ENABLE_FUNC(padapter, DF_TX_BIT);
++
++	padapter->bLinkInfoDump = 0;
++
++	padapter->xmitpriv.tx_pkts = 0;
++	padapter->recvpriv.rx_pkts = 0;
++
++	pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
++
++	/* pmlmepriv->LinkDetectInfo.TrafficBusyState = _FALSE; */
++	pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0;
++	pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0;
++
++	_clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING);
++
++#ifdef DBG_CONFIG_ERROR_DETECT
++	if (is_primary_adapter(padapter))
++		rtw_hal_sreset_reset_value(padapter);
++#endif
++	pwrctrlpriv->pwr_state_check_cnts = 0;
++
++	/* mlmeextpriv */
++	mlmeext_set_scan_state(&padapter->mlmeextpriv, SCAN_DISABLE);
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++	rtw_set_signal_stat_timer(&padapter->recvpriv);
++#endif
++
++	return ret8;
++}
++
++
++u8 rtw_init_drv_sw(_adapter *padapter)
++{
++	u8	ret8 = _SUCCESS;
++
++#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++#endif
++
++	#if defined(CONFIG_AP_MODE) && defined(CONFIG_SUPPORT_MULTI_BCN)
++	_rtw_init_listhead(&padapter->list);
++	#ifdef CONFIG_FW_HANDLE_TXBCN
++	padapter->vap_id = CONFIG_LIMITED_AP_NUM;
++	if (is_primary_adapter(padapter))
++		adapter_to_dvobj(padapter)->vap_tbtt_rpt_map = adapter_to_regsty(padapter)->fw_tbtt_rpt;
++	#endif
++	#endif
++
++	#ifdef CONFIG_CLIENT_PORT_CFG
++	padapter->client_id = MAX_CLIENT_PORT_NUM;
++	padapter->client_port = CLT_PORT_INVALID;
++	#endif
++
++	if (is_primary_adapter(padapter)) {
++		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++		struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++
++		dvobj->macid_ctl.num = rtw_min(hal_spec->macid_num, MACID_NUM_SW_LIMIT);
++		dvobj->macid_ctl.macid_cap = hal_spec->macid_cap;
++		dvobj->macid_ctl.macid_txrpt = hal_spec->macid_txrpt;
++		dvobj->macid_ctl.macid_txrpt_pgsz = hal_spec->macid_txrpt_pgsz;
++		dvobj->cam_ctl.sec_cap = hal_spec->sec_cap;
++		dvobj->cam_ctl.num = rtw_min(hal_spec->sec_cam_ent_num, SEC_CAM_ENT_NUM_SW_LIMIT);
++		
++		dvobj->wow_ctl.wow_cap = hal_spec->wow_cap;
++
++		#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
++		dvobj->tx_aval_int_thr_mode = 2; /*setting by max tx length*/
++		dvobj->tx_aval_int_thr_value = 0;
++		#endif /*CONFIG_SDIO_TX_ENABLE_AVAL_INT*/
++		
++		#if CONFIG_TX_AC_LIFETIME
++		{
++			struct registry_priv *regsty = adapter_to_regsty(padapter);
++			int i;
++
++			dvobj->tx_aclt_flags = regsty->tx_aclt_flags;
++			for (i = 0; i < TX_ACLT_CONF_NUM; i++) {
++				dvobj->tx_aclt_confs[i].en = regsty->tx_aclt_confs[i].en;
++				dvobj->tx_aclt_confs[i].vo_vi
++					= regsty->tx_aclt_confs[i].vo_vi / (hal_spec->tx_aclt_unit_factor * 32);
++				if (dvobj->tx_aclt_confs[i].vo_vi > 0xFFFF)
++					dvobj->tx_aclt_confs[i].vo_vi = 0xFFFF;
++				dvobj->tx_aclt_confs[i].be_bk
++					= regsty->tx_aclt_confs[i].be_bk / (hal_spec->tx_aclt_unit_factor * 32);
++				if (dvobj->tx_aclt_confs[i].be_bk > 0xFFFF)
++					dvobj->tx_aclt_confs[i].be_bk = 0xFFFF;
++			}
++
++			dvobj->tx_aclt_force_val.en = 0xFF;
++		}
++		#endif
++	}
++
++	ret8 = rtw_init_default_value(padapter);
++
++	if ((rtw_init_cmd_priv(&padapter->cmdpriv)) == _FAIL) {
++		ret8 = _FAIL;
++		goto exit;
++	}
++
++	padapter->cmdpriv.padapter = padapter;
++
++	if ((rtw_init_evt_priv(&padapter->evtpriv)) == _FAIL) {
++		ret8 = _FAIL;
++		goto exit;
++	}
++
++	if (is_primary_adapter(padapter))
++		rtw_rfctl_init(padapter);
++
++	if (is_primary_adapter(padapter)) {
++		if (rtw_hal_rfpath_init(padapter) == _FAIL) {
++			ret8 = _FAIL;
++			goto exit;
++		}
++		if (rtw_hal_trxnss_init(padapter) == _FAIL) {
++			ret8 = _FAIL;
++			goto exit;
++		}
++	}
++
++	if (rtw_init_mlme_priv(padapter) == _FAIL) {
++		ret8 = _FAIL;
++		goto exit;
++	}
++
++#ifdef CONFIG_P2P
++	rtw_init_wifidirect_timers(padapter);
++	init_wifidirect_info(padapter, P2P_ROLE_DISABLE);
++	reset_global_wifidirect_info(padapter);
++	#ifdef CONFIG_IOCTL_CFG80211
++	rtw_init_cfg80211_wifidirect_info(padapter);
++	#endif
++#ifdef CONFIG_WFD
++	if (rtw_init_wifi_display_info(padapter) == _FAIL)
++		RTW_ERR("Can't init init_wifi_display_info\n");
++#endif
++#endif /* CONFIG_P2P */
++
++	if (init_mlme_ext_priv(padapter) == _FAIL) {
++		ret8 = _FAIL;
++		goto exit;
++	}
++
++#ifdef CONFIG_TDLS
++	if (rtw_init_tdls_info(padapter) == _FAIL) {
++		RTW_INFO("Can't rtw_init_tdls_info\n");
++		ret8 = _FAIL;
++		goto exit;
++	}
++#endif /* CONFIG_TDLS */
++
++#ifdef CONFIG_RTW_MESH
++	rtw_mesh_cfg_init(padapter);
++#endif
++
++	if (_rtw_init_xmit_priv(&padapter->xmitpriv, padapter) == _FAIL) {
++		RTW_INFO("Can't _rtw_init_xmit_priv\n");
++		ret8 = _FAIL;
++		goto exit;
++	}
++
++	if (_rtw_init_recv_priv(&padapter->recvpriv, padapter) == _FAIL) {
++		RTW_INFO("Can't _rtw_init_recv_priv\n");
++		ret8 = _FAIL;
++		goto exit;
++	}
++	/* add for CONFIG_IEEE80211W, none 11w also can use */
++	_rtw_spinlock_init(&padapter->security_key_mutex);
++
++	/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
++	/* _rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof (struct security_priv)); */
++
++	if (_rtw_init_sta_priv(&padapter->stapriv) == _FAIL) {
++		RTW_INFO("Can't _rtw_init_sta_priv\n");
++		ret8 = _FAIL;
++		goto exit;
++	}
++
++	padapter->setband = WIFI_FREQUENCY_BAND_AUTO;
++	padapter->fix_rate = 0xFF;
++	padapter->power_offset = 0;
++	padapter->rsvd_page_offset = 0;
++	padapter->rsvd_page_num = 0;
++
++	padapter->data_fb = 0;
++	padapter->fix_rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID;
++	padapter->fix_rx_ampdu_size = RX_AMPDU_SIZE_INVALID;
++#ifdef DBG_RX_COUNTER_DUMP
++	padapter->dump_rx_cnt_mode = 0;
++	padapter->drv_rx_cnt_ok = 0;
++	padapter->drv_rx_cnt_crcerror = 0;
++	padapter->drv_rx_cnt_drop = 0;
++#endif
++	rtw_init_bcmc_stainfo(padapter);
++
++	rtw_init_pwrctrl_priv(padapter);
++
++	/* _rtw_memset((u8 *)&padapter->qospriv, 0, sizeof (struct qos_priv)); */ /* move to mlme_priv */
++
++#ifdef CONFIG_MP_INCLUDED
++	if (init_mp_priv(padapter) == _FAIL)
++		RTW_INFO("%s: initialize MP private data Fail!\n", __func__);
++#endif
++
++	rtw_hal_dm_init(padapter);
++#ifdef CONFIG_RTW_SW_LED
++	rtw_hal_sw_led_init(padapter);
++#endif
++#ifdef DBG_CONFIG_ERROR_DETECT
++	rtw_hal_sreset_init(padapter);
++#endif
++
++#ifdef CONFIG_WAPI_SUPPORT
++	padapter->WapiSupport = true; /* set true temp, will revise according to Efuse or Registry value later. */
++	rtw_wapi_init(padapter);
++#endif
++
++#ifdef CONFIG_BR_EXT
++	_rtw_spinlock_init(&padapter->br_ext_lock);
++#endif /* CONFIG_BR_EXT */
++
++#ifdef CONFIG_BEAMFORMING
++#ifdef RTW_BEAMFORMING_VERSION_2
++	rtw_bf_init(padapter);
++#endif /* RTW_BEAMFORMING_VERSION_2 */
++#endif /* CONFIG_BEAMFORMING */
++
++#ifdef CONFIG_RTW_REPEATER_SON
++	init_rtw_rson_data(adapter_to_dvobj(padapter));
++#endif
++
++#ifdef CONFIG_RTW_80211K
++	rtw_init_rm(padapter);
++#endif
++
++#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++	memset(pwdev_priv->pno_mac_addr, 0xFF, ETH_ALEN);
++#endif
++
++exit:
++
++
++
++	return ret8;
++
++}
++
++#ifdef CONFIG_WOWLAN
++void rtw_cancel_dynamic_chk_timer(_adapter *padapter)
++{
++	_cancel_timer_ex(&adapter_to_dvobj(padapter)->dynamic_chk_timer);
++}
++#endif
++
++void rtw_cancel_all_timer(_adapter *padapter)
++{
++
++	_cancel_timer_ex(&padapter->mlmepriv.assoc_timer);
++
++	_cancel_timer_ex(&padapter->mlmepriv.scan_to_timer);
++
++#ifdef CONFIG_DFS_MASTER
++	_cancel_timer_ex(&adapter_to_rfctl(padapter)->radar_detect_timer);
++#endif
++
++	_cancel_timer_ex(&adapter_to_dvobj(padapter)->dynamic_chk_timer);
++	_cancel_timer_ex(&adapter_to_dvobj(padapter)->periodic_tsf_update_end_timer);
++#ifdef CONFIG_RTW_SW_LED
++	/* cancel sw led timer */
++	rtw_hal_sw_led_deinit(padapter);
++#endif
++	_cancel_timer_ex(&(adapter_to_pwrctl(padapter)->pwr_state_check_timer));
++
++#ifdef CONFIG_TX_AMSDU
++	_cancel_timer_ex(&padapter->xmitpriv.amsdu_bk_timer);
++	_cancel_timer_ex(&padapter->xmitpriv.amsdu_be_timer);
++	_cancel_timer_ex(&padapter->xmitpriv.amsdu_vo_timer);
++	_cancel_timer_ex(&padapter->xmitpriv.amsdu_vi_timer);
++#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++#ifdef CONFIG_P2P
++	_cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer);
++#endif /* CONFIG_P2P */
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++#ifdef CONFIG_SET_SCAN_DENY_TIMER
++	_cancel_timer_ex(&padapter->mlmepriv.set_scan_deny_timer);
++	rtw_clear_scan_deny(padapter);
++#endif
++
++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
++	_cancel_timer_ex(&padapter->recvpriv.signal_stat_timer);
++#endif
++
++#ifdef CONFIG_LPS_RPWM_TIMER
++	_cancel_timer_ex(&(adapter_to_pwrctl(padapter)->pwr_rpwm_timer));
++#endif /* CONFIG_LPS_RPWM_TIMER */
++
++#ifdef CONFIG_RTW_TOKEN_BASED_XMIT	
++	_cancel_timer_ex(&padapter->mlmeextpriv.tbtx_xmit_timer);
++	_cancel_timer_ex(&padapter->mlmeextpriv.tbtx_token_dispatch_timer);
++#endif
++
++	/* cancel dm timer */
++	rtw_hal_dm_deinit(padapter);
++
++#ifdef CONFIG_PLATFORM_FS_MX61
++	msleep(50);
++#endif
++}
++
++u8 rtw_free_drv_sw(_adapter *padapter)
++{
++
++#ifdef CONFIG_WAPI_SUPPORT
++	rtw_wapi_free(padapter);
++#endif
++
++	/* we can call rtw_p2p_enable here, but: */
++	/* 1. rtw_p2p_enable may have IO operation */
++	/* 2. rtw_p2p_enable is bundled with wext interface */
++	#ifdef CONFIG_P2P
++	{
++		struct wifidirect_info *pwdinfo = &padapter->wdinfo;
++		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
++			_cancel_timer_ex(&pwdinfo->find_phase_timer);
++			_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
++			_cancel_timer_ex(&pwdinfo->pre_tx_scan_timer);
++			#ifdef CONFIG_CONCURRENT_MODE
++			_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);
++			#endif /* CONFIG_CONCURRENT_MODE */
++			rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE);
++		}
++	}
++	#endif
++	/* add for CONFIG_IEEE80211W, none 11w also can use */
++	_rtw_spinlock_free(&padapter->security_key_mutex);
++
++#ifdef CONFIG_BR_EXT
++	_rtw_spinlock_free(&padapter->br_ext_lock);
++#endif /* CONFIG_BR_EXT */
++
++	free_mlme_ext_priv(&padapter->mlmeextpriv);
++
++#ifdef CONFIG_TDLS
++	/* rtw_free_tdls_info(&padapter->tdlsinfo); */
++#endif /* CONFIG_TDLS */
++
++#ifdef CONFIG_RTW_80211K
++	rtw_free_rm_priv(padapter);
++#endif
++
++	rtw_free_cmd_priv(&padapter->cmdpriv);
++
++	rtw_free_evt_priv(&padapter->evtpriv);
++
++	rtw_free_mlme_priv(&padapter->mlmepriv);
++
++	if (is_primary_adapter(padapter))
++		rtw_rfctl_deinit(padapter);
++
++	/* free_io_queue(padapter); */
++
++	_rtw_free_xmit_priv(&padapter->xmitpriv);
++
++	_rtw_free_sta_priv(&padapter->stapriv); /* will free bcmc_stainfo here */
++
++	_rtw_free_recv_priv(&padapter->recvpriv);
++
++	rtw_free_pwrctrl_priv(padapter);
++
++	/* rtw_mfree((void *)padapter, sizeof (padapter)); */
++
++	rtw_hal_free_data(padapter);
++
++	return _SUCCESS;
++
++}
++void rtw_intf_start(_adapter *adapter)
++{
++	if (adapter->intf_start)
++		adapter->intf_start(adapter);
++	GET_HAL_DATA(adapter)->intf_start = 1;
++}
++void rtw_intf_stop(_adapter *adapter)
++{
++	if (adapter->intf_stop)
++		adapter->intf_stop(adapter);
++	GET_HAL_DATA(adapter)->intf_start = 0;
++}
++
++#ifdef CONFIG_CONCURRENT_MODE
++#ifndef CONFIG_NEW_NETDEV_HDL
++int _netdev_vir_if_open(struct net_device *pnetdev)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++	_adapter *primary_padapter = GET_PRIMARY_ADAPTER(padapter);
++
++	RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
++
++	if (!primary_padapter)
++		goto _netdev_virtual_iface_open_error;
++
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++	if (padapter->bup == _FALSE) {
++		u8 mac[ETH_ALEN];
++
++		/* get mac address from primary_padapter */
++		if (primary_padapter->bup == _FALSE)
++			rtw_macaddr_cfg(adapter_mac_addr(primary_padapter), get_hal_mac_addr(primary_padapter));
++
++		_rtw_memcpy(mac, adapter_mac_addr(primary_padapter), ETH_ALEN);
++
++		/*
++		* If the BIT1 is 0, the address is universally administered.
++		* If it is 1, the address is locally administered
++		*/
++		mac[0] |= BIT(1);
++
++		_rtw_memcpy(adapter_mac_addr(padapter), mac, ETH_ALEN);
++
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++		rtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter));
++#endif
++		rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));
++		_rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN);
++	}
++#endif /*CONFIG_PLATFORM_INTEL_BYT*/
++
++	if (primary_padapter->bup == _FALSE || !rtw_is_hw_init_completed(primary_padapter))
++		_netdev_open(primary_padapter->pnetdev);
++
++	if (padapter->bup == _FALSE && primary_padapter->bup == _TRUE &&
++	    rtw_is_hw_init_completed(primary_padapter)) {
++#if 0 /*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/
++		rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */
++#endif
++
++	}
++
++	if (padapter->bup == _FALSE) {
++		if (rtw_start_drv_threads(padapter) == _FAIL)
++			goto _netdev_virtual_iface_open_error;
++	}
++
++#ifdef CONFIG_RTW_NAPI
++	if (padapter->napi_state == NAPI_DISABLE) {
++		napi_enable(&padapter->napi);
++		padapter->napi_state = NAPI_ENABLE;
++	}
++#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++	rtw_cfg80211_init_wiphy(padapter);
++	rtw_cfg80211_init_wdev_data(padapter);
++#endif
++
++	padapter->bup = _TRUE;
++
++	padapter->net_closed = _FALSE;
++
++	rtw_netif_wake_queue(pnetdev);
++
++	RTW_INFO(FUNC_NDEV_FMT" (bup=%d) exit\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
++
++	return 0;
++
++_netdev_virtual_iface_open_error:
++
++	padapter->bup = _FALSE;
++
++#ifdef CONFIG_RTW_NAPI
++	if(padapter->napi_state == NAPI_ENABLE) {
++		napi_disable(&padapter->napi);
++		padapter->napi_state = NAPI_DISABLE;
++	}
++#endif
++
++	rtw_netif_carrier_off(pnetdev);
++	rtw_netif_stop_queue(pnetdev);
++
++	return -1;
++
++}
++
++int netdev_vir_if_open(struct net_device *pnetdev)
++{
++	int ret;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++
++	_enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
++	ret = _netdev_vir_if_open(pnetdev);
++	_exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
++
++#ifdef CONFIG_AUTO_AP_MODE
++	/* if(padapter->iface_id == 2) */
++	/*	rtw_start_auto_ap(padapter); */
++#endif
++
++	return ret;
++}
++
++static int netdev_vir_if_close(struct net_device *pnetdev)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++
++	RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
++	padapter->net_closed = _TRUE;
++	pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
++
++	if (pnetdev)
++		rtw_netif_stop_queue(pnetdev);
++
++#ifdef CONFIG_P2P
++	if (!rtw_p2p_chk_role(&padapter->wdinfo, P2P_ROLE_DISABLE))
++		rtw_p2p_enable(padapter, P2P_ROLE_DISABLE);
++#endif
++
++#ifdef CONFIG_IOCTL_CFG80211
++	rtw_scan_abort(padapter);
++	rtw_cfg80211_wait_scan_req_empty(padapter, 200);
++	adapter_wdev_data(padapter)->bandroid_scan = _FALSE;
++#endif
++
++	return 0;
++}
++#endif /*#ifndef CONFIG_NEW_NETDEV_HDL*/
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
++static const struct net_device_ops rtw_netdev_vir_if_ops = {
++	.ndo_init = rtw_ndev_init,
++	.ndo_uninit = rtw_ndev_uninit,
++	#ifdef CONFIG_NEW_NETDEV_HDL
++	.ndo_open = netdev_open,
++	.ndo_stop = netdev_close,
++	#else
++	.ndo_open = netdev_vir_if_open,
++	.ndo_stop = netdev_vir_if_close,
++	#endif
++	.ndo_start_xmit = rtw_xmit_entry,
++	.ndo_set_mac_address = rtw_net_set_mac_address,
++	.ndo_get_stats = rtw_net_get_stats,
++	.ndo_do_ioctl = rtw_ioctl,
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	.ndo_select_queue	= rtw_select_queue,
++#endif
++};
++#endif
++
++static void rtw_hook_vir_if_ops(struct net_device *ndev)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
++	ndev->netdev_ops = &rtw_netdev_vir_if_ops;
++#else
++	ndev->init = rtw_ndev_init;
++	ndev->uninit = rtw_ndev_uninit;
++	#ifdef CONFIG_NEW_NETDEV_HDL
++	ndev->open = netdev_open;
++	ndev->stop = netdev_close;
++	#else
++	ndev->open = netdev_vir_if_open;
++	ndev->stop = netdev_vir_if_close;
++	#endif
++
++	ndev->set_mac_address = rtw_net_set_mac_address;
++#endif
++}
++_adapter *rtw_drv_add_vir_if(_adapter *primary_padapter,
++	void (*set_intf_ops)(_adapter *primary_padapter, struct _io_ops *pops))
++{
++	int res = _FAIL;
++	_adapter *padapter = NULL;
++	struct dvobj_priv *pdvobjpriv;
++	u8 mac[ETH_ALEN];
++
++	/****** init adapter ******/
++	padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter));
++	if (padapter == NULL)
++		goto exit;
++
++	if (loadparam(padapter) != _SUCCESS)
++		goto free_adapter;
++
++	_rtw_memcpy(padapter, primary_padapter, sizeof(_adapter));
++
++	/*  */
++	padapter->bup = _FALSE;
++	padapter->net_closed = _TRUE;
++	padapter->dir_dev = NULL;
++	padapter->dir_odm = NULL;
++
++	/*set adapter_type/iface type*/
++	padapter->isprimary = _FALSE;
++	padapter->adapter_type = VIRTUAL_ADAPTER;
++
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++	padapter->hw_port = HW_PORT0;
++#else
++	padapter->hw_port = HW_PORT1;
++#endif
++
++
++	/****** hook vir if into dvobj ******/
++	pdvobjpriv = adapter_to_dvobj(padapter);
++	padapter->iface_id = pdvobjpriv->iface_nums;
++	pdvobjpriv->padapters[pdvobjpriv->iface_nums++] = padapter;
++
++	padapter->intf_start = primary_padapter->intf_start;
++	padapter->intf_stop = primary_padapter->intf_stop;
++
++	/* step init_io_priv */
++	if ((rtw_init_io_priv(padapter, set_intf_ops)) == _FAIL) {
++		goto free_adapter;
++	}
++
++	/*init drv data*/
++	if (rtw_init_drv_sw(padapter) != _SUCCESS)
++		goto free_drv_sw;
++
++
++	/*get mac address from primary_padapter*/
++	_rtw_memcpy(mac, adapter_mac_addr(primary_padapter), ETH_ALEN);
++
++	/*
++	* If the BIT1 is 0, the address is universally administered.
++	* If it is 1, the address is locally administered
++	*/
++	mac[0] |= BIT(1);
++	if (padapter->iface_id > IFACE_ID1)
++		mac[0] ^= ((padapter->iface_id)<<2);
++
++	_rtw_memcpy(adapter_mac_addr(padapter), mac, ETH_ALEN);
++	/* update mac-address to mbsid-cam cache*/
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++	rtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter));
++#endif
++	RTW_INFO("%s if%d mac_addr : "MAC_FMT"\n", __func__, padapter->iface_id + 1, MAC_ARG(adapter_mac_addr(padapter)));
++#ifdef CONFIG_P2P
++	rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));
++#endif
++
++	rtw_led_set_ctl_en_mask_virtual(padapter);
++	rtw_led_set_iface_en(padapter, 1);
++
++	res = _SUCCESS;
++
++free_drv_sw:
++	if (res != _SUCCESS && padapter)
++		rtw_free_drv_sw(padapter);
++free_adapter:
++	if (res != _SUCCESS && padapter) {
++		rtw_vmfree((u8 *)padapter, sizeof(*padapter));
++		padapter = NULL;
++	}
++exit:
++	return padapter;
++}
++
++void rtw_drv_stop_vir_if(_adapter *padapter)
++{
++	struct net_device *pnetdev = NULL;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++	if (padapter == NULL)
++		return;
++	RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(padapter));
++
++	pnetdev = padapter->pnetdev;
++
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
++		rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY);
++
++#ifdef CONFIG_AP_MODE
++	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
++		free_mlme_ap_info(padapter);
++		#ifdef CONFIG_HOSTAPD_MLME
++		hostapd_mode_unload(padapter);
++		#endif
++	}
++#endif
++
++	if (padapter->bup == _TRUE) {
++		#ifdef CONFIG_XMIT_ACK
++		if (padapter->xmitpriv.ack_tx)
++			rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP);
++		#endif
++
++		rtw_intf_stop(padapter);
++	#ifndef CONFIG_NEW_NETDEV_HDL
++		rtw_stop_drv_threads(padapter);
++	#endif
++		padapter->bup = _FALSE;
++	}
++	#ifdef CONFIG_NEW_NETDEV_HDL
++	rtw_stop_drv_threads(padapter);
++	#endif
++	/* cancel timer after thread stop */
++	rtw_cancel_all_timer(padapter);
++}
++
++void rtw_drv_free_vir_if(_adapter *padapter)
++{
++	if (padapter == NULL)
++		return;
++
++	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++	rtw_free_drv_sw(padapter);
++
++	/* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */
++	rtw_os_ndev_free(padapter);
++
++	rtw_vmfree((u8 *)padapter, sizeof(_adapter));
++}
++
++
++void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj)
++{
++	int i;
++
++	for (i = VIF_START_ID; i < dvobj->iface_nums; i++)
++		rtw_drv_stop_vir_if(dvobj->padapters[i]);
++}
++
++void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj)
++{
++	int i;
++
++	for (i = VIF_START_ID; i < dvobj->iface_nums; i++)
++		rtw_drv_free_vir_if(dvobj->padapters[i]);
++}
++
++
++#endif /*end of CONFIG_CONCURRENT_MODE*/
++
++/* IPv4, IPv6 IP addr notifier */
++static int rtw_inetaddr_notifier_call(struct notifier_block *nb,
++				      unsigned long action, void *data)
++{
++	struct in_ifaddr *ifa = (struct in_ifaddr *)data;
++	struct net_device *ndev;
++	struct mlme_ext_priv *pmlmeext = NULL;
++	struct mlme_ext_info *pmlmeinfo = NULL;
++	_adapter *adapter = NULL;
++
++	if (!ifa || !ifa->ifa_dev || !ifa->ifa_dev->dev)
++		return NOTIFY_DONE;
++
++	ndev = ifa->ifa_dev->dev;
++
++	if (!is_rtw_ndev(ndev))
++		return NOTIFY_DONE;
++
++	adapter = (_adapter *)rtw_netdev_priv(ifa->ifa_dev->dev);
++
++	if (adapter == NULL)
++		return NOTIFY_DONE;
++
++	pmlmeext = &adapter->mlmeextpriv;
++	pmlmeinfo = &pmlmeext->mlmext_info;
++
++	switch (action) {
++	case NETDEV_UP:
++		_rtw_memcpy(pmlmeinfo->ip_addr, &ifa->ifa_address,
++					RTW_IP_ADDR_LEN);
++		RTW_DBG("%s[%s]: up IP: %pI4\n", __func__,
++					ifa->ifa_label, pmlmeinfo->ip_addr);
++	break;
++	case NETDEV_DOWN:
++		_rtw_memset(pmlmeinfo->ip_addr, 0, RTW_IP_ADDR_LEN);
++		RTW_DBG("%s[%s]: down IP: %pI4\n", __func__,
++					ifa->ifa_label, pmlmeinfo->ip_addr);
++	break;
++	default:
++		RTW_DBG("%s: default action\n", __func__);
++	break;
++	}
++	return NOTIFY_DONE;
++}
++
++#ifdef CONFIG_IPV6
++static int rtw_inet6addr_notifier_call(struct notifier_block *nb,
++				       unsigned long action, void *data)
++{
++	struct inet6_ifaddr *inet6_ifa = data;
++	struct net_device *ndev;
++	struct pwrctrl_priv *pwrctl = NULL;
++	struct mlme_ext_priv *pmlmeext = NULL;
++	struct mlme_ext_info *pmlmeinfo = NULL;
++	_adapter *adapter = NULL;
++
++	if (!inet6_ifa || !inet6_ifa->idev || !inet6_ifa->idev->dev)
++		return NOTIFY_DONE;
++
++	ndev = inet6_ifa->idev->dev;
++
++	if (!is_rtw_ndev(ndev))
++		return NOTIFY_DONE;
++
++	adapter = (_adapter *)rtw_netdev_priv(inet6_ifa->idev->dev);
++
++	if (adapter == NULL)
++		return NOTIFY_DONE;
++
++	pmlmeext =  &adapter->mlmeextpriv;
++	pmlmeinfo = &pmlmeext->mlmext_info;
++	pwrctl = adapter_to_pwrctl(adapter);
++
++	pmlmeext = &adapter->mlmeextpriv;
++	pmlmeinfo = &pmlmeext->mlmext_info;
++
++	switch (action) {
++	case NETDEV_UP:
++#ifdef CONFIG_WOWLAN
++		pwrctl->wowlan_ns_offload_en = _TRUE;
++#endif
++		_rtw_memcpy(pmlmeinfo->ip6_addr, &inet6_ifa->addr,
++					RTW_IPv6_ADDR_LEN);
++		RTW_DBG("%s: up IPv6 addrs: %pI6\n", __func__,
++					pmlmeinfo->ip6_addr);
++			break;
++	case NETDEV_DOWN:
++#ifdef CONFIG_WOWLAN
++		pwrctl->wowlan_ns_offload_en = _FALSE;
++#endif
++		_rtw_memset(pmlmeinfo->ip6_addr, 0, RTW_IPv6_ADDR_LEN);
++		RTW_DBG("%s: down IPv6 addrs: %pI6\n", __func__,
++					pmlmeinfo->ip6_addr);
++		break;
++	default:
++		RTW_DBG("%s: default action\n", __func__);
++		break;
++	}
++	return NOTIFY_DONE;
++}
++#endif
++
++static struct notifier_block rtw_inetaddr_notifier = {
++	.notifier_call = rtw_inetaddr_notifier_call
++};
++
++#ifdef CONFIG_IPV6
++static struct notifier_block rtw_inet6addr_notifier = {
++	.notifier_call = rtw_inet6addr_notifier_call
++};
++#endif
++
++void rtw_inetaddr_notifier_register(void)
++{
++	RTW_INFO("%s\n", __func__);
++	register_inetaddr_notifier(&rtw_inetaddr_notifier);
++#ifdef CONFIG_IPV6
++	register_inet6addr_notifier(&rtw_inet6addr_notifier);
++#endif
++}
++
++void rtw_inetaddr_notifier_unregister(void)
++{
++	RTW_INFO("%s\n", __func__);
++	unregister_inetaddr_notifier(&rtw_inetaddr_notifier);
++#ifdef CONFIG_IPV6
++	unregister_inet6addr_notifier(&rtw_inet6addr_notifier);
++#endif
++}
++
++int rtw_os_ndevs_register(struct dvobj_priv *dvobj)
++{
++	int i, status = _SUCCESS;
++	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
++	_adapter *adapter;
++
++#if defined(CONFIG_IOCTL_CFG80211)
++	if (rtw_cfg80211_dev_res_register(dvobj) != _SUCCESS) {
++		rtw_warn_on(1);
++		return _FAIL;
++	}
++#endif
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++
++		if (i >= CONFIG_IFACE_NUMBER) {
++			RTW_ERR("%s %d >= CONFIG_IFACE_NUMBER(%d)\n", __func__, i, CONFIG_IFACE_NUMBER);
++			rtw_warn_on(1);
++			continue;
++		}
++
++		adapter = dvobj->padapters[i];
++		if (adapter) {
++			char *name;
++
++			#ifdef CONFIG_RTW_DYNAMIC_NDEV
++			if (!is_primary_adapter(adapter))
++				continue;
++			#endif
++
++			if (adapter->iface_id == IFACE_ID0)
++				name = regsty->ifname;
++			else if (adapter->iface_id == IFACE_ID1)
++				name = regsty->if2name;
++			else
++				name = "wlan%d";
++
++			status = rtw_os_ndev_register(adapter, name);
++
++			if (status != _SUCCESS) {
++				rtw_warn_on(1);
++				break;
++			}
++		}
++	}
++
++	if (status != _SUCCESS) {
++		for (; i >= 0; i--) {
++			adapter = dvobj->padapters[i];
++			if (adapter)
++				rtw_os_ndev_unregister(adapter);
++		}
++	}
++
++#if defined(CONFIG_IOCTL_CFG80211)
++	if (status != _SUCCESS)
++		rtw_cfg80211_dev_res_unregister(dvobj);
++#endif
++	return status;
++}
++
++void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj)
++{
++	int i;
++	_adapter *adapter = NULL;
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		adapter = dvobj->padapters[i];
++
++		if (adapter == NULL)
++			continue;
++
++		rtw_os_ndev_unregister(adapter);
++	}
++
++#if defined(CONFIG_IOCTL_CFG80211)
++	rtw_cfg80211_dev_res_unregister(dvobj);
++#endif
++}
++
++/**
++ * rtw_os_ndevs_init - Allocate and register OS layer net devices and relating structures for @dvobj
++ * @dvobj: the dvobj on which this function applies
++ *
++ * Returns:
++ * _SUCCESS or _FAIL
++ */
++int rtw_os_ndevs_init(struct dvobj_priv *dvobj)
++{
++	int ret = _FAIL;
++
++	if (rtw_os_ndevs_alloc(dvobj) != _SUCCESS)
++		goto exit;
++
++	if (rtw_os_ndevs_register(dvobj) != _SUCCESS)
++		goto os_ndevs_free;
++
++	ret = _SUCCESS;
++
++os_ndevs_free:
++	if (ret != _SUCCESS)
++		rtw_os_ndevs_free(dvobj);
++exit:
++	return ret;
++}
++
++/**
++ * rtw_os_ndevs_deinit - Unregister and free OS layer net devices and relating structures for @dvobj
++ * @dvobj: the dvobj on which this function applies
++ */
++void rtw_os_ndevs_deinit(struct dvobj_priv *dvobj)
++{
++	rtw_os_ndevs_unregister(dvobj);
++	rtw_os_ndevs_free(dvobj);
++}
++
++#ifdef CONFIG_BR_EXT
++void netdev_br_init(struct net_device *netdev)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
++	rcu_read_lock();
++#endif
++
++	/* if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) */
++	{
++		/* struct net_bridge	*br = netdev->br_port->br; */ /* ->dev->dev_addr; */
++		#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++		if (netdev->br_port)
++		#else
++		if (rcu_dereference(adapter->pnetdev->rx_handler_data))
++		#endif
++		{
++			struct net_device *br_netdev;
++
++			br_netdev = rtw_get_bridge_ndev_by_name(CONFIG_BR_EXT_BRNAME);
++			if (br_netdev) {
++				memcpy(adapter->br_mac, br_netdev->dev_addr, ETH_ALEN);
++				dev_put(br_netdev);
++				RTW_INFO(FUNC_NDEV_FMT" bind bridge dev "NDEV_FMT"("MAC_FMT")\n"
++					, FUNC_NDEV_ARG(netdev), NDEV_ARG(br_netdev), MAC_ARG(br_netdev->dev_addr));
++			} else {
++				RTW_INFO(FUNC_NDEV_FMT" can't get bridge dev by name \"%s\"\n"
++					, FUNC_NDEV_ARG(netdev), CONFIG_BR_EXT_BRNAME);
++			}
++		}
++
++		adapter->ethBrExtInfo.addPPPoETag = 1;
++	}
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
++	rcu_read_unlock();
++#endif
++}
++#endif /* CONFIG_BR_EXT */
++
++#ifdef CONFIG_NEW_NETDEV_HDL
++int _netdev_open(struct net_device *pnetdev)
++{
++	uint status;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++
++	RTW_INFO(FUNC_NDEV_FMT" start\n", FUNC_NDEV_ARG(pnetdev));
++
++	if (!rtw_is_hw_init_completed(padapter)) { // ips 
++		rtw_clr_surprise_removed(padapter);
++		rtw_clr_drv_stopped(padapter);
++		RTW_ENABLE_FUNC(padapter, DF_RX_BIT);
++		RTW_ENABLE_FUNC(padapter, DF_TX_BIT);
++		status = rtw_hal_init(padapter);
++		if (status == _FAIL)
++			goto netdev_open_error;
++		rtw_led_control(padapter, LED_CTL_NO_LINK);
++		#ifndef RTW_HALMAC
++		status = rtw_mi_start_drv_threads(padapter);
++		if (status == _FAIL) {
++			RTW_ERR(FUNC_NDEV_FMT "Initialize driver thread failed!\n", FUNC_NDEV_ARG(pnetdev));
++			goto netdev_open_error;
++		}
++
++		rtw_intf_start(GET_PRIMARY_ADAPTER(padapter));
++		#endif /* !RTW_HALMAC */
++
++		{
++	#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++			_adapter *prim_adpt = GET_PRIMARY_ADAPTER(padapter);
++		
++			if (prim_adpt && (_TRUE == prim_adpt->EEPROMBluetoothCoexist)) {
++				rtw_btcoex_init_socket(prim_adpt);
++				prim_adpt->coex_info.BtMgnt.ExtConfig.HCIExtensionVer = 0x04;
++				rtw_btcoex_SetHciVersion(prim_adpt, 0x04);
++			}
++	#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++
++			_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
++
++	#ifndef CONFIG_IPS_CHECK_IN_WD
++			rtw_set_pwr_state_check_timer(pwrctrlpriv);
++	#endif /*CONFIG_IPS_CHECK_IN_WD*/
++		}
++
++	}
++
++	/*if (padapter->bup == _FALSE) */
++	{
++		rtw_hal_iface_init(padapter);
++
++		#ifdef CONFIG_RTW_NAPI
++		if(padapter->napi_state == NAPI_DISABLE) {
++			napi_enable(&padapter->napi);
++			padapter->napi_state = NAPI_ENABLE;
++		}
++		#endif
++
++		#ifdef CONFIG_IOCTL_CFG80211
++		rtw_cfg80211_init_wiphy(padapter);
++		rtw_cfg80211_init_wdev_data(padapter);
++		#endif
++		/* rtw_netif_carrier_on(pnetdev); */ /* call this func when rtw_joinbss_event_callback return success */
++		rtw_netif_wake_queue(pnetdev);
++
++		#ifdef CONFIG_BR_EXT
++		if (is_primary_adapter(padapter))
++			netdev_br_init(pnetdev);
++		#endif /* CONFIG_BR_EXT */
++
++
++		padapter->bup = _TRUE;
++		padapter->net_closed = _FALSE;
++		padapter->netif_up = _TRUE;
++		pwrctrlpriv->bips_processing = _FALSE;
++	}
++
++	RTW_INFO(FUNC_NDEV_FMT" Success (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
++	return 0;
++
++netdev_open_error:
++	padapter->bup = _FALSE;
++
++	#ifdef CONFIG_RTW_NAPI
++	if(padapter->napi_state == NAPI_ENABLE) {
++		napi_disable(&padapter->napi);
++		padapter->napi_state = NAPI_DISABLE;
++	}
++	#endif
++
++	rtw_netif_carrier_off(pnetdev);
++	rtw_netif_stop_queue(pnetdev);
++
++	RTW_ERR(FUNC_NDEV_FMT" Failed!! (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
++
++	return -1;
++
++}
++
++#else
++int _netdev_open(struct net_device *pnetdev)
++{
++	uint status;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++
++
++	RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
++
++	padapter->netif_up = _TRUE;
++
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++	rtw_sdio_set_power(1);
++#endif /* CONFIG_PLATFORM_INTEL_BYT */
++
++	if (padapter->bup == _FALSE) {
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++		rtw_macaddr_cfg(adapter_mac_addr(padapter),  get_hal_mac_addr(padapter));
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++		rtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter));
++#endif
++		rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));
++		_rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN);
++#endif /* CONFIG_PLATFORM_INTEL_BYT */
++
++		rtw_clr_surprise_removed(padapter);
++		rtw_clr_drv_stopped(padapter);
++
++		status = rtw_hal_init(padapter);
++		if (status == _FAIL) {
++			goto netdev_open_error;
++		}
++#if 0/*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/
++		rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */
++#endif
++
++		RTW_INFO("MAC Address = "MAC_FMT"\n", MAC_ARG(pnetdev->dev_addr));
++
++#ifndef RTW_HALMAC
++		status = rtw_start_drv_threads(padapter);
++		if (status == _FAIL) {
++			RTW_INFO("Initialize driver software resource Failed!\n");
++			goto netdev_open_error;
++		}
++#endif /* !RTW_HALMAC */
++
++#ifdef CONFIG_RTW_NAPI
++		if(padapter->napi_state == NAPI_DISABLE) {
++			napi_enable(&padapter->napi);
++			padapter->napi_state = NAPI_ENABLE;
++		}
++#endif
++
++#ifndef RTW_HALMAC
++		rtw_intf_start(padapter);
++#endif /* !RTW_HALMAC */
++
++#ifdef CONFIG_IOCTL_CFG80211
++		rtw_cfg80211_init_wiphy(padapter);
++		rtw_cfg80211_init_wdev_data(padapter);
++#endif
++
++		rtw_led_control(padapter, LED_CTL_NO_LINK);
++
++		padapter->bup = _TRUE;
++		pwrctrlpriv->bips_processing = _FALSE;
++
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++#ifdef CONFIG_BT_COEXIST
++		rtw_btcoex_IpsNotify(padapter, IPS_NONE);
++#endif /* CONFIG_BT_COEXIST */
++#endif /* CONFIG_PLATFORM_INTEL_BYT		 */
++	}
++	padapter->net_closed = _FALSE;
++
++	_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
++
++#ifndef CONFIG_IPS_CHECK_IN_WD
++	rtw_set_pwr_state_check_timer(pwrctrlpriv);
++#endif
++
++	/* rtw_netif_carrier_on(pnetdev); */ /* call this func when rtw_joinbss_event_callback return success */
++	rtw_netif_wake_queue(pnetdev);
++
++#ifdef CONFIG_BR_EXT
++	netdev_br_init(pnetdev);
++#endif /* CONFIG_BR_EXT */
++
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++	if (is_primary_adapter(padapter) && (_TRUE == pHalData->EEPROMBluetoothCoexist)) {
++		rtw_btcoex_init_socket(padapter);
++		padapter->coex_info.BtMgnt.ExtConfig.HCIExtensionVer = 0x04;
++		rtw_btcoex_SetHciVersion(padapter, 0x04);
++	} else
++		RTW_INFO("CONFIG_BT_COEXIST: VIRTUAL_ADAPTER\n");
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++
++#ifdef CONFIG_CONCURRENT_MODE
++	{
++		_adapter *sec_adapter = adapter_to_dvobj(padapter)->padapters[IFACE_ID1];
++
++		#ifndef CONFIG_RTW_DYNAMIC_NDEV
++		if (sec_adapter && (sec_adapter->bup == _FALSE))
++			_netdev_vir_if_open(sec_adapter->pnetdev);
++		#endif
++	}
++#endif
++
++#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
++	pwrctrlpriv->radio_on_start_time = rtw_get_current_time();
++	pwrctrlpriv->pwr_saving_start_time = rtw_get_current_time();
++	pwrctrlpriv->pwr_saving_time = 0;
++	pwrctrlpriv->on_time = 0;
++	pwrctrlpriv->tx_time = 0;
++	pwrctrlpriv->rx_time = 0;
++#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */
++
++	RTW_INFO("-871x_drv - drv_open, bup=%d\n", padapter->bup);
++
++	return 0;
++
++netdev_open_error:
++
++	padapter->bup = _FALSE;
++
++#ifdef CONFIG_RTW_NAPI
++	if(padapter->napi_state == NAPI_ENABLE) {
++		napi_disable(&padapter->napi);
++		padapter->napi_state = NAPI_DISABLE;
++	}
++#endif
++
++	rtw_netif_carrier_off(pnetdev);
++	rtw_netif_stop_queue(pnetdev);
++
++	RTW_INFO("-871x_drv - drv_open fail, bup=%d\n", padapter->bup);
++
++	return -1;
++
++}
++#endif
++int netdev_open(struct net_device *pnetdev)
++{
++	int ret = _FALSE;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++
++	if (pwrctrlpriv->bInSuspend == _TRUE) {
++		RTW_INFO(" [WARN] "ADPT_FMT" %s  failed, bInSuspend=%d\n", ADPT_ARG(padapter), __func__, pwrctrlpriv->bInSuspend);
++		return 0;
++	}
++
++	_enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
++#ifdef CONFIG_NEW_NETDEV_HDL
++	ret = _netdev_open(pnetdev);
++#else
++	if (is_primary_adapter(padapter))
++		ret = _netdev_open(pnetdev);
++#ifdef CONFIG_CONCURRENT_MODE
++	else
++		ret = _netdev_vir_if_open(pnetdev);
++#endif
++#endif
++	_exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
++
++
++#ifdef CONFIG_AUTO_AP_MODE
++	if (padapter->iface_id == IFACE_ID2)
++		rtw_start_auto_ap(padapter);
++#endif
++
++	return ret;
++}
++
++#ifdef CONFIG_IPS
++int  ips_netdrv_open(_adapter *padapter)
++{
++	int status = _SUCCESS;
++	/* struct pwrctrl_priv	*pwrpriv = adapter_to_pwrctl(padapter); */
++
++	padapter->net_closed = _FALSE;
++
++	RTW_INFO("===> %s.........\n", __FUNCTION__);
++
++
++	rtw_clr_drv_stopped(padapter);
++	/* padapter->bup = _TRUE; */
++#ifdef CONFIG_NEW_NETDEV_HDL
++	if (!rtw_is_hw_init_completed(padapter)) {
++		status = rtw_hal_init(padapter);
++		if (status == _FAIL) {
++			goto netdev_open_error;
++		}
++		rtw_mi_hal_iface_init(padapter);
++	}
++#else
++	status = rtw_hal_init(padapter);
++	if (status == _FAIL) {
++		goto netdev_open_error;
++	}
++#endif
++#if 0
++	rtw_mi_set_mac_addr(padapter);
++#endif
++#ifndef RTW_HALMAC
++	rtw_intf_start(padapter);
++#endif /* !RTW_HALMAC */
++
++#ifndef CONFIG_IPS_CHECK_IN_WD
++	rtw_set_pwr_state_check_timer(adapter_to_pwrctl(padapter));
++#endif
++	_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
++
++	return _SUCCESS;
++
++netdev_open_error:
++	/* padapter->bup = _FALSE; */
++	RTW_INFO("-ips_netdrv_open - drv_open failure, bup=%d\n", padapter->bup);
++
++	return _FAIL;
++}
++
++int rtw_ips_pwr_up(_adapter *padapter)
++{
++	int result;
++#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS)
++#ifdef DBG_CONFIG_ERROR_DETECT
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */
++#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */
++	systime start_time = rtw_get_current_time();
++	RTW_INFO("===>  rtw_ips_pwr_up..............\n");
++
++#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS)
++#ifdef DBG_CONFIG_ERROR_DETECT
++	if (psrtpriv->silent_reset_inprogress == _TRUE)
++#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */
++#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */
++		rtw_reset_drv_sw(padapter);
++
++	result = ips_netdrv_open(padapter);
++
++	rtw_led_control(padapter, LED_CTL_NO_LINK);
++
++	RTW_INFO("<===  rtw_ips_pwr_up.............. in %dms\n", rtw_get_passing_time_ms(start_time));
++	return result;
++
++}
++
++void rtw_ips_pwr_down(_adapter *padapter)
++{
++	systime start_time = rtw_get_current_time();
++	RTW_INFO("===> rtw_ips_pwr_down...................\n");
++
++	padapter->net_closed = _TRUE;
++
++	rtw_ips_dev_unload(padapter);
++	RTW_INFO("<=== rtw_ips_pwr_down..................... in %dms\n", rtw_get_passing_time_ms(start_time));
++}
++#endif
++void rtw_ips_dev_unload(_adapter *padapter)
++{
++#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS)
++#ifdef DBG_CONFIG_ERROR_DETECT
++	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
++	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
++#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */
++#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */
++	RTW_INFO("====> %s...\n", __FUNCTION__);
++
++
++#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS)
++#ifdef DBG_CONFIG_ERROR_DETECT
++	if (psrtpriv->silent_reset_inprogress == _TRUE)
++#endif /* #ifdef DBG_CONFIG_ERROR_DETECT */
++#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */
++	{
++		rtw_hal_set_hwreg(padapter, HW_VAR_FIFO_CLEARN_UP, 0);
++		rtw_intf_stop(padapter);
++	}
++
++	if (!rtw_is_surprise_removed(padapter))
++		rtw_hal_deinit(padapter);
++
++}
++#ifdef CONFIG_NEW_NETDEV_HDL
++int _pm_netdev_open(_adapter *padapter)
++{
++	uint status;
++	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
++	struct net_device *pnetdev = padapter->pnetdev;
++
++	RTW_INFO(FUNC_NDEV_FMT" start\n", FUNC_NDEV_ARG(pnetdev));
++
++	if (!rtw_is_hw_init_completed(padapter)) { // ips 
++		rtw_clr_surprise_removed(padapter);
++		rtw_clr_drv_stopped(padapter);
++		status = rtw_hal_init(padapter);
++		if (status == _FAIL)
++			goto netdev_open_error;
++		rtw_led_control(padapter, LED_CTL_NO_LINK);
++		#ifndef RTW_HALMAC
++		status = rtw_mi_start_drv_threads(padapter);
++		if (status == _FAIL) {
++			RTW_ERR(FUNC_NDEV_FMT "Initialize driver thread failed!\n", FUNC_NDEV_ARG(pnetdev));
++			goto netdev_open_error;
++		}
++
++		rtw_intf_start(GET_PRIMARY_ADAPTER(padapter));
++		#endif /* !RTW_HALMAC */
++
++		{
++			_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
++
++	#ifndef CONFIG_IPS_CHECK_IN_WD
++			rtw_set_pwr_state_check_timer(pwrctrlpriv);
++	#endif /*CONFIG_IPS_CHECK_IN_WD*/
++		}
++
++	}
++
++	/*if (padapter->bup == _FALSE) */
++	{
++		rtw_hal_iface_init(padapter);
++
++		padapter->bup = _TRUE;
++		padapter->net_closed = _FALSE;
++		padapter->netif_up = _TRUE;
++		pwrctrlpriv->bips_processing = _FALSE;
++	}
++
++	RTW_INFO(FUNC_NDEV_FMT" Success (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
++	return 0;
++
++netdev_open_error:
++	padapter->bup = _FALSE;
++
++	rtw_netif_carrier_off(pnetdev);
++	rtw_netif_stop_queue(pnetdev);
++
++	RTW_ERR(FUNC_NDEV_FMT" Failed!! (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
++
++	return -1;
++
++}
++int _mi_pm_netdev_open(struct net_device *pnetdev)
++{
++	int i;
++	int status = 0;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++	_adapter *iface;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (iface->netif_up) {
++			status = _pm_netdev_open(iface);
++			if (status == -1) {
++				RTW_ERR("%s failled\n", __func__);
++				break;
++			}
++		}
++	}
++
++	return status;
++}
++#endif /*CONFIG_NEW_NETDEV_HDL*/
++int pm_netdev_open(struct net_device *pnetdev, u8 bnormal)
++{
++	int status = 0;
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++
++	if (_TRUE == bnormal) {
++		_enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
++		#ifdef CONFIG_NEW_NETDEV_HDL
++		status = _mi_pm_netdev_open(pnetdev);
++		#else
++		status = _netdev_open(pnetdev);
++		#endif
++		_exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
++	}
++#ifdef CONFIG_IPS
++	else
++		status = (_SUCCESS == ips_netdrv_open(padapter)) ? (0) : (-1);
++#endif
++
++	return status;
++}
++#ifdef CONFIG_CLIENT_PORT_CFG
++extern void rtw_hw_client_port_release(_adapter *adapter);
++#endif
++static int netdev_close(struct net_device *pnetdev)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++	RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
++#ifndef CONFIG_PLATFORM_INTEL_BYT
++	padapter->net_closed = _TRUE;
++	padapter->netif_up = _FALSE;
++	pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
++
++#ifdef CONFIG_CLIENT_PORT_CFG
++	if (MLME_IS_STA(padapter))
++		rtw_hw_client_port_release(padapter);
++#endif
++	/*	if (!rtw_is_hw_init_completed(padapter)) {
++			RTW_INFO("(1)871x_drv - drv_close, bup=%d, hw_init_completed=%s\n", padapter->bup, rtw_is_hw_init_completed(padapter)?"_TRUE":"_FALSE");
++
++			rtw_set_drv_stopped(padapter);
++
++			rtw_dev_unload(padapter);
++		}
++		else*/
++	if (pwrctl->rf_pwrstate == rf_on) {
++		RTW_INFO("(2)871x_drv - drv_close, bup=%d, hw_init_completed=%s\n", padapter->bup, rtw_is_hw_init_completed(padapter) ? "_TRUE" : "_FALSE");
++
++		/* s1. */
++		if (pnetdev)
++			rtw_netif_stop_queue(pnetdev);
++
++#ifndef CONFIG_RTW_ANDROID
++		/* s2. */
++		LeaveAllPowerSaveMode(padapter);
++		rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK);
++		/* s2-2.  indicate disconnect to os */
++		rtw_indicate_disconnect(padapter, 0, _FALSE);
++		/* s2-3. */
++		rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK);
++		/* s2-4. */
++		rtw_free_network_queue(padapter, _TRUE);
++#endif
++	}
++
++#ifdef CONFIG_BR_EXT
++	/* if (OPMODE & (WIFI_STATION_STATE | WIFI_ADHOC_STATE)) */
++	{
++		/* void nat25_db_cleanup(_adapter *priv); */
++		nat25_db_cleanup(padapter);
++	}
++#endif /* CONFIG_BR_EXT */
++
++#ifdef CONFIG_P2P
++	if (!rtw_p2p_chk_role(&padapter->wdinfo, P2P_ROLE_DISABLE))
++		rtw_p2p_enable(padapter, P2P_ROLE_DISABLE);
++#endif /* CONFIG_P2P */
++
++	rtw_scan_abort(padapter); /* stop scanning process before wifi is going to down */
++#ifdef CONFIG_IOCTL_CFG80211
++	rtw_cfg80211_wait_scan_req_empty(padapter, 200);
++	adapter_wdev_data(padapter)->bandroid_scan = _FALSE;
++	/* padapter->rtw_wdev->iftype = NL80211_IFTYPE_MONITOR; */ /* set this at the end */
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++#ifdef CONFIG_WAPI_SUPPORT
++	rtw_wapi_disable_tx(padapter);
++#endif
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++	if (is_primary_adapter(padapter) && (_TRUE == pHalData->EEPROMBluetoothCoexist))
++		rtw_btcoex_close_socket(padapter);
++	else
++		RTW_INFO("CONFIG_BT_COEXIST: VIRTUAL_ADAPTER\n");
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++#else /* !CONFIG_PLATFORM_INTEL_BYT */
++
++	if (pwrctl->bInSuspend == _TRUE) {
++		RTW_INFO("+871x_drv - drv_close, bInSuspend=%d\n", pwrctl->bInSuspend);
++		return 0;
++	}
++
++	rtw_scan_abort(padapter); /* stop scanning process before wifi is going to down */
++#ifdef CONFIG_IOCTL_CFG80211
++	rtw_cfg80211_wait_scan_req_empty(padapter, 200);
++#endif
++
++	RTW_INFO("netdev_close, bips_processing=%d\n", pwrctl->bips_processing);
++	while (pwrctl->bips_processing == _TRUE) /* waiting for ips_processing done before call rtw_dev_unload() */
++		rtw_msleep_os(1);
++
++	rtw_dev_unload(padapter);
++	rtw_sdio_set_power(0);
++
++#endif /* !CONFIG_PLATFORM_INTEL_BYT */
++
++	RTW_INFO("-871x_drv - drv_close, bup=%d\n", padapter->bup);
++
++	return 0;
++
++}
++
++int pm_netdev_close(struct net_device *pnetdev, u8 bnormal)
++{
++	int status = 0;
++
++	status = netdev_close(pnetdev);
++
++	return status;
++}
++
++void rtw_ndev_destructor(struct net_device *ndev)
++{
++	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (ndev->ieee80211_ptr)
++		rtw_mfree((u8 *)ndev->ieee80211_ptr, sizeof(struct wireless_dev));
++#endif
++	free_netdev(ndev);
++}
++
++#ifdef CONFIG_ARP_KEEP_ALIVE
++struct route_info {
++	struct in_addr dst_addr;
++	struct in_addr src_addr;
++	struct in_addr gateway;
++	unsigned int dev_index;
++};
++
++static void parse_routes(struct nlmsghdr *nl_hdr, struct route_info *rt_info)
++{
++	struct rtmsg *rt_msg;
++	struct rtattr *rt_attr;
++	int rt_len;
++
++	rt_msg = (struct rtmsg *) NLMSG_DATA(nl_hdr);
++	if ((rt_msg->rtm_family != AF_INET) || (rt_msg->rtm_table != RT_TABLE_MAIN))
++		return;
++
++	rt_attr = (struct rtattr *) RTM_RTA(rt_msg);
++	rt_len = RTM_PAYLOAD(nl_hdr);
++
++	for (; RTA_OK(rt_attr, rt_len); rt_attr = RTA_NEXT(rt_attr, rt_len)) {
++		switch (rt_attr->rta_type) {
++		case RTA_OIF:
++			rt_info->dev_index = *(int *) RTA_DATA(rt_attr);
++			break;
++		case RTA_GATEWAY:
++			rt_info->gateway.s_addr = *(u_int *) RTA_DATA(rt_attr);
++			break;
++		case RTA_PREFSRC:
++			rt_info->src_addr.s_addr = *(u_int *) RTA_DATA(rt_attr);
++			break;
++		case RTA_DST:
++			rt_info->dst_addr.s_addr = *(u_int *) RTA_DATA(rt_attr);
++			break;
++		}
++	}
++}
++
++static int route_dump(u32 *gw_addr , int *gw_index)
++{
++	int err = 0;
++	struct socket *sock;
++	struct {
++		struct nlmsghdr nlh;
++		struct rtgenmsg g;
++	} req;
++	struct msghdr msg;
++	struct iovec iov;
++	struct sockaddr_nl nladdr;
++	mm_segment_t oldfs;
++	char *pg;
++	int size = 0;
++
++	err = sock_create(AF_NETLINK, SOCK_DGRAM, NETLINK_ROUTE, &sock);
++	if (err) {
++		printk(": Could not create a datagram socket, error = %d\n", -ENXIO);
++		return err;
++	}
++
++	memset(&nladdr, 0, sizeof(nladdr));
++	nladdr.nl_family = AF_NETLINK;
++
++	req.nlh.nlmsg_len = sizeof(req);
++	req.nlh.nlmsg_type = RTM_GETROUTE;
++	req.nlh.nlmsg_flags = NLM_F_ROOT | NLM_F_MATCH | NLM_F_REQUEST;
++	req.nlh.nlmsg_pid = 0;
++	req.g.rtgen_family = AF_INET;
++
++	iov.iov_base = &req;
++	iov.iov_len = sizeof(req);
++
++	msg.msg_name = &nladdr;
++	msg.msg_namelen = sizeof(nladdr);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++	/* referece:sock_xmit in kernel code
++	 * WRITE for sock_sendmsg, READ for sock_recvmsg
++	 * third parameter for msg_iovlen
++	 * last parameter for iov_len
++	 */
++	iov_iter_init(&msg.msg_iter, WRITE, &iov, 1, sizeof(req));
++#else
++	msg.msg_iov = &iov;
++	msg.msg_iovlen = 1;
++#endif
++	msg.msg_control = NULL;
++	msg.msg_controllen = 0;
++	msg.msg_flags = MSG_DONTWAIT;
++
++	oldfs = get_fs();
++	set_fs(KERNEL_DS);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
++	err = sock_sendmsg(sock, &msg);
++#else
++	err = sock_sendmsg(sock, &msg, sizeof(req));
++#endif
++	set_fs(oldfs);
++
++	if (err < 0)
++		goto out_sock;
++
++	pg = (char *) __get_free_page(GFP_KERNEL);
++	if (pg == NULL) {
++		err = -ENOMEM;
++		goto out_sock;
++	}
++
++#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
++restart:
++#endif
++
++	for (;;) {
++		struct nlmsghdr *h;
++
++		iov.iov_base = pg;
++		iov.iov_len = PAGE_SIZE;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++		iov_iter_init(&msg.msg_iter, READ, &iov, 1, PAGE_SIZE);
++#endif
++
++		oldfs = get_fs();
++		set_fs(KERNEL_DS);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))
++		err = sock_recvmsg(sock, &msg, MSG_DONTWAIT);
++#else
++		err = sock_recvmsg(sock, &msg, PAGE_SIZE, MSG_DONTWAIT);
++#endif
++		set_fs(oldfs);
++
++		if (err < 0)
++			goto out_sock_pg;
++
++		if (msg.msg_flags & MSG_TRUNC) {
++			err = -ENOBUFS;
++			goto out_sock_pg;
++		}
++
++		h = (struct nlmsghdr *) pg;
++
++		while (NLMSG_OK(h, err)) {
++			struct route_info rt_info;
++			if (h->nlmsg_type == NLMSG_DONE) {
++				err = 0;
++				goto done;
++			}
++
++			if (h->nlmsg_type == NLMSG_ERROR) {
++				struct nlmsgerr *errm = (struct nlmsgerr *) NLMSG_DATA(h);
++				err = errm->error;
++				printk("NLMSG error: %d\n", errm->error);
++				goto done;
++			}
++
++			if (h->nlmsg_type == RTM_GETROUTE)
++				printk("RTM_GETROUTE: NLMSG: %d\n", h->nlmsg_type);
++			if (h->nlmsg_type != RTM_NEWROUTE) {
++				printk("NLMSG: %d\n", h->nlmsg_type);
++				err = -EINVAL;
++				goto done;
++			}
++
++			memset(&rt_info, 0, sizeof(struct route_info));
++			parse_routes(h, &rt_info);
++			if (!rt_info.dst_addr.s_addr && rt_info.gateway.s_addr && rt_info.dev_index) {
++				*gw_addr = rt_info.gateway.s_addr;
++				*gw_index = rt_info.dev_index;
++
++			}
++			h = NLMSG_NEXT(h, err);
++		}
++
++		if (err) {
++			printk("!!!Remnant of size %d %d %d\n", err, h->nlmsg_len, h->nlmsg_type);
++			err = -EINVAL;
++			break;
++		}
++	}
++
++done:
++#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
++	if (!err && req.g.rtgen_family == AF_INET) {
++		req.g.rtgen_family = AF_INET6;
++
++		iov.iov_base = &req;
++		iov.iov_len = sizeof(req);
++
++		msg.msg_name = &nladdr;
++		msg.msg_namelen = sizeof(nladdr);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++		iov_iter_init(&msg.msg_iter, WRITE, &iov, 1, sizeof(req));
++#else
++		msg.msg_iov = &iov;
++		msg.msg_iovlen = 1;
++#endif
++		msg.msg_control = NULL;
++		msg.msg_controllen = 0;
++		msg.msg_flags = MSG_DONTWAIT;
++
++		oldfs = get_fs();
++		set_fs(KERNEL_DS);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
++		err = sock_sendmsg(sock, &msg);
++#else
++		err = sock_sendmsg(sock, &msg, sizeof(req));
++#endif
++		set_fs(oldfs);
++
++		if (err > 0)
++			goto restart;
++	}
++#endif
++
++out_sock_pg:
++	free_page((unsigned long) pg);
++
++out_sock:
++	sock_release(sock);
++	return err;
++}
++
++static int arp_query(unsigned char *haddr, u32 paddr,
++		     struct net_device *dev)
++{
++	struct neighbour *neighbor_entry;
++	int	ret = 0;
++
++	neighbor_entry = neigh_lookup(&arp_tbl, &paddr, dev);
++
++	if (neighbor_entry != NULL) {
++		neighbor_entry->used = jiffies;
++		if (neighbor_entry->nud_state & NUD_VALID) {
++			_rtw_memcpy(haddr, neighbor_entry->ha, dev->addr_len);
++			ret = 1;
++		}
++		neigh_release(neighbor_entry);
++	}
++	return ret;
++}
++
++static int get_defaultgw(u32 *ip_addr , char mac[])
++{
++	int gw_index = 0; /* oif device index */
++	struct net_device *gw_dev = NULL; /* oif device */
++
++	route_dump(ip_addr, &gw_index);
++
++	if (!(*ip_addr) || !gw_index) {
++		/* RTW_INFO("No default GW\n"); */
++		return -1;
++	}
++
++	gw_dev = dev_get_by_index(&init_net, gw_index);
++
++	if (gw_dev == NULL) {
++		/* RTW_INFO("get Oif Device Fail\n"); */
++		return -1;
++	}
++
++	if (!arp_query(mac, *ip_addr, gw_dev)) {
++		/* RTW_INFO( "arp query failed\n"); */
++		dev_put(gw_dev);
++		return -1;
++
++	}
++	dev_put(gw_dev);
++
++	return 0;
++}
++
++int	rtw_gw_addr_query(_adapter *padapter)
++{
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
++	u32 gw_addr = 0; /* default gw address */
++	unsigned char gw_mac[32] = {0}; /* default gw mac */
++	int i;
++	int res;
++
++	res = get_defaultgw(&gw_addr, gw_mac);
++	if (!res) {
++		pmlmepriv->gw_ip[0] = gw_addr & 0xff;
++		pmlmepriv->gw_ip[1] = (gw_addr & 0xff00) >> 8;
++		pmlmepriv->gw_ip[2] = (gw_addr & 0xff0000) >> 16;
++		pmlmepriv->gw_ip[3] = (gw_addr & 0xff000000) >> 24;
++		_rtw_memcpy(pmlmepriv->gw_mac_addr, gw_mac, ETH_ALEN);
++		RTW_INFO("%s Gateway Mac:\t" MAC_FMT "\n", __FUNCTION__, MAC_ARG(pmlmepriv->gw_mac_addr));
++		RTW_INFO("%s Gateway IP:\t" IP_FMT "\n", __FUNCTION__, IP_ARG(pmlmepriv->gw_ip));
++	} else
++		RTW_INFO("Get Gateway IP/MAC fail!\n");
++
++	return res;
++}
++#endif
++
++void rtw_dev_unload(PADAPTER padapter)
++{
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
++	struct dvobj_priv *pobjpriv = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &pobjpriv->drv_dbg;
++	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
++
++	if (padapter->bup == _TRUE) {
++		RTW_INFO("==> "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++
++#ifdef CONFIG_WOWLAN
++#ifdef CONFIG_GPIO_WAKEUP
++		/*default wake up pin change to BT*/
++		RTW_INFO("%s:default wake up pin change to BT\n", __FUNCTION__);
++		rtw_hal_switch_gpio_wl_ctrl(padapter, pwrctl->wowlan_gpio_index, _FALSE);
++#endif /* CONFIG_GPIO_WAKEUP */
++#endif /* CONFIG_WOWLAN */
++
++		rtw_set_drv_stopped(padapter);
++#ifdef CONFIG_XMIT_ACK
++		if (padapter->xmitpriv.ack_tx)
++			rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP);
++#endif
++
++		rtw_intf_stop(padapter);
++		
++		rtw_stop_drv_threads(padapter);
++
++		if (ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _TRUE) {
++			RTW_ERR("cmd_thread not stop !!\n");
++			rtw_warn_on(1);
++		}
++		
++		/* check the status of IPS */
++		if (rtw_hal_check_ips_status(padapter) == _TRUE || pwrctl->rf_pwrstate == rf_off) { /* check HW status and SW state */
++			RTW_PRINT("%s: driver in IPS-FWLPS\n", __func__);
++			pdbgpriv->dbg_dev_unload_inIPS_cnt++;
++		} else
++			RTW_PRINT("%s: driver not in IPS\n", __func__);
++
++		if (!rtw_is_surprise_removed(padapter)) {
++#ifdef CONFIG_BT_COEXIST
++			rtw_btcoex_IpsNotify(padapter, pwrctl->ips_mode_req);
++#endif
++#ifdef CONFIG_WOWLAN
++			if (pwrctl->bSupportRemoteWakeup == _TRUE &&
++			    pwrctl->wowlan_mode == _TRUE)
++				RTW_PRINT("%s bSupportRemoteWakeup==_TRUE  do not run rtw_hal_deinit()\n", __FUNCTION__);
++			else
++#endif
++			{
++				/* amy modify 20120221 for power seq is different between driver open and ips */
++				rtw_hal_deinit(padapter);
++			}
++			rtw_set_surprise_removed(padapter);
++		}
++
++		padapter->bup = _FALSE;
++
++		RTW_INFO("<== "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
++	} else {
++		RTW_INFO("%s: bup==_FALSE\n", __FUNCTION__);
++	}
++	rtw_cancel_all_timer(padapter);
++}
++
++int rtw_suspend_free_assoc_resource(_adapter *padapter)
++{
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++#ifdef CONFIG_P2P
++	struct wifidirect_info	*pwdinfo = &padapter->wdinfo;
++#endif /* CONFIG_P2P */
++
++	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
++
++	if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) {
++		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
++			&& check_fwstate(pmlmepriv, WIFI_ASOC_STATE)
++			#ifdef CONFIG_P2P
++			&& (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
++				#if defined(CONFIG_IOCTL_CFG80211) && RTW_P2P_GROUP_INTERFACE
++				|| rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)
++				#endif
++				)
++			#endif /* CONFIG_P2P */
++		) {
++			RTW_INFO("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n", __FUNCTION__,
++				pmlmepriv->cur_network.network.Ssid.Ssid,
++				MAC_ARG(pmlmepriv->cur_network.network.MacAddress),
++				pmlmepriv->cur_network.network.Ssid.SsidLength,
++				pmlmepriv->assoc_ssid.SsidLength);
++			rtw_set_to_roam(padapter, 1);
++		}
++	}
++
++	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
++		rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY);
++		/* s2-2.  indicate disconnect to os */
++		rtw_indicate_disconnect(padapter, 0, _FALSE);
++	}
++#ifdef CONFIG_AP_MODE
++	else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter))
++		rtw_sta_flush(padapter, _TRUE);
++#endif
++
++	/* s2-3. */
++	rtw_free_assoc_resources(padapter, _TRUE);
++
++	/* s2-4. */
++	rtw_free_network_queue(padapter, _TRUE);
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)) {
++		RTW_PRINT("%s: fw_under_survey\n", __func__);
++		rtw_indicate_scan_done(padapter, 1);
++		clr_fwstate(pmlmepriv, WIFI_UNDER_SURVEY);
++	}
++
++	if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) {
++		RTW_PRINT("%s: fw_under_linking\n", __FUNCTION__);
++		rtw_indicate_disconnect(padapter, 0, _FALSE);
++	}
++
++	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
++	return _SUCCESS;
++}
++
++#ifdef CONFIG_WOWLAN
++int rtw_suspend_wow(_adapter *padapter)
++{
++	u8 ch, bw, offset;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct wowlan_ioctl_param poidparam;
++	int ret = _SUCCESS;
++	u8 en = _TRUE, i;
++	struct registry_priv *registry_par = &padapter->registrypriv;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++	_adapter *iface = NULL;
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++
++	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
++
++
++	RTW_INFO("wowlan_mode: %d\n", pwrpriv->wowlan_mode);
++	RTW_INFO("wowlan_pno_enable: %d\n", pwrpriv->wowlan_pno_enable);
++#ifdef CONFIG_P2P_WOWLAN
++	RTW_INFO("wowlan_p2p_enable: %d\n", pwrpriv->wowlan_p2p_enable);
++#endif
++
++	if (pwrpriv->wowlan_mode == _TRUE) {
++		rtw_mi_netif_stop_queue(padapter);
++		#ifdef CONFIG_CONCURRENT_MODE
++		rtw_mi_buddy_netif_carrier_off(padapter);
++		#endif
++
++		/* 0. Power off LED */
++		rtw_led_control(padapter, LED_CTL_POWER_OFF);
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++		/* 2.only for SDIO disable interrupt */
++		rtw_intf_stop(padapter);
++
++		/* 2.1 clean interrupt */
++		rtw_hal_clear_interrupt(padapter);
++#endif /* CONFIG_SDIO_HCI */
++		
++		/* enable ac lifetime during scan to avoid txfifo not empty. */
++		dvobj->lifetime_en = rtw_read8(padapter, 0x426);
++		dvobj->pkt_lifetime = rtw_read32(padapter, 0x4c0);
++		rtw_write8(padapter, 0x426, rtw_read8(padapter, 0x426) | 0x0f);
++		if(hal_spec->tx_aclt_unit_factor == 1) {
++			rtw_write16(padapter, 0x4c0, 0x1000);	// unit: 32us. 131ms 
++			rtw_write16(padapter, 0x4c0 + 2 , 0x1000);	// unit: 32us. 131ms
++		} else {
++			rtw_write16(padapter, 0x4c0, 0x0200);	// unit: 256us. 131ms 
++			rtw_write16(padapter, 0x4c0 + 2 , 0x0200);	// unit: 256us. 131ms
++		}
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			iface = dvobj->padapters[i];
++			if ((iface) && rtw_is_adapter_up(iface)) {
++				rtw_write_port_cancel(iface);
++				RTW_INFO(ADPT_FMT " write port cancel\n", ADPT_ARG(iface));
++			}
++		}
++		RTW_INFO("lifetime_en=%x, pkt_lifetime=%x\n", rtw_read8(padapter, 0x426), rtw_read32(padapter, 0x4c0));
++		rtw_msleep_os(200);
++		
++		/* 1. stop thread */
++		rtw_set_drv_stopped(padapter);	/*for stop thread*/
++		rtw_mi_stop_drv_threads(padapter);
++
++		rtw_clr_drv_stopped(padapter);	/*for 32k command*/
++
++		/* #ifdef CONFIG_LPS */
++		/* rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "WOWLAN"); */
++		/* #endif */
++
++		#ifdef CONFIG_SDIO_HCI
++		/* 2.2 free irq */
++		#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
++		sdio_free_irq(adapter_to_dvobj(padapter));
++		#endif
++		#endif/*CONFIG_SDIO_HCI*/
++
++#ifdef CONFIG_RUNTIME_PORT_SWITCH
++		if (rtw_port_switch_chk(padapter)) {
++			RTW_INFO(" ### PORT SWITCH ###\n");
++			rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);
++		}
++#endif
++		if(registry_par->suspend_type == FW_IPS_WRC)
++			rtw_hal_set_hwreg(padapter, HW_VAR_VENDOR_WOW_MODE, &en);
++		rtw_wow_lps_level_decide(padapter, _TRUE);
++		poidparam.subcode = WOWLAN_ENABLE;
++		rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam);
++		if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) {
++			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
++			    && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
++				RTW_INFO("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n", __FUNCTION__,
++					pmlmepriv->cur_network.network.Ssid.Ssid,
++					MAC_ARG(pmlmepriv->cur_network.network.MacAddress),
++					pmlmepriv->cur_network.network.Ssid.SsidLength,
++					 pmlmepriv->assoc_ssid.SsidLength);
++
++				rtw_set_to_roam(padapter, 0);
++			}
++		}
++
++		RTW_PRINT("%s: wowmode suspending\n", __func__);
++
++		if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE) {
++			RTW_PRINT("%s: fw_under_survey\n", __func__);
++			rtw_indicate_scan_done(padapter, 1);
++			clr_fwstate(pmlmepriv, WIFI_UNDER_SURVEY);
++		}
++
++#if 1
++		if (rtw_mi_check_status(padapter, MI_LINKED)) {
++			ch =  rtw_mi_get_union_chan(padapter);
++			bw = rtw_mi_get_union_bw(padapter);
++			offset = rtw_mi_get_union_offset(padapter);
++			RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n",
++				 FUNC_ADPT_ARG(padapter), ch, bw, offset);
++			set_channel_bwmode(padapter, ch, offset, bw);
++		}
++#else
++		if (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) {
++			RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n",
++				 FUNC_ADPT_ARG(padapter), ch, bw, offset);
++			set_channel_bwmode(padapter, ch, offset, bw);
++			rtw_mi_update_union_chan_inf(padapter, ch, offset, bw);
++		}
++#endif
++#ifdef CONFIG_CONCURRENT_MODE
++		rtw_mi_buddy_suspend_free_assoc_resource(padapter);
++#endif
++
++#ifdef CONFIG_BT_COEXIST
++		rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT);
++#endif
++
++		if (pwrpriv->wowlan_pno_enable) {
++			RTW_PRINT("%s: pno: %d\n", __func__,
++				  pwrpriv->wowlan_pno_enable);
++#ifdef CONFIG_FWLPS_IN_IPS
++			rtw_set_fw_in_ips_mode(padapter, _TRUE);
++#endif
++		}
++#ifdef CONFIG_LPS
++		else {
++			if(pwrpriv->wowlan_power_mgmt != PS_MODE_ACTIVE) {
++				rtw_set_ps_mode(padapter, pwrpriv->wowlan_power_mgmt, 0, 0, "WOWLAN");
++			}
++		}
++#endif /* #ifdef CONFIG_LPS */
++
++	} else
++		RTW_PRINT("%s: ### ERROR ### wowlan_mode=%d\n", __FUNCTION__, pwrpriv->wowlan_mode);
++	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
++	return ret;
++}
++#endif /* #ifdef CONFIG_WOWLAN */
++
++#ifdef CONFIG_AP_WOWLAN
++int rtw_suspend_ap_wow(_adapter *padapter)
++{
++	u8 ch, bw, offset;
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct wowlan_ioctl_param poidparam;
++	int ret = _SUCCESS;
++
++	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
++
++	pwrpriv->wowlan_ap_mode = _TRUE;
++
++	RTW_INFO("wowlan_ap_mode: %d\n", pwrpriv->wowlan_ap_mode);
++
++	rtw_mi_netif_stop_queue(padapter);
++
++	/* 0. Power off LED */
++	rtw_led_control(padapter, LED_CTL_POWER_OFF);
++#ifdef CONFIG_SDIO_HCI
++	/* 2.only for SDIO disable interrupt*/
++	rtw_intf_stop(padapter);
++
++	/* 2.1 clean interrupt */
++	rtw_hal_clear_interrupt(padapter);
++#endif /* CONFIG_SDIO_HCI */
++
++	/* 1. stop thread */
++	rtw_set_drv_stopped(padapter);	/*for stop thread*/
++	rtw_mi_stop_drv_threads(padapter);
++	rtw_clr_drv_stopped(padapter);	/*for 32k command*/
++
++	#ifdef CONFIG_SDIO_HCI
++	/* 2.2 free irq */
++	#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
++	sdio_free_irq(adapter_to_dvobj(padapter));
++	#endif
++	#endif/*CONFIG_SDIO_HCI*/
++
++#ifdef CONFIG_RUNTIME_PORT_SWITCH
++	if (rtw_port_switch_chk(padapter)) {
++		RTW_INFO(" ### PORT SWITCH ###\n");
++		rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);
++	}
++#endif
++
++	rtw_wow_lps_level_decide(padapter, _TRUE);
++	poidparam.subcode = WOWLAN_AP_ENABLE;
++	rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam);
++
++	RTW_PRINT("%s: wowmode suspending\n", __func__);
++#if 1
++	if (rtw_mi_check_status(padapter, MI_LINKED)) {
++		ch =  rtw_mi_get_union_chan(padapter);
++		bw = rtw_mi_get_union_bw(padapter);
++		offset = rtw_mi_get_union_offset(padapter);
++		RTW_INFO("back to linked/linking union - ch:%u, bw:%u, offset:%u\n", ch, bw, offset);
++		set_channel_bwmode(padapter, ch, offset, bw);
++	}
++#else
++	if (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) {
++		RTW_INFO("back to linked/linking union - ch:%u, bw:%u, offset:%u\n", ch, bw, offset);
++		set_channel_bwmode(padapter, ch, offset, bw);
++		rtw_mi_update_union_chan_inf(padapter, ch, offset, bw);
++	}
++#endif
++
++	/*FOR ONE AP - TODO :Multi-AP*/
++	{
++		int i;
++		_adapter *iface;
++		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			iface = dvobj->padapters[i];
++			if ((iface) && rtw_is_adapter_up(iface)) {
++				if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE) == _FALSE)
++					rtw_suspend_free_assoc_resource(iface);
++			}
++		}
++
++	}
++
++#ifdef CONFIG_BT_COEXIST
++	rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT);
++#endif
++
++#ifdef CONFIG_LPS
++	if(pwrpriv->wowlan_power_mgmt != PS_MODE_ACTIVE) {
++		rtw_set_ps_mode(padapter, pwrpriv->wowlan_power_mgmt, 0, 0, "AP-WOWLAN");
++	}
++#endif
++
++	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
++	return ret;
++}
++#endif /* #ifdef CONFIG_AP_WOWLAN */
++
++
++int rtw_suspend_normal(_adapter *padapter)
++{
++	int ret = _SUCCESS;
++
++	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
++
++#ifdef CONFIG_BT_COEXIST
++	rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND);
++#endif
++	rtw_mi_netif_caroff_qstop(padapter);
++
++	rtw_mi_suspend_free_assoc_resource(padapter);
++
++	rtw_led_control(padapter, LED_CTL_POWER_OFF);
++
++	if ((rtw_hal_check_ips_status(padapter) == _TRUE)
++	    || (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off))
++		RTW_PRINT("%s: ### ERROR #### driver in IPS ####ERROR###!!!\n", __FUNCTION__);
++
++
++#ifdef CONFIG_CONCURRENT_MODE
++	rtw_set_drv_stopped(padapter);	/*for stop thread*/
++	rtw_stop_cmd_thread(padapter);
++	rtw_drv_stop_vir_ifaces(adapter_to_dvobj(padapter));
++#endif
++	rtw_dev_unload(padapter);
++
++	#ifdef CONFIG_SDIO_HCI
++	sdio_deinit(adapter_to_dvobj(padapter));
++
++	#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
++	sdio_free_irq(adapter_to_dvobj(padapter));
++	#endif
++	#endif /*CONFIG_SDIO_HCI*/
++
++	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
++	return ret;
++}
++
++int rtw_suspend_common(_adapter *padapter)
++{
++	struct dvobj_priv *dvobj = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
++	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
++#ifdef CONFIG_WOWLAN
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct registry_priv *registry_par = &padapter->registrypriv;
++#endif
++
++	int ret = 0;
++	systime start_time = rtw_get_current_time();
++
++	RTW_PRINT(" suspend start\n");
++	RTW_INFO("==> %s (%s:%d)\n", __FUNCTION__, current->comm, current->pid);
++
++	pdbgpriv->dbg_suspend_cnt++;
++
++	pwrpriv->bInSuspend = _TRUE;
++
++	while (pwrpriv->bips_processing == _TRUE)
++		rtw_msleep_os(1);
++
++#ifdef CONFIG_IOL_READ_EFUSE_MAP
++	if (!padapter->bup) {
++		u8 bMacPwrCtrlOn = _FALSE;
++		rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++		if (bMacPwrCtrlOn)
++			rtw_hal_power_off(padapter);
++	}
++#endif
++
++	if ((!padapter->bup) || RTW_CANNOT_RUN(padapter)) {
++		RTW_INFO("%s bup=%d bDriverStopped=%s bSurpriseRemoved = %s\n", __func__
++			 , padapter->bup
++			 , rtw_is_drv_stopped(padapter) ? "True" : "False"
++			, rtw_is_surprise_removed(padapter) ? "True" : "False");
++		pdbgpriv->dbg_suspend_error_cnt++;
++		goto exit;
++	}
++	rtw_mi_scan_abort(padapter, _TRUE);
++	rtw_ps_deny(padapter, PS_DENY_SUSPEND);
++
++	rtw_mi_cancel_all_timer(padapter);
++	LeaveAllPowerSaveModeDirect(padapter);
++
++	rtw_ps_deny_cancel(padapter, PS_DENY_SUSPEND);
++
++	if (rtw_mi_check_status(padapter, MI_AP_MODE) == _FALSE) {
++#ifdef CONFIG_WOWLAN
++		if (WOWLAN_IS_STA_MIX_MODE(padapter))
++			pwrpriv->wowlan_mode = _TRUE;
++		else if ( registry_par->wowlan_enable && check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
++			pwrpriv->wowlan_mode = _TRUE;
++		else if (pwrpriv->wowlan_pno_enable == _TRUE)
++			pwrpriv->wowlan_mode |= pwrpriv->wowlan_pno_enable;
++
++#ifdef CONFIG_P2P_WOWLAN
++		if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE) || P2P_ROLE_DISABLE != padapter->wdinfo.role)
++			pwrpriv->wowlan_p2p_mode = _TRUE;
++		if (_TRUE == pwrpriv->wowlan_p2p_mode)
++			pwrpriv->wowlan_mode |= pwrpriv->wowlan_p2p_mode;
++#endif /* CONFIG_P2P_WOWLAN */
++
++		if (pwrpriv->wowlan_mode == _TRUE)
++			rtw_suspend_wow(padapter);
++		else
++#endif /* CONFIG_WOWLAN */
++			rtw_suspend_normal(padapter);
++	} else if (rtw_mi_check_status(padapter, MI_AP_MODE)) {
++#ifdef CONFIG_AP_WOWLAN
++		rtw_suspend_ap_wow(padapter);
++#else
++		rtw_suspend_normal(padapter);
++#endif /*CONFIG_AP_WOWLAN*/
++	}
++
++
++	RTW_PRINT("rtw suspend success in %d ms\n",
++		  rtw_get_passing_time_ms(start_time));
++
++exit:
++	RTW_INFO("<===  %s return %d.............. in %dms\n", __FUNCTION__
++		 , ret, rtw_get_passing_time_ms(start_time));
++
++	return ret;
++}
++
++#ifdef CONFIG_WOWLAN
++int rtw_resume_process_wow(_adapter *padapter)
++{
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct dvobj_priv *psdpriv = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
++	struct wowlan_ioctl_param poidparam;
++	struct sta_info	*psta = NULL;
++	struct registry_priv  *registry_par = &padapter->registrypriv;
++	int ret = _SUCCESS;
++	u8 en = _FALSE;
++
++	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
++
++	if (padapter) {
++		pwrpriv = adapter_to_pwrctl(padapter);
++	} else {
++		pdbgpriv->dbg_resume_error_cnt++;
++		ret = -1;
++		goto exit;
++	}
++
++	if (RTW_CANNOT_RUN(padapter)) {
++		RTW_INFO("%s pdapter %p bDriverStopped %s bSurpriseRemoved %s\n"
++			 , __func__, padapter
++			 , rtw_is_drv_stopped(padapter) ? "True" : "False"
++			, rtw_is_surprise_removed(padapter) ? "True" : "False");
++		goto exit;
++	}
++
++	pwrpriv->wowlan_in_resume = _TRUE;
++#ifdef CONFIG_PNO_SUPPORT
++#ifdef CONFIG_FWLPS_IN_IPS
++	if (pwrpriv->wowlan_pno_enable)
++		rtw_set_fw_in_ips_mode(padapter, _FALSE);
++#endif /* CONFIG_FWLPS_IN_IPS */
++#endif/* CONFIG_PNO_SUPPORT */
++
++	if (pwrpriv->wowlan_mode == _TRUE) {
++#ifdef CONFIG_LPS
++		if(pwrpriv->wowlan_power_mgmt != PS_MODE_ACTIVE) {
++			rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "WOWLAN");
++			rtw_wow_lps_level_decide(padapter, _FALSE);
++		}
++#endif /* CONFIG_LPS */
++
++		rtw_write8(padapter, 0x426, psdpriv->lifetime_en);
++		rtw_write32(padapter, 0x4c0, psdpriv->pkt_lifetime);
++
++		pwrpriv->bFwCurrentInPSMode = _FALSE;
++
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_PCI_HCI)
++		rtw_mi_intf_stop(padapter);
++		rtw_hal_clear_interrupt(padapter);
++#endif
++
++		#ifdef CONFIG_SDIO_HCI
++		#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
++		if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) {
++			ret = -1;
++			goto exit;
++		}
++		#endif
++		#endif/*CONFIG_SDIO_HCI*/
++
++		/* Disable WOW, set H2C command */
++		poidparam.subcode = WOWLAN_DISABLE;
++		rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam);
++
++#ifdef CONFIG_CONCURRENT_MODE
++		rtw_mi_buddy_reset_drv_sw(padapter);
++#endif
++
++		psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
++		if (psta)
++			set_sta_rate(padapter, psta);
++
++
++		rtw_clr_drv_stopped(padapter);
++		RTW_INFO("%s: wowmode resuming, DriverStopped:%s\n", __func__, rtw_is_drv_stopped(padapter) ? "True" : "False");
++		
++		if(registry_par->suspend_type == FW_IPS_WRC)
++			rtw_hal_set_hwreg(padapter, HW_VAR_VENDOR_WOW_MODE, &en);
++		
++		rtw_mi_start_drv_threads(padapter);
++
++		rtw_mi_intf_start(padapter);
++		
++		if(registry_par->suspend_type == FW_IPS_DISABLE_BBRF && !check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
++			if (!rtw_is_surprise_removed(padapter)) {
++				rtw_hal_deinit(padapter);
++				rtw_hal_init(padapter);
++			}
++			RTW_INFO("FW_IPS_DISABLE_BBRF hal deinit, hal init \n");
++		}
++
++#ifdef CONFIG_CONCURRENT_MODE
++		rtw_mi_buddy_netif_carrier_on(padapter);
++#endif
++
++		/* start netif queue */
++		rtw_mi_netif_wake_queue(padapter);
++
++	} else
++
++		RTW_PRINT("%s: ### ERROR ### wowlan_mode=%d\n", __FUNCTION__, pwrpriv->wowlan_mode);
++
++	if (padapter->pid[1] != 0) {
++		RTW_INFO("pid[1]:%d\n", padapter->pid[1]);
++		rtw_signal_process(padapter->pid[1], SIGUSR2);
++	}
++
++	if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) {
++		if (pwrpriv->wowlan_wake_reason == FW_DECISION_DISCONNECT ||
++		    pwrpriv->wowlan_wake_reason == RX_DISASSOC||
++		    pwrpriv->wowlan_wake_reason == RX_DEAUTH) {
++
++			RTW_INFO("%s: disconnect reason: %02x\n", __func__,
++				 pwrpriv->wowlan_wake_reason);
++			rtw_indicate_disconnect(padapter, 0, _FALSE);
++
++			rtw_sta_media_status_rpt(padapter,
++					 rtw_get_stainfo(&padapter->stapriv,
++					 get_bssid(&padapter->mlmepriv)), 0);
++
++			rtw_free_assoc_resources(padapter, _TRUE);
++			pmlmeinfo->state = WIFI_FW_NULL_STATE;
++
++		} else {
++			RTW_INFO("%s: do roaming\n", __func__);
++			rtw_roaming(padapter, NULL);
++		}
++	}
++
++	if (pwrpriv->wowlan_mode == _TRUE) {
++		pwrpriv->bips_processing = _FALSE;
++		_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
++#ifndef CONFIG_IPS_CHECK_IN_WD
++		rtw_set_pwr_state_check_timer(pwrpriv);
++#endif
++	} else
++		RTW_PRINT("do not reset timer\n");
++
++	pwrpriv->wowlan_mode = _FALSE;
++
++	/* Power On LED */
++#ifdef CONFIG_RTW_SW_LED
++
++	if (pwrpriv->wowlan_wake_reason == RX_DISASSOC||
++	    pwrpriv->wowlan_wake_reason == RX_DEAUTH||
++	    pwrpriv->wowlan_wake_reason == FW_DECISION_DISCONNECT)
++		rtw_led_control(padapter, LED_CTL_NO_LINK);
++	else
++		rtw_led_control(padapter, LED_CTL_LINK);
++#endif
++	/* clean driver side wake up reason. */
++	pwrpriv->wowlan_last_wake_reason = pwrpriv->wowlan_wake_reason;
++	pwrpriv->wowlan_wake_reason = 0;
++
++#ifdef CONFIG_BT_COEXIST
++	rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME);
++#endif /* CONFIG_BT_COEXIST */
++
++exit:
++	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
++	return ret;
++}
++#endif /* #ifdef CONFIG_WOWLAN */
++
++#ifdef CONFIG_AP_WOWLAN
++int rtw_resume_process_ap_wow(_adapter *padapter)
++{
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct dvobj_priv *psdpriv = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
++	struct wowlan_ioctl_param poidparam;
++	struct sta_info	*psta = NULL;
++	int ret = _SUCCESS;
++	u8 ch, bw, offset;
++
++	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
++
++	if (padapter) {
++		pwrpriv = adapter_to_pwrctl(padapter);
++	} else {
++		pdbgpriv->dbg_resume_error_cnt++;
++		ret = -1;
++		goto exit;
++	}
++
++
++#ifdef CONFIG_LPS
++	if(pwrpriv->wowlan_power_mgmt != PS_MODE_ACTIVE) {
++		rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "AP-WOWLAN");
++		rtw_wow_lps_level_decide(padapter, _FALSE);
++	}
++#endif /* CONFIG_LPS */
++
++	pwrpriv->bFwCurrentInPSMode = _FALSE;
++
++	rtw_hal_disable_interrupt(padapter);
++
++	rtw_hal_clear_interrupt(padapter);
++
++	#ifdef CONFIG_SDIO_HCI
++	#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
++	if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) {
++		ret = -1;
++		goto exit;
++	}
++	#endif
++	#endif/*CONFIG_SDIO_HCI*/
++	/* Disable WOW, set H2C command */
++	poidparam.subcode = WOWLAN_AP_DISABLE;
++	rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam);
++	pwrpriv->wowlan_ap_mode = _FALSE;
++
++	rtw_clr_drv_stopped(padapter);
++	RTW_INFO("%s: wowmode resuming, DriverStopped:%s\n", __func__, rtw_is_drv_stopped(padapter) ? "True" : "False");
++
++	rtw_mi_start_drv_threads(padapter);
++
++#if 1
++	if (rtw_mi_check_status(padapter, MI_LINKED)) {
++		ch =  rtw_mi_get_union_chan(padapter);
++		bw = rtw_mi_get_union_bw(padapter);
++		offset = rtw_mi_get_union_offset(padapter);
++		RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", FUNC_ADPT_ARG(padapter), ch, bw, offset);
++		set_channel_bwmode(padapter, ch, offset, bw);
++	}
++#else
++	if (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) {
++		RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", FUNC_ADPT_ARG(padapter), ch, bw, offset);
++		set_channel_bwmode(padapter, ch, offset, bw);
++		rtw_mi_update_union_chan_inf(padapter, ch, offset, bw);
++	}
++#endif
++
++	/*FOR ONE AP - TODO :Multi-AP*/
++	{
++		int i;
++		_adapter *iface;
++		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			iface = dvobj->padapters[i];
++			if ((iface) && rtw_is_adapter_up(iface)) {
++				if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE | WIFI_ASOC_STATE))
++					rtw_reset_drv_sw(iface);
++			}
++		}
++
++	}
++	rtw_mi_intf_start(padapter);
++
++	/* start netif queue */
++	rtw_mi_netif_wake_queue(padapter);
++
++	if (padapter->pid[1] != 0) {
++		RTW_INFO("pid[1]:%d\n", padapter->pid[1]);
++		rtw_signal_process(padapter->pid[1], SIGUSR2);
++	}
++
++#ifdef CONFIG_RESUME_IN_WORKQUEUE
++	/* rtw_unlock_suspend(); */
++#endif /* CONFIG_RESUME_IN_WORKQUEUE */
++
++	pwrpriv->bips_processing = _FALSE;
++	_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
++#ifndef CONFIG_IPS_CHECK_IN_WD
++	rtw_set_pwr_state_check_timer(pwrpriv);
++#endif
++	/* clean driver side wake up reason. */
++	pwrpriv->wowlan_wake_reason = 0;
++
++#ifdef CONFIG_BT_COEXIST
++	rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME);
++#endif /* CONFIG_BT_COEXIST */
++
++	/* Power On LED */
++#ifdef CONFIG_RTW_SW_LED
++
++	rtw_led_control(padapter, LED_CTL_LINK);
++#endif
++exit:
++	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
++	return ret;
++}
++#endif /* #ifdef CONFIG_APWOWLAN */
++
++void rtw_mi_resume_process_normal(_adapter *padapter)
++{
++	int i;
++	_adapter *iface;
++	struct mlme_priv *pmlmepriv;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if ((iface) && rtw_is_adapter_up(iface)) {
++			pmlmepriv = &iface->mlmepriv;
++
++			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
++				RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv));
++
++				if (rtw_chk_roam_flags(iface, RTW_ROAM_ON_RESUME))
++					rtw_roaming(iface, NULL);
++
++			} else if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) {
++				RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(iface), MLME_IS_AP(iface) ? "AP" : "MESH");
++				rtw_ap_restore_network(iface);
++			} else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE))
++				RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv));
++			else
++				RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv));
++		}
++	}
++}
++
++int rtw_resume_process_normal(_adapter *padapter)
++{
++	struct net_device *pnetdev;
++	struct pwrctrl_priv *pwrpriv;
++	struct dvobj_priv *psdpriv;
++	struct debug_priv *pdbgpriv;
++
++	int ret = _SUCCESS;
++
++	if (!padapter) {
++		ret = -1;
++		goto exit;
++	}
++
++	pnetdev = padapter->pnetdev;
++	pwrpriv = adapter_to_pwrctl(padapter);
++	psdpriv = padapter->dvobj;
++	pdbgpriv = &psdpriv->drv_dbg;
++
++	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
++
++	#ifdef CONFIG_SDIO_HCI
++	/* interface init */
++	if (sdio_init(adapter_to_dvobj(padapter)) != _SUCCESS) {
++		ret = -1;
++		goto exit;
++	}
++	#endif/*CONFIG_SDIO_HCI*/
++
++	rtw_clr_surprise_removed(padapter);
++	rtw_hal_disable_interrupt(padapter);
++
++	#ifdef CONFIG_SDIO_HCI
++	#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
++	if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) {
++		ret = -1;
++		goto exit;
++	}
++	#endif
++	#endif/*CONFIG_SDIO_HCI*/
++
++	rtw_mi_reset_drv_sw(padapter);
++
++	pwrpriv->bkeepfwalive = _FALSE;
++
++	RTW_INFO("bkeepfwalive(%x)\n", pwrpriv->bkeepfwalive);
++	if (pm_netdev_open(pnetdev, _TRUE) != 0) {
++		ret = -1;
++		pdbgpriv->dbg_resume_error_cnt++;
++		goto exit;
++	}
++
++	rtw_mi_netif_caron_qstart(padapter);
++
++	if (padapter->pid[1] != 0) {
++		RTW_INFO("pid[1]:%d\n", padapter->pid[1]);
++		rtw_signal_process(padapter->pid[1], SIGUSR2);
++	}
++
++#ifdef CONFIG_BT_COEXIST
++	rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME);
++#endif /* CONFIG_BT_COEXIST */
++
++	rtw_mi_resume_process_normal(padapter);
++
++#ifdef CONFIG_RESUME_IN_WORKQUEUE
++	/* rtw_unlock_suspend(); */
++#endif /* CONFIG_RESUME_IN_WORKQUEUE */
++	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
++
++exit:
++	return ret;
++}
++
++int rtw_resume_common(_adapter *padapter)
++{
++	int ret = 0;
++	systime start_time = rtw_get_current_time();
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++
++	if (pwrpriv == NULL)
++		return 0;
++
++	if (pwrpriv->bInSuspend == _FALSE)
++		return 0;
++
++	RTW_PRINT("resume start\n");
++	RTW_INFO("==> %s (%s:%d)\n", __FUNCTION__, current->comm, current->pid);
++
++	if (rtw_mi_check_status(padapter, MI_AP_MODE) == _FALSE) {
++#ifdef CONFIG_WOWLAN
++		if (pwrpriv->wowlan_mode == _TRUE)
++			rtw_resume_process_wow(padapter);
++		else
++#endif
++			rtw_resume_process_normal(padapter);
++
++	} else if (rtw_mi_check_status(padapter, MI_AP_MODE)) {
++#ifdef CONFIG_AP_WOWLAN
++		rtw_resume_process_ap_wow(padapter);
++#else
++		rtw_resume_process_normal(padapter);
++#endif /* CONFIG_AP_WOWLAN */
++	}
++
++	pwrpriv->bInSuspend = _FALSE;
++	pwrpriv->wowlan_in_resume = _FALSE;
++
++	RTW_PRINT("%s:%d in %d ms\n", __FUNCTION__ , ret,
++		  rtw_get_passing_time_ms(start_time));
++
++
++	return ret;
++}
++
++#ifdef CONFIG_GPIO_API
++u8 rtw_get_gpio(struct net_device *netdev, u8 gpio_num)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
++	return rtw_hal_get_gpio(adapter, gpio_num);
++}
++EXPORT_SYMBOL(rtw_get_gpio);
++
++int  rtw_set_gpio_output_value(struct net_device *netdev, u8 gpio_num, bool isHigh)
++{
++	u8 direction = 0;
++	u8 res = -1;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
++	return rtw_hal_set_gpio_output_value(adapter, gpio_num, isHigh);
++}
++EXPORT_SYMBOL(rtw_set_gpio_output_value);
++
++int rtw_config_gpio(struct net_device *netdev, u8 gpio_num, bool isOutput)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
++	return rtw_hal_config_gpio(adapter, gpio_num, isOutput);
++}
++EXPORT_SYMBOL(rtw_config_gpio);
++int rtw_register_gpio_interrupt(struct net_device *netdev, int gpio_num, void(*callback)(u8 level))
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
++	return rtw_hal_register_gpio_interrupt(adapter, gpio_num, callback);
++}
++EXPORT_SYMBOL(rtw_register_gpio_interrupt);
++
++int rtw_disable_gpio_interrupt(struct net_device *netdev, int gpio_num)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
++	return rtw_hal_disable_gpio_interrupt(adapter, gpio_num);
++}
++EXPORT_SYMBOL(rtw_disable_gpio_interrupt);
++
++#endif /* #ifdef CONFIG_GPIO_API */
++
++#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
++
++int rtw_vendor_ie_get_api(struct net_device *dev, int ie_num, char *extra,
++		u16 extra_len)
++{
++	int ret = 0;
++
++	ret = rtw_vendor_ie_get_raw_data(dev, ie_num, extra, extra_len);
++	return ret;
++}
++EXPORT_SYMBOL(rtw_vendor_ie_get_api);
++
++int rtw_vendor_ie_set_api(struct net_device *dev, char *extra)
++{
++	return rtw_vendor_ie_set(dev, NULL, NULL, extra);
++}
++EXPORT_SYMBOL(rtw_vendor_ie_set_api);
++
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/recv_linux.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/recv_linux.c
+new file mode 100644
+index 000000000..0c80b46b5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/recv_linux.c
+@@ -0,0 +1,678 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RECV_OSDEP_C_
++
++#include <drv_types.h>
++
++int rtw_os_recvframe_duplicate_skb(_adapter *padapter, union recv_frame *pcloneframe, _pkt *pskb)
++{
++	int res = _SUCCESS;
++	_pkt	*pkt_copy = NULL;
++
++	if (pskb == NULL) {
++		RTW_INFO("%s [WARN] skb == NULL, drop frag frame\n", __func__);
++		return _FAIL;
++	}
++#if 1
++	pkt_copy = rtw_skb_copy(pskb);
++
++	if (pkt_copy == NULL) {
++		RTW_INFO("%s [WARN] rtw_skb_copy fail , drop frag frame\n", __func__);
++		return _FAIL;
++	}
++#else
++	pkt_copy = rtw_skb_clone(pskb);
++
++	if (pkt_copy == NULL) {
++		RTW_INFO("%s [WARN] rtw_skb_clone fail , drop frag frame\n", __func__);
++		return _FAIL;
++	}
++#endif
++	pkt_copy->dev = padapter->pnetdev;
++
++	pcloneframe->u.hdr.pkt = pkt_copy;
++	pcloneframe->u.hdr.rx_head = pkt_copy->head;
++	pcloneframe->u.hdr.rx_data = pkt_copy->data;
++	pcloneframe->u.hdr.rx_end = skb_end_pointer(pkt_copy);
++	pcloneframe->u.hdr.rx_tail = skb_tail_pointer(pkt_copy);
++	pcloneframe->u.hdr.len = pkt_copy->len;
++
++	return res;
++}
++
++int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 *pdata, _pkt *pskb)
++{
++	int res = _SUCCESS;
++	u8	shift_sz = 0;
++	u32	skb_len, alloc_sz;
++	_pkt	*pkt_copy = NULL;
++	struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
++
++
++	if (pdata == NULL) {
++		precvframe->u.hdr.pkt = NULL;
++		res = _FAIL;
++		return res;
++	}
++
++
++	/*	Modified by Albert 20101213 */
++	/*	For 8 bytes IP header alignment. */
++	shift_sz = pattrib->qos ? 6 : 0; /*	Qos data, wireless lan header length is 26 */
++
++	skb_len = pattrib->pkt_len;
++
++	/* for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. */
++	/* modify alloc_sz for recvive crc error packet by thomas 2011-06-02 */
++	if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) {
++		/* alloc_sz = 1664;	 */ /* 1664 is 128 alignment. */
++		alloc_sz = (skb_len <= 1650) ? 1664 : (skb_len + 14);
++	} else {
++		alloc_sz = skb_len;
++		/*	6 is for IP header 8 bytes alignment in QoS packet case. */
++		/*	8 is for skb->data 4 bytes alignment. */
++		alloc_sz += 14;
++	}
++
++	pkt_copy = rtw_skb_alloc(alloc_sz);
++
++	if (pkt_copy) {
++		pkt_copy->dev = padapter->pnetdev;
++		pkt_copy->len = skb_len;
++		precvframe->u.hdr.pkt = pkt_copy;
++		precvframe->u.hdr.rx_head = pkt_copy->head;
++		precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz;
++		skb_reserve(pkt_copy, 8 - ((SIZE_PTR)(pkt_copy->data) & 7));  /* force pkt_copy->data at 8-byte alignment address */
++		skb_reserve(pkt_copy, shift_sz);/* force ip_hdr at 8-byte alignment address according to shift_sz. */
++		_rtw_memcpy(pkt_copy->data, pdata, skb_len);
++		precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data;
++	} else {
++#if 0
++		{
++			rtw_free_recvframe(precvframe_if2, &precvpriv->free_recv_queue);
++			rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
++
++			/* The case of can't allocate skb is serious and may never be recovered,
++			 once bDriverStopped is enable, this task should be stopped.*/
++			if (!rtw_is_drv_stopped(secondary_padapter))
++#ifdef PLATFORM_LINUX
++				tasklet_schedule(&precvpriv->recv_tasklet);
++#endif
++			return ret;
++		}
++
++#endif
++
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
++		RTW_INFO("%s:can not allocate memory for skb copy\n", __func__);
++
++		precvframe->u.hdr.pkt = NULL;
++
++		/* rtw_free_recvframe(precvframe, pfree_recv_queue); */
++		/*exit_rtw_os_recv_resource_alloc;*/
++
++		res = _FAIL;
++#else
++		if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) {
++			RTW_INFO("%s: alloc_skb fail , drop frag frame\n", __FUNCTION__);
++			/* rtw_free_recvframe(precvframe, pfree_recv_queue); */
++			res = _FAIL;
++			goto exit_rtw_os_recv_resource_alloc;
++		}
++
++		if (pskb == NULL) {
++			res = _FAIL;
++			goto exit_rtw_os_recv_resource_alloc;
++		}
++
++		precvframe->u.hdr.pkt = rtw_skb_clone(pskb);
++		if (precvframe->u.hdr.pkt) {
++			precvframe->u.hdr.pkt->dev = padapter->pnetdev;
++			precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pdata;
++			precvframe->u.hdr.rx_end =  pdata + alloc_sz;
++		} else {
++			RTW_INFO("%s: rtw_skb_clone fail\n", __FUNCTION__);
++			/* rtw_free_recvframe(precvframe, pfree_recv_queue); */
++			/*exit_rtw_os_recv_resource_alloc;*/
++			res = _FAIL;
++		}
++#endif
++	}
++
++exit_rtw_os_recv_resource_alloc:
++
++	return res;
++
++}
++
++void rtw_os_free_recvframe(union recv_frame *precvframe)
++{
++	if (precvframe->u.hdr.pkt) {
++		rtw_os_pkt_free(precvframe->u.hdr.pkt);
++		precvframe->u.hdr.pkt = NULL;
++	}
++}
++
++/* init os related resource in struct recv_priv */
++int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter)
++{
++	int	res = _SUCCESS;
++
++
++#ifdef CONFIG_RTW_NAPI
++	skb_queue_head_init(&precvpriv->rx_napi_skb_queue);
++#endif /* CONFIG_RTW_NAPI */
++
++	return res;
++}
++
++/* alloc os related resource in union recv_frame */
++int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe)
++{
++	int	res = _SUCCESS;
++
++	precvframe->u.hdr.pkt = NULL;
++
++	return res;
++}
++
++/* free os related resource in union recv_frame */
++void rtw_os_recv_resource_free(struct recv_priv *precvpriv)
++{
++	sint i;
++	union recv_frame *precvframe;
++	precvframe = (union recv_frame *) precvpriv->precv_frame_buf;
++
++
++#ifdef CONFIG_RTW_NAPI
++	if (skb_queue_len(&precvpriv->rx_napi_skb_queue))
++		RTW_WARN("rx_napi_skb_queue not empty\n");
++	rtw_skb_queue_purge(&precvpriv->rx_napi_skb_queue);
++#endif /* CONFIG_RTW_NAPI */
++
++	for (i = 0; i < NR_RECVFRAME; i++) {
++		rtw_os_free_recvframe(precvframe);
++		precvframe++;
++	}
++}
++
++/* alloc os related resource in struct recv_buf */
++int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf)
++{
++	int res = _SUCCESS;
++
++#ifdef CONFIG_USB_HCI
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
++	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
++	struct usb_device	*pusbd = pdvobjpriv->pusbdev;
++#endif
++
++	precvbuf->irp_pending = _FALSE;
++	precvbuf->purb = usb_alloc_urb(0, GFP_KERNEL);
++	if (precvbuf->purb == NULL)
++		res = _FAIL;
++
++	precvbuf->pskb = NULL;
++
++	precvbuf->pallocated_buf  = precvbuf->pbuf = NULL;
++
++	precvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pend = NULL;
++
++	precvbuf->transfer_len = 0;
++
++	precvbuf->len = 0;
++
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
++	precvbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)precvbuf->alloc_sz, &precvbuf->dma_transfer_addr);
++	precvbuf->pbuf = precvbuf->pallocated_buf;
++	if (precvbuf->pallocated_buf == NULL)
++		return _FAIL;
++#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
++
++#endif /* CONFIG_USB_HCI */
++
++	return res;
++}
++
++/* free os related resource in struct recv_buf */
++int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf)
++{
++	int ret = _SUCCESS;
++
++#ifdef CONFIG_USB_HCI
++
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
++
++	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
++	struct usb_device	*pusbd = pdvobjpriv->pusbdev;
++
++	rtw_usb_buffer_free(pusbd, (size_t)precvbuf->alloc_sz, precvbuf->pallocated_buf, precvbuf->dma_transfer_addr);
++	precvbuf->pallocated_buf =  NULL;
++	precvbuf->dma_transfer_addr = 0;
++
++#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
++
++	if (precvbuf->purb) {
++		/* usb_kill_urb(precvbuf->purb); */
++		usb_free_urb(precvbuf->purb);
++	}
++
++#endif /* CONFIG_USB_HCI */
++
++
++	if (precvbuf->pskb) {
++#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
++		if (rtw_free_skb_premem(precvbuf->pskb) != 0)
++#endif
++			rtw_skb_free(precvbuf->pskb);
++	}
++	return ret;
++
++}
++
++_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, const u8 *da, const u8 *sa
++	, u8 *msdu ,u16 msdu_len, enum rtw_rx_llc_hdl llc_hdl)
++{
++	u8	*data_ptr;
++	_pkt *sub_skb;
++	struct rx_pkt_attrib *pattrib;
++
++	pattrib = &prframe->u.hdr.attrib;
++
++#ifdef CONFIG_SKB_COPY
++	sub_skb = rtw_skb_alloc(msdu_len + 14);
++	if (sub_skb) {
++		skb_reserve(sub_skb, 14);
++		data_ptr = (u8 *)skb_put(sub_skb, msdu_len);
++		_rtw_memcpy(data_ptr, msdu, msdu_len);
++	} else
++#endif /* CONFIG_SKB_COPY */
++	{
++		sub_skb = rtw_skb_clone(prframe->u.hdr.pkt);
++		if (sub_skb) {
++			sub_skb->data = msdu;
++			sub_skb->len = msdu_len;
++			skb_set_tail_pointer(sub_skb, msdu_len);
++		} else {
++			RTW_INFO("%s(): rtw_skb_clone() Fail!!!\n", __FUNCTION__);
++			return NULL;
++		}
++	}
++
++	if (llc_hdl) {
++		/* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */
++		skb_pull(sub_skb, SNAP_SIZE);
++		_rtw_memcpy(skb_push(sub_skb, ETH_ALEN), sa, ETH_ALEN);
++		_rtw_memcpy(skb_push(sub_skb, ETH_ALEN), da, ETH_ALEN);
++	} else {
++		/* Leave Ethernet header part of hdr and full payload */
++		u16 len;
++
++		len = htons(sub_skb->len);
++		_rtw_memcpy(skb_push(sub_skb, 2), &len, 2);
++		_rtw_memcpy(skb_push(sub_skb, ETH_ALEN), sa, ETH_ALEN);
++		_rtw_memcpy(skb_push(sub_skb, ETH_ALEN), da, ETH_ALEN);
++	}
++
++	return sub_skb;
++}
++
++#ifdef CONFIG_RTW_NAPI
++static int napi_recv(_adapter *padapter, int budget)
++{
++	_pkt *pskb;
++	struct recv_priv *precvpriv = &padapter->recvpriv;
++	int work_done = 0;
++	struct registry_priv *pregistrypriv = &padapter->registrypriv;
++	u8 rx_ok;
++
++
++	while ((work_done < budget) &&
++	       (!skb_queue_empty(&precvpriv->rx_napi_skb_queue))) {
++		pskb = skb_dequeue(&precvpriv->rx_napi_skb_queue);
++		if (!pskb)
++			break;
++
++		rx_ok = _FALSE;
++
++#ifdef CONFIG_RTW_GRO
++		if (pregistrypriv->en_gro) {
++			if (rtw_napi_gro_receive(&padapter->napi, pskb) != GRO_DROP)
++				rx_ok = _TRUE;
++			goto next;
++		}
++#endif /* CONFIG_RTW_GRO */
++
++		if (rtw_netif_receive_skb(padapter->pnetdev, pskb) == NET_RX_SUCCESS)
++			rx_ok = _TRUE;
++
++next:
++		if (rx_ok == _TRUE) {
++			work_done++;
++			DBG_COUNTER(padapter->rx_logs.os_netif_ok);
++		} else {
++			DBG_COUNTER(padapter->rx_logs.os_netif_err);
++		}
++	}
++
++	return work_done;
++}
++
++int rtw_recv_napi_poll(struct napi_struct *napi, int budget)
++{
++	_adapter *padapter = container_of(napi, _adapter, napi);
++	int work_done = 0;
++	struct recv_priv *precvpriv = &padapter->recvpriv;
++
++
++	work_done = napi_recv(padapter, budget);
++	if (work_done < budget) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) && defined(CONFIG_PCI_HCI)
++		napi_complete_done(napi, work_done);
++#else
++		napi_complete(napi);
++#endif
++		if (!skb_queue_empty(&precvpriv->rx_napi_skb_queue))
++			napi_schedule(napi);
++	}
++
++	return work_done;
++}
++
++#ifdef CONFIG_RTW_NAPI_DYNAMIC
++void dynamic_napi_th_chk (_adapter *adapter)
++{
++
++	if (adapter->registrypriv.en_napi) {
++		struct dvobj_priv *dvobj;
++		struct registry_priv *registry;
++	
++		dvobj = adapter_to_dvobj(adapter);
++		registry = &adapter->registrypriv;
++		if (dvobj->traffic_stat.cur_rx_tp > registry->napi_threshold)
++			dvobj->en_napi_dynamic = 1;
++		else
++			dvobj->en_napi_dynamic = 0;
++	}
++
++}
++#endif /* CONFIG_RTW_NAPI_DYNAMIC */
++#endif /* CONFIG_RTW_NAPI */
++
++void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, union recv_frame *rframe)
++{
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++	struct recv_priv *precvpriv = &(padapter->recvpriv);
++	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
++#ifdef CONFIG_BR_EXT
++	void *br_port = NULL;
++#endif
++	int ret;
++
++	/* Indicat the packets to upper layer */
++	if (pkt) {
++		struct ethhdr *ehdr = (struct ethhdr *)pkt->data;
++
++		DBG_COUNTER(padapter->rx_logs.os_indicate);
++
++#ifdef CONFIG_BR_EXT
++		if (!adapter_use_wds(padapter) && check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) {
++			/* Insert NAT2.5 RX here! */
++			#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
++			br_port = padapter->pnetdev->br_port;
++			#else
++			rcu_read_lock();
++			br_port = rcu_dereference(padapter->pnetdev->rx_handler_data);
++			rcu_read_unlock();
++			#endif
++
++			if (br_port) {
++				int nat25_handle_frame(_adapter *priv, struct sk_buff *skb);
++
++				if (nat25_handle_frame(padapter, pkt) == -1) {
++					/* priv->ext_stats.rx_data_drops++; */
++					/* DEBUG_ERR("RX DROP: nat25_handle_frame fail!\n"); */
++					/* return FAIL; */
++
++					#if 1
++					/* bypass this frame to upper layer!! */
++					#else
++					rtw_skb_free(sub_skb);
++					continue;
++					#endif
++				}
++			}
++		}
++#endif /* CONFIG_BR_EXT */
++
++		/* After eth_type_trans process , pkt->data pointer will move from ethrnet header to ip header */
++		pkt->protocol = eth_type_trans(pkt, padapter->pnetdev);
++		pkt->dev = padapter->pnetdev;
++		pkt->ip_summed = CHECKSUM_NONE; /* CONFIG_TCP_CSUM_OFFLOAD_RX */
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
++		if ((rframe->u.hdr.attrib.csum_valid == 1)
++		    && (rframe->u.hdr.attrib.csum_err == 0))
++			pkt->ip_summed = CHECKSUM_UNNECESSARY;
++#endif /* CONFIG_TCP_CSUM_OFFLOAD_RX */
++
++#ifdef CONFIG_RTW_NAPI
++#ifdef CONFIG_RTW_NAPI_DYNAMIC
++		if (!skb_queue_empty(&precvpriv->rx_napi_skb_queue)
++			&& !adapter_to_dvobj(padapter)->en_napi_dynamic			
++			)
++			napi_recv(padapter, RTL_NAPI_WEIGHT);
++#endif
++
++		if (pregistrypriv->en_napi
++			#ifdef CONFIG_RTW_NAPI_DYNAMIC
++			&& adapter_to_dvobj(padapter)->en_napi_dynamic
++			#endif
++		) {
++			skb_queue_tail(&precvpriv->rx_napi_skb_queue, pkt);
++			#ifndef CONFIG_RTW_NAPI_V2
++			napi_schedule(&padapter->napi);
++			#endif
++			return;
++		}
++#endif /* CONFIG_RTW_NAPI */
++
++		ret = rtw_netif_rx(padapter->pnetdev, pkt);
++		if (ret == NET_RX_SUCCESS)
++			DBG_COUNTER(padapter->rx_logs.os_netif_ok);
++		else
++			DBG_COUNTER(padapter->rx_logs.os_netif_err);
++	}
++}
++
++void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup)
++{
++#ifdef CONFIG_IOCTL_CFG80211
++	enum nl80211_key_type key_type = 0;
++#endif
++	union iwreq_data wrqu;
++	struct iw_michaelmicfailure    ev;
++	struct security_priv	*psecuritypriv = &padapter->securitypriv;
++	systime cur_time = 0;
++
++	if (psecuritypriv->last_mic_err_time == 0)
++		psecuritypriv->last_mic_err_time = rtw_get_current_time();
++	else {
++		cur_time = rtw_get_current_time();
++
++		if (cur_time - psecuritypriv->last_mic_err_time < 60 * HZ) {
++			psecuritypriv->btkip_countermeasure = _TRUE;
++			psecuritypriv->last_mic_err_time = 0;
++			psecuritypriv->btkip_countermeasure_time = cur_time;
++		} else
++			psecuritypriv->last_mic_err_time = rtw_get_current_time();
++	}
++
++#ifdef CONFIG_IOCTL_CFG80211
++	if (bgroup)
++		key_type |= NL80211_KEYTYPE_GROUP;
++	else
++		key_type |= NL80211_KEYTYPE_PAIRWISE;
++
++	cfg80211_michael_mic_failure(padapter->pnetdev, sta->cmn.mac_addr, key_type, -1, NULL, GFP_ATOMIC);
++#endif
++
++	_rtw_memset(&ev, 0x00, sizeof(ev));
++	if (bgroup)
++		ev.flags |= IW_MICFAILURE_GROUP;
++	else
++		ev.flags |= IW_MICFAILURE_PAIRWISE;
++
++	ev.src_addr.sa_family = ARPHRD_ETHER;
++	_rtw_memcpy(ev.src_addr.sa_data, sta->cmn.mac_addr, ETH_ALEN);
++
++	_rtw_memset(&wrqu, 0x00, sizeof(wrqu));
++	wrqu.data.length = sizeof(ev);
++
++#ifndef CONFIG_IOCTL_CFG80211
++	wireless_send_event(padapter->pnetdev, IWEVMICHAELMICFAILURE, &wrqu, (char *) &ev);
++#endif
++}
++
++#ifdef CONFIG_HOSTAPD_MLME
++void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame)
++{
++	_pkt *skb;
++	struct hostapd_priv *phostapdpriv  = padapter->phostapdpriv;
++	struct net_device *pmgnt_netdev = phostapdpriv->pmgnt_netdev;
++
++
++	skb = precv_frame->u.hdr.pkt;
++
++	if (skb == NULL)
++		return;
++
++	skb->data = precv_frame->u.hdr.rx_data;
++	skb->tail = precv_frame->u.hdr.rx_tail;
++	skb->len = precv_frame->u.hdr.len;
++
++	/* pskb_copy = rtw_skb_copy(skb);
++	*	if(skb == NULL) goto _exit; */
++
++	skb->dev = pmgnt_netdev;
++	skb->ip_summed = CHECKSUM_NONE;
++	skb->pkt_type = PACKET_OTHERHOST;
++	/* skb->protocol = __constant_htons(0x0019); ETH_P_80211_RAW */
++	skb->protocol = __constant_htons(0x0003); /*ETH_P_80211_RAW*/
++
++	/* RTW_INFO("(1)data=0x%x, head=0x%x, tail=0x%x, mac_header=0x%x, len=%d\n", skb->data, skb->head, skb->tail, skb->mac_header, skb->len); */
++
++	/* skb->mac.raw = skb->data; */
++	skb_reset_mac_header(skb);
++
++	/* skb_pull(skb, 24); */
++	_rtw_memset(skb->cb, 0, sizeof(skb->cb));
++
++	rtw_netif_rx(pmgnt_netdev, skb);
++
++	precv_frame->u.hdr.pkt = NULL; /* set pointer to NULL before rtw_free_recvframe() if call rtw_netif_rx() */
++}
++#endif /* CONFIG_HOSTAPD_MLME */
++
++#ifdef CONFIG_WIFI_MONITOR
++/* 
++   precv_frame: impossible to be NULL
++   precv_frame: free by caller
++ */
++int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame)
++{
++	int ret = _FAIL;
++	_pkt *skb;
++
++	skb = precv_frame->u.hdr.pkt;
++	if (skb == NULL) {
++		RTW_INFO("%s :skb==NULL something wrong!!!!\n", __func__);
++		goto _recv_drop;
++	}
++
++	skb->data = precv_frame->u.hdr.rx_data;
++	skb_set_tail_pointer(skb, precv_frame->u.hdr.len);
++	skb->len = precv_frame->u.hdr.len;
++	skb->ip_summed = CHECKSUM_NONE;
++	skb->pkt_type = PACKET_OTHERHOST;
++	skb->protocol = htons(0x0019); /* ETH_P_80211_RAW */
++
++	/* send to kernel */
++	rtw_netif_rx(padapter->pnetdev, skb);
++
++	/* pointers to NULL before rtw_free_recvframe() */
++	precv_frame->u.hdr.pkt = NULL;
++
++	ret = _SUCCESS;
++
++_recv_drop:
++	return ret;
++}
++#endif /* CONFIG_WIFI_MONITOR */
++
++inline void rtw_rframe_set_os_pkt(union recv_frame *rframe)
++{
++	_pkt *skb = rframe->u.hdr.pkt;
++
++	skb->data = rframe->u.hdr.rx_data;
++	skb_set_tail_pointer(skb, rframe->u.hdr.len);
++	skb->len = rframe->u.hdr.len;
++}
++
++int rtw_recv_indicatepkt(_adapter *padapter, union recv_frame *precv_frame)
++{
++	struct recv_priv *precvpriv;
++	_queue	*pfree_recv_queue;
++
++	precvpriv = &(padapter->recvpriv);
++	pfree_recv_queue = &(precvpriv->free_recv_queue);
++
++	if (precv_frame->u.hdr.pkt == NULL)
++		goto _recv_indicatepkt_drop;
++
++	rtw_os_recv_indicate_pkt(padapter, precv_frame->u.hdr.pkt, precv_frame);
++
++	precv_frame->u.hdr.pkt = NULL;
++	rtw_free_recvframe(precv_frame, pfree_recv_queue);
++	return _SUCCESS;
++
++_recv_indicatepkt_drop:
++	rtw_free_recvframe(precv_frame, pfree_recv_queue);
++	DBG_COUNTER(padapter->rx_logs.os_indicate_err);
++	return _FAIL;
++}
++
++void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf)
++{
++#ifdef CONFIG_USB_HCI
++	struct recv_priv *precvpriv = &padapter->recvpriv;
++
++	precvbuf->ref_cnt--;
++
++	/* free skb in recv_buf */
++	rtw_skb_free(precvbuf->pskb);
++
++	precvbuf->pskb = NULL;
++
++	if (precvbuf->irp_pending == _FALSE)
++		rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
++
++
++#endif
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	precvbuf->pskb = NULL;
++#endif
++
++}
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rhashtable.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rhashtable.c
+new file mode 100644
+index 000000000..0163a4b07
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rhashtable.c
+@@ -0,0 +1,844 @@
++/*
++ * Resizable, Scalable, Concurrent Hash Table
++ *
++ * Copyright (c) 2015 Herbert Xu <herbert@gondor.apana.org.au>
++ * Copyright (c) 2014-2015 Thomas Graf <tgraf@suug.ch>
++ * Copyright (c) 2008-2014 Patrick McHardy <kaber@trash.net>
++ *
++ * Code partially derived from nft_hash
++ * Rewritten with rehash code from br_multicast plus single list
++ * pointer as suggested by Josh Triplett
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/atomic.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/log2.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/vmalloc.h>
++#include <linux/mm.h>
++#include <linux/jhash.h>
++#include <linux/random.h>
++#include <linux/err.h>
++#include <linux/export.h>
++
++#define HASH_DEFAULT_SIZE	64UL
++#define HASH_MIN_SIZE		4U
++#define BUCKET_LOCKS_PER_CPU   128UL
++
++static u32 head_hashfn(struct rhashtable *ht,
++		       const struct bucket_table *tbl,
++		       const struct rhash_head *he)
++{
++	return rht_head_hashfn(ht, tbl, he, ht->p);
++}
++
++#ifdef CONFIG_PROVE_LOCKING
++#define ASSERT_RHT_MUTEX(HT) BUG_ON(!lockdep_rht_mutex_is_held(HT))
++
++int lockdep_rht_mutex_is_held(struct rhashtable *ht)
++{
++	return (debug_locks) ? lockdep_is_held(&ht->mutex) : 1;
++}
++
++int lockdep_rht_bucket_is_held(const struct bucket_table *tbl, u32 hash)
++{
++	spinlock_t *lock = rht_bucket_lock(tbl, hash);
++
++	return (debug_locks) ? lockdep_is_held(lock) : 1;
++}
++#else
++#define ASSERT_RHT_MUTEX(HT)
++#endif
++
++
++static int alloc_bucket_locks(struct rhashtable *ht, struct bucket_table *tbl,
++			      gfp_t gfp)
++{
++	unsigned int i, size;
++#if defined(CONFIG_PROVE_LOCKING)
++	unsigned int nr_pcpus = 2;
++#else
++	unsigned int nr_pcpus = num_possible_cpus();
++#endif
++
++	nr_pcpus = min_t(unsigned int, nr_pcpus, 32UL);
++	size = roundup_pow_of_two(nr_pcpus * ht->p.locks_mul);
++
++	/* Never allocate more than 0.5 locks per bucket */
++	size = min_t(unsigned int, size, tbl->size >> 1);
++
++	if (sizeof(spinlock_t) != 0) {
++#ifdef CONFIG_NUMA
++		if (size * sizeof(spinlock_t) > PAGE_SIZE &&
++		    gfp == GFP_KERNEL)
++			tbl->locks = vmalloc(size * sizeof(spinlock_t));
++		else
++#endif
++		tbl->locks = kmalloc_array(size, sizeof(spinlock_t),
++					   gfp);
++		if (!tbl->locks)
++			return -ENOMEM;
++		for (i = 0; i < size; i++)
++			spin_lock_init(&tbl->locks[i]);
++	}
++	tbl->locks_mask = size - 1;
++
++	return 0;
++}
++
++static void bucket_table_free(const struct bucket_table *tbl)
++{
++	if (tbl)
++		kvfree(tbl->locks);
++
++	kvfree(tbl);
++}
++
++static void bucket_table_free_rcu(struct rcu_head *head)
++{
++	bucket_table_free(container_of(head, struct bucket_table, rcu));
++}
++
++static struct bucket_table *bucket_table_alloc(struct rhashtable *ht,
++					       size_t nbuckets,
++					       gfp_t gfp)
++{
++	struct bucket_table *tbl = NULL;
++	size_t size;
++	int i;
++
++	size = sizeof(*tbl) + nbuckets * sizeof(tbl->buckets[0]);
++	if (size <= (PAGE_SIZE << PAGE_ALLOC_COSTLY_ORDER) ||
++	    gfp != GFP_KERNEL)
++		tbl = kzalloc(size, gfp | __GFP_NOWARN | __GFP_NORETRY);
++	if (tbl == NULL && gfp == GFP_KERNEL)
++		tbl = vzalloc(size);
++	if (tbl == NULL)
++		return NULL;
++
++	tbl->size = nbuckets;
++
++	if (alloc_bucket_locks(ht, tbl, gfp) < 0) {
++		bucket_table_free(tbl);
++		return NULL;
++	}
++
++	INIT_LIST_HEAD(&tbl->walkers);
++
++	get_random_bytes(&tbl->hash_rnd, sizeof(tbl->hash_rnd));
++
++	for (i = 0; i < nbuckets; i++)
++		INIT_RHT_NULLS_HEAD(tbl->buckets[i], ht, i);
++
++	return tbl;
++}
++
++static struct bucket_table *rhashtable_last_table(struct rhashtable *ht,
++						  struct bucket_table *tbl)
++{
++	struct bucket_table *new_tbl;
++
++	do {
++		new_tbl = tbl;
++		tbl = rht_dereference_rcu(tbl->future_tbl, ht);
++	} while (tbl);
++
++	return new_tbl;
++}
++
++static int rhashtable_rehash_one(struct rhashtable *ht, unsigned int old_hash)
++{
++	struct bucket_table *old_tbl = rht_dereference(ht->tbl, ht);
++	struct bucket_table *new_tbl = rhashtable_last_table(ht,
++		rht_dereference_rcu(old_tbl->future_tbl, ht));
++	struct rhash_head __rcu **pprev = &old_tbl->buckets[old_hash];
++	int err = -ENOENT;
++	struct rhash_head *head, *next, *entry;
++	spinlock_t *new_bucket_lock;
++	unsigned int new_hash;
++
++	rht_for_each(entry, old_tbl, old_hash) {
++		err = 0;
++		next = rht_dereference_bucket(entry->next, old_tbl, old_hash);
++
++		if (rht_is_a_nulls(next))
++			break;
++
++		pprev = &entry->next;
++	}
++
++	if (err)
++		goto out;
++
++	new_hash = head_hashfn(ht, new_tbl, entry);
++
++	new_bucket_lock = rht_bucket_lock(new_tbl, new_hash);
++
++	spin_lock_nested(new_bucket_lock, SINGLE_DEPTH_NESTING);
++	head = rht_dereference_bucket(new_tbl->buckets[new_hash],
++				      new_tbl, new_hash);
++
++	RCU_INIT_POINTER(entry->next, head);
++
++	rcu_assign_pointer(new_tbl->buckets[new_hash], entry);
++	spin_unlock(new_bucket_lock);
++
++	rcu_assign_pointer(*pprev, next);
++
++out:
++	return err;
++}
++
++static void rhashtable_rehash_chain(struct rhashtable *ht,
++				    unsigned int old_hash)
++{
++	struct bucket_table *old_tbl = rht_dereference(ht->tbl, ht);
++	spinlock_t *old_bucket_lock;
++
++	old_bucket_lock = rht_bucket_lock(old_tbl, old_hash);
++
++	spin_lock_bh(old_bucket_lock);
++	while (!rhashtable_rehash_one(ht, old_hash))
++		;
++	old_tbl->rehash++;
++	spin_unlock_bh(old_bucket_lock);
++}
++
++static int rhashtable_rehash_attach(struct rhashtable *ht,
++				    struct bucket_table *old_tbl,
++				    struct bucket_table *new_tbl)
++{
++	/* Protect future_tbl using the first bucket lock. */
++	spin_lock_bh(old_tbl->locks);
++
++	/* Did somebody beat us to it? */
++	if (rcu_access_pointer(old_tbl->future_tbl)) {
++		spin_unlock_bh(old_tbl->locks);
++		return -EEXIST;
++	}
++
++	/* Make insertions go into the new, empty table right away. Deletions
++	 * and lookups will be attempted in both tables until we synchronize.
++	 */
++	rcu_assign_pointer(old_tbl->future_tbl, new_tbl);
++
++	/* Ensure the new table is visible to readers. */
++	smp_wmb();
++
++	spin_unlock_bh(old_tbl->locks);
++
++	return 0;
++}
++
++static int rhashtable_rehash_table(struct rhashtable *ht)
++{
++	struct bucket_table *old_tbl = rht_dereference(ht->tbl, ht);
++	struct bucket_table *new_tbl;
++	struct rhashtable_walker *walker;
++	unsigned int old_hash;
++
++	new_tbl = rht_dereference(old_tbl->future_tbl, ht);
++	if (!new_tbl)
++		return 0;
++
++	for (old_hash = 0; old_hash < old_tbl->size; old_hash++)
++		rhashtable_rehash_chain(ht, old_hash);
++
++	/* Publish the new table pointer. */
++	rcu_assign_pointer(ht->tbl, new_tbl);
++
++	spin_lock(&ht->lock);
++	list_for_each_entry(walker, &old_tbl->walkers, list)
++		walker->tbl = NULL;
++	spin_unlock(&ht->lock);
++
++	/* Wait for readers. All new readers will see the new
++	 * table, and thus no references to the old table will
++	 * remain.
++	 */
++	call_rcu(&old_tbl->rcu, bucket_table_free_rcu);
++
++	return rht_dereference(new_tbl->future_tbl, ht) ? -EAGAIN : 0;
++}
++
++/**
++ * rhashtable_expand - Expand hash table while allowing concurrent lookups
++ * @ht:		the hash table to expand
++ *
++ * A secondary bucket array is allocated and the hash entries are migrated.
++ *
++ * This function may only be called in a context where it is safe to call
++ * synchronize_rcu(), e.g. not within a rcu_read_lock() section.
++ *
++ * The caller must ensure that no concurrent resizing occurs by holding
++ * ht->mutex.
++ *
++ * It is valid to have concurrent insertions and deletions protected by per
++ * bucket locks or concurrent RCU protected lookups and traversals.
++ */
++static int rhashtable_expand(struct rhashtable *ht)
++{
++	struct bucket_table *new_tbl, *old_tbl = rht_dereference(ht->tbl, ht);
++	int err;
++
++	ASSERT_RHT_MUTEX(ht);
++
++	old_tbl = rhashtable_last_table(ht, old_tbl);
++
++	new_tbl = bucket_table_alloc(ht, old_tbl->size * 2, GFP_KERNEL);
++	if (new_tbl == NULL)
++		return -ENOMEM;
++
++	err = rhashtable_rehash_attach(ht, old_tbl, new_tbl);
++	if (err)
++		bucket_table_free(new_tbl);
++
++	return err;
++}
++
++/**
++ * rhashtable_shrink - Shrink hash table while allowing concurrent lookups
++ * @ht:		the hash table to shrink
++ *
++ * This function shrinks the hash table to fit, i.e., the smallest
++ * size would not cause it to expand right away automatically.
++ *
++ * The caller must ensure that no concurrent resizing occurs by holding
++ * ht->mutex.
++ *
++ * The caller must ensure that no concurrent table mutations take place.
++ * It is however valid to have concurrent lookups if they are RCU protected.
++ *
++ * It is valid to have concurrent insertions and deletions protected by per
++ * bucket locks or concurrent RCU protected lookups and traversals.
++ */
++static int rhashtable_shrink(struct rhashtable *ht)
++{
++	struct bucket_table *new_tbl, *old_tbl = rht_dereference(ht->tbl, ht);
++	unsigned int size;
++	int err;
++
++	ASSERT_RHT_MUTEX(ht);
++
++	size = roundup_pow_of_two(atomic_read(&ht->nelems) * 3 / 2);
++	if (size < ht->p.min_size)
++		size = ht->p.min_size;
++
++	if (old_tbl->size <= size)
++		return 0;
++
++	if (rht_dereference(old_tbl->future_tbl, ht))
++		return -EEXIST;
++
++	new_tbl = bucket_table_alloc(ht, size, GFP_KERNEL);
++	if (new_tbl == NULL)
++		return -ENOMEM;
++
++	err = rhashtable_rehash_attach(ht, old_tbl, new_tbl);
++	if (err)
++		bucket_table_free(new_tbl);
++
++	return err;
++}
++
++static void rht_deferred_worker(struct work_struct *work)
++{
++	struct rhashtable *ht;
++	struct bucket_table *tbl;
++	int err = 0;
++
++	ht = container_of(work, struct rhashtable, run_work);
++	mutex_lock(&ht->mutex);
++
++	tbl = rht_dereference(ht->tbl, ht);
++	tbl = rhashtable_last_table(ht, tbl);
++
++	if (rht_grow_above_75(ht, tbl))
++		rhashtable_expand(ht);
++	else if (ht->p.automatic_shrinking && rht_shrink_below_30(ht, tbl))
++		rhashtable_shrink(ht);
++
++	err = rhashtable_rehash_table(ht);
++
++	mutex_unlock(&ht->mutex);
++
++	if (err)
++		schedule_work(&ht->run_work);
++}
++
++static bool rhashtable_check_elasticity(struct rhashtable *ht,
++					struct bucket_table *tbl,
++					unsigned int hash)
++{
++	unsigned int elasticity = ht->elasticity;
++	struct rhash_head *head;
++
++	rht_for_each(head, tbl, hash)
++		if (!--elasticity)
++			return true;
++
++	return false;
++}
++
++int rhashtable_insert_rehash(struct rhashtable *ht,
++			     struct bucket_table *tbl)
++{
++	struct bucket_table *old_tbl;
++	struct bucket_table *new_tbl;
++	unsigned int size;
++	int err;
++
++	old_tbl = rht_dereference_rcu(ht->tbl, ht);
++
++	size = tbl->size;
++
++	err = -EBUSY;
++
++	if (rht_grow_above_75(ht, tbl))
++		size *= 2;
++	/* Do not schedule more than one rehash */
++	else if (old_tbl != tbl)
++		goto fail;
++
++	err = -ENOMEM;
++
++	new_tbl = bucket_table_alloc(ht, size, GFP_ATOMIC);
++	if (new_tbl == NULL)
++		goto fail;
++
++	err = rhashtable_rehash_attach(ht, tbl, new_tbl);
++	if (err) {
++		bucket_table_free(new_tbl);
++		if (err == -EEXIST)
++			err = 0;
++	} else
++		schedule_work(&ht->run_work);
++
++	return err;
++
++fail:
++	/* Do not fail the insert if someone else did a rehash. */
++	if (likely(rcu_dereference_raw(tbl->future_tbl)))
++		return 0;
++
++	/* Schedule async rehash to retry allocation in process context. */
++	if (err == -ENOMEM)
++		schedule_work(&ht->run_work);
++
++	return err;
++}
++
++struct bucket_table *rhashtable_insert_slow(struct rhashtable *ht,
++					    const void *key,
++					    struct rhash_head *obj,
++					    struct bucket_table *tbl)
++{
++	struct rhash_head *head;
++	unsigned int hash;
++	int err;
++
++	tbl = rhashtable_last_table(ht, tbl);
++	hash = head_hashfn(ht, tbl, obj);
++	spin_lock_nested(rht_bucket_lock(tbl, hash), SINGLE_DEPTH_NESTING);
++
++	err = -EEXIST;
++	if (key && rhashtable_lookup_fast(ht, key, ht->p))
++		goto exit;
++
++	err = -E2BIG;
++	if (unlikely(rht_grow_above_max(ht, tbl)))
++		goto exit;
++
++	err = -EAGAIN;
++	if (rhashtable_check_elasticity(ht, tbl, hash) ||
++	    rht_grow_above_100(ht, tbl))
++		goto exit;
++
++	err = 0;
++
++	head = rht_dereference_bucket(tbl->buckets[hash], tbl, hash);
++
++	RCU_INIT_POINTER(obj->next, head);
++
++	rcu_assign_pointer(tbl->buckets[hash], obj);
++
++	atomic_inc(&ht->nelems);
++
++exit:
++	spin_unlock(rht_bucket_lock(tbl, hash));
++
++	if (err == 0)
++		return NULL;
++	else if (err == -EAGAIN)
++		return tbl;
++	else
++		return ERR_PTR(err);
++}
++
++/**
++ * rhashtable_walk_init - Initialise an iterator
++ * @ht:		Table to walk over
++ * @iter:	Hash table Iterator
++ *
++ * This function prepares a hash table walk.
++ *
++ * Note that if you restart a walk after rhashtable_walk_stop you
++ * may see the same object twice.  Also, you may miss objects if
++ * there are removals in between rhashtable_walk_stop and the next
++ * call to rhashtable_walk_start.
++ *
++ * For a completely stable walk you should construct your own data
++ * structure outside the hash table.
++ *
++ * This function may sleep so you must not call it from interrupt
++ * context or with spin locks held.
++ *
++ * You must call rhashtable_walk_exit if this function returns
++ * successfully.
++ */
++int rhashtable_walk_init(struct rhashtable *ht, struct rhashtable_iter *iter)
++{
++	iter->ht = ht;
++	iter->p = NULL;
++	iter->slot = 0;
++	iter->skip = 0;
++
++	iter->walker = kmalloc(sizeof(*iter->walker), GFP_KERNEL);
++	if (!iter->walker)
++		return -ENOMEM;
++
++	spin_lock(&ht->lock);
++	iter->walker->tbl =
++		rcu_dereference_protected(ht->tbl, lockdep_is_held(&ht->lock));
++	list_add(&iter->walker->list, &iter->walker->tbl->walkers);
++	spin_unlock(&ht->lock);
++
++	return 0;
++}
++
++/**
++ * rhashtable_walk_exit - Free an iterator
++ * @iter:	Hash table Iterator
++ *
++ * This function frees resources allocated by rhashtable_walk_init.
++ */
++void rhashtable_walk_exit(struct rhashtable_iter *iter)
++{
++	spin_lock(&iter->ht->lock);
++	if (iter->walker->tbl)
++		list_del(&iter->walker->list);
++	spin_unlock(&iter->ht->lock);
++	kfree(iter->walker);
++}
++
++/**
++ * rhashtable_walk_start - Start a hash table walk
++ * @iter:	Hash table iterator
++ *
++ * Start a hash table walk.  Note that we take the RCU lock in all
++ * cases including when we return an error.  So you must always call
++ * rhashtable_walk_stop to clean up.
++ *
++ * Returns zero if successful.
++ *
++ * Returns -EAGAIN if resize event occured.  Note that the iterator
++ * will rewind back to the beginning and you may use it immediately
++ * by calling rhashtable_walk_next.
++ */
++int rhashtable_walk_start(struct rhashtable_iter *iter)
++	__acquires(RCU)
++{
++	struct rhashtable *ht = iter->ht;
++
++	rcu_read_lock();
++
++	spin_lock(&ht->lock);
++	if (iter->walker->tbl)
++		list_del(&iter->walker->list);
++	spin_unlock(&ht->lock);
++
++	if (!iter->walker->tbl) {
++		iter->walker->tbl = rht_dereference_rcu(ht->tbl, ht);
++		return -EAGAIN;
++	}
++
++	return 0;
++}
++
++/**
++ * rhashtable_walk_next - Return the next object and advance the iterator
++ * @iter:	Hash table iterator
++ *
++ * Note that you must call rhashtable_walk_stop when you are finished
++ * with the walk.
++ *
++ * Returns the next object or NULL when the end of the table is reached.
++ *
++ * Returns -EAGAIN if resize event occured.  Note that the iterator
++ * will rewind back to the beginning and you may continue to use it.
++ */
++void *rhashtable_walk_next(struct rhashtable_iter *iter)
++{
++	struct bucket_table *tbl = iter->walker->tbl;
++	struct rhashtable *ht = iter->ht;
++	struct rhash_head *p = iter->p;
++
++	if (p) {
++		p = rht_dereference_bucket_rcu(p->next, tbl, iter->slot);
++		goto next;
++	}
++
++	for (; iter->slot < tbl->size; iter->slot++) {
++		int skip = iter->skip;
++
++		rht_for_each_rcu(p, tbl, iter->slot) {
++			if (!skip)
++				break;
++			skip--;
++		}
++
++next:
++		if (!rht_is_a_nulls(p)) {
++			iter->skip++;
++			iter->p = p;
++			return rht_obj(ht, p);
++		}
++
++		iter->skip = 0;
++	}
++
++	iter->p = NULL;
++
++	/* Ensure we see any new tables. */
++	smp_rmb();
++
++	iter->walker->tbl = rht_dereference_rcu(tbl->future_tbl, ht);
++	if (iter->walker->tbl) {
++		iter->slot = 0;
++		iter->skip = 0;
++		return ERR_PTR(-EAGAIN);
++	}
++
++	return NULL;
++}
++
++/**
++ * rhashtable_walk_stop - Finish a hash table walk
++ * @iter:	Hash table iterator
++ *
++ * Finish a hash table walk.
++ */
++void rhashtable_walk_stop(struct rhashtable_iter *iter)
++	__releases(RCU)
++{
++	struct rhashtable *ht;
++	struct bucket_table *tbl = iter->walker->tbl;
++
++	if (!tbl)
++		goto out;
++
++	ht = iter->ht;
++
++	spin_lock(&ht->lock);
++	if (tbl->rehash < tbl->size)
++		list_add(&iter->walker->list, &tbl->walkers);
++	else
++		iter->walker->tbl = NULL;
++	spin_unlock(&ht->lock);
++
++	iter->p = NULL;
++
++out:
++	rcu_read_unlock();
++}
++
++static size_t rounded_hashtable_size(const struct rhashtable_params *params)
++{
++	return max(roundup_pow_of_two(params->nelem_hint * 4 / 3),
++		   (unsigned long)params->min_size);
++}
++
++static u32 rhashtable_jhash2(const void *key, u32 length, u32 seed)
++{
++	return jhash2(key, length, seed);
++}
++
++/**
++ * rhashtable_init - initialize a new hash table
++ * @ht:		hash table to be initialized
++ * @params:	configuration parameters
++ *
++ * Initializes a new hash table based on the provided configuration
++ * parameters. A table can be configured either with a variable or
++ * fixed length key:
++ *
++ * Configuration Example 1: Fixed length keys
++ * struct test_obj {
++ *	int			key;
++ *	void *			my_member;
++ *	struct rhash_head	node;
++ * };
++ *
++ * struct rhashtable_params params = {
++ *	.head_offset = offsetof(struct test_obj, node),
++ *	.key_offset = offsetof(struct test_obj, key),
++ *	.key_len = sizeof(int),
++ *	.hashfn = jhash,
++ *	.nulls_base = (1U << RHT_BASE_SHIFT),
++ * };
++ *
++ * Configuration Example 2: Variable length keys
++ * struct test_obj {
++ *	[...]
++ *	struct rhash_head	node;
++ * };
++ *
++ * u32 my_hash_fn(const void *data, u32 len, u32 seed)
++ * {
++ *	struct test_obj *obj = data;
++ *
++ *	return [... hash ...];
++ * }
++ *
++ * struct rhashtable_params params = {
++ *	.head_offset = offsetof(struct test_obj, node),
++ *	.hashfn = jhash,
++ *	.obj_hashfn = my_hash_fn,
++ * };
++ */
++int rhashtable_init(struct rhashtable *ht,
++		    const struct rhashtable_params *params)
++{
++	struct bucket_table *tbl;
++	size_t size;
++
++	size = HASH_DEFAULT_SIZE;
++
++	if ((!params->key_len && !params->obj_hashfn) ||
++	    (params->obj_hashfn && !params->obj_cmpfn))
++		return -EINVAL;
++
++	if (params->nulls_base && params->nulls_base < (1U << RHT_BASE_SHIFT))
++		return -EINVAL;
++
++	memset(ht, 0, sizeof(*ht));
++	mutex_init(&ht->mutex);
++	spin_lock_init(&ht->lock);
++	memcpy(&ht->p, params, sizeof(*params));
++
++	if (params->min_size)
++		ht->p.min_size = roundup_pow_of_two(params->min_size);
++
++	if (params->max_size)
++		ht->p.max_size = rounddown_pow_of_two(params->max_size);
++
++	if (params->insecure_max_entries)
++		ht->p.insecure_max_entries =
++			rounddown_pow_of_two(params->insecure_max_entries);
++	else
++		ht->p.insecure_max_entries = ht->p.max_size * 2;
++
++	ht->p.min_size = max(ht->p.min_size, HASH_MIN_SIZE);
++
++	if (params->nelem_hint)
++		size = rounded_hashtable_size(&ht->p);
++
++	/* The maximum (not average) chain length grows with the
++	 * size of the hash table, at a rate of (log N)/(log log N).
++	 * The value of 16 is selected so that even if the hash
++	 * table grew to 2^32 you would not expect the maximum
++	 * chain length to exceed it unless we are under attack
++	 * (or extremely unlucky).
++	 *
++	 * As this limit is only to detect attacks, we don't need
++	 * to set it to a lower value as you'd need the chain
++	 * length to vastly exceed 16 to have any real effect
++	 * on the system.
++	 */
++	if (!params->insecure_elasticity)
++		ht->elasticity = 16;
++
++	if (params->locks_mul)
++		ht->p.locks_mul = roundup_pow_of_two(params->locks_mul);
++	else
++		ht->p.locks_mul = BUCKET_LOCKS_PER_CPU;
++
++	ht->key_len = ht->p.key_len;
++	if (!params->hashfn) {
++		ht->p.hashfn = jhash;
++
++		if (!(ht->key_len & (sizeof(u32) - 1))) {
++			ht->key_len /= sizeof(u32);
++			ht->p.hashfn = rhashtable_jhash2;
++		}
++	}
++
++	tbl = bucket_table_alloc(ht, size, GFP_KERNEL);
++	if (tbl == NULL)
++		return -ENOMEM;
++
++	atomic_set(&ht->nelems, 0);
++
++	RCU_INIT_POINTER(ht->tbl, tbl);
++
++	INIT_WORK(&ht->run_work, rht_deferred_worker);
++
++	return 0;
++}
++
++/**
++ * rhashtable_free_and_destroy - free elements and destroy hash table
++ * @ht:		the hash table to destroy
++ * @free_fn:	callback to release resources of element
++ * @arg:	pointer passed to free_fn
++ *
++ * Stops an eventual async resize. If defined, invokes free_fn for each
++ * element to releasal resources. Please note that RCU protected
++ * readers may still be accessing the elements. Releasing of resources
++ * must occur in a compatible manner. Then frees the bucket array.
++ *
++ * This function will eventually sleep to wait for an async resize
++ * to complete. The caller is responsible that no further write operations
++ * occurs in parallel.
++ */
++void rhashtable_free_and_destroy(struct rhashtable *ht,
++				 void (*free_fn)(void *ptr, void *arg),
++				 void *arg)
++{
++	const struct bucket_table *tbl;
++	unsigned int i;
++
++	cancel_work_sync(&ht->run_work);
++
++	mutex_lock(&ht->mutex);
++	tbl = rht_dereference(ht->tbl, ht);
++	if (free_fn) {
++		for (i = 0; i < tbl->size; i++) {
++			struct rhash_head *pos, *next;
++
++			for (pos = rht_dereference(tbl->buckets[i], ht),
++			     next = !rht_is_a_nulls(pos) ?
++					rht_dereference(pos->next, ht) : NULL;
++			     !rht_is_a_nulls(pos);
++			     pos = next,
++			     next = !rht_is_a_nulls(pos) ?
++					rht_dereference(pos->next, ht) : NULL)
++				free_fn(rht_obj(ht, pos), arg);
++		}
++	}
++
++	bucket_table_free(tbl);
++	mutex_unlock(&ht->mutex);
++}
++
++void rhashtable_destroy(struct rhashtable *ht)
++{
++	return rhashtable_free_and_destroy(ht, NULL, NULL);
++}
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rhashtable.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rhashtable.h
+new file mode 100644
+index 000000000..b47107ff6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rhashtable.h
+@@ -0,0 +1,827 @@
++/*
++ * Resizable, Scalable, Concurrent Hash Table
++ *
++ * Copyright (c) 2015 Herbert Xu <herbert@gondor.apana.org.au>
++ * Copyright (c) 2014-2015 Thomas Graf <tgraf@suug.ch>
++ * Copyright (c) 2008-2014 Patrick McHardy <kaber@trash.net>
++ *
++ * Code partially derived from nft_hash
++ * Rewritten with rehash code from br_multicast plus single list
++ * pointer as suggested by Josh Triplett
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef _LINUX_RHASHTABLE_H
++#define _LINUX_RHASHTABLE_H
++
++#include <linux/atomic.h>
++#include <linux/compiler.h>
++#include <linux/err.h>
++#include <linux/errno.h>
++#include <linux/jhash.h>
++#include <linux/list_nulls.h>
++#include <linux/workqueue.h>
++#include <linux/mutex.h>
++#include <linux/rcupdate.h>
++
++/*
++ * The end of the chain is marked with a special nulls marks which has
++ * the following format:
++ *
++ * +-------+-----------------------------------------------------+-+
++ * | Base  |                      Hash                           |1|
++ * +-------+-----------------------------------------------------+-+
++ *
++ * Base (4 bits) : Reserved to distinguish between multiple tables.
++ *                 Specified via &struct rhashtable_params.nulls_base.
++ * Hash (27 bits): Full hash (unmasked) of first element added to bucket
++ * 1 (1 bit)     : Nulls marker (always set)
++ *
++ * The remaining bits of the next pointer remain unused for now.
++ */
++#define RHT_BASE_BITS		4
++#define RHT_HASH_BITS		27
++#define RHT_BASE_SHIFT		RHT_HASH_BITS
++
++/* Base bits plus 1 bit for nulls marker */
++#define RHT_HASH_RESERVED_SPACE	(RHT_BASE_BITS + 1)
++
++struct rhash_head {
++	struct rhash_head __rcu		*next;
++};
++
++/**
++ * struct bucket_table - Table of hash buckets
++ * @size: Number of hash buckets
++ * @rehash: Current bucket being rehashed
++ * @hash_rnd: Random seed to fold into hash
++ * @locks_mask: Mask to apply before accessing locks[]
++ * @locks: Array of spinlocks protecting individual buckets
++ * @walkers: List of active walkers
++ * @rcu: RCU structure for freeing the table
++ * @future_tbl: Table under construction during rehashing
++ * @buckets: size * hash buckets
++ */
++struct bucket_table {
++	unsigned int		size;
++	unsigned int		rehash;
++	u32			hash_rnd;
++	unsigned int		locks_mask;
++	spinlock_t		*locks;
++	struct list_head	walkers;
++	struct rcu_head		rcu;
++
++	struct bucket_table __rcu *future_tbl;
++
++	struct rhash_head __rcu	*buckets[] ____cacheline_aligned_in_smp;
++};
++
++/**
++ * struct rhashtable_compare_arg - Key for the function rhashtable_compare
++ * @ht: Hash table
++ * @key: Key to compare against
++ */
++struct rhashtable_compare_arg {
++	struct rhashtable *ht;
++	const void *key;
++};
++
++typedef u32 (*rht_hashfn_t)(const void *data, u32 len, u32 seed);
++typedef u32 (*rht_obj_hashfn_t)(const void *data, u32 len, u32 seed);
++typedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *arg,
++			       const void *obj);
++
++struct rhashtable;
++
++/**
++ * struct rhashtable_params - Hash table construction parameters
++ * @nelem_hint: Hint on number of elements, should be 75% of desired size
++ * @key_len: Length of key
++ * @key_offset: Offset of key in struct to be hashed
++ * @head_offset: Offset of rhash_head in struct to be hashed
++ * @insecure_max_entries: Maximum number of entries (may be exceeded)
++ * @max_size: Maximum size while expanding
++ * @min_size: Minimum size while shrinking
++ * @nulls_base: Base value to generate nulls marker
++ * @insecure_elasticity: Set to true to disable chain length checks
++ * @automatic_shrinking: Enable automatic shrinking of tables
++ * @locks_mul: Number of bucket locks to allocate per cpu (default: 128)
++ * @hashfn: Hash function (default: jhash2 if !(key_len % 4), or jhash)
++ * @obj_hashfn: Function to hash object
++ * @obj_cmpfn: Function to compare key with object
++ */
++struct rhashtable_params {
++	size_t			nelem_hint;
++	size_t			key_len;
++	size_t			key_offset;
++	size_t			head_offset;
++	unsigned int		insecure_max_entries;
++	unsigned int		max_size;
++	unsigned int		min_size;
++	u32			nulls_base;
++	bool			insecure_elasticity;
++	bool			automatic_shrinking;
++	size_t			locks_mul;
++	rht_hashfn_t		hashfn;
++	rht_obj_hashfn_t	obj_hashfn;
++	rht_obj_cmpfn_t		obj_cmpfn;
++};
++
++/**
++ * struct rhashtable - Hash table handle
++ * @tbl: Bucket table
++ * @nelems: Number of elements in table
++ * @key_len: Key length for hashfn
++ * @elasticity: Maximum chain length before rehash
++ * @p: Configuration parameters
++ * @run_work: Deferred worker to expand/shrink asynchronously
++ * @mutex: Mutex to protect current/future table swapping
++ * @lock: Spin lock to protect walker list
++ */
++struct rhashtable {
++	struct bucket_table __rcu	*tbl;
++	atomic_t			nelems;
++	unsigned int			key_len;
++	unsigned int			elasticity;
++	struct rhashtable_params	p;
++	struct work_struct		run_work;
++	struct mutex                    mutex;
++	spinlock_t			lock;
++};
++
++/**
++ * struct rhashtable_walker - Hash table walker
++ * @list: List entry on list of walkers
++ * @tbl: The table that we were walking over
++ */
++struct rhashtable_walker {
++	struct list_head list;
++	struct bucket_table *tbl;
++};
++
++/**
++ * struct rhashtable_iter - Hash table iterator, fits into netlink cb
++ * @ht: Table to iterate through
++ * @p: Current pointer
++ * @walker: Associated rhashtable walker
++ * @slot: Current slot
++ * @skip: Number of entries to skip in slot
++ */
++struct rhashtable_iter {
++	struct rhashtable *ht;
++	struct rhash_head *p;
++	struct rhashtable_walker *walker;
++	unsigned int slot;
++	unsigned int skip;
++};
++
++static inline unsigned long rht_marker(const struct rhashtable *ht, u32 hash)
++{
++	return NULLS_MARKER(ht->p.nulls_base + hash);
++}
++
++#define INIT_RHT_NULLS_HEAD(ptr, ht, hash) \
++	((ptr) = (typeof(ptr)) rht_marker(ht, hash))
++
++static inline bool rht_is_a_nulls(const struct rhash_head *ptr)
++{
++	return ((unsigned long) ptr & 1);
++}
++
++static inline unsigned long rht_get_nulls_value(const struct rhash_head *ptr)
++{
++	return ((unsigned long) ptr) >> 1;
++}
++
++static inline void *rht_obj(const struct rhashtable *ht,
++			    const struct rhash_head *he)
++{
++	return (char *)he - ht->p.head_offset;
++}
++
++static inline unsigned int rht_bucket_index(const struct bucket_table *tbl,
++					    unsigned int hash)
++{
++	return (hash >> RHT_HASH_RESERVED_SPACE) & (tbl->size - 1);
++}
++
++static inline unsigned int rht_key_hashfn(
++	struct rhashtable *ht, const struct bucket_table *tbl,
++	const void *key, const struct rhashtable_params params)
++{
++	unsigned int hash;
++
++	/* params must be equal to ht->p if it isn't constant. */
++	if (!__builtin_constant_p(params.key_len))
++		hash = ht->p.hashfn(key, ht->key_len, tbl->hash_rnd);
++	else if (params.key_len) {
++		unsigned int key_len = params.key_len;
++
++		if (params.hashfn)
++			hash = params.hashfn(key, key_len, tbl->hash_rnd);
++		else if (key_len & (sizeof(u32) - 1))
++			hash = jhash(key, key_len, tbl->hash_rnd);
++		else
++			hash = jhash2(key, key_len / sizeof(u32),
++				      tbl->hash_rnd);
++	} else {
++		unsigned int key_len = ht->p.key_len;
++
++		if (params.hashfn)
++			hash = params.hashfn(key, key_len, tbl->hash_rnd);
++		else
++			hash = jhash(key, key_len, tbl->hash_rnd);
++	}
++
++	return rht_bucket_index(tbl, hash);
++}
++
++static inline unsigned int rht_head_hashfn(
++	struct rhashtable *ht, const struct bucket_table *tbl,
++	const struct rhash_head *he, const struct rhashtable_params params)
++{
++	const char *ptr = rht_obj(ht, he);
++
++	return likely(params.obj_hashfn) ?
++	       rht_bucket_index(tbl, params.obj_hashfn(ptr, params.key_len ?:
++							    ht->p.key_len,
++						       tbl->hash_rnd)) :
++	       rht_key_hashfn(ht, tbl, ptr + params.key_offset, params);
++}
++
++/**
++ * rht_grow_above_75 - returns true if nelems > 0.75 * table-size
++ * @ht:		hash table
++ * @tbl:	current table
++ */
++static inline bool rht_grow_above_75(const struct rhashtable *ht,
++				     const struct bucket_table *tbl)
++{
++	/* Expand table when exceeding 75% load */
++	return atomic_read(&ht->nelems) > (tbl->size / 4 * 3) &&
++	       (!ht->p.max_size || tbl->size < ht->p.max_size);
++}
++
++/**
++ * rht_shrink_below_30 - returns true if nelems < 0.3 * table-size
++ * @ht:		hash table
++ * @tbl:	current table
++ */
++static inline bool rht_shrink_below_30(const struct rhashtable *ht,
++				       const struct bucket_table *tbl)
++{
++	/* Shrink table beneath 30% load */
++	return atomic_read(&ht->nelems) < (tbl->size * 3 / 10) &&
++	       tbl->size > ht->p.min_size;
++}
++
++/**
++ * rht_grow_above_100 - returns true if nelems > table-size
++ * @ht:		hash table
++ * @tbl:	current table
++ */
++static inline bool rht_grow_above_100(const struct rhashtable *ht,
++				      const struct bucket_table *tbl)
++{
++	return atomic_read(&ht->nelems) > tbl->size &&
++		(!ht->p.max_size || tbl->size < ht->p.max_size);
++}
++
++/**
++ * rht_grow_above_max - returns true if table is above maximum
++ * @ht:		hash table
++ * @tbl:	current table
++ */
++static inline bool rht_grow_above_max(const struct rhashtable *ht,
++				      const struct bucket_table *tbl)
++{
++	return ht->p.insecure_max_entries &&
++	       atomic_read(&ht->nelems) >= ht->p.insecure_max_entries;
++}
++
++/* The bucket lock is selected based on the hash and protects mutations
++ * on a group of hash buckets.
++ *
++ * A maximum of tbl->size/2 bucket locks is allocated. This ensures that
++ * a single lock always covers both buckets which may both contains
++ * entries which link to the same bucket of the old table during resizing.
++ * This allows to simplify the locking as locking the bucket in both
++ * tables during resize always guarantee protection.
++ *
++ * IMPORTANT: When holding the bucket lock of both the old and new table
++ * during expansions and shrinking, the old bucket lock must always be
++ * acquired first.
++ */
++static inline spinlock_t *rht_bucket_lock(const struct bucket_table *tbl,
++					  unsigned int hash)
++{
++	return &tbl->locks[hash & tbl->locks_mask];
++}
++
++#ifdef CONFIG_PROVE_LOCKING
++int lockdep_rht_mutex_is_held(struct rhashtable *ht);
++int lockdep_rht_bucket_is_held(const struct bucket_table *tbl, u32 hash);
++#else
++static inline int lockdep_rht_mutex_is_held(struct rhashtable *ht)
++{
++	return 1;
++}
++
++static inline int lockdep_rht_bucket_is_held(const struct bucket_table *tbl,
++					     u32 hash)
++{
++	return 1;
++}
++#endif /* CONFIG_PROVE_LOCKING */
++
++int rhashtable_init(struct rhashtable *ht,
++		    const struct rhashtable_params *params);
++
++struct bucket_table *rhashtable_insert_slow(struct rhashtable *ht,
++					    const void *key,
++					    struct rhash_head *obj,
++					    struct bucket_table *old_tbl);
++int rhashtable_insert_rehash(struct rhashtable *ht, struct bucket_table *tbl);
++
++int rhashtable_walk_init(struct rhashtable *ht, struct rhashtable_iter *iter);
++void rhashtable_walk_exit(struct rhashtable_iter *iter);
++int rhashtable_walk_start(struct rhashtable_iter *iter) __acquires(RCU);
++void *rhashtable_walk_next(struct rhashtable_iter *iter);
++void rhashtable_walk_stop(struct rhashtable_iter *iter) __releases(RCU);
++
++void rhashtable_free_and_destroy(struct rhashtable *ht,
++				 void (*free_fn)(void *ptr, void *arg),
++				 void *arg);
++void rhashtable_destroy(struct rhashtable *ht);
++
++#define rht_dereference(p, ht) \
++	rcu_dereference_protected(p, lockdep_rht_mutex_is_held(ht))
++
++#define rht_dereference_rcu(p, ht) \
++	rcu_dereference_check(p, lockdep_rht_mutex_is_held(ht))
++
++#define rht_dereference_bucket(p, tbl, hash) \
++	rcu_dereference_protected(p, lockdep_rht_bucket_is_held(tbl, hash))
++
++#define rht_dereference_bucket_rcu(p, tbl, hash) \
++	rcu_dereference_check(p, lockdep_rht_bucket_is_held(tbl, hash))
++
++#define rht_entry(tpos, pos, member) \
++	({ tpos = container_of(pos, typeof(*tpos), member); 1; })
++
++/**
++ * rht_for_each_continue - continue iterating over hash chain
++ * @pos:	the &struct rhash_head to use as a loop cursor.
++ * @head:	the previous &struct rhash_head to continue from
++ * @tbl:	the &struct bucket_table
++ * @hash:	the hash value / bucket index
++ */
++#define rht_for_each_continue(pos, head, tbl, hash) \
++	for (pos = rht_dereference_bucket(head, tbl, hash); \
++	     !rht_is_a_nulls(pos); \
++	     pos = rht_dereference_bucket((pos)->next, tbl, hash))
++
++/**
++ * rht_for_each - iterate over hash chain
++ * @pos:	the &struct rhash_head to use as a loop cursor.
++ * @tbl:	the &struct bucket_table
++ * @hash:	the hash value / bucket index
++ */
++#define rht_for_each(pos, tbl, hash) \
++	rht_for_each_continue(pos, (tbl)->buckets[hash], tbl, hash)
++
++/**
++ * rht_for_each_entry_continue - continue iterating over hash chain
++ * @tpos:	the type * to use as a loop cursor.
++ * @pos:	the &struct rhash_head to use as a loop cursor.
++ * @head:	the previous &struct rhash_head to continue from
++ * @tbl:	the &struct bucket_table
++ * @hash:	the hash value / bucket index
++ * @member:	name of the &struct rhash_head within the hashable struct.
++ */
++#define rht_for_each_entry_continue(tpos, pos, head, tbl, hash, member)	\
++	for (pos = rht_dereference_bucket(head, tbl, hash);		\
++	     (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member);	\
++	     pos = rht_dereference_bucket((pos)->next, tbl, hash))
++
++/**
++ * rht_for_each_entry - iterate over hash chain of given type
++ * @tpos:	the type * to use as a loop cursor.
++ * @pos:	the &struct rhash_head to use as a loop cursor.
++ * @tbl:	the &struct bucket_table
++ * @hash:	the hash value / bucket index
++ * @member:	name of the &struct rhash_head within the hashable struct.
++ */
++#define rht_for_each_entry(tpos, pos, tbl, hash, member)		\
++	rht_for_each_entry_continue(tpos, pos, (tbl)->buckets[hash],	\
++				    tbl, hash, member)
++
++/**
++ * rht_for_each_entry_safe - safely iterate over hash chain of given type
++ * @tpos:	the type * to use as a loop cursor.
++ * @pos:	the &struct rhash_head to use as a loop cursor.
++ * @next:	the &struct rhash_head to use as next in loop cursor.
++ * @tbl:	the &struct bucket_table
++ * @hash:	the hash value / bucket index
++ * @member:	name of the &struct rhash_head within the hashable struct.
++ *
++ * This hash chain list-traversal primitive allows for the looped code to
++ * remove the loop cursor from the list.
++ */
++#define rht_for_each_entry_safe(tpos, pos, next, tbl, hash, member)	    \
++	for (pos = rht_dereference_bucket((tbl)->buckets[hash], tbl, hash), \
++	     next = !rht_is_a_nulls(pos) ?				    \
++		       rht_dereference_bucket(pos->next, tbl, hash) : NULL; \
++	     (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member);	    \
++	     pos = next,						    \
++	     next = !rht_is_a_nulls(pos) ?				    \
++		       rht_dereference_bucket(pos->next, tbl, hash) : NULL)
++
++/**
++ * rht_for_each_rcu_continue - continue iterating over rcu hash chain
++ * @pos:	the &struct rhash_head to use as a loop cursor.
++ * @head:	the previous &struct rhash_head to continue from
++ * @tbl:	the &struct bucket_table
++ * @hash:	the hash value / bucket index
++ *
++ * This hash chain list-traversal primitive may safely run concurrently with
++ * the _rcu mutation primitives such as rhashtable_insert() as long as the
++ * traversal is guarded by rcu_read_lock().
++ */
++#define rht_for_each_rcu_continue(pos, head, tbl, hash)			\
++	for (({barrier(); }),						\
++	     pos = rht_dereference_bucket_rcu(head, tbl, hash);		\
++	     !rht_is_a_nulls(pos);					\
++	     pos = rcu_dereference_raw(pos->next))
++
++/**
++ * rht_for_each_rcu - iterate over rcu hash chain
++ * @pos:	the &struct rhash_head to use as a loop cursor.
++ * @tbl:	the &struct bucket_table
++ * @hash:	the hash value / bucket index
++ *
++ * This hash chain list-traversal primitive may safely run concurrently with
++ * the _rcu mutation primitives such as rhashtable_insert() as long as the
++ * traversal is guarded by rcu_read_lock().
++ */
++#define rht_for_each_rcu(pos, tbl, hash)				\
++	rht_for_each_rcu_continue(pos, (tbl)->buckets[hash], tbl, hash)
++
++/**
++ * rht_for_each_entry_rcu_continue - continue iterating over rcu hash chain
++ * @tpos:	the type * to use as a loop cursor.
++ * @pos:	the &struct rhash_head to use as a loop cursor.
++ * @head:	the previous &struct rhash_head to continue from
++ * @tbl:	the &struct bucket_table
++ * @hash:	the hash value / bucket index
++ * @member:	name of the &struct rhash_head within the hashable struct.
++ *
++ * This hash chain list-traversal primitive may safely run concurrently with
++ * the _rcu mutation primitives such as rhashtable_insert() as long as the
++ * traversal is guarded by rcu_read_lock().
++ */
++#define rht_for_each_entry_rcu_continue(tpos, pos, head, tbl, hash, member) \
++	for (({barrier(); }),						    \
++	     pos = rht_dereference_bucket_rcu(head, tbl, hash);		    \
++	     (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member);	    \
++	     pos = rht_dereference_bucket_rcu(pos->next, tbl, hash))
++
++/**
++ * rht_for_each_entry_rcu - iterate over rcu hash chain of given type
++ * @tpos:	the type * to use as a loop cursor.
++ * @pos:	the &struct rhash_head to use as a loop cursor.
++ * @tbl:	the &struct bucket_table
++ * @hash:	the hash value / bucket index
++ * @member:	name of the &struct rhash_head within the hashable struct.
++ *
++ * This hash chain list-traversal primitive may safely run concurrently with
++ * the _rcu mutation primitives such as rhashtable_insert() as long as the
++ * traversal is guarded by rcu_read_lock().
++ */
++#define rht_for_each_entry_rcu(tpos, pos, tbl, hash, member)		\
++	rht_for_each_entry_rcu_continue(tpos, pos, (tbl)->buckets[hash],\
++					tbl, hash, member)
++
++static inline int rhashtable_compare(struct rhashtable_compare_arg *arg,
++				     const void *obj)
++{
++	struct rhashtable *ht = arg->ht;
++	const char *ptr = obj;
++
++	return memcmp(ptr + ht->p.key_offset, arg->key, ht->p.key_len);
++}
++
++/**
++ * rhashtable_lookup_fast - search hash table, inlined version
++ * @ht:		hash table
++ * @key:	the pointer to the key
++ * @params:	hash table parameters
++ *
++ * Computes the hash value for the key and traverses the bucket chain looking
++ * for a entry with an identical key. The first matching entry is returned.
++ *
++ * Returns the first entry on which the compare function returned true.
++ */
++static inline void *rhashtable_lookup_fast(
++	struct rhashtable *ht, const void *key,
++	const struct rhashtable_params params)
++{
++	struct rhashtable_compare_arg arg = {
++		.ht = ht,
++		.key = key,
++	};
++	const struct bucket_table *tbl;
++	struct rhash_head *he;
++	unsigned int hash;
++
++	rcu_read_lock();
++
++	tbl = rht_dereference_rcu(ht->tbl, ht);
++restart:
++	hash = rht_key_hashfn(ht, tbl, key, params);
++	rht_for_each_rcu(he, tbl, hash) {
++		if (params.obj_cmpfn ?
++		    params.obj_cmpfn(&arg, rht_obj(ht, he)) :
++		    rhashtable_compare(&arg, rht_obj(ht, he)))
++			continue;
++		rcu_read_unlock();
++		return rht_obj(ht, he);
++	}
++
++	/* Ensure we see any new tables. */
++	smp_rmb();
++
++	tbl = rht_dereference_rcu(tbl->future_tbl, ht);
++	if (unlikely(tbl))
++		goto restart;
++	rcu_read_unlock();
++
++	return NULL;
++}
++
++/* Internal function, please use rhashtable_insert_fast() instead */
++static inline int __rhashtable_insert_fast(
++	struct rhashtable *ht, const void *key, struct rhash_head *obj,
++	const struct rhashtable_params params)
++{
++	struct rhashtable_compare_arg arg = {
++		.ht = ht,
++		.key = key,
++	};
++	struct bucket_table *tbl, *new_tbl;
++	struct rhash_head *head;
++	spinlock_t *lock;
++	unsigned int elasticity;
++	unsigned int hash;
++	int err;
++
++restart:
++	rcu_read_lock();
++
++	tbl = rht_dereference_rcu(ht->tbl, ht);
++
++	/* All insertions must grab the oldest table containing
++	 * the hashed bucket that is yet to be rehashed.
++	 */
++	for (;;) {
++		hash = rht_head_hashfn(ht, tbl, obj, params);
++		lock = rht_bucket_lock(tbl, hash);
++		spin_lock_bh(lock);
++
++		if (tbl->rehash <= hash)
++			break;
++
++		spin_unlock_bh(lock);
++		tbl = rht_dereference_rcu(tbl->future_tbl, ht);
++	}
++
++	new_tbl = rht_dereference_rcu(tbl->future_tbl, ht);
++	if (unlikely(new_tbl)) {
++		tbl = rhashtable_insert_slow(ht, key, obj, new_tbl);
++		if (!IS_ERR_OR_NULL(tbl))
++			goto slow_path;
++
++		err = PTR_ERR(tbl);
++		goto out;
++	}
++
++	err = -E2BIG;
++	if (unlikely(rht_grow_above_max(ht, tbl)))
++		goto out;
++
++	if (unlikely(rht_grow_above_100(ht, tbl))) {
++slow_path:
++		spin_unlock_bh(lock);
++		err = rhashtable_insert_rehash(ht, tbl);
++		rcu_read_unlock();
++		if (err)
++			return err;
++
++		goto restart;
++	}
++
++	err = -EEXIST;
++	elasticity = ht->elasticity;
++	rht_for_each(head, tbl, hash) {
++		if (key &&
++		    unlikely(!(params.obj_cmpfn ?
++			       params.obj_cmpfn(&arg, rht_obj(ht, head)) :
++			       rhashtable_compare(&arg, rht_obj(ht, head)))))
++			goto out;
++		if (!--elasticity)
++			goto slow_path;
++	}
++
++	err = 0;
++
++	head = rht_dereference_bucket(tbl->buckets[hash], tbl, hash);
++
++	RCU_INIT_POINTER(obj->next, head);
++
++	rcu_assign_pointer(tbl->buckets[hash], obj);
++
++	atomic_inc(&ht->nelems);
++	if (rht_grow_above_75(ht, tbl))
++		schedule_work(&ht->run_work);
++
++out:
++	spin_unlock_bh(lock);
++	rcu_read_unlock();
++
++	return err;
++}
++
++/**
++ * rhashtable_insert_fast - insert object into hash table
++ * @ht:		hash table
++ * @obj:	pointer to hash head inside object
++ * @params:	hash table parameters
++ *
++ * Will take a per bucket spinlock to protect against mutual mutations
++ * on the same bucket. Multiple insertions may occur in parallel unless
++ * they map to the same bucket lock.
++ *
++ * It is safe to call this function from atomic context.
++ *
++ * Will trigger an automatic deferred table resizing if the size grows
++ * beyond the watermark indicated by grow_decision() which can be passed
++ * to rhashtable_init().
++ */
++static inline int rhashtable_insert_fast(
++	struct rhashtable *ht, struct rhash_head *obj,
++	const struct rhashtable_params params)
++{
++	return __rhashtable_insert_fast(ht, NULL, obj, params);
++}
++
++/**
++ * rhashtable_lookup_insert_fast - lookup and insert object into hash table
++ * @ht:		hash table
++ * @obj:	pointer to hash head inside object
++ * @params:	hash table parameters
++ *
++ * Locks down the bucket chain in both the old and new table if a resize
++ * is in progress to ensure that writers can't remove from the old table
++ * and can't insert to the new table during the atomic operation of search
++ * and insertion. Searches for duplicates in both the old and new table if
++ * a resize is in progress.
++ *
++ * This lookup function may only be used for fixed key hash table (key_len
++ * parameter set). It will BUG() if used inappropriately.
++ *
++ * It is safe to call this function from atomic context.
++ *
++ * Will trigger an automatic deferred table resizing if the size grows
++ * beyond the watermark indicated by grow_decision() which can be passed
++ * to rhashtable_init().
++ */
++static inline int rhashtable_lookup_insert_fast(
++	struct rhashtable *ht, struct rhash_head *obj,
++	const struct rhashtable_params params)
++{
++	const char *key = rht_obj(ht, obj);
++
++	BUG_ON(ht->p.obj_hashfn);
++
++	return __rhashtable_insert_fast(ht, key + ht->p.key_offset, obj,
++					params);
++}
++
++/**
++ * rhashtable_lookup_insert_key - search and insert object to hash table
++ *				  with explicit key
++ * @ht:		hash table
++ * @key:	key
++ * @obj:	pointer to hash head inside object
++ * @params:	hash table parameters
++ *
++ * Locks down the bucket chain in both the old and new table if a resize
++ * is in progress to ensure that writers can't remove from the old table
++ * and can't insert to the new table during the atomic operation of search
++ * and insertion. Searches for duplicates in both the old and new table if
++ * a resize is in progress.
++ *
++ * Lookups may occur in parallel with hashtable mutations and resizing.
++ *
++ * Will trigger an automatic deferred table resizing if the size grows
++ * beyond the watermark indicated by grow_decision() which can be passed
++ * to rhashtable_init().
++ *
++ * Returns zero on success.
++ */
++static inline int rhashtable_lookup_insert_key(
++	struct rhashtable *ht, const void *key, struct rhash_head *obj,
++	const struct rhashtable_params params)
++{
++	BUG_ON(!ht->p.obj_hashfn || !key);
++
++	return __rhashtable_insert_fast(ht, key, obj, params);
++}
++
++/* Internal function, please use rhashtable_remove_fast() instead */
++static inline int __rhashtable_remove_fast(
++	struct rhashtable *ht, struct bucket_table *tbl,
++	struct rhash_head *obj, const struct rhashtable_params params)
++{
++	struct rhash_head __rcu **pprev;
++	struct rhash_head *he;
++	spinlock_t * lock;
++	unsigned int hash;
++	int err = -ENOENT;
++
++	hash = rht_head_hashfn(ht, tbl, obj, params);
++	lock = rht_bucket_lock(tbl, hash);
++
++	spin_lock_bh(lock);
++
++	pprev = &tbl->buckets[hash];
++	rht_for_each(he, tbl, hash) {
++		if (he != obj) {
++			pprev = &he->next;
++			continue;
++		}
++
++		rcu_assign_pointer(*pprev, obj->next);
++		err = 0;
++		break;
++	}
++
++	spin_unlock_bh(lock);
++
++	return err;
++}
++
++/**
++ * rhashtable_remove_fast - remove object from hash table
++ * @ht:		hash table
++ * @obj:	pointer to hash head inside object
++ * @params:	hash table parameters
++ *
++ * Since the hash chain is single linked, the removal operation needs to
++ * walk the bucket chain upon removal. The removal operation is thus
++ * considerable slow if the hash table is not correctly sized.
++ *
++ * Will automatically shrink the table via rhashtable_expand() if the
++ * shrink_decision function specified at rhashtable_init() returns true.
++ *
++ * Returns zero on success, -ENOENT if the entry could not be found.
++ */
++static inline int rhashtable_remove_fast(
++	struct rhashtable *ht, struct rhash_head *obj,
++	const struct rhashtable_params params)
++{
++	struct bucket_table *tbl;
++	int err;
++
++	rcu_read_lock();
++
++	tbl = rht_dereference_rcu(ht->tbl, ht);
++
++	/* Because we have already taken (and released) the bucket
++	 * lock in old_tbl, if we find that future_tbl is not yet
++	 * visible then that guarantees the entry to still be in
++	 * the old tbl if it exists.
++	 */
++	while ((err = __rhashtable_remove_fast(ht, tbl, obj, params)) &&
++	       (tbl = rht_dereference_rcu(tbl->future_tbl, ht)))
++		;
++
++	if (err)
++		goto out;
++
++	atomic_dec(&ht->nelems);
++	if (unlikely(ht->p.automatic_shrinking &&
++		     rht_shrink_below_30(ht, tbl)))
++		schedule_work(&ht->run_work);
++
++out:
++	rcu_read_unlock();
++
++	return err;
++}
++
++#endif /* _LINUX_RHASHTABLE_H */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_android.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_android.c
+new file mode 100644
+index 000000000..86cb9f604
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_android.c
+@@ -0,0 +1,1344 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifdef CONFIG_GPIO_WAKEUP
++#include <linux/gpio.h>
++#endif
++
++#include <drv_types.h>
++
++#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC)
++#include <linux/platform_device.h>
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	#include <linux/wlan_plat.h>
++#else
++	#include <linux/wifi_tiwlan.h>
++#endif
++#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
++#define strnicmp	strncasecmp
++#endif /* Linux kernel >= 4.0.0 */
++
++#ifdef CONFIG_GPIO_WAKEUP
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#endif
++
++#include "rtw_version.h"
++
++extern void macstr2num(u8 *dst, u8 *src);
++
++const char *android_wifi_cmd_str[ANDROID_WIFI_CMD_MAX] = {
++	"START",
++	"STOP",
++	"SCAN-ACTIVE",
++	"SCAN-PASSIVE",
++	"RSSI",
++	"LINKSPEED",
++	"RXFILTER-START",
++	"RXFILTER-STOP",
++	"RXFILTER-ADD",
++	"RXFILTER-REMOVE",
++	"BTCOEXSCAN-START",
++	"BTCOEXSCAN-STOP",
++	"BTCOEXMODE",
++	"SETSUSPENDMODE",
++	"SETSUSPENDOPT",
++	"P2P_DEV_ADDR",
++	"SETFWPATH",
++	"SETBAND",
++	"GETBAND",
++	"COUNTRY",
++	"P2P_SET_NOA",
++	"P2P_GET_NOA",
++	"P2P_SET_PS",
++	"SET_AP_WPS_P2P_IE",
++
++	"MIRACAST",
++
++#ifdef CONFIG_PNO_SUPPORT
++	"PNOSSIDCLR",
++	"PNOSETUP",
++	"PNOFORCE",
++	"PNODEBUG",
++#endif
++
++	"MACADDR",
++
++	"BLOCK_SCAN",
++	"BLOCK",
++	"WFD-ENABLE",
++	"WFD-DISABLE",
++	"WFD-SET-TCPPORT",
++	"WFD-SET-MAXTPUT",
++	"WFD-SET-DEVTYPE",
++	"SET_DTIM",
++	"HOSTAPD_SET_MACADDR_ACL",
++	"HOSTAPD_ACL_ADD_STA",
++	"HOSTAPD_ACL_REMOVE_STA",
++#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))
++	"GTK_REKEY_OFFLOAD",
++#endif /* CONFIG_GTK_OL */
++/*	Private command for	P2P disable*/
++	"P2P_DISABLE",
++	"SET_AEK",
++	"EXT_AUTH_STATUS",
++	"DRIVER_VERSION"
++};
++
++#ifdef CONFIG_PNO_SUPPORT
++#define PNO_TLV_PREFIX			'S'
++#define PNO_TLV_VERSION			'1'
++#define PNO_TLV_SUBVERSION		'2'
++#define PNO_TLV_RESERVED		'0'
++#define PNO_TLV_TYPE_SSID_IE	'S'
++#define PNO_TLV_TYPE_TIME		'T'
++#define PNO_TLV_FREQ_REPEAT		'R'
++#define PNO_TLV_FREQ_EXPO_MAX	'M'
++
++typedef struct cmd_tlv {
++	char prefix;
++	char version;
++	char subver;
++	char reserved;
++} cmd_tlv_t;
++
++#ifdef CONFIG_PNO_SET_DEBUG
++char pno_in_example[] = {
++	'P', 'N', 'O', 'S', 'E', 'T', 'U', 'P', ' ',
++	'S', '1', '2', '0',
++	'S',	/* 1 */
++	0x05,
++	'd', 'l', 'i', 'n', 'k',
++	'S',	/* 2 */
++	0x06,
++	'B', 'U', 'F', 'B', 'U', 'F',
++	'S',	/* 3 */
++	0x20,
++	'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', '!', '@', '#', '$', '%', '^',
++	'S',	/* 4 */
++	0x0a,
++	'!', '@', '#', '$', '%', '^', '&', '*', '(', ')',
++	'T',
++	'0', '5',
++	'R',
++	'2',
++	'M',
++	'2',
++	0x00
++};
++#endif /* CONFIG_PNO_SET_DEBUG */
++#endif /* PNO_SUPPORT */
++
++typedef struct android_wifi_priv_cmd {
++	char *buf;
++	int used_len;
++	int total_len;
++} android_wifi_priv_cmd;
++
++#ifdef CONFIG_COMPAT
++typedef struct compat_android_wifi_priv_cmd {
++	compat_uptr_t buf;
++	int used_len;
++	int total_len;
++} compat_android_wifi_priv_cmd;
++#endif /* CONFIG_COMPAT */
++
++/**
++ * Local (static) functions and variables
++ */
++
++/* Initialize g_wifi_on to 1 so dhd_bus_start will be called for the first
++ * time (only) in dhd_open, subsequential wifi on will be handled by
++ * wl_android_wifi_on
++ */
++static int g_wifi_on = _TRUE;
++
++unsigned int oob_irq = 0;
++unsigned int oob_gpio = 0;
++
++#ifdef CONFIG_PNO_SUPPORT
++/*
++ * rtw_android_pno_setup
++ * Description:
++ * This is used for private command.
++ *
++ * Parameter:
++ * net: net_device
++ * command: parameters from private command
++ * total_len: the length of the command.
++ *
++ * */
++static int rtw_android_pno_setup(struct net_device *net, char *command, int total_len)
++{
++	pno_ssid_t pno_ssids_local[MAX_PNO_LIST_COUNT];
++	int res = -1;
++	int nssid = 0;
++	cmd_tlv_t *cmd_tlv_temp;
++	char *str_ptr;
++	int tlv_size_left;
++	int pno_time = 0;
++	int pno_repeat = 0;
++	int pno_freq_expo_max = 0;
++	int cmdlen = strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_PNOSETUP_SET]) + 1;
++
++#ifdef CONFIG_PNO_SET_DEBUG
++	int i;
++	char *p;
++	p = pno_in_example;
++
++	total_len = sizeof(pno_in_example);
++	str_ptr = p + cmdlen;
++#else
++	str_ptr = command + cmdlen;
++#endif
++
++	if (total_len < (cmdlen + sizeof(cmd_tlv_t))) {
++		RTW_INFO("%s argument=%d less min size\n", __func__, total_len);
++		goto exit_proc;
++	}
++
++	tlv_size_left = total_len - cmdlen;
++
++	cmd_tlv_temp = (cmd_tlv_t *)str_ptr;
++	memset(pno_ssids_local, 0, sizeof(pno_ssids_local));
++
++	if ((cmd_tlv_temp->prefix == PNO_TLV_PREFIX) &&
++	    (cmd_tlv_temp->version == PNO_TLV_VERSION) &&
++	    (cmd_tlv_temp->subver == PNO_TLV_SUBVERSION)) {
++
++		str_ptr += sizeof(cmd_tlv_t);
++		tlv_size_left -= sizeof(cmd_tlv_t);
++
++		nssid = rtw_parse_ssid_list_tlv(&str_ptr, pno_ssids_local,
++			     MAX_PNO_LIST_COUNT, &tlv_size_left);
++		if (nssid <= 0) {
++			RTW_INFO("SSID is not presented or corrupted ret=%d\n", nssid);
++			goto exit_proc;
++		} else {
++			if ((str_ptr[0] != PNO_TLV_TYPE_TIME) || (tlv_size_left <= 1)) {
++				RTW_INFO("%s scan duration corrupted field size %d\n",
++					 __func__, tlv_size_left);
++				goto exit_proc;
++			}
++			str_ptr++;
++			pno_time = simple_strtoul(str_ptr, &str_ptr, 16);
++			RTW_INFO("%s: pno_time=%d\n", __func__, pno_time);
++
++			if (str_ptr[0] != 0) {
++				if ((str_ptr[0] != PNO_TLV_FREQ_REPEAT)) {
++					RTW_INFO("%s pno repeat : corrupted field\n",
++						 __func__);
++					goto exit_proc;
++				}
++				str_ptr++;
++				pno_repeat = simple_strtoul(str_ptr, &str_ptr, 16);
++				RTW_INFO("%s :got pno_repeat=%d\n", __FUNCTION__, pno_repeat);
++				if (str_ptr[0] != PNO_TLV_FREQ_EXPO_MAX) {
++					RTW_INFO("%s FREQ_EXPO_MAX corrupted field size\n",
++						 __func__);
++					goto exit_proc;
++				}
++				str_ptr++;
++				pno_freq_expo_max = simple_strtoul(str_ptr, &str_ptr, 16);
++				RTW_INFO("%s: pno_freq_expo_max=%d\n",
++					 __func__, pno_freq_expo_max);
++			}
++		}
++	} else {
++		RTW_INFO("%s get wrong TLV command\n", __FUNCTION__);
++		goto exit_proc;
++	}
++
++	res = rtw_dev_pno_set(net, pno_ssids_local, nssid, pno_time, pno_repeat, pno_freq_expo_max);
++
++#ifdef CONFIG_PNO_SET_DEBUG
++	rtw_dev_pno_debug(net);
++#endif
++
++exit_proc:
++	return res;
++}
++
++/*
++ * rtw_android_cfg80211_pno_setup
++ * Description:
++ * This is used for cfg80211 sched_scan.
++ *
++ * Parameter:
++ * net: net_device
++ * request: cfg80211_request
++ * */
++
++int rtw_android_cfg80211_pno_setup(struct net_device *net,
++		   struct cfg80211_ssid *ssids, int n_ssids, int interval)
++{
++	int res = -1;
++	int nssid = 0;
++	int pno_time = 0;
++	int pno_repeat = 0;
++	int pno_freq_expo_max = 0;
++	int index = 0;
++	pno_ssid_t pno_ssids_local[MAX_PNO_LIST_COUNT];
++
++	if (n_ssids > MAX_PNO_LIST_COUNT || n_ssids < 0) {
++		RTW_INFO("%s: nssids(%d) is invalid.\n", __func__, n_ssids);
++		return -EINVAL;
++	}
++
++	memset(pno_ssids_local, 0, sizeof(pno_ssids_local));
++
++	nssid = n_ssids;
++
++	for (index = 0 ; index < nssid ; index++) {
++		pno_ssids_local[index].SSID_len = ssids[index].ssid_len;
++		memcpy(pno_ssids_local[index].SSID, ssids[index].ssid,
++		       ssids[index].ssid_len);
++	}
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)
++	if(ssids)
++		rtw_mfree((u8 *)ssids, (n_ssids * sizeof(struct cfg80211_ssid)));
++#endif
++	pno_time = (interval / 1000);
++
++	RTW_INFO("%s: nssids: %d, pno_time=%d\n", __func__, nssid, pno_time);
++
++	res = rtw_dev_pno_set(net, pno_ssids_local, nssid, pno_time,
++			      pno_repeat, pno_freq_expo_max);
++
++#ifdef CONFIG_PNO_SET_DEBUG
++	rtw_dev_pno_debug(net);
++#endif
++exit_proc:
++	return res;
++}
++
++int rtw_android_pno_enable(struct net_device *net, int pno_enable)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
++	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
++
++	if (pwrctl) {
++		pwrctl->wowlan_pno_enable = pno_enable;
++		RTW_INFO("%s: wowlan_pno_enable: %d\n", __func__, pwrctl->wowlan_pno_enable);
++		if (pwrctl->wowlan_pno_enable == 0) {
++			if (pwrctl->pnlo_info != NULL) {
++				rtw_mfree((u8 *)pwrctl->pnlo_info, sizeof(pno_nlo_info_t));
++				pwrctl->pnlo_info = NULL;
++			}
++			if (pwrctl->pno_ssid_list != NULL) {
++				rtw_mfree((u8 *)pwrctl->pno_ssid_list, sizeof(pno_ssid_list_t));
++				pwrctl->pno_ssid_list = NULL;
++			}
++			if (pwrctl->pscan_info != NULL) {
++				rtw_mfree((u8 *)pwrctl->pscan_info, sizeof(pno_scan_info_t));
++				pwrctl->pscan_info = NULL;
++			}
++		}
++		return 0;
++	} else
++		return -1;
++}
++#endif /* CONFIG_PNO_SUPPORT */
++
++int rtw_android_cmdstr_to_num(char *cmdstr)
++{
++	int cmd_num;
++	for (cmd_num = 0 ; cmd_num < ANDROID_WIFI_CMD_MAX; cmd_num++)
++		if (0 == strnicmp(cmdstr , android_wifi_cmd_str[cmd_num], strlen(android_wifi_cmd_str[cmd_num])))
++			break;
++
++	return cmd_num;
++}
++
++int rtw_android_get_rssi(struct net_device *net, char *command, int total_len)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
++	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	struct	wlan_network	*pcur_network = &pmlmepriv->cur_network;
++	int bytes_written = 0;
++
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
++		bytes_written += snprintf(&command[bytes_written], total_len, "%s rssi %d",
++			pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi);
++	}
++
++	return bytes_written;
++}
++
++int rtw_android_get_link_speed(struct net_device *net, char *command, int total_len)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
++	int bytes_written = 0;
++	u16 link_speed = 0;
++
++	link_speed = rtw_get_cur_max_rate(padapter) / 10;
++	bytes_written = snprintf(command, total_len, "LinkSpeed %d", link_speed);
++
++	return bytes_written;
++}
++
++int rtw_android_get_macaddr(struct net_device *net, char *command, int total_len)
++{
++	int bytes_written = 0;
++
++	bytes_written = snprintf(command, total_len, "Macaddr = "MAC_FMT, MAC_ARG(net->dev_addr));
++	return bytes_written;
++}
++
++int rtw_android_set_country(struct net_device *net, char *command, int total_len)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
++	char *country_code = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_COUNTRY]) + 1;
++	int ret = _FAIL;
++
++	ret = rtw_set_country(adapter, country_code);
++
++	return (ret == _SUCCESS) ? 0 : -1;
++}
++
++int rtw_android_get_p2p_dev_addr(struct net_device *net, char *command, int total_len)
++{
++	int bytes_written = 0;
++
++	/* We use the same address as our HW MAC address */
++	_rtw_memcpy(command, net->dev_addr, ETH_ALEN);
++
++	bytes_written = ETH_ALEN;
++	return bytes_written;
++}
++
++int rtw_android_set_block_scan(struct net_device *net, char *command, int total_len)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
++	char *block_value = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_BLOCK_SCAN]) + 1;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	adapter_wdev_data(adapter)->block_scan = (*block_value == '0') ? _FALSE : _TRUE;
++#endif
++
++	return 0;
++}
++
++int rtw_android_set_block(struct net_device *net, char *command, int total_len)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
++	char *block_value = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_BLOCK]) + 1;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	adapter_wdev_data(adapter)->block = (*block_value == '0') ? _FALSE : _TRUE;
++#endif
++
++	return 0;
++}
++
++int rtw_android_setband(struct net_device *net, char *command, int total_len)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
++	char *arg = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SETBAND]) + 1;
++	u32 band = WIFI_FREQUENCY_BAND_AUTO;
++	int ret = _FAIL;
++
++	if (sscanf(arg, "%u", &band) >= 1)
++		ret = rtw_set_band(adapter, band);
++
++	return (ret == _SUCCESS) ? 0 : -1;
++}
++
++int rtw_android_getband(struct net_device *net, char *command, int total_len)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
++	int bytes_written = 0;
++
++	bytes_written = snprintf(command, total_len, "%u", adapter->setband);
++
++	return bytes_written;
++}
++
++#ifdef CONFIG_WFD
++int rtw_android_set_miracast_mode(struct net_device *net, char *command, int total_len)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
++	struct wifi_display_info *wfd_info = &adapter->wfd_info;
++	char *arg = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_MIRACAST]) + 1;
++	u8 mode;
++	int num;
++	int ret = _FAIL;
++
++	num = sscanf(arg, "%hhu", &mode);
++
++	if (num < 1)
++		goto exit;
++
++	switch (mode) {
++	case 1: /* soruce */
++		mode = MIRACAST_SOURCE;
++		break;
++	case 2: /* sink */
++		mode = MIRACAST_SINK;
++		break;
++	case 0: /* disabled */
++	default:
++		mode = MIRACAST_DISABLED;
++		break;
++	}
++	wfd_info->stack_wfd_mode = mode;
++	RTW_INFO("stack miracast mode: %s\n", get_miracast_mode_str(wfd_info->stack_wfd_mode));
++
++	ret = _SUCCESS;
++
++exit:
++	return (ret == _SUCCESS) ? 0 : -1;
++}
++#endif /* CONFIG_WFD */
++
++int get_int_from_command(char *pcmd)
++{
++	int i = 0;
++
++	for (i = 0; i < strlen(pcmd); i++) {
++		if (pcmd[i] == '=') {
++			/*	Skip the '=' and space characters. */
++			i += 2;
++			break;
++		}
++	}
++	return rtw_atoi(pcmd + i) ;
++}
++
++#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))
++int rtw_gtk_offload(struct net_device *net, u8 *cmd_ptr)
++{
++	int i;
++	/* u8 *cmd_ptr = priv_cmd.buf; */
++	struct sta_info *psta;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
++	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	struct security_priv *psecuritypriv = &(padapter->securitypriv);
++	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
++
++
++	if (psta == NULL)
++		RTW_INFO("%s, : Obtain Sta_info fail\n", __func__);
++	else {
++		/* string command length of "GTK_REKEY_OFFLOAD" */
++		cmd_ptr += 18;
++
++		_rtw_memcpy(psta->kek, cmd_ptr, RTW_KEK_LEN);
++		cmd_ptr += RTW_KEK_LEN;
++		/*
++		printk("supplicant KEK: ");
++		for(i=0;i<RTW_KEK_LEN; i++)
++			printk(" %02x ", psta->kek[i]);
++		printk("\n supplicant KCK: ");
++		*/
++		_rtw_memcpy(psta->kck, cmd_ptr, RTW_KCK_LEN);
++		cmd_ptr += RTW_KCK_LEN;
++		/*
++		for(i=0;i<RTW_KEK_LEN; i++)
++			printk(" %02x ", psta->kck[i]);
++		*/
++		_rtw_memcpy(psta->replay_ctr, cmd_ptr, RTW_REPLAY_CTR_LEN);
++		psecuritypriv->binstallKCK_KEK = _TRUE;
++
++		/* printk("\nREPLAY_CTR: "); */
++		/* for(i=0;i<RTW_REPLAY_CTR_LEN; i++) */
++		/* printk(" %02x ", psta->replay_ctr[i]); */
++	}
++
++	return _SUCCESS;
++}
++#endif /* CONFIG_GTK_OL */
++
++#ifdef CONFIG_RTW_MESH_AEK
++static int rtw_android_set_aek(struct net_device *ndev, char *command, int total_len)
++{
++#define SET_AEK_DATA_LEN (ETH_ALEN + 32)
++
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
++	u8 *addr;
++	u8 *aek;
++	int err = 0;
++
++	if (total_len - strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AEK]) - 1 != SET_AEK_DATA_LEN) {
++		err = -EINVAL;
++		goto exit;
++	}
++
++	addr = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AEK]) + 1;
++	aek = addr + ETH_ALEN;
++
++	RTW_PRINT(FUNC_NDEV_FMT" addr="MAC_FMT"\n"
++		, FUNC_NDEV_ARG(ndev), MAC_ARG(addr));
++	if (0)
++		RTW_PRINT(FUNC_NDEV_FMT" aek="KEY_FMT KEY_FMT"\n"
++			, FUNC_NDEV_ARG(ndev), KEY_ARG(aek), KEY_ARG(aek + 16));
++
++	if (rtw_mesh_plink_set_aek(adapter, addr, aek) != _SUCCESS)
++		err = -ENOENT;
++
++exit:
++	return err;
++}
++#endif /* CONFIG_RTW_MESH_AEK */
++
++int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd)
++{
++	#define PRIVATE_COMMAND_MAX_LEN        8192
++	int ret = 0;
++	char *command = NULL;
++	int cmd_num;
++	int bytes_written = 0;
++#ifdef CONFIG_PNO_SUPPORT
++	uint cmdlen = 0;
++	uint pno_enable = 0;
++#endif
++	android_wifi_priv_cmd priv_cmd;
++	_adapter	*padapter = (_adapter *) rtw_netdev_priv(net);
++#ifdef CONFIG_WFD
++	struct wifi_display_info		*pwfd_info;
++#endif
++
++	rtw_lock_suspend();
++
++	if (!ifr->ifr_data) {
++		ret = -EINVAL;
++		goto exit;
++	}
++	if (padapter->registrypriv.mp_mode == 1) {
++		ret = -EINVAL;
++		goto exit;
++	}
++#ifdef CONFIG_COMPAT
++#if (KERNEL_VERSION(4, 6, 0) > LINUX_VERSION_CODE)
++	if (is_compat_task()) {
++#else
++	if (in_compat_syscall()) {
++#endif
++		/* User space is 32-bit, use compat ioctl */
++		compat_android_wifi_priv_cmd compat_priv_cmd;
++
++		if (copy_from_user(&compat_priv_cmd, ifr->ifr_data, sizeof(compat_android_wifi_priv_cmd))) {
++			ret = -EFAULT;
++			goto exit;
++		}
++		priv_cmd.buf = compat_ptr(compat_priv_cmd.buf);
++		priv_cmd.used_len = compat_priv_cmd.used_len;
++		priv_cmd.total_len = compat_priv_cmd.total_len;
++	} else
++#endif /* CONFIG_COMPAT */
++		if (copy_from_user(&priv_cmd, ifr->ifr_data, sizeof(android_wifi_priv_cmd))) {
++			ret = -EFAULT;
++			goto exit;
++		}
++	if (padapter->registrypriv.mp_mode == 1) {
++		ret = -EFAULT;
++		goto exit;
++	}
++	/*RTW_INFO("%s priv_cmd.buf=%p priv_cmd.total_len=%d  priv_cmd.used_len=%d\n",__func__,priv_cmd.buf,priv_cmd.total_len,priv_cmd.used_len);*/
++	if (priv_cmd.total_len > PRIVATE_COMMAND_MAX_LEN || priv_cmd.total_len < 0) {
++		RTW_WARN("%s: invalid private command (%d)\n", __FUNCTION__,
++			priv_cmd.total_len);
++		ret = -EFAULT;
++		goto exit;
++	}
++	
++	command = rtw_zmalloc(priv_cmd.total_len+1);
++	if (!command) {
++		RTW_INFO("%s: failed to allocate memory\n", __FUNCTION__);
++		ret = -ENOMEM;
++		goto exit;
++	}
++	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0))
++	if (!access_ok(priv_cmd.buf, priv_cmd.total_len)) {
++	#else
++	if (!access_ok(VERIFY_READ, priv_cmd.buf, priv_cmd.total_len)) {
++	#endif
++		RTW_INFO("%s: failed to access memory\n", __FUNCTION__);
++		ret = -EFAULT;
++		goto exit;
++	}
++	if (copy_from_user(command, (void *)priv_cmd.buf, priv_cmd.total_len)) {
++		ret = -EFAULT;
++		goto exit;
++	}
++	command[priv_cmd.total_len] = '\0';
++	RTW_INFO("%s: Android private cmd \"%s\" on %s\n"
++		 , __FUNCTION__, command, ifr->ifr_name);
++
++	cmd_num = rtw_android_cmdstr_to_num(command);
++
++	switch (cmd_num) {
++	case ANDROID_WIFI_CMD_START:
++		/* bytes_written = wl_android_wifi_on(net); */
++		goto response;
++	case ANDROID_WIFI_CMD_SETFWPATH:
++		goto response;
++	}
++
++	if (!g_wifi_on) {
++		RTW_INFO("%s: Ignore private cmd \"%s\" - iface %s is down\n"
++			 , __FUNCTION__, command, ifr->ifr_name);
++		ret = 0;
++		goto exit;
++	}
++
++	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
++		switch (cmd_num) {
++		case ANDROID_WIFI_CMD_WFD_ENABLE:
++		case ANDROID_WIFI_CMD_WFD_DISABLE:
++		case ANDROID_WIFI_CMD_WFD_SET_TCPPORT:
++		case ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT:
++		case ANDROID_WIFI_CMD_WFD_SET_DEVTYPE:
++			goto response;
++		}
++	}
++
++	switch (cmd_num) {
++
++	case ANDROID_WIFI_CMD_STOP:
++		/* bytes_written = wl_android_wifi_off(net); */
++		break;
++
++	case ANDROID_WIFI_CMD_SCAN_ACTIVE:
++		/* rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_ACTIVE); */
++#ifdef CONFIG_PLATFORM_MSTAR
++#ifdef CONFIG_IOCTL_CFG80211
++		adapter_wdev_data((_adapter *)rtw_netdev_priv(net))->bandroid_scan = _TRUE;
++#endif /* CONFIG_IOCTL_CFG80211 */
++#endif /* CONFIG_PLATFORM_MSTAR */
++		break;
++	case ANDROID_WIFI_CMD_SCAN_PASSIVE:
++		/* rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_PASSIVE); */
++		break;
++
++	case ANDROID_WIFI_CMD_RSSI:
++		bytes_written = rtw_android_get_rssi(net, command, priv_cmd.total_len);
++		break;
++	case ANDROID_WIFI_CMD_LINKSPEED:
++		bytes_written = rtw_android_get_link_speed(net, command, priv_cmd.total_len);
++		break;
++
++	case ANDROID_WIFI_CMD_MACADDR:
++		bytes_written = rtw_android_get_macaddr(net, command, priv_cmd.total_len);
++		break;
++
++	case ANDROID_WIFI_CMD_BLOCK_SCAN:
++		bytes_written = rtw_android_set_block_scan(net, command, priv_cmd.total_len);
++		break;
++
++	case ANDROID_WIFI_CMD_BLOCK:
++		bytes_written = rtw_android_set_block(net, command, priv_cmd.total_len);
++		break;
++
++	case ANDROID_WIFI_CMD_RXFILTER_START:
++		/* bytes_written = net_os_set_packet_filter(net, 1); */
++		break;
++	case ANDROID_WIFI_CMD_RXFILTER_STOP:
++		/* bytes_written = net_os_set_packet_filter(net, 0); */
++		break;
++	case ANDROID_WIFI_CMD_RXFILTER_ADD:
++		/* int filter_num = *(command + strlen(CMD_RXFILTER_ADD) + 1) - '0'; */
++		/* bytes_written = net_os_rxfilter_add_remove(net, TRUE, filter_num); */
++		break;
++	case ANDROID_WIFI_CMD_RXFILTER_REMOVE:
++		/* int filter_num = *(command + strlen(CMD_RXFILTER_REMOVE) + 1) - '0'; */
++		/* bytes_written = net_os_rxfilter_add_remove(net, FALSE, filter_num); */
++		break;
++
++	case ANDROID_WIFI_CMD_BTCOEXSCAN_START:
++		/* TBD: BTCOEXSCAN-START */
++		break;
++	case ANDROID_WIFI_CMD_BTCOEXSCAN_STOP:
++		/* TBD: BTCOEXSCAN-STOP */
++		break;
++	case ANDROID_WIFI_CMD_BTCOEXMODE:
++#if 0
++		uint mode = *(command + strlen(CMD_BTCOEXMODE) + 1) - '0';
++		if (mode == 1)
++			net_os_set_packet_filter(net, 0); /* DHCP starts */
++		else
++			net_os_set_packet_filter(net, 1); /* DHCP ends */
++#ifdef WL_CFG80211
++		bytes_written = wl_cfg80211_set_btcoex_dhcp(net, command);
++#endif
++#endif
++		break;
++
++	case ANDROID_WIFI_CMD_SETSUSPENDMODE:
++		break;
++
++	case ANDROID_WIFI_CMD_SETSUSPENDOPT:
++		/* bytes_written = wl_android_set_suspendopt(net, command, priv_cmd.total_len); */
++		break;
++
++	case ANDROID_WIFI_CMD_SETBAND:
++		bytes_written = rtw_android_setband(net, command, priv_cmd.total_len);
++		break;
++
++	case ANDROID_WIFI_CMD_GETBAND:
++		bytes_written = rtw_android_getband(net, command, priv_cmd.total_len);
++		break;
++
++	case ANDROID_WIFI_CMD_COUNTRY:
++		bytes_written = rtw_android_set_country(net, command, priv_cmd.total_len);
++		break;
++
++#ifdef CONFIG_PNO_SUPPORT
++	case ANDROID_WIFI_CMD_PNOSSIDCLR_SET:
++		/* bytes_written = dhd_dev_pno_reset(net); */
++		break;
++	case ANDROID_WIFI_CMD_PNOSETUP_SET:
++		bytes_written = rtw_android_pno_setup(net, command, priv_cmd.total_len);
++		break;
++	case ANDROID_WIFI_CMD_PNOENABLE_SET:
++		cmdlen = strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_PNOENABLE_SET]);
++		pno_enable = *(command + cmdlen + 1) - '0';
++		bytes_written = rtw_android_pno_enable(net, pno_enable);
++		break;
++#endif
++
++	case ANDROID_WIFI_CMD_P2P_DEV_ADDR:
++		bytes_written = rtw_android_get_p2p_dev_addr(net, command, priv_cmd.total_len);
++		break;
++	case ANDROID_WIFI_CMD_P2P_SET_NOA:
++		/* int skip = strlen(CMD_P2P_SET_NOA) + 1; */
++		/* bytes_written = wl_cfg80211_set_p2p_noa(net, command + skip, priv_cmd.total_len - skip); */
++		break;
++	case ANDROID_WIFI_CMD_P2P_GET_NOA:
++		/* bytes_written = wl_cfg80211_get_p2p_noa(net, command, priv_cmd.total_len); */
++		break;
++	case ANDROID_WIFI_CMD_P2P_SET_PS:
++		/* int skip = strlen(CMD_P2P_SET_PS) + 1; */
++		/* bytes_written = wl_cfg80211_set_p2p_ps(net, command + skip, priv_cmd.total_len - skip); */
++		break;
++
++#ifdef CONFIG_IOCTL_CFG80211
++	case ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE: {
++		int skip = strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE]) + 3;
++		bytes_written = rtw_cfg80211_set_mgnt_wpsp2pie(net, command + skip, priv_cmd.total_len - skip, *(command + skip - 2) - '0');
++		break;
++	}
++#endif /* CONFIG_IOCTL_CFG80211 */
++
++#ifdef CONFIG_WFD
++
++	case ANDROID_WIFI_CMD_MIRACAST:
++		bytes_written = rtw_android_set_miracast_mode(net, command, priv_cmd.total_len);
++		break;
++
++	case ANDROID_WIFI_CMD_WFD_ENABLE: {
++		/*	Commented by Albert 2012/07/24 */
++		/*	We can enable the WFD function by using the following command: */
++		/*	wpa_cli driver wfd-enable */
++
++		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211)
++			rtw_wfd_enable(padapter, 1);
++		break;
++	}
++
++	case ANDROID_WIFI_CMD_WFD_DISABLE: {
++		/*	Commented by Albert 2012/07/24 */
++		/*	We can disable the WFD function by using the following command: */
++		/*	wpa_cli driver wfd-disable */
++
++		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211)
++			rtw_wfd_enable(padapter, 0);
++		break;
++	}
++	case ANDROID_WIFI_CMD_WFD_SET_TCPPORT: {
++		/*	Commented by Albert 2012/07/24 */
++		/*	We can set the tcp port number by using the following command: */
++		/*	wpa_cli driver wfd-set-tcpport = 554 */
++
++		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211)
++			rtw_wfd_set_ctrl_port(padapter, (u16)get_int_from_command(command));
++		break;
++	}
++	case ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT: {
++		break;
++	}
++	case ANDROID_WIFI_CMD_WFD_SET_DEVTYPE: {
++		/*	Commented by Albert 2012/08/28 */
++		/*	Specify the WFD device type ( WFD source/primary sink ) */
++
++		pwfd_info = &padapter->wfd_info;
++		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) {
++			pwfd_info->wfd_device_type = (u8) get_int_from_command(command);
++			pwfd_info->wfd_device_type &= WFD_DEVINFO_DUAL;
++		}
++		break;
++	}
++#endif
++	case ANDROID_WIFI_CMD_CHANGE_DTIM: {
++#ifdef CONFIG_LPS
++		u8 dtim;
++		u8 *ptr = (u8 *) command;
++
++		ptr += 9;/* string command length of  "SET_DTIM"; */
++
++		dtim = rtw_atoi(ptr);
++
++		RTW_INFO("DTIM=%d\n", dtim);
++
++		rtw_lps_change_dtim_cmd(padapter, dtim);
++#endif
++	}
++	break;
++
++#if CONFIG_RTW_MACADDR_ACL
++	case ANDROID_WIFI_CMD_HOSTAPD_SET_MACADDR_ACL: {
++		rtw_set_macaddr_acl(padapter, RTW_ACL_PERIOD_BSS, get_int_from_command(command));
++		break;
++	}
++	case ANDROID_WIFI_CMD_HOSTAPD_ACL_ADD_STA: {
++		u8 addr[ETH_ALEN] = {0x00};
++		macstr2num(addr, command + strlen("HOSTAPD_ACL_ADD_STA") + 3);	/* 3 is space bar + "=" + space bar these 3 chars */
++		rtw_acl_add_sta(padapter, RTW_ACL_PERIOD_BSS, addr);
++		break;
++	}
++	case ANDROID_WIFI_CMD_HOSTAPD_ACL_REMOVE_STA: {
++		u8 addr[ETH_ALEN] = {0x00};
++		macstr2num(addr, command + strlen("HOSTAPD_ACL_REMOVE_STA") + 3);	/* 3 is space bar + "=" + space bar these 3 chars */
++		rtw_acl_remove_sta(padapter, RTW_ACL_PERIOD_BSS, addr);
++		break;
++	}
++#endif /* CONFIG_RTW_MACADDR_ACL */
++#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))
++	case ANDROID_WIFI_CMD_GTK_REKEY_OFFLOAD:
++		rtw_gtk_offload(net, (u8 *)command);
++		break;
++#endif /* CONFIG_GTK_OL		 */
++	case ANDROID_WIFI_CMD_P2P_DISABLE: {
++#ifdef CONFIG_P2P
++		rtw_p2p_enable(padapter, P2P_ROLE_DISABLE);
++#endif /* CONFIG_P2P */
++		break;
++	}
++
++#ifdef CONFIG_RTW_MESH_AEK
++	case ANDROID_WIFI_CMD_SET_AEK:
++		bytes_written = rtw_android_set_aek(net, command, priv_cmd.total_len);
++		break;
++#endif
++	
++	case ANDROID_WIFI_CMD_EXT_AUTH_STATUS: {
++		rtw_set_external_auth_status(padapter,
++			command + strlen("EXT_AUTH_STATUS "),
++			priv_cmd.total_len - strlen("EXT_AUTH_STATUS "));
++		break;
++	}
++	case ANDROID_WIFI_CMD_DRIVERVERSION: {
++		bytes_written = strlen(DRIVERVERSION);
++		snprintf(command, bytes_written + 1, DRIVERVERSION);
++		break;
++	}
++	default:
++		RTW_INFO("Unknown PRIVATE command %s - ignored\n", command);
++		snprintf(command, 3, "OK");
++		bytes_written = strlen("OK");
++	}
++
++response:
++	if (bytes_written >= 0) {
++		if ((bytes_written == 0) && (priv_cmd.total_len > 0))
++			command[0] = '\0';
++		if (bytes_written >= priv_cmd.total_len) {
++			RTW_INFO("%s: bytes_written = %d\n", __FUNCTION__, bytes_written);
++			bytes_written = priv_cmd.total_len;
++		} else
++			bytes_written++;
++		priv_cmd.used_len = bytes_written;
++		if (copy_to_user((void *)priv_cmd.buf, command, bytes_written)) {
++			RTW_INFO("%s: failed to copy data to user buffer\n", __FUNCTION__);
++			ret = -EFAULT;
++		}
++	} else
++		ret = bytes_written;
++
++exit:
++	rtw_unlock_suspend();
++	if (command)
++		rtw_mfree(command, priv_cmd.total_len + 1);
++
++	return ret;
++}
++
++
++/**
++ * Functions for Android WiFi card detection
++ */
++#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC)
++
++static int g_wifidev_registered = 0;
++static struct semaphore wifi_control_sem;
++static struct wifi_platform_data *wifi_control_data = NULL;
++static struct resource *wifi_irqres = NULL;
++
++static int wifi_add_dev(void);
++static void wifi_del_dev(void);
++
++int rtw_android_wifictrl_func_add(void)
++{
++	int ret = 0;
++	sema_init(&wifi_control_sem, 0);
++
++	ret = wifi_add_dev();
++	if (ret) {
++		RTW_INFO("%s: platform_driver_register failed\n", __FUNCTION__);
++		return ret;
++	}
++	g_wifidev_registered = 1;
++
++	/* Waiting callback after platform_driver_register is done or exit with error */
++	if (down_timeout(&wifi_control_sem,  msecs_to_jiffies(1000)) != 0) {
++		ret = -EINVAL;
++		RTW_INFO("%s: platform_driver_register timeout\n", __FUNCTION__);
++	}
++
++	return ret;
++}
++
++void rtw_android_wifictrl_func_del(void)
++{
++	if (g_wifidev_registered) {
++		wifi_del_dev();
++		g_wifidev_registered = 0;
++	}
++}
++
++void *wl_android_prealloc(int section, unsigned long size)
++{
++	void *alloc_ptr = NULL;
++	if (wifi_control_data && wifi_control_data->mem_prealloc) {
++		alloc_ptr = wifi_control_data->mem_prealloc(section, size);
++		if (alloc_ptr) {
++			RTW_INFO("success alloc section %d\n", section);
++			if (size != 0L)
++				memset(alloc_ptr, 0, size);
++			return alloc_ptr;
++		}
++	}
++
++	RTW_INFO("can't alloc section %d\n", section);
++	return NULL;
++}
++
++int wifi_get_irq_number(unsigned long *irq_flags_ptr)
++{
++	if (wifi_irqres) {
++		*irq_flags_ptr = wifi_irqres->flags & IRQF_TRIGGER_MASK;
++		return (int)wifi_irqres->start;
++	}
++#ifdef CUSTOM_OOB_GPIO_NUM
++	return CUSTOM_OOB_GPIO_NUM;
++#else
++	return -1;
++#endif
++}
++
++int wifi_set_power(int on, unsigned long msec)
++{
++	RTW_INFO("%s = %d\n", __FUNCTION__, on);
++	if (wifi_control_data && wifi_control_data->set_power)
++		wifi_control_data->set_power(on);
++	if (msec)
++		msleep(msec);
++	return 0;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++int wifi_get_mac_addr(unsigned char *buf)
++{
++	RTW_INFO("%s\n", __FUNCTION__);
++	if (!buf)
++		return -EINVAL;
++	if (wifi_control_data && wifi_control_data->get_mac_addr)
++		return wifi_control_data->get_mac_addr(buf);
++	return -EOPNOTSUPP;
++}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) */
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) || defined(COMPAT_KERNEL_RELEASE)
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
++void *wifi_get_country_code(char *ccode, u32 flags)
++#else /* Linux kernel < 3.18 */
++void *wifi_get_country_code(char *ccode)
++#endif /* Linux kernel < 3.18 */
++{
++	RTW_INFO("%s\n", __FUNCTION__);
++	if (!ccode)
++		return NULL;
++	if (wifi_control_data && wifi_control_data->get_country_code)
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
++		return wifi_control_data->get_country_code(ccode, flags);
++#else /* Linux kernel < 3.18 */
++		return wifi_control_data->get_country_code(ccode);
++#endif /* Linux kernel < 3.18 */
++	return NULL;
++}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) */
++
++static int wifi_set_carddetect(int on)
++{
++	RTW_INFO("%s = %d\n", __FUNCTION__, on);
++	if (wifi_control_data && wifi_control_data->set_carddetect)
++		wifi_control_data->set_carddetect(on);
++	return 0;
++}
++
++static int wifi_probe(struct platform_device *pdev)
++{
++	struct wifi_platform_data *wifi_ctrl =
++		(struct wifi_platform_data *)(pdev->dev.platform_data);
++	int wifi_wake_gpio = 0;
++
++	RTW_INFO("## %s\n", __FUNCTION__);
++	wifi_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "bcmdhd_wlan_irq");
++
++	if (wifi_irqres == NULL)
++		wifi_irqres = platform_get_resource_byname(pdev,
++				IORESOURCE_IRQ, "bcm4329_wlan_irq");
++	else
++		wifi_wake_gpio = wifi_irqres->start;
++
++#ifdef CONFIG_GPIO_WAKEUP
++	RTW_INFO("%s: gpio:%d wifi_wake_gpio:%d\n", __func__,
++	       (int)wifi_irqres->start, wifi_wake_gpio);
++
++	if (wifi_wake_gpio > 0) {
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++		wifi_configure_gpio();
++#else /* CONFIG_PLATFORM_INTEL_BYT */
++		gpio_request(wifi_wake_gpio, "oob_irq");
++		gpio_direction_input(wifi_wake_gpio);
++		oob_irq = gpio_to_irq(wifi_wake_gpio);
++#endif /* CONFIG_PLATFORM_INTEL_BYT */
++		RTW_INFO("%s oob_irq:%d\n", __func__, oob_irq);
++	} else if (wifi_irqres) {
++		oob_irq = wifi_irqres->start;
++		RTW_INFO("%s oob_irq:%d\n", __func__, oob_irq);
++	}
++#endif
++	wifi_control_data = wifi_ctrl;
++
++	wifi_set_power(1, 0);	/* Power On */
++	wifi_set_carddetect(1);	/* CardDetect (0->1) */
++
++	up(&wifi_control_sem);
++	return 0;
++}
++
++#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN
++extern PADAPTER g_test_adapter;
++
++static void shutdown_card(void)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(g_test_adapter);
++	u32 addr;
++	u8 tmp8, cnt = 0;
++
++	if (NULL == g_test_adapter) {
++		RTW_INFO("%s: padapter==NULL\n", __FUNCTION__);
++		return;
++	}
++
++#ifdef CONFIG_FWLPS_IN_IPS
++	LeaveAllPowerSaveMode(g_test_adapter);
++#endif /* CONFIG_FWLPS_IN_IPS */
++
++#ifdef CONFIG_WOWLAN
++#ifdef CONFIG_GPIO_WAKEUP
++	/*default wake up pin change to BT*/
++	RTW_INFO("%s:default wake up pin change to BT\n", __FUNCTION__);
++	rtw_hal_switch_gpio_wl_ctrl(g_test_adapter, pwrpriv->wowlan_gpio_index, _FALSE);
++#endif /* CONFIG_GPIO_WAKEUP */
++#endif /* CONFIG_WOWLAN */
++
++	/* Leave SDIO HCI Suspend */
++	addr = 0x10250086;
++	rtw_write8(g_test_adapter, addr, 0);
++	do {
++		tmp8 = rtw_read8(g_test_adapter, addr);
++		cnt++;
++		RTW_INFO(FUNC_ADPT_FMT ": polling SDIO_HSUS_CTRL(0x%x)=0x%x, cnt=%d\n",
++			 FUNC_ADPT_ARG(g_test_adapter), addr, tmp8, cnt);
++
++		if (tmp8 & BIT(1))
++			break;
++
++		if (cnt >= 100) {
++			RTW_INFO(FUNC_ADPT_FMT ": polling 0x%x[1]==1 FAIL!!\n",
++				 FUNC_ADPT_ARG(g_test_adapter), addr);
++			break;
++		}
++
++		rtw_mdelay_os(10);
++	} while (1);
++
++	/* unlock register I/O */
++	rtw_write8(g_test_adapter, 0x1C, 0);
++
++	/* enable power down function */
++	/* 0x04[4] = 1 */
++	/* 0x05[7] = 1 */
++	addr = 0x04;
++	tmp8 = rtw_read8(g_test_adapter, addr);
++	tmp8 |= BIT(4);
++	rtw_write8(g_test_adapter, addr, tmp8);
++	RTW_INFO(FUNC_ADPT_FMT ": read after write 0x%x=0x%x\n",
++		FUNC_ADPT_ARG(g_test_adapter), addr, rtw_read8(g_test_adapter, addr));
++
++	addr = 0x05;
++	tmp8 = rtw_read8(g_test_adapter, addr);
++	tmp8 |= BIT(7);
++	rtw_write8(g_test_adapter, addr, tmp8);
++	RTW_INFO(FUNC_ADPT_FMT ": read after write 0x%x=0x%x\n",
++		FUNC_ADPT_ARG(g_test_adapter), addr, rtw_read8(g_test_adapter, addr));
++
++	/* lock register page0 0x0~0xB read/write */
++	rtw_write8(g_test_adapter, 0x1C, 0x0E);
++
++	rtw_set_surprise_removed(g_test_adapter);
++	RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=%s\n",
++		FUNC_ADPT_ARG(g_test_adapter), rtw_is_surprise_removed(g_test_adapter) ? "True" : "False");
++}
++#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */
++
++static int wifi_remove(struct platform_device *pdev)
++{
++	struct wifi_platform_data *wifi_ctrl =
++		(struct wifi_platform_data *)(pdev->dev.platform_data);
++
++	RTW_INFO("## %s\n", __FUNCTION__);
++	wifi_control_data = wifi_ctrl;
++
++	wifi_set_power(0, 0);	/* Power Off */
++	wifi_set_carddetect(0);	/* CardDetect (1->0) */
++
++	up(&wifi_control_sem);
++	return 0;
++}
++
++#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN
++static void wifi_shutdown(struct platform_device *pdev)
++{
++	struct wifi_platform_data *wifi_ctrl =
++		(struct wifi_platform_data *)(pdev->dev.platform_data);
++
++
++	RTW_INFO("## %s\n", __FUNCTION__);
++
++	wifi_control_data = wifi_ctrl;
++
++	shutdown_card();
++	wifi_set_power(0, 0);	/* Power Off */
++	wifi_set_carddetect(0);	/* CardDetect (1->0) */
++}
++#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */
++
++static int wifi_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	RTW_INFO("##> %s\n", __FUNCTION__);
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY)
++	bcmsdh_oob_intr_set(0);
++#endif
++	return 0;
++}
++
++static int wifi_resume(struct platform_device *pdev)
++{
++	RTW_INFO("##> %s\n", __FUNCTION__);
++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY)
++	if (dhd_os_check_if_up(bcmsdh_get_drvdata()))
++		bcmsdh_oob_intr_set(1);
++#endif
++	return 0;
++}
++
++/* temporarily use these two */
++static struct platform_driver wifi_device = {
++	.probe          = wifi_probe,
++	.remove         = wifi_remove,
++	.suspend        = wifi_suspend,
++	.resume         = wifi_resume,
++#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN
++	.shutdown       = wifi_shutdown,
++#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */
++	.driver         = {
++		.name   = "bcmdhd_wlan",
++	}
++};
++
++static struct platform_driver wifi_device_legacy = {
++	.probe          = wifi_probe,
++	.remove         = wifi_remove,
++	.suspend        = wifi_suspend,
++	.resume         = wifi_resume,
++	.driver         = {
++		.name   = "bcm4329_wlan",
++	}
++};
++
++static int wifi_add_dev(void)
++{
++	RTW_INFO("## Calling platform_driver_register\n");
++	platform_driver_register(&wifi_device);
++	platform_driver_register(&wifi_device_legacy);
++	return 0;
++}
++
++static void wifi_del_dev(void)
++{
++	RTW_INFO("## Unregister platform_driver_register\n");
++	platform_driver_unregister(&wifi_device);
++	platform_driver_unregister(&wifi_device_legacy);
++}
++#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */
++
++#ifdef CONFIG_GPIO_WAKEUP
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++int wifi_configure_gpio(void)
++{
++	if (gpio_request(oob_gpio, "oob_irq")) {
++		RTW_INFO("## %s Cannot request GPIO\n", __FUNCTION__);
++		return -1;
++	}
++	gpio_export(oob_gpio, 0);
++	if (gpio_direction_input(oob_gpio)) {
++		RTW_INFO("## %s Cannot set GPIO direction input\n", __FUNCTION__);
++		return -1;
++	}
++	oob_irq = gpio_to_irq(oob_gpio);
++	if (oob_irq < 0) {
++		RTW_INFO("## %s Cannot convert GPIO to IRQ\n", __FUNCTION__);
++		return -1;
++	}
++
++	RTW_INFO("## %s OOB_IRQ=%d\n", __FUNCTION__, oob_irq);
++
++	return 0;
++}
++#endif /* CONFIG_PLATFORM_INTEL_BYT */
++void wifi_free_gpio(unsigned int gpio)
++{
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++	if (gpio)
++		gpio_free(gpio);
++#endif /* CONFIG_PLATFORM_INTEL_BYT */
++}
++#endif /* CONFIG_GPIO_WAKEUP */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_cfgvendor.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_cfgvendor.c
+new file mode 100644
+index 000000000..8781d2318
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_cfgvendor.c
+@@ -0,0 +1,2117 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <drv_types.h>
++
++#ifdef CONFIG_IOCTL_CFG80211
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT)
++
++/*
++#include <linux/kernel.h>
++#include <linux/if_arp.h>
++#include <asm/uaccess.h>
++
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/netdevice.h>
++#include <linux/sched.h>
++#include <linux/etherdevice.h>
++#include <linux/wireless.h>
++#include <linux/ieee80211.h>
++#include <linux/wait.h>
++#include <net/cfg80211.h>
++*/
++
++#include <net/rtnetlink.h>
++
++#ifndef MIN
++#define MIN(x,y) (((x) < (y)) ? (x) : (y))
++#endif
++
++#ifdef DBG_MEM_ALLOC
++extern bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size);
++struct sk_buff *dbg_rtw_cfg80211_vendor_event_alloc(struct wiphy *wiphy, struct wireless_dev *wdev, int len, int event_id, gfp_t gfp
++		, const enum mstat_f flags, const char *func, const int line)
++{
++	struct sk_buff *skb;
++	unsigned int truesize = 0;
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0))
++	skb = cfg80211_vendor_event_alloc(wiphy, len, event_id, gfp);
++#else
++	skb = cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp);
++#endif
++
++	if (skb)
++		truesize = skb->truesize;
++
++	if (!skb || truesize < len || match_mstat_sniff_rules(flags, truesize))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\n", func, line, __FUNCTION__, len, skb, truesize);
++
++	rtw_mstat_update(
++		flags
++		, skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++		, truesize
++	);
++
++	return skb;
++}
++
++void dbg_rtw_cfg80211_vendor_event(struct sk_buff *skb, gfp_t gfp
++		   , const enum mstat_f flags, const char *func, const int line)
++{
++	unsigned int truesize = skb->truesize;
++
++	if (match_mstat_sniff_rules(flags, truesize))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
++
++	cfg80211_vendor_event(skb, gfp);
++
++	rtw_mstat_update(
++		flags
++		, MSTAT_FREE
++		, truesize
++	);
++}
++
++struct sk_buff *dbg_rtw_cfg80211_vendor_cmd_alloc_reply_skb(struct wiphy *wiphy, int len
++		, const enum mstat_f flags, const char *func, const int line)
++{
++	struct sk_buff *skb;
++	unsigned int truesize = 0;
++
++	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len);
++
++	if (skb)
++		truesize = skb->truesize;
++
++	if (!skb || truesize < len || match_mstat_sniff_rules(flags, truesize))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\n", func, line, __FUNCTION__, len, skb, truesize);
++
++	rtw_mstat_update(
++		flags
++		, skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++		, truesize
++	);
++
++	return skb;
++}
++
++int dbg_rtw_cfg80211_vendor_cmd_reply(struct sk_buff *skb
++	      , const enum mstat_f flags, const char *func, const int line)
++{
++	unsigned int truesize = skb->truesize;
++	int ret;
++
++	if (match_mstat_sniff_rules(flags, truesize))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
++
++	ret = cfg80211_vendor_cmd_reply(skb);
++
++	rtw_mstat_update(
++		flags
++		, MSTAT_FREE
++		, truesize
++	);
++
++	return ret;
++}
++
++#define rtw_cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp) \
++	dbg_rtw_cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++
++#define rtw_cfg80211_vendor_event(skb, gfp) \
++	dbg_rtw_cfg80211_vendor_event(skb, gfp, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++
++#define rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len) \
++	dbg_rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++
++#define rtw_cfg80211_vendor_cmd_reply(skb) \
++	dbg_rtw_cfg80211_vendor_cmd_reply(skb, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
++#else
++
++struct sk_buff *rtw_cfg80211_vendor_event_alloc(
++	struct wiphy *wiphy, struct wireless_dev *wdev, int len, int event_id, gfp_t gfp)
++{
++	struct sk_buff *skb;
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0))
++	skb = cfg80211_vendor_event_alloc(wiphy, len, event_id, gfp);
++#else
++	skb = cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp);
++#endif
++	return skb;
++}
++
++#define rtw_cfg80211_vendor_event(skb, gfp) \
++	cfg80211_vendor_event(skb, gfp)
++
++#define rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len) \
++	cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len)
++
++#define rtw_cfg80211_vendor_cmd_reply(skb) \
++	cfg80211_vendor_cmd_reply(skb)
++#endif /* DBG_MEM_ALLOC */
++
++/*
++ * This API is to be used for asynchronous vendor events. This
++ * shouldn't be used in response to a vendor command from its
++ * do_it handler context (instead rtw_cfgvendor_send_cmd_reply should
++ * be used).
++ */
++int rtw_cfgvendor_send_async_event(struct wiphy *wiphy,
++	   struct net_device *dev, int event_id, const void  *data, int len)
++{
++	u16 kflags;
++	struct sk_buff *skb;
++
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++
++	/* Alloc the SKB for vendor_event */
++	skb = rtw_cfg80211_vendor_event_alloc(wiphy, ndev_to_wdev(dev), len, event_id, kflags);
++	if (!skb) {
++		RTW_ERR(FUNC_NDEV_FMT" skb alloc failed", FUNC_NDEV_ARG(dev));
++		return -ENOMEM;
++	}
++
++	/* Push the data to the skb */
++	nla_put_nohdr(skb, len, data);
++
++	rtw_cfg80211_vendor_event(skb, kflags);
++
++	return 0;
++}
++
++static int rtw_cfgvendor_send_cmd_reply(struct wiphy *wiphy,
++			struct net_device *dev, const void  *data, int len)
++{
++	struct sk_buff *skb;
++
++	/* Alloc the SKB for vendor_event */
++	skb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len);
++	if (unlikely(!skb)) {
++		RTW_ERR(FUNC_NDEV_FMT" skb alloc failed", FUNC_NDEV_ARG(dev));
++		return -ENOMEM;
++	}
++
++	/* Push the data to the skb */
++	nla_put_nohdr(skb, len, data);
++
++	return rtw_cfg80211_vendor_cmd_reply(skb);
++}
++
++/* Feature enums */
++#define WIFI_FEATURE_INFRA              0x0001      // Basic infrastructure mode
++#define WIFI_FEATURE_INFRA_5G           0x0002      // Support for 5 GHz Band
++#define WIFI_FEATURE_HOTSPOT            0x0004      // Support for GAS/ANQP
++#define WIFI_FEATURE_P2P                0x0008      // Wifi-Direct
++#define WIFI_FEATURE_SOFT_AP            0x0010      // Soft AP
++#define WIFI_FEATURE_GSCAN              0x0020      // Google-Scan APIs
++#define WIFI_FEATURE_NAN                0x0040      // Neighbor Awareness Networking
++#define WIFI_FEATURE_D2D_RTT            0x0080      // Device-to-device RTT
++#define WIFI_FEATURE_D2AP_RTT           0x0100      // Device-to-AP RTT
++#define WIFI_FEATURE_BATCH_SCAN         0x0200      // Batched Scan (legacy)
++#define WIFI_FEATURE_PNO                0x0400      // Preferred network offload
++#define WIFI_FEATURE_ADDITIONAL_STA     0x0800      // Support for two STAs
++#define WIFI_FEATURE_TDLS               0x1000      // Tunnel directed link setup
++#define WIFI_FEATURE_TDLS_OFFCHANNEL    0x2000      // Support for TDLS off channel
++#define WIFI_FEATURE_EPR                0x4000      // Enhanced power reporting
++#define WIFI_FEATURE_AP_STA             0x8000      // Support for AP STA Concurrency
++#define WIFI_FEATURE_LINK_LAYER_STATS   0x10000     // Link layer stats collection
++#define WIFI_FEATURE_LOGGER             0x20000     // WiFi Logger
++#define WIFI_FEATURE_HAL_EPNO           0x40000     // WiFi PNO enhanced
++#define WIFI_FEATURE_RSSI_MONITOR       0x80000     // RSSI Monitor
++#define WIFI_FEATURE_MKEEP_ALIVE        0x100000    // WiFi mkeep_alive
++#define WIFI_FEATURE_CONFIG_NDO         0x200000    // ND offload configure
++#define WIFI_FEATURE_TX_TRANSMIT_POWER  0x400000    // Capture Tx transmit power levels
++#define WIFI_FEATURE_CONTROL_ROAMING    0x800000    // Enable/Disable firmware roaming
++#define WIFI_FEATURE_IE_WHITELIST       0x1000000   // Support Probe IE white listing
++#define WIFI_FEATURE_SCAN_RAND          0x2000000   // Support MAC & Probe Sequence Number randomization
++#define WIFI_FEATURE_TX_POWER_LIMIT     0x4000000   // Set Tx power limit
++#define WIFI_FEATURE_WPA3_SAE		0x8000000   // WPA3-Personal SAE
++#define WIFI_FEATURE_WPA3_SUITE_B	0x10000000  // WPA3-Enterprise Suite-B
++#define WIFI_FEATURE_OWE		0x20000000  // Enhanced Open
++#define WIFI_FEATURE_LOW_LATENCY	0x40000000  // Low Latency modes
++#define WIFI_FEATURE_DPP		0x80000000  // DPP (Easy-Connect)
++#define WIFI_FEATURE_P2P_RAND_MAC	0x100000000L// Random P2P MAC
++// Add more features here
++
++#define MAX_FEATURE_SET_CONCURRRENT_GROUPS  3
++
++#include <hal_data.h>
++int rtw_dev_get_feature_set(struct net_device *dev)
++{
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
++	int feature_set = 0;
++
++	feature_set |= WIFI_FEATURE_INFRA;
++
++#if CONFIG_IEEE80211_BAND_5GHZ
++	if (is_supported_5g(adapter_to_regsty(adapter)->wireless_mode))
++		feature_set |= WIFI_FEATURE_INFRA_5G;
++#endif
++
++	feature_set |= WIFI_FEATURE_P2P;
++	feature_set |= WIFI_FEATURE_SOFT_AP;
++
++	feature_set |= WIFI_FEATURE_ADDITIONAL_STA;
++#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
++	feature_set |= WIFI_FEATURE_LINK_LAYER_STATS;
++#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
++
++#ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
++        feature_set |= WIFI_FEATURE_RSSI_MONITOR;
++#endif
++
++#ifdef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER
++	feature_set |= WIFI_FEATURE_LOGGER;
++#endif
++
++#ifdef CONFIG_RTW_WIFI_HAL
++	feature_set |= WIFI_FEATURE_CONFIG_NDO;
++	feature_set |= WIFI_FEATURE_SCAN_RAND;
++#endif
++
++
++	feature_set |= WIFI_FEATURE_WPA3_SAE;
++	feature_set |= WIFI_FEATURE_OWE;
++	feature_set |= WIFI_FEATURE_DPP;
++
++#ifdef CONFIG_WPA3_SUITE_B
++	feature_set |= WIFI_FEATURE_WPA3_SUITE_B;
++#endif
++
++	return feature_set;
++}
++
++int *rtw_dev_get_feature_set_matrix(struct net_device *dev, int *num)
++{
++	int feature_set_full, mem_needed;
++	int *ret;
++
++	*num = 0;
++	mem_needed = sizeof(int) * MAX_FEATURE_SET_CONCURRRENT_GROUPS;
++	ret = (int *)rtw_malloc(mem_needed);
++
++	if (!ret) {
++		RTW_ERR(FUNC_NDEV_FMT" failed to allocate %d bytes\n"
++			, FUNC_NDEV_ARG(dev), mem_needed);
++		return ret;
++	}
++
++	feature_set_full = rtw_dev_get_feature_set(dev);
++
++	ret[0] = (feature_set_full & WIFI_FEATURE_INFRA) |
++		 (feature_set_full & WIFI_FEATURE_INFRA_5G) |
++		 (feature_set_full & WIFI_FEATURE_NAN) |
++		 (feature_set_full & WIFI_FEATURE_D2D_RTT) |
++		 (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
++		 (feature_set_full & WIFI_FEATURE_PNO) |
++		 (feature_set_full & WIFI_FEATURE_BATCH_SCAN) |
++		 (feature_set_full & WIFI_FEATURE_GSCAN) |
++		 (feature_set_full & WIFI_FEATURE_HOTSPOT) |
++		 (feature_set_full & WIFI_FEATURE_ADDITIONAL_STA) |
++		 (feature_set_full & WIFI_FEATURE_EPR);
++
++	ret[1] = (feature_set_full & WIFI_FEATURE_INFRA) |
++		 (feature_set_full & WIFI_FEATURE_INFRA_5G) |
++		 /* Not yet verified NAN with P2P */
++		 /* (feature_set_full & WIFI_FEATURE_NAN) | */
++		 (feature_set_full & WIFI_FEATURE_P2P) |
++		 (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
++		 (feature_set_full & WIFI_FEATURE_D2D_RTT) |
++		 (feature_set_full & WIFI_FEATURE_EPR);
++
++	ret[2] = (feature_set_full & WIFI_FEATURE_INFRA) |
++		 (feature_set_full & WIFI_FEATURE_INFRA_5G) |
++		 (feature_set_full & WIFI_FEATURE_NAN) |
++		 (feature_set_full & WIFI_FEATURE_D2D_RTT) |
++		 (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
++		 (feature_set_full & WIFI_FEATURE_TDLS) |
++		 (feature_set_full & WIFI_FEATURE_TDLS_OFFCHANNEL) |
++		 (feature_set_full & WIFI_FEATURE_EPR);
++	*num = MAX_FEATURE_SET_CONCURRRENT_GROUPS;
++
++	return ret;
++}
++
++static int rtw_cfgvendor_get_feature_set(struct wiphy *wiphy,
++		struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	int reply;
++
++	reply = rtw_dev_get_feature_set(wdev_to_ndev(wdev));
++
++	err =  rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), &reply, sizeof(int));
++
++	if (unlikely(err))
++		RTW_ERR(FUNC_NDEV_FMT" Vendor Command reply failed ret:%d\n"
++			, FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err);
++
++	return err;
++}
++
++static int rtw_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy,
++		struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct sk_buff *skb;
++	int *reply;
++	int num, mem_needed, i;
++
++	reply = rtw_dev_get_feature_set_matrix(wdev_to_ndev(wdev), &num);
++
++	if (!reply) {
++		RTW_ERR(FUNC_NDEV_FMT" Could not get feature list matrix\n"
++			, FUNC_NDEV_ARG(wdev_to_ndev(wdev)));
++		err = -EINVAL;
++		return err;
++	}
++
++	mem_needed = VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * num) +
++		     ATTRIBUTE_U32_LEN;
++
++	/* Alloc the SKB for vendor_event */
++	skb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		RTW_ERR(FUNC_NDEV_FMT" skb alloc failed", FUNC_NDEV_ARG(wdev_to_ndev(wdev)));
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET, num);
++	for (i = 0; i < num; i++)
++		nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_FEATURE_SET, reply[i]);
++
++	err =  rtw_cfg80211_vendor_cmd_reply(skb);
++
++	if (unlikely(err))
++		RTW_ERR(FUNC_NDEV_FMT" Vendor Command reply failed ret:%d\n"
++			, FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err);
++exit:
++	rtw_mfree((u8 *)reply, sizeof(int) * num);
++	return err;
++}
++
++#if defined(GSCAN_SUPPORT) && 0
++int rtw_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
++	struct net_device *dev, void  *data, int len, rtw_vendor_event_t event)
++{
++	u16 kflags;
++	const void *ptr;
++	struct sk_buff *skb;
++	int malloc_len, total, iter_cnt_to_send, cnt;
++	gscan_results_cache_t *cache = (gscan_results_cache_t *)data;
++
++	total = len / sizeof(wifi_gscan_result_t);
++	while (total > 0) {
++		malloc_len = (total * sizeof(wifi_gscan_result_t)) + VENDOR_DATA_OVERHEAD;
++		if (malloc_len > NLMSG_DEFAULT_SIZE)
++			malloc_len = NLMSG_DEFAULT_SIZE;
++		iter_cnt_to_send =
++			(malloc_len - VENDOR_DATA_OVERHEAD) / sizeof(wifi_gscan_result_t);
++		total = total - iter_cnt_to_send;
++
++		kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++
++		/* Alloc the SKB for vendor_event */
++		skb = rtw_cfg80211_vendor_event_alloc(wiphy, ndev_to_wdev(dev), malloc_len, event, kflags);
++		if (!skb) {
++			WL_ERR(("skb alloc failed"));
++			return -ENOMEM;
++		}
++
++		while (cache && iter_cnt_to_send) {
++			ptr = (const void *) &cache->results[cache->tot_consumed];
++
++			if (iter_cnt_to_send < (cache->tot_count - cache->tot_consumed))
++				cnt = iter_cnt_to_send;
++			else
++				cnt = (cache->tot_count - cache->tot_consumed);
++
++			iter_cnt_to_send -= cnt;
++			cache->tot_consumed += cnt;
++			/* Push the data to the skb */
++			nla_append(skb, cnt * sizeof(wifi_gscan_result_t), ptr);
++			if (cache->tot_consumed == cache->tot_count)
++				cache = cache->next;
++
++		}
++
++		rtw_cfg80211_vendor_event(skb, kflags);
++	}
++
++	return 0;
++}
++
++
++static int rtw_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy,
++		struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pno_gscan_capabilities_t *reply = NULL;
++	uint32 reply_len = 0;
++
++
++	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++			      DHD_PNO_GET_CAPABILITIES, NULL, &reply_len);
++	if (!reply) {
++		WL_ERR(("Could not get capabilities\n"));
++		err = -EINVAL;
++		return err;
++	}
++
++	err =  rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++					    reply, reply_len);
++
++	if (unlikely(err))
++		WL_ERR(("Vendor Command reply failed ret:%d\n", err));
++
++	kfree(reply);
++	return err;
++}
++
++static int rtw_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy,
++		struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0, type, band;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	uint16 *reply = NULL;
++	uint32 reply_len = 0, num_channels, mem_needed;
++	struct sk_buff *skb;
++
++	type = nla_type(data);
++
++	if (type == GSCAN_ATTRIBUTE_BAND)
++		band = nla_get_u32(data);
++	else
++		return -1;
++
++	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++			      DHD_PNO_GET_CHANNEL_LIST, &band, &reply_len);
++
++	if (!reply) {
++		WL_ERR(("Could not get channel list\n"));
++		err = -EINVAL;
++		return err;
++	}
++	num_channels =  reply_len / sizeof(uint32);
++	mem_needed = reply_len + VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * 2);
++
++	/* Alloc the SKB for vendor_event */
++	skb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		WL_ERR(("skb alloc failed"));
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_CHANNELS, num_channels);
++	nla_put(skb, GSCAN_ATTRIBUTE_CHANNEL_LIST, reply_len, reply);
++
++	err =  rtw_cfg80211_vendor_cmd_reply(skb);
++
++	if (unlikely(err))
++		WL_ERR(("Vendor Command reply failed ret:%d\n", err));
++exit:
++	kfree(reply);
++	return err;
++}
++
++static int rtw_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy,
++		struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_results_cache_t *results, *iter;
++	uint32 reply_len, complete = 0, num_results_iter;
++	int32 mem_needed;
++	wifi_gscan_result_t *ptr;
++	uint16 num_scan_ids, num_results;
++	struct sk_buff *skb;
++	struct nlattr *scan_hdr;
++
++	dhd_dev_wait_batch_results_complete(bcmcfg_to_prmry_ndev(cfg));
++	dhd_dev_pno_lock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++	results = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++				DHD_PNO_GET_BATCH_RESULTS, NULL, &reply_len);
++
++	if (!results) {
++		WL_ERR(("No results to send %d\n", err));
++		err =  rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++						    results, 0);
++
++		if (unlikely(err))
++			WL_ERR(("Vendor Command reply failed ret:%d\n", err));
++		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++		return err;
++	}
++	num_scan_ids = reply_len & 0xFFFF;
++	num_results = (reply_len & 0xFFFF0000) >> 16;
++	mem_needed = (num_results * sizeof(wifi_gscan_result_t)) +
++		     (num_scan_ids * GSCAN_BATCH_RESULT_HDR_LEN) +
++		     VENDOR_REPLY_OVERHEAD + SCAN_RESULTS_COMPLETE_FLAG_LEN;
++
++	if (mem_needed > (int32)NLMSG_DEFAULT_SIZE) {
++		mem_needed = (int32)NLMSG_DEFAULT_SIZE;
++		complete = 0;
++	} else
++		complete = 1;
++
++	WL_TRACE(("complete %d mem_needed %d max_mem %d\n", complete, mem_needed,
++		  (int)NLMSG_DEFAULT_SIZE));
++	/* Alloc the SKB for vendor_event */
++	skb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		WL_ERR(("skb alloc failed"));
++		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++		return -ENOMEM;
++	}
++	iter = results;
++
++	nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE, complete);
++
++	mem_needed = mem_needed - (SCAN_RESULTS_COMPLETE_FLAG_LEN + VENDOR_REPLY_OVERHEAD);
++
++	while (iter && ((mem_needed - GSCAN_BATCH_RESULT_HDR_LEN)  > 0)) {
++		scan_hdr = nla_nest_start(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS);
++		nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_ID, iter->scan_id);
++		nla_put_u8(skb, GSCAN_ATTRIBUTE_SCAN_FLAGS, iter->flag);
++		num_results_iter =
++			(mem_needed - GSCAN_BATCH_RESULT_HDR_LEN) / sizeof(wifi_gscan_result_t);
++
++		if ((iter->tot_count - iter->tot_consumed) < num_results_iter)
++			num_results_iter = iter->tot_count - iter->tot_consumed;
++
++		nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_OF_RESULTS, num_results_iter);
++		if (num_results_iter) {
++			ptr = &iter->results[iter->tot_consumed];
++			iter->tot_consumed += num_results_iter;
++			nla_put(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS,
++				num_results_iter * sizeof(wifi_gscan_result_t), ptr);
++		}
++		nla_nest_end(skb, scan_hdr);
++		mem_needed -= GSCAN_BATCH_RESULT_HDR_LEN +
++			      (num_results_iter * sizeof(wifi_gscan_result_t));
++		iter = iter->next;
++	}
++
++	dhd_dev_gscan_batch_cache_cleanup(bcmcfg_to_prmry_ndev(cfg));
++	dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++
++	return rtw_cfg80211_vendor_cmd_reply(skb);
++}
++
++static int rtw_cfgvendor_initiate_gscan(struct wiphy *wiphy,
++		       struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type, tmp = len;
++	int run = 0xFF;
++	int flush = 0;
++	const struct nlattr *iter;
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++		if (type == GSCAN_ATTRIBUTE_ENABLE_FEATURE)
++			run = nla_get_u32(iter);
++		else if (type == GSCAN_ATTRIBUTE_FLUSH_FEATURE)
++			flush = nla_get_u32(iter);
++	}
++
++	if (run != 0xFF) {
++		err = dhd_dev_pno_run_gscan(bcmcfg_to_prmry_ndev(cfg), run, flush);
++
++		if (unlikely(err))
++			WL_ERR(("Could not run gscan:%d\n", err));
++		return err;
++	} else
++		return -1;
++
++
++}
++
++static int rtw_cfgvendor_enable_full_scan_result(struct wiphy *wiphy,
++		struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type;
++	bool real_time = FALSE;
++
++	type = nla_type(data);
++
++	if (type == GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS) {
++		real_time = nla_get_u32(data);
++
++		err = dhd_dev_pno_enable_full_scan_result(bcmcfg_to_prmry_ndev(cfg), real_time);
++
++		if (unlikely(err))
++			WL_ERR(("Could not run gscan:%d\n", err));
++
++	} else
++		err = -1;
++
++	return err;
++}
++
++static int rtw_cfgvendor_set_scan_cfg(struct wiphy *wiphy,
++		     struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_scan_params_t *scan_param;
++	int j = 0;
++	int type, tmp, tmp1, tmp2, k = 0;
++	const struct nlattr *iter, *iter1, *iter2;
++	struct dhd_pno_gscan_channel_bucket  *ch_bucket;
++
++	scan_param = kzalloc(sizeof(gscan_scan_params_t), GFP_KERNEL);
++	if (!scan_param) {
++		WL_ERR(("Could not set GSCAN scan cfg, mem alloc failure\n"));
++		err = -EINVAL;
++		return err;
++
++	}
++
++	scan_param->scan_fr = PNO_SCAN_MIN_FW_SEC;
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++
++		if (j >= GSCAN_MAX_CH_BUCKETS)
++			break;
++
++		switch (type) {
++		case GSCAN_ATTRIBUTE_BASE_PERIOD:
++			scan_param->scan_fr = nla_get_u32(iter) / 1000;
++			break;
++		case GSCAN_ATTRIBUTE_NUM_BUCKETS:
++			scan_param->nchannel_buckets = nla_get_u32(iter);
++			break;
++		case GSCAN_ATTRIBUTE_CH_BUCKET_1:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_2:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_3:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_4:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_5:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_6:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_7:
++			nla_for_each_nested(iter1, iter, tmp1) {
++				type = nla_type(iter1);
++				ch_bucket =
++					scan_param->channel_bucket;
++
++				switch (type) {
++				case GSCAN_ATTRIBUTE_BUCKET_ID:
++					break;
++				case GSCAN_ATTRIBUTE_BUCKET_PERIOD:
++					ch_bucket[j].bucket_freq_multiple =
++						nla_get_u32(iter1) / 1000;
++					break;
++				case GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS:
++					ch_bucket[j].num_channels =
++						nla_get_u32(iter1);
++					break;
++				case GSCAN_ATTRIBUTE_BUCKET_CHANNELS:
++					nla_for_each_nested(iter2, iter1, tmp2) {
++						if (k >= PFN_SWC_RSSI_WINDOW_MAX)
++							break;
++						ch_bucket[j].chan_list[k] =
++							nla_get_u32(iter2);
++						k++;
++					}
++					k = 0;
++					break;
++				case GSCAN_ATTRIBUTE_BUCKETS_BAND:
++					ch_bucket[j].band = (uint16)
++							    nla_get_u32(iter1);
++					break;
++				case GSCAN_ATTRIBUTE_REPORT_EVENTS:
++					ch_bucket[j].report_flag = (uint8)
++							   nla_get_u32(iter1);
++					break;
++				}
++			}
++			j++;
++			break;
++		}
++	}
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_SCAN_CFG_ID, scan_param, 0) < 0) {
++		WL_ERR(("Could not set GSCAN scan cfg\n"));
++		err = -EINVAL;
++	}
++
++	kfree(scan_param);
++	return err;
++
++}
++
++static int rtw_cfgvendor_hotlist_cfg(struct wiphy *wiphy,
++		    struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_hotlist_scan_params_t *hotlist_params;
++	int tmp, tmp1, tmp2, type, j = 0, dummy;
++	const struct nlattr *outer, *inner, *iter;
++	uint8 flush = 0;
++	struct bssid_t *pbssid;
++
++	hotlist_params = (gscan_hotlist_scan_params_t *)kzalloc(len, GFP_KERNEL);
++	if (!hotlist_params) {
++		WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes\n", len));
++		return -1;
++	}
++
++	hotlist_params->lost_ap_window = GSCAN_LOST_AP_WINDOW_DEFAULT;
++
++	nla_for_each_attr(iter, data, len, tmp2) {
++		type = nla_type(iter);
++		switch (type) {
++		case GSCAN_ATTRIBUTE_HOTLIST_BSSIDS:
++			pbssid = hotlist_params->bssid;
++			nla_for_each_nested(outer, iter, tmp) {
++				nla_for_each_nested(inner, outer, tmp1) {
++					type = nla_type(inner);
++
++					switch (type) {
++					case GSCAN_ATTRIBUTE_BSSID:
++						memcpy(&(pbssid[j].macaddr),
++						       nla_data(inner), ETHER_ADDR_LEN);
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_LOW:
++						pbssid[j].rssi_reporting_threshold =
++							(int8) nla_get_u8(inner);
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_HIGH:
++						dummy = (int8) nla_get_u8(inner);
++						break;
++					}
++				}
++				j++;
++			}
++			hotlist_params->nbssid = j;
++			break;
++		case GSCAN_ATTRIBUTE_HOTLIST_FLUSH:
++			flush = nla_get_u8(iter);
++			break;
++		case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
++			hotlist_params->lost_ap_window = nla_get_u32(iter);
++			break;
++		}
++
++	}
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++		DHD_PNO_GEOFENCE_SCAN_CFG_ID, hotlist_params, flush) < 0) {
++		WL_ERR(("Could not set GSCAN HOTLIST cfg\n"));
++		err = -EINVAL;
++		goto exit;
++	}
++exit:
++	kfree(hotlist_params);
++	return err;
++}
++static int rtw_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy,
++		struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0, tmp, type;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_batch_params_t batch_param;
++	const struct nlattr *iter;
++
++	batch_param.mscan = batch_param.bestn = 0;
++	batch_param.buffer_threshold = GSCAN_BATCH_NO_THR_SET;
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++
++		switch (type) {
++		case GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN:
++			batch_param.bestn = nla_get_u32(iter);
++			break;
++		case GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE:
++			batch_param.mscan = nla_get_u32(iter);
++			break;
++		case GSCAN_ATTRIBUTE_REPORT_THRESHOLD:
++			batch_param.buffer_threshold = nla_get_u32(iter);
++			break;
++		}
++	}
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++			      DHD_PNO_BATCH_SCAN_CFG_ID, &batch_param, 0) < 0) {
++		WL_ERR(("Could not set batch cfg\n"));
++		err = -EINVAL;
++		return err;
++	}
++
++	return err;
++}
++
++static int rtw_cfgvendor_significant_change_cfg(struct wiphy *wiphy,
++		struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_swc_params_t *significant_params;
++	int tmp, tmp1, tmp2, type, j = 0;
++	const struct nlattr *outer, *inner, *iter;
++	uint8 flush = 0;
++	wl_pfn_significant_bssid_t *pbssid;
++
++	significant_params = (gscan_swc_params_t *) kzalloc(len, GFP_KERNEL);
++	if (!significant_params) {
++		WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes\n", len));
++		return -1;
++	}
++
++
++	nla_for_each_attr(iter, data, len, tmp2) {
++		type = nla_type(iter);
++
++		switch (type) {
++		case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH:
++			flush = nla_get_u8(iter);
++			break;
++		case GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE:
++			significant_params->rssi_window = nla_get_u16(iter);
++			break;
++		case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
++			significant_params->lost_ap_window = nla_get_u16(iter);
++			break;
++		case GSCAN_ATTRIBUTE_MIN_BREACHING:
++			significant_params->swc_threshold = nla_get_u16(iter);
++			break;
++		case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS:
++			pbssid = significant_params->bssid_elem_list;
++			nla_for_each_nested(outer, iter, tmp) {
++				nla_for_each_nested(inner, outer, tmp1) {
++					switch (nla_type(inner)) {
++					case GSCAN_ATTRIBUTE_BSSID:
++						memcpy(&(pbssid[j].macaddr),
++						       nla_data(inner),
++						       ETHER_ADDR_LEN);
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_HIGH:
++						pbssid[j].rssi_high_threshold =
++							(int8) nla_get_u8(inner);
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_LOW:
++						pbssid[j].rssi_low_threshold =
++							(int8) nla_get_u8(inner);
++						break;
++					}
++				}
++				j++;
++			}
++			break;
++		}
++	}
++	significant_params->nbssid = j;
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++		DHD_PNO_SIGNIFICANT_SCAN_CFG_ID, significant_params, flush) < 0) {
++		WL_ERR(("Could not set GSCAN significant cfg\n"));
++		err = -EINVAL;
++		goto exit;
++	}
++exit:
++	kfree(significant_params);
++	return err;
++}
++#endif /* GSCAN_SUPPORT */
++
++#if defined(RTT_SUPPORT) && 0
++void rtw_cfgvendor_rtt_evt(void *ctx, void *rtt_data)
++{
++	struct wireless_dev *wdev = (struct wireless_dev *)ctx;
++	struct wiphy *wiphy;
++	struct sk_buff *skb;
++	uint32 tot_len = NLMSG_DEFAULT_SIZE, entry_len = 0;
++	gfp_t kflags;
++	rtt_report_t *rtt_report = NULL;
++	rtt_result_t *rtt_result = NULL;
++	struct list_head *rtt_list;
++	wiphy = wdev->wiphy;
++
++	WL_DBG(("In\n"));
++	/* Push the data to the skb */
++	if (!rtt_data) {
++		WL_ERR(("rtt_data is NULL\n"));
++		goto exit;
++	}
++	rtt_list = (struct list_head *)rtt_data;
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	/* Alloc the SKB for vendor_event */
++	skb = rtw_cfg80211_vendor_event_alloc(wiphy, wdev, tot_len, GOOGLE_RTT_COMPLETE_EVENT, kflags);
++	if (!skb) {
++		WL_ERR(("skb alloc failed"));
++		goto exit;
++	}
++	/* fill in the rtt results on each entry */
++	list_for_each_entry(rtt_result, rtt_list, list) {
++		entry_len = 0;
++		if (rtt_result->TOF_type == TOF_TYPE_ONE_WAY) {
++			entry_len = sizeof(rtt_report_t);
++			rtt_report = kzalloc(entry_len, kflags);
++			if (!rtt_report) {
++				WL_ERR(("rtt_report alloc failed"));
++				goto exit;
++			}
++			rtt_report->addr = rtt_result->peer_mac;
++			rtt_report->num_measurement = 1; /* ONE SHOT */
++			rtt_report->status = rtt_result->err_code;
++			rtt_report->type = (rtt_result->TOF_type == TOF_TYPE_ONE_WAY) ? RTT_ONE_WAY : RTT_TWO_WAY;
++			rtt_report->peer = rtt_result->target_info->peer;
++			rtt_report->channel = rtt_result->target_info->channel;
++			rtt_report->rssi = rtt_result->avg_rssi;
++			/* tx_rate */
++			rtt_report->tx_rate = rtt_result->tx_rate;
++			/* RTT */
++			rtt_report->rtt = rtt_result->meanrtt;
++			rtt_report->rtt_sd = rtt_result->sdrtt;
++			/* convert to centi meter */
++			if (rtt_result->distance != 0xffffffff)
++				rtt_report->distance = (rtt_result->distance >> 2) * 25;
++			else /* invalid distance */
++				rtt_report->distance = -1;
++
++			rtt_report->ts = rtt_result->ts;
++			nla_append(skb, entry_len, rtt_report);
++			kfree(rtt_report);
++		}
++	}
++	rtw_cfg80211_vendor_event(skb, kflags);
++exit:
++	return;
++}
++
++static int rtw_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev *wdev,
++				       const void *data, int len)
++{
++	int err = 0, rem, rem1, rem2, type;
++	rtt_config_params_t rtt_param;
++	rtt_target_info_t *rtt_target = NULL;
++	const struct nlattr *iter, *iter1, *iter2;
++	int8 eabuf[ETHER_ADDR_STR_LEN];
++	int8 chanbuf[CHANSPEC_STR_LEN];
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	WL_DBG(("In\n"));
++	err = dhd_dev_rtt_register_noti_callback(wdev->netdev, wdev, wl_cfgvendor_rtt_evt);
++	if (err < 0) {
++		WL_ERR(("failed to register rtt_noti_callback\n"));
++		goto exit;
++	}
++	memset(&rtt_param, 0, sizeof(rtt_param));
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++		case RTT_ATTRIBUTE_TARGET_CNT:
++			rtt_param.rtt_target_cnt = nla_get_u8(iter);
++			if (rtt_param.rtt_target_cnt > RTT_MAX_TARGET_CNT) {
++				WL_ERR(("exceed max target count : %d\n",
++					rtt_param.rtt_target_cnt));
++				err = BCME_RANGE;
++			}
++			break;
++		case RTT_ATTRIBUTE_TARGET_INFO:
++			rtt_target = rtt_param.target_info;
++			nla_for_each_nested(iter1, iter, rem1) {
++				nla_for_each_nested(iter2, iter1, rem2) {
++					type = nla_type(iter2);
++					switch (type) {
++					case RTT_ATTRIBUTE_TARGET_MAC:
++						memcpy(&rtt_target->addr, nla_data(iter2), ETHER_ADDR_LEN);
++						break;
++					case RTT_ATTRIBUTE_TARGET_TYPE:
++						rtt_target->type = nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_PEER:
++						rtt_target->peer = nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_CHAN:
++						memcpy(&rtt_target->channel, nla_data(iter2),
++						       sizeof(rtt_target->channel));
++						break;
++					case RTT_ATTRIBUTE_TARGET_MODE:
++						rtt_target->continuous = nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_INTERVAL:
++						rtt_target->interval = nla_get_u32(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT:
++						rtt_target->measure_cnt = nla_get_u32(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_PKT:
++						rtt_target->ftm_cnt = nla_get_u32(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_RETRY:
++						rtt_target->retry_cnt = nla_get_u32(iter2);
++					}
++				}
++				/* convert to chanspec value */
++				rtt_target->chanspec = dhd_rtt_convert_to_chspec(rtt_target->channel);
++				if (rtt_target->chanspec == 0) {
++					WL_ERR(("Channel is not valid\n"));
++					goto exit;
++				}
++				WL_INFORM(("Target addr %s, Channel : %s for RTT\n",
++					bcm_ether_ntoa((const struct ether_addr *)&rtt_target->addr, eabuf),
++					wf_chspec_ntoa(rtt_target->chanspec, chanbuf)));
++				rtt_target++;
++			}
++			break;
++		}
++	}
++	WL_DBG(("leave :target_cnt : %d\n", rtt_param.rtt_target_cnt));
++	if (dhd_dev_rtt_set_cfg(bcmcfg_to_prmry_ndev(cfg), &rtt_param) < 0) {
++		WL_ERR(("Could not set RTT configuration\n"));
++		err = -EINVAL;
++	}
++exit:
++	return err;
++}
++
++static int rtw_cfgvendor_rtt_cancel_config(struct wiphy *wiphy, struct wireless_dev *wdev,
++		const void *data, int len)
++{
++	int err = 0, rem, type, target_cnt = 0;
++	const struct nlattr *iter;
++	struct ether_addr *mac_list = NULL, *mac_addr = NULL;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++		case RTT_ATTRIBUTE_TARGET_CNT:
++			target_cnt = nla_get_u8(iter);
++			mac_list = (struct ether_addr *)kzalloc(target_cnt * ETHER_ADDR_LEN , GFP_KERNEL);
++			if (mac_list == NULL) {
++				WL_ERR(("failed to allocate mem for mac list\n"));
++				goto exit;
++			}
++			mac_addr = &mac_list[0];
++			break;
++		case RTT_ATTRIBUTE_TARGET_MAC:
++			if (mac_addr)
++				memcpy(mac_addr++, nla_data(iter), ETHER_ADDR_LEN);
++			else {
++				WL_ERR(("mac_list is NULL\n"));
++				goto exit;
++			}
++			break;
++		}
++		if (dhd_dev_rtt_cancel_cfg(bcmcfg_to_prmry_ndev(cfg), mac_list, target_cnt) < 0) {
++			WL_ERR(("Could not cancel RTT configuration\n"));
++			err = -EINVAL;
++			goto exit;
++		}
++	}
++exit:
++	if (mac_list)
++		kfree(mac_list);
++	return err;
++}
++static int rtw_cfgvendor_rtt_get_capability(struct wiphy *wiphy, struct wireless_dev *wdev,
++		const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	rtt_capabilities_t capability;
++
++	err = dhd_dev_rtt_capability(bcmcfg_to_prmry_ndev(cfg), &capability);
++	if (unlikely(err)) {
++		WL_ERR(("Vendor Command reply failed ret:%d\n", err));
++		goto exit;
++	}
++	err =  rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++					    &capability, sizeof(capability));
++
++	if (unlikely(err))
++		WL_ERR(("Vendor Command reply failed ret:%d\n", err));
++exit:
++	return err;
++}
++
++#endif /* RTT_SUPPORT */
++
++#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
++enum {
++    LSTATS_SUBCMD_GET_INFO = ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START,
++	LSTATS_SUBCMD_SET_INFO,
++	LSTATS_SUBCMD_CLEAR_INFO,
++};
++static void LinkLayerStats(_adapter *padapter)
++{
++	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
++	struct recv_priv		*precvpriv = &(padapter->recvpriv);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
++	u32 ps_time, trx_total_time;
++	u64 tx_bytes, rx_bytes, trx_total_bytes = 0;
++	u64 tmp = 0;
++	
++	RTW_DBG("%s adapter type : %u\n", __func__, padapter->adapter_type);
++
++	tx_bytes = 0;
++	rx_bytes = 0;
++	ps_time = 0;
++	trx_total_time = 0;
++
++	if ( padapter->netif_up == _TRUE ) {
++
++		pwrpriv->on_time = rtw_get_passing_time_ms(pwrpriv->radio_on_start_time);
++
++		if (rtw_mi_check_fwstate(padapter, WIFI_ASOC_STATE)) {
++			if ( pwrpriv->bpower_saving == _TRUE ) {
++				pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);
++				pwrpriv->pwr_saving_start_time = rtw_get_current_time();
++			}
++		} else {		
++#ifdef CONFIG_IPS
++			if ( pwrpriv->bpower_saving == _TRUE ) {
++				pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);
++				pwrpriv->pwr_saving_start_time = rtw_get_current_time();
++			}
++#else
++			pwrpriv->pwr_saving_time = pwrpriv->on_time;
++#endif
++		}
++
++		ps_time = pwrpriv->pwr_saving_time;
++
++		/* Deviation caused by caculation start time */
++		if ( ps_time > pwrpriv->on_time )
++			ps_time = pwrpriv->on_time;
++
++		tx_bytes = pdvobjpriv->traffic_stat.last_tx_bytes;
++		rx_bytes = pdvobjpriv->traffic_stat.last_rx_bytes;		
++		trx_total_bytes = tx_bytes + rx_bytes;
++
++		trx_total_time = pwrpriv->on_time - ps_time;
++
++		if ( trx_total_bytes == 0) {
++			pwrpriv->tx_time = 0;
++			pwrpriv->rx_time = 0;
++		} else {
++
++			/* tx_time = (trx_total_time * tx_total_bytes) / trx_total_bytes; */
++			/* rx_time = (trx_total_time * rx_total_bytes) / trx_total_bytes; */
++
++			tmp = (tx_bytes * trx_total_time);
++			tmp = rtw_division64(tmp, trx_total_bytes);
++			pwrpriv->tx_time = tmp;
++
++			tmp = (rx_bytes * trx_total_time);
++			tmp = rtw_division64(tmp, trx_total_bytes);
++			pwrpriv->rx_time = tmp;		
++
++		}
++	
++	}
++	else {
++			pwrpriv->on_time = 0;
++			pwrpriv->tx_time = 0;
++			pwrpriv->rx_time = 0;	
++	}
++
++#ifdef CONFIG_RTW_WIFI_HAL_DEBUG
++	RTW_INFO("- tx_bytes : %llu rx_bytes : %llu total bytes : %llu\n", tx_bytes, rx_bytes, trx_total_bytes);
++	RTW_INFO("- netif_up = %s, on_time : %u ms\n", padapter->netif_up ? "1":"0", pwrpriv->on_time);
++	RTW_INFO("- pwr_saving_time : %u (%u) ms\n", pwrpriv->pwr_saving_time, ps_time);
++	RTW_INFO("- trx_total_time : %u ms\n", trx_total_time);		
++	RTW_INFO("- tx_time : %u ms\n", pwrpriv->tx_time);
++	RTW_INFO("- rx_time : %u ms\n", pwrpriv->rx_time);	
++#endif /* CONFIG_RTW_WIFI_HAL_DEBUG */
++
++}
++
++#define DUMMY_TIME_STATICS 99
++static int rtw_cfgvendor_lstats_get_info(struct wiphy *wiphy,	
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	wifi_radio_stat_internal *radio;
++	wifi_iface_stat *iface;
++	char *output;
++
++	output = rtw_malloc(sizeof(wifi_radio_stat_internal) + sizeof(wifi_iface_stat));
++	if (output == NULL) {
++		RTW_DBG("Allocate lstats info buffer fail!\n");
++	}
++
++	radio = (wifi_radio_stat_internal *)output;
++
++	radio->num_channels = 0;
++	radio->radio = 1;
++
++	/* to get on_time, tx_time, rx_time */
++	LinkLayerStats(padapter); 
++	
++	radio->on_time = pwrpriv->on_time;
++	radio->tx_time = pwrpriv->tx_time;
++	radio->rx_time = pwrpriv->rx_time;
++	radio->on_time_scan = 0;
++	radio->on_time_nbd = 0;
++	radio->on_time_gscan = 0;
++	radio->on_time_pno_scan = 0;
++	radio->on_time_hs20 = 0;
++	#ifdef CONFIG_RTW_WIFI_HAL_DEBUG
++	RTW_INFO("==== %s ====\n", __func__);
++	RTW_INFO("radio->radio : %d\n", (radio->radio));
++	RTW_INFO("pwrpriv->on_time : %u ms\n", (pwrpriv->on_time));
++	RTW_INFO("pwrpriv->tx_time :  %u ms\n", (pwrpriv->tx_time));
++	RTW_INFO("pwrpriv->rx_time :  %u ms\n", (pwrpriv->rx_time));
++	RTW_INFO("radio->on_time :  %u ms\n", (radio->on_time));
++	RTW_INFO("radio->tx_time :  %u ms\n", (radio->tx_time));
++	RTW_INFO("radio->rx_time :  %u ms\n", (radio->rx_time));
++	#endif /* CONFIG_RTW_WIFI_HAL_DEBUG */
++	
++	RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);
++	err =  rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), 
++		output, sizeof(wifi_iface_stat) + sizeof(wifi_radio_stat_internal));
++	if (unlikely(err))
++		RTW_ERR(FUNC_NDEV_FMT"Vendor Command reply failed ret:%d \n"
++			, FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err);
++	rtw_mfree(output, sizeof(wifi_iface_stat) + sizeof(wifi_radio_stat_internal));
++	return err;
++}
++static int rtw_cfgvendor_lstats_set_info(struct wiphy *wiphy,	
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	RTW_INFO("%s\n", __func__);
++	return err;
++}
++static int rtw_cfgvendor_lstats_clear_info(struct wiphy *wiphy,	
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	RTW_INFO("%s\n", __func__);
++	return err;
++}
++#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
++#ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
++static int rtw_cfgvendor_set_rssi_monitor(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++        _adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
++        struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++
++        struct recv_priv *precvpriv = &padapter->recvpriv;
++	int err = 0, rem, type;
++        const struct nlattr *iter;
++
++        RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++
++		switch (type) {
++        		case RSSI_MONITOR_ATTRIBUTE_MAX_RSSI:
++                                pwdev_priv->rssi_monitor_max = (s8)nla_get_u32(iter);;
++	        		break;
++		        case RSSI_MONITOR_ATTRIBUTE_MIN_RSSI:
++                                pwdev_priv->rssi_monitor_min = (s8)nla_get_u32(iter);
++			        break;
++        		case RSSI_MONITOR_ATTRIBUTE_START:
++                                pwdev_priv->rssi_monitor_enable = (u8)nla_get_u32(iter);
++	        		break;
++		}
++	}
++
++	return err;
++}
++
++void rtw_cfgvendor_rssi_monitor_evt(_adapter *padapter) {
++	struct wireless_dev *wdev =  padapter->rtw_wdev;
++	struct wiphy *wiphy= wdev->wiphy;
++        struct recv_priv *precvpriv = &padapter->recvpriv;
++	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	struct	wlan_network	*pcur_network = &pmlmepriv->cur_network;
++        struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
++	struct sk_buff *skb;
++	u32 tot_len = NLMSG_DEFAULT_SIZE;
++	gfp_t kflags;
++        rssi_monitor_evt data ;
++        s8 rssi = precvpriv->rssi;
++
++        if (pwdev_priv->rssi_monitor_enable == 0 || check_fwstate(pmlmepriv, WIFI_ASOC_STATE) != _TRUE)
++                return;
++
++        if (rssi < pwdev_priv->rssi_monitor_max || rssi > pwdev_priv->rssi_monitor_min)
++                return;
++
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++
++	/* Alloc the SKB for vendor_event */
++	skb = rtw_cfg80211_vendor_event_alloc(wiphy, wdev, tot_len, GOOGLE_RSSI_MONITOR_EVENT, kflags);
++	if (!skb) {
++		goto exit;
++	}
++
++        _rtw_memset(&data, 0, sizeof(data));
++
++        data.version = RSSI_MONITOR_EVT_VERSION;
++        data.cur_rssi = rssi;
++        _rtw_memcpy(data.BSSID, pcur_network->network.MacAddress, sizeof(mac_addr));
++
++        nla_append(skb, sizeof(data), &data);
++
++	rtw_cfg80211_vendor_event(skb, kflags);
++exit:
++	return;
++}
++#endif /* CONFIG_RTW_CFGVENDOR_RSSIMONITR */
++
++#ifdef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER
++static int rtw_cfgvendor_logger_start_logging(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = 0, rem, type;
++	char ring_name[32] = {0};
++	int log_level = 0, flags = 0, time_intval = 0, threshold = 0;
++	const struct nlattr *iter;
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case LOGGER_ATTRIBUTE_RING_NAME:
++				strncpy(ring_name, nla_data(iter),
++					MIN(sizeof(ring_name) -1, nla_len(iter)));
++				break;
++			case LOGGER_ATTRIBUTE_LOG_LEVEL:
++				log_level = nla_get_u32(iter);
++				break;
++			case LOGGER_ATTRIBUTE_RING_FLAGS:
++				flags = nla_get_u32(iter);
++				break;
++			case LOGGER_ATTRIBUTE_LOG_TIME_INTVAL:
++				time_intval = nla_get_u32(iter);
++				break;
++			case LOGGER_ATTRIBUTE_LOG_MIN_DATA_SIZE:
++				threshold = nla_get_u32(iter);
++				break;
++			default:
++				RTW_ERR("Unknown type: %d\n", type);
++				ret = WIFI_ERROR_INVALID_ARGS;
++				goto exit;
++		}
++	}
++
++exit:
++	return ret;
++}
++static int rtw_cfgvendor_logger_get_feature(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void *data, int len)
++{
++	int err = 0;
++	u32 supported_features = 0;
++
++	err =  rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), &supported_features, sizeof(supported_features));
++
++	if (unlikely(err))
++		RTW_ERR(FUNC_NDEV_FMT" Vendor Command reply failed ret:%d\n"
++			, FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err);
++
++	return err;
++}
++static int rtw_cfgvendor_logger_get_version(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void *data, int len)
++{
++	_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
++	HAL_DATA_TYPE *hal = GET_HAL_DATA(padapter);
++	int ret = 0, rem, type;
++	int buf_len = 1024;
++	char *buf_ptr;
++	const struct nlattr *iter;
++	gfp_t kflags;
++
++	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
++	buf_ptr = kzalloc(buf_len, kflags);
++	if (!buf_ptr) {
++		RTW_ERR("failed to allocate the buffer for version n");
++		ret = -ENOMEM;
++		goto exit;
++	}
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case LOGGER_ATTRIBUTE_GET_DRIVER:
++				memcpy(buf_ptr, DRIVERVERSION, strlen(DRIVERVERSION)+1);
++				break;
++			case LOGGER_ATTRIBUTE_GET_FW:
++				sprintf(buf_ptr, "v%d.%d", hal->firmware_version, hal->firmware_sub_version);
++				break;
++			default:
++				RTW_ERR("Unknown type: %d\n", type);
++				ret = -EINVAL;
++				goto exit;
++		}
++	}
++	if (ret < 0) {
++		RTW_ERR("failed to get the version %d\n", ret);
++		goto exit;
++	}
++
++
++	ret =  rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), buf_ptr, strlen(buf_ptr));
++exit:
++	kfree(buf_ptr);
++	return ret;
++}
++
++static int rtw_cfgvendor_logger_get_ring_status(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = 0;
++	int ring_id;
++	char ring_buf_name[] = "RTW_RING_BUFFER";
++
++	struct sk_buff *skb;
++	wifi_ring_buffer_status ring_status;
++
++
++	_rtw_memcpy(ring_status.name, ring_buf_name, strlen(ring_buf_name)+1);
++	ring_status.ring_id = 1;
++	/* Alloc the SKB for vendor_event */
++	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy,
++		sizeof(wifi_ring_buffer_status));
++	if (!skb) {
++		RTW_ERR("skb allocation is failed\n");
++		ret = FAIL;
++		goto exit;
++	}
++
++	nla_put_u32(skb, LOGGER_ATTRIBUTE_RING_NUM, 1);
++	nla_put(skb, LOGGER_ATTRIBUTE_RING_STATUS, sizeof(wifi_ring_buffer_status),
++				&ring_status);
++	ret = cfg80211_vendor_cmd_reply(skb);
++
++	if (ret) {
++		RTW_ERR("Vendor Command reply failed ret:%d \n", ret);
++	}
++exit:
++	return ret;
++}
++
++static int rtw_cfgvendor_logger_get_ring_data(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = 0, rem, type;
++	char ring_name[32] = {0};
++	const struct nlattr *iter;
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case LOGGER_ATTRIBUTE_RING_NAME:
++				strncpy(ring_name, nla_data(iter),
++					MIN(sizeof(ring_name) -1, nla_len(iter)));
++				RTW_INFO(" %s LOGGER_ATTRIBUTE_RING_NAME : %s\n", __func__, ring_name);
++				break;
++			default:
++				RTW_ERR("Unknown type: %d\n", type);
++				return ret;
++		}
++	}
++
++
++	return ret;
++}
++
++static int rtw_cfgvendor_logger_get_firmware_memory_dump(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = WIFI_ERROR_NOT_SUPPORTED;
++
++	return ret;
++}
++
++static int rtw_cfgvendor_logger_start_pkt_fate_monitoring(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = WIFI_SUCCESS;
++
++	return ret;
++}
++
++static int rtw_cfgvendor_logger_get_tx_pkt_fates(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = WIFI_SUCCESS;
++
++	return ret;
++}
++
++static int rtw_cfgvendor_logger_get_rx_pkt_fates(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++	int ret = WIFI_SUCCESS;
++
++	return ret;
++}
++
++#endif /* CONFIG_RTW_CFGVENDOR_WIFI_LOGGER */
++#ifdef CONFIG_RTW_WIFI_HAL
++#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++
++#ifndef ETHER_ISMULTI
++#define ETHER_ISMULTI(ea) (((const u8 *)(ea))[0] & 1)
++#endif
++
++
++static u8 null_addr[ETH_ALEN] = {0};
++static void rtw_hal_random_gen_mac_addr(u8 *mac_addr)
++{
++	do {
++		get_random_bytes(&mac_addr[3], ETH_ALEN-3);
++		if (memcmp(mac_addr, null_addr, ETH_ALEN) != 0)
++			break;
++	} while(1);
++}
++
++void rtw_hal_pno_random_gen_mac_addr(PADAPTER adapter)
++{
++	u8 mac_addr[ETH_ALEN];
++	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
++
++	memcpy(mac_addr, pwdev_priv->pno_mac_addr, ETH_ALEN);
++	if (mac_addr[0] == 0xFF) return;
++	rtw_hal_random_gen_mac_addr(mac_addr);
++	memcpy(pwdev_priv->pno_mac_addr, mac_addr, ETH_ALEN);
++#ifdef CONFIG_RTW_DEBUG
++	print_hex_dump(KERN_DEBUG, "pno_mac_addr: ",
++		       DUMP_PREFIX_OFFSET, 16, 1, pwdev_priv->pno_mac_addr,
++		       ETH_ALEN, 1);
++#endif
++}
++
++void rtw_hal_set_hw_mac_addr(PADAPTER adapter, u8 *mac_addr)
++{
++	rtw_ps_deny(adapter, PS_DENY_IOCTL);
++	LeaveAllPowerSaveModeDirect(adapter);
++
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++	rtw_hal_change_macaddr_mbid(adapter, mac_addr);
++#else
++	rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, mac_addr);
++#endif
++#ifdef CONFIG_RTW_DEBUG
++	rtw_hal_dump_macaddr(RTW_DBGDUMP, adapter);
++#endif
++	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
++}
++
++static int rtw_cfgvendor_set_rand_mac_oui(struct wiphy *wiphy,
++		struct wireless_dev *wdev, const void  *data, int len)
++{
++	int err = 0;
++	PADAPTER adapter;
++	void *devaddr;
++	struct net_device *netdev;
++	int type, mac_len;
++	u8 pno_random_mac_oui[3];
++	u8 mac_addr[ETH_ALEN] = {0};
++	struct pwrctrl_priv *pwrctl;
++	struct rtw_wdev_priv *pwdev_priv;
++
++	type = nla_type(data);
++	mac_len = nla_len(data);
++	if (mac_len != 3) {
++		RTW_ERR("%s oui len error %d != 3\n", __func__, mac_len);
++		return -1;
++	}
++
++	if (type == ANDR_WIFI_ATTRIBUTE_RANDOM_MAC_OUI) {
++		memcpy(pno_random_mac_oui, nla_data(data), 3);
++		print_hex_dump(KERN_DEBUG, "pno_random_mac_oui: ",
++			       DUMP_PREFIX_OFFSET, 16, 1, pno_random_mac_oui,
++			       3, 1);
++
++		if (ETHER_ISMULTI(pno_random_mac_oui)) {
++			pr_err("%s: oui is multicast address\n", __func__);
++			return -1;
++		}
++
++		adapter = wiphy_to_adapter(wiphy);
++		if (adapter == NULL) {
++			pr_err("%s: wiphy_to_adapter == NULL\n", __func__);
++			return -1;
++		}
++
++		pwdev_priv = adapter_wdev_data(adapter);
++
++		memcpy(mac_addr, pno_random_mac_oui, 3);
++		rtw_hal_random_gen_mac_addr(mac_addr);
++		memcpy(pwdev_priv->pno_mac_addr, mac_addr, ETH_ALEN);
++#ifdef CONFIG_RTW_DEBUG
++		print_hex_dump(KERN_DEBUG, "pno_mac_addr: ",
++			       DUMP_PREFIX_OFFSET, 16, 1, pwdev_priv->pno_mac_addr,
++			       ETH_ALEN, 1);
++#endif
++	} else {
++		RTW_ERR("%s oui type error %x != 0x2\n", __func__, type);
++		err = -1;
++	}
++
++
++	return err;
++}
++
++#endif
++
++#ifdef CONFIG_RTW_CFGVENDOR_WIFI_OFFLOAD
++static int rtw_cfgvendor_start_mkeep_alive(struct wiphy *wiphy, struct wireless_dev *wdev,
++	const void *data, int len)
++{
++	int ret = WIFI_SUCCESS;
++
++	RTW_INFO("%s : TODO\n", __func__);
++
++	return ret;
++}
++
++static int rtw_cfgvendor_stop_mkeep_alive(struct wiphy *wiphy, struct wireless_dev *wdev,
++	const void *data, int len)
++{
++	int ret = WIFI_SUCCESS;
++
++	RTW_INFO("%s : TODO\n", __func__);
++
++	return ret;
++}
++#endif
++
++static int rtw_cfgvendor_set_nodfs_flag(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void *data, int len)
++{
++	int err = 0;	
++	int type;
++	u32 nodfs = 0;
++	_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
++
++	RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);
++
++	type = nla_type(data);
++	if (type == ANDR_WIFI_ATTRIBUTE_NODFS_SET) {
++		nodfs = nla_get_u32(data);
++		adapter_to_dvobj(padapter)->nodfs = nodfs;
++	} else {
++		err = -EINVAL;
++	}
++
++	RTW_INFO("%s nodfs=%d, err=%d\n", __func__, nodfs, err);
++	
++	return err;
++}
++
++static int rtw_cfgvendor_set_country(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void  *data, int len)
++{
++#define CNTRY_BUF_SZ	4	/* Country string is 3 bytes + NUL */
++	int err = 0, rem, type;
++	char country_code[CNTRY_BUF_SZ] = {0};
++	const struct nlattr *iter;
++	_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
++
++	RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++			case ANDR_WIFI_ATTRIBUTE_COUNTRY:
++				_rtw_memcpy(country_code, nla_data(iter),
++					MIN(nla_len(iter), CNTRY_BUF_SZ));
++				break;
++			default:
++				RTW_ERR("Unknown type: %d\n", type);
++				return -EINVAL;
++		}
++	}
++
++	RTW_INFO("%s country_code:\"%c%c\" \n", __func__, country_code[0], country_code[1]);
++
++	rtw_set_country(padapter, country_code);
++
++	return err;
++}
++
++static int rtw_cfgvendor_set_nd_offload(struct wiphy *wiphy,
++	struct wireless_dev *wdev, const void *data, int len)
++{
++	int err = 0;	
++	int type;
++	u8 nd_en = 0;
++	_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
++
++	RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);
++
++	type = nla_type(data);
++	if (type == ANDR_WIFI_ATTRIBUTE_ND_OFFLOAD_VALUE) {
++		nd_en = nla_get_u8(data);
++		/* ND has been enabled when wow is enabled */
++	} else {
++		err = -EINVAL;
++	}
++
++	RTW_INFO("%s nd_en=%d, err=%d\n", __func__, nd_en, err);
++	
++	return err;
++}
++#endif /* CONFIG_RTW_WIFI_HAL */
++
++static const struct wiphy_vendor_command rtw_vendor_cmds[] = {
++#if defined(GSCAN_SUPPORT) && 0
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_GET_CAPABILITIES
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_gscan_get_capabilities
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_SET_CONFIG
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_set_scan_cfg
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_set_batch_scan_cfg
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_ENABLE_GSCAN
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_initiate_gscan
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_enable_full_scan_result
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_SET_HOTLIST
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_hotlist_cfg
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_significant_change_cfg
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_gscan_get_batch_results
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_gscan_get_channel_list
++	},
++#endif /* GSCAN_SUPPORT */
++#if defined(RTT_SUPPORT) && 0
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = RTT_SUBCMD_SET_CONFIG
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_rtt_set_config
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = RTT_SUBCMD_CANCEL_CONFIG
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_rtt_cancel_config
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = RTT_SUBCMD_GETCAPABILITY
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_rtt_get_capability
++	},
++#endif /* RTT_SUPPORT */
++#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = LSTATS_SUBCMD_GET_INFO
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_lstats_get_info
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = LSTATS_SUBCMD_SET_INFO
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_lstats_set_info
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = LSTATS_SUBCMD_CLEAR_INFO
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_lstats_clear_info
++	},
++#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
++#ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
++        {
++                {
++                        .vendor_id = OUI_GOOGLE,
++                        .subcmd = WIFI_SUBCMD_SET_RSSI_MONITOR
++                },
++                .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++                .doit = rtw_cfgvendor_set_rssi_monitor
++        },
++#endif /* CONFIG_RTW_CFGVENDOR_RSSIMONITOR */
++#ifdef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = LOGGER_START_LOGGING
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_logger_start_logging
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = LOGGER_GET_FEATURE
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_logger_get_feature
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = LOGGER_GET_VER
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_logger_get_version
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = LOGGER_GET_RING_STATUS
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_logger_get_ring_status
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = LOGGER_GET_RING_DATA
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_logger_get_ring_data
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = LOGGER_TRIGGER_MEM_DUMP
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_logger_get_firmware_memory_dump
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = LOGGER_START_PKT_FATE_MONITORING
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_logger_start_pkt_fate_monitoring
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = LOGGER_GET_TX_PKT_FATES
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_logger_get_tx_pkt_fates
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = LOGGER_GET_RX_PKT_FATES
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_logger_get_rx_pkt_fates
++	},	
++#endif /* CONFIG_RTW_CFGVENDOR_WIFI_LOGGER */
++#ifdef CONFIG_RTW_WIFI_HAL
++#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_SET_PNO_RANDOM_MAC_OUI
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_set_rand_mac_oui
++	},
++#endif
++#ifdef CONFIG_RTW_CFGVENDOR_WIFI_OFFLOAD
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_OFFLOAD_SUBCMD_START_MKEEP_ALIVE
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_start_mkeep_alive
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_OFFLOAD_SUBCMD_STOP_MKEEP_ALIVE
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_stop_mkeep_alive
++	},
++#endif
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_NODFS_SET
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_set_nodfs_flag
++
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_SET_COUNTRY_CODE
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_set_country
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_CONFIG_ND_OFFLOAD
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_set_nd_offload
++	},
++#endif /* CONFIG_RTW_WIFI_HAL */
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_GET_FEATURE_SET
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_get_feature_set
++	},
++	{
++		{
++			.vendor_id = OUI_GOOGLE,
++			.subcmd = WIFI_SUBCMD_GET_FEATURE_SET_MATRIX
++		},
++		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++		.doit = rtw_cfgvendor_get_feature_set_matrix
++	}
++};
++
++static const struct  nl80211_vendor_cmd_info rtw_vendor_events[] = {
++#if defined(GSCAN_SUPPORT) && 0
++	{ OUI_GOOGLE, GSCAN_EVENT_SIGNIFICANT_CHANGE_RESULTS },
++	{ OUI_GOOGLE, GSCAN_EVENT_HOTLIST_RESULTS_FOUND },
++	{ OUI_GOOGLE, GSCAN_EVENT_SCAN_RESULTS_AVAILABLE },
++	{ OUI_GOOGLE, GSCAN_EVENT_FULL_SCAN_RESULTS },
++#endif /* GSCAN_SUPPORT */
++#if defined(RTT_SUPPORT) && 0
++	{ OUI_GOOGLE, RTT_EVENT_COMPLETE },
++#endif /* RTT_SUPPORT */
++
++#ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
++	{ OUI_GOOGLE, GOOGLE_RSSI_MONITOR_EVENT },
++#endif /* RTW_CFGVENDOR_RSSIMONITR */
++
++#if defined(GSCAN_SUPPORT) && 0
++	{ OUI_GOOGLE, GSCAN_EVENT_COMPLETE_SCAN },
++	{ OUI_GOOGLE, GSCAN_EVENT_HOTLIST_RESULTS_LOST }
++#endif /* GSCAN_SUPPORT */
++};
++
++int rtw_cfgvendor_attach(struct wiphy *wiphy)
++{
++
++	RTW_INFO("Register RTW cfg80211 vendor cmd(0x%x) interface\n", NL80211_CMD_VENDOR);
++
++	wiphy->vendor_commands	= rtw_vendor_cmds;
++	wiphy->n_vendor_commands = ARRAY_SIZE(rtw_vendor_cmds);
++	wiphy->vendor_events	= rtw_vendor_events;
++	wiphy->n_vendor_events	= ARRAY_SIZE(rtw_vendor_events);
++
++	return 0;
++}
++
++int rtw_cfgvendor_detach(struct wiphy *wiphy)
++{
++	RTW_INFO("Vendor: Unregister RTW cfg80211 vendor interface\n");
++
++	wiphy->vendor_commands  = NULL;
++	wiphy->vendor_events    = NULL;
++	wiphy->n_vendor_commands = 0;
++	wiphy->n_vendor_events  = 0;
++
++	return 0;
++}
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */
++
++#endif /* CONFIG_IOCTL_CFG80211 */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_cfgvendor.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_cfgvendor.h
+new file mode 100644
+index 000000000..0e59b2b94
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_cfgvendor.h
+@@ -0,0 +1,636 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef _RTW_CFGVENDOR_H_
++#define _RTW_CFGVENDOR_H_
++
++#define OUI_GOOGLE  0x001A11
++#define ATTRIBUTE_U32_LEN                  (NLA_HDRLEN  + 4)
++#define VENDOR_ID_OVERHEAD                 ATTRIBUTE_U32_LEN
++#define VENDOR_SUBCMD_OVERHEAD             ATTRIBUTE_U32_LEN
++#define VENDOR_DATA_OVERHEAD               (NLA_HDRLEN)
++
++#define SCAN_RESULTS_COMPLETE_FLAG_LEN       ATTRIBUTE_U32_LEN
++#define SCAN_INDEX_HDR_LEN                   (NLA_HDRLEN)
++#define SCAN_ID_HDR_LEN                      ATTRIBUTE_U32_LEN
++#define SCAN_FLAGS_HDR_LEN                   ATTRIBUTE_U32_LEN
++#define GSCAN_NUM_RESULTS_HDR_LEN            ATTRIBUTE_U32_LEN
++#define GSCAN_RESULTS_HDR_LEN                (NLA_HDRLEN)
++#define GSCAN_BATCH_RESULT_HDR_LEN  (SCAN_INDEX_HDR_LEN + SCAN_ID_HDR_LEN + \
++				     SCAN_FLAGS_HDR_LEN + \
++				     GSCAN_NUM_RESULTS_HDR_LEN + \
++				     GSCAN_RESULTS_HDR_LEN)
++
++#define VENDOR_REPLY_OVERHEAD       (VENDOR_ID_OVERHEAD + \
++				     VENDOR_SUBCMD_OVERHEAD + \
++				     VENDOR_DATA_OVERHEAD)
++typedef enum {
++    /* don't use 0 as a valid subcommand */
++    VENDOR_NL80211_SUBCMD_UNSPECIFIED,
++
++    /* define all vendor startup commands between 0x0 and 0x0FFF */
++    VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001,
++    VENDOR_NL80211_SUBCMD_RANGE_END   = 0x0FFF,
++
++    /* define all GScan related commands between 0x1000 and 0x10FF */
++    ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000,
++    ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END   = 0x10FF,
++
++    /* define all NearbyDiscovery related commands between 0x1100 and 0x11FF */
++    ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1100,
++    ANDROID_NL80211_SUBCMD_NBD_RANGE_END   = 0x11FF,
++
++    /* define all RTT related commands between 0x1100 and 0x11FF */
++    ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100,
++    ANDROID_NL80211_SUBCMD_RTT_RANGE_END   = 0x11FF,
++
++    ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200,
++    ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END   = 0x12FF,
++
++    /* define all Logger related commands between 0x1400 and 0x14FF */
++    ANDROID_NL80211_SUBCMD_DEBUG_RANGE_START = 0x1400,
++    ANDROID_NL80211_SUBCMD_DEBUG_RANGE_END   = 0x14FF,
++
++    /* define all wifi offload related commands between 0x1600 and 0x16FF */
++    ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_START = 0x1600,
++    ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_END   = 0x16FF,
++
++    /* define all NAN related commands between 0x1700 and 0x17FF */
++    ANDROID_NL80211_SUBCMD_NAN_RANGE_START = 0x1700,
++    ANDROID_NL80211_SUBCMD_NAN_RANGE_END   = 0x17FF,
++
++    /* define all Android Packet Filter related commands between 0x1800 and 0x18FF */
++    ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_START = 0x1800,
++    ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_END   = 0x18FF,
++
++    /* This is reserved for future usage */
++
++} ANDROID_VENDOR_SUB_COMMAND;
++
++enum rtw_vendor_subcmd {
++    GSCAN_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START,
++
++    GSCAN_SUBCMD_SET_CONFIG,                            /* 0x1001 */
++
++    GSCAN_SUBCMD_SET_SCAN_CONFIG,                       /* 0x1002 */
++    GSCAN_SUBCMD_ENABLE_GSCAN,                          /* 0x1003 */
++    GSCAN_SUBCMD_GET_SCAN_RESULTS,                      /* 0x1004 */
++    GSCAN_SUBCMD_SCAN_RESULTS,                          /* 0x1005 */
++
++    GSCAN_SUBCMD_SET_HOTLIST,                           /* 0x1006 */
++
++    GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG,         /* 0x1007 */
++    GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS,              /* 0x1008 */
++    GSCAN_SUBCMD_GET_CHANNEL_LIST,                       /* 0x1009 */
++
++    WIFI_SUBCMD_GET_FEATURE_SET,                         /* 0x100A */
++    WIFI_SUBCMD_GET_FEATURE_SET_MATRIX,                  /* 0x100B */
++    WIFI_SUBCMD_SET_PNO_RANDOM_MAC_OUI,                  /* 0x100C */
++    WIFI_SUBCMD_NODFS_SET,                               /* 0x100D */
++    WIFI_SUBCMD_SET_COUNTRY_CODE,                             /* 0x100E */
++    /* Add more sub commands here */
++    GSCAN_SUBCMD_SET_EPNO_SSID,                          /* 0x100F */
++
++    WIFI_SUBCMD_SET_SSID_WHITE_LIST,                    /* 0x1010 */
++    WIFI_SUBCMD_SET_ROAM_PARAMS,                        /* 0x1011 */
++    WIFI_SUBCMD_ENABLE_LAZY_ROAM,                       /* 0x1012 */
++    WIFI_SUBCMD_SET_BSSID_PREF,                         /* 0x1013 */
++    WIFI_SUBCMD_SET_BSSID_BLACKLIST,                     /* 0x1014 */
++
++    GSCAN_SUBCMD_ANQPO_CONFIG,                          /* 0x1015 */
++    WIFI_SUBCMD_SET_RSSI_MONITOR,                       /* 0x1016 */
++    WIFI_SUBCMD_CONFIG_ND_OFFLOAD,                      /* 0x1017 */
++    /* Add more sub commands here */
++
++    GSCAN_SUBCMD_MAX,
++
++	RTT_SUBCMD_SET_CONFIG = ANDROID_NL80211_SUBCMD_RTT_RANGE_START,
++	RTT_SUBCMD_CANCEL_CONFIG,
++	RTT_SUBCMD_GETCAPABILITY,
++
++    APF_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_START,
++    APF_SUBCMD_SET_FILTER,
++    
++    LOGGER_START_LOGGING = ANDROID_NL80211_SUBCMD_DEBUG_RANGE_START,
++    LOGGER_TRIGGER_MEM_DUMP,
++    LOGGER_GET_MEM_DUMP,
++    LOGGER_GET_VER,
++    LOGGER_GET_RING_STATUS,
++    LOGGER_GET_RING_DATA,
++    LOGGER_GET_FEATURE,
++    LOGGER_RESET_LOGGING,
++    LOGGER_TRIGGER_DRIVER_MEM_DUMP,
++    LOGGER_GET_DRIVER_MEM_DUMP,
++    LOGGER_START_PKT_FATE_MONITORING,
++    LOGGER_GET_TX_PKT_FATES,
++    LOGGER_GET_RX_PKT_FATES,
++
++	WIFI_OFFLOAD_SUBCMD_START_MKEEP_ALIVE = ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_START,
++	WIFI_OFFLOAD_SUBCMD_STOP_MKEEP_ALIVE,
++
++	VENDOR_SUBCMD_MAX
++};
++
++enum gscan_attributes {
++	GSCAN_ATTRIBUTE_NUM_BUCKETS = 10,
++	GSCAN_ATTRIBUTE_BASE_PERIOD,
++	GSCAN_ATTRIBUTE_BUCKETS_BAND,
++	GSCAN_ATTRIBUTE_BUCKET_ID,
++	GSCAN_ATTRIBUTE_BUCKET_PERIOD,
++	GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS,
++	GSCAN_ATTRIBUTE_BUCKET_CHANNELS,
++	GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN,
++	GSCAN_ATTRIBUTE_REPORT_THRESHOLD,
++	GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE,
++	GSCAN_ATTRIBUTE_BAND = GSCAN_ATTRIBUTE_BUCKETS_BAND,
++
++	GSCAN_ATTRIBUTE_ENABLE_FEATURE = 20,
++	GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE,
++	GSCAN_ATTRIBUTE_FLUSH_FEATURE,
++	GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS,
++	GSCAN_ATTRIBUTE_REPORT_EVENTS,
++	/* remaining reserved for additional attributes */
++	GSCAN_ATTRIBUTE_NUM_OF_RESULTS = 30,
++	GSCAN_ATTRIBUTE_FLUSH_RESULTS,
++	GSCAN_ATTRIBUTE_SCAN_RESULTS,                       /* flat array of wifi_scan_result */
++	GSCAN_ATTRIBUTE_SCAN_ID,                            /* indicates scan number */
++	GSCAN_ATTRIBUTE_SCAN_FLAGS,                         /* indicates if scan was aborted */
++	GSCAN_ATTRIBUTE_AP_FLAGS,                           /* flags on significant change event */
++	GSCAN_ATTRIBUTE_NUM_CHANNELS,
++	GSCAN_ATTRIBUTE_CHANNEL_LIST,
++
++	/* remaining reserved for additional attributes */
++
++	GSCAN_ATTRIBUTE_SSID = 40,
++	GSCAN_ATTRIBUTE_BSSID,
++	GSCAN_ATTRIBUTE_CHANNEL,
++	GSCAN_ATTRIBUTE_RSSI,
++	GSCAN_ATTRIBUTE_TIMESTAMP,
++	GSCAN_ATTRIBUTE_RTT,
++	GSCAN_ATTRIBUTE_RTTSD,
++
++	/* remaining reserved for additional attributes */
++
++	GSCAN_ATTRIBUTE_HOTLIST_BSSIDS = 50,
++	GSCAN_ATTRIBUTE_RSSI_LOW,
++	GSCAN_ATTRIBUTE_RSSI_HIGH,
++	GSCAN_ATTRIBUTE_HOSTLIST_BSSID_ELEM,
++	GSCAN_ATTRIBUTE_HOTLIST_FLUSH,
++
++	/* remaining reserved for additional attributes */
++	GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE = 60,
++	GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE,
++	GSCAN_ATTRIBUTE_MIN_BREACHING,
++	GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS,
++	GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH,
++	GSCAN_ATTRIBUTE_MAX
++};
++
++enum gscan_bucket_attributes {
++	GSCAN_ATTRIBUTE_CH_BUCKET_1,
++	GSCAN_ATTRIBUTE_CH_BUCKET_2,
++	GSCAN_ATTRIBUTE_CH_BUCKET_3,
++	GSCAN_ATTRIBUTE_CH_BUCKET_4,
++	GSCAN_ATTRIBUTE_CH_BUCKET_5,
++	GSCAN_ATTRIBUTE_CH_BUCKET_6,
++	GSCAN_ATTRIBUTE_CH_BUCKET_7
++};
++
++enum gscan_ch_attributes {
++	GSCAN_ATTRIBUTE_CH_ID_1,
++	GSCAN_ATTRIBUTE_CH_ID_2,
++	GSCAN_ATTRIBUTE_CH_ID_3,
++	GSCAN_ATTRIBUTE_CH_ID_4,
++	GSCAN_ATTRIBUTE_CH_ID_5,
++	GSCAN_ATTRIBUTE_CH_ID_6,
++	GSCAN_ATTRIBUTE_CH_ID_7
++};
++
++enum wifi_rssi_monitor_attr {
++        RSSI_MONITOR_ATTRIBUTE_MAX_RSSI,
++        RSSI_MONITOR_ATTRIBUTE_MIN_RSSI,
++        RSSI_MONITOR_ATTRIBUTE_START,
++};
++
++
++enum rtt_attributes {
++	RTT_ATTRIBUTE_TARGET_CNT,
++	RTT_ATTRIBUTE_TARGET_INFO,
++	RTT_ATTRIBUTE_TARGET_MAC,
++	RTT_ATTRIBUTE_TARGET_TYPE,
++	RTT_ATTRIBUTE_TARGET_PEER,
++	RTT_ATTRIBUTE_TARGET_CHAN,
++	RTT_ATTRIBUTE_TARGET_MODE,
++	RTT_ATTRIBUTE_TARGET_INTERVAL,
++	RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT,
++	RTT_ATTRIBUTE_TARGET_NUM_PKT,
++	RTT_ATTRIBUTE_TARGET_NUM_RETRY
++};
++
++enum logger_attributes {
++	LOGGER_ATTRIBUTE_GET_DRIVER,
++	LOGGER_ATTRIBUTE_GET_FW,
++	LOGGER_ATTRIBUTE_RING_ID,
++	LOGGER_ATTRIBUTE_RING_NAME,
++	LOGGER_ATTRIBUTE_RING_FLAGS,
++	LOGGER_ATTRIBUTE_LOG_LEVEL,
++	LOGGER_ATTRIBUTE_LOG_TIME_INTVAL,
++	LOGGER_ATTRIBUTE_LOG_MIN_DATA_SIZE,
++	LOGGER_ATTRIBUTE_FW_DUMP_LEN,
++	LOGGER_ATTRIBUTE_FW_DUMP_DATA,
++	LOGGERG_ATTRIBUTE_RING_DATA,
++	LOGGER_ATTRIBUTE_RING_STATUS,
++	LOGGER_ATTRIBUTE_RING_NUM
++};
++typedef enum rtw_vendor_event {
++    RTK_RESERVED1,
++    RTK_RESERVED2,
++    GSCAN_EVENT_SIGNIFICANT_CHANGE_RESULTS ,
++    GSCAN_EVENT_HOTLIST_RESULTS_FOUND,
++    GSCAN_EVENT_SCAN_RESULTS_AVAILABLE,
++    GSCAN_EVENT_FULL_SCAN_RESULTS,
++    RTT_EVENT_COMPLETE,
++    GSCAN_EVENT_COMPLETE_SCAN,
++    GSCAN_EVENT_HOTLIST_RESULTS_LOST,
++    GSCAN_EVENT_EPNO_EVENT,
++    GOOGLE_DEBUG_RING_EVENT,
++    GOOGLE_DEBUG_MEM_DUMP_EVENT,
++    GSCAN_EVENT_ANQPO_HOTSPOT_MATCH,
++    GOOGLE_RSSI_MONITOR_EVENT
++} rtw_vendor_event_t;
++
++enum andr_wifi_feature_set_attr {
++	ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET,
++	ANDR_WIFI_ATTRIBUTE_FEATURE_SET,
++	ANDR_WIFI_ATTRIBUTE_RANDOM_MAC_OUI,
++	ANDR_WIFI_ATTRIBUTE_NODFS_SET,
++	ANDR_WIFI_ATTRIBUTE_COUNTRY,
++	ANDR_WIFI_ATTRIBUTE_ND_OFFLOAD_VALUE
++	// Add more attribute here
++};
++
++typedef enum rtw_vendor_gscan_attribute {
++	ATTR_START_GSCAN,
++	ATTR_STOP_GSCAN,
++	ATTR_SET_SCAN_BATCH_CFG_ID, /* set batch scan params */
++	ATTR_SET_SCAN_GEOFENCE_CFG_ID, /* set list of bssids to track */
++	ATTR_SET_SCAN_SIGNIFICANT_CFG_ID, /* set list of bssids, rssi threshold etc.. */
++	ATTR_SET_SCAN_CFG_ID, /* set common scan config params here */
++	ATTR_GET_GSCAN_CAPABILITIES_ID,
++	/* Add more sub commands here */
++	ATTR_GSCAN_MAX
++} rtw_vendor_gscan_attribute_t;
++
++typedef enum gscan_batch_attribute {
++	ATTR_GSCAN_BATCH_BESTN,
++	ATTR_GSCAN_BATCH_MSCAN,
++	ATTR_GSCAN_BATCH_BUFFER_THRESHOLD
++} gscan_batch_attribute_t;
++
++typedef enum gscan_geofence_attribute {
++	ATTR_GSCAN_NUM_HOTLIST_BSSID,
++	ATTR_GSCAN_HOTLIST_BSSID
++} gscan_geofence_attribute_t;
++
++typedef enum gscan_complete_event {
++	WIFI_SCAN_BUFFER_FULL,
++	WIFI_SCAN_COMPLETE
++} gscan_complete_event_t;
++/* wifi_hal.h */
++/* WiFi Common definitions */
++typedef unsigned char byte;
++typedef int wifi_request_id;
++typedef int wifi_channel;                       // indicates channel frequency in MHz
++typedef int wifi_rssi;
++typedef byte mac_addr[6];
++typedef byte oui[3];
++typedef int64_t wifi_timestamp;                 // In microseconds (us)
++typedef int64_t wifi_timespan;                  // In picoseconds  (ps)
++
++struct wifi_info;
++struct wifi_interface_info;
++typedef struct wifi_info *wifi_handle;
++typedef struct wifi_interface_info *wifi_interface_handle;
++
++/* channel operating width */
++typedef enum {
++    WIFI_CHAN_WIDTH_20    = 0,
++    WIFI_CHAN_WIDTH_40    = 1,
++    WIFI_CHAN_WIDTH_80    = 2,
++    WIFI_CHAN_WIDTH_160   = 3,
++    WIFI_CHAN_WIDTH_80P80 = 4,
++    WIFI_CHAN_WIDTH_5     = 5,
++    WIFI_CHAN_WIDTH_10    = 6,
++    WIFI_CHAN_WIDTH_INVALID = -1
++} wifi_channel_width;
++
++typedef int wifi_radio;
++
++typedef struct {
++    wifi_channel_width width;
++    int center_frequency0;
++    int center_frequency1;
++    int primary_frequency;
++} wifi_channel_spec;
++
++typedef enum {
++    WIFI_SUCCESS = 0,
++    WIFI_ERROR_NONE = 0,
++    WIFI_ERROR_UNKNOWN = -1,
++    WIFI_ERROR_UNINITIALIZED = -2,
++    WIFI_ERROR_NOT_SUPPORTED = -3,
++    WIFI_ERROR_NOT_AVAILABLE = -4,              // Not available right now, but try later
++    WIFI_ERROR_INVALID_ARGS = -5,
++    WIFI_ERROR_INVALID_REQUEST_ID = -6,
++    WIFI_ERROR_TIMED_OUT = -7,
++    WIFI_ERROR_TOO_MANY_REQUESTS = -8,          // Too many instances of this request
++    WIFI_ERROR_OUT_OF_MEMORY = -9,
++    WIFI_ERROR_BUSY = -10,
++} wifi_error;
++
++typedef int wifi_ring_buffer_id;
++/* ring buffer params */
++/**
++ * written_bytes and read_bytes implement a producer consumer API
++ *     hence written_bytes >= read_bytes
++ * a modulo arithmetic of the buffer size has to be applied to those counters:
++ * actual offset into ring buffer = written_bytes % ring_buffer_byte_size
++ *
++ */
++typedef struct {
++    u8 name[32];
++    u32 flags;
++    wifi_ring_buffer_id ring_id; // unique integer representing the ring
++    u32 ring_buffer_byte_size;   // total memory size allocated for the buffer
++    u32 verbose_level;           // verbose level for ring buffer
++    u32 written_bytes;           // number of bytes that was written to the buffer by driver,
++                                 // monotonously increasing integer
++    u32 read_bytes;              // number of bytes that was read from the buffer by user land,
++                                 // monotonously increasing integer
++    u32 written_records;         // number of records that was written to the buffer by driver,
++                                 // monotonously increasing integer
++} wifi_ring_buffer_status;
++
++#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
++#define STATS_MAJOR_VERSION      1
++#define STATS_MINOR_VERSION      0
++#define STATS_MICRO_VERSION      0
++
++typedef enum {
++    WIFI_DISCONNECTED = 0,
++    WIFI_AUTHENTICATING = 1,
++    WIFI_ASSOCIATING = 2,
++    WIFI_ASSOCIATED = 3,
++    WIFI_EAPOL_STARTED = 4,   // if done by firmware/driver
++    WIFI_EAPOL_COMPLETED = 5, // if done by firmware/driver
++} wifi_connection_state;
++
++typedef enum {
++    WIFI_ROAMING_IDLE = 0,
++    WIFI_ROAMING_ACTIVE = 1,
++} wifi_roam_state;
++
++typedef enum {
++    WIFI_INTERFACE_STA = 0,
++    WIFI_INTERFACE_SOFTAP = 1,
++    WIFI_INTERFACE_IBSS = 2,
++    WIFI_INTERFACE_P2P_CLIENT = 3,
++    WIFI_INTERFACE_P2P_GO = 4,
++    WIFI_INTERFACE_NAN = 5,
++    WIFI_INTERFACE_MESH = 6,
++    WIFI_INTERFACE_UNKNOWN = -1
++ } wifi_interface_mode;
++
++#define WIFI_CAPABILITY_QOS          0x00000001     // set for QOS association
++#define WIFI_CAPABILITY_PROTECTED    0x00000002     // set for protected association (802.11 beacon frame control protected bit set)
++#define WIFI_CAPABILITY_INTERWORKING 0x00000004     // set if 802.11 Extended Capabilities element interworking bit is set
++#define WIFI_CAPABILITY_HS20         0x00000008     // set for HS20 association
++#define WIFI_CAPABILITY_SSID_UTF8    0x00000010     // set is 802.11 Extended Capabilities element UTF-8 SSID bit is set
++#define WIFI_CAPABILITY_COUNTRY      0x00000020     // set is 802.11 Country Element is present
++
++typedef struct {
++   wifi_interface_mode mode;     // interface mode
++   u8 mac_addr[6];               // interface mac address (self)
++   wifi_connection_state state;  // connection state (valid for STA, CLI only)
++   wifi_roam_state roaming;      // roaming state
++   u32 capabilities;             // WIFI_CAPABILITY_XXX (self)
++   u8 ssid[33];                  // null terminated SSID
++   u8 bssid[6];                  // bssid
++   u8 ap_country_str[3];         // country string advertised by AP
++   u8 country_str[3];            // country string for this association
++} wifi_interface_link_layer_info;
++
++/* channel information */
++typedef struct {
++   wifi_channel_width width;   // channel width (20, 40, 80, 80+80, 160)
++   wifi_channel center_freq;   // primary 20 MHz channel
++   wifi_channel center_freq0;  // center frequency (MHz) first segment
++   wifi_channel center_freq1;  // center frequency (MHz) second segment
++} wifi_channel_info;
++
++/* wifi rate */
++typedef struct {
++   u32 preamble   :3;   // 0: OFDM, 1:CCK, 2:HT 3:VHT 4..7 reserved
++   u32 nss        :2;   // 0:1x1, 1:2x2, 3:3x3, 4:4x4
++   u32 bw         :3;   // 0:20MHz, 1:40Mhz, 2:80Mhz, 3:160Mhz
++   u32 rateMcsIdx :8;   // OFDM/CCK rate code would be as per ieee std in the units of 0.5mbps
++                        // HT/VHT it would be mcs index
++   u32 reserved  :16;   // reserved
++   u32 bitrate;         // units of 100 Kbps
++} wifi_rate;
++
++/* channel statistics */
++typedef struct {
++   wifi_channel_info channel;  // channel
++   u32 on_time;                // msecs the radio is awake (32 bits number accruing over time)
++   u32 cca_busy_time;          // msecs the CCA register is busy (32 bits number accruing over time)
++} wifi_channel_stat;
++
++// Max number of tx power levels. The actual number vary per device and is specified by |num_tx_levels|
++#define RADIO_STAT_MAX_TX_LEVELS 256
++
++/* Internal radio statistics structure in the driver */
++typedef struct {
++   wifi_radio radio;                      // wifi radio (if multiple radio supported)
++   u32 on_time;                           // msecs the radio is awake (32 bits number accruing over time)
++   u32 tx_time;                           // msecs the radio is transmitting (32 bits number accruing over time)
++   u32 rx_time;                           // msecs the radio is in active receive (32 bits number accruing over time)
++   u32 on_time_scan;                      // msecs the radio is awake due to all scan (32 bits number accruing over time)
++   u32 on_time_nbd;                       // msecs the radio is awake due to NAN (32 bits number accruing over time)
++   u32 on_time_gscan;                     // msecs the radio is awake due to G?scan (32 bits number accruing over time)
++   u32 on_time_roam_scan;                 // msecs the radio is awake due to roam?scan (32 bits number accruing over time)
++   u32 on_time_pno_scan;                  // msecs the radio is awake due to PNO scan (32 bits number accruing over time)
++   u32 on_time_hs20;                      // msecs the radio is awake due to HS2.0 scans and GAS exchange (32 bits number accruing over time)
++   u32 num_channels;                      // number of channels
++   wifi_channel_stat channels[];          // channel statistics
++} wifi_radio_stat_internal;
++
++/**
++ * Packet statistics reporting by firmware is performed on MPDU basi (i.e. counters increase by 1 for each MPDU)
++ * As well, "data packet" in associated comments, shall be interpreted as 802.11 data packet,
++ * that is, 802.11 frame control subtype == 2 and excluding management and control frames.
++ *
++ * As an example, in the case of transmission of an MSDU fragmented in 16 MPDUs which are transmitted
++ * OTA in a 16 units long a-mpdu, for which a block ack is received with 5 bits set:
++ *          tx_mpdu : shall increase by 5
++ *          retries : shall increase by 16
++ *          tx_ampdu : shall increase by 1
++ * data packet counters shall not increase regardless of the number of BAR potentially sent by device for this a-mpdu
++ * data packet counters shall not increase regardless of the number of BA received by device for this a-mpdu
++ *
++ * For each subsequent retransmission of the 11 remaining non ACK'ed mpdus
++ * (regardless of the fact that they are transmitted in a-mpdu or not)
++ *          retries : shall increase by 1
++ *
++ * If no subsequent BA or ACK are received from AP, until packet lifetime expires for those 11 packet that were not ACK'ed
++ *          mpdu_lost : shall increase by 11
++ */
++
++/* per rate statistics */
++typedef struct {
++   wifi_rate rate;     // rate information
++   u32 tx_mpdu;        // number of successfully transmitted data pkts (ACK rcvd)
++   u32 rx_mpdu;        // number of received data pkts
++   u32 mpdu_lost;      // number of data packet losses (no ACK)
++   u32 retries;        // total number of data pkt retries
++   u32 retries_short;  // number of short data pkt retries
++   u32 retries_long;   // number of long data pkt retries
++} wifi_rate_stat;
++
++/* access categories */
++typedef enum {
++   WIFI_AC_VO  = 0,
++   WIFI_AC_VI  = 1,
++   WIFI_AC_BE  = 2,
++   WIFI_AC_BK  = 3,
++   WIFI_AC_MAX = 4,
++} wifi_traffic_ac;
++
++/* wifi peer type */
++typedef enum
++{
++   WIFI_PEER_STA,
++   WIFI_PEER_AP,
++   WIFI_PEER_P2P_GO,
++   WIFI_PEER_P2P_CLIENT,
++   WIFI_PEER_NAN,
++   WIFI_PEER_TDLS,
++   WIFI_PEER_INVALID,
++} wifi_peer_type;
++
++/* per peer statistics */
++typedef struct {
++   wifi_peer_type type;           // peer type (AP, TDLS, GO etc.)
++   u8 peer_mac_address[6];        // mac address
++   u32 capabilities;              // peer WIFI_CAPABILITY_XXX
++   u32 num_rate;                  // number of rates
++   wifi_rate_stat rate_stats[];   // per rate statistics, number of entries  = num_rate
++} wifi_peer_info;
++
++/* Per access category statistics */
++typedef struct {
++   wifi_traffic_ac ac;             // access category (VI, VO, BE, BK)
++   u32 tx_mpdu;                    // number of successfully transmitted unicast data pkts (ACK rcvd)
++   u32 rx_mpdu;                    // number of received unicast data packets
++   u32 tx_mcast;                   // number of succesfully transmitted multicast data packets
++                                   // STA case: implies ACK received from AP for the unicast packet in which mcast pkt was sent
++   u32 rx_mcast;                   // number of received multicast data packets
++   u32 rx_ampdu;                   // number of received unicast a-mpdus; support of this counter is optional
++   u32 tx_ampdu;                   // number of transmitted unicast a-mpdus; support of this counter is optional
++   u32 mpdu_lost;                  // number of data pkt losses (no ACK)
++   u32 retries;                    // total number of data pkt retries
++   u32 retries_short;              // number of short data pkt retries
++   u32 retries_long;               // number of long data pkt retries
++   u32 contention_time_min;        // data pkt min contention time (usecs)
++   u32 contention_time_max;        // data pkt max contention time (usecs)
++   u32 contention_time_avg;        // data pkt avg contention time (usecs)
++   u32 contention_num_samples;     // num of data pkts used for contention statistics
++} wifi_wmm_ac_stat;
++
++/* interface statistics */
++typedef struct {
++   wifi_interface_handle iface;          // wifi interface
++   wifi_interface_link_layer_info info;  // current state of the interface
++   u32 beacon_rx;                        // access point beacon received count from connected AP
++   u64 average_tsf_offset;               // average beacon offset encountered (beacon_TSF - TBTT)
++                                         // The average_tsf_offset field is used so as to calculate the
++                                         // typical beacon contention time on the channel as well may be
++                                         // used to debug beacon synchronization and related power consumption issue
++   u32 leaky_ap_detected;                // indicate that this AP typically leaks packets beyond the driver guard time.
++   u32 leaky_ap_avg_num_frames_leaked;  // average number of frame leaked by AP after frame with PM bit set was ACK'ed by AP
++   u32 leaky_ap_guard_time;              // guard time currently in force (when implementing IEEE power management based on
++                                         // frame control PM bit), How long driver waits before shutting down the radio and
++                                         // after receiving an ACK for a data frame with PM bit set)
++   u32 mgmt_rx;                          // access point mgmt frames received count from connected AP (including Beacon)
++   u32 mgmt_action_rx;                   // action frames received count
++   u32 mgmt_action_tx;                   // action frames transmit count
++   wifi_rssi rssi_mgmt;                  // access Point Beacon and Management frames RSSI (averaged)
++   wifi_rssi rssi_data;                  // access Point Data Frames RSSI (averaged) from connected AP
++   wifi_rssi rssi_ack;                   // access Point ACK RSSI (averaged) from connected AP
++   wifi_wmm_ac_stat ac[WIFI_AC_MAX];     // per ac data packet statistics
++   u32 num_peers;                        // number of peers
++   wifi_peer_info peer_info[];           // per peer statistics
++} wifi_iface_stat;
++
++/* configuration params */
++typedef struct {
++   u32 mpdu_size_threshold;             // threshold to classify the pkts as short or long
++                                        // packet size < mpdu_size_threshold => short
++   u32 aggressive_statistics_gathering; // set for field debug mode. Driver should collect all statistics regardless of performance impact.
++} wifi_link_layer_params;
++
++#define RSSI_MONITOR_EVT_VERSION   1
++typedef struct {
++    u8 version;
++    s8 cur_rssi;
++    mac_addr BSSID;
++} rssi_monitor_evt;
++
++
++/* wifi statistics bitmap  */
++#define WIFI_STATS_RADIO              0x00000001      // all radio statistics
++#define WIFI_STATS_RADIO_CCA          0x00000002      // cca_busy_time (within radio statistics)
++#define WIFI_STATS_RADIO_CHANNELS     0x00000004      // all channel statistics (within radio statistics)
++#define WIFI_STATS_RADIO_SCAN         0x00000008      // all scan statistics (within radio statistics)
++#define WIFI_STATS_IFACE              0x00000010      // all interface statistics
++#define WIFI_STATS_IFACE_TXRATE       0x00000020      // all tx rate statistics (within interface statistics)
++#define WIFI_STATS_IFACE_AC           0x00000040      // all ac statistics (within interface statistics)
++#define WIFI_STATS_IFACE_CONTENTION   0x00000080      // all contention (min, max, avg) statistics (within ac statisctics)
++
++#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
++
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT)
++extern int rtw_cfgvendor_attach(struct wiphy *wiphy);
++extern int rtw_cfgvendor_detach(struct wiphy *wiphy);
++extern int rtw_cfgvendor_send_async_event(struct wiphy *wiphy,
++	struct net_device *dev, int event_id, const void  *data, int len);
++#if defined(GSCAN_SUPPORT) && 0
++extern int rtw_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
++	struct net_device *dev, void  *data, int len, rtw_vendor_event_t event);
++#endif
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */
++
++#ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
++void rtw_cfgvendor_rssi_monitor_evt(_adapter *padapter);
++#endif
++
++#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
++void rtw_hal_pno_random_gen_mac_addr(PADAPTER adapter);
++void rtw_hal_set_hw_mac_addr(PADAPTER adapter, u8 *mac_addr);
++#endif
++
++
++#endif /* _RTW_CFGVENDOR_H_ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_proc.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_proc.c
+new file mode 100755
+index 000000000..e31bf994b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_proc.c
+@@ -0,0 +1,5614 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <linux/ctype.h>	/* tolower() */
++#include <drv_types.h>
++#include <hal_data.h>
++#include "rtw_proc.h"
++#include <rtw_btcoex.h>
++
++#ifdef CONFIG_PROC_DEBUG
++
++static struct proc_dir_entry *rtw_proc = NULL;
++
++inline struct proc_dir_entry *get_rtw_drv_proc(void)
++{
++	return rtw_proc;
++}
++
++#define RTW_PROC_NAME DRV_NAME
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
++#define file_inode(file) ((file)->f_dentry->d_inode)
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))
++#define PDE_DATA(inode) PDE((inode))->data
++#define proc_get_parent_data(inode) PDE((inode))->parent->data
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
++#define get_proc_net proc_net
++#else
++#define get_proc_net init_net.proc_net
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))
++int single_open_size(struct file *file, int (*show)(struct seq_file *, void *),
++		void *data, size_t size)
++{
++	char *buf = kmalloc(size, GFP_KERNEL);
++	int ret;
++	if (!buf)
++		return -ENOMEM;
++	ret = single_open(file, show, data);
++	if (ret) {
++		kfree(buf);
++		return ret;
++	}
++	((struct seq_file *)file->private_data)->buf = buf;
++	((struct seq_file *)file->private_data)->size = size;
++	return 0;
++}
++#endif
++
++inline struct proc_dir_entry *rtw_proc_create_dir(const char *name, struct proc_dir_entry *parent, void *data)
++{
++	struct proc_dir_entry *entry;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
++	entry = proc_mkdir_data(name, S_IRUGO | S_IXUGO, parent, data);
++#else
++	/* entry = proc_mkdir_mode(name, S_IRUGO|S_IXUGO, parent); */
++	entry = proc_mkdir(name, parent);
++	if (entry)
++		entry->data = data;
++#endif
++
++	return entry;
++}
++
++inline struct proc_dir_entry *rtw_proc_create_entry(const char *name, struct proc_dir_entry *parent,
++	const struct file_operations *fops, void * data)
++{
++	struct proc_dir_entry *entry;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26))
++	entry = proc_create_data(name,  S_IFREG | S_IRUGO | S_IWUGO, parent, fops, data);
++#else
++	entry = create_proc_entry(name, S_IFREG | S_IRUGO | S_IWUGO, parent);
++	if (entry) {
++		entry->data = data;
++		entry->proc_fops = fops;
++	}
++#endif
++
++	return entry;
++}
++
++static int proc_get_dummy(struct seq_file *m, void *v)
++{
++	return 0;
++}
++
++static int proc_get_drv_version(struct seq_file *m, void *v)
++{
++	dump_drv_version(m);
++	return 0;
++}
++
++static int proc_get_log_level(struct seq_file *m, void *v)
++{
++	dump_log_level(m);
++	return 0;
++}
++
++static int proc_get_drv_cfg(struct seq_file *m, void *v)
++{
++	dump_drv_cfg(m);
++	return 0;
++}
++
++static ssize_t proc_set_log_level(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	char tmp[32];
++	int log_level;
++
++	if (count < 1)
++		return -EINVAL;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++#ifdef CONFIG_RTW_DEBUG
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d ", &log_level);
++
++		if (num == 1 &&
++		    log_level >= _DRV_NONE_ && log_level <= _DRV_MAX_) {
++			rtw_drv_log_level = log_level;
++			printk("rtw_drv_log_level:%d\n", rtw_drv_log_level);
++		}
++	} else
++		return -EFAULT;
++#else
++	printk("CONFIG_RTW_DEBUG is disabled\n");
++#endif
++
++	return count;
++}
++
++#ifdef DBG_MEM_ALLOC
++static int proc_get_mstat(struct seq_file *m, void *v)
++{
++	rtw_mstat_dump(m);
++	return 0;
++}
++#endif /* DBG_MEM_ALLOC */
++
++static int proc_get_country_chplan_map(struct seq_file *m, void *v)
++{
++	dump_country_chplan_map(m);
++	return 0;
++}
++
++static int proc_get_chplan_id_list(struct seq_file *m, void *v)
++{
++	dump_chplan_id_list(m);
++	return 0;
++}
++
++static int proc_get_chplan_test(struct seq_file *m, void *v)
++{
++	dump_chplan_test(m);
++	return 0;
++}
++
++static int proc_get_chplan_ver(struct seq_file *m, void *v)
++{
++	dump_chplan_ver(m);
++	return 0;
++}
++
++static int proc_get_global_op_class(struct seq_file *m, void *v)
++{
++	dump_global_op_class(m);
++	return 0;
++}
++
++#ifdef RTW_HALMAC
++extern void rtw_halmac_get_version(char *str, u32 len);
++
++static int proc_get_halmac_info(struct seq_file *m, void *v)
++{
++	char ver[30] = {0};
++
++
++	rtw_halmac_get_version(ver, 30);
++	RTW_PRINT_SEL(m, "version: %s\n", ver);
++
++	return 0;
++}
++#endif
++
++/*
++* rtw_drv_proc:
++* init/deinit when register/unregister driver
++*/
++const struct rtw_proc_hdl drv_proc_hdls[] = {
++	RTW_PROC_HDL_SSEQ("ver_info", proc_get_drv_version, NULL),
++	RTW_PROC_HDL_SSEQ("log_level", proc_get_log_level, proc_set_log_level),
++	RTW_PROC_HDL_SSEQ("drv_cfg", proc_get_drv_cfg, NULL),
++#ifdef DBG_MEM_ALLOC
++	RTW_PROC_HDL_SSEQ("mstat", proc_get_mstat, NULL),
++#endif /* DBG_MEM_ALLOC */
++	RTW_PROC_HDL_SSEQ("country_chplan_map", proc_get_country_chplan_map, NULL),
++	RTW_PROC_HDL_SSEQ("chplan_id_list", proc_get_chplan_id_list, NULL),
++	RTW_PROC_HDL_SSEQ("chplan_test", proc_get_chplan_test, NULL),
++	RTW_PROC_HDL_SSEQ("chplan_ver", proc_get_chplan_ver, NULL),
++	RTW_PROC_HDL_SSEQ("global_op_class", proc_get_global_op_class, NULL),
++#ifdef RTW_HALMAC
++	RTW_PROC_HDL_SSEQ("halmac_info", proc_get_halmac_info, NULL),
++#endif /* RTW_HALMAC */
++};
++
++const int drv_proc_hdls_num = sizeof(drv_proc_hdls) / sizeof(struct rtw_proc_hdl);
++
++static int rtw_drv_proc_open(struct inode *inode, struct file *file)
++{
++	/* struct net_device *dev = proc_get_parent_data(inode); */
++	ssize_t index = (ssize_t)PDE_DATA(inode);
++	const struct rtw_proc_hdl *hdl = drv_proc_hdls + index;
++	void *private = NULL;
++
++	if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {
++		int res = seq_open(file, hdl->u.seq_op);
++
++		if (res == 0)
++			((struct seq_file *)file->private_data)->private = private;
++
++		return res;
++	} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {
++		int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;
++
++		return single_open(file, show, private);
++	} else if (hdl->type == RTW_PROC_HDL_TYPE_SZSEQ) {
++		int (*show)(struct seq_file *, void *) = hdl->u.sz.show ? hdl->u.sz.show : proc_get_dummy;
++
++		return single_open_size(file, show, private, hdl->u.sz.size);
++	} else {
++		return -EROFS;
++	}
++}
++
++static ssize_t rtw_drv_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)
++{
++	ssize_t index = (ssize_t)PDE_DATA(file_inode(file));
++	const struct rtw_proc_hdl *hdl = drv_proc_hdls + index;
++	ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;
++
++	if (write)
++		return write(file, buffer, count, pos, NULL);
++
++	return -EROFS;
++}
++
++static const struct file_operations rtw_drv_proc_seq_fops = {
++	.owner = THIS_MODULE,
++	.open = rtw_drv_proc_open,
++	.read = seq_read,
++	.llseek = seq_lseek,
++	.release = seq_release,
++	.write = rtw_drv_proc_write,
++};
++
++static const struct file_operations rtw_drv_proc_sseq_fops = {
++	.owner = THIS_MODULE,
++	.open = rtw_drv_proc_open,
++	.read = seq_read,
++	.llseek = seq_lseek,
++	.release = single_release,
++	.write = rtw_drv_proc_write,
++};
++
++int rtw_drv_proc_init(void)
++{
++	int ret = _FAIL;
++	ssize_t i;
++	struct proc_dir_entry *entry = NULL;
++
++	if (rtw_proc != NULL) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	rtw_proc = rtw_proc_create_dir(RTW_PROC_NAME, get_proc_net, NULL);
++
++	if (rtw_proc == NULL) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	for (i = 0; i < drv_proc_hdls_num; i++) {
++		if (drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)
++			entry = rtw_proc_create_entry(drv_proc_hdls[i].name, rtw_proc, &rtw_drv_proc_seq_fops, (void *)i);
++		else if (drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ ||
++			 drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SZSEQ)
++			entry = rtw_proc_create_entry(drv_proc_hdls[i].name, rtw_proc, &rtw_drv_proc_sseq_fops, (void *)i);
++		else
++			entry = NULL;
++
++		if (!entry) {
++			rtw_warn_on(1);
++			goto exit;
++		}
++	}
++
++	ret = _SUCCESS;
++
++exit:
++	return ret;
++}
++
++void rtw_drv_proc_deinit(void)
++{
++	int i;
++
++	if (rtw_proc == NULL)
++		return;
++
++	for (i = 0; i < drv_proc_hdls_num; i++)
++		remove_proc_entry(drv_proc_hdls[i].name, rtw_proc);
++
++	remove_proc_entry(RTW_PROC_NAME, get_proc_net);
++	rtw_proc = NULL;
++}
++
++#ifndef RTW_SEQ_FILE_TEST
++#define RTW_SEQ_FILE_TEST 0
++#endif
++
++#if RTW_SEQ_FILE_TEST
++#define RTW_SEQ_FILE_TEST_SHOW_LIMIT 300
++static void *proc_start_seq_file_test(struct seq_file *m, loff_t *pos)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_PRINT(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
++	if (*pos >= RTW_SEQ_FILE_TEST_SHOW_LIMIT) {
++		RTW_PRINT(FUNC_ADPT_FMT" pos:%llu, out of range return\n", FUNC_ADPT_ARG(adapter), *pos);
++		return NULL;
++	}
++
++	RTW_PRINT(FUNC_ADPT_FMT" return pos:%lld\n", FUNC_ADPT_ARG(adapter), *pos);
++	return pos;
++}
++void proc_stop_seq_file_test(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_PRINT(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
++}
++
++void *proc_next_seq_file_test(struct seq_file *m, void *v, loff_t *pos)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	(*pos)++;
++	if (*pos >= RTW_SEQ_FILE_TEST_SHOW_LIMIT) {
++		RTW_PRINT(FUNC_ADPT_FMT" pos:%lld, out of range return\n", FUNC_ADPT_ARG(adapter), *pos);
++		return NULL;
++	}
++
++	RTW_PRINT(FUNC_ADPT_FMT" return pos:%lld\n", FUNC_ADPT_ARG(adapter), *pos);
++	return pos;
++}
++
++static int proc_get_seq_file_test(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	u32 pos = *((loff_t *)(v));
++	RTW_PRINT(FUNC_ADPT_FMT" pos:%d\n", FUNC_ADPT_ARG(adapter), pos);
++	RTW_PRINT_SEL(m, FUNC_ADPT_FMT" pos:%d\n", FUNC_ADPT_ARG(adapter), pos);
++	return 0;
++}
++
++struct seq_operations seq_file_test = {
++	.start = proc_start_seq_file_test,
++	.stop  = proc_stop_seq_file_test,
++	.next  = proc_next_seq_file_test,
++	.show  = proc_get_seq_file_test,
++};
++#endif /* RTW_SEQ_FILE_TEST */
++
++#ifdef CONFIG_SDIO_HCI
++static int proc_get_sd_f0_reg_dump(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	sd_f0_reg_dump(m, adapter);
++
++	return 0;
++}
++
++static int proc_get_sdio_local_reg_dump(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	sdio_local_reg_dump(m, adapter);
++
++	return 0;
++}
++static int proc_get_sdio_card_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_sdio_card_info(m, adapter_to_dvobj(adapter));
++
++	return 0;
++}
++
++#ifdef DBG_SDIO
++static int proc_get_sdio_dbg(struct seq_file *m, void *v)
++{
++	struct net_device *dev;
++	struct _ADAPTER *a;
++	struct dvobj_priv *d;
++	struct sdio_data *sdio;
++
++
++	dev = m->private;
++	a = (struct _ADAPTER *)rtw_netdev_priv(dev);
++	d = adapter_to_dvobj(a);
++	sdio = &d->intf_data;
++
++	dump_sdio_card_info(m, d);
++
++	RTW_PRINT_SEL(m, "CMD52 error cnt: %d\n", sdio->cmd52_err_cnt);
++	RTW_PRINT_SEL(m, "CMD53 error cnt: %d\n", sdio->cmd53_err_cnt);
++
++#if (DBG_SDIO >= 3)
++	RTW_PRINT_SEL(m, "dbg: %s\n", sdio->dbg_enable?"enable":"disable");
++	RTW_PRINT_SEL(m, "err_stop: %s\n", sdio->err_stop?"enable":"disable");
++	RTW_PRINT_SEL(m, "err_test: %s\n", sdio->err_test?"enable":"disable");
++	RTW_PRINT_SEL(m, "err_test_triggered: %s\n",
++		      sdio->err_test_triggered?"yes":"no");
++#endif /* DBG_SDIO >= 3 */
++
++#if (DBG_SDIO >= 2)
++	RTW_PRINT_SEL(m, "I/O error dump mark: %d\n", sdio->reg_dump_mark);
++	if (sdio->reg_dump_mark) {
++		if (sdio->dbg_msg)
++			RTW_PRINT_SEL(m, "debug messages: %s\n", sdio->dbg_msg);
++		if (sdio->reg_mac)
++			RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, m, "MAC register:",
++					 _TRUE, sdio->reg_mac, 0x800);
++		if (sdio->reg_mac_ext)
++			RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, m, "MAC EXT register:",
++					 _TRUE, sdio->reg_mac_ext, 0x800);
++		if (sdio->reg_local)
++			RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, m, "SDIO Local register:",
++					 _TRUE, sdio->reg_local, 0x100);
++		if (sdio->reg_cia)
++			RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, m, "SDIO CIA register:",
++					 _TRUE, sdio->reg_cia, 0x200);
++	}
++#endif /* DBG_SDIO >= 2 */
++
++	return 0;
++}
++
++#if (DBG_SDIO >= 2)
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
++#define strnicmp	strncasecmp
++#endif /* Linux kernel >= 4.0.0 */
++void rtw_sdio_dbg_reg_free(struct dvobj_priv *d);
++#endif /* DBG_SDIO >= 2 */
++
++ssize_t proc_set_sdio_dbg(struct file *file, const char __user *buffer,
++			  size_t count, loff_t *pos, void *data)
++{
++#if (DBG_SDIO >= 2)
++	struct net_device *dev = data;
++	struct dvobj_priv *d;
++	struct _ADAPTER *a;
++	struct sdio_data *sdio;
++	char tmp[32], cmd[32] = {0};
++	int num;
++
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	a = (struct _ADAPTER *)rtw_netdev_priv(dev);
++	d = adapter_to_dvobj(a);
++	sdio = &d->intf_data;
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		num = sscanf(tmp, "%s", cmd);
++
++		if (num >= 1) {
++			if (strnicmp(cmd, "reg_reset", 10) == 0) {
++				sdio->reg_dump_mark = 0;
++				goto exit;
++			}
++			if (strnicmp(cmd, "reg_free", 9) == 0) {
++				rtw_sdio_dbg_reg_free(d);
++				sdio->reg_dump_mark = 0;
++				goto exit;
++			}
++#if (DBG_SDIO >= 3)
++			if (strnicmp(cmd, "dbg_enable", 11) == 0) {
++				sdio->dbg_enable = 1;
++				goto exit;
++			}
++			if (strnicmp(cmd, "dbg_disable", 12) == 0) {
++				sdio->dbg_enable = 0;
++				goto exit;
++			}
++			if (strnicmp(cmd, "err_stop", 9) == 0) {
++				sdio->err_stop = 1;
++				goto exit;
++			}
++			if (strnicmp(cmd, "err_stop_disable", 16) == 0) {
++				sdio->err_stop = 0;
++				goto exit;
++			}
++			if (strnicmp(cmd, "err_test", 9) == 0) {
++				sdio->err_test_triggered = 0;
++				sdio->err_test = 1;
++				goto exit;
++			}
++#endif /* DBG_SDIO >= 3 */
++		}
++
++		return -EINVAL;
++	}
++
++exit:
++#endif /* DBG_SDIO >= 2 */
++	return count;
++}
++#endif /* DBG_SDIO */
++#endif /* CONFIG_SDIO_HCI */
++
++static int proc_get_fw_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	rtw_dump_fw_info(m, adapter);
++	return 0;
++}
++static int proc_get_mac_reg_dump(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	mac_reg_dump(m, adapter);
++
++	return 0;
++}
++
++static int proc_get_bb_reg_dump(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	bb_reg_dump(m, adapter);
++
++	return 0;
++}
++
++static int proc_get_bb_reg_dump_ex(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	bb_reg_dump_ex(m, adapter);
++
++	return 0;
++}
++
++static int proc_get_rf_reg_dump(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	rf_reg_dump(m, adapter);
++
++	return 0;
++}
++
++#ifdef CONFIG_RTW_LED
++int proc_get_led_config(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_led_config(m, adapter);
++
++	return 0;
++}
++
++ssize_t proc_set_led_config(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	char tmp[32];
++	u8 strategy;
++	u8 iface_en_mask;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhu %hhx", &strategy, &iface_en_mask);
++
++		if (num >= 1)
++			rtw_led_set_strategy(adapter, strategy);
++		if (num >= 2)
++			rtw_led_set_iface_en_mask(adapter, iface_en_mask);
++	}
++
++	return count;
++}
++#endif /* CONFIG_RTW_LED */
++
++#ifdef CONFIG_AP_MODE
++int proc_get_aid_status(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_aid_status(m, adapter);
++
++	return 0;
++}
++
++ssize_t proc_set_aid_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct sta_priv *stapriv = &adapter->stapriv;
++
++	char tmp[32];
++	u8 rr;
++	u16 started_aid;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhu %hu", &rr, &started_aid);
++
++		if (num >= 1)
++			stapriv->rr_aid = rr ? 1 : 0;
++		if (num >= 2) {
++			started_aid = started_aid % (stapriv->max_aid + 1);
++			stapriv->started_aid = started_aid ? started_aid : 1;
++		}
++	}
++
++	return count;
++}
++
++int proc_get_ap_isolate(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_PRINT_SEL(m, "%d\n", adapter->mlmepriv.ap_isolate);
++
++	return 0;
++}
++
++ssize_t proc_set_ap_isolate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int ap_isolate;
++		int num = sscanf(tmp, "%d", &ap_isolate);
++
++		if (num >= 1)
++			adapter->mlmepriv.ap_isolate = ap_isolate ? 1 : 0;
++	}
++
++	return count;
++}
++
++#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++static int proc_get_ap_b2u_flags(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = rtw_netdev_priv(dev);
++
++	if (MLME_IS_AP(adapter))
++		dump_ap_b2u_flags(m, adapter);
++
++	return 0;
++}
++
++static ssize_t proc_set_ap_b2u_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = rtw_netdev_priv(dev);
++	char tmp[32];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		u8 src, fwd;
++		int num = sscanf(tmp, "%hhx %hhx", &src, &fwd);
++
++		if (num >= 1)
++			adapter->b2u_flags_ap_src = src;
++		if (num >= 2)
++			adapter->b2u_flags_ap_fwd = fwd;
++	}
++
++	return count;
++}
++#endif /* CONFIG_RTW_AP_DATA_BMC_TO_UC */
++#endif /* CONFIG_AP_MODE */
++
++static int proc_get_dump_tx_rate_bmp(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_tx_rate_bmp(m, adapter_to_dvobj(adapter));
++
++	return 0;
++}
++
++static int proc_get_dump_adapters_status(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_adapters_status(m, adapter_to_dvobj(adapter));
++
++	return 0;
++}
++
++#ifdef CONFIG_RTW_CUSTOMER_STR
++static int proc_get_customer_str(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	u8 cstr[RTW_CUSTOMER_STR_LEN];
++
++	rtw_ps_deny(adapter, PS_DENY_IOCTL);
++	if (rtw_pwr_wakeup(adapter) == _FAIL)
++		goto exit;
++
++	if (rtw_hal_customer_str_read(adapter, cstr) != _SUCCESS)
++		goto exit;
++
++	RTW_PRINT_SEL(m, RTW_CUSTOMER_STR_FMT"\n", RTW_CUSTOMER_STR_ARG(cstr));
++
++exit:
++	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
++	return 0;
++}
++#endif /* CONFIG_RTW_CUSTOMER_STR */
++
++#ifdef CONFIG_SCAN_BACKOP
++static int proc_get_backop_flags_sta(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++
++	RTW_PRINT_SEL(m, "0x%02x\n", mlmeext_scan_backop_flags_sta(mlmeext));
++
++	return 0;
++}
++
++static ssize_t proc_set_backop_flags_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++
++	char tmp[32];
++	u8 flags;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhx", &flags);
++
++		if (num == 1)
++			mlmeext_assign_scan_backop_flags_sta(mlmeext, flags);
++	}
++
++	return count;
++}
++
++#ifdef CONFIG_AP_MODE
++static int proc_get_backop_flags_ap(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++
++	RTW_PRINT_SEL(m, "0x%02x\n", mlmeext_scan_backop_flags_ap(mlmeext));
++
++	return 0;
++}
++
++static ssize_t proc_set_backop_flags_ap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++
++	char tmp[32];
++	u8 flags;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhx", &flags);
++
++		if (num == 1)
++			mlmeext_assign_scan_backop_flags_ap(mlmeext, flags);
++	}
++
++	return count;
++}
++#endif /* CONFIG_AP_MODE */
++
++#ifdef CONFIG_RTW_MESH
++static int proc_get_backop_flags_mesh(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++
++	RTW_PRINT_SEL(m, "0x%02x\n", mlmeext_scan_backop_flags_mesh(mlmeext));
++
++	return 0;
++}
++
++static ssize_t proc_set_backop_flags_mesh(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++
++	char tmp[32];
++	u8 flags;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhx", &flags);
++
++		if (num == 1)
++			mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags);
++	}
++
++	return count;
++}
++#endif /* CONFIG_RTW_MESH */
++
++#endif /* CONFIG_SCAN_BACKOP */
++
++#if defined(CONFIG_LPS_PG) && defined(CONFIG_RTL8822C)
++static int proc_get_lps_pg_debug(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = rtw_netdev_priv(dev);
++	struct dm_struct *dm = adapter_to_phydm(adapter);
++
++	rtw_run_in_thread_cmd(adapter, ((void *)(odm_lps_pg_debug_8822c)), dm);
++
++	return 0;
++}
++#endif
++
++/* gpio setting */
++#ifdef CONFIG_GPIO_API
++static ssize_t proc_set_config_gpio(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32] = {0};
++	int num = 0, gpio_pin = 0, gpio_mode = 0; /* gpio_mode:0 input  1:output; */
++
++	if (count < 2)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		num	= sscanf(tmp, "%d %d", &gpio_pin, &gpio_mode);
++		RTW_INFO("num=%d gpio_pin=%d mode=%d\n", num, gpio_pin, gpio_mode);
++		padapter->pre_gpio_pin = gpio_pin;
++
++		if (gpio_mode == 0 || gpio_mode == 1)
++			rtw_hal_config_gpio(padapter, gpio_pin, gpio_mode);
++	}
++	return count;
++
++}
++static ssize_t proc_set_gpio_output_value(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32] = {0};
++	int num = 0, gpio_pin = 0, pin_mode = 0; /* pin_mode: 1 high         0:low */
++
++	if (count < 2)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		num	= sscanf(tmp, "%d %d", &gpio_pin, &pin_mode);
++		RTW_INFO("num=%d gpio_pin=%d pin_high=%d\n", num, gpio_pin, pin_mode);
++		padapter->pre_gpio_pin = gpio_pin;
++
++		if (pin_mode == 0 || pin_mode == 1)
++			rtw_hal_set_gpio_output_value(padapter, gpio_pin, pin_mode);
++	}
++	return count;
++}
++static int proc_get_gpio(struct seq_file *m, void *v)
++{
++	u8 gpioreturnvalue = 0;
++	struct net_device *dev = m->private;
++
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	if (!padapter)
++		return -EFAULT;
++	gpioreturnvalue = rtw_hal_get_gpio(padapter, padapter->pre_gpio_pin);
++	RTW_PRINT_SEL(m, "get_gpio %d:%d\n", padapter->pre_gpio_pin, gpioreturnvalue);
++
++	return 0;
++
++}
++static ssize_t proc_set_gpio(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32] = {0};
++	int num = 0, gpio_pin = 0;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		num	= sscanf(tmp, "%d", &gpio_pin);
++		RTW_INFO("num=%d gpio_pin=%d\n", num, gpio_pin);
++		padapter->pre_gpio_pin = gpio_pin;
++
++	}
++	return count;
++}
++#endif
++
++static ssize_t proc_set_rx_info_msg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct recv_priv *precvpriv = &(padapter->recvpriv);
++	char tmp[32] = {0};
++	int phy_info_flag = 0;
++
++	if (!padapter)
++		return -EFAULT;
++
++	if (count < 1) {
++		RTW_INFO("argument size is less than 1\n");
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%d", &phy_info_flag);
++
++		if (num == 1)
++			precvpriv->store_law_data_flag = (BOOLEAN) phy_info_flag;
++
++		/*RTW_INFO("precvpriv->store_law_data_flag = %d\n",( BOOLEAN )(precvpriv->store_law_data_flag));*/
++	}
++	return count;
++}
++static int proc_get_rx_info_msg(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	rtw_hal_set_odm_var(padapter, HAL_ODM_RX_Dframe_INFO, m, _FALSE);
++	return 0;
++}
++static int proc_get_tx_info_msg(struct seq_file *m, void *v)
++{
++	_irqL irqL;
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct sta_info *psta;
++	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
++	u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct sta_priv *pstapriv = &padapter->stapriv;
++	int i;
++	_list	*plist, *phead;
++	u8 current_rate_id = 0, current_sgi = 0;
++
++	char *BW, *status;
++
++	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++	if (MLME_IS_STA(padapter))
++		status = "station mode";
++	else if (MLME_IS_AP(padapter))
++		status = "AP mode";
++	else if (MLME_IS_MESH(padapter))
++		status = "mesh mode";
++	else
++		status = " ";
++	_RTW_PRINT_SEL(m, "status=%s\n", status);
++	for (i = 0; i < NUM_STA; i++) {
++		phead = &(pstapriv->sta_hash[i]);
++		plist = get_next(phead);
++
++		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
++
++			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
++
++			plist = get_next(plist);
++
++			if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)  !=  _TRUE)
++				&& (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE)
++				&& (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN) != _TRUE)) {
++
++				switch (psta->cmn.bw_mode) {
++
++				case CHANNEL_WIDTH_20:
++					BW = "20M";
++					break;
++
++				case CHANNEL_WIDTH_40:
++					BW = "40M";
++					break;
++
++				case CHANNEL_WIDTH_80:
++					BW = "80M";
++					break;
++
++				case CHANNEL_WIDTH_160:
++					BW = "160M";
++					break;
++
++				default:
++					BW = "";
++					break;
++				}
++				current_rate_id = rtw_get_current_tx_rate(adapter, psta);
++				current_sgi = rtw_get_current_tx_sgi(adapter, psta);
++
++				RTW_PRINT_SEL(m, "==============================\n");
++				_RTW_PRINT_SEL(m, "macaddr=" MAC_FMT"\n", MAC_ARG(psta->cmn.mac_addr));
++				_RTW_PRINT_SEL(m, "Tx_Data_Rate=%s\n", HDATA_RATE(current_rate_id));
++				_RTW_PRINT_SEL(m, "BW=%s,sgi=%u\n", BW, current_sgi);
++
++			}
++		}
++	}
++
++	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
++
++	return 0;
++
++}
++
++
++static int proc_get_linked_info_dump(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	if (padapter)
++		RTW_PRINT_SEL(m, "linked_info_dump :%s\n", (padapter->bLinkInfoDump) ? "enable" : "disable");
++
++	return 0;
++}
++
++
++static ssize_t proc_set_linked_info_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	char tmp[32] = {0};
++	int mode = 0, pre_mode = 0;
++	int num = 0;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	pre_mode = padapter->bLinkInfoDump;
++	RTW_INFO("pre_mode=%d\n", pre_mode);
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		num	= sscanf(tmp, "%d ", &mode);
++		RTW_INFO("num=%d mode=%d\n", num, mode);
++
++		if (num != 1) {
++			RTW_INFO("argument number is wrong\n");
++			return -EFAULT;
++		}
++
++		if (mode == 1 || (mode == 0 && pre_mode == 1)) /* not consider pwr_saving 0: */
++			padapter->bLinkInfoDump = mode;
++
++		else if ((mode == 2) || (mode == 0 && pre_mode == 2)) { /* consider power_saving */
++			/* RTW_INFO("linked_info_dump =%s\n", (padapter->bLinkInfoDump)?"enable":"disable") */
++			linked_info_dump(padapter, mode);
++		}
++	}
++	return count;
++}
++
++
++static int proc_get_sta_tp_dump(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (padapter)
++		RTW_PRINT_SEL(m, "sta_tp_dump :%s\n", (padapter->bsta_tp_dump) ? "enable" : "disable");
++
++	return 0;
++}
++
++static ssize_t proc_set_sta_tp_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	char tmp[32] = {0};
++	int mode = 0;
++	int num = 0;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		num	= sscanf(tmp, "%d ", &mode);
++
++		if (num != 1) {
++			RTW_INFO("argument number is wrong\n");
++			return -EFAULT;
++		}
++		if (padapter)
++			padapter->bsta_tp_dump = mode;
++	}
++	return count;
++}
++
++static int proc_get_sta_tp_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (padapter)
++		rtw_sta_traffic_info(m, padapter);
++
++	return 0;
++}
++
++static int proc_get_turboedca_ctrl(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
++
++	if (hal_data) {
++
++		u32 edca_param;
++
++		if (hal_data->dis_turboedca == 0)
++			RTW_PRINT_SEL(m, "Turbo-EDCA : %s\n", "Enable");
++		else
++			RTW_PRINT_SEL(m, "Turbo-EDCA : %s, mode=%d, edca_param_mode=0x%x\n", "Disable", hal_data->dis_turboedca, hal_data->edca_param_mode);
++
++
++		rtw_hal_get_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
++
++		_RTW_PRINT_SEL(m, "PARAM_BE:0x%x\n", edca_param);
++
++	}
++
++	return 0;
++}
++
++static ssize_t proc_set_turboedca_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
++	char tmp[32] = {0};
++	int mode = 0, num = 0;
++	u32 param_mode = 0;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp))
++		return -EFAULT;
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		num = sscanf(tmp, "%d %x", &mode, &param_mode);
++
++		if (num < 1 || num > 2) {
++			RTW_INFO("argument number is wrong\n");
++			return -EFAULT;
++		}
++
++		/*  0: enable turboedca,
++			1: disable turboedca,
++			2: disable turboedca and setting EDCA parameter based on the input parameter
++			> 2 : currently reset to 0 */
++
++		if (mode > 2)
++			mode = 0;
++
++		hal_data->dis_turboedca = mode;
++
++		hal_data->edca_param_mode = 0; /* init. value */
++
++		RTW_INFO("dis_turboedca mode = 0x%x\n", hal_data->dis_turboedca);
++
++		if (num == 2) {
++
++			hal_data->edca_param_mode = param_mode;
++
++			RTW_INFO("param_mode = 0x%x\n", param_mode);
++		}
++
++	}
++
++	return count;
++
++}
++
++static int proc_get_mac_qinfo(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	rtw_hal_get_hwreg(adapter, HW_VAR_DUMP_MAC_QUEUE_INFO, (u8 *)m);
++
++	return 0;
++}
++
++int proc_get_wifi_spec(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv	*pregpriv = &padapter->registrypriv;
++
++	RTW_PRINT_SEL(m, "wifi_spec=%d\n", pregpriv->wifi_spec);
++	return 0;
++}
++
++static int proc_get_chan_plan(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_cur_chset(m, adapter_to_rfctl(adapter));
++
++	return 0;
++}
++
++static ssize_t proc_set_chan_plan(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u8 chan_plan = RTW_CHPLAN_UNSPECIFIED;
++
++	if (!padapter)
++		return -EFAULT;
++
++	if (count < 1) {
++		RTW_INFO("argument size is less than 1\n");
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%hhx", &chan_plan);
++		if (num !=  1)
++			return count;
++	}
++
++	rtw_set_channel_plan(padapter, chan_plan);
++
++	return count;
++}
++
++static int proc_get_country_code(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++
++	if (rfctl->country_ent)
++		dump_country_chplan(m, rfctl->country_ent);
++	else
++		RTW_PRINT_SEL(m, "unspecified\n");
++
++	return 0;
++}
++
++static ssize_t proc_set_country_code(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	char alpha2[2];
++	int num;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (!buffer || copy_from_user(tmp, buffer, count))
++		goto exit;
++
++	num = sscanf(tmp, "%c%c", &alpha2[0], &alpha2[1]);
++	if (num !=	2)
++		return count;
++
++	rtw_set_country(padapter, alpha2);
++
++exit:
++	return count;
++}
++
++static int proc_get_cap_spt_op_class_ch(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_cap_spt_op_class_ch(m , adapter_to_rfctl(adapter), 0);
++	return 0;
++}
++
++static int proc_get_cur_spt_op_class_ch(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_cur_spt_op_class_ch(m , adapter_to_rfctl(adapter), 0);
++
++	return 0;
++}
++
++#if CONFIG_RTW_MACADDR_ACL
++static int proc_get_macaddr_acl(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_macaddr_acl(m, adapter);
++	return 0;
++}
++
++ssize_t proc_set_macaddr_acl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[17 * NUM_ACL + 32] = {0};
++	u8 period;
++	char cmd[32];
++	u8 mode;
++	u8 addr[ETH_ALEN];
++
++#define MAC_ACL_CMD_MODE	0
++#define MAC_ACL_CMD_ADD		1
++#define MAC_ACL_CMD_DEL		2
++#define MAC_ACL_CMD_CLR		3
++#define MAC_ACL_CMD_NUM		4
++
++	static const char * const mac_acl_cmd_str[] = {
++		"mode",
++		"add",
++		"del",
++		"clr",
++	};
++	u8 cmd_id = MAC_ACL_CMD_NUM;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		/*
++		* <period> mode <mode> <macaddr> [<macaddr>]
++		* <period> mode <mode>
++		* <period> add <macaddr> [<macaddr>]
++		* <period> del <macaddr> [<macaddr>]
++		* <period> clr
++		*/
++		char *c, *next;
++		int i;
++		u8 is_bcast;
++
++		next = tmp;
++		c = strsep(&next, " \t");
++		if (!c || sscanf(c, "%hhu", &period) != 1)
++			goto exit;
++
++		if (period >= RTW_ACL_PERIOD_NUM) {
++			RTW_WARN(FUNC_ADPT_FMT" invalid period:%u", FUNC_ADPT_ARG(adapter), period);
++			goto exit;
++		}
++
++		c = strsep(&next, " \t");
++		if (!c || sscanf(c, "%s", cmd) != 1)
++			goto exit;
++
++		for (i = 0; i < MAC_ACL_CMD_NUM; i++)
++			if (strcmp(mac_acl_cmd_str[i], cmd) == 0)
++				cmd_id = i;
++
++		switch (cmd_id) {
++		case MAC_ACL_CMD_MODE:
++			c = strsep(&next, " \t");
++			if (!c || sscanf(c, "%hhu", &mode) != 1)
++				goto exit;
++
++			if (mode >= RTW_ACL_MODE_MAX) {
++				RTW_WARN(FUNC_ADPT_FMT" invalid mode:%u", FUNC_ADPT_ARG(adapter), mode);
++				goto exit;
++			}
++			break;
++
++		case MAC_ACL_CMD_ADD:
++		case MAC_ACL_CMD_DEL:
++			break;
++
++		case MAC_ACL_CMD_CLR:
++			/* clear settings */
++			rtw_macaddr_acl_clear(adapter, period);
++			goto exit;
++
++		default:
++			RTW_WARN(FUNC_ADPT_FMT" invalid cmd:\"%s\"", FUNC_ADPT_ARG(adapter), cmd);
++			goto exit;
++		}
++
++		/* check for macaddr list */
++		c = strsep(&next, " \t");
++		if (!c && cmd_id == MAC_ACL_CMD_MODE) {
++			/* set mode only  */
++			rtw_set_macaddr_acl(adapter, period, mode);
++			goto exit;
++		}
++
++		if (cmd_id == MAC_ACL_CMD_MODE) {
++			/* set mode and entire macaddr list */
++			rtw_macaddr_acl_clear(adapter, period);
++			rtw_set_macaddr_acl(adapter, period, mode);
++		}
++
++		while (c != NULL) {
++			if (sscanf(c, MAC_SFMT, MAC_SARG(addr)) != 6)
++				break;
++
++			is_bcast = is_broadcast_mac_addr(addr);
++			if (is_bcast
++				|| rtw_check_invalid_mac_address(addr, 0) == _FALSE
++			) {
++				if (cmd_id == MAC_ACL_CMD_DEL) {
++					rtw_acl_remove_sta(adapter, period, addr);
++					if (is_bcast)
++						break;
++				 } else if (!is_bcast)
++					rtw_acl_add_sta(adapter, period, addr);
++			}
++
++			c = strsep(&next, " \t");
++		}
++	}
++
++exit:
++	return count;
++}
++#endif /* CONFIG_RTW_MACADDR_ACL */
++
++#if CONFIG_RTW_PRE_LINK_STA
++static int proc_get_pre_link_sta(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_pre_link_sta_ctl(m, &adapter->stapriv);
++	return 0;
++}
++
++ssize_t proc_set_pre_link_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
++	char tmp[17 * RTW_PRE_LINK_STA_NUM + 32] = {0};
++	char arg0[16] = {0};
++	u8 addr[ETH_ALEN];
++
++#define PRE_LINK_STA_CMD_RESET	0
++#define PRE_LINK_STA_CMD_ADD	1
++#define PRE_LINK_STA_CMD_DEL	2
++#define PRE_LINK_STA_CMD_NUM	3
++
++	static const char * const pre_link_sta_cmd_str[] = {
++		"reset",
++		"add",
++		"del"
++	};
++	u8 cmd_id = PRE_LINK_STA_CMD_NUM;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		/* cmd [<macaddr>] */
++		char *c, *next;
++		int i;
++
++		next = tmp;
++		c = strsep(&next, " \t");
++
++		if (sscanf(c, "%s", arg0) != 1)
++			goto exit;
++
++		for (i = 0; i < PRE_LINK_STA_CMD_NUM; i++)
++			if (strcmp(pre_link_sta_cmd_str[i], arg0) == 0)
++				cmd_id = i;
++
++		switch (cmd_id) {
++		case PRE_LINK_STA_CMD_RESET:
++			rtw_pre_link_sta_ctl_reset(&adapter->stapriv);
++			goto exit;
++		case PRE_LINK_STA_CMD_ADD:
++		case PRE_LINK_STA_CMD_DEL:
++			break;
++		default:
++			goto exit;
++		}
++
++		/* macaddr list */
++		c = strsep(&next, " \t");
++		while (c != NULL) {
++			if (sscanf(c, MAC_SFMT, MAC_SARG(addr)) != 6)
++				break;
++
++			if (rtw_check_invalid_mac_address(addr, 0) == _FALSE) {
++				if (cmd_id == PRE_LINK_STA_CMD_ADD)
++					rtw_pre_link_sta_add(&adapter->stapriv, addr);
++				else
++					rtw_pre_link_sta_del(&adapter->stapriv, addr);
++			}
++
++			c = strsep(&next, " \t");
++		}
++	}
++
++exit:
++	return count;
++}
++#endif /* CONFIG_RTW_PRE_LINK_STA */
++
++static int proc_get_ch_sel_policy(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++
++	RTW_PRINT_SEL(m, "%-16s\n", "within_same_band");
++
++	RTW_PRINT_SEL(m, "%16d\n", rfctl->ch_sel_within_same_band);
++
++	return 0;
++}
++
++static ssize_t proc_set_ch_sel_policy(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	char tmp[32];
++	u8 within_sb;
++	int num;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (!buffer || copy_from_user(tmp, buffer, count))
++		goto exit;
++
++	num = sscanf(tmp, "%hhu", &within_sb);
++	if (num >=	1)
++		rfctl->ch_sel_within_same_band = within_sb ? 1 : 0;
++
++exit:
++	return count;
++}
++
++#ifdef CONFIG_DFS_MASTER
++static int proc_get_dfs_test_case(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++
++	RTW_PRINT_SEL(m, "%-24s %-19s\n", "radar_detect_trigger_non", "choose_dfs_ch_first");
++	RTW_PRINT_SEL(m, "%24hhu %19hhu\n"
++		, rfctl->dbg_dfs_radar_detect_trigger_non
++		, rfctl->dbg_dfs_choose_dfs_ch_first
++	);
++
++	return 0;
++}
++
++static ssize_t proc_set_dfs_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	char tmp[32];
++	u8 radar_detect_trigger_non;
++	u8 choose_dfs_ch_first;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%hhu %hhu", &radar_detect_trigger_non, &choose_dfs_ch_first);
++
++		if (num >= 1)
++			rfctl->dbg_dfs_radar_detect_trigger_non = radar_detect_trigger_non;
++		if (num >= 2)
++			rfctl->dbg_dfs_choose_dfs_ch_first = choose_dfs_ch_first;
++	}
++
++	return count;
++}
++
++ssize_t proc_set_update_non_ocp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	char tmp[32];
++	u8 ch, bw = CHANNEL_WIDTH_20, offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++	int ms = -1;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhu %hhu %hhu %d", &ch, &bw, &offset, &ms);
++
++		if (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3))
++			goto exit;
++
++		if (bw == CHANNEL_WIDTH_20)
++			rtw_chset_update_non_ocp_ms(rfctl->channel_set
++				, ch, bw, HAL_PRIME_CHNL_OFFSET_DONT_CARE, ms);
++		else
++			rtw_chset_update_non_ocp_ms(rfctl->channel_set
++				, ch, bw, offset, ms);
++	}
++
++exit:
++	return count;
++}
++
++ssize_t proc_set_radar_detect(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	char tmp[32];
++	u8 fake_radar_detect_cnt = 0;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhu", &fake_radar_detect_cnt);
++
++		if (num < 1)
++			goto exit;
++
++		rfctl->dbg_dfs_fake_radar_detect_cnt = fake_radar_detect_cnt;
++	}
++
++exit:
++	return count;
++}
++
++static int proc_get_dfs_ch_sel_d_flags(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++
++	RTW_PRINT_SEL(m, "0x%02x\n", rfctl->dfs_ch_sel_d_flags);
++
++	return 0;
++}
++
++static ssize_t proc_set_dfs_ch_sel_d_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	char tmp[32];
++	u8 d_flags;
++	int num;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (!buffer || copy_from_user(tmp, buffer, count))
++		goto exit;
++
++	num = sscanf(tmp, "%hhx", &d_flags);
++	if (num != 1)
++		goto exit;
++
++	rfctl->dfs_ch_sel_d_flags = d_flags;
++
++exit:
++	return count;
++}
++
++#if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
++static int proc_get_dfs_slave_with_rd(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++
++	RTW_PRINT_SEL(m, "%u\n", rfctl->dfs_slave_with_rd);
++
++	return 0;
++}
++
++static ssize_t proc_set_dfs_slave_with_rd(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++	char tmp[32];
++	u8 rd;
++	int num;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (!buffer || copy_from_user(tmp, buffer, count))
++		goto exit;
++
++	num = sscanf(tmp, "%hhu", &rd);
++	if (num != 1)
++		goto exit;
++
++	rd = rd ? 1 : 0;
++
++	if (rfctl->dfs_slave_with_rd != rd) {
++		rfctl->dfs_slave_with_rd = rd;
++		rtw_dfs_rd_en_decision_cmd(adapter);
++	}
++
++exit:
++	return count;
++}
++#endif /* CONFIG_DFS_SLAVE_WITH_RADAR_DETECT */
++#endif /* CONFIG_DFS_MASTER */
++
++#ifdef CONFIG_80211N_HT
++int proc_get_rx_ampdu_size_limit(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_regsty_rx_ampdu_size_limit(m, adapter);
++
++	return 0;
++}
++
++ssize_t proc_set_rx_ampdu_size_limit(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv *regsty = adapter_to_regsty(adapter);
++	char tmp[32];
++	u8 nss;
++	u8 limit_by_bw[4] = {0xFF};
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int i;
++		int num = sscanf(tmp, "%hhu %hhu %hhu %hhu %hhu"
++			, &nss, &limit_by_bw[0], &limit_by_bw[1], &limit_by_bw[2], &limit_by_bw[3]);
++
++		if (num < 2)
++			goto exit;
++		if (nss == 0 || nss > 4)
++			goto exit;
++
++		for (i = 0; i < num - 1; i++)
++			regsty->rx_ampdu_sz_limit_by_nss_bw[nss - 1][i] = limit_by_bw[i];
++
++		rtw_rx_ampdu_apply(adapter);
++	}
++
++exit:
++	return count;
++}
++#endif /* CONFIG_80211N_HT */
++
++static int proc_get_rx_chk_limit(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_PRINT_SEL(m, "Rx chk limit : %d\n", rtw_get_rx_chk_limit(padapter));
++
++	return 0;
++}
++
++static ssize_t proc_set_rx_chk_limit(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	char tmp[32];
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	int rx_chk_limit;
++
++	if (count < 1) {
++		RTW_INFO("argument size is less than 1\n");
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%d", &rx_chk_limit);
++
++		rtw_set_rx_chk_limit(padapter, rx_chk_limit);
++	}
++
++	return count;
++}
++
++static int proc_get_udpport(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct recv_priv *precvpriv = &(padapter->recvpriv);
++
++	RTW_PRINT_SEL(m, "%d\n", precvpriv->sink_udpport);
++	return 0;
++}
++static ssize_t proc_set_udpport(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct recv_priv *precvpriv = &(padapter->recvpriv);
++	int sink_udpport = 0;
++	char tmp[32];
++
++
++	if (!padapter)
++		return -EFAULT;
++
++	if (count < 1) {
++		RTW_INFO("argument size is less than 1\n");
++		return -EFAULT;
++	}
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%d", &sink_udpport);
++
++		if (num !=  1) {
++			RTW_INFO("invalid input parameter number!\n");
++			return count;
++		}
++
++	}
++	precvpriv->sink_udpport = sink_udpport;
++
++	return count;
++
++}
++
++static int proc_get_mi_ap_bc_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++	u8 i;
++
++	for (i = 0; i < dvobj->iface_nums; i++)
++		RTW_PRINT_SEL(m, "iface_id:%d, mac_id && sec_cam_id = %d\n", i, macid_ctl->iface_bmc[i]);
++
++	return 0;
++}
++static int proc_get_macid_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
++	u8 i;
++	u8 null_addr[ETH_ALEN] = {0};
++	u8 *macaddr;
++
++	RTW_PRINT_SEL(m, "max_num:%u\n", macid_ctl->num);
++	RTW_PRINT_SEL(m, "\n");
++
++	RTW_PRINT_SEL(m, "used:\n");
++	dump_macid_map(m, &macid_ctl->used, macid_ctl->num);
++	RTW_PRINT_SEL(m, "\n");
++
++	RTW_PRINT_SEL(m, "%-3s %-3s %-5s %-4s %-17s %-6s %-3s"
++		, "id", "bmc", "ifbmp", "ch_g", "macaddr", "bw", "vht");
++
++	if (GET_HAL_TX_NSS(adapter) > 2)
++		_RTW_PRINT_SEL(m, " %-10s", "rate_bmp1");
++
++	_RTW_PRINT_SEL(m, " %-10s %s\n", "rate_bmp0", "status");
++
++	for (i = 0; i < macid_ctl->num; i++) {
++		if (rtw_macid_is_used(macid_ctl, i)
++			|| macid_ctl->h2c_msr[i]
++		) {
++			if (macid_ctl->sta[i])
++				macaddr = macid_ctl->sta[i]->cmn.mac_addr;
++			else
++				macaddr = null_addr;
++
++			RTW_PRINT_SEL(m, "%3u %3u  0x%02x %4d "MAC_FMT" %6s %3u"
++				, i
++				, rtw_macid_is_bmc(macid_ctl, i)
++				, rtw_macid_get_iface_bmp(macid_ctl, i)
++				, rtw_macid_get_ch_g(macid_ctl, i)
++				, MAC_ARG(macaddr)
++				, ch_width_str(macid_ctl->bw[i])
++				, macid_ctl->vht_en[i]
++			);
++
++			if (GET_HAL_TX_NSS(adapter) > 2)
++				_RTW_PRINT_SEL(m, " 0x%08X", macid_ctl->rate_bmp1[i]);
++
++			_RTW_PRINT_SEL(m, " 0x%08X "H2C_MSR_FMT" %s\n"
++				, macid_ctl->rate_bmp0[i]
++				, H2C_MSR_ARG(&macid_ctl->h2c_msr[i])
++				, rtw_macid_is_used(macid_ctl, i) ? "" : "[unused]"
++			);
++		}
++	}
++	RTW_PRINT_SEL(m, "\n");
++
++	for (i = 0; i < H2C_MSR_ROLE_MAX; i++) {
++		if (macid_ctl->op_num[i]) {
++			RTW_PRINT_SEL(m, "%-5s op_num:%u\n"
++				, h2c_msr_role_str(i), macid_ctl->op_num[i]);
++		}
++	}
++
++	return 0;
++}
++
++static int proc_get_sec_cam(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++
++	RTW_PRINT_SEL(m, "sec_cap:0x%02x\n", cam_ctl->sec_cap);
++	RTW_PRINT_SEL(m, "flags:0x%08x\n", cam_ctl->flags);
++	RTW_PRINT_SEL(m, "\n");
++
++	RTW_PRINT_SEL(m, "max_num:%u\n", cam_ctl->num);
++	RTW_PRINT_SEL(m, "used:\n");
++	dump_sec_cam_map(m, &cam_ctl->used, cam_ctl->num);
++	RTW_PRINT_SEL(m, "\n");
++
++	RTW_PRINT_SEL(m, "reg_scr:0x%04x\n", rtw_read16(adapter, 0x680));
++	RTW_PRINT_SEL(m, "\n");
++
++	dump_sec_cam(m, adapter);
++
++	return 0;
++}
++
++static ssize_t proc_set_sec_cam(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
++	char tmp[32] = {0};
++	char cmd[4];
++	u8 id_1 = 0, id_2 = 0;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		/* c <id_1>: clear specific cam entry */
++		/* wfc <id_1>: write specific cam entry from cam cache */
++		/* sw <id_1> <id_2>: sec_cam 1/2 swap */
++
++		int num = sscanf(tmp, "%s %hhu %hhu", cmd, &id_1, &id_2);
++
++		if (num < 2)
++			return count;
++
++		if ((id_1 >= cam_ctl->num) || (id_2 >= cam_ctl->num)) {
++			RTW_ERR(FUNC_ADPT_FMT" invalid id_1:%u id_2:%u\n", FUNC_ADPT_ARG(adapter), id_1, id_2);
++			return count;
++		}
++
++		if (strcmp("c", cmd) == 0) {
++			_clear_cam_entry(adapter, id_1);
++			adapter->securitypriv.hw_decrypted = _FALSE; /* temporarily set this for TX path to use SW enc */
++		} else if (strcmp("wfc", cmd) == 0)
++			write_cam_from_cache(adapter, id_1);
++		else if (strcmp("sw", cmd) == 0)
++			rtw_sec_cam_swap(adapter, id_1, id_2);
++		else if (strcmp("cdk", cmd) == 0)
++			rtw_clean_dk_section(adapter);
++#ifdef DBG_SEC_CAM_MOVE
++		else if (strcmp("sgd", cmd) == 0)
++			rtw_hal_move_sta_gk_to_dk(adapter);
++		else if (strcmp("rsd", cmd) == 0)
++			rtw_hal_read_sta_dk_key(adapter, id_1);
++#endif
++	}
++
++	return count;
++}
++
++static int proc_get_sec_cam_cache(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_sec_cam_cache(m, adapter);
++	return 0;
++}
++
++static ssize_t proc_set_change_bss_chbw(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	int i;
++	char tmp[32];
++	s16 ch;
++	s8 bw = REQ_BW_NONE, offset = REQ_OFFSET_NONE;
++	u8 ifbmp = 0;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hd %hhd %hhd %hhx", &ch, &bw, &offset, &ifbmp);
++
++		if (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3))
++			goto exit;
++
++		if (num < 4)
++			ifbmp = BIT(adapter->iface_id);
++		else
++			ifbmp &= (1 << dvobj->iface_nums) - 1;
++
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
++				continue;
++
++			if (!CHK_MLME_STATE(dvobj->padapters[i], WIFI_AP_STATE | WIFI_MESH_STATE)
++				|| !MLME_IS_ASOC(dvobj->padapters[i]))
++				ifbmp &= ~BIT(i);
++		}
++
++		if (ifbmp)
++			rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_WAIT_ACK, ifbmp, 0, ch, bw, offset);
++	}
++
++exit:
++	return count;
++}
++
++#if CONFIG_TX_AC_LIFETIME
++static int proc_get_tx_aclt_force_val(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++	dump_tx_aclt_force_val(m, dvobj);
++
++	return 0;
++}
++
++static ssize_t proc_set_tx_aclt_force_val(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = rtw_netdev_priv(dev);
++	char tmp[32] = {0};
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++		struct tx_aclt_conf_t input;
++		int num = sscanf(tmp, "%hhx %u %u", &input.en, &input.vo_vi, &input.be_bk);
++
++		if (num < 1)
++			return count;
++
++		rtw_hal_set_tx_aclt_force_val(adapter, &input, num);
++		rtw_run_in_thread_cmd(adapter, ((void *)(rtw_hal_update_tx_aclt)), adapter);
++	}
++
++	return count;
++}
++
++static int proc_get_tx_aclt_flags(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++	RTW_PRINT_SEL(m, "0x%02x\n", dvobj->tx_aclt_flags);
++
++	return 0;
++}
++
++static ssize_t proc_set_tx_aclt_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = rtw_netdev_priv(dev);
++	char tmp[32] = {0};
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++		u8 flags;
++		int num = sscanf(tmp, "%hhx", &flags);
++
++		if (num < 1)
++			return count;
++
++		if (dvobj->tx_aclt_flags == flags)
++			return count;
++
++		dvobj->tx_aclt_flags = flags;
++
++		rtw_run_in_thread_cmd(adapter, ((void *)(rtw_hal_update_tx_aclt)), adapter);
++	}
++
++	return count;
++}
++
++static int proc_get_tx_aclt_confs(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++	RTW_PRINT_SEL(m, "flags:0x%02x\n", dvobj->tx_aclt_flags);
++	dump_tx_aclt_confs(m, dvobj);
++
++	return 0;
++}
++
++static ssize_t proc_set_tx_aclt_confs(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = rtw_netdev_priv(dev);
++	char tmp[32] = {0};
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++		u8 id;
++		struct tx_aclt_conf_t input;
++		int num = sscanf(tmp, "%hhu %hhx %u %u", &id, &input.en, &input.vo_vi, &input.be_bk);
++
++		if (num < 2)
++			return count;
++
++		rtw_hal_set_tx_aclt_conf(adapter, id, &input, num - 1);
++		rtw_run_in_thread_cmd(adapter, ((void *)(rtw_hal_update_tx_aclt)), adapter);
++	}
++
++	return count;
++}
++#endif /* CONFIG_TX_AC_LIFETIME */
++
++static int proc_get_tx_bw_mode(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	RTW_PRINT_SEL(m, "0x%02x\n", adapter->driver_tx_bw_mode);
++	RTW_PRINT_SEL(m, "2.4G:%s\n", ch_width_str(ADAPTER_TX_BW_2G(adapter)));
++	RTW_PRINT_SEL(m, "5G:%s\n", ch_width_str(ADAPTER_TX_BW_5G(adapter)));
++
++	return 0;
++}
++
++static void rtw_set_tx_bw_mode(struct _ADAPTER *adapter, u8 bw_mode)
++{
++	struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv);
++	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
++	u8 update = _FALSE;
++
++	if ((MLME_STATE(adapter) & WIFI_ASOC_STATE)
++		&& ((mlmeext->cur_channel <= 14 && BW_MODE_2G(bw_mode) != ADAPTER_TX_BW_2G(adapter))
++			|| (mlmeext->cur_channel >= 36 && BW_MODE_5G(bw_mode) != ADAPTER_TX_BW_5G(adapter)))
++	) {
++		/* RA mask update needed */
++		update = _TRUE;
++	}
++	adapter->driver_tx_bw_mode = bw_mode;
++
++	if (update == _TRUE) {
++		struct sta_info *sta;
++		int i;
++
++		for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
++			sta = macid_ctl->sta[i];
++			if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr))
++				rtw_dm_ra_mask_wk_cmd(adapter, (u8 *)sta);
++		}
++	}
++}
++
++static ssize_t proc_set_tx_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u8 bw_mode;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhx", &bw_mode);
++
++		if (num < 1 || bw_mode == adapter->driver_tx_bw_mode)
++			goto exit;
++
++		rtw_set_tx_bw_mode(adapter, bw_mode);
++	}
++
++exit:
++	return count;
++}
++
++static int proc_get_hal_txpwr_info(struct seq_file *m, void *v)
++{
++#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++
++	if (hal_data->txpwr_pg_mode == TXPWR_PG_WITH_PWR_IDX) {
++		if (hal_is_band_support(adapter, BAND_ON_2_4G))
++			dump_hal_txpwr_info_2g(m, adapter, hal_spec->rfpath_num_2g, hal_data->max_tx_cnt);
++
++		#if CONFIG_IEEE80211_BAND_5GHZ
++		if (hal_is_band_support(adapter, BAND_ON_5G))
++			dump_hal_txpwr_info_5g(m, adapter, hal_spec->rfpath_num_5g, hal_data->max_tx_cnt);
++		#endif
++	}
++#endif
++
++	return 0;
++}
++
++static int proc_get_target_tx_power(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_target_tx_power(m, adapter);
++
++	return 0;
++}
++
++static int proc_get_tx_power_by_rate(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_tx_power_by_rate(m, adapter);
++
++	return 0;
++}
++
++#if CONFIG_TXPWR_LIMIT
++static int proc_get_tx_power_limit(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_txpwr_lmt(m, adapter);
++
++	return 0;
++}
++#endif /* CONFIG_TXPWR_LIMIT */
++
++static int proc_get_tx_power_ext_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_tx_power_ext_info(m, adapter);
++
++	return 0;
++}
++
++static ssize_t proc_set_tx_power_ext_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	char tmp[32] = {0};
++	char cmd[16] = {0};
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%s", cmd);
++
++		if (num < 1)
++			return count;
++
++		#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
++		phy_free_filebuf_mask(adapter, LOAD_BB_PG_PARA_FILE | LOAD_RF_TXPWR_LMT_PARA_FILE);
++		#endif
++
++		rtw_ps_deny(adapter, PS_DENY_IOCTL);
++		if (rtw_pwr_wakeup(adapter) == _FALSE)
++			goto clear_ps_deny;
++
++		if (strcmp("default", cmd) == 0)
++			rtw_run_in_thread_cmd(adapter, ((void *)(phy_reload_default_tx_power_ext_info)), adapter);
++		else
++			rtw_run_in_thread_cmd(adapter, ((void *)(phy_reload_tx_power_ext_info)), adapter);
++
++		rtw_run_in_thread_cmd_wait(adapter, ((void *)(rtw_hal_update_txpwr_level)), adapter, 2000);
++
++clear_ps_deny:
++		rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
++	}
++
++	return count;
++}
++
++static void *proc_start_tx_power_idx(struct seq_file *m, loff_t *pos)
++{
++	u8 path = ((*pos) & 0xFF00) >> 8;
++
++	if (path >= RF_PATH_MAX)
++		return NULL;
++
++	return pos;
++}
++static void proc_stop_tx_power_idx(struct seq_file *m, void *v)
++{
++}
++
++static void *proc_next_tx_power_idx(struct seq_file *m, void *v, loff_t *pos)
++{
++	u8 path = ((*pos) & 0xFF00) >> 8;
++	u8 rs = *pos & 0xFF;
++
++	rs++;
++	if (rs >= RATE_SECTION_NUM) {
++		rs = 0;
++		path++;
++	}
++
++	if (path >= RF_PATH_MAX)
++		return NULL;
++
++	*pos = (path << 8) | rs;
++
++	return pos;
++}
++
++static int proc_get_tx_power_idx(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	u32 pos = *((loff_t *)(v));
++	u8 path = (pos & 0xFF00) >> 8;
++	u8 rs = pos & 0xFF;
++	enum channel_width bw = hal_data->current_channel_bw;
++	u8 cch = hal_data->current_channel;
++
++	if (0)
++		RTW_INFO("%s path=%u, rs=%u\n", __func__, path, rs);
++
++	if (path == RF_PATH_A && rs == CCK)
++		dump_tx_power_idx_title(m, adapter, bw, cch, 0);
++	dump_tx_power_idx_by_path_rs(m, adapter, path, rs, bw, cch, 0);
++
++	return 0;
++}
++
++static struct seq_operations seq_ops_tx_power_idx = {
++	.start = proc_start_tx_power_idx,
++	.stop  = proc_stop_tx_power_idx,
++	.next  = proc_next_tx_power_idx,
++	.show  = proc_get_tx_power_idx,
++};
++
++static ssize_t proc_set_tx_power_idx_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	char tmp[32] = {0};
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		u8 ch, bw, offset;
++		u8 cch;
++
++		int num = sscanf(tmp, "%hhu %hhu %hhu", &ch, &bw, &offset);
++
++		if (num < 3)
++			return count;
++
++		cch = rtw_get_center_ch(ch, bw, offset);
++		dump_tx_power_idx(RTW_DBGDUMP, adapter, bw, cch, ch);
++	}
++
++	return count;
++}
++
++static void *proc_start_txpwr_total_dbm(struct seq_file *m, loff_t *pos)
++{
++	u8 rs = *pos;
++
++	if (rs >= RATE_SECTION_NUM)
++		return NULL;
++
++	return pos;
++}
++
++static void proc_stop_txpwr_total_dbm(struct seq_file *m, void *v)
++{
++}
++
++static void *proc_next_txpwr_total_dbm(struct seq_file *m, void *v, loff_t *pos)
++{
++	u8 rs = *pos;
++
++	rs++;
++	if (rs >= RATE_SECTION_NUM)
++		return NULL;
++
++	*pos = rs;
++
++	return pos;
++}
++
++static int proc_get_txpwr_total_dbm(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++	u32 pos = *((loff_t *)(v));
++	u8 rs = pos;
++	enum channel_width bw = hal_data->current_channel_bw;
++	u8 cch = hal_data->current_channel;
++
++	if (rs == CCK)
++		dump_txpwr_total_dbm_title(m, adapter, bw, cch, 0);
++	dump_txpwr_total_dbm_by_rs(m, adapter, rs, bw, cch, 0);
++
++	return 0;
++}
++
++static struct seq_operations seq_ops_txpwr_total_dbm = {
++	.start = proc_start_txpwr_total_dbm,
++	.stop  = proc_stop_txpwr_total_dbm,
++	.next  = proc_next_txpwr_total_dbm,
++	.show  = proc_get_txpwr_total_dbm,
++};
++
++static ssize_t proc_set_txpwr_total_dbm_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	char tmp[32] = {0};
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		u8 ch, bw, offset;
++		u8 cch;
++
++		int num = sscanf(tmp, "%hhu %hhu %hhu", &ch, &bw, &offset);
++
++		if (num < 3)
++			return count;
++
++		cch = rtw_get_center_ch(ch, bw, offset);
++		dump_txpwr_total_dbm(RTW_DBGDUMP, adapter, bw, cch, ch);
++	}
++
++	return count;
++}
++
++#ifdef CONFIG_RF_POWER_TRIM
++static int proc_get_kfree_flag(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
++
++	RTW_PRINT_SEL(m, "0x%02x\n", kfree_data->flag);
++
++	return 0;
++}
++
++static ssize_t proc_set_kfree_flag(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
++	char tmp[32] = {0};
++	u8 flag;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhx", &flag);
++
++		if (num < 1)
++			return count;
++
++		kfree_data->flag = flag;
++	}
++
++	return count;
++}
++
++static int proc_get_kfree_bb_gain(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
++	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
++	u8 i, j;
++
++	for (i = 0; i < BB_GAIN_NUM; i++) {
++
++			if (i == 0)
++				_RTW_PRINT_SEL(m, "2G: ");
++#if CONFIG_IEEE80211_BAND_5GHZ
++			switch (i) {
++			case 1:
++					_RTW_PRINT_SEL(m, "5GLB1: ");
++					break;
++			case 2:
++					_RTW_PRINT_SEL(m, "5GLB2: ");
++					break;
++			case 3:
++					_RTW_PRINT_SEL(m, "5GMB1: ");
++					break;
++			case 4:
++					_RTW_PRINT_SEL(m, "5GMB2: ");
++					break;
++			case 5:
++					_RTW_PRINT_SEL(m, "5GHB: ");
++					break;
++		}
++#endif
++		for (j = 0; j < hal_spec->rf_reg_path_num; j++)
++			_RTW_PRINT_SEL(m, "%d ", kfree_data->bb_gain[i][j]);
++		_RTW_PRINT_SEL(m, "\n");
++	}
++
++	return 0;
++}
++
++static ssize_t proc_set_kfree_bb_gain(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
++	char tmp[BB_GAIN_NUM * RF_PATH_MAX] = {0};
++	u8 chidx;
++	s8 bb_gain[BB_GAIN_NUM];
++	char ch_band_Group[6];
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		char *c, *next;
++		int i = 0;
++
++		next = tmp;
++		c = strsep(&next, " \t");
++
++		if (sscanf(c, "%s", ch_band_Group) != 1) {
++			RTW_INFO("Error Head Format, channel Group select\n,Please input:\t 2G , 5GLB1 , 5GLB2 , 5GMB1 , 5GMB2 , 5GHB\n");
++			return count;
++		}
++		if (strcmp("2G", ch_band_Group) == 0)
++			chidx = BB_GAIN_2G;
++#if CONFIG_IEEE80211_BAND_5GHZ
++		else if (strcmp("5GLB1", ch_band_Group) == 0)
++			chidx = BB_GAIN_5GLB1;
++		else if (strcmp("5GLB2", ch_band_Group) == 0)
++			chidx = BB_GAIN_5GLB2;
++		else if (strcmp("5GMB1", ch_band_Group) == 0)
++			chidx = BB_GAIN_5GMB1;
++		else if (strcmp("5GMB2", ch_band_Group) == 0)
++			chidx = BB_GAIN_5GMB2;
++		else if (strcmp("5GHB", ch_band_Group) == 0)
++			chidx = BB_GAIN_5GHB;
++#endif /*CONFIG_IEEE80211_BAND_5GHZ*/
++		else {
++			RTW_INFO("Error Head Format, channel Group select\n,Please input:\t 2G , 5GLB1 , 5GLB2 , 5GMB1 , 5GMB2 , 5GHB\n");
++			return count;
++		}
++		c = strsep(&next, " \t");
++
++		while (c != NULL) {
++			if (sscanf(c, "%hhx", &bb_gain[i]) != 1)
++				break;
++
++			kfree_data->bb_gain[chidx][i] = bb_gain[i];
++			RTW_INFO("%s,kfree_data->bb_gain[%d][%d]=%x\n", __func__, chidx, i, kfree_data->bb_gain[chidx][i]);
++
++			c = strsep(&next, " \t");
++			i++;
++		}
++
++	}
++
++	return count;
++
++}
++
++static int proc_get_kfree_thermal(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
++
++	_RTW_PRINT_SEL(m, "%d\n", kfree_data->thermal);
++
++	return 0;
++}
++
++static ssize_t proc_set_kfree_thermal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
++	char tmp[32] = {0};
++	s8 thermal;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhd", &thermal);
++
++		if (num < 1)
++			return count;
++
++		kfree_data->thermal = thermal;
++	}
++
++	return count;
++}
++
++static ssize_t proc_set_tx_gain_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter;
++	char tmp[32] = {0};
++	u8 rf_path;
++	s8 offset;
++
++	adapter = (_adapter *)rtw_netdev_priv(dev);
++	if (!adapter)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = sscanf(tmp, "%hhu %hhd", &rf_path, &offset);
++
++		if (num < 2)
++			return count;
++
++		RTW_INFO("write rf_path:%u tx gain offset:%d\n", rf_path, offset);
++		rtw_rf_set_tx_gain_offset(adapter, rf_path, offset);
++	}
++
++	return count;
++}
++#endif /* CONFIG_RF_POWER_TRIM */
++
++#ifdef CONFIG_BT_COEXIST
++ssize_t proc_set_btinfo_evt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u8 btinfo[8];
++
++	if (count < 6)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		int num = 0;
++
++		_rtw_memset(btinfo, 0, 8);
++
++		num = sscanf(tmp, "%hhx %hhx %hhx %hhx %hhx %hhx %hhx %hhx"
++			, &btinfo[0], &btinfo[1], &btinfo[2], &btinfo[3]
++			, &btinfo[4], &btinfo[5], &btinfo[6], &btinfo[7]);
++
++		if (num < 6)
++			return -EINVAL;
++
++		btinfo[1] = num - 2;
++
++		rtw_btinfo_cmd(padapter, btinfo, btinfo[1] + 2);
++	}
++
++	return count;
++}
++
++static u8 btreg_read_type = 0;
++static u16 btreg_read_addr = 0;
++static int btreg_read_error = 0;
++static u8 btreg_write_type = 0;
++static u16 btreg_write_addr = 0;
++static int btreg_write_error = 0;
++
++static u8 *btreg_type[] = {
++	"rf",
++	"modem",
++	"bluewize",
++	"vendor",
++	"le"
++};
++
++static int btreg_parse_str(char const *input, u8 *type, u16 *addr, u16 *val)
++{
++	u32 num;
++	u8 str[80] = {0};
++	u8 t = 0;
++	u32 a, v;
++	u8 i, n;
++
++
++	num = sscanf(input, "%s %x %x", str, &a, &v);
++	if (num < 2) {
++		RTW_INFO("%s: INVALID input!(%s)\n", __FUNCTION__, input);
++		return -EINVAL;
++	}
++	if ((num < 3) && val) {
++		RTW_INFO("%s: INVALID input!(%s)\n", __FUNCTION__, input);
++		return -EINVAL;
++	}
++
++	n = sizeof(btreg_type) / sizeof(btreg_type[0]);
++	for (i = 0; i < n; i++) {
++		if (!strcasecmp(str, btreg_type[i])) {
++			t = i;
++			break;
++		}
++	}
++	if (i == n) {
++		RTW_INFO("%s: unknown type(%s)!\n", __FUNCTION__, str);
++		return -EINVAL;
++	}
++
++	switch (t) {
++	case 0:
++		/* RF */
++		if (a & 0xFFFFFF80) {
++			RTW_INFO("%s: INVALID address(0x%X) for type %s(%d)!\n",
++				 __FUNCTION__, a, btreg_type[t], t);
++			return -EINVAL;
++		}
++		break;
++	case 1:
++		/* Modem */
++		if (a & 0xFFFFFE00) {
++			RTW_INFO("%s: INVALID address(0x%X) for type %s(%d)!\n",
++				 __FUNCTION__, a, btreg_type[t], t);
++			return -EINVAL;
++		}
++		break;
++	default:
++		/* Others(Bluewize, Vendor, LE) */
++		if (a & 0xFFFFF000) {
++			RTW_INFO("%s: INVALID address(0x%X) for type %s(%d)!\n",
++				 __FUNCTION__, a, btreg_type[t], t);
++			return -EINVAL;
++		}
++		break;
++	}
++
++	if (val) {
++		if (v & 0xFFFF0000) {
++			RTW_INFO("%s: INVALID value(0x%x)!\n", __FUNCTION__, v);
++			return -EINVAL;
++		}
++		*val = (u16)v;
++	}
++
++	*type = (u8)t;
++	*addr = (u16)a;
++
++	return 0;
++}
++
++int proc_get_btreg_read(struct seq_file *m, void *v)
++{
++	struct net_device *dev;
++	PADAPTER padapter;
++	u16 ret;
++	u32 data;
++
++
++	if (btreg_read_error)
++		return btreg_read_error;
++
++	dev = m->private;
++	padapter = (PADAPTER)rtw_netdev_priv(dev);
++
++	ret = rtw_btcoex_btreg_read(padapter, btreg_read_type, btreg_read_addr, &data);
++	if (CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS))
++		RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X = 0x%08x\n", btreg_type[btreg_read_type], btreg_read_addr, data);
++	else
++		RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X read fail. error code = 0x%04x.\n", btreg_type[btreg_read_type], btreg_read_addr, ret);
++
++	return 0;
++}
++
++ssize_t proc_set_btreg_read(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	PADAPTER padapter;
++	u8 tmp[80] = {0};
++	u32 num;
++	int err;
++
++
++	padapter = (PADAPTER)rtw_netdev_priv(dev);
++
++	if (NULL == buffer) {
++		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n",
++			 FUNC_ADPT_ARG(padapter));
++		err = -EFAULT;
++		goto exit;
++	}
++
++	if (count < 1) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n",
++			 FUNC_ADPT_ARG(padapter));
++		err = -EFAULT;
++		goto exit;
++	}
++
++	num = count;
++	if (num > (sizeof(tmp) - 1))
++		num = (sizeof(tmp) - 1);
++
++	if (copy_from_user(tmp, buffer, num)) {
++		RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n",
++			 FUNC_ADPT_ARG(padapter));
++		err = -EFAULT;
++		goto exit;
++	}
++	/* [Coverity] sure tmp end with '\0'(string terminal) */
++	tmp[sizeof(tmp) - 1] = 0;
++
++	err = btreg_parse_str(tmp, &btreg_read_type, &btreg_read_addr, NULL);
++	if (err)
++		goto exit;
++
++	RTW_INFO(FUNC_ADPT_FMT ": addr=(%s)0x%X\n",
++		FUNC_ADPT_ARG(padapter), btreg_type[btreg_read_type], btreg_read_addr);
++
++exit:
++	btreg_read_error = err;
++
++	return count;
++}
++
++int proc_get_btreg_write(struct seq_file *m, void *v)
++{
++	struct net_device *dev;
++	PADAPTER padapter;
++	u16 ret;
++	u32 data;
++
++
++	if (btreg_write_error < 0)
++		return btreg_write_error;
++	else if (btreg_write_error > 0) {
++		RTW_PRINT_SEL(m, "BTREG write: (%s)0x%04X write fail. error code = 0x%04x.\n", btreg_type[btreg_write_type], btreg_write_addr, btreg_write_error);
++		return 0;
++	}
++
++	dev = m->private;
++	padapter = (PADAPTER)rtw_netdev_priv(dev);
++
++	ret = rtw_btcoex_btreg_read(padapter, btreg_write_type, btreg_write_addr, &data);
++	if (CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS))
++		RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X = 0x%08x\n", btreg_type[btreg_write_type], btreg_write_addr, data);
++	else
++		RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X read fail. error code = 0x%04x.\n", btreg_type[btreg_write_type], btreg_write_addr, ret);
++
++	return 0;
++}
++
++ssize_t proc_set_btreg_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	PADAPTER padapter;
++	u8 tmp[80] = {0};
++	u32 num;
++	u16 val;
++	u16 ret;
++	int err;
++
++
++	padapter = (PADAPTER)rtw_netdev_priv(dev);
++
++	if (NULL == buffer) {
++		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n",
++			 FUNC_ADPT_ARG(padapter));
++		err = -EFAULT;
++		goto exit;
++	}
++
++	if (count < 1) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n",
++			 FUNC_ADPT_ARG(padapter));
++		err = -EFAULT;
++		goto exit;
++	}
++
++	num = count;
++	if (num > (sizeof(tmp) - 1))
++		num = (sizeof(tmp) - 1);
++
++	if (copy_from_user(tmp, buffer, num)) {
++		RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n",
++			 FUNC_ADPT_ARG(padapter));
++		err = -EFAULT;
++		goto exit;
++	}
++
++	err = btreg_parse_str(tmp, &btreg_write_type, &btreg_write_addr, &val);
++	if (err)
++		goto exit;
++
++	RTW_INFO(FUNC_ADPT_FMT ": Set (%s)0x%X = 0x%x\n",
++		FUNC_ADPT_ARG(padapter), btreg_type[btreg_write_type], btreg_write_addr, val);
++
++	ret = rtw_btcoex_btreg_write(padapter, btreg_write_type, btreg_write_addr, val);
++	if (!CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS))
++		err = ret;
++
++exit:
++	btreg_write_error = err;
++
++	return count;
++}
++
++int proc_get_btc_reduce_wl_txpwr(struct seq_file *m, void *v)
++{
++	struct net_device *dev;
++	PADAPTER padapter;
++	u8 data;
++
++	dev = m->private;
++	padapter = (PADAPTER)rtw_netdev_priv(dev);
++
++	data = rtw_btcoex_get_reduce_wl_txpwr(padapter);
++	RTW_PRINT_SEL(m, "BTC reduce WL TxPwr = %d dB\n", data);
++
++	return 0;
++}
++
++ssize_t proc_set_btc_reduce_wl_txpwr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	PADAPTER padapter;
++	HAL_DATA_TYPE *hal_data;
++	u8 tmp[80] = {0};
++	u32 val = 0;
++	u32 num;
++
++	padapter = (PADAPTER)rtw_netdev_priv(dev);
++	hal_data = GET_HAL_DATA(padapter);
++
++	/*	RTW_INFO("+" FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(padapter)); */
++
++	if (NULL == buffer) {
++		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n",
++			 FUNC_ADPT_ARG(padapter));
++
++		return -EFAULT;
++	}
++
++	if (count < 1) {
++		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n",
++			 FUNC_ADPT_ARG(padapter));
++
++		return -EFAULT;
++	}
++
++	num = count;
++	if (num > (sizeof(tmp) - 1))
++		num = (sizeof(tmp) - 1);
++
++	if (copy_from_user(tmp, buffer, num)) {
++		RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n",
++			 FUNC_ADPT_ARG(padapter));
++
++		return -EFAULT;
++	}
++
++	num = sscanf(tmp, "%d", &val);
++
++	if ((IS_HARDWARE_TYPE_8822C(padapter)) && (hal_data->EEPROMBluetoothCoexist == _TRUE))
++		rtw_btc_reduce_wl_txpwr_cmd(padapter, val);
++
++	return count;
++}
++
++#endif /* CONFIG_BT_COEXIST */
++
++#ifdef CONFIG_MBSSID_CAM
++int proc_get_mbid_cam_cache(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	rtw_mbid_cam_cache_dump(m, __func__, adapter);
++	rtw_mbid_cam_dump(m, __func__, adapter);
++	return 0;
++}
++#endif /* CONFIG_MBSSID_CAM */
++
++int proc_get_mac_addr(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	rtw_hal_dump_macaddr(m, adapter);
++	return 0;
++}
++
++static int proc_get_skip_band(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	int bandskip;
++
++	bandskip = RTW_GET_SCAN_BAND_SKIP(adapter);
++	RTW_PRINT_SEL(m, "bandskip:0x%02x\n", bandskip);
++	return 0;
++}
++
++static ssize_t proc_set_skip_band(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[6];
++	u8 skip_band;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhu", &skip_band);
++
++		if (num < 1)
++			return -EINVAL;
++
++		if (1 == skip_band)
++			RTW_SET_SCAN_BAND_SKIP(padapter, BAND_24G);
++		else if (2 == skip_band)
++			RTW_SET_SCAN_BAND_SKIP(padapter, BAND_5G);
++		else if (3 == skip_band)
++			RTW_CLR_SCAN_BAND_SKIP(padapter, BAND_24G);
++		else if (4 == skip_band)
++			RTW_CLR_SCAN_BAND_SKIP(padapter, BAND_5G);
++	}
++	return count;
++
++}
++
++#ifdef CONFIG_RTW_ACS
++static int proc_get_chan_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	rtw_acs_chan_info_dump(m, adapter);
++	return 0;
++}
++
++static int proc_get_best_chan(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (IS_ACS_ENABLE(adapter))
++		rtw_acs_info_dump(m, adapter);
++	else
++		_RTW_PRINT_SEL(m,"ACS disabled\n");
++	return 0;
++}
++
++static ssize_t proc_set_acs(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++#ifdef CONFIG_RTW_ACS_DBG
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u8 acs_state = 0;
++	u16 scan_ch_ms= 0, acs_scan_ch_ms = 0;
++	u8 scan_type = SCAN_ACTIVE, igi= 0, bw = 0;
++	u8 acs_scan_type = SCAN_ACTIVE, acs_igi= 0, acs_bw = 0;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhu %hhu %hu %hhx %hhu",
++			&acs_state, &scan_type, &scan_ch_ms, &igi, &bw);
++
++		if (num < 1)
++			return -EINVAL;
++
++		if (acs_state)
++			rtw_acs_start(padapter);
++		else
++			rtw_acs_stop(padapter);
++		num = num -1;
++
++		if(num) {
++			if (num-- > 0)
++				acs_scan_type = scan_type;
++			if (num-- > 0)
++				acs_scan_ch_ms = scan_ch_ms;
++			if (num-- > 0)
++				acs_igi = igi;
++			if (num-- > 0)
++				acs_bw = bw;
++			rtw_acs_adv_setting(padapter, acs_scan_type, acs_scan_ch_ms, acs_igi, acs_bw);
++		}
++	}
++#endif /*CONFIG_RTW_ACS_DBG*/
++	return count;
++}
++#endif /*CONFIG_RTW_ACS*/
++
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++static int proc_get_nm(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	rtw_noise_info_dump(m, adapter);
++	return 0;
++}
++
++static ssize_t proc_set_nm(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u8 nm_state = 0;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhu", &nm_state);
++
++		if (num < 1)
++			return -EINVAL;
++
++		if (nm_state)
++			rtw_nm_enable(padapter);
++		else
++			rtw_nm_disable(padapter);
++
++	}
++	return count;
++}
++#endif /*CONFIG_RTW_ACS*/
++
++static int proc_get_hal_spec(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_hal_spec(m, adapter);
++	return 0;
++}
++
++static int proc_get_hal_trx_mode(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = rtw_netdev_priv(dev);
++
++	dump_hal_trx_mode(m, adapter);
++	return 0;
++}
++
++static int proc_get_phy_cap(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	rtw_dump_phy_cap(m, adapter);
++#ifdef CONFIG_80211N_HT
++	rtw_dump_drv_phy_cap(m, adapter);
++	rtw_get_dft_phy_cap(m, adapter);
++#endif /* CONFIG_80211N_HT */
++	return 0;
++}
++
++#ifdef CONFIG_SUPPORT_TRX_SHARED
++#include "../../hal/hal_halmac.h"
++static int proc_get_trx_share_mode(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_trx_share_mode(m, adapter);
++	return 0;
++}
++#endif
++
++static int proc_dump_rsvd_page(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	rtw_dump_rsvd_page(m, adapter, adapter->rsvd_page_offset, adapter->rsvd_page_num);
++	return 0;
++}
++static ssize_t proc_set_rsvd_page_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u8 page_offset, page_num;
++
++	if (count < 2)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhu %hhu", &page_offset, &page_num);
++
++		if (num < 2)
++			return -EINVAL;
++		padapter->rsvd_page_offset = page_offset;
++		padapter->rsvd_page_num = page_num;
++	}
++	return count;
++}
++
++#ifdef CONFIG_SUPPORT_FIFO_DUMP
++static int proc_dump_fifo(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	rtw_dump_fifo(m, adapter, adapter->fifo_sel, adapter->fifo_addr, adapter->fifo_size);
++	return 0;
++}
++static ssize_t proc_set_fifo_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u8 fifo_sel = 0;
++	u32 fifo_addr = 0;
++	u32 fifo_size = 0;
++
++	if (count < 3)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%hhu %x %d", &fifo_sel, &fifo_addr, &fifo_size);
++
++		if (num < 3)
++			return -EINVAL;
++
++		padapter->fifo_sel = fifo_sel;
++		padapter->fifo_addr = fifo_addr;
++		padapter->fifo_size = fifo_size;
++	}
++	return count;
++}
++#endif
++
++#ifdef CONFIG_WOW_PATTERN_HW_CAM
++int proc_dump_pattern_cam(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	int i;
++	struct  rtl_wow_pattern context;
++
++	for (i = 0 ; i < pwrpriv->wowlan_pattern_idx; i++) {
++		rtw_wow_pattern_read_cam_ent(padapter, i, &context);
++		rtw_dump_wow_pattern(m, &context, i);
++	}
++
++	return 0;
++}
++#endif
++
++static int proc_get_napi_info(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv *pregistrypriv = &adapter->registrypriv;
++	u8 napi = 0, gro = 0;
++	u32 weight = 0;
++	struct dvobj_priv *d;
++	d = adapter_to_dvobj(adapter);
++
++
++#ifdef CONFIG_RTW_NAPI
++	if (pregistrypriv->en_napi) {
++		napi = 1;
++		weight = RTL_NAPI_WEIGHT;
++	}
++
++#ifdef CONFIG_RTW_GRO
++	if (pregistrypriv->en_gro)
++		gro = 1;
++#endif /* CONFIG_RTW_GRO */
++#endif /* CONFIG_RTW_NAPI */
++
++	if (napi) {
++		RTW_PRINT_SEL(m, "NAPI enable, weight=%d\n", weight);
++#ifdef CONFIG_RTW_NAPI_DYNAMIC
++		RTW_PRINT_SEL(m, "Dynamaic NAPI mechanism is on, current NAPI %s\n",
++			      d->en_napi_dynamic ? "enable" : "disable");
++		RTW_PRINT_SEL(m, "Dynamaic NAPI info:\n"
++				 "\ttcp_rx_threshold = %d Mbps\n"
++				 "\tcur_rx_tp = %d Mbps\n",
++			      pregistrypriv->napi_threshold,
++			      d->traffic_stat.cur_rx_tp);
++#endif /* CONFIG_RTW_NAPI_DYNAMIC */
++	} else {
++		RTW_PRINT_SEL(m, "NAPI disable\n");
++	}
++	RTW_PRINT_SEL(m, "GRO %s\n", gro?"enable":"disable");
++
++	return 0;
++
++}
++
++#ifdef CONFIG_RTW_NAPI_DYNAMIC
++static ssize_t proc_set_napi_th(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	struct _ADAPTER *adapter = (struct _ADAPTER *)rtw_netdev_priv(dev);
++	struct registry_priv *registry = &adapter->registrypriv;
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	PADAPTER iface = NULL;
++	char tmp[32] = {0};
++	int thrshld = 0;
++	int num = 0, i = 0;
++
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	RTW_INFO("%s: Last threshold = %d Mbps\n", __FUNCTION__, registry->napi_threshold);
++
++
++	for (i = 0; i < dvobj->iface_nums; i++) {
++		iface = dvobj->padapters[i];
++		if (iface) {
++			if (buffer && !copy_from_user(tmp, buffer, count)) {
++				registry = &iface->registrypriv;
++				num = sscanf(tmp, "%d", &thrshld);
++				if (num > 0) {
++					if (thrshld > 0)
++						registry->napi_threshold = thrshld;
++				}
++			}
++		}
++	}
++	RTW_INFO("%s: New threshold = %d Mbps\n", __FUNCTION__, registry->napi_threshold);
++	RTW_INFO("%s: Current RX throughput = %d Mbps\n",
++		 __FUNCTION__, adapter_to_dvobj(adapter)->traffic_stat.cur_rx_tp);
++
++	return count;
++}
++#endif /* CONFIG_RTW_NAPI_DYNAMIC */
++
++
++ssize_t proc_set_dynamic_agg_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	int enable = 0, i = 0;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
++		PADAPTER iface = NULL;
++		int num = sscanf(tmp, "%d", &enable);
++
++		if (num !=  1) {
++			RTW_INFO("invalid parameter!\n");
++			return count;
++		}
++
++		RTW_INFO("dynamic_agg_enable:%d\n", enable);
++
++		for (i = 0; i < dvobj->iface_nums; i++) {
++			iface = dvobj->padapters[i];
++			if (iface)
++				iface->registrypriv.dynamic_agg_enable = enable;
++		}
++
++	}
++
++	return count;
++
++}
++
++static int proc_get_dynamic_agg_enable(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv *pregistrypriv = &adapter->registrypriv;
++
++	RTW_PRINT_SEL(m, "dynamic_agg_enable:%d\n", pregistrypriv->dynamic_agg_enable);
++
++	return 0;
++}
++
++#ifdef CONFIG_RTW_WDS
++static int proc_get_wds_en(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = rtw_netdev_priv(dev);
++
++	if (MLME_STATE(adapter) & (WIFI_AP_STATE | WIFI_STATION_STATE))
++		RTW_PRINT_SEL(m, "%d\n", adapter_use_wds(adapter));
++
++	return 0;
++}
++
++static ssize_t proc_set_wds_en(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = rtw_netdev_priv(dev);
++	char tmp[32];
++
++	if (!(MLME_STATE(adapter) & (WIFI_AP_STATE | WIFI_STATION_STATE)))
++		return -EFAULT;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		u8 enable;
++		int num = sscanf(tmp, "%hhu", &enable);
++
++		if (num >= 1)
++			adapter_set_use_wds(adapter, enable);
++	}
++
++	return count;
++}
++
++static ssize_t proc_set_sta_wds_en(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = rtw_netdev_priv(dev);
++	char tmp[32];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		u8 enable;
++		u8 addr[ETH_ALEN];
++		struct sta_info *sta;
++		int num = sscanf(tmp, "%hhu "MAC_SFMT, &enable, MAC_SARG(addr));
++
++		if (num != 7)
++			return -EINVAL;
++
++		if (IS_MCAST(addr) || _rtw_memcmp(adapter_mac_addr(adapter), addr, ETH_ALEN))
++			return -EINVAL;
++
++		sta = rtw_get_stainfo(&adapter->stapriv, addr);
++		if (!sta)
++			return -EINVAL;
++
++		if (enable)
++			sta->flags |= WLAN_STA_WDS;
++		else
++			sta->flags &= ~WLAN_STA_WDS;
++	}
++
++	return count;
++}
++
++#ifdef CONFIG_AP_MODE
++static int proc_get_wds_path(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = rtw_netdev_priv(dev);
++
++	if (MLME_IS_AP(adapter) && MLME_IS_ASOC(adapter))
++		dump_wpath(m, adapter);
++
++	return 0;
++}
++#endif /* CONFIG_AP_MODE */
++#endif /* CONFIG_RTW_WDS */
++
++#ifdef CONFIG_RTW_MULTI_AP
++static int proc_get_multi_ap_opmode(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = rtw_netdev_priv(dev);
++
++	if (MLME_STATE(adapter) & (WIFI_AP_STATE | WIFI_STATION_STATE))
++		RTW_PRINT_SEL(m, "0x%02x\n", adapter->multi_ap);
++
++	return 0;
++}
++
++static ssize_t proc_set_multi_ap_opmode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = rtw_netdev_priv(dev);
++	char tmp[32];
++
++	if (!(MLME_STATE(adapter) & (WIFI_AP_STATE | WIFI_STATION_STATE)))
++		return -EFAULT;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		u8 mode;
++		int num = sscanf(tmp, "%hhx", &mode);
++
++		if (num >= 1) {
++			if (MLME_IS_AP(adapter))
++				adapter->multi_ap = mode & (MULTI_AP_FRONTHAUL_BSS | MULTI_AP_BACKHAUL_BSS);
++			else
++				adapter->multi_ap = mode & MULTI_AP_BACKHAUL_STA;
++			if (adapter->multi_ap & (MULTI_AP_BACKHAUL_BSS | MULTI_AP_BACKHAUL_STA))
++				adapter_set_use_wds(adapter, 1);
++		}
++	}
++
++	return count;
++}
++#ifdef CONFIG_IOCTL_CFG80211
++static u8 assoc_req_mac_addr[6];
++int proc_get_sta_assoc_req_frame_body(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (MLME_IS_AP(adapter)) {
++		struct sta_info *psta;
++		_irqL irqL;
++		u8 *passoc_req = NULL;
++		u32 assoc_req_len = 0;
++
++		psta = rtw_get_stainfo(&adapter->stapriv, assoc_req_mac_addr);
++		if (psta == NULL) {
++			RTW_PRINT(FUNC_ADPT_FMT" sta("MAC_FMT") not found\n",
++				  FUNC_ADPT_ARG(adapter), MAC_ARG(assoc_req_mac_addr));
++			return 0;
++		}
++		RTW_PRINT(FUNC_ADPT_FMT" sta("MAC_FMT") found\n",
++			  FUNC_ADPT_ARG(adapter), MAC_ARG(assoc_req_mac_addr));
++		_enter_critical_bh(&psta->lock, &irqL);
++		if (psta->passoc_req && psta->assoc_req_len > 0) {
++			passoc_req = rtw_zmalloc(psta->assoc_req_len);
++			if (passoc_req) {
++				assoc_req_len = psta->assoc_req_len;
++				_rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len);
++			}
++		}
++		_exit_critical_bh(&psta->lock, &irqL);
++		if (passoc_req && assoc_req_len > IEEE80211_3ADDR_LEN) {
++			u8 *body = passoc_req + IEEE80211_3ADDR_LEN;
++			u32 body_len = assoc_req_len - IEEE80211_3ADDR_LEN;
++			u16 i;
++
++			for (i = 0; i < body_len; i++)
++				_RTW_PRINT_SEL(m, "%02X", body[i]);
++			_RTW_PRINT_SEL(m, "\n");
++		}
++		if (passoc_req && assoc_req_len > 0)
++			rtw_mfree(passoc_req, assoc_req_len);
++	}
++
++	return 0;
++}
++
++ssize_t proc_set_sta_assoc_req_frame_body(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[18] = {0};
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		if (sscanf(tmp, MAC_SFMT, MAC_SARG(assoc_req_mac_addr)) != 6) {
++			_rtw_memset(assoc_req_mac_addr, 0, 6);
++			RTW_PRINT(FUNC_ADPT_FMT" Invalid format\n",
++				  FUNC_ADPT_ARG(adapter));
++		}
++
++	}
++
++	return count;
++}
++#endif /* CONFIG_IOCTL_CFG80211 */
++#endif /* CONFIG_RTW_MULTI_AP */
++
++#ifdef CONFIG_RTW_MESH
++static int proc_get_mesh_peer_sel_policy(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_mesh_peer_sel_policy(m, adapter);
++
++	return 0;
++}
++
++#if CONFIG_RTW_MESH_ACNODE_PREVENT
++static int proc_get_mesh_acnode_prevent(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (MLME_IS_MESH(adapter))
++		dump_mesh_acnode_prevent_settings(m, adapter);
++
++	return 0;
++}
++
++static ssize_t proc_set_mesh_acnode_prevent(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
++		u8 enable;
++		u32 conf_timeout_ms;
++		u32 notify_timeout_ms;
++		int num = sscanf(tmp, "%hhu %u %u", &enable, &conf_timeout_ms, &notify_timeout_ms);
++
++		if (num >= 1)
++			peer_sel_policy->acnode_prevent = enable;
++		if (num >= 2)
++			peer_sel_policy->acnode_conf_timeout_ms = conf_timeout_ms;
++		if (num >= 3)
++			peer_sel_policy->acnode_notify_timeout_ms = notify_timeout_ms;
++	}
++
++	return count;
++}
++#endif /* CONFIG_RTW_MESH_ACNODE_PREVENT */
++
++#if CONFIG_RTW_MESH_OFFCH_CAND
++static int proc_get_mesh_offch_cand(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (MLME_IS_MESH(adapter))
++		dump_mesh_offch_cand_settings(m, adapter);
++
++	return 0;
++}
++
++static ssize_t proc_set_mesh_offch_cand(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
++		u8 enable;
++		u32 find_int_ms;
++		int num = sscanf(tmp, "%hhu %u", &enable, &find_int_ms);
++
++		if (num >= 1)
++			peer_sel_policy->offch_cand = enable;
++		if (num >= 2)
++			peer_sel_policy->offch_find_int_ms = find_int_ms;
++	}
++
++	return count;
++}
++#endif /* CONFIG_RTW_MESH_OFFCH_CAND */
++
++#if CONFIG_RTW_MESH_PEER_BLACKLIST
++static int proc_get_mesh_peer_blacklist(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (MLME_IS_MESH(adapter)) {
++		dump_mesh_peer_blacklist_settings(m, adapter);
++		if (MLME_IS_ASOC(adapter))
++			dump_mesh_peer_blacklist(m, adapter);
++	}
++
++	return 0;
++}
++
++static ssize_t proc_set_mesh_peer_blacklist(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
++		u32 conf_timeout_ms;
++		u32 blacklist_timeout_ms;
++		int num = sscanf(tmp, "%u %u", &conf_timeout_ms, &blacklist_timeout_ms);
++
++		if (num >= 1)
++			peer_sel_policy->peer_conf_timeout_ms = conf_timeout_ms;
++		if (num >= 2)
++			peer_sel_policy->peer_blacklist_timeout_ms = blacklist_timeout_ms;
++	}
++
++	return count;
++}
++#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */
++
++#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++static int proc_get_mesh_cto_mgate_require(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (MLME_IS_MESH(adapter))
++		RTW_PRINT_SEL(m, "%u\n", adapter->mesh_cfg.peer_sel_policy.cto_mgate_require);
++
++	return 0;
++}
++
++static ssize_t proc_set_mesh_cto_mgate_require(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
++		u8 require;
++		int num = sscanf(tmp, "%hhu", &require);
++
++		if (num >= 1) {
++			peer_sel_policy->cto_mgate_require = require;
++			#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER
++			if (rtw_mesh_cto_mgate_required(adapter))
++				rtw_netif_carrier_off(adapter->pnetdev);
++			else
++				rtw_netif_carrier_on(adapter->pnetdev);
++			#endif
++		}
++	}
++
++	return count;
++}
++
++static int proc_get_mesh_cto_mgate_blacklist(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (MLME_IS_MESH(adapter)) {
++		dump_mesh_cto_mgate_blacklist_settings(m, adapter);
++		if (MLME_IS_ASOC(adapter))
++			dump_mesh_cto_mgate_blacklist(m, adapter);
++	}
++
++	return 0;
++}
++
++static ssize_t proc_set_mesh_cto_mgate_blacklist(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
++		u32 conf_timeout_ms;
++		u32 blacklist_timeout_ms;
++		int num = sscanf(tmp, "%u %u", &conf_timeout_ms, &blacklist_timeout_ms);
++
++		if (num >= 1)
++			peer_sel_policy->cto_mgate_conf_timeout_ms = conf_timeout_ms;
++		if (num >= 2)
++			peer_sel_policy->cto_mgate_blacklist_timeout_ms = blacklist_timeout_ms;
++	}
++
++	return count;
++}
++#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
++
++static int proc_get_mesh_networks(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	dump_mesh_networks(m, adapter);
++
++	return 0;
++}
++
++static int proc_get_mesh_plink_ctl(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (MLME_IS_MESH(adapter))
++		dump_mesh_plink_ctl(m, adapter);
++
++	return 0;
++}
++
++static int proc_get_mesh_mpath(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter))
++		dump_mpath(m, adapter);
++
++	return 0;
++}
++
++static int proc_get_mesh_mpp(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter))
++		dump_mpp(m, adapter);
++
++	return 0;
++}
++
++static int proc_get_mesh_known_gates(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (MLME_IS_MESH(adapter))
++		dump_known_gates(m, adapter);
++
++	return 0;
++}
++
++#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++static int proc_get_mesh_b2u_flags(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (MLME_IS_MESH(adapter))
++		dump_mesh_b2u_flags(m, adapter);
++
++	return 0;
++}
++
++static ssize_t proc_set_mesh_b2u_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++		u8 msrc, mfwd;
++		int num = sscanf(tmp, "%hhx %hhx", &msrc, &mfwd);
++
++		if (num >= 1)
++			mcfg->b2u_flags_msrc = msrc;
++		if (num >= 2)
++			mcfg->b2u_flags_mfwd = mfwd;
++	}
++
++	return count;
++}
++#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */
++
++static int proc_get_mesh_stats(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (MLME_IS_MESH(adapter))
++		dump_mesh_stats(m, adapter);
++
++	return 0;
++}
++
++static int proc_get_mesh_gate_timeout(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++
++	if (MLME_IS_MESH(adapter))
++		RTW_PRINT_SEL(m, "%u factor\n",
++			       adapter->mesh_cfg.path_gate_timeout_factor);
++
++	return 0;
++}
++
++static ssize_t proc_set_mesh_gate_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++		u32 timeout;
++		int num = sscanf(tmp, "%u", &timeout);
++
++		if (num < 1)
++			goto exit;
++
++		mcfg->path_gate_timeout_factor = timeout;
++	}
++
++exit:
++	return count;
++}
++
++static int proc_get_mesh_gate_state(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
++	u8 cto_mgate = 0;
++
++	if (MLME_IS_MESH(adapter)) {
++		if (rtw_mesh_is_primary_gate(adapter))
++			RTW_PRINT_SEL(m, "PG\n");
++		else if (mcfg->dot11MeshGateAnnouncementProtocol)
++			RTW_PRINT_SEL(m, "G\n");
++		else if (rtw_mesh_gate_num(adapter))
++			RTW_PRINT_SEL(m, "C\n");
++		else
++			RTW_PRINT_SEL(m, "N\n");
++	}
++
++	return 0;
++}
++
++static int proc_get_peer_alive_based_preq(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	struct _ADAPTER *adapter= (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv  *rp = &adapter->registrypriv;
++
++	RTW_PRINT_SEL(m, "peer_alive_based_preq = %u\n",
++		      rp->peer_alive_based_preq);
++
++	return 0;
++}
++
++static ssize_t
++proc_set_peer_alive_based_preq(struct file *file, const char __user *buffer,
++			       size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	struct _ADAPTER *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct registry_priv  *rp = &adapter->registrypriv;
++	char tmp[8];
++	int num = 0;
++	u8 enable = 0;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (!buffer || copy_from_user(tmp, buffer, count))
++		goto exit;
++
++	num = sscanf(tmp, "%hhu", &enable);
++	if (num !=  1) {
++		RTW_ERR("%s: invalid parameter!\n", __FUNCTION__);
++		goto exit;
++	}
++
++	if (enable > 1) {
++		RTW_ERR("%s: invalid value!\n", __FUNCTION__);
++		goto exit;
++	}
++	rp->peer_alive_based_preq = enable;
++
++exit:
++	return count;
++}
++#endif /* CONFIG_RTW_MESH */
++
++#ifdef RTW_BUSY_DENY_SCAN
++static int proc_get_scan_interval_thr(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	struct _ADAPTER *adapter= (struct _ADAPTER *)rtw_netdev_priv(dev);
++	struct registry_priv *rp = &adapter->registrypriv;
++
++
++	RTW_PRINT_SEL(m, "scan interval threshold = %u ms\n",
++		      rp->scan_interval_thr);
++
++	return 0;
++}
++
++static ssize_t proc_set_scan_interval_thr(struct file *file,
++				          const char __user *buffer,
++				          size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	struct _ADAPTER *adapter= (struct _ADAPTER *)rtw_netdev_priv(dev);
++	struct registry_priv *rp = &adapter->registrypriv;
++	char tmp[12];
++	int num = 0;
++	u32 thr = 0;
++
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (!buffer || copy_from_user(tmp, buffer, count))
++		goto exit;
++
++	num = sscanf(tmp, "%u", &thr);
++	if (num != 1) {
++		RTW_ERR("%s: invalid parameter!\n", __FUNCTION__);
++		goto exit;
++	}
++
++	rp->scan_interval_thr = thr;
++
++	RTW_PRINT("%s: scan interval threshold = %u ms\n",
++		  __FUNCTION__, rp->scan_interval_thr);
++
++exit:
++	return count;
++}
++
++#endif /* RTW_BUSY_DENY_SCAN */
++
++static int proc_get_scan_deny(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	struct _ADAPTER *adapter= (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++	RTW_PRINT_SEL(m, "scan_deny is %s\n", (dvobj->scan_deny == _TRUE) ? "enable":"disable");
++
++	return 0;
++}
++
++static ssize_t proc_set_scan_deny(struct file *file, const char __user *buffer,
++				size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	struct _ADAPTER *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	char tmp[8];
++	int num = 0;
++	int enable = 0;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (!buffer || copy_from_user(tmp, buffer, count))
++		goto exit;
++
++	num = sscanf(tmp, "%d", &enable);
++	if (num !=  1) {
++		RTW_ERR("%s: invalid parameter!\n", __FUNCTION__);
++		goto exit;
++	}
++
++	dvobj->scan_deny = enable ? _TRUE : _FALSE;
++
++	RTW_PRINT("%s: scan_deny is %s\n",
++		  __FUNCTION__, (dvobj->scan_deny == _TRUE) ? "enable":"disable");
++
++exit:
++	return count;
++}
++
++#ifdef CONFIG_RTW_TPT_MODE
++static int proc_get_tpt_mode(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	struct _ADAPTER *adapter= (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++	RTW_PRINT_SEL(m, "current tpt_mode = %d\n", dvobj->tpt_mode);
++
++	return 0;
++}
++
++static void tpt_mode_default(struct _ADAPTER *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++	/* 1. disable scan deny */
++	dvobj->scan_deny = _FALSE;
++
++	/* 2. back to original LPS mode */
++#ifdef CONFIG_LPS
++	rtw_pm_set_lps(adapter, adapter->registrypriv.power_mgnt);
++#endif
++
++	/* 3. back to original 2.4 tx bw mode */
++	rtw_set_tx_bw_mode(adapter, adapter->registrypriv.tx_bw_mode);
++}
++
++static void rtw_tpt_mode(struct _ADAPTER *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++
++	if (dvobj->tpt_mode > 0) {
++
++		/* when enable each tpt mode
++			1. scan deny
++			2. disable LPS */
++
++		dvobj->scan_deny = _TRUE;
++
++#ifdef CONFIG_LPS
++		rtw_pm_set_lps(adapter, PS_MODE_ACTIVE);
++#endif
++
++	}
++
++	switch (dvobj->tpt_mode) {
++		case 0: /* default mode */
++			tpt_mode_default(adapter);
++			break;
++		case 1: /* High TP*/
++			/*tpt_mode1(adapter);*/
++			dvobj->edca_be_ul = 0x5e431c;
++			dvobj->edca_be_dl = 0x00431c;
++			break;
++		case 2: /* noise */
++			/* tpt_mode2(adapter); */
++			dvobj->edca_be_ul = 0x00431c;
++			dvobj->edca_be_dl = 0x00431c;
++
++			rtw_set_tx_bw_mode(adapter, 0x20); /* for 2.4g, fixed tx_bw_mode to 20Mhz */
++			break;
++		case 3: /* long distance */
++			/* tpt_mode3(adapter); */
++			dvobj->edca_be_ul = 0x00431c;
++			dvobj->edca_be_dl = 0x00431c;
++
++			rtw_set_tx_bw_mode(adapter, 0x20); /* for 2.4g, fixed tx_bw_mode to 20Mhz */
++			break;
++		case 4: /* noise + long distance */
++			/* tpt_mode4(adapter); */
++			dvobj->edca_be_ul = 0x00431c;
++			dvobj->edca_be_dl = 0x00431c;
++
++			rtw_set_tx_bw_mode(adapter, 0x20); /* for 2.4g, fixed tx_bw_mode to 20Mhz */
++			break;
++		default: /* default mode */
++			tpt_mode_default(adapter);
++			break;
++	}
++
++}
++
++static ssize_t proc_set_tpt_mode(struct file *file, const char __user *buffer,
++				size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	struct _ADAPTER *adapter = (_adapter *)rtw_netdev_priv(dev);
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	char tmp[32];
++	int num = 0;
++	int mode = 0;
++
++#define MAX_TPT_MODE_NUM 4
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (!buffer || copy_from_user(tmp, buffer, count))
++		goto exit;
++
++	num = sscanf(tmp, "%d", &mode);
++	if (num !=  1) {
++		RTW_ERR("%s: invalid parameter!\n", __FUNCTION__);
++		goto exit;
++	}
++
++	if (mode > MAX_TPT_MODE_NUM )
++		mode = 0;
++
++	RTW_PRINT("%s: previous mode =  %d\n",
++		  __FUNCTION__, dvobj->tpt_mode);
++
++	RTW_PRINT("%s: enabled mode = %d\n",
++		  __FUNCTION__, mode);
++
++	dvobj->tpt_mode = mode;
++
++	rtw_tpt_mode(adapter);
++
++exit:
++	return count;
++
++}
++#endif /* CONFIG_RTW_TPT_MODE */
++
++int proc_get_cur_beacon_keys(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *adapter = rtw_netdev_priv(dev);
++	struct mlme_priv *mlme = &adapter->mlmepriv;
++
++	rtw_dump_bcn_keys(m, &mlme->cur_beacon_keys);
++
++	return 0;
++}
++
++/*
++* rtw_adapter_proc:
++* init/deinit when register/unregister net_device
++*/
++const struct rtw_proc_hdl adapter_proc_hdls[] = {
++#if RTW_SEQ_FILE_TEST
++	RTW_PROC_HDL_SEQ("seq_file_test", &seq_file_test, NULL),
++#endif
++	RTW_PROC_HDL_SSEQ("write_reg", NULL, proc_set_write_reg),
++	RTW_PROC_HDL_SSEQ("read_reg", proc_get_read_reg, proc_set_read_reg),
++	RTW_PROC_HDL_SSEQ("tx_rate_bmp", proc_get_dump_tx_rate_bmp, NULL),
++	RTW_PROC_HDL_SSEQ("adapters_status", proc_get_dump_adapters_status, NULL),
++#ifdef CONFIG_RTW_CUSTOMER_STR
++	RTW_PROC_HDL_SSEQ("customer_str", proc_get_customer_str, NULL),
++#endif
++	RTW_PROC_HDL_SSEQ("fwstate", proc_get_fwstate, NULL),
++	RTW_PROC_HDL_SSEQ("sec_info", proc_get_sec_info, NULL),
++	RTW_PROC_HDL_SSEQ("mlmext_state", proc_get_mlmext_state, NULL),
++	RTW_PROC_HDL_SSEQ("qos_option", proc_get_qos_option, NULL),
++	RTW_PROC_HDL_SSEQ("ht_option", proc_get_ht_option, NULL),
++	RTW_PROC_HDL_SSEQ("rf_info", proc_get_rf_info, NULL),
++	RTW_PROC_HDL_SSEQ("scan_param", proc_get_scan_param, proc_set_scan_param),
++	RTW_PROC_HDL_SSEQ("scan_abort", proc_get_scan_abort, NULL),
++#ifdef CONFIG_SCAN_BACKOP
++	RTW_PROC_HDL_SSEQ("backop_flags_sta", proc_get_backop_flags_sta, proc_set_backop_flags_sta),
++	#ifdef CONFIG_AP_MODE
++	RTW_PROC_HDL_SSEQ("backop_flags_ap", proc_get_backop_flags_ap, proc_set_backop_flags_ap),
++	#endif
++	#ifdef CONFIG_RTW_MESH
++	RTW_PROC_HDL_SSEQ("backop_flags_mesh", proc_get_backop_flags_mesh, proc_set_backop_flags_mesh),
++	#endif
++#endif
++#ifdef CONFIG_RTW_REPEATER_SON
++	RTW_PROC_HDL_SSEQ("rson_data", proc_get_rson_data, proc_set_rson_data),
++#endif
++	RTW_PROC_HDL_SSEQ("survey_info", proc_get_survey_info, proc_set_survey_info),
++	RTW_PROC_HDL_SSEQ("ap_info", proc_get_ap_info, NULL),
++#ifdef ROKU_PRIVATE
++	RTW_PROC_HDL_SSEQ("infra_ap", proc_get_infra_ap, NULL),
++#endif /* ROKU_PRIVATE */
++	RTW_PROC_HDL_SSEQ("trx_info", proc_get_trx_info, proc_reset_trx_info),
++	RTW_PROC_HDL_SSEQ("tx_power_offset", proc_get_tx_power_offset, proc_set_tx_power_offset),
++	RTW_PROC_HDL_SSEQ("rate_ctl", proc_get_rate_ctl, proc_set_rate_ctl),
++	RTW_PROC_HDL_SSEQ("bw_ctl", proc_get_bw_ctl, proc_set_bw_ctl),
++	RTW_PROC_HDL_SSEQ("mac_qinfo", proc_get_mac_qinfo, NULL),
++	RTW_PROC_HDL_SSEQ("macid_info", proc_get_macid_info, NULL),
++	RTW_PROC_HDL_SSEQ("bcmc_info", proc_get_mi_ap_bc_info, NULL),
++	RTW_PROC_HDL_SSEQ("sec_cam", proc_get_sec_cam, proc_set_sec_cam),
++	RTW_PROC_HDL_SSEQ("sec_cam_cache", proc_get_sec_cam_cache, NULL),
++	RTW_PROC_HDL_SSEQ("ps_dbg_info", proc_get_ps_dbg_info, proc_set_ps_dbg_info),
++	RTW_PROC_HDL_SSEQ("wifi_spec", proc_get_wifi_spec, NULL),
++#ifdef CONFIG_LAYER2_ROAMING
++	RTW_PROC_HDL_SSEQ("roam_flags", proc_get_roam_flags, proc_set_roam_flags),
++	RTW_PROC_HDL_SSEQ("roam_param", proc_get_roam_param, proc_set_roam_param),
++	RTW_PROC_HDL_SSEQ("roam_tgt_addr", NULL, proc_set_roam_tgt_addr),
++#endif /* CONFIG_LAYER2_ROAMING */
++#ifdef CONFIG_RTW_MBO
++	RTW_PROC_HDL_SSEQ("non_pref_ch", rtw_mbo_proc_non_pref_chans_get, rtw_mbo_proc_non_pref_chans_set),
++	RTW_PROC_HDL_SSEQ("cell_data", rtw_mbo_proc_cell_data_get, rtw_mbo_proc_cell_data_set),
++#endif
++#ifdef CONFIG_RTW_80211R
++	RTW_PROC_HDL_SSEQ("ft_flags", rtw_ft_proc_flags_get, rtw_ft_proc_flags_set),
++#endif
++	RTW_PROC_HDL_SSEQ("defs_param", proc_get_defs_param, proc_set_defs_param),
++#ifdef CONFIG_SDIO_HCI
++	RTW_PROC_HDL_SSEQ("sd_f0_reg_dump", proc_get_sd_f0_reg_dump, NULL),
++	RTW_PROC_HDL_SSEQ("sdio_local_reg_dump", proc_get_sdio_local_reg_dump, NULL),
++	RTW_PROC_HDL_SSEQ("sdio_card_info", proc_get_sdio_card_info, NULL),
++#ifdef DBG_SDIO
++	RTW_PROC_HDL_SSEQ("sdio_dbg", proc_get_sdio_dbg, proc_set_sdio_dbg),
++#endif /* DBG_SDIO */
++#endif /* CONFIG_SDIO_HCI */
++
++	RTW_PROC_HDL_SSEQ("fwdl_test_case", NULL, proc_set_fwdl_test_case),
++	RTW_PROC_HDL_SSEQ("del_rx_ampdu_test_case", NULL, proc_set_del_rx_ampdu_test_case),
++	RTW_PROC_HDL_SSEQ("wait_hiq_empty", NULL, proc_set_wait_hiq_empty),
++	RTW_PROC_HDL_SSEQ("sta_linking_test", NULL, proc_set_sta_linking_test),
++#ifdef CONFIG_AP_MODE
++	RTW_PROC_HDL_SSEQ("ap_linking_test", NULL, proc_set_ap_linking_test),
++#endif
++
++	RTW_PROC_HDL_SSEQ("mac_reg_dump", proc_get_mac_reg_dump, NULL),
++	RTW_PROC_HDL_SSEQ("bb_reg_dump", proc_get_bb_reg_dump, NULL),
++	RTW_PROC_HDL_SSEQ("bb_reg_dump_ex", proc_get_bb_reg_dump_ex, NULL),
++	RTW_PROC_HDL_SSEQ("rf_reg_dump", proc_get_rf_reg_dump, NULL),
++
++#ifdef CONFIG_RTW_LED
++	RTW_PROC_HDL_SSEQ("led_config", proc_get_led_config, proc_set_led_config),
++#endif
++
++#ifdef CONFIG_AP_MODE
++	RTW_PROC_HDL_SSEQ("aid_status", proc_get_aid_status, proc_set_aid_status),
++	RTW_PROC_HDL_SSEQ("ap_isolate", proc_get_ap_isolate, proc_set_ap_isolate),
++	RTW_PROC_HDL_SSEQ("all_sta_info", proc_get_all_sta_info, NULL),
++	RTW_PROC_HDL_SSEQ("bmc_tx_rate", proc_get_bmc_tx_rate, proc_set_bmc_tx_rate),
++	#if CONFIG_RTW_AP_DATA_BMC_TO_UC
++	RTW_PROC_HDL_SSEQ("ap_b2u_flags", proc_get_ap_b2u_flags, proc_set_ap_b2u_flags),
++	#endif
++#endif /* CONFIG_AP_MODE */
++
++#ifdef DBG_MEMORY_LEAK
++	RTW_PROC_HDL_SSEQ("_malloc_cnt", proc_get_malloc_cnt, NULL),
++#endif /* DBG_MEMORY_LEAK */
++
++#ifdef CONFIG_FIND_BEST_CHANNEL
++	RTW_PROC_HDL_SSEQ("best_channel", proc_get_best_channel, proc_set_best_channel),
++#endif
++
++	RTW_PROC_HDL_SSEQ("rx_signal", proc_get_rx_signal, proc_set_rx_signal),
++	RTW_PROC_HDL_SSEQ("rx_chk_limit", proc_get_rx_chk_limit, proc_set_rx_chk_limit),
++	RTW_PROC_HDL_SSEQ("hw_info", proc_get_hw_status, proc_set_hw_status),
++	RTW_PROC_HDL_SSEQ("mac_rptbuf", proc_get_mac_rptbuf, NULL),
++#ifdef CONFIG_80211N_HT
++	RTW_PROC_HDL_SSEQ("ht_enable", proc_get_ht_enable, proc_set_ht_enable),
++	RTW_PROC_HDL_SSEQ("bw_mode", proc_get_bw_mode, proc_set_bw_mode),
++	RTW_PROC_HDL_SSEQ("ampdu_enable", proc_get_ampdu_enable, proc_set_ampdu_enable),
++	RTW_PROC_HDL_SSEQ("rx_ampdu", proc_get_rx_ampdu, proc_set_rx_ampdu),
++	RTW_PROC_HDL_SSEQ("rx_ampdu_size_limit", proc_get_rx_ampdu_size_limit, proc_set_rx_ampdu_size_limit),
++	RTW_PROC_HDL_SSEQ("rx_ampdu_factor", proc_get_rx_ampdu_factor, proc_set_rx_ampdu_factor),
++	RTW_PROC_HDL_SSEQ("rx_ampdu_density", proc_get_rx_ampdu_density, proc_set_rx_ampdu_density),
++	RTW_PROC_HDL_SSEQ("tx_ampdu_density", proc_get_tx_ampdu_density, proc_set_tx_ampdu_density),
++	RTW_PROC_HDL_SSEQ("tx_max_agg_num", proc_get_tx_max_agg_num, proc_set_tx_max_agg_num),
++	RTW_PROC_HDL_SSEQ("tx_quick_addba_req", proc_get_tx_quick_addba_req, proc_set_tx_quick_addba_req),
++#ifdef CONFIG_TX_AMSDU
++	RTW_PROC_HDL_SSEQ("tx_amsdu", proc_get_tx_amsdu, proc_set_tx_amsdu),
++	RTW_PROC_HDL_SSEQ("tx_amsdu_rate", proc_get_tx_amsdu_rate, proc_set_tx_amsdu_rate),
++#endif
++#endif /* CONFIG_80211N_HT */
++
++	#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
++	RTW_PROC_HDL_SSEQ("tx_aval_int_threshold", proc_get_tx_aval_th, proc_set_tx_aval_th),
++	#endif
++
++	RTW_PROC_HDL_SSEQ("dynamic_rrsr", proc_get_dyn_rrsr, proc_set_dyn_rrsr),
++	RTW_PROC_HDL_SSEQ("en_fwps", proc_get_en_fwps, proc_set_en_fwps),
++
++	/* RTW_PROC_HDL_SSEQ("path_rssi", proc_get_two_path_rssi, NULL),
++	* 	RTW_PROC_HDL_SSEQ("rssi_disp",proc_get_rssi_disp, proc_set_rssi_disp), */
++
++#ifdef CONFIG_BT_COEXIST
++	RTW_PROC_HDL_SSEQ("btcoex_dbg", proc_get_btcoex_dbg, proc_set_btcoex_dbg),
++	RTW_PROC_HDL_SSEQ("btcoex", proc_get_btcoex_info, NULL),
++	RTW_PROC_HDL_SSEQ("btinfo_evt", NULL, proc_set_btinfo_evt),
++	RTW_PROC_HDL_SSEQ("btreg_read", proc_get_btreg_read, proc_set_btreg_read),
++	RTW_PROC_HDL_SSEQ("btreg_write", proc_get_btreg_write, proc_set_btreg_write),
++	RTW_PROC_HDL_SSEQ("btc_reduce_wl_txpwr", proc_get_btc_reduce_wl_txpwr, proc_set_btc_reduce_wl_txpwr),
++#ifdef CONFIG_RF4CE_COEXIST
++	RTW_PROC_HDL_SSEQ("rf4ce_state", proc_get_rf4ce_state, proc_set_rf4ce_state),
++#endif
++#endif /* CONFIG_BT_COEXIST */
++
++#if defined(DBG_CONFIG_ERROR_DETECT)
++	RTW_PROC_HDL_SSEQ("sreset", proc_get_sreset, proc_set_sreset),
++#endif /* DBG_CONFIG_ERROR_DETECT */
++	RTW_PROC_HDL_SSEQ("trx_info_debug", proc_get_trx_info_debug, NULL),
++
++#ifdef CONFIG_HUAWEI_PROC
++	RTW_PROC_HDL_SSEQ("huawei_trx_info", proc_get_huawei_trx_info, NULL),
++#endif
++	RTW_PROC_HDL_SSEQ("linked_info_dump", proc_get_linked_info_dump, proc_set_linked_info_dump),
++	RTW_PROC_HDL_SSEQ("sta_tp_dump", proc_get_sta_tp_dump, proc_set_sta_tp_dump),
++	RTW_PROC_HDL_SSEQ("sta_tp_info", proc_get_sta_tp_info, NULL),
++	RTW_PROC_HDL_SSEQ("dis_turboedca", proc_get_turboedca_ctrl, proc_set_turboedca_ctrl),
++	RTW_PROC_HDL_SSEQ("tx_info_msg", proc_get_tx_info_msg, NULL),
++	RTW_PROC_HDL_SSEQ("rx_info_msg", proc_get_rx_info_msg, proc_set_rx_info_msg),
++
++#if defined(CONFIG_LPS_PG) && defined(CONFIG_RTL8822C)
++	RTW_PROC_HDL_SSEQ("lps_pg_debug", proc_get_lps_pg_debug, NULL),
++#endif
++
++#ifdef CONFIG_GPIO_API
++	RTW_PROC_HDL_SSEQ("gpio_info", proc_get_gpio, proc_set_gpio),
++	RTW_PROC_HDL_SSEQ("gpio_set_output_value", NULL, proc_set_gpio_output_value),
++	RTW_PROC_HDL_SSEQ("gpio_set_direction", NULL, proc_set_config_gpio),
++#endif
++
++#ifdef CONFIG_DBG_COUNTER
++	RTW_PROC_HDL_SSEQ("rx_logs", proc_get_rx_logs, NULL),
++	RTW_PROC_HDL_SSEQ("tx_logs", proc_get_tx_logs, NULL),
++	RTW_PROC_HDL_SSEQ("int_logs", proc_get_int_logs, NULL),
++#endif
++
++#ifdef CONFIG_DBG_RF_CAL
++	RTW_PROC_HDL_SSEQ("iqk", proc_get_iqk_info, proc_set_iqk),
++	RTW_PROC_HDL_SSEQ("lck", proc_get_lck_info, proc_set_lck),
++#endif
++
++#ifdef CONFIG_PCI_HCI
++	RTW_PROC_HDL_SSEQ("rx_ring", proc_get_rx_ring, NULL),
++	RTW_PROC_HDL_SSEQ("tx_ring", proc_get_tx_ring, NULL),
++#ifdef DBG_TXBD_DESC_DUMP
++	RTW_PROC_HDL_SSEQ("tx_ring_ext", proc_get_tx_ring_ext, proc_set_tx_ring_ext),
++#endif
++	RTW_PROC_HDL_SSEQ("pci_aspm", proc_get_pci_aspm, NULL),
++
++	RTW_PROC_HDL_SSEQ("pci_conf_space", proc_get_pci_conf_space, proc_set_pci_conf_space),
++
++	RTW_PROC_HDL_SSEQ("pci_bridge_conf_space", proc_get_pci_bridge_conf_space, proc_set_pci_bridge_conf_space),
++
++#endif
++
++#ifdef CONFIG_WOWLAN
++	RTW_PROC_HDL_SSEQ("wow_enable", proc_get_wow_enable, proc_set_wow_enable),
++	RTW_PROC_HDL_SSEQ("wow_pattern_info", proc_get_pattern_info, proc_set_pattern_info),
++	RTW_PROC_HDL_SSEQ("wow_wakeup_event", proc_get_wakeup_event,
++			  proc_set_wakeup_event),
++	RTW_PROC_HDL_SSEQ("wowlan_last_wake_reason", proc_get_wakeup_reason, NULL),
++#ifdef CONFIG_WOW_PATTERN_HW_CAM
++	RTW_PROC_HDL_SSEQ("wow_pattern_cam", proc_dump_pattern_cam, NULL),
++#endif
++#endif
++
++#ifdef CONFIG_GPIO_WAKEUP
++	RTW_PROC_HDL_SSEQ("wowlan_gpio_info", proc_get_wowlan_gpio_info, proc_set_wowlan_gpio_info),
++#endif
++#ifdef CONFIG_P2P_WOWLAN
++	RTW_PROC_HDL_SSEQ("p2p_wowlan_info", proc_get_p2p_wowlan_info, NULL),
++#endif
++	RTW_PROC_HDL_SSEQ("country_code", proc_get_country_code, proc_set_country_code),
++	RTW_PROC_HDL_SSEQ("chan_plan", proc_get_chan_plan, proc_set_chan_plan),
++	RTW_PROC_HDL_SSEQ("cap_spt_op_class_ch", proc_get_cap_spt_op_class_ch, NULL),
++	RTW_PROC_HDL_SSEQ("cur_spt_op_class_ch", proc_get_cur_spt_op_class_ch, NULL),
++#if CONFIG_RTW_MACADDR_ACL
++	RTW_PROC_HDL_SSEQ("macaddr_acl", proc_get_macaddr_acl, proc_set_macaddr_acl),
++#endif
++#if CONFIG_RTW_PRE_LINK_STA
++	RTW_PROC_HDL_SSEQ("pre_link_sta", proc_get_pre_link_sta, proc_set_pre_link_sta),
++#endif
++	RTW_PROC_HDL_SSEQ("ch_sel_policy", proc_get_ch_sel_policy, proc_set_ch_sel_policy),
++#ifdef CONFIG_DFS_MASTER
++	RTW_PROC_HDL_SSEQ("dfs_test_case", proc_get_dfs_test_case, proc_set_dfs_test_case),
++	RTW_PROC_HDL_SSEQ("update_non_ocp", NULL, proc_set_update_non_ocp),
++	RTW_PROC_HDL_SSEQ("radar_detect", NULL, proc_set_radar_detect),
++	RTW_PROC_HDL_SSEQ("dfs_ch_sel_d_flags", proc_get_dfs_ch_sel_d_flags, proc_set_dfs_ch_sel_d_flags),
++	#if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
++	RTW_PROC_HDL_SSEQ("dfs_slave_with_rd", proc_get_dfs_slave_with_rd, proc_set_dfs_slave_with_rd),
++	#endif
++#endif
++#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
++	RTW_PROC_HDL_SSEQ("new_bcn_max", proc_get_new_bcn_max, proc_set_new_bcn_max),
++#endif
++	RTW_PROC_HDL_SSEQ("sink_udpport", proc_get_udpport, proc_set_udpport),
++#ifdef DBG_RX_COUNTER_DUMP
++	RTW_PROC_HDL_SSEQ("dump_rx_cnt_mode", proc_get_rx_cnt_dump, proc_set_rx_cnt_dump),
++#endif
++	RTW_PROC_HDL_SSEQ("change_bss_chbw", NULL, proc_set_change_bss_chbw),
++#if CONFIG_TX_AC_LIFETIME
++	RTW_PROC_HDL_SSEQ("tx_aclt_force_val", proc_get_tx_aclt_force_val, proc_set_tx_aclt_force_val),
++	RTW_PROC_HDL_SSEQ("tx_aclt_flags", proc_get_tx_aclt_flags, proc_set_tx_aclt_flags),
++	RTW_PROC_HDL_SSEQ("tx_aclt_confs", proc_get_tx_aclt_confs, proc_set_tx_aclt_confs),
++#endif
++	RTW_PROC_HDL_SSEQ("tx_bw_mode", proc_get_tx_bw_mode, proc_set_tx_bw_mode),
++	RTW_PROC_HDL_SSEQ("hal_txpwr_info", proc_get_hal_txpwr_info, NULL),
++	RTW_PROC_HDL_SSEQ("target_tx_power", proc_get_target_tx_power, NULL),
++	RTW_PROC_HDL_SSEQ("tx_power_by_rate", proc_get_tx_power_by_rate, NULL),
++#if CONFIG_TXPWR_LIMIT
++	RTW_PROC_HDL_SSEQ("tx_power_limit", proc_get_tx_power_limit, NULL),
++#endif
++	RTW_PROC_HDL_SSEQ("tx_power_ext_info", proc_get_tx_power_ext_info, proc_set_tx_power_ext_info),
++	RTW_PROC_HDL_SEQ("tx_power_idx", &seq_ops_tx_power_idx, proc_set_tx_power_idx_dump),
++	RTW_PROC_HDL_SEQ("txpwr_total_dbm", &seq_ops_txpwr_total_dbm, proc_set_txpwr_total_dbm_dump),
++#ifdef CONFIG_RF_POWER_TRIM
++	RTW_PROC_HDL_SSEQ("tx_gain_offset", NULL, proc_set_tx_gain_offset),
++	RTW_PROC_HDL_SSEQ("kfree_flag", proc_get_kfree_flag, proc_set_kfree_flag),
++	RTW_PROC_HDL_SSEQ("kfree_bb_gain", proc_get_kfree_bb_gain, proc_set_kfree_bb_gain),
++	RTW_PROC_HDL_SSEQ("kfree_thermal", proc_get_kfree_thermal, proc_set_kfree_thermal),
++#endif
++#ifdef CONFIG_POWER_SAVING
++	RTW_PROC_HDL_SSEQ("ps_info", proc_get_ps_info, proc_set_ps_info),
++#ifdef CONFIG_WMMPS_STA
++	RTW_PROC_HDL_SSEQ("wmmps_info", proc_get_wmmps_info, proc_set_wmmps_info),
++#endif /* CONFIG_WMMPS_STA */
++#endif
++#ifdef CONFIG_TDLS
++	RTW_PROC_HDL_SSEQ("tdls_info", proc_get_tdls_info, NULL),
++	RTW_PROC_HDL_SSEQ("tdls_enable", proc_get_tdls_enable, proc_set_tdls_enable),
++#endif
++	RTW_PROC_HDL_SSEQ("monitor", proc_get_monitor, proc_set_monitor),
++#ifdef RTW_SIMPLE_CONFIG
++	RTW_PROC_HDL_SSEQ("rtw_simple_config", proc_get_simple_config, proc_set_simple_config),
++#endif
++
++#ifdef CONFIG_RTW_ACS
++	RTW_PROC_HDL_SSEQ("acs", proc_get_best_chan, proc_set_acs),
++	RTW_PROC_HDL_SSEQ("chan_info", proc_get_chan_info, NULL),
++#endif
++
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++	RTW_PROC_HDL_SSEQ("noise_monitor", proc_get_nm, proc_set_nm),
++#endif
++
++#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
++	RTW_PROC_HDL_SSEQ("rtkm_info", proc_get_rtkm_info, NULL),
++#endif
++	RTW_PROC_HDL_SSEQ("efuse_map", proc_get_efuse_map, NULL),
++#ifdef CONFIG_IEEE80211W
++	RTW_PROC_HDL_SSEQ("11w_tx_sa_query", proc_get_tx_sa_query, proc_set_tx_sa_query),
++	RTW_PROC_HDL_SSEQ("11w_tx_deauth", proc_get_tx_deauth, proc_set_tx_deauth),
++	RTW_PROC_HDL_SSEQ("11w_tx_auth", proc_get_tx_auth, proc_set_tx_auth),
++#endif /* CONFIG_IEEE80211W */
++
++#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
++	RTW_PROC_HDL_SSEQ("pathb_phase", proc_get_pathb_phase, proc_set_pathb_phase),
++#endif
++
++#ifdef CONFIG_MBSSID_CAM
++	RTW_PROC_HDL_SSEQ("mbid_cam", proc_get_mbid_cam_cache, NULL),
++#endif
++	RTW_PROC_HDL_SSEQ("mac_addr", proc_get_mac_addr, NULL),
++	RTW_PROC_HDL_SSEQ("skip_band", proc_get_skip_band, proc_set_skip_band),
++	RTW_PROC_HDL_SSEQ("hal_spec", proc_get_hal_spec, NULL),
++	RTW_PROC_HDL_SSEQ("hal_trx_mode", proc_get_hal_trx_mode, NULL),
++
++	RTW_PROC_HDL_SSEQ("rx_stat", proc_get_rx_stat, NULL),
++
++	RTW_PROC_HDL_SSEQ("tx_stat", proc_get_tx_stat, NULL),
++	/**** PHY Capability ****/
++	RTW_PROC_HDL_SSEQ("phy_cap", proc_get_phy_cap, NULL),
++#ifdef CONFIG_80211N_HT
++	RTW_PROC_HDL_SSEQ("rx_stbc", proc_get_rx_stbc, proc_set_rx_stbc),
++	RTW_PROC_HDL_SSEQ("stbc_cap", proc_get_stbc_cap, proc_set_stbc_cap),
++	RTW_PROC_HDL_SSEQ("ldpc_cap", proc_get_ldpc_cap, proc_set_ldpc_cap),
++#endif /* CONFIG_80211N_HT */
++#ifdef CONFIG_BEAMFORMING
++	RTW_PROC_HDL_SSEQ("txbf_cap", proc_get_txbf_cap, proc_set_txbf_cap),
++#endif
++
++#ifdef CONFIG_SUPPORT_TRX_SHARED
++	RTW_PROC_HDL_SSEQ("trx_share_mode", proc_get_trx_share_mode, NULL),
++#endif
++	RTW_PROC_HDL_SSEQ("napi_info", proc_get_napi_info, NULL),
++#ifdef CONFIG_RTW_NAPI_DYNAMIC
++	RTW_PROC_HDL_SSEQ("napi_th", proc_get_napi_info, proc_set_napi_th),
++#endif /* CONFIG_RTW_NAPI_DYNAMIC */
++
++	RTW_PROC_HDL_SSEQ("rsvd_page", proc_dump_rsvd_page, proc_set_rsvd_page_info),
++
++#ifdef CONFIG_SUPPORT_FIFO_DUMP
++	RTW_PROC_HDL_SSEQ("fifo_dump", proc_dump_fifo, proc_set_fifo_info),
++#endif
++	RTW_PROC_HDL_SSEQ("fw_info", proc_get_fw_info, NULL),
++
++#ifdef DBG_XMIT_BLOCK
++	RTW_PROC_HDL_SSEQ("xmit_block", proc_get_xmit_block, proc_set_xmit_block),
++#endif
++
++	RTW_PROC_HDL_SSEQ("ack_timeout", proc_get_ack_timeout, proc_set_ack_timeout),
++
++	RTW_PROC_HDL_SSEQ("dynamic_agg_enable", proc_get_dynamic_agg_enable, proc_set_dynamic_agg_enable),
++	RTW_PROC_HDL_SSEQ("fw_offload", proc_get_fw_offload, proc_set_fw_offload),
++
++#ifdef CONFIG_RTW_WDS
++	RTW_PROC_HDL_SSEQ("wds_en", proc_get_wds_en, proc_set_wds_en),
++	RTW_PROC_HDL_SSEQ("sta_wds_en", NULL, proc_set_sta_wds_en),
++	#ifdef CONFIG_AP_MODE
++	RTW_PROC_HDL_SSEQ("wds_path", proc_get_wds_path, NULL),
++	#endif
++#endif
++
++#ifdef CONFIG_RTW_MULTI_AP
++	RTW_PROC_HDL_SSEQ("multi_ap_opmode", proc_get_multi_ap_opmode, proc_set_multi_ap_opmode),
++#ifdef CONFIG_IOCTL_CFG80211
++	RTW_PROC_HDL_SSEQ("sta_assoc_req_frame_body", proc_get_sta_assoc_req_frame_body, proc_set_sta_assoc_req_frame_body),
++#endif
++#endif
++
++#ifdef CONFIG_RTW_MESH
++	#if CONFIG_RTW_MESH_ACNODE_PREVENT
++	RTW_PROC_HDL_SSEQ("mesh_acnode_prevent", proc_get_mesh_acnode_prevent, proc_set_mesh_acnode_prevent),
++	#endif
++	#if CONFIG_RTW_MESH_OFFCH_CAND
++	RTW_PROC_HDL_SSEQ("mesh_offch_cand", proc_get_mesh_offch_cand, proc_set_mesh_offch_cand),
++	#endif
++	#if CONFIG_RTW_MESH_PEER_BLACKLIST
++	RTW_PROC_HDL_SSEQ("mesh_peer_blacklist", proc_get_mesh_peer_blacklist, proc_set_mesh_peer_blacklist),
++	#endif
++	#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
++	RTW_PROC_HDL_SSEQ("mesh_cto_mgate_require", proc_get_mesh_cto_mgate_require, proc_set_mesh_cto_mgate_require),
++	RTW_PROC_HDL_SSEQ("mesh_cto_mgate_blacklist", proc_get_mesh_cto_mgate_blacklist, proc_set_mesh_cto_mgate_blacklist),
++	#endif
++	RTW_PROC_HDL_SSEQ("mesh_peer_sel_policy", proc_get_mesh_peer_sel_policy, NULL),
++	RTW_PROC_HDL_SSEQ("mesh_networks", proc_get_mesh_networks, NULL),
++	RTW_PROC_HDL_SSEQ("mesh_plink_ctl", proc_get_mesh_plink_ctl, NULL),
++	RTW_PROC_HDL_SSEQ("mesh_mpath", proc_get_mesh_mpath, NULL),
++	RTW_PROC_HDL_SSEQ("mesh_mpp", proc_get_mesh_mpp, NULL),
++	RTW_PROC_HDL_SSEQ("mesh_known_gates", proc_get_mesh_known_gates, NULL),
++	#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
++	RTW_PROC_HDL_SSEQ("mesh_b2u_flags", proc_get_mesh_b2u_flags, proc_set_mesh_b2u_flags),
++	#endif
++	RTW_PROC_HDL_SSEQ("mesh_stats", proc_get_mesh_stats, NULL),
++	RTW_PROC_HDL_SSEQ("mesh_gate_timeout_factor", proc_get_mesh_gate_timeout, proc_set_mesh_gate_timeout),
++	RTW_PROC_HDL_SSEQ("mesh_gate_state", proc_get_mesh_gate_state, NULL),
++	RTW_PROC_HDL_SSEQ("mesh_peer_alive_based_preq", proc_get_peer_alive_based_preq, proc_set_peer_alive_based_preq),
++#endif
++#ifdef CONFIG_FW_HANDLE_TXBCN
++	RTW_PROC_HDL_SSEQ("fw_tbtt_rpt", proc_get_fw_tbtt_rpt, proc_set_fw_tbtt_rpt),
++#endif
++#ifdef CONFIG_LPS_CHK_BY_TP
++	RTW_PROC_HDL_SSEQ("lps_chk_tp", proc_get_lps_chk_tp, proc_set_lps_chk_tp),
++#endif
++#ifdef CONFIG_SUPPORT_STATIC_SMPS
++	RTW_PROC_HDL_SSEQ("smps", proc_get_smps, proc_set_smps),
++#endif
++
++#ifdef RTW_BUSY_DENY_SCAN
++	RTW_PROC_HDL_SSEQ("scan_interval_thr", proc_get_scan_interval_thr, \
++			  proc_set_scan_interval_thr),
++#endif
++	RTW_PROC_HDL_SSEQ("scan_deny", proc_get_scan_deny, proc_set_scan_deny),
++#ifdef CONFIG_RTW_TPT_MODE
++	RTW_PROC_HDL_SSEQ("tpt_mode", proc_get_tpt_mode, proc_set_tpt_mode),
++#endif
++
++#ifdef CONFIG_CTRL_TXSS_BY_TP
++	RTW_PROC_HDL_SSEQ("txss_tp", proc_get_txss_tp, proc_set_txss_tp),
++	#ifdef DBG_CTRL_TXSS
++	RTW_PROC_HDL_SSEQ("txss_ctrl", proc_get_txss_ctrl, proc_set_txss_ctrl),
++	#endif
++#endif
++
++	RTW_PROC_HDL_SSEQ("cur_beacon_keys", proc_get_cur_beacon_keys, NULL),
++};
++
++const int adapter_proc_hdls_num = sizeof(adapter_proc_hdls) / sizeof(struct rtw_proc_hdl);
++
++static int rtw_adapter_proc_open(struct inode *inode, struct file *file)
++{
++	ssize_t index = (ssize_t)PDE_DATA(inode);
++	const struct rtw_proc_hdl *hdl = adapter_proc_hdls + index;
++	void *private = proc_get_parent_data(inode);
++
++	if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {
++		int res = seq_open(file, hdl->u.seq_op);
++
++		if (res == 0)
++			((struct seq_file *)file->private_data)->private = private;
++
++		return res;
++	} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {
++		int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;
++
++		return single_open(file, show, private);
++	} else if (hdl->type == RTW_PROC_HDL_TYPE_SZSEQ) {
++		int (*show)(struct seq_file *, void *) = hdl->u.sz.show ? hdl->u.sz.show : proc_get_dummy;
++
++		return single_open_size(file, show, private, hdl->u.sz.size);
++	} else {
++		return -EROFS;
++	}
++}
++
++static ssize_t rtw_adapter_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)
++{
++	ssize_t index = (ssize_t)PDE_DATA(file_inode(file));
++	const struct rtw_proc_hdl *hdl = adapter_proc_hdls + index;
++	ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;
++
++	if (write)
++		return write(file, buffer, count, pos, ((struct seq_file *)file->private_data)->private);
++
++	return -EROFS;
++}
++
++static const struct file_operations rtw_adapter_proc_seq_fops = {
++	.owner = THIS_MODULE,
++	.open = rtw_adapter_proc_open,
++	.read = seq_read,
++	.llseek = seq_lseek,
++	.release = seq_release,
++	.write = rtw_adapter_proc_write,
++};
++
++static const struct file_operations rtw_adapter_proc_sseq_fops = {
++	.owner = THIS_MODULE,
++	.open = rtw_adapter_proc_open,
++	.read = seq_read,
++	.llseek = seq_lseek,
++	.release = single_release,
++	.write = rtw_adapter_proc_write,
++};
++
++int proc_get_odm_adaptivity(struct seq_file *m, void *v)
++{
++	struct net_device *dev = m->private;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++
++	rtw_odm_adaptivity_parm_msg(m, padapter);
++
++	return 0;
++}
++
++ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *dev = data;
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
++	char tmp[32];
++	u32 th_l2h_ini;
++	s8 th_edcca_hl_diff;
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp)) {
++		rtw_warn_on(1);
++		return -EFAULT;
++	}
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++
++		int num = sscanf(tmp, "%x %hhd", &th_l2h_ini, &th_edcca_hl_diff);
++
++		if (num != 2)
++			return count;
++
++		rtw_odm_adaptivity_parm_set(padapter, (s8)th_l2h_ini, th_edcca_hl_diff);
++	}
++
++	return count;
++}
++
++static char *phydm_msg = NULL;
++#define PHYDM_MSG_LEN	80*24*4
++
++int proc_get_phydm_cmd(struct seq_file *m, void *v)
++{
++	struct net_device *netdev;
++	PADAPTER padapter;
++	struct dm_struct *phydm;
++
++
++	netdev = m->private;
++	padapter = (PADAPTER)rtw_netdev_priv(netdev);
++	phydm = adapter_to_phydm(padapter);
++
++	if (NULL == phydm_msg) {
++		phydm_msg = rtw_zmalloc(PHYDM_MSG_LEN);
++		if (NULL == phydm_msg)
++			return -ENOMEM;
++
++		phydm_cmd(phydm, NULL, 0, 0, phydm_msg, PHYDM_MSG_LEN);
++	}
++
++	_RTW_PRINT_SEL(m, "%s\n", phydm_msg);
++
++	rtw_mfree(phydm_msg, PHYDM_MSG_LEN);
++	phydm_msg = NULL;
++
++	return 0;
++}
++
++ssize_t proc_set_phydm_cmd(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
++{
++	struct net_device *netdev;
++	PADAPTER padapter;
++	struct dm_struct *phydm;
++	char tmp[64] = {0};
++
++
++	netdev = (struct net_device *)data;
++	padapter = (PADAPTER)rtw_netdev_priv(netdev);
++	phydm = adapter_to_phydm(padapter);
++
++	if (count < 1)
++		return -EFAULT;
++
++	if (count > sizeof(tmp))
++		return -EFAULT;
++
++	if (buffer && !copy_from_user(tmp, buffer, count)) {
++		if (NULL == phydm_msg) {
++			phydm_msg = rtw_zmalloc(PHYDM_MSG_LEN);
++			if (NULL == phydm_msg)
++				return -ENOMEM;
++		} else
++			_rtw_memset(phydm_msg, 0, PHYDM_MSG_LEN);
++
++		phydm_cmd(phydm, tmp, count, 1, phydm_msg, PHYDM_MSG_LEN);
++
++		if (strlen(phydm_msg) == 0) {
++			rtw_mfree(phydm_msg, PHYDM_MSG_LEN);
++			phydm_msg = NULL;
++		}
++	}
++
++	return count;
++}
++
++/*
++* rtw_odm_proc:
++* init/deinit when register/unregister net_device, along with rtw_adapter_proc
++*/
++const struct rtw_proc_hdl odm_proc_hdls[] = {
++	RTW_PROC_HDL_SSEQ("adaptivity", proc_get_odm_adaptivity, proc_set_odm_adaptivity),
++	RTW_PROC_HDL_SZSEQ("cmd", proc_get_phydm_cmd, proc_set_phydm_cmd, PHYDM_MSG_LEN),
++};
++
++const int odm_proc_hdls_num = sizeof(odm_proc_hdls) / sizeof(struct rtw_proc_hdl);
++
++static int rtw_odm_proc_open(struct inode *inode, struct file *file)
++{
++	ssize_t index = (ssize_t)PDE_DATA(inode);
++	const struct rtw_proc_hdl *hdl = odm_proc_hdls + index;
++	void *private = proc_get_parent_data(inode);
++
++	if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {
++		int res = seq_open(file, hdl->u.seq_op);
++
++		if (res == 0)
++			((struct seq_file *)file->private_data)->private = private;
++
++		return res;
++	} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {
++		int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;
++
++		return single_open(file, show, private);
++	} else if (hdl->type == RTW_PROC_HDL_TYPE_SZSEQ) {
++		int (*show)(struct seq_file *, void *) = hdl->u.sz.show ? hdl->u.sz.show : proc_get_dummy;
++
++		return single_open_size(file, show, private, hdl->u.sz.size);
++	} else {
++		return -EROFS;
++	}
++}
++
++static ssize_t rtw_odm_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)
++{
++	ssize_t index = (ssize_t)PDE_DATA(file_inode(file));
++	const struct rtw_proc_hdl *hdl = odm_proc_hdls + index;
++	ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;
++
++	if (write)
++		return write(file, buffer, count, pos, ((struct seq_file *)file->private_data)->private);
++
++	return -EROFS;
++}
++
++static const struct file_operations rtw_odm_proc_seq_fops = {
++	.owner = THIS_MODULE,
++	.open = rtw_odm_proc_open,
++	.read = seq_read,
++	.llseek = seq_lseek,
++	.release = seq_release,
++	.write = rtw_odm_proc_write,
++};
++
++static const struct file_operations rtw_odm_proc_sseq_fops = {
++	.owner = THIS_MODULE,
++	.open = rtw_odm_proc_open,
++	.read = seq_read,
++	.llseek = seq_lseek,
++	.release = single_release,
++	.write = rtw_odm_proc_write,
++};
++
++struct proc_dir_entry *rtw_odm_proc_init(struct net_device *dev)
++{
++	struct proc_dir_entry *dir_odm = NULL;
++	struct proc_dir_entry *entry = NULL;
++	_adapter	*adapter = rtw_netdev_priv(dev);
++	ssize_t i;
++
++	if (adapter->dir_dev == NULL) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (adapter->dir_odm != NULL) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	dir_odm = rtw_proc_create_dir("odm", adapter->dir_dev, dev);
++	if (dir_odm == NULL) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	adapter->dir_odm = dir_odm;
++
++	for (i = 0; i < odm_proc_hdls_num; i++) {
++		if (odm_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)
++			entry = rtw_proc_create_entry(odm_proc_hdls[i].name, dir_odm, &rtw_odm_proc_seq_fops, (void *)i);
++		else if (odm_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ ||
++			 odm_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SZSEQ)
++			entry = rtw_proc_create_entry(odm_proc_hdls[i].name, dir_odm, &rtw_odm_proc_sseq_fops, (void *)i);
++		else
++			entry = NULL;
++
++		if (!entry) {
++			rtw_warn_on(1);
++			goto exit;
++		}
++	}
++
++exit:
++	return dir_odm;
++}
++
++void rtw_odm_proc_deinit(_adapter	*adapter)
++{
++	struct proc_dir_entry *dir_odm = NULL;
++	int i;
++
++	dir_odm = adapter->dir_odm;
++
++	if (dir_odm == NULL) {
++		rtw_warn_on(1);
++		return;
++	}
++
++	for (i = 0; i < odm_proc_hdls_num; i++)
++		remove_proc_entry(odm_proc_hdls[i].name, dir_odm);
++
++	remove_proc_entry("odm", adapter->dir_dev);
++
++	adapter->dir_odm = NULL;
++
++	if (phydm_msg) {
++		rtw_mfree(phydm_msg, PHYDM_MSG_LEN);
++		phydm_msg = NULL;
++	}
++}
++
++#ifdef CONFIG_MCC_MODE
++/*
++* rtw_mcc_proc:
++* init/deinit when register/unregister net_device, along with rtw_adapter_proc
++*/
++const struct rtw_proc_hdl mcc_proc_hdls[] = {
++	RTW_PROC_HDL_SSEQ("mcc_info", proc_get_mcc_info, NULL),
++	RTW_PROC_HDL_SSEQ("mcc_enable", proc_get_mcc_info, proc_set_mcc_enable),
++	RTW_PROC_HDL_SSEQ("mcc_duration", proc_get_mcc_info, proc_set_mcc_duration),
++	#ifdef CONFIG_MCC_PHYDM_OFFLOAD
++	RTW_PROC_HDL_SSEQ("mcc_phydm_offload", proc_get_mcc_info, proc_set_mcc_phydm_offload_enable),
++	#endif
++	RTW_PROC_HDL_SSEQ("mcc_single_tx_criteria", proc_get_mcc_info, proc_set_mcc_single_tx_criteria),
++	RTW_PROC_HDL_SSEQ("mcc_ap_bw20_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw20_target_tp),
++	RTW_PROC_HDL_SSEQ("mcc_ap_bw40_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw40_target_tp),
++	RTW_PROC_HDL_SSEQ("mcc_ap_bw80_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw80_target_tp),
++	RTW_PROC_HDL_SSEQ("mcc_sta_bw20_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw20_target_tp),
++	RTW_PROC_HDL_SSEQ("mcc_sta_bw40_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw40_target_tp),
++	RTW_PROC_HDL_SSEQ("mcc_sta_bw80_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw80_target_tp),
++	RTW_PROC_HDL_SSEQ("mcc_policy_table", proc_get_mcc_policy_table, NULL),
++};
++
++const int mcc_proc_hdls_num = sizeof(mcc_proc_hdls) / sizeof(struct rtw_proc_hdl);
++
++static int rtw_mcc_proc_open(struct inode *inode, struct file *file)
++{
++	ssize_t index = (ssize_t)PDE_DATA(inode);
++	const struct rtw_proc_hdl *hdl = mcc_proc_hdls + index;
++	void *private = proc_get_parent_data(inode);
++
++	if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {
++		int res = seq_open(file, hdl->u.seq_op);
++
++		if (res == 0)
++			((struct seq_file *)file->private_data)->private = private;
++
++		return res;
++	} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {
++		int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;
++
++		return single_open(file, show, private);
++	} else if (hdl->type == RTW_PROC_HDL_TYPE_SZSEQ) {
++		int (*show)(struct seq_file *, void *) = hdl->u.sz.show ? hdl->u.sz.show : proc_get_dummy;
++
++		return single_open_size(file, show, private, hdl->u.sz.size);
++	} else {
++		return -EROFS;
++	}
++}
++
++static ssize_t rtw_mcc_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)
++{
++	ssize_t index = (ssize_t)PDE_DATA(file_inode(file));
++	const struct rtw_proc_hdl *hdl = mcc_proc_hdls + index;
++	ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;
++
++	if (write)
++		return write(file, buffer, count, pos, ((struct seq_file *)file->private_data)->private);
++
++	return -EROFS;
++}
++
++static const struct file_operations rtw_mcc_proc_seq_fops = {
++	.owner = THIS_MODULE,
++	.open = rtw_mcc_proc_open,
++	.read = seq_read,
++	.llseek = seq_lseek,
++	.release = seq_release,
++	.write = rtw_mcc_proc_write,
++};
++
++static const struct file_operations rtw_mcc_proc_sseq_fops = {
++	.owner = THIS_MODULE,
++	.open = rtw_mcc_proc_open,
++	.read = seq_read,
++	.llseek = seq_lseek,
++	.release = single_release,
++	.write = rtw_mcc_proc_write,
++};
++
++struct proc_dir_entry *rtw_mcc_proc_init(struct net_device *dev)
++{
++	struct proc_dir_entry *dir_mcc = NULL;
++	struct proc_dir_entry *entry = NULL;
++	_adapter	*adapter = rtw_netdev_priv(dev);
++	ssize_t i;
++
++	if (adapter->dir_dev == NULL) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (adapter->dir_mcc != NULL) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	dir_mcc = rtw_proc_create_dir("mcc", adapter->dir_dev, dev);
++	if (dir_mcc == NULL) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	adapter->dir_mcc = dir_mcc;
++
++	for (i = 0; i < mcc_proc_hdls_num; i++) {
++		if (mcc_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)
++			entry = rtw_proc_create_entry(mcc_proc_hdls[i].name, dir_mcc, &rtw_mcc_proc_seq_fops, (void *)i);
++		else if (mcc_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ ||
++			 mcc_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SZSEQ)
++			entry = rtw_proc_create_entry(mcc_proc_hdls[i].name, dir_mcc, &rtw_mcc_proc_sseq_fops, (void *)i);
++		else
++			entry = NULL;
++
++		if (!entry) {
++			rtw_warn_on(1);
++			goto exit;
++		}
++	}
++
++exit:
++	return dir_mcc;
++}
++
++void rtw_mcc_proc_deinit(_adapter	*adapter)
++{
++	struct proc_dir_entry *dir_mcc = NULL;
++	int i;
++
++	dir_mcc = adapter->dir_mcc;
++
++	if (dir_mcc == NULL) {
++		rtw_warn_on(1);
++		return;
++	}
++
++	for (i = 0; i < mcc_proc_hdls_num; i++)
++		remove_proc_entry(mcc_proc_hdls[i].name, dir_mcc);
++
++	remove_proc_entry("mcc", adapter->dir_dev);
++
++	adapter->dir_mcc = NULL;
++}
++#endif /* CONFIG_MCC_MODE */
++
++struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev)
++{
++	struct proc_dir_entry *drv_proc = get_rtw_drv_proc();
++	struct proc_dir_entry *dir_dev = NULL;
++	struct proc_dir_entry *entry = NULL;
++	_adapter *adapter = rtw_netdev_priv(dev);
++	ssize_t i;
++
++	if (drv_proc == NULL) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (adapter->dir_dev != NULL) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	dir_dev = rtw_proc_create_dir(dev->name, drv_proc, dev);
++	if (dir_dev == NULL) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	adapter->dir_dev = dir_dev;
++
++	for (i = 0; i < adapter_proc_hdls_num; i++) {
++		if (adapter_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)
++			entry = rtw_proc_create_entry(adapter_proc_hdls[i].name, dir_dev, &rtw_adapter_proc_seq_fops, (void *)i);
++		else if (adapter_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ ||
++			 adapter_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SZSEQ)
++			entry = rtw_proc_create_entry(adapter_proc_hdls[i].name, dir_dev, &rtw_adapter_proc_sseq_fops, (void *)i);
++		else
++			entry = NULL;
++
++		if (!entry) {
++			rtw_warn_on(1);
++			goto exit;
++		}
++	}
++
++	rtw_odm_proc_init(dev);
++
++#ifdef CONFIG_MCC_MODE
++	rtw_mcc_proc_init(dev);
++#endif /* CONFIG_MCC_MODE */
++
++exit:
++	return dir_dev;
++}
++
++void rtw_adapter_proc_deinit(struct net_device *dev)
++{
++	struct proc_dir_entry *drv_proc = get_rtw_drv_proc();
++	struct proc_dir_entry *dir_dev = NULL;
++	_adapter *adapter = rtw_netdev_priv(dev);
++	int i;
++
++	dir_dev = adapter->dir_dev;
++
++	if (dir_dev == NULL) {
++		rtw_warn_on(1);
++		return;
++	}
++
++	for (i = 0; i < adapter_proc_hdls_num; i++)
++		remove_proc_entry(adapter_proc_hdls[i].name, dir_dev);
++
++	rtw_odm_proc_deinit(adapter);
++
++#ifdef CONFIG_MCC_MODE
++	rtw_mcc_proc_deinit(adapter);
++#endif /* CONFIG_MCC_MODE */
++
++	remove_proc_entry(dev->name, drv_proc);
++
++	adapter->dir_dev = NULL;
++}
++
++void rtw_adapter_proc_replace(struct net_device *dev)
++{
++	struct proc_dir_entry *drv_proc = get_rtw_drv_proc();
++	struct proc_dir_entry *dir_dev = NULL;
++	_adapter *adapter = rtw_netdev_priv(dev);
++	int i;
++
++	dir_dev = adapter->dir_dev;
++
++	if (dir_dev == NULL) {
++		rtw_warn_on(1);
++		return;
++	}
++
++	for (i = 0; i < adapter_proc_hdls_num; i++)
++		remove_proc_entry(adapter_proc_hdls[i].name, dir_dev);
++
++	rtw_odm_proc_deinit(adapter);
++
++#ifdef CONFIG_MCC_MODE
++	rtw_mcc_proc_deinit(adapter);
++#endif /* CONIG_MCC_MODE */
++
++	remove_proc_entry(adapter->old_ifname, drv_proc);
++
++	adapter->dir_dev = NULL;
++
++	rtw_adapter_proc_init(dev);
++
++}
++
++#endif /* CONFIG_PROC_DEBUG */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_proc.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_proc.h
+new file mode 100644
+index 000000000..b26f04486
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_proc.h
+@@ -0,0 +1,66 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_PROC_H__
++#define __RTW_PROC_H__
++
++#include <linux/proc_fs.h>
++#include <linux/seq_file.h>
++
++#define RTW_PROC_HDL_TYPE_SEQ	0
++#define RTW_PROC_HDL_TYPE_SSEQ	1
++#define RTW_PROC_HDL_TYPE_SZSEQ	2
++
++struct rtw_proc_hdl {
++	char *name;
++	u8 type;
++	union {
++		int (*show)(struct seq_file *, void *);
++		struct seq_operations *seq_op;
++		struct {
++			int (*show)(struct seq_file *, void *);
++			size_t size;
++		} sz;
++	} u;
++	ssize_t (*write)(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
++};
++
++#define RTW_PROC_HDL_SEQ(_name, _seq_op, _write) \
++	{ .name = _name, .type = RTW_PROC_HDL_TYPE_SEQ, .u.seq_op = _seq_op, .write = _write}
++
++#define RTW_PROC_HDL_SSEQ(_name, _show, _write) \
++	{ .name = _name, .type = RTW_PROC_HDL_TYPE_SSEQ, .u.show = _show, .write = _write}
++
++#define RTW_PROC_HDL_SZSEQ(_name, _show, _write, _size) \
++	{ .name = _name, .type = RTW_PROC_HDL_TYPE_SZSEQ, .u.sz.show = _show, .write = _write, .u.sz.size = _size}
++
++#ifdef CONFIG_PROC_DEBUG
++
++int rtw_drv_proc_init(void);
++void rtw_drv_proc_deinit(void);
++struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev);
++void rtw_adapter_proc_deinit(struct net_device *dev);
++void rtw_adapter_proc_replace(struct net_device *dev);
++
++#else /* !CONFIG_PROC_DEBUG */
++
++static inline int rtw_drv_proc_init(void) {return _FAIL;}
++#define rtw_drv_proc_deinit() do {} while (0)
++static inline struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev) {return NULL;}
++#define rtw_adapter_proc_deinit(dev) do {} while (0)
++#define rtw_adapter_proc_replace(dev) do {} while (0)
++
++#endif /* !CONFIG_PROC_DEBUG */
++
++#endif /* __RTW_PROC_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_rhashtable.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_rhashtable.c
+new file mode 100644
+index 000000000..df303b237
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_rhashtable.c
+@@ -0,0 +1,77 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <drv_types.h>
++
++#if defined(CONFIG_RTW_WDS) || defined(CONFIG_RTW_MESH) /* for now, only promised for kernel versions we support mesh */
++
++int rtw_rhashtable_walk_enter(rtw_rhashtable *ht, rtw_rhashtable_iter *iter)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0))
++	rhashtable_walk_enter((ht), (iter));
++	return 0;
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))
++	return rhashtable_walk_init((ht), (iter), GFP_ATOMIC);
++#else
++	/* kernel >= 4.4.0 rhashtable_walk_init use GFP_KERNEL to alloc, spin_lock for assignment */
++	iter->ht = ht;
++	iter->p = NULL;
++	iter->slot = 0;
++	iter->skip = 0;
++
++	iter->walker = kmalloc(sizeof(*iter->walker), GFP_ATOMIC);
++	if (!iter->walker)
++		return -ENOMEM;
++
++	spin_lock(&ht->lock);
++	iter->walker->tbl =
++		rcu_dereference_protected(ht->tbl, lockdep_is_held(&ht->lock));
++	list_add(&iter->walker->list, &iter->walker->tbl->walkers);
++	spin_unlock(&ht->lock);
++
++	return 0;
++#endif
++}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0))
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25))
++static inline int is_vmalloc_addr(const void *x)
++{
++#ifdef CONFIG_MMU
++	unsigned long addr = (unsigned long)x;
++
++	return addr >= VMALLOC_START && addr < VMALLOC_END;
++#else
++	return 0;
++#endif
++}
++#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25)) */
++
++void kvfree(const void *addr)
++{
++	if (is_vmalloc_addr(addr))
++		vfree(addr);
++	else
++		kfree(addr);
++}
++#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)) */
++
++#include "rhashtable.c"
++
++#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) */
++
++#endif /* defined(CONFIG_RTW_WDS) || defined(CONFIG_RTW_MESH) */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_rhashtable.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_rhashtable.h
+new file mode 100644
+index 000000000..af5ba7e4d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/rtw_rhashtable.h
+@@ -0,0 +1,67 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __RTW_RHASHTABLE_H__
++#define __RTW_RHASHTABLE_H__
++
++#if defined(CONFIG_RTW_WDS) || defined(CONFIG_RTW_MESH) /* for now, only promised for kernel versions we support mesh */
++
++/* directly reference rhashtable in kernel */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
++#include <linux/rhashtable.h>
++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) */
++
++/* Use rhashtable from kernel 4.4 */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))
++#define NULLS_MARKER(value) (1UL | (((long)value) << 1))
++#endif
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0))
++static inline void *kmalloc_array(size_t n, size_t size, gfp_t flags)
++{
++	if (size != 0 && n > ULONG_MAX / size)
++		return NULL;
++	return __kmalloc(n * size, flags);
++}
++#endif
++#include "rhashtable.h"
++#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) */
++
++typedef struct rhashtable rtw_rhashtable;
++typedef struct rhash_head rtw_rhash_head;
++typedef struct rhashtable_params rtw_rhashtable_params;
++
++#define rtw_rhashtable_init(ht, params) rhashtable_init(ht, params)
++
++typedef struct rhashtable_iter rtw_rhashtable_iter;
++
++int rtw_rhashtable_walk_enter(rtw_rhashtable *ht, rtw_rhashtable_iter *iter);
++#define rtw_rhashtable_walk_exit(iter) rhashtable_walk_exit(iter)
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 16, 0))
++#define rtw_rhashtable_walk_start(iter) rhashtable_walk_start_check(iter)
++#else
++#define rtw_rhashtable_walk_start(iter) rhashtable_walk_start(iter)
++#endif
++#define rtw_rhashtable_walk_next(iter) rhashtable_walk_next(iter)
++#define rtw_rhashtable_walk_stop(iter) rhashtable_walk_stop(iter)
++
++#define rtw_rhashtable_free_and_destroy(ht, free_fn, arg) rhashtable_free_and_destroy((ht), (free_fn), (arg))
++#define rtw_rhashtable_lookup_fast(ht, key, params) rhashtable_lookup_fast((ht), (key), (params))
++#define rtw_rhashtable_lookup_insert_fast(ht, obj, params) rhashtable_lookup_insert_fast((ht), (obj), (params))
++#define rtw_rhashtable_remove_fast(ht, obj, params) rhashtable_remove_fast((ht), (obj), (params))
++
++#endif /* defined(CONFIG_RTW_WDS) || defined(CONFIG_RTW_MESH) */
++
++#endif /* __RTW_RHASHTABLE_H__ */
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/sdio_intf.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/sdio_intf.c
+new file mode 100644
+index 000000000..85a0eae47
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/sdio_intf.c
+@@ -0,0 +1,1374 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _HCI_INTF_C_
++
++#include <drv_types.h>
++#include <hal_data.h>
++#include <platform_ops.h>
++
++#ifndef CONFIG_SDIO_HCI
++#error "CONFIG_SDIO_HCI shall be on!\n"
++#endif
++
++#ifdef CONFIG_RTL8822B
++#include <rtl8822b_hal.h>	/* rtl8822bs_set_hal_ops() */
++#endif /* CONFIG_RTL8822B */
++
++#ifdef CONFIG_RTL8822C
++#include <rtl8822c_hal.h>
++#endif /* CONFIG_RTL8822C */
++
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++#ifdef CONFIG_ACPI
++#include <linux/acpi.h>
++#include <linux/acpi_gpio.h>
++#include "rtw_android.h"
++#endif
++static int wlan_en_gpio = -1;
++#endif /* CONFIG_PLATFORM_INTEL_BYT */
++
++#ifndef dev_to_sdio_func
++#define dev_to_sdio_func(d)     container_of(d, struct sdio_func, dev)
++#endif
++
++static const struct sdio_device_id sdio_ids[] = {
++#ifdef CONFIG_RTL8723B
++	{ SDIO_DEVICE(0x024c, 0xB723), .driver_data = RTL8723B},
++#endif
++#ifdef CONFIG_RTL8188E
++	{ SDIO_DEVICE(0x024c, 0x8179), .driver_data = RTL8188E},
++#endif /* CONFIG_RTL8188E */
++
++#ifdef CONFIG_RTL8821A
++	{ SDIO_DEVICE(0x024c, 0x8821), .driver_data = RTL8821},
++#endif /* CONFIG_RTL8821A */
++
++#ifdef CONFIG_RTL8192E
++	{ SDIO_DEVICE(0x024c, 0x818B), .driver_data = RTL8192E},
++#endif /* CONFIG_RTL8192E */
++
++#ifdef CONFIG_RTL8703B
++	{ SDIO_DEVICE(0x024c, 0xB703), .driver_data = RTL8703B},
++#endif
++
++#ifdef CONFIG_RTL8188F
++	{SDIO_DEVICE(0x024c, 0xF179), .driver_data = RTL8188F},
++#endif
++
++#ifdef CONFIG_RTL8188GTV
++	{SDIO_DEVICE(0x024c, 0x018C), .driver_data = RTL8188GTV},
++#endif
++
++#ifdef CONFIG_RTL8822B
++	{SDIO_DEVICE(0x024c, 0xB822), .driver_data = RTL8822B},
++#endif
++
++#ifdef CONFIG_RTL8723D
++	{ SDIO_DEVICE(0x024c, 0xD723), .driver_data = RTL8723D},
++	{ SDIO_DEVICE(0x024c, 0xD724), .driver_data = RTL8723D},
++#endif
++
++#ifdef CONFIG_RTL8192F
++	{ SDIO_DEVICE(0x024c, 0x818C), .driver_data = RTL8192F},/*A CUT*/
++	{ SDIO_DEVICE(0x024c, 0xF192), .driver_data = RTL8192F},/*B CUT*/
++	{ SDIO_DEVICE(0x024c, 0xA725), .driver_data = RTL8192F},/*8725AS*/
++#endif /* CONFIG_RTL8192F */
++
++#ifdef CONFIG_RTL8821C
++	{SDIO_DEVICE(0x024C, 0xB821), .driver_data = RTL8821C},
++	{SDIO_DEVICE(0x024C, 0xC821), .driver_data = RTL8821C},
++#endif
++
++#ifdef CONFIG_RTL8822C
++	{SDIO_DEVICE(0x024c, 0xC822), .class = SDIO_CLASS_WLAN, .driver_data = RTL8822C},
++	{SDIO_DEVICE(0x024c, 0xD821), .class = SDIO_CLASS_WLAN, .driver_data = RTL8822C}, /* 8821DS */
++#endif
++
++#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC) /* temporarily add this to accept all sdio wlan id */
++	{ SDIO_DEVICE_CLASS(SDIO_CLASS_WLAN) },
++#endif
++	{ /* end: all zeroes */				},
++};
++
++MODULE_DEVICE_TABLE(sdio, sdio_ids);
++
++static int rtw_drv_init(struct sdio_func *func, const struct sdio_device_id *id);
++static void rtw_dev_remove(struct sdio_func *func);
++#ifdef CONFIG_SDIO_HOOK_DEV_SHUTDOWN
++static void rtw_dev_shutdown(struct device *dev);
++#endif
++static int rtw_sdio_resume(struct device *dev);
++static int rtw_sdio_suspend(struct device *dev);
++extern void rtw_dev_unload(PADAPTER padapter);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
++static const struct dev_pm_ops rtw_sdio_pm_ops = {
++	.suspend	= rtw_sdio_suspend,
++	.resume	= rtw_sdio_resume,
++};
++#endif
++
++struct sdio_drv_priv {
++	struct sdio_driver r871xs_drv;
++	int drv_registered;
++};
++
++static struct sdio_drv_priv sdio_drvpriv = {
++	.r871xs_drv.probe = rtw_drv_init,
++	.r871xs_drv.remove = rtw_dev_remove,
++	.r871xs_drv.name = (char *)DRV_NAME,
++	.r871xs_drv.id_table = sdio_ids,
++	.r871xs_drv.drv = {
++#ifdef CONFIG_SDIO_HOOK_DEV_SHUTDOWN
++		.shutdown = rtw_dev_shutdown,
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
++		.pm = &rtw_sdio_pm_ops,
++#endif
++	}
++};
++
++static struct rtw_if_operations sdio_ops = {
++	.read		= rtw_sdio_raw_read,
++	.write		= rtw_sdio_raw_write,
++};
++
++static void sd_sync_int_hdl(struct sdio_func *func)
++{
++	struct dvobj_priv *psdpriv;
++
++	psdpriv = sdio_get_drvdata(func);
++
++	if (!dvobj_get_primary_adapter(psdpriv)) {
++		RTW_INFO("%s primary adapter == NULL\n", __func__);
++		return;
++	}
++
++	rtw_sdio_set_irq_thd(psdpriv, current);
++	sd_int_hdl(dvobj_get_primary_adapter(psdpriv));
++	rtw_sdio_set_irq_thd(psdpriv, NULL);
++}
++
++int sdio_alloc_irq(struct dvobj_priv *dvobj)
++{
++	PSDIO_DATA psdio_data;
++	struct sdio_func *func;
++	int err;
++
++	psdio_data = &dvobj->intf_data;
++	func = psdio_data->func;
++
++	sdio_claim_host(func);
++
++	err = sdio_claim_irq(func, &sd_sync_int_hdl);
++	if (err) {
++		dvobj->drv_dbg.dbg_sdio_alloc_irq_error_cnt++;
++		RTW_PRINT("%s: sdio_claim_irq FAIL(%d)!\n", __func__, err);
++	} else {
++		dvobj->drv_dbg.dbg_sdio_alloc_irq_cnt++;
++		dvobj->irq_alloc = 1;
++	}
++
++	sdio_release_host(func);
++
++	return err ? _FAIL : _SUCCESS;
++}
++
++void sdio_free_irq(struct dvobj_priv *dvobj)
++{
++	PSDIO_DATA psdio_data;
++	struct sdio_func *func;
++	int err;
++
++	if (dvobj->irq_alloc) {
++		psdio_data = &dvobj->intf_data;
++		func = psdio_data->func;
++
++		if (func) {
++			sdio_claim_host(func);
++			err = sdio_release_irq(func);
++			if (err) {
++				dvobj->drv_dbg.dbg_sdio_free_irq_error_cnt++;
++				RTW_ERR("%s: sdio_release_irq FAIL(%d)!\n", __func__, err);
++			} else
++				dvobj->drv_dbg.dbg_sdio_free_irq_cnt++;
++			sdio_release_host(func);
++		}
++		dvobj->irq_alloc = 0;
++	}
++}
++
++#ifdef CONFIG_GPIO_WAKEUP
++extern unsigned int oob_irq;
++extern unsigned int oob_gpio;
++static irqreturn_t gpio_hostwakeup_irq_thread(int irq, void *data)
++{
++	PADAPTER padapter = (PADAPTER)data;
++	RTW_PRINT("gpio_hostwakeup_irq_thread\n");
++	/* Disable interrupt before calling handler */
++	/* disable_irq_nosync(oob_irq); */
++#ifdef CONFIG_PLATFORM_ARM_SUN6I
++	return 0;
++#else
++	return IRQ_HANDLED;
++#endif
++}
++
++static u8 gpio_hostwakeup_alloc_irq(PADAPTER padapter)
++{
++	int err;
++	u32 status = 0;
++
++	if (oob_irq == 0) {
++		RTW_INFO("oob_irq ZERO!\n");
++		return _FAIL;
++	}
++
++	RTW_INFO("%s : oob_irq = %d\n", __func__, oob_irq);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32))
++	status = IRQF_NO_SUSPEND;
++#endif
++
++	if (HIGH_ACTIVE_DEV2HST)
++		status |= IRQF_TRIGGER_RISING;
++	else
++		status |= IRQF_TRIGGER_FALLING;
++
++	err = request_threaded_irq(oob_irq, gpio_hostwakeup_irq_thread, NULL,
++		status, "rtw_wifi_gpio_wakeup", padapter);
++
++	if (err < 0) {
++		RTW_INFO("Oops: can't allocate gpio irq %d err:%d\n", oob_irq, err);
++		return _FALSE;
++	} else
++		RTW_INFO("allocate gpio irq %d ok\n", oob_irq);
++
++#ifndef CONFIG_PLATFORM_ARM_SUN8I
++	enable_irq_wake(oob_irq);
++#endif
++	return _SUCCESS;
++}
++
++static void gpio_hostwakeup_free_irq(PADAPTER padapter)
++{
++	wifi_free_gpio(oob_gpio);
++
++	if (oob_irq == 0)
++		return;
++
++#ifndef CONFIG_PLATFORM_ARM_SUN8I
++	disable_irq_wake(oob_irq);
++#endif
++	free_irq(oob_irq, padapter);
++}
++#endif
++
++void dump_sdio_card_info(void *sel, struct dvobj_priv *dvobj)
++{
++	PSDIO_DATA psdio_data = &dvobj->intf_data;
++	struct mmc_card *card = psdio_data->card;
++	int i;
++
++	RTW_PRINT_SEL(sel, "== SDIO Card Info ==\n");
++	RTW_PRINT_SEL(sel, "  card: %p\n", card);
++	RTW_PRINT_SEL(sel, "  clock: %d Hz\n", psdio_data->clock);
++
++	RTW_PRINT_SEL(sel, "  timing spec: ");
++	switch (psdio_data->timing) {
++	case MMC_TIMING_LEGACY:
++		_RTW_PRINT_SEL(sel, "legacy");
++		break;
++	case MMC_TIMING_MMC_HS:
++		_RTW_PRINT_SEL(sel, "mmc high-speed");
++		break;
++	case MMC_TIMING_SD_HS:
++		_RTW_PRINT_SEL(sel, "sd high-speed");
++		break;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)
++	#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
++	case MMC_TIMING_UHS_SDR12:
++		_RTW_PRINT_SEL(sel, "sd uhs SDR12");
++		break;
++	case MMC_TIMING_UHS_SDR25:
++		_RTW_PRINT_SEL(sel, "sd uhs SDR25");
++		break;
++	#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0) */
++
++	case MMC_TIMING_UHS_SDR50:
++		_RTW_PRINT_SEL(sel, "sd uhs SDR50");
++		break;
++
++	#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)
++	case MMC_TIMING_MMC_DDR52:
++		_RTW_PRINT_SEL(sel, "mmc DDR52");
++		break;
++	#endif
++
++	case MMC_TIMING_UHS_SDR104:
++		_RTW_PRINT_SEL(sel, "sd uhs SDR104");
++		break;
++	case MMC_TIMING_UHS_DDR50:
++		_RTW_PRINT_SEL(sel, "sd uhs DDR50");
++		break;
++
++	#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)
++	case MMC_TIMING_MMC_HS200:
++		_RTW_PRINT_SEL(sel, "mmc HS200");
++		break;
++	#endif
++
++	#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)
++	case MMC_TIMING_MMC_HS400:
++		_RTW_PRINT_SEL(sel, "mmc HS400");
++		break;
++	#endif
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
++	default:
++		_RTW_PRINT_SEL(sel, "unknown(%d)", psdio_data->timing);
++		break;
++	}
++	_RTW_PRINT_SEL(sel, "\n");
++
++	RTW_PRINT_SEL(sel, "  sd3_bus_mode: %s\n", (psdio_data->sd3_bus_mode) ? "TRUE" : "FALSE");
++
++	rtw_warn_on(card->sdio_funcs != sdio_get_num_of_func(dvobj));
++	RTW_PRINT_SEL(sel, "  func num: %u\n", card->sdio_funcs);
++	for (i = 0; card->sdio_func[i]; i++) {
++		RTW_PRINT_SEL(sel, "  func%u: %p%s\n"
++			, card->sdio_func[i]->num, card->sdio_func[i]
++			, psdio_data->func == card->sdio_func[i] ? " (*)" : "");
++	}
++
++	RTW_PRINT_SEL(sel, "================\n");
++}
++
++#define SDIO_CARD_INFO_DUMP(dvobj)	dump_sdio_card_info(RTW_DBGDUMP, dvobj)
++
++#ifdef DBG_SDIO
++#if (DBG_SDIO >= 2)
++void rtw_sdio_dbg_reg_free(struct dvobj_priv *d)
++{
++	struct sdio_data *sdio;
++	u8 *buf;
++	u32 size;
++
++
++	sdio = &d->intf_data;
++
++	buf = sdio->dbg_msg;
++	size = sdio->dbg_msg_size;
++	if (buf){
++		sdio->dbg_msg = NULL;
++		sdio->dbg_msg_size = 0;
++		rtw_mfree(buf, size);
++	}
++
++	buf = sdio->reg_mac;
++	if (buf) {
++		sdio->reg_mac = NULL;
++		rtw_mfree(buf, 0x800);
++	}
++
++	buf = sdio->reg_mac_ext;
++	if (buf) {
++		sdio->reg_mac_ext = NULL;
++		rtw_mfree(buf, 0x800);
++	}
++
++	buf = sdio->reg_local;
++	if (buf) {
++		sdio->reg_local = NULL;
++		rtw_mfree(buf, 0x100);
++	}
++
++	buf = sdio->reg_cia;
++	if (buf) {
++		sdio->reg_cia = NULL;
++		rtw_mfree(buf, 0x200);
++	}
++}
++
++void rtw_sdio_dbg_reg_alloc(struct dvobj_priv *d)
++{
++	struct sdio_data *sdio;
++	u8 *buf;
++
++
++	sdio = &d->intf_data;
++
++	buf = _rtw_zmalloc(0x800);
++	if (buf)
++		sdio->reg_mac = buf;
++
++	buf = _rtw_zmalloc(0x800);
++	if (buf)
++		sdio->reg_mac_ext = buf;
++
++	buf = _rtw_zmalloc(0x100);
++	if (buf)
++		sdio->reg_local = buf;
++
++	buf = _rtw_zmalloc(0x200);
++	if (buf)
++		sdio->reg_cia = buf;
++}
++#endif /* DBG_SDIO >= 2 */
++
++static void sdio_dbg_init(struct dvobj_priv *d)
++{
++	struct sdio_data *sdio;
++
++
++	sdio = &d->intf_data;
++
++	sdio->cmd52_err_cnt = 0;
++	sdio->cmd53_err_cnt = 0;
++
++#if (DBG_SDIO >= 1)
++	sdio->reg_dump_mark = 0;
++#endif /* DBG_SDIO >= 1 */
++
++#if (DBG_SDIO >= 3)
++	sdio->dbg_enable = 0;
++	sdio->err_stop = 0;
++	sdio->err_test = 0;
++	sdio->err_test_triggered = 0;
++#endif /* DBG_SDIO >= 3 */
++}
++
++static void sdio_dbg_deinit(struct dvobj_priv *d)
++{
++#if (DBG_SDIO >= 2)
++	rtw_sdio_dbg_reg_free(d);
++#endif /* DBG_SDIO >= 2 */
++}
++#endif /* DBG_SDIO */
++
++u32 sdio_init(struct dvobj_priv *dvobj)
++{
++	PSDIO_DATA psdio_data;
++	struct sdio_func *func;
++	int err;
++
++
++	psdio_data = &dvobj->intf_data;
++	func = psdio_data->func;
++
++	/* 3 1. init SDIO bus */
++	sdio_claim_host(func);
++
++	err = sdio_enable_func(func);
++	if (err) {
++		dvobj->drv_dbg.dbg_sdio_init_error_cnt++;
++		RTW_PRINT("%s: sdio_enable_func FAIL(%d)!\n", __func__, err);
++		goto release;
++	}
++
++	err = sdio_set_block_size(func, 512);
++	if (err) {
++		dvobj->drv_dbg.dbg_sdio_init_error_cnt++;
++		RTW_PRINT("%s: sdio_set_block_size FAIL(%d)!\n", __func__, err);
++		goto release;
++	}
++	psdio_data->block_transfer_len = 512;
++	psdio_data->tx_block_mode = 1;
++	psdio_data->rx_block_mode = 1;
++
++	psdio_data->card = func->card;
++	psdio_data->timing = func->card->host->ios.timing;
++	psdio_data->clock = func->card->host->ios.clock;
++	psdio_data->func_number = func->card->sdio_funcs;
++
++	psdio_data->sd3_bus_mode = _FALSE;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)
++	if (psdio_data->timing <= MMC_TIMING_UHS_DDR50
++		#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
++		&& psdio_data->timing >= MMC_TIMING_UHS_SDR12
++		#else
++		&& psdio_data->timing >= MMC_TIMING_UHS_SDR50
++		#endif
++	)
++		psdio_data->sd3_bus_mode = _TRUE;
++#endif
++
++#ifdef DBG_SDIO
++	sdio_dbg_init(dvobj);
++#endif /* DBG_SDIO */
++
++	SDIO_CARD_INFO_DUMP(dvobj);
++
++
++release:
++	sdio_release_host(func);
++
++	if (err)
++		return _FAIL;
++	return _SUCCESS;
++}
++
++void sdio_deinit(struct dvobj_priv *dvobj)
++{
++	struct sdio_func *func;
++	int err;
++
++
++
++	func = dvobj->intf_data.func;
++
++	if (func) {
++		sdio_claim_host(func);
++		err = sdio_disable_func(func);
++		if (err) {
++			dvobj->drv_dbg.dbg_sdio_deinit_error_cnt++;
++			RTW_ERR("%s: sdio_disable_func(%d)\n", __func__, err);
++		}
++
++		sdio_release_host(func);
++	}
++
++#ifdef DBG_SDIO
++	sdio_dbg_deinit(dvobj);
++#endif /* DBG_SDIO */
++}
++
++u8 sdio_get_num_of_func(struct dvobj_priv *dvobj)
++{
++	return dvobj->intf_data.func_number;
++}
++
++static void rtw_decide_chip_type_by_device_id(struct dvobj_priv *dvobj, const struct sdio_device_id  *pdid)
++{
++	dvobj->chip_type = pdid->driver_data;
++
++#if defined(CONFIG_RTL8188E)
++	if (dvobj->chip_type == RTL8188E) {
++		dvobj->HardwareType = HARDWARE_TYPE_RTL8188ES;
++		RTW_INFO("CHIP TYPE: RTL8188E\n");
++	}
++#endif
++
++#if defined(CONFIG_RTL8723B)
++	if (dvobj->chip_type == RTL8723B) {
++		dvobj->HardwareType = HARDWARE_TYPE_RTL8723BS;
++		RTW_INFO("CHIP TYPE: RTL8723B\n");
++	}
++#endif
++
++#if defined(CONFIG_RTL8821A)
++	if (dvobj->chip_type == RTL8821) {
++		dvobj->HardwareType = HARDWARE_TYPE_RTL8821S;
++		RTW_INFO("CHIP TYPE: RTL8821A\n");
++	}
++#endif
++
++#if defined(CONFIG_RTL8192E)
++	if (dvobj->chip_type == RTL8192E) {
++		dvobj->HardwareType = HARDWARE_TYPE_RTL8192ES;
++		RTW_INFO("CHIP TYPE: RTL8192E\n");
++	}
++#endif
++
++#if defined(CONFIG_RTL8703B)
++	if (dvobj->chip_type == RTL8703B) {
++		dvobj->HardwareType = HARDWARE_TYPE_RTL8703BS;
++		RTW_INFO("CHIP TYPE: RTL8703B\n");
++	}
++#endif
++
++#if defined(CONFIG_RTL8723D)
++	if (dvobj->chip_type == RTL8723D) {
++		dvobj->HardwareType = HARDWARE_TYPE_RTL8723DS;
++		RTW_INFO("CHIP TYPE: RTL8723D\n");
++	}
++#endif
++
++#if defined(CONFIG_RTL8188F)
++	if (dvobj->chip_type == RTL8188F) {
++		dvobj->HardwareType = HARDWARE_TYPE_RTL8188FS;
++		RTW_INFO("CHIP TYPE: RTL8188F\n");
++	}
++#endif
++
++#if defined(CONFIG_RTL8188GTV)
++	if (dvobj->chip_type == RTL8188GTV) {
++		dvobj->HardwareType = HARDWARE_TYPE_RTL8188GTVS;
++		RTW_INFO("CHIP TYPE: RTL8188GTV\n");
++	}
++#endif
++
++#if defined(CONFIG_RTL8822B)
++	if (dvobj->chip_type == RTL8822B) {
++		dvobj->HardwareType = HARDWARE_TYPE_RTL8822BS;
++		RTW_INFO("CHIP TYPE: RTL8822B\n");
++	}
++#endif
++
++#if defined(CONFIG_RTL8821C)
++	if (dvobj->chip_type == RTL8821C) {
++		dvobj->HardwareType = HARDWARE_TYPE_RTL8821CS;
++		RTW_INFO("CHIP TYPE: RTL8821C\n");
++	}
++#endif
++
++#if defined(CONFIG_RTL8192F)
++	if (dvobj->chip_type == RTL8192F) {
++		dvobj->HardwareType = HARDWARE_TYPE_RTL8192FS;
++		RTW_INFO("CHIP TYPE: RTL8192F\n");
++	}
++#endif
++
++#if defined(CONFIG_RTL8822C)
++	if (dvobj->chip_type == RTL8822C) {
++		dvobj->HardwareType = HARDWARE_TYPE_RTL8822CS;
++		RTW_INFO("CHIP TYPE: RTL8822C\n");
++	}
++#endif
++
++}
++
++static struct dvobj_priv *sdio_dvobj_init(struct sdio_func *func, const struct sdio_device_id  *pdid)
++{
++	int status = _FAIL;
++	struct dvobj_priv *dvobj = NULL;
++	PSDIO_DATA psdio;
++
++	dvobj = devobj_init();
++	if (dvobj == NULL)
++		goto exit;
++	dvobj->intf_ops = &sdio_ops;
++
++	sdio_set_drvdata(func, dvobj);
++
++	psdio = &dvobj->intf_data;
++	psdio->func = func;
++
++	if (sdio_init(dvobj) != _SUCCESS) {
++		goto free_dvobj;
++	}
++
++	dvobj->interface_type = RTW_SDIO;
++	rtw_decide_chip_type_by_device_id(dvobj, pdid);
++
++	rtw_reset_continual_io_error(dvobj);
++	status = _SUCCESS;
++
++free_dvobj:
++	if (status != _SUCCESS && dvobj) {
++		sdio_set_drvdata(func, NULL);
++
++		devobj_deinit(dvobj);
++
++		dvobj = NULL;
++	}
++exit:
++	return dvobj;
++}
++
++static void sdio_dvobj_deinit(struct sdio_func *func)
++{
++	struct dvobj_priv *dvobj = sdio_get_drvdata(func);
++
++	sdio_set_drvdata(func, NULL);
++	if (dvobj) {
++		sdio_deinit(dvobj);
++		sdio_free_irq(dvobj);
++		devobj_deinit(dvobj);
++	}
++
++	return;
++}
++
++u8 rtw_set_hal_ops(PADAPTER padapter)
++{
++	/* alloc memory for HAL DATA */
++	if (rtw_hal_data_init(padapter) == _FAIL)
++		return _FAIL;
++
++#if defined(CONFIG_RTL8188E)
++	if (rtw_get_chip_type(padapter) == RTL8188E)
++		rtl8188es_set_hal_ops(padapter);
++#endif
++
++#if defined(CONFIG_RTL8723B)
++	if (rtw_get_chip_type(padapter) == RTL8723B)
++		rtl8723bs_set_hal_ops(padapter);
++#endif
++
++#if defined(CONFIG_RTL8821A)
++	if (rtw_get_chip_type(padapter) == RTL8821)
++		rtl8821as_set_hal_ops(padapter);
++#endif
++
++#if defined(CONFIG_RTL8192E)
++	if (rtw_get_chip_type(padapter) == RTL8192E)
++		rtl8192es_set_hal_ops(padapter);
++#endif
++
++#if defined(CONFIG_RTL8703B)
++	if (rtw_get_chip_type(padapter) == RTL8703B)
++		rtl8703bs_set_hal_ops(padapter);
++#endif
++
++#if defined(CONFIG_RTL8723D)
++	if (rtw_get_chip_type(padapter) == RTL8723D)
++		rtl8723ds_set_hal_ops(padapter);
++#endif
++
++#if defined(CONFIG_RTL8188F)
++	if (rtw_get_chip_type(padapter) == RTL8188F)
++		rtl8188fs_set_hal_ops(padapter);
++#endif
++
++#if defined(CONFIG_RTL8188GTV)
++	if (rtw_get_chip_type(padapter) == RTL8188GTV)
++		rtl8188gtvs_set_hal_ops(padapter);
++#endif
++
++#if defined(CONFIG_RTL8822B)
++	if (rtw_get_chip_type(padapter) == RTL8822B)
++		rtl8822bs_set_hal_ops(padapter);
++#endif
++
++#if defined(CONFIG_RTL8821C)
++	if (rtw_get_chip_type(padapter) == RTL8821C) {
++		if (rtl8821cs_set_hal_ops(padapter) == _FAIL)
++			return _FAIL;
++	}
++#endif
++
++#if defined(CONFIG_RTL8192F)
++	if (rtw_get_chip_type(padapter) == RTL8192F)
++		rtl8192fs_set_hal_ops(padapter);
++#endif
++
++#if defined(CONFIG_RTL8822C)
++	if (rtw_get_chip_type(padapter) == RTL8822C)
++		rtl8822cs_set_hal_ops(padapter);
++#endif
++
++	if (rtw_hal_ops_check(padapter) == _FAIL)
++		return _FAIL;
++
++	if (hal_spec_init(padapter) == _FAIL)
++		return _FAIL;
++
++	return _SUCCESS;
++}
++
++static void sd_intf_start(PADAPTER padapter)
++{
++	if (padapter == NULL) {
++		RTW_ERR("%s: padapter is NULL!\n", __func__);
++		return;
++	}
++
++	/* hal dep */
++	rtw_hal_enable_interrupt(padapter);
++}
++
++static void sd_intf_stop(PADAPTER padapter)
++{
++	if (padapter == NULL) {
++		RTW_ERR("%s: padapter is NULL!\n", __func__);
++		return;
++	}
++
++	/* hal dep */
++	rtw_hal_disable_interrupt(padapter);
++}
++
++
++#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN
++PADAPTER g_test_adapter = NULL;
++#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */
++
++_adapter *rtw_sdio_primary_adapter_init(struct dvobj_priv *dvobj)
++{
++	int status = _FAIL;
++	PADAPTER padapter = NULL;
++
++	padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter));
++	if (padapter == NULL)
++		goto exit;
++
++	if (loadparam(padapter) != _SUCCESS)
++		goto free_adapter;
++
++#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN
++	g_test_adapter = padapter;
++#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */
++	padapter->dvobj = dvobj;
++
++	rtw_set_drv_stopped(padapter);/*init*/
++
++	dvobj->padapters[dvobj->iface_nums++] = padapter;
++	padapter->iface_id = IFACE_ID0;
++
++	/* set adapter_type/iface type for primary padapter */
++	padapter->isprimary = _TRUE;
++	padapter->adapter_type = PRIMARY_ADAPTER;
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++	padapter->hw_port = HW_PORT0;
++#else
++	padapter->hw_port = HW_PORT0;
++#endif
++
++	/* 3 3. init driver special setting, interface, OS and hardware relative */
++
++	/* 4 3.1 set hardware operation functions */
++	if (rtw_set_hal_ops(padapter) == _FAIL)
++		goto free_hal_data;
++
++	/* 3 5. initialize Chip version */
++	padapter->intf_start = &sd_intf_start;
++	padapter->intf_stop = &sd_intf_stop;
++
++	if (rtw_init_io_priv(padapter, sdio_set_intf_ops) == _FAIL) {
++		goto free_hal_data;
++	}
++
++	rtw_hal_read_chip_version(padapter);
++
++	rtw_hal_chip_configure(padapter);
++
++#ifdef CONFIG_BT_COEXIST
++	rtw_btcoex_Initialize(padapter);
++#endif
++	rtw_btcoex_wifionly_initialize(padapter);
++
++	/* 3 6. read efuse/eeprom data */
++	if (rtw_hal_read_chip_info(padapter) == _FAIL)
++		goto free_hal_data;
++
++	/* 3 7. init driver common data */
++	if (rtw_init_drv_sw(padapter) == _FAIL) {
++		goto free_hal_data;
++	}
++
++	/* 3 8. get WLan MAC address */
++	/* set mac addr */
++	rtw_macaddr_cfg(adapter_mac_addr(padapter),  get_hal_mac_addr(padapter));
++
++#ifdef CONFIG_MI_WITH_MBSSID_CAM
++	rtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter));
++#endif
++#ifdef CONFIG_P2P
++	rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));
++#endif /* CONFIG_P2P */
++
++	rtw_hal_disable_interrupt(padapter);
++
++	RTW_INFO("bDriverStopped:%s, bSurpriseRemoved:%s, bup:%d, hw_init_completed:%d\n"
++		, rtw_is_drv_stopped(padapter) ? "True" : "False"
++		, rtw_is_surprise_removed(padapter) ? "True" : "False"
++		, padapter->bup
++		, rtw_get_hw_init_completed(padapter)
++	);
++
++	status = _SUCCESS;
++
++free_hal_data:
++	if (status != _SUCCESS && padapter->HalData)
++		rtw_hal_free_data(padapter);
++
++free_adapter:
++	if (status != _SUCCESS && padapter) {
++		#ifdef RTW_HALMAC
++		rtw_halmac_deinit_adapter(dvobj);
++		#endif
++		rtw_vmfree((u8 *)padapter, sizeof(*padapter));
++		padapter = NULL;
++	}
++exit:
++	return padapter;
++}
++
++static void rtw_sdio_primary_adapter_deinit(_adapter *padapter)
++{
++	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++
++	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
++		rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY);
++
++#ifdef CONFIG_AP_MODE
++	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
++		free_mlme_ap_info(padapter);
++		#ifdef CONFIG_HOSTAPD_MLME
++		hostapd_mode_unload(padapter);
++		#endif
++	}
++#endif
++
++#ifdef CONFIG_GPIO_WAKEUP
++#ifdef CONFIG_PLATFORM_ARM_SUN6I
++	sw_gpio_eint_set_enable(gpio_eint_wlan, 0);
++	sw_gpio_irq_free(eint_wlan_handle);
++#else
++	gpio_hostwakeup_free_irq(padapter);
++#endif
++#endif
++
++	/*rtw_cancel_all_timer(if1);*/
++
++#ifdef CONFIG_WOWLAN
++	adapter_to_pwrctl(padapter)->wowlan_mode = _FALSE;
++	RTW_PRINT("%s wowlan_mode:%d\n", __func__, adapter_to_pwrctl(padapter)->wowlan_mode);
++#endif /* CONFIG_WOWLAN */
++
++	rtw_dev_unload(padapter);
++	RTW_INFO("+r871xu_dev_remove, hw_init_completed=%d\n", rtw_get_hw_init_completed(padapter));
++
++	rtw_free_drv_sw(padapter);
++
++	/* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */
++	rtw_os_ndev_free(padapter);
++
++#ifdef RTW_HALMAC
++	rtw_halmac_deinit_adapter(adapter_to_dvobj(padapter));
++#endif /* RTW_HALMAC */
++
++	rtw_vmfree((u8 *)padapter, sizeof(_adapter));
++
++#ifdef CONFIG_PLATFORM_RTD2880B
++	RTW_INFO("wlan link down\n");
++	rtd2885_wlan_netlink_sendMsg("linkdown", "8712");
++#endif
++
++#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN
++	g_test_adapter = NULL;
++#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */
++}
++
++/*
++ * drv_init() - a device potentially for us
++ *
++ * notes: drv_init() is called when the bus driver has located a card for us to support.
++ *        We accept the new device by returning 0.
++ */
++static int rtw_drv_init(
++	struct sdio_func *func,
++	const struct sdio_device_id *id)
++{
++	int status = _FAIL;
++#ifdef CONFIG_CONCURRENT_MODE
++	int i;
++#endif
++	PADAPTER padapter = NULL;
++	struct dvobj_priv *dvobj;
++
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++
++#ifdef CONFIG_ACPI
++	acpi_handle handle;
++	struct acpi_device *adev;
++#endif
++
++#if defined(CONFIG_ACPI) && defined(CONFIG_GPIO_WAKEUP)
++	handle = ACPI_HANDLE(&func->dev);
++
++	if (handle) {
++		/* Dont try to do acpi pm for the wifi module */
++		if (!handle || acpi_bus_get_device(handle, &adev))
++			RTW_INFO("Could not get acpi pointer!\n");
++		else {
++			adev->flags.power_manageable = 0;
++			RTW_INFO("Disabling ACPI power management support!\n");
++		}
++		oob_gpio = acpi_get_gpio_by_index(&func->dev, 0, NULL);
++		RTW_INFO("rtw_drv_init: ACPI_HANDLE found oob_gpio %d!\n", oob_gpio);
++		wifi_configure_gpio();
++	} else
++		RTW_INFO("rtw_drv_init: ACPI_HANDLE NOT found!\n");
++#endif
++
++#if defined(CONFIG_ACPI)
++	if (&func->dev && ACPI_HANDLE(&func->dev)) {
++		wlan_en_gpio = acpi_get_gpio_by_index(&func->dev, 1, NULL);
++		RTW_INFO("rtw_drv_init: ACPI_HANDLE found wlan_en %d!\n", wlan_en_gpio);
++	} else
++		RTW_INFO("rtw_drv_init: ACPI_HANDLE NOT found!\n");
++#endif
++#endif /* CONFIG_PLATFORM_INTEL_BYT */
++
++
++
++	dvobj = sdio_dvobj_init(func, id);
++	if (dvobj == NULL) {
++		goto exit;
++	}
++
++	padapter = rtw_sdio_primary_adapter_init(dvobj);
++	if (padapter == NULL) {
++		RTW_INFO("rtw_init_primary_adapter Failed!\n");
++		goto free_dvobj;
++	}
++
++#ifdef CONFIG_CONCURRENT_MODE
++	if (padapter->registrypriv.virtual_iface_num > (CONFIG_IFACE_NUMBER - 1))
++		padapter->registrypriv.virtual_iface_num = (CONFIG_IFACE_NUMBER - 1);
++
++	for (i = 0; i < padapter->registrypriv.virtual_iface_num; i++) {
++		if (rtw_drv_add_vir_if(padapter, sdio_set_intf_ops) == NULL) {
++			RTW_INFO("rtw_drv_add_iface failed! (%d)\n", i);
++			goto free_if_vir;
++		}
++	}
++#endif
++
++	/* dev_alloc_name && register_netdev */
++	if (rtw_os_ndevs_init(dvobj) != _SUCCESS)
++		goto free_if_vir;
++
++#ifdef CONFIG_HOSTAPD_MLME
++	hostapd_mode_init(padapter);
++#endif
++
++#ifdef CONFIG_PLATFORM_RTD2880B
++	RTW_INFO("wlan link up\n");
++	rtd2885_wlan_netlink_sendMsg("linkup", "8712");
++#endif
++
++	if (sdio_alloc_irq(dvobj) != _SUCCESS)
++		goto os_ndevs_deinit;
++
++#ifdef CONFIG_GPIO_WAKEUP
++#ifdef CONFIG_PLATFORM_ARM_SUN6I
++	eint_wlan_handle = sw_gpio_irq_request(gpio_eint_wlan, TRIG_EDGE_NEGATIVE, (peint_handle)gpio_hostwakeup_irq_thread, NULL);
++	if (!eint_wlan_handle) {
++		RTW_INFO("%s: request irq failed\n", __func__);
++		return -1;
++	}
++#else
++	gpio_hostwakeup_alloc_irq(padapter);
++#endif
++#endif
++
++#ifdef CONFIG_GLOBAL_UI_PID
++	if (ui_pid[1] != 0) {
++		RTW_INFO("ui_pid[1]:%d\n", ui_pid[1]);
++		rtw_signal_process(ui_pid[1], SIGUSR2);
++	}
++#endif
++
++
++	status = _SUCCESS;
++
++os_ndevs_deinit:
++	if (status != _SUCCESS)
++		rtw_os_ndevs_deinit(dvobj);
++free_if_vir:
++	if (status != _SUCCESS) {
++		#ifdef CONFIG_CONCURRENT_MODE
++		rtw_drv_stop_vir_ifaces(dvobj);
++		rtw_drv_free_vir_ifaces(dvobj);
++		#endif
++	}
++
++	if (status != _SUCCESS && padapter)
++		rtw_sdio_primary_adapter_deinit(padapter);
++
++free_dvobj:
++	if (status != _SUCCESS)
++		sdio_dvobj_deinit(func);
++exit:
++	return status == _SUCCESS ? 0 : -ENODEV;
++}
++
++static void rtw_dev_remove(struct sdio_func *func)
++{
++	struct dvobj_priv *dvobj = sdio_get_drvdata(func);
++	struct pwrctrl_priv *pwrctl = dvobj_to_pwrctl(dvobj);
++	PADAPTER padapter = dvobj_get_primary_adapter(dvobj);
++
++
++
++	dvobj->processing_dev_remove = _TRUE;
++
++	/* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */
++	rtw_os_ndevs_unregister(dvobj);
++
++	if (!rtw_is_surprise_removed(padapter)) {
++		int err;
++
++		/* test surprise remove */
++		sdio_claim_host(func);
++		sdio_readb(func, 0, &err);
++		sdio_release_host(func);
++		if (err == -ENOMEDIUM) {
++			rtw_set_surprise_removed(padapter);
++			RTW_INFO("%s: device had been removed!\n", __func__);
++		}
++	}
++
++#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
++	rtw_unregister_early_suspend(pwrctl);
++#endif
++
++	if (GET_HAL_DATA(padapter)->bFWReady == _TRUE) {
++		rtw_ps_deny(padapter, PS_DENY_DRV_REMOVE);
++		rtw_pm_set_ips(padapter, IPS_NONE);
++		rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
++		LeaveAllPowerSaveMode(padapter);
++	}
++	rtw_set_drv_stopped(padapter);	/*for stop thread*/
++	rtw_stop_cmd_thread(padapter);
++#ifdef CONFIG_CONCURRENT_MODE
++	rtw_drv_stop_vir_ifaces(dvobj);
++#endif
++
++#ifdef CONFIG_BT_COEXIST
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++	if (GET_HAL_DATA(padapter)->EEPROMBluetoothCoexist)
++		rtw_btcoex_close_socket(padapter);
++#endif
++	rtw_btcoex_HaltNotify(padapter);
++#endif
++
++	rtw_sdio_primary_adapter_deinit(padapter);
++
++#ifdef CONFIG_CONCURRENT_MODE
++	rtw_drv_free_vir_ifaces(dvobj);
++#endif
++
++	sdio_dvobj_deinit(func);
++
++
++}
++
++#ifdef CONFIG_SDIO_HOOK_DEV_SHUTDOWN
++static void rtw_dev_shutdown(struct device *dev)
++{
++	struct sdio_func *func = dev_to_sdio_func(dev);
++
++	if (func == NULL)
++		return;
++
++	RTW_INFO("==> %s !\n", __func__);
++
++	rtw_dev_remove(func);
++
++	RTW_INFO("<== %s !\n", __func__);
++}
++#endif
++
++extern int pm_netdev_open(struct net_device *pnetdev, u8 bnormal);
++extern int pm_netdev_close(struct net_device *pnetdev, u8 bnormal);
++
++static int rtw_sdio_suspend(struct device *dev)
++{
++	struct sdio_func *func = dev_to_sdio_func(dev);
++	struct dvobj_priv *psdpriv;
++	struct pwrctrl_priv *pwrpriv = NULL;
++	_adapter *padapter = NULL;
++	struct debug_priv *pdbgpriv = NULL;
++	int ret = 0;
++#ifdef CONFIG_RTW_SDIO_PM_KEEP_POWER
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34))
++	mmc_pm_flag_t pm_flag = 0;
++#endif
++#endif
++
++	if (dev == NULL)
++		goto exit;
++
++	psdpriv = sdio_get_drvdata(func);
++	if (psdpriv == NULL)
++		goto exit;
++
++	pwrpriv = dvobj_to_pwrctl(psdpriv);
++	padapter = dvobj_get_primary_adapter(psdpriv);
++	pdbgpriv = &psdpriv->drv_dbg;
++	if (rtw_is_drv_stopped(padapter)) {
++		RTW_INFO("%s bDriverStopped == _TRUE\n", __func__);
++		goto exit;
++	}
++
++	if (pwrpriv->bInSuspend == _TRUE) {
++		RTW_INFO("%s bInSuspend = %d\n", __func__, pwrpriv->bInSuspend);
++		pdbgpriv->dbg_suspend_error_cnt++;
++		goto exit;
++	}
++
++	ret = rtw_suspend_common(padapter);
++
++#ifdef CONFIG_RTW_SDIO_PM_KEEP_POWER
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34))
++	/* Android 4.0 don't support WIFI close power */
++	/* or power down or clock will close after wifi resume, */
++	/* this is sprd's bug in Android 4.0, but sprd don't */
++	/* want to fix it. */
++	/* we have test power under 8723as, power consumption is ok */
++	pm_flag = sdio_get_host_pm_caps(func);
++	RTW_INFO("cmd: %s: suspend: PM flag = 0x%x\n", sdio_func_id(func), pm_flag);
++	if (!(pm_flag & MMC_PM_KEEP_POWER)) {
++		RTW_INFO("%s: cannot remain alive while host is suspended\n", sdio_func_id(func));
++		if (pdbgpriv)
++			pdbgpriv->dbg_suspend_error_cnt++;
++		return -ENOSYS;
++	} else {
++		RTW_INFO("cmd: suspend with MMC_PM_KEEP_POWER\n");
++		sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
++	}
++#endif
++#endif
++exit:
++	return ret;
++}
++int rtw_resume_process(_adapter *padapter)
++{
++	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
++	struct dvobj_priv *psdpriv = padapter->dvobj;
++	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
++
++	if (pwrpriv->bInSuspend == _FALSE) {
++		pdbgpriv->dbg_resume_error_cnt++;
++		RTW_INFO("%s bInSuspend = %d\n", __FUNCTION__, pwrpriv->bInSuspend);
++		return -1;
++	}
++
++	return rtw_resume_common(padapter);
++}
++
++static int rtw_sdio_resume(struct device *dev)
++{
++	struct sdio_func *func = dev_to_sdio_func(dev);
++	struct dvobj_priv *psdpriv = sdio_get_drvdata(func);
++	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(psdpriv);
++	_adapter *padapter = dvobj_get_primary_adapter(psdpriv);
++	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
++	int ret = 0;
++	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
++
++	RTW_INFO("==> %s (%s:%d)\n", __FUNCTION__, current->comm, current->pid);
++
++	pdbgpriv->dbg_resume_cnt++;
++
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++	if (0)
++#else
++	if (pwrpriv->wowlan_mode || pwrpriv->wowlan_ap_mode)
++#endif
++	{
++		rtw_resume_lock_suspend();
++		ret = rtw_resume_process(padapter);
++		rtw_resume_unlock_suspend();
++	} else {
++#ifdef CONFIG_RESUME_IN_WORKQUEUE
++		rtw_resume_in_workqueue(pwrpriv);
++#else
++		if (rtw_is_earlysuspend_registered(pwrpriv)) {
++			/* jeff: bypass resume here, do in late_resume */
++			rtw_set_do_late_resume(pwrpriv, _TRUE);
++		} else {
++			rtw_resume_lock_suspend();
++			ret = rtw_resume_process(padapter);
++			rtw_resume_unlock_suspend();
++		}
++#endif
++	}
++	pmlmeext->last_scan_time = rtw_get_current_time();
++	RTW_INFO("<========  %s return %d\n", __FUNCTION__, ret);
++	return ret;
++
++}
++
++static int __init rtw_drv_entry(void)
++{
++	int ret = 0;
++
++	RTW_PRINT("module init start\n");
++	dump_drv_version(RTW_DBGDUMP);
++#ifdef BTCOEXVERSION
++	RTW_PRINT(DRV_NAME" BT-Coex version = %s\n", BTCOEXVERSION);
++#endif /* BTCOEXVERSION */
++
++#ifndef CONFIG_PLATFORM_INTEL_BYT
++	rtw_android_wifictrl_func_add();
++#endif /* !CONFIG_PLATFORM_INTEL_BYT */
++
++	ret = platform_wifi_power_on();
++	if (ret) {
++		RTW_INFO("%s: power on failed!!(%d)\n", __FUNCTION__, ret);
++		ret = -1;
++		goto exit;
++	}
++
++	sdio_drvpriv.drv_registered = _TRUE;
++	rtw_suspend_lock_init();
++	rtw_drv_proc_init();
++	rtw_ndev_notifier_register();
++	rtw_inetaddr_notifier_register();
++
++	ret = sdio_register_driver(&sdio_drvpriv.r871xs_drv);
++	if (ret != 0) {
++		sdio_drvpriv.drv_registered = _FALSE;
++		rtw_suspend_lock_uninit();
++		rtw_drv_proc_deinit();
++		rtw_ndev_notifier_unregister();
++		rtw_inetaddr_notifier_unregister();
++		RTW_INFO("%s: register driver failed!!(%d)\n", __FUNCTION__, ret);
++		goto poweroff;
++	}
++
++	goto exit;
++
++poweroff:
++	platform_wifi_power_off();
++
++exit:
++	RTW_PRINT("module init ret=%d\n", ret);
++	return ret;
++}
++
++static void __exit rtw_drv_halt(void)
++{
++	RTW_PRINT("module exit start\n");
++
++	sdio_drvpriv.drv_registered = _FALSE;
++
++	sdio_unregister_driver(&sdio_drvpriv.r871xs_drv);
++
++	rtw_android_wifictrl_func_del();
++
++	platform_wifi_power_off();
++
++	rtw_suspend_lock_uninit();
++	rtw_drv_proc_deinit();
++	rtw_ndev_notifier_unregister();
++	rtw_inetaddr_notifier_unregister();
++
++	RTW_PRINT("module exit success\n");
++
++	rtw_mstat_dump(RTW_DBGDUMP);
++}
++
++#ifdef CONFIG_PLATFORM_INTEL_BYT
++int rtw_sdio_set_power(int on)
++{
++
++	if (wlan_en_gpio >= 0) {
++		if (on)
++			gpio_set_value(wlan_en_gpio, 1);
++		else
++			gpio_set_value(wlan_en_gpio, 0);
++	}
++
++	return 0;
++}
++#endif /* CONFIG_PLATFORM_INTEL_BYT */
++
++late_initcall(rtw_drv_entry);
++module_exit(rtw_drv_halt);
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/sdio_ops_linux.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/sdio_ops_linux.c
+new file mode 100644
+index 000000000..af6a9636e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/sdio_ops_linux.c
+@@ -0,0 +1,1347 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2019 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _SDIO_OPS_LINUX_C_
++
++#include <drv_types.h>
++
++inline bool rtw_is_sdio30(_adapter *adapter)
++{
++	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
++	PSDIO_DATA psdio_data = &dvobj->intf_data;
++
++	return (psdio_data->sd3_bus_mode) ? _TRUE : _FALSE;
++}
++
++static bool rtw_sdio_claim_host_needed(struct sdio_func *func)
++{
++	struct dvobj_priv *dvobj = sdio_get_drvdata(func);
++	PSDIO_DATA sdio_data = &dvobj->intf_data;
++
++	if (sdio_data->sys_sdio_irq_thd && sdio_data->sys_sdio_irq_thd == current)
++		return _FALSE;
++	return _TRUE;
++}
++
++inline void rtw_sdio_set_irq_thd(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl)
++{
++	PSDIO_DATA sdio_data = &dvobj->intf_data;
++
++	sdio_data->sys_sdio_irq_thd = thd_hdl;
++}
++#ifndef RTW_HALMAC
++u8 sd_f0_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	u8 v = 0;
++	struct sdio_func *func;
++	bool claim_needed;
++
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return v;
++	}
++
++	func = psdio->func;
++	claim_needed = rtw_sdio_claim_host_needed(func);
++
++	if (claim_needed)
++		sdio_claim_host(func);
++	v = sdio_f0_readb(func, addr, err);
++	if (claim_needed)
++		sdio_release_host(func);
++	if (err && *err)
++		RTW_ERR("%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr);
++
++
++	return v;
++}
++
++void sd_f0_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	struct sdio_func *func;
++	bool claim_needed;
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return;
++	}
++
++	func = psdio->func;
++	claim_needed = rtw_sdio_claim_host_needed(func);
++
++	if (claim_needed)
++		sdio_claim_host(func);
++	sdio_f0_writeb(func, v, addr, err);
++	if (claim_needed)
++		sdio_release_host(func);
++	if (err && *err)
++		RTW_ERR("%s: FAIL!(%d) addr=0x%05x val=0x%02x\n", __func__, *err, addr, v);
++
++}
++
++/*
++ * Return:
++ *	0		Success
++ *	others	Fail
++ */
++s32 _sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	int err = 0, i;
++	struct sdio_func *func;
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return err;
++	}
++
++	func = psdio->func;
++
++	for (i = 0; i < cnt; i++) {
++		pdata[i] = sdio_readb(func, addr + i, &err);
++		if (err) {
++			RTW_ERR("%s: FAIL!(%d) addr=0x%05x\n", __func__, err, addr + i);
++			break;
++		}
++	}
++
++
++	return err;
++}
++
++/*
++ * Return:
++ *	0		Success
++ *	others	Fail
++ */
++s32 sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	int err = 0, i;
++	struct sdio_func *func;
++	bool claim_needed;
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return err;
++	}
++
++	func = psdio->func;
++	claim_needed = rtw_sdio_claim_host_needed(func);
++
++	if (claim_needed)
++		sdio_claim_host(func);
++	err = _sd_cmd52_read(pintfhdl, addr, cnt, pdata);
++	if (claim_needed)
++		sdio_release_host(func);
++
++
++	return err;
++}
++
++/*
++ * Return:
++ *	0		Success
++ *	others	Fail
++ */
++s32 _sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	int err = 0, i;
++	struct sdio_func *func;
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return err;
++	}
++
++	func = psdio->func;
++
++	for (i = 0; i < cnt; i++) {
++		sdio_writeb(func, pdata[i], addr + i, &err);
++		if (err) {
++			RTW_ERR("%s: FAIL!(%d) addr=0x%05x val=0x%02x\n", __func__, err, addr + i, pdata[i]);
++			break;
++		}
++	}
++
++
++	return err;
++}
++
++/*
++ * Return:
++ *	0		Success
++ *	others	Fail
++ */
++s32 sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	int err = 0, i;
++	struct sdio_func *func;
++	bool claim_needed;
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return err;
++	}
++
++	func = psdio->func;
++	claim_needed = rtw_sdio_claim_host_needed(func);
++
++	if (claim_needed)
++		sdio_claim_host(func);
++	err = _sd_cmd52_write(pintfhdl, addr, cnt, pdata);
++	if (claim_needed)
++		sdio_release_host(func);
++
++
++	return err;
++}
++
++u8 _sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	u8 v = 0;
++	struct sdio_func *func;
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return v;
++	}
++
++	func = psdio->func;
++
++	v = sdio_readb(func, addr, err);
++
++	if (err && *err)
++		RTW_ERR("%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr);
++
++
++	return v;
++}
++
++u8 sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	u8 v = 0;
++	struct sdio_func *func;
++	bool claim_needed;
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return v;
++	}
++
++	func = psdio->func;
++	claim_needed = rtw_sdio_claim_host_needed(func);
++
++	if (claim_needed)
++		sdio_claim_host(func);
++	v = sdio_readb(func, addr, err);
++	if (claim_needed)
++		sdio_release_host(func);
++	if (err && *err)
++		RTW_ERR("%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr);
++
++
++	return v;
++}
++
++u16 sd_read16(struct intf_hdl *pintfhdl, u32 addr, s32 *err)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	u16 v = 0;
++	struct sdio_func *func;
++	bool claim_needed;
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return v;
++	}
++
++	func = psdio->func;
++	claim_needed = rtw_sdio_claim_host_needed(func);
++
++	if (claim_needed)
++		sdio_claim_host(func);
++	v = sdio_readw(func, addr, err);
++	if (claim_needed)
++		sdio_release_host(func);
++	if (err && *err)
++		RTW_ERR("%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr);
++
++
++	return  v;
++}
++
++u32 _sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	u32 v = 0;
++	struct sdio_func *func;
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return v;
++	}
++
++	func = psdio->func;
++
++	v = sdio_readl(func, addr, err);
++
++	if (err && *err) {
++		int i;
++
++		RTW_ERR("%s: (%d) addr=0x%05x, val=0x%x\n", __func__, *err, addr, v);
++
++		*err = 0;
++		for (i = 0; i < SD_IO_TRY_CNT; i++) {
++			/* sdio_claim_host(func); */
++			v = sdio_readl(func, addr, err);
++			/* sdio_release_host(func); */
++			if (*err == 0) {
++				rtw_reset_continual_io_error(psdiodev);
++				break;
++			} else {
++				RTW_ERR("%s: (%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i);
++				if ((-ESHUTDOWN == *err) || (-ENODEV == *err))
++					rtw_set_surprise_removed(padapter);
++
++				if (rtw_inc_and_chk_continual_io_error(psdiodev) == _TRUE) {
++					rtw_set_surprise_removed(padapter);
++					break;
++				}
++
++			}
++		}
++
++		if (i == SD_IO_TRY_CNT)
++			RTW_ERR("%s: FAIL!(%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i);
++		else
++			RTW_ERR("%s: (%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i);
++
++	}
++
++
++	return  v;
++}
++
++u32 sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	u32 v = 0;
++	struct sdio_func *func;
++	bool claim_needed;
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return v;
++	}
++
++	func = psdio->func;
++	claim_needed = rtw_sdio_claim_host_needed(func);
++
++	if (claim_needed)
++		sdio_claim_host(func);
++	v = sdio_readl(func, addr, err);
++	if (claim_needed)
++		sdio_release_host(func);
++
++	if (err && *err) {
++		int i;
++
++		RTW_ERR("%s: (%d) addr=0x%05x, val=0x%x\n", __func__, *err, addr, v);
++
++		*err = 0;
++		for (i = 0; i < SD_IO_TRY_CNT; i++) {
++			if (claim_needed)
++				sdio_claim_host(func);
++			v = sdio_readl(func, addr, err);
++			if (claim_needed)
++				sdio_release_host(func);
++
++			if (*err == 0) {
++				rtw_reset_continual_io_error(psdiodev);
++				break;
++			} else {
++				RTW_ERR("%s: (%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i);
++				if ((-ESHUTDOWN == *err) || (-ENODEV == *err))
++					rtw_set_surprise_removed(padapter);
++
++				if (rtw_inc_and_chk_continual_io_error(psdiodev) == _TRUE) {
++					rtw_set_surprise_removed(padapter);
++					break;
++				}
++			}
++		}
++
++		if (i == SD_IO_TRY_CNT)
++			RTW_ERR("%s: FAIL!(%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i);
++		else
++			RTW_ERR("%s: (%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i);
++
++	}
++
++
++	return  v;
++}
++
++void sd_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	struct sdio_func *func;
++	bool claim_needed;
++
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return ;
++	}
++
++	func = psdio->func;
++	claim_needed = rtw_sdio_claim_host_needed(func);
++
++	if (claim_needed)
++		sdio_claim_host(func);
++	sdio_writeb(func, v, addr, err);
++	if (claim_needed)
++		sdio_release_host(func);
++	if (err && *err)
++		RTW_ERR("%s: FAIL!(%d) addr=0x%05x val=0x%02x\n", __func__, *err, addr, v);
++
++}
++
++void sd_write16(struct intf_hdl *pintfhdl, u32 addr, u16 v, s32 *err)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	struct sdio_func *func;
++	bool claim_needed;
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return ;
++	}
++
++	func = psdio->func;
++	claim_needed = rtw_sdio_claim_host_needed(func);
++
++	if (claim_needed)
++		sdio_claim_host(func);
++	sdio_writew(func, v, addr, err);
++	if (claim_needed)
++		sdio_release_host(func);
++	if (err && *err)
++		RTW_ERR("%s: FAIL!(%d) addr=0x%05x val=0x%04x\n", __func__, *err, addr, v);
++
++}
++
++void _sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	struct sdio_func *func;
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return ;
++	}
++
++	func = psdio->func;
++
++	sdio_writel(func, v, addr, err);
++
++	if (err && *err) {
++		int i;
++
++		RTW_ERR("%s: (%d) addr=0x%05x val=0x%08x\n", __func__, *err, addr, v);
++
++		*err = 0;
++		for (i = 0; i < SD_IO_TRY_CNT; i++) {
++			sdio_writel(func, v, addr, err);
++			if (*err == 0) {
++				rtw_reset_continual_io_error(psdiodev);
++				break;
++			} else {
++				RTW_ERR("%s: (%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i);
++				if ((-ESHUTDOWN == *err) || (-ENODEV == *err))
++					rtw_set_surprise_removed(padapter);
++
++				if (rtw_inc_and_chk_continual_io_error(psdiodev) == _TRUE) {
++					rtw_set_surprise_removed(padapter);
++					break;
++				}
++			}
++		}
++
++		if (i == SD_IO_TRY_CNT)
++			RTW_ERR("%s: FAIL!(%d) addr=0x%05x val=0x%08x, try_cnt=%d\n", __func__, *err, addr, v, i);
++		else
++			RTW_ERR("%s: (%d) addr=0x%05x val=0x%08x, try_cnt=%d\n", __func__, *err, addr, v, i);
++
++	}
++
++}
++
++void sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++	struct sdio_func *func;
++	bool claim_needed;
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return ;
++	}
++
++	func = psdio->func;
++	claim_needed = rtw_sdio_claim_host_needed(func);
++
++	if (claim_needed)
++		sdio_claim_host(func);
++	sdio_writel(func, v, addr, err);
++	if (claim_needed)
++		sdio_release_host(func);
++
++	if (err && *err) {
++		int i;
++
++		RTW_ERR("%s: (%d) addr=0x%05x val=0x%08x\n", __func__, *err, addr, v);
++
++		*err = 0;
++		for (i = 0; i < SD_IO_TRY_CNT; i++) {
++			if (claim_needed)
++				sdio_claim_host(func);
++			sdio_writel(func, v, addr, err);
++			if (claim_needed)
++				sdio_release_host(func);
++			if (*err == 0) {
++				rtw_reset_continual_io_error(psdiodev);
++				break;
++			} else {
++				RTW_ERR("%s: (%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i);
++				if ((-ESHUTDOWN == *err) || (-ENODEV == *err))
++					rtw_set_surprise_removed(padapter);
++
++				if (rtw_inc_and_chk_continual_io_error(psdiodev) == _TRUE) {
++					rtw_set_surprise_removed(padapter);
++					break;
++				}
++			}
++		}
++
++		if (i == SD_IO_TRY_CNT)
++			RTW_ERR("%s: FAIL!(%d) addr=0x%05x val=0x%08x, try_cnt=%d\n", __func__, *err, addr, v, i);
++		else
++			RTW_ERR("%s: (%d) addr=0x%05x val=0x%08x, try_cnt=%d\n", __func__, *err, addr, v, i);
++	}
++
++}
++#endif /* !RTW_HALMAC */
++
++/*
++ * Use CMD53 to read data from SDIO device.
++ * This function MUST be called after sdio_claim_host() or
++ * in SDIO ISR(host had been claimed).
++ *
++ * Parameters:
++ *	psdio	pointer of SDIO_DATA
++ *	addr	address to read
++ *	cnt		amount to read
++ *	pdata	pointer to put data, this should be a "DMA:able scratch buffer"!
++ *
++ * Return:
++ *	0		Success
++ *	others	Fail
++ */
++s32 _sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	int err = -EPERM;
++	struct sdio_func *func;
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return err;
++	}
++
++	func = psdio->func;
++
++	if (unlikely((cnt == 1) || (cnt == 2))) {
++		int i;
++		u8 *pbuf = (u8 *)pdata;
++
++		for (i = 0; i < cnt; i++) {
++			*(pbuf + i) = sdio_readb(func, addr + i, &err);
++
++			if (err) {
++				RTW_ERR("%s: FAIL!(%d) addr=0x%05x\n", __func__, err, addr);
++				break;
++			}
++		}
++		return err;
++	}
++
++	err = sdio_memcpy_fromio(func, pdata, addr, cnt);
++	if (err)
++		RTW_ERR("%s: FAIL(%d)! ADDR=%#x Size=%d\n", __func__, err, addr, cnt);
++
++	if (err == (-ESHUTDOWN) || err == (-ENODEV) || err == (-ENOMEDIUM) || err == (-ETIMEDOUT))
++		rtw_set_surprise_removed(padapter);
++
++
++	return err;
++}
++
++/*
++ * Use CMD53 to read data from SDIO device.
++ *
++ * Parameters:
++ *	psdio	pointer of SDIO_DATA
++ *	addr	address to read
++ *	cnt		amount to read
++ *	pdata	pointer to put data, this should be a "DMA:able scratch buffer"!
++ *
++ * Return:
++ *	0		Success
++ *	others	Fail
++ */
++s32 sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	struct sdio_func *func;
++	bool claim_needed;
++	s32 err = -EPERM;
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return err;
++	}
++	func = psdio->func;
++	claim_needed = rtw_sdio_claim_host_needed(func);
++
++	if (claim_needed)
++		sdio_claim_host(func);
++	err = _sd_read(pintfhdl, addr, cnt, pdata);
++	if (claim_needed)
++		sdio_release_host(func);
++	return err;
++}
++
++/*
++ * Use CMD53 to write data to SDIO device.
++ * This function MUST be called after sdio_claim_host() or
++ * in SDIO ISR(host had been claimed).
++ *
++ * Parameters:
++ *	psdio	pointer of SDIO_DATA
++ *	addr	address to write
++ *	cnt		amount to write
++ *	pdata	data pointer, this should be a "DMA:able scratch buffer"!
++ *
++ * Return:
++ *	0		Success
++ *	others	Fail
++ */
++s32 _sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	struct sdio_func *func;
++	u32 size;
++	s32 err = -EPERM;
++
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return err;
++	}
++
++	func = psdio->func;
++	/*	size = sdio_align_size(func, cnt); */
++
++	if (unlikely((cnt == 1) || (cnt == 2))) {
++		int i;
++		u8 *pbuf = (u8 *)pdata;
++
++		for (i = 0; i < cnt; i++) {
++			sdio_writeb(func, *(pbuf + i), addr + i, &err);
++			if (err) {
++				RTW_ERR("%s: FAIL!(%d) addr=0x%05x val=0x%02x\n", __func__, err, addr, *(pbuf + i));
++				break;
++			}
++		}
++
++		return err;
++	}
++
++	size = cnt;
++	err = sdio_memcpy_toio(func, addr, pdata, size);
++	if (err)
++		RTW_ERR("%s: FAIL(%d)! ADDR=%#x Size=%d(%d)\n", __func__, err, addr, cnt, size);
++
++
++	return err;
++}
++
++/*
++ * Use CMD53 to write data to SDIO device.
++ *
++ * Parameters:
++ *  psdio	pointer of SDIO_DATA
++ *  addr	address to write
++ *  cnt		amount to write
++ *  pdata	data pointer, this should be a "DMA:able scratch buffer"!
++ *
++ * Return:
++ *  0		Success
++ *  others	Fail
++ */
++s32 sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata)
++{
++	PADAPTER padapter;
++	struct dvobj_priv *psdiodev;
++	PSDIO_DATA psdio;
++
++	struct sdio_func *func;
++	bool claim_needed;
++	s32 err = -EPERM;
++	padapter = pintfhdl->padapter;
++	psdiodev = pintfhdl->pintf_dev;
++	psdio = &psdiodev->intf_data;
++
++	if (rtw_is_surprise_removed(padapter)) {
++		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
++		return err;
++	}
++
++	func = psdio->func;
++	claim_needed = rtw_sdio_claim_host_needed(func);
++
++	if (claim_needed)
++		sdio_claim_host(func);
++	err = _sd_write(pintfhdl, addr, cnt, pdata);
++	if (claim_needed)
++		sdio_release_host(func);
++	return err;
++}
++
++#if 1
++/*#define RTW_SDIO_DUMP*/
++#ifdef RTW_SDIO_DUMP
++#define DUMP_LEN_LMT	0	/* buffer dump size limit */
++				/* unit: byte, 0 for no limit */
++#else 
++#define DUMP_LEN_LMT	32
++#endif
++#define GET_DUMP_LEN(len)	(DUMP_LEN_LMT ? rtw_min(len, DUMP_LEN_LMT) : len)
++
++#ifdef DBG_SDIO
++#if (DBG_SDIO >= 1)
++static void sdio_dump_reg_by_cmd52(struct dvobj_priv *d,
++				   u32 addr, size_t len, u8 *buf)
++{
++	struct sdio_func *func;
++	size_t i;
++	u8 val;
++	u8 str[80], used = 0;
++	u8 read_twice = 0;
++	int error;
++
++
++	if (buf)
++		_rtw_memset(buf, 0xAE, len);
++	func = dvobj_to_sdio_func(d);
++	/*
++	 * When register is WLAN IOREG,
++	 * read twice to guarantee the result is correct.
++	 */
++	if (addr & 0x10000)
++		read_twice = 1;
++
++	_rtw_memset(str, 0, 80);
++	used = 0;
++	if (addr & 0xF) {
++		used += snprintf(str+used, (80-used), "0x%02x:\t", addr&~0xF);
++		used += snprintf(str+used, (80-used), "%*s", (addr&0xF)*5, "");
++	}
++	for (i = 0; i < len; i++, addr++) {
++		val = sdio_readb(func, addr, &error);
++		if (read_twice)
++			val = sdio_readb(func, addr, &error);
++		if (error)
++			break;
++
++		if (buf)
++			buf[i] = val;
++
++		if (!(addr & 0xF))
++			used += snprintf(str+used, (80-used), "0x%02x:\t", addr&~0xF);
++		used += snprintf(str+used, (80-used), "%02x ", val);
++		if (((i + 1) < len) && ((addr + 1) & 0xF) == 0) {
++			dev_err(&func->dev, "%s", str);
++			_rtw_memset(str, 0, 80);
++			used = 0;
++		}
++	}
++
++	if (used) {
++		dev_err(&func->dev, "%s", str);
++		_rtw_memset(str, 0, 80);
++		used = 0;
++	}
++
++	if (error)
++		dev_err(&func->dev, "rtw_sdio_dbg: READ 0x%02x FAIL!", addr);
++}
++
++static void sdio_dump_cia(struct dvobj_priv *d, u32 addr, size_t len, u8 *buf)
++{
++	struct sdio_func *func;
++	size_t i;
++	u8 val;
++	u8 str[80], used = 0;
++	int error;
++
++
++	if (buf)
++		_rtw_memset(buf, 0xAE, len);
++	func = dvobj_to_sdio_func(d);
++
++	_rtw_memset(str, 0, 80);
++	used = 0;
++	if (addr & 0xF) {
++		used += snprintf(str+used, (80-used), "0x%02x:\t", addr&~0xF);
++		used += snprintf(str+used, (80-used), "%*s", (addr&0xF)*5, "");
++	}
++	for (i = 0; i < len; i++, addr++) {
++		val = sdio_f0_readb(func, addr, &error);
++		if (error)
++			break;
++
++		if (buf)
++			buf[i] = val;
++
++		if (!(addr & 0xF))
++			used += snprintf(str+used, (80-used), "0x%02x:\t", addr&~0xF);
++		used += snprintf(str+used, (80-used), "%02x ", val);
++		if (((i + 1) < len) && ((addr + 1) & 0xF) == 0) {
++			dev_err(&func->dev, "%s", str);
++			_rtw_memset(str, 0, 80);
++			used = 0;
++		}
++	}
++
++	if (used) {
++		dev_err(&func->dev, "%s", str);
++		_rtw_memset(str, 0, 80);
++		used = 0;
++	}
++
++	if (error)
++		dev_err(&func->dev, "rtw_sdio_dbg: READ CIA 0x%02x FAIL!",
++			addr);
++}
++
++#if (DBG_SDIO >= 2)
++void rtw_sdio_dbg_reg_alloc(struct dvobj_priv *d);
++#endif /* DBG_SDIO >= 2 */
++
++/*
++ * Dump register when CMD53 fail
++ */
++static void sdio_dump_dbg_reg(struct dvobj_priv *d, u8 write,
++			      unsigned int addr, size_t len)
++{
++	struct sdio_data *sdio;
++	struct sdio_func *func;
++	u8 *buf = NULL;
++#if (DBG_SDIO >= 2)
++	u8 *msg;
++#endif /* DBG_SDIO >= 2 */
++
++
++	sdio = &d->intf_data;
++	if (sdio->reg_dump_mark)
++		return;
++	func = dvobj_to_sdio_func(d);
++
++	sdio->reg_dump_mark = sdio->cmd53_err_cnt;
++
++#if (DBG_SDIO >= 2)
++	if (!sdio->dbg_msg) {
++		msg = rtw_zmalloc(80);
++		if (msg) {
++			sdio->dbg_msg = msg;
++			sdio->dbg_msg_size = 80;
++		}
++	}
++	if (sdio->dbg_msg_size) {
++		snprintf(sdio->dbg_msg, sdio->dbg_msg_size,
++			 "CMD53 %s 0x%05x, %zu bytes FAIL "
++			 "at err_cnt=%d",
++			 write?"WRITE":"READ",
++			 addr, len, sdio->reg_dump_mark);
++	}
++
++	rtw_sdio_dbg_reg_alloc(d);
++#endif /* DBG_SDIO >= 2 */
++
++	/* MAC register */
++	dev_err(&func->dev, "MAC register:");
++#if (DBG_SDIO >= 2)
++	buf = sdio->reg_mac;
++#endif /* DBG_SDIO >= 2 */
++	sdio_dump_reg_by_cmd52(d, 0x10000, 0x800, buf);
++	dev_err(&func->dev, "MAC Extend register:");
++#if (DBG_SDIO >= 2)
++	buf = sdio->reg_mac_ext;
++#endif /* DBG_SDIO >= 2 */
++	sdio_dump_reg_by_cmd52(d, 0x11000, 0x800, buf);
++
++	/* SDIO local register */
++	dev_err(&func->dev, "SDIO Local register:");
++#if (DBG_SDIO >= 2)
++	buf = sdio->reg_local;
++#endif /* DBG_SDIO >= 2 */
++	sdio_dump_reg_by_cmd52(d, 0x0, 0x100, buf);
++
++	/* F0 */
++	dev_err(&func->dev, "f0 register:");
++#if (DBG_SDIO >= 2)
++	buf = sdio->reg_cia;
++#endif /* DBG_SDIO >= 2 */
++	sdio_dump_cia(d, 0x0, 0x200, buf);
++}
++#endif /* DBG_SDIO >= 1 */
++#endif /* DBG_SDIO */
++
++/**
++ *	Returns driver error code,
++ *	0	no error
++ *	-1	Level 1 error, critical error and can't be recovered
++ *	-2	Level 2 error, normal error, retry to recover is possible
++ */
++static int linux_io_err_to_drv_err(int err)
++{
++	if (!err)
++		return 0;
++
++	/* critical error */
++	if ((err == -ESHUTDOWN) ||
++	    (err == -ENODEV) ||
++	    (err == -ENOMEDIUM))
++		return -1;
++
++	/* other error */
++	return -2;
++}
++
++/**
++ *	rtw_sdio_raw_read - Read from SDIO device
++ *	@d: driver object private data
++ *	@addr: address to read
++ *	@buf: buffer to store the data
++ *	@len: number of bytes to read
++ *	@fixed:
++ *
++ *	Reads from the address space of a SDIO device.
++ *	Return value indicates if the transfer succeeded or not.
++ */
++int __must_check rtw_sdio_raw_read(struct dvobj_priv *d, unsigned int addr,
++				   void *buf, size_t len, bool fixed)
++{
++	int error = -EPERM;
++	bool f0, cmd52;
++	struct sdio_func *func;
++	bool claim_needed;
++	u32 offset, i;
++
++
++	func = dvobj_to_sdio_func(d);
++	claim_needed = rtw_sdio_claim_host_needed(func);
++	f0 = RTW_SDIO_ADDR_F0_CHK(addr);
++	cmd52 = RTW_SDIO_ADDR_CMD52_CHK(addr);
++
++	/*
++	 * Mask addr to remove driver defined bit and
++	 * make sure addr is in valid range
++	 */
++	if (f0)
++		addr &= 0xFFF;
++	else
++		addr &= 0x1FFFF;
++
++#ifdef RTW_SDIO_DUMP
++	if (f0)
++		dev_dbg(&func->dev, "rtw_sdio: READ F0\n");
++	else if (cmd52)
++		dev_dbg(&func->dev, "rtw_sdio: READ use CMD52\n");
++	else
++		dev_dbg(&func->dev, "rtw_sdio: READ use CMD53\n");
++
++	dev_dbg(&func->dev, "rtw_sdio: READ from 0x%05x\n", addr);
++#endif /* RTW_SDIO_DUMP */
++
++	if (claim_needed)
++		sdio_claim_host(func);
++
++	if (f0) {
++		offset = addr;
++		for (i = 0; i < len; i++, offset++) {
++			((u8 *)buf)[i] = sdio_f0_readb(func, offset, &error);
++			if (error)
++				break;
++#if 0
++			dev_info(&func->dev, "%s: sdio f0 read 52 addr 0x%x, byte 0x%02x\n",
++				 __func__, offset, ((u8 *)buf)[i]);
++#endif
++		}
++	} else {
++		if (cmd52) {
++#ifdef RTW_SDIO_IO_DBG
++			dev_info(&func->dev, "%s: sdio read 52 addr 0x%x, %zu bytes\n",
++				 __func__, addr, len);
++#endif
++			offset = addr;
++			for (i = 0; i < len; i++) {
++				((u8 *)buf)[i] = sdio_readb(func, offset, &error);
++				if (error)
++					break;
++#if 0
++				dev_info(&func->dev, "%s: sdio read 52 addr 0x%x, byte 0x%02x\n",
++					 __func__, offset, ((u8 *)buf)[i]);
++#endif
++				if (!fixed)
++					offset++;
++			}
++		} else {
++#ifdef RTW_SDIO_IO_DBG
++			dev_info(&func->dev, "%s: sdio read 53 addr 0x%x, %zu bytes\n",
++				 __func__, addr, len);
++#endif
++			if (fixed)
++				error = sdio_readsb(func, buf, addr, len);
++			else
++				error = sdio_memcpy_fromio(func, buf, addr, len);
++		}
++	}
++
++#ifdef DBG_SDIO
++#if (DBG_SDIO >= 3)
++	if (!error && !f0 && !cmd52
++	    && (d->intf_data.dbg_enable
++		&& d->intf_data.err_test && !d->intf_data.err_test_triggered
++		&& ((addr & 0x10000)
++		    || (!(addr & 0xE000)
++			&& !((addr >= 0x40) && (addr < 0x48)))))) {
++		d->intf_data.err_test_triggered = 1;
++		error = -ETIMEDOUT;
++		dev_warn(&func->dev, "Simulate error(%d) READ addr=0x%05x %zu bytes",
++			 error, addr, len);
++	}
++#endif /* DBG_SDIO >= 3 */
++
++	if (error) {
++		if (f0 || cmd52) {
++			d->intf_data.cmd52_err_cnt++;
++		} else {
++			d->intf_data.cmd53_err_cnt++;
++#if (DBG_SDIO >= 1)
++			sdio_dump_dbg_reg(d, 0, addr, len);
++#endif /* DBG_SDIO >= 1 */
++		}
++	}
++#endif /* DBG_SDIO */
++
++	if (claim_needed)
++		sdio_release_host(func);
++
++#ifdef RTW_SDIO_DUMP
++	print_hex_dump(KERN_DEBUG, "rtw_sdio: READ ",
++		       DUMP_PREFIX_OFFSET, 16, 1,
++		       buf, GET_DUMP_LEN(len), false);
++#endif /* RTW_SDIO_DUMP */
++
++	if (WARN_ON(error)) {
++		dev_err(&func->dev, "%s: sdio read failed (%d)\n", __func__, error);
++#ifndef RTW_SDIO_DUMP
++		if (f0)
++			dev_err(&func->dev, "rtw_sdio: READ F0\n");
++		if (cmd52)
++			dev_err(&func->dev, "rtw_sdio: READ use CMD52\n");
++		else
++			dev_err(&func->dev, "rtw_sdio: READ use CMD53\n");
++		dev_err(&func->dev, "rtw_sdio: READ from 0x%05x, %zu bytes\n", addr, len);
++		print_hex_dump(KERN_ERR, "rtw_sdio: READ ",
++			       DUMP_PREFIX_OFFSET, 16, 1,
++			       buf, GET_DUMP_LEN(len), false);
++#endif /* !RTW_SDIO_DUMP */
++	}
++
++	return linux_io_err_to_drv_err(error);
++}
++
++/**
++ *	rtw_sdio_raw_write - Write to SDIO device
++ *	@d: driver object private data
++ *	@addr: address to write
++ *	@buf: buffer that contains the data to write
++ *	@len: number of bytes to write
++ *	@fixed: address is fixed(FIFO) or incremented
++ *
++ *	Writes to the address space of a SDIO device.
++ *	Return value indicates if the transfer succeeded or not.
++ */
++int __must_check rtw_sdio_raw_write(struct dvobj_priv *d, unsigned int addr,
++				    void *buf, size_t len, bool fixed)
++{
++	int error = -EPERM;
++	bool f0, cmd52;
++	struct sdio_func *func;
++	bool claim_needed;
++	u32 offset, i;
++
++
++	func = dvobj_to_sdio_func(d);
++	claim_needed = rtw_sdio_claim_host_needed(func);
++	f0 = RTW_SDIO_ADDR_F0_CHK(addr);
++	cmd52 = RTW_SDIO_ADDR_CMD52_CHK(addr);
++
++	/*
++	 * Mask addr to remove driver defined bit and
++	 * make sure addr is in valid range
++	 */
++	if (f0)
++		addr &= 0xFFF;
++	else
++		addr &= 0x1FFFF;
++
++#ifdef RTW_SDIO_DUMP
++	if (f0)
++		dev_dbg(&func->dev, "rtw_sdio: WRITE F0\n");
++	else if (cmd52)
++		dev_dbg(&func->dev, "rtw_sdio: WRITE use CMD52\n");
++	else
++		dev_dbg(&func->dev, "rtw_sdio: WRITE use CMD53\n");
++	dev_dbg(&func->dev, "rtw_sdio: WRITE to 0x%05x\n", addr);
++	print_hex_dump(KERN_DEBUG, "rtw_sdio: WRITE ",
++		       DUMP_PREFIX_OFFSET, 16, 1,
++		       buf, GET_DUMP_LEN(len), false);
++#endif /* RTW_SDIO_DUMP */
++
++	if (claim_needed)
++		sdio_claim_host(func);
++
++	if (f0) {
++		offset = addr;
++		for (i = 0; i < len; i++, offset++) {
++			sdio_f0_writeb(func, ((u8 *)buf)[i], offset, &error);
++			if (error)
++				break;
++#if 0
++			dev_info(&func->dev, "%s: sdio f0 write 52 addr 0x%x, byte 0x%02x\n",
++				 __func__, offset, ((u8 *)buf)[i]);
++#endif
++		}
++	} else {
++		if (cmd52) {
++#ifdef RTW_SDIO_IO_DBG
++			dev_info(&func->dev, "%s: sdio write 52 addr 0x%x, %zu bytes\n",
++				 __func__, addr, len);
++#endif
++			offset = addr;
++			for (i = 0; i < len; i++) {
++				sdio_writeb(func, ((u8 *)buf)[i], offset, &error);
++				if (error)
++					break;
++#if 0
++				dev_info(&func->dev, "%s: sdio write 52 addr 0x%x, byte 0x%02x\n",
++					 __func__, offset, ((u8 *)buf)[i]);
++#endif
++				if (!fixed)
++					offset++;
++			}
++		} else {
++#ifdef RTW_SDIO_IO_DBG
++			dev_info(&func->dev, "%s: sdio write 53 addr 0x%x, %zu bytes\n",
++				 __func__, addr, len);
++#endif
++			if (fixed)
++				error = sdio_writesb(func, addr, buf, len);
++			else
++				error = sdio_memcpy_toio(func, addr, buf, len);
++		}
++	}
++
++#ifdef DBG_SDIO
++	if (error) {
++		if (f0 || cmd52) {
++			d->intf_data.cmd52_err_cnt++;
++		} else {
++			d->intf_data.cmd53_err_cnt++;
++#if (DBG_SDIO >= 1)
++			sdio_dump_dbg_reg(d, 1, addr, len);
++#endif /* DBG_SDIO >= 1 */
++		}
++	}
++#endif /* DBG_SDIO */
++
++	if (claim_needed)
++		sdio_release_host(func);
++
++	if (WARN_ON(error)) {
++		dev_err(&func->dev, "%s: sdio write failed (%d)\n", __func__, error);
++#ifndef RTW_SDIO_DUMP
++		if (f0)
++			dev_err(&func->dev, "rtw_sdio: WRITE F0\n");
++		if (cmd52)
++			dev_err(&func->dev, "rtw_sdio: WRITE use CMD52\n");
++		else
++			dev_err(&func->dev, "rtw_sdio: WRITE use CMD53\n");
++		dev_err(&func->dev, "rtw_sdio: WRITE to 0x%05x, %zu bytes\n", addr, len);
++		print_hex_dump(KERN_ERR, "rtw_sdio: WRITE ",
++			       DUMP_PREFIX_OFFSET, 16, 1,
++			       buf, GET_DUMP_LEN(len), false);
++#endif /* !RTW_SDIO_DUMP */
++	}
++
++	return linux_io_err_to_drv_err(error);
++}
++#endif
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/wifi_regd.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/wifi_regd.c
+new file mode 100644
+index 000000000..c4bfc005b
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/wifi_regd.c
+@@ -0,0 +1,128 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2009-2010 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include <drv_types.h>
++
++#ifdef CONFIG_IOCTL_CFG80211
++void rtw_regd_apply_flags(struct wiphy *wiphy)
++{
++	struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);
++	struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
++	RT_CHANNEL_INFO *channel_set = rfctl->channel_set;
++	u8 max_chan_nums = rfctl->max_chan_nums;
++
++	struct ieee80211_supported_band *sband;
++	struct ieee80211_channel *ch;
++	unsigned int i, j;
++	u16 channel;
++	u32 freq;
++
++	/* all channels disable */
++	for (i = 0; i < NUM_NL80211_BANDS; i++) {
++		sband = wiphy->bands[i];
++		if (!sband)
++			continue;
++		for (j = 0; j < sband->n_channels; j++) {
++			ch = &sband->channels[j];
++			if (!ch)
++				continue;
++			ch->flags = IEEE80211_CHAN_DISABLED;
++		}
++	}
++
++	/* channels apply by channel plans. */
++	for (i = 0; i < max_chan_nums; i++) {
++		channel = channel_set[i].ChannelNum;
++		freq = rtw_ch2freq(channel);
++		ch = ieee80211_get_channel(wiphy, freq);
++		if (!ch)
++			continue;
++
++		/* enable */
++		ch->flags = 0;
++
++		if (channel_set[i].dfs) {
++			/*
++			* before integrating with nl80211 flow
++			* bypass IEEE80211_CHAN_RADAR when configured with radar detection
++			* to prevent from hostapd blocking DFS channels
++			*/
++			if (rtw_rfctl_dfs_domain_unknown(rfctl))
++				ch->flags |= IEEE80211_CHAN_RADAR;
++		}
++
++		if (channel_set[i].ScanType == SCAN_PASSIVE) {
++			#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
++			ch->flags |= IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN;
++			#else
++			ch->flags |= IEEE80211_CHAN_NO_IR;
++			#endif
++		}
++	}
++}
++
++static void rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
++{
++	switch (request->initiator) {
++	case NL80211_REGDOM_SET_BY_DRIVER:
++		RTW_INFO("%s: %s\n", __func__, "NL80211_REGDOM_SET_BY_DRIVER");
++		break;
++	case NL80211_REGDOM_SET_BY_CORE:
++		RTW_INFO("%s: %s\n", __func__, "NL80211_REGDOM_SET_BY_CORE");
++		break;
++	case NL80211_REGDOM_SET_BY_USER:
++		RTW_INFO("%s: %s alpha2:%c%c\n", __func__, "NL80211_REGDOM_SET_BY_USER"
++			, request->alpha2[0], request->alpha2[1]);
++		rtw_set_country(wiphy_to_adapter(wiphy), request->alpha2);
++		break;
++	case NL80211_REGDOM_SET_BY_COUNTRY_IE:
++		RTW_INFO("%s: %s\n", __func__, "NL80211_REGDOM_SET_BY_COUNTRY_IE");
++		break;
++	}
++
++	rtw_regd_apply_flags(wiphy);
++}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
++static int rtw_reg_notifier_return(struct wiphy *wiphy, struct regulatory_request *request)
++{
++	rtw_reg_notifier(wiphy, request);
++	return 0;
++}
++#endif
++
++int rtw_regd_init(struct wiphy *wiphy)
++{
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
++	wiphy->reg_notifier = rtw_reg_notifier_return;
++#else
++	wiphy->reg_notifier = rtw_reg_notifier;
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
++	wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY;
++	wiphy->flags &= ~WIPHY_FLAG_STRICT_REGULATORY;
++	wiphy->flags &= ~WIPHY_FLAG_DISABLE_BEACON_HINTS;
++#else
++	wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG;
++	wiphy->regulatory_flags &= ~REGULATORY_STRICT_REG;
++	wiphy->regulatory_flags &= ~REGULATORY_DISABLE_BEACON_HINTS;
++#endif
++
++	rtw_regd_apply_flags(wiphy);
++
++	return 0;
++}
++#endif /* CONFIG_IOCTL_CFG80211 */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/wifi_regd.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/wifi_regd.h
+new file mode 100644
+index 000000000..94c16a3f3
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/wifi_regd.h
+@@ -0,0 +1,22 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2009-2010 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __WIFI_REGD_H__
++#define __WIFI_REGD_H__
++
++void rtw_regd_apply_flags(struct wiphy *wiphy);
++int rtw_regd_init(struct wiphy *wiphy);
++
++#endif /* __WIFI_REGD_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/xmit_linux.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/xmit_linux.c
+new file mode 100644
+index 000000000..fdcba46c5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/linux/xmit_linux.c
+@@ -0,0 +1,538 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _XMIT_OSDEP_C_
++
++#include <drv_types.h>
++
++#define DBG_DUMP_OS_QUEUE_CTL 0
++
++uint rtw_remainder_len(struct pkt_file *pfile)
++{
++	return pfile->buf_len - ((SIZE_PTR)(pfile->cur_addr) - (SIZE_PTR)(pfile->buf_start));
++}
++
++void _rtw_open_pktfile(_pkt *pktptr, struct pkt_file *pfile)
++{
++
++	pfile->pkt = pktptr;
++	pfile->cur_addr = pfile->buf_start = pktptr->data;
++	pfile->pkt_len = pfile->buf_len = pktptr->len;
++
++	pfile->cur_buffer = pfile->buf_start ;
++
++}
++
++uint _rtw_pktfile_read(struct pkt_file *pfile, u8 *rmem, uint rlen)
++{
++	uint	len = 0;
++
++
++	len =  rtw_remainder_len(pfile);
++	len = (rlen > len) ? len : rlen;
++
++	if (rmem)
++		skb_copy_bits(pfile->pkt, pfile->buf_len - pfile->pkt_len, rmem, len);
++
++	pfile->cur_addr += len;
++	pfile->pkt_len -= len;
++
++
++	return len;
++}
++
++sint rtw_endofpktfile(struct pkt_file *pfile)
++{
++
++	if (pfile->pkt_len == 0) {
++		return _TRUE;
++	}
++
++
++	return _FALSE;
++}
++
++void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib)
++{
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX	
++	struct sk_buff *skb = (struct sk_buff *)pkt;
++	struct iphdr *iph = NULL;
++	struct ipv6hdr *i6ph = NULL;
++	struct udphdr *uh = NULL;
++	struct tcphdr *th = NULL;
++	u8 	protocol = 0xFF;
++
++	if (skb->protocol == htons(ETH_P_IP)) {
++		iph = (struct iphdr *)skb_network_header(skb);
++		protocol = iph->protocol;
++	} else if (skb->protocol == htons(ETH_P_IPV6)) {
++		i6ph = (struct ipv6hdr *)skb_network_header(skb);
++		protocol = i6ph->nexthdr;
++	} else
++		{}
++
++	/*	HW unable to compute CSUM if header & payload was be encrypted by SW(cause TXDMA error) */
++	if (pattrib->bswenc == _TRUE) {
++		if (skb->ip_summed == CHECKSUM_PARTIAL)
++			skb_checksum_help(skb);
++		return;
++	}
++
++	/*	For HW rule, clear ipv4_csum & UDP/TCP_csum if it is UDP/TCP packet	*/
++	switch (protocol) {
++	case IPPROTO_UDP:
++		uh = (struct udphdr *)skb_transport_header(skb);
++		uh->check = 0;
++		if (iph)
++			iph->check = 0;
++		pattrib->hw_csum = _TRUE;
++		break;
++	case IPPROTO_TCP:
++		th = (struct tcphdr *)skb_transport_header(skb);
++		th->check = 0;
++		if (iph)
++			iph->check = 0;
++		pattrib->hw_csum = _TRUE;
++		break;
++	default:
++		break;
++	}
++#endif
++
++}
++
++int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 alloc_sz, u8 flag)
++{
++	if (alloc_sz > 0) {
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX
++		struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
++		struct usb_device	*pusbd = pdvobjpriv->pusbdev;
++
++		pxmitbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)alloc_sz, &pxmitbuf->dma_transfer_addr);
++		pxmitbuf->pbuf = pxmitbuf->pallocated_buf;
++		if (pxmitbuf->pallocated_buf == NULL)
++			return _FAIL;
++#else /* CONFIG_USE_USB_BUFFER_ALLOC_TX */
++
++		pxmitbuf->pallocated_buf = rtw_zmalloc(alloc_sz);
++		if (pxmitbuf->pallocated_buf == NULL)
++			return _FAIL;
++
++		pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ);
++
++#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */
++	}
++
++	if (flag) {
++#ifdef CONFIG_USB_HCI
++		int i;
++		for (i = 0; i < 8; i++) {
++			pxmitbuf->pxmit_urb[i] = usb_alloc_urb(0, GFP_KERNEL);
++			if (pxmitbuf->pxmit_urb[i] == NULL) {
++				RTW_INFO("pxmitbuf->pxmit_urb[i]==NULL");
++				return _FAIL;
++			}
++		}
++#endif
++	}
++
++	return _SUCCESS;
++}
++
++void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 free_sz, u8 flag)
++{
++	if (flag) {
++#ifdef CONFIG_USB_HCI
++		int i;
++
++		for (i = 0; i < 8; i++) {
++			if (pxmitbuf->pxmit_urb[i]) {
++				/* usb_kill_urb(pxmitbuf->pxmit_urb[i]); */
++				usb_free_urb(pxmitbuf->pxmit_urb[i]);
++			}
++		}
++#endif
++	}
++
++	if (free_sz > 0) {
++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX
++		struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
++		struct usb_device	*pusbd = pdvobjpriv->pusbdev;
++
++		rtw_usb_buffer_free(pusbd, (size_t)free_sz, pxmitbuf->pallocated_buf, pxmitbuf->dma_transfer_addr);
++		pxmitbuf->pallocated_buf =  NULL;
++		pxmitbuf->dma_transfer_addr = 0;
++#else	/* CONFIG_USE_USB_BUFFER_ALLOC_TX */
++		if (pxmitbuf->pallocated_buf)
++			rtw_mfree(pxmitbuf->pallocated_buf, free_sz);
++#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */
++	}
++}
++
++void dump_os_queue(void *sel, _adapter *padapter)
++{
++	struct net_device *ndev = padapter->pnetdev;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	int i;
++
++	for (i = 0; i < 4; i++) {
++		RTW_PRINT_SEL(sel, "os_queue[%d]:%s\n"
++			, i, __netif_subqueue_stopped(ndev, i) ? "stopped" : "waked");
++	}
++#else
++	RTW_PRINT_SEL(sel, "os_queue:%s\n"
++		      , netif_queue_stopped(ndev) ? "stopped" : "waked");
++#endif
++}
++
++#define WMM_XMIT_THRESHOLD	(NR_XMITFRAME*2/5)
++
++static inline bool rtw_os_need_wake_queue(_adapter *padapter, u16 os_qid)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++
++	if (padapter->registrypriv.wifi_spec) {
++		if (pxmitpriv->hwxmits[os_qid].accnt < WMM_XMIT_THRESHOLD)
++			return _TRUE;
++#ifdef DBG_CONFIG_ERROR_DETECT
++#ifdef DBG_CONFIG_ERROR_RESET
++	} else if (rtw_hal_sreset_inprogress(padapter) == _TRUE) {
++		return _FALSE;
++#endif/* #ifdef DBG_CONFIG_ERROR_RESET */
++#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */
++	} else {
++#ifdef CONFIG_MCC_MODE
++		if (MCC_EN(padapter)) {
++			if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)
++			    && MCC_STOP(padapter))
++				return _FALSE;
++		}
++#endif /* CONFIG_MCC_MODE */
++		return _TRUE;
++	}
++	return _FALSE;
++#else
++#ifdef CONFIG_MCC_MODE
++	if (MCC_EN(padapter)) {
++		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)
++		    && MCC_STOP(padapter))
++			return _FALSE;
++	}
++#endif /* CONFIG_MCC_MODE */
++	return _TRUE;
++#endif
++}
++
++static inline bool rtw_os_need_stop_queue(_adapter *padapter, u16 os_qid)
++{
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	if (padapter->registrypriv.wifi_spec) {
++		/* No free space for Tx, tx_worker is too slow */
++		if (pxmitpriv->hwxmits[os_qid].accnt > WMM_XMIT_THRESHOLD)
++			return _TRUE;
++	} else {
++		if (pxmitpriv->free_xmitframe_cnt <= 4)
++			return _TRUE;
++	}
++#else
++	if (pxmitpriv->free_xmitframe_cnt <= 4)
++		return _TRUE;
++#endif
++	return _FALSE;
++}
++
++void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt)
++{
++	rtw_skb_free(pkt);
++}
++
++void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe)
++{
++	if (pxframe->pkt)
++		rtw_os_pkt_complete(padapter, pxframe->pkt);
++
++	pxframe->pkt = NULL;
++}
++
++void rtw_os_xmit_schedule(_adapter *padapter)
++{
++#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
++	_adapter *pri_adapter;
++
++	if (!padapter)
++		return;
++	pri_adapter = GET_PRIMARY_ADAPTER(padapter);
++
++	if (_rtw_queue_empty(&padapter->xmitpriv.pending_xmitbuf_queue) == _FALSE)
++		_rtw_up_sema(&pri_adapter->xmitpriv.xmit_sema);
++
++
++#else
++	_irqL  irqL;
++	struct xmit_priv *pxmitpriv;
++
++	if (!padapter)
++		return;
++
++	pxmitpriv = &padapter->xmitpriv;
++
++	_enter_critical_bh(&pxmitpriv->lock, &irqL);
++
++	if (rtw_txframes_pending(padapter))
++		tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
++
++	_exit_critical_bh(&pxmitpriv->lock, &irqL);
++	
++#if defined(CONFIG_PCI_HCI) && defined(CONFIG_XMIT_THREAD_MODE)
++	if (_rtw_queue_empty(&padapter->xmitpriv.pending_xmitbuf_queue) == _FALSE)
++		_rtw_up_sema(&padapter->xmitpriv.xmit_sema);
++#endif
++	
++
++#endif
++}
++
++void rtw_os_check_wakup_queue(_adapter *adapter, u16 os_qid)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	if (rtw_os_need_wake_queue(adapter, os_qid)) {
++		if (DBG_DUMP_OS_QUEUE_CTL)
++			RTW_INFO(FUNC_ADPT_FMT": netif_wake_subqueue[%d]\n", FUNC_ADPT_ARG(adapter), os_qid);
++		netif_wake_subqueue(adapter->pnetdev, os_qid);
++	}
++#else
++	if (rtw_os_need_wake_queue(adapter, 0)) {
++		if (DBG_DUMP_OS_QUEUE_CTL)
++			RTW_INFO(FUNC_ADPT_FMT": netif_wake_queue\n", FUNC_ADPT_ARG(adapter));
++		netif_wake_queue(adapter->pnetdev);
++	}
++#endif
++}
++
++bool rtw_os_check_stop_queue(_adapter *adapter, u16 os_qid)
++{
++	bool busy = _FALSE;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	if (rtw_os_need_stop_queue(adapter, os_qid)) {
++		if (DBG_DUMP_OS_QUEUE_CTL)
++			RTW_INFO(FUNC_ADPT_FMT": netif_stop_subqueue[%d]\n", FUNC_ADPT_ARG(adapter), os_qid);
++		netif_stop_subqueue(adapter->pnetdev, os_qid);
++		busy = _TRUE;
++	}
++#else
++	if (rtw_os_need_stop_queue(adapter, 0)) {
++		if (DBG_DUMP_OS_QUEUE_CTL)
++			RTW_INFO(FUNC_ADPT_FMT": netif_stop_queue\n", FUNC_ADPT_ARG(adapter));
++		rtw_netif_stop_queue(adapter->pnetdev);
++		busy = _TRUE;
++	}
++#endif
++	return busy;
++}
++
++void rtw_os_wake_queue_at_free_stainfo(_adapter *padapter, int *qcnt_freed)
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	int i;
++
++	for (i = 0; i < 4; i++) {
++		if (qcnt_freed[i] == 0)
++			continue;
++
++		if (rtw_os_need_wake_queue(padapter, i)) {
++			if (DBG_DUMP_OS_QUEUE_CTL)
++				RTW_INFO(FUNC_ADPT_FMT": netif_wake_subqueue[%d]\n", FUNC_ADPT_ARG(padapter), i);
++			netif_wake_subqueue(padapter->pnetdev, i);
++		}
++	}
++#else
++	if (qcnt_freed[0] || qcnt_freed[1] || qcnt_freed[2] || qcnt_freed[3]) {
++		if (rtw_os_need_wake_queue(padapter, 0)) {
++			if (DBG_DUMP_OS_QUEUE_CTL)
++				RTW_INFO(FUNC_ADPT_FMT": netif_wake_queue\n", FUNC_ADPT_ARG(padapter));
++			netif_wake_queue(padapter->pnetdev);
++		}
++	}
++#endif
++}
++
++int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX	
++	struct sk_buff *skb = pkt;
++	struct sk_buff *segs, *nskb;
++	netdev_features_t features = padapter->pnetdev->features;
++#endif
++	u16 os_qid = 0;
++	s32 res = 0;
++
++	if (padapter->registrypriv.mp_mode) {
++		RTW_INFO("MP_TX_DROP_OS_FRAME\n");
++		goto drop_packet;
++	}
++	DBG_COUNTER(padapter->tx_logs.os_tx);
++
++	if (rtw_if_up(padapter) == _FALSE) {
++		DBG_COUNTER(padapter->tx_logs.os_tx_err_up);
++		#ifdef DBG_TX_DROP_FRAME
++		RTW_INFO("DBG_TX_DROP_FRAME %s if_up fail\n", __FUNCTION__);
++		#endif
++		goto drop_packet;
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	os_qid = skb_get_queue_mapping(pkt);
++#endif
++
++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
++	if (skb_shinfo(skb)->gso_size) {
++	/*	split a big(65k) skb into several small(1.5k) skbs */
++		features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
++		segs = skb_gso_segment(skb, features);
++		if (IS_ERR(segs) || !segs)
++			goto drop_packet;
++
++		do {
++			nskb = segs;
++			segs = segs->next;
++			nskb->next = NULL;
++			rtw_mstat_update( MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, nskb->truesize);
++			res = rtw_xmit(padapter, &nskb, os_qid);
++			if (res < 0) {
++				#ifdef DBG_TX_DROP_FRAME
++				RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__);
++				#endif
++				pxmitpriv->tx_drop++;
++				rtw_os_pkt_complete(padapter, nskb);
++			}
++		} while (segs);
++		rtw_os_pkt_complete(padapter, skb);
++		goto exit;
++	}
++#endif
++
++	res = rtw_xmit(padapter, &pkt, os_qid);
++	if (res < 0) {
++		#ifdef DBG_TX_DROP_FRAME
++		RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__);
++		#endif
++		goto drop_packet;
++	}
++
++	goto exit;
++
++drop_packet:
++	pxmitpriv->tx_drop++;
++	rtw_os_pkt_complete(padapter, pkt);
++
++exit:
++
++
++	return 0;
++}
++
++#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
++int check_alibaba_meshpkt(struct sk_buff *skb)
++{
++	u16 protocol;
++
++	if (skb)
++		return (htons(skb->protocol) == ETH_P_ALL);
++
++	return _FALSE;
++}
++
++s32 rtw_alibaba_mesh_xmit_entry(_pkt *pkt, struct net_device *ndev)
++{
++	u16 frame_ctl;
++	
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
++	struct pkt_file pktfile;
++	struct rtw_ieee80211_hdr *pwlanhdr;
++	struct pkt_attrib		*pattrib;
++	struct xmit_frame		*pmgntframe;
++	struct mlme_ext_priv    *pmlmeext = &(padapter->mlmeextpriv);
++	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
++	unsigned char   *pframe;
++	struct sk_buff *skb =  (struct sk_buff *)pkt;
++	int len = skb->len;
++	
++	rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize);
++	
++	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
++	if (pmgntframe == NULL) {
++		goto fail;
++		return -1;
++	}
++	
++	pattrib = &pmgntframe->attrib;
++	update_mgntframe_attrib(padapter, pattrib);
++	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
++	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
++	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
++
++	_rtw_open_pktfile(pkt, &pktfile);
++	_rtw_pktfile_read(&pktfile, pframe, len);
++
++	pattrib->type = pframe[0] & 0x0C;
++	pattrib->subtype = pframe[0] & 0xF0;
++	pattrib->raid =  rtw_get_mgntframe_raid(padapter, WIRELESS_11G);
++	pattrib->rate = MGN_24M;
++	pattrib->pktlen = len;
++	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
++	pmlmeext->mgnt_seq++;
++
++	RTW_DBG_DUMP("rtw_alibaba_mesh_xmit_entry payload:", skb->data, len);
++
++	pattrib->last_txcmdsz = pattrib->pktlen;
++	dump_mgntframe(padapter, pmgntframe);
++
++fail:
++	rtw_skb_free(skb);
++	return 0;
++}
++#endif
++
++int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev)
++{
++	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
++	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
++	int ret = 0;
++
++	if (pkt) {
++#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
++		if (check_alibaba_meshpkt(pkt)) {
++			return rtw_alibaba_mesh_xmit_entry(pkt, pnetdev);
++		}
++#endif
++		if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
++			rtw_monitor_xmit_entry((struct sk_buff *)pkt, pnetdev);
++#endif
++		}
++		else {
++			rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, pkt->truesize);
++			ret = _rtw_xmit_entry(pkt, pnetdev);
++		}
++
++	}
++
++	return ret;
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/osdep_service.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/osdep_service.c
+new file mode 100644
+index 000000000..233efcb65
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/os_dep/osdep_service.c
+@@ -0,0 +1,3220 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++
++#define _OSDEP_SERVICE_C_
++
++#include <drv_types.h>
++
++#define RT_TAG	'1178'
++
++#ifdef DBG_MEMORY_LEAK
++#ifdef PLATFORM_LINUX
++atomic_t _malloc_cnt = ATOMIC_INIT(0);
++atomic_t _malloc_size = ATOMIC_INIT(0);
++#endif
++#endif /* DBG_MEMORY_LEAK */
++
++
++#if defined(PLATFORM_LINUX)
++/*
++* Translate the OS dependent @param error_code to OS independent RTW_STATUS_CODE
++* @return: one of RTW_STATUS_CODE
++*/
++inline int RTW_STATUS_CODE(int error_code)
++{
++	if (error_code >= 0)
++		return _SUCCESS;
++
++	switch (error_code) {
++	/* case -ETIMEDOUT: */
++	/*	return RTW_STATUS_TIMEDOUT; */
++	default:
++		return _FAIL;
++	}
++}
++#else
++inline int RTW_STATUS_CODE(int error_code)
++{
++	return error_code;
++}
++#endif
++
++u32 rtw_atoi(u8 *s)
++{
++
++	int num = 0, flag = 0;
++	int i;
++	for (i = 0; i <= strlen(s); i++) {
++		if (s[i] >= '0' && s[i] <= '9')
++			num = num * 10 + s[i] - '0';
++		else if (s[0] == '-' && i == 0)
++			flag = 1;
++		else
++			break;
++	}
++
++	if (flag == 1)
++		num = num * -1;
++
++	return num;
++
++}
++
++inline void *_rtw_vmalloc(u32 sz)
++{
++	void *pbuf;
++#ifdef PLATFORM_LINUX
++	pbuf = vmalloc(sz);
++#endif
++#ifdef PLATFORM_FREEBSD
++	pbuf = malloc(sz, M_DEVBUF, M_NOWAIT);
++#endif
++
++#ifdef PLATFORM_WINDOWS
++	NdisAllocateMemoryWithTag(&pbuf, sz, RT_TAG);
++#endif
++
++#ifdef DBG_MEMORY_LEAK
++#ifdef PLATFORM_LINUX
++	if (pbuf != NULL) {
++		atomic_inc(&_malloc_cnt);
++		atomic_add(sz, &_malloc_size);
++	}
++#endif
++#endif /* DBG_MEMORY_LEAK */
++
++	return pbuf;
++}
++
++inline void *_rtw_zvmalloc(u32 sz)
++{
++	void *pbuf;
++#ifdef PLATFORM_LINUX
++	pbuf = _rtw_vmalloc(sz);
++	if (pbuf != NULL)
++		memset(pbuf, 0, sz);
++#endif
++#ifdef PLATFORM_FREEBSD
++	pbuf = malloc(sz, M_DEVBUF, M_ZERO | M_NOWAIT);
++#endif
++#ifdef PLATFORM_WINDOWS
++	NdisAllocateMemoryWithTag(&pbuf, sz, RT_TAG);
++	if (pbuf != NULL)
++		NdisFillMemory(pbuf, sz, 0);
++#endif
++
++	return pbuf;
++}
++
++inline void _rtw_vmfree(void *pbuf, u32 sz)
++{
++#ifdef PLATFORM_LINUX
++	vfree(pbuf);
++#endif
++#ifdef PLATFORM_FREEBSD
++	free(pbuf, M_DEVBUF);
++#endif
++#ifdef PLATFORM_WINDOWS
++	NdisFreeMemory(pbuf, sz, 0);
++#endif
++
++#ifdef DBG_MEMORY_LEAK
++#ifdef PLATFORM_LINUX
++	atomic_dec(&_malloc_cnt);
++	atomic_sub(sz, &_malloc_size);
++#endif
++#endif /* DBG_MEMORY_LEAK */
++}
++
++void *_rtw_malloc(u32 sz)
++{
++	void *pbuf = NULL;
++
++#ifdef PLATFORM_LINUX
++#ifdef RTK_DMP_PLATFORM
++	if (sz > 0x4000)
++		pbuf = dvr_malloc(sz);
++	else
++#endif
++		pbuf = kmalloc(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++	pbuf = malloc(sz, M_DEVBUF, M_NOWAIT);
++#endif
++#ifdef PLATFORM_WINDOWS
++
++	NdisAllocateMemoryWithTag(&pbuf, sz, RT_TAG);
++
++#endif
++
++#ifdef DBG_MEMORY_LEAK
++#ifdef PLATFORM_LINUX
++	if (pbuf != NULL) {
++		atomic_inc(&_malloc_cnt);
++		atomic_add(sz, &_malloc_size);
++	}
++#endif
++#endif /* DBG_MEMORY_LEAK */
++
++	return pbuf;
++
++}
++
++
++void *_rtw_zmalloc(u32 sz)
++{
++#ifdef PLATFORM_FREEBSD
++	return malloc(sz, M_DEVBUF, M_ZERO | M_NOWAIT);
++#else /* PLATFORM_FREEBSD */
++	void *pbuf = _rtw_malloc(sz);
++
++	if (pbuf != NULL) {
++
++#ifdef PLATFORM_LINUX
++		memset(pbuf, 0, sz);
++#endif
++
++#ifdef PLATFORM_WINDOWS
++		NdisFillMemory(pbuf, sz, 0);
++#endif
++
++	}
++
++	return pbuf;
++#endif /* PLATFORM_FREEBSD */
++}
++
++void _rtw_mfree(void *pbuf, u32 sz)
++{
++
++#ifdef PLATFORM_LINUX
++#ifdef RTK_DMP_PLATFORM
++	if (sz > 0x4000)
++		dvr_free(pbuf);
++	else
++#endif
++		kfree(pbuf);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++	free(pbuf, M_DEVBUF);
++#endif
++#ifdef PLATFORM_WINDOWS
++
++	NdisFreeMemory(pbuf, sz, 0);
++
++#endif
++
++#ifdef DBG_MEMORY_LEAK
++#ifdef PLATFORM_LINUX
++	atomic_dec(&_malloc_cnt);
++	atomic_sub(sz, &_malloc_size);
++#endif
++#endif /* DBG_MEMORY_LEAK */
++
++}
++
++#ifdef PLATFORM_FREEBSD
++/* review again */
++struct sk_buff *dev_alloc_skb(unsigned int size)
++{
++	struct sk_buff *skb = NULL;
++	u8 *data = NULL;
++
++	/* skb = _rtw_zmalloc(sizeof(struct sk_buff)); */ /* for skb->len, etc. */
++	skb = _rtw_malloc(sizeof(struct sk_buff));
++	if (!skb)
++		goto out;
++	data = _rtw_malloc(size);
++	if (!data)
++		goto nodata;
++
++	skb->head = (unsigned char *)data;
++	skb->data = (unsigned char *)data;
++	skb->tail = (unsigned char *)data;
++	skb->end = (unsigned char *)data + size;
++	skb->len = 0;
++	/* printf("%s()-%d: skb=%p, skb->head = %p\n", __FUNCTION__, __LINE__, skb, skb->head); */
++
++out:
++	return skb;
++nodata:
++	_rtw_mfree(skb, sizeof(struct sk_buff));
++	skb = NULL;
++	goto out;
++
++}
++
++void dev_kfree_skb_any(struct sk_buff *skb)
++{
++	/* printf("%s()-%d: skb->head = %p\n", __FUNCTION__, __LINE__, skb->head); */
++	if (skb->head)
++		_rtw_mfree(skb->head, 0);
++	/* printf("%s()-%d: skb = %p\n", __FUNCTION__, __LINE__, skb); */
++	if (skb)
++		_rtw_mfree(skb, 0);
++}
++struct sk_buff *skb_clone(const struct sk_buff *skb)
++{
++	return NULL;
++}
++
++#endif /* PLATFORM_FREEBSD */
++
++inline struct sk_buff *_rtw_skb_alloc(u32 sz)
++{
++#ifdef PLATFORM_LINUX
++	return __dev_alloc_skb(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
++#endif /* PLATFORM_LINUX */
++
++#ifdef PLATFORM_FREEBSD
++	return dev_alloc_skb(sz);
++#endif /* PLATFORM_FREEBSD */
++}
++
++inline void _rtw_skb_free(struct sk_buff *skb)
++{
++	dev_kfree_skb_any(skb);
++}
++
++inline struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb)
++{
++#ifdef PLATFORM_LINUX
++	return skb_copy(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
++#endif /* PLATFORM_LINUX */
++
++#ifdef PLATFORM_FREEBSD
++	return NULL;
++#endif /* PLATFORM_FREEBSD */
++}
++
++inline struct sk_buff *_rtw_skb_clone(struct sk_buff *skb)
++{
++#ifdef PLATFORM_LINUX
++	return skb_clone(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
++#endif /* PLATFORM_LINUX */
++
++#ifdef PLATFORM_FREEBSD
++	return skb_clone(skb);
++#endif /* PLATFORM_FREEBSD */
++}
++inline struct sk_buff *_rtw_pskb_copy(struct sk_buff *skb)
++{
++#ifdef PLATFORM_LINUX
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))
++	return pskb_copy(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
++#else
++	return skb_clone(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
++#endif
++#endif /* PLATFORM_LINUX */
++
++#ifdef PLATFORM_FREEBSD
++	return NULL;
++#endif /* PLATFORM_FREEBSD */
++}
++
++inline int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb)
++{
++#if defined(PLATFORM_LINUX)
++	skb->dev = ndev;
++	return netif_rx(skb);
++#elif defined(PLATFORM_FREEBSD)
++	return (*ndev->if_input)(ndev, skb);
++#else
++	rtw_warn_on(1);
++	return -1;
++#endif
++}
++
++#ifdef CONFIG_RTW_NAPI
++inline int _rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb)
++{
++#if defined(PLATFORM_LINUX)
++	skb->dev = ndev;
++	return netif_receive_skb(skb);
++#else
++	rtw_warn_on(1);
++	return -1;
++#endif
++}
++
++#ifdef CONFIG_RTW_GRO
++inline gro_result_t _rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb)
++{
++#if defined(PLATFORM_LINUX)
++	return napi_gro_receive(napi, skb);
++#else
++	rtw_warn_on(1);
++	return -1;
++#endif
++}
++#endif /* CONFIG_RTW_GRO */
++#endif /* CONFIG_RTW_NAPI */
++
++void _rtw_skb_queue_purge(struct sk_buff_head *list)
++{
++	struct sk_buff *skb;
++
++	while ((skb = skb_dequeue(list)) != NULL)
++		_rtw_skb_free(skb);
++}
++
++#ifdef CONFIG_USB_HCI
++inline void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma)
++{
++#ifdef PLATFORM_LINUX
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	return usb_alloc_coherent(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma);
++#else
++	return usb_buffer_alloc(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma);
++#endif
++#endif /* PLATFORM_LINUX */
++
++#ifdef PLATFORM_FREEBSD
++	return malloc(size, M_USBDEV, M_NOWAIT | M_ZERO);
++#endif /* PLATFORM_FREEBSD */
++}
++inline void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma)
++{
++#ifdef PLATFORM_LINUX
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	usb_free_coherent(dev, size, addr, dma);
++#else
++	usb_buffer_free(dev, size, addr, dma);
++#endif
++#endif /* PLATFORM_LINUX */
++
++#ifdef PLATFORM_FREEBSD
++	free(addr, M_USBDEV);
++#endif /* PLATFORM_FREEBSD */
++}
++#endif /* CONFIG_USB_HCI */
++
++#if defined(DBG_MEM_ALLOC)
++
++struct rtw_mem_stat {
++	ATOMIC_T alloc; /* the memory bytes we allocate currently */
++	ATOMIC_T peak; /* the peak memory bytes we allocate */
++	ATOMIC_T alloc_cnt; /* the alloc count for alloc currently */
++	ATOMIC_T alloc_err_cnt; /* the error times we fail to allocate memory */
++};
++
++struct rtw_mem_stat rtw_mem_type_stat[mstat_tf_idx(MSTAT_TYPE_MAX)];
++#ifdef RTW_MEM_FUNC_STAT
++struct rtw_mem_stat rtw_mem_func_stat[mstat_ff_idx(MSTAT_FUNC_MAX)];
++#endif
++
++char *MSTAT_TYPE_str[] = {
++	"VIR",
++	"PHY",
++	"SKB",
++	"USB",
++};
++
++#ifdef RTW_MEM_FUNC_STAT
++char *MSTAT_FUNC_str[] = {
++	"UNSP",
++	"IO",
++	"TXIO",
++	"RXIO",
++	"TX",
++	"RX",
++};
++#endif
++
++void rtw_mstat_dump(void *sel)
++{
++	int i;
++	int value_t[4][mstat_tf_idx(MSTAT_TYPE_MAX)];
++#ifdef RTW_MEM_FUNC_STAT
++	int value_f[4][mstat_ff_idx(MSTAT_FUNC_MAX)];
++#endif
++
++	for (i = 0; i < mstat_tf_idx(MSTAT_TYPE_MAX); i++) {
++		value_t[0][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc));
++		value_t[1][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].peak));
++		value_t[2][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc_cnt));
++		value_t[3][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc_err_cnt));
++	}
++
++#ifdef RTW_MEM_FUNC_STAT
++	for (i = 0; i < mstat_ff_idx(MSTAT_FUNC_MAX); i++) {
++		value_f[0][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc));
++		value_f[1][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].peak));
++		value_f[2][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc_cnt));
++		value_f[3][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc_err_cnt));
++	}
++#endif
++
++	RTW_PRINT_SEL(sel, "===================== MSTAT =====================\n");
++	RTW_PRINT_SEL(sel, "%4s %10s %10s %10s %10s\n", "TAG", "alloc", "peak", "aloc_cnt", "err_cnt");
++	RTW_PRINT_SEL(sel, "-------------------------------------------------\n");
++	for (i = 0; i < mstat_tf_idx(MSTAT_TYPE_MAX); i++)
++		RTW_PRINT_SEL(sel, "%4s %10d %10d %10d %10d\n", MSTAT_TYPE_str[i], value_t[0][i], value_t[1][i], value_t[2][i], value_t[3][i]);
++#ifdef RTW_MEM_FUNC_STAT
++	RTW_PRINT_SEL(sel, "-------------------------------------------------\n");
++	for (i = 0; i < mstat_ff_idx(MSTAT_FUNC_MAX); i++)
++		RTW_PRINT_SEL(sel, "%4s %10d %10d %10d %10d\n", MSTAT_FUNC_str[i], value_f[0][i], value_f[1][i], value_f[2][i], value_f[3][i]);
++#endif
++}
++
++void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz)
++{
++	static systime update_time = 0;
++	int peak, alloc;
++	int i;
++
++	/* initialization */
++	if (!update_time) {
++		for (i = 0; i < mstat_tf_idx(MSTAT_TYPE_MAX); i++) {
++			ATOMIC_SET(&(rtw_mem_type_stat[i].alloc), 0);
++			ATOMIC_SET(&(rtw_mem_type_stat[i].peak), 0);
++			ATOMIC_SET(&(rtw_mem_type_stat[i].alloc_cnt), 0);
++			ATOMIC_SET(&(rtw_mem_type_stat[i].alloc_err_cnt), 0);
++		}
++		#ifdef RTW_MEM_FUNC_STAT
++		for (i = 0; i < mstat_ff_idx(MSTAT_FUNC_MAX); i++) {
++			ATOMIC_SET(&(rtw_mem_func_stat[i].alloc), 0);
++			ATOMIC_SET(&(rtw_mem_func_stat[i].peak), 0);
++			ATOMIC_SET(&(rtw_mem_func_stat[i].alloc_cnt), 0);
++			ATOMIC_SET(&(rtw_mem_func_stat[i].alloc_err_cnt), 0);
++		}
++		#endif
++	}
++
++	switch (status) {
++	case MSTAT_ALLOC_SUCCESS:
++		ATOMIC_INC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_cnt));
++		alloc = ATOMIC_ADD_RETURN(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc), sz);
++		peak = ATOMIC_READ(&(rtw_mem_type_stat[mstat_tf_idx(flags)].peak));
++		if (peak < alloc)
++			ATOMIC_SET(&(rtw_mem_type_stat[mstat_tf_idx(flags)].peak), alloc);
++
++		#ifdef RTW_MEM_FUNC_STAT
++		ATOMIC_INC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_cnt));
++		alloc = ATOMIC_ADD_RETURN(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc), sz);
++		peak = ATOMIC_READ(&(rtw_mem_func_stat[mstat_ff_idx(flags)].peak));
++		if (peak < alloc)
++			ATOMIC_SET(&(rtw_mem_func_stat[mstat_ff_idx(flags)].peak), alloc);
++		#endif
++		break;
++
++	case MSTAT_ALLOC_FAIL:
++		ATOMIC_INC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_err_cnt));
++		#ifdef RTW_MEM_FUNC_STAT
++		ATOMIC_INC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_err_cnt));
++		#endif
++		break;
++
++	case MSTAT_FREE:
++		ATOMIC_DEC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_cnt));
++		ATOMIC_SUB(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc), sz);
++		#ifdef RTW_MEM_FUNC_STAT
++		ATOMIC_DEC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_cnt));
++		ATOMIC_SUB(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc), sz);
++		#endif
++		break;
++	};
++
++	/* if (rtw_get_passing_time_ms(update_time) > 5000) { */
++	/*	rtw_mstat_dump(RTW_DBGDUMP); */
++	update_time = rtw_get_current_time();
++	/* } */
++}
++
++#ifndef SIZE_MAX
++	#define SIZE_MAX (~(size_t)0)
++#endif
++
++struct mstat_sniff_rule {
++	enum mstat_f flags;
++	size_t lb;
++	size_t hb;
++};
++
++struct mstat_sniff_rule mstat_sniff_rules[] = {
++	{MSTAT_TYPE_PHY, 4097, SIZE_MAX},
++};
++
++int mstat_sniff_rule_num = sizeof(mstat_sniff_rules) / sizeof(struct mstat_sniff_rule);
++
++bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size)
++{
++	int i;
++	for (i = 0; i < mstat_sniff_rule_num; i++) {
++		if (mstat_sniff_rules[i].flags == flags
++			&& mstat_sniff_rules[i].lb <= size
++			&& mstat_sniff_rules[i].hb >= size)
++			return _TRUE;
++	}
++
++	return _FALSE;
++}
++
++inline void *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
++{
++	void *p;
++
++	if (match_mstat_sniff_rules(flags, sz))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
++
++	p = _rtw_vmalloc((sz));
++
++	rtw_mstat_update(
++		flags
++		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++		, sz
++	);
++
++	return p;
++}
++
++inline void *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
++{
++	void *p;
++
++	if (match_mstat_sniff_rules(flags, sz))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
++
++	p = _rtw_zvmalloc((sz));
++
++	rtw_mstat_update(
++		flags
++		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++		, sz
++	);
++
++	return p;
++}
++
++inline void dbg_rtw_vmfree(void *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line)
++{
++
++	if (match_mstat_sniff_rules(flags, sz))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
++
++	_rtw_vmfree((pbuf), (sz));
++
++	rtw_mstat_update(
++		flags
++		, MSTAT_FREE
++		, sz
++	);
++}
++
++inline void *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
++{
++	void *p;
++
++	if (match_mstat_sniff_rules(flags, sz))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
++
++	p = _rtw_malloc((sz));
++
++	rtw_mstat_update(
++		flags
++		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++		, sz
++	);
++
++	return p;
++}
++
++inline void *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
++{
++	void *p;
++
++	if (match_mstat_sniff_rules(flags, sz))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
++
++	p = _rtw_zmalloc((sz));
++
++	rtw_mstat_update(
++		flags
++		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++		, sz
++	);
++
++	return p;
++}
++
++inline void dbg_rtw_mfree(void *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line)
++{
++	if (match_mstat_sniff_rules(flags, sz))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
++
++	_rtw_mfree((pbuf), (sz));
++
++	rtw_mstat_update(
++		flags
++		, MSTAT_FREE
++		, sz
++	);
++}
++
++inline struct sk_buff *dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, int line)
++{
++	struct sk_buff *skb;
++	unsigned int truesize = 0;
++
++	skb = _rtw_skb_alloc(size);
++
++	if (skb)
++		truesize = skb->truesize;
++
++	if (!skb || truesize < size || match_mstat_sniff_rules(flags, truesize))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\n", func, line, __FUNCTION__, size, skb, truesize);
++
++	rtw_mstat_update(
++		flags
++		, skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++		, truesize
++	);
++
++	return skb;
++}
++
++inline void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
++{
++	unsigned int truesize = skb->truesize;
++
++	if (match_mstat_sniff_rules(flags, truesize))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
++
++	_rtw_skb_free(skb);
++
++	rtw_mstat_update(
++		flags
++		, MSTAT_FREE
++		, truesize
++	);
++}
++
++inline struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line)
++{
++	struct sk_buff *skb_cp;
++	unsigned int truesize = skb->truesize;
++	unsigned int cp_truesize = 0;
++
++	skb_cp = _rtw_skb_copy(skb);
++	if (skb_cp)
++		cp_truesize = skb_cp->truesize;
++
++	if (!skb_cp || cp_truesize < truesize || match_mstat_sniff_rules(flags, cp_truesize))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u), skb_cp:%p, cp_truesize=%u\n", func, line, __FUNCTION__, truesize, skb_cp, cp_truesize);
++
++	rtw_mstat_update(
++		flags
++		, skb_cp ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++		, cp_truesize
++	);
++
++	return skb_cp;
++}
++
++inline struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line)
++{
++	struct sk_buff *skb_cl;
++	unsigned int truesize = skb->truesize;
++	unsigned int cl_truesize = 0;
++
++	skb_cl = _rtw_skb_clone(skb);
++	if (skb_cl)
++		cl_truesize = skb_cl->truesize;
++
++	if (!skb_cl || cl_truesize < truesize || match_mstat_sniff_rules(flags, cl_truesize))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u), skb_cl:%p, cl_truesize=%u\n", func, line, __FUNCTION__, truesize, skb_cl, cl_truesize);
++
++	rtw_mstat_update(
++		flags
++		, skb_cl ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++		, cl_truesize
++	);
++
++	return skb_cl;
++}
++
++inline int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
++{
++	int ret;
++	unsigned int truesize = skb->truesize;
++
++	if (match_mstat_sniff_rules(flags, truesize))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
++
++	ret = _rtw_netif_rx(ndev, skb);
++
++	rtw_mstat_update(
++		flags
++		, MSTAT_FREE
++		, truesize
++	);
++
++	return ret;
++}
++
++#ifdef CONFIG_RTW_NAPI
++inline int dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
++{
++	int ret;
++	unsigned int truesize = skb->truesize;
++
++	if (match_mstat_sniff_rules(flags, truesize))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
++
++	ret = _rtw_netif_receive_skb(ndev, skb);
++
++	rtw_mstat_update(
++		flags
++		, MSTAT_FREE
++		, truesize
++	);
++
++	return ret;
++}
++
++#ifdef CONFIG_RTW_GRO
++inline gro_result_t dbg_rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
++{
++	int ret;
++	unsigned int truesize = skb->truesize;
++
++	if (match_mstat_sniff_rules(flags, truesize))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
++
++	ret = _rtw_napi_gro_receive(napi, skb);
++
++	rtw_mstat_update(
++		flags
++		, MSTAT_FREE
++		, truesize
++	);
++
++	return ret;
++}
++#endif /* CONFIG_RTW_GRO */
++#endif /* CONFIG_RTW_NAPI */
++
++inline void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line)
++{
++	struct sk_buff *skb;
++
++	while ((skb = skb_dequeue(list)) != NULL)
++		dbg_rtw_skb_free(skb, flags, func, line);
++}
++
++#ifdef CONFIG_USB_HCI
++inline void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, int line)
++{
++	void *p;
++
++	if (match_mstat_sniff_rules(flags, size))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%zu)\n", func, line, __FUNCTION__, size);
++
++	p = _rtw_usb_buffer_alloc(dev, size, dma);
++
++	rtw_mstat_update(
++		flags
++		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
++		, size
++	);
++
++	return p;
++}
++
++inline void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, int line)
++{
++
++	if (match_mstat_sniff_rules(flags, size))
++		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%zu)\n", func, line, __FUNCTION__, size);
++
++	_rtw_usb_buffer_free(dev, size, addr, dma);
++
++	rtw_mstat_update(
++		flags
++		, MSTAT_FREE
++		, size
++	);
++}
++#endif /* CONFIG_USB_HCI */
++
++#endif /* defined(DBG_MEM_ALLOC) */
++
++void *rtw_malloc2d(int h, int w, size_t size)
++{
++	int j;
++
++	void **a = (void **) rtw_zmalloc(h * sizeof(void *) + h * w * size);
++	if (a == NULL) {
++		RTW_INFO("%s: alloc memory fail!\n", __FUNCTION__);
++		return NULL;
++	}
++
++	for (j = 0; j < h; j++)
++		a[j] = ((char *)(a + h)) + j * w * size;
++
++	return a;
++}
++
++void rtw_mfree2d(void *pbuf, int h, int w, int size)
++{
++	rtw_mfree((u8 *)pbuf, h * sizeof(void *) + w * h * size);
++}
++
++inline void rtw_os_pkt_free(_pkt *pkt)
++{
++#if defined(PLATFORM_LINUX)
++	rtw_skb_free(pkt);
++#elif defined(PLATFORM_FREEBSD)
++	m_freem(pkt);
++#else
++	#error "TBD\n"
++#endif
++}
++
++inline _pkt *rtw_os_pkt_copy(_pkt *pkt)
++{
++#if defined(PLATFORM_LINUX)
++	return rtw_skb_copy(pkt);
++#elif defined(PLATFORM_FREEBSD)
++	return m_dup(pkt, M_NOWAIT);
++#else
++	#error "TBD\n"
++#endif
++}
++
++inline void *rtw_os_pkt_data(_pkt *pkt)
++{
++#if defined(PLATFORM_LINUX)
++	return pkt->data;
++#elif defined(PLATFORM_FREEBSD)
++	return pkt->m_data;
++#else
++	#error "TBD\n"
++#endif
++}
++
++inline u32 rtw_os_pkt_len(_pkt *pkt)
++{
++#if defined(PLATFORM_LINUX)
++	return pkt->len;
++#elif defined(PLATFORM_FREEBSD)
++	return pkt->m_pkthdr.len;
++#else
++	#error "TBD\n"
++#endif
++}
++
++void _rtw_memcpy(void *dst, const void *src, u32 sz)
++{
++
++#if defined(PLATFORM_LINUX) || defined (PLATFORM_FREEBSD)
++
++	memcpy(dst, src, sz);
++
++#endif
++
++#ifdef PLATFORM_WINDOWS
++
++	NdisMoveMemory(dst, src, sz);
++
++#endif
++
++}
++
++inline void _rtw_memmove(void *dst, const void *src, u32 sz)
++{
++#if defined(PLATFORM_LINUX)
++	memmove(dst, src, sz);
++#else
++	#error "TBD\n"
++#endif
++}
++
++int	_rtw_memcmp(const void *dst, const void *src, u32 sz)
++{
++
++#if defined(PLATFORM_LINUX) || defined (PLATFORM_FREEBSD)
++	/* under Linux/GNU/GLibc, the return value of memcmp for two same mem. chunk is 0 */
++
++	if (!(memcmp(dst, src, sz)))
++		return _TRUE;
++	else
++		return _FALSE;
++#endif
++
++
++#ifdef PLATFORM_WINDOWS
++	/* under Windows, the return value of NdisEqualMemory for two same mem. chunk is 1 */
++
++	if (NdisEqualMemory(dst, src, sz))
++		return _TRUE;
++	else
++		return _FALSE;
++
++#endif
++
++
++
++}
++
++int _rtw_memcmp2(const void *dst, const void *src, u32 sz)
++{
++	const unsigned char *p1 = dst, *p2 = src;
++
++	if (sz == 0)
++		return 0;
++
++	while (*p1 == *p2) {
++		p1++;
++		p2++;
++		sz--;
++		if (sz == 0)
++			return 0;
++	}
++
++	return *p1 - *p2;
++}
++
++void _rtw_memset(void *pbuf, int c, u32 sz)
++{
++
++#if defined(PLATFORM_LINUX) || defined (PLATFORM_FREEBSD)
++
++	memset(pbuf, c, sz);
++
++#endif
++
++#ifdef PLATFORM_WINDOWS
++#if 0
++	NdisZeroMemory(pbuf, sz);
++	if (c != 0)
++		memset(pbuf, c, sz);
++#else
++	NdisFillMemory(pbuf, sz, c);
++#endif
++#endif
++
++}
++
++#ifdef PLATFORM_FREEBSD
++static inline void __list_add(_list *pnew, _list *pprev, _list *pnext)
++{
++	pnext->prev = pnew;
++	pnew->next = pnext;
++	pnew->prev = pprev;
++	pprev->next = pnew;
++}
++#endif /* PLATFORM_FREEBSD */
++
++
++void _rtw_init_listhead(_list *list)
++{
++
++#ifdef PLATFORM_LINUX
++
++	INIT_LIST_HEAD(list);
++
++#endif
++
++#ifdef PLATFORM_FREEBSD
++	list->next = list;
++	list->prev = list;
++#endif
++#ifdef PLATFORM_WINDOWS
++
++	NdisInitializeListHead(list);
++
++#endif
++
++}
++
++
++/*
++For the following list_xxx operations,
++caller must guarantee the atomic context.
++Otherwise, there will be racing condition.
++*/
++u32	rtw_is_list_empty(_list *phead)
++{
++
++#ifdef PLATFORM_LINUX
++
++	if (list_empty(phead))
++		return _TRUE;
++	else
++		return _FALSE;
++
++#endif
++#ifdef PLATFORM_FREEBSD
++
++	if (phead->next == phead)
++		return _TRUE;
++	else
++		return _FALSE;
++
++#endif
++
++
++#ifdef PLATFORM_WINDOWS
++
++	if (IsListEmpty(phead))
++		return _TRUE;
++	else
++		return _FALSE;
++
++#endif
++
++
++}
++
++void rtw_list_insert_head(_list *plist, _list *phead)
++{
++
++#ifdef PLATFORM_LINUX
++	list_add(plist, phead);
++#endif
++
++#ifdef PLATFORM_FREEBSD
++	__list_add(plist, phead, phead->next);
++#endif
++
++#ifdef PLATFORM_WINDOWS
++	InsertHeadList(phead, plist);
++#endif
++}
++
++void rtw_list_insert_tail(_list *plist, _list *phead)
++{
++
++#ifdef PLATFORM_LINUX
++
++	list_add_tail(plist, phead);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++
++	__list_add(plist, phead->prev, phead);
++
++#endif
++#ifdef PLATFORM_WINDOWS
++
++	InsertTailList(phead, plist);
++
++#endif
++
++}
++
++inline void rtw_list_splice(_list *list, _list *head)
++{
++#ifdef PLATFORM_LINUX
++	list_splice(list, head);
++#else
++	#error "TBD\n"
++#endif
++}
++
++inline void rtw_list_splice_init(_list *list, _list *head)
++{
++#ifdef PLATFORM_LINUX
++	list_splice_init(list, head);
++#else
++	#error "TBD\n"
++#endif
++}
++
++inline void rtw_list_splice_tail(_list *list, _list *head)
++{
++#ifdef PLATFORM_LINUX
++	#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27))
++	if (!list_empty(list))
++		__list_splice(list, head);
++	#else
++	list_splice_tail(list, head);
++	#endif
++#else
++	#error "TBD\n"
++#endif
++}
++
++inline void rtw_hlist_head_init(rtw_hlist_head *h)
++{
++#ifdef PLATFORM_LINUX
++	INIT_HLIST_HEAD(h);
++#else
++	#error "TBD\n"
++#endif
++}
++
++inline void rtw_hlist_add_head(rtw_hlist_node *n, rtw_hlist_head *h)
++{
++#ifdef PLATFORM_LINUX
++	hlist_add_head(n, h);
++#else
++	#error "TBD\n"
++#endif
++}
++
++inline void rtw_hlist_del(rtw_hlist_node *n)
++{
++#ifdef PLATFORM_LINUX
++	hlist_del(n);
++#else
++	#error "TBD\n"
++#endif
++}
++
++inline void rtw_hlist_add_head_rcu(rtw_hlist_node *n, rtw_hlist_head *h)
++{
++#ifdef PLATFORM_LINUX
++	hlist_add_head_rcu(n, h);
++#else
++	#error "TBD\n"
++#endif
++}
++
++inline void rtw_hlist_del_rcu(rtw_hlist_node *n)
++{
++#ifdef PLATFORM_LINUX
++	hlist_del_rcu(n);
++#else
++	#error "TBD\n"
++#endif
++}
++
++void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx)
++{
++	_adapter *adapter = (_adapter *)padapter;
++
++#ifdef PLATFORM_LINUX
++	_init_timer(ptimer, adapter->pnetdev, pfunc, ctx);
++#endif
++#ifdef PLATFORM_FREEBSD
++	_init_timer(ptimer, adapter->pifp, pfunc, ctx);
++#endif
++#ifdef PLATFORM_WINDOWS
++	_init_timer(ptimer, adapter->hndis_adapter, pfunc, ctx);
++#endif
++}
++
++/*
++
++Caller must check if the list is empty before calling rtw_list_delete
++
++*/
++
++
++void _rtw_init_sema(_sema	*sema, int init_val)
++{
++
++#ifdef PLATFORM_LINUX
++
++	sema_init(sema, init_val);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++	sema_init(sema, init_val, "rtw_drv");
++#endif
++#ifdef PLATFORM_OS_XP
++
++	KeInitializeSemaphore(sema, init_val,  SEMA_UPBND); /* count=0; */
++
++#endif
++
++#ifdef PLATFORM_OS_CE
++	if (*sema == NULL)
++		*sema = CreateSemaphore(NULL, init_val, SEMA_UPBND, NULL);
++#endif
++
++}
++
++void _rtw_free_sema(_sema	*sema)
++{
++#ifdef PLATFORM_FREEBSD
++	sema_destroy(sema);
++#endif
++#ifdef PLATFORM_OS_CE
++	CloseHandle(*sema);
++#endif
++
++}
++
++void _rtw_up_sema(_sema	*sema)
++{
++
++#ifdef PLATFORM_LINUX
++
++	up(sema);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++	sema_post(sema);
++#endif
++#ifdef PLATFORM_OS_XP
++
++	KeReleaseSemaphore(sema, IO_NETWORK_INCREMENT, 1,  FALSE);
++
++#endif
++
++#ifdef PLATFORM_OS_CE
++	ReleaseSemaphore(*sema,  1,  NULL);
++#endif
++}
++
++u32 _rtw_down_sema(_sema *sema)
++{
++
++#ifdef PLATFORM_LINUX
++
++	if (down_interruptible(sema))
++		return _FAIL;
++	else
++		return _SUCCESS;
++
++#endif
++#ifdef PLATFORM_FREEBSD
++	sema_wait(sema);
++	return  _SUCCESS;
++#endif
++#ifdef PLATFORM_OS_XP
++
++	if (STATUS_SUCCESS == KeWaitForSingleObject(sema, Executive, KernelMode, TRUE, NULL))
++		return  _SUCCESS;
++	else
++		return _FAIL;
++#endif
++
++#ifdef PLATFORM_OS_CE
++	if (WAIT_OBJECT_0 == WaitForSingleObject(*sema, INFINITE))
++		return _SUCCESS;
++	else
++		return _FAIL;
++#endif
++}
++
++inline void thread_exit(_completion *comp)
++{
++#ifdef PLATFORM_LINUX
++	complete_and_exit(comp, 0);
++#endif
++
++#ifdef PLATFORM_FREEBSD
++	printf("%s", "RTKTHREAD_exit");
++#endif
++
++#ifdef PLATFORM_OS_CE
++	ExitThread(STATUS_SUCCESS);
++#endif
++
++#ifdef PLATFORM_OS_XP
++	PsTerminateSystemThread(STATUS_SUCCESS);
++#endif
++}
++
++inline void _rtw_init_completion(_completion *comp)
++{
++#ifdef PLATFORM_LINUX
++	init_completion(comp);
++#endif
++}
++inline void _rtw_wait_for_comp_timeout(_completion *comp)
++{
++#ifdef PLATFORM_LINUX
++	wait_for_completion_timeout(comp, msecs_to_jiffies(3000));
++#endif
++}
++inline void _rtw_wait_for_comp(_completion *comp)
++{
++#ifdef PLATFORM_LINUX
++	wait_for_completion(comp);
++#endif
++}
++
++void	_rtw_mutex_init(_mutex *pmutex)
++{
++#ifdef PLATFORM_LINUX
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
++	mutex_init(pmutex);
++#else
++	init_MUTEX(pmutex);
++#endif
++
++#endif
++#ifdef PLATFORM_FREEBSD
++	mtx_init(pmutex, "", NULL, MTX_DEF | MTX_RECURSE);
++#endif
++#ifdef PLATFORM_OS_XP
++
++	KeInitializeMutex(pmutex, 0);
++
++#endif
++
++#ifdef PLATFORM_OS_CE
++	*pmutex =  CreateMutex(NULL, _FALSE, NULL);
++#endif
++}
++
++void	_rtw_mutex_free(_mutex *pmutex);
++void	_rtw_mutex_free(_mutex *pmutex)
++{
++#ifdef PLATFORM_LINUX
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
++	mutex_destroy(pmutex);
++#else
++#endif
++
++#ifdef PLATFORM_FREEBSD
++	sema_destroy(pmutex);
++#endif
++
++#endif
++
++#ifdef PLATFORM_OS_XP
++
++#endif
++
++#ifdef PLATFORM_OS_CE
++
++#endif
++}
++
++void	_rtw_spinlock_init(_lock *plock)
++{
++
++#ifdef PLATFORM_LINUX
++
++	spin_lock_init(plock);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++	mtx_init(plock, "", NULL, MTX_DEF | MTX_RECURSE);
++#endif
++#ifdef PLATFORM_WINDOWS
++
++	NdisAllocateSpinLock(plock);
++
++#endif
++
++}
++
++void	_rtw_spinlock_free(_lock *plock)
++{
++#ifdef PLATFORM_FREEBSD
++	mtx_destroy(plock);
++#endif
++
++#ifdef PLATFORM_WINDOWS
++
++	NdisFreeSpinLock(plock);
++
++#endif
++
++}
++#ifdef PLATFORM_FREEBSD
++extern PADAPTER prtw_lock;
++
++void rtw_mtx_lock(_lock *plock)
++{
++	if (prtw_lock)
++		mtx_lock(&prtw_lock->glock);
++	else
++		printf("%s prtw_lock==NULL", __FUNCTION__);
++}
++void rtw_mtx_unlock(_lock *plock)
++{
++	if (prtw_lock)
++		mtx_unlock(&prtw_lock->glock);
++	else
++		printf("%s prtw_lock==NULL", __FUNCTION__);
++
++}
++#endif /* PLATFORM_FREEBSD */
++
++
++void	_rtw_spinlock(_lock	*plock)
++{
++
++#ifdef PLATFORM_LINUX
++
++	spin_lock(plock);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++	mtx_lock(plock);
++#endif
++#ifdef PLATFORM_WINDOWS
++
++	NdisAcquireSpinLock(plock);
++
++#endif
++
++}
++
++void	_rtw_spinunlock(_lock *plock)
++{
++
++#ifdef PLATFORM_LINUX
++
++	spin_unlock(plock);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++	mtx_unlock(plock);
++#endif
++#ifdef PLATFORM_WINDOWS
++
++	NdisReleaseSpinLock(plock);
++
++#endif
++}
++
++
++void	_rtw_spinlock_ex(_lock	*plock)
++{
++
++#ifdef PLATFORM_LINUX
++
++	spin_lock(plock);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++	mtx_lock(plock);
++#endif
++#ifdef PLATFORM_WINDOWS
++
++	NdisDprAcquireSpinLock(plock);
++
++#endif
++
++}
++
++void	_rtw_spinunlock_ex(_lock *plock)
++{
++
++#ifdef PLATFORM_LINUX
++
++	spin_unlock(plock);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++	mtx_unlock(plock);
++#endif
++#ifdef PLATFORM_WINDOWS
++
++	NdisDprReleaseSpinLock(plock);
++
++#endif
++}
++
++
++
++void _rtw_init_queue(_queue *pqueue)
++{
++	_rtw_init_listhead(&(pqueue->queue));
++	_rtw_spinlock_init(&(pqueue->lock));
++}
++
++void _rtw_deinit_queue(_queue *pqueue)
++{
++	_rtw_spinlock_free(&(pqueue->lock));
++}
++
++u32	  _rtw_queue_empty(_queue	*pqueue)
++{
++	return rtw_is_list_empty(&(pqueue->queue));
++}
++
++
++u32 rtw_end_of_queue_search(_list *head, _list *plist)
++{
++	if (head == plist)
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++
++systime _rtw_get_current_time(void)
++{
++
++#ifdef PLATFORM_LINUX
++	return jiffies;
++#endif
++#ifdef PLATFORM_FREEBSD
++	struct timeval tvp;
++	getmicrotime(&tvp);
++	return tvp.tv_sec;
++#endif
++#ifdef PLATFORM_WINDOWS
++	LARGE_INTEGER	SystemTime;
++	NdisGetCurrentSystemTime(&SystemTime);
++	return SystemTime.LowPart;/* count of 100-nanosecond intervals */
++#endif
++}
++
++inline u32 _rtw_systime_to_ms(systime stime)
++{
++#ifdef PLATFORM_LINUX
++	return jiffies_to_msecs(stime);
++#endif
++#ifdef PLATFORM_FREEBSD
++	return stime * 1000;
++#endif
++#ifdef PLATFORM_WINDOWS
++	return stime / 10000 ;
++#endif
++}
++
++inline systime _rtw_ms_to_systime(u32 ms)
++{
++#ifdef PLATFORM_LINUX
++	return msecs_to_jiffies(ms);
++#endif
++#ifdef PLATFORM_FREEBSD
++	return ms / 1000;
++#endif
++#ifdef PLATFORM_WINDOWS
++	return ms * 10000 ;
++#endif
++}
++
++inline systime _rtw_us_to_systime(u32 us)
++{
++#ifdef PLATFORM_LINUX
++	return usecs_to_jiffies(us);
++#else
++	#error "TBD\n"
++#endif
++}
++
++/* the input parameter start use the same unit as returned by rtw_get_current_time */
++inline s32 _rtw_get_passing_time_ms(systime start)
++{
++	return _rtw_systime_to_ms(_rtw_get_current_time() - start);
++}
++
++inline s32 _rtw_get_remaining_time_ms(systime end)
++{
++	return _rtw_systime_to_ms(end - _rtw_get_current_time());
++}
++
++inline s32 _rtw_get_time_interval_ms(systime start, systime end)
++{
++	return _rtw_systime_to_ms(end - start);
++}
++
++inline bool _rtw_time_after(systime a, systime b)
++{
++#ifdef PLATFORM_LINUX
++	return time_after(a, b);
++#else
++	#error "TBD\n"
++#endif
++}
++
++void rtw_sleep_schedulable(int ms)
++{
++
++#ifdef PLATFORM_LINUX
++
++	u32 delta;
++
++	delta = (ms * HZ) / 1000; /* (ms) */
++	if (delta == 0) {
++		delta = 1;/* 1 ms */
++	}
++	set_current_state(TASK_INTERRUPTIBLE);
++        schedule_timeout(delta);
++	return;
++
++#endif
++#ifdef PLATFORM_FREEBSD
++	DELAY(ms * 1000);
++	return ;
++#endif
++
++#ifdef PLATFORM_WINDOWS
++
++	NdisMSleep(ms * 1000); /* (us)*1000=(ms) */
++
++#endif
++
++}
++
++
++void rtw_msleep_os(int ms)
++{
++
++#ifdef PLATFORM_LINUX
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))
++	if (ms < 20) {
++		unsigned long us = ms * 1000UL;
++		usleep_range(us, us + 1000UL);
++	} else
++#endif
++		msleep((unsigned int)ms);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++	/* Delay for delay microseconds */
++	DELAY(ms * 1000);
++	return ;
++#endif
++#ifdef PLATFORM_WINDOWS
++
++	NdisMSleep(ms * 1000); /* (us)*1000=(ms) */
++
++#endif
++
++
++}
++void rtw_usleep_os(int us)
++{
++#ifdef PLATFORM_LINUX
++
++	/* msleep((unsigned int)us); */
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))
++	usleep_range(us, us + 1);
++#else
++	if (1 < (us / 1000))
++		msleep(1);
++	else
++		msleep((us / 1000) + 1);
++#endif
++#endif
++
++#ifdef PLATFORM_FREEBSD
++	/* Delay for delay microseconds */
++	DELAY(us);
++
++	return ;
++#endif
++#ifdef PLATFORM_WINDOWS
++
++	NdisMSleep(us); /* (us) */
++
++#endif
++
++
++}
++
++
++#ifdef DBG_DELAY_OS
++void _rtw_mdelay_os(int ms, const char *func, const int line)
++{
++#if 0
++	if (ms > 10)
++		RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms);
++	rtw_msleep_os(ms);
++	return;
++#endif
++
++
++	RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms);
++
++#if defined(PLATFORM_LINUX)
++
++	mdelay((unsigned long)ms);
++
++#elif defined(PLATFORM_WINDOWS)
++
++	NdisStallExecution(ms * 1000); /* (us)*1000=(ms) */
++
++#endif
++
++
++}
++void _rtw_udelay_os(int us, const char *func, const int line)
++{
++
++#if 0
++	if (us > 1000) {
++		RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, us);
++		rtw_usleep_os(us);
++		return;
++	}
++#endif
++
++
++	RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, us);
++
++
++#if defined(PLATFORM_LINUX)
++
++	udelay((unsigned long)us);
++
++#elif defined(PLATFORM_WINDOWS)
++
++	NdisStallExecution(us); /* (us) */
++
++#endif
++
++}
++#else
++void rtw_mdelay_os(int ms)
++{
++
++#ifdef PLATFORM_LINUX
++
++	mdelay((unsigned long)ms);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++	DELAY(ms * 1000);
++	return ;
++#endif
++#ifdef PLATFORM_WINDOWS
++
++	NdisStallExecution(ms * 1000); /* (us)*1000=(ms) */
++
++#endif
++
++
++}
++void rtw_udelay_os(int us)
++{
++
++#ifdef PLATFORM_LINUX
++
++	udelay((unsigned long)us);
++
++#endif
++#ifdef PLATFORM_FREEBSD
++	/* Delay for delay microseconds */
++	DELAY(us);
++	return ;
++#endif
++#ifdef PLATFORM_WINDOWS
++
++	NdisStallExecution(us); /* (us) */
++
++#endif
++
++}
++#endif
++
++void rtw_yield_os(void)
++{
++#ifdef PLATFORM_LINUX
++	yield();
++#endif
++#ifdef PLATFORM_FREEBSD
++	yield();
++#endif
++#ifdef PLATFORM_WINDOWS
++	SwitchToThread();
++#endif
++}
++
++bool rtw_macaddr_is_larger(const u8 *a, const u8 *b)
++{
++	u32 va, vb;
++
++	va = be32_to_cpu(*((u32 *)a));
++	vb = be32_to_cpu(*((u32 *)b));
++	if (va > vb)
++		return 1;
++	else if (va < vb)
++		return 0;
++
++	return be16_to_cpu(*((u16 *)(a + 4))) > be16_to_cpu(*((u16 *)(b + 4)));
++}
++
++#define RTW_SUSPEND_LOCK_NAME "rtw_wifi"
++#define RTW_SUSPEND_TRAFFIC_LOCK_NAME "rtw_wifi_traffic"
++#define RTW_SUSPEND_RESUME_LOCK_NAME "rtw_wifi_resume"
++#ifdef CONFIG_WAKELOCK
++static struct wake_lock rtw_suspend_lock;
++static struct wake_lock rtw_suspend_traffic_lock;
++static struct wake_lock rtw_suspend_resume_lock;
++#elif defined(CONFIG_ANDROID_POWER)
++static android_suspend_lock_t rtw_suspend_lock = {
++	.name = RTW_SUSPEND_LOCK_NAME
++};
++static android_suspend_lock_t rtw_suspend_traffic_lock = {
++	.name = RTW_SUSPEND_TRAFFIC_LOCK_NAME
++};
++static android_suspend_lock_t rtw_suspend_resume_lock = {
++	.name = RTW_SUSPEND_RESUME_LOCK_NAME
++};
++#endif
++
++inline void rtw_suspend_lock_init(void)
++{
++#ifdef CONFIG_WAKELOCK
++	wake_lock_init(&rtw_suspend_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_LOCK_NAME);
++	wake_lock_init(&rtw_suspend_traffic_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_TRAFFIC_LOCK_NAME);
++	wake_lock_init(&rtw_suspend_resume_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_RESUME_LOCK_NAME);
++#elif defined(CONFIG_ANDROID_POWER)
++	android_init_suspend_lock(&rtw_suspend_lock);
++	android_init_suspend_lock(&rtw_suspend_traffic_lock);
++	android_init_suspend_lock(&rtw_suspend_resume_lock);
++#endif
++}
++
++inline void rtw_suspend_lock_uninit(void)
++{
++#ifdef CONFIG_WAKELOCK
++	wake_lock_destroy(&rtw_suspend_lock);
++	wake_lock_destroy(&rtw_suspend_traffic_lock);
++	wake_lock_destroy(&rtw_suspend_resume_lock);
++#elif defined(CONFIG_ANDROID_POWER)
++	android_uninit_suspend_lock(&rtw_suspend_lock);
++	android_uninit_suspend_lock(&rtw_suspend_traffic_lock);
++	android_uninit_suspend_lock(&rtw_suspend_resume_lock);
++#endif
++}
++
++inline void rtw_lock_suspend(void)
++{
++#ifdef CONFIG_WAKELOCK
++	wake_lock(&rtw_suspend_lock);
++#elif defined(CONFIG_ANDROID_POWER)
++	android_lock_suspend(&rtw_suspend_lock);
++#endif
++
++#if  defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)
++	/* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */
++#endif
++}
++
++inline void rtw_unlock_suspend(void)
++{
++#ifdef CONFIG_WAKELOCK
++	wake_unlock(&rtw_suspend_lock);
++#elif defined(CONFIG_ANDROID_POWER)
++	android_unlock_suspend(&rtw_suspend_lock);
++#endif
++
++#if  defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)
++	/* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */
++#endif
++}
++
++inline void rtw_resume_lock_suspend(void)
++{
++#ifdef CONFIG_WAKELOCK
++	wake_lock(&rtw_suspend_resume_lock);
++#elif defined(CONFIG_ANDROID_POWER)
++	android_lock_suspend(&rtw_suspend_resume_lock);
++#endif
++
++#if  defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)
++	/* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */
++#endif
++}
++
++inline void rtw_resume_unlock_suspend(void)
++{
++#ifdef CONFIG_WAKELOCK
++	wake_unlock(&rtw_suspend_resume_lock);
++#elif defined(CONFIG_ANDROID_POWER)
++	android_unlock_suspend(&rtw_suspend_resume_lock);
++#endif
++
++#if  defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)
++	/* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */
++#endif
++}
++
++inline void rtw_lock_suspend_timeout(u32 timeout_ms)
++{
++#ifdef CONFIG_WAKELOCK
++	wake_lock_timeout(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms));
++#elif defined(CONFIG_ANDROID_POWER)
++	android_lock_suspend_auto_expire(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms));
++#endif
++}
++
++
++inline void rtw_lock_traffic_suspend_timeout(u32 timeout_ms)
++{
++#ifdef CONFIG_WAKELOCK
++	wake_lock_timeout(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms));
++#elif defined(CONFIG_ANDROID_POWER)
++	android_lock_suspend_auto_expire(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms));
++#endif
++	/* RTW_INFO("traffic lock timeout:%d\n", timeout_ms); */
++}
++
++inline void rtw_set_bit(int nr, unsigned long *addr)
++{
++#ifdef PLATFORM_LINUX
++	set_bit(nr, addr);
++#else
++	#error "TBD\n";
++#endif
++}
++
++inline void rtw_clear_bit(int nr, unsigned long *addr)
++{
++#ifdef PLATFORM_LINUX
++	clear_bit(nr, addr);
++#else
++	#error "TBD\n";
++#endif
++}
++
++inline int rtw_test_and_clear_bit(int nr, unsigned long *addr)
++{
++#ifdef PLATFORM_LINUX
++	return test_and_clear_bit(nr, addr);
++#else
++	#error "TBD\n";
++#endif
++}
++
++inline void ATOMIC_SET(ATOMIC_T *v, int i)
++{
++#ifdef PLATFORM_LINUX
++	atomic_set(v, i);
++#elif defined(PLATFORM_WINDOWS)
++	*v = i; /* other choice???? */
++#elif defined(PLATFORM_FREEBSD)
++	atomic_set_int(v, i);
++#endif
++}
++
++inline int ATOMIC_READ(ATOMIC_T *v)
++{
++#ifdef PLATFORM_LINUX
++	return atomic_read(v);
++#elif defined(PLATFORM_WINDOWS)
++	return *v; /* other choice???? */
++#elif defined(PLATFORM_FREEBSD)
++	return atomic_load_acq_32(v);
++#endif
++}
++
++inline void ATOMIC_ADD(ATOMIC_T *v, int i)
++{
++#ifdef PLATFORM_LINUX
++	atomic_add(i, v);
++#elif defined(PLATFORM_WINDOWS)
++	InterlockedAdd(v, i);
++#elif defined(PLATFORM_FREEBSD)
++	atomic_add_int(v, i);
++#endif
++}
++inline void ATOMIC_SUB(ATOMIC_T *v, int i)
++{
++#ifdef PLATFORM_LINUX
++	atomic_sub(i, v);
++#elif defined(PLATFORM_WINDOWS)
++	InterlockedAdd(v, -i);
++#elif defined(PLATFORM_FREEBSD)
++	atomic_subtract_int(v, i);
++#endif
++}
++
++inline void ATOMIC_INC(ATOMIC_T *v)
++{
++#ifdef PLATFORM_LINUX
++	atomic_inc(v);
++#elif defined(PLATFORM_WINDOWS)
++	InterlockedIncrement(v);
++#elif defined(PLATFORM_FREEBSD)
++	atomic_add_int(v, 1);
++#endif
++}
++
++inline void ATOMIC_DEC(ATOMIC_T *v)
++{
++#ifdef PLATFORM_LINUX
++	atomic_dec(v);
++#elif defined(PLATFORM_WINDOWS)
++	InterlockedDecrement(v);
++#elif defined(PLATFORM_FREEBSD)
++	atomic_subtract_int(v, 1);
++#endif
++}
++
++inline int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i)
++{
++#ifdef PLATFORM_LINUX
++	return atomic_add_return(i, v);
++#elif defined(PLATFORM_WINDOWS)
++	return InterlockedAdd(v, i);
++#elif defined(PLATFORM_FREEBSD)
++	atomic_add_int(v, i);
++	return atomic_load_acq_32(v);
++#endif
++}
++
++inline int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i)
++{
++#ifdef PLATFORM_LINUX
++	return atomic_sub_return(i, v);
++#elif defined(PLATFORM_WINDOWS)
++	return InterlockedAdd(v, -i);
++#elif defined(PLATFORM_FREEBSD)
++	atomic_subtract_int(v, i);
++	return atomic_load_acq_32(v);
++#endif
++}
++
++inline int ATOMIC_INC_RETURN(ATOMIC_T *v)
++{
++#ifdef PLATFORM_LINUX
++	return atomic_inc_return(v);
++#elif defined(PLATFORM_WINDOWS)
++	return InterlockedIncrement(v);
++#elif defined(PLATFORM_FREEBSD)
++	atomic_add_int(v, 1);
++	return atomic_load_acq_32(v);
++#endif
++}
++
++inline int ATOMIC_DEC_RETURN(ATOMIC_T *v)
++{
++#ifdef PLATFORM_LINUX
++	return atomic_dec_return(v);
++#elif defined(PLATFORM_WINDOWS)
++	return InterlockedDecrement(v);
++#elif defined(PLATFORM_FREEBSD)
++	atomic_subtract_int(v, 1);
++	return atomic_load_acq_32(v);
++#endif
++}
++
++inline bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u)
++{
++#ifdef PLATFORM_LINUX
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 15))
++	return atomic_add_unless(v, 1, u);
++#else
++	/* only make sure not exceed after this function */
++	if (ATOMIC_INC_RETURN(v) > u) {
++		ATOMIC_DEC(v);
++		return 0;
++	}
++	return 1;
++#endif
++#else
++	#error "TBD\n"
++#endif
++}
++
++#ifdef PLATFORM_LINUX
++/*
++* Open a file with the specific @param path, @param flag, @param mode
++* @param fpp the pointer of struct file pointer to get struct file pointer while file opening is success
++* @param path the path of the file to open
++* @param flag file operation flags, please refer to linux document
++* @param mode please refer to linux document
++* @return Linux specific error code
++*/
++static int openFile(struct file **fpp, const char *path, int flag, int mode)
++{
++	struct file *fp;
++
++	fp = filp_open(path, flag, mode);
++	if (IS_ERR(fp)) {
++		*fpp = NULL;
++		return PTR_ERR(fp);
++	} else {
++		*fpp = fp;
++		return 0;
++	}
++}
++
++/*
++* Close the file with the specific @param fp
++* @param fp the pointer of struct file to close
++* @return always 0
++*/
++static int closeFile(struct file *fp)
++{
++	filp_close(fp, NULL);
++	return 0;
++}
++
++static int readFile(struct file *fp, char *buf, int len)
++{
++	int rlen = 0, sum = 0;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
++	if (!(fp->f_mode & FMODE_CAN_READ))
++#else
++	if (!fp->f_op || !fp->f_op->read)
++#endif
++		return -EPERM;
++
++	while (sum < len) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
++		rlen = kernel_read(fp, buf + sum, len - sum, &fp->f_pos);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
++		rlen = __vfs_read(fp, buf + sum, len - sum, &fp->f_pos);
++#else
++		rlen = fp->f_op->read(fp, buf + sum, len - sum, &fp->f_pos);
++#endif
++		if (rlen > 0)
++			sum += rlen;
++		else if (0 != rlen)
++			return rlen;
++		else
++			break;
++	}
++
++	return  sum;
++
++}
++
++static int writeFile(struct file *fp, char *buf, int len)
++{
++	int wlen = 0, sum = 0;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
++	if (!(fp->f_mode & FMODE_CAN_WRITE))
++#else
++	if (!fp->f_op || !fp->f_op->write)
++#endif
++		return -EPERM;
++
++	while (sum < len) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
++		wlen = kernel_write(fp, buf + sum, len - sum, &fp->f_pos);
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
++		wlen = __vfs_write(fp, buf + sum, len - sum, &fp->f_pos);
++#else
++		wlen = fp->f_op->write(fp, buf + sum, len - sum, &fp->f_pos);
++#endif
++		if (wlen > 0)
++			sum += wlen;
++		else if (0 != wlen)
++			return wlen;
++		else
++			break;
++	}
++
++	return sum;
++
++}
++
++/*
++* Test if the specifi @param pathname is a direct and readable
++* If readable, @param sz is not used
++* @param pathname the name of the path to test
++* @return Linux specific error code
++*/
++static int isDirReadable(const char *pathname, u32 *sz)
++{
++	struct path path;
++	int error = 0;
++
++	return kern_path(pathname, LOOKUP_FOLLOW, &path);
++}
++
++/*
++* Test if the specifi @param path is a file and readable
++* If readable, @param sz is got
++* @param path the path of the file to test
++* @return Linux specific error code
++*/
++static int isFileReadable(const char *path, u32 *sz)
++{
++	struct file *fp;
++	int ret = 0;
++	mm_segment_t oldfs;
++	char buf;
++
++	fp = filp_open(path, O_RDONLY, 0);
++	if (IS_ERR(fp))
++		ret = PTR_ERR(fp);
++	else {
++		oldfs = get_fs();
++		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0))
++		set_fs(KERNEL_DS);
++		#else
++		set_fs(get_ds());
++		#endif
++
++		if (1 != readFile(fp, &buf, 1))
++			ret = PTR_ERR(fp);
++
++		if (ret == 0 && sz) {
++			#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++			*sz = i_size_read(fp->f_path.dentry->d_inode);
++			#else
++			*sz = i_size_read(fp->f_dentry->d_inode);
++			#endif
++		}
++
++		set_fs(oldfs);
++		filp_close(fp, NULL);
++	}
++	return ret;
++}
++
++/*
++* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most
++* @param path the path of the file to open and read
++* @param buf the starting address of the buffer to store file content
++* @param sz how many bytes to read at most
++* @return the byte we've read, or Linux specific error code
++*/
++static int retriveFromFile(const char *path, u8 *buf, u32 sz)
++{
++	int ret = -1;
++	mm_segment_t oldfs;
++	struct file *fp;
++
++	if (path && buf) {
++		ret = openFile(&fp, path, O_RDONLY, 0);
++		if (0 == ret) {
++			RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp);
++
++			oldfs = get_fs();
++			#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0))
++			set_fs(KERNEL_DS);
++			#else
++			set_fs(get_ds());
++			#endif
++			ret = readFile(fp, buf, sz);
++			set_fs(oldfs);
++			closeFile(fp);
++
++			RTW_INFO("%s readFile, ret:%d\n", __FUNCTION__, ret);
++
++		} else
++			RTW_INFO("%s openFile path:%s Fail, ret:%d\n", __FUNCTION__, path, ret);
++	} else {
++		RTW_INFO("%s NULL pointer\n", __FUNCTION__);
++		ret =  -EINVAL;
++	}
++	return ret;
++}
++
++/*
++* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file
++* @param path the path of the file to open and write
++* @param buf the starting address of the data to write into file
++* @param sz how many bytes to write at most
++* @return the byte we've written, or Linux specific error code
++*/
++static int storeToFile(const char *path, u8 *buf, u32 sz)
++{
++	int ret = 0;
++	mm_segment_t oldfs;
++	struct file *fp;
++
++	if (path && buf) {
++		ret = openFile(&fp, path, O_CREAT | O_WRONLY, 0666);
++		if (0 == ret) {
++			RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp);
++
++			oldfs = get_fs();
++			#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0))
++			set_fs(KERNEL_DS);
++			#else
++			set_fs(get_ds());
++			#endif
++			ret = writeFile(fp, buf, sz);
++			set_fs(oldfs);
++			closeFile(fp);
++
++			RTW_INFO("%s writeFile, ret:%d\n", __FUNCTION__, ret);
++
++		} else
++			RTW_INFO("%s openFile path:%s Fail, ret:%d\n", __FUNCTION__, path, ret);
++	} else {
++		RTW_INFO("%s NULL pointer\n", __FUNCTION__);
++		ret =  -EINVAL;
++	}
++	return ret;
++}
++#endif /* PLATFORM_LINUX */
++
++/*
++* Test if the specifi @param path is a direct and readable
++* @param path the path of the direct to test
++* @return _TRUE or _FALSE
++*/
++int rtw_is_dir_readable(const char *path)
++{
++#ifdef PLATFORM_LINUX
++	if (isDirReadable(path, NULL) == 0)
++		return _TRUE;
++	else
++		return _FALSE;
++#else
++	/* Todo... */
++	return _FALSE;
++#endif
++}
++
++/*
++* Test if the specifi @param path is a file and readable
++* @param path the path of the file to test
++* @return _TRUE or _FALSE
++*/
++int rtw_is_file_readable(const char *path)
++{
++#ifdef PLATFORM_LINUX
++	if (isFileReadable(path, NULL) == 0)
++		return _TRUE;
++	else
++		return _FALSE;
++#else
++	/* Todo... */
++	return _FALSE;
++#endif
++}
++
++/*
++* Test if the specifi @param path is a file and readable.
++* If readable, @param sz is got
++* @param path the path of the file to test
++* @return _TRUE or _FALSE
++*/
++int rtw_is_file_readable_with_size(const char *path, u32 *sz)
++{
++#ifdef PLATFORM_LINUX
++	if (isFileReadable(path, sz) == 0)
++		return _TRUE;
++	else
++		return _FALSE;
++#else
++	/* Todo... */
++	return _FALSE;
++#endif
++}
++
++/*
++* Test if the specifi @param path is a readable file with valid size.
++* If readable, @param sz is got
++* @param path the path of the file to test
++* @return _TRUE or _FALSE
++*/
++int rtw_readable_file_sz_chk(const char *path, u32 sz)
++{
++	u32 fsz;
++
++	if (rtw_is_file_readable_with_size(path, &fsz) == _FALSE)
++		return _FALSE;
++
++	if (fsz > sz)
++		return _FALSE;
++	
++	return _TRUE;
++}
++
++/*
++* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most
++* @param path the path of the file to open and read
++* @param buf the starting address of the buffer to store file content
++* @param sz how many bytes to read at most
++* @return the byte we've read
++*/
++int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz)
++{
++#ifdef PLATFORM_LINUX
++	int ret = retriveFromFile(path, buf, sz);
++	return ret >= 0 ? ret : 0;
++#else
++	/* Todo... */
++	return 0;
++#endif
++}
++
++/*
++* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file
++* @param path the path of the file to open and write
++* @param buf the starting address of the data to write into file
++* @param sz how many bytes to write at most
++* @return the byte we've written
++*/
++int rtw_store_to_file(const char *path, u8 *buf, u32 sz)
++{
++#ifdef PLATFORM_LINUX
++	int ret = storeToFile(path, buf, sz);
++	return ret >= 0 ? ret : 0;
++#else
++	/* Todo... */
++	return 0;
++#endif
++}
++
++#ifdef PLATFORM_LINUX
++struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv)
++{
++	struct net_device *pnetdev;
++	struct rtw_netdev_priv_indicator *pnpi;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4);
++#else
++	pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator));
++#endif
++	if (!pnetdev)
++		goto RETURN;
++
++	pnpi = netdev_priv(pnetdev);
++	pnpi->priv = old_priv;
++	pnpi->sizeof_priv = sizeof_priv;
++
++RETURN:
++	return pnetdev;
++}
++
++struct net_device *rtw_alloc_etherdev(int sizeof_priv)
++{
++	struct net_device *pnetdev;
++	struct rtw_netdev_priv_indicator *pnpi;
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
++	pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4);
++#else
++	pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator));
++#endif
++	if (!pnetdev)
++		goto RETURN;
++
++	pnpi = netdev_priv(pnetdev);
++
++	pnpi->priv = rtw_zvmalloc(sizeof_priv);
++	if (!pnpi->priv) {
++		free_netdev(pnetdev);
++		pnetdev = NULL;
++		goto RETURN;
++	}
++
++	pnpi->sizeof_priv = sizeof_priv;
++RETURN:
++	return pnetdev;
++}
++
++void rtw_free_netdev(struct net_device *netdev)
++{
++	struct rtw_netdev_priv_indicator *pnpi;
++
++	if (!netdev)
++		goto RETURN;
++
++	pnpi = netdev_priv(netdev);
++
++	if (!pnpi->priv)
++		goto RETURN;
++
++	free_netdev(netdev);
++
++RETURN:
++	return;
++}
++
++int rtw_change_ifname(_adapter *padapter, const char *ifname)
++{
++	struct dvobj_priv *dvobj;
++	struct net_device *pnetdev;
++	struct net_device *cur_pnetdev;
++	struct rereg_nd_name_data *rereg_priv;
++	int ret;
++	u8 rtnl_lock_needed;
++
++	if (!padapter)
++		goto error;
++
++	dvobj = adapter_to_dvobj(padapter);
++	cur_pnetdev = padapter->pnetdev;
++	rereg_priv = &padapter->rereg_nd_name_priv;
++
++	/* free the old_pnetdev */
++	if (rereg_priv->old_pnetdev) {
++		free_netdev(rereg_priv->old_pnetdev);
++		rereg_priv->old_pnetdev = NULL;
++	}
++
++	rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj);
++
++	if (rtnl_lock_needed)
++		unregister_netdev(cur_pnetdev);
++	else
++		unregister_netdevice(cur_pnetdev);
++
++	rereg_priv->old_pnetdev = cur_pnetdev;
++
++	pnetdev = rtw_init_netdev(padapter);
++	if (!pnetdev)  {
++		ret = -1;
++		goto error;
++	}
++
++	SET_NETDEV_DEV(pnetdev, dvobj_to_dev(adapter_to_dvobj(padapter)));
++
++	rtw_init_netdev_name(pnetdev, ifname);
++
++	_rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN);
++
++	if (rtnl_lock_needed)
++		ret = register_netdev(pnetdev);
++	else
++		ret = register_netdevice(pnetdev);
++
++	if (ret != 0) {
++		goto error;
++	}
++
++	return 0;
++
++error:
++
++	return -1;
++
++}
++#endif
++
++#ifdef PLATFORM_FREEBSD
++/*
++ * Copy a buffer from userspace and write into kernel address
++ * space.
++ *
++ * This emulation just calls the FreeBSD copyin function (to
++ * copy data from user space buffer into a kernel space buffer)
++ * and is designed to be used with the above io_write_wrapper.
++ *
++ * This function should return the number of bytes not copied.
++ * I.e. success results in a zero value.
++ * Negative error values are not returned.
++ */
++unsigned long
++copy_from_user(void *to, const void *from, unsigned long n)
++{
++	if (copyin(from, to, n) != 0) {
++		/* Any errors will be treated as a failure
++		   to copy any of the requested bytes */
++		return n;
++	}
++
++	return 0;
++}
++
++unsigned long
++copy_to_user(void *to, const void *from, unsigned long n)
++{
++	if (copyout(from, to, n) != 0) {
++		/* Any errors will be treated as a failure
++		   to copy any of the requested bytes */
++		return n;
++	}
++
++	return 0;
++}
++
++
++/*
++ * The usb_register and usb_deregister functions are used to register
++ * usb drivers with the usb subsystem. In this compatibility layer
++ * emulation a list of drivers (struct usb_driver) is maintained
++ * and is used for probing/attaching etc.
++ *
++ * usb_register and usb_deregister simply call these functions.
++ */
++int
++usb_register(struct usb_driver *driver)
++{
++	rtw_usb_linux_register(driver);
++	return 0;
++}
++
++
++int
++usb_deregister(struct usb_driver *driver)
++{
++	rtw_usb_linux_deregister(driver);
++	return 0;
++}
++
++void module_init_exit_wrapper(void *arg)
++{
++	int (*func)(void) = arg;
++	func();
++	return;
++}
++
++#endif /* PLATFORM_FREEBSD */
++
++#ifdef CONFIG_PLATFORM_SPRD
++	#ifdef do_div
++		#undef do_div
++	#endif
++	#include <asm-generic/div64.h>
++#endif
++
++u64 rtw_modular64(u64 x, u64 y)
++{
++#ifdef PLATFORM_LINUX
++	return do_div(x, y);
++#elif defined(PLATFORM_WINDOWS)
++	return x % y;
++#elif defined(PLATFORM_FREEBSD)
++	return x % y;
++#endif
++}
++
++u64 rtw_division64(u64 x, u64 y)
++{
++#ifdef PLATFORM_LINUX
++	do_div(x, y);
++	return x;
++#elif defined(PLATFORM_WINDOWS)
++	return x / y;
++#elif defined(PLATFORM_FREEBSD)
++	return x / y;
++#endif
++}
++
++inline u32 rtw_random32(void)
++{
++#ifdef PLATFORM_LINUX
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
++	return prandom_u32();
++#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 18))
++	u32 random_int;
++	get_random_bytes(&random_int , 4);
++	return random_int;
++#else
++	return random32();
++#endif
++#elif defined(PLATFORM_WINDOWS)
++#error "to be implemented\n"
++#elif defined(PLATFORM_FREEBSD)
++#error "to be implemented\n"
++#endif
++}
++
++void rtw_buf_free(u8 **buf, u32 *buf_len)
++{
++	u32 ori_len;
++
++	if (!buf || !buf_len)
++		return;
++
++	ori_len = *buf_len;
++
++	if (*buf) {
++		u32 tmp_buf_len = *buf_len;
++		*buf_len = 0;
++		rtw_mfree(*buf, tmp_buf_len);
++		*buf = NULL;
++	}
++}
++
++void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len)
++{
++	u32 ori_len = 0, dup_len = 0;
++	u8 *ori = NULL;
++	u8 *dup = NULL;
++
++	if (!buf || !buf_len)
++		return;
++
++	if (!src || !src_len)
++		goto keep_ori;
++
++	/* duplicate src */
++	dup = rtw_malloc(src_len);
++	if (dup) {
++		dup_len = src_len;
++		_rtw_memcpy(dup, src, dup_len);
++	}
++
++keep_ori:
++	ori = *buf;
++	ori_len = *buf_len;
++
++	/* replace buf with dup */
++	*buf_len = 0;
++	*buf = dup;
++	*buf_len = dup_len;
++
++	/* free ori */
++	if (ori && ori_len > 0)
++		rtw_mfree(ori, ori_len);
++}
++
++
++/**
++ * rtw_cbuf_full - test if cbuf is full
++ * @cbuf: pointer of struct rtw_cbuf
++ *
++ * Returns: _TRUE if cbuf is full
++ */
++inline bool rtw_cbuf_full(struct rtw_cbuf *cbuf)
++{
++	return (cbuf->write == cbuf->read - 1) ? _TRUE : _FALSE;
++}
++
++/**
++ * rtw_cbuf_empty - test if cbuf is empty
++ * @cbuf: pointer of struct rtw_cbuf
++ *
++ * Returns: _TRUE if cbuf is empty
++ */
++inline bool rtw_cbuf_empty(struct rtw_cbuf *cbuf)
++{
++	return (cbuf->write == cbuf->read) ? _TRUE : _FALSE;
++}
++
++/**
++ * rtw_cbuf_push - push a pointer into cbuf
++ * @cbuf: pointer of struct rtw_cbuf
++ * @buf: pointer to push in
++ *
++ * Lock free operation, be careful of the use scheme
++ * Returns: _TRUE push success
++ */
++bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf)
++{
++	if (rtw_cbuf_full(cbuf))
++		return _FAIL;
++
++	if (0)
++		RTW_INFO("%s on %u\n", __func__, cbuf->write);
++	cbuf->bufs[cbuf->write] = buf;
++	cbuf->write = (cbuf->write + 1) % cbuf->size;
++
++	return _SUCCESS;
++}
++
++/**
++ * rtw_cbuf_pop - pop a pointer from cbuf
++ * @cbuf: pointer of struct rtw_cbuf
++ *
++ * Lock free operation, be careful of the use scheme
++ * Returns: pointer popped out
++ */
++void *rtw_cbuf_pop(struct rtw_cbuf *cbuf)
++{
++	void *buf;
++	if (rtw_cbuf_empty(cbuf))
++		return NULL;
++
++	if (0)
++		RTW_INFO("%s on %u\n", __func__, cbuf->read);
++	buf = cbuf->bufs[cbuf->read];
++	cbuf->read = (cbuf->read + 1) % cbuf->size;
++
++	return buf;
++}
++
++/**
++ * rtw_cbuf_alloc - allocte a rtw_cbuf with given size and do initialization
++ * @size: size of pointer
++ *
++ * Returns: pointer of srtuct rtw_cbuf, NULL for allocation failure
++ */
++struct rtw_cbuf *rtw_cbuf_alloc(u32 size)
++{
++	struct rtw_cbuf *cbuf;
++
++	cbuf = (struct rtw_cbuf *)rtw_malloc(sizeof(*cbuf) + sizeof(void *) * size);
++
++	if (cbuf) {
++		cbuf->write = cbuf->read = 0;
++		cbuf->size = size;
++	}
++
++	return cbuf;
++}
++
++/**
++ * rtw_cbuf_free - free the given rtw_cbuf
++ * @cbuf: pointer of struct rtw_cbuf to free
++ */
++void rtw_cbuf_free(struct rtw_cbuf *cbuf)
++{
++	rtw_mfree((u8 *)cbuf, sizeof(*cbuf) + sizeof(void *) * cbuf->size);
++}
++
++/**
++ * map_readN - read a range of map data
++ * @map: map to read
++ * @offset: start address to read
++ * @len: length to read
++ * @buf: pointer of buffer to store data read
++ *
++ * Returns: _SUCCESS or _FAIL
++ */
++int map_readN(const struct map_t *map, u16 offset, u16 len, u8 *buf)
++{
++	const struct map_seg_t *seg;
++	int ret = _FAIL;
++	int i;
++
++	if (len == 0) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	if (offset + len > map->len) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	_rtw_memset(buf, map->init_value, len);
++
++	for (i = 0; i < map->seg_num; i++) {
++		u8 *c_dst, *c_src;
++		u16 c_len;
++
++		seg = map->segs + i;
++		if (seg->sa + seg->len <= offset || seg->sa >= offset + len)
++			continue;
++
++		if (seg->sa >= offset) {
++			c_dst = buf + (seg->sa - offset);
++			c_src = seg->c;
++			if (seg->sa + seg->len <= offset + len)
++				c_len = seg->len;
++			else
++				c_len = offset + len - seg->sa;
++		} else {
++			c_dst = buf;
++			c_src = seg->c + (offset - seg->sa);
++			if (seg->sa + seg->len >= offset + len)
++				c_len = len;
++			else
++				c_len = seg->sa + seg->len - offset;
++		}
++			
++		_rtw_memcpy(c_dst, c_src, c_len);
++	}
++
++exit:
++	return ret;
++}
++
++/**
++ * map_read8 - read 1 byte of map data
++ * @map: map to read
++ * @offset: address to read
++ *
++ * Returns: value of data of specified offset. map.init_value if offset is out of range
++ */
++u8 map_read8(const struct map_t *map, u16 offset)
++{
++	const struct map_seg_t *seg;
++	u8 val = map->init_value;
++	int i;
++
++	if (offset + 1 > map->len) {
++		rtw_warn_on(1);
++		goto exit;
++	}
++
++	for (i = 0; i < map->seg_num; i++) {
++		seg = map->segs + i;
++		if (seg->sa + seg->len <= offset || seg->sa >= offset + 1)
++			continue;
++
++		val = *(seg->c + offset - seg->sa);
++		break;
++	}
++
++exit:
++	return val;
++}
++
++int rtw_blacklist_add(_queue *blist, const u8 *addr, u32 timeout_ms)
++{
++	struct blacklist_ent *ent;
++	_list *list, *head;
++	u8 exist = _FALSE, timeout = _FALSE;
++
++	enter_critical_bh(&blist->lock);
++
++	head = &blist->queue;
++	list = get_next(head);
++	while (rtw_end_of_queue_search(head, list) == _FALSE) {
++		ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
++		list = get_next(list);
++
++		if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) {
++			exist = _TRUE;
++			if (rtw_time_after(rtw_get_current_time(), ent->exp_time))
++				timeout = _TRUE;
++			ent->exp_time = rtw_get_current_time()
++				+ rtw_ms_to_systime(timeout_ms);
++			break;
++		}
++
++		if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
++			rtw_list_delete(&ent->list);
++			rtw_mfree(ent, sizeof(struct blacklist_ent));
++		}
++	}
++
++	if (exist == _FALSE) {
++		ent = rtw_malloc(sizeof(struct blacklist_ent));
++		if (ent) {
++			_rtw_memcpy(ent->addr, addr, ETH_ALEN);
++			ent->exp_time = rtw_get_current_time()
++				+ rtw_ms_to_systime(timeout_ms);
++			rtw_list_insert_tail(&ent->list, head);
++		}
++	}
++
++	exit_critical_bh(&blist->lock);
++
++	return (exist == _TRUE && timeout == _FALSE) ? RTW_ALREADY : (ent ? _SUCCESS : _FAIL);
++}
++
++int rtw_blacklist_del(_queue *blist, const u8 *addr)
++{
++	struct blacklist_ent *ent = NULL;
++	_list *list, *head;
++	u8 exist = _FALSE;
++
++	enter_critical_bh(&blist->lock);
++	head = &blist->queue;
++	list = get_next(head);
++	while (rtw_end_of_queue_search(head, list) == _FALSE) {
++		ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
++		list = get_next(list);
++
++		if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) {
++			rtw_list_delete(&ent->list);
++			rtw_mfree(ent, sizeof(struct blacklist_ent));
++			exist = _TRUE;
++			break;
++		}
++
++		if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
++			rtw_list_delete(&ent->list);
++			rtw_mfree(ent, sizeof(struct blacklist_ent));
++		}
++	}
++
++	exit_critical_bh(&blist->lock);
++
++	return exist == _TRUE ? _SUCCESS : RTW_ALREADY;
++}
++
++int rtw_blacklist_search(_queue *blist, const u8 *addr)
++{
++	struct blacklist_ent *ent = NULL;
++	_list *list, *head;
++	u8 exist = _FALSE;
++
++	enter_critical_bh(&blist->lock);
++	head = &blist->queue;
++	list = get_next(head);
++	while (rtw_end_of_queue_search(head, list) == _FALSE) {
++		ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
++		list = get_next(list);
++
++		if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) {
++			if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
++				rtw_list_delete(&ent->list);
++				rtw_mfree(ent, sizeof(struct blacklist_ent));
++			} else
++				exist = _TRUE;
++			break;
++		}
++
++		if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
++			rtw_list_delete(&ent->list);
++			rtw_mfree(ent, sizeof(struct blacklist_ent));
++		}
++	}
++
++	exit_critical_bh(&blist->lock);
++
++	return exist;
++}
++
++void rtw_blacklist_flush(_queue *blist)
++{
++	struct blacklist_ent *ent;
++	_list *list, *head;
++	_list tmp;
++
++	_rtw_init_listhead(&tmp);
++
++	enter_critical_bh(&blist->lock);
++	rtw_list_splice_init(&blist->queue, &tmp);
++	exit_critical_bh(&blist->lock);
++
++	head = &tmp;
++	list = get_next(head);
++	while (rtw_end_of_queue_search(head, list) == _FALSE) {
++		ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
++		list = get_next(list);
++		rtw_list_delete(&ent->list);
++		rtw_mfree(ent, sizeof(struct blacklist_ent));
++	}
++}
++
++void dump_blacklist(void *sel, _queue *blist, const char *title)
++{
++	struct blacklist_ent *ent = NULL;
++	_list *list, *head;
++
++	enter_critical_bh(&blist->lock);
++	head = &blist->queue;
++	list = get_next(head);
++
++	if (rtw_end_of_queue_search(head, list) == _FALSE) {
++		if (title)
++			RTW_PRINT_SEL(sel, "%s:\n", title);
++	
++		while (rtw_end_of_queue_search(head, list) == _FALSE) {
++			ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
++			list = get_next(list);
++
++			if (rtw_time_after(rtw_get_current_time(), ent->exp_time))
++				RTW_PRINT_SEL(sel, MAC_FMT" expired\n", MAC_ARG(ent->addr));
++			else
++				RTW_PRINT_SEL(sel, MAC_FMT" %u\n", MAC_ARG(ent->addr)
++					, rtw_get_remaining_time_ms(ent->exp_time));
++		}
++
++	}
++	exit_critical_bh(&blist->lock);
++}
++
++/**
++* is_null -
++*
++* Return	TRUE if c is null character
++*		FALSE otherwise.
++*/
++inline BOOLEAN is_null(char c)
++{
++	if (c == '\0')
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++inline BOOLEAN is_all_null(char *c, int len)
++{
++	for (; len > 0; len--)
++		if (c[len - 1] != '\0')
++			return _FALSE;
++
++	return _TRUE;
++}
++
++/**
++* is_eol -
++*
++* Return	TRUE if c is represent for EOL (end of line)
++*		FALSE otherwise.
++*/
++inline BOOLEAN is_eol(char c)
++{
++	if (c == '\r' || c == '\n')
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++/**
++* is_space -
++*
++* Return	TRUE if c is represent for space
++*		FALSE otherwise.
++*/
++inline BOOLEAN is_space(char c)
++{
++	if (c == ' ' || c == '\t')
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++/**
++* IsHexDigit -
++*
++* Return	TRUE if chTmp is represent for hex digit
++*		FALSE otherwise.
++*/
++inline BOOLEAN IsHexDigit(char chTmp)
++{
++	if ((chTmp >= '0' && chTmp <= '9') ||
++		(chTmp >= 'a' && chTmp <= 'f') ||
++		(chTmp >= 'A' && chTmp <= 'F'))
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++/**
++* is_alpha -
++*
++* Return	TRUE if chTmp is represent for alphabet
++*		FALSE otherwise.
++*/
++inline BOOLEAN is_alpha(char chTmp)
++{
++	if ((chTmp >= 'a' && chTmp <= 'z') ||
++		(chTmp >= 'A' && chTmp <= 'Z'))
++		return _TRUE;
++	else
++		return _FALSE;
++}
++
++inline char alpha_to_upper(char c)
++{
++	if ((c >= 'a' && c <= 'z'))
++		c = 'A' + (c - 'a');
++	return c;
++}
++
++int hex2num_i(char c)
++{
++	if (c >= '0' && c <= '9')
++		return c - '0';
++	if (c >= 'a' && c <= 'f')
++		return c - 'a' + 10;
++	if (c >= 'A' && c <= 'F')
++		return c - 'A' + 10;
++	return -1;
++}
++
++int hex2byte_i(const char *hex)
++{
++	int a, b;
++	a = hex2num_i(*hex++);
++	if (a < 0)
++		return -1;
++	b = hex2num_i(*hex++);
++	if (b < 0)
++		return -1;
++	return (a << 4) | b;
++}
++
++int hexstr2bin(const char *hex, u8 *buf, size_t len)
++{
++	size_t i;
++	int a;
++	const char *ipos = hex;
++	u8 *opos = buf;
++
++	for (i = 0; i < len; i++) {
++		a = hex2byte_i(ipos);
++		if (a < 0)
++			return -1;
++		*opos++ = a;
++		ipos += 2;
++	}
++	return 0;
++}
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/custom_country_chplan.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/custom_country_chplan.h
+new file mode 100644
+index 000000000..f8cc13bf1
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/custom_country_chplan.h
+@@ -0,0 +1,22 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#error "You have defined CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP to use a customized map of your own instead of the default one"
++#error "Before removing these error notifications, please make sure regulatory certification requirements of your target markets"
++
++static const struct country_chplan CUSTOMIZED_country_chplan_map[] = {
++	COUNTRY_CHPLAN_ENT("TW", 0x76, 1, 0x3FF), /* Taiwan */
++};
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ARM_SUN50IW1P1_sdio.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ARM_SUN50IW1P1_sdio.c
+new file mode 100644
+index 000000000..2586455de
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ARM_SUN50IW1P1_sdio.c
+@@ -0,0 +1,86 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*
++ * Description:
++ *	This file can be applied to following platforms:
++ *	CONFIG_PLATFORM_ARM_SUN50IW1P1
++ */
++#include <drv_types.h>
++#ifdef CONFIG_GPIO_WAKEUP
++#include <linux/gpio.h>
++#endif
++
++#ifdef CONFIG_MMC
++#if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)
++extern void sunxi_mmc_rescan_card(unsigned ids);
++extern void sunxi_wlan_set_power(int on);
++extern int sunxi_wlan_get_bus_index(void);
++extern int sunxi_wlan_get_oob_irq(void);
++extern int sunxi_wlan_get_oob_irq_flags(void);
++#endif
++#ifdef CONFIG_GPIO_WAKEUP
++extern unsigned int oob_irq;
++#endif
++#endif /* CONFIG_MMC */
++
++/*
++ * Return:
++ *	0:	power on successfully
++ *	others: power on failed
++ */
++int platform_wifi_power_on(void)
++{
++	int ret = 0;
++
++#ifdef CONFIG_MMC
++	{
++
++#if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)
++		int wlan_bus_index = sunxi_wlan_get_bus_index();
++		if (wlan_bus_index < 0)
++			return wlan_bus_index;
++
++		sunxi_wlan_set_power(1);
++		mdelay(100);
++		sunxi_mmc_rescan_card(wlan_bus_index);
++#endif
++		RTW_INFO("%s: power up, rescan card.\n", __FUNCTION__);
++
++#ifdef CONFIG_GPIO_WAKEUP
++#if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)
++		oob_irq = sunxi_wlan_get_oob_irq();
++#endif
++#endif /* CONFIG_GPIO_WAKEUP */
++	}
++#endif /* CONFIG_MMC */
++
++	return ret;
++}
++
++void platform_wifi_power_off(void)
++{
++#ifdef CONFIG_MMC
++#if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)
++	int wlan_bus_index = sunxi_wlan_get_bus_index();
++	if (wlan_bus_index < 0)
++		return;
++
++	sunxi_mmc_rescan_card(wlan_bus_index);
++	mdelay(100);
++	sunxi_wlan_set_power(0);
++#endif
++	RTW_INFO("%s: remove card, power off.\n", __FUNCTION__);
++#endif /* CONFIG_MMC */
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ARM_SUNnI_sdio.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ARM_SUNnI_sdio.c
+new file mode 100644
+index 000000000..8a52aa90c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ARM_SUNnI_sdio.c
+@@ -0,0 +1,130 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*
++ * Description:
++ *	This file can be applied to following platforms:
++ *	CONFIG_PLATFORM_ARM_SUN6I
++ *	CONFIG_PLATFORM_ARM_SUN7I
++ *	CONFIG_PLATFORM_ARM_SUN8I
++ */
++#include <drv_types.h>
++#include <mach/sys_config.h>
++#ifdef CONFIG_GPIO_WAKEUP
++#include <linux/gpio.h>
++#endif
++
++#ifdef CONFIG_MMC
++static int sdc_id = -1;
++static signed int gpio_eint_wlan = -1;
++static u32 eint_wlan_handle = 0;
++
++#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
++extern void sw_mci_rescan_card(unsigned id, unsigned insert);
++#elif defined(CONFIG_PLATFORM_ARM_SUN8I)
++extern void sunxi_mci_rescan_card(unsigned id, unsigned insert);
++#endif
++
++#ifdef CONFIG_PLATFORM_ARM_SUN8I_W5P1
++extern int get_rf_mod_type(void);
++#else
++extern int wifi_pm_get_mod_type(void);
++#endif
++
++extern void wifi_pm_power(int on);
++#ifdef CONFIG_GPIO_WAKEUP
++extern unsigned int oob_irq;
++#endif
++#endif /* CONFIG_MMC */
++
++/*
++ * Return:
++ *	0:	power on successfully
++ *	others: power on failed
++ */
++int platform_wifi_power_on(void)
++{
++	int ret = 0;
++
++#ifdef CONFIG_MMC
++	{
++		script_item_u val;
++		script_item_value_type_e type;
++
++#ifdef CONFIG_PLATFORM_ARM_SUN8I_W5P1
++		unsigned int mod_sel = get_rf_mod_type();
++#else
++		unsigned int mod_sel = wifi_pm_get_mod_type();
++#endif
++
++		type = script_get_item("wifi_para", "wifi_sdc_id", &val);
++		if (SCIRPT_ITEM_VALUE_TYPE_INT != type) {
++			RTW_INFO("get wifi_sdc_id failed\n");
++			ret = -1;
++		} else {
++			sdc_id = val.val;
++			RTW_INFO("----- %s sdc_id: %d, mod_sel: %d\n", __FUNCTION__, sdc_id, mod_sel);
++
++#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
++			sw_mci_rescan_card(sdc_id, 1);
++#elif defined(CONFIG_PLATFORM_ARM_SUN8I)
++			sunxi_mci_rescan_card(sdc_id, 1);
++#endif
++			mdelay(100);
++			wifi_pm_power(1);
++
++			RTW_INFO("%s: power up, rescan card.\n", __FUNCTION__);
++		}
++
++#ifdef CONFIG_GPIO_WAKEUP
++#ifdef CONFIG_PLATFORM_ARM_SUN8I_W5P1
++		type = script_get_item("wifi_para", "wl_host_wake", &val);
++#else
++#ifdef CONFIG_RTL8723B
++		type = script_get_item("wifi_para", "rtl8723bs_wl_host_wake", &val);
++#endif
++#ifdef CONFIG_RTL8188E
++		type = script_get_item("wifi_para", "rtl8189es_host_wake", &val);
++#endif
++#endif /* CONFIG_PLATFORM_ARM_SUN8I_W5P1 */
++		if (SCIRPT_ITEM_VALUE_TYPE_PIO != type) {
++			RTW_INFO("No definition of wake up host PIN\n");
++			ret = -1;
++		} else {
++			gpio_eint_wlan = val.gpio.gpio;
++#ifdef CONFIG_PLATFORM_ARM_SUN8I
++			oob_irq = gpio_to_irq(gpio_eint_wlan);
++#endif
++		}
++#endif /* CONFIG_GPIO_WAKEUP */
++	}
++#endif /* CONFIG_MMC */
++
++	return ret;
++}
++
++void platform_wifi_power_off(void)
++{
++#ifdef CONFIG_MMC
++#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
++	sw_mci_rescan_card(sdc_id, 0);
++#elif defined(CONFIG_PLATFORM_ARM_SUN8I)
++	sunxi_mci_rescan_card(sdc_id, 0);
++#endif
++	mdelay(100);
++	wifi_pm_power(0);
++
++	RTW_INFO("%s: remove card, power off.\n", __FUNCTION__);
++#endif /* CONFIG_MMC */
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ARM_SUNxI_sdio.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ARM_SUNxI_sdio.c
+new file mode 100644
+index 000000000..795b7e7f7
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ARM_SUNxI_sdio.c
+@@ -0,0 +1,90 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#include <drv_types.h>
++
++#ifdef CONFIG_MMC_SUNXI_POWER_CONTROL
++#ifdef CONFIG_WITS_EVB_V13
++	#define SDIOID	0
++#else /* !CONFIG_WITS_EVB_V13 */
++	#define SDIOID (CONFIG_CHIP_ID == 1123 ? 3 : 1)
++#endif /* !CONFIG_WITS_EVB_V13 */
++
++#define SUNXI_SDIO_WIFI_NUM_RTL8189ES  10
++extern void sunximmc_rescan_card(unsigned id, unsigned insert);
++extern int mmc_pm_get_mod_type(void);
++extern int mmc_pm_gpio_ctrl(char *name, int level);
++/*
++ *	rtl8189es_shdn	= port:PH09<1><default><default><0>
++ *	rtl8189es_wakeup	= port:PH10<1><default><default><1>
++ *	rtl8189es_vdd_en  = port:PH11<1><default><default><0>
++ *	rtl8189es_vcc_en  = port:PH12<1><default><default><0>
++ */
++
++int rtl8189es_sdio_powerup(void)
++{
++	mmc_pm_gpio_ctrl("rtl8189es_vdd_en", 1);
++	udelay(100);
++	mmc_pm_gpio_ctrl("rtl8189es_vcc_en", 1);
++	udelay(50);
++	mmc_pm_gpio_ctrl("rtl8189es_shdn", 1);
++	return 0;
++}
++
++int rtl8189es_sdio_poweroff(void)
++{
++	mmc_pm_gpio_ctrl("rtl8189es_shdn", 0);
++	mmc_pm_gpio_ctrl("rtl8189es_vcc_en", 0);
++	mmc_pm_gpio_ctrl("rtl8189es_vdd_en", 0);
++	return 0;
++}
++#endif /* CONFIG_MMC_SUNXI_POWER_CONTROL */
++
++/*
++ * Return:
++ *	0:	power on successfully
++ *	others:	power on failed
++ */
++int platform_wifi_power_on(void)
++{
++	int ret = 0;
++#ifdef CONFIG_MMC_SUNXI_POWER_CONTROL
++	unsigned int mod_sel = mmc_pm_get_mod_type();
++#endif /* CONFIG_MMC_SUNXI_POWER_CONTROL */
++
++
++#ifdef CONFIG_MMC_SUNXI_POWER_CONTROL
++	if (mod_sel == SUNXI_SDIO_WIFI_NUM_RTL8189ES) {
++		rtl8189es_sdio_powerup();
++		sunximmc_rescan_card(SDIOID, 1);
++		printk("[rtl8189es] %s: power up, rescan card.\n", __FUNCTION__);
++	} else {
++		ret = -1;
++		printk("[rtl8189es] %s: mod_sel = %d is incorrect.\n", __FUNCTION__, mod_sel);
++	}
++#endif /* CONFIG_MMC_SUNXI_POWER_CONTROL */
++
++	return ret;
++}
++
++void platform_wifi_power_off(void)
++{
++#ifdef CONFIG_MMC_SUNXI_POWER_CONTROL
++	sunximmc_rescan_card(SDIOID, 0);
++#ifdef CONFIG_RTL8188E
++	rtl8189es_sdio_poweroff();
++	printk("[rtl8189es] %s: remove card, power off.\n", __FUNCTION__);
++#endif /* CONFIG_RTL8188E */
++#endif /* CONFIG_MMC_SUNXI_POWER_CONTROL */
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ARM_SUNxI_usb.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ARM_SUNxI_usb.c
+new file mode 100644
+index 000000000..9c2abc4f6
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ARM_SUNxI_usb.c
+@@ -0,0 +1,136 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*
++ * Description:
++ *	This file can be applied to following platforms:
++ *	CONFIG_PLATFORM_ARM_SUNXI Series platform
++ *
++ */
++
++#include <drv_types.h>
++#include <mach/sys_config.h>
++
++#ifdef CONFIG_PLATFORM_ARM_SUNxI
++extern int sw_usb_disable_hcd(__u32 usbc_no);
++extern int sw_usb_enable_hcd(__u32 usbc_no);
++static int usb_wifi_host = 2;
++#endif
++
++#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
++extern int sw_usb_disable_hcd(__u32 usbc_no);
++extern int sw_usb_enable_hcd(__u32 usbc_no);
++extern void wifi_pm_power(int on);
++static script_item_u item;
++#endif
++
++#ifdef CONFIG_PLATFORM_ARM_SUN8I
++extern int sunxi_usb_disable_hcd(__u32 usbc_no);
++extern int sunxi_usb_enable_hcd(__u32 usbc_no);
++extern void wifi_pm_power(int on);
++static script_item_u item;
++#endif
++
++
++int platform_wifi_power_on(void)
++{
++	int ret = 0;
++
++#ifdef CONFIG_PLATFORM_ARM_SUNxI
++#ifndef CONFIG_RTL8723A
++	{
++		/* ----------get usb_wifi_usbc_num------------- */
++		ret = script_parser_fetch("usb_wifi_para", "usb_wifi_usbc_num", (int *)&usb_wifi_host, 64);
++		if (ret != 0) {
++			RTW_INFO("ERR: script_parser_fetch usb_wifi_usbc_num failed\n");
++			ret = -ENOMEM;
++			goto exit;
++		}
++		RTW_INFO("sw_usb_enable_hcd: usbc_num = %d\n", usb_wifi_host);
++		sw_usb_enable_hcd(usb_wifi_host);
++	}
++#endif /* CONFIG_RTL8723A */
++#endif /* CONFIG_PLATFORM_ARM_SUNxI */
++
++#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
++	{
++		script_item_value_type_e type;
++
++		type = script_get_item("wifi_para", "wifi_usbc_id", &item);
++		if (SCIRPT_ITEM_VALUE_TYPE_INT != type) {
++			printk("ERR: script_get_item wifi_usbc_id failed\n");
++			ret = -ENOMEM;
++			goto exit;
++		}
++
++		printk("sw_usb_enable_hcd: usbc_num = %d\n", item.val);
++		wifi_pm_power(1);
++		mdelay(10);
++
++#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B))
++		sw_usb_enable_hcd(item.val);
++#endif
++	}
++#endif /* defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) */
++
++#if defined(CONFIG_PLATFORM_ARM_SUN8I)
++	{
++		script_item_value_type_e type;
++
++		type = script_get_item("wifi_para", "wifi_usbc_id", &item);
++		if (SCIRPT_ITEM_VALUE_TYPE_INT != type) {
++			printk("ERR: script_get_item wifi_usbc_id failed\n");
++			ret = -ENOMEM;
++			goto exit;
++		}
++
++		printk("sw_usb_enable_hcd: usbc_num = %d\n", item.val);
++		wifi_pm_power(1);
++		mdelay(10);
++
++#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B))
++		sunxi_usb_enable_hcd(item.val);
++#endif
++	}
++#endif /* CONFIG_PLATFORM_ARM_SUN8I */
++
++exit:
++	return ret;
++}
++
++void platform_wifi_power_off(void)
++{
++
++#ifdef CONFIG_PLATFORM_ARM_SUNxI
++#ifndef CONFIG_RTL8723A
++	RTW_INFO("sw_usb_disable_hcd: usbc_num = %d\n", usb_wifi_host);
++	sw_usb_disable_hcd(usb_wifi_host);
++#endif /* ifndef CONFIG_RTL8723A */
++#endif /* CONFIG_PLATFORM_ARM_SUNxI */
++
++#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
++	#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B))
++	sw_usb_disable_hcd(item.val);
++	#endif
++	wifi_pm_power(0);
++#endif /* defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) */
++
++#if defined(CONFIG_PLATFORM_ARM_SUN8I)
++	#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B))
++	sunxi_usb_disable_hcd(item.val);
++	#endif
++	wifi_pm_power(0);
++#endif /* defined(CONFIG_PLATFORM_ARM_SUN8I) */
++
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ARM_WMT_sdio.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ARM_WMT_sdio.c
+new file mode 100644
+index 000000000..d85002c15
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ARM_WMT_sdio.c
+@@ -0,0 +1,46 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#include <drv_types.h>
++#include <mach/wmt_iomux.h>
++#include <linux/gpio.h>
++
++extern void wmt_detect_sdio2(void);
++extern void force_remove_sdio2(void);
++
++int platform_wifi_power_on(void)
++{
++	int err = 0;
++	err = gpio_request(WMT_PIN_GP62_SUSGPIO1, "wifi_chip_en");
++	if (err < 0) {
++		printk("request gpio for rtl8188eu failed!\n");
++		return err;
++	}
++	gpio_direction_output(WMT_PIN_GP62_SUSGPIO1, 0);/* pull sus_gpio1 to 0 to open vcc_wifi. */
++	printk("power on rtl8189.\n");
++	msleep(500);
++	wmt_detect_sdio2();
++	printk("[rtl8189es] %s: new card, power on.\n", __FUNCTION__);
++	return err;
++}
++
++void platform_wifi_power_off(void)
++{
++	force_remove_sdio2();
++
++	gpio_direction_output(WMT_PIN_GP62_SUSGPIO1, 1);/* pull sus_gpio1 to 1 to close vcc_wifi. */
++	printk("power off rtl8189.\n");
++	gpio_free(WMT_PIN_GP62_SUSGPIO1);
++	printk("[rtl8189es] %s: remove card, power off.\n", __FUNCTION__);
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_RTK_DMP_usb.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_RTK_DMP_usb.c
+new file mode 100644
+index 000000000..cb740b2ee
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_RTK_DMP_usb.c
+@@ -0,0 +1,30 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#include <drv_types.h>
++
++int platform_wifi_power_on(void)
++{
++	int ret = 0;
++	u32 tmp;
++	tmp = readl((volatile unsigned int *)0xb801a608);
++	tmp &= 0xffffff00;
++	tmp |= 0x55;
++	writel(tmp, (volatile unsigned int *)0xb801a608); /* write dummy register for 1055 */
++	return ret;
++}
++
++void platform_wifi_power_off(void)
++{
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_aml_s905_sdio.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_aml_s905_sdio.c
+new file mode 100644
+index 000000000..334ca03c9
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_aml_s905_sdio.c
+@@ -0,0 +1,54 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2018 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#include <linux/printk.h>		/* pr_info(() */
++#include <linux/delay.h>		/* msleep() */
++#include "platform_aml_s905_sdio.h"	/* sdio_reinit() and etc */
++
++
++/*
++ * Return:
++ *	0:	power on successfully
++ *	others:	power on failed
++ */
++int platform_wifi_power_on(void)
++{
++	int ret = 0;
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
++	ret = wifi_setup_dt();
++	if (ret) {
++		pr_err("%s: setup dt failed!!(%d)\n", __func__, ret);
++		return -1;
++	}
++#endif /* kernel < 3.14.0 */
++
++#if 0 /* Seems redundancy? Already done before insert driver */
++	pr_info("######%s:\n", __func__);
++	extern_wifi_set_enable(0);
++	msleep(500);
++	extern_wifi_set_enable(1);
++	msleep(500);
++	sdio_reinit();
++#endif
++
++	return ret;
++}
++
++void platform_wifi_power_off(void)
++{
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
++	wifi_teardown_dt();
++#endif /* kernel < 3.14.0 */
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_aml_s905_sdio.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_aml_s905_sdio.h
+new file mode 100644
+index 000000000..2b87576dd
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_aml_s905_sdio.h
+@@ -0,0 +1,28 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2018 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __PLATFORM_AML_S905_SDIO_H__
++#define __PLATFORM_AML_S905_SDIO_H__
++
++#include <linux/version.h>	/* Linux vresion */
++
++extern void sdio_reinit(void);
++extern void extern_wifi_set_enable(int is_on);
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
++extern void wifi_teardown_dt(void);
++extern int wifi_setup_dt(void);
++#endif /* kernel < 3.14.0 */
++
++#endif /* __PLATFORM_AML_S905_SDIO_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_arm_act_sdio.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_arm_act_sdio.c
+new file mode 100644
+index 000000000..ad7b6cfed
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_arm_act_sdio.c
+@@ -0,0 +1,53 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*
++ * Description:
++ *	This file can be applied to following platforms:
++ *    CONFIG_PLATFORM_ACTIONS_ATM703X
++ */
++#include <drv_types.h>
++
++#ifdef CONFIG_PLATFORM_ACTIONS_ATM705X
++extern int acts_wifi_init(void);
++extern void acts_wifi_cleanup(void);
++#endif
++
++/*
++ * Return:
++ *	0:	power on successfully
++ *	others: power on failed
++ */
++int platform_wifi_power_on(void)
++{
++	int ret = 0;
++
++#ifdef CONFIG_PLATFORM_ACTIONS_ATM705X
++	ret = acts_wifi_init();
++	if (unlikely(ret < 0)) {
++		pr_err("%s Failed to register the power control driver.\n", __FUNCTION__);
++		goto exit;
++	}
++#endif
++
++exit:
++	return ret;
++}
++
++void platform_wifi_power_off(void)
++{
++#ifdef CONFIG_PLATFORM_ACTIONS_ATM705X
++	acts_wifi_cleanup();
++#endif
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_hisilicon_hi3798_sdio.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_hisilicon_hi3798_sdio.c
+new file mode 100644
+index 000000000..11a08320e
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_hisilicon_hi3798_sdio.c
+@@ -0,0 +1,110 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2017 - 2018 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#include <linux/delay.h>		/* mdelay() */
++#include <mach/hardware.h>		/* __io_address(), readl(), writel() */
++#include "platform_hisilicon_hi3798_sdio.h"	/* HI_S32() and etc. */
++
++typedef enum hi_GPIO_DIR_E {
++	HI_DIR_OUT = 0,
++	HI_DIR_IN  = 1,
++} HI_GPIO_DIR_E;
++
++#define RTL_REG_ON_GPIO		(4*8 + 3)
++
++#define REG_BASE_CTRL		__io_address(0xf8a20008)
++
++int gpio_wlan_reg_on = RTL_REG_ON_GPIO;
++#if 0
++module_param(gpio_wlan_reg_on, uint, 0644);
++MODULE_PARM_DESC(gpio_wlan_reg_on, "wlan reg_on gpio num (default:gpio4_3)");
++#endif
++
++static int hi_gpio_set_value(u32 gpio, u32 value)
++{
++	HI_S32 s32Status;
++
++	s32Status = HI_DRV_GPIO_SetDirBit(gpio, HI_DIR_OUT);
++	if (s32Status != HI_SUCCESS) {
++		pr_err("gpio(%d) HI_DRV_GPIO_SetDirBit HI_DIR_OUT failed\n",
++			gpio);
++		return -1;
++	}
++
++	s32Status = HI_DRV_GPIO_WriteBit(gpio, value);
++	if (s32Status != HI_SUCCESS) {
++		pr_err("gpio(%d) HI_DRV_GPIO_WriteBit value(%d) failed\n",
++			gpio, value);
++		return -1;
++	}
++
++	return 0;
++}
++
++static int hisi_wlan_set_carddetect(bool present)
++{
++	u32 regval;
++	u32 mask;
++
++
++#ifndef CONFIG_HISI_SDIO_ID
++	return;
++#endif
++	pr_info("SDIO ID=%d\n", CONFIG_HISI_SDIO_ID);
++#if (CONFIG_HISI_SDIO_ID == 1)
++	mask = 1;
++#elif (CONFIG_HISI_SDIO_ID == 0)
++	mask = 2;
++#endif
++
++	regval = readl(REG_BASE_CTRL);
++	if (present) {
++		pr_info("====== Card detection to detect SDIO card! ======\n");
++		/* set card_detect low to detect card */
++		regval |= mask;
++	} else {
++		pr_info("====== Card detection to remove SDIO card! ======\n");
++		/* set card_detect high to remove card */
++		regval &= ~(mask);
++	}
++	writel(regval, REG_BASE_CTRL);
++
++	return 0;
++}
++
++/*
++ * Return:
++ *	0:	power on successfully
++ *	others: power on failed
++ */
++int platform_wifi_power_on(void)
++{
++	int ret = 0;
++
++
++	hi_gpio_set_value(gpio_wlan_reg_on, 1);
++	mdelay(100);
++	hisi_wlan_set_carddetect(1);
++	mdelay(2000);
++	pr_info("======== set_carddetect delay 2s! ========\n");
++
++	return ret;
++}
++
++void platform_wifi_power_off(void)
++{
++	hisi_wlan_set_carddetect(0);
++	mdelay(100);
++	hi_gpio_set_value(gpio_wlan_reg_on, 0);
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_hisilicon_hi3798_sdio.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_hisilicon_hi3798_sdio.h
+new file mode 100644
+index 000000000..1ad42406f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_hisilicon_hi3798_sdio.h
+@@ -0,0 +1,28 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2017 - 2018 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __PLATFORM_HISILICON_HI3798_SDIO_H__
++#define __PLATFORM_HISILICON_HI3798_SDIO_H__
++
++typedef unsigned int	HI_U32;
++
++typedef int		HI_S32;
++
++#define HI_SUCCESS	0
++#define HI_FAILURE	(-1)
++
++extern HI_S32 HI_DRV_GPIO_SetDirBit(HI_U32 u32GpioNo, HI_U32 u32DirBit);
++extern HI_S32 HI_DRV_GPIO_WriteBit(HI_U32 u32GpioNo, HI_U32 u32BitValue);
++
++#endif /* __PLATFORM_HISILICON_HI3798_SDIO_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ops.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ops.c
+new file mode 100644
+index 000000000..a322e258f
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ops.c
+@@ -0,0 +1,34 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef CONFIG_PLATFORM_OPS
++/*
++ * Return:
++ *	0:	power on successfully
++ *	others: power on failed
++ */
++extern void rtw_wifi_gpio_wlan_ctrl(int onoff);
++int platform_wifi_power_on(void)
++{
++	int ret = 0;
++  rtw_wifi_gpio_wlan_ctrl(1);
++
++	return ret;
++}
++
++void platform_wifi_power_off(void)
++{
++  rtw_wifi_gpio_wlan_ctrl(0);
++}
++#endif /* !CONFIG_PLATFORM_OPS */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ops.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ops.h
+new file mode 100644
+index 000000000..12caf3c85
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_ops.h
+@@ -0,0 +1,26 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __PLATFORM_OPS_H__
++#define __PLATFORM_OPS_H__
++
++/*
++ * Return:
++ *	0:	power on successfully
++ *	others: power on failed
++ */
++int platform_wifi_power_on(void);
++void platform_wifi_power_off(void);
++
++#endif /* __PLATFORM_OPS_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_sprd_sdio.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_sprd_sdio.c
+new file mode 100644
+index 000000000..34061d05d
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_sprd_sdio.c
+@@ -0,0 +1,84 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#include <drv_types.h>
++
++extern void sdhci_bus_scan(void);
++#ifndef ANDROID_2X
++extern int sdhci_device_attached(void);
++#endif
++
++/*
++ * Return:
++ *	0:	power on successfully
++ *	others:	power on failed
++ */
++int platform_wifi_power_on(void)
++{
++	int ret = 0;
++
++
++#ifdef CONFIG_RTL8188E
++	rtw_wifi_gpio_wlan_ctrl(WLAN_POWER_ON);
++#endif /* CONFIG_RTL8188E */
++
++	/* Pull up pwd pin, make wifi leave power down mode. */
++	rtw_wifi_gpio_init();
++	rtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_ON);
++
++#if (MP_DRIVER == 1) && (defined(CONFIG_RTL8723A) || defined(CONFIG_RTL8723B))
++	/* Pull up BT reset pin. */
++	rtw_wifi_gpio_wlan_ctrl(WLAN_BT_PWDN_ON);
++#endif
++	rtw_mdelay_os(5);
++
++	sdhci_bus_scan();
++#ifdef CONFIG_RTL8723B
++	/* YJ,test,130305 */
++	rtw_mdelay_os(1000);
++#endif
++#ifdef ANDROID_2X
++	rtw_mdelay_os(200);
++#else /* !ANDROID_2X */
++	if (1) {
++		int i = 0;
++
++		for (i = 0; i <= 50; i++) {
++			msleep(10);
++			if (sdhci_device_attached())
++				break;
++			printk("%s delay times:%d\n", __func__, i);
++		}
++	}
++#endif /* !ANDROID_2X */
++
++	return ret;
++}
++
++void platform_wifi_power_off(void)
++{
++	/* Pull down pwd pin, make wifi enter power down mode. */
++	rtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_OFF);
++	rtw_mdelay_os(5);
++	rtw_wifi_gpio_deinit();
++
++#ifdef CONFIG_RTL8188E
++	rtw_wifi_gpio_wlan_ctrl(WLAN_POWER_OFF);
++#endif /* CONFIG_RTL8188E */
++
++#ifdef CONFIG_WOWLAN
++	if (mmc_host)
++		mmc_host->pm_flags &= ~MMC_PM_KEEP_POWER;
++#endif /* CONFIG_WOWLAN */
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_zte_zx296716_sdio.c b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_zte_zx296716_sdio.c
+new file mode 100644
+index 000000000..472d24d85
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_zte_zx296716_sdio.c
+@@ -0,0 +1,53 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2018 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#include <linux/printk.h>		/* pr_info(() */
++#include <linux/delay.h>		/* msleep() */
++#include "platform_zte_zx296716_sdio.h"	/* sdio_reinit() and etc */
++
++
++/*
++ * Return:
++ *	0:	power on successfully
++ *	others:	power on failed
++ */
++int platform_wifi_power_on(void)
++{
++	int ret = 0;
++
++	pr_info("######%s: disable--1--\n", __func__);
++	extern_wifi_set_enable(0);
++	/*msleep(500);*/ /* add in function:extern_wifi_set_enable */
++	pr_info("######%s: enable--2---\n", __func__);
++	extern_wifi_set_enable(1);
++	/*msleep(500);*/
++	sdio_reinit();
++
++	return ret;
++}
++
++void platform_wifi_power_off(void)
++{
++	int card_val;
++
++	pr_info("######%s:\n", __func__);
++#ifdef CONFIG_A16T03_BOARD
++	card_val = sdio_host_is_null();
++	if (card_val)
++		remove_card();
++#endif /* CONFIG_A16T03_BOARD */
++	extern_wifi_set_enable(0);
++
++	/*msleep(500);*/
++}
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_zte_zx296716_sdio.h b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_zte_zx296716_sdio.h
+new file mode 100644
+index 000000000..3a4fba1a5
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/platform/platform_zte_zx296716_sdio.h
+@@ -0,0 +1,25 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2018 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __PLATFORM_ZTE_ZX296716_SDIO_H__
++#define __PLATFORM_ZTE_ZX296716_SDIO_H__
++
++extern void sdio_reinit(void);
++extern void extern_wifi_set_enable(int val);
++#ifdef CONFIG_A16T03_BOARD
++extern int sdio_host_is_null(void);
++extern void remove_card(void);
++#endif /* CONFIG_A16T03_BOARD */
++
++#endif /* __PLATFORM_ZTE_ZX296716_SDIO_H__ */
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/runwpa b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/runwpa
+new file mode 100644
+index 000000000..f825e8bdb
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/runwpa
+@@ -0,0 +1,20 @@
++#!/bin/bash
++
++if [ "`which iwconfig`" = "" ] ; then 
++	echo "WARNING:Wireless tool not exist!"
++	echo "        Please install it!"
++	exit
++else
++	if [ `uname -r | cut -d. -f2` -eq 4 ]; then
++		wpa_supplicant -D ipw -c wpa1.conf -i wlan0	
++	else
++	if [ `iwconfig -v |awk '{print $4}' | head -n 1` -lt  18 ] ; then
++		wpa_supplicant -D ipw -c wpa1.conf -i wlan0  
++	else	  
++		wpa_supplicant -D wext -c wpa1.conf -i wlan0 
++	fi
++
++	fi
++fi
++
++
+diff --git a/module_drivers/drivers/net/wireless/realtek/rtl8723ds/wlan0dhcp b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/wlan0dhcp
+new file mode 100644
+index 000000000..60433829c
+--- /dev/null
++++ b/module_drivers/drivers/net/wireless/realtek/rtl8723ds/wlan0dhcp
+@@ -0,0 +1,16 @@
++#!/bin/bash
++
++var0=`ps aux|awk '/dhclient wlan0/'|awk '$11!="awk"{print $2}'`
++
++kill $var0
++cp ifcfg-wlan0 /etc/sysconfig/network-scripts/
++
++dhclient wlan0
++
++var1=`ifconfig wlan0 |awk '/inet/{print $2}'|awk -F: '{print $2}'`
++
++
++rm -f /etc/sysconfig/network-scripts/ifcfg-wlan0
++
++echo "get ip: $var1"
++
+diff --git a/module_drivers/drivers/pinctrl/Kconfig b/module_drivers/drivers/pinctrl/Kconfig
+new file mode 100644
+index 000000000..95cf13d1b
+--- /dev/null
++++ b/module_drivers/drivers/pinctrl/Kconfig
+@@ -0,0 +1,16 @@
++
++config PINCTRL_INGENIC_V2
++	bool "Pinctrl driver for the Ingenic X2000/X1600 SoCs"
++	default y
++	depends on OF
++	depends on MIPS || COMPILE_TEST
++	select GENERIC_PINCONF
++	select GENERIC_PINCTRL_GROUPS
++	select GENERIC_PINMUX_FUNCTIONS
++	select GPIOLIB
++	select GPIOLIB_IRQCHIP
++	select REGMAP_MMIO
++
++config MULTI_VGPIO_INGENIC
++	   bool "multiple input lineout to signle output"
++
+diff --git a/module_drivers/drivers/pinctrl/Makefile b/module_drivers/drivers/pinctrl/Makefile
+new file mode 100644
+index 000000000..27f9447ad
+--- /dev/null
++++ b/module_drivers/drivers/pinctrl/Makefile
+@@ -0,0 +1,3 @@
++ccflags-y := -I$(srctree)/drivers/pinctrl/
++obj-$(CONFIG_PINCTRL_INGENIC_V2)   += pinctrl-ingenic.o
++obj-$(CONFIG_MULTI_VGPIO_INGENIC)   += multi-vgpio.o
+diff --git a/module_drivers/drivers/pinctrl/multi-vgpio.c b/module_drivers/drivers/pinctrl/multi-vgpio.c
+new file mode 100644
+index 000000000..e552005ca
+--- /dev/null
++++ b/module_drivers/drivers/pinctrl/multi-vgpio.c
+@@ -0,0 +1,168 @@
++#include <linux/module.h>
++#include <linux/io.h>
++#include <linux/gpio.h>
++#include <linux/of_irq.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++
++/*
++ * multiple input lineout to signle output
++ * dts sample
++ charger_en:vgpa {
++ compatible = "ingenic,multi-vgpio";
++ status = "okay";
++ gpio-controller;
++ #gpio-cells = <2>;
++ ingenic,real-gpio = <&gpd 2 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++ ingenic,count = <2>;
++ ingenic,name = "vgpb";
++ };
++
++ *
++ *  in0 \
++ *       lineout -- out
++ *  in1 /
++ *
++ *  gpio out LOW:
++    Out: GPIO_ACTIVE_HIGH  In: GPIO_ACTIVE_LOW
++	Out: GPIO_ACTIVE_LOW   In: GPIO_ACTIVE_HIGH
++ *  gpio out HIGH:
++    Out: GPIO_ACTIVE_HIGH  In: GPIO_ACTIVE_HIGH
++	Out: GPIO_ACTIVE_LOW   In: GPIO_ACTIVE_LOW
++ */
++
++
++struct multi_vgpio
++{
++	struct gpio_chip gc;
++	unsigned int value;
++	int in_count;
++	const char *name;
++	struct gpio_desc *gpiod_real;
++};
++
++static int multi_vgpio_get_direction(struct gpio_chip *gc, unsigned offset)
++{
++	struct multi_vgpio *priv = container_of(gc,struct multi_vgpio,gc);
++	return gpiod_get_direction(priv->gpiod_real);
++}
++
++static int multi_vgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
++{
++	struct multi_vgpio *priv = container_of(gc,struct multi_vgpio,gc);
++	return gpiod_get_value(priv->gpiod_real);
++}
++
++static int multi_vgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
++{
++	struct multi_vgpio *priv = container_of(gc,struct multi_vgpio,gc);
++	return gpiod_direction_output(priv->gpiod_real,val);
++}
++
++static int multi_vgpio_request(struct gpio_chip *gc, unsigned int pins)
++{
++	struct multi_vgpio *priv = container_of(gc,struct multi_vgpio,gc);
++	if(pins < priv->in_count)
++		return 0;
++	return -EINVAL;
++}
++
++static void multi_vgpio_set(struct gpio_chip *gc,unsigned pin, int value)
++{
++	struct multi_vgpio *priv = container_of(gc,struct multi_vgpio,gc);
++	return gpiod_set_value(priv->gpiod_real,value);
++}
++
++static int multi_vgpio_get(struct gpio_chip *gc, unsigned pin)
++{
++	struct multi_vgpio *priv = container_of(gc,struct multi_vgpio,gc);
++	return gpiod_get_value(priv->gpiod_real);
++}
++
++static int ingenic_multi_vgpio_probe(struct platform_device *pdev)
++{
++	struct multi_vgpio *priv;
++	struct device_node *np = pdev->dev.of_node;
++	int rc;
++
++	priv = devm_kzalloc(&pdev->dev,sizeof(*priv),GFP_KERNEL);
++	if(!priv)
++		return -ENOMEM;
++
++	rc = of_property_read_string_index(np,"ingenic,name",0,&priv->name);
++	if(rc != 0)
++	{
++		priv->name = "vgpio";
++	}
++
++	rc = of_property_read_u32(np, "ingenic,count", &priv->in_count);
++	if(rc != 0)
++	{
++		priv->in_count = 2;
++	}
++
++	priv->gpiod_real = devm_gpiod_get_optional(&pdev->dev,"ingenic,real", GPIOD_ASIS);
++	if(IS_ERR_OR_NULL(priv->gpiod_real))
++	{
++		dev_err(&pdev->dev,"real gpio request failed!\n");
++		return -ENODEV;
++	}
++
++	priv->gc.dev = &pdev->dev;
++	priv->gc.label = priv->name;
++	priv->gc.base = -1;
++	priv->gc.request = multi_vgpio_request;
++
++	priv->gc.direction_input = multi_vgpio_dir_in;
++	priv->gc.direction_output = multi_vgpio_dir_out;
++	priv->gc.set = multi_vgpio_set;
++	priv->gc.get = multi_vgpio_get;
++
++	priv->gc.get_direction = multi_vgpio_get_direction;
++	priv->gc.ngpio = priv->in_count;
++	priv->gc.owner = THIS_MODULE;
++	priv->gc.can_sleep = 0;
++	platform_set_drvdata(pdev, priv);
++	printk("multi-vgpio register ok!\n");
++	return gpiochip_add(&priv->gc);
++}
++
++static int ingenic_multi_vgpio_remove(struct platform_device *pdev)
++{
++	struct multi_vgpio *priv = platform_get_drvdata(pdev);
++	gpiochip_remove(&priv->gc);
++	return 0;
++}
++
++static const struct of_device_id mult_vgpio_ids[] = {
++	{.compatible	= "ingenic,multi-vgpio"},
++	{},
++};
++
++static struct platform_driver multi_vgpio_driver = {
++	.probe = ingenic_multi_vgpio_probe,
++	.remove = ingenic_multi_vgpio_remove,
++	.driver = {
++		.name = "ingenic-multi-vgpio",
++		.owner = THIS_MODULE,
++		.of_match_table = mult_vgpio_ids,
++	},
++};
++
++
++static int __init multi_vgpio_drv_init(void)
++{
++	return platform_driver_register(&multi_vgpio_driver);
++}
++
++static void __exit multi_vgpio_drv_exit(void)
++{
++	platform_driver_unregister(&multi_vgpio_driver);
++}
++
++postcore_initcall(multi_vgpio_drv_init);
++module_exit(multi_vgpio_drv_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Stephen <stephen@ingenic.com>");
++MODULE_DESCRIPTION("VIRTUAL GPIO driver");
+diff --git a/module_drivers/drivers/pinctrl/pinctrl-ingenic.c b/module_drivers/drivers/pinctrl/pinctrl-ingenic.c
+new file mode 100644
+index 000000000..6d3898ac7
+--- /dev/null
++++ b/module_drivers/drivers/pinctrl/pinctrl-ingenic.c
+@@ -0,0 +1,2056 @@
++/*
++ * pinctrl/ingenic/pinctrl-ingenic.c
++ *
++ * Copyright 2015 Ingenic Semiconductor Co.,Ltd
++ *
++ * Author: cli <chen.li@ingenic.com>
++ *
++ * redistribute from drivers/pinctrl/pinctrl-samsung.c
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/syscore_ops.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/gpio.h>
++#include <linux/of_irq.h>
++#include <linux/of.h>
++#include <linux/pinctrl/pinctrl.h>
++#include <linux/pinctrl/pinmux.h>
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/pinctrl/pinconf-generic.h>
++#include <linux/slab.h>
++#include <linux/gpio/driver.h>
++#include <dt-bindings/gpio/ingenic-gpio.h>
++
++#include "pinctrl-ingenic.h"
++
++static struct ingenic_pinctrl *gpctl = NULL;
++static const struct ingenic_priv common_priv_data[];
++static const struct of_device_id ingenic_pinctrl_dt_match[];
++
++static void ingenic_gpio_set_func_normal(struct ingenic_gpio_chip *chip,
++		enum gpio_function func, u32 pins)
++{
++	unsigned long flags, func_tmp = func;
++	spin_lock_irqsave(&chip->lock, flags);
++	if(chip->pctl->priv->dual_edge_interrupt){
++		if (func & 0x10)
++			ingenic_gpio_writel(chip, PxEDGS, pins);
++		else
++			ingenic_gpio_writel(chip, PxEDGC, pins);
++	} else {
++		if(func_tmp & 0x10){
++			func = GPIO_INT_FE;
++		}
++	}
++	if (func & 0x8)
++		ingenic_gpio_writel(chip, PxINTS, pins);
++	else
++		ingenic_gpio_writel(chip, PxINTC, pins);
++	if (func & 0x4)
++		ingenic_gpio_writel(chip, PxMSKS, pins);
++	else
++		ingenic_gpio_writel(chip, PxMSKC, pins);
++
++	if (func & 0x2)
++		ingenic_gpio_writel(chip, PxPAT1S, pins);
++	else
++		ingenic_gpio_writel(chip, PxPAT1C, pins);
++
++	if(chip->pctl->priv->dual_edge_interrupt){
++		if (func & 0x1)
++			ingenic_gpio_writel(chip, PxPAT0S, pins);
++		else
++			ingenic_gpio_writel(chip, PxPAT0C, pins);
++	} else {
++		if(func_tmp & 0x10){
++			int old, new, timeout = 10;
++			do {
++				old = ingenic_gpio_readl(chip, PxPIN) & pins;
++				if (old)
++					func = GPIO_INT_FE;
++				else
++					func = GPIO_INT_RE;
++				if (func & 0x1)
++					ingenic_gpio_writel(chip, PxPAT0S, pins);
++				else
++					ingenic_gpio_writel(chip, PxPAT0C, pins);
++				new = ingenic_gpio_readl(chip, PxPIN) & pins;
++				timeout --;
++			}while(old != new && timeout);
++			if(!timeout)
++				pr_err("pins %x function %d failed\n", pins, func);
++		} else {
++			if (func & 0x1)
++				ingenic_gpio_writel(chip, PxPAT0S, pins);
++			else
++				ingenic_gpio_writel(chip, PxPAT0C, pins);
++		}
++	}
++	ingenic_gpio_writel(chip, PxFLGC, pins);
++	spin_unlock_irqrestore(&chip->lock, flags);
++}
++
++static void ingenic_gpio_fill_func_shadow(struct ingenic_gpio_chip *chip,
++		enum gpio_function func, u32 pins)
++{
++	if (func & 0x8)
++		ingenic_gpio_shadow_fill(chip, PxINTS, pins);
++	else
++		ingenic_gpio_shadow_fill(chip, PxINTC, pins);
++	if (func & 0x4)
++		ingenic_gpio_shadow_fill(chip, PxMSKS, pins);
++	else
++		ingenic_gpio_shadow_fill(chip, PxMSKC, pins);
++	if (func & 0x2)
++		ingenic_gpio_shadow_fill(chip, PxPAT1S, pins);
++	else
++		ingenic_gpio_shadow_fill(chip, PxPAT1C, pins);
++	if (func & 0x1)
++		ingenic_gpio_shadow_fill(chip, PxPAT0S, pins);
++	else
++		ingenic_gpio_shadow_fill(chip, PxPAT0C, pins);
++}
++
++static void ingenic_gpio_set_func_shadow(struct ingenic_gpio_chip *chip,
++		enum gpio_function func, u32 pins)
++{
++	struct ingenic_pinctrl *pctl = chip->pctl;
++	unsigned long flags;
++	unsigned long func_tmp = func;
++
++	spin_lock_irqsave(&pctl->shadow_lock, flags);
++
++	if(chip->pctl->priv->dual_edge_interrupt){
++		ingenic_gpio_fill_func_shadow(chip, func, pins);
++		ingenic_gpio_shadow_writel(chip);
++
++		/*No Shadows registers for EDG, set registers directly.*/
++		if (func & 0x10)
++			ingenic_gpio_writel(chip, PxEDGS, pins);
++		else
++			ingenic_gpio_writel(chip, PxEDGC, pins);
++	} else {
++		if(func_tmp & 0x10){
++			int old, new, timeout = 10;
++			do {
++				old = ingenic_gpio_readl(chip, PxPIN) & pins;
++				if (old)
++					func = GPIO_INT_FE;
++				else
++					func = GPIO_INT_RE;
++				ingenic_gpio_fill_func_shadow(chip, func, pins);
++				ingenic_gpio_shadow_writel(chip);
++				new = ingenic_gpio_readl(chip, PxPIN) & pins;
++				timeout --;
++			}while(old != new && timeout);
++			if(!timeout)
++				pr_err("pins %x function %d failed\n",pins, func);
++		} else {
++			ingenic_gpio_fill_func_shadow(chip, func, pins);
++			ingenic_gpio_shadow_writel(chip);
++		}
++	}
++
++	/* clear possible irqs since not enabled by irq core.*/
++	ingenic_gpio_writel(chip, PxFLGC, pins);
++
++	spin_unlock_irqrestore(&pctl->shadow_lock, flags);
++}
++
++/**************************************************************
++ * Set GPIO Function
++ *	chip:		gpio chip
++ *	have_shadow:	soc support shadow register ot not
++ *	func:		function select
++ *	pins:		pins bitmap
++ **************************************************************/
++static void ingenic_gpio_set_func(struct ingenic_gpio_chip *chip,
++		bool have_shadow, enum gpio_function func,
++		u32 pins)
++{
++	if (have_shadow)
++		ingenic_gpio_set_func_shadow(chip, func, pins);
++	else
++		ingenic_gpio_set_func_normal(chip, func, pins);
++}
++
++static void ingenic_gpio_set_pull(struct ingenic_gpio_chip *chip,
++		u32 pins, unsigned int state)
++{
++	const struct ingenic_priv *priv = chip->pctl->priv;
++
++	/*1. try pull_up pull_down hiz settings first.*/
++	if(priv->pull_tristate) {
++		if(state == INGENIC_GPIO_PULLUP) {
++			ingenic_gpio_writel(chip, PxPDC, pins);
++			ingenic_gpio_writel(chip, PxPUS, pins);
++		} else if(state == INGENIC_GPIO_PULLDOWN) {
++			ingenic_gpio_writel(chip, PxPUC, pins);
++			ingenic_gpio_writel(chip, PxPDS, pins);
++		} else if(state == INGENIC_GPIO_HIZ) {
++			ingenic_gpio_writel(chip, PxPUC, pins);
++			ingenic_gpio_writel(chip, PxPDC, pins);
++		}
++		return;
++	}
++
++	/*2. For gpios pullup/pulldown state can not be changed.*/
++	if(priv->pullen_set) {
++		if(state == INGENIC_GPIO_PULLEN) {
++			ingenic_gpio_writel(chip, PxPENS, pins);
++		} else {
++			ingenic_gpio_writel(chip, PxPENC, pins);
++		}
++	} else {
++		if(state == INGENIC_GPIO_PULLEN) {
++			ingenic_gpio_writel(chip, PxPENC, pins);
++		} else {
++			ingenic_gpio_writel(chip, PxPENS, pins);
++		}
++	}
++
++}
++
++static int ingenic_gpio_get_pull_state(struct ingenic_gpio_chip *chip, u32 pins)
++{
++	unsigned int pull_down = 0;
++	unsigned int pull_up = 0;
++	int state = 0;
++
++	pull_down = (ingenic_gpio_readl(chip, PxPD) & BIT(pins)) >> pins;
++	pull_up = (ingenic_gpio_readl(chip, PxPU) & BIT(pins)) >> pins;
++
++	if(pull_down && pull_up) {
++		dev_warn(chip->gc.parent, "Set both pull_up and pull_down on %s %d\n", chip->name, pins);
++	}
++
++	if(pull_down) {
++		state = INGENIC_GPIO_PULLDOWN;
++	} else if(pull_up) {
++		state = INGENIC_GPIO_PULLUP;
++	} else {
++		state = INGENIC_GPIO_HIZ;
++	}
++
++	return state;
++
++}
++/*************************************************************
++ * Set GPIO Input&Interrupt HW filter
++ *	chip:	gpio chip
++ *	pin:	pin num (one pin)
++ *	pinflt:	filter to set
++ *************************************************************/
++static void ingenic_gpio_set_filter(struct ingenic_gpio_chip *chip,
++		u32 pin, u16 pinflt)
++{
++	const struct ingenic_priv *priv = chip->pctl->priv;
++	if (chip->filter_bitmap & BIT(pin))
++		priv->set_filter(chip, pin, pinflt);
++}
++
++static void ingenic_gpio_set_schmitt_enable(struct ingenic_gpio_chip *chip,
++		u32 pin, int enable)
++{
++	const struct ingenic_priv *priv = chip->pctl->priv;
++
++	if(!priv->have_schmit) {
++		/* dev_warn(chip->gc.dev, "Do not support schmit for this chip."); */
++		return;
++	}
++
++	if(enable) {
++		ingenic_gpio_writel(chip, PxSMTS, BIT(pin));
++	} else {
++		ingenic_gpio_writel(chip, PxSMTC, BIT(pin));
++	}
++}
++
++static void ingenic_gpio_set_slew_rate(struct ingenic_gpio_chip *chip,
++		u32 pin, int enable)
++{
++	const struct ingenic_priv *priv = chip->pctl->priv;
++
++	if(!priv->have_slew) {
++		/* dev_warn(chip->gc.dev, "Do not support slew_rate for this chip."); */
++		return;
++	}
++
++	if(enable) {
++		ingenic_gpio_writel(chip, PxSRS, BIT(pin));
++	} else {
++		ingenic_gpio_writel(chip, PxSRC, BIT(pin));
++	}
++}
++
++static void ingenic_gpio_set_drive_strength(struct ingenic_gpio_chip *chip,
++		u32 pin, u16 strength)
++{
++	const struct ingenic_priv *priv = chip->pctl->priv;
++
++	if(!priv->have_ds) {
++		/* dev_warn(chip->gc.dev, "Do not support drive strength settings for this chip."); */
++		return;
++	}
++
++	if(strength > 7)
++		strength = 7;
++
++	if(strength & BIT(0))
++		ingenic_gpio_writel(chip, PXDS0S, BIT(pin));
++	else
++		ingenic_gpio_writel(chip, PXDS0C, BIT(pin));
++
++	if(strength & BIT(1))
++		ingenic_gpio_writel(chip, PXDS1S, BIT(pin));
++	else
++		ingenic_gpio_writel(chip, PXDS1C, BIT(pin));
++
++	if(strength & BIT(2))
++		ingenic_gpio_writel(chip, PXDS2S, BIT(pin));
++	else
++		ingenic_gpio_writel(chip, PXDS2C, BIT(pin));
++}
++
++static unsigned short ingenic_gpio_get_drive_strength(struct ingenic_gpio_chip *chip,
++		u32 pin)
++{
++	unsigned short strength = 0;
++
++	const struct ingenic_priv *priv = chip->pctl->priv;
++
++	if(!priv->have_ds) {
++		dev_warn(chip->gc.parent, "Do not support drive strength settings for this chip.");
++		return 0;
++	}
++
++	strength |= (ingenic_gpio_readl(chip, PXDS0) & BIT(pin)) ? (1 << 0) : 0;
++	strength |= (ingenic_gpio_readl(chip, PXDS1) & BIT(pin)) ? (1 << 1) : 0;
++	strength |= (ingenic_gpio_readl(chip, PXDS2) & BIT(pin)) ? (1 << 2) : 0;
++
++	return strength;
++}
++
++static void ingenic_gpio_irq_mask(struct irq_data *irqd)
++{
++	struct ingenic_gpio_chip *jzgc = irq_data_get_irq_chip_data(irqd);
++	struct ingenic_pinctrl	*pctl = jzgc->pctl;
++	unsigned long flags;
++
++	spin_lock_irqsave(&pctl->shadow_lock, flags);
++	ingenic_gpio_writel(jzgc, PxMSKS, BIT(irqd->hwirq));
++	spin_unlock_irqrestore(&pctl->shadow_lock, flags);
++}
++
++static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
++{
++	struct ingenic_gpio_chip *jzgc = irq_data_get_irq_chip_data(irqd);
++	struct ingenic_pinctrl	*pctl = jzgc->pctl;
++	unsigned long flags;
++
++	spin_lock_irqsave(&pctl->shadow_lock, flags);
++	ingenic_gpio_writel(jzgc, PxMSKC, BIT(irqd->hwirq));
++	spin_unlock_irqrestore(&pctl->shadow_lock, flags);
++}
++
++static void ingenic_gpio_irq_ack(struct irq_data *irqd)
++{
++	struct ingenic_gpio_chip *jzgc = irq_data_get_irq_chip_data(irqd);
++	struct ingenic_pinctrl	*pctl = jzgc->pctl;
++	unsigned long flags, pins, pins_before, pending;
++
++	spin_lock_irqsave(&pctl->shadow_lock, flags);
++	ingenic_gpio_writel(jzgc, PxFLGC, BIT(irqd->hwirq));
++	spin_unlock_irqrestore(&pctl->shadow_lock, flags);
++
++	if(jzgc->pctl->priv->dual_edge_interrupt){
++		return;
++	}
++
++	/*
++	 * The controller not support BOTH EDGE trigger
++	 * So we set the right trigger edge after irq ack
++	 * Note: To make sure our edge interrupt will be tigger and handle at next time
++	 *	 0, clear pending
++	 *	 1, read the pin level
++	 *	 2, set edge according the pin level
++	 *	 3, read the pin level
++	 *	 4, read the pending
++	 *	 5, if pin level is change and irq not pending the irq may miss, goto 2 retry
++	 */
++	if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) {
++		pins = ingenic_gpio_readl(jzgc, PxPIN);
++		do {
++			ingenic_gpio_writel(jzgc, pins & BIT(irqd->hwirq) ?
++					PxPAT0C : PxPAT0S, BIT(irqd->hwirq));
++			pins_before = pins;
++			pins = ingenic_gpio_readl(jzgc, PxPIN);
++			pending = ingenic_gpio_readl(jzgc, PxFLG);
++		} while(( (pins & BIT(irqd->hwirq)) !=
++					(pins_before & BIT(irqd->hwirq)) ) &&
++				!(pending & BIT(irqd->hwirq)));
++	}
++}
++
++static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int flow_type)
++{
++	struct ingenic_gpio_chip *jzgc = irq_data_get_irq_chip_data(irqd);
++	const struct ingenic_priv *priv = jzgc->pctl->priv;
++	enum gpio_function func;
++
++	if (!(flow_type & IRQ_TYPE_SENSE_MASK))
++		return 0;
++
++	if (flow_type & IRQ_TYPE_EDGE_BOTH)
++		irq_set_handler_locked(irqd, handle_edge_irq);
++	else
++		irq_set_handler_locked(irqd, handle_level_irq);
++
++	switch (flow_type & IRQD_TRIGGER_MASK) {
++	case IRQ_TYPE_LEVEL_HIGH:       func = GPIO_INT_HI;     break;
++	case IRQ_TYPE_LEVEL_LOW:        func = GPIO_INT_LO;     break;
++	case IRQ_TYPE_EDGE_RISING:      func = GPIO_INT_RE;     break;
++	case IRQ_TYPE_EDGE_FALLING:     func = GPIO_INT_FE;     break;
++	case IRQ_TYPE_EDGE_BOTH:        func = GPIO_INT_RE_FE;  break;
++	default:
++		pr_err("unsupported external interrupt type\n");
++		return -EINVAL;
++	}
++
++	ingenic_gpio_set_func(jzgc, priv->have_shadow, func, BIT(irqd->hwirq));
++	return 0;
++}
++
++static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
++{
++	struct ingenic_gpio_chip *jzgc = irq_data_get_irq_chip_data(irqd);
++
++	if (on)
++		jzgc->wakeup_bitmap |= BIT(irqd->hwirq);
++	else
++		jzgc->wakeup_bitmap &= ~BIT(irqd->hwirq);
++
++	return irq_set_irq_wake(jzgc->irq, on);
++}
++
++static void ingenic_gpio_irq_suspend(struct irq_data *irqd)
++{
++	struct ingenic_gpio_chip *jzgc = irq_data_get_irq_chip_data(irqd);
++
++	if ((!(jzgc->wakeup_bitmap & BIT(irqd->hwirq))) &&
++			(!(ingenic_gpio_readl(jzgc, PxMSK) & BIT(irqd->hwirq)))) {
++		jzgc->pm_irq_bitmap |= BIT(irqd->hwirq);
++		ingenic_gpio_writel(jzgc, PxMSKS, BIT(irqd->hwirq));
++	}
++}
++
++static void ingenic_gpio_irq_resume(struct irq_data *irqd)
++{
++	struct ingenic_gpio_chip *jzgc = irq_data_get_irq_chip_data(irqd);
++
++	if (jzgc->pm_irq_bitmap & BIT(irqd->hwirq)) {
++		ingenic_gpio_writel(jzgc, PxMSKC, BIT(irqd->hwirq));
++		jzgc->pm_irq_bitmap &= ~BIT(irqd->hwirq);
++	}
++}
++
++static int ingenic_irq_request_resources(struct irq_data *irqd)
++{
++	struct gpio_chip *chip = irq_data_get_irq_chip_data(irqd);
++
++	if (!try_module_get(chip->owner))
++		return -ENODEV;
++
++	if (gpiochip_lock_as_irq(chip, irqd->hwirq)) {
++		pr_err("GPIO chip %s: unable to lock HW IRQ %lu for IRQ\n",
++			chip->label,
++			irqd->hwirq);
++		module_put(chip->owner);
++		return -EINVAL;
++	}
++	return 0;
++}
++
++static void ingenic_irq_release_resources(struct irq_data *irqd)
++{
++	struct gpio_chip *chip = irq_data_get_irq_chip_data(irqd);
++
++	gpiochip_unlock_as_irq(chip, irqd->hwirq);
++	module_put(chip->owner);
++}
++
++static struct irq_chip ingenic_gpio_irq_chip = {
++	.name           = "GPIO",
++	.irq_unmask     = ingenic_gpio_irq_unmask,
++	.irq_mask       = ingenic_gpio_irq_mask,
++	.irq_ack        = ingenic_gpio_irq_ack,
++	.irq_set_type   = ingenic_gpio_irq_set_type,
++	.irq_set_wake	= ingenic_gpio_irq_set_wake,
++	.irq_suspend	= ingenic_gpio_irq_suspend,
++	.irq_resume	= ingenic_gpio_irq_resume,
++	.irq_request_resources = ingenic_irq_request_resources,
++	.irq_release_resources = ingenic_irq_release_resources,
++};
++
++static void ingenic_gpio_irq_handler(struct irq_desc *desc)
++{
++	struct ingenic_gpio_chip *jzgc = irq_desc_get_handler_data(desc);
++	unsigned long pend, mask;
++	unsigned long i;
++
++	if (IS_ERR_OR_NULL(jzgc->mcu_gpio_reg)) {
++		mask = ingenic_gpio_readl(jzgc, PxMSK);
++		pend = ingenic_gpio_readl(jzgc, PxFLG);
++		pend = pend & ~mask;
++	} else {
++		pend = *(jzgc->mcu_gpio_reg);
++	}
++
++	for_each_set_bit(i, &pend, jzgc->gc.ngpio) {
++        if (irq_find_mapping(jzgc->irq_domain, i))
++		    generic_handle_irq(irq_find_mapping(jzgc->irq_domain, i));
++    }
++
++	if (!IS_ERR_OR_NULL(jzgc->mcu_gpio_reg))
++		*(jzgc->mcu_gpio_reg) = 0;
++	return;
++}
++
++static void ingenic_gpio_set(struct gpio_chip *chip,
++		unsigned pin, int value)
++{
++	unsigned long flags, chip_flags;
++	struct ingenic_gpio_chip *jzgc = gc_to_ingenic_gc(chip);
++	struct ingenic_pinctrl *pctl = jzgc->pctl;
++
++	spin_lock_irqsave(&pctl->shadow_lock, flags);
++	spin_lock_irqsave(&jzgc->lock, chip_flags);
++
++	BUG_ON(pin > jzgc->gc.ngpio);
++	if (value)
++		ingenic_gpio_writel(jzgc, PxPAT0S, BIT(pin));
++	else
++		ingenic_gpio_writel(jzgc, PxPAT0C, BIT(pin));
++
++	spin_unlock_irqrestore(&jzgc->lock, chip_flags);
++	spin_unlock_irqrestore(&pctl->shadow_lock, flags);
++}
++
++static int ingenic_gpio_get(struct gpio_chip *chip, unsigned pin)
++{
++	struct ingenic_gpio_chip *jzgc = gc_to_ingenic_gc(chip);
++
++	BUG_ON(pin > chip->ngpio);
++	if (jzgc->resume_pending & BIT(pin)) {
++		jzgc->resume_pending &= ~BIT(pin);
++		return !!(jzgc->sleep_level & BIT(pin));
++	}
++	return !!(ingenic_gpio_readl(jzgc, PxPIN) & BIT(pin));
++}
++
++static int ingenic_gpio_direction_input(struct gpio_chip *chip,
++		unsigned pin)
++{
++	BUG_ON(pin > chip->ngpio);
++	return pinctrl_gpio_direction_input(chip->base + pin);
++}
++
++static int ingenic_gpio_direction_output(struct gpio_chip *chip,
++		unsigned pin, int value)
++{
++	ingenic_gpio_set(chip, pin, value);
++	return pinctrl_gpio_direction_output(chip->base + pin);
++}
++
++static int ingenic_gpio_to_irq(struct gpio_chip *chip,
++		unsigned pin)
++{
++	struct ingenic_gpio_chip *jzgc = gc_to_ingenic_gc(chip);
++	unsigned int virq;
++
++
++	BUG_ON(pin > chip->ngpio);
++	if (NULL == jzgc->irq_domain) return -ENXIO;
++	virq = irq_create_mapping(jzgc->irq_domain, pin);
++
++	return (virq) ?: -ENXIO;
++}
++static int ingenic_gpio_request(struct gpio_chip *chip, unsigned offset)
++{
++	struct ingenic_gpio_chip *jzgc = gc_to_ingenic_gc(chip);
++	unsigned gpio = chip->base + offset;
++
++	if(jzgc->used_pins_bitmap & (1 << offset)) {
++		printk("%s: GP:%s  used_pins_bitmap: 0X%08X\n", __func__, jzgc->name, jzgc->used_pins_bitmap);
++		printk("current gpio request pin: chip->name %s, gpio: 0X%08X\n", chip->of_node->name, 1 << offset);
++		dump_stack();
++		printk("%s:gpio functions has redefinition\n", __FILE__);
++	}
++
++	jzgc->used_pins_bitmap |= 1 << offset;
++
++	return pinctrl_gpio_request(gpio);
++}
++static void ingenic_gpio_free(struct gpio_chip *chip, unsigned offset)
++{
++	struct ingenic_gpio_chip *jzgc = gc_to_ingenic_gc(chip);
++	unsigned gpio = chip->base + offset;
++	pinctrl_gpio_free(gpio);
++	jzgc->used_pins_bitmap &= ~(1 << offset);
++}
++
++static const struct gpio_chip ingenic_gpiolib_chip = {
++	.owner = THIS_MODULE,
++	.set = ingenic_gpio_set,
++	.get = ingenic_gpio_get,
++	.direction_input = ingenic_gpio_direction_input,
++	.direction_output = ingenic_gpio_direction_output,
++	.to_irq = ingenic_gpio_to_irq,
++	.request = ingenic_gpio_request,
++	.free = ingenic_gpio_free,
++};
++
++static int ingenic_of_gpio_xlate(struct gpio_chip *gc,
++		const struct of_phandle_args *gpiospec, u32 *flags)
++{
++	struct ingenic_gpio_chip *jzgc = gc_to_ingenic_gc(gc);
++	u32 pin;
++	u32 pull;
++#if defined(INGENIC_GPIO_FILTER)
++	u32 filter;
++#endif
++	u32 drive_strength = 0;
++	u32 schmit_enable = 0;
++	u32 slewrate_enable = 0;
++
++	if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
++		return -EINVAL;
++
++	if (gpiospec->args[0] >= gc->ngpio)
++		return -EINVAL;
++
++	if (flags)
++		*flags = gpiospec->args[1];
++
++	pin = gpiospec->args[0];
++
++	pull = INGENIC_GPIO_PULL(gpiospec->args[2]);
++	ingenic_gpio_set_pull(jzgc, BIT(pin), pull);
++
++	drive_strength = INGENIC_GPIO_DRIVE_STRENGTH(gpiospec->args[2]);
++	schmit_enable = INGENIC_GPIO_SCHMITT_ENABLE(gpiospec->args[2]);
++	slewrate_enable	= INGENIC_GPIO_SLEW_RATE_ENABLE(gpiospec->args[2]);
++
++	ingenic_gpio_set_drive_strength(jzgc, pin, drive_strength);
++	ingenic_gpio_set_schmitt_enable(jzgc, pin, schmit_enable);
++	ingenic_gpio_set_slew_rate(jzgc, pin, slewrate_enable);
++
++#if defined(INGENIC_GPIO_FILTER)
++	filter = INGENIC_GPIO_FILTER(gpiospec->args[2]);
++	if (jzgc->filter_bitmap & BIT(pin))
++		ingenic_gpio_set_filter(jzgc, pin, filter);
++#endif
++	return pin;
++}
++
++static int ingenic_gpio_chip_add(struct ingenic_pinctrl *pctl,
++		struct device_node *np, int base, int idx)
++{
++	struct ingenic_gpio_chip *jzgc = &pctl->gpio_chips[idx];
++	struct gpio_chip *gc = &jzgc->gc;
++	u32 ngpio;
++
++	jzgc->gc = ingenic_gpiolib_chip;
++	snprintf(jzgc->name, sizeof(jzgc->name), "GP%c", 'A' + idx);
++
++	if (of_property_read_u32(np, "ingenic,ngpio", &ngpio))
++		ngpio = MAX_GPIOS_ON_CHIP;
++	if (of_property_read_u32(np, "ingenic,filter-bitmap", &jzgc->filter_bitmap))
++		jzgc->filter_bitmap = 0;
++	if (of_property_read_u32(np, "ingenic,pull-bitmap", &jzgc->pull_bitmap))
++		jzgc->pull_bitmap = 0;
++	if (of_property_read_u32(np, "#gpio-cells", &gc->of_gpio_n_cells))
++		gc->of_gpio_n_cells = 3;
++	jzgc->used_pins_bitmap = 0;
++	pr_debug("%s (%d) config:\nfilter %08x\npull %08x\ncells=%d\nbase%d\n",
++			jzgc->name,
++			ngpio,
++			jzgc->filter_bitmap,
++			jzgc->pull_bitmap,
++			gc->of_gpio_n_cells,
++			base);
++	jzgc->of_node = np;
++	jzgc->idx = idx;
++	jzgc->pctl = pctl;
++	gc->ngpio = (u16)ngpio;
++	gc->of_node = np;
++	gc->base = base;
++	gc->parent = pctl->dev;
++	gc->label = jzgc->name;
++	gc->of_xlate = ingenic_of_gpio_xlate;
++
++	return gpiochip_add(gc);
++}
++
++static void ingenic_gpio_sleep_init(struct device_node *np,
++		const char *list_name, u32 *pm_pin)
++{
++	int size, i, array[32], pin_bitmap = 0;
++
++	if (!of_find_property(np, list_name, &size))
++		return;
++
++	if (of_property_read_u32_array(np, list_name,
++			array, size/sizeof(u32)))
++		return;
++
++	for (i = 0; i < size/sizeof(u32); i++) {
++		BUG_ON(array[i] > 31);
++		pin_bitmap |= BIT(array[i]);
++	}
++
++	*pm_pin = pin_bitmap;
++}
++
++static void ingenic_gpio_pm_init(struct ingenic_pinctrl *pctl,
++		struct device_node *np, int idx)
++{
++	struct ingenic_gpio_chip *jzgc = &pctl->gpio_chips[idx];
++
++	ingenic_gpio_sleep_init(np, "ingenic,gpio-sleep-low",
++			&jzgc->pm_bitmap[PM_SLEEP_LOW]);
++	ingenic_gpio_sleep_init(np, "ingenic,gpio-sleep-high",
++			&jzgc->pm_bitmap[PM_SLEEP_HIGH]);
++	ingenic_gpio_sleep_init(np, "ingenic,gpio-sleep-pull",
++			&jzgc->pm_bitmap[PM_SLEEP_PULL]);
++	ingenic_gpio_sleep_init(np, "ingenic,gpio-sleep-npul",
++			&jzgc->pm_bitmap[PM_SLEEP_NOPULL]);
++	ingenic_gpio_sleep_init(np, "ingenic,gpio-sleep-pullup",
++			&jzgc->pm_bitmap[PM_SLEEP_PULLUP]);
++	ingenic_gpio_sleep_init(np, "ingenic,gpio-sleep-pulldown",
++			&jzgc->pm_bitmap[PM_SLEEP_PULLDOWN]);
++	ingenic_gpio_sleep_init(np, "ingenic,gpio-sleep-hiz",
++			&jzgc->pm_bitmap[PM_SLEEP_HIZ]);
++
++	jzgc->wakeup_bitmap = 0;
++
++	/*pr_info("%s pm sleep:\nlow  %08x\nhigh %08x\npull %08x\nnpull %08x\n",
++			jzgc->name, jzgc->pm_bitmap[PM_SLEEP_LOW],
++			jzgc->pm_bitmap[PM_SLEEP_HIGH],
++			jzgc->pm_bitmap[PM_SLEEP_PULL],
++			jzgc->pm_bitmap[PM_SLEEP_NOPULL]);
++			*/
++}
++
++static int ingenic_irq_domain_xlate(struct irq_domain *d,
++		struct device_node *ctrlr,
++		const u32 *intspec, unsigned int intsize,
++		unsigned long *out_hwirq, unsigned int *out_type)
++{
++	struct ingenic_gpio_chip *jzgc = d->host_data;
++	u32 pin;
++#if defined(INGENIC_GPIO_PULL)
++	u32 pull;
++#endif
++#if defined(INGENIC_GPIO_FILTER)
++	u32 filter;
++#endif
++	if (WARN_ON(intsize < 2))
++		return -EINVAL;
++	pin = *out_hwirq = intspec[0];
++	*out_type = (intsize > 1) ? intspec[1] : IRQ_TYPE_NONE;
++
++#if defined(INGENIC_GPIO_PULL)
++	pull = INGENIC_GPIO_PULL(intspec[2]);
++	ingenic_gpio_set_pull(jzgc, BIT(pin), pull);
++#endif
++
++#if defined(INGENIC_GPIO_FILTER)
++	filter = INGENIC_GPIO_FILTER(intspec[2]);
++	if (jzgc->filter_bitmap & BIT(pin))
++		ingenic_gpio_set_filter(jzgc, pin, filter);
++#endif
++	return 0;
++}
++
++static int ingenic_irq_domain_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw)
++{
++	struct ingenic_gpio_chip *jzgc = d->host_data;
++	irq_set_chip_data(virq, jzgc);
++	irq_set_chip_and_handler(virq, &ingenic_gpio_irq_chip,
++				handle_level_irq);
++	return 0;
++}
++
++static const struct irq_domain_ops ingenic_irq_domain_ops = {
++	.map = ingenic_irq_domain_map,
++	.xlate = ingenic_irq_domain_xlate,
++};
++
++static int ingenic_gpio_irq_init(struct ingenic_pinctrl *pctl,
++		struct device_node *np, int idx)
++{
++	struct ingenic_gpio_chip *jzgc = &pctl->gpio_chips[idx];
++
++	jzgc->irq = irq_of_parse_and_map(np, 0);
++	if (!jzgc->irq)
++		return -EINVAL;
++
++	jzgc->irq_domain = irq_domain_add_linear(np, jzgc->gc.ngpio,
++			&ingenic_irq_domain_ops, (void *)jzgc);
++	if (!jzgc->irq_domain)
++		return -ENOMEM;
++	irq_set_handler_data(jzgc->irq, jzgc);
++	irq_set_chained_handler(jzgc->irq, ingenic_gpio_irq_handler);
++	return 0;
++}
++
++static int ingenic_gpiolib_register(struct ingenic_pinctrl *pctl)
++{
++	struct ingenic_gpio_chip *gpio_chips;
++	struct device_node *np;
++	int idx = 0, ret;
++	u32 offset;
++
++	if (!of_property_read_u32(pctl->of_node,"ingenic,regs-offset", &offset)){
++		pctl->group_regs_offset = offset;
++	}
++	if (of_property_read_u32(pctl->of_node,"ingenic,num-chips", &pctl->num_chips))
++		return -EINVAL;
++
++	pctl->bitmap_priv = devm_kzalloc(pctl->dev, sizeof(u32) * pctl->num_chips,
++			GFP_KERNEL);
++	if (!pctl->bitmap_priv)
++		return -ENOMEM;
++
++	gpio_chips = devm_kzalloc(pctl->dev,
++			pctl->num_chips * sizeof(struct ingenic_gpio_chip),
++			GFP_KERNEL);
++	pctl->gpio_chips = gpio_chips;
++	pctl->total_pins = 0;
++	spin_lock_init(&pctl->shadow_lock);
++
++	for_each_child_of_node(pctl->of_node, np) {
++		if (!of_find_property(np, "gpio-controller", NULL))
++			continue;
++
++		if (WARN_ON(idx >= pctl->num_chips))
++			break;
++
++		ret = ingenic_gpio_chip_add(pctl, np, pctl->total_pins, idx);
++		if (ret) {
++			dev_err(pctl->dev, "%s gpio add failed\n", gpio_chips[idx].name);
++			return ret;
++		}
++		pctl->total_pins += gpio_chips[idx].gc.ngpio;
++		spin_lock_init(&gpio_chips[idx].lock);
++
++		ingenic_gpio_pm_init(pctl, np, idx);
++
++		if (!of_find_property(np, "interrupt-controller", NULL))
++			goto next_chip;
++
++		ret = ingenic_gpio_irq_init(pctl, np, idx);
++		if (ret)
++			dev_err(pctl->dev, "%s irq init failed\n",
++					gpio_chips[idx].gc.label);
++
++next_chip:
++		of_node_get(np);
++		idx++;
++	}
++
++	dev_info(pctl->dev, "%d gpio chip add success, pins %d\n",
++			idx, pctl->total_pins);
++	return 0;
++}
++
++static int ingenic_get_group_count(struct pinctrl_dev *pctldev)
++{
++	struct ingenic_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++	return pctl->num_groups;
++}
++
++static const char* ingenic_get_group_name(struct pinctrl_dev *pctldev,
++		unsigned selector)
++{
++	struct ingenic_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++
++	BUG_ON(selector >= pctl->num_groups);
++	return pctl->groups[selector].name;
++}
++
++static int ingenic_get_group_pins(struct pinctrl_dev *pctldev,
++		unsigned selector,
++		const unsigned **pins,
++		unsigned *num_pins)
++{
++	struct ingenic_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++
++	BUG_ON(selector >= pctl->num_groups);
++	*pins = pctl->groups[selector].pins;
++	*num_pins = pctl->groups[selector].num_pins;
++	return 0;
++}
++
++static int ingenic_gc_match(struct gpio_chip *chip, void *data)
++{
++	return chip->of_node == data;
++}
++
++
++static int ingenic_packed_config(int cfgval, int *config)
++{
++	int value;
++
++	value = PINCFG_UNPACK_VALUE(cfgval);
++	switch (cfgval & PINCTL_CFG_TYPE_MSK ) {
++	case PINCTL_CFG_FILTER:
++		*config = pinconf_to_config_packed(PIN_CONFIG_INPUT_DEBOUNCE, value & 0xffff);
++	case PINCTL_CFG_DRIVE_STRENGTH:
++		*config = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, value & 0xffff);
++		 break;
++	case PINCTL_CFG_BIAS_PULL_PIN_DEFAULT:
++		*config = pinconf_to_config_packed(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1);
++		break;
++	case PINCTL_CFG_BIAS_DISABLE:
++		*config = pinconf_to_config_packed(PIN_CONFIG_BIAS_DISABLE, 1);
++		break;
++	case PINCTL_CFG_BIAS_HIGH_IMPEDANCE:
++		*config = pinconf_to_config_packed(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 1);
++		break;
++	case PINCTL_CFG_INPUT_SCHMITT_ENABLE:
++		*config = pinconf_to_config_packed(PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1);
++		break;
++	case PINCTL_CFG_SLEW_RATE:
++		*config = pinconf_to_config_packed(PIN_CONFIG_SLEW_RATE, 1);
++		break;
++	default:
++		*config = 0;
++	}
++	return 0;
++}
++
++#if defined(PINCTL_CFG_TYPES)
++static int of_prase_pincfg_to_map(struct device_node *np,
++		struct pinctrl_map *map, int num_maps)
++{
++	struct of_phandle_args out_args;
++	struct ingenic_gpio_chip *jzgc;
++	struct gpio_chip *gc;
++	u32 idx = 0, config = 0, index = 0;
++	unsigned long pin, bitmap;
++	char *pin_names;
++
++	while (!of_parse_phandle_with_args(np, "ingenic,pincfg",
++				"#ingenic,pincfg-cells", index++,
++				&out_args)) {
++		gc = gpiochip_find(out_args.np, ingenic_gc_match);
++		if (!gc) return -EINVAL;
++		jzgc = gc_to_ingenic_gc(gc);
++
++		bitmap = pin_bitmap(out_args.args[PIN_ARGS_FROM_INDEX],
++				out_args.args[PIN_ARGS_TO_INDEX]);
++
++		ingenic_packed_config(out_args.args[PIN_ARGS_CFG_INDEX], &config);
++		for_each_set_bit(pin, &bitmap, jzgc->gc.ngpio) {
++			pin_names = kzalloc(sizeof(char) * PIN_NAMES_LEN, GFP_KERNEL);
++			if (!pin_names) return -ENOMEM;
++			sprintf(pin_names, "%s-%d", jzgc->name, (unsigned)pin);
++			for (idx = 0; idx < num_maps &&
++					map[idx].data.configs.group_or_pin &&
++					strcmp(pin_names, map[idx].data.configs.group_or_pin);
++					idx++);
++			BUG_ON(num_maps == idx);
++			if (map[idx].data.configs.num_configs == PINCTL_CFG_TYPES) {
++				__WARN();
++				continue;
++			}
++			kfree(map[idx].data.configs.group_or_pin);
++			map[idx].data.configs.group_or_pin = pin_names;
++			map[idx].data.configs.configs[map[idx].data.configs.num_configs] = config;
++			map[idx].data.configs.num_configs++;
++			map[idx].type = PIN_MAP_TYPE_CONFIGS_PIN;
++		}
++	}
++	return 0;
++}
++#endif
++
++static int ingenic_dt_node_to_map(struct pinctrl_dev *pctldev,
++		struct device_node *np_config,
++		struct pinctrl_map **maps, unsigned *num_maps)
++{
++	struct ingenic_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++	struct gpio_chip *gc;
++	struct ingenic_gpio_chip *jzgc;
++	struct device_node *node;
++	struct ingenic_pinctrl_group *grp;
++	struct ingenic_pinctrl_func *func;
++	struct pinctrl_map *new_map;
++	unsigned long *cfgs;
++	int index = 0, ret = 0;
++	unsigned map_cnt = 0, cfg_map_cnt = 0, idx;
++	struct of_phandle_args out_args;
++	u32 *pincfg_bitmap = pctl->bitmap_priv;
++
++	grp = find_group_by_of_node(pctl, np_config);
++	if (!grp)
++		return -EINVAL;
++
++	if ((node = of_get_parent(np_config)) == pctl->of_node)
++		func = find_func_by_of_node(pctl, np_config);
++	else
++		func = find_func_by_of_node(pctl, node);
++	of_node_put(node);
++	if (!func)
++		return -EINVAL;
++
++
++#if defined(PINCTL_CFG_TYPES)
++	for (idx = 0; idx < pctl->num_chips; idx++)
++		pincfg_bitmap[idx] = 0;
++	while (!of_parse_phandle_with_args(np_config, "ingenic,pincfg",
++					"#ingenic,pincfg-cells", index++, &out_args)) {
++		gc = gpiochip_find(out_args.np, ingenic_gc_match);
++		if (!gc) return -ENOMEM;
++		jzgc = gc_to_ingenic_gc(gc);
++		pincfg_bitmap[jzgc->idx] |= pin_bitmap(out_args.args[PIN_ARGS_FROM_INDEX],
++				out_args.args[PIN_ARGS_TO_INDEX]);
++	};
++	for (idx = 0; idx < pctl->num_chips; idx++)
++		cfg_map_cnt += bit_count(pincfg_bitmap[idx]);
++	map_cnt = cfg_map_cnt;
++#endif
++
++	if (of_find_property(np_config, "ingenic,pinmux", NULL) &&
++			of_find_property(np_config, "ingenic,pinmux-funcsel", NULL))
++		map_cnt++;
++	if (!map_cnt) return -EINVAL;
++
++	*maps = new_map = kzalloc(sizeof(*new_map) * map_cnt, GFP_KERNEL);
++	if (!new_map)
++		return -ENOMEM;
++
++#if defined(PINCTL_CFG_TYPES)
++	if (!cfg_map_cnt)
++		goto skip_config;
++
++	cfgs = kzalloc(sizeof(*cfgs) * PINCTL_CFG_TYPES * cfg_map_cnt, GFP_KERNEL);
++	if (!cfgs)
++		return -ENOMEM;
++
++	for (idx = 0; idx < cfg_map_cnt; idx++, cfgs += PINCTL_CFG_TYPES) {
++		new_map[idx].data.configs.configs = cfgs;
++	}
++
++	ret = of_prase_pincfg_to_map(np_config, new_map, cfg_map_cnt);
++	if (ret)
++		return ret;
++#endif
++skip_config:
++	*num_maps = cfg_map_cnt;
++	if (!of_find_property(np_config, "ingenic,pinmux", NULL))
++		return 0;
++
++	jzgc = gc_to_ingenic_gc(grp->gc);
++	/* if(jzgc->used_pins_bitmap & grp->pinmux_bitmap) { */
++	/* 	printk("%s: GP:%s  used_pins_bitmap: 0X%08X\n", __func__, jzgc->name, jzgc->used_pins_bitmap); */
++	/* 	printk("current set function pin: chip->name %s, gpio: 0X%08X\n", grp->name, grp->pinmux_bitmap); */
++	/* 	dump_stack(); */
++	/* 	printk("%s:gpio functions has redefinition\n", __FILE__); */
++	/* } */
++	jzgc->used_pins_bitmap |= grp->pinmux_bitmap;
++	new_map[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
++	new_map[*num_maps].data.mux.function = func->name;
++	new_map[*num_maps].data.mux.group = grp->name;
++	(*num_maps)++;
++	return 0;
++}
++
++static void ingenic_dt_free_map(struct pinctrl_dev *pctldev,
++		struct pinctrl_map *maps, unsigned num_maps)
++{
++	unsigned long *configs = NULL;
++	int idx;
++	for (idx = 0; idx < num_maps; idx++) {
++		if (maps[idx].type == PIN_MAP_TYPE_CONFIGS_GROUP) {
++			if (NULL == configs)
++				configs = maps[idx].data.configs.configs;
++			kfree(maps[idx].data.configs.group_or_pin);
++		}
++	}
++	kfree(configs);
++	kfree(maps);
++}
++
++static const struct pinctrl_ops ingenic_pctl_ops = {
++	.get_groups_count       = ingenic_get_group_count,
++	.get_group_name         = ingenic_get_group_name,
++	.get_group_pins         = ingenic_get_group_pins,
++	.dt_node_to_map         = ingenic_dt_node_to_map,	/* TODO: use generic map*/
++	.dt_free_map            = ingenic_dt_free_map,
++};
++
++static int ingenic_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
++{
++	struct ingenic_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++	return pctl->num_funs;
++}
++
++static const char *ingenic_pinmux_get_function_name(struct pinctrl_dev *pctldev,
++		unsigned selector)
++{
++	struct ingenic_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++	return pctl->functions[selector].name;
++}
++
++static int ingenic_pinmux_get_groups(struct pinctrl_dev *pctldev,
++		unsigned selector,
++		const char * const **groups,
++		unsigned * const num_groups)
++{
++	struct ingenic_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++
++	BUG_ON(selector > pctl->num_funs);
++	*groups = pctl->functions[selector].groups;
++	*num_groups = pctl->functions[selector].num_groups;
++	return 0;
++}
++
++static int ingenic_pinmux_enable(struct pinctrl_dev *pctldev,
++		unsigned func_selector,
++		unsigned group_selector)
++{
++	struct ingenic_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++	struct ingenic_pinctrl_group *grp = NULL;
++	const struct ingenic_priv *priv = pctl->priv;
++	struct ingenic_gpio_chip *jzgc;
++
++	if (func_selector > pctl->num_funs ||
++			group_selector > pctl->num_groups)
++		return -EINVAL;
++
++	grp = &pctl->groups[group_selector];
++	jzgc = gc_to_ingenic_gc(grp->gc);
++	ingenic_gpio_set_func(jzgc, priv->have_shadow,
++			grp->pinmux_func, grp->pinmux_bitmap);
++	return 0;
++}
++
++static int ingenic_pinmux_gpio_set_dir(struct pinctrl_dev *pctldev,
++		struct pinctrl_gpio_range *range, unsigned gpio,
++		bool input)
++{
++	struct ingenic_gpio_chip *jzgc = gc_to_ingenic_gc(range->gc);
++	const struct ingenic_priv *priv = jzgc->pctl->priv;
++	unsigned pin = gpio - range->gc->base;
++	unsigned pxpat0, pxint;
++	enum gpio_function func = GPIO_INPUT;
++	if (!input) {
++		pxpat0 = ingenic_gpio_readl(jzgc, PxPAT0);
++		if (pxpat0 & BIT(pin))
++			func = GPIO_OUTPUT1;
++		else
++			func = GPIO_OUTPUT0;
++	} else {
++		pxint = ingenic_gpio_readl(jzgc, PxINT);
++		if (pxint & BIT(pin))
++			return 0;
++	}
++	ingenic_gpio_set_func(jzgc, priv->have_shadow, func, BIT(pin));
++	return 0;
++}
++
++static const struct pinmux_ops ingenic_pinmux_ops = {
++	.get_functions_count    = ingenic_pinmux_get_functions_count,
++	.get_function_name      = ingenic_pinmux_get_function_name,
++	.get_function_groups    = ingenic_pinmux_get_groups,
++	.set_mux		= ingenic_pinmux_enable,
++	.gpio_set_direction	= ingenic_pinmux_gpio_set_dir,
++};
++
++static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
++		unsigned gpio,
++		unsigned long *config)
++{
++	struct gpio_chip *gc = gpio_to_chip(gpio);
++	struct ingenic_gpio_chip *jzgc = gc_to_ingenic_gc(gc);
++	enum pin_config_param param;
++	unsigned pin;
++	unsigned arg;
++	bool pull;
++
++	if (!jzgc) return -EINVAL;
++
++	pin = gpio - jzgc->gc.base;
++
++	param = pinconf_to_config_param(*config);
++
++	switch (param) {
++	case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
++	case PIN_CONFIG_BIAS_DISABLE:
++		pull = ingenic_gpio_readl(jzgc, PxPEN)&BIT(pin);
++		if ((jzgc->pull_bitmap & BIT(pin)) && pull)
++			*config = pinconf_to_config_packed(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1);
++		else
++			*config = pinconf_to_config_packed(PIN_CONFIG_BIAS_DISABLE, 1);
++		break;
++	case PIN_CONFIG_DRIVE_STRENGTH:
++		arg = ingenic_gpio_get_drive_strength(jzgc, pin);
++		*config = pinconf_to_config_packed(param, arg);
++		break;
++	case PIN_CONFIG_BIAS_PULL_UP:
++	case PIN_CONFIG_BIAS_PULL_DOWN:
++	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
++		arg = ingenic_gpio_get_pull_state(jzgc, pin);
++		*config = pinconf_to_config_packed(param, arg);
++		break;
++	case PIN_CONFIG_SLEW_RATE:
++		arg = !!(ingenic_gpio_readl(jzgc, PxSR) & BIT(pin));
++		*config = pinconf_to_config_packed(param, arg);
++		break;
++	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
++		arg = !!(ingenic_gpio_readl(jzgc, PxSMT) & BIT(pin));
++		*config = pinconf_to_config_packed(param, arg);
++		break;
++	default:
++		return -ENOTSUPP;
++		break;
++	}
++	return 0;
++}
++
++static int ingenic_pinconf_set(struct pinctrl_dev *pctldev,
++			       unsigned gpio,
++			       unsigned long *configs,
++			       unsigned num_configs)
++{
++	struct gpio_chip *gc = gpio_to_chip(gpio);
++	struct ingenic_gpio_chip *jzgc = gc_to_ingenic_gc(gc);
++	enum pin_config_param param;
++	u16 value;
++	unsigned pin;
++	int i;
++
++
++	if (!jzgc) {
++		return -EINVAL;
++	}
++
++	pin = gpio - jzgc->gc.base;
++
++	dev_dbg(pctldev->dev, "%s %s %u %lx\n", __func__, jzgc->gc.label, pin, *configs);
++
++	for(i = 0; i < num_configs; i++) {
++		param = pinconf_to_config_param(configs[i]);
++		switch (param) {
++			case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
++				if (!(jzgc->pull_bitmap & BIT(pin)))
++					return -EINVAL;
++				ingenic_gpio_set_pull(jzgc, BIT(pin), INGENIC_GPIO_PULLEN);
++				break;
++			case PIN_CONFIG_BIAS_DISABLE:
++				if ((!(jzgc->pull_bitmap & BIT(pin))))
++					return -EINVAL;
++				ingenic_gpio_set_pull(jzgc, BIT(pin), !INGENIC_GPIO_PULLEN);
++				break;
++			case PIN_CONFIG_INPUT_DEBOUNCE:
++				value = pinconf_to_config_argument(configs[i]);
++				ingenic_gpio_set_filter(jzgc, pin, value);
++				break;
++			case PIN_CONFIG_DRIVE_STRENGTH:
++				value = pinconf_to_config_argument(configs[i]);
++				ingenic_gpio_set_drive_strength(jzgc, pin, value);
++				break;
++			case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
++				ingenic_gpio_set_schmitt_enable(jzgc, pin, 1);
++				break;
++			case PIN_CONFIG_SLEW_RATE:
++				ingenic_gpio_set_slew_rate(jzgc, pin, 1);
++				break;
++			case PIN_CONFIG_BIAS_PULL_UP:
++				ingenic_gpio_set_pull(jzgc, BIT(pin), INGENIC_GPIO_PULLUP);
++				break;
++			case PIN_CONFIG_BIAS_PULL_DOWN:
++				ingenic_gpio_set_pull(jzgc, BIT(pin), INGENIC_GPIO_PULLDOWN);
++				break;
++			case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
++				ingenic_gpio_set_pull(jzgc, BIT(pin), INGENIC_GPIO_HIZ);
++				break;
++			default:
++				return -ENOTSUPP;
++		}
++	}
++	return 0;
++}
++
++/* set the pin config settings for a specified pin group */
++static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
++			unsigned group, unsigned long *configs,
++			unsigned num_configs)
++{
++	struct ingenic_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++	struct ingenic_pinctrl_group *grp = NULL;
++	const unsigned int *pins;
++	unsigned int cnt;
++
++	grp = &pctl->groups[group];
++	pins = grp->pins;
++
++	for (cnt = 0; cnt < grp->num_pins; cnt++)
++		ingenic_pinconf_set(pctldev, pins[cnt], configs, num_configs);
++
++	return 0;
++}
++
++/* get the pin config settings for a specified pin group */
++static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,
++				unsigned int group, unsigned long *config)
++{
++	struct ingenic_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
++	const unsigned int *pins;
++
++	pins = pctl->groups[group].pins;
++	ingenic_pinconf_get(pctldev, pins[0], config);
++	return 0;
++}
++
++
++static const struct pinconf_ops ingenic_pinconf_ops = {
++	.pin_config_get   	= ingenic_pinconf_get,
++	.pin_config_set   	= ingenic_pinconf_set,
++	.pin_config_group_get	= ingenic_pinconf_group_get,
++	.pin_config_group_set	= ingenic_pinconf_group_set,
++};
++
++static int ingenic_init_group(struct device *dev, struct device_node *np,
++		struct ingenic_pinctrl_group *grp)
++{
++	struct device_node *gpio_np = NULL;
++	struct of_phandle_args out_args;
++	u32 func;
++	int pin, idx = 0, index = 0;
++
++	grp->name = np->name;
++	grp->of_node = np;
++
++	while(!of_parse_phandle_with_args(np, "ingenic,pinmux",
++				"#ingenic,pinmux-cells", index++, &out_args)) {
++		if (gpio_np != NULL && out_args.np != gpio_np)
++			return -EINVAL;
++		if (of_property_read_u32(np, "ingenic,pinmux-funcsel", &func))
++			return -EINVAL;
++		gpio_np = out_args.np;
++		grp->pinmux_bitmap |= pin_bitmap(out_args.args[PIN_ARGS_FROM_INDEX],
++				out_args.args[PIN_ARGS_TO_INDEX]);
++	}
++	if (!gpio_np)
++		return 0;
++	grp->gc = gpiochip_find(gpio_np, ingenic_gc_match);
++	if (!grp->gc) return -EINVAL;
++	grp->num_pins = bit_count(grp->pinmux_bitmap);
++	grp->pins = devm_kzalloc(dev, sizeof(unsigned) * grp->num_pins,
++			GFP_KERNEL);
++	if (!grp->pins)
++		return -ENOMEM;
++
++	switch (func) {
++	case PINCTL_FUNCTION0:  grp->pinmux_func = GPIO_FUNC_0; break;
++	case PINCTL_FUNCTION1:	grp->pinmux_func = GPIO_FUNC_1; break;
++	case PINCTL_FUNCTION2:	grp->pinmux_func = GPIO_FUNC_2; break;
++	case PINCTL_FUNCTION3:	grp->pinmux_func = GPIO_FUNC_3; break;
++	case PINCTL_FUNCLOLVL:	grp->pinmux_func = GPIO_OUTPUT0; break;
++	case PINCTL_FUNCHILVL:	grp->pinmux_func = GPIO_OUTPUT1; break;
++	case PINCTL_FUNCINPUT:	grp->pinmux_func = GPIO_INPUT; break;
++	case PINCTL_FUNCINPUT_LO: grp->pinmux_func = GPIO_INT_LO; break;
++	case PINCTL_FUNCINPUT_HI: grp->pinmux_func = GPIO_INT_HI; break;
++	case PINCTL_FUNCINPUT_FE: grp->pinmux_func = GPIO_INT_FE; break;
++	case PINCTL_FUNCINPUT_RE: grp->pinmux_func = GPIO_INT_RE; break;
++	case PINCTL_FUNCINPUT_RE_FE: grp->pinmux_func = GPIO_INT_RE_FE; break;
++	default:
++		return -EINVAL;
++	}
++	for_each_set_bit(pin, (unsigned long *)&grp->pinmux_bitmap, grp->gc->ngpio)
++		grp->pins[idx++] = grp->gc->base + pin;
++	return 0;
++}
++
++static struct ingenic_pinctrl_group* ingenic_pinctrl_create_groups(
++		struct device *dev, unsigned *cnt)
++{
++	struct device_node *np, *subnp;
++	struct ingenic_pinctrl_group *grp;
++	unsigned int i = 0;
++
++	*cnt = 0;
++	for_each_child_of_node(dev->of_node, np) {
++		unsigned count = 0;
++		if (!!of_find_property(np, "gpio-controller", NULL))
++			continue;
++		if (!!(count = of_get_child_count(np)))
++			*cnt += count;
++		else
++			(*cnt)++;
++	}
++
++	grp = devm_kzalloc(dev, sizeof(*grp) * (*cnt), GFP_KERNEL);
++	if (!grp)
++		return ERR_PTR(-ENOMEM);
++
++	for_each_child_of_node(dev->of_node, np) {
++		if (!!of_find_property(np, "gpio-controller", NULL))
++			continue;
++
++		if (!of_get_child_count(np)) {
++			ingenic_init_group(dev, np, &grp[i++]);
++			continue;
++		}
++
++		for_each_child_of_node(np, subnp) {
++			ingenic_init_group(dev, subnp, &grp[i++]);
++		}
++	}
++	return grp;
++}
++
++static struct ingenic_pinctrl_func* ingenic_pinctrl_create_functions(
++		struct device *dev, unsigned int *cnt)
++{
++	struct device_node *np, *subnp;
++	struct ingenic_pinctrl_func *func;
++	int i = 0;
++
++	*cnt = 0;
++	for_each_child_of_node(dev->of_node, np) {
++		if (!!of_find_property(np, "gpio-controller", NULL))
++			continue;
++		(*cnt)++;
++	}
++
++	func = devm_kzalloc(dev, sizeof(*func) * (*cnt), GFP_KERNEL);
++	if (!func)
++		return ERR_PTR(-ENOMEM);
++
++	for_each_child_of_node(dev->of_node, np) {
++		u8 num_child, j = 0;
++		if (!!of_find_property(np, "gpio-controller", NULL))
++			continue;
++		func[i].name = np->name;
++		func[i].of_node = np;
++		num_child = of_get_child_count(np);
++		func[i].num_groups = num_child ?:1;
++		func[i].groups = devm_kzalloc(dev, sizeof(char *) * func[i].num_groups,
++				GFP_KERNEL);
++		if (!func[i].groups)
++			return ERR_PTR(-ENOMEM);
++		if (num_child) {
++			for_each_child_of_node(np, subnp)
++				func[i].groups[j++] = subnp->name;
++		} else
++			func[i].groups[0] = func[i].name;
++		i++;
++	}
++	return func;
++}
++
++static int ingenic_pinctrl_parse_dt(struct ingenic_pinctrl *pctl)
++{
++	struct ingenic_pinctrl_group *groups;
++	struct ingenic_pinctrl_func *functions;
++	unsigned int grp_cnt = 0, func_cnt = 0;
++
++	groups = ingenic_pinctrl_create_groups(pctl->dev, &grp_cnt);
++	if (IS_ERR(groups)) {
++		dev_err(pctl->dev, "failed to parse pin groups\n");
++		return PTR_ERR(groups);
++	}
++
++	functions = ingenic_pinctrl_create_functions(pctl->dev, &func_cnt);
++	if (IS_ERR(functions)) {
++		dev_err(pctl->dev, "failed to parse pin functions\n");
++		return PTR_ERR(groups);
++	}
++
++	pctl->groups = groups;
++	pctl->num_groups = grp_cnt;
++	pctl->functions = functions;
++	pctl->num_funs = func_cnt;
++	return 0;
++}
++
++static int ingenic_pinctrl_register(struct ingenic_pinctrl *pctl)
++{
++	struct pinctrl_desc *pctl_desc = &pctl->pctl_desc;
++	struct pinctrl_pin_desc *pindesc, *pdesc;
++	char *pin_names;
++	unsigned chip, pin;
++	int ret;
++
++	pctl_desc->name = "ingenic pinctrl";
++	pctl_desc->owner = THIS_MODULE;
++	pctl_desc->pctlops = &ingenic_pctl_ops;
++	pctl_desc->pmxops = &ingenic_pinmux_ops;
++	pctl_desc->confops = &ingenic_pinconf_ops;
++	pctl_desc->npins = pctl->total_pins;
++	pindesc = devm_kzalloc(pctl->dev,
++			sizeof(*pindesc) * pctl_desc->npins, GFP_KERNEL);
++	if (!pindesc)
++		return -ENOMEM;
++	pctl_desc->pins = pindesc;
++
++	for (pin = 0, pdesc = pindesc; pin < pctl_desc->npins; pin++, pdesc++)
++		pdesc->number = pin;
++
++	pin_names = devm_kzalloc(pctl->dev,
++			sizeof(char) * PIN_NAMES_LEN * pctl_desc->npins,
++			GFP_KERNEL);
++	if (!pin_names)
++		return -ENOMEM;
++
++	for (chip = 0; chip < pctl->num_chips; chip++) {
++		struct ingenic_gpio_chip *jzgc = &pctl->gpio_chips[chip];
++		for (pin = 0; pin < jzgc->gc.ngpio; pin++) {
++			sprintf(pin_names, "%s-%d", jzgc->name, pin);
++			pdesc = pindesc++;
++			pdesc->name = pin_names;
++			pin_names += PIN_NAMES_LEN;
++		}
++	}
++
++	ret = ingenic_pinctrl_parse_dt(pctl);
++	if (ret)
++		return ret;
++
++	pctl->pctl_dev = pinctrl_register(pctl_desc, pctl->dev, pctl);
++	if (!pctl->pctl_dev)
++		return -EINVAL;
++
++	for (chip = 0; chip < pctl->num_chips; chip++) {
++		struct ingenic_gpio_chip *jzgc = &pctl->gpio_chips[chip];
++
++		jzgc->grange.name = jzgc->name;
++		jzgc->grange.id = jzgc->idx;
++		jzgc->grange.pin_base = jzgc->gc.base;
++		jzgc->grange.base = jzgc->gc.base;
++		jzgc->grange.npins = jzgc->gc.ngpio;
++		jzgc->grange.gc = &jzgc->gc;
++		pinctrl_add_gpio_range(pctl->pctl_dev, &jzgc->grange);
++	}
++
++	return 0;
++}
++
++static ssize_t dump_gpio(struct device *dev,
++		struct device_attribute *attr,
++		char *buf)
++{
++	struct ingenic_pinctrl *pctl = dev_get_drvdata(dev);
++	struct ingenic_gpio_chip *gpio_chips = pctl->gpio_chips;
++	const struct ingenic_priv *priv = pctl->priv;
++	int idx;
++	ssize_t len = 0;
++
++	/*1. Table Header */
++
++	len += snprintf(buf + len, PAGE_SIZE - len, "REG \t|");
++	for (idx = 0;  idx < pctl->num_chips; idx++)
++		len += snprintf(buf + len, PAGE_SIZE - len, "+++GP%c++|",
++				'A' + idx);
++	len += snprintf(buf+len, PAGE_SIZE - len, "\n\n");
++
++	/*2. INL Level*/
++	len += snprintf(buf + len, PAGE_SIZE - len, "INL \t|");
++	for (idx = 0;  idx < pctl->num_chips; idx++)
++		len += snprintf(buf + len, PAGE_SIZE - len, "%08x|",
++				ingenic_gpio_readl(&gpio_chips[idx], PxPIN));
++	len += snprintf(buf+len, PAGE_SIZE - len, "\n");
++
++	/*3. INT register*/
++	len += snprintf(buf + len, PAGE_SIZE - len, "INT \t|");
++	for (idx = 0;  idx < pctl->num_chips; idx++)
++		len += snprintf(buf + len, PAGE_SIZE - len, "%08x|",
++				ingenic_gpio_readl(&gpio_chips[idx], PxINT));
++	len += snprintf(buf+len, PAGE_SIZE - len, "\n");
++
++	/*4. MSK register*/
++	len += snprintf(buf + len, PAGE_SIZE - len, "MSK \t|");
++	for (idx = 0;  idx < pctl->num_chips; idx++)
++		len += snprintf(buf + len, PAGE_SIZE - len, "%08x|",
++				ingenic_gpio_readl(&gpio_chips[idx], PxMSK));
++	len += snprintf(buf+len, PAGE_SIZE - len, "\n");
++
++	/*5. PAT1 Register*/
++	len += snprintf(buf + len, PAGE_SIZE - len, "PAT1 \t|");
++	for (idx = 0;  idx < pctl->num_chips; idx++)
++		len += snprintf(buf + len, PAGE_SIZE - len, "%08x|",
++				ingenic_gpio_readl(&gpio_chips[idx], PxPAT1));
++	len += snprintf(buf+len, PAGE_SIZE - len, "\n");
++
++	/*6. PAT0 Register*/
++	len += snprintf(buf + len, PAGE_SIZE - len, "PAT0 \t|");
++	for (idx = 0;  idx < pctl->num_chips; idx++)
++		len += snprintf(buf + len, PAGE_SIZE - len, "%08x|",
++				ingenic_gpio_readl(&gpio_chips[idx], PxPAT0));
++	len += snprintf(buf+len, PAGE_SIZE - len, "\n");
++
++	/*7. EGE Register*/
++	len += snprintf(buf + len, PAGE_SIZE - len, "EDG \t|");
++	for (idx = 0;  idx < pctl->num_chips; idx++)
++		len += snprintf(buf + len, PAGE_SIZE - len, "%08x|",
++				ingenic_gpio_readl(&gpio_chips[idx], PxEDG));
++	len += snprintf(buf+len, PAGE_SIZE - len, "\n");
++
++
++	/*7. PULL/PULLUP/PULLDOWN */
++	if(!priv->pull_tristate) {
++		len += snprintf(buf + len, PAGE_SIZE - len, "PULL \t|");
++		for (idx = 0;  idx < pctl->num_chips; idx++)
++			len += snprintf(buf + len, PAGE_SIZE - len, "%08x|",
++					ingenic_gpio_readl(&gpio_chips[idx], PxPEN));
++		len += snprintf(buf+len, PAGE_SIZE - len, "\n");
++	} else {
++		len += snprintf(buf + len, PAGE_SIZE - len, "PLUP \t|");
++		for (idx = 0;  idx < pctl->num_chips; idx++)
++			len += snprintf(buf + len, PAGE_SIZE - len, "%08x|",
++					ingenic_gpio_readl(&gpio_chips[idx], PxPU));
++		len += snprintf(buf+len, PAGE_SIZE - len, "\n");
++
++		len += snprintf(buf + len, PAGE_SIZE - len, "PLDWN \t|");
++		for (idx = 0;  idx < pctl->num_chips; idx++)
++			len += snprintf(buf + len, PAGE_SIZE - len, "%08x|",
++					ingenic_gpio_readl(&gpio_chips[idx], PxPD));
++		len += snprintf(buf+len, PAGE_SIZE - len, "\n");
++
++	}
++	/*8. FLAG register */
++	len += snprintf(buf + len, PAGE_SIZE - len, "FLAG \t|");
++	for (idx = 0;  idx < pctl->num_chips; idx++)
++		len += snprintf(buf + len, PAGE_SIZE - len, "%08x|",
++				ingenic_gpio_readl(&gpio_chips[idx], PxFLG));
++	len += snprintf(buf+len, PAGE_SIZE - len, "\n");
++
++	if (priv->dump_filter)
++		len += priv->dump_filter(pctl, buf+len, PAGE_SIZE - len);
++
++	unsigned char *func_map[] = {"F0", "F1", "F2", "F3", "Out0", "Out1", "In0", "In1"};
++	/* Pretty dump.*/
++	for (idx = 0; idx < pctl->num_chips; idx++) {
++		unsigned int pxint = ingenic_gpio_readl(&gpio_chips[idx], PxINT);
++		unsigned int pxmsk = ingenic_gpio_readl(&gpio_chips[idx], PxMSK);
++		unsigned int pxpat1 = ingenic_gpio_readl(&gpio_chips[idx], PxPAT1);
++		unsigned int pxpat0 = ingenic_gpio_readl(&gpio_chips[idx], PxPAT0);
++		unsigned int level = ingenic_gpio_readl(&gpio_chips[idx], PxPIN);
++		int i = 0;
++		for(i = 0; i < 32; i++) {
++			unsigned int func = ((pxint >> i) & 1) << 3 |
++					    ((pxmsk >> i) & 1) << 2 |
++					    ((pxpat1 >> i)& 1) << 1 |
++					    ((pxpat0 >> i)& 1) << 0;
++			unsigned pin = (level >> i) & 1;
++
++			func = func < 6 ? func: 6 + pin;
++			if(func < 4) {
++				len += sprintf(buf + len, "P%c%02d:%s,%s\n", 'A' + idx, i, func_map[func], pin ? "High":"Low");
++			} else {
++				len += sprintf(buf + len, "P%c%02d:%s\n", 'A' + idx, i, func_map[func]);
++			}
++		}
++	}
++
++	return len;
++}
++static DEVICE_ATTR(dump_gpio, 0444, dump_gpio, NULL);
++
++static struct attribute *ingenic_pinctrl_attrs[] = {
++	&dev_attr_dump_gpio.attr,
++	NULL,
++};
++
++static const struct attribute_group ingenic_pinctrl_attr_group = {
++	.attrs = (struct attribute **)ingenic_pinctrl_attrs,
++};
++
++
++static int ingenic_pinctrl_probe(struct platform_device *pdev)
++{
++	struct ingenic_pinctrl *pctl;
++	const struct of_device_id *match;
++	struct resource *res;
++	int ret;
++
++	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
++	if (!pctl)
++		return -ENOMEM;
++	match = of_match_node(ingenic_pinctrl_dt_match, pdev->dev.of_node);
++	if (!match)
++		return -ENODEV;
++
++	pctl->priv = !match->data ? common_priv_data : (struct ingenic_priv *)match->data;
++	pctl->dev = &pdev->dev;
++	pctl->of_node = pdev->dev.of_node;
++
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res)
++		return -ENOMEM;
++
++	pctl->io_base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(pctl->io_base))
++		return PTR_ERR(pctl->io_base);
++
++	platform_set_drvdata(pdev, pctl);
++
++	ret = ingenic_gpiolib_register(pctl);
++	if (ret)
++		return ret;
++
++	ret = ingenic_pinctrl_register(pctl);
++	if (ret)
++		return ret;
++
++	ret = sysfs_create_group(&pdev->dev.kobj, &ingenic_pinctrl_attr_group);
++	if (ret)
++		dev_info(&pdev->dev, "ingenic pinctrl attr create failed\n");
++
++	#define CPM_EXCLK_DS 0xb00000E0
++	if(pctl->priv->voltage_switchable)
++	{
++		u32 voltage;
++		ret = of_property_read_u32(pdev->dev.of_node, "ingenic,gpa_voltage", &voltage);
++		if(!ret) {
++			if(voltage == GPIO_VOLTAGE_1V8)
++				*(volatile unsigned int *)CPM_EXCLK_DS |= (1 << 30);
++			if(voltage == GPIO_VOLTAGE_3V3)
++				*(volatile unsigned int *)CPM_EXCLK_DS &= ~(1 << 30);
++		}
++		ret = of_property_read_u32(pdev->dev.of_node, "ingenic,gpe_msc_voltage", &voltage);
++		if(!ret) {
++			if(voltage == GPIO_VOLTAGE_1V8)
++				*(volatile unsigned int *)CPM_EXCLK_DS |= (1 << 31);
++			if(voltage == GPIO_VOLTAGE_3V3)
++				*(volatile unsigned int *)CPM_EXCLK_DS &= ~(1 << 31);
++		}
++	}
++
++	gpctl = pctl;
++
++	dev_info(&pdev->dev, "ingenic pinctrl probe success\n");
++	return 0;
++}
++
++unsigned long ingenic_pinctrl_lock(int port)
++{
++	unsigned long flags;
++	struct ingenic_gpio_chip *chip;
++
++	if (port < 0 || port >= gpctl->num_chips)
++		return 0;
++
++	chip = &gpctl->gpio_chips[port];
++
++	spin_lock_irqsave(&chip->lock, flags);
++
++	return flags;
++}
++
++unsigned long ingenic_pinctrl_unlock(int port, unsigned long flags)
++{
++	struct ingenic_gpio_chip *chip;
++
++	if (port < 0 || port >= gpctl->num_chips)
++		return 0;
++
++	chip = &gpctl->gpio_chips[port];
++
++	spin_unlock_irqrestore(&chip->lock, flags);
++
++	return flags;
++}
++
++#ifdef CONFIG_PM_SLEEP
++#ifdef PINCTL_DEBUG
++static char dump_buf[PAGE_SIZE];
++static void dump_pinctl(void)
++{
++	struct ingenic_pinctrl *pctl = gpctl;
++	char *buf = dump_buf;
++	dump_gpio(pctl->dev, NULL, buf);
++	printk("%s\n", buf);
++}
++#else
++static void dump_pinctl(void) {}
++#endif
++
++static int ingenic_gpio_suspend_set(struct ingenic_gpio_chip *jzgc)
++{
++	const struct ingenic_priv *priv = jzgc->pctl->priv;
++	u32 pm_pull = 0, pm_high = 0, pm_low = 0, pm_nopull = 0, pm_pullup = 0, pm_pulldown = 0, pm_hiz = 0;
++
++	jzgc->pm_bitmap[PM_RESUME_INT] = ingenic_gpio_readl(jzgc, PxINT);
++	jzgc->pm_bitmap[PM_RESUME_MSK] = ingenic_gpio_readl(jzgc, PxMSK);
++	jzgc->pm_bitmap[PM_RESUME_PAT0] = ingenic_gpio_readl(jzgc, PxPAT0);
++	jzgc->pm_bitmap[PM_RESUME_PAT1] = ingenic_gpio_readl(jzgc, PxPAT1);
++
++	if(!priv->pull_tristate) {
++		jzgc->pm_bitmap[PM_RESUME_PULL] = ingenic_gpio_readl(jzgc, PxPEN);
++		pm_pull = jzgc->pm_bitmap[PM_SLEEP_PULL] & (~(jzgc->wakeup_bitmap));
++		pm_nopull = jzgc->pm_bitmap[PM_SLEEP_NOPULL] & (~(jzgc->wakeup_bitmap));
++	} else {
++		jzgc->pm_bitmap[PM_RESUME_PULLUP] = ingenic_gpio_readl(jzgc, PxPU);
++		jzgc->pm_bitmap[PM_RESUME_PULLDOWN] = ingenic_gpio_readl(jzgc, PxPD);
++
++		pm_pullup = jzgc->pm_bitmap[PM_SLEEP_PULLUP] & (~(jzgc->wakeup_bitmap));
++		pm_pulldown = jzgc->pm_bitmap[PM_SLEEP_PULLDOWN] & (~(jzgc->wakeup_bitmap));
++	}
++
++	pm_high = jzgc->pm_bitmap[PM_SLEEP_HIGH] & (~(jzgc->wakeup_bitmap));
++	pm_low 	= jzgc->pm_bitmap[PM_SLEEP_LOW] & (~(jzgc->wakeup_bitmap));
++	pm_hiz	= jzgc->pm_bitmap[PM_SLEEP_HIZ] & (~(jzgc->wakeup_bitmap));
++
++	if (pm_pull) {
++		ingenic_gpio_set_func(jzgc, priv->have_shadow, GPIO_INPUT, pm_pull);
++		ingenic_gpio_set_pull(jzgc, pm_pull, true);
++	}
++	if (pm_nopull) {
++		ingenic_gpio_set_func(jzgc, priv->have_shadow, GPIO_INPUT, pm_nopull);
++		ingenic_gpio_set_pull(jzgc, pm_nopull, false);
++	}
++
++	if(pm_pullup) {
++		ingenic_gpio_set_func(jzgc, priv->have_shadow, GPIO_INPUT, pm_pullup);
++		ingenic_gpio_set_pull(jzgc, pm_pullup, INGENIC_GPIO_PULLUP);
++	}
++	if(pm_pulldown) {
++		ingenic_gpio_set_func(jzgc, priv->have_shadow, GPIO_INPUT, pm_pulldown);
++		ingenic_gpio_set_pull(jzgc, pm_pulldown, INGENIC_GPIO_PULLDOWN);
++	}
++	if(pm_hiz) {
++		ingenic_gpio_set_func(jzgc, priv->have_shadow, GPIO_INPUT, pm_hiz);
++		ingenic_gpio_set_pull(jzgc, pm_hiz, INGENIC_GPIO_HIZ);
++	}
++
++	if (pm_high)
++		ingenic_gpio_set_func(jzgc, priv->have_shadow, GPIO_OUTPUT1, pm_high);
++	if (pm_low)
++		ingenic_gpio_set_func(jzgc, priv->have_shadow, GPIO_OUTPUT0, pm_low);
++
++	return 0;
++}
++
++static int ingenic_pinctrl_suspend(void)
++{
++	struct ingenic_pinctrl *pctl = gpctl;
++	int idx;
++
++	if (!gpctl)
++		return 0;
++	dump_pinctl();
++	for (idx = 0; idx < pctl->num_chips; idx++) {
++		struct ingenic_gpio_chip *chip = &pctl->gpio_chips[idx];
++		ingenic_gpio_suspend_set(chip);
++		chip->resume_pending = 0;
++	}
++
++	dump_pinctl();
++	return 0;
++}
++
++static void ingenic_check_wakeup_gpio(struct ingenic_gpio_chip *jzgc)
++{
++	u32 pend, mask;
++
++	pend = ingenic_gpio_readl(jzgc, PxFLG);
++	mask = ingenic_gpio_readl(jzgc, PxMSK);
++	pend = pend & ~mask;
++	pend = pend & jzgc->wakeup_bitmap;
++	if(pend) {
++		jzgc->resume_pending = pend;
++		jzgc->sleep_level = ingenic_gpio_readl(jzgc, PxPAT0) & pend;
++	}
++}
++
++static void ingenic_pinctrl_resume(void)
++{
++	struct ingenic_pinctrl *pctl = gpctl;
++	int idx;
++
++	if (!gpctl)
++		return;
++	for (idx = 0; idx < pctl->num_chips; idx++) {
++		struct ingenic_gpio_chip *jzgc = &pctl->gpio_chips[idx];
++		const struct ingenic_priv *priv = jzgc->pctl->priv;
++		ingenic_check_wakeup_gpio(jzgc);
++		ingenic_gpio_writel(jzgc, PxINT, jzgc->pm_bitmap[PM_RESUME_INT]);
++		ingenic_gpio_writel(jzgc, PxMSK, jzgc->pm_bitmap[PM_RESUME_MSK]);
++		ingenic_gpio_writel(jzgc, PxPAT0, jzgc->pm_bitmap[PM_RESUME_PAT0]);
++		ingenic_gpio_writel(jzgc, PxPAT1, jzgc->pm_bitmap[PM_RESUME_PAT1]);
++		if(!priv->pull_tristate) {
++			ingenic_gpio_writel(jzgc, PxPEN, jzgc->pm_bitmap[PM_RESUME_PULL]);
++		} else {
++			ingenic_gpio_writel(jzgc, PxPU, jzgc->pm_bitmap[PM_RESUME_PULLUP]);
++			ingenic_gpio_writel(jzgc, PxPD, jzgc->pm_bitmap[PM_RESUME_PULLDOWN]);
++		}
++	}
++}
++#else
++#define ingenic_pinctrl_suspend	NULL
++#define ingenic_pinctrl_resume	NULL
++#endif
++
++static struct syscore_ops ingenic_pinctrl_syscore_ops = {
++	.suspend = ingenic_pinctrl_suspend,
++	.resume = ingenic_pinctrl_resume,
++};
++
++static const struct ingenic_priv common_priv_data[] = {
++	{
++		.have_shadow = true,
++		.pullen_set = false,
++	},
++};
++
++static const struct ingenic_priv x1800_priv_data[] = {
++	{
++		.have_shadow = true,
++		.pullen_set = true,
++	},
++};
++
++static const struct ingenic_priv x1021_priv_data[] = {
++	{
++		.have_shadow = true,
++		.pullen_set = true,
++	},
++};
++
++static const struct ingenic_priv x1520_priv_data[] = {
++	{
++		.have_shadow = true,
++		.pullen_set = true,
++	},
++};
++
++static const struct ingenic_priv x1600_priv_data[] = {
++	{
++		.have_shadow = true,
++		.pullen_set = true,
++		.dual_edge_interrupt = true,
++	},
++};
++
++static const struct ingenic_priv x1630_priv_data[] = {
++	{
++		.have_shadow = true,
++		.pullen_set = true,
++	},
++};
++
++static const struct ingenic_priv x2000_priv_data[] = {
++	{
++		.have_shadow = true,
++		.pull_tristate = true,
++		.voltage_switchable = true,
++		.dual_edge_interrupt = true,
++		.have_ds = true,	// support driver strength settings.
++		.have_slew = true,
++		.have_schmit = true,
++	},
++};
++
++static const struct ingenic_priv x2500_priv_data[] = {
++	{
++		.have_shadow = true,
++		.pull_tristate = true,
++		.have_ds = true,	// support drive strength settings.
++		.have_slew = true,
++		.have_schmit = true,
++	},
++};
++
++static const struct ingenic_priv m300_priv_data[] = {
++	{
++		.have_shadow = true,
++		.pull_tristate = true,
++		.voltage_switchable = true,
++		.dual_edge_interrupt = true,
++		.have_ds = true,
++	},
++};
++
++
++static const struct of_device_id ingenic_pinctrl_dt_match[] = {
++	{ .compatible = "ingenic,x1000-pinctrl", .data = (void *)common_priv_data},
++	{ .compatible = "ingenic,x1800-pinctrl", .data = (void *)x1800_priv_data},
++	{ .compatible = "ingenic,x1021-pinctrl", .data = (void *)x1021_priv_data},
++	{ .compatible = "ingenic,x1520-pinctrl", .data = (void *)x1520_priv_data},
++	{ .compatible = "ingenic,x1600-pinctrl", .data = (void *)x1600_priv_data},
++	{ .compatible = "ingenic,x1630-pinctrl", .data = (void *)x1630_priv_data},
++	{ .compatible = "ingenic,x2000-pinctrl", .data = (void *)x2000_priv_data},
++	{ .compatible = "ingenic,m300-pinctrl", .data = (void *)m300_priv_data},
++	{ .compatible = "ingenic,x2500-pinctrl", .data = (void *)x2500_priv_data},
++	{},
++};
++MODULE_DEVICE_TABLE(of, ingenic_pinctrl_dt_match);
++
++static struct platform_driver ingenic_pinctrl_drv = {
++	.probe = ingenic_pinctrl_probe,
++	.driver = {
++		.name = "ingenic pinctrl",
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(ingenic_pinctrl_dt_match),
++	},
++};
++
++static int __init ingenic_pinctrl_drv_init(void)
++{
++	register_syscore_ops(&ingenic_pinctrl_syscore_ops);
++	return platform_driver_register(&ingenic_pinctrl_drv);
++}
++postcore_initcall(ingenic_pinctrl_drv_init);
++
++static void __exit ingenic_pinctrl_drv_exit(void)
++{
++	unregister_syscore_ops(&ingenic_pinctrl_syscore_ops);
++	platform_driver_unregister(&ingenic_pinctrl_drv);
++	return;
++}
++module_exit(ingenic_pinctrl_drv_exit);
++
++
++int mcu_gpio_register(unsigned int ggpio, unsigned int reg)
++{
++	struct ingenic_pinctrl *pctl = gpctl;
++	struct ingenic_gpio_chip *jzgc = NULL;
++	if (!gpctl)
++		return -ENODEV;
++	jzgc = &pctl->gpio_chips[ggpio];
++	jzgc->mcu_gpio_reg = (unsigned int *)reg;
++	return 0;
++}
++EXPORT_SYMBOL_GPL(mcu_gpio_register);
++
++void mcu_gpio_unregister(unsigned int ggpio)
++{
++	struct ingenic_pinctrl *pctl = gpctl;
++	struct ingenic_gpio_chip *jzgc = NULL;
++
++	if (!gpctl)
++		return;
++	jzgc = &pctl->gpio_chips[ggpio];
++	jzgc->mcu_gpio_reg = NULL;
++}
++EXPORT_SYMBOL_GPL(mcu_gpio_unregister);
++
++MODULE_AUTHOR("cli <chen.li@ingenic.com>");
++MODULE_DESCRIPTION("Ingenic pinctrl driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:pinctrl");
+diff --git a/module_drivers/drivers/pinctrl/pinctrl-ingenic.h b/module_drivers/drivers/pinctrl/pinctrl-ingenic.h
+new file mode 100644
+index 000000000..6890fff38
+--- /dev/null
++++ b/module_drivers/drivers/pinctrl/pinctrl-ingenic.h
+@@ -0,0 +1,370 @@
++/*
++ * pinctrl/ingenic/pinctrl-ingenic.c
++ *
++ * Copyright 2015 Ingenic Semiconductor Co.,Ltd
++ *
++ * Author: cli <chen.li@inegnic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef __PINCTRL_INGENIC_H__
++#define __PINCTRL_INGENIC_H__
++
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/irqdomain.h>
++#include <linux/gpio.h>
++#include <linux/pinctrl/pinctrl.h>
++#include <dt-bindings/pinctrl/ingenic-pinctrl.h>
++#include <linux/types.h>
++#include <linux/bitops.h>
++#include "core.h"
++
++enum gpio_function {
++	GPIO_FUNC_0	= 0x00,  //0000, GPIO as function 0 / device 0
++	GPIO_FUNC_1	= 0x01,  //0001, GPIO as function 1 / device 1
++	GPIO_FUNC_2	= 0x02,  //0010, GPIO as function 2 / device 2
++	GPIO_FUNC_3	= 0x03,  //0011, GPIO as function 3 / device 3
++	GPIO_OUTPUT0	= 0x04,  //0100, GPIO output low  level
++	GPIO_OUTPUT1	= 0x05,  //0101, GPIO output high level
++	GPIO_INPUT	= 0x06,  //0110, GPIO as input
++	GPIO_INT_LO 	= 0x08,  //1100, Low  Level trigger interrupt
++	GPIO_INT_HI 	= 0x09,  //1101, High Level trigger interrupt
++	GPIO_INT_FE 	= 0x0a,  //1110, Fall Edge trigger interrupt
++	GPIO_INT_RE 	= 0x0b,  //1111, Rise Edge trigger interrupt
++	GPIO_INT_RE_FE 	= 0x1a,  //Fall&Rise Edge trigger interrupt
++};
++
++#define PxPIN           0x00   /* PIN Level Register */
++#define PxINT           0x10   /* Port Interrupt Register */
++#define PxINTS          0x14   /* Port Interrupt Set Register */
++#define PxINTC          0x18   /* Port Interrupt Clear Register */
++#define PxMSK           0x20   /* Port Interrupt Mask Reg */
++#define PxMSKS          0x24   /* Port Interrupt Mask Set Reg */
++#define PxMSKC          0x28   /* Port Interrupt Mask Clear Reg */
++#define PxPAT1          0x30   /* Port Pattern 1 Set Reg. */
++#define PxPAT1S         0x34   /* Port Pattern 1 Set Reg. */
++#define PxPAT1C         0x38   /* Port Pattern 1 Clear Reg. */
++#define PxPAT0          0x40   /* Port Pattern 0 Register */
++#define PxPAT0S         0x44   /* Port Pattern 0 Set Register */
++#define PxPAT0C         0x48   /* Port Pattern 0 Clear Register */
++#define PxFLG           0x50   /* Port Flag Register */
++#define PxFLGC          0x58   /* Port Flag clear Register */
++
++/* TODO: move these regs to soc special. */
++
++#if defined(CONFIG_SOC_X1520)
++	#define PxPEN	0x60
++	#define PxPENS	0x64
++	#define PxPENC	0x68
++#elif defined(CONFIG_SOC_X1600)
++	#define PxPEN	0x70
++	#define PxPENS	0x74
++	#define PxPENC	0x78
++#else
++	#define PxPEN	-1
++	#define PxPENS	-1
++	#define PxPENC	-1
++#endif
++
++/* Note: Not All Socs have these regs. */
++#if defined(CONFIG_SOC_X2000_V12) || defined(CONFIG_SOC_X2000)	\
++    || defined(CONFIG_SOC_X2100) || defined(CONFIG_SOC_M300)	\
++    || defined(CONFIG_SOC_X1600)
++	#define PxEDG		0x70	/* PORT Dual-Edge Interrupt Register */
++	#define PxEDGS		0x74	/* PORT Dual-Edge Interrupt Register Set */
++	#define PxEDGC		0x78	/* PORT Dual-Edge Interrupt Register Clear */
++#else
++	#define PxEDG		-1
++	#define PxEDGS		-1
++	#define PxEDGC		-1
++#endif
++
++
++/* Soc Secial. X2000 s.*/
++#if defined(CONFIG_SOC_X2000_V12) || defined(CONFIG_SOC_X2000)	\
++    || defined(CONFIG_SOC_X2100) || defined(CONFIG_SOC_M300)	\
++    || defined(CONFIG_SOC_X1600)
++	#define PxPU		0x80	/* PORT PULL-UP State Register */
++	#define PxPUS		0x84	/* PORT PULL-UP State Register Set */
++	#define PxPUC		0x88	/* PORT PULL-UP State Register Clear */
++	#define PxPD		0x90	/* PORT PULL-DOWN State Register */
++	#define PxPDS		0x94	/* PORT PULL-DOWN State Register Set */
++	#define PxPDC		0x98	/* PORT PULL-DOWN State Register Clear */
++
++#elif defined(CONFIG_SOC_X2500)
++/* Soc Secial. T40/X2500 s.*/
++	#define PxPU		0x110	/* PORT PULL-UP State Register */
++	#define PxPUS		0x114	/* PORT PULL-UP State Register Set */
++	#define PxPUC		0x118	/* PORT PULL-UP State Register Clear */
++	#define PxPD		0x120	/* PORT PULL-DOWN State Register */
++	#define PxPDS		0x124	/* PORT PULL-DOWN State Register Set */
++	#define PxPDC		0x128	/* PORT PULL-DOWN State Register Clear */
++#else
++	#define PxPU		-1	/* PORT PULL-UP State Register */
++	#define PxPUS		-1	/* PORT PULL-UP State Register Set */
++	#define PxPUC		-1	/* PORT PULL-UP State Register Clear */
++	#define PxPD		-1	/* PORT PULL-DOWN State Register */
++	#define PxPDS		-1	/* PORT PULL-DOWN State Register Set */
++	#define PxPDC		-1	/* PORT PULL-DOWN State Register Clear */
++#endif
++
++
++#if defined(CONFIG_SOC_X2000_V12) || defined(CONFIG_SOC_X2000)	\
++    || defined(CONFIG_SOC_X2100) || defined(CONFIG_SOC_M300)
++/* Soc Special. X2000 */
++	#define PXDS0		0xA0   /* PORT Drive Strength State Register0*/
++	#define PXDS0S		0xA4   /* PORT Drive Strength State set Register0*/
++	#define PXDS0C		0xA8   /* PORT Drive Strength State clear Register0*/
++	#define PXDS1		0xB0   /* PORT Drive Strength State Register1*/
++	#define PXDS1S		0xB4   /* PORT Drive Strength State set Register1*/
++	#define PXDS1C		0xB8   /* PORT Drive Strength State clear Register1*/
++	#define PXDS2		0xC0   /* PORT Drive Strength State Register2*/
++	#define PXDS2S		0xC4   /* PORT Drive Strength State set Register2*/
++	#define PXDS2C		0xC8   /* PORT Drive Strength State clear Register2*/
++
++#elif defined(CONFIG_SOC_X2500)
++/* T40/X2500. */
++	#define PXDS0		0x130   /* PORT Drive Strength State Register0*/
++	#define PXDS0S		0x134   /* PORT Drive Strength State set Register0*/
++	#define PXDS0C		0x138   /* PORT Drive Strength State clear Register0*/
++	#define PXDS1		0x140   /* PORT Drive Strength State Register1*/
++	#define PXDS1S		0x144   /* PORT Drive Strength State set Register1*/
++	#define PXDS1C		0x148   /* PORT Drive Strength State clear Register1*/
++	#define PXDS2		0x150   /* PORT Drive Strength State Register2*/
++	#define PXDS2S		0x154   /* PORT Drive Strength State set Register2*/
++	#define PXDS2C		0x158   /* PORT Drive Strength State clear Register2*/
++#else
++	#define PXDS0		-1   /* PORT Drive Strength State Register0*/
++	#define PXDS0S		-1   /* PORT Drive Strength State set Register0*/
++	#define PXDS0C		-1   /* PORT Drive Strength State clear Register0*/
++	#define PXDS1		-1   /* PORT Drive Strength State Register1*/
++	#define PXDS1S		-1   /* PORT Drive Strength State set Register1*/
++	#define PXDS1C		-1   /* PORT Drive Strength State clear Register1*/
++	#define PXDS2		-1   /* PORT Drive Strength State Register2*/
++	#define PXDS2S		-1   /* PORT Drive Strength State set Register2*/
++	#define PXDS2C		-1   /* PORT Drive Strength State clear Register2*/
++#endif
++
++/* Soc Special. */
++
++#if defined(CONFIG_SOC_X2000_V12) || defined(CONFIG_SOC_X2000)	\
++    || defined(CONFIG_SOC_X2100) || defined(CONFIG_SOC_M300)
++	#define PxSR		0xD0    /* PORT Slew Rate Register */
++	#define PxSRS		0xD4	/* PORT Slew Rate Register Set */
++	#define PxSRC		0xD8	/* PORT Slew Rate Register Clear */
++#elif defined(CONFIG_SOC_X2500)
++	#define PxSR		0x160    /* PORT Slew Rate Register */
++	#define PxSRS		0x164	/* PORT Slew Rate Register Set */
++	#define PxSRC		0x168	/* PORT Slew Rate Register Clear */
++#else
++	#define PxSR		-1    /* PORT Slew Rate Register */
++	#define PxSRS		-1	/* PORT Slew Rate Register Set */
++	#define PxSRC		-1	/* PORT Slew Rate Register Clear */
++#endif
++
++#if defined(CONFIG_SOC_X2000_V12) || defined(CONFIG_SOC_X2000)	\
++    || defined(CONFIG_SOC_X2100) || defined(CONFIG_SOC_M300)
++	#define PxSMT		0xE0	/* PORT Schmitt Trigger Register */
++	#define PxSMTS		0xE4	/* PORT Schmitt Trigger Register Set */
++	#define PxSMTC		0xE8	/*  PORT Schmitt Trigger Register Clear */
++#elif defined(CONFIG_SOC_X2500)
++	#define PxSMT		0x170    /* PORT Slew Rate Register */
++	#define PxSMTS		0x174	/* PORT Slew Rate Register Set */
++	#define PxSMTC		0x178	/* PORT Slew Rate Register Clear */
++// TODO: X2500 has different schmit registers for GPC.
++
++#else
++	#define PxSMT		-1    /* PORT Slew Rate Register */
++	#define PxSMTS		-1	/* PORT Slew Rate Register Set */
++	#define PxSMTC		-1	/* PORT Slew Rate Register Clear */
++#endif
++
++
++#define PSHADOW_OFF(regsoffset)		(7*(regsoffset))
++#define PZGIDLD         0xF0   /* GPIOZ Group ID to load */
++
++#define PIN_NAMES_LEN		10
++#define MAX_GPIOS_ON_CHIP	32
++#define MAX_FUNCTIONS_ON_GPIO	4
++#define PIN_ARGS_FROM_INDEX	0
++#define PIN_ARGS_TO_INDEX	1
++#define PIN_ARGS_CFG_INDEX	2
++
++static inline u32 pin_bitmap(u32 from, u32 to)
++{
++	if (to == 31)
++		return ~((1<<(from))-1);
++	return ((~((1<<(from))-1))&((1 << ((to)+1))-1));
++}
++
++static inline unsigned bit_count(unsigned v)
++{
++	unsigned int c;
++	for (c = 0; v; c++)
++		v &= v - 1;
++	return c;
++}
++
++typedef enum ingenic_gpio_pm_arr {
++	PM_SLEEP_PULL = 0,	/*sleep state*/		/*input pull*/
++	PM_SLEEP_NOPULL,				/*input no pull*/
++	PM_SLEEP_PULLUP,				/*input pullup*/
++	PM_SLEEP_PULLDOWN,				/*input pulldown*/
++	PM_SLEEP_HIZ,					/*input hiz*/
++	PM_SLEEP_HIGH,					/*output high*/
++	PM_SLEEP_LOW,					/*output low*/
++	PM_RESUME_INT,		/*keep register for resume*/
++	PM_RESUME_MSK,
++	PM_RESUME_PAT0,
++	PM_RESUME_PAT1,
++	PM_RESUME_PULL,
++	PM_RESUME_PULLUP,
++	PM_RESUME_PULLDOWN,
++	PM_STATE_CNT,
++} ingenic_gpio_pm_arr_t;
++
++/*ingenic gpio chip*/
++struct ingenic_gpio_chip {
++	struct gpio_chip		gc;
++	char				name[4];			/*name format "GPX"(X = 'A' + idx)*/
++	u8				idx;				/*gpio index of this chip*/
++	const struct device_node	*of_node;			/*gpio chip device node*/
++	int				irq;				/*gpio chip irq*/
++	struct irq_domain		*irq_domain;
++	struct pinctrl_gpio_range	grange;
++	struct ingenic_pinctrl		*pctl;
++	spinlock_t			lock;				/*gpio func write lock*/
++	u32				*mcu_gpio_reg;			/*used for gpio irq to mcu
++									  mcu's pending register*/
++	u32				used_pins_bitmap;			/*bitmap of pins for been had requested*/
++	u32				resume_pending;			/*bitmap of pins wakeup pending when sleep*/
++	u32				sleep_level;			/*bitmap of pins level when sleep*/
++	u32				filter_bitmap;			/*bitmap of pins filter support*/
++	u32				pull_bitmap;			/*bitmap of pins pill support*/
++	u32				wakeup_bitmap;			/*bitmap of pins wakeup pins*/
++	u32				pm_irq_bitmap;			/*bitmap of pins used for irq sleep&resume*/
++	u32				pm_bitmap[PM_STATE_CNT];	/*bitmap of pins used for sleep&resume*/
++};
++
++#define gc_to_ingenic_gc(gpiochip) container_of(gpiochip, struct ingenic_gpio_chip, gc)
++
++/*function information*/
++struct ingenic_pinctrl_func {
++	const char              *name;
++	struct device_node	*of_node;	/* function device node */
++	const char              **groups;	/* all sub groups name*/
++	u8                      num_groups;	/* num groups of this function */
++};
++
++/*group information*/
++struct ingenic_pinctrl_group {
++	const char              *name;
++	struct device_node	*of_node;	/* group device node */
++	struct gpio_chip	*gc;		/* corresponding gpio chip*/
++	unsigned		*pins;		/* Contained pins software gpio num*/
++	u8                      num_pins;	/* num gpios of the set group*/
++	u32			pinmux_bitmap;	/* pins bitmap of this group*/
++	enum gpio_function	pinmux_func;	/* pins function select of this group*/
++};
++
++
++struct soc_special_regs {
++	unsigned int reg; 		/* register offset */
++	unsigned int reg_set;		/* register set offset */
++	unsigned int reg_clear;		/* register clear offset */
++};
++
++/*soc private data*/
++struct ingenic_priv {
++	bool				have_shadow;		/*support shadow register or not*/
++	bool				have_filter;		/*support input pin filter of nor*/
++	bool				pullen_set;		/*set bit to enable pull function.*/
++	bool				voltage_switchable;	/*ports support 1.8v and 3.3v switch.*/
++	bool				dual_edge_interrupt ;	/*support Dual-Edge Interrupt.*/
++	bool				pull_tristate;		/*support pullup/pulldown/hiz settable.*/
++	bool				have_ds;		/*support drive strength settings.*/
++	bool				have_slew;		/*support drive strength settings.*/
++	bool				have_schmit;		/*support drive strength settings.*/
++	int (*set_filter)(struct ingenic_gpio_chip *jzgc,	/*set input pin filter function*/
++			unsigned pin,
++			u16 filter);
++	ssize_t (*dump_filter)(struct ingenic_pinctrl *pctl,
++			char *buf,
++			ssize_t size);
++};
++
++struct ingenic_pinctrl {
++	void __iomem			*io_base;
++	struct device_node		*of_node;		/*pinctrl device_node*/
++	struct device			*dev;
++
++	spinlock_t			shadow_lock;		/*shadow register access lock*/
++	struct ingenic_gpio_chip	*gpio_chips;		/*gpio chips of this pinctrl*/
++	unsigned			num_chips;		/*num gpio chips*/
++	unsigned			total_pins;		/*total pins of this pinctrl*/
++	u32				*bitmap_priv;		/*******private*******/
++
++	struct pinctrl_desc		pctl_desc;
++	struct pinctrl_dev		*pctl_dev;
++
++	struct ingenic_pinctrl_group	*groups;
++	unsigned			num_groups;
++
++	struct ingenic_pinctrl_func	*functions;
++	unsigned			num_funs;
++	u32				group_regs_offset;		/* gpio group regs offset get from dts  */
++
++	const struct ingenic_priv		*priv;			/*soc data*/
++};
++
++static inline struct ingenic_pinctrl_group *find_group_by_of_node(
++		struct ingenic_pinctrl *pctl, struct device_node *np)
++{
++	int i;
++	for (i = 0; i < pctl->num_groups; i++) {
++		if (pctl->groups[i].of_node == np)
++			return &pctl->groups[i];
++	}
++	return NULL;
++}
++
++static inline struct ingenic_pinctrl_func *find_func_by_of_node(
++		struct ingenic_pinctrl *pctl, struct device_node *np)
++{
++	int i;
++	for (i = 0; i < pctl->num_funs; i++) {
++		if (pctl->functions[i].of_node == np)
++			return &pctl->functions[i];
++	}
++	return NULL;
++}
++
++static inline u32 ingenic_gpio_readl(struct ingenic_gpio_chip *chip, int offset)
++{
++	struct ingenic_pinctrl *pctl = chip->pctl;
++	return readl(pctl->io_base + (chip->idx * pctl->group_regs_offset) + offset);
++}
++
++static inline void ingenic_gpio_writel(struct ingenic_gpio_chip *chip, int offset, int value)
++{
++	struct ingenic_pinctrl *pctl = chip->pctl;
++	writel(value , pctl->io_base + (chip->idx * pctl->group_regs_offset) + offset);
++}
++
++static inline void ingenic_gpio_shadow_fill(struct ingenic_gpio_chip *chip, int offset, int value)
++{
++	struct ingenic_pinctrl *pctl = chip->pctl;
++	writel(value, pctl->io_base + PSHADOW_OFF(pctl->group_regs_offset)+ offset);
++}
++
++static inline void ingenic_gpio_shadow_writel(struct ingenic_gpio_chip *chip)
++{
++	struct ingenic_pinctrl *pctl = chip->pctl;
++	writel(chip->idx, pctl->io_base + PSHADOW_OFF(pctl->group_regs_offset) + PZGIDLD);
++}
++#endif /*__PINCTRL_INGENIC_H__*/
+diff --git a/module_drivers/drivers/power/Makefile b/module_drivers/drivers/power/Makefile
+new file mode 100644
+index 000000000..26ddaaf28
+--- /dev/null
++++ b/module_drivers/drivers/power/Makefile
+@@ -0,0 +1 @@
++obj-y += supply/
+diff --git a/module_drivers/drivers/power/supply/Makefile b/module_drivers/drivers/power/supply/Makefile
+new file mode 100644
+index 000000000..0ee78a091
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_KP_AXP)       += axp_power/
+diff --git a/module_drivers/drivers/power/supply/axp_power/Kconfig b/module_drivers/drivers/power/supply/axp_power/Kconfig
+new file mode 100644
+index 000000000..b5752720b
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/Kconfig
+@@ -0,0 +1,37 @@
++menuconfig KP_AXP
++	bool "AXP Power drivers"
++	depends on REGULATOR
++	default n
++	help
++	  This option allows you to select AXP power driver
++
++if KP_AXP
++
++choice
++	prompt "AXP PMU type"
++	default AXP216
++
++config AXP216
++	bool "AXP216 driver"
++	help
++	  AXP216 driver
++
++endchoice
++
++config AXP_DEBUG
++	bool "AXP debug interface"
++	default n
++
++config KP_OUTPUTINIT
++	bool "AXP output init"
++	default n
++
++config AXP_CHARGEINIT
++	bool "AXP initial charging environment set"
++	default y
++
++config AXP_CHGCHANGE
++	bool "AXP charging current set when suspend\resume\shutdown"
++	default y
++
++endif # !KP_AXP
+diff --git a/module_drivers/drivers/power/supply/axp_power/Makefile b/module_drivers/drivers/power/supply/axp_power/Makefile
+new file mode 100644
+index 000000000..8c151d85f
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/Makefile
+@@ -0,0 +1,12 @@
++obj-y += axp-mfd.o
++
++#Make this built-in, so that it will be loaded before I2C driver
++
++#obj-$(CONFIG_KP_AXP) += axp-board.o
++obj-$(CONFIG_KP_AXP) += axp-regu.o
++obj-$(CONFIG_KP_AXP) += axp-sply.o
++#obj-$(CONFIG_KP_AXP) += axp-gpio.o
++obj-$(CONFIG_KP_AXP) += virtual216_dev.o
++obj-$(CONFIG_KP_AXP) += virtual216.o
++
++
+diff --git a/module_drivers/drivers/power/supply/axp_power/axp-board.c b/module_drivers/drivers/power/supply/axp_power/axp-board.c
+new file mode 100644
+index 000000000..a2bbecaea
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/axp-board.c
+@@ -0,0 +1,476 @@
++/*
++ * Base driver for X-Powers AXP
++ *
++ * Copyright (C) 2013 X-Powers, Ltd.
++ *  Zhang Donglu <zhangdonglu@x-powers.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/machine.h>
++#include <linux/i2c.h>
++//#include <mach/irqs.h>
++#include <linux/power_supply.h>
++#include <linux/apm_bios.h>
++#include <linux/apm-emulation.h>
++#include <linux/module.h>
++
++#include "axp-cfg.h"
++#include "axp-mfd.h"
++//#include "axp216-regu.h"
++
++/* Reverse engineered partly from Platformx drivers */
++enum axp_regls{
++
++	rtcldo,
++	aldo1,
++	aldo2,
++	aldo3,
++
++	eldo1,
++	eldo2,
++
++
++	dcdc1,
++	dcdc2,
++	dcdc3,
++	dcdc4,
++	dcdc5,
++
++	gpioldo1,
++
++};
++
++/* The values of the various regulator constraints are obviously dependent
++ * on exactly what is wired to each ldo.  Unfortunately this information is
++ * not generally available.  More information has been requested from Xbow
++ * but as of yet they haven't been forthcoming.
++ *
++ * Some of these are clearly Stargate 2 related (no way of plugging
++ * in an lcd on the IM2 for example!).
++ */
++
++static struct regulator_consumer_supply rtcldo_data[] = {
++		{
++			.supply = "rtcldo",
++		},
++	};
++
++
++static struct regulator_consumer_supply aldo1_data[] = {
++		{
++			.supply = "aldo1",    ///vcc_18
++		},
++	};
++
++static struct regulator_consumer_supply aldo2_data[] = {
++		{
++			.supply = "aldo2",   ///vdd_10
++		},
++	};
++
++static struct regulator_consumer_supply aldo3_data[] = {
++		{
++			.supply = "aldo3",   ///vcca_codec 3.3v
++		},
++	};
++
++static struct regulator_consumer_supply eldo1_data[] = {
++		{
++			.supply = "eldo1",  //vccio_pmu 3.3v
++		},
++	};
++
++
++static struct regulator_consumer_supply eldo2_data[] = {
++		{
++			.supply = "eldo2",  //vcc_tp 3.3v
++		},
++	};
++
++static struct regulator_consumer_supply gpioldo1_data[] = {
++		{
++			.supply = "gpio_ldo1",   //VCC18_LCD 1.8V
++		},
++	};
++
++static struct regulator_consumer_supply dcdc1_data[] = {
++		{
++			.supply = "dcdc1",     //vcc_io  3.3v
++		},
++	};
++
++static struct regulator_consumer_supply dcdc2_data[] = {
++		{
++			.supply = "dcdc2",   //vdd_cpu_fb vcc_20 2.0v
++		},
++	};
++
++static struct regulator_consumer_supply dcdc3_data[] = {
++		{
++			.supply = "dcdc3",    //vdd_cpu_fb vccio_lcd  3.3v
++		},
++	};
++
++static struct regulator_consumer_supply dcdc4_data[] = {
++		{
++			.supply = "dcdc4",    //vcclog 1.0v   x
++		},
++	};
++
++static struct regulator_consumer_supply dcdc5_data[] = {
++		{
++			//.supply = "DCDC5",   //vcc_ddr  1.2v
++			.supply = "dcdc5",
++		},
++	};
++
++static struct regulator_init_data axp_regl_init_data[] = {
++	[rtcldo] = {
++		.constraints = {
++			.name = "rtcldo",
++			.min_uV =  AXP_LDO1_MIN,
++			.max_uV =  AXP_LDO1_MAX,
++			.always_on = 1,
++			.boot_on = 1,
++			.apply_uV = 1,
++		},
++		.num_consumer_supplies = ARRAY_SIZE(rtcldo_data),
++		.consumer_supplies = rtcldo_data,
++	},
++	[aldo1] = {
++		.constraints = {
++			.name = "ALDO1",
++			.min_uV = AXP_ALDO1_MIN,
++			.max_uV = AXP_ALDO1_MAX,
++			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
++#if defined (CONFIG_KP_OUTPUTINIT)
++			.initial_state = PM_SUSPEND_STANDBY,
++			.state_standby = {
++				.uV = AXP_ALDO1_VALUE * 1000,
++				.enabled = 1,
++			}
++#endif
++			.always_on = 1,
++			.boot_on = 1,
++			.apply_uV = 1,
++		},
++		.num_consumer_supplies = ARRAY_SIZE(aldo1_data),
++		.consumer_supplies = aldo1_data,
++	},
++	[aldo2] = {
++		.constraints = {
++			.name = "ALDO2",
++			.min_uV =  AXP_ALDO2_MIN,
++			.max_uV =  AXP_ALDO2_MAX,
++			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
++#if defined (CONFIG_KP_OUTPUTINIT)
++			.initial_state = PM_SUSPEND_STANDBY,
++			.state_standby = {
++				.uV = AXP_ALDO2_VALUE * 1000,
++				.enabled = 1,
++			}
++#endif
++			.always_on = 1,
++			.boot_on = 1,
++			.apply_uV = 1,
++		},
++		.num_consumer_supplies = ARRAY_SIZE(aldo2_data),
++		.consumer_supplies = aldo2_data,
++	},
++	[aldo3] = {
++		.constraints = {
++			.name = "axp_aldo3",
++			.min_uV = AXP_ALDO3_MIN,
++			.max_uV = AXP_ALDO3_MAX,
++			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
++#if defined (CONFIG_KP_OUTPUTINIT)
++			.initial_state = PM_SUSPEND_STANDBY,
++			.state_standby = {
++				.uV = AXP_ALDO3_VALUE * 1000,
++				.enabled = 1,
++			}
++#endif
++			.always_on = 0,
++			.boot_on = 0,
++			.apply_uV = 1,
++		},
++		.num_consumer_supplies = ARRAY_SIZE(aldo3_data),
++		.consumer_supplies = aldo3_data,
++	},
++	
++	[eldo1] = {
++		.constraints = {
++			.name = "axp_eldo1",
++			.min_uV = AXP_ELDO1_MIN,
++			.max_uV = AXP_ELDO1_MAX,
++			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
++#if defined (CONFIG_KP_OUTPUTINIT)
++			.initial_state = PM_SUSPEND_STANDBY,
++			.state_standby = {
++				.uV = AXP_ELDO1_VALUE * 1000,
++				.enabled = 1,
++			}
++#endif
++			.always_on = 1,
++			.boot_on = 1,
++			.apply_uV = 1,
++		},
++		.num_consumer_supplies = ARRAY_SIZE(eldo1_data),
++		.consumer_supplies = eldo1_data,
++	},
++	[eldo2] = {
++		.constraints = {
++			.name = "axp_eldo2",
++			.min_uV = AXP_ELDO2_MIN,
++			.max_uV = AXP_ELDO2_MAX,
++			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
++#if defined (CONFIG_KP_OUTPUTINIT)
++			.initial_state = PM_SUSPEND_STANDBY,
++			.state_standby = {
++				.uV = AXP_ELDO2_VALUE * 1000,
++				.enabled = 1,
++			}
++#endif
++			.always_on = 1,
++			.boot_on = 1,
++			.apply_uV = 1,
++		},
++		.num_consumer_supplies = ARRAY_SIZE(eldo2_data),
++		.consumer_supplies = eldo2_data,
++	},
++
++	[dcdc1] = {
++		.constraints = {
++			.name = "DCDC1",
++			.min_uV = AXP_DCDC1_MIN,
++			.max_uV = AXP_DCDC1_MAX,
++			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
++#if defined (CONFIG_KP_OUTPUTINIT)
++			.initial_state = PM_SUSPEND_STANDBY,
++			.state_standby = {
++				.uV = AXP_DCDC1_VALUE * 1000,
++				.enabled = 1,
++			}
++#endif
++			.always_on = 1,
++			.boot_on = 1,
++			.apply_uV = 1,
++		},
++		.num_consumer_supplies = ARRAY_SIZE(dcdc1_data),
++		.consumer_supplies = dcdc1_data,
++	},
++	[dcdc2] = {
++		.constraints = {
++			.name = "DCDC2",
++			.min_uV = AXP_DCDC2_MIN,
++			.max_uV = AXP_DCDC2_MAX,
++			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
++#if defined (CONFIG_KP_OUTPUTINIT)
++			.initial_state = PM_SUSPEND_STANDBY,
++			.state_standby = {
++				.uV = AXP_DCDC2_VALUE * 1000,
++				.enabled = 1,
++			}
++#endif
++			.always_on = 1,
++			.boot_on = 1,
++			.apply_uV = 1,
++		},
++		.num_consumer_supplies = ARRAY_SIZE(dcdc2_data),
++		.consumer_supplies = dcdc2_data,
++	},
++	[dcdc3] = {
++		.constraints = {
++			.name = "DCDC3",
++			.min_uV = AXP_DCDC3_MIN,
++			.max_uV = AXP_DCDC3_MAX,
++			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
++#if defined (CONFIG_KP_OUTPUTINIT)
++			.initial_state = PM_SUSPEND_STANDBY,
++			.state_standby = {
++				.uV = AXP_DCDC3_VALUE * 1000,
++				.enabled = 1,
++			}
++#endif
++			.always_on = 1,
++			.boot_on = 1,
++			.apply_uV = 1,
++		},
++		.num_consumer_supplies = ARRAY_SIZE(dcdc3_data),
++		.consumer_supplies = dcdc3_data,
++	},
++	[dcdc4] = {
++		.constraints = {
++			.name = "DCDC4",
++			.min_uV = AXP_DCDC4_MIN,
++			.max_uV = AXP_DCDC4_MAX,
++			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
++#if defined (CONFIG_KP_OUTPUTINIT)
++			.initial_state = PM_SUSPEND_STANDBY,
++			.state_standby = {
++				.uV = AXP_DCDC4_VALUE * 1000,
++				.enabled = 1,
++			}
++#endif
++			.always_on = 0,
++			.boot_on = 0,
++			.apply_uV = 0,
++		},
++		.num_consumer_supplies = ARRAY_SIZE(dcdc4_data),
++		.consumer_supplies = dcdc4_data,
++	},
++	[dcdc5] = {
++		.constraints = {
++			.name = "DCDC5",
++			.min_uV = AXP_DCDC5_MIN,
++			.max_uV = AXP_DCDC5_MAX,
++			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
++#if defined (CONFIG_KP_OUTPUTINIT)
++			.initial_state = PM_SUSPEND_STANDBY,
++			.state_standby = {
++				.uV = AXP_DCDC5_VALUE * 1000,
++				.enabled = 1,
++			}
++#endif
++			.always_on = 1,
++			.boot_on = 1,
++			.apply_uV = 1,
++		},
++		.num_consumer_supplies = ARRAY_SIZE(dcdc5_data),
++		.consumer_supplies = dcdc5_data,
++	},
++
++	[gpioldo1] = {
++		.constraints = {
++			.name = "GPIO_LDO1",
++			.min_uV = GPIO_LDO1_MIN,
++			.max_uV = GPIO_LDO1_MAX,
++			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
++			.always_on = 1,
++			.boot_on = 1,
++			.apply_uV = 1,
++		},
++		.num_consumer_supplies = ARRAY_SIZE(gpioldo1_data),
++		.consumer_supplies = gpioldo1_data,
++	},
++
++	
++};
++
++static struct axp_funcdev_info axp_regldevs[] = {
++	{
++		.name = "axp216-regulator",
++		.id = AXP_ID_RTC,
++		.platform_data = &axp_regl_init_data[rtcldo],
++	}, {
++		.name = "axp216-regulator",
++		.id = AXP_ID_ALDO1,
++		.platform_data = &axp_regl_init_data[aldo1],
++	}, {
++		.name = "axp216-regulator",
++		.id = AXP_ID_ALDO2,
++		.platform_data = &axp_regl_init_data[aldo2],
++	}, {
++		.name = "axp216-regulator",
++		.id = AXP_ID_ALDO3,
++		.platform_data = &axp_regl_init_data[aldo3],
++	},{
++		.name = "axp216-regulator",
++		.id = AXP_ID_ELDO1,
++		.platform_data = &axp_regl_init_data[eldo1],
++	}, {
++		.name = "axp216-regulator",
++		.id = AXP_ID_ELDO2,
++		.platform_data = &axp_regl_init_data[eldo2],
++	},
++	{
++		.name = "axp216-regulator",
++		.id = AXP_ID_DCDC1,
++		.platform_data = &axp_regl_init_data[dcdc1],
++	}, {
++		.name = "axp216-regulator",
++		.id = AXP_ID_DCDC2,
++		.platform_data = &axp_regl_init_data[dcdc2],
++	}, {
++		.name = "axp216-regulator",
++		.id = AXP_ID_DCDC3,
++		.platform_data = &axp_regl_init_data[dcdc3],
++	}, {
++		.name = "axp216-regulator",
++		.id = AXP_ID_DCDC4,
++		.platform_data = &axp_regl_init_data[dcdc4],
++	}, {
++		.name = "axp216-regulator",
++		.id = AXP_ID_DCDC5,
++		.platform_data = &axp_regl_init_data[dcdc5],
++	},{
++		.name = "axp216-regulator",
++		.id = AXP_ID_LDOIO1,
++		.platform_data = &axp_regl_init_data[gpioldo1],
++	},
++};
++
++static struct power_supply_info battery_data ={
++		.name ="PTI PL336078",
++		.technology = POWER_SUPPLY_TECHNOLOGY_LION,
++		.voltage_max_design = CHGVOL,
++		.voltage_min_design = SHUTDOWNVOL,
++		.energy_full_design = BATCAP,
++		.use_for_apm = 1,
++};
++
++
++static struct axp_supply_init_data axp_sply_init_data = {
++	.battery_info = &battery_data,
++	.chgcur = STACHGCUR,
++	.chgvol = CHGVOL,
++	.chgend = ENDCHGRATE,
++	.chgen = CHGEN,
++	.sample_time = ADCFREQ,
++	.chgpretime = CHGPRETIME,
++	.chgcsttime = CHGCSTTIME,
++};
++
++static struct axp_funcdev_info axp_splydev[]={
++   	{
++   		.name = "axp216-supplyer",
++		.id = AXP_ID_SUPPLY,
++		.platform_data = &axp_sply_init_data,
++    },
++};
++
++
++static struct axp_platform_data axp_pdata = {
++	.num_regl_devs = ARRAY_SIZE(axp_regldevs),
++	.num_sply_devs = ARRAY_SIZE(axp_splydev),
++	//.num_gpio_devs = ARRAY_SIZE(axp_gpiodev),
++	.regl_devs = axp_regldevs,
++	.sply_devs = axp_splydev,
++	//.gpio_devs = axp_gpiodev,
++	.gpio_base = 0,
++};
++
++static struct i2c_board_info __initdata axp_mfd_i2c_board_info[] = {
++	{
++		.type = "axp_mfd",
++		.addr = AXP_DEVICES_ADDR,
++		.platform_data = &axp_pdata,
++		.irq = AXP_IRQNO,
++	},
++};
++
++static int __init axp_board_init(void)
++{
++        return i2c_register_board_info(AXP_I2CBUS, axp_mfd_i2c_board_info, ARRAY_SIZE(axp_mfd_i2c_board_info));
++}
++arch_initcall(axp_board_init);
++
++MODULE_DESCRIPTION("X-powers axp board");
++MODULE_AUTHOR("David Chan");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/power/supply/axp_power/axp-cfg.h b/module_drivers/drivers/power/supply/axp_power/axp-cfg.h
+new file mode 100755
+index 000000000..be7277f64
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/axp-cfg.h
+@@ -0,0 +1,344 @@
++#ifndef __LINUX_AXP_CFG_H_
++#define __LINUX_AXP_CFG_H_
++#include "axp-mfd.h"
++
++/*É豸µØÖ·*/
++/*
++	Ò»°ã²»¸Ä±ä£º
++	AXP216:0x34
++*/
++#define	AXP_DEVICES_ADDR	(0x68 >> 1)
++/*i2c¿ØÖÆÆ÷µÄÉ豸ºÅ:¾ßÌå¿´ËùʹÓÃƽ̨Ӳ¼þµÄÁ¬½Ó*/
++//#define	AXP_I2CBUS			3 //for aa.
++#define	AXP_I2CBUS			4      // for ab.
++/*µçԴоƬ¶ÔÓ¦µÄÖжϺţº¾ßÌå¿´ËùʹÓõÄƽ̨Ӳ¼þµÄÁ¬½Ó£¬
++ÖжÏÏßnmiÁ¬½ÓcpuµÄÄÄ·irq»òÕßgpio*/
++//#define AXP_IRQNO			IRQ_EINT(20)
++#define AXP_IRQNO			(32*3+18) //PD(18) //6//192//192//64
++
++/*³õʼ»¯¸÷·Êä³ö£¬µ¥Î»mV£¬0¶¼Îª¹Ø±Õ*/
++/*
++	ldo1£º
++		ÓÉÓ²¼þ¾ö¶¨Êä³öµçѹ£¬Èí¼þ¸Ä²»ÁË£¬Ö»ÊÇÈí¼þµÄÏÔʾµçѹ£º
++*/
++#define AXP_LDO1_VALUE			1800 // 3000
++/*
++	aldo1£º
++		AXP:700~3300,100/step
++*/
++#define AXP_ALDO1_VALUE		1800
++/*
++	aldo2£º
++		AXP:700~3300,100/step
++*/
++#define AXP_ALDO2_VALUE		1000
++/*
++	aldo3£º
++		AXP:700~3300,100/step
++*/
++#define AXP_ALDO3_VALUE		3300
++
++/*
++	eldo1£º
++		AXP:700~3300,100/step
++*/
++#define AXP_ELDO1_VALUE		3300
++/*
++	eldo2£º
++		AXP:700~3300,100/step
++*/
++#define AXP_ELDO2_VALUE		3300
++
++
++/*
++	DCDC1:
++		AXP:1600~3400,100/setp
++*/
++#define AXP_DCDC1_VALUE		3300
++/*
++	DCDC2£º
++		AXP:600~1540£¬20/step
++*/
++#define AXP_DCDC2_VALUE		1200 //1100
++/*
++	DCDC3£º
++		AXP:600~1860£¬20/step
++*/
++#define AXP_DCDC3_VALUE		900 //1100
++/*
++	DCDC4£º
++		AXP:600~1540£¬20/step
++*/
++#define AXP_DCDC4_VALUE		1000
++/*
++	DCDC5£º
++		AXP:1000~2550£¬50/step
++*/
++#define AXP_DCDC5_VALUE		1800 //1200
++
++/*µç³ØÈÝÁ¿£¬mAh£º¸ù¾Ýʵ¼Êµç³ØÈÝÁ¿À´¶¨Ò壬¶Ô¿âÂؼƷ½·¨À´Ëµ
++Õâ¸ö²ÎÊýºÜÖØÒª£¬±ØÐëÅäÖÃ*/
++#define BATCAP				1000/*752*/ /*680*/
++
++/*³õʼ»¯µç³ØÄÚ×裬m¦¸£ºÒ»°ãÔÚ100~200Ö®¼ä£¬²»¹ý×îºÃ¸ù¾Ýʵ¼Ê
++²âÊÔ³öÀ´µÄÈ·¶¨£¬·½·¨ÊÇ´ò¿ª´òÓ¡ÐÅÏ¢£¬²»½Óµç³ØÉպù̼þºó£¬
++Éϵç³Ø£¬²»½Ó³äµçÆ÷£¬¿ª»ú£¬¿ª»ú1·ÖÖӺ󣬽ÓÉϳäµçÆ÷£¬³ä
++1~2·ÖÖÓ£¬¿´´òÓ¡ÐÅÏ¢ÖеÄrdcÖµ£¬ÌîÈëÕâÀï*/
++#define BATRDC				203 //clivia 100
++/*¿ªÂ·µçѹ·½·¨Öеĵç³ØµçѹµÄ»º´æ*/
++#define AXP_VOL_MAX			1
++/*
++	³äµç¹¦ÄÜʹÄÜ£º
++        AXP:0-¹Ø±Õ£¬1-´ò¿ª
++*/
++#define CHGEN       1
++
++/*
++	³äµçµçÁ÷ÉèÖã¬uA£¬0Ϊ¹Ø±Õ£º
++		AXP:300~2550,100/step
++*/
++/*¿ª»ú³äµçµçÁ÷£¬uA*/
++#define STACHGCUR			750*1000
++/*¹ØÆÁ³äµçµçÁ÷£¬uA*/
++#define EARCHGCUR			750*1000
++/*ÐÝÃß³äµçµçÁ÷£¬uA*/
++#define SUSCHGCUR			750*1000
++/*¹Ø»ú³äµçµçÁ÷£¬uA*/
++#define CLSCHGCUR			750*1000
++
++/*Ä¿±ê³äµçµçѹ£¬mV*/
++/*
++	AXP:4100000/4200000/4240000/4350000
++*/
++#define CHGVOL				4350000
++/*³äµçµçÁ÷СÓÚÉèÖõçÁ÷µÄENDCHGRATE%ʱ£¬Í£Ö¹³äµç£¬%*/
++/*
++	AXP:10\15
++*/
++#define ENDCHGRATE			10
++/*¹Ø»úµçѹ£¬mV*/
++/*
++	ϵͳÉè¼ÆµÄ¹Ø»ú¹ýºóµÄµç³Ø¶Ëµçѹ£¬ÐèÒªÓë¹Ø»ú°Ù·Ö±È¡¢
++	¿ªÂ·µçѹ¶ÔÓ¦°Ù·Ö±È±í¼°µÍµç¾¯¸æµçѹÏ໥ÅäºÏ²Å»áÓÐ×÷ÓÃ
++*/
++#define SHUTDOWNVOL			3300
++
++/*adc²ÉÑùÂÊÉèÖã¬Hz*/
++/*
++	AXP:100\200\400\800
++*/
++#define ADCFREQ				100
++/*Ô¤³äµç³¬Ê±Ê±¼ä£¬min*/
++/*
++	AXP:40\50\60\70
++*/
++#define CHGPRETIME			50
++/*ºãÁ÷³äµç³¬Ê±Ê±¼ä£¬min*/
++/*
++	AXP:360\480\600\720
++*/
++#define CHGCSTTIME			480
++
++
++/*pek¿ª»úʱ¼ä£¬ms*/
++/*
++	°´power¼üÓ²¼þ¿ª»úʱ¼ä£º
++		AXP:128/1000/2000/3000
++*/
++#define PEKOPEN				1000
++/*pek³¤°´Ê±¼ä£¬ms*/
++/*
++	°´power¼ü·¢³¤°´ÖжϵÄʱ¼ä£¬¶ÌÓÚ´Ëʱ¼äÊǶ̰´£¬·¢¶Ì°´¼üirq£¬
++	³¤ÓÚ´Ëʱ¼äÊdz¤°´£¬·¢³¤°´¼üirq£º
++		AXP:1000/1500/2000/2500
++*/
++#define PEKLONG				1500
++/*pek³¤°´¹Ø»úʹÄÜ*/
++/*
++	°´power¼ü³¬¹ý¹Ø»úʱ³¤Ó²¼þ¹Ø»ú¹¦ÄÜʹÄÜ£º
++		AXP:0-²»¹Ø£¬1-¹Ø»ú
++*/
++#define PEKOFFEN			1
++/*pek³¤°´¹Ø»úʹÄܺ󿪻úÑ¡Ôñ*/
++/*
++	°´power¼ü³¬¹ý¹Ø»úʱ³¤Ó²¼þ¹Ø»ú»¹ÊÇÖØÆôÑ¡Ôñ:
++		AXP:0-Ö»¹Ø»ú²»ÖØÆô£¬1-¹Ø»úºóÖØÆô
++*/
++#define PEKOFFRESTART			0
++/*pekpwrÑÓ³Ùʱ¼ä£¬ms*/
++/*
++	¿ª»úºópowerokÐźŵÄÑÓ³Ùʱ¼ä£º
++		AXP20:8/16/32/64
++*/
++#define PEKDELAY			32
++/*pek³¤°´¹Ø»úʱ¼ä£¬ms*/
++/*
++	°´power¼üµÄ¹Ø»úʱ³¤£º
++		AXP:4000/6000/8000/10000
++*/
++#define PEKOFF				6000
++/*¹ýιػúʹÄÜ*/
++/*
++	AXPÄÚ²¿Î¶ȹý¸ßÓ²¼þ¹Ø»ú¹¦ÄÜʹÄÜ£º
++		AXP:0-²»¹Ø£¬1-¹Ø»ú
++*/
++#define OTPOFFEN			0
++/* ³äµçµçѹÏÞÖÆʹÄÜ*/
++/*
++	AXP:0-¹Ø±Õ£¬1-´ò¿ª
++*/
++#define USBVOLLIMEN		1
++/*  ³äµçÏÞѹ£¬mV£¬0Ϊ²»ÏÞÖÆ*/
++/*
++	AXP:4000~4700£¬100/step
++*/
++#define USBVOLLIM			4500
++/*  USB³äµçÏÞѹ£¬mV£¬0Ϊ²»ÏÞÖÆ*/
++/*
++	AXP:4000~4700£¬100/step
++*/
++#define USBVOLLIMPC			4700
++
++/* ³äµçµçÁ÷ÏÞÖÆʹÄÜ*/
++/*
++	AXP:0-¹Ø±Õ£¬1-´ò¿ª
++*/
++#define USBCURLIMEN		1
++/* ³äµçÏÞÁ÷£¬mA£¬0Ϊ²»ÏÞÖÆ*/
++/*
++	AXP:500/900
++*/
++#define USBCURLIM			0
++/* usb ³äµçÏÞÁ÷£¬mA£¬0Ϊ²»ÏÞÖÆ*/
++/*
++	AXP:500/900
++*/
++#define USBCURLIMPC			500
++/* PMU Öжϴ¥·¢»½ÐÑʹÄÜ*/
++/*
++	AXP:0-²»»½ÐÑ£¬1-»½ÐÑ
++*/
++#define IRQWAKEUP			0
++/* N_VBUSEN PIN ¹¦ÄÜ¿ØÖÆ*/
++/*
++	AXP:0-Êä³ö£¬Çý¶¯OTGÉýѹģ¿é£¬1-ÊäÈ룬¿ØÖÆVBUSͨ·
++*/
++#define VBUSEN			1
++/* ACIN/VBUS In-short ¹¦ÄÜÉèÖÃ*/
++/*
++	AXP:0-AC VBUS·Ö¿ª£¬1-ʹÓÃVBUSµ±AC,ÎÞµ¥¶ÀAC
++*/
++#define VBUSACINSHORT			0
++/* CHGLED ¹Ü½Å¿ØÖÆÉèÖÃ*/
++/*
++	AXP:0-Çý¶¯Âí´ï£¬1-Óɳäµç¹¦ÄÜ¿ØÖÆ
++*/
++#define CHGLEDFUN			0
++/* CHGLED LED ÀàÐÍÉèÖÃ*/
++/*
++	AXP:0-³äµçʱled³¤ÁÁ£¬1-³äµçʱledÉÁ˸
++*/
++#define CHGLEDTYPE			0
++/* µç³Ø×ÜÈÝÁ¿Ð£ÕýʹÄÜ*/
++/*
++	AXP:0-¹Ø±Õ£¬1-´ò¿ª
++*/
++#define BATCAPCORRENT			1
++/* ³äµçÍê³Éºó£¬³äµçÊä³öʹÄÜ*/
++/*
++	AXP:0-¹Ø±Õ£¬1-´ò¿ª
++*/
++#define BATREGUEN			0
++/* µç³Ø¼ì²â¹¦ÄÜʹÄÜ*/
++/*
++	AXP:0-¹Ø±Õ£¬1-´ò¿ª
++*/
++#define BATDET		1
++/* PMUÖØÖÃʹÄÜ*/
++/*
++	AXP:0-¹Ø±Õ£¬1-´ò¿ª°´µçÔ´¼ü16ÃëÖØÖÃPMU¹¦ÄÜ
++*/
++#define PMURESET		0
++/*µÍµç¾¯¸æµçѹ1£¬%*/
++/*
++	¸ù¾ÝϵͳÉè¼ÆÀ´¶¨£º
++	AXP:5%~20%
++*/
++#define BATLOWLV1    15
++/*µÍµç¾¯¸æµçѹ2£¬%*/
++/*
++	¸ù¾ÝϵͳÉè¼ÆÀ´¶¨£º
++	AXP:0%~15%
++*/
++#define BATLOWLV2    0
++
++#define ABS(x)				((x) >0 ? (x) : -(x) )
++
++#ifdef	CONFIG_KP_AXP
++/*AXP GPIO start NUM,¸ù¾Ýƽ̨ʵ¼ÊÇé¿ö¶¨Òå*/
++#define AXP_NR_BASE 100
++
++/*AXP GPIO NUM,°üÀ¨Âí´ïÇý¶¯¡¢LCD powerÒÔ¼°VBUS driver pin*/
++#define AXP_NR 5
++
++/*³õʼ»¯¿ªÂ·µçѹ¶ÔÓ¦°Ù·Ö±È±í*/
++/*
++	¿ÉÒÔʹÓÃĬÈÏÖµ£¬µ«ÊÇ×îºÃ¸ù¾Ýʵ¼Ê²âÊԵĵç³ØÀ´È·¶¨Ã¿¼¶
++	¶ÔÓ¦µÄÊ£Óà°Ù·Ö±È£¬ÌرðÐèҪעÒ⣬¹Ø»úµçѹSHUTDOWNVOLºÍµç³Ø
++	ÈÝÁ¿¿ªÊ¼Ð£×¼Ê£ÓàÈÝÁ¿°Ù·Ö±ÈBATCAPCORRATEÕâÁ½¼¶µÄ׼ȷÐÔ
++	AXPÊÊÓÃ
++*/
++#define OCVREG0				0		 //3.13V
++#define OCVREG1				0		 //3.27V
++#define OCVREG2				0		 //3.34V
++#define OCVREG3				0		 //3.41V
++#define OCVREG4				5		 //3.48V
++#define OCVREG5				12		 //3.52V
++#define OCVREG6				23		 //3.55V
++#define OCVREG7				32		 //3.57V
++#define OCVREG8				39		 //3.59V
++#define OCVREG9				44		 //3.61V
++#define OCVREGA				52		 //3.63V
++#define OCVREGB				54		 //3.64V
++#define OCVREGC				58		 //3.66V
++#define OCVREGD				63		 //3.7V
++#define OCVREGE				67		 //3.73V
++#define OCVREGF				70		 //3.77V
++#define OCVREG10		 	72                //3.78V
++#define OCVREG11		 	74                //3.8V
++#define OCVREG12		 	76                //3.82V
++#define OCVREG13		 	79                //3.84V
++#define OCVREG14		 	82                //3.85V
++#define OCVREG15		 	84                //3.87V
++#define OCVREG16		 	87                //3.91V
++#define OCVREG17		 	90                //3.94V
++#define OCVREG18		 	92                //3.98V
++#define OCVREG19		 	93                //4.01V
++#define OCVREG1A		 	95                //4.05V
++#define OCVREG1B		 	96                //4.08V
++#define OCVREG1C		 	98                //4.1V
++#define OCVREG1D		 	100                //4.12V
++#define OCVREG1E		 	100                //4.14V
++#define OCVREG1F		 	100                //4.15V
++
++#endif
++
++#ifdef AXP_INPUT_PWR_KEY
++static const uint64_t AXP_NOTIFIER_ON = (AXP_IRQ_USBIN |AXP_IRQ_USBRE |
++				       		                            AXP_IRQ_ACIN |AXP_IRQ_ACRE |
++				       		                            AXP_IRQ_BATIN |AXP_IRQ_BATRE |
++				       		                            AXP_IRQ_CHAST |AXP_IRQ_CHAOV |
++						                            (uint64_t)AXP_IRQ_PEKFE |(uint64_t)AXP_IRQ_PEKRE);
++#else
++/*Ñ¡ÔñÐèÒª´ò¿ªµÄÖжÏʹÄÜ*/
++static const uint64_t AXP_NOTIFIER_ON = (AXP_IRQ_USBIN |AXP_IRQ_USBRE |
++				       		                            AXP_IRQ_ACIN |AXP_IRQ_ACRE |
++				       		                            AXP_IRQ_BATIN |AXP_IRQ_BATRE |
++				       		                            AXP_IRQ_CHAST |AXP_IRQ_CHAOV /*|
++						                            (uint64_t)AXP_IRQ_PEKFE |(uint64_t)AXP_IRQ_PEKRE*/);
++#endif
++/* ÐèÒª×ö²åÈë»ðÅ£¡¢usb¹Ø»úÖØÆô½øbootʱpower_startÉèÖÃΪ1£¬·ñÔòΪ0*/
++#define POWER_START 1
++#define RESET_WHEN_ACIN 1	//clivia add Ôڹػúʱac in »òÕßusb in£¬reset
++
++#endif
+diff --git a/module_drivers/drivers/power/supply/axp_power/axp-filenode.c b/module_drivers/drivers/power/supply/axp_power/axp-filenode.c
+new file mode 100644
+index 000000000..e1a2ab8ca
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/axp-filenode.c
+@@ -0,0 +1,511 @@
++/*
++ * Battery charger driver for X-POWERS AXP28X
++ *
++ * Copyright (C) 2014 X-POWERS Ltd.
++ *  Ming Li <liming@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++
++int axp_debug = 0x3;
++int vbus_curr_limit_debug = 1;
++static int long_key_power_off = 1;
++
++static ssize_t axpdebug_store(struct class *class,
++			struct class_attribute *attr,	const char *buf, size_t count)
++{
++	if(buf[0] == '1')
++		axp_debug = 1;
++	else
++		axp_debug = 0;
++	return count;
++}
++
++static ssize_t axpdebug_show(struct class *class,
++			struct class_attribute *attr,	char *buf)
++{
++	return sprintf(buf, "bat-debug value is %d\n", axp_debug);
++}
++
++static ssize_t vbuslimit_store(struct class *class,
++			struct class_attribute *attr,	const char *buf, size_t count)
++{
++	if(buf[0] == '1')
++		vbus_curr_limit_debug = 1;
++	else
++		vbus_curr_limit_debug = 0;
++	return count;
++}
++
++static ssize_t vbuslimit_show(struct class *class,
++			struct class_attribute *attr,	char *buf)
++{
++	return sprintf(buf, "vbus curr limit value is %d\n", vbus_curr_limit_debug);
++}
++/*for long key power off control added by zhwj at 20130502*/
++static ssize_t longkeypoweroff_store(struct class *class,
++			struct class_attribute *attr,	const char *buf, size_t count)
++{
++	int addr;
++	uint8_t data;
++	if(buf[0] == '1'){
++		long_key_power_off = 1;
++	}
++	else{
++		long_key_power_off = 0;
++	}
++	/*for long key power off control added by zhwj at 20130502*/
++	addr = AXP_POK_SET;
++	axp_read(axp_charger->master, addr , &data);
++	data &= 0xf7;
++	data |= (long_key_power_off << 3);
++	axp_write(axp_charger->master, addr , data);
++	return count;
++}
++
++static ssize_t longkeypoweroff_show(struct class *class,
++			struct class_attribute *attr,	char *buf)
++{
++	return sprintf(buf, "long key power off value is %d\n", long_key_power_off);
++}
++
++static ssize_t out_factory_mode_show(struct class *class,
++    struct class_attribute *attr, char *buf)
++{
++	uint8_t addr = AXP_BUFFERC;
++	uint8_t data;
++	axp_read(axp_charger->master, addr , &data);
++	return sprintf(buf, "0x%x\n",data);
++}
++
++static ssize_t out_factory_mode_store(struct class *class,
++        struct class_attribute *attr, const char *buf, size_t count)
++{
++	uint8_t addr = AXP_BUFFERC;
++	uint8_t data;
++	int var;
++	var = simple_strtoul(buf, NULL, 10);
++	if(var){
++	  data = 0x0d;
++	  axp_write(axp_charger->master, addr , data);
++	}
++	else{
++	  data = 0x00;
++	  axp_write(axp_charger->master, addr , data);
++	}
++	return count;
++}
++
++static struct class_attribute axppower_class_attrs[] = {
++	__ATTR(vbuslimit,S_IRUGO|S_IWUSR,vbuslimit_show,vbuslimit_store),
++	__ATTR(axpdebug,S_IRUGO|S_IWUSR,axpdebug_show,axpdebug_store),
++	__ATTR(longkeypoweroff,S_IRUGO|S_IWUSR,longkeypoweroff_show,longkeypoweroff_store),
++	__ATTR(out_factory_mode,S_IRUGO|S_IWUSR,out_factory_mode_show,out_factory_mode_store),
++	__ATTR_NULL
++};
++struct class axppower_class = {
++	.name = "axppower",
++	.class_attrs = axppower_class_attrs,
++};
++
++static ssize_t chgen_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++	 struct axp_charger *charger = dev_get_drvdata(dev);
++	 uint8_t val;
++
++	 axp_read(charger->master, AXP_CHARGE_CONTROL1, &val);
++	 spin_lock(&charger->charger_lock);
++	 charger->chgen  = val >> 7;
++	 spin_unlock(&charger->charger_lock);
++	 return sprintf(buf, "%d\n",charger->chgen);
++}
++
++static ssize_t chgen_store(struct device *dev,
++	 struct device_attribute *attr, const char *buf, size_t count)
++{
++	 struct axp_charger *charger = dev_get_drvdata(dev);
++	 int var;
++
++	 var = simple_strtoul(buf, NULL, 10);
++	 if(var){
++		spin_lock(&charger->charger_lock);
++		charger->chgen = 1;
++		spin_unlock(&charger->charger_lock);
++		axp_set_bits(charger->master,AXP_CHARGE_CONTROL1,0x80);
++	 }else{
++	 	spin_lock(&charger->charger_lock);
++		charger->chgen = 0;
++		spin_unlock(&charger->charger_lock);
++		axp_clr_bits(charger->master,AXP_CHARGE_CONTROL1,0x80);
++	 }
++	 return count;
++}
++
++static ssize_t chgmicrovol_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++	 struct axp_charger *charger = dev_get_drvdata(dev);
++	 uint8_t val;
++
++	 axp_read(charger->master, AXP_CHARGE_CONTROL1, &val);
++	 spin_lock(&charger->charger_lock);
++	 switch ((val >> 5) & 0x03){
++		 case 0: charger->chgvol = 4100000;break;
++		 case 1: charger->chgvol = 4200000;break;
++		 case 2: charger->chgvol = 4240000;break;
++		 case 3: charger->chgvol = 4350000;break;
++	 }
++	 spin_unlock(&charger->charger_lock);
++	 return sprintf(buf, "%d\n",charger->chgvol);
++}
++
++static ssize_t chgmicrovol_store(struct device *dev,
++	 struct device_attribute *attr, const char *buf, size_t count)
++{
++	 struct axp_charger *charger = dev_get_drvdata(dev);
++	 int var;
++	 uint8_t tmp, val;
++
++	 var = simple_strtoul(buf, NULL, 10);
++	 switch(var){
++		 case 4100000:tmp = 0;break;
++		 case 4200000:tmp = 1;break;
++		 case 4240000:tmp = 2;break;
++		 case 4350000:tmp = 3;break;
++		 default:  tmp = 4;break;
++	 }
++	 if(tmp < 4){
++		spin_lock(&charger->charger_lock);
++		charger->chgvol = var;
++		spin_unlock(&charger->charger_lock);
++		axp_read(charger->master, AXP_CHARGE_CONTROL1, &val);
++		val &= 0x9F;
++		val |= tmp << 5;
++		axp_write(charger->master, AXP_CHARGE_CONTROL1, val);
++	 }
++	 return count;
++}
++
++static ssize_t chgintmicrocur_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++	 struct axp_charger *charger = dev_get_drvdata(dev);
++	 uint8_t val;
++
++	 axp_read(charger->master, AXP_CHARGE_CONTROL1, &val);
++	 spin_lock(&charger->charger_lock);
++	 charger->chgcur = (val & 0x0F) * 150000 +300000;
++	 spin_unlock(&charger->charger_lock);
++	 return sprintf(buf, "%d\n",charger->chgcur);
++}
++
++static ssize_t chgintmicrocur_store(struct device *dev,
++	 struct device_attribute *attr, const char *buf, size_t count)
++{
++	 struct axp_charger *charger = dev_get_drvdata(dev);
++	 int var;
++	 uint8_t val,tmp;
++
++	 var = simple_strtoul(buf, NULL, 10);
++	 if(var >= 300000 && var <= 2550000){
++		 tmp = (var -200001)/150000;
++		 spin_lock(&charger->charger_lock);
++		 charger->chgcur = tmp *150000 + 300000;
++		 spin_unlock(&charger->charger_lock);
++		 axp_read(charger->master, AXP_CHARGE_CONTROL1, &val);
++		 val &= 0xF0;
++		 val |= tmp;
++		 axp_write(charger->master, AXP_CHARGE_CONTROL1, val);
++	 }
++	 return count;
++}
++
++static ssize_t chgendcur_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++	 struct axp_charger *charger = dev_get_drvdata(dev);
++	 uint8_t val;
++
++	 axp_read(charger->master, AXP_CHARGE_CONTROL1, &val);
++	 spin_lock(&charger->charger_lock);
++	 charger->chgend = ((val >> 4)& 0x01)? 15 : 10;
++	 spin_unlock(&charger->charger_lock);
++	 return sprintf(buf, "%d\n",charger->chgend);
++}
++
++static ssize_t chgendcur_store(struct device *dev,
++	struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct axp_charger *charger = dev_get_drvdata(dev);
++	int var;
++
++	var = simple_strtoul(buf, NULL, 10);
++	if(var == 10 ){
++		 axp_clr_bits(charger->master ,AXP_CHARGE_CONTROL1,0x10);
++	}else if (var == 15){
++		 axp_set_bits(charger->master ,AXP_CHARGE_CONTROL1,0x10);
++	}
++	spin_lock(&charger->charger_lock);
++	charger->chgend = var;
++	spin_unlock(&charger->charger_lock);
++	return count;
++}
++
++static ssize_t chgpretimemin_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++	struct axp_charger *charger = dev_get_drvdata(dev);
++	uint8_t val;
++
++	axp_read(charger->master,AXP_CHARGE_CONTROL2, &val);
++	spin_lock(&charger->charger_lock);
++	charger->chgpretime = (val >> 6) * 10 +40;
++	spin_unlock(&charger->charger_lock);
++	return sprintf(buf, "%d\n",charger->chgpretime);
++}
++
++static ssize_t chgpretimemin_store(struct device *dev,
++	struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct axp_charger *charger = dev_get_drvdata(dev);
++	int var;
++	uint8_t tmp,val;
++
++	var = simple_strtoul(buf, NULL, 10);
++	if(var >= 40 && var <= 70){
++		tmp = (var - 40)/10;
++		spin_lock(&charger->charger_lock);
++		charger->chgpretime = tmp * 10 + 40;
++		spin_unlock(&charger->charger_lock);
++		axp_read(charger->master,AXP_CHARGE_CONTROL2,&val);
++		val &= 0x3F;
++		val |= (tmp << 6);
++		axp_write(charger->master,AXP_CHARGE_CONTROL2,val);
++	}
++	return count;
++}
++
++static ssize_t chgcsttimemin_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++	struct axp_charger *charger = dev_get_drvdata(dev);
++	uint8_t val;
++
++	axp_read(charger->master,AXP_CHARGE_CONTROL2, &val);
++	spin_lock(&charger->charger_lock);
++	charger->chgcsttime = (val & 0x03) *120 + 360;
++	spin_unlock(&charger->charger_lock);
++	return sprintf(buf, "%d\n",charger->chgcsttime);
++}
++
++static ssize_t chgcsttimemin_store(struct device *dev,
++	struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct axp_charger *charger = dev_get_drvdata(dev);
++	int var;
++	uint8_t tmp,val;
++
++	var = simple_strtoul(buf, NULL, 10);
++	if(var >= 360 && var <= 720){
++		tmp = (var - 360)/120;
++		spin_lock(&charger->charger_lock);
++		charger->chgcsttime = tmp * 120 + 360;
++		spin_unlock(&charger->charger_lock);
++		axp_read(charger->master,AXP_CHARGE_CONTROL2,&val);
++		val &= 0xFC;
++		val |= tmp;
++		axp_write(charger->master,AXP_CHARGE_CONTROL2,val);
++	}
++	return count;
++}
++
++static ssize_t adcfreq_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++	struct axp_charger *charger = dev_get_drvdata(dev);
++	uint8_t val;
++
++	axp_read(charger->master, AXP_ADC_CONTROL3, &val);
++	spin_lock(&charger->charger_lock);
++	switch ((val >> 6) & 0x03){
++		case 0: charger->sample_time = 100;break;
++		case 1: charger->sample_time = 200;break;
++		case 2: charger->sample_time = 400;break;
++		case 3: charger->sample_time = 800;break;
++		default:break;
++	}
++	spin_unlock(&charger->charger_lock);
++	return sprintf(buf, "%d\n",charger->sample_time);
++}
++
++static ssize_t adcfreq_store(struct device *dev,
++	 struct device_attribute *attr, const char *buf, size_t count)
++{
++	 struct axp_charger *charger = dev_get_drvdata(dev);
++	 int var;
++	 uint8_t val;
++
++	 var = simple_strtoul(buf, NULL, 10);
++	 axp_read(charger->master, AXP_ADC_CONTROL3, &val);
++	 spin_lock(&charger->charger_lock);
++	 switch (var/25){
++		 case 1: val &= ~(3 << 6);charger->sample_time = 100;break;
++		 case 2: val &= ~(3 << 6);val |= 1 << 6;charger->sample_time = 200;break;
++		 case 4: val &= ~(3 << 6);val |= 2 << 6;charger->sample_time = 400;break;
++		 case 8: val |= 3 << 6;charger->sample_time = 800;break;
++		 default: break;
++	 }
++	 spin_unlock(&charger->charger_lock);
++	 axp_write(charger->master, AXP_ADC_CONTROL3, val);
++	 return count;
++}
++
++
++static ssize_t vholden_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++	 struct axp_charger *charger = dev_get_drvdata(dev);
++	 uint8_t val;
++
++	 axp_read(charger->master,AXP_CHARGE_VBUS, &val);
++	 val = (val>>6) & 0x01;
++	 return sprintf(buf, "%d\n",val);
++}
++
++static ssize_t vholden_store(struct device *dev,
++	 struct device_attribute *attr, const char *buf, size_t count)
++{
++	 struct axp_charger *charger = dev_get_drvdata(dev);
++	 int var;
++
++	 var = simple_strtoul(buf, NULL, 10);
++	 if(var)
++	 axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x40);
++	 else
++	 axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x40);
++	 return count;
++}
++
++static ssize_t vhold_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++	 struct axp_charger *charger = dev_get_drvdata(dev);
++	 uint8_t val;
++	 int vhold;
++
++	 axp_read(charger->master,AXP_CHARGE_VBUS, &val);
++	 vhold = ((val >> 3) & 0x07) * 100000 + 4000000;
++	 return sprintf(buf, "%d\n",vhold);
++}
++
++static ssize_t vhold_store(struct device *dev,
++	 struct device_attribute *attr, const char *buf, size_t count)
++{
++	 struct axp_charger *charger = dev_get_drvdata(dev);
++	 int var;
++	 uint8_t val,tmp;
++
++	 var = simple_strtoul(buf, NULL, 10);
++	 if(var >= 4000000 && var <=4700000){
++		 tmp = (var - 4000000)/100000;
++		 axp_read(charger->master, AXP_CHARGE_VBUS,&val);
++		 val &= 0xC7;
++		 val |= tmp << 3;
++		 axp_write(charger->master, AXP_CHARGE_VBUS,val);
++	 }
++	 return count;
++}
++
++static ssize_t iholden_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++	 struct axp_charger *charger = dev_get_drvdata(dev);
++	 uint8_t val;
++
++	 axp_read(charger->master,AXP_CHARGE_VBUS, &val);
++	 return sprintf(buf, "%d\n",((val & 0x03) == 0x03)?0:1);
++}
++
++static ssize_t iholden_store(struct device *dev,
++	 struct device_attribute *attr, const char *buf, size_t count)
++{
++	 struct axp_charger *charger = dev_get_drvdata(dev);
++	 int var;
++
++	 var = simple_strtoul(buf, NULL, 10);
++	 if(var)
++		 axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x01);
++	 else
++		 axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x03);
++	 return count;
++}
++
++static ssize_t ihold_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++	 struct axp_charger *charger = dev_get_drvdata(dev);
++	 uint8_t val,tmp;
++	 int ihold;
++
++	 axp_read(charger->master,AXP_CHARGE_VBUS, &val);
++	 tmp = (val) & 0x03;
++	 switch(tmp){
++		 case 0: ihold = 900000;break;
++		 case 1: ihold = 500000;break;
++		 default: ihold = 0;break;
++	 }
++	 return sprintf(buf, "%d\n",ihold);
++}
++
++static ssize_t ihold_store(struct device *dev,
++	 struct device_attribute *attr, const char *buf, size_t count)
++{
++	 struct axp_charger *charger = dev_get_drvdata(dev);
++	 int var;
++
++	 var = simple_strtoul(buf, NULL, 10);
++	 if(var == 900000)
++		 axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x03);
++	 else if (var == 500000){
++		 axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x02);
++		 axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x01);
++	 }
++	 return count;
++}
++
++static struct device_attribute axp_charger_attrs[] = {
++	 AXP_CHG_ATTR(chgen),
++	 AXP_CHG_ATTR(chgmicrovol),
++	 AXP_CHG_ATTR(chgintmicrocur),
++	 AXP_CHG_ATTR(chgendcur),
++	 AXP_CHG_ATTR(chgpretimemin),
++	 AXP_CHG_ATTR(chgcsttimemin),
++	 AXP_CHG_ATTR(adcfreq),
++	 AXP_CHG_ATTR(vholden),
++	 AXP_CHG_ATTR(vhold),
++	 AXP_CHG_ATTR(iholden),
++	 AXP_CHG_ATTR(ihold),
++};
++
++int axp_charger_create_attrs(struct power_supply *psy)
++{
++	int j,ret;
++
++	for (j = 0; j < ARRAY_SIZE(axp_charger_attrs); j++) {
++		ret = device_create_file(psy->dev,&axp_charger_attrs[j]);
++		if (ret)
++			goto sysfs_failed;
++	}
++	goto succeed;
++
++sysfs_failed:
++	while (j--)
++		device_remove_file(psy->dev, &axp_charger_attrs[j]);
++succeed:
++  return ret;
++}
++
+diff --git a/module_drivers/drivers/power/supply/axp_power/axp-gpio.c b/module_drivers/drivers/power/supply/axp_power/axp-gpio.c
+new file mode 100644
+index 000000000..0ee064c71
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/axp-gpio.c
+@@ -0,0 +1,542 @@
++/*
++ * axp809x-gpio.c  --  gpiolib support for Krosspower &axp PMICs
++ *
++ * Copyright 2012 X-POWERS Microelectronics PLC.
++ *
++ * Author: Weijin Zhong <>
++ *
++ *  This program is free software; you can redistribute  it and/or modify it
++ *  under  the terms of  the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the  License, or (at your
++ *  option) any later version.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <linux/mfd/core.h>
++#include <linux/platform_device.h>
++#include <linux/seq_file.h>
++#include <linux/i2c.h>
++#include <mach/gpio.h>
++#include "axp-gpio.h"
++#include "axp-cfg.h"
++#include "axp-mfd.h"
++
++#define GPIO_AXP809(n)		(AXP_NR_BASE + (n))
++
++struct virtual_gpio_data {
++	struct mutex lock;
++	int gpio;				//gpio number : 0/1/2/...
++	int io;         //0: input      1: output
++	int value;		  //0: low        1: high
++};
++
++int axp_gpio_set_io(int gpio, int io_mode)
++{
++	if(io_mode == 1){//output
++		switch(gpio)
++		{
++			case 0: return axp_clr_bits(&axp->dev,AXP_GPIO0_CFG, 0x06);
++			case 1: return axp_clr_bits(&axp->dev,AXP_GPIO1_CFG, 0x06);
++			case 2: return 0;
++			case 3: return axp_clr_bits(&axp->dev,AXP_GPIO3_CFG, 0x08);
++			case 4: return axp_clr_bits(&axp->dev,AXP_GPIO4_CFG, 0x10);
++			default:return -ENXIO;
++		}
++	}
++	else if(io_mode == 0){//input
++		switch(gpio)
++		{
++			case 0: axp_clr_bits(&axp->dev,AXP_GPIO0_CFG,0x05);
++					return axp_set_bits(&axp->dev,AXP_GPIO0_CFG,0x02);
++			case 1: axp_clr_bits(&axp->dev,AXP_GPIO1_CFG,0x05);
++					return axp_set_bits(&axp->dev,AXP_GPIO1_CFG,0x02);
++			case 2:
++					printk("This IO can not config as an input!");
++					return -EINVAL;
++			case 3:
++					printk("This IO can not config as an input!");
++					return -EINVAL;
++			case 4:
++					printk("This IO can not config as an input!");
++					return -EINVAL;
++			default:return -ENXIO;
++		}
++	}
++	return -EINVAL;
++}
++EXPORT_SYMBOL_GPL(axp_gpio_set_io);
++
++
++int axp_gpio_get_io(int gpio, int *io_mode)
++{
++	uint8_t val;
++	switch(gpio)
++	{
++		case 0: axp_read(&axp->dev,AXP_GPIO0_CFG,&val);val &= 0x07;
++				if(val < 0x02)
++					*io_mode = 1;
++				else if (val == 0x02)
++					*io_mode = 0;
++				else
++					return -EIO;
++				break;
++		case 1: axp_read(&axp->dev,AXP_GPIO1_CFG,&val);val &= 0x07;
++				if(val < 0x02)
++					*io_mode = 1;
++				else if (val == 0x02)
++					*io_mode = 0;
++				else
++					return -EIO;
++				break;
++		case 2: *io_mode = 1;
++				break;
++		case 3: axp_read(&axp->dev,AXP_GPIO3_CFG,&val);val &= 0x08;
++				if(!val)
++					*io_mode = 1;
++				else
++					return -EIO;
++				break;
++		case 4: axp_read(&axp->dev,AXP_GPIO4_CFG,&val);val &= 0x10;
++				if(!val)
++					*io_mode = 1;
++				else
++					return -EIO;
++				break;
++
++		default:return -ENXIO;
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(axp_gpio_get_io);
++
++
++int axp_gpio_set_value(int gpio, int value)
++{
++	int io_mode,ret;
++	ret = axp_gpio_get_io(gpio,&io_mode);
++	if(ret)
++		return ret;
++	if(1 == io_mode){//output
++		if(value){//high
++			switch(gpio) {
++				case 0: {
++					axp_clr_bits(&axp->dev,AXP_GPIO0_CFG,0x06);
++					return axp_set_bits(&axp->dev,AXP_GPIO0_CFG,0x01);
++				}
++				case 1: {
++						axp_clr_bits(&axp->dev,AXP_GPIO1_CFG,0x06);
++						ret = axp_set_bits(&axp->dev,AXP_GPIO1_CFG,0x01);
++						return ret;
++				}
++				case 2: {
++					return axp_set_bits(&axp->dev,AXP_GPIO2_CFG,0x80);
++				}
++				case 3: {
++					axp_clr_bits(&axp->dev,AXP_GPIO3_CFG, 0x08);
++					ret = axp_clr_bits(&axp->dev,AXP_GPIO3_CFG,0x30);
++					return ret;
++				}
++				case 4: {
++					axp_clr_bits(&axp->dev,AXP_GPIO4_CFG, 0x10);
++					return axp_set_bits(&axp->dev,AXP_GPIO4_STA,0x04);
++				}
++				default:break;
++			}
++		}
++		else{//low
++			switch(gpio)
++			{
++				case 0: axp_clr_bits(&axp->dev,AXP_GPIO0_CFG,0x06);
++						return axp_clr_bits(&axp->dev,AXP_GPIO0_CFG,0x03);
++				case 1: axp_clr_bits(&axp->dev,AXP_GPIO1_CFG,0x06);
++						return axp_clr_bits(&axp->dev,AXP_GPIO1_CFG,0x03);
++				case 2: return axp_clr_bits(&axp->dev,AXP_GPIO2_CFG,0x80);
++				case 3: axp_clr_bits(&axp->dev,AXP_GPIO3_CFG, 0x08);
++						return axp_set_bits(&axp->dev,AXP_GPIO3_CFG,0x30);
++				case 4: axp_clr_bits(&axp->dev,AXP_GPIO4_CFG, 0x10);
++						return axp_clr_bits(&axp->dev,AXP_GPIO4_STA,0x04);
++				default:break;
++			}
++		}
++		return -ENXIO;
++	}
++	return -ENXIO;
++}
++EXPORT_SYMBOL_GPL(axp_gpio_set_value);
++
++
++int axp_gpio_get_value(int gpio, int *value)
++{
++	int io_mode;
++	int ret;
++	uint8_t val;
++	ret = axp_gpio_get_io(gpio,&io_mode);
++//	printk("%s: line %d,%d,0x%x\n", __func__, __LINE__,gpio,(int)value);
++	if(ret)
++		return ret;
++	if(1 == io_mode){//output
++		switch(gpio)
++		{
++			case 0:
++				ret = axp_read(&axp->dev,AXP_GPIO0_CFG,&val);
++				if(ret)
++					{
++						printk("Read AXP_GPIO0 value fail! ");
++					*value = 0;
++						return -ENXIO;
++				  }
++				else
++				   *value = val & 0x01;
++				break;
++			case 1:
++				ret =axp_read(&axp->dev,AXP_GPIO1_CFG,&val);
++				if(ret)
++					{
++						printk("Read AXP_GPIO1 value fail! ");
++					*value = 0;
++						return -ENXIO;
++				  }
++				*value = val & 0x01;
++				break;
++			case 2:
++					ret =axp_read(&axp->dev,AXP_GPIO2_CFG,&val);
++					if(ret)
++						{
++							printk("Read AXP_GPIO2 value fail! ");
++						*value = 0;
++							return -ENXIO;
++					  }
++				  *value = ((val & 0x80) >> 7);
++					break;
++			case 3:
++					ret =axp_read(&axp->dev,AXP_GPIO3_CFG,&val);
++					if(ret)
++						{
++							printk("Read AXP_GPIO3 value fail! ");
++						*value = 0;
++							return -ENXIO;
++					  }
++					  if((val & 0x30) == 0x30)
++					  	{
++					  		*value = 0;
++					  	}
++					  	else
++					  		{
++					  			*value = 1;
++					  		}
++					break;
++			case 4:
++					ret =axp_read(&axp->dev,AXP_GPIO4_STA,&val);
++						if(ret)
++							{
++								printk("Read AXP_GPIO4 value fail! ");
++							*value = 0;
++								return -ENXIO;
++						  }
++						  *value = ((val & 0x04) >> 2);
++						break;
++			default:return -ENXIO;
++		}
++	}
++	else{//input
++		switch(gpio)
++		{
++			case 0:ret = axp_read(&axp->dev,AXP_GPIO01_STATE,&val);val &= 0x10;*value = val>>4;break;
++			case 1:ret = axp_read(&axp->dev,AXP_GPIO01_STATE,&val);val &= 0x20;*value = val>>5;break;
++			case 2:printk("This IO is not an input,no return value!");return -ENXIO;
++			case 3:printk("This IO is not an input,no return value!");return -ENXIO;
++			case 4:printk("This IO is not an input,no return value!");return -ENXIO;
++			default:return -ENXIO;
++		}
++	}
++	return ret;
++}
++EXPORT_SYMBOL_GPL(axp_gpio_get_value);
++
++static int __axp_gpio_input(struct gpio_chip *chip, unsigned offset)
++{
++	u32  index = chip->base + offset;
++//	printk("%s: line %d,%d,\n", __func__, __LINE__,offset);
++
++	if(GPIO_AXP809(0) == index)
++		return axp_gpio_set_io(0, 0);
++	else if(GPIO_AXP809(1) == index)
++		return axp_gpio_set_io(1, 0);
++	else if(GPIO_AXP809(2) == index || GPIO_AXP809(3) == index || GPIO_AXP809(4) == index)
++		{
++			printk("This IO can not config as an input IO!");
++			return -EINVAL;
++		}
++	else
++		return -EINVAL;
++}
++static int __axp_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
++{
++	u32  index = chip->base + (int)offset;
++	int  ret = 0;
++	int  id = index - GPIO_AXP809(0);
++
++//	printk("%s: line %d,%d,%d\n", __func__, __LINE__,offset,value);
++	switch(id) {
++		case 0:
++			ret = axp_gpio_set_io(0, 1); /* set to output */
++			if(ret)
++				return ret;
++			return axp_gpio_set_value(0, value); /* set value */
++		case 1:
++			ret = axp_gpio_set_io(1, 1); /* set to output */
++			if(ret)
++				return ret;
++			return axp_gpio_set_value(1, value); /* set value */
++		case 2:
++			ret = axp_gpio_set_io(2, 1); /* set to output */
++			if(ret)
++				return ret;
++			return axp_gpio_set_value(2, value); /* set value */
++		case 3:
++			ret = axp_gpio_set_io(3, 1); /* set to output */
++			if(ret)
++				return ret;
++			return axp_gpio_set_value(3, value); /* set value */
++		case 4:
++			ret = axp_gpio_set_io(4, 1); /* set to output */
++			if(ret)
++				return ret;
++			return axp_gpio_set_value(4, value); /* set value */
++		default: return -EINVAL;
++	}
++}
++static void __axp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
++{
++	u32  index = chip->base + offset;
++	int id = index - GPIO_AXP809(0);
++//	printk("%s: line %d,%d,%d\n", __func__, __LINE__,offset,value);
++
++	switch (id) {
++		case 0:axp_gpio_set_value(0, value);break;
++		case 1:axp_gpio_set_value(1, value);break;
++		case 2:axp_gpio_set_value(2, value);break;
++		case 3:axp_gpio_set_value(3, value);break;
++		case 4:axp_gpio_set_value(4, value);break;
++		default:WARN_ON(1);
++	}
++}
++static int __axp_gpio_get(struct gpio_chip *chip, unsigned offset)
++{
++	u32  index = chip->base + offset;
++	int  value = 0;
++//	printk("%s: line %d,%d,\n", __func__, __LINE__,offset);
++
++	if(GPIO_AXP809(0) == index) {
++		WARN_ON(0 != axp_gpio_get_value(0, &value));
++		return value;
++	} else if(GPIO_AXP809(1) == index) {
++		WARN_ON(0 != axp_gpio_get_value(1, &value));
++		return value;
++	} else if(GPIO_AXP809(2) == index) {
++		WARN_ON(0 != axp_gpio_get_value(2, &value));
++		return value;
++	} else if(GPIO_AXP809(3) == index) {
++		WARN_ON(0 != axp_gpio_get_value(3, &value));
++		return value;
++	} else if(GPIO_AXP809(4) == index) {
++		WARN_ON(0 != axp_gpio_get_value(4, &value));
++		return value;
++	}	else {
++		printk("%s err: line %d\n", __func__, __LINE__);;
++		return 0;
++	}
++}
++
++struct gpio_chip axp_gpio_chip = {
++	.base	= AXP_NR_BASE,
++	.ngpio	= AXP_NR,
++	.label	= "axp_pin",
++	.direction_input = __axp_gpio_input,
++	.direction_output = __axp_gpio_output,
++	.set	= __axp_gpio_set,
++	.get	= __axp_gpio_get,
++};
++
++static ssize_t show_gpio(struct device *dev,
++			   struct device_attribute *attr, char *buf)
++{
++	struct virtual_gpio_data *data = dev_get_drvdata(dev);
++	return sprintf(buf, "%d\n", data->gpio);
++}
++
++static ssize_t set_gpio(struct device *dev, struct device_attribute *attr,
++			  const char *buf, size_t count)
++{
++	struct virtual_gpio_data *data = dev_get_drvdata(dev);
++	long val;
++
++	if (strict_strtol(buf, 10, &val) != 0)
++		return count;
++
++	data->gpio = val;
++
++	return count;
++}
++
++static ssize_t show_io(struct device *dev,
++			   struct device_attribute *attr, char *buf)
++{
++	struct virtual_gpio_data *data = dev_get_drvdata(dev);
++	int ret;
++	mutex_lock(&data->lock);
++
++	ret = axp_gpio_get_io(data->gpio,&data->io);
++
++	mutex_unlock(&data->lock);
++
++	if(ret)
++		return ret;
++
++	return sprintf(buf, "%d\n", data->io);
++}
++
++static ssize_t set_io(struct device *dev, struct device_attribute *attr,
++			  const char *buf, size_t count)
++{
++	struct virtual_gpio_data *data = dev_get_drvdata(dev);
++	long val;
++	int ret;
++
++	if (strict_strtol(buf, 10, &val) != 0)
++		return count;
++
++	mutex_lock(&data->lock);
++
++	data->io = val;
++	ret = axp_gpio_set_io(data->gpio,data->io);
++
++	mutex_unlock(&data->lock);
++	if(ret)
++		return ret;
++	return count;
++}
++
++
++static ssize_t show_value(struct device *dev,
++			   struct device_attribute *attr, char *buf)
++{
++	struct virtual_gpio_data *data = dev_get_drvdata(dev);
++	int ret;
++
++	mutex_lock(&data->lock);
++
++	ret = axp_gpio_get_value(data->gpio,&data->value);
++
++	mutex_unlock(&data->lock);
++
++	if(ret)
++		return ret;
++
++	return sprintf(buf, "%d\n", data->value);
++}
++
++static ssize_t set_value(struct device *dev, struct device_attribute *attr,
++			  const char *buf, size_t count)
++{
++	struct virtual_gpio_data *data = dev_get_drvdata(dev);
++	long val;
++	int ret;
++
++	if (strict_strtol(buf, 10, &val) != 0)
++		return count;
++
++	mutex_lock(&data->lock);
++
++	data->value = val;
++	ret = axp_gpio_set_value(data->gpio,data->value);
++
++	mutex_unlock(&data->lock);
++
++	if(ret){
++		return ret;
++	}
++
++	return count;
++}
++
++
++static DEVICE_ATTR(gpio,0664, show_gpio, set_gpio);
++static DEVICE_ATTR(io, 0664, show_io, set_io);
++static DEVICE_ATTR(value, 0664, show_value, set_value);
++
++struct device_attribute *attributes[] = {
++	&dev_attr_gpio,
++	&dev_attr_io,
++	&dev_attr_value,
++};
++
++
++static int __devinit axp_gpio_probe(struct platform_device *pdev)
++{
++	//struct axp_mfd_chip *axp_chip = dev_get_drvdata(pdev->dev.parent);
++	struct virtual_gpio_data *drvdata;
++	int ret, i;
++
++	drvdata = kzalloc(sizeof(struct virtual_gpio_data), GFP_KERNEL);
++	if (drvdata == NULL) {
++		ret = -ENOMEM;
++		goto err;
++	}
++
++	mutex_init(&drvdata->lock);
++
++	for (i = 0; i < ARRAY_SIZE(attributes); i++) {
++		ret = device_create_file(&pdev->dev, attributes[i]);
++		if (ret != 0)
++			goto err;
++	}
++
++	platform_set_drvdata(pdev, drvdata);
++
++	return 0;
++
++err:
++	for (i = 0; i < ARRAY_SIZE(attributes); i++)
++		device_remove_file(&pdev->dev, attributes[i]);
++	kfree(drvdata);
++	return ret;
++
++return 0;
++}
++
++static int __devexit axp_gpio_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static struct platform_driver axp_gpio_driver = {
++	.driver.name	= "axp216-gpio",
++	.driver.owner	= THIS_MODULE,
++	.probe		= axp_gpio_probe,
++	.remove		= __devexit_p(axp_gpio_remove),
++};
++
++static int __init axp_gpio_init(void)
++{
++	/* register axp gpio chip */
++	if(0 != gpiochip_add(&axp_gpio_chip))
++		printk("%s err, line %d\n", __func__, __LINE__);
++	return platform_driver_register(&axp_gpio_driver);
++}
++subsys_initcall(axp_gpio_init);
++
++static void __exit axp_gpio_exit(void)
++{
++	platform_driver_unregister(&axp_gpio_driver);
++}
++module_exit(axp_gpio_exit);
++
++MODULE_AUTHOR("Weijin Zhong ");
++MODULE_DESCRIPTION("GPIO interface for AXP PMICs");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:axp-gpio");
+diff --git a/module_drivers/drivers/power/supply/axp_power/axp-gpio.h b/module_drivers/drivers/power/supply/axp_power/axp-gpio.h
+new file mode 100644
+index 000000000..b378b70dd
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/axp-gpio.h
+@@ -0,0 +1,30 @@
++/*
++ * gpio.h  --  GPIO Driver for X-Powers AXP
++ *
++ * Copyright (C) 2013 X-Powers, Ltd.
++ *
++ *  This program is free software; you can redistribute  it and/or modify it
++ *  under  the terms of  the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the  License, or (at your
++ *  option) any later version.
++ *
++ */
++
++#ifndef _LINUX_AXP_GPIO_H_
++#define _LINUX_AXP_GPIO_H_
++
++/*    AXP   */
++#define AXP_GPIO0_CFG                   (AXP_GPIO0_CTL)//0x90
++#define AXP_GPIO1_CFG                   (AXP_GPIO1_CTL)//0x92
++#define AXP_GPIO2_CFG                   (AXP_LDO_DC_EN2)//0x12
++#define AXP_GPIO3_CFG                   (AXP_OFF_CTL)//0x32
++#define AXP_GPIO4_CFG                   (AXP_HOTOVER_CTL)//0x8f
++#define AXP_GPIO4_STA                   (AXP_IPS_SET)//0x30
++
++#define AXP_GPIO01_STATE               (AXP_GPIO01_SIGNAL)
++
++extern int axp_gpio_set_io(int gpio, int io_state);
++extern int axp_gpio_get_io(int gpio, int *io_state);
++extern int axp_gpio_set_value(int gpio, int value);
++extern int axp_gpio_get_value(int gpio, int *value);
++#endif
+diff --git a/module_drivers/drivers/power/supply/axp_power/axp-mfd-216.h b/module_drivers/drivers/power/supply/axp_power/axp-mfd-216.h
+new file mode 100644
+index 000000000..2ef3d5821
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/axp-mfd-216.h
+@@ -0,0 +1,191 @@
++#ifndef __LINUX_AXP_MFD_216_H_
++#define __LINUX_AXP_MFD_216_H_
++/* Unified sub device IDs for AXP */
++/* LDO0 For RTCLDO ,LDO1-3 for ALDO,LDO*/
++enum {
++	AXP_ID_RTC,   //RTCLDO
++	AXP_ID_ALDO1,   //ALDO1
++	AXP_ID_ALDO2,   //ALDO2
++	AXP_ID_ALDO3,   //ALDO3
++
++	AXP_ID_ELDO1,   //ELDO1
++	AXP_ID_ELDO2,  //ELDO2
++
++	AXP_ID_DCDC1,
++	AXP_ID_DCDC2,
++	AXP_ID_DCDC3,
++	AXP_ID_DCDC4,
++	AXP_ID_DCDC5,
++
++	AXP_ID_LDOIO1,
++
++
++
++	AXP_ID_SUPPLY,
++	AXP_ID_GPIO,
++};
++
++/*For AXP216*/
++#define AXP216                   (216)
++#define AXP_STATUS              (0x00)
++#define AXP_MODE_CHGSTATUS      (0x01)
++#define AXP_IC_TYPE			    (0x03)
++#define AXP_BUFFER1             (0x04)
++#define AXP_BUFFER2             (0x05)
++#define AXP_BUFFER3             (0x06)
++#define AXP_BUFFER4             (0x07)
++#define AXP_BUFFER5             (0x08)
++#define AXP_BUFFER6             (0x09)
++#define AXP_BUFFER7             (0x0A)
++#define AXP_BUFFER8             (0x0B)
++#define AXP_BUFFER9             (0x0C)
++#define AXP_BUFFERA             (0x0D)
++#define AXP_BUFFERB             (0x0E)
++#define AXP_BUFFERC             (0x0F)
++#define AXP_IPS_SET             (0x30)
++#define AXP_VOFF_SET            (0x31)
++#define AXP_OFF_CTL             (0x32)
++#define AXP_CHARGE1             (0x33)
++#define AXP_CHARGE2             (0x34)
++#define AXP_CHARGE3             (0x35)
++#define AXP_POK_SET             (0x36)
++#define AXP_INTEN1              (0x40)
++#define AXP_INTEN2              (0x41)
++#define AXP_INTEN3              (0x42)
++#define AXP_INTEN4              (0x43)
++#define AXP_INTEN5              (0x44)
++#define AXP_INTSTS1             (0x48)
++#define AXP_INTSTS2             (0x49)
++#define AXP_INTSTS3             (0x4A)
++#define AXP_INTSTS4             (0x4B)
++#define AXP_INTSTS5             (0x4C)
++
++#define AXP_LDO_DC_EN1          (0X10)
++#define AXP_LDO_DC_EN2          (0X12)
++#define AXP_LDO_DC_EN3          (0X13)
++#define AXP_DLDO1OUT_VOL        (0x15)
++#define AXP_DLDO2OUT_VOL        (0x16)
++#define AXP_DLDO3OUT_VOL        (0x17)
++#define AXP_DLDO4OUT_VOL        (0x18)
++#define AXP_ELDO1OUT_VOL        (0x19)
++#define AXP_ELDO2OUT_VOL        (0x1A)
++#define AXP_ELDO3OUT_VOL        (0x1B)
++#define AXP_DC5LDOOUT_VOL       (0x1C)
++#define AXP_DC1OUT_VOL          (0x21)
++#define AXP_DC2OUT_VOL          (0x22)
++#define AXP_DC3OUT_VOL          (0x23)
++#define AXP_DC4OUT_VOL          (0x24)
++#define AXP_DC5OUT_VOL          (0x25)
++#define AXP_GPIO0LDOOUT_VOL     (0x91)
++#define AXP_GPIO1LDOOUT_VOL     (0x93)
++#define AXP_ALDO1OUT_VOL        (0x28)
++#define AXP_ALDO2OUT_VOL        (0x29)
++#define AXP_ALDO3OUT_VOL        (0x2A)
++#define AXP_OFFLEVEL_DELAY      (0x37)
++#define AXP_DCDC_FREQSET        (0x3B)
++
++#define AXP_DCDC_MODESET        (0x80)
++#define AXP_ADC_EN              (0x82)
++#define AXP_HOTOVER_CTL         (0x8F)
++
++#define AXP_GPIO0_CTL           (0x90)
++#define AXP_GPIO1_CTL           (0x92)
++#define AXP_GPIO01_SIGNAL       (0x94)
++#define AXP_BAT_CHGCOULOMB3     (0xB0)
++#define AXP_BAT_CHGCOULOMB2     (0xB1)
++#define AXP_BAT_CHGCOULOMB1     (0xB2)
++#define AXP_BAT_CHGCOULOMB0     (0xB3)
++#define AXP_BAT_DISCHGCOULOMB3  (0xB4)
++#define AXP_BAT_DISCHGCOULOMB2  (0xB5)
++#define AXP_BAT_DISCHGCOULOMB1  (0xB6)
++#define AXP_BAT_DISCHGCOULOMB0  (0xB7)
++#define AXP_COULOMB_CTL         (0xB8)
++
++
++
++/* bit definitions for AXP events ,irq event */
++/*  AXP216*/
++#define	AXP_IRQ_USBLO			( 1 <<  1)
++#define	AXP_IRQ_USBRE			( 1 <<  2)
++#define	AXP_IRQ_USBIN			( 1 <<  3)
++#define	AXP_IRQ_USBOV     	( 1 <<  4)
++#define	AXP_IRQ_ACRE     		( 1 <<  5)
++#define	AXP_IRQ_ACIN     		( 1 <<  6)
++#define	AXP_IRQ_ACOV     		( 1 <<  7)
++#define	AXP_IRQ_TEMLO      	( 1 <<  8)
++#define	AXP_IRQ_TEMOV      	( 1 <<  9)
++#define	AXP_IRQ_CHAOV			( 1 << 10)
++#define	AXP_IRQ_CHAST 	    ( 1 << 11)
++#define	AXP_IRQ_BATATOU    	( 1 << 12)
++#define	AXP_IRQ_BATATIN  		( 1 << 13)
++#define AXP_IRQ_BATRE			( 1 << 14)
++#define AXP_IRQ_BATIN		( 1 << 15)
++#define AXP_IRQ_QBATINWORK	( 1 << 16)
++#define AXP_IRQ_BATINWORK	( 1 << 17)
++#define AXP_IRQ_QBATOVWORK	( 1 << 18)
++#define AXP_IRQ_BATOVWORK	( 1 << 19)
++#define AXP_IRQ_QBATINCHG	( 1 << 20)
++#define AXP_IRQ_BATINCHG	( 1 << 21)
++#define AXP_IRQ_QBATOVCHG	( 1 << 22)
++#define AXP_IRQ_BATOVCHG	( 1 << 23)
++#define AXP_IRQ_EXTLOWARN2  	( 1 << 24)
++#define AXP_IRQ_EXTLOWARN1  	( 1 << 25)
++#define AXP_IRQ_ICTEMOV    	( 1 << 31)
++#define AXP_IRQ_GPIO0TG     	((uint64_t)1 << 32)
++#define AXP_IRQ_GPIO1TG     	((uint64_t)1 << 33)
++#define AXP_IRQ_POKLO     	((uint64_t)1 << 35)
++#define AXP_IRQ_POKSH     	((uint64_t)1 << 36)
++
++#define AXP_IRQ_PEKFE     	((uint64_t)1 << 37)
++#define AXP_IRQ_PEKRE     	((uint64_t)1 << 38)
++#define AXP_IRQ_TIMER     	((uint64_t)1 << 39)
++
++
++/* Status Query Interface */
++/*  AXP216 */
++#define AXP_STATUS_SOURCE    	( 1 <<  0)
++#define AXP_STATUS_ACUSBSH 	( 1 <<  1)
++#define AXP_STATUS_BATCURDIR 	( 1 <<  2)
++#define AXP_STATUS_USBLAVHO 	( 1 <<  3)
++#define AXP_STATUS_USBVA    	( 1 <<  4)
++#define AXP_STATUS_USBEN    	( 1 <<  5)
++#define AXP_STATUS_ACVA	    ( 1 <<  6)
++#define AXP_STATUS_ACEN	    ( 1 <<  7)
++
++#define AXP_STATUS_BATINACT  	( 1 << 11)
++
++#define AXP_STATUS_BATEN     	( 1 << 13)
++#define AXP_STATUS_INCHAR    	( 1 << 14)
++#define AXP_STATUS_ICTEMOV   	( 1 << 15)
++
++#define AXP_LDO1_MIN		3000000
++#define AXP_LDO1_MAX		3000000
++#define AXP_ALDO1_MIN		700000
++#define AXP_ALDO1_MAX		3300000
++#define AXP_ALDO2_MIN		700000
++#define AXP_ALDO2_MAX		3300000
++#define AXP_ALDO3_MIN		700000
++#define AXP_ALDO3_MAX		3300000
++
++#define AXP_ELDO1_MIN		700000
++#define AXP_ELDO1_MAX		3300000
++#define AXP_ELDO2_MIN         700000
++#define AXP_ELDO2_MAX         3300000
++
++
++#define AXP_DCDC1_MIN		1600000
++#define AXP_DCDC1_MAX		3400000
++#define AXP_DCDC2_MIN		600000
++#define AXP_DCDC2_MAX		1540000
++#define AXP_DCDC3_MIN		600000
++#define AXP_DCDC3_MAX		1860000
++#define AXP_DCDC4_MIN		600000
++#define AXP_DCDC4_MAX		1540000
++#define AXP_DCDC5_MIN		1000000
++#define AXP_DCDC5_MAX		2550000
++
++
++#define GPIO_LDO1_MIN		700000
++#define GPIO_LDO1_MAX		3300000
++
++#endif /* __LINUX_AXP_MFD_216_H_ */
+diff --git a/module_drivers/drivers/power/supply/axp_power/axp-mfd.c b/module_drivers/drivers/power/supply/axp_power/axp-mfd.c
+new file mode 100755
+index 000000000..871e60300
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/axp-mfd.c
+@@ -0,0 +1,302 @@
++/*
++ * Base driver for X-Powers AXP
++ *
++ * Copyright (C) 2013 X-Powers, Ltd.
++ *  Zhang Donglu <zhangdonglu@x-powers.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/i2c.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/version.h>
++//#include <mach/system.h>
++
++//#include "axp-cfg.h"
++#include "axp216-mfd.h"
++
++#include <linux/regulator/driver.h>
++#include <linux/regulator/machine.h>
++
++#include <linux/irq.h>
++#include <linux/gpio.h>
++#include <linux/of_gpio.h>
++#include <linux/mfd/core.h>
++#include <linux/platform_device.h>
++static const struct mfd_cell axp216_cells[] = {
++	{ .name = "axp216-regulator" },
++	{ .name = "axp216-supplyer" },
++};
++
++static void axp_mfd_irq_work(struct work_struct *work)
++{
++	struct axp_mfd_chip *chip = container_of(work, struct axp_mfd_chip, irq_work);
++	uint64_t irqs = 0;
++	while (1) {
++		if (chip->ops->read_irqs(chip, &irqs)){
++			printk("read irq fail\n");
++			break;
++		}
++		irqs &= chip->irqs_enabled;
++		if (irqs == 0){
++			break;
++		}
++
++		if(irqs > 0xffffffff){
++			blocking_notifier_call_chain(&chip->notifier_list, (uint32_t)(irqs>>32), (void *)1);
++		}
++		else{
++			blocking_notifier_call_chain(&chip->notifier_list, (uint32_t)irqs, (void *)0);
++		}
++	}
++	enable_irq(chip->client->irq);
++}
++
++static irqreturn_t axp_mfd_irq_handler(int irq, void *data)
++{
++	struct axp_mfd_chip *chip = data;
++	disable_irq_nosync(irq);
++	(void)schedule_work(&chip->irq_work);
++
++	return IRQ_HANDLED;
++}
++
++static struct axp_mfd_chip_ops axp_mfd_ops[] = {
++	[0] = {
++		.init_chip    = axp_init_chip,
++		.enable_irqs  = axp_enable_irqs,
++		.disable_irqs = axp_disable_irqs,
++		.read_irqs    = axp_read_irqs,
++	},
++};
++
++int axp_mfd_create_attrs(struct axp_mfd_chip *chip)
++{
++	int j,ret;
++	if (chip->type ==  AXP216){
++		for (j = 0; j < ARRAY_SIZE(axp_mfd_attrs); j++) {
++			ret = device_create_file(chip->dev,&axp_mfd_attrs[j]);
++			if (ret)
++			goto sysfs_failed;
++		}
++	}
++	else
++		ret = 0;
++	goto succeed;
++
++sysfs_failed:
++	while (j--)
++		device_remove_file(chip->dev,&axp_mfd_attrs[j]);
++succeed:
++	return ret;
++}
++
++static int __remove_subdev(struct device *dev, void *unused)
++{
++	platform_device_unregister(to_platform_device(dev));
++	return 0;
++}
++
++static int axp_mfd_remove_subdevs(struct axp_mfd_chip *chip)
++{
++	return device_for_each_child(chip->dev, NULL, __remove_subdev);
++}
++
++void axp_power_off(void)
++{
++	uint8_t val;
++
++    axp_clr_bits(&axp->dev, AXP_GPIO1_CTL, 0x07);//out low
++#if defined (CONFIG_KP_AXP)
++	if(SHUTDOWNVOL >= 2600 && SHUTDOWNVOL <= 3300){
++		if (SHUTDOWNVOL > 3200){
++			val = 0x7;
++		}
++		else if (SHUTDOWNVOL > 3100){
++			val = 0x6;
++		}
++		else if (SHUTDOWNVOL > 3000){
++			val = 0x5;
++		}
++		else if (SHUTDOWNVOL > 2900){
++			val = 0x4;
++		}
++		else if (SHUTDOWNVOL > 2800){
++			val = 0x3;
++		}
++		else if (SHUTDOWNVOL > 2700){
++			val = 0x2;
++		}
++		else if (SHUTDOWNVOL > 2600){
++			val = 0x1;
++		}
++		else
++			val = 0x0;
++
++		axp_update(&axp->dev, AXP_VOFF_SET, val, 0x7);
++	}
++	val = 0xff;
++    mdelay(20);
++    if(POWER_START != 1){
++		axp_read(&axp->dev, AXP_STATUS, &val);
++		if(val & 0xF0){
++	    	axp_read(&axp->dev, AXP_MODE_CHGSTATUS, &val);
++	    	if(val & 0x20){
++	        	axp_write(&axp->dev, AXP_BUFFERC, 0x0f);
++            	mdelay(20);
++		//# if LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)
++		  //  	arch_reset(0,NULL);
++		//#endif
++		dev_err(&axp->dev,"[axp] warning!!! arch can't ,reboot, maybe some error happend!\n");
++	    	}
++		}
++	}
++    axp_write(&axp->dev, AXP_BUFFERC, 0x00);
++    mdelay(20);
++#if RESET_WHEN_ACIN
++	axp_read(&axp->dev, AXP_STATUS, &val);
++	if(val & 0xF0){
++		printk("[axp] reset!\n");
++		axp_set_bits(&axp->dev, AXP_VOFF_SET, 0x40);
++	}else
++#endif
++    axp_set_bits(&axp->dev, AXP_OFF_CTL, 0x80);
++    mdelay(20);
++    dev_dbg(&axp->dev, "[axp] warning!!! axp can't power-off, maybe some error happend!\n");
++
++#endif
++}
++EXPORT_SYMBOL_GPL(axp_power_off);
++static int  axp_mfd_probe(struct i2c_client *client,
++				  const struct i2c_device_id *id)
++{
++	struct axp_mfd_chip *chip;
++	struct device_node *np = client->dev.of_node;
++	//enum of_gpio_flags flags;
++	enum of_gpio_flags flags;
++	int ret;
++	unsigned int axp216_irq;
++
++	chip = kzalloc(sizeof(struct axp_mfd_chip), GFP_KERNEL);
++	if (chip == NULL)
++		return -ENOMEM;
++
++	axp = client;
++
++	chip->client = client;
++	chip->dev = &client->dev;
++	chip->ops = &axp_mfd_ops[id->driver_data];
++
++	mutex_init(&chip->lock);
++	INIT_WORK(&chip->irq_work, axp_mfd_irq_work);
++	BLOCKING_INIT_NOTIFIER_HEAD(&chip->notifier_list);
++
++	axp216_irq = of_get_named_gpio_flags(np, "ingenic,axp216-gpio", 0, &flags);
++	if(!gpio_is_valid(axp216_irq)) {
++		dev_err(&client->dev,"couldn't find pmu irq gpio, axp216_irq = %d\n", axp216_irq);
++		goto out_free_chip;
++	}
++
++	i2c_set_clientdata(client, chip);
++
++	ret = chip->ops->init_chip(chip);
++	if (ret)
++		goto out_free_chip;
++
++	client->irq=gpio_to_irq(axp216_irq); //chan
++	if (client->irq < 0) {
++		dev_err(&client->dev,"couldn't find pmu irq\n");
++		goto out_free_chip;
++	}
++	dev_dbg(&client->dev, "[axp-mfd] client->irq=%d!\n",client->irq);
++
++	ret = request_irq(/*gpio_to_irq(4)*/client->irq, axp_mfd_irq_handler,
++		flags, "axp_mfd", chip);
++  	if (ret) {
++  		dev_err(&client->dev, "failed to request irq %d\n",
++  				client->irq);
++  		goto out_free_chip;
++  	}
++       //enable_irq(gpio_to_irq(225));
++	ret = mfd_add_devices(&client->dev, -1, axp216_cells,
++			ARRAY_SIZE(axp216_cells), NULL, 0, NULL);
++	if (ret) {
++		dev_err(&client->dev, "failed to add sub-devices: %d\n", ret);
++		goto out_free_irq;
++	}
++
++	/* PM hookup */
++	//if(!pm_power_off)
++	pm_power_off = axp_power_off;
++
++	ret = axp_mfd_create_attrs(chip);
++	if(ret){
++		return ret;
++	}
++	return 0;
++
++out_free_irq:
++	free_irq(client->irq, chip);
++
++out_free_chip:
++	i2c_set_clientdata(client, NULL);
++	kfree(chip);
++
++	return ret;
++}
++
++static int  axp_mfd_remove(struct i2c_client *client)
++{
++	struct axp_mfd_chip *chip = i2c_get_clientdata(client);
++
++	pm_power_off = NULL;
++	axp = NULL;
++
++	axp_mfd_remove_subdevs(chip);
++	kfree(chip);
++	return 0;
++}
++static const struct of_device_id axp216_match[] = {
++	{.compatible = "x-power,axp216",},
++	{},
++};
++
++MODULE_DEVICE_TABLE(of, axp216_match);
++static const struct i2c_device_id axp_mfd_id_table[] = {
++	{"axp216", 0},
++	{},
++};
++static struct i2c_driver axp_mfd_driver = {
++	.probe		= axp_mfd_probe,
++	.remove		= axp_mfd_remove,
++	.driver	= {
++		.name	= "axp216",
++		.owner	= THIS_MODULE,
++		.of_match_table = of_match_ptr(axp216_match),
++	},
++	.id_table	= axp_mfd_id_table,
++};
++
++static int __init axp_mfd_init(void)
++{
++	return i2c_add_driver(&axp_mfd_driver);
++}
++subsys_initcall(axp_mfd_init);
++
++static void __exit axp_mfd_exit(void)
++{
++	i2c_del_driver(&axp_mfd_driver);
++}
++module_exit(axp_mfd_exit);
++
++MODULE_DESCRIPTION("MFD Driver for X-Powers AXP PMIC");
++MODULE_AUTHOR("Weijin Zhong X-POWERS");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/power/supply/axp_power/axp-mfd.h b/module_drivers/drivers/power/supply/axp_power/axp-mfd.h
+new file mode 100644
+index 000000000..900192712
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/axp-mfd.h
+@@ -0,0 +1,95 @@
++#ifndef __LINUX_AXP_MFD_H_
++#define __LINUX_AXP_MFD_H_
++
++#include "axp-mfd-216.h"
++
++#define AXP_MFD_ATTR(_name)					\
++{									\
++	.attr = { .name = #_name,.mode = 0644 },					\
++	.show =  _name##_show,				\
++	.store = _name##_store, \
++}
++
++/* AXP battery charger data */
++struct power_supply_info;
++
++struct axp_supply_init_data {
++	/* battery parameters */
++	struct power_supply_info *battery_info;
++
++	/* current and voltage to use for battery charging */
++	unsigned int chgcur;
++	unsigned int chgvol;
++	unsigned int chgend;
++	/*charger control*/
++	bool chgen;
++	bool limit_on;
++	/*charger time */
++	int chgpretime;
++	int chgcsttime;
++
++	/*adc sample time */
++	unsigned int sample_time;
++
++	/* platform callbacks for battery low and critical IRQs */
++	void (*battery_low)(void);
++	void (*battery_critical)(void);
++};
++
++struct axp_funcdev_info {
++	int		id;
++	const char	*name;
++	void	*platform_data;
++};
++
++struct axp_platform_data {
++	int num_regl_devs;
++	int num_sply_devs;
++	int num_gpio_devs;
++	int gpio_base;
++	struct axp_funcdev_info *regl_devs;
++	struct axp_funcdev_info *sply_devs;
++	struct axp_funcdev_info *gpio_devs;
++
++};
++
++struct axp_mfd_chip {
++	struct i2c_client	*client;
++	struct device		*dev;
++	struct axp_mfd_chip_ops	*ops;
++
++	int			type;
++	uint64_t		irqs_enabled;
++
++	struct mutex		lock;
++	struct work_struct	irq_work;
++
++	struct blocking_notifier_head notifier_list;
++};
++
++struct axp_mfd_chip_ops {
++	int	(*init_chip)(struct axp_mfd_chip *);
++	int	(*enable_irqs)(struct axp_mfd_chip *, uint64_t irqs);
++	int	(*disable_irqs)(struct axp_mfd_chip *, uint64_t irqs);
++	int	(*read_irqs)(struct axp_mfd_chip *, uint64_t *irqs);
++};
++
++extern struct device *axp_get_dev(void);
++extern int axp_register_notifier(struct device *dev,
++		struct notifier_block *nb, uint64_t irqs);
++extern int axp_unregister_notifier(struct device *dev,
++		struct notifier_block *nb, uint64_t irqs);
++
++
++/* NOTE: the functions below are not intended for use outside
++ * of the AXP sub-device drivers
++ */
++extern int axp_write(struct device *dev, int reg, uint8_t val);
++extern int axp_writes(struct device *dev, int reg, int len, uint8_t *val);
++extern int axp_read(struct device *dev, int reg, uint8_t *val);
++extern int axp_reads(struct device *dev, int reg, int len, uint8_t *val);
++extern int axp_update(struct device *dev, int reg, uint8_t val, uint8_t mask);
++extern int axp_set_bits(struct device *dev, int reg, uint8_t bit_mask);
++extern int axp_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
++extern struct i2c_client *axp;
++#endif /* __LINUX_PMIC_AXP_H */
+diff --git a/module_drivers/drivers/power/supply/axp_power/axp-regu.c b/module_drivers/drivers/power/supply/axp_power/axp-regu.c
+new file mode 100644
+index 000000000..24ade7fe1
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/axp-regu.c
+@@ -0,0 +1,495 @@
++/*
++ * Regulators driver for X-Powers AXP
++ *
++ * Copyright (C) 2013 X-Powers, Ltd.
++ *  Zhang Donglu <zhangdonglu@x-powers.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/driver.h>
++#include <linux/regulator/machine.h>
++#include <linux/module.h>
++#include <linux/version.h>
++
++
++#include "axp-cfg.h"
++#include "axp-regu.h"
++
++
++static inline struct device *to_axp_dev(struct regulator_dev *rdev)
++{
++	return rdev_get_dev(rdev)->parent;
++}
++
++static inline int check_range(struct axp_regulator_info *info,
++				int min_uV, int max_uV)
++{
++	if (min_uV < info->min_uV || min_uV > info->max_uV)
++		return -EINVAL;
++
++	return 0;
++}
++
++
++/* AXP common operations */
++static int axp_set_voltage(struct regulator_dev *rdev,
++				  int min_uV, int max_uV,unsigned *selector)
++{
++	struct axp_regulator_info *info = rdev_get_drvdata(rdev);
++	struct device *axp_dev = to_axp_dev(rdev);
++	uint8_t val, mask;
++
++	if (check_range(info, min_uV, max_uV)) {
++		pr_err("invalid voltage range (%d, %d) uV\n", min_uV, max_uV);
++		return -EINVAL;
++	}
++	if ((info->switch_uV != 0) && (info->step2_uV!= 0) &&
++	(info->new_level_uV != 0) && (min_uV > info->switch_uV)) {
++		val = (info->switch_uV- info->min_uV + info->step1_uV - 1) / info->step1_uV;
++		if (min_uV <= info->new_level_uV){
++			val += 1;
++		} else {
++			val += (min_uV - info->new_level_uV) / info->step2_uV;
++			val += 1;
++		}
++		mask = ((1 << info->vol_nbits) - 1)  << info->vol_shift;
++	} else if ((info->switch_uV != 0) && (info->step2_uV!= 0) &&
++	(min_uV > info->switch_uV) && (info->new_level_uV == 0)) {
++		val = (info->switch_uV- info->min_uV + info->step1_uV - 1) / info->step1_uV;
++		val += (min_uV - info->switch_uV) / info->step2_uV;
++		mask = ((1 << info->vol_nbits) - 1)  << info->vol_shift;
++	} else {
++		val = (min_uV - info->min_uV + info->step1_uV - 1) / info->step1_uV;
++		val <<= info->vol_shift;
++		mask = ((1 << info->vol_nbits) - 1)  << info->vol_shift;
++	}
++	//if(info->vol_reg==0x25 || info->vol_reg==0x10){
++		dev_dbg(axp_dev, "[AXP216-reg] axp_regulator_set_voltage reg=0x%x,val=0x%x!\n",info->vol_reg,val);
++	//}
++	return axp_update(axp_dev, info->vol_reg, val, mask);
++}
++
++static int axp_get_voltage(struct regulator_dev *rdev)
++{
++	struct axp_regulator_info *info = rdev_get_drvdata(rdev);
++	struct device *axp_dev = to_axp_dev(rdev);
++	uint8_t val, mask;
++	int ret, switch_val, vol;
++
++	ret = axp_read(axp_dev, rdev->desc->vsel_reg, &val);
++	if (ret)
++		return ret;
++
++	mask = ((1 << info->vol_nbits) - 1)  << info->vol_shift;
++	switch_val = ((info->switch_uV- info->min_uV + info->step1_uV - 1) / info->step1_uV);
++	val = (val & mask) >> info->vol_shift;
++
++	if ((info->switch_uV != 0) && (info->step2_uV!= 0) &&
++	(val > switch_val) && (info->new_level_uV != 0)) {
++		val -= switch_val;
++		vol = info->new_level_uV + info->step2_uV * val;
++	} else if ((info->switch_uV != 0) && (info->step2_uV!= 0) &&
++	(val > switch_val) && (info->new_level_uV == 0)) {
++		val -= switch_val;
++		vol = info->switch_uV + info->step2_uV * val;
++	} else {
++		vol = info->min_uV + info->step1_uV * val;
++	}
++
++	return vol;
++
++}
++
++static int axp_enable(struct regulator_dev *rdev)
++{
++	struct axp_regulator_info *info = rdev_get_drvdata(rdev);
++	struct device *axp_dev = to_axp_dev(rdev);
++	return axp_set_bits(axp_dev, info->enable_reg,
++					1 << info->enable_bit);
++}
++
++static int axp_disable(struct regulator_dev *rdev)
++{
++	struct axp_regulator_info *info = rdev_get_drvdata(rdev);
++	struct device *axp_dev = to_axp_dev(rdev);
++	return axp_clr_bits(axp_dev, info->enable_reg,
++					1 << info->enable_bit);
++}
++
++static int axp_is_enabled(struct regulator_dev *rdev)
++{
++	struct axp_regulator_info *info = rdev_get_drvdata(rdev);
++	struct device *axp_dev = to_axp_dev(rdev);
++	uint8_t reg_val;
++	int ret;
++	ret = axp_read(axp_dev, info->enable_reg, &reg_val);
++	if (ret)
++		return ret;
++
++	return !!(reg_val & (1 << info->enable_bit));
++}
++
++static int axp_list_voltage(struct regulator_dev *rdev, unsigned selector)
++{
++	struct axp_regulator_info *info = rdev_get_drvdata(rdev);
++	int ret;
++
++	ret = info->min_uV + info->step1_uV * selector;
++	if ((info->switch_uV != 0) && (info->step2_uV != 0) &&
++	(ret > info->switch_uV) && (info->new_level_uV != 0)) {
++		selector -= ((info->switch_uV-info->min_uV)/info->step1_uV);
++		ret = info->new_level_uV + info->step2_uV * selector;
++	} else if ((info->switch_uV != 0) && (info->step2_uV != 0) &&
++	(ret > info->switch_uV) && (info->new_level_uV == 0)) {
++		selector -= ((info->switch_uV-info->min_uV)/info->step1_uV);
++		ret = info->switch_uV + info->step2_uV * selector;
++	}
++	if (ret > info->max_uV)
++		return -EINVAL;
++	return ret;
++}
++
++static int axp_set_suspend_voltage(struct regulator_dev *rdev, int uV)
++{
++	return axp_set_voltage(rdev, uV, uV,NULL);
++}
++
++
++static struct regulator_ops axp_ops = {
++	.set_voltage	= axp_set_voltage,
++	.get_voltage	= axp_get_voltage,
++	.list_voltage	= axp_list_voltage,
++	.enable		= axp_enable,
++	.disable	= axp_disable,
++	.is_enabled	= axp_is_enabled,
++//	.set_suspend_enable		= axp_enable,
++//	.set_suspend_disable	= axp_disable,
++	.set_suspend_voltage	= axp_set_suspend_voltage,
++};
++
++
++static int axp_ldoio01_enable(struct regulator_dev *rdev)
++{
++	struct axp_regulator_info *info = rdev_get_drvdata(rdev);
++	struct device *axp_dev = to_axp_dev(rdev);
++
++	 axp_set_bits(axp_dev, info->enable_reg,0x03);
++	 return axp_clr_bits(axp_dev, info->enable_reg,0x04);
++}
++
++static int axp_ldoio01_disable(struct regulator_dev *rdev)
++{
++	struct axp_regulator_info *info = rdev_get_drvdata(rdev);
++	struct device *axp_dev = to_axp_dev(rdev);
++
++	return axp_clr_bits(axp_dev, info->enable_reg,0x07);
++}
++
++static int axp_ldoio01_is_enabled(struct regulator_dev *rdev)
++{
++	struct axp_regulator_info *info = rdev_get_drvdata(rdev);
++	struct device *axp_dev = to_axp_dev(rdev);
++	uint8_t reg_val;
++	int ret;
++
++	ret = axp_read(axp_dev, info->enable_reg, &reg_val);
++	if (ret)
++		return ret;
++
++	return (((reg_val &= 0x07)== 0x03)?1:0);
++}
++
++static struct regulator_ops axp_ldoio01_ops = {
++	.set_voltage	= axp_set_voltage,
++	.get_voltage	= axp_get_voltage,
++	.list_voltage	= axp_list_voltage,
++	.enable		= axp_ldoio01_enable,
++	.disable	= axp_ldoio01_disable,
++	.is_enabled	= axp_ldoio01_is_enabled,
++	.set_suspend_enable		= axp_ldoio01_enable,
++	.set_suspend_disable	= axp_ldoio01_disable,
++	.set_suspend_voltage	= axp_set_suspend_voltage,
++};
++
++
++#define AXP216_LDO(_id, min, max, step1, vreg, shift, nbits, ereg, ebit, switch_vol, step2, new_level)	\
++	AXP_LDO(AXP, _id, min, max, step1, vreg, shift, nbits, ereg, ebit, switch_vol, step2, new_level)
++
++#define AXP216_DCDC(_id, min, max, step1, vreg, shift, nbits, ereg, ebit, switch_vol, step2, new_level)	\
++	AXP_DCDC(AXP, _id, min, max, step1, vreg, shift, nbits, ereg, ebit, switch_vol, step2, new_level)
++
++
++
++static struct axp_regulator_info axp_regulator_info[12] = {
++	AXP216_LDO(RTC,	3000,	3000,	0,	LDO1,	0,	0,	LDO1EN,	0, 0, 0, 0),//ldo1 for rtc
++	AXP216_LDO(ALDO1,	700,	3300,	100,	LDO2,	0,	5,	LDO2EN,	6, 0, 0, 0),//ldo2 for aldo1
++	AXP216_LDO(ALDO2,	700,	3300,	100,	LDO3,	0,	5,	LDO3EN,	7, 0, 0, 0),//ldo3 for aldo2
++	AXP216_LDO(ALDO3,	700,	3300,	100,	LDO4,	0,	5,	LDO4EN,	5, 0, 0, 0),//ldo3 for aldo3
++
++	AXP216_LDO(ELDO1,	700,	3300,	100,	LDO9,	0,	5,	LDO9EN,	0, 0, 0, 0),//ldo9 for eldo1
++	AXP216_LDO(ELDO2,	700,	3300,	100,	LDO10,	0,	5,	LDO10EN,1, 0, 0, 0),//ldo10 for eldo2
++
++	AXP216_DCDC(1,	1600,	3400,	100,	DCDC1,	0,	5,	DCDC1EN,1, 0, 0, 0),//buck1 for io
++	AXP216_DCDC(2,	600,	1540,	20,	DCDC2,	0,	6,	DCDC2EN,2, 0, 0, 0),//buck2 for cpu
++	AXP216_DCDC(3,	600,	1860,	20,	DCDC3,	0,	6,	DCDC3EN,3, 0, 0, 0),//buck3 for gpu
++	AXP216_DCDC(4,	600,	2600,	20,	DCDC4,	0,	6,	DCDC4EN,4, 1540, 100, 1800),//buck4 for core
++	AXP216_DCDC(5,	1000,	2550,	50,	DCDC5,	0,	5,	DCDC5EN,5, 0, 0, 0),//buck5 for ddr
++
++	AXP216_LDO(LDOIO1,	700,	3300,	100,	LDOIO1,	0,	5,	LDOIO1EN,0, 0, 0, 0),//ldoio1
++};
++
++#define REGULATOR_NODE_NAME	"regulators"
++
++static ssize_t workmode_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct regulator_dev *rdev = dev_get_drvdata(dev);
++	struct axp_regulator_info *info = rdev_get_drvdata(rdev);
++	struct device *axp_dev = to_axp_dev(rdev);
++	int ret;
++	uint8_t val;
++	ret = axp_read(axp_dev, AXP_BUCKMODE, &val);
++	if (ret)
++		return sprintf(buf, "IO ERROR\n");
++
++	if(info->desc.id == AXP_ID_DCDC1){
++		switch (val & 0x04) {
++			case 0:return sprintf(buf, "AUTO\n");
++			case 4:return sprintf(buf, "PWM\n");
++			default:return sprintf(buf, "UNKNOWN\n");
++		}
++	}
++	else if(info->desc.id == AXP_ID_DCDC2){
++		switch (val & 0x02) {
++			case 0:return sprintf(buf, "AUTO\n");
++			case 2:return sprintf(buf, "PWM\n");
++			default:return sprintf(buf, "UNKNOWN\n");
++		}
++	}
++	else if(info->desc.id == AXP_ID_DCDC3){
++		switch (val & 0x02) {
++			case 0:return sprintf(buf, "AUTO\n");
++			case 2:return sprintf(buf, "PWM\n");
++			default:return sprintf(buf, "UNKNOWN\n");
++		}
++	}
++	else if(info->desc.id == AXP_ID_DCDC4){
++		switch (val & 0x02) {
++			case 0:return sprintf(buf, "AUTO\n");
++			case 2:return sprintf(buf, "PWM\n");
++			default:return sprintf(buf, "UNKNOWN\n");
++		}
++	}
++	else if(info->desc.id == AXP_ID_DCDC5){
++		switch (val & 0x02) {
++			case 0:return sprintf(buf, "AUTO\n");
++			case 2:return sprintf(buf, "PWM\n");
++			default:return sprintf(buf, "UNKNOWN\n");
++		}
++	}
++	else
++		return sprintf(buf, "IO ID ERROR\n");
++}
++
++static ssize_t workmode_store(struct device *dev,
++				struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct regulator_dev *rdev = dev_get_drvdata(dev);
++	struct axp_regulator_info *info = rdev_get_drvdata(rdev);
++	struct device *axp_dev = to_axp_dev(rdev);
++	char mode;
++	uint8_t val;
++	if(  buf[0] > '0' && buf[0] < '9' )// 1/AUTO: auto mode; 2/PWM: pwm mode;
++		mode = buf[0];
++	else
++		mode = buf[1];
++
++	switch(mode){
++	 case 'U':
++	 case 'u':
++	 case '1':
++		val = 0;break;
++	 case 'W':
++	 case 'w':
++	 case '2':
++	 	val = 1;break;
++	 default:
++	    val =0;
++	}
++
++	if(info->desc.id == AXP_ID_DCDC1){
++		if(val)
++			axp_set_bits(axp_dev, AXP_BUCKMODE,0x01);
++		else
++			axp_clr_bits(axp_dev, AXP_BUCKMODE,0x01);
++	}
++	else if(info->desc.id == AXP_ID_DCDC2){
++		if(val)
++			axp_set_bits(axp_dev, AXP_BUCKMODE,0x02);
++		else
++			axp_clr_bits(axp_dev, AXP_BUCKMODE,0x02);
++	}
++	else if(info->desc.id == AXP_ID_DCDC3){
++		if(val)
++			axp_set_bits(axp_dev, AXP_BUCKMODE,0x04);
++		else
++			axp_clr_bits(axp_dev, AXP_BUCKMODE,0x04);
++	}
++	else if(info->desc.id == AXP_ID_DCDC4){
++		if(val)
++			axp_set_bits(axp_dev, AXP_BUCKMODE,0x08);
++		else
++			axp_clr_bits(axp_dev, AXP_BUCKMODE,0x08);
++	}
++	else if(info->desc.id == AXP_ID_DCDC5){
++		if(val)
++			axp_set_bits(axp_dev, AXP_BUCKMODE,0x10);
++		else
++			axp_clr_bits(axp_dev, AXP_BUCKMODE,0x10);
++	}
++	return count;
++}
++
++static ssize_t frequency_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct regulator_dev *rdev = dev_get_drvdata(dev);
++	struct device *axp_dev = to_axp_dev(rdev);
++	int ret;
++	uint8_t val;
++	ret = axp_read(axp_dev, AXP_BUCKFREQ, &val);
++	if (ret)
++		return ret;
++	ret = val & 0x0F;
++	return sprintf(buf, "%d\n",(ret*75 + 750));
++}
++
++static ssize_t frequency_store(struct device *dev,
++				struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct regulator_dev *rdev = dev_get_drvdata(dev);
++	struct device *axp_dev = to_axp_dev(rdev);
++	uint8_t val,tmp;
++	int var;
++	var = simple_strtoul(buf, NULL, 10);
++	if(var < 750)
++		var = 750;
++	if(var > 1875)
++		var = 1875;
++
++	val = (var -750)/75;
++	val &= 0x0F;
++
++	axp_read(axp_dev, AXP_BUCKFREQ, &tmp);
++	tmp &= 0xF0;
++	val |= tmp;
++	axp_write(axp_dev, AXP_BUCKFREQ, val);
++	return count;
++}
++
++
++static struct device_attribute axp_regu_attrs[] = {
++	AXP_REGU_ATTR(workmode),
++	AXP_REGU_ATTR(frequency),
++};
++
++int axp_regu_create_attrs(struct platform_device *pdev)
++{
++	int j,ret;
++	for (j = 0; j < ARRAY_SIZE(axp_regu_attrs); j++) {
++		ret = device_create_file(&pdev->dev,&axp_regu_attrs[j]);
++		if (ret)
++			goto sysfs_failed;
++	}
++    goto succeed;
++
++sysfs_failed:
++	while (j--)
++		device_remove_file(&pdev->dev,&axp_regu_attrs[j]);
++succeed:
++	return ret;
++}
++
++static int  axp_regulator_probe(struct platform_device *pdev)
++{
++	struct regulator_dev *rdev;
++# if LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)
++	struct regulator_config config = { };
++#endif
++	struct  axp_reg_init * platform_data = (struct  axp_reg_init *)(pdev->dev.platform_data);
++	//struct axp_regulator_info *info = platform_data->info;
++	struct axp_regulator_info *ri = NULL;
++	int i;
++
++	dev_dbg(&pdev->dev, "pdev->name = %s\n",pdev->name);
++	dev_dbg(&pdev->dev, "pdev->dev.parent->driver->name %s\n",pdev->dev.parent->driver->name);
++	for (i = 0; i < 12; i++) {
++
++		ri = &axp_regulator_info[i];
++		if (ri->desc.id == AXP_ID_RTC || ri->desc.id == AXP_ID_ALDO1 \
++				|| ri->desc.id == AXP_ID_ALDO2 || ri->desc.id == AXP_ID_ALDO3 \
++				|| ri->desc.id == AXP_ID_ELDO1 || ri->desc.id == AXP_ID_ELDO2 \
++				|| ri->desc.id == AXP_ID_DCDC1 || ri->desc.id == AXP_ID_DCDC2 \
++				|| ri->desc.id == AXP_ID_DCDC3 || ri->desc.id == AXP_ID_DCDC4 \
++				|| ri->desc.id == AXP_ID_DCDC5 )
++			ri->desc.ops = &axp_ops;
++		if (ri->desc.id == AXP_ID_LDOIO1 )
++			ri->desc.ops = &axp_ldoio01_ops;
++
++		ri->desc.of_match	= of_match_ptr(ri->desc.name);
++		ri->desc.regulators_node = of_match_ptr(REGULATOR_NODE_NAME);
++
++		config.dev = pdev->dev.parent;
++		config.init_data = &(platform_data->axp_reg_init_data);
++		config.driver_data = ri;
++
++		rdev = devm_regulator_register(&pdev->dev, &ri->desc, &config);
++		if (IS_ERR(rdev)) {
++			dev_err(&pdev->dev, "failed to register %s regulator (errno %ld\n)\n",
++					ri->desc.name, PTR_ERR(rdev));
++			return PTR_ERR(rdev);
++		}
++	}
++	return 0;
++}
++
++static int  axp_regulator_remove(struct platform_device *pdev)
++{
++	struct regulator_dev *rdev = platform_get_drvdata(pdev);
++
++	regulator_unregister(rdev);
++	return 0;
++}
++
++static struct platform_driver axp_regulator_driver = {
++	.driver	= {
++		.name	= "axp216-regulator",
++		.owner	= THIS_MODULE,
++	},
++	.probe		= axp_regulator_probe,
++	.remove		= axp_regulator_remove,
++};
++
++static int __init axp_regulator_init(void)
++{
++	return platform_driver_register(&axp_regulator_driver);
++}
++subsys_initcall(axp_regulator_init);
++
++static void __exit axp_regulator_exit(void)
++{
++	platform_driver_unregister(&axp_regulator_driver);
++}
++module_exit(axp_regulator_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Criss");
++MODULE_DESCRIPTION("Regulator Driver for X-powers AXP216 PMIC");
++MODULE_ALIAS("platform:axp-regulator");
+diff --git a/module_drivers/drivers/power/supply/axp_power/axp-regu.h b/module_drivers/drivers/power/supply/axp_power/axp-regu.h
+new file mode 100644
+index 000000000..b50fb8e49
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/axp-regu.h
+@@ -0,0 +1,186 @@
++#ifndef _LINUX_AXP_REGU_H_
++#define _LINUX_AXP_REGU_H_
++
++#include "axp-cfg.h"
++#include "axp-mfd.h"
++
++/* AXP216 Regulator Registers */
++#define AXP_LDO1			AXP_STATUS
++#define AXP_LDO5	        AXP_DLDO1OUT_VOL
++#define AXP_LDO6	        AXP_DLDO2OUT_VOL
++#define AXP_LDO7	        AXP_DLDO3OUT_VOL
++#define AXP_LDO8	        AXP_DLDO4OUT_VOL
++#define AXP_LDO9			AXP_ELDO1OUT_VOL
++#define AXP_LDO10			AXP_ELDO2OUT_VOL
++#define AXP_LDO11			AXP_ELDO3OUT_VOL
++#define AXP_LDO12			AXP_DC5LDOOUT_VOL
++#define AXP_DCDC1	        AXP_DC1OUT_VOL
++#define AXP_DCDC2	        AXP_DC2OUT_VOL
++#define AXP_DCDC3	        AXP_DC3OUT_VOL
++#define AXP_DCDC4	        AXP_DC4OUT_VOL
++#define AXP_DCDC5	        AXP_DC5OUT_VOL
++
++#define AXP_LDOIO0		AXP_GPIO0LDOOUT_VOL
++#define AXP_LDOIO1		AXP_GPIO1LDOOUT_VOL
++#define AXP_LDO2	        AXP_ALDO1OUT_VOL
++#define AXP_LDO3	        AXP_ALDO2OUT_VOL
++#define AXP_LDO4	        AXP_ALDO3OUT_VOL
++#define AXP_SW0		AXP_STATUS
++
++#define AXP_LDO1EN		AXP_STATUS
++#define AXP_LDO2EN		AXP_LDO_DC_EN1
++#define AXP_LDO3EN		AXP_LDO_DC_EN1
++//#ifdef CONFIG_AXP809
++#define AXP_LDO4EN		AXP_LDO_DC_EN2
++//#else
++//#define AXP_LDO4EN		AXP_LDO_DC_EN3
++//#endif
++#define AXP_LDO5EN		AXP_LDO_DC_EN2
++#define AXP_LDO6EN		AXP_LDO_DC_EN2
++#define AXP_LDO7EN		AXP_LDO_DC_EN2
++#define AXP_LDO8EN		AXP_LDO_DC_EN2
++#define AXP_LDO9EN		AXP_LDO_DC_EN2
++#define AXP_LDO10EN		AXP_LDO_DC_EN2
++#define AXP_LDO11EN		AXP_LDO_DC_EN2
++#define AXP_LDO12EN		AXP_LDO_DC_EN1
++#define AXP_DCDC1EN		AXP_LDO_DC_EN1
++#define AXP_DCDC2EN		AXP_LDO_DC_EN1
++#define AXP_DCDC3EN		AXP_LDO_DC_EN1
++#define AXP_DCDC4EN		AXP_LDO_DC_EN1
++#define AXP_DCDC5EN		AXP_LDO_DC_EN1
++#define AXP_LDOIO0EN		AXP_GPIO0_CTL
++#define AXP_LDOIO1EN		AXP_GPIO1_CTL
++#define AXP_DC1SW1EN		AXP_LDO_DC_EN2
++#define AXP_SW0EN		AXP_LDO_DC_EN2
++
++#define AXP_BUCKMODE		AXP_DCDC_MODESET
++#define AXP_BUCKFREQ		AXP_DCDC_FREQSET
++
++#define AXP_LDO(_pmic, _id, min, max, step1, vreg, shift, nbits, ereg, ebit, switch_vol, step2, new_level)	\
++{									\
++	.desc	= {							\
++/*		.name	= #_pmic"_LDO" #_id,				*/\
++		.name	= #_id,					        \
++		.type	= REGULATOR_VOLTAGE,				\
++		.id	= _pmic##_ID_##_id,				\
++		.n_voltages = (step1) ? ( (switch_vol) ? ((switch_vol - min) / step1 +	\
++				(max - switch_vol) / step2  +1):	\
++				((max - min) / step1 +1) ): 1,		\
++		.owner	= THIS_MODULE,					\
++	},								\
++	.min_uV		= (min) * 1000,					\
++	.max_uV		= (max) * 1000,					\
++	.step1_uV	= (step1) * 1000,				\
++	.vol_reg	= _pmic##_##vreg,				\
++	.vol_shift	= (shift),					\
++	.vol_nbits	= (nbits),					\
++	.enable_reg	= _pmic##_##ereg,				\
++	.enable_bit	= (ebit),					\
++	.switch_uV	= (switch_vol)*1000,				\
++	.step2_uV	= (step2)*1000,					\
++	.new_level_uV	= (new_level)*1000,				\
++}
++
++#define AXP_BUCK(_pmic, _id, min, max, step1, vreg, shift, nbits, ereg, ebit, switch_vol, step2, new_level) \
++{									\
++	.desc	= {							\
++		.name	= #_pmic"_BUCK" #_id,					\
++		.type	= REGULATOR_VOLTAGE,				\
++		.id	= _pmic##_ID_BUCK##_id,				\
++		.n_voltages = (step1) ? ( (switch_vol) ? ((new_level)?((switch_vol - min) / step1 +	\
++				(max - new_level) / step2  +2) : ((switch_vol - min) / step1 +	\
++				(max - switch_vol) / step2  +1)):	\
++				((max - min) / step1 +1) ): 1,		\
++	},								\
++	.min_uV		= (min) * 1000,					\
++	.max_uV		= (max) * 1000,					\
++	.step1_uV	= (step1) * 1000,				\
++	.vol_reg	= _pmic##_##vreg,				\
++	.vol_shift	= (shift),					\
++	.vol_nbits	= (nbits),					\
++	.enable_reg	= _pmic##_##ereg,				\
++	.enable_bit	= (ebit),					\
++	.switch_uV	= (switch_vol)*1000,				\
++	.step2_uV	= (step2)*1000,					\
++	.new_level_uV	= (new_level)*1000,				\
++}
++
++#define AXP_DCDC(_pmic, _id, min, max, step1, vreg, shift, nbits, ereg, ebit, switch_vol, step2, new_level)	\
++{									\
++	.desc	= {							\
++		.name	= "DCDC"#_id,					\
++		.type	= REGULATOR_VOLTAGE,				\
++		.id	= _pmic##_ID_DCDC##_id,				\
++		.n_voltages = (step1) ? ( (switch_vol) ? ((new_level)?((switch_vol - min) / step1 +	\
++				(max - new_level) / step2  +2) : ((switch_vol - min) / step1 +	\
++				(max - switch_vol) / step2  +1)):	\
++				((max - min) / step1 +1) ): 1,		\
++		.owner	= THIS_MODULE,					\
++	},								\
++	.min_uV		= (min) * 1000,					\
++	.max_uV		= (max) * 1000,					\
++	.step1_uV	= (step1) * 1000,				\
++	.vol_reg	= _pmic##_##vreg,				\
++	.vol_shift	= (shift),					\
++	.vol_nbits	= (nbits),					\
++	.enable_reg	= _pmic##_##ereg,				\
++	.enable_bit	= (ebit),					\
++	.switch_uV	= (switch_vol)*1000,				\
++	.step2_uV	= (step2)*1000,					\
++	.new_level_uV	= (new_level)*1000,				\
++}
++//AXP_LDO2EN
++#define AXP_SW(_pmic, _id, min, max, step1, vreg, shift, nbits, ereg, ebit, switch_vol, step2, new_level) \
++{									\
++	.desc	= {							\
++		.name	= #_pmic"_SW" #_id,					\
++		.type	= REGULATOR_VOLTAGE,				\
++		.id	= _pmic##_ID_SW##_id,				\
++		.n_voltages = (step1) ? ( (switch_vol) ? ((new_level)?((switch_vol - min) / step1 +	\
++				(max - new_level) / step2  +2) : ((switch_vol - min) / step1 +	\
++				(max - switch_vol) / step2  +1)):	\
++				((max - min) / step1 +1) ): 1,		\
++		.owner	= THIS_MODULE,					\
++	},								\
++	.min_uV		= (min) * 1000,					\
++	.max_uV		= (max) * 1000,					\
++	.step1_uV	= (step1) * 1000,				\
++	.vol_reg	= _pmic##_##vreg,				\
++	.vol_shift	= (shift),					\
++	.vol_nbits	= (nbits),					\
++	.enable_reg	= _pmic##_##ereg,				\
++	.enable_bit	= (ebit),					\
++	.switch_uV	= (switch_vol)*1000,				\
++	.step2_uV	= (step2)*1000,					\
++	.new_level_uV	= (new_level)*1000,				\
++}
++
++#define AXP_REGU_ATTR(_name)						\
++{									\
++	.attr = { .name = #_name,.mode = 0644 },			\
++	.show =  _name##_show,						\
++	.store = _name##_store,						\
++}
++
++struct axp_regulator_info {
++	struct regulator_desc desc;
++
++	int	min_uV;
++	int	max_uV;
++	int	step1_uV;
++	int	vol_reg;
++	int	vol_shift;
++	int	vol_nbits;
++	int	enable_reg;
++	int	enable_bit;
++	int	switch_uV;
++	int	step2_uV;
++	int	new_level_uV;
++};
++
++struct  axp_reg_init {
++	struct regulator_init_data axp_reg_init_data;
++	struct axp_regulator_info *info;
++};
++
++#endif
+diff --git a/module_drivers/drivers/power/supply/axp_power/axp-rw.c b/module_drivers/drivers/power/supply/axp_power/axp-rw.c
+new file mode 100644
+index 000000000..54e90063c
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/axp-rw.c
+@@ -0,0 +1,142 @@
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <mach/irqs.h>
++#include <linux/module.h>
++#include <linux/apm_bios.h>
++#include <linux/apm-emulation.h>
++#include <linux/mfd/axp-mfd.h>
++#include "axp-cfg.h"
++#include "axp-rw.h"
++
++int axp_register_notifier(struct device *dev, struct notifier_block *nb,
++				uint64_t irqs)
++{
++	struct axp_dev *chip = dev_get_drvdata(dev);
++
++	chip->ops->enable_irqs(chip, irqs);
++	if(NULL != nb) {
++	    return blocking_notifier_chain_register(&chip->notifier_list, nb);
++	}
++
++    return 0;
++}
++EXPORT_SYMBOL_GPL(axp_register_notifier);
++
++int axp_unregister_notifier(struct device *dev, struct notifier_block *nb,
++				uint64_t irqs)
++{
++	struct axp_dev *chip = dev_get_drvdata(dev);
++
++	chip->ops->disable_irqs(chip, irqs);
++	if(NULL != nb) {
++	    return blocking_notifier_chain_unregister(&chip->notifier_list, nb);
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(axp_unregister_notifier);
++
++int axp_write(struct device *dev, int reg, uint8_t val)
++{
++
++
++	return __axp_write(to_i2c_client(dev), reg, val);
++}
++EXPORT_SYMBOL_GPL(axp_write);
++
++int axp_writes(struct device *dev, int reg, int len, uint8_t *val)
++{
++
++
++	return  __axp_writes(to_i2c_client(dev), reg, len, val);
++}
++EXPORT_SYMBOL_GPL(axp_writes);
++
++int axp_read(struct device *dev, int reg, uint8_t *val)
++{
++
++
++	return __axp_read(to_i2c_client(dev), reg, val);
++}
++EXPORT_SYMBOL_GPL(axp_read);
++
++int axp_reads(struct device *dev, int reg, int len, uint8_t *val)
++{
++
++
++	return __axp_reads(to_i2c_client(dev), reg, len, val);
++}
++EXPORT_SYMBOL_GPL(axp_reads);
++
++int axp_set_bits(struct device *dev, int reg, uint8_t bit_mask)
++{
++	uint8_t reg_val;
++	int ret = 0;
++	struct axp_dev *chip;
++
++	chip = dev_get_drvdata(dev);
++
++	mutex_lock(&chip->lock);
++	ret = __axp_read(chip->client, reg, &reg_val);
++	if (ret)
++		goto out;
++
++	if ((reg_val & bit_mask) != bit_mask) {
++		reg_val |= bit_mask;
++		ret = __axp_write(chip->client, reg, reg_val);
++	}
++out:
++	mutex_unlock(&chip->lock);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(axp_set_bits);
++
++int axp_clr_bits(struct device *dev, int reg, uint8_t bit_mask)
++{
++	uint8_t reg_val;
++	int ret = 0;
++	struct axp_dev *chip;
++
++	chip = dev_get_drvdata(dev);
++
++	mutex_lock(&chip->lock);
++
++	ret = __axp_read(chip->client, reg, &reg_val);
++	if (ret)
++		goto out;
++
++	if (reg_val & bit_mask) {
++		reg_val &= ~bit_mask;
++		ret = __axp_write(chip->client, reg, reg_val);
++	}
++out:
++	mutex_unlock(&chip->lock);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(axp_clr_bits);
++
++int axp_update(struct device *dev, int reg, uint8_t val, uint8_t mask)
++{
++	struct axp_dev *chip = dev_get_drvdata(dev);
++	uint8_t reg_val;
++	int ret = 0;
++
++	mutex_lock(&chip->lock);
++
++	ret = __axp_read(chip->client, reg, &reg_val);
++	if (ret)
++		goto out;
++
++	if ((reg_val & mask) != val) {
++		reg_val = (reg_val & ~mask) | val;
++		ret = __axp_write(chip->client, reg, reg_val);
++	}
++out:
++	mutex_unlock(&chip->lock);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(axp_update);
++
+diff --git a/module_drivers/drivers/power/supply/axp_power/axp-rw.h b/module_drivers/drivers/power/supply/axp_power/axp-rw.h
+new file mode 100644
+index 000000000..323010efc
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/axp-rw.h
+@@ -0,0 +1,209 @@
++/*
++ * Read/Write driver for X-Powers AXP
++ *
++ * Copyright (C) 2013 X-Powers, Ltd.
++ *  Zhang Donglu <zhangdonglu@x-powers.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++ 
++#ifndef _LINUX_AXP_RW_H_
++#define _LINUX_AXP_RW_H_
++
++#include <linux/i2c.h>
++#include "axp-mfd.h"
++
++static uint8_t axp_reg_addr = 0;
++
++struct i2c_client *axp;
++EXPORT_SYMBOL_GPL(axp);
++
++static inline int __axp_read(struct i2c_client *client,
++				int reg, uint8_t *val)
++{
++	int ret;
++	//printk("[AXP216-rw] axp_read reg=0x%02x!\n",reg);
++	ret = i2c_smbus_read_byte_data(client, reg);
++	if (ret < 0) {
++		dev_err(&client->dev, "failed reading at 0x%02x\n", reg);
++		return ret;
++	}
++
++	*val = (uint8_t)ret;
++
++	return 0;
++}
++
++static inline int __axp_reads(struct i2c_client *client, int reg,
++				 int len, uint8_t *val)
++{
++	int ret;
++
++	ret = i2c_smbus_read_i2c_block_data(client, reg, len, val);
++	if (ret < 0) {
++		dev_err(&client->dev, "failed reading from 0x%02x\n", reg);
++		return ret;
++	}
++	return 0;
++}
++
++static inline int __axp_write(struct i2c_client *client,
++				 int reg, uint8_t val)
++{
++	int ret;
++//	printk("[AXP216-rw] __axp_write reg=0x%02x,val=0x%02x!\n",reg,val);
++	
++	ret = i2c_smbus_write_byte_data(client, reg, val);
++	if (ret < 0) {
++		dev_err(&client->dev, "failed writing 0x%02x to 0x%02x\n",
++				val, reg);
++		return ret;
++	}
++
++	return 0;
++}
++
++
++static inline int __axp_writes(struct i2c_client *client, int reg,
++				  int len, uint8_t *val)
++{
++	int ret;
++
++	ret = i2c_smbus_write_i2c_block_data(client, reg, len, val);
++	if (ret < 0) {
++		dev_err(&client->dev, "failed writings to 0x%02x\n", reg);
++		return ret;
++	}
++
++	return 0;
++}
++
++int axp_register_notifier(struct device *dev, struct notifier_block *nb,
++				uint64_t irqs)
++{
++	struct axp_mfd_chip *chip = dev_get_drvdata(dev);
++
++	chip->ops->enable_irqs(chip, irqs);
++	if(NULL != nb) {
++	    return blocking_notifier_chain_register(&chip->notifier_list, nb);
++    }
++
++    return 0;
++}
++EXPORT_SYMBOL_GPL(axp_register_notifier);
++
++int axp_unregister_notifier(struct device *dev, struct notifier_block *nb,
++				uint64_t irqs)
++{
++	struct axp_mfd_chip *chip = dev_get_drvdata(dev);
++
++	chip->ops->disable_irqs(chip, irqs);
++	if(NULL != nb) {
++	    return blocking_notifier_chain_unregister(&chip->notifier_list, nb);
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(axp_unregister_notifier);
++
++int axp_write(struct device *dev, int reg, uint8_t val)
++{
++	return __axp_write(to_i2c_client(dev), reg, val);
++}
++EXPORT_SYMBOL_GPL(axp_write);
++
++int axp_writes(struct device *dev, int reg, int len, uint8_t *val)
++{
++	return  __axp_writes(to_i2c_client(dev), reg, len, val);
++}
++EXPORT_SYMBOL_GPL(axp_writes);
++
++int axp_read(struct device *dev, int reg, uint8_t *val)
++{
++	return __axp_read(to_i2c_client(dev), reg, val);
++}
++EXPORT_SYMBOL_GPL(axp_read);
++
++int axp_reads(struct device *dev, int reg, int len, uint8_t *val)
++{
++	return __axp_reads(to_i2c_client(dev), reg, len, val);
++}
++EXPORT_SYMBOL_GPL(axp_reads);
++
++int axp_set_bits(struct device *dev, int reg, uint8_t bit_mask)
++{
++	uint8_t reg_val;
++	int ret = 0;
++	struct axp_mfd_chip *chip;
++
++	chip = dev_get_drvdata(dev);
++	mutex_lock(&chip->lock);
++	ret = __axp_read(chip->client, reg, &reg_val);
++	if (ret)
++		goto out;
++
++	if ((reg_val & bit_mask) != bit_mask) {
++		reg_val |= bit_mask;
++		ret = __axp_write(chip->client, reg, reg_val);
++	}
++out:
++	mutex_unlock(&chip->lock);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(axp_set_bits);
++
++int axp_clr_bits(struct device *dev, int reg, uint8_t bit_mask)
++{
++	uint8_t reg_val;
++	int ret = 0;
++	struct axp_mfd_chip *chip;
++	
++	chip = dev_get_drvdata(dev);
++
++	mutex_lock(&chip->lock);
++
++	ret = __axp_read(chip->client, reg, &reg_val);
++	if (ret)
++		goto out;
++
++	if (reg_val & bit_mask) {
++		reg_val &= ~bit_mask;
++		ret = __axp_write(chip->client, reg, reg_val);
++	}
++out:
++	mutex_unlock(&chip->lock);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(axp_clr_bits);
++
++int axp_update(struct device *dev, int reg, uint8_t val, uint8_t mask)
++{
++	struct axp_mfd_chip *chip = dev_get_drvdata(dev);
++	uint8_t reg_val;
++	int ret = 0;
++
++	mutex_lock(&chip->lock);
++
++	ret = __axp_read(chip->client, reg, &reg_val);
++	if (ret)
++		goto out;
++
++	if ((reg_val & mask) != val) {
++		reg_val = (reg_val & ~mask) | val;
++		ret = __axp_write(chip->client, reg, reg_val);
++	}
++out:
++	mutex_unlock(&chip->lock);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(axp_update);
++
++struct device *axp_get_dev(void)
++{
++	return &axp->dev;
++}
++EXPORT_SYMBOL_GPL(axp_get_dev);
++
++#endif
+diff --git a/module_drivers/drivers/power/supply/axp_power/axp-sply.c b/module_drivers/drivers/power/supply/axp_power/axp-sply.c
+new file mode 100755
+index 000000000..337f66e15
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/axp-sply.c
+@@ -0,0 +1,2297 @@
++/*
++ * Battery charger driver for X-Powers AXP
++ *
++ * Copyright (C) 2013 X-Powers, Ltd.
++ *  Zhang Donglu <zhangdonglu@x-powers.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/types.h>
++#include <linux/err.h>
++#include <linux/device.h>
++#include <linux/workqueue.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/power_supply.h>
++
++#include <linux/delay.h>
++#include <linux/kthread.h>
++#include <linux/slab.h>
++#include <linux/debugfs.h>
++#include <linux/seq_file.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <asm/div64.h>
++//#include <mach/gpio.h>
++
++
++#include "axp-cfg.h"
++#include "axp-sply.h"
++
++#ifdef CONFIG_HAS_EARLYSUSPEND
++#include <linux/earlysuspend.h>
++#endif
++
++
++
++#include <linux/gpio.h>
++
++#define DBG_AXP_PSY 0
++#if  DBG_AXP_PSY
++#define DBG_PSY_MSG(format,args...)   printk( "[AXP]"format,##args)
++#else
++#define DBG_PSY_MSG(format,args...)   do {} while (0)
++#endif
++
++static int axp_debug = 0;
++static uint8_t axp_reg_addr = 0;
++struct axp_adc_res adc;
++struct delayed_work usbwork;
++#ifdef CONFIG_HAS_EARLYSUSPEND
++static struct early_suspend axp_early_suspend;
++int early_suspend_flag = 0;
++#endif
++
++int pmu_usbvolnew = 0;
++int pmu_usbcurnew = 0;
++int axp_usbcurflag = 0;
++int axp_usbvolflag = 0;
++
++int axp_chip_id_get(uint8_t chip_id[16])
++{
++	uint8_t ret;
++	ret = axp_write(axp_charger->master,0xff,0x01);
++	if(ret)
++	{
++		printk("[axpx] axpx write REG_ff fail!");
++	}
++	axp_reads(axp_charger->master,0x20,16,chip_id);
++	if(ret)
++	{
++		printk("[axpx] axpx reads REG_12x fail!");
++	}
++	axp_write(axp_charger->master,0xff,0x00);
++	if(ret)
++	{
++		printk("[axpx] axpx write REG_ff fail!");
++	}
++
++    return ret;
++}
++EXPORT_SYMBOL_GPL(axp_chip_id_get);
++/*¿ØÖÆusbµçѹµÄ¿ª¹Ø£¬ÆÚÍûÔÚÍâ½Óusb host ³äµçʱµ÷ÓÃ*/
++int axp_usbvol(void)
++{
++	axp_usbvolflag = 1;
++    return 0;
++}
++EXPORT_SYMBOL_GPL(axp_usbvol);
++
++int axp_usb_det(void)
++{
++	uint8_t ret;
++	axp_read(axp_charger->master,AXP_CHARGE_STATUS,&ret);
++	if(ret & 0x10)/*usb or usb adapter can be used*/
++	{
++		return 1;
++	}
++	else/*no usb or usb adapter*/
++	{
++		return 0;
++	}
++}
++EXPORT_SYMBOL_GPL(axp_usb_det);
++
++/*¿ØÖÆusbµçÁ÷µÄ¿ª¹Ø£¬ÆÚÍûÔÚÍâ½Óusb host ³äµçʱµ÷ÓÃ*/
++int axp_usbcur(void)
++{
++    axp_usbcurflag = 1;
++    return 0;
++}
++EXPORT_SYMBOL_GPL(axp_usbcur);
++/*¿ØÖÆusbµçѹµÄ¿ª¹Ø£¬ÆÚÍûÔÚ´Óusb host °Î³öʱµ÷ÓÃ*/
++int axp_usbvol_restore(void)
++{
++ 	axp_usbvolflag = 0;
++    return 0;
++}
++EXPORT_SYMBOL_GPL(axp_usbvol_restore);
++/*¿ØÖÆusbµçÁ÷µÄ¿ª¹Ø£¬ÆÚÍûÔÚ´Óusb host °Î³öʱµ÷ÓÃ*/
++int axp_usbcur_restore(void)
++{
++	axp_usbcurflag = 0;
++    return 0;
++}
++EXPORT_SYMBOL_GPL(axp_usbcur_restore);
++
++/*µ÷ÊÔ½Ó¿Ú*/
++static ssize_t axp_reg_show(struct class *class, struct class_attribute *attr, char *buf)
++{
++    uint8_t val;
++    axp_read(axp_charger->master,axp_reg_addr,&val);
++    return sprintf(buf,"REG[%x]=%x\n",axp_reg_addr,val);
++}
++
++static ssize_t axp_reg_store(struct class *class, struct class_attribute *attr, const char *buf, size_t count)
++{
++    int tmp;
++    uint8_t val;
++    tmp = simple_strtoul(buf, NULL, 16);
++    if( tmp < 256 )
++    	axp_reg_addr = tmp;
++    else {
++    	val = tmp & 0x00FF;
++    	axp_reg_addr= (tmp >> 8) & 0x00FF;
++    	axp_write(axp_charger->master,axp_reg_addr, val);
++    }
++    return count;
++}
++
++static ssize_t axp_regs_show(struct class *class, struct class_attribute *attr, char *buf)
++{
++    uint8_t val[4];
++    axp_reads(axp_charger->master,axp_reg_addr,4,val);
++    return sprintf(buf,"REG[0x%x]=0x%x,REG[0x%x]=0x%x,REG[0x%x]=0x%x,REG[0x%x]=0x%x\n",axp_reg_addr,val[0],axp_reg_addr+1,val[1],axp_reg_addr+2,val[2],axp_reg_addr+3,val[3]);
++}
++
++static ssize_t axp_regs_store(struct class *class,struct class_attribute *attr, const char *buf, size_t count)
++{
++	int tmp;
++	uint8_t val[5];
++	tmp = simple_strtoul(buf, NULL, 16);
++	if( tmp < 256 )
++        	axp_reg_addr = tmp;
++	else {
++		axp_reg_addr= (tmp >> 24) & 0xFF;
++		val[0] = (tmp >> 16) & 0xFF;
++		val[1] =  axp_reg_addr + 1;
++		val[2] = (tmp >>  8)& 0xFF;
++		val[3] =  axp_reg_addr + 2;
++		val[4] = (tmp >>  0)& 0xFF;
++		axp_writes(axp_charger->master,axp_reg_addr,5,val);
++	}
++	return count;
++}
++
++static ssize_t axpdebug_store(struct class *class, struct class_attribute *attr, const char *buf, size_t count)
++{
++    if(buf[0] == '1'){
++        axp_debug = 1;
++    }
++    else{
++        axp_debug = 0;
++    }
++    return count;
++}
++
++static ssize_t axpdebug_show(struct class *class,struct class_attribute *attr, char *buf)
++{
++    return sprintf(buf, "bat-debug value is %d\n", axp_debug);
++}
++
++static CLASS_ATTR_RW(axpdebug);
++static CLASS_ATTR_RW(axp_reg);
++static CLASS_ATTR_RW(axp_regs);
++
++static struct attribute *axppower_class_attrs[] = {
++  &class_attr_axpdebug.attr,
++  &class_attr_axp_reg.attr,
++  &class_attr_axp_regs.attr,
++  NULL,
++};
++
++ATTRIBUTE_GROUPS(axppower_class);
++
++static struct class axppower_class = {
++    .name = "axppower",
++    .class_groups = axppower_class_groups,
++};
++
++int ADC_Freq_Get(struct axp_charger *charger)
++{
++	uint8_t  temp;
++	int  rValue = 25;
++
++	axp_read(charger->master, AXP_ADC_CONTROL3,&temp);
++	temp &= 0xc0;
++	switch(temp >> 6)
++	{
++		case 0:
++			rValue = 100;
++			break;
++		case 1:
++			rValue = 200;
++			break;
++		case 2:
++			rValue = 400;
++			break;
++		case 3:
++			rValue = 800;
++			break;
++		default:
++			break;
++	}
++	return rValue;
++}
++static inline int axp22_vts_to_mV(uint16_t reg)
++{
++    return ((int)(((reg >> 8) << 4 ) | (reg & 0x000F))) * 800 / 1000;
++}
++static inline int axp_vbat_to_mV(uint16_t reg)
++{
++  return ((int)((( reg >> 8) << 4 ) | (reg & 0x000F))) * 1100 / 1000;
++}
++
++static inline int axp_ocvbat_to_mV(uint16_t reg)
++{
++  return ((int)((( reg >> 8) << 4 ) | (reg & 0x000F))) * 1100 / 1000;
++}
++
++
++static inline int axp_vdc_to_mV(uint16_t reg)
++{
++  return ((int)(((reg >> 8) << 4 ) | (reg & 0x000F))) * 1700 / 1000;
++}
++
++
++static inline int axp_ibat_to_mA(uint16_t reg)
++{
++    return ((int)(((reg >> 8) << 4 ) | (reg & 0x000F))) ;
++}
++
++static inline int axp_icharge_to_mA(uint16_t reg)
++{
++    return ((int)(((reg >> 8) << 4 ) | (reg & 0x000F)));
++}
++
++static inline int axp_iac_to_mA(uint16_t reg)
++{
++    return ((int)(((reg >> 8) << 4 ) | (reg & 0x000F))) * 625 / 1000;
++}
++
++static inline int axp_iusb_to_mA(uint16_t reg)
++{
++    return ((int)(((reg >> 8) << 4 ) | (reg & 0x000F))) * 375 / 1000;
++}
++
++
++static inline void axp_read_adc(struct axp_charger *charger,
++  struct axp_adc_res *adc)
++{
++  uint8_t tmp[8];
++//
++//  axp_reads(charger->master,AXP_VACH_RES,8,tmp);
++  adc->vac_res = 0;
++  adc->iac_res = 0;
++  adc->vusb_res = 0;
++  adc->iusb_res = 0;
++  axp_reads(charger->master,AXP_VBATH_RES,6,tmp);
++  adc->vbat_res = ((uint16_t) tmp[0] << 8 )| tmp[1];
++  adc->ichar_res = ((uint16_t) tmp[2] << 8 )| tmp[3];
++  adc->idischar_res = ((uint16_t) tmp[4] << 8 )| tmp[5];
++  axp_reads(charger->master,AXP_OCVBATH_RES,2,tmp);
++  adc->ocvbat_res = ((uint16_t) tmp[0] << 8 )| tmp[1];
++}
++
++
++static void axp_charger_update_state(struct axp_charger *charger)
++{
++  uint8_t val[2];
++  uint16_t tmp;
++  axp_reads(charger->master,AXP_CHARGE_STATUS,2,val);
++  tmp = (val[1] << 8 )+ val[0];
++  charger->is_on = (val[1] & AXP_IN_CHARGE) ? 1 : 0;
++  charger->fault = val[1];
++  charger->bat_det = (tmp & AXP_STATUS_BATEN)?1:0;
++  charger->ac_det = (tmp & AXP_STATUS_ACEN)?1:0;
++  charger->usb_det = (tmp & AXP_STATUS_USBEN)?1:0;
++  charger->usb_valid = (tmp & AXP_STATUS_USBVA)?1:0;
++  charger->ac_valid = (tmp & AXP_STATUS_ACVA)?1:0;
++  charger->ext_valid = charger->ac_valid | charger->usb_valid;
++  charger->bat_current_direction = (tmp & AXP_STATUS_BATCURDIR)?1:0;
++  charger->in_short = (tmp& AXP_STATUS_ACUSBSH)?1:0;
++  charger->batery_active = (tmp & AXP_STATUS_BATINACT)?1:0;
++  charger->int_over_temp = (tmp & AXP_STATUS_ICTEMOV)?1:0;
++  axp_read(charger->master,AXP_CHARGE_CONTROL1,val);
++  charger->charge_on = ((val[0] >> 7) & 0x01);
++}
++
++static void axp_charger_update(struct axp_charger *charger)
++{
++  uint16_t tmp;
++  uint8_t val[2];
++	//int bat_temp_mv;
++  charger->adc = &adc;
++  axp_read_adc(charger, &adc);
++  tmp = charger->adc->vbat_res;
++  charger->vbat = axp_vbat_to_mV(tmp);
++  tmp = charger->adc->ocvbat_res;
++  charger->ocv = axp_ocvbat_to_mV(tmp);
++   //tmp = charger->adc->ichar_res + charger->adc->idischar_res;
++  charger->ibat = ABS(axp_icharge_to_mA(charger->adc->ichar_res)-axp_ibat_to_mA(charger->adc->idischar_res));
++  tmp = 00;
++  charger->vac = axp_vdc_to_mV(tmp);
++  tmp = 00;
++  charger->iac = axp_iac_to_mA(tmp);
++  tmp = 00;
++  charger->vusb = axp_vdc_to_mV(tmp);
++  tmp = 00;
++  charger->iusb = axp_iusb_to_mA(tmp);
++  axp_reads(charger->master,AXP_INTTEMP,2,val);
++  //DBG_PSY_MSG("TEMPERATURE:val1=0x%x,val2=0x%x\n",val[1],val[0]);
++  tmp = (val[0] << 4 ) + (val[1] & 0x0F);
++  charger->ic_temp = (int) tmp *1063/10000  - 2667/10;
++  charger->disvbat =  charger->vbat;
++  charger->disibat =  axp_ibat_to_mA(charger->adc->idischar_res);
++//	tmp = charger->adc->ts_res;
++//	bat_temp_mv = axp22_vts_to_mV(tmp);
++//	charger->bat_temp = axp22_vts_to_temp(bat_temp_mv);
++}
++
++#if defined  (CONFIG_AXP_CHARGEINIT)
++static void axp_set_charge(struct axp_charger *charger)
++{
++  uint8_t val=0x00;
++  uint8_t tmp=0x00;
++	if(charger->chgvol < 4200000){
++		val &= ~(3 << 5);
++	}else if (charger->chgvol<4240000){
++		val &= ~(3 << 5);
++		val |= 1 << 5;
++	}else if (charger->chgvol<4350000){
++		val &= ~(3 << 5);
++		val |= 1 << 6;
++	}else{
++		val |= 3 << 5;
++	}
++
++	if(charger->chgcur == 0)
++		charger->chgen = 0;
++
++    if(charger->chgcur< 300000)
++      charger->chgcur = 300000;
++    else if(charger->chgcur > 2550000)
++     charger->chgcur = 2550000;
++
++    val |= (charger->chgcur - 300000) / 150000 ;
++    if(charger ->chgend == 10){
++      val &= ~(1 << 4);
++    }
++    else {
++      val |= 1 << 4;
++    }
++    val &= 0x7F;
++    val |= charger->chgen << 7;
++      if(charger->chgpretime < 30)
++      charger->chgpretime = 30;
++    if(charger->chgcsttime < 360)
++      charger->chgcsttime = 360;
++
++    tmp = ((((charger->chgpretime - 40) / 10) << 6)  \
++      | ((charger->chgcsttime - 360) / 120));
++	axp_write(charger->master, AXP_CHARGE_CONTROL1,val);
++	axp_update(charger->master, AXP_CHARGE_CONTROL2,tmp,0xC2);
++}
++#else
++static void axp_set_charge(struct axp_charger *charger)
++{
++
++}
++#endif
++
++static enum power_supply_property axp_battery_props[] = {
++  POWER_SUPPLY_PROP_MODEL_NAME,
++  POWER_SUPPLY_PROP_STATUS,
++  POWER_SUPPLY_PROP_PRESENT,
++  POWER_SUPPLY_PROP_ONLINE,
++  POWER_SUPPLY_PROP_HEALTH,
++  POWER_SUPPLY_PROP_TECHNOLOGY,
++  POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
++  POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
++  POWER_SUPPLY_PROP_VOLTAGE_NOW,
++  POWER_SUPPLY_PROP_CURRENT_NOW,
++  //POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
++  //POWER_SUPPLY_PROP_CHARGE_FULL,
++  POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN,
++  POWER_SUPPLY_PROP_CAPACITY,
++  //POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
++  //POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,
++  //POWER_SUPPLY_PROP_TEMP,
++};
++
++static enum power_supply_property axp_ac_props[] = {
++  POWER_SUPPLY_PROP_MODEL_NAME,
++  POWER_SUPPLY_PROP_PRESENT,
++  POWER_SUPPLY_PROP_ONLINE,
++  POWER_SUPPLY_PROP_VOLTAGE_NOW,
++  POWER_SUPPLY_PROP_CURRENT_NOW,
++};
++
++static enum power_supply_property axp_usb_props[] = {
++  POWER_SUPPLY_PROP_MODEL_NAME,
++  POWER_SUPPLY_PROP_PRESENT,
++  POWER_SUPPLY_PROP_ONLINE,
++  POWER_SUPPLY_PROP_VOLTAGE_NOW,
++  POWER_SUPPLY_PROP_CURRENT_NOW,
++};
++
++static void axp_battery_check_status(struct axp_charger *charger,
++            union power_supply_propval *val)
++{
++  if (charger->bat_det) {
++    if (charger->ext_valid){
++    	if( charger->rest_vol == 100)
++        val->intval = POWER_SUPPLY_STATUS_FULL;
++    	else if(charger->charge_on)
++    		val->intval = POWER_SUPPLY_STATUS_CHARGING;
++    	else
++    		val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
++    }
++    else
++      val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
++  }
++  else
++    val->intval = POWER_SUPPLY_STATUS_FULL;
++}
++
++static void axp_battery_check_health(struct axp_charger *charger,
++            union power_supply_propval *val)
++{
++    if (charger->fault & AXP_FAULT_LOG_BATINACT)
++    val->intval = POWER_SUPPLY_HEALTH_DEAD;
++  else if (charger->fault & AXP_FAULT_LOG_OVER_TEMP)
++    val->intval = POWER_SUPPLY_HEALTH_OVERHEAT;
++  else if (charger->fault & AXP_FAULT_LOG_COLD)
++    val->intval = POWER_SUPPLY_HEALTH_COLD;
++  else
++    val->intval = POWER_SUPPLY_HEALTH_GOOD;
++}
++
++static int axp_battery_get_property(struct power_supply *psy,
++           enum power_supply_property psp,
++           union power_supply_propval *val)
++{
++  struct axp_charger *charger;
++  int ret = 0;
++  //charger = container_of(psy, struct axp_charger, batt);
++  charger = (struct axp_charger*)psy->drv_data;
++  //printk("%s() psp=%x, charger=%p, psy=%p\n", __func__, psp, charger, psy);
++  //printk("%s() psp=%x, charger->batt->desc=%p\n", __func__, psp, charger->batt->desc);
++  switch (psp) {
++  case POWER_SUPPLY_PROP_STATUS:
++    axp_battery_check_status(charger, val);
++    break;
++  case POWER_SUPPLY_PROP_HEALTH:
++    axp_battery_check_health(charger, val);
++    break;
++  case POWER_SUPPLY_PROP_TECHNOLOGY:
++    val->intval = charger->battery_info->technology;
++    break;
++  case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
++    val->intval = charger->battery_info->voltage_max_design;
++    break;
++  case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
++    val->intval = charger->battery_info->voltage_min_design;
++    break;
++  case POWER_SUPPLY_PROP_VOLTAGE_NOW:
++    val->intval = charger->vbat * 1000;
++    break;
++  case POWER_SUPPLY_PROP_CURRENT_NOW:
++    val->intval = charger->ibat * 1000;
++    break;
++  case POWER_SUPPLY_PROP_MODEL_NAME:
++    val->strval = charger->batt->desc->name;
++    break;
++/*  case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
++  case POWER_SUPPLY_PROP_CHARGE_FULL:
++    val->intval = charger->battery_info->charge_full_design;
++        break;
++*/
++  case POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN:
++  case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
++    val->intval = charger->battery_info->energy_full_design;
++  //  DBG_PSY_MSG("POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN:%d\n",val->intval);
++       break;
++  case POWER_SUPPLY_PROP_CAPACITY:
++    val->intval = charger->rest_vol;
++    break;
++/*  case POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW:
++    if(charger->bat_det && !(charger->is_on) && !(charger->ext_valid))
++      val->intval = charger->rest_time;
++    else
++      val->intval = 0;
++    break;
++  case POWER_SUPPLY_PROP_TIME_TO_FULL_NOW:
++    if(charger->bat_det && charger->is_on)
++      val->intval = charger->rest_time;
++    else
++      val->intval = 0;
++    break;
++*/
++  case POWER_SUPPLY_PROP_ONLINE:
++  {
++    axp_charger_update_state(charger);
++    val->intval = charger->bat_current_direction;
++    printk(KERN_DEBUG "axp battery hardware current direction %d\n", charger->bat_current_direction);
++    if (charger->bat_temp > 50 || -5 < charger->bat_temp)
++			val->intval = 0;
++    break;
++  }
++  case POWER_SUPPLY_PROP_PRESENT:
++    val->intval = charger->bat_det;
++    break;
++ // case POWER_SUPPLY_PROP_TEMP:
++    //val->intval = charger->ic_temp - 200;
++    //val->intval =  300;
++//			val->intval =  charger->bat_temp * 10;
++
++//    break;
++  default:
++    printk(KERN_DEBUG "%s() psp=%x not handled\n", __func__, psp);
++    ret = -EINVAL;
++    break;
++  }
++
++  if(axp_debug)
++	  printk("%s() psp=%x propval->intval=%x\n", __func__, psp, val->intval);
++
++  return ret;
++}
++
++static int axp_ac_get_property(struct power_supply *psy,
++           enum power_supply_property psp,
++           union power_supply_propval *val)
++{
++  struct axp_charger *charger;
++  int ret = 0;
++  //charger = container_of(psy, struct axp_charger, ac);
++  charger = (struct axp_charger*)psy->drv_data;
++  //printk("%s() psp=%x\n", __func__, psp);
++
++  switch(psp){
++  case POWER_SUPPLY_PROP_MODEL_NAME:
++    val->strval = charger->ac->desc->name;break;
++  case POWER_SUPPLY_PROP_PRESENT:
++    val->intval = charger->ac_det;
++    break;
++  case POWER_SUPPLY_PROP_ONLINE:
++    val->intval = charger->ac_valid;break;
++  case POWER_SUPPLY_PROP_VOLTAGE_NOW:
++    val->intval = charger->vac * 1000;
++    break;
++  case POWER_SUPPLY_PROP_CURRENT_NOW:
++    val->intval = charger->iac * 1000;
++    break;
++  default:
++    ret = -EINVAL;
++    break;
++  }
++  printk(KERN_DEBUG "%s() psp=%x propval->intval=%x\n", __func__, psp, val->intval);
++   return ret;
++}
++
++static int axp_usb_get_property(struct power_supply *psy,
++           enum power_supply_property psp,
++           union power_supply_propval *val)
++{
++  struct axp_charger *charger;
++  int ret = 0;
++  //charger = container_of(psy, struct axp_charger, usb);
++  charger = (struct axp_charger*)psy->drv_data;
++  //printk("%s() psp=%x\n", __func__, psp);
++
++  switch(psp){
++  case POWER_SUPPLY_PROP_MODEL_NAME:
++    val->strval = charger->usb->desc->name;break;
++  case POWER_SUPPLY_PROP_PRESENT:
++    val->intval = charger->usb_det;
++    break;
++  case POWER_SUPPLY_PROP_ONLINE:
++    val->intval = charger->usb_valid;
++    break;
++  case POWER_SUPPLY_PROP_VOLTAGE_NOW:
++    val->intval = charger->vusb * 1000;
++    break;
++  case POWER_SUPPLY_PROP_CURRENT_NOW:
++    val->intval = charger->iusb * 1000;
++    break;
++  default:
++    ret = -EINVAL;
++    break;
++  }
++  printk(KERN_DEBUG "%s() psp=%x propval->intval=%x\n", __func__, psp, val->intval);
++   return ret;
++}
++
++static void axp_change(struct axp_charger *charger)
++{
++  uint8_t val,tmp;
++  int var;
++  DBG_PSY_MSG("battery state change\n");
++  axp_charger_update_state(charger);
++  axp_charger_update(charger);
++  printk(KERN_DEBUG "charger->usb_valid = %d\n",charger->usb_valid);
++	if(!charger->usb_valid){
++		printk(KERN_DEBUG "set usb vol-lim to %d mV, cur-lim to %d mA\n",USBVOLLIM,USBCURLIM);
++        //cancel_delayed_work_sync(&usbwork);
++		//reset usb-ac after usb removed
++		if((USBCURLIM) && (USBCURLIMEN)){
++			axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x01);
++			var = USBCURLIM * 1000;
++			if(var >= 900000)
++				axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x03);
++			else if ((var >= 500000)&& (var < 900000)){
++				axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x02);
++				axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x01);
++			}
++			else if ((var >= 100000)&& (var < 500000)){
++				axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x01);
++				axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x02);
++			}
++			else
++				printk(KERN_DEBUG "set usb limit current error,%d mA\n",USBCURLIM);
++		}
++		else
++			axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x03);
++
++		if((USBVOLLIM) && (USBVOLLIMEN)){
++			axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x40);
++			var = USBVOLLIM * 1000;
++			if(var >= 4000000 && var <=4700000){
++				tmp = (var - 4000000)/100000;
++			    axp_read(charger->master, AXP_CHARGE_VBUS,&val);
++			    val &= 0xC7;
++			    val |= tmp << 3;
++			    axp_write(charger->master, AXP_CHARGE_VBUS,val);
++			}
++			else
++				printk(KERN_DEBUG "set usb limit voltage error,%d mV\n",USBVOLLIM);
++		}
++		else
++			axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x40);
++	}
++  flag_state_change = 1;
++  power_supply_changed(charger->batt);
++}
++#ifdef AXP_INPUT_PWR_KEY
++static void axp_presslong(struct axp_charger *charger)
++{
++	DBG_PSY_MSG("press long\n");
++	input_report_key(powerkeydev, KEY_POWER, 1);
++	input_sync(powerkeydev);
++	ssleep(2);
++	DBG_PSY_MSG("press long up\n");
++	input_report_key(powerkeydev, KEY_POWER, 0);
++	input_sync(powerkeydev);
++}
++
++static void axp_pressshort(struct axp_charger *charger)
++{
++	DBG_PSY_MSG("press short\n");
++  	input_report_key(powerkeydev, KEY_POWER, 1);
++ 	input_sync(powerkeydev);
++ 	msleep(100);
++ 	input_report_key(powerkeydev, KEY_POWER, 0);
++ 	input_sync(powerkeydev);
++}
++
++static void axp_keyup(struct axp_charger *charger)
++{
++	DBG_PSY_MSG("power key up\n");
++	input_report_key(powerkeydev, KEY_POWER, 0);
++	input_sync(powerkeydev);
++}
++
++static void axp_keydown(struct axp_charger *charger)
++{
++	DBG_PSY_MSG("power key down\n");
++	input_report_key(powerkeydev, KEY_POWER, 1);
++	input_sync(powerkeydev);
++}
++#endif
++
++static void axp_capchange(struct axp_charger *charger)
++{
++    uint8_t val;
++    int k;
++
++    DBG_PSY_MSG("battery change\n");
++    ssleep(2);
++    axp_charger_update_state(charger);
++    axp_charger_update(charger);
++    axp_read(charger->master, AXP_CAP,&val);
++    charger->rest_vol = (int) (val & 0x7F);
++
++    if((charger->bat_det == 0) || (charger->rest_vol == 127)){
++  	charger->rest_vol = 100;
++  }
++
++  DBG_PSY_MSG("rest_vol = %d\n",charger->rest_vol);
++  memset(Bat_Cap_Buffer, 0, sizeof(Bat_Cap_Buffer));
++  for(k = 0;k < AXP_VOL_MAX; k++){
++    Bat_Cap_Buffer[k] = charger->rest_vol;
++  }
++  Total_Cap = charger->rest_vol * AXP_VOL_MAX;
++  power_supply_changed(charger->batt);
++}
++
++static int axp_battery_event(struct notifier_block *nb, unsigned long event,
++        void *data)
++{
++    struct axp_charger *charger =
++    container_of(nb, struct axp_charger, nb);
++
++    uint8_t w[9];
++	printk(KERN_DEBUG "[axp-sply] axp_battery_event !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
++	if(axp_debug){
++		DBG_PSY_MSG("axp_battery_event enter...\n");
++	}
++    if((bool)data==0){
++		if(axp_debug){
++    		DBG_PSY_MSG("low 32bit status...\n");
++		}
++			if(event & (AXP_IRQ_BATIN|AXP_IRQ_BATRE)) {
++				axp_capchange(charger);
++			}
++
++			if(event & (AXP_IRQ_BATINWORK|AXP_IRQ_BATOVWORK|AXP_IRQ_QBATINCHG|AXP_IRQ_BATINCHG
++						|AXP_IRQ_QBATOVCHG|AXP_IRQ_BATOVCHG)) {
++				axp_change(charger);
++			}
++
++			if(event & (AXP_IRQ_ACIN|AXP_IRQ_USBIN|AXP_IRQ_ACOV|AXP_IRQ_USBOV|AXP_IRQ_CHAOV
++						|AXP_IRQ_CHAST)) {
++				axp_change(charger);
++			}
++
++			if(event & (AXP_IRQ_ACRE|AXP_IRQ_USBRE)) {
++				axp_change(charger);
++			}
++#ifdef AXP_INPUT_PWR_KEY
++			if(event & AXP_IRQ_POKLO) {
++				axp_presslong(charger);
++			}
++
++			if(event & AXP_IRQ_POKSH) {
++				axp_pressshort(charger);
++			}
++#endif
++			w[0] = (uint8_t) ((event) & 0xFF);
++    		w[1] = AXP_INTSTS2;
++    		w[2] = (uint8_t) ((event >> 8) & 0xFF);
++    		w[3] = AXP_INTSTS3;
++    		w[4] = (uint8_t) ((event >> 16) & 0xFF);
++    		w[5] = AXP_INTSTS4;
++    		w[6] = (uint8_t) ((event >> 24) & 0xFF);
++    		w[7] = AXP_INTSTS5;
++    		w[8] = 0;
++	} else {
++#ifdef AXP_INPUT_PWR_KEY
++		if((event) & (AXP_IRQ_PEKFE>>32)) {
++			axp_keydown(charger);
++		}
++
++		if((event) & (AXP_IRQ_PEKRE>>32)) {
++			axp_keyup(charger);
++		}
++#endif
++		if(axp_debug){
++			DBG_PSY_MSG("high 32bit status...\n");
++		}
++		w[0] = 0;
++    	w[1] = AXP_INTSTS2;
++    	w[2] = 0;
++    	w[3] = AXP_INTSTS3;
++    	w[4] = 0;
++    	w[5] = AXP_INTSTS4;
++    	w[6] = 0;
++    	w[7] = AXP_INTSTS5;
++    	w[8] = (uint8_t) ((event) & 0xFF);;
++	}
++    DBG_PSY_MSG("event = 0x%x\n",(int) event);
++    axp_writes(charger->master,AXP_INTSTS1,9,w);
++
++    return 0;
++}
++
++static char *supply_list[] = {
++  "battery",
++};
++
++
++static const struct power_supply_desc batt_desc = {
++	.name = "battery",
++	.type = POWER_SUPPLY_TYPE_BATTERY,
++	.properties = axp_battery_props,
++	.num_properties = ARRAY_SIZE(axp_battery_props),
++	.get_property = axp_battery_get_property,
++};
++
++
++static const struct power_supply_desc ac_desc = {
++	.name = "ac",
++	.type = POWER_SUPPLY_TYPE_MAINS,
++	.properties = axp_ac_props,
++	.num_properties = ARRAY_SIZE(axp_ac_props),
++	.get_property = axp_ac_get_property,
++};
++
++
++static const struct power_supply_desc usb_desc = {
++	.name = "usb",
++	.type = POWER_SUPPLY_TYPE_USB,
++	.properties = axp_usb_props,
++	.num_properties = ARRAY_SIZE(axp_usb_props),
++	.get_property = axp_usb_get_property,
++};
++
++
++#if 0				/* deprecated... */
++static void axp_battery_setup_psy(struct axp_charger *charger)
++{
++  struct power_supply *batt = charger->batt;
++  struct power_supply *ac = charger->ac;
++  struct power_supply *usb = charger->usb;
++  struct power_supply_info *info = charger->battery_info;
++
++  batt->name = "battery";
++  batt->use_for_apm = info->use_for_apm;
++  batt->type = POWER_SUPPLY_TYPE_BATTERY;
++  batt->get_property = axp_battery_get_property;
++  printk("\n\n\nguojunbin add for battery setup 1111\n\n\n");
++  batt->properties = axp_battery_props;
++  batt->num_properties = ARRAY_SIZE(axp_battery_props);
++
++  ac->name = "ac";
++  ac->type = POWER_SUPPLY_TYPE_MAINS;
++  ac->get_property = axp_ac_get_property;
++  printk("\n\n\nguojunbin add for battery setup 2222\n\n\n");
++
++  ac->supplied_to = supply_list,
++  ac->num_supplicants = ARRAY_SIZE(supply_list),
++
++  ac->properties = axp_ac_props;
++  ac->num_properties = ARRAY_SIZE(axp_ac_props);
++
++  usb->name = "usb";
++  usb->type = POWER_SUPPLY_TYPE_USB;
++  usb->get_property = axp_usb_get_property;
++  printk("\n\n\nguojunbin add for battery setup 3333\n\n\n");
++  usb->supplied_to = supply_list,
++  usb->num_supplicants = ARRAY_SIZE(supply_list),
++
++  usb->properties = axp_usb_props;
++  usb->num_properties = ARRAY_SIZE(axp_usb_props);
++  printk("\n\n\nguojunbin add for battery setup 4444\n\n\n");
++
++};
++#endif
++
++#if defined  (CONFIG_AXP_CHARGEINIT)
++static int axp_battery_adc_set(struct axp_charger *charger)
++{
++   int ret ;
++   uint8_t val;
++
++  /*enable adc and set adc */
++  val= AXP_ADC_BATVOL_ENABLE | AXP_ADC_BATCUR_ENABLE;
++
++  ret = axp_update(charger->master, AXP_ADC_CONTROL, val , val);
++  if (ret)
++    return ret;
++  ret = axp_read(charger->master, AXP_ADC_CONTROL3, &val);
++  switch (charger->sample_time/100){
++  case 1: val &= ~(3 << 6);break;
++  case 2: val &= ~(3 << 6);val |= 1 << 6;break;
++  case 4: val &= ~(3 << 6);val |= 2 << 6;break;
++  case 8: val |= 3 << 6;break;
++  default: break;
++  }
++  ret = axp_write(charger->master, AXP_ADC_CONTROL3, val);
++  if (ret)
++    return ret;
++
++  return 0;
++}
++#else
++static int axp_battery_adc_set(struct axp_charger *charger)
++{
++  return 0;
++}
++#endif
++
++static int axp_battery_first_init(struct axp_charger *charger)
++{
++   int ret;
++   uint8_t val;
++   axp_set_charge(charger);
++   ret = axp_battery_adc_set(charger);
++   if(ret)
++    return ret;
++
++   ret = axp_read(charger->master, AXP_ADC_CONTROL3, &val);
++   switch ((val >> 6) & 0x03){
++  case 0: charger->sample_time = 100;break;
++  case 1: charger->sample_time = 200;break;
++  case 2: charger->sample_time = 400;break;
++  case 3: charger->sample_time = 800;break;
++  default:break;
++  }
++  return ret;
++}
++#if defined (CONFIG_AXP_DEBUG)
++static ssize_t chgen_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  uint8_t val;
++  axp_read(charger->master, AXP_CHARGE_CONTROL1, &val);
++  charger->chgen  = val >> 7;
++  return sprintf(buf, "%d\n",charger->chgen);
++}
++
++static ssize_t chgen_store(struct device *dev,
++        struct device_attribute *attr, const char *buf, size_t count)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  int var;
++  var = simple_strtoul(buf, NULL, 10);
++  if(var){
++    charger->chgen = 1;
++    axp_set_bits(charger->master,AXP_CHARGE_CONTROL1,0x80);
++  }
++  else{
++    charger->chgen = 0;
++    axp_clr_bits(charger->master,AXP_CHARGE_CONTROL1,0x80);
++  }
++  return count;
++}
++
++static ssize_t chgmicrovol_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  uint8_t val;
++  axp_read(charger->master, AXP_CHARGE_CONTROL1, &val);
++  switch ((val >> 5) & 0x03){
++    case 0: charger->chgvol = 4100000;break;
++    case 1: charger->chgvol = 4200000;break;
++    case 2: charger->chgvol = 4240000;break;
++    case 3: charger->chgvol = 4350000;break;
++  }
++  return sprintf(buf, "%d\n",charger->chgvol);
++}
++
++static ssize_t chgmicrovol_store(struct device *dev,
++        struct device_attribute *attr, const char *buf, size_t count)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  int var;
++  uint8_t tmp, val;
++  var = simple_strtoul(buf, NULL, 10);
++  switch(var){
++    case 4100000:tmp = 0;break;
++    case 4200000:tmp = 1;break;
++    case 4240000:tmp = 2;break;
++    case 4350000:tmp = 3;break;
++    default:  tmp = 4;break;
++  }
++  if(tmp < 4){
++    charger->chgvol = var;
++    axp_read(charger->master, AXP_CHARGE_CONTROL1, &val);
++    val &= 0x9F;
++    val |= tmp << 5;
++    axp_write(charger->master, AXP_CHARGE_CONTROL1, val);
++  }
++  return count;
++}
++
++static ssize_t chgintmicrocur_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  uint8_t val;
++  axp_read(charger->master, AXP_CHARGE_CONTROL1, &val);
++  charger->chgcur = (val & 0x0F) * 150000 +300000;
++  return sprintf(buf, "%d\n",charger->chgcur);
++}
++
++static ssize_t chgintmicrocur_store(struct device *dev,
++        struct device_attribute *attr, const char *buf, size_t count)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  int var;
++  uint8_t val,tmp;
++  var = simple_strtoul(buf, NULL, 10);
++  if(var >= 300000 && var <= 2550000){
++    tmp = (var -200001)/150000;
++    charger->chgcur = tmp *150000 + 300000;
++    axp_read(charger->master, AXP_CHARGE_CONTROL1, &val);
++    val &= 0xF0;
++    val |= tmp;
++    axp_write(charger->master, AXP_CHARGE_CONTROL1, val);
++  }
++  return count;
++}
++
++static ssize_t chgendcur_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  uint8_t val;
++  axp_read(charger->master, AXP_CHARGE_CONTROL1, &val);
++  charger->chgend = ((val >> 4)& 0x01)? 15 : 10;
++  return sprintf(buf, "%d\n",charger->chgend);
++}
++
++static ssize_t chgendcur_store(struct device *dev,
++        struct device_attribute *attr, const char *buf, size_t count)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  int var;
++  var = simple_strtoul(buf, NULL, 10);
++  if(var == 10 ){
++    charger->chgend = var;
++    axp_clr_bits(charger->master ,AXP_CHARGE_CONTROL1,0x10);
++  }
++  else if (var == 15){
++    charger->chgend = var;
++    axp_set_bits(charger->master ,AXP_CHARGE_CONTROL1,0x10);
++
++  }
++  return count;
++}
++
++static ssize_t chgpretimemin_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  uint8_t val;
++  axp_read(charger->master,AXP_CHARGE_CONTROL2, &val);
++  charger->chgpretime = (val >> 6) * 10 +40;
++  return sprintf(buf, "%d\n",charger->chgpretime);
++}
++
++static ssize_t chgpretimemin_store(struct device *dev,
++        struct device_attribute *attr, const char *buf, size_t count)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  int var;
++  uint8_t tmp,val;
++  var = simple_strtoul(buf, NULL, 10);
++  if(var >= 40 && var <= 70){
++    tmp = (var - 40)/10;
++    charger->chgpretime = tmp * 10 + 40;
++    axp_read(charger->master,AXP_CHARGE_CONTROL2,&val);
++    val &= 0x3F;
++    val |= (tmp << 6);
++    axp_write(charger->master,AXP_CHARGE_CONTROL2,val);
++  }
++  return count;
++}
++
++static ssize_t chgcsttimemin_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  uint8_t val;
++  axp_read(charger->master,AXP_CHARGE_CONTROL2, &val);
++  charger->chgcsttime = (val & 0x03) *120 + 360;
++  return sprintf(buf, "%d\n",charger->chgcsttime);
++}
++
++static ssize_t chgcsttimemin_store(struct device *dev,
++        struct device_attribute *attr, const char *buf, size_t count)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  int var;
++  uint8_t tmp,val;
++  var = simple_strtoul(buf, NULL, 10);
++  if(var >= 360 && var <= 720){
++    tmp = (var - 360)/120;
++    charger->chgcsttime = tmp * 120 + 360;
++    axp_read(charger->master,AXP_CHARGE_CONTROL2,&val);
++    val &= 0xFC;
++    val |= tmp;
++    axp_write(charger->master,AXP_CHARGE_CONTROL2,val);
++  }
++  return count;
++}
++
++static ssize_t adcfreq_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  uint8_t val;
++  axp_read(charger->master, AXP_ADC_CONTROL3, &val);
++  switch ((val >> 6) & 0x03){
++     case 0: charger->sample_time = 100;break;
++     case 1: charger->sample_time = 200;break;
++     case 2: charger->sample_time = 400;break;
++     case 3: charger->sample_time = 800;break;
++     default:break;
++  }
++  return sprintf(buf, "%d\n",charger->sample_time);
++}
++
++static ssize_t adcfreq_store(struct device *dev,
++        struct device_attribute *attr, const char *buf, size_t count)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  int var;
++  uint8_t val;
++  var = simple_strtoul(buf, NULL, 10);
++  axp_read(charger->master, AXP_ADC_CONTROL3, &val);
++  switch (var/25){
++    case 1: val &= ~(3 << 6);charger->sample_time = 100;break;
++    case 2: val &= ~(3 << 6);val |= 1 << 6;charger->sample_time = 200;break;
++    case 4: val &= ~(3 << 6);val |= 2 << 6;charger->sample_time = 400;break;
++    case 8: val |= 3 << 6;charger->sample_time = 800;break;
++    default: break;
++    }
++  axp_write(charger->master, AXP_ADC_CONTROL3, val);
++  return count;
++}
++
++
++static ssize_t vholden_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  uint8_t val;
++  axp_read(charger->master,AXP_CHARGE_VBUS, &val);
++  val = (val>>6) & 0x01;
++  return sprintf(buf, "%d\n",val);
++}
++
++static ssize_t vholden_store(struct device *dev,
++        struct device_attribute *attr, const char *buf, size_t count)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  int var;
++  var = simple_strtoul(buf, NULL, 10);
++  if(var)
++    axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x40);
++  else
++    axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x40);
++
++  return count;
++}
++
++static ssize_t vhold_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  uint8_t val;
++  int vhold;
++  axp_read(charger->master,AXP_CHARGE_VBUS, &val);
++  vhold = ((val >> 3) & 0x07) * 100000 + 4000000;
++  return sprintf(buf, "%d\n",vhold);
++}
++
++static ssize_t vhold_store(struct device *dev,
++        struct device_attribute *attr, const char *buf, size_t count)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  int var;
++  uint8_t val,tmp;
++  var = simple_strtoul(buf, NULL, 10);
++  if(var >= 4000000 && var <=4700000){
++    tmp = (var - 4000000)/100000;
++    //printk("tmp = 0x%x\n",tmp);
++    axp_read(charger->master, AXP_CHARGE_VBUS,&val);
++    val &= 0xC7;
++    val |= tmp << 3;
++    //printk("val = 0x%x\n",val);
++    axp_write(charger->master, AXP_CHARGE_VBUS,val);
++  }
++  return count;
++}
++
++static ssize_t iholden_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  uint8_t val;
++  axp_read(charger->master,AXP_CHARGE_VBUS, &val);
++  return sprintf(buf, "%d\n",((val & 0x03) == 0x03)?0:1);
++}
++
++static ssize_t iholden_store(struct device *dev,
++        struct device_attribute *attr, const char *buf, size_t count)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  int var;
++  var = simple_strtoul(buf, NULL, 10);
++  if(var)
++    axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x01);
++  else
++    axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x03);
++
++  return count;
++}
++
++static ssize_t ihold_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  uint8_t val,tmp;
++  int ihold;
++  axp_read(charger->master,AXP_CHARGE_VBUS, &val);
++  tmp = (val) & 0x03;
++  switch(tmp){
++    case 0: ihold = 900000;break;
++    case 1: ihold = 500000;break;
++    default: ihold = 0;break;
++  }
++  return sprintf(buf, "%d\n",ihold);
++}
++
++static ssize_t ihold_store(struct device *dev,
++        struct device_attribute *attr, const char *buf, size_t count)
++{
++  struct axp_charger *charger = dev_get_drvdata(dev);
++  int var;
++  var = simple_strtoul(buf, NULL, 10);
++  if(var == 900000)
++    axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x03);
++  else if (var == 500000){
++    axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x02);
++    axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x01);
++  }
++  return count;
++}
++static ssize_t acin_enable_show(struct device *dev,
++    struct device_attribute *attr, char *buf)
++{
++	struct axp_charger *charger = dev_get_drvdata(dev);
++	uint8_t val;
++
++	axp_read(charger->master,AXP_CHARGE3,&val);
++	val = (val) & 0x10;
++	if(val)
++		return 0;
++	else
++		return 1;
++}
++
++static ssize_t acin_enable_store(struct device *dev,
++        struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct axp_charger *charger = dev_get_drvdata(dev);
++	int var;
++	uint8_t val;
++
++	var = simple_strtoul(buf, NULL, 10);
++	axp_read(charger->master,AXP_CHARGE3,&val);
++	if(var) {
++		val &= ~(0x10);
++		axp_write(charger->master,AXP_CHARGE3,val);
++	}
++	else {
++		val |= 0x10;
++		axp_write(charger->master,AXP_CHARGE3,val);
++	}
++	return count;
++}
++
++static struct device_attribute axp_charger_attrs[] = {
++  AXP_CHG_ATTR(chgen),
++  AXP_CHG_ATTR(chgmicrovol),
++  AXP_CHG_ATTR(chgintmicrocur),
++  AXP_CHG_ATTR(chgendcur),
++  AXP_CHG_ATTR(chgpretimemin),
++  AXP_CHG_ATTR(chgcsttimemin),
++  AXP_CHG_ATTR(adcfreq),
++  AXP_CHG_ATTR(vholden),
++  AXP_CHG_ATTR(vhold),
++  AXP_CHG_ATTR(iholden),
++  AXP_CHG_ATTR(ihold),
++  AXP_CHG_ATTR(acin_enable),
++};
++#endif
++
++#if defined CONFIG_HAS_EARLYSUSPEND
++static void axp_earlysuspend(struct early_suspend *h)
++{
++	uint8_t tmp;
++	DBG_PSY_MSG("======early suspend=======\n");
++
++#if defined (CONFIG_AXP_CHGCHANGE)
++  	early_suspend_flag = 1;
++  	if(EARCHGCUR == 0)
++  		axp_clr_bits(axp_charger->master,AXP_CHARGE_CONTROL1,0x80);
++  	else
++  		axp_set_bits(axp_charger->master,AXP_CHARGE_CONTROL1,0x80);
++
++    if(EARCHGCUR >= 300000 && EARCHGCUR <= 2550000){
++    	tmp = (EARCHGCUR -200001)/150000;
++    	axp_update(axp_charger->master, AXP_CHARGE_CONTROL1, tmp,0x0F);
++    }
++#endif
++
++}
++static void axp_lateresume(struct early_suspend *h)
++{
++	uint8_t tmp;
++	DBG_PSY_MSG("======late resume=======\n");
++
++#if defined (CONFIG_AXP_CHGCHANGE)
++	early_suspend_flag = 0;
++	if(STACHGCUR == 0)
++  		axp_clr_bits(axp_charger->master,AXP_CHARGE_CONTROL1,0x80);
++  else
++  		axp_set_bits(axp_charger->master,AXP_CHARGE_CONTROL1,0x80);
++
++    if(STACHGCUR >= 300000 && STACHGCUR <= 2550000){
++        tmp = (STACHGCUR -200001)/150000;
++        axp_update(axp_charger->master, AXP_CHARGE_CONTROL1, tmp,0x0F);
++    }
++    else if(STACHGCUR < 300000){
++    	axp_clr_bits(axp_charger->master, AXP_CHARGE_CONTROL1,0x0F);
++    }
++    else{
++    	axp_set_bits(axp_charger->master, AXP_CHARGE_CONTROL1,0x0F);
++    }
++#endif
++
++}
++#endif
++
++#if defined (CONFIG_AXP_DEBUG)
++int axp_charger_create_attrs(struct power_supply *psy)
++{
++  int j,ret;
++  for (j = 0; j < ARRAY_SIZE(axp_charger_attrs); j++) {
++    ret = device_create_file(&psy->dev,
++          &axp_charger_attrs[j]);
++    if (ret)
++      goto sysfs_failed;
++  }
++    goto succeed;
++
++sysfs_failed:
++  while (j--)
++    device_remove_file(&psy->dev,
++         &axp_charger_attrs[j]);
++succeed:
++  return ret;
++}
++#endif
++#define MAX_PRINT_TIMES 3
++static void axp_charging_monitor(struct work_struct *work)
++{
++	struct axp_charger *charger;
++	uint8_t	val,temp_val[10];
++	int	pre_rest_vol,pre_bat_curr_dir;
++	uint8_t	batt_max_cap_val[3];	
++	int	batt_max_cap,coulumb_counter;
++  static int printtimes=0;
++  static bool bk_is_on = -1;
++  static bool bat_current_direction = -1;
++
++    printk("%s\n",__FUNCTION__);
++	charger = container_of(work, struct axp_charger, work.work);
++	pre_rest_vol = charger->rest_vol;
++	pre_bat_curr_dir = charger->bat_current_direction;
++	axp_charger_update_state(charger);
++	axp_charger_update(charger);
++
++	axp_read(charger->master, AXP_CAP,&val);
++	charger->rest_vol	= (int)	(val & 0x7F);
++
++		axp_reads(charger->master,0xe2,2,temp_val);	
++		coulumb_counter = (((temp_val[0] & 0x7f) <<8) + temp_val[1])*1456/1000;
++		axp_reads(charger->master,0xe0,2,temp_val);	
++		batt_max_cap = (((temp_val[0] & 0x7f) <<8) + temp_val[1])*1456/1000;
++		/* Avoid the power stay in 100% for a long time. */
++		if(coulumb_counter > batt_max_cap){		
++			batt_max_cap_val[0] = temp_val[0] | (0x1<<7);	
++			batt_max_cap_val[1] = 0xe3;		
++			batt_max_cap_val[2] = temp_val[1];		
++			axp_writes(charger->master, 0xe2,3,batt_max_cap_val);	
++			DBG_PSY_MSG("Axp22 coulumb_counter = %d\n",batt_max_cap);	
++
++		}
++			
++	if(axp_debug){
++		DBG_PSY_MSG("charger->ic_temp = %d\n",charger->ic_temp);
++		DBG_PSY_MSG("charger->vbat = %d\n",charger->vbat);
++		DBG_PSY_MSG("charger->ibat = %d\n",charger->ibat);
++		DBG_PSY_MSG("charger->ocv = %d\n",charger->ocv);
++		DBG_PSY_MSG("charger->disvbat = %d\n",charger->disvbat);
++		DBG_PSY_MSG("charger->disibat = %d\n",charger->disibat);
++		DBG_PSY_MSG("charger->rest_vol = %d\n",charger->rest_vol);
++		axp_reads(charger->master,0xba,2,temp_val);
++		DBG_PSY_MSG("AXP Rdc = %d\n",(((temp_val[0] & 0x1f) <<8) + temp_val[1])*10742/10000);
++		axp_reads(charger->master,0xe0,2,temp_val);
++		DBG_PSY_MSG("AXP batt_max_cap = %d\n",(((temp_val[0] & 0x7f) <<8) + temp_val[1])*1456/1000);
++		axp_reads(charger->master,0xe2,2,temp_val);
++		DBG_PSY_MSG("AXP coulumb_counter = %d\n",(((temp_val[0] & 0x7f) <<8) + temp_val[1])*1456/1000);
++		axp_read(charger->master,0xb8,temp_val);
++		DBG_PSY_MSG("AXP REG_B8 = %x\n",temp_val[0]);
++		axp_reads(charger->master,0xe4,2,temp_val);
++		DBG_PSY_MSG("AXP OCV_percentage = %d\n",(temp_val[0] & 0x7f));
++		DBG_PSY_MSG("AXP Coulumb_percentage = %d\n",(temp_val[1] & 0x7f));
++		DBG_PSY_MSG("charger->is_on = %d\n",charger->is_on);
++		DBG_PSY_MSG("charger->bat_current_direction = %d\n",charger->bat_current_direction);
++		DBG_PSY_MSG("charger->charge_on = %d\n",charger->charge_on);
++		DBG_PSY_MSG("charger->ext_valid = %d\n",charger->ext_valid);
++		DBG_PSY_MSG("pmu_runtime_chgcur           = %d\n",STACHGCUR);
++		DBG_PSY_MSG("pmu_earlysuspend_chgcur   = %d\n",EARCHGCUR);
++		DBG_PSY_MSG("pmu_suspend_chgcur        = %d\n",SUSCHGCUR);
++		DBG_PSY_MSG("pmu_shutdown_chgcur       = %d\n\n\n",CLSCHGCUR);
++//		axp_chip_id_get(chip_id);
++	}else{
++    if((printtimes == 0)|| (bk_is_on != charger->is_on) || (bat_current_direction!=charger->bat_current_direction)) {//clivia
++    axp_reads(charger->master,0xe0,2,temp_val);
++    axp_reads(charger->master,0xe2,2,&temp_val[2]);
++		axp_reads(charger->master,0xe2,2,&temp_val[4]);
++    axp_reads(charger->master,0xe4,2,&temp_val[6]);
++    axp_reads(charger->master,AXP_CHARGE_CONTROL1, 1, &temp_val[8]);
++    axp_reads(charger->master,AXP_CHARGE3, 1, &temp_val[9]);
++    
++    printk("charger->vbat=%d,ibat=%d ,Rdc=%d batt_max_cap=%d ,coulumb_counter=%d,OCV_percent=%d ,Coulumb_percent=%d ,is_on=%d ,bat_current_direction=%d \
++,charge_on=%d ,ext_valid=%d, pmu_runtime_chgcur=%d,pmu_suspend_chgcur=%d,0x33:%02x,0x35:%02x\n",
++      charger->vbat,charger->ibat,
++      (((temp_val[0] & 0x1f) <<8) + temp_val[1])*10742/10000 //Rdc
++      ,(((temp_val[2] & 0x7f) <<8) + temp_val[3])*1456/1000 //batt_max_cap
++      ,(((temp_val[4] & 0x7f) <<8) + temp_val[5])*1456/1000 //coulumb_counter
++      ,(temp_val[6] & 0x7f) ,(temp_val[7] & 0x7f)
++      ,charger->is_on
++      ,charger->bat_current_direction
++      ,charger->charge_on
++      ,charger->ext_valid
++      ,STACHGCUR
++      ,SUSCHGCUR
++      ,temp_val[8]
++      ,temp_val[9]
++      );
++    }
++    bk_is_on = charger->is_on;
++    bat_current_direction = charger->bat_current_direction;
++    printtimes = (printtimes+1) % MAX_PRINT_TIMES;
++	}
++
++	//for test usb detect
++#if DBG_AXP_PSY
++	val = axp_usb_det();
++	if(val)
++	{
++		printk("axp usb or usb adapter can be used!!\n");
++	}
++	else
++	{
++		printk("axp no usb or usb adaper!\n");
++	}
++#endif
++	/* if battery volume changed, inform uevent */
++	if((charger->rest_vol - pre_rest_vol) || (charger->bat_current_direction != pre_bat_curr_dir)){
++		if(axp_debug)
++			{
++				axp_reads(charger->master,0xe2,2,temp_val);
++				axp_reads(charger->master,0xe4,2,(temp_val+2));
++				printk("battery vol change: %d->%d \n", pre_rest_vol, charger->rest_vol);
++				printk("for test %d %d %d %d %d %d\n",charger->vbat,charger->ocv,charger->ibat,(temp_val[2] & 0x7f),(temp_val[3] & 0x7f),(((temp_val[0] & 0x7f) <<8) + temp_val[1])*1456/1000);
++			}
++		pre_rest_vol = charger->rest_vol;
++		power_supply_changed(charger->batt);
++	}
++	/* reschedule for the next time */
++	schedule_delayed_work(&charger->work, charger->interval);
++}
++
++static void axp_usb(struct work_struct *work)
++{
++	int var;
++	uint8_t tmp,val;
++	struct axp_charger *charger;
++
++	charger = axp_charger;
++	if(axp_debug)
++	{
++		printk("[axp_usb]axp_usbcurflag = %d\n",axp_usbcurflag);
++	}
++	if(axp_usbcurflag){
++		if(axp_debug)
++		{
++			printk("set usbcur_pc %d mA\n",USBCURLIMPC);
++		}
++		if(USBCURLIMPC){
++			axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x01);
++			var = USBCURLIMPC * 1000;
++			if(var >= 900000)
++				axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x03);
++			else if ((var >= 500000)&& (var < 900000)){
++				axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x02);
++				axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x01);
++			}
++			else{
++				printk("set usb limit current error,%d mA\n",USBCURLIMPC);
++			}
++		}
++		else//not limit
++			axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x03);
++	}else {
++		if(axp_debug)
++		{
++			printk("set usbcur %d mA\n",USBCURLIM);
++		}
++		if((USBCURLIM) && (USBCURLIMEN)){
++			axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x01);
++			var = USBCURLIM * 1000;
++			if(var >= 900000)
++				axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x03);
++			else if ((var >= 500000)&& (var < 900000)){
++				axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x02);
++				axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x01);
++			}
++			else
++				printk("set usb limit current error,%d mA\n",USBCURLIM);
++		}
++		else //not limit
++			axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x03);
++	}
++
++	if(axp_usbvolflag){
++		if(axp_debug)
++		{
++			printk("set usbvol_pc %d mV\n",USBVOLLIMPC);
++		}
++		if(USBVOLLIMPC){
++		    axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x40);
++		  	var = USBVOLLIMPC * 1000;
++		  	if(var >= 4000000 && var <=4700000){
++		    	tmp = (var - 4000000)/100000;
++		    	axp_read(charger->master, AXP_CHARGE_VBUS,&val);
++		    	val &= 0xC7;
++		    	val |= tmp << 3;
++		    	axp_write(charger->master, AXP_CHARGE_VBUS,val);
++		  	}
++		  	else
++		  		printk("set usb limit voltage error,%d mV\n",USBVOLLIMPC);
++		}
++		else
++		    axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x40);
++	}else {
++		if(axp_debug)
++		{
++			printk("set usbvol %d mV\n",USBVOLLIM);
++		}
++		if((USBVOLLIM) && (USBVOLLIMEN)){
++		    axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x40);
++		  	var = USBVOLLIM * 1000;
++		  	if(var >= 4000000 && var <=4700000){
++		    	tmp = (var - 4000000)/100000;
++		    	axp_read(charger->master, AXP_CHARGE_VBUS,&val);
++		    	val &= 0xC7;
++		    	val |= tmp << 3;
++		    	axp_write(charger->master, AXP_CHARGE_VBUS,val);
++		  	}
++		  	else
++		  		printk("set usb limit voltage error,%d mV\n",USBVOLLIM);
++		}
++		else
++		    axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x40);
++	}
++	schedule_delayed_work(&usbwork, msecs_to_jiffies(5* 1000));
++}
++
++static struct axp_supply_init_data *axp_thermistor_parse_dt(struct platform_device *pdev)
++{
++	struct device *dev = pdev->dev.parent;
++	struct device_node *np;
++	struct axp_supply_init_data *pdata;
++
++	np = of_get_child_by_name(dev->of_node,"supplyer");
++        dev->class = &axppower_class;
++
++	if (!np)
++		return NULL;
++
++	pdata = devm_kzalloc(&pdev->dev, sizeof(struct axp_supply_init_data), GFP_KERNEL);
++	if (!pdata)
++		return ERR_PTR(-ENOMEM);
++	pdata->battery_info = devm_kzalloc(&pdev->dev, sizeof(struct power_supply_info), GFP_KERNEL);
++	if (!pdata->battery_info)
++		return ERR_PTR(-ENOMEM);
++
++	if(of_property_read_string(np, "names", &pdata->battery_info->name))
++		return ERR_PTR(-ENODEV);
++	if (of_property_read_u32(np, "chgcur", &pdata->chgcur))
++		return ERR_PTR(-ENODEV);
++	if (of_property_read_u32(np, "chgvol", &pdata->chgvol))
++		return ERR_PTR(-ENODEV);
++printk("pmu of read chgvol=%d\n",pdata->chgvol);
++	if (of_property_read_u32(np, "chgend", &pdata->chgend))
++		return ERR_PTR(-ENODEV);
++	pdata->chgen = of_property_read_bool(np, "chgen");
++	if (of_property_read_u32(np, "sample_time", &pdata->sample_time))
++		return ERR_PTR(-ENODEV);
++	if (of_property_read_u32(np, "chgpretime", &pdata->chgpretime))
++		return ERR_PTR(-ENODEV);
++	if (of_property_read_u32(np, "chgcsttime", &pdata->chgcsttime))
++		return ERR_PTR(-ENODEV);
++	if (of_property_read_u32(np, "voltage_max_design", &pdata->battery_info->voltage_max_design))
++		return ERR_PTR(-ENODEV);
++	if (of_property_read_u32(np, "voltage_min_design", &pdata->battery_info->voltage_min_design))
++		return ERR_PTR(-ENODEV);
++	if (of_property_read_u32(np, "energy_full_design", &pdata->battery_info->energy_full_design))
++		return ERR_PTR(-ENODEV);
++	if (of_property_read_u32(np, "technology", &pdata->battery_info->technology))
++		return ERR_PTR(-ENODEV);
++	if (of_property_read_u32(np, "use_for_apm", &pdata->battery_info->use_for_apm))
++		return ERR_PTR(-ENODEV);
++
++	return pdata;
++}
++
++static int axp_battery_probe(struct platform_device *pdev)
++{
++	struct power_supply_config psy_cfg = {};
++  struct axp_charger *charger;
++  struct axp_supply_init_data *pdata;
++  int ret,var,tmp;
++  uint8_t val2,val;
++  uint8_t ocv_cap[63];
++  int Cur_CoulombCounter,rdc;
++
++
++  pdata = axp_thermistor_parse_dt(pdev);
++  if (IS_ERR(pdata))
++    return PTR_ERR(pdata);
++
++  if (pdata == NULL)
++    return -EINVAL;
++
++
++  if (!pdata) {
++    dev_err(&pdev->dev, "No platform init data supplied.\n");
++      return -ENODEV;
++  }
++#ifdef AXP_INPUT_PWR_KEY //del by clivia
++
++  powerkeydev = input_allocate_device();
++  if (!powerkeydev) {
++    kfree(powerkeydev);
++    return -ENODEV;
++  }
++
++  powerkeydev->name = pdev->name;
++  powerkeydev->phys = "m1kbd/input2";
++  powerkeydev->id.bustype = BUS_HOST;
++  powerkeydev->id.vendor = 0x0001;
++  powerkeydev->id.product = 0x0001;
++  powerkeydev->id.version = 0x0100;
++  powerkeydev->open = NULL;
++  powerkeydev->close = NULL;
++  powerkeydev->dev.parent = &pdev->dev;
++
++  set_bit(EV_KEY, powerkeydev->evbit);
++  set_bit(EV_REL, powerkeydev->evbit);
++  set_bit(EV_REP, powerkeydev->evbit);
++  set_bit(KEY_POWER, powerkeydev->keybit);
++
++  ret = input_register_device(powerkeydev);
++  if(ret) {
++    dev_err(&pdev->dev,"Unable to Register the power key\n");
++    }
++#else
++  powerkeydev = 0;
++#endif
++
++  if (pdata->chgcur > 2550000 ||
++      pdata->chgvol < 4100000 ||
++      pdata->chgvol > 4350000){
++        dev_err(&pdev->dev, "charger milliamp is too high or target voltage is over range\n");
++        return -EINVAL;
++    }
++
++  //printk("pmu chgcur=%d,chgvol=%d\n",pdata->chgcur, pdata->chgvol);
++  if (pdata->chgpretime < 40 || pdata->chgpretime >70 ||
++    pdata->chgcsttime < 360 || pdata->chgcsttime > 720){
++            dev_err(&pdev->dev, "prechaging time or constant current charging time is over range\n");
++        return -EINVAL;
++  }
++
++  charger = kzalloc(sizeof(*charger), GFP_KERNEL);
++  if (charger == NULL)
++    return -ENOMEM;
++
++  charger->master = pdev->dev.parent;
++
++  charger->chgcur      = pdata->chgcur;
++  charger->chgvol     = pdata->chgvol;
++  charger->chgend           = pdata->chgend;
++  charger->sample_time          = pdata->sample_time;
++  charger->chgen                   = pdata->chgen;
++  charger->chgpretime      = pdata->chgpretime;
++  charger->chgcsttime = pdata->chgcsttime;
++  charger->battery_info         = pdata->battery_info;
++  charger->disvbat			= 0;
++  charger->disibat			= 0;
++
++  ret = axp_battery_first_init(charger);
++  if (ret)
++    goto err_charger_init;
++
++//  printk("add axp_battery_event to notifier[%2x]\n", axp_battery_event);
++  charger->nb.notifier_call = axp_battery_event;
++  ret = axp_register_notifier(charger->master, &charger->nb, AXP_NOTIFIER_ON);
++  if (ret)
++    goto err_notifier;
++  //axp_battery_setup_psy(charger);
++  charger->batt = power_supply_register(&pdev->dev, &batt_desc, &psy_cfg);
++  if (IS_ERR(charger->batt)) {
++	  dev_err(&pdev->dev, "failed to register %s power supply\n",
++		  batt_desc.name);
++	  ret = PTR_ERR(charger->batt);
++	  goto err_ps_register;
++  }
++  dev_dbg(&pdev->dev, "%s() charger=%p, charger->batt=%p, &batt_desc=%p, charger->batt->desc=%p, drv_data=%p\n",
++	 __func__, charger, charger->batt, &batt_desc, charger->batt->desc, charger->batt->drv_data);
++  charger->batt->drv_data = (void *)charger;
++
++  psy_cfg.supplied_to = supply_list;
++  psy_cfg.num_supplicants = ARRAY_SIZE(supply_list);
++
++  axp_read(charger->master,AXP_CHARGE_STATUS,&val);
++  if(!((val >> 1) & 0x01)){
++	  charger->ac = power_supply_register(&pdev->dev, &ac_desc, &psy_cfg);
++	  if (IS_ERR(charger->ac)) {
++		  dev_err(&pdev->dev, "failed to register %s power supply\n",
++			  ac_desc.name);
++		  ret = PTR_ERR(charger->ac);
++		  power_supply_unregister(charger->batt);
++		  goto err_ps_register;
++	  }
++	  charger->ac->drv_data = (void *)charger;
++  }
++
++  charger->usb = power_supply_register(&pdev->dev, &usb_desc, &psy_cfg);
++  if (IS_ERR(charger->usb)) {
++	  dev_err(&pdev->dev, "failed to register %s power supply\n",
++		  usb_desc.name);
++	  ret = PTR_ERR(charger->usb);
++    power_supply_unregister(charger->ac);
++    power_supply_unregister(charger->batt);
++    goto err_ps_register;
++  }
++  charger->usb->drv_data = (void *)charger;
++#if defined (CONFIG_AXP_DEBUG)
++  ret = axp_charger_create_attrs(charger->batt);
++  if(ret){
++	dev_err(&pdev->dev, "cat notaxp_charger_create_attrs!!!===\n ");
++    return ret;
++  }
++#endif
++
++  platform_set_drvdata(pdev, charger);
++
++  /* usb voltage limit */
++  if((USBVOLLIM) && (USBVOLLIMEN)){
++    axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x40);
++  	var = USBVOLLIM * 1000;
++  	if(var >= 4000000 && var <=4700000){
++    	tmp = (var - 4000000)/100000;
++    	axp_read(charger->master, AXP_CHARGE_VBUS,&val);
++    	val &= 0xC7;
++    	val |= tmp << 3;
++    	axp_write(charger->master, AXP_CHARGE_VBUS,val);
++  	}
++  }
++  else
++    axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x40);
++
++	/*usb current limit*/
++  if((USBCURLIM) && (USBCURLIMEN)){
++    axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x02);
++    var = USBCURLIM * 1000;
++  	if(var == 900000)
++    	axp_clr_bits(charger->master, AXP_CHARGE_VBUS, 0x03);
++  	else if (var == 500000){
++    	axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x01);
++  	}
++  }
++  else
++    axp_set_bits(charger->master, AXP_CHARGE_VBUS, 0x03);
++
++
++  // set lowe power warning/shutdown level
++  axp_write(charger->master, AXP_WARNING_LEVEL,((BATLOWLV1-5) << 4)+BATLOWLV2);
++
++  ocv_cap[0]  = OCVREG0;
++  ocv_cap[1]  = 0xC1;
++  ocv_cap[2]  = OCVREG1;
++  ocv_cap[3]  = 0xC2;
++  ocv_cap[4]  = OCVREG2;
++  ocv_cap[5]  = 0xC3;
++  ocv_cap[6]  = OCVREG3;
++  ocv_cap[7]  = 0xC4;
++  ocv_cap[8]  = OCVREG4;
++  ocv_cap[9]  = 0xC5;
++  ocv_cap[10] = OCVREG5;
++  ocv_cap[11] = 0xC6;
++  ocv_cap[12] = OCVREG6;
++  ocv_cap[13] = 0xC7;
++  ocv_cap[14] = OCVREG7;
++  ocv_cap[15] = 0xC8;
++  ocv_cap[16] = OCVREG8;
++  ocv_cap[17] = 0xC9;
++  ocv_cap[18] = OCVREG9;
++  ocv_cap[19] = 0xCA;
++  ocv_cap[20] = OCVREGA;
++  ocv_cap[21] = 0xCB;
++  ocv_cap[22] = OCVREGB;
++  ocv_cap[23] = 0xCC;
++  ocv_cap[24] = OCVREGC;
++  ocv_cap[25] = 0xCD;
++  ocv_cap[26] = OCVREGD;
++  ocv_cap[27] = 0xCE;
++  ocv_cap[28] = OCVREGE;
++  ocv_cap[29] = 0xCF;
++  ocv_cap[30] = OCVREGF;
++  ocv_cap[31] = 0xD0;
++  ocv_cap[32] = OCVREG10;
++  ocv_cap[33] = 0xD1;
++  ocv_cap[34] = OCVREG11;
++  ocv_cap[35] = 0xD2;
++  ocv_cap[36] = OCVREG12;
++  ocv_cap[37] = 0xD3;
++  ocv_cap[38] = OCVREG13;
++  ocv_cap[39] = 0xD4;
++  ocv_cap[40] = OCVREG14;
++  ocv_cap[41] = 0xD5;
++  ocv_cap[42] = OCVREG15;
++  ocv_cap[43] = 0xD6;
++  ocv_cap[44] = OCVREG16;
++  ocv_cap[45] = 0xD7;
++  ocv_cap[46] = OCVREG17;
++  ocv_cap[47] = 0xD8;
++  ocv_cap[48] = OCVREG18;
++  ocv_cap[49] = 0xD9;
++  ocv_cap[50] = OCVREG19;
++  ocv_cap[51] = 0xDA;
++  ocv_cap[52] = OCVREG1A;
++  ocv_cap[53] = 0xDB;
++  ocv_cap[54] = OCVREG1B;
++  ocv_cap[55] = 0xDC;
++  ocv_cap[56] = OCVREG1C;
++  ocv_cap[57] = 0xDD;
++  ocv_cap[58] = OCVREG1D;
++  ocv_cap[59] = 0xDE;
++  ocv_cap[60] = OCVREG1E;
++  ocv_cap[61] = 0xDF;
++  ocv_cap[62] = OCVREG1F;
++  axp_writes(charger->master, 0xC0,31,ocv_cap);
++  axp_writes(charger->master, 0xD0,31,ocv_cap+32);
++	/* pok open time set */
++	axp_read(charger->master,AXP_POK_SET,&val);
++	if (PEKOPEN < 1000)
++		val &= 0x3f;
++	else if(PEKOPEN < 2000){
++		val &= 0x3f;
++		val |= 0x40;
++	}
++	else if(PEKOPEN < 3000){
++		val &= 0x3f;
++		val |= 0x80;
++	}
++	else {
++		val &= 0x3f;
++		val |= 0xc0;
++	}
++	axp_write(charger->master,AXP_POK_SET,val);
++
++	/* pok long time set*/
++	if(PEKLONG < 1000)
++		tmp = 1000;
++	else if(PEKLONG > 2500)
++		tmp = 2500;
++	else
++		tmp = PEKLONG;
++	axp_read(charger->master,AXP_POK_SET,&val);
++	val &= 0xcf;
++	val |= (((tmp - 1000) / 500) << 4);
++	axp_write(charger->master,AXP_POK_SET,val);
++
++	/* pek offlevel poweroff en set*/
++	if(PEKOFFEN)
++	{
++			tmp = 1;
++	}
++	else
++	{
++			tmp = 0;
++	}
++	axp_read(charger->master,AXP_POK_SET,&val);
++	val &= 0xf7;
++	val |= (tmp << 3);
++	axp_write(charger->master,AXP_POK_SET,val);
++
++	/*Init offlevel restart or not */
++	if(PEKOFFRESTART)
++	{
++			axp_set_bits(charger->master,AXP_POK_SET,0x04); //restart
++	}
++	else
++	{
++			axp_clr_bits(charger->master,AXP_POK_SET,0x04); //not restart
++	}
++
++	/* pek delay set */
++	axp_read(charger->master,AXP_OFF_CTL,&val);
++	val &= 0xfc;
++	val |= ((PEKDELAY / 8) - 1);
++	axp_write(charger->master,AXP_OFF_CTL,val);
++
++	/* pek offlevel time set */
++	if(PEKOFF < 4000)
++		tmp = 4000;
++	else if(PEKOFF > 10000)
++		tmp =10000;
++	else
++		tmp = PEKOFF;
++	tmp = (tmp - 4000) / 2000 ;
++	axp_read(charger->master,AXP_POK_SET,&val);
++	val &= 0xfc;
++	val |= tmp ;
++	axp_write(charger->master,AXP_POK_SET,val);
++	/*Init 16's Reset PMU en */
++	if(PMURESET)
++	{
++		axp_set_bits(charger->master,0x8F,0x08); //enable
++	}
++	else
++	{
++		axp_clr_bits(charger->master,0x8F,0x08); //disable
++	}
++
++	/*Init IRQ wakeup en*/
++	if(IRQWAKEUP)
++	{
++		axp_set_bits(charger->master,0x8F,0x80); //enable
++	}
++	else
++	{
++		axp_clr_bits(charger->master,0x8F,0x80); //disable
++	}
++
++	/*Init N_VBUSEN status*/
++	if(VBUSEN)
++	{
++		axp_set_bits(charger->master,0x8F,0x10); //output
++	}
++	else
++	{
++		axp_clr_bits(charger->master,0x8F,0x10); //input
++	}
++
++	/*Init InShort status*/
++	if(VBUSACINSHORT)
++	{
++		axp_set_bits(charger->master,0x8F,0x60); //InShort
++	}
++	else
++	{
++		axp_clr_bits(charger->master,0x8F,0x60); //auto detect
++	}
++
++	/*Init CHGLED function*/
++	if(CHGLEDFUN)
++	{
++		axp_set_bits(charger->master,0x32,0x08); //control by charger
++	}
++	else
++	{
++		axp_clr_bits(charger->master,0x32,0x08); //drive MOTO
++	}
++
++	/*set CHGLED Indication Type*/
++	if(CHGLEDTYPE)
++	{
++		axp_set_bits(charger->master,0x45,0x10); //Type A
++	}
++	else
++	{
++		axp_clr_bits(charger->master,0x45,0x10); //Type B
++	}
++
++	/*Init PMU Over Temperature protection*/
++	if(OTPOFFEN)
++	{
++		axp_set_bits(charger->master,0x8f,0x04); //enable
++	}
++	else
++	{
++		axp_clr_bits(charger->master,0x8f,0x04); //disable
++	}
++
++	/*Init battery capacity correct function*/
++	if(BATCAPCORRENT)
++	{
++		axp_set_bits(charger->master,0xb8,0x20); //enable
++	}
++	else
++	{
++		axp_clr_bits(charger->master,0xb8,0x20); //disable
++	}
++	/* Init battery regulator enable or not when charge finish*/
++	if(BATREGUEN)
++	{
++		axp_set_bits(charger->master,0x34,0x20); //enable
++	}
++	else
++	{
++		axp_clr_bits(charger->master,0x34,0x20); //disable
++	}
++
++	if(!BATDET)
++		axp_clr_bits(charger->master,AXP_PDBC,0x40);
++	else
++		axp_set_bits(charger->master,AXP_PDBC,0x40);
++
++
++/* RDC initial */
++	axp_read(charger->master, AXP_RDC0,&val2);
++	if((BATRDC) && (!(val2 & 0x40)))		//Èç¹ûÅäÖõç³ØÄÚ×裬ÔòÊÖ¶¯ÅäÖÃ
++	{
++		rdc = (BATRDC * 10000 + 5371) / 10742;
++		axp_write(charger->master, AXP_RDC0, ((rdc >> 8) & 0x1F)|0x80);
++		axp_write(charger->master,AXP_RDC1,rdc & 0x00FF);
++	}
++
++//probe ʱ³õʼ»¯RDC£¬Ê¹ÆäÌáÇ°¼ÆËãÕýÈ·µÄOCV£¬È»ºóÔÚ´Ë´¦Æô¶¯¼ÆÁ¿ÏµÍ³
++	axp_read(charger->master,AXP_BATCAP0,&val2);
++	if((BATCAP) && (!(val2 & 0x80)))
++	{
++		Cur_CoulombCounter = BATCAP * 1000 / 1456;
++		axp_write(charger->master, AXP_BATCAP0, ((Cur_CoulombCounter >> 8) | 0x80));
++		axp_write(charger->master,AXP_BATCAP1,Cur_CoulombCounter & 0x00FF);
++	}
++	else if(!BATCAP)
++	{
++		axp_write(charger->master, AXP_BATCAP0, 0x00);
++		axp_write(charger->master,AXP_BATCAP1,0x00);
++	}
++
++  axp_charger_update_state((struct axp_charger *)charger);
++
++  axp_read(charger->master, AXP_CAP,&val2);
++	charger->rest_vol = (int) (val2 & 0x7F);
++
++  charger->interval = msecs_to_jiffies(10 * 1000);
++  INIT_DELAYED_WORK(&charger->work, axp_charging_monitor);
++  schedule_delayed_work(&charger->work, charger->interval);
++
++  /* set usb cur-vol limit*/
++	INIT_DELAYED_WORK(&usbwork, axp_usb);
++	schedule_delayed_work(&usbwork, msecs_to_jiffies(7 * 1000));
++	/*¸ø¾Ö²¿±äÁ¿¸³Öµ*/
++	axp_charger = charger;
++#ifdef CONFIG_HAS_EARLYSUSPEND
++
++    axp_early_suspend.suspend = axp_earlysuspend;
++    axp_early_suspend.resume = axp_lateresume;
++    axp_early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 2;
++    register_early_suspend(&axp_early_suspend);
++#endif
++	/* µ÷ÊÔ½Ó¿Ú×¢²á */
++	class_register(&axppower_class);
++
++    return ret;
++
++err_ps_register:
++  axp_unregister_notifier(charger->master, &charger->nb, AXP_NOTIFIER_ON);
++
++err_notifier:
++  cancel_delayed_work_sync(&charger->work);
++
++err_charger_init:
++  kfree(charger);
++#ifdef AXP_INPUT_PWR_KEY //del by clivia
++
++  if(powerkeydev){
++	  input_unregister_device(powerkeydev);
++	  kfree(powerkeydev);
++  }
++#endif
++  return ret;
++}
++
++static int axp_battery_remove(struct platform_device *dev)
++{
++    struct axp_charger *charger = platform_get_drvdata(dev);
++
++    if(main_task){
++        kthread_stop(main_task);
++        main_task = NULL;
++    }
++
++    axp_unregister_notifier(charger->master, &charger->nb, AXP_NOTIFIER_ON);
++    cancel_delayed_work_sync(&charger->work);
++    power_supply_unregister(charger->usb);
++    power_supply_unregister(charger->ac);
++    power_supply_unregister(charger->batt);
++
++    kfree(charger);
++#ifdef AXP_INPUT_PWR_KEY //del by clivia
++    if(powerkeydev){
++    input_unregister_device(powerkeydev);
++    kfree(powerkeydev);
++	}
++#endif
++    return 0;
++}
++
++
++static int axp_suspend(struct platform_device *dev, pm_message_t state)
++{
++    uint8_t irq_w[9];
++    uint8_t tmp;
++
++    struct axp_charger *charger = platform_get_drvdata(dev);
++
++    cancel_delayed_work_sync(&charger->work);
++    cancel_delayed_work_sync(&usbwork);
++
++    /*clear all irqs events*/
++    irq_w[0] = 0xff;
++    irq_w[1] = AXP_INTSTS2;
++    irq_w[2] = 0xff;
++    irq_w[3] = AXP_INTSTS3;
++    irq_w[4] = 0xff;
++    irq_w[5] = AXP_INTSTS4;
++    irq_w[6] = 0xff;
++    irq_w[7] = AXP_INTSTS5;
++    irq_w[8] = 0xff;
++    axp_writes(charger->master, AXP_INTSTS1, 9, irq_w);
++    /* unregister notifier */
++    //axp_unregister_notifier(charger->master, &charger->nb, 0);
++    enable_irq_wake(AXP_IRQNO);
++
++#if defined (CONFIG_AXP_CHGCHANGE)
++    if(SUSCHGCUR == 0)
++        axp_clr_bits(charger->master,AXP_CHARGE_CONTROL1,0x80);
++    else
++        axp_set_bits(charger->master,AXP_CHARGE_CONTROL1,0x80);
++
++    if(SUSCHGCUR >= 300000 && SUSCHGCUR <= 2550000){
++        tmp = (SUSCHGCUR -200001)/150000;
++        charger->chgcur = tmp *150000 + 300000;
++        axp_update(charger->master, AXP_CHARGE_CONTROL1, tmp,0x0F);
++    }
++#endif
++
++    return 0;
++}
++
++static int axp_resume(struct platform_device *dev)
++{
++    struct axp_charger *charger = platform_get_drvdata(dev);
++
++    int pre_rest_vol;
++    uint8_t val,tmp;
++    /*wakeup IQR notifier work sequence*/
++    //axp_register_notifier(charger->master, &charger->nb, AXP_NOTIFIER_ON);
++    disable_irq_wake(AXP_IRQNO);
++    axp_charger_update_state(charger);
++
++    pre_rest_vol = charger->rest_vol;
++
++    axp_read(charger->master, AXP_CAP,&val);
++    charger->rest_vol = val & 0x7f;
++
++    if(charger->rest_vol - pre_rest_vol){
++    	printk("battery vol change: %d->%d \n", pre_rest_vol, charger->rest_vol);
++    	pre_rest_vol = charger->rest_vol;
++    	axp_write(charger->master,AXP_DATA_BUFFER1,charger->rest_vol | 0x80);
++    	power_supply_changed(charger->batt);
++    }
++
++#if defined (CONFIG_AXP_CHGCHANGE)
++    if(STACHGCUR == 0)
++    	axp_clr_bits(charger->master,AXP_CHARGE_CONTROL1,0x80);
++    else
++    	axp_set_bits(charger->master,AXP_CHARGE_CONTROL1,0x80);
++
++    printk("pmu_runtime_chgcur = %d\n", STACHGCUR);
++
++    if(STACHGCUR >= 300000 && STACHGCUR <= 2550000){
++        tmp = (STACHGCUR -200001)/150000;
++        charger->chgcur = tmp *150000 + 300000;
++        axp_update(charger->master, AXP_CHARGE_CONTROL1, tmp,0x0F);
++    }else if(STACHGCUR < 300000){
++    	axp_clr_bits(axp_charger->master, AXP_CHARGE_CONTROL1,0x0F);
++    }
++    else{
++    	axp_set_bits(axp_charger->master, AXP_CHARGE_CONTROL1,0x0F);
++    }
++#endif
++
++    charger->disvbat = 0;
++    charger->disibat = 0;
++    schedule_delayed_work(&charger->work, charger->interval);
++    schedule_delayed_work(&usbwork, msecs_to_jiffies(7 * 1000));
++
++    return 0;
++}
++
++static void axp_shutdown(struct platform_device *dev)
++{
++    uint8_t tmp;
++    struct axp_charger *charger = platform_get_drvdata(dev);
++
++    cancel_delayed_work_sync(&charger->work);
++
++#if defined (CONFIG_AXP_CHGCHANGE)
++    if(CLSCHGCUR == 0)
++        axp_clr_bits(charger->master,AXP_CHARGE_CONTROL1,0x80);
++    else
++        axp_set_bits(charger->master,AXP_CHARGE_CONTROL1,0x80);
++
++    printk("pmu_shutdown_chgcur = %d\n", CLSCHGCUR);
++
++    if(CLSCHGCUR >= 300000 && CLSCHGCUR <= 2550000){
++    	tmp = (CLSCHGCUR -200001)/150000;
++    	charger->chgcur = tmp *150000 + 300000;
++    	axp_update(charger->master, AXP_CHARGE_CONTROL1, tmp, 0x0F);
++    }
++#endif
++}
++
++static struct platform_driver axp_battery_driver = {
++  .driver = {
++    .name = "axp216-supplyer",
++    .owner  = THIS_MODULE,
++  },
++  .probe = axp_battery_probe,
++  .remove = axp_battery_remove,
++  .suspend = axp_suspend,
++  .resume = axp_resume,
++  .shutdown = axp_shutdown,
++};
++
++static int axp_battery_init(void)
++{
++    int ret =0;
++    ret = platform_driver_register(&axp_battery_driver);
++    return ret;
++}
++
++static void axp_battery_exit(void)
++{
++    platform_driver_unregister(&axp_battery_driver);
++}
++
++subsys_initcall(axp_battery_init);
++module_exit(axp_battery_exit);
++
++MODULE_DESCRIPTION("AXP battery charger driver");
++MODULE_AUTHOR("Weijin Zhong");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/power/supply/axp_power/axp-sply.h b/module_drivers/drivers/power/supply/axp_power/axp-sply.h
+new file mode 100644
+index 000000000..888971456
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/axp-sply.h
+@@ -0,0 +1,180 @@
++#ifndef	_LINUX_AXP_SPLY_H_
++#define	_LINUX_AXP_SPLY_H_
++
++static 	struct input_dev * powerkeydev;
++
++/*      AXP      */
++#define AXP_CHARGE_STATUS		AXP_STATUS
++#define AXP_IN_CHARGE			(1 << 6)
++#define AXP_PDBC			(0x32)
++#define AXP_CHARGE_CONTROL1		AXP_CHARGE1
++#define AXP_CHARGER_ENABLE		(1 << 7)
++#define AXP_CHARGE_CONTROL2		AXP_CHARGE2
++#define AXP_CHARGE_VBUS		AXP_IPS_SET
++#define AXP_CAP			(0xB9)
++#define AXP_BATCAP0			(0xe0)
++#define AXP_BATCAP1			(0xe1)
++#define AXP_RDC0			(0xba)
++#define AXP_RDC1			(0xbb)
++#define AXP_WARNING_LEVEL		(0xe6)
++#define AXP_ADJUST_PARA		(0xe8)
++#define AXP_FAULT_LOG1		AXP_MODE_CHGSTATUS
++#define AXP_FAULT_LOG_CHA_CUR_LOW	(1 << 2)
++#define AXP_FAULT_LOG_BATINACT	(1 << 3)
++#define AXP_FAULT_LOG_OVER_TEMP	(1 << 7)
++#define AXP_FAULT_LOG2		AXP_INTSTS2
++#define AXP_FAULT_LOG_COLD		(1 << 0)
++#define AXP_FINISH_CHARGE		(1 << 2)
++#define AXP_COULOMB_CONTROL		AXP_COULOMB_CTL
++#define AXP_COULOMB_ENABLE		(1 << 7)
++#define AXP_COULOMB_SUSPEND		(1 << 6)
++#define AXP_COULOMB_CLEAR		(1 << 5)
++
++#define AXP_ADC_CONTROL				AXP_ADC_EN
++#define AXP_ADC_BATVOL_ENABLE				(1 << 7)
++#define AXP_ADC_BATCUR_ENABLE				(1 << 6)
++#define AXP_ADC_DCINVOL_ENABLE			(1 << 5)
++#define AXP_ADC_DCINCUR_ENABLE			(1 << 4)
++#define AXP_ADC_USBVOL_ENABLE				(1 << 3)
++#define AXP_ADC_USBCUR_ENABLE				(1 << 2)
++#define AXP_ADC_APSVOL_ENABLE				(1 << 1)
++#define AXP_ADC_TSVOL_ENABLE				(1 << 0)
++#define AXP_ADC_INTERTEM_ENABLE			(1 << 7)
++#define AXP_ADC_GPIO0_ENABLE				(1 << 3)
++#define AXP_ADC_GPIO1_ENABLE				(1 << 2)
++#define AXP_ADC_GPIO2_ENABLE				(1 << 1)
++#define AXP_ADC_GPIO3_ENABLE				(1 << 0)
++#define AXP_ADC_CONTROL3				(0x84)
++#define AXP_VBATH_RES					(0x78)
++#define AXP_VTS_RES					(0x58)
++#define AXP_VBATL_RES					(0x79)
++#define AXP_OCVBATH_RES				(0xBC)
++#define AXP_OCVBATL_RES				(0xBD)
++#define AXP_INTTEMP					(0x56)
++#define AXP_DATA_BUFFER0				AXP_BUFFER1
++#define AXP_DATA_BUFFER1				AXP_BUFFER2
++#define AXP_DATA_BUFFER2				AXP_BUFFER3
++#define AXP_DATA_BUFFER3				AXP_BUFFER4
++#define AXP_DATA_BUFFER4				AXP_BUFFER5
++#define AXP_DATA_BUFFER5				AXP_BUFFER6
++#define AXP_DATA_BUFFER6				AXP_BUFFER7
++#define AXP_DATA_BUFFER7				AXP_BUFFER8
++#define AXP_DATA_BUFFER8				AXP_BUFFER9
++#define AXP_DATA_BUFFER9				AXP_BUFFERA
++#define AXP_DATA_BUFFERA				AXP_BUFFERB
++#define AXP_DATA_BUFFERB				AXP_BUFFERC
++
++
++#define AXP_CHG_ATTR(_name)					\
++{								\
++	.attr = { .name = #_name,.mode = 0644 },		\
++	.show =  _name##_show,					\
++	.store = _name##_store,					\
++}
++
++struct axp_adc_res {//struct change
++	uint16_t vbat_res;
++	uint16_t ocvbat_res;
++	uint16_t ibat_res;
++	uint16_t ichar_res;
++	uint16_t idischar_res;
++	uint16_t vac_res;
++	uint16_t iac_res;
++	uint16_t vusb_res;
++	uint16_t iusb_res;
++	uint16_t ts_res;
++};
++
++struct axp_charger {
++	/*power supply sysfs*/
++	struct power_supply *batt;
++	struct power_supply *	ac;
++	struct power_supply *	usb;
++	struct power_supply *bubatt;
++
++	/*i2c device*/
++	struct device *master;
++
++	/* adc */
++	struct axp_adc_res *adc;
++	unsigned int sample_time;
++
++	/*monitor*/
++	struct delayed_work work;
++	unsigned int interval;
++
++	/*battery info*/
++	struct power_supply_info *battery_info;
++
++	/*charger control*/
++	bool chgen;
++	bool limit_on;
++	unsigned int chgcur;
++	unsigned int chgvol;
++	unsigned int chgend;
++
++	/*charger time */
++	int chgpretime;
++	int chgcsttime;
++
++	/*external charger*/
++	bool chgexten;
++	int chgextcur;
++
++	/* charger status */
++	bool bat_det;
++	bool is_on;
++	bool is_finish;
++	bool ac_not_enough;
++	bool ac_det;
++	bool usb_det;
++	bool ac_valid;
++	bool usb_valid;
++	bool ext_valid;
++	bool bat_current_direction;
++	bool in_short;
++	bool batery_active;
++	bool low_charge_current;
++	bool int_over_temp;
++	uint8_t fault;
++	int charge_on;
++
++	int vbat;
++	int ibat;
++	int pbat;
++	int vac;
++	int iac;
++	int vusb;
++	int iusb;
++	int ocv;
++
++	int disvbat;
++	int disibat;
++
++	/*rest time*/
++	int rest_vol;
++	int ocv_rest_vol;
++	int base_restvol;
++	int rest_time;
++
++	/*ic temperature*/
++	int ic_temp;
++	int bat_temp;
++
++	/*irq*/
++	struct notifier_block nb;
++
++	/* platform callbacks for battery low and critical events */
++	void (*battery_low)(void);
++	void (*battery_critical)(void);
++
++	struct dentry *debug_file;
++};
++
++static struct task_struct *main_task;
++static struct axp_charger *axp_charger;
++static int Total_Cap = 0;
++static int flag_state_change = 0;
++static int Bat_Cap_Buffer[AXP_VOL_MAX];
++
++#endif
+diff --git a/module_drivers/drivers/power/supply/axp_power/axp-state.c b/module_drivers/drivers/power/supply/axp_power/axp-state.c
+new file mode 100644
+index 000000000..2b3f075bb
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/axp-state.c
+@@ -0,0 +1,197 @@
++/*
++ * Battery charger driver for X-POWERS AXP28X
++ *
++ * Copyright (C) 2014 X-POWERS Ltd.
++ *  Ming Li <liming@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include "axp-cfg.h"
++
++struct axp_adc_res adc;
++
++static inline int axp_vts_to_temp(int data, const struct axp_config_info *axp_config)
++{
++	 int temp;
++	 if (data < 80)
++		 return 30;
++	 else if (data < axp_config->pmu_temp_para16)
++		 return 80;
++	 else if (data <= axp_config->pmu_temp_para15) {
++		 temp = 70 + (axp_config->pmu_temp_para15-data)*10/(axp_config->pmu_temp_para15-axp_config->pmu_temp_para16);
++	 } else if (data <= axp_config->pmu_temp_para14) {
++		 temp = 60 + (axp_config->pmu_temp_para14-data)*10/(axp_config->pmu_temp_para14-axp_config->pmu_temp_para15);
++	 } else if (data <= axp_config->pmu_temp_para13) {
++		 temp = 55 + (axp_config->pmu_temp_para13-data)*5/(axp_config->pmu_temp_para13-axp_config->pmu_temp_para14);
++	 } else if (data <= axp_config->pmu_temp_para12) {
++		 temp = 50 + (axp_config->pmu_temp_para12-data)*5/(axp_config->pmu_temp_para12-axp_config->pmu_temp_para13);
++	 } else if (data <= axp_config->pmu_temp_para11) {
++		 temp = 45 + (axp_config->pmu_temp_para11-data)*5/(axp_config->pmu_temp_para11-axp_config->pmu_temp_para12);
++	 } else if (data <= axp_config->pmu_temp_para10) {
++		 temp = 40 + (axp_config->pmu_temp_para10-data)*5/(axp_config->pmu_temp_para10-axp_config->pmu_temp_para11);
++	 } else if (data <= axp_config->pmu_temp_para9) {
++		 temp = 30 + (axp_config->pmu_temp_para9-data)*10/(axp_config->pmu_temp_para9-axp_config->pmu_temp_para10);
++	 } else if (data <= axp_config->pmu_temp_para8) {
++		 temp = 20 + (axp_config->pmu_temp_para8-data)*10/(axp_config->pmu_temp_para8-axp_config->pmu_temp_para9);
++	 } else if (data <= axp_config->pmu_temp_para7) {
++		 temp = 10 + (axp_config->pmu_temp_para7-data)*10/(axp_config->pmu_temp_para7-axp_config->pmu_temp_para8);
++	 } else if (data <= axp_config->pmu_temp_para6) {
++		 temp = 5 + (axp_config->pmu_temp_para6-data)*5/(axp_config->pmu_temp_para6-axp_config->pmu_temp_para7);
++	 } else if (data <= axp_config->pmu_temp_para5) {
++		 temp = 0 + (axp_config->pmu_temp_para5-data)*5/(axp_config->pmu_temp_para5-axp_config->pmu_temp_para6);
++	 } else if (data <= axp_config->pmu_temp_para4) {
++		 temp = -5 + (axp_config->pmu_temp_para4-data)*5/(axp_config->pmu_temp_para4-axp_config->pmu_temp_para5);
++	 } else if (data <= axp_config->pmu_temp_para3) {
++		 temp = -10 + (axp_config->pmu_temp_para3-data)*5/(axp_config->pmu_temp_para3-axp_config->pmu_temp_para4);
++	 } else if (data <= axp_config->pmu_temp_para2) {
++		 temp = -15 + (axp_config->pmu_temp_para2-data)*5/(axp_config->pmu_temp_para2-axp_config->pmu_temp_para3);
++	 } else if (data <= axp_config->pmu_temp_para1) {
++		 temp = -25 + (axp_config->pmu_temp_para1-data)*10/(axp_config->pmu_temp_para1-axp_config->pmu_temp_para2);
++	 } else
++		 temp = -25;
++    return temp;
++}
++
++static inline int axp_vts_to_mV(uint16_t reg)
++{
++    return ((int)(((reg >> 8) << 4 ) | (reg & 0x000F))) * 800 / 1000;
++}
++
++static inline int axp_vbat_to_mV(uint16_t reg)
++{
++	 return ((int)((( reg >> 8) << 4 ) | (reg & 0x000F))) * 1100 / 1000;
++}
++
++static inline int axp_ocvbat_to_mV(uint16_t reg)
++{
++	 return ((int)((( reg >> 8) << 4 ) | (reg & 0x000F))) * 1100 / 1000;
++}
++
++
++static inline int axp_vdc_to_mV(uint16_t reg)
++{
++	 return ((int)(((reg >> 8) << 4 ) | (reg & 0x000F))) * 1700 / 1000;
++}
++
++
++static inline int axp_ibat_to_mA(uint16_t reg)
++{
++	 return ((int)(((reg >> 8) << 4 ) | (reg & 0x000F))) ;
++}
++
++static inline int axp_icharge_to_mA(uint16_t reg)
++{
++	 return ((int)(((reg >> 8) << 4 ) | (reg & 0x000F)));
++}
++
++static inline int axp_iac_to_mA(uint16_t reg)
++{
++	 return ((int)(((reg >> 8) << 4 ) | (reg & 0x000F))) * 625 / 1000;
++}
++
++static inline int axp_iusb_to_mA(uint16_t reg)
++{
++	 return ((int)(((reg >> 8) << 4 ) | (reg & 0x000F))) * 375 / 1000;
++}
++
++
++static inline void axp_read_adc(struct axp_charger *charger,
++  struct axp_adc_res *adc)
++{
++	 uint8_t tmp[8];
++	 adc->vac_res = 0;
++	 adc->iac_res = 0;
++	 adc->vusb_res = 0;
++	 adc->iusb_res = 0;
++
++	 axp_reads(charger->master,AXP_VBATH_RES,6,tmp);
++	 adc->vbat_res = ((uint16_t) tmp[0] << 8 )| tmp[1];
++	 adc->ichar_res = ((uint16_t) tmp[2] << 8 )| tmp[3];
++	 adc->idischar_res = ((uint16_t) tmp[4] << 8 )| tmp[5];
++	 axp_reads(charger->master,AXP_OCVBATH_RES,2,tmp);
++	 adc->ocvbat_res = ((uint16_t) tmp[0] << 8 )| tmp[1];
++	 axp_reads(charger->master,AXP_VTS_RES,2,tmp);
++	 adc->ts_res = ((uint16_t) tmp[0] << 8 )| tmp[1];
++}
++
++
++void axp_charger_update_state(struct axp_charger *charger)
++{
++	 uint8_t val[2];
++	 uint16_t tmp;
++	 
++	 axp_reads(charger->master,AXP_CHARGE_STATUS,2,val);
++	 tmp = (val[1] << 8 )+ val[0];
++	 spin_lock(&charger->charger_lock);
++	 charger->is_on = (val[1] & AXP_IN_CHARGE) ? 1 : 0;
++	 charger->fault = val[1];
++	 charger->bat_det = (tmp & AXP_STATUS_BATEN)?1:0;
++	 charger->ac_det = (tmp & AXP_STATUS_ACEN)?1:0;
++	 charger->usb_det = (tmp & AXP_STATUS_USBEN)?1:0;
++	 charger->usb_valid = (tmp & AXP_STATUS_USBVA)?1:0;
++	 charger->ac_valid = (tmp & AXP_STATUS_ACVA)?1:0;
++	 charger->ext_valid = charger->ac_valid | charger->usb_valid;
++	 charger->bat_current_direction = (tmp & AXP_STATUS_BATCURDIR)?1:0;
++	 charger->in_short = (tmp& AXP_STATUS_ACUSBSH)?1:0;
++	 charger->batery_active = (tmp & AXP_STATUS_BATINACT)?1:0;
++	 charger->int_over_temp = (tmp & AXP_STATUS_ICTEMOV)?1:0;
++	 spin_unlock(&charger->charger_lock);
++	 axp_read(charger->master,AXP_CHARGE_CONTROL1,val);
++	 spin_lock(&charger->charger_lock);
++	 charger->charge_on = ((val[0] >> 7) & 0x01);
++	 spin_unlock(&charger->charger_lock);
++}
++
++void axp_charger_update(struct axp_charger *charger, const struct axp_config_info *axp_config)
++{
++	uint16_t tmp;
++	uint8_t val[2];
++	int bat_temp_mv;
++
++	charger->adc = &adc;
++	axp_read_adc(charger, &adc);
++	tmp = charger->adc->vbat_res;
++
++	spin_lock(&charger->charger_lock);
++	charger->vbat = axp_vbat_to_mV(tmp);
++	spin_unlock(&charger->charger_lock);
++
++	tmp = charger->adc->ocvbat_res;
++
++	spin_lock(&charger->charger_lock);
++	charger->ocv = axp_ocvbat_to_mV(tmp);
++	spin_unlock(&charger->charger_lock);
++
++	//tmp = charger->adc->ichar_res + charger->adc->idischar_res;
++	spin_lock(&charger->charger_lock);
++	charger->ibat = ABS(axp_icharge_to_mA(charger->adc->ichar_res)-axp_ibat_to_mA(charger->adc->idischar_res));
++	tmp = 00;
++	charger->vac = axp_vdc_to_mV(tmp);
++	tmp = 00;
++	charger->iac = axp_iac_to_mA(tmp);
++	tmp = 00;
++	charger->vusb = axp_vdc_to_mV(tmp);
++	tmp = 00;
++	charger->iusb = axp_iusb_to_mA(tmp);
++	spin_unlock(&charger->charger_lock);
++
++	axp_reads(charger->master,AXP_INTTEMP,2,val);
++	//DBG_PSY_MSG("TEMPERATURE:val1=0x%x,val2=0x%x\n",val[1],val[0]);
++	tmp = (val[0] << 4 ) + (val[1] & 0x0F);
++
++	spin_lock(&charger->charger_lock);
++	charger->ic_temp = (int) tmp *1063/10000  - 2667/10;
++	charger->disvbat =  charger->vbat;
++	charger->disibat =  axp_ibat_to_mA(charger->adc->idischar_res);
++	spin_unlock(&charger->charger_lock);
++	
++	tmp = charger->adc->ts_res;
++	bat_temp_mv = axp_vts_to_mV(tmp);
++	
++	spin_lock(&charger->charger_lock);
++	charger->bat_temp = axp_vts_to_temp(bat_temp_mv, axp_config);
++	spin_unlock(&charger->charger_lock);
++}
++
+diff --git a/module_drivers/drivers/power/supply/axp_power/axp216-mfd.h b/module_drivers/drivers/power/supply/axp_power/axp216-mfd.h
+new file mode 100644
+index 000000000..02c956a61
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/axp216-mfd.h
+@@ -0,0 +1,385 @@
++#include "axp-rw.h"
++#include "axp-cfg.h"
++
++
++static int  axp_init_chip(struct axp_mfd_chip *chip)
++{
++	uint8_t chip_id;
++	uint8_t v[19] = {0xd8,AXP_INTEN2, 0xff,AXP_INTEN3,0x03,
++						  AXP_INTEN4, 0x01,AXP_INTEN5, 0x00,
++						  AXP_INTSTS1,0xff,AXP_INTSTS2, 0xff,
++						  AXP_INTSTS3,0xff,AXP_INTSTS4, 0xff,
++						  AXP_INTSTS5,0xff};
++	int err;
++
++	/*read chip id*/	//???which int should enable must check with SD4
++	err =  __axp_read(chip->client, AXP_IC_TYPE, &chip_id);
++	if (err) {
++	    dev_err(chip->dev, "[AXP216-MFD] try to read chip id failed!\n");
++		return err;
++	}
++
++	/*enable irqs and clear*/
++	err =  __axp_writes(chip->client, AXP_INTEN1, 19, v);
++	if (err) {
++	    dev_err(chip->dev, "[AXP216-MFD] try to clear irq failed!\n");
++		return err;
++	}
++
++	dev_info(chip->dev, "AXP (CHIP ID: 0x%02x) detected\n", chip_id);
++	chip->type = AXP216;
++	
++	err =  __axp_write(chip->client, 0x81, 0xc1);
++	if (err) {
++	    dev_err(chip->dev, "[AXP216-MFD] try 0x81 failed!\n");
++		return err;
++	}
++	err =  __axp_read(chip->client, 0x81, &chip_id);
++	if (err) {
++	    //printk("[AXP216-MFD] read 0x81 0x%02x!\n",chip_id);
++		return err;
++	}
++
++	/* mask and clear all IRQs */
++	chip->irqs_enabled = 0xffffffff | (uint64_t)0xff << 32;
++	chip->ops->disable_irqs(chip, chip->irqs_enabled);
++
++	return 0;
++}
++
++static int axp_disable_irqs(struct axp_mfd_chip *chip, uint64_t irqs)
++{
++	uint8_t v[9];
++	int ret;
++
++	chip->irqs_enabled &= ~irqs;
++
++	v[0] = ((chip->irqs_enabled) & 0xff);
++	v[1] = AXP_INTEN2;
++	v[2] = ((chip->irqs_enabled) >> 8) & 0xff;
++	v[3] = AXP_INTEN3;
++	v[4] = ((chip->irqs_enabled) >> 16) & 0xff;
++	v[5] = AXP_INTEN4;
++	v[6] = ((chip->irqs_enabled) >> 24) & 0xff;
++	v[7] = AXP_INTEN5;
++	v[8] = ((chip->irqs_enabled) >> 32) & 0xff;
++	ret =  __axp_writes(chip->client, AXP_INTEN1, 9, v);
++
++	return ret;
++}
++
++static int axp_enable_irqs(struct axp_mfd_chip *chip, uint64_t irqs)
++{
++	uint8_t v[9];
++	int ret;
++
++	chip->irqs_enabled |=  irqs;
++
++	v[0] = ((chip->irqs_enabled) & 0xff);
++	v[1] = AXP_INTEN2;
++	v[2] = ((chip->irqs_enabled) >> 8) & 0xff;
++	v[3] = AXP_INTEN3;
++	v[4] = ((chip->irqs_enabled) >> 16) & 0xff;
++	v[5] = AXP_INTEN4;
++	v[6] = ((chip->irqs_enabled) >> 24) & 0xff;
++	v[7] = AXP_INTEN5;
++	v[8] = ((chip->irqs_enabled) >> 32) & 0xff;
++	ret =  __axp_writes(chip->client, AXP_INTEN1, 9, v);
++
++	return ret;
++}
++
++static int axp_read_irqs(struct axp_mfd_chip *chip, uint64_t *irqs)
++{
++	uint8_t v[5] = {0, 0, 0, 0, 0};
++	int ret;
++	ret =  __axp_reads(chip->client, AXP_INTSTS1, 5, v);
++	if (ret < 0)
++		return ret;
++	
++	*irqs =(((uint64_t) v[4]) << 32) |(((uint64_t) v[3]) << 24) | (((uint64_t) v[2])<< 16) | (((uint64_t)v[1]) << 8) | ((uint64_t) v[0]);
++	return 0;
++}
++
++
++static ssize_t axp_offvol_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++    uint8_t val = 0;
++	axp_read(dev,AXP_VOFF_SET,&val);
++	return sprintf(buf,"%d\n",(val & 0x07) * 100 + 2600);
++}
++
++static ssize_t axp_offvol_store(struct device *dev,
++				struct device_attribute *attr, const char *buf, size_t count)
++{
++	int tmp;
++	uint8_t val;
++	tmp = simple_strtoul(buf, NULL, 10);
++	if (tmp < 2600)
++		tmp = 2600;
++	if (tmp > 3300)
++		tmp = 3300;
++
++	axp_read(dev,AXP_VOFF_SET,&val);
++	val &= 0xf8;
++	val |= ((tmp - 2600) / 100);
++	axp_write(dev,AXP_VOFF_SET,val);
++	return count;
++}
++
++static ssize_t axp_noedelay_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++    uint8_t val;
++	axp_read(dev,AXP_OFF_CTL,&val);
++	if( (val & 0x03) == 0)
++		return sprintf(buf,"%d\n",128);
++	else
++		return sprintf(buf,"%d\n",(val & 0x03) * 1000);
++}
++
++static ssize_t axp_noedelay_store(struct device *dev,
++				struct device_attribute *attr, const char *buf, size_t count)
++{
++	int tmp;
++	uint8_t val;
++	tmp = simple_strtoul(buf, NULL, 10);
++	if (tmp < 1000)
++		tmp = 128;
++	if (tmp > 3000)
++		tmp = 3000;
++	axp_read(dev,AXP_OFF_CTL,&val);
++	val &= 0xfc;
++	val |= ((tmp) / 1000);
++	axp_write(dev,AXP_OFF_CTL,val);
++	return count;
++}
++
++static ssize_t axp_pekopen_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++    uint8_t val;
++	int tmp = 0;
++	axp_read(dev,AXP_POK_SET,&val);
++	switch(val >> 6){
++		case 0: tmp = 128;break;
++		case 1: tmp = 3000;break;
++		case 2: tmp = 1000;break;
++		case 3: tmp = 2000;break;
++		default:
++			tmp = 0;break;
++	}
++	return sprintf(buf,"%d\n",tmp);
++}
++
++static ssize_t axp_pekopen_store(struct device *dev,
++				struct device_attribute *attr, const char *buf, size_t count)
++{
++	int tmp;
++	uint8_t val;
++	tmp = simple_strtoul(buf, NULL, 10);
++	axp_read(dev,AXP_POK_SET,&val);
++	if (tmp < 1000)
++		val &= 0x3f;
++	else if(tmp < 2000){
++		val &= 0x3f;
++		val |= 0x80;
++	}
++	else if(tmp < 3000){
++		val &= 0x3f;
++		val |= 0xc0;
++	}
++	else {
++		val &= 0x3f;
++		val |= 0x40;
++	}
++	axp_write(dev,AXP_POK_SET,val);
++	return count;
++}
++
++static ssize_t axp_peklong_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++    uint8_t val = 0;
++	axp_read(dev,AXP_POK_SET,&val);
++	return sprintf(buf,"%d\n",((val >> 4) & 0x03) * 500 + 1000);
++}
++
++static ssize_t axp_peklong_store(struct device *dev,
++				struct device_attribute *attr, const char *buf, size_t count)
++{
++	int tmp;
++	uint8_t val;
++	tmp = simple_strtoul(buf, NULL, 10);
++	if(tmp < 1000)
++		tmp = 1000;
++	if(tmp > 2500)
++		tmp = 2500;
++	axp_read(dev,AXP_POK_SET,&val);
++	val &= 0xcf;
++	val |= (((tmp - 1000) / 500) << 4);
++	axp_write(dev,AXP_POK_SET,val);
++	return count;
++}
++
++static ssize_t axp_peken_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++    uint8_t val;
++	axp_read(dev,AXP_POK_SET,&val);
++	return sprintf(buf,"%d\n",((val >> 3) & 0x01));
++}
++
++static ssize_t axp_peken_store(struct device *dev,
++				struct device_attribute *attr, const char *buf, size_t count)
++{
++	int tmp;
++	uint8_t val;
++	tmp = simple_strtoul(buf, NULL, 10);
++	if(tmp)
++		tmp = 1;
++	axp_read(dev,AXP_POK_SET,&val);
++	val &= 0xf7;
++	val |= (tmp << 3);
++	axp_write(dev,AXP_POK_SET,val);
++	return count;
++}
++
++static ssize_t axp_pekdelay_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++    uint8_t val;
++	axp_read(dev,AXP_POK_SET,&val);
++
++	return sprintf(buf,"%d\n",((val >> 2) & 0x01)? 64:8);
++}
++
++static ssize_t axp_pekdelay_store(struct device *dev,
++				struct device_attribute *attr, const char *buf, size_t count)
++{
++	int tmp;
++	uint8_t val;
++	tmp = simple_strtoul(buf, NULL, 10);
++	if(tmp <= 8)
++		tmp = 0;
++	else
++		tmp = 1;
++	axp_read(dev,AXP_POK_SET,&val);
++	val &= 0xfb;
++	val |= tmp << 2;
++	axp_write(dev,AXP_POK_SET,val);
++	return count;
++}
++
++static ssize_t axp_pekclose_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++    uint8_t val;
++	axp_read(dev,AXP_POK_SET,&val);
++	return sprintf(buf,"%d\n",((val & 0x03) * 2000) + 4000);
++}
++
++static ssize_t axp_pekclose_store(struct device *dev,
++				struct device_attribute *attr, const char *buf, size_t count)
++{
++	int tmp;
++	uint8_t val;
++	tmp = simple_strtoul(buf, NULL, 10);
++	if(tmp < 4000)
++		tmp = 4000;
++	if(tmp > 10000)
++		tmp =10000;
++	tmp = (tmp - 4000) / 2000 ;
++	axp_read(dev,AXP_POK_SET,&val);
++	val &= 0xfc;
++	val |= tmp ;
++	axp_write(dev,AXP_POK_SET,val);
++	return count;
++}
++
++static ssize_t axp_ovtemclsen_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++    uint8_t val;
++	axp_read(dev,AXP_HOTOVER_CTL,&val);
++	return sprintf(buf,"%d\n",((val >> 2) & 0x01));
++}
++
++static ssize_t axp_ovtemclsen_store(struct device *dev,
++				struct device_attribute *attr, const char *buf, size_t count)
++{
++	int tmp;
++	uint8_t val;
++	tmp = simple_strtoul(buf, NULL, 10);
++	if(tmp)
++		tmp = 1;
++	axp_read(dev,AXP_HOTOVER_CTL,&val);
++	val &= 0xfb;
++	val |= tmp << 2 ;
++	axp_write(dev,AXP_HOTOVER_CTL,val);
++	return count;
++}
++
++static ssize_t axp_reg_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++    uint8_t val;
++	axp_read(dev,axp_reg_addr,&val);
++	return sprintf(buf,"REG[%x]=%x\n",axp_reg_addr,val);
++}
++
++static ssize_t axp_reg_store(struct device *dev,
++				struct device_attribute *attr, const char *buf, size_t count)
++{
++	int tmp;
++	uint8_t val;
++	tmp = simple_strtoul(buf, NULL, 16);
++	if( tmp < 256 )
++		axp_reg_addr = tmp;
++	else {
++		val = tmp & 0x00FF;
++		axp_reg_addr= (tmp >> 8) & 0x00FF;
++		axp_write(dev,axp_reg_addr, val);
++	}
++	return count;
++}
++
++static ssize_t axp_regs_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++  uint8_t val[2];
++	axp_reads(dev,axp_reg_addr,2,val);
++	return sprintf(buf,"REG[0x%x]=0x%x,REG[0x%x]=0x%x\n",axp_reg_addr,val[0],axp_reg_addr+1,val[1]);
++}
++
++static ssize_t axp_regs_store(struct device *dev,
++				struct device_attribute *attr, const char *buf, size_t count)
++{
++	int tmp;
++	uint8_t val[3];
++	tmp = simple_strtoul(buf, NULL, 16);
++	if( tmp < 256 )
++		axp_reg_addr = tmp;
++	else {
++		axp_reg_addr= (tmp >> 16) & 0xFF;
++		val[0] = (tmp >> 8) & 0xFF;
++		val[1] = axp_reg_addr + 1;
++		val[2] = tmp & 0xFF;
++		axp_writes(dev,axp_reg_addr,3,val);
++	}
++	return count;
++}
++
++static struct device_attribute axp_mfd_attrs[] = {
++	AXP_MFD_ATTR(axp_offvol),
++	AXP_MFD_ATTR(axp_noedelay),
++	AXP_MFD_ATTR(axp_pekopen),
++	AXP_MFD_ATTR(axp_peklong),
++	AXP_MFD_ATTR(axp_peken),
++	AXP_MFD_ATTR(axp_pekdelay),
++	AXP_MFD_ATTR(axp_pekclose),
++	AXP_MFD_ATTR(axp_ovtemclsen),
++	AXP_MFD_ATTR(axp_reg),
++	AXP_MFD_ATTR(axp_regs),
++};
+diff --git a/module_drivers/drivers/power/supply/axp_power/virtual216.c b/module_drivers/drivers/power/supply/axp_power/virtual216.c
+new file mode 100644
+index 000000000..85e001808
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/virtual216.c
+@@ -0,0 +1,472 @@
++/*
++ * reg-virtual-consumer.c
++ *
++ * Copyright 2008 Wolfson Microelectronics PLC.
++ *
++ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ */
++
++#include <linux/err.h>
++#include <linux/mutex.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++
++struct virtual_consumer_data {
++	struct mutex lock;
++	struct regulator *regulator;
++	int enabled;
++	int min_uV;
++	int max_uV;
++	int min_uA;
++	int max_uA;
++	unsigned int mode;
++};
++
++static void update_voltage_constraints(struct virtual_consumer_data *data)
++{
++	int ret;
++
++	if (data->min_uV && data->max_uV
++	    && data->min_uV <= data->max_uV) {
++		ret = regulator_set_voltage(data->regulator,
++					    data->min_uV, data->max_uV);
++		if (ret != 0) {
++			printk(KERN_ERR "regulator_set_voltage() failed: %d\n",
++			       ret);
++			return;
++		}
++	}
++
++	if (data->min_uV && data->max_uV && !data->enabled) {
++		ret = regulator_enable(data->regulator);
++		if (ret == 0)
++			data->enabled = 1;
++		else
++			printk(KERN_ERR "regulator_enable() failed: %d\n",
++				ret);
++	}
++
++	if (!(data->min_uV && data->max_uV) && data->enabled) {
++		ret = regulator_disable(data->regulator);
++		if (ret == 0)
++			data->enabled = 0;
++		else
++			printk(KERN_ERR "regulator_disable() failed: %d\n",
++				ret);
++	}
++}
++
++static void update_current_limit_constraints(struct virtual_consumer_data
++						*data)
++{
++	int ret;
++
++	if (data->max_uA
++	    && data->min_uA <= data->max_uA) {
++		ret = regulator_set_current_limit(data->regulator,
++					data->min_uA, data->max_uA);
++		if (ret != 0) {
++			pr_err("regulator_set_current_limit() failed: %d\n",
++			       ret);
++			return;
++		}
++	}
++
++	if (data->max_uA && !data->enabled) {
++		ret = regulator_enable(data->regulator);
++		if (ret == 0)
++			data->enabled = 1;
++		else
++			printk(KERN_ERR "regulator_enable() failed: %d\n",
++				ret);
++	}
++
++	if (!(data->min_uA && data->max_uA) && data->enabled) {
++		ret = regulator_disable(data->regulator);
++		if (ret == 0)
++			data->enabled = 0;
++		else
++			printk(KERN_ERR "regulator_disable() failed: %d\n",
++				ret);
++	}
++}
++
++static ssize_t show_min_uV(struct device *dev,
++			   struct device_attribute *attr, char *buf)
++{
++	struct virtual_consumer_data *data = dev_get_drvdata(dev);
++	return sprintf(buf, "%d\n", data->min_uV);
++}
++
++static ssize_t set_min_uV(struct device *dev, struct device_attribute *attr,
++			  const char *buf, size_t count)
++{
++	struct virtual_consumer_data *data = dev_get_drvdata(dev);
++	long val;
++
++#define strict_strtoul	kstrtoul
++#define strict_strtol	kstrtol
++#define strict_strtoull	kstrtoull
++#define strict_strtoll	kstrtoll
++	if (strict_strtol(buf, 10, &val) != 0)
++		return count;
++
++	mutex_lock(&data->lock);
++
++	data->min_uV = val;
++	update_voltage_constraints(data);
++
++	mutex_unlock(&data->lock);
++
++	return count;
++}
++
++static ssize_t show_max_uV(struct device *dev,
++			   struct device_attribute *attr, char *buf)
++{
++	struct virtual_consumer_data *data = dev_get_drvdata(dev);
++	return sprintf(buf, "%d\n", data->max_uV);
++}
++
++static ssize_t set_max_uV(struct device *dev, struct device_attribute *attr,
++			  const char *buf, size_t count)
++{
++	struct virtual_consumer_data *data = dev_get_drvdata(dev);
++	long val;
++
++	if (strict_strtol(buf, 10, &val) != 0)
++		return count;
++
++	mutex_lock(&data->lock);
++
++	data->max_uV = val;
++	update_voltage_constraints(data);
++
++	mutex_unlock(&data->lock);
++
++	return count;
++}
++
++static ssize_t show_min_uA(struct device *dev,
++			   struct device_attribute *attr, char *buf)
++{
++	struct virtual_consumer_data *data = dev_get_drvdata(dev);
++	return sprintf(buf, "%d\n", data->min_uA);
++}
++
++static ssize_t set_min_uA(struct device *dev, struct device_attribute *attr,
++			  const char *buf, size_t count)
++{
++	struct virtual_consumer_data *data = dev_get_drvdata(dev);
++	long val;
++
++	if (strict_strtol(buf, 10, &val) != 0)
++		return count;
++
++	mutex_lock(&data->lock);
++
++	data->min_uA = val;
++	update_current_limit_constraints(data);
++
++	mutex_unlock(&data->lock);
++
++	return count;
++}
++
++static ssize_t show_max_uA(struct device *dev,
++			   struct device_attribute *attr, char *buf)
++{
++	struct virtual_consumer_data *data = dev_get_drvdata(dev);
++	return sprintf(buf, "%d\n", data->max_uA);
++}
++
++static ssize_t set_max_uA(struct device *dev, struct device_attribute *attr,
++			  const char *buf, size_t count)
++{
++	struct virtual_consumer_data *data = dev_get_drvdata(dev);
++	long val;
++
++	if (strict_strtol(buf, 10, &val) != 0)
++		return count;
++
++	mutex_lock(&data->lock);
++
++	data->max_uA = val;
++	update_current_limit_constraints(data);
++
++	mutex_unlock(&data->lock);
++
++	return count;
++}
++
++static ssize_t show_mode(struct device *dev,
++			 struct device_attribute *attr, char *buf)
++{
++	struct virtual_consumer_data *data = dev_get_drvdata(dev);
++
++	switch (data->mode) {
++	case REGULATOR_MODE_FAST:
++		return sprintf(buf, "fast\n");
++	case REGULATOR_MODE_NORMAL:
++		return sprintf(buf, "normal\n");
++	case REGULATOR_MODE_IDLE:
++		return sprintf(buf, "idle\n");
++	case REGULATOR_MODE_STANDBY:
++		return sprintf(buf, "standby\n");
++	default:
++		return sprintf(buf, "unknown\n");
++	}
++}
++
++static ssize_t set_mode(struct device *dev, struct device_attribute *attr,
++			const char *buf, size_t count)
++{
++	struct virtual_consumer_data *data = dev_get_drvdata(dev);
++	unsigned int mode;
++	int ret;
++
++	if (strncmp(buf, "fast", strlen("fast")) == 0)
++		mode = REGULATOR_MODE_FAST;
++	else if (strncmp(buf, "normal", strlen("normal")) == 0)
++		mode = REGULATOR_MODE_NORMAL;
++	else if (strncmp(buf, "idle", strlen("idle")) == 0)
++		mode = REGULATOR_MODE_IDLE;
++	else if (strncmp(buf, "standby", strlen("standby")) == 0)
++		mode = REGULATOR_MODE_STANDBY;
++	else {
++		dev_err(dev, "Configuring invalid mode\n");
++		return count;
++	}
++
++	mutex_lock(&data->lock);
++	ret = regulator_set_mode(data->regulator, mode);
++	if (ret == 0)
++		data->mode = mode;
++	else
++		dev_err(dev, "Failed to configure mode: %d\n", ret);
++	mutex_unlock(&data->lock);
++
++	return count;
++}
++
++static DEVICE_ATTR(min_microvolts, 0644, show_min_uV, set_min_uV);
++static DEVICE_ATTR(max_microvolts, 0644, show_max_uV, set_max_uV);
++static DEVICE_ATTR(min_microamps, 0644, show_min_uA, set_min_uA);
++static DEVICE_ATTR(max_microamps, 0644, show_max_uA, set_max_uA);
++static DEVICE_ATTR(mode, 0644, show_mode, set_mode);
++
++struct device_attribute *attributes_virtual[] = {
++	&dev_attr_min_microvolts,
++	&dev_attr_max_microvolts,
++	&dev_attr_min_microamps,
++	&dev_attr_max_microamps,
++	&dev_attr_mode,
++};
++
++static int regulator_virtual_consumer_probe(struct platform_device *pdev)
++{
++	char *reg_id = pdev->dev.platform_data;
++	struct virtual_consumer_data *drvdata;
++	int ret, i;
++	drvdata = kzalloc(sizeof(struct virtual_consumer_data), GFP_KERNEL);
++	if (drvdata == NULL) {
++		ret = -ENOMEM;
++		goto err;
++	}
++
++	mutex_init(&drvdata->lock);
++
++	drvdata->regulator = regulator_get(NULL, reg_id);
++	if (IS_ERR(drvdata->regulator)) {
++		ret = PTR_ERR(drvdata->regulator);
++		dev_err(&pdev->dev, "IS_ERR \n");
++		goto err;
++	}
++	for (i = 0; i < ARRAY_SIZE(attributes_virtual); i++) {
++		ret = device_create_file(&pdev->dev, attributes_virtual[i]);
++		if (ret != 0)
++		{
++			dev_err(&pdev->dev, "device_create_file err\n") ;
++			goto err;}
++
++	}
++
++	drvdata->mode = regulator_get_mode(drvdata->regulator);
++
++	platform_set_drvdata(pdev, drvdata);
++
++	return 0;
++
++err:
++	for (i = 0; i < ARRAY_SIZE(attributes_virtual); i++)
++		device_remove_file(&pdev->dev, attributes_virtual[i]);
++	kfree(drvdata);
++	return ret;
++}
++
++static int regulator_virtual_consumer_remove(struct platform_device *pdev)
++{
++	struct virtual_consumer_data *drvdata = platform_get_drvdata(pdev);
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(attributes_virtual); i++)
++		device_remove_file(&pdev->dev, attributes_virtual[i]);
++	if (drvdata->enabled)
++		regulator_disable(drvdata->regulator);
++	regulator_put(drvdata->regulator);
++
++	kfree(drvdata);
++
++	return 0;
++}
++
++static struct platform_driver regulator_virtual_consumer_driver[] = {
++	{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-216-cs-rtc",
++		},
++	},{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-216-cs-aldo1",
++		},
++	},{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-216-cs-aldo2",
++		},
++	},{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-216-cs-aldo3",
++		},
++	},/*{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-22-cs-dldo1",
++		},
++	},{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-22-cs-dldo2",
++		},
++	},{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-22-cs-dldo3",
++		},
++	},{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-22-cs-dldo4",
++		},
++	},*/{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-216-cs-eldo1",
++		},
++	},{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-216-cs-eldo2",
++		},
++	},/*{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-22-cs-eldo3",
++		},
++	},*/{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-216-cs-dcdc1",
++		},
++	},{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-216-cs-dcdc2",
++		},
++	},{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-216-cs-dcdc3",
++		},
++	},{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-216-cs-dcdc4",
++		},
++	},{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-216-cs-dcdc5",
++		},
++	},/*{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-22-cs-gpio0ldo",
++		},
++	},*/{
++		.probe		= regulator_virtual_consumer_probe,
++		.remove		= regulator_virtual_consumer_remove,
++		.driver		= {
++			.name		= "reg-216-cs-gpio1ldo",
++		},
++	},
++	
++};
++
++
++static int __init regulator_virtual_consumer_init(void)
++{
++	int j,ret;
++	for (j = 0; j < ARRAY_SIZE(regulator_virtual_consumer_driver); j++){ 
++		ret =  platform_driver_register(&regulator_virtual_consumer_driver[j]);
++		if (ret)
++			goto creat_drivers_failed;
++	}
++	return ret;
++		
++creat_drivers_failed:
++	while (j--)
++		platform_driver_unregister(&regulator_virtual_consumer_driver[j]);
++	return ret;
++}
++module_init(regulator_virtual_consumer_init);
++
++static void __exit regulator_virtual_consumer_exit(void)
++{
++	int j;
++	for (j = ARRAY_SIZE(regulator_virtual_consumer_driver) - 1; j >= 0; j--){ 
++			platform_driver_unregister(&regulator_virtual_consumer_driver[j]);
++	}
++}
++module_exit(regulator_virtual_consumer_exit);
++
++MODULE_AUTHOR("Donglu Zhang Krosspower");
++MODULE_DESCRIPTION("Virtual regulator consumer");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/power/supply/axp_power/virtual216_dev.c b/module_drivers/drivers/power/supply/axp_power/virtual216_dev.c
+new file mode 100644
+index 000000000..a55a83104
+--- /dev/null
++++ b/module_drivers/drivers/power/supply/axp_power/virtual216_dev.c
+@@ -0,0 +1,157 @@
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/machine.h>
++#include <linux/i2c.h>
++//#include <mach/irqs.h>
++#include <linux/power_supply.h>
++#include <linux/module.h>
++
++#include "axp-cfg.h"
++#include "axp-mfd.h"
++
++static struct platform_device virt[]={
++	{
++			.name = "reg-216-cs-rtc",
++			.id = -1,
++			.dev		= {
++				.platform_data = "rtc_on",
++			}
++ 	},{
++			.name = "reg-216-cs-aldo1",
++			.id = -1,
++			.dev		= {
++				.platform_data = "cam_on",
++			}
++ 	},{
++			.name = "reg-216-cs-aldo2",
++			.id = -1,
++			.dev		= {
++				.platform_data = "codec_on",
++			}
++ 	},{
++			.name = "reg-216-cs-aldo3",
++			.id = -1,
++			.dev		= {
++				.platform_data = "ledir_on",
++			}
++	},/*{
++			.name = "reg-22-cs-dldo1",
++			.id = -1,
++			.dev		= {
++				.platform_data = "axp22_dldo1",
++			}
++ 	},{
++			.name = "reg-22-cs-dldo2",
++			.id = -1,
++			.dev		= {
++				.platform_data = "axp22_dldo2",
++			}
++ 	},{
++			.name = "reg-22-cs-dldo3",
++			.id = -1,
++			.dev		= {
++				.platform_data = "axp22_dldo3",
++			}
++	},{
++			.name = "reg-22-cs-dldo4",
++			.id = -1,
++			.dev		= {
++				.platform_data = "axp22_dldo4",
++			}
++	},*/{
++			.name = "reg-216-cs-eldo1",
++			.id = -1,
++			.dev		= {
++				.platform_data = "dvp_on",
++			}
++	},{
++			.name = "reg-216-cs-eldo2",
++			.id = -1,
++			.dev		= {
++				.platform_data = "wlreg_on",
++			}
++	},/*{
++			.name = "reg-22-cs-eldo3",
++			.id = -1,
++			.dev		= {
++				.platform_data = "axp22_eldo3",
++			}
++	},*/{
++			.name = "reg-216-cs-dcdc1",
++			.id = -1,
++			.dev		= {
++				.platform_data = "cpu_vddio_3v3",
++			}
++	},{
++			.name = "reg-216-cs-dcdc2",
++			.id = -1,
++			.dev		= {
++				.platform_data = "cpu_vmem",
++			}
++	},{
++			.name = "reg-216-cs-dcdc3",
++			.id = -1,
++			.dev		= {
++				.platform_data = "cpu_core",
++			}
++	},{
++			.name = "reg-216-cs-dcdc4",
++			.id = -1,
++			.dev		= {
++				.platform_data = "dcdc4",
++			}
++ 	},{
++			.name = "reg-216-cs-dcdc5",
++			.id = -1,
++			.dev		= {
++				.platform_data = "cpu_vddio_1v8",
++			}
++	},/*{
++			.name = "reg-22-cs-gpio0ldo",
++			.id = -1,
++			.dev		= {
++				.platform_data = "axp22_ldoio0",
++			}
++ 	},*/{
++			.name = "reg-216-cs-gpio1ldo",
++			.id = -1,
++			.dev		= {
++				.platform_data = "dmic_on",
++			}
++	},
++};
++
++
++
++ static int __init virtual_init(void)
++{
++	int j,ret;
++	for (j = 0; j < ARRAY_SIZE(virt); j++){
++ 		ret =  platform_device_register(&virt[j]);
++  		if (ret)
++				goto creat_devices_failed;
++	}
++	return ret;
++
++creat_devices_failed:
++	while (j--)
++		platform_device_register(&virt[j]);
++	return ret;
++
++}
++
++module_init(virtual_init);
++
++static void __exit virtual_exit(void)
++{
++	int j;
++	for (j = ARRAY_SIZE(virt) - 1; j >= 0; j--){
++		platform_device_unregister(&virt[j]);
++	}
++}
++module_exit(virtual_exit);
++
++MODULE_DESCRIPTION("X-POWER axp regulator test");
++MODULE_AUTHOR("Weijin Zhong Krosspower");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/pwm/Kconfig b/module_drivers/drivers/pwm/Kconfig
+new file mode 100644
+index 000000000..7a5e27ac9
+--- /dev/null
++++ b/module_drivers/drivers/pwm/Kconfig
+@@ -0,0 +1,36 @@
++
++config PWM_INGENIC
++        tristate "Ingenic PWM support"
++        depends on MACH_XBURST || SOC_X2500
++        help
++          Generic PWM framework driver for Ingenic soc based
++          machines.
++
++          To compile this driver as a module, choose M here: the module
++          will be called pwm-ingenic.
++
++config PWM_INGENIC_V2
++        tristate "Ingenic PWM V2 support"
++        depends on SOC_X2000_V12 || SOC_X2000 || SOC_M300 || SOC_X2100
++        help
++          Generic PWM framework driver for Ingenic soc based
++          machines.
++          Support SOCs: X2000,
++
++          To compile this driver as a module, choose M here: the module
++          will be called pwm-ingenic.
++
++
++config PWM_INGENIC_V3
++        bool "Ingenic V3 PWM support"
++        depends on SOC_X1600
++        help
++          Generic PWM framework driver for ingenic PWM-V3
++          machines.
++
++config JZ_PWM_GPIO_TRIGGER
++        bool "pwm gpio trigger support"
++        depends on PWM_INGENIC_V3
++        default n
++
++
+diff --git a/module_drivers/drivers/pwm/Makefile b/module_drivers/drivers/pwm/Makefile
+new file mode 100644
+index 000000000..45802766e
+--- /dev/null
++++ b/module_drivers/drivers/pwm/Makefile
+@@ -0,0 +1,4 @@
++
++obj-$(CONFIG_PWM_INGENIC)       += pwm-ingenic.o
++obj-$(CONFIG_PWM_INGENIC_V2)    += pwm-ingenic-v2.o
++obj-$(CONFIG_PWM_INGENIC_V3)    += pwm-ingenic-v3.o
+diff --git a/module_drivers/drivers/pwm/pwm-ingenic-v2.c b/module_drivers/drivers/pwm/pwm-ingenic-v2.c
+new file mode 100644
+index 000000000..d93bc0e91
+--- /dev/null
++++ b/module_drivers/drivers/pwm/pwm-ingenic-v2.c
+@@ -0,0 +1,906 @@
++/* drivers/pwm/pwm-ingenic-x2000.c
++ * PWM driver of Ingenic's SoC X2000
++ *
++ * Copyright (C) 2015 Ingenic Semiconductor Co., Ltd.
++ *	http://www.ingenic.com
++ * Author:	sihui.liu <sihui.liu@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/slab.h>
++#include <linux/gpio.h>
++#include <linux/pwm.h>
++#include <linux/clk.h>
++#include <linux/ctype.h>
++#include <linux/stat.h>
++#include <linux/pwm.h>
++#include <linux/time.h>
++#include <asm/io.h>
++#include <asm-generic/div64.h>
++#include <linux/sysfs.h>
++#include <irq.h>
++#include <linux/interrupt.h>
++#include <linux/dma-mapping.h>
++
++#define INGENIC_PWM_NUM		(16)
++#define NS_IN_HZ		(1000000000UL)
++#define DEFAULT_PWM_CLK_RATE	(50000000)
++#define PWM_INIT_HIGH		(1)
++#define PWM_INIT_LOW		(0)
++#define PWM_WCFG_HIGH		(16)
++#define PWM_WCFG_LOW		(0)
++
++#define DE_WARNING	0
++
++struct ingenic_pwm_channel {
++	u32 period_ns;
++	u32 duty_ns;
++};
++
++enum pwm_mode_sel{
++	COMMON_MODE,
++	DMA_MODE
++};
++
++struct ingenic_pwm_chip {
++	struct pwm_chip chip;
++	struct clk *clk_pwm;
++	struct clk *clk_gate;
++	void __iomem    *iomem;
++	int init_level;
++	struct mutex mutex;
++	unsigned int output_mask;
++
++	struct pwm_device *debug_pwm[INGENIC_PWM_NUM];
++	void *vir_addr[INGENIC_PWM_NUM];
++	unsigned int phy_addr[INGENIC_PWM_NUM];
++	int debug_current_id;
++	int mode_sel[INGENIC_PWM_NUM];
++	int irq;
++};
++
++/**-----------------------------------------------------------------------------
++ **                       reg offset
++ **-----------------------------------------------------------------------------*/
++
++#define	PWM_CCFG0	(0x0)
++#define	PWM_CCFG1	(0x4)
++#define	PWM_ENS		(0x10)
++#define	PWM_ENC		(0x14)
++#define	PWM_EN		(0x18)
++#define	PWM_UP		(0x20)
++#define	PWM_BUSY	(0x24)
++#define PWM_INITR	(0x30)
++#define PWM_WCFG	(0xb0)
++#define PWM_DES		(0x100)
++#define PWM_DEC		(0x104)
++#define PWM_DE		(0x108)
++#define PWM_DCR0	(0x110)
++#define PWM_DCR1	(0x114)
++#define PWM_DTRIG	(0x120)
++#define PWM_DFER	(0x124)
++#define PWM_DFSM	(0x128)
++#define PWM_DSR		(0x130)
++#define PWM_DSCR	(0x134)
++#define PWM_DINTC	(0x138)
++#define PWM_DMADDR	(0x140)
++#define PWM_DTLR	(0x190)
++#define PWM_OEN		(0x300)
++
++
++#define PRESCALE_MSK	(0xf)
++#define PRESCALE	(0x2)
++#define TRANS_LEN	(32)
++#define	PWM_PER		(0x30)
++
++
++/**-----------------------------------------------------------------------------
++ **                       reg bit field
++ **-----------------------------------------------------------------------------*/
++
++static void pwm_writel(struct ingenic_pwm_chip *chip, unsigned int value, unsigned int offset)
++{
++	writel(value, chip->iomem + offset);
++}
++
++static unsigned int pwm_readl(struct ingenic_pwm_chip *chip, unsigned int offset)
++{
++	return readl(chip->iomem + offset);
++}
++
++static void pwm_clk_config(struct ingenic_pwm_chip *chip, unsigned int channel, unsigned int prescale)
++{
++	int tmp = 0;
++	if(channel < 8) {
++		tmp = pwm_readl(chip, PWM_CCFG0) & ~(PRESCALE_MSK << (channel *4));
++		tmp |= prescale << (channel * 4);
++		pwm_writel(chip, tmp, PWM_CCFG0);
++	} else {
++		tmp = pwm_readl(chip, PWM_CCFG1) & ~(PRESCALE_MSK << ((channel - 8) * 4));
++		tmp |= prescale << ((channel - 8) * 4);
++		pwm_writel(chip, tmp, PWM_CCFG1);
++	}
++}
++
++static unsigned int pwm_get_prescale(struct ingenic_pwm_chip *chip, unsigned int channel)
++{
++	int tmp = 0;
++	int prescale = 0;
++	if(channel < 8) {
++		tmp = pwm_readl(chip, PWM_CCFG0);
++		prescale = tmp & (0xf << channel * 4);
++	} else {
++		tmp = pwm_readl(chip, PWM_CCFG1);
++		prescale = tmp & (0xf << (channel - 8) * 4);
++	}
++	return prescale;
++}
++
++static void pwm_enable_hw(struct ingenic_pwm_chip *chip, unsigned int channel)
++{
++	int tmp = 0;
++	tmp = pwm_readl(chip, PWM_EN);
++	tmp |= (1 << channel);
++	pwm_writel(chip, tmp, PWM_ENS);
++}
++
++static void pwm_disable_hw(struct ingenic_pwm_chip *chip, unsigned int channel)
++{
++	pwm_writel(chip, 1 << channel, PWM_ENC);
++}
++
++static int pwm_enable_status(struct ingenic_pwm_chip *chip)
++{
++	return pwm_readl(chip, PWM_EN);
++}
++
++static void pwm_update(struct ingenic_pwm_chip *chip, unsigned int channel)
++{
++	pwm_writel(chip, 1 << channel, PWM_UP);
++}
++
++static int pwm_busy(struct ingenic_pwm_chip *chip, unsigned int channel)
++{
++	int tmp = 0;
++	tmp = pwm_readl(chip, PWM_BUSY);
++	return tmp & (1 << channel);
++}
++
++#if DE_WARNING
++static void pwm_set_period_hw(struct ingenic_pwm_chip *chip, unsigned int channel, unsigned int period)
++{
++	pwm_writel(chip, period, PWM_PER + channel * 4);
++}
++#endif
++
++static void pwm_set_init_level(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel, unsigned int level)
++{
++	int tmp;
++	tmp = pwm_readl(ingenic_pwm,PWM_INITR);
++	if(level)
++		tmp |= 1 << channel;
++	else
++		tmp &= ~(1 << channel);
++	pwm_writel(ingenic_pwm,tmp,PWM_INITR);
++}
++
++static void pwm_set_finish_level(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel, unsigned int level)
++{
++	int tmp;
++	tmp = pwm_readl(ingenic_pwm,PWM_INITR);
++	if(level)
++		tmp |= 1 << (channel + 16);
++	else
++		tmp &= ~(1 << (channel + 16));
++	pwm_writel(ingenic_pwm,tmp,PWM_INITR);
++}
++
++static void pwm_waveform_high(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel, unsigned int high_num)
++{
++	int tmp = 0;
++	tmp = pwm_readl(ingenic_pwm, PWM_WCFG + channel * 4);
++	tmp &= ~(0xffff << PWM_WCFG_HIGH);
++	tmp |= high_num << PWM_WCFG_HIGH;
++	pwm_writel(ingenic_pwm, tmp, PWM_WCFG + channel * 4);
++}
++
++static void pwm_waveform_low(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel, unsigned int low_num)
++{
++	int tmp = 0;
++	tmp = pwm_readl(ingenic_pwm, PWM_WCFG + channel * 4);
++	tmp &= ~(0xffff);
++	tmp |= low_num << PWM_WCFG_LOW;
++	pwm_writel(ingenic_pwm, tmp, PWM_WCFG + channel * 4);
++}
++
++/*pwm DMA mode control register operation*/
++static void pwm_dma_enable_hw(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	int tmp = 0;
++	tmp = pwm_readl(ingenic_pwm, PWM_DES);
++	tmp |= (1 << channel);
++	pwm_writel(ingenic_pwm, tmp, PWM_DES);
++}
++
++static void pwm_dma_disable_hw(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	pwm_writel(ingenic_pwm, 1 << channel, PWM_DEC);
++}
++
++#if DE_WARNING
++static int pwm_dma_enable_status(struct ingenic_pwm_chip *ingenic_pwm)
++{
++	return pwm_readl(ingenic_pwm, PWM_DE);
++}
++#endif
++
++static void pwm_set_update_mode(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel, int mode_sel)
++{
++	int tmp;
++	tmp = pwm_readl(ingenic_pwm,PWM_DCR0);
++	if(mode_sel == DMA_MODE)
++		tmp |= 1 << channel;
++	if(mode_sel == COMMON_MODE)
++		tmp &= ~(1 << channel);
++	pwm_writel(ingenic_pwm,tmp,PWM_DCR0);
++}
++
++#if DE_WARNING
++static void pwm_dma_set_loop(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	int tmp;
++	tmp = pwm_readl(ingenic_pwm,PWM_DCR1);
++	tmp |= 1 << channel;
++	pwm_writel(ingenic_pwm,tmp,PWM_DCR1);
++}
++#endif
++
++static void pwm_dma_clear_loop(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	int tmp;
++	tmp = pwm_readl(ingenic_pwm,PWM_DCR1);
++	tmp &= ~(1 << channel);
++	pwm_writel(ingenic_pwm,tmp,PWM_DCR1);
++}
++
++static unsigned int pwm_dma_get_loop_status(struct ingenic_pwm_chip *ingenic_pwm,unsigned int channel)
++{
++	return pwm_readl(ingenic_pwm,PWM_DCR1) & (1 << channel);
++}
++
++static void pwm_dma_trans_trigger(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	int tmp;
++	tmp = pwm_readl(ingenic_pwm,PWM_DTRIG);
++	tmp |= 1 << channel;
++	pwm_writel(ingenic_pwm,tmp,PWM_DTRIG);
++}
++
++static unsigned int pwm_dma_fifo_empty(struct ingenic_pwm_chip *ingenic_pwm,unsigned int channel)
++{
++	return pwm_readl(ingenic_pwm,PWM_DFER) & (1 << channel);
++}
++
++static unsigned int pwm_dma_get_dfsm(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	int tmp;
++	tmp = pwm_readl(ingenic_pwm,PWM_DFSM);
++	tmp &= 1 << channel;
++	return tmp;
++}
++
++static int pwm_dma_get_status(struct ingenic_pwm_chip *ingenic_pwm)
++{
++	return pwm_readl(ingenic_pwm,PWM_DSR);
++}
++
++#if DE_WARNING
++static void pwm_dma_clear_status(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	int tmp;
++	tmp = pwm_readl(ingenic_pwm,PWM_DSCR);
++	tmp |= 1 << channel;
++	pwm_writel(ingenic_pwm,tmp,PWM_DSCR);
++}
++#endif
++
++#if DE_WARNING
++static void pwm_dma_interrupt_mask(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	int tmp;
++	tmp = pwm_readl(ingenic_pwm,PWM_DINTC);
++	tmp |= 1 << channel;
++	pwm_writel(ingenic_pwm,tmp,PWM_DINTC);
++}
++#endif
++
++static void pwm_dma_interrupt_unmask(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	int tmp;
++	tmp = pwm_readl(ingenic_pwm,PWM_DINTC);
++	tmp &=  ~(1 << channel);
++	pwm_writel(ingenic_pwm,tmp,PWM_DINTC);
++}
++
++static void pwm_dma_set_mem_addr(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel, unsigned int mem_addr)
++{
++	pwm_writel(ingenic_pwm,mem_addr,PWM_DMADDR + channel * 4);
++}
++
++/*DMA transfer length must 4 word align*/
++static void pwm_dma_set_trans_length(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel, int tran_len)
++{
++	pwm_writel(ingenic_pwm,tran_len,PWM_DTLR + channel * 4);
++}
++
++static void pwm_set_io_output_enable(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel, int enable)
++{
++	int tmp;
++	tmp = pwm_readl(ingenic_pwm, PWM_OEN);
++	if(enable)
++		tmp |= 1 << channel;
++	else
++		tmp &= ~(1 << channel);
++	pwm_writel(ingenic_pwm, tmp, PWM_OEN);
++}
++
++static void dump_pwm_reg(struct ingenic_pwm_chip *ingenic_pwm)
++{
++	int i;
++	printk("PWM_CCFG0 addr %08x  = %08x\n", (unsigned int)(ingenic_pwm->iomem + PWM_CCFG0),pwm_readl(ingenic_pwm, PWM_CCFG0));
++	printk("PWM_CCFG1 addr %08x  = %08x\n", (unsigned int)(ingenic_pwm->iomem + PWM_CCFG1),pwm_readl(ingenic_pwm, PWM_CCFG1));
++	printk("PWM_ENS   addr %08x  = %08x\n", (unsigned int)(ingenic_pwm->iomem + PWM_ENS), pwm_readl(ingenic_pwm, PWM_ENS));
++	printk("PWM_ENC   addr %08x  = %08x\n", (unsigned int)(ingenic_pwm->iomem + PWM_ENC),pwm_readl(ingenic_pwm, PWM_ENC));
++	printk("PWM_EN    addr %08x  = %08x\n", (unsigned int)(ingenic_pwm->iomem + PWM_EN),pwm_readl(ingenic_pwm, PWM_EN));
++	printk("PWM_UP    addr %08x  = %08x\n", (unsigned int)(ingenic_pwm->iomem + PWM_UP),pwm_readl(ingenic_pwm, PWM_UP));
++	printk("PWM_LOOP  addr %08x  = %08x\n", (unsigned int)(ingenic_pwm->iomem + PWM_DCR1),pwm_readl(ingenic_pwm, PWM_DCR1));
++	printk("PWM_MASK  addr %08x  = %08x\n", (unsigned int)(ingenic_pwm->iomem + PWM_DINTC),pwm_readl(ingenic_pwm, PWM_DINTC));
++	printk("PWM_BUSY  addr %08x  = %08x\n", (unsigned int)(ingenic_pwm->iomem + PWM_BUSY),pwm_readl(ingenic_pwm, PWM_BUSY));
++	for(i = 0; i < 16; i++) {
++		printk("PWM_DAR %d addr %08x = %08x\n", i,(unsigned int)(ingenic_pwm->iomem + i * 4), pwm_readl(ingenic_pwm, PWM_DMADDR + i * 4));
++	}
++	for(i = 0; i < 16; i++) {
++		printk("PWM_WCFG%d addr %08x = %08x\n", i,(unsigned int)(ingenic_pwm->iomem + i * 4), pwm_readl(ingenic_pwm, PWM_WCFG + i * 4));
++	}
++	for(i = 0; i < 16; i++) {
++		printk("PWM_DTLR%d addr %08x = %08x\n", i, (unsigned int)(ingenic_pwm->iomem + i * 4),pwm_readl(ingenic_pwm, PWM_DTLR + i * 4));
++	}
++}
++
++
++static irqreturn_t ingenic_pwm_interrupt(int irq, void *dev_id)
++{
++	int tmp;
++	struct ingenic_pwm_chip *ingenic_pwm = (struct ingenic_pwm_chip *)(dev_id);
++	tmp = pwm_dma_get_status(ingenic_pwm);
++	/*clear end flag*/
++	pwm_writel(ingenic_pwm,tmp,PWM_DSCR);
++
++	/*restart DMA transfer*/
++	pwm_writel(ingenic_pwm,tmp,PWM_DTRIG);
++
++	return IRQ_HANDLED;
++}
++//--------------------------add end----------------------
++
++static inline struct ingenic_pwm_chip *to_ingenic_chip(struct pwm_chip *chip)
++{
++	return container_of(chip, struct ingenic_pwm_chip, chip);
++}
++
++static int ingenic_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
++		int duty_ns, int period_ns)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = to_ingenic_chip(chip);
++	int channel = pwm->hwpwm;
++	unsigned int period = 0;
++	unsigned int duty = 0;
++	unsigned int pwm_freq = 0;
++	unsigned int clk_in = 0;
++	unsigned int prescale = 0;
++	unsigned int tmp = 1;
++	int i = 0;
++	int update_flag = 1;
++	int mode = 0;
++	void *dma_coherent;
++	dma_addr_t dma_coherent_handle;
++	unsigned long long clk_ns = 1000000000ULL;
++
++	mutex_lock(&ingenic_pwm->mutex);
++	if (duty_ns < 0 || duty_ns > period_ns) {
++		pr_err("%s, duty_ns(%d)< 0 or duty_ns > period_ns(%d)\n", __func__, duty_ns, period_ns);
++		return -EINVAL;
++	}
++
++	if(period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
++		return -ERANGE;
++
++	/*select mode */
++	mode = ingenic_pwm->mode_sel[channel];
++
++	/*set prescale*/
++	pwm_clk_config(ingenic_pwm, channel, PRESCALE);
++	clk_in = clk_get_rate(ingenic_pwm->clk_pwm);
++	prescale = pwm_get_prescale(ingenic_pwm, channel);
++
++	for (i = 0; i < PRESCALE; i++)
++		tmp = 2 * tmp;
++
++	pwm_freq = clk_in / tmp;
++	do_div(clk_ns, pwm_freq);
++
++	period = (period_ns / (unsigned int)clk_ns);
++	printk("period=%d\n", period);
++	//pwm_set_period_hw(ingenic_pwm, channel, period);
++	duty = duty_ns / (unsigned int)clk_ns;
++
++	/*set init level*/
++	if (ingenic_pwm->init_level == PWM_INIT_HIGH)
++		pwm_set_init_level(ingenic_pwm,channel,1);
++	else if (ingenic_pwm->init_level == PWM_INIT_LOW)
++		pwm_set_init_level(ingenic_pwm,channel,0);
++	else
++		pr_err("%s, pwm init level error\n", __func__);
++
++	printk("duty=%d level_init=%d low=%d\n", duty, ingenic_pwm->init_level, period - duty);
++
++	/*set waveform high_num and low_num*/
++	if(COMMON_MODE == mode){
++		//*****************************test**(duty**period)**********
++		pwm_waveform_high(ingenic_pwm, channel, duty);
++		pwm_waveform_low(ingenic_pwm, channel, period - duty);
++	}
++
++	/*Set the level state at the end of the waveform*/
++	pwm_set_finish_level(ingenic_pwm,channel,0);
++
++	/*pwm output enable*/
++	pwm_set_io_output_enable(ingenic_pwm, channel, 1);
++
++	/*Update bit according to mode setting*/
++	pwm_set_update_mode(ingenic_pwm, channel, mode);
++
++	/*Whether to update*/
++	if(pwm->state.enabled) {
++		if(COMMON_MODE == mode){
++			pwm_update(ingenic_pwm, channel);
++			while(pwm_busy(ingenic_pwm, channel));
++		}
++		if(DMA_MODE == mode){
++			update_flag = 0;
++			if(!pwm_dma_get_loop_status(ingenic_pwm, channel)){
++				while(!pwm_dma_fifo_empty(ingenic_pwm, channel));
++				if(pwm_dma_fifo_empty(ingenic_pwm, channel))
++					update_flag = 1;
++			}
++		}
++	}
++	/*DMA mode related configuration*/
++	if(DMA_MODE == mode && update_flag){
++
++		dma_coherent = dma_alloc_coherent(ingenic_pwm->chip.dev, sizeof(int) * TRANS_LEN, &dma_coherent_handle, GFP_KERNEL);
++		//printk("--%s-------%d-dma_coherent = %x--dma_coherent_handle = %x---write value = %x----\n",__func__,__LINE__,(unsigned int)dma_coherent,dma_coherent_handle,(0x1111ffff));
++		dma_cache_wback_inv((unsigned int)dma_coherent,sizeof(int) * TRANS_LEN);
++		for(i = 0; i < TRANS_LEN; i++ ){
++			//printk("-----------befor-addr = %x--value ----%x --- \n",(unsigned int)dma_coherent + i * 4,*(volatile unsigned int *)(dma_coherent + i * 4));
++			/* configuration duty ratio 1/2 */
++			*(volatile unsigned int *)(dma_coherent + i * 4) = (0xffffffff);
++			//printk("-----------after-addr = %x--value ----%x --- \n",(unsigned int)dma_coherent + i * 4,*(volatile unsigned int *)(dma_coherent + i * 4));
++		}
++		ingenic_pwm->vir_addr[channel] = dma_coherent;
++		ingenic_pwm->phy_addr[channel] = dma_coherent_handle;
++
++		/*set addr and trans_len*/
++		pwm_dma_set_mem_addr(ingenic_pwm, channel, dma_coherent_handle);
++		pwm_dma_set_trans_length(ingenic_pwm, channel, TRANS_LEN);
++
++		/*set interrupt */
++		pwm_dma_clear_loop(ingenic_pwm, channel);
++		pwm_dma_interrupt_unmask(ingenic_pwm, channel);
++	}
++	mutex_unlock(&ingenic_pwm->mutex);
++	return 0;
++}
++
++
++static int ingenic_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = to_ingenic_chip(chip);
++	int channel = pwm->hwpwm;
++	int count = 0;
++	mutex_lock(&ingenic_pwm->mutex);
++
++	if(ingenic_pwm->mode_sel[channel] == DMA_MODE){
++		/*enable DMA mode*/
++		while(pwm_dma_get_dfsm(ingenic_pwm,channel)){
++			count ++;
++			if(count == 0x10000000){
++				printk("pwm %d channel is working\n",channel);
++				return 0;
++			}
++		}
++		pwm_dma_enable_hw(ingenic_pwm, channel);
++		pwm_dma_trans_trigger(ingenic_pwm, channel);
++	}
++	pwm_enable_hw(ingenic_pwm, channel);
++	mutex_unlock(&ingenic_pwm->mutex);
++
++	return 0;
++}
++
++static void ingenic_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = to_ingenic_chip(chip);
++	int channel = pwm->hwpwm;
++
++	mutex_lock(&ingenic_pwm->mutex);
++	if(ingenic_pwm->mode_sel[channel] == DMA_MODE){
++		pwm_dma_disable_hw(ingenic_pwm,channel);
++		dma_free_coherent(ingenic_pwm->chip.dev,sizeof(int) * TRANS_LEN, ingenic_pwm->vir_addr[channel], ingenic_pwm->phy_addr[channel]);
++	}
++
++	pwm_disable_hw(ingenic_pwm, channel);
++	mutex_unlock(&ingenic_pwm->mutex);
++}
++
++
++
++static const struct pwm_ops ingenic_pwm_ops = {
++	.config = ingenic_pwm_config,
++	.enable = ingenic_pwm_enable,
++	.disable = ingenic_pwm_disable,
++	.owner = THIS_MODULE,
++};
++
++
++static ssize_t pwm_show_enable(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	return sprintf(buf, "%x", pwm_enable_status(ingenic_pwm));
++}
++
++static ssize_t pwm_store_enable(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	int enable;
++	const char *str = buf;
++	int ret_count = 0;
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count)
++			return count;
++	}
++	enable = simple_strtoul(str, (char **)&str, 10);
++
++	printk("input enable value %d,current_id %d\n",enable,ingenic_pwm->debug_current_id);
++	if (enable) {
++		pwm_enable(ingenic_pwm->debug_pwm[ingenic_pwm->debug_current_id]);
++	} else
++		pwm_disable(ingenic_pwm->debug_pwm[ingenic_pwm->debug_current_id]);
++	return count;
++}
++
++
++static ssize_t pwm_show_config(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	dump_pwm_reg(ingenic_pwm);
++	printk("\n");
++	return 0;
++}
++
++static ssize_t pwm_store_config(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	const char *str = buf;
++	unsigned int period_ns, duty_ns;
++	int mode = 0;
++	int ret_count = 0;
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count)
++			return count;
++	}
++	mode = simple_strtoul(str, (char **)&str, 10);
++	if(DMA_MODE == mode)
++		ingenic_pwm->mode_sel[ingenic_pwm->debug_current_id] = DMA_MODE;
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count)
++			return count;
++	}
++	duty_ns = simple_strtoul(str, (char **)&str, 10);
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count)
++			return count;
++	}
++	period_ns = simple_strtoul(str, (char **)&str, 10);
++
++	printk("current_id = %d, period_ns = %d , duty_ns = %d mode = %s\n",ingenic_pwm->debug_current_id, period_ns,duty_ns,mode? "DMA_MODE":"COMMON_MODE");
++	pwm_config(ingenic_pwm->debug_pwm[ingenic_pwm->debug_current_id], duty_ns, period_ns);
++	printk("pwm_config finish\n");
++
++	return count;
++}
++
++static ssize_t pwm_show_channel(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++
++	return sprintf(buf, "channel = %x", ingenic_pwm->debug_current_id);
++
++}
++
++static ssize_t pwm_store_channel(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	const char *str = buf;
++	int ret_count = 0;
++	int pwm_id = 0;
++	struct pwm_device *pwm = NULL;
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count)
++			return count;
++	}
++	pwm_id = simple_strtoul(str, (char **)&str, 10);
++	pwm = pwm_request(pwm_id, "pwm_request_test");
++	if (IS_ERR(pwm)) {
++		printk("unable to request pwm\n");
++		return -1;
++	}
++	ingenic_pwm->debug_pwm[pwm_id] = pwm;
++	ingenic_pwm->debug_current_id = pwm_id;
++	printk("channel = %d\n", ingenic_pwm->debug_current_id);
++	return count;
++}
++
++static ssize_t pwm_store_free(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	const char *str = buf;
++	int ret_count = 0;
++	int pwm_id = 0;
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count)
++			return count;
++	}
++	pwm_id = simple_strtoul(str, (char **)&str, 10);
++
++	pwm_disable(ingenic_pwm->debug_pwm[pwm_id]);
++	pwm_put(ingenic_pwm->debug_pwm[pwm_id]);
++	ingenic_pwm->debug_pwm[pwm_id] = NULL;
++	return count;
++}
++
++static ssize_t pwm_show_requested_channel(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	int i = 0;
++	int ret = 0;
++
++	for (i = 0; i <INGENIC_PWM_NUM ; i++) {
++		if (ingenic_pwm->debug_pwm[i] == &(ingenic_pwm->chip.pwms[i]))
++			ret += sprintf(buf + ret, "ch: %02d requested\n", i);
++		else
++			ret += sprintf(buf + ret, "ch: %02d unrequested\n", i);
++	}
++	return ret;
++}
++
++static struct device_attribute pwm_device_attributes[] = {
++	__ATTR(enable, S_IRUGO|S_IWUSR, pwm_show_enable, pwm_store_enable),
++	__ATTR(config, S_IRUGO|S_IWUSR, pwm_show_config, pwm_store_config),
++	__ATTR(request, S_IRUGO|S_IWUSR, pwm_show_channel, pwm_store_channel),
++	__ATTR(free, S_IWUSR, NULL, pwm_store_free),
++	__ATTR(channels, S_IRUGO, pwm_show_requested_channel, NULL),
++};
++
++static int ingenic_pwm_probe(struct platform_device *pdev)
++{
++	struct ingenic_pwm_chip *chip;
++	struct resource *res;
++	int err = 0;
++	int ret = 0;
++	int i = 0;
++
++	chip = devm_kzalloc(&pdev->dev,
++			sizeof(struct ingenic_pwm_chip), GFP_KERNEL);
++	if (!chip) {
++		pr_err("%s %d,malloc ingenic_pwm_chip error\n",
++				__func__, __LINE__);
++		return -ENOMEM;
++	}
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (res == NULL) {
++		dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
++		return  -ENOENT;
++	}
++
++	chip->irq = platform_get_irq(pdev, 0);
++	if(chip->irq < 0){
++		dev_err(&pdev->dev, "Cannot get %d  IORESOURCE_IRQ\n",chip->irq);
++		return  -ENOENT;
++	}
++
++	chip->iomem = ioremap(res->start, (res->end - res->start) + 1);
++	if (chip->iomem == NULL) {
++		dev_err(&pdev->dev, "Cannot map IO\n");
++		err = -ENXIO;
++		goto err_no_iomap;
++	}
++
++	chip->clk_gate = devm_clk_get(&pdev->dev, "gate_pwm");
++	if (IS_ERR(chip->clk_gate)) {
++		dev_err(&pdev->dev, "get pwm clk gate failed %ld\n", PTR_ERR(chip->clk_gate));
++		return PTR_ERR(chip->clk_gate);
++	}
++
++	chip->clk_pwm = devm_clk_get(&pdev->dev, "div_pwm");
++	if(IS_ERR(chip->clk_pwm)){
++		dev_err(&pdev->dev, "get pwm clk failed %ld\n", PTR_ERR(chip->clk_pwm));
++		return PTR_ERR(chip->clk_pwm);
++	}
++
++	if(chip->clk_gate) {
++		ret = clk_prepare_enable(chip->clk_gate);
++		if(ret) {
++			dev_err(&pdev->dev, "enable pwm clock gate failed!\n");
++		}
++	}
++
++	if(chip->clk_pwm) {
++		ret = clk_set_rate(chip->clk_pwm, DEFAULT_PWM_CLK_RATE);
++		if(ret) {
++			dev_err(&pdev->dev, "set pwm clock rate failed!\n");
++		}
++		ret = clk_prepare_enable(chip->clk_pwm);
++		if(ret) {
++			dev_err(&pdev->dev, "enable pwm clock failed!\n");
++		}
++	}
++
++	chip->chip.dev = &pdev->dev;
++	chip->chip.ops = &ingenic_pwm_ops;
++	chip->chip.base = 0;
++	chip->chip.npwm = INGENIC_PWM_NUM;
++	chip->init_level = PWM_INIT_HIGH;
++
++	ret = pwmchip_add(&chip->chip);
++	if (ret < 0) {
++		devm_kfree(&pdev->dev, chip);
++		return ret;
++	}
++
++	ret = request_irq(chip->irq,ingenic_pwm_interrupt,
++			IRQF_SHARED | IRQF_TRIGGER_LOW,"pwm-interrupt",chip);
++	if (ret) {
++		dev_err(&pdev->dev, "request_irq failed !! %d-\n",chip->irq);
++		goto err_no_iomap;
++	}
++
++	platform_set_drvdata(pdev, chip);
++	mutex_init(&chip->mutex);
++
++	for (i = 0; i < ARRAY_SIZE(pwm_device_attributes); i++) {
++		ret = device_create_file(&pdev->dev, &pwm_device_attributes[i]);
++		if (ret)
++			dev_warn(&pdev->dev, "attribute %d create failed", i);
++	}
++
++	dev_info(&pdev->dev, "ingenic-x2000 Probe of pwm success!\n");
++	return 0;
++
++err_no_iomap:
++	iounmap(chip->iomem);
++
++	return err;
++}
++
++static int ingenic_pwm_remove(struct platform_device *pdev)
++{
++	struct ingenic_pwm_chip *chip;
++	chip =platform_get_drvdata(pdev);
++	if (!chip)
++		return -ENODEV;
++
++	free_irq(chip->irq,chip);
++	pwmchip_remove(&chip->chip);
++	devm_clk_put(&pdev->dev,chip->clk_pwm);
++	devm_clk_put(&pdev->dev,chip->clk_gate);
++	devm_kfree(&pdev->dev, chip);
++	return 0;
++}
++
++static const struct of_device_id ingenic_pwm_matches[] = {
++	{ .compatible = "ingenic,x2000-pwm", .data = NULL },
++	{ .compatible = "ingenic,m300-pwm", .data = NULL },
++	{},
++};
++
++#ifdef CONFIG_PM_SLEEP
++static int ingenic_pwm_suspend(struct device *dev)
++{
++	struct ingenic_pwm_chip *chip = dev_get_drvdata(dev);
++	unsigned int i;
++
++	/*
++	 * No one preserves these values during suspend so reset them.
++	 * Otherwise driver leaves PWM unconfigured if same values are
++	 * passed to pwm_config() next time.
++	 */
++	for (i = 0; i < INGENIC_PWM_NUM; ++i) {
++		struct pwm_device *pwm = &chip->chip.pwms[i];
++		struct ingenic_pwm_channel *chan = pwm_get_chip_data(pwm);
++
++		if (!chan)
++			continue;
++		chan->period_ns = 0;
++		chan->duty_ns = 0;
++	}
++
++	return 0;
++}
++
++static int ingenic_pwm_resume(struct device *dev)
++{
++	struct ingenic_pwm_chip *chip = dev_get_drvdata(dev);
++	unsigned int chan;
++
++	/*
++	 * Inverter setting must be preserved across suspend/resume
++	 * as nobody really seems to configure it more than once.
++	 */
++	for (chan = 0; chan < INGENIC_PWM_NUM; ++chan) {
++		if (chip->output_mask & BIT(chan)) {
++			/*TODO: ??*/
++		}
++	}
++	return 0;
++}
++#endif
++
++static SIMPLE_DEV_PM_OPS(ingenic_pwm_pm_ops, ingenic_pwm_suspend, ingenic_pwm_resume);
++
++static struct platform_driver ingenic_pwm_driver = {
++	.driver = {
++		.name = "ingenic-pwm",
++		.pm = &ingenic_pwm_pm_ops,
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(ingenic_pwm_matches),
++	},
++	.probe = ingenic_pwm_probe,
++	.remove = ingenic_pwm_remove,
++};
++module_platform_driver(ingenic_pwm_driver);
++
++MODULE_DESCRIPTION("Ingenic SoC PWM driver");
++MODULE_ALIAS("platform:ingenic-pwm");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/pwm/pwm-ingenic-v3.c b/module_drivers/drivers/pwm/pwm-ingenic-v3.c
+new file mode 100644
+index 000000000..96f0210bc
+--- /dev/null
++++ b/module_drivers/drivers/pwm/pwm-ingenic-v3.c
+@@ -0,0 +1,1273 @@
++/* drivers/pwm/pwm-ingenic-x1600.c
++ * PWM driver of Ingenic's SoC X1600
++ *
++ * Copyright (C) 2015 Ingenic Semiconductor Co., Ltd.
++ *	http://www.ingenic.com
++ * Author:	sihui.liu <sihui.liu@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/slab.h>
++#include <linux/gpio.h>
++#include <linux/pwm.h>
++#include <linux/clk.h>
++#include <linux/ctype.h>
++#include <linux/stat.h>
++#include <linux/pwm.h>
++#include <linux/time.h>
++#include <asm/io.h>
++#include <asm-generic/div64.h>
++#include <linux/sysfs.h>
++#include <irq.h>
++#include <linux/interrupt.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <dt-bindings/dma/ingenic-pdma.h>
++
++#define PWM_DBUG
++#ifndef PWM_DBUG
++#define print_dbg(fmt, argv...)
++#else
++#define print_dbg(fmt, argv...) printk(fmt, ##argv)
++#endif
++
++#define INGENIC_PWM_NUM		(8)
++#define BUFFER_SIZE		PAGE_SIZE
++#define NS_IN_HZ		(1000000000UL)
++#define DEFAULT_PWM_CLK_RATE	(40000000)
++#define SG_PWM_NUM	(100)
++unsigned int add_off = 0;
++
++struct ingenic_pwm_channel {
++	u32 period_ns;
++	u32 duty_ns;
++};
++
++struct ingenic_pwm_chan {
++	int id;
++	struct ingenic_pwm_chip *chip;
++	struct dma_chan 	*dma_chan;
++	struct scatterlist  	*sg;	/* I/O scatter list */
++	void			*buffer;
++	dma_addr_t		buffer_dma;
++	int mode;
++	unsigned int duty_ns;
++	unsigned int period_ns;
++	bool init_level;
++	bool finish_level;
++	bool trigger_en;
++	bool trigger_posedge;
++	bool trigger_negedge;
++	int trigger_filter;
++	unsigned int store_irq_num;
++	unsigned int sg_pwm_num;
++	unsigned int full_duty_status; /*Record last output level*/
++};
++
++enum pwm_mode_sel{
++	COMMON_MODE,
++	DMA_MODE_SG,
++	DMA_MODE_CYCLIC,
++};
++
++struct ingenic_pwm_chip {
++	struct pwm_chip chip;
++	struct clk *clk_pwm;
++	struct clk *clk_gate;
++	void __iomem    *iomem;
++	int irq;
++	struct mutex mutex;
++	unsigned int output_mask;
++
++	struct pwm_device *debug_pwm[INGENIC_PWM_NUM];
++	int debug_current_id;
++
++	unsigned long		phys;
++	struct ingenic_pwm_chan chan[INGENIC_PWM_NUM];
++};
++
++#define GENMASK(hi, lo)   (((1ULL << ((hi) - (lo) + 1)) - 1) << (lo))
++#define	PWM_ENS		(0x00)
++#define	PWM_ENC		(0x04)
++#define	PWM_EN		(0x08)
++#define	PWM_UPT		(0x10)
++#define	PWM_BUSY	(0x14)
++#define	PWM_MS		(0x20)
++#define PWM_INL		(0x24)
++#define PWM_IDL		(0x28)
++#define PWM_CCFG0	(0x40)
++#define PWM_WCFG0	(0x80)
++#define PWM_DR0		(0xc0)
++#define PWM_DFN0	(0x100)
++#define PWM_DRTN0	(0x140)
++#define PWM_DRE		(0x180)
++#define PWM_DRS		(0x184)
++#define PWM_DFIE	(0x188)
++#define PWM_DFS		(0x18c)
++#define PWM_DAFF	(0x190)
++#define PWM_DCFF	(0x194)
++#define PWM_SS		(0x200)
++#define PWM_SIE		(0x204)
++#define PWM_SC0		(0x210)
++#define PWM_SN0		(0x250)
++#define PWM_ON0		(0x290)
++#define PWM_CCFG(n)	(PWM_CCFG0 + 4*n)
++#define PWM_WCFG(n)	(PWM_WCFG0 + 4*n)
++#define PWM_DR(n)	(PWM_DR0 + 4*n)
++#define PWM_DFN(n)	(PWM_DFN0 + 4*n)
++#define PWM_DRTN(n)	(PWM_DRTN0 + 4*n)
++#define PWM_SC(n)	(PWM_SC0 + 4*n)
++#define PWM_SN(n)	(PWM_SN0 + 4*n)
++#define PWM_ON(n)	(PWM_ON0 + 4*n)
++
++#define PWM_WCFG_HIGH		(16)
++#define PWM_WCFG_LOW		(0)
++
++#define PWM_STORE_SE	BIT(18)
++#define PWM_STORE_SPE	BIT(17)
++#define PWM_STORE_SNE	BIT(16)
++#define PWM_STORE_SFN_LBIT	0
++#define PWM_STORE_SFN_HBIT	9
++#define PWM_STORE_SFN_MASK	\
++	GENMASK(PWM_STORE_SFN_HBIT, PWM_STORE_SFN_LBIT)
++
++
++/**
++ **		pwm basic operation configuration interface
++ **/
++static void pwm_writel(struct ingenic_pwm_chip *ingenic_pwm, unsigned int value, unsigned int offset)
++{
++	writel(value, ingenic_pwm->iomem + offset);
++}
++
++static unsigned int pwm_readl(struct ingenic_pwm_chip *ingenic_pwm, unsigned int offset)
++{
++	return readl(ingenic_pwm->iomem + offset);
++}
++
++static unsigned int pwm_store_status(struct ingenic_pwm_chip *ingenic_pwm)
++{
++	return pwm_readl(ingenic_pwm, PWM_SS);
++}
++
++static void pwm_store_clear_status(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	pwm_writel(ingenic_pwm, 1 << channel, PWM_SS);
++}
++
++static void pwm_trigger_enable_interrupt(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	unsigned int val;
++	val = pwm_readl(ingenic_pwm, PWM_SIE);
++	pwm_writel(ingenic_pwm, val | (1 << channel), PWM_SIE);
++}
++
++static void pwm_store_disable_interrupt(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	unsigned int val;
++	val = pwm_readl(ingenic_pwm, PWM_SIE);
++	pwm_writel(ingenic_pwm, val & ~(1 << channel), PWM_SIE);
++}
++
++static void pwm_trigger_enable(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	unsigned int val;
++	val = pwm_readl(ingenic_pwm, PWM_SC(channel));
++	pwm_writel(ingenic_pwm, val | PWM_STORE_SE, PWM_SC(channel));
++}
++
++static void pwm_store_disable(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	unsigned int val;
++	val = pwm_readl(ingenic_pwm, PWM_SC(channel));
++	pwm_writel(ingenic_pwm, val & ~PWM_STORE_SE, PWM_SC(channel));
++}
++
++static void pwm_trigger_posedge_enable(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	unsigned int val;
++	val = pwm_readl(ingenic_pwm, PWM_SC(channel));
++	pwm_writel(ingenic_pwm, val | PWM_STORE_SPE, PWM_SC(channel));
++}
++
++static void pwm_trigger_posedge_disable(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	unsigned int val;
++	val = pwm_readl(ingenic_pwm, PWM_SC(channel));
++	pwm_writel(ingenic_pwm, val & ~PWM_STORE_SPE, PWM_SC(channel));
++}
++static void pwm_trigger_negedge_enable(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	unsigned int val;
++	val = pwm_readl(ingenic_pwm, PWM_SC(channel));
++	pwm_writel(ingenic_pwm, val | PWM_STORE_SNE, PWM_SC(channel));
++}
++
++static void pwm_trigger_negedge_disable(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	unsigned int val;
++	val = pwm_readl(ingenic_pwm, PWM_SC(channel));
++	pwm_writel(ingenic_pwm, val & ~PWM_STORE_SNE, PWM_SC(channel));
++}
++
++static void pwm_trigger_filter_set(struct ingenic_pwm_chip *ingenic_pwm,
++		unsigned int channel,
++		unsigned int number)
++{
++	unsigned int val;
++	val = pwm_readl(ingenic_pwm, PWM_SC(channel));
++	pwm_writel(ingenic_pwm, (val & ~PWM_STORE_SFN_MASK) | number, PWM_SC(channel));
++}
++
++static unsigned int pwm_get_store_num(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	return pwm_readl(ingenic_pwm, PWM_SN(channel));
++}
++
++static unsigned int pwm_get_output_num(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	return pwm_readl(ingenic_pwm, PWM_ON(channel));
++}
++
++static void pwm_clk_config(struct ingenic_pwm_chip *ingenic_pwm,
++		unsigned int channel, unsigned int prescale)
++{
++	pwm_writel(ingenic_pwm, prescale, PWM_CCFG(channel));
++}
++
++static int pwm_get_prescale(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	return pwm_readl(ingenic_pwm, PWM_CCFG(channel));
++}
++
++static void pwm_enable_hw(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	pwm_writel(ingenic_pwm, 1 << channel, PWM_ENS);
++}
++
++static void pwm_disable_hw(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	pwm_writel(ingenic_pwm, 1 << channel, PWM_ENC);
++}
++
++static int pwm_enable_status(struct ingenic_pwm_chip *ingenic_pwm)
++{
++	return pwm_readl(ingenic_pwm, PWM_EN);
++}
++static void pwm_update(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	pwm_writel(ingenic_pwm, 1 << channel, PWM_UPT);
++}
++
++static int pwm_busy(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	int tmp = 0;
++	tmp = pwm_readl(ingenic_pwm, PWM_BUSY);
++	return tmp & (1 << channel);
++}
++
++static void pwm_set_init_level(struct ingenic_pwm_chip *ingenic_pwm,
++		unsigned int channel, unsigned int level)
++{
++	int tmp;
++	tmp = pwm_readl(ingenic_pwm,PWM_INL);
++
++	if(level)
++		tmp |= 1 << channel;
++	else
++		tmp &= ~(1 << channel);
++	pwm_writel(ingenic_pwm,tmp,PWM_INL);
++}
++
++static void pwm_set_finish_level(struct ingenic_pwm_chip *ingenic_pwm,
++		unsigned int channel, unsigned int level)
++{
++	int tmp;
++	tmp = pwm_readl(ingenic_pwm,PWM_IDL);
++	if(level)
++		tmp |= 1 << channel;
++	else
++		tmp &= ~(1 << channel);
++	pwm_writel(ingenic_pwm,tmp,PWM_IDL);
++}
++
++static void pwm_waveform_high(struct ingenic_pwm_chip *ingenic_pwm,
++		unsigned int channel, unsigned int high_num)
++{
++	int tmp = 0;
++	tmp = pwm_readl(ingenic_pwm, PWM_WCFG(channel));
++	tmp &= ~(0xffff << PWM_WCFG_HIGH);
++	tmp |= high_num << PWM_WCFG_HIGH;
++	pwm_writel(ingenic_pwm, tmp, PWM_WCFG(channel));
++}
++
++static void pwm_waveform_low(struct ingenic_pwm_chip *ingenic_pwm,
++		unsigned int channel, unsigned int low_num)
++{
++	int tmp = 0;
++	tmp = pwm_readl(ingenic_pwm, PWM_WCFG(channel));
++	tmp &= ~(0xffff);
++	tmp |= low_num << PWM_WCFG_LOW;
++	pwm_writel(ingenic_pwm, tmp, PWM_WCFG(channel));
++}
++
++/*pwm DMA mode control register operation*/
++static void pwm_dma_enable_hw(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	int tmp = 0;
++	tmp = pwm_readl(ingenic_pwm, PWM_DRE);
++	tmp |= (1 << channel);
++	pwm_writel(ingenic_pwm, tmp, PWM_DRE);
++}
++
++static void pwm_dma_disable_hw(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	int tmp = 0;
++	tmp = pwm_readl(ingenic_pwm, PWM_DRE);
++	tmp &= ~(1 << channel);
++	pwm_writel(ingenic_pwm, tmp, PWM_DRE);
++}
++
++static void pwm_set_update_mode(struct ingenic_pwm_chip *ingenic_pwm,
++		unsigned int channel, int mode_sel)
++{
++	int tmp;
++	tmp = pwm_readl(ingenic_pwm,PWM_MS);
++	if(mode_sel == DMA_MODE_SG || mode_sel == DMA_MODE_CYCLIC)
++		tmp |= 1 << channel;
++	if(mode_sel == COMMON_MODE)
++		tmp &= ~(1 << channel);
++	pwm_writel(ingenic_pwm,tmp,PWM_MS);
++}
++static void pwm_dma_under_irq_enable(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	int tmp;
++	tmp = pwm_readl(ingenic_pwm,PWM_DFIE);
++	tmp |= (1 << channel);
++	pwm_writel(ingenic_pwm,tmp,PWM_DFIE);
++}
++
++static void pwm_dma_under_irq_disable(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	int tmp;
++	tmp = pwm_readl(ingenic_pwm,PWM_DFIE);
++	tmp &= ~(1 << channel);
++	pwm_writel(ingenic_pwm,tmp,PWM_DFIE);
++}
++
++static unsigned int pwm_dma_under_status(struct ingenic_pwm_chip *ingenic_pwm)
++{
++	return pwm_readl(ingenic_pwm,PWM_DFS);
++}
++
++static void pwm_dma_clear_under(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	int tmp;
++	tmp = pwm_readl(ingenic_pwm,PWM_DFS);
++	tmp |= (1 << channel);
++	pwm_writel(ingenic_pwm,tmp,PWM_DFS);
++}
++
++static void pwm_set_fifo_throshold(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	pwm_writel(ingenic_pwm, 32, PWM_DRTN(channel));
++}
++
++static void pwm_dma_fifo_flush(struct ingenic_pwm_chip *ingenic_pwm, unsigned int channel)
++{
++	pwm_writel(ingenic_pwm, 1 << channel, PWM_DCFF);
++}
++
++static void dump_pwm_reg(struct ingenic_pwm_chip *ingenic_pwm)
++{
++	int i;
++	printk("PWM_EN(%08x)	= %08x\n", PWM_EN, pwm_readl(ingenic_pwm, PWM_EN));
++	printk("PWM_UPT(%08x)	= %08x\n", PWM_UPT, pwm_readl(ingenic_pwm, PWM_UPT));
++	printk("PWM_BUSY(%08x)  = %08x\n", PWM_BUSY, pwm_readl(ingenic_pwm, PWM_BUSY));
++	printk("PWM_MS(%08x)	= %08x\n", PWM_MS, pwm_readl(ingenic_pwm, PWM_MS));
++	printk("PWM_INL(%08x)	= %08x\n", PWM_INL, pwm_readl(ingenic_pwm, PWM_INL));
++	printk("PWM_IDL(%08x)  = %08x\n", PWM_IDL, pwm_readl(ingenic_pwm, PWM_IDL));
++	printk("PWM_DRS(%08x)  = %08x\n", PWM_DRS, pwm_readl(ingenic_pwm, PWM_DRS));
++	printk("PWM_DFIE(%08x)  = %08x\n", PWM_DFIE, pwm_readl(ingenic_pwm, PWM_DFIE));
++	printk("PWM_DFS(%08x)  = %08x\n", PWM_DFS, pwm_readl(ingenic_pwm, PWM_DFS));
++	printk("PWM_DRE(%08x)  = %08x\n", PWM_DRE,pwm_readl(ingenic_pwm, PWM_DRE));
++	printk("PWM_SS(%08x)  = %08x\n", PWM_SS,pwm_readl(ingenic_pwm, PWM_SS));
++	printk("PWM_SIE(%08x)  = %08x\n", PWM_SIE,pwm_readl(ingenic_pwm, PWM_SIE));
++	for(i = 0; i < INGENIC_PWM_NUM; i++) {
++		if(!(pwm_readl(ingenic_pwm, PWM_EN) & (1 << i)))
++			continue;
++		printk("\n>>>Channel-%d store_num = (0x%x)%d:\n",i, ingenic_pwm->chan[i].store_irq_num, ingenic_pwm->chan[i].store_irq_num);
++		printk("PWM_CCFG(%08x)  = %08x\n", PWM_CCFG(i),pwm_readl(ingenic_pwm, PWM_CCFG(i)));
++		printk("PWM_WCFG(%08x)  = %08x\n", PWM_WCFG(i),pwm_readl(ingenic_pwm, PWM_WCFG(i)));
++		printk("PWM_DR(%08x)  = %08x\n", PWM_DR(i),pwm_readl(ingenic_pwm, PWM_DR(i)));
++		printk("PWM_DFN(%08x)  = %08x\n", PWM_DFN(i),pwm_readl(ingenic_pwm, PWM_DFN(i)));
++		printk("PWM_DRTN(%08x)  = %08x\n\n", PWM_DRTN(i),pwm_readl(ingenic_pwm, PWM_DRTN(i)));
++		printk("PWM_SC(%08x)  = %08x\n\n", PWM_SC(i),pwm_readl(ingenic_pwm, PWM_SC(i)));
++		printk("PWM_SN(%08x)  = %08x\n\n", PWM_SN(i),pwm_readl(ingenic_pwm, PWM_SN(i)));
++		printk("PWM_ON(%08x)  = %08x\n\n", PWM_ON(i),pwm_readl(ingenic_pwm, PWM_ON(i)));
++	}
++}
++
++static inline struct ingenic_pwm_chip *to_ingenic_chip(struct pwm_chip *chip)
++{
++	return container_of(chip, struct ingenic_pwm_chip, chip);
++}
++
++static void dma_tx_callback(void *data)
++{
++	/* print_dbg(">>%s %d\n",__func__,__LINE__); */
++}
++
++static int ingenic_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
++		int duty_ns, int period_ns)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = to_ingenic_chip(chip);
++	int channel = pwm->hwpwm;
++	struct ingenic_pwm_chan *ingenic_chan = &ingenic_pwm->chan[channel];
++	unsigned int period = 0;
++	unsigned int duty = 0;
++	unsigned int clk_in = 0;
++	unsigned int prescale = 0;
++	unsigned long long tmp;
++	int mode = 0;
++	int stable_output_flag = 0;
++
++	mutex_lock(&ingenic_pwm->mutex);
++	if (duty_ns < 0 || duty_ns > period_ns) {
++		pr_err("%s, duty_ns(%d)< 0 or duty_ns > period_ns(%d)\n", __func__, duty_ns, period_ns);
++		mutex_unlock(&ingenic_pwm->mutex);
++		return -EINVAL;
++	}
++
++	if(duty_ns < 0 || duty_ns > period_ns){
++		mutex_unlock(&ingenic_pwm->mutex);
++		return -ERANGE;
++	}
++
++	/*select mode */
++	mode = ingenic_chan->mode;
++	ingenic_chan->duty_ns = duty_ns;
++	ingenic_chan->period_ns = period_ns;
++
++	/*set prescale*/
++	clk_in = clk_get_rate(ingenic_pwm->clk_pwm);
++
++	/* period = period_ns / (1000000000 / clk_in) */
++	tmp = (unsigned long long)clk_in * period_ns;
++	do_div(tmp, 1000000000);
++	period = tmp;
++	while (period > 0xffff && prescale < 8) {
++		period >>= 1;
++		++prescale;
++	}
++	if (prescale == 8){
++		mutex_unlock(&ingenic_pwm->mutex);
++		return -EINVAL;
++	}
++
++	/* duty = period / (period_ns / duty_ns) */
++	tmp = (unsigned long long)period * duty_ns;
++	do_div(tmp, period_ns);
++	duty = tmp;
++
++	print_dbg("period_ns=%d duty_ns = %d high_ns = %d clk_in = %u\n",
++			period_ns, duty_ns,
++			period_ns-duty_ns,
++			clk_in);
++	print_dbg("period = %d LOW=%d HIGH=%d init_level=%d finsh_level = %d div = %d\n",
++			period, duty, period-duty,
++			ingenic_chan->init_level,
++			ingenic_chan->finish_level,
++			prescale);
++	print_dbg("trigger_en = %d negedge = %d posedge  =%d filter = %d\n",
++			ingenic_chan->trigger_en,
++			ingenic_chan->trigger_posedge,
++			ingenic_chan->trigger_negedge,
++			ingenic_chan->trigger_filter);
++	if(duty_ns == period_ns){
++		ingenic_chan->finish_level = !ingenic_chan->init_level;
++		stable_output_flag = 1;
++	}
++	else if(duty_ns == 0){
++		ingenic_chan->finish_level = ingenic_chan->init_level;
++		stable_output_flag = 1;
++	}
++
++	/*set init level*/
++	pwm_clk_config(ingenic_pwm, channel, prescale);
++	pwm_set_init_level(ingenic_pwm,channel,ingenic_chan->init_level);
++	pwm_set_finish_level(ingenic_pwm,channel,ingenic_chan->finish_level);
++	pwm_set_update_mode(ingenic_pwm, channel, mode);
++	if(ingenic_chan->trigger_en) {
++		pwm_trigger_enable(ingenic_pwm, channel);
++		if(ingenic_chan->trigger_negedge)
++			pwm_trigger_negedge_enable(ingenic_pwm, channel);
++		else
++			pwm_trigger_negedge_disable(ingenic_pwm, channel);
++		if(ingenic_chan->trigger_posedge)
++			pwm_trigger_posedge_enable(ingenic_pwm, channel);
++		else
++			pwm_trigger_posedge_disable(ingenic_pwm, channel);
++		pwm_trigger_enable_interrupt(ingenic_pwm, channel);
++		pwm_trigger_filter_set(ingenic_pwm, channel, ingenic_chan->trigger_filter);
++	}
++
++	/*set waveform high_num and low_num*/
++	if(COMMON_MODE == mode){
++		pwm_waveform_high(ingenic_pwm, channel, duty);
++		pwm_waveform_low(ingenic_pwm, channel, period - duty);
++
++		if(stable_output_flag == 1){
++			pwm_disable_hw(ingenic_pwm, channel);
++			ingenic_chan->full_duty_status = 1;
++		}
++		else if(ingenic_chan->full_duty_status == 1){
++			pwm_enable_hw(ingenic_pwm, channel);
++			ingenic_chan->full_duty_status = 0;
++		}
++		else if(ingenic_pwm->chip.pwms[channel].flags) {
++			pwm_update(ingenic_pwm, channel);
++			while(pwm_busy(ingenic_pwm, channel));
++		}
++	}
++
++	if(DMA_MODE_SG == mode || DMA_MODE_CYCLIC == mode)
++	{
++		struct dma_slave_config tx_config;
++		struct dma_async_tx_descriptor *txdesc;
++		struct dma_chan *txchan = ingenic_chan->dma_chan;
++		unsigned int *wave;
++		unsigned int val;
++		int i;
++		tx_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++		tx_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++		tx_config.dst_maxburst = 4;
++		tx_config.src_maxburst = 4;
++		tx_config.dst_addr = (dma_addr_t)(ingenic_pwm->phys+PWM_DR(channel));
++		tx_config.slave_id = 0;
++		tx_config.direction = DMA_MEM_TO_DEV;
++		dmaengine_slave_config(txchan, &tx_config);
++
++		ingenic_chan->buffer = dma_alloc_coherent(ingenic_pwm->chip.dev, BUFFER_SIZE,
++						&ingenic_chan->buffer_dma, GFP_KERNEL);
++		if (!ingenic_chan->buffer) {
++			dev_err(ingenic_pwm->chip.dev, "PWM request temp dma buffer failed");
++		}
++		memset(ingenic_chan->buffer, 0, BUFFER_SIZE);
++		wave = ingenic_chan->buffer;
++		val = duty | ((period-duty) << 16);
++		for(i = 0; i < BUFFER_SIZE / 4; i++) {
++			wave[i] = val;
++		}
++		if(mode == DMA_MODE_CYCLIC) {
++			txdesc = txchan->device->device_prep_dma_cyclic(txchan,
++						      ingenic_chan->buffer_dma,
++						      BUFFER_SIZE,
++						      BUFFER_SIZE/4,
++						      DMA_MEM_TO_DEV,
++						      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
++		} else {
++			sg_init_one(ingenic_chan->sg, ingenic_chan->buffer, ingenic_chan->sg_pwm_num*4);
++			if (dma_map_sg(ingenic_pwm->chip.dev,
++				       ingenic_chan->sg, 1, DMA_TO_DEVICE) != 1) {
++				dev_err(ingenic_pwm->chip.dev, "dma_map_sg tx error\n");
++			}
++
++			txdesc = dmaengine_prep_slave_sg(txchan,
++						      ingenic_chan->sg,
++						      1,
++						      DMA_MEM_TO_DEV,
++						      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
++		}
++		if(!txdesc) {
++			dev_err(ingenic_pwm->chip.dev, "PWM request dma desc failed");
++		}
++		txdesc->callback = dma_tx_callback;
++		txdesc->callback_param = ingenic_chan;
++		dmaengine_submit(txdesc);
++		if(mode == DMA_MODE_CYCLIC)
++			pwm_dma_under_irq_enable(ingenic_pwm, channel);
++		pwm_set_fifo_throshold(ingenic_pwm, channel);
++		pwm_dma_fifo_flush(ingenic_pwm, channel);
++
++		dma_async_issue_pending(txchan);
++	}
++	mutex_unlock(&ingenic_pwm->mutex);
++	return 0;
++}
++
++static int ingenic_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = to_ingenic_chip(chip);
++	int channel = pwm->hwpwm;
++	struct ingenic_pwm_chan *ingenic_chan = &ingenic_pwm->chan[channel];
++
++	if(ingenic_chan->full_duty_status)
++		return 0;
++
++	mutex_lock(&ingenic_pwm->mutex);
++	ingenic_chan->store_irq_num = 0;
++
++	if(DMA_MODE_SG == ingenic_chan->mode ||
++			DMA_MODE_CYCLIC == ingenic_chan->mode)
++		pwm_dma_enable_hw(ingenic_pwm, channel);
++	pwm_enable_hw(ingenic_pwm, channel);
++//	dump_pwm_reg(ingenic_pwm);
++	mutex_unlock(&ingenic_pwm->mutex);
++
++	return 0;
++}
++
++static void ingenic_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = to_ingenic_chip(chip);
++	int channel = pwm->hwpwm;
++	struct ingenic_pwm_chan *ingenic_chan = &ingenic_pwm->chan[channel];
++
++	mutex_lock(&ingenic_pwm->mutex);
++
++	if(ingenic_chan->mode == DMA_MODE_SG || ingenic_chan->mode == DMA_MODE_CYCLIC){
++		dmaengine_terminate_all(ingenic_chan->dma_chan);
++		pwm_dma_disable_hw(ingenic_pwm,channel);
++		dma_free_coherent(ingenic_pwm->chip.dev, BUFFER_SIZE,
++				ingenic_chan->buffer, ingenic_chan->buffer_dma);
++		if(ingenic_chan->mode == DMA_MODE_SG)
++			dma_unmap_sg(ingenic_pwm->chip.dev, ingenic_chan->sg, 1, DMA_TO_DEVICE);
++		pwm_dma_under_irq_disable(ingenic_pwm,channel);
++	}
++
++	if(ingenic_chan->trigger_en) {
++		pwm_store_disable(ingenic_pwm, channel);
++		pwm_trigger_negedge_disable(ingenic_pwm, channel);
++		pwm_trigger_posedge_disable(ingenic_pwm, channel);
++		pwm_store_disable_interrupt(ingenic_pwm, channel);
++		pwm_trigger_filter_set(ingenic_pwm, channel, 0);
++	}
++	pwm_disable_hw(ingenic_pwm, channel);
++
++	mutex_unlock(&ingenic_pwm->mutex);
++}
++
++
++static const struct pwm_ops ingenic_pwm_ops = {
++	.config = ingenic_pwm_config,
++	.enable = ingenic_pwm_enable,
++	.disable = ingenic_pwm_disable,
++	.owner = THIS_MODULE,
++};
++
++
++static ssize_t pwm_enable_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	return sprintf(buf, "0x%x", pwm_enable_status(ingenic_pwm));
++}
++
++static ssize_t pwm_enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	struct ingenic_pwm_chan *ingenic_chan = &ingenic_pwm->chan[ingenic_pwm->debug_current_id];
++	int enable;
++	const char *str = buf;
++	int ret_count = 0;
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count)
++			return count;
++	}
++	enable = simple_strtoul(str, (char **)&str, 10);
++
++	print_dbg("input enable value %d,current_id %d\n",enable,ingenic_pwm->debug_current_id);
++	if (enable) {
++		pwm_config(ingenic_pwm->debug_pwm[ingenic_pwm->debug_current_id],
++				ingenic_chan->duty_ns, ingenic_chan->period_ns);
++		pwm_enable(ingenic_pwm->debug_pwm[ingenic_pwm->debug_current_id]);
++	} else
++		pwm_disable(ingenic_pwm->debug_pwm[ingenic_pwm->debug_current_id]);
++	return count;
++}
++
++
++static ssize_t pwm_channel_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++
++	return sprintf(buf, "channel = %x", ingenic_pwm->debug_current_id);
++
++}
++
++static ssize_t pwm_channel_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	const char *str = buf;
++	int ret_count = 0;
++	int pwm_id = 0;
++	struct pwm_device *pwm = NULL;
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count)
++			return count;
++	}
++	pwm_id = simple_strtoul(str, (char **)&str, 10);
++	pwm = pwm_request(pwm_id, "pwm_request_test");
++	if (IS_ERR(pwm)) {
++		printk("unable to request pwm\n");
++		return -1;
++	}
++	ingenic_pwm->debug_pwm[pwm_id] = pwm;
++	ingenic_pwm->debug_current_id = pwm_id;
++	print_dbg("channel = %d\n", ingenic_pwm->debug_current_id);
++	return count;
++}
++
++static ssize_t pwm_free_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	const char *str = buf;
++	int ret_count = 0;
++	int pwm_id = 0;
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count)
++			return count;
++	}
++	pwm_id = simple_strtoul(str, (char **)&str, 10);
++
++	pwm_disable(ingenic_pwm->debug_pwm[pwm_id]);
++	pwm_put(ingenic_pwm->debug_pwm[pwm_id]);
++	ingenic_pwm->debug_pwm[pwm_id] = NULL;
++	return count;
++}
++
++static ssize_t pwm_show_requested_channel(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	int i = 0;
++	int ret = 0;
++
++	for (i = 0; i <INGENIC_PWM_NUM ; i++) {
++		if (ingenic_pwm->debug_pwm[i] == &(ingenic_pwm->chip.pwms[i]))
++			ret += sprintf(buf + ret, "ch: %02d requested\n", i);
++		else
++			ret += sprintf(buf + ret, "ch: %02d unrequested\n", i);
++	}
++	return ret;
++}
++
++static ssize_t pwm_duty_ns_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	struct ingenic_pwm_chan *ingenic_chan =
++		&ingenic_pwm->chan[ingenic_pwm->debug_current_id];
++
++	return sprintf(buf, "%d\n", ingenic_chan->duty_ns);
++}
++
++static ssize_t pwm_duty_ns_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	struct ingenic_pwm_chan *ingenic_chan =
++		&ingenic_pwm->chan[ingenic_pwm->debug_current_id];
++	const char *str = buf;
++	int ret_count = 0;
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count) {
++			dev_err(dev, "NO duty_ns config!\n");
++			return count;
++		}
++	}
++	ingenic_chan->duty_ns = simple_strtoul(str, (char **)&str, 10);
++
++	return count;
++}
++
++static ssize_t pwm_sg_pwm_num_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	struct ingenic_pwm_chan *ingenic_chan =
++		&ingenic_pwm->chan[ingenic_pwm->debug_current_id];
++
++	return sprintf(buf, "%d\n", ingenic_chan->sg_pwm_num);
++}
++
++static ssize_t pwm_sg_pwm_num_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	struct ingenic_pwm_chan *ingenic_chan =
++		&ingenic_pwm->chan[ingenic_pwm->debug_current_id];
++	const char *str = buf;
++	int ret_count = 0;
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count) {
++			dev_err(dev, "NO sg_pwm_num config!\n");
++			return count;
++		}
++	}
++	ingenic_chan->sg_pwm_num = simple_strtoul(str, (char **)&str, 10);
++
++	return count;
++}
++static ssize_t pwm_period_ns_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	struct ingenic_pwm_chan *ingenic_chan =
++		&ingenic_pwm->chan[ingenic_pwm->debug_current_id];
++
++	return sprintf(buf, "%d\n", ingenic_chan->period_ns);
++}
++
++static ssize_t pwm_period_ns_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	struct ingenic_pwm_chan *ingenic_chan =
++		&ingenic_pwm->chan[ingenic_pwm->debug_current_id];
++	const char *str = buf;
++	int ret_count = 0;
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count) {
++			dev_err(dev, "NO period_ns config!\n");
++			return count;
++		}
++	}
++	ingenic_chan->period_ns = simple_strtoul(str, (char **)&str, 10);
++
++	return count;
++}
++
++static ssize_t pwm_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	struct ingenic_pwm_chan *ingenic_chan =
++		&ingenic_pwm->chan[ingenic_pwm->debug_current_id];
++	int ret;
++
++	ret = sprintf(buf, "0 --> CPU mode, Continuous waveform.\n"
++			   "1 --> DMA mode,Specified number of waveforms.\n"
++			   "2 --> DMA mode,Continuous waveform.\n");
++	ret += sprintf(buf + ret, "current mode: %d\n", ingenic_chan->mode);
++	return ret;
++}
++
++static ssize_t pwm_mode_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	struct ingenic_pwm_chan *ingenic_chan =
++		&ingenic_pwm->chan[ingenic_pwm->debug_current_id];
++	const char *str = buf;
++	int ret_count = 0;
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count) {
++			dev_err(dev, "NO mode config!\n");
++			return count;
++		}
++	}
++	ingenic_chan->mode = simple_strtoul(str, (char **)&str, 10);
++
++	return count;
++}
++
++static ssize_t pwm_init_level_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	struct ingenic_pwm_chan *ingenic_chan =
++		&ingenic_pwm->chan[ingenic_pwm->debug_current_id];
++
++	return sprintf(buf, "%d\n", ingenic_chan->init_level);
++}
++
++static ssize_t pwm_init_level_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	struct ingenic_pwm_chan *ingenic_chan =
++		&ingenic_pwm->chan[ingenic_pwm->debug_current_id];
++	const char *str = buf;
++	int ret_count = 0;
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count) {
++			dev_err(dev, "NO init_level config!\n");
++			return count;
++		}
++	}
++	ingenic_chan->init_level = simple_strtoul(str, (char **)&str, 10);
++
++	return count;
++}
++
++static ssize_t pwm_finish_level_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	struct ingenic_pwm_chan *ingenic_chan =
++		&ingenic_pwm->chan[ingenic_pwm->debug_current_id];
++
++	return sprintf(buf, "%d\n", ingenic_chan->finish_level);
++}
++
++static ssize_t pwm_finish_level_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	struct ingenic_pwm_chan *ingenic_chan =
++		&ingenic_pwm->chan[ingenic_pwm->debug_current_id];
++	const char *str = buf;
++	int ret_count = 0;
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count) {
++			dev_err(dev, "NO finish_level config!\n");
++			return count;
++		}
++	}
++	ingenic_chan->finish_level = simple_strtoul(str, (char **)&str, 10);
++
++	return count;
++}
++
++static ssize_t pwm_trigger_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	struct ingenic_pwm_chan *ingenic_chan =
++		&ingenic_pwm->chan[ingenic_pwm->debug_current_id];
++
++	return sprintf(buf, "trigger_en:%d trigger_negedge:%d trigger_posedge:%d trigger_filter:%d\n",
++			ingenic_chan->trigger_en, ingenic_chan->trigger_negedge,
++			ingenic_chan->trigger_posedge, ingenic_chan->trigger_filter);
++}
++
++static ssize_t pwm_trigger_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct ingenic_pwm_chip *ingenic_pwm = dev_get_drvdata(dev);
++	struct ingenic_pwm_chan *ingenic_chan = &ingenic_pwm->chan[ingenic_pwm->debug_current_id];
++	const char *str = buf;
++	int ret_count = 0;
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count) {
++			dev_err(dev, "No trigger_en config!\n");
++			ingenic_chan->trigger_en = 0;
++			return count;
++		}
++	}
++	ingenic_chan->trigger_en = simple_strtoul(str, (char **)&str, 10);
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count) {
++			dev_err(dev, "No trigger_negedge config!\n");
++			return count;
++		}
++	}
++	ingenic_chan->trigger_negedge = simple_strtoul(str, (char **)&str, 10);
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count) {
++			dev_err(dev, "No trigger_posedge config!\n");
++			return count;
++		}
++	}
++	ingenic_chan->trigger_posedge = simple_strtoul(str, (char **)&str, 10);
++
++	while (!isxdigit(*str)) {
++		str++;
++		if(++ret_count >= count) {
++			dev_err(dev, "No trigger_filter config!\n");
++			return count;
++		}
++	}
++	ingenic_chan->trigger_filter = simple_strtoul(str, (char **)&str, 10);
++
++	return count;
++}
++
++
++static struct device_attribute pwm_device_attributes[] = {
++	__ATTR(request, S_IRUGO|S_IWUSR, pwm_channel_show, pwm_channel_store),
++	__ATTR(free, S_IWUSR, NULL, pwm_free_store),
++
++	__ATTR(duty_ns, S_IRUGO|S_IWUSR, pwm_duty_ns_show, pwm_duty_ns_store),
++	__ATTR(period_ns, S_IRUGO|S_IWUSR, pwm_period_ns_show, pwm_period_ns_store),
++	__ATTR(sg_pwm_num, S_IRUGO|S_IWUSR, pwm_sg_pwm_num_show, pwm_sg_pwm_num_store),
++	__ATTR(mode, S_IRUGO|S_IWUSR, pwm_mode_show, pwm_mode_store),
++	__ATTR(init_level, S_IRUGO|S_IWUSR, pwm_init_level_show, pwm_init_level_store),
++	__ATTR(finish_level, S_IRUGO|S_IWUSR, pwm_finish_level_show, pwm_finish_level_store),
++	__ATTR(trigger, S_IRUGO|S_IWUSR, pwm_trigger_show, pwm_trigger_store),
++	__ATTR(enable, S_IRUGO|S_IWUSR, pwm_enable_show, pwm_enable_store),
++
++	__ATTR(channels, S_IRUGO, pwm_show_requested_channel, NULL),
++};
++
++static bool pwm_dma_chan_filter(struct dma_chan *chan, void *param)
++{
++	struct ingenic_pwm_chan *pwm_chan = param;
++
++	return (INGENIC_DMA_REQ_PWM0_TX + pwm_chan->id) == (int)chan->private;
++}
++
++static irqreturn_t ingenic_pwm_interrupt(int irq, void *dev_id)
++{
++	unsigned int under_st, store_st;
++	struct ingenic_pwm_chip *ingenic_pwm = (struct ingenic_pwm_chip *)(dev_id);
++	int n;
++
++	under_st = pwm_dma_under_status(ingenic_pwm) & pwm_readl(ingenic_pwm,PWM_DFIE);
++
++	store_st = pwm_store_status(ingenic_pwm) & pwm_readl(ingenic_pwm,PWM_SIE);
++
++	if(store_st) {
++		n = ffs(store_st) - 1;
++		pwm_store_clear_status(ingenic_pwm, n);
++		ingenic_pwm->chan[n].store_irq_num++;
++		printk("%d %d %d %d\n",n ,pwm_get_store_num(ingenic_pwm, n),
++				pwm_get_output_num(ingenic_pwm, n), ingenic_pwm->chan[n].store_irq_num);
++		goto end;
++	}
++
++	if(under_st) {
++		n = ffs(under_st) - 1;
++		pwm_dma_clear_under(ingenic_pwm, n);
++		/* printk("pwm%d under come!\n", n); */
++		goto end;
++	}
++
++	printk("pwm irq entry, but not pwm valid irq!\n");
++end:
++	return IRQ_HANDLED;
++}
++
++static int ingenic_pwm_probe(struct platform_device *pdev)
++{
++	struct ingenic_pwm_chip *chip;
++	struct resource *res;
++	int err = 0;
++	int ret = 0;
++	int i = 0;
++
++	chip = devm_kzalloc(&pdev->dev,
++			sizeof(struct ingenic_pwm_chip), GFP_KERNEL);
++	if (!chip) {
++		pr_err("%s %d,malloc ingenic_pwm_chip error\n",
++				__func__, __LINE__);
++		return -ENOMEM;
++	}
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (res == NULL) {
++		dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
++		return  -ENOENT;
++	}
++
++	chip->irq = platform_get_irq(pdev, 0);
++	if(chip->irq < 0){
++		dev_err(&pdev->dev, "Cannot get %d  IORESOURCE_IRQ\n",chip->irq);
++		return  -ENOENT;
++	}
++
++	chip->iomem = ioremap(res->start, (res->end - res->start) + 1);
++	if (chip->iomem == NULL) {
++		dev_err(&pdev->dev, "Cannot map IO\n");
++		err = -ENXIO;
++		goto err_no_iomap;
++	}
++
++	chip->clk_gate = devm_clk_get(&pdev->dev, "gate_pwm");
++	if (IS_ERR(chip->clk_gate)) {
++		dev_err(&pdev->dev, "get pwm clk gate failed %ld\n", PTR_ERR(chip->clk_gate));
++		return PTR_ERR(chip->clk_gate);
++	}
++
++	chip->clk_pwm = devm_clk_get(&pdev->dev, "div_pwm");
++	if(IS_ERR(chip->clk_pwm)){
++		dev_err(&pdev->dev, "get pwm clk failed %ld\n", PTR_ERR(chip->clk_pwm));
++		return PTR_ERR(chip->clk_pwm);
++	}
++
++	if(chip->clk_gate) {
++		ret = clk_prepare_enable(chip->clk_gate);
++		if(ret) {
++			dev_err(&pdev->dev, "enable pwm clock gate failed!\n");
++		}
++	}
++
++	if(chip->clk_pwm) {
++		ret = clk_set_rate(chip->clk_pwm, DEFAULT_PWM_CLK_RATE);
++		if(ret) {
++			dev_err(&pdev->dev, "set pwm clock rate failed!\n");
++		}
++		ret = clk_prepare_enable(chip->clk_pwm);
++		if(ret) {
++			dev_err(&pdev->dev, "enable pwm clock failed!\n");
++		}
++	}
++
++	chip->chip.dev = &pdev->dev;
++	chip->chip.ops = &ingenic_pwm_ops;
++	chip->chip.base = 0;
++	chip->chip.npwm = INGENIC_PWM_NUM;
++	chip->phys = res->start;
++
++	ret = pwmchip_add(&chip->chip);
++	if (ret < 0) {
++		devm_kfree(&pdev->dev, chip);
++		return ret;
++	}
++
++	{
++		dma_cap_mask_t mask;
++		dma_cap_zero(mask);
++		dma_cap_set(DMA_SLAVE, mask);
++
++		for(i = 0; i < INGENIC_PWM_NUM; i++) {
++			chip->chan[i].id = i;
++			chip->chan[i].chip = chip;
++			char str[2] = "0";
++			sprintf(str, "%d", i);
++			chip->chan[i].dma_chan = dma_request_chan(&pdev->dev, str);
++			if(!chip->chan[i].dma_chan) {
++				dev_err(&pdev->dev, "PWM request dma tx channel failed");
++			}
++			chip->chan[i].sg = kmalloc(sizeof(struct scatterlist), GFP_KERNEL);
++			if (!chip->chan[i].sg) {
++				dev_err(&pdev->dev, "Failed to alloc tx scatterlist\n");
++			}
++			chip->chan[i].init_level = 0;
++			chip->chan[i].finish_level = 0;
++			chip->chan[i].trigger_en = 0;
++			chip->chan[i].sg_pwm_num = SG_PWM_NUM;
++		}
++	}
++
++	ret = request_irq(chip->irq,ingenic_pwm_interrupt,
++			IRQF_SHARED | IRQF_TRIGGER_LOW,"pwm-interrupt",chip);
++	if (ret) {
++		dev_err(&pdev->dev, "request_irq failed !! %d-\n",chip->irq);
++		goto err_no_iomap;
++	}
++
++	platform_set_drvdata(pdev, chip);
++	mutex_init(&chip->mutex);
++
++	for (i = 0; i < ARRAY_SIZE(pwm_device_attributes); i++) {
++		ret = device_create_file(&pdev->dev, &pwm_device_attributes[i]);
++		if (ret)
++			dev_warn(&pdev->dev, "attribute %d create failed", i);
++	}
++
++	dev_info(&pdev->dev, "ingenic-x1600 Probe of pwm success!\n");
++	return 0;
++
++err_no_iomap:
++	iounmap(chip->iomem);
++
++	return err;
++}
++
++static int ingenic_pwm_remove(struct platform_device *pdev)
++{
++	struct ingenic_pwm_chip *chip;
++	chip =platform_get_drvdata(pdev);
++	if (!chip)
++		return -ENODEV;
++
++	pwmchip_remove(&chip->chip);
++	devm_clk_put(&pdev->dev,chip->clk_pwm);
++	devm_clk_put(&pdev->dev,chip->clk_gate);
++	devm_kfree(&pdev->dev, chip);
++	return 0;
++}
++
++static const struct of_device_id ingenic_pwm_matches[] = {
++	{ .compatible = "ingenic,x1600-pwm", .data = NULL },
++	{},
++};
++
++#ifdef CONFIG_PM_SLEEP
++static int ingenic_pwm_suspend(struct device *dev)
++{
++	struct ingenic_pwm_chip *chip = dev_get_drvdata(dev);
++	unsigned int i;
++
++	/*
++	 * No one preserves these values during suspend so reset them.
++	 * Otherwise driver leaves PWM unconfigured if same values are
++	 * passed to pwm_config() next time.
++	 */
++	for (i = 0; i < INGENIC_PWM_NUM; ++i) {
++		struct pwm_device *pwm = &chip->chip.pwms[i];
++		struct ingenic_pwm_channel *chan = pwm_get_chip_data(pwm);
++
++		if (!chan)
++			continue;
++		chan->period_ns = 0;
++		chan->duty_ns = 0;
++	}
++
++	return 0;
++}
++
++static int ingenic_pwm_resume(struct device *dev)
++{
++	struct ingenic_pwm_chip *chip = dev_get_drvdata(dev);
++	unsigned int chan;
++
++	/*
++	 * Inverter setting must be preserved across suspend/resume
++	 * as nobody really seems to configure it more than once.
++	 */
++	for (chan = 0; chan < INGENIC_PWM_NUM; ++chan) {
++		if (chip->output_mask & BIT(chan)) {
++			/*TODO: ??*/
++		}
++	}
++	return 0;
++}
++#endif
++
++static SIMPLE_DEV_PM_OPS(ingenic_pwm_pm_ops, ingenic_pwm_suspend, ingenic_pwm_resume);
++
++static struct platform_driver ingenic_pwm_driver = {
++	.driver = {
++		.name = "ingenic-pwm",
++		.pm = &ingenic_pwm_pm_ops,
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(ingenic_pwm_matches),
++	},
++	.probe = ingenic_pwm_probe,
++	.remove = ingenic_pwm_remove,
++};
++module_platform_driver(ingenic_pwm_driver);
++
++MODULE_DESCRIPTION("Ingenic SoC PWM driver");
++MODULE_ALIAS("platform:ingenic-pwm");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/pwm/pwm-ingenic.c b/module_drivers/drivers/pwm/pwm-ingenic.c
+new file mode 100644
+index 000000000..ecf541d07
+--- /dev/null
++++ b/module_drivers/drivers/pwm/pwm-ingenic.c
+@@ -0,0 +1,495 @@
++/*
++ * Copyright (c) 2007 Ben Dooks
++ * Copyright (c) 2008 Simtec Electronics
++ *     Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
++ * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
++ *
++ * PWM driver for Samsung SoCs
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License.
++ */
++
++#include <linux/bitops.h>
++#include <linux/clk.h>
++#include <linux/export.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pwm.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/time.h>
++
++#include <linux/mfd/core.h>
++
++#ifdef CONFIG_SOC_X2500
++#include <linux/mfd/ingenic-tcu_v1.h>
++#else
++#include <linux/mfd/ingenic-tcu.h>
++#endif
++/**
++ * struct ingenic_pwm_channel - private data of PWM channel
++ * @period_ns:	current period in nanoseconds programmed to the hardware
++ * @duty_ns:	current duty time in nanoseconds programmed to the hardware
++ */
++struct ingenic_pwm_channel {
++	struct ingenic_tcu_chn *chan;
++	u32 period_ns;
++	u32 duty_ns;
++};
++
++/**
++ * struct ingenic_pwm_chip - private data of PWM chip
++ * @chip:		generic PWM chip
++ * @rtc_clk:		external RTC clock(can be ERR_PTR if not present)
++ * @ext_clk:		external EXT clock(can be ERR_PTR if not present)
++ * @output_mask:	output status for all channels - one bit per channel
++ */
++struct ingenic_pwm_chip {
++	struct pwm_chip chip;
++	struct clk *rtc_clk;
++	struct clk *ext_clk;
++	u32 output_mask;
++};
++
++static inline
++struct ingenic_pwm_chip *to_ingenic_pwm_chip(struct pwm_chip *chip)
++{
++	return container_of(chip, struct ingenic_pwm_chip, chip);
++}
++static inline
++struct ingenic_tcu_chn *to_ingenic_tcu_channel(struct pwm_device *pwm)
++{
++	return ((struct ingenic_pwm_channel *)pwm_get_chip_data(pwm))->chan;
++}
++
++static int pwm_get_period_num(struct ingenic_pwm_chip *chip,
++							  struct ingenic_tcu_chn *tcu_chan, int period_ns)
++{
++	unsigned long long rate;
++	unsigned long long tmp;
++	int div = 0;
++	int period = 0;
++
++	if(tcu_chan->clk_src == TCU_CLKSRC_EXT) {
++		rate = (unsigned long long)clk_get_rate(chip->ext_clk);
++	} else if(tcu_chan->clk_src == TCU_CLKSRC_RTC) {
++		rate = (unsigned long long)clk_get_rate(chip->ext_clk);
++	} else {
++		printk("not support clk soruce\n");
++		return -EINVAL;
++	}
++
++	tmp =  rate * period_ns;
++	do_div(tmp, 1000000000);
++	period = tmp;
++
++	while (period > 0xffff && div < 6) {
++		period >>= 2;
++		++div;
++	}
++
++	if (div == 6)
++		return -EINVAL;
++
++	tcu_chan->full_num = period;
++	tcu_chan->clk_div = div;
++	return period;
++}
++static int pwm_ingenic_get_period(struct ingenic_pwm_chip *chip,
++								  struct pwm_device *pwm, int period_ns)
++{
++		struct ingenic_tcu_chn *tcu_chan;
++		int period;
++
++		tcu_chan = to_ingenic_tcu_channel(pwm);
++		/*
++		 * Compare minimum PWM frequency that can be achieved with possible
++		 * divider settings and choose the lowest divisor that can generate
++		 * frequencies lower than requested.
++		 */
++		tcu_chan->clk_src = TCU_CLKSRC_EXT;
++		period = pwm_get_period_num(chip, tcu_chan, period_ns);
++		if(period < 0) {
++			tcu_chan->clk_src = TCU_CLKSRC_RTC;
++			period = pwm_get_period_num(chip, tcu_chan, period_ns);
++			if(period < 0) {
++				dev_err(chip->chip.dev,"can not find right div\n");
++			}
++		}
++
++		return period;
++}
++
++static int pwm_ingenic_request(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++	struct ingenic_pwm_chip *our_chip = to_ingenic_pwm_chip(chip);
++	struct ingenic_pwm_channel *our_chan;
++	struct mfd_cell *cell;
++
++	if (!(our_chip->output_mask & BIT(pwm->hwpwm))) {
++		dev_warn(chip->dev,
++				 "tried to request PWM channel %d without output\n",
++				 pwm->hwpwm);
++		return -EINVAL;
++	}
++
++	cell = request_cell(pwm->hwpwm);
++	if(!cell){
++		dev_err(chip->dev, "tried to request tcu channel %d busy\n",
++				 pwm->hwpwm);
++		return -EINVAL;
++	}
++
++	our_chan = devm_kzalloc(chip->dev, sizeof(*our_chan), GFP_KERNEL);
++	if (!our_chan)
++		return -ENOMEM;
++
++	our_chan->chan = cell->platform_data;
++	our_chan->chan->enable(cell->id);
++
++	pwm_set_chip_data(pwm, our_chan);
++
++	return 0;
++}
++
++static void pwm_ingenic_free(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++	struct ingenic_pwm_channel *our_chan;
++	int id;
++
++	our_chan = pwm_get_chip_data(pwm);
++
++	id = pwm->hwpwm;
++	our_chan->chan->disable(id);
++	free_cell(id);
++	devm_kfree(chip->dev, our_chan);
++	pwm_set_chip_data(pwm, NULL);
++}
++
++static int pwm_ingenic_enable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++	struct ingenic_tcu_chn *tcu_chan;
++	tcu_chan = to_ingenic_tcu_channel(pwm);
++	ingenic_tcu_counter_begin(tcu_chan);
++
++	return 0;
++}
++
++static void pwm_ingenic_disable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++	struct ingenic_tcu_chn *tcu_chan;
++	tcu_chan = to_ingenic_tcu_channel(pwm);
++	ingenic_tcu_counter_stop(tcu_chan);
++}
++
++static int pwm_ingenic_config(struct pwm_chip *chip, struct pwm_device *pwm,
++							  int duty_ns, int period_ns)
++{
++	struct ingenic_pwm_chip *our_chip = to_ingenic_pwm_chip(chip);
++	struct ingenic_pwm_channel *our_chan = pwm_get_chip_data(pwm);
++	struct ingenic_tcu_chn *tcu_chan = our_chan->chan;
++	u16 tfull = tcu_chan->full_num, thalf;
++
++	/*
++	 * We currently avoid using 64bit arithmetic by using the
++	 * fact that anything faster than 1Hz is easily representable
++	 * by 32bits.
++	 */
++	if (period_ns > NSEC_PER_SEC)
++		return -ERANGE;
++
++	if (period_ns == our_chan->period_ns && duty_ns == our_chan->duty_ns)
++		return 0;
++
++	/* Check to see if we are changing the clock rate of the PWM. */
++	if (our_chan->period_ns != period_ns) {
++		int period;
++
++		period = pwm_ingenic_get_period(our_chip, pwm, period_ns);
++		dev_dbg(our_chip->chip.dev, "duty_ns=%d, period_ns=%d (%u)\n",
++				duty_ns, period_ns, period);
++		if(period < 0)
++			return -ERANGE;
++		tfull = period;
++	}
++	/* Period is too short. */
++	if (tfull <= 1)
++		return -ERANGE;
++
++	/* Note that counters count down. */
++	{
++		unsigned long long tmp;
++		tmp = (unsigned long long)tfull * duty_ns;
++		do_div(tmp, period_ns);
++		thalf = tmp;
++	}
++
++	/* 0% duty is not available */
++	if (!thalf)
++		++thalf;
++
++	thalf = tfull - thalf;
++	if(!thalf){
++		/* set pwm output 1 */
++	}
++
++	dev_info(our_chip->chip.dev,
++			 "thalf=%u/%u\n", thalf, tfull);
++
++	tcu_chan->irq_type = NULL_IRQ_MODE;
++	tcu_chan->is_pwm = 1;
++	tcu_chan->full_num = tfull;
++	tcu_chan->half_num = thalf;
++	tcu_chan->shutdown_mode = 0;
++
++	ingenic_tcu_config(tcu_chan);
++
++	our_chan->period_ns = period_ns;
++	our_chan->duty_ns = duty_ns;
++
++	return 0;
++}
++
++static int pwm_ingenic_set_polarity(struct pwm_chip *chip,
++									struct pwm_device *pwm,
++									enum pwm_polarity polarity)
++{
++	struct ingenic_tcu_chn *tcu_chan;
++	bool invert = (polarity == PWM_POLARITY_NORMAL);
++
++	tcu_chan = to_ingenic_tcu_channel(pwm);
++	if (invert) {
++		tcu_chan->init_level = 1;
++	} else {
++		tcu_chan->init_level = 0;
++	}
++
++	return 0;
++}
++
++static const struct pwm_ops pwm_ingenic_ops = {
++	.request	= pwm_ingenic_request,
++	.free		= pwm_ingenic_free,
++	.enable		= pwm_ingenic_enable,
++	.disable	= pwm_ingenic_disable,
++	.config		= pwm_ingenic_config,
++	.set_polarity	= pwm_ingenic_set_polarity,
++	.owner		= THIS_MODULE,
++};
++
++#ifdef CONFIG_OF
++/**
++ * of_irq_find_parent - Given a device node, find its interrupt parent node
++ * @child: pointer to device node
++ *
++ * Returns a pointer to the interrupt parent node, or NULL if the interrupt
++ * parent could not be determined.
++ */
++struct device_node *of_pwm_find_parent(struct device_node *child)
++{
++	struct device_node *p;
++	const __be32 *parp;
++
++	if (!of_node_get(child))
++		return NULL;
++
++	do {
++		parp = of_get_property(child, "ingenic,timer-parent", NULL);
++		if (parp == NULL)
++			p = of_get_parent(child);
++		else {
++			p = of_find_node_by_phandle(be32_to_cpup(parp));
++		}
++		of_node_put(child);
++	} while (!p);
++
++	return p;
++}
++
++static void pwm_ingenic_parse_dt(struct ingenic_pwm_chip *chip)
++{
++	struct device_node *np = chip->chip.dev->of_node;
++	struct device_node *child, *parent;
++	int enable_pwm_num = 0;
++
++	for_each_child_of_node(np, child) {
++		const char *status;
++		parent = of_pwm_find_parent(child);
++		of_property_read_string(child, "status", &status);
++
++		if(!strcmp(status, "okay") ){
++			unsigned int info, id;
++			of_property_read_u32(parent, "ingenic,channel-info", &info);
++			id = info & (CHANNEL_BASE_OFF*2 - 1);
++			chip->output_mask |= BIT(id);
++			enable_pwm_num ++;
++		}
++	}
++	chip->chip.of_pwm_n_cells = enable_pwm_num;
++}
++static const struct of_device_id ingenic_pwm_matches[] = {
++	{ .compatible = "ingenic,pwm", .data = NULL },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ingenic_pwm_matches);
++#else
++static int pwm_ingenic_parse_dt(struct ingenic_pwm_chip *chip)
++{
++	return -ENODEV;
++}
++#endif
++
++static int pwm_ingenic_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct ingenic_pwm_chip *chip;
++	struct device_node *np;
++	unsigned int pwmnum;
++	int ret = 0;
++
++	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
++	if (chip == NULL)
++		return -ENOMEM;
++
++	np = pdev->dev.of_node;
++	pwmnum = of_get_child_count(np);
++	chip->chip.dev = &pdev->dev;
++	chip->chip.dev->of_node = np;
++	chip->chip.ops = &pwm_ingenic_ops;
++	chip->chip.base = -1;
++	chip->chip.npwm = pwmnum;
++
++	if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
++		pwm_ingenic_parse_dt(chip);
++		/* chip->chip.of_xlate = of_pwm_xlate_with_flags; */
++	} else {
++		if (!pdev->dev.platform_data) {
++			dev_err(&pdev->dev, "no platform data specified\n");
++			return -EINVAL;
++		}
++	}
++
++	chip->ext_clk = devm_clk_get(&pdev->dev, "ext");
++#ifdef CONFIG_SOC_X2500
++	chip->rtc_clk = devm_clk_get(&pdev->dev, "rtc_ext");
++#else
++	chip->rtc_clk = devm_clk_get(&pdev->dev, "rtc");
++#endif
++	if (IS_ERR(chip->ext_clk) || IS_ERR(chip->rtc_clk)) {
++		dev_err(dev, "failed to get timer base clk\n");
++		return -EINVAL;
++	}
++
++	platform_set_drvdata(pdev, chip);
++
++	ret = pwmchip_add(&chip->chip);
++	if (ret < 0) {
++		dev_err(dev, "failed to register PWM chip\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static int pwm_ingenic_remove(struct platform_device *pdev)
++{
++	struct ingenic_pwm_chip *chip = platform_get_drvdata(pdev);
++	int ret;
++
++	ret = pwmchip_remove(&chip->chip);
++	if (ret < 0)
++		return ret;
++
++	clk_disable_unprepare(chip->ext_clk);
++	clk_disable_unprepare(chip->rtc_clk);
++
++	return 0;
++}
++
++
++#ifdef CONFIG_PM_SLEEP
++static int pwm_ingenic_suspend(struct device *dev)
++{
++	struct ingenic_pwm_chip *chip = dev_get_drvdata(dev);
++	unsigned int i;
++
++	/*
++	 * No one preserves these values during suspend so reset them.
++	 * Otherwise driver leaves PWM unconfigured if same values are
++	 * passed to pwm_config() next time.
++	 */
++	for (i = 0; i < chip->chip.npwm; ++i) {
++		struct pwm_device *pwm = &chip->chip.pwms[i];
++		struct ingenic_pwm_channel *chan = pwm_get_chip_data(pwm);
++		int id;
++		if (!chan)
++			continue;
++
++		id = pwm->hwpwm;
++		chan->chan->disable(id);
++	}
++
++	return 0;
++}
++
++static int pwm_ingenic_resume(struct device *dev)
++{
++	struct ingenic_pwm_chip *chip = dev_get_drvdata(dev);
++	unsigned int chan;
++
++	/*
++	 * Inverter setting must be preserved across suspend/resume
++	 * as nobody really seems to configure it more than once.
++	 */
++	for (chan = 0; chan < chip->chip.npwm; ++chan) {
++		if (chip->output_mask & BIT(chan)) {
++			struct pwm_device *pwm = &chip->chip.pwms[chan];
++			struct ingenic_pwm_channel *chan = pwm_get_chip_data(pwm);
++			int id;
++			if (!chan)
++				continue;
++
++			id = pwm->hwpwm;
++			chan->chan->enable(id);
++		}
++	}
++
++	return 0;
++}
++#endif
++
++static SIMPLE_DEV_PM_OPS(pwm_ingenic_pm_ops, pwm_ingenic_suspend,
++						 pwm_ingenic_resume);
++
++static struct platform_driver pwm_ingenic_driver = {
++	.driver		= {
++		.name	= "ingenic,pwm",
++		.pm	= &pwm_ingenic_pm_ops,
++		.of_match_table = of_match_ptr(ingenic_pwm_matches),
++	},
++	.probe		= pwm_ingenic_probe,
++	.remove		= pwm_ingenic_remove,
++};
++
++static int __init ingenic_pwm_init(void)
++{
++	return platform_driver_register(&pwm_ingenic_driver);
++}
++
++static void __exit ingenic_pwm_exit(void)
++{
++	platform_driver_unregister(&pwm_ingenic_driver);
++}
++
++device_initcall_sync(ingenic_pwm_init);
++module_exit(ingenic_pwm_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("bo.liu <bo.liu@ingenic.com>");
++MODULE_ALIAS("platform:ingenic-pwm");
+diff --git a/module_drivers/drivers/rtc/Kconfig b/module_drivers/drivers/rtc/Kconfig
+new file mode 100644
+index 000000000..d25948f7c
+--- /dev/null
++++ b/module_drivers/drivers/rtc/Kconfig
+@@ -0,0 +1,22 @@
++config RTC_DRV_INGENIC
++    tristate "INGENIC RTC"
++            help
++            If you say Y here you will get access to the real time clock
++              built into your INGENIC CPU.
++
++              To compile this driver as a module, choose M here: the
++	      module will be called rtc-ingenic.
++
++config SUSPEND_TEST
++	  bool "Ingenic RTC suspend test"
++	  depends on RTC_DRV_INGENIC
++	  help
++	  If you say yes here the Ingenic rtc will support suspend test.
++
++config SUSPEND_ALARM_TIME
++	  int "Ingenic RTC suspend alarm time Unit of second"
++	  depends on SUSPEND_TEST
++	  default "60"
++	  help
++	  If you say yes here Automatically wake up after a set time of sleep.
++
+diff --git a/module_drivers/drivers/rtc/Makefile b/module_drivers/drivers/rtc/Makefile
+new file mode 100644
+index 000000000..ffdd88c79
+--- /dev/null
++++ b/module_drivers/drivers/rtc/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_RTC_DRV_INGENIC)   += rtc-ingenic.o
+diff --git a/module_drivers/drivers/rtc/rtc-ingenic.c b/module_drivers/drivers/rtc/rtc-ingenic.c
+new file mode 100644
+index 000000000..43377d1bb
+--- /dev/null
++++ b/module_drivers/drivers/rtc/rtc-ingenic.c
+@@ -0,0 +1,644 @@
++/* drivers/rtc/rtc-ingenic_.c
++ *
++ * Real Time Clock interface for Ingenic's SOC, such as ingenic_x2000_v2.
++ *
++ *
++ * Copyright (C) 2015 Ingenic Semiconductor Co., Ltd.
++ *	http://www.ingenic.com
++ * Author:	Wang Chengwan<cwwang@ingenic.cn>
++ *		Aaron Wang<hfwang@ingenic.cn>
++ *		Sun Jiwei <jiwei.sun@ingenic.com>
++ *		wssong <wenshuo.song@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/rtc.h>
++#include <linux/init.h>
++#include <linux/fs.h>
++#include <linux/interrupt.h>
++#include <linux/string.h>
++#include <linux/clk.h>
++#include <linux/bitops.h>
++#include <linux/pm.h>
++
++#include "rtc-ingenic.h"
++
++/*FIXME by wssong,it should in board info*/
++/* Default time for the first-time power on */
++static struct rtc_time default_tm = {
++	.tm_year = (2020 - 1900),	// year 2019
++	.tm_mon = (3 - 1),		// month 3
++	.tm_mday = 1,			// day 1
++	.tm_hour = 12,
++	.tm_min = 0,
++	.tm_sec = 0
++};
++
++static inline int rtc_periodic_alarm(struct rtc_time *tm)
++{
++	return  (tm->tm_year == -1) ||
++		((unsigned)tm->tm_mon >= 12) ||
++		((unsigned)(tm->tm_mday - 1) >= 31) ||
++		((unsigned)tm->tm_hour > 23) ||
++		((unsigned)tm->tm_min > 59) ||
++		((unsigned)tm->tm_sec > 59);
++}
++
++static unsigned int ingenic_rtc_readl(struct ingenic_rtc *dev,int offset)
++{
++	unsigned int data, timeout = 0x100000;
++	do {
++		data = readl(dev->iomem + offset);
++	} while (readl(dev->iomem + offset) != data && timeout--);
++	if (timeout <= 0)
++		pr_info("RTC : rtc_read_reg timeout!\n");
++	return data;
++}
++
++static inline void wait_write_ready(struct ingenic_rtc *dev)
++{
++	int timeout = 0x100000;
++	while (!(ingenic_rtc_readl(dev,RTC_RTCCR) & RTCCR_WRDY) && timeout--);
++	if (timeout <= 0){
++		pr_info("RTC : %s timeout!\n",__func__);
++	}
++}
++
++static void ingenic_rtc_writel(struct ingenic_rtc *dev,int offset, unsigned int value)
++{
++
++	int timeout = 0x100000;
++	mutex_lock(&dev->mutex_wr_lock);
++	wait_write_ready(dev);
++	writel(WENR_WENPAT_WRITABLE, dev->iomem + RTC_WENR);
++	wait_write_ready(dev);
++	while (!(ingenic_rtc_readl(dev,RTC_WENR) & WENR_WEN) && timeout--);
++	if (timeout <= 0){
++		pr_info("RTC :  wait_writable timeout!\n");
++	}
++	wait_write_ready(dev);
++	writel(value,dev->iomem + offset);
++	wait_write_ready(dev);
++	mutex_unlock(&dev->mutex_wr_lock);
++}
++
++static inline void ingenic_rtc_clrl(struct ingenic_rtc *dev,int offset, unsigned int value)
++{
++	ingenic_rtc_writel(dev, offset, ingenic_rtc_readl(dev,offset) & ~(value));
++}
++
++static inline void ingenic_rtc_setl(struct ingenic_rtc *dev,int offset, unsigned int value)
++{
++	ingenic_rtc_writel(dev,offset,ingenic_rtc_readl(dev,offset) | (value));
++}
++
++#define IS_RTC_IRQ(x,y)  (((x) & (y)) == (y))
++
++#ifndef RTC_DBUG_DUMP
++static void ingenic_rtc_dump(struct ingenic_rtc *dev)
++{
++	printk ("******************************ingenic_rtc_dump**********************\n\n");
++	printk ("ingenic_rtc_dump-----RTC_RTCCR is --%08x--\n",ingenic_rtc_readl(dev, RTC_RTCCR));
++	printk ("ingenic_rtc_dump-----RTC_RTCSR is --%08x--\n",ingenic_rtc_readl(dev, RTC_RTCSR));
++	printk ("ingenic_rtc_dump-----RTC_RTCSAR is --%08x--\n",ingenic_rtc_readl(dev,RTC_RTCSAR));
++	printk ("ingenic_rtc_dump-----RTC_RTCGR is --%08x--\n",ingenic_rtc_readl(dev, RTC_RTCGR));
++	printk ("ingenic_rtc_dump-----RTC_HCR is --%08x--\n",ingenic_rtc_readl(dev, RTC_HCR));
++	printk ("ingenic_rtc_dump-----RTC_HWFCR is --%08x--\n",ingenic_rtc_readl(dev, RTC_HWFCR));
++	printk ("ingenic_rtc_dump-----RTC_HRCR is --%08x--\n",ingenic_rtc_readl(dev, RTC_HRCR));
++	printk ("ingenic_rtc_dump-----RTC_HWCR is --%08x--\n",ingenic_rtc_readl(dev, RTC_HWCR));
++	printk ("ingenic_rtc_dump-----RTC_HWRSR is --%08x--\n",ingenic_rtc_readl(dev,RTC_HWRSR));
++	printk ("ingenic_rtc_dump-----RTC_HSPR is --%08x--\n",ingenic_rtc_readl(dev, RTC_HSPR));
++	printk ("ingenic_rtc_dump-----RTC_WENR is --%08x--\n",ingenic_rtc_readl(dev, RTC_WENR));
++	printk ("ingenic_rtc_dump-----RTC_WKUPPINCR is --%08x--\n",ingenic_rtc_readl(dev,RTC_WKUPPINCR));
++	printk ("***************************ingenic_rtc_dump***************************\n");
++
++	return;
++}
++#endif
++
++static void ingenic_rtc_irq_work(struct work_struct *work)
++{
++
++	unsigned int rtsr,save_rtsr;
++	unsigned long events;
++	struct ingenic_rtc *rtc =  container_of(work, struct ingenic_rtc, work);
++
++	rtsr = ingenic_rtc_readl(rtc, RTC_RTCCR);
++	save_rtsr = rtsr;
++	//is rtc interrupt
++	events = 0;
++	if (IS_RTC_IRQ(rtsr,RTCCR_AF)) {
++
++		events = RTC_AF | RTC_IRQF;
++		rtsr &= ~RTCCR_AF;
++
++		if (rtc_periodic_alarm(&rtc->rtc_alarm) == 0)
++			rtsr &= ~(RTCCR_AIE | RTCCR_AE);
++	}
++
++	if (IS_RTC_IRQ(rtsr,RTCCR_1HZ)) {
++		rtsr &= ~(RTCCR_1HZ | RTCCR_1HZIE); //Turn off interrupt after triggering interrupt
++		events = RTC_UF | RTC_IRQF;
++	}
++
++	if(events != 0)
++		rtc_update_irq(rtc->rtc, 1, events);
++
++	if(rtsr != save_rtsr)
++		ingenic_rtc_writel(rtc, RTC_RTCCR,rtsr);
++
++	enable_irq(rtc->irq);
++
++	return;
++}
++
++static irqreturn_t ingenic_rtc_interrupt(int irq, void *dev_id)
++{
++	struct ingenic_rtc *rtc = (struct ingenic_rtc *) (dev_id);
++	disable_irq_nosync(rtc->irq);
++	schedule_work(&rtc->work);
++	return IRQ_HANDLED;
++}
++
++/*add by wssong for rtc x2000 at 2019-07-06 begin*/
++static void enter_hib_mode(struct ingenic_rtc *rtc)
++{
++	ingenic_rtc_setl(rtc,RTC_RTCCR,RTCCR_AE);
++	ingenic_rtc_setl(rtc,RTC_HWCR,HWCR_EALM);
++	ingenic_rtc_setl(rtc,RTC_HCR,HCR_PD);
++}
++
++static void wkuppincr_on(struct ingenic_rtc *rtc)
++{
++	ingenic_rtc_setl(rtc,RTC_WKUPPINCR,WKUPPINCR_BUFFEREN | WKUPPINCR_FASTBOOT
++			| WKUPPINCR_RAMSLEEP | WKUPPINCR_RAMSHUT);
++}
++
++static void wkuppincr_off(struct ingenic_rtc *rtc)
++{
++	ingenic_rtc_clrl(rtc,RTC_WKUPPINCR,WKUPPINCR_BUFFEREN | WKUPPINCR_FASTBOOT
++			| WKUPPINCR_RAMSLEEP | WKUPPINCR_RAMSHUT);
++}
++
++static void  set_1hzie_on(struct ingenic_rtc *rtc)
++{
++	ingenic_rtc_setl(rtc,RTC_RTCCR,RTCCR_1HZIE);
++}
++
++static void set_1hzie_off(struct ingenic_rtc *rtc)
++{
++	ingenic_rtc_clrl(rtc,RTC_RTCCR,RTCCR_1HZIE);
++}
++
++static void set_extend_press_reset_en(struct ingenic_rtc *rtc)
++{
++	ingenic_rtc_clrl(rtc,RTC_WKUPPINCR,WKUPPINCR_P_RST_CLEAR);
++	ingenic_rtc_setl(rtc,RTC_WKUPPINCR,WKUPPINCR_P_RST_EN);
++}
++
++static void set_extend_press_reset_off(struct ingenic_rtc *rtc)
++{
++	ingenic_rtc_setl(rtc,RTC_WKUPPINCR,WKUPPINCR_P_RST_EN_DEF);
++}
++
++/*add by wssong for rtc x2000 at 2019-07-06 end*/
++
++static int ingenic_rtc_ioctl(struct device *dev, unsigned int cmd,
++		unsigned long arg)
++{
++	struct ingenic_rtc *rtc = dev_get_drvdata(dev);
++	switch (cmd) {
++		case SET_PD_STEP:
++			enter_hib_mode(rtc);
++			break;
++		case SET_DDRBUFER_EN:
++			wkuppincr_on(rtc);
++			break;
++		case SET_DDRBUFER_DISEN:
++			wkuppincr_off(rtc);
++			break;
++		case SET_RTCCR_1HZIE_ON:
++			set_1hzie_on(rtc);
++			break;
++		case SET_RTCCR_1HZIE_OFF:
++			set_1hzie_off(rtc);
++			break;
++		case SET_WKUPPINCR_P_RST_EN:
++			set_extend_press_reset_en(rtc);
++			break;
++		case SET_WKUPPINCR_P_RST_OFF:
++			set_extend_press_reset_off(rtc);
++			break;
++		case PRINT_INFO:
++			ingenic_rtc_dump(rtc);
++			break;
++		default:
++			return 0;
++	}
++	return 0;
++}
++
++static int ingenic_rtc_set_time(struct device *dev, struct rtc_time *tm)
++{
++	struct ingenic_rtc *rtc = NULL;
++	unsigned long time = 0;
++	int ret = -1;
++
++	if (dev) {
++		rtc = dev_get_drvdata(dev);
++	} else {
++		return ret;
++	}
++
++	time = rtc_tm_to_time64(tm);
++	if (time)
++		ingenic_rtc_writel(rtc, RTC_RTCSR, time);
++	return 0;
++}
++
++static int ingenic_rtc_read_time(struct device *dev, struct rtc_time *tm)
++{
++	unsigned int tmp;
++	struct ingenic_rtc *rtc = dev_get_drvdata(dev);
++
++	tmp = ingenic_rtc_readl(rtc, RTC_RTCSR);
++	rtc_time64_to_tm(tmp, tm);
++
++	if (rtc_valid_tm(tm) < 0) {
++		/* Set the default time */
++		ingenic_rtc_set_time(dev, &default_tm);
++		tmp = ingenic_rtc_readl(rtc, RTC_RTCSR);
++		rtc_time64_to_tm(tmp, tm);
++	}
++
++	return 0;
++}
++
++static int ingenic_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
++{
++	unsigned int rtc_rcr,tmp;
++	struct ingenic_rtc *rtc = dev_get_drvdata(dev);
++
++	tmp = ingenic_rtc_readl(rtc, RTC_RTCSAR);
++	rtc_time64_to_tm(tmp, &rtc->rtc_alarm);
++	memcpy(&alrm->time, &rtc->rtc_alarm, sizeof(struct rtc_time));
++	rtc_rcr = ingenic_rtc_readl(rtc, RTC_RTCCR);
++	alrm->enabled = (rtc_rcr & RTCCR_AIE) ? 1 : 0;
++	alrm->pending = (rtc_rcr & RTCCR_AF) ? 1 : 0;
++	return 0;
++}
++
++static int ingenic_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
++{
++	int ret = 0;
++	unsigned long time;
++	unsigned int tmp;
++	struct ingenic_rtc *rtc = dev_get_drvdata(dev);
++
++	mutex_lock(&rtc->mutexlock);
++	if (alrm->enabled) {
++		pr_debug("Next alarm year:%d, mon:%d, day:%d, "
++				"hour:%d, min:%d, sec:%d\n",
++				alrm->time.tm_year, alrm->time.tm_mon,
++				alrm->time.tm_mday, alrm->time.tm_hour,
++				alrm->time.tm_min, alrm->time.tm_sec);
++		time = rtc_tm_to_time64(&alrm->time);
++		ingenic_rtc_writel(rtc, RTC_RTCSAR, time);
++		tmp = ingenic_rtc_readl(rtc, RTC_RTCCR);
++		tmp &= ~RTCCR_AF;
++		tmp |= RTCCR_AIE | RTCCR_AE;
++		ingenic_rtc_writel(rtc, RTC_RTCCR, tmp);
++	} else {
++		ingenic_rtc_clrl(rtc,RTC_RTCCR, RTCCR_AIE | RTCCR_AE | RTCCR_AF);
++	}
++	mutex_unlock(&rtc->mutexlock);
++
++	return ret;
++}
++
++static int ingenic_rtc_proc(struct device *dev, struct seq_file *seq)
++{
++	struct ingenic_rtc *rtc = dev_get_drvdata(dev);
++	seq_printf(seq, "RTC regulator\t: 0x%08x\n",
++			ingenic_rtc_readl(rtc, RTC_RTCGR));
++	seq_printf(seq, "update_IRQ\t: %s\n",
++			(ingenic_rtc_readl(rtc, RTC_RTCCR) & RTCCR_1HZIE) ? "yes" : "no");
++
++	return 0;
++}
++
++static int ingenic_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
++{
++	struct ingenic_rtc *rtc = dev_get_drvdata(dev);
++	unsigned int tmp;
++
++	mutex_lock(&rtc->mutexlock);
++	if (enabled) {
++		ingenic_rtc_clrl(rtc,RTC_RTCCR, RTCCR_AIE | RTCCR_AE | RTCCR_AF);
++		tmp = ingenic_rtc_readl(rtc, RTC_RTCCR);
++		tmp &= ~RTCCR_AF;
++		tmp |= RTCCR_AIE | RTCCR_AE;
++		ingenic_rtc_writel(rtc, RTC_RTCCR, tmp);
++	} else {
++		tmp = ingenic_rtc_readl(rtc, RTC_RTCCR);
++		tmp &= ~(RTCCR_AF | RTCCR_AE | RTCCR_AIE);
++		ingenic_rtc_writel(rtc, RTC_RTCCR, tmp);
++	}
++	mutex_unlock(&rtc->mutexlock);
++	return 0;
++}
++
++static const struct rtc_class_ops ingenic_rtc_ops = {
++	.ioctl      = ingenic_rtc_ioctl,
++	.read_time  = ingenic_rtc_read_time,
++	.set_time   = ingenic_rtc_set_time,
++	.read_alarm = ingenic_rtc_read_alarm,
++	.set_alarm  = ingenic_rtc_set_alarm,
++	.proc       = ingenic_rtc_proc,
++	.alarm_irq_enable	= ingenic_rtc_alarm_irq_enable,
++};
++
++static void ingenic_rtc_enable(struct ingenic_rtc *rtc)
++{
++	unsigned int cfc,hspr,rgr_1hz;
++	unsigned long time = 0;
++
++	/*
++	 * When we are powered on for the first time, init the rtc and reset time.
++	 *
++	 * For other situations, we remain the rtc status unchanged.
++	 */
++
++//	cpm_set_clock(CGU_RTCCLK, 32768); //later to know if we need to set it ,it may decided by hardware.
++	cfc = HSPR_RTCV;
++	hspr = ingenic_rtc_readl(rtc, RTC_HSPR);
++	rgr_1hz = ingenic_rtc_readl(rtc, RTC_RTCGR) & RTCGR_NC1HZ_MASK;
++
++	if ((hspr != cfc) || (rgr_1hz != RTC_FREQ_DIVIDER)) {
++		/* We are powered on for the first time !!! */
++
++		pr_info("ingenic_rtc: rtc power on reset !\n");
++
++		/* Set 32768 rtc clocks per seconds */
++		ingenic_rtc_writel(rtc, RTC_RTCGR, RTC_FREQ_DIVIDER);
++
++		/*FIXME,by jwsun, should not be in here*/
++		/* Set minimum wakeup_n pin low-level assertion time for wakeup: 100ms */
++		ingenic_rtc_writel(rtc, RTC_HWFCR, HWFCR_WAIT_TIME(100));
++		ingenic_rtc_writel(rtc, RTC_HRCR, HRCR_WAIT_TIME(60));
++
++
++		/* Reset to the default time */
++		time = rtc_tm_to_time64(&default_tm);
++		ingenic_rtc_writel(rtc, RTC_RTCSR, time);
++
++		/* clear alarm register */
++		ingenic_rtc_writel(rtc, RTC_RTCSAR, 0);
++
++		/* start rtc */
++		ingenic_rtc_writel(rtc, RTC_RTCCR, RTCCR_RTCE);
++		ingenic_rtc_writel(rtc, RTC_HSPR, cfc);
++	}
++
++	/*FIXME,by jwsun, should not be in here*/
++	/* clear all rtc flags */
++	ingenic_rtc_writel(rtc, RTC_HWRSR, 0);
++
++	/*FIXME,by wssong, should not be in here*/
++	/* Set the default value of WKUPPINCR */
++	if (rtc->priv->version_num == 2)
++		ingenic_rtc_writel(rtc,RTC_WKUPPINCR, WKUPPINCR_DEFAULT_V1);
++	else
++		ingenic_rtc_writel(rtc,RTC_WKUPPINCR, WKUPPINCR_DEFAULT);
++
++	/* enabled Power detect*/
++	mutex_lock(&rtc->mutexlock);
++	if (rtc->priv->version_num == 2)
++		ingenic_rtc_writel(rtc, RTC_HWCR, (ingenic_rtc_readl(rtc, RTC_HWCR) & 0x1));
++	else
++		ingenic_rtc_writel(rtc, RTC_HWCR,((ingenic_rtc_readl(rtc, RTC_HWCR) & 0x1) | (EPDET_DEFAULT << 3)));
++
++	mutex_unlock(&rtc->mutexlock);
++}
++
++static struct rtc_private priv_data1 = {
++	.version_num = 1,
++};
++
++static struct rtc_private priv_data2 = {
++	.version_num = 2,
++};
++
++static const struct of_device_id ingenic_rtc_of_match[] = {
++	{ .compatible = "ingenic,rtc", .data = (struct priv_data *)&priv_data1, },
++	{ .compatible = "ingenic,rtc-x1600", .data = (struct priv_data *)&priv_data2, },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ingenic_rtc_of_match);
++
++static int ingenic_rtc_probe(struct platform_device *pdev)
++{
++
++	struct ingenic_rtc *rtc;
++	struct clk *rtc_gate;
++	const struct of_device_id *dev_match;
++	int ret;
++
++	rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
++	if (!rtc) {
++		ret = -ENOMEM;
++		goto err_nomem;
++	}
++
++	dev_match =of_match_node(ingenic_rtc_of_match, pdev->dev.of_node);
++	rtc->priv = (struct rtc_private *)dev_match->data;
++
++	rtc_gate = devm_clk_get(&pdev->dev, "gate_rtc");
++	if (IS_ERR(rtc_gate)) {
++		dev_err(&pdev->dev, "cannot find RTC clock\n");
++		ret = PTR_ERR(rtc_gate);
++		goto err_mem;
++	}
++
++	clk_prepare_enable(rtc_gate);
++	clk_put(rtc_gate);
++
++	rtc->irq = platform_get_irq(pdev, 0);
++	if (rtc->irq < 0) {
++		dev_err(&pdev->dev, "no irq for rtc tick\n");
++		ret = rtc->irq;
++		goto err_nosrc;
++	}
++
++	rtc->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (rtc->res == NULL) {
++		dev_err(&pdev->dev, "failed to get memory region resource\n");
++		ret = -ENXIO;
++		goto err_nosrc;
++	}
++
++	rtc->res = request_mem_region(rtc->res->start,
++			rtc->res->end - rtc->res->start+1, pdev->name);
++	if (rtc->res == NULL) {
++		dev_err(&pdev->dev, "failed to reserve memory region\n");
++		ret = -EFAULT;
++		goto err_mem;
++	}
++
++	rtc->iomem = ioremap(rtc->res->start,
++			rtc->res->end - rtc->res->start + 1);
++	if (rtc->iomem == NULL) {
++		dev_err(&pdev->dev, "failed ioremap()\n");
++		ret = -EFAULT;
++		goto err_nomap;
++	}
++
++	platform_set_drvdata(pdev, rtc);
++	device_init_wakeup(&pdev->dev, 1);
++
++	rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
++			&ingenic_rtc_ops, THIS_MODULE);
++	if (IS_ERR(rtc->rtc)) {
++		ret = PTR_ERR(rtc->rtc);
++		dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
++		goto err_unregister_rtc;
++	}
++
++	INIT_WORK(&rtc->work, ingenic_rtc_irq_work);
++	mutex_init(&rtc->mutexlock);
++	mutex_init(&rtc->mutex_wr_lock);
++
++	ret = request_irq(rtc->irq, ingenic_rtc_interrupt,
++			IRQF_TRIGGER_LOW | IRQF_SHARED,
++			"rtc 1Hz and alarm", rtc);
++	if (ret) {
++		pr_debug("IRQ %d already in use.\n", rtc->irq);
++		goto err_free_irq;
++	}
++
++	ingenic_rtc_enable(rtc);
++	printk("ingenic RTC probe success \n");
++	return 0;
++
++err_free_irq:
++	free_irq(rtc->irq,rtc);
++err_unregister_rtc:
++	iounmap(rtc->iomem);
++err_nomap:
++	release_mem_region(rtc->res->start, resource_size(rtc->res));
++err_mem:
++err_nosrc:
++	kfree(rtc);
++err_nomem:
++	return ret;
++}
++
++static int ingenic_rtc_remove(struct platform_device *pdev)
++{
++	struct ingenic_rtc *rtc = platform_get_drvdata(pdev);
++
++	ingenic_rtc_writel(rtc, RTC_RTCCR, 0);
++
++	clk_disable(rtc->clk);
++	clk_put(rtc->clk);
++	rtc->clk = NULL;
++
++	free_irq(rtc->irq,rtc);
++	iounmap(rtc->iomem);
++	release_resource(rtc->res);
++	kfree(rtc);
++	platform_set_drvdata(pdev, NULL);
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int ingenic_rtc_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	struct ingenic_rtc *rtc = platform_get_drvdata(pdev);
++#ifdef CONFIG_SUSPEND_TEST
++	unsigned int val;
++	unsigned int test_alarm_time, sr_time;
++
++	val = ingenic_rtc_readl(rtc, RTC_RTCCR);
++	if(val & RTCCR_AE) {
++		rtc->save_rtccr = val;
++		rtc->os_alarm_time = ingenic_rtc_readl(rtc, RTC_RTCSAR);
++	}
++	val |= RTCCR_AIE | RTCCR_AE;
++	ingenic_rtc_writel(rtc, RTC_RTCCR, val);
++
++	sr_time = ingenic_rtc_readl(rtc, RTC_RTCSR);
++	test_alarm_time = sr_time + CONFIG_SUSPEND_ALARM_TIME;
++	if(rtc->os_alarm_time && rtc->os_alarm_time > sr_time \
++	   && rtc->os_alarm_time < test_alarm_time)
++		test_alarm_time =  rtc->os_alarm_time;
++	ingenic_rtc_writel(rtc, RTC_RTCSAR, test_alarm_time);
++
++	printk("-------suspend count = %d\n", rtc->sleep_count++);
++#endif
++	if (device_may_wakeup(&pdev->dev)) {
++		enable_irq_wake(rtc->irq);
++	}
++
++	return 0;
++}
++
++static int ingenic_rtc_resume(struct platform_device *pdev)
++{
++	struct ingenic_rtc *rtc = platform_get_drvdata(pdev);
++
++	if (device_may_wakeup(&pdev->dev)) {
++		disable_irq_wake(rtc->irq);
++	}
++#ifdef CONFIG_SUSPEND_TEST
++	if(rtc->save_rtccr & RTCCR_AE) {
++		ingenic_rtc_writel(rtc, RTC_RTCSAR, rtc->os_alarm_time);
++		ingenic_rtc_writel(rtc, RTC_RTCCR, rtc->save_rtccr);
++		rtc->os_alarm_time = 0;
++		rtc->save_rtccr = 0;
++	} else {
++		unsigned int val;
++		val = ingenic_rtc_readl(rtc, RTC_RTCCR);
++		val &= ~ (RTCCR_AF |RTCCR_AIE | RTCCR_AE);
++		ingenic_rtc_writel(rtc, RTC_RTCCR, val);
++	}
++#endif
++	return 0;
++}
++#else
++#define ingenic_rtc_suspend	NULL
++#define ingenic_rtc_resume	NULL
++#endif
++static struct platform_driver ingenic_rtc_driver = {
++	.driver	= {
++		.name = "rtc-ingenic",
++		.of_match_table = ingenic_rtc_of_match,
++	},
++	.remove		= __exit_p(ingenic_rtc_remove),
++	.suspend	= ingenic_rtc_suspend,
++	.resume		= ingenic_rtc_resume,
++};
++module_platform_driver_probe(ingenic_rtc_driver, ingenic_rtc_probe);
++
++MODULE_AUTHOR("Aaron <hfwang@ingenic.cn>");
++MODULE_DESCRIPTION("Ingenic SoC Realtime Clock Driver (RTC)");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-rtc");
+diff --git a/module_drivers/drivers/rtc/rtc-ingenic.h b/module_drivers/drivers/rtc/rtc-ingenic.h
+new file mode 100644
+index 000000000..66d227a91
+--- /dev/null
++++ b/module_drivers/drivers/rtc/rtc-ingenic.h
+@@ -0,0 +1,141 @@
++/*
++ * ingenic RTC register definition
++ * Copyright (C) 2014 Ingenic Semiconductor Co., Ltd.
++ *
++ */
++#ifndef __INGENIC_RTC_H__
++#define __INGENIC_RTC_H__
++
++/*Case option definition for the 'ingenic_rtc_ioctl' function*/
++#define RTC_CMD_BASE 'R'
++#define SET_PD_STEP _IOW(RTC_CMD_BASE, 1u, int)
++#define SET_DDRBUFER_EN _IOW(RTC_CMD_BASE, 2u, int)
++#define SET_DDRBUFER_DISEN _IOW(RTC_CMD_BASE, 3u, int)
++#define PRINT_INFO _IOW(RTC_CMD_BASE, 4u, int)
++#define SET_RTCCR_1HZIE_ON _IOW(RTC_CMD_BASE, 5u, int)
++#define SET_RTCCR_1HZIE_OFF _IOW(RTC_CMD_BASE, 6u, int)
++#define SET_WKUPPINCR_P_RST_EN _IOW(RTC_CMD_BASE, 7u, int)
++#define SET_WKUPPINCR_P_RST_OFF _IOW(RTC_CMD_BASE, 8u, int)
++
++/*
++ * RTC registers offset address definition
++ */
++#define RTC_RTCCR		(0x00)	/* rw, 32, 0x00000081 */
++#define RTC_RTCSR		(0x04)	/* rw, 32, 0x???????? */
++#define RTC_RTCSAR		(0x08)	/* rw, 32, 0x???????? */
++#define RTC_RTCGR		(0x0c)	/* rw, 32, 0x0??????? */
++#define RTC_HCR			(0x20)  /* rw, 32, 0x00000000 */
++#define RTC_HWFCR		(0x24)  /* rw, 32, 0x0000???0 */
++#define RTC_HRCR		(0x28)  /* rw, 32, 0x00000??0 */
++#define RTC_HWCR		(0x2c)  /* rw, 32, 0x00000008 */
++#define RTC_HWRSR		(0x30)  /* rw, 32, 0x00000000 */
++#define RTC_HSPR		(0x34)  /* rw, 32, 0x???????? */
++#define RTC_WENR		(0x3c)  /* rw, 32, 0x00000000 */
++#define RTC_WKUPPINCR		(0x48)	/* rw, 32, 0x00af0064 */
++/*
++ * RTC registers common define
++ */
++
++/* RTC control register(RTCCR) */
++#define RTCCR_WRDY		BIT(7)
++#define RTCCR_1HZ		BIT(6)
++#define RTCCR_1HZIE		BIT(5)
++#define RTCCR_AF		BIT(4)
++#define RTCCR_AIE		BIT(3)
++#define RTCCR_AE		BIT(2)
++#define RTCCR_SELEXC		BIT(1)
++#define RTCCR_RTCE		BIT(0)
++
++/* Generate the bit field mask from msb to lsb */
++#define BITS_H2L(msb, lsb)  ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))
++
++/* RTC regulator register(RTCGR) */
++#define RTCGR_LOCK		BIT(31)
++#define RTCGR_ADJC_LSB		16
++#define RTCGR_ADJC_MASK		BITS_H2L(25, RTCGR_ADJC_LSB)
++#define RTCGR_NC1HZ_LSB		0
++#define RTCGR_NC1HZ_MASK	BITS_H2L(15, RTCGR_NC1HZ_LSB)
++
++/* Hibernate control register(HCR) */
++#define HCR_PD			BIT(0)
++
++/* Hibernate wakeup filter counter register(HWFCR) */
++#define HWFCR_LSB		5
++#define HWFCR_MASK		BITS_H2L(15, HWFCR_LSB)
++#define HWFCR_WAIT_TIME(ms)	(((ms) << HWFCR_LSB) > HWFCR_MASK ? HWFCR_MASK : ((ms) << HWFCR_LSB))
++
++/* Hibernate reset counter register(HRCR) */
++#define HRCR_LSB		11
++#define HRCR_MASK		BITS_H2L(14, HRCR_LSB)
++#define HRCR_WAIT_TIME(ms)     (ms < 62 ? 0 : (((ms / 62 - 1) << HRCR_LSB) > HRCR_MASK ? HRCR_MASK : ((ms / 62 - 1) << HRCR_LSB)))
++
++/* Hibernate wakeup control register(HWCR) */
++
++/* Power detect default value; this value means enable */
++#define EPDET_DEFAULT           (0x5aa5a5a)
++#define EPDET_ENABLE		(0x5aa5a5a)
++#define EPDET_DISABLE		(0x1a55a5a5)
++#define HWCR_EPDET		BIT(3)
++#define HWCR_WKUPVL		BIT(2)
++#define HWCR_EALM		BIT(0)
++
++/* Hibernate wakeup status register(HWRSR) */
++#define HWRSR_APD		BIT(8)
++#define HWRSR_HR		BIT(5)
++#define HWRSR_PPR		BIT(4)
++#define HWRSR_PIN		BIT(1)
++#define HWRSR_ALM		BIT(0)
++
++/* write enable pattern register(WENR) */
++#define WENR_WEN		BIT(31)
++#define WENR_WENPAT_LSB		0
++#define WENR_WENPAT_MASK	BITS_H2L(15, WENR_WENPAT_LSB)
++#define WENR_WENPAT_WRITABLE	(0xa55a)
++
++/* Hibernate scratch pattern register(HSPR) */
++#define HSPR_RTCV               (0x52544356)      /* The value is 'RTCV', means rtc is valid */
++
++/*WKUP_PIN_RST control register (WKUPPINCR)*/
++#define WKUPPINCR_DEFAULT	(0x00af0064)
++#define WKUPPINCR_DEFAULT_V1	(0x00a30064)
++
++#define WKUPPINCR_P_RST_EN_DEF	(0x4)
++#define WKUPPINCR_P_RST_EN	(0xb)
++#define WKUPPINCR_P_RST_CLEAR	(0xf)
++#define WKUPPINCR_OSC_EN	BIT(16)
++#define WKUPPINCR_FASTBOOT	BIT(20)
++#define WKUPPINCR_BUFFEREN	BIT(21)
++#define WKUPPINCR_RAMSLEEP	BIT(22)
++#define WKUPPINCR_RAMSHUT	BIT(23)
++
++/* The divider is decided by the RTC clock frequency. */
++#define RTC_FREQ_DIVIDER	(32768 - 1)
++#define ms2clycle(x)  (((x) * RTC_FREQ_DIVIDER) / 1000)
++
++struct rtc_private {
++	int version_num;
++};
++
++/*ingenic rtc device struct*/
++struct ingenic_rtc {
++	int irq;
++	struct clk *clk;
++	spinlock_t lock;
++	spinlock_t rd_lock;
++	spinlock_t wr_lock;
++	void __iomem *iomem;
++	struct mutex	mutexlock;
++	struct mutex	mutex_wr_lock;
++	struct resource *res;
++	struct work_struct work;
++	struct rtc_device *rtc;
++	struct rtc_time rtc_alarm;
++	struct rtc_private *priv;
++#ifdef CONFIG_SUSPEND_TEST
++	unsigned int sleep_count;
++	unsigned int os_alarm_time;
++	unsigned int save_rtccr;
++#endif
++};
++
++#endif /* __INGENIC_RTC_H__ */
+diff --git a/module_drivers/drivers/spi/Kconfig b/module_drivers/drivers/spi/Kconfig
+new file mode 100644
+index 000000000..b36af355b
+--- /dev/null
++++ b/module_drivers/drivers/spi/Kconfig
+@@ -0,0 +1,27 @@
++config INGENIC_SPI
++        tristate "Ingenic SPI Controller"
++        depends on (MACH_XBURST || MACH_XBURST2)
++        select SPI_BITBANG
++        help
++                SPI driver for Ingenic series SoCs
++
++config INGENIC_SPI0
++    bool "Ingenic SoC SSI controller 0 for SPI Host driver"
++        depends on INGENIC_SPI
++
++config INGENIC_SPI_PIO_CE
++        bool "Use GPIO CE on Ingenic SSI controller 0"
++        depends on INGENIC_SPI
++        default n
++        help
++                Use GPIO control SSI CE by CPU. Sometimes controller's CE NOT match SPI Protocal
++config INGENIC_SLV
++        tristate "Ingenic series SPI slave driver"
++        depends on MACH_XBURST
++        select SPI_BITBANG
++        help
++                SPI slave driver for Ingenic JZ series SoCs
++config INGENIC_SLV0
++        bool "Ingenic SoC SSI_SLV controller 0 for SPI SLV Host driver"
++        depends on INGENIC_SLV
++
+diff --git a/module_drivers/drivers/spi/Makefile b/module_drivers/drivers/spi/Makefile
+new file mode 100644
+index 000000000..8707adf6a
+--- /dev/null
++++ b/module_drivers/drivers/spi/Makefile
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_INGENIC_SPI)               += ingenic_spi.o
++obj-$(CONFIG_INGENIC_SLV)               += ingenic_slv.o
+diff --git a/module_drivers/drivers/spi/ingenic_slv.c b/module_drivers/drivers/spi/ingenic_slv.c
+new file mode 100755
+index 000000000..dddec0e00
+--- /dev/null
++++ b/module_drivers/drivers/spi/ingenic_slv.c
+@@ -0,0 +1,1201 @@
++/* linux/drivers/spi/ingenic_sslv.c
++ *
++ * SSI controller for SPI protocol,use FIFO and DMA;
++ * base-to: linux/drivers/spi/spi_bitbang.c
++ *
++ * Copyright (c) 2011 Ingenic
++ * Author:Shumb <sbhuang@ingenic.cn>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/fs.h>
++#include <linux/file.h>
++#include <linux/spinlock.h>
++#include <linux/workqueue.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/gpio.h>
++#include <linux/platform_device.h>
++#include <linux/spi/spi.h>
++#include <linux/spi/spi_bitbang.h>
++#include <linux/module.h>
++#include <asm/uaccess.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++#include <linux/spi/spidev.h>
++
++#include "ingenic_slv.h"
++
++
++#define FPGA_TEST_SPI_SLV
++#define INTERRUPT_TEST
++/* #define SSI_DEGUG */
++#ifdef SSI_DEGUG
++#define  print_dbg(format,arg...)			\
++	printk(format,## arg)
++#else
++#define  print_dbg(format,arg...)
++#endif
++
++#if 0
++#define INGENIC_SPI_RX_BUF(type) 				\
++	u32 ingenic_sslv_rx_buf_##type(struct ingenic_sslv *hw) 		\
++{								\
++	u32 data  = ss_read(hw, SSLV_DR);			\
++	printk("read data : 0x%08x\n",data); \
++	type * rx = (type *)hw->rx;				\
++	*rx++ = (type)(data);			  		\
++	hw->rx = (u8 *)rx;					\
++	return (u32)data;					\
++}
++
++#define INGENIC_SPI_TX_BUF(type)					\
++	u32 ingenic_sslv_tx_buf_##type(struct ingenic_sslv *hw)		\
++{								\
++	u32 data;						\
++	const type * tx = (type *)hw->tx;			\
++	data = *tx++;						\
++	hw->tx = (u8 *)tx;					\
++	transmit_data(hw, data);				\
++	return (u32)data;					\
++}
++	/* printk("data regs:   0x%08x\n",ss_read(hw, SSLV_DR));\ */
++	/* printk("write data : 0x%08x\n",data); \ */
++#else
++#define INGENIC_SPI_RX_BUF(type) 				\
++	u32 ingenic_sslv_rx_buf_##type(struct ingenic_sslv *hw) 		\
++{								\
++	u32 data  = ss_read(hw, SSLV_DR);			\
++	type * rx = (type *)hw->rx;				\
++	*rx++ = (type)(data);			  		\
++	hw->rx = (u8 *)rx;					\
++	return (u32)data;					\
++}
++
++#define INGENIC_SPI_TX_BUF(type)					\
++	u32 ingenic_sslv_tx_buf_##type(struct ingenic_sslv *hw)		\
++{								\
++	u32 data;						\
++	const type * tx = (type *)hw->tx;			\
++	data = *tx++;						\
++	hw->tx = (u8 *)tx;					\
++	transmit_data(hw, data);				\
++	return (u32)data;					\
++}
++#endif
++
++INGENIC_SPI_RX_BUF(u8)
++INGENIC_SPI_TX_BUF(u8)
++
++INGENIC_SPI_RX_BUF(u16)
++INGENIC_SPI_TX_BUF(u16)
++
++INGENIC_SPI_RX_BUF(u32)
++INGENIC_SPI_TX_BUF(u32)
++
++
++void dump_spi_slaver_regs(struct ingenic_sslv *hw)
++{
++	printk("******************** dump slaver regs *********************\n");
++	printk("CTRLR0(0x%08x) =		0x%08x\n",CTRLR0, ss_read(hw, CTRLR0));
++	printk("ENABLE(0x%08x) =		0x%08x\n",0x8,  ss_read(hw, 0x8));
++	printk("MIC CONTROL(0x%08x) =		0x%08x\n",0xc,  ss_read(hw, 0xc));
++	printk("TFIFO THRES(0x%08x) = 		0x%08x\n",0x18, ss_read(hw, 0x18));
++	printk("RFIFO THRES(0x%08x) = 		0x%08x\n",0x1c, ss_read(hw, 0x1c));
++	printk("TFIFO LEVEL(0x%08x) = 		0x%08x\n",0x20, ss_read(hw, 0x20));
++	printk("RFIFO LEVEL(0x%08x) = 		0x%08x\n",0x24, ss_read(hw, 0x24));
++	printk("status reg(0x%08x) =		0x%08x\n",0x28, ss_read(hw, 0x28));
++	printk("intc mask(0x%08x) = 		0x%08x\n",0x2c, ss_read(hw, 0x2c));
++	printk("intc status(0x%08x) =		0x%08x\n",0x30, ss_read(hw, 0x30));
++	printk("intc raw status(0x%08x) =	0x%08x\n",0x34, ss_read(hw, 0x34));
++	printk("DMA control(0x%08x) =		0x%08x\n",0x4c, ss_read(hw, 0x4c));
++	printk("DMA t level(0x%08x) =		0x%08x\n",0x50, ss_read(hw, 0x50));
++	printk("DMA r level(0x%08x) = 		0x%08x\n",0x54, ss_read(hw, 0x54));
++	printk("******************** dump slaver end *********************\n");
++}
++
++static void dma_tx_callback(void *data)
++{
++	struct ingenic_sslv *hw = data;
++	dma_unmap_sg(hw->txchan->device->dev, hw->sg_tx, 1, DMA_TO_DEVICE);
++	complete(&hw->done_tx_dma);
++}
++
++static void dma_rx_callback(void *data)
++{
++	struct ingenic_sslv *hw = data;
++	dma_unmap_sg(hw->rxchan->device->dev, hw->sg_rx, 1, DMA_FROM_DEVICE);
++	complete(&hw->done_rx_dma);
++}
++
++static int ingenic_sslv_dma_txrx(struct ingenic_sslv *hw, struct spi_transfer *t)
++{
++	int ret;
++	struct dma_slave_config rx_config, tx_config;
++	struct dma_async_tx_descriptor *rxdesc;
++	struct dma_async_tx_descriptor *txdesc;
++	struct dma_chan *rxchan = hw->rxchan;
++	struct dma_chan *txchan = hw->txchan;
++	u32 entries = 0;
++	int dma_ds[] = {64, 32, 16, 4, 2, 1};
++	unsigned int dma_unit = 0;
++	int i;
++
++	hw->len = t->len;
++	/* Check that the channels are available */
++	if (!hw->txchan || !hw->rxchan) {
++		dev_err(NULL, "no dma channel\n");
++		return -ENODEV;
++	}
++
++	if (t->len % hw->transfer_unit_size) {
++		pr_err("The length of tranfer data is error\n");
++		return -EFAULT;
++	}
++
++	// config controller
++	disable_all_interrupts(hw);
++
++	switch (hw->transfer_unit_size) {
++		case SPI_8BITS:
++			tx_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
++			tx_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
++			rx_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
++			rx_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
++			tx_config.dst_maxburst = 1;
++			tx_config.src_maxburst = 1;
++			rx_config.src_maxburst = 1;
++			rx_config.dst_maxburst = 1;
++			break;
++		case SPI_16BITS:
++			tx_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++			tx_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++			rx_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++			rx_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++			tx_config.dst_maxburst = 1;
++			tx_config.src_maxburst = 1;
++			rx_config.src_maxburst = 1;
++			rx_config.dst_maxburst = 1;
++			break;
++		case SPI_32BITS:
++			tx_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++			tx_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++			rx_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++			rx_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++			tx_config.dst_maxburst = 1;
++			tx_config.src_maxburst = 1;
++			rx_config.src_maxburst = 1;
++			rx_config.dst_maxburst = 1;
++			break;
++	}
++
++	tx_config.dst_addr = (dma_addr_t)(hw->phys + SSLV_DR);
++	rx_config.src_addr = (dma_addr_t)(hw->phys + SSLV_DR);
++	tx_config.direction = DMA_MEM_TO_DEV;
++	rx_config.direction = DMA_DEV_TO_MEM;
++	tx_config.slave_id = 0;
++	rx_config.slave_id = 0;
++
++	dmaengine_slave_config(txchan, &tx_config);
++	dmaengine_slave_config(rxchan, &rx_config);
++
++	hw->tx_trigger = 1;
++	hw->rx_trigger = 1;
++	set_tx_trigger(hw, hw->tx_trigger);
++	set_rx_trigger(hw, hw->rx_trigger);
++	/* set tx dma trigger */
++	set_txdma_threshold(hw, hw->tx_trigger);
++	/* set rx dma trigger */
++	set_rxdma_threshold(hw, hw->rx_trigger);
++
++	hw->tx = hw->txbuffer;
++	hw->rx = hw->rxbuffer;
++
++	print_dbg("t->len: %d, tx fifo width: %d, set tx trigger value to %d\n", t->len, hw->txfifo_width, hw->tx_trigger);
++
++	//set_rx_trigger(hw, 1); //the rx trigger is steady for tranfer
++	print_dbg("t->len: %d, rx fifo width: %d, set rx trigger value to %d\n", t->len, hw->rxfifo_width, hw->rx_trigger);
++
++	hw->rw_mode = 0;
++	/* all transfer starts with tx, ends with rx. */
++	if(t->tx_buf){
++		hw->rw_mode |= W_MODE;
++	}
++	if(t->rx_buf){
++		hw->rw_mode |= R_MODE;
++	}
++
++	/* config tx dma  */
++	sg_init_one(hw->sg_tx, hw->tx, t->len);
++	if (dma_map_sg(hw->txchan->device->dev,
++				hw->sg_tx, 1, DMA_TO_DEVICE) != 1) {
++		dev_err(NULL, "dma_map_sg tx error\n");
++		printk("%s LINE %d: %s\n", __func__, __LINE__, __FILE__);
++		goto err_tx_sgmap;
++	}
++
++	hw->sg_tx->dma_address &= 0xfffffff;
++
++	txdesc = dmaengine_prep_slave_sg(txchan,
++			hw->sg_tx,
++			1,
++			DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
++	if (!txdesc) {
++		dev_err(NULL, "device_prep_slave_sg error\n");
++		printk("%s LINE %d: %s\n", __func__, __LINE__, __FILE__);
++		goto err_txdesc;
++	}
++
++	txdesc->callback = dma_tx_callback;
++	txdesc->callback_param = hw;
++
++	/* config rx dma  */
++	sg_init_one(hw->sg_rx, hw->rx, t->len);
++	if (dma_map_sg(hw->rxchan->device->dev,
++				hw->sg_rx, 1, DMA_FROM_DEVICE) != 1) {
++		dev_err(NULL, "dma_map_sg rx error\n");
++		goto err_rx_sgmap;
++	}
++
++	hw->sg_rx->dma_address &= 0xfffffff;
++
++	rxdesc = dmaengine_prep_slave_sg(rxchan,
++			hw->sg_rx,
++			1,
++			DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
++	if (!rxdesc) {
++		dev_err(NULL, "device_prep_slave_sg error\n");
++		goto err_rxdesc;
++	}
++
++	rxdesc->callback = dma_rx_callback;
++	rxdesc->callback_param = hw;
++
++	enable_rxfifo_overflow_intr(hw);
++	enable_txfifo_overflow_intr(hw);
++
++	enable_tx_dmamode(hw);
++	enable_rx_dmamode(hw);
++
++	dmaengine_submit(txdesc);
++	dmaengine_submit(rxdesc);
++
++	start_transmit(hw);
++
++	dma_async_issue_pending(txchan);
++	dma_async_issue_pending(rxchan);
++
++	/* start transfer */
++	if(hw->rw_mode & W_MODE)
++
++	ret = wait_for_completion_interruptible_timeout(&hw->done_tx_dma, 240 * HZ);
++	if (ret <= 0) {
++		printk("The tx_dma umap wait timeout\n");
++		goto err_txdesc;
++	}
++
++	ret = wait_for_completion_interruptible_timeout(&hw->done_rx_dma, 240 * HZ);
++	if (ret <= 0) {
++		printk("The spi dam_callback wait timeout\n");
++		goto err_rxdesc;
++	}
++
++	/* dump_spi_slaver_regs(hw); */
++	if(hw->rw_mode & W_MODE)
++
++	finish_transmit(hw);
++	disable_all_interrupts(hw);
++	disable_tx_dmamode(hw);
++	disable_rx_dmamode(hw);
++
++	return t->len;
++
++err_rxdesc:
++err_txdesc:
++	dma_unmap_sg(rxchan->device->dev, hw->sg_rx, 1, DMA_FROM_DEVICE);
++err_rx_sgmap:
++	dma_unmap_sg(txchan->device->dev, hw->sg_tx, 1, DMA_TO_DEVICE);
++err_tx_sgmap:
++	printk("<< dma_txrx error. out of memory >>\n");
++	finish_transmit(hw);
++	return -ENOMEM;
++}
++
++static irqreturn_t ingenic_sslv_dma_irq_callback(struct ingenic_sslv *hw)
++{
++	unsigned int status;
++	unsigned int irq_status;
++
++	status = ss_read(hw, SLV_SR);
++	irq_status = ss_read(hw, SLV_ISR);
++	clear_all_interrupt(hw);
++
++	if(status & SR_TXE){
++		printk("%s[%d]: transfer error!\n",__func__,__LINE__);
++	}
++
++	/* rxfifo overflow */
++	if(status & SR_RFF){
++		printk("%s[%d]: rxfifo overflow!\n",__func__,__LINE__);
++	}
++
++	/* rxfifo is empty */
++	if(!(status & SR_RFNE)){
++		printk("%s[%d]: rxfifo is empty!\n",__func__,__LINE__);
++	}
++
++	/* txfifo is empty */
++	if(status & SR_TFE){
++		printk("%s[%d]: txfifo is empty!\n",__func__,__LINE__);
++	}
++
++	/* txfifo is full */
++	if(!(status & SR_TFNF)){
++		printk("%s[%d]: txfifo is full!\n",__func__,__LINE__);
++	}
++
++	/* rxfifo more than threshold */
++	if(irq_status & RXFIM){
++		printk("%s[%d]:dma error rxfifo more than threshold!\n",__func__,__LINE__);
++	}
++
++	/* txfifo less than threshold */
++	if(irq_status & ISR_TXEIS){
++		printk("%s[%d]:dma error txfifo less than threshold!\n",__func__,__LINE__);
++	}
++
++	return IRQ_HANDLED;
++}
++
++/* return value that is reveiced counter */
++static inline u32 cpu_read_rxfifo(struct ingenic_sslv *hw, unsigned int cnt)
++{
++	int i = 0;
++	u32 dat;
++
++//	print_dbg("The count of RxFIFO is %d \n", get_rxfifo_count(hw));
++
++	if ((hw->rw_mode & RW_MODE) == W_MODE) {
++		print_dbg("W_MODE\n");
++	}
++
++	for(i = 0; i < cnt; i++){
++		dat = hw->get_rx(hw);
++	}
++
++	return cnt;
++}
++
++/* return value that is transfered counter */
++static inline u32 cpu_write_txfifo(struct ingenic_sslv *hw, u32 entries)
++{
++	u32 i = 0;
++	u32 dat;
++
++	if ((!entries ) || (!(hw->rw_mode & RW_MODE)))
++		return 0;
++
++	if (hw->rw_mode & W_MODE) {
++		for (i = 0; i < entries; i++) {
++			dat = (u32)(hw->get_tx(hw));
++		}
++	}
++
++	return entries;
++}
++
++
++static void inline cale_rxfifo_trigger(struct ingenic_sslv *hw, unsigned int entries)
++{
++	if(entries <= INGENIC_SSI_MAX_FIFO_ENTRIES / 2){
++		hw->rx_trigger = entries;
++	}else{
++		hw->rx_trigger = INGENIC_SSI_MAX_FIFO_ENTRIES / 2;
++	}
++}
++
++static void inline cale_txfifo_trigger(struct ingenic_sslv *hw, unsigned int entries)
++{
++	if(entries <= INGENIC_SSI_MAX_FIFO_ENTRIES / 2){
++		hw->tx_trigger = entries;
++	}else{
++		hw->tx_trigger = INGENIC_SSI_MAX_FIFO_ENTRIES / 2;
++	}
++}
++
++static void wait_read(struct ingenic_sslv *hw)
++{
++	int i;
++	u32 thr;
++	/* u32 read_num = hw->len; */
++	while(hw->rentries > 0)
++	{
++		if(hw->rentries < hw->rx_trigger){
++			set_rx_trigger(hw, hw->rentries);
++		}
++		while((ss_read(hw, SLV_RISR) & ISR_RXFIR) == 0);
++		thr = read_rxfifo_entries(hw);
++		cpu_read_rxfifo(hw, thr);
++		hw->rentries -= thr;
++	}
++}
++static void wait_write(struct ingenic_sslv *hw)
++{
++	int i;
++	u32 thr;
++	u32 write_num = hw->len;
++	while(hw->wentries > 0)
++	{
++		while((ss_read(hw,SLV_RISR) & ISR_TXEIR) == 0);
++		thr = read_txfifo_entries(hw);
++		thr = hw->wentries > (INGENIC_SSI_MAX_FIFO_ENTRIES-thr) ? (INGENIC_SSI_MAX_FIFO_ENTRIES-thr) : hw->wentries;
++		cpu_write_txfifo(hw, thr);
++		hw->wentries -= thr;
++	}
++}
++
++static int ingenic_sslv_pio_txrx(struct ingenic_sslv *hw, struct spi_transfer *t)
++{
++	struct ingenic_intr_cnt *g_ingenic_intr = hw->g_ingenic_intr;
++	u32 entries = 0, unit_size = 0, send_entries = 0;
++	unsigned long flags;
++	int retlen = 0;
++	hw->len = t->len;
++	hw->wentries = 0;
++	hw->rentries = 0;
++	hw->dma_flag &= ~SPI_DMA_ACK;
++
++	unit_size = hw->transfer_unit_size;
++	if (unit_size == SPI_8BITS)
++		entries = hw->len;
++	else if (unit_size == SPI_16BITS )
++		entries = hw->len >> 1;
++	else if (unit_size == SPI_32BITS )
++		entries = hw->len >> 2;
++	else {
++		dev_err(hw->dev,"transfer_unit_size error!\n");
++		return -1;
++	}
++	/* set default trigger  */
++	hw->wentries = hw->rentries = entries;
++	hw->rx_trigger = INGENIC_SSI_MAX_FIFO_ENTRIES / 2;
++	hw->tx_trigger = INGENIC_SSI_MAX_FIFO_ENTRIES / 2;
++
++	/* config mode and trigger */
++	hw->rw_mode = 0;
++	if(t->tx_buf){
++		hw->rw_mode |= W_MODE;
++		hw->tx = hw->txbuffer;
++		cale_txfifo_trigger(hw, entries);
++	}
++
++	if(t->rx_buf){
++		hw->rw_mode |= R_MODE;
++		hw->rx = hw->rxbuffer;
++		cale_rxfifo_trigger(hw, entries);
++	}
++
++	print_dbg("tx trigger = %d, rx trigger = %d\n",hw->tx_trigger, hw->rx_trigger);
++
++	set_tx_trigger(hw, hw->tx_trigger);
++	set_rx_trigger(hw, hw->rx_trigger);
++
++	/* wait for sslv idle */
++	disable_all_interrupts(hw);
++	clear_all_interrupt(hw);
++	memset(g_ingenic_intr, 0, sizeof(struct ingenic_intr_cnt));
++
++#ifdef INTERRUPT_TEST
++	/* This start SSI transfer, write data or 0 to txFIFO.
++	 * irq is locked to protect SSI config registers */
++	spin_lock_irqsave(&hw->txrx_lock, flags);
++
++	/* enable interrupts */
++	if(hw->rw_mode & R_MODE){
++		enable_rxfifo_overflow_intr(hw);
++		enable_rxfifo_threshold_intr(hw);
++	}
++	if(hw->rw_mode & W_MODE){
++		enable_txfifo_overflow_intr(hw);
++		enable_txfifo_threshold_intr(hw);
++	}
++	/* start transfer */
++	start_transmit(hw);
++
++	spin_unlock_irqrestore(&hw->txrx_lock, flags);
++
++	/* wait the interrupt finish the transfer( one spi_transfer be sent ) */
++	if(hw->rw_mode & R_MODE){
++		int cnt = 6;
++		wait_for_completion_interruptible(&hw->done_rx);
++	}else{
++		unsigned int status;
++		wait_for_completion_interruptible(&hw->done);
++		status = ss_read(hw, SLV_SR);
++		while(!(status & SR_TFE)){
++			udelay(100000);
++			status = ss_read(hw, SLV_SR);
++		}
++	}
++
++#else
++	spin_lock_irqsave(&hw->txrx_lock, flags);
++
++	/* start transfer */
++	start_transmit(hw);
++
++	spin_unlock_irqrestore(&hw->txrx_lock, flags);
++	if(hw->rw_mode & R_MODE){
++		printk("%s[%d]:wait read\n",__func__,__LINE__);
++		wait_read(hw);
++	}else{
++		printk("%s[%d]: wait write\n",__func__,__LINE__);
++		wait_write(hw);
++	}
++#endif
++	finish_transmit(hw);
++	disable_all_interrupts(hw);
++
++	retlen = hw->len;
++	if(hw->rw_mode & R_MODE){
++		if(hw->rentries){
++			dev_info(hw->dev,"The received count isn't enough, the lost count is %d!\n", hw->rentries);
++			retlen = -1;
++		}
++	}else{
++		if(hw->wentries){
++			dev_info(hw->dev,"The transfer count isn't enough, the lost count is %d!\n", hw->wentries);
++			retlen = -1;
++		}
++	}
++
++	return retlen;
++}
++
++static irqreturn_t ingenic_sslv_pio_irq_callback(struct ingenic_sslv *hw)
++{
++	u32 cnt;
++	unsigned int status;
++	unsigned int irq_status;
++	int entries = 0;
++
++	status = ss_read(hw, SLV_SR);
++	irq_status = ss_read(hw, SLV_ISR);
++	clear_all_interrupt(hw);
++#if 0
++	if(status & SR_TXE){
++		printk("%s[%d]: transfer error!\n",__func__,__LINE__);
++	}
++
++	/* rxfifo overflow */
++	if(status & SR_RFF){
++		printk("%s[%d]: rxfifo overflow!\n",__func__,__LINE__);
++	}
++
++	/* rxfifo is empty */
++	if(!(status & SR_RFNE)){
++		printk("%s[%d]: rxfifo is empty!\n",__func__,__LINE__);
++	}
++
++	/* txfifo is empty */
++	if(status & SR_TFE){
++		printk("%s[%d]: txfifo is empty!\n",__func__,__LINE__);
++	}
++
++	/* txfifo is full */
++	if(!(status & SR_TFNF)){
++		printk("%s[%d]: txfifo is full!\n",__func__,__LINE__);
++	}
++#endif
++
++	/* rxfifo more than threshold */
++	if(irq_status & ISR_RXFIS){
++		cnt = read_rxfifo_entries(hw);
++		entries = hw->rentries > cnt ? cnt : hw->rentries;
++		cnt = cpu_read_rxfifo(hw, entries);
++		if(hw->rentries){
++			hw->rentries -= cnt;
++		}
++		if((hw->rentries > 0) && (hw->rentries < hw->rx_trigger)){
++			cale_rxfifo_trigger(hw, hw->rentries);
++			set_rx_trigger(hw, hw->rx_trigger);
++		}else if(hw->rentries <= 0){
++			disable_rxfifo_threshold_intr(hw);
++			disable_rxfifo_overflow_intr(hw);
++			if(hw->rw_mode & R_MODE){
++			complete(&hw->done_rx);
++			}
++		}
++	}
++	/* txfifo less than threshold */
++	if(irq_status & ISR_TXEIS){
++		cnt = read_txfifo_entries(hw);
++		entries = hw->wentries > INGENIC_SSI_MAX_FIFO_ENTRIES - cnt ?
++			INGENIC_SSI_MAX_FIFO_ENTRIES - cnt : hw->wentries ;
++		cpu_write_txfifo(hw, entries);
++		if(hw->wentries){
++			hw->wentries -= entries;
++		}
++		if((hw->wentries > 0)&&(hw->wentries < hw->tx_trigger)){
++			cale_txfifo_trigger(hw, hw->wentries);
++			set_tx_trigger(hw, hw->tx_trigger);
++		}
++		else if(hw->wentries <= 0){
++			disable_txfifo_threshold_intr(hw);
++			disable_txfifo_overflow_intr(hw);
++			wait_for_sslv_idle(hw);
++			if(hw->rw_mode & W_MODE)
++				complete(&hw->done);
++		}
++	}
++
++	return IRQ_HANDLED;
++}
++
++/* every spi_transfer could call this routine to setup itself */
++static int ingenic_sslv_setupxfer(struct ingenic_sslv *hw, struct spi_transfer *t)
++{
++	u8  bpw = 0, fifo_width = 0;
++
++	if (t) {
++		if(t->bits_per_word)
++			bpw = t->bits_per_word;
++	}
++
++	if (bpw < 4 || bpw > 32) {
++		printk("invalid bits-per-word (%d)\n", bpw);
++		return -EINVAL;
++	}
++
++	if (hw->use_dma) {
++		hw->txrx_bufs = ingenic_sslv_dma_txrx;
++		hw->irq_callback = ingenic_sslv_dma_irq_callback;
++	} else {
++		hw->txrx_bufs = ingenic_sslv_pio_txrx;
++		hw->irq_callback = ingenic_sslv_pio_irq_callback;
++	}
++
++	hw->bits_per_word = bpw;
++	if (bpw <= 8) {
++		hw->transfer_unit_size = SPI_8BITS;
++		hw->get_rx = ingenic_sslv_rx_buf_u8;
++		hw->get_tx = ingenic_sslv_tx_buf_u8;
++		fifo_width = FIFO_W8;
++	} else if (bpw <= 16) {
++		hw->transfer_unit_size = SPI_16BITS;
++		hw->get_rx = ingenic_sslv_rx_buf_u16;
++		hw->get_tx = ingenic_sslv_tx_buf_u16;
++		fifo_width = FIFO_W16;
++	} else {
++		hw->transfer_unit_size = SPI_32BITS;
++		hw->get_rx = ingenic_sslv_rx_buf_u32;
++		hw->get_tx = ingenic_sslv_tx_buf_u32;
++		fifo_width = FIFO_W32;
++	}
++
++	hw->txfifo_width = fifo_width;
++	hw->rxfifo_width = fifo_width;
++	set_frame_length(hw, fifo_width);
++
++	return 0;
++}
++
++static irqreturn_t ingenic_sslv_irq(int irq, void *dev)
++{
++	struct ingenic_sslv *hw = dev;
++	if(hw->irq_callback)
++		return hw->irq_callback(hw);
++	else
++		return IRQ_HANDLED;
++}
++
++int ingenic_sslv_init_setup(struct ingenic_sslv *hw)
++{
++#ifndef FPGA_TEST_SPI_SLV
++	if (!clk_is_enabled(hw->clk_gate)){
++		printk("%s[%d]: enable spi slave clk\n",__func__,__LINE__);
++		clk_enable(hw->clk_gate);
++	}
++#endif
++	/* disable the SSI controller */
++	start_config_regs(hw);
++
++	/* set default half_intr trigger */
++	hw->tx_trigger = INGENIC_SSI_MAX_FIFO_ENTRIES/2;
++	hw->rx_trigger = INGENIC_SSI_MAX_FIFO_ENTRIES/2;
++	set_tx_trigger(hw, hw->tx_trigger);
++	set_rx_trigger(hw, hw->rx_trigger);
++
++	/**********************
++	0:Motorola spi mode
++	1:TI ssp mode
++	2:NSM
++	3:reserved
++	**********************/
++	set_default_format(hw,0);
++
++	/**********************
++	0:pol=0,pha=0
++	1:pol=0,pha=1
++	2:pol=1,pha=0
++	3:pol=1,pha=1
++	**********************/
++	set_polcph_mode(hw,3);
++
++	/**********************
++	0:transfer & receive
++	1:transfer only
++	2:receive only
++	3:reserved
++	**********************/
++	set_transfer_mode(hw, 0);
++
++	/* First,mask the interrupt, while verify the status ? */
++	disable_all_interrupts(hw);
++	clear_all_interrupt(hw);
++
++	return 0;
++}
++
++static int test_loop(struct ingenic_sslv *hw)
++{
++	int i = 0, flag = 1;
++	int number = 32;
++	int thr = 8;
++	int cnt = 32;
++	int read_num = 0, write_num = 0;
++	unsigned char read_c[64], write_c[64];
++
++	for(i = 0; i < 64; i++)
++		write_c[i]=i;
++
++	start_config_regs(hw);
++	set_loop(hw, 1);
++	set_tx_trigger(hw, 8);
++	set_rx_trigger(hw, 32);
++	set_frame_length(hw, FIFO_W8);
++	set_transfer_mode(hw, 0);
++	start_transmit(hw);
++
++	printk("slv ready\n");
++	while(number > 0)
++	{
++		/* write fifo */
++		while((ss_read(hw, SLV_RISR) & ISR_TXEIR) == 0);
++		cnt = number > cnt ? cnt : number;
++		for(i = 0; i < cnt; i++)
++		{
++			transmit_data(hw, write_c[write_num]);
++			printk("write data %d\n",write_c[write_num]);
++			write_num++;
++		}
++
++		/* read fifo */
++		while((ss_read(hw, SLV_RISR) & ISR_RXFIR) == 0);
++		for(i = 0; i < cnt; i++)
++		{
++			read_c[read_num] = ss_read(hw, SSLV_DR);
++			read_num++;
++		}
++		number -= cnt;
++	}
++	finish_transmit(hw);
++	set_loop(hw, 0);
++
++	printk("write number: %d ; reads number:%d\n", write_num, read_num);
++	for(i = 0; i < write_num; i++){
++		printk("read_c[%d] = %d\n", i, read_c[i]);
++		if(read_c[i] != write_c[i]){
++			flag = 0;
++			printk("**********************************\n");
++			printk(" slv loop test error!!!\n");
++			printk(" read_c[%d] = %d; write_c[%d] = %d\n",i, read_c[i], i, write_c[i]);
++			printk("**********************************\n");
++		}
++	}
++	if(flag)
++		printk("@@@@@@ SLV LOOP TEST OK  @@@@@@\n");
++	return 0;
++}
++
++static int ingenic_sslv_open(struct inode *inode, struct file *file)
++{
++	struct miscdevice *dev = file->private_data;
++	struct ingenic_sslv *hw = container_of(dev, struct ingenic_sslv, mdev);
++	int ret = 0;
++	u32 value;
++
++	/*select old (SOC T31) SSI_SLV control */
++	value = ss_read(hw,0x0);
++	if(value & (0x1<<31))
++		printk("SSI_SLV CTRLR0 : %x\n",ss_read(hw,0x0));
++	else
++		ss_write(hw,0x0,0x1<<31);
++
++	/* config registers*/
++	ret = ingenic_sslv_init_setup(hw);
++
++	return ret;
++}
++
++static int ingenic_sslv_release(struct inode *inode, struct file *file)
++{
++	struct miscdevice *dev = file->private_data;
++	struct ingenic_sslv *hw = container_of(dev, struct ingenic_sslv, mdev);
++	ingenic_sslv_init_setup(hw);
++
++	return 0;
++}
++
++static long ingenic_sslv_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
++{
++	struct miscdevice *dev = filp->private_data;
++	struct ingenic_sslv *hw = container_of(dev, struct ingenic_sslv, mdev);
++	struct spi_transfer t;
++	long ret = 0;
++	int cnt = 0;
++
++	switch(cmd){
++		case INGENIC_SPI_LOOP_OPS:
++			test_loop(hw);
++			ingenic_sslv_init_setup(hw);
++			ret = 1;
++			break;
++		case INGENIC_SPI_INT_OPS:
++			printk("No Support!!!\n");
++			ret = 1;
++			break;
++		case INGENIC_SPI_CPU_OPS:
++			hw->use_dma = 0;
++			ret = 0;
++			break;
++		case INGENIC_SPI_DMA_OPS:
++			hw->use_dma = 1;
++			ret = 0;
++			break;
++		default:
++			printk("The cmd is invalid\n");
++			ret = -EINVAL;
++			break;
++	}
++	if(ret)
++		goto out;
++
++	if(arg){
++		if ((cnt = copy_from_user(&t, (void __user *)arg, sizeof(t)))) {
++			printk("cnt:	%d\n", cnt);
++			printk("[%s][%d] copy from user error\n",
++					__func__, __LINE__);
++			return -EFAULT;
++		}
++	}
++
++	if(t.len <= 0 || t.len > BUFFER_SIZE){
++		ret = -EINVAL;
++		printk("%s[%d]:The length(%d) is invalid\n",__func__,__LINE__, t.len);
++		goto out;
++	}
++	print_dbg("siziof(t) = %d, cs_change = %d, bits_per_word = %d\n",sizeof(t), t.cs_change, t.bits_per_word);
++
++	memset(hw->txbuffer, 0, BUFFER_SIZE);
++	memset(hw->rxbuffer, 0, BUFFER_SIZE);
++
++	if(t.tx_buf){
++		if (cnt = copy_from_user(hw->txbuffer, (void __user *)t.tx_buf,
++					t.len)) {
++			printk("cnt:	%d\n", cnt);
++			printk("[%s][%d] copy from user error\n",
++					__func__, __LINE__);
++			return -EFAULT;
++		}
++	}
++
++	if((ret = ingenic_sslv_setupxfer(hw, &t))){
++		printk("%s[%d]:Failed to setupxfer\n",__func__,__LINE__);
++		goto out;
++	}
++
++	//tranfer or receive data
++	ret = hw->txrx_bufs(hw, &t);
++	if(ret != t.len){
++		printk("%s[%d]: transfer %ld, len = %d\n",__func__,__LINE__, ret, t.len);
++	}else{
++		ret = 0;
++	}
++
++	if(t.rx_buf){
++		if (copy_to_user((void __user *)t.rx_buf, hw->rxbuffer,
++					t.len)) {
++			dev_err(NULL, "[%s][%d] copy to user error\n",
++					__func__, __LINE__);
++			return -EFAULT;
++		}
++	}
++out:
++	return ret;
++}
++
++
++static struct file_operations ingenic_sslv_fops = {
++	.open = ingenic_sslv_open,
++	.release = ingenic_sslv_release,
++	.unlocked_ioctl = ingenic_sslv_ioctl,
++};
++
++static bool spi_dma_chan_filter(struct dma_chan *chan, void *param)
++{
++	struct ingenic_sslv *hw = param;
++
++	printk("chan->chan_id = %d, dma_type = %d\n", chan->chan_id, hw->dma_type);
++	return hw->dma_type == (int)chan->private;
++}
++
++static int ingenic_sslv_probe(struct platform_device *pdev)
++{
++	struct ingenic_sslv *hw;
++	struct resource *res;
++	dma_cap_mask_t mask;
++	int err = 0;
++
++	hw = kzalloc(sizeof(struct ingenic_sslv), GFP_KERNEL);
++	if(!hw){
++		dev_err(&pdev->dev, "No memory for ingenic_sslv_slv\n");
++		err = -ENOMEM;
++		goto err_nomem;
++	}
++
++	memset(hw, 0, sizeof(struct ingenic_sslv));
++
++	hw->g_ingenic_intr = kzalloc(sizeof(struct ingenic_intr_cnt),GFP_KERNEL);
++	if(hw->g_ingenic_intr == NULL)
++	{
++		dev_err(&pdev->dev, "No memory for ingenic_intr_cnt\n");
++		err = -ENOMEM;
++		goto err_intr;
++	}
++
++	hw->dev = &pdev->dev;
++
++	/* find and map our resources */
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (res == NULL) {
++		dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
++		err = -ENOENT;
++		goto err_no_iores;
++	}
++
++	hw->ioarea = request_mem_region(res->start, resource_size(res),
++			pdev->name);
++	if (hw->ioarea == NULL) {
++		dev_err(&pdev->dev, "Cannot reserve iomem region\n");
++		err = -ENXIO;
++		goto err_no_iores;
++	}
++
++	hw->phys = res->start;
++
++	print_dbg("%s[%d]: res->start = 0x%08x\n",__func__,__LINE__, res->start);
++	hw->iomem = ioremap(res->start, (res->end - res->start)+1);
++	if (hw->iomem == NULL) {
++		dev_err(&pdev->dev, "Cannot map IO\n");
++		err = -ENXIO;
++		goto err_no_iomap;
++	}
++
++	hw->irq = platform_get_irq(pdev, 0);
++	if (hw->irq <= 0) {
++		dev_err(&pdev->dev, "No IRQ specified\n");
++		err = -ENOENT;
++		goto err_no_irq;
++	}
++
++	hw->clk_gate = devm_clk_get(&pdev->dev, "gate_ssislv");
++	clk_prepare_enable(hw->clk_gate);
++
++	platform_set_drvdata(pdev, hw);
++	init_completion(&hw->done);
++	init_completion(&hw->done_rx);
++	init_completion(&hw->done_tx_dma);
++	init_completion(&hw->done_rx_dma);
++	spin_lock_init(&hw->lock);
++	spin_lock_init(&hw->txrx_lock);
++
++	dma_cap_zero(mask);
++	dma_cap_set(DMA_SLAVE, mask);
++
++	hw->txchan = dma_request_chan(hw->dev, "tx");
++	if(IS_ERR(hw->txchan)) {
++		dev_err(&pdev->dev, "SPI request dma tx channel failed");
++		goto err_no_irq;
++	}
++
++	hw->rxchan = dma_request_chan(hw->dev, "rx");
++	if(IS_ERR(hw->rxchan)) {
++		dev_err(&pdev->dev, "SPI request dma rx channel failed");
++		goto free_txchan;
++	}
++
++	//alloc temp buffer for dma
++	hw->txbuffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
++			&hw->txbuffer_dma, GFP_KERNEL);
++	if (!hw->txbuffer) {
++		dev_err(&pdev->dev, "SPI request temp dma txbuffer failed");
++		goto free_rxchan;
++	}
++
++	hw->rxbuffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
++			&hw->rxbuffer_dma, GFP_KERNEL);
++	if (!hw->rxbuffer) {
++		dev_err(&pdev->dev, "SPI request temp dma rxbuffer failed");
++		goto free_txbuffer;
++	}
++
++	hw->sg_tx = devm_kmalloc(&pdev->dev,sizeof(struct scatterlist), GFP_KERNEL);
++	if (!hw->sg_tx) {
++		dev_err(&pdev->dev, "Failed to alloc tx scatterlist\n");
++		goto err_tx_sgmap;
++	}
++
++	hw->sg_rx = devm_kmalloc(&pdev->dev,sizeof(struct scatterlist), GFP_KERNEL);
++	if(!hw->sg_rx) {
++		dev_err(&pdev->dev, "Failed to alloc rx scatterlist\n");
++		goto err_rx_sgmap;
++	}
++
++	/* request SSI irq */
++	err = devm_request_irq(&pdev->dev, hw->irq, ingenic_sslv_irq, 0, pdev->name, hw);
++	if (err) {
++		dev_err(&pdev->dev, "Cannot claim IRQ\n");
++		goto err_no_irq;
++	}
++
++
++	hw->fifodepth = INGENIC_SSI_MAX_FIFO_ENTRIES;
++
++	/* SSI controller initializations for SPI */
++
++	hw->mdev.minor = MISC_DYNAMIC_MINOR;
++	hw->mdev.name = "spi_slv";
++	hw->mdev.fops = &ingenic_sslv_fops;
++	err = misc_register(&hw->mdev);
++	if (err < 0) {
++		err = -ENOENT;
++		dev_err(&pdev->dev, "misc_register failed\n");
++		goto error_misc_register;
++	}
++
++	printk("INGENIC SSI slaver Controller ok!!\n");
++
++	return 0;
++
++error_misc_register:
++	free_irq(hw->irq, hw);
++free_rxchan:
++	dma_release_channel(hw->rxchan);
++free_txchan:
++	dma_release_channel(hw->txchan);
++err_no_irq:
++	if (hw->sg_rx)
++		kfree(hw->sg_rx);
++err_rx_sgmap:
++	if (hw->sg_tx)
++		kfree(hw->sg_tx);
++err_tx_sgmap:
++	if (hw->rxbuffer)
++		kfree(hw->rxbuffer);
++free_txbuffer:
++	if (hw->txbuffer)
++		kfree(hw->txbuffer);
++	iounmap(hw->iomem);
++
++err_no_iomap:
++	release_resource(hw->ioarea);
++	kfree(hw->ioarea);
++
++err_no_iores:
++	kfree(hw->g_ingenic_intr);
++err_intr:
++	kfree(hw);
++err_nomem:
++	return err;
++}
++
++static int ingenic_sslv_remove(struct platform_device *dev)
++{
++	struct ingenic_sslv *hw = platform_get_drvdata(dev);
++
++	platform_set_drvdata(dev, NULL);
++
++	free_irq(hw->irq, hw);
++	iounmap(hw->iomem);
++	release_resource(hw->ioarea);
++	kfree(hw->ioarea);
++#ifndef FPGA_TEST_SPI_SLV
++	if(clk_is_enabled(hw->clk_gate))
++		clk_disable(hw->clk_gate);
++
++	clk_put(hw->clk_gate);
++#endif
++
++	/* release DMA channel */
++	if (hw->rxchan) {
++		dma_release_channel(hw->rxchan);
++		printk("dma_rx_chnl release\n");
++	}
++	if (hw->txchan) {
++		dma_release_channel(hw->txchan);
++		printk("dma_tx_chnl release\n");
++	}
++
++	kfree(hw->g_ingenic_intr);
++	kfree(hw);
++	printk(KERN_INFO "INGENIC SSI slaver Controller driver removed\n");
++
++	return 0;
++}
++
++MODULE_ALIAS("ingenic_spi_slave");			/* for platform bus hotplug */
++static const struct of_device_id ingenic_slv_match[] = {
++        { .compatible = "ingenic,slv", },
++        {},
++};
++MODULE_DEVICE_TABLE(of, ingenic_slv_match);
++static struct platform_driver ingenic_sslvdrv = {
++	.probe		= ingenic_sslv_probe,
++	.remove		= ingenic_sslv_remove,
++	.suspend	= NULL,
++	.resume		= NULL,
++	.driver		= {
++		.owner	= THIS_MODULE,
++		.name	= "ingenic.slv",
++		.of_match_table = of_match_ptr(ingenic_slv_match),
++	},
++};
++
++static int __init ingenic_sslv_init(void)
++{
++	return platform_driver_register(&ingenic_sslvdrv);
++}
++
++static void __exit ingenic_sslv_exit(void)
++{
++	platform_driver_unregister(&ingenic_sslvdrv);
++	printk(KERN_INFO "INGENIC SSI Controller Module EXIT\n");
++
++}
++
++module_init(ingenic_sslv_init);
++module_exit(ingenic_sslv_exit);
++
++MODULE_DESCRIPTION("INGENIC SPI SLAVER Driver");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/spi/ingenic_slv.h b/module_drivers/drivers/spi/ingenic_slv.h
+new file mode 100644
+index 000000000..0fd91a180
+--- /dev/null
++++ b/module_drivers/drivers/spi/ingenic_slv.h
+@@ -0,0 +1,564 @@
++#ifndef __SPI_SLV_H__
++#define __SPI_SLV_H__
++
++#include <linux/miscdevice.h>
++#include <linux/dmaengine.h>
++
++/*SSI register*/
++#define CTRLR0	0x0	/* Control Register 0 */
++#define SPI_FRF_SSF	(0<<21) /* Standard SPI Format */
++#define	DFS_MASK_BITS	((0x1f)<<16)	/* Date Frame Size */
++#define	DFS_32_BITS	((32-1)<<16)	/* Date Frame Size, 32 bits */
++#define	DFS_16_BITS	((16-1)<<16)	/* Date Frame Size, 16 bits */
++#define	DFS_8_BITS	((8-1)<<16)		/* Date Frame Size, 8 bits */
++#define	DCS_MASK_BITS	((0xf)<<12)	/* Control Frame Size */
++#define	SRL_NOMAL	(0<<11) /* Shift Register Loop,Nomal Mode Operation */
++#define	SRL_TEST	(1<<11) /* Shift Register Loop,Test Mode Operation */
++#define SLV_OE	(0<<10) /* Slave Output Enable */
++#define TMOD_T_R	(0<<8) /* Transmit & Receive */
++#define TMOD_T	(1<<8) /* Transmit Only */
++#define TMOD_R	(2<<8) /* Receive Only */
++#define	SCPOL_L	(0<<7) /* Serial Clock Polarity,Inactive state of serial clock is low */
++#define	SCPOL_H	(1<<7) /* Serial Clock Polarity,Inactive state of serial clock is high */
++#define SCPH_M	(0<<6) /* Serial Clock Phase,Serial clock toggles in middle of first data bit */
++#define SCPH_S	(1<<6) /* Serial Clock Phase,Serial clock toggles at start of first data bit */
++#define FRF_SPI	(0<<4) /* Frame Format, Motorola SPI */
++
++#define CTRLR1	0x4 /* Control Register 1 */
++
++#define	SSIENR	0x8 /* SSI Enable Register */
++#define SSI_EN	0x1 /* SSI Enable */
++#define SSI_DISEN	0x0 /* SSI Disenable */
++
++#define	MWCR	0xc /* Microwire Control Register */
++
++#define	SER		0x10 /* Slave Enable Register */
++
++#define	BAUDR	0x14 /* Baud Rate Select */
++
++#define	TXFTLR	0x18 /* Transmit FIFO Threshold Level */
++#define	RXFTLR	0x1c /* Receive FIFO Threshold Level */
++#define	TXFLR	0x20 /* Transmit FIFO Level Register */
++#define	RXFLR	0x24 /* Receive FIFO Level Register */
++
++#define	SLV_SR		0x28 /* Status Register */
++#define SR_TXE	(1<<5) /* Transmission error */
++#define SR_RFF	(1<<4) /* Receive FIFO is full */
++#define SR_RFNE	(1<<3) /* Receive FIFO is not empty */
++#define SR_TFE	(1<<2) /* Transmit FIFO is empty */
++#define	SR_TFNF	(1<<1) /* Transmit FIFO is not full */
++#define	SR_BUSY	(1<<0) /* SSI_SLV is actively transferring data */
++
++#define	SLV_IMR		0x2c /* Interrupt Mask Register */
++#define RXFIM	(1<<4) /* Receive FIFO more than threshold Interrupt Mask */
++#define	RXOIM	(1<<3) /* Receive FIFO Overflow Interrupt Mask */
++#define	RXUIM	(1<<2) /* Receive FIFO Empty Interrupt Mask */
++#define	TXOIM	(1<<1) /* Transmit FIFO Overflow Interrupt Mask */
++#define	TXEIM	(1<<0) /* Transmit FIFO less than threshold Interrupt Mask */
++
++#define	SLV_ISR		0x30 /* Interrupt Status Register */
++#define	ISR_RXFIS	(1<<4) /* Receive FIFO more than threshold Interrupt Status */
++#define ISR_RXOIS	(1<<3) /* Receive FIFO Overflow Interrupt Status */
++#define	ISR_RXUIS	(1<<2) /* Receive FIFO empty Interrupt Status */
++#define ISR_TXOIS	(1<<1) /* Transmit FIFO Overflow Interrupt Status */
++#define ISR_TXEIS	(1<<0) /* Transmit FIFO less than threshold Status */
++
++#define SLV_RISR	0x34 /* Raw Interrupt Status Register */
++#define	ISR_RXFIR	(1<<4) /* Receive FIFO more than threshold Interrupt Status */
++#define ISR_RXOIR	(1<<3) /* Receive FIFO Overflow Interrupt Status */
++#define	ISR_RXUIR	(1<<2) /* Receive FIFO empty Interrupt Status */
++#define ISR_TXOIR	(1<<1) /* Transmit FIFO Overflow Interrupt Status */
++#define ISR_TXEIR	(1<<0) /* Transmit FIFO less than threshold Status */
++
++#define	TXOICR	0x38 /* Transmit FIFO Overflow Interrupt Clear Register */
++#define	RXOICR	0x3c /* Receive FIFO Overflow Interrupt Clear Register */
++#define	RXUICR	0x40 /* Receive FIFO Underflow Interrupt Clear Registe */
++
++#define	DMACR	0x4c /* DMA Control Register */
++#define	TDMAE	(1<<1) /* Transmit DMA Enable */
++#define	RDMAE	(1<<0) /* Receive DMA Enable */
++
++#define	DMATDLR	0x50 /* DMA Transmit Data Level */
++#define	DMARDLR	0x54 /* DMA Receive Data Level */
++
++#define	SSLV_IDR		0x58 /* Identification Register */
++
++#define	SSI_COMP_VERSION	0x5c /* coreKit version ID register */
++
++#define	SSLV_DR		0x60 /* Data Registe */
++
++#define	RX_SAMPLE_DLY	0xf0 /* Rx Sample Delay Register */
++
++#define	SPI_CTRLR0	0xf4 /* SPI Control Register*/
++
++#define	RSVD_1	0xf8 /* Reserved location for future use */
++
++#define	RSVD_2	0xfc /* Reserved location for future use */
++
++
++/* These definitions of structs and macros are used in driver */
++#define R_MODE			0x1
++#define W_MODE			0x2
++#define RW_MODE			(R_MODE | W_MODE)
++
++#define R_DMA			0x4
++#define W_DMA			0x8
++#define RW_DMA			(R_DMA |W_DMA)
++
++#define SPI_DMA_ACK		0x1
++
++#define SPI_DMA_ERROR  		-3
++#define SPI_CPU_ERROR		-4
++
++#define SPI_COMPLETE		5
++
++#define INGENIC_SSI_MAX_FIFO_ENTRIES 	64
++#define INGENIC_SSI_DMA_BURST_LENGTH 	16
++
++#define FIFO_W8			8
++#define FIFO_W16		16
++#define FIFO_W32		32
++
++#define SPI_BITS_8		8
++#define SPI_BITS_16		16
++#define SPI_BITS_32		32
++
++#define SPI_8BITS		1
++#define SPI_16BITS		2
++#define SPI_32BITS		4
++
++
++/* tx rx threshold from 0x0 to 0xF */
++#define SSI_TX_FIFO_THRESHOLD		0x1
++#define SSI_RX_FIFO_THRESHOLD		0x1
++#define SSI_SAFE_THRESHOLD		0x1
++
++#define MAX_SSI_INTR		10000
++
++#define MAX_SSICDR			63
++#define MAX_CGV				255
++
++#define SSI_DMA_FASTNESS_CHNL 	 0   // SSI controller [n] FASTNESS when probe();
++
++#define INGENIC_NEW_CODE_TYPE
++
++#define BUFFER_SIZE	PAGE_SIZE
++
++#define INGENIC_SPI_LOOP_OPS 0
++#define INGENIC_SPI_INT_OPS 1
++#define INGENIC_SPI_CPU_OPS 2
++#define INGENIC_SPI_DMA_OPS 3
++
++enum jzdma_req_type {
++#define _RTP(NAME) JZDMA_REQ_##NAME##_TX,JZDMA_REQ_##NAME##_RX
++	                JZDMA_REQ_RESERVED0 = 0x03,
++	                _RTP(I2S1),
++	                _RTP(I2S0),
++	                JZDMA_REQ_AUTO_TXRX = 0x08,
++	                JZDMA_REQ_SADC_RX,
++	                JZDMA_REQ_RESERVED1 = 0x0b,
++	                _RTP(UART4),
++	                _RTP(UART3),
++	                _RTP(UART2),
++	                _RTP(UART1),
++	                _RTP(UART0),
++	                _RTP(SSI0),
++	                _RTP(SSI1),
++	                _RTP(MSC0),
++	                _RTP(MSC1),
++	                _RTP(MSC2),
++	                _RTP(PCM0),
++	                _RTP(PCM1),
++	                _RTP(I2C0),
++	                _RTP(I2C1),
++	                _RTP(I2C2),
++	                _RTP(I2C3),
++	                _RTP(I2C4),
++	                _RTP(DES),
++#undef _RTP
++	        };
++
++enum jzdma_type {
++        JZDMA_REQ_INVAL = 0,
++#define _RTP(NAME) JZDMA_REQ_##NAME = JZDMA_REQ_##NAME##_TX
++        _RTP(I2S1),
++        _RTP(I2S0),
++        JZDMA_REQ_AUTO = JZDMA_REQ_AUTO_TXRX,
++        JZDMA_REQ_SADC = JZDMA_REQ_SADC_RX,
++        _RTP(UART4),
++        _RTP(UART3),
++        _RTP(UART2),
++        _RTP(UART1),
++        _RTP(UART0),
++        _RTP(SSI0),
++        _RTP(SSI1),
++        _RTP(MSC0),
++        _RTP(MSC1),
++        _RTP(MSC2),
++        _RTP(PCM0),
++        _RTP(PCM1),
++        _RTP(I2C0),
++        _RTP(I2C1),
++        _RTP(I2C2),
++        _RTP(I2C3),
++        _RTP(I2C4),
++        _RTP(DES),
++        JZDMA_REQ_NAND0 = JZDMA_REQ_AUTO_TXRX | (1 << 16),
++        JZDMA_REQ_NAND1 = JZDMA_REQ_AUTO_TXRX | (2 << 16),
++        JZDMA_REQ_NAND2 = JZDMA_REQ_AUTO_TXRX | (3 << 16),
++        JZDMA_REQ_NAND3 = JZDMA_REQ_AUTO_TXRX | (4 << 16),
++        JZDMA_REQ_NAND4 = JZDMA_REQ_AUTO_TXRX | (5 << 16),
++        TYPE_MASK = 0xffff,
++#undef _RTP
++};
++
++struct ingenic_sslv {
++	/* bitbang has to be first */
++	struct miscdevice mdev;
++	struct completion	done;
++	struct completion	done_rx;
++	struct completion	done_tx_dma;
++	struct completion	done_rx_dma;
++
++	struct clk		*clk_gate;
++	unsigned int            clk_gate_flag;
++	struct clk		*clk;
++	unsigned int		clk_flag;
++	unsigned int		set_clk_flag;
++
++	spinlock_t		lock;
++	spinlock_t		txrx_lock;
++
++	unsigned int		state;
++
++	u8			chnl;
++	u8			rw_mode;
++	u8			spi_mode;
++	u8			use_dma;
++	u8			is_first;
++
++	u8			bits_per_word;		/*8 or 16 (or 32)*/
++	u8			transfer_unit_size;	/* 1 or 2 (or 4) */
++	u8			tx_trigger;		/* 0-128 */
++	u8			rx_trigger;		/* 0-128 */
++	u8			dma_tx_unit;		/* 1 or 2 or 4 or 16 or 32*/
++	u8			dma_rx_unit;		/* 1 or 2 or 4 or 16 or 32*/
++	u8			txfifo_width;
++	u8			rxfifo_width;
++	u32			fifodepth;
++
++	/* data buffers */
++	const u8		*tx;
++	u8			*rx;
++
++	/* temp buffers */
++	void			*txbuffer;
++	dma_addr_t		txbuffer_dma;
++	void			*rxbuffer;
++	dma_addr_t		rxbuffer_dma;
++
++	void __iomem		*iomem;
++	unsigned long		phys;
++	int			 irq;
++	u32			 len;
++	int			 rentries;	 /* receive count */
++	int			 wentries;   /* sent count */
++	enum jzdma_type          dma_type;
++	u32			 dma_flag;
++
++	void			(*set_cs)(struct ingenic_spi_info *spi, u8 cs, unsigned int pol);
++
++	/* functions to deal with different size buffers */
++	u32 (*get_rx) (struct ingenic_sslv *);
++	u32 (*get_tx) (struct ingenic_sslv *);
++	int (*txrx_bufs)(struct ingenic_sslv *spi, struct spi_transfer *t);
++	irqreturn_t (*irq_callback)(struct ingenic_sslv *);
++
++	struct dma_chan 	*txchan;
++	struct dma_chan 	*rxchan;
++	struct scatterlist  	*sg_rx;	/* I/O scatter list */
++	struct scatterlist  	*sg_tx;	/* I/O scatter list */
++
++	unsigned long src_clk;
++	unsigned long spi_clk;
++
++	struct ingenic_intr_cnt *g_ingenic_intr;
++
++	struct resource		*ioarea;
++	struct device		*dev;
++
++	struct ingenic_spi_info *pdata;
++};
++
++struct ingenic_intr_cnt{
++	int dma_tx_cnt;
++	int dma_rx_cnt;
++	int ssi_intr_cnt;
++	int max_ssi_intr;
++	int ssi_txi;
++	int ssi_rxi;
++	int ssi_eti;
++	int ssi_eri;
++	int ssi_rlen;
++	int dma_tx_err;
++	int dma_tx_end;
++	int dma_rx_err;
++	int dma_rx_end;
++};
++
++int ingenic_sslv_init_setup(struct ingenic_sslv *);
++
++void inline ss_write(struct ingenic_sslv *hw, unsigned int offset, unsigned int value)
++{
++	writel(value, (hw->iomem + offset));
++}
++
++unsigned int inline ss_read(struct ingenic_sslv *hw, unsigned int offset)
++{
++	return readl(hw->iomem + offset);
++}
++
++/* the functions is about SSI_SLV control register */
++void inline set_frame_length(struct ingenic_sslv *hw, unsigned int len)
++{
++	unsigned int value = ss_read(hw, CTRLR0);
++	value &= ~DFS_MASK_BITS;
++	value |= ((len - 1) << 16);
++	/*err bit, will delete*/
++	value &= ~(1<<31);
++	ss_write(hw, CTRLR0, value);
++}
++
++void inline set_control_length(struct ingenic_sslv *hw, unsigned int len)
++{
++	unsigned int value = ss_read(hw, CTRLR0);
++	value &= ~DCS_MASK_BITS;
++	value |= ((len - 1) << 12);
++	value &= ~(1<<31);
++	ss_write(hw, CTRLR0, value);
++}
++void inline set_polcph_mode(struct ingenic_sslv *hw,unsigned int mode)
++{
++	unsigned int value = ss_read(hw, CTRLR0);
++	value &= ~(0x3<<6);
++	value |= (mode<<6);
++	value &= ~(1<<31);
++	ss_write(hw, CTRLR0, value);
++}
++
++void inline set_default_format(struct ingenic_sslv *hw,unsigned int mode)
++{
++	unsigned int value = ss_read(hw, CTRLR0);
++	value &= ~((3<<21) | (3<<4));
++	value &= ~(1<<31);
++	ss_write(hw, CTRLR0, value);
++}
++
++void inline set_transfer_mode(struct ingenic_sslv *hw, unsigned int mode)
++{
++	unsigned int value = ss_read(hw, CTRLR0);
++	if(mode == 0x2) {
++		value |= (0x1 << 10);
++	} else {
++		value &= ~(0x1 << 10);
++	}
++	value &= ~(3<<8);
++	value |= mode<<8;
++	value &= ~(1<<31);
++	ss_write(hw, CTRLR0, value);
++}
++
++void inline start_config_regs(struct ingenic_sslv *hw)
++{
++	/* printk(">>>>>>>>>%s %d\n",__func__,__LINE__); */
++	ss_write(hw, SSIENR, SSI_DISEN);
++}
++
++void inline start_transmit(struct ingenic_sslv *hw)
++{
++	ss_write(hw, SSIENR, SSI_EN);
++}
++
++void inline finish_transmit(struct ingenic_sslv *hw)
++{
++	/* printk(">>>>>>>>>%s %d\n",__func__,__LINE__); */
++	ss_write(hw, SSIENR, SSI_DISEN);
++}
++
++void inline set_tx_trigger(struct ingenic_sslv *hw, int value)
++{
++	value = value >= 1 ? value : 1;
++	ss_write(hw, TXFTLR, (value & 0x3f));
++}
++
++void inline set_rx_trigger(struct ingenic_sslv *hw, int value)
++{
++	value = value >= 1 ? value : 1;
++	ss_write(hw, RXFTLR, ((value - 1) & 0x3f));
++}
++
++int inline read_txfifo_entries(struct ingenic_sslv *hw)
++{
++	return ss_read(hw, TXFLR);
++}
++
++int inline read_rxfifo_entries(struct ingenic_sslv *hw)
++{
++	return ss_read(hw, RXFLR);
++}
++
++void inline disable_all_interrupts(struct ingenic_sslv *hw)
++{
++	ss_write(hw, SLV_IMR, 0x0);
++}
++
++void inline enable_all_interrupts(struct ingenic_sslv *hw)
++{
++	ss_write(hw, SLV_IMR, 0x1f);
++}
++
++void inline disable_rxfifo_threshold_intr(struct ingenic_sslv *hw)
++{
++	unsigned int value = ss_read(hw, SLV_IMR);
++	value &= ~RXFIM;
++	ss_write(hw, SLV_IMR, value);
++}
++
++void inline enable_rxfifo_threshold_intr(struct ingenic_sslv *hw)
++{
++	unsigned int value = ss_read(hw, SLV_IMR);
++	value |= RXFIM;
++	ss_write(hw, SLV_IMR, value);
++}
++
++void inline disable_rxfifo_overflow_intr(struct ingenic_sslv *hw)
++{
++	unsigned int value = ss_read(hw, SLV_IMR);
++	value &= ~RXOIM;
++	ss_write(hw, SLV_IMR, value);
++}
++
++void inline enable_rxfifo_overflow_intr(struct ingenic_sslv *hw)
++{
++	unsigned int value = ss_read(hw, SLV_IMR);
++	value |= RXOIM;
++	ss_write(hw, SLV_IMR, value);
++}
++
++void inline disable_rxfifo_empty_intr(struct ingenic_sslv *hw)
++{
++	unsigned int value = ss_read(hw, SLV_IMR);
++	value &= ~RXUIM;
++	ss_write(hw, SLV_IMR, value);
++}
++
++void inline enable_rxfifo_empty_intr(struct ingenic_sslv *hw)
++{
++	unsigned int value = ss_read(hw, SLV_IMR);
++	value |= RXUIM;
++	ss_write(hw, SLV_IMR, value);
++}
++
++void inline disable_txfifo_threshold_intr(struct ingenic_sslv *hw)
++{
++	unsigned int value = ss_read(hw, SLV_IMR);
++	value &= ~TXEIM;
++	ss_write(hw, SLV_IMR, value);
++}
++
++void inline enable_txfifo_threshold_intr(struct ingenic_sslv *hw)
++{
++	unsigned int value = ss_read(hw, SLV_IMR);
++	value |= TXEIM;
++	ss_write(hw, SLV_IMR, value);
++}
++
++void inline disable_txfifo_overflow_intr(struct ingenic_sslv *hw)
++{
++	unsigned int value = ss_read(hw, SLV_IMR);
++	value &= ~TXOIM;
++	ss_write(hw, SLV_IMR, value);
++}
++
++void inline enable_txfifo_overflow_intr(struct ingenic_sslv *hw)
++{
++	unsigned int value = ss_read(hw, SLV_IMR);
++	value |= TXOIM;
++	ss_write(hw, SLV_IMR, value);
++}
++
++void inline clear_all_interrupt(struct ingenic_sslv *hw)
++{
++	ss_read(hw, TXOICR);
++	ss_read(hw, RXOICR);
++	ss_read(hw, RXUICR);
++}
++
++void inline wait_for_sslv_idle(struct ingenic_sslv *hw)
++{
++	while(ss_read(hw, SLV_SR) & SR_BUSY);
++}
++
++void inline enable_tx_dmamode(struct ingenic_sslv *hw)
++{
++	unsigned int value = ss_read(hw, DMACR);
++	value |= TDMAE;
++	ss_write(hw, DMACR, value);
++}
++
++void inline enable_rx_dmamode(struct ingenic_sslv *hw)
++{
++	unsigned int value = ss_read(hw, DMACR);
++	value |= RDMAE;
++	ss_write(hw, DMACR, value);
++}
++
++void inline disable_tx_dmamode(struct ingenic_sslv *hw)
++{
++	unsigned int value = ss_read(hw, DMACR);
++	value &= ~TDMAE;
++	ss_write(hw, DMACR, value);
++}
++
++void inline disable_rx_dmamode(struct ingenic_sslv *hw)
++{
++	unsigned int value = ss_read(hw, DMACR);
++	value &= ~RDMAE;
++	ss_write(hw, DMACR, value);
++}
++
++int inline set_txdma_threshold(struct ingenic_sslv *hw, unsigned int value)
++{
++	int ret = 0;
++	if(value > 0x3f)
++		ret = -EINVAL;
++	else
++		ss_write(hw, DMATDLR, value & 0x3f);
++	return ret;
++}
++
++int inline set_rxdma_threshold(struct ingenic_sslv *hw, unsigned int value)
++{
++	int ret = 0;
++	if(value > 0x3f)
++		ret = -EINVAL;
++	else
++		ss_write(hw, DMARDLR, (value - 1) & 0x3f);
++	return ret;
++}
++
++static inline void set_loop(struct ingenic_sslv *hw, u32 mode)
++{
++	u32 value = ss_read(hw, CTRLR0);
++	if(mode)
++		value |= SRL_TEST;
++	else if(mode == 0)
++		value &= ~SRL_TEST;
++	value &= ~(0x1<<31);
++	ss_write(hw, CTRLR0, value);
++}
++static inline void transmit_data(struct ingenic_sslv *hw, u32 value)
++{
++	ss_write(hw, SSLV_DR, value);
++}
++#endif /*__SPI_SLV_H__*/
+diff --git a/module_drivers/drivers/spi/ingenic_spi.c b/module_drivers/drivers/spi/ingenic_spi.c
+new file mode 100755
+index 000000000..51e12e17f
+--- /dev/null
++++ b/module_drivers/drivers/spi/ingenic_spi.c
+@@ -0,0 +1,1505 @@
++/* linux/drivers/spi/ingenic_spi.c
++ *
++ * SSI controller for SPI protocol,use FIFO and DMA;
++ * base-to: linux/drivers/spi/spi_bitbang.c
++ *
++ * Copyright (c) 2010 Ingenic
++ * Author:Shumb <sbhuang@ingenic.cn>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++*/
++
++#include <linux/init.h>
++#include <linux/spinlock.h>
++#include <linux/workqueue.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/gpio.h>
++#include <linux/platform_device.h>
++#include <linux/spi/spi.h>
++#include <linux/spi/spi_bitbang.h>
++#include <linux/module.h>
++#include <linux/of_gpio.h>
++#include <asm/uaccess.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++#include "ingenic_spi.h"
++
++/* #define SSI_DEGUG */
++#ifdef SSI_DEGUG
++#define  print_dbg(format,arg...)				\
++	printk(format,## arg)
++#else
++#define  print_dbg(format,arg...)
++#endif
++
++#define INGENIC_SPI_RX_BUF(type)							\
++	u32 ingenic_spi_rx_buf_##type(struct ingenic_spi *ingspi)	\
++	{														\
++		u32 data  = spi_readl(ingspi, SSI_DR);					\
++		type * rx = (type *)ingspi->rx;							\
++		*rx++ = (type)(data);								\
++		ingspi->rx = (u8 *)rx;									\
++		return (u32)data;									\
++	}
++
++#define INGENIC_SPI_TX_BUF(type)							\
++	u32 ingenic_spi_tx_buf_##type(struct ingenic_spi *ingspi)	\
++	{														\
++		u32 data;											\
++		const type * tx = (type *)ingspi->tx;					\
++		data = *tx++;										\
++		ingspi->tx = (u8 *)tx;									\
++		transmit_data(ingspi, data);							\
++		return (u32)data;									\
++	}
++
++INGENIC_SPI_RX_BUF(u8)
++INGENIC_SPI_TX_BUF(u8)
++
++INGENIC_SPI_RX_BUF(u16)
++INGENIC_SPI_TX_BUF(u16)
++
++INGENIC_SPI_RX_BUF(u32)
++INGENIC_SPI_TX_BUF(u32)
++
++/* the spi->mode bits understood by this driver: */
++#define MODEBITS (SPI_3WIRE | SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST | SPI_LOOP)
++#define SPI_BITS_SUPPORT  (SPI_BITS_8 | SPI_BITS_16 | SPI_BITS_32)
++
++static void ingenic_spi_cs(struct ingenic_spi_info *spi, u8 cs, unsigned int pol)
++{
++	u32 cs_gpio = spi->chipselects[cs];
++	if(gpio_is_valid(cs_gpio)) {
++		gpio_direction_output(cs_gpio, !pol ? 0 : 1);
++	}
++}
++
++static void ingenic_spi_chipsel(struct spi_device *spi, int value)
++{
++	struct ingenic_spi *ingspi = spi_master_get_devdata(spi->master);
++	unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
++
++	switch (value) {
++	case BITBANG_CS_INACTIVE:
++		/* chip disable selected */
++		if (ingspi->set_cs && ingspi->pdata)
++			ingspi->set_cs(ingspi->pdata, spi->chip_select, cspol^1);
++		break;
++	case BITBANG_CS_ACTIVE:
++		/* chip enable selected */
++		if (ingspi->set_cs && ingspi->pdata)
++			ingspi->set_cs(ingspi->pdata, spi->chip_select, cspol);
++		break;
++	default:
++		break;
++	}
++}
++
++static void ingenic_spi_clk_enable(struct ingenic_spi *ingspi) {
++	if(ingspi->clk_flag == 0)
++		return;
++
++	clk_prepare_enable(ingspi->clk_cgu);
++	clk_prepare_enable(ingspi->clk_gate);
++	ingspi->clk_flag = 0;
++}
++
++static void ingenic_spi_clk_disable(struct ingenic_spi *ingspi) {
++	if(ingspi->clk_flag)
++		return;
++
++	clk_disable_unprepare(ingspi->clk_cgu);
++	clk_disable_unprepare(ingspi->clk_gate);
++	ingspi->clk_flag = 1;
++}
++
++static unsigned long ingenic_spi_clk_get_rate(struct spi_device *spi)
++{
++	struct ingenic_spi *ingspi = spi_master_get_devdata(spi->master);
++	unsigned long rate;
++	u16 cgv;
++
++	spin_lock(&ingspi->lock);
++	rate = clk_get_rate(ingspi->clk_cgu);
++	cgv = spi_readl(ingspi, SSI_GR);
++	spin_unlock(&ingspi->lock);
++	return (rate / (2 * (cgv + 1)));
++}
++static int ingenic_spi_clk_set_rate(struct spi_device *spi, unsigned long rate)
++{
++	struct ingenic_spi *ingspi = spi_master_get_devdata(spi->master);
++	unsigned long parent_clk = 0;
++	unsigned long cur_rate, real_rate = 0;
++	int cgv, ret;
++
++	cur_rate = ingenic_spi_clk_get_rate(spi);
++	if(cur_rate == rate)
++		return 0;
++
++	ingspi->clk_parent = clk_get_parent(ingspi->clk_cgu);
++	parent_clk = clk_get_rate(ingspi->clk_parent);
++	ret = clk_set_rate(ingspi->clk_cgu, 2 * rate);
++	if(ret){
++		printk("---------> clk_set_rate operation failed!!!\n");
++		return ret;
++	}
++	real_rate = clk_get_rate(ingspi->clk_cgu) / 2;/* SSI clock 2 division */
++	if(real_rate <= rate){
++		cgv = 0;
++	}else{
++		if((real_rate % rate) >= (rate / 2)){
++			cgv = real_rate / rate;
++		}else{
++			cgv = real_rate / rate - 1;
++		}
++		if(cgv > 255){
++			cgv = 255;
++			printk("-------> Setting frequency too lowi!!!\n");
++		}
++	}
++
++	spin_lock(&ingspi->lock);
++	spi_writel(ingspi, SSI_GR, cgv);
++	spin_unlock(&ingspi->lock);
++	return 0;
++}
++
++static void dma_tx_callback(void *data)
++{
++	struct ingenic_spi *ingspi = data;
++	complete(&ingspi->done_tx_dma);
++}
++
++static void dma_rx_callback(void *data)
++{
++	struct ingenic_spi *ingspi = data;
++
++	dma_unmap_sg(ingspi->txchan->device->dev, ingspi->sg_tx, 1, DMA_TO_DEVICE);
++	complete(&ingspi->done_rx_dma);
++}
++
++static int ingenic_spi_dma_txrx(struct spi_device *spi, struct spi_transfer *t)
++{
++	int ret;
++	struct ingenic_spi *ingspi = spi_master_get_devdata(spi->master);
++	struct dma_slave_config rx_config, tx_config;
++	struct dma_async_tx_descriptor *rxdesc;
++	struct dma_async_tx_descriptor *txdesc;
++	struct dma_chan *rxchan = ingspi->rxchan;
++	struct dma_chan *txchan = ingspi->txchan;
++	struct ingenic_intr_cnt *g_ingenic_intr;
++	int dma_ds[] = {64, 32, 16, 4, 2, 1};
++	int i;
++
++	/* Check that the channels are available */
++	if (!txchan || !rxchan) {
++		dev_err(&spi->dev, "no dma channel\n");
++		return -ENODEV;
++	}
++
++	if (t->len % ingspi->transfer_unit_size) {
++		pr_err("The length of tranfer data is error\n");
++		return -EFAULT;
++	}
++
++	ingspi->rw_mode = 0;
++	if(t->tx_buf)
++		ingspi->rw_mode |= W_MODE;
++	if(t->rx_buf)
++		ingspi->rw_mode |= R_MODE;
++
++	/* all transfer starts with tx, ends with rx. */
++	if (ingspi->rw_mode & W_MODE)
++		ingspi->tx = t->tx_buf;
++	else
++		ingspi->tx = ingspi->buffer;
++
++	if (ingspi->rw_mode & R_MODE)
++		ingspi->rx = t->rx_buf;
++	else
++		ingspi->rx = ingspi->buffer;
++
++	memset(ingspi->buffer, 0, BUFFER_SIZE);
++
++	switch (ingspi->transfer_unit_size) {
++	case SPI_8BITS:
++		tx_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
++		tx_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
++		rx_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
++		rx_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
++		tx_config.dst_maxburst = 1;
++		tx_config.src_maxburst = 1;
++		rx_config.src_maxburst = 1;
++		rx_config.dst_maxburst = 1;
++		break;
++	case SPI_16BITS:
++		tx_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++		tx_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++		rx_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++		rx_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++		tx_config.dst_maxburst = 1;
++		tx_config.src_maxburst = 1;
++		rx_config.src_maxburst = 1;
++		rx_config.dst_maxburst = 1;
++		break;
++	case SPI_32BITS:
++		tx_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++		tx_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++		rx_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++		rx_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++		tx_config.dst_maxburst = 1;
++		tx_config.src_maxburst = 1;
++		rx_config.src_maxburst = 1;
++		rx_config.dst_maxburst = 1;
++		break;
++	}
++
++	tx_config.dst_addr = (dma_addr_t)(ingspi->phys + SSI_DR);
++	rx_config.src_addr = (dma_addr_t)(ingspi->phys + SSI_DR);
++
++	tx_config.direction = DMA_MEM_TO_DEV;
++	rx_config.direction = DMA_DEV_TO_MEM;
++
++	tx_config.slave_id = 0;
++	rx_config.slave_id = 0;
++
++	dmaengine_slave_config(txchan, &tx_config);
++	dmaengine_slave_config(rxchan, &rx_config);
++
++	/* set tx dma trigger */
++	for (i = 0; i < ARRAY_SIZE(dma_ds); i++) {
++		if (t->len / dma_ds[i])
++			break;
++	}
++
++	if (i < ARRAY_SIZE(dma_ds)) {
++		ingspi->dma_tx_unit = dma_ds[i];
++	} else {
++		print_dbg("DMA tx block_size force to defaut set!!!");
++		ingspi->dma_tx_unit = INGENIC_SSI_DMA_BURST_LENGTH;
++	}
++
++	ingspi->tx_trigger = ingspi->dma_tx_unit / (ingspi->txfifo_width >> 3);
++	//set_tx_trigger(ingspi, ingspi->tx_trigger);
++	set_tx_trigger(ingspi, 0); //The transfer is steady if the trigger number is used
++	print_dbg("t->len: %d, tx fifo width: %d, set tx trigger value to %d\n", t->len, ingspi->txfifo_width, ingspi->tx_trigger);
++
++	if (t->tx_buf) {
++		txdesc = dmaengine_prep_slave_sg(
++				txchan,
++				t->tx_sg.sgl, t->tx_sg.nents,
++				DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
++	} else {
++		sg_init_one(ingspi->sg_tx, ingspi->buffer, t->len);
++
++		if (dma_map_sg(ingspi->txchan->device->dev,
++				ingspi->sg_tx, 1, DMA_TO_DEVICE) != 1) {
++			dev_err(&spi->dev, "dma_map_sg tx error\n");
++			printk("%s LINE %d: %s\n", __func__, __LINE__, __FILE__);
++			goto err_tx_sgmap;
++		}
++		txdesc = dmaengine_prep_slave_sg(
++					txchan,
++					ingspi->sg_tx, 1,
++					DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
++	}
++
++	if (!txdesc) {
++		dev_err(&spi->dev, "device_prep_slave_sg error\n");
++		printk("%s LINE %d: %s\n", __func__, __LINE__, __FILE__);
++		goto err_txdesc;
++	}
++
++	// config controller
++	disable_tx_intr(ingspi);
++	disable_rx_intr(ingspi);
++
++	//revisit
++	disable_tx_error_intr(ingspi);
++	disable_rx_error_intr(ingspi);
++
++	start_transmit(ingspi);
++	//finish_transmit(ingspi);
++
++	flush_fifo(ingspi);
++
++	enable_receive(ingspi);
++	clear_errors(ingspi);
++
++	g_ingenic_intr = ingspi->g_ingenic_intr;
++	memset(g_ingenic_intr, 0, sizeof *g_ingenic_intr);
++
++	if (!(ingspi->rw_mode & R_MODE)) {
++		txdesc->callback = dma_tx_callback;
++		txdesc->callback_param = ingspi;
++		enable_tx_error_intr(ingspi);
++
++		dmaengine_submit(txdesc);
++		dma_async_issue_pending(txchan);
++
++		ret = wait_for_completion_interruptible_timeout(&ingspi->done_tx_dma, 60 * HZ);
++		if (ret <= 0) {
++			printk("The tx_dma umap wait timeout\n");
++			goto err_txdesc;
++		}
++		ret = wait_for_completion_interruptible_timeout(&ingspi->done, 60 * HZ);
++		if (ret <= 0) {
++			printk("The spi transfer wait timeout\n");
++			goto err_txdesc;
++		}
++
++		finish_transmit(ingspi);
++		flush_rxfifo(ingspi);
++		clear_errors(ingspi);
++
++		return t->len;
++	}
++	/*  prepare spi dma rx */
++	for (i = 0; i < ARRAY_SIZE(dma_ds); i++) {
++		if (!(t->len % dma_ds[i]))
++			break;
++	}
++
++	if (i < ARRAY_SIZE(dma_ds)) {
++		ingspi->dma_rx_unit = dma_ds[i];
++	} else {
++		print_dbg("DMA rx block_size force to defaut set!!!");
++		ingspi->dma_rx_unit = INGENIC_SSI_DMA_BURST_LENGTH;
++	}
++
++	ingspi->rx_trigger = ingspi->dma_rx_unit/(ingspi->rxfifo_width >> 3);
++	//set_rx_trigger(ingspi, ingspi->rx_trigger);
++	set_rx_trigger(ingspi, 0); //the rx trigger is steady for tranfer
++	print_dbg("t->len: %d, rx fifo width: %d, set rx trigger value to %d\n", t->len, ingspi->rxfifo_width, ingspi->rx_trigger);
++
++	if (t->rx_buf) {
++		rxdesc = dmaengine_prep_slave_sg(
++				rxchan,
++				t->rx_sg.sgl, t->rx_sg.nents,
++				DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
++	}
++
++	if (!rxdesc) {
++		dev_err(&spi->dev, "device_prep_slave_sg error\n");
++		goto err_rxdesc;
++	}
++
++	txdesc->callback = NULL;
++	txdesc->callback_param = NULL;
++
++	rxdesc->callback = dma_rx_callback;
++	rxdesc->callback_param = ingspi;
++	enable_rx_error_intr(ingspi);
++	enable_tx_error_intr(ingspi);
++
++	dmaengine_submit(txdesc);
++	dmaengine_submit(rxdesc);
++	dma_async_issue_pending(rxchan);
++	dma_async_issue_pending(txchan);
++
++	ret = wait_for_completion_interruptible_timeout(&ingspi->done_rx, 60 * HZ);
++	if (ret <= 0) {
++		dump_spi_reg(ingspi);
++		printk("The spi receiver wait timeout\n");
++		goto err_rxdesc;
++	}
++
++	ret = wait_for_completion_interruptible_timeout(&ingspi->done_rx_dma, 60 * HZ);
++	if (ret <= 0) {
++		dump_spi_reg(ingspi);
++		printk("The spi dam_callback wait timeout\n");
++		goto err_rxdesc;
++	}
++
++	finish_transmit(ingspi);
++	//flush_rxfifo(ingspi);
++	clear_errors(ingspi);
++
++	return t->len;
++
++err_rxdesc:
++err_txdesc:
++	dma_unmap_sg(txchan->device->dev, ingspi->sg_tx, 1, DMA_TO_DEVICE);
++err_tx_sgmap:
++	printk("<< dma_txrx error. out of memory >>\n");
++	return -ENOMEM;
++}
++
++static irqreturn_t ingenic_spi_dma_irq_callback(struct ingenic_spi *ingspi)
++{
++	struct ingenic_intr_cnt *g_ingenic_intr = ingspi->g_ingenic_intr;
++	print_dbg("%s: status register: %08x\n", __func__, spi_readl(ingspi, SSI_SR));
++
++	if (ssi_underrun(ingspi) && tx_error_intr(ingspi)) {
++		print_dbg("UNDR:\n");
++
++		g_ingenic_intr->ssi_eti++;
++		disable_tx_error_intr(ingspi);
++
++		clear_errors(ingspi);
++		complete(&ingspi->done);
++		complete(&ingspi->done_rx);
++
++		goto irq_done;
++	}
++
++	if (ssi_overrun(ingspi) && rx_error_intr(ingspi)) {
++			print_dbg(" overrun:\n");
++			g_ingenic_intr->ssi_eri++;
++
++			clear_errors(ingspi);
++			complete(&ingspi->done);
++			complete(&ingspi->done_rx);
++	}
++
++irq_done:
++	return IRQ_HANDLED;
++}
++
++static inline u32 cpu_read_rxfifo(struct ingenic_spi *ingspi)
++{
++	u8 unit_size = ingspi->transfer_unit_size;
++	u32 cnt, dat;
++	int dummy_read = 0;
++
++	print_dbg("The count of RxFIFO is %d \n", get_rxfifo_count(ingspi));
++	if (get_rxfifo_count(ingspi) < 1)
++		return 0;
++
++	cnt = ingspi->rlen;
++	if ((ingspi->rw_mode & RW_MODE) == W_MODE) {
++		print_dbg("W_MODE\n");
++		dummy_read = 1;
++	}
++
++	spin_lock(&ingspi->lock);
++
++	while (!rxfifo_empty(ingspi)) {
++		ingspi->rlen += unit_size;
++		if (dummy_read){
++			dat = spi_readl(ingspi, SSI_DR);
++		} else {
++			dat = ingspi->get_rx(ingspi);
++			ingspi->r_count--;
++		}
++	}
++
++	spin_unlock(&ingspi->lock);
++
++	return (ingspi->rlen - cnt);
++}
++
++static inline u32 cpu_write_txfifo(struct ingenic_spi *ingspi, u32 entries)
++{
++	u8 unit_size = ingspi->transfer_unit_size;
++	u32 i, cnt, count;
++	u32 dat;
++
++	if ((!entries ) || (!(ingspi->rw_mode & RW_MODE)))
++		return 0;
++
++	cnt = entries;
++	count = cnt * unit_size;
++
++	spin_lock(&ingspi->lock);
++	if (ingspi->rw_mode & W_MODE) {
++		for (i = 0; i < cnt; i++) {
++			ingspi->count += unit_size;
++			dat = (u32)(ingspi->get_tx(ingspi));
++			ingspi->t_count--;
++		}
++	} else {		 /* read, fill txfifo with 0 */
++		for (i = 0; i < cnt; i++) {
++			ingspi->count += unit_size;
++			transmit_data(ingspi, 0);
++			ingspi->t_count--;
++		}
++	}
++	spin_unlock(&ingspi->lock);
++
++	return count;
++}
++
++static int ingenic_spi_cpu_transfer(struct ingenic_spi *ingspi)
++{
++	u32 retlen, w_entries;
++
++	if (ingspi->t_count <= ingspi->fifodepth) {
++		/* last transfer */
++		w_entries = ingspi->t_count;
++		ingspi->last_transfer = 1;
++
++	} else {
++
++		/* continue transfer */
++		w_entries = ingspi->fifodepth - ingspi->tx_trigger;	/* 128 - tx_trigger */
++		start_transmit(ingspi);
++	}
++
++	/* write fifo */
++	retlen = cpu_write_txfifo(ingspi, w_entries);
++	if (!retlen) {
++		dev_info(ingspi->dev,"cpu_write_txfifo error!\n");
++		return -1;
++	}
++
++	/* wait fifo empty to finish transfer */
++	if(ingspi->last_transfer)
++		finish_transmit(ingspi);
++
++	/* enable interrupt */
++	enable_tx_intr(ingspi);
++	if (ingspi->rw_mode & R_MODE)
++		enable_rx_intr(ingspi);
++
++	print_dbg("+:(%d)\n", retlen);
++
++#ifdef SSI_DEGUG
++	dump_spi_reg(ingspi);
++#endif
++	return 0;
++}
++
++/*
++ * Wait until SSI is idle, or timeout occurs.
++ * Returns non-zero if error.
++ */
++static int ingenic_wait_transfer_busy(struct ingenic_spi *ingspi)
++{
++	unsigned long deadline;
++	int timeout = 0;
++	int status = 0;
++
++	/* timeout period is 1s */
++	deadline = jiffies + msecs_to_jiffies(1000);
++
++	while (!timeout) {
++		if (time_after_eq(jiffies, deadline))
++			timeout = 1;
++
++		spin_lock(&ingspi->lock);
++		status = transfer_busy(ingspi);
++		spin_unlock(&ingspi->lock);
++
++		if (!status)
++			return 0;
++
++		cond_resched();
++	}
++
++	return -ETIMEDOUT;
++}
++
++static int ingenic_spi_pio_txrx(struct spi_device *spi, struct spi_transfer *t)
++{
++	struct ingenic_spi *ingspi = spi_master_get_devdata(spi->master);
++	u32 entries;
++	int status;
++	unsigned long flags;
++	int is_timeout;
++
++	ingspi->tx = t->tx_buf;
++	ingspi->rx = t->rx_buf;
++	ingspi->len = t->len;
++	ingspi->count = 0;
++	ingspi->r_count = 0;
++	ingspi->t_count = 0;
++	ingspi->rlen = 0;
++	ingspi->rw_mode = 0;
++	ingspi->last_transfer = 0;
++	ingspi->dma_flag &= ~SPI_DMA_ACK;
++	ingspi->tx_trigger = SSI_TX_FIFO_THRESHOLD * 8;
++	ingspi->rx_trigger = SSI_RX_FIFO_THRESHOLD * 8;
++
++
++	disable_tx_intr(ingspi);
++	disable_rx_intr(ingspi);
++
++	finish_transmit(ingspi);
++	disable_receive_continue(ingspi);
++	flush_fifo(ingspi);
++	clear_errors(ingspi);
++
++	/* deal entries */
++	entries = (t->len << 3) >> (ffs(ingspi->txfifo_width) - 1);
++	ingspi->t_count = entries;
++
++	if(ingspi->tx)
++		ingspi->rw_mode |= W_MODE;
++
++	if(ingspi->rx) {
++		ingspi->rw_mode |= R_MODE;
++		ingspi->r_count = entries;
++	}
++
++	/* deal receive mode */
++	if (ingspi->rw_mode & R_MODE) {
++		/* enable receive */
++		if (ingspi->r_count < ingspi->rx_trigger) {
++			ingspi->rx_trigger = ingspi->r_count;
++		}
++		/* set rx trigger */
++		set_rx_trigger(ingspi, ingspi->rx_trigger);
++		enable_receive(ingspi);
++	} else {
++		/* disable receive */
++		disable_receive(ingspi);
++	}
++	/* set rx trigger */
++	set_tx_trigger(ingspi, ingspi->tx_trigger);
++
++
++	/* This start SSI transfer, write data or 0 to txFIFO.
++	 * irq is locked to protect SSI config registers */
++	spin_lock_irqsave(&ingspi->txrx_lock, flags);
++	status = ingenic_spi_cpu_transfer(ingspi);
++	if (status < 0) {
++		dev_err(ingspi->dev,"ERROR:spi_transfer error(%d)!\n", status);
++		disable_tx_intr(ingspi);
++		disable_rx_intr(ingspi);
++		spin_unlock_irqrestore(&ingspi->txrx_lock, flags);
++
++		return status;
++	}
++	spin_unlock_irqrestore(&ingspi->txrx_lock, flags);
++
++	/* wait the interrupt finish the transfer( one spi_transfer be sent ) */
++	wait_for_completion_interruptible(&ingspi->done);
++
++	/* wait until SSI is idle */
++	is_timeout = ingenic_wait_transfer_busy(ingspi);
++
++	/* finish transfer and receive */
++	if (ingspi->rw_mode & W_MODE)
++		finish_transmit(ingspi);
++	if (ingspi->rw_mode & R_MODE)
++		disable_receive(ingspi);
++
++	/* finish clear state */
++	flush_fifo(ingspi);
++	clear_errors(ingspi);
++
++	/*
++	 * in order to flush fifo and clear errors
++	 * if wait until SSI is idle timeout.
++	 */
++	if (is_timeout == -ETIMEDOUT) {
++		dev_err(ingspi->dev, "Wait until SSI is idle timeout!\n");
++		return -ETIMEDOUT;
++	}
++
++	/* overrun error */
++	if(ingspi->r_count)
++		return -EIO;
++
++	if ((ingspi->rw_mode & R_MODE) && (ingspi->rlen != t->len)) {
++		dev_info(ingspi->dev, "Length error:ingspi->rlen=%d  t->len=%d\n", ingspi->rlen,t->len);
++
++		if(ingspi->rlen > ingspi->len)
++			ingspi->rlen = ingspi->len;
++	} else if ((ingspi->rw_mode & RW_MODE) == W_MODE) {
++		ingspi->rlen = ingspi->count;
++	}
++
++	return ingspi->rlen;
++}
++
++static irqreturn_t ingenic_spi_pio_irq_callback(struct ingenic_spi *ingspi)
++{
++	u32 cnt;
++	int status;
++
++	/* Write only or full duplex transmission done */
++	if (!ingspi->t_count && !ingspi->r_count) {
++		print_dbg("done:");
++		goto done;
++	}
++
++	if ( ssi_underrun(ingspi) && tx_error_intr(ingspi) ) {
++
++		print_dbg("TEI:(underrun):");
++		clear_errors(ingspi);
++
++		if (!ingspi->t_count && !ingspi->r_count)
++			goto done;
++
++	}
++
++	if ( ssi_overrun(ingspi) && rx_error_intr(ingspi) ) {
++
++		dev_err(ingspi->dev,"overrun error!\n");
++		print_dbg("REI:(overrun):");
++		goto done;
++	}
++
++	if ( rxfifo_half_full(ingspi) &&
++		rxfifo_half_full_intr(ingspi)) {
++
++		print_dbg("RXI:");
++		cnt = cpu_read_rxfifo(ingspi);
++		print_dbg("-:(%d)\n",cnt);
++
++		if (!ingspi->t_count && !ingspi->r_count)
++			goto done;
++
++		if (ingspi->r_count < ingspi->rx_trigger) {
++			ingspi->rx_trigger = ingspi->r_count;
++			set_rx_trigger(ingspi, ingspi->rx_trigger);
++		}
++	}
++
++	if ( txfifo_half_empty_intr(ingspi) &&
++		txfifo_half_empty(ingspi)) {
++
++		print_dbg("TXI:");
++
++		if (!ingspi->t_count && !ingspi->r_count)
++			goto done;
++
++		if (ingspi->t_count) {
++			status = ingenic_spi_cpu_transfer(ingspi);
++			if (status < 0) {
++				dev_err(ingspi->dev,"ingenic_spi_cpu_transfer error!\n");
++				goto done;
++			}
++		} else {
++			disable_tx_intr(ingspi);
++		}
++	}
++
++	return IRQ_HANDLED;
++
++done:
++	disable_tx_intr(ingspi);
++	disable_rx_intr(ingspi);
++
++	// flush_fifo(ingspi);
++	// clear_errors(ingspi);
++	complete(&ingspi->done);
++
++	return IRQ_HANDLED;
++}
++
++/* every spi_transfer could call this routine to setup itself */
++static int ingenic_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
++{
++	struct ingenic_spi *ingspi = spi_master_get_devdata(spi->master);
++	u8  bpw, fifo_width;
++	u32 hz;
++	int ret;
++
++	bpw = spi->bits_per_word;
++	hz  = spi->max_speed_hz;
++
++	if (t) {
++		if(t->bits_per_word)
++			bpw = t->bits_per_word;
++		if(t->speed_hz)
++			hz = t->speed_hz;
++	}
++
++	if (bpw < 2 || bpw > 32) {
++		dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
++		return -EINVAL;
++	}
++
++	if (ingspi->use_dma) {
++		ingspi->txrx_bufs = &ingenic_spi_dma_txrx;
++		ingspi->irq_callback = &ingenic_spi_dma_irq_callback;
++	} else {
++		ingspi->txrx_bufs = &ingenic_spi_pio_txrx;
++		ingspi->irq_callback = &ingenic_spi_pio_irq_callback;
++	}
++
++	ingspi->bits_per_word = bpw;
++	if (bpw <= 8) {
++		ingspi->transfer_unit_size = SPI_8BITS;
++		ingspi->get_rx = ingenic_spi_rx_buf_u8;
++		ingspi->get_tx = ingenic_spi_tx_buf_u8;
++		fifo_width = FIFO_W8;
++	} else if (bpw <= 16) {
++		ingspi->transfer_unit_size = SPI_16BITS;
++		ingspi->get_rx = ingenic_spi_rx_buf_u16;
++		ingspi->get_tx = ingenic_spi_tx_buf_u16;
++		fifo_width = FIFO_W16;
++	} else {
++		ingspi->transfer_unit_size = SPI_32BITS;
++		ingspi->get_rx = ingenic_spi_rx_buf_u32;
++		ingspi->get_tx = ingenic_spi_tx_buf_u32;
++		fifo_width = FIFO_W32;
++	}
++
++	ingspi->txfifo_width = fifo_width;
++	ingspi->rxfifo_width = fifo_width;
++	set_frame_length(ingspi, fifo_width);
++
++	if (spi->mode & SPI_LSB_FIRST) {
++		set_tx_lsb(ingspi);
++		set_rx_lsb(ingspi);
++	} else {
++		set_tx_msb(ingspi);
++		set_rx_msb(ingspi);
++	}
++
++	if (spi->mode & SPI_CPHA)
++		set_spi_clock_phase(ingspi, 1);
++	else
++		set_spi_clock_phase(ingspi, 0);
++
++	if (spi->mode & SPI_CPOL)
++		set_spi_clock_polarity(ingspi, 1);
++	else
++		set_spi_clock_polarity(ingspi, 0);
++
++	if (spi->mode & SPI_LOOP)
++		enable_loopback(ingspi);
++	else
++		disable_loopback(ingspi);
++
++	if((ret = ingenic_spi_clk_set_rate(spi, hz)))
++		return ret;
++
++	dev_dbg(&spi->dev, "The real SPI CLK is %ld Hz\n", ingenic_spi_clk_get_rate(spi));
++
++	mutex_lock(&ingspi->bitbang.lock);
++	if (!ingspi->bitbang.busy) {
++		ingspi->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
++		/* need to ndelay for 0.5 clocktick ? */
++	}
++	mutex_unlock(&ingspi->bitbang.lock);
++
++	return 0;
++}
++
++static int ingenic_spi_setup(struct spi_device *spi)
++{
++	struct ingenic_spi *ingspi = spi_master_get_devdata(spi->master);
++	unsigned long flags;
++
++	spin_lock_irqsave(&ingspi->lock, flags);
++	if (ingspi->state & SUSPND) {
++		spin_unlock_irqrestore(&ingspi->lock, flags);
++		dev_err(&spi->dev,
++			"setup: SPI-%d not active!\n", spi->master->bus_num);
++		return -ESHUTDOWN;
++	}
++	spin_unlock_irqrestore(&ingspi->lock, flags);
++
++	if (spi->chip_select >= spi->master->num_chipselect) {
++		dev_err(&spi->dev, "cs%d >= max %d\n",
++			spi->chip_select,
++			spi->master->num_chipselect);
++		return -EINVAL;
++	}
++
++	if (spi->chip_select == 0) {
++		select_ce(ingspi);
++	} else if (spi->chip_select == 1) {
++		select_ce2(ingspi);
++	} else
++		return -EINVAL;
++
++	if (!spi->bits_per_word)
++		spi->bits_per_word = 8;
++
++	if (spi->mode & ~MODEBITS) {
++		dev_info(&spi->dev, "Warning: unsupported mode bits %x\n",
++			spi->mode & ~MODEBITS);
++		return -EINVAL;
++	}
++	ingspi->spi_mode = spi->mode;
++
++	if (spi->mode & SPI_LSB_FIRST) {
++		set_tx_lsb(ingspi);
++		set_rx_lsb(ingspi);
++	} else {
++		set_tx_msb(ingspi);
++		set_rx_msb(ingspi);
++	}
++
++	if (spi->bits_per_word & ~SPI_BITS_SUPPORT) {
++		dev_info(&spi->dev, "Warning: unsupported bits_per_word: %d\n",
++			spi->bits_per_word);
++		return -EINVAL;
++	}
++
++	if (!spi->max_speed_hz) {
++		return -EINVAL;
++	}
++
++	if (ingspi->max_clk < spi->max_speed_hz) {
++		dev_info(&spi->dev, "Warning:invalid clock(%d Hz) be set to source clk(%d Hz)!\n",
++				 spi->max_speed_hz,(uint)ingspi->max_clk);
++		spi->max_speed_hz = ingspi->max_clk;
++	}
++
++	mutex_lock(&ingspi->bitbang.lock);
++	if (!ingspi->bitbang.busy) {
++		ingspi->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
++		/* need to ndelay for 0.5 clocktick ? */
++	}
++	mutex_unlock(&ingspi->bitbang.lock);
++
++	return 0;
++}
++
++/**
++ * ingenic_spi_txrx - functions which will handle transfer data
++ * @spi: spi device on which data transfer to be done
++ * @t: spi transfer in which transfer info is filled
++ *
++ * This function will put data to be transferred into data register
++ * of SPI controller and then wait until the completion will be marked
++ * by the IRQ Handler.
++ */
++static int ingenic_spi_txrx(struct spi_device * spi, struct spi_transfer *t)
++{
++	struct ingenic_spi *ingspi = spi_master_get_devdata(spi->master);
++	unsigned int ret;
++	unsigned long flags;
++
++	spin_lock_irqsave(&ingspi->lock, flags);
++	if (ingspi->state & SUSPND) {
++		ingspi->state &= ~SPIBUSY;
++		spin_unlock_irqrestore(&ingspi->lock, flags);
++		printk("Now enter suspend, so cann't tranfer data\n");
++		return -ESHUTDOWN;
++	}
++	ingspi->state |= SPIBUSY;
++	spin_unlock_irqrestore(&ingspi->lock, flags);
++
++	ret = ingspi->txrx_bufs(spi, t);
++
++	spin_lock_irqsave(&ingspi->lock, flags);
++	ingspi->state &= ~SPIBUSY;
++	spin_unlock_irqrestore(&ingspi->lock, flags);
++	return ret;
++}
++
++static irqreturn_t ingenic_spi_irq(int irq, void *dev)
++{
++	struct ingenic_spi *ingspi = dev;
++
++	return ingspi->irq_callback(ingspi);
++}
++
++static int ingenic_spi_init_setup(struct ingenic_spi *ingspi)
++{
++	ingspi->clk_flag = 1;
++	ingenic_spi_clk_enable(ingspi);
++
++	/* disable the SSI controller */
++	ssi_disable(ingspi);
++
++	/* set default half_intr trigger */
++	ingspi->tx_trigger = SSI_TX_FIFO_THRESHOLD * 8;
++	ingspi->rx_trigger = SSI_RX_FIFO_THRESHOLD * 8;
++	set_tx_trigger(ingspi, ingspi->tx_trigger);
++	set_rx_trigger(ingspi, ingspi->rx_trigger);
++
++	/* First,mask the interrupt, while verify the status ? */
++	disable_tx_intr(ingspi);
++	disable_rx_intr(ingspi);
++
++	disable_receive(ingspi);
++
++	set_spi_clock_phase(ingspi, 0);
++	set_spi_clock_polarity(ingspi, 0);
++	set_tx_msb(ingspi);
++	set_rx_msb(ingspi);
++
++	set_spi_format(ingspi);
++	set_frame_length(ingspi, 8);
++	disable_loopback(ingspi);
++	flush_fifo(ingspi);
++
++	underrun_auto_clear(ingspi);
++	clear_errors(ingspi);
++	ssi_enable(ingspi);
++
++	return 0;
++}
++
++#ifdef CONFIG_OF
++static struct ingenic_spi_info *ingenic_spi_parse_dt(struct ingenic_spi *ingspi)
++{
++	struct ingenic_spi_info *isi;
++	struct device *dev = ingspi->dev;
++	unsigned int value;
++	isi = devm_kzalloc(dev, sizeof(*isi), GFP_KERNEL);
++	if (!isi)
++		return ERR_PTR(-ENOMEM);
++
++	if(of_property_read_u32(dev->of_node, "spi-max-frequency", &value)) {
++		dev_warn(dev, "spi-max-frequency not specified\n");
++		isi->max_clk = 0;
++	} else {
++		isi->max_clk = value;
++	}
++
++	if(of_property_read_u32(dev->of_node, "ingenic,has_dma_support", &value)) {
++		dev_warn(dev, "spi-max-frequency not specified\n");
++		ingspi->use_dma = 0;
++	} else {
++		ingspi->use_dma = value;
++	}
++
++	if (of_property_read_u32(dev->of_node, "ingenic,chnl", &value)) {
++		dev_warn(dev, "ingenic,channel not specified\n");
++		isi->chnl = 0;
++	} else {
++		isi->chnl = value;
++	}
++
++	if (of_property_read_u32(dev->of_node, "num-cs", &value)) {
++		dev_warn(dev, "num_cs not specified\n");
++		isi->num_chipselect = 0;
++	} else {
++		isi->num_chipselect = value;
++	}
++
++	if (of_property_read_u32(dev->of_node, "ingenic,spi-src-clk", &value)) {
++		dev_warn(dev, "ingenic,spi-src-clk not specified\n");
++		isi->src_clk = 0;
++	} else {
++		isi->src_clk = value;
++	}
++
++	if (of_property_read_u32(dev->of_node, "ingenic,allow_cs_same", &value)) {
++		dev_warn(dev, "ingenic,allow_cs_same not specified\n");
++		isi->allow_cs_same = 0;
++	} else {
++		isi->allow_cs_same = value;
++	}
++
++
++	if( (value = of_alias_get_id(dev->of_node, "spi")) < 0) {
++		isi->bus_num = -1;
++	} else {
++		isi->bus_num = value;
++	}
++
++	{
++		int i;
++		for (i = 0; i < isi->num_chipselect; i++) {
++			int cs_gpio = of_get_named_gpio(dev->of_node, "cs-gpios", i);
++
++			if (cs_gpio == -EPROBE_DEFER) {
++				break;
++			}
++			isi->chipselects[i] = cs_gpio;
++			if (gpio_is_valid(cs_gpio)) {
++				if (devm_gpio_request(dev, cs_gpio, "INGENIC_SPI_CS")) {
++					if(!isi->allow_cs_same)
++						dev_err(dev, "could not request %d gpio\n", cs_gpio);
++
++				} else if (gpio_direction_output(cs_gpio, 1))
++					dev_err(dev, "could not set gpio %d as output\n", cs_gpio);
++			}
++		}
++	}
++
++	return isi;
++}
++
++#else
++static struct ingenic_spi_info *ingenic_spi_parse_dt(struct device *dev)
++{
++	return dev_get_platdata(dev);
++}
++#endif
++
++static const struct ingenic_priv default_priv = {
++	.clk_flag = SSI_CLK,
++};
++
++static const struct ingenic_priv cgu_priv = {
++	.clk_flag = SFC_CLK,
++};
++
++static const struct of_device_id ingenic_spi_match[] = {
++
++	{ .compatible = "ingenic,m300-spi", .data = (void *)&default_priv },
++	{ .compatible = "ingenic,x1600-spi", .data = (void *)&default_priv },
++	{ .compatible = "ingenic,x2000-spi", .data = (void *)&default_priv },
++	{ .compatible = "ingenic,x2100-spi", .data = (void *)&default_priv },
++	{ .compatible = "ingenic,x2500-spi", .data = (void *)&default_priv },
++	{}
++};
++MODULE_DEVICE_TABLE(of, ingenic_spi_match);
++
++static int ingenic_spi_clk_init(struct platform_device *pdev, struct ingenic_spi *ingspi)
++{
++	const struct of_device_id *match;
++	struct clk *clk;
++	char clkname[16];
++	int err = 0;
++
++	pdev->id = of_alias_get_id(pdev->dev.of_node, "spi");
++	sprintf(clkname, "gate_ssi%d", pdev->id);
++	ingspi->clk_gate = devm_clk_get(&pdev->dev, clkname);
++
++	match = of_match_node(ingenic_spi_match, pdev->dev.of_node);
++	ingspi->priv = (void*)match->data;
++
++	if(ingspi->priv->clk_flag == SSI_CLK)
++		ingspi->clk_cgu = devm_clk_get(&pdev->dev, "div_ssi");
++	else
++		ingspi->clk_cgu = devm_clk_get(&pdev->dev, "cgu_ssi");
++
++	if (IS_ERR(ingspi->clk_cgu) || IS_ERR(ingspi->clk_gate)) {
++		dev_err(&pdev->dev, "Cannot get spi clock\n");
++		err = PTR_ERR(ingspi->clk_cgu);
++		return err;
++	}
++
++	if(!ingspi->pdata->src_clk) {
++		/* Use external parent clock */
++		clk = devm_clk_get(&pdev->dev, "ext");
++		if(!clk) {
++			dev_err(&pdev->dev, "Cannot get ext clock\n");
++			return -1;
++		}
++	} else {
++		/* Use SSI clock */
++		if(ingspi->priv->clk_flag == SSI_CLK)
++			return 0;
++
++		/* Use SFC parent clock */
++		clk = devm_clk_get(&pdev->dev, "cgu_sfc");
++		if(!clk) {
++			dev_err(&pdev->dev, "Cannot get cgu_sfc clock\n");
++			return -1;
++		}
++	}
++
++	err = clk_set_parent(ingspi->clk_cgu, clk);
++	if(err < 0) {
++		dev_err(&pdev->dev, "clk set  parent failed\n");
++		return -1;
++	}
++	return 0;
++}
++
++static int ingenic_spi_configure_dma(struct ingenic_spi *ingspi)
++{
++	struct device *dev = ingspi->dev;
++	dma_cap_mask_t mask;
++	int err = 0;
++
++	dma_cap_zero(mask);
++	dma_cap_set(DMA_SLAVE, mask);
++
++	ingspi->txchan = dma_request_chan(dev, "tx");
++	if (IS_ERR(ingspi->txchan)) {
++		err = PTR_ERR(ingspi->txchan);
++		if (err == -EPROBE_DEFER) {
++			dev_warn(dev, "no DMA channel available at the moment\n");
++			return err;
++		}
++		dev_err(dev, "DMA TX channel not available, SPI unable to use DMA\n");
++		err = -EBUSY;
++		goto error;
++	}
++
++	/*
++	 * No reason to check EPROBE_DEFER here since we have already requested
++	 * tx channel. If it fails here, it's for another reason.
++	 */
++	ingspi->rxchan = dma_request_chan(dev, "rx");
++
++	if (!ingspi->rxchan) {
++		dev_err(dev, "DMA RX channel not available, SPI unable to use DMA\n");
++		err = -EBUSY;
++		goto error;
++	}
++
++	//alloc temp buffer for dma
++	ingspi->buffer = dma_alloc_coherent(dev, BUFFER_SIZE, &ingspi->buffer_dma, GFP_KERNEL);
++	if (!ingspi->buffer) {
++		dev_err(dev, "SPI request temp dma buffer failed");
++		goto error;
++	}
++
++#if 0
++	ingspi->buffer = kmalloc(BUFFER_SIZE, GFP_KERNEL);
++	if (!ingspi->buffer) {
++		dev_err(dev, "SPI request temp dma buffer failed");
++		goto error;
++	}
++	print_dbg("<< ingspi->buffer addr:%p >>\n", ingspi->buffer);
++#endif
++
++	ingspi->sg_tx = devm_kmalloc(dev, sizeof(struct scatterlist), GFP_KERNEL);
++	if (!ingspi->sg_tx) {
++		dev_err(dev, "Failed to alloc tx scatterlist\n");
++		goto error;
++	}
++
++	ingspi->sg_rx = devm_kmalloc(dev, sizeof(struct scatterlist), GFP_KERNEL);
++	if(!ingspi->sg_rx) {
++		dev_err(dev, "Failed to alloc rx scatterlist\n");
++		goto error;
++	}
++
++
++	dev_info(dev, "Using %s (tx) and %s (rx) for DMA transfers\n",
++			 dma_chan_name(ingspi->txchan),
++			 dma_chan_name(ingspi->rxchan));
++	return 0;
++error:
++	if (ingspi->rxchan)
++		dma_release_channel(ingspi->rxchan);
++	if (!IS_ERR(ingspi->txchan))
++		dma_release_channel(ingspi->txchan);
++	return err;
++}
++
++static bool ingenic_spi_can_dma(struct spi_master *master, struct spi_device *spi,
++			 struct spi_transfer *transfer)
++{
++	return true;
++}
++
++static int ingenic_spi_probe(struct platform_device *pdev)
++{
++	struct ingenic_spi *ingspi;
++	struct spi_master *master;
++	struct device_node *np = pdev->dev.of_node;
++	struct ingenic_spi_info *pdata = dev_get_platdata(&pdev->dev);
++	struct resource	*res;
++	int err = 0;
++
++	master = spi_alloc_master(&pdev->dev, sizeof(struct ingenic_spi));
++	if (!master) {
++		dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
++		return -ENOMEM;
++	}
++
++	/* the spi->mode bits understood by this drivers: */
++	master->mode_bits = MODEBITS;
++
++	ingspi = spi_master_get_devdata(master);
++	ingspi->g_ingenic_intr = devm_kzalloc(&pdev->dev,
++										  sizeof(struct ingenic_intr_cnt),GFP_KERNEL);
++	if(!ingspi->g_ingenic_intr) {
++		dev_err(&pdev->dev, "No memory for ingenic_intr_cnt\n");
++		return -ENOMEM;
++	}
++
++	ingspi->master = spi_master_get(master);
++	ingspi->dev = &pdev->dev;
++
++	if (!pdata && np) {
++		pdata = ingenic_spi_parse_dt(ingspi);
++		if (IS_ERR(pdata))
++			return PTR_ERR(pdata);
++	}
++
++	if (!pdata) {
++		dev_err(&pdev->dev, "platform_data missing!\n");
++		return -ENODEV;
++	}
++
++	ingspi->pdata = pdata;
++	ingspi->chnl= ingspi->pdata->chnl;
++	master->bus_num = (s16)ingspi->pdata->bus_num;
++	if(master->bus_num != 0 && master->bus_num != 1){
++		dev_err(&pdev->dev, "No this channel, bus_num= %d.\n", master->bus_num);
++		err = -ENOENT;
++		goto err_no_pdata;
++	}
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res) {
++		dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
++		return -ENXIO;
++	}
++	ingspi->phys = res->start;
++	ingspi->iomem = devm_ioremap_resource(&pdev->dev, res);
++	if (!ingspi->iomem) {
++		dev_err(&pdev->dev, "Cannot map IO\n");
++		err = -ENXIO;
++		goto err_no_iomap;
++	}
++
++	ingspi->irq = platform_get_irq(pdev, 0);
++	if (ingspi->irq <= 0) {
++		dev_err(&pdev->dev, "No IRQ specified\n");
++		err = -ENOENT;
++		goto err_no_irq;
++	}
++
++	ingenic_spi_clk_init(pdev, ingspi);
++
++	ingspi->spi_clk = ingspi->pdata->src_clk;
++	ingspi->max_clk = ingspi->pdata->max_clk;
++
++	platform_set_drvdata(pdev, ingspi);
++	init_completion(&ingspi->done);
++	init_completion(&ingspi->done_rx);
++	init_completion(&ingspi->done_tx_dma);
++	init_completion(&ingspi->done_rx_dma);
++	spin_lock_init(&ingspi->lock);
++	spin_lock_init(&ingspi->txrx_lock);
++
++	master->num_chipselect = ingspi->pdata->num_chipselect;
++	master->dev.of_node = pdev->dev.of_node;
++
++	/* setup the state for the bitbang driver */
++	ingspi->bitbang.master         = ingspi->master;
++	ingspi->bitbang.setup_transfer = ingenic_spi_setupxfer;
++	ingspi->bitbang.chipselect     = ingenic_spi_chipsel;
++	ingspi->bitbang.txrx_bufs      = ingenic_spi_txrx;
++	ingspi->bitbang.master->setup  = ingenic_spi_setup;
++	ingspi->fifodepth = INGENIC_SSI_MAX_FIFO_ENTRIES;
++	ingspi->set_cs = &ingenic_spi_cs;
++
++	ingenic_spi_init_setup(ingspi);
++
++	if (ingspi->use_dma) {
++		master->can_dma = ingenic_spi_can_dma;
++		ingenic_spi_configure_dma(ingspi);
++	}
++
++	/* request SSI irq */
++	err = devm_request_irq(&pdev->dev, ingspi->irq, ingenic_spi_irq, 0, pdev->name, ingspi);
++	if (err) {
++		dev_err(&pdev->dev, "Cannot claim IRQ\n");
++		goto err_register;
++	}
++
++	dev_dbg(ingspi->dev, "bitbang at %p\n", &ingspi->bitbang);
++	err = spi_bitbang_start(&ingspi->bitbang);
++	if (err) {
++		dev_err(&pdev->dev, "Failed to register SPI master ERR_NO:%d\n",err);
++		goto err_register;
++	}
++
++	printk(KERN_INFO "INGENIC SSI Controller for SPI channel %d driver register\n",ingspi->chnl);
++	return 0;
++
++err_register:
++	free_irq(ingspi->irq, ingspi);
++err_no_irq:
++	if(ingspi->clk_gate)
++		clk_put(ingspi->clk_gate);
++	if(ingspi->clk_cgu)
++		clk_put(ingspi->clk_cgu);
++	iounmap(ingspi->iomem);
++err_no_iomap:
++	release_resource(ingspi->ioarea);
++	kfree(ingspi->ioarea);
++err_no_pdata:
++	spi_master_put(ingspi->master);
++
++	return err;
++}
++
++static int ingenic_spi_remove(struct platform_device *dev)
++{
++	struct ingenic_spi *ingspi = platform_get_drvdata(dev);
++
++	spi_master_put(ingspi->master);
++	spi_bitbang_stop(&ingspi->bitbang);
++
++	platform_set_drvdata(dev, NULL);
++
++	free_irq(ingspi->irq, ingspi);
++	iounmap(ingspi->iomem);
++
++	ingenic_spi_clk_disable(ingspi);
++	clk_put(ingspi->clk_gate);
++	clk_put(ingspi->clk_cgu);
++
++	release_resource(ingspi->ioarea);
++	kfree(ingspi->ioarea);
++
++	/* release DMA channel */
++	if (ingspi->rxchan) {
++		dma_release_channel(ingspi->rxchan);
++	}
++	if (ingspi->txchan) {
++		dma_release_channel(ingspi->txchan);
++	}
++
++	/* release chipselect gpio */
++	{
++		int i;
++		for (i = 0; i < ingspi->pdata->num_chipselect; i++)
++			if(gpio_is_valid(ingspi->pdata->chipselects[i])) {
++				gpio_free(ingspi->pdata->chipselects[i]);
++			}
++	}
++
++	kfree(ingspi->g_ingenic_intr);
++	kfree(ingspi);
++	printk(KERN_INFO "INGENIC SSI Controller for SPI channel %d driver removed\n",ingspi->chnl);
++
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int ingenic_spi_suspend(struct platform_device *pdev, pm_message_t msg)
++{
++	struct ingenic_spi *ingspi = platform_get_drvdata(pdev);
++	unsigned long flags;
++
++	spin_lock_irqsave(&ingspi->lock, flags);
++	ingspi->state |= SUSPND;
++	spin_unlock_irqrestore(&ingspi->lock, flags);
++
++	while (ingspi->state & SPIBUSY)
++		printk("Now spi is busy, waitting!\n");
++
++	ingenic_spi_clk_disable(ingspi);
++
++	return 0;
++}
++
++static int ingenic_spi_resume(struct platform_device *pdev)
++{
++	struct ingenic_spi *ingspi = platform_get_drvdata(pdev);
++	unsigned long	flags;
++
++	ingenic_spi_clk_enable(ingspi);
++
++	spin_lock_irqsave(&ingspi->lock, flags);
++	ingspi->state &= ~SUSPND;
++	spin_unlock_irqrestore(&ingspi->lock, flags);
++
++	return 0;
++}
++
++#else
++#define ingenic_spi_suspend NULL
++#define ingenic_spi_resume  NULL
++#endif
++
++static struct platform_driver ingenic_spidrv = {
++	.probe	    = ingenic_spi_probe,
++	.remove		= ingenic_spi_remove,
++	.suspend	= ingenic_spi_suspend,
++	.resume		= ingenic_spi_resume,
++	.driver		= {
++		.name	= "ingenic-spi",
++		.of_match_table	= ingenic_spi_match,
++		.owner	= THIS_MODULE,
++	},
++};
++
++module_platform_driver(ingenic_spidrv);
++
++MODULE_ALIAS("ingenic_spi");
++MODULE_AUTHOR("Bo Liu <bo.liu@ingenic.com>");
++MODULE_DESCRIPTION("INGENIC SPI controller driver");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/spi/ingenic_spi.h b/module_drivers/drivers/spi/ingenic_spi.h
+new file mode 100755
+index 000000000..e0316ac9b
+--- /dev/null
++++ b/module_drivers/drivers/spi/ingenic_spi.h
+@@ -0,0 +1,1175 @@
++#ifndef __LINUX_SPI_JZ_H
++#define __LINUX_SPI_JZ_H
++
++#include <linux/interrupt.h>
++#include <linux/dmaengine.h>
++
++#define NR_DMA_CHANNELS	8
++
++#define CH_DSA	0x00
++#define CH_DTA	0x04
++#define CH_DTC	0x08
++#define CH_DRT	0x0C
++#define CH_DCS	0x10
++#define CH_DCM	0x14
++#define CH_DDA	0x18
++#define CH_DSD	0x1C
++
++#define TCSM	0x2000
++
++#define DMAC	0x1000
++#define DIRQP	0x1004
++#define DDR	0x1008
++#define DDRS	0x100C
++#define DMACP	0x101C
++#define DSIRQP	0x1020
++#define DSIRQM	0x1024
++#define DCIRQP	0x1028
++#define DCIRQM	0x102C
++
++/* MCU of PDMA */
++#define DMCS	0x1030
++#define DMNMB	0x1034
++#define DMSMB	0x1038
++#define DMINT	0x103C
++
++/* MCU of PDMA */
++#define DMINT_S_IP      BIT(17)
++#define DMINT_N_IP      BIT(16)
++
++#define DMAC_HLT	BIT(3)
++#define DMAC_AR		BIT(2)
++
++#define DCS_NDES	BIT(31)
++#define DCS_AR		BIT(4)
++#define DCS_TT		BIT(3)
++#define DCS_HLT		BIT(2)
++#define DCS_CTE		BIT(0)
++
++#define DCM_SAI		BIT(23)
++#define DCM_DAI		BIT(22)
++#define DCM_SP_MSK	(0x3 << 14)
++#define DCM_SP_32	DCM_SP_MSK
++#define DCM_SP_16	BIT(15)
++#define DCM_SP_8	BIT(14)
++#define DCM_DP_MSK	(0x3 << 12)
++#define DCM_DP_32	DCM_DP_MSK
++#define DCM_DP_16	BIT(13)
++#define DCM_DP_8	BIT(12)
++#define DCM_TSZ_MSK	(0x7 << 8)
++#define DCM_TSZ_SHF	8
++#define DCM_STDE	BIT(2)
++#define DCM_TIE		BIT(1)
++#define DCM_LINK	BIT(0)
++
++#define DCM_CH1_SRC_TCSM    (0x0 << 26)
++#define DCM_CH1_SRC_NEMC    (0x1 << 26)
++#define DCM_CH1_SRC_DDR     (0x2 << 26)
++
++#define DCM_CH1_DST_TCSM    (0x0 << 24)
++#define DCM_CH1_DST_NEMC    (0x1 << 24)
++#define DCM_CH1_DST_DDR     (0x2 << 24)
++
++#define DCM_CH1_DDR_TO_NAND  (DCM_CH1_SRC_DDR  | DCM_CH1_DST_NEMC)
++#define DCM_CH1_NAND_TO_DDR  (DCM_CH1_SRC_NEMC | DCM_CH1_DST_DDR)
++
++#define DCM_CH1_TCSM_TO_NAND (DCM_CH1_SRC_TCSM | DCM_CH1_DST_NEMC)
++#define DCM_CH1_NAND_TO_TCSM (DCM_CH1_SRC_NEMC | DCM_CH1_DST_TCSM)
++
++#define DCM_CH1_TCSM_TO_DDR  (DCM_CH1_SRC_TCSM | DCM_CH1_DST_DDR)
++#define DCM_CH1_DDR_TO_TCSM  (DCM_CH1_SRC_DDR  | DCM_CH1_DST_TCSM)
++
++#define MCU_MSG_TYPE_NORMAL	0x1
++#define MCU_MSG_TYPE_INTC	0x2
++#define MCU_MSG_TYPE_INTC_MASKA	0x3
++
++	enum jzdma_req_type {
++#define _RTP(NAME) JZDMA_REQ_##NAME##_TX,JZDMA_REQ_##NAME##_RX
++		JZDMA_REQ_RESERVED0 = 0x03,
++		_RTP(I2S1),
++		_RTP(I2S0),
++		JZDMA_REQ_AUTO_TXRX = 0x08,
++		JZDMA_REQ_SADC_RX,
++		JZDMA_REQ_RESERVED1 = 0x0b,
++		_RTP(UART4),
++		_RTP(UART3),
++		_RTP(UART2),
++		_RTP(UART1),
++		_RTP(UART0),
++		_RTP(SSI0),
++		_RTP(SSI1),
++		_RTP(MSC0),
++		_RTP(MSC1),
++		_RTP(MSC2),
++		_RTP(PCM0),
++		_RTP(PCM1),
++		_RTP(I2C0),
++		_RTP(I2C1),
++		_RTP(I2C2),
++		_RTP(I2C3),
++		_RTP(I2C4),
++		_RTP(DES),
++#undef _RTP
++	};
++
++enum jzdma_type {
++	JZDMA_REQ_INVAL = 0,
++#define _RTP(NAME) JZDMA_REQ_##NAME = JZDMA_REQ_##NAME##_TX
++	_RTP(I2S1),
++	_RTP(I2S0),
++	JZDMA_REQ_AUTO = JZDMA_REQ_AUTO_TXRX,
++	JZDMA_REQ_SADC = JZDMA_REQ_SADC_RX,
++	_RTP(UART4),
++	_RTP(UART3),
++	_RTP(UART2),
++	_RTP(UART1),
++	_RTP(UART0),
++	_RTP(SSI0),
++	_RTP(SSI1),
++	_RTP(MSC0),
++	_RTP(MSC1),
++	_RTP(MSC2),
++	_RTP(PCM0),
++	_RTP(PCM1),
++	_RTP(I2C0),
++	_RTP(I2C1),
++	_RTP(I2C2),
++	_RTP(I2C3),
++	_RTP(I2C4),
++	_RTP(DES),
++	JZDMA_REQ_NAND0 = JZDMA_REQ_AUTO_TXRX | (1 << 16),
++	JZDMA_REQ_NAND1 = JZDMA_REQ_AUTO_TXRX | (2 << 16),
++	JZDMA_REQ_NAND2 = JZDMA_REQ_AUTO_TXRX | (3 << 16),
++	JZDMA_REQ_NAND3 = JZDMA_REQ_AUTO_TXRX | (4 << 16),
++	JZDMA_REQ_NAND4 = JZDMA_REQ_AUTO_TXRX | (5 << 16),
++	TYPE_MASK = 0xffff,
++#undef _RTP
++};
++
++#define GET_MAP_TYPE(type) (type & (TYPE_MASK))
++
++struct jzdma_platform_data {
++	int irq_base;
++	int irq_end;
++	enum jzdma_type map[NR_DMA_CHANNELS];
++};
++
++
++struct jzdma_master;
++
++struct dma_desc {
++	unsigned long dcm;
++	dma_addr_t dsa;
++	dma_addr_t dta;
++	unsigned long dtc;
++	unsigned long sd;
++	unsigned long drt;
++	unsigned long reserved[2];
++};
++
++struct jzdma_channel {
++	int			id;
++	int			residue;
++	struct dma_chan		chan;
++	enum jzdma_type		type;
++	struct dma_async_tx_descriptor	tx_desc;
++	dma_cookie_t		last_completed;
++	dma_cookie_t		last_good;
++	struct tasklet_struct	tasklet;
++	spinlock_t		lock;
++#define CHFLG_SLAVE		BIT(0)
++	unsigned short		flags;
++	unsigned short		status;
++	unsigned long		dcs_saved;
++	struct dma_desc		*desc;
++	dma_addr_t		desc_phys;
++	unsigned short		desc_nr;
++	unsigned short		desc_max;
++	struct scatterlist	*sgl;
++	unsigned long		sg_len;
++	unsigned short		last_sg;
++#define FAKECYCLIC_ACTIVE (1 << 15)
++#define FAKECYCLIC_POSSIBLE (1 << 14)
++#define FAKECYCLIC_IDX 0x3fff
++	unsigned short fake_cyclic;
++	unsigned long		tx_dcm_def;
++	unsigned long		rx_dcm_def;
++	struct dma_slave_config	*config;
++	void __iomem		*iomem;
++	struct jzdma_master	*master;
++};
++
++enum channel_status {
++	STAT_STOPED,STAT_SUBED,STAT_PREPED,STAT_RUNNING,
++};
++
++enum ssi_clk_flag {
++	SFC_CLK, SSI_CLK,
++};
++
++struct jzdma_master {
++	struct device		*dev;
++	void __iomem		*iomem;
++	struct clk		*clk;
++	int			irq;
++	int                     irq_pdmam;   /* irq_pdmam for PDMAM irq */
++	struct dma_device	dma_device;
++	enum jzdma_type		*map;
++	struct irq_chip		irq_chip;
++	struct jzdma_channel	channel[NR_DMA_CHANNELS];
++};
++
++static inline struct device *chan2dev(struct dma_chan *chan)
++{
++	return &chan->dev->device;
++}
++
++static inline struct jzdma_channel *to_jzdma_chan(struct dma_chan *chan)
++{
++	return container_of(chan, struct jzdma_channel, chan);
++}
++
++void jzdma_dump(struct dma_chan *chan);
++
++/*SPI NOR FLASH Instructions*/
++#define CMD_WREN        0x06 /* Write Enable */
++#define CMD_WRDI        0x04 /* Write Disable */
++#define CMD_RDSR        0x05 /* Read Status Register */
++#define CMD_RDSR_1      0x35 /* Read Status1 Register */
++#define CMD_RDSR_2      0x15 /* Read Status2 Register */
++#define CMD_WRSR        0x01 /* Write Status Register */
++#define CMD_WRSR_1      0x31 /* Write Status1 Register */
++#define CMD_WRSR_2      0x11 /* Write Status2 Register */
++#define CMD_READ        0x03 /* Read Data */
++#define CMD_DUAL_READ   0x3b /* DUAL Read Data */
++#define CMD_QUAD_READ   0x6b /* QUAD Read Data */
++#define CMD_QUAD_IO_FAST_READ   0xeb /* QUAD FAST Read Data */
++#define CMD_QUAD_IO_WORD_FAST_READ   0xe7 /* QUAD IO WORD Read Data */
++#define CMD_FAST_READ   0x0B /* Read Data at high speed */
++#define CMD_PP          0x02 /* Page Program(write data) */
++#define CMD_QPP         0x32 /* QUAD Page Program(write data) */
++#define CMD_SE          0x20 /* Sector Erase */
++#define CMD_BE_32K      0x52 /* Block Erase */
++#define CMD_BE_64K		0XD8 /* Block Erase */
++#define CMD_CE          0xC7 /* Bulk or Chip Erase */
++#define CMD_DP          0xB9 /* Deep Power-Down */
++#define CMD_RES         0xAB /* Release from Power-Down and Read Electronic Signature */
++#define CMD_REMS        0x90 /* Read Manufacture ID/ Device ID */
++#define CMD_RDID        0x9F /* Read Identification */
++#define CMD_NON         0x00 /* Read Identification */
++#define CMD_EN4B		0xB7 /* Enter 4 bytes address mode */
++#define CMD_EX4B		0xE9 /* Exit 4 bytes address mode */
++
++/* SPI NAND Flash Instructions */
++//#define CMD_WREN    0x06    /* Write Enable */
++//#define CMD_WRDI    0x04    /* Write Disable */
++#define CMD_G_FEATURE   0x0F    /* Get Feature */
++#define CMD_S_FEATURE   0x1F    /* Set Feature */
++#define CMD_R_PAGE  0x13    /* Page Read (to cache) */
++#define CMD_R_CACHE 0x03    /* Read From Cache */
++#define CMD_P_LOAD  0x02    /* Program Load(write data to cache) */
++#define CMD_P_EXECUTE   0x10    /* Program Execute(write data) */
++#define CMD_E_BLOCK 0xD8    /* Block Erase */
++//#define CMD_RDID    0x9F    /* Read ID */
++#define CMD_RESET   0xFF    /* Reset */
++
++/*for sfc register config*/
++#define TRAN_SPI_QUAD   (0x5 )
++#define TRAN_SPI_IO_QUAD   (0x6 )
++
++
++#define SPIFLASH_PARAMER_OFFSET 0x3c00
++#define SPI_NORFLASH_PART_OFFSET 0x3c6c
++
++#define NORFLASH_PART_RW		0
++#define NORFLASH_PART_WO		1
++#define NORFLASH_PART_RO		2
++
++#define NOR_MAJOR_VERSION_NUMBER	1
++#define NOR_MINOR_VERSION_NUMBER	0
++#define NOR_REVERSION_NUMBER	0
++#define NOR_VERSION		(NOR_MAJOR_VERSION_NUMBER | (NOR_MINOR_VERSION_NUMBER << 8) | (NOR_REVERSION_NUMBER << 16))
++
++#define NOR_MAGIC	0x726f6e	//ascii "nor"
++
++struct sfc_nor_info {
++	u8 cmd;
++	u8 addr_len;
++	u8 daten;
++	u8 pollen;
++	u8 M7_0;// some cmd must be send the M7-0
++	u8 dummy_byte;
++	u8 dma_mode;
++};
++
++struct spi_nor_block_info {
++	u32 blocksize;
++	u8 cmd_blockerase;
++	/* MAX Busytime for block erase, unit: ms */
++	u32 be_maxbusy;
++};
++
++struct spi_quad_mode {
++	u8 dummy_byte;
++	u8 RDSR_CMD;
++	u8 WRSR_CMD;
++	unsigned int RDSR_DATE;//the data is write the spi status register for QE bit
++	unsigned int RD_DATE_SIZE;//the data is write the spi status register for QE bit
++	unsigned int WRSR_DATE;//this bit should be the flash QUAD mode enable
++	unsigned int WD_DATE_SIZE;//the data is write the spi status register for QE bit
++	u8 cmd_read;
++	u8 sfc_mode;
++};
++
++#define SIZEOF_NAME         32
++#define NOR_PART_NUM	10
++struct norflash_params {
++	char name[SIZEOF_NAME];
++	u32 pagesize;
++	u32 sectorsize;
++	u32 chipsize;
++	u32 erasesize;
++	int id;
++	/* Flash Address size, unit: Bytes */
++	int addrsize;
++
++	/* MAX Busytime for page program, unit: ms */
++	u32 pp_maxbusy;
++	/* MAX Busytime for sector erase, unit: ms */
++	u32 se_maxbusy;
++	/* MAX Busytime for chip erase, unit: ms */
++	u32 ce_maxbusy;
++
++	/* Flash status register num, Max support 3 register */
++	int st_regnum;
++	/* Some NOR flash has different blocksize and block erase command,
++	 *          * One command with One blocksize. */
++	struct spi_nor_block_info block_info;
++	struct spi_quad_mode quad_mode;
++};
++
++struct ingenic_priv {
++	uint32_t clk_flag;
++};
++
++struct nor_partition {
++	char name[SIZEOF_NAME];
++	uint32_t size;
++	uint32_t offset;
++	uint32_t mask_flags;//bit0-1 mask the partition RW mode, 0:RW  1:WO  2:RO
++	uint32_t manager_mode;
++};
++
++struct norflash_partitions {
++	struct nor_partition nor_partition[NOR_PART_NUM];
++	uint32_t num_partition_info;
++};
++
++struct nor_sharing_params {
++	uint32_t magic;
++	uint32_t version;
++	struct norflash_params norflash_params;
++	struct norflash_partitions norflash_partitions;
++};
++
++
++struct spi_nor_platform_data {
++	char *name;
++	u32 pagesize;
++	u32 sectorsize;
++	u32 chipsize;
++	u32 erasesize;
++	int id;
++	/* Some NOR flash has different blocksize and block erase command,
++	 *          * One command with One blocksize. */
++	struct spi_nor_block_info *block_info;
++	int num_block_info;
++
++	/* Flash Address size, unit: Bytes */
++	int addrsize;
++
++	/* MAX Busytime for page program, unit: ms */
++	u32 pp_maxbusy;
++	/* MAX Busytime for sector erase, unit: ms */
++	u32 se_maxbusy;
++	/* MAX Busytime for chip erase, unit: ms */
++	u32 ce_maxbusy;
++
++	/* Flash status register num, Max support 3 register */
++	int st_regnum;
++	struct mtd_partition *mtd_partition;
++	struct spi_quad_mode *quad_mode;
++	int num_partition_info;
++};
++
++struct ingenic_spi_info {
++	u8	chnl;				/* the chanel of SSI controller */
++	u16	bus_num;			/* spi_master.bus_num */
++	u8 src_clk;			/* source clock: 1---sfcclk;0---exclk */
++	unsigned long	max_clk;
++	unsigned long	board_size;		/* spi_master.num_chipselect */
++	struct spi_board_info	*board_info; 	/* link to spi devices info */
++	u32	 num_chipselect;
++	u32	 allow_cs_same;
++	unsigned int chipselects[2];
++
++	void (*set_cs)(struct ingenic_spi_info *spi, u8 cs,unsigned int pol); /* be defined by spi devices driver user */
++	void (*pins_config)(void);		/* configure spi function pins (CLK,DR,RT) by user if need. */
++};
++
++struct jz_sfc_info {
++	u8	chnl;				/* the chanel of SSI controller */
++	u16	bus_num;			/* spi_master.bus_num */
++	unsigned is_pllclk:1;			/* source clock: 1---pllclk;0---exclk */
++	unsigned long	board_size;		/* spi_master.num_chipselect */
++	u32	 num_chipselect;
++	u32	 allow_cs_same;
++	void  *board_info;
++	u32  board_info_size;
++};
++struct jz_sfc_nand_info{
++	u8      chnl;                           /* the chanel of SSI controller */
++	u16     bus_num;                        /* spi_master.bus_num */
++	unsigned is_pllclk:1;                   /* source clock: 1---pllclk;0---exclk */
++	unsigned long   board_size;             /* spi_master.num_chipselect */
++	u32      num_chipselect;
++	u32      allow_cs_same;
++	void  *board_info;
++	u32  board_info_size;
++};
++#define SPL_TYPE_FLAG_LEN 6
++struct jz_spi_support {
++	unsigned int id_manufactory;
++	unsigned char id_device;
++	char name[SIZEOF_NAME];
++	int page_size;
++	int oobsize;
++	int sector_size;
++	int block_size;
++	int size;
++	int page_num;
++
++	/* MAX Busytime for page read, unit: us */
++	u32 tRD_maxbusy;
++	/* MAX Busytime for Page Program, unit: us */
++	u32 tPROG_maxbusy;
++	/* MAX Busytime for block erase, unit: us */
++	u32 tBERS_maxbusy;
++
++	unsigned short column_cmdaddr_bits;/* read from cache ,the bits of cmd + addr */
++
++};
++
++struct jz_spi_support_from_burner {
++	unsigned int chip_id;
++	unsigned char id_device;
++	char name[32];
++	int page_size;
++	int oobsize;
++	int sector_size;
++	int block_size;
++	int size;
++	int page_num;
++	uint32_t tRD_maxbusy;
++	uint32_t tPROG_maxbusy;
++	uint32_t tBERS_maxbusy;
++	unsigned short column_cmdaddr_bits;
++
++};
++struct jz_spinand_partition {
++	char name[32];         /* identifier string */
++	uint32_t size;          /* partition size */
++	uint32_t offset;        /* offset within the master MTD space */
++	u_int32_t mask_flags;       /* master MTD flags to mask out for this partition */
++	u_int32_t manager_mode;         /* manager_mode mtd or ubi */
++};
++struct get_chip_param {
++	int version;
++	int flash_type;
++	int para_num;
++	struct jz_spi_support_from_burner *addr;
++	int partition_num;
++	struct jz_spinand_partition *partition;
++};
++struct jz_spi_nand_platform_data {
++	struct jz_spi_support *jz_spi_support;
++	int num_spi_flash;
++	struct mtd_partition *mtd_partition;
++	int num_partitions;
++};
++
++/*************************************************************************
++ * SSI (Synchronous Serial Interface)
++ *************************************************************************/
++/* n = 0, 1 (SSI0, SSI1) */
++#define	SSI_DR			0x000
++#define	SSI_CR0			0x004
++#define	SSI_CR1			0x008
++#define	SSI_SR			0x00C
++#define	SSI_ITR			0x010
++#define	SSI_ICR			0x014
++#define	SSI_GR			0x018
++#define	SSI_RCNT		0x01C
++
++/* SSI Data Register (SSI_DR) */
++#define	DR_GPC_BIT		0
++#define	DR_GPC_MASK		(0x1ff << SSI_DR_GPC_BIT)
++
++/* SSI Control Register 0 (SSI_CR0) */
++#define CR0_TENDIAN_BIT		18
++#define CR0_TENDIAN_MASK	(3 << CR0_TENDIAN_BIT)
++#define CR0_RENDIAN_BIT		16
++#define CR0_RENDIAN_MASK	(3 << CR0_RENDIAN_BIT)
++#define CR0_SSIE		(1 << 15)
++#define CR0_TIE			(1 << 14)
++#define CR0_RIE			(1 << 13)
++#define CR0_TEIE		(1 << 12)
++#define CR0_REIE		(1 << 11)
++#define CR0_LOOP		(1 << 10)
++#define CR0_RFINE		(1 << 9)
++#define CR0_RFINC		(1 << 8)
++#define CR0_EACLRUN		(1 << 7) /* hardware auto clear underrun when TxFifo no empty */
++#define CR0_FSEL		(1 << 6)
++#define CR0_VRCNT		(1 << 4)
++#define CR0_TFMODE		(1 << 3)
++#define CR0_TFLUSH		(1 << 2)
++#define CR0_RFLUSH		(1 << 1)
++#define CR0_DISREV		(1 << 0)
++
++/* SSI Control Register 1 (SSI_CR1) */
++#define CR1_FRMHL_BIT		30
++#define CR1_FRMHL_MASK		(0x3 << CR1_FRMHL_BIT)
++#define CR1_FRMHL_CELOW_CE2LOW	(0 << CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
++#define CR1_FRMHL_CEHIGH_CE2LOW	(1 << CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
++#define CR1_FRMHL_CELOW_CE2HIGH	(2 << CR1_FRMHL_BIT) /* SSI_CE_ is low valid  and SSI_CE2_ is high valid */
++#define CR1_FRMHL_CEHIGH_CE2HIGH	(3 << CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
++#define CR1_TFVCK_BIT		28
++#define CR1_TFVCK_MASK		(0x3 << CR1_TFVCK_BIT)
++  #define CR1_TFVCK_0		  (0 << CR1_TFVCK_BIT)
++  #define CR1_TFVCK_1		  (1 << CR1_TFVCK_BIT)
++  #define CR1_TFVCK_2		  (2 << CR1_TFVCK_BIT)
++  #define CR1_TFVCK_3		  (3 << CR1_TFVCK_BIT)
++#define CR1_TCKFI_BIT		26
++#define CR1_TCKFI_MASK		(0x3 << CR1_TCKFI_BIT)
++  #define CR1_TCKFI_0		  (0 << CR1_TCKFI_BIT)
++  #define CR1_TCKFI_1		  (1 << CR1_TCKFI_BIT)
++  #define CR1_TCKFI_2		  (2 << CR1_TCKFI_BIT)
++  #define CR1_TCKFI_3		  (3 << CR1_TCKFI_BIT)
++#define CR1_ITFRM		(1 << 24)
++#define CR1_UNFIN		(1 << 23)
++#define CR1_FMAT_BIT		20
++#define CR1_FMAT_MASK		(0x3 << CR1_FMAT_BIT)
++  #define CR1_FMAT_SPI		  (0 << CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
++  #define CR1_FMAT_SSP		  (1 << CR1_FMAT_BIT) /* TI's SSP format */
++  #define CR1_FMAT_MW1		  (2 << CR1_FMAT_BIT) /* National Microwire 1 format */
++  #define CR1_FMAT_MW2		  (3 << CR1_FMAT_BIT) /* National Microwire 2 format */
++#define CR1_TTRG_BIT		16 /* SSI1 TX trigger */
++#define CR1_TTRG_MASK		(0xf << CR1_TTRG_BIT)
++#define CR1_MCOM_BIT		12
++#define CR1_MCOM_MASK		(0xf << CR1_MCOM_BIT)
++//  #define CR1_MCOM_BIT(NO)	  (##NO## << CR1_MCOM_BIT) /* N-bit command selected */
++#define CR1_RTRG_BIT		8 /* SSI RX trigger */
++#define CR1_RTRG_MASK		(0xf << CR1_RTRG_BIT)
++#define CR1_FLEN_BIT		3
++#define CR1_FLEN_MASK		(0x1f << CR1_FLEN_BIT)
++  #define CR1_FLEN_2BIT		  (0x0 << CR1_FLEN_BIT)
++#define CR1_PHA			(1 << 1)
++#define CR1_POL			(1 << 0)
++
++/* SSI Status Register (SSI_SR) */
++#define SR_TFIFONUM_BIT		16
++#define SR_TFIFONUM_MASK	(0xff << SR_TFIFONUM_BIT)
++#define SR_RFIFONUM_BIT		8
++#define SR_RFIFONUM_MASK	(0xff << SR_RFIFONUM_BIT)
++#define SR_END			(1 << 7)
++#define SR_BUSY			(1 << 6)
++#define SR_TFF			(1 << 5)
++#define SR_RFE			(1 << 4)
++#define SR_TFHE			(1 << 3)
++#define SR_RFHF			(1 << 2)
++#define SR_UNDR			(1 << 1)
++#define SR_OVER			(1 << 0)
++
++/* SSI Interval Time Control Register (SSI_ITR) */
++#define	ITR_CNTCLK		(1 << 15)
++#define ITR_IVLTM_BIT		0
++#define ITR_IVLTM_MASK		(0x7fff << ITR_IVLTM_BIT)
++
++
++
++#define R_MODE			0x1
++#define W_MODE			0x2
++#define RW_MODE			(R_MODE | W_MODE)
++
++#define R_DMA			0x4
++#define W_DMA			0x8
++#define RW_DMA			(R_DMA |W_DMA)
++
++#define SPI_DMA_ACK		0x1
++
++#define SPI_DMA_ERROR  		-3
++#define SPI_CPU_ERROR		-4
++
++#define SPI_COMPLETE		5
++
++#define INGENIC_SSI_MAX_FIFO_ENTRIES 	128
++#define INGENIC_SSI_DMA_BURST_LENGTH 	16
++
++#define FIFO_W8			8
++#define FIFO_W16		16
++#define FIFO_W32		32
++
++#define SPI_BITS_8		8
++#define SPI_BITS_16		16
++#define SPI_BITS_32		32
++
++#define SPI_8BITS		1
++#define SPI_16BITS		2
++#define SPI_32BITS		4
++
++
++/* tx rx threshold from 0x0 to 0xF */
++#define SSI_FULL_THRESHOLD		0xF
++#define SSI_TX_FIFO_THRESHOLD		0x1
++#define SSI_RX_FIFO_THRESHOLD		(SSI_FULL_THRESHOLD - SSI_TX_FIFO_THRESHOLD)
++#define SSI_SAFE_THRESHOLD		0x1
++
++#define CPU_ONCE_BLOCK_ENTRIES 		((SSI_FULL_THRESHOLD-SSI_TX_FIFO_THRESHOLD)*8)
++
++#define MAX_SSI_INTR		10000
++
++#define MAX_SSICDR			63
++#define MAX_CGV				255
++
++#define SSI_DMA_FASTNESS_CHNL 	 0   // SSI controller [n] FASTNESS when probe();
++
++#define JZ_NEW_CODE_TYPE
++
++#define BUFFER_SIZE	PAGE_SIZE
++
++#define CONFIG_DMA_ENGINE 1
++
++#define SUSPND    (1<<0)
++#define SPIBUSY   (1<<1)
++#define RXBUSY    (1<<2)
++#define TXBUSY    (1<<3)
++
++struct ingenic_spi {
++	/* bitbang has to be first */
++	struct spi_bitbang	bitbang;
++	struct clk		*clk_gate;
++	struct clk		*clk_cgu;
++	struct clk		*clk_parent;
++	unsigned int		clk_flag;
++	unsigned int		set_clk_flag;
++	struct completion	done;
++	struct completion	done_rx;
++	struct completion	done_tx_dma;
++	struct completion	done_rx_dma;
++
++	spinlock_t		lock;
++	spinlock_t		txrx_lock;
++
++	unsigned int		state;
++
++	u8			chnl;
++	u8			rw_mode;
++	u8			spi_mode;
++	u8			use_dma;
++	u8			last_transfer;
++
++	u8			bits_per_word;		/*8 or 16 (or 32)*/
++	u8			transfer_unit_size;	/* 1 or 2 (or 4) */
++	u8			tx_trigger;		/* 0-128 */
++	u8			rx_trigger;		/* 0-128 */
++	u8			dma_tx_unit;		/* 1 or 2 or 4 or 16 or 32*/
++	u8			dma_rx_unit;		/* 1 or 2 or 4 or 16 or 32*/
++	u8			txfifo_width;
++	u8			rxfifo_width;
++	u32			fifodepth;
++	u32			t_count;
++	u32			r_count;
++
++	/* data buffers */
++	const u8		*tx;
++	u8			*rx;
++
++	/* temp buffers */
++	void			*buffer;
++	dma_addr_t		buffer_dma;
++
++	void __iomem		*iomem;
++	unsigned long		phys;
++	int			 irq;
++	u32			 len;
++	u32			 rlen;	  /* receive len */
++	u32			 count;   /* sent count */
++	enum jzdma_type     	 dma_type;
++	u32			 dma_flag;
++
++	void			(*set_cs)(struct ingenic_spi_info *spi, u8 cs, unsigned int pol);
++
++	/* functions to deal with different size buffers */
++	u32 (*get_rx) (struct ingenic_spi *);
++	u32 (*get_tx) (struct ingenic_spi *);
++	int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
++	irqreturn_t (*irq_callback)(struct ingenic_spi *);
++
++#ifdef CONFIG_DMA_ENGINE
++	struct dma_chan 	*txchan;
++	struct dma_chan 	*rxchan;
++	struct scatterlist  	*sg_rx;	/* I/O scatter list */
++	struct scatterlist  	*sg_tx;	/* I/O scatter list */
++#endif
++
++	unsigned long max_clk;
++	unsigned long spi_clk;
++
++	struct ingenic_intr_cnt *g_ingenic_intr;
++
++	struct resource		*ioarea;
++	struct spi_master	*master;
++	struct device		*dev;
++	struct ingenic_spi_info *pdata;
++	struct ingenic_priv     *priv;
++//	struct spi_board_info *pdata;
++};
++
++
++struct ingenic_intr_cnt{
++	int dma_tx_cnt;
++	int dma_rx_cnt;
++	int ssi_intr_cnt;
++	int max_ssi_intr;
++	int ssi_txi;
++	int ssi_rxi;
++	int ssi_eti;
++	int ssi_eri;
++	int ssi_rlen;
++	int dma_tx_err;
++	int dma_tx_end;
++	int dma_rx_err;
++	int dma_rx_end;
++};
++/* the max number of spi devices */
++#define MAX_SPI_DEVICES				10
++#define MAX_SPI_HOST				2
++
++#define INGENIC_SPI_ID_INVALID(ssi_id) ( ((ssi_id) < 0) || ((ssi_id) > (MAX_SPI_HOST - 1)) )
++
++#define MAX_SPI_CHIPSELECT_NUM 		MAX_GPIO_NUM
++
++
++static inline void spi_writel(struct ingenic_spi *spi, unsigned short offset, u32 value)
++{
++	writel(value, spi->iomem + offset);
++}
++
++static inline u32 spi_readl(struct ingenic_spi *spi,
++				      unsigned short offset)
++{
++	return readl(spi->iomem + offset);
++}
++
++static inline void set_frmhl(struct ingenic_spi *spi, unsigned int frmhl)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR1);
++	tmp = (tmp & ~CR1_FRMHL_MASK) | frmhl;
++	spi_writel(spi, SSI_CR1, tmp);
++}
++
++static inline void set_spi_clock_phase(struct ingenic_spi *spi, unsigned int cpha)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR1);
++	tmp = (tmp & ~CR1_PHA) | (cpha ? CR1_PHA : 0);
++	spi_writel(spi, SSI_CR1, tmp);
++}
++
++static inline void set_spi_clock_polarity(struct ingenic_spi *spi,
++					  unsigned int cpol)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR1);
++	tmp = (tmp & ~CR1_POL) | (cpol ? CR1_POL : 0);
++	spi_writel(spi, SSI_CR1, tmp);
++}
++
++static inline void set_tx_msb(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp &= ~CR0_TENDIAN_MASK;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void set_tx_lsb(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp |= (tmp & ~CR0_TENDIAN_MASK) | (0x3 << CR0_TENDIAN_BIT);
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void set_rx_msb(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp &= ~CR0_RENDIAN_MASK;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void set_rx_lsb(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp |= (tmp & ~CR0_RENDIAN_MASK) | (0x3 << CR0_RENDIAN_BIT);
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void enable_loopback(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp |= CR0_LOOP;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void disable_loopback(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp &= ~CR0_LOOP;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void transmit_data(struct ingenic_spi *spi, u32 value)
++{
++	spi_writel(spi, SSI_DR, value);
++}
++
++static inline void set_frame_length(struct ingenic_spi *spi, u32 len)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR1);
++	tmp = (tmp & ~CR1_FLEN_MASK) | (((len) - 2) << CR1_FLEN_BIT);
++	spi_writel(spi, SSI_CR1, tmp);
++}
++
++static inline void set_tx_trigger(struct ingenic_spi *spi, u32 val)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR1);
++	tmp = (tmp & ~CR1_TTRG_MASK) | ((val)/8) << CR1_TTRG_BIT;
++	spi_writel(spi, SSI_CR1, tmp);
++}
++
++static inline void set_rx_trigger(struct ingenic_spi *spi, u32 val)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR1);
++	tmp = (tmp & ~CR1_RTRG_MASK) | ((val)/8) << CR1_RTRG_BIT;
++	spi_writel(spi, SSI_CR1, tmp);
++}
++
++static inline void enable_txfifo_half_empty_intr(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp |= CR0_TIE;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void disable_txfifo_half_empty_intr(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp &= ~CR0_TIE;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void enable_rxfifo_half_full_intr(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp |= CR0_RIE;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void disable_rxfifo_half_full_intr(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp &= ~CR0_RIE;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void enable_tx_intr(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp |= CR0_TIE | CR0_TEIE;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void disable_tx_intr(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp &= ~(CR0_TIE | CR0_TEIE);
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void enable_rx_intr(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp |= CR0_RIE | CR0_REIE;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void disable_rx_intr(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp &= ~(CR0_RIE | CR0_REIE);
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void enable_tx_error_intr(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp |= CR0_TEIE;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void disable_tx_error_intr(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp &= ~CR0_TEIE;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void enable_rx_error_intr(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp |= CR0_REIE;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void disable_rx_error_intr(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp &= ~CR0_REIE;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void underrun_auto_clear(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp |= CR0_EACLRUN;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void clear_errors(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_SR);
++	tmp &= ~(SR_UNDR | SR_OVER);
++	spi_writel(spi, SSI_SR, tmp);
++}
++
++static inline void set_spi_format(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR1);
++	tmp &= ~CR1_FMAT_MASK;
++	tmp |= CR1_FMAT_SPI;
++	tmp &= ~(CR1_TFVCK_MASK | CR1_TCKFI_MASK);
++	tmp |= (CR1_TFVCK_0 | CR1_TCKFI_0);
++//	tmp |= (CR1_TFVCK_1 | CR1_TCKFI_1);
++//	tmp |= (CR1_TFVCK_2 | CR1_TCKFI_2);
++//	tmp |= (CR1_TFVCK_3 | CR1_TCKFI_3);
++	spi_writel(spi, SSI_CR1, tmp);
++}
++
++static inline void enable_receive(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp &= ~CR0_DISREV;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void disable_receive(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp |= CR0_DISREV;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void flush_fifo(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp |= CR0_TFLUSH | CR0_RFLUSH;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void disable_receive_continue(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp &= ~(CR0_RFINE | CR0_RFINC);
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void finish_transmit(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR1);
++	tmp &= ~CR1_UNFIN;
++	spi_writel(spi, SSI_CR1, tmp);
++}
++
++static inline void start_transmit(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR1);
++	tmp |= CR1_UNFIN;
++	spi_writel(spi, SSI_CR1, tmp);
++}
++
++static inline int rxfifo_empty(struct ingenic_spi *spi)
++{
++	return spi_readl(spi, SSI_SR) & SR_RFE;
++}
++
++static inline int ssi_busy(struct ingenic_spi *spi)
++{
++	return spi_readl(spi, SSI_SR) & SR_BUSY;
++}
++
++static inline void ssi_disable(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp &= ~CR0_SSIE;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void ssi_enable(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp |= CR0_SSIE;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline u32 get_rxfifo_count(struct ingenic_spi *spi)
++{
++	return (spi_readl(spi, SSI_SR) & SR_RFIFONUM_MASK) >> SR_RFIFONUM_BIT;
++}
++
++static inline u32 transfer_busy(struct ingenic_spi *spi)
++{
++	return spi_readl(spi, SSI_SR) & SR_BUSY;
++}
++
++static inline void flush_txfifo(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp |= CR0_TFLUSH;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void flush_rxfifo(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp |= CR0_RFLUSH;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline int ssi_underrun(struct ingenic_spi *spi)
++{
++	return spi_readl(spi, SSI_SR) & SR_UNDR;
++}
++
++static inline int ssi_overrun(struct ingenic_spi *spi)
++{
++	return spi_readl(spi, SSI_SR) & SR_OVER;
++}
++
++static inline int ssi_transfer_end(struct ingenic_spi *spi)
++{
++	return spi_readl(spi, SSI_SR) & SR_END;
++}
++
++static inline int tx_error_intr(struct ingenic_spi *spi)
++{
++	return spi_readl(spi, SSI_CR0) & CR0_TEIE;
++}
++
++static inline int rx_error_intr(struct ingenic_spi *spi)
++{
++	return spi_readl(spi, SSI_CR0) & CR0_REIE;
++}
++
++static inline int rxfifo_half_full(struct ingenic_spi *spi)
++{
++	return spi_readl(spi, SSI_SR) & SR_RFHF;
++}
++
++static inline int txfifo_half_empty(struct ingenic_spi *spi)
++{
++	return spi_readl(spi, SSI_SR) & SR_TFHE;
++}
++
++static inline int txfifo_half_empty_intr(struct ingenic_spi *spi)
++{
++	return spi_readl(spi, SSI_CR0) & CR0_TIE;
++}
++
++static inline int rxfifo_half_full_intr(struct ingenic_spi *spi)
++{
++	return spi_readl(spi, SSI_CR0) & CR0_RIE;
++}
++
++static inline void select_ce(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp &= ~CR0_FSEL;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void select_ce2(struct ingenic_spi *spi)
++{
++	u32 tmp;
++	tmp = spi_readl(spi, SSI_CR0);
++	tmp |= CR0_FSEL;
++	spi_writel(spi, SSI_CR0, tmp);
++}
++
++static inline void dump_spi_reg(struct ingenic_spi *spi)
++{
++//	printk("SSI_DR	:%08x\n", spi_readl(spi, SSI_DR	));
++	printk("SSI_CR0	:%08x\n", spi_readl(spi, SSI_CR0 ));
++	printk("SSI_CR1	:%08x\n", spi_readl(spi, SSI_CR1 ));
++	printk("SSI_SR	:%08x\n", spi_readl(spi, SSI_SR	));
++	printk("SSI_ITR	:%08x\n", spi_readl(spi, SSI_ITR ));
++	printk("SSI_ICR	:%08x\n", spi_readl(spi, SSI_ICR ));
++	printk("SSI_GR	:%08x\n", spi_readl(spi, SSI_GR	));
++	printk("SSI_RCNT:%08x\n", spi_readl(spi, SSI_RCNT));
++}
++
++#endif /* __LINUX_SPI_JZ_H */
+diff --git a/module_drivers/drivers/tty/Makefile b/module_drivers/drivers/tty/Makefile
+new file mode 100644
+index 000000000..dd3b9b662
+--- /dev/null
++++ b/module_drivers/drivers/tty/Makefile
+@@ -0,0 +1 @@
++obj-y += serial/
+diff --git a/module_drivers/drivers/tty/serial/Kconfig b/module_drivers/drivers/tty/serial/Kconfig
+new file mode 100644
+index 000000000..79cd473a8
+--- /dev/null
++++ b/module_drivers/drivers/tty/serial/Kconfig
+@@ -0,0 +1,41 @@
++config SERIAL_INGENIC_UART
++        tristate "ingenic serial port support"
++        select SERIAL_CORE
++        help
++          If you have a machine based on a xbrust mips soc you can
++          enable its onboard serial port by enabling this option.
++
++config SERIAL_INGENIC_CONSOLE
++        bool "Console on ingenic soc and compatible serial port"
++        depends on SERIAL_INGENIC_UART=y
++        select SERIAL_CORE_CONSOLE
++        help
++          If you say Y here, it will be possible to use a serial port as the
++          system console (the system console is the device which receives all
++          kernel messages and warnings and which allows logins in single user
++          mode). This could be useful if some terminal or printer is connected
++          to that serial port.
++
++          Even if you say Y here, the currently visible virtual console
++          (/dev/tty0) will still be used as the system console by default, but
++          you can alter that using a kernel command line option such as
++          "console=ttyS1". (Try "man bootparam" or see the documentation of
++          your boot loader (grub or lilo or loadlin) about how to pass options
++          to the kernel at boot time.)
++
++          If you don't have a VGA card installed and you say Y here, the
++          kernel will automatically use the first serial line, /dev/ttyS0, as
++          system console.
++
++          If unsure, say N.
++
++config SERIAL_INGENIC_LARGE_BAUDRATE
++        bool "ingenic baudrate add support greater than 1M"
++        depends on SERIAL_INGENIC_UART=y
++        default y
++
++config SERIAL_INGENIC_MAGIC_SYSRQ
++        bool "ingenic uart enable Magic SysRq key"
++        depends on MAGIC_SYSRQ=y && SERIAL_INGENIC_UART=y
++        default n
++
+diff --git a/module_drivers/drivers/tty/serial/Makefile b/module_drivers/drivers/tty/serial/Makefile
+new file mode 100644
+index 000000000..5610f781c
+--- /dev/null
++++ b/module_drivers/drivers/tty/serial/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_SERIAL_INGENIC_UART) += ingenic_uart.o
+diff --git a/module_drivers/drivers/tty/serial/ingenic_uart.c b/module_drivers/drivers/tty/serial/ingenic_uart.c
+new file mode 100644
+index 000000000..5f3761d1e
+--- /dev/null
++++ b/module_drivers/drivers/tty/serial/ingenic_uart.c
+@@ -0,0 +1,1219 @@
++/*
++ *  Based on drivers/serial/8250.c by Russell King.
++ *
++ *  Author:	Nicolas Pitre
++ *  Created:	Feb 20, 2003
++ *  Copyright:	(C) 2003 Monta Vista Software, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * Note 1: This driver is made separate from the already too overloaded
++ * 8250.c because it needs some kirks of its own and that'll make it
++ * easier to add DMA support.
++ *
++ * Note 2: I'm too sick of device allocation policies for serial ports.
++ * If someone else wants to request an "official" allocation of major/minor
++ * for this driver please be my guest.  And don't forget that new hardware
++ * to come from Intel might have more than 3 or 4 of those UARTs.  Let's
++ * hope for a better port registration and dynamic device allocation scheme
++ * with the serial core maintainer satisfaction to appear soon.
++ */
++
++
++#if defined(CONFIG_SERIAL_INGENIC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
++#define SUPPORT_SYSRQ
++#endif
++#include <linux/module.h>
++#include <linux/ioport.h>
++#include <linux/init.h>
++#include <linux/console.h>
++#include <linux/sysrq.h>
++#include <linux/serial_core.h>
++#include <linux/circ_buf.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/bsearch.h>
++#include <linux/platform_device.h>
++#include <linux/tty.h>
++#include <linux/tty_flip.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/debugfs.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_gpio.h>
++
++#include "ingenic_uart.h"
++
++#define PORT_NR 10
++#define DMA_BUFFER 1024
++#define COUNT_DMA_BUFFER 2048
++static unsigned short quot1[3] = {0}; /* quot[0]:baud_div, quot[1]:umr, quot[2]:uacr */
++struct uart_ingenic_port {
++	struct uart_port        port;
++	unsigned char           ier;
++	unsigned char           lcr;
++	unsigned char           mcr;/* just store bit status of MDCE and FCM in UART_MCR */
++	unsigned char           old_mcr; /* store the old value of UART_MCR */
++	unsigned int            lsr_break_flag;
++	struct clk		*clk;
++	char			name[16];
++
++#ifdef CONFIG_DEBUG_FS
++	struct dentry	*debugfs;
++#endif
++};
++static inline void check_modem_status(struct uart_ingenic_port *up);
++static unsigned short *serial47xx_get_divisor(struct uart_port *port, unsigned int baud);
++static inline void serial_dl_write(struct uart_port *up, int value);
++
++static struct baudtoregs_t
++{
++	unsigned int baud;
++	unsigned short div;
++	unsigned int umr:5;
++	unsigned int uacr:12;
++} baudtoregs[] = {
++	/*
++	  The data is generated by a python,
++	  the script is tools/tty/get_divisor.py
++	 */
++ #if (CONFIG_EXTAL_CLOCK == 24)
++	{50,0x7530,0x10,0x0},
++	{75,0x4e20,0x10,0x0},
++	{110,0x3521,0x10,0x0},
++	{134,0x2b9d,0x10,0x0},
++	{150,0x2710,0x10,0x0},
++	{200,0x1d4c,0x10,0x0},
++	{300,0x1388,0x10,0x0},
++	{600,0x9c4,0x10,0x0},
++	{1200,0x4e2,0x10,0x0},
++	{1800,0x340,0x10,0x0},
++	{2400,0x271,0x10,0x0},
++	{4800,0x138,0x10,0x0},
++	{9600,0x9c,0x10,0x0},
++	{19200,0x4e,0x10,0x0},
++	{38400,0x27,0x10,0x0},
++	{57600,0x1a,0x10,0x0},
++	{115200,0xd,0x10,0x0},
++	{230400,0x6,0x11,0x252},
++	{460800,0x3,0x11,0x252},
++	{500000,0x3,0x10,0x0},
++	{576000,0x3,0xd,0xfef},
++	{921600,0x2,0xd,0x0},
++	{1000000,0x2,0xc,0x0},
++	{1152000,0x1,0x14,0xefb},
++	{1500000,0x1,0x10,0x0},
++	{2000000,0x1,0xc,0x0},
++	{2500000,0x1,0x9,0x6b5},
++	{3000000,0x1,0x8,0x0},
++	{3500000,0x1,0x6,0xbf7},
++	{4000000,0x1,0x6,0x0},
++#elif (CONFIG_EXTAL_CLOCK == 26)
++	{50,0x7ef4,0x10,0x0},
++	{75,0x546b,0x10,0x0},
++	{110,0x398f,0x10,0x0},
++	{134,0x2f40,0x10,0x0},
++	{150,0x2a36,0x10,0x0},
++	{200,0x1fbd,0x10,0x0},
++	{300,0x151b,0x10,0x0},
++	{600,0xa8e,0x10,0x0},
++	{1200,0x547,0x10,0x0},
++	{1800,0x385,0x10,0x0},
++	{2400,0x2a4,0x10,0x0},
++	{4800,0x152,0x10,0x0},
++	{9600,0xa9,0x10,0x0},
++	{19200,0x54,0x10,0x2},
++	{38400,0x2a,0x10,0x2},
++	{57600,0x1c,0x10,0x2},
++	{115200,0xe,0x10,0x2},
++	{230400,0x7,0x10,0x2},
++	{460800,0x4,0xe,0x2},
++	{500000,0x3,0x11,0x550},
++	{576000,0x3,0xf,0x2},
++	{921600,0x2,0xe,0x2},
++	{1000000,0x2,0xd,0x0},
++	{1152000,0x2,0xb,0x248},
++	{1500000,0x1,0x11,0x550},
++	{2000000,0x1,0xd,0x0},
++	{2500000,0x1,0xa,0x2a0},
++	{3000000,0x1,0x8,0x700},
++	{3500000,0x1,0x7,0x2a0},
++	{4000000,0x1,0x6,0x7c0},
++#elif (CONFIG_EXTAL_CLOCK == 48)
++	{50,0xea60,0x10,0x0},
++	{75,0x9c40,0x10,0x0},
++	{110,0x6a42,0x10,0x0},
++	{134,0x573a,0x10,0x0},
++	{150,0x4e20,0x10,0x0},
++	{200,0x3a98,0x10,0x0},
++	{300,0x2710,0x10,0x0},
++	{600,0x1388,0x10,0x0},
++	{1200,0x9c4,0x10,0x0},
++	{1800,0x67f,0x10,0x0},
++	{2400,0x4e2,0x10,0x0},
++	{4800,0x271,0x10,0x0},
++	{9600,0x138,0x10,0x0},
++	{19200,0x9c,0x10,0x0},
++	{38400,0x4e,0x10,0x0},
++	{57600,0x34,0x10,0x0},
++	{115200,0x1a,0x10,0x0},
++	{230400,0xd,0x10,0x0},
++	{460800,0x6,0x11,0x550},
++	{500000,0x6,0x10,0x0},
++	{576000,0x5,0x10,0x700},
++	{921600,0x3,0x11,0x550},
++	{1000000,0x3,0x10,0x0},
++	{1152000,0x3,0xd,0x0},
++	{1500000,0x2,0x10,0x0},
++	{2000000,0x2,0xc,0x0},
++	{2500000,0x1,0x13,0x84},
++	{3000000,0x1,0x10,0x0},
++	{3500000,0x1,0xd,0x600},
++	{4000000,0x1,0xc,0x0},
++#endif
++};
++
++/*
++*Function:read register
++*Parameter:struct uart_ingenic_port *up, int offset
++*Return:unsigned int:Register address
++*/
++static inline unsigned int serial_in(struct uart_ingenic_port *up, int offset)
++{
++	offset <<= 2;
++	return readl(up->port.membase + offset);
++}
++
++/*
++*Function:write register
++*Parameter:struct uart_ingenic_port *up, int offset,int value:write value
++*Return:void
++*/
++static inline void serial_out(struct uart_ingenic_port *up, int offset, int value)
++{
++	offset <<= 2;
++	writel(value, up->port.membase + offset);
++}
++
++/*
++*Function: Enable Modem status interrupt
++*Parameter:struct uart_ingenic_port
++*Return:void
++*/
++static void serial_ingenic_enable_ms(struct uart_port *port)
++{
++	struct uart_ingenic_port *up = (struct uart_ingenic_port *)port;
++
++	up->ier |= UART_IER_MSI;// Enable Modem status interrupt
++	serial_out(up, UART_IER, up->ier);
++}
++
++/*
++*Function:stop transmitting
++*Parameter:struct uart_ingenic_port
++*Return:void
++*/
++static void serial_ingenic_stop_tx(struct uart_port *port)
++{
++	struct uart_ingenic_port *up = (struct uart_ingenic_port *)port;
++
++	if (up->ier & UART_IER_THRI) {
++		up->ier &= ~UART_IER_THRI;// Disable the transmit data request interrupt
++		serial_out(up, UART_IER, up->ier);
++	}
++}
++
++/*
++*Function:stop receiving
++*Parameter:struct uart_ingenic_port *up
++*Return:void
++*/
++static void serial_ingenic_stop_rx(struct uart_port *port)
++{
++	struct uart_ingenic_port *up = (struct uart_ingenic_port *)port;
++
++	up->ier &= ~UART_IER_RLSI;
++	up->port.read_status_mask &= ~UART_LSR_DR;
++	serial_out(up, UART_IER, up->ier);
++}
++
++/*
++*Function:receive char
++*Parameter:unsigned long data,unsigned int status
++*Return:void
++*/
++static inline void receive_chars(unsigned long data)
++{
++	struct uart_ingenic_port *up = (struct uart_ingenic_port *)data;
++	struct tty_struct *tty = up->port.state->port.tty;
++	unsigned int ch, flag;
++	int max_count = 256;
++	unsigned int status= serial_in(up, UART_LSR);
++	while ((status & UART_LSR_DR) && (max_count-- > 0))
++		//ready to receive data and max_count>0
++	{
++		ch = serial_in(up, UART_RX);//read RX_Register
++		flag = TTY_NORMAL;// TTY_NORMAL=0
++		up->port.icount.rx++;
++
++#ifdef CONFIG_SERIAL_INGENIC_MAGIC_SYSRQ
++		/* Test SYSRQ */
++		if((status == 0xe1) && ch == 0x00) {
++			if (uart_handle_break(&up->port))
++				goto ignore_char;
++		}
++#endif
++		/*  Break interrupt error | prrity error | Frame error | overun error */
++		if (unlikely(status & (UART_LSR_BI | UART_LSR_PE |
++						UART_LSR_FE | UART_LSR_OE))) {
++			if (status & UART_LSR_BI) {
++				status &= ~(UART_LSR_FE | UART_LSR_PE);
++				up->port.icount.brk++;
++				/*
++				 * We do the SysRQ and SAK checking
++				 * here because otherwise the break
++				 * may get masked by ignore_status_mask
++				 * or read_status_mask.
++				 */
++				if (uart_handle_break(&up->port))
++					goto ignore_char;
++			} else if (status & UART_LSR_PE)
++				up->port.icount.parity++;
++			else if (status & UART_LSR_FE)
++				up->port.icount.frame++;
++			if (status & UART_LSR_OE)
++				up->port.icount.overrun++;
++			/*
++			 * Mask off conditions which should be ignored.
++			 */
++			status &= up->port.read_status_mask;
++
++#ifdef CONFIG_SERIAL_INGENIC_CONSOLE
++			if (up->port.line == up->port.cons->index) {
++				/* Recover the break flag from console xmit */
++				status |= up->lsr_break_flag;
++				up->lsr_break_flag = 0;
++			}
++#endif
++#ifdef CONFIG_SERIAL_INGENIC_MAGIC_SYSRQ
++			if (status == 0xe1) {
++				printk("handling break ....!\n");
++#else
++				if (status & UART_LSR_BI) {
++#endif
++				flag = TTY_BREAK;
++			} else if (status & UART_LSR_PE)
++				flag = TTY_PARITY;
++			else if (status & UART_LSR_FE)
++				flag = TTY_FRAME;
++		}
++#ifdef CONFIG_SERIAL_INGENIC_MAGIC_SYSRQ
++		if (uart_handle_sysrq_char(&up->port, ch))
++			goto ignore_char;
++#endif
++		uart_insert_char(&up->port, status, UART_LSR_OE, ch, flag);
++
++ignore_char:
++		status = serial_in(up, UART_LSR);
++	}
++	tty_flip_buffer_push(tty->port);
++}
++/* transmit one char*/
++static void transmit_chars(struct uart_ingenic_port *up)
++{
++	struct circ_buf *xmit = &up->port.state->xmit;
++	int count;
++	if (up->port.x_char) {
++		serial_out(up, UART_TX, up->port.x_char);//transmit char=port.x_char
++		up->port.icount.tx++;
++		up->port.x_char = 0;//transmit finish x_char=0
++		return;
++	}
++	if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {//xmit is empty or stop tx
++		serial_ingenic_stop_tx(&up->port);
++		return;
++	}
++
++	/* try to tx char until xmit is empty or count=0*/
++	count = up->port.fifosize / 2;
++	do {
++		serial_out(up, UART_TX, xmit->buf[xmit->tail]);
++		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
++		up->port.icount.tx++;
++		if (uart_circ_empty(xmit))
++			break;
++	} while (--count > 0);
++
++	/*if circ_chars is less than WARKUP_CHARS,then warkup 	*/
++	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)//get the renainder of circ_chars
++		uart_write_wakeup(&up->port);
++
++	/* if (uart_circ_empty(xmit)) */
++	/* 	serial_ingenic_stop_tx(&up->port); */
++}
++
++static void serial_ingenic_start_tx(struct uart_port *port)
++{
++	struct uart_ingenic_port *up = (struct uart_ingenic_port *)port;
++
++	if (!(up->ier & UART_IER_THRI)) {
++		up->ier |= UART_IER_THRI;
++		serial_out(up, UART_IER, up->ier);
++	}
++}
++
++static inline void check_modem_status(struct uart_ingenic_port *up)
++{
++	int status;
++	status = serial_in(up, UART_MSR);
++
++	if ((status & UART_MSR_ANY_DELTA) == 0)
++		return;
++
++	if (status & UART_MSR_DCTS)
++		uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
++
++	wake_up_interruptible(&up->port.state->port.delta_msr_wait);
++}
++/*
++ * This handles the interrupt from one port.
++ */
++static inline irqreturn_t serial_ingenic_irq(int irq, void *dev_id)
++{
++	struct uart_ingenic_port *up = dev_id;
++	unsigned int iir, lsr;
++	iir = serial_in(up, UART_IIR);
++	lsr = serial_in(up, UART_LSR);
++	if (iir & UART_IIR_NO_INT)
++		return IRQ_NONE;
++
++	if (lsr & UART_LSR_DR)
++		receive_chars((unsigned long)up);
++	check_modem_status(up);
++	if (lsr & UART_LSR_THRE)
++		transmit_chars(up);
++	return IRQ_HANDLED;
++}
++
++static unsigned int serial_ingenic_tx_empty(struct uart_port *port)
++{
++	struct uart_ingenic_port *up = (struct uart_ingenic_port *)port;
++	unsigned long flags;
++	unsigned int ret;
++
++	spin_lock_irqsave(&up->port.lock, flags);
++	ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
++	spin_unlock_irqrestore(&up->port.lock, flags);
++
++	return ret;
++}
++
++/*get modem control*/
++static unsigned int serial_ingenic_get_mctrl(struct uart_port *port)
++{
++	struct uart_ingenic_port *up = (struct uart_ingenic_port *)port;
++	unsigned char status;
++	unsigned int ret;
++
++	status = serial_in(up, UART_MSR);
++
++	ret = 0;
++	if (status & UART_MSR_CTS)
++		ret |= TIOCM_CTS;
++	return ret;
++}
++
++static void serial_ingenic_set_mctrl(struct uart_port *port, unsigned int mctrl)
++{
++	struct uart_ingenic_port *up = (struct uart_ingenic_port *)port;
++	unsigned char mcr = 0;
++	int is_auto_rts = up->mcr & UART_MCR_FCM;
++	int is_mctrl_enabled = up->mcr & UART_MCR_MDCE;
++
++	if (!is_mctrl_enabled) {
++		mcr = up->mcr;
++		up->old_mcr = mcr;
++
++		serial_out(up, UART_MCR, mcr);
++		return;
++	}
++
++	mcr |= UART_MCR_MDCE;
++
++	/*
++	 * If bit ITIOCM_RTS is cleared, force RTS to high whether auto RTS
++	 * is enabled or not, which is: in UMCR, MDCE bit set to 1, bit FCM
++	 * set to 0, and bit RTS set to 0.
++	 */
++	if (mctrl & TIOCM_RTS) {
++		if (is_auto_rts)
++			mcr |= UART_MCR_FCM;
++		else
++			mcr |= UART_MCR_RTS;
++	}
++	if (mctrl & TIOCM_LOOP)
++		mcr |= UART_MCR_LOOP;
++
++	if (mcr == up->old_mcr)
++		return;
++
++	up->old_mcr = mcr;
++	serial_out(up, UART_MCR, mcr);
++}
++
++static void serial_ingenic_break_ctl(struct uart_port *port, int break_state)
++{
++	struct uart_ingenic_port *up = (struct uart_ingenic_port *)port;
++	unsigned long flags;
++
++	spin_lock_irqsave(&up->port.lock, flags);
++	if (break_state == -1)
++		up->lcr |= UART_LCR_SBC;
++	else
++		up->lcr &= ~UART_LCR_SBC;
++	serial_out(up, UART_LCR, up->lcr);
++	spin_unlock_irqrestore(&up->port.lock, flags);
++}
++
++static int serial_ingenic_startup(struct uart_port *port)
++{
++	struct uart_ingenic_port *up = (struct uart_ingenic_port *)port;
++	unsigned long flags;
++	int retval;
++
++	/*
++	 * Allocate the IRQ
++	 */
++	retval = request_irq(port->irq, serial_ingenic_irq, 0, up->name, up);
++	if (retval)
++		return retval;
++
++	/*
++	 * Clear the FIFO buffers and disable them.
++	 * (they will be reenabled in set_termios())
++	 */
++	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
++	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO
++		   | UART_FCR_CLEAR_RCVR
++		   | UART_FCR_CLEAR_XMIT
++		   | UART_FCR_UME);
++	serial_out(up, UART_FCR, 0);
++
++	/*
++	 * Clear the interrupt registers.
++	 */
++	(void) serial_in(up, UART_LSR);
++	(void) serial_in(up, UART_RX);
++	(void) serial_in(up, UART_IIR);
++	(void) serial_in(up, UART_MSR);
++
++	/*
++	 * Now, initialize the UART
++	 */
++	serial_out(up, UART_LCR, UART_LCR_WLEN8);
++	serial_out(up, UART_ISR, 0);
++
++	spin_lock_irqsave(&up->port.lock, flags);
++	spin_unlock_irqrestore(&up->port.lock, flags);
++
++	/*
++	 * Finally, enable interrupts.  Note: Modem status interrupts
++	 * are set via set_termos(), which will be occurring imminently
++	 * anyway, so we don't enable them here.
++	 */
++	up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
++	serial_out(up, UART_IER, up->ier);
++
++	/*
++	 * And clear the interrupt registers again for luck.
++	 */
++	(void) serial_in(up, UART_LSR);
++	(void) serial_in(up, UART_RX);
++	(void) serial_in(up, UART_IIR);
++	(void) serial_in(up, UART_MSR);
++
++	return 0;
++}
++
++static void serial_ingenic_shutdown(struct uart_port *port)
++{
++	struct uart_ingenic_port *up = (struct uart_ingenic_port *)port;
++	unsigned long flags;
++	int tries;
++
++	/*
++	 * Disable interrupts from this port
++	 */
++	spin_lock_irqsave(&port->lock, flags);
++	up->ier = 0;
++	serial_out(up, UART_IER, 0);
++
++	spin_unlock_irqrestore(&port->lock, flags);
++
++	/*
++	 * Wait the RX FIFO to be read.
++	 */
++	for (tries = 3; (serial_in(up, UART_RCR) != 0) && tries; tries--) {
++		printk(KERN_WARNING "%s: waiting RX FIFO to be read\n", up->name);
++		msleep(10);
++	}
++	if (!tries)
++		printk(KERN_ERR "%s: RX FIFO hasn't been read before clearing\n",
++				up->name);
++
++	/*
++	 * Disable break condition and FIFOs
++	 */
++	serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
++	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO
++		   | UART_FCR_CLEAR_RCVR
++		   | UART_FCR_CLEAR_XMIT
++		   | UART_FCR_UME);
++
++	free_irq(port->irq, up);
++}
++
++static void init_hw_stopped_status(struct uart_port *uport)
++{
++	struct tty_port tport = uport->state->port;
++	struct tty_struct *tty = tport.tty;
++
++	if (tport.flags & ASYNC_CTS_FLOW) {
++		unsigned int mctrl;
++		spin_lock_irq(&uport->lock);
++		if (!((mctrl = uport->ops->get_mctrl(uport)) & TIOCM_CTS))
++			tty->hw_stopped = 1;
++		else
++			tty->hw_stopped = 0;
++		spin_unlock_irq(&uport->lock);
++	}
++}
++
++static void serial_ingenic_set_termios(struct uart_port *port, struct ktermios *termios,struct ktermios *old)
++{
++	struct uart_ingenic_port *up = (struct uart_ingenic_port *)port;
++	unsigned char cval=0;
++	unsigned long flags;
++	unsigned int baud;
++	unsigned short *quot1;
++
++	switch (termios->c_cflag & CSIZE) {
++		case CS5:
++			cval = UART_LCR_WLEN5;
++			break;
++		case CS6:
++			cval = UART_LCR_WLEN6;
++			break;
++		case CS7:
++			cval = UART_LCR_WLEN7;
++			break;
++		default:
++		case CS8:
++			cval = UART_LCR_WLEN8;
++			break;
++	}
++
++	if (termios->c_cflag & CSTOPB){
++		cval |= UART_LCR_STOP;
++	  }
++	if (termios->c_cflag & PARENB){
++		cval |= UART_LCR_PARITY;
++	  }
++	if (!(termios->c_cflag & PARODD)){
++		cval |= UART_LCR_EPAR;
++	  }
++	serial_out(up, UART_LCR, cval);//write cval to UART_LCR
++	/*
++	 * Ask the core to calculate the divisor for us.
++	 */
++	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);//get BaudRate
++	quot1 = serial47xx_get_divisor(port, baud);
++	/*
++	 * Ok, we're now changing the port state.  Do it with
++	 * interrupts disabled.
++	 */
++	spin_lock_irqsave(&up->port.lock, flags);
++	/*
++	 * Update the per-port timeout.
++	 */
++	uart_update_timeout(port, termios->c_cflag, baud);
++	up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
++	if (termios->c_iflag & INPCK)
++		up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
++	if (termios->c_iflag & (BRKINT | PARMRK))
++		up->port.read_status_mask |= UART_LSR_BI;
++
++	/*
++	 * Characters to ignore
++	 */
++	up->port.ignore_status_mask = 0;
++	if (termios->c_iflag & IGNPAR)
++		up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
++	if (termios->c_iflag & IGNBRK) {
++		up->port.ignore_status_mask |= UART_LSR_BI;
++		/*
++		 * If we're ignoring parity and break indicators,
++		 * ignore overruns too (for real raw support).
++		 */
++		if (termios->c_iflag & IGNPAR)
++			up->port.ignore_status_mask |= UART_LSR_OE;
++	}
++
++	/*
++	 * ignore all characters if CREAD is not set
++	 */
++	if ((termios->c_cflag & CREAD) == 0)
++		up->port.ignore_status_mask |= UART_LSR_DR;
++
++	/*
++	 * CTS flow control flag and modem status interrupts
++	 */
++	up->ier &= ~UART_IER_MSI;
++	/*
++	 *enable modem status interrupts and enable modem function and control by hardware
++	 */
++	if (UART_ENABLE_MS(&up->port, termios->c_cflag)) {
++		up->ier |= UART_IER_MSI;
++		serial_out(up, UART_IER, up->ier);
++		up->mcr |= UART_MCR_MDCE | UART_MCR_FCM;
++	}
++	/*
++	 *disable modem status interrupts and clear MCR bits of modem function and control by hardware
++	 */
++	else {
++		up->ier &= ~UART_IER_MSI;
++		serial_out(up, UART_IER, up->ier);
++		up->mcr &= ~(UART_MCR_MDCE | UART_MCR_FCM);
++	}
++
++	serial_dl_write(port, quot1[0]);
++	serial_out(up,UART_UMR, quot1[1]);//UART send or receive one bit takes quot1[1] cycles
++	serial_out(up,UART_UACR, quot1[2]);
++
++	up->lcr = cval;					/* Save LCR */
++	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 | UART_FCR_UME);
++
++	serial_ingenic_set_mctrl(port, up->port.mctrl);
++	spin_unlock_irqrestore(&up->port.lock, flags);
++
++	init_hw_stopped_status(port);
++}
++
++static inline void serial_dl_write(struct uart_port *up, int value)
++{
++	struct uart_ingenic_port *port = (struct uart_ingenic_port*)up;
++	int lcr = serial_in(port,UART_LCR);
++	serial_out(port,UART_LCR, UART_LCR_DLAB);
++	serial_out(port,UART_DLL, value & 0xff);
++	serial_out(port,UART_DLM, (value >> 8 )& 0xff);
++	serial_out(port,UART_LCR, lcr);
++}
++
++
++static int uart_setting_baud(const void *key,const void *elt)
++{
++	unsigned long *d = (unsigned long*)key;
++	struct baudtoregs_t *b = (struct baudtoregs_t *)elt;
++	if(*d > b->baud)
++		return 1;
++	else if(*d < b->baud)
++		return -1;
++	return 0;
++}
++
++static struct baudtoregs_t *search_divisor(unsigned int baud)
++{
++	struct baudtoregs_t *b = NULL;
++
++	if(baud <= baudtoregs[ARRAY_SIZE(baudtoregs) - 1].baud)
++		b = (struct baudtoregs_t *)bsearch((const void*)&baud,(const void*)baudtoregs,ARRAY_SIZE(baudtoregs),
++						       sizeof(struct baudtoregs_t),uart_setting_baud);
++
++	return b;
++}
++
++static unsigned short *get_divisor(struct uart_port *port, unsigned int baud)
++{
++	int err, sum, i, j;
++	int a[12], b[12];
++	unsigned short div, umr, uacr;
++	unsigned short umr_best, div_best, uacr_best;
++	unsigned long long t0, t1, t2, t3;
++
++	sum = 0;
++	umr_best = div_best = uacr_best = 0;
++	div = 1;
++
++	if ((port->uartclk % (16 * baud)) == 0) {
++		quot1[0] = port->uartclk / (16 * baud);
++		quot1[1] = 16;
++		quot1[2] = 0;
++		return quot1;
++	}
++
++	while (1) {
++		umr = port->uartclk / (baud * div);
++		if (umr > 32) {
++			div++;
++			continue;
++		}
++		if (umr < 4) {
++			break;
++		}
++		for (i = 0; i < 12; i++) {
++			a[i] = umr;
++			b[i] = 0;
++			sum = 0;
++			for (j = 0; j <= i; j++) {
++				sum += a[j];
++			}
++
++			/* the precision could be 1/2^(36) due to the value of t0 */
++			t0 = 0x1000000000LL;
++			t1 = (i + 1) * t0;
++			t2 = (sum * div) * t0;
++			t3 = div * t0;
++			do_div(t1, baud);
++			do_div(t2, port->uartclk);
++			do_div(t3, (2 * port->uartclk));
++			err = t1 - t2 - t3;
++
++			if (err > 0) {
++				a[i] += 1;
++				b[i] = 1;
++			}
++		}
++
++		uacr = 0;
++		for (i = 0; i < 12; i++) {
++			if (b[i] == 1) {
++				uacr |= 1 << i;
++			}
++		}
++		if (div_best ==0){
++			div_best = div;
++			umr_best = umr;
++			uacr_best = uacr;
++		}
++
++		/* the best value of umr should be near 16, and the value of uacr should better be smaller */
++		if (abs(umr - 16) < abs(umr_best - 16) || (abs(umr - 16) == abs(umr_best - 16) && uacr_best > uacr))
++		{
++			div_best = div;
++			umr_best = umr;
++			uacr_best = uacr;
++		}
++		div++;
++	}
++
++	quot1[0] = div_best;
++	quot1[1] = umr_best;
++	quot1[2] = uacr_best;
++
++	return quot1;
++}
++static unsigned short *serial47xx_get_divisor(struct uart_port *port, unsigned int baud)
++{
++	struct baudtoregs_t *bt;
++
++	bt = search_divisor(baud);
++	if(bt) {
++		quot1[0] = bt->div;
++		quot1[1] = bt->umr;
++		quot1[2] = bt->uacr;
++		return quot1;
++	}
++
++	return get_divisor(port, baud);
++}
++
++static void serial_ingenic_release_port(struct uart_port *port)
++{
++}
++
++static int serial_ingenic_request_port(struct uart_port *port)
++{
++	return 0;
++}
++
++static void serial_ingenic_config_port(struct uart_port *port, int flags)
++{
++	struct uart_ingenic_port *up = (struct uart_ingenic_port *)port;
++	up->port.type = PORT_8250;
++}
++
++static int serial_ingenic_verify_port(struct uart_port *port, struct serial_struct *ser)
++{
++	/* we don't want the core code to modify any port params */
++	return -EINVAL;
++}
++
++static const char *serial_ingenic_type(struct uart_port *port)
++{
++	struct uart_ingenic_port *up = (struct uart_ingenic_port *)port;
++	return up->name;
++}
++static struct uart_ingenic_port *serial_ingenic_ports[PORT_NR];
++static struct uart_driver serial_ingenic_reg;
++
++#ifdef CONFIG_SERIAL_INGENIC_CONSOLE
++
++#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
++
++/*
++ *	Wait for transmitter & holding register to empty
++ */
++static inline void wait_for_xmitr(struct uart_ingenic_port *up)
++{
++	unsigned int status, tmout = 10000;
++
++	/* Wait up to 10ms for the character(s) to be sent. */
++	do {
++		status = serial_in(up, UART_LSR);
++
++		if (status & UART_LSR_BI)
++			up->lsr_break_flag = UART_LSR_BI;
++
++		if (--tmout == 0)
++			break;
++		udelay(1);
++	} while ((status & BOTH_EMPTY) != BOTH_EMPTY);
++
++	/* Wait up to 1s for flow control if necessary */
++	if (up->port.flags & UPF_CONS_FLOW) {
++		tmout = 1000000;
++		while (--tmout &&
++				((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))//no CTS
++			udelay(1);
++	}
++}
++
++static void serial_ingenic_console_putchar(struct uart_port *port, int ch)
++{
++	struct uart_ingenic_port *up = (struct uart_ingenic_port *)port;
++
++	wait_for_xmitr(up);
++	serial_out(up, UART_TX, ch);
++}
++
++/*
++ * Print a string to the serial port trying not to disturb
++ * any possible real use of the port...
++ *
++ *	The console_lock must be held when we get here.
++ */
++static void serial_ingenic_console_write(struct console *co, const char *s, unsigned int count)
++{
++	struct uart_ingenic_port *up = serial_ingenic_ports[co->index];
++	unsigned int ier;
++
++	/*
++	 *	First save the IER then disable the interrupts
++	 */
++	spin_lock(&up->port.lock);
++	ier = up->ier;
++	up->ier &= ~UART_IER_THRI;
++	serial_out(up, UART_IER, up->ier);
++
++	uart_console_write(&up->port, s, count, serial_ingenic_console_putchar);
++
++	/*
++	 *	Finally, wait for transmitter to become empty
++	 *	and restore the IER
++	 */
++	wait_for_xmitr(up);
++	up->ier = ier;
++	serial_out(up, UART_IER, ier);
++	spin_unlock(&up->port.lock);
++}
++
++static int __init serial_ingenic_console_setup(struct console *co, char *options)
++{
++	struct uart_ingenic_port *up;
++	int baud = 57600;
++	int bits = 8;
++	int parity = 'n';
++	int flow = 'n';
++
++	if (co->index == -1 || co->index >= serial_ingenic_reg.nr)
++		co->index = 0;
++	up = serial_ingenic_ports[co->index];
++	if (!up)
++		return -ENODEV;
++
++	if (options)
++		uart_parse_options(options, &baud, &parity, &bits, &flow);
++
++	return uart_set_options(&up->port, co, baud, parity, bits, flow);
++}
++
++static struct console serial_ingenic_console = {
++	.name		= "ttyS",
++	.write		= serial_ingenic_console_write,
++	.device		= uart_console_device,
++	.setup		= serial_ingenic_console_setup,
++	.flags		= CON_PRINTBUFFER,
++	.index		= -1,
++	.data		= &serial_ingenic_reg,
++};
++
++#define INGENIC_CONSOLE	&serial_ingenic_console
++#else
++#define INGENIC_CONSOLE	NULL
++#endif
++
++struct uart_ops serial_ingenic_pops = {
++	.tx_empty	= serial_ingenic_tx_empty,//TX Buffer empty
++	.set_mctrl	= serial_ingenic_set_mctrl,//set Modem control
++	.get_mctrl	= serial_ingenic_get_mctrl,//get Modem control
++	.stop_tx	= serial_ingenic_stop_tx,//stop TX
++	.start_tx	= serial_ingenic_start_tx,//start tx
++	.stop_rx	= serial_ingenic_stop_rx,//stop rx
++	.enable_ms	= serial_ingenic_enable_ms,//modem status enable
++	.break_ctl	= serial_ingenic_break_ctl,//
++	.startup	= serial_ingenic_startup,//start endport
++	.shutdown	= serial_ingenic_shutdown,//shutdown endport
++	.set_termios	= serial_ingenic_set_termios,//change para of endport
++	.type		= serial_ingenic_type,//
++	.release_port	= serial_ingenic_release_port,//release port I/O
++	.request_port	= serial_ingenic_request_port,//
++	.config_port	= serial_ingenic_config_port,//
++	.verify_port	= serial_ingenic_verify_port,//
++};
++
++static struct uart_driver serial_ingenic_reg = {
++	.owner		= THIS_MODULE,
++	.driver_name	= "INGENIC serial",
++	.dev_name	= "ttyS",
++	.major		= TTY_MAJOR,
++	.minor		= 64,
++	.nr		= PORT_NR,
++	.cons		= INGENIC_CONSOLE,
++};
++
++#ifdef CONFIG_PM
++static int serial_ingenic_suspend(struct device *dev)
++{
++	struct uart_ingenic_port *up = dev_get_drvdata(dev);
++
++	if (up)
++		uart_suspend_port(&serial_ingenic_reg, &up->port);
++
++	return 0;
++}
++
++static int serial_ingenic_resume(struct device *dev)
++{
++	struct uart_ingenic_port *up = dev_get_drvdata(dev);
++
++	if (up)
++		uart_resume_port(&serial_ingenic_reg, &up->port);
++
++	return 0;
++}
++
++static const struct dev_pm_ops serial_ingenic_pm_ops = {
++	.suspend	= serial_ingenic_suspend,
++	.resume		= serial_ingenic_resume,
++};
++#endif
++
++#ifdef CONFIG_DEBUG_FS
++
++
++static ssize_t port_show_regs(struct file *file, char __user *user_buf,
++				size_t count, loff_t *ppos)
++{
++	struct uart_ingenic_port *up = file->private_data;
++	char *buf;
++	int len = 0;
++	unsigned int lcr;
++	unsigned long flags;
++	ssize_t ret;
++
++#define REGS_BUFSIZE	1024
++	buf = kzalloc(REGS_BUFSIZE, GFP_KERNEL);
++	if (!buf)
++		return 0;
++
++	spin_lock_irqsave(&up->port.lock, flags);
++
++	lcr = serial_in(up, UART_LCR);
++	serial_out(up, UART_LCR, lcr | UART_LCR_DLAB);
++	len += snprintf(buf + len, REGS_BUFSIZE - len, "%s:\n", up->name);
++	len += snprintf(buf + len, REGS_BUFSIZE - len, "UDLLR: 0x%02x\n", serial_in(up, UART_DLL));
++	len += snprintf(buf + len, REGS_BUFSIZE - len, "UDLHR: 0x%02x\n", serial_in(up, UART_DLM));
++	serial_out(up, UART_LCR, lcr & (~UART_LCR_DLAB));
++	len += snprintf(buf + len, REGS_BUFSIZE - len, "UIER: 0x%02x\n", serial_in(up, UART_IER));
++	serial_out(up, UART_LCR, lcr);
++	len += snprintf(buf + len, REGS_BUFSIZE - len, "UIIR: 0x%02x\n", serial_in(up, UART_IIR));
++	len += snprintf(buf + len, REGS_BUFSIZE - len, "UFCR: 0x%02x\n", serial_in(up, UART_FCR));
++	len += snprintf(buf + len, REGS_BUFSIZE - len, "ULCR: 0x%02x\n", lcr);
++	len += snprintf(buf + len, REGS_BUFSIZE - len, "UMCR: 0x%02x\n", serial_in(up, UART_MCR));
++	len += snprintf(buf + len, REGS_BUFSIZE - len, "ULSR: 0x%02x\n", serial_in(up, UART_LSR));
++	len += snprintf(buf + len, REGS_BUFSIZE - len, "UMSR: 0x%02x\n", serial_in(up, UART_MSR));
++	len += snprintf(buf + len, REGS_BUFSIZE - len, "USPR: 0x%02x\n", serial_in(up, UART_SCR));
++	len += snprintf(buf + len, REGS_BUFSIZE - len, "UISR: 0x%02x\n", serial_in(up, UART_ISR));
++	len += snprintf(buf + len, REGS_BUFSIZE - len, "UMR: 0x%02x\n", serial_in(up, UART_UMR));
++	len += snprintf(buf + len, REGS_BUFSIZE - len, "UACR: 0x%03x\n", serial_in(up, UART_UACR));
++	len += snprintf(buf + len, REGS_BUFSIZE - len, "URCR: 0x%03x\n", serial_in(up, UART_RCR));
++	len += snprintf(buf + len, REGS_BUFSIZE - len, "UTCR: 0x%03x\n", serial_in(up, UART_TCR));
++
++	spin_unlock_irqrestore(&up->port.lock, flags);
++
++	ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
++	kfree(buf);
++#undef REGS_BUFSIZE
++	return ret;
++}
++
++static const struct file_operations port_regs_ops = {
++	.owner		= THIS_MODULE,
++	.open		= simple_open,
++	.read		= port_show_regs,
++	.llseek		= default_llseek,
++};
++#endif
++
++static const struct of_device_id serial_ingenic_of_match[] = {
++	{.compatible = "ingenic,8250-uart", .data = NULL},
++};
++
++MODULE_DEVICE_TABLE(of, serial_ingenic_of_match);
++
++static int serial_ingenic_probe(struct platform_device *pdev)
++{
++	struct uart_ingenic_port *up;
++	struct resource *mmres;
++	int irq;
++	char clk_name[20];
++	unsigned long uartclk;
++
++	mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	irq = platform_get_irq(pdev, 0);
++	if (!mmres || irq < 0)
++		return -ENODEV;
++
++	up = devm_kzalloc(&pdev->dev, sizeof(struct uart_ingenic_port), GFP_KERNEL);
++	if (!up)
++		return -ENOMEM;
++
++	pdev->id = of_alias_get_id(pdev->dev.of_node, "uart");
++
++	sprintf(up->name,"uart%d",pdev->id);
++
++	sprintf(clk_name, "gate_uart%d",pdev->id);
++	up->clk = devm_clk_get(&pdev->dev, clk_name);
++	if (IS_ERR_OR_NULL(up->clk)) {
++		printk(KERN_WARNING "%s: Failed to get uart clk. Using Default clk rate(24MHz)\n", up->name);
++		uartclk = 24000000;
++		up->clk = NULL;
++	} else {
++		uartclk = clk_get_rate(up->clk);
++	}
++
++	up->port.type = PORT_8250;
++	up->port.iotype = UPIO_MEM;
++	up->port.mapbase = mmres->start;
++	up->port.mapsize = resource_size(mmres);
++	up->port.irq = irq;
++	up->port.fifosize = 64;
++	up->port.ops = &serial_ingenic_pops;
++	up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_INGENIC_CONSOLE);
++	up->port.line = pdev->id;
++	up->port.dev = &pdev->dev;
++	up->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
++	up->port.uartclk = uartclk;
++	up->port.membase = devm_ioremap_resource(&pdev->dev, mmres);
++	if (!up->port.membase)
++		return -ENOMEM;
++
++	if(up->clk)
++		clk_prepare_enable(up->clk);
++
++	serial_ingenic_ports[pdev->id] = up;
++	uart_add_one_port(&serial_ingenic_reg, &up->port);
++
++	platform_set_drvdata(pdev, up);
++
++#ifdef CONFIG_DEBUG_FS
++	{
++		char name[20];
++		snprintf(name, sizeof(name), "uart%d_regs", up->port.line);
++		up->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
++					NULL, up, &port_regs_ops);
++	}
++#endif
++	return 0;
++}
++
++static int serial_ingenic_remove(struct platform_device *pdev)
++{
++	struct uart_ingenic_port *up = platform_get_drvdata(pdev);
++
++#ifdef CONFIG_DEBUG_FS
++	if (up->debugfs)
++		debugfs_remove(up->debugfs);
++#endif
++	platform_set_drvdata(pdev, NULL);
++
++	uart_remove_one_port(&serial_ingenic_reg, &up->port);
++
++	if(up->clk)
++		clk_disable_unprepare(up->clk);
++
++	return 0;
++}
++
++static struct platform_driver serial_ingenic_driver = {
++	.probe          = serial_ingenic_probe,
++	.remove         = serial_ingenic_remove,
++
++	.driver		= {
++		.name	= "ingenic-uart",
++		.owner	= THIS_MODULE,
++		.of_match_table = of_match_ptr(serial_ingenic_of_match),
++#ifdef CONFIG_PM
++		.pm	= &serial_ingenic_pm_ops,
++#endif
++	},
++};
++
++int __init serial_ingenic_init(void)
++{
++	int ret;
++	ret = uart_register_driver(&serial_ingenic_reg);
++	if (ret != 0)
++		return ret;
++
++	ret = platform_driver_register(&serial_ingenic_driver);
++	if (ret != 0)
++		uart_unregister_driver(&serial_ingenic_reg);
++
++	return ret;
++}
++
++void __exit serial_ingenic_exit(void)
++{
++	platform_driver_unregister(&serial_ingenic_driver);
++	uart_unregister_driver(&serial_ingenic_reg);
++}
++
++#ifdef CONFIG_EARLY_INIT_RUN
++rootfs_initcall(serial_ingenic_init);
++
++#else
++module_init(serial_ingenic_init);
++
++#endif
++
++module_exit(serial_ingenic_exit);
++
++MODULE_DESCRIPTION("Ingenic Compatible UART driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-uart");
+diff --git a/module_drivers/drivers/tty/serial/ingenic_uart.h b/module_drivers/drivers/tty/serial/ingenic_uart.h
+new file mode 100644
+index 000000000..75491928a
+--- /dev/null
++++ b/module_drivers/drivers/tty/serial/ingenic_uart.h
+@@ -0,0 +1,117 @@
++/*
++ *
++ * Copyright (C) 1992, 1994 by Theodore Ts'o.
++ *
++ * Redistribution of this file is permitted under the terms of the GNU
++ * Public License (GPL)
++ *
++ * These are the UART port assignments, expressed as offsets from the base
++ * register.  These assignments should hold for any serial port based on
++ * a 8250, 16450, or 16550(A).
++ */
++
++#ifndef __INGENIC_UART_H__
++#define __INGENIC_UART_H__
++
++/*
++ * DLAB=0
++ */
++#define UART_RX		0	/* In:  Receive buffer */
++#define UART_TX		0	/* Out: Transmit buffer */
++
++#define UART_IER	1	/* Out: Interrupt Enable Register */
++#define UART_IER_RTOIE		0x10 /* Receiver Time Out Interrupt Enable */
++#define UART_IER_MSI		0x08 /* Enable Modem status interrupt */
++#define UART_IER_RLSI		0x04 /* Enable receiver line status interrupt */
++#define UART_IER_THRI		0x02 /* Enable Transmitter holding register int. */
++#define UART_IER_RDI		0x01 /* Enable receiver data interrupt */
++
++#define UART_IIR	2	/* In:  Interrupt ID Register */
++#define UART_IIR_NO_INT		0x01 /* No interrupts pending */
++#define UART_IIR_ID		0x06 /* Mask for the interrupt ID */
++#define UART_IIR_MSI		0x00 /* Modem status interrupt */
++#define UART_IIR_THRI		0x02 /* Transmitter holding register empty */
++#define UART_IIR_RDI		0x04 /* Receiver data interrupt */
++#define UART_IIR_RLSI		0x06 /* Receiver line status interrupt */
++
++#define UART_IIR_BUSY		0x07 /* DesignWare APB Busy Detect */
++
++#define UART_FCR	2	/* Out: FIFO Control Register */
++#define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
++#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
++#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
++#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
++#define UART_FCR_UME		0x10 /* UME */
++
++#define UART_FCR_R_TRIG_00	0x00
++#define UART_FCR_R_TRIG_01	0x40
++#define UART_FCR_R_TRIG_10	0x80
++#define UART_FCR_R_TRIG_11	0xc0
++#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
++
++#define UART_LCR	3	/* Out: Line Control Register */
++/*
++ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
++ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
++ */
++#define UART_LCR_DLAB		0x80 /* Divisor latch access bit */
++#define UART_LCR_SBC		0x40 /* Set break control */
++#define UART_LCR_SPAR		0x20 /* Stick parity (?) */
++#define UART_LCR_EPAR		0x10 /* Even parity select */
++#define UART_LCR_PARITY		0x08 /* Parity Enable */
++#define UART_LCR_STOP		0x04 /* Stop bits: 0=1 bit, 1=2 bits */
++#define UART_LCR_WLEN5		0x00 /* Wordlength: 5 bits */
++#define UART_LCR_WLEN6		0x01 /* Wordlength: 6 bits */
++#define UART_LCR_WLEN7		0x02 /* Wordlength: 7 bits */
++#define UART_LCR_WLEN8		0x03 /* Wordlength: 8 bits */
++
++/*
++ * Access to some registers depends on register access / configuration
++ * mode.
++ */
++#define UART_LCR_CONF_MODE_A	UART_LCR_DLAB	/* Configutation mode A */
++#define UART_LCR_CONF_MODE_B	0xBF		/* Configutation mode B */
++
++#define UART_MCR	4	/* Out: Modem Control Register */
++#define UART_MCR_MDCE		0x80 /* Enable modem function */
++#define UART_MCR_FCM		0x40 /* flow control by hardware */
++#define UART_MCR_LOOP		0x10 /* Enable loopback test mode */
++#define UART_MCR_RTS		0x02 /* RTS complement */
++
++#define UART_LSR	5	/* In:  Line Status Register */
++#define UART_LSR_FIFOE		0x80 /* Fifo error */
++#define UART_LSR_TEMT		0x40 /* Transmitter empty */
++#define UART_LSR_THRE		0x20 /* Transmit-hold-register empty */
++#define UART_LSR_BI		0x10 /* Break interrupt indicator */
++#define UART_LSR_FE		0x08 /* Frame error indicator */
++#define UART_LSR_PE		0x04 /* Parity error indicator */
++#define UART_LSR_OE		0x02 /* Overrun error indicator */
++#define UART_LSR_DR		0x01 /* Receiver data ready */
++#define UART_LSR_BRK_ERROR_BITS	0x1E /* BI, FE, PE, OE bits */
++
++#define UART_MSR	6	/* In:  Modem Status Register */
++#define UART_MSR_CTS		0x10 /* Clear to Send */
++#define UART_MSR_DCTS		0x01 /* Delta CTS */
++#define UART_MSR_ANY_DELTA	0x0F /* Any of the delta bits! */
++#define UART_RCR   16
++#define UART_TCR   17
++
++#define UART_SCR	7	/* I/O: Scratch Register */
++
++/*
++ * The Ingenic xburst on-chip UARTs define these bits
++ */
++
++#define UART_ISR	8
++#define UART_UMR	9
++#define UART_UACR	10
++#define UART_RCR    16 /* RX FIFO Counter Register */
++#define UART_TCR    17 /* TX FIFO Counter Register */
++
++/*
++ * DLAB=1
++ */
++#define UART_DLL	0	/* Out: Divisor Latch Low */
++#define UART_DLM	1	/* Out: Divisor Latch High */
++
++#endif /* __INGENIC_UART_H__ */
+diff --git a/module_drivers/drivers/video/Makefile b/module_drivers/drivers/video/Makefile
+new file mode 100644
+index 000000000..feb5d7ceb
+--- /dev/null
++++ b/module_drivers/drivers/video/Makefile
+@@ -0,0 +1,6 @@
++obj-y += fbdev/
++obj-$(CONFIG_INGENIC_AVPU) += ingenic_avpu/
++obj-$(CONFIG_INGENIC_BSCALER) += ingenic_bscaler/
++obj-$(CONFIG_JZ_IPU) += ingenic_ipu/
++obj-$(CONFIG_INGENIC_SOC_NNA) += ingenic-nna/
++obj-$(CONFIG_TRUE_COLOR_LOGO) += logo-ingenic/
+diff --git a/module_drivers/drivers/video/fbdev/Makefile b/module_drivers/drivers/video/fbdev/Makefile
+new file mode 100644
+index 000000000..10e2febc6
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/Makefile
+@@ -0,0 +1 @@
++obj-y += ingenic/
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/Kconfig b/module_drivers/drivers/video/fbdev/ingenic/Kconfig
+new file mode 100644
+index 000000000..42361a132
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/Kconfig
+@@ -0,0 +1,60 @@
++menuconfig FB_INGENIC
++	tristate "Ingenic Framebuffer Driver"
++	depends on FB
++	select FB_CFB_FILLRECT
++	select FB_CFB_COPYAREA
++	select FB_CFB_IMAGEBLIT
++	help
++		LCD Driver for INGENIC
++
++config FB_VSYNC_SKIP_DISABLE
++        bool "Disable Vsync skip"
++        depends on FB_INGENIC
++        help
++          Disable Vsync skip
++
++config FB_VSYNC_SKIP
++        int "Vsync skip ratio[0..9]"
++        depends on FB_INGENIC
++        default 9
++        help
++          Vsync skip ratio
++
++config FB_INGENIC_NR_FRAMES
++	int "how many frames support"
++	depends on FB_INGENIC
++	default 3
++
++config FB_INGENIC_NR_LAYERS
++	int "how many layers support"
++	depends on FB_INGENIC
++	default 4
++
++config FB_INGENIC_DEBUG
++        bool "fb test for displaying color bar"
++        depends on FB_INGENIC
++        default n
++        help
++           fb test for displaying color bar in your board.
++
++config SLCDC_CONTINUA
++    tristate "SLCDC CONTINUA TRANFER"
++    depends on FB_INGENIC
++    default n
++
++config SLCDC_USE_TE
++	tristate "SLCDC USE TE SIGNAL"
++	depends on FB_INGENIC
++	default n
++
++config FB_INGENIC_MIPI_DSI
++	bool "ingenic mipi dsi interface"
++	depends on FB_INGENIC_V12
++	default n
++
++
++if FB_INGENIC
++#source "module_drivers/drivers/video/fbdev/ingenic/spi_fb_v12/Kconfig"
++source "module_drivers/drivers/video/fbdev/ingenic/fb_stage/Kconfig"
++endif
++
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/Makefile b/module_drivers/drivers/video/fbdev/ingenic/Makefile
+new file mode 100644
+index 000000000..9a59e98a2
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/Makefile
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_FB_INGENIC_STAGE)  += fb_stage/
++#obj-$(CONFIG_SPI_FB_V12)	+= spi_fb_v12/
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/Kconfig b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/Kconfig
+new file mode 100644
+index 000000000..ddedd57f5
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/Kconfig
+@@ -0,0 +1,12 @@
++menuconfig FB_INGENIC_STAGE
++	tristate "Ingenic Framebuffer Driver for stage"
++	depends on FB_INGENIC
++	select FB_INGENIC_DISPLAYS_STAGE
++	select FB_CFB_FILLRECT
++	select FB_CFB_COPYAREA
++	select FB_CFB_IMAGEBLIT
++	select V4L2_MEM2MEM_DEV
++	help
++	  Framebuffer support for the Version 12 DPU SoC.
++
++source "module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/Kconfig"
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/Makefile b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/Makefile
+new file mode 100644
+index 000000000..6f7c8f6d6
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/Makefile
+@@ -0,0 +1,12 @@
++ingenic_fb_stage-y := ingenicfb.o\
++			dpu_ctrl.o\
++			hw_composer.o\
++			hw_composer_fb.o\
++			sysfs.o\
++			jz_mipi_dsi/jz_mipi_dsi.o\
++			jz_mipi_dsi/jz_mipi_dsi_lowlevel.o\
++			jz_mipi_dsi/jz_mipi_dsih_hal.o
++obj-$(CONFIG_FB_INGENIC_STAGE) += ingenic_fb_stage.o
++obj-y += displays/
++
++obj-y += hw_composer_v4l2.o
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/README.md b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/README.md
+new file mode 100644
+index 000000000..c4c1fb77c
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/README.md
+@@ -0,0 +1,59 @@
++## 驱动结构
++
++
++
++
++1. dpu ctrls 最底层硬件�作
++2. hwcomposer �装的���作.
++3. hwcomp-v4l2 利用composer的功能，导出到v4l2层，支�格�转�，和缩放硬件加速处�。memory to memory.
++4. ingenicfb 是标准framebuffer驱动，默认使用的是Simple RDMA 用���数�. �时实例化了hwcomposer，�供用户接�全功能自定义�置.
++5. hwcomp-fb 是利用composer的功能，导出标准framebuffer接�，用户�以�独在�一层上绘图，互�干扰.
++	-> 例如： 一层�UI， 一层�视频.
++6. sysfs 接�主�是用于快速修改hwcomp-fb的属性，方便用户动�改�layer 属性.
++
++
++注�事项: hwcomp-v4l2 和 hwcomp-fb �能�时使用。当有格�转�和��显示�时存在时，最好先��到内存，在通过RDMA显示.
++
++
++
++
++```
++
++        ┌───────────────────�    ┌───────────────�     ┌──────────────────�   ┌───────────────�
++        │   v4l2-hwcomp     │    │               │     │                  │   │dynamic ctrl   │
++        │   NV12/RGB->RGB   │    │ ioctl ops     │     │ standard fb dev  │   │for export fb  │
++        │    scale/csc      │    │               │     │                  │   │               │
++        └────────┬──────────┘    └──────┬────────┘     └─────────┬────────┘   └───────┬───────┘
++                 │                      │                        │                    │
++  ───────────────┼──────────────────────┼────────────────────────┼────────────────────┼─────────
++                 │                      │                        │                    │
++        ┌────────▼──────────�   ┌───────▼────────�     ┌─────────▼────────�           │
++        │                   │   │                │     │                  │    ┌──────▼──────�
++        │                   │   │                │     │                  │    │             │
++        │   hwcomp-v4l2     │   │  ingenicfb     │     │  hwcomp-fb       ◄────┤   sysfs     │
++        │                   │   │                │     │                  │    │             │
++        │                   │   │                │     │                  │    └─────────────┘
++        └────────▲──────────┘   └───────▲────────┘     └─────────▲────────┘
++                 │                      │                        │
++                 │                      │                        │
++                 │                      │                        │
++                 │                      │                        │
++                 │                      │                        │
++                 │                      │                        │
++                 │        ┌─────────────┴──────────�             │
++                 │        │                        │             │
++                 └────────┤     hwcomposer         ├─────────────┘
++                          │                        │
++                          └────────────┬───────────┘
++                                       │
++                                       │
++           ┌───────────────────────────▼───────────────────────────�
++           │                                                       │
++           │                    dpu ctrls                          │
++           │                                                       │
++           └───────────────────────────────────────────────────────┘
++
++```
++
++
++
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/Kconfig b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/Kconfig
+new file mode 100644
+index 000000000..df7c2fc6c
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/Kconfig
+@@ -0,0 +1,182 @@
++menuconfig FB_INGENIC_DISPLAYS_STAGE
++	tristate "Supported lcd panels"
++	depends on FB_INGENIC_STAGE
++	select BACKLIGHT_LCD_SUPPORT
++	select LCD_CLASS_DEVICE
++	select BACKLIGHT_CLASS_DEVICE
++
++
++config STAGE_Y88249
++	tristate "lcd panel y88249"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel y88249, for ingenicfb drivers.
++
++config STAGE_KD050HDFIA019
++	tristate "lcd panel kd050hdfia019"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel kd050hdfia019, for ingenicfb drivers.
++
++config STAGE_MA0060
++	tristate "lcd panel MA0060"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel MA0060, for ingenicfb drivers.
++
++config STAGE_KD050HDFIA020
++	tristate "lcd panel kd050hdfia020"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel kd050hdfia020, for ingenicfb drivers.
++
++config STAGE_FW050
++	tristate "lcd panel FW050"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel FW050, for ingenicfb drivers.
++
++config STAGE_FW040
++	tristate "lcd panel FW040"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel FW040, for ingenicfb drivers.
++
++config STAGE_FW035
++	tristate "lcd panel FW035"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel FW035, for ingenicfb drivers.
++
++config STAGE_TL040WVS03CT
++	tristate "lcd panel tl040wvs03ct"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel tl040wvs03ct, for ingenicfb drivers.
++
++config STAGE_TL040HDS01CT
++	tristate "lcd panel tl040hds01ct"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel tl040hds01ct, for ingenicfb drivers.
++
++config STAGE_JD9161Z
++	tristate "lcd panel JD9161Z"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel JD9161Z, for ingenicfb drivers.
++
++config STAGE_JD9365D
++	tristate "lcd panel JD9365D"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel JD9365D, for ingenicfb drivers.
++
++config STAGE_ATK7016
++	tristate "lcd panel ATK7016"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel ATK7016, for ingenicfb drivers.
++
++config STAGE_JD9365
++	tristate "lcd panel JD9365"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel JD9365, for ingenicfb drivers.
++
++config STAGE_GC9203
++	tristate "lcd panel gc9203"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		spi slcd panel r108104_gc9203, for ingenicfb drivers.
++
++config STAGE_ST7701S
++	tristate "lcd panel ST7701S"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel ST7701S, for ingenicfb drivers.
++
++config STAGE_ST7701S_RGB666
++	tristate "lcd panel ST7701S-RGB666"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel ST7701S spi+rgb (fmt:rgb666) interface, for ingenicfb drivers.
++
++config STAGE_ST7701S_DX
++	tristate "lcd panel st7701s_dx3.95ips"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel st7701s_dx3.95ips(mipi)480*480, for ingenicfb drivers.
++
++config STAGE_YTS500XLAI
++	tristate "lcd panel YTS500XLAI"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel YTS500XLAI, for ingenicfb drivers.
++
++config STAGE_YLYM286A
++	tristate "lcd panel ylym286a"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel ylym286a with bridge lt9211, for ingenicfb drivers.
++
++config STAGE_KD035HVFBD037
++	tristate "SLCD KD035HVFBD037 with control IC otm4802a (320x480)"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel KD035HVFBD037, for ingenicfb drivers.
++
++config PANEL_STAGE_MV238FHM_N30
++	tristate "lcd panel MV238FHM-N30"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel MV238FHM-N30 with bridge lt9211, for ingenicfb drivers.
++
++config STAGE_EK79007AD
++	tristate "lcd panel ek79007ad"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel EK79007AD, for ingenicfb drivers.
++
++config STAGE_JD9366
++	tristate "lcd panel JD9366"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel JD9366, for ingenicfb drivers.
++
++config STAGE_BM8766
++	tristate "tft bm8766 (480x800)"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel bm8766, for ingenicfb drivers.
++
++config STAGE_KD050WVFPA029
++	tristate "tft kd050wvfpa029 (800x480)"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel kd050wvfpa029, for ingenicfb drivers.
++
++config STAGE_GWMTF16499B
++	tristate "tft gwmtf16499b (240X320)"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel gwmtf16499b, for ingenicfb drivers.
++
++config STAGE_ST7282
++	tristate "lcd panel st7282"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel st7282, for ingenicfb drivers.
++
++config STAGE_G104X1L04
++	tristate "lcd panel G104X1L04"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel G104X1L04, for ingenicfb drivers.
++
++
++config STAGE_KD035HVFMD057
++	tristate "lcd panel kd035hvfmd057"
++	depends on FB_INGENIC_DISPLAYS_STAGE
++	help
++		lcd panel kd035hvfmd057, for ingenicfb drivers.
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/Makefile b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/Makefile
+new file mode 100644
+index 000000000..a8da7d04c
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/Makefile
+@@ -0,0 +1,29 @@
++obj-$(CONFIG_STAGE_Y88249) += panel-y88249.o
++obj-$(CONFIG_STAGE_KD050HDFIA019) += panel-kd050hdfia019.o
++obj-$(CONFIG_STAGE_MA0060) += panel-ma0060.o
++obj-$(CONFIG_STAGE_TL040WVS03CT) += panel-tl040wvs03ct.o
++obj-$(CONFIG_STAGE_TL040HDS01CT) += panel-tl040hds01ct.o
++obj-$(CONFIG_STAGE_JD9161Z) += panel-jd9161z.o
++obj-$(CONFIG_STAGE_JD9365D) += jd9365d/panel-jd9365d.o
++obj-$(CONFIG_STAGE_JD9365) += jd9365/panel-jd9365.o
++obj-$(CONFIG_STAGE_ST7701S) += panel-st7701s.o
++obj-$(CONFIG_STAGE_ST7701S_DX) += st7701s_dx3.95ips/panel-st7701sdx.o
++obj-$(CONFIG_STAGE_ST7701S_RGB666) += panel-st7701s-rgb666.o
++obj-$(CONFIG_STAGE_YTS500XLAI) += panel-yts500xlai.o
++obj-$(CONFIG_STAGE_YLYM286A) += panel-ylym286a.o
++obj-$(CONFIG_STAGE_KD035HVFBD037)	+= panel-kd035hvfbd037.o
++obj-$(CONFIG_PANEL_STAGE_MV238FHM_N30) += panel-MV238FHM-N30.o
++obj-$(CONFIG_STAGE_EK79007AD) += panel-ek79007ad.o
++obj-$(CONFIG_STAGE_JD9366) += panel-jd9366.o
++obj-$(CONFIG_STAGE_BM8766) += panel-bm8766.o
++obj-$(CONFIG_STAGE_GWMTF16499B) += panel-gwmtf16499b.o
++obj-$(CONFIG_STAGE_KD050HDFIA020) += panel-kd050hdfia020.o
++obj-$(CONFIG_STAGE_FW050) += panel-fw050.o
++obj-$(CONFIG_STAGE_ST7282) += panel-st7282.o
++obj-$(CONFIG_STAGE_KD050WVFPA029) += panel-kd050wvfpa029.o
++obj-$(CONFIG_STAGE_G104X1L04) += panel-G104X1L04.o
++obj-$(CONFIG_STAGE_KD035HVFMD057) += panel-kd035hvfmd057.o
++obj-$(CONFIG_STAGE_GC9203) += panel-gc9203.o
++obj-$(CONFIG_STAGE_FW040) += panel-fw040.o
++obj-$(CONFIG_STAGE_FW035) += panel-fw035.o
++obj-$(CONFIG_STAGE_ATK7016) += panel-atk7016.o
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/jd9365/JD9365_8001280init-4lane.txt b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/jd9365/JD9365_8001280init-4lane.txt
+new file mode 100644
+index 000000000..8c7b34d8a
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/jd9365/JD9365_8001280init-4lane.txt
+@@ -0,0 +1,284 @@
++//========== JD9365 INX T2 10.1" initial setting ==========//
++Resolution:800x1280
++
++External system porch setting: 
++VS=4;
++VBP=8;
++VFP=30;
++HS=20;
++HBP=20;
++HFP=20;
++Frame rate:60HZ
++
++MIPI CLK:410Mbps(205MHZ);
++
++//-----------------------Initial  Code--------------------------------------//
++
++//Page0
++SSD_Single(0xE0,0x00);
++
++//--- PASSWORD  ----//
++SSD_Single(0xE1,0x93);
++SSD_Single(0xE2,0x65);
++SSD_Single(0xE3,0xF8);
++SSD_Single(0x80,0x03);
++
++
++
++//--- Page1  ----//
++SSD_Single(0xE0,0x01);
++
++//Set VCOM
++SSD_Single(0x01,0x67);
++
++//Set Gamma Power, VGMP,VGMN,VGSP,VGSN
++SSD_Single(0x17,0x00);
++SSD_Single(0x18,0xBF);//4.5V, D7=4.8V
++SSD_Single(0x19,0x01);//0.0V
++SSD_Single(0x1A,0x00);
++SSD_Single(0x1B,0xBF);
++SSD_Single(0x1C,0x01);
++SSD_Single(0x0C,0x74);
++                
++//Set Gate Power
++SSD_Single(0x1F,0x70);	//VGH_REG=16.2V
++SSD_Single(0x20,0x2D);	//VGL_REG=-12V
++SSD_Single(0x21,0x2D);	//VGL_REG2=-12V
++SSD_Single(0x22,0x7E);
++SSD_Single(0x0C,0x74);	
++
++
++SSD_Single(0x35,0x28);	//SAP
++
++SSD_Single(0x37,0x19);	//SS=1,BGR=1
++
++//SET RGBCYC
++SSD_Single(0x38,0x05);	//JDT=101 zigzag inversion
++SSD_Single(0x39,0x00);
++SSD_Single(0x3A,0x01);
++SSD_Single(0x3C,0x7C);	//SET EQ3 for TE_H
++SSD_Single(0x3D,0xFF);	//SET CHGEN_ON, modify 20140806 
++SSD_Single(0x3E,0xFF);	//SET CHGEN_OFF, modify 20140806 
++SSD_Single(0x3F,0x7F);	//SET CHGEN_OFF2, modify 20140806
++
++
++//Set TCON
++SSD_Single(0x40,0x06);	//RSO=
++SSD_Single(0x41,0xA0);	//LN=640->1280 line
++SSD_Single(0x43,0x1E);	//VFP=30
++SSD_Single(0x44,0x0B);	//VBP=12
++SSD_Single(0x45,0x28);  //HBP=40
++
++//--- power voltage  ----//
++SSD_Single(0x55,0x01);	
++SSD_Single(0x57,0xA9);
++//SSD_Single(0x58,0x0A);
++SSD_Single(0x59,0x0A);	//VCL = -2.5V
++SSD_Single(0x5A,0x2E);	//VGH = 16.2V
++SSD_Single(0x5B,0x1A);	//VGL = -12V
++SSD_Single(0x5C,0x15);	//pump clk
++
++
++//--- Gamma  ----//
++SSD_Single(0x5D,0x7F);
++SSD_Single(0x5E,0x64);
++SSD_Single(0x5F,0x53);
++SSD_Single(0x60,0x47);
++SSD_Single(0x61,0x43);
++SSD_Single(0x62,0x33);
++SSD_Single(0x63,0x37);
++SSD_Single(0x64,0x21);
++SSD_Single(0x65,0x39);
++SSD_Single(0x66,0x37);
++SSD_Single(0x67,0x34);
++SSD_Single(0x68,0x50);
++SSD_Single(0x69,0x3D);
++SSD_Single(0x6A,0x44);
++SSD_Single(0x6B,0x36);
++SSD_Single(0x6C,0x34);
++SSD_Single(0x6D,0x25);
++SSD_Single(0x6E,0x15);
++SSD_Single(0x6F,0x02);
++SSD_Single(0x70,0x7F);
++SSD_Single(0x71,0x64);
++SSD_Single(0x72,0x53);
++SSD_Single(0x73,0x47);
++SSD_Single(0x74,0x43);
++SSD_Single(0x75,0x33);
++SSD_Single(0x76,0x37);
++SSD_Single(0x77,0x21);
++SSD_Single(0x78,0x39);
++SSD_Single(0x79,0x37);
++SSD_Single(0x7A,0x34);
++SSD_Single(0x7B,0x50);
++SSD_Single(0x7C,0x3D);
++SSD_Single(0x7D,0x44);
++SSD_Single(0x7E,0x36);
++SSD_Single(0x7F,0x34);
++SSD_Single(0x80,0x25);
++SSD_Single(0x81,0x15);
++SSD_Single(0x82,0x02);
++
++
++//Page2, for GIP
++SSD_Single(0xE0,0x02);
++
++//GIP_L Pin mapping
++SSD_Single(0x00,0x52);//RESET_EVEN
++SSD_Single(0x01,0x55);//VSSG_EVEN 
++SSD_Single(0x02,0x55);//VSSG_EVEN 
++SSD_Single(0x03,0x50);//STV2_ODD  
++SSD_Single(0x04,0x77);//VDD2_ODD  
++SSD_Single(0x05,0x57);//VDD1_ODD  
++SSD_Single(0x06,0x55);//x         
++SSD_Single(0x07,0x4E);//CK11      
++SSD_Single(0x08,0x4C);//CK9       
++SSD_Single(0x09,0x5F);//x         
++SSD_Single(0x0A,0x4A);//CK7       
++SSD_Single(0x0B,0x48);//CK5       
++SSD_Single(0x0C,0x55);//x         
++SSD_Single(0x0D,0x46);//CK3       
++SSD_Single(0x0E,0x44);//CK1       
++SSD_Single(0x0F,0x40);//STV1_ODD  
++SSD_Single(0x10,0x55);//x         
++SSD_Single(0x11,0x55);//x         
++SSD_Single(0x12,0x55);//x         
++SSD_Single(0x13,0x55);//x         
++SSD_Single(0x14,0x55);//x         
++SSD_Single(0x15,0x55);//x         
++
++//GIP_R Pin mapping
++SSD_Single(0x16,0x53);//RESET__EVEN
++SSD_Single(0x17,0x55);//VSSG_EVEN  
++SSD_Single(0x18,0x55);//VSSG_EVEN  
++SSD_Single(0x19,0x51);//STV2_EVEN  
++SSD_Single(0x1A,0x77);//VDD2_EVEN  
++SSD_Single(0x1B,0x57);//VDD1_EVEN  
++SSD_Single(0x1C,0x55);//x          
++SSD_Single(0x1D,0x4F);//CK12       
++SSD_Single(0x1E,0x4D);//CK10       
++SSD_Single(0x1F,0x5F);//x          
++SSD_Single(0x20,0x4B);//CK8        
++SSD_Single(0x21,0x49);//CK6        
++SSD_Single(0x22,0x55);//x          
++SSD_Single(0x23,0x47);//CK4        
++SSD_Single(0x24,0x45);//CK2        
++SSD_Single(0x25,0x41);//STV1_EVEN  
++SSD_Single(0x26,0x55);//x          
++SSD_Single(0x27,0x55);//x          
++SSD_Single(0x28,0x55);//x          
++SSD_Single(0x29,0x55);//x          
++SSD_Single(0x2A,0x55);//x          
++SSD_Single(0x2B,0x55);//x          
++                      
++//GIP_L_GS Pin mapping
++SSD_Single(0x2C,0x13);//RESET_EVEN     
++SSD_Single(0x2D,0x15);//VSSG_EVEN         
++SSD_Single(0x2E,0x15);//VSSG_EVEN       
++SSD_Single(0x2F,0x01);//STV2_ODD        
++SSD_Single(0x30,0x37);//VDD2_ODD        
++SSD_Single(0x31,0x17);//VDD1_ODD        
++SSD_Single(0x32,0x15);//x               
++SSD_Single(0x33,0x0D);//CK11            
++SSD_Single(0x34,0x0F);//CK9             
++SSD_Single(0x35,0x15);//x               
++SSD_Single(0x36,0x05);//CK7             
++SSD_Single(0x37,0x07);//CK5             
++SSD_Single(0x38,0x15);//x               
++SSD_Single(0x39,0x09);//CK3             
++SSD_Single(0x3A,0x0B);//CK1             
++SSD_Single(0x3B,0x11);//STV1_ODD        
++SSD_Single(0x3C,0x15);//x               
++SSD_Single(0x3D,0x15);//x               
++SSD_Single(0x3E,0x15);//x               
++SSD_Single(0x3F,0x15);//x               
++SSD_Single(0x40,0x15);//x               
++SSD_Single(0x41,0x15);//x              
++                                       
++//GIP_R_GS Pin mapping                 
++SSD_Single(0x42,0x12);//RESET__EVEN    
++SSD_Single(0x43,0x15);//VSSG_EVEN         
++SSD_Single(0x44,0x15);//VSSG_EVEN       
++SSD_Single(0x45,0x00);//STV2_EVEN       
++SSD_Single(0x46,0x37);//VDD2_EVEN       
++SSD_Single(0x47,0x17);//VDD1_EVEN       
++SSD_Single(0x48,0x15);//x               
++SSD_Single(0x49,0x0C);//CK12            
++SSD_Single(0x4A,0x0E);//CK10            
++SSD_Single(0x4B,0x15);//x               
++SSD_Single(0x4C,0x04);//CK8             
++SSD_Single(0x4D,0x06);//CK6             
++SSD_Single(0x4E,0x15);//x               
++SSD_Single(0x4F,0x08);//CK4             
++SSD_Single(0x50,0x0A);//CK2              
++SSD_Single(0x51,0x10);//STV1_EVEN       
++SSD_Single(0x52,0x15);//x               
++SSD_Single(0x53,0x15);//x               
++SSD_Single(0x54,0x15);//x               
++SSD_Single(0x55,0x15);//x               
++SSD_Single(0x56,0x15);//x               
++SSD_Single(0x57,0x15);//x               
++
++//GIP Timing  
++SSD_Single(0x58,0x40); 
++SSD_Single(0x5B,0x10); 
++SSD_Single(0x5C,0x06);//STV_S0 
++SSD_Single(0x5D,0x40); 
++SSD_Single(0x5E,0x00); 
++SSD_Single(0x5F,0x00); 
++SSD_Single(0x60,0x40);//ETV_W 
++SSD_Single(0x61,0x03); 
++SSD_Single(0x62,0x04); 
++SSD_Single(0x63,0x6C);//CKV_ON 
++SSD_Single(0x64,0x6C);//CKV_OFF 
++SSD_Single(0x65,0x75); 
++SSD_Single(0x66,0x08);//ETV_S0 
++SSD_Single(0x67,0xB4); //ckv_num/ckv_w
++SSD_Single(0x68,0x08); //CKV_S0
++SSD_Single(0x69,0x6C);//CKV_ON
++SSD_Single(0x6A,0x6C);//CKV_OFF 
++SSD_Single(0x6B,0x0C); //dummy
++SSD_Single(0x6D,0x00);//GGND1 
++SSD_Single(0x6E,0x00);//GGND2 
++SSD_Single(0x6F,0x88); 
++ 
++SSD_Single(0x75,0xBB);//FLM_EN 
++SSD_Single(0x76,0x00); 
++SSD_Single(0x77,0x05); 
++SSD_Single(0x78,0x2A);//FLM_OFF 
++
++
++
++//Page4
++SSD_Single(0xE0,0x04);
++SSD_Single(0x09,0x11);
++SSD_Single(0x0E,0x48);	//Source EQ option
++SSD_Single(0x2B,0x2B);
++SSD_Single(0x2D,0x03);//defult 0x01
++SSD_Single(0x2E,0x44);
++
++//Page5
++SSD_Single(0xE0,0x05);
++SSD_Single(0x12,0x72);//VCI GAS detect voltage
++
++//Page0
++SSD_Single(0xE0,0x00);
++SSD_Single(0xE6,0x02);//WD_Timer
++SSD_Single(0xE7,0x0C);//WD_Timer
++
++//SLP OUT
++SSD_Number(0x01);    ///ºÍƽ̨Ïà¹Ø£¬²»ÊDzÎÊý¡£
++SSD_CMD(0x11);  	// SLPOUT
++Delayms(120);
++
++
++//DISP ON
++SSD_Number(0x01);      ///Õâ¸öºÍƽ̨Ïà¹Ø£¬²»ÊDzÎÊý
++SSD_CMD(0x29);  	// DSPON
++Delayms(5);
++
++
++
++
++
++
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/jd9365/panel-jd9365.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/jd9365/panel-jd9365.c
+new file mode 100644
+index 000000000..a83cff2cb
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/jd9365/panel-jd9365.c
+@@ -0,0 +1,692 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-jd9365d.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++#include <linux/fb.h>
++#include <linux/backlight.h>
++
++
++#include "../../ingenicfb.h"
++#include "../../jz_dsim.h"
++
++static int test = 0;
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio lcd_te;
++	struct board_gpio lcd_pwm;
++	struct board_gpio bl_en;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++};
++
++struct panel_dev *panel;
++
++#define lcd_to_master(a)	(a->dsim_dev->master)
++#define lcd_to_master_ops(a)	((lcd_to_master(a))->master_ops)
++
++struct jd9365d {
++	struct device *dev;
++	unsigned int power;
++	unsigned int id;
++
++	struct lcd_device *ld;
++	struct backlight_device *bd;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++
++};
++
++static struct dsi_cmd_packet fitipower_jd9365d_800_1280_cmd_list1[] =
++{
++	//Page0
++		{0x15, 0xE0, 0x00},
++	//--- PASSWORD  ----//
++		{0x15, 0xE1, 0x93},
++		{0x15, 0xE2, 0x65},
++		{0x15, 0xE3, 0xF8},
++//		{0x15, 0x80, 0x03},//4 lane
++		{0x15, 0x80, 0x01},//2 lane
++       //--- Page1  ----//
++		{0x15, 0xE0, 0x01},
++       //Set VCOM
++		{0x15, 0x01, 0x67},
++
++//Set Gamma Power, VGMP,VGMN,VGSP,VGSN
++
++		{0x15, 0x17, 0x00},
++		{0x15, 0x18, 0xBF},//4.5V, D7=4.8V
++		{0x15, 0x19, 0x01},//0.0v
++		{0x15, 0x1A, 0x00},
++		{0x15, 0x1B, 0xBF},
++		{0x15, 0x1C, 0x01},
++		{0x15, 0x0C, 0x74},
++//Set Gate Power
++		{0x15, 0x1F, 0x70},//VGH_REG=16.2V
++		{0x15, 0x20, 0x2D},//VGL_REG=-12V
++		{0x15, 0x21, 0x2D},//VGL_REG2=-12V
++		{0x15, 0x22, 0x7E},
++		{0x15, 0x0C, 0x74},
++
++		{0x15, 0x35, 0x28},//SAP
++
++		{0x15, 0x37, 0x19},//SS=1,BGR=1
++//SET RGBCYC
++
++		{0x15, 0x38, 0x05},//JDT=101 zigzag inversion
++		{0x15, 0x39, 0x00},
++		{0x15, 0x3A, 0x01},
++		{0x15, 0x3C, 0x7C},//SET EQ3 for TE_H
++		{0x15, 0x3D, 0xFF},//SET CHGEN_ON, modify 20140806
++		{0x15, 0x3E, 0xFF},//SET CHGEN_OFF, modify 20140806
++		{0x15, 0x3F, 0x7F},//SET CHGEN_OFF2, modify 20140806
++//Set TCON
++		{0x15, 0x40, 0x06},//RSO=
++		{0x15, 0x41, 0xA0},//LN=640->1280 line
++		{0x15, 0x43, 0x1E},//VFP=30
++		{0x15, 0x44, 0x0B},//VBP=12
++		{0x15, 0x45, 0x28},//HBP=40
++//--- power voltage  ----//
++		{0x15, 0x55, 0x01},
++		{0x15, 0x57, 0xA9},
++		{0x15, 0x59, 0x0A},//VCL = -2.5V
++		{0x15, 0x5A, 0x2E},//VGH = 16.2V
++		{0x15, 0x5B, 0x1A},//VGL = -12V
++		{0x15, 0x5C, 0x15},//pump clk
++//--- Gamma  ----//
++		{0x15, 0x5D, 0x7F},
++		{0x15, 0x5E, 0x64},
++		{0x15, 0x5F, 0x53},
++		{0x15, 0x60, 0x47},
++		{0x15, 0x61, 0x43},
++		{0x15, 0x62, 0x33},
++		{0x15, 0x63, 0x37},
++		{0x15, 0x64, 0x21},
++		{0x15, 0x65, 0x39},
++		{0x15, 0x66, 0x37},
++		{0x15, 0x67, 0x34},
++		{0x15, 0x68, 0x50},
++		{0x15, 0x69, 0x3D},
++		{0x15, 0x6A, 0x44},
++		{0x15, 0x6B, 0x36},
++		{0x15, 0x6C, 0x34},
++		{0x15, 0x6D, 0x25},
++		{0x15, 0x6E, 0x15},
++		{0x15, 0x6F, 0x02},
++		{0x15, 0x70, 0x7F},
++		{0x15, 0x71, 0x64},
++		{0x15, 0x72, 0x53},
++		{0x15, 0x73, 0x47},
++		{0x15, 0x74, 0x43},
++		{0x15, 0x75, 0x33},
++		{0x15, 0x76, 0x37},
++		{0x15, 0x77, 0x21},
++		{0x15, 0x78, 0x39},
++		{0x15, 0x79, 0x37},
++		{0x15, 0x7A, 0x34},
++		{0x15, 0x7B, 0x50},
++		{0x15, 0x7C, 0x3D},
++		{0x15, 0x7D, 0x44},
++		{0x15, 0x7E, 0x36},
++		{0x15, 0x7F, 0x34},
++		{0x15, 0x80, 0x25},
++		{0x15, 0x81, 0x15},
++		{0x15, 0x82, 0x02},
++//Page2, for GIP
++		{0x15, 0xE0, 0x02},
++//GIP_L Pin mapping
++		{0x15, 0x00, 0x52},//RESET_EVEN
++		{0x15, 0x01, 0x55},//VSSG_EVEN
++		{0x15, 0x02, 0x55},//VSSG_EVEN
++		{0x15, 0x03, 0x50},//STV2_ODD
++		{0x15, 0x04, 0x77},//VDD2_ODD
++		{0x15, 0x05, 0x57},//VDD1_ODD
++		{0x15, 0x06, 0x55},//x
++		{0x15, 0x07, 0x4E},//CK11
++		{0x15, 0x08, 0x4C},//CK9
++		{0x15, 0x09, 0x5F},//x
++		{0x15, 0x0A, 0x4A},//CK7
++		{0x15, 0x0B, 0x48},//CK5
++		{0x15, 0x0C, 0x55},//x
++		{0x15, 0x0D, 0x46},//CK3
++		{0x15, 0x0E, 0x44},//CK1
++		{0x15, 0x0F, 0x40},//STV1_ODD
++		{0x15, 0x10, 0x55},//x
++		{0x15, 0x11, 0x55},//x
++		{0x15, 0x12, 0x55},//x
++		{0x15, 0x13, 0x55},//x
++		{0x15, 0x14, 0x55},//x
++		{0x15, 0x15, 0x55},//x
++//GIP_R Pin mapping
++		{0x15, 0x16, 0x53},//RESET__EVEN
++		{0x15, 0x17, 0x55},//VSSG_EVEN
++		{0x15, 0x18, 0x55},//VSSG_EVEN
++		{0x15, 0x19, 0x51},//STV2_EVEN
++		{0x15, 0x1A, 0x77},//VDD2_EVEN
++		{0x15, 0x1B, 0x57},//VDD1_EVEN
++		{0x15, 0x1C, 0x55},//x
++		{0x15, 0x1D, 0x4F},//CK12
++		{0x15, 0x1E, 0x4D},//CK10
++		{0x15, 0x1F, 0x5F},//x
++		{0x15, 0x20, 0x4B},//CK8
++		{0x15, 0x21, 0x49},//CK6
++		{0x15, 0x22, 0x55},//x
++		{0x15, 0x23, 0x47},//CK4
++		{0x15, 0x24, 0x45},//CK2
++		{0x15, 0x25, 0x41},//STV1_EVEN
++		{0x15, 0x26, 0x55},//x
++		{0x15, 0x27, 0x55},//x
++		{0x15, 0x28, 0x55},//x
++		{0x15, 0x29, 0x55},//x
++		{0x15, 0x2A, 0x55},//x
++		{0x15, 0x2B, 0x55},//x
++//GIP_L_GS Pin mapping
++		{0x15, 0x2C, 0x13},//RESET_EVEN
++		{0x15, 0x2D, 0x15},//VSSG_EVEN
++		{0x15, 0x2E, 0x15},//VSSG_EVEN
++		{0x15, 0x2F, 0x01},//STV2_ODD
++		{0x15, 0x30, 0x37},//VDD2_ODD
++		{0x15, 0x31, 0x17},//VDD1_ODD
++		{0x15, 0x32, 0x15},//x
++		{0x15, 0x33, 0x0D},//CK11
++		{0x15, 0x34, 0x0F},//CK9
++		{0x15, 0x35, 0x15},//x
++		{0x15, 0x36, 0x05},//CK7
++		{0x15, 0x37, 0x07},//CK5
++		{0x15, 0x38, 0x15},//x
++		{0x15, 0x39, 0x09},//CK3
++		{0x15, 0x3A, 0x0B},//CK1
++		{0x15, 0x3B, 0x11},//STV1_ODD
++		{0x15, 0x3C, 0x15},//x
++		{0x15, 0x3D, 0x15},//x
++		{0x15, 0x3E, 0x15},//x
++		{0x15, 0x3F, 0x15},//x
++		{0x15, 0x40, 0x15},//x
++		{0x15, 0x41, 0x15},//x
++//GIP_R_GS Pin mapping
++		{0x15, 0x42, 0x12},//RESET__EVEN
++		{0x15, 0x43, 0x15},//VSSG_EVEN
++		{0x15, 0x44, 0x15},//VSSG_EVEN
++		{0x15, 0x45, 0x00},//STV2_EVEN
++		{0x15, 0x46, 0x37},//VDD2_EVEN
++		{0x15, 0x47, 0x17},//VDD1_EVEN
++		{0x15, 0x48, 0x15},//x
++		{0x15, 0x49, 0x0C},//CK12
++		{0x15, 0x4A, 0x0E},//CK10
++		{0x15, 0x4B, 0x15},//x
++		{0x15, 0x4C, 0x04},//CK8
++		{0x15, 0x4D, 0x06},//CK6
++		{0x15, 0x4E, 0x15},//x
++		{0x15, 0x4F, 0x08},//CK4
++		{0x15, 0x50, 0x0A},//CK2
++		{0x15, 0x51, 0x10},//STV1_EVEN
++		{0x15, 0x52, 0x15},//x
++		{0x15, 0x53, 0x15},//x
++		{0x15, 0x54, 0x15},//x
++		{0x15, 0x55, 0x15},//x
++		{0x15, 0x56, 0x15},//x
++		{0x15, 0x57, 0x15},//x
++//GIP Timing
++		{0x15, 0x58, 0x40},
++		{0x15, 0x5B, 0x10},
++		{0x15, 0x5C, 0x06},//STV_S0
++		{0x15, 0x5D, 0x40},
++		{0x15, 0x5E, 0x00},
++		{0x15, 0x5F, 0x00},
++		{0x15, 0x60, 0x40},//ETV_W
++		{0x15, 0x61, 0x03},
++		{0x15, 0x62, 0x04},
++		{0x15, 0x63, 0x6C},//CKV_ON
++		{0x15, 0x64, 0x6C},//CKV_OFF
++		{0x15, 0x65, 0x75},
++		{0x15, 0x66, 0x08},//ETV_S0
++		{0x15, 0x67, 0xB4},//ckv_num/ckv_w
++		{0x15, 0x68, 0x08}, //CKV_S0
++		{0x15, 0x69, 0x6C},//CKV_ON
++		{0x15, 0x6A, 0x6C},//CKV_OFF
++		{0x15, 0x6B, 0x0C},//dummy
++		{0x15, 0x6D, 0x00},//GGND1
++		{0x15, 0x6E, 0x00},//GGND2
++		{0x15, 0x6F, 0x88},
++
++		{0x15, 0x75, 0xBB},//FLM_EN
++		{0x15, 0x76, 0x00},
++		{0x15, 0x77, 0x05},
++		{0x15, 0x78, 0x2A},//FLM_OFF
++//Page4
++		{0x15, 0xE0, 0x04},
++		{0x15, 0x09, 0x11},
++		{0x15, 0x0E, 0x48},//Source EQ option
++		{0x15, 0x2B, 0x2B},
++		{0x15, 0x2D, 0x03},//defult 0x01
++		{0x15, 0X2E, 0x44},
++//Page5
++		{0x15, 0XE0, 0x05},
++		{0x15, 0X12, 0x72},//VCI GAS detect voltage
++
++//Page0
++		{0x15, 0xE0, 0x00},
++		{0x15, 0xE6, 0x02},//WD_Timer
++		{0x15, 0xE7, 0x0C},//WD_Timer
++};
++
++
++static void panel_dev_sleep_in(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x10, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_sleep_out(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x11, 0x00};
++//	struct dsi_cmd_packet data_to_send1 = {0x15, 0xc2, 0x20};//color bar test mode.
++//	while (1) {
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++//	ops->cmd_write(lcd_to_master(lcd), data_to_send1);
++//	}
++}
++
++static void panel_dev_display_on(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);//color bar turn off 0x29 command.
++	struct dsi_cmd_packet data_to_send = {0x05, 0x29, 0x00};
++	/* struct dsi_cmd_packet data_to_send1 = {0x15, 0x51, 250}; */
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++	/* ops->cmd_write(lcd_to_master(lcd), data_to_send1); */
++}
++
++static void panel_dev_display_off(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x28, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++
++static void panel_dev_panel_init(struct panel_dev *lcd)
++{
++	int  i;
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_device *dsi = lcd_to_master(lcd);
++
++	for (i = 0; i < ARRAY_SIZE(fitipower_jd9365d_800_1280_cmd_list1); i++)
++	{
++		ops->cmd_write(dsi,  fitipower_jd9365d_800_1280_cmd_list1[i]);
++	}
++}
++
++static int panel_dev_ioctl(struct mipi_dsim_lcd_device *dsim_dev, int cmd)
++{
++	return 0;
++}
++static void panel_dev_set_sequence(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct jd9365d *lcd = dev_get_drvdata(&dsim_dev->dev);
++
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++	if(test != 0)
++		return;
++	test++;
++
++	panel_dev_panel_init(panel);
++	panel_dev_sleep_out(panel);
++	msleep(120);
++	panel_dev_display_on(panel);
++	msleep(5);
++	/* dump_dsi_reg(dsi); */
++	lcd->power = FB_BLANK_UNBLANK;
++}
++static void panel_dev_power_on(struct mipi_dsim_lcd_device *dsim_dev, int power)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++	struct board_gpio *bl_en = &panel->bl_en;
++	struct board_gpio *lcd_te = &panel->lcd_te;
++
++	if(test != 0)
++		return;
++
++//	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++	gpio_direction_output(bl_en->gpio, bl_en->active_level);
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d : bl_en-gpio = %d,bl_en active_level =%d\n",__func__,__LINE__,bl_en->gpio,bl_en->active_level);
++
++	if (gpio_is_valid(lcd_te->gpio)) {
++		gpio_direction_input(lcd_te->gpio);
++	}
++	msleep(50);
++	gpio_direction_output(rst->gpio, 0);
++	msleep(10);
++	gpio_direction_output(rst->gpio, 1);
++	msleep(120);
++
++	panel->power = power;
++}
++
++static struct fb_videomode panel_modes = {
++	.name = "fitipower_jd9365d-lcd",
++	.xres = 800,
++	.yres = 1280,
++
++//	.refresh = 10,
++	.refresh = 60,
++
++	.left_margin = 20,//hbp
++	.right_margin = 20,//hfp
++	.hsync_len = 20, //hsync
++
++	.upper_margin = 8,//vbp
++	.lower_margin = 30,//vfp
++	.vsync_len = 4, //vsync
++
++	.sync                   = FB_SYNC_HOR_HIGH_ACT & FB_SYNC_VERT_HIGH_ACT,
++	.vmode                  = FB_VMODE_NONINTERLACED,
++	.flag = 0,
++};
++
++struct jzdsi_data jzdsi_pdata = {
++	.modes = &panel_modes,
++	.video_config.no_of_lanes = 2,
++	.video_config.virtual_channel = 0,
++	.video_config.color_coding = COLOR_CODE_24BIT,
++	.video_config.video_mode = VIDEO_BURST_WITH_SYNC_PULSES,
++	.video_config.receive_ack_packets = 0,	/* enable receiving of ack packets */
++	.video_config.is_18_loosely = 0,
++	.video_config.data_en_polarity = 1,
++	.video_config.byte_clock = 0, // driver will auto calculate byte_clock.
++	.video_config.byte_clock_coef = MIPI_PHY_BYTE_CLK_COEF_MUL3_DIV2, // byte_clock *3/2.
++
++	.dsi_config.max_lanes = 2,
++	.dsi_config.max_hs_to_lp_cycles = 100,
++	.dsi_config.max_lp_to_hs_cycles = 40,
++//	.dsi_config.max_hs_to_lp_cycles = 200,
++//	.dsi_config.max_lp_to_hs_cycles = 80,
++	.dsi_config.max_bta_cycles = 4095,
++	.dsi_config.color_mode_polarity = 1,
++	.dsi_config.shut_down_polarity = 1,
++	.dsi_config.max_bps = 2750,
++//	.max_bps = 650,  // 650 Mbps
++	.bpp_info = 24,
++};
++static struct tft_config kd050hdfia019_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++
++struct lcd_panel lcd_panel = {
++	.num_modes = 1,
++	.modes = &panel_modes,
++	.dsi_pdata = &jzdsi_pdata,
++
++	.lcd_type = LCD_TYPE_MIPI_TFT,
++	.tft_config = &kd050hdfia019_cfg,
++	.bpp = 24,
++//	.width = 68,
++//	.height = 121,
++	.width = 135,
++	.height = 216,
++	.dither_enable = 0,
++	.dither.dither_red = 0,
++	.dither.dither_green = 0,
++	.dither.dither_blue = 0,
++
++
++};
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++* @ pannel_jd9365d_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++	panel->bl_en.gpio = of_get_named_gpio_flags(np, "ingenic,bl-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->bl_en.gpio)) {
++		panel->bl_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->bl_en.gpio, GPIOF_DIR_OUT, "bl_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request bl_en pin!\n");
++//			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio bl_en.gpio: %d\n", panel->bl_en.gpio);
++	}
++
++//
++//	panel->lcd_pwm.gpio = of_get_named_gpio_flags(np, "ingenic,lcd-pwm-gpio", 0, &flags);
++//	if(gpio_is_valid(panel->lcd_pwm.gpio)) {
++//		panel->lcd_pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++//		ret = gpio_request_one(panel->lcd_pwm.gpio, GPIOF_DIR_OUT, "lcd-pwm");
++//		ret = gpio_direction_output(panel->lcd_pwm.gpio,1);
++//		if(ret < 0) {
++//			dev_err(dev, "Failed to request lcd-pwm pin!\n");
++//			return ret;
++//		}
++//	} else {
++//		dev_warn(dev, "invalid gpio lcd-pwm.gpio: %d\n", panel->lcd_pwm.gpio);
++//	}
++
++
++	return 0;
++err_request_lcd_te:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++err_request_rst:
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++	return ret;
++}
++
++static int panel_dev_probe(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct jd9365d *lcd;
++	lcd = devm_kzalloc(&dsim_dev->dev, sizeof(struct jd9365d), GFP_KERNEL);
++	if (!lcd)
++	{
++		dev_err(&dsim_dev->dev, "failed to allocate fitipower_jd9365d structure.\n");
++		return -ENOMEM;
++	}
++
++	lcd->dsim_dev = dsim_dev;
++	lcd->dev = &dsim_dev->dev;
++
++	lcd->ld = lcd_device_register("fitipower_jd9365d", lcd->dev, lcd,
++	                              &panel_lcd_ops);
++	if (IS_ERR(lcd->ld))
++	{
++		dev_err(lcd->dev, "failed to register lcd ops.\n");
++		return PTR_ERR(lcd->ld);
++	}
++
++	dev_set_drvdata(&dsim_dev->dev, lcd);
++
++
++	dev_dbg(lcd->dev, "probed fitipower_jd9365d panel driver.\n");
++
++
++	panel->dsim_dev = dsim_dev;
++
++
++	return 0;
++
++}
++
++static int panel_suspend(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++	panel_dev_display_off(panel);
++	panel_dev_sleep_in(panel);
++	gpio_direction_output(vdd_en->gpio, !vdd_en->active_level);
++
++	return 0;
++}
++
++static int panel_resume(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	return 0;
++}
++
++static struct mipi_dsim_lcd_driver panel_dev_dsim_ddi_driver = {
++	.name = "fitipower_jd9365d-lcd",
++	.id = -1,
++
++	.power_on = panel_dev_power_on,
++	.set_sequence = panel_dev_set_sequence,
++	.probe = panel_dev_probe,
++//	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++
++
++struct mipi_dsim_lcd_device panel_dev_device={
++	.name		= "fitipower_jd9365d-lcd",
++	.id = 0,
++};
++
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	mipi_dsi_register_lcd_device(&panel_dev_device);
++	mipi_dsi_register_lcd_driver(&panel_dev_dsim_ddi_driver);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_of_parse;
++	}
++
++	return 0;
++
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,jd9365d", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "jd9365d",
++		.of_match_table = panel_of_match,
++	},
++};
++
++module_platform_driver(panel_driver);
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/jd9365d/C_JD9365D_800x1280_FP7721BX2_Column_G2.2_190613_Nolan.txt b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/jd9365d/C_JD9365D_800x1280_FP7721BX2_Column_G2.2_190613_Nolan.txt
+new file mode 100644
+index 000000000..11f79c8c1
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/jd9365d/C_JD9365D_800x1280_FP7721BX2_Column_G2.2_190613_Nolan.txt
+@@ -0,0 +1,245 @@
++params->dsi.vertical_sync_active=4
++params->dsi.vertical_backporch=8
++params->dsi.vertical_frontporch=30
++params->dsi.horizontal_sync_active=20
++params->dsi.horizontal_backporch=20
++params->dsi.horizontal_frontporch=20
++params->dsi.PLL_CLOCK=205MHZ£¨410Mbps£©
++ 
++LCD_nReset=1;
++Delayms(5);
++LCD_nReset=0;
++Delayms(10);
++LCD_nReset=1;
++Delayms(120);
++ 
++{0xE0,1,{0x00}},
++
++{0xE1,1,{0x93}},
++{0xE2,1,{0x65}},
++{0xE3,1,{0xF8}},
++{0x80,1,{0x03}},
++
++{0xE0,1,{0x01}},
++
++{0x00,1,{0x00}},
++{0x01,1,{0x3C}},
++{0x03,1,{0x00}},
++{0x04,1,{0x3C}},
++
++{0x17,1,{0x00}},
++{0x18,1,{0xF7}},
++{0x19,1,{0x01}},
++{0x1A,1,{0x00}},
++{0x1B,1,{0xF7}},
++{0x1C,1,{0x01}},
++
++{0x24,1,{0xF1}},
++
++{0x35,1,{0x23}},
++
++{0x37,1,{0x09}},
++
++{0x38,1,{0x04}},
++{0x39,1,{0x00}},
++{0x3A,1,{0x01}},
++{0x3C,1,{0x70}},
++{0x3D,1,{0xFF}},
++{0x3E,1,{0xFF}},
++{0x3F,1,{0x7F}},
++
++{0x40,1,{0x06}},
++{0x41,1,{0xA0}},
++{0x43,1,{0x1E}},
++{0x44,1,{0x0B}},
++{0x45,1,{0x28}},
++{0x0C,1,{0x74}},
++
++{0x55,1,{0x01}},
++{0x57,1,{0x69}},
++{0x59,1,{0x0A}},
++{0x5A,1,{0x2D}},
++{0x5B,1,{0x1A}},
++{0x5C,1,{0x15}},
++
++{0x5D,1,{0x7F}},
++{0x5E,1,{0x69}},
++{0x5F,1,{0x59}},
++{0x60,1,{0x4C}},
++{0x61,1,{0x47}},
++{0x62,1,{0x38}},
++{0x63,1,{0x3D}},
++{0x64,1,{0x27}},
++{0x65,1,{0x41}},
++{0x66,1,{0x40}},
++{0x67,1,{0x40}},
++{0x68,1,{0x5B}},
++{0x69,1,{0x46}},
++{0x6A,1,{0x49}},
++{0x6B,1,{0x3A}},
++{0x6C,1,{0x34}},
++{0x6D,1,{0x25}},
++{0x6E,1,{0x15}},
++{0x6F,1,{0x02}},
++{0x70,1,{0x7F}},
++{0x71,1,{0x69}},
++{0x72,1,{0x59}},
++{0x73,1,{0x4C}},
++{0x74,1,{0x47}},
++{0x75,1,{0x38}},
++{0x76,1,{0x3D}},
++{0x77,1,{0x27}},
++{0x78,1,{0x41}},
++{0x79,1,{0x40}},
++{0x7A,1,{0x40}},
++{0x7B,1,{0x5B}},
++{0x7C,1,{0x46}},
++{0x7D,1,{0x49}},
++{0x7E,1,{0x3A}},
++{0x7F,1,{0x34}},
++{0x80,1,{0x25}},
++{0x81,1,{0x15}},
++{0x82,1,{0x02}},
++
++{0xE0,1,{0x02}},
++
++{0x00,1,{0x50}},
++{0x01,1,{0x55}},
++{0x02,1,{0x55}},
++{0x03,1,{0x52}},
++{0x04,1,{0x77}},
++{0x05,1,{0x57}},
++{0x06,1,{0x55}},
++{0x07,1,{0x4E}},
++{0x08,1,{0x4C}},
++{0x09,1,{0x55}},
++{0x0A,1,{0x4A}},
++{0x0B,1,{0x48}},
++{0x0C,1,{0x55}},
++{0x0D,1,{0x46}},
++{0x0E,1,{0x44}},
++{0x0F,1,{0x40}},
++{0x10,1,{0x55}},
++{0x11,1,{0x55}},
++{0x12,1,{0x55}},
++{0x13,1,{0x55}},
++{0x14,1,{0x55}},
++{0x15,1,{0x55}},
++
++{0x16,1,{0x51}},
++{0x17,1,{0x55}},
++{0x18,1,{0x55}},
++{0x19,1,{0x53}},
++{0x1A,1,{0x77}},
++{0x1B,1,{0x57}},
++{0x1C,1,{0x55}},
++{0x1D,1,{0x4F}},
++{0x1E,1,{0x4D}},
++{0x1F,1,{0x55}},
++{0x20,1,{0x4B}},
++{0x21,1,{0x49}},
++{0x22,1,{0x55}},
++{0x23,1,{0x47}},
++{0x24,1,{0x45}},
++{0x25,1,{0x41}},
++{0x26,1,{0x55}},
++{0x27,1,{0x55}},
++{0x28,1,{0x55}},
++{0x29,1,{0x55}},
++{0x2A,1,{0x55}},
++{0x2B,1,{0x55}},
++
++{0x2C,1,{0x01}},
++{0x2D,1,{0x15}},
++{0x2E,1,{0x15}},
++{0x2F,1,{0x13}},
++{0x30,1,{0x17}},
++{0x31,1,{0x17}},
++{0x32,1,{0x15}},
++{0x33,1,{0x0D}},
++{0x34,1,{0x0F}},
++{0x35,1,{0x15}},
++{0x36,1,{0x05}},
++{0x37,1,{0x07}},
++{0x38,1,{0x15}},
++{0x39,1,{0x09}},
++{0x3A,1,{0x0B}},
++{0x3B,1,{0x11}},
++{0x3C,1,{0x15}},
++{0x3D,1,{0x15}},
++{0x3E,1,{0x15}},
++{0x3F,1,{0x15}},
++{0x40,1,{0x15}},
++{0x41,1,{0x15}},
++
++{0x42,1,{0x00}},
++{0x43,1,{0x15}},
++{0x44,1,{0x15}},
++{0x45,1,{0x12}},
++{0x46,1,{0x17}},
++{0x47,1,{0x17}},
++{0x48,1,{0x15}},
++{0x49,1,{0x0C}},
++{0x4A,1,{0x0E}},
++{0x4B,1,{0x15}},
++{0x4C,1,{0x04}},
++{0x4D,1,{0x06}},
++{0x4E,1,{0x15}},
++{0x4F,1,{0x08}},
++{0x50,1,{0x0A}},
++{0x51,1,{0x10}},
++{0x52,1,{0x15}},
++{0x53,1,{0x15}},
++{0x54,1,{0x15}},
++{0x55,1,{0x15}},
++{0x56,1,{0x15}},
++{0x57,1,{0x15}},
++
++{0x58,1,{0x40}},
++{0x5B,1,{0x10}},
++{0x5C,1,{0x06}},
++{0x5D,1,{0x40}},
++{0x5E,1,{0x00}},
++{0x5F,1,{0x00}},
++{0x60,1,{0x40}},
++{0x61,1,{0x03}},
++{0x62,1,{0x04}},
++{0x63,1,{0x6C}},
++{0x64,1,{0x6C}},
++{0x65,1,{0x75}},
++{0x66,1,{0x08}},
++{0x67,1,{0xB4}},
++{0x68,1,{0x08}},
++{0x69,1,{0x6C}},
++{0x6A,1,{0x6C}},
++{0x6B,1,{0x0C}},
++{0x6D,1,{0x00}},
++{0x6E,1,{0x00}},
++{0x6F,1,{0x88}},
++{0x75,1,{0xBB}},
++{0x76,1,{0x00}},
++{0x77,1,{0x05}},
++{0x78,1,{0x2A}},
++
++{0xE0,1,{0x04}},
++{0x09,1,{0x11}},
++{0x0E,1,{0x48}},
++{0x2B,1,{0x08}},
++{0X2E,1,{0x03}},
++
++
++{0xE0,1,{0x00}},
++
++{0x11,1,{0x00}},
++{REGFLAG_DELAY,120,{}},
++
++{0x29,1,{0x00}},
++{REGFLAG_DELAY,5,{}},
++
++//{0x35,1,{0x00}},
++
++//{0xE0,1,{0x00}},
++
++
++
++{REGFLAG_END_OF_TABLE,0x00,{}}
+\ No newline at end of file
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/jd9365d/panel-jd9365d.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/jd9365d/panel-jd9365d.c
+new file mode 100644
+index 000000000..e7ad0236e
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/jd9365d/panel-jd9365d.c
+@@ -0,0 +1,725 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-jd9365d.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++#include <linux/fb.h>
++#include <linux/backlight.h>
++
++
++#include "../../ingenicfb.h"
++#include "../../jz_dsim.h"
++
++static int test = 0;
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio vdd_1v8_en;
++	struct board_gpio vdd_3v3_en;
++	struct board_gpio rst;
++	struct board_gpio lcd_te;
++	struct board_gpio lcd_pwm;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++};
++
++struct panel_dev *panel;
++
++#define lcd_to_master(a)	(a->dsim_dev->master)
++#define lcd_to_master_ops(a)	((lcd_to_master(a))->master_ops)
++
++struct jd9365d {
++	struct device *dev;
++	unsigned int power;
++	unsigned int id;
++
++	struct lcd_device *ld;
++	struct backlight_device *bd;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++
++};
++
++static struct dsi_cmd_packet fitipower_jd9365d_800_1280_cmd_list1[] =
++{
++		{0x15, 0xE0, 0x00},
++
++		{0x15, 0xE1, 0x93},
++		{0x15, 0xE2, 0x65},
++		{0x15, 0xE3, 0xF8},
++//		{0x15, 0x80, 0x03},
++		{0x15, 0x80, 0x01},//2 lane
++
++		{0x15, 0xE0, 0x01},
++
++		{0x15, 0x00, 0x00},
++		{0x15, 0x01, 0x3C},
++		{0x15, 0x03, 0x00},
++		{0x15, 0x04, 0x3C},
++
++		{0x15, 0x17, 0x00},
++		{0x15, 0x18, 0xF7},
++		{0x15, 0x19, 0x01},
++		{0x15, 0x1A, 0x00},
++		{0x15, 0x1B, 0xF7},
++		{0x15, 0x1C, 0x01},
++
++		{0x15, 0x24, 0xF1},
++
++		{0x15, 0x35, 0x23},
++
++		{0x15, 0x37, 0x09},
++
++		{0x15, 0x38, 0x04},
++		{0x15, 0x39, 0x00},
++		{0x15, 0x3A, 0x01},
++		{0x15, 0x3C, 0x70},
++		{0x15, 0x3D, 0xFF},
++		{0x15, 0x3E, 0xFF},
++		{0x15, 0x3F, 0x7F},
++
++		{0x15, 0x40, 0x06},
++		{0x15, 0x41, 0xA0},
++		{0x15, 0x43, 0x1E},
++		{0x15, 0x44, 0x0B},
++		{0x15, 0x45, 0x28},
++		{0x15, 0x0C, 0x74},
++
++		{0x15, 0x55, 0x01},
++		{0x15, 0x57, 0x69},
++		{0x15, 0x59, 0x0A},
++		{0x15, 0x5A, 0x2D},
++		{0x15, 0x5B, 0x1A},
++		{0x15, 0x5C, 0x15},
++
++		{0x15, 0x5D, 0x7F},
++		{0x15, 0x5E, 0x69},
++		{0x15, 0x5F, 0x59},
++		{0x15, 0x60, 0x4C},
++		{0x15, 0x61, 0x47},
++		{0x15, 0x62, 0x38},
++		{0x15, 0x63, 0x3D},
++		{0x15, 0x64, 0x27},
++		{0x15, 0x65, 0x41},
++		{0x15, 0x66, 0x40},
++		{0x15, 0x67, 0x40},
++		{0x15, 0x68, 0x5B},
++		{0x15, 0x69, 0x46},
++		{0x15, 0x6A, 0x49},
++		{0x15, 0x6B, 0x3A},
++		{0x15, 0x6C, 0x34},
++		{0x15, 0x6D, 0x25},
++		{0x15, 0x6E, 0x15},
++		{0x15, 0x6F, 0x02},
++		{0x15, 0x70, 0x7F},
++		{0x15, 0x71, 0x69},
++		{0x15, 0x72, 0x59},
++		{0x15, 0x73, 0x4C},
++		{0x15, 0x74, 0x47},
++		{0x15, 0x75, 0x38},
++		{0x15, 0x76, 0x3D},
++		{0x15, 0x77, 0x27},
++		{0x15, 0x78, 0x41},
++		{0x15, 0x79, 0x40},
++		{0x15, 0x7A, 0x40},
++		{0x15, 0x7B, 0x5B},
++		{0x15, 0x7C, 0x46},
++		{0x15, 0x7D, 0x49},
++		{0x15, 0x7E, 0x3A},
++		{0x15, 0x7F, 0x34},
++		{0x15, 0x80, 0x25},
++		{0x15, 0x81, 0x15},
++		{0x15, 0x82, 0x02},
++
++		{0x15, 0xE0, 0x02},
++
++		{0x15, 0x00, 0x50},
++		{0x15, 0x01, 0x55},
++		{0x15, 0x02, 0x55},
++		{0x15, 0x03, 0x52},
++		{0x15, 0x04, 0x77},
++		{0x15, 0x05, 0x57},
++		{0x15, 0x06, 0x55},
++		{0x15, 0x07, 0x4E},
++		{0x15, 0x08, 0x4C},
++		{0x15, 0x09, 0x55},
++		{0x15, 0x0A, 0x4A},
++		{0x15, 0x0B, 0x48},
++		{0x15, 0x0C, 0x55},
++		{0x15, 0x0D, 0x46},
++		{0x15, 0x0E, 0x44},
++		{0x15, 0x0F, 0x40},
++		{0x15, 0x10, 0x55},
++		{0x15, 0x11, 0x55},
++		{0x15, 0x12, 0x55},
++		{0x15, 0x13, 0x55},
++		{0x15, 0x14, 0x55},
++		{0x15, 0x15, 0x55},
++
++		{0x15, 0x16, 0x51},
++		{0x15, 0x17, 0x55},
++		{0x15, 0x18, 0x55},
++		{0x15, 0x19, 0x53},
++		{0x15, 0x1A, 0x77},
++		{0x15, 0x1B, 0x57},
++		{0x15, 0x1C, 0x55},
++		{0x15, 0x1D, 0x4F},
++		{0x15, 0x1E, 0x4D},
++		{0x15, 0x1F, 0x55},
++		{0x15, 0x20, 0x4B},
++		{0x15, 0x21, 0x49},
++		{0x15, 0x22, 0x55},
++		{0x15, 0x23, 0x47},
++		{0x15, 0x24, 0x45},
++		{0x15, 0x25, 0x41},
++		{0x15, 0x26, 0x55},
++		{0x15, 0x27, 0x55},
++		{0x15, 0x28, 0x55},
++		{0x15, 0x29, 0x55},
++		{0x15, 0x2A, 0x55},
++		{0x15, 0x2B, 0x55},
++
++		{0x15, 0x2C, 0x01},
++		{0x15, 0x2D, 0x15},
++		{0x15, 0x2E, 0x15},
++		{0x15, 0x2F, 0x13},
++		{0x15, 0x30, 0x17},
++		{0x15, 0x31, 0x17},
++		{0x15, 0x32, 0x15},
++		{0x15, 0x33, 0x0D},
++		{0x15, 0x34, 0x0F},
++		{0x15, 0x35, 0x15},
++		{0x15, 0x36, 0x05},
++		{0x15, 0x37, 0x07},
++		{0x15, 0x38, 0x15},
++		{0x15, 0x39, 0x09},
++		{0x15, 0x3A, 0x0B},
++		{0x15, 0x3B, 0x11},
++		{0x15, 0x3C, 0x15},
++		{0x15, 0x3D, 0x15},
++		{0x15, 0x3E, 0x15},
++		{0x15, 0x3F, 0x15},
++		{0x15, 0x40, 0x15},
++		{0x15, 0x41, 0x15},
++
++		{0x15, 0x42, 0x00},
++		{0x15, 0x43, 0x15},
++		{0x15, 0x44, 0x15},
++		{0x15, 0x45, 0x12},
++		{0x15, 0x46, 0x17},
++		{0x15, 0x47, 0x17},
++		{0x15, 0x48, 0x15},
++		{0x15, 0x49, 0x0C},
++		{0x15, 0x4A, 0x0E},
++		{0x15, 0x4B, 0x15},
++		{0x15, 0x4C, 0x04},
++		{0x15, 0x4D, 0x06},
++		{0x15, 0x4E, 0x15},
++		{0x15, 0x4F, 0x08},
++		{0x15, 0x50, 0x0A},
++		{0x15, 0x51, 0x10},
++		{0x15, 0x52, 0x15},
++		{0x15, 0x53, 0x15},
++		{0x15, 0x54, 0x15},
++		{0x15, 0x55, 0x15},
++		{0x15, 0x56, 0x15},
++		{0x15, 0x57, 0x15},
++
++		{0x15, 0x58, 0x40},
++		{0x15, 0x5B, 0x10},
++		{0x15, 0x5C, 0x06},
++		{0x15, 0x5D, 0x40},
++		{0x15, 0x5E, 0x00},
++		{0x15, 0x5F, 0x00},
++		{0x15, 0x60, 0x40},
++		{0x15, 0x61, 0x03},
++		{0x15, 0x62, 0x04},
++		{0x15, 0x63, 0x6C},
++		{0x15, 0x64, 0x6C},
++		{0x15, 0x65, 0x75},
++		{0x15, 0x66, 0x08},
++		{0x15, 0x67, 0xB4},
++		{0x15, 0x68, 0x08},
++		{0x15, 0x69, 0x6C},
++		{0x15, 0x6A, 0x6C},
++		{0x15, 0x6B, 0x0C},
++		{0x15, 0x6D, 0x00},
++		{0x15, 0x6E, 0x00},
++		{0x15, 0x6F, 0x88},
++		{0x15, 0x75, 0xBB},
++		{0x15, 0x76, 0x00},
++		{0x15, 0x77, 0x05},
++		{0x15, 0x78, 0x2A},
++
++		{0x15, 0xE0, 0x04},
++		{0x15, 0x09, 0x11},
++		{0x15, 0x0E, 0x48},
++		{0x15, 0x2B, 0x08},
++		{0x15, 0X2E, 0x03},
++
++		{0x15, 0xE0, 0x00},
++};
++
++
++static void panel_dev_sleep_in(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x10, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_sleep_out(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x11, 0x00};
++//	struct dsi_cmd_packet data_to_send1 = {0x15, 0xc2, 0x20};//color bar test mode.
++//	while (1) {
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++//	ops->cmd_write(lcd_to_master(lcd), data_to_send1);
++//	}
++}
++
++static void panel_dev_display_on(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);//color bar turn off 0x29 command.
++	struct dsi_cmd_packet data_to_send = {0x05, 0x29, 0x00};
++	/* struct dsi_cmd_packet data_to_send1 = {0x15, 0x51, 250}; */
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++	/* ops->cmd_write(lcd_to_master(lcd), data_to_send1); */
++}
++
++static void panel_dev_display_off(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x28, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++
++static void panel_dev_panel_init(struct panel_dev *lcd)
++{
++	int  i;
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_device *dsi = lcd_to_master(lcd);
++
++	for (i = 0; i < ARRAY_SIZE(fitipower_jd9365d_800_1280_cmd_list1); i++)
++	{
++		ops->cmd_write(dsi,  fitipower_jd9365d_800_1280_cmd_list1[i]);
++	}
++}
++
++static int panel_dev_ioctl(struct mipi_dsim_lcd_device *dsim_dev, int cmd)
++{
++	return 0;
++}
++static void panel_dev_set_sequence(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct jd9365d *lcd = dev_get_drvdata(&dsim_dev->dev);
++
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++	if(test != 0)
++		return;
++	test++;
++
++	panel_dev_panel_init(panel);
++	panel_dev_sleep_out(panel);
++	msleep(120);
++	panel_dev_display_on(panel);
++	msleep(5);
++	/* dump_dsi_reg(dsi); */
++	lcd->power = FB_BLANK_UNBLANK;
++}
++static void panel_dev_power_on(struct mipi_dsim_lcd_device *dsim_dev, int power)
++{
++//	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *vdd_1v8_en = &panel->vdd_1v8_en;
++	struct board_gpio *vdd_3v3_en = &panel->vdd_3v3_en;
++	struct board_gpio *rst = &panel->rst;
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++
++	if(test != 0)
++		return;
++
++	gpio_direction_output(vdd_1v8_en->gpio, vdd_1v8_en->active_level);
++	gpio_direction_output(vdd_3v3_en->gpio, vdd_3v3_en->active_level);
++
++	msleep(50);
++	gpio_direction_output(rst->gpio, 1);
++	msleep(5);
++	gpio_direction_output(rst->gpio, 0);
++	msleep(10);
++	gpio_direction_output(rst->gpio, 1);
++	msleep(120);
++
++	panel->power = power;
++}
++
++static struct fb_videomode panel_modes = {
++	.name = "fitipower_jd9365d-lcd",
++	.xres = 800,
++	.yres = 1280,
++
++//	.refresh = 10,
++	.refresh = 60,
++
++	.left_margin = 20,//hbp
++	.right_margin = 20,//hfp
++	.hsync_len = 20, //hsync
++
++	.upper_margin = 8,//vbp
++	.lower_margin = 30,//vfp
++	.vsync_len = 4, //vsync
++
++	.sync                   = FB_SYNC_HOR_HIGH_ACT & FB_SYNC_VERT_HIGH_ACT,
++	.vmode                  = FB_VMODE_NONINTERLACED,
++	.flag = 0,
++};
++
++struct jzdsi_data jzdsi_pdata = {
++	.modes = &panel_modes,
++	.video_config.no_of_lanes = 2,
++	.video_config.virtual_channel = 0,
++	.video_config.color_coding = COLOR_CODE_24BIT,
++	.video_config.video_mode = VIDEO_BURST_WITH_SYNC_PULSES,
++	.video_config.receive_ack_packets = 0,	/* enable receiving of ack packets */
++	.video_config.is_18_loosely = 0,
++	.video_config.data_en_polarity = 1,
++	.video_config.byte_clock = 0, // driver will auto calculate byte_clock.
++	.video_config.byte_clock_coef = MIPI_PHY_BYTE_CLK_COEF_MUL3_DIV2, // byte_clock *3/2.
++
++	.dsi_config.max_lanes = 2,
++	.dsi_config.max_hs_to_lp_cycles = 100,
++	.dsi_config.max_lp_to_hs_cycles = 40,
++//	.dsi_config.max_hs_to_lp_cycles = 200,
++//	.dsi_config.max_lp_to_hs_cycles = 80,
++	.dsi_config.max_bta_cycles = 4095,
++	.dsi_config.color_mode_polarity = 1,
++	.dsi_config.shut_down_polarity = 1,
++	.dsi_config.max_bps = 2750,
++//	.max_bps = 650,  // 650 Mbps
++	.bpp_info = 24,
++};
++static struct tft_config kd050hdfia019_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++
++struct lcd_panel lcd_panel = {
++	.num_modes = 1,
++	.modes = &panel_modes,
++	.dsi_pdata = &jzdsi_pdata,
++
++	.lcd_type = LCD_TYPE_MIPI_TFT,
++	.tft_config = &kd050hdfia019_cfg,
++	.bpp = 24,
++//	.width = 700,
++//	.height = 1230,
++	.width = 68,
++	.height = 121,
++	.dither_enable = 0,
++	.dither.dither_red = 0,
++	.dither.dither_green = 0,
++	.dither.dither_blue = 0,
++
++
++};
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++* @ pannel_jd9365d_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->vdd_1v8_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-1v8-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_1v8_en.gpio)) {
++		panel->vdd_1v8_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->vdd_1v8_en.gpio, GPIOF_DIR_OUT, "vdd_1v8_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_1v8_en pin!\n");
++			goto err_request_vdd_1v8_en;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_1v8_en.gpio: %d\n", panel->vdd_1v8_en.gpio);
++	}
++
++	panel->vdd_3v3_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-3v3-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_3v3_en.gpio)) {
++		panel->vdd_3v3_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->vdd_3v3_en.gpio, GPIOF_DIR_OUT, "vdd_3v3_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_3v3_en pin!\n");
++			goto err_request_vdd_3v3_en;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_3v3_en.gpio: %d\n", panel->vdd_3v3_en.gpio);
++	}
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++//
++//
++//
++//	panel->lcd_pwm.gpio = of_get_named_gpio_flags(np, "ingenic,lcd-pwm-gpio", 0, &flags);
++//	if(gpio_is_valid(panel->lcd_pwm.gpio)) {
++//		panel->lcd_pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++//		ret = gpio_request_one(panel->lcd_pwm.gpio, GPIOF_DIR_OUT, "lcd-pwm");
++//		ret = gpio_direction_output(panel->lcd_pwm.gpio,1);
++//		if(ret < 0) {
++//			dev_err(dev, "Failed to request lcd-pwm pin!\n");
++//			return ret;
++//		}
++//	} else {
++//		dev_warn(dev, "invalid gpio lcd-pwm.gpio: %d\n", panel->lcd_pwm.gpio);
++//	}
++
++
++	return 0;
++err_request_rst:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++//	return ret;
++err_request_vdd_1v8_en:
++	if(gpio_is_valid(panel->vdd_1v8_en.gpio))
++		gpio_free(panel->vdd_1v8_en.gpio);
++//	return ret;
++err_request_vdd_3v3_en:
++	if(gpio_is_valid(panel->vdd_3v3_en.gpio))
++		gpio_free(panel->vdd_3v3_en.gpio);
++//	return ret;
++}
++
++static int panel_dev_probe(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct jd9365d *lcd;
++	lcd = devm_kzalloc(&dsim_dev->dev, sizeof(struct jd9365d), GFP_KERNEL);
++	if (!lcd)
++	{
++		dev_err(&dsim_dev->dev, "failed to allocate fitipower_jd9365d structure.\n");
++		return -ENOMEM;
++	}
++
++	lcd->dsim_dev = dsim_dev;
++	lcd->dev = &dsim_dev->dev;
++
++	lcd->ld = lcd_device_register("fitipower_jd9365d", lcd->dev, lcd,
++	                              &panel_lcd_ops);
++	if (IS_ERR(lcd->ld))
++	{
++		dev_err(lcd->dev, "failed to register lcd ops.\n");
++		return PTR_ERR(lcd->ld);
++	}
++
++	dev_set_drvdata(&dsim_dev->dev, lcd);
++
++
++	dev_dbg(lcd->dev, "probed fitipower_jd9365d panel driver.\n");
++
++
++	panel->dsim_dev = dsim_dev;
++
++
++	return 0;
++
++}
++
++static int panel_suspend(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	return 0;
++}
++
++static int panel_resume(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int panel_pm_suspend(struct device *dev)
++{
++//	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *vdd_1v8_en = &panel->vdd_1v8_en;
++	struct board_gpio *vdd_3v3_en = &panel->vdd_3v3_en;
++
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++	panel_dev_display_off(panel);
++	panel_dev_sleep_in(panel);
++//	gpio_direction_output(vdd_en->gpio, !vdd_en->active_level);
++	gpio_direction_output(vdd_1v8_en->gpio, !vdd_1v8_en->active_level);
++	gpio_direction_output(vdd_3v3_en->gpio, !vdd_3v3_en->active_level);
++
++	return 0;
++}
++
++static int panel_pm_resume(struct device *dev)
++{
++//	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *vdd_1v8_en = &panel->vdd_1v8_en;
++	struct board_gpio *vdd_3v3_en = &panel->vdd_3v3_en;
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++
++//	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++	gpio_direction_output(vdd_1v8_en->gpio, vdd_1v8_en->active_level);
++	gpio_direction_output(vdd_3v3_en->gpio, vdd_3v3_en->active_level);
++
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_pm_suspend,
++	.resume = panel_pm_resume,
++};
++#endif
++
++static struct mipi_dsim_lcd_driver panel_dev_dsim_ddi_driver = {
++	.name = "fitipower_jd9365d-lcd",
++	.id = -1,
++
++	.power_on = panel_dev_power_on,
++	.set_sequence = panel_dev_set_sequence,
++	.probe = panel_dev_probe,
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++
++
++struct mipi_dsim_lcd_device panel_dev_device={
++	.name		= "fitipower_jd9365d-lcd",
++	.id = 0,
++};
++
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	mipi_dsi_register_lcd_device(&panel_dev_device);
++	mipi_dsi_register_lcd_driver(&panel_dev_dsim_ddi_driver);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_of_parse;
++	}
++
++	return 0;
++
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,jd9365d", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "jd9365d",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/lt9211.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/lt9211.c
+new file mode 100644
+index 000000000..e19503eb0
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/lt9211.c
+@@ -0,0 +1,585 @@
++#include "lt9211.h"
++
++static unsigned char mipi_fmt = 0;
++
++struct video_timing *pVideo_Format;
++
++#define DEBUG
++
++#ifdef DEBUG
++#define debug(info, ...) printk(info, ##__VA_ARGS__)
++#else
++#define debug(info, ...)
++#endif
++
++#define HTOTAL (HFP + HACT + HBP + HS)
++#define VTOTAL (VFP + VACT + VBP + VS)
++
++#define PIXCLK (HTOTAL * VTOTAL * FPS / 1000)
++
++#if 0
++#define FPS    60
++#define HACT   1920
++#define VACT   1080
++
++#define HFP    88
++#define HBP    148
++#define HS     44
++
++#define VFP    4
++#define VBP    36
++#define VS     5
++#endif
++
++//hfp, hs, hbp, hact, htotal, vfp, vs, vbp, vact, vtotal, pixclk
++struct video_timing video_640x480_60Hz     ={ 8, 96,  40, 640,   800, 33,  2,  10, 480,   525,  25000};
++struct video_timing video_720x480_60Hz     ={16, 62,  60, 720,   858,  9,  6,  30, 480,   525,  27000};
++struct video_timing video_1280x720_60Hz    ={110,40, 220,1280,  1650,  5,  5,  20, 720,   750,  74250};
++struct video_timing video_1280x720_30Hz    ={110,40, 220,1280,  1650,  5,  5,  20, 720,   750,  37125};
++struct video_timing video_1366x768_60Hz    ={26, 110,110,1366,  1592,  13, 6,  13, 768,   800,  81000};
++struct video_timing video_1920x720_60Hz    ={148,44, 88, 1920,  2200, 28,  5,  12, 720,   765,  88000};
++struct video_timing video_1920x1080_30Hz   ={88, 44, 148,1920,  2200,  4,  5,  36, 1080, 1125,  74250};
++struct video_timing video_1920x1080_60Hz   ={HFP, HS, HBP, HACT, HTOTAL, VFP, VS, VBP, VACT, VTOTAL, PIXCLK};
++//struct video_timing video_1920x1080_60Hz   ={90, 100, 90, 1920, 2200, 20, 5, 20, 1080, 1125, 148500};//60fps
++//struct video_timing video_1920x1080_60Hz   ={90, 100, 90, 1920, 2200, 20, 5, 20, 1080, 1125, 74250};//30fps
++struct video_timing video_1920x1200_60Hz   ={48, 32,  80,1920,  2080,  3,  6,  26, 1200, 1235, 154000};
++struct video_timing video_3840x2160_30Hz   ={176,88, 296,3840,  4400,  8,  10, 72, 2160, 2250, 297000};
++
++static unsigned int i2c_write(struct i2c_client *client,unsigned char addr,unsigned char value);
++static unsigned char i2c_read(struct i2c_client *client, u8 addr);
++
++#ifdef DEBUG
++static void LT9211_ChipID(struct i2c_client *client)
++{
++	i2c_write(client, 0xff,0x81);//register bank
++	printk("LT9211 Chip ID:%x,",i2c_read(client, 0x00));
++	printk("%02x, ",i2c_read(client, 0x01));
++	printk("%02x\n",i2c_read(client, 0x02));
++}
++#endif
++
++/** video chk soft rst **/
++#if 0
++static void lt9211_vid_chk_rst(struct i2c_client *client)
++{
++	i2c_write(client, 0xff,0x81);
++	i2c_write(client, 0x10,0xbe);
++	mdelay(10);
++	i2c_write(client, 0x10,0xfe);
++}
++#endif
++
++/** lvds rx logic rst **/
++static void lt9211_mipirx_logic_rst(struct i2c_client *client)
++{
++	i2c_write(client, 0xff,0x81);
++	i2c_write(client, 0x0a,0xc0);
++	i2c_write(client, 0x20,0xbf);  //mipi rx div logic reset,for portb input
++	mdelay(10);
++	i2c_write(client, 0x0a,0xc1);
++	i2c_write(client, 0x20,0xff);
++}
++
++static void LT9211_SystemInt(struct i2c_client *client)
++{
++	/* system clock init */
++	i2c_write(client, 0xff,0x82);
++	i2c_write(client, 0x01,0x18);
++
++	i2c_write(client, 0xff,0x86);
++	i2c_write(client, 0x06,0x61);
++	i2c_write(client, 0x07,0xa8); //fm for sys_clk
++
++	i2c_write(client, 0xff,0x87);
++	i2c_write(client, 0x14,0x08); //default value
++	i2c_write(client, 0x15,0x00); //default value
++	i2c_write(client, 0x18,0x0f);
++	i2c_write(client, 0x22,0x08); //default value
++	i2c_write(client, 0x23,0x00); //default value
++	i2c_write(client, 0x26,0x0f);
++
++	i2c_write(client, 0xff,0x81);
++	i2c_write(client, 0x0B,0xFE); //rpt reset
++}
++
++#if 0
++static void LT9211_ClkDetDebug(struct i2c_client *client)
++{
++	unsigned int fm_value;
++
++	i2c_write(client, 0xff,0x86);
++	i2c_write(client, 0x00,0x14);
++	mdelay(100);
++	fm_value = 0;
++	fm_value = (i2c_read(client, 0x08) &(0x0f));
++	fm_value = (fm_value<<8) ;
++	fm_value = fm_value + i2c_read(client, 0x09);
++	fm_value = (fm_value<<8) ;
++	fm_value = fm_value + i2c_read(client, 0x0a);
++
++	printk("input ttlclk: \n");
++	printk("\033[33m fm_value = %x |\033[0m\n", fm_value);
++}
++#endif
++
++static void LT9211_MipiRxPhy(struct i2c_client *client)
++{
++#ifdef INPUT_PORTA
++	debug("Port A PHY Config\n");
++	i2c_write(client, 0xff,0x82);
++	i2c_write(client, 0x02,0x44);  //Port A MIPI mode enable
++	i2c_write(client, 0x04,0xa0);  //select port A clk as byteclk
++	i2c_write(client, 0x05,0x22);  //port A CLK lane swap
++	i2c_write(client, 0x07,0x9f);  //port A clk enable
++	i2c_write(client, 0x08,0xfc);  //port A clk enable
++	i2c_write(client, 0x09,0x01);  //port A P/N swap
++	i2c_write(client, 0x17,0x0c);
++
++	i2c_write(client, 0xff,0x86);
++	i2c_write(client, 0x33,0x1b); //port a lane swap	1b:no swap
++#endif
++
++#ifdef INPUT_PORTB
++	debug("Port B PHY Config\n");
++	i2c_write(client, 0xff,0x82);
++	i2c_write(client, 0x02,0x44);   //Port A/B MIPI mode enable
++	i2c_write(client, 0x04,0xa1);  //select port A clk as byteclk
++	i2c_write(client, 0x05,0x26);  //port A CLK lane swap
++	i2c_write(client, 0x0d,0x26);   //port B CLK lane swap
++	i2c_write(client, 0x07,0x9f);   //port A clk enable  (??Portb?,porta?lane0 clk???)
++	i2c_write(client, 0x0f,0x9f);   //port B clk enable
++	i2c_write(client, 0x10,0xfc);   //select port B clk as byteclk
++	i2c_write(client, 0x11,0x01);   //port B P/N swap
++	i2c_write(client, 0x17,0x0c);
++	i2c_write(client, 0x1d,0x0c);
++
++	i2c_write(client, 0xff,0x86);
++	i2c_write(client, 0x34,0x1b);   //Port B Lane swap
++#endif
++
++	i2c_write(client, 0xff,0x81);
++	i2c_write(client, 0x20,0x7f);
++	i2c_write(client, 0x20,0xff);  //mlrx calib reset
++}
++
++static void LT9211_MipiRxDigital(struct i2c_client *client)
++{
++	i2c_write(client, 0xff,0x86);
++#ifdef INPUT_PORTA
++	i2c_write(client, 0x30,0x85);      //mipirx input port sel
++#endif
++
++#ifdef INPUT_PORTB
++	i2c_write(client, 0x30,0x8f);      //mipirx input port sel
++#endif
++
++	i2c_write(client, 0xff,0x85);
++	i2c_write(client, 0x88,0x40);       //select mipi in lvds out
++
++#ifdef MIPI_CSI
++	debug("Set to CSI Mode\n");
++	i2c_write(client, 0xff,0xd0);  //CSI_EN
++	i2c_write(client, 0x04,0x10);
++	i2c_write(client, 0x21,0xc6);  //CSI_SEL
++#else
++	debug("Set to DSI Mode\n");
++#endif
++
++	i2c_write(client, 0xff,0xd0);
++	i2c_write(client, 0x00,0x02);        //4Lane:0x00, 2Lane:0x02, 1Lane:0x01
++	i2c_write(client, 0x02,0x05);        //settle
++}
++
++static void LT9211_SetVideoTiming(struct i2c_client *client, struct video_timing *video_format)
++{
++	mdelay(100);
++	i2c_write(client, 0xff,0xd0);
++	i2c_write(client, 0x0d,(unsigned char)(video_format->vtotal>>8)); //vtotal[15:8]
++	i2c_write(client, 0x0e,(unsigned char)(video_format->vtotal)); //vtotal[7:0]
++	i2c_write(client, 0x0f,(unsigned char)(video_format->vact>>8)); //vactive[15:8]
++	i2c_write(client, 0x10,(unsigned char)(video_format->vact)); //vactive[7:0]
++	i2c_write(client, 0x15,(unsigned char)(video_format->vs)); //vs[7:0]
++	i2c_write(client, 0x17,(unsigned char)(video_format->vfp>>8)); //vfp[15:8]
++	i2c_write(client, 0x18,(unsigned char)(video_format->vfp)); //vfp[7:0]
++
++	i2c_write(client, 0x11,(unsigned char)(video_format->htotal>>8)); //htotal[15:8]
++	i2c_write(client, 0x12,(unsigned char)(video_format->htotal)); //htotal[7:0]
++	i2c_write(client, 0x13,(unsigned char)(video_format->hact>>8)); //hactive[15:8]
++	i2c_write(client, 0x14,(unsigned char)(video_format->hact)); //hactive[7:0]
++	i2c_write(client, 0x16,(unsigned char)(video_format->hs)); //hs[7:0]
++	i2c_write(client, 0x19,(unsigned char)(video_format->hfp>>8)); //hfp[15:8]
++	i2c_write(client, 0x1a,(unsigned char)(video_format->hfp)); //hfp[7:0]
++}
++
++#ifdef DEBUG
++static void LT9211_debug(struct i2c_client *client)
++{
++	int i;
++	unsigned char start = 0x80;
++	i2c_write(client, 0xff,0xd0);
++	for(i=0;i<30;i++)
++		printk("read 0x%02x = 0x%02x\n", start+i, i2c_read(client, start+i));
++}
++#endif
++
++static int LT9211_TimingSet(struct i2c_client *client)
++{
++	unsigned short hact ;
++	unsigned short vact ;
++	unsigned char pa_lpn = 0;
++
++	lt9211_mipirx_logic_rst(client);
++	mdelay(100);
++
++	i2c_write(client, 0xff,0xd0);
++	hact = (i2c_read(client, 0x82)<<8) + i2c_read(client, 0x83) ;
++	mipi_fmt = (i2c_read(client, 0x84) & 0x0f);
++	vact = (i2c_read(client, 0x85)<<8) +i2c_read(client, 0x86);
++	pa_lpn = i2c_read(client, 0x9c);
++#ifdef DEBUG
++	LT9211_debug(client);
++#endif
++
++	if(mipi_fmt == 0x03) {
++		debug("Input MIPI FMT: CSI_YUV422_16\n");
++		hact = hact / 2;
++	} else if(mipi_fmt == 0x0a) {
++		debug("Input MIPI FMT: RGB888\n");
++		hact = hact / 3;
++	}
++
++	debug("\033[33m hact = %d |\033[0m\n", hact);
++	debug("\033[33m vact = %d |\033[0m\n", vact);
++
++	debug("fmt = %x\n", mipi_fmt);
++	debug("pa_lpn = %x\n", pa_lpn);
++
++	mdelay(100);
++	if ((hact == video_1280x720_60Hz.hact ) &&( vact == video_1280x720_60Hz.vact )) {
++		pVideo_Format = &video_1280x720_60Hz;
++		LT9211_SetVideoTiming(client, &video_1280x720_60Hz);
++	} else if ((hact == video_1366x768_60Hz.hact ) &&( vact == video_1366x768_60Hz.vact )) {
++		pVideo_Format = &video_1366x768_60Hz;
++		LT9211_SetVideoTiming(client, &video_1366x768_60Hz);
++	} else if ((hact == video_1920x1080_60Hz.hact ) &&( vact == video_1920x1080_60Hz.vact )) {
++		pVideo_Format = &video_1920x1080_60Hz;
++		LT9211_SetVideoTiming(client, &video_1920x1080_60Hz);
++	} else if ((hact == video_1920x1200_60Hz.hact ) &&( vact == video_1920x1200_60Hz.vact )) {
++		pVideo_Format = &video_1920x1200_60Hz;
++		LT9211_SetVideoTiming(client, &video_1920x1200_60Hz);
++	} else {
++		pVideo_Format = NULL;
++		printk("video_none\n");
++		return -1;
++	}
++
++	return 0;
++}
++
++static void LT9211_DesscPll(struct i2c_client *client)
++{
++	i2c_write(client, 0xff,0x82);
++	i2c_write(client, 0x2d,0x48);
++
++	if(pVideo_Format->pclk_khz < 44000) {
++		i2c_write(client, 0x35,0x83);
++	} else if(pVideo_Format->pclk_khz < 88000) {
++		i2c_write(client, 0x35,0x82);
++	} else if(pVideo_Format->pclk_khz < 176000) {
++		i2c_write(client, 0x35,0x81);
++	}
++}
++
++static int LT9211_MipiPcr(struct i2c_client *client)
++{
++	unsigned char loopx;
++	i2c_write(client, 0xff,0xd0);
++	i2c_write(client, 0x26,0x17);
++	i2c_write(client, 0x27,0xC3);
++	i2c_write(client, 0x2d,0x30);  //PCR M overflow limit setting.
++	i2c_write(client, 0x31,0x10);  //PCR M underflow limit setting.
++	i2c_write(client, 0x23,0x20);
++
++	i2c_write(client, 0x38,0x02);
++	i2c_write(client, 0x39,0x10);
++	i2c_write(client, 0x3a,0x20);
++	i2c_write(client, 0x3b,0x60);
++	i2c_write(client, 0x3f,0x04);
++	i2c_write(client, 0x40,0x08);
++	i2c_write(client, 0x41,0x10);
++
++	i2c_write(client, 0xff,0x81);
++	i2c_write(client, 0x0B,0xEE);
++	i2c_write(client, 0x0B,0xFE);
++
++	for(loopx = 0; loopx < 5; loopx++) //Check pcr_stable
++	{
++		mdelay(200);
++		i2c_write(client, 0xff,0xd0);
++		if(i2c_read(client, 0x87)&0x08) {
++			debug("\033[32mLT9211 pcr stable\033[0m\n");
++			return 0;
++		}
++	}
++	printk("LT9211 pcr unstable!!!!\n");
++	return -1;
++}
++
++static void LT9211_CSC(struct i2c_client *client)
++{
++	//yuv422 to rgb888
++	if(mipi_fmt == 0x03) {
++		debug("csc:yuv422 to rgb888\n");
++		i2c_write(client, 0xff,0xf9);
++		i2c_write(client, 0x90,0x03);
++		i2c_write(client, 0x91,0x03);
++	}
++}
++
++static void LT9211_TxPhy(struct i2c_client *client)
++{
++	i2c_write(client, 0xff,0x82);
++	i2c_write(client, 0x62,0x00); //ttl output disable
++	if( LVDS_PORTNUM == LVDS_2PORT ) {
++		i2c_write(client, 0x3b,0xb8);
++	} else {
++		i2c_write(client, 0x3b,0x38);  //dual-port lvds tx phy
++	}
++	i2c_write(client, 0x3e,0x92);
++	i2c_write(client, 0x3f,0x48);
++	i2c_write(client, 0x40,0x31);
++	i2c_write(client, 0x43,0x80);
++	i2c_write(client, 0x44,0x00);
++	i2c_write(client, 0x45,0x00);
++	i2c_write(client, 0x49,0x00);
++	i2c_write(client, 0x4a,0x01);
++	i2c_write(client, 0x4e,0x00);
++	i2c_write(client, 0x4f,0x00);
++	i2c_write(client, 0x50,0x00);
++	i2c_write(client, 0x53,0x00);
++	i2c_write(client, 0x54,0x01);
++
++	i2c_write(client, 0xff,0x86);
++	i2c_write(client, 0x46,0x10);
++#ifdef LVDS_2PORT_SWAP
++	debug("LVDS Output Port Swap!\n");
++	i2c_write(client, 0x46,0x40);
++#endif
++
++	i2c_write(client, 0xff,0x81);
++	i2c_write(client, 0x20,0x7b);
++	i2c_write(client, 0x20,0xff); //mlrx mltx calib reset
++}
++
++static void LT9211_TxDigital(struct i2c_client *client)
++{
++	debug("LT9211 LVDS_OUTPUT_MODE: \n");
++	i2c_write(client, 0xff,0x85); /* lvds tx controller */
++	i2c_write(client, 0x59,0x40);
++	if( LVDS_DATAFORMAT == VESA ) {
++		debug("Data Format: VESA\n");
++		i2c_write(client, 0x59, (i2c_read(client, 0x59) & 0x7f));
++	} else if( LVDS_DATAFORMAT == JEIDA ) {
++		debug("Data Format: JEIDA\n");
++		i2c_write(client, 0x59, (i2c_read(client, 0x59) | 0x80));
++	}
++	if( LVDS_COLORDEPTH == DEPTH_6BIT ) {
++		debug("ColorDepth: 6Bit\n");
++		i2c_write(client, 0x59, (i2c_read(client, 0x59) & 0xef));
++	} else if( LVDS_COLORDEPTH == DEPTH_8BIT ) {
++		debug("ColorDepth: 8Bit\n");
++		i2c_write(client, 0x59, (i2c_read(client, 0x59) | 0x10));
++	}
++	if( LVDS_MODE == SYNC_MODE ) {
++		debug("LVDS_MODE: Sync Mode\n");
++		i2c_write(client, 0x59, (i2c_read(client, 0x59) & 0xdf));
++	} else if( LVDS_MODE == DE_MODE ) {
++		debug("LVDS_MODE: De Mode\n");
++		i2c_write(client, 0x59, (i2c_read(client, 0x59) | 0x20));
++	}
++
++	i2c_write(client, 0x5a,0xaa);
++	i2c_write(client, 0x5b,0xaa);
++	if( LVDS_PORTNUM == LVDS_2PORT ) {
++		debug("LVDS Output Port Num: 2Port\n");
++		i2c_write(client, 0x5c,0x01);	//lvdstx port sel 01:dual;00:single
++	} else {
++		debug("LVDS Output Port Num: 1Port\n");
++		i2c_write(client, 0x5c,0x00);
++	}
++	i2c_write(client, 0xa1,0x77);
++	i2c_write(client, 0xff,0x86);
++	i2c_write(client, 0x40,0x40); //tx_src_sel
++	/*port src sel*/
++	i2c_write(client, 0x41,0x34);
++	i2c_write(client, 0x42,0x10);
++	i2c_write(client, 0x43,0x23); //pt0_tx_src_sel
++	i2c_write(client, 0x44,0x41);
++	i2c_write(client, 0x45,0x02); //pt1_tx_src_scl
++}
++
++static void LT9211_Txpll(struct i2c_client *client)
++{
++	unsigned char loopx;
++
++	i2c_write(client, 0xff,0x82);
++	i2c_write(client, 0x36,0x01); //b7:txpll_pd
++	if( LVDS_PORTNUM == LVDS_1PORT ) {
++		i2c_write(client, 0x37,0x29);
++	} else {
++		i2c_write(client, 0x37,0x2a);
++	}
++	i2c_write(client, 0x38,0x06);
++	i2c_write(client, 0x39,0x30);
++	i2c_write(client, 0x3a,0x8e);
++	i2c_write(client, 0xff,0x87);
++	i2c_write(client, 0x37,0x14);
++	i2c_write(client, 0x13,0x00);
++	i2c_write(client, 0x13,0x80);
++	mdelay(100);
++	for(loopx = 0; loopx < 10; loopx++) //Check Tx PLL cal
++	{
++		i2c_write(client, 0xff,0x87);
++		if(i2c_read(client, 0x1f)& 0x80) {
++			if(i2c_read(client, 0x20)& 0x80) {
++				debug("LT9211 tx pll lock\n");
++			} else {
++				printk("LT9211 tx pll unlocked\n");
++			}
++			debug("LT9211 tx pll cal done\n");
++			break;
++		} else {
++			printk("LT9211 tx pll unlocked\n");
++		}
++	}
++}
++
++#ifdef DEBUG
++static void LT9211_LvdsClkDebug(struct i2c_client *client)
++{
++	unsigned int fm_value;
++
++	i2c_write(client, 0xff,0x86);
++	i2c_write(client, 0x00,0x12);
++	mdelay(100);
++	fm_value = 0;
++	fm_value = (i2c_read(client, 0x08) &(0x0f));
++	fm_value = (fm_value<<8) ;
++	fm_value = fm_value + i2c_read(client, 0x09);
++	fm_value = (fm_value<<8) ;
++	fm_value = fm_value + i2c_read(client, 0x0a);
++
++	printk("\033[33m lvds pixclk = %d |\033[0m\n", fm_value);
++}
++
++static void LT9211_MipiByteClkDebug(struct i2c_client *client)
++{
++	unsigned int fm_value;
++
++	i2c_write(client, 0xff,0x86);
++#ifdef INPUT_PORTA
++	i2c_write(client, 0x00,0x01);
++#endif
++#ifdef INPUT_PORTB
++	i2c_write(client, 0x00,0x02);
++#endif
++	mdelay(100);
++	fm_value = 0;
++	fm_value = (i2c_read(client, 0x08) &(0x0f));
++	fm_value = (fm_value<<8) ;
++	fm_value = fm_value + i2c_read(client, 0x09);
++	fm_value = (fm_value<<8) ;
++	fm_value = fm_value + i2c_read(client, 0x0a);
++	printk("\033[33m mipi byteclk = %d |\033[0m\n", fm_value);
++}
++
++static void LT9211_VideoCheckDebug(struct i2c_client *client)
++{
++	unsigned char sync_polarity;
++	unsigned short hact, vact;
++	unsigned short hs, vs;
++	unsigned short hbp, vbp;
++	unsigned short htotal, vtotal;
++	unsigned short hfp, vfp;
++
++	i2c_write(client, 0xff,0x86);
++	i2c_write(client, 0x20,0x00);
++
++	sync_polarity = i2c_read(client, 0x70);
++	vs = i2c_read(client, 0x71);
++
++	hs = i2c_read(client, 0x72);
++	hs = (hs<<8) + i2c_read(client, 0x73);
++
++	vbp = i2c_read(client, 0x74);
++	vfp = i2c_read(client, 0x75);
++
++	hbp = i2c_read(client, 0x76);
++	hbp = (hbp<<8) + i2c_read(client, 0x77);
++
++	hfp = i2c_read(client, 0x78);
++	hfp = (hfp<<8) + i2c_read(client, 0x79);
++
++	vtotal = i2c_read(client, 0x7A);
++	vtotal = (vtotal<<8) + i2c_read(client, 0x7B);
++
++	htotal = i2c_read(client, 0x7C);
++	htotal = (htotal<<8) + i2c_read(client, 0x7D);
++
++	vact = i2c_read(client, 0x7E);
++	vact = (vact<<8)+ i2c_read(client, 0x7F);
++
++	hact = i2c_read(client, 0x80);
++	hact = (hact<<8) + i2c_read(client, 0x81);
++
++	printk("sync_polarity = %x\n", sync_polarity);
++
++	printk("\033[33m hfp = %d , hs = %d , hbp = %d , hact = %d , htotal = %d\033[0m\n", hfp, hs, hbp, hact, htotal);
++
++	printk("\033[33m vfp = %d , vs = %d , vbp = %d , vact = %d , vtotal = %d\033[0m\n", vfp, vs, vbp, vact, vtotal);
++}
++#endif
++
++int LT9211_MIPI2LVDS_Config(struct i2c_client *client)
++{
++	int retry = 5;
++	int ret = 0;
++	debug("*************LT9211 MIPI2LVDS Config*************\n");
++#ifdef DEBUG
++	LT9211_ChipID(client);
++#endif
++	LT9211_SystemInt(client);
++	LT9211_MipiRxPhy(client);
++	LT9211_MipiRxDigital(client);
++
++	while(retry--)
++		if ((ret = LT9211_TimingSet(client)) == 0) break;
++
++	if( pVideo_Format != NULL )
++	{
++#ifdef DEBUG
++		LT9211_MipiByteClkDebug(client);
++#endif
++		LT9211_DesscPll(client);
++
++		retry = 5;
++		while(retry--)
++			if ((ret = LT9211_MipiPcr(client)) == 0) break;
++
++		LT9211_CSC(client);
++		/********LVDS OUTPUT CONFIG********/
++		LT9211_TxPhy(client);
++		LT9211_TxDigital(client);
++		LT9211_Txpll(client);
++
++#ifdef DEBUG
++		/* i2c_write(client, 0xff,0x85); */
++		/* i2c_write(client, 0x88,0xC0); // debug: colorbar */
++		/* i2c_write(client, 0xA1,0x04); // single color 0x1: blue, 0x2: green, 0x4: red. */
++
++		LT9211_LvdsClkDebug(client);
++		LT9211_VideoCheckDebug(client);
++#endif
++	}
++	return ret;
++}
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/lt9211.h b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/lt9211.h
+new file mode 100644
+index 000000000..5fce433ec
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/lt9211.h
+@@ -0,0 +1,62 @@
++#ifndef _LT9211_H
++#define _LT9211_H
++
++/* #define DEBUG */
++
++/******************* MIPI Input Config ********************/
++/* #define MIPI_CSI */
++
++#define INPUT_PORTA
++//#define INPUT_PORTB
++
++#define Lane_Num 2
++/******************* MIPI Input Config ********************/
++
++/******************* Lvds Output Config ********************/
++enum LT9211_LVDSPORT_ENUM
++{
++    LVDS_1PORT = 0,
++    LVDS_2PORT = 1
++};
++#define LVDS_PORTNUM LVDS_2PORT
++
++enum LT9211_LVDSMODE_ENUM
++{
++    DE_MODE = 0,
++    SYNC_MODE = 1
++};
++#define LVDS_MODE DE_MODE
++
++enum LT9211_LVDSDATAFORMAT_ENUM
++{
++    VESA = 0,
++    JEIDA = 1
++};
++#define LVDS_DATAFORMAT VESA
++
++enum LT9211_LVDSCOLORDEPTH_ENUM
++{
++    DEPTH_6BIT = 0,
++    DEPTH_8BIT = 1
++};
++#define LVDS_COLORDEPTH DEPTH_8BIT
++
++//#define LVDS_2PORT_SWAP
++
++/******************* Lvds Output Config ********************/
++
++struct video_timing {
++unsigned short hfp;
++unsigned short hs;
++unsigned short hbp;
++unsigned short hact;
++unsigned short htotal;
++unsigned short vfp;
++unsigned short vs;
++unsigned short vbp;
++unsigned short vact;
++unsigned short vtotal;
++unsigned int pclk_khz;
++};
++
++#endif
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-G104X1L04.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-G104X1L04.c
+new file mode 100644
+index 000000000..d5c9cb66f
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-G104X1L04.c
+@@ -0,0 +1,1124 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-G104X1L04.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++
++#include "../ingenicfb.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct i2c_client *client;
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	int power;
++
++	int i2c_id;
++	struct board_gpio reset;
++	struct board_gpio lcd_en;
++	struct board_gpio bl_en;
++
++	char *panel_name;
++};
++
++#define FPS    60
++#define HACT   1024
++
++#define VACT   768
++
++#define HFP    160
++#define HBP    140
++#define HS     20
++
++#define VFP    20
++#define VBP    10
++#define VS     8
++
++
++////////////////////////////LT9211 begin/////////////////////////////////////////////
++//#include "lt9211.h"
++/******************* MIPI Input Config ********************/
++#define INPUT_PORTA
++//#define INPUT_PORTB
++#define Lane_Num 2
++/******************* MIPI Input Config ********************/
++
++/******************* Lvds Output Config ********************/
++enum LT9211_LVDSPORT_ENUM
++{
++    LVDS_1PORT = 0,
++    LVDS_2PORT = 1
++};
++#define LVDS_PORTNUM LVDS_1PORT
++
++enum LT9211_LVDSMODE_ENUM
++{
++    DE_MODE = 0,
++    SYNC_MODE = 1
++};
++#define LVDS_MODE DE_MODE
++
++enum LT9211_LVDSDATAFORMAT_ENUM
++{
++    VESA = 0,
++    JEIDA = 1
++};
++#define LVDS_DATAFORMAT VESA
++
++enum LT9211_LVDSCOLORDEPTH_ENUM
++{
++    DEPTH_6BIT = 0,
++    DEPTH_8BIT = 1
++};
++#define LVDS_COLORDEPTH DEPTH_8BIT
++
++//#define LVDS_2PORT_SWAP
++/******************* Lvds Output Config ********************/
++
++struct video_timing {
++unsigned short hfp;
++unsigned short hs;
++unsigned short hbp;
++unsigned short hact;
++unsigned short htotal;
++unsigned short vfp;
++unsigned short vs;
++unsigned short vbp;
++unsigned short vact;
++unsigned short vtotal;
++unsigned int pclk_khz;
++};
++
++//#include "lt9211.c"
++static unsigned char mipi_fmt = 0;
++struct video_timing *pVideo_Format;
++//#define DEBUG
++
++#ifdef DEBUG
++#define debug(info, ...) printk(info, ##__VA_ARGS__)
++#else
++#define debug(info, ...)
++#endif
++
++#define HTOTAL (HFP + HACT + HBP + HS)
++#define VTOTAL (VFP + VACT + VBP + VS)
++
++#define PIXCLK (HTOTAL * VTOTAL * FPS / 1000)
++
++//hfp, hs, hbp, hact, htotal, vfp, vs, vbp, vact, vtotal, pixclk
++//struct video_timing video_1920x1080_60Hz   ={HFP, HS, HBP, HACT, HTOTAL, VFP, VS, VBP, VACT, VTOTAL, PIXCLK};
++struct video_timing video_1024x768_60Hz = {HFP, HS, HBP, HACT, HTOTAL, VFP, VS, VBP, VACT, VTOTAL, PIXCLK};
++
++static unsigned int i2c_write(struct i2c_client *client,unsigned char addr,unsigned char value);
++static unsigned char i2c_read(struct i2c_client *client, u8 addr);
++
++#ifdef DEBUG
++static void LT9211_ChipID(struct i2c_client *client)
++{
++	i2c_write(client, 0xff,0x81);//register bank
++	printk("LT9211 Chip ID:%x,",i2c_read(client, 0x00));
++	printk("%02x, ",i2c_read(client, 0x01));
++	printk("%02x\n",i2c_read(client, 0x02));
++}
++#endif
++
++/** lvds rx logic rst **/
++static void lt9211_mipirx_logic_rst(struct i2c_client *client)
++{
++	i2c_write(client, 0xff,0x81);
++	i2c_write(client, 0x0a,0xc0);
++	i2c_write(client, 0x20,0xbf);  //mipi rx div logic reset,for portb input
++	mdelay(10);
++	i2c_write(client, 0x0a,0xc1);
++	i2c_write(client, 0x20,0xff);
++}
++
++static void LT9211_SystemInt(struct i2c_client *client)
++{
++	/* system clock init */
++	i2c_write(client, 0xff,0x82);
++	i2c_write(client, 0x01,0x18);
++
++	i2c_write(client, 0xff,0x86);
++	i2c_write(client, 0x06,0x61);
++	i2c_write(client, 0x07,0xa8); //fm for sys_clk
++
++	i2c_write(client, 0xff,0x87);
++	i2c_write(client, 0x14,0x08); //default value
++	i2c_write(client, 0x15,0x00); //default value
++	i2c_write(client, 0x18,0x0f);
++	i2c_write(client, 0x22,0x08); //default value
++	i2c_write(client, 0x23,0x00); //default value
++	i2c_write(client, 0x26,0x0f);
++
++//	i2c_write(client, 0xff,0x81);
++//	i2c_write(client, 0x0B,0xFE); //rpt reset
++}
++
++static void LT9211_MipiRxPhy(struct i2c_client *client)
++{
++#ifdef INPUT_PORTA
++	debug("Port A PHY Config\n");
++	i2c_write(client, 0xff,0x82);
++	i2c_write(client, 0x02,0x44);  //Port A MIPI mode enable
++	i2c_write(client, 0x04,0xa0);  //select port A clk as byteclk
++	i2c_write(client, 0x05,0x22);  //port A CLK lane swap
++	i2c_write(client, 0x07,0x9f);  //port A clk enable
++	i2c_write(client, 0x08,0xfc);  //port A clk enable
++	i2c_write(client, 0x09,0x01);  //port A P/N swap
++	i2c_write(client, 0x17,0x0c);
++
++	i2c_write(client, 0xff,0x86);
++	i2c_write(client, 0x33,0x1b); //port a lane swap	1b:no swap
++#endif
++
++#ifdef INPUT_PORTB
++	debug("Port B PHY Config\n");
++	i2c_write(client, 0xff,0x82);
++	i2c_write(client, 0x02,0x44);   //Port A/B MIPI mode enable
++	i2c_write(client, 0x04,0xa1);  //select port A clk as byteclk
++	i2c_write(client, 0x05,0x26);  //port A CLK lane swap
++	i2c_write(client, 0x0d,0x26);   //port B CLK lane swap
++	i2c_write(client, 0x07,0x9f);   //port A clk enable  (??Portb?,porta?lane0 clk???)
++	i2c_write(client, 0x0f,0x9f);   //port B clk enable
++	i2c_write(client, 0x10,0xfc);   //select port B clk as byteclk
++	i2c_write(client, 0x11,0x01);   //port B P/N swap
++	i2c_write(client, 0x17,0x0c);
++	i2c_write(client, 0x1d,0x0c);
++
++	i2c_write(client, 0xff,0x86);
++	i2c_write(client, 0x34,0x1b);   //Port B Lane swap
++#endif
++
++	i2c_write(client, 0xff,0x81);
++	i2c_write(client, 0x20,0x7f);
++	i2c_write(client, 0x20,0xff);  //mlrx calib reset
++}
++
++static void LT9211_MipiRxDigital(struct i2c_client *client)
++{
++	i2c_write(client, 0xff,0x86);
++#ifdef INPUT_PORTA
++	i2c_write(client, 0x30,0x85);      //mipirx input port sel
++#endif
++
++#ifdef INPUT_PORTB
++	i2c_write(client, 0x30,0x8f);      //mipirx input port sel
++#endif
++
++	i2c_write(client, 0xff,0x85);
++	i2c_write(client, 0x88,0x40);       //select mipi in lvds out
++
++#ifdef MIPI_CSI
++	debug("Set to CSI Mode\n");
++	i2c_write(client, 0xff,0xd0);  //CSI_EN
++	i2c_write(client, 0x04,0x10);
++	i2c_write(client, 0x21,0xc6);  //CSI_SEL
++#else
++	debug("Set to DSI Mode\n");
++#endif
++
++	i2c_write(client, 0xff,0xd0);
++	i2c_write(client, 0x00,0x02);        //4Lane:0x00, 2Lane:0x02, 1Lane:0x01
++	i2c_write(client, 0x02,0x05);        //settle
++}
++
++static void LT9211_SetVideoTiming(struct i2c_client *client, struct video_timing *video_format)
++{
++	mdelay(100);
++	i2c_write(client, 0xff,0xd0);
++	i2c_write(client, 0x0d,(unsigned char)(video_format->vtotal>>8)); //vtotal[15:8]
++	i2c_write(client, 0x0e,(unsigned char)(video_format->vtotal)); //vtotal[7:0]
++	i2c_write(client, 0x0f,(unsigned char)(video_format->vact>>8)); //vactive[15:8]
++	i2c_write(client, 0x10,(unsigned char)(video_format->vact)); //vactive[7:0]
++	i2c_write(client, 0x15,(unsigned char)(video_format->vs)); //vs[7:0]
++	i2c_write(client, 0x17,(unsigned char)(video_format->vfp>>8)); //vfp[15:8]
++	i2c_write(client, 0x18,(unsigned char)(video_format->vfp)); //vfp[7:0]
++
++	i2c_write(client, 0x11,(unsigned char)(video_format->htotal>>8)); //htotal[15:8]
++	i2c_write(client, 0x12,(unsigned char)(video_format->htotal)); //htotal[7:0]
++	i2c_write(client, 0x13,(unsigned char)(video_format->hact>>8)); //hactive[15:8]
++	i2c_write(client, 0x14,(unsigned char)(video_format->hact)); //hactive[7:0]
++	i2c_write(client, 0x16,(unsigned char)(video_format->hs)); //hs[7:0]
++	i2c_write(client, 0x19,(unsigned char)(video_format->hfp>>8)); //hfp[15:8]
++	i2c_write(client, 0x1a,(unsigned char)(video_format->hfp)); //hfp[7:0]
++}
++
++#ifdef DEBUG
++static void LT9211_debug(struct i2c_client *client)
++{
++	int i;
++	unsigned char start = 0x80;
++	i2c_write(client, 0xff,0xd0);
++	for(i=0;i<30;i++)
++		printk("read 0x%02x = 0x%02x\n", start+i, i2c_read(client, start+i));
++}
++#endif
++
++static int LT9211_TimingSet(struct i2c_client *client)
++{
++	unsigned short hact ;
++	unsigned short vact ;
++	unsigned char pa_lpn = 0;
++
++	lt9211_mipirx_logic_rst(client);
++	mdelay(100);
++
++	i2c_write(client, 0xff,0xd0);
++	hact = (i2c_read(client, 0x82)<<8) + i2c_read(client, 0x83) ;
++	mipi_fmt = (i2c_read(client, 0x84) & 0x0f);
++	vact = (i2c_read(client, 0x85)<<8) +i2c_read(client, 0x86);
++	pa_lpn = i2c_read(client, 0x9c);
++#ifdef DEBUG
++	LT9211_debug(client);
++#endif
++
++	if(mipi_fmt == 0x03) {
++		debug("Input MIPI FMT: CSI_YUV422_16\n");
++		hact = hact / 2;
++	} else if(mipi_fmt == 0x0a) {
++		debug("Input MIPI FMT: RGB888\n");
++		hact = hact / 3;
++	}
++
++	debug("\033[33m hact = %d |\033[0m\n", hact);
++	debug("\033[33m vact = %d |\033[0m\n", vact);
++
++	debug("fmt = %x\n", mipi_fmt);
++	debug("pa_lpn = %x\n", pa_lpn);
++
++	mdelay(100);
++	pVideo_Format = &video_1024x768_60Hz;
++	LT9211_SetVideoTiming(client, &video_1024x768_60Hz);
++
++	return 0;
++}
++
++static void LT9211_DesscPll(struct i2c_client *client)
++{
++	i2c_write(client, 0xff,0x82);
++	i2c_write(client, 0x2d,0x48);
++
++	if(pVideo_Format->pclk_khz < 44000) {
++		i2c_write(client, 0x35,0x83);
++	} else if(pVideo_Format->pclk_khz < 88000) {
++		i2c_write(client, 0x35,0x82);
++	} else if(pVideo_Format->pclk_khz < 176000) {
++		i2c_write(client, 0x35,0x81);
++	}
++}
++
++/*
++static int LT9211_MipiPcr(struct i2c_client *client)
++{
++	unsigned char loopx;
++	i2c_write(client, 0xff,0xd0);
++	i2c_write(client, 0x26,0x17);
++	i2c_write(client, 0x27,0xC3);
++	i2c_write(client, 0x2d,0x30);  //PCR M overflow limit setting.
++	i2c_write(client, 0x31,0x10);  //PCR M underflow limit setting.
++	i2c_write(client, 0x23,0x20);
++
++	i2c_write(client, 0x38,0x02);
++	i2c_write(client, 0x39,0x10);
++	i2c_write(client, 0x3a,0x20);
++	i2c_write(client, 0x3b,0x60);
++	i2c_write(client, 0x3f,0x04);
++	i2c_write(client, 0x40,0x08);
++	i2c_write(client, 0x41,0x10);
++
++	i2c_write(client, 0xff,0x81);
++	i2c_write(client, 0x0B,0xEE);
++	i2c_write(client, 0x0B,0xFE);
++
++	for(loopx = 0; loopx < 5; loopx++) //Check pcr_stable
++	{
++		mdelay(200);
++		i2c_write(client, 0xff,0xd0);
++		if(i2c_read(client, 0x87)&0x08) {
++			debug("\033[32mLT9211 pcr stable\033[0m\n");
++			return 0;
++		}
++	}
++	printk("LT9211 pcr unstable!!!!\n");
++	return -1;
++}
++*/
++
++static int  LT9211_MipiPcr(struct i2c_client *client)
++{
++	u8 loopx;
++	u8 pcr_m;
++
++    i2c_write(client, 0xff,0xd0);
++    i2c_write(client, 0x0c,0x60);  //fifo position
++	i2c_write(client, 0x1c,0x60);  //fifo position
++	i2c_write(client, 0x24,0x70);  //pcr mode( de hs vs)
++
++	i2c_write(client, 0x2d,0x30); //M up limit
++	i2c_write(client, 0x31,0x0a); //M down limit
++
++	/*stage1 hs mode*/
++	i2c_write(client, 0x25,0xf0);  //line limit
++	i2c_write(client, 0x2a,0x30);  //step in limit
++	i2c_write(client, 0x21,0x4f);  //hs_step
++	i2c_write(client, 0x22,0x00);
++
++	/*stage2 hs mode*/
++	i2c_write(client, 0x1e,0x01);  //RGD_DIFF_SND[7:4],RGD_DIFF_FST[3:0]
++	i2c_write(client, 0x23,0x80);  //hs_step
++    /*stage2 de mode*/
++	i2c_write(client, 0x0a,0x02); //de adjust pre line
++	i2c_write(client, 0x38,0x02); //de_threshold 1
++	i2c_write(client, 0x39,0x04); //de_threshold 2
++	i2c_write(client, 0x3a,0x08); //de_threshold 3
++	i2c_write(client, 0x3b,0x10); //de_threshold 4
++
++	i2c_write(client, 0x3f,0x04); //de_step 1
++	i2c_write(client, 0x40,0x08); //de_step 2
++	i2c_write(client, 0x41,0x10); //de_step 3
++	i2c_write(client, 0x42,0x20); //de_step 4
++
++	i2c_write(client, 0x2b,0xa0); //stable out
++	//Timer0_Delay1ms(100);
++    i2c_write(client, 0xff,0xd0);   //enable HW pcr_m
++	pcr_m = i2c_read(client, 0x26);
++	pcr_m &= 0x7f;
++	i2c_write(client, 0x26,pcr_m);
++	i2c_write(client, 0x27,0x0f);
++
++	i2c_write(client, 0xff,0x81);  //pcr reset
++	i2c_write(client, 0x20,0xbf); // mipi portB div issue
++	i2c_write(client, 0x20,0xff);
++	mdelay(5);
++	i2c_write(client, 0x0B,0x6F);
++	i2c_write(client, 0x0B,0xFF);
++
++
++	mdelay(800);//800->120
++	for(loopx = 0; loopx < 10; loopx++) //Check pcr_stable 10
++	{
++		mdelay(200);
++		i2c_write(client, 0xff,0xd0);
++		if(i2c_read(client, 0x87)&0x08)
++		{
++			printk("\r\nLT9211 pcr stable");
++			i2c_write(client, 0xff,0xd0);
++			printk("LT9211 pcr_stable_M=%x\n",(i2c_read(client, 0x94)&0x7F));//打�M值
++			return 0;
++		}
++	}
++
++
++	printk("\r\nLT9211 pcr unstable!!!!");
++	i2c_write(client, 0xff,0xd0);
++	printk("LT9211 pcr_stable_M=%x\n",(i2c_read(client, 0x94)&0x7F));//打�M值
++	return -1;
++}
++
++static void LT9211_CSC(struct i2c_client *client)
++{
++	//yuv422 to rgb888
++	if(mipi_fmt == 0x03) {
++		debug("csc:yuv422 to rgb888\n");
++		i2c_write(client, 0xff,0xf9);
++		i2c_write(client, 0x90,0x03);
++		i2c_write(client, 0x91,0x03);
++	}
++}
++
++static void LT9211_TxPhy(struct i2c_client *client)
++{
++	i2c_write(client, 0xff,0x82);
++	i2c_write(client, 0x62,0x00); //ttl output disable
++	if( LVDS_PORTNUM == LVDS_2PORT ) {
++		i2c_write(client, 0x3b,0xb8);
++	} else {
++		i2c_write(client, 0x3b,0x38);  //dual-port lvds tx phy
++	}
++	i2c_write(client, 0x3e,0x92);
++	i2c_write(client, 0x3f,0x48);
++	i2c_write(client, 0x40,0x31);
++	i2c_write(client, 0x43,0x80);
++	i2c_write(client, 0x44,0x00);
++	i2c_write(client, 0x45,0x00);
++	i2c_write(client, 0x49,0x00);
++	i2c_write(client, 0x4a,0x01);
++	i2c_write(client, 0x4e,0x00);
++	i2c_write(client, 0x4f,0x00);
++	i2c_write(client, 0x50,0x00);
++	i2c_write(client, 0x53,0x00);
++	i2c_write(client, 0x54,0x01);
++
++	i2c_write(client, 0xff,0x86);
++	i2c_write(client, 0x46,0x10);
++#ifdef LVDS_2PORT_SWAP
++	debug("LVDS Output Port Swap!\n");
++	i2c_write(client, 0x46,0x40);
++#endif
++
++	i2c_write(client, 0xff,0x81);
++	i2c_write(client, 0x20,0x7b);
++	i2c_write(client, 0x20,0xff); //mlrx mltx calib reset
++}
++
++static void LT9211_TxDigital(struct i2c_client *client)
++{
++	debug("LT9211 LVDS_OUTPUT_MODE: \n");
++	i2c_write(client, 0xff,0x85); /* lvds tx controller */
++	i2c_write(client, 0x59,0x40);
++	if( LVDS_DATAFORMAT == VESA ) {
++		debug("Data Format: VESA\n");
++		i2c_write(client, 0x59, (i2c_read(client, 0x59) & 0x7f));
++	} else if( LVDS_DATAFORMAT == JEIDA ) {
++		debug("Data Format: JEIDA\n");
++		i2c_write(client, 0x59, (i2c_read(client, 0x59) | 0x80));
++	}
++	if( LVDS_COLORDEPTH == DEPTH_6BIT ) {
++		debug("ColorDepth: 6Bit\n");
++		i2c_write(client, 0x59, (i2c_read(client, 0x59) & 0xef));
++	} else if( LVDS_COLORDEPTH == DEPTH_8BIT ) {
++		debug("ColorDepth: 8Bit\n");
++		i2c_write(client, 0x59, (i2c_read(client, 0x59) | 0x10));
++	}
++	if( LVDS_MODE == SYNC_MODE ) {
++		debug("LVDS_MODE: Sync Mode\n");
++		i2c_write(client, 0x59, (i2c_read(client, 0x59) & 0xdf));
++	} else if( LVDS_MODE == DE_MODE ) {
++		debug("LVDS_MODE: De Mode\n");
++		i2c_write(client, 0x59, (i2c_read(client, 0x59) | 0x20));
++	}
++
++	i2c_write(client, 0x5a,0xaa);
++	i2c_write(client, 0x5b,0xaa);
++	if( LVDS_PORTNUM == LVDS_2PORT ) {
++		debug("LVDS Output Port Num: 2Port\n");
++		i2c_write(client, 0x5c,0x01);	//lvdstx port sel 01:dual;00:single
++	} else {
++		debug("LVDS Output Port Num: 1Port\n");
++		i2c_write(client, 0x5c,0x00);
++	}
++//	i2c_write(client, 0xa1,0x77);
++	i2c_write(client, 0xff,0x86);
++	i2c_write(client, 0x40,0x40); //tx_src_sel
++	/*port src sel*/
++	i2c_write(client, 0x41,0x34);
++	i2c_write(client, 0x42,0x10);
++	i2c_write(client, 0x43,0x23); //pt0_tx_src_sel
++	i2c_write(client, 0x44,0x41);
++	i2c_write(client, 0x45,0x02); //pt1_tx_src_scl
++}
++
++static void LT9211_Txpll(struct i2c_client *client)
++{
++	unsigned char loopx;
++
++	i2c_write(client, 0xff,0x82);
++	i2c_write(client, 0x36,0x01); //b7:txpll_pd
++	if( LVDS_PORTNUM == LVDS_1PORT ) {
++		i2c_write(client, 0x37,0x29);
++	} else {
++		i2c_write(client, 0x37,0x2a);
++	}
++	i2c_write(client, 0x38,0x06);
++	i2c_write(client, 0x39,0x30);
++	i2c_write(client, 0x3a,0x8e);
++	i2c_write(client, 0xff,0x87);
++	i2c_write(client, 0x37,0x14);
++	i2c_write(client, 0x13,0x00);
++	i2c_write(client, 0x13,0x80);
++	mdelay(100);
++	for(loopx = 0; loopx < 10; loopx++) //Check Tx PLL cal
++	{
++		i2c_write(client, 0xff,0x87);
++		if(i2c_read(client, 0x1f)& 0x80) {
++			if(i2c_read(client, 0x20)& 0x80) {
++				debug("LT9211 tx pll lock\n");
++			} else {
++				printk("LT9211 tx pll unlocked\n");
++			}
++			debug("LT9211 tx pll cal done\n");
++			break;
++		} else {
++			printk("LT9211 tx pll unlocked\n");
++		}
++	}
++}
++
++#ifdef DEBUG
++static void LT9211_LvdsClkDebug(struct i2c_client *client)
++{
++	unsigned int fm_value;
++
++	i2c_write(client, 0xff,0x86);
++	i2c_write(client, 0x00,0x12);
++	mdelay(100);
++	fm_value = 0;
++	fm_value = (i2c_read(client, 0x08) &(0x0f));
++	fm_value = (fm_value<<8) ;
++	fm_value = fm_value + i2c_read(client, 0x09);
++	fm_value = (fm_value<<8) ;
++	fm_value = fm_value + i2c_read(client, 0x0a);
++
++	printk("\033[33m lvds pixclk = %d |\033[0m\n", fm_value);
++}
++
++static void LT9211_MipiByteClkDebug(struct i2c_client *client)
++{
++	unsigned int fm_value;
++
++	i2c_write(client, 0xff,0x86);
++#ifdef INPUT_PORTA
++	i2c_write(client, 0x00,0x01);
++#endif
++#ifdef INPUT_PORTB
++	i2c_write(client, 0x00,0x02);
++#endif
++	mdelay(100);
++	fm_value = 0;
++	fm_value = (i2c_read(client, 0x08) &(0x0f));
++	fm_value = (fm_value<<8) ;
++	fm_value = fm_value + i2c_read(client, 0x09);
++	fm_value = (fm_value<<8) ;
++	fm_value = fm_value + i2c_read(client, 0x0a);
++	printk("\033[33m mipi byteclk = %d |\033[0m\n", fm_value);
++}
++
++static void LT9211_VideoCheckDebug(struct i2c_client *client)
++{
++	unsigned char sync_polarity;
++	unsigned short hact, vact;
++	unsigned short hs, vs;
++	unsigned short hbp, vbp;
++	unsigned short htotal, vtotal;
++	unsigned short hfp, vfp;
++
++	i2c_write(client, 0xff,0x86);
++	i2c_write(client, 0x20,0x00);
++
++	sync_polarity = i2c_read(client, 0x70);
++	vs = i2c_read(client, 0x71);
++
++	hs = i2c_read(client, 0x72);
++	hs = (hs<<8) + i2c_read(client, 0x73);
++
++	vbp = i2c_read(client, 0x74);
++	vfp = i2c_read(client, 0x75);
++
++	hbp = i2c_read(client, 0x76);
++	hbp = (hbp<<8) + i2c_read(client, 0x77);
++
++	hfp = i2c_read(client, 0x78);
++	hfp = (hfp<<8) + i2c_read(client, 0x79);
++
++	vtotal = i2c_read(client, 0x7A);
++	vtotal = (vtotal<<8) + i2c_read(client, 0x7B);
++
++	htotal = i2c_read(client, 0x7C);
++	htotal = (htotal<<8) + i2c_read(client, 0x7D);
++
++	vact = i2c_read(client, 0x7E);
++	vact = (vact<<8)+ i2c_read(client, 0x7F);
++
++	hact = i2c_read(client, 0x80);
++	hact = (hact<<8) + i2c_read(client, 0x81);
++
++	printk("sync_polarity = %x\n", sync_polarity);
++
++	printk("\033[33m hfp = %d , hs = %d , hbp = %d , hact = %d , htotal = %d\033[0m\n", hfp, hs, hbp, hact, htotal);
++
++	printk("\033[33m vfp = %d , vs = %d , vbp = %d , vact = %d , vtotal = %d\033[0m\n", vfp, vs, vbp, vact, vtotal);
++}
++#endif
++
++int LT9211_MIPI2LVDS_Config(struct i2c_client *client)
++{
++	int retry = 5;
++	int ret = 0;
++	debug("*************LT9211 MIPI2LVDS Config*************\n");
++#ifdef DEBUG
++	LT9211_ChipID(client);
++#endif
++	LT9211_SystemInt(client);
++	LT9211_MipiRxPhy(client);
++	LT9211_MipiRxDigital(client);
++
++	while(retry--)
++		if ((ret = LT9211_TimingSet(client)) == 0) break;
++
++	if( pVideo_Format != NULL )
++	{
++#ifdef DEBUG
++		LT9211_MipiByteClkDebug(client);
++#endif
++		LT9211_DesscPll(client);
++
++		retry = 5;
++		while(retry--)
++			if ((ret = LT9211_MipiPcr(client)) == 0) break;
++
++		LT9211_CSC(client);
++		/********LVDS OUTPUT CONFIG********/
++		LT9211_TxPhy(client);
++		LT9211_TxDigital(client);
++		LT9211_Txpll(client);
++
++#ifdef DEBUG
++//		 i2c_write(client, 0xff,0x85);
++//		 i2c_write(client, 0x88,0xC0); // debug: colorbar
++//		 i2c_write(client, 0xA1,0x04); // single color 0x1: blue, 0x2: green, 0x4: red.
++
++		LT9211_LvdsClkDebug(client);
++		LT9211_VideoCheckDebug(client);
++#endif
++	}
++	return ret;
++}
++
++////////////////////////////LT9211 end/////////////////////////////////////////////
++
++static struct panel_dev *lt9211_info;
++
++static void panel_enable(struct lcd_panel *panel)
++{
++}
++
++static void panel_disable(struct lcd_panel *panel)
++{
++}
++
++static struct lcd_panel_ops panel_ops = {
++	.enable  = (void*)panel_enable,
++	.disable = (void*)panel_disable,
++};
++
++static struct fb_videomode panel_modes = {
++	.name                   = "lt9211-G104X1L04",
++	.refresh                = FPS,
++	.xres                   = HACT,
++	.yres                   = VACT,
++	.left_margin            = HFP,
++	.right_margin           = HBP,
++	.upper_margin           = VFP,
++	.lower_margin           = VBP,
++
++	.hsync_len              = HS,
++	.vsync_len              = VS,
++	.sync                   = FB_SYNC_HOR_HIGH_ACT & FB_SYNC_VERT_HIGH_ACT,
++	.vmode                  = FB_VMODE_NONINTERLACED,
++	.flag                   = 0,
++};
++
++struct jzdsi_data jzdsi_pdata = {
++	.modes = &panel_modes,
++	.video_config.no_of_lanes = 2,
++	.video_config.virtual_channel = 0,
++	.video_config.color_coding = COLOR_CODE_24BIT,
++	.video_config.video_mode = VIDEO_BURST_WITH_SYNC_PULSES,
++	.video_config.receive_ack_packets = 0,	/* enable receiving of ack packets */
++	.video_config.is_18_loosely = 0,
++	.video_config.data_en_polarity = 1,
++	.video_config.byte_clock = 0, // driver will auto calculate byte_clock.
++	.video_config.byte_clock_coef = MIPI_PHY_BYTE_CLK_COEF_MUL1,
++
++	.dsi_config.max_lanes = 2,
++	.dsi_config.max_hs_to_lp_cycles = 100,
++	.dsi_config.max_lp_to_hs_cycles = 40,
++	.dsi_config.max_bta_cycles = 4095,
++	.dsi_config.color_mode_polarity = 1,
++	.dsi_config.shut_down_polarity = 1,
++	.dsi_config.max_bps = 2750,
++	.bpp_info = 24,
++};
++
++static struct tft_config kd050hdfia019_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++struct lcd_panel lcd_panel[] = {
++	[0] = {
++		.name = "G104X1L04",
++		.modes = &panel_modes,
++		.num_modes = 1,
++		.dsi_pdata = &jzdsi_pdata,
++
++		.bpp = 24,
++		.width = 699,
++		.height = 197,
++
++		.lcd_type = LCD_TYPE_MIPI_TFT,
++
++		.tft_config = &kd050hdfia019_cfg,
++		.dsi_pdata = &jzdsi_pdata,
++
++		.dither_enable = 0,
++		.dither.dither_red = 0,
++		.dither.dither_green = 0,
++		.dither.dither_blue = 0,
++
++		.ops = &panel_ops,
++	},
++};
++
++static unsigned char i2c_read(struct i2c_client *client, unsigned char addr)
++{
++	return i2c_smbus_read_byte_data(client, addr);
++}
++
++static unsigned int i2c_write(struct i2c_client *client,unsigned char addr,unsigned char value)
++{
++	return i2c_smbus_write_byte_data(client, addr, value);
++}
++
++void lt9211_reset(struct panel_dev *lt9211_info)
++{
++	struct board_gpio *rst = &lt9211_info->reset;
++
++	gpio_direction_output(rst->gpio, 1);
++	mdelay(1);
++	gpio_direction_output(rst->gpio, 0);
++	mdelay(100);
++	gpio_direction_output(rst->gpio, 1);
++	mdelay(100);
++}
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	struct panel_dev *lt9211_info = lcd_get_data(lcd);
++	struct i2c_client *client = lt9211_info->client;
++
++	struct board_gpio *lcd_en = &lt9211_info->lcd_en;
++	struct board_gpio *bl_en = &lt9211_info->bl_en;
++	struct board_gpio *rst = &lt9211_info->reset;
++
++	if(POWER_IS_ON(power) && !POWER_IS_ON(lt9211_info->power)) {
++		gpio_direction_output(rst->gpio, 0);
++		gpio_direction_output(lcd_en->gpio, 1);
++		mdelay(15);
++
++		lt9211_reset(lt9211_info);
++		if (LT9211_MIPI2LVDS_Config(client))
++			return -1;
++
++	    gpio_direction_output(bl_en->gpio, 1);
++	}
++	if(!POWER_IS_ON(power) && POWER_IS_ON(lt9211_info->power)) {
++		gpio_direction_output(bl_en->gpio, 0);
++		gpio_direction_output(lcd_en->gpio, 0);
++	}
++
++	lt9211_info->power = power;
++	return 0;
++}
++
++int panel_bridge_init(void)
++{
++	int ret = 0;
++	struct i2c_client *client = lt9211_info->client;
++
++	ret = LT9211_MIPI2LVDS_Config(client);
++
++	return ret;
++}
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *lt9211_info = lcd_get_data(lcd);
++
++	return lt9211_info->power;
++}
++
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++
++int _of_get_named_gpio_lvl(struct device *dev, short *gpio, short *lvl, char *of_name)
++{
++	int ret = 0;
++	enum of_gpio_flags flags;
++
++	/* devm_gpio_request_one */
++	*gpio = of_get_named_gpio_flags(dev->of_node, of_name, 0, &flags);
++	if(gpio_is_valid(*gpio)) {
++		*lvl = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(*gpio, GPIOF_DIR_OUT, of_name);
++		if(ret < 0) {
++			dev_err(dev, "Failed to request reset pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio: %s\n", of_name);
++		return -1;
++	}
++	return 0;
++}
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *lt9211_info = dev_get_drvdata(dev);
++	int ret = 0;
++
++
++	if ((ret = _of_get_named_gpio_lvl(dev,
++				&lt9211_info->reset.gpio,
++				&lt9211_info->reset.active_level,
++				"lt9211,reset-gpio")))
++		return ret;
++
++	if ((ret = _of_get_named_gpio_lvl(dev,
++				&lt9211_info->lcd_en.gpio,
++				&lt9211_info->lcd_en.active_level,
++				"lt9211,lcd_en-gpio")))
++		goto err_request_reset;
++
++	if ((ret = _of_get_named_gpio_lvl(dev,
++				&lt9211_info->bl_en.gpio,
++				&lt9211_info->bl_en.active_level,
++				"lt9211,bl_en-gpio")))
++		goto err_request_reset;
++
++	/* devm_ */
++
++	return 0;
++err_request_reset:
++	if(gpio_is_valid(lt9211_info->reset.gpio))
++		gpio_free(lt9211_info->reset.gpio);
++	return ret;
++}
++#if 0
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int panel_suspend(struct device *dev)
++{
++	struct panel_dev *lt9211_info = dev_get_drvdata(dev);
++
++	panel_set_power(lt9211_info->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++static int panel_resume(struct device *dev)
++{
++	struct panel_dev *lt9211_info = dev_get_drvdata(dev);
++
++	panel_set_power(lt9211_info->lcd, FB_BLANK_UNBLANK);
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++#endif
++
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,G104X1L04", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "G104X1L04",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++#endif
++
++static struct mipi_dsim_lcd_driver panel_dev_dsim_ddi_driver = {
++	.name = "lt9211-G104X1L04",
++	.id = -1,
++
++	/* .power_on = panel_dev_power_on, */
++	/* .set_sequence = panel_dev_set_sequence, */
++	/* .probe = panel_dev_probe, */
++	/* .suspend = panel_suspend, */
++	/* .resume = panel_resume, */
++};
++
++
++struct mipi_dsim_lcd_device panel_dev_device={
++	.name		= "lt9211-G104X1L04",
++	.id = 0,
++};
++
++static int lt9211_probe(struct i2c_client *client, const struct i2c_device_id *id)
++{
++	int ret = 0, i;
++	struct device *dev = &client->dev;
++	struct device_node *np = dev->of_node;
++
++	lt9211_info = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(lt9211_info == NULL) {
++		dev_err(dev, "Failed to alloc memory!");
++		return -ENOMEM;
++	}
++	lt9211_info->dev = dev;
++	lt9211_info->client = client;
++	dev_set_drvdata(dev, lt9211_info);
++
++	// set dev_info.
++	ret = of_panel_parse(dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	// register lcd device.
++	lt9211_info->lcd = lcd_device_register("panel_lcd", dev, lt9211_info, &panel_lcd_ops);
++	if(IS_ERR_OR_NULL(lt9211_info->lcd)) {
++		dev_err(dev, "Error register lcd!\n");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++	of_property_read_string(np, "lt9211,panel_name", (const char**)&lt9211_info->panel_name);
++
++	if (lt9211_info->panel_name) {
++		for (i = 0; i < ARRAY_SIZE(lcd_panel); ++i) {
++			if (strcmp(lcd_panel[i].name, lt9211_info->panel_name) == 0)
++				break;
++		}
++		if (i == ARRAY_SIZE(lcd_panel)) {
++			printk("\033[31munsupport panel!\033[0m\n");
++			goto err_lcd_register;
++		}
++	} else {
++		printk("\033[31mno found specid lcd panel!\033[0m\n");
++		goto err_lcd_register;
++	}
++
++	mipi_dsi_register_lcd_device(&panel_dev_device);
++	mipi_dsi_register_lcd_driver(&panel_dev_dsim_ddi_driver);
++
++	ret = ingenicfb_register_panel(&lcd_panel[i]);
++	if(ret < 0) {
++		dev_err(dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++
++	// register ingenicfb device.
++	/* TODO: should this power status sync from uboot */
++	lt9211_info->power = FB_BLANK_POWERDOWN;
++	if (panel_set_power(lt9211_info->lcd, FB_BLANK_UNBLANK))
++		goto err_lcd_register;
++
++	printk("\033[32mregister %s sucess.\033[0m\n", lt9211_info->panel_name);
++
++	return 0;
++
++err_lcd_register:
++	lcd_device_unregister(lt9211_info->lcd);
++err_of_parse:
++	kfree(lt9211_info);
++	printk("\033[31mregister %s dailed.\033[0m\n", lt9211_info->panel_name);
++	return ret;
++}
++
++static int lt9211_remove(struct i2c_client *client)
++{
++	struct panel_dev *lt9211_info = dev_get_drvdata(&client->dev);
++
++	panel_set_power(lt9211_info->lcd, FB_BLANK_POWERDOWN);
++
++	return 0;
++}
++
++#ifdef CONFIG_OF
++static const struct of_device_id lt9211_match_table[] = {
++		{.compatible = "mipi2lvds,lt9211",},
++		{ },
++};
++MODULE_DEVICE_TABLE(of, lt9211_match_table);
++#endif
++
++static const struct i2c_device_id lt9211_id[] = {
++	{ "lt9211", },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, lt9211_id);
++
++static struct i2c_driver lt9211_driver = {
++    .probe      = lt9211_probe,
++    .remove     = lt9211_remove,
++    .driver = {
++        .name     = "lt9211",
++        .owner    = THIS_MODULE,
++#ifdef CONFIG_OF
++		.of_match_table = of_match_ptr(lt9211_match_table),
++#endif
++    },
++	.id_table = lt9211_id,
++};
++
++static int __init lt9211_init(void)
++{
++	int ret;
++	printk("\033[33m%s\033[0m\n", "lt9211 driver installing...");
++	ret = i2c_add_driver(&lt9211_driver);
++    if ( ret != 0 ) {
++        printk("lt9211 driver init failed!\n");
++    }
++
++    return ret;
++}
++
++static void __exit lt9211_exit(void)
++{
++	printk("lt9211 driver exited.\n");
++	i2c_del_driver(&lt9211_driver);
++}
++
++/* module_i2c_driver(lt9211_driver); */
++module_init(lt9211_init);
++module_exit(lt9211_exit);
++
++MODULE_DESCRIPTION("LT9211 Driver");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-MV238FHM-N30.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-MV238FHM-N30.c
+new file mode 100644
+index 000000000..8b1429956
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-MV238FHM-N30.c
+@@ -0,0 +1,416 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-ylym286a.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++
++#include "../ingenicfb.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct i2c_client *client;
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	int power;
++
++	struct board_gpio reset;
++	struct board_gpio lcd_en;
++	char *panel_name;
++};
++#if 1
++//#define FPS    60
++#define FPS    30
++#define HACT   1920
++#define VACT   1080
++
++#define HFP    88
++#define HBP    148
++#define HS     44
++
++#define VFP    4
++#define VBP    36
++#define VS     5
++#endif
++
++#if 0
++#define FPS    20
++//#define FPS    30
++#define HACT   1920
++#define VACT   1080
++
++#define HFP    70
++#define HBP    70
++#define HS     44
++
++#define VFP    4
++#define VBP    36
++#define VS     5
++#endif
++
++#include "lt9211.c"
++
++static struct panel_dev *lt9211_info;
++
++static void panel_enable(struct lcd_panel *panel)
++{
++}
++
++static void panel_disable(struct lcd_panel *panel)
++{
++}
++
++static struct lcd_panel_ops panel_ops = {
++	.enable  = (void*)panel_enable,
++	.disable = (void*)panel_disable,
++};
++
++static struct fb_videomode panel_modes = {
++	.name                   = "lt9211-MV238FHM-N30",
++	.refresh                = FPS,
++	.xres                   = HACT,
++	.yres                   = VACT,
++	.left_margin            = HFP,
++	.right_margin           = HBP,
++	.upper_margin           = VFP,
++	.lower_margin           = VBP,
++
++	.hsync_len              = HS,
++	.vsync_len              = VS,
++	.sync                   = FB_SYNC_HOR_HIGH_ACT & FB_SYNC_VERT_HIGH_ACT,
++	.vmode                  = FB_VMODE_NONINTERLACED,
++	.flag                   = 0,
++};
++
++struct jzdsi_data jzdsi_pdata = {
++	.modes = &panel_modes,
++	.video_config.no_of_lanes = 2,
++	.video_config.virtual_channel = 0,
++	.video_config.color_coding = COLOR_CODE_24BIT,
++	.video_config.video_mode = VIDEO_BURST_WITH_SYNC_PULSES,
++	.video_config.receive_ack_packets = 0,	/* enable receiving of ack packets */
++	.video_config.is_18_loosely = 0,
++	.video_config.data_en_polarity = 1,
++	.video_config.byte_clock = 0, // driver will auto calculate byte_clock.
++	.video_config.byte_clock_coef = MIPI_PHY_BYTE_CLK_COEF_MUL1,
++
++	.dsi_config.max_lanes = 2,
++	.dsi_config.max_hs_to_lp_cycles = 100,
++	.dsi_config.max_lp_to_hs_cycles = 40,
++	.dsi_config.max_bta_cycles = 4095,
++	.dsi_config.color_mode_polarity = 1,
++	.dsi_config.shut_down_polarity = 1,
++	.dsi_config.max_bps = 2750,
++	.bpp_info = 24,
++};
++
++static struct tft_config kd050hdfia019_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++struct lcd_panel lcd_panel[] = {
++	[0] = {
++		.name = "MV238FHM-N30",
++		.modes = &panel_modes,
++		.num_modes = 1,
++		.dsi_pdata = &jzdsi_pdata,
++
++		.bpp = 24,
++		.width = 1920,
++		.height = 1080,
++
++		.lcd_type = LCD_TYPE_MIPI_TFT,
++
++		.tft_config = &kd050hdfia019_cfg,
++
++		.dither_enable = 0,
++		.dither.dither_red = 0,
++		.dither.dither_green = 0,
++		.dither.dither_blue = 0,
++
++		.ops = &panel_ops,
++	},
++};
++
++static unsigned char i2c_read(struct i2c_client *client, unsigned char addr)
++{
++	return i2c_smbus_read_byte_data(client, addr);
++}
++
++static unsigned int i2c_write(struct i2c_client *client,unsigned char addr,unsigned char value)
++{
++	return i2c_smbus_write_byte_data(client, addr, value);
++}
++
++void lt9211_reset(struct panel_dev *lt9211_info)
++{
++	struct board_gpio *rst = &lt9211_info->reset;
++
++	gpio_direction_output(rst->gpio, 1);
++	mdelay(1);
++	gpio_direction_output(rst->gpio, 0);
++	mdelay(100);
++	gpio_direction_output(rst->gpio, 1);
++	mdelay(100);
++}
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	struct panel_dev *lt9211_info = lcd_get_data(lcd);
++	struct i2c_client *client = lt9211_info->client;
++
++//	struct board_gpio *lcd_en = &lt9211_info->lcd_en;
++	struct board_gpio *rst = &lt9211_info->reset;
++
++	if(POWER_IS_ON(power) && !POWER_IS_ON(lt9211_info->power)) {
++//		gpio_direction_output(lcd_en->gpio, 1);
++
++		lt9211_reset(lt9211_info);
++		if (LT9211_MIPI2LVDS_Config(client))
++			return -1;
++	}
++//	if(!POWER_IS_ON(power) && POWER_IS_ON(lt9211_info->power)) {
++//		gpio_direction_output(lcd_en->gpio, 0);
++//	}
++
++	lt9211_info->power = power;
++	return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *lt9211_info = lcd_get_data(lcd);
++
++	return lt9211_info->power;
++}
++
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++
++int _of_get_named_gpio_lvl(struct device *dev, short *gpio, short *lvl, char *of_name)
++{
++	int ret = 0;
++	enum of_gpio_flags flags;
++
++	/* devm_gpio_request_one */
++	*gpio = of_get_named_gpio_flags(dev->of_node, of_name, 0, &flags);
++	if(gpio_is_valid(*gpio)) {
++		*lvl = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(*gpio, GPIOF_DIR_OUT, of_name);
++		if(ret < 0) {
++			dev_err(dev, "Failed to request reset pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio: %s\n", of_name);
++		return -1;
++	}
++	return 0;
++}
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *lt9211_info = dev_get_drvdata(dev);
++	int ret = 0;
++
++	if ((ret = _of_get_named_gpio_lvl(dev,
++				&lt9211_info->reset.gpio,
++				&lt9211_info->reset.active_level,
++				"lt9211,reset-gpio")))
++		return ret;
++#if 0
++	if ((ret = _of_get_named_gpio_lvl(dev,
++				&lt9211_info->lcd_en.gpio,
++				&lt9211_info->lcd_en.active_level,
++				"lt9211,lcd_en-gpio")))
++		goto err_request_reset;
++#endif
++	/* devm_ */
++
++	return 0;
++err_request_reset:
++	if(gpio_is_valid(lt9211_info->reset.gpio))
++		gpio_free(lt9211_info->reset.gpio);
++	return ret;
++}
++
++static struct mipi_dsim_lcd_driver panel_dev_dsim_ddi_driver = {
++	.name = "lt9211-MV238FHM-N30",
++	.id = -1,
++
++	/* .power_on = panel_dev_power_on, */
++	/* .set_sequence = panel_dev_set_sequence, */
++	/* .probe = panel_dev_probe, */
++	/* .suspend = panel_suspend, */
++	/* .resume = panel_resume, */
++};
++
++
++struct mipi_dsim_lcd_device panel_dev_device={
++	.name		= "lt9211-MV238FHM-N30",
++	.id = 0,
++};
++
++static int lt9211_probe(struct i2c_client *client, const struct i2c_device_id *id)
++{
++	int ret = 0, i;
++	struct device *dev = &client->dev;
++	struct device_node *np = dev->of_node;
++
++	lt9211_info = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(lt9211_info == NULL) {
++		dev_err(dev, "Failed to alloc memory!");
++		return -ENOMEM;
++	}
++	lt9211_info->dev = dev;
++	lt9211_info->client = client;
++	dev_set_drvdata(dev, lt9211_info);
++
++	// set dev_info.
++	ret = of_panel_parse(dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	// register lcd device.
++	lt9211_info->lcd = lcd_device_register("panel_lcd", dev, lt9211_info, &panel_lcd_ops);
++	if(IS_ERR_OR_NULL(lt9211_info->lcd)) {
++		dev_err(dev, "Error register lcd!\n");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++	of_property_read_string(np, "lt9211,panel_name", (const char**)&lt9211_info->panel_name);
++
++	if (lt9211_info->panel_name) {
++		for (i = 0; i < ARRAY_SIZE(lcd_panel); ++i) {
++			if (strcmp(lcd_panel[i].name, lt9211_info->panel_name) == 0)
++				break;
++		}
++		if (i == ARRAY_SIZE(lcd_panel)) {
++			printk("\033[31munsupport panel!\033[0m\n");
++			goto err_lcd_register;
++		}
++	} else {
++		printk("\033[31mno found specid lcd panel!\033[0m\n");
++		goto err_lcd_register;
++	}
++
++	mipi_dsi_register_lcd_device(&panel_dev_device);
++	mipi_dsi_register_lcd_driver(&panel_dev_dsim_ddi_driver);
++
++	ret = ingenicfb_register_panel(&lcd_panel[i]);
++	if(ret < 0) {
++		dev_err(dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++
++	// register ingenicfb device.
++	/* TODO: should this power status sync from uboot */
++	lt9211_info->power = FB_BLANK_POWERDOWN;
++	if (panel_set_power(lt9211_info->lcd, FB_BLANK_UNBLANK))
++		goto err_lcd_register;
++
++	printk("\033[32mregister %s sucess.\033[0m\n", lt9211_info->panel_name);
++
++	return 0;
++
++err_lcd_register:
++	lcd_device_unregister(lt9211_info->lcd);
++err_of_parse:
++	kfree(lt9211_info);
++	printk("\033[31mregister %s dailed.\033[0m\n", lt9211_info->panel_name);
++	return ret;
++}
++
++static int lt9211_remove(struct i2c_client *client)
++{
++	struct panel_dev *lt9211_info = dev_get_drvdata(&client->dev);
++
++	panel_set_power(lt9211_info->lcd, FB_BLANK_POWERDOWN);
++
++	return 0;
++}
++
++#ifdef CONFIG_OF
++static const struct of_device_id lt9211_match_table[] = {
++		{.compatible = "mipi2lvds,lt9211",},
++		{ },
++};
++MODULE_DEVICE_TABLE(of, lt9211_match_table);
++#endif
++
++static const struct i2c_device_id lt9211_id[] = {
++	{ "lt9211", },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, lt9211_id);
++
++static struct i2c_driver lt9211_driver = {
++    .probe      = lt9211_probe,
++    .remove     = lt9211_remove,
++    .driver = {
++        .name     = "lt9211",
++        .owner    = THIS_MODULE,
++#ifdef CONFIG_OF
++		.of_match_table = of_match_ptr(lt9211_match_table),
++#endif
++    },
++	.id_table = lt9211_id,
++};
++
++static int __init lt9211_init(void)
++{
++	int ret;
++	printk("\033[33m%s\033[0m\n", "lt9211 driver installing...");
++	ret = i2c_add_driver(&lt9211_driver);
++    if ( ret != 0 ) {
++        printk("lt9211 driver init failed!\n");
++    }
++
++    return ret;
++}
++
++static void __exit lt9211_exit(void)
++{
++	printk("lt9211 driver exited.\n");
++	i2c_del_driver(&lt9211_driver);
++}
++
++/* module_i2c_driver(lt9211_driver); */
++module_init(lt9211_init);
++module_exit(lt9211_exit);
++
++MODULE_DESCRIPTION("LT9211 Driver");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-atk7016.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-atk7016.c
+new file mode 100644
+index 000000000..05ac83cf5
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-atk7016.c
+@@ -0,0 +1,309 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-atk7016.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++
++#include "../ingenicfb.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio pwm;
++};
++
++static void panel_enable(struct lcd_panel *panel)
++{
++}
++
++static void panel_disable(struct lcd_panel *panel)
++{
++}
++
++static struct lcd_panel_ops panel_ops = {
++	.enable  = (void*)panel_enable,
++	.disable = (void*)panel_disable,
++};
++
++static struct fb_videomode panel_modes[] = {
++	[0] = {
++		.name                   = "1024x600",
++		.refresh                = 50,
++		.xres                   = 1024,
++		.yres                   = 600,
++//		.pixclock               = KHZ2PICOS(33264),
++		.left_margin            = 140,
++		.right_margin           = 160,
++		.upper_margin           = 20,
++		.lower_margin           = 12,
++
++		.hsync_len              = 20,
++		.vsync_len              = 3,
++		.sync                   = ~FB_SYNC_HOR_HIGH_ACT & ~FB_SYNC_VERT_HIGH_ACT,
++		.vmode                  = FB_VMODE_NONINTERLACED,
++		.flag                   = 0,
++	},
++};
++
++static struct tft_config atk7016_cfg = {
++	.pix_clk_inv = 1,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_BGR,
++	.color_odd = TFT_LCD_COLOR_ODD_BGR,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++struct lcd_panel lcd_panel = {
++	.name = "atk7016",
++	.num_modes = ARRAY_SIZE(panel_modes),
++	.modes = panel_modes,
++	.bpp = 24,
++	.width = 1024,
++	.height = 600,
++
++	.lcd_type = LCD_TYPE_TFT,
++
++	.tft_config = &atk7016_cfg,
++
++	.dither_enable = 1,
++	.dither.dither_red = 1,
++	.dither.dither_green = 1,
++	.dither.dither_blue = 1,
++
++	.ops = &panel_ops,
++};
++
++#define POWER_IS_ON(pwr)        (pwr)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++//	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++	/*struct board_gpio *pwm = &panel->pwm;*/
++    printk("%s, %d, power = %d, panel power = %d\n", __func__, __LINE__, power, panel->power);
++
++	if(POWER_IS_ON(power) && !POWER_IS_ON(panel->power)) {
++    printk("%s, %d, power = %d\n", __func__, __LINE__, power);
++		/*gpio_direction_output(pwm->gpio, 1);*/
++//		gpio_direction_output(vdd_en->gpio, 0);
++	}
++	if(!POWER_IS_ON(power) && POWER_IS_ON(panel->power)) {
++    printk("%s, %d, power = %d\n", __func__, __LINE__, power);
++//		gpio_direction_output(vdd_en->gpio, 1);
++		gpio_direction_output(rst->gpio, 1);
++	}
++
++	panel->power = power;
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++* @ panel_atk7016_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++#if 0
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->vdd_en.gpio, GPIOF_DIR_OUT, "vdd_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++#endif
++    
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++#if 0
++	panel->pwm.gpio = of_get_named_gpio_flags(np, "ingenic,pwm-gpio", 0, &flags);
++	if(gpio_is_valid(panel->pwm.gpio)) {
++		panel->pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->pwm.gpio, GPIOF_DIR_OUT, "pwm");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request pwm pin!\n");
++			goto err_request_pwm;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio pwm.gpio: %d\n", panel->pwm.gpio);
++	}
++#endif
++
++	return 0;
++err_request_pwm:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++err_request_rst:
++/*
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++*/
++	return ret;
++}
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	struct panel_dev *panel;
++	struct backlight_properties props;
++
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	panel->lcd = lcd_device_register("panel_lcd", &pdev->dev, panel, &panel_lcd_ops);
++	if(IS_ERR_OR_NULL(panel->lcd)) {
++		dev_err(&pdev->dev, "Error register lcd!\n");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++
++	/* TODO: should this power status sync from uboot */
++	panel->power = FB_BLANK_POWERDOWN;
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++
++	return 0;
++
++err_lcd_register:
++	lcd_device_unregister(panel->lcd);
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	struct panel_dev *panel = dev_get_drvdata(&pdev->dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int panel_suspend(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++static int panel_resume(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++#endif
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,atk7016", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "atk7016",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-bm8766.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-bm8766.c
+new file mode 100644
+index 000000000..83156fd5c
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-bm8766.c
+@@ -0,0 +1,310 @@
++/*
++ * ingenic_bsp/chip-x2000/fpga/dpu/bm8766.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * Author:clwang<chunlei.wang@ingenic.com>
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++#include <soc/gpio.h>
++
++#include "../ingenicfb.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio bl;
++	struct board_gpio rst;
++	struct board_gpio pwm;
++};
++
++static struct panel_dev *panel;
++
++static void bm8766_power_on(struct lcd_panel *ppanel)
++{
++	struct panel_dev *panel_bm8766 = dev_get_drvdata(panel->dev);
++
++	gpio_direction_output(panel_bm8766->bl.gpio, panel_bm8766->bl.active_level);
++}
++
++static void bm8766_power_off(struct lcd_panel *ppanel)
++{
++	struct panel_dev *panel_bm8766 = dev_get_drvdata(panel->dev);
++
++	gpio_direction_output(panel_bm8766->bl.gpio, !panel_bm8766->bl.active_level);
++	return;
++}
++
++static struct lcd_panel_ops bm8766_ops = {
++	.enable  = (void*)bm8766_power_on,
++	.disable = (void*)bm8766_power_off,
++};
++
++static struct fb_videomode jzfb_bm8766_videomode[] = {
++	[0] = {
++		.name = "800x480",
++		.refresh = 30,
++		//.refresh = 60,
++		.xres = 800,
++		.yres = 480,
++		.pixclock = KHZ2PICOS(16632),
++		//.pixclock = KHZ2PICOS(33264),
++		.left_margin = 88,
++		.right_margin = 40,
++		.upper_margin = 8,
++		.lower_margin = 35,
++		.hsync_len = 128,
++		.vsync_len = 2,
++		.sync = ~FB_SYNC_HOR_HIGH_ACT & ~FB_SYNC_VERT_HIGH_ACT,
++		.vmode = FB_VMODE_NONINTERLACED,
++		.flag = 0,
++	},
++};
++
++static struct tft_config bm8766_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_BGR,
++	.color_odd = TFT_LCD_COLOR_ODD_BGR,
++	.mode = TFT_LCD_MODE_PARALLEL_666,
++};
++
++struct lcd_panel lcd_panel = {
++	.name = "bm8766",
++	.num_modes = ARRAY_SIZE(jzfb_bm8766_videomode),
++	.modes = jzfb_bm8766_videomode,
++	.lcd_type = LCD_TYPE_TFT,
++	.bpp = 24,
++	.width = 800,
++	.height = 480,
++
++	.tft_config = &bm8766_cfg,
++
++	/*T40 RGB real line is 666, so, for RGB888, we discard low 2 bytes, config as follows:*/
++	.dither_enable = 1,
++	.dither.dither_red = 1,
++	.dither.dither_green = 1,
++	.dither.dither_blue = 1,
++
++	.ops = &bm8766_ops,
++};
++
++#if 0
++static int panel_update_status(struct backlight_device *bd)
++{
++	struct panel_dev *panel = dev_get_drvdata(&bd->dev);
++	int brightness = bd->props.brightness;
++	unsigned int i;
++	int pulse_num = MAX_BRIGHTNESS_STEP - brightness / CONVERT_FACTOR - 1;
++
++	if (FB_BLANK_POWERDOWN == bd->pros.fb_blank)
++		return 0;
++
++	if (bd->props.state & BL_CORE_SUSPEND)
++		brightness = 0;
++
++	if (brightness) {
++		gpio_direction_output(panel->pwm.gpio, 0);
++		udelay(5000);
++		gpio_direction_output(panel->pwm.gpio, 1);
++		udelay(100);
++
++		for (i = pulse_num; i > 0 ; i--) {
++			gpio_direction_output(panel->pwm.gpio, 0);
++			udelay(1);
++			gpio_direction_output(panel->pwm.gpio, 1);
++			udelay(3);
++		}
++	} else
++		gpio_direction_output(panel->pwm.gpio, 0);
++
++	return 0;
++}
++
++static struct backlight_ops panel_backlight_ops = {
++	.options = BL_CORE_SUSPENDRESUME,
++	.update_status = panel_update_status,
++};
++#endif
++
++#define RESET(n)\
++	gpio_direction_output(panel->rst.gpio, n)
++#define POWER_IS_ON(pwr)     ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++ * @ panel_bm8766_lcd_ops, register to kernel common backlight/lcd.c frameworks.
++ */
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->bl.gpio = of_get_named_gpio_flags(np, "gpios", 0, &flags);
++	if (gpio_is_valid(panel->bl.gpio)) {
++		panel->bl.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = devm_gpio_request(dev, panel->bl.gpio, "backlight");
++		if (ret < 0) {
++			dev_err(dev, "Failed to request backlight pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio backlight.gpio: %d\n", panel->bl.gpio);
++	}
++
++	return 0;
++}
++
++/**
++ * @panel_probe
++ *
++ *	1. register to ingenicfb.
++ *	2. register to lcd.
++ *	3. register to backlight if possible.
++ *
++ *	@pdev
++ *
++ *	@return -
++ * */
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	struct backlight_properties props;   //backlight properties
++
++	memset(&props, 0, sizeof(props));
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if (NULL == panel) {
++		dev_err(&pdev->dev, "Failed to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	/* panel pinctrl parse */
++	ret = of_panel_parse(&pdev->dev);
++	if (ret < 0) {
++		goto err_of_parse;
++	}
++
++	panel->lcd = lcd_device_register("panel_lcd", &pdev->dev, panel, &panel_lcd_ops);
++	if (IS_ERR_OR_NULL(panel->lcd)) {
++		dev_err(&pdev->dev, "Error register lcd!");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++	/* TODO: should this power status sync from uboot */
++	panel->power = FB_BLANK_POWERDOWN;
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++
++	return 0;
++
++err_lcd_register:
++	lcd_device_unregister(panel->lcd);
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	struct panel_dev *panel = dev_get_drvdata(&pdev->dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int panel_suspend(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++static int panel_resume(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++#endif
++
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,bm8766", },
++	{ .compatible = "bm8766", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe = panel_probe,
++	.remove = panel_remove,
++	.driver = {
++		.name = "bm8766",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-ek79007ad.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-ek79007ad.c
+new file mode 100644
+index 000000000..c24b61edc
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-ek79007ad.c
+@@ -0,0 +1,462 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-ek79007ad.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++#include <linux/fb.h>
++#include <linux/backlight.h>
++
++
++#include "../ingenicfb.h"
++#include "../jz_dsim.h"
++
++static int test = 0;
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio lcd_pwm;
++	struct board_gpio stbyb;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++};
++
++struct panel_dev *panel;
++
++#define lcd_to_master(a)	(a->dsim_dev->master)
++#define lcd_to_master_ops(a)	((lcd_to_master(a))->master_ops)
++
++struct ek79007ad {
++	struct device *dev;
++	unsigned int power;
++	unsigned int id;
++
++	struct lcd_device *ld;
++	struct backlight_device *bd;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++
++};
++
++static struct dsi_cmd_packet fitipower_ek79007ad_1080_600_cmd_list[] =
++{
++	{0x15, 0x80, 0x88},
++	{0x15, 0x81, 0x78},
++	{0x15, 0x82, 0x84},
++	{0x15, 0x83, 0x88},
++	{0x15, 0x84, 0xA8},
++	{0x15, 0x85, 0x83},
++	{0x15, 0x86, 0x88},
++	{0x15, 0xb2, 0x10},
++
++};
++
++
++static void panel_dev_sleep_in(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x10, 0x00};
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_sleep_out(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x11, 0x00};
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_display_on(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);//color bar turn off 0x29 command.
++	struct dsi_cmd_packet data_to_send = {0x05, 0x29, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_display_off(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x28, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++
++static void panel_dev_panel_init(struct panel_dev *lcd)
++{
++	int  i;
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_device *dsi = lcd_to_master(lcd);
++	for (i = 0; i < ARRAY_SIZE(fitipower_ek79007ad_1080_600_cmd_list); i++)
++	{
++		ops->cmd_write(dsi,  fitipower_ek79007ad_1080_600_cmd_list[i]);
++	}
++}
++
++static int panel_dev_ioctl(struct mipi_dsim_lcd_device *dsim_dev, int cmd)
++{
++	return 0;
++}
++static void panel_dev_set_sequence(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct ek79007ad *lcd = dev_get_drvdata(&dsim_dev->dev);
++
++	if(test != 0)
++		return;
++	test++;
++
++	panel_dev_panel_init(panel);
++	panel_dev_sleep_out(panel);
++	msleep(120);
++	panel_dev_display_on(panel);
++	msleep(5);
++	/* dump_dsi_reg(dsi); */
++	lcd->power = FB_BLANK_UNBLANK;
++}
++static void panel_dev_power_on(struct mipi_dsim_lcd_device *dsim_dev, int power)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++	struct board_gpio *stbyb = &panel->stbyb;
++
++	if(test != 0)
++		return;
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	gpio_direction_output(stbyb->gpio, stbyb->active_level);
++
++	msleep(50);
++	gpio_direction_output(rst->gpio, 0);
++	msleep(50);
++	gpio_direction_output(rst->gpio, 1);
++	msleep(120);
++
++	panel->power = power;
++}
++
++static struct fb_videomode panel_modes = {
++	.name = "fitipower_ek79007ad-lcd",
++	.xres = 1024,
++	.yres = 600,
++
++	.refresh = 60,
++
++	.left_margin = 160,//hbp
++	.right_margin = 160,//hfp
++	.hsync_len = 10, //hsync
++
++	.upper_margin = 23,//vbp
++	.lower_margin = 12,//vfp
++	.vsync_len = 1, //vsync
++
++	.sync                   = FB_SYNC_HOR_HIGH_ACT & FB_SYNC_VERT_HIGH_ACT,
++	.vmode                  = FB_VMODE_NONINTERLACED,
++	.flag = 0,
++};
++
++struct jzdsi_data jzdsi_pdata = {
++	.modes = &panel_modes,
++	.video_config.no_of_lanes = 2,
++	.video_config.virtual_channel = 0,
++	.video_config.color_coding = COLOR_CODE_24BIT,
++	.video_config.video_mode = VIDEO_BURST_WITH_SYNC_PULSES,
++	.video_config.receive_ack_packets = 0,	/* enable receiving of ack packets */
++	.video_config.is_18_loosely = 0,
++	.video_config.data_en_polarity = 1,
++	.video_config.byte_clock = 0, // driver will auto calculate byte_clock.
++	.video_config.byte_clock_coef = MIPI_PHY_BYTE_CLK_COEF_MUL3_DIV2, // byte_clock *3/2.
++
++	.dsi_config.max_lanes = 2,
++	.dsi_config.max_hs_to_lp_cycles = 100,
++	.dsi_config.max_lp_to_hs_cycles = 40,
++	.dsi_config.max_bta_cycles = 4095,
++	.dsi_config.color_mode_polarity = 1,
++	.dsi_config.shut_down_polarity = 1,
++	.dsi_config.max_bps = 2750,
++//	.max_bps = 650,  // 650 Mbps
++	.bpp_info = 24,
++};
++static struct tft_config kd050hdfia019_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++
++struct lcd_panel lcd_panel = {
++	.num_modes = 1,
++	.modes = &panel_modes,
++	.dsi_pdata = &jzdsi_pdata,
++
++	.lcd_type = LCD_TYPE_MIPI_TFT,
++	.tft_config = &kd050hdfia019_cfg,
++	.bpp = 24,
++	.width = 1024,
++	.height = 600,
++	.dither_enable = 0,
++	.dither.dither_red = 0,
++	.dither.dither_green = 0,
++	.dither.dither_blue = 0,
++
++
++};
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++	return panel->power;
++}
++
++/**
++* @ pannel_ek79007ad_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->vdd_en.gpio, GPIOF_DIR_OUT, "vdd_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++
++	panel->stbyb.gpio = of_get_named_gpio_flags(np, "ingenic,stbyb-gpio", 0, &flags);
++	if(gpio_is_valid(panel->stbyb.gpio)) {
++		panel->stbyb.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->stbyb.gpio, GPIOF_DIR_OUT, "stbyb");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request standby pin!\n");
++		//	goto err_request_rst;
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio stbyb.gpio: %d\n", panel->stbyb.gpio);
++	}
++
++
++	panel->lcd_pwm.gpio = of_get_named_gpio_flags(np, "ingenic,lcd-pwm-gpio", 0, &flags);
++	if(gpio_is_valid(panel->lcd_pwm.gpio)) {
++		panel->lcd_pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++//		ret = gpio_request_one(panel->lcd_pwm.gpio, GPIOF_DIR_OUT, "lcd-pwm");
++		ret = gpio_direction_output(panel->lcd_pwm.gpio,1);
++		if(ret < 0) {
++			dev_err(dev, "Failed to request lcd-pwm pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio lcd-pwm.gpio: %d\n", panel->lcd_pwm.gpio);
++	}
++
++
++	return 0;
++err_request_lcd_te:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++err_request_rst:
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++	return ret;
++}
++
++static int panel_dev_probe(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct ek79007ad *lcd;
++	lcd = devm_kzalloc(&dsim_dev->dev, sizeof(struct ek79007ad), GFP_KERNEL);
++	if (!lcd)
++	{
++		dev_err(&dsim_dev->dev, "failed to allocate fitipower_ek79007ad structure.\n");
++		return -ENOMEM;
++	}
++
++	lcd->dsim_dev = dsim_dev;
++	lcd->dev = &dsim_dev->dev;
++
++	lcd->ld = lcd_device_register("fitipower_ek79007ad", lcd->dev, lcd,
++	                              &panel_lcd_ops);
++	if (IS_ERR(lcd->ld))
++	{
++		dev_err(lcd->dev, "failed to register lcd ops.\n");
++		return PTR_ERR(lcd->ld);
++	}
++
++	dev_set_drvdata(&dsim_dev->dev, lcd);
++
++
++	dev_dbg(lcd->dev, "probed fitipower_ek79007ad panel driver.\n");
++
++
++	panel->dsim_dev = dsim_dev;
++
++
++	return 0;
++
++}
++
++static int panel_suspend(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++
++	panel_dev_display_off(panel);
++	panel_dev_sleep_in(panel);
++	gpio_direction_output(vdd_en->gpio, !vdd_en->active_level);
++
++	return 0;
++}
++
++static int panel_resume(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	return 0;
++}
++
++static struct mipi_dsim_lcd_driver panel_dev_dsim_ddi_driver = {
++	.name = "fitipower_ek79007ad-lcd",
++	.id = -1,
++
++	.power_on = panel_dev_power_on,
++	.set_sequence = panel_dev_set_sequence,
++	.probe = panel_dev_probe,
++//	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++
++
++struct mipi_dsim_lcd_device panel_dev_device={
++	.name		= "fitipower_ek79007ad-lcd",
++	.id = 0,
++};
++
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	mipi_dsi_register_lcd_device(&panel_dev_device);
++	mipi_dsi_register_lcd_driver(&panel_dev_dsim_ddi_driver);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_of_parse;
++	}
++
++	return 0;
++
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,ek79007ad", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "ek79007ad",
++		.of_match_table = panel_of_match,
++	},
++};
++
++module_platform_driver(panel_driver);
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-fw035.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-fw035.c
+new file mode 100644
+index 000000000..788d23482
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-fw035.c
+@@ -0,0 +1,509 @@
++/*
++ * driver/video/fbdev/ingenic/fb_v12/displays/fw035.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * Author:clwang<chunlei.wang@ingenic.com>
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++
++#include "../ingenicfb.h"
++#include "../dpu_ctrl.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio cs;
++	struct board_gpio rst;
++	struct board_gpio vdd_en;
++	struct board_gpio vddio_en;
++	struct board_gpio pwm;
++	struct board_gpio rd;
++};
++
++static struct smart_lcd_data_table fw035_data_table[] = {
++/* LCD init code */
++	{SMART_CONFIG_CMD    , 0xE0},
++	{SMART_CONFIG_PRM    , 0x00},
++	{SMART_CONFIG_PRM    , 0x07},
++	{SMART_CONFIG_PRM    , 0x10},
++	{SMART_CONFIG_PRM    , 0x09},
++	{SMART_CONFIG_PRM    , 0x17},
++	{SMART_CONFIG_PRM    , 0x0B},
++	{SMART_CONFIG_PRM    , 0x40},
++	{SMART_CONFIG_PRM    , 0x8A},
++	{SMART_CONFIG_PRM    , 0x4B},
++	{SMART_CONFIG_PRM    , 0x0A},
++	{SMART_CONFIG_PRM    , 0x0D},
++	{SMART_CONFIG_PRM    , 0x0F},
++	{SMART_CONFIG_PRM    , 0x15},
++	{SMART_CONFIG_PRM    , 0x16},
++	{SMART_CONFIG_PRM    , 0x0F},
++
++	{SMART_CONFIG_CMD    , 0xE1},
++	{SMART_CONFIG_PRM    , 0x00},
++	{SMART_CONFIG_PRM    , 0x1A},
++	{SMART_CONFIG_PRM    , 0x1B},
++	{SMART_CONFIG_PRM    , 0x02},
++	{SMART_CONFIG_PRM    , 0x0D},
++	{SMART_CONFIG_PRM    , 0x05},
++	{SMART_CONFIG_PRM    , 0x30},
++	{SMART_CONFIG_PRM    , 0x35},
++	{SMART_CONFIG_PRM    , 0x43},
++	{SMART_CONFIG_PRM    , 0x02},
++	{SMART_CONFIG_PRM    , 0x0A},
++	{SMART_CONFIG_PRM    , 0x09},
++	{SMART_CONFIG_PRM    , 0x32},
++	{SMART_CONFIG_PRM    , 0x36},
++	{SMART_CONFIG_PRM    , 0x0F},
++
++	{SMART_CONFIG_CMD    , 0xB1},
++	{SMART_CONFIG_PRM    , 0xA0},
++	{SMART_CONFIG_PRM    , 0x11},
++
++	{SMART_CONFIG_CMD    , 0xB4},
++	{SMART_CONFIG_PRM    , 0x02},
++
++	{SMART_CONFIG_CMD    , 0xC0},
++	{SMART_CONFIG_PRM    , 0x17},
++	{SMART_CONFIG_PRM    , 0x15},
++
++	{SMART_CONFIG_CMD    , 0xC1},
++	{SMART_CONFIG_PRM    , 0x41},
++
++	{SMART_CONFIG_CMD    , 0xC5},
++	{SMART_CONFIG_PRM    , 0x00},
++	{SMART_CONFIG_PRM    , 0x0A},
++	{SMART_CONFIG_PRM    , 0x80},
++
++	{SMART_CONFIG_CMD    , 0xB6},
++	{SMART_CONFIG_PRM    , 0x02},
++
++	{SMART_CONFIG_CMD    , 0x36},
++	{SMART_CONFIG_PRM    , 0x48},
++
++	{SMART_CONFIG_CMD    , 0x3A},
++	{SMART_CONFIG_PRM    , 0x56},
++
++	{SMART_CONFIG_CMD    , 0xE9},
++	{SMART_CONFIG_PRM    , 0x00},
++
++	{SMART_CONFIG_CMD    , 0xF7},
++	{SMART_CONFIG_PRM    , 0xA9},
++	{SMART_CONFIG_PRM    , 0x51},
++	{SMART_CONFIG_PRM    , 0x2C},
++	{SMART_CONFIG_PRM    , 0x82},
++
++	{SMART_CONFIG_CMD    , 0x11},
++	{SMART_CONFIG_UDELAY, 120000},
++	{SMART_CONFIG_CMD    , 0x29},
++	{SMART_CONFIG_CMD    , 0x2c},
++};
++
++static struct fb_videomode panel_modes[] = {
++	[0] = {
++		.name = "320x480",
++		.refresh = 60,
++		.xres = 320,
++		.yres = 480,
++		.pixclock = KHZ2PICOS(18432),
++		.left_margin = 0,
++		.right_margin = 0,
++		.upper_margin = 0,
++		.lower_margin = 0,
++		.hsync_len = 0,
++		.vsync_len = 0,
++		.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++		.vmode = FB_VMODE_NONINTERLACED,
++		.flag = 0,
++	},
++};
++
++struct smart_config fw035_cfg = {
++	.te_anti_jit = 1,
++	.te_md = 0,
++	.te_switch = 0,
++	.dc_md = 0,
++	.wr_md = 1,
++	.te_dp = 1,
++	.smart_type = SMART_LCD_TYPE_8080,
++	.pix_fmt = SMART_LCD_FORMAT_888,
++	.dwidth = SMART_LCD_DWIDTH_8_BIT,
++	.cwidth = SMART_LCD_CWIDTH_8_BIT,
++	.bus_width = 8,
++
++	.write_gram_cmd = 0x2c,
++	.data_table = fw035_data_table,
++	.length_data_table = ARRAY_SIZE(fw035_data_table),
++};
++
++static struct lcd_device *lcd_power = NULL;
++
++/* SGM3146 supports 16 brightness step */
++#define MAX_BRIGHTNESS_STEP     16
++/* System support 256 brightness step */
++#define CONVERT_FACTOR          (256/MAX_BRIGHTNESS_STEP)
++
++static int panel_update_status(struct backlight_device *bd)
++{
++	struct panel_dev *panel = dev_get_drvdata(&bd->dev);
++	int brightness = bd->props.brightness;
++	unsigned int i;
++	int pulse_num = MAX_BRIGHTNESS_STEP - brightness / CONVERT_FACTOR - 1;
++
++	if (bd->props.fb_blank == FB_BLANK_POWERDOWN) {
++		return 0;
++	}
++
++	if (bd->props.state & BL_CORE_SUSPENDED)
++		brightness = 0;
++
++	if (brightness && gpio_is_valid(panel->pwm.gpio)) {
++		gpio_direction_output(panel->pwm.gpio,0);
++		udelay(5000);
++		gpio_direction_output(panel->pwm.gpio,1);
++		udelay(100);
++
++		for (i = pulse_num; i > 0; i--) {
++			gpio_direction_output(panel->pwm.gpio,0);
++			udelay(1);
++			gpio_direction_output(panel->pwm.gpio,1);
++			udelay(3);
++		}
++	} else if (gpio_is_valid(panel->pwm.gpio))
++		gpio_direction_output(panel->pwm.gpio, 0);
++
++	return 0;
++}
++
++static struct backlight_ops panel_backlight_ops = {
++	.options = BL_CORE_SUSPENDRESUME,
++	.update_status = panel_update_status,
++};
++
++static void panel_power_reset(struct board_gpio *rst)
++{
++	gpio_direction_output(rst->gpio, 0);
++	mdelay(120);
++	gpio_direction_output(rst->gpio, 1);
++	mdelay(120);
++}
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++	struct board_gpio *cs = &panel->cs;
++	struct board_gpio *rst = &panel->rst;
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *vddio_en = &panel->vddio_en;
++	struct board_gpio *rd = &panel->rd;
++
++	if(POWER_IS_ON(power) && !POWER_IS_ON(panel->power)) {
++		if(gpio_is_valid(panel->pwm.gpio))
++			gpio_direction_output(panel->pwm.gpio, 1);
++		gpio_direction_output(vdd_en->gpio, 1);
++		gpio_direction_output(rd->gpio, 1);
++		if(gpio_is_valid(panel->vddio_en.gpio))
++			gpio_direction_output(vddio_en->gpio, 1);
++		gpio_direction_output(cs->gpio, 1);
++		gpio_direction_output(rst->gpio, 1);
++		mdelay(10);
++		panel_power_reset(rst);
++		gpio_direction_output(cs->gpio, 0);
++	}
++	if(!POWER_IS_ON(power) && POWER_IS_ON(panel->power)) {
++		gpio_direction_output(cs->gpio, 0);
++		gpio_direction_output(rst->gpio, 0);
++		if(gpio_is_valid(panel->vddio_en.gpio))
++			gpio_direction_output(vddio_en->gpio, 0);
++		gpio_direction_output(rd->gpio, 0);
++		gpio_direction_output(vdd_en->gpio, 0);
++	}
++
++	panel->power = power;
++	return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++static struct lcd_ops panel_lcd_ops = {
++/*	.set_power = panel_set_power,*/
++/*	.get_power = panel_get_power,*/
++};
++
++static int panel_power_off(struct lcd_panel *lcd_panel)
++{
++	if(lcd_power)
++		panel_set_power(lcd_power, FB_BLANK_POWERDOWN);
++
++	return 0;
++}
++
++static int panel_power_on(struct lcd_panel *lcd_panel)
++{
++	if(lcd_power)
++		panel_set_power(lcd_power, FB_BLANK_UNBLANK);
++
++	return 0;
++}
++
++static struct lcd_panel_ops fw035_ops = {
++	.disable  = (void*)panel_power_off,
++	.enable = (void*)panel_power_on,
++};
++
++struct lcd_panel lcd_panel = {
++	.name = "fw035",
++	.num_modes = ARRAY_SIZE(panel_modes),
++	.modes = panel_modes,
++	.lcd_type = LCD_TYPE_SLCD,
++	.width = 320,
++	.height = 480,
++
++	.smart_config = &fw035_cfg,
++
++	.dither_enable = 0,
++	.dither.dither_red = 0,
++	.dither.dither_green = 0,
++	.dither.dither_blue = 0,
++
++	.ops = &fw035_ops,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->cs.gpio = of_get_named_gpio_flags(np, "ingenic,cs-gpio", 0, &flags);
++	if(gpio_is_valid(panel->cs.gpio)) {
++		panel->cs.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->cs.gpio, GPIOF_DIR_OUT, "cs");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request cs pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio cs.gpio: %d\n", panel->cs.gpio);
++	}
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++
++	panel->pwm.gpio = of_get_named_gpio_flags(np, "ingenic,pwm-gpio", 0, &flags);
++	if(gpio_is_valid(panel->pwm.gpio)) {
++		panel->pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->pwm.gpio, GPIOF_DIR_OUT, "pwm");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request pwm pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio pwm.gpio: %d\n", panel->pwm.gpio);
++	}
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->vdd_en.gpio, GPIOF_DIR_OUT, "vdd_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	panel->rd.gpio = of_get_named_gpio_flags(np, "ingenic,rd-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rd.gpio)) {
++		panel->rd.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->rd.gpio, GPIOF_DIR_OUT, "rd");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rd pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rd.gpio: %d\n", panel->rd.gpio);
++	}
++
++	panel->vddio_en.gpio = of_get_named_gpio_flags(np, "ingenic,vddio-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vddio_en.gpio)) {
++		panel->vddio_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->vddio_en.gpio, GPIOF_DIR_OUT, "vddio_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vddio_en pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vddio_en.gpio: %d\n", panel->vddio_en.gpio);
++	}
++
++	return 0;
++err_request_rst:
++	gpio_free(panel->cs.gpio);
++	return ret;
++}
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++
++	int ret = 0;
++	struct panel_dev *panel;
++	struct backlight_properties props;
++
++	memset(&props, 0, sizeof(props));
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	panel->lcd = lcd_device_register("panel_lcd", &pdev->dev, panel, &panel_lcd_ops);
++	if(IS_ERR_OR_NULL(panel->lcd)) {
++		dev_err(&pdev->dev, "Error register lcd!\n");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++	lcd_power = panel->lcd;
++
++	/* TODO: should this power status sync from uboot */
++	panel->power = FB_BLANK_POWERDOWN;
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++
++	props.type = BACKLIGHT_RAW;
++	props.max_brightness = 255;
++	panel->backlight = backlight_device_register("pwm-backlight.0",
++						&pdev->dev, panel,
++						&panel_backlight_ops,
++						&props);
++	if (IS_ERR_OR_NULL(panel->backlight)) {
++		dev_err(panel->dev, "failed to register 'pwm-backlight.0'.\n");
++		goto err_lcd_register;
++	}
++	panel->backlight->props.brightness = props.max_brightness;
++	backlight_update_status(panel->backlight);
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++	return 0;
++err_lcd_register:
++	lcd_device_unregister(panel->lcd);
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	struct panel_dev *panel = dev_get_drvdata(&pdev->dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int panel_suspend(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++static int panel_resume(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++#endif
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,fw035", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "fw035",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-fw040.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-fw040.c
+new file mode 100644
+index 000000000..96cbfe367
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-fw040.c
+@@ -0,0 +1,644 @@
++/*
++ * driver/video/fbdev/ingenic/fb_stage/displays/panel-fw040.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++
++#include "../ingenicfb.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct gpio_spi {
++	short sdo;
++	short sdi;
++	short sck;
++	short cs;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio pwm;
++	struct gpio_spi spi;
++};
++
++struct fw040_pinctrl{
++	struct pinctrl_state *sda_high;
++	struct pinctrl_state *sda_low;
++	struct pinctrl_state *sck_high;
++	struct pinctrl_state *sck_low;
++	struct pinctrl_state *i2c;
++};
++
++static struct panel_dev *panel;
++static struct fw040_pinctrl *state;
++static struct pinctrl *p = NULL;
++
++#define RESET(n)\
++     gpio_direction_output(panel->rst.gpio, n)
++
++#define CS(n)\
++     gpio_direction_output(panel->spi.cs, n)
++
++#define SCK_HIGH()\
++	pinctrl_select_state(p, state->sck_high)
++
++#define SCK_LOW()\
++	pinctrl_select_state(p, state->sck_low)
++#define SDA_HIGH()\
++	pinctrl_select_state(p, state->sda_high)
++
++#define SDA_LOW()\
++	pinctrl_select_state(p, state->sda_low)
++
++void SPI_SendData(unsigned short data)
++{
++   unsigned char n;
++
++   for(n = 0; n < 16; n++) {
++	   if(data&0x8000)
++		   SDA_HIGH();
++	   else
++		   SDA_LOW();
++	   data = data << 1;
++
++	   SCK_HIGH();
++	   udelay(1);
++	   SCK_LOW();
++	   udelay(1);
++   }
++}
++
++void spi_writecomm(unsigned short cmd)
++{
++	unsigned short addr_h = (0x2000 + ((cmd >> 8) & 0xff));
++	unsigned short addr_l = (cmd & 0xff);
++
++	CS(0);
++	udelay(50);
++
++	SPI_SendData(addr_h);
++
++	SPI_SendData(addr_l);
++
++	CS(1);
++	udelay(50);
++}
++
++void spi_writedata(unsigned char d)
++{
++	unsigned short data = (0x4000 + d);
++
++	CS(0);
++	udelay(50);
++
++	SPI_SendData(data);
++
++	CS(1);
++	udelay(50);
++}
++
++void Initial_IC(void)
++{
++	unsigned char data = 0;
++
++	SDA_LOW();
++	SCK_LOW();
++	CS(1);
++
++	udelay(1200);
++	spi_writecomm(0xFF00);spi_writedata(0x77);
++	spi_writecomm(0XFF01);spi_writedata(0x01);
++	spi_writecomm(0xFF02);spi_writedata(0x00);
++	spi_writecomm(0xFF03);spi_writedata(0x00);
++	spi_writecomm(0xFF04);spi_writedata(0x10);
++
++	spi_writecomm(0xC000);spi_writedata(0x63);
++	spi_writecomm(0xC001);spi_writedata(0x00);
++
++	spi_writecomm(0xC100);spi_writedata(0x11);
++	spi_writecomm(0xC101);spi_writedata(0x02);
++
++	spi_writecomm(0xC200);spi_writedata(0x01);
++	spi_writecomm(0xC201);spi_writedata(0x08);
++
++	spi_writecomm(0xCC00);spi_writedata(0x10);
++
++	spi_writecomm(0xB000);spi_writedata(0x00);
++	spi_writecomm(0xB001);spi_writedata(0x0d);
++	spi_writecomm(0xB002);spi_writedata(0x14);
++	spi_writecomm(0xB003);spi_writedata(0x0e);
++	spi_writecomm(0xB004);spi_writedata(0x11);
++	spi_writecomm(0xB005);spi_writedata(0x07);
++	spi_writecomm(0xB006);spi_writedata(0x44);
++	spi_writecomm(0xB007);spi_writedata(0x08);
++	spi_writecomm(0xB008);spi_writedata(0x08);
++	spi_writecomm(0xB009);spi_writedata(0x60);
++	spi_writecomm(0xB00A);spi_writedata(0x03);
++	spi_writecomm(0xB00B);spi_writedata(0x11);
++	spi_writecomm(0xB00C);spi_writedata(0x10);
++	spi_writecomm(0xB00D);spi_writedata(0x2d);
++	spi_writecomm(0xB00E);spi_writedata(0x34);
++	spi_writecomm(0xB00F);spi_writedata(0x1F);
++
++	spi_writecomm(0xB100);spi_writedata(0x00);
++	spi_writecomm(0xB101);spi_writedata(0x0c);
++	spi_writecomm(0xB102);spi_writedata(0x13);
++	spi_writecomm(0xB103);spi_writedata(0x0d);
++	spi_writecomm(0xB104);spi_writedata(0x10);
++	spi_writecomm(0xB105);spi_writedata(0x05);
++	spi_writecomm(0xB106);spi_writedata(0x43);
++	spi_writecomm(0xB107);spi_writedata(0x08);
++	spi_writecomm(0xB108);spi_writedata(0x07);
++	spi_writecomm(0xB109);spi_writedata(0x60);
++	spi_writecomm(0xB10A);spi_writedata(0x04);
++	spi_writecomm(0xB10B);spi_writedata(0x11);
++	spi_writecomm(0xB10C);spi_writedata(0x10);
++	spi_writecomm(0xB10D);spi_writedata(0x2d);
++	spi_writecomm(0xB10E);spi_writedata(0x34);
++	spi_writecomm(0xB10F);spi_writedata(0x1F);
++
++	spi_writecomm(0xFF00);spi_writedata(0x77);
++	spi_writecomm(0XFF01);spi_writedata(0x01);
++	spi_writecomm(0xFF02);spi_writedata(0x00);
++	spi_writecomm(0xFF03);spi_writedata(0x00);
++	spi_writecomm(0xFF04);spi_writedata(0x11);
++
++	spi_writecomm(0xB000);spi_writedata(0x67);
++
++	spi_writecomm(0xB100);spi_writedata(0x66);
++
++	spi_writecomm(0xB200);spi_writedata(0x07);
++
++	spi_writecomm(0xB300);spi_writedata(0x80);
++
++	spi_writecomm(0xB500);spi_writedata(0x45);
++
++	spi_writecomm(0xB700);spi_writedata(0x85);
++
++	spi_writecomm(0xB800);spi_writedata(0x21);
++
++	spi_writecomm(0xB900);spi_writedata(0x00);
++	spi_writecomm(0xB901);spi_writedata(0x10);
++
++	spi_writecomm(0xC100);spi_writedata(0x78);
++
++	spi_writecomm(0xC200);spi_writedata(0x78);
++
++	spi_writecomm(0xD000);spi_writedata(0x88);
++
++	spi_writecomm(0xE000);spi_writedata(0x00);
++	spi_writecomm(0xE001);spi_writedata(0x00);
++	spi_writecomm(0xE002);spi_writedata(0x02);
++
++	spi_writecomm(0xE100);spi_writedata(0x08);
++	spi_writecomm(0xE101);spi_writedata(0x00);
++	spi_writecomm(0xE102);spi_writedata(0x0a);
++	spi_writecomm(0xE105);spi_writedata(0x00);
++	spi_writecomm(0xE104);spi_writedata(0x07);
++	spi_writecomm(0xE105);spi_writedata(0x00);
++	spi_writecomm(0xE106);spi_writedata(0x09);
++	spi_writecomm(0xE107);spi_writedata(0x00);
++	spi_writecomm(0xE108);spi_writedata(0x00);
++	spi_writecomm(0xE109);spi_writedata(0x33);
++	spi_writecomm(0xE10A);spi_writedata(0x33);
++
++	spi_writecomm(0xE200);spi_writedata(0x00);
++	spi_writecomm(0xE201);spi_writedata(0x00);
++	spi_writecomm(0xE202);spi_writedata(0x00);
++	spi_writecomm(0xE203);spi_writedata(0x00);
++	spi_writecomm(0xE204);spi_writedata(0x00);
++	spi_writecomm(0xE205);spi_writedata(0x00);
++	spi_writecomm(0xE206);spi_writedata(0x00);
++	spi_writecomm(0xE207);spi_writedata(0x00);
++	spi_writecomm(0xE208);spi_writedata(0x00);
++	spi_writecomm(0xE209);spi_writedata(0x00);
++	spi_writecomm(0xE20A);spi_writedata(0x00);
++	spi_writecomm(0xE20B);spi_writedata(0x00);
++	spi_writecomm(0xE20C);spi_writedata(0x00);
++
++	spi_writecomm(0xE300);spi_writedata(0x00);
++	spi_writecomm(0xE301);spi_writedata(0x00);
++	spi_writecomm(0xE302);spi_writedata(0x33);
++	spi_writecomm(0xE303);spi_writedata(0x33);
++
++	spi_writecomm(0xE400);spi_writedata(0x44);
++	spi_writecomm(0xE401);spi_writedata(0x44);
++
++	spi_writecomm(0xE500);spi_writedata(0x0e);
++	spi_writecomm(0xE501);spi_writedata(0x2d);
++	spi_writecomm(0xE502);spi_writedata(0xa0);
++	spi_writecomm(0xE503);spi_writedata(0xA0);
++	spi_writecomm(0xE504);spi_writedata(0x10);
++	spi_writecomm(0xE505);spi_writedata(0x2d);
++	spi_writecomm(0xE506);spi_writedata(0xa0);
++	spi_writecomm(0xE507);spi_writedata(0xA0);
++	spi_writecomm(0xE508);spi_writedata(0x0a);
++	spi_writecomm(0xE509);spi_writedata(0x2d);
++	spi_writecomm(0xE50A);spi_writedata(0xa0);
++	spi_writecomm(0xE50B);spi_writedata(0xA0);
++	spi_writecomm(0xE50C);spi_writedata(0x0c);
++	spi_writecomm(0xE50D);spi_writedata(0x2d);
++	spi_writecomm(0xE50E);spi_writedata(0xa0);
++	spi_writecomm(0xE50F);spi_writedata(0xA0);
++
++	spi_writecomm(0xE600);spi_writedata(0x00);
++	spi_writecomm(0xE601);spi_writedata(0x00);
++	spi_writecomm(0xE602);spi_writedata(0x33);
++	spi_writecomm(0xE603);spi_writedata(0x33);
++
++	spi_writecomm(0xE700);spi_writedata(0x44);
++	spi_writecomm(0xE701);spi_writedata(0x44);
++
++	spi_writecomm(0xE800);spi_writedata(0x0d);
++	spi_writecomm(0xE801);spi_writedata(0x2d);
++	spi_writecomm(0xE802);spi_writedata(0xa0);
++	spi_writecomm(0xE803);spi_writedata(0xA0);
++	spi_writecomm(0xE804);spi_writedata(0x0f);
++	spi_writecomm(0xE805);spi_writedata(0x2d);
++	spi_writecomm(0xE806);spi_writedata(0xa0);
++	spi_writecomm(0xE807);spi_writedata(0xA0);
++	spi_writecomm(0xE808);spi_writedata(0x09);
++	spi_writecomm(0xE809);spi_writedata(0x2d);
++	spi_writecomm(0xE80A);spi_writedata(0xa0);
++	spi_writecomm(0xE80B);spi_writedata(0xA0);
++	spi_writecomm(0xE80C);spi_writedata(0x0b);
++	spi_writecomm(0xE80D);spi_writedata(0x2d);
++	spi_writecomm(0xE80E);spi_writedata(0xa0);
++	spi_writecomm(0xE80F);spi_writedata(0xA0);
++
++	spi_writecomm(0xEB00);spi_writedata(0x02);
++	spi_writecomm(0xEB01);spi_writedata(0x01);
++	spi_writecomm(0xEB02);spi_writedata(0xe4);
++	spi_writecomm(0xEB03);spi_writedata(0xe4);
++	spi_writecomm(0xEB04);spi_writedata(0x44);
++	spi_writecomm(0xEB05);spi_writedata(0x00);
++	spi_writecomm(0xEB06);spi_writedata(0x40);
++
++	spi_writecomm(0xEC00);spi_writedata(0x02);
++	spi_writecomm(0xEC01);spi_writedata(0x01);
++
++	spi_writecomm(0xED00);spi_writedata(0xab);
++	spi_writecomm(0xED01);spi_writedata(0x89);
++	spi_writecomm(0xED02);spi_writedata(0x76);
++	spi_writecomm(0xED03);spi_writedata(0x54);
++	spi_writecomm(0xED04);spi_writedata(0x01);
++	spi_writecomm(0xED05);spi_writedata(0xFF);
++	spi_writecomm(0xED06);spi_writedata(0xFF);
++	spi_writecomm(0xED07);spi_writedata(0xFF);
++	spi_writecomm(0xED08);spi_writedata(0xFF);
++	spi_writecomm(0xED09);spi_writedata(0xFF);
++	spi_writecomm(0xED0A);spi_writedata(0xFf);
++	spi_writecomm(0xED0B);spi_writedata(0x10);
++	spi_writecomm(0xED0C);spi_writedata(0x45);
++	spi_writecomm(0xED0D);spi_writedata(0x67);
++	spi_writecomm(0xED0E);spi_writedata(0x98);
++	spi_writecomm(0xED0F);spi_writedata(0xba);
++
++	spi_writecomm(0xFF00);spi_writedata(0x77);
++	spi_writecomm(0XFF01);spi_writedata(0x01);
++	spi_writecomm(0xFF02);spi_writedata(0x00);
++	spi_writecomm(0xFF03);spi_writedata(0x00);
++	spi_writecomm(0xFF04);spi_writedata(0x00);
++
++	spi_writecomm(0x3a00);spi_writedata(0x77);
++	spi_writecomm(0x3600);spi_writedata(0x00);
++	spi_writecomm(0x1100);spi_writedata(0x00);
++	msleep(150);
++	spi_writecomm(0x2900);spi_writedata(0xFF);
++}
++
++
++static void panel_enable(struct lcd_panel *panel)
++{
++}
++
++static void panel_disable(struct lcd_panel *panel)
++{
++}
++
++static struct lcd_panel_ops panel_ops = {
++	.enable  = (void*)panel_enable,
++	.disable = (void*)panel_disable,
++};
++
++static struct fb_videomode panel_modes[] = {
++	[0] = {
++		.name                   = "fw040",
++		.refresh                = 60,
++		.xres                   = 480,
++		.yres                   = 800,
++		.pixclock               = KHZ2PICOS(14000),
++		.left_margin            = 42,
++		.right_margin           = 16,
++		.upper_margin           = 28,
++		.lower_margin           = 12,
++
++		.hsync_len              = 2,
++		.vsync_len              = 2,
++		.sync                   = ~FB_SYNC_HOR_HIGH_ACT & ~FB_SYNC_VERT_HIGH_ACT,
++		.vmode                  = FB_VMODE_NONINTERLACED,
++		.flag                   = 0,
++	},
++};
++
++static struct tft_config fw040_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.vsync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++struct lcd_panel lcd_panel = {
++	.name = "fw040",
++	.num_modes = ARRAY_SIZE(panel_modes),
++	.modes = panel_modes,
++	.bpp = 32,
++	.width = 480,
++	.height = 800,
++
++	.lcd_type = LCD_TYPE_TFT,
++
++	.tft_config = &fw040_cfg,
++
++	.dither_enable = 0,
++	.dither.dither_red = 0,
++	.dither.dither_green = 0,
++	.dither.dither_blue = 0,
++
++	.ops = &panel_ops,
++};
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++	struct board_gpio *pwm = &panel->pwm;
++
++	if(!POWER_IS_ON(power) && POWER_IS_ON(panel->power)) {
++		gpio_direction_output(vdd_en->gpio, 0);
++	}else{
++		if(gpio_is_valid(pwm->gpio)){
++			gpio_direction_output(pwm->gpio, 1);
++			msleep(180);
++		}
++	gpio_direction_output(vdd_en->gpio, 0);
++	gpio_direction_output(rst->gpio, 1);
++	msleep(100);
++
++	gpio_direction_output(vdd_en->gpio, 1);
++	msleep(180);
++
++	gpio_direction_output(rst->gpio, 0);
++	msleep(20);
++	gpio_direction_output(rst->gpio, 1);
++	msleep(20);
++
++	Initial_IC();
++	pinctrl_select_state(p, state->i2c);
++	gpio_free(panel->spi.cs);
++	}
++
++	panel->power = power;
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++* @ pannel_fw040_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->vdd_en.gpio, GPIOF_DIR_OUT, "vdd_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++
++	panel->pwm.gpio = of_get_named_gpio_flags(np, "ingenic,lcd-pwm-gpio", 0, &flags);
++	if(gpio_is_valid(panel->pwm.gpio)) {
++		panel->pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->pwm.gpio, GPIOF_DIR_OUT, "pwm");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request pwm pin!\n");
++			goto err_request_pwm;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio pwm.gpio: %d\n", panel->pwm.gpio);
++	}
++
++	panel->spi.cs = of_get_named_gpio_flags(np, "ingenic,lcd-cs-gpio", 0, &flags);
++	if(gpio_is_valid(panel->spi.cs)) {
++		ret = gpio_request_one(panel->spi.cs, GPIOF_DIR_OUT, "cs");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request cs pin!\n");
++			goto err_request_cs;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio spi.cs: %d\n", panel->spi.cs);
++	}
++
++	state->i2c = pinctrl_lookup_state(p, "i2c-func");
++	state->sda_high = pinctrl_lookup_state(p, "sda-high");
++	state->sda_low = pinctrl_lookup_state(p, "sda-low");
++	state->sck_high = pinctrl_lookup_state(p, "sck-high");
++	state->sck_low = pinctrl_lookup_state(p, "sck-low");
++
++	return 0;
++err_request_cs:
++	if(gpio_is_valid(panel->spi.sck))
++		gpio_free(panel->spi.sck);
++err_request_sck:
++	if(gpio_is_valid(panel->spi.sdo))
++		gpio_free(panel->spi.sdo);
++err_request_sdo:
++	if(gpio_is_valid(panel->pwm.gpio))
++		gpio_free(panel->pwm.gpio);
++err_request_pwm:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++err_request_rst:
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++	return ret;
++}
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++
++	int ret = 0;
++	/* struct panel_dev *panel; */
++	struct backlight_properties props;
++
++	state = kzalloc(sizeof(struct fw040_pinctrl), GFP_KERNEL);
++	if(state == NULL) {
++		dev_err(&pdev->dev, "Failed to alloc memory!");
++		return -ENOMEM;
++	}
++
++	memset(&props, 0, sizeof(props));
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Failed to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	p = pinctrl_get(&pdev->dev);
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	panel->lcd = lcd_device_register("panel_lcd", &pdev->dev, panel, &panel_lcd_ops);
++	if(IS_ERR_OR_NULL(panel->lcd)) {
++		dev_err(&pdev->dev, "Error register lcd!\n");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++	/* TODO: should this power status sync from uboot */
++	panel->power = FB_BLANK_POWERDOWN;
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++	return 0;
++
++err_lcd_register:
++	lcd_device_unregister(panel->lcd);
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	struct panel_dev *panel = dev_get_drvdata(&pdev->dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int panel_suspend(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++static int panel_resume(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++#endif
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,fw040", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "fw040",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-fw050.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-fw050.c
+new file mode 100644
+index 000000000..1195d7882
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-fw050.c
+@@ -0,0 +1,717 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-fw050.c
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ * This program is free software, you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++#include <linux/fb.h>
++#include <linux/backlight.h>
++
++#include "../ingenicfb.h"
++#include "../jz_dsim.h"
++
++
++static char panel_fw050_debug = 0;
++#define PANEL_DEBUG_MSG(msg...)			\
++	do {					\
++		if (panel_fw050_debug)		\
++			printk(">>>>>>>>>>>>>>>>PANEL FW050: " msg);		\
++	} while(0)
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio lcd_te;
++	struct board_gpio lcd_pwm;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++};
++
++struct panel_dev *panel;
++
++#define lcd_to_master(a)	(a->dsim_dev->master)
++#define lcd_to_master_ops(a)	((lcd_to_master(a))->master_ops)
++
++#define PANEL_FW050_ID	(0x98815c)
++
++struct fw050 {
++	struct device *dev;
++	unsigned int power;
++	unsigned int id;
++
++	struct lcd_device *ld;
++	struct backlight_device *bd;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++
++};
++
++
++static struct dsi_cmd_packet fitipower_fw050_720_1280_cmd_list[] =
++{
++	{0x39, 0x04, 0x00, {0xFF, 0x98, 0x81, 0x03}},
++	{0x39, 0x02, 0x00, {0x01, 0x00}},
++	{0x39, 0x02, 0x00, {0x02, 0x00}},
++	{0x39, 0x02, 0x00, {0x03, 0x73}},
++	{0x39, 0x02, 0x00, {0x04, 0x00}},
++	{0x39, 0x02, 0x00, {0x05, 0x00}},
++	{0x39, 0x02, 0x00, {0x06, 0x0A}},
++	{0x39, 0x02, 0x00, {0x07, 0x00}},
++	{0x39, 0x02, 0x00, {0x08, 0x00}},
++	{0x39, 0x02, 0x00, {0x09, 0x01}},
++	{0x39, 0x02, 0x00, {0x0A, 0x00}},
++	{0x39, 0x02, 0x00, {0x0B, 0x00}},
++	{0x39, 0x02, 0x00, {0x0C, 0x01}},
++	{0x39, 0x02, 0x00, {0x0D, 0x00}},
++	{0x39, 0x02, 0x00, {0x0E, 0x00}},
++	{0x39, 0x02, 0x00, {0x0F, 0x1D}},
++	{0x39, 0x02, 0x00, {0x10, 0x1D}},
++	{0x39, 0x02, 0x00, {0x11, 0x00}},
++	{0x39, 0x02, 0x00, {0x12, 0x00}},
++	{0x39, 0x02, 0x00, {0x13, 0x00}},
++	{0x39, 0x02, 0x00, {0x14, 0x00}},
++	{0x39, 0x02, 0x00, {0x15, 0x00}},
++	{0x39, 0x02, 0x00, {0x16, 0x00}},
++	{0x39, 0x02, 0x00, {0x17, 0x00}},
++	{0x39, 0x02, 0x00, {0x18, 0x00}},
++	{0x39, 0x02, 0x00, {0x19, 0x00}},
++	{0x39, 0x02, 0x00, {0x1A, 0x00}},
++	{0x39, 0x02, 0x00, {0x1B, 0x00}},
++	{0x39, 0x02, 0x00, {0x1C, 0x00}},
++	{0x39, 0x02, 0x00, {0x1D, 0x00}},
++	{0x39, 0x02, 0x00, {0x1E, 0x40}},
++	{0x39, 0x02, 0x00, {0x1F, 0x80}},
++	{0x39, 0x02, 0x00, {0x20, 0x06}},
++	{0x39, 0x02, 0x00, {0x21, 0x02}},
++	{0x39, 0x02, 0x00, {0x22, 0x00}},
++	{0x39, 0x02, 0x00, {0x23, 0x00}},
++	{0x39, 0x02, 0x00, {0x24, 0x00}},
++	{0x39, 0x02, 0x00, {0x25, 0x00}},
++	{0x39, 0x02, 0x00, {0x26, 0x00}},
++	{0x39, 0x02, 0x00, {0x27, 0x00}},
++	{0x39, 0x02, 0x00, {0x28, 0x33}},
++	{0x39, 0x02, 0x00, {0x29, 0x03}},
++	{0x39, 0x02, 0x00, {0x2A, 0x00}},
++	{0x39, 0x02, 0x00, {0x2B, 0x00}},
++	{0x39, 0x02, 0x00, {0x2C, 0x00}},
++	{0x39, 0x02, 0x00, {0x2D, 0x00}},
++	{0x39, 0x02, 0x00, {0x2E, 0x00}},
++	{0x39, 0x02, 0x00, {0x2F, 0x00}},
++	{0x39, 0x02, 0x00, {0x30, 0x00}},
++	{0x39, 0x02, 0x00, {0x31, 0x00}},
++	{0x39, 0x02, 0x00, {0x32, 0x00}},
++	{0x39, 0x02, 0x00, {0x33, 0x00}},
++	{0x39, 0x02, 0x00, {0x34, 0x04}},
++	{0x39, 0x02, 0x00, {0x35, 0x00}},
++	{0x39, 0x02, 0x00, {0x36, 0x00}},
++	{0x39, 0x02, 0x00, {0x37, 0x00}},
++	{0x39, 0x02, 0x00, {0x38, 0x3C}},
++	{0x39, 0x02, 0x00, {0x39, 0x00}},
++	{0x39, 0x02, 0x00, {0x3A, 0x40}},
++	{0x39, 0x02, 0x00, {0x3B, 0x40}},
++	{0x39, 0x02, 0x00, {0x3C, 0x00}},
++	{0x39, 0x02, 0x00, {0x3D, 0x00}},
++	{0x39, 0x02, 0x00, {0x3E, 0x00}},
++	{0x39, 0x02, 0x00, {0x3F, 0x00}},
++	{0x39, 0x02, 0x00, {0x40, 0x00}},
++	{0x39, 0x02, 0x00, {0x41, 0x00}},
++	{0x39, 0x02, 0x00, {0x42, 0x00}},
++	{0x39, 0x02, 0x00, {0x43, 0x00}},
++	{0x39, 0x02, 0x00, {0x44, 0x00}},
++
++	{0x39, 0x02, 0x00, {0x50, 0x01}},
++	{0x39, 0x02, 0x00, {0x51, 0x23}},
++	{0x39, 0x02, 0x00, {0x52, 0x45}},
++	{0x39, 0x02, 0x00, {0x53, 0x67}},
++	{0x39, 0x02, 0x00, {0x54, 0x89}},
++	{0x39, 0x02, 0x00, {0x55, 0xAB}},
++	{0x39, 0x02, 0x00, {0x56, 0x01}},
++	{0x39, 0x02, 0x00, {0x57, 0x23}},
++	{0x39, 0x02, 0x00, {0x58, 0x45}},
++	{0x39, 0x02, 0x00, {0x59, 0x67}},
++	{0x39, 0x02, 0x00, {0x5A, 0x89}},
++	{0x39, 0x02, 0x00, {0x5B, 0xAB}},
++	{0x39, 0x02, 0x00, {0x5C, 0xCD}},
++	{0x39, 0x02, 0x00, {0x5D, 0xEF}},
++
++	{0x39, 0x02, 0x00, {0x5E, 0x11}},
++	{0x39, 0x02, 0x00, {0x5F, 0x01}},
++	{0x39, 0x02, 0x00, {0x60, 0x00}},
++	{0x39, 0x02, 0x00, {0x61, 0x15}},
++	{0x39, 0x02, 0x00, {0x62, 0x14}},
++	{0x39, 0x02, 0x00, {0x63, 0x0E}},
++	{0x39, 0x02, 0x00, {0x64, 0x0F}},
++	{0x39, 0x02, 0x00, {0x65, 0x0C}},
++	{0x39, 0x02, 0x00, {0x66, 0x0D}},
++	{0x39, 0x02, 0x00, {0x67, 0x06}},
++	{0x39, 0x02, 0x00, {0x68, 0x02}},
++	{0x39, 0x02, 0x00, {0x69, 0x07}},
++	{0x39, 0x02, 0x00, {0x6A, 0x02}},
++	{0x39, 0x02, 0x00, {0x6B, 0x02}},
++	{0x39, 0x02, 0x00, {0x6C, 0x02}},
++	{0x39, 0x02, 0x00, {0x6D, 0x02}},
++	{0x39, 0x02, 0x00, {0x6E, 0x02}},
++	{0x39, 0x02, 0x00, {0x6F, 0x02}},
++	{0x39, 0x02, 0x00, {0x70, 0x02}},
++	{0x39, 0x02, 0x00, {0x71, 0x02}},
++	{0x39, 0x02, 0x00, {0x72, 0x02}},
++	{0x39, 0x02, 0x00, {0x73, 0x02}},
++	{0x39, 0x02, 0x00, {0x74, 0x02}},
++	{0x39, 0x02, 0x00, {0x75, 0x01}},
++	{0x39, 0x02, 0x00, {0x76, 0x00}},
++	{0x39, 0x02, 0x00, {0x77, 0x14}},
++	{0x39, 0x02, 0x00, {0x78, 0x15}},
++	{0x39, 0x02, 0x00, {0x79, 0x0E}},
++	{0x39, 0x02, 0x00, {0x7A, 0x0F}},
++	{0x39, 0x02, 0x00, {0x7B, 0x0C}},
++	{0x39, 0x02, 0x00, {0x7C, 0x0D}},
++	{0x39, 0x02, 0x00, {0x7D, 0x06}},
++	{0x39, 0x02, 0x00, {0x7E, 0x02}},
++	{0x39, 0x02, 0x00, {0x7F, 0x07}},
++	{0x39, 0x02, 0x00, {0x80, 0x02}},
++	{0x39, 0x02, 0x00, {0x81, 0x02}},
++	{0x39, 0x02, 0x00, {0x82, 0x02}},
++	{0x39, 0x02, 0x00, {0x83, 0x02}},
++	{0x39, 0x02, 0x00, {0x84, 0x02}},
++	{0x39, 0x02, 0x00, {0x85, 0x02}},
++	{0x39, 0x02, 0x00, {0x86, 0x02}},
++	{0x39, 0x02, 0x00, {0x87, 0x02}},
++	{0x39, 0x02, 0x00, {0x88, 0x02}},
++	{0x39, 0x02, 0x00, {0x89, 0x02}},
++	{0x39, 0x02, 0x00, {0x8A, 0x02}},
++	{0x39, 0x04, 0x00, {0xFF, 0x98, 0x81, 0x04}},
++
++	{0x39, 0x02, 0x00, {0x00, 0x80}}, //set 2 line mode
++
++	{0x39, 0x02, 0x00, {0x6C, 0x15}},
++	{0x39, 0x02, 0x00, {0x6E, 0x2A}},
++	{0x39, 0x02, 0x00, {0x6F, 0x33}},
++	{0x39, 0x02, 0x00, {0x8D, 0x14}},
++	{0x39, 0x02, 0x00, {0x87, 0xBA}},
++	{0x39, 0x02, 0x00, {0x26, 0x76}},
++	{0x39, 0x02, 0x00, {0xB2, 0xD1}},
++	{0x39, 0x02, 0x00, {0xB5, 0x06}},
++	{0x39, 0x02, 0x00, {0x3A, 0x24}},
++	{0x39, 0x02, 0x00, {0x35, 0x1F}},
++	{0x39, 0x02, 0x00, {0x32, 0x05}},
++	{0x39, 0x02, 0x00, {0x33, 0x00}},
++	{0x39, 0x02, 0x00, {0x7A, 0x0F}},
++	{0x39, 0x04, 0x00, {0xFF, 0x98, 0x81, 0x01}},
++	{0x39, 0x02, 0x00, {0x22, 0x0A}},
++	{0x39, 0x02, 0x00, {0x31, 0x00}},
++	{0x39, 0x02, 0x00, {0x53, 0x9c}},
++	{0x39, 0x02, 0x00, {0x55, 0x9c}},
++	{0x39, 0x02, 0x00, {0xB7, 0x03}},/*software set lansel pin */
++
++	{0x39, 0x02, 0x00, {0x50, 0xA0}},
++	{0x39, 0x02, 0x00, {0x51, 0xA0}},
++
++	{0x39, 0x02, 0x00, {0x60, 0x22}},
++	{0x39, 0x02, 0x00, {0x61, 0x00}},
++	{0x39, 0x02, 0x00, {0x62, 0x19}},
++	{0x39, 0x02, 0x00, {0x63, 0x00}},
++	{0x39, 0x02, 0x00, {0xA0, 0x08}},
++	{0x39, 0x02, 0x00, {0xA1, 0x19}},
++	{0x39, 0x02, 0x00, {0xA2, 0x20}},
++	{0x39, 0x02, 0x00, {0xA3, 0x12}},
++	{0x39, 0x02, 0x00, {0xA4, 0x13}},
++	{0x39, 0x02, 0x00, {0xA5, 0x24}},
++	{0x39, 0x02, 0x00, {0xA6, 0x19}},
++	{0x39, 0x02, 0x00, {0xA7, 0x19}},
++	{0x39, 0x02, 0x00, {0xA8, 0x6b}},
++	{0x39, 0x02, 0x00, {0xA9, 0x1a}},
++	{0x39, 0x02, 0x00, {0xAA, 0x27}},
++	{0x39, 0x02, 0x00, {0xAB, 0x62}},
++	{0x39, 0x02, 0x00, {0xAC, 0x18}},
++	{0x39, 0x02, 0x00, {0xAD, 0x15}},
++	{0x39, 0x02, 0x00, {0xAE, 0x4c}},
++	{0x39, 0x02, 0x00, {0xAF, 0x22}},
++	{0x39, 0x02, 0x00, {0xB0, 0x25}},
++	{0x39, 0x02, 0x00, {0xB1, 0x5b}},
++	{0x39, 0x02, 0x00, {0xB2, 0x6f}},
++	{0x39, 0x02, 0x00, {0xB3, 0x39}},
++
++	{0x39, 0x02, 0x00, {0xC0, 0x08}},
++	{0x39, 0x02, 0x00, {0xC1, 0x0d}},
++	{0x39, 0x02, 0x00, {0xC2, 0x19}},
++	{0x39, 0x02, 0x00, {0xC3, 0x0C}},
++	{0x39, 0x02, 0x00, {0xC4, 0x0c}},
++	{0x39, 0x02, 0x00, {0xC5, 0x1F}},
++	{0x39, 0x02, 0x00, {0xC6, 0x13}},
++	{0x39, 0x02, 0x00, {0xC7, 0x1a}},
++	{0x39, 0x02, 0x00, {0xC8, 0x5d}},
++	{0x39, 0x02, 0x00, {0xC9, 0x1b}},
++	{0x39, 0x02, 0x00, {0xCA, 0x26}},
++	{0x39, 0x02, 0x00, {0xCB, 0x5b}},
++	{0x39, 0x02, 0x00, {0xCC, 0x19}},
++	{0x39, 0x02, 0x00, {0xCD, 0x18}},
++	{0x39, 0x02, 0x00, {0xCE, 0x4C}},
++	{0x39, 0x02, 0x00, {0xCF, 0x22}},
++	{0x39, 0x02, 0x00, {0xD0, 0x2d}},
++	{0x39, 0x02, 0x00, {0xD1, 0x5D}},
++	{0x39, 0x02, 0x00, {0xD2, 0x6b}},
++	{0x39, 0x02, 0x00, {0xD3, 0x39}},
++
++	{0x39, 0x04, 0x00, {0xFF, 0x98, 0x81, 0x00}},
++};
++
++
++static void panel_dev_sleep_in(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x10, 0x00};
++	PANEL_DEBUG_MSG("enter %s %d \n",__func__, __LINE__);
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_sleep_out(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x11, 0x00};
++	PANEL_DEBUG_MSG("enter %s %d \n",__func__, __LINE__);
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_display_on(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x29, 0x00};
++	PANEL_DEBUG_MSG("enter %s %d \n",__func__, __LINE__);
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_display_off(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x28, 0x00};
++	PANEL_DEBUG_MSG("enter %s %d \n",__func__, __LINE__);
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_power_on(struct mipi_dsim_lcd_device *dsim_dev, int power)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++	struct board_gpio *lcd_te = &panel->lcd_te;
++	struct board_gpio *pwm = &panel->lcd_pwm;
++	PANEL_DEBUG_MSG("enter %s %d \n",__func__, __LINE__);
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++	if(gpio_is_valid(pwm->gpio))
++		gpio_direction_output(pwm->gpio, pwm->active_level);
++
++	if (gpio_is_valid(lcd_te->gpio)) {
++		gpio_direction_input(lcd_te->gpio);
++	}
++	msleep(50);
++	gpio_direction_output(rst->gpio, 0);
++	msleep(10);
++	gpio_direction_output(rst->gpio, 1);
++	msleep(120);
++
++	panel->power = power;
++}
++
++static int panel_dev_read_id(struct mipi_dsim_lcd_device *dsim_dev, unsigned char *buf, int count)
++{
++	struct dsi_master_ops *ops = dsim_dev->master->master_ops;
++
++	struct dsi_cmd_packet data_to_send0 = {0x14, 0x00, 0x0};
++	struct dsi_cmd_packet data_to_send1 = {0x14, 0x01, 0x0};
++	struct dsi_cmd_packet data_to_send2 = {0x14, 0x02, 0x0};
++	struct dsi_cmd_packet set_page1 = {0x39, 0x04, 0x00, {0xFF, 0x98, 0x81, 0x01}};
++	struct dsi_cmd_packet set_page0 = {0x39, 0x04, 0x00, {0xFF, 0x98, 0x81, 0x00}};
++	int ret = 0;
++	int panel_id = 0;
++
++	panel_dev_power_on(dsim_dev, 1);
++	ops->cmd_write(dsim_dev->master,  set_page1);
++	ret = ops->cmd_read(dsim_dev->master, data_to_send0, &buf[0], 1);
++	ret = ops->cmd_read(dsim_dev->master, data_to_send1, &buf[1], 1);
++	ret = ops->cmd_read(dsim_dev->master, data_to_send2, &buf[2], 1);
++	ops->cmd_write(dsim_dev->master,  set_page0);
++	panel_dev_power_on(dsim_dev, 0);
++
++	panel_id = (buf[0] << 16) + (buf[1] << 8) + buf[2];
++	printk("----------%s, (%d) id[0]: %x id[1]: %x, id[2]: %x, id:%08x \n", __func__, __LINE__, buf[0], buf[1], buf[2], panel_id);
++
++	if(panel_id == PANEL_FW050_ID)
++		return 0;
++	else
++		return -1;
++}
++
++static void panel_dev_panel_init(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_device *dsi = lcd_to_master(lcd);
++	int  i;
++	int ret;
++
++	for (i = 0; i < ARRAY_SIZE(fitipower_fw050_720_1280_cmd_list); i++)
++	{
++		ret = ops->cmd_write(dsi,  fitipower_fw050_720_1280_cmd_list[i]);
++	}
++}
++
++static void panel_dev_set_sequence(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct fw050 *lcd = dev_get_drvdata(&dsim_dev->dev);
++	PANEL_DEBUG_MSG("enter %s %d \n",__func__, __LINE__);
++
++	panel_dev_panel_init(panel);
++	panel_dev_sleep_out(panel);
++	msleep(120);
++	panel_dev_display_on(panel);
++	msleep(5);
++
++	lcd->power = FB_BLANK_UNBLANK;
++}
++
++
++static struct fb_videomode panel_modes = {
++	.name = "fitipower_fw050-lcd",
++	.xres = 720,
++	.yres = 1280,
++
++	.refresh = 30,
++
++	.left_margin = 120,	//hbp
++	.right_margin = 100,	//hfp
++	.hsync_len = 10,	//hsync
++
++	.upper_margin = 25,	//vbp
++	.lower_margin = 20,	//vfp
++	.vsync_len = 10,	//vsync
++
++	.sync                   = FB_SYNC_HOR_HIGH_ACT & FB_SYNC_VERT_HIGH_ACT,
++	.vmode                  = FB_VMODE_NONINTERLACED,
++	.flag = 0,
++};
++
++struct jzdsi_data jzdsi_pdata = {
++	.modes = &panel_modes,
++	.video_config.no_of_lanes = 2,
++	.video_config.virtual_channel = 0,
++	.video_config.color_coding = COLOR_CODE_24BIT,
++	.video_config.video_mode = VIDEO_BURST_WITH_SYNC_PULSES,
++	.video_config.receive_ack_packets = 0,	/* enable receiving of ack packets */
++	.video_config.is_18_loosely = 0,
++	.video_config.data_en_polarity = 1,
++	.video_config.byte_clock = 0, // driver will auto calculate byte_clock.
++	.video_config.byte_clock_coef = MIPI_PHY_BYTE_CLK_COEF_MUL6_DIV5, // byte_clock *6/5.
++
++	.dsi_config.max_lanes = 2,
++	.dsi_config.max_hs_to_lp_cycles = 100,
++	.dsi_config.max_lp_to_hs_cycles = 40,
++	.dsi_config.max_bta_cycles = 4095,
++	.dsi_config.color_mode_polarity = 1,
++	.dsi_config.shut_down_polarity = 1,
++	.dsi_config.max_bps = 2750,
++	.bpp_info = 24,
++};
++
++static struct tft_config fw050_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++struct lcd_panel lcd_panel = {
++	.num_modes = 1,
++	.modes = &panel_modes,
++	.dsi_pdata = &jzdsi_pdata,
++
++	.lcd_type = LCD_TYPE_MIPI_TFT,
++	.tft_config = &fw050_cfg,
++	.bpp = 24,
++	.width = 62,
++	.height = 110,
++	.dither_enable = 0,
++	.dither.dither_red = 0,
++	.dither.dither_green = 0,
++	.dither.dither_blue = 0,
++};
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/*
++* @ pannel_fw050_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++	PANEL_DEBUG_MSG("enter %s %d \n",__func__, __LINE__);
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		gpio_direction_output(panel->rst.gpio, !panel->rst.active_level);
++		gpio_direction_output(panel->rst.gpio, panel->rst.active_level);
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		gpio_direction_output(panel->vdd_en.gpio, !panel->vdd_en.active_level);
++		ret = gpio_request_one(panel->vdd_en.gpio, GPIOF_DIR_OUT, "vdd_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++			goto err_request_lcd_vdd;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	 panel->lcd_pwm.gpio = of_get_named_gpio_flags(np, "ingenic,lcd-pwm-gpio", 0, &flags);
++	 if(gpio_is_valid(panel->lcd_pwm.gpio)) {
++	 	panel->lcd_pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	 	ret = gpio_request_one(panel->lcd_pwm.gpio, GPIOF_DIR_OUT, "lcd-pwm");
++	 	if(ret < 0) {
++	 		dev_err(dev, "Failed to request lcd-pwm pin!\n");
++	 		goto err_request_lcd_pwm;
++	 	}
++	 } else {
++	 	dev_warn(dev, "invalid gpio lcd-pwm.gpio: %d\n", panel->lcd_pwm.gpio);
++	 }
++
++	return 0;
++
++err_request_lcd_pwm:
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++err_request_lcd_vdd:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++	return ret;
++}
++
++static int panel_dev_probe(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct fw050 *lcd;
++	char buffer[4];
++	int ret;
++	ret = panel_dev_read_id(dsim_dev, buffer, 4);
++	if(ret < 0) {
++		return -EINVAL;
++	}
++
++	lcd = devm_kzalloc(&dsim_dev->dev, sizeof(struct fw050), GFP_KERNEL);
++	if (!lcd)
++	{
++		dev_err(&dsim_dev->dev, "failed to allocate fitipower_fw050 structure.\n");
++		return -ENOMEM;
++	}
++
++	lcd->dsim_dev = dsim_dev;
++	lcd->dev = &dsim_dev->dev;
++
++	lcd->ld = lcd_device_register("fitipower_fw050", lcd->dev, lcd,
++	                              &panel_lcd_ops);
++	if (IS_ERR(lcd->ld))
++	{
++		dev_err(lcd->dev, "failed to register lcd ops.\n");
++		return PTR_ERR(lcd->ld);
++	}
++
++	dev_set_drvdata(&dsim_dev->dev, lcd);
++
++
++	dev_dbg(lcd->dev, "probed fitipower_fw050 panel driver.\n");
++
++
++	panel->dsim_dev = dsim_dev;
++
++
++	return 0;
++
++}
++
++static int panel_suspend(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	return 0;
++}
++
++static int panel_resume(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	return 0;
++}
++
++static struct mipi_dsim_lcd_driver panel_dev_dsim_ddi_driver = {
++	.name = "fitipower_fw050-lcd",
++	.id = -1,
++
++	.power_on = panel_dev_power_on,
++	.set_sequence = panel_dev_set_sequence,
++	.probe = panel_dev_probe,
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++
++#ifdef CONFIG_PM
++static int panel_pm_suspend(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++
++	panel_dev_display_off(panel);
++	panel_dev_sleep_in(panel);
++	gpio_direction_output(vdd_en->gpio, !vdd_en->active_level);
++
++	return 0;
++}
++
++static int panel_pm_resume(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_pm_suspend,
++	.resume = panel_pm_resume,
++};
++#endif
++
++struct mipi_dsim_lcd_device panel_dev_device={
++	.name		= "fitipower_fw050-lcd",
++	.id = 0,
++};
++
++/*
++* @panel_probe
++
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++
++* @pdev
++
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	PANEL_DEBUG_MSG("enter %s %d \n",__func__, __LINE__);
++
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	mipi_dsi_register_lcd_device(&panel_dev_device);
++	mipi_dsi_register_lcd_driver(&panel_dev_dsim_ddi_driver);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_of_parse;
++	}
++
++	return 0;
++
++err_of_parse:
++	if(gpio_is_valid(panel->lcd_pwm.gpio))
++		gpio_free(panel->lcd_pwm.gpio);
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,fw050", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "fw050",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
++
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-gc9203.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-gc9203.c
+new file mode 100644
+index 000000000..312c91fb2
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-gc9203.c
+@@ -0,0 +1,507 @@
++/*
++ * driver/video/fbdev/ingenic/fb_stage/displays/panel-gc9203.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * Author:zhxiao<zhihao.xiao@ingenic.com>
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++
++#include "../ingenicfb.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio cs;
++	struct board_gpio rst;
++	struct board_gpio vdd_en;
++	struct board_gpio vddio_en;
++	struct board_gpio pwm;
++};
++
++static struct smart_lcd_data_table gc9203_data_table[] = {
++
++    /* LCD init code */
++	{SMART_CONFIG_UDELAY, 120000},
++	{SMART_CONFIG_CMD, 0xff},
++	{SMART_CONFIG_PRM, 0x5a},
++	{SMART_CONFIG_PRM, 0xa5},
++
++	{SMART_CONFIG_CMD, 0xf6},
++	{SMART_CONFIG_PRM, 0x01},
++	{SMART_CONFIG_PRM, 0x12},
++
++	{SMART_CONFIG_CMD, 0xef},
++	{SMART_CONFIG_PRM, 0x14},
++	{SMART_CONFIG_PRM, 0x52},
++
++	{SMART_CONFIG_CMD, 0xa5},
++	{SMART_CONFIG_PRM, 0x07},
++	{SMART_CONFIG_PRM, 0x80},
++
++	{SMART_CONFIG_CMD, 0x02},
++	{SMART_CONFIG_PRM, 0x01},
++	{SMART_CONFIG_PRM, 0x00},
++
++	{SMART_CONFIG_CMD, 0x03},
++	{SMART_CONFIG_PRM, 0x10},	//0x10, 65k color, rgb565
++//	{SMART_CONFIG_PRM, 0x12},	//0x12, 262k color, rgb666
++	{SMART_CONFIG_PRM, 0x18},
++
++	{SMART_CONFIG_CMD, 0xf6},
++	{SMART_CONFIG_PRM, 0x01},
++	{SMART_CONFIG_PRM, 0x12},
++
++	{SMART_CONFIG_CMD, 0x11},
++	{SMART_CONFIG_PRM, 0x10},
++	{SMART_CONFIG_PRM, 0x00},
++
++	{SMART_CONFIG_CMD, 0xeb},
++	{SMART_CONFIG_PRM, 0x16},
++	{SMART_CONFIG_PRM, 0x0a},
++
++	{SMART_CONFIG_CMD, 0xec},
++	{SMART_CONFIG_PRM, 0x16},
++	{SMART_CONFIG_PRM, 0x0a},
++
++	{SMART_CONFIG_CMD, 0x50},
++	{SMART_CONFIG_PRM, 0xf9},
++	{SMART_CONFIG_PRM, 0x80},
++
++	{SMART_CONFIG_CMD, 0x51},
++	{SMART_CONFIG_PRM, 0x13},
++	{SMART_CONFIG_PRM, 0x06},
++
++	{SMART_CONFIG_CMD, 0x52},
++	{SMART_CONFIG_PRM, 0x0e},
++	{SMART_CONFIG_PRM, 0x09},
++
++	{SMART_CONFIG_CMD, 0x53},
++	{SMART_CONFIG_PRM, 0x33},
++	{SMART_CONFIG_PRM, 0x09},
++
++	{SMART_CONFIG_CMD, 0x54},
++	{SMART_CONFIG_PRM, 0x4e},
++	{SMART_CONFIG_PRM, 0x24},
++
++	{SMART_CONFIG_CMD, 0x55},
++	{SMART_CONFIG_PRM, 0x1b},
++	{SMART_CONFIG_PRM, 0x1c},
++
++	{SMART_CONFIG_CMD, 0x56},
++	{SMART_CONFIG_PRM, 0x37},
++	{SMART_CONFIG_PRM, 0x36},
++
++	{SMART_CONFIG_CMD, 0x57},
++	{SMART_CONFIG_PRM, 0xf5},
++	{SMART_CONFIG_PRM, 0x80},
++
++	{SMART_CONFIG_CMD, 0x58},
++	{SMART_CONFIG_PRM, 0x13},
++	{SMART_CONFIG_PRM, 0x06},
++
++	{SMART_CONFIG_CMD, 0x59},
++	{SMART_CONFIG_PRM, 0x0e},
++	{SMART_CONFIG_PRM, 0x13},
++
++	{SMART_CONFIG_CMD, 0x5a},
++	{SMART_CONFIG_PRM, 0x3f},
++	{SMART_CONFIG_PRM, 0x09},
++
++	{SMART_CONFIG_CMD, 0x5b},
++	{SMART_CONFIG_PRM, 0x52},
++	{SMART_CONFIG_PRM, 0x24},
++
++	{SMART_CONFIG_CMD, 0x5c},
++	{SMART_CONFIG_PRM, 0x0f},
++	{SMART_CONFIG_PRM, 0x0d},
++
++	{SMART_CONFIG_CMD, 0x5d},
++	{SMART_CONFIG_PRM, 0x37},
++	{SMART_CONFIG_PRM, 0x36},
++
++	{SMART_CONFIG_CMD, 0x07},
++	{SMART_CONFIG_PRM, 0x10},
++	{SMART_CONFIG_PRM, 0x13},
++
++	{SMART_CONFIG_CMD, 0x01},
++	{SMART_CONFIG_PRM, 0x01},
++	{SMART_CONFIG_PRM, 0x1c},
++
++	{SMART_CONFIG_CMD, 0xfe},
++
++/* set display resolution */
++/* 6.2.18. Horizontal and Vertical RAM Address Position (R36h/R37h,R38h/R39h) */
++	{SMART_CONFIG_CMD, 0x36},
++	{SMART_CONFIG_PRM, 0x00},
++	{SMART_CONFIG_PRM, 0x98},
++	{SMART_CONFIG_CMD, 0x37},
++	{SMART_CONFIG_PRM, 0x00},
++	{SMART_CONFIG_PRM, 0x18},
++
++	{SMART_CONFIG_UDELAY, 120000},
++
++	{SMART_CONFIG_CMD, 0x22},
++};
++
++
++static struct fb_videomode panel_modes[] = {
++	[0] = {
++		.name = "220x128",
++		.refresh = 60,
++		.xres = 220,
++		.yres = 128+1,
++		.pixclock = KHZ2PICOS(30000),
++		.left_margin = 0,
++		.right_margin = 0,
++		.upper_margin = 0,
++		.lower_margin = 0,
++		.hsync_len = 0,
++		.vsync_len = 0,
++		.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++		.vmode = FB_VMODE_NONINTERLACED,
++		.flag = 0,
++	},
++};
++
++struct smart_config gc9203_cfg = {
++	.te_anti_jit = 1,
++	.te_md = 1,
++	.te_dp = 1,
++	.te_switch = 0,
++	.dc_md = 0,
++	.wr_md = 1,
++	.smart_type = SMART_LCD_TYPE_SPI_4,
++	.pix_fmt = SMART_LCD_FORMAT_565,
++
++	.write_gram_cmd = 0x22222222,
++	.data_table = gc9203_data_table,
++	.length_data_table = ARRAY_SIZE(gc9203_data_table),
++};
++
++struct lcd_panel lcd_panel = {
++	.name = "gc9203",
++	.num_modes = ARRAY_SIZE(panel_modes),
++	.modes = panel_modes,
++	.lcd_type = LCD_TYPE_SLCD,
++	.width = 220,
++	.height = 128,
++
++	.smart_config = &gc9203_cfg,
++
++	.dither_enable = 0,
++	.dither.dither_red = 2,
++	.dither.dither_green = 1,
++	.dither.dither_blue = 2,
++};
++
++/* SGM3146 supports 16 brightness step */
++#define MAX_BRIGHTNESS_STEP     16
++/* System support 256 brightness step */
++#define CONVERT_FACTOR          (256/MAX_BRIGHTNESS_STEP)
++
++static int panel_update_status(struct backlight_device *bd)
++{
++	struct panel_dev *panel = dev_get_drvdata(&bd->dev);
++	int brightness = bd->props.brightness;
++	unsigned int i;
++	int pulse_num = MAX_BRIGHTNESS_STEP - brightness / CONVERT_FACTOR - 1;
++
++	if (bd->props.fb_blank == FB_BLANK_POWERDOWN) {
++		return 0;
++	}
++
++	if (bd->props.state & BL_CORE_SUSPENDED)
++		brightness = 0;
++
++	if (brightness) {
++		gpio_direction_output(panel->pwm.gpio,0);
++		udelay(5000);
++		gpio_direction_output(panel->pwm.gpio,1);
++		udelay(100);
++
++		for (i = pulse_num; i > 0; i--) {
++			gpio_direction_output(panel->pwm.gpio,0);
++			udelay(1);
++			gpio_direction_output(panel->pwm.gpio,1);
++			udelay(3);
++		}
++	} else
++		gpio_direction_output(panel->pwm.gpio, 0);
++
++	return 0;
++}
++
++static struct backlight_ops panel_backlight_ops = {
++	.options = BL_CORE_SUSPENDRESUME,
++	.update_status = panel_update_status,
++};
++
++static void panel_power_reset(struct board_gpio *rst)
++{
++	gpio_direction_output(rst->gpio, 0);
++	mdelay(20);
++	gpio_direction_output(rst->gpio, 1);
++	mdelay(10);
++}
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++	struct board_gpio *cs = &panel->cs;
++	struct board_gpio *rst = &panel->rst;
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *vddio_en = &panel->vddio_en;
++
++	if(POWER_IS_ON(power) && !POWER_IS_ON(panel->power)) {
++		gpio_direction_output(vdd_en->gpio, 1);
++		gpio_direction_output(vddio_en->gpio, 1);
++		gpio_direction_output(rst->gpio, 1);
++		gpio_direction_output(cs->gpio, 1);
++		mdelay(5);
++		panel_power_reset(rst);
++		gpio_direction_output(cs->gpio, 0);
++	}
++	if(!POWER_IS_ON(power) && POWER_IS_ON(panel->power)) {
++		gpio_direction_output(cs->gpio, 0);
++		gpio_direction_output(rst->gpio, 0);
++		gpio_direction_output(vddio_en->gpio, 0);
++		gpio_direction_output(vdd_en->gpio, 0);
++	}
++
++	panel->power = power;
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->cs.gpio = of_get_named_gpio_flags(np, "ingenic,cs-gpio", 0, &flags);
++	if(gpio_is_valid(panel->cs.gpio)) {
++		panel->cs.active_level = OF_GPIO_ACTIVE_LOW ? 0 : 1;
++		ret = gpio_request_one(panel->cs.gpio, GPIOF_DIR_OUT, "cs");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request cs pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio cs.gpio: %d\n", panel->cs.gpio);
++	}
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = OF_GPIO_ACTIVE_LOW ? 0 : 1;
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = OF_GPIO_ACTIVE_LOW ? 0 : 1;
++		ret = gpio_request_one(panel->vdd_en.gpio, GPIOF_DIR_OUT, "vdd_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	panel->vddio_en.gpio = of_get_named_gpio_flags(np, "ingenic,vddio-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vddio_en.gpio)) {
++		panel->vddio_en.active_level = OF_GPIO_ACTIVE_LOW ? 0 : 1;
++		ret = gpio_request_one(panel->vddio_en.gpio, GPIOF_DIR_OUT, "vddio_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vddio_en pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vddio_en.gpio: %d\n", panel->vddio_en.gpio);
++	}
++
++	panel->pwm.gpio = of_get_named_gpio_flags(np, "ingenic,pwm-gpio", 0, &flags);
++	if(gpio_is_valid(panel->pwm.gpio)) {
++		panel->pwm.active_level = OF_GPIO_ACTIVE_LOW ? 0 : 1;
++		ret = gpio_request_one(panel->pwm.gpio, GPIOF_DIR_OUT, "pwm");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request pwm pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio pwm.gpio: %d\n", panel->pwm.gpio);
++	}
++
++	return 0;
++err_request_rst:
++	gpio_free(panel->cs.gpio);
++	return ret;
++}
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	struct panel_dev *panel;
++	struct backlight_properties props;
++
++	memset(&props, 0, sizeof(props));
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	panel->lcd = lcd_device_register("panel_lcd", &pdev->dev, panel, &panel_lcd_ops);
++	if(IS_ERR_OR_NULL(panel->lcd)) {
++		dev_err(&pdev->dev, "Error register lcd!\n");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++	/* TODO: should this power status sync from uboot */
++	panel->power = FB_BLANK_POWERDOWN;
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++
++	props.type = BACKLIGHT_RAW;
++	props.max_brightness = 255;
++	panel->backlight = backlight_device_register("pwm-backlight.0",
++						&pdev->dev, panel,
++						&panel_backlight_ops,
++						&props);
++	if (IS_ERR_OR_NULL(panel->backlight)) {
++		dev_err(panel->dev, "failed to register 'pwm-backlight.0'.\n");
++		goto err_lcd_register;
++	}
++	panel->backlight->props.brightness = props.max_brightness;
++	backlight_update_status(panel->backlight);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++
++	return 0;
++
++err_lcd_register:
++	lcd_device_unregister(panel->lcd);
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	struct panel_dev *panel = dev_get_drvdata(&pdev->dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++
++#ifdef CONFIG_PM
++static int panel_suspend(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++static int panel_resume(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++#endif
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,gc9203", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "gc9203",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-gwmtf16499b.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-gwmtf16499b.c
+new file mode 100644
+index 000000000..ced590472
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-gwmtf16499b.c
+@@ -0,0 +1,304 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-gwmtf16499b.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++
++#include "../ingenicfb.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio pwm;
++};
++
++static void panel_enable(struct lcd_panel *panel)
++{
++}
++
++static void panel_disable(struct lcd_panel *panel)
++{
++}
++
++static struct lcd_panel_ops panel_ops = {
++	.enable  = (void*)panel_enable,
++	.disable = (void*)panel_disable,
++};
++
++static struct fb_videomode panel_modes[] = {
++	[0] = {
++		.name                   = "320x240",
++		.refresh                = 50,
++		.xres                   = 320,
++		.yres                   = 240,
++//		.pixclock               = KHZ2PICOS(33264),
++		.left_margin            = 10,
++		.right_margin           = 38,
++		.upper_margin           = 4,
++		.lower_margin           = 8,
++
++		.hsync_len              = 10,
++		.vsync_len              = 4,
++		.sync                   = ~FB_SYNC_HOR_HIGH_ACT & ~FB_SYNC_VERT_HIGH_ACT,
++		.vmode                  = FB_VMODE_NONINTERLACED,
++		.flag                   = 0,
++	},
++};
++
++static struct tft_config gwmtf16499b_cfg = {
++	.pix_clk_inv = 1,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++struct lcd_panel lcd_panel = {
++	.name = "gwmtf16499b",
++	.num_modes = ARRAY_SIZE(panel_modes),
++	.modes = panel_modes,
++	.bpp = 24,
++	.width = 320,
++	.height = 240,
++
++	.lcd_type = LCD_TYPE_TFT,
++
++	.tft_config = &gwmtf16499b_cfg,
++
++	.dither_enable = 1,
++	.dither.dither_red = 1,
++	.dither.dither_green = 1,
++	.dither.dither_blue = 1,
++
++	.ops = &panel_ops,
++};
++
++#define POWER_IS_ON(pwr)        (pwr)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++	/*struct board_gpio *pwm = &panel->pwm;*/
++    printk("%s, %d, power = %d, panel power = %d\n", __func__, __LINE__, power, panel->power);
++
++	if(POWER_IS_ON(power) && !POWER_IS_ON(panel->power)) {
++    printk("%s, %d, power = %d\n", __func__, __LINE__, power);
++		/*gpio_direction_output(pwm->gpio, 1);*/
++		gpio_direction_output(vdd_en->gpio, 0);
++	}
++	if(!POWER_IS_ON(power) && POWER_IS_ON(panel->power)) {
++    printk("%s, %d, power = %d\n", __func__, __LINE__, power);
++		gpio_direction_output(vdd_en->gpio, 1);
++		gpio_direction_output(rst->gpio, 1);
++	}
++
++	panel->power = power;
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++* @ pannel_gwmtf16499b_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->vdd_en.gpio, GPIOF_DIR_OUT, "vdd_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++#if 0
++	panel->pwm.gpio = of_get_named_gpio_flags(np, "ingenic,pwm-gpio", 0, &flags);
++	if(gpio_is_valid(panel->pwm.gpio)) {
++		panel->pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->pwm.gpio, GPIOF_DIR_OUT, "pwm");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request pwm pin!\n");
++			goto err_request_pwm;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio pwm.gpio: %d\n", panel->pwm.gpio);
++	}
++#endif
++
++	return 0;
++err_request_pwm:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++err_request_rst:
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++	return ret;
++}
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	struct panel_dev *panel;
++	struct backlight_properties props;
++
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	panel->lcd = lcd_device_register("panel_lcd", &pdev->dev, panel, &panel_lcd_ops);
++	if(IS_ERR_OR_NULL(panel->lcd)) {
++		dev_err(&pdev->dev, "Error register lcd!\n");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++
++	/* TODO: should this power status sync from uboot */
++	panel->power = FB_BLANK_POWERDOWN;
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++
++	return 0;
++
++err_lcd_register:
++	lcd_device_unregister(panel->lcd);
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	struct panel_dev *panel = dev_get_drvdata(&pdev->dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int panel_suspend(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++static int panel_resume(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++#endif
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,gwmtf16499b", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "gwmtf16499b",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-jd9161z.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-jd9161z.c
+new file mode 100644
+index 000000000..1f5b22311
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-jd9161z.c
+@@ -0,0 +1,528 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-jd9161z.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++#include <linux/fb.h>
++#include <linux/backlight.h>
++
++
++#include "../ingenicfb.h"
++#include "../jz_dsim.h"
++
++static int power_flag = 0;
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio lcd_te;
++	struct board_gpio lcd_pwm;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++};
++
++struct panel_dev *panel;
++
++#define lcd_to_master(a)	(a->dsim_dev->master)
++#define lcd_to_master_ops(a)	((lcd_to_master(a))->master_ops)
++
++struct jd9161z {
++	struct device *dev;
++	unsigned int power;
++	unsigned int id;
++
++	struct lcd_device *ld;
++	struct backlight_device *bd;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++
++};
++
++static struct dsi_cmd_packet fitipower_jd9161z_480_800_cmd_list1[] =
++{
++	{0x39, 0x04, 0x00, {0xDF, 0x91, 0x62, 0xF3}},//Delayms(1)
++	{0x39, 0x03, 0x00, {0xB2, 0x00, 0x92}}, //Set VCOM, Delayms(1);
++	{0x39, 0x03, 0x00, {0xB3, 0x00, 0x92}}, //Set VCOM_R, Delayms(1);
++	{0x39, 0x07, 0x00, {0xB7, 0x10, 0x1A, 0x49, 0x00, 0x50, 0x53}}, //Set Gamma Power, VGMP,VGMN,VGSP,VGSN, Delayms(1);(0x1A); //VGMP = 5V;(0x49); //VGSP = 0V,R(0x50); //VGMN = -5V,(0x53); //VGSN = -0V  33
++	{0x39, 0x07, 0x00, {0xB7, 0x10, 0x04, 0x33, 0x00, 0x3C, 0x67}}, //(0x04); VGMP = 5V,(0x33); //VGSP = 0V,(0x3C); //VGMN = -5V,(0x67); //VGSN = -0V  33
++	{0x39, 0x07, 0x00, {0xB7, 0x00, 0xF3, 0x22, 0x00, 0x17, 0x8C}},//Delayms(1);(0x00); //VGMP = 5V,(0x22); //VGSP = 0V,(0x17); //VGMN = -5V,(0x8C); //VGSN = -0V  33
++	{0x39, 0x0C, 0x00, {0xBB, 0x69, 0x1E, 0xB2, 0xB2, 0xB2, 0xC0, 0xC0, 0x20, 0x30, 0x50, 0x50}},//DCDC_CTRL RBBh,Delayms(1);(0x69);//68,C0  20200511,(0xC0);//E0  20200511,(0x20); //30  20200511,(0x30);//F0,(0x50);//F0,(0x50);//F0
++	{0x39, 0x0F, 0x00, {0xC3, 0x34, 0x0C, 0x0C, 0x1C, 0x00, 0x1C, 0x04, 0x1C, 0x1C, 0x00, 0x1C, 0x7F, 0x04, 0x7C}},
++	{0x39, 0x07, 0x00, {0xC4, 0x10, 0x90, 0x92, 0x0E, 0x12, 0x16}},//12:0e
++	{0x39, 0x27, 0x00, {0xC8, 0x7F, 0x73, 0x6A, 0x62, 0x64, 0x57, 0x60, 0x4B, 0x65, 0x63, 0x60, 0x79, 0x63, 0x63, 0x55, 0x40, 0x30, 0x1E, 0x00, 0x7F, 0x73, 0x6A, 0x62, 0x64, 0x57,  0x60, 0x4B, 0x65, 0x63, 0x60, 0x79, 0x63, 0x63, 0x55, 0x40, 0x30, 0x1E, 0x00}},//--- Gamma  ----//
++	{0x39, 0x11, 0x00, {0xD0, 0x15, 0x10, 0x35, 0x03, 0x1E, 0x1F, 0x01, 0x1F, 0x05, 0x07, 0x09, 0x0B, 0x1F, 0x1F, 0x1F, 0x1F}},//SET GIP_R,Delayms(1);
++		{0x39, 0x11, 0x00, {0xD1, 0x15, 0x10, 0x35, 0x02, 0x1E, 0x1F, 0x00, 0x1F, 0x04, 0x06, 0x08, 0x0A, 0x1F, 0x1F, 0x1F, 0x1F}},//SET GIP_L,Delayms(1);
++	{0x39, 0x11, 0x00, {0xD2, 0x1F, 0x02, 0x35, 0x10, 0x15, 0x1E, 0x00, 0x1F, 0x04, 0x0A, 0x08, 0x06, 0x1F, 0x1F, 0x1F, 0x1F}},//SET GIP_GS_L,Delayms(1);
++	{0x39, 0x11, 0x00, {0xD3, 0x1F, 0x03, 0x35, 0x10, 0x15, 0x1E, 0x01, 0x1F, 0x05, 0x0B, 0x09, 0x07, 0x1F, 0x1F, 0x1F, 0x1F}},//SET GIP_GS_R,Delayms(1);
++	{0x39, 0x1e, 0x00, {0xD4, 0x30, 0x00, 0x00, 0x00, 0x00, 0x08, 0x30, 0x00, 0x0A, 0x04, 0x6F, 0x04, 0x6F, 0x04, 0x30, 0x80, 0x00, 0x04, 0x6F, 0x73, 0x0C, 0x04, 0x6F, 0x0F, 0x25, 0x00, 0x63, 0x03, 0x00}},//Gip timing,Delayms(1);
++	{0x39, 0x21, 0x00, {0xD5, 0x01, 0x08, 0x80, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x06, 0x60, 0x00, 0x87, 0x50, 0x00, 0x83, 0xC0, 0x00, 0x60, 0x03, 0x00, 0x00, 0x00, 0x04, 0x6F, 0x06, 0x10, 0x00, 0x00, 0x0F, 0x4F, 0x00, 0x10, 0x1F, 0x3F}},//GIP Timing  ,
++#if 0
++	{0x39, 0x02, 0x00, {0xDE, 0x02}},//Page2
++	{0x39, 0x02, 0x00, {0xC1, 0x71}},//Delayms(1);
++	{0x39, 0x02, 0x00, {0xDE, 0x00}},//Page0
++#else
++		{0x15, 0xDE, 0x02},
++		{0x15, 0xC1, 0x71},
++		{0x15, 0xDE, 0x00},
++//		{0x15, 0xc2, 0x28},// color bar
++
++#endif
++
++};
++
++static struct dsi_cmd_packet fitipower_jd9161z_480_800_cmd_list2[] =
++{
++		{0x15, 0xDE, 0x02},
++		{0x15, 0xC1, 0x71},
++		{0x15, 0xDE, 0x00},
++//		{0x15, 0xc2, 0x28},// color bar
++};
++
++
++static void panel_dev_sleep_in(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x10, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_sleep_out(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x11, 0x00};
++//	struct dsi_cmd_packet data_to_send1 = {0x15, 0xc2, 0x20};//color bar test mode.
++//	while (1) {
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++//	ops->cmd_write(lcd_to_master(lcd), data_to_send1);
++//	}
++}
++
++static void panel_dev_display_on(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);//color bar turn off 0x29 command.
++	struct dsi_cmd_packet data_to_send = {0x05, 0x29, 0x00};
++	/* struct dsi_cmd_packet data_to_send1 = {0x15, 0x51, 250}; */
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++	/* ops->cmd_write(lcd_to_master(lcd), data_to_send1); */
++}
++
++static void panel_dev_display_off(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x28, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++
++static void panel_dev_panel_init(struct panel_dev *lcd)
++{
++	int  i;
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_device *dsi = lcd_to_master(lcd);
++
++	for (i = 0; i < ARRAY_SIZE(fitipower_jd9161z_480_800_cmd_list1); i++)
++	{
++		ops->cmd_write(dsi,  fitipower_jd9161z_480_800_cmd_list1[i]);
++	}
++//	msleep(20);
++//	for (i = 0; i < ARRAY_SIZE(fitipower_jd9161z_480_800_cmd_list2); i++)
++//	{
++//		ops->cmd_write(dsi,  fitipower_jd9161z_480_800_cmd_list2[i]);
++//	}
++}
++
++static int panel_dev_ioctl(struct mipi_dsim_lcd_device *dsim_dev, int cmd)
++{
++	return 0;
++}
++static void panel_dev_set_sequence(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct jd9161z *lcd = dev_get_drvdata(&dsim_dev->dev);
++
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++
++	panel_dev_panel_init(panel);
++	panel_dev_sleep_out(panel);
++	msleep(120);
++	panel_dev_display_on(panel);
++	msleep(5);
++	/* dump_dsi_reg(dsi); */
++	lcd->power = FB_BLANK_UNBLANK;
++}
++static void panel_dev_power_on(struct mipi_dsim_lcd_device *dsim_dev, int power)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++	struct board_gpio *lcd_te = &panel->lcd_te;
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	if (gpio_is_valid(lcd_te->gpio)) {
++		gpio_direction_input(lcd_te->gpio);
++	}
++	if(power){
++		msleep(50);
++		gpio_direction_output(rst->gpio, 0);
++		msleep(50);
++		gpio_direction_output(rst->gpio, 1);
++		msleep(120);
++	}
++
++	panel->power = power;
++}
++
++static struct fb_videomode panel_modes = {
++	.name = "fitipower_jd9161z-lcd",
++	.xres = 480,
++	.yres = 800,
++	.refresh = 60,
++
++	.left_margin = 20,//hbp
++	.right_margin = 20,//hfp
++	.hsync_len = 20, //hsync
++
++	.upper_margin = 16,//vbp
++	.lower_margin = 16,//vfp
++	.vsync_len = 4, //vsync
++
++	.sync                   = FB_SYNC_HOR_HIGH_ACT & FB_SYNC_VERT_HIGH_ACT,
++	.vmode                  = FB_VMODE_NONINTERLACED,
++	.flag = 0,
++};
++
++struct jzdsi_data jzdsi_pdata = {
++	.modes = &panel_modes,
++	.video_config.no_of_lanes = 2,
++	.video_config.virtual_channel = 0,
++	.video_config.color_coding = COLOR_CODE_24BIT,
++	.video_config.video_mode = VIDEO_BURST_WITH_SYNC_PULSES,
++	.video_config.receive_ack_packets = 0,	/* enable receiving of ack packets */
++	.video_config.is_18_loosely = 0,
++	.video_config.data_en_polarity = 1,
++	.video_config.byte_clock = 0, // driver will auto calculate byte_clock.
++	.video_config.byte_clock_coef = MIPI_PHY_BYTE_CLK_COEF_MUL3_DIV2, // byte_clock *3/2.
++
++	.dsi_config.max_lanes = 2,
++	.dsi_config.max_hs_to_lp_cycles = 100,
++	.dsi_config.max_lp_to_hs_cycles = 40,
++//	.dsi_config.max_hs_to_lp_cycles = 200,
++//	.dsi_config.max_lp_to_hs_cycles = 80,
++	.dsi_config.max_bta_cycles = 4095,
++	.dsi_config.color_mode_polarity = 1,
++	.dsi_config.shut_down_polarity = 1,
++	.dsi_config.max_bps = 2750,
++//	.max_bps = 650,  // 650 Mbps
++	.bpp_info = 24,
++};
++static struct tft_config kd050hdfia019_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++
++struct lcd_panel lcd_panel = {
++	.num_modes = 1,
++	.modes = &panel_modes,
++	.dsi_pdata = &jzdsi_pdata,
++
++	.lcd_type = LCD_TYPE_MIPI_TFT,
++	.tft_config = &kd050hdfia019_cfg,
++	.bpp = 24,
++//	.width = 700,
++//	.height = 1230,
++	.width = 68,
++	.height = 121,
++	.dither_enable = 0,
++	.dither.dither_red = 0,
++	.dither.dither_green = 0,
++	.dither.dither_blue = 0,
++
++
++};
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++* @ pannel_jd9161z_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++#ifndef CONFIG_SOC_X2500
++	*(volatile  unsigned int * )0xb0010188 = (0x1 << 27); //lcd_te high impedance config.
++	*(volatile  unsigned int * )0xb0010198 = (0x1 << 27);
++#endif
++	panel->lcd_te.gpio = of_get_named_gpio_flags(np, "ingenic,lcd-te-gpio", 0, &flags);
++	if(gpio_is_valid(panel->lcd_te.gpio)) {
++		panel->lcd_te.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++
++	} else {
++		dev_warn(dev, "invalid gpio lcd_te.gpio: %d\n", panel->lcd_te.gpio);
++	}
++
++	panel->lcd_pwm.gpio = of_get_named_gpio_flags(np, "ingenic,lcd-pwm-gpio", 0, &flags);
++	if(gpio_is_valid(panel->lcd_pwm.gpio)) {
++		panel->lcd_pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_direction_output(panel->lcd_pwm.gpio,1);
++		if(ret < 0) {
++			dev_err(dev, "Failed to request lcd-pwm pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio lcd-pwm.gpio: %d\n", panel->lcd_pwm.gpio);
++	}
++
++
++	return 0;
++err_request_lcd_te:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++err_request_rst:
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++	return ret;
++}
++
++#define JD9161ZID       0x001A6191
++static int panel_detect_id(struct mipi_dsim_lcd_device *dsim_dev, unsigned char *buf, int count)
++{
++	int ret = 0;
++	unsigned int *id = NULL;
++
++	struct dsi_master_ops *ops = dsim_dev->master->master_ops;
++	struct dsi_cmd_packet set_max_return_packet_size = {0x37, 0x04, 0x00};	//设置最大回读byte数.
++	struct dsi_cmd_packet data_to_send0 = {0x14, 0x04, 0x00};
++	struct dsi_cmd_packet data_to_send1 = {0x14, 0x04, 0x01};
++	struct dsi_cmd_packet data_to_send2 = {0x14, 0x04, 0x02};
++
++	if(!power_flag){
++		panel_dev_power_on(dsim_dev, 1);
++		power_flag = 1;
++	}
++	ret = ops->cmd_write(dsim_dev->master, set_max_return_packet_size);
++	ret = ops->cmd_read(dsim_dev->master, data_to_send0, &buf[0], 4);
++
++	id=(unsigned int *)buf;
++	if(*id == JD9161ZID)
++		return 0;
++	return -1;
++}
++
++static int panel_dev_probe(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct jd9161z *lcd;
++	int ret = 0;
++	char buffer[4];
++	ret = panel_detect_id(dsim_dev, buffer, 4);
++	if(ret < 0) {
++		return -EINVAL;
++	}
++
++	lcd = devm_kzalloc(&dsim_dev->dev, sizeof(struct jd9161z), GFP_KERNEL);
++	if (!lcd)
++	{
++		dev_err(&dsim_dev->dev, "failed to allocate fitipower_jd9161z structure.\n");
++		return -ENOMEM;
++	}
++
++	lcd->dsim_dev = dsim_dev;
++	lcd->dev = &dsim_dev->dev;
++
++	lcd->ld = lcd_device_register("fitipower_jd9161z", lcd->dev, lcd,
++	                              &panel_lcd_ops);
++	if (IS_ERR(lcd->ld))
++	{
++		dev_err(lcd->dev, "failed to register lcd ops.\n");
++		return PTR_ERR(lcd->ld);
++	}
++
++	dev_set_drvdata(&dsim_dev->dev, lcd);
++
++
++	dev_dbg(lcd->dev, "probed fitipower_jd9161z panel driver.\n");
++
++
++	panel->dsim_dev = dsim_dev;
++
++
++	return 0;
++
++}
++
++static int panel_suspend(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++	panel_dev_display_off(panel);
++	panel_dev_sleep_in(panel);
++	gpio_direction_output(vdd_en->gpio, !vdd_en->active_level);
++
++	return 0;
++}
++
++static int panel_resume(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	return 0;
++}
++
++static struct mipi_dsim_lcd_driver panel_dev_dsim_ddi_driver = {
++	.name = "fitipower_jd9161z-lcd",
++	.id = -1,
++
++	.power_on = panel_dev_power_on,
++	.set_sequence = panel_dev_set_sequence,
++	.probe = panel_dev_probe,
++//	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++
++
++struct mipi_dsim_lcd_device panel_dev_device={
++	.name		= "fitipower_jd9161z-lcd",
++	.id = 0,
++};
++
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	mipi_dsi_register_lcd_device(&panel_dev_device);
++	mipi_dsi_register_lcd_driver(&panel_dev_dsim_ddi_driver);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_of_parse;
++	}
++
++	return 0;
++
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,jd9161z", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "jd9161z",
++		.of_match_table = panel_of_match,
++	},
++};
++
++module_platform_driver(panel_driver);
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-jd9366.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-jd9366.c
+new file mode 100644
+index 000000000..e9cc21bda
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-jd9366.c
+@@ -0,0 +1,749 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-jd9366.c
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ * This program is free software, you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++#include <linux/fb.h>
++#include <linux/backlight.h>
++
++
++#include "../ingenicfb.h"
++#include "../jz_dsim.h"
++
++static int test = 0;
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio lcd_te;
++	struct board_gpio lcd_pwm;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++};
++
++struct panel_dev *panel;
++
++#define lcd_to_master(a)	(a->dsim_dev->master)
++#define lcd_to_master_ops(a)	((lcd_to_master(a))->master_ops)
++
++struct jd9366 {
++	struct device *dev;
++	unsigned int power;
++	unsigned int id;
++
++	struct lcd_device *ld;
++	struct backlight_device *bd;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++
++};
++
++static struct dsi_cmd_packet fitipower_jd9366_800_1280_cmd_list1[] =
++{
++		//Page0
++	{0x15,0xE0,0x00},
++
++	//--- PASSWORD  ----//
++	{0x15, 0xE1,0x93},
++	{0x15, 0xE2,0x65},
++	{0x15, 0xE3,0xF8},
++
++
++	//Page0
++	{0x15, 0xE0,0x00},
++	//--- Sequence Ctrl  ----//
++	{0x15, 0x70,0x10},	//DC0,DC1
++	{0x15, 0x71,0x13},	//DC2,DC3
++	{0x15, 0x72,0x06},	//DC7
++
++	{0x15, 0x80,0x03},	//0x03:4-Laneï¼›0x02:3-Lane ; 0x01 : 2-lane
++	//--- Page4  ----//
++	{0x15, 0xE0,0x04},
++	{0x15, 0x2D,0x03},
++	//--- Page1  ----//
++	{0x15, 0xE0,0x01},
++
++	//Set VCOM
++	{0x15, 0x00,0x00},
++	{0x15, 0x01,0xA0},
++	//Set VCOM_Reverse
++	{0x15, 0x03,0x00},
++	{0x15, 0x04,0xA0},
++
++	//Set Gamma Power, VGMP,VGMN,VGSP,VGSN
++	{0x15, 0x17,0x00},
++	{0x15, 0x18,0xB1},
++	{0x15, 0x19,0x01},
++	{0x15, 0x1A,0x00},
++	{0x15, 0x1B,0xB1},  //VGMN=0
++	{0x15, 0x1C,0x01},
++	//Set Gate Power
++	{0x15, 0x1F,0x3E},     //VGH_R  = 15V
++	{0x15, 0x20,0x2D},     //VGL_R  = -12V
++	{0x15, 0x21,0x2D},     //VGL_R2 = -12V
++	{0x15, 0x22,0x0E},     //PA[6]=0, PA[5]=0, PA[4]=0, PA[0]=0
++
++	//SETPANEL
++	{0x15, 0x37,0x19},	//SS=1,BGR=1
++
++	//SET RGBCYC
++	{0x15, 0x38,0x05},	//JDT=101 zigzag inversion
++	{0x15, 0x39,0x08},	//RGB_N_EQ1, modify 20140806
++	{0x15, 0x3A,0x12},	//RGB_N_EQ2, modify 20140806
++	{0x15, 0x3C,0x78},	//SET EQ3 for TE_H
++	{0x15, 0x3E,0x80},	//SET CHGEN_OFF, modify 20140806
++	{0x15, 0x3F,0x80},	//SET CHGEN_OFF2, modify 20140806 --------------
++
++
++	//Set TCON
++	{0x15, 0x40,0x06},	//RSO=800 RGB
++	{0x15, 0x41,0xA0},	//LN=640->1280 line
++
++	//--- power voltage  ----//
++	{0x15, 0x55,0x01},	//DCDCM=0001, JD PWR_IC
++	{0x15, 0x56,0x01},
++	{0x15, 0x57,0x69},
++	{0x15, 0x58,0x0A},
++	{0x15, 0x59,0x0A},	//VCL = -2.9V
++	{0x15, 0x5A,0x28},	//VGH = 19V
++	{0x15, 0x5B,0x19},	//VGL = -11V
++
++
++
++	//--- Gamma  ----//
++	{0x15, 0x5D,0x7C},
++	{0x15, 0x5E,0x65},
++	{0x15, 0x5F,0x53},
++	{0x15, 0x60,0x48},
++	{0x15, 0x61,0x43},
++	{0x15, 0x62,0x35},
++	{0x15, 0x63,0x39},
++	{0x15, 0x64,0x23},
++	{0x15, 0x65,0x3D},
++	{0x15, 0x66,0x3C},
++	{0x15, 0x67,0x3D},
++	{0x15, 0x68,0x5A},
++	{0x15, 0x69,0x46},
++	{0x15, 0x6A,0x57},
++	{0x15, 0x6B,0x4B},
++	{0x15, 0x6C,0x49},
++	{0x15, 0x6D,0x2F},
++	{0x15, 0x6E,0x03},
++	{0x15, 0x6F,0x00},
++	{0x15, 0x70,0x7C},
++	{0x15, 0x71,0x65},
++	{0x15, 0x72,0x53},
++	{0x15, 0x73,0x48},
++	{0x15, 0x74,0x43},
++	{0x15, 0x75,0x35},
++	{0x15, 0x76,0x39},
++	{0x15, 0x77,0x23},
++	{0x15, 0x78,0x3D},
++	{0x15, 0x79,0x3C},
++	{0x15, 0x7A,0x3D},
++	{0x15, 0x7B,0x5A},
++	{0x15, 0x7C,0x46},
++	{0x15, 0x7D,0x57},
++	{0x15, 0x7E,0x4B},
++	{0x15, 0x7F,0x49},
++	{0x15, 0x80,0x2F},
++	{0x15, 0x81,0x03},
++	{0x15, 0x82,0x00},
++
++
++	//Page2, for GIP
++	{0x15, 0xE0,0x02},
++
++	//GIP_L Pin mapping
++	{0x15, 0x00,0x47},
++	{0x15, 0x01,0x47},
++	{0x15, 0x02,0x45},
++	{0x15, 0x03,0x45},
++	{0x15, 0x04,0x4B},
++	{0x15, 0x05,0x4B},
++	{0x15, 0x06,0x49},
++	{0x15, 0x07,0x49},
++	{0x15, 0x08,0x41},
++	{0x15, 0x09,0x1F},
++	{0x15, 0x0A,0x1F},
++	{0x15, 0x0B,0x1F},
++	{0x15, 0x0C,0x1F},
++	{0x15, 0x0D,0x1F},
++	{0x15, 0x0E,0x1F},
++	{0x15, 0x0F,0x43},
++	{0x15, 0x10,0x1F},
++	{0x15, 0x11,0x1F},
++	{0x15, 0x12,0x1F},
++	{0x15, 0x13,0x1F},
++	{0x15, 0x14,0x1F},
++	{0x15, 0x15,0x1F},
++
++	//GIP_R Pin mapping
++	{0x15, 0x16,0x46},
++	{0x15, 0x17,0x46},
++	{0x15, 0x18,0x44},
++	{0x15, 0x19,0x44},
++	{0x15, 0x1A,0x4A},
++	{0x15, 0x1B,0x4A},
++	{0x15, 0x1C,0x48},
++	{0x15, 0x1D,0x48},
++	{0x15, 0x1E,0x40},
++	{0x15, 0x1F,0x1F},
++	{0x15, 0x20,0x1F},
++	{0x15, 0x21,0x1F},
++	{0x15, 0x22,0x1F},
++	{0x15, 0x23,0x1F},
++	{0x15, 0x24,0x1F},
++	{0x15, 0x25,0x42},
++	{0x15, 0x26,0x1F},
++	{0x15, 0x27,0x1F},
++	{0x15, 0x28,0x1F},
++	{0x15, 0x29,0x1F},
++	{0x15, 0x2A,0x1F},
++	{0x15, 0x2B,0x1F},
++	//GIP_L_GS Pin mapping
++	{0x15, 0x2C,0x11},
++	{0x15, 0x2D,0x0F},
++	{0x15, 0x2E,0x0D},
++	{0x15, 0x2F,0x0B},
++	{0x15, 0x30,0x09},
++	{0x15, 0x31,0x07},
++	{0x15, 0x32,0x05},
++	{0x15, 0x33,0x18},
++	{0x15, 0x34,0x17},
++	{0x15, 0x35,0x1F},
++	{0x15, 0x36,0x01},
++	{0x15, 0x37,0x1F},
++	{0x15, 0x38,0x1F},
++	{0x15, 0x39,0x1F},
++	{0x15, 0x3A,0x1F},
++	{0x15, 0x3B,0x1F},
++	{0x15, 0x3C,0x1F},
++	{0x15, 0x3D,0x1F},
++	{0x15, 0x3E,0x1F},
++	{0x15, 0x3F,0x13},
++	{0x15, 0x40,0x1F},
++	{0x15, 0x41,0x1F},
++	//GIP_R_GS Pin mapping
++	{0x15, 0x42,0x10},
++	{0x15, 0x43,0x0E},
++	{0x15, 0x44,0x0C},
++	{0x15, 0x45,0x0A},
++	{0x15, 0x46,0x08},
++	{0x15, 0x47,0x06},
++	{0x15, 0x48,0x04},
++	{0x15, 0x49,0x18},
++	{0x15, 0x4A,0x17},
++	{0x15, 0x4B,0x1F},
++	{0x15, 0x4C,0x00},
++	{0x15, 0x4D,0x1F},
++	{0x15, 0x4E,0x1F},
++	{0x15, 0x4F,0x1F},
++	{0x15, 0x50,0x1F},
++	{0x15, 0x51,0x1F},
++	{0x15, 0x52,0x1F},
++	{0x15, 0x53,0x1F},
++	{0x15, 0x54,0x1F},
++	{0x15, 0x55,0x12},
++	{0x15, 0x56,0x1F},
++	{0x15, 0x57,0x1F},
++
++	//GIP Timing
++	{0x15, 0x58,0x40},
++	{0x15, 0x59,0x00},
++	{0x15, 0x5A,0x00},
++	{0x15, 0x5B,0x30},
++	{0x15, 0x5C,0x03},
++	{0x15, 0x5D,0x30},
++	{0x15, 0x5E,0x01},
++	{0x15, 0x5F,0x02},
++	{0x15, 0x60,0x00},
++	{0x15, 0x61,0x01},
++	{0x15, 0x62,0x02},
++	{0x15, 0x63,0x03},
++	{0x15, 0x64,0x6B},
++	{0x15, 0x65,0x00},
++	{0x15, 0x66,0x00},
++	{0x15, 0x67,0x73},
++	{0x15, 0x68,0x05},
++	{0x15, 0x69,0x06},
++	{0x15, 0x6A,0x6B},
++	{0x15, 0x6B,0x08},
++	{0x15, 0x6C,0x00},
++	{0x15, 0x6D,0x04},
++	{0x15, 0x6E,0x04},
++	{0x15, 0x6F,0x88},
++	{0x15, 0x70,0x00},
++	{0x15, 0x71,0x00},
++	{0x15, 0x72,0x06},
++	{0x15, 0x73,0x7B},
++	{0x15, 0x74,0x00},
++	{0x15, 0x75,0x07},
++	{0x15, 0x76,0x00},
++	{0x15, 0x77,0x5D},
++	{0x15, 0x78,0x17},
++	{0x15, 0x79,0x1F},
++	{0x15, 0x7A,0x00},
++	{0x15, 0x7B,0x00},
++	{0x15, 0x7C,0x00},
++	{0x15, 0x7D,0x03},
++	{0x15, 0x7E,0x7B},
++
++
++	//Page1
++	{0x15, 0xE0,0x01},
++	{0x15, 0x0E,0x01},	//LEDON output VCSW2
++
++
++	//Page3
++	{0x15, 0xE0,0x03},
++	{0x15, 0x98,0x2F},	//From 2E to 2F, LED_VOL
++
++	//Page4
++	{0x15, 0xE0,0x04},
++	{0x15, 0x09,0x10},
++	{0x15, 0x2B,0x2B},
++	{0x15, 0x2E,0x44},
++
++	//Page0
++	{0x15, 0xE0,0x00},
++	{0x15, 0xE6,0x02},
++	{0x15, 0xE7,0x02},
++
++	{0x15,0x51,0xFF},
++	{0x15,0x53,0x2C},
++	{0x15,0x55,0x01},
++
++};
++
++
++static void panel_dev_sleep_in(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x10, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_sleep_out(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x11, 0x00};
++	/* struct dsi_cmd_packet data_to_send1 = {0x15, 0xc2, 0x20};//color bar test mode. */
++//	while (1) {
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++	/* ops->cmd_write(lcd_to_master(lcd), data_to_send1); */
++//	}
++}
++
++static void panel_dev_display_on(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);//color bar turn off 0x29 command.
++	struct dsi_cmd_packet data_to_send = {0x05, 0x29, 0x00};
++	/* struct dsi_cmd_packet data_to_send1 = {0x15, 0x51, 250}; */
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++	/* ops->cmd_write(lcd_to_master(lcd), data_to_send1); */
++}
++
++static void panel_dev_display_off(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x28, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static int panel_dev_rdid(struct panel_dev *lcd, unsigned char *buf, int count)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++
++	struct dsi_cmd_packet data_to_send0 = {0x14, 0xDA, 0x0};
++	struct dsi_cmd_packet data_to_send1 = {0x14, 0xDB, 0x0};
++	struct dsi_cmd_packet data_to_send2 = {0x14, 0xDC, 0x0};
++	int ret = 0;
++
++	ret = ops->cmd_read(lcd_to_master(lcd), data_to_send0, &buf[0], 1);
++	ret = ops->cmd_read(lcd_to_master(lcd), data_to_send1, &buf[1], 1);
++	ret = ops->cmd_read(lcd_to_master(lcd), data_to_send2, &buf[2], 1);
++	printk("----------%s, %d id[0]: %x id[1]: %x, id[2]: %x, id[3]: %x\n", __func__, __LINE__, buf[0], buf[1], buf[2], buf[3]);
++
++	return ret;
++}
++
++static void panel_dev_panel_init(struct panel_dev *lcd)
++{
++	int  i;
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_device *dsi = lcd_to_master(lcd);
++
++	char id[4];
++
++	memset(id, 0, 4);
++
++	panel_dev_rdid(lcd, id, 4);
++
++	for (i = 0; i < ARRAY_SIZE(fitipower_jd9366_800_1280_cmd_list1); i++)
++	{
++		ops->cmd_write(dsi,  fitipower_jd9366_800_1280_cmd_list1[i]);
++	}
++}
++
++static int panel_dev_ioctl(struct mipi_dsim_lcd_device *dsim_dev, int cmd)
++{
++	return 0;
++}
++static void panel_dev_set_sequence(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct jd9366 *lcd = dev_get_drvdata(&dsim_dev->dev);
++
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++	if(test != 0)
++		return;
++	test++;
++
++	panel_dev_panel_init(panel);
++	panel_dev_sleep_out(panel);
++	msleep(120);
++	panel_dev_display_on(panel);
++	msleep(5);
++	/* dump_dsi_reg(dsi); */
++	lcd->power = FB_BLANK_UNBLANK;
++}
++static void panel_dev_power_on(struct mipi_dsim_lcd_device *dsim_dev, int power)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++	struct board_gpio *lcd_te = &panel->lcd_te;
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++
++	if(test != 0)
++		return;
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	if (gpio_is_valid(lcd_te->gpio)) {
++		gpio_direction_input(lcd_te->gpio);
++	}
++	msleep(50);
++	gpio_direction_output(rst->gpio, 0);
++	msleep(10);
++	gpio_direction_output(rst->gpio, 1);
++	msleep(120);
++
++	panel->power = power;
++}
++
++static struct fb_videomode panel_modes = {
++	.name = "fitipower_jd9366-lcd",
++	.xres = 800,
++	.yres = 1280,
++
++	.refresh = 60,
++	.left_margin = 20,//hbp
++	.right_margin = 32,//hfp
++	.hsync_len =20,//hsync
++
++	.upper_margin = 4,//vbp
++	.lower_margin = 8,//vfp
++	.vsync_len = 4, //vsync
++
++	.sync                   = FB_SYNC_HOR_HIGH_ACT & FB_SYNC_VERT_HIGH_ACT,
++	.vmode                  = FB_VMODE_NONINTERLACED,
++	.flag = 0,
++};
++
++struct jzdsi_data jzdsi_pdata = {
++	.modes = &panel_modes,
++	.video_config.no_of_lanes = 4,
++	.video_config.virtual_channel = 0,
++	.video_config.color_coding = COLOR_CODE_24BIT,
++	/* .video_config.video_mode = VIDEO_NON_BURST_WITH_SYNC_PULSES, */
++	.video_config.video_mode = VIDEO_BURST_WITH_SYNC_PULSES,
++	.video_config.receive_ack_packets = 0,	/* enable receiving of ack packets */
++	.video_config.is_18_loosely = 0,
++	.video_config.data_en_polarity = 1,
++	.video_config.byte_clock = 0, // driver will auto calculate byte_clock.
++	.video_config.byte_clock_coef = MIPI_PHY_BYTE_CLK_COEF_MUL3_DIV2, // byte_clock *3/2.
++
++	.dsi_config.max_lanes = 4,
++	.dsi_config.max_hs_to_lp_cycles = 100,
++	.dsi_config.max_lp_to_hs_cycles = 40,
++	//.dsi_config.max_hs_to_lp_cycles = 200,
++	//.dsi_config.max_lp_to_hs_cycles = 80,
++	.dsi_config.max_bta_cycles = 4095,
++	.dsi_config.color_mode_polarity = 1,
++	.dsi_config.shut_down_polarity = 1,
++	.dsi_config.max_bps = 2750,
++//	.max_bps = 650,  // 650 Mbps
++	.bpp_info = 24,
++};
++static struct tft_config kd050hdfia019_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++
++struct lcd_panel lcd_panel = {
++	.num_modes = 1,
++	.modes = &panel_modes,
++	.dsi_pdata = &jzdsi_pdata,
++
++	.lcd_type = LCD_TYPE_MIPI_TFT,
++	.tft_config = &kd050hdfia019_cfg,
++	.bpp = 24,
++	.width = 107,
++	.height = 172,
++	.dither_enable = 0,
++	.dither.dither_red = 0,
++	.dither.dither_green = 0,
++	.dither.dither_blue = 0,
++
++
++};
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/*
++* @ pannel_jd9366_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		gpio_direction_output(panel->rst.gpio,0);
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		gpio_direction_output(panel->vdd_en.gpio, !panel->vdd_en.active_level);
++		ret = gpio_request_one(panel->vdd_en.gpio, GPIOF_DIR_OUT, "vdd_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	/* panel->lcd_pwm.gpio = of_get_named_gpio_flags(np, "ingenic,lcd-pwm-gpio", 0, &flags); */
++	/* if(gpio_is_valid(panel->lcd_pwm.gpio)) { */
++	/* 	panel->lcd_pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1; */
++	/* 	ret = gpio_request_one(panel->lcd_pwm.gpio, GPIOF_DIR_OUT, "lcd-pwm"); */
++	/* 	ret = gpio_direction_output(panel->lcd_pwm.gpio,0); */
++	/* 	if(ret < 0) { */
++	/* 		dev_err(dev, "Failed to request lcd-pwm pin!\n"); */
++	/* 		return ret; */
++	/* 	} */
++	/* } else { */
++	/* 	dev_warn(dev, "invalid gpio lcd-pwm.gpio: %d\n", panel->lcd_pwm.gpio); */
++	/* } */
++
++
++	return 0;
++err_request_lcd_te:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++err_request_rst:
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++	return ret;
++}
++
++static int panel_dev_probe(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct jd9366 *lcd;
++	lcd = devm_kzalloc(&dsim_dev->dev, sizeof(struct jd9366), GFP_KERNEL);
++	if (!lcd)
++	{
++		dev_err(&dsim_dev->dev, "failed to allocate fitipower_jd9366 structure.\n");
++		return -ENOMEM;
++	}
++
++	lcd->dsim_dev = dsim_dev;
++	lcd->dev = &dsim_dev->dev;
++
++	lcd->ld = lcd_device_register("fitipower_jd9366", lcd->dev, lcd,
++	                              &panel_lcd_ops);
++	if (IS_ERR(lcd->ld))
++	{
++		dev_err(lcd->dev, "failed to register lcd ops.\n");
++		return PTR_ERR(lcd->ld);
++	}
++
++	dev_set_drvdata(&dsim_dev->dev, lcd);
++
++
++	dev_dbg(lcd->dev, "probed fitipower_jd9366 panel driver.\n");
++
++
++	panel->dsim_dev = dsim_dev;
++
++
++	return 0;
++
++}
++
++static int panel_suspend(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++	panel_dev_display_off(panel);
++	panel_dev_sleep_in(panel);
++	gpio_direction_output(vdd_en->gpio, !vdd_en->active_level);
++
++	return 0;
++}
++
++static int panel_resume(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	return 0;
++}
++
++static struct mipi_dsim_lcd_driver panel_dev_dsim_ddi_driver = {
++	.name = "fitipower_jd9366-lcd",
++	.id = -1,
++
++	.power_on = panel_dev_power_on,
++	.set_sequence = panel_dev_set_sequence,
++	.probe = panel_dev_probe,
++//	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++
++
++struct mipi_dsim_lcd_device panel_dev_device={
++	.name		= "fitipower_jd9366-lcd",
++	.id = 0,
++};
++
++/*
++* @panel_probe
++
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++
++* @pdev
++
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	mipi_dsi_register_lcd_device(&panel_dev_device);
++	mipi_dsi_register_lcd_driver(&panel_dev_dsim_ddi_driver);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_of_parse;
++	}
++
++	return 0;
++
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,jd9366", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "jd9366",
++		.of_match_table = panel_of_match,
++	},
++};
++
++module_platform_driver(panel_driver);
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd035hvfbd037.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd035hvfbd037.c
+new file mode 100644
+index 000000000..035efc3b4
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd035hvfbd037.c
+@@ -0,0 +1,563 @@
++/*
++ * driver/video/fbdev/ingenic/fb_v12/displays/kd035hvfbd037.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * Author:clwang<chunlei.wang@ingenic.com>
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++
++#include "../ingenicfb.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio cs;
++	struct board_gpio rst;
++	struct board_gpio vdd_en;
++	struct board_gpio vddio_en;
++	struct board_gpio pwm;
++};
++
++static struct smart_lcd_data_table kd035hvfbd037_data_table[] = {
++/* LCD init code */
++	{SMART_CONFIG_UDELAY, 12000},
++	{SMART_CONFIG_CMD    , 0xff},   //Command 2 Enable
++	{SMART_CONFIG_PRM    , 0x48},
++	{SMART_CONFIG_PRM   , 0x02},
++	{SMART_CONFIG_PRM   , 0x01},
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0x80},
++	{SMART_CONFIG_CMD    , 0xff},  //ORISE Command Enable
++	{SMART_CONFIG_PRM   , 0x48},
++	{SMART_CONFIG_PRM   , 0x02},
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0x90},
++	{SMART_CONFIG_CMD    , 0xFF},  //MPU 16bit setting
++	{SMART_CONFIG_PRM   , 0x01},	//02-16BIT MCU,01-8BIT MCU
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0x93},
++	{SMART_CONFIG_CMD    , 0xFF},  //SW MPU enable
++	{SMART_CONFIG_PRM   , 0x20},
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0x00},
++	{SMART_CONFIG_CMD    , 0x51},    //Wright Display brightness
++	{SMART_CONFIG_PRM   , 0xf0},
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0x00},
++	{SMART_CONFIG_CMD    , 0x53},   // Wright CTRL Display
++	{SMART_CONFIG_PRM   , 0x24},
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM  , 0xb1},
++	{SMART_CONFIG_CMD    , 0xc5},   //VSEL setting
++	{SMART_CONFIG_PRM   , 0x00},
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0xB0},
++	{SMART_CONFIG_CMD    , 0xc4},   //Gate Timing control
++	{SMART_CONFIG_PRM   , 0x02},
++	{SMART_CONFIG_PRM   , 0x08},
++	{SMART_CONFIG_PRM   , 0x05},
++	{SMART_CONFIG_PRM   , 0x00},
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0x90},
++	{SMART_CONFIG_CMD    , 0xc0},   //TCON MCLK Shift Control
++	{SMART_CONFIG_PRM   , 0x00},
++	{SMART_CONFIG_PRM   , 0x0f},
++	{SMART_CONFIG_PRM   , 0x00},
++	{SMART_CONFIG_PRM   , 0x15},
++	{SMART_CONFIG_PRM   , 0x00},
++	{SMART_CONFIG_PRM   , 0x17},
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0x82},
++	{SMART_CONFIG_CMD    , 0xc5},  //Adjust pump phase
++	{SMART_CONFIG_PRM   , 0x01},
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0x90},
++	{SMART_CONFIG_CMD    , 0xc5},  //Adjust pump phase
++	{SMART_CONFIG_PRM   , 0x47},
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0x00},
++	{SMART_CONFIG_CMD    , 0xd8},  //GVDD/NGVDD Setting
++	{SMART_CONFIG_PRM   , 0x58},  //58,17V
++	{SMART_CONFIG_PRM   , 0x58},  //58
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0x00},
++	{SMART_CONFIG_CMD    , 0xd9},  //VCOM Setting
++	{SMART_CONFIG_PRM   , 0xb0},  //
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0x91},
++	{SMART_CONFIG_CMD    , 0xb3},  //Display setting
++	{SMART_CONFIG_PRM   , 0xC0},
++	{SMART_CONFIG_PRM   , 0x25},
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0x81},
++	{SMART_CONFIG_CMD    , 0xC1}, //Osillator Adjustment:70Hz
++	{SMART_CONFIG_PRM   , 0x77},
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0x00},
++	{SMART_CONFIG_CMD    , 0xe1},   //Gamma setting                     ( positive)
++	{SMART_CONFIG_PRM   , 0x00},
++	{SMART_CONFIG_PRM   , 0x05},
++	{SMART_CONFIG_PRM   , 0x09},
++	{SMART_CONFIG_PRM   , 0x04},
++	{SMART_CONFIG_PRM   , 0x02},
++	{SMART_CONFIG_PRM   , 0x0b},
++	{SMART_CONFIG_PRM   , 0x0a},
++	{SMART_CONFIG_PRM   , 0x09},
++	{SMART_CONFIG_PRM   , 0x05},
++	{SMART_CONFIG_PRM   , 0x08},
++	{SMART_CONFIG_PRM   , 0x10},
++	{SMART_CONFIG_PRM   , 0x05},
++	{SMART_CONFIG_PRM   , 0x06},
++	{SMART_CONFIG_PRM   , 0x11},
++	{SMART_CONFIG_PRM   , 0x09},
++	{SMART_CONFIG_PRM   , 0x01},
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0x00},
++	{SMART_CONFIG_CMD    , 0xe2},  //Gamma setting                      ( negative)
++	{SMART_CONFIG_PRM   , 0x00},
++	{SMART_CONFIG_PRM   , 0x05},
++	{SMART_CONFIG_PRM   , 0x09},
++	{SMART_CONFIG_PRM   , 0x04},
++	{SMART_CONFIG_PRM   , 0x02},
++	{SMART_CONFIG_PRM   , 0x0b},
++	{SMART_CONFIG_PRM   , 0x0a},
++	{SMART_CONFIG_PRM   , 0x09},
++	{SMART_CONFIG_PRM   , 0x05},
++	{SMART_CONFIG_PRM   , 0x08},
++	{SMART_CONFIG_PRM   , 0x10},
++	{SMART_CONFIG_PRM   , 0x05},
++	{SMART_CONFIG_PRM   , 0x06},
++	{SMART_CONFIG_PRM   , 0x11},
++	{SMART_CONFIG_PRM   , 0x09},
++	{SMART_CONFIG_PRM   , 0x01},
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0x00},
++	{SMART_CONFIG_CMD    , 0x00},  //End Gamma setting
++	{SMART_CONFIG_PRM   , 0x00},
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0x80},
++	{SMART_CONFIG_CMD    , 0xff}, //Orise mode  command Disable
++	{SMART_CONFIG_PRM   , 0x00},
++	{SMART_CONFIG_PRM   , 0x00},
++
++	{SMART_CONFIG_CMD    , 0x00},
++	{SMART_CONFIG_PRM   , 0x00},
++
++	{SMART_CONFIG_CMD    , 0xff}, //Command 2 Disable
++	{SMART_CONFIG_PRM   , 0xff},
++	{SMART_CONFIG_PRM   , 0xff},
++	{SMART_CONFIG_PRM   , 0xff},
++
++	//{SMART_CONFIG_CMD  , 0x35}, //TE ON
++	//{SMART_CONFIG_DATA , 0x00},
++
++	{SMART_CONFIG_CMD    , 0x36}, //set X Y refresh direction
++	{SMART_CONFIG_PRM   , 0x00},
++
++	{SMART_CONFIG_CMD    , 0x3A},    //16-bit/pixe 565
++	{SMART_CONFIG_PRM   , 0x05},
++
++	{SMART_CONFIG_CMD    , 0x2A}, //Frame rate control	320
++	{SMART_CONFIG_PRM   , 0x00},
++	{SMART_CONFIG_PRM   , 0x00},
++	{SMART_CONFIG_PRM   , 0x01},
++	{SMART_CONFIG_PRM   , 0x3F},
++
++	{SMART_CONFIG_CMD    , 0x2B}, //Display function control	 480
++	{SMART_CONFIG_PRM   , 0x00},
++	{SMART_CONFIG_PRM   , 0x00},
++	{SMART_CONFIG_PRM   , 0x01},
++	{SMART_CONFIG_PRM   , 0xDF},
++
++	{SMART_CONFIG_CMD    , 0x11},
++	{SMART_CONFIG_UDELAY , 12000},
++	{SMART_CONFIG_CMD    , 0x29}, //display on
++
++	{SMART_CONFIG_CMD    , 0x2c},
++
++};
++
++static struct fb_videomode panel_modes[] = {
++	[0] = {
++		.name = "320x480",
++		.refresh = 60,
++		.xres = 320,
++		.yres = 480,
++		.pixclock = KHZ2PICOS(18432),
++		.left_margin = 0,
++		.right_margin = 0,
++		.upper_margin = 0,
++		.lower_margin = 0,
++		.hsync_len = 0,
++		.vsync_len = 0,
++		.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++		.vmode = FB_VMODE_NONINTERLACED,
++		.flag = 0,
++	},
++};
++
++struct smart_config kd035hvfbd037_cfg = {
++	.te_anti_jit = 1,
++	.te_md = 0,
++	.te_switch = 0,
++	.dc_md = 0,
++	.wr_md = 1,
++	.te_dp = 1,
++	.smart_type = SMART_LCD_TYPE_8080,
++	.pix_fmt = SMART_LCD_FORMAT_565,
++	.dwidth = SMART_LCD_DWIDTH_8_BIT,
++	.cwidth = SMART_LCD_CWIDTH_8_BIT,
++	.bus_width = 8,
++
++	.write_gram_cmd = 0x2c,
++	.data_table = kd035hvfbd037_data_table,
++	.length_data_table = ARRAY_SIZE(kd035hvfbd037_data_table),
++};
++
++struct lcd_panel lcd_panel = {
++	.name = "kd035hvfbd037",
++	.num_modes = ARRAY_SIZE(panel_modes),
++	.modes = panel_modes,
++	.lcd_type = LCD_TYPE_SLCD,
++	.width = 320,
++	.height = 480,
++
++	.smart_config = &kd035hvfbd037_cfg,
++
++	.dither_enable = 0,
++	.dither.dither_red = 0,
++	.dither.dither_green = 0,
++	.dither.dither_blue = 0,
++};
++
++/* SGM3146 supports 16 brightness step */
++#define MAX_BRIGHTNESS_STEP     16
++/* System support 256 brightness step */
++#define CONVERT_FACTOR          (256/MAX_BRIGHTNESS_STEP)
++
++static int panel_update_status(struct backlight_device *bd)
++{
++	struct panel_dev *panel = dev_get_drvdata(&bd->dev);
++	int brightness = bd->props.brightness;
++	unsigned int i;
++	int pulse_num = MAX_BRIGHTNESS_STEP - brightness / CONVERT_FACTOR - 1;
++
++	if (bd->props.fb_blank == FB_BLANK_POWERDOWN) {
++		return 0;
++	}
++
++	if (bd->props.state & BL_CORE_SUSPENDED)
++		brightness = 0;
++
++	if (brightness) {
++		gpio_direction_output(panel->pwm.gpio,0);
++		udelay(5000);
++		gpio_direction_output(panel->pwm.gpio,1);
++		udelay(100);
++
++		for (i = pulse_num; i > 0; i--) {
++			gpio_direction_output(panel->pwm.gpio,0);
++			udelay(1);
++			gpio_direction_output(panel->pwm.gpio,1);
++			udelay(3);
++		}
++	} else
++		gpio_direction_output(panel->pwm.gpio, 0);
++
++	return 0;
++}
++
++static struct backlight_ops panel_backlight_ops = {
++	.options = BL_CORE_SUSPENDRESUME,
++	.update_status = panel_update_status,
++};
++
++static void panel_power_reset(struct board_gpio *rst)
++{
++	gpio_direction_output(rst->gpio, 0);
++	mdelay(20);
++	gpio_direction_output(rst->gpio, 1);
++	mdelay(10);
++}
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++	struct board_gpio *cs = &panel->cs;
++	struct board_gpio *rst = &panel->rst;
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *vddio_en = &panel->vddio_en;
++
++	if(POWER_IS_ON(power) && !POWER_IS_ON(panel->power)) {
++		gpio_direction_output(vdd_en->gpio, 1);
++		if(gpio_is_valid(panel->vddio_en.gpio))
++			gpio_direction_output(vddio_en->gpio, 1);
++		gpio_direction_output(rst->gpio, 1);
++		gpio_direction_output(cs->gpio, 1);
++		mdelay(5);
++		panel_power_reset(rst);
++		gpio_direction_output(cs->gpio, 0);
++	}
++	if(!POWER_IS_ON(power) && POWER_IS_ON(panel->power)) {
++		gpio_direction_output(cs->gpio, 0);
++		gpio_direction_output(rst->gpio, 0);
++		if(gpio_is_valid(panel->vddio_en.gpio))
++			gpio_direction_output(vddio_en->gpio, 0);
++		gpio_direction_output(vdd_en->gpio, 0);
++	}
++
++	panel->power = power;
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->cs.gpio = of_get_named_gpio_flags(np, "ingenic,cs-gpio", 0, &flags);
++	if(gpio_is_valid(panel->cs.gpio)) {
++		panel->cs.active_level = OF_GPIO_ACTIVE_LOW ? 0 : 1;
++		ret = gpio_request_one(panel->cs.gpio, GPIOF_DIR_OUT, "cs");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request cs pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio cs.gpio: %d\n", panel->cs.gpio);
++	}
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = OF_GPIO_ACTIVE_LOW ? 0 : 1;
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = OF_GPIO_ACTIVE_LOW ? 0 : 1;
++		ret = gpio_request_one(panel->vdd_en.gpio, GPIOF_DIR_OUT, "vdd_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	panel->vddio_en.gpio = of_get_named_gpio_flags(np, "ingenic,vddio-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vddio_en.gpio)) {
++		panel->vddio_en.active_level = OF_GPIO_ACTIVE_LOW ? 0 : 1;
++		ret = gpio_request_one(panel->vddio_en.gpio, GPIOF_DIR_OUT, "vddio_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vddio_en pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vddio_en.gpio: %d\n", panel->vddio_en.gpio);
++	}
++
++	panel->pwm.gpio = of_get_named_gpio_flags(np, "ingenic,pwm-gpio", 0, &flags);
++	if(gpio_is_valid(panel->pwm.gpio)) {
++		panel->pwm.active_level = OF_GPIO_ACTIVE_LOW ? 0 : 1;
++		ret = gpio_request_one(panel->pwm.gpio, GPIOF_DIR_OUT, "pwm");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request pwm pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio pwm.gpio: %d\n", panel->pwm.gpio);
++	}
++
++	return 0;
++err_request_rst:
++	gpio_free(panel->cs.gpio);
++	return ret;
++}
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	struct panel_dev *panel;
++	struct backlight_properties props;
++
++	memset(&props, 0, sizeof(props));
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	panel->lcd = lcd_device_register("panel_lcd", &pdev->dev, panel, &panel_lcd_ops);
++	if(IS_ERR_OR_NULL(panel->lcd)) {
++		dev_err(&pdev->dev, "Error register lcd!\n");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++	/* TODO: should this power status sync from uboot */
++	panel->power = FB_BLANK_POWERDOWN;
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++
++	props.type = BACKLIGHT_RAW;
++	props.max_brightness = 255;
++	panel->backlight = backlight_device_register("pwm-backlight.0",
++						&pdev->dev, panel,
++						&panel_backlight_ops,
++						&props);
++	if (IS_ERR_OR_NULL(panel->backlight)) {
++		dev_err(panel->dev, "failed to register 'pwm-backlight.0'.\n");
++		goto err_lcd_register;
++	}
++	panel->backlight->props.brightness = props.max_brightness;
++	backlight_update_status(panel->backlight);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++
++	return 0;
++
++err_lcd_register:
++	lcd_device_unregister(panel->lcd);
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	struct panel_dev *panel = dev_get_drvdata(&pdev->dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++
++#ifdef CONFIG_PM
++static int panel_suspend(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++static int panel_resume(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++#endif
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,kd035hvfbd037", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "kd035hvfbd037",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd035hvfmd057.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd035hvfmd057.c
+new file mode 100644
+index 000000000..be1295615
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd035hvfmd057.c
+@@ -0,0 +1,472 @@
++/*
++ * driver/video/fbdev/ingenic/fb_stage/displays/panel-kd035hvfmd057.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * Author:zhxiao<zhihao.xiao@ingenic.com>
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++
++#include "../ingenicfb.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio cs;
++	struct board_gpio rst;
++	struct board_gpio vdd_en;
++	struct board_gpio vddio_en;
++	struct board_gpio pwm;
++};
++
++
++static struct smart_lcd_data_table kd035hvfmd057_data_table[] = {
++    /* LCD init code */
++    {SMART_CONFIG_UDELAY, 200000},
++    {SMART_CONFIG_CMD, 0xE0}, //P-Gamma
++    {SMART_CONFIG_PRM, 0x00},
++    {SMART_CONFIG_PRM, 0x13},
++    {SMART_CONFIG_PRM, 0x18},
++    {SMART_CONFIG_PRM, 0x04},
++    {SMART_CONFIG_PRM, 0x0F},
++    {SMART_CONFIG_PRM, 0x06},
++    {SMART_CONFIG_PRM, 0x3A},
++    {SMART_CONFIG_PRM, 0x56},
++    {SMART_CONFIG_PRM, 0x4D},
++    {SMART_CONFIG_PRM, 0x03},
++    {SMART_CONFIG_PRM, 0x0A},
++    {SMART_CONFIG_PRM, 0x06},
++    {SMART_CONFIG_PRM, 0x30},
++    {SMART_CONFIG_PRM, 0x3E},
++    {SMART_CONFIG_PRM, 0x0F},
++
++    {SMART_CONFIG_CMD, 0XE1}, //N-Gamma
++    {SMART_CONFIG_PRM, 0x00},
++    {SMART_CONFIG_PRM, 0x13},
++    {SMART_CONFIG_PRM, 0x18},
++    {SMART_CONFIG_PRM, 0x01},
++    {SMART_CONFIG_PRM, 0x11},
++    {SMART_CONFIG_PRM, 0x06},
++    {SMART_CONFIG_PRM, 0x38},
++    {SMART_CONFIG_PRM, 0x34},
++    {SMART_CONFIG_PRM, 0x4D},
++    {SMART_CONFIG_PRM, 0x06},
++    {SMART_CONFIG_PRM, 0x0D},
++    {SMART_CONFIG_PRM, 0x0B},
++    {SMART_CONFIG_PRM, 0x31},
++    {SMART_CONFIG_PRM, 0x37},
++    {SMART_CONFIG_PRM, 0x0F},
++
++    {SMART_CONFIG_CMD, 0XC0},   //Power Control 1
++    {SMART_CONFIG_PRM, 0x18}, //Vreg1out
++    {SMART_CONFIG_PRM, 0x17}, //Verg2out
++
++    {SMART_CONFIG_CMD, 0xC1},   //Power Control 2
++    {SMART_CONFIG_PRM, 0x41}, //VGH,VGL
++
++    {SMART_CONFIG_CMD, 0xC5},   //Power Control 3
++    {SMART_CONFIG_PRM, 0x00},
++    {SMART_CONFIG_PRM, 0x1A}, //Vcom
++    {SMART_CONFIG_PRM, 0x80},
++
++    {SMART_CONFIG_CMD, 0x36},   //Memory Access
++    {SMART_CONFIG_PRM, 0x48},   //48
++
++    {SMART_CONFIG_CMD, 0x3A},   // Interface Pixel Format
++    {SMART_CONFIG_PRM, 0x55}, //16bit
++//    {SMART_CONFIG_PRM, 0x66}, //18bit
++
++    {SMART_CONFIG_CMD, 0XB0},   // Interface Mode Control
++    {SMART_CONFIG_PRM, 0x00},
++
++    {SMART_CONFIG_CMD, 0xB1},   //Frame rate
++    {SMART_CONFIG_PRM, 0xA0}, //60Hz
++
++    {SMART_CONFIG_CMD, 0xB4},   //Display Inversion Control
++    {SMART_CONFIG_PRM, 0x02}, //2-dot
++
++    {SMART_CONFIG_CMD, 0XB6},   //RGB/MCU Interface Control
++    {SMART_CONFIG_PRM, 0x02}, //MCU RGB
++    {SMART_CONFIG_PRM, 0x02}, //Source,Gate scan dieection
++
++    {SMART_CONFIG_CMD, 0XE9},    // Set Image Function
++    {SMART_CONFIG_PRM, 0x00},  //disable 24 bit data input
++
++    {SMART_CONFIG_CMD, 0xF7},    // Adjust Control
++    {SMART_CONFIG_PRM, 0xA9},
++    {SMART_CONFIG_PRM, 0x51},
++    {SMART_CONFIG_PRM, 0x2C},
++    {SMART_CONFIG_PRM, 0x82},  // D7 stream, loose
++
++    {SMART_CONFIG_CMD, 0x21},    //Normal Black
++    {SMART_CONFIG_CMD, 0x11},    //Sleep out
++    {SMART_CONFIG_UDELAY, 200000},
++    {SMART_CONFIG_CMD, 0x29},
++
++    {SMART_CONFIG_CMD, 0x2C},
++};
++
++
++static struct fb_videomode panel_modes[] = {
++	[0] = {
++		.name = "320x480",
++		.refresh = 60,
++		.xres = 320,
++		.yres = 480,
++		.pixclock = KHZ2PICOS(18432),
++		.left_margin = 0,
++		.right_margin = 0,
++		.upper_margin = 0,
++		.lower_margin = 0,
++		.hsync_len = 0,
++		.vsync_len = 0,
++		.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++		.vmode = FB_VMODE_NONINTERLACED,
++		.flag = 0,
++	},
++};
++
++struct smart_config kd035hvfmd057_cfg = {
++	.te_anti_jit = 1,
++	.te_md = 0,
++	.te_switch = 0,
++	.dc_md = 0,
++	.wr_md = 1,
++	.te_dp = 1,
++	.smart_type = SMART_LCD_TYPE_8080,
++	.pix_fmt = SMART_LCD_FORMAT_565,
++	.dwidth = SMART_LCD_DWIDTH_16_BIT,
++	.cwidth = SMART_LCD_CWIDTH_16_BIT,
++	.bus_width = 16,
++
++	.write_gram_cmd = 0x2c,
++	.data_table = kd035hvfmd057_data_table,
++	.length_data_table = ARRAY_SIZE(kd035hvfmd057_data_table),
++};
++
++struct lcd_panel lcd_panel = {
++	.name = "kd035hvfmd057",
++	.num_modes = ARRAY_SIZE(panel_modes),
++	.modes = panel_modes,
++	.lcd_type = LCD_TYPE_SLCD,
++	.width = 320,
++	.height = 480,
++
++	.smart_config = &kd035hvfmd057_cfg,
++
++	.dither_enable = 0,
++	.dither.dither_red = 2,
++	.dither.dither_green = 1,
++	.dither.dither_blue = 2,
++};
++
++/* SGM3146 supports 16 brightness step */
++#define MAX_BRIGHTNESS_STEP     16
++/* System support 256 brightness step */
++#define CONVERT_FACTOR          (256/MAX_BRIGHTNESS_STEP)
++
++static int panel_update_status(struct backlight_device *bd)
++{
++	struct panel_dev *panel = dev_get_drvdata(&bd->dev);
++	int brightness = bd->props.brightness;
++	unsigned int i;
++	int pulse_num = MAX_BRIGHTNESS_STEP - brightness / CONVERT_FACTOR - 1;
++
++	if (bd->props.fb_blank == FB_BLANK_POWERDOWN) {
++		return 0;
++	}
++
++	if (bd->props.state & BL_CORE_SUSPENDED)
++		brightness = 0;
++
++	if (brightness) {
++		gpio_direction_output(panel->pwm.gpio,0);
++		udelay(5000);
++		gpio_direction_output(panel->pwm.gpio,1);
++		udelay(100);
++
++		for (i = pulse_num; i > 0; i--) {
++			gpio_direction_output(panel->pwm.gpio,0);
++			udelay(1);
++			gpio_direction_output(panel->pwm.gpio,1);
++			udelay(3);
++		}
++	} else
++		gpio_direction_output(panel->pwm.gpio, 0);
++
++	return 0;
++}
++
++static struct backlight_ops panel_backlight_ops = {
++	.options = BL_CORE_SUSPENDRESUME,
++	.update_status = panel_update_status,
++};
++
++static void panel_power_reset(struct board_gpio *rst)
++{
++	gpio_direction_output(rst->gpio, 0);
++	mdelay(20);
++	gpio_direction_output(rst->gpio, 1);
++	mdelay(10);
++}
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++	struct board_gpio *cs = &panel->cs;
++	struct board_gpio *rst = &panel->rst;
++	struct board_gpio *vddio_en = &panel->vddio_en;
++	struct board_gpio *vdd_en = &panel->vdd_en;
++
++	if(POWER_IS_ON(power) && !POWER_IS_ON(panel->power)) {
++		gpio_direction_output(vdd_en->gpio, 1);
++		gpio_direction_output(vddio_en->gpio, 1);
++		gpio_direction_output(rst->gpio, 1);
++		gpio_direction_output(cs->gpio, 1);
++		mdelay(5);
++		panel_power_reset(rst);
++		gpio_direction_output(cs->gpio, 0);
++	}
++	if(!POWER_IS_ON(power) && POWER_IS_ON(panel->power)) {
++		gpio_direction_output(cs->gpio, 0);
++		gpio_direction_output(rst->gpio, 0);
++		gpio_direction_output(vddio_en->gpio, 0);
++		gpio_direction_output(vdd_en->gpio, 0);
++	}
++
++	panel->power = power;
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->cs.gpio = of_get_named_gpio_flags(np, "ingenic,cs-gpio", 0, &flags);
++	if(gpio_is_valid(panel->cs.gpio)) {
++		panel->cs.active_level = OF_GPIO_ACTIVE_LOW ? 0 : 1;
++		ret = gpio_request_one(panel->cs.gpio, GPIOF_DIR_OUT, "cs");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request cs pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio cs.gpio: %d\n", panel->cs.gpio);
++	}
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = OF_GPIO_ACTIVE_LOW ? 0 : 1;
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = OF_GPIO_ACTIVE_LOW ? 0 : 1;
++		ret = gpio_request_one(panel->vdd_en.gpio, GPIOF_DIR_OUT, "vdd_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	panel->vddio_en.gpio = of_get_named_gpio_flags(np, "ingenic,vddio-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vddio_en.gpio)) {
++		panel->vddio_en.active_level = OF_GPIO_ACTIVE_LOW ? 0 : 1;
++		ret = gpio_request_one(panel->vddio_en.gpio, GPIOF_DIR_OUT, "vddio_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vddio_en pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vddio_en.gpio: %d\n", panel->vddio_en.gpio);
++	}
++
++	panel->pwm.gpio = of_get_named_gpio_flags(np, "ingenic,pwm-gpio", 0, &flags);
++	if(gpio_is_valid(panel->pwm.gpio)) {
++		panel->pwm.active_level = OF_GPIO_ACTIVE_LOW ? 0 : 1;
++		ret = gpio_request_one(panel->pwm.gpio, GPIOF_DIR_OUT, "pwm");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request pwm pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio pwm.gpio: %d\n", panel->pwm.gpio);
++	}
++
++	return 0;
++err_request_rst:
++	gpio_free(panel->cs.gpio);
++	return ret;
++}
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	struct panel_dev *panel;
++	struct backlight_properties props;
++
++	memset(&props, 0, sizeof(props));
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	panel->lcd = lcd_device_register("panel_lcd", &pdev->dev, panel, &panel_lcd_ops);
++	if(IS_ERR_OR_NULL(panel->lcd)) {
++		dev_err(&pdev->dev, "Error register lcd!\n");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++	/* TODO: should this power status sync from uboot */
++	panel->power = FB_BLANK_POWERDOWN;
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++
++	props.type = BACKLIGHT_RAW;
++	props.max_brightness = 255;
++	panel->backlight = backlight_device_register("pwm-backlight.0",
++						&pdev->dev, panel,
++						&panel_backlight_ops,
++						&props);
++	if (IS_ERR_OR_NULL(panel->backlight)) {
++		dev_err(panel->dev, "failed to register 'pwm-backlight.0'.\n");
++		goto err_lcd_register;
++	}
++	panel->backlight->props.brightness = props.max_brightness;
++	backlight_update_status(panel->backlight);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++
++	return 0;
++
++err_lcd_register:
++	lcd_device_unregister(panel->lcd);
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	struct panel_dev *panel = dev_get_drvdata(&pdev->dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++
++#ifdef CONFIG_PM
++static int panel_suspend(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++static int panel_resume(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++#endif
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,kd035hvfmd057", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "kd035hvfmd057",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd050hdfia019.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd050hdfia019.c
+new file mode 100644
+index 000000000..63e4e78c2
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd050hdfia019.c
+@@ -0,0 +1,474 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-kd050hdfia019.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++
++#include "../ingenicfb.h"
++#include "../jz_dsim.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio pwm;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++};
++
++struct panel_dev *panel;
++
++ struct dsi_cmd_packet kd050hdfia019_cmd_list[] = {
++	/* for KD050FWFIA019-C019A */
++	{0x39, 0x06, 0x00, {0xFF, 0xFF, 0x98, 0x06, 0x04, 0x01}},
++	{0x15, 0x08, 0x10},
++	{0x15, 0x20, 0x00},
++	{0x15, 0x21, 0x01},
++	{0x15, 0x30, 0x01},
++	{0x15, 0x31, 0x00},
++	{0x15, 0x40, 0x16},
++	{0x15, 0x41, 0x33},
++	{0x15, 0x42, 0x03},
++	{0x15, 0x43, 0x09},
++	{0x15, 0x44, 0x06},
++	{0x15, 0x50, 0x88},
++	{0x15, 0x51, 0x88},
++	{0x15, 0x52, 0x00},
++	{0x15, 0x53, 0x49},
++	{0x15, 0x55, 0x49},
++	{0x15, 0x60, 0x07},
++	{0x15, 0x61, 0x00},
++	{0x15, 0x62, 0x07},
++	{0x15, 0x63, 0x00},
++	{0x15, 0xA0, 0x00},
++	{0x15, 0xA1, 0x09},
++	{0x15, 0xA2, 0x11},
++	{0x15, 0xA3, 0x0B},
++	{0x15, 0xA4, 0x05},
++	{0x15, 0xA5, 0x08},
++	{0x15, 0xA6, 0x06},
++	{0x15, 0xA7, 0x04},
++	{0x15, 0xA8, 0x09},
++	{0x15, 0xA9, 0x0C},
++	{0x15, 0xAA, 0x15},
++	{0x15, 0xAB, 0x08},
++	{0x15, 0xAC, 0x0F},
++	{0x15, 0xAD, 0x12},
++	{0x15, 0xAE, 0x09},
++	{0x15, 0xAF, 0x00},
++	{0x15, 0xC0, 0x00},
++	{0x15, 0xC1, 0x09},
++	{0x15, 0xC2, 0x10},
++	{0x15, 0xC3, 0x0C},
++	{0x15, 0xC4, 0x05},
++	{0x15, 0xC5, 0x08},
++	{0x15, 0xC6, 0x06},
++	{0x15, 0xC7, 0x04},
++	{0x15, 0xC8, 0x08},
++	{0x15, 0xC9, 0x0C},
++	{0x15, 0xCA, 0x14},
++	{0x15, 0xCB, 0x08},
++	{0x15, 0xCC, 0x0F},
++	{0x15, 0xCD, 0x11},
++	{0x15, 0xCE, 0x09},
++	{0x15, 0xCF, 0x00},
++	{0x39, 0x06, 0x00,{0xFF, 0xFF, 0x98, 0x06, 0x04, 0x06}},
++	{0x15, 0x00, 0x20},
++	{0x15, 0x01, 0x0A},
++	{0x15, 0x02, 0x00},
++	{0x15, 0x03, 0x00},
++	{0x15, 0x04, 0x01},
++	{0x15, 0x05, 0x01},
++	{0x15, 0x06, 0x98},
++	{0x15, 0x07, 0x06},
++	{0x15, 0x08, 0x01},
++	{0x15, 0x09, 0x80},
++	{0x15, 0x0A, 0x00},
++	{0x15, 0x0B, 0x00},
++	{0x15, 0x0C, 0x01},
++	{0x15, 0x0D, 0x01},
++	{0x15, 0x0E, 0x05},
++	{0x15, 0x0F, 0x00},
++	{0x15, 0x10, 0xF0},
++	{0x15, 0x11, 0xF4},
++	{0x15, 0x12, 0x01},
++	{0x15, 0x13, 0x00},
++	{0x15, 0x14, 0x00},
++	{0x15, 0x15, 0xC0},
++	{0x15, 0x16, 0x08},
++	{0x15, 0x17, 0x00},
++	{0x15, 0x18, 0x00},
++	{0x15, 0x19, 0x00},
++	{0x15, 0x1A, 0x00},
++	{0x15, 0x1B, 0x00},
++	{0x15, 0x1C, 0x00},
++	{0x15, 0x1D, 0x00},
++	{0x15, 0x20, 0x01},
++	{0x15, 0x21, 0x23},
++	{0x15, 0x22, 0x45},
++	{0x15, 0x23, 0x67},
++	{0x15, 0x24, 0x01},
++	{0x15, 0x25, 0x23},
++	{0x15, 0x26, 0x45},
++	{0x15, 0x27, 0x67},
++	{0x15, 0x30, 0x11},
++	{0x15, 0x31, 0x11},
++	{0x15, 0x32, 0x00},
++	{0x15, 0x33, 0xEE},
++	{0x15, 0x34, 0xFF},
++	{0x15, 0x35, 0xBB},
++	{0x15, 0x36, 0xAA},
++	{0x15, 0x37, 0xDD},
++	{0x15, 0x38, 0xCC},
++	{0x15, 0x39, 0x66},
++	{0x15, 0x3A, 0x77},
++	{0x15, 0x3B, 0x22},
++	{0x15, 0x3C, 0x22},
++	{0x15, 0x3D, 0x22},
++	{0x15, 0x3E, 0x22},
++	{0x15, 0x3F, 0x22},
++	{0x15, 0x40, 0x22},
++	{0x39, 0x06, 0x00,{0xFF, 0xFF, 0x98, 0x06, 0x04, 0x07}},
++	{0x15, 0x17, 0x22},
++	{0x15, 0x02, 0x77},
++	{0x15, 0x26, 0xB2},
++	{0x39, 0x06, 0x00,{0xFF, 0xFF, 0x98, 0x06, 0x04, 0x00}},
++	{0x15, 0x3A, 0x70},
++	{0x05, 0x11, 0x00},
++//	{0x05, 0x29, 0x00}, display on
++ };
++
++struct kd050hdfia019 {
++	struct device *dev;
++	unsigned int power;
++	unsigned int id;
++
++	struct lcd_device *ld;
++	struct backlight_device *bd;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++	struct kd050hdfia019_platform_data *ddi_pd;
++
++};
++
++#define lcd_to_master(a)	(a->dsim_dev->master)
++#define lcd_to_master_ops(a)	((lcd_to_master(a))->master_ops)
++
++static void panel_dev_sleep_out(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x11, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_display_on(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x29, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_panel_condition_setting(struct panel_dev *lcd)
++{
++	int  i;
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_device *dsi = lcd_to_master(lcd);
++	for(i = 0; i < ARRAY_SIZE(kd050hdfia019_cmd_list); i++) {
++		ops->cmd_write(dsi,  kd050hdfia019_cmd_list[i]);
++	}
++
++}
++
++static int panel_dev_ioctl(struct mipi_dsim_lcd_device *dsim_dev, int cmd)
++{
++	return 0;
++}
++static void panel_dev_set_sequence(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct panel_dev *lcd = dev_get_drvdata(&dsim_dev->dev);
++
++	/* panel reset ... */
++
++	panel_dev_panel_condition_setting(lcd);
++
++	panel_dev_sleep_out(lcd);
++
++	msleep(120);
++	panel_dev_display_on(lcd);
++
++	lcd->power = FB_BLANK_UNBLANK;
++}
++static int panel_dev_probe(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	panel->dsim_dev = dsim_dev;
++	dev_set_drvdata(&dsim_dev->dev, panel);
++	return 0;
++}
++static struct mipi_dsim_lcd_driver panel_dev_dsim_ddi_driver = {
++	.name = "kd050hdfia019-lcd",
++	.id = 0,
++
++//	.power_on = panel_dev_power_on,
++	.set_sequence = panel_dev_set_sequence,
++	.ioctl        = panel_dev_ioctl,
++	.probe = panel_dev_probe,
++};
++
++struct mipi_dsim_lcd_device panel_dev_device={
++	.name		= "kd050hdfia019-lcd",
++	.id = 0,
++	.platform_data = NULL,
++};
++
++static void panel_enable(struct lcd_panel *panel)
++{
++}
++
++static void panel_disable(struct lcd_panel *panel)
++{
++}
++
++static struct lcd_panel_ops panel_ops = {
++	.enable  = (void*)panel_enable,
++	.disable = (void*)panel_disable,
++};
++
++static struct fb_videomode panel_modes = {
++	.name                   = "kd050hdfia019-lcd",
++	.refresh                = 0,
++	.xres                   = 480,
++	.yres                   = 854,
++	.pixclock               = KHZ2PICOS(30000),
++	.left_margin            = 40,
++	.right_margin           = 50,
++	.upper_margin           = 16,
++	.lower_margin           = 4,
++
++	.hsync_len              = 8,
++	.vsync_len              = 10,
++	.sync                   = FB_SYNC_HOR_HIGH_ACT & FB_SYNC_VERT_HIGH_ACT,
++	.vmode                  = FB_VMODE_NONINTERLACED,
++	.flag                   = 0,
++};
++
++struct jzdsi_data jzdsi_pdata = {
++	.modes = &panel_modes,
++	.video_config.no_of_lanes = 2,
++	.video_config.virtual_channel = 0,
++	.video_config.color_coding = COLOR_CODE_24BIT,
++	.video_config.video_mode = VIDEO_BURST_WITH_SYNC_PULSES,
++	.video_config.receive_ack_packets = 0,
++	.video_config.is_18_loosely = 0,
++	.video_config.data_en_polarity = 1,
++	.video_config.byte_clock = 0, // driver will auto calculate byte_clock.
++	.video_config.byte_clock_coef = MIPI_PHY_BYTE_CLK_COEF_MUL3_DIV2, //for auto calculate byte clock
++
++	.dsi_config.max_lanes = 4,
++	.dsi_config.max_hs_to_lp_cycles = 100,
++	.dsi_config.max_lp_to_hs_cycles = 40,
++	.dsi_config.max_bta_cycles = 4095,
++	.dsi_config.color_mode_polarity = 1,
++	.dsi_config.shut_down_polarity = 1,
++	.dsi_config.max_bps = 650,
++	.bpp_info = 24,
++};
++
++static struct tft_config kd050hdfia019_cfg = {
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++struct lcd_panel lcd_panel = {
++	.name = "kd050hdfia019",
++	.num_modes = 1,
++	.modes = &panel_modes,
++	.bpp = 24,
++	.width = 62,
++	.height = 110,
++
++	.lcd_type = LCD_TYPE_MIPI_TFT,
++
++	.tft_config = &kd050hdfia019_cfg,
++	.dsi_pdata = &jzdsi_pdata,
++
++	.dither_enable = 0,
++	.dither.dither_red = 0,
++	.dither.dither_green = 0,
++	.dither.dither_blue = 0,
++
++	.ops = &panel_ops,
++};
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	if(POWER_IS_ON(power) && !POWER_IS_ON(panel->power)) {
++	}
++	if(!POWER_IS_ON(power) && POWER_IS_ON(panel->power)) {
++	}
++
++	panel->power = power;
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++* @ pannel_kd050hdfia019_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	return 0;
++}
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	panel->lcd = lcd_device_register("panel_lcd", &pdev->dev, panel, &panel_lcd_ops);
++	if(IS_ERR_OR_NULL(panel->lcd)) {
++		dev_err(&pdev->dev, "Error register lcd!\n");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++	/* TODO: should this power status sync from uboot */
++	panel->power = FB_BLANK_POWERDOWN;
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++
++	mipi_dsi_register_lcd_device(&panel_dev_device);
++	mipi_dsi_register_lcd_driver(&panel_dev_dsim_ddi_driver);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++
++	return 0;
++
++err_lcd_register:
++	lcd_device_unregister(panel->lcd);
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	struct panel_dev *panel = dev_get_drvdata(&pdev->dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int panel_suspend(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++static int panel_resume(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++#endif
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,kd050hdfia019", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "kd050hdfia019",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd050hdfia020.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd050hdfia020.c
+new file mode 100644
+index 000000000..90affe082
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd050hdfia020.c
+@@ -0,0 +1,724 @@
++/*
++ * driver/video/fbdev/ingenic/fb_stage/displays/panel-kd050hdfia020.c
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ * This program is free software, you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++#include <linux/fb.h>
++#include <linux/backlight.h>
++
++#include "../ingenicfb.h"
++#include "../jz_dsim.h"
++
++
++static char panel_kd050hdfia020_debug = 0;
++#define PANEL_DEBUG_MSG(msg...)			\
++	do {					\
++		if (panel_kd050hdfia020_debug)		\
++			printk(">>>>>>>>>>>>>>>>PANEL KD050HDFIA020: " msg);		\
++	} while(0)
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio lcd_te;
++	struct board_gpio lcd_pwm;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++};
++
++struct panel_dev *panel;
++
++#define lcd_to_master(a)	(a->dsim_dev->master)
++#define lcd_to_master_ops(a)	((lcd_to_master(a))->master_ops)
++
++#define PANEL_KD050HDFIA020_ID	(0x98815c)
++
++struct kd050hdfia020 {
++	struct device *dev;
++	unsigned int power;
++	unsigned int id;
++
++	struct lcd_device *ld;
++	struct backlight_device *bd;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++
++};
++
++
++static struct dsi_cmd_packet fitipower_kd050hdfia020_720_1280_cmd_list[] =
++{
++	{0x39, 0x04, 0x00, {0xFF, 0x98, 0x81, 0x03}},
++	{0x39, 0x02, 0x00, {0x01, 0x00}},
++	{0x39, 0x02, 0x00, {0x02, 0x00}},
++	{0x39, 0x02, 0x00, {0x03, 0x73}},
++	{0x39, 0x02, 0x00, {0x04, 0x00}},
++	{0x39, 0x02, 0x00, {0x05, 0x00}},
++	{0x39, 0x02, 0x00, {0x06, 0x0A}},
++	{0x39, 0x02, 0x00, {0x07, 0x00}},
++	{0x39, 0x02, 0x00, {0x08, 0x00}},
++	{0x39, 0x02, 0x00, {0x09, 0x01}},
++	{0x39, 0x02, 0x00, {0x0A, 0x00}},
++	{0x39, 0x02, 0x00, {0x0B, 0x00}},
++	{0x39, 0x02, 0x00, {0x0C, 0x01}},
++	{0x39, 0x02, 0x00, {0x0D, 0x00}},
++	{0x39, 0x02, 0x00, {0x0E, 0x00}},
++	{0x39, 0x02, 0x00, {0x0F, 0x1D}},
++	{0x39, 0x02, 0x00, {0x10, 0x1D}},
++	{0x39, 0x02, 0x00, {0x11, 0x00}},
++	{0x39, 0x02, 0x00, {0x12, 0x00}},
++	{0x39, 0x02, 0x00, {0x13, 0x00}},
++	{0x39, 0x02, 0x00, {0x14, 0x00}},
++	{0x39, 0x02, 0x00, {0x15, 0x00}},
++	{0x39, 0x02, 0x00, {0x16, 0x00}},
++	{0x39, 0x02, 0x00, {0x17, 0x00}},
++	{0x39, 0x02, 0x00, {0x18, 0x00}},
++	{0x39, 0x02, 0x00, {0x19, 0x00}},
++	{0x39, 0x02, 0x00, {0x1A, 0x00}},
++	{0x39, 0x02, 0x00, {0x1B, 0x00}},
++	{0x39, 0x02, 0x00, {0x1C, 0x00}},
++	{0x39, 0x02, 0x00, {0x1D, 0x00}},
++	{0x39, 0x02, 0x00, {0x1E, 0x40}},
++	{0x39, 0x02, 0x00, {0x1F, 0x80}},
++	{0x39, 0x02, 0x00, {0x20, 0x06}},
++	{0x39, 0x02, 0x00, {0x21, 0x02}},
++	{0x39, 0x02, 0x00, {0x22, 0x00}},
++	{0x39, 0x02, 0x00, {0x23, 0x00}},
++	{0x39, 0x02, 0x00, {0x24, 0x00}},
++	{0x39, 0x02, 0x00, {0x25, 0x00}},
++	{0x39, 0x02, 0x00, {0x26, 0x00}},
++	{0x39, 0x02, 0x00, {0x27, 0x00}},
++	{0x39, 0x02, 0x00, {0x28, 0x33}},
++	{0x39, 0x02, 0x00, {0x29, 0x03}},
++	{0x39, 0x02, 0x00, {0x2A, 0x00}},
++	{0x39, 0x02, 0x00, {0x2B, 0x00}},
++	{0x39, 0x02, 0x00, {0x2C, 0x00}},
++	{0x39, 0x02, 0x00, {0x2D, 0x00}},
++	{0x39, 0x02, 0x00, {0x2E, 0x00}},
++	{0x39, 0x02, 0x00, {0x2F, 0x00}},
++	{0x39, 0x02, 0x00, {0x30, 0x00}},
++	{0x39, 0x02, 0x00, {0x31, 0x00}},
++	{0x39, 0x02, 0x00, {0x32, 0x00}},
++	{0x39, 0x02, 0x00, {0x33, 0x00}},
++	{0x39, 0x02, 0x00, {0x34, 0x04}},
++	{0x39, 0x02, 0x00, {0x35, 0x00}},
++	{0x39, 0x02, 0x00, {0x36, 0x00}},
++	{0x39, 0x02, 0x00, {0x37, 0x00}},
++	{0x39, 0x02, 0x00, {0x38, 0x3C}},
++	{0x39, 0x02, 0x00, {0x39, 0x00}},
++	{0x39, 0x02, 0x00, {0x3A, 0x40}},
++	{0x39, 0x02, 0x00, {0x3B, 0x40}},
++	{0x39, 0x02, 0x00, {0x3C, 0x00}},
++	{0x39, 0x02, 0x00, {0x3D, 0x00}},
++	{0x39, 0x02, 0x00, {0x3E, 0x00}},
++	{0x39, 0x02, 0x00, {0x3F, 0x00}},
++	{0x39, 0x02, 0x00, {0x40, 0x00}},
++	{0x39, 0x02, 0x00, {0x41, 0x00}},
++	{0x39, 0x02, 0x00, {0x42, 0x00}},
++	{0x39, 0x02, 0x00, {0x43, 0x00}},
++	{0x39, 0x02, 0x00, {0x44, 0x00}},
++
++	{0x39, 0x02, 0x00, {0x50, 0x01}},
++	{0x39, 0x02, 0x00, {0x51, 0x23}},
++	{0x39, 0x02, 0x00, {0x52, 0x45}},
++	{0x39, 0x02, 0x00, {0x53, 0x67}},
++	{0x39, 0x02, 0x00, {0x54, 0x89}},
++	{0x39, 0x02, 0x00, {0x55, 0xAB}},
++	{0x39, 0x02, 0x00, {0x56, 0x01}},
++	{0x39, 0x02, 0x00, {0x57, 0x23}},
++	{0x39, 0x02, 0x00, {0x58, 0x45}},
++	{0x39, 0x02, 0x00, {0x59, 0x67}},
++	{0x39, 0x02, 0x00, {0x5A, 0x89}},
++	{0x39, 0x02, 0x00, {0x5B, 0xAB}},
++	{0x39, 0x02, 0x00, {0x5C, 0xCD}},
++	{0x39, 0x02, 0x00, {0x5D, 0xEF}},
++
++	{0x39, 0x02, 0x00, {0x5E, 0x11}},
++	{0x39, 0x02, 0x00, {0x5F, 0x01}},
++	{0x39, 0x02, 0x00, {0x60, 0x00}},
++	{0x39, 0x02, 0x00, {0x61, 0x15}},
++	{0x39, 0x02, 0x00, {0x62, 0x14}},
++	{0x39, 0x02, 0x00, {0x63, 0x0E}},
++	{0x39, 0x02, 0x00, {0x64, 0x0F}},
++	{0x39, 0x02, 0x00, {0x65, 0x0C}},
++	{0x39, 0x02, 0x00, {0x66, 0x0D}},
++	{0x39, 0x02, 0x00, {0x67, 0x06}},
++	{0x39, 0x02, 0x00, {0x68, 0x02}},
++	{0x39, 0x02, 0x00, {0x69, 0x07}},
++	{0x39, 0x02, 0x00, {0x6A, 0x02}},
++	{0x39, 0x02, 0x00, {0x6B, 0x02}},
++	{0x39, 0x02, 0x00, {0x6C, 0x02}},
++	{0x39, 0x02, 0x00, {0x6D, 0x02}},
++	{0x39, 0x02, 0x00, {0x6E, 0x02}},
++	{0x39, 0x02, 0x00, {0x6F, 0x02}},
++	{0x39, 0x02, 0x00, {0x70, 0x02}},
++	{0x39, 0x02, 0x00, {0x71, 0x02}},
++	{0x39, 0x02, 0x00, {0x72, 0x02}},
++	{0x39, 0x02, 0x00, {0x73, 0x02}},
++	{0x39, 0x02, 0x00, {0x74, 0x02}},
++	{0x39, 0x02, 0x00, {0x75, 0x01}},
++	{0x39, 0x02, 0x00, {0x76, 0x00}},
++	{0x39, 0x02, 0x00, {0x77, 0x14}},
++	{0x39, 0x02, 0x00, {0x78, 0x15}},
++	{0x39, 0x02, 0x00, {0x79, 0x0E}},
++	{0x39, 0x02, 0x00, {0x7A, 0x0F}},
++	{0x39, 0x02, 0x00, {0x7B, 0x0C}},
++	{0x39, 0x02, 0x00, {0x7C, 0x0D}},
++	{0x39, 0x02, 0x00, {0x7D, 0x06}},
++	{0x39, 0x02, 0x00, {0x7E, 0x02}},
++	{0x39, 0x02, 0x00, {0x7F, 0x07}},
++	{0x39, 0x02, 0x00, {0x80, 0x02}},
++	{0x39, 0x02, 0x00, {0x81, 0x02}},
++	{0x39, 0x02, 0x00, {0x82, 0x02}},
++	{0x39, 0x02, 0x00, {0x83, 0x02}},
++	{0x39, 0x02, 0x00, {0x84, 0x02}},
++	{0x39, 0x02, 0x00, {0x85, 0x02}},
++	{0x39, 0x02, 0x00, {0x86, 0x02}},
++	{0x39, 0x02, 0x00, {0x87, 0x02}},
++	{0x39, 0x02, 0x00, {0x88, 0x02}},
++	{0x39, 0x02, 0x00, {0x89, 0x02}},
++	{0x39, 0x02, 0x00, {0x8A, 0x02}},
++	{0x39, 0x04, 0x00, {0xFF, 0x98, 0x81, 0x04}},
++
++	{0x39, 0x02, 0x00, {0x00, 0x80}}, //set 2 line mode
++
++	{0x39, 0x02, 0x00, {0x6C, 0x15}},
++	{0x39, 0x02, 0x00, {0x6E, 0x2A}},
++	{0x39, 0x02, 0x00, {0x6F, 0x33}},
++	{0x39, 0x02, 0x00, {0x8D, 0x14}},
++	{0x39, 0x02, 0x00, {0x87, 0xBA}},
++	{0x39, 0x02, 0x00, {0x26, 0x76}},
++	{0x39, 0x02, 0x00, {0xB2, 0xD1}},
++	{0x39, 0x02, 0x00, {0xB5, 0x06}},
++	{0x39, 0x02, 0x00, {0x3A, 0x24}},
++	{0x39, 0x02, 0x00, {0x35, 0x1F}},
++	{0x39, 0x02, 0x00, {0x32, 0x05}},
++	{0x39, 0x02, 0x00, {0x33, 0x00}},
++	{0x39, 0x02, 0x00, {0x7A, 0x0F}},
++	{0x39, 0x04, 0x00, {0xFF, 0x98, 0x81, 0x01}},
++	{0x39, 0x02, 0x00, {0x22, 0x0A}},
++	{0x39, 0x02, 0x00, {0x31, 0x00}},
++	{0x39, 0x02, 0x00, {0x53, 0x9c}},
++	{0x39, 0x02, 0x00, {0x55, 0x9c}},
++	{0x39, 0x02, 0x00, {0xB7, 0x03}},/*software set lansel pin */
++
++	{0x39, 0x02, 0x00, {0x50, 0xA0}},
++	{0x39, 0x02, 0x00, {0x51, 0xA0}},
++
++	{0x39, 0x02, 0x00, {0x60, 0x22}},
++	{0x39, 0x02, 0x00, {0x61, 0x00}},
++	{0x39, 0x02, 0x00, {0x62, 0x19}},
++	{0x39, 0x02, 0x00, {0x63, 0x00}},
++	{0x39, 0x02, 0x00, {0xA0, 0x08}},
++	{0x39, 0x02, 0x00, {0xA1, 0x19}},
++	{0x39, 0x02, 0x00, {0xA2, 0x20}},
++	{0x39, 0x02, 0x00, {0xA3, 0x12}},
++	{0x39, 0x02, 0x00, {0xA4, 0x13}},
++	{0x39, 0x02, 0x00, {0xA5, 0x24}},
++	{0x39, 0x02, 0x00, {0xA6, 0x19}},
++	{0x39, 0x02, 0x00, {0xA7, 0x19}},
++	{0x39, 0x02, 0x00, {0xA8, 0x6b}},
++	{0x39, 0x02, 0x00, {0xA9, 0x1a}},
++	{0x39, 0x02, 0x00, {0xAA, 0x27}},
++	{0x39, 0x02, 0x00, {0xAB, 0x62}},
++	{0x39, 0x02, 0x00, {0xAC, 0x18}},
++	{0x39, 0x02, 0x00, {0xAD, 0x15}},
++	{0x39, 0x02, 0x00, {0xAE, 0x4c}},
++	{0x39, 0x02, 0x00, {0xAF, 0x22}},
++	{0x39, 0x02, 0x00, {0xB0, 0x25}},
++	{0x39, 0x02, 0x00, {0xB1, 0x5b}},
++	{0x39, 0x02, 0x00, {0xB2, 0x6f}},
++	{0x39, 0x02, 0x00, {0xB3, 0x39}},
++
++	{0x39, 0x02, 0x00, {0xC0, 0x08}},
++	{0x39, 0x02, 0x00, {0xC1, 0x0d}},
++	{0x39, 0x02, 0x00, {0xC2, 0x19}},
++	{0x39, 0x02, 0x00, {0xC3, 0x0C}},
++	{0x39, 0x02, 0x00, {0xC4, 0x0c}},
++	{0x39, 0x02, 0x00, {0xC5, 0x1F}},
++	{0x39, 0x02, 0x00, {0xC6, 0x13}},
++	{0x39, 0x02, 0x00, {0xC7, 0x1a}},
++	{0x39, 0x02, 0x00, {0xC8, 0x5d}},
++	{0x39, 0x02, 0x00, {0xC9, 0x1b}},
++	{0x39, 0x02, 0x00, {0xCA, 0x26}},
++	{0x39, 0x02, 0x00, {0xCB, 0x5b}},
++	{0x39, 0x02, 0x00, {0xCC, 0x19}},
++	{0x39, 0x02, 0x00, {0xCD, 0x18}},
++	{0x39, 0x02, 0x00, {0xCE, 0x4C}},
++	{0x39, 0x02, 0x00, {0xCF, 0x22}},
++	{0x39, 0x02, 0x00, {0xD0, 0x2d}},
++	{0x39, 0x02, 0x00, {0xD1, 0x5D}},
++	{0x39, 0x02, 0x00, {0xD2, 0x6b}},
++	{0x39, 0x02, 0x00, {0xD3, 0x39}},
++
++	{0x39, 0x04, 0x00, {0xFF, 0x98, 0x81, 0x00}},
++};
++
++
++static void panel_dev_sleep_in(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x10, 0x00};
++	PANEL_DEBUG_MSG("enter %s %d \n",__func__, __LINE__);
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_sleep_out(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x11, 0x00};
++	PANEL_DEBUG_MSG("enter %s %d \n",__func__, __LINE__);
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_display_on(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x29, 0x00};
++	PANEL_DEBUG_MSG("enter %s %d \n",__func__, __LINE__);
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_display_off(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x28, 0x00};
++	PANEL_DEBUG_MSG("enter %s %d \n",__func__, __LINE__);
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_power_on(struct mipi_dsim_lcd_device *dsim_dev, int power)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++	struct board_gpio *lcd_te = &panel->lcd_te;
++	struct board_gpio *pwm = &panel->lcd_pwm;
++	PANEL_DEBUG_MSG("enter %s %d \n",__func__, __LINE__);
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	if(gpio_is_valid(pwm->gpio))
++		gpio_direction_output(pwm->gpio, pwm->active_level);
++
++	if (gpio_is_valid(lcd_te->gpio)) {
++		gpio_direction_input(lcd_te->gpio);
++	}
++	/* msleep(50); */
++	gpio_direction_output(rst->gpio, 0);
++	mdelay(3);
++	gpio_direction_output(rst->gpio, 1);
++	mdelay(3);
++
++	panel->power = power;
++}
++
++static int panel_dev_read_id(struct mipi_dsim_lcd_device *dsim_dev, unsigned char *buf, int count)
++{
++	struct dsi_master_ops *ops = dsim_dev->master->master_ops;
++
++	struct dsi_cmd_packet data_to_send0 = {0x14, 0x00, 0x0};
++	struct dsi_cmd_packet data_to_send1 = {0x14, 0x01, 0x0};
++	struct dsi_cmd_packet data_to_send2 = {0x14, 0x02, 0x0};
++	struct dsi_cmd_packet set_page1 = {0x39, 0x04, 0x00, {0xFF, 0x98, 0x81, 0x01}};
++	struct dsi_cmd_packet set_page0 = {0x39, 0x04, 0x00, {0xFF, 0x98, 0x81, 0x00}};
++	int ret = 0;
++	int panel_id = 0;
++
++	panel_dev_power_on(dsim_dev, 1);
++	ops->cmd_write(dsim_dev->master,  set_page1);
++	ret = ops->cmd_read(dsim_dev->master, data_to_send0, &buf[0], 1);
++	ret = ops->cmd_read(dsim_dev->master, data_to_send1, &buf[1], 1);
++	ret = ops->cmd_read(dsim_dev->master, data_to_send2, &buf[2], 1);
++	ops->cmd_write(dsim_dev->master,  set_page0);
++	/* panel_dev_power_on(dsim_dev, 0); */
++	panel->power = 0;
++
++	panel_id = (buf[0] << 16) + (buf[1] << 8) + buf[2];
++	printk("----------%s, (%d) id[0]: %x id[1]: %x, id[2]: %x, id:%08x \n", __func__, __LINE__, buf[0], buf[1], buf[2], panel_id);
++
++	if(panel_id == PANEL_KD050HDFIA020_ID)
++		return 0;
++	else
++		return -1;
++}
++
++static void panel_dev_panel_init(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_device *dsi = lcd_to_master(lcd);
++	int  i;
++	int ret;
++
++	for (i = 0; i < ARRAY_SIZE(fitipower_kd050hdfia020_720_1280_cmd_list); i++)
++	{
++		ret = ops->cmd_write(dsi,  fitipower_kd050hdfia020_720_1280_cmd_list[i]);
++	}
++}
++
++static void panel_dev_set_sequence(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct kd050hdfia020 *lcd = dev_get_drvdata(&dsim_dev->dev);
++	PANEL_DEBUG_MSG("enter %s %d \n",__func__, __LINE__);
++
++	panel_dev_panel_init(panel);
++	panel_dev_sleep_out(panel);
++	mdelay(1);
++	panel_dev_display_on(panel);
++	/* msleep(1); */
++
++	lcd->power = FB_BLANK_UNBLANK;
++}
++
++
++static struct fb_videomode panel_modes = {
++	.name = "fitipower_kd050hdfia020-lcd",
++	.xres = 720,
++	.yres = 1280,
++
++	.refresh = 30,
++
++	.left_margin = 20,	//hbp
++	.right_margin = 50,	//hfp
++	.hsync_len = 6,	//hsync
++
++	.upper_margin = 10,	//vbp
++	.lower_margin = 20,	//vfp
++	.vsync_len = 6,	//vsync
++
++	.sync                   = FB_SYNC_HOR_HIGH_ACT & FB_SYNC_VERT_HIGH_ACT,
++	.vmode                  = FB_VMODE_NONINTERLACED,
++	.flag = 0,
++};
++
++struct jzdsi_data jzdsi_pdata = {
++	.modes = &panel_modes,
++	.video_config.no_of_lanes = 2,
++	.video_config.virtual_channel = 0,
++	.video_config.color_coding = COLOR_CODE_24BIT,
++	.video_config.video_mode = VIDEO_BURST_WITH_SYNC_PULSES,
++	.video_config.receive_ack_packets = 0,	/* enable receiving of ack packets */
++	.video_config.is_18_loosely = 0,
++	.video_config.data_en_polarity = 1,
++	.video_config.byte_clock = 0, // driver will auto calculate byte_clock.
++	.video_config.byte_clock_coef = MIPI_PHY_BYTE_CLK_COEF_MUL6_DIV5, // byte_clock *6/5.
++
++	.dsi_config.max_lanes = 2,
++	.dsi_config.max_hs_to_lp_cycles = 100,
++	.dsi_config.max_lp_to_hs_cycles = 40,
++	.dsi_config.max_bta_cycles = 4095,
++	.dsi_config.color_mode_polarity = 1,
++	.dsi_config.shut_down_polarity = 1,
++	.dsi_config.max_bps = 2750,
++	.bpp_info = 24,
++};
++
++static struct tft_config kd050hdfia020_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++struct lcd_panel lcd_panel = {
++	.num_modes = 1,
++	.modes = &panel_modes,
++	.dsi_pdata = &jzdsi_pdata,
++
++	.lcd_type = LCD_TYPE_MIPI_TFT,
++	.tft_config = &kd050hdfia020_cfg,
++	.bpp = 24,
++	.width = 62,
++	.height = 110,
++	.dither_enable = 0,
++	.dither.dither_red = 0,
++	.dither.dither_green = 0,
++	.dither.dither_blue = 0,
++};
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/*
++* @ pannel_kd050hdfia020_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++	PANEL_DEBUG_MSG("enter %s %d \n",__func__, __LINE__);
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		gpio_direction_output(panel->rst.gpio, !panel->rst.active_level);
++		gpio_direction_output(panel->rst.gpio, panel->rst.active_level);
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		gpio_direction_output(panel->vdd_en.gpio, !panel->vdd_en.active_level);
++		ret = gpio_request_one(panel->vdd_en.gpio, GPIOF_DIR_OUT, "vdd_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++			goto err_request_lcd_vdd;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	 panel->lcd_pwm.gpio = of_get_named_gpio_flags(np, "ingenic,lcd-pwm-gpio", 0, &flags);
++	 if(gpio_is_valid(panel->lcd_pwm.gpio)) {
++	 	panel->lcd_pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++	 	ret = gpio_request_one(panel->lcd_pwm.gpio, GPIOF_DIR_OUT, "lcd-pwm");
++	 	if(ret < 0) {
++	 		dev_err(dev, "Failed to request lcd-pwm pin!\n");
++	 		goto err_request_lcd_pwm;
++	 	}
++	 } else {
++	 	dev_warn(dev, "invalid gpio lcd-pwm.gpio: %d\n", panel->lcd_pwm.gpio);
++	 }
++
++	return 0;
++
++err_request_lcd_pwm:
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++err_request_lcd_vdd:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++	return ret;
++}
++
++static int panel_dev_probe(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct kd050hdfia020 *lcd;
++	char buffer[4];
++	int ret;
++	ret = panel_dev_read_id(dsim_dev, buffer, 4);
++	if(ret < 0) {
++		return -EINVAL;
++	}
++
++	lcd = devm_kzalloc(&dsim_dev->dev, sizeof(struct kd050hdfia020), GFP_KERNEL);
++	if (!lcd)
++	{
++		dev_err(&dsim_dev->dev, "failed to allocate fitipower_kd050hdfia020 structure.\n");
++		return -ENOMEM;
++	}
++
++	lcd->dsim_dev = dsim_dev;
++	lcd->dev = &dsim_dev->dev;
++
++	lcd->ld = lcd_device_register("fitipower_kd050hdfia020", lcd->dev, lcd,
++	                              &panel_lcd_ops);
++	if (IS_ERR(lcd->ld))
++	{
++		dev_err(lcd->dev, "failed to register lcd ops.\n");
++		return PTR_ERR(lcd->ld);
++	}
++
++	dev_set_drvdata(&dsim_dev->dev, lcd);
++
++	dev_dbg(lcd->dev, "probed fitipower_kd050hdfia020 panel driver.\n");
++
++
++	panel->dsim_dev = dsim_dev;
++
++
++	return 0;
++
++}
++
++static int panel_suspend(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	return 0;
++}
++
++static int panel_resume(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	return 0;
++}
++
++static struct mipi_dsim_lcd_driver panel_dev_dsim_ddi_driver = {
++	.name = "fitipower_kd050hdfia020-lcd",
++	.id = -1,
++
++	.power_on = panel_dev_power_on,
++	.set_sequence = panel_dev_set_sequence,
++	.probe = panel_dev_probe,
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++
++#ifdef CONFIG_PM
++static int panel_pm_suspend(struct device *dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++
++	panel_dev_display_off(panel);
++	panel_dev_sleep_in(panel);
++	gpio_direction_output(vdd_en->gpio, !vdd_en->active_level);
++
++	return 0;
++}
++
++static int panel_pm_resume(struct device *dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_pm_suspend,
++	.resume = panel_pm_resume,
++};
++#endif
++
++struct mipi_dsim_lcd_device panel_dev_device={
++	.name		= "fitipower_kd050hdfia020-lcd",
++	.id = 0,
++};
++
++/*
++* @panel_probe
++
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++
++* @pdev
++
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	PANEL_DEBUG_MSG("enter %s %d \n",__func__, __LINE__);
++
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	mipi_dsi_register_lcd_device(&panel_dev_device);
++	mipi_dsi_register_lcd_driver(&panel_dev_dsim_ddi_driver);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_of_parse;
++	}
++
++	return 0;
++
++err_of_parse:
++	if(gpio_is_valid(panel->lcd_pwm.gpio))
++		gpio_free(panel->lcd_pwm.gpio);
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,kd050hdfia020", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "kd050hdfia020",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++/* module_platform_driver(panel_driver); */
++static int __init panel_driver_init(void)
++{
++    return platform_driver_register(&(panel_driver));
++}
++fs_initcall(panel_driver_init);
++
++
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd050wvfpa029.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd050wvfpa029.c
+new file mode 100644
+index 000000000..6802787f7
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-kd050wvfpa029.c
+@@ -0,0 +1,307 @@
++/*
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * Author:zhxiao<zhihao.xiao@ingenic.com>
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++#include <linux/fb.h>
++#include <linux/backlight.h>
++
++#include "../ingenicfb.h"
++#include "../jz_dsim.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio bl;
++	struct board_gpio rst;
++	struct board_gpio pwm;
++};
++
++static struct panel_dev *panel;
++
++static void kd050wvfpa029_power_on(struct lcd_panel *ppanel)
++{
++	struct panel_dev *panel_kd050wvfpa029 = dev_get_drvdata(panel->dev);
++
++	if(panel_kd050wvfpa029->bl.gpio > 0){
++		gpio_direction_output(panel_kd050wvfpa029->bl.gpio, panel_kd050wvfpa029->bl.active_level);
++	}
++	if(panel_kd050wvfpa029->vdd_en.gpio > 0){
++		gpio_direction_output(panel_kd050wvfpa029->vdd_en.gpio, panel_kd050wvfpa029->vdd_en.active_level);
++	}
++}
++
++static void kd050wvfpa029_power_off(struct lcd_panel *ppanel)
++{
++	struct panel_dev *panel_kd050wvfpa029 = dev_get_drvdata(panel->dev);
++
++	if(panel_kd050wvfpa029->bl.gpio > 0){
++		gpio_direction_output(panel_kd050wvfpa029->bl.gpio, !panel_kd050wvfpa029->bl.active_level);
++	}
++	if(panel_kd050wvfpa029->vdd_en.gpio > 0){
++		gpio_direction_output(panel_kd050wvfpa029->vdd_en.gpio, !panel_kd050wvfpa029->vdd_en.active_level);
++	}
++	return;
++}
++
++static struct lcd_panel_ops kd050wvfpa029_ops = {
++	.enable  = (void*)kd050wvfpa029_power_on,
++	.disable = (void*)kd050wvfpa029_power_off,
++};
++
++static struct fb_videomode jzfb_kd050wvfpa029_videomode[] = {
++	[0] = {
++		.name = "800x480",
++		.refresh = 60,
++		.xres = 800,
++		.yres = 480,
++		.pixclock = KHZ2PICOS(27000),
++		.left_margin = 48,
++		.right_margin = 48,
++		.upper_margin = 12,
++		.lower_margin = 12,
++		.hsync_len = 8,
++		.vsync_len = 8,
++		.sync = ~FB_SYNC_HOR_HIGH_ACT & ~FB_SYNC_VERT_HIGH_ACT,
++		.vmode = FB_VMODE_NONINTERLACED,
++		.flag = 0,
++	},
++};
++
++
++struct lcd_panel lcd_panel = {
++	.name = "kd050wvfpa029",
++	.num_modes = ARRAY_SIZE(jzfb_kd050wvfpa029_videomode),
++	.modes = jzfb_kd050wvfpa029_videomode,
++	.lcd_type = LCD_TYPE_TFT,
++	.bpp = 32,
++	.width = 800,
++	.height = 480,
++
++	/*T40 RGB real line is 666, so, for RGB888, we discard low 2 bytes, config as follows:*/
++	.dither_enable = 0,
++	.dither.dither_red = 0,
++	.dither.dither_green = 0,
++	.dither.dither_blue = 0,
++
++	.ops = &kd050wvfpa029_ops,
++};
++
++#define RESET(n)\
++	gpio_direction_output(panel->rst.gpio, n)
++#define POWER_IS_ON(pwr)     ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++ * @ panel_kd050wvfpa029_lcd_ops, register to kernel common backlight/lcd.c frameworks.
++ */
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = devm_gpio_request(dev, panel->vdd_en.gpio, "vdd-en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	panel->bl.gpio = of_get_named_gpio_flags(np, "ingenic,lcd-pwm-gpio", 0, &flags);
++	if (gpio_is_valid(panel->bl.gpio)) {
++		panel->bl.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = devm_gpio_request(dev, panel->bl.gpio, "backlight");
++		if (ret < 0) {
++			dev_err(dev, "Failed to request backlight pin!\n");
++		//	return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio backlight.gpio: %d\n", panel->bl.gpio);
++	}
++
++
++	return 0;
++}
++
++static struct tft_config kd050wvfpa029_bgr_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.vsync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_BGR,
++	.color_odd = TFT_LCD_COLOR_ODD_BGR,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++static struct tft_config kd050wvfpa029_rgb_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.vsync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,kd050wvfpa029", .data = (struct tft_config *)&kd050wvfpa029_bgr_cfg, },
++	{ .compatible = "ingenic,kd050wvfpa029-rgb", .data = (struct tft_config *)&kd050wvfpa029_rgb_cfg, },
++	{},
++};
++
++/**
++ * @panel_probe
++ *
++ *	1. register to ingenicfb.
++ *	2. register to lcd.
++ *	3. register to backlight if possible.
++ *
++ *	@pdev
++ *
++ *	@return -
++ * */
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	struct backlight_properties props;   //backlight properties
++	const struct of_device_id *priv;
++
++	memset(&props, 0, sizeof(props));
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if (NULL == panel) {
++		dev_err(&pdev->dev, "Failed to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	/* panel pinctrl parse */
++	ret = of_panel_parse(&pdev->dev);
++	if (ret < 0) {
++		goto err_of_parse;
++	}
++
++	panel->lcd = lcd_device_register("panel_lcd", &pdev->dev, panel, &panel_lcd_ops);
++	if (IS_ERR_OR_NULL(panel->lcd)) {
++		dev_err(&pdev->dev, "Error register lcd!");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++	priv = of_match_node(panel_of_match, pdev->dev.of_node);
++	lcd_panel.tft_config = (struct tft_config *)priv->data;
++
++	/* TODO: should this power status sync from uboot */
++	panel->power = FB_BLANK_POWERDOWN;
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++
++	return 0;
++
++err_lcd_register:
++	lcd_device_unregister(panel->lcd);
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	struct panel_dev *panel = dev_get_drvdata(&pdev->dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int panel_suspend(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++static int panel_resume(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++#endif
++
++static struct platform_driver panel_driver = {
++	.probe = panel_probe,
++	.remove = panel_remove,
++	.driver = {
++		.name = "kd050wvfpa029",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-ma0060.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-ma0060.c
+new file mode 100644
+index 000000000..3f7b80fc4
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-ma0060.c
+@@ -0,0 +1,1115 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-ma0060.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++#include <linux/fb.h>
++#include <linux/backlight.h>
++
++
++#include "../ingenicfb.h"
++#include "../jz_dsim.h"
++
++//#define _1080P
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio oled;
++	struct board_gpio lcd_pwm;
++	struct board_gpio swire;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++};
++
++static struct panel_dev *panel;
++
++#define lcd_to_master(a)	(a->dsim_dev->master)
++#define lcd_to_master_ops(a)	((lcd_to_master(a))->master_ops)
++
++#define PANEL_MA0060_ID		(0x8000)
++
++
++struct ma0060 {
++	struct device *dev;
++	unsigned int power;
++	unsigned int id;
++
++	struct lcd_device *ld;
++	struct backlight_device *bd;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++
++};
++
++static struct dsi_cmd_packet visionox_ma0060_720p_cmd_list1[] =
++{
++	{0x39, 0x02, 0x00, {0xFE, 0xD0}},
++	{0x39, 0x02, 0x00, {0x40, 0x02}},
++	{0x39, 0x02, 0x00, {0x4B, 0x4C}},
++	{0x39, 0x02, 0x00, {0x49, 0x01}},
++
++	/* {0x39, 0x02, 0x00, {0xFE, 0xD0}}, /1* �2 lane 设置】 *1/ */
++	{0x39, 0x02, 0x00, {0x1E, 0x05}},
++
++	{0x39, 0x02, 0x00, {0xFE, 0x40}},
++	{0x39, 0x02, 0x00, {0xC7, 0x85}},
++	{0x39, 0x02, 0x00, {0xC8, 0x32}},
++	{0x39, 0x02, 0x00, {0xC9, 0x18}},
++	{0x39, 0x02, 0x00, {0xCA, 0x09}},
++	{0x39, 0x02, 0x00, {0xCB, 0x22}},
++	{0x39, 0x02, 0x00, {0xCC, 0x44}},
++	{0x39, 0x02, 0x00, {0xCD, 0x11}},
++	{0x39, 0x02, 0x00, {0x05, 0x0F}},
++	{0x39, 0x02, 0x00, {0x06, 0x09}},
++	{0x39, 0x02, 0x00, {0x08, 0x0F}},
++	{0x39, 0x02, 0x00, {0x09, 0x09}},
++	{0x39, 0x02, 0x00, {0x0A, 0xE6}},
++	{0x39, 0x02, 0x00, {0x0B, 0x88}},
++
++	{0x39, 0x02, 0x00, {0x0E, 0x10}},
++	{0x39, 0x02, 0x00, {0x20, 0x93}},
++	{0x39, 0x02, 0x00, {0x21, 0x93}},
++	{0x39, 0x02, 0x00, {0x24, 0x02}},
++	{0x39, 0x02, 0x00, {0x26, 0x02}},
++	{0x39, 0x02, 0x00, {0x28, 0x05}},
++	{0x39, 0x02, 0x00, {0x2A, 0x05}},
++	{0x39, 0x02, 0x00, {0x2D, 0x23}},
++	{0x39, 0x02, 0x00, {0x2F, 0x23}},
++	{0x39, 0x02, 0x00, {0x30, 0x23}},
++	{0x39, 0x02, 0x00, {0x31, 0x23}},
++	{0x39, 0x02, 0x00, {0x37, 0x80}},
++	{0x39, 0x02, 0x00, {0x38, 0x50}},
++	{0x39, 0x02, 0x00, {0x39, 0x00}},
++	{0x39, 0x02, 0x00, {0x46, 0x27}},
++	{0x39, 0x02, 0x00, {0x6F, 0x00}},
++	{0x39, 0x02, 0x00, {0x74, 0x2F}},
++	{0x39, 0x02, 0x00, {0x75, 0x19}},
++	{0x39, 0x02, 0x00, {0x79, 0x00}},
++	{0x39, 0x02, 0x00, {0xAD, 0x00}},
++	{0x39, 0x02, 0x00, {0xFE, 0x60}},
++	{0x39, 0x02, 0x00, {0x00, 0xC4}},
++	{0x39, 0x02, 0x00, {0x01, 0x00}},
++	{0x39, 0x02, 0x00, {0x02, 0x02}},
++	{0x39, 0x02, 0x00, {0x03, 0x00}},
++	{0x39, 0x02, 0x00, {0x04, 0x00}},
++	{0x39, 0x02, 0x00, {0x05, 0x07}},
++	{0x39, 0x02, 0x00, {0x06, 0x00}},
++	{0x39, 0x02, 0x00, {0x07, 0x83}},
++	{0x39, 0x02, 0x00, {0x09, 0xC4}},
++	{0x39, 0x02, 0x00, {0x0A, 0x00}},
++	{0x39, 0x02, 0x00, {0x0B, 0x02}},
++	{0x39, 0x02, 0x00, {0x0C, 0x00}},
++	{0x39, 0x02, 0x00, {0x0D, 0x00}},
++	{0x39, 0x02, 0x00, {0x0E, 0x08}},
++	{0x39, 0x02, 0x00, {0x0F, 0x00}},
++	{0x39, 0x02, 0x00, {0x10, 0x83}},
++	{0x39, 0x02, 0x00, {0x12, 0xCC}},
++	{0x39, 0x02, 0x00, {0x13, 0x0F}},
++	{0x39, 0x02, 0x00, {0x14, 0xFF}},
++	{0x39, 0x02, 0x00, {0x15, 0x01}},
++	{0x39, 0x02, 0x00, {0x16, 0x00}},
++	{0x39, 0x02, 0x00, {0x17, 0x02}},
++	{0x39, 0x02, 0x00, {0x18, 0x00}},
++	{0x39, 0x02, 0x00, {0x19, 0x00}},
++	{0x39, 0x02, 0x00, {0x1B, 0xC4}},
++	{0x39, 0x02, 0x00, {0x1C, 0x00}},
++	{0x39, 0x02, 0x00, {0x1D, 0x02}},
++	{0x39, 0x02, 0x00, {0x1E, 0x00}},
++	{0x39, 0x02, 0x00, {0x1F, 0x00}},
++	{0x39, 0x02, 0x00, {0x20, 0x08}},
++	{0x39, 0x02, 0x00, {0x21, 0x00}},
++	{0x39, 0x02, 0x00, {0x22, 0x89}},
++	{0x39, 0x02, 0x00, {0x24, 0xC4}},
++	{0x39, 0x02, 0x00, {0x25, 0x00}},
++	{0x39, 0x02, 0x00, {0x26, 0x02}},
++	{0x39, 0x02, 0x00, {0x27, 0x00}},
++	{0x39, 0x02, 0x00, {0x28, 0x00}},
++	{0x39, 0x02, 0x00, {0x29, 0x07}},
++	{0x39, 0x02, 0x00, {0x2A, 0x00}},
++	{0x39, 0x02, 0x00, {0x2B, 0x89}},
++	{0x39, 0x02, 0x00, {0x2F, 0xC4}},
++	{0x39, 0x02, 0x00, {0x30, 0x00}},
++	{0x39, 0x02, 0x00, {0x31, 0x02}},
++	{0x39, 0x02, 0x00, {0x32, 0x00}},
++	{0x39, 0x02, 0x00, {0x33, 0x00}},
++	{0x39, 0x02, 0x00, {0x34, 0x06}},
++	{0x39, 0x02, 0x00, {0x35, 0x00}},
++	{0x39, 0x02, 0x00, {0x36, 0x89}},
++	{0x39, 0x02, 0x00, {0x38, 0xC4}},
++	{0x39, 0x02, 0x00, {0x39, 0x00}},
++	{0x39, 0x02, 0x00, {0x3A, 0x02}},
++	{0x39, 0x02, 0x00, {0x3B, 0x00}},
++	{0x39, 0x02, 0x00, {0x3D, 0x00}},
++	{0x39, 0x02, 0x00, {0x3F, 0x07}},
++	{0x39, 0x02, 0x00, {0x40, 0x00}},
++	{0x39, 0x02, 0x00, {0x41, 0x89}},
++	{0x39, 0x02, 0x00, {0x4C, 0xC4}},
++	{0x39, 0x02, 0x00, {0x4D, 0x00}},
++	{0x39, 0x02, 0x00, {0x4E, 0x04}},
++	{0x39, 0x02, 0x00, {0x4F, 0x01}},
++	{0x39, 0x02, 0x00, {0x50, 0x00}},
++	{0x39, 0x02, 0x00, {0x51, 0x08}},
++	{0x39, 0x02, 0x00, {0x52, 0x00}},
++	{0x39, 0x02, 0x00, {0x53, 0x61}},
++	{0x39, 0x02, 0x00, {0x55, 0xC4}},
++	{0x39, 0x02, 0x00, {0x56, 0x00}},
++	{0x39, 0x02, 0x00, {0x58, 0x04}},
++	{0x39, 0x02, 0x00, {0x59, 0x01}},
++	{0x39, 0x02, 0x00, {0x5A, 0x00}},
++	{0x39, 0x02, 0x00, {0x5B, 0x06}},
++	{0x39, 0x02, 0x00, {0x5C, 0x00}},
++	{0x39, 0x02, 0x00, {0x5D, 0x61}},
++	{0x39, 0x02, 0x00, {0x5F, 0xCE}},
++	{0x39, 0x02, 0x00, {0x60, 0x00}},
++	{0x39, 0x02, 0x00, {0x61, 0x07}},
++	{0x39, 0x02, 0x00, {0x62, 0x05}},
++	{0x39, 0x02, 0x00, {0x63, 0x00}},
++	{0x39, 0x02, 0x00, {0x64, 0x04}},
++	{0x39, 0x02, 0x00, {0x65, 0x00}},
++	{0x39, 0x02, 0x00, {0x66, 0x60}},
++	{0x39, 0x02, 0x00, {0x67, 0x80}},
++	{0x39, 0x02, 0x00, {0x9B, 0x03}},
++	{0x39, 0x02, 0x00, {0xA9, 0x10}},
++	{0x39, 0x02, 0x00, {0xAA, 0x10}},
++	{0x39, 0x02, 0x00, {0xAB, 0x02}},
++	{0x39, 0x02, 0x00, {0xAC, 0x04}},
++	{0x39, 0x02, 0x00, {0xAD, 0x03}},
++	{0x39, 0x02, 0x00, {0xAE, 0x10}},
++	{0x39, 0x02, 0x00, {0xAF, 0x10}},
++	{0x39, 0x02, 0x00, {0xB0, 0x10}},
++	{0x39, 0x02, 0x00, {0xB1, 0x10}},
++	{0x39, 0x02, 0x00, {0xB2, 0x10}},
++	{0x39, 0x02, 0x00, {0xB3, 0x10}},
++	{0x39, 0x02, 0x00, {0xB4, 0x10}},
++	{0x39, 0x02, 0x00, {0xB5, 0x10}},
++	{0x39, 0x02, 0x00, {0xB6, 0x10}},
++	{0x39, 0x02, 0x00, {0xB7, 0x10}},
++	{0x39, 0x02, 0x00, {0xB8, 0x10}},
++	{0x39, 0x02, 0x00, {0xB9, 0x08}},
++	{0x39, 0x02, 0x00, {0xBA, 0x09}},
++	{0x39, 0x02, 0x00, {0xBB, 0x0A}},
++	{0x39, 0x02, 0x00, {0xBC, 0x05}},
++	{0x39, 0x02, 0x00, {0xBD, 0x06}},
++	{0x39, 0x02, 0x00, {0xBE, 0x02}},
++	{0x39, 0x02, 0x00, {0xBF, 0x10}},
++	{0x39, 0x02, 0x00, {0xC0, 0x10}},
++	{0x39, 0x02, 0x00, {0xC1, 0x03}},
++	{0x39, 0x02, 0x00, {0xC4, 0x80}},
++	{0x39, 0x02, 0x00, {0xFE, 0x70}},
++	{0x39, 0x02, 0x00, {0x48, 0x05}},
++	{0x39, 0x02, 0x00, {0x52, 0x00}},
++	{0x39, 0x02, 0x00, {0x5A, 0xFF}},
++	{0x39, 0x02, 0x00, {0x5C, 0xF6}},
++	{0x39, 0x02, 0x00, {0x5D, 0x07}},
++	{0x39, 0x02, 0x00, {0x7D, 0x75}},
++	{0x39, 0x02, 0x00, {0x86, 0x07}},
++	{0x39, 0x02, 0x00, {0xA7, 0x02}},
++	{0x39, 0x02, 0x00, {0xA9, 0x2C}},
++	{0x39, 0x02, 0x00, {0xFE, 0xA0}},
++	{0x39, 0x02, 0x00, {0x2B, 0x18}},
++
++#if 1
++	{0x39, 0x02, 0x00, {0xFE, 0x40}}, /* �scaling up 设置】 */
++	{0x39, 0x02, 0x00, {0x36, 0x55}}, //scal_en */
++	{0x39, 0x02, 0x00, {0x0D, 0x90}}, //2a2b_en */
++	{0x39, 0x02, 0x00, {0x0E, 0x00}},
++
++	{0x39, 0x02, 0x00, {0xFE, 0xD0}},
++	{0x39, 0x02, 0x00, {0x07, 0x84}},
++
++	{0x39, 0x02, 0x00, {0xFE, 0x00}},
++	{0x39, 0x05, 0x00, {0x2A, 0x00, 0x00, 0x02, 0xCF}},
++	{0x39, 0x05, 0x00, {0x2B, 0x00, 0x00, 0x04, 0xFF}},
++#endif
++};
++
++#ifndef _1080P
++static struct dsi_cmd_packet visionox_ma0060_720p_cmd_list2[] =
++{
++	{0x15, 0xFE, 0x00},
++	{0x15, 0xC2, 0x08},
++	{0x15, 0x35, 0x00},
++};
++
++static struct dsi_cmd_packet visionox_ma0060_720p_cmd_list11[] =
++{
++	{0X39, 0X02, 0X00, {0XFE, 0XD0}},
++	{0X39, 0X02, 0X00, {0X07, 0X84}},
++	{0X39, 0X02, 0X00, {0X40, 0X02}},
++	{0X39, 0X02, 0X00, {0X4B, 0X4C}},
++	{0X39, 0X02, 0X00, {0X49, 0X01}},
++	{0X39, 0X02, 0X00, {0XFE, 0X40}},
++	{0X39, 0X02, 0X00, {0XC7, 0X85}},
++	{0X39, 0X02, 0X00, {0XC8, 0X32}},
++	{0X39, 0X02, 0X00, {0XC9, 0X18}},
++	{0X39, 0X02, 0X00, {0XCA, 0X09}},
++	{0X39, 0X02, 0X00, {0XCB, 0X22}},
++	{0X39, 0X02, 0X00, {0XCC, 0X44}},
++	{0X39, 0X02, 0X00, {0XCD, 0X11}},
++	{0X39, 0X02, 0X00, {0X05, 0X0F}},
++	{0X39, 0X02, 0X00, {0X06, 0X09}},
++	{0X39, 0X02, 0X00, {0X08, 0X0F}},
++	{0X39, 0X02, 0X00, {0X09, 0X09}},
++	{0X39, 0X02, 0X00, {0X0A, 0XE6}},
++	{0X39, 0X02, 0X00, {0X0B, 0X88}},
++	{0X39, 0X02, 0X00, {0X0D, 0X90}},
++	{0X39, 0X02, 0X00, {0X0E, 0X10}},
++	{0X39, 0X02, 0X00, {0X20, 0X93}},
++	{0X39, 0X02, 0X00, {0X21, 0X93}},
++	{0X39, 0X02, 0X00, {0X24, 0X02}},
++	{0X39, 0X02, 0X00, {0X26, 0X02}},
++	{0X39, 0X02, 0X00, {0X28, 0X05}},
++	{0X39, 0X02, 0X00, {0X2A, 0X05}},
++	{0X39, 0X02, 0X00, {0X2D, 0X23}},
++	{0X39, 0X02, 0X00, {0X2F, 0X23}},
++	{0X39, 0X02, 0X00, {0X30, 0X23}},
++	{0X39, 0X02, 0X00, {0X31, 0X23}},
++	{0X39, 0X02, 0X00, {0X36, 0X55}},
++	{0X39, 0X02, 0X00, {0X37, 0X80}},
++	{0X39, 0X02, 0X00, {0X38, 0X50}},
++	{0X39, 0X02, 0X00, {0X39, 0X00}},
++	{0X39, 0X02, 0X00, {0X46, 0X27}},
++	{0X39, 0X02, 0X00, {0X6F, 0X00}},
++	{0X39, 0X02, 0X00, {0X74, 0X2F}},
++	{0X39, 0X02, 0X00, {0X75, 0X19}},
++	{0X39, 0X02, 0X00, {0X79, 0X00}},
++	{0X39, 0X02, 0X00, {0XAD, 0X00}},
++	{0X39, 0X02, 0X00, {0XFE, 0X60}},
++	{0X39, 0X02, 0X00, {0X00, 0XC4}},
++	{0X39, 0X02, 0X00, {0X01, 0X00}},
++	{0X39, 0X02, 0X00, {0X02, 0X02}},
++	{0X39, 0X02, 0X00, {0X03, 0X00}},
++	{0X39, 0X02, 0X00, {0X04, 0X00}},
++	{0X39, 0X02, 0X00, {0X05, 0X07}},
++	{0X39, 0X02, 0X00, {0X06, 0X00}},
++	{0X39, 0X02, 0X00, {0X07, 0X83}},
++	{0X39, 0X02, 0X00, {0X09, 0XC4}},
++	{0X39, 0X02, 0X00, {0X0A, 0X00}},
++	{0X39, 0X02, 0X00, {0X0B, 0X02}},
++	{0X39, 0X02, 0X00, {0X0C, 0X00}},
++	{0X39, 0X02, 0X00, {0X0D, 0X00}},
++	{0X39, 0X02, 0X00, {0X0E, 0X08}},
++	{0X39, 0X02, 0X00, {0X0F, 0X00}},
++	{0X39, 0X02, 0X00, {0X10, 0X83}},
++	{0X39, 0X02, 0X00, {0X12, 0XCC}},
++	{0X39, 0X02, 0X00, {0X13, 0X0F}},
++	{0X39, 0X02, 0X00, {0X14, 0XFF}},
++	{0X39, 0X02, 0X00, {0X15, 0X01}},
++	{0X39, 0X02, 0X00, {0X16, 0X00}},
++	{0X39, 0X02, 0X00, {0X17, 0X02}},
++	{0X39, 0X02, 0X00, {0X18, 0X00}},
++	{0X39, 0X02, 0X00, {0X19, 0X00}},
++	{0X39, 0X02, 0X00, {0X1B, 0XC4}},
++	{0X39, 0X02, 0X00, {0X1C, 0X00}},
++	{0X39, 0X02, 0X00, {0X1D, 0X02}},
++	{0X39, 0X02, 0X00, {0X1E, 0X00}},
++	{0X39, 0X02, 0X00, {0X1F, 0X00}},
++	{0X39, 0X02, 0X00, {0X20, 0X08}},
++	{0X39, 0X02, 0X00, {0X21, 0X00}},
++	{0X39, 0X02, 0X00, {0X22, 0X89}},
++	{0X39, 0X02, 0X00, {0X24, 0XC4}},
++	{0X39, 0X02, 0X00, {0X25, 0X00}},
++	{0X39, 0X02, 0X00, {0X26, 0X02}},
++	{0X39, 0X02, 0X00, {0X27, 0X00}},
++	{0X39, 0X02, 0X00, {0X28, 0X00}},
++	{0X39, 0X02, 0X00, {0X29, 0X07}},
++	{0X39, 0X02, 0X00, {0X2A, 0X00}},
++	{0X39, 0X02, 0X00, {0X2B, 0X89}},
++	{0X39, 0X02, 0X00, {0X2F, 0XC4}},
++	{0X39, 0X02, 0X00, {0X30, 0X00}},
++	{0X39, 0X02, 0X00, {0X31, 0X02}},
++	{0X39, 0X02, 0X00, {0X32, 0X00}},
++	{0X39, 0X02, 0X00, {0X33, 0X00}},
++	{0X39, 0X02, 0X00, {0X34, 0X06}},
++	{0X39, 0X02, 0X00, {0X35, 0X00}},
++	{0X39, 0X02, 0X00, {0X36, 0X89}},
++	{0X39, 0X02, 0X00, {0X38, 0XC4}},
++	{0X39, 0X02, 0X00, {0X39, 0X00}},
++	{0X39, 0X02, 0X00, {0X3A, 0X02}},
++	{0X39, 0X02, 0X00, {0X3B, 0X00}},
++	{0X39, 0X02, 0X00, {0X3D, 0X00}},
++	{0X39, 0X02, 0X00, {0X3F, 0X07}},
++	{0X39, 0X02, 0X00, {0X40, 0X00}},
++	{0X39, 0X02, 0X00, {0X41, 0X89}},
++	{0X39, 0X02, 0X00, {0X4C, 0XC4}},
++	{0X39, 0X02, 0X00, {0X4D, 0X00}},
++	{0X39, 0X02, 0X00, {0X4E, 0X04}},
++	{0X39, 0X02, 0X00, {0X4F, 0X01}},
++	{0X39, 0X02, 0X00, {0X50, 0X00}},
++	{0X39, 0X02, 0X00, {0X51, 0X08}},
++	{0X39, 0X02, 0X00, {0X52, 0X00}},
++	{0X39, 0X02, 0X00, {0X53, 0X61}},
++	{0X39, 0X02, 0X00, {0X55, 0XC4}},
++	{0X39, 0X02, 0X00, {0X56, 0X00}},
++	{0X39, 0X02, 0X00, {0X58, 0X04}},
++	{0X39, 0X02, 0X00, {0X59, 0X01}},
++	{0X39, 0X02, 0X00, {0X5A, 0X00}},
++	{0X39, 0X02, 0X00, {0X5B, 0X06}},
++	{0X39, 0X02, 0X00, {0X5C, 0X00}},
++	{0X39, 0X02, 0X00, {0X5D, 0X61}},
++	{0X39, 0X02, 0X00, {0X5F, 0XCE}},
++	{0X39, 0X02, 0X00, {0X60, 0X00}},
++	{0X39, 0X02, 0X00, {0X61, 0X07}},
++	{0X39, 0X02, 0X00, {0X62, 0X05}},
++	{0X39, 0X02, 0X00, {0X63, 0X00}},
++	{0X39, 0X02, 0X00, {0X64, 0X04}},
++	{0X39, 0X02, 0X00, {0X65, 0X00}},
++	{0X39, 0X02, 0X00, {0X66, 0X60}},
++	{0X39, 0X02, 0X00, {0X67, 0X80}},
++	{0X39, 0X02, 0X00, {0X9B, 0X03}},
++	{0X39, 0X02, 0X00, {0XA9, 0X10}},
++	{0X39, 0X02, 0X00, {0XAA, 0X10}},
++	{0X39, 0X02, 0X00, {0XAB, 0X02}},
++	{0X39, 0X02, 0X00, {0XAC, 0X04}},
++	{0X39, 0X02, 0X00, {0XAD, 0X03}},
++	{0X39, 0X02, 0X00, {0XAE, 0X10}},
++	{0X39, 0X02, 0X00, {0XAF, 0X10}},
++	{0X39, 0X02, 0X00, {0XB0, 0X10}},
++	{0X39, 0X02, 0X00, {0XB1, 0X10}},
++	{0X39, 0X02, 0X00, {0XB2, 0X10}},
++	{0X39, 0X02, 0X00, {0XB3, 0X10}},
++	{0X39, 0X02, 0X00, {0XB4, 0X10}},
++	{0X39, 0X02, 0X00, {0XB5, 0X10}},
++	{0X39, 0X02, 0X00, {0XB6, 0X10}},
++	{0X39, 0X02, 0X00, {0XB7, 0X10}},
++	{0X39, 0X02, 0X00, {0XB8, 0X10}},
++	{0X39, 0X02, 0X00, {0XB9, 0X08}},
++	{0X39, 0X02, 0X00, {0XBA, 0X09}},
++	{0X39, 0X02, 0X00, {0XBB, 0X0A}},
++	{0X39, 0X02, 0X00, {0XBC, 0X05}},
++	{0X39, 0X02, 0X00, {0XBD, 0X06}},
++	{0X39, 0X02, 0X00, {0XBE, 0X02}},
++	{0X39, 0X02, 0X00, {0XBF, 0X10}},
++	{0X39, 0X02, 0X00, {0XC0, 0X10}},
++	{0X39, 0X02, 0X00, {0XC1, 0X03}},
++	{0X39, 0X02, 0X00, {0XC4, 0X80}},
++	{0X39, 0X02, 0X00, {0XFE, 0X70}},
++	{0X39, 0X02, 0X00, {0X48, 0X05}},
++	{0X39, 0X02, 0X00, {0X52, 0X00}},
++	{0X39, 0X02, 0X00, {0X5A, 0XFF}},
++	{0X39, 0X02, 0X00, {0X5C, 0XF6}},
++	{0X39, 0X02, 0X00, {0X5D, 0X07}},
++	{0X39, 0X02, 0X00, {0X7D, 0X75}},
++	{0X39, 0X02, 0X00, {0X86, 0X07}},
++	{0X39, 0X02, 0X00, {0XA7, 0X02}},
++	{0X39, 0X02, 0X00, {0XA9, 0X2C}},
++	{0X39, 0X02, 0X00, {0XFE, 0XA0}},
++	{0X39, 0X02, 0X00, {0X2B, 0X18}},
++
++	{0x39, 0x02, 0x00, {0xFE, 0xD0}}, /* �2 lane 设置】 */
++	{0x39, 0x02, 0x00, {0x1E, 0x05}},
++
++	{0x39, 0x02, 0x00, {0xFE, 0x00}},
++	{0x39, 0x05, 0x00, {0x2A, 0x00, 0x00, 0x02, 0xCF}},
++	{0x39, 0x05, 0x00, {0x2B, 0x00, 0x00, 0x04, 0xFF}},
++};
++#endif
++
++#ifdef _1080P
++static struct dsi_cmd_packet visionox_ma0060_1080p_cmd_list1[] =
++{
++	{0x39, 0x02, 0x00, {0xFE, 0x04}},
++	{0x39, 0x02, 0x00, {0x01, 0x08}},
++	{0x39, 0x02, 0x00, {0x0D, 0x80}},
++	{0x39, 0x02, 0x00, {0x05, 0x07}},
++	{0x39, 0x02, 0x00, {0x06, 0x09}},
++	{0x39, 0x02, 0x00, {0x0A, 0xDB}},
++	{0x39, 0x02, 0x00, {0x0B, 0x8C}},
++	{0x39, 0x02, 0x00, {0x0E, 0x10}},
++	{0x39, 0x02, 0x00, {0x0F, 0xE0}},
++	{0x39, 0x02, 0x00, {0x1A, 0x11}},
++	{0x39, 0x02, 0x00, {0x29, 0x93}},
++	{0x39, 0x02, 0x00, {0x2A, 0x93}},
++	{0x39, 0x02, 0x00, {0x2F, 0x02}},
++	{0x39, 0x02, 0x00, {0x31, 0x02}},
++	{0x39, 0x02, 0x00, {0x33, 0x05}},
++	{0x39, 0x02, 0x00, {0x37, 0x23}},
++	{0x39, 0x02, 0x00, {0x38, 0x23}},
++	{0x39, 0x02, 0x00, {0x3A, 0x23}},
++	{0x39, 0x02, 0x00, {0x3B, 0x23}},
++	{0x39, 0x02, 0x00, {0x3D, 0x2C}},
++	{0x39, 0x02, 0x00, {0x3F, 0x80}},
++	{0x39, 0x02, 0x00, {0x40, 0x50}},
++	{0x39, 0x02, 0x00, {0x41, 0x8E}},
++	{0x39, 0x02, 0x00, {0x4F, 0x2F}},
++	{0x39, 0x02, 0x00, {0x50, 0x19}},
++	{0x39, 0x02, 0x00, {0x51, 0x0A}},
++
++	{0x39, 0x02, 0x00, {0xFE, 0x07}},
++	{0x39, 0x02, 0x00, {0x03, 0x40}},
++	{0x39, 0x02, 0x00, {0x05, 0x00}},
++	{0x39, 0x02, 0x00, {0x07, 0x0A}},
++
++	{0x39, 0x02, 0x00, {0xFE, 0x06}},
++	{0x39, 0x02, 0x00, {0xB0, 0x11}},
++	{0x39, 0x02, 0x00, {0x00, 0xE4}},
++	{0x39, 0x02, 0x00, {0x01, 0x0F}},
++	{0x39, 0x02, 0x00, {0x02, 0xFF}},
++	{0x39, 0x02, 0x00, {0x03, 0x00}},
++	{0x39, 0x02, 0x00, {0x04, 0x00}},
++	{0x39, 0x02, 0x00, {0x05, 0x02}},
++	{0x39, 0x02, 0x00, {0x06, 0x00}},
++	{0x39, 0x02, 0x00, {0x07, 0xC0}},
++	{0x39, 0x02, 0x00, {0x08, 0xE4}},
++	{0x39, 0x02, 0x00, {0x09, 0x00}},
++	{0x39, 0x02, 0x00, {0x0A, 0x02}},
++	{0x39, 0x02, 0x00, {0x0B, 0x00}},
++	{0x39, 0x02, 0x00, {0x0C, 0x00}},
++	{0x39, 0x02, 0x00, {0x0D, 0x08}},
++	{0x39, 0x02, 0x00, {0x0E, 0x00}},
++	{0x39, 0x02, 0x00, {0x0F, 0x83}},
++	{0x39, 0x02, 0x00, {0x10, 0xE4}},
++	{0x39, 0x02, 0x00, {0x11, 0x00}},
++	{0x39, 0x02, 0x00, {0x12, 0x02}},
++	{0x39, 0x02, 0x00, {0x13, 0x00}},
++	{0x39, 0x02, 0x00, {0x14, 0x00}},
++	{0x39, 0x02, 0x00, {0x15, 0x07}},
++	{0x39, 0x02, 0x00, {0x16, 0x00}},
++	{0x39, 0x02, 0x00, {0x17, 0x67}},
++	{0x39, 0x02, 0x00, {0x18, 0xE4}},
++	{0x39, 0x02, 0x00, {0x19, 0x00}},
++	{0x39, 0x02, 0x00, {0x1A, 0x02}},
++	{0x39, 0x02, 0x00, {0x1B, 0x00}},
++	{0x39, 0x02, 0x00, {0x1C, 0x00}},
++	{0x39, 0x02, 0x00, {0x1D, 0x07}},
++	{0x39, 0x02, 0x00, {0x1E, 0x00}},
++	{0x39, 0x02, 0x00, {0x1F, 0x67}},
++	{0x39, 0x02, 0x00, {0x20, 0xE4}},
++	{0x39, 0x02, 0x00, {0x21, 0x00}},
++	{0x39, 0x02, 0x00, {0x22, 0x02}},
++	{0x39, 0x02, 0x00, {0x23, 0x00}},
++	{0x39, 0x02, 0x00, {0x24, 0x00}},
++	{0x39, 0x02, 0x00, {0x25, 0x08}},
++	{0x39, 0x02, 0x00, {0x26, 0x00}},
++	{0x39, 0x02, 0x00, {0x27, 0x83}},
++	{0x39, 0x02, 0x00, {0x28, 0xE4}},
++	{0x39, 0x02, 0x00, {0x29, 0x00}},
++	{0x39, 0x02, 0x00, {0x2A, 0x02}},
++	{0x39, 0x02, 0x00, {0x2B, 0x00}},
++	{0x39, 0x02, 0x00, {0x2D, 0x00}},
++	{0x39, 0x02, 0x00, {0x2F, 0x07}},
++	{0x39, 0x02, 0x00, {0x30, 0x00}},
++	{0x39, 0x02, 0x00, {0x31, 0x67}},
++	{0x39, 0x02, 0x00, {0x32, 0xE4}},
++	{0x39, 0x02, 0x00, {0x33, 0x00}},
++	{0x39, 0x02, 0x00, {0x34, 0x02}},
++	{0x39, 0x02, 0x00, {0x35, 0x00}},
++	{0x39, 0x02, 0x00, {0x36, 0x00}},
++	{0x39, 0x02, 0x00, {0x37, 0x08}},
++	{0x39, 0x02, 0x00, {0x38, 0x00}},
++	{0x39, 0x02, 0x00, {0x39, 0x67}},
++	{0x39, 0x02, 0x00, {0x44, 0xE4}},
++	{0x39, 0x02, 0x00, {0x45, 0x00}},
++	{0x39, 0x02, 0x00, {0x46, 0x04}},
++	{0x39, 0x02, 0x00, {0x47, 0x01}},
++	{0x39, 0x02, 0x00, {0x48, 0x00}},
++	{0x39, 0x02, 0x00, {0x49, 0x08}},
++	{0x39, 0x02, 0x00, {0x4A, 0x00}},
++	{0x39, 0x02, 0x00, {0x4B, 0x64}},
++	{0x39, 0x02, 0x00, {0x4C, 0xE4}},
++	{0x39, 0x02, 0x00, {0x4D, 0x00}},
++	{0x39, 0x02, 0x00, {0x4E, 0x04}},
++	{0x39, 0x02, 0x00, {0x4F, 0x01}},
++	{0x39, 0x02, 0x00, {0x50, 0x00}},
++	{0x39, 0x02, 0x00, {0x51, 0x06}},
++	{0x39, 0x02, 0x00, {0x52, 0x00}},
++	{0x39, 0x02, 0x00, {0x53, 0x64}},
++	{0x39, 0x02, 0x00, {0x8D, 0xEA}},
++	{0x39, 0x02, 0x00, {0x8E, 0x0F}},
++	{0x39, 0x02, 0x00, {0x8F, 0xFF}},
++	{0x39, 0x02, 0x00, {0x90, 0x05}},
++	{0x39, 0x02, 0x00, {0x91, 0x00}},
++	{0x39, 0x02, 0x00, {0x92, 0x04}},
++	{0x39, 0x02, 0x00, {0x93, 0x00}},
++	{0x39, 0x02, 0x00, {0x94, 0xAB}},
++	{0x39, 0x02, 0x00, {0xAC, 0x00}},
++	{0x39, 0x02, 0x00, {0xA6, 0x20}},
++	{0x39, 0x02, 0x00, {0xA7, 0x04}},
++	{0x39, 0x02, 0x00, {0xA9, 0x58}},
++	{0x39, 0x02, 0x00, {0xB1, 0x17}},
++	{0x39, 0x02, 0x00, {0xB2, 0x17}},
++	{0x39, 0x02, 0x00, {0xB3, 0x00}},
++	{0x39, 0x02, 0x00, {0xB4, 0x03}},
++	{0x39, 0x02, 0x00, {0xB5, 0x04}},
++	{0x39, 0x02, 0x00, {0xB6, 0x17}},
++	{0x39, 0x02, 0x00, {0xB7, 0x17}},
++	{0x39, 0x02, 0x00, {0xB8, 0x17}},
++	{0x39, 0x02, 0x00, {0xB9, 0x17}},
++	{0x39, 0x02, 0x00, {0xBA, 0x17}},
++	{0x39, 0x02, 0x00, {0xBB, 0x17}},
++	{0x39, 0x02, 0x00, {0xBC, 0x17}},
++	{0x39, 0x02, 0x00, {0xBD, 0x17}},
++	{0x39, 0x02, 0x00, {0xBE, 0x17}},
++	{0x39, 0x02, 0x00, {0xBF, 0x17}},
++	{0x39, 0x02, 0x00, {0xC0, 0x17}},
++	{0x39, 0x02, 0x00, {0xC1, 0x08}},
++	{0x39, 0x02, 0x00, {0xC2, 0x09}},
++	{0x39, 0x02, 0x00, {0xC3, 0x11}},
++	{0x39, 0x02, 0x00, {0xC4, 0x06}},
++	{0x39, 0x02, 0x00, {0xC5, 0x05}},
++	{0x39, 0x02, 0x00, {0xC6, 0x00}},
++	{0x39, 0x02, 0x00, {0xC7, 0x17}},
++	{0x39, 0x02, 0x00, {0xC8, 0x17}},
++
++	{0x39, 0x02, 0x00, {0xFE, 0x09}},
++	{0x39, 0x02, 0x00, {0x15, 0x92}},
++	{0x39, 0x02, 0x00, {0x16, 0x24}},
++	{0x39, 0x02, 0x00, {0x17, 0x49}},
++	{0x39, 0x02, 0x00, {0x1B, 0x92}},
++	{0x39, 0x02, 0x00, {0x1C, 0x24}},
++	{0x39, 0x02, 0x00, {0x1D, 0x49}},
++	{0x39, 0x02, 0x00, {0x21, 0x92}},
++	{0x39, 0x02, 0x00, {0x22, 0x24}},
++	{0x39, 0x02, 0x00, {0x23, 0x49}},
++	{0x39, 0x02, 0x00, {0x9B, 0x47}},
++	{0x39, 0x02, 0x00, {0x9C, 0x81}},
++	{0x39, 0x02, 0x00, {0xA3, 0x18}},
++
++	{0x39, 0x02, 0x00, {0xFE, 0x0A}},
++	{0x39, 0x02, 0x00, {0x25, 0x66}},
++	{0x39, 0x02, 0x00, {0xFE, 0x0E}},
++	{0x39, 0x02, 0x00, {0x12, 0x33}},
++
++	{0x39, 0x02, 0x00, {0xFE, 0xD0}}, /* �2 lane 设置】 */
++	{0x39, 0x02, 0x00, {0x1E, 0x05}},
++
++#if 0
++	{0x39, 0x02, 0x00, {0xFE, 0x40}}, /* �scaling up 设置】 */
++	{0x39, 0x02, 0x00, {0x36, 0x55}}, //scal_en */
++	{0x39, 0x02, 0x00, {0x0D, 0x90}}, //2a2b_en */
++	{0x39, 0x02, 0x00, {0x0E, 0x00}},
++
++	{0x39, 0x02, 0x00, {0xFE, 0xD0}},
++	{0x39, 0x02, 0x00, {0x07, 0x84}},
++
++	{0x39, 0x02, 0x00, {0xFE, 0x00}},
++	{0x39, 0x05, 0x00, {0x2A, 0x00, 0x00, 0x02, 0xCF}},
++	{0x39, 0x05, 0x00, {0x2B, 0x00, 0x00, 0x04, 0xFF}},
++#endif
++	/* {0x39, 0x02, 0x00, {0x3A, 0x55}}, */
++};
++
++static struct dsi_cmd_packet visionox_ma0060_1080p_cmd_list2[] =
++{
++	{0x15, 0xFE, 0x00},
++	{0x15, 0xC2, 0x08},
++	{0x15, 0x35, 0x00},
++};
++#endif
++
++
++static void panel_dev_sleep_in(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x10, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_sleep_out(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x11, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_display_on(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x29, 0x00};
++	/* struct dsi_cmd_packet data_to_send1 = {0x15, 0x51, 250}; */
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++	/* ops->cmd_write(lcd_to_master(lcd), data_to_send1); */
++}
++
++static void panel_dev_display_off(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x28, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_panel_init(struct panel_dev *lcd)
++{
++	int  i;
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_device *dsi = lcd_to_master(lcd);
++
++#ifdef _1080P
++	for (i = 0; i < ARRAY_SIZE(visionox_ma0060_1080p_cmd_list1); i++)
++	{
++		ops->cmd_write(dsi,  visionox_ma0060_1080p_cmd_list1[i]);
++	}
++	msleep(20);
++	for (i = 0; i < ARRAY_SIZE(visionox_ma0060_1080p_cmd_list2); i++)
++	{
++		ops->cmd_write(dsi,  visionox_ma0060_1080p_cmd_list2[i]);
++	}
++#else
++	for (i = 0; i < ARRAY_SIZE(visionox_ma0060_720p_cmd_list11); i++)
++	{
++		ops->cmd_write(dsi,  visionox_ma0060_720p_cmd_list11[i]);
++	}
++	msleep(20);
++	for (i = 0; i < ARRAY_SIZE(visionox_ma0060_720p_cmd_list2); i++)
++	{
++		ops->cmd_write(dsi,  visionox_ma0060_720p_cmd_list2[i]);
++	}
++#endif
++
++}
++
++static int panel_dev_ioctl(struct mipi_dsim_lcd_device *dsim_dev, int cmd)
++{
++	return 0;
++}
++static void panel_dev_set_sequence(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct ma0060 *lcd = dev_get_drvdata(&dsim_dev->dev);
++
++	panel_dev_panel_init(panel);
++	msleep(120);
++	panel_dev_sleep_out(panel);
++	msleep(120);
++	panel_dev_display_on(panel);
++	msleep(80);
++	/* dump_dsi_reg(dsi); */
++	lcd->power = FB_BLANK_UNBLANK;
++}
++static void panel_dev_power_on(struct mipi_dsim_lcd_device *dsim_dev, int power)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++	struct board_gpio *oled = &panel->oled;
++	struct board_gpio *swire = &panel->swire;
++
++
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	if (gpio_is_valid(swire->gpio)) {
++		gpio_direction_input(swire->gpio);
++	}
++
++	if (gpio_is_valid(oled->gpio)) {
++		gpio_direction_input(oled->gpio);
++	}
++	msleep(100);
++
++	gpio_direction_output(rst->gpio, 1);
++	msleep(100);
++	gpio_direction_output(rst->gpio, 0);
++	msleep(150);
++	gpio_direction_output(rst->gpio, 1);
++	msleep(100);
++
++	panel->power = power;
++}
++
++static struct fb_videomode panel_modes = {
++	.name = "visionox_ma0060-lcd",
++#ifdef _1080P
++	.refresh = 30,
++	.xres = 1080,
++	.yres = 1920,
++#else
++	.refresh = 60,
++	.xres = 720,
++	.yres = 1280,
++#endif
++	.left_margin = 0,
++	.right_margin = 0,
++	.upper_margin = 0,
++	.lower_margin = 0,
++
++	.hsync_len = 0,
++	.vsync_len = 0,
++	.vmode = FB_VMODE_NONINTERLACED,
++	.flag = 0,
++};
++
++static struct jzdsi_data jzdsi_pdata = {
++	.modes = &panel_modes,
++	.video_config.no_of_lanes = 2,
++	.video_config.virtual_channel = 0,
++	.video_config.color_coding = COLOR_CODE_24BIT,
++	.video_config.video_mode = VIDEO_BURST_WITH_SYNC_PULSES,
++	.video_config.receive_ack_packets = 0,	/* enable receiving of ack packets */
++	.video_config.is_18_loosely = 0,
++	.video_config.data_en_polarity = 1,
++	.video_config.byte_clock = 0, // driver will auto calculate byte_clock.
++	.video_config.byte_clock_coef = MIPI_PHY_BYTE_CLK_COEF_MUL6_DIV5, //for auto calculate byte clock
++
++	.dsi_config.max_lanes = 2,
++	.dsi_config.max_hs_to_lp_cycles = 100,
++	.dsi_config.max_lp_to_hs_cycles = 40,
++	.dsi_config.max_bta_cycles = 4095,
++	.dsi_config.color_mode_polarity = 1,
++	.dsi_config.shut_down_polarity = 1,
++	.dsi_config.max_bps = 2750,
++	.bpp_info = 24,
++};
++
++static struct smart_config smart_cfg = {
++	.dc_md = 0,
++	.wr_md = 1,
++	.smart_type = SMART_LCD_TYPE_8080,
++	.pix_fmt = SMART_LCD_FORMAT_888,
++	.dwidth = SMART_LCD_DWIDTH_24_BIT,
++	.te_mipi_switch = 1,
++	.te_switch = 1,
++};
++
++static struct lcd_panel lcd_panel = {
++	.num_modes = 1,
++	.modes = &panel_modes,
++	.dsi_pdata = &jzdsi_pdata,
++	.smart_config = &smart_cfg,
++
++	.lcd_type = LCD_TYPE_MIPI_SLCD,
++	.bpp = 24,
++	.width = 68,
++	.height = 121,
++};
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++* @ pannel_ma0060_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->vdd_en.gpio, GPIOF_DIR_OUT, "vdd_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++
++	panel->oled.gpio = of_get_named_gpio_flags(np, "ingenic,oled-gpio", 0, &flags);
++	if(gpio_is_valid(panel->oled.gpio)) {
++		panel->oled.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->oled.gpio, GPIOF_DIR_OUT, "oled");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request oled pin!\n");
++			goto err_request_oled;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio oled.gpio: %d\n", panel->oled.gpio);
++	}
++
++	panel->lcd_pwm.gpio = of_get_named_gpio_flags(np, "ingenic,lcd-pwm-gpio", 0, &flags);
++	if(gpio_is_valid(panel->lcd_pwm.gpio)) {
++		panel->lcd_pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->lcd_pwm.gpio, GPIOF_DIR_OUT, "lcd-pwm");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request lcd-pwm pin!\n");
++			goto err_request_pwm;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio lcd-pwm.gpio: %d\n", panel->lcd_pwm.gpio);
++	}
++
++	panel->swire.gpio = of_get_named_gpio_flags(np, "ingenic,swire-gpio", 0, &flags);
++	if(gpio_is_valid(panel->swire.gpio)) {
++		panel->swire.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->swire.gpio, GPIOF_DIR_OUT, "swire");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request swire pin!\n");
++			goto err_request_swire;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio swire.gpio: %d\n", panel->swire.gpio);
++	}
++
++	return 0;
++
++err_request_swire:
++	if(gpio_is_valid(panel->lcd_pwm.gpio))
++		gpio_free(panel->lcd_pwm.gpio);
++err_request_pwm:
++	if(gpio_is_valid(panel->oled.gpio))
++		gpio_free(panel->oled.gpio);
++err_request_oled:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++err_request_rst:
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++	return ret;
++}
++
++static int panel_detect_id(struct mipi_dsim_lcd_device *dsim_dev, unsigned char *buf, int count)
++{
++	struct dsi_master_ops *ops = dsim_dev->master->master_ops;
++	struct dsi_cmd_packet set_max_return_packet_size = {0x37, 0x04, 0x00};	//设置最大回读byte数.
++	struct dsi_cmd_packet data_to_send0 = {0x14, 0x04, 0x00};
++	struct dsi_cmd_packet data_to_send1 = {0x14, 0x04, 0x01};
++	struct dsi_cmd_packet data_to_send2 = {0x14, 0x04, 0x02};
++	int ret = 0;
++	int panel_id = 0;
++
++	/*XXXTODO:*/
++//	return 0;
++
++	panel_dev_power_on(dsim_dev, 1);
++//	ret = ops->cmd_write(master, set_max_return_packet_size);
++	ret = ops->cmd_read(dsim_dev->master, data_to_send0, &buf[0], 1);
++	ret = ops->cmd_read(dsim_dev->master, data_to_send1, &buf[1], 1);
++	ret = ops->cmd_read(dsim_dev->master, data_to_send2, &buf[2], 1);
++	/* ops->cmd_write(lcd_to_master(lcd), data_to_send1); */
++	panel_dev_power_on(dsim_dev, 0);
++
++	panel_id = (buf[0] << 16) + (buf[1] << 8) + buf[2];
++	printk("----------%s, (%d) id[0]: %x id[1]: %x, id[2]: %x, id:%08x\n", __func__, __LINE__, buf[0], buf[1], buf[2], panel_id);
++
++	/*TODO: check ID*/
++	if(panel_id == PANEL_MA0060_ID)
++		return 0;
++	else
++		return -1;
++}
++
++
++static int panel_dev_probe(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct ma0060 *lcd;
++	int ret = 0;
++
++	char buffer[4];
++	ret = panel_detect_id(dsim_dev, buffer, 4);
++	if(ret < 0) {
++		return -EINVAL;
++	}
++
++	lcd = devm_kzalloc(&dsim_dev->dev, sizeof(struct ma0060), GFP_KERNEL);
++	if (!lcd)
++	{
++		dev_err(&dsim_dev->dev, "failed to allocate visionox_ma0060 structure.\n");
++		return -ENOMEM;
++	}
++
++	lcd->dsim_dev = dsim_dev;
++	lcd->dev = &dsim_dev->dev;
++
++	lcd->ld = lcd_device_register("visionox_ma0060", lcd->dev, lcd,
++	                              &panel_lcd_ops);
++	if (IS_ERR(lcd->ld))
++	{
++		dev_err(lcd->dev, "failed to register lcd ops.\n");
++		return PTR_ERR(lcd->ld);
++	}
++
++	dev_set_drvdata(&dsim_dev->dev, lcd);
++
++	dev_dbg(lcd->dev, "probed visionox_ma0060 panel driver.\n");
++
++	panel->dsim_dev = dsim_dev;
++
++
++	return 0;
++}
++
++static int panel_suspend(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	return 0;
++}
++
++static int panel_pm_suspend(struct device *dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++
++	panel_dev_display_off(panel);
++	panel_dev_sleep_in(panel);
++	gpio_direction_output(vdd_en->gpio, !vdd_en->active_level);
++
++	return 0;
++}
++
++static int panel_resume(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	return 0;
++}
++
++static int panel_pm_resume(struct device *dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_pm_suspend,
++	.resume = panel_pm_resume,
++};
++
++static struct mipi_dsim_lcd_driver panel_dev_dsim_ddi_driver = {
++	.name = "visionox_ma0060-lcd",
++	.id = -1,
++
++	.power_on = panel_dev_power_on,
++	.set_sequence = panel_dev_set_sequence,
++	.probe = panel_dev_probe,
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++
++
++static struct mipi_dsim_lcd_device panel_dev_device={
++	.name		= "visionox_ma0060-lcd",
++	.id = 0,
++};
++
++
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	mipi_dsi_register_lcd_device(&panel_dev_device);
++	mipi_dsi_register_lcd_driver(&panel_dev_dsim_ddi_driver);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_of_parse;
++	}
++
++	return 0;
++
++err_of_parse:
++if(gpio_is_valid(panel->lcd_pwm.gpio))
++	gpio_free(panel->lcd_pwm.gpio);
++if(gpio_is_valid(panel->oled.gpio))
++	gpio_free(panel->oled.gpio);
++if(gpio_is_valid(panel->rst.gpio))
++	gpio_free(panel->rst.gpio);
++if(gpio_is_valid(panel->vdd_en.gpio))
++	gpio_free(panel->vdd_en.gpio);
++if(gpio_is_valid(panel->swire.gpio))
++	gpio_free(panel->swire.gpio);
++
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,ma0060", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "ma0060",
++		.of_match_table = panel_of_match,
++		.pm = &panel_pm_ops,
++	},
++};
++
++module_platform_driver(panel_driver);
++
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-st7282.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-st7282.c
+new file mode 100644
+index 000000000..94e7811fd
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-st7282.c
+@@ -0,0 +1,271 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-st7282.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++
++#include "../ingenicfb.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio pwm;
++};
++
++static void panel_enable(struct lcd_panel *panel)
++{
++}
++
++static void panel_disable(struct lcd_panel *panel)
++{
++}
++
++static struct lcd_panel_ops panel_ops = {
++	.enable  = (void*)panel_enable,
++	.disable = (void*)panel_disable,
++};
++
++static struct fb_videomode panel_modes[] = {
++	[0] = {
++		.name                   = "480X272",
++		.refresh                = 65,
++		.xres                   = 480,
++		.yres                   = 272,
++		.pixclock               = KHZ2PICOS(33264),
++		.left_margin            = 48,
++		.right_margin           = 8,
++		.upper_margin           = 6,
++		.lower_margin           = 12,
++
++		.hsync_len              = 8,
++		.vsync_len              = 8,
++		.sync                   = FB_SYNC_HOR_HIGH_ACT & FB_SYNC_VERT_HIGH_ACT,
++		.vmode                  = FB_VMODE_NONINTERLACED,
++		.flag                   = 0,
++	},
++};
++
++static struct tft_config st7282_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++struct lcd_panel lcd_panel = {
++	.name = "st7282",
++	.num_modes = ARRAY_SIZE(panel_modes),
++	.modes = panel_modes,
++	.bpp = 24,
++	.width = 480,
++	.height = 272,
++
++	.lcd_type = LCD_TYPE_TFT,
++
++	.tft_config = &st7282_cfg,
++
++	.dither_enable = 1,
++	.dither.dither_red = 1,
++	.dither.dither_green = 1,
++	.dither.dither_blue = 1,
++
++	.ops = &panel_ops,
++};
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++	struct board_gpio *pwm = &panel->pwm;
++
++	if(POWER_IS_ON(power) && !POWER_IS_ON(panel->power)) {
++		gpio_direction_output(vdd_en->gpio, (vdd_en->active_level));
++	}
++	if(!POWER_IS_ON(power) && POWER_IS_ON(panel->power)) {
++		gpio_direction_output(vdd_en->gpio, 0);
++	}
++
++	panel->power = power;
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++* @ pannel_st7282_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->vdd_en.gpio, GPIOF_DIR_OUT, "vdd_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	return 0;
++err_request_pwm:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++err_request_rst:
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++	return ret;
++}
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	struct panel_dev *panel;
++
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	panel->lcd = lcd_device_register("panel_lcd", &pdev->dev, panel, &panel_lcd_ops);
++	if(IS_ERR_OR_NULL(panel->lcd)) {
++		dev_err(&pdev->dev, "Error register lcd!\n");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++	/* TODO: should this power status sync from uboot */
++	panel->power = FB_BLANK_POWERDOWN;
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++	printk("============panel st7282 probe ok!\n\n");
++	return 0;
++
++err_lcd_register:
++	lcd_device_unregister(panel->lcd);
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	struct panel_dev *panel = dev_get_drvdata(&pdev->dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int panel_suspend(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++static int panel_resume(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++#endif
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,st7282", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "st7282",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-st7701s-rgb666.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-st7701s-rgb666.c
+new file mode 100644
+index 000000000..9dc733a59
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-st7701s-rgb666.c
+@@ -0,0 +1,976 @@
++/*
++ * kernel-4.4.94/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-st7701s-rgb666.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++
++#include "../ingenicfb.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct gpio_spi {
++	short sdo;
++	short sdi;
++	short sck;
++	short cs;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio pwm;
++	struct gpio_spi spi;
++};
++
++static struct panel_dev *panel;
++
++#define RESET(n)\
++     gpio_direction_output(panel->rst.gpio, n)
++
++#define CS(n)\
++     gpio_direction_output(panel->spi.cs, n)
++
++#define SCK(n)\
++     gpio_direction_output(panel->spi.sck, n)
++
++#define SDO(n)\
++	 gpio_direction_output(panel->spi.sdo, n)
++
++#if 0
++#define SDI()\
++	gpio_get_value(panel->spi.sdi)
++#endif
++
++void SPI_SendData(unsigned char i)
++{
++   unsigned char n;
++
++   for(n=0; n<8; n++) {
++	   if(i&0x80)
++		   SDO(1);
++	   else
++		   SDO(0);
++	   i = i << 1;
++
++	   SCK(0);
++	   udelay(10);
++	   SCK(1);
++	   udelay(10);
++   }
++}
++
++void SPI_WriteComm(unsigned char c)
++{
++	CS(0);
++
++	SDO(0);
++
++	SCK(0);
++	udelay(10);
++	SCK(1);
++	udelay(10);
++
++	SPI_SendData(c);
++
++	CS(1);
++}
++
++void SPI_WriteData(unsigned char d)
++{
++	CS(0);
++
++	SDO(1);
++
++	SCK(0);
++	udelay(10);
++	SCK(1);
++	udelay(10);
++
++	SPI_SendData(d);
++
++	CS(1);
++}
++
++void Initial_IC(void)
++{
++	RESET(1);
++	udelay(10000);
++	RESET(0);
++	udelay(10);
++	RESET(1);
++	udelay(120000); // Delay 120ms // This delay time is necessary
++	SPI_WriteComm(0x11);//Attention !!! sleep out config or color display error.
++	/* udelay(120000); // Delay 120ms // This delay time is necessary */
++	//PAGE1
++#if 1
++	SPI_WriteComm(0xFF);
++	SPI_WriteData(0x77);
++	SPI_WriteData(0x01);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x10);
++
++	SPI_WriteComm(0xC0);
++	SPI_WriteData(0x3B);
++	SPI_WriteData(0x00);
++
++	SPI_WriteComm(0xC1);
++	SPI_WriteData(0x0D);
++	SPI_WriteData(0x02);
++
++	SPI_WriteComm(0xC2);
++	SPI_WriteData(0x31);
++	SPI_WriteData(0x05);
++
++	SPI_WriteComm(0xCD);//COLCTRL	(CDh/CD00h):Color Control.MDT=�1�, pixel collect to DB[17:0].
++	SPI_WriteData(0x08);//D3,MDT=�1�, pixel collect to DB[17:0].
++
++	SPI_WriteComm(0xB0);
++	SPI_WriteData(0x00);//Positive Voltage Gamma Control
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x18);
++	SPI_WriteData(0x0E);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x06);
++	SPI_WriteData(0x07);
++	SPI_WriteData(0x08);
++	SPI_WriteData(0x07);
++	SPI_WriteData(0x22);
++	SPI_WriteData(0x04);
++	SPI_WriteData(0x12);
++	SPI_WriteData(0x0F);
++	SPI_WriteData(0xAA);
++	SPI_WriteData(0x31);
++	SPI_WriteData(0x18);
++
++	SPI_WriteComm(0xB1);
++	SPI_WriteData(0x00);// //Negative Voltage Gamma Control
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x19);
++	SPI_WriteData(0x0E);
++	SPI_WriteData(0x12);
++	SPI_WriteData(0x07);
++	SPI_WriteData(0x08);
++	SPI_WriteData(0x08);
++	SPI_WriteData(0x08);
++	SPI_WriteData(0x22);
++	SPI_WriteData(0x04);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0xA9);
++	SPI_WriteData(0x32);
++	SPI_WriteData(0x18);
++//PAGE1
++
++	SPI_WriteComm(0xFF);
++	SPI_WriteData(0x77);
++	SPI_WriteData(0x01);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x11);
++
++	SPI_WriteComm(0xB0);    SPI_WriteData(0x60); //Vop=4.7375v
++
++	SPI_WriteComm(0xB1);    SPI_WriteData(0x32);//VCOM=32
++
++	SPI_WriteComm(0xB2);    SPI_WriteData(0x07); //VGH=15v
++
++	SPI_WriteComm(0xB3);    SPI_WriteData(0x80);
++
++	SPI_WriteComm(0xB5);    SPI_WriteData(0x49);//VGL=-10.17v
++
++	SPI_WriteComm(0xB7);    SPI_WriteData(0x85);
++
++	SPI_WriteComm(0xB8);    SPI_WriteData(0x21);//AVDD=6.6 & AVCL=-4.6
++
++	SPI_WriteComm(0xC1);    SPI_WriteData(0x78);
++
++	SPI_WriteComm(0xC2);    SPI_WriteData(0x78);
++
++	SPI_WriteComm(0xE0);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x1B);
++	SPI_WriteData(0x02);
++
++	SPI_WriteComm(0xE1);
++	SPI_WriteData(0x08);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x07);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x44);
++	SPI_WriteData(0x44);
++
++	SPI_WriteComm(0xE2);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x44);
++	SPI_WriteData(0x44);
++	SPI_WriteData(0xED);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0xEC);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++
++	SPI_WriteComm(0xE3);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x11);
++
++	SPI_WriteComm(0xE4);
++	SPI_WriteData(0x44);
++	SPI_WriteData(0x44);
++
++	SPI_WriteComm(0xE5);
++	SPI_WriteData(0x0A);
++	SPI_WriteData(0xE9);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x0C);
++	SPI_WriteData(0xEB);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x0E);
++	SPI_WriteData(0xED);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x10);
++	SPI_WriteData(0xEF);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++
++	SPI_WriteComm(0xE6);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x11);
++
++	SPI_WriteComm(0xE7);
++	SPI_WriteData(0x44);
++	SPI_WriteData(0x44);
++
++	SPI_WriteComm(0xE8);
++	SPI_WriteData(0x09);
++	SPI_WriteData(0xE8);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x0B);
++	SPI_WriteData(0xEA);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x0D);
++	SPI_WriteData(0xEC);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x0F);
++	SPI_WriteData(0xEE);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++
++	SPI_WriteComm(0xEB);
++	SPI_WriteData(0x02);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0xE4);
++	SPI_WriteData(0xE4);
++	SPI_WriteData(0x88);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x40);
++
++	SPI_WriteComm(0xEC);
++	SPI_WriteData(0x3C);
++	SPI_WriteData(0x00);
++
++	SPI_WriteComm(0xED);
++	SPI_WriteData(0xAB);
++	SPI_WriteData(0x89);
++	SPI_WriteData(0x76);
++	SPI_WriteData(0x54);
++	SPI_WriteData(0x02);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0x20);
++	SPI_WriteData(0x45);
++	SPI_WriteData(0x67);
++	SPI_WriteData(0x98);
++	SPI_WriteData(0xBA);
++
++	SPI_WriteComm(0x36);//MADCTL(36h/3600h): Display data access control
++	SPI_WriteData(0x00);//BGR=0->RGB
++//	SPI_WriteData(0x08);//BGR=1->BGR
++
++ //-----------VAP & VAN---------------
++	SPI_WriteComm(0xFF);
++	SPI_WriteData(0x77);
++	SPI_WriteData(0x01);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x13);
++
++	SPI_WriteComm(0xE5);
++	SPI_WriteData(0xE4);
++
++	SPI_WriteComm(0xFF);
++	SPI_WriteData(0x77);
++	SPI_WriteData(0x01);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++
++	SPI_WriteComm(0x3A);
++	SPI_WriteData(0x66);
++
++	SPI_WriteComm(0x0C);//RDDCOLMOD (0Ch/0C00h): Read Display Pixel Format.
++	SPI_WriteData(0x60);//VIPF[2:0]:“110� = 18-bit / pixel
++
++
++	SPI_WriteComm(0x21);//NVON (21h/2100h): Display Inversion On
++	udelay(1000); // Delay 1ms
++	SPI_WriteComm(0x11);
++	udelay(120000); // Delay 120ms // This delay time is necessary
++	SPI_WriteComm(0x29);
++//	udelay(20000); // Delay 20ms // This delay time is necessary
++#else
++	SPI_WriteComm(0xFF);
++	SPI_WriteData(0x77);
++	SPI_WriteData(0x01);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x13);
++
++	SPI_WriteComm(0xEF);
++	SPI_WriteData(0x08);
++
++	SPI_WriteComm(0xFF);
++	SPI_WriteData(0x77);
++	SPI_WriteData(0x01);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x10);
++
++	SPI_WriteComm(0xC0);
++	SPI_WriteData(0x3B);
++	SPI_WriteData(0x00);
++
++	SPI_WriteComm(0xC1);
++	SPI_WriteData(0x0D);
++	SPI_WriteData(0x02);
++
++	SPI_WriteComm(0xC2);
++	SPI_WriteData(0x21);
++	SPI_WriteData(0x08);
++
++	SPI_WriteComm(0xCD);
++	SPI_WriteData(0x08);
++
++	SPI_WriteComm(0xB0);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x18);
++	SPI_WriteData(0x0E);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x06);
++	SPI_WriteData(0x07);
++	SPI_WriteData(0x08);
++	SPI_WriteData(0x07);
++	SPI_WriteData(0x22);
++	SPI_WriteData(0x04);
++	SPI_WriteData(0x12);
++	SPI_WriteData(0x0F);
++	SPI_WriteData(0xAA);
++	SPI_WriteData(0x31);
++	SPI_WriteData(0x18);
++
++	SPI_WriteComm(0xB1);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x19);
++	SPI_WriteData(0x0E);
++	SPI_WriteData(0x12);
++	SPI_WriteData(0x07);
++	SPI_WriteData(0x08);
++	SPI_WriteData(0x08);
++	SPI_WriteData(0x08);
++	SPI_WriteData(0x22);
++	SPI_WriteData(0x04);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0xA9);
++	SPI_WriteData(0x32);
++	SPI_WriteData(0x18);
++
++	SPI_WriteComm(0xFF);
++	SPI_WriteData(0x77);
++	SPI_WriteData(0x01);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x11);
++
++	SPI_WriteComm(0xB0);    SPI_WriteData(0x60);
++
++	SPI_WriteComm(0xB1);    SPI_WriteData(0x30);
++
++	SPI_WriteComm(0xB2);    SPI_WriteData(0x87);
++
++	SPI_WriteComm(0xB3);    SPI_WriteData(0x80);
++
++	SPI_WriteComm(0xB5);    SPI_WriteData(0x49);
++
++	SPI_WriteComm(0xB7);    SPI_WriteData(0x85);
++
++	SPI_WriteComm(0xB8);    SPI_WriteData(0x21);
++
++	SPI_WriteComm(0xC1);    SPI_WriteData(0x78);
++
++	SPI_WriteComm(0xC2);    SPI_WriteData(0x78);
++
++	udelay(20000); // Delay 20ms
++
++	SPI_WriteComm(0xE0);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x1B);
++	SPI_WriteData(0x02);
++
++	SPI_WriteComm(0xE1);
++	SPI_WriteData(0x08);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x07);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x44);
++	SPI_WriteData(0x44);
++
++	SPI_WriteComm(0xE2);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x44);
++	SPI_WriteData(0x44);
++	SPI_WriteData(0xED);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0xEC);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++
++	SPI_WriteComm(0xE3);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x11);
++
++	SPI_WriteComm(0xE4);
++	SPI_WriteData(0x44);
++	SPI_WriteData(0x44);
++
++	SPI_WriteComm(0xE5);
++	SPI_WriteData(0x0A);
++	SPI_WriteData(0xE9);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x0c);
++	SPI_WriteData(0xEB);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x0E);
++	SPI_WriteData(0xED);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x10);
++	SPI_WriteData(0xEF);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++
++	SPI_WriteComm(0xE6);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x11);
++
++	SPI_WriteComm(0xE7);
++	SPI_WriteData(0x44);
++	SPI_WriteData(0x44);
++
++	SPI_WriteComm(0xE8);
++	SPI_WriteData(0x09);
++	SPI_WriteData(0xE8);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x0B);
++	SPI_WriteData(0xEA);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x0D);
++	SPI_WriteData(0xEC);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x0F);
++	SPI_WriteData(0xEE);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++
++	SPI_WriteComm(0xEB);
++	SPI_WriteData(0x02);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0xE4);
++	SPI_WriteData(0xE4);
++	SPI_WriteData(0x88);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x40);
++
++	SPI_WriteComm(0xEC);
++	SPI_WriteData(0x3C);
++	SPI_WriteData(0x00);
++
++	SPI_WriteComm(0xED);
++	SPI_WriteData(0xAB);
++	SPI_WriteData(0x89);
++	SPI_WriteData(0x76);
++	SPI_WriteData(0x54);
++	SPI_WriteData(0x02);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0x20);
++	SPI_WriteData(0x45);
++	SPI_WriteData(0x67);
++	SPI_WriteData(0x98);
++	SPI_WriteData(0xBA);
++
++	SPI_WriteComm(0xFF);
++	SPI_WriteData(0x77);
++	SPI_WriteData(0x01);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++
++//	SPI_WriteComm(0x21);//NVON (21h/2100h): Display Inversion On
++	udelay(1000); // Delay 1ms
++	SPI_WriteComm(0x11);
++	udelay(120000); // Delay 120ms // This delay time is necessary
++	SPI_WriteComm(0x29);
++	udelay(20000); // Delay 20ms // This delay time is necessary
++#endif
++}
++
++
++static void panel_enable(struct lcd_panel *panel)
++{
++}
++
++static void panel_disable(struct lcd_panel *panel)
++{
++}
++
++static struct lcd_panel_ops panel_ops = {
++	.enable  = (void*)panel_enable,
++	.disable = (void*)panel_disable,
++};
++
++static struct fb_videomode panel_modes[] = {
++	[0] = {
++		.name                   = "480X480",
++		.refresh                = 60,
++		.xres                   = 480,
++		.yres                   = 480,
++		.pixclock               = KHZ2PICOS(14000),
++//		.left_margin            = 160,
++//		.right_margin           = 10,
++//		.upper_margin           = 2,
++//		.lower_margin           = 1,
++		.left_margin            = 20,
++		.right_margin           = 20,
++		.upper_margin           = 16,
++		.lower_margin           = 16,
++
++
++//		.hsync_len              = 16,
++//		.vsync_len              = 13,
++		.hsync_len              = 20,
++		.vsync_len              = 4,
++		/* .sync                   = ~FB_SYNC_HOR_HIGH_ACT & ~FB_SYNC_VERT_HIGH_ACT, */
++		.vmode                  = FB_VMODE_NONINTERLACED,
++		.flag                   = 0,
++	},
++};
++
++static struct tft_config st7701ds_spirgb_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++//	.color_even = TFT_LCD_COLOR_EVEN_RBG,
++//	.color_odd = TFT_LCD_COLOR_ODD_RBG,
++	.mode = TFT_LCD_MODE_PARALLEL_666,
++};
++
++struct lcd_panel lcd_panel = {
++	.name = "st7701ds_spirgb",
++	.num_modes = ARRAY_SIZE(panel_modes),
++	.modes = panel_modes,
++	.bpp = 32,
++	.width = 72,
++	.height = 70,
++
++	.lcd_type = LCD_TYPE_TFT,
++
++	.tft_config = &st7701ds_spirgb_cfg,
++#if 0
++	.dither_enable = 1,
++	.dither.dither_red = 1,
++	.dither.dither_green = 1,
++	.dither.dither_blue = 1,
++#else
++	.dither_enable = 0,
++	.dither.dither_red = 0,
++	.dither.dither_green = 0,
++	.dither.dither_blue = 0,
++#endif
++	.ops = &panel_ops,
++};
++
++#if 0
++static int panel_update_status(struct backlight_device *bd)
++{
++	struct panel_dev *panel = dev_get_drvdata(&bd->dev);
++	int brightness = bd->props.brightness;
++	unsigned int i;
++	int pulse_num = MAX_BRIGHTNESS_STEP - brightness / CONVERT_FACTOR - 1;
++
++	if (bd->props.fb_blank == FB_BLANK_POWERDOWN) {
++		return 0;
++	}
++
++	if (bd->props.state & BL_CORE_SUSPENDED)
++		brightness = 0;
++
++	if (brightness) {
++		gpio_direction_output(panel->pwm.gpio,0);
++		udelay(5000);
++		gpio_direction_output(panel->pwm.gpio,1);
++		udelay(100);
++
++		for (i = pulse_num; i > 0; i--) {
++			gpio_direction_output(panel->pwm.gpio,0);
++			udelay(1);
++			gpio_direction_output(panel->pwm.gpio,1);
++			udelay(3);
++		}
++	} else
++		gpio_direction_output(panel->pwm.gpio, 0);
++
++	return 0;
++}
++
++static struct backlight_ops panel_backlight_ops = {
++	.options = BL_CORE_SUSPENDRESUME,
++	.update_status = panel_update_status,
++};
++#endif
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++
++	if(POWER_IS_ON(power) && !POWER_IS_ON(panel->power)) {
++		/* *(unsigned int*)(0xb00101a4) = 0xf000000; */
++		/* *(unsigned int*)(0xb00101b4) = 0xf000000; */
++		/* *(unsigned int*)(0xb00101c4) = 0xf000000; */
++		gpio_direction_output(vdd_en->gpio, 0);
++		gpio_direction_output(rst->gpio, 1);
++//		printk("==============vdd_en=%d,rst=%d,func=%s,line=%d\n",vdd_en->gpio,rst->gpio,__func__,__LINE__);
++		Initial_IC();
++	}
++	if(!POWER_IS_ON(power) && POWER_IS_ON(panel->power)) {
++		gpio_direction_output(vdd_en->gpio, 1);
++//		printk("==============vdd_en=%d,rst=%d,func=%s,line=%d\n",vdd_en->gpio,rst->gpio,__func__,__LINE__);
++	}
++
++	panel->power = power;
++//		printk("==============power=%d,func=%s,line=%d\n",panel->power,__func__,__LINE__);
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++* @ pannel_st7701ds_spirgb_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->vdd_en.gpio, GPIOF_DIR_OUT, "vdd_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++#if 0
++	panel->pwm.gpio = of_get_named_gpio_flags(np, "ingenic,lcd-pwm-gpio", 0, &flags);
++	if(gpio_is_valid(panel->pwm.gpio)) {
++		panel->pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->pwm.gpio, GPIOF_DIR_OUT, "pwm");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request pwm pin!\n");
++			goto err_request_pwm;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio pwm.gpio: %d\n", panel->pwm.gpio);
++	}
++#endif
++
++	panel->spi.sdo = of_get_named_gpio_flags(np, "ingenic,lcd-sdo-gpio", 0, &flags);
++	if(gpio_is_valid(panel->spi.sdo)) {
++		ret = gpio_request_one(panel->spi.sdo, GPIOF_DIR_OUT, "sdo");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request sdo pin!\n");
++			goto err_request_sdo;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio spi.sdo: %d\n", panel->spi.sdo);
++	}
++
++	panel->spi.sck = of_get_named_gpio_flags(np, "ingenic,lcd-sck-gpio", 0, &flags);
++	if(gpio_is_valid(panel->spi.sck)) {
++		ret = gpio_request_one(panel->spi.sck, GPIOF_DIR_OUT, "sck");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request sck pin!\n");
++			goto err_request_sck;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio spi.sck: %d\n", panel->spi.sck);
++	}
++
++	panel->spi.cs = of_get_named_gpio_flags(np, "ingenic,lcd-cs-gpio", 0, &flags);
++	if(gpio_is_valid(panel->spi.cs)) {
++		ret = gpio_request_one(panel->spi.cs, GPIOF_DIR_OUT, "cs");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request cs pin!\n");
++			goto err_request_cs;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio spi.cs: %d\n", panel->spi.cs);
++	}
++
++	return 0;
++err_request_cs:
++	if(gpio_is_valid(panel->spi.cs))
++		gpio_free(panel->spi.cs);
++err_request_sck:
++	if(gpio_is_valid(panel->spi.sck))
++		gpio_free(panel->spi.sck);
++err_request_sdo:
++	if(gpio_is_valid(panel->spi.sdo))
++		gpio_free(panel->spi.sdo);
++err_request_pwm:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++err_request_rst:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++	return ret;
++}
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	/* struct panel_dev *panel; */
++	struct backlight_properties props;
++
++	memset(&props, 0, sizeof(props));
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Failed to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	panel->lcd = lcd_device_register("panel_lcd", &pdev->dev, panel, &panel_lcd_ops);
++	if(IS_ERR_OR_NULL(panel->lcd)) {
++		dev_err(&pdev->dev, "Error register lcd!\n");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++	/* TODO: should this power status sync from uboot */
++	panel->power = FB_BLANK_POWERDOWN;
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++
++#if 0
++	props.type = BACKLIGHT_RAW;
++	props.max_brightness = 255;
++	panel->backlight = backlight_device_register("pwm-backlight.0",
++						&pdev->dev, panel,
++						&panel_backlight_ops,
++						&props);
++	if (IS_ERR_OR_NULL(panel->backlight)) {
++		dev_err(panel->dev, "failed to register 'pwm-backlight.0'.\n");
++		goto err_lcd_register;
++	}
++	panel->backlight->props.brightness = props.max_brightness;
++	backlight_update_status(panel->backlight);
++#endif
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++
++	return 0;
++
++err_lcd_register:
++	lcd_device_unregister(panel->lcd);
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	struct panel_dev *panel = dev_get_drvdata(&pdev->dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int panel_suspend(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++static int panel_resume(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++#endif
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,st7701ds_spirgb", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "st7701ds_spirgb",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-st7701s.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-st7701s.c
+new file mode 100644
+index 000000000..fde63ec85
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-st7701s.c
+@@ -0,0 +1,580 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-st7701s.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++#include <linux/fb.h>
++#include <linux/backlight.h>
++
++
++#include "../ingenicfb.h"
++#include "../jz_dsim.h"
++
++static int test = 0;
++static int power_flag;
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio lcd_te;
++	struct board_gpio lcd_pwm;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++};
++
++static struct panel_dev *panel;
++
++#define lcd_to_master(a)	(a->dsim_dev->master)
++#define lcd_to_master_ops(a)	((lcd_to_master(a))->master_ops)
++
++struct st7701s {
++	struct device *dev;
++	unsigned int power;
++	unsigned int id;
++
++	struct lcd_device *ld;
++	struct backlight_device *bd;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++
++};
++
++static struct dsi_cmd_packet fitipower_st7701s_480_800_cmd_list1[] =
++{
++
++/**st7701s***/
++	{0x39, 0x06, 0x00, {0xFF, 0x77, 0x01, 0x00, 0x00, 0x13}},
++	{0x15, 0xEF, 0x08},
++	{0x39, 0x06, 0x00, {0xFF, 0x77, 0x01, 0x00, 0x00, 0x10}},
++	{0x39, 0x03, 0x00, {0xC0, 0x63, 0x00}},
++	{0x39, 0x03, 0x00, {0xC1, 0x11, 0x0C}},
++	{0x39, 0x03, 0x00, {0xC2, 0x07, 0x08}},
++	{0x15, 0xCC, 0x10},
++	{0x39, 0x11, 0x00, {0xB0, 0x00, 0x08, 0x0E, 0x0C, 0x10, 0x06, 0x01,0x07,0x07, 0x1E, 0x05, 0x13, 0x10, 0x2C, 0x34, 0x1E}},
++	{0x39, 0x11, 0x00, {0xB1, 0x00, 0x0F, 0x16, 0x0D, 0x10, 0x05, 0x01,0x08,0x07, 0x1E, 0x04, 0x12, 0x11, 0x28, 0x30, 0x1E}},
++	{0x39, 0x06, 0x00, {0xFF, 0x77, 0x01, 0x00, 0x00, 0x11}},
++	{0x15, 0xB0, 0x72},
++	{0x15, 0xB1, 0x8E},
++	{0x15, 0xB2, 0x87},
++	{0x15, 0xB3, 0x80},
++	{0x15, 0xB5, 0x4C},
++	{0x15, 0xB7, 0x85},
++	{0x15, 0xB8, 0x20},
++	{0x15, 0xC1, 0x78},
++	{0x15, 0xC2, 0x78},
++	{0x15, 0xD0, 0x88},
++	{0x39, 0x07, 0x00, {0xE0, 0x00, 0x00, 0x02, 0x00, 0x00, 0x0C}},
++	{0x39, 0x0C, 0x00, {0xE1, 0x06, 0x8C, 0x08, 0x8C, 0x07, 0x8C, 0x09, 0x8C, 0x00, 0x44, 0x44}},
++	{0x39, 0x0D, 0x00, {0xE2, 0x00, 0x00, 0x04, 0x04, 0x00, 0x00, 0x03, 0xA0, 0x00, 0x00, 0x03, 0xA0}},
++	{0x39, 0x05, 0x00, {0xE3, 0x00, 0x00, 0x33, 0x33}},
++	{0x39, 0x03, 0x00, {0xE4, 0x44, 0x44}},
++	{0x39, 0x11, 0x00, {0xE5, 0x0D, 0x31, 0x0C, 0xA0, 0x0F, 0x33, 0x0C, 0xA0, 0x09, 0x2D, 0x0C, 0xA0, 0x0B, 0x2F, 0x0C, 0xA0}},
++	{0x39, 0x05, 0x00, {0xE6, 0x00, 0x00, 0x33, 0x33}},
++	{0x39, 0x03, 0x00, {0xE7, 0x44, 0x44}},
++	{0x39, 0x11, 0x00, {0xE8, 0x0E, 0x32, 0x0C, 0xA0, 0x10, 0x34, 0x0C, 0xA0, 0x0A, 0x2E, 0x0C, 0xA0, 0x0C, 0x30, 0x0C, 0xA0}},
++	{0x39, 0x07, 0x00, {0xEB, 0x00, 0x01, 0xE4, 0xE4, 0x44, 0x00}},
++	{0x39, 0x11, 0x00, {0xED, 0xF3, 0xC1, 0xAB, 0x0F, 0x67, 0x45, 0xFF, 0xFF, 0xFF, 0xFF, 0x54, 0x76, 0xF0, 0xBA, 0x1C, 0x3F}},
++	{0x39, 0x07, 0x00, {0xEF, 0x10, 0x0D, 0x04, 0x08, 0x3F, 0x1F}},
++	{0x39, 0x06, 0x00, {0xFF, 0x77, 0x01, 0x00, 0x00, 0x13}},
++	{0x39, 0x03, 0x00, {0xE8, 0x00, 0x0E}},
++	/**/
++	{0x05, 0x11, 0x00},//delay 120ms
++	 /***/
++//	{0x39, 0x03, 0x00, {0xE8, 0x00, 0x0C}},//delay 20ms
++//	{0x39, 0x03, 0x00, {0xE8, 0x00, 0x00}},
++//	{0x39, 0x06, 0x00, {0xFF, 0x77, 0x01, 0x00, 0x00,0x00}},
++//	{0x39, 0x03, 0x00, {0x29, 0x36, 0x00}},
++/**st7701s***/
++
++};
++
++static struct dsi_cmd_packet fitipower_st7701s_480_800_cmd_list2[] =
++{
++	{0x39, 0x03, 0x00, {0xE8, 0x00, 0x0C}},//delay 20ms
++};
++
++static struct dsi_cmd_packet fitipower_st7701s_480_800_cmd_list3[] =
++{
++	{0x39, 0x03, 0x00, {0xE8, 0x00, 0x00}},
++	{0x39, 0x06, 0x00, {0xFF, 0x77, 0x01, 0x00, 0x00,0x00}},
++	{0x39, 0x03, 0x00, {0x29, 0x36, 0x00}},
++};
++
++
++static void panel_dev_sleep_in(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x10, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_sleep_out(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x11, 0x00};
++//	struct dsi_cmd_packet data_to_send1 = {0x15, 0xc2, 0x20};//color bar test mode.
++//	while (1) {
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++//	ops->cmd_write(lcd_to_master(lcd), data_to_send1);
++//	}
++}
++
++static void panel_dev_display_on(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);//color bar turn off 0x29 command.
++	struct dsi_cmd_packet data_to_send = {0x05, 0x29, 0x00};
++	/* struct dsi_cmd_packet data_to_send1 = {0x15, 0x51, 250}; */
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++	/* ops->cmd_write(lcd_to_master(lcd), data_to_send1); */
++}
++
++static void panel_dev_display_off(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x28, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++
++static void panel_dev_panel_init(struct panel_dev *lcd)
++{
++	int  i;
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_device *dsi = lcd_to_master(lcd);
++
++	for (i = 0; i < ARRAY_SIZE(fitipower_st7701s_480_800_cmd_list1); i++)
++	{
++		ops->cmd_write(dsi,  fitipower_st7701s_480_800_cmd_list1[i]);
++	}
++	msleep(120);
++	for (i = 0; i < ARRAY_SIZE(fitipower_st7701s_480_800_cmd_list2); i++)
++	{
++		ops->cmd_write(dsi,  fitipower_st7701s_480_800_cmd_list2[i]);
++	}
++	msleep(20);
++	for (i = 0; i < ARRAY_SIZE(fitipower_st7701s_480_800_cmd_list3); i++)
++	{
++		ops->cmd_write(dsi,  fitipower_st7701s_480_800_cmd_list3[i]);
++	}
++}
++
++static int panel_dev_ioctl(struct mipi_dsim_lcd_device *dsim_dev, int cmd)
++{
++	return 0;
++}
++static void panel_dev_set_sequence(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct st7701s *lcd = dev_get_drvdata(&dsim_dev->dev);
++
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++
++	panel_dev_panel_init(panel);
++	panel_dev_sleep_out(panel);
++	msleep(120);
++	panel_dev_display_on(panel);
++	msleep(5);
++	/* dump_dsi_reg(dsi); */
++	lcd->power = FB_BLANK_UNBLANK;
++}
++static void panel_dev_power_on(struct mipi_dsim_lcd_device *dsim_dev, int power)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++	struct board_gpio *lcd_te = &panel->lcd_te;
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	if (gpio_is_valid(lcd_te->gpio)) {
++		gpio_direction_input(lcd_te->gpio);
++	}
++	if(power){
++		msleep(50);
++		gpio_direction_output(rst->gpio, 0);
++		msleep(50);
++		gpio_direction_output(rst->gpio, 1);
++		msleep(120);
++	}
++
++	panel->power = power;
++}
++
++static struct fb_videomode panel_modes = {
++	.name = "fitipower_st7701s-lcd",
++	.xres = 480,
++	.yres = 800,
++//	.xres = 268,
++//	.yres = 800,
++
++//	.refresh = 10,
++	.refresh = 60,
++
++	.left_margin = 20,//hbp
++	.right_margin = 20,//hfp
++	.hsync_len = 20, //hsync
++
++//	.upper_margin = 16,//vbp
++	.upper_margin = 18,//vbp
++	.lower_margin = 16,//vfp
++	.vsync_len = 4, //vsync
++
++	.sync                   = FB_SYNC_HOR_HIGH_ACT & FB_SYNC_VERT_HIGH_ACT,
++	.vmode                  = FB_VMODE_NONINTERLACED,
++	.flag = 0,
++};
++
++static struct jzdsi_data jzdsi_pdata = {
++	.modes = &panel_modes,
++	.video_config.no_of_lanes = 2,
++	.video_config.virtual_channel = 0,
++	.video_config.color_coding = COLOR_CODE_24BIT,
++	.video_config.video_mode = VIDEO_BURST_WITH_SYNC_PULSES,
++	.video_config.receive_ack_packets = 0,	/* enable receiving of ack packets */
++	.video_config.is_18_loosely = 0,
++	.video_config.data_en_polarity = 1,
++	.video_config.byte_clock = 0, // driver will auto calculate byte_clock.
++	.video_config.byte_clock_coef = MIPI_PHY_BYTE_CLK_COEF_MUL3_DIV2, // byte_clock *3/2.
++
++	.dsi_config.max_lanes = 2,
++	.dsi_config.max_hs_to_lp_cycles = 100,
++	.dsi_config.max_lp_to_hs_cycles = 40,
++//	.dsi_config.max_hs_to_lp_cycles = 200,
++//	.dsi_config.max_lp_to_hs_cycles = 80,
++	.dsi_config.max_bta_cycles = 4095,
++	.dsi_config.color_mode_polarity = 1,
++	.dsi_config.shut_down_polarity = 1,
++	.dsi_config.max_bps = 2750,
++//	.max_bps = 650,  // 650 Mbps
++	.bpp_info = 24,
++};
++static struct tft_config kd050hdfia019_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++
++static struct lcd_panel lcd_panel = {
++	.num_modes = 1,
++	.modes = &panel_modes,
++	.dsi_pdata = &jzdsi_pdata,
++
++	.lcd_type = LCD_TYPE_MIPI_TFT,
++	.tft_config = &kd050hdfia019_cfg,
++	.bpp = 24,
++//	.width = 700,
++//	.height = 1230,
++	.width = 68,
++	.height = 121,
++	.dither_enable = 0,
++	.dither.dither_red = 0,
++	.dither.dither_green = 0,
++	.dither.dither_blue = 0,
++
++
++};
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++* @ pannel_st7701s_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++
++	*(volatile  unsigned int * )0xb0010188 = (0x1 << 27); //lcd_te high impedance config.
++	*(volatile  unsigned int * )0xb0010198 = (0x1 << 27);
++
++	panel->lcd_te.gpio = of_get_named_gpio_flags(np, "ingenic,lcd-te-gpio", 0, &flags);
++	if(gpio_is_valid(panel->lcd_te.gpio)) {
++		panel->lcd_te.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++
++	} else {
++		dev_warn(dev, "invalid gpio lcd_te.gpio: %d\n", panel->lcd_te.gpio);
++	}
++/**lcd_bl_pwm pin as normal io pin config pull up***/
++//	panel->lcd_pwm.gpio = of_get_named_gpio_flags(np, "ingenic,lcd-pwm-gpio", 0, &flags);
++//	if(gpio_is_valid(panel->lcd_pwm.gpio)) {
++//		panel->lcd_pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++//		ret = gpio_direction_output(panel->lcd_pwm.gpio,1);
++//		if(ret < 0) {
++//			dev_err(dev, "Failed to request lcd-pwm pin!\n");
++//			return ret;
++//		}
++//	} else {
++//		dev_warn(dev, "invalid gpio lcd-pwm.gpio: %d\n", panel->lcd_pwm.gpio);
++//	}
++//
++
++	return 0;
++err_request_lcd_te:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++err_request_rst:
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++	return ret;
++}
++
++#define ST7701SID       0xFFFF0288
++static int panel_detect_id(struct mipi_dsim_lcd_device *dsim_dev, unsigned char *buf, int count)
++{
++	int ret = 0;
++	unsigned int *id = NULL;
++
++	struct dsi_master_ops *ops = dsim_dev->master->master_ops;
++	struct dsi_cmd_packet set_max_return_packet_size = {0x37, 0x04, 0x00};	//设置最大回读byte数.
++	struct dsi_cmd_packet data_to_send0 = {0x14, 0xa1, 0x00};
++	struct dsi_cmd_packet data_to_send1 = {0x14, 0xa1, 0x01};
++	struct dsi_cmd_packet data_to_send2 = {0x14, 0xa1, 0x02};
++
++	if(!power_flag){
++		panel_dev_power_on(dsim_dev, 1);
++		power_flag = 1;
++	}
++	ret = ops->cmd_write(dsim_dev->master, set_max_return_packet_size);
++	ret = ops->cmd_read(dsim_dev->master, data_to_send0, &buf[0], 4);
++
++	id=(unsigned int *)buf;
++	if(*id == ST7701SID)
++		return 0;
++
++	return -1;
++}
++
++static int panel_dev_probe(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct st7701s *lcd;
++	int ret = 0;
++	char buffer[4];
++	ret = panel_detect_id(dsim_dev, buffer, 4);
++	if(ret < 0) {
++		return -EINVAL;
++	}
++
++	lcd = devm_kzalloc(&dsim_dev->dev, sizeof(struct st7701s), GFP_KERNEL);
++	if (!lcd)
++	{
++		dev_err(&dsim_dev->dev, "failed to allocate fitipower_st7701s structure.\n");
++		return -ENOMEM;
++	}
++
++	lcd->dsim_dev = dsim_dev;
++	lcd->dev = &dsim_dev->dev;
++
++	lcd->ld = lcd_device_register("fitipower_st7701s", lcd->dev, lcd,
++	                              &panel_lcd_ops);
++	if (IS_ERR(lcd->ld))
++	{
++		dev_err(lcd->dev, "failed to register lcd ops.\n");
++		return PTR_ERR(lcd->ld);
++	}
++
++	dev_set_drvdata(&dsim_dev->dev, lcd);
++
++
++	dev_dbg(lcd->dev, "probed fitipower_st7701s panel driver.\n");
++
++
++	panel->dsim_dev = dsim_dev;
++
++
++	return 0;
++
++}
++
++static int panel_suspend(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	return 0;
++}
++
++static int panel_resume(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int panel_pm_suspend(struct device *dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++	panel_dev_display_off(panel);
++	panel_dev_sleep_in(panel);
++	gpio_direction_output(vdd_en->gpio, !vdd_en->active_level);
++
++	return 0;
++}
++
++static int panel_pm_resume(struct device *dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	return 0;
++}
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_pm_suspend,
++	.resume = panel_pm_resume,
++};
++#endif
++
++static struct mipi_dsim_lcd_driver panel_dev_dsim_ddi_driver = {
++	.name = "fitipower_st7701s-lcd",
++	.id = -1,
++
++	.power_on = panel_dev_power_on,
++	.set_sequence = panel_dev_set_sequence,
++	.probe = panel_dev_probe,
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++
++
++static struct mipi_dsim_lcd_device panel_dev_device={
++	.name		= "fitipower_st7701s-lcd",
++	.id = 0,
++};
++
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	mipi_dsi_register_lcd_device(&panel_dev_device);
++	mipi_dsi_register_lcd_driver(&panel_dev_dsim_ddi_driver);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_of_parse;
++	}
++
++	return 0;
++
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,st7701s", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "st7701s",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-tl040hds01ct.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-tl040hds01ct.c
+new file mode 100644
+index 000000000..4c63b8d3f
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-tl040hds01ct.c
+@@ -0,0 +1,373 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-tl040hds01ct.c
++ *
++ * Copyright (C) 2020 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++
++#include "../ingenicfb.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio pwm;
++};
++
++static struct panel_dev *panel;
++
++#define RESET(n)\
++     gpio_direction_output(panel->rst.gpio, n)
++
++static void panel_enable(struct lcd_panel *panel)
++{
++}
++
++static void panel_disable(struct lcd_panel *panel)
++{
++}
++
++static struct lcd_panel_ops panel_ops = {
++	.enable  = (void*)panel_enable,
++	.disable = (void*)panel_disable,
++};
++
++static struct fb_videomode panel_modes[] = {
++	[0] = {
++		.name                   = "720x720",
++		.refresh                = 60,
++		.xres                   = 720,
++		.yres                   = 720,
++		/* .pixclock               = KHZ2PICOS(35000), */
++		.left_margin            = 10,
++		.right_margin           = 20,
++		.upper_margin           = 10,
++		.lower_margin           = 10,
++
++		.hsync_len              = 20,
++		.vsync_len              = 10,
++		.sync                   = ~FB_SYNC_HOR_HIGH_ACT & ~FB_SYNC_VERT_HIGH_ACT,
++		.vmode                  = FB_VMODE_NONINTERLACED,
++		.flag                   = 0,
++	},
++};
++
++static struct tft_config tl040hds01ct_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_666,
++};
++
++struct lcd_panel lcd_panel = {
++	.name = "tl040hds01ct",
++	.num_modes = ARRAY_SIZE(panel_modes),
++	.modes = panel_modes,
++	.bpp = 24,
++	.width = 72,
++	.height = 72,
++
++	.lcd_type = LCD_TYPE_TFT,
++
++	.tft_config = &tl040hds01ct_cfg,
++
++	.dither_enable = 1,
++	.dither.dither_red = 1,
++	.dither.dither_green = 1,
++	.dither.dither_blue = 1,
++
++	.ops = &panel_ops,
++};
++
++#if 0
++static int panel_update_status(struct backlight_device *bd)
++{
++	struct panel_dev *panel = dev_get_drvdata(&bd->dev);
++	int brightness = bd->props.brightness;
++	unsigned int i;
++	int pulse_num = MAX_BRIGHTNESS_STEP - brightness / CONVERT_FACTOR - 1;
++
++	if (bd->props.fb_blank == FB_BLANK_POWERDOWN) {
++		return 0;
++	}
++
++	if (bd->props.state & BL_CORE_SUSPENDED)
++		brightness = 0;
++
++	if (brightness) {
++		gpio_direction_output(panel->pwm.gpio,0);
++		udelay(5000);
++		gpio_direction_output(panel->pwm.gpio,1);
++		udelay(100);
++
++		for (i = pulse_num; i > 0; i--) {
++			gpio_direction_output(panel->pwm.gpio,0);
++			udelay(1);
++			gpio_direction_output(panel->pwm.gpio,1);
++			udelay(3);
++		}
++	} else
++		gpio_direction_output(panel->pwm.gpio, 0);
++
++	return 0;
++}
++
++static struct backlight_ops panel_backlight_ops = {
++	.options = BL_CORE_SUSPENDRESUME,
++	.update_status = panel_update_status,
++};
++#endif
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++
++	if(POWER_IS_ON(power) && !POWER_IS_ON(panel->power)) {
++		/* *(unsigned int*)(0xb00101a4) = 0xf000000; */
++		/* *(unsigned int*)(0xb00101b8) = 0xf000000; */
++		/* *(unsigned int*)(0xb00101c4) = 0xf000000; */
++
++		gpio_direction_output(vdd_en->gpio, 0);
++
++		RESET(1);
++		udelay(50000);
++		RESET(0);
++		udelay(120000);
++		RESET(1);
++		udelay(20000);
++
++	}
++	if(!POWER_IS_ON(power) && POWER_IS_ON(panel->power)) {
++		gpio_direction_output(vdd_en->gpio, 1);
++	}
++
++	panel->power = power;
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++* @ pannel_tl040hds01ct_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->vdd_en.gpio, GPIOF_DIR_OUT, "vdd_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++
++#if 0
++	panel->pwm.gpio = of_get_named_gpio_flags(np, "ingenic,lcd-pwm-gpio", 0, &flags);
++	if(gpio_is_valid(panel->pwm.gpio)) {
++		panel->pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->pwm.gpio, GPIOF_DIR_OUT, "pwm");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request pwm pin!\n");
++			goto err_request_pwm;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio pwm.gpio: %d\n", panel->pwm.gpio);
++	}
++#endif
++
++	return 0;
++err_request_sdo:
++	if(gpio_is_valid(panel->pwm.gpio))
++		gpio_free(panel->pwm.gpio);
++err_request_pwm:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++err_request_rst:
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++	return ret;
++}
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	/* struct panel_dev *panel; */
++	struct backlight_properties props;
++
++	memset(&props, 0, sizeof(props));
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Failed to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	panel->lcd = lcd_device_register("panel_lcd", &pdev->dev, panel, &panel_lcd_ops);
++	if(IS_ERR_OR_NULL(panel->lcd)) {
++		dev_err(&pdev->dev, "Error register lcd!\n");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++	/* TODO: should this power status sync from uboot */
++	panel->power = FB_BLANK_POWERDOWN;
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++
++#if 0
++	props.type = BACKLIGHT_RAW;
++	props.max_brightness = 255;
++	panel->backlight = backlight_device_register("pwm-backlight.0",
++						&pdev->dev, panel,
++						&panel_backlight_ops,
++						&props);
++	if (IS_ERR_OR_NULL(panel->backlight)) {
++		dev_err(panel->dev, "failed to register 'pwm-backlight.0'.\n");
++		goto err_lcd_register;
++	}
++	panel->backlight->props.brightness = props.max_brightness;
++	backlight_update_status(panel->backlight);
++#endif
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++
++	return 0;
++
++err_lcd_register:
++	lcd_device_unregister(panel->lcd);
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	struct panel_dev *panel = dev_get_drvdata(&pdev->dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int panel_suspend(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++static int panel_resume(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++#endif
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,tl040hds01ct", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "tl040hds01ct",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-tl040wvs03ct.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-tl040wvs03ct.c
+new file mode 100644
+index 000000000..9261fb917
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-tl040wvs03ct.c
+@@ -0,0 +1,736 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-88249.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++
++#include "../ingenicfb.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct gpio_spi {
++	short sdo;
++	short sdi;
++	short sck;
++	short cs;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio pwm;
++	struct gpio_spi spi;
++};
++
++static struct panel_dev *panel;
++
++#define RESET(n)\
++     gpio_direction_output(panel->rst.gpio, n)
++
++#define CS(n)\
++     gpio_direction_output(panel->spi.cs, n)
++
++#define SCK(n)\
++     gpio_direction_output(panel->spi.sck, n)
++
++#define SDO(n)\
++	 gpio_direction_output(panel->spi.sdo, n)
++
++#if 0
++#define SDI()\
++	gpio_get_value(panel->spi.sdi)
++#endif
++
++void SPI_SendData(unsigned char i)
++{
++   unsigned char n;
++
++   for(n=0; n<8; n++) {
++	   if(i&0x80)
++		   SDO(1);
++	   else
++		   SDO(0);
++	   i = i << 1;
++
++	   SCK(0);
++	   udelay(10);
++	   SCK(1);
++	   udelay(10);
++   }
++}
++
++void SPI_WriteComm(unsigned char c)
++{
++	CS(0);
++
++	SDO(0);
++
++	SCK(0);
++	udelay(10);
++	SCK(1);
++	udelay(10);
++
++	SPI_SendData(c);
++
++	CS(1);
++}
++
++void SPI_WriteData(unsigned char d)
++{
++	CS(0);
++
++	SDO(1);
++
++	SCK(0);
++	udelay(10);
++	SCK(1);
++	udelay(10);
++
++	SPI_SendData(d);
++
++	CS(1);
++}
++
++void Initial_IC(void)
++{
++	RESET(1);
++	udelay(10000);
++	RESET(0);
++	udelay(10);
++	RESET(1);
++	udelay(120000); // Delay 120ms // This delay time is necessary
++	SPI_WriteComm(0x11);
++	/* udelay(120000); // Delay 120ms // This delay time is necessary */
++	//PAGE1
++	SPI_WriteComm(0xFF);
++	SPI_WriteData(0x77);
++	SPI_WriteData(0x01);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x10);
++
++	SPI_WriteComm(0xC0);
++	SPI_WriteData(0x3B);
++	SPI_WriteData(0x00);
++
++	SPI_WriteComm(0xC1);
++	SPI_WriteData(0x0D);
++	SPI_WriteData(0x02);
++
++	SPI_WriteComm(0xC2);
++	SPI_WriteData(0x31);
++	SPI_WriteData(0x05);
++
++	SPI_WriteComm(0xCd);
++	SPI_WriteData(0x08);
++
++	SPI_WriteComm(0xB0);
++	SPI_WriteData(0x00); //Positive Voltage Gamma Control
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x18);
++	SPI_WriteData(0x0E);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x06);
++	SPI_WriteData(0x07);
++	SPI_WriteData(0x08);
++	SPI_WriteData(0x07);
++	SPI_WriteData(0x22);
++	SPI_WriteData(0x04);
++	SPI_WriteData(0x12);
++	SPI_WriteData(0x0F);
++	SPI_WriteData(0xAA);
++	SPI_WriteData(0x31);
++	SPI_WriteData(0x18);
++
++
++	SPI_WriteComm(0xB1);
++	SPI_WriteData(0x00); //Negative Voltage Gamma Control
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x19);
++	SPI_WriteData(0x0E);
++	SPI_WriteData(0x12);
++	SPI_WriteData(0x07);
++	SPI_WriteData(0x08);
++	SPI_WriteData(0x08);
++	SPI_WriteData(0x08);
++	SPI_WriteData(0x22);
++	SPI_WriteData(0x04);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0xA9);
++	SPI_WriteData(0x32);
++	SPI_WriteData(0x18);
++
++	//PAGE1
++	SPI_WriteComm(0xFF);
++	SPI_WriteData(0x77);
++	SPI_WriteData(0x01);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x11);
++
++
++	SPI_WriteComm(0xB0);    SPI_WriteData(0x60); //Vop=4.7375v
++
++	SPI_WriteComm(0xB1);    SPI_WriteData(0x32); //VCOM=32
++
++	SPI_WriteComm(0xB2);    SPI_WriteData(0x07); //VGH=15v
++
++	SPI_WriteComm(0xB3);    SPI_WriteData(0x80);
++
++	SPI_WriteComm(0xB5);    SPI_WriteData(0x49); //VGL=-10.17v
++
++	SPI_WriteComm(0xB7);    SPI_WriteData(0x85);
++
++	SPI_WriteComm(0xB8);    SPI_WriteData(0x21); //AVDD=6.6 & AVCL=-4.6
++
++	SPI_WriteComm(0xC1);    SPI_WriteData(0x78);
++
++	SPI_WriteComm(0xC2);    SPI_WriteData(0x78);
++
++	SPI_WriteComm(0xE0);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x1B);
++	SPI_WriteData(0x02);
++
++	SPI_WriteComm(0xE1);
++	SPI_WriteData(0x08);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x07);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x44);
++	SPI_WriteData(0x44);
++
++
++
++	SPI_WriteComm(0xE2);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x44);
++	SPI_WriteData(0x44);
++	SPI_WriteData(0xED);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0xEC);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++
++
++	SPI_WriteComm(0xE3);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x11);
++
++
++	SPI_WriteComm(0xE4);
++	SPI_WriteData(0x44);
++	SPI_WriteData(0x44);
++
++	SPI_WriteComm(0xE5);
++	SPI_WriteData(0x0A);
++	SPI_WriteData(0xE9);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x0C);
++	SPI_WriteData(0xEB);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x0E);
++	SPI_WriteData(0xED);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x10);
++	SPI_WriteData(0xEF);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++
++
++
++
++	SPI_WriteComm(0xE6);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x11);
++	SPI_WriteData(0x11);
++
++	SPI_WriteComm(0xE7);
++	SPI_WriteData(0x44);
++	SPI_WriteData(0x44);
++
++
++	SPI_WriteComm(0xE8);
++	SPI_WriteData(0x09);
++	SPI_WriteData(0xE8);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x0B);
++	SPI_WriteData(0xEA);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x0D);
++	SPI_WriteData(0xEC);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++	SPI_WriteData(0x0F);
++	SPI_WriteData(0xEE);
++	SPI_WriteData(0xD8);
++	SPI_WriteData(0xA0);
++
++
++	SPI_WriteComm(0xEB);
++	SPI_WriteData(0x02);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0xE4);
++	SPI_WriteData(0xE4);
++	SPI_WriteData(0x88);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x40);
++
++
++	SPI_WriteComm(0xEC);
++	SPI_WriteData(0x3C);
++	SPI_WriteData(0x00);
++
++
++	SPI_WriteComm(0xED);
++	SPI_WriteData(0xAB);
++	SPI_WriteData(0x89);
++	SPI_WriteData(0x76);
++	SPI_WriteData(0x54);
++	SPI_WriteData(0x02);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0xFF);
++	SPI_WriteData(0x20);
++	SPI_WriteData(0x45);
++	SPI_WriteData(0x67);
++	SPI_WriteData(0x98);
++	SPI_WriteData(0xBA);
++
++	SPI_WriteComm(0x36);
++	SPI_WriteData(0x00);
++
++
++	//-----------VAP & VAN---------------
++	SPI_WriteComm(0xFF);
++	SPI_WriteData(0x77);
++	SPI_WriteData(0x01);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x13);
++
++	SPI_WriteComm(0xE5);
++	SPI_WriteData(0xE4);
++
++	SPI_WriteComm(0xFF);
++	SPI_WriteData(0x77);
++	SPI_WriteData(0x01);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++	SPI_WriteData(0x00);
++
++	SPI_WriteComm(0x3a);
++	SPI_WriteData(0x66);
++	SPI_WriteComm(0x21);
++	udelay(1000); // Delay 1ms
++	SPI_WriteComm(0x11);
++	udelay(120000); // Delay 120ms // This delay time is necessary
++	SPI_WriteComm(0x29);
++}
++
++
++static void panel_enable(struct lcd_panel *panel)
++{
++}
++
++static void panel_disable(struct lcd_panel *panel)
++{
++}
++
++static struct lcd_panel_ops panel_ops = {
++	.enable  = (void*)panel_enable,
++	.disable = (void*)panel_disable,
++};
++
++static struct fb_videomode panel_modes[] = {
++	[0] = {
++		.name                   = "480X480",
++		.refresh                = 60,
++		.xres                   = 480,
++		.yres                   = 480,
++		.pixclock               = KHZ2PICOS(14000),
++		.left_margin            = 160,
++		.right_margin           = 10,
++		.upper_margin           = 2,
++		.lower_margin           = 1,
++
++		.hsync_len              = 16,
++		.vsync_len              = 13,
++		/* .sync                   = ~FB_SYNC_HOR_HIGH_ACT & ~FB_SYNC_VERT_HIGH_ACT, */
++		.vmode                  = FB_VMODE_NONINTERLACED,
++		.flag                   = 0,
++	},
++};
++
++static struct tft_config tl040wvs03ct_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_666,
++};
++
++struct lcd_panel lcd_panel = {
++	.name = "tl040wvs03ct",
++	.num_modes = ARRAY_SIZE(panel_modes),
++	.modes = panel_modes,
++	.bpp = 32,
++	.width = 71,
++	.height = 70,
++
++	.lcd_type = LCD_TYPE_TFT,
++
++	.tft_config = &tl040wvs03ct_cfg,
++
++	.dither_enable = 1,
++	.dither.dither_red = 1,
++	.dither.dither_green = 1,
++	.dither.dither_blue = 1,
++
++	.ops = &panel_ops,
++};
++
++#if 0
++static int panel_update_status(struct backlight_device *bd)
++{
++	struct panel_dev *panel = dev_get_drvdata(&bd->dev);
++	int brightness = bd->props.brightness;
++	unsigned int i;
++	int pulse_num = MAX_BRIGHTNESS_STEP - brightness / CONVERT_FACTOR - 1;
++
++	if (bd->props.fb_blank == FB_BLANK_POWERDOWN) {
++		return 0;
++	}
++
++	if (bd->props.state & BL_CORE_SUSPENDED)
++		brightness = 0;
++
++	if (brightness) {
++		gpio_direction_output(panel->pwm.gpio,0);
++		udelay(5000);
++		gpio_direction_output(panel->pwm.gpio,1);
++		udelay(100);
++
++		for (i = pulse_num; i > 0; i--) {
++			gpio_direction_output(panel->pwm.gpio,0);
++			udelay(1);
++			gpio_direction_output(panel->pwm.gpio,1);
++			udelay(3);
++		}
++	} else
++		gpio_direction_output(panel->pwm.gpio, 0);
++
++	return 0;
++}
++
++static struct backlight_ops panel_backlight_ops = {
++	.options = BL_CORE_SUSPENDRESUME,
++	.update_status = panel_update_status,
++};
++#endif
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++
++	if(POWER_IS_ON(power) && !POWER_IS_ON(panel->power)) {
++		/* *(unsigned int*)(0xb00101a4) = 0xf000000; */
++		/* *(unsigned int*)(0xb00101b4) = 0xf000000; */
++		/* *(unsigned int*)(0xb00101c4) = 0xf000000; */
++		gpio_direction_output(vdd_en->gpio, 0);
++		gpio_direction_output(rst->gpio, 1);
++
++		Initial_IC();
++	}
++	if(!POWER_IS_ON(power) && POWER_IS_ON(panel->power)) {
++		gpio_direction_output(vdd_en->gpio, 1);
++	}
++
++	panel->power = power;
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++* @ pannel_tl040wvs03ct_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->vdd_en.gpio, GPIOF_DIR_OUT, "vdd_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++#if 0
++	panel->pwm.gpio = of_get_named_gpio_flags(np, "ingenic,lcd-pwm-gpio", 0, &flags);
++	if(gpio_is_valid(panel->pwm.gpio)) {
++		panel->pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->pwm.gpio, GPIOF_DIR_OUT, "pwm");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request pwm pin!\n");
++			goto err_request_pwm;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio pwm.gpio: %d\n", panel->pwm.gpio);
++	}
++#endif
++
++	panel->spi.sdo = of_get_named_gpio_flags(np, "ingenic,lcd-sdo-gpio", 0, &flags);
++	if(gpio_is_valid(panel->spi.sdo)) {
++		ret = gpio_request_one(panel->spi.sdo, GPIOF_DIR_OUT, "sdo");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request sdo pin!\n");
++			goto err_request_sdo;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio spi.sdo: %d\n", panel->spi.sdo);
++	}
++
++	panel->spi.sck = of_get_named_gpio_flags(np, "ingenic,lcd-sck-gpio", 0, &flags);
++	if(gpio_is_valid(panel->spi.sck)) {
++		ret = gpio_request_one(panel->spi.sck, GPIOF_DIR_OUT, "sck");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request sck pin!\n");
++			goto err_request_sck;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio spi.sck: %d\n", panel->spi.sck);
++	}
++
++	panel->spi.cs = of_get_named_gpio_flags(np, "ingenic,lcd-cs-gpio", 0, &flags);
++	if(gpio_is_valid(panel->spi.cs)) {
++		ret = gpio_request_one(panel->spi.cs, GPIOF_DIR_OUT, "cs");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request cs pin!\n");
++			goto err_request_cs;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio spi.cs: %d\n", panel->spi.cs);
++	}
++
++	return 0;
++err_request_cs:
++	if(gpio_is_valid(panel->spi.sck))
++		gpio_free(panel->spi.sck);
++err_request_sck:
++	if(gpio_is_valid(panel->spi.sdo))
++		gpio_free(panel->spi.sdo);
++err_request_sdo:
++	if(gpio_is_valid(panel->pwm.gpio))
++		gpio_free(panel->pwm.gpio);
++err_request_pwm:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++err_request_rst:
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++	return ret;
++}
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	/* struct panel_dev *panel; */
++	struct backlight_properties props;
++
++	memset(&props, 0, sizeof(props));
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Failed to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	panel->lcd = lcd_device_register("panel_lcd", &pdev->dev, panel, &panel_lcd_ops);
++	if(IS_ERR_OR_NULL(panel->lcd)) {
++		dev_err(&pdev->dev, "Error register lcd!\n");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++	/* TODO: should this power status sync from uboot */
++	panel->power = FB_BLANK_POWERDOWN;
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++
++#if 0
++	props.type = BACKLIGHT_RAW;
++	props.max_brightness = 255;
++	panel->backlight = backlight_device_register("pwm-backlight.0",
++						&pdev->dev, panel,
++						&panel_backlight_ops,
++						&props);
++	if (IS_ERR_OR_NULL(panel->backlight)) {
++		dev_err(panel->dev, "failed to register 'pwm-backlight.0'.\n");
++		goto err_lcd_register;
++	}
++	panel->backlight->props.brightness = props.max_brightness;
++	backlight_update_status(panel->backlight);
++#endif
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++
++	return 0;
++
++err_lcd_register:
++	lcd_device_unregister(panel->lcd);
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	struct panel_dev *panel = dev_get_drvdata(&pdev->dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int panel_suspend(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++static int panel_resume(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++#endif
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,tl040wvs03ct", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "tl040wvs03ct",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-y88249.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-y88249.c
+new file mode 100644
+index 000000000..b7ce10b3a
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-y88249.c
+@@ -0,0 +1,297 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-y88249.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++
++#include "../ingenicfb.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio pwm;
++};
++
++static void panel_enable(struct lcd_panel *panel)
++{
++}
++
++static void panel_disable(struct lcd_panel *panel)
++{
++}
++
++static struct lcd_panel_ops panel_ops = {
++	.enable  = (void*)panel_enable,
++	.disable = (void*)panel_disable,
++};
++
++static struct fb_videomode panel_modes[] = {
++	[0] = {
++		.name                   = "640X480",
++		.refresh                = 65,
++		.xres                   = 640,
++		.yres                   = 480,
++		.pixclock               = KHZ2PICOS(33264),
++		.left_margin            = 20,
++		.right_margin           = 20,
++		.upper_margin           = 6,
++		.lower_margin           = 12,
++
++		.hsync_len              = 2,
++		.vsync_len              = 2,
++		.sync                   = ~FB_SYNC_HOR_HIGH_ACT & ~FB_SYNC_VERT_HIGH_ACT,
++		.vmode                  = FB_VMODE_NONINTERLACED,
++		.flag                   = 0,
++	},
++};
++
++static struct tft_config y88249_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++struct lcd_panel lcd_panel = {
++	.name = "y88249",
++	.num_modes = ARRAY_SIZE(panel_modes),
++	.modes = panel_modes,
++	.bpp = 24,
++	.width = 640,
++	.height = 480,
++
++	.lcd_type = LCD_TYPE_TFT,
++
++	.tft_config = &y88249_cfg,
++
++	.dither_enable = 1,
++	.dither.dither_red = 1,
++	.dither.dither_green = 1,
++	.dither.dither_blue = 1,
++
++	.ops = &panel_ops,
++};
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++	struct board_gpio *pwm = &panel->pwm;
++
++	if(POWER_IS_ON(power) && !POWER_IS_ON(panel->power)) {
++		gpio_direction_output(vdd_en->gpio, 1);
++		gpio_direction_output(rst->gpio, 1);
++		gpio_direction_output(pwm->gpio, 1);
++	}
++	if(!POWER_IS_ON(power) && POWER_IS_ON(panel->power)) {
++		gpio_direction_output(vdd_en->gpio, 0);
++	}
++
++	panel->power = power;
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++* @ pannel_y88249_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->vdd_en.gpio = of_get_named_gpio_flags(np, "ingenic,vdd-en-gpio", 0, &flags);
++	if(gpio_is_valid(panel->vdd_en.gpio)) {
++		panel->vdd_en.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->vdd_en.gpio, GPIOF_DIR_OUT, "vdd_en");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request vdd_en pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio vdd_en.gpio: %d\n", panel->vdd_en.gpio);
++	}
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++	panel->pwm.gpio = of_get_named_gpio_flags(np, "ingenic,pwm-gpio", 0, &flags);
++	if(gpio_is_valid(panel->pwm.gpio)) {
++		panel->pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->pwm.gpio, GPIOF_DIR_OUT, "pwm");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request pwm pin!\n");
++			goto err_request_pwm;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio pwm.gpio: %d\n", panel->pwm.gpio);
++	}
++
++	return 0;
++err_request_pwm:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++err_request_rst:
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++	return ret;
++}
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	struct panel_dev *panel;
++
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	panel->lcd = lcd_device_register("panel_lcd", &pdev->dev, panel, &panel_lcd_ops);
++	if(IS_ERR_OR_NULL(panel->lcd)) {
++		dev_err(&pdev->dev, "Error register lcd!\n");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++	/* TODO: should this power status sync from uboot */
++	panel->power = FB_BLANK_POWERDOWN;
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++
++	return 0;
++
++err_lcd_register:
++	lcd_device_unregister(panel->lcd);
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	struct panel_dev *panel = dev_get_drvdata(&pdev->dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int panel_suspend(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++static int panel_resume(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++
++	panel_set_power(panel->lcd, FB_BLANK_UNBLANK);
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++#endif
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,y88249", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "y88249",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-ylym286a.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-ylym286a.c
+new file mode 100644
+index 000000000..8f5c2d2f5
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-ylym286a.c
+@@ -0,0 +1,490 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-ylym286a.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++
++#include "../ingenicfb.h"
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct i2c_client *client;
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	int power;
++
++	int i2c_id;
++	struct board_gpio reset;
++	struct board_gpio lcd_en;
++	struct board_gpio bl_en;
++	char *panel_name;
++};
++
++#define FPS    60
++#define HACT   1920
++#if 1
++
++#define VACT   540
++
++#define HFP    200
++#define HBP    200
++#else
++#define VACT   1080
++
++#define HFP    88
++#define HBP    148
++
++#endif
++#define HS     44
++
++#define VFP    4
++#define VBP    36
++#define VS     5
++
++#include "lt9211.c"
++
++static struct panel_dev *lt9211_info;
++
++static void panel_enable(struct lcd_panel *panel)
++{
++}
++
++static void panel_disable(struct lcd_panel *panel)
++{
++}
++
++static struct lcd_panel_ops panel_ops = {
++	.enable  = (void*)panel_enable,
++	.disable = (void*)panel_disable,
++};
++
++static struct fb_videomode panel_modes = {
++	.name                   = "lt9211-ylym286a",
++	.refresh                = FPS,
++	.xres                   = HACT,
++	.yres                   = VACT,
++	.left_margin            = HFP,
++	.right_margin           = HBP,
++	.upper_margin           = VFP,
++	.lower_margin           = VBP,
++
++	.hsync_len              = HS,
++	.vsync_len              = VS,
++	.sync                   = FB_SYNC_HOR_HIGH_ACT & FB_SYNC_VERT_HIGH_ACT,
++	.vmode                  = FB_VMODE_NONINTERLACED,
++	.flag                   = 0,
++};
++
++struct jzdsi_data jzdsi_pdata = {
++	.modes = &panel_modes,
++	.video_config.no_of_lanes = 2,
++	.video_config.virtual_channel = 0,
++	.video_config.color_coding = COLOR_CODE_24BIT,
++	.video_config.video_mode = VIDEO_BURST_WITH_SYNC_PULSES,
++	.video_config.receive_ack_packets = 0,	/* enable receiving of ack packets */
++	.video_config.is_18_loosely = 0,
++	.video_config.data_en_polarity = 1,
++	.video_config.byte_clock = 0, // driver will auto calculate byte_clock.
++	.video_config.byte_clock_coef = MIPI_PHY_BYTE_CLK_COEF_MUL1,
++
++	.dsi_config.max_lanes = 2,
++	.dsi_config.max_hs_to_lp_cycles = 100,
++	.dsi_config.max_lp_to_hs_cycles = 40,
++	.dsi_config.max_bta_cycles = 4095,
++	.dsi_config.color_mode_polarity = 1,
++	.dsi_config.shut_down_polarity = 1,
++	.dsi_config.max_bps = 2750,
++	.bpp_info = 24,
++};
++
++static struct tft_config kd050hdfia019_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++struct lcd_panel lcd_panel[] = {
++	[0] = {
++		.name = "ylym286a",
++		.modes = &panel_modes,
++		.num_modes = 1,
++		.dsi_pdata = &jzdsi_pdata,
++
++		.bpp = 24,
++		.width = 699,
++		.height = 197,
++
++		.lcd_type = LCD_TYPE_MIPI_TFT,
++
++		.tft_config = &kd050hdfia019_cfg,
++		.dsi_pdata = &jzdsi_pdata,
++
++		.dither_enable = 0,
++		.dither.dither_red = 0,
++		.dither.dither_green = 0,
++		.dither.dither_blue = 0,
++
++		.ops = &panel_ops,
++	},
++};
++
++static unsigned char i2c_read(struct i2c_client *client, unsigned char addr)
++{
++	return i2c_smbus_read_byte_data(client, addr);
++}
++
++static unsigned int i2c_write(struct i2c_client *client,unsigned char addr,unsigned char value)
++{
++	return i2c_smbus_write_byte_data(client, addr, value);
++}
++
++void lt9211_reset(struct panel_dev *lt9211_info)
++{
++	struct board_gpio *rst = &lt9211_info->reset;
++
++	gpio_direction_output(rst->gpio, 1);
++	mdelay(1);
++	gpio_direction_output(rst->gpio, 0);
++	mdelay(100);
++	gpio_direction_output(rst->gpio, 1);
++	mdelay(100);
++}
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++	struct panel_dev *lt9211_info = lcd_get_data(lcd);
++	struct i2c_client *client = lt9211_info->client;
++
++	struct board_gpio *lcd_en = &lt9211_info->lcd_en;
++	struct board_gpio *bl_en = &lt9211_info->bl_en;
++	struct board_gpio *rst = &lt9211_info->reset;
++
++	if(POWER_IS_ON(power) && !POWER_IS_ON(lt9211_info->power)) {
++		gpio_direction_output(rst->gpio, 0);
++		gpio_direction_output(lcd_en->gpio, 1);
++		mdelay(15);
++
++		lt9211_reset(lt9211_info);
++		if (LT9211_MIPI2LVDS_Config(client))
++			return -1;
++
++	    gpio_direction_output(bl_en->gpio, 1);
++	}
++	if(!POWER_IS_ON(power) && POWER_IS_ON(lt9211_info->power)) {
++		gpio_direction_output(bl_en->gpio, 0);
++		gpio_direction_output(lcd_en->gpio, 0);
++	}
++
++	lt9211_info->power = power;
++	return 0;
++}
++
++int panel_bridge_init(void)
++{
++	int ret = 0;
++	struct i2c_client *client = lt9211_info->client;
++
++	ret = LT9211_MIPI2LVDS_Config(client);
++
++	return ret;
++}
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *lt9211_info = lcd_get_data(lcd);
++
++	return lt9211_info->power;
++}
++
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++
++int _of_get_named_gpio_lvl(struct device *dev, short *gpio, short *lvl, char *of_name)
++{
++	int ret = 0;
++	enum of_gpio_flags flags;
++
++	/* devm_gpio_request_one */
++	*gpio = of_get_named_gpio_flags(dev->of_node, of_name, 0, &flags);
++	if(gpio_is_valid(*gpio)) {
++		*lvl = (flags == OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(*gpio, GPIOF_DIR_OUT, of_name);
++		if(ret < 0) {
++			dev_err(dev, "Failed to request reset pin!\n");
++			return ret;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio: %s\n", of_name);
++		return -1;
++	}
++	return 0;
++}
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *lt9211_info = dev_get_drvdata(dev);
++	int ret = 0;
++
++
++	if ((ret = _of_get_named_gpio_lvl(dev,
++				&lt9211_info->reset.gpio,
++				&lt9211_info->reset.active_level,
++				"lt9211,reset-gpio")))
++		return ret;
++
++	if ((ret = _of_get_named_gpio_lvl(dev,
++				&lt9211_info->lcd_en.gpio,
++				&lt9211_info->lcd_en.active_level,
++				"lt9211,lcd_en-gpio")))
++		goto err_request_reset;
++
++	if ((ret = _of_get_named_gpio_lvl(dev,
++				&lt9211_info->bl_en.gpio,
++				&lt9211_info->bl_en.active_level,
++				"lt9211,bl_en-gpio")))
++		goto err_request_reset;
++
++	/* devm_ */
++
++	return 0;
++err_request_reset:
++	if(gpio_is_valid(lt9211_info->reset.gpio))
++		gpio_free(lt9211_info->reset.gpio);
++	return ret;
++}
++#if 0
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int panel_suspend(struct device *dev)
++{
++	struct panel_dev *lt9211_info = dev_get_drvdata(dev);
++
++	panel_set_power(lt9211_info->lcd, FB_BLANK_POWERDOWN);
++	return 0;
++}
++
++static int panel_resume(struct device *dev)
++{
++	struct panel_dev *lt9211_info = dev_get_drvdata(dev);
++
++	panel_set_power(lt9211_info->lcd, FB_BLANK_UNBLANK);
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++#endif
++
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,ylym286a", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "ylym286a",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++#endif
++
++static struct mipi_dsim_lcd_driver panel_dev_dsim_ddi_driver = {
++	.name = "lt9211-ylym286a",
++	.id = -1,
++
++	/* .power_on = panel_dev_power_on, */
++	/* .set_sequence = panel_dev_set_sequence, */
++	/* .probe = panel_dev_probe, */
++	/* .suspend = panel_suspend, */
++	/* .resume = panel_resume, */
++};
++
++
++struct mipi_dsim_lcd_device panel_dev_device={
++	.name		= "lt9211-ylym286a",
++	.id = 0,
++};
++
++static int lt9211_probe(struct i2c_client *client, const struct i2c_device_id *id)
++{
++	int ret = 0, i;
++	struct device *dev = &client->dev;
++	struct device_node *np = dev->of_node;
++
++	lt9211_info = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(lt9211_info == NULL) {
++		dev_err(dev, "Failed to alloc memory!");
++		return -ENOMEM;
++	}
++	lt9211_info->dev = dev;
++	lt9211_info->client = client;
++	dev_set_drvdata(dev, lt9211_info);
++
++	// set dev_info.
++	ret = of_panel_parse(dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	// register lcd device.
++	lt9211_info->lcd = lcd_device_register("panel_lcd", dev, lt9211_info, &panel_lcd_ops);
++	if(IS_ERR_OR_NULL(lt9211_info->lcd)) {
++		dev_err(dev, "Error register lcd!\n");
++		ret = -EINVAL;
++		goto err_of_parse;
++	}
++
++	of_property_read_string(np, "lt9211,panel_name", (const char**)&lt9211_info->panel_name);
++
++	if (lt9211_info->panel_name) {
++		for (i = 0; i < ARRAY_SIZE(lcd_panel); ++i) {
++			if (strcmp(lcd_panel[i].name, lt9211_info->panel_name) == 0)
++				break;
++		}
++		if (i == ARRAY_SIZE(lcd_panel)) {
++			printk("\033[31munsupport panel!\033[0m\n");
++			goto err_lcd_register;
++		}
++	} else {
++		printk("\033[31mno found specid lcd panel!\033[0m\n");
++		goto err_lcd_register;
++	}
++
++	mipi_dsi_register_lcd_device(&panel_dev_device);
++	mipi_dsi_register_lcd_driver(&panel_dev_dsim_ddi_driver);
++
++	ret = ingenicfb_register_panel(&lcd_panel[i]);
++	if(ret < 0) {
++		dev_err(dev, "Failed to register lcd panel!\n");
++		goto err_lcd_register;
++	}
++
++	// register ingenicfb device.
++	/* TODO: should this power status sync from uboot */
++	lt9211_info->power = FB_BLANK_POWERDOWN;
++	if (panel_set_power(lt9211_info->lcd, FB_BLANK_UNBLANK))
++		goto err_lcd_register;
++
++	printk("\033[32mregister %s sucess.\033[0m\n", lt9211_info->panel_name);
++
++	return 0;
++
++err_lcd_register:
++	lcd_device_unregister(lt9211_info->lcd);
++err_of_parse:
++	kfree(lt9211_info);
++	printk("\033[31mregister %s dailed.\033[0m\n", lt9211_info->panel_name);
++	return ret;
++}
++
++static int lt9211_remove(struct i2c_client *client)
++{
++	struct panel_dev *lt9211_info = dev_get_drvdata(&client->dev);
++
++	panel_set_power(lt9211_info->lcd, FB_BLANK_POWERDOWN);
++
++	return 0;
++}
++
++#ifdef CONFIG_OF
++static const struct of_device_id lt9211_match_table[] = {
++		{.compatible = "mipi2lvds,lt9211",},
++		{ },
++};
++MODULE_DEVICE_TABLE(of, lt9211_match_table);
++#endif
++
++static const struct i2c_device_id lt9211_id[] = {
++	{ "lt9211", },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, lt9211_id);
++
++static struct i2c_driver lt9211_driver = {
++    .probe      = lt9211_probe,
++    .remove     = lt9211_remove,
++    .driver = {
++        .name     = "lt9211",
++        .owner    = THIS_MODULE,
++#ifdef CONFIG_OF
++		.of_match_table = of_match_ptr(lt9211_match_table),
++#endif
++    },
++	.id_table = lt9211_id,
++};
++
++static int __init lt9211_init(void)
++{
++	int ret;
++	printk("\033[33m%s\033[0m\n", "lt9211 driver installing...");
++	ret = i2c_add_driver(&lt9211_driver);
++    if ( ret != 0 ) {
++        printk("lt9211 driver init failed!\n");
++    }
++
++    return ret;
++}
++
++static void __exit lt9211_exit(void)
++{
++	printk("lt9211 driver exited.\n");
++	i2c_del_driver(&lt9211_driver);
++}
++
++/* module_i2c_driver(lt9211_driver); */
++module_init(lt9211_init);
++module_exit(lt9211_exit);
++
++MODULE_DESCRIPTION("LT9211 Driver");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-yts500xlai.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-yts500xlai.c
+new file mode 100644
+index 000000000..b8c4fe998
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/panel-yts500xlai.c
+@@ -0,0 +1,494 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-yts500xlai.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++#include <linux/fb.h>
++#include <linux/backlight.h>
++
++
++#include "../ingenicfb.h"
++#include "../jz_dsim.h"
++#include "../jz_mipi_dsi/jz_mipi_dsih_hal.h"
++#include "../jz_mipi_dsi/jz_mipi_dsi_regs.h"
++
++extern void dump_dsi_reg(struct dsi_device *dsi);
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio lcd_te;
++	struct board_gpio lcd_pwm;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++};
++
++struct panel_dev *panel;
++
++#define lcd_to_master(a)	(a->dsim_dev->master)
++#define lcd_to_master_ops(a)	((lcd_to_master(a))->master_ops)
++
++struct yts500xlai {
++	struct device *dev;
++	unsigned int power;
++	unsigned int id;
++
++	struct lcd_device *ld;
++	struct backlight_device *bd;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++
++};
++
++static struct dsi_cmd_packet fitipower_yts500xlai_480_800_cmd_list1[] =
++{
++
++/**yts500xlai***/
++	{0x39, 0x04, 0x00, {0xB9, 0xFF, 0x83, 0x89}}, //set extc.
++	{0x39, 0x04, 0x00, {0xB9, 0xFF, 0x83, 0x94}}, //pdf->p21.
++	{0x39, 0x0B, 0x00, {0xB1, 0x48, 0x12, 0x72, 0x09, 0x33, 0x54, 0x51, 0x51, 0x30, 0x43}}, //set power.
++//	{0x39, 0x07, 0x00, {0xBA, 0x63, 0x03, 0x68, 0x6B, 0xB2, 0xC0}}, //set mipi 4lane.
++	{0x39, 0x07, 0x00, {0xBA, 0x61, 0x03, 0x68, 0x6B, 0xB2, 0xC0}}, //set mipi 2lane.
++	{0x39, 0x07, 0x00, {0xB2, 0x00, 0x80, 0x64, 0x0C, 0x06, 0x2F}}, //set display.
++//	test color
++//	{0x39, 0x0C, 0x00, {0xB2, 0x00, 0x80, 0x64, 0x0C, 0x06, 0x2F, 0x00, 0x00, 0x00, 0x00, 0xC8}}, //set display to color test.
++//	test color
++	{0x39, 0x1F, 0x00, {0xB4, 0x76, 0x74, 0x76, 0x74, 0x76, 0x74, 0x01, 0x05, 0x84, 0x35, 0x00, 0x3f, 0x76, 0x74, 0x76, 0x74, 0x76, 0x74, 0x01, 0x05, 0x84, 0x3F, 0x00, 0xFF, 0x81, 0x81, 0x81, 0x81, 0x08, 0x01}}, //set cyc.
++	{0x39, 0x22, 0x00, {0xD3, 0x00, 0x00, 0x0F, 0x0F, 0x00, 0x00, 0x12, 0x10, 0x32, 0x10, 0x00, 0x00, 0x00, 0x32, 0x13, 0xC0, 0x00, 0x00, 0x32, 0x10, 0x08, 0x00, 0x00, 0x47, 0x04, 0x02, 0x02, 0x47, 0x04, 0x00, 0x47, 0x0C, 0x40}}, //set w_d(0xD3).
++	{0x39, 0x2D, 0x00, {0xD5, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x20, 0x21, 0x22, 0x23, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,  0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 0x18, 0x18}}, //set GIP.
++	{0x39, 0x2D, 0x00, {0xD6, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x23, 0x22, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,  0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x19, 0x19}}, //set.
++	{0x39, 0x03, 0x00, {0xB6, 0x34, 0x34}}, //set VCOM.
++	{0x39, 0x3B, 0x00, {0xE0, 0x00, 0x06, 0x13, 0x18, 0x1C, 0x20, 0x23, 0x22, 0x48, 0x58, 0x6A, 0x6B, 0x74, 0x88, 0x8E, 0x94, 0xA2, 0xA6, 0xA3, 0xB2, 0xC5, 0x63, 0x61, 0x66, 0x6C, 0x6C, 0x73, 0x7F, 0x7F, 0x00, 0x06, 0x13, 0x18, 0x1C, 0x20, 0x23, 0x22, 0x48, 0x58, 0x6A, 0x6B, 0x75, 0x89, 0x8F, 0x95, 0xA3, 0xA6, 0xA3, 0xB3, 0xC5, 0x63, 0x62, 0x67, 0x6C, 0x71, 0x78, 0x7F, 0x7F}}, //set GAMMA.
++	{0x15, 0xCC, 0x03}, //set pannal.
++	{0x39, 0x03, 0x00, {0xC0, 0x1F, 0x31}}, //set.
++	{0x15, 0xD4, 0x02}, //set.
++	{0x15, 0xBD, 0x01}, //set.
++	{0x15, 0xB1, 0x60}, //set GAS.
++	{0x15, 0xBD, 0x00}, //set .
++	{0x39, 0x08, 0x00, {0xBF, 0x40, 0x81, 0x50, 0x00, 0x1A, 0xFC, 0x01}}, //set power option HX5186 Mode.
++	{0x15, 0x36, 0x02}, // .
++/**yts500xlai***/
++};
++
++
++static void panel_dev_sleep_in(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x10, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_sleep_out(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x11, 0x00};
++//	struct dsi_cmd_packet data_to_send = {0x15, 0x11, 0x00};
++//	while (1) {
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++//	}
++}
++
++static void panel_dev_display_on(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);//color bar turn off 0x29 command.
++	struct dsi_cmd_packet data_to_send = {0x05, 0x29, 0x00};
++//	struct dsi_cmd_packet data_to_send = {0x15, 0x29, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_display_off(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x28, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++
++static void panel_dev_panel_init(struct panel_dev *lcd)
++{
++	int  i;
++	unsigned int value;
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_device *dsi = lcd_to_master(lcd);
++
++	for (i = 0; i < ARRAY_SIZE(fitipower_yts500xlai_480_800_cmd_list1); i++)
++	{
++		ops->cmd_write(dsi,  fitipower_yts500xlai_480_800_cmd_list1[i]);
++		value=mipi_dsih_read_word(dsi, R_DSI_HOST_INT_ST0);
++		if(value & 0x180000)
++		{
++			printk("-----2--->i=%d\n",i);
++		}
++	}
++//	dump_dsi_reg(dsi);
++}
++
++static int panel_dev_ioctl(struct mipi_dsim_lcd_device *dsim_dev, int cmd)
++{
++	return 0;
++}
++static void panel_dev_set_sequence(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct yts500xlai *lcd = dev_get_drvdata(&dsim_dev->dev);
++
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++
++	panel_dev_panel_init(panel);
++	panel_dev_sleep_out(panel);
++	msleep(150);
++	panel_dev_display_on(panel);
++	msleep(20);
++	/* dump_dsi_reg(dsi); */
++	lcd->power = FB_BLANK_UNBLANK;
++}
++static void panel_dev_power_on(struct mipi_dsim_lcd_device *dsim_dev, int power)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++	struct board_gpio *lcd_te = &panel->lcd_te;
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	if (gpio_is_valid(lcd_te->gpio)) {
++		gpio_direction_input(lcd_te->gpio);
++	}
++	msleep(50);
++	gpio_direction_output(rst->gpio, 0);
++	msleep(50);
++	gpio_direction_output(rst->gpio, 1);
++	msleep(120);
++
++	panel->power = power;
++}
++
++static struct fb_videomode panel_modes = {
++	.name = "fitipower_yts500xlai-lcd",
++	.xres = 720,
++	.yres = 1280,
++
++//	.refresh = 10,
++//	.refresh = 30,
++	.refresh = 35,
++//	.refresh = 60, /*no display*/
++//debug1
++	.left_margin = 88,//hbp
++	.right_margin = 35,//hfp
++	.hsync_len = 10, //hsync
++
++	.upper_margin = 37,//vbp
++	.lower_margin = 13,//vfp
++	.vsync_len = 10, //vsync
++//debug2
++//	.left_margin = 48,//hbp
++//	.right_margin = 16,//hfp
++//	.hsync_len = 8, //hsync
++//
++//	.upper_margin = 3,//vbp
++//	.lower_margin = 5,//vfp
++//	.vsync_len = 8, //vsync
++
++	.sync                   = FB_SYNC_HOR_HIGH_ACT & FB_SYNC_VERT_HIGH_ACT,
++	.vmode                  = FB_VMODE_NONINTERLACED,
++	.flag = 0,
++};
++
++struct jzdsi_data jzdsi_pdata = {
++	.modes = &panel_modes,
++	.video_config.no_of_lanes = 2,
++	.video_config.virtual_channel = 0,
++	.video_config.color_coding = COLOR_CODE_16BIT_CONFIG1,
++	.video_config.video_mode = VIDEO_BURST_WITH_SYNC_PULSES,
++	.video_config.receive_ack_packets = 0,	/* enable receiving of ack packets */
++	.video_config.is_18_loosely = 0,
++	.video_config.data_en_polarity = 1,
++	.video_config.byte_clock = 0, // driver will auto calculate byte_clock.
++//	.video_config.byte_clock_coef = MIPI_PHY_BYTE_CLK_COEF_MUL3_DIV2, //1: byte_clock *3/2.
++//	.video_config.byte_clock_coef = 2, // byte_clock *4/3 .
++	.video_config.byte_clock_coef = 3, // byte_clock *5/4 35fps.
++
++	.dsi_config.max_lanes = 2,
++	.dsi_config.max_hs_to_lp_cycles = 100,
++	.dsi_config.max_lp_to_hs_cycles = 40,
++//	.dsi_config.max_hs_to_lp_cycles = 200,
++//	.dsi_config.max_lp_to_hs_cycles = 80,
++	.dsi_config.max_bta_cycles = 4095,
++	.dsi_config.color_mode_polarity = 1,
++	.dsi_config.shut_down_polarity = 1,
++	.dsi_config.max_bps = 2750,
++//	.max_bps = 650,  // 650 Mbps
++//	.bpp_info = 24,
++	.bpp_info = 16,
++};
++static struct tft_config kd050hdfia019_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_565,
++};
++
++
++struct lcd_panel lcd_panel = {
++	.num_modes = 1,
++	.modes = &panel_modes,
++	.dsi_pdata = &jzdsi_pdata,
++
++	.lcd_type = LCD_TYPE_MIPI_TFT,
++	.tft_config = &kd050hdfia019_cfg,
++//	.bpp = 24,
++	.bpp = 16,
++//	.width = 700,
++//	.height = 1230,
++	.width = 68,
++	.height = 121,
++	.dither_enable = 0,
++	.dither.dither_red = 0,
++	.dither.dither_green = 0,
++	.dither.dither_blue = 0,
++
++
++};
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++* @ pannel_yts500xlai_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++
++
++	return 0;
++err_request_lcd_te:
++	if(gpio_is_valid(panel->rst.gpio))
++		gpio_free(panel->rst.gpio);
++err_request_rst:
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++	return ret;
++}
++
++static int panel_dev_probe(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct yts500xlai *lcd;
++	lcd = devm_kzalloc(&dsim_dev->dev, sizeof(struct yts500xlai), GFP_KERNEL);
++	if (!lcd)
++	{
++		dev_err(&dsim_dev->dev, "failed to allocate fitipower_yts500xlai structure.\n");
++		return -ENOMEM;
++	}
++
++	lcd->dsim_dev = dsim_dev;
++	lcd->dev = &dsim_dev->dev;
++
++	lcd->ld = lcd_device_register("fitipower_yts500xlai", lcd->dev, lcd,
++	                              &panel_lcd_ops);
++	if (IS_ERR(lcd->ld))
++	{
++		dev_err(lcd->dev, "failed to register lcd ops.\n");
++		return PTR_ERR(lcd->ld);
++	}
++
++	dev_set_drvdata(&dsim_dev->dev, lcd);
++
++
++	dev_dbg(lcd->dev, "probed fitipower_yts500xlai panel driver.\n");
++
++
++	panel->dsim_dev = dsim_dev;
++
++
++	return 0;
++
++}
++
++static int panel_suspend(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	return 0;
++}
++
++static int panel_resume(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int panel_pm_suspend(struct device *dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++	panel_dev_display_off(panel);
++	panel_dev_sleep_in(panel);
++	gpio_direction_output(vdd_en->gpio, !vdd_en->active_level);
++
++	return 0;
++}
++
++static int panel_pm_resume(struct device *dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	return 0;
++}
++
++static const struct dev_pm_ops panel_pm_ops = {
++	.suspend = panel_pm_suspend,
++	.resume = panel_pm_resume,
++};
++#endif
++
++static struct mipi_dsim_lcd_driver panel_dev_dsim_ddi_driver = {
++	.name = "fitipower_yts500xlai-lcd",
++	.id = -1,
++
++	.power_on = panel_dev_power_on,
++	.set_sequence = panel_dev_set_sequence,
++	.probe = panel_dev_probe,
++//	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++
++
++struct mipi_dsim_lcd_device panel_dev_device={
++	.name		= "fitipower_yts500xlai-lcd",
++	.id = 0,
++};
++
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	mipi_dsi_register_lcd_device(&panel_dev_device);
++	mipi_dsi_register_lcd_driver(&panel_dev_dsim_ddi_driver);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_of_parse;
++	}
++
++	return 0;
++
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,yts500xlai", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "yts500xlai",
++		.of_match_table = panel_of_match,
++#ifdef CONFIG_PM
++		.pm = &panel_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(panel_driver);
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/st7701s_dx3.95ips/ST7701S_DX3.95IPS_mipi_480x480_V1.0-RGB.txt b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/st7701s_dx3.95ips/ST7701S_DX3.95IPS_mipi_480x480_V1.0-RGB.txt
+new file mode 100644
+index 000000000..b565227ed
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/st7701s_dx3.95ips/ST7701S_DX3.95IPS_mipi_480x480_V1.0-RGB.txt
+@@ -0,0 +1,225 @@
++/******************************************************************************/
++/* Panel Name : D395N9375V0                                    */
++/* Resulation : 480x480                                                       */
++/* Inversion  : 2dot                                                          */
++/* Porch      : vbp=15 , vfp=12                                               */
++/* Line Time  : 32us                                                          */
++/* Frame Rate : 60hz                                                          */
++/******************************************************************************/
++
++
++IO1SET=RESB;        //reset=1
++delayms(10);
++IO1CLR=RESB;	    //reset=0
++delayms(50);
++IO1SET=RESB;        //reset=1
++delayms(120);
++
++GP_COMMAD_PA(6);OTA_SPI_writedat(0xFF);
++OTA_SPI_writedat(0x77);
++OTA_SPI_writedat(0x01);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x13);
++GP_COMMAD_PA(2);OTA_SPI_writedat(0xEF);
++OTA_SPI_writedat(0x08);
++GP_COMMAD_PA(6);OTA_SPI_writedat(0xFF);
++OTA_SPI_writedat(0x77);
++OTA_SPI_writedat(0x01);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x10);
++GP_COMMAD_PA(3);OTA_SPI_writedat(0xC0);
++OTA_SPI_writedat(0x3B);
++OTA_SPI_writedat(0x00);
++GP_COMMAD_PA(3);OTA_SPI_writedat(0xC1);
++OTA_SPI_writedat(0x0D);
++OTA_SPI_writedat(0x02);
++GP_COMMAD_PA(3);OTA_SPI_writedat(0xC2);
++OTA_SPI_writedat(0x21);
++OTA_SPI_writedat(0x08);
++//GP_COMMAD_PA(3);OTA_SPI_writedat(0xCD);
++//OTA_SPI_writedat(0x08);//18-bit/pixel: MDT=0:D[21:16]=R,D[13:8]=G,D[5:0]=B(CDH=00) ;
++
++//                 //              MDT=1:D[17:12]=R,D[11:6]=G,D[5:0]=B(CDH=08) ;
++
++
++GP_COMMAD_PA(17);OTA_SPI_writedat(0xB0);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x11);
++OTA_SPI_writedat(0x18);
++OTA_SPI_writedat(0x0E);
++OTA_SPI_writedat(0x11);
++OTA_SPI_writedat(0x06);
++OTA_SPI_writedat(0x07);
++OTA_SPI_writedat(0x08);
++OTA_SPI_writedat(0x07);
++OTA_SPI_writedat(0x22);
++OTA_SPI_writedat(0x04);
++OTA_SPI_writedat(0x12);
++OTA_SPI_writedat(0x0F);
++OTA_SPI_writedat(0xAA);
++OTA_SPI_writedat(0x31);
++OTA_SPI_writedat(0x18);
++GP_COMMAD_PA(17);OTA_SPI_writedat(0xB1);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x11);
++OTA_SPI_writedat(0x19);
++OTA_SPI_writedat(0x0E);
++OTA_SPI_writedat(0x12);
++OTA_SPI_writedat(0x07);
++OTA_SPI_writedat(0x08);
++OTA_SPI_writedat(0x08);
++OTA_SPI_writedat(0x08);
++OTA_SPI_writedat(0x22);
++OTA_SPI_writedat(0x04);
++OTA_SPI_writedat(0x11);
++OTA_SPI_writedat(0x11);
++OTA_SPI_writedat(0xA9);
++OTA_SPI_writedat(0x32);
++OTA_SPI_writedat(0x18);
++GP_COMMAD_PA(6);OTA_SPI_writedat(0xFF);
++OTA_SPI_writedat(0x77);
++OTA_SPI_writedat(0x01);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x11);
++GP_COMMAD_PA(2);OTA_SPI_writedat(0xB0);
++OTA_SPI_writedat(0x60);
++GP_COMMAD_PA(2);OTA_SPI_writedat(0xB1);
++OTA_SPI_writedat(0x30);
++GP_COMMAD_PA(2);OTA_SPI_writedat(0xB2);
++OTA_SPI_writedat(0x87);
++GP_COMMAD_PA(2);OTA_SPI_writedat(0xB3);
++OTA_SPI_writedat(0x80);
++GP_COMMAD_PA(2);OTA_SPI_writedat(0xB5);
++OTA_SPI_writedat(0x49);
++GP_COMMAD_PA(2);OTA_SPI_writedat(0xB7);
++OTA_SPI_writedat(0x85);
++GP_COMMAD_PA(2);OTA_SPI_writedat(0xB8);
++OTA_SPI_writedat(0x21);
++GP_COMMAD_PA(2);OTA_SPI_writedat(0xC1);
++OTA_SPI_writedat(0x78);
++GP_COMMAD_PA(2);OTA_SPI_writedat(0xC2);
++OTA_SPI_writedat(0x78);
++delayms(20);
++GP_COMMAD_PA(4);OTA_SPI_writedat(0xE0);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x1B);
++OTA_SPI_writedat(0x02);
++GP_COMMAD_PA(12);OTA_SPI_writedat(0xE1);
++OTA_SPI_writedat(0x08);
++OTA_SPI_writedat(0xA0);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x07);
++OTA_SPI_writedat(0xA0);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x44);
++OTA_SPI_writedat(0x44);
++GP_COMMAD_PA(13);OTA_SPI_writedat(0xE2);
++OTA_SPI_writedat(0x11);
++OTA_SPI_writedat(0x11);
++OTA_SPI_writedat(0x44);
++OTA_SPI_writedat(0x44);
++OTA_SPI_writedat(0xED);
++OTA_SPI_writedat(0xA0);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0xEC);
++OTA_SPI_writedat(0xA0);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x00);
++GP_COMMAD_PA(5);OTA_SPI_writedat(0xE3);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x11);
++OTA_SPI_writedat(0x11);
++GP_COMMAD_PA(3);OTA_SPI_writedat(0xE4);
++OTA_SPI_writedat(0x44);
++OTA_SPI_writedat(0x44);
++GP_COMMAD_PA(17);OTA_SPI_writedat(0xE5);
++OTA_SPI_writedat(0x0A);
++OTA_SPI_writedat(0xE9);
++OTA_SPI_writedat(0xD8);
++OTA_SPI_writedat(0xA0);
++OTA_SPI_writedat(0x0C);
++OTA_SPI_writedat(0xEB);
++OTA_SPI_writedat(0xD8);
++OTA_SPI_writedat(0xA0);
++OTA_SPI_writedat(0x0E);
++OTA_SPI_writedat(0xED);
++OTA_SPI_writedat(0xD8);
++OTA_SPI_writedat(0xA0);
++OTA_SPI_writedat(0x10);
++OTA_SPI_writedat(0xEF);
++OTA_SPI_writedat(0xD8);
++OTA_SPI_writedat(0xA0);
++GP_COMMAD_PA(5);OTA_SPI_writedat(0xE6);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x11);
++OTA_SPI_writedat(0x11);
++GP_COMMAD_PA(3);OTA_SPI_writedat(0xE7);
++OTA_SPI_writedat(0x44);
++OTA_SPI_writedat(0x44);
++GP_COMMAD_PA(17);OTA_SPI_writedat(0xE8);
++OTA_SPI_writedat(0x09);
++OTA_SPI_writedat(0xE8);
++OTA_SPI_writedat(0xD8);
++OTA_SPI_writedat(0xA0);
++OTA_SPI_writedat(0x0B);
++OTA_SPI_writedat(0xEA);
++OTA_SPI_writedat(0xD8);
++OTA_SPI_writedat(0xA0);
++OTA_SPI_writedat(0x0D);
++OTA_SPI_writedat(0xEC);
++OTA_SPI_writedat(0xD8);
++OTA_SPI_writedat(0xA0);
++OTA_SPI_writedat(0x0F);
++OTA_SPI_writedat(0xEE);
++OTA_SPI_writedat(0xD8);
++OTA_SPI_writedat(0xA0);
++GP_COMMAD_PA(8);OTA_SPI_writedat(0xEB);
++OTA_SPI_writedat(0x02);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0xE4);
++OTA_SPI_writedat(0xE4);
++OTA_SPI_writedat(0x88);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x40);
++GP_COMMAD_PA(3);OTA_SPI_writedat(0xEC);
++OTA_SPI_writedat(0x3C);
++OTA_SPI_writedat(0x00);
++GP_COMMAD_PA(17);OTA_SPI_writedat(0xED);
++OTA_SPI_writedat(0xAB);
++OTA_SPI_writedat(0x89);
++OTA_SPI_writedat(0x76);
++OTA_SPI_writedat(0x54);
++OTA_SPI_writedat(0x02);
++OTA_SPI_writedat(0xFF);
++OTA_SPI_writedat(0xFF);
++OTA_SPI_writedat(0xFF);
++OTA_SPI_writedat(0xFF);
++OTA_SPI_writedat(0xFF);
++OTA_SPI_writedat(0xFF);
++OTA_SPI_writedat(0x20);
++OTA_SPI_writedat(0x45);
++OTA_SPI_writedat(0x67);
++OTA_SPI_writedat(0x98);
++OTA_SPI_writedat(0xBA);
++GP_COMMAD_PA(6);OTA_SPI_writedat(0xFF);
++OTA_SPI_writedat(0x77);
++OTA_SPI_writedat(0x01);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x00);
++OTA_SPI_writedat(0x00);
++//GP_COMMAD_PA(6);OTA_SPI_writedat(0x3A);
++//OTA_SPI_writedat(0x66);//55/50=16bit(RGB565);66=18bit(RGB666);77?????3AH?=24bit(RGB888)
++GP_COMMAD_PA(1);OTA_SPI_writedat(0x11);
++delayms(120);
++GP_COMMAD_PA(1);OTA_SPI_writedat(0x29);
++delayms(20);
++
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/st7701s_dx3.95ips/panel-st7701sdx.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/st7701s_dx3.95ips/panel-st7701sdx.c
+new file mode 100644
+index 000000000..692528d05
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/displays/st7701s_dx3.95ips/panel-st7701sdx.c
+@@ -0,0 +1,497 @@
++/*
++ * driver/video/fbdev/ingenic/x2000_v12/displays/panel-st7701sdx.c
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/gpio.h>
++#include <linux/pwm_backlight.h>
++#include <linux/delay.h>
++#include <linux/lcd.h>
++#include <linux/of_gpio.h>
++#include <linux/fb.h>
++#include <linux/backlight.h>
++
++
++#include "../../ingenicfb.h"
++#include "../../jz_dsim.h"
++
++static int test = 0;
++
++struct board_gpio {
++	short gpio;
++	short active_level;
++};
++
++struct panel_dev {
++	/* ingenic frame buffer */
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	/* common lcd framework */
++	struct lcd_device *lcd;
++	struct backlight_device *backlight;
++	int power;
++
++	struct regulator *vcc;
++	struct board_gpio vdd_en;
++	struct board_gpio rst;
++	struct board_gpio lcd_te;
++	struct board_gpio lcd_pwm;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++};
++
++struct panel_dev *panel;
++
++#define lcd_to_master(a)	(a->dsim_dev->master)
++#define lcd_to_master_ops(a)	((lcd_to_master(a))->master_ops)
++
++struct st7701sdx {
++	struct device *dev;
++	unsigned int power;
++	unsigned int id;
++
++	struct lcd_device *ld;
++	struct backlight_device *bd;
++
++	struct mipi_dsim_lcd_device *dsim_dev;
++
++};
++
++static struct dsi_cmd_packet fitipower_st7701sdx_480_480_cmd_list1[] =
++{
++
++/**st7701sdx***/
++	{0x39, 0x06, 0x00, {0xFF, 0x77, 0x01, 0x00, 0x00, 0x13}},
++	{0x15, 0xEF, 0x08},
++	{0x39, 0x06, 0x00, {0xFF, 0x77, 0x01, 0x00, 0x00, 0x10}},
++	{0x39, 0x03, 0x00, {0xC0, 0x3B, 0x00}},
++	{0x39, 0x03, 0x00, {0xC1, 0x0D, 0x02}},
++	{0x39, 0x03, 0x00, {0xC2, 0x21, 0x08}},
++	{0x39, 0x11, 0x00, {0xB0, 0x00, 0x11, 0x18, 0x0E, 0x11, 0x06, 0x07, 0x08, 0x07, 0x22, 0x04, 0x12, 0x0F, 0xAA, 0x31, 0x18}},
++	{0x39, 0x11, 0x00, {0xB1, 0x00, 0x11, 0x19, 0x0E, 0x12, 0x07, 0x08, 0x08, 0x08, 0x22, 0x04, 0x11, 0x11, 0xA9, 0x32, 0x18}},
++	{0x39, 0x06, 0x00, {0xFF, 0x77, 0x01, 0x00, 0x00, 0x11}},
++	{0x39, 0x03, 0x00, {0xE8, 0x00, 0x0E}},
++/**st7701sdx***/
++
++};
++
++static struct dsi_cmd_packet fitipower_st7701sdx_480_480_cmd_list2[] =
++{
++	{0x15, 0xB0, 0x60},
++	{0x15, 0xB1, 0x30},
++	{0x15, 0xB2, 0x87},
++	{0x15, 0xB3, 0x80},
++	{0x15, 0xB5, 0x49},
++	{0x15, 0xB7, 0x85},
++	{0x15, 0xB8, 0x21},
++	{0x15, 0xC1, 0x78},
++	{0x15, 0xC2, 0x78},//delay 20ms
++};
++
++static struct dsi_cmd_packet fitipower_st7701sdx_480_480_cmd_list3[] =
++{
++	{0x39, 0x04, 0x00, {0xE0, 0x00, 0x1B, 0x02}},
++	{0x39, 0x0C, 0x00, {0xE1, 0x08, 0xA0, 0x00, 0x00, 0x07, 0xA0, 0x00, 0x00, 0x00, 0x44, 0x44}},
++	{0x39, 0x0D, 0x00, {0xE2, 0x11, 0x11, 0x44, 0x44, 0xED, 0xA0, 0x00, 0x00, 0xEC, 0xA0, 0x00, 0x00}},
++	{0x39, 0x05, 0x00, {0xE3, 0x00, 0x00, 0x11, 0x11}},
++	{0x39, 0x03, 0x00, {0xE4, 0x44, 0x44}},
++	{0x39, 0x11, 0x00, {0xE5, 0x0A, 0xE9, 0xD8, 0xA0, 0x0C, 0xEB, 0xD8, 0xA0, 0x0E, 0xED, 0xD8, 0xA0, 0x10, 0xEF, 0xD8, 0xA0}},
++	{0x39, 0x05, 0x00, {0xE6, 0x00, 0x00, 0x11, 0x11}},
++	{0x39, 0x04, 0x00, {0xE7, 0x44, 0x44}},
++	{0x39, 0x11, 0x00, {0xE8, 0x09, 0xE8, 0xD8, 0xA0, 0x0B, 0xEA, 0xD8, 0xA0, 0x0D, 0xEC, 0xD8, 0xA0, 0x0F, 0xEE, 0xD8, 0xA0}},
++	{0x39, 0x08, 0x00, {0xEB, 0x02, 0x00, 0xE4, 0xE4, 0x88, 0x00, 0x40}},
++	{0x39, 0x03, 0x00, {0xEC, 0x3C, 0x00}},
++	{0x39, 0x11, 0x00, {0xED, 0xAB, 0x89, 0x76, 0x54, 0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFf, 0x20, 0x45, 0x67, 0x98, 0xBA}},
++	{0x39, 0x06, 0x00, {0xFF, 0x77, 0x01, 0x00, 0x00, 0x00}},
++};
++
++
++static void panel_dev_sleep_in(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x10, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_sleep_out(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x11, 0x00};
++//	while (1) {
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++//	}
++}
++
++static void panel_dev_display_on(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);//color bar turn off 0x29 command.
++	struct dsi_cmd_packet data_to_send = {0x05, 0x29, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++static void panel_dev_display_off(struct panel_dev *lcd)
++{
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_cmd_packet data_to_send = {0x05, 0x28, 0x00};
++
++	ops->cmd_write(lcd_to_master(lcd), data_to_send);
++}
++
++
++static void panel_dev_panel_init(struct panel_dev *lcd)
++{
++	int  i;
++	struct dsi_master_ops *ops = lcd_to_master_ops(lcd);
++	struct dsi_device *dsi = lcd_to_master(lcd);
++
++	for (i = 0; i < ARRAY_SIZE(fitipower_st7701sdx_480_480_cmd_list1); i++)
++	{
++		ops->cmd_write(dsi,  fitipower_st7701sdx_480_480_cmd_list1[i]);
++	}
++//	msleep(120);
++	for (i = 0; i < ARRAY_SIZE(fitipower_st7701sdx_480_480_cmd_list2); i++)
++	{
++		ops->cmd_write(dsi,  fitipower_st7701sdx_480_480_cmd_list2[i]);
++	}
++	msleep(20);
++	for (i = 0; i < ARRAY_SIZE(fitipower_st7701sdx_480_480_cmd_list3); i++)
++	{
++		ops->cmd_write(dsi,  fitipower_st7701sdx_480_480_cmd_list3[i]);
++	}
++}
++
++static int panel_dev_ioctl(struct mipi_dsim_lcd_device *dsim_dev, int cmd)
++{
++	return 0;
++}
++static void panel_dev_set_sequence(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct st7701sdx *lcd = dev_get_drvdata(&dsim_dev->dev);
++
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++	if(test != 0)
++		return;
++	test++;
++
++	panel_dev_panel_init(panel);
++	panel_dev_sleep_out(panel);
++	msleep(120);
++	panel_dev_display_on(panel);
++	msleep(20);
++	/* dump_dsi_reg(dsi); */
++	lcd->power = FB_BLANK_UNBLANK;
++}
++static void panel_dev_power_on(struct mipi_dsim_lcd_device *dsim_dev, int power)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	struct board_gpio *rst = &panel->rst;
++	struct board_gpio *lcd_te = &panel->lcd_te;
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++
++	if(test != 0)
++		return;
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	if (gpio_is_valid(lcd_te->gpio)) {
++		gpio_direction_input(lcd_te->gpio);
++	}
++	msleep(50);
++	gpio_direction_output(rst->gpio, 0);
++	msleep(50);
++	gpio_direction_output(rst->gpio, 1);
++	msleep(120);
++
++	panel->power = power;
++}
++
++static struct fb_videomode panel_modes = {
++	.name = "fitipower_st7701sdx-lcd",
++	.xres = 480,
++	.yres = 480,
++//	.xres = 268,
++//	.yres = 800,
++
++//	.refresh = 10,
++	.refresh = 60,
++
++	.left_margin = 20,//hbp
++	.right_margin = 20,//hfp
++	.hsync_len = 20, //hsync
++
++//	.upper_margin = 16,//vbp
++	.upper_margin = 18,//vbp
++	.lower_margin = 16,//vfp
++	.vsync_len = 4, //vsync
++
++	.sync                   = FB_SYNC_HOR_HIGH_ACT & FB_SYNC_VERT_HIGH_ACT,
++	.vmode                  = FB_VMODE_NONINTERLACED,
++	.flag = 0,
++};
++
++struct jzdsi_data jzdsi_pdata = {
++	.modes = &panel_modes,
++	.video_config.no_of_lanes = 2,
++	.video_config.virtual_channel = 0,
++	.video_config.color_coding = COLOR_CODE_24BIT,
++	.video_config.video_mode = VIDEO_BURST_WITH_SYNC_PULSES,
++	.video_config.receive_ack_packets = 0,	/* enable receiving of ack packets */
++	.video_config.is_18_loosely = 0,
++	.video_config.data_en_polarity = 1,
++	.video_config.byte_clock = 0, // driver will auto calculate byte_clock.
++	.video_config.byte_clock_coef = MIPI_PHY_BYTE_CLK_COEF_MUL3_DIV2, // byte_clock *3/2.
++
++	.dsi_config.max_lanes = 2,
++	.dsi_config.max_hs_to_lp_cycles = 100,
++	.dsi_config.max_lp_to_hs_cycles = 40,
++//	.dsi_config.max_hs_to_lp_cycles = 200,
++//	.dsi_config.max_lp_to_hs_cycles = 80,
++	.dsi_config.max_bta_cycles = 4095,
++	.dsi_config.color_mode_polarity = 1,
++	.dsi_config.shut_down_polarity = 1,
++	.dsi_config.max_bps = 2750,
++//	.max_bps = 650,  // 650 Mbps
++	.bpp_info = 24,
++};
++static struct tft_config kd050hdfia019_cfg = {
++	.pix_clk_inv = 0,
++	.de_dl = 0,
++	.sync_dl = 0,
++	.color_even = TFT_LCD_COLOR_EVEN_RGB,
++	.color_odd = TFT_LCD_COLOR_ODD_RGB,
++	.mode = TFT_LCD_MODE_PARALLEL_888,
++};
++
++
++struct lcd_panel lcd_panel = {
++	.num_modes = 1,
++	.modes = &panel_modes,
++	.dsi_pdata = &jzdsi_pdata,
++
++	.lcd_type = LCD_TYPE_MIPI_TFT,
++	.tft_config = &kd050hdfia019_cfg,
++	.bpp = 24,
++//	.width = 700,
++//	.height = 1230,
++	.width = 68,
++	.height = 121,
++	.dither_enable = 0,
++	.dither.dither_red = 0,
++	.dither.dither_green = 0,
++	.dither.dither_blue = 0,
++
++
++};
++
++#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
++static int panel_set_power(struct lcd_device *lcd, int power)
++{
++        return 0;
++}
++
++static int panel_get_power(struct lcd_device *lcd)
++{
++	struct panel_dev *panel = lcd_get_data(lcd);
++
++	return panel->power;
++}
++
++/**
++* @ pannel_st7701sdx_lcd_ops, register to kernel common backlight/lcd.c framworks.
++*/
++static struct lcd_ops panel_lcd_ops = {
++	.early_set_power = panel_set_power,
++	.set_power = panel_set_power,
++	.get_power = panel_get_power,
++};
++
++static int of_panel_parse(struct device *dev)
++{
++	struct panel_dev *panel = dev_get_drvdata(dev);
++	struct device_node *np = dev->of_node;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	panel->rst.gpio = of_get_named_gpio_flags(np, "ingenic,rst-gpio", 0, &flags);
++	if(gpio_is_valid(panel->rst.gpio)) {
++		panel->rst.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++		ret = gpio_request_one(panel->rst.gpio, GPIOF_DIR_OUT, "rst");
++		if(ret < 0) {
++			dev_err(dev, "Failed to request rst pin!\n");
++			goto err_request_rst;
++		}
++	} else {
++		dev_warn(dev, "invalid gpio rst.gpio: %d\n", panel->rst.gpio);
++	}
++
++/**lcd_bl_pwm pin as normal io pin config pull up***/
++//	panel->lcd_pwm.gpio = of_get_named_gpio_flags(np, "ingenic,lcd-pwm-gpio", 0, &flags);
++//	if(gpio_is_valid(panel->lcd_pwm.gpio)) {
++//		panel->lcd_pwm.active_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
++//		ret = gpio_direction_output(panel->lcd_pwm.gpio,1);
++//		if(ret < 0) {
++//			dev_err(dev, "Failed to request lcd-pwm pin!\n");
++//			return ret;
++//		}
++//	} else {
++//		dev_warn(dev, "invalid gpio lcd-pwm.gpio: %d\n", panel->lcd_pwm.gpio);
++//	}
++//
++
++	return 0;
++err_request_rst:
++	if(gpio_is_valid(panel->vdd_en.gpio))
++		gpio_free(panel->vdd_en.gpio);
++	return ret;
++}
++
++static int panel_dev_probe(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct st7701sdx *lcd;
++	lcd = devm_kzalloc(&dsim_dev->dev, sizeof(struct st7701sdx), GFP_KERNEL);
++	if (!lcd)
++	{
++		dev_err(&dsim_dev->dev, "failed to allocate fitipower_st7701sdx structure.\n");
++		return -ENOMEM;
++	}
++
++	lcd->dsim_dev = dsim_dev;
++	lcd->dev = &dsim_dev->dev;
++
++	lcd->ld = lcd_device_register("fitipower_st7701sdx", lcd->dev, lcd,
++	                              &panel_lcd_ops);
++	if (IS_ERR(lcd->ld))
++	{
++		dev_err(lcd->dev, "failed to register lcd ops.\n");
++		return PTR_ERR(lcd->ld);
++	}
++
++	dev_set_drvdata(&dsim_dev->dev, lcd);
++
++
++	dev_dbg(lcd->dev, "probed fitipower_st7701sdx panel driver.\n");
++
++
++	panel->dsim_dev = dsim_dev;
++
++
++	return 0;
++
++}
++
++static int panel_suspend(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++	panel_dev_display_off(panel);
++	panel_dev_sleep_in(panel);
++	gpio_direction_output(vdd_en->gpio, !vdd_en->active_level);
++
++	return 0;
++}
++
++static int panel_resume(struct mipi_dsim_lcd_device *dsim_dev)
++{
++	struct board_gpio *vdd_en = &panel->vdd_en;
++	printk(">>>>>>>>>>>>>>>>>>>>%s %d\n",__func__,__LINE__);
++
++	gpio_direction_output(vdd_en->gpio, vdd_en->active_level);
++
++	return 0;
++}
++
++static struct mipi_dsim_lcd_driver panel_dev_dsim_ddi_driver = {
++	.name = "fitipower_st7701sdx-lcd",
++	.id = -1,
++
++	.power_on = panel_dev_power_on,
++	.set_sequence = panel_dev_set_sequence,
++	.probe = panel_dev_probe,
++//	.suspend = panel_suspend,
++	.resume = panel_resume,
++};
++
++
++struct mipi_dsim_lcd_device panel_dev_device={
++	.name		= "fitipower_st7701sdx-lcd",
++	.id = 0,
++};
++
++/**
++* @panel_probe
++*
++* 	1. Register to ingenicfb.
++* 	2. Register to lcd.
++* 	3. Register to backlight if possible.
++*
++* @pdev
++*
++* @Return -
++*/
++static int panel_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++
++	panel = kzalloc(sizeof(struct panel_dev), GFP_KERNEL);
++	if(panel == NULL) {
++		dev_err(&pdev->dev, "Faile to alloc memory!");
++		return -ENOMEM;
++	}
++	panel->dev = &pdev->dev;
++	dev_set_drvdata(&pdev->dev, panel);
++
++	ret = of_panel_parse(&pdev->dev);
++	if(ret < 0) {
++		goto err_of_parse;
++	}
++
++	mipi_dsi_register_lcd_device(&panel_dev_device);
++	mipi_dsi_register_lcd_driver(&panel_dev_dsim_ddi_driver);
++
++	ret = ingenicfb_register_panel(&lcd_panel);
++	if(ret < 0) {
++		dev_err(&pdev->dev, "Failed to register lcd panel!\n");
++		goto err_of_parse;
++	}
++
++	return 0;
++
++err_of_parse:
++	kfree(panel);
++	return ret;
++}
++
++static int panel_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id panel_of_match[] = {
++	{ .compatible = "ingenic,st7701s-dx", },
++	{},
++};
++
++static struct platform_driver panel_driver = {
++	.probe		= panel_probe,
++	.remove		= panel_remove,
++	.driver		= {
++		.name	= "st7701sdx",
++		.of_match_table = panel_of_match,
++	},
++};
++
++module_platform_driver(panel_driver);
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/dpu_ctrl.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/dpu_ctrl.c
+new file mode 100644
+index 000000000..1e5332e0a
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/dpu_ctrl.c
+@@ -0,0 +1,2005 @@
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++#include <linux/poll.h>
++#include <linux/wait.h>
++#include <linux/fs.h>
++#include <linux/irq.h>
++#include <linux/mm.h>
++#include <linux/fb.h>
++#include <linux/delay.h>
++#include <linux/ctype.h>
++#include <linux/dma-mapping.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/memory.h>
++#include <linux/suspend.h>
++#include <linux/string.h>
++#include <linux/kthread.h>
++#include <linux/gpio.h>
++#include <asm/cacheflush.h>
++#include <linux/of_address.h>
++
++#include "dpu_reg.h"
++#include "dpu_ctrl.h"
++
++
++static void dump_dc_reg(struct dpu_ctrl *dctrl)
++{
++	printk("-----------------dc_reg------------------\n");
++	printk("DC_FRM_CFG_ADDR(0x%04x):    0x%08lx\n", DC_FRM_CFG_ADDR,reg_read(dctrl, DC_FRM_CFG_ADDR));
++	printk("DC_FRM_CFG_CTRL(0x%04x):    0x%08lx\n", DC_FRM_CFG_CTRL,reg_read(dctrl, DC_FRM_CFG_CTRL));
++	printk("DC_RDMA_CHAIN_ADDR(0x%04x):    0x%08lx\n", DC_RDMA_CHAIN_ADDR,reg_read(dctrl, DC_RDMA_CHAIN_ADDR));
++	printk("DC_RDMA_CHAIN_CTRL(0x%04x):    0x%08lx\n", DC_RDMA_CHAIN_CTRL,reg_read(dctrl, DC_RDMA_CHAIN_CTRL));
++	printk("DC_CTRL(0x%04x):            0x%08lx\n", DC_CTRL, reg_read(dctrl, DC_CTRL));
++	printk("DC_CSC_MULT_YRV(0x%04x):    0x%08lx\n", DC_CSC_MULT_YRV,reg_read(dctrl, DC_CSC_MULT_YRV));
++	printk("DC_CSC_MULT_GUGV(0x%04x):   0x%08lx\n", DC_CSC_MULT_GUGV,reg_read(dctrl, DC_CSC_MULT_GUGV));
++	printk("DC_CSC_MULT_BU(0x%04x):     0x%08lx\n", DC_CSC_MULT_BU,reg_read(dctrl, DC_CSC_MULT_BU));
++	printk("DC_CSC_SUB_YUV(0x%04x):     0x%08lx\n", DC_CSC_SUB_YUV,reg_read(dctrl, DC_CSC_SUB_YUV));
++	printk("DC_ST(0x%04x):              0x%08lx\n", DC_ST, reg_read(dctrl, DC_ST));
++	printk("DC_INTC(0x%04x):            0x%08lx\n", DC_INTC, reg_read(dctrl, DC_INTC));
++	printk("DC_INT_FLAG(0x%04x):	   0x%08lx\n", DC_INT_FLAG, reg_read(dctrl, DC_INT_FLAG));
++	printk("DC_COM_CONFIG(0x%04x):      0x%08lx\n", DC_COM_CONFIG ,reg_read(dctrl, DC_COM_CONFIG));
++	printk("DC_TLB_GLBC(0x%04x):        0x%08lx\n", DC_TLB_GLBC,reg_read(dctrl, DC_TLB_GLBC));
++	printk("DC_TLB_TLBA(0x%04x):        0x%08lx\n", DC_TLB_TLBA,reg_read(dctrl, DC_TLB_TLBA));
++	printk("DC_TLB_TLBC(0x%04x):        0x%08lx\n", DC_TLB_TLBC,reg_read(dctrl, DC_TLB_TLBC));
++	printk("DC_TLB0_VPN(0x%04x):        0x%08lx\n", DC_TLB0_VPN,reg_read(dctrl, DC_TLB0_VPN));
++	printk("DC_TLB1_VPN(0x%04x):        0x%08lx\n", DC_TLB1_VPN,reg_read(dctrl, DC_TLB1_VPN));
++	printk("DC_TLB2_VPN(0x%04x):        0x%08lx\n", DC_TLB2_VPN,reg_read(dctrl, DC_TLB2_VPN));
++	printk("DC_TLB3_VPN(0x%04x):        0x%08lx\n", DC_TLB3_VPN,reg_read(dctrl, DC_TLB3_VPN));
++	printk("DC_TLB_TLBV(0x%04x):        0x%08lx\n", DC_TLB_TLBV,reg_read(dctrl, DC_TLB_TLBV));
++	printk("DC_TLB_STAT(0x%04x):        0x%08lx\n", DC_TLB_STAT,reg_read(dctrl, DC_TLB_STAT));
++	printk("DC_PCFG_RD_CTRL(0x%04x):    0x%08lx\n", DC_PCFG_RD_CTRL,reg_read(dctrl, DC_PCFG_RD_CTRL));
++	printk("DC_PCFG_WR_CTRL(0x%04x):    0x%08lx\n", DC_PCFG_WR_CTRL,reg_read(dctrl, DC_PCFG_WR_CTRL));
++	printk("DC_OFIFO_PCFG(0x%04x):	   0x%08lx\n", DC_OFIFO_PCFG,reg_read(dctrl, DC_OFIFO_PCFG));
++	printk("DC_WDMA_PCFG(0x%04x):	   0x%08lx\n", DC_WDMA_PCFG,reg_read(dctrl, DC_WDMA_PCFG));
++	printk("DC_CMPW_PCFG_CTRL(0x%04x): 0x%08lx\n", DC_CMPW_PCFG_CTRL,reg_read(dctrl, DC_CMPW_PCFG_CTRL));
++	printk("DC_CMPW_PCFG0(0x%04x):	   0x%08lx\n", DC_CMPW_PCFG0,reg_read(dctrl, DC_CMPW_PCFG0));
++	printk("DC_CMPW_PCFG1(0x%04x):	   0x%08lx\n", DC_CMPW_PCFG1,reg_read(dctrl, DC_CMPW_PCFG1));
++	printk("DC_CMPW_PCFG2(0x%04x):	   0x%08lx\n", DC_CMPW_PCFG2,reg_read(dctrl, DC_CMPW_PCFG2));
++	printk("DC_PCFG_RD_CTRL(0x%04x):    0x%08lx\n", DC_PCFG_RD_CTRL,reg_read(dctrl, DC_PCFG_RD_CTRL));
++	printk("DC_OFIFO_PCFG(0x%04x):	   0x%08lx\n", DC_OFIFO_PCFG,reg_read(dctrl, DC_OFIFO_PCFG));
++	printk("DC_DISP_COM(0x%04x):        0x%08lx\n", DC_DISP_COM,reg_read(dctrl, DC_DISP_COM));
++	printk("-----------------dc_reg------------------\n");
++}
++
++static void dump_tft_reg(struct dpu_ctrl *dctrl)
++{
++	printk("----------------tft_reg------------------\n");
++	printk("TFT_TIMING_HSYNC(0x%04x):   0x%08lx\n", DC_TFT_HSYNC, reg_read(dctrl, DC_TFT_HSYNC));
++	printk("TFT_TIMING_VSYNC(0x%04x):   0x%08lx\n", DC_TFT_VSYNC, reg_read(dctrl, DC_TFT_VSYNC));
++	printk("TFT_TIMING_HDE(0x%04x):     0x%08lx\n", DC_TFT_HDE, reg_read(dctrl, DC_TFT_HDE));
++	printk("TFT_TIMING_VDE(0x%04x):     0x%08lx\n", DC_TFT_VDE, reg_read(dctrl, DC_TFT_VDE));
++	printk("TFT_TRAN_CFG(0x%04x):       0x%08lx\n", DC_TFT_CFG, reg_read(dctrl, DC_TFT_CFG));
++	printk("TFT_ST(0x%04x):             0x%08lx\n", DC_TFT_ST, reg_read(dctrl, DC_TFT_ST));
++	printk("----------------tft_reg------------------\n");
++}
++
++static void dump_slcd_reg(struct dpu_ctrl *dctrl)
++{
++	printk("---------------slcd_reg------------------\n");
++	printk("SLCD_CFG(0x%04x):           0x%08lx\n", DC_SLCD_CFG, reg_read(dctrl, DC_SLCD_CFG));
++	printk("SLCD_WR_DUTY(0x%04x):       0x%08lx\n", DC_SLCD_WR_DUTY, reg_read(dctrl, DC_SLCD_WR_DUTY));
++	printk("SLCD_TIMING(0x%04x):        0x%08lx\n", DC_SLCD_TIMING, reg_read(dctrl, DC_SLCD_TIMING));
++	printk("SLCD_FRM_SIZE(0x%04x):      0x%08lx\n", DC_SLCD_FRM_SIZE, reg_read(dctrl, DC_SLCD_FRM_SIZE));
++	printk("SLCD_SLOW_TIME(0x%04x):     0x%08lx\n", DC_SLCD_SLOW_TIME, reg_read(dctrl, DC_SLCD_SLOW_TIME));
++	printk("SLCD_REG_IF(0x%04x):	    0x%08lx\n", DC_SLCD_REG_IF, reg_read(dctrl, DC_SLCD_REG_IF));
++	printk("SLCD_ST(0x%04x):            0x%08lx\n", DC_SLCD_ST, reg_read(dctrl, DC_SLCD_ST));
++	printk("---------------slcd_reg------------------\n");
++}
++
++static void dump_frm_desc_reg(struct dpu_ctrl *dctrl)
++{
++	unsigned int ctrl;
++	ctrl = reg_read(dctrl, DC_CTRL);
++	ctrl |= DC_DES_CNT_RST;
++	reg_write(dctrl, DC_CTRL, ctrl);
++
++	printk("--------Frame Descriptor register--------\n");
++	printk("FrameNextCfgAddr:   %lx\n",reg_read(dctrl, DC_FRM_DES));
++	printk("FrameSize:          %lx\n",reg_read(dctrl, DC_FRM_DES));
++	printk("FrameCtrl:          %lx\n",reg_read(dctrl, DC_FRM_DES));
++	printk("WritebackAddr:      %lx\n",reg_read(dctrl, DC_FRM_DES));
++	printk("WritebackStride:    %lx\n",reg_read(dctrl, DC_FRM_DES));
++	printk("Layer0CfgAddr:      %lx\n",reg_read(dctrl, DC_FRM_DES));
++	printk("Layer1CfgAddr:      %lx\n",reg_read(dctrl, DC_FRM_DES));
++	printk("Layer2CfgAddr:      %lx\n",reg_read(dctrl, DC_FRM_DES));
++	printk("Layer3CfgAddr:      %lx\n",reg_read(dctrl, DC_FRM_DES));
++	printk("LayCfgEn:	    %lx\n",reg_read(dctrl, DC_FRM_DES));
++	printk("InterruptControl:   %lx\n",reg_read(dctrl, DC_FRM_DES));
++	printk("--------Frame Descriptor register--------\n");
++}
++
++static void dump_layer_desc_reg(struct dpu_ctrl *dctrl)
++{
++	unsigned int ctrl;
++	ctrl = reg_read(dctrl, DC_CTRL);
++	ctrl |= DC_DES_CNT_RST;
++	reg_write(dctrl, DC_CTRL, ctrl);
++
++	printk("--------layer0 Descriptor register-------\n");
++	printk("LayerSize:          %lx\n",reg_read(dctrl, DC_LAY0_DES));
++	printk("LayerCfg:           %lx\n",reg_read(dctrl, DC_LAY0_DES));
++	printk("LayerBufferAddr:    %lx\n",reg_read(dctrl, DC_LAY0_DES));
++	printk("LayerScale:         %lx\n",reg_read(dctrl, DC_LAY0_DES));
++	printk("LayerRotation:      %lx\n",reg_read(dctrl, DC_LAY0_DES));
++	printk("LayerScratch:       %lx\n",reg_read(dctrl, DC_LAY0_DES));
++	printk("LayerPos:           %lx\n",reg_read(dctrl, DC_LAY0_DES));
++	printk("LayerResizeCoef_X:  %lx\n",reg_read(dctrl, DC_LAY0_DES));
++	printk("LayerResizeCoef_Y:  %lx\n",reg_read(dctrl, DC_LAY0_DES));
++	printk("LayerStride:        %lx\n",reg_read(dctrl, DC_LAY0_DES));
++//	printk("Layer_UV_addr:	    %lx\n",reg_read(dctrl, DC_LAY0_DES));
++//	printk("Layer_UV_stride:    %lx\n",reg_read(dctrl, DC_LAY0_DES));
++	printk("--------layer0 Descriptor register-------\n");
++
++	printk("--------layer1 Descriptor register-------\n");
++	printk("LayerSize:          %lx\n",reg_read(dctrl, DC_LAY1_DES));
++	printk("LayerCfg:           %lx\n",reg_read(dctrl, DC_LAY1_DES));
++	printk("LayerBufferAddr:    %lx\n",reg_read(dctrl, DC_LAY1_DES));
++	printk("LayerScale:         %lx\n",reg_read(dctrl, DC_LAY1_DES));
++	printk("LayerRotation:      %lx\n",reg_read(dctrl, DC_LAY1_DES));
++	printk("LayerScratch:       %lx\n",reg_read(dctrl, DC_LAY1_DES));
++	printk("LayerPos:           %lx\n",reg_read(dctrl, DC_LAY1_DES));
++	printk("LayerResizeCoef_X:  %lx\n",reg_read(dctrl, DC_LAY1_DES));
++	printk("LayerResizeCoef_Y:  %lx\n",reg_read(dctrl, DC_LAY1_DES));
++	printk("LayerStride:        %lx\n",reg_read(dctrl, DC_LAY1_DES));
++//	printk("Layer_UV_addr:	    %lx\n",reg_read(dctrl, DC_LAY1_DES));
++//	printk("Layer_UV_stride:    %lx\n",reg_read(dctrl, DC_LAY1_DES));
++	printk("--------layer1 Descriptor register-------\n");
++
++	printk("--------layer2 Descriptor register-------\n");
++	printk("LayerSize:          %lx\n",reg_read(dctrl, DC_LAY2_DES));
++	printk("LayerCfg:           %lx\n",reg_read(dctrl, DC_LAY2_DES));
++	printk("LayerBufferAddr:    %lx\n",reg_read(dctrl, DC_LAY2_DES));
++	printk("LayerScale:         %lx\n",reg_read(dctrl, DC_LAY2_DES));
++	printk("LayerRotation:      %lx\n",reg_read(dctrl, DC_LAY2_DES));
++	printk("LayerScratch:       %lx\n",reg_read(dctrl, DC_LAY2_DES));
++	printk("LayerPos:           %lx\n",reg_read(dctrl, DC_LAY2_DES));
++	printk("LayerResizeCoef_X:  %lx\n",reg_read(dctrl, DC_LAY2_DES));
++	printk("LayerResizeCoef_Y:  %lx\n",reg_read(dctrl, DC_LAY2_DES));
++	printk("LayerStride:        %lx\n",reg_read(dctrl, DC_LAY2_DES));
++//	printk("Layer_UV_addr:	    %lx\n",reg_read(dctrl, DC_LAY2_DES));
++//	printk("Layer_UV_stride:    %lx\n",reg_read(dctrl, DC_LAY2_DES));
++	printk("--------layer2 Descriptor register-------\n");
++
++	printk("--------layer3 Descriptor register-------\n");
++	printk("LayerSize:          %lx\n",reg_read(dctrl, DC_LAY3_DES));
++	printk("LayerCfg:           %lx\n",reg_read(dctrl, DC_LAY3_DES));
++	printk("LayerBufferAddr:    %lx\n",reg_read(dctrl, DC_LAY3_DES));
++	printk("LayerScale:         %lx\n",reg_read(dctrl, DC_LAY3_DES));
++	printk("LayerRotation:      %lx\n",reg_read(dctrl, DC_LAY3_DES));
++	printk("LayerScratch:       %lx\n",reg_read(dctrl, DC_LAY3_DES));
++	printk("LayerPos:           %lx\n",reg_read(dctrl, DC_LAY3_DES));
++	printk("LayerResizeCoef_X:  %lx\n",reg_read(dctrl, DC_LAY3_DES));
++	printk("LayerResizeCoef_Y:  %lx\n",reg_read(dctrl, DC_LAY3_DES));
++	printk("LayerStride:        %lx\n",reg_read(dctrl, DC_LAY3_DES));
++//	printk("Layer_UV_addr:	    %lx\n",reg_read(dctrl, DC_LAY3_DES));
++//	printk("Layer_UV_stride:    %lx\n",reg_read(dctrl, DC_LAY3_DES));
++	printk("--------layer3 Descriptor register-------\n");
++}
++
++static void dump_rdma_desc_reg(struct dpu_ctrl *dctrl)
++{
++	unsigned int ctrl;
++	ctrl = reg_read(dctrl, DC_CTRL);
++	ctrl |= (1 << 2);
++	reg_write(dctrl, DC_CTRL, ctrl);
++	printk("====================rdma Descriptor register======================\n");
++	printk("RdmaNextCfgAddr:    %lx\n",reg_read(dctrl, DC_RDMA_DES));
++	printk("FrameBufferAddr:    %lx\n",reg_read(dctrl, DC_RDMA_DES));
++	printk("Stride:             %lx\n",reg_read(dctrl, DC_RDMA_DES));
++	printk("ChainCfg:           %lx\n",reg_read(dctrl, DC_RDMA_DES));
++	printk("InterruptControl:   %lx\n",reg_read(dctrl, DC_RDMA_DES));
++	printk("==================rdma Descriptor register end======================\n");
++}
++
++void dump_lcdc_registers(struct dpu_ctrl *dctrl)
++{
++	dump_dc_reg(dctrl);
++	dump_tft_reg(dctrl);
++	dump_slcd_reg(dctrl);
++	dump_frm_desc_reg(dctrl);
++	dump_layer_desc_reg(dctrl);
++	dump_rdma_desc_reg(dctrl);
++}
++static irqreturn_t dpu_ctrl_irq_handler(int irq, void *data)
++{
++	unsigned int irq_flag;
++	struct dpu_ctrl *dctrl = (struct dpu_ctrl *)data;
++
++	spin_lock(&dctrl->irq_lock);
++
++	dbg_irqcnt_inc(dctrl->dbg_irqcnt, irqcnt);
++
++	irq_flag = reg_read(dctrl, DC_INT_FLAG);
++	if(likely(irq_flag & DC_CMP_START)) {
++		reg_write(dctrl, DC_CLR_ST, DC_CLR_CMP_START);
++		dbg_irqcnt_inc(dctrl->dbg_irqcnt, cmp_start);
++		//TODO:
++		//ingenicfb_set_vsync_value(dctrl);
++		//dctrl->set_vsync_value(dctrl->vsync_data);
++		dctrl->comp_hw_framedesc = reg_read(dctrl, DC_FRM_CHAIN_SITE);
++		wake_up_interruptible(&dctrl->wq);
++		spin_unlock(&dctrl->irq_lock);
++		return IRQ_HANDLED;
++	}
++#define IRQ_P_N 50
++
++	if(unlikely(irq_flag & DC_STOP_CMP_ACK)) {
++		reg_write(dctrl, DC_CLR_ST, DC_CLR_STOP_CMP_ACK);
++		dbg_irqcnt_inc(dctrl->dbg_irqcnt, stop_disp_ack);
++
++		dctrl->comp_stopped = 1;
++		wake_up_interruptible(&dctrl->wq);
++		spin_unlock(&dctrl->irq_lock);
++		return IRQ_HANDLED;
++	}
++
++	if(unlikely(irq_flag & DC_DISP_END)) {
++		reg_write(dctrl, DC_CLR_ST, DC_CLR_DISP_END);
++		dbg_irqcnt_inc(dctrl->dbg_irqcnt, disp_end);
++		//dev_dbg(dctrl->dev, "DC_DISP_END");
++		//dctrl->dsi->master_ops->query_te(dctrl->dsi);
++		spin_unlock(&dctrl->irq_lock);
++		return IRQ_HANDLED;
++	}
++
++
++	if(unlikely(irq_flag & DC_TFT_UNDR)) {
++		reg_write(dctrl, DC_CLR_ST, DC_CLR_TFT_UNDR);
++		dbg_irqcnt_inc(dctrl->dbg_irqcnt, tft_under);
++		spin_unlock(&dctrl->irq_lock);
++		return IRQ_HANDLED;
++	}
++
++	if(likely(irq_flag & DC_WDMA_OVER)) {
++		dbg_irqcnt_inc(dctrl->dbg_irqcnt, wdma_over);
++		reg_write(dctrl, DC_CLR_ST, DC_CLR_WDMA_OVER);
++		spin_unlock(&dctrl->irq_lock);
++		return IRQ_HANDLED;
++	}
++	if(likely(irq_flag & DC_WDMA_END)) {
++		static int cnt = 0;
++		cnt++;
++		dbg_irqcnt_inc(dctrl->dbg_irqcnt, wdma_end);
++		dctrl->wback_end = 1;
++		reg_write(dctrl, DC_CLR_ST, DC_CLR_WDMA_END);
++		if(cnt < IRQ_P_N)
++			dev_dbg(dctrl->dev, "DC_WDMA_END irq came here!!!!!!!!!!!!!!");
++
++		wake_up_interruptible(&dctrl->wq);
++		spin_unlock(&dctrl->irq_lock);
++		return IRQ_HANDLED;
++	}
++	if(likely(irq_flag & DC_LAY3_END)) {
++		static int cnt = 0;
++		cnt++;
++		dbg_irqcnt_inc(dctrl->dbg_irqcnt, layer3_end);
++		reg_write(dctrl, DC_CLR_ST, DC_CLR_LAY3_END);
++		if(cnt < IRQ_P_N)
++		dev_dbg(dctrl->dev, "DC_LAY3_END irq came here!!!!!!!!!!!!!!");
++		spin_unlock(&dctrl->irq_lock);
++		return IRQ_HANDLED;
++	}
++	if(likely(irq_flag & DC_LAY2_END)) {
++		static int cnt = 0;
++		cnt++;
++		dbg_irqcnt_inc(dctrl->dbg_irqcnt, layer2_end);
++		reg_write(dctrl, DC_CLR_ST, DC_CLR_LAY2_END);
++		if(cnt < IRQ_P_N)
++		dev_dbg(dctrl->dev, "DC_LAY2_END irq came here!!!!!!!!!!!!!!");
++		spin_unlock(&dctrl->irq_lock);
++		return IRQ_HANDLED;
++	}
++	if(likely(irq_flag & DC_LAY1_END)) {
++		static int cnt = 0;
++		cnt++;
++		dbg_irqcnt_inc(dctrl->dbg_irqcnt, layer1_end);
++		reg_write(dctrl, DC_CLR_ST, DC_CLR_LAY1_END);
++		if(cnt < IRQ_P_N)
++		dev_dbg(dctrl->dev, "DC_LAY1_END irq came here!!!!!!!!!!!!!!");
++		spin_unlock(&dctrl->irq_lock);
++		return IRQ_HANDLED;
++	}
++	if(likely(irq_flag & DC_LAY0_END)) {
++		static int cnt = 0;
++		cnt++;
++		dbg_irqcnt_inc(dctrl->dbg_irqcnt, layer0_end);
++		reg_write(dctrl, DC_CLR_ST, DC_CLR_LAY0_END);
++		if(cnt < IRQ_P_N)
++		dev_dbg(dctrl->dev, "DC_LAY0_END irq came here!!!!!!!!!!!!!!");
++		spin_unlock(&dctrl->irq_lock);
++		return IRQ_HANDLED;
++	}
++	if(likely(irq_flag & DC_CMP_END)) {
++		static int cnt = 0;
++		cnt++;
++		dbg_irqcnt_inc(dctrl->dbg_irqcnt, clr_cmp_end);
++		reg_write(dctrl, DC_CLR_ST, DC_CLR_CMP_END);
++		if(cnt < IRQ_P_N)
++		dev_dbg(dctrl->dev, "DC_CMP_END irq came here!!!!!!!!!!!!!!");
++		spin_unlock(&dctrl->irq_lock);
++		return IRQ_HANDLED;
++	}
++	if(likely(irq_flag & DC_STOP_SRD_ACK)) {
++		static int cnt = 0;
++		cnt++;
++		dbg_irqcnt_inc(dctrl->dbg_irqcnt, stop_wrbk_ack);
++		reg_write(dctrl, DC_CLR_ST, DC_CLR_STOP_SRD_ACK);
++		dctrl->srd_stopped = 1;
++		wake_up_interruptible(&dctrl->wq);
++		if(cnt < IRQ_P_N)
++		dev_dbg(dctrl->dev, "DC_STOP_SRD irq came here!!!!!!!!!!!!!!");
++		spin_unlock(&dctrl->irq_lock);
++		return IRQ_HANDLED;
++	}
++	if(likely(irq_flag & DC_SRD_START)) {
++		static int cnt = 0;
++		cnt++;
++		dbg_irqcnt_inc(dctrl->dbg_irqcnt, srd_start);
++		reg_write(dctrl, DC_CLR_ST, DC_CLR_SRD_START);
++		if(dctrl->rdma_desc_changing) {
++			dctrl->rdma_desc_changing = 0;
++			/*SRD_START
++			 *
++			 * 1. descriptor is done loading, it's save to  update rdma_last_frame descriptor.
++			 *
++			 * 	[rdma_last_frame] --     [current_refresh_frame]
++			 * 		^	   |
++			 *		|----------|
++			 * */
++			dctrl->sreadesc[dctrl->rdma_last_frame]->RdmaNextCfgAddr = dctrl->sreadesc_phys[dctrl->rdma_last_frame];
++			dctrl->rdma_last_frame = dctrl->rdma_changing_frame;
++		}
++		dctrl->set_vsync_value(dctrl->vsync_data);
++		if(cnt < IRQ_P_N)
++		dev_dbg(dctrl->dev, "DC_SRD_START irq came here!!!!!!!!!!!!!!");
++		spin_unlock(&dctrl->irq_lock);
++		return IRQ_HANDLED;
++	}
++	if(likely(irq_flag & DC_SRD_END)) {
++		static int cnt = 0;
++		cnt++;
++		dbg_irqcnt_inc(dctrl->dbg_irqcnt, srd_end);
++		reg_write(dctrl, DC_CLR_ST, DC_CLR_SRD_END);
++		if(cnt < IRQ_P_N)
++		dev_dbg(dctrl->dev, "DC_SRD_END irq came here!!!!!!!!!!!!!!");
++		spin_unlock(&dctrl->irq_lock);
++		return IRQ_HANDLED;
++	}
++	if(likely(irq_flag & DC_CMP_W_SLOW)) {
++		static int cnt = 0;
++		cnt++;
++		dbg_irqcnt_inc(dctrl->dbg_irqcnt, cmp_w_slow);
++		reg_write(dctrl, DC_CLR_ST, DC_CLR_CMP_W_SLOW);
++		if(cnt < IRQ_P_N)
++		dev_dbg(dctrl->dev, "DC_CMP_W_SLOW came here!!!!!!!!!!!!!! DC_ST = 0x%lx cnt = %d",reg_read(dctrl,DC_ST),cnt);
++		if(cnt > 10)
++		reg_write(dctrl, DC_CMPW_PCFG_CTRL, 0 << 10 | 30);
++		spin_unlock(&dctrl->irq_lock);
++		return IRQ_HANDLED;
++	}
++
++	dev_err(dctrl->dev, "DPU irq nothing do, please check!!! DC_ST = 0x%lx\n",reg_read(dctrl,DC_ST));
++	spin_unlock(&dctrl->irq_lock);
++	return IRQ_HANDLED;
++}
++
++static void dctrl_tlb_invalidate_ch(struct dpu_ctrl *dctrl , int ch)
++{
++	int val;
++
++	val = ch & 0xF;
++	/*Invalid for ch layers.*/
++	reg_write(dctrl, DC_TLB_TLBC, val);
++}
++
++static void dctrl_tlb_enable(struct dpu_ctrl *dctrl)
++{
++	struct comp_setup_info *comp_info = &dctrl->comp_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &comp_info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = frm_cfg->lay_cfg;
++	unsigned int glbc, val;
++	int i;
++
++	lay_cfg = frm_cfg->lay_cfg;
++
++	val = reg_read(dctrl, DC_TLB_GLBC);
++	glbc = val;
++
++	for(i = 0; i < DPU_SUPPORT_MAX_LAYERS; i++) {
++		if(lay_cfg[i].lay_en) {
++			if(lay_cfg[i].tlb_en != (glbc>>i & 0x1)) {
++				glbc = lay_cfg[i].tlb_en ?
++					(glbc | (0x1 << i)) : (glbc & ~(0x1 << i));
++			}
++		} else {
++			glbc &= ~(0x1 << i);
++		}
++	}
++	if(val != glbc) {
++		dctrl_tlb_invalidate_ch(dctrl, glbc);	/*invalidate tlb*/
++		if(val > glbc) {			/*When a TLB channel is disable, val is greater than glbc*/
++			dctrl->tlb_disable = true;	/*The TLB should be disable after the current descriptor execution completes*/
++			dctrl->tlb_disable_ch = glbc;
++		} else {
++			reg_write(dctrl, DC_TLB_GLBC, glbc);
++		}
++	}
++}
++
++static void dctrl_tlb_configure(struct dpu_ctrl *dctrl)
++{
++	unsigned int tlbv = 0;
++
++	tlbv |= (1 << DC_CNM_LBIT);
++	tlbv |= (1 << DC_GCN_LBIT);
++
++	/*mutex_lock(dctrl->lock);*/
++	reg_write(dctrl, DC_TLB_TLBV, tlbv);
++	reg_write(dctrl, DC_TLB_TLBA, dctrl->tlba);
++#if 0
++	reg_write(dctrl, DC_TLB_TLBC, DC_CH0_INVLD | DC_CH1_INVLD |
++			DC_CH2_INVLD | DC_CH3_INVLD);
++#endif
++	/*mutex_unlock(dctrl->lock);*/
++}
++
++static void dctrl_tlb_disable(struct dpu_ctrl *dctrl)
++{
++	/*Invalid and disable for all layers.*/
++	reg_write(dctrl, DC_TLB_TLBC, DC_CH0_INVLD | DC_CH1_INVLD |
++			DC_CH2_INVLD | DC_CH3_INVLD);
++	reg_write(dctrl, DC_TLB_GLBC, 0);
++}
++
++static void csc_mode_set(struct dpu_ctrl *dctrl, csc_mode_t mode) {
++	switch(mode) {
++	case CSC_MODE_0:
++		reg_write(dctrl, DC_CSC_MULT_YRV, DC_CSC_MULT_Y_MD0 | DC_CSC_MULT_RV_MD0);
++		reg_write(dctrl, DC_CSC_MULT_GUGV, DC_CSC_MULT_GU_MD0 | DC_CSC_MULT_GV_MD0);
++		reg_write(dctrl, DC_CSC_MULT_BU, DC_CSC_MULT_BU_MD0);
++		reg_write(dctrl, DC_CSC_SUB_YUV, DC_CSC_SUB_Y_MD0 | DC_CSC_SUB_UV_MD0);
++		break;
++	case CSC_MODE_1:
++		reg_write(dctrl, DC_CSC_MULT_YRV, DC_CSC_MULT_Y_MD1 | DC_CSC_MULT_RV_MD1);
++		reg_write(dctrl, DC_CSC_MULT_GUGV, DC_CSC_MULT_GU_MD1 | DC_CSC_MULT_GV_MD1);
++		reg_write(dctrl, DC_CSC_MULT_BU, DC_CSC_MULT_BU_MD1);
++		reg_write(dctrl, DC_CSC_SUB_YUV, DC_CSC_SUB_Y_MD1 | DC_CSC_SUB_UV_MD1);
++		break;
++	case CSC_MODE_2:
++		reg_write(dctrl, DC_CSC_MULT_YRV, DC_CSC_MULT_Y_MD2 | DC_CSC_MULT_RV_MD2);
++		reg_write(dctrl, DC_CSC_MULT_GUGV, DC_CSC_MULT_GU_MD2 | DC_CSC_MULT_GV_MD2);
++		reg_write(dctrl, DC_CSC_MULT_BU, DC_CSC_MULT_BU_MD2);
++		reg_write(dctrl, DC_CSC_SUB_YUV, DC_CSC_SUB_Y_MD2 | DC_CSC_SUB_UV_MD2);
++		break;
++	case CSC_MODE_3:
++		reg_write(dctrl, DC_CSC_MULT_YRV, DC_CSC_MULT_Y_MD3 | DC_CSC_MULT_RV_MD3);
++		reg_write(dctrl, DC_CSC_MULT_GUGV, DC_CSC_MULT_GU_MD3 | DC_CSC_MULT_GV_MD3);
++		reg_write(dctrl, DC_CSC_MULT_BU, DC_CSC_MULT_BU_MD3);
++		reg_write(dctrl, DC_CSC_SUB_YUV, DC_CSC_SUB_Y_MD3 | DC_CSC_SUB_UV_MD3);
++		break;
++	default:
++		dev_err(dctrl->dev, "Set csc mode err!\n");
++		break;
++	}
++}
++
++static void slcd_send_mcu_command(struct dpu_ctrl *dctrl, unsigned long cmd)
++{
++	int count = 10000;
++	uint32_t slcd_cfg;
++
++	while ((reg_read(dctrl, DC_SLCD_ST) & DC_SLCD_ST_BUSY) && count--) {
++		udelay(10);
++	}
++	if (count < 0) {
++		dev_err(dctrl->dev, "SLCDC wait busy state wrong");
++	}
++
++	slcd_cfg = reg_read(dctrl, DC_SLCD_CFG);
++	reg_write(dctrl, DC_SLCD_CFG, (slcd_cfg & ~DC_FMT_EN));
++	reg_write(dctrl, DC_SLCD_REG_IF, DC_SLCD_REG_IF_FLAG_CMD | (cmd & ~DC_SLCD_REG_IF_FLAG_MASK));
++}
++
++static void slcd_send_mcu_data(struct dpu_ctrl *dctrl, unsigned long data)
++{
++	int count = 10000;
++	uint32_t slcd_cfg;
++
++	while ((reg_read(dctrl, DC_SLCD_ST) & DC_SLCD_ST_BUSY) && count--) {
++		udelay(10);
++	}
++	if (count < 0) {
++		dev_err(dctrl->dev, "SLCDC wait busy state wrong");
++	}
++
++	slcd_cfg = reg_read(dctrl, DC_SLCD_CFG);
++	reg_write(dctrl, DC_SLCD_CFG, (slcd_cfg | DC_FMT_EN));
++	reg_write(dctrl, DC_SLCD_REG_IF, DC_SLCD_REG_IF_FLAG_DATA | (data & ~DC_SLCD_REG_IF_FLAG_MASK));
++}
++
++static void slcd_send_mcu_prm(struct dpu_ctrl *dctrl, unsigned long data)
++{
++	int count = 10000;
++	uint32_t slcd_cfg;
++
++	while ((reg_read(dctrl, DC_SLCD_ST) & DC_SLCD_ST_BUSY) && count--) {
++		udelay(10);
++	}
++	if (count < 0) {
++		dev_err(dctrl->dev, "SLCDC wait busy state wrong");
++	}
++
++	slcd_cfg = reg_read(dctrl, DC_SLCD_CFG);
++	reg_write(dctrl, DC_SLCD_CFG, (slcd_cfg & ~DC_FMT_EN));
++	reg_write(dctrl, DC_SLCD_REG_IF, DC_SLCD_REG_IF_FLAG_PRM | (data & ~DC_SLCD_REG_IF_FLAG_MASK));
++}
++
++static void wait_slcd_busy(struct dpu_ctrl *dctrl)
++{
++	int count = 100000;
++	while ((reg_read(dctrl, DC_SLCD_ST) & DC_SLCD_ST_BUSY)
++			&& count--) {
++		udelay(10);
++	}
++	if (count < 0) {
++		dev_err(dctrl->dev,"SLCDC wait busy state wrong");
++	}
++}
++
++static int wait_dc_state(struct dpu_ctrl *dctrl, uint32_t state, uint32_t flag)
++{
++	unsigned long timeout = 20000;
++	while(((!(reg_read(dctrl, DC_ST) & state)) == flag) && timeout) {
++		timeout--;
++		udelay(10);
++	}
++	if(timeout <= 0) {
++		printk("LCD wait state timeout! state = 0x%08x, DC_ST = 0x%08x\n", state, reg_read(dctrl, DC_ST));
++		return -1;
++	}
++
++	return 0;
++}
++
++static void ingenicfb_cmp_start(struct dpu_ctrl *dctrl)
++{
++	reg_write(dctrl, DC_FRM_CFG_CTRL, DC_FRM_START);
++}
++
++static void ingenicfb_slcd_mcu_init(struct dpu_ctrl *dctrl)
++{
++	struct lcd_panel *panel = dctrl->panel;
++	struct smart_config *smart_config;
++	struct smart_lcd_data_table *data_table;
++	uint32_t length_data_table;
++	uint32_t i;
++
++	smart_config = panel->smart_config;
++	if (panel->lcd_type != LCD_TYPE_SLCD || smart_config == NULL)
++		return;
++
++	data_table = smart_config->data_table;
++	length_data_table = smart_config->length_data_table;
++	if(length_data_table && data_table) {
++		for(i = 0; i < length_data_table; i++) {
++			switch (data_table[i].type) {
++			case SMART_CONFIG_DATA:
++				slcd_send_mcu_data(dctrl, data_table[i].value);
++				break;
++			case SMART_CONFIG_PRM:
++				slcd_send_mcu_prm(dctrl, data_table[i].value);
++				break;
++			case SMART_CONFIG_CMD:
++				slcd_send_mcu_command(dctrl, data_table[i].value);
++				break;
++			case SMART_CONFIG_UDELAY:
++				udelay(data_table[i].value);
++				break;
++			default:
++				printk("Unknow SLCD data type\n");
++				break;
++			}
++		}
++	}
++}
++
++static void tft_timing_init(struct dpu_ctrl *dctrl, struct fb_videomode *modes) {
++	uint32_t hps;
++	uint32_t hpe;
++	uint32_t vps;
++	uint32_t vpe;
++	uint32_t hds;
++	uint32_t hde;
++	uint32_t vds;
++	uint32_t vde;
++
++	hps = modes->hsync_len;
++	hpe = hps + modes->left_margin + modes->xres + modes->right_margin;
++	vps = modes->vsync_len;
++	vpe = vps + modes->upper_margin + modes->yres + modes->lower_margin;
++
++	hds = modes->hsync_len + modes->left_margin;
++	hde = hds + modes->xres;
++	vds = modes->vsync_len + modes->upper_margin;
++	vde = vds + modes->yres;
++
++	reg_write(dctrl, DC_TFT_HSYNC,
++		  (hps << DC_HPS_LBIT) |
++		  (hpe << DC_HPE_LBIT));
++	reg_write(dctrl, DC_TFT_VSYNC,
++		  (vps << DC_VPS_LBIT) |
++		  (vpe << DC_VPE_LBIT));
++	reg_write(dctrl, DC_TFT_HDE,
++		  (hds << DC_HDS_LBIT) |
++		  (hde << DC_HDE_LBIT));
++	reg_write(dctrl, DC_TFT_VDE,
++		  (vds << DC_VDS_LBIT) |
++		  (vde << DC_VDE_LBIT));
++}
++
++void tft_cfg_init(struct dpu_ctrl *dctrl, struct tft_config *tft_config) {
++	uint32_t tft_cfg;
++	uint32_t lcd_cgu;
++
++	lcd_cgu = *(volatile unsigned int *)(0xb0000064);
++	if(tft_config->pix_clk_inv) {
++		lcd_cgu |= (0x1 << 26);
++	} else {
++		lcd_cgu &= ~(0x1 << 26);
++	}
++	*(volatile unsigned int *)(0xb0000064) = lcd_cgu;
++
++	tft_cfg = reg_read(dctrl, DC_TFT_CFG);
++	if(tft_config->de_dl) {
++		tft_cfg |= DC_DE_DL;
++	} else {
++		tft_cfg &= ~DC_DE_DL;
++	}
++
++	if(tft_config->sync_dl) {
++		tft_cfg |= DC_SYNC_DL;
++	} else {
++		tft_cfg &= ~DC_SYNC_DL;
++	}
++	if(tft_config->vsync_dl) {
++		tft_cfg |= DC_VSYNC_DL;
++	} else {
++		tft_cfg &= ~DC_VSYNC_DL;
++	}
++
++	tft_cfg &= ~DC_COLOR_EVEN_MASK;
++	switch(tft_config->color_even) {
++	case TFT_LCD_COLOR_EVEN_RGB:
++		tft_cfg |= DC_EVEN_RGB;
++		break;
++	case TFT_LCD_COLOR_EVEN_RBG:
++		tft_cfg |= DC_EVEN_RBG;
++		break;
++	case TFT_LCD_COLOR_EVEN_BGR:
++		tft_cfg |= DC_EVEN_BGR;
++		break;
++	case TFT_LCD_COLOR_EVEN_BRG:
++		tft_cfg |= DC_EVEN_BRG;
++		break;
++	case TFT_LCD_COLOR_EVEN_GBR:
++		tft_cfg |= DC_EVEN_GBR;
++		break;
++	case TFT_LCD_COLOR_EVEN_GRB:
++		tft_cfg |= DC_EVEN_GRB;
++		break;
++	default:
++		printk("err!\n");
++		break;
++	}
++
++	tft_cfg &= ~DC_COLOR_ODD_MASK;
++	switch(tft_config->color_odd) {
++	case TFT_LCD_COLOR_ODD_RGB:
++		tft_cfg |= DC_ODD_RGB;
++		break;
++	case TFT_LCD_COLOR_ODD_RBG:
++		tft_cfg |= DC_ODD_RBG;
++		break;
++	case TFT_LCD_COLOR_ODD_BGR:
++		tft_cfg |= DC_ODD_BGR;
++		break;
++	case TFT_LCD_COLOR_ODD_BRG:
++		tft_cfg |= DC_ODD_BRG;
++		break;
++	case TFT_LCD_COLOR_ODD_GBR:
++		tft_cfg |= DC_ODD_GBR;
++		break;
++	case TFT_LCD_COLOR_ODD_GRB:
++		tft_cfg |= DC_ODD_GRB;
++		break;
++	default:
++		printk("err!\n");
++		break;
++	}
++
++	tft_cfg &= ~DC_MODE_MASK;
++	switch(tft_config->mode) {
++	case TFT_LCD_MODE_PARALLEL_888:
++		tft_cfg |= DC_MODE_PARALLEL_888;
++		break;
++	case TFT_LCD_MODE_PARALLEL_666:
++		tft_cfg |= DC_MODE_PARALLEL_666;
++		break;
++	case TFT_LCD_MODE_PARALLEL_565:
++		tft_cfg |= DC_MODE_PARALLEL_565;
++		break;
++	case TFT_LCD_MODE_SERIAL_RGB:
++		tft_cfg |= DC_MODE_SERIAL_8BIT_RGB;
++		break;
++	case TFT_LCD_MODE_SERIAL_RGBD:
++		tft_cfg |= DC_MODE_SERIAL_8BIT_RGBD;
++		break;
++	default:
++		printk("err!\n");
++		break;
++	}
++	reg_write(dctrl, DC_TFT_CFG, tft_cfg);
++}
++
++static int ingenicfb_tft_set_par(struct dpu_ctrl *dctrl)
++{
++	struct lcd_panel *panel = dctrl->panel;
++	struct lcd_panel_ops *panel_ops;
++	struct fb_videomode *mode = dctrl->active_video_mode;
++
++	panel_ops = panel->ops;
++
++	tft_timing_init(dctrl, mode);
++	tft_cfg_init(dctrl, panel->tft_config);
++	if(panel_ops && panel_ops->enable)
++		panel_ops->enable(panel);
++
++	return 0;
++}
++
++static void slcd_cfg_init(struct dpu_ctrl *dctrl,
++		struct smart_config *smart_config) {
++	uint32_t slcd_cfg;
++
++	if (smart_config == NULL) {
++		dev_info(dctrl->dev, "SLCD use default config\n");
++		return;
++	}
++
++	slcd_cfg = reg_read(dctrl, DC_SLCD_CFG);
++	slcd_cfg &= ~DC_RDY_SWITCH;
++	slcd_cfg &= ~DC_CS_EN;
++
++	if(smart_config->te_switch) {
++		slcd_cfg |= DC_TE_SWITCH;
++
++		if(smart_config->te_dp) {
++			slcd_cfg |= DC_TE_DP;
++		} else {
++			slcd_cfg &= ~DC_TE_DP;
++		}
++		if(smart_config->te_md) {
++			slcd_cfg |= DC_TE_MD;
++		} else {
++			slcd_cfg &= ~DC_TE_MD;
++		}
++		if(smart_config->te_anti_jit) {
++			slcd_cfg |= DC_TE_ANTI_JIT;
++		} else {
++			slcd_cfg &= ~DC_TE_ANTI_JIT;
++		}
++	} else {
++		slcd_cfg &= ~DC_TE_SWITCH;
++	}
++
++	if(smart_config->te_mipi_switch) {
++		slcd_cfg |= DC_TE_MIPI_SWITCH;
++	} else {
++		slcd_cfg &= ~DC_TE_MIPI_SWITCH;
++	}
++
++	if(smart_config->dc_md) {
++		slcd_cfg |= DC_DC_MD;
++	} else {
++		slcd_cfg &= ~DC_DC_MD;
++	}
++
++	if(smart_config->wr_md) {
++		slcd_cfg |= DC_WR_DP;
++	} else {
++		slcd_cfg &= ~DC_WR_DP;
++	}
++
++	slcd_cfg &= ~DC_DBI_TYPE_MASK;
++	switch(smart_config->smart_type){
++	case SMART_LCD_TYPE_8080:
++		slcd_cfg |= DC_DBI_TYPE_B_8080;
++		break;
++	case SMART_LCD_TYPE_6800:
++		slcd_cfg |= DC_DBI_TYPE_A_6800;
++		break;
++	case SMART_LCD_TYPE_SPI_3:
++		slcd_cfg |= DC_DBI_TYPE_C_SPI_3;
++		break;
++	case SMART_LCD_TYPE_SPI_4:
++		slcd_cfg |= DC_DBI_TYPE_C_SPI_4;
++		break;
++	default:
++		printk("err!\n");
++		break;
++	}
++
++	slcd_cfg &= ~DC_DATA_FMT_MASK;
++	switch(smart_config->pix_fmt) {
++	case SMART_LCD_FORMAT_888:
++		slcd_cfg |= DC_DATA_FMT_888;
++		break;
++	case SMART_LCD_FORMAT_666:
++		slcd_cfg |= DC_DATA_FMT_666;
++		break;
++	case SMART_LCD_FORMAT_565:
++		slcd_cfg |= DC_DATA_FMT_565;
++		break;
++	default:
++		printk("err!\n");
++		break;
++	}
++
++	slcd_cfg &= ~DC_DWIDTH_MASK;
++	switch(smart_config->dwidth) {
++	case SMART_LCD_DWIDTH_8_BIT:
++		slcd_cfg |= DC_DWIDTH_8BITS;
++		break;
++	case SMART_LCD_DWIDTH_9_BIT:
++		slcd_cfg |= DC_DWIDTH_9BITS;
++		break;
++	case SMART_LCD_DWIDTH_16_BIT:
++		slcd_cfg |= DC_DWIDTH_16BITS;
++		break;
++	case SMART_LCD_DWIDTH_18_BIT:
++		slcd_cfg |= DC_DWIDTH_18BITS;
++		break;
++	case SMART_LCD_DWIDTH_24_BIT:
++		slcd_cfg |= DC_DWIDTH_24BITS;
++		break;
++	default:
++		printk("err!\n");
++		break;
++	}
++
++	slcd_cfg &= ~DC_CWIDTH_MASK;
++	switch(smart_config->cwidth) {
++	case SMART_LCD_CWIDTH_8_BIT:
++		slcd_cfg |= DC_CWIDTH_8BITS;
++		break;
++	case SMART_LCD_CWIDTH_9_BIT:
++		slcd_cfg |= DC_CWIDTH_9BITS;
++		break;
++	case SMART_LCD_CWIDTH_16_BIT:
++		slcd_cfg |= DC_CWIDTH_16BITS;
++		break;
++	case SMART_LCD_CWIDTH_18_BIT:
++		slcd_cfg |= DC_CWIDTH_18BITS;
++		break;
++	case SMART_LCD_CWIDTH_24_BIT:
++		slcd_cfg |= DC_CWIDTH_24BITS;
++		break;
++	default:
++		printk("err!\n");
++		break;
++	}
++
++	reg_write(dctrl, DC_SLCD_CFG, slcd_cfg);
++
++	return;
++}
++
++static int slcd_timing_init(struct dpu_ctrl *dctrl, struct lcd_panel *panel,
++		struct fb_videomode *mode)
++{
++	uint32_t width = mode->xres;
++	uint32_t height = mode->yres;
++	uint32_t dhtime = 0;
++	uint32_t dltime = 0;
++	uint32_t chtime = 0;
++	uint32_t cltime = 0;
++	uint32_t tah = 0;
++	uint32_t tas = 0;
++	uint32_t slowtime = 0;
++
++	/*frm_size*/
++	reg_write(dctrl, DC_SLCD_FRM_SIZE,
++		  ((width << DC_SLCD_FRM_H_SIZE_LBIT) |
++		   (height << DC_SLCD_FRM_V_SIZE_LBIT)));
++
++	/* wr duty */
++	reg_write(dctrl, DC_SLCD_WR_DUTY,
++		  ((dhtime << DC_DSTIME_LBIT) |
++		   (dltime << DC_DDTIME_LBIT) |
++		   (chtime << DC_CSTIME_LBIT) |
++		   (cltime << DC_CDTIME_LBIT)));
++
++	/* slcd timing */
++	reg_write(dctrl, DC_SLCD_TIMING,
++		  ((tah << DC_TAH_LBIT) |
++		  (tas << DC_TAS_LBIT)));
++
++	/* slow time */
++	reg_write(dctrl, DC_SLCD_SLOW_TIME, slowtime);
++
++	return 0;
++}
++
++static int ingenicfb_slcd_set_par(struct dpu_ctrl *dctrl)
++{
++	struct lcd_panel *panel = dctrl->panel;
++	struct lcd_panel_ops *panel_ops;
++	struct fb_videomode *mode = dctrl->active_video_mode;
++
++	panel_ops = panel->ops;
++
++	slcd_cfg_init(dctrl, panel->smart_config);
++	slcd_timing_init(dctrl, panel, mode);
++
++	if(panel_ops && panel_ops->enable)
++		    panel_ops->enable(panel);
++
++	ingenicfb_slcd_mcu_init(dctrl);
++
++	return 0;
++}
++
++
++
++static void disp_common_init(struct dpu_ctrl *dctrl, struct lcd_panel *panel) {
++	uint32_t disp_com;
++
++	disp_com = reg_read(dctrl, DC_DISP_COM);
++	disp_com &= ~DC_DP_IF_SEL_MASK;
++	if(panel->lcd_type == LCD_TYPE_SLCD) {
++		disp_com |= DC_DISP_COM_SLCD;
++	} else if(panel->lcd_type == LCD_TYPE_MIPI_SLCD) {
++		disp_com |= DC_DISP_COM_MIPI_SLCD;
++	} else {
++		disp_com |= DC_DISP_COM_TFT;
++	}
++	if(panel->dither_enable) {
++		disp_com |= DC_DP_DITHER_EN;
++		disp_com &= ~DC_DP_DITHER_DW_MASK;
++		disp_com |= panel->dither.dither_red
++			     << DC_DP_DITHER_DW_RED_LBIT;
++		disp_com |= panel->dither.dither_green
++			    << DC_DP_DITHER_DW_GREEN_LBIT;
++		disp_com |= panel->dither.dither_blue
++			    << DC_DP_DITHER_DW_BLUE_LBIT;
++	} else {
++		disp_com &= ~DC_DP_DITHER_EN;
++	}
++	reg_write(dctrl, DC_DISP_COM, disp_com);
++
++	/* QOS */
++#if 0
++	reg_write(dctrl, DC_PCFG_RD_CTRL, 7);
++	reg_write(dctrl, DC_PCFG_WR_CTRL, 1);
++	reg_write(dctrl, DC_WDMA_PCFG, 0x1ff << 18 | 0x1f0 << 9 | 0x1e0 << 0);
++	reg_write(dctrl, DC_OFIFO_PCFG, 0x1ff << 18 | 0x1f0 << 9 | 0x1e0 << 0);
++	reg_write(dctrl, DC_CMPW_PCFG_CTRL, 1 << 10);
++#endif
++}
++
++static void common_cfg_init(struct dpu_ctrl *dctrl)
++{
++	unsigned com_cfg = 0;
++
++	com_cfg = reg_read(dctrl, DC_COM_CONFIG);
++	/*Keep COM_CONFIG reg first bit 0 */
++
++	com_cfg &= ~DC_OUT_SEL;
++	if(dctrl->chan == DATA_CH_RDMA) {
++		com_cfg |= DC_OUT_SEL_RDMA;
++	} else {
++		com_cfg |= DC_OUT_SEL_CMP;
++	}
++
++	/* set burst length 32*/
++	com_cfg &= ~DC_BURST_LEN_BDMA_MASK;
++	com_cfg |= DC_BURST_LEN_BDMA_32;
++	com_cfg &= ~DC_BURST_LEN_WDMA_MASK;
++	com_cfg |= DC_BURST_LEN_WDMA_32;
++	com_cfg &= ~DC_BURST_LEN_RDMA_MASK;
++	com_cfg |= DC_BURST_LEN_RDMA_32;
++
++	reg_write(dctrl, DC_COM_CONFIG, com_cfg);
++}
++
++static void ingenic_set_pixclk(struct dpu_ctrl *dctrl, unsigned int pixclock_khz)
++{
++	unsigned long rate, prate;
++	struct clk *clk;
++
++	rate = PICOS2KHZ(pixclock_khz) * 1000;
++	clk = clk_get_parent(dctrl->pclk);
++	prate = clk_get_rate(clk);
++
++	if(prate % rate)
++		rate = prate / (prate / rate) + 1;
++
++	clk_set_rate(dctrl->pclk, rate);
++}
++
++void dump_rdma_desc(struct dpu_ctrl *dctrl)
++{
++	struct ingenicfb_sreadesc **sreadesc;
++	struct rdma_setup_info *rdma_info = &dctrl->rdma_info;
++	int i = 0;
++
++	sreadesc = dctrl->sreadesc;
++	for(i = 0; i < rdma_info->nframes; i++) {
++
++		dev_info(dctrl->dev, "sreadesc[%d]->RdmaNextCfgAddr: 0x%x\n", i, sreadesc[i]->RdmaNextCfgAddr);
++		dev_info(dctrl->dev, "sreadesc[%d]->FrameBufferAddr: 0x%x\n", i, sreadesc[i]->FrameBufferAddr);
++		dev_info(dctrl->dev, "sreadesc[%d]->Stride	: %d\n", i, sreadesc[i]->Stride);
++		dev_info(dctrl->dev, "sreadesc[%d]->ChainCfg	: %x\n", i, sreadesc[i]->ChainCfg.d32);
++		dev_info(dctrl->dev, "sreadesc[%d]->InterruptControl: %x\n", i, sreadesc[i]->InterruptControl.d32);
++	}
++
++}
++/*
++ *
++ *	�置寄LCD控制器, �以�置到寄存器.
++ *
++ *	1. 根�rdma需求的�置信�，�置rdma�述符.
++ *	2. 控制器需�处于�止状�?
++ * */
++int dpu_ctrl_rdma_setup(struct dpu_ctrl *dctrl, struct rdma_setup_info *rdma_info)
++{
++
++	struct ingenicfb_sreadesc **sreadesc;
++	int i = 0;
++
++	/* Init RDMA DESC as continous. */
++	sreadesc = dctrl->sreadesc;
++	for(i = 0; i < rdma_info->nframes; i++) {
++		sreadesc[i]->RdmaNextCfgAddr = dctrl->sreadesc_phys[i];
++		sreadesc[i]->FrameBufferAddr = rdma_info->vidmem_phys[i];
++		sreadesc[i]->Stride = rdma_info->stride;
++		sreadesc[i]->ChainCfg.d32 = 0;
++		sreadesc[i]->ChainCfg.b.format = rdma_info->format;
++		sreadesc[i]->ChainCfg.b.color = rdma_info->color;
++		sreadesc[i]->ChainCfg.b.change_2_cmp = 0;
++		sreadesc[i]->ChainCfg.b.chain_end = !rdma_info->continuous;
++#ifdef TEST_IRQ
++		sreadesc[i]->InterruptControl.d32 = DC_SOS_MSK | DC_EOS_MSK | DC_EOD_MSK;
++#else
++		sreadesc[i]->InterruptControl.d32 = DC_SOS_MSK;
++#endif
++	}
++	sreadesc[0]->RdmaNextCfgAddr = dctrl->sreadesc_phys[0];
++	dctrl->rdma_last_frame = 0;
++
++	memcpy(&dctrl->rdma_info, rdma_info, sizeof(struct rdma_setup_info));
++
++	//dump_rdma_desc(dctrl);
++
++
++
++	return 0;
++}
++
++int dpu_ctrl_rdma_change(struct dpu_ctrl *dctrl, int frame)
++{
++	struct ingenicfb_sreadesc **sreadesc;
++	unsigned long flags;
++
++	sreadesc = dctrl->sreadesc;
++
++	/* TODO: �能改�的内容，包括格�，大�等。这里�是切�frame, 什么时候真正切�还�一定.*/
++
++
++	spin_lock_irqsave(&dctrl->irq_lock, flags);
++
++
++	/*如果此时正处于直通显示, 需��止直通，切�到rdma通�.*/
++
++	if(dctrl->rdma_desc_changing) {
++		dev_warn(dctrl->dev, "[rdma] last frame [%d] still in changing!\n", dctrl->rdma_changing_frame);
++		dctrl_tlb_invalidate_ch(dctrl, DC_ALL_INVLD);
++	}
++
++	sreadesc[dctrl->rdma_last_frame]->RdmaNextCfgAddr = dctrl->sreadesc_phys[frame];
++
++	dctrl->rdma_changing_frame = frame;
++	dctrl->rdma_desc_changing = 1;
++
++	spin_unlock_irqrestore(&dctrl->irq_lock, flags);
++
++	return 0;
++}
++
++int dpu_ctrl_rdma_start(struct dpu_ctrl *dctrl)
++{
++	reg_write(dctrl, DC_RDMA_CHAIN_ADDR, dctrl->sreadesc_phys[0]);
++	reg_write(dctrl, DC_RDMA_CHAIN_CTRL, DC_RDMA_START);
++
++	//dump_rdma_desc_reg(dctrl);
++
++	return 0;
++}
++
++int dpu_ctrl_rdma_stop(struct dpu_ctrl *dctrl, enum stop_mode mode)
++{
++	int ret = 0;
++
++	if(mode == QCK_STOP) {
++		reg_write(dctrl, DC_CTRL, DC_QCK_STP_RDMA);
++		wait_dc_state(dctrl, DC_SRD_WORKING, 0);
++	} else {
++		dctrl->srd_stopped = 0;
++		reg_write(dctrl, DC_CTRL, DC_GEN_STP_RDMA);
++		dev_info(dctrl->dev, "stopping rdma ...\n");
++		ret = wait_event_interruptible_timeout(dctrl->wq,
++				dctrl->srd_stopped == 1,msecs_to_jiffies(1000/dctrl->active_video_mode->refresh + 3));
++		if((ret == 0) && reg_read(dctrl, DC_ST) & DC_SRD_WORKING) {
++			dev_err(dctrl->dev, "dpu rdma wait gen stop timeout!!!\n");
++			dump_lcdc_registers(dctrl);
++		}
++	}
++
++	return 0;
++}
++
++static void dump_frm_desc(struct ingenicfb_framedesc *framedesc, int index)
++{
++	printk("-------User Frame Descriptor index[%d]-----\n", index);
++	printk("FramedescAddr:	    0x%x\n",(uint32_t)framedesc);
++	printk("FrameNextCfgAddr:   0x%x\n",framedesc->FrameNextCfgAddr);
++	printk("FrameSize:          0x%x\n",framedesc->FrameSize.d32);
++	printk("FrameCtrl:          0x%x\n",framedesc->FrameCtrl.d32);
++	printk("WritebackAddr:	    0x%x\n",framedesc->WritebackAddr);
++	printk("WritebackStride:    0X%x\n",framedesc->WritebackStride);
++	printk("Layer0CfgAddr:      0x%x\n",framedesc->Layer0CfgAddr);
++	printk("Layer1CfgAddr:      0x%x\n",framedesc->Layer1CfgAddr);
++	printk("Layer2CfgAddr:      0x%x\n",framedesc->Layer2CfgAddr);
++	printk("Layer3CfgAddr:      0x%x\n",framedesc->Layer3CfgAddr);
++	printk("LayerCfgEn:	    0x%x\n",framedesc->LayCfgEn.d32);
++	printk("InterruptControl:   0x%x\n",framedesc->InterruptControl.d32);
++	printk("-------User Frame Descriptor index[%d]-----\n", index);
++}
++
++static void dump_layer_desc(struct ingenicfb_layerdesc *layerdesc, int row, int col)
++{
++	printk("------User layer Descriptor index[%d][%d]------\n", row, col);
++	printk("LayerdescAddr:	    0x%x\n",(uint32_t)layerdesc);
++	printk("LayerSize:          0x%x\n",layerdesc->LayerSize.d32);
++	printk("LayerCfg:           0x%x\n",layerdesc->LayerCfg.d32);
++	printk("LayerBufferAddr:    0x%x\n",layerdesc->LayerBufferAddr);
++	printk("LayerScale:         0x%x\n",layerdesc->LayerScale.d32);
++	printk("LayerResizeCoef_X:  0x%x\n",layerdesc->layerresizecoef_x);
++	printk("LayerResizeCoef_Y:  0x%x\n",layerdesc->layerresizecoef_y);
++	printk("LayerPos:           0x%x\n",layerdesc->LayerPos.d32);
++	printk("LayerStride:        0x%x\n",layerdesc->LayerStride);
++	printk("Layer_UV_addr:	    0x%x\n",layerdesc->UVBufferAddr);
++	printk("Layer_UV_stride:    0x%x\n",layerdesc->UVStride);
++	printk("------User layer Descriptor index[%d][%d]------\n", row, col);
++}
++
++void dump_lay_cfg(struct ingenicfb_lay_cfg * lay_cfg, int index)
++{
++	printk("------User disp set index[%d]------\n", index);
++	printk("lay_en:		   0x%x\n",lay_cfg->lay_en);
++	printk("tlb_en:		   0x%x\n",lay_cfg->tlb_en);
++	printk("lay_scale_en:	   0x%x\n",lay_cfg->lay_scale_en);
++	printk("lay_z_order:	   0x%x\n",lay_cfg->lay_z_order);
++	printk("source_w:	   0x%x\n",lay_cfg->source_w);
++	printk("source_h:	   0x%x\n",lay_cfg->source_h);
++	printk("disp_pos_x:	   0x%x\n",lay_cfg->disp_pos_x);
++	printk("disp_pos_y:	   0x%x\n",lay_cfg->disp_pos_y);
++	printk("scale_w:	   0x%x\n",lay_cfg->scale_w);
++	printk("scale_h:	   0x%x\n",lay_cfg->scale_h);
++	printk("g_alpha_en:	   0x%x\n",lay_cfg->g_alpha_en);
++	printk("g_alpha_val:	   0x%x\n",lay_cfg->g_alpha_val);
++	printk("color:		   0x%x\n",lay_cfg->color);
++	printk("format:		   0x%x\n",lay_cfg->format);
++	printk("stride:		   0x%x\n",lay_cfg->stride);
++	printk("addr[0]:	   0x%x\n",lay_cfg->addr[0]);
++	printk("addr[1]:	   0x%x\n",lay_cfg->addr[1]);
++	printk("addr[2]:	   0x%x\n",lay_cfg->addr[2]);
++
++	printk("------User disp set index[%d]------\n", index);
++}
++
++static void dump_comp_info(struct comp_setup_info *comp_info)
++{
++	struct ingenicfb_frm_cfg *frm_cfg = &comp_info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = frm_cfg->lay_cfg;
++	struct wback_cfg *wback_info	= &frm_cfg->wback_info;
++	int i;
++
++	printk("\n\n");
++	printk("width: %d, height: %d\n",frm_cfg->width, frm_cfg->height);
++
++	printk("wback_info: en:%d  dither_en:%d  fmt:%d  stride:%d  addr:%08x \n",wback_info->en, wback_info->dither_en, wback_info->fmt, wback_info->stride, wback_info->addr);
++
++	for(i = 0; i < DPU_SUPPORT_MAX_LAYERS; i++) {
++		printk("####################lay_cfg info %d ###################\n", i);
++		printk("lay_en:%d  tlb_en:%d \n", lay_cfg[i].lay_en, lay_cfg[i].tlb_en);
++		printk("source_w:%d  source_h:%d disp_pos_x:%d disp_pos_y:%d \n", lay_cfg[i].source_w, lay_cfg[i].source_h, lay_cfg[i].disp_pos_x, lay_cfg[i].disp_pos_y);
++		printk("g_alpha_en:%d g_alpha_val:%d color:%d format:%d stride:%d \n", lay_cfg[i].g_alpha_en, lay_cfg[i].g_alpha_val, lay_cfg[i].color, lay_cfg[i].format, lay_cfg[i].stride);
++		printk("scale_w:%d scale_h:%d addr:%08x uv_addr:%08x uv_stride:%d\n",lay_cfg[i].scale_w, lay_cfg[i].scale_h, lay_cfg[i].addr, lay_cfg[i].uv_addr, lay_cfg[i].uv_stride);
++
++		printk("\n");
++	}
++	printk("\n\n");
++}
++
++void dump_comp_desc(struct dpu_ctrl *dctrl)
++{
++	int i, j;
++	for(i = 0; i < DPU_COMP_MAX_FRAMEDESC; i++) {
++		for(j = 0; j < DPU_SUPPORT_MAX_LAYERS; j++) {
++			dump_layer_desc(dctrl->layerdesc[i][j], i, j);
++		}
++		dump_frm_desc(dctrl->framedesc[i], i);
++	}
++}
++
++static int dpu_comp_framedesc_setup(struct dpu_ctrl *dctrl, struct comp_setup_info *comp_info)
++{
++	struct ingenicfb_framedesc **framedesc;
++	struct ingenicfb_frm_cfg *frm_cfg = &comp_info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = frm_cfg->lay_cfg;
++	struct wback_cfg *wback_info	= &frm_cfg->wback_info;
++	struct fb_videomode *mode = dctrl->active_video_mode;
++	int i = 0;
++	int next_frame = 0;
++
++	if(wback_info->en) {
++		comp_info->out_mode = COMP_WRITE_BACK;
++	} else {
++		comp_info->out_mode = COMP_DIRECT_OUT;
++		frm_cfg->width = mode->xres;
++		frm_cfg->height = mode->yres;
++	}
++
++	if(dctrl->comp_stopped) {
++		/*如果composer没有�动，则�始化为第0帧.*/
++		dctrl->comp_next_frame = 0;
++		next_frame = 0;
++	} else {
++
++		/*如果composer�动，�次setup的修改的是下一个待刷新的帧�述符.*/
++		dctrl->comp_next_frame += 1;
++		dctrl->comp_next_frame %= DPU_COMP_MAX_FRAMEDESC;
++
++		next_frame = dctrl->comp_next_frame;
++	}
++
++	/*update framedesc*/
++
++	framedesc = dctrl->framedesc;
++
++	/*构建链接自己的帧�述符.*/
++
++	framedesc[next_frame]->FrameNextCfgAddr = dctrl->framedesc_phys[next_frame];
++	framedesc[next_frame]->FrameSize.d32 = 0;
++	framedesc[next_frame]->FrameSize.b.width = frm_cfg->width;
++	framedesc[next_frame]->FrameSize.b.height = frm_cfg->height;
++	framedesc[next_frame]->FrameCtrl.d32 = 0;
++	framedesc[next_frame]->FrameCtrl.b.stop = comp_info->out_mode == COMP_DIRECT_OUT ? 0 : 1; //当直接显示时，帧�述符��止.
++	framedesc[next_frame]->FrameCtrl.b.wb_en = !!wback_info->en;
++	framedesc[next_frame]->FrameCtrl.b.direct_en = comp_info->out_mode == COMP_DIRECT_OUT ? 1 : 0;
++	framedesc[next_frame]->FrameCtrl.b.change_2_rdma = 0;
++	framedesc[next_frame]->FrameCtrl.b.wb_dither_en = 0;
++	framedesc[next_frame]->FrameCtrl.b.wb_dither_auto = 0;
++	framedesc[next_frame]->FrameCtrl.b.wb_dither_auto = 0;
++	framedesc[next_frame]->FrameCtrl.b.wb_dither_b_dw = 0;
++	framedesc[next_frame]->FrameCtrl.b.wb_dither_g_dw = 0;
++	framedesc[next_frame]->FrameCtrl.b.wb_dither_r_dw = 0;
++
++	framedesc[next_frame]->WritebackAddr = wback_info->addr;
++	framedesc[next_frame]->WritebackStride = wback_info->stride;
++	framedesc[next_frame]->FrameCtrl.b.wb_format = wback_info->fmt;
++	framedesc[next_frame]->Layer0CfgAddr = dctrl->layerdesc_phys[next_frame][0];
++	framedesc[next_frame]->Layer1CfgAddr = dctrl->layerdesc_phys[next_frame][1];
++	framedesc[next_frame]->Layer2CfgAddr = dctrl->layerdesc_phys[next_frame][2];
++	framedesc[next_frame]->Layer3CfgAddr = dctrl->layerdesc_phys[next_frame][3];
++	framedesc[next_frame]->LayCfgEn.d32 = 0;
++	framedesc[next_frame]->LayCfgEn.b.lay0_scl_en = lay_cfg[0].lay_scale_en;
++	framedesc[next_frame]->LayCfgEn.b.lay1_scl_en = lay_cfg[1].lay_scale_en;
++	framedesc[next_frame]->LayCfgEn.b.lay2_scl_en = lay_cfg[2].lay_scale_en;
++	framedesc[next_frame]->LayCfgEn.b.lay3_scl_en = lay_cfg[3].lay_scale_en;
++	framedesc[next_frame]->LayCfgEn.b.lay0_en = lay_cfg[0].lay_en;
++	framedesc[next_frame]->LayCfgEn.b.lay1_en = lay_cfg[1].lay_en;
++	framedesc[next_frame]->LayCfgEn.b.lay2_en = lay_cfg[2].lay_en;
++	framedesc[next_frame]->LayCfgEn.b.lay3_en = lay_cfg[3].lay_en;
++	framedesc[next_frame]->LayCfgEn.b.lay0_z_order = lay_cfg[0].lay_z_order;
++	framedesc[next_frame]->LayCfgEn.b.lay1_z_order = lay_cfg[1].lay_z_order;
++	framedesc[next_frame]->LayCfgEn.b.lay2_z_order = lay_cfg[2].lay_z_order;
++	framedesc[next_frame]->LayCfgEn.b.lay3_z_order = lay_cfg[3].lay_z_order;
++
++	/*使能写回功能，则认为是需�开�EOW中断.*/
++	if((comp_info->out_mode == COMP_WRITE_BACK) && (wback_info->en == 1)) {
++		framedesc[next_frame]->InterruptControl.d32 = DC_EOW_MSK;
++	} else {
++		framedesc[next_frame]->InterruptControl.d32 = DC_SOC_MSK;
++	}
++	/*
++#ifndef TEST_IRQ
++framedesc[i]->InterruptControl.d32 = DC_SOC_MSK;
++#else
++framedesc[i]->InterruptControl.d32 = DC_SOC_MSK | DC_EOD_MSK | DC_EOW_MSK | DC_EOC_MSK;
++#endif
++*/
++
++	return 0;
++}
++
++static int dpu_comp_layerdesc_setup(struct dpu_ctrl *dctrl, struct comp_setup_info *comp_info)
++{
++	struct ingenicfb_frm_cfg *frm_cfg = &comp_info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = frm_cfg->lay_cfg;
++	struct wback_cfg *wback_info	= &frm_cfg->wback_info;
++	int j = 0;
++
++	unsigned int next_frame = dctrl->comp_next_frame;
++
++	for(j = 0; j < DPU_SUPPORT_MAX_LAYERS; j++) {
++		if(!lay_cfg[j].lay_en) {
++			dctrl->layerdesc[next_frame][j]->LayerScale.b.target_width = lay_cfg[j].scale_w = 0;
++			dctrl->layerdesc[next_frame][j]->LayerScale.b.target_height = lay_cfg[j].scale_h = 0;
++			dctrl->layerdesc[next_frame][j]->layerresizecoef_x = 0;
++			dctrl->layerdesc[next_frame][j]->layerresizecoef_y = 0;
++			lay_cfg[j].lay_scale_en = 0;
++			lay_cfg[j].tlb_en = 0;
++			continue;
++		}
++
++		dctrl->layerdesc[next_frame][j]->LayerSize.d32 		= 0;
++		dctrl->layerdesc[next_frame][j]->LayerSize.b.width 	= lay_cfg[j].source_w;
++		dctrl->layerdesc[next_frame][j]->LayerSize.b.height 	= lay_cfg[j].source_h;
++		dctrl->layerdesc[next_frame][j]->LayerPos.d32 		= 0;
++		dctrl->layerdesc[next_frame][j]->LayerPos.b.x_pos 	= lay_cfg[j].disp_pos_x;
++		dctrl->layerdesc[next_frame][j]->LayerPos.b.y_pos 	= lay_cfg[j].disp_pos_y;
++		dctrl->layerdesc[next_frame][j]->LayerCfg.d32 		= 0;
++		dctrl->layerdesc[next_frame][j]->LayerCfg.b.g_alpha_en 	= lay_cfg[j].g_alpha_en;
++		dctrl->layerdesc[next_frame][j]->LayerCfg.b.g_alpha 	= lay_cfg[j].g_alpha_val;
++		dctrl->layerdesc[next_frame][j]->LayerCfg.b.color 	= lay_cfg[j].color;
++		dctrl->layerdesc[next_frame][j]->LayerCfg.b.domain_multi = 1;
++		dctrl->layerdesc[next_frame][j]->LayerCfg.b.format 	= lay_cfg[j].format;
++		dctrl->layerdesc[next_frame][j]->LayerCfg.b.sharpl 	= 0;
++		dctrl->layerdesc[next_frame][j]->LayerStride 		= lay_cfg[j].stride;
++		dctrl->layerdesc[next_frame][j]->LayerScale.d32 	= 0;
++		if(lay_cfg[j].lay_scale_en) {
++			dctrl->layerdesc[next_frame][j]->LayerScale.b.target_width 	= lay_cfg[j].scale_w;
++			dctrl->layerdesc[next_frame][j]->LayerScale.b.target_height 	= lay_cfg[j].scale_h;
++			dctrl->layerdesc[next_frame][j]->layerresizecoef_x 		= (512 * lay_cfg[j].source_w) / lay_cfg[j].scale_w;
++			dctrl->layerdesc[next_frame][j]->layerresizecoef_y 		= (512 * lay_cfg[j].source_h) / lay_cfg[j].scale_h;
++		} else {
++			dctrl->layerdesc[next_frame][j]->LayerScale.b.target_width 	= 0;
++			dctrl->layerdesc[next_frame][j]->LayerScale.b.target_height 	= 0;
++			dctrl->layerdesc[next_frame][j]->layerresizecoef_x 		= 0;
++			dctrl->layerdesc[next_frame][j]->layerresizecoef_y 		= 0;
++		}
++
++		dctrl->layerdesc[next_frame][j]->LayerBufferAddr 				= lay_cfg[j].addr[0];
++		dctrl->layerdesc[next_frame][j]->UVBufferAddr 					= lay_cfg[j].uv_addr[0];
++		dctrl->layerdesc[next_frame][j]->UVStride 					= lay_cfg[j].uv_stride;
++	}
++
++	return 0;
++}
++
++int dpu_ctrl_comp_setup(struct dpu_ctrl *dctrl, struct comp_setup_info *comp_info)
++{
++	int ret = 0;
++
++	/*调用者需���comp_info的�法性.*/
++//	dump_comp_info(comp_info);
++
++	ret = dpu_comp_framedesc_setup(dctrl, comp_info);
++	ret = dpu_comp_layerdesc_setup(dctrl, comp_info);
++
++	//dump_comp_desc(dctrl);
++
++	memcpy(&dctrl->comp_info, comp_info, sizeof(struct comp_setup_info));
++
++	/*Only Composer Need CSC settings.*/
++	dctrl->csc_mode = CSC_MODE_1;
++	csc_mode_set(dctrl, dctrl->csc_mode);
++
++	return ret;
++}
++
++static inline long timeval_sub_to_us(struct timespec64 lhs,
++				struct timespec64 rhs)
++{
++	long sec, nsec;
++	sec = lhs.tv_sec - rhs.tv_sec;
++	nsec = lhs.tv_nsec - rhs.tv_nsec;
++
++	return (sec*1000000 + nsec/1000);
++}
++
++
++static int dpu_ctrl_comp_start_block(struct dpu_ctrl *dctrl)
++{
++	//Mutex lock, this function used for comp writeback, oneshot.
++	struct comp_setup_info *comp_info = &dctrl->comp_info;
++	int ret = 0;
++
++	struct timespec64 time_start, time_end;
++	unsigned int interval_in_us;
++	unsigned int interval_in_ms;
++
++
++	dctrl->wback_end = 0;
++
++	ktime_get_real_ts64(&time_start);
++
++	reg_write(dctrl, DC_FRM_CFG_CTRL, DC_FRM_START);
++
++	ret = wait_event_interruptible_timeout(dctrl->wq, dctrl->wback_end == 1, msecs_to_jiffies(3000));
++	if(ret == 0) {
++		dev_err(dctrl->dev, "wait for wback timeout!\n");
++		return -ETIMEDOUT;
++	}
++
++	ktime_get_real_ts64(&time_end);
++	interval_in_us = timeval_sub_to_us(time_end, time_start);
++	interval_in_ms = interval_in_us / 1000;
++
++//	printk("composer cost %d us -- %dms\n", interval_in_us, interval_in_ms);
++
++
++	return 0;
++}
++
++static int dpu_ctrl_comp_start_nonblock(struct dpu_ctrl *dctrl)
++{
++	//Mutex lock. this function used for comp direct output.
++
++	if(!(reg_read(dctrl, DC_ST) & DC_DIRECT_WORKING)) {
++		reg_write(dctrl, DC_FRM_CFG_CTRL, DC_FRM_START);
++		dctrl->comp_stopped = 0;
++	}
++
++	return 0;
++}
++
++static void dctrl_flush_cache(struct dpu_ctrl *dctrl)
++{
++	struct comp_setup_info *comp_info = &dctrl->comp_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &comp_info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = frm_cfg->lay_cfg;
++	unsigned int next_frame = dctrl->comp_next_frame;
++	unsigned int buf_size;
++	int i = 0;
++
++	/* TODO:
++	 * 如果使用的是tlb方�，则�次在更新�述符时，需�flush cache, ��dpu��的是正确的数�.
++	 * */
++
++	for(i = 0; i < DPU_SUPPORT_MAX_LAYERS; i++) {
++
++		if((!lay_cfg[i].lay_en) || (!lay_cfg[i].tlb_en)) {
++			continue;
++		}
++
++		if(lay_cfg[i].format == LAYER_CFG_FORMAT_NV12 ||
++				lay_cfg[i].format == LAYER_CFG_FORMAT_NV21) {
++			unsigned int y_size = 0;
++			unsigned int uv_size = 0;
++
++			y_size = lay_cfg[i].stride * lay_cfg[i].source_h;
++			uv_size = lay_cfg[i].stride * lay_cfg[i].source_h / 2;
++
++			/* Y */
++			if(lay_cfg[i].addr[0]) {
++				dma_cache_wback_inv(lay_cfg[i].addr[0], y_size);
++			}
++
++			/* UV */
++			if(lay_cfg[i].uv_addr[0]) {
++				dma_cache_wback_inv(lay_cfg[i].uv_addr[0], uv_size);
++			}
++
++		} else if(lay_cfg[i].format == LAYER_CFG_FORMAT_RGB888 ||
++				lay_cfg[i].format == LAYER_CFG_FORMAT_ARGB8888) {
++			/*RGB888/ARGB888*/
++			unsigned int buf_size = 0;
++			buf_size = lay_cfg[i].stride * lay_cfg[i].source_h * 4;
++			dma_cache_wback_inv(lay_cfg[i].addr[0], buf_size);
++		} else {
++
++			/*RGB565/RGB555.*/
++			unsigned int buf_size = 0;
++			buf_size = lay_cfg[i].stride * lay_cfg[i].source_h * 2;
++			dma_cache_wback_inv(lay_cfg[i].addr[0], buf_size);
++		}
++	}
++}
++
++int dpu_ctrl_comp_start(struct dpu_ctrl *dctrl, int block)
++{
++	struct comp_setup_info *comp_info = &dctrl->comp_info;
++	int ret = 0;
++	unsigned int com_cfg = 0;
++	unsigned int curr_frame_addr = 0;
++	unsigned int curr_frame_site = 0;
++
++	dctrl_tlb_configure(dctrl);
++	dctrl_tlb_enable(dctrl);
++
++	/*Flush cache if tlb en.*/
++	dctrl_flush_cache(dctrl);
++
++
++	if(0) { //DEBUG.
++		curr_frame_addr = reg_read(dctrl, DC_FRM_CFG_ADDR);
++		curr_frame_site = reg_read(dctrl, DC_FRM_CHAIN_SITE);
++		if(curr_frame_addr != curr_frame_site) {
++			dev_err(dctrl->dev, "--------error, framedesc overflow!!!curr_frame_addr: %x , curr_frame_site: %x\n", curr_frame_addr, curr_frame_site);
++		}
++	}
++
++	/*comp_next_frame, 等待硬件更新的buffer.*/
++	dctrl->comp_last_framedesc = dctrl->framedesc_phys[dctrl->comp_next_frame];
++	dctrl->comp_last_frame = dctrl->comp_next_frame;
++
++	reg_write(dctrl, DC_FRM_CFG_ADDR, dctrl->framedesc_phys[dctrl->comp_next_frame]);
++	/*等待上一帧�述符确实被硬件读�，�继续更新下一帧�述符.*/
++
++	if(!dctrl->comp_stopped) {
++		ret = wait_event_interruptible_timeout(dctrl->wq,
++				(dctrl->comp_hw_framedesc == dctrl->comp_last_framedesc), msecs_to_jiffies(400)); //40ms 25FPS �论上肯定能够更新完��述符.
++
++		if(ret == 0) {
++			dctrl_tlb_invalidate_ch(dctrl, DC_ALL_INVLD);
++			dev_err(dctrl->dev, "wait fo dpu update comp framdesc timed out, dctrl->comp_hw_framedesc: %x, dctrl->comp_last_framedesc: %x\n",
++					dctrl->comp_hw_framedesc, dctrl->comp_last_framedesc);
++		} else {
++#if 0
++			dev_err(dctrl->dev, "last_frame: %d dctrl->comp_hw_framedesc: %x, dctrl->comp_last_framedesc: %x, LayerBufferAddr: %x\n",
++					dctrl->comp_last_frame, dctrl->comp_hw_framedesc, dctrl->comp_last_framedesc, dctrl->layerdesc[dctrl->comp_last_frame][2]->LayerBufferAddr);
++#endif
++
++		}
++	}
++
++	if(dctrl->tlb_disable == true) {
++		reg_write(dctrl, DC_TLB_GLBC, dctrl->tlb_disable_ch);
++		dctrl->tlb_disable = false;
++	}
++
++	dctrl->comp_fps++;
++
++	/*切�到comp 之�，先�止rdma.*/
++	if((comp_info->out_mode == COMP_DIRECT_OUT) && (dctrl->chan == DATA_CH_RDMA)) {
++		/*stop rdma ??*/
++		if(reg_read(dctrl, DC_ST) & DC_SRD_WORKING) {
++			dpu_ctrl_rdma_stop(dctrl, GEN_STOP);
++		}
++	}
++
++	/* �有当comp�止的时候，�需��新�动��.
++	 * �始化时，comp_stopped = 1.
++	 * �动一次之�, comp_stopped = 0.
++	 *
++	 * 当处于�直通的时候
++	 * */
++	if(block && comp_info->out_mode == COMP_WRITE_BACK) {
++		ret = dpu_ctrl_comp_start_block(dctrl);
++	} else {
++		ret = dpu_ctrl_comp_start_nonblock(dctrl);
++	}
++
++
++	/* 切�显示数�通路到composer */
++	if((comp_info->out_mode == COMP_DIRECT_OUT) && (dctrl->chan == DATA_CH_RDMA)) {
++
++		com_cfg = reg_read(dctrl, DC_COM_CONFIG);
++		com_cfg &= ~DC_OUT_SEL;
++
++		com_cfg |= DC_OUT_SEL_CMP;
++		reg_write(dctrl, DC_COM_CONFIG, com_cfg);
++		dctrl->chan = DATA_CH_COMP;
++	}
++
++	//dump_lcdc_registers(dctrl);
++
++	return ret;
++}
++
++int dpu_ctrl_comp_stop(struct dpu_ctrl *dctrl, enum stop_mode mode)
++{
++	struct ingenicfb_framedesc **framedesc = dctrl->framedesc;
++	int ret = 0;
++	int i = 0;
++
++	if(!dctrl->support_comp) {
++		return 0;
++	}
++
++	for(i = 0; i < DPU_COMP_MAX_FRAMEDESC; i++) {
++		/*当comp stop时，将�述符的LayCfgEn 都设置为0, 防止TLB没有�始化时出错.*/
++		framedesc[i]->LayCfgEn.d32 = 0;
++	}
++
++	if(mode == QCK_STOP) {
++		reg_write(dctrl, DC_CTRL, DC_QCK_STP_CMP);
++		wait_dc_state(dctrl, DC_DIRECT_WORKING | DC_WRBK_WORKING, 0);
++		dctrl->comp_stopped = 1;
++	} else {
++		dctrl->comp_stopped = 0;
++		reg_write(dctrl, DC_CTRL, DC_GEN_STP_CMP);
++		ret = wait_event_interruptible_timeout(dctrl->wq,
++				dctrl->comp_stopped == 1,msecs_to_jiffies(3000));
++		if(ret == 0) {
++			dev_err(dctrl->dev, "dpu composer gen stop timeout!!!\n");
++		}
++	}
++
++	dctrl_tlb_disable(dctrl);
++	dctrl->comp_fps = 0;
++
++	return ret;
++}
++
++
++/* 1. slcd/tft 接��始化.
++ * 2. 设置pixclk.
++ * */
++int dpu_ctrl_setup(struct dpu_ctrl *dctrl)
++{
++	struct lcd_panel *panel = dctrl->panel;
++	unsigned int intc = 0;
++	int ret = 0;
++
++	disp_common_init(dctrl, dctrl->panel);
++	common_cfg_init(dctrl);
++
++	reg_write(dctrl, DC_CLR_ST, 0x01FFFFFE);
++
++	switch (panel->lcd_type) {
++		case LCD_TYPE_TFT:
++			ingenicfb_tft_set_par(dctrl);
++			break;
++		case LCD_TYPE_MIPI_TFT:
++			ingenicfb_tft_set_par(dctrl);
++			dctrl->dsi->master_ops->mode_cfg(dctrl->dsi, 1);
++			break;
++		case LCD_TYPE_SLCD:
++			ingenicfb_slcd_set_par(dctrl);
++			break;
++		case LCD_TYPE_MIPI_SLCD:
++			ingenicfb_slcd_set_par(dctrl);
++			dctrl->dsi->master_ops->mode_cfg(dctrl->dsi, 0);
++			break;
++	}
++
++        /*       disp end      gen_stop    tft_under    frm_start    frm_end     wback over  GEN_STOP_SRD*/
++//	intc = DC_EOD_MSK | DC_SDA_MSK | DC_UOT_MSK | DC_SOC_MSK | DC_EOF_MSK | DC_OOW_MSK | DC_SSA_MSK;
++	intc = DC_EOD_MSK | DC_SDA_MSK | DC_UOT_MSK | DC_SOC_MSK | DC_OOW_MSK | DC_EOW_MSK | DC_SOS_MSK | DC_STOP_SRD_ACK;
++	reg_write(dctrl, DC_INTC, intc);
++
++
++	/* tlb init disabled. */
++	dctrl_tlb_configure(dctrl);
++
++
++	return ret;
++}
++
++
++/* 申请和释放rdma的�述符. */
++static int dpu_ctrl_alloc_rdma_desc(struct dpu_ctrl *dctrl)
++{
++	unsigned int size = 0;
++	unsigned int alloc_size = 0;
++	dma_addr_t addr_phy;
++	uint8_t * addr = 0;
++	int i = 0;
++
++	dctrl->sreadesc_size = 0;
++	size = sizeof(struct ingenicfb_sreadesc);
++
++	size = ALIGN(size, DESC_ALIGN);
++	alloc_size = size * CONFIG_FB_INGENIC_NR_FRAMES;
++	addr = dma_alloc_coherent(dctrl->dev, alloc_size, &addr_phy, GFP_KERNEL);
++
++	if(IS_ERR_OR_NULL(addr)) {
++		dev_err(dctrl->dev, "Failed to alloc dma desc for rdma!\n");
++		return -ENOMEM;
++	}
++
++	for(i = 0; i < CONFIG_FB_INGENIC_NR_FRAMES; i++) {
++		dctrl->sreadesc[i] =
++			(struct ingenicfb_sreadesc *)(addr + i * size);
++		dctrl->sreadesc_phys[i] = addr_phy + i * size;
++	}
++
++	dctrl->sreadesc_size = alloc_size;
++
++	dev_info(dctrl->dev, "rdma_desc @ 0x%x size: %d", dctrl->sreadesc[0], dctrl->sreadesc_size);
++
++	return 0;
++}
++
++static int dpu_ctrl_release_rdma_desc(struct dpu_ctrl *dctrl)
++{
++	if(dctrl->sreadesc_size) {
++		dma_free_coherent(dctrl->dev, dctrl->sreadesc_size, dctrl->sreadesc[0], dctrl->sreadesc_phys[0]);
++		dctrl->sreadesc_size = 0;
++	}
++
++	return 0;
++}
++
++/* 申请和释放composer的�述符
++ * dpu控制器所拥有的�述符是固定的，当�动时，�个�述的内容需�由外部填充.
++ * 例如:
++ * 	1. 当用户调用composer进行��时，�以先修改上层的内容，最���馈到实际的buffer.
++ * */
++static int dpu_ctrl_alloc_comp_desc(struct dpu_ctrl *dctrl)
++{
++	unsigned int size = 0;
++	unsigned int alloc_size = 0;
++	dma_addr_t addr_phy = 0;
++	uint8_t * addr = 0;
++	int ret = 0;
++	int i = 0, j = 0;
++
++	/*Composer Frame desc. */
++	dctrl->framedesc_size = 0;
++	size = sizeof(struct ingenicfb_framedesc);
++
++	size = ALIGN(size, DESC_ALIGN);
++	alloc_size = size * DPU_COMP_MAX_FRAMEDESC;
++	addr = dma_alloc_coherent(dctrl->dev, alloc_size, &addr_phy, GFP_KERNEL);
++
++	if(IS_ERR_OR_NULL(addr)) {
++		dev_err(dctrl->dev, "Failed to alloc dma desc for rdma!\n");
++		return -ENOMEM;
++	}
++
++	for(i = 0; i < DPU_COMP_MAX_FRAMEDESC; i++) {
++		dctrl->framedesc[i] =
++			(struct ingenicfb_framedesc *)(addr + i * size);
++		dctrl->framedesc_phys[i] = addr_phy + i * size;
++	}
++	dctrl->framedesc_size = alloc_size;
++
++	/*Composer Layer Desc*/
++	size = sizeof(struct ingenicfb_layerdesc);
++	size = ALIGN(size, DESC_ALIGN);
++	alloc_size = size * DPU_COMP_MAX_FRAMEDESC * DPU_SUPPORT_MAX_LAYERS;
++
++	addr = dma_alloc_coherent(dctrl->dev, alloc_size, &addr_phy, GFP_KERNEL);
++	if(addr == NULL) {
++		ret = -ENOMEM;
++		goto err_layer_desc;
++	}
++	for(i = 0; i < DPU_COMP_MAX_FRAMEDESC; i++) {
++		for(j = 0; j < DPU_SUPPORT_MAX_LAYERS; j++) {
++			dctrl->layerdesc[i][j] = (struct ingenicfb_layerdesc *)
++				(addr + j * size + i * size * DPU_SUPPORT_MAX_LAYERS);
++			dctrl->layerdesc_phys[i][j] =
++				addr_phy + j * size + i * size * DPU_SUPPORT_MAX_LAYERS;
++		}
++	}
++	dctrl->layerdesc_size = alloc_size;
++
++	dctrl->comp_stopped = 1;
++	dctrl->srd_stopped = 0;
++
++
++	dev_info(dctrl->dev, "composer framedesc @ 0x%x size %d\n", dctrl->framedesc[0], dctrl->framedesc_size);
++	dev_info(dctrl->dev, "composer layerdesc @ 0x%x size %d\n", dctrl->layerdesc[0][0], dctrl->layerdesc_size);
++	return ret;
++
++err_layer_desc:
++	dma_free_coherent(dctrl->dev, dctrl->framedesc_size, dctrl->framedesc[0], dctrl->framedesc_phys[0]);
++	return ret;
++}
++
++static int dpu_ctrl_release_comp_desc(struct dpu_ctrl *dctrl)
++{
++	if(dctrl->framedesc_size) {
++		dma_free_coherent(dctrl->dev, dctrl->framedesc_size, dctrl->framedesc[0], dctrl->framedesc_phys[0]);
++	}
++
++	if(dctrl->layerdesc_size) {
++		dma_free_coherent(dctrl->dev, dctrl->layerdesc_size, dctrl->layerdesc[0][0], dctrl->layerdesc_phys[0][0]);
++	}
++
++	return 0;
++}
++
++
++int dpu_ctrl_try_rdma_release(struct dpu_ctrl *dctrl)
++{
++	unsigned int stat = reg_read(dctrl, DC_ST);
++	int ret = 0;
++	/*如果当�rdma没有使用，�以�试释放rdma申请的dma�述符资�，�功返回0.*/
++	if((dctrl->srd_stopped == 1) || !(stat & DC_SRD_WORKING)) {
++		dpu_ctrl_release_rdma_desc(dctrl);
++	} else {
++		ret = -EBUSY;
++	}
++
++	return ret;
++}
++
++
++
++/*
++ *	�始化LCD相关数�结构资�. 与具体硬件的�作无关.
++ *
++ * */
++int dpu_ctrl_init(struct dpu_ctrl *dctrl, struct lcd_panel *panel)
++{
++	int ret = 0;
++
++	dev_info(dctrl->dev, "dpu_ctrl_init start!\n");
++
++	spin_lock_init(&dctrl->irq_lock);
++
++	sprintf(dctrl->clk_name, "gate_lcd");
++	sprintf(dctrl->pclk_name, "div_lcd");
++
++	dctrl->clk = devm_clk_get(dctrl->dev, dctrl->clk_name);
++	if(IS_ERR(dctrl->clk)) {
++		ret = PTR_ERR(dctrl->clk);
++		dev_err(dctrl->dev, "Failed to get lcd clk\n");
++
++		goto err_clk;
++	}
++	dctrl->pclk = devm_clk_get(dctrl->dev, dctrl->pclk_name);
++	if(IS_ERR(dctrl->pclk)) {
++		ret = PTR_ERR(dctrl->pclk);
++		dev_err(dctrl->dev, "Failed to get lcd pclk\n");
++
++		goto err_pclk;
++	}
++
++	dctrl->base = of_iomap(dctrl->dev->of_node, 0);
++	if (!dctrl->base) {
++		dev_err(dctrl->dev,
++				"Failed to ioremap register memory region\n");
++		ret = -EBUSY;
++		goto err_put_clk;
++	}
++
++	dctrl->irq = platform_get_irq(dctrl->pdev, 0);
++	sprintf(dctrl->irq_name, "lcdc%d", dctrl->pdev->id);
++	if (devm_request_irq(dctrl->dev, dctrl->irq, dpu_ctrl_irq_handler, 0,
++				dctrl->irq_name, dctrl)) {
++		dev_err(dctrl->dev, "request irq failed\n");
++		ret = -EINVAL;
++		goto err_irq_req;
++	}
++
++
++	dctrl->panel = panel;
++
++	ingenic_set_pixclk(dctrl, dctrl->active_video_mode->pixclock);
++
++	clk_prepare_enable(dctrl->clk);
++	clk_prepare_enable(dctrl->pclk);
++
++
++	ret = dpu_ctrl_alloc_rdma_desc(dctrl);
++	if(ret < 0) {
++		goto err_rdma_desc;
++	}
++
++	if(dctrl->support_comp) {
++		ret = dpu_ctrl_alloc_comp_desc(dctrl);
++		if(ret < 0) {
++			goto err_comp_desc;
++		}
++	}
++
++	init_waitqueue_head(&dctrl->wq);
++
++	dpu_ctrl_rdma_stop(dctrl, QCK_STOP);//关闭rdma
++	dpu_ctrl_comp_stop(dctrl, QCK_STOP);//关闭composer
++	/*DSI �始化会�赖pixclk.所以�先设置pixclk.**/
++	if(panel->lcd_type == LCD_TYPE_MIPI_SLCD || panel->lcd_type == LCD_TYPE_MIPI_TFT){
++
++		dctrl->dsi = jzdsi_init(panel->dsi_pdata);
++		if (!dctrl->dsi) {
++			ret = -EINVAL;
++			goto err_iounmap;
++		}
++	}
++
++
++	dev_info(dctrl->dev, "dpu_ctrl_init success\n");
++
++	return 0;
++err_comp_desc:
++	dpu_ctrl_release_rdma_desc(dctrl);
++err_rdma_desc:
++	jzdsi_remove(dctrl->dsi);
++err_iounmap:
++	clk_disable_unprepare(dctrl->pclk);
++	clk_disable_unprepare(dctrl->clk);
++	free_irq(dctrl->irq, dctrl);
++err_irq_req:
++	iounmap(dctrl->base);
++err_put_clk:
++	devm_clk_put(dctrl->dev, dctrl->pclk);
++err_pclk:
++	devm_clk_put(dctrl->dev, dctrl->clk);
++err_clk:
++	return ret;
++}
++
++
++void dpu_ctrl_exit(struct dpu_ctrl *dctrl)
++{
++	dpu_ctrl_rdma_stop(dctrl, QCK_STOP);
++	dpu_ctrl_comp_stop(dctrl, QCK_STOP);
++
++	dpu_ctrl_release_rdma_desc(dctrl);
++	dpu_ctrl_release_comp_desc(dctrl);
++	if(dctrl->panel->lcd_type == LCD_TYPE_MIPI_SLCD ||dctrl->panel->lcd_type == LCD_TYPE_MIPI_TFT){
++		jzdsi_remove(dctrl->dsi);
++	}
++	iounmap(dctrl->base);
++	free_irq(dctrl->irq, dctrl);
++
++	devm_clk_put(dctrl->dev, dctrl->pclk);
++	devm_clk_put(dctrl->dev, dctrl->clk);
++}
++
++int dpu_ctrl_suspend(struct dpu_ctrl *dctrl)
++{
++
++	if(dctrl->panel->lcd_type == LCD_TYPE_MIPI_SLCD || dctrl->panel->lcd_type == LCD_TYPE_MIPI_TFT){
++		dctrl->dsi->master_ops->set_blank_mode(dctrl->dsi, FB_BLANK_POWERDOWN);
++	}
++	//TODO: Lock??
++	if(dctrl->chan == DATA_CH_RDMA) {
++		dpu_ctrl_rdma_stop(dctrl, QCK_STOP);
++	} else {
++		dpu_ctrl_comp_stop(dctrl, QCK_STOP);
++	}
++
++	clk_disable_unprepare(dctrl->clk);
++	clk_disable_unprepare(dctrl->pclk);
++
++	return 0;
++}
++
++int dpu_ctrl_resume(struct dpu_ctrl *dctrl)
++{
++	clk_prepare_enable(dctrl->pclk);
++	clk_prepare_enable(dctrl->clk);
++
++	/*!! dpu must not enabled before dsi UNBLANK.*/
++	if(dctrl->panel->lcd_type == LCD_TYPE_MIPI_SLCD || dctrl->panel->lcd_type == LCD_TYPE_MIPI_TFT){
++		dctrl->dsi->master_ops->set_blank_mode(dctrl->dsi, FB_BLANK_UNBLANK);
++	}
++
++	//TODO: lock??
++	dpu_ctrl_setup(dctrl);
++
++	if(dctrl->chan == DATA_CH_RDMA) {
++		dpu_ctrl_rdma_setup(dctrl, &dctrl->rdma_info);
++		dpu_ctrl_rdma_start(dctrl);
++	} else {
++		dpu_ctrl_comp_setup(dctrl, &dctrl->comp_info);
++		dpu_ctrl_comp_start(dctrl, 0);
++	}
++
++	return 0;
++}
++
++
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/dpu_ctrl.h b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/dpu_ctrl.h
+new file mode 100644
+index 000000000..f94a8c4fd
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/dpu_ctrl.h
+@@ -0,0 +1,196 @@
++#ifndef __DPU_CTRL_H__
++#define __DPU_CTRL_H__
++
++#include "uapi_ingenicfb.h"
++#include "jz_dsim.h"
++#include "lcd_panel.h"
++
++#include "dpu_dma_desc.h"
++#include "./jz_mipi_dsi/jz_mipi_dsih_hal.h"
++#include "./jz_mipi_dsi/jz_mipi_dsi_regs.h"
++#include "./jz_mipi_dsi/jz_mipi_dsi_lowlevel.h"
++extern struct dsi_device * jzdsi_init(struct jzdsi_data *pdata);
++extern void jzdsi_remove(struct dsi_device *dsi);
++extern void dump_dsi_reg(struct dsi_device *dsi);
++extern int jz_mipi_dsi_set_client(struct dsi_device *dsi, int power);
++
++
++
++#define DPU_COMP_MAX_FRAMEDESC 3
++
++#define DESC_ALIGN 8
++typedef enum stop_mode {
++	QCK_STOP,
++	GEN_STOP,
++} stop_mode_t;
++
++typedef enum csc_mode {
++	CSC_MODE_0,
++	CSC_MODE_1,
++	CSC_MODE_2,
++	CSC_MODE_3,
++} csc_mode_t;
++
++
++typedef enum data_ch {
++	DATA_CH_COMP,
++	DATA_CH_RDMA,
++} data_ch_t;
++
++struct rdma_setup_info {
++	unsigned int nframes;
++	unsigned int format;
++	unsigned int color;
++	unsigned int stride;
++	int continuous;		/*连续帧还是�帧模�.*/
++	unsigned char **vidmem;
++	unsigned int **vidmem_phys;
++};
++
++
++typedef enum comp_mode {
++	COMP_DIRECT_OUT,
++	COMP_WRITE_BACK,
++} comp_mode_t;
++
++struct comp_setup_info {
++	unsigned int nframes;
++	comp_mode_t out_mode;	/*Direct Display or Writeback to Memory.*/
++
++	struct ingenicfb_frm_cfg frm_cfg;
++};
++
++struct dbg_irqcnt {
++	unsigned long long irqcnt;
++	unsigned long long cmp_start;
++	unsigned long long stop_disp_ack;
++	unsigned long long disp_end;
++	unsigned long long tft_under;
++	unsigned long long wdma_over;
++	unsigned long long wdma_end;
++	unsigned long long layer3_end;
++	unsigned long long layer2_end;
++	unsigned long long layer1_end;
++	unsigned long long layer0_end;
++	unsigned long long clr_cmp_end;
++	unsigned long long stop_wrbk_ack;
++	unsigned long long srd_start;
++	unsigned long long srd_end;
++	unsigned long long cmp_w_slow;
++};
++#define dbg_irqcnt_inc(dbg,x)	dbg.x++
++
++struct dpu_ctrl {
++
++	int irq;		/* lcdc interrupt num */
++	void __iomem *base;
++	struct resource *mem;
++	struct device *dev;
++	struct platform_device *pdev;
++
++
++	struct lcd_panel *panel;
++	struct fb_videomode *active_video_mode;
++
++	char clk_name[16];
++	char pclk_name[16];
++	char irq_name[16];
++	struct clk *clk;
++	struct clk *pclk;
++
++	spinlock_t	irq_lock;
++
++	/* wait 事件.*/
++	int srd_stopped;
++	int comp_stopped;
++	int wback_end;
++	wait_queue_head_t wq;
++	struct dsi_device *dsi;
++
++	void (*set_vsync_value)(void *data);
++	void *vsync_data;
++
++	unsigned int user_addr;
++	unsigned int tlba;
++	unsigned int tlb_err_cnt;
++
++	struct ingenicfb_sreadesc *sreadesc[CONFIG_FB_INGENIC_NR_FRAMES];
++	dma_addr_t sreadesc_phys[CONFIG_FB_INGENIC_NR_FRAMES];
++	unsigned int sreadesc_size;
++
++	struct ingenicfb_framedesc *framedesc[DPU_COMP_MAX_FRAMEDESC];
++	dma_addr_t framedesc_phys[DPU_COMP_MAX_FRAMEDESC];
++	unsigned int framedesc_size;
++
++	struct ingenicfb_layerdesc *layerdesc[DPU_COMP_MAX_FRAMEDESC][DPU_SUPPORT_MAX_LAYERS];
++	dma_addr_t layerdesc_phys[DPU_COMP_MAX_FRAMEDESC][DPU_SUPPORT_MAX_LAYERS];
++	unsigned int layerdesc_size;
++
++	csc_mode_t csc_mode;
++
++	unsigned int comp_last_framedesc;	/*记录软件需�更新的�述符物�地�.*/
++	int comp_last_frame;			/*记录软件上一次刷新的帧.*/
++	unsigned int comp_hw_framedesc;		/*记录硬件当�使用的�述符物�地�.*/
++
++	int comp_next_frame;		/*记录comp下一帧需���的帧number.*/
++
++	int rdma_changing_frame;	/*记录正在changing 的 frame.*/
++	int rdma_desc_changing;		/*记录当�正处于desc 切�状�.*/
++	int rdma_last_frame;		/*记录正在刷新的rdma frame index.*/
++	struct rdma_setup_info rdma_info;
++	struct comp_setup_info comp_info;
++
++	data_ch_t chan;	/*当�显示使用的数�通�， RDMA or COMPOSER.*/
++
++	struct dbg_irqcnt dbg_irqcnt;
++	unsigned long long comp_fps;	/*记录软件更新的帧率.*/
++
++	bool tlb_disable;
++	int tlb_disable_ch;
++
++	bool support_comp;	/*This value is false for some controllers that do not support comp mode*/
++};
++
++
++
++
++int dpu_ctrl_init(struct dpu_ctrl *dctrl, struct lcd_panel *panel);
++void dpu_ctrl_exit(struct dpu_ctrl *dctrl);
++
++int dpu_ctrl_suspend(struct dpu_ctrl *dctrl);
++int dpu_ctrl_resume(struct dpu_ctrl *dctrl);
++
++
++
++
++int dpu_ctrl_setup(struct dpu_ctrl *dctrl);
++
++int dpu_ctrl_rdma_setup(struct dpu_ctrl *dctrl, struct rdma_setup_info *rdma_info);
++int dpu_ctrl_rdma_start(struct dpu_ctrl *dctrl);
++int dpu_ctrl_rdma_stop(struct dpu_ctrl *dctrl, enum stop_mode mode);
++int dpu_ctrl_rdma_change(struct dpu_ctrl *dctrl, int frame);
++
++int dpu_ctrl_comp_setup(struct dpu_ctrl *dctrl, struct comp_setup_info *comp_info);
++int dpu_ctrl_comp_start(struct dpu_ctrl *dctrl, int block);
++int dpu_ctrl_comp_stop(struct dpu_ctrl *dctrl, enum stop_mode mode);
++int dpu_ctrl_try_rdma_release(struct dpu_ctrl *dctrl);
++
++
++void dump_lcdc_registers(struct dpu_ctrl *dctrl);
++void dump_comp_desc(struct dpu_ctrl *dctrl);
++void dump_rdma_desc(struct dpu_ctrl *dctrl);
++
++
++static inline unsigned long reg_read(struct dpu_ctrl *dctrl, int offset)
++{
++	return readl(dctrl->base + offset);
++}
++
++static inline void reg_write(struct dpu_ctrl *dctrl, int offset, unsigned long val)
++{
++	writel(val, dctrl->base + offset);
++}
++
++
++
++#endif
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/dpu_dma_desc.h b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/dpu_dma_desc.h
+new file mode 100644
+index 000000000..3da525e1c
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/dpu_dma_desc.h
+@@ -0,0 +1,183 @@
++#ifndef __DPU_DMA_DESC_H__
++#define __DPU_DMA_DESC_H__
++
++
++typedef union frm_size {
++	uint32_t d32;
++	struct {
++		uint32_t width:12;
++	        uint32_t reserve12_15:4;
++	        uint32_t height:12;
++	        uint32_t reserve28_31:4;
++	}b;
++} frm_size_t;
++
++typedef union frm_ctrl {
++	uint32_t d32;
++	struct {
++		uint32_t stop:1;
++		uint32_t wb_en:1;
++		uint32_t direct_en:1;
++		uint32_t change_2_rdma:1;
++		uint32_t wb_dither_en:1;
++		uint32_t wb_dither_auto:1;
++		uint32_t reserve6_15:10;
++		uint32_t wb_format:3;
++		uint32_t reserve19:1;
++		uint32_t wb_dither_b_dw:2;
++		uint32_t wb_dither_g_dw:2;
++		uint32_t wb_dither_r_dw:2;
++		uint32_t reserve26_31:6;
++	}b;
++} frm_ctrl_t;
++
++typedef union lay_cfg_en {
++	uint32_t d32;
++	struct {
++		uint32_t lay0_scl_en:1;
++		uint32_t lay1_scl_en:1;
++		uint32_t lay2_scl_en:1;
++		uint32_t lay3_scl_en:1;
++		uint32_t lay0_en:1;
++		uint32_t lay1_en:1;
++		uint32_t lay2_en:1;
++		uint32_t lay3_en:1;
++		uint32_t lay0_z_order:2;
++		uint32_t lay1_z_order:2;
++		uint32_t lay2_z_order:2;
++		uint32_t lay3_z_order:2;
++		uint32_t leserve16_31:16;
++	}b;
++} lay_cfg_en_t;
++
++typedef union cmp_irq_ctrl {
++	uint32_t d32;
++	struct {
++		uint32_t reserve0_8:9;
++		uint32_t eoc_msk:1;
++		uint32_t reserve10_13:4;
++		uint32_t soc_msk:1;
++		uint32_t eow_msk:1;
++		uint32_t reserve_16:1;
++		uint32_t eod_msk:1;
++		uint32_t reserve18_31:14;
++	}b;
++} cmp_irq_ctrl_t;
++
++typedef union lay_size {
++	uint32_t d32;
++	struct {
++		uint32_t width:12;
++	        uint32_t reserve12_15:4;
++	        uint32_t height:12;
++	        uint32_t reserve28_31:4;
++	}b;
++} lay_size_t;
++
++typedef union lay_cfg {
++	uint32_t d32;
++	struct {
++		uint32_t g_alpha:8;
++		uint32_t reserve8_9:2;
++		uint32_t color:3;
++		uint32_t g_alpha_en:1;
++		uint32_t domain_multi:1;
++		uint32_t reserve15:1;
++		uint32_t format:4;
++		uint32_t sharpl:2;
++		uint32_t reserve22_31:10;
++	}b;
++} lay_cfg_t;
++
++typedef union lay_scale {
++	uint32_t d32;
++	struct {
++		uint32_t target_width:12;
++	        uint32_t reserve12_15:4;
++	        uint32_t target_height:12;
++	        uint32_t reserve28_31:4;
++	}b;
++} lay_scale_t;
++
++typedef union lay_rotation {
++	uint32_t d32;
++	struct {
++		uint32_t rotation:3;
++		uint32_t reserve3_31:29;
++	}b;
++} lay_rotation_t;
++
++typedef union lay_pos {
++	uint32_t d32;
++	struct {
++		uint32_t x_pos:12;
++	        uint32_t reserve12_15:4;
++	        uint32_t y_pos:12;
++	        uint32_t reserve28_31:4;
++	}b;
++} lay_pos_t;
++
++typedef union chain_cfg {
++	uint32_t d32;
++	struct {
++		uint32_t chain_end:1;
++		uint32_t change_2_cmp:1;
++		uint32_t reserve2_15:14;
++		uint32_t color:3;
++		uint32_t format:4;
++		uint32_t reserve23_31:9;
++	}b;
++} chain_cfg_t;
++
++typedef union rdma_irq_ctrl {
++	uint32_t d32;
++	struct {
++		uint32_t reserve_0:1;
++		uint32_t eos_msk:1;
++		uint32_t sos_msk:1;
++		uint32_t reserve3_16:14;
++		uint32_t eod_msk:1;
++		uint32_t reserve18_31:4;
++	}b;
++} rdma_irq_ctrl_t;
++
++struct ingenicfb_framedesc {
++	uint32_t	   FrameNextCfgAddr;
++	frm_size_t	   FrameSize;
++	frm_ctrl_t	   FrameCtrl;
++	uint32_t	   WritebackAddr;
++	uint32_t	   WritebackStride;
++	uint32_t	   Layer0CfgAddr;
++	uint32_t	   Layer1CfgAddr;
++	uint32_t 	   Layer2CfgAddr;
++	uint32_t	   Layer3CfgAddr;
++	lay_cfg_en_t       LayCfgEn;
++	cmp_irq_ctrl_t	   InterruptControl;
++};
++
++struct ingenicfb_layerdesc {
++	lay_size_t	LayerSize;
++	lay_cfg_t	LayerCfg;
++	uint32_t	LayerBufferAddr;
++	lay_scale_t	LayerScale;
++	lay_rotation_t	LayerRotation;
++	uint32_t	LayerScratch;
++	lay_pos_t	LayerPos;
++	uint32_t	layerresizecoef_x;
++	uint32_t	layerresizecoef_y;
++	uint32_t	LayerStride;
++	uint32_t        UVBufferAddr;
++	uint32_t        UVStride;
++
++};
++
++struct ingenicfb_sreadesc {
++	uint32_t	RdmaNextCfgAddr;
++	uint32_t	FrameBufferAddr;
++	uint32_t	Stride;
++	chain_cfg_t	ChainCfg;
++	rdma_irq_ctrl_t	InterruptControl;
++};
++
++
++#endif
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/dpu_reg.h b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/dpu_reg.h
+new file mode 100644
+index 000000000..6b679b525
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/dpu_reg.h
+@@ -0,0 +1,888 @@
++/*
++ * drivers/video/fbdev/ingenic/x2000_v12/dpu_reg.h
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * Author:clwang<chunlei.wang@ingenic.com>
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++
++#ifndef _DPU_REG_H_
++#define _DPU_REG_H_
++
++#define         DPU_BASE	 	0xb3050000
++
++/*-------------------------------------------------------------------------------
++ *			      DPU Register Offset
++ * -----------------------------------------------------------------------------*/
++
++
++/* RW	32	0x0000_0000	frame descriptor's address*/
++#define DC_FRM_CFG_ADDR		        (0x0000)
++/* -W	32	0x0000_0000	frame descriptor's control*/
++#define DC_FRM_CFG_CTRL		        (0x0004)
++/* RW	32	0x0000_0000	RDMA descriptor's address*/
++#define DC_RDMA_CHAIN_ADDR              (0x1000)
++/* -W	32	0x0000_0000	RDMA descriptor's control*/
++#define DC_RDMA_CHAIN_CTRL              (0x1004)
++/* RW	32	0x0000_0000	DC control*/
++#define DC_CTRL				(0x2000)
++/* RW	32	0x0000_0000	DC status*/
++#define DC_ST				(0x2004)
++/* -W	32	0x0000_0000	DC clear status*/
++#define DC_CLR_ST			(0x2008)
++/* RW	32	0x0000_0000	DC interrupt mask*/
++#define DC_INTC				(0x200c)
++/* R-	32	0x0000_0000	For debug*/
++#define DC_INT_FLAG			(0x2010)
++/* RW	32	0x0000_0000	Common configure register*/
++#define DC_COM_CONFIG		        (0x2014)
++
++/* RW	32	0x0000-0006	RDMA Priority level soft config*/
++#define DC_PCFG_RD_CTRL		        (0x2018)
++/* RW	32	0x0000-0006	writeback Priority level soft config*/
++#define DC_PCFG_WR_CTRL		        (0x201c)
++/* RW	32	0x0066-4422	OFIFO Priority level threshold config*/
++#define DC_OFIFO_PCFG		        (0x2020)
++/* RW	32	0x0018-1008	WDMA Priority level threshold config*/
++#define DC_WDMA_PCFG		        (0x2024)
++/* RW	32	0x0000-0006	CMP_W Priority level soft config*/
++#define DC_CMPW_PCFG_CTRL		(0x2028)
++/* RW	32	0x0000-0006	CMPW PCFG0 soft config*/
++#define DC_CMPW_PCFG0			(0x202c)
++/* RW	32	0x0000-0006	CMPW PCFG1 soft config*/
++#define DC_CMPW_PCFG1			(0x2030)
++/* RW	32	0x0000-0006	CMPW PCFG2 soft config*/
++#define DC_CMPW_PCFG2			(0x2034)
++
++/* R-	32	0x0000_0000	For debug*/
++#define DC_FRM_DES			(0x2100)
++/* R-	32	0x0000_0000	For debug*/
++#define DC_LAY0_DES			(0x2104)
++/* R-	32	0x0000_0000	For debug*/
++#define DC_LAY1_DES			(0x2108)
++/* R-	32	0x0000_0000	For debug*/
++#define DC_LAY2_DES			(0x210c)
++/* R-	32	0x0000_0000	For debug*/
++#define DC_LAY3_DES			(0x2110)
++/* R-	32	0x0000_0000	For debug*/
++#define DC_RDMA_DES			(0x2114)
++/* R-	32	0x0000_0000	frame descriptor's current site*/
++#define DC_FRM_CHAIN_SITE		(0x2200)
++/* R-	32	0x0000_0000	rdma descriptor's current site*/
++#define DC_RDMA_CHAIN_SITE		(0x2204)
++/* R-	32	0x0000_0000	layer0's current site*/
++#define DC_LAY0_SITE			(0x3100)
++/* R-	32	0x0000_0000	layer1's current site*/
++#define DC_LAY1_SITE			(0x3104)
++/* R-	32	0x0000_0000	layer2's current site*/
++#define DC_LAY2_SITE			(0x3108)
++/* R-	32	0x0000_0000	layer3's current site*/
++#define DC_LAY3_SITE			(0x310c)
++/* R-	32	0x0000_0000	rdma's current site*/
++#define DC_RDMA_SITE			(0x3110)
++/* R-	32	0x0000_0000	wdma's current site*/
++#define DC_WDMA_SITE			(0x221c)
++/* RW	32	0x0000_0000	TLB Global Control*/
++#define DC_TLB_GLBC			(0x3000)
++/* RW	32	0x0000_0000	TLB table entry address*/
++#define DC_TLB_TLBA			(0x3010)
++/* RW	32	0x0000_0000	TLB trigger control*/
++#define DC_TLB_TLBC			(0x3020)
++/* R-	32	0x0000_0000	VPN probe 0*/
++#define DC_TLB0_VPN			(0x3030)
++/* R-	32	0x0000_0000	VPN probe 1*/
++#define DC_TLB1_VPN			(0x3034)
++/* R-	32	0x0000_0000	VPN probe 2*/
++#define DC_TLB2_VPN			(0x3038)
++/* R-	32	0x0000_0000	VPN probe 3*/
++#define DC_TLB3_VPN			(0x303c)
++/* RW	32	0x0000_0000	TLB table entry verification*/
++#define DC_TLB_TLBV			(0x3040)
++/* R-	32	0x0000_0000	TLB status*/
++#define DC_TLB_STAT			(0x3050)
++/* RW   32      0x066204a8	CscMultYRv*/
++#define DC_CSC_MULT_YRV			(0x3200)
++/* RW   32      0x03410190      CscMultGuGv*/
++#define DC_CSC_MULT_GUGV		(0x3204)
++/* RW   32      0x00000812      CscMultBu*/
++#define DC_CSC_MULT_BU			(0x3208)
++/* RW   32      0x00800000      CscSubYUV*/
++#define DC_CSC_SUB_YUV			(0x320c)
++/* RW	32	0x0000_0000	display common configure*/
++#define DC_DISP_COM			(0x8000)
++/* RW	32	0x0000_0000	TFT HSYNC*/
++#define DC_TFT_HSYNC		        (0x9000)
++/* RW	32	0x0000_0000	TFT VSYNC*/
++#define DC_TFT_VSYNC		        (0x9004)
++/* RW	32	0x0000_0000	TFT HDE*/
++#define DC_TFT_HDE			(0x9008)
++/* RW	32	0x0000_0000	TFT VDE*/
++#define DC_TFT_VDE			(0x900C)
++/* RW	32	0x0000_0000	TFT configure*/
++#define DC_TFT_CFG			(0x9010)
++/* RW	32	0x0000_0000	TFT status*/
++#define DC_TFT_ST			(0x9014)
++/* RW	32	0x0000_0000	SLCD configure*/
++#define DC_SLCD_CFG			(0xA000)
++/* RW	32	0x0000_0000	SLCD WR's duty*/
++#define DC_SLCD_WR_DUTY		        (0xA004)
++/* RW	32	0x0000_0000	SLCD timing*/
++#define DC_SLCD_TIMING		        (0xA008)
++/* RW	32	0x0000_0000	frame size*/
++#define DC_SLCD_FRM_SIZE	        (0xA00C)
++/* RW	32	0x0000_0000	slow time*/
++#define DC_SLCD_SLOW_TIME	        (0xA010)
++/* RW	32	0x0000_0000	SLCD command*/
++#define DC_SLCD_REG_IF			(0xA014)
++/* RW	32	0x0000_0000	SLCD status*/
++#define DC_SLCD_ST			(0xA018)
++#define DC_SLCD_REG_CTRL		(0xA01c)
++
++
++/*-------------------------------------------------------------------------------
++ *			DPU Registers Bits Field Define
++ * -----------------------------------------------------------------------------*/
++
++
++/* Frame descriptor control(DC_FRM_CFG_CTRL) bit field define */
++
++/* 1:change to single read channel after the current frame ; 0:no effect */
++#define	DC_CHANGE_2_RDMA		BIT(1)
++/* Frame descriptor DMA start */
++#define	DC_FRM_START			BIT(0)
++
++/* RDMA descriptor control(DC_RDMA_CHAIN_CTRL) bit field define */
++
++/* 1:change to composer channel after the current frame ; 0:no effect */
++#define	DC_CHANGE_2_CMP 		BIT(1)
++/* RDMA descriptor DMA start */
++#define	DC_RDMA_START			BIT(0)
++
++/* Control configure(DC_CTRL) bit field define */
++
++/* General stop the simple read channel.Assure integrity of the current frame */
++#define DC_GEN_STP_RDMA			BIT(4)
++/* General stop the composer channel. Assure integrity of the current frame */
++#define DC_GEN_STP_CMP			BIT(3)
++/* Reset the counter of FRM_DES, LAYx_DES and RDMA_DES */
++#define DC_DES_CNT_RST			BIT(2)
++/* Quick stop the simple read channel. */
++#define DC_QCK_STP_RDMA			BIT(1)
++/* Quick stop the composer channel. */
++#define DC_QCK_STP_CMP			BIT(0)
++
++/* Status Register(DC_ST) bit field define */
++
++/* Composer cannot meet the writeback frame rate*/
++#define DC_CMP_W_SLOW			BIT(31)
++/* One frame display end */
++#define DC_DISP_END			BIT(17)
++/* write back DMA is over-run. */
++#define DC_WDMA_OVER	 		BIT(16)
++/* write back DMA end. */
++#define DC_WDMA_END			BIT(15)
++/* simple read DMA end. */
++#define DC_CMP_START			BIT(14)
++/* layer3's block DMA end. */
++#define DC_LAY3_END			BIT(13)
++/* layer2's block DMA end. */
++#define DC_LAY2_END			BIT(12)
++/* layer1's block DMA end. */
++#define DC_LAY1_END			BIT(11)
++/* layer0's block DMA end. */
++#define DC_LAY0_END			BIT(10)
++/*  composer end of each frame. */
++#define DC_CMP_END			BIT(9)
++/* TFT jump into under-run mode. */
++#define DC_TFT_UNDR			BIT(8)
++/* writeback channel is general stop */
++#define DC_STOP_SRD_ACK		BIT(7)
++/* Display channel general stop */
++#define DC_STOP_CMP_ACK		BIT(6)
++/* writeback channel is working */
++#define DC_WRBK_WORKING			BIT(5)
++/* composer direct output channel is working. */
++#define DC_DIRECT_WORKING		BIT(4)
++#define DC_SRD_WORKING			BIT(3)
++#define DC_SRD_START			BIT(2)
++#define DC_SRD_END			BIT(1)
++/* display controller is working. */
++#define DC_WORKING			BIT(0)
++
++/* Clear status Register(DC_CSR) bit field define */
++
++/* Clear CMP_W_SLOW*/
++#define DC_CLR_CMP_W_SLOW		BIT(31)
++#define DC_CLR_DISP_END			BIT(17)
++/* clear WDMA_OVER */
++#define DC_CLR_WDMA_OVER		BIT(16)
++/* clear WDMA_END */
++#define DC_CLR_WDMA_END			BIT(15)
++#define DC_CLR_CMP_START			BIT(14)
++/* clear BDMA3_END */
++#define DC_CLR_LAY3_END		BIT(13)
++/* clear BDMA2_END */
++#define DC_CLR_LAY2_END		BIT(12)
++/* clear BDMA1_END */
++#define DC_CLR_LAY1_END		BIT(11)
++/* clear BDMA0_END */
++#define DC_CLR_LAY0_END		BIT(10)
++/* clear BDMA_END */
++#define DC_CLR_CMP_END			BIT(9)
++/* clear TFT_UNDR */
++#define DC_CLR_TFT_UNDR			BIT(8)
++/* clear STOP_WRBK_ACK */
++#define DC_CLR_STOP_SRD_ACK		BIT(7)
++/* clear STOP_DISP_ACK */
++#define DC_CLR_STOP_CMP_ACK		BIT(6)
++#define DC_CLR_SRD_START		BIT(2)
++#define DC_CLR_SRD_END			BIT(1)
++
++/* INTC register(DC_INTC) bit field define */
++
++/* Mask of CMP_W_SLOW*/
++#define DC_CWS_MSK			BIT(31)
++/* mask of DISP_END */
++#define DC_EOD_MSK			BIT(17)
++/* mask of WDMA_OVER */
++#define DC_OOW_MSK			BIT(16)
++/* mask of WDMA_END */
++#define DC_EOW_MSK			BIT(15)
++#define DC_SOC_MSK			BIT(14)
++/* mask of BDMA3_END */
++#define DC_EOL3_MSK			BIT(13)
++/* mask of BDMA2_END */
++#define DC_EOL2_MSK			BIT(12)
++/* mask of BDMA1_END */
++#define DC_EOL1_MSK			BIT(11)
++/* mask of BDMA0_END */
++#define DC_EOL0_MSK			BIT(10)
++#define DC_EOC_MSK			BIT(9)
++/* mask of TFT_UNDR */
++#define DC_UOT_MSK			BIT(8)
++/* mask of STOP_WRBK_ACK */
++#define DC_SWA_MSK			BIT(7)
++/* mask of STOP_DISP_ACK */
++#define DC_SDA_MSK			BIT(6)
++#define DC_SOS_MSK			BIT(2)
++#define DC_EOS_MSK			BIT(1)
++
++/* DC interrupt flag(DC_INT_FLAG) */
++
++/* Interrupt of CMP_W_SLOW*/
++#define DC_INT_CWS			BIT(31)
++/* Interrupt of DISP_END */
++#define DC_INT_EOD			BIT(17)
++#define DC_INT_OOW			BIT(16)
++#define DC_INT_EOW			BIT(15)
++#define DC_INT_SOC			BIT(14)
++#define DC_INT_EOL3			BIT(13)
++#define DC_INT_EOL2			BIT(12)
++/* Interrupt of BDMA1_END */
++#define DC_INT_EOL1			BIT(11)
++/* Interrupt of BDMA0_END */
++#define DC_INT_EOL0			BIT(10)
++/* Interrupt of BDMA_END */
++#define DC_INT_EOC			BIT(9)
++/* Interrupt of TFT_UNDR */
++#define DC_INT_UOT			BIT(8)
++#define DC_INT_SWA			BIT(7)
++/* Interrupt of STOP_DISP_ACK */
++#define DC_INT_SDA			BIT(6)
++#define DC_INT_SOS			BIT(2)
++#define DC_INT_EOS			BIT(1)
++
++
++
++/* Common configure register(DC_COM_CONFIG) bit field define */
++
++
++/***add reg  clk_gate_en***/
++#define DC_BURST_LEN_WDMA_LBIT		(6)
++#define DC_BURST_LEN_WDMA_HBIT		(7)
++#define DC_BURST_LEN_WDMA_MASK	\
++	GENMASK(DC_BURST_LEN_WDMA_HBIT, DC_BURST_LEN_WDMA_LBIT)
++#define DC_BURST_LEN_WDMA_4		(0) << DC_BURST_LEN_WDMA_LBIT
++#define DC_BURST_LEN_WDMA_8		(1) << DC_BURST_LEN_WDMA_LBIT
++#define DC_BURST_LEN_WDMA_16		(2) << DC_BURST_LEN_WDMA_LBIT
++#define DC_BURST_LEN_WDMA_32		(3) << DC_BURST_LEN_WDMA_LBIT
++
++#define DC_BURST_LEN_RDMA_LBIT		(4)
++#define DC_BURST_LEN_RDMA_HBIT		(5)
++#define DC_BURST_LEN_RDMA_MASK	\
++	GENMASK(DC_BURST_LEN_RDMA_HBIT, DC_BURST_LEN_RDMA_LBIT)
++#define DC_BURST_LEN_RDMA_4		(0) << DC_BURST_LEN_RDMA_LBIT
++#define DC_BURST_LEN_RDMA_8		(1) << DC_BURST_LEN_RDMA_LBIT
++#define DC_BURST_LEN_RDMA_16		(2) << DC_BURST_LEN_RDMA_LBIT
++#define DC_BURST_LEN_RDMA_32		(3) << DC_BURST_LEN_RDMA_LBIT
++
++#define DC_BURST_LEN_BDMA_LBIT		(2)
++#define DC_BURST_LEN_BDMA_HBIT		(3)
++#define DC_BURST_LEN_BDMA_MASK	\
++	GENMASK(DC_BURST_LEN_BDMA_HBIT, DC_BURST_LEN_BDMA_LBIT)
++#define DC_BURST_LEN_BDMA_4		(0) << DC_BURST_LEN_BDMA_LBIT
++#define DC_BURST_LEN_BDMA_8		(1) << DC_BURST_LEN_BDMA_LBIT
++#define DC_BURST_LEN_BDMA_16		(2) << DC_BURST_LEN_BDMA_LBIT
++#define DC_BURST_LEN_BDMA_32		(3) << DC_BURST_LEN_BDMA_LBIT
++
++/* keep default value */
++#define	DC_OUT_SEL			BIT(1)
++#define DC_OUT_SEL_RDMA                 BIT(1)
++#define DC_OUT_SEL_CMP			~BIT(1)
++
++/* PCFG_RD_CTRL register */
++
++/*  QoS value */
++#define DC_ARQOS_VAL_LBIT		(1)
++#define DC_ARQOS_VAL_HBIT		(2)
++#define DC_ARQOS_VAL_MASK   \
++	GENMASK(DC_ARQOS_VAL_HBIT, DC_ARQOS_VAL_LBIT)
++#define DC_ARQOS_VAL_0			(0) << DC_ARQOS_VAL_LBIT
++#define DC_ARQOS_VAL_1			(1) << DC_ARQOS_VAL_LBIT
++#define DC_ARQOS_VAL_2			(2) << DC_ARQOS_VAL_LBIT
++#define DC_ARQOS_VAL_3			(3) << DC_ARQOS_VAL_LBIT
++/*  QoS ctrl */
++#define DC_ARQOS_CTRL			BIT(0)
++
++/* PCFG register(OFIFO's PCFG Register) bit field define */
++#define DC_PCFG0_LBIT			(0)
++#define DC_PCFG0_HBIT			(8)
++#define DC_PCFG0_MASK	      \
++	GENMASK(DC_PCFG0_HBIT, DC_PCFG0_LBIT)
++
++#define DC_PCFG1_LBIT			(9)
++#define DC_PCFG1_HBIT			(17)
++#define DC_PCFG1_MASK	      \
++	GENMASK(DC_PCFG1_HBIT, DC_PCFG1_LBIT)
++
++#define DC_PCFG2_LBIT			(18)
++#define DC_PCFG2_HBIT			(26)
++#define DC_PCFG2_MASK	       \
++	GENMASK(DC_PCFG2_HBIT, DC_PCFG2_LBIT)
++
++/* Global control(GLBC) bit field define */
++
++/* TLB enable */
++#define DC_TLBE_LBIT			(0)
++#define DC_TLBE_HBIT			(3)
++#define DC_TLBE_MASK        \
++	GENMASK(DC_TLBE_HBIT, DC_TLBE_LBIT)
++/* TLB channel 0 enable */
++#define DC_CH0_TLBE 			BIT(0)
++/* TLB channel 1 enable */
++#define DC_CH1_TLBE 			BIT(1)
++/* TLB channel 2 enable */
++#define DC_CH2_TLBE 			BIT(2)
++/* TLB channel 3 enable */
++#define DC_CH3_TLBE 			BIT(3)
++
++/* Interrupt enable */
++#define DC_INTE_LBIT			(4)
++#define DC_INTE_HBIT			(7)
++#define DC_INTE_MASK        \
++	GENMASK(DC_INTE_HBIT, DC_INTE_LBIT)
++/* TLB channel 0 interrupt enable */
++#define DC_CH0_INTE			BIT(4)
++/* TLB channel 1 interrupt enable */
++#define DC_CH1_INTE			BIT(5)
++/* TLB channel 2 interrupt enable */
++#define DC_CH2_INTE			BIT(6)
++/* TLB channel 3 interrupt enable */
++#define DC_CH3_INTE			BIT(7)
++
++/* TLB fetch mode, for STB miss */
++#define DC_FMODE_LBIT			(8)
++#define DC_FMODE_HBIT			(11)
++#define DC_FMODE_MASK        \
++	GENMASK(DC_FMODE_HBIT, DC_FMODE_LBIT)
++#define DC_CH0_FMODE			BIT(8)
++#define DC_CH1_FMODE			BIT(9)
++#define DC_CH2_FMODE			BIT(10)
++#define DC_CH3_FMODE			BIT(11)
++
++/* TLB table address(GLBA) bit field define */
++
++/* TLB table address,Its only used and must \
++ *  be initialized when GLBC.TLBEn was set */
++#define DC_TLBA_LBIT			(12)
++#define DC_TLBA_HBIT			(31)
++#define DC_TLBA_MASK        \
++	GENMASK(DC_TLBA_HBIT, DC_TLBA_LBIT)
++
++/* TLB control Trigger(TLBC) bit field define */
++
++/*  When TLB table entry un-usable case occurs, SW set this bit to \
++ *  inform to retry reading the TLB table entry again.*/
++#define DC_RETRY_LBIT			(4)
++#define DC_RETRY_HBIT			(7)
++#define DC_RETRY_MASK        \
++	GENMASK(DC_RETRY_HBIT, DC_RETRY_LBIT)
++#define DC_CH0_RETRY                    BIT(4)
++#define DC_CH1_RETRY		        BIT(5)
++#define DC_CH2_RETRY                    BIT(6)
++#define DC_CH3_RETRY                    BIT(7)
++
++/*  Write 1 to invalidate all TLB caches. */
++#define DC_INVLD_LBIT	                (0)
++#define DC_INVLD_HBIT		        (3)
++#define DC_INVLD_MASK        \
++	GENMASK(DC_INVLD_HBIT, DC_INVLD_LBIT)
++#define DC_CH0_INVLD         	        BIT(0)
++#define DC_CH1_INVLD		        BIT(1)
++#define DC_CH2_INVLD                    BIT(2)
++#define DC_CH3_INVLD		  	BIT(3)
++#define DC_ALL_INVLD		  	(0xF)
++
++/* TLB VPNX Status(VPNX) bit field define */
++
++/* When working in TLB enable case, if the relative TLB table
++ * entry in the external DDR is un-useable, VPU will record its
++ * virtual address bit31:12 into VPN. SW can read-out VPN for
++ * TLB table entry,s rebuilding.*/
++#define	DC_VPNX_LBIT			(12)
++#define DC_VPNX_HBIT			(31)
++#define DC_VPNX_MASK		\
++	GENMASK(DC_VPNX_HBIT, DC_VPNX_LBIT)
++
++/* TLB table entry verification(TLBV) bit field define */
++
++/* Check bit ignored(ignore the vld bit for PEntry, SEntry in memory*/
++#define DC_RCI				BIT(31)
++/* Check number mask */
++#define DC_CNM_LBIT	                (16)
++#define DC_CNM_HBIT                     (27)
++#define DC_CNM_MASK		\
++	GENMASK(DC_CNM_HBIT, DC_CNM_LBIT)
++/* Golden Check number,
++ * VPU will check its secondary table entry to judge whether it is valid.
++ * If (GCN & CNM) == (TLB entry data readed by TLB [11:0] &CNM)
++ * indicates current entry is valid, otherwise it is unusable.*/
++#define DC_GCN_LBIT                     (0)
++#define DC_GCN_HBIT                     (11)
++#define DC_GCN_MASK          \
++	GENMASK(DC_GCN_HBIT, DC_GCN_LBIT)
++
++/* SCH status(STAT) bit field define */
++
++/* CH3 TLB error occurs. Write 0 to cleared */
++#define DC_CH3_TLB_ERR			BIT(3)
++/* CH2 TLB error occurs. Write 0 to cleared */
++#define DC_CH2_TLB_ERR			BIT(2)
++/* CH1 TLB error occurs. Write 0 to cleared */
++#define DC_CH1_TLB_ERR			BIT(1)
++/* CH0 TLB error occurs. Write 0 to cleared */
++#define DC_CH0_TLB_ERR			BIT(0)
++
++/* CscMultYRv */
++
++#define DC_CSC_MULT_Y_LBIT		(0)
++#define DC_CSC_MULT_Y_HBIT		(10)
++#define DC_CSC_MULT_Y_MASK        \
++	GENMASK(DC_CSC_MULT_Y_HBIT, DC_CSC_MULT_Y_LBIT)
++#define DC_CSC_MULT_Y_MD0		(0x400) << DC_CSC_MULT_Y_LBIT
++#define DC_CSC_MULT_Y_MD1		(0x4a8) << DC_CSC_MULT_Y_LBIT
++#define DC_CSC_MULT_Y_MD2		(0x400) << DC_CSC_MULT_Y_LBIT
++#define DC_CSC_MULT_Y_MD3		(0x47c) << DC_CSC_MULT_Y_LBIT
++
++#define DC_CSC_MULT_RV_LBIT		(16)
++#define DC_CSC_MULT_RV_HBIT		(26)
++#define DC_CSC_MULT_RV_MASK        \
++	GENMASK(DC_CSC_MULT_RV_HBIT, DC_CSC_MULT_RV_LBIT)
++#define DC_CSC_MULT_RV_MD0		(0x48f) << DC_CSC_MULT_RV_LBIT
++#define DC_CSC_MULT_RV_MD1		(0x662) << DC_CSC_MULT_RV_LBIT
++#define DC_CSC_MULT_RV_MD2		(0x59c) << DC_CSC_MULT_RV_LBIT
++#define DC_CSC_MULT_RV_MD3		(0x57c) << DC_CSC_MULT_RV_LBIT
++
++/* CscMultGuGv */
++
++#define DC_CSC_MULT_GU_LBIT		(0)
++#define DC_CSC_MULT_GU_HBIT		(8)
++#define DC_CSC_MULT_GU_MASK        \
++	GENMASK(DC_CSC_MULT_GU_HBIT, DC_CSC_MULT_GU_LBIT)
++#define DC_CSC_MULT_GU_MD0		(0x193) << DC_CSC_MULT_GU_LBIT
++#define DC_CSC_MULT_GU_MD1		(0x190) << DC_CSC_MULT_GU_LBIT
++#define DC_CSC_MULT_GU_MD2		(0x160) << DC_CSC_MULT_GU_LBIT
++#define DC_CSC_MULT_GU_MD3		(0x15a) << DC_CSC_MULT_GU_LBIT
++
++#define DC_CSC_MULT_GV_LBIT		(16)
++#define DC_CSC_MULT_GV_HBIT		(25)
++#define DC_CSC_MULT_GV_MASK        \
++	GENMASK(DC_CSC_MULT_GV_HBIT, DC_CSC_MULT_GV_LBIT)
++#define DC_CSC_MULT_GV_MD0		(0x253) << DC_CSC_MULT_GV_LBIT
++#define DC_CSC_MULT_GV_MD1		(0x341) << DC_CSC_MULT_GV_LBIT
++#define DC_CSC_MULT_GV_MD2		(0x2db) << DC_CSC_MULT_GV_LBIT
++#define DC_CSC_MULT_GV_MD3		(0x2cb) << DC_CSC_MULT_GV_LBIT
++
++/* CscMultBu */
++
++#define DC_CSC_MULT_BU_LBIT		(0)
++#define DC_CSC_MULT_BU_HBIT		(11)
++#define DC_CSC_MULT_BU_MASK        \
++	GENMASK(DC_CSC_MULT_BU_HBIT, DC_CSC_MULT_BU_LBIT)
++#define DC_CSC_MULT_BU_MD0		(0x820) << DC_CSC_MULT_BU_LBIT
++#define DC_CSC_MULT_BU_MD1		(0x812) << DC_CSC_MULT_BU_LBIT
++#define DC_CSC_MULT_BU_MD2		(0x717) << DC_CSC_MULT_BU_LBIT
++#define DC_CSC_MULT_BU_MD3		(0x6ee) << DC_CSC_MULT_BU_LBIT
++
++/* CscSubYUV */
++
++#define DC_CSC_SUB_Y_LBIT		(0)
++#define DC_CSC_SUB_Y_HBIT		(4)
++#define DC_CSC_SUB_Y_MASK        \
++	GENMASK(DC_CSC_SUB_Y_HBIT, DC_CSC_SUB_Y_LBIT)
++#define DC_CSC_SUB_Y_MD0		(0x00) << DC_CSC_SUB_Y_LBIT
++#define DC_CSC_SUB_Y_MD1		(0x00) << DC_CSC_SUB_Y_LBIT
++#define DC_CSC_SUB_Y_MD2		(0x00) << DC_CSC_SUB_Y_LBIT
++#define DC_CSC_SUB_Y_MD3		(0x00) << DC_CSC_SUB_Y_LBIT
++
++#define DC_CSC_SUB_UV_LBIT		(16)
++#define DC_CSC_SUB_UV_HBIT		(23)
++#define DC_CSC_SUB_UV_MASK        \
++	GENMASK(DC_CSC_SUB_UV_HBIT, DC_CSC_SUB_UV_LBIT)
++#define DC_CSC_SUB_UV_MD0		(0x00) << DC_CSC_SUB_UV_LBIT
++#define DC_CSC_SUB_UV_MD1		(0x80) << DC_CSC_SUB_UV_LBIT
++#define DC_CSC_SUB_UV_MD2		(0x80) << DC_CSC_SUB_UV_LBIT
++#define DC_CSC_SUB_UV_MD3		(0x80) << DC_CSC_SUB_UV_LBIT
++
++/* Common(DISP_COM) bit field define */
++
++/* Dither drop bit. */
++#define DC_DP_DITHER_DW_LBIT		(16)
++#define DC_DP_DITHER_DW_HBIT		(21)
++#define DC_DP_DITHER_DW_MASK        \
++	GENMASK(DC_DP_DITHER_DW_HBIT, DC_DP_DITHER_DW_LBIT)
++#define DC_DP_DITHER_DW_BLUE_LBIT       (16)
++#define DC_DP_DITHER_DW_GREEN_LBIT      (18)
++#define DC_DP_DITHER_DW_RED_LBIT        (20)
++#define DC_DP_DITHER_DROP_0_BITS	(0)
++#define DC_DP_DITHER_DROP_2_BITS	(1)
++#define DC_DP_DITHER_DROP_3_BITS	(2)
++#define DC_DP_DITHER_DROP_4_BITS	(3)
++#define	DC_RGB888_TO_RGB565_DITHER	(0b100110) << DC_DP_DITHER_DW_LBIT
++#define	DC_RGB888_TO_RGB666_DITHER	(0b010101) << DC_DP_DITHER_DW_LBIT
++/* Dither Clk gate enable */
++#define DC_DITHER_CLKGATE_EN		BIT(4)
++/* SLCD Clk gate enable */
++#define DC_SLCD_CLKGATE_EN			BIT(3)
++/* TFT Clk gate enable */
++#define DC_TFT_CLKGATE_EN			BIT(2)
++/* Dither enable. 1:dither enable 0:dither disable */
++#define DC_DP_DITHER_EN			BIT(4)
++/* Display interfaces select. 1:TFT 2:SLCD */
++
++#define DC_DP_IF_SEL_LBIT		(0)
++#define DC_DP_IF_SEL_HBIT		(1)
++#define DC_DP_IF_SEL_MASK		GENMASK(DC_DP_IF_SEL_HBIT, DC_DP_IF_SEL_LBIT)
++#define	DC_DISP_COM_NO_DISP		(0b00) << DC_DP_IF_SEL_LBIT
++#define	DC_DISP_COM_TFT			(0b01) << DC_DP_IF_SEL_LBIT
++#define	DC_DISP_COM_SLCD		(0b10) << DC_DP_IF_SEL_LBIT
++#define	DC_DISP_COM_MIPI_SLCD		(0b11) << DC_DP_IF_SEL_LBIT
++
++/* TIMING_HSYNC(TFT_TIMING_HSYNC) bit field define */
++
++/* HSYNC pulse start point(base on dot clock cycle) */
++#define DC_HPS_LBIT			(16)
++#define DC_HPS_HBIT			(27)
++#define DC_HPS_MASK           \
++	GENMASK(DC_HPS_HBIT, DC_HPS_LBIT)
++/* HSYNC pulse end point(base on dot clock cycle) */
++#define DC_HPE_LBIT			(0)
++#define DC_HPE_HBIT			(11)
++#define DC_HPE_MASK           \
++	GENMASK(DC_HPE_HBIT, DC_HPE_LBIT)
++
++/* TIMING_VSYNC(TFT_TIMING_VSYNC) bit field define */
++
++/* VSYNC pulse start point(base on dot clock cycle) */
++#define DC_VPS_LBIT			(16)
++#define DC_VPS_HBIT			(27)
++#define DC_VPS_MASK           \
++	GENMASK(DC_VPS_HBIT, DC_VPS_LBIT)
++/* VSYNC pulse end point(base on dot clock cycle) */
++#define DC_VPE_LBIT			(0)
++#define DC_VPE_HBIT			(11)
++#define DC_VPE_MASK           \
++	GENMASK(DC_VPE_HBIT, DC_VPE_LBIT)
++
++/* TIMING_HDE(TFT_TIMING_HDE) bit field define */
++
++/* Horizontal display area start point (base on dot clock cycle).
++ * And it is also the DE pulse start point in horizontal.
++ * It indicate the end point of vertical back porch.*/
++#define DC_HDS_LBIT			(16)
++#define DC_HDS_HBIT			(27)
++#define DC_HDS_MASK              \
++	GENMASK(HDE_HDS_HBIT, DC_HDS_LBIT)
++/* Horizontal display area end point (base on dot clock cycle).
++ * And it is also the DE pulse end point in horizontal.
++ * It indicate the end point of horizontal front porch.*/
++#define DC_HDE_LBIT			(0)
++#define DC_HDE_HBIT			(11)
++#define DC_HDE_MASK              \
++	GENMASK(DC_HDE_HBIT, DC_HDE_LBIT)
++
++/* TIMING_VDE(TFT_TIMING_VDE) bit field define */
++
++/* Vertical display area start point(base on dot clock cycle).
++ * And it is also the DE pulse start point in vertical.
++ * It indicate the end point of vertical back porch. */
++#define DC_VDS_LBIT			(16)
++#define DC_VDS_HBIT			(27)
++#define DC_VDS_MASK               \
++	GENMASK(VDE_VDS_HBIT, DC_VDS_LBIT)
++/*  Vertical display area end point(base on dot clock cycle).
++ *  And it is also the DE pulse end point in vertical.
++ *  It indicate the start point of vertical front porch. */
++#define DC_VDE_LBIT			(0)
++#define DC_VDE_HBIT			(11)
++#define DC_VDE_MASK               \
++	GENMASK(DC_VDE_HBIT, DC_VDE_LBIT)
++
++/* TRANS_CONFIG(TFT_TRAN_CFG) bit field define */
++
++/* Inverse the polarity of the DOT_CLK */
++#define	DC_PIX_CLK_INV			BIT(10)
++/* Default level of DE(invalid level) */
++#define	DC_DE_DL			BIT(9)
++/* Default level of HSYNC and VSYNC(invalid level) */
++#define DC_SYNC_DL			BIT(8)
++#define DC_VSYNC_DL			BIT(7)
++/* Output color mode of even lines(2,4,6...) */
++#define DC_COLOR_EVEN_LBIT		(19)
++#define DC_COLOR_EVEN_HBIT		(21)
++#define DC_COLOR_EVEN_MASK        \
++	GENMASK(DC_COLOR_EVEN_HBIT, DC_COLOR_EVEN_LBIT)
++#define DC_EVEN_RGB             	(0b000) << DC_COLOR_EVEN_LBIT
++#define DC_EVEN_RBG             	(0b001) << DC_COLOR_EVEN_LBIT
++#define DC_EVEN_BGR             	(0b010) << DC_COLOR_EVEN_LBIT
++#define DC_EVEN_BRG             	(0b011) << DC_COLOR_EVEN_LBIT
++#define DC_EVEN_GBR             	(0b100) << DC_COLOR_EVEN_LBIT
++#define DC_EVEN_GRB             	(0b101) << DC_COLOR_EVEN_LBIT
++/* Output color mode of odd lines(1, 3, 5...) */
++#define DC_COLOR_ODD_LBIT		(16)
++#define DC_COLOR_ODD_HBIT		(18)
++#define DC_COLOR_ODD_MASK          \
++	GENMASK(DC_COLOR_ODD_HBIT, DC_COLOR_ODD_LBIT)
++#define DC_ODD_RGB			(0b000) << DC_COLOR_ODD_LBIT
++#define DC_ODD_RBG			(0b001) << DC_COLOR_ODD_LBIT
++#define DC_ODD_BGR			(0b010) << DC_COLOR_ODD_LBIT
++#define DC_ODD_BRG			(0b011) << DC_COLOR_ODD_LBIT
++#define DC_ODD_GBR			(0b100) << DC_COLOR_ODD_LBIT
++#define DC_ODD_GRB			(0b101) << DC_COLOR_ODD_LBIT
++/* 0x:0x: 24bits parallel mode
++ * 10: 8bits serial mode without dummy(RGB)
++ * 11: 8bits serial mode with dummy(RGBD)*/
++#define DC_MODE_LBIT			(0)
++#define DC_MODE_HBIT		        (2)
++#define DC_MODE_MASK               \
++	GENMASK(DC_MODE_HBIT, DC_MODE_LBIT)
++#define DC_MODE_PARALLEL_888		(0b000) << DC_MODE_LBIT
++#define DC_MODE_PARALLEL_666		(0b001) << DC_MODE_LBIT
++#define DC_MODE_PARALLEL_565		(0b010) << DC_MODE_LBIT
++#define DC_MODE_SERIAL_8BIT_RGB	        (0b100) << DC_MODE_LBIT
++#define DC_MODE_SERIAL_8BIT_RGBD	(0b101) << DC_MODE_LBIT
++
++/* STATUS(TFT_ST) bit field define */
++
++/* 0: TFT is not working 1: TFT is working */
++#define	DC_TFT_WORKING			BIT(1)
++/* Indicate the controller jump into recovery state,
++ * and starting trans one frame 0 to panel.
++ * 0: TFT is working order 1: TFT is in UNDER mode.*/
++#define	DC_TFT_UNDER			BIT(0)
++
++/* SLCD_CONFIG(SLCD_PANEL_CFG) bit field define */
++
++/* Anti-jitter for RDY.
++ * 0: sample RDY with 1 pixclk cycle(default)
++ * 1: sample RDY with 3 pixclk cycles for anti-jitter.*/
++#define	DC_RDY_ANTI_JIT			BIT(27)
++/* Whether the pixel data or command need conversion
++ * 0: no use conversion, such as parameter of command(default)
++ * 1: need conversion, such as pixel data*/
++#define	DC_FMT_EN			BIT(26)
++/*  001: typeA(6800) 010: typeB(8080)(default) 100: typeC(SPI) */
++#define DC_DBI_TYPE_LBIT		(23)
++#define DC_DBI_TYPE_HBIT		(25)
++#define DC_DBI_TYPE_MASK        \
++	GENMASK(DC_DBI_TYPE_HBIT, DC_DBI_TYPE_LBIT)
++#define	DC_DBI_TYPE_A_6800		(0b001) << DC_DBI_TYPE_LBIT
++#define	DC_DBI_TYPE_B_8080		(0b010) << DC_DBI_TYPE_LBIT
++#define DC_DBI_TYPE_C_SPI_3             (0b100) << DC_DBI_TYPE_LBIT
++#define DC_DBI_TYPE_C_SPI_4             (0b101) << DC_DBI_TYPE_LBIT
++/* Color format.
++ * 00: 565  01: 666 10: 888(default) */
++#define DC_DATA_FMT_LBIT		(21)
++#define DC_DATA_FMT_HBIT		(22)
++#define DC_DATA_FMT_MASK        \
++	GENMASK(DC_DATA_FMT_HBIT, DC_DATA_FMT_LBIT)
++#define DC_DATA_FMT_565			(0b00) << DC_DATA_FMT_LBIT
++#define DC_DATA_FMT_444			(0b01) << DC_DATA_FMT_LBIT
++#define DC_DATA_FMT_666			(0b01) << DC_DATA_FMT_LBIT
++#define DC_DATA_FMT_888			(0b10) << DC_DATA_FMT_LBIT
++/*  Anti-jitter for TE.
++ *  0: sample TE with 1 pixclk cycle;
++ *  1: sample TE with 3 pixclk cycles for anti-jitter(default).*/
++#define	DC_TE_ANTI_JIT	                BIT(20)
++/* The active edge of TE.
++ * 0: the front edge(default) 1: the back edge*/
++#define	DC_TE_MD			BIT(19)
++/* 0: do not wait TE, send pix_data after SLCD_START;
++ * 1: wait TE, and then send pix_data.(default)*/
++#define	DC_TE_SWITCH	        	BIT(18)
++/* 0: do not wait RDY, send command or data immediately;(default)
++ * 1: wait RDY, and then send command or data. */
++#define	DC_RDY_SWITCH			BIT(17)
++/* CS control enable.
++ * 0: The CS pin is controlled by GPIO.(default)
++ * 1: The CS pin is controlled by Display Controller. */
++#define	DC_CS_EN			BIT(16)
++/* The CS's default polarity
++ * 0: the default(invalid) level is low;
++ * 1: the default(invalid) level is high;(default) */
++#define	DC_CS_DP			BIT(11)
++/* The RDY's default polarity
++ * 0: the default(invalid) level is low;
++ * 1: the default(invalid) level is high;(default) */
++#define	DC_RDY_DP			BIT(10)
++/* DC's definition.
++ * 0: Command DC = low, Data DC = high(default)
++ * 1: Command DC = high, Data DC = low */
++#define	DC_DC_MD			BIT(9)
++/* WR's default polarity.
++ * 0: drive at posedge, and sample at negedge;
++ * 1: drive at negedge, and sample at posedge.(default) */
++#define	DC_WR_DP			BIT(8)
++///* SPI_CLK Polarity.
++// * 0: Active edge is Falling(default)
++// * 1: Active edge is Rising Used for serial transfer mode. */
++//#define	DC_CLKPLY			BIT(7)
++
++#define DC_TE_MIPI_SWITCH		BIT(7)
++
++/* The TE' default polarity
++ * 0: the default(invalid) level is low;(default)
++ * 1: the default(invalid) level is high; */
++#define	DC_TE_DP			BIT(6)
++/* Panel's data width. It's also used in MIPI DSI command mod
++ * 000: 8bits 001: 9bits 010: 16bits 011: 18bits 100: 24bits(default)  */
++#define DC_DWIDTH_LBIT			(3)
++#define DC_DWIDTH_HBIT			(5)
++#define DC_DWIDTH_MASK        \
++	GENMASK(DC_DWIDTH_HBIT, DC_DWIDTH_LBIT)
++#define	DC_DWIDTH_8BITS			(0b000) << DC_DWIDTH_LBIT
++#define	DC_DWIDTH_9BITS			(0b001) << DC_DWIDTH_LBIT
++#define	DC_DWIDTH_16BITS		(0b010) << DC_DWIDTH_LBIT
++#define	DC_DWIDTH_18BITS		(0b011) << DC_DWIDTH_LBIT
++#define	DC_DWIDTH_24BITS		(0b100) << DC_DWIDTH_LBIT
++/* The width of panel's command and it's parameters
++ * 000: 8bits(default) 001: 9bits 010: 16bits 011: 18bits 100: 24bits */
++#define DC_CWIDTH_LBIT			(0)
++#define DC_CWIDTH_HBIT			(2)
++#define DC_CWIDTH_MASK        \
++	GENMASK(DC_CWIDTH_HBIT, DC_CWIDTH_LBIT)
++#define	DC_CWIDTH_8BITS			(0b000) << DC_CWIDTH_LBIT
++#define	DC_CWIDTH_9BITS			(0b001) << DC_CWIDTH_LBIT
++#define	DC_CWIDTH_16BITS		(0b010) << DC_CWIDTH_LBIT
++#define	DC_CWIDTH_18BITS		(0b011) << DC_CWIDTH_LBIT
++#define	DC_CWIDTH_24BITS		(0b100) << DC_CWIDTH_LBIT
++
++/* SLCD_WR_DUTY(SLCD_WR_DUTY) bit field define */
++
++/* WR's high time period when transmitting data
++ * (base on MIPI DBI Type B, and this is low time at Type A) */
++#define DC_DSTIME_LBIT			(24)
++#define DC_DSTIME_HBIT			(31)
++#define DC_DSTIME_MASK        \
++	GENMASK(DC_DSTIME_HBIT, DC_DSTIME_LBIT)
++/* WR's low time period when transmitting data
++ * (base on MIPI DBI Type B, and this is high time at Type A) */
++#define DC_DDTIME_LBIT			(16)
++#define DC_DDTIME_HBIT			(23)
++#define DC_DDTIME_MASK        \
++	GENMASK(DC_DDTIME_HBIT, DC_DDTIME_LBIT)
++/* WR's high time period when transmitting command
++ * (base on MIPI DBI Type B, and this is low time at Type A) */
++#define DC_CSTIME_LBIT			(8)
++#define DC_CSTIME_HBIT			(15)
++#define DC_CSTIME_MASK        \
++	GENMASK(DC_CSTIME_HBIT, DC_CSTIME_LBIT)
++/* WR's low time period when transmitting command
++ * (base on MIPI DBI Type B, and this is high time at Type A) */
++#define DC_CDTIME_LBIT			(0)
++#define DC_CDTIME_HBIT			(7)
++#define DC_CDTIME_MASK        \
++	GENMASK(DC_CDTIME_HBIT, DC_CDTIME_LBIT)
++
++/* SLCD_TIMING(SLCD_TIMING) bit field define */
++#define DC_TCH_LBIT			(24)
++#define DC_TCH_HBIT			(31)
++#define DC_TCH_MASK        \
++	GENMASK(DC_TCH_HBIT, DC_TCH_LBIT)
++#define DC_TCS_LBIT			(16)
++#define DC_TCS_HBIT			(23)
++#define DC_TCS_MASK        \
++	GENMASK(DC_TCS_HBIT, DC_TCS_LBIT)
++#define DC_TAH_LBIT			(8)
++#define DC_TAH_HBIT			(15)
++#define DC_TAH_MASK        \
++	GENMASK(DC_TAH_HBIT, DC_TAH_LBIT)
++#define DC_TAS_LBIT			(0)
++#define DC_TAS_HBIT			(7)
++#define DC_TAS_MASK        \
++	GENMASK(DC_TAS_HBIT, DC_TAS_LBIT)
++
++/* SLCD_FRM_SIZE(SLCD_FRM_SIZE) bit field define */
++
++/* Line number of each frame. */
++#define DC_SLCD_FRM_V_SIZE_LBIT		(16)
++#define DC_SLCD_FRM_V_SIZE_HBIT		(31)
++#define DC_SLCD_FRM_V_SIZE_MASK        \
++	GENMASK(DC_SLCD_FRM_V_SIZE_HBIT, DC_SLCD_FRM_V_SIZE_LBIT)
++/* Pixel number of each line. */
++#define DC_SLCD_FRM_H_SIZE_LBIT		(0)
++#define DC_SLCD_FRM_H_SIZE_HBIT		(15)
++#define DC_SLCD_FRM_H_SIZE_MASK        \
++	GENMASK(DC_SLCD_FRM_H_SIZE_HBIT, DC_SLCD_FRM_H_SIZE_LBIT)
++
++/* SLCD_SLOW_TIME(SLCD_SLOW_TIME) bit field define */
++
++/* SLCD will delay some period of pixclk before transmitting data,
++ * after TE鈥檚 relative edge. */
++#define DC_SLOW_TIME_LBIT			(0)
++#define DC_SLOW_TIME_HBIT			(15)
++#define DC_SLOW_TIME_MASK         \
++	GENMASK(DC_SLOW_TIME_HBIT, DC_SLOW_TIME_LBIT)
++
++/* SLCD_REG_IF(SLCD_REG_IF) bit field define */
++
++/* It is used to decide the meanings of the DATA/CMD/PARAMETER.
++ * 00: pix_data; 01: parameter; 1x: command(default). */
++#define DC_SLCD_REG_IF_FLAG_LBIT		(30)
++#define DC_SLCD_REG_IF_FLAG_HBIT		(31)
++#define DC_SLCD_REG_IF_FLAG_MASK       \
++	GENMASK(DC_SLCD_REG_IF_FLAG_HBIT, DC_SLCD_REG_IF_FLAG_LBIT)
++#define DC_SLCD_REG_IF_FLAG_DATA		(0b00) << DC_SLCD_REG_IF_FLAG_LBIT
++#define DC_SLCD_REG_IF_FLAG_PRM			(0b01) << DC_SLCD_REG_IF_FLAG_LBIT
++#define DC_SLCD_REG_IF_FLAG_CMD			(0b10) << DC_SLCD_REG_IF_FLAG_LBIT
++/* Indicate this is the last content, the hardware will disable the CS */
++#define	DC_SLCD_REG_IF_END		        BIT(29)
++/* content */
++#define DC_SLCD_REG_IF_CONTENT_LBIT	(0)
++#define DC_SLCD_REG_IF_CONTENT_HBIT	(23)
++#define DC_SLCD_REG_IF_CONTENT_MASK     \
++	GENMASK(DC_SLCD_REG_IF_CONTENT_HBIT, DC_SLCD_REG_IF_CONTENT_LBIT)
++
++/* SLCD_STATUS(SLCD_ST) bit field define */
++
++/* Indicate whether the SLCD DBI interface controller is working or not.
++ * 0: idle 1: busy */
++#define DC_SLCD_ST_BUSY			BIT(0)
++
++#endif /* _DPU_REG_H_ */
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer.c
+new file mode 100644
+index 000000000..79d6a2c8f
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer.c
+@@ -0,0 +1,135 @@
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++#include <linux/poll.h>
++#include <linux/wait.h>
++#include <linux/fs.h>
++#include <linux/irq.h>
++#include <linux/mm.h>
++#include <linux/fb.h>
++#include <linux/delay.h>
++#include <linux/ctype.h>
++#include <linux/dma-mapping.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/memory.h>
++#include <linux/suspend.h>
++#include <linux/string.h>
++#include <linux/kthread.h>
++#include <linux/gpio.h>
++#include <asm/cacheflush.h>
++#include <linux/of_address.h>
++
++#include "hw_composer.h"
++
++struct hw_composer_master *hw_comp_master;
++
++struct hw_composer_master * hw_composer_init(struct dpu_ctrl *dctrl)
++{
++	int ret = 0;
++
++	hw_comp_master = kzalloc(sizeof(struct hw_composer_master), GFP_KERNEL);
++	if(IS_ERR_OR_NULL(hw_comp_master)) {
++		return -ENOMEM;
++	}
++
++	hw_comp_master->dctrl = dctrl;
++
++	/*comp mutex??*/
++	mutex_init(&hw_comp_master->lock);
++
++	return hw_comp_master;
++}
++EXPORT_SYMBOL(hw_composer_init);
++
++
++void hw_composer_exit(struct hw_composer_master *comp_master)
++{
++	mutex_destroy(&comp_master->lock);
++
++	if(comp_master) {
++		kfree(comp_master);
++	}
++}
++EXPORT_SYMBOL(hw_composer_exit);
++
++struct hw_composer_ctx *hw_composer_create(void *priv_data)
++{
++	struct hw_composer_ctx *ctx = kzalloc(sizeof(struct hw_composer_ctx), GFP_KERNEL);
++
++	if(IS_ERR_OR_NULL(ctx)) {
++		return -ENOMEM;
++	}
++	/*设置ctx的master.*/
++	ctx->master = hw_comp_master;
++
++	ctx->block = 1;
++
++	INIT_LIST_HEAD(&ctx->list);
++
++	/*添加到ctx链表.*/
++
++	return ctx;
++}
++EXPORT_SYMBOL(hw_composer_create);
++
++int hw_composer_destroy(struct hw_composer_ctx *ctx)
++{
++
++	list_del(&ctx->list);
++	kfree(ctx);
++
++	return 0;
++}
++EXPORT_SYMBOL(hw_composer_destroy);
++
++void hw_composer_lock(struct hw_composer_ctx *ctx)
++{
++	mutex_lock(&ctx->master->lock);
++}
++EXPORT_SYMBOL(hw_composer_lock);
++
++void hw_composer_unlock(struct hw_composer_ctx *ctx)
++{
++	mutex_unlock(&ctx->master->lock);
++}
++EXPORT_SYMBOL(hw_composer_unlock);
++
++int hw_composer_setup(struct hw_composer_ctx *ctx, struct comp_setup_info *comp_info)
++{
++	/*TODO: check comp_info.*/
++
++	memcpy(&ctx->comp_info, comp_info, sizeof(struct comp_setup_info));
++	return 0;
++}
++EXPORT_SYMBOL(hw_composer_setup);
++
++
++int hw_composer_start(struct hw_composer_ctx *ctx)
++{
++	struct hw_composer_master *master = ctx->master;
++	struct dpu_ctrl *dctrl = master->dctrl;
++	int ret = 0;
++
++	ret = dpu_ctrl_comp_setup(dctrl, &ctx->comp_info);
++	ret = dpu_ctrl_comp_start(dctrl, ctx->block);
++
++	return ret;
++}
++EXPORT_SYMBOL(hw_composer_start);
++
++int hw_composer_stop(struct hw_composer_ctx *ctx)
++{
++	struct hw_composer_master *master = ctx->master;
++	struct dpu_ctrl *dctrl = master->dctrl;
++	int ret = 0;
++
++	// TODO:
++	dpu_ctrl_comp_stop(dctrl, QCK_STOP);
++
++	return ret;
++}
++EXPORT_SYMBOL(hw_composer_stop);
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer.h b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer.h
+new file mode 100644
+index 000000000..37b20db21
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer.h
+@@ -0,0 +1,40 @@
++#ifndef __HW_COMPOSER_H__
++#define __HW_COMPOSER_H__
++
++#include "dpu_ctrl.h"
++
++
++struct hw_composer_master {
++	int mode;
++	struct mutex lock;
++	struct dpu_ctrl *dctrl;
++};
++
++struct hw_composer_ctx {
++	struct hw_composer_master *master;
++	struct list_head list;
++	int block;	// 当�composer工作模�，是阻塞的还是�阻塞的.
++
++	struct comp_setup_info comp_info;	/* current comp settings.*/
++};
++
++/*hw_composer驱动�始化*/
++struct hw_composer_master *hw_composer_init(struct dpu_ctrl *dctrl);
++
++void hw_composer_exit(struct hw_composer_master *comp_master);
++
++struct hw_composer_ctx *hw_composer_create(void *data);
++
++int hw_composer_destroy(struct hw_composer_ctx *ctx);
++
++int hw_composer_setup(struct hw_composer_ctx *ctx, struct comp_setup_info *comp_info);
++
++int hw_composer_start(struct hw_composer_ctx *ctx);
++
++int hw_composer_stop(struct hw_composer_ctx *ctx);
++
++void hw_composer_lock(struct hw_composer_ctx *ctx);
++
++void hw_composer_unlock(struct hw_composer_ctx *ctx);
++
++#endif
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer_fb.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer_fb.c
+new file mode 100644
+index 000000000..a58118f67
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer_fb.c
+@@ -0,0 +1,871 @@
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++#include <linux/poll.h>
++#include <linux/wait.h>
++#include <linux/fs.h>
++#include <linux/irq.h>
++#include <linux/mm.h>
++#include <linux/fb.h>
++#include <linux/delay.h>
++#include <linux/ctype.h>
++#include <linux/dma-mapping.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/memory.h>
++#include <linux/suspend.h>
++#include <linux/string.h>
++#include <linux/kthread.h>
++#include <linux/gpio.h>
++#include <asm/cacheflush.h>
++#include <linux/of_address.h>
++
++#include "dpu_reg.h"
++#include "hw_composer.h"
++#include "hw_composer_fb.h"
++
++#include <libdmmu.h>
++
++static int hw_compfb_update_vidmem(struct hw_compfb_device *compfb);
++
++const struct fb_fix_screeninfo compfb_layer_fix[]  = {
++	{
++	.id = "layer0",
++	.type = FB_TYPE_PACKED_PIXELS,
++	.visual = FB_VISUAL_TRUECOLOR,
++	.xpanstep = 0,
++	.ypanstep = 1,
++	.ywrapstep = 0,
++	.accel = FB_ACCEL_NONE,
++	},
++	{
++	.id = "layer1",
++	.type = FB_TYPE_PACKED_PIXELS,
++	.visual = FB_VISUAL_TRUECOLOR,
++	.xpanstep = 0,
++	.ypanstep = 1,
++	.ywrapstep = 0,
++	.accel = FB_ACCEL_NONE,
++	},
++	{
++	.id = "layer2",
++	.type = FB_TYPE_PACKED_PIXELS,
++	.visual = FB_VISUAL_TRUECOLOR,
++	.xpanstep = 0,
++	.ypanstep = 1,
++	.ywrapstep = 0,
++	.accel = FB_ACCEL_NONE,
++	},
++	{
++	.id = "layer3",
++	.type = FB_TYPE_PACKED_PIXELS,
++	.visual = FB_VISUAL_TRUECOLOR,
++	.xpanstep = 0,
++	.ypanstep = 1,
++	.ywrapstep = 0,
++	.accel = FB_ACCEL_NONE,
++	},
++};
++
++static struct compfb_colormode compfb_colormodes[] = {
++	{
++		.mode = LAYER_CFG_FORMAT_RGB888,
++		.name = "rgb888",
++		.color = LAYER_CFG_COLOR_RGB,
++		.bits_per_pixel = 32,
++		.nonstd = 0,
++		.color = LAYER_CFG_COLOR_RGB,
++		.red	= { .length = 8, .offset = 16, .msb_right = 0 },
++		.green	= { .length = 8, .offset = 8, .msb_right = 0 },
++		.blue	= { .length = 8, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 0, .offset = 0, .msb_right = 0 },
++	}, {
++		.mode = LAYER_CFG_FORMAT_ARGB8888,
++		.name = "argb888",
++		.bits_per_pixel = 32,
++		.nonstd = 0,
++		.color = LAYER_CFG_COLOR_RGB,
++		.red	= { .length = 8, .offset = 16, .msb_right = 0 },
++		.green	= { .length = 8, .offset = 8, .msb_right = 0 },
++		.blue	= { .length = 8, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 8, .offset = 24, .msb_right = 0 },
++	}, {
++		.mode = LAYER_CFG_FORMAT_RGB555,
++		.name = "rgb555",
++		.color = LAYER_CFG_COLOR_RGB,
++		.bits_per_pixel = 16,
++		.nonstd = 0,
++		.red	= { .length = 5, .offset = 10, .msb_right = 0 },
++		.green	= { .length = 5, .offset = 5, .msb_right = 0 },
++		.blue	= { .length = 5, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 0, .offset = 0, .msb_right = 0 },
++	}, {
++		.mode = LAYER_CFG_FORMAT_ARGB1555,
++		.name = "argb1555",
++		.color = LAYER_CFG_COLOR_RGB,
++		.bits_per_pixel = 16,
++		.nonstd = 0,
++		.red	= { .length = 5, .offset = 10, .msb_right = 0 },
++		.green	= { .length = 5, .offset = 5, .msb_right = 0 },
++		.blue	= { .length = 5, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 1, .offset = 15, .msb_right = 0 },
++	}, {
++		.mode = LAYER_CFG_FORMAT_RGB565,
++		.name = "rgb565",
++		.color = LAYER_CFG_COLOR_RGB,
++		.bits_per_pixel = 16,
++		.nonstd = 0,
++		.red	= { .length = 5, .offset = 11, .msb_right = 0 },
++		.green	= { .length = 6, .offset = 5, .msb_right = 0 },
++		.blue	= { .length = 5, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 0, .offset = 0, .msb_right = 0 },
++	}, {
++		.mode = LAYER_CFG_FORMAT_YUV422,
++		.name = "yuv422",
++		.bits_per_pixel = 16,
++		.nonstd = LAYER_CFG_FORMAT_YUV422,
++	}, {
++		.mode = LAYER_CFG_FORMAT_NV12,
++		.name = "nv12",
++		.bits_per_pixel = 12,
++		.nonstd = LAYER_CFG_FORMAT_NV12,
++	}, {
++		.mode = LAYER_CFG_FORMAT_NV21,
++		.name = "nv21",
++		.bits_per_pixel = 12,
++		.nonstd = LAYER_CFG_FORMAT_NV21,
++	},
++};
++
++static struct compfb_colormode compfb_wback_colormodes[] = {
++	{
++		.mode = DC_WB_FORMAT_888,
++		.name = "rgb888",
++		.color = LAYER_CFG_COLOR_RGB, //TODO
++		.bits_per_pixel = 32,
++		.nonstd = 0,
++		.color = LAYER_CFG_COLOR_RGB,
++		.red	= { .length = 8, .offset = 16, .msb_right = 0 },
++		.green	= { .length = 8, .offset = 8, .msb_right = 0 },
++		.blue	= { .length = 8, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 0, .offset = 0, .msb_right = 0 },
++	}, {
++		.mode = DC_WB_FORMAT_8888,
++		.name = "argb888",
++		.bits_per_pixel = 32,
++		.nonstd = 0,
++		.color = LAYER_CFG_COLOR_RGB,
++		.red	= { .length = 8, .offset = 16, .msb_right = 0 },
++		.green	= { .length = 8, .offset = 8, .msb_right = 0 },
++		.blue	= { .length = 8, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 8, .offset = 24, .msb_right = 0 },
++	}, {
++		.mode = DC_WB_FORMAT_555,
++		.name = "rgb555",
++		.color = LAYER_CFG_COLOR_RGB,
++		.bits_per_pixel = 16,
++		.nonstd = 0,
++		.red	= { .length = 5, .offset = 10, .msb_right = 0 },
++		.green	= { .length = 5, .offset = 5, .msb_right = 0 },
++		.blue	= { .length = 5, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 0, .offset = 0, .msb_right = 0 },
++	}, {
++		.mode = DC_WB_FORMAT_565,
++		.name = "rgb565",
++		.color = LAYER_CFG_COLOR_RGB,
++		.bits_per_pixel = 16,
++		.nonstd = 0,
++		.red	= { .length = 5, .offset = 11, .msb_right = 0 },
++		.green	= { .length = 6, .offset = 5, .msb_right = 0 },
++		.blue	= { .length = 5, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 0, .offset = 0, .msb_right = 0 },
++	},
++};
++
++
++
++/* export hw_composer layers to /dev/fbX */
++
++
++static int compfb_open(struct fb_info *info, int user)
++{
++	return 0;
++}
++static int compfb_release(struct fb_info *info, int user)
++{
++	return 0;
++}
++
++static int compfb_set_par(struct fb_info *info)
++{
++	//TODO:
++
++	return 0;
++}
++
++static void compfb_videomode_to_var(struct fb_var_screeninfo *var,
++		const struct fb_videomode *mode)
++{
++	var->left_margin = mode->left_margin;
++	var->right_margin = mode->right_margin;
++	var->upper_margin = mode->upper_margin;
++	var->lower_margin = mode->lower_margin;
++	var->hsync_len = mode->hsync_len;
++	var->vsync_len = mode->vsync_len;
++	var->sync = mode->sync;
++	var->vmode = mode->vmode & FB_VMODE_MASK;
++	var->pixclock = mode->pixclock;
++}
++
++static void export_info_to_var(struct fb_var_screeninfo *var,
++		struct export_info *info, int layer)
++{
++	struct ingenicfb_frm_cfg *frm_cfg = &info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	int nframes = info->layer_frames[layer];
++
++	var->xres = lay_cfg->source_w;
++	var->yres = lay_cfg->source_h;
++	var->xres_virtual = lay_cfg->source_w;
++	var->yres_virtual = lay_cfg->source_h * nframes;
++	var->xoffset = 0;
++	var->yoffset = 0;
++}
++
++static void compfb_colormode_to_var(struct fb_var_screeninfo *var,
++		struct compfb_colormode *color)
++{
++	var->bits_per_pixel = color->bits_per_pixel;
++	var->nonstd = color->nonstd;
++	var->red = color->red;
++	var->green = color->green;
++	var->blue = color->blue;
++	var->transp = color->transp;
++}
++
++static bool cmp_component(struct fb_bitfield *f1, struct fb_bitfield *f2)
++{
++	return f1->length == f2->length &&
++		f1->offset == f2->offset &&
++		f1->msb_right == f2->msb_right;
++}
++static bool cmp_var_to_colormode(struct fb_var_screeninfo *var,
++		struct compfb_colormode *color)
++{
++
++	if (var->bits_per_pixel == 0 ||
++			var->red.length == 0 ||
++			var->blue.length == 0 ||
++			var->green.length == 0)
++		return 0;
++
++	return var->bits_per_pixel == color->bits_per_pixel &&
++		cmp_component(&var->red, &color->red) &&
++		cmp_component(&var->green, &color->green) &&
++		cmp_component(&var->blue, &color->blue) &&
++		cmp_component(&var->transp, &color->transp);
++}
++
++
++static int compfb_check_colormode(struct fb_var_screeninfo *var, uint32_t *mode)
++{
++	int i;
++
++	if (var->nonstd) {
++		for (i = 0; i < ARRAY_SIZE(compfb_colormodes); ++i) {
++			struct compfb_colormode *m = &compfb_colormodes[i];
++			if (var->nonstd == m->nonstd) {
++				compfb_colormode_to_var(var, m);
++				*mode = m->mode;
++				return 0;
++			}
++		}
++
++		return -EINVAL;
++	}
++
++	for (i = 0; i < ARRAY_SIZE(compfb_colormodes); ++i) {
++		struct compfb_colormode *m = &compfb_colormodes[i];
++		if (cmp_var_to_colormode(var, m)) {
++			compfb_colormode_to_var(var, m);
++			*mode = m->mode;
++			return 0;
++		}
++	}
++	/* To support user libraries that only support RGB format */
++	for (i = 0; i < ARRAY_SIZE(compfb_colormodes); ++i) {
++		struct compfb_colormode *m = &compfb_colormodes[i];
++		if (var->bits_per_pixel == m->bits_per_pixel) {
++			compfb_colormode_to_var(var, m);
++			*mode = m->mode;
++			return 0;
++		}
++	}
++
++	return -EINVAL;
++}
++
++
++static int compfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++	struct hw_compfb_device *compfb = info->par;
++	struct fb_videomode *mode = compfb->active_video_mode;
++	uint32_t colormode;
++	int ret;
++
++	compfb_videomode_to_var(var, mode);
++
++	ret = compfb_check_colormode(var, &colormode);
++	if(ret) {
++		dev_err(info->dev,"Check colormode failed!\n");
++		return  ret;
++	}
++
++	return 0;
++}
++
++static inline uint32_t convert_color_to_hw(unsigned val, struct fb_bitfield *bf)
++{
++	return (((val << bf->length) + 0x7FFF - val) >> 16) << bf->offset;
++}
++
++static int compfb_setcolreg(unsigned regno, unsigned red, unsigned green,
++		unsigned blue, unsigned transp, struct fb_info *fb)
++{
++	if (regno >= 16)
++		return -EINVAL;
++
++	((uint32_t *)(fb->pseudo_palette))[regno] =
++		convert_color_to_hw(red, &fb->var.red) |
++		convert_color_to_hw(green, &fb->var.green) |
++		convert_color_to_hw(blue, &fb->var.blue) |
++		convert_color_to_hw(transp, &fb->var.transp);
++
++	return 0;
++}
++
++static int compfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++	struct hw_compfb_device *compfb = info->par;
++	struct comp_setup_info *comp_info = &compfb->comp_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &comp_info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = frm_cfg->lay_cfg;
++
++	int layer = -1;
++	int next_frm = 0;
++	int i = 0;
++
++	for(i = 0; i < DPU_SUPPORT_MAX_LAYERS; i++) {
++		if(info == compfb->fbs[i]) {
++			layer = i;
++			break;
++		}
++	}
++
++	if(var->xoffset != 0 || layer < 0) {
++		return -EINVAL;
++	}
++
++	hw_composer_lock(compfb->comp_ctx);
++	/*�能和unexport产生冲�，当comp_ctx被释放时，此时应该返回�法.*/
++	if(!compfb->comp_ctx) {
++		hw_composer_unlock(compfb->comp_ctx);
++		return -EINVAL;
++	}
++
++
++	next_frm = var->yoffset / var->yres;
++
++	/*更新lay_cfg信�.*/
++	/*修改layer信�，需�加�.*/
++
++	hw_compfb_update_vidmem(compfb);
++
++	if(compfb->vidmem_phys[layer][next_frm]) {
++		lay_cfg[layer].addr[0] = compfb->vidmem_phys[layer][next_frm];
++		lay_cfg[layer].uv_addr[0] = compfb->vidmem_phys[layer][next_frm] + lay_cfg[layer].stride * lay_cfg[layer].source_h;
++	} else {
++		dev_err(compfb->dev, "Error address for pan display!, please check\n");
++	}
++
++	/*更新comp_setup_info 并且�动 composer. */
++	hw_composer_setup(compfb->comp_ctx, &compfb->comp_info);
++	hw_composer_start(compfb->comp_ctx);
++
++	hw_composer_unlock(compfb->comp_ctx);
++
++	return 0;
++}
++
++static int compfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
++{
++	void __user *argp = (void __user *)arg;
++
++	switch (cmd) {
++		/*composer 在调用hw_composer_start时,能��vsync, 此时�需��处�.*/
++		case FBIO_WAITFORVSYNC:
++			break;
++		default:
++			break;
++	}
++
++	return 0;
++}
++
++
++static struct fb_ops compfb_layerx_ops = {
++	.owner 		= THIS_MODULE,
++	.fb_open 	= compfb_open,
++	.fb_release 	= compfb_release,
++	.fb_check_var 	= compfb_check_var,
++	.fb_set_par 	= compfb_set_par,
++	.fb_setcolreg 	= compfb_setcolreg,
++	.fb_pan_display = compfb_pan_display,
++	.fb_write	= ingenicfb_write,
++	.fb_fillrect 	= cfb_fillrect,
++	.fb_copyarea 	= cfb_copyarea,
++	.fb_imageblit 	= cfb_imageblit,
++	.fb_ioctl 	= compfb_ioctl,
++	.fb_mmap 	= ingenicfb_mmap,
++};
++
++static ssize_t
++compfb_wback_read(struct fb_info *info, char __user *buf, size_t count, loff_t *ppos)
++{
++	unsigned long p = *ppos;
++	struct hw_compfb_device *compfb = info->par;
++	u8 *buffer, *dst;
++	u8 __iomem *src;
++	int c, cnt = 0, err = 0;
++	unsigned long total_size;
++	int ret = 0;
++
++	if (!info || ! info->screen_base)
++		return -ENODEV;
++
++	if (info->state != FBINFO_STATE_RUNNING)
++		return -EPERM;
++
++	/*Wait wback complete.*/
++	ret = hw_composer_start(compfb->comp_ctx);
++	if(ret < 0) {
++		return ret;
++	}
++
++	return 0;
++
++	total_size = info->screen_size;
++
++	if (total_size == 0)
++		total_size = info->fix.smem_len;
++
++	if (p >= total_size)
++		return 0;
++
++	if (count >= total_size)
++		count = total_size;
++
++	if (count + p > total_size)
++		count = total_size - p;
++
++	buffer = kmalloc((count > PAGE_SIZE) ? PAGE_SIZE : count,
++			 GFP_KERNEL);
++	if (!buffer)
++		return -ENOMEM;
++
++	src = (u8 __iomem *) (info->screen_base + p);
++
++	if (info->fbops->fb_sync)
++		info->fbops->fb_sync(info);
++
++	while (count) {
++		c  = (count > PAGE_SIZE) ? PAGE_SIZE : count;
++		dst = buffer;
++		fb_memcpy_fromfb(dst, src, c);
++		dst += c;
++		src += c;
++
++		if (copy_to_user(buf, buffer, c)) {
++			err = -EFAULT;
++			break;
++		}
++		*ppos += c;
++		buf += c;
++		cnt += c;
++		count -= c;
++	}
++
++	kfree(buffer);
++
++	return (err) ? err : cnt;
++}
++
++
++static struct fb_ops compfb_wback_ops = {
++	.owner = THIS_MODULE,
++	.fb_open = compfb_open,
++	.fb_release = compfb_release,
++	.fb_read = compfb_wback_read,
++	.fb_check_var = compfb_check_var,
++	.fb_set_par = compfb_set_par,
++	.fb_setcolreg = compfb_setcolreg,
++	.fb_fillrect = cfb_fillrect,
++	.fb_copyarea = cfb_copyarea,
++	.fb_imageblit = cfb_imageblit,
++	.fb_mmap = ingenicfb_mmap,
++};
++
++static int hw_compfb_directout_comp_info(struct hw_compfb_device *compfb)
++{
++	struct comp_setup_info *comp_info = &compfb->comp_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &comp_info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = frm_cfg->lay_cfg;
++	struct fb_videomode *mode = compfb->active_video_mode;
++	int i = 0;
++
++	compfb->comp_ctx->block = 0;	//使用�阻塞的方�.
++	comp_info->nframes = 1;
++	comp_info->out_mode = COMP_DIRECT_OUT;
++
++	frm_cfg->width = mode->xres;
++	frm_cfg->height = mode->yres;
++	frm_cfg->wback_info.en = 0;	//关闭写回功能.
++
++	return 0;
++}
++
++static int hw_compfb_wback_comp_info(struct hw_compfb_device *compfb)
++{
++	struct comp_setup_info *comp_info = &compfb->comp_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &comp_info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = frm_cfg->lay_cfg;
++	struct fb_videomode *mode = compfb->active_video_mode;
++	int i = 0;
++
++	compfb->comp_ctx->block = 1;	//使用�阻塞的方�.
++	comp_info->nframes = 1;
++	//comp_info->out_mode = COMP_WRITE_BACK;
++
++	frm_cfg->width = mode->xres;
++	frm_cfg->height = mode->yres;
++
++	frm_cfg->wback_info.addr = compfb->wback_phys;
++	frm_cfg->wback_info.stride = 1280 * 2;
++	frm_cfg->wback_info.fmt = compfb->wb_color_mode->color;
++
++	frm_cfg->wback_info.en = 1;	//关闭写回功能.
++
++	return 0;
++}
++
++static int hw_compfb_update_comp_info(struct hw_compfb_device *compfb)
++{
++	struct comp_setup_info *comp_info = &compfb->comp_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &comp_info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = frm_cfg->lay_cfg;
++	struct fb_videomode *mode = compfb->active_video_mode;
++	struct export_info *info = &compfb->export_info;
++	struct ingenicfb_frm_cfg *update_frm_cfg = &info->frm_cfg;
++	struct ingenicfb_lay_cfg *update_lay_cfg = update_frm_cfg->lay_cfg;
++	int i = 0;
++
++	for(i = 0; i < DPU_SUPPORT_MAX_LAYERS; i++) {
++		lay_cfg[i].lay_z_order  = update_lay_cfg[i].lay_z_order; /* top */
++		lay_cfg[i].lay_en 	= update_lay_cfg[i].lay_en;
++		lay_cfg[i].source_w 	= update_lay_cfg[i].source_w;
++		lay_cfg[i].source_h 	= update_lay_cfg[i].source_h;
++		lay_cfg[i].disp_pos_x 	= update_lay_cfg[i].disp_pos_x;
++		lay_cfg[i].disp_pos_y 	= update_lay_cfg[i].disp_pos_y;
++
++
++		if(lay_cfg[i].lay_en == 1) {
++			lay_cfg[i].scale_w 	= update_lay_cfg[i].scale_w;
++			lay_cfg[i].scale_h 	= update_lay_cfg[i].scale_h;
++			if(update_lay_cfg[i].source_w != update_lay_cfg[i].scale_w ||
++					update_lay_cfg[i].source_h != update_lay_cfg[i].scale_h) {
++				lay_cfg[i].lay_scale_en = 1;
++			}
++		} else {
++			/*Scale must be zero if layer not enabled.*/
++			lay_cfg[i].lay_scale_en = 0;
++			lay_cfg[i].scale_w 	= 0;
++			lay_cfg[i].scale_h 	= 0;
++		}
++
++		lay_cfg[i].g_alpha_en = 0;
++		lay_cfg[i].g_alpha_val = 128;
++		lay_cfg[i].stride 	= update_lay_cfg[i].stride;
++		lay_cfg[i].uv_stride 	= update_lay_cfg[i].uv_stride;
++
++	}
++
++	for(i = 0; i < DPU_SUPPORT_MAX_LAYERS; i++) {
++		if(compfb->export_info.layer_exported[i] == 1) {
++
++			/*update lay cfg.*/
++			lay_cfg[i].color  = update_lay_cfg[i].color
++				= compfb->color_modes[i]->color;
++			lay_cfg[i].format = update_lay_cfg[i].format
++				= compfb->color_modes[i]->mode;
++
++		} else {
++			lay_cfg[i].color = 0;
++			lay_cfg[i].format = 0;
++		}
++
++        if (!lay_cfg[i].addr[0]) {
++		if(update_lay_cfg[i].addr[0]) {
++			lay_cfg[i].addr[0] = update_lay_cfg[i].addr[0];
++			lay_cfg[i].uv_addr[0] = update_lay_cfg[i].uv_addr[0];
++			lay_cfg[i].tlb_en = update_lay_cfg[i].tlb_en =
++				update_lay_cfg[i].addr[0] < 0x80000000 ? 1:0;
++		} else {
++			lay_cfg[i].addr[0] = compfb->vidmem_phys[i][0];
++			lay_cfg[i].uv_addr[0] = compfb->vidmem_phys[i][0] + lay_cfg[i].stride * lay_cfg[i].source_h;
++		}
++		}
++
++	}
++
++	return 0;
++}
++
++static int hw_compfb_update_fb_info(struct hw_compfb_device *compfb)
++{
++	struct export_info *info = &compfb->export_info;
++	int i;
++
++
++	for(i = 0; i < DPU_SUPPORT_MAX_LAYERS; i++) {
++		if(!compfb->fbs[i]) {
++			continue;
++		}
++
++		/*update fb infos*/
++		export_info_to_var(&compfb->fbs[i]->var, info, i);
++
++		int color_mode = info->layer_color_mode[i];
++		/*update fb_info var color mode*/
++		compfb->color_modes[i] = &compfb_colormodes[color_mode];
++
++		compfb_colormode_to_var(&compfb->fbs[i]->var, compfb->color_modes[i]);
++
++		compfb->fbs[i]->fix.line_length = (compfb->fbs[i]->var.bits_per_pixel * compfb->fbs[i]->var.xres) >> 3;
++	}
++	return 0;
++
++}
++
++int hw_compfb_update(struct hw_compfb_device *compfb)
++{
++
++	hw_composer_lock(compfb->comp_ctx);
++
++	/*lock*/
++	hw_compfb_update_fb_info(compfb);
++
++	hw_compfb_update_vidmem(compfb);
++
++	hw_compfb_update_comp_info(compfb);
++
++	hw_composer_setup(compfb->comp_ctx, &compfb->comp_info);
++	hw_composer_start(compfb->comp_ctx);
++
++	hw_composer_unlock(compfb->comp_ctx);
++	return 0;
++}
++
++static int hw_compfb_export_layer(struct hw_compfb_device *compfb, int layer)
++{
++	struct export_info *info = &compfb->export_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[layer];
++	int color_mode = lay_cfg->format;
++	struct fb_info *fb_layer = NULL;
++	/* unsigned int frame_size = info->layer_frame_size_w[layer] * info->layer_frame_size_h[layer] * 4; //TODO: rgb申请的buffer， 32bit �个pixel, 对于nv12的�需� w * h * 3 / 2. 能够节�很多空间. */
++	unsigned int frame_size = info->layer_frame_size_w[layer] * info->layer_frame_size_h[layer] * compfb_colormodes[info->layer_color_mode[layer]].bits_per_pixel / 8;
++
++	int nframes = info->layer_frames[layer];
++	unsigned int buff_size = 0;
++	int i = 0;
++	int ret = 0;
++
++	/*�制最大帧数，并且更新到export info.*/
++	info->layer_frames[layer] = nframes = nframes > CONFIG_FB_INGENIC_NR_FRAMES ? CONFIG_FB_INGENIC_NR_FRAMES : nframes;
++	buff_size = nframes * frame_size;
++
++
++	compfb->vidmem[layer][0] = dma_alloc_coherent(compfb->dev, buff_size, &compfb->vidmem_phys[layer][0], GFP_KERNEL);
++
++	if(compfb->vidmem[layer][0] == NULL) {
++		dev_err(compfb->dev, "Failed to alloc vidmem for layer %d, buff_size: %d\n", layer, buff_size);
++		//TODO error handle....
++	}
++	compfb->vidmem_size[layer] = buff_size;
++
++	compfb->fbs[layer] = framebuffer_alloc(sizeof(struct hw_compfb_device), compfb->dev);
++	if(compfb->fbs[layer] == NULL) {
++		dev_err(compfb->dev, "Failed to alloc framebuffer for layer: %d\n", layer);
++		return -ENOMEM;
++	}
++
++	compfb->fbs[layer]->par = compfb;
++
++	fb_layer = compfb->fbs[layer];
++
++	fb_videomode_to_modelist(compfb->active_video_mode, 1, &fb_layer->modelist);
++	compfb_videomode_to_var(&fb_layer->var, compfb->active_video_mode);
++	export_info_to_var(&fb_layer->var, info, layer);
++
++	fb_layer->fbops = &compfb_layerx_ops;
++	fb_layer->flags = FBINFO_DEFAULT;
++	fb_layer->var.width = compfb->panel->width; //TODO, 这里指尺寸.
++	fb_layer->var.height = compfb->panel->height;
++
++	compfb->color_modes[layer] = &compfb_colormodes[color_mode];
++	compfb_colormode_to_var(&fb_layer->var, compfb->color_modes[layer]);
++
++	fb_layer->fix 			= compfb_layer_fix[layer];
++	fb_layer->fix.line_length 	= (fb_layer->var.bits_per_pixel * fb_layer->var.xres) >> 3;
++	fb_layer->fix.smem_start 	= compfb->vidmem_phys[layer][0];
++	fb_layer->fix.smem_len 		= compfb->vidmem_size[layer];
++	fb_layer->screen_size 		= fb_layer->fix.line_length * fb_layer->var.yres;
++	fb_layer->screen_base 		= compfb->vidmem[layer][0];
++	fb_layer->pseudo_palette 	= compfb->pseudo_palette;
++	ret = register_framebuffer(fb_layer);
++	if(ret) {
++		dev_err(compfb->dev, "Failed to register framebuffer layer : %d\n", layer);
++	}
++
++
++	return ret;
++}
++
++static int hw_compfb_update_vidmem(struct hw_compfb_device *compfb)
++{
++	/*update vidmem info.*/
++	struct export_info *info = &compfb->export_info;
++	int i,j;
++
++	for(i = 0; i < DPU_SUPPORT_MAX_LAYERS; i++) {
++		struct fb_info *fb_layer = compfb->fbs[i];
++
++		if(!fb_layer) {
++			continue;
++		}
++
++		int nframes = info->layer_frames[i];
++		unsigned int layer_size = fb_layer->fix.line_length * fb_layer->var.yres;
++		unsigned int vidmem = compfb->vidmem[i][0];
++		unsigned int vidmem_phys = compfb->vidmem_phys[i][0];
++
++		for(j = 0; j < nframes; j++) {
++			compfb->vidmem[i][j] = vidmem + j*layer_size;
++			compfb->vidmem_phys[i][j] = vidmem_phys + j*layer_size;
++		}
++
++	}
++
++	return 0;
++}
++
++int hw_compfb_export2(struct hw_compfb_device *compfb, struct export_info *info)
++{
++
++	int i = 0;
++	int ret = 0;
++
++	if(compfb->exported) {
++		return -EBUSY;
++	}
++
++	compfb->comp_ctx = hw_composer_create(compfb);
++	if(IS_ERR_OR_NULL(compfb->comp_ctx)) {
++		dev_err(compfb->dev, "Faield to create ctx for compfb!\n");
++		return -ENOMEM;
++	}
++
++	hw_composer_lock(compfb->comp_ctx);
++
++	/* export layer. */
++	for(i = 0; i < DPU_SUPPORT_MAX_LAYERS; i++) {
++		if(info->layer_exported[i] == 1) {
++			ret = hw_compfb_export_layer(compfb, i);
++			if(ret < 0) {
++				dev_err(compfb->dev, "Failed to export layer %d\n", i);
++			}
++		}
++	}
++
++	/* export wback. */
++
++
++	compfb->exported = 1;
++
++	hw_composer_unlock(compfb->comp_ctx);
++
++	return ret;
++
++}
++
++void hw_compfb_unexport(struct hw_compfb_device *compfb)
++{
++	int i = 0;
++
++	if(compfb->exported == 0) {
++		return;
++	}
++
++	hw_composer_lock(compfb->comp_ctx);
++
++	if(compfb->comp_ctx) {
++		hw_composer_stop(compfb->comp_ctx);
++		hw_composer_destroy(compfb->comp_ctx);
++		compfb->comp_ctx = NULL;
++	}
++	hw_composer_unlock(compfb->comp_ctx);
++
++	for(i = 0; i < DPU_SUPPORT_MAX_LAYERS; i++) {
++		if(compfb->fbs[i]) {
++			unregister_framebuffer(compfb->fbs[i]);
++			framebuffer_release(compfb->fbs[i]);
++			compfb->fbs[i] = NULL;
++
++			if(compfb->vidmem[i][0]) {
++				dma_free_coherent(compfb->dev, compfb->vidmem_size[i], compfb->vidmem[i][0], compfb->vidmem_phys[i][0]);
++			}
++		}
++	}
++
++	compfb->exported = 0;
++}
++
++
++/* 主设备�始化compfb数�结构. */
++struct hw_compfb_device *hw_compfb_init(void *data)
++{
++	struct hw_compfb_device *compfb = kzalloc(sizeof(struct hw_compfb_device), GFP_KERNEL);
++	if(IS_ERR_OR_NULL(compfb)) {
++		return -ENOMEM;
++	}
++
++	/*xxx Init Stuffs.. */
++
++	return compfb;
++}
++
++int hw_compfb_exit(struct hw_compfb_device *compfb)
++{
++
++	if(compfb) {
++		kfree(compfb);
++	}
++
++	return 0;
++}
++
++
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer_fb.h b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer_fb.h
+new file mode 100644
+index 000000000..0db0e957c
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer_fb.h
+@@ -0,0 +1,84 @@
++#ifndef __HW_COMPFB_DEVICE_H__
++#define __HW_COMPFB_DEVICE_H__
++
++
++struct compfb_colormode {
++	uint32_t mode;
++	const char *name;
++	uint32_t color;
++	uint32_t bits_per_pixel;
++	uint32_t nonstd;
++	struct fb_bitfield red;
++	struct fb_bitfield green;
++	struct fb_bitfield blue;
++	struct fb_bitfield transp;
++};
++
++struct export_info {
++	int layer_exported[DPU_SUPPORT_MAX_LAYERS];
++	int layer_frames[DPU_SUPPORT_MAX_LAYERS];	/*how many framebuffers for layer.*/
++	int layer_frame_size_w[DPU_SUPPORT_MAX_LAYERS];	/*存储当�layer最大frame宽高, 设置的src_size必须�于frame_size.*/
++	int layer_frame_size_h[DPU_SUPPORT_MAX_LAYERS];
++	int layer_color_mode[DPU_SUPPORT_MAX_LAYERS];		/*存储当�layer的格�信�.*/
++	int wback_exported;
++
++	struct ingenicfb_frm_cfg frm_cfg;
++};
++
++struct hw_compfb_device {
++
++	struct fb_info *fbs[DPU_SUPPORT_MAX_LAYERS];
++	struct fb_info *wbfb;
++	struct hw_composer_ctx *comp_ctx;
++	struct hw_composer_master *comp_master;
++	struct device *dev;
++	struct lcd_panel *panel;
++
++	int logo_pan_layer;	//init logo pan layer.
++
++
++	struct export_info export_info;
++
++	/*�个Layer的显存.*/
++	unsigned char *vidmem[DPU_SUPPORT_MAX_LAYERS][CONFIG_FB_INGENIC_NR_FRAMES];
++	dma_addr_t vidmem_phys[DPU_SUPPORT_MAX_LAYERS][CONFIG_FB_INGENIC_NR_FRAMES];
++	unsigned int vidmem_size[DPU_SUPPORT_MAX_LAYERS];
++	unsigned int frm_size[DPU_SUPPORT_MAX_LAYERS];
++
++	/*writeback memory*/
++	dma_addr_t wback_phys;
++	unsigned int wback_vidmem;
++
++	int exported;		/*state of export*/
++	unsigned int pseudo_palette[16];
++
++	struct fb_videomode *active_video_mode;
++
++	struct comp_setup_info comp_info;	//实例化direct out �置.
++
++	struct compfb_colormode *color_modes[DPU_SUPPORT_MAX_LAYERS];//当��层使用的colormode.
++	struct compfb_colormode *wb_color_mode;//当��层使用的colormode.
++};
++
++
++
++struct hw_compfb_device *hw_compfb_init(void *data);
++
++int hw_compfb_exit(struct hw_compfb_device *compfb);
++
++int hw_compfb_export(struct hw_compfb_device *compfb, unsigned int width, unsigned int height, int wback);
++
++/* export composer layer and writback mem to fb.*/
++int hw_compfb_export2(struct hw_compfb_device *compfb, struct export_info *info);
++
++void hw_compfb_unexport(struct hw_compfb_device *compfb);
++
++/* update composer configurations after export or modify layer configs. */
++int hw_compfb_update(struct hw_compfb_device *compfb);
++
++extern int ingenicfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
++extern ssize_t ingenicfb_write(struct fb_info *info, const char __user *buf,
++			    size_t count, loff_t *ppos);
++
++extern const struct fb_fix_screeninfo ingenicfb_fix;
++#endif
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer_v4l2.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer_v4l2.c
+new file mode 100644
+index 000000000..1681d906d
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer_v4l2.c
+@@ -0,0 +1,737 @@
++//v4l2_video.c --> export to v4l2 subsystem.
++//support hw acc functions:
++// CSC:
++//	YUV -> RGB; RGB -> YUV
++// Scale:
++//	Scale functions.
++//
++// v4l2 m2m frameworks.
++// Output : mmap/userptr/dmabuf.
++//	userptr can use dmmu for input.
++// Capture: mmap/userptr/dmabuf.
++
++
++#include <linux/module.h>
++#include <linux/fs.h>
++#include <linux/version.h>
++#include <linux/timer.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/of.h>
++
++#include <linux/platform_device.h>
++#include <media/v4l2-mem2mem.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ioctl.h>
++#include <media/videobuf2-core.h>
++#include <media/videobuf2-dma-contig-ingenic.h>
++#include <media/ingenic_video_nr.h>
++
++#include "hw_composer.h"
++#include "hw_composer_v4l2.h"
++
++#define DPU_DRIVER_NAME "dpu-csc-scaler"
++
++
++static struct dpu_fmt formats[] = {
++	{
++		.name	= "NV12",
++		.fourcc	= V4L2_PIX_FMT_NV12,
++		.layer_fmt = LAYER_CFG_FORMAT_NV12,
++		.depth	= 16,
++		.types	= MEM2MEM_OUTPUT,
++	},
++	{
++		.name	= "NV21",
++		.fourcc	= V4L2_PIX_FMT_NV21,
++		.layer_fmt = LAYER_CFG_FORMAT_NV21,
++		.depth	= 16,
++		.types	= MEM2MEM_OUTPUT,
++	},
++	{
++		.name	= "YUV 422",
++		.fourcc	= V4L2_PIX_FMT_VYUY,
++		.layer_fmt = LAYER_CFG_FORMAT_YUV422,
++		.depth	= 16,
++		.types	= MEM2MEM_OUTPUT,
++	},
++	{//TODO
++		.name	= "MONO8",
++		.fourcc	= V4L2_PIX_FMT_SBGGR8,
++		.depth	= 16,
++		.types	= MEM2MEM_OUTPUT,
++	},
++	{//TODO
++		.name = "MONO16",
++		.fourcc = V4L2_PIX_FMT_SBGGR16,
++		.depth = 16,
++		.types = MEM2MEM_OUTPUT,
++	},
++	/*input and wback formts.*/
++	{
++		.name	= "RGB_565",
++		.fourcc	= V4L2_PIX_FMT_RGB565,
++		.layer_fmt = LAYER_CFG_FORMAT_RGB565,
++		.wb_fmt = DC_WB_FORMAT_565,
++		.depth	= 16,
++		.types	= MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
++	},
++	{
++		.name	= "RGB_888",
++		.fourcc	= V4L2_PIX_FMT_RGB24,
++		.layer_fmt = LAYER_CFG_FORMAT_RGB888,
++		.wb_fmt = DC_WB_FORMAT_888,
++		.depth	= 32,
++		.types	= MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
++	},
++	{
++		.name	= "ARGB_8888",
++		.fourcc	= V4L2_PIX_FMT_ARGB32,
++		.layer_fmt = LAYER_CFG_FORMAT_ARGB8888,
++		.wb_fmt = DC_WB_FORMAT_8888,
++		.depth	= 32,
++		.types	= MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
++	},
++};
++
++#define NUM_FORMATS ARRAY_SIZE(formats)
++
++static struct dpu_fmt *find_fmt(struct v4l2_format *f)
++{
++	unsigned int i;
++	for (i = 0; i < NUM_FORMATS; i++) {
++		if (formats[i].fourcc == f->fmt.pix.pixelformat)
++			return &formats[i];
++	}
++	return NULL;
++}
++
++static int vidioc_querycap(struct file *file, void *priv,
++				struct v4l2_capability *cap)
++{
++	strncpy(cap->driver, DPU_DRIVER_NAME, sizeof(cap->driver) - 1);
++	strncpy(cap->card, DPU_DRIVER_NAME, sizeof(cap->card) - 1);
++	cap->bus_info[0] = 0;
++	cap->version = KERNEL_VERSION(4, 4, 19);
++	/*
++	 * This is only a mem-to-mem video device. The capture and output
++	 * device capability flags are left only for backward compatibility
++	 * and are scheduled for removal.
++	 */
++	cap->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M;
++	cap->capabilities =  cap->device_caps |
++		V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
++		V4L2_CAP_DEVICE_CAPS;
++
++	return 0;
++}
++
++static inline struct ingenic_dpu_ctx *fh_to_ctx(struct v4l2_fh *fh)
++{
++	return container_of(fh, struct ingenic_dpu_ctx, fh);
++}
++
++static int enum_fmt(struct v4l2_fmtdesc *f, u32 type)
++{
++	int i, num;
++	struct dpu_fmt *fmt;
++
++	num = 0;
++	for (i = 0; i < NUM_FORMATS; ++i) {
++		if (formats[i].types & type) {
++			/* index-th format of type type found ? */
++			if (num == f->index)
++				break;
++			/* Correct type but haven't reached our index yet,
++			 * just increment per-type index */
++			++num;
++		}
++	}
++
++	if (i < NUM_FORMATS) {
++		/* Format found */
++		fmt = &formats[i];
++		strncpy(f->description, fmt->name, sizeof(f->description) - 1);
++		f->pixelformat = fmt->fourcc;
++		return 0;
++	}
++
++	/* Format not found */
++	return -EINVAL;
++}
++
++static int vidioc_try_fmt(struct file *file, void *prv, struct v4l2_format *f)
++{
++	struct dpu_fmt *fmt;
++	enum v4l2_field *field;
++
++	fmt = find_fmt(f);
++	if (!fmt)
++		return -EINVAL;
++
++	field = &f->fmt.pix.field;
++	if (*field == V4L2_FIELD_ANY)
++		*field = V4L2_FIELD_NONE;
++	else if (*field != V4L2_FIELD_NONE)
++		return -EINVAL;
++
++	if (f->fmt.pix.width > MAX_WIDTH
++		|| f->fmt.pix.height > MAX_HEIGHT
++		|| f->fmt.pix.width < MIN_WIDTH
++		|| f->fmt.pix.height < MIN_HEIGHT) {
++		return -EINVAL;
++	}
++
++	f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3;
++	f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
++	return 0;
++}
++static struct dpu_frame_info *get_frame(struct ingenic_dpu_ctx *ctx,
++		enum v4l2_buf_type type)
++{
++	switch (type) {
++	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++		return &ctx->out_info;
++	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++		return &ctx->cap_info;
++	default:
++		return ERR_PTR(-EINVAL);
++	}
++}
++static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
++				   struct v4l2_fmtdesc *f)
++{
++	return enum_fmt(f, MEM2MEM_CAPTURE);
++}
++
++static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
++				   struct v4l2_fmtdesc *f)
++{
++	return enum_fmt(f, MEM2MEM_OUTPUT);
++}
++
++static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f)
++{
++	struct ingenic_dpu_ctx *ctx = fh_to_ctx(prv);
++	struct vb2_queue *vq;
++	struct dpu_frame_info *frame;
++
++	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
++	if (!vq)
++		return -EINVAL;
++	frame = get_frame(ctx, f->type);
++	if (IS_ERR(frame))
++		return PTR_ERR(frame);
++
++	f->fmt.pix.width		= frame->width;
++	f->fmt.pix.height		= frame->height;
++	f->fmt.pix.field		= V4L2_FIELD_NONE;
++	f->fmt.pix.pixelformat		= frame->fmt->fourcc;
++	f->fmt.pix.bytesperline		= (frame->width * frame->fmt->depth) >> 3;
++	f->fmt.pix.sizeimage		= frame->size;
++	return 0;
++}
++
++static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f)
++{
++	struct ingenic_dpu_ctx *ctx = fh_to_ctx(prv);
++	struct ingenic_dpu_dev *dev = ctx->dpu_dev;
++	struct vb2_queue *vq;
++	struct dpu_frame_info *frame;
++	struct dpu_fmt *fmt;
++	int ret = 0;
++
++	/* Adjust all values accordingly to the hardware capabilities
++	 * and chosen format. */
++	ret = vidioc_try_fmt(file, prv, f);
++	if (ret)
++		return ret;
++	vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
++	if (vb2_is_busy(vq)) {
++		v4l2_err(&dev->v4l2_dev, "queue (%d) bust\n", f->type);
++		return -EBUSY;
++	}
++	frame = get_frame(ctx, f->type);
++	if (IS_ERR(frame))
++		return PTR_ERR(frame);
++	fmt = find_fmt(f);
++	if (!fmt)
++		return -EINVAL;
++	frame->width	= f->fmt.pix.width;
++	frame->height	= f->fmt.pix.height;
++	frame->size		= f->fmt.pix.sizeimage;
++	frame->fmt		= fmt;
++	frame->bytesperline	= f->fmt.pix.bytesperline;
++	return 0;
++}
++
++static int vidioc_streamon(struct file *file, void *priv,
++					enum v4l2_buf_type type)
++{
++	struct ingenic_dpu_ctx *ctx = priv;
++
++	return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
++}
++
++static int vidioc_streamoff(struct file *file, void *priv,
++					enum v4l2_buf_type type)
++{
++	struct ingenic_dpu_ctx *ctx = priv;
++
++	return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
++}
++
++static int dpu_queue_setup(struct vb2_queue *vq,
++			   unsigned int *nbuffers, unsigned int *nplanes,
++			   unsigned int sizes[], struct device *alloc_ctxs[])
++{
++	struct ingenic_dpu_ctx *ctx = vb2_get_drv_priv(vq);
++	struct dpu_frame_info *frame = get_frame(ctx, vq->type);
++
++	if (IS_ERR(frame))
++		return PTR_ERR(frame);
++
++	*nplanes = 1;
++	sizes[0] = frame->size;
++	alloc_ctxs[0] = (struct device *)ctx->dpu_dev->alloc_ctx;
++
++	if (*nbuffers == 0)
++		*nbuffers = 1;
++
++	return 0;
++}
++
++static int dpu_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	//struct ingenic_dpu_ctx *ctx = container_of(ctrl->handler, struct ingenic_dpu_ctx,ctrl_handler);
++	//TODO
++	return 0;
++}
++
++static const struct v4l2_ctrl_ops dpu_ctrl_ops = {
++	.s_ctrl		= dpu_s_ctrl,
++};
++
++static int dpu_setup_ctrls(struct ingenic_dpu_ctx *ctx)
++{
++	struct ingenic_dpu_dev *dev = ctx->dpu_dev;
++
++	v4l2_ctrl_handler_init(&ctx->ctrl_handler, 3);
++
++	// TODO...
++	ctx->ctrl_hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &dpu_ctrl_ops,
++						V4L2_CID_HFLIP, 0, 1, 1, 0);
++
++	ctx->ctrl_vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &dpu_ctrl_ops,
++						V4L2_CID_VFLIP, 0, 1, 1, 0);
++	ctx->ctrl_rot = v4l2_ctrl_new_std(&ctx->ctrl_handler, &dpu_ctrl_ops,
++						V4L2_CID_ROTATE, 0, 270, 90, 0);
++
++	if (ctx->ctrl_handler.error) {
++		int err = ctx->ctrl_handler.error;
++		v4l2_err(&dev->v4l2_dev, "rot_setup_ctrls failed\n");
++		v4l2_ctrl_handler_free(&ctx->ctrl_handler);
++		return err;
++	}
++
++	return 0;
++}
++
++static int dpu_buf_prepare(struct vb2_buffer *vb)
++{
++	struct ingenic_dpu_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
++	struct dpu_frame_info *frame = get_frame(ctx, vb->vb2_queue->type);
++
++	if (IS_ERR(frame))
++		return PTR_ERR(frame);
++	vb2_set_plane_payload(vb, 0, frame->size);
++	return 0;
++}
++
++static void dpu_buf_queue(struct vb2_buffer *vb)
++{
++	struct ingenic_dpu_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
++	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
++
++	if (ctx->m2m_ctx)
++		v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
++}
++
++static struct vb2_ops dpu_qops = {
++	.queue_setup	= dpu_queue_setup,
++	.buf_prepare	= dpu_buf_prepare,
++	.buf_queue	= dpu_buf_queue,
++};
++
++static int queue_init(void *priv, struct vb2_queue *src_vq,
++						struct vb2_queue *dst_vq)
++{
++	struct ingenic_dpu_ctx *ctx = priv;
++	int ret;
++
++	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
++	src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
++	src_vq->drv_priv = ctx;
++	src_vq->ops = &dpu_qops;
++	src_vq->mem_ops = &ingenic_vb2_dma_contig_memops;
++	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
++	src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
++	src_vq->lock = &ctx->dpu_dev->dev_mutex;
++
++	ret = vb2_queue_init(src_vq);
++	if (ret)
++		return ret;
++
++	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++	dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
++	dst_vq->drv_priv = ctx;
++	dst_vq->ops = &dpu_qops;
++	dst_vq->mem_ops = &ingenic_vb2_dma_contig_memops;
++	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
++	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
++	dst_vq->lock = &ctx->dpu_dev->dev_mutex;
++
++	return vb2_queue_init(dst_vq);
++}
++
++static void set_default_fmt(struct ingenic_dpu_ctx *ctx)
++{
++	struct dpu_frame_info *cap, *out;
++
++	cap = &ctx->cap_info;
++	out = &ctx->out_info;
++
++	cap->width = DEFAULT_WIDTH;
++	cap->height = DEFAULT_HEIGHT;
++	cap->fmt = &formats[0];
++	cap->bytesperline = DEFAULT_WIDTH * cap->fmt->depth >> 3;
++	cap->size = cap->bytesperline * cap->height;
++
++	out->width = DEFAULT_WIDTH;
++	out->height = DEFAULT_HEIGHT;
++	out->fmt = &formats[0];
++	out->bytesperline = DEFAULT_WIDTH * out->fmt->depth >> 3;
++	out->size = out->bytesperline * out->height;
++}
++
++
++static int dpu_open(struct file *file)
++{
++	struct ingenic_dpu_dev *dev = video_drvdata(file);
++	struct ingenic_dpu_ctx *ctx = NULL;
++	int ret = 0;
++
++	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
++	if (!ctx)
++		return -ENOMEM;
++
++	if (mutex_lock_interruptible(&dev->dev_mutex)) {
++		kfree(ctx);
++		return -ERESTARTSYS;
++	}
++
++	ctx->hw_comp = hw_composer_create(ctx);
++	if(!ctx->hw_comp) {
++		goto err_hw_comp;
++	}
++
++	ctx->dpu_dev = dev;
++
++	/* Set default formats */
++	set_default_fmt(ctx);
++
++	v4l2_fh_init(&ctx->fh, video_devdata(file));
++	ctx->fh.ctrl_handler = &ctx->ctrl_handler;
++	file->private_data = &ctx->fh;
++	v4l2_fh_add(&ctx->fh);
++
++
++	ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
++	if (IS_ERR(ctx->m2m_ctx)) {
++		ret = PTR_ERR(ctx->m2m_ctx);
++		goto err;
++	}
++	ctx->fh.m2m_ctx = ctx->m2m_ctx;
++
++
++	ret = dpu_setup_ctrls(ctx);
++	if(ret)
++		goto err;
++
++	/* Write the default values to the ctx struct */
++	v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
++
++	mutex_unlock(&dev->dev_mutex);
++
++	return 0;
++err:
++	v4l2_fh_del(&ctx->fh);
++	v4l2_fh_exit(&ctx->fh);
++err_hw_comp:
++	mutex_unlock(&dev->dev_mutex);
++	kfree(ctx);
++	return ret;
++}
++
++static int dpu_release(struct file *file)
++{
++	struct ingenic_dpu_dev *dev = video_drvdata(file);
++	struct ingenic_dpu_ctx *ctx = fh_to_ctx(file->private_data);
++
++	mutex_lock(&dev->dev_mutex);
++
++	hw_composer_destroy(ctx->hw_comp);
++	v4l2_m2m_ctx_release(ctx->m2m_ctx);
++	mutex_unlock(&dev->dev_mutex);
++
++	v4l2_ctrl_handler_free(&ctx->ctrl_handler);
++	v4l2_fh_del(&ctx->fh);
++	v4l2_fh_exit(&ctx->fh);
++	kfree(ctx);
++	return 0;
++}
++
++/*
++ �始化comp_info，
++该驱动主�使用layer0进行CSC和缩放�作.
++将frame_cfg 和 layer_cfg 都�始化，
++在实际执行�加时，�更新涉�部分.
++*/
++static int hw_comp_v4l2_init_info(struct ingenic_dpu_ctx *ctx)
++{
++	struct comp_setup_info *comp_info = &ctx->comp_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &comp_info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = frm_cfg->lay_cfg;
++	int i = 0;
++
++	memset(comp_info, 0, sizeof(struct comp_setup_info));
++
++	for(i = 0; i < DPU_SUPPORT_MAX_LAYERS; i++) {
++		lay_cfg[i].lay_z_order  = i; /* top */
++	}
++
++	return 0;
++}
++
++static int hw_comp_v4l2_update_info(struct ingenic_dpu_ctx *ctx, struct vb2_v4l2_buffer *src, struct vb2_v4l2_buffer *dst)
++{
++	struct comp_setup_info *comp_info = &ctx->comp_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &comp_info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = frm_cfg->lay_cfg;
++	struct wback_cfg *wback_info = &frm_cfg->wback_info;
++
++	struct dpu_frame_info *out_info = &ctx->out_info;
++	struct dpu_frame_info *cap_info = &ctx->cap_info;
++
++	// TODO, handle with userptr address.
++	unsigned long src_paddr = ingenic_vb2_dma_contig_plane_dma_addr(&src->vb2_buf,0);
++	unsigned long dst_paddr = ingenic_vb2_dma_contig_plane_dma_addr(&dst->vb2_buf,0);
++
++	unsigned int src_w = out_info->width;
++	unsigned int src_h = out_info->height;
++	unsigned int src_fmt = out_info->fmt->layer_fmt;
++	unsigned int dst_w = cap_info->width;
++	unsigned int dst_h = cap_info->height;
++	unsigned int dst_fmt = cap_info->fmt->wb_fmt;
++
++	lay_cfg[0].lay_en = 1;
++	lay_cfg[0].source_w = src_w;
++	lay_cfg[0].source_h = src_h;
++	lay_cfg[0].disp_pos_x = 0;
++	lay_cfg[0].disp_pos_y = 0;
++
++	if(src_w != dst_w || src_h != dst_h) {
++		lay_cfg[0].scale_w = dst_w;
++		lay_cfg[0].scale_h = dst_h;
++		lay_cfg[0].lay_scale_en = 1;
++	}
++
++	lay_cfg[0].g_alpha_en = 0;
++	lay_cfg[0].g_alpha_val = 128;
++	lay_cfg[0].stride = src_w;
++	lay_cfg[0].uv_stride = src_w;
++
++	lay_cfg[0].color = LAYER_CFG_COLOR_RGB; //TODO: export ctrls to user?
++	lay_cfg[0].format = src_fmt;
++
++	lay_cfg[0].addr[0] = src_paddr;
++	lay_cfg[0].uv_addr[0] = src_paddr + src_w * src_h;
++	lay_cfg[0].tlb_en = 0; // TODO. for USERPTR Mode
++
++
++	//frm_cfg
++	frm_cfg->width = dst_w;
++	frm_cfg->height = dst_h;
++
++	//wback_cfg
++	wback_info->en = 1;
++	wback_info->fmt = dst_fmt; //TODO.
++	wback_info->addr = dst_paddr; //TODO
++	wback_info->stride = dst_w; // TODO
++	wback_info->dither_en = 0;
++
++	//printk("src_paddr: %x, src_w: %d, src_h: %d\n", src_paddr, src_w, src_h);
++	//printk("dst_paddr: %x, dst_w: %d, dst_h: %d\n", dst_paddr, dst_w, dst_h);
++
++	return 0;
++}
++
++static void device_run(void *prv)
++{
++	struct ingenic_dpu_ctx *ctx = prv;
++	struct ingenic_dpu_dev *dev = ctx->dpu_dev;
++	struct vb2_v4l2_buffer *src, *dst;
++
++	src = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
++	if(unlikely(src == NULL)) {
++		printk("DPU:src == NULL\n");
++	}
++	dst = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
++	if(unlikely(dst == NULL)) {
++		printk("DPU:dst == NULL\n");
++	}
++	hw_composer_lock(ctx->hw_comp);
++
++	hw_comp_v4l2_init_info(ctx);
++	hw_comp_v4l2_update_info(ctx, src, dst);
++	hw_composer_setup(ctx->hw_comp, &ctx->comp_info);
++
++	hw_composer_start(ctx->hw_comp); //block compose.
++	hw_composer_unlock(ctx->hw_comp);
++
++
++	v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE);
++	v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
++
++	v4l2_m2m_job_finish(dev->m2m_dev, ctx->m2m_ctx);
++}
++
++
++
++static void job_abort(void *prv)
++{
++	printk("----abort\n");
++}
++
++static const struct v4l2_file_operations dpu_fops = {
++	.owner		= THIS_MODULE,
++	.open		= dpu_open,
++	.release	= dpu_release,
++	.poll		= v4l2_m2m_fop_poll,
++	.unlocked_ioctl	= video_ioctl2,
++	.mmap		= v4l2_m2m_fop_mmap,
++};
++
++static const struct v4l2_ioctl_ops dpu_ioctl_ops = {
++	.vidioc_querycap		= vidioc_querycap,
++
++	.vidioc_enum_fmt_vid_cap	= vidioc_enum_fmt_vid_cap,
++	.vidioc_g_fmt_vid_cap		= vidioc_g_fmt,
++	.vidioc_try_fmt_vid_cap		= vidioc_try_fmt,
++	.vidioc_s_fmt_vid_cap		= vidioc_s_fmt,
++
++	.vidioc_enum_fmt_vid_out	= vidioc_enum_fmt_vid_out,
++	.vidioc_g_fmt_vid_out		= vidioc_g_fmt,
++	.vidioc_try_fmt_vid_out		= vidioc_try_fmt,
++	.vidioc_s_fmt_vid_out		= vidioc_s_fmt,
++
++	.vidioc_reqbufs			= v4l2_m2m_ioctl_reqbufs,
++	.vidioc_querybuf		= v4l2_m2m_ioctl_querybuf,
++	.vidioc_qbuf			= v4l2_m2m_ioctl_qbuf,
++	.vidioc_dqbuf			= v4l2_m2m_ioctl_dqbuf,
++
++	.vidioc_streamon		= vidioc_streamon,
++	.vidioc_streamoff		= vidioc_streamoff,
++};
++
++
++static struct video_device dpu_videodev = {
++	.name		= "dpu-hwcomp",
++	.fops		= &dpu_fops,
++	.ioctl_ops	= &dpu_ioctl_ops,
++	.minor		= -1,
++	.release	= video_device_release,
++	.vfl_dir	= VFL_DIR_M2M,
++	.device_caps	= V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M,
++};
++
++static struct v4l2_m2m_ops dpu_m2m_ops = {
++	.device_run	= device_run,
++	.job_abort	= job_abort,
++};
++
++
++void * hw_comp_v4l2_init(struct device *dev)
++{
++	struct ingenic_dpu_dev *dpu_dev;
++	struct video_device *vfd;
++	int ret = 0;
++
++	dpu_dev = devm_kzalloc(dev, sizeof(*dpu_dev), GFP_KERNEL);
++	if (!dpu_dev)
++		return NULL;
++
++	dpu_dev->dev = dev;
++	dpu_dev->name = dpu_videodev.name;
++
++	mutex_init(&dpu_dev->dev_mutex);
++
++	dpu_dev->alloc_ctx = ingenic_vb2_dma_contig_init_ctx(dpu_dev->dev);
++	if (IS_ERR(dpu_dev->alloc_ctx)) {
++		ret = PTR_ERR(dpu_dev->alloc_ctx);
++	}
++
++	ret = v4l2_device_register(dpu_dev->dev, &dpu_dev->v4l2_dev);
++	if (ret)
++		goto alloc_ctx_cleanup;
++
++
++	vfd = &dpu_videodev;
++	vfd->lock = &dpu_dev->dev_mutex;
++	vfd->v4l2_dev = &dpu_dev->v4l2_dev;
++
++	ret = video_register_device(vfd, VFL_TYPE_VIDEO, INGENIC_DPU_COMP_VIDEO_NR);
++	if (ret) {
++		v4l2_err(&dpu_dev->v4l2_dev, "Failed to register video device\n");
++		goto free_video_device;
++	}
++
++	video_set_drvdata(vfd, dpu_dev);
++	snprintf(vfd->name, sizeof(vfd->name), "%s", dpu_videodev.name);
++	dpu_dev->vfd = vfd;
++	v4l2_info(&dpu_dev->v4l2_dev, "device registered as /dev/video%d\n",vfd->num);
++
++	dpu_dev->m2m_dev = v4l2_m2m_init(&dpu_m2m_ops);
++
++	if (IS_ERR(dpu_dev->m2m_dev)) {
++		v4l2_err(&dpu_dev->v4l2_dev, "Failed to init mem2mem device\n");
++		ret = PTR_ERR(dpu_dev->m2m_dev);
++		goto unreg_video_dev;
++	}
++
++	return dpu_dev;
++
++unreg_video_dev:
++	video_unregister_device(vfd);
++free_video_device:
++	v4l2_device_unregister(&dpu_dev->v4l2_dev);
++alloc_ctx_cleanup:
++	ingenic_vb2_dma_contig_cleanup_ctx(dpu_dev->alloc_ctx);
++	return NULL;
++}
++
++int hw_comp_v4l2_exit(void *priv)
++{
++	struct ingenic_dpu_dev *dev = (struct ingenic_dpu_dev *)priv;
++
++	v4l2_m2m_release(dev->m2m_dev);
++	video_unregister_device(dev->vfd);
++	video_device_release(dev->vfd);
++	v4l2_device_unregister(&dev->v4l2_dev);
++	ingenic_vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
++
++	return 0;
++}
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer_v4l2.h b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer_v4l2.h
+new file mode 100644
+index 000000000..e5621125d
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/hw_composer_v4l2.h
+@@ -0,0 +1,72 @@
++#ifndef __I2D_VIDEO_H__
++#define __I2D_VIDEO_H__
++
++#include <linux/platform_device.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++
++#define MAX_WIDTH	3840
++#define MAX_HEIGHT	2160
++#define MIN_WIDTH	0
++#define	MIN_HEIGHT	0
++
++#define DEFAULT_WIDTH 640
++#define DEFAULT_HEIGHT 480
++
++
++#define MEM2MEM_CAPTURE	(1 << 0)
++#define MEM2MEM_OUTPUT	(1 << 1)
++
++struct dpu_fmt {
++	char	*name;
++	u32	fourcc;
++	int	depth;
++	u32	types;
++	u32	layer_fmt;
++	u32	wb_fmt;
++};
++
++struct dpu_frame_info{
++	uint16_t width;
++	uint16_t height;
++	struct dpu_fmt *fmt;
++	uint32_t	size;
++	uint32_t	bytesperline;
++};
++
++struct ingenic_dpu_dev {
++	char* name;
++	struct device *dev;
++	struct v4l2_device	v4l2_dev;
++	struct v4l2_m2m_dev	*m2m_dev;
++	struct video_device	*vfd;
++	atomic_t			num_inst;
++	struct mutex		dev_mutex;
++	struct vb2_alloc_ctx	*alloc_ctx;
++};
++
++struct ingenic_dpu_ctx {
++	struct v4l2_fh		fh;
++	struct ingenic_dpu_dev	*dpu_dev;
++	struct v4l2_m2m_ctx	*m2m_ctx;
++	struct v4l2_ctrl_handler ctrl_handler;
++	struct v4l2_ctrl	*ctrl_hflip;
++	struct v4l2_ctrl	*ctrl_vflip;
++	struct v4l2_ctrl	*ctrl_rot;
++	struct dpu_frame_info	cap_info;
++	struct dpu_frame_info	out_info;
++	uint32_t			vflip;
++	uint32_t			hflip;
++	uint32_t			angle;
++
++	struct hw_composer_ctx *hw_comp;
++	struct comp_setup_info	comp_info;
++};
++
++
++void *hw_comp_v4l2_init(struct device *dev);
++int hw_comp_v4l2_exit(void *priv);
++
++#endif		// __I2D_VIDEO_H__
++
++
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/ingenicfb.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/ingenicfb.c
+new file mode 100644
+index 000000000..d941a0cb7
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/ingenicfb.c
+@@ -0,0 +1,1487 @@
++/*
++ * drivers/video/fbdev/ingenic/x2000_v12/ingenicfb.c
++ *
++ * Copyright (c) 2020 Ingenic Semiconductor Co., Ltd.
++ *              http://www.ingenic.com/
++ *
++ * Core file for Ingenic Display Controller driver
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++#include <linux/poll.h>
++#include <linux/wait.h>
++#include <linux/fs.h>
++#include <linux/irq.h>
++#include <linux/mm.h>
++#include <linux/fb.h>
++#include <linux/delay.h>
++#include <linux/ctype.h>
++#include <linux/dma-mapping.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/of_reserved_mem.h>
++#include <linux/memory.h>
++#include <linux/suspend.h>
++#include <linux/string.h>
++#include <linux/kthread.h>
++#include <linux/gpio.h>
++#include <asm/cacheflush.h>
++#include <linux/of_address.h>
++#include "dpu_reg.h"
++#include "ingenicfb.h"
++#include "hw_composer_fb.h"
++#include "hw_composer_v4l2.h"
++#include <libdmmu.h>
++
++#define dpu_debug 1
++#define print_dbg(f, arg...) if(dpu_debug) printk(KERN_INFO "dpu: %s, %d: " f "\n", __func__, __LINE__, ## arg)
++
++#define COMPOSER_DIRECT_OUT_EN
++
++#include "./jz_mipi_dsi/jz_mipi_dsih_hal.h"
++#include "./jz_mipi_dsi/jz_mipi_dsi_regs.h"
++#include "./jz_mipi_dsi/jz_mipi_dsi_lowlevel.h"
++extern struct dsi_device * jzdsi_init(struct jzdsi_data *pdata);
++extern void jzdsi_remove(struct dsi_device *dsi);
++extern void dump_dsi_reg(struct dsi_device *dsi);
++int jz_mipi_dsi_set_client(struct dsi_device *dsi, int power);
++static const struct of_device_id ingenicfb_of_match[];
++#ifdef CONFIG_TRUE_COLOR_LOGO
++#include <video/ingenic_logo.h>
++extern unsigned char logo_buf_initdata[] __initdata; /* obj/drivers/video/logo-ingenic/logo.c */
++extern void show_logo(struct fb_info *info);
++static unsigned char * copyed_logo_buf = NULL;
++#endif
++
++struct lcd_panel *fbdev_panel = NULL;
++struct platform_device *fbdev_pdev = NULL;
++static unsigned int cmp_gen_sop = 0;
++static int uboot_inited;
++static int showFPS = 0;
++static int over_cnt = 0;
++static bool panel_mipi_init_ok = false;
++static struct ingenicfb_device *fbdev;
++
++#ifdef CONFIG_FB_VSYNC_SKIP_DISABLE
++static unsigned int old_desc_addr = 0;
++#endif
++
++/* #define TEST_IRQ */
++
++const struct fb_fix_screeninfo ingenicfb_fix  = {
++	.id = "ingenicfb",
++	.type = FB_TYPE_PACKED_PIXELS,
++	.visual = FB_VISUAL_TRUECOLOR,
++	.xpanstep = 0,
++	.ypanstep = 1,
++	.ywrapstep = 0,
++	.accel = FB_ACCEL_NONE,
++};
++
++struct ingenicfb_colormode {
++	uint32_t mode;
++	const char *name;
++	uint32_t color;
++	uint32_t bits_per_pixel;
++	uint32_t nonstd;
++	struct fb_bitfield red;
++	struct fb_bitfield green;
++	struct fb_bitfield blue;
++	struct fb_bitfield transp;
++};
++
++struct ingenic_priv {
++	unsigned int dsi_iobase;
++	unsigned int dsi_phy_iobase;
++	bool support_comp;
++};
++
++/* 这个实际是comp支�的, 应该放在compfb中。这里应该�记录rdma支�的格�.*/
++static struct ingenicfb_colormode ingenicfb_colormodes[] = {
++	{
++		.mode = RDMA_CHAIN_CFG_FORMAT_888,
++		.name = "rgb888",
++		.color = RDMA_CHAIN_CFG_COLOR_RGB,
++		.bits_per_pixel = 32,
++		.nonstd = 0,
++		.color = RDMA_CHAIN_CFG_COLOR_RGB,
++		.red	= { .length = 8, .offset = 16, .msb_right = 0 },
++		.green	= { .length = 8, .offset = 8, .msb_right = 0 },
++		.blue	= { .length = 8, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 0, .offset = 0, .msb_right = 0 },
++	}, {
++		.mode = RDMA_CHAIN_CFG_FORMAT_555,
++		.name = "rgb555",
++		.color = RDMA_CHAIN_CFG_COLOR_RGB,
++		.bits_per_pixel = 16,
++		.nonstd = 0,
++		.red	= { .length = 5, .offset = 10, .msb_right = 0 },
++		.green	= { .length = 5, .offset = 5, .msb_right = 0 },
++		.blue	= { .length = 5, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 0, .offset = 0, .msb_right = 0 },
++	}, {
++		.mode = RDMA_CHAIN_CFG_FORMAT_ARGB1555,
++		.name = "argb1555",
++		.color = RDMA_CHAIN_CFG_COLOR_RGB,
++		.bits_per_pixel = 16,
++		.nonstd = 0,
++		.red	= { .length = 5, .offset = 10, .msb_right = 0 },
++		.green	= { .length = 5, .offset = 5, .msb_right = 0 },
++		.blue	= { .length = 5, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 1, .offset = 15, .msb_right = 0 },
++	}, {
++		.mode = RDMA_CHAIN_CFG_FORMAT_565,
++		.name = "rgb565",
++		.color = RDMA_CHAIN_CFG_COLOR_RGB,
++		.bits_per_pixel = 16,
++		.nonstd = 0,
++		.red	= { .length = 5, .offset = 11, .msb_right = 0 },
++		.green	= { .length = 6, .offset = 5, .msb_right = 0 },
++		.blue	= { .length = 5, .offset = 0, .msb_right = 0 },
++		.transp	= { .length = 0, .offset = 0, .msb_right = 0 },
++	},
++};
++
++static int ingenicfb_dmmu_mm_release(void *data)
++{
++	struct ingenicfb_device *fbdev = (struct ingenicfb_device *)data;
++
++	hw_composer_lock(fbdev->comp_ctx);
++	hw_composer_stop(fbdev->comp_ctx);
++	hw_composer_unlock(fbdev->comp_ctx);
++
++	return 0;
++}
++
++
++static struct dmmu_mm_ops ingenicfb_dmmu_mm_ops = {
++	.mm_release = ingenicfb_dmmu_mm_release,
++};
++
++	static void
++ingenicfb_videomode_to_var(struct fb_var_screeninfo *var,
++		const struct fb_videomode *mode)
++{
++	var->xres = mode->xres;
++	var->yres = mode->yres;
++	var->xres_virtual = mode->xres;
++	var->yres_virtual = mode->yres * CONFIG_FB_INGENIC_NR_FRAMES;
++	var->xoffset = 0;
++	var->yoffset = 0;
++	var->left_margin = mode->left_margin;
++	var->right_margin = mode->right_margin;
++	var->upper_margin = mode->upper_margin;
++	var->lower_margin = mode->lower_margin;
++	var->hsync_len = mode->hsync_len;
++	var->vsync_len = mode->vsync_len;
++	var->sync = mode->sync;
++	var->vmode = mode->vmode & FB_VMODE_MASK;
++	var->pixclock = mode->pixclock;
++}
++
++static struct fb_videomode *ingenicfb_get_mode(struct fb_var_screeninfo *var,
++		struct fb_info *info)
++{
++	size_t i;
++	struct ingenicfb_device *fbdev = info->par;
++	struct fb_videomode *mode = fbdev->panel->modes;
++
++	for (i = 0; i < fbdev->panel->num_modes; ++i, ++mode) {
++		if (mode->xres == var->xres && mode->yres == var->yres
++				&& mode->vmode == var->vmode
++				&& mode->right_margin == var->right_margin) {
++			if (fbdev->panel->lcd_type != LCD_TYPE_SLCD) {
++				if (mode->pixclock == var->pixclock)
++					return mode;
++			} else {
++				return mode;
++			}
++		}
++	}
++
++	return NULL;
++}
++
++static void ingenicfb_colormode_to_var(struct fb_var_screeninfo *var,
++		struct ingenicfb_colormode *color)
++{
++	var->bits_per_pixel = color->bits_per_pixel;
++	var->nonstd = color->nonstd;
++	var->red = color->red;
++	var->green = color->green;
++	var->blue = color->blue;
++	var->transp = color->transp;
++}
++
++static bool cmp_component(struct fb_bitfield *f1, struct fb_bitfield *f2)
++{
++	return f1->length == f2->length &&
++		f1->offset == f2->offset &&
++		f1->msb_right == f2->msb_right;
++}
++static bool cmp_var_to_colormode(struct fb_var_screeninfo *var,
++		struct ingenicfb_colormode *color)
++{
++
++	if (var->bits_per_pixel == 0 ||
++			var->red.length == 0 ||
++			var->blue.length == 0 ||
++			var->green.length == 0)
++		return 0;
++
++	return var->bits_per_pixel == color->bits_per_pixel &&
++		cmp_component(&var->red, &color->red) &&
++		cmp_component(&var->green, &color->green) &&
++		cmp_component(&var->blue, &color->blue) &&
++		cmp_component(&var->transp, &color->transp);
++}
++
++static struct ingenicfb_colormode *ingenicfb_check_colormode(struct fb_var_screeninfo *var)
++{
++	int i;
++
++	if (var->nonstd) {
++		for (i = 0; i < ARRAY_SIZE(ingenicfb_colormodes); ++i) {
++			struct ingenicfb_colormode *m = &ingenicfb_colormodes[i];
++			if (var->nonstd == m->nonstd) {
++				ingenicfb_colormode_to_var(var, m);
++				return m;
++			}
++		}
++
++		return NULL;
++	}
++
++	for (i = 0; i < ARRAY_SIZE(ingenicfb_colormodes); ++i) {
++		struct ingenicfb_colormode *m = &ingenicfb_colormodes[i];
++		if (cmp_var_to_colormode(var, m)) {
++			ingenicfb_colormode_to_var(var, m);
++			return m;
++		}
++	}
++	/* To support user libraries that only support RGB format */
++	for (i = 0; i < ARRAY_SIZE(ingenicfb_colormodes); ++i) {
++		struct ingenicfb_colormode *m = &ingenicfb_colormodes[i];
++		if (var->bits_per_pixel == m->bits_per_pixel) {
++			ingenicfb_colormode_to_var(var, m);
++			return m;
++		}
++	}
++
++	return NULL;
++}
++
++static int ingenicfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++	struct ingenicfb_device *fbdev = info->par;
++	struct fb_videomode *mode;
++	struct ingenicfb_colormode *color_mode;
++	int ret;
++
++	mode = ingenicfb_get_mode(var, info);
++	if (mode == NULL) {
++		dev_err(info->dev, "%s get video mode failed\n", __func__);
++		return -EINVAL;
++	}
++
++	ingenicfb_videomode_to_var(var, mode);
++
++	/*TODO:�应该修改var.*/
++	color_mode = ingenicfb_check_colormode(var);
++	if(color_mode == NULL) {
++		dev_err(info->dev,"Check colormode failed!\n");
++		return  -EINVAL;
++	}
++
++	fbdev->color_mode = color_mode;
++
++	return 0;
++}
++
++#define DPU_WAIT_IRQ_TIME 8000
++static int ingenicfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
++{
++	void __user *argp = (void __user *)arg;
++	struct comp_setup_info comp_info;
++	struct ingenicfb_device *fbdev = info->par;
++	int ret;
++	csc_mode_t csc_mode;
++	int value;
++	int tmp;
++	int i;
++
++	switch (cmd) {
++		case JZFB_SET_VSYNCINT:
++			if (unlikely(copy_from_user(&value, argp, sizeof(int))))
++				return -EFAULT;
++			break;
++		case FBIO_WAITFORVSYNC:
++			if(fbdev->dctrl.chan == DATA_CH_COMP)
++				break;
++#ifndef CONFIG_FB_VSYNC_SKIP_DISABLE
++			unlock_fb_info(info);
++			ret = wait_event_interruptible_timeout(fbdev->vsync_wq,
++					fbdev->timestamp.wp != fbdev->timestamp.rp,
++					msecs_to_jiffies(DPU_WAIT_IRQ_TIME));
++			lock_fb_info(info);
++			if(ret == 0) {
++				dev_err(info->dev, "DPU wait vsync timeout!\n");
++				return -EFAULT;
++			}
++
++			ret = copy_to_user(argp, fbdev->timestamp.value + fbdev->timestamp.rp,
++					sizeof(u64));
++			fbdev->timestamp.rp = (fbdev->timestamp.rp + 1) % TIMESTAMP_CAP;
++
++			if (unlikely(ret))
++				return -EFAULT;
++#else
++			{
++				unlock_fb_info(info);
++				fbdev->timestamp.rp = fbdev->timestamp.wp;
++				ret = wait_event_interruptible_timeout(fbdev->vsync_wq,
++						fbdev->timestamp.wp != fbdev->timestamp.rp,
++						msecs_to_jiffies(DPU_WAIT_IRQ_TIME));
++				lock_fb_info(info);
++				if(ret == 0) {
++					dev_err(info->dev, "DPU wait vsync timeout!\n");
++					return -EFAULT;
++				}
++			}
++#endif
++			break;
++		case JZFB_PUT_FRM_CFG:
++			copy_from_user(&comp_info.frm_cfg, (void *)argp, sizeof(struct ingenicfb_frm_cfg));
++
++
++			comp_info.nframes = 1;
++			//comp_info.out_mode = COMP_WRITE_BACK;
++
++			/*设置composer帧信�，并且�动一次comp设备进行��.*/
++			hw_composer_lock(fbdev->comp_ctx);
++
++			hw_composer_setup(fbdev->comp_ctx, &comp_info);
++
++			hw_composer_start(fbdev->comp_ctx);
++			hw_composer_unlock(fbdev->comp_ctx);
++
++			break;
++		case JZFB_GET_FRM_CFG:
++			copy_to_user((void *)argp,
++				      &fbdev->comp_ctx->comp_info.frm_cfg,
++				      sizeof(struct ingenicfb_frm_cfg));
++			break;
++		case JZFB_GET_LAYERS_NUM:
++			{
++				unsigned int layers_num = CONFIG_FB_INGENIC_NR_LAYERS;
++				copy_to_user((void *)argp,
++					      &layers_num,
++					      sizeof(unsigned int));
++			}
++			break;
++		case JZFB_SET_CSC_MODE:
++			if (unlikely(copy_from_user(&csc_mode, argp, sizeof(csc_mode_t))))
++				return -EFAULT;
++
++			//TODO:
++			//csc_mode_set(fbdev, csc_mode);
++			break;
++		case JZFB_USE_TLB:
++			if((unsigned int)arg != 0){
++				fbdev->dctrl.tlba = (unsigned int)arg;
++
++				dmmu_register_mm_notifier(&fbdev->dmn);
++			} else
++				printk("tlb err!!!\n");
++			break;
++		case JZFB_DMMU_MEM_SMASH:
++			{
++				struct smash_mode sm;
++				if (copy_from_user(&sm, (void *)arg, sizeof(sm))) {
++					ret = -EFAULT;
++					break;
++				}
++				return dmmu_memory_smash(sm.vaddr, sm.mode);
++				break;
++			}
++		case JZFB_DMMU_DUMP_MAP:
++			{
++				unsigned long vaddr;
++				if (copy_from_user(&vaddr, (void *)arg, sizeof(unsigned long))) {
++					ret = -EFAULT;
++					break;
++				}
++				return dmmu_dump_map(vaddr);
++				break;
++			}
++		case JZFB_DMMU_MAP:
++			{
++				struct dpu_dmmu_map_info di;
++				if (copy_from_user(&di, (void *)arg, sizeof(di))) {
++					ret = -EFAULT;
++					break;
++				}
++				fbdev->user_addr = di.addr;
++				return dmmu_map(info->dev,di.addr,di.len);
++				break;
++			}
++		case JZFB_DMMU_UNMAP:
++			{
++				struct dpu_dmmu_map_info di;
++				if (copy_from_user(&di, (void *)arg, sizeof(di))) {
++					ret = -EFAULT;
++					break;
++				}
++				return dmmu_unmap(info->dev,di.addr,di.len);
++				break;
++			}
++		case JZFB_DMMU_UNMAP_ALL:
++			dmmu_unmap_all(info->dev);
++			break;
++		case JZFB_DMMU_FLUSH_CACHE:
++			{
++				struct dpu_dmmu_map_info di;
++				if (copy_from_user(&di, (void *)arg, sizeof(di))) {
++					ret = -EFAULT;
++					break;
++				}
++				return dmmu_flush_cache(di.addr,di.len);
++				break;
++			}
++		default:
++			printk("Command:%x Error!\n",cmd);
++			break;
++	}
++	return 0;
++}
++
++int ingenicfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
++{
++	unsigned long start;
++	unsigned long off;
++	u32 len;
++
++	off = vma->vm_pgoff << PAGE_SHIFT;
++
++	start = info->fix.smem_start;
++	len = PAGE_ALIGN((start & ~PAGE_MASK) + info->fix.smem_len);
++	start &= PAGE_MASK;
++
++	if ((vma->vm_end - vma->vm_start + off) > len)
++		return -EINVAL;
++	off += start;
++
++	vma->vm_pgoff = off >> PAGE_SHIFT;
++	vma->vm_flags |= VM_IO;
++
++	pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
++	/* Write-Acceleration */
++	pgprot_val(vma->vm_page_prot) |= _CACHE_CACHABLE_WA;
++
++	if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
++				vma->vm_end - vma->vm_start, vma->vm_page_prot))
++	{
++		return -EAGAIN;
++	}
++
++	return 0;
++}
++
++static void ingenicfb_set_vsync_value(void *data)
++{
++	struct ingenicfb_device *fbdev = (struct ingenicfb_device *)data;
++
++	fbdev->vsync_skip_map = (fbdev->vsync_skip_map >> 1 |
++				fbdev->vsync_skip_map << 9) & 0x3ff;
++	if(likely(fbdev->vsync_skip_map & 0x1)) {
++		fbdev->timestamp.value[fbdev->timestamp.wp] =
++			ktime_to_ns(ktime_get());
++		fbdev->timestamp.wp = (fbdev->timestamp.wp + 1) % TIMESTAMP_CAP;
++		wake_up_interruptible(&fbdev->vsync_wq);
++#ifdef CONFIG_FB_VSYNC_SKIP_DISABLE
++	} else {
++		fbdev->timestamp.wp = fbdev->timestamp.rp + 1;
++		wake_up_interruptible(&fbdev->vsync_wq);
++#endif
++	}
++}
++
++static inline uint32_t convert_color_to_hw(unsigned val, struct fb_bitfield *bf)
++{
++	return (((val << bf->length) + 0x7FFF - val) >> 16) << bf->offset;
++}
++
++static int ingenicfb_setcolreg(unsigned regno, unsigned red, unsigned green,
++		unsigned blue, unsigned transp, struct fb_info *fb)
++{
++	if (regno >= 16)
++		return -EINVAL;
++
++	((uint32_t *)(fb->pseudo_palette))[regno] =
++		convert_color_to_hw(red, &fb->var.red) |
++		convert_color_to_hw(green, &fb->var.green) |
++		convert_color_to_hw(blue, &fb->var.blue) |
++		convert_color_to_hw(transp, &fb->var.transp);
++
++	return 0;
++}
++
++static int calc_refresh_ratio(struct lcd_panel *panel)
++{
++	struct smart_config *smart_config = panel->smart_config;
++
++	switch(smart_config->smart_type){
++	case SMART_LCD_TYPE_8080:
++	case SMART_LCD_TYPE_6800:
++		break;
++	case SMART_LCD_TYPE_SPI_3:
++		return 9;
++	case SMART_LCD_TYPE_SPI_4:
++		return 8;
++	default:
++		printk("%s %d err!\n",__func__,__LINE__);
++		break;
++	}
++
++	switch(smart_config->pix_fmt) {
++	case SMART_LCD_FORMAT_888:
++		if(smart_config->dwidth == SMART_LCD_DWIDTH_8_BIT)
++			return 3;
++		if(smart_config->dwidth == SMART_LCD_DWIDTH_24_BIT)
++			return 1;
++	case SMART_LCD_FORMAT_565:
++		if(smart_config->dwidth == SMART_LCD_DWIDTH_8_BIT)
++			return 2;
++		if(smart_config->dwidth == SMART_LCD_DWIDTH_16_BIT)
++			return 1;
++	default:
++		printk("%s %d err!\n",__func__,__LINE__);
++		break;
++	}
++
++	return 1;
++
++}
++
++static int refresh_pixclock_auto_adapt(struct fb_info *info, struct fb_videomode *mode)
++{
++	struct ingenicfb_device *fbdev = info->par;
++	struct lcd_panel *panel = fbdev->panel;
++	struct fb_var_screeninfo *var = &info->var;
++	uint16_t hds, vds;
++	uint16_t hde, vde;
++	uint16_t ht, vt;
++	unsigned long rate;
++	unsigned int refresh_ratio = 1;
++
++	if (mode == NULL) {
++		dev_err(fbdev->dev, "%s get video mode failed\n", __func__);
++		return -EINVAL;
++	}
++
++	if (fbdev->panel->lcd_type == LCD_TYPE_SLCD) {
++		refresh_ratio = calc_refresh_ratio(panel);
++	}
++
++	hds = mode->hsync_len + mode->left_margin;
++	hde = hds + mode->xres;
++	ht = hde + mode->right_margin;
++
++	vds = mode->vsync_len + mode->upper_margin;
++	vde = vds + mode->yres;
++	vt = vde + mode->lower_margin;
++
++	if(mode->refresh){
++		rate = mode->refresh * vt * ht * refresh_ratio;
++
++		mode->pixclock = KHZ2PICOS(round_up(rate, 1000)/1000);
++		var->pixclock = mode->pixclock;
++	}else if(mode->pixclock){
++		rate = PICOS2KHZ(mode->pixclock) * 1000;
++		mode->refresh = rate / vt / ht / refresh_ratio;
++	}else{
++		dev_err(fbdev->dev,"%s error:lcd important config info is absenced\n",__func__);
++		return -EINVAL;
++	}
++
++	dev_info(fbdev->dev, "mode->refresh: %d, mode->pixclock: %d, rate: %ld, modex->pixclock: %d\n", mode->refresh, mode->pixclock, rate, mode->pixclock);
++
++	return 0;
++}
++
++
++static int ingenicfb_set_par(struct fb_info *info)
++{
++	struct ingenicfb_device *fbdev = info->par;
++	struct fb_var_screeninfo *var = &info->var;
++	struct dpu_ctrl *dctrl = &fbdev->dctrl;
++	struct fb_videomode *mode;
++	struct ingenicfb_colormode *color_mode;
++	unsigned long flags;
++	int ret;
++
++	/*根�var xres,yres信�，查找panel支�的mode*/
++	mode = ingenicfb_get_mode(var, info);
++	if (mode == NULL) {
++		dev_err(info->dev, "%s get video mode failed\n", __func__);
++		return -EINVAL;
++	}
++	info->mode = mode;
++
++	/*根�var信�, 查找到colormode.*/
++	color_mode = ingenicfb_check_colormode(var);
++	if(color_mode == NULL) {
++		dev_err(info->dev,"Check colormode failed!\n");
++		return  -EINVAL;
++	}
++
++	/*修改当�指�的color_mode? 那check_var需�修改�?*/
++	fbdev->color_mode = color_mode;
++
++	/*构建rdma信�，设置并�动.*/
++	struct rdma_setup_info *rdma_info = &fbdev->rdma_info;
++	rdma_info->nframes = CONFIG_FB_INGENIC_NR_FRAMES;	//TODO:
++	rdma_info->format = color_mode->mode;
++	rdma_info->color = color_mode->color;
++	rdma_info->stride = var->xres;
++	rdma_info->continuous = 1; //TODO:
++	rdma_info->vidmem = (unsigned char**)&fbdev->vidmem;
++	rdma_info->vidmem_phys = (unsigned int**)&fbdev->vidmem_phys;
++
++	dpu_ctrl_rdma_stop(dctrl, QCK_STOP);
++
++	dpu_ctrl_rdma_setup(dctrl, rdma_info);
++
++	dpu_ctrl_rdma_start(dctrl);
++
++	return 0;
++}
++
++static inline int timeval_sub_to_us(struct timespec64 lhs,
++						struct timespec64 rhs)
++{
++	int sec, nsec;
++	sec = lhs.tv_sec - rhs.tv_sec;
++	nsec = lhs.tv_nsec - rhs.tv_nsec;
++
++	return (sec*1000000 + nsec/1000);
++}
++
++static inline int time_us2ms(int us)
++{
++	return (us/1000);
++}
++
++static void calculate_frame_rate(void)
++{
++	static struct timespec64 time_now, time_last;
++	unsigned int interval_in_us;
++	unsigned int interval_in_ms;
++	static unsigned int fpsCount = 0;
++
++	switch(showFPS){
++	case 1:
++		fpsCount++;
++		ktime_get_real_ts64(&time_now);
++		interval_in_us = timeval_sub_to_us(time_now, time_last);
++		if ( interval_in_us > (USEC_PER_SEC) ) { /* 1 second = 1000000 us. */
++			printk(" Pan display FPS: %d\n",fpsCount);
++			fpsCount = 0;
++			time_last = time_now;
++		}
++		break;
++	case 2:
++		ktime_get_real_ts64(&time_now);
++		interval_in_us = timeval_sub_to_us(time_now, time_last);
++		interval_in_ms = time_us2ms(interval_in_us);
++		printk(" Pan display interval ms: %d\n",interval_in_ms);
++		time_last = time_now;
++		break;
++	default:
++		if (showFPS > 3) {
++			int d, f;
++			fpsCount++;
++			ktime_get_real_ts64(&time_now);
++			interval_in_us = timeval_sub_to_us(time_now, time_last);
++			if (interval_in_us > USEC_PER_SEC * showFPS ) { /* 1 second = 1000000 us. */
++				d = fpsCount / showFPS;
++				f = (fpsCount * 10) / showFPS - d * 10;
++				printk(" Pan display FPS: %d.%01d\n", d, f);
++				fpsCount = 0;
++				time_last = time_now;
++			}
++		}
++		break;
++	}
++}
++
++static int ingenicfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++	struct ingenicfb_device *fbdev = info->par;
++	struct dpu_ctrl *dctrl = &fbdev->dctrl;
++	int next_frm;
++	int ret = 0;
++
++	if (var->xoffset - info->var.xoffset) {
++		dev_err(info->dev, "No support for X panning for now\n");
++		return -EINVAL;
++	}
++
++	fbdev->pan_display_count++;
++	if(showFPS){
++		calculate_frame_rate();
++	}
++
++	next_frm = var->yoffset / var->yres;
++
++	dpu_ctrl_rdma_change(dctrl, next_frm);
++
++	return 0;
++}
++
++static int ingenicfb_do_resume(struct ingenicfb_device *fbdev)
++{
++	struct dpu_ctrl *dctrl = &fbdev->dctrl;
++	int ret = 0;
++
++	ret = dpu_ctrl_resume(dctrl);
++
++	return ret;
++}
++
++static int ingenicfb_do_suspend(struct ingenicfb_device *fbdev)
++{
++	struct dpu_ctrl *dctrl = &fbdev->dctrl;
++	int ret = 0;
++
++	ret = dpu_ctrl_suspend(dctrl);
++
++	return ret;
++}
++
++static int ingenicfb_blank(int blank_mode, struct fb_info *info)
++{
++	struct ingenicfb_device *fbdev = info->par;
++	int ret = 0;
++
++	if (blank_mode == FB_BLANK_UNBLANK) {
++		ret = ingenicfb_do_resume(fbdev);
++	} else {
++		ret = ingenicfb_do_suspend(fbdev);
++	}
++
++	return ret;
++}
++
++static int ingenicfb_open(struct fb_info *info, int user)
++{
++	struct ingenicfb_device *fbdev = info->par;
++	int ret;
++#if 0 //TODO:
++
++	if (!fbdev->is_lcd_en && fbdev->vidmem_phys) {
++		fbdev->timestamp.rp = 0;
++		fbdev->timestamp.wp = 0;
++		ingenicfb_set_fix_par(info);
++		ret = ingenicfb_set_par(info);
++		if(ret) {
++			dev_err(info->dev, "Set par failed!\n");
++			return ret;
++		}
++		memset(fbdev->vidmem[fbdev->current_frm_desc][0], 0, fbdev->frm_size);
++		ingenicfb_enable(info);
++	}
++#endif
++	dev_dbg(info->dev, "####open count : %d\n", ++fbdev->open_cnt);
++
++	return 0;
++}
++
++static int ingenicfb_release(struct fb_info *info, int user)
++{
++	struct ingenicfb_device *fbdev = info->par;
++
++	dev_dbg(info->dev, "####close count : %d\n", fbdev->open_cnt--);
++	if(!fbdev->open_cnt) {
++//		fbdev->timestamp.rp = 0;
++//		fbdev->timestamp.wp = 0;
++	}
++	return 0;
++}
++
++ssize_t ingenicfb_write(struct fb_info *info, const char __user *buf,
++			    size_t count, loff_t *ppos)
++{
++	struct ingenicfb_device *fbdev = info->par;
++	u8 *buffer, *src;
++	u8 __iomem *dst;
++	int c, cnt = 0, err = 0;
++	unsigned long total_size;
++	unsigned long p = *ppos;
++	int screen_base_offset = 0;
++	int next_frm = 0;
++
++	next_frm = info->var.yoffset / info->var.yres;
++
++	screen_base_offset = next_frm * info->screen_size;
++
++	total_size = info->screen_size;
++
++	if (total_size == 0)
++		total_size = info->fix.smem_len;
++
++	if (p > total_size)
++		return -EFBIG;
++
++	if (count > total_size) {
++		err = -EFBIG;
++		count = total_size;
++	}
++
++	if (count + p > total_size) {
++		if (!err)
++			err = -ENOSPC;
++
++		count = total_size - p;
++	}
++
++	buffer = kmalloc((count > PAGE_SIZE) ? PAGE_SIZE : count,
++			 GFP_KERNEL);
++	if (!buffer)
++		return -ENOMEM;
++
++	dst = (u8 __iomem *) (info->screen_base + p + screen_base_offset);
++
++	while (count) {
++		c = (count > PAGE_SIZE) ? PAGE_SIZE : count;
++		src = buffer;
++
++		if (copy_from_user(src, buf, c)) {
++			err = -EFAULT;
++			break;
++		}
++
++		fb_memcpy_tofb(dst, src, c);
++		dst += c;
++		src += c;
++		*ppos += c;
++		buf += c;
++		cnt += c;
++		count -= c;
++	}
++
++	kfree(buffer);
++end:
++	return (cnt) ? cnt : err;
++}
++
++static ssize_t
++ingenicfb_read(struct fb_info *info, char __user *buf, size_t count, loff_t *ppos)
++{
++	unsigned long p = *ppos;
++	u8 *buffer, *dst;
++	u8 __iomem *src;
++	int c, cnt = 0, err = 0;
++	unsigned long total_size;
++
++	int screen_base_offset = 0;
++	int next_frm = 0;
++
++	next_frm = info->var.yoffset / info->var.yres;
++
++	if (!info || ! info->screen_base)
++		return -ENODEV;
++
++	if (info->state != FBINFO_STATE_RUNNING)
++		return -EPERM;
++
++	total_size = info->screen_size;
++
++	if (total_size == 0)
++		total_size = info->fix.smem_len;
++
++	if (p >= total_size)
++		return 0;
++
++	if (count >= total_size)
++		count = total_size;
++
++	if (count + p > total_size)
++		count = total_size - p;
++
++	buffer = kmalloc((count > PAGE_SIZE) ? PAGE_SIZE : count,
++			 GFP_KERNEL);
++	if (!buffer)
++		return -ENOMEM;
++
++	src = (u8 __iomem *) (info->screen_base + p + screen_base_offset);
++
++	while (count) {
++		c  = (count > PAGE_SIZE) ? PAGE_SIZE : count;
++		dst = buffer;
++		fb_memcpy_fromfb(dst, src, c);
++		dst += c;
++		src += c;
++
++		if (copy_to_user(buf, buffer, c)) {
++			err = -EFAULT;
++			break;
++		}
++		*ppos += c;
++		buf += c;
++		cnt += c;
++		count -= c;
++	}
++
++	kfree(buffer);
++
++	return (err) ? err : cnt;
++
++
++}
++
++static struct fb_ops ingenicfb_ops = {
++	.owner 		= THIS_MODULE,
++	.fb_open 	= ingenicfb_open,
++	.fb_release 	= ingenicfb_release,
++	.fb_write 	= ingenicfb_write,
++	.fb_read 	= ingenicfb_read,
++	.fb_check_var 	= ingenicfb_check_var,
++	.fb_set_par 	= ingenicfb_set_par,
++	.fb_setcolreg 	= ingenicfb_setcolreg,
++	.fb_blank 	= ingenicfb_blank,
++	.fb_pan_display = ingenicfb_pan_display,
++	.fb_fillrect 	= cfb_fillrect,
++	.fb_copyarea 	= cfb_copyarea,
++	.fb_imageblit 	= cfb_imageblit,
++	.fb_ioctl 	= ingenicfb_ioctl,
++	.fb_mmap 	= ingenicfb_mmap,
++};
++
++
++static int vsync_skip_set(struct ingenicfb_device *fbdev, int vsync_skip)
++{
++#if 0
++	unsigned int map_wide10 = 0;
++	int rate, i, p, n;
++	int fake_float_1k;
++
++	if (vsync_skip < 0 || vsync_skip > 9)
++		return -EINVAL;
++
++	rate = vsync_skip + 1;
++	fake_float_1k = 10000 / rate;   /* 10.0 / rate */
++
++	p = 1;
++	n = (fake_float_1k * p + 500) / 1000;   /* +0.5 to int */
++
++	for (i = 1; i <= 10; i++) {
++		map_wide10 = map_wide10 << 1;
++		if (i == n) {
++			map_wide10++;
++			p++;
++			n = (fake_float_1k * p + 500) / 1000;
++		}
++	}
++	mutex_lock(&fbdev->lock);
++	fbdev->vsync_skip_map = map_wide10;
++	fbdev->vsync_skip_ratio = rate - 1;     /* 0 ~ 9 */
++	mutex_unlock(&fbdev->lock);
++
++	printk("vsync_skip_ratio = %d\n", fbdev->vsync_skip_ratio);
++	printk("vsync_skip_map = 0x%08x\n", fbdev->vsync_skip_map);
++#endif
++	return 0;
++}
++
++
++static int ingenicfb_copy_logo(struct fb_info *info)
++{
++
++#if 0
++	unsigned long src_addr = 0;	/* u-boot logo buffer address */
++	unsigned long dst_addr = 0;	/* kernel frame buffer address */
++	struct ingenicfb_device *fbdev = info->par;
++	unsigned long size;
++	unsigned int ctrl;
++	unsigned read_times;
++	lay_cfg_en_t lay_cfg_en;
++
++	/* Sure the uboot SLCD using the continuous mode, Close irq */
++	if (!(reg_read(fbdev, DC_ST) & DC_WORKING)) {
++		dev_err(fbdev->dev, "uboot is not display logo!\n");
++#ifdef CONFIG_TRUE_COLOR_LOGO
++        fbdev->current_frm_desc = 0;
++        ingenicfb_set_fix_par(fbdev->fb);
++        ingenicfb_set_par(fbdev->fb);
++        ingenicfb_enable(fbdev->fb);
++        show_logo(fbdev->fb);
++        fb_blank(fbdev->fb, FB_BLANK_UNBLANK);
++#endif
++		return -ENOEXEC;
++	}
++
++	/*fbdev->is_lcd_en = 1;*/
++
++	/* Reading Desc from regisger need reset */
++	ctrl = reg_read(fbdev, DC_CTRL);
++	ctrl |= DC_DES_CNT_RST;
++	reg_write(fbdev, DC_CTRL, ctrl);
++
++	/* For geting LayCfgEn need read  DC_FRM_DES 10 times */
++	read_times = 10 - 1;
++	while(read_times--) {
++		reg_read(fbdev, DC_FRM_DES);
++	}
++	lay_cfg_en.d32 = reg_read(fbdev, DC_FRM_DES);
++	if(!lay_cfg_en.b.lay0_en) {
++		dev_err(fbdev->dev, "Uboot initialization is not using layer0!\n");
++		return -ENOEXEC;
++	}
++
++	/* For geting LayerBufferAddr need read  DC_LAY0_DES 3 times */
++	read_times = 3 - 1;
++	/* get buffer physical address */
++	while(read_times--) {
++		reg_read(fbdev, DC_LAY0_DES);
++	}
++	src_addr = (unsigned long)reg_read(fbdev, DC_LAY0_DES);
++
++	if (src_addr) {
++		size = info->fix.line_length * info->var.yres;
++		src_addr = (unsigned long)phys_to_virt(src_addr);
++		dst_addr = (unsigned long)fbdev->vidmem[0][0];
++		memcpy((void *)dst_addr, (void *)src_addr, size);
++	}
++#endif
++	return 0;
++}
++
++static int ingenicfb_alloc_vidmem(struct ingenicfb_device *fbdev, unsigned int x_res, unsigned int y_res, unsigned int bits_per_pixel)
++{
++	unsigned int alloc_size = 0;
++	int i = 0;
++
++	fbdev->vidmem_size = 0;
++
++	alloc_size = x_res * y_res;
++	fbdev->frm_size = alloc_size * bits_per_pixel >> 3;
++	alloc_size *= MAX_BITS_PER_PIX >> 3;
++
++	alloc_size = alloc_size * CONFIG_FB_INGENIC_NR_FRAMES;
++	fbdev->vidmem[0] = dma_alloc_coherent(fbdev->dev, alloc_size, &fbdev->vidmem_phys[0], GFP_KERNEL);
++
++	if(IS_ERR_OR_NULL(fbdev->vidmem[0])) {
++		return -ENOMEM;
++	}
++	fbdev->vidmem_size = alloc_size;
++
++	for(i = 1; i < CONFIG_FB_INGENIC_NR_FRAMES; i++) {
++		fbdev->vidmem[i] = fbdev->vidmem[0] + i * fbdev->frm_size;
++		fbdev->vidmem_phys[i] = fbdev->vidmem_phys[0] + i * fbdev->frm_size;
++	}
++
++	dev_info(fbdev->dev, "vidmem @ 0x%x size %d\n", fbdev->vidmem[0], fbdev->vidmem_size);
++
++	return 0;
++}
++
++int ingenicfb_release_vidmem(struct ingenicfb_device *fbdev)
++{
++	if(fbdev->vidmem_size) {
++		dma_free_coherent(fbdev->dev, fbdev->vidmem_size, fbdev->vidmem[0], fbdev->vidmem_phys[0]);
++		fbdev->vidmem_size = 0;
++	}
++
++	return 0;
++}
++
++int pan_init_logo(struct fb_info *fb)
++{
++
++#ifdef CONFIG_TRUE_COLOR_LOGO
++	if(!copyed_logo_buf || !fb) {
++		return 0;
++	}
++
++	logo_info.p8 = copyed_logo_buf;
++	show_logo(fb);
++	/* free logo mem */
++//	kfree(copyed_logo_buf);
++//	copyed_logo_buf = NULL;
++#endif
++
++	return 0;
++}
++static int ingenicfb_do_probe(struct platform_device *pdev, struct lcd_panel *panel)
++{
++	struct fb_videomode *video_mode;
++	struct fb_info *fb;
++	struct dpu_ctrl *dctrl;
++	int ret = 0;
++
++	const struct of_device_id *match;
++	struct ingenic_priv *ingenic_priv;
++
++	ret = of_reserved_mem_device_init(&pdev->dev);
++	if(ret)
++		dev_warn(&pdev->dev, "failed to init reserved mem\n");
++
++	fb = framebuffer_alloc(sizeof(struct ingenicfb_device), &pdev->dev);
++	if (!fb) {
++		dev_err(&pdev->dev, "Failed to allocate framebuffer device\n");
++		return -ENOMEM;
++	}
++
++
++	fbdev = fb->par;
++	fbdev->fb = fb;
++	fbdev->dev = &pdev->dev;
++
++	fbdev->dmn.dev = fbdev->dev;
++	fbdev->dmn.data = fbdev;
++	fbdev->dmn.ops = &ingenicfb_dmmu_mm_ops;
++
++	of_property_read_u32(fbdev->dev->of_node, "ingenic,disable-rdma-fb", &fbdev->disable_rdma_fb);
++
++	match = of_match_node(ingenicfb_of_match, pdev->dev.of_node);
++	if (!match)
++		        return -ENODEV;
++	ingenic_priv = (struct ingenic_priv *)match->data;
++	if(panel->dsi_pdata){
++		panel->dsi_pdata->dsi_iobase = ingenic_priv->dsi_iobase;
++		panel->dsi_pdata->dsi_phy_iobase = ingenic_priv->dsi_phy_iobase;
++	}
++	fbdev->panel = panel;
++
++	/*一个�幕�能由多个modes, 将所有的modes转��modelist.*/
++	fb_videomode_to_modelist(panel->modes, panel->num_modes, &fb->modelist);
++
++	/*�一时刻应该�有一个video_mode, 所以�找到active_video_mode.*/
++	fbdev->active_video_mode = &panel->modes[0];
++	ingenicfb_videomode_to_var(&fb->var, fbdev->active_video_mode);
++
++	ret = refresh_pixclock_auto_adapt(fb, fbdev->active_video_mode);
++	if(ret) {
++		goto err_calc_pixclk;
++	}
++
++	dctrl = &fbdev->dctrl;
++
++	dctrl->dev = &pdev->dev;
++	dctrl->pdev = pdev;
++	dctrl->active_video_mode = fbdev->active_video_mode;
++
++	dctrl->set_vsync_value = ingenicfb_set_vsync_value;
++	dctrl->vsync_data = fbdev;
++	dctrl->support_comp = ingenic_priv->support_comp;
++
++	ret = dpu_ctrl_init(dctrl, panel);
++	if(ret) {
++		goto err_dctrl_init;
++	}
++	panel_mipi_init_ok = true;
++
++	if(ingenic_priv->support_comp) {
++		// composer master
++		fbdev->comp_master = hw_composer_init(dctrl);
++		if(IS_ERR_OR_NULL(fbdev->comp_master)) {
++			goto err_comp_init;
++		}
++
++		// one composer instance for fbdev.
++		// using by ioctl procedure.
++		fbdev->comp_ctx = hw_composer_create(fbdev);
++		if(IS_ERR_OR_NULL(fbdev->comp_ctx)) {
++			goto err_comp_ctx;
++		}
++	}
++
++	/*width�是物�尺寸，以mm为��。�以用于计算PPI*/
++	fb->fbops = &ingenicfb_ops;
++	fb->flags = FBINFO_DEFAULT;
++	fb->var.width = panel->width;
++	fb->var.height = panel->height;
++
++	/*默认使用第一个colormode. */
++	fbdev->color_mode = &ingenicfb_colormodes[0];
++	ingenicfb_colormode_to_var(&fb->var, fbdev->color_mode);
++
++	ret = ingenicfb_check_var(&fb->var, fb);
++	if (ret) {
++		goto err_check_var;
++	}
++
++	platform_set_drvdata(pdev, fbdev);
++
++	vsync_skip_set(fbdev, CONFIG_FB_VSYNC_SKIP);
++	init_waitqueue_head(&fbdev->vsync_wq);
++
++
++	fbdev->open_cnt = 0;
++	fbdev->is_lcd_en = 0;
++	fbdev->timestamp.rp = 0;
++	fbdev->timestamp.wp = 0;
++
++
++	if(!fbdev->disable_rdma_fb) {
++
++		ret = ingenicfb_alloc_vidmem(fbdev, fb->var.xres, fb->var.yres, fb->var.bits_per_pixel);
++		if (ret) {
++			dev_err(&pdev->dev, "Failed to allocate video memory\n");
++			goto err_alloc_vidmem;
++		}
++
++		fb->fix = ingenicfb_fix;
++		fb->fix.line_length = (fb->var.bits_per_pixel * fb->var.xres) >> 3;
++		fb->fix.smem_start = fbdev->vidmem_phys[0];
++		fb->fix.smem_len = fbdev->vidmem_size;
++		fb->screen_size = fb->fix.line_length * fb->var.yres;
++		fb->screen_base = fbdev->vidmem[0];
++		fb->pseudo_palette = fbdev->pseudo_palette;
++
++		ret = register_framebuffer(fb);
++		if (ret) {
++			dev_err(&pdev->dev, "Failed to register framebuffer: %d\n",
++					ret);
++			goto err_register_framebuffer;
++		}
++
++
++	}
++
++	/*1. Common setup. */
++	dctrl->chan = DATA_CH_RDMA;
++	dpu_ctrl_setup(dctrl);
++
++
++	if(!fbdev->disable_rdma_fb) {
++		struct rdma_setup_info *rdma_info = &fbdev->rdma_info;
++		rdma_info->nframes = CONFIG_FB_INGENIC_NR_FRAMES;	//TODO:
++		rdma_info->format = fbdev->color_mode->mode;
++		rdma_info->color = fbdev->color_mode->color;
++		rdma_info->stride = fb->var.xres;
++		rdma_info->continuous = 1; //TODO:
++		rdma_info->vidmem = (unsigned char**)&fbdev->vidmem;
++		rdma_info->vidmem_phys = (unsigned int**)&fbdev->vidmem_phys;
++
++		dpu_ctrl_rdma_setup(dctrl, rdma_info);
++
++		dpu_ctrl_rdma_start(dctrl);
++
++		pan_init_logo(fbdev->fb);
++	}
++
++
++	if(ingenic_priv->support_comp) {
++		/*2. compfb init and export.*/
++		fbdev->compfb = hw_compfb_init(fbdev);
++		if(IS_ERR_OR_NULL(fbdev->compfb)) {
++			dev_err(&pdev->dev, "Failed to init compfb!\n");
++			goto err_compfb_init;
++		}
++
++		/*3. export composer.*/
++		fbdev->compfb->active_video_mode = fbdev->active_video_mode;
++		fbdev->compfb->dev = &pdev->dev;
++		fbdev->compfb->panel = panel;
++	}
++
++	{
++		fbdev->comp_v4l2 = hw_comp_v4l2_init(&pdev->dev);
++	}
++
++	ret = dpu_sysfs_init(&fbdev->sysfs, dctrl, fbdev->compfb);
++	if(ret < 0) {
++		dev_err(fbdev->dev, "failed to init sysfs!\n");
++	}
++
++
++	return 0;
++
++err_compfb_init:
++err_register_framebuffer:
++err_alloc_vidmem:
++err_check_var:
++err_comp_ctx:
++	hw_composer_exit(fbdev->comp_master);
++err_comp_init:
++	dpu_ctrl_exit(dctrl);
++err_dctrl_init:
++	fb_delete_videomode(panel->modes, &fb->modelist);
++	fb_destroy_modelist(&fb->modelist);
++err_calc_pixclk:
++	framebuffer_release(fb);
++	return ret;
++}
++
++int ingenicfb_register_panel(struct lcd_panel *panel)
++{
++	WARN_ON(fbdev_panel != NULL);
++
++	if(fbdev_pdev != NULL) {
++		if(panel_mipi_init_ok == false)
++			return ingenicfb_do_probe(fbdev_pdev, panel);
++		else
++			return -EBUSY;
++	}
++
++	fbdev_panel = panel;
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(ingenicfb_register_panel);
++
++static int ingenicfb_probe(struct platform_device *pdev)
++{
++	WARN_ON(fbdev_pdev != NULL);
++
++	fbdev_pdev = pdev;
++
++	if(fbdev_panel != NULL) {
++		return ingenicfb_do_probe(fbdev_pdev, fbdev_panel);
++	}
++
++	return 0;
++}
++
++static int ingenicfb_remove(struct platform_device *pdev)
++{
++	struct ingenicfb_device *fbdev = platform_get_drvdata(pdev);
++
++	// TODO:
++	// release comp_ctx, compfb, comp_v4l2.
++
++	hw_compfb_exit(fbdev->compfb);
++	hw_comp_v4l2_exit(fbdev->comp_v4l2);
++	hw_composer_destroy(fbdev->comp_ctx);
++	hw_composer_exit(fbdev->comp_master);
++
++	dpu_ctrl_exit(&fbdev->dctrl);
++
++	platform_set_drvdata(pdev, NULL);
++
++	dpu_sysfs_exit(&fbdev->sysfs);
++
++	ingenicfb_release_vidmem(fbdev);
++	framebuffer_release(fbdev->fb);
++
++	return 0;
++}
++
++static void ingenicfb_shutdown(struct platform_device *pdev)
++{
++	struct ingenicfb_device *fbdev = platform_get_drvdata(pdev);
++
++	if(!IS_ERR_OR_NULL(fbdev))
++		fb_blank(fbdev->fb, FB_BLANK_POWERDOWN);
++};
++
++#ifdef CONFIG_PM
++
++static int ingenicfb_suspend(struct device *dev)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	struct ingenicfb_device *fbdev = platform_get_drvdata(pdev);
++
++	if(!IS_ERR_OR_NULL(fbdev))
++		fb_blank(fbdev->fb, FB_BLANK_POWERDOWN);
++
++	return 0;
++}
++
++static int ingenicfb_resume(struct device *dev)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	struct ingenicfb_device *fbdev = platform_get_drvdata(pdev);
++
++	if(!IS_ERR_OR_NULL(fbdev))
++		fb_blank(fbdev->fb, FB_BLANK_UNBLANK);
++
++	return 0;
++}
++
++static const struct dev_pm_ops ingenicfb_pm_ops = {
++	.suspend = ingenicfb_suspend,
++	.resume = ingenicfb_resume,
++};
++#endif
++
++static struct ingenic_priv x2000_m300_priv = {
++	.dsi_iobase = 0x10075000,
++	.dsi_phy_iobase = 0x10077000,
++	.support_comp = true,
++};
++
++static struct ingenic_priv x2500_priv = {
++	.dsi_iobase = 0x10003000,
++	.dsi_phy_iobase = 0x10004000,
++	.support_comp = true,
++};
++
++static struct ingenic_priv x1600_priv = {
++	.support_comp = false,
++};
++
++static const struct of_device_id ingenicfb_of_match[] = {
++	{ .compatible = "ingenic,x2000-dpu",.data = (void*)&x2000_m300_priv},
++	{ .compatible = "ingenic,x2500-dpu",.data = (void*)&x2500_priv},
++	{ .compatible = "ingenic,m300-dpu",.data = (void*)&x2000_m300_priv},
++	{ .compatible = "ingenic,x1600-dpu",.data = (void*)&x1600_priv},
++	{},
++};
++
++static struct platform_driver ingenicfb_driver = {
++	.probe = ingenicfb_probe,
++	.remove = ingenicfb_remove,
++	.shutdown = ingenicfb_shutdown,
++	.driver = {
++		.name = "ingenic-fb",
++		.of_match_table = ingenicfb_of_match,
++#ifdef CONFIG_PM
++		.pm = &ingenicfb_pm_ops,
++#endif
++
++	},
++};
++
++static int __init ingenicfb_init(void)
++{
++#ifdef CONFIG_TRUE_COLOR_LOGO
++	/* copy logo_buf from .init.data section */
++	int size;
++	size = logo_info.width*logo_info.height*(logo_info.bpp/8);
++	printk(KERN_INFO "copy logo_buf from .init.data section, size=%d\n", size);
++	copyed_logo_buf = kmalloc(size, GFP_KERNEL);
++	memcpy(copyed_logo_buf, &logo_buf_initdata[0], size);
++#endif
++	platform_driver_register(&ingenicfb_driver);
++	return 0;
++}
++
++static void __exit ingenicfb_cleanup(void)
++{
++	platform_driver_unregister(&ingenicfb_driver);
++}
++
++
++#ifdef CONFIG_EARLY_INIT_RUN
++rootfs_initcall(ingenicfb_init);
++#else
++module_init(ingenicfb_init);
++#endif
++
++module_exit(ingenicfb_cleanup);
++
++MODULE_DESCRIPTION("JZ LCD Controller driver");
++MODULE_AUTHOR("qipenzhen <aric.pzqi@ingenic.com>");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/ingenicfb.h b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/ingenicfb.h
+new file mode 100644
+index 000000000..193fd0d74
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/ingenicfb.h
+@@ -0,0 +1,144 @@
++/* drivers/video/fbdev/ingenic/x2000_v12/ingenicfb.h
++ *
++ * Copyright (C) 2016 Ingenic Semiconductor Inc.
++ *
++ * Author:clwang<chunlei.wang@ingenic.com>
++ *
++ * This program is free software, you can redistribute it and/or modify it
++ *
++ * under the terms of the GNU General Public License version 2 as published by
++ *
++ * the Free Software Foundation.
++ */
++#ifndef __JZ_FB_H__
++#define	__JZ_FB_H__
++#include <linux/fb.h>
++#include <libdmmu.h>
++
++#include "jz_dsim.h"
++
++#include "uapi_ingenicfb.h"
++#include "hw_composer.h"
++#include "dpu_ctrl.h"
++#include "sysfs.h"
++
++#define FRAME_CTRL_DEFAULT_SET  (0x04)
++
++#define FRAME_CFG_ALL_UPDATE (0xFF)
++
++enum {
++	RDMA_CHAIN_CFG_COLOR_RGB = 0,
++	RDMA_CHAIN_CFG_COLOR_RBG = 1,
++	RDMA_CHAIN_CFG_COLOR_GRB = 2,
++	RDMA_CHAIN_CFG_COLOR_GBR = 3,
++	RDMA_CHAIN_CFG_COLOR_BRG = 4,
++	RDMA_CHAIN_CFG_COLOR_BGR = 5,
++};
++enum {
++	RDMA_CHAIN_CFG_FORMAT_555 = 0,
++	RDMA_CHAIN_CFG_FORMAT_ARGB1555 = 1,
++	RDMA_CHAIN_CFG_FORMAT_565 = 2,
++	RDMA_CHAIN_CFG_FORMAT_888 = 4,
++};
++
++struct ingenicfb_timestamp {
++	#define TIMESTAMP_CAP	16
++	volatile int wp; /* write position */
++	int rp;	/* read position */
++	u64 value[TIMESTAMP_CAP];
++};
++
++
++struct ingenicfb_device {
++	int open_cnt;
++	int is_lcd_en;		/* 0, disable  1, enable */
++
++	struct fb_videomode *active_video_mode;
++	struct dpu_ctrl dctrl;
++
++	struct hw_composer_master *comp_master;
++	struct hw_composer_ctx *comp_ctx;
++
++	struct hw_compfb_device *compfb;
++	void *comp_v4l2;
++
++	struct ingenicfb_colormode *color_mode; //当�rdma所用的color_mode;
++	struct rdma_setup_info rdma_info;
++
++	struct fb_info *fb;
++	struct device *dev;
++	struct lcd_panel *panel;
++	int disable_rdma_fb;				//是�将rdma导出为fb节点.dts指定.默认为1, dts�以设置为0.
++
++	struct dpu_sysfs sysfs;
++
++	size_t vidmem_size;
++
++	void *vidmem[CONFIG_FB_INGENIC_NR_FRAMES];
++	dma_addr_t vidmem_phys[CONFIG_FB_INGENIC_NR_FRAMES];
++
++	size_t frm_size;
++
++	wait_queue_head_t vsync_wq;
++	unsigned int vsync_skip_map;	/* 10 bits width */
++	int vsync_skip_ratio;
++
++	struct ingenicfb_timestamp timestamp;
++
++	struct mutex lock;
++	struct mutex suspend_lock;
++
++#ifdef CONFIG_HAS_EARLYSUSPEND
++	struct early_suspend early_suspend;
++#endif
++	int is_suspend;
++	unsigned int pan_display_count;
++	int blank;
++	unsigned int pseudo_palette[16];
++	int slcd_continua;
++
++	unsigned int user_addr;
++	unsigned int tlba;
++	unsigned int tlb_err_cnt;
++	struct dmmu_mm_notifier dmn;
++
++};
++
++static inline struct ingenicfb_device *sysfs_get_fbdev(struct device *dev)
++{
++	return dev_get_drvdata(dev);
++}
++
++static inline struct dpu_ctrl *sysfs_get_dctrl(struct device *dev)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++
++	return &fbdev->dctrl;
++}
++
++static inline struct hw_compfb_device *sysfs_get_compfb(struct device *dev)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++
++	return fbdev->compfb;
++}
++
++
++struct dpu_dmmu_map_info {
++	unsigned int addr;
++	unsigned int len;
++};
++
++struct smash_mode {
++    unsigned long vaddr;
++    int mode;
++};
++
++void ingenicfb_clk_enable(struct ingenicfb_device *ingenicfb);
++void ingenicfb_clk_disable(struct ingenicfb_device *fbdev);
++int ingenicfb_release_vidmem(struct ingenicfb_device *fbdev);
++int pan_init_logo(struct fb_info *fb);
++
++
++extern int ingenicfb_register_panel(struct lcd_panel *panel);
++#endif
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_dsim.h b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_dsim.h
+new file mode 100644
+index 000000000..a5f807e55
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_dsim.h
+@@ -0,0 +1,298 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++#ifndef _JZ_MIPI_DSIM_H
++#define _JZ_MIPI_DSIM_H
++
++#include <linux/device.h>
++#include <linux/fb.h>
++
++#define REFERENCE_FREQ (24000)  //24MHZ, ext
++#define DPHY_DIV_UPPER_LIMIT    (40000)
++#define DPHY_DIV_LOWER_LIMIT    (1000)
++#define MIN_OUTPUT_FREQ		(80)
++
++#define DSIH_FIFO_ACTIVE_WAIT	500
++
++#define PRECISION_FACTOR	(1000)
++#define DSIH_PIXEL_TOLERANCE	2
++
++#define VIDEO_PACKET_OVERHEAD   6
++#define NULL_PACKET_OVERHEAD    6
++#define SHORT_PACKET		4
++#define BLANKING_PACKET         6
++#define MAX_NULL_SIZE		1023
++#define TX_ESC_CLK_DIV		7
++#define MAX_WORD_COUNT     150
++#define PANEL_NAME_SIZE     (32)
++
++
++enum dsi_interface_type {
++	DSIM_COMMAND,
++	DSIM_VIDEO
++};
++
++enum dsi_virtual_ch_no {
++	DSIM_VIRTUAL_CH_0,
++	DSIM_VIRTUAL_CH_1,
++	DSIM_VIRTUAL_CH_2,
++	DSIM_VIRTUAL_CH_3
++};
++
++enum dsi_no_of_data_lane {
++	DSIM_DATA_LANE_1,
++	DSIM_DATA_LANE_2,
++	DSIM_DATA_LANE_3,
++	DSIM_DATA_LANE_4
++};
++
++enum dsi_byte_clk_src {
++	DSIM_PLL_OUT_DIV8,
++	DSIM_EXT_CLK_DIV8,
++	DSIM_EXT_CLK_BYPASS
++};
++
++struct dsi_config {
++	unsigned char max_lanes;
++	unsigned char max_hs_to_lp_cycles;
++	unsigned char max_lp_to_hs_cycles;
++	unsigned short max_bta_cycles;
++	unsigned int max_bps;
++	int color_mode_polarity;
++	int shut_down_polarity;
++	int te_gpio;
++	int te_irq_level;
++	int te_mipi_en;
++
++};
++
++typedef enum {
++	OK = 0,
++	ERR_DSI_COLOR_CODING,
++	ERR_DSI_OUT_OF_BOUND,
++	ERR_DSI_OVERFLOW,
++	ERR_DSI_INVALID_INSTANCE,
++	ERR_DSI_CORE_INCOMPATIBLE,
++	ERR_DSI_VIDEO_MODE,
++	ERR_DSI_INVALID_COMMAND,
++	ERR_DSI_INVALID_EVENT,
++	ERR_DSI_INVALID_HANDLE,
++	ERR_DSI_PHY_POWERUP,
++	ERR_DSI_PHY_INVALID,
++	ERR_DSI_PHY_FREQ_OUT_OF_BOUND,
++	ERR_DSI_TIMEOUT
++} dsih_error_t;
++
++enum {
++	DSI_BLANK_UNBLANK,
++	DSI_BLANK_NORMAL,
++	DSI_BLANK_POWERDOWN,
++	DSI_BLANK_POWERUP
++};
++typedef enum {
++	NOT_INITIALIZED = 0,
++	INITIALIZED,
++	ON,
++	OFF,
++	UBOOT_INITIALIZED
++} dsih_state_t;
++
++typedef enum {
++	VIDEO_NON_BURST_WITH_SYNC_PULSES = 0,
++	VIDEO_NON_BURST_WITH_SYNC_EVENTS,
++	VIDEO_BURST_WITH_SYNC_PULSES
++} dsih_video_mode_t;
++/**
++ *  * Color coding type (depth and pixel configuration)
++ *   */
++typedef enum {
++	COLOR_CODE_16BIT_CONFIG1,
++	COLOR_CODE_16BIT_CONFIG2,
++	COLOR_CODE_16BIT_CONFIG3,
++	COLOR_CODE_18BIT_CONFIG1,
++	COLOR_CODE_18BIT_CONFIG2,
++	COLOR_CODE_24BIT
++} dsih_color_coding_t;
++
++typedef enum {
++	MIPI_PHY_BYTE_CLK_COEF_MUL1 = 0,
++	MIPI_PHY_BYTE_CLK_COEF_MUL3_DIV2 = 1,
++	MIPI_PHY_BYTE_CLK_COEF_MUL4_DIV3 = 2,
++	MIPI_PHY_BYTE_CLK_COEF_MUL5_DIV4 = 3,
++	MIPI_PHY_BYTE_CLK_COEF_MUL6_DIV5 = 4,
++	MIPI_PHY_BYTE_CLK_COEF_MUL2,
++	MIPI_PHY_BYTE_CLK_COEF_MUL3,
++	MIPI_PHY_BYTE_CLK_COEF_MUL4,
++	MIPI_PHY_BYTE_CLK_COEF_MUL5_DIV2,
++	MIPI_PHY_BYTE_CLK_COEF_MUL7_DIV2,
++	MIPI_PHY_BYTE_CLK_COEF_MUL9_DIV2,
++} byte_clock_coef_t;
++
++struct video_config {
++	unsigned char no_of_lanes;
++	unsigned char virtual_channel;
++	dsih_video_mode_t video_mode;
++	int receive_ack_packets;
++	unsigned int byte_clock;
++	byte_clock_coef_t byte_clock_coef;
++	unsigned int pixel_clock;
++	dsih_color_coding_t color_coding;
++	int is_18_loosely;
++	int data_en_polarity;
++	int h_polarity;
++	unsigned short h_active_pixels;	/* hadr */
++	unsigned short h_sync_pixels;
++	unsigned short h_back_porch_pixels;	/* hbp */
++	unsigned short h_total_pixels;	/* h_total */
++	int v_polarity;
++	unsigned short v_active_lines;	/* vadr */
++	unsigned short v_sync_lines;
++	unsigned short v_back_porch_lines;	/* vbp */
++	unsigned short v_total_lines;	/* v_total */
++};
++
++
++struct dsi_device {
++	unsigned int __iomem address;
++	unsigned int __iomem phy_address;
++	struct mutex lock;
++	spinlock_t	irq_lock;
++	struct clk *clk;
++	struct dsi_config *dsi_config;
++	struct dsi_phy *dsi_phy;
++	struct video_config *video_config;
++	struct dsi_master_ops *master_ops;
++	struct mipi_dsim_lcd_device *dsim_lcd_dev;
++	struct mipi_dsim_lcd_driver *dsim_lcd_drv;
++
++
++	struct dsi_cmd_packet *cmd_list;
++	int cmd_packet_len;
++	unsigned int state;
++	unsigned int data_lane;
++	bool suspended;
++	int counter;
++	unsigned int real_mipiclk;
++};
++
++struct dsi_phy {
++	unsigned int reference_freq;
++	dsih_state_t status;
++	unsigned int address;
++	void (*bsp_pre_config) (struct dsi_device * dsi, void *param);
++
++};
++
++struct mipi_dsim_lcd_device {
++	char            *name;
++	struct device       dev;
++	int         id;
++	int         bus_id;
++	int         irq;
++	int         panel_reverse;
++
++	struct dsi_device *master;
++	void            *platform_data;
++};
++
++enum {
++    POWER_ON_LCD = 1,
++    POWER_ON_BL,
++};
++enum {
++    CMD_MIPI_DISPLAY_ON = 1,
++    CMD_MIPI_END,
++};
++struct mipi_dsim_lcd_driver {
++	char            *name;
++	int         id;
++
++	void    (*power_on)(struct mipi_dsim_lcd_device *dsim_dev, int mode);
++	void    (*set_sequence)(struct mipi_dsim_lcd_device *dsim_dev);
++	int    (*ioctl)(struct mipi_dsim_lcd_device *dsim_dev, int cmd);
++	int (*probe)(struct mipi_dsim_lcd_device *dsim_dev);
++	int (*remove)(struct mipi_dsim_lcd_device *dsim_dev);
++	void    (*shutdown)(struct mipi_dsim_lcd_device *dsim_dev);
++	int (*suspend)(struct mipi_dsim_lcd_device *dsim_dev);
++	int (*resume)(struct mipi_dsim_lcd_device *dsim_dev);
++};
++struct mipi_dsim_platform_data {
++	char				lcd_panel_name[PANEL_NAME_SIZE];
++
++	struct mipi_dsim_config		*dsim_config;
++	unsigned int			enabled;
++	void				*lcd_panel_info;
++};
++
++struct dsi_cmd_packet {
++	unsigned char packet_type;
++	unsigned char cmd0_or_wc_lsb;
++	unsigned char cmd1_or_wc_msb;
++	unsigned char cmd_data[MAX_WORD_COUNT];
++};
++
++typedef struct {
++	/** Register offset */
++	unsigned int addr;
++	/** Register data [in or out]*/
++	unsigned int data;
++} register_config_t;
++
++struct freq_ranges {
++	unsigned int freq;	/* upper margin of frequency range */
++	unsigned char hs_freq;	/* hsfreqrange */
++	unsigned char vco_range;	/* vcorange */
++};
++
++struct loop_band {
++	unsigned int loop_div;	/* upper limit of loop divider range */
++	unsigned char cp_current;	/* icpctrl */
++	unsigned char lpf_resistor;	/* lpfctrl */
++};
++
++/*
++ * struct dsi_master_ops - callbacks to mipi-dsi operations.
++ *
++ * @cmd_write: transfer command to lcd panel at LP mode.
++ * @cmd_read: read command from rx register.
++ * @get_dsi_frame_done: get the status that all screen data have been
++ *	transferred to mipi-dsi.
++ * @clear_dsi_frame_done: clear frame done status.
++ * @get_fb_frame_done: get frame done status of display controller.
++ * @trigger: trigger display controller.
++ *	- this one would be used only in case of CPU mode.
++ *  @set_early_blank_mode: set framebuffer blank mode.
++ *	- this callback should be called prior to fb_blank() by a client driver
++ *	only if needing.
++ *  @set_blank_mode: set framebuffer blank mode.
++ *	- this callback should be called after fb_blank() by a client driver
++ *	only if needing.
++ */
++
++struct dsi_master_ops {
++	int (*cmd_write) (struct dsi_device * dsi, struct dsi_cmd_packet cmd_data);
++	int (*cmd_read) (struct dsi_device * dsi, struct dsi_cmd_packet cmd_data, u8 * rx_buf, int count);
++	int (*video_cfg) (struct dsi_device * dsi);
++	int (*mode_cfg) (struct dsi_device *dsi, int mode);
++	int (*query_te) (struct dsi_device *dsi);
++	int (*set_early_blank_mode)(struct dsi_device *dsi, int power);
++	int (*set_blank_mode)(struct dsi_device *dsi, int power);
++	int (*set_blank)(struct dsi_device *dsi, int blank_mode);
++    int (*ioctl)(struct dsi_device *dsi, int cmd);
++};
++
++//extern struct jzdsi_data jzdsi_pdata;
++int mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
++		                        *lcd_dev);
++/**
++ *  * register mipi_dsim_lcd_driver object defined by lcd panel driver
++ *   * to mipi-dsi driver.
++ *    */
++int mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver
++		                        *lcd_drv);
++
++
++#endif /* _JZ_MIPI_DSIM_H */
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/Makefile b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/Makefile
+new file mode 100644
+index 000000000..12ebd6466
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/Makefile
+@@ -0,0 +1 @@
++obj-y += jz_mipi_dsi.o jz_mipi_dsi_lowlevel.o jz_mipi_dsih_hal.o
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsi.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsi.c
+new file mode 100644
+index 000000000..80e30ee20
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsi.c
+@@ -0,0 +1,1031 @@
++/*
++ * Ingenic SoC MIPI-DSI dsim driver.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++#include <linux/wait.h>
++#include <linux/fs.h>
++#include <linux/mm.h>
++#include <linux/fb.h>
++#include <linux/ctype.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/irq.h>
++#include <linux/memory.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/kthread.h>
++#include <linux/notifier.h>
++#include <linux/regulator/consumer.h>
++#include <linux/pm_runtime.h>
++#include <linux/gpio.h>
++
++#include "../ingenicfb.h"
++#include "../jz_dsim.h"
++#include "jz_mipi_dsi_lowlevel.h"
++#include "jz_mipi_dsih_hal.h"
++#include "jz_mipi_dsi_regs.h"
++extern struct jzfb_platform_data jzfb_platform_data;
++#define jzfb_pdata jzfb_platform_data
++
++
++
++struct mipi_dsim_ddi {
++	int				bus_id;
++	struct list_head		list;
++	struct mipi_dsim_lcd_device	*dsim_lcd_dev;
++	struct mipi_dsim_lcd_driver	*dsim_lcd_drv;
++};
++
++static LIST_HEAD(dsim_ddi_list);
++
++static DEFINE_MUTEX(mipi_dsim_lock);
++
++void dump_dsi_reg(struct dsi_device *dsi);
++static DEFINE_MUTEX(dsi_lock);
++
++int jz_dsi_video_cfg(struct dsi_device *dsi)
++{
++	dsih_error_t err_code = OK;
++	unsigned short bytes_per_pixel_x100 = 0;	/* bpp x 100 because it can be 2.25 */
++	unsigned short video_size = 0;
++	unsigned int ratio_clock_xPF = 0;	/* holds dpi clock/byte clock times precision factor */
++	unsigned short null_packet_size = 0;
++	unsigned char video_size_step = 1;
++	unsigned int total_bytes = 0;
++	unsigned int bytes_per_chunk = 0;
++	unsigned int no_of_chunks = 0;
++	unsigned int bytes_left = 0;
++	unsigned int chunk_overhead = 0;
++
++	struct video_config *video_config;
++	video_config = dsi->video_config;
++
++	/* check DSI controller dsi */
++	if ((dsi == NULL) || (video_config == NULL)) {
++		return ERR_DSI_INVALID_INSTANCE;
++	}
++#if 1
++	if(dsi->state == UBOOT_INITIALIZED) {
++		/*no need to reconfig, just return*/
++		printk("dsi has already been initialized by uboot!!\n");
++		return OK;
++	}
++#endif
++	if (dsi->state != INITIALIZED) {
++		return ERR_DSI_INVALID_INSTANCE;
++	}
++
++	ratio_clock_xPF =
++	    (video_config->byte_clock * PRECISION_FACTOR) /
++	    (video_config->pixel_clock);
++
++	video_size = video_config->h_active_pixels;
++	/*  disable set up ACKs and error reporting */
++	mipi_dsih_hal_dpi_frame_ack_en(dsi, video_config->receive_ack_packets);
++	if (video_config->receive_ack_packets) {	/* if ACK is requested, enable BTA, otherwise leave as is */
++		mipi_dsih_hal_bta_en(dsi, 1);
++	}
++	/*0:switch to high speed transfer, 1 low power mode */
++	mipi_dsih_write_word(dsi, R_DSI_HOST_CMD_MODE_CFG, 0);
++	/*0:enable video mode, 1:enable cmd mode */
++	mipi_dsih_hal_gen_set_mode(dsi, 0);
++
++	err_code =
++	    jz_dsi_video_coding(dsi, &bytes_per_pixel_x100, &video_size_step,
++				&video_size);
++	if (err_code) {
++		return err_code;
++	}
++
++	jz_dsi_dpi_cfg(dsi, &ratio_clock_xPF, &bytes_per_pixel_x100);
++
++	/* TX_ESC_CLOCK_DIV must be less than 20000KHz */
++	jz_dsih_hal_tx_escape_division(dsi, TX_ESC_CLK_DIV);
++
++	/* video packetisation   */
++	if (video_config->video_mode == VIDEO_BURST_WITH_SYNC_PULSES) {	/* BURST */
++		//mipi_dsih_hal_dpi_null_packet_en(dsi, 0);
++		mipi_dsih_hal_dpi_null_packet_size(dsi, 0);
++		//mipi_dsih_hal_dpi_multi_packet_en(dsi, 0);
++		err_code =
++		    err_code ? err_code : mipi_dsih_hal_dpi_chunks_no(dsi, 1);
++		err_code =
++		    err_code ? err_code :
++		    mipi_dsih_hal_dpi_video_packet_size(dsi, video_size);
++		if (err_code != OK) {
++			return err_code;
++		}
++		/* BURST by default, returns to LP during ALL empty periods - energy saving */
++		mipi_dsih_hal_dpi_lp_during_hfp(dsi, 1);
++		mipi_dsih_hal_dpi_lp_during_hbp(dsi, 1);
++		mipi_dsih_hal_dpi_lp_during_vactive(dsi, 1);
++		mipi_dsih_hal_dpi_lp_during_vfp(dsi, 1);
++		mipi_dsih_hal_dpi_lp_during_vbp(dsi, 1);
++		mipi_dsih_hal_dpi_lp_during_vsync(dsi, 1);
++#ifdef CONFIG_DSI_DPI_DEBUG
++		/*      D E B U G               */
++		{
++			pr_info("burst video");
++			pr_info("h line time %d ,",
++			       (unsigned
++				short)((video_config->h_total_pixels *
++					ratio_clock_xPF) / PRECISION_FACTOR));
++			pr_info("video_size %d ,", video_size);
++		}
++#endif
++	} else {		/* non burst transmission */
++		null_packet_size = 0;
++		/* bytes to be sent - first as one chunk */
++		bytes_per_chunk =
++		    (bytes_per_pixel_x100 * video_config->h_active_pixels) /
++		    100 + VIDEO_PACKET_OVERHEAD;
++		/* bytes being received through the DPI interface per byte clock cycle */
++		total_bytes =
++		    (ratio_clock_xPF * video_config->no_of_lanes *
++		     (video_config->h_total_pixels -
++		      video_config->h_back_porch_pixels -
++		      video_config->h_sync_pixels)) / PRECISION_FACTOR;
++		pr_debug("---->total_bytes:%d, bytes_per_chunk:%d\n", total_bytes,
++		       bytes_per_chunk);
++		/* check if the in pixels actually fit on the DSI link */
++		if (total_bytes >= bytes_per_chunk) {
++			chunk_overhead = total_bytes - bytes_per_chunk;
++			/* overhead higher than 1 -> enable multi packets */
++			if (chunk_overhead > 1) {
++				for (video_size = video_size_step; video_size < video_config->h_active_pixels; video_size += video_size_step) {	/* determine no of chunks */
++					if ((((video_config->h_active_pixels *
++					       PRECISION_FACTOR) / video_size) %
++					     PRECISION_FACTOR) == 0) {
++						no_of_chunks =
++						    video_config->
++						    h_active_pixels /
++						    video_size;
++						bytes_per_chunk =
++						    (bytes_per_pixel_x100 *
++						     video_size) / 100 +
++						    VIDEO_PACKET_OVERHEAD;
++						if (total_bytes >=
++						    (bytes_per_chunk *
++						     no_of_chunks)) {
++							bytes_left =
++							    total_bytes -
++							    (bytes_per_chunk *
++							     no_of_chunks);
++							break;
++						}
++					}
++				}
++				/* prevent overflow (unsigned - unsigned) */
++				if (bytes_left >
++				    (NULL_PACKET_OVERHEAD * no_of_chunks)) {
++					null_packet_size =
++					    (bytes_left -
++					     (NULL_PACKET_OVERHEAD *
++					      no_of_chunks)) / no_of_chunks;
++					if (null_packet_size > MAX_NULL_SIZE) {	/* avoid register overflow */
++						null_packet_size =
++						    MAX_NULL_SIZE;
++					}
++				}
++			} else {	/* no multi packets */
++				no_of_chunks = 1;
++#ifdef CONFIG_DSI_DPI_DEBUG
++				/*      D E B U G               */
++				{
++					pr_info("no multi no null video");
++					pr_info("h line time %d",
++					       (unsigned
++						short)((video_config->
++							h_total_pixels *
++							ratio_clock_xPF) /
++						       PRECISION_FACTOR));
++					pr_info("video_size %d", video_size);
++				}
++#endif
++				/* video size must be a multiple of 4 when not 18 loosely */
++				for (video_size = video_config->h_active_pixels;
++				     (video_size % video_size_step) != 0;
++				     video_size++) {
++					;
++				}
++			}
++		} else {
++			pr_err
++			    ("resolution cannot be sent to display through current settings");
++			err_code = ERR_DSI_OVERFLOW;
++
++		}
++	}
++	err_code =
++	    err_code ? err_code : mipi_dsih_hal_dpi_chunks_no(dsi,
++							      no_of_chunks);
++	err_code =
++	    err_code ? err_code : mipi_dsih_hal_dpi_video_packet_size(dsi,
++								      video_size);
++	err_code =
++	    err_code ? err_code : mipi_dsih_hal_dpi_null_packet_size(dsi,
++								     null_packet_size);
++
++	// mipi_dsih_hal_dpi_null_packet_en(dsi, null_packet_size > 0? 1: 0);
++	// mipi_dsih_hal_dpi_multi_packet_en(dsi, (no_of_chunks > 1)? 1: 0);
++#ifdef  CONFIG_DSI_DPI_DEBUG
++	/*      D E B U G               */
++	{
++		pr_info("total_bytes %d ,", total_bytes);
++		pr_info("bytes_per_chunk %d ,", bytes_per_chunk);
++		pr_info("bytes left %d ,", bytes_left);
++		pr_info("null packets %d ,", null_packet_size);
++		pr_info("chunks %d ,", no_of_chunks);
++		pr_info("video_size %d ", video_size);
++	}
++#endif
++	mipi_dsih_hal_dpi_video_vc(dsi, video_config->virtual_channel);
++	jz_dsih_dphy_no_of_lanes(dsi, video_config->no_of_lanes);
++	/* enable high speed clock */
++	mipi_dsih_dphy_enable_hs_clk(dsi, 1);
++	pr_debug("video configure is ok!\n");
++	return err_code;
++
++}
++
++/* set all register settings to MIPI DSI controller. */
++dsih_error_t jz_dsi_phy_cfg(struct dsi_device * dsi)
++{
++	dsih_error_t err = OK;
++	err = jz_dsi_set_clock(dsi);
++	if (err) {
++		return err;
++	}
++	err = jz_init_dsi(dsi);
++	if (err) {
++		return err;
++	}
++	return OK;
++}
++
++int jz_dsi_phy_open(struct dsi_device *dsi)
++{
++	struct video_config *video_config;
++	video_config = dsi->video_config;
++
++	pr_debug("entry %s()\n", __func__);
++
++	jz_dsih_dphy_reset(dsi, 0);
++	jz_dsih_dphy_stop_wait_time(dsi, 0x1c);	/* 0x1c: */
++
++	if (video_config->no_of_lanes > 4 || video_config->no_of_lanes < 1)
++		return ERR_DSI_OUT_OF_BOUND;
++	jz_dsih_dphy_no_of_lanes(dsi, video_config->no_of_lanes);
++
++	jz_dsih_dphy_clock_en(dsi, 1);
++	jz_dsih_dphy_shutdown(dsi, 1);
++	jz_dsih_dphy_reset(dsi, 1);
++
++	dsi->dsi_phy->status = INITIALIZED;
++	return OK;
++}
++
++void dump_dsi_reg(struct dsi_device *dsi)
++{
++	pr_info("dsi->dev: ===========>dump dsi reg\n");
++	pr_info("dsi->dev: VERSION------------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VERSION));
++	pr_info("dsi->dev: PWR_UP:------------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_PWR_UP));
++	pr_info("dsi->dev: CLKMGR_CFG---------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_CLKMGR_CFG));
++	pr_info("dsi->dev: DPI_VCID-----------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_DPI_VCID));
++	pr_info("dsi->dev: DPI_COLOR_CODING---:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_DPI_COLOR_CODING));
++	pr_info("dsi->dev: DPI_CFG_POL--------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_DPI_CFG_POL));
++	pr_info("dsi->dev: DPI_LP_CMD_TIM-----:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_DPI_LP_CMD_TIM));
++	pr_info("dsi->dev: DBI_VCID-----------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_DBI_VCID));
++	pr_info("dsi->dev: DBI_CFG------------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_DBI_CFG));
++	pr_info("dsi->dev: DBI_PARTITIONING_EN:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_DBI_PARTITIONING_EN));
++	pr_info("dsi->dev: DBI_CMDSIZE--------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_DBI_CMDSIZE));
++	pr_info("dsi->dev: PCKHDL_CFG---------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_PCKHDL_CFG));
++	pr_info("dsi->dev: GEN_VCID-----------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_GEN_VCID));
++	pr_info("dsi->dev: MODE_CFG-----------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_MODE_CFG));
++	pr_info("dsi->dev: VID_MODE_CFG-------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_MODE_CFG));
++	pr_info("dsi->dev: VID_PKT_SIZE-------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_PKT_SIZE));
++	pr_info("dsi->dev: VID_NUM_CHUNKS-----:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_NUM_CHUNKS));
++	pr_info("dsi->dev: VID_NULL_SIZE------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_NULL_SIZE));
++	pr_info("dsi->dev: VID_HSA_TIME-------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_HSA_TIME));
++	pr_info("dsi->dev: VID_HBP_TIME-------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_HBP_TIME));
++	pr_info("dsi->dev: VID_HLINE_TIME-----:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_HLINE_TIME));
++	pr_info("dsi->dev: VID_VSA_LINES------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_VSA_LINES));
++	pr_info("dsi->dev: VID_VBP_LINES------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_VBP_LINES));
++	pr_info("dsi->dev: VID_VFP_LINES------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_VFP_LINES));
++	pr_info("dsi->dev: VID_VACTIVE_LINES--:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_VACTIVE_LINES));
++	pr_info("dsi->dev: EDPI_CMD_SIZE------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_EDPI_CMD_SIZE));
++	pr_info("dsi->dev: CMD_MODE_CFG-------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_CMD_MODE_CFG));
++	pr_info("dsi->dev: GEN_HDR------------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_GEN_HDR));
++	pr_info("dsi->dev: GEN_PLD_DATA-------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_GEN_PLD_DATA));
++	pr_info("dsi->dev: CMD_PKT_STATUS-----:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_CMD_PKT_STATUS));
++	pr_info("dsi->dev: TO_CNT_CFG---------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_TO_CNT_CFG));
++	pr_info("dsi->dev: HS_RD_TO_CNT-------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_HS_RD_TO_CNT));
++	pr_info("dsi->dev: LP_RD_TO_CNT-------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_LP_RD_TO_CNT));
++	pr_info("dsi->dev: HS_WR_TO_CNT-------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_HS_WR_TO_CNT));
++	pr_info("dsi->dev: LP_WR_TO_CNT_CFG---:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_LP_WR_TO_CNT));
++	pr_info("dsi->dev: BTA_TO_CNT---------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_BTA_TO_CNT));
++	pr_info("dsi->dev: SDF_3D-------------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_SDF_3D));
++	pr_info("dsi->dev: LPCLK_CTRL---------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_LPCLK_CTRL));
++	pr_info("dsi->dev: PHY_TMR_LPCLK_CFG--:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_PHY_TMR_LPCLK_CFG));
++	pr_info("dsi->dev: PHY_TMR_CFG--------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_PHY_TMR_CFG));
++	pr_info("dsi->dev: PHY_RSTZ-----------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_PHY_RSTZ));
++	pr_info("dsi->dev: PHY_IF_CFG---------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_PHY_IF_CFG));
++	pr_info("dsi->dev: PHY_ULPS_CTRL------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_PHY_ULPS_CTRL));
++	pr_info("dsi->dev: PHY_TX_TRIGGERS----:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_PHY_TX_TRIGGERS));
++	pr_info("dsi->dev: PHY_STATUS---------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_PHY_STATUS));
++	pr_info("dsi->dev: PHY_TST_CTRL0------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_PHY_TST_CTRL0));
++	pr_info("dsi->dev: PHY_TST_CTRL1------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_PHY_TST_CTRL1));
++	pr_info("dsi->dev: INT_ST0------------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_INT_ST0));
++	pr_info("dsi->dev: INT_ST1------------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_INT_ST1));
++	pr_info("dsi->dev: INT_MSK0-----------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_INT_MSK0));
++	pr_info("dsi->dev: INT_MSK1-----------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_INT_MSK1));
++	pr_info("dsi->dev: INT_FORCE0---------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_INT_FORCE0));
++	pr_info("dsi->dev: INT_FORCE1---------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_INT_FORCE1));
++	pr_info("dsi->dev: VID_SHADOW_CTRL----:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_SHADOW_CTRL));
++	pr_info("dsi->dev: DPI_VCID_ACT-------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_DPI_VCID_ACT));
++	pr_info("dsi->dev: DPI_COLOR_CODING_AC:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_DPI_COLOR_CODING_ACT));
++	pr_info("dsi->dev: DPI_LP_CMD_TIM_ACT-:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_DPI_LP_CMD_TIM_ACT));
++	pr_info("dsi->dev: VID_MODE_CFG_ACT---:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_MODE_CFG_ACT));
++	pr_info("dsi->dev: VID_PKT_SIZE_ACT---:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_PKT_SIZE_ACT));
++	pr_info("dsi->dev: VID_NUM_CHUNKS_ACT-:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_NUM_CHUNKS_ACT));
++	pr_info("dsi->dev: VID_HSA_TIME_ACT---:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_HSA_TIME_ACT));
++	pr_info("dsi->dev: VID_HBP_TIME_ACT---:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_HBP_TIME_ACT));
++	pr_info("dsi->dev: VID_HLINE_TIME_ACT-:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_HLINE_TIME_ACT));
++	pr_info("dsi->dev: VID_VSA_LINES_ACT--:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_VSA_LINES_ACT));
++	pr_info("dsi->dev: VID_VBP_LINES_ACT--:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_VBP_LINES_ACT));
++	pr_info("dsi->dev: VID_VFP_LINES_ACT--:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_VFP_LINES_ACT));
++	pr_info("dsi->dev: VID_VACTIVE_LINES_ACT:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_VID_VACTIVE_LINES_ACT));
++	pr_info("dsi->dev: SDF_3D_ACT---------:%08x\n",
++		 mipi_dsih_read_word(dsi, R_DSI_HOST_SDF_3D_ACT));
++
++}
++
++void set_base_dir_tx(struct dsi_device *dsi, void *param)
++{
++	int i = 0;
++	register_config_t phy_direction[] = {
++		{0xb4, 0x02},
++		{0xb8, 0xb0},
++		{0xb8, 0x100b0},
++		{0xb4, 0x00},
++		{0xb8, 0x000b0},
++		{0xb8, 0x0000},
++		{0xb4, 0x02},
++		{0xb4, 0x00}
++	};
++	i = mipi_dsih_write_register_configuration(dsi, phy_direction,
++						   (sizeof(phy_direction) /
++						    sizeof(register_config_t)));
++	if (i != (sizeof(phy_direction) / sizeof(register_config_t))) {
++		pr_err("ERROR setting up testchip %d", i);
++	}
++}
++
++static int jz_mipi_update_cfg(struct dsi_device *dsi)
++{
++	int ret;
++	int st_mask = 0;
++	int retry = 5;
++	ret = jz_dsi_phy_open(dsi);
++	if (ret) {
++		pr_err("open the phy failed!\n");
++		return ret;
++	}
++
++	mipi_dsih_write_word(dsi, R_DSI_HOST_CMD_MODE_CFG,
++				     0xffffff0);
++
++	/*set command mode */
++	mipi_dsih_write_word(dsi, R_DSI_HOST_MODE_CFG, 0x1);
++	/*set this register for cmd size, default 0x6 */
++	mipi_dsih_write_word(dsi, R_DSI_HOST_EDPI_CMD_SIZE, 6);
++
++	/*
++	 * jz_dsi_phy_cfg:
++	 * PLL programming, config the output freq to DEFAULT_DATALANE_BPS.
++	 * */
++	ret = jz_dsi_phy_cfg(dsi);
++	if (ret) {
++		pr_err("phy configigure failed!\n");
++		return ret;
++	}
++
++	pr_debug("wait for phy config ready\n");
++	if (dsi->video_config->no_of_lanes == 2)
++		st_mask = 0x95;
++	else
++		st_mask = 0x15;
++
++	/*checkout phy clk lock and  clklane, datalane stopstate  */
++	udelay(10);
++	while ((mipi_dsih_read_word(dsi, R_DSI_HOST_PHY_STATUS) & st_mask) !=
++			st_mask && --retry) {
++		pr_info("phy status = %08x\n", mipi_dsih_read_word(dsi, R_DSI_HOST_PHY_STATUS));
++	}
++
++	if (!retry){
++		pr_err("wait for phy config failed!\n");
++		//return ret;
++	}
++
++	dsi->state = INITIALIZED;
++	return 0;
++}
++
++/* for debug lcd power on/off */
++int jz_mipi_dsi_set_client(struct dsi_device *dsi, int power)
++{
++	struct mipi_dsim_lcd_driver *client_drv = dsi->dsim_lcd_drv;
++	struct mipi_dsim_lcd_device *client_dev = dsi->dsim_lcd_dev;
++
++	switch (power) {
++	case FB_BLANK_POWERDOWN:
++		if (client_drv && client_drv->suspend)
++			client_drv->suspend(client_dev);
++
++		break;
++	case FB_BLANK_UNBLANK:
++		/* lcd panel power on. */
++		if (client_drv && client_drv->power_on)
++			client_drv->power_on(client_dev, POWER_ON_LCD);
++
++		/* set lcd panel sequence commands. */
++		if (client_drv && client_drv->set_sequence)
++			client_drv->set_sequence(client_dev);
++
++		break;
++	case FB_BLANK_NORMAL:
++		/* TODO. */
++		break;
++
++	default:
++		break;
++	}
++	return 0;
++}
++
++static int jz_mipi_dsi_blank_mode(struct dsi_device *dsi, int power)
++{
++	struct mipi_dsim_lcd_driver *client_drv = dsi->dsim_lcd_drv;
++	struct mipi_dsim_lcd_device *client_dev = dsi->dsim_lcd_dev;
++
++    switch (power) {
++	case FB_BLANK_POWERDOWN:
++        if (dsi->suspended)
++            return 0;
++
++        if (client_drv && client_drv->suspend)
++            client_drv->suspend(client_dev);
++
++	jz_dsih_dphy_reset(dsi, 0);
++        jz_dsih_dphy_shutdown(dsi, 0);
++        mipi_dsih_hal_power(dsi, 0);
++        jz_dsih_dphy_clock_en(dsi, 0);
++        clk_disable_unprepare(dsi->clk);
++
++        dsi->state = NOT_INITIALIZED;
++        dsi->suspended = true;
++
++        break;
++    case FB_BLANK_UNBLANK:
++        if (!dsi->suspended)
++            return 0;
++
++        clk_prepare_enable(dsi->clk);
++        jz_mipi_update_cfg(dsi);
++
++        /* lcd panel power on. */
++        if (client_drv && client_drv->power_on)
++            client_drv->power_on(client_dev, POWER_ON_LCD);
++
++        /* set lcd panel sequence commands. */
++        if (client_drv && client_drv->set_sequence)
++            client_drv->set_sequence(client_dev);
++
++        dsi->suspended = false;
++
++        break;
++    case FB_BLANK_NORMAL:
++        /* TODO. */
++        break;
++
++
++    default:
++        break;
++    }
++
++    return 0;
++}
++
++static int jz_mipi_dsi_ioctl(struct dsi_device *dsi, int cmd)
++{
++    struct mipi_dsim_lcd_driver *client_drv = dsi->dsim_lcd_drv;
++    struct mipi_dsim_lcd_device *client_dev = dsi->dsim_lcd_dev;
++
++    if (client_drv && client_drv->ioctl)
++        client_drv->ioctl(client_dev, cmd);
++
++    return 0;
++}
++
++int jz_dsi_mode_cfg(struct dsi_device *dsi, int mode)
++{
++	struct video_config *video_config;
++	struct dsi_config *dsi_config;
++	video_config = dsi->video_config;
++	dsi_config = dsi->dsi_config;
++
++	if(mode == 1) {
++		/* video mode */
++		jz_dsih_hal_power(dsi, 0);
++		jz_dsi_video_cfg(dsi);
++		jz_dsih_hal_power(dsi, 1);
++	} else {
++		mipi_dsih_write_word(dsi, R_DSI_HOST_EDPI_CMD_SIZE, 1024); /* 当设置太�时, 对于M31传输数�会有�死的现象??, 这里设置�1024。*/
++		mipi_dsih_dphy_enable_hs_clk(dsi, 1);
++		mipi_dsih_dphy_auto_clklane_ctrl(dsi, 1);
++		mipi_dsih_write_word(dsi, R_DSI_HOST_CMD_MODE_CFG, 1);
++
++		/* cmd mode */
++		/* color coding fix to 24bit ???? */
++		mipi_dsih_hal_dpi_frame_ack_en(dsi, video_config->receive_ack_packets);
++		if (video_config->receive_ack_packets) {	/* if ACK is requested, enable BTA, otherwise leave as is */
++			mipi_dsih_hal_bta_en(dsi, 1);
++		}
++		if(dsi_config->te_mipi_en) {
++			mipi_dsih_hal_tear_effect_ack_en(dsi, 1);
++		} else {
++			mipi_dsih_hal_tear_effect_ack_en(dsi, 0);
++		}
++		mipi_dsih_hal_gen_set_mode(dsi, 1);
++		mipi_dsih_hal_dpi_color_coding(dsi, dsi->video_config->color_coding);
++	}
++
++	return 0;
++}
++
++static int jz_dsi_query_te(struct dsi_device *dsi)
++{
++	struct dsi_cmd_packet set_tear_on = {0x15, 0x35, 0x00};
++	/* unsigned int cmd_mode_cfg; */
++
++	if(!dsi->dsi_config->te_mipi_en)
++		return 0;
++
++	//return 0;
++
++	/* According to DSI host spec. */
++	/*
++	Tearing effect request must always be triggered by a set_tear_on
++	command in the DWC_mipi_dsi_host implementation
++	*/
++	write_command(dsi, set_tear_on);
++
++	return 0;
++
++}
++
++/* define MIPI-DSI Master operations. */
++static struct dsi_master_ops jz_master_ops = {
++    .video_cfg      = jz_dsi_video_cfg,
++    .mode_cfg	    = jz_dsi_mode_cfg,
++    .cmd_write      = write_command,	/*jz_dsi_wr_data, */
++    .query_te	    = jz_dsi_query_te,
++    .cmd_read       = read_command,	/*jz_dsi_rd_data, */
++    .ioctl          = jz_mipi_dsi_ioctl,
++    .set_blank_mode = jz_mipi_dsi_blank_mode,
++};
++
++int mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device *lcd_dev)
++{
++	struct mipi_dsim_ddi *dsim_ddi;
++
++	if (!lcd_dev->name) {
++		pr_err("dsim_lcd_device name is NULL.\n");
++		return -EFAULT;
++	}
++
++	dsim_ddi = kzalloc(sizeof(struct mipi_dsim_ddi), GFP_KERNEL);
++	if (!dsim_ddi) {
++		pr_err("failed to allocate dsim_ddi object.\n");
++		return -ENOMEM;
++	}
++
++	dsim_ddi->dsim_lcd_dev = lcd_dev;
++
++	mutex_lock(&mipi_dsim_lock);
++	list_add_tail(&dsim_ddi->list, &dsim_ddi_list);
++	mutex_unlock(&mipi_dsim_lock);
++
++	return 0;
++}
++EXPORT_SYMBOL(mipi_dsi_register_lcd_device);
++static struct mipi_dsim_ddi *mipi_dsi_find_lcd_device(
++					struct mipi_dsim_lcd_driver *lcd_drv)
++{
++	struct mipi_dsim_ddi *dsim_ddi, *next;
++	struct mipi_dsim_lcd_device *lcd_dev;
++
++	mutex_lock(&mipi_dsim_lock);
++
++	list_for_each_entry_safe(dsim_ddi, next, &dsim_ddi_list, list) {
++		if (!dsim_ddi)
++			goto out;
++
++		lcd_dev = dsim_ddi->dsim_lcd_dev;
++		if (!lcd_dev)
++			continue;
++
++		if ((strcmp(lcd_drv->name, lcd_dev->name)) == 0) {
++			/**
++			 * bus_id would be used to identify
++			 * connected bus.
++			 */
++			dsim_ddi->bus_id = lcd_dev->bus_id;
++			mutex_unlock(&mipi_dsim_lock);
++
++			return dsim_ddi;
++		}
++
++		list_del(&dsim_ddi->list);
++		kfree(dsim_ddi);
++	}
++
++out:
++	mutex_unlock(&mipi_dsim_lock);
++
++	return NULL;
++}
++
++int mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver *lcd_drv)
++{
++	struct mipi_dsim_ddi *dsim_ddi;
++
++	if (!lcd_drv->name) {
++		pr_err("dsim_lcd_driver name is NULL.\n");
++		return -EFAULT;
++	}
++
++	dsim_ddi = mipi_dsi_find_lcd_device(lcd_drv);
++	if (!dsim_ddi) {
++		pr_err("mipi_dsim_ddi object not found.\n");
++		return -EFAULT;
++	}
++
++	dsim_ddi->dsim_lcd_drv = lcd_drv;
++
++	pr_info("registered panel driver(%s) to mipi-dsi driver.\n",
++		lcd_drv->name);
++
++	return 0;
++
++}
++EXPORT_SYMBOL(mipi_dsi_register_lcd_driver);
++
++static void dummy_release(struct device *dev)
++{
++
++}
++
++static struct mipi_dsim_ddi *mipi_dsi_bind_lcd_ddi(
++						struct dsi_device *dsim,
++						const char *name)
++{
++	struct mipi_dsim_ddi *dsim_ddi, *next;
++	struct mipi_dsim_lcd_driver *lcd_drv;
++	struct mipi_dsim_lcd_device *lcd_dev;
++	int ret;
++
++	mutex_lock(&dsim->lock);
++
++	list_for_each_entry_safe(dsim_ddi, next, &dsim_ddi_list, list) {
++		lcd_drv = dsim_ddi->dsim_lcd_drv;
++		lcd_dev = dsim_ddi->dsim_lcd_dev;
++
++		pr_debug("dsi->dev: lcd_drv->name  = %s, name = %s\n",
++				lcd_drv->name, name);
++		if ((strcmp(lcd_drv->name, name) == 0)) {
++			lcd_dev->master = dsim;
++
++			dev_set_name(&lcd_dev->dev, "%s", lcd_drv->name);
++
++			ret = device_register(&lcd_dev->dev);
++			if (ret < 0) {
++				pr_err("can't register %s, status %d\n",
++					dev_name(&lcd_dev->dev), ret);
++				mutex_unlock(&dsim->lock);
++				return NULL;
++			}
++
++			lcd_dev->dev.release = dummy_release;
++
++			dsim->dsim_lcd_dev = lcd_dev;
++			dsim->dsim_lcd_drv = lcd_drv;
++
++			mutex_unlock(&dsim->lock);
++
++			return dsim_ddi;
++		}else{
++			pr_err("dsi->dev: lcd_drv->name is different with fb name\n");
++		}
++	}
++
++	mutex_unlock(&dsim->lock);
++
++	return NULL;
++}
++
++static struct mipi_dsim_ddi *mipi_dsi_unbind_lcd_ddi(struct dsi_device *dsim, const char *name)
++{
++	struct mipi_dsim_ddi *dsim_ddi, *next;
++	struct mipi_dsim_lcd_driver *lcd_drv;
++	struct mipi_dsim_lcd_device *lcd_dev;
++	int ret;
++
++	mutex_lock(&dsim->lock);
++	list_for_each_entry_safe(dsim_ddi, next, &dsim_ddi_list, list) {
++
++		lcd_drv = dsim_ddi->dsim_lcd_drv;
++		lcd_dev = dsim_ddi->dsim_lcd_dev;
++
++		pr_debug("dsi->dev: lcd_drv->name  = %s, name = %s\n",
++				lcd_drv->name, name);
++		if ((strcmp(lcd_drv->name, name) == 0)) {
++
++			device_unregister(&lcd_dev->dev);
++
++			/*TODO:*/
++			dsim->dsim_lcd_dev = NULL;
++			dsim->dsim_lcd_drv = NULL;
++
++			mutex_unlock(&dsim->lock);
++
++			return dsim_ddi;
++		}else{
++			pr_err("dsi->dev: lcd_drv->name is different with fb name\n");
++		}
++	}
++
++	mutex_unlock(&dsim->lock);
++
++	return NULL;
++}
++
++struct dsi_device * jzdsi_init(struct jzdsi_data *pdata)
++{
++	struct dsi_device *dsi;
++	struct dsi_phy *dsi_phy;
++	struct mipi_dsim_ddi *dsim_ddi;
++	int ret = -EINVAL;
++	pr_debug("entry %s()\n", __func__);
++
++	dsi = (struct dsi_device *)kzalloc(sizeof(struct dsi_device), GFP_KERNEL);
++	if (!dsi) {
++		pr_err("dsi->dev: failed to allocate dsi object.\n");
++		ret = -ENOMEM;
++		goto err_dsi;
++	}
++
++	dsi_phy = (struct dsi_phy *)kzalloc(sizeof(struct dsi_phy), GFP_KERNEL);
++	if (!dsi_phy) {
++		pr_err("dsi->dev: failed to allocate dsi phy  object.\n");
++		ret = -ENOMEM;
++		goto err_dsi_phy;
++	}
++	dsi->dsi_config = &(pdata->dsi_config);
++
++	dsi_phy->status = NOT_INITIALIZED;
++	dsi_phy->reference_freq = REFERENCE_FREQ;
++	dsi_phy->bsp_pre_config = set_base_dir_tx;
++	dsi->dsi_phy = dsi_phy;
++	dsi->video_config = &(pdata->video_config);
++	dsi->video_config->pixel_clock = PICOS2KHZ(pdata->modes->pixclock);	// dpi_clock
++	dsi->video_config->h_polarity = pdata->modes->sync & FB_SYNC_HOR_HIGH_ACT;
++	dsi->video_config->h_active_pixels = pdata->modes->xres;
++	dsi->video_config->h_sync_pixels = pdata->modes->hsync_len;
++	dsi->video_config->h_back_porch_pixels = pdata->modes->left_margin;
++	dsi->video_config->h_total_pixels = pdata->modes->xres + pdata->modes->hsync_len + pdata->modes->left_margin + pdata->modes->right_margin;
++	dsi->video_config->v_active_lines = pdata->modes->yres;
++	dsi->video_config->v_polarity =  pdata->modes->sync & FB_SYNC_VERT_HIGH_ACT;
++	dsi->video_config->v_sync_lines = pdata->modes->vsync_len;
++	dsi->video_config->v_back_porch_lines = pdata->modes->upper_margin;
++	dsi->video_config->v_total_lines = pdata->modes->yres + pdata->modes->upper_margin + pdata->modes->lower_margin + pdata->modes->vsync_len;
++
++	pr_debug("dsi->video_config->h_total_pixels: %d\n", dsi->video_config->h_total_pixels);
++	pr_debug("dsi->video_config->v_total_lines: %d\n", dsi->video_config->v_total_lines);
++	pr_debug("jzfb_pdata.modes->refresh: %d\n", pdata->modes->refresh);
++	pr_debug("jzfb_pdata.bpp: %d\n", pdata->bpp_info);
++	pr_debug("dsi->video_config->no_of_lanes: %d\n", dsi->video_config->no_of_lanes);
++	pr_debug("---dsi->video_config->byte_clock: %d\n", dsi->video_config->byte_clock);
++
++	if(!dsi->video_config->byte_clock) {
++		dsi->video_config->byte_clock = dsi->video_config->h_total_pixels * dsi->video_config->v_total_lines * pdata->modes->refresh * 32 / dsi->video_config->no_of_lanes / 8 / 1000 ;
++		switch(dsi->video_config->byte_clock_coef) {
++		case MIPI_PHY_BYTE_CLK_COEF_MUL1:
++			break;
++		case MIPI_PHY_BYTE_CLK_COEF_MUL3:
++			dsi->video_config->byte_clock = dsi->video_config->byte_clock*3;
++			break;
++		case MIPI_PHY_BYTE_CLK_COEF_MUL4:
++			dsi->video_config->byte_clock = dsi->video_config->byte_clock*4;
++			break;
++		case MIPI_PHY_BYTE_CLK_COEF_MUL3_DIV2:
++			dsi->video_config->byte_clock = dsi->video_config->byte_clock * 3 / 2;
++			break;
++		case MIPI_PHY_BYTE_CLK_COEF_MUL4_DIV3:
++			dsi->video_config->byte_clock = dsi->video_config->byte_clock * 4 / 3;
++			break;
++		case MIPI_PHY_BYTE_CLK_COEF_MUL5_DIV4:
++			dsi->video_config->byte_clock = dsi->video_config->byte_clock * 5 / 4;
++			break;
++		case MIPI_PHY_BYTE_CLK_COEF_MUL6_DIV5:
++			dsi->video_config->byte_clock = dsi->video_config->byte_clock * 6 / 5;
++			break;
++		default:
++			break;
++		}
++	}
++
++	if (dsi->video_config->byte_clock * 8 > dsi->dsi_config->max_bps * 1000) {
++		dsi->video_config->byte_clock = dsi->dsi_config->max_bps * 1000 / 8;
++		pr_err("+++++++++++++warning: DATALANE_BPS is over lcd max_bps allowed ,auto set it lcd max_bps\n");
++	}
++
++	dsi->real_mipiclk = dsi->video_config->byte_clock * 8 * 1000;
++
++	/*dsi->video_config->byte_clock = dsi->video_config->pixel_clock / 4;*/
++
++	pr_debug("%s, %d byte_clock %d KHz, pixel_clock:%d KHz\n", __func__, __LINE__, dsi->video_config->byte_clock, dsi->video_config->pixel_clock);
++
++	dsi->master_ops = &jz_master_ops;
++
++	dsi->clk = clk_get(NULL, "gate_dsi");
++	if (IS_ERR(dsi->clk)) {
++		pr_err("failed to get dsi clock source\n");
++		goto err_put_clk;
++	}
++	clk_prepare_enable(dsi->clk);
++	dsi->address = (unsigned int)ioremap(pdata->dsi_iobase, 0x190);
++	if (!dsi->address) {
++		pr_err("Failed to ioremap register dsi memory region\n");
++		goto err_iounmap;
++	}
++	dsi->phy_address = (unsigned int)ioremap(pdata->dsi_phy_iobase, 0x200);
++	if(!dsi->phy_address) {
++		pr_err("Failed to ioremap dsi phy memory region!\n");
++		goto err_iounmap;
++	}
++
++	mutex_init(&dsi->lock);
++
++	dsim_ddi = mipi_dsi_bind_lcd_ddi(dsi, pdata->modes->name);
++	if (!dsim_ddi) {
++		pr_err("dsi->dev: mipi_dsim_ddi object not found.\n");
++		ret = -EINVAL;
++		goto err_bind_lcd;
++	}
++
++	dsi->state = NOT_INITIALIZED; /*must be here for set_sequence function*/
++	ret = jz_mipi_update_cfg(dsi);
++	if (ret) {
++		goto err_dsi_init;
++	}
++
++	if (dsim_ddi->dsim_lcd_drv && dsim_ddi->dsim_lcd_drv->probe) {
++		ret = dsim_ddi->dsim_lcd_drv->probe(dsim_ddi->dsim_lcd_dev);
++		if(ret < 0) {
++			pr_err("Failed to probe dsi lcd panel!\n");
++
++			goto err_lcd_probe;
++		}
++	}
++
++	if (dsim_ddi->dsim_lcd_drv) {
++		if (dsim_ddi->dsim_lcd_drv->power_on)
++			dsim_ddi->dsim_lcd_drv->power_on(dsim_ddi->dsim_lcd_dev, 1);
++		if (dsim_ddi->dsim_lcd_drv->set_sequence)
++			dsim_ddi->dsim_lcd_drv->set_sequence(dsim_ddi->dsim_lcd_dev);
++	}else{
++		pr_err("lcd mipi panel init failed!\n");
++		goto err_panel_init;
++	}
++
++	/* jz_mipi_dsi_init_interrupt(dsi); */
++
++	dsi->suspended = false;
++
++#ifdef CONFIG_DSI_DPI_DEBUG	/*test pattern */
++	unsigned int tmp = 0;
++	jz_dsi_video_cfg(dsi);
++
++	tmp = mipi_dsih_read_word(dsi, R_DSI_HOST_VID_MODE_CFG);
++	tmp |= 1 << 16 | 0 << 20 | 1 << 24;
++	mipi_dsih_write_word(dsi, R_DSI_HOST_VID_MODE_CFG, tmp);
++#endif
++
++	return dsi;
++err_panel_init:
++	pr_err("dsi->dev: lcd mipi panel init error\n");
++err_lcd_probe:
++	mipi_dsi_unbind_lcd_ddi(dsi, pdata->modes->name);
++err_dsi_init:
++	pr_err("dsi->dev: lcd mipi dsi init error\n");
++err_bind_lcd:
++	iounmap((void __iomem *)dsi->address);
++err_iounmap:
++	clk_put(dsi->clk);
++err_put_clk:
++	kfree(dsi_phy);
++err_dsi_phy:
++	kfree(dsi);
++err_dsi:
++	return NULL;
++}
++
++void jzdsi_remove(struct dsi_device *dsi)
++{
++	struct dsi_phy *dsi_phy;
++	dsi_phy = dsi->dsi_phy;
++
++	iounmap((void __iomem *)dsi->address);
++	clk_disable(dsi->clk);
++	clk_put(dsi->clk);
++	kfree(dsi_phy);
++	kfree(dsi);
++}
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsi_lowlevel.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsi_lowlevel.c
+new file mode 100644
+index 000000000..0be9a5093
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsi_lowlevel.c
+@@ -0,0 +1,705 @@
++/*
++ * Ingenic SoC MIPI-DSI lowlevel driver.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/mutex.h>
++#include <linux/wait.h>
++#include <linux/delay.h>
++#include <linux/fs.h>
++#include <linux/mm.h>
++#include <linux/ctype.h>
++#include <linux/io.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++
++#include "../jz_dsim.h"
++#include "jz_mipi_dsi_regs.h"
++#include "jz_mipi_dsih_hal.h"
++
++struct freq_ranges ranges[] = {
++	{90, 0x00, 0x01}, {100, 0x10, 0x01}, {110, 0x20, 0x01},
++	{125, 0x01, 0x01}, {140, 0x11, 0x01}, {150, 0x21, 0x01},
++	{160, 0x02, 0x01}, {180, 0x12, 0x03}, {200, 0x22, 0x03},
++	{210, 0x03, 0x03}, {240, 0x13, 0x03}, {250, 0x23, 0x03},
++	{270, 0x04, 0x07}, {300, 0x14, 0x07}, {330, 0x24, 0x07},
++	{360, 0x15, 0x07}, {400, 0x25, 0x07}, {450, 0x06, 0x07},
++	{500, 0x16, 0x07}, {550, 0x07, 0x0f}, {600, 0x17, 0x0f},
++	{650, 0x08, 0x0f}, {700, 0x18, 0x0f}, {750, 0x09, 0x0f},
++	{800, 0x19, 0x0f}, {850, 0x0A, 0x0f}, {900, 0x1A, 0x0f},
++	{950, 0x2A, 0x0f}, {1000, 0x3A, 0x0f}
++};
++
++struct loop_band loop_bandwidth[] = {
++	{32, 0x06, 0x10}, {64, 0x06, 0x10}, {128, 0x0C, 0x08},
++	{256, 0x04, 0x04}, {512, 0x00, 0x01}, {768, 0x01, 0x01},
++	{1000, 0x02, 0x01}
++};
++
++void jz_dsih_dphy_reset(struct dsi_device *dsi, int reset)
++{
++
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_RSTZ, reset, 1, 1);
++}
++
++void jz_dsih_dphy_stop_wait_time(struct dsi_device *dsi,
++				 unsigned char no_of_byte_cycles)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_IF_CFG, no_of_byte_cycles, 8,
++			     8);
++}
++
++void jz_dsih_dphy_no_of_lanes(struct dsi_device *dsi, unsigned char no_of_lanes)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_IF_CFG, no_of_lanes - 1, 0, 2);
++}
++
++void jz_dsih_dphy_clock_en(struct dsi_device *dsi, int en)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_RSTZ, en, 2, 1);
++}
++
++void jz_dsih_dphy_shutdown(struct dsi_device *dsi, int powerup)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_RSTZ, powerup, 0, 1);
++}
++
++void jz_dsih_dphy_ulpm_enter(struct dsi_device *dsi)
++{
++	/* PHY_STATUS[6:1] == 6'h00 */
++	if (mipi_dsih_read_part(dsi, R_DSI_HOST_PHY_STATUS, 1, 6) == 0x0) {
++		printk("MIPI D-PHY is already in ULPM state now\n");
++		return;
++	}
++	/* PHY_RSTZ[3:0] = 4'hF */
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_RSTZ, 0xF, 0, 4);
++	/* PHY_ULPS_CTRL[3:0] = 4'h0 */
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_ULPS_CTRL, 0x0, 0, 4);
++	/* PHY_TX_TRIGGERS[3:0] = 4'h0 */
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_TX_TRIGGERS, 0x0, 0, 4);
++	/* PHY_STATUS[6:4] == 3'h3 */
++	while (mipi_dsih_read_part(dsi, R_DSI_HOST_PHY_STATUS, 4, 3) != 0x3 ||
++		   mipi_dsih_read_part(dsi, R_DSI_HOST_PHY_STATUS, 0, 2) != 0x1)
++		;
++	/* PHY_ULPS_CTRL [3:0] = 4'h5 */
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_ULPS_CTRL, 0x5, 0, 4);
++	/* LPCLK_CTRL[1:0] = 2'h2 */
++	mipi_dsih_write_part(dsi, R_DSI_HOST_LPCLK_CTRL, 0x2, 0, 2);
++	/* PHY_STATUS[6:0] == 7'h1 */
++	while (mipi_dsih_read_part(dsi, R_DSI_HOST_PHY_STATUS, 0, 7) != 0x1)
++		;
++	/* PHY_RSTZ[3] = 1'b0 */
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_RSTZ, 0x0, 3, 1);
++	/* PHY_STATUS [0] == 1'b0 */
++	while(mipi_dsih_read_part(dsi, R_DSI_HOST_PHY_STATUS, 0, 1) != 0x0)
++		;
++	printk("%s ...\n", __func__);
++}
++
++void jz_dsih_dphy_ulpm_exit(struct dsi_device *dsi)
++{
++	/* PHY_STATUS[6:1] == 6'h00 */
++	if (mipi_dsih_read_part(dsi, R_DSI_HOST_PHY_STATUS, 1, 6) != 0x0) {
++		printk("MIPI D-PHY is not in ULPM state now\n");
++		return;
++	}
++	/* PHY_STATUS[0] == 1'b1 */
++	if (mipi_dsih_read_part(dsi, R_DSI_HOST_PHY_STATUS, 0, 1) == 0x1)
++		goto step5;
++
++	/* PHY_RSTZ [3] = 1'b1 */
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_RSTZ, 0x1, 3, 1);
++	/* PHY_STATUS[0] == 1'b1 */
++	while (mipi_dsih_read_part(dsi, R_DSI_HOST_PHY_STATUS, 0, 1) != 0x1)
++		;
++
++step5:
++	/* PHY_ULPS_CTRL[3:0] = 4'hF */
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_ULPS_CTRL, 0xF, 0, 4);
++	/* PHY_STATUS [5] == 1'b1 && PHY_STATUS [3] == 1'b1 */
++	while(mipi_dsih_read_part(dsi, R_DSI_HOST_PHY_STATUS, 5, 1) != 0x1 ||
++	      mipi_dsih_read_part(dsi, R_DSI_HOST_PHY_STATUS, 3, 1) != 0x1)
++		;
++	/* Wait for 1 ms */
++	mdelay(1);
++	/* PHY_ULPS_CTRL [3:0] = 4'h0 */
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_ULPS_CTRL, 0x0, 0, 4);
++	/* LPCLK_CTRL[1:0] = 2'h1 */
++	mipi_dsih_write_part(dsi, R_DSI_HOST_LPCLK_CTRL, 0x1, 0, 2);
++	/* PHY_STATUS [6:4] == 3'h3 && PHY_STATUS [1:0] == 2'h1 */
++	while (mipi_dsih_read_part(dsi, R_DSI_HOST_PHY_STATUS, 4, 3) != 0x3 ||
++           mipi_dsih_read_part(dsi, R_DSI_HOST_PHY_STATUS, 0, 2) != 0x1)
++		;
++	/* PHY_RSTZ [3] = 1'b0 */
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_RSTZ, 0x0, 3, 1);
++	printk("%s ...\n", __func__);
++}
++
++void jz_dsih_hal_power(struct dsi_device *dsi, int on)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PWR_UP, on, 0, 1);
++}
++
++int jz_dsi_init_config(struct dsi_device *dsi)
++{
++	struct dsi_config *dsi_config;
++	dsih_error_t err = OK;
++
++	dsi_config = dsi->dsi_config;
++
++	mipi_dsih_hal_dpi_color_mode_pol(dsi, !dsi_config->color_mode_polarity);
++	mipi_dsih_hal_dpi_shut_down_pol(dsi, !dsi_config->shut_down_polarity);
++
++	err = mipi_dsih_phy_hs2lp_config(dsi, dsi_config->max_hs_to_lp_cycles);
++	err |= mipi_dsih_phy_lp2hs_config(dsi, dsi_config->max_lp_to_hs_cycles);
++	err |= mipi_dsih_phy_bta_time(dsi, dsi_config->max_bta_cycles);
++	if (err) {
++		return err;
++	}
++
++	mipi_dsih_hal_dpi_lp_during_hfp(dsi, 1);
++	mipi_dsih_hal_dpi_lp_during_hbp(dsi, 1);
++
++	mipi_dsih_hal_dpi_lp_during_vactive(dsi, 1);
++	mipi_dsih_hal_dpi_lp_during_vfp(dsi, 1);
++	mipi_dsih_hal_dpi_lp_during_vbp(dsi, 1);
++	mipi_dsih_hal_dpi_lp_during_vsync(dsi, 1);
++	mipi_dsih_hal_dcs_wr_tx_type(dsi, 0, 1);
++	mipi_dsih_hal_dcs_wr_tx_type(dsi, 1, 1);
++	mipi_dsih_hal_dcs_wr_tx_type(dsi, 3, 1);	/* long packet */
++	mipi_dsih_hal_dcs_rd_tx_type(dsi, 0, 1);
++
++	mipi_dsih_hal_gen_wr_tx_type(dsi, 0, 1);
++	mipi_dsih_hal_gen_wr_tx_type(dsi, 1, 1);
++	mipi_dsih_hal_gen_wr_tx_type(dsi, 2, 1);
++	mipi_dsih_hal_gen_wr_tx_type(dsi, 3, 1);	/* long packet */
++	mipi_dsih_hal_gen_rd_tx_type(dsi, 0, 1);
++	mipi_dsih_hal_gen_rd_tx_type(dsi, 1, 1);
++	mipi_dsih_hal_gen_rd_tx_type(dsi, 2, 1);
++	mipi_dsih_hal_gen_rd_vc(dsi, 0);
++	mipi_dsih_hal_gen_eotp_rx_en(dsi, 0);
++	mipi_dsih_hal_gen_eotp_tx_en(dsi, 0);
++	mipi_dsih_hal_bta_en(dsi, 0);
++	mipi_dsih_hal_gen_ecc_rx_en(dsi, 0);
++	mipi_dsih_hal_gen_crc_rx_en(dsi, 0);
++	return OK;
++}
++
++dsih_error_t jz_init_dsi(struct dsi_device * dsi)
++{
++
++	dsih_error_t err = OK;
++	if (dsi->state == INITIALIZED) {
++		return ERR_DSI_INVALID_INSTANCE;
++	} else {
++		jz_dsih_hal_power(dsi, 0);
++		jz_dsih_hal_power(dsi, 1);
++		err = jz_dsi_init_config(dsi);
++		if (err) {
++			return err;
++		}
++		jz_dsih_hal_power(dsi, 0);
++		jz_dsih_hal_power(dsi, 1);
++
++	}
++
++	return err;
++}
++
++static irqreturn_t ingenicfb_irq_handler(int irq, void *data)
++{
++	unsigned int irq_flag;
++	struct dsi_device *dsi = (struct dsi_device *)data;
++
++	spin_lock(&dsi->irq_lock);
++
++	irq_flag = mipi_dsih_read_word(dsi, R_DSI_HOST_INT_ST1);
++
++	if(likely(irq_flag & (1 << 6))) {
++		printk("\033[31m(l:%d, f:%s, F: %s) %d %s\033[0m\n", __LINE__, __func__, __FILE__, 0, "");
++	}
++
++	spin_unlock(&dsi->irq_lock);
++	return IRQ_HANDLED;
++}
++
++void dsi_irq_test(struct dsi_device *dsi)
++{
++	mipi_dsih_write_word(dsi, R_DSI_HOST_INT_FORCE1, 1 << 6);
++}
++
++void jz_mipi_dsi_init_interrupt(struct dsi_device *dsi)
++{
++	/* fiexed */
++	struct device *dev = &dsi->dsim_lcd_dev->dev;
++
++	spin_lock_init(&dsi->irq_lock);
++
++	mipi_dsih_write_word(dsi, R_DSI_HOST_INT_MSK0, 0x3fffff);
++	mipi_dsih_write_word(dsi, R_DSI_HOST_INT_MSK1, 0xfff);
++
++	if (devm_request_irq(dev, 18, ingenicfb_irq_handler, 0,
++				"mipidsi", dsi)) {
++		dev_err(dev, "request dsi irq failed\n");
++	}
++}
++
++int jz_dsi_video_coding(struct dsi_device *dsi,
++			unsigned short *bytes_per_pixel_x100,
++			unsigned char *video_size_step,
++			unsigned short *video_size)
++{
++	struct video_config *video_config;
++	dsih_error_t err_code = OK;
++	video_config = dsi->video_config;
++
++	switch (video_config->color_coding) {
++	case COLOR_CODE_16BIT_CONFIG1:
++	case COLOR_CODE_16BIT_CONFIG2:
++	case COLOR_CODE_16BIT_CONFIG3:
++		*bytes_per_pixel_x100 = 200;
++		*video_size_step = 1;
++		break;
++	case COLOR_CODE_18BIT_CONFIG1:
++	case COLOR_CODE_18BIT_CONFIG2:
++		mipi_dsih_hal_dpi_18_loosely_packet_en(dsi,
++						       video_config->
++						       is_18_loosely);
++		*bytes_per_pixel_x100 = 225;
++		if (!video_config->is_18_loosely) {	// 18bits per pixel and NOT loosely, packets should be multiples of 4
++			*video_size_step = 4;
++			//round up active H pixels to a multiple of 4
++			for (; ((*video_size) % 4) != 0; (*video_size)++) {
++				;
++			}
++		} else {
++			*video_size_step = 1;
++		}
++		break;
++	case COLOR_CODE_24BIT:
++		*bytes_per_pixel_x100 = 300;	//burst mode
++		*video_size_step = 1;	//no burst mode
++		break;
++	default:
++		printk("invalid color coding\n");
++		err_code = ERR_DSI_COLOR_CODING;
++		break;
++	}
++	if (err_code == OK) {
++		pr_debug("video_config->color_coding:%d\n",
++		       video_config->color_coding);
++		err_code =
++		    mipi_dsih_hal_dpi_color_coding(dsi,
++						   video_config->color_coding);
++	}
++	if (err_code != OK) {
++		return err_code;
++	}
++	return 0;
++
++}
++
++void jz_dsi_dpi_cfg(struct dsi_device *dsi, unsigned int *ratio_clock_xPF,
++		    unsigned short *bytes_per_pixel_x100)
++{
++	struct video_config *video_config;
++	unsigned int hs_timeout = 0;
++	int counter = 0;
++
++	video_config = dsi->video_config;
++	mipi_dsih_hal_dpi_video_mode_type(dsi, video_config->video_mode);
++
++	/*HSA+HBP+HACT+HFP * 1 */
++	mipi_dsih_hal_dpi_hline(dsi,
++				(unsigned
++				 short)((video_config->h_total_pixels *
++					 (*ratio_clock_xPF)) /
++					PRECISION_FACTOR));
++	mipi_dsih_hal_dpi_hbp(dsi,
++			      ((video_config->h_back_porch_pixels *
++				(*ratio_clock_xPF)) / PRECISION_FACTOR));
++	mipi_dsih_hal_dpi_hsa(dsi,
++			      ((video_config->h_sync_pixels *
++				(*ratio_clock_xPF)) / PRECISION_FACTOR));
++	mipi_dsih_hal_dpi_vactive(dsi, video_config->v_active_lines);
++	mipi_dsih_hal_dpi_vfp(dsi,
++			      video_config->v_total_lines -
++			      (video_config->v_back_porch_lines +
++			       video_config->v_sync_lines +
++			       video_config->v_active_lines));
++	mipi_dsih_hal_dpi_vbp(dsi, video_config->v_back_porch_lines);
++	mipi_dsih_hal_dpi_vsync(dsi, video_config->v_sync_lines);
++
++#ifdef CONFIG_DSI_DPI_DEBUG
++	printk("hline:%d\n",
++	       (unsigned
++		short)((video_config->h_total_pixels * (*ratio_clock_xPF)) /
++		       PRECISION_FACTOR));
++	printk("hbp:%d\n",
++	       ((video_config->h_back_porch_pixels * (*ratio_clock_xPF)) /
++		PRECISION_FACTOR));
++	printk("hsa:%d\n",
++	       ((video_config->h_sync_pixels * (*ratio_clock_xPF)) /
++		PRECISION_FACTOR));
++	printk("vactive:%d\n", video_config->v_active_lines);
++	printk("vfp:%d\n",
++	       video_config->v_total_lines - (video_config->v_back_porch_lines +
++					      video_config->v_sync_lines +
++					      video_config->v_active_lines));
++	printk("vbp:%d\n", video_config->v_back_porch_lines);
++	printk("vsync:%d\n", video_config->v_sync_lines);
++#endif
++
++	mipi_dsih_hal_dpi_hsync_pol(dsi, !video_config->h_polarity);	//active low
++	mipi_dsih_hal_dpi_vsync_pol(dsi, !video_config->v_polarity);	//active low
++	mipi_dsih_hal_dpi_dataen_pol(dsi, !video_config->data_en_polarity);	// active high
++	// HS timeout timing
++	hs_timeout =
++	    ((video_config->h_total_pixels * video_config->v_active_lines) +
++	     (DSIH_PIXEL_TOLERANCE * (*bytes_per_pixel_x100)) / 100);
++	for (counter = 0x80; (counter < hs_timeout) && (counter > 2); counter--) {
++		if ((hs_timeout % counter) == 0) {
++			mipi_dsih_hal_timeout_clock_division(dsi, counter);
++			mipi_dsih_hal_lp_rx_timeout(dsi,
++						    (unsigned short)(hs_timeout
++								     /
++								     counter));
++			mipi_dsih_hal_hs_tx_timeout(dsi,
++						    (unsigned short)(hs_timeout
++								     /
++								     counter));
++			break;
++		}
++	}
++
++}
++
++void jz_dsih_hal_tx_escape_division(struct dsi_device *dsi,
++				    unsigned char tx_escape_division)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_CLKMGR_CFG, tx_escape_division, 0,
++			     8);
++}
++
++dsih_error_t jz_dsih_dphy_configure(struct dsi_device *dsi,
++				    unsigned char no_of_lanes,
++				    unsigned int output_freq)
++{
++	unsigned int loop_divider = 0;	/* (M) */
++	unsigned int input_divider = 1;	/* (N) */
++	unsigned char data[4];	/* maximum data for now are 4 bytes per test mode */
++	unsigned char no_of_bytes = 0;
++	unsigned char i = 0;	/* iterator */
++	unsigned char range = 0;	/* ranges iterator */
++	int flag = 0;
++	struct dsi_phy *phy;
++	phy = dsi->dsi_phy;
++	printk("entry function :%s\n", __func__);
++	if (phy == NULL) {
++		return ERR_DSI_INVALID_INSTANCE;
++	}
++	if (phy->status == NOT_INITIALIZED) {
++		return ERR_DSI_INVALID_INSTANCE;
++	}
++	if (output_freq < MIN_OUTPUT_FREQ) {
++		return ERR_DSI_PHY_FREQ_OUT_OF_BOUND;
++	}
++	/* find M and N dividers */
++	/* M :loop_divider, N: input_divider */
++	for (input_divider = 1 + (phy->reference_freq / DPHY_DIV_UPPER_LIMIT); ((phy->reference_freq / input_divider) >= DPHY_DIV_LOWER_LIMIT) && (!flag); input_divider++) {	/* here the >= DPHY_DIV_LOWER_LIMIT is a phy constraint, formula should be above 1 MHz */
++		if (((output_freq * input_divider) % (phy->reference_freq)) == 0) {	/*found the input_divider we want, but how can we be sure,
++											 * for example ,now output_freq is 90000 , that's 90MHZ.
++											 * if (90000 * input_divider) % fref == 0, and fref = 27000,
++											 * then input_divider = 3;
++											 * then loop_divider = 90000 * 3 / 27000 = 10;
++											 * if input_divider = 6, then loop_divider is 20; flag = 1 exit loop.
++											 */
++			/* values found */
++			loop_divider =
++			    ((output_freq * input_divider) /
++			     (phy->reference_freq));
++			if (loop_divider >= 12) {
++				flag = 1;
++			}
++		}
++	}
++
++	if ((!flag)
++	    || ((phy->reference_freq / input_divider) < DPHY_DIV_LOWER_LIMIT)) {
++		/* no exact value found in previous for loop */
++		/* this solution is not favourable as jitter would be maximum */
++		loop_divider = output_freq / DPHY_DIV_LOWER_LIMIT;
++		input_divider = phy->reference_freq / DPHY_DIV_LOWER_LIMIT;
++		//make sure M is not overflowed,M mask 9 bits
++		if(loop_divider > 511){
++			loop_divider = output_freq / (DPHY_DIV_LOWER_LIMIT * 2);
++			input_divider = phy->reference_freq / (DPHY_DIV_LOWER_LIMIT * 2);
++		}
++	} else {		/* variable was incremented before exiting the loop */
++		/*
++		 * input_divider is 6 now,
++		 * */
++		input_divider--;
++		/* now is 5.
++		 * loop_divider is still 20.
++		 * */
++	}
++	for (i = 0; (i < (sizeof(loop_bandwidth) / sizeof(loop_bandwidth[0])))
++	     && (loop_divider > loop_bandwidth[i].loop_div); i++) {
++		;
++	}
++	/* i = 0;
++	 * */
++	if (i >= (sizeof(loop_bandwidth) / sizeof(loop_bandwidth[0]))) {
++		return ERR_DSI_PHY_FREQ_OUT_OF_BOUND;
++	}
++	/* get the PHY in power down mode (shutdownz=0) and reset it (rstz=0) to
++	   avoid transient periods in PHY operation during re-configuration procedures. */
++	jz_dsih_dphy_reset(dsi, 0);
++	jz_dsih_dphy_clock_en(dsi, 0);
++	jz_dsih_dphy_shutdown(dsi, 0);
++	/* provide an initial active-high test clear pulse in TESTCLR  */
++	//performs vendor-specific interface initialization
++	mipi_dsih_dphy_test_clear(dsi, 1);
++	mipi_dsih_dphy_test_clear(dsi, 0);
++	/* find ranges */
++	for (range = 0; (range < (sizeof(ranges) / sizeof(ranges[0])))
++	     && ((output_freq / 1000) > ranges[range].freq); range++) {
++		;
++	}
++	if (range >= (sizeof(ranges) / sizeof(ranges[0]))) {
++		return ERR_DSI_PHY_FREQ_OUT_OF_BOUND;
++	}
++	/* set up board depending on environment if any */
++	if (phy->bsp_pre_config != 0) {
++		/*set master-phy output direction */
++		phy->bsp_pre_config(dsi, 0);
++	}
++	/* setup digital part */
++	/* hs frequency range [7]|[6:1]|[0] */
++	data[0] = (0 << 7) | (ranges[range].hs_freq << 1) | 0;
++	mipi_dsih_dphy_write(dsi, 0x44, data, 1);
++	/* setup PLL */
++	/* vco range  [7]|[6:3]|[2:1]|[0] */
++	data[0] = (1 << 7) | (ranges[range].vco_range << 3) | (0 << 1) | 0;
++	mipi_dsih_dphy_write(dsi, 0x10, data, 1);
++	/* PLL  reserved|Input divider control|Loop Divider Control|Post Divider Ratio [7:6]|[5]|[4]|[3:0] */
++	data[0] = (0x00 << 6) | (0x01 << 5) | (0x01 << 4) | (0x03 << 0);	/* post divider default = 0x03 - it is only used for clock out 2 */
++
++	/* PLL post divider ratio and PLL input and divider ratios control */
++	mipi_dsih_dphy_write(dsi, 0x19, data, 1);
++	/* PLL Lock bypass|charge pump current [7:4]|[3:0] */
++	data[0] = (0x00 << 4) | (loop_bandwidth[i].cp_current << 0);
++
++	/* PLL CP control , PLL lock bypass for initialization and for ULP mode */
++	mipi_dsih_dphy_write(dsi, 0x11, data, 1);
++	/* bypass CP default|bypass LPF default| LPF resistor [7]|[6]|[5:0] */
++	data[0] =
++	    (0x01 << 7) | (0x01 << 6) | (loop_bandwidth[i].lpf_resistor << 0);
++	mipi_dsih_dphy_write(dsi, 0x12, data, 1);
++	/* PLL input divider ratio [7:0] */
++	data[0] = input_divider - 1;
++
++	/*PLL input divider ratio */
++	mipi_dsih_dphy_write(dsi, 0x17, data, 1);
++	no_of_bytes = 2;	/* pll loop divider (code 0x18) takes only 2 bytes (10 bits in data) */
++	for (i = 0; i < no_of_bytes; i++) {
++		data[i] =
++		    ((unsigned char)((((loop_divider - 1) >> (5 * i)) & 0x1F) |
++				     (i << 7)));
++		/* 7 is dependent on no_of_bytes
++		   make sure 5 bits only of value are written at a time */
++	}
++	/* *******PLL loop divider ratio - SET no|reserved|feedback divider [7]|[6:5]|[4:0] */
++	mipi_dsih_dphy_write(dsi, 0x18, data, no_of_bytes);
++
++	/*now recover the phy state as it before */
++	jz_dsih_dphy_no_of_lanes(dsi, no_of_lanes);
++	jz_dsih_dphy_stop_wait_time(dsi, 0x1C);
++	jz_dsih_dphy_clock_en(dsi, 1);
++	jz_dsih_dphy_shutdown(dsi, 1);
++	jz_dsih_dphy_reset(dsi, 1);
++	pr_info("configure master-phy is ok\n");
++	return OK;
++}
++
++struct dphy_pll_range {
++	unsigned int start_clk_sel;
++	unsigned int output_freq0;	/*start freq in same resolution*/
++	unsigned int output_freq1;	/*end freq in same resolution*/
++	unsigned int resolution;
++};
++
++struct dphy_pll_range dphy_pll_table[] = {
++	{0,   63750000,  93125000,   312500},
++	{95,  93750000,  186250000,  625000},
++	{244, 187500000, 372500000,  1250000},
++	{393, 375000000, 745000000,  2500000},
++	{542, 750000000, 2750000000UL, 5000000},
++};
++
++dsih_error_t jz_dsih_dphy_configure_x2000(struct dsi_device *dsi,
++				    unsigned char no_of_lanes,
++				    unsigned int output_freq)
++{
++	int i;
++	struct dphy_pll_range *pll;
++	unsigned int pll_clk_sel = 0xffffffff;
++	for(i = 0; i < ARRAY_SIZE(dphy_pll_table); i++) {
++		pll = &dphy_pll_table[i];
++		if(output_freq >= pll->output_freq0 && output_freq <= pll->output_freq1) {
++			pll_clk_sel = pll->start_clk_sel + (output_freq - pll->output_freq0) / pll->resolution;
++			break;
++		}
++	}
++	if(pll_clk_sel == 0xffffffff) {
++		printk("can not find appropriate pll freq set for dsi phy! output_freq: %d\n", output_freq);
++		return ERR_DSI_PHY_FREQ_OUT_OF_BOUND;
++	}
++
++//	printk("before setting dsi phy: pll_clk_sel: %x\n", readl(dsi->phy_address + 0x64));
++	writel(pll_clk_sel, (unsigned int *)(dsi->phy_address + 0x64));	/* pll_clk_sel */
++//	printk("after setting dsi phy: pll_clk_sel: %x, output_freq: %d\n", readl(dsi->phy_address + 0x64), output_freq);
++
++	return OK;
++}
++
++static unsigned char calc_x2500_dphy_fbdiv(struct dsi_device* dsi)
++{
++	unsigned int real_mipi_clk = 0;
++	real_mipi_clk = dsi->real_mipiclk / 1000000;	//  hz --- Mhz
++	unsigned char fbdiv = 0;
++	unsigned int prediv = 1;	//Fix value
++	unsigned int ref = 12;		//12Mhz fix value
++
++	fbdiv = (real_mipi_clk * 2) / (12 / prediv);
++
++	pr_debug("%s   real_mipiclk = %d >>>>>>>>>>>>>>>>>>>>>>>>>>> \n",__func__,real_mipi_clk);
++	return (fbdiv < 70)?70 : fbdiv;
++}
++
++static void init_dsi_phy_x2500(struct dsi_device *dsi)
++{
++	unsigned int temp = 0xffffffff;
++
++	pr_debug("dsi phy address = 0x%x\n", dsi->phy_address);
++	//power on ,reset, set pin_enable_ck/0/1/* of lanes to be used to high level and others to low
++	pr_debug("%s,%d  step0 do nothing now.\n", __func__, __LINE__);
++
++	//step1
++	temp = *(volatile unsigned int*)(dsi->phy_address+0x0C);
++	temp &= ~0xff;
++	temp |= 0x01;	//prediv
++	writel(temp, (volatile unsigned int*)(dsi->phy_address+0x0C));
++	if ((*(volatile unsigned int*)(dsi->phy_address+0x0C) & 0xff) != 0x01) {
++		printk("%s,%d reg write error. Step1\n", __func__, __LINE__);
++	}
++	pr_debug("reg:0x03, value:0x%x\n", *(volatile unsigned int*)(dsi->phy_address+0x0C));
++	//step2
++	temp = *(volatile unsigned int*)(dsi->phy_address+0x10);
++	temp &= ~0xff;
++	temp |= calc_x2500_dphy_fbdiv(dsi);	//fbdiv
++	writel(temp, (volatile unsigned int*)(dsi->phy_address+0x10));
++	pr_debug("reg:0x04, value:0x%x\n", *(volatile unsigned int*)(dsi->phy_address+0x10));
++	msleep(20);
++	//step3
++	temp = *(volatile unsigned int*)(dsi->phy_address+0x04);
++	temp &= ~0xff;
++	temp |= 0xe4;		//PLL LDO
++	writel(temp, (volatile unsigned int*)(dsi->phy_address+0x04));
++	if ((*(volatile unsigned int*)(dsi->phy_address+0x04) & 0xff) != 0xe4) {
++		printk("%s,%d reg write error. Step3\n", __func__, __LINE__);
++	}
++	pr_debug("reg:0x01, value:0x%x\n", *(volatile unsigned int*)(dsi->phy_address+0x04));
++	//step4
++	if (dsi->video_config->no_of_lanes == 4) {
++		temp = *(volatile unsigned int*)(dsi->phy_address+0x00);
++		temp &= ~0xff;
++		temp |= 0x7d;     //4lane
++		writel(temp, (volatile unsigned int*)(dsi->phy_address+0x00));
++		if ((*(volatile unsigned int*)(dsi->phy_address+0x00) & 0xff) != 0x7d) {
++			printk("%s,%d reg write error. Step4\n", __func__, __LINE__);
++		}
++		/* printk("%s>>>>>>>>>>>>>>>>>>>>>>>> config as 4 lane \n",__func__); */
++	}
++	else if (dsi->video_config->no_of_lanes == 2){
++		temp = *(volatile unsigned int*)(dsi->phy_address+0x00);
++		temp &= ~0xff;
++		temp |= 0x4d;     //2lane
++		writel(temp, (volatile unsigned int*)(dsi->phy_address+0x00));
++		if ((*(volatile unsigned int*)(dsi->phy_address+0x00) & 0xff) != 0x4d) {
++			printk("%s,%d reg write error. Step4\n", __func__, __LINE__);
++		}
++	}
++	pr_debug("reg:0x00, value:0x%x\n", *(volatile unsigned int*)(dsi->phy_address+0x00));
++	//step5
++	temp = *(volatile unsigned int*)(dsi->phy_address+0x04);
++	temp &= ~0xff;
++	temp |= 0xe0;
++	writel(temp, (volatile unsigned int*)(dsi->phy_address+0x04));
++	if ((*(volatile unsigned int*)(dsi->phy_address+0x04) & 0xff) != 0xe0) {
++		printk("%s,%d reg write error. Step5\n", __func__, __LINE__);
++	}
++	pr_debug("reg:0x01, value:0x%x\n", *(volatile unsigned int*)(dsi->phy_address+0x04));
++
++	//step6
++	msleep(20);   //at lease 20ms, shortening need validation
++
++	//step7
++	temp = *(volatile unsigned int*)(dsi->phy_address+0x80);
++	temp &= ~0xff;
++	temp |= 0x1e;
++	writel(temp, (volatile unsigned int*)(dsi->phy_address+0x80));
++	if ((*(volatile unsigned int*)(dsi->phy_address+0x80) & 0xff) != 0x1e) {
++		printk("%s,%d reg write error. Step7\n", __func__, __LINE__);
++	}
++	pr_debug("reg:0x20, value:0x%x\n", *(volatile unsigned int*)(dsi->phy_address+0x80));
++	msleep(5);
++	//step8
++	temp = *(volatile unsigned int*)(dsi->phy_address+0x80);
++	temp &= ~0xff;
++	temp |= 0x1f;
++	writel(temp, (volatile unsigned int*)(dsi->phy_address+0x80));
++	if ((*(volatile unsigned int*)(dsi->phy_address+0x80) & 0xff) != 0x1f) {
++		printk("%s,%d reg write error. Step8\n", __func__, __LINE__);
++	}
++	pr_debug("reg:0x20, value:0x%x\n", *(volatile unsigned int*)(dsi->phy_address+0x80));
++	//step9
++	msleep(10);
++
++	pr_debug("%s,%d  dsi phy init over now...\n", __func__, __LINE__);
++}
++
++dsih_error_t jz_dsi_set_clock(struct dsi_device * dsi)
++{
++#if 0
++	dsih_error_t err = OK;
++	/* TODO: configure M31 phy PLL */
++	err =
++	    jz_dsih_dphy_configure(dsi, dsi->video_config->no_of_lanes,
++				   dsi->video_config->byte_clock * 8);
++	if (err) {
++		return err;	/* ERR_DSI_PHY_POWERUP; */
++	}
++#endif
++
++#ifndef CONFIG_SOC_X2500
++	jz_dsih_dphy_configure_x2000(dsi, dsi->video_config->no_of_lanes,
++				dsi->video_config->byte_clock * 1000 * 8);
++#else
++	init_dsi_phy_x2500(dsi);
++#endif
++	jz_dsih_dphy_stop_wait_time(dsi, 0x1C);
++	jz_dsih_dphy_clock_en(dsi, 1);
++	jz_dsih_dphy_shutdown(dsi, 1);
++	jz_dsih_dphy_reset(dsi, 1);
++	printk("configure master-phy is ok\n");
++	jz_dsih_hal_tx_escape_division(dsi, TX_ESC_CLK_DIV);
++	return OK;
++}
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsi_lowlevel.h b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsi_lowlevel.h
+new file mode 100644
+index 000000000..93f70091d
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsi_lowlevel.h
+@@ -0,0 +1,29 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++#ifndef _JZ_MIPI_DSI_LOWLEVEL_H
++#define _JZ_MIPI_DSI_LOWLEVEL_H
++
++
++void jz_dsih_dphy_reset(struct dsi_device *dsi, int reset);
++
++void jz_dsih_dphy_stop_wait_time(struct dsi_device *dsi, unsigned char no_of_byte_cycles);
++
++void jz_dsih_dphy_no_of_lanes(struct dsi_device * dsi, unsigned char no_of_lanes);
++void jz_dsih_dphy_clock_en(struct dsi_device *dsi, int en);
++void jz_dsih_dphy_shutdown(struct dsi_device *dsi, int powerup);
++void jz_dsih_hal_power(struct dsi_device *dsi, int on);
++int jz_dsi_init_config(struct dsi_device *dsi);
++int jz_init_dsi(struct dsi_device *dsi);
++int jz_dsi_set_clock(struct dsi_device *dsi);
++void jz_mipi_dsi_init_interrupt(struct dsi_device *dsi);
++int jz_dsi_video_coding(struct dsi_device *dsi, unsigned short *bytes_per_pixel_x100, unsigned char *video_size_step, unsigned short *video_size);
++void jz_dsi_dpi_cfg(struct dsi_device *dsi, unsigned int *ratio_clock_xPF, unsigned short *bytes_per_pixel_x100);
++void jz_dsih_hal_tx_escape_division(struct dsi_device * dsi, unsigned char tx_escape_division);
++dsih_error_t jz_dsih_dphy_configure(struct dsi_device *dsi, unsigned char no_of_lanes, unsigned int output_freq);
++void jz_dsih_dphy_ulpm_enter(struct dsi_device *dsi);
++void jz_dsih_dphy_ulpm_exit(struct dsi_device *dsi);
++#endif /* _JZ_MIPI_DSI_LOWLEVEL_H */
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsi_regs.h b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsi_regs.h
+new file mode 100644
+index 000000000..bf7b22cd7
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsi_regs.h
+@@ -0,0 +1,79 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++#ifndef _JZ_MIPI_DSI_REGS_H
++#define _JZ_MIPI_DSI_REGS_H
++
++#define R_DSI_HOST_VERSION                0x000
++#define R_DSI_HOST_PWR_UP                 0x004
++#define R_DSI_HOST_CLKMGR_CFG             0x008
++#define R_DSI_HOST_DPI_VCID               0x00c
++#define R_DSI_HOST_DPI_COLOR_CODING       0x010
++#define R_DSI_HOST_DPI_CFG_POL            0x014
++#define R_DSI_HOST_DPI_LP_CMD_TIM         0x018
++#define R_DSI_HOST_DBI_VCID               0x01c
++#define R_DSI_HOST_DBI_CFG                0x020
++#define R_DSI_HOST_DBI_PARTITIONING_EN    0x024
++#define R_DSI_HOST_DBI_CMDSIZE            0x028
++#define R_DSI_HOST_PCKHDL_CFG             0x02c
++#define R_DSI_HOST_GEN_VCID               0x030
++#define R_DSI_HOST_MODE_CFG               0x034
++#define R_DSI_HOST_VID_MODE_CFG           0x038
++#define R_DSI_HOST_VID_PKT_SIZE           0x03c
++#define R_DSI_HOST_VID_NUM_CHUNKS         0x040
++#define R_DSI_HOST_VID_NULL_SIZE          0x044
++#define R_DSI_HOST_VID_HSA_TIME           0x048
++#define R_DSI_HOST_VID_HBP_TIME           0x04c
++#define R_DSI_HOST_VID_HLINE_TIME         0x050
++#define R_DSI_HOST_VID_VSA_LINES          0x054
++#define R_DSI_HOST_VID_VBP_LINES          0x058
++#define R_DSI_HOST_VID_VFP_LINES          0x05c
++#define R_DSI_HOST_VID_VACTIVE_LINES      0x060
++#define R_DSI_HOST_EDPI_CMD_SIZE          0x064
++#define R_DSI_HOST_CMD_MODE_CFG           0x068
++#define R_DSI_HOST_GEN_HDR                0x06c
++#define R_DSI_HOST_GEN_PLD_DATA           0x070
++#define R_DSI_HOST_CMD_PKT_STATUS         0x074
++#define R_DSI_HOST_TO_CNT_CFG             0x078
++#define R_DSI_HOST_HS_RD_TO_CNT           0x07c
++#define R_DSI_HOST_LP_RD_TO_CNT           0x080
++#define R_DSI_HOST_HS_WR_TO_CNT           0x084
++#define R_DSI_HOST_LP_WR_TO_CNT           0x088
++#define R_DSI_HOST_BTA_TO_CNT             0x08c
++#define R_DSI_HOST_SDF_3D                 0x090
++#define R_DSI_HOST_LPCLK_CTRL             0x094
++#define R_DSI_HOST_PHY_TMR_LPCLK_CFG      0x098
++#define R_DSI_HOST_PHY_TMR_CFG            0x09c
++#define R_DSI_HOST_PHY_RSTZ               0x0a0
++#define R_DSI_HOST_PHY_IF_CFG             0x0a4
++#define R_DSI_HOST_PHY_ULPS_CTRL          0x0a8
++#define R_DSI_HOST_PHY_TX_TRIGGERS        0x0ac
++#define R_DSI_HOST_PHY_STATUS             0x0b0
++#define R_DSI_HOST_PHY_TST_CTRL0          0x0b4
++#define R_DSI_HOST_PHY_TST_CTRL1          0x0b8
++#define R_DSI_HOST_INT_ST0                0x0bC
++#define R_DSI_HOST_INT_ST1                0x0C0
++#define R_DSI_HOST_INT_MSK0               0x0C4
++#define R_DSI_HOST_INT_MSK1               0x0C8
++#define R_DSI_HOST_INT_FORCE0             0x0D8
++#define R_DSI_HOST_INT_FORCE1             0x0DC
++#define R_DSI_HOST_VID_SHADOW_CTRL        0x100
++#define R_DSI_HOST_DPI_VCID_ACT           0x10C
++#define R_DSI_HOST_DPI_COLOR_CODING_ACT   0x110
++#define R_DSI_HOST_DPI_LP_CMD_TIM_ACT     0x118
++#define R_DSI_HOST_VID_MODE_CFG_ACT       0x138
++#define R_DSI_HOST_VID_PKT_SIZE_ACT       0x13C
++#define R_DSI_HOST_VID_NUM_CHUNKS_ACT     0x140
++#define R_DSI_HOST_VID_NULL_SIZE_ACT      0x144
++#define R_DSI_HOST_VID_HSA_TIME_ACT       0x148
++#define R_DSI_HOST_VID_HBP_TIME_ACT       0x14C
++#define R_DSI_HOST_VID_HLINE_TIME_ACT     0x150
++#define R_DSI_HOST_VID_VSA_LINES_ACT      0x154
++#define R_DSI_HOST_VID_VBP_LINES_ACT      0x158
++#define R_DSI_HOST_VID_VFP_LINES_ACT      0x15C
++#define R_DSI_HOST_VID_VACTIVE_LINES_ACT  0x160
++#define R_DSI_HOST_SDF_3D_ACT             0x190
++#endif /* _JZ_MIPI_DSI_REGS_H */
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsih_hal.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsih_hal.c
+new file mode 100644
+index 000000000..5ba977b54
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsih_hal.c
+@@ -0,0 +1,1302 @@
++/*
++ * Ingenic SoC MIPI-DSI hal driver.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of thVe GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++#include "jz_mipi_dsih_hal.h"
++#include "jz_mipi_dsi_regs.h"
++#include <linux/delay.h>
++/**
++ * Write a 32-bit word to the DSI Host core
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param reg_address register offset in core
++ * @param data 32-bit word to be written to register
++ */
++void mipi_dsih_write_word(struct dsi_device * dsi, unsigned int reg_address, unsigned int data)
++{
++	writel(data, (volatile unsigned int *)(dsi->address + reg_address));
++}
++/**
++ * Write a bit field o a 32-bit word to the DSI Host core
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param reg_address register offset in core
++ * @param data to be written to register
++ * @param shift bit shift from the left (system is BIG ENDIAN)
++ * @param width of bit field
++ */
++void mipi_dsih_write_part(struct dsi_device * dsi, unsigned int reg_address, unsigned int data, unsigned char shift, unsigned char width)
++{
++	unsigned int mask = (1 << width) - 1;
++	unsigned int temp = mipi_dsih_read_word(dsi, reg_address);
++
++	temp &= ~(mask << shift);
++	temp |= (data & mask) << shift;
++	mipi_dsih_write_word(dsi, reg_address, temp);
++}
++/**
++ * Write a 32-bit word to the DSI Host core
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param reg_address offset of register
++ * @return 32-bit word value stored in register
++ */
++unsigned int mipi_dsih_read_word(struct dsi_device * dsi, unsigned int reg_address)
++{
++	return readl((volatile unsigned int *)(dsi->address + reg_address));
++}
++/**
++ * Write a 32-bit word to the DSI Host core
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param reg_address offset of register in core
++ * @param shift bit shift from the left (system is BIG ENDIAN)
++ * @param width of bit field
++ * @return bit field read from register
++ */
++unsigned int mipi_dsih_read_part(struct dsi_device * dsi, unsigned int reg_address, unsigned char shift, unsigned char width)
++{
++	return (mipi_dsih_read_word(dsi, reg_address) >> shift) & ((1 << width) - 1);
++}
++/**
++ * Get DSI Host core version
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @return ascii number of the version
++ */
++unsigned int mipi_dsih_hal_get_version(struct dsi_device * dsi)
++{
++	return mipi_dsih_read_word(dsi, R_DSI_HOST_VERSION);
++}
++/**
++ * Modify power status of DSI Host core
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param on (1) or off (0)
++ */
++void mipi_dsih_hal_power(struct dsi_device * dsi, int on)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PWR_UP, on, 0, 1);
++}
++/**
++ * Get the power status of the DSI Host core
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @return power status
++ */
++int mipi_dsih_hal_get_power(struct dsi_device * dsi)
++{
++	return (int)(mipi_dsih_read_word(dsi, R_DSI_HOST_PWR_UP));
++}
++/**
++ * Write transmission escape timeout
++ * a safe guard so that the state machine would reset if transmission
++ * takes too long
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param tx_escape_division
++ */
++void mipi_dsih_hal_tx_escape_division(struct dsi_device * dsi, unsigned char tx_escape_division)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_CLKMGR_CFG, tx_escape_division, 0, 8);
++}
++/**
++ * Write the DPI video virtual channel destination
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param vc virtual channel
++ */
++void mipi_dsih_hal_dpi_video_vc(struct dsi_device * dsi, unsigned char vc)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_DPI_VCID, (unsigned int)(vc), 0, 2);
++}
++/**
++ * Get the DPI video virtual channel destination
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @return virtual channel
++ */
++unsigned char mipi_dsih_hal_dpi_get_video_vc(struct dsi_device * dsi)
++{
++	return mipi_dsih_read_part(dsi, R_DSI_HOST_DPI_VCID, 0, 2);
++}
++/**
++ * Set DPI video color coding
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param color_coding enum (configuration and color depth)
++ * @return error code
++ */
++dsih_error_t mipi_dsih_hal_dpi_color_coding(struct dsi_device * dsi, dsih_color_coding_t color_coding)
++{
++	dsih_error_t err = OK;
++	if (color_coding > 7)
++	{
++		{
++			printk("invalid colour configuration");
++		}
++		err = ERR_DSI_COLOR_CODING;
++	}
++	else
++	{
++		mipi_dsih_write_part(dsi, R_DSI_HOST_DPI_COLOR_CODING, color_coding, 0, 4);
++	}
++	return err;
++}
++/**
++ * Get DPI video color coding
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @return color coding enum (configuration and color depth)
++ */
++dsih_color_coding_t mipi_dsih_hal_dpi_get_color_coding(struct dsi_device * dsi)
++{
++	return (dsih_color_coding_t)(mipi_dsih_read_part(dsi, R_DSI_HOST_DPI_COLOR_CODING, 0, 4));
++}
++/**
++ * Get DPI video color depth
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @return number of bits per pixel
++ */
++unsigned char mipi_dsih_hal_dpi_get_color_depth(struct dsi_device * dsi)
++{
++	unsigned char color_depth = 0;
++	switch (mipi_dsih_read_part(dsi, R_DSI_HOST_DPI_COLOR_CODING, 0, 4))
++	{
++		case 0:
++		case 1:
++		case 2:
++			color_depth = 16;
++			break;
++		case 3:
++		case 4:
++			color_depth = 18;
++			break;
++		case 5:
++			color_depth = 24;
++			break;
++		default:
++			printk("###############please make sure your configure!!!################3\n");
++			break;
++	}
++	return color_depth;
++}
++/**
++ * Get DPI video pixel configuration
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @return pixel configuration
++ */
++unsigned char mipi_dsih_hal_dpi_get_color_config(struct dsi_device * dsi)
++{
++	unsigned char color_config = 0;
++	switch (mipi_dsih_read_part(dsi, R_DSI_HOST_DPI_COLOR_CODING, 0, 4))
++	{
++		case 0:
++			color_config = 1;
++		case 1:
++			color_config = 2;
++			break;
++		case 2:
++			color_config = 3;
++			break;
++		case 3:
++			color_config = 1;
++			break;
++		case 4:
++			color_config = 2;
++			break;
++		case 5:
++			color_config = 0;
++			break;
++		default:
++			printk("@@@@@@@@@@@@please make sure your configure!!!@@@@@@@@@@@@\n");
++			break;
++	}
++	return color_config;
++}
++/**
++ * Set DPI loosely packetisation video (used only when color depth = 18
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable
++ */
++void mipi_dsih_hal_dpi_18_loosely_packet_en(struct dsi_device * dsi, int enable)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_DPI_COLOR_CODING, enable, 8, 1);
++}
++/**
++ * Set DPI color mode pin polarity
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param active_low (1) or active high (0)
++ */
++void mipi_dsih_hal_dpi_color_mode_pol(struct dsi_device * dsi, int active_low)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_DPI_CFG_POL, active_low, 4, 1);
++}
++/**
++ * Set DPI shut down pin polarity
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param active_low (1) or active high (0)
++ */
++void mipi_dsih_hal_dpi_shut_down_pol(struct dsi_device * dsi, int active_low)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_DPI_CFG_POL, active_low, 3, 1);
++}
++/**
++ * Set DPI horizontal sync pin polarity
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param active_low (1) or active high (0)
++ */
++void mipi_dsih_hal_dpi_hsync_pol(struct dsi_device * dsi, int active_low)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_DPI_CFG_POL, active_low, 2, 1);
++}
++/**
++ * Set DPI vertical sync pin polarity
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param active_low (1) or active high (0)
++ */
++void mipi_dsih_hal_dpi_vsync_pol(struct dsi_device * dsi, int active_low)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_DPI_CFG_POL, active_low, 1, 1);
++}
++/**
++ * Set DPI data enable pin polarity
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param active_low (1) or active high (0)
++ */
++void mipi_dsih_hal_dpi_dataen_pol(struct dsi_device * dsi, int active_low)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_DPI_CFG_POL, active_low, 0, 1);
++}
++/**
++ * Enable FRAME BTA ACK
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable (1) - disable (0)
++ */
++void mipi_dsih_hal_dpi_frame_ack_en(struct dsi_device * dsi, int enable)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_VID_MODE_CFG, enable, 14, 1);
++}
++/**
++ * Enable null packets (value in null packet size will be taken in calculations)
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable (1) - disable (0)
++ */
++//void mipi_dsih_hal_dpi_null_packet_en(struct dsi_device * dsi, int enable)
++//{
++//	mipi_dsih_write_part(dsi, R_DSI_HOST_VID_MODE_CFG, enable, 10, 1);
++//}
++/**
++ * Enable multi packets (value in no of chunks will be taken in calculations)
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable (1) - disable (0)
++ */
++//void mipi_dsih_hal_dpi_multi_packet_en(struct dsi_device * dsi, int enable)
++//{
++//	mipi_dsih_write_part(dsi, R_DSI_HOST_VID_MODE_CFG, enable, 9, 1);
++//}
++/**
++ * Enable return to low power mode inside horizontal front porch periods when
++ *  timing allows
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable (1) - disable (0)
++ */
++void mipi_dsih_hal_dpi_lp_during_hfp(struct dsi_device * dsi, int enable)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_VID_MODE_CFG, enable, 13, 1);
++}
++/**
++ * Enable return to low power mode inside horizontal back porch periods when
++ *  timing allows
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable (1) - disable (0)
++ */
++void mipi_dsih_hal_dpi_lp_during_hbp(struct dsi_device * dsi, int enable)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_VID_MODE_CFG, enable, 12, 1);
++}
++/**
++ * Enable return to low power mode inside vertical active lines periods when
++ *  timing allows
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable (1) - disable (0)
++ */
++void mipi_dsih_hal_dpi_lp_during_vactive(struct dsi_device * dsi, int enable)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_VID_MODE_CFG, enable, 11, 1);
++}
++/**
++ * Enable return to low power mode inside vertical front porch periods when
++ *  timing allows
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable (1) - disable (0)
++ */
++void mipi_dsih_hal_dpi_lp_during_vfp(struct dsi_device * dsi, int enable)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_VID_MODE_CFG, enable, 10, 1);
++}
++/**
++ * Enable return to low power mode inside vertical back porch periods when
++ * timing allows
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable (1) - disable (0)
++ */
++void mipi_dsih_hal_dpi_lp_during_vbp(struct dsi_device * dsi, int enable)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_VID_MODE_CFG, enable, 9, 1);
++}
++/**
++ * Enable return to low power mode inside vertical sync periods when
++ *  timing allows
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable (1) - disable (0)
++ */
++void mipi_dsih_hal_dpi_lp_during_vsync(struct dsi_device * dsi, int enable)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_VID_MODE_CFG, enable, 8, 1);
++}
++/**
++ * Set DPI video mode type (burst/non-burst - with sync pulses or events)
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param type
++ * @return error code
++ */
++dsih_error_t mipi_dsih_hal_dpi_video_mode_type(struct dsi_device * dsi, dsih_video_mode_t type)
++{
++	if (type < 3)
++	{
++		mipi_dsih_write_part(dsi, R_DSI_HOST_VID_MODE_CFG, type, 0, 2);
++		return OK;
++	}
++	else
++	{
++		{
++			printk("undefined type");
++		}
++		return ERR_DSI_OUT_OF_BOUND;
++	}
++}
++/**
++ * Write the null packet size - will only be taken into account when null
++ * packets are enabled.
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param size of null packet
++ * @return error code
++ */
++dsih_error_t mipi_dsih_hal_dpi_null_packet_size(struct dsi_device * dsi, unsigned short size)
++{
++	if (size < 0x3ff) /* 10-bit field */
++	{
++		mipi_dsih_write_part(dsi, R_DSI_HOST_VID_NULL_SIZE, size, 0, 13);
++		return OK;
++	}
++	else
++	{
++		return ERR_DSI_OUT_OF_BOUND;
++	}
++}
++/**
++ * Write no of chunks to core - taken into consideration only when multi packet
++ * is enabled
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param no of chunks
++ */
++dsih_error_t mipi_dsih_hal_dpi_chunks_no(struct dsi_device * dsi, unsigned short no)
++{
++	if (no < 0x3ff)
++	{
++		mipi_dsih_write_part(dsi, R_DSI_HOST_VID_NUM_CHUNKS, no, 0, 13);
++		return OK;
++	}
++	else
++	{
++		return ERR_DSI_OUT_OF_BOUND;
++	}
++}
++/**
++ * Write video packet size. obligatory for sending video
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param size of video packet - containing information
++ * @return error code
++ */
++dsih_error_t mipi_dsih_hal_dpi_video_packet_size(struct dsi_device * dsi, unsigned short size)
++{
++	if (size < 0x7ff) /* 11-bit field */
++	{
++		mipi_dsih_write_part(dsi, R_DSI_HOST_VID_PKT_SIZE, size, 0, 14);
++		return OK;
++	}
++	else
++	{
++		return ERR_DSI_OUT_OF_BOUND;
++	}
++}
++/**
++ * Enable tear effect acknowledge
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable (1) - disable (0)
++ */
++void mipi_dsih_hal_tear_effect_ack_en(struct dsi_device * dsi, int enable)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_CMD_MODE_CFG, enable, 0, 1);
++}
++/**
++ * Enable packets acknowledge request after each packet transmission
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable (1) - disable (0)
++ */
++void mipi_dsih_hal_cmd_ack_en(struct dsi_device * dsi, int enable)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_CMD_MODE_CFG, enable, 1, 1);
++}
++/**
++ * Set DCS command packet transmission to transmission type
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param no_of_param of command
++ * @param lp transmit in low power
++ * @return error code
++ */
++dsih_error_t mipi_dsih_hal_dcs_wr_tx_type(struct dsi_device * dsi, unsigned no_of_param, int lp)
++{
++	switch (no_of_param)
++	{
++		case 0:
++			mipi_dsih_write_part(dsi, R_DSI_HOST_CMD_MODE_CFG, lp, 16, 1);
++			break;
++		case 1:
++			mipi_dsih_write_part(dsi, R_DSI_HOST_CMD_MODE_CFG, lp, 17, 1);
++			break;
++		default:
++			mipi_dsih_write_part(dsi, R_DSI_HOST_CMD_MODE_CFG, lp, 19, 1);
++			break;
++	}
++	return OK;
++}
++/**
++ * Set DCS read command packet transmission to transmission type
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param no_of_param of command
++ * @param lp transmit in low power
++ * @return error code
++ */
++dsih_error_t mipi_dsih_hal_dcs_rd_tx_type(struct dsi_device * dsi, unsigned no_of_param, int lp)
++{
++	dsih_error_t err = OK;
++	switch (no_of_param)
++	{
++		case 0:
++			mipi_dsih_write_part(dsi, R_DSI_HOST_CMD_MODE_CFG, lp, 18, 1);
++			break;
++		default:
++			printk("undefined DCS Read packet type");
++			err = ERR_DSI_OUT_OF_BOUND;
++			break;
++	}
++	return err;
++}
++/**
++ * Set generic write command packet transmission to transmission type
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param no_of_param of command
++ * @param lp transmit in low power
++ * @return error code
++ */
++dsih_error_t mipi_dsih_hal_gen_wr_tx_type(struct dsi_device * dsi, unsigned no_of_param, int lp)
++{
++	switch (no_of_param)
++	{
++		case 0:
++			mipi_dsih_write_part(dsi, R_DSI_HOST_CMD_MODE_CFG, lp, 8, 1);
++			break;
++		case 1:
++			mipi_dsih_write_part(dsi, R_DSI_HOST_CMD_MODE_CFG, lp, 9, 1);
++			break;
++		case 2:
++			mipi_dsih_write_part(dsi, R_DSI_HOST_CMD_MODE_CFG, lp, 10, 1);
++			break;
++		default:
++			mipi_dsih_write_part(dsi, R_DSI_HOST_CMD_MODE_CFG, lp, 14, 1);
++			break;
++	}
++	return OK;
++}
++/**
++ * Set generic command packet transmission to transmission type
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param no_of_param of command
++ * @param lp transmit in low power
++ * @return error code
++ */
++dsih_error_t mipi_dsih_hal_gen_rd_tx_type(struct dsi_device * dsi, unsigned no_of_param, int lp)
++{
++	dsih_error_t err = OK;
++	switch (no_of_param)
++	{
++		case 0:
++			mipi_dsih_write_part(dsi, R_DSI_HOST_CMD_MODE_CFG, lp, 11, 1);
++			break;
++		case 1:
++			mipi_dsih_write_part(dsi, R_DSI_HOST_CMD_MODE_CFG, lp, 12, 1);
++			break;
++		case 2:
++			mipi_dsih_write_part(dsi, R_DSI_HOST_CMD_MODE_CFG, lp, 13, 1);
++			break;
++		default:
++			printk("undefined Generic Read packet type");
++			err = ERR_DSI_OUT_OF_BOUND;
++			break;
++	}
++	return err;
++}
++/**
++ * Configure maximum read packet size command transmission type
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param lp set to low power
++ */
++void mipi_dsih_hal_max_rd_size_tx_type(struct dsi_device * dsi, int lp)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_CMD_MODE_CFG, lp, 24, 1);
++}
++/**
++ * Enable command mode (Generic interface)
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable 1
++ */
++void mipi_dsih_hal_gen_set_mode(struct dsi_device * dsi, int enable)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_MODE_CFG, enable, 0, 1);
++}
++/**
++ * Retrieve the controller's status of whether command mode is ON or not
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @return whether command mode is ON
++ */
++int mipi_dsih_hal_gen_get_mode(struct dsi_device * dsi)
++{
++	return mipi_dsih_read_part(dsi, R_DSI_HOST_MODE_CFG, 0, 1);
++}
++/**
++ * Configure the Horizontal Line time
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param time taken to transmit the total of the horizontal line
++ */
++void mipi_dsih_hal_dpi_hline(struct dsi_device * dsi, unsigned short time)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_VID_HLINE_TIME, time, 0, 15);
++}
++/**
++ * Configure the Horizontal back porch time
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param time taken to transmit the horizontal back porch
++ */
++void mipi_dsih_hal_dpi_hbp(struct dsi_device * dsi, unsigned short time)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_VID_HBP_TIME, time, 0, 12);
++}
++/**
++ * Configure the Horizontal sync time
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param time taken to transmit the horizontal sync
++ */
++void mipi_dsih_hal_dpi_hsa(struct dsi_device * dsi, unsigned short time)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_VID_HSA_TIME, time, 0, 12);
++}
++/**
++ * Configure the vertical active lines of the video stream
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param lines
++ */
++void mipi_dsih_hal_dpi_vactive(struct dsi_device * dsi, unsigned short lines)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_VID_VACTIVE_LINES, lines, 0, 14);
++}
++/**
++ * Configure the vertical front porch lines of the video stream
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param lines
++ */
++void mipi_dsih_hal_dpi_vfp(struct dsi_device * dsi, unsigned short lines)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_VID_VFP_LINES, lines, 0, 10);
++}
++/**
++ * Configure the vertical back porch lines of the video stream
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param lines
++ */
++void mipi_dsih_hal_dpi_vbp(struct dsi_device * dsi, unsigned short lines)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_VID_VBP_LINES, lines, 0, 10);
++}
++/**
++ * Configure the vertical sync lines of the video stream
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param lines
++ */
++void mipi_dsih_hal_dpi_vsync(struct dsi_device * dsi, unsigned short lines)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_VID_VSA_LINES, lines, 0, 10);
++}
++/**
++ * configure timeout divisions (so they would have more clock ticks)
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param byte_clk_division_factor no of hs cycles before transiting back to LP in
++ *  (lane_clk / byte_clk_division_factor)
++ */
++void mipi_dsih_hal_timeout_clock_division(struct dsi_device * dsi, unsigned char byte_clk_division_factor)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_CLKMGR_CFG, byte_clk_division_factor, 8, 8);
++}
++/**
++ * Configure the Low power receive time out
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param count (of byte cycles)
++ */
++void mipi_dsih_hal_lp_rx_timeout(struct dsi_device * dsi, unsigned short count)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_TO_CNT_CFG, count, 0, 16);
++}
++/**
++ * Configure a high speed transmission time out7
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param count (byte cycles)
++ */
++void mipi_dsih_hal_hs_tx_timeout(struct dsi_device * dsi, unsigned short count)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_TO_CNT_CFG, count, 16, 16);
++}
++/**
++ * Get the error 0 interrupt register status
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param mask the mask to be read from the register
++ * @return error status 0 value
++ */
++unsigned int mipi_dsih_hal_error_status_0(struct dsi_device * dsi, unsigned int mask)
++{
++	return (mipi_dsih_read_word(dsi, R_DSI_HOST_INT_ST0) & mask);
++}
++/**
++ * Get the error 1 interrupt register status
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param mask the mask to be read from the register
++ * @return error status 1 value
++ */
++unsigned int mipi_dsih_hal_error_status_1(struct dsi_device * dsi, unsigned int mask)
++{
++	return (mipi_dsih_read_word(dsi, R_DSI_HOST_INT_ST1) & mask);
++}
++/**
++ * Configure MASK (hiding) of interrupts coming from error 0 source
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param mask to be written to the register
++ */
++void mipi_dsih_hal_error_mask_0(struct dsi_device * dsi, unsigned int mask)
++{
++	mipi_dsih_write_word(dsi, R_DSI_HOST_INT_MSK0, mask);
++}
++/**
++ * Get the ERROR MASK  0 register status
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param mask the bits to read from the mask register
++ */
++unsigned int mipi_dsih_hal_get_error_mask_0(struct dsi_device * dsi, unsigned int mask)
++{
++	return (mipi_dsih_read_word(dsi, R_DSI_HOST_INT_MSK0) & mask);
++}
++/**
++ * Configure MASK (hiding) of interrupts coming from error 0 source
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param mask the mask to be written to the register
++ */
++void mipi_dsih_hal_error_mask_1(struct dsi_device * dsi, unsigned int mask)
++{
++	mipi_dsih_write_word(dsi, R_DSI_HOST_INT_MSK1, mask);
++}
++/**
++ * Get the ERROR MASK  1 register status
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param mask the bits to read from the mask register
++ */
++unsigned int mipi_dsih_hal_get_error_mask_1(struct dsi_device * dsi, unsigned int mask)
++{
++	return (mipi_dsih_read_word(dsi, R_DSI_HOST_INT_MSK1) & mask);
++}
++/* DBI NOT IMPLEMENTED */
++void mipi_dsih_hal_dbi_out_color_coding(struct dsi_device * dsi, unsigned char color_depth, unsigned char option);
++void mipi_dsih_hal_dbi_in_color_coding(struct dsi_device * dsi, unsigned char color_depth, unsigned char option);
++void mipi_dsih_hal_dbi_lut_size(struct dsi_device * dsi, unsigned char size);
++void mipi_dsih_hal_dbi_partitioning_en(struct dsi_device * dsi, int enable);
++void mipi_dsih_hal_dbi_dcs_vc(struct dsi_device * dsi, unsigned char vc);
++void mipi_dsih_hal_dbi_max_cmd_size(struct dsi_device * dsi, unsigned short size);
++void mipi_dsih_hal_dbi_cmd_size(struct dsi_device * dsi, unsigned short size);
++void mipi_dsih_hal_dbi_max_cmd_size(struct dsi_device * dsi, unsigned short size);
++int mipi_dsih_hal_dbi_rd_cmd_busy(struct dsi_device * dsi);
++int mipi_dsih_hal_dbi_read_fifo_full(struct dsi_device * dsi);
++int mipi_dsih_hal_dbi_read_fifo_empty(struct dsi_device * dsi);
++int mipi_dsih_hal_dbi_write_fifo_full(struct dsi_device * dsi);
++int mipi_dsih_hal_dbi_write_fifo_empty(struct dsi_device * dsi);
++int mipi_dsih_hal_dbi_cmd_fifo_full(struct dsi_device * dsi);
++int mipi_dsih_hal_dbi_cmd_fifo_empty(struct dsi_device * dsi);
++
++/**
++ * Write command header in the generic interface
++ * (which also sends DCS commands) as a subset
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param vc of destination
++ * @param packet_type (or type of DCS command)
++ * @param ls_byte (if DCS, it is the DCS command)
++ * @param ms_byte (only parameter of short DCS packet)
++ * @return error code
++ */
++dsih_error_t mipi_dsih_hal_gen_packet_header(struct dsi_device * dsi, unsigned char vc, unsigned char packet_type, unsigned char ms_byte, unsigned char ls_byte)
++{
++	if (vc < 4)
++	{
++		mipi_dsih_write_part(dsi, R_DSI_HOST_GEN_HDR, (ms_byte <<  16) | (ls_byte << 8 ) | ((vc << 6) | packet_type), 0, 24);
++		return OK;
++	}
++	return  ERR_DSI_OVERFLOW;
++}
++/**
++ * Write the payload of the long packet commands
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param payload array of bytes of payload
++ * @return error code
++ */
++dsih_error_t mipi_dsih_hal_gen_packet_payload(struct dsi_device * dsi, unsigned int payload)
++{
++	if (mipi_dsih_hal_gen_write_fifo_full(dsi))
++	{
++		return ERR_DSI_OVERFLOW;
++	}
++	mipi_dsih_write_word(dsi, R_DSI_HOST_GEN_PLD_DATA, payload);
++	return OK;
++
++}
++/**
++ * Write the payload of the long packet commands
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param payload pointer to 32-bit array to hold read information
++ * @return error code
++ */
++dsih_error_t  mipi_dsih_hal_gen_read_payload(struct dsi_device * dsi, unsigned int* payload)
++{
++	*payload = mipi_dsih_read_word(dsi, R_DSI_HOST_GEN_PLD_DATA);
++	return OK;
++}
++
++/**
++ * Configure the read back virtual channel for the generic interface
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param vc to listen to on the line
++ */
++void mipi_dsih_hal_gen_rd_vc(struct dsi_device * dsi, unsigned char vc)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_GEN_VCID, vc, 0, 2);
++}
++/**
++ * Enable EOTp reception
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable
++ */
++void mipi_dsih_hal_gen_eotp_rx_en(struct dsi_device * dsi, int enable)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PCKHDL_CFG, enable, 1, 1);
++}
++/**
++ * Enable EOTp transmission
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable
++ */
++void mipi_dsih_hal_gen_eotp_tx_en(struct dsi_device * dsi, int enable)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PCKHDL_CFG, enable, 0, 1);
++}
++/**
++ * Enable Bus Turn-around request
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable
++ */
++void mipi_dsih_hal_bta_en(struct dsi_device * dsi, int enable)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PCKHDL_CFG, enable, 2, 1);
++}
++/**
++ * Enable ECC reception, error correction and reporting
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable
++ */
++void mipi_dsih_hal_gen_ecc_rx_en(struct dsi_device * dsi, int enable)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PCKHDL_CFG, enable, 3, 1);
++}
++/**
++ * Enable CRC reception, error reporting
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param enable
++ */
++void mipi_dsih_hal_gen_crc_rx_en(struct dsi_device * dsi, int enable)
++{
++	mipi_dsih_write_part(dsi, R_DSI_HOST_PCKHDL_CFG, enable, 4, 1);
++}
++/**
++ * Get status of read command
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @return 1 if busy
++ */
++int mipi_dsih_hal_gen_rd_cmd_busy(struct dsi_device * dsi)
++{
++	return mipi_dsih_read_part(dsi, R_DSI_HOST_CMD_PKT_STATUS, 6, 1);
++}
++/**
++ * Get the FULL status of generic read payload fifo
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @return 1 if fifo full
++ */
++int mipi_dsih_hal_gen_read_fifo_full(struct dsi_device * dsi)
++{
++	return mipi_dsih_read_part(dsi, R_DSI_HOST_CMD_PKT_STATUS, 5, 1);
++}
++/**
++ * Get the EMPTY status of generic read payload fifo
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @return 1 if fifo empty
++ */
++int mipi_dsih_hal_gen_read_fifo_empty(struct dsi_device * dsi)
++{
++	return mipi_dsih_read_part(dsi, R_DSI_HOST_CMD_PKT_STATUS, 4, 1);
++}
++/**
++ * Get the FULL status of generic write payload fifo
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @return 1 if fifo full
++ */
++int mipi_dsih_hal_gen_write_fifo_full(struct dsi_device * dsi)
++{
++	return mipi_dsih_read_part(dsi, R_DSI_HOST_CMD_PKT_STATUS, 3, 1);
++}
++/**
++ * Get the EMPTY status of generic write payload fifo
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @return 1 if fifo empty
++ */
++int mipi_dsih_hal_gen_write_fifo_empty(struct dsi_device * dsi)
++{
++	return mipi_dsih_read_part(dsi, R_DSI_HOST_CMD_PKT_STATUS, 2, 1);
++}
++/**
++ * Get the FULL status of generic command fifo
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @return 1 if fifo full
++ */
++int mipi_dsih_hal_gen_cmd_fifo_full(struct dsi_device * dsi)
++{
++	return mipi_dsih_read_part(dsi, R_DSI_HOST_CMD_PKT_STATUS, 1, 1);
++}
++/**
++ * Get the EMPTY status of generic command fifo
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @return 1 if fifo empty
++ */
++int mipi_dsih_hal_gen_cmd_fifo_empty(struct dsi_device * dsi)
++{
++	return mipi_dsih_read_part(dsi, R_DSI_HOST_CMD_PKT_STATUS, 0, 1);
++}
++/* only if DPI */
++/**
++ * Configure how many cycles of byte clock would the PHY module take
++ * to switch from high speed to low power
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param no_of_byte_cycles
++ * @return error code
++ */
++dsih_error_t mipi_dsih_phy_hs2lp_config(struct dsi_device * dsi, unsigned char no_of_byte_cycles)
++{
++	if (no_of_byte_cycles < 0x100) {
++		mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_TMR_CFG, no_of_byte_cycles, 24, 8);
++	}
++	else {
++		return ERR_DSI_OVERFLOW;
++	}
++	return OK;
++}
++/**
++ * Configure how many cycles of byte clock would the PHY module take
++ * to switch from to low power high speed
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param no_of_byte_cycles
++ * @return error code
++ */
++dsih_error_t mipi_dsih_phy_lp2hs_config(struct dsi_device * dsi, unsigned char no_of_byte_cycles)
++{
++	if (no_of_byte_cycles < 0x100) {
++		mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_TMR_CFG, no_of_byte_cycles, 16, 8);
++	}
++	else {
++		return ERR_DSI_OVERFLOW;
++	}
++	return OK;
++}
++/**
++ * Configure how many cycles of byte clock would the PHY module take
++ * to turn the bus around to start receiving
++ * @param dsi pointer to structure holding the DSI Host core information
++ * @param no_of_byte_cycles
++ * @return error code
++ */
++dsih_error_t mipi_dsih_phy_bta_time(struct dsi_device * dsi, unsigned short no_of_byte_cycles)
++{
++	if (no_of_byte_cycles < 0x8000) /* 12-bit field */
++	{
++		mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_TMR_CFG, no_of_byte_cycles, 0, 15);
++	}
++	else
++	{
++		return ERR_DSI_OVERFLOW;
++	}
++	return OK;
++}
++
++void mipi_dsih_dphy_test_clock(struct dsi_device * dsi, int value)
++{
++        mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_TST_CTRL0, value, 1, 1);
++}
++void mipi_dsih_dphy_test_clear(struct dsi_device * dsi, int value)
++{
++        mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_TST_CTRL0, value, 0, 1);
++}
++void mipi_dsih_dphy_test_en(struct dsi_device * dsi, unsigned char on_falling_edge)
++{
++        mipi_dsih_write_part(dsi, R_DSI_HOST_PHY_TST_CTRL1, on_falling_edge, 16, 1);
++}
++void mipi_dsih_dphy_test_data_in(struct dsi_device *dsi, unsigned char test_data)
++{
++        mipi_dsih_write_word(dsi, R_DSI_HOST_PHY_TST_CTRL1, test_data);
++}
++
++
++void mipi_dsih_dphy_write(struct dsi_device * dsi, unsigned char address, unsigned char * data, unsigned char data_length)
++{
++        unsigned i = 0;
++        if (data != 0)
++        {
++                /* set the TESTCLK input high in preparation to latch in the desired test mode */
++                mipi_dsih_dphy_test_clock(dsi, 1);
++                /* set the desired test code in the input 8-bit bus TESTDIN[7:0] */
++                mipi_dsih_dphy_test_data_in(dsi, address);
++                /* set TESTEN input high  */
++                mipi_dsih_dphy_test_en(dsi, 1);
++                /* drive the TESTCLK input low; the falling edge captures the chosen test code into the transceiver */
++                mipi_dsih_dphy_test_clock(dsi, 0);
++                /* set TESTEN input low to disable further test mode code latching  */
++                mipi_dsih_dphy_test_en(dsi, 0);
++                /* start writing MSB first */
++                for (i = data_length; i > 0; i--)
++                {       /* set TESTDIN[7:0] to the desired test data appropriate to the chosen test mode */
++                        mipi_dsih_dphy_test_data_in(dsi, data[i - 1]);
++                        /* pulse TESTCLK high to capture this test data into the macrocell; repeat these two steps as necessary */
++                        mipi_dsih_dphy_test_clock(dsi, 1);
++                        mipi_dsih_dphy_test_clock(dsi, 0);
++                }
++        }
++}
++void mipi_dsih_dphy_enable_hs_clk(struct dsi_device *dsi, int enable)
++{
++        mipi_dsih_write_part(dsi, R_DSI_HOST_LPCLK_CTRL, enable, 0, 1);
++}
++
++void mipi_dsih_dphy_auto_clklane_ctrl(struct dsi_device *dsi, int enable)
++{
++        mipi_dsih_write_part(dsi, R_DSI_HOST_LPCLK_CTRL, enable, 1, 1);
++}
++
++void mipi_dsih_cmd_mode(struct dsi_device * dsi, int en)
++{
++	if (dsi == NULL || dsi->state != INITIALIZED){
++		printk("dsi is NULL, or dsi state error\n");
++		return ;
++	}
++
++	if ((!mipi_dsih_hal_gen_get_mode(dsi)) && en)
++	{	/* disable video mode first */
++		mipi_dsih_hal_gen_set_mode(dsi, 1);
++	}
++	else if ((mipi_dsih_hal_gen_get_mode(dsi)) && !en)
++	{
++		mipi_dsih_hal_gen_set_mode(dsi, 0);
++	}
++	return;
++}
++
++unsigned short mipi_dsih_gen_rd_packet(struct dsi_device * dsi, unsigned char vc, unsigned char data_type, unsigned char msb_byte, unsigned char lsb_byte, unsigned char bytes_to_read, unsigned char* read_buffer)
++{
++	dsih_error_t err_code = OK;
++	int timeout = 0;
++	int counter = 0;
++	int i = 0;
++	int last_count = 0;
++	unsigned int temp[1] = {0};
++	if (dsi == 0)
++	{
++		return 0;
++	}
++	if (dsi->state != INITIALIZED)
++	{
++		return 0;
++	}
++	if (bytes_to_read < 1)
++	{
++		return 0;
++	}
++	if (read_buffer == 0)
++	{
++		return 0;
++	}
++	/* make sure command mode is on */
++	mipi_dsih_cmd_mode(dsi, 1);
++	/* make sure receiving is enabled */
++	mipi_dsih_hal_bta_en(dsi, 1);
++	/* listen to the same virtual channel as the one sent to */
++	mipi_dsih_hal_gen_rd_vc(dsi, vc);
++	for (timeout = 0; timeout < DSIH_FIFO_ACTIVE_WAIT; timeout++)
++	{	/* check if payload Tx fifo is not full */
++		if (!mipi_dsih_hal_gen_cmd_fifo_full(dsi))
++		{
++				printk("I am here!\n");
++			mipi_dsih_hal_gen_packet_header(dsi, vc, data_type, msb_byte, lsb_byte);
++			break;
++		}
++	}
++	if (!(timeout < DSIH_FIFO_ACTIVE_WAIT))
++	{
++		printk("tx rd command timed out\n");
++		return 0;
++	}
++	/* loop for the number of words to be read */
++	for (timeout = 0; timeout < DSIH_FIFO_ACTIVE_WAIT; timeout++)
++	{	/* check if command transaction is done */
++		if (!mipi_dsih_hal_gen_rd_cmd_busy(dsi))
++		{
++			printk("is not busy\n");
++			if (!mipi_dsih_hal_gen_read_fifo_empty(dsi))
++			{
++				for (counter = 0; (!mipi_dsih_hal_gen_read_fifo_empty(dsi)); counter += 4)
++				{
++						err_code = mipi_dsih_hal_gen_read_payload(dsi, temp);
++						if (err_code)
++						{
++							return 0;
++						}
++					if (counter < bytes_to_read)
++					{
++						for (i = 0; i < 4; i++)
++						{
++							if ((counter + i) < bytes_to_read)
++							{
++								/* put 32 bit temp in 4 bytes of buffer passed by user*/
++								read_buffer[counter + i] = (unsigned char)(temp[0] >> (i * 8));
++								last_count = i + counter;
++							}
++							else
++							{
++								if ((unsigned char)(temp[0] >> (i * 8)) != 0x00)
++								{
++									last_count = i + counter;
++								}
++							}
++						}
++					}
++					else
++					{
++						last_count = counter;
++						for (i = 0; i < 4; i++)
++						{
++							if ((unsigned char)(temp[0] >> (i * 8)) != 0x00)
++							{
++								last_count = i + counter;
++							}
++						}
++					}
++				}
++				return last_count + 1;
++			}
++		}
++	}
++	printk("rx command timed out\n");
++	return 0;
++}
++
++dsih_error_t mipi_dsih_gen_wr_packet(struct dsi_device * dsi, unsigned char vc, unsigned char data_type, unsigned char* params, unsigned short param_length)
++{
++	dsih_error_t err_code = OK;
++	/* active delay iterator */
++	int timeout = 0;
++	/* iterators */
++	int i = 0;
++	int j = 0;
++	/* holds padding bytes needed */
++	int compliment_counter = 0;
++	unsigned char* payload = 0;
++	/* temporary variable to arrange bytes into words */
++	unsigned int temp = 0;
++	unsigned short word_count = 0;
++	if (dsi == 0)
++	{
++		return ERR_DSI_INVALID_INSTANCE;
++	}
++	if (dsi->state != INITIALIZED)
++	{
++		return ERR_DSI_INVALID_INSTANCE;
++	}
++	if ((params == 0) && (param_length != 0)) /* pointer NULL */
++	{
++		return ERR_DSI_OUT_OF_BOUND;
++	}
++	if (param_length > 2)
++	{	/* long packet - write word count to header, and the rest to payload */
++		payload = params + (2 * sizeof(params[0]));
++		word_count = (params[1] << 8) | params[0];
++		if ((param_length - 2) < word_count)
++		{
++			printk("sent > input payload. complemented with zeroes\n");
++			compliment_counter = (param_length - 2) - word_count;
++		}
++		else if ((param_length - 2) > word_count)
++		{
++				printk("Overflow - input > sent. payload truncated\n");
++		}
++		for (i = 0; i < (param_length - 2); i += j)
++		{
++			temp = 0;
++			for (j = 0; (j < 4) && ((j + i) < (param_length - 2)); j++)
++			{	/* temp = (payload[i + 3] << 24) | (payload[i + 2] << 16) | (payload[i + 1] << 8) | payload[i]; */
++				temp |= payload[i + j] << (j * 8);
++			}
++			/* check if payload Tx fifo is not full */
++			for (timeout = 0; timeout < DSIH_FIFO_ACTIVE_WAIT; timeout++)
++			{
++				/*send data , or parameters*/
++				if (!mipi_dsih_hal_gen_packet_payload(dsi, temp))
++				{
++					break;
++				}
++			}
++			if (!(timeout < DSIH_FIFO_ACTIVE_WAIT))
++			{
++				return ERR_DSI_TIMEOUT;
++			}
++		}
++		/* if word count entered by the user more than actual parameters received
++		 * fill with zeroes - a fail safe mechanism, otherwise controller will
++		 * want to send data from an empty buffer */
++		for (i = 0; i < compliment_counter; i++)
++		{
++			/* check if payload Tx fifo is not full */
++			for (timeout = 0; timeout < DSIH_FIFO_ACTIVE_WAIT; timeout++)
++			{
++				if (!mipi_dsih_hal_gen_packet_payload(dsi, 0x00))
++				{
++					break;
++				}
++			}
++			if (!(timeout < DSIH_FIFO_ACTIVE_WAIT))
++			{
++				return ERR_DSI_TIMEOUT;
++			}
++		}
++	}
++
++	for (timeout = 0; timeout < DSIH_FIFO_ACTIVE_WAIT; timeout++)
++	{
++		/* check if payload Tx fifo is not full */
++		if (!mipi_dsih_hal_gen_cmd_fifo_full(dsi))
++		{
++			if (param_length == 0)
++			{
++				err_code |= mipi_dsih_hal_gen_packet_header(dsi, vc, data_type, 0x0, 0x0);
++			}
++			else if (param_length == 1)
++			{
++				err_code |= mipi_dsih_hal_gen_packet_header(dsi, vc, data_type, 0x0, params[0]);
++			}
++			else
++			{
++				/*make the header*/
++				err_code |= mipi_dsih_hal_gen_packet_header(dsi, vc, data_type, params[1], params[0]);
++			}
++			break;
++		}
++	}
++	if (!(timeout < DSIH_FIFO_ACTIVE_WAIT))
++	{
++		printk("dsi_gen_write timeout!\n");
++		err_code = ERR_DSI_TIMEOUT;
++	}
++	return err_code;
++}
++
++unsigned int  mipi_dsih_write_register_configuration(struct dsi_device * dsi, register_config_t *config, uint16_t config_length)
++{
++	unsigned short count = 0;
++	if (dsi == 0)
++	{
++		return ERR_DSI_INVALID_INSTANCE;
++	}
++	for (count = 0; count < config_length; count++)
++	{
++		mipi_dsih_write_word(dsi, config[count].addr, config[count].data);
++	}
++	return count;
++}
++
++int write_command(struct dsi_device * dsi, struct dsi_cmd_packet cmd_data)
++{
++	unsigned int i, j;
++	unsigned int packet_type;
++	unsigned char dsi_command_param[MAX_WORD_COUNT] = {0};
++	unsigned short word_count = 0;
++	unsigned int ret;
++	/*word count*/
++	packet_type = cmd_data.packet_type;
++	dsi_command_param[0] = cmd_data.cmd0_or_wc_lsb;
++	dsi_command_param[1] = cmd_data.cmd1_or_wc_msb;
++	if(packet_type == 0x39 || packet_type == 0x29){ //dcs long packet
++		word_count = ((dsi_command_param[1] << 8 ) | dsi_command_param[0]);
++		j = 2;
++		/*payload: */
++		for(i = 0; i < word_count; i++) {
++			dsi_command_param[j++] = cmd_data.cmd_data[i];
++		}
++
++	}else if (packet_type == 0x05 || packet_type == 0x15){ //dcs short packet
++		word_count = 0;
++	}else{
++		printk("not support packet type, please checkout!,\n");
++	}
++	ret = mipi_dsih_gen_wr_packet(dsi, 0, packet_type, dsi_command_param, word_count + 2);
++	if(ret < 0) {
++		printk("gen_wr_packet failed. ret:%d\n", ret);
++	}
++	mdelay(1); //Some panels failed to init without this.
++
++	return 0;
++}
++
++int read_command(struct dsi_device *dsi, struct dsi_cmd_packet cmd_data, unsigned char *buf, int count)
++{
++
++	unsigned int i, j;
++	unsigned int packet_type;
++	unsigned char dsi_command_param[MAX_WORD_COUNT] = {0};
++	unsigned short word_count = 0;
++	unsigned int ret;
++	/*word count*/
++	packet_type = cmd_data.packet_type;
++	dsi_command_param[0] = cmd_data.cmd0_or_wc_lsb;
++	dsi_command_param[1] = cmd_data.cmd1_or_wc_msb;
++	if (packet_type == 0x04 || packet_type == 0x14 || packet_type == 0x24 || packet_type == 0x06){ //dcs short packet
++		word_count = 0;
++	}else{
++		printk("not support packet type, please checkout!,\n");
++	}
++
++	ret = mipi_dsih_gen_rd_packet(dsi, 0, packet_type, dsi_command_param[1], dsi_command_param[0], count, buf);
++	if(ret < 0) {
++		printk("gen_rd_packet failed. ret:%d\n", ret);
++	}
++	mdelay(1); //Some panels failed to init without this.
++
++	return 0;
++}
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsih_hal.h b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsih_hal.h
+new file mode 100644
+index 000000000..aa3b54f94
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/jz_mipi_dsi/jz_mipi_dsih_hal.h
+@@ -0,0 +1,147 @@
++/*
++ * @file mipi_dsih_hal.h
++ *
++ *  SG DWC PT02
++ */
++#ifndef MIPI_DSIH_HAL_H_
++#define MIPI_DSIH_HAL_H_
++
++#include "../jz_dsim.h"
++
++
++/**
++ * @return the dsi host core version
++ */
++unsigned int mipi_dsih_hal_get_version(struct dsi_device * dsi);
++/*enable dsihost*/
++void mipi_dsih_hal_power(struct dsi_device * dsi, int on);
++/**
++ * set the virtual channel ID that is indexes to the DPI video mode stream
++ * @param vc virtual channel ID
++ */
++void mipi_dsih_hal_dpi_video_vc(struct dsi_device * dsi, unsigned char vc);
++/**
++ * @return vc virtual channel ID
++ */
++unsigned char mipi_dsih_hal_dpi_get_video_vc(struct dsi_device * dsi);
++
++dsih_error_t mipi_dsih_hal_dpi_color_coding(struct dsi_device * dsi, dsih_color_coding_t color_coding);
++dsih_color_coding_t mipi_dsih_hal_dpi_get_color_coding(struct dsi_device * dsi);
++unsigned char mipi_dsih_hal_dpi_get_color_depth(struct dsi_device * dsi);
++unsigned char mipi_dsih_hal_dpi_get_color_config(struct dsi_device * dsi);
++void mipi_dsih_hal_dpi_18_loosely_packet_en(struct dsi_device * dsi, int enable);
++void mipi_dsih_hal_dpi_color_mode_pol(struct dsi_device * dsi, int active_low);
++void mipi_dsih_hal_dpi_shut_down_pol(struct dsi_device * dsi, int active_low);
++void mipi_dsih_hal_dpi_hsync_pol(struct dsi_device * dsi, int active_low);
++void mipi_dsih_hal_dpi_vsync_pol(struct dsi_device * dsi, int active_low);
++void mipi_dsih_hal_dpi_dataen_pol(struct dsi_device * dsi, int active_low);
++void mipi_dsih_hal_dpi_frame_ack_en(struct dsi_device * dsi, int enable);
++void mipi_dsih_hal_dpi_null_packet_en(struct dsi_device * dsi, int enable);
++void mipi_dsih_hal_dpi_multi_packet_en(struct dsi_device * dsi, int enable);
++void mipi_dsih_hal_dpi_lp_during_hfp(struct dsi_device * dsi, int enable);
++void mipi_dsih_hal_dpi_lp_during_hbp(struct dsi_device * dsi, int enable);
++void mipi_dsih_hal_dpi_lp_during_vactive(struct dsi_device * dsi, int enable);
++void mipi_dsih_hal_dpi_lp_during_vfp(struct dsi_device * dsi, int enable);
++void mipi_dsih_hal_dpi_lp_during_vbp(struct dsi_device * dsi, int enable);
++void mipi_dsih_hal_dpi_lp_during_vsync(struct dsi_device * dsi, int enable);
++
++dsih_error_t mipi_dsih_hal_dpi_video_mode_type(struct dsi_device * dsi, dsih_video_mode_t type);
++void mipi_dsih_hal_dpi_video_mode_en(struct dsi_device * dsi, int enable);
++int mipi_dsih_hal_dpi_is_video_mode(struct dsi_device * dsi);
++dsih_error_t mipi_dsih_hal_dpi_null_packet_size(struct dsi_device * dsi, unsigned short size);
++dsih_error_t mipi_dsih_hal_dpi_chunks_no(struct dsi_device * dsi, unsigned short no);
++dsih_error_t mipi_dsih_hal_dpi_video_packet_size(struct dsi_device * dsi, unsigned short size);
++
++void mipi_dsih_hal_tear_effect_ack_en(struct dsi_device * dsi, int enable);
++
++void mipi_dsih_hal_cmd_ack_en(struct dsi_device * dsi, int enable);
++dsih_error_t mipi_dsih_hal_dcs_wr_tx_type(struct dsi_device * dsi, unsigned no_of_param, int lp);
++dsih_error_t mipi_dsih_hal_dcs_rd_tx_type(struct dsi_device * dsi, unsigned no_of_param, int lp);
++dsih_error_t mipi_dsih_hal_gen_wr_tx_type(struct dsi_device * dsi, unsigned no_of_param, int lp);
++dsih_error_t mipi_dsih_hal_gen_rd_tx_type(struct dsi_device * dsi, unsigned no_of_param, int lp);
++void mipi_dsih_hal_max_rd_size_type(struct dsi_device * dsi, int lp);
++void mipi_dsih_hal_gen_cmd_mode_en(struct dsi_device * dsi, int enable);
++int mipi_dsih_hal_gen_is_cmd_mode(struct dsi_device * dsi);
++
++void mipi_dsih_hal_dpi_hline(struct dsi_device * dsi, unsigned short time);
++void mipi_dsih_hal_dpi_hbp(struct dsi_device * dsi, unsigned short time);
++void mipi_dsih_hal_dpi_hsa(struct dsi_device * dsi, unsigned short time);
++void mipi_dsih_hal_dpi_vactive(struct dsi_device * dsi, unsigned short lines);
++void mipi_dsih_hal_dpi_vfp(struct dsi_device * dsi, unsigned short lines);
++void mipi_dsih_hal_dpi_vbp(struct dsi_device * dsi, unsigned short lines);
++void mipi_dsih_hal_dpi_vsync(struct dsi_device * dsi, unsigned short lines);
++dsih_error_t mipi_dsih_hal_gen_packet_header(struct dsi_device * dsi, unsigned char vc, unsigned char packet_type, unsigned char ms_byte, unsigned char ls_byte);
++/*dsih_error_t mipi_dsih_hal_gen_packet_payload(struct dsi_device * dsi, unsigned int* payload, unsigned short payload_size);*/
++dsih_error_t mipi_dsih_hal_gen_packet_payload(struct dsi_device * dsi, unsigned int payload);
++dsih_error_t mipi_dsih_hal_gen_read_payload(struct dsi_device * dsi, unsigned int* payload);
++
++void mipi_dsih_hal_timeout_clock_division(struct dsi_device * dsi, unsigned char byte_clk_division_factor);
++void mipi_dsih_hal_lp_rx_timeout(struct dsi_device * dsi, unsigned short count);
++void mipi_dsih_hal_hs_tx_timeout(struct dsi_device * dsi, unsigned short count);
++
++unsigned int mipi_dsih_hal_error_status_0(struct dsi_device * dsi, unsigned int mask);
++unsigned int mipi_dsih_hal_error_status_1(struct dsi_device * dsi, unsigned int mask);
++void mipi_dsih_hal_error_mask_0(struct dsi_device * dsi, unsigned int mask);
++void mipi_dsih_hal_error_mask_1(struct dsi_device * dsi, unsigned int mask);
++unsigned int mipi_dsih_hal_get_error_mask_0(struct dsi_device * dsi, unsigned int mask);
++unsigned int mipi_dsih_hal_get_error_mask_1(struct dsi_device * dsi, unsigned int mask);
++
++void mipi_dsih_hal_dbi_out_color_coding(struct dsi_device * dsi, unsigned char color_depth, unsigned char option);
++void mipi_dsih_hal_dbi_in_color_coding(struct dsi_device * dsi, unsigned char color_depth, unsigned char option);
++void mipi_dsih_hal_dbi_lut_size(struct dsi_device * dsi, unsigned char size);
++void mipi_dsih_hal_dbi_partitioning_en(struct dsi_device * dsi, int enable);
++void mipi_dsih_hal_dbi_dcs_vc(struct dsi_device * dsi, unsigned char vc);
++
++void mipi_dsih_hal_dbi_cmd_size(struct dsi_device * dsi, unsigned short size);
++void mipi_dsih_hal_dbi_max_cmd_size(struct dsi_device * dsi, unsigned short size);
++int mipi_dsih_hal_dbi_rd_cmd_busy(struct dsi_device * dsi);
++int mipi_dsih_hal_dbi_read_fifo_full(struct dsi_device * dsi);
++int mipi_dsih_hal_dbi_read_fifo_empty(struct dsi_device * dsi);
++int mipi_dsih_hal_dbi_write_fifo_full(struct dsi_device * dsi);
++int mipi_dsih_hal_dbi_write_fifo_empty(struct dsi_device * dsi);
++int mipi_dsih_hal_dbi_cmd_fifo_full(struct dsi_device * dsi);
++int mipi_dsih_hal_dbi_cmd_fifo_empty(struct dsi_device * dsi);
++
++void mipi_dsih_hal_gen_rd_vc(struct dsi_device * dsi, unsigned char vc);
++void mipi_dsih_hal_gen_eotp_rx_en(struct dsi_device * dsi, int enable);
++void mipi_dsih_hal_gen_eotp_tx_en(struct dsi_device * dsi, int enable);
++void mipi_dsih_hal_bta_en(struct dsi_device * dsi, int enable);
++void mipi_dsih_hal_gen_ecc_rx_en(struct dsi_device * dsi, int enable);
++void mipi_dsih_hal_gen_crc_rx_en(struct dsi_device * dsi, int enable);
++int mipi_dsih_hal_gen_rd_cmd_busy(struct dsi_device * dsi);
++int mipi_dsih_hal_gen_read_fifo_full(struct dsi_device * dsi);
++int mipi_dsih_hal_gen_read_fifo_empty(struct dsi_device * dsi);
++int mipi_dsih_hal_gen_write_fifo_full(struct dsi_device * dsi);
++int mipi_dsih_hal_gen_write_fifo_empty(struct dsi_device * dsi);
++int mipi_dsih_hal_gen_cmd_fifo_full(struct dsi_device * dsi);
++int mipi_dsih_hal_gen_cmd_fifo_empty(struct dsi_device * dsi);
++
++/* only if DPI */
++dsih_error_t mipi_dsih_phy_hs2lp_config(struct dsi_device * dsi, unsigned char no_of_byte_cycles);
++dsih_error_t mipi_dsih_phy_lp2hs_config(struct dsi_device * dsi, unsigned char no_of_byte_cycles);
++dsih_error_t mipi_dsih_phy_bta_time(struct dsi_device * dsi, unsigned short no_of_byte_cycles);
++/* */
++
++void mipi_dsih_write_word(struct dsi_device * dsi, unsigned int reg_address, unsigned int data);
++void mipi_dsih_write_part(struct dsi_device * dsi, unsigned int reg_address, unsigned int data, unsigned char shift, unsigned char width);
++unsigned int mipi_dsih_read_word(struct dsi_device * dsi, unsigned int reg_address);
++unsigned int mipi_dsih_read_part(struct dsi_device * dsi, unsigned int reg_address, unsigned char shift, unsigned char width);
++void mipi_dsih_dphy_enable_hs_clk(struct dsi_device *dsi, int enable);
++void mipi_dsih_dphy_auto_clklane_ctrl(struct dsi_device *dsi, int enable);
++void mipi_dsih_dphy_test_clock(struct dsi_device * dsi, int value);
++void mipi_dsih_dphy_test_clear(struct dsi_device * dsi, int value);
++void mipi_dsih_dphy_test_en(struct dsi_device * dsi, unsigned char on_falling_edge);
++void mipi_dsih_dphy_test_data_in(struct dsi_device *dsi, unsigned char test_data);
++void mipi_dsih_dphy_write(struct dsi_device * dsi, unsigned char address, unsigned char * data, unsigned char data_length);
++void mipi_dsih_cmd_mode(struct dsi_device * dsi, int en);
++
++
++void mipi_dsih_hal_gen_set_mode(struct dsi_device * dsi, int enable);
++
++unsigned int  mipi_dsih_write_register_configuration(struct dsi_device * dsi, register_config_t *config, uint16_t config_length);
++unsigned short mipi_dsih_gen_rd_packet(struct dsi_device * dsi, unsigned char vc, unsigned char data_type, unsigned char msb_byte, unsigned char lsb_byte, unsigned char bytes_to_read, unsigned char* read_buffer);
++dsih_error_t mipi_dsih_gen_wr_packet(struct dsi_device * dsi, unsigned char vc, unsigned char data_type, unsigned char* params, unsigned short param_length);
++
++int write_command(struct dsi_device * dsi, struct dsi_cmd_packet cmd_data);
++int read_command(struct dsi_device *dsi, struct dsi_cmd_packet cmd_data, unsigned char *buf, int count);
++#endif /* MIPI_DSI_API_H_ */
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/lcd_panel.h b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/lcd_panel.h
+new file mode 100644
+index 000000000..090140773
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/lcd_panel.h
+@@ -0,0 +1,156 @@
++#ifndef __LCD_PANEL_H__
++#define __LCD_PANEL_H__
++
++enum ingenic_lcd_type {
++        LCD_TYPE_TFT = 0,
++        LCD_TYPE_SLCD =1,
++        LCD_TYPE_MIPI_SLCD = 2,
++	LCD_TYPE_MIPI_TFT,
++};
++
++/* smart lcd interface_type */
++enum smart_lcd_type {
++	SMART_LCD_TYPE_6800,
++	SMART_LCD_TYPE_8080,
++	SMART_LCD_TYPE_SPI_3,
++	SMART_LCD_TYPE_SPI_4,
++};
++
++/* smart lcd format */
++enum smart_lcd_format {
++	SMART_LCD_FORMAT_565,
++	SMART_LCD_FORMAT_666,
++	SMART_LCD_FORMAT_888,
++};
++
++/* smart lcd command width */
++enum smart_lcd_cwidth {
++	SMART_LCD_CWIDTH_8_BIT,
++	SMART_LCD_CWIDTH_9_BIT,
++	SMART_LCD_CWIDTH_16_BIT,
++	SMART_LCD_CWIDTH_18_BIT,
++	SMART_LCD_CWIDTH_24_BIT,
++};
++
++/* smart lcd data width */
++enum smart_lcd_dwidth {
++        SMART_LCD_DWIDTH_8_BIT,
++        SMART_LCD_DWIDTH_9_BIT,
++        SMART_LCD_DWIDTH_16_BIT,
++        SMART_LCD_DWIDTH_18_BIT,
++        SMART_LCD_DWIDTH_24_BIT,
++};
++
++/* smart lcd data width */
++enum smart_config_type {
++	SMART_CONFIG_DATA,
++	SMART_CONFIG_PRM,
++	SMART_CONFIG_CMD,
++	SMART_CONFIG_UDELAY,
++};
++struct smart_lcd_data_table {
++	enum smart_config_type type;
++	unsigned int value;
++};
++enum tft_lcd_color_even {
++	TFT_LCD_COLOR_EVEN_RGB,
++	TFT_LCD_COLOR_EVEN_RBG,
++	TFT_LCD_COLOR_EVEN_BGR,
++	TFT_LCD_COLOR_EVEN_BRG,
++	TFT_LCD_COLOR_EVEN_GBR,
++	TFT_LCD_COLOR_EVEN_GRB,
++};
++
++enum tft_lcd_color_odd {
++	TFT_LCD_COLOR_ODD_RGB,
++	TFT_LCD_COLOR_ODD_RBG,
++	TFT_LCD_COLOR_ODD_BGR,
++	TFT_LCD_COLOR_ODD_BRG,
++	TFT_LCD_COLOR_ODD_GBR,
++	TFT_LCD_COLOR_ODD_GRB,
++};
++
++enum tft_lcd_mode {
++	TFT_LCD_MODE_PARALLEL_888,
++	TFT_LCD_MODE_PARALLEL_666,
++	TFT_LCD_MODE_PARALLEL_565,
++	TFT_LCD_MODE_SERIAL_RGB,
++	TFT_LCD_MODE_SERIAL_RGBD,
++};
++
++struct tft_config {
++	unsigned int pix_clk_inv:1;
++	unsigned int de_dl:1;
++	unsigned int sync_dl:1;
++	unsigned int vsync_dl:1;
++	enum tft_lcd_color_even color_even;
++	enum tft_lcd_color_odd color_odd;
++	enum tft_lcd_mode mode;
++};
++
++struct smart_config {
++	unsigned int te_switch:1;
++	unsigned int te_mipi_switch:1;
++	unsigned int te_md:1;
++	unsigned int te_dp:1;
++	unsigned int te_anti_jit:1;
++	unsigned int dc_md:1;
++	unsigned int wr_md:1;
++	enum smart_lcd_type smart_type;
++	enum smart_lcd_format pix_fmt;
++	enum smart_lcd_dwidth dwidth;
++	enum smart_lcd_cwidth cwidth;
++	unsigned int bus_width;
++
++	unsigned long write_gram_cmd;
++	unsigned int length_cmd;
++	struct smart_lcd_data_table *data_table;
++	unsigned int length_data_table;
++	int (*init) (void);
++	int (*gpio_for_slcd) (void);
++};
++
++
++struct lcd_panel_ops {
++	void (*init)(void *panel);
++	void (*enable)(void *panel);
++	void (*disable)(void *panel);
++};
++
++struct jzdsi_data {
++	struct fb_videomode *modes;
++	struct video_config video_config;
++	struct dsi_config dsi_config;
++	unsigned int bpp_info;
++	unsigned int max_bps;
++	unsigned int dsi_iobase;
++	unsigned int dsi_phy_iobase;
++};
++
++struct lcd_panel {
++	const char *name;
++	unsigned int num_modes;
++	struct fb_videomode *modes;
++	struct jzdsi_data *dsi_pdata;
++
++	enum ingenic_lcd_type lcd_type;
++	unsigned int bpp;
++	unsigned int width;
++	unsigned int height;
++
++	struct smart_config *smart_config;
++	struct tft_config *tft_config;
++
++	unsigned dither_enable:1;
++	struct {
++		unsigned dither_red;
++		unsigned dither_green;
++		unsigned dither_blue;
++	} dither;
++
++	struct lcd_panel_ops *ops;
++};
++
++
++
++#endif
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/sysfs.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/sysfs.c
+new file mode 100644
+index 000000000..3486274ac
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/sysfs.c
+@@ -0,0 +1,784 @@
++#include <linux/device.h>
++#include <linux/kernel.h>
++#include <linux/sysfs.h>
++#include <linux/fs.h>
++#include <linux/fb.h>
++
++#include "sysfs.h"
++#include "ingenicfb.h"
++#include "hw_composer_fb.h"
++#include "uapi_ingenicfb.h"
++
++static ssize_t
++dump_lcd(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct dpu_ctrl *dctrl = sysfs_get_dctrl(dev);
++
++	dump_lcdc_registers(dctrl);
++
++	dump_comp_desc(dctrl);
++
++	dump_rdma_desc(dctrl);
++
++	return 0;
++}
++
++	static ssize_t
++dump_irqcnts(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct dpu_ctrl *dctrl = sysfs_get_dctrl(dev);
++	struct dbg_irqcnt *dbg = &dctrl->dbg_irqcnt;
++	char *p = buf;
++
++	p += sprintf(p, "comp_fps	: %lld\n", dctrl->comp_fps);
++	p += sprintf(p, "---------------------\n");
++	p += sprintf(p, "irqcnt		: %lld\n", dbg->irqcnt);
++	p += sprintf(p, "cmp_start	: %lld\n", dbg->cmp_start);
++	p += sprintf(p, "stop_disp_ack	: %lld\n", dbg->stop_disp_ack);
++	p += sprintf(p, "disp_end	: %lld\n", dbg->disp_end);
++	p += sprintf(p, "tft_under	: %lld\n", dbg->tft_under);
++	p += sprintf(p, "wdma_over	: %lld\n", dbg->wdma_over);
++	p += sprintf(p, "wdma_end	: %lld\n", dbg->wdma_end);
++	p += sprintf(p, "layer3_end	: %lld\n", dbg->layer3_end);
++	p += sprintf(p, "layer2_end	: %lld\n", dbg->layer2_end);
++	p += sprintf(p, "layer1_end	: %lld\n", dbg->layer1_end);
++	p += sprintf(p, "layer0_end	: %lld\n", dbg->layer0_end);
++	p += sprintf(p, "clr_cmp_end	: %lld\n", dbg->clr_cmp_end);
++	p += sprintf(p, "stop_wrbk_ack	: %lld\n", dbg->stop_wrbk_ack);
++	p += sprintf(p, "srd_start	: %lld\n", dbg->srd_start);
++	p += sprintf(p, "srd_end	: %lld\n", dbg->srd_end);
++	p += sprintf(p, "cmp_w_slow	: %lld\n", dbg->cmp_w_slow);
++
++	return p - buf;
++}
++
++
++static DEVICE_ATTR(dump_lcd, S_IRUGO|S_IWUSR, dump_lcd, NULL);
++static DEVICE_ATTR(dump_irqcnts, (S_IRUGO|S_IWUGO) & (~S_IWOTH), dump_irqcnts, NULL);
++
++/*Debug sysfs*/
++static struct attribute *lcd_debug_attrs[] = {
++	&dev_attr_dump_lcd.attr,
++	&dev_attr_dump_irqcnts.attr,
++        NULL,
++};
++
++const char lcd_group_name[] = "debug";
++static struct attribute_group lcd_debug_attr_group = {
++        .name   = lcd_group_name,
++        .attrs  = lcd_debug_attrs,
++};
++
++/* ===========================Composer=============================*/
++
++static ssize_t store_frame_size(struct device *dev,
++                struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct hw_compfb_device *compfb = sysfs_get_compfb(dev);
++	int layer = to_layer_attr(attr)->id;
++
++	struct export_info *info = &compfb->export_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	char *p;
++	char *s = (char *)buf;
++
++	p = strsep(&s, "x");
++	if(!s) {
++		return -EINVAL;
++	}
++
++	if(info->layer_exported[layer] == 1) {
++		return -EBUSY;
++	}
++
++	info->layer_frame_size_w[layer] = simple_strtoul(p, NULL, 0);
++	info->layer_frame_size_h[layer] = simple_strtoul(s, NULL, 0);
++
++	return n;
++}
++
++
++static ssize_t store_src_size(struct device *dev,
++                struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct hw_compfb_device *compfb = sysfs_get_compfb(dev);
++	int layer = to_layer_attr(attr)->id;
++
++	struct export_info *info = &compfb->export_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	char *p;
++	char *s = (char *)buf;
++	unsigned int src_w = 0;
++	unsigned int src_h = 0;
++
++	p = strsep(&s, "x");
++	if(!s) {
++		return -EINVAL;
++	}
++
++	src_w = simple_strtoul(p, NULL, 0);
++	src_h = simple_strtoul(s, NULL, 0);
++
++	if((src_w * src_h) > (info->layer_frame_size_w[layer] * info->layer_frame_size_h[layer])) {
++		dev_err(dev, "src_size(%xx%x) should smaller than frame_size(%xx%x)",
++				src_w, src_h,
++				info->layer_frame_size_w[layer], info->layer_frame_size_h[layer]);
++		return -EINVAL;
++	}
++
++	lay_cfg->source_w = src_w;
++	lay_cfg->source_h = src_h;
++
++	return n;
++}
++
++static ssize_t store_stride(struct device *dev,
++                struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct hw_compfb_device *compfb = sysfs_get_compfb(dev);
++	int layer = to_layer_attr(attr)->id;
++
++	struct export_info *info = &compfb->export_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	char *s = (char *)buf;
++	unsigned int stride = 0;
++
++	stride = simple_strtoul(s, NULL, 0);
++
++	lay_cfg->stride = stride;
++
++	return n;
++}
++
++static ssize_t store_uv_stride(struct device *dev,
++                struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct hw_compfb_device *compfb = sysfs_get_compfb(dev);
++	int layer = to_layer_attr(attr)->id;
++
++	struct export_info *info = &compfb->export_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	char *s = (char *)buf;
++	unsigned int stride = 0;
++
++	stride = simple_strtoul(s, NULL, 0);
++
++	lay_cfg->uv_stride = stride;
++
++	return n;
++}
++
++static ssize_t store_z_order(struct device *dev,
++                struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct hw_compfb_device *compfb = sysfs_get_compfb(dev);
++	int layer = to_layer_attr(attr)->id;
++
++	struct export_info *info = &compfb->export_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	char *s = (char *)buf;
++	unsigned int z_order = 0;
++
++	z_order = simple_strtoul(s, NULL, 0);
++
++	lay_cfg->lay_z_order = z_order;
++
++	return n;
++}
++
++static ssize_t store_src_fmt(struct device *dev,
++                struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct hw_compfb_device *compfb = sysfs_get_compfb(dev);
++	int layer = to_layer_attr(attr)->id;
++
++	struct export_info *info = &compfb->export_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	int format = simple_strtoul(buf, NULL, 0);
++
++	info->layer_color_mode[layer] = format;
++
++	return n;
++
++}
++
++static ssize_t store_target_size(struct device *dev,
++                struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct hw_compfb_device *compfb = sysfs_get_compfb(dev);
++	int layer = to_layer_attr(attr)->id;
++
++	struct export_info *info = &compfb->export_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	char *p;
++	char *s = (char *)buf;
++
++	p = strsep(&s, "x");
++	if(!s) {
++		return -EINVAL;
++	}
++
++
++	lay_cfg->scale_w = simple_strtoul(p, NULL, 0);
++	lay_cfg->scale_h = simple_strtoul(s, NULL, 0);
++
++	return n;
++}
++
++static ssize_t store_target_pos(struct device *dev,
++                struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct hw_compfb_device *compfb = sysfs_get_compfb(dev);
++	int layer = to_layer_attr(attr)->id;
++
++	struct export_info *info = &compfb->export_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	char *p;
++	char *s = (char *)buf;
++
++	p = strsep(&s, "x");
++	if(!s) {
++		return -EINVAL;
++	}
++
++
++	lay_cfg->disp_pos_x = simple_strtoul(p, NULL, 0);
++	lay_cfg->disp_pos_y = simple_strtoul(s, NULL, 0);
++
++	return n;
++}
++
++static ssize_t store_nframes(struct device *dev,
++                struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct hw_compfb_device *compfb = sysfs_get_compfb(dev);
++	int layer = to_layer_attr(attr)->id;
++
++	struct export_info *info = &compfb->export_info;
++
++	if(info->layer_exported[layer] == 1) {
++		return -EBUSY;
++	}
++
++	info->layer_frames[layer] = simple_strtoul(buf, NULL, 0);
++
++	return n;
++}
++
++/*tlb_en:buf_addr:uv_addr*/
++static ssize_t store_buf_addr(struct device *dev,
++                struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct hw_compfb_device *compfb = sysfs_get_compfb(dev);
++	int layer = to_layer_attr(attr)->id;
++
++	struct export_info *info = &compfb->export_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	char *p;
++	char *s = (char *)buf;
++
++	p = strsep(&s, ":");
++	if(!s) {
++		return -EINVAL;
++	}
++
++	lay_cfg->addr[0] = simple_strtoul(p, NULL, 16);
++	lay_cfg->uv_addr[0] = simple_strtoul(s, NULL, 16);
++
++	return n;
++}
++
++static ssize_t store_enable(struct device *dev,
++                struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct hw_compfb_device *compfb = sysfs_get_compfb(dev);
++	int layer = to_layer_attr(attr)->id;
++
++	struct export_info *info = &compfb->export_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	if(lay_cfg->scale_w == 0 || lay_cfg->scale_h == 0) {
++		dev_err(compfb->dev, "invalid scale_w and scale_h for layer: %d\n", layer);
++	}
++
++	lay_cfg->lay_en = simple_strtoul(buf, NULL, 0);
++
++	return n;
++}
++
++static ssize_t show_exportfb(struct device *dev,
++                struct device_attribute *attr, char *buf)
++{
++	struct hw_compfb_device *compfb = sysfs_get_compfb(dev);
++	int layer = to_layer_attr(attr)->id;
++
++	struct export_info *info = &compfb->export_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[layer];
++	int ret = 0;
++	char *p = buf;
++
++	p += sprintf(p, "==== info ====\n");
++	p += sprintf(p, "export:%d\n", info->layer_exported[layer]);
++	p += sprintf(p, "src:%dx%d\n", lay_cfg->source_w, lay_cfg->source_h);
++	p += sprintf(p, "stride:%d\n", lay_cfg->stride);
++	p += sprintf(p, "uv_stride:%d\n", lay_cfg->uv_stride);
++	p += sprintf(p, "z_order:%d\n", lay_cfg->lay_z_order);
++	p += sprintf(p, "fmt:%d \n", info->layer_color_mode[layer]);
++	p += sprintf(p, "target:%dx%d\n", lay_cfg->scale_w, lay_cfg->scale_h);
++	p += sprintf(p, "pos:%dx%d\n", lay_cfg->disp_pos_x, lay_cfg->disp_pos_y);
++	p += sprintf(p, "nframes:%d\n", info->layer_frames[layer]);
++	p += sprintf(p, "addr:%d\n", lay_cfg->addr[0]);
++	p += sprintf(p, "uv_buf_addr:%d\n", lay_cfg->uv_addr[0]);
++	p += sprintf(p, "framesize:%dx%d\n", info->layer_frame_size_w[layer], info->layer_frame_size_h[layer]);
++	p += sprintf(p, "enable:%d\n", lay_cfg->lay_en);
++
++	return p - buf;
++}
++
++static ssize_t store_exportfb(struct device *dev,
++                struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct hw_compfb_device *compfb = sysfs_get_compfb(dev);
++	struct export_info *info = &compfb->export_info;
++	int layer = to_layer_attr(attr)->id;
++
++	struct ingenicfb_frm_cfg *frm_cfg = &info->frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	int export = simple_strtoul(buf, NULL, 0);
++
++	if(export) {
++		/*TODO:add Lock.*/
++		if(info->layer_exported[layer] == 1) {
++			return -EBUSY;
++		}
++
++		if(lay_cfg->source_w == 0 || lay_cfg->source_h == 0) {
++			dev_err(compfb->dev, "Invalid layer src_size %dx%d\n", lay_cfg->source_w, lay_cfg->source_h);
++			return -EINVAL;
++		}
++
++		if(info->layer_frame_size_w[layer] == 0 || info->layer_frame_size_h[layer] == 0) {
++			dev_err(compfb->dev, "Invalid layer_framesize %dx%d, wrap to lay_cfg src_size: %dx%d\n",
++					info->layer_frame_size_w[layer], info->layer_frame_size_h[layer],
++					lay_cfg->source_w, lay_cfg->source_h);
++			info->layer_frame_size_w[layer] = lay_cfg->source_w;
++			info->layer_frame_size_h[layer] = lay_cfg->source_h;
++		}
++
++		info->layer_exported[layer] = 1;
++	} else {
++		/*TODO:add Lock.*/
++		if(info->layer_exported[layer] == 0) {
++			return n;
++		}
++
++		/*Do unexport.*/
++		info->layer_exported[layer] = 0;
++	}
++
++	return  n;
++}
++
++LAYER_DEVICE_ATTR(frame_size, S_IRUGO|S_IWUSR, NULL, store_frame_size);
++LAYER_DEVICE_ATTR(src_size, S_IRUGO|S_IWUSR, NULL, store_src_size);
++LAYER_DEVICE_ATTR(stride, S_IRUGO|S_IWUSR, NULL, store_stride);
++LAYER_DEVICE_ATTR(uv_stride, S_IRUGO|S_IWUSR, NULL, store_uv_stride);
++LAYER_DEVICE_ATTR(z_order, S_IRUGO|S_IWUSR, NULL, store_z_order);
++LAYER_DEVICE_ATTR(src_fmt, S_IRUGO|S_IWUSR, NULL, store_src_fmt);
++LAYER_DEVICE_ATTR(target_size, S_IRUGO|S_IWUSR, NULL, store_target_size);
++LAYER_DEVICE_ATTR(target_pos, S_IRUGO|S_IWUSR, NULL, store_target_pos);
++LAYER_DEVICE_ATTR(nframes, S_IRUGO|S_IWUSR, NULL, store_nframes);
++LAYER_DEVICE_ATTR(buf_addr, S_IRUGO|S_IWUSR, NULL, store_buf_addr);
++LAYER_DEVICE_ATTR(enable, S_IRUGO|S_IWUSR, NULL, store_enable);
++LAYER_DEVICE_ATTR(exportfb, S_IRUGO|S_IWUSR, show_exportfb, store_exportfb);
++
++
++#define LAYER_ATTRIBUTE_GROUP(name)                                     \
++        static struct attribute *comp_##name##_attrs[] = {               \
++		&dev_attr_frame_size##name.attr.attr,			\
++                &dev_attr_src_size##name.attr.attr,                     \
++                &dev_attr_stride##name.attr.attr,                     \
++                &dev_attr_uv_stride##name.attr.attr,                     \
++                &dev_attr_z_order##name.attr.attr,                     \
++                &dev_attr_src_fmt##name.attr.attr,                      \
++                &dev_attr_target_size##name.attr.attr,                  \
++                &dev_attr_target_pos##name.attr.attr,                   \
++                &dev_attr_nframes##name.attr.attr,                       \
++                &dev_attr_buf_addr##name.attr.attr,                       \
++                &dev_attr_enable##name.attr.attr,                       \
++                &dev_attr_exportfb##name.attr.attr,                       \
++                NULL,                                                   \
++        };
++
++
++LAYER_ATTRIBUTE_GROUP(layer0);
++LAYER_ATTRIBUTE_GROUP(layer1);
++LAYER_ATTRIBUTE_GROUP(layer2);
++LAYER_ATTRIBUTE_GROUP(layer3);
++
++static struct attribute_group comp_layer0_group = {
++                .name = "layer0",
++                .attrs = comp_layer0_attrs,
++};
++static struct attribute_group comp_layer1_group = {
++                .name = "layer1",
++                .attrs = comp_layer1_attrs,
++};
++static struct attribute_group comp_layer2_group = {
++                .name = "layer2",
++                .attrs = comp_layer2_attrs,
++};
++static struct attribute_group comp_layer3_group = {
++                .name = "layer3",
++                .attrs = comp_layer3_attrs,
++};
++
++static struct attribute *comp_wback_attrs[] = {
++#if 0
++	&dev_attr_wback_framesize.attr,
++	&dev_attr_wback_fmt.attr,
++	&dev_attr_wback_enable.attr,
++	&dev_attr_wback_export.attr,
++#endif
++        NULL,
++};
++
++static struct attribute_group comp_wback_group = {
++	.name = "wback",
++	.attrs = comp_wback_attrs,
++};
++
++static const struct attribute_group *comp_groups[] = {
++        &comp_layer0_group,
++        &comp_layer1_group,
++        &comp_layer2_group,
++        &comp_layer3_group,
++	&comp_wback_group,
++        NULL,
++};
++
++
++
++static ssize_t show_comp_exportfbs(struct device *dev,
++                struct device_attribute *attr, char *buf)
++{
++	return 0;
++}
++static ssize_t store_comp_exportfbs(struct device *dev,
++                struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct hw_compfb_device *compfb = sysfs_get_compfb(dev);
++	struct export_info *info = &compfb->export_info;
++	int ret = 0;
++
++	int export = simple_strtoul(buf, NULL, 0);
++
++	if(export == 1) {
++		ret = hw_compfb_export2(compfb, info);
++		if(ret < 0) {
++			return ret;
++		}
++	} else {
++		hw_compfb_unexport(compfb);
++	}
++
++	return n;
++}
++
++static ssize_t store_comp_update(struct device *dev,
++                struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct hw_compfb_device *compfb = sysfs_get_compfb(dev);
++	struct export_info *info = &compfb->export_info;
++	int ret = 0;
++
++	ret = hw_compfb_update(compfb);
++
++	return n;
++}
++
++
++static ssize_t store_rdma_destroy(struct device *dev,
++                struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct ingenicfb_device *fbdev = sysfs_get_fbdev(dev);
++	struct dpu_ctrl *dctrl = sysfs_get_dctrl(dev);
++	struct hw_compfb_device *compfb = sysfs_get_compfb(dev);
++	struct export_info *info = &compfb->export_info;
++	int ret = 0;
++	int value = simple_strtoul(buf, NULL, 0);
++
++	if(value != 1) {
++		return -EINVAL;
++	}
++
++	ret = dpu_ctrl_try_rdma_release(dctrl);
++	if(ret < 0) {
++		return ret;
++	}
++
++#if 0
++	unregister_framebuffer(fbdev->fb);
++	framebuffer_release(fbdev->fb);
++	fbdev->fb = NULL;
++#endif
++	ingenicfb_release_vidmem(fbdev);
++	return n;
++}
++
++static DEVICE_ATTR(comp_exportfbs, S_IRUGO|S_IWUSR, show_comp_exportfbs, store_comp_exportfbs);
++static DEVICE_ATTR(comp_update, S_IRUGO|S_IWUSR, show_comp_exportfbs, store_comp_update);
++static DEVICE_ATTR(rdma_destroy, S_IWUSR, NULL, store_rdma_destroy);
++
++static int of_sysfs_parse_export_info(struct hw_compfb_device *compfb)
++{
++	struct device_node *np = compfb->dev->of_node;
++	struct export_info *info = &compfb->export_info;
++	struct ingenicfb_frm_cfg *frm_cfg = &info->frm_cfg;
++	unsigned int value[8];
++	int ret = 0;
++	unsigned int comp_fb = 0;
++	int i = 0;
++
++	if(of_property_read_u32_array(np, "ingenic,layer-exported", info->layer_exported, 4) < 0) {
++		info->layer_exported[0] = 0;
++		info->layer_exported[1] = 0;
++		info->layer_exported[2] = 0;
++		info->layer_exported[3] = 0;
++	}
++
++	if(of_property_read_u32_array(np, "ingenic,layer-frames", info->layer_frames, 4) < 0) {
++		info->layer_frames[0] = 1;
++		info->layer_frames[1] = 1;
++		info->layer_frames[2] = 1;
++		info->layer_frames[3] = 1;
++	}
++
++	if(of_property_read_u32_array(np, "layer,color_mode", info->layer_color_mode, 4) < 0) {
++		info->layer_color_mode[0] = 0;
++		info->layer_color_mode[1] = 0;
++		info->layer_color_mode[2] = 0;
++		info->layer_color_mode[3] = 0;
++	}
++
++
++	ret = of_property_read_u32_array(np, "layer,src-size", value, 8);
++	if(ret == 0) {
++		for(i = 0; i < 4; i++) {
++			struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[i];
++
++			lay_cfg->source_w = value[i*2 + 0];
++			lay_cfg->source_h = value[i*2 + 1];
++		}
++	}
++
++	ret = of_property_read_u32_array(np, "layer,stride", value, 4);
++	if(ret == 0) {
++		for(i = 0; i < 4; i++) {
++			struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[i];
++
++			lay_cfg->stride = value[i];
++		}
++	} else {
++		for(i = 0; i < 4; i++) {
++			struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[i];
++			lay_cfg->stride = lay_cfg->source_w;
++		}
++	}
++
++	ret = of_property_read_u32_array(np, "layer,uv_stride", value, 4);
++	if(ret == 0) {
++		for(i = 0; i < 4; i++) {
++			struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[i];
++
++			lay_cfg->uv_stride = value[i];
++		}
++	} else {
++		for(i = 0; i < 4; i++) {
++			struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[i];
++			lay_cfg->uv_stride = lay_cfg->source_w;
++		}
++	}
++
++	ret = of_property_read_u32_array(np, "layer,z_order", value, 4);
++	if(ret == 0) {
++		for(i = 0; i < 4; i++) {
++			struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[i];
++
++			lay_cfg->lay_z_order = value[i];
++		}
++	} else {
++		for(i = 0; i < 4; i++) {
++			struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[i];
++			lay_cfg->lay_z_order = LAYER_Z_ORDER_3 - i;
++		}
++	}
++
++	ret = of_property_read_u32_array(np, "ingenic,layer-framesize", value, 8);
++	if(ret == 0) {
++		for(i = 0; i < 4; i++) {
++			info->layer_frame_size_w[i] = value[i*2 + 0];
++			info->layer_frame_size_h[i] = value[i*2 + 1];
++		}
++	} else {
++		for(i = 0; i < 4; i++) {
++			struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[i];
++			info->layer_frame_size_w[i] = lay_cfg->source_w;
++			info->layer_frame_size_h[i] = lay_cfg->source_h;
++		}
++
++	}
++
++	ret = of_property_read_u32_array(np, "layer,target-size", value, 8);
++	if(ret == 0) {
++		for(i = 0; i < 4; i++) {
++			struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[i];
++
++			lay_cfg->scale_w = value[i*2 + 0];
++			lay_cfg->scale_h = value[i*2 + 1];
++		}
++	}
++
++	ret = of_property_read_u32_array(np, "layer,target-pos", value, 8);
++	if(ret == 0) {
++		for(i = 0; i < 4; i++) {
++			struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[i];
++
++			lay_cfg->disp_pos_x = value[i*2 + 0];
++			lay_cfg->disp_pos_y = value[i*2 + 1];
++		}
++	}
++
++	ret = of_property_read_u32_array(np, "layer,enable", value, 4);
++	if(ret == 0) {
++		for(i = 0; i < 4; i++) {
++			struct ingenicfb_lay_cfg *lay_cfg = &frm_cfg->lay_cfg[i];
++			lay_cfg->lay_en = info->layer_exported[i] ? value[i] : 0;
++		}
++	}
++
++
++
++	of_property_read_u32(np, "ingenic,logo-pan-layer", &compfb->logo_pan_layer);
++
++	return 0;
++}
++
++int dpu_sysfs_init(struct dpu_sysfs *sysfs, struct dpu_ctrl *dctrl, struct hw_compfb_device *compfb)
++{
++	int ret = 0;
++	struct export_info *info = &compfb->export_info;
++	int export = 0;
++	int i = 0;
++
++	sysfs->dctrl = dctrl;
++	sysfs->compfb = compfb;
++
++	/*1. create debug group.*/
++	ret = sysfs_create_group(&dctrl->dev->kobj, &lcd_debug_attr_group);
++	if (ret) {
++		dev_err(dctrl->dev, "device create sysfs group failed\n");
++		ret = -EINVAL;
++	}
++	if(dctrl->support_comp) {
++		/*2. create comp group.*/
++		ret = sysfs_create_groups(&dctrl->dev->kobj, comp_groups);
++		if(ret) {
++			dev_err(dctrl->dev, "Failed to create sysfs groups\n");
++		}
++
++		/*3. comp controller*/
++		ret = device_create_file(dctrl->dev, &dev_attr_comp_exportfbs);
++		if(ret) {
++			dev_err(dctrl->dev, "Failed to create comp_exportfbs\n");
++		}
++
++		ret = device_create_file(dctrl->dev, &dev_attr_comp_update);
++		if(ret) {
++			dev_err(dctrl->dev, "Failed to create comp_update\n");
++		}
++	}
++	ret = device_create_file(dctrl->dev, &dev_attr_rdma_destroy);
++	if(ret) {
++		dev_err(dctrl->dev, "Failed to create rdma_destroy\n");
++	}
++
++	if(dctrl->support_comp) {
++		of_sysfs_parse_export_info(compfb);
++		for(i = 0; i < DPU_SUPPORT_MAX_LAYERS; i++) {
++			if(info->layer_exported[i] == 1) {
++				export = 1;
++				break;
++			}
++		}
++	}
++
++	/*Try to export compfb at init stage if dts has set export values.*/
++	if(export) {
++		ret = hw_compfb_export2(compfb, info);
++		if(ret < 0) {
++			dev_err(compfb->dev, "Failed to export composer fbs.\n");
++			goto err_export;
++		}
++
++		pan_init_logo(compfb->fbs[compfb->logo_pan_layer]);
++
++#if 0
++		pan_init_logo(compfb->fbs[1]);
++		pan_init_logo(compfb->fbs[2]);
++		pan_init_logo(compfb->fbs[3]);
++#endif
++		ret = hw_compfb_update(compfb);
++		if(ret < 0) {
++			dev_err(compfb->dev, "failed to update composer!\n");
++		}
++	}
++
++	return ret;
++err_export:
++	return ret;
++}
++
++
++int dpu_sysfs_exit(struct dpu_sysfs *sysfs)
++{
++	struct dpu_ctrl *dctrl = sysfs->dctrl;
++	struct hw_compfb_device *compfb = sysfs->compfb;
++	int ret = 0;
++
++	if(dctrl->support_comp)
++		hw_compfb_unexport(compfb);
++
++	device_remove_file(dctrl->dev, &dev_attr_rdma_destroy);
++
++	if(dctrl->support_comp) {
++		device_remove_file(dctrl->dev, &dev_attr_comp_update);
++		device_remove_file(dctrl->dev, &dev_attr_comp_exportfbs);
++		sysfs_remove_groups(&dctrl->dev->kobj, comp_groups);
++	}
++
++	sysfs_remove_group(&dctrl->dev->kobj, &lcd_debug_attr_group);
++
++	return ret;
++}
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/sysfs.h b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/sysfs.h
+new file mode 100644
+index 000000000..78ba00751
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/sysfs.h
+@@ -0,0 +1,45 @@
++#ifndef __DPU_SYSFS_H__
++#define __DPU_SYSFS_H__
++
++#include <linux/kernel.h>
++#include <linux/device.h>
++#include <linux/sysfs.h>
++
++
++struct dpu_sysfs {
++
++	struct dpu_ctrl *dctrl;
++	struct hw_compfb_device *compfb;
++
++};
++
++struct layer_device_attr {
++        struct device_attribute attr;
++        unsigned int id;
++};
++
++#define to_layer_attr(attr)     \
++        container_of(attr, struct layer_device_attr, attr)
++
++
++#define LAYER_ATTR(layer, _name, _mode, _show, _store)          \
++        {                                                       \
++        .attr   = __ATTR(_name, _mode, _show, _store),  \
++        .id     = layer,                                                \
++        }
++
++
++#define LAYER_DEVICE_ATTR(_name, _mode, _show, _store)                                                    \
++        static struct layer_device_attr dev_attr_##_name##layer0 = LAYER_ATTR(0, _name, _mode, _show, _store); \
++        static struct layer_device_attr dev_attr_##_name##layer1 = LAYER_ATTR(1, _name, _mode, _show, _store); \
++        static struct layer_device_attr dev_attr_##_name##layer2 = LAYER_ATTR(2, _name, _mode, _show, _store); \
++        static struct layer_device_attr dev_attr_##_name##layer3 = LAYER_ATTR(3, _name, _mode, _show, _store)
++
++
++int dpu_sysfs_init(struct dpu_sysfs *sysfs, struct dpu_ctrl *dctrl, struct hw_compfb_device *compfb);
++
++
++int dpu_sysfs_exit(struct dpu_sysfs *sysfs);
++
++
++#endif
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/todo/colorbar.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/todo/colorbar.c
+new file mode 100644
+index 000000000..e3c7a10cb
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/todo/colorbar.c
+@@ -0,0 +1,247 @@
++
++static void __maybe_unused ingenicfb_display_sread_v_color_bar(struct fb_info *info)
++{
++	int i, j;
++	int w, h;
++	int bpp;
++	unsigned short *p16;
++	unsigned int *p32;
++	struct ingenicfb_device *fbdev = info->par;
++	struct fb_videomode *mode = fbdev->panel->modes;
++
++
++	if (!mode) {
++		dev_err(fbdev->dev, "%s, video mode is NULL\n", __func__);
++		return;
++	}
++
++	p16 = (unsigned short *)fbdev->sread_vidmem[0];
++	p32 = (unsigned int *)fbdev->sread_vidmem[0];
++	w = mode->xres;
++	h = mode->yres;
++	bpp = info->var.bits_per_pixel;
++
++
++	for (i = 0; i < h; i++) {
++		for (j = 0; j < w; j++) {
++			short c16;
++			int c32 = 0;
++			switch ((j / 10) % 4) {
++				case 0:
++					c16 = 0xF800;
++					c32 = 0xFFFF0000;
++					break;
++				case 1:
++					c16 = 0x07C0;
++					c32 = 0xFF00FF00;
++					break;
++				case 2:
++					c16 = 0x001F;
++					c32 = 0xFF0000FF;
++					break;
++				default:
++					c16 = 0xFFFF;
++					c32 = 0xFFFFFFFF;
++					break;
++			}
++			switch (bpp) {
++				case 18:
++				case 24:
++				case 32:
++					*p32++ = c32;
++					break;
++				default:
++					*p16++ = c16;
++			}
++		}
++		if (w % PIXEL_ALIGN) {
++			switch (bpp) {
++				case 18:
++				case 24:
++				case 32:
++					p32 += (ALIGN(mode->xres, PIXEL_ALIGN) - w);
++					break;
++				default:
++					p16 += (ALIGN(mode->xres, PIXEL_ALIGN) - w);
++					break;
++			}
++		}
++	}
++}
++
++static void ingenicfb_display_v_color_bar(struct fb_info *info)
++{
++	int i, j;
++	int w, h;
++	int bpp;
++	unsigned short *p16;
++	unsigned int *p32;
++	struct ingenicfb_device *fbdev = info->par;
++	struct fb_videomode *mode = fbdev->panel->modes;
++
++	if (!mode) {
++		dev_err(fbdev->dev, "%s, video mode is NULL\n", __func__);
++		return;
++	}
++	if (!fbdev->vidmem_phys[fbdev->current_frm_desc][0]) {
++		dev_err(fbdev->dev, "Not allocate frame buffer yet\n");
++		return;
++	}
++	if (!fbdev->vidmem[fbdev->current_frm_desc][0])
++		fbdev->vidmem[fbdev->current_frm_desc][0] =
++			(void *)phys_to_virt(fbdev->vidmem_phys[fbdev->current_frm_desc][0]);
++	p16 = (unsigned short *)fbdev->vidmem[fbdev->current_frm_desc][0];
++	p32 = (unsigned int *)fbdev->vidmem[fbdev->current_frm_desc][0];
++	w = mode->xres;
++	h = mode->yres;
++	bpp = info->var.bits_per_pixel;
++
++	dev_info(info->dev,
++			"LCD V COLOR BAR w,h,bpp(%d,%d,%d) fbdev->vidmem[0]=%p\n", w, h,
++			bpp, fbdev->vidmem[fbdev->current_frm_desc][0]);
++
++	for (i = 0; i < h; i++) {
++		for (j = 0; j < w; j++) {
++			short c16;
++			int c32 = 0;
++			switch ((j / 10) % 4) {
++				case 0:
++					c16 = 0xF800;
++					c32 = 0xFFFF0000;
++					break;
++				case 1:
++					c16 = 0x07C0;
++					c32 = 0xFF00FF00;
++					break;
++				case 2:
++					c16 = 0x001F;
++					c32 = 0xFF0000FF;
++					break;
++				default:
++					c16 = 0xFFFF;
++					c32 = 0xFFFFFFFF;
++					break;
++			}
++			switch (bpp) {
++				case 18:
++				case 24:
++				case 32:
++					*p32++ = c32;
++					break;
++				default:
++					*p16++ = c16;
++			}
++		}
++		if (w % PIXEL_ALIGN) {
++			switch (bpp) {
++				case 18:
++				case 24:
++				case 32:
++					p32 += (ALIGN(mode->xres, PIXEL_ALIGN) - w);
++					break;
++				default:
++					p16 += (ALIGN(mode->xres, PIXEL_ALIGN) - w);
++					break;
++			}
++		}
++	}
++}
++
++static void ingenicfb_display_h_color_bar(struct fb_info *info)
++{
++	int i, j;
++	int w, h;
++	int bpp;
++	unsigned short *p16;
++	unsigned int *p32;
++	struct ingenicfb_device *fbdev = info->par;
++	struct fb_videomode *mode = fbdev->panel->modes;
++
++	if (!mode) {
++		dev_err(fbdev->dev, "%s, video mode is NULL\n", __func__);
++		return;
++	}
++	if (!fbdev->vidmem_phys[fbdev->current_frm_desc][0]) {
++		dev_err(fbdev->dev, "Not allocate frame buffer yet\n");
++		return;
++	}
++	if (!fbdev->vidmem[fbdev->current_frm_desc][0])
++		fbdev->vidmem[fbdev->current_frm_desc][0] =
++			(void *)phys_to_virt(fbdev->vidmem_phys[fbdev->current_frm_desc][0]);
++	p16 = (unsigned short *)fbdev->vidmem[fbdev->current_frm_desc][0];
++	p32 = (unsigned int *)fbdev->vidmem[fbdev->current_frm_desc][0];
++	w = mode->xres;
++	h = mode->yres;
++	bpp = info->var.bits_per_pixel;
++
++	dev_info(info->dev,
++			"LCD H COLOR BAR w,h,bpp(%d,%d,%d), fbdev->vidmem[0]=%p\n", w, h,
++			bpp, fbdev->vidmem[fbdev->current_frm_desc][0]);
++
++	for (i = 0; i < h; i++) {
++		for (j = 0; j < w; j++) {
++			short c16;
++			int c32;
++			switch ((i / 10) % 4) {
++				case 0:
++					c16 = 0xF800;
++					c32 = 0x00FF0000;
++					break;
++				case 1:
++					c16 = 0x07C0;
++					c32 = 0x0000FF00;
++					break;
++				case 2:
++					c16 = 0x001F;
++					c32 = 0x000000FF;
++					break;
++				default:
++					c16 = 0xFFFF;
++					c32 = 0xFFFFFFFF;
++					break;
++			}
++			switch (bpp) {
++				case 18:
++				case 24:
++				case 32:
++					*p32++ = c32;
++					break;
++				default:
++					*p16++ = c16;
++			}
++		}
++		if (w % PIXEL_ALIGN) {
++			switch (bpp) {
++				case 18:
++				case 24:
++				case 32:
++					p32 += (ALIGN(mode->xres, PIXEL_ALIGN) - w);
++					break;
++				default:
++					p16 += (ALIGN(mode->xres, PIXEL_ALIGN) - w);
++					break;
++			}
++		}
++	}
++}
++
++int test_pattern(struct ingenicfb_device *fbdev)
++{
++	int ret;
++
++	ingenicfb_disable(fbdev->fb, QCK_STOP);
++	ingenicfb_display_h_color_bar(fbdev->fb);
++	//ingenicfb_display_sread_v_color_bar(fbdev->fb);
++	fbdev->current_frm_desc = 0;
++	ingenicfb_set_fix_par(fbdev->fb);
++	ret = ingenicfb_set_par(fbdev->fb);
++	if(ret) {
++		dev_err(fbdev->dev, "Set par failed!\n");
++		return ret;
++	}
++	ingenicfb_enable(fbdev->fb);
++
++	return 0;
++}
++
++
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/todo/sysfs.c b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/todo/sysfs.c
+new file mode 100644
+index 000000000..7977b7330
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/todo/sysfs.c
+@@ -0,0 +1,1259 @@
++
++static void dump_dc_reg(void)
++{
++	printk("-----------------dc_reg------------------\n");
++	printk("DC_FRM_CFG_ADDR(0x%04x):    0x%08lx\n", DC_FRM_CFG_ADDR,reg_read(fbdev, DC_FRM_CFG_ADDR));
++	printk("DC_FRM_CFG_CTRL(0x%04x):    0x%08lx\n", DC_FRM_CFG_CTRL,reg_read(fbdev, DC_FRM_CFG_CTRL));
++	printk("DC_CTRL(0x%04x):            0x%08lx\n", DC_CTRL, reg_read(fbdev, DC_CTRL));
++	printk("DC_CSC_MULT_YRV(0x%04x):    0x%08lx\n", DC_CSC_MULT_YRV,reg_read(fbdev, DC_CSC_MULT_YRV));
++	printk("DC_CSC_MULT_GUGV(0x%04x):   0x%08lx\n", DC_CSC_MULT_GUGV,reg_read(fbdev, DC_CSC_MULT_GUGV));
++	printk("DC_CSC_MULT_BU(0x%04x):     0x%08lx\n", DC_CSC_MULT_BU,reg_read(fbdev, DC_CSC_MULT_BU));
++	printk("DC_CSC_SUB_YUV(0x%04x):     0x%08lx\n", DC_CSC_SUB_YUV,reg_read(fbdev, DC_CSC_SUB_YUV));
++	printk("DC_ST(0x%04x):              0x%08lx\n", DC_ST, reg_read(fbdev, DC_ST));
++	printk("DC_INTC(0x%04x):            0x%08lx\n", DC_INTC, reg_read(fbdev, DC_INTC));
++	printk("DC_INT_FLAG(0x%04x):	   0x%08lx\n", DC_INT_FLAG, reg_read(fbdev, DC_INT_FLAG));
++	printk("DC_COM_CONFIG(0x%04x):      0x%08lx\n", DC_COM_CONFIG ,reg_read(fbdev, DC_COM_CONFIG));
++	printk("DC_TLB_GLBC(0x%04x):        0x%08lx\n", DC_TLB_GLBC,reg_read(fbdev, DC_TLB_GLBC));
++	printk("DC_TLB_TLBA(0x%04x):        0x%08lx\n", DC_TLB_TLBA,reg_read(fbdev, DC_TLB_TLBA));
++	printk("DC_TLB_TLBC(0x%04x):        0x%08lx\n", DC_TLB_TLBC,reg_read(fbdev, DC_TLB_TLBC));
++	printk("DC_TLB0_VPN(0x%04x):        0x%08lx\n", DC_TLB0_VPN,reg_read(fbdev, DC_TLB0_VPN));
++	printk("DC_TLB1_VPN(0x%04x):        0x%08lx\n", DC_TLB1_VPN,reg_read(fbdev, DC_TLB1_VPN));
++	printk("DC_TLB2_VPN(0x%04x):        0x%08lx\n", DC_TLB2_VPN,reg_read(fbdev, DC_TLB2_VPN));
++	printk("DC_TLB3_VPN(0x%04x):        0x%08lx\n", DC_TLB3_VPN,reg_read(fbdev, DC_TLB3_VPN));
++	printk("DC_TLB_TLBV(0x%04x):        0x%08lx\n", DC_TLB_TLBV,reg_read(fbdev, DC_TLB_TLBV));
++	printk("DC_TLB_STAT(0x%04x):        0x%08lx\n", DC_TLB_STAT,reg_read(fbdev, DC_TLB_STAT));
++	printk("DC_PCFG_RD_CTRL(0x%04x):    0x%08lx\n", DC_PCFG_RD_CTRL,reg_read(fbdev, DC_PCFG_RD_CTRL));
++	printk("DC_PCFG_WR_CTRL(0x%04x):    0x%08lx\n", DC_PCFG_WR_CTRL,reg_read(fbdev, DC_PCFG_WR_CTRL));
++	printk("DC_OFIFO_PCFG(0x%04x):	   0x%08lx\n", DC_OFIFO_PCFG,reg_read(fbdev, DC_OFIFO_PCFG));
++	printk("DC_WDMA_PCFG(0x%04x):	   0x%08lx\n", DC_WDMA_PCFG,reg_read(fbdev, DC_WDMA_PCFG));
++	printk("DC_CMPW_PCFG_CTRL(0x%04x): 0x%08lx\n", DC_CMPW_PCFG_CTRL,reg_read(fbdev, DC_CMPW_PCFG_CTRL));
++	printk("DC_CMPW_PCFG0(0x%04x):	   0x%08lx\n", DC_CMPW_PCFG0,reg_read(fbdev, DC_CMPW_PCFG0));
++	printk("DC_CMPW_PCFG1(0x%04x):	   0x%08lx\n", DC_CMPW_PCFG1,reg_read(fbdev, DC_CMPW_PCFG1));
++	printk("DC_CMPW_PCFG2(0x%04x):	   0x%08lx\n", DC_CMPW_PCFG2,reg_read(fbdev, DC_CMPW_PCFG2));
++	printk("DC_PCFG_RD_CTRL(0x%04x):    0x%08lx\n", DC_PCFG_RD_CTRL,reg_read(fbdev, DC_PCFG_RD_CTRL));
++	printk("DC_OFIFO_PCFG(0x%04x):	   0x%08lx\n", DC_OFIFO_PCFG,reg_read(fbdev, DC_OFIFO_PCFG));
++	printk("DC_DISP_COM(0x%04x):        0x%08lx\n", DC_DISP_COM,reg_read(fbdev, DC_DISP_COM));
++	printk("-----------------dc_reg------------------\n");
++}
++
++static void dump_tft_reg(void)
++{
++	printk("----------------tft_reg------------------\n");
++	printk("TFT_TIMING_HSYNC(0x%04x):   0x%08lx\n", DC_TFT_HSYNC, reg_read(fbdev, DC_TFT_HSYNC));
++	printk("TFT_TIMING_VSYNC(0x%04x):   0x%08lx\n", DC_TFT_VSYNC, reg_read(fbdev, DC_TFT_VSYNC));
++	printk("TFT_TIMING_HDE(0x%04x):     0x%08lx\n", DC_TFT_HDE, reg_read(fbdev, DC_TFT_HDE));
++	printk("TFT_TIMING_VDE(0x%04x):     0x%08lx\n", DC_TFT_VDE, reg_read(fbdev, DC_TFT_VDE));
++	printk("TFT_TRAN_CFG(0x%04x):       0x%08lx\n", DC_TFT_CFG, reg_read(fbdev, DC_TFT_CFG));
++	printk("TFT_ST(0x%04x):             0x%08lx\n", DC_TFT_ST, reg_read(fbdev, DC_TFT_ST));
++	printk("----------------tft_reg------------------\n");
++}
++
++static void dump_slcd_reg(void)
++{
++	printk("---------------slcd_reg------------------\n");
++	printk("SLCD_CFG(0x%04x):           0x%08lx\n", DC_SLCD_CFG, reg_read(fbdev, DC_SLCD_CFG));
++	printk("SLCD_WR_DUTY(0x%04x):       0x%08lx\n", DC_SLCD_WR_DUTY, reg_read(fbdev, DC_SLCD_WR_DUTY));
++	printk("SLCD_TIMING(0x%04x):        0x%08lx\n", DC_SLCD_TIMING, reg_read(fbdev, DC_SLCD_TIMING));
++	printk("SLCD_FRM_SIZE(0x%04x):      0x%08lx\n", DC_SLCD_FRM_SIZE, reg_read(fbdev, DC_SLCD_FRM_SIZE));
++	printk("SLCD_SLOW_TIME(0x%04x):     0x%08lx\n", DC_SLCD_SLOW_TIME, reg_read(fbdev, DC_SLCD_SLOW_TIME));
++	printk("SLCD_REG_IF(0x%04x):	    0x%08lx\n", DC_SLCD_REG_IF, reg_read(fbdev, DC_SLCD_REG_IF));
++	printk("SLCD_ST(0x%04x):            0x%08lx\n", DC_SLCD_ST, reg_read(fbdev, DC_SLCD_ST));
++	printk("---------------slcd_reg------------------\n");
++}
++
++static void dump_frm_desc_reg(void)
++{
++	unsigned int ctrl;
++	ctrl = reg_read(fbdev, DC_CTRL);
++	ctrl |= DC_DES_CNT_RST;
++	reg_write(fbdev, DC_CTRL, ctrl);
++
++	printk("--------Frame Descriptor register--------\n");
++	printk("FrameNextCfgAddr:   %lx\n",reg_read(fbdev, DC_FRM_DES));
++	printk("FrameSize:          %lx\n",reg_read(fbdev, DC_FRM_DES));
++	printk("FrameCtrl:          %lx\n",reg_read(fbdev, DC_FRM_DES));
++	printk("WritebackAddr:      %lx\n",reg_read(fbdev, DC_FRM_DES));
++	printk("WritebackStride:    %lx\n",reg_read(fbdev, DC_FRM_DES));
++	printk("Layer0CfgAddr:      %lx\n",reg_read(fbdev, DC_FRM_DES));
++	printk("Layer1CfgAddr:      %lx\n",reg_read(fbdev, DC_FRM_DES));
++	printk("Layer2CfgAddr:      %lx\n",reg_read(fbdev, DC_FRM_DES));
++	printk("Layer3CfgAddr:      %lx\n",reg_read(fbdev, DC_FRM_DES));
++	printk("LayCfgEn:	    %lx\n",reg_read(fbdev, DC_FRM_DES));
++	printk("InterruptControl:   %lx\n",reg_read(fbdev, DC_FRM_DES));
++	printk("--------Frame Descriptor register--------\n");
++}
++
++static void dump_layer_desc_reg(void)
++{
++	unsigned int ctrl;
++	ctrl = reg_read(fbdev, DC_CTRL);
++	ctrl |= DC_DES_CNT_RST;
++	reg_write(fbdev, DC_CTRL, ctrl);
++
++	printk("--------layer0 Descriptor register-------\n");
++	printk("LayerSize:          %lx\n",reg_read(fbdev, DC_LAY0_DES));
++	printk("LayerCfg:           %lx\n",reg_read(fbdev, DC_LAY0_DES));
++	printk("LayerBufferAddr:    %lx\n",reg_read(fbdev, DC_LAY0_DES));
++	printk("LayerScale:         %lx\n",reg_read(fbdev, DC_LAY0_DES));
++	printk("LayerRotation:      %lx\n",reg_read(fbdev, DC_LAY0_DES));
++	printk("LayerScratch:       %lx\n",reg_read(fbdev, DC_LAY0_DES));
++	printk("LayerPos:           %lx\n",reg_read(fbdev, DC_LAY0_DES));
++	printk("LayerResizeCoef_X:  %lx\n",reg_read(fbdev, DC_LAY0_DES));
++	printk("LayerResizeCoef_Y:  %lx\n",reg_read(fbdev, DC_LAY0_DES));
++	printk("LayerStride:        %lx\n",reg_read(fbdev, DC_LAY0_DES));
++//	printk("Layer_UV_addr:	    %lx\n",reg_read(fbdev, DC_LAY0_DES));
++//	printk("Layer_UV_stride:    %lx\n",reg_read(fbdev, DC_LAY0_DES));
++	printk("--------layer0 Descriptor register-------\n");
++
++	printk("--------layer1 Descriptor register-------\n");
++	printk("LayerSize:          %lx\n",reg_read(fbdev, DC_LAY1_DES));
++	printk("LayerCfg:           %lx\n",reg_read(fbdev, DC_LAY1_DES));
++	printk("LayerBufferAddr:    %lx\n",reg_read(fbdev, DC_LAY1_DES));
++	printk("LayerScale:         %lx\n",reg_read(fbdev, DC_LAY1_DES));
++	printk("LayerRotation:      %lx\n",reg_read(fbdev, DC_LAY1_DES));
++	printk("LayerScratch:       %lx\n",reg_read(fbdev, DC_LAY1_DES));
++	printk("LayerPos:           %lx\n",reg_read(fbdev, DC_LAY1_DES));
++	printk("LayerResizeCoef_X:  %lx\n",reg_read(fbdev, DC_LAY1_DES));
++	printk("LayerResizeCoef_Y:  %lx\n",reg_read(fbdev, DC_LAY1_DES));
++	printk("LayerStride:        %lx\n",reg_read(fbdev, DC_LAY1_DES));
++//	printk("Layer_UV_addr:	    %lx\n",reg_read(fbdev, DC_LAY1_DES));
++//	printk("Layer_UV_stride:    %lx\n",reg_read(fbdev, DC_LAY1_DES));
++	printk("--------layer1 Descriptor register-------\n");
++
++	printk("--------layer2 Descriptor register-------\n");
++	printk("LayerSize:          %lx\n",reg_read(fbdev, DC_LAY2_DES));
++	printk("LayerCfg:           %lx\n",reg_read(fbdev, DC_LAY2_DES));
++	printk("LayerBufferAddr:    %lx\n",reg_read(fbdev, DC_LAY2_DES));
++	printk("LayerScale:         %lx\n",reg_read(fbdev, DC_LAY2_DES));
++	printk("LayerRotation:      %lx\n",reg_read(fbdev, DC_LAY2_DES));
++	printk("LayerScratch:       %lx\n",reg_read(fbdev, DC_LAY2_DES));
++	printk("LayerPos:           %lx\n",reg_read(fbdev, DC_LAY2_DES));
++	printk("LayerResizeCoef_X:  %lx\n",reg_read(fbdev, DC_LAY2_DES));
++	printk("LayerResizeCoef_Y:  %lx\n",reg_read(fbdev, DC_LAY2_DES));
++	printk("LayerStride:        %lx\n",reg_read(fbdev, DC_LAY2_DES));
++//	printk("Layer_UV_addr:	    %lx\n",reg_read(fbdev, DC_LAY2_DES));
++//	printk("Layer_UV_stride:    %lx\n",reg_read(fbdev, DC_LAY2_DES));
++	printk("--------layer2 Descriptor register-------\n");
++
++	printk("--------layer3 Descriptor register-------\n");
++	printk("LayerSize:          %lx\n",reg_read(fbdev, DC_LAY3_DES));
++	printk("LayerCfg:           %lx\n",reg_read(fbdev, DC_LAY3_DES));
++	printk("LayerBufferAddr:    %lx\n",reg_read(fbdev, DC_LAY3_DES));
++	printk("LayerScale:         %lx\n",reg_read(fbdev, DC_LAY3_DES));
++	printk("LayerRotation:      %lx\n",reg_read(fbdev, DC_LAY3_DES));
++	printk("LayerScratch:       %lx\n",reg_read(fbdev, DC_LAY3_DES));
++	printk("LayerPos:           %lx\n",reg_read(fbdev, DC_LAY3_DES));
++	printk("LayerResizeCoef_X:  %lx\n",reg_read(fbdev, DC_LAY3_DES));
++	printk("LayerResizeCoef_Y:  %lx\n",reg_read(fbdev, DC_LAY3_DES));
++	printk("LayerStride:        %lx\n",reg_read(fbdev, DC_LAY3_DES));
++//	printk("Layer_UV_addr:	    %lx\n",reg_read(fbdev, DC_LAY3_DES));
++//	printk("Layer_UV_stride:    %lx\n",reg_read(fbdev, DC_LAY3_DES));
++	printk("--------layer3 Descriptor register-------\n");
++}
++
++static void dump_rdma_desc_reg(void)
++{
++	unsigned int ctrl;
++	  ctrl = reg_read(fbdev, DC_CTRL);
++	  ctrl |= (1 << 2);
++	  reg_write(fbdev, DC_CTRL, ctrl);
++	printk("====================rdma Descriptor register======================\n");
++	printk("RdmaNextCfgAddr:    %lx\n",reg_read(fbdev, DC_RDMA_DES));
++	printk("FrameBufferAddr:    %lx\n",reg_read(fbdev, DC_RDMA_DES));
++	printk("Stride:             %lx\n",reg_read(fbdev, DC_RDMA_DES));
++	printk("ChainCfg:           %lx\n",reg_read(fbdev, DC_RDMA_DES));
++	printk("InterruptControl:   %lx\n",reg_read(fbdev, DC_RDMA_DES));
++	printk("==================rdma Descriptor register end======================\n");
++}
++
++
++static void dump_frm_desc(struct ingenicfb_framedesc *framedesc, int index)
++{
++	printk("-------User Frame Descriptor index[%d]-----\n", index);
++	printk("FramedescAddr:	    0x%x\n",(uint32_t)framedesc);
++	printk("FrameNextCfgAddr:   0x%x\n",framedesc->FrameNextCfgAddr);
++	printk("FrameSize:          0x%x\n",framedesc->FrameSize.d32);
++	printk("FrameCtrl:          0x%x\n",framedesc->FrameCtrl.d32);
++	printk("Layer0CfgAddr:      0x%x\n",framedesc->Layer0CfgAddr);
++	printk("Layer1CfgAddr:      0x%x\n",framedesc->Layer1CfgAddr);
++	printk("LayerCfgEn:	    0x%x\n",framedesc->LayCfgEn.d32);
++	printk("InterruptControl:   0x%x\n",framedesc->InterruptControl.d32);
++	printk("-------User Frame Descriptor index[%d]-----\n", index);
++}
++
++static void dump_layer_desc(struct ingenicfb_layerdesc *layerdesc, int row, int col)
++{
++	printk("------User layer Descriptor index[%d][%d]------\n", row, col);
++	printk("LayerdescAddr:	    0x%x\n",(uint32_t)layerdesc);
++	printk("LayerSize:          0x%x\n",layerdesc->LayerSize.d32);
++	printk("LayerCfg:           0x%x\n",layerdesc->LayerCfg.d32);
++	printk("LayerBufferAddr:    0x%x\n",layerdesc->LayerBufferAddr);
++	printk("LayerScale:         0x%x\n",layerdesc->LayerScale.d32);
++	printk("LayerResizeCoef_X:  0x%x\n",layerdesc->layerresizecoef_x);
++	printk("LayerResizeCoef_Y:  0x%x\n",layerdesc->layerresizecoef_y);
++	printk("LayerPos:           0x%x\n",layerdesc->LayerPos.d32);
++	printk("LayerStride:        0x%x\n",layerdesc->LayerStride);
++//	printk("Layer_UV_addr:	    0x%x\n",layer_config->BufferAddr_UV);
++//	printk("Layer_UV_stride:    0x%x\n",layer_config->stride_UV);
++	printk("------User layer Descriptor index[%d][%d]------\n", row, col);
++}
++
++void dump_lay_cfg(struct ingenicfb_lay_cfg * lay_cfg, int index)
++{
++	printk("------User disp set index[%d]------\n", index);
++	printk("lay_en:		   0x%x\n",lay_cfg->lay_en);
++	printk("tlb_en:		   0x%x\n",lay_cfg->tlb_en);
++	printk("lay_scale_en:	   0x%x\n",lay_cfg->lay_scale_en);
++	printk("lay_z_order:	   0x%x\n",lay_cfg->lay_z_order);
++	printk("source_w:	   0x%x\n",lay_cfg->source_w);
++	printk("source_h:	   0x%x\n",lay_cfg->source_h);
++	printk("disp_pos_x:	   0x%x\n",lay_cfg->disp_pos_x);
++	printk("disp_pos_y:	   0x%x\n",lay_cfg->disp_pos_y);
++	printk("scale_w:	   0x%x\n",lay_cfg->scale_w);
++	printk("scale_h:	   0x%x\n",lay_cfg->scale_h);
++	printk("g_alpha_en:	   0x%x\n",lay_cfg->g_alpha_en);
++	printk("g_alpha_val:	   0x%x\n",lay_cfg->g_alpha_val);
++	printk("color:		   0x%x\n",lay_cfg->color);
++	printk("format:		   0x%x\n",lay_cfg->format);
++	printk("stride:		   0x%x\n",lay_cfg->stride);
++	printk("addr[0]:	   0x%x\n",lay_cfg->addr[0]);
++	printk("addr[1]:	   0x%x\n",lay_cfg->addr[1]);
++	printk("addr[2]:	   0x%x\n",lay_cfg->addr[2]);
++
++	printk("------User disp set index[%d]------\n", index);
++}
++
++static void dump_lcdc_registers(void)
++{
++	dump_dc_reg();
++	dump_tft_reg();
++	dump_slcd_reg();
++	dump_frm_desc_reg();
++	dump_layer_desc_reg();
++	dump_rdma_desc_reg();
++}
++
++static void dump_desc(struct ingenicfb_device *fbdev)
++{
++	int i, j;
++	for(i = 0; i < CONFIG_FB_INGENIC_NR_FRAMES*2; i++) {
++		for(j = 0; j < DPU_SUPPORT_MAX_LAYERS; j++) {
++			dump_layer_desc(fbdev->layerdesc[i][j], i, j);
++		}
++		dump_frm_desc(fbdev->framedesc[i], i);
++	}
++}
++
++	static ssize_t
++dump_lcd(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++
++	printk("\nDisp_end_num = %d\n\n",fbdev->irq_cnt);
++	printk("\nTFT_UNDR_num = %d\n\n",fbdev->tft_undr_cnt);
++	printk("\nFrm_start_num = %d\n\n", fbdev->frm_start);
++	printk(" Pand display count=%d\n",fbdev->pan_display_count);
++	printk("timestamp.wp = %d , timestamp.rp = %d\n\n", fbdev->timestamp.wp, fbdev->timestamp.rp);
++	dump_lcdc_registers();
++	dump_desc(fbdev);
++	return 0;
++}
++
++static void dump_all(struct ingenicfb_device *fbdev)
++{
++	printk("\ndisp_end_num = %d\n\n", fbdev->irq_cnt);
++	printk("\nTFT_UNDR_num = %d\n\n", fbdev->tft_undr_cnt);
++	printk("\nFrm_start_num = %d\n\n", fbdev->frm_start);
++	dump_lcdc_registers();
++	dump_desc(fbdev);
++}
++
++#ifdef CONFIG_DEBUG_DPU_IRQCNT
++	static ssize_t
++dump_irqcnts(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct dbg_irqcnt *dbg = &fbdev->dbg_irqcnt;
++	char *p = buf;
++	p += sprintf(p, "irqcnt		: %lld\n", dbg->irqcnt);
++	p += sprintf(p, "cmp_start	: %lld\n", dbg->cmp_start);
++	p += sprintf(p, "stop_disp_ack	: %lld\n", dbg->stop_disp_ack);
++	p += sprintf(p, "disp_end	: %lld\n", dbg->disp_end);
++	p += sprintf(p, "tft_under	: %lld\n", dbg->tft_under);
++	p += sprintf(p, "wdma_over	: %lld\n", dbg->wdma_over);
++	p += sprintf(p, "wdma_end	: %lld\n", dbg->wdma_end);
++	p += sprintf(p, "layer3_end	: %lld\n", dbg->layer3_end);
++	p += sprintf(p, "layer2_end	: %lld\n", dbg->layer2_end);
++	p += sprintf(p, "layer1_end	: %lld\n", dbg->layer1_end);
++	p += sprintf(p, "layer0_end	: %lld\n", dbg->layer0_end);
++	p += sprintf(p, "clr_cmp_end	: %lld\n", dbg->clr_cmp_end);
++	p += sprintf(p, "stop_wrbk_ack	: %lld\n", dbg->stop_wrbk_ack);
++	p += sprintf(p, "srd_start	: %lld\n", dbg->srd_start);
++	p += sprintf(p, "srd_end	: %lld\n", dbg->srd_end);
++	p += sprintf(p, "cmp_w_slow	: %lld\n", dbg->cmp_w_slow);
++
++	return p - buf;
++}
++#endif
++
++/*Sysfs interface.*/
++	static ssize_t
++dump_h_color_bar(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	ingenicfb_display_h_color_bar(fbdev->fb);
++	ingenicfb_cmp_start(fbdev->fb);
++	return 0;
++}
++
++	static ssize_t
++dump_v_color_bar(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	ingenicfb_display_v_color_bar(fbdev->fb);
++	ingenicfb_cmp_start(fbdev->fb);
++	return 0;
++}
++
++	static ssize_t
++vsync_skip_r(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	mutex_lock(&fbdev->lock);
++	snprintf(buf, 3, "%d\n", fbdev->vsync_skip_ratio);
++	printk("vsync_skip_map = 0x%08x\n", fbdev->vsync_skip_map);
++	mutex_unlock(&fbdev->lock);
++	return 3;		/* sizeof ("%d\n") */
++}
++
++static int vsync_skip_set(struct ingenicfb_device *fbdev, int vsync_skip)
++{
++	unsigned int map_wide10 = 0;
++	int rate, i, p, n;
++	int fake_float_1k;
++
++	if (vsync_skip < 0 || vsync_skip > 9)
++		return -EINVAL;
++
++	rate = vsync_skip + 1;
++	fake_float_1k = 10000 / rate;	/* 10.0 / rate */
++
++	p = 1;
++	n = (fake_float_1k * p + 500) / 1000;	/* +0.5 to int */
++
++	for (i = 1; i <= 10; i++) {
++		map_wide10 = map_wide10 << 1;
++		if (i == n) {
++			map_wide10++;
++			p++;
++			n = (fake_float_1k * p + 500) / 1000;
++		}
++	}
++	mutex_lock(&fbdev->lock);
++	fbdev->vsync_skip_map = map_wide10;
++	fbdev->vsync_skip_ratio = rate - 1;	/* 0 ~ 9 */
++	mutex_unlock(&fbdev->lock);
++
++	printk("vsync_skip_ratio = %d\n", fbdev->vsync_skip_ratio);
++	printk("vsync_skip_map = 0x%08x\n", fbdev->vsync_skip_map);
++
++	return 0;
++}
++
++	static ssize_t
++vsync_skip_w(struct device *dev, struct device_attribute *attr,
++		const char *buf, size_t count)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++
++	if ((count != 1) && (count != 2))
++		return -EINVAL;
++	if ((*buf < '0') && (*buf > '9'))
++		return -EINVAL;
++
++	vsync_skip_set(fbdev, *buf - '0');
++
++	return count;
++}
++
++static ssize_t fps_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	printk("\n-----you can choice print way:\n");
++	printk("Example: echo NUM > show_fps\n");
++	printk("NUM = 0: close fps statistics\n");
++	printk("NUM = 1: print recently fps\n");
++	printk("NUM = 2: print interval between last and this pan_display\n");
++	printk("NUM = 3: print pan_display count\n\n");
++	return 0;
++}
++
++static ssize_t fps_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	int num = 0;
++	num = simple_strtoul(buf, NULL, 0);
++	if(num < 0){
++		printk("\n--please 'cat show_fps' to view using the method\n\n");
++		return n;
++	}
++	showFPS = num;
++	if(showFPS == 3)
++		printk(KERN_DEBUG " Pand display count=%d\n",fbdev->pan_display_count);
++	return n;
++}
++
++
++	static ssize_t
++debug_clr_st(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	reg_write(fbdev, DC_CLR_ST, 0xffffffff);
++	return 0;
++}
++
++static ssize_t test_suspend(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	int num = 0;
++	num = simple_strtoul(buf, NULL, 0);
++	printk("0 --> resume | 1 --> suspend\nnow input %d\n", num);
++	if (num == 0) {
++		ingenicfb_do_resume(fbdev);
++	} else {
++		ingenicfb_do_suspend(fbdev);
++	}
++	return n;
++}
++
++/*************************self test******************************/
++static ssize_t test_slcd_send_value(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	int num = 0;
++	num = simple_strtoul(buf, NULL, 0);
++	if (num == 0) {
++		slcd_send_mcu_command(fbdev, 0x0);
++		slcd_send_mcu_command(fbdev, 0xffffff);
++		slcd_send_mcu_command(fbdev, 0x0);
++		slcd_send_mcu_command(fbdev, 0xffffff);
++		slcd_send_mcu_command(fbdev, 0x0);
++		slcd_send_mcu_command(fbdev, 0xffffff);
++		slcd_send_mcu_command(fbdev, 0x0);
++		slcd_send_mcu_command(fbdev, 0xffffff);
++		slcd_send_mcu_command(fbdev, 0x0);
++		slcd_send_mcu_command(fbdev, 0xffffff);
++		printk("Send command value 101\n");
++	} else if(num == 1){
++		slcd_send_mcu_prm(fbdev, 0x0);
++		slcd_send_mcu_prm(fbdev, 0xffffffff);
++		slcd_send_mcu_prm(fbdev, 0x0);
++		slcd_send_mcu_prm(fbdev, 0xffffffff);
++		slcd_send_mcu_prm(fbdev, 0x0);
++		slcd_send_mcu_prm(fbdev, 0xffffffff);
++		slcd_send_mcu_prm(fbdev, 0x0);
++		slcd_send_mcu_prm(fbdev, 0xffffffff);
++		slcd_send_mcu_prm(fbdev, 0x0);
++		slcd_send_mcu_prm(fbdev, 0xffffffff);
++		slcd_send_mcu_prm(fbdev, 0x0);
++		slcd_send_mcu_prm(fbdev, 0xffffffff);
++		printk("Send prm value 0x101\n");
++	} else {
++		slcd_send_mcu_data(fbdev, 0x0);
++		slcd_send_mcu_data(fbdev, 0xffffffff);
++		slcd_send_mcu_data(fbdev, 0x0);
++		slcd_send_mcu_data(fbdev, 0xffffffff);
++		slcd_send_mcu_data(fbdev, 0x0);
++		slcd_send_mcu_data(fbdev, 0xffffffff);
++		slcd_send_mcu_data(fbdev, 0x0);
++		slcd_send_mcu_data(fbdev, 0xffffffff);
++		slcd_send_mcu_data(fbdev, 0x0);
++		slcd_send_mcu_data(fbdev, 0xffffffff);
++		slcd_send_mcu_data(fbdev, 0x0);
++		slcd_send_mcu_data(fbdev, 0xffffffff);
++		printk("Send data value 0x101\n");
++	}
++	return n;
++}
++
++static ssize_t test_fifo_threshold(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	int num = 0;
++	unsigned int ctrl;
++	unsigned int cfg = 0;
++	num = simple_strtoul(buf, NULL, 0);
++	if (num == 0) {
++		ctrl = reg_read(fbdev, DC_PCFG_RD_CTRL);
++		ctrl &=  ~DC_ARQOS_CTRL;
++		reg_write(fbdev, DC_PCFG_RD_CTRL, ctrl);
++		printk("Close software control %d\n", num);
++	} else {
++		ctrl = reg_read(fbdev, DC_PCFG_RD_CTRL);
++		ctrl |=  DC_ARQOS_CTRL;
++		ctrl &= ~DC_ARQOS_VAL_MASK;
++		switch(num) {
++			case 1:
++				ctrl |= DC_ARQOS_VAL_0;
++				break;
++			case 2:
++				ctrl |= DC_ARQOS_VAL_1;
++				break;
++			case 3:
++				ctrl |= DC_ARQOS_VAL_2;
++				break;
++			case 4:
++				ctrl |= DC_ARQOS_VAL_3;
++				break;
++			default:
++				printk("Input err value %d\n", num);
++				return n;
++		}
++		reg_write(fbdev, DC_PCFG_RD_CTRL, ctrl);
++		cfg = (60 << DC_PCFG0_LBIT) | (120 << DC_PCFG1_LBIT) | (180 << DC_PCFG2_LBIT);
++		reg_write(fbdev, DC_OFIFO_PCFG, cfg);
++		printk("DC_OFIFO_PCFG = 0x%x  DC_PCFG_RD_CTRL = 0x%x\n", DC_OFIFO_PCFG, DC_PCFG_RD_CTRL);
++	}
++	return n;
++}
++static ssize_t test_slcd_time(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	unsigned int num = 0;
++	unsigned int type = 0;
++	unsigned int value;
++	num = simple_strtoul(buf, NULL, 0);
++
++	type = (num >> 8) & 0xff;
++	switch(type) {
++		case 0:
++			printk("\n0: print set ways\n");
++			printk("1: CDTIME\n");
++			printk("2: CSTIME\n");
++			printk("3: DDTIME\n");
++			printk("4: DSTIME\n");
++			printk("5: TAS\n");
++			printk("6: TAH\n");
++			printk("7: TCS\n");
++			printk("8: TCH\n");
++			printk("9: Slow time\n\n");
++			break;
++		case 1:
++			value = reg_read(fbdev, DC_SLCD_WR_DUTY);
++			reg_write(fbdev, DC_SLCD_WR_DUTY, ((num & 0xff) << DC_CDTIME_LBIT) | (value & ~DC_CDTIME_MASK));
++			break;
++		case 2:
++			value = reg_read(fbdev, DC_SLCD_WR_DUTY);
++			reg_write(fbdev, DC_SLCD_WR_DUTY, ((num & 0xff) << DC_CSTIME_LBIT) | (value & ~DC_CSTIME_MASK));
++			break;
++		case 3:
++			value = reg_read(fbdev, DC_SLCD_WR_DUTY);
++			reg_write(fbdev, DC_SLCD_WR_DUTY, ((num & 0xff) << DC_DDTIME_LBIT) | (value & ~DC_DDTIME_MASK));
++			break;
++		case 4:
++			value = reg_read(fbdev, DC_SLCD_WR_DUTY);
++			reg_write(fbdev, DC_SLCD_WR_DUTY, ((num & 0xff) << DC_DSTIME_LBIT) | (value & ~DC_DSTIME_MASK));
++			break;
++		case 5:
++			value = reg_read(fbdev, DC_SLCD_TIMING);
++			reg_write(fbdev, DC_SLCD_TIMING, ((num & 0xff) << DC_TAS_LBIT) | (value & ~DC_TAS_MASK));
++			break;
++		case 6:
++			value = reg_read(fbdev, DC_SLCD_TIMING);
++			reg_write(fbdev, DC_SLCD_TIMING, ((num & 0xff) << DC_TAH_LBIT) | (value & ~DC_TAH_MASK));
++			break;
++		case 7:
++			value = reg_read(fbdev, DC_SLCD_TIMING);
++			reg_write(fbdev, DC_SLCD_TIMING, ((num & 0xff) << DC_TCS_LBIT) | (value & ~DC_TCS_MASK));
++			break;
++		case 8:
++			value = reg_read(fbdev, DC_SLCD_TIMING);
++			reg_write(fbdev, DC_SLCD_TIMING, ((num & 0xff) << DC_TCH_LBIT) | (value & ~DC_TCH_MASK));
++			break;
++		case 9:
++			value = reg_read(fbdev, DC_SLCD_SLOW_TIME);
++			reg_write(fbdev, DC_SLCD_SLOW_TIME, ((num & 0xff) << DC_SLOW_TIME_LBIT) | (value & ~DC_SLOW_TIME_MASK));
++			break;
++		default:
++			printk("Input err value %d\n", num);
++			return n;
++	}
++	printk("DC_SLCD_WR_DUTY = 0x%lx\n", reg_read(fbdev, DC_SLCD_WR_DUTY));
++	printk("DC_SLCD_TIMING = 0x%lx\n", reg_read(fbdev, DC_SLCD_TIMING));
++	printk("DC_SLCD_SLOW_TIME = 0x%lx\n", reg_read(fbdev, DC_SLCD_SLOW_TIME));
++	return n;
++}
++static ssize_t show_irq_msg(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	char *p = buf;
++	p += printk(p, "0 -> set: all irq\n");
++	p += printk(p, "1 -> set: DC_CMP_W_SLOW\n");
++	p += printk(p, "2 -> set: DC_DISP_END\n");
++	p += printk(p, "3 -> set: DC_WDMA_OVER\n");
++	p += printk(p, "4 -> set: DC_WDMA_END\n");
++	p += printk(p, "5 -> set: DC_CMP_START\n");
++	p += printk(p, "6 -> set: DC_LAY3_END\n");
++	p += printk(p, "7 -> set: DC_LAY2_END\n");
++	p += printk(p, "8 -> set: DC_LAY1_END\n");
++	p += printk(p, "9 -> set: DC_LAY0_END\n");
++	p += printk(p, "10 -> set: DC_CMP_END\n");
++	p += printk(p, "11 -> set: DC_TFT_UNDR\n");
++	p += printk(p, "12 -> set: DC_STOP_WRBK_ACK\n");
++	p += printk(p, "13 -> set: DC_STOP_DISP_ACK\n");
++	p += printk(p, "14 -> set: DC_SRD_START\n");
++	p += printk(p, "15 -> set: DC_SRD_END\n");
++
++	return p - buf;
++}
++static ssize_t set_irq_bit(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	int num = 0;
++	unsigned int irq;
++	num = simple_strtoul(buf, NULL, 0);
++	irq = reg_read(fbdev, DC_INTC);
++	switch(num) {
++		case 0:
++			reg_write(fbdev, DC_INTC, 0x820f46);
++			break;
++		case 1:
++			reg_write(fbdev, DC_INTC, DC_CMP_W_SLOW | irq);
++			break;
++		case 2:
++			reg_write(fbdev, DC_INTC, DC_DISP_END | irq);
++			break;
++		case 3:
++			reg_write(fbdev, DC_INTC, DC_WDMA_OVER | irq);
++			break;
++		case 4:
++			reg_write(fbdev, DC_INTC, DC_WDMA_END | irq);
++			break;
++		case 5:
++			reg_write(fbdev, DC_INTC, DC_CMP_START | irq);
++			break;
++		case 6:
++			reg_write(fbdev, DC_INTC, DC_LAY3_END | irq);
++			break;
++		case 7:
++			reg_write(fbdev, DC_INTC, DC_LAY2_END | irq);
++			break;
++		case 8:
++			reg_write(fbdev, DC_INTC, DC_LAY1_END | irq);
++			break;
++		case 9:
++			reg_write(fbdev, DC_INTC, DC_LAY0_END | irq);
++			break;
++		case 10:
++			reg_write(fbdev, DC_INTC, DC_CMP_END | irq);
++			break;
++		case 11:
++			reg_write(fbdev, DC_INTC, DC_TFT_UNDR | irq);
++			break;
++		case 12:
++			reg_write(fbdev, DC_INTC, DC_STOP_WRBK_ACK | irq);
++			break;
++		case 13:
++			reg_write(fbdev, DC_INTC, DC_STOP_DISP_ACK | irq);
++			break;
++		case 14:
++			reg_write(fbdev, DC_INTC, DC_SRD_START | irq);
++			break;
++		case 15:
++			reg_write(fbdev, DC_INTC, DC_SRD_END | irq);
++			break;
++		default:
++			printk("Err: Please check num = %d", num);
++			reg_write(fbdev, DC_INTC, DC_CMP_START);
++			break;
++	}
++
++	return n;
++}
++
++#ifdef CONFIG_FB_INGENIC_MIPI_DSI
++	static ssize_t
++dump_dsi(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	struct dsi_device *dsi = fbdev->dsi;
++
++	mutex_lock(&fbdev->lock);
++	dump_dsi_reg(dsi);
++	mutex_unlock(&fbdev->lock);
++	return 0;
++}
++
++	static ssize_t
++dsi_query_te(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	struct dsi_device *dsi = fbdev->dsi;
++
++	mutex_lock(&fbdev->lock);
++	fbdev->dsi->master_ops->query_te(dsi);
++	mutex_unlock(&fbdev->lock);
++	return 0;
++}
++#endif
++
++
++	static ssize_t
++test_fb_disable(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++
++	ingenicfb_disable(fbdev->fb, GEN_STOP);
++	return 0;
++}
++
++	static ssize_t
++test_fb_enable(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++
++	ingenicfb_enable(fbdev->fb);
++	return 0;
++}
++
++static ssize_t show_color_modes(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	struct ingenicfb_colormode *current_mode = NULL;
++	char *p = buf;
++	int i = 0;
++
++	p += sprintf(p, "supported color modes:\n");
++	for(i = 0; i < ARRAY_SIZE(ingenicfb_colormodes); i++) {
++		struct ingenicfb_colormode * m = &ingenicfb_colormodes[i];
++		p += sprintf(p, "[%d]:%s\n", i, m->name);
++
++		if(m->mode == fbdev->current_frm_mode.frm_cfg.lay_cfg[0].format) {
++			current_mode = m;
++		}
++	}
++	p += sprintf(p, "Current color mode: [%s]\n", current_mode ? current_mode->name:"none");
++	p += sprintf(p, "Tips: echo [%s] to select one of supported color modes\n", current_mode ? current_mode->name:"none");
++
++	return p - buf;
++
++}
++
++static ssize_t store_color_modes(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	struct fb_info *fb = fbdev->fb;
++	struct ingenicfb_colormode *m = NULL;
++	int index = 0;
++	int ret = 0;
++
++	index = simple_strtol(buf, NULL, 10);
++
++	if(index < 0 && index > ARRAY_SIZE(ingenicfb_colormodes))
++		return -EINVAL;
++
++	m = &ingenicfb_colormodes[index];
++
++	/* modify fb var. */
++	ingenicfb_colormode_to_var(&fb->var, m);
++
++	/* reset params. */
++	ret = ingenicfb_set_par(fbdev->fb);
++	if(ret < 0)
++		return ret;
++
++	return n;
++}
++static ssize_t show_wback_en(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	char *p = buf;
++
++	p += sprintf(p, "help: write [1/0] to [en/dis] wback\n");
++	p += sprintf(p, "wback_en: %d\n", fbdev->wback_en);
++
++	return p - buf;
++}
++
++static ssize_t store_wback_en(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	int en = 0;
++	int ret = 0;
++
++	en = simple_strtol(buf, NULL, 10);
++
++	fbdev->wback_en = !!en;
++
++	/* reset params. */
++	ret = ingenicfb_set_par(fbdev->fb);
++	if(ret < 0)
++		return ret;
++
++	return n;
++}
++
++static ssize_t show_csc_mode(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	char *p = buf;
++
++	p += sprintf(p, "current csc_mode: %d\n", fbdev->csc_mode);
++
++	return p - buf;
++}
++
++static ssize_t store_csc_mode(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	int csc_mode = 0;
++	int ret = 0;
++
++	csc_mode = simple_strtol(buf, NULL, 10);
++
++	if(csc_mode < 0 || csc_mode > 3) {
++		return -EINVAL;
++	}
++
++	csc_mode_set(fbdev, csc_mode);
++	fbdev->csc_mode = csc_mode;
++
++	/* reset params. */
++	ret = ingenicfb_set_par(fbdev->fb);
++	if(ret < 0)
++		return ret;
++
++	return n;
++}
++
++static ssize_t show_wbackbuf(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++
++	char *wbackbuf = fbdev->sread_vidmem[0];	/* TODO: where should wback addr is?*/
++	unsigned int wbackbuf_len = fbdev->frm_size;
++	int copy_len = wbackbuf_len < 1024 ? wbackbuf_len : 1024; /* only copy first 1024 bytes for quik debug.*/
++
++	if(fbdev->wback_en == 0) {
++		return -EINVAL;
++	}
++
++	print_hex_dump(KERN_INFO, "wback data: ", DUMP_PREFIX_ADDRESS, 16, 1, wbackbuf, 128, true);
++
++	memcpy(buf, wbackbuf, copy_len);
++
++	return copy_len;
++}
++
++/*************************self test******************************/
++
++/**********************lcd_debug***************************/
++static DEVICE_ATTR(dump_lcd, S_IRUGO|S_IWUSR, dump_lcd, NULL);
++static DEVICE_ATTR(dump_h_color_bar, S_IRUGO|S_IWUSR, dump_h_color_bar, NULL);
++static DEVICE_ATTR(dump_v_color_bar, S_IRUGO|S_IWUSR, dump_v_color_bar, NULL);
++static DEVICE_ATTR(vsync_skip, S_IRUGO|S_IWUSR, vsync_skip_r, vsync_skip_w);
++static DEVICE_ATTR(show_fps, S_IRUGO|S_IWUSR, fps_show, fps_store);
++static DEVICE_ATTR(debug_clr_st, S_IRUGO|S_IWUSR, debug_clr_st, NULL);
++static DEVICE_ATTR(test_suspend, S_IRUGO|S_IWUSR, NULL, test_suspend);
++
++#ifdef CONFIG_DEBUG_DPU_IRQCNT
++static DEVICE_ATTR(dump_irqcnts, (S_IRUGO|S_IWUGO) & (~S_IWOTH), dump_irqcnts, NULL);
++#endif
++
++#ifdef CONFIG_FB_INGENIC_MIPI_DSI
++static DEVICE_ATTR(dump_dsi, S_IRUGO|S_IWUSR, dump_dsi, NULL);
++static DEVICE_ATTR(dsi_query_te, S_IRUGO|S_IWUSR, dsi_query_te, NULL);
++#endif
++static DEVICE_ATTR(test_fb_disable, (S_IRUGO|S_IWUGO)&(~S_IWOTH), test_fb_disable, NULL);
++static DEVICE_ATTR(test_fb_enable, (S_IRUGO|S_IWUGO)&(~S_IWOTH) , test_fb_enable, NULL);
++
++static DEVICE_ATTR(test_irq, S_IRUGO|S_IWUSR, show_irq_msg, set_irq_bit);
++static DEVICE_ATTR(test_fifo_threshold, S_IRUGO|S_IWUSR, NULL, test_fifo_threshold);
++static DEVICE_ATTR(test_slcd_time, S_IRUGO|S_IWUSR, NULL, test_slcd_time);
++static DEVICE_ATTR(test_slcd_send_value, S_IRUGO|S_IWUSR, NULL, test_slcd_send_value);
++static DEVICE_ATTR(color_modes, S_IRUGO|S_IWUSR, show_color_modes, store_color_modes);
++static DEVICE_ATTR(wback_en, S_IRUGO|S_IWUSR, show_wback_en, store_wback_en);
++static DEVICE_ATTR(wbackbuf, S_IRUGO|S_IWUSR, show_wbackbuf, NULL);
++static DEVICE_ATTR(csc_mode, S_IRUGO|S_IWUSR, show_csc_mode, store_csc_mode);
++
++
++static struct attribute *lcd_debug_attrs[] = {
++	&dev_attr_dump_lcd.attr,
++	&dev_attr_dump_h_color_bar.attr,
++	&dev_attr_dump_v_color_bar.attr,
++	&dev_attr_vsync_skip.attr,
++	&dev_attr_show_fps.attr,
++	&dev_attr_debug_clr_st.attr,
++	&dev_attr_test_suspend.attr,
++
++#ifdef CONFIG_DEBUG_DPU_IRQCNT
++	&dev_attr_dump_irqcnts.attr,
++#endif
++
++#ifdef CONFIG_FB_INGENIC_MIPI_DSI
++	&dev_attr_dump_dsi.attr,
++	&dev_attr_dsi_query_te.attr,
++#endif
++	&dev_attr_test_fb_disable.attr,
++	&dev_attr_test_fb_enable.attr,
++	&dev_attr_test_irq.attr,
++	&dev_attr_test_fifo_threshold.attr,
++	&dev_attr_test_slcd_time.attr,
++	&dev_attr_test_slcd_send_value.attr,
++	&dev_attr_color_modes.attr,
++	&dev_attr_wback_en.attr,
++	&dev_attr_wbackbuf.attr,
++	&dev_attr_csc_mode.attr,
++	NULL,
++};
++
++const char lcd_group_name[] = "debug";
++static struct attribute_group lcd_debug_attr_group = {
++	.name	= lcd_group_name,
++	.attrs	= lcd_debug_attrs,
++};
++
++struct layer_device_attr {
++	struct device_attribute attr;
++	unsigned int id;
++};
++
++#define to_layer_attr(attr)	\
++	container_of(attr, struct layer_device_attr, attr)
++
++
++static ssize_t show_src_size(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	int layer = to_layer_attr(attr)->id;
++	struct ingenicfb_frm_cfg *frm_cfg = &fbdev->current_frm_mode.frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg;
++	char *p = buf;
++
++	if(layer > CONFIG_FB_INGENIC_NR_LAYERS) {
++		return -EINVAL;
++	}
++	lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	p += sprintf(p, "layer: %d, src_w: %d, src_h: %d\n", layer, lay_cfg->source_w, lay_cfg->source_h);
++
++	return p - buf;
++}
++static ssize_t store_src_size(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++
++	return n;
++}
++static ssize_t show_src_fmt(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	struct ingenicfb_colormode *current_mode = NULL;
++	int layer = to_layer_attr(attr)->id;
++	char *p = buf;
++	int i = 0;
++
++	p += sprintf(p, "supported color modes:\n");
++	for(i = 0; i < ARRAY_SIZE(ingenicfb_colormodes); i++) {
++		struct ingenicfb_colormode * m = &ingenicfb_colormodes[i];
++		p += sprintf(p, "[%d]:%s\n", i, m->name);
++
++		if(m->mode == fbdev->current_frm_mode.frm_cfg.lay_cfg[layer].format) {
++			current_mode = m;
++		}
++	}
++	p += sprintf(p, "Current color mode: [%s]\n", current_mode ? current_mode->name:"none");
++	p += sprintf(p, "Tips: echo [%s] to select one of supported color modes\n", current_mode ? current_mode->name:"none");
++
++	return p - buf;
++}
++static ssize_t store_src_fmt(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	struct fb_info *fb = fbdev->fb;
++	struct ingenicfb_colormode *m = NULL;
++	int index = 0;
++	int layer = to_layer_attr(attr)->id;
++	struct ingenicfb_frm_cfg *frm_cfg = &fbdev->current_frm_mode.frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg;
++
++	index = simple_strtol(buf, NULL, 10);
++
++	if(index < 0 && index > ARRAY_SIZE(ingenicfb_colormodes))
++		return -EINVAL;
++
++	m = &ingenicfb_colormodes[index];
++
++	if(layer > CONFIG_FB_INGENIC_NR_LAYERS) {
++		return -EINVAL;
++	}
++
++	lay_cfg = &frm_cfg->lay_cfg[layer];
++	lay_cfg->format = m->mode;
++
++	/*update fb_info.*/
++	fb = fbdev->fbs[layer];
++	ingenicfb_colormode_to_var(&fb->var, m);
++	fb->mode = ingenicfb_get_mode(&fb->var, fb);
++
++	return n;
++
++}
++static ssize_t show_target_size(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	int layer = to_layer_attr(attr)->id;
++	struct ingenicfb_frm_cfg *frm_cfg = &fbdev->current_frm_mode.frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg;
++	char *p = buf;
++
++	if(layer > CONFIG_FB_INGENIC_NR_LAYERS) {
++		return -EINVAL;
++	}
++
++	lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	p += sprintf(p, "%dx%d\n", lay_cfg->scale_w, lay_cfg->scale_h);
++
++	return p - buf;
++}
++static ssize_t store_target_size(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	int layer = to_layer_attr(attr)->id;
++	struct ingenicfb_frm_cfg *frm_cfg = &fbdev->current_frm_mode.frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg;
++	char *p;
++	char *s = (char *)buf;
++
++	if(layer > CONFIG_FB_INGENIC_NR_LAYERS) {
++		return -EINVAL;
++	}
++
++	lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	p = strsep(&s, "x");
++	if(!s) {
++		return -EINVAL;
++	}
++
++	lay_cfg->scale_w = simple_strtoul(p, NULL, 0);
++	lay_cfg->scale_h = simple_strtoul(s, NULL, 0);
++
++
++	printk("scale_w: %d, scale_h: %d\n", lay_cfg->scale_w, lay_cfg->scale_h);
++
++	return n;
++}
++static ssize_t show_target_pos(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	int layer = to_layer_attr(attr)->id;
++	struct ingenicfb_frm_cfg *frm_cfg = &fbdev->current_frm_mode.frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg;
++	char *p = buf;
++
++	if(layer > CONFIG_FB_INGENIC_NR_LAYERS) {
++		return -EINVAL;
++	}
++
++	lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	p += sprintf(p, "layer:%d, pos_x: %d, pos_y:%d\n", layer, lay_cfg->disp_pos_x, lay_cfg->disp_pos_y);
++
++	return p - buf;
++}
++static ssize_t store_target_pos(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	int layer = to_layer_attr(attr)->id;
++	struct ingenicfb_frm_cfg *frm_cfg = &fbdev->current_frm_mode.frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg;
++	char *p;
++	char *s = (char *)buf;
++
++	if(layer > CONFIG_FB_INGENIC_NR_LAYERS) {
++		return -EINVAL;
++	}
++
++	lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	p = strsep(&s, "x");
++	if(!s) {
++		return -EINVAL;
++	}
++
++	lay_cfg->disp_pos_x = simple_strtoul(p, NULL, 0);
++	lay_cfg->disp_pos_y = simple_strtoul(s, NULL, 0);
++
++
++	printk("-pos_x: %d, pos_y: %d\n", lay_cfg->disp_pos_x, lay_cfg->disp_pos_y);
++
++	return n;
++}
++
++static ssize_t show_enable(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	int layer = to_layer_attr(attr)->id;
++	struct ingenicfb_frm_cfg *frm_cfg = &fbdev->current_frm_mode.frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg;
++	char *p = buf;
++
++	if(layer > CONFIG_FB_INGENIC_NR_LAYERS) {
++		return -EINVAL;
++	}
++
++	lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	p += sprintf(p, "layer: %d, enable: %d\n", layer, lay_cfg->lay_en);
++
++	return p - buf;
++}
++static ssize_t store_enable(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t n)
++{
++	struct ingenicfb_device *fbdev = dev_get_drvdata(dev);
++	struct fb_info *fb = fbdev->fb;
++	struct ingenicfb_frm_cfg *frm_cfg = &fbdev->current_frm_mode.frm_cfg;
++	struct ingenicfb_lay_cfg *lay_cfg;
++	int layer = to_layer_attr(attr)->id;
++	int enable = 0;
++
++	if(layer > CONFIG_FB_INGENIC_NR_LAYERS) {
++		return -EINVAL;
++	}
++
++	lay_cfg = &frm_cfg->lay_cfg[layer];
++
++	if(lay_cfg->scale_w == 0 || lay_cfg->scale_h == 0) {
++		return -EINVAL;
++	}
++
++	enable = simple_strtoul(buf, NULL, 0);
++	if(enable) {
++		lay_cfg->lay_en = 1;
++		if(lay_cfg->scale_w != lay_cfg->source_w || lay_cfg->scale_h != lay_cfg->source_h) {
++			lay_cfg->lay_scale_en = 1;
++		} else {
++			lay_cfg->lay_scale_en = 0;
++		}
++	} else {
++		lay_cfg->lay_en = 0;
++		lay_cfg->lay_scale_en = 0;
++	}
++
++
++
++#if 0
++	printk("layer: %d src_w: %d, src_h: %d, scale_w: %d, scale_h: %d, pos_x:%d, pos_y:%d\n",
++		layer, lay_cfg->source_w, lay_cfg->source_h, lay_cfg->scale_w, lay_cfg->scale_h, lay_cfg->disp_pos_x, lay_cfg->disp_pos_y);
++#endif
++
++	/*update all layers?*/
++	if(layer == 0) {
++		ingenicfb_disable(fbdev->fb, GEN_STOP);
++		ingenicfb_set_par(fb);
++		ingenicfb_enable(fbdev->fb);
++	}
++	return n;
++}
++
++
++#define LAYER_ATTR(layer, _name, _mode, _show, _store)		\
++	{							\
++	.attr 	= __ATTR(_name, _mode, _show, _store),	\
++	.id 	= layer,						\
++	}
++
++
++#define LAYER_DEVICE_ATTR(_name, _mode, _show, _store)							  \
++	static struct layer_device_attr dev_attr_##_name##layer0 = LAYER_ATTR(0, _name, _mode, _show, _store); \
++	static struct layer_device_attr dev_attr_##_name##layer1 = LAYER_ATTR(1, _name, _mode, _show, _store); \
++	static struct layer_device_attr dev_attr_##_name##layer2 = LAYER_ATTR(2, _name, _mode, _show, _store); \
++	static struct layer_device_attr dev_attr_##_name##layer3 = LAYER_ATTR(3, _name, _mode, _show, _store)
++
++LAYER_DEVICE_ATTR(src_size, S_IRUGO|S_IWUSR, show_src_size, store_src_size);
++LAYER_DEVICE_ATTR(src_fmt, S_IRUGO|S_IWUSR, show_src_fmt, store_src_fmt);
++LAYER_DEVICE_ATTR(target_size, S_IRUGO|S_IWUSR, show_target_size, store_target_size);
++LAYER_DEVICE_ATTR(target_pos, S_IRUGO|S_IWUSR, show_target_pos, store_target_pos);
++LAYER_DEVICE_ATTR(enable, S_IRUGO|S_IWUSR, show_enable, store_enable);
++
++#define LAYER_ATTRIBUTE_GROUP(name)					\
++	static struct attribute *lcd_##name##_attrs[] = {		\
++		&dev_attr_src_size##name.attr.attr,			\
++		&dev_attr_src_fmt##name.attr.attr,                      \
++		&dev_attr_target_size##name.attr.attr,                  \
++		&dev_attr_target_pos##name.attr.attr,                   \
++		&dev_attr_enable##name.attr.attr,                       \
++		NULL,							\
++	};
++
++LAYER_ATTRIBUTE_GROUP(layer0);
++LAYER_ATTRIBUTE_GROUP(layer1);
++LAYER_ATTRIBUTE_GROUP(layer2);
++LAYER_ATTRIBUTE_GROUP(layer3);
++
++static struct attribute_group lcd_layer0_group = {
++		.name = "layer0",
++		.attrs = lcd_layer0_attrs,
++};
++static struct attribute_group lcd_layer1_group = {
++		.name = "layer1",
++		.attrs = lcd_layer1_attrs,
++};
++static struct attribute_group lcd_layer2_group = {
++		.name = "layer2",
++		.attrs = lcd_layer2_attrs,
++};
++static struct attribute_group lcd_layer3_group = {
++		.name = "layer3",
++		.attrs = lcd_layer3_attrs,
++};
++
++static const struct attribute_group *lcd_layerx_groups[] = {
++	&lcd_layer0_group,
++	&lcd_layer1_group,
++	&lcd_layer2_group,
++	&lcd_layer3_group,
++	NULL,
++};
++
++
++
++
++
++int ingenicfb_sysfs_init()
++{
++	ret = sysfs_create_group(&fbdev->dev->kobj, &lcd_debug_attr_group);
++	if (ret) {
++		dev_err(&pdev->dev, "device create sysfs group failed\n");
++
++		ret = -EINVAL;
++		goto err_free_irq;
++	}
++
++	ret = sysfs_create_groups(&fbdev->dev->kobj, lcd_layerx_groups);
++	if(ret) {
++		dev_err(&pdev->dev, "Failed to create sysfs groups\n");
++	}
++
++
++
++}
+diff --git a/module_drivers/drivers/video/fbdev/ingenic/fb_stage/uapi_ingenicfb.h b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/uapi_ingenicfb.h
+new file mode 100644
+index 000000000..f7c6437e0
+--- /dev/null
++++ b/module_drivers/drivers/video/fbdev/ingenic/fb_stage/uapi_ingenicfb.h
+@@ -0,0 +1,121 @@
++#ifndef __UAPI_INGENICFB_H__
++#define __UAPI_INGENICFB_H__
++
++/* structs export to userspace */
++
++#define PIXEL_ALIGN 4
++#define DESC_ALIGN 8
++#define MAX_BITS_PER_PIX (32)
++#define DPU_MAX_SIZE (2047)
++#define DPU_MIN_SIZE (4)
++#define DPU_STRIDE_SIZE (4096)
++#define DPU_SCALE_MIN_SIZE (20)
++
++
++#define MAX_STRIDE_VALUE (4096)
++
++/* Maximum layers supported by DPU hardware */
++#define DPU_SUPPORT_MAX_LAYERS 4
++
++/* Maximum frames supported by DPU drivers */
++#define DPU_SUPPORT_MAX_FRAMES 3
++
++
++enum {
++	DC_WB_FORMAT_8888 = 0,
++	DC_WB_FORMAT_565 = 1,
++	DC_WB_FORMAT_555 = 2,
++	DC_WB_FORMAT_YUV422 = 3,	/*Not support*/
++	DC_WB_FORMAT_MONO = 4,		/*Not support*/
++	DC_WB_FORMAT_888 = 6,
++};
++
++enum {
++	LAYER_CFG_FORMAT_RGB555 = 0,
++	LAYER_CFG_FORMAT_ARGB1555 = 1,
++	LAYER_CFG_FORMAT_RGB565	= 2,
++	LAYER_CFG_FORMAT_RGB888	= 4,
++	LAYER_CFG_FORMAT_ARGB8888 = 5,
++	LAYER_CFG_FORMAT_MONO8 = 6,
++	LAYER_CFG_FORMAT_MONO16 = 7,
++	LAYER_CFG_FORMAT_NV12 = 8,
++	LAYER_CFG_FORMAT_NV21 = 9,
++	LAYER_CFG_FORMAT_YUV422 = 10,
++	LAYER_CFG_FORMAT_TILE_H264 = 12,
++};
++
++enum {
++	LAYER_CFG_COLOR_RGB = 0,
++	LAYER_CFG_COLOR_RBG = 1,
++	LAYER_CFG_COLOR_GRB = 2,
++	LAYER_CFG_COLOR_GBR = 3,
++	LAYER_CFG_COLOR_BRG = 4,
++	LAYER_CFG_COLOR_BGR = 5,
++};
++
++enum {
++	LAYER_Z_ORDER_0 = 0, /* bottom */
++	LAYER_Z_ORDER_1 = 1,
++	LAYER_Z_ORDER_2 = 2,
++	LAYER_Z_ORDER_3 = 3, /* top */
++};
++
++
++struct ingenicfb_lay_cfg {
++	unsigned int lay_en:1;
++	unsigned int tlb_en:1;
++	unsigned int lay_scale_en:1;
++	unsigned int lay_z_order:3;
++	unsigned int format:4;
++	unsigned int color:3;
++	unsigned int g_alpha_en:1;
++	unsigned int g_alpha_val:8;
++	unsigned int source_w;
++	unsigned int source_h;
++	unsigned int stride;
++	unsigned int uv_stride;	/*NV12 only.*/
++	unsigned int scale_w;
++	unsigned int scale_h;
++	unsigned int disp_pos_x;
++	unsigned int disp_pos_y;
++	unsigned int addr[3];
++	unsigned int uv_addr[3]; /*uv_addr for NV12 format.*/
++	unsigned int reserve[4];
++};
++
++struct wback_cfg {
++	int en;
++	unsigned int fmt;
++	unsigned int addr;
++	unsigned int stride;
++	int dither_en;
++};
++
++
++struct ingenicfb_frm_cfg {
++	struct ingenicfb_lay_cfg lay_cfg[DPU_SUPPORT_MAX_LAYERS];
++	struct wback_cfg wback_info;
++	unsigned int width;
++	unsigned int height;
++};
++
++
++#define JZFB_PUT_FRM_CFG		_IOWR('F', 0x101, struct ingenicfb_frm_cfg *)
++#define JZFB_GET_FRM_CFG		_IOWR('F', 0x102, struct ingenicfb_frm_cfg *)
++
++#define JZFB_SET_CSC_MODE		_IOW('F', 0x120, csc_mode_t)
++#define JZFB_USE_TLB			_IOW('F', 0x124, unsigned int)
++#define JZFB_DMMU_MAP			_IOWR('F', 0x130, struct dpu_dmmu_map_info)
++#define JZFB_DMMU_UNMAP			_IOWR('F', 0x131, struct dpu_dmmu_map_info)
++#define JZFB_DMMU_UNMAP_ALL		_IOWR('F', 0x132, struct dpu_dmmu_map_info)
++#define JZFB_DMMU_MEM_SMASH		_IOWR('F', 0x133, struct smash_mode)
++#define JZFB_DMMU_DUMP_MAP		_IOWR('F', 0x134, unsigned long)
++#define JZFB_DMMU_FLUSH_CACHE		_IOWR('F', 0x135, struct dpu_dmmu_map_info)
++#define JZFB_DUMP_LCDC_REG		_IOW('F', 0x150, int)
++
++#define JZFB_SET_VSYNCINT		_IOW('F', 0x210, int)
++#define JZFB_GET_LAYERS_NUM		_IOWR('F', 0x211, unsigned int)
++
++
++
++#endif
+diff --git a/module_drivers/drivers/video/ingenic-nna/Kconfig b/module_drivers/drivers/video/ingenic-nna/Kconfig
+new file mode 100644
+index 000000000..d1ff1e71b
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic-nna/Kconfig
+@@ -0,0 +1,9 @@
++config INGENIC_SOC_NNA
++	tristate "[NNA] ingenic soc nna module"
++	depends on SOC_X2500
++	default n
++	help
++		this is ingenic soc-nna for x2500 ,register as a misc device
++
++
++
+diff --git a/module_drivers/drivers/video/ingenic-nna/Makefile b/module_drivers/drivers/video/ingenic-nna/Makefile
+new file mode 100644
+index 000000000..307d95928
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic-nna/Makefile
+@@ -0,0 +1,5 @@
++obj-$(CONFIG_INGENIC_SOC_NNA)	+= soc_nna.o
++obj-$(CONFIG_INGENIC_SOC_NNA)   += mpsys-firmware/
++
++
++
+diff --git a/module_drivers/drivers/video/ingenic-nna/mpsys-firmware/Makefile b/module_drivers/drivers/video/ingenic-nna/mpsys-firmware/Makefile
+new file mode 100644
+index 000000000..e4c90b07b
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic-nna/mpsys-firmware/Makefile
+@@ -0,0 +1,4 @@
++obj-y	+= mpsys_module.o mpsys-funcs.o mpsys_firmware.a
++
++
++
+diff --git a/module_drivers/drivers/video/ingenic-nna/mpsys-firmware/mpsys-funcs.c b/module_drivers/drivers/video/ingenic-nna/mpsys-firmware/mpsys-funcs.c
+new file mode 100755
+index 000000000..e2a25b8c1
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic-nna/mpsys-firmware/mpsys-funcs.c
+@@ -0,0 +1,182 @@
++#include "mpsys-funcs.h"
++
++/* semaphore and mutex interfaces */
++int mpsys_down_interruptible(struct semaphore *sem)
++{
++    return down_interruptible(sem);
++}
++
++void mpsys_up(struct semaphore *sem)
++{
++    up(sem);
++}
++
++void mpsys_mutex_lock(struct mutex *lock)
++{
++	mutex_lock(lock);
++}
++
++void mpsys_mutex_unlock(struct mutex *lock)
++{
++	mutex_unlock(lock);
++}
++
++int mpsys_mutex_lock_interruptible(struct mutex *lock)
++{
++    return mutex_lock_interruptible(lock);
++}
++
++/* wait interfaces */
++void mpsys_init_completion(struct completion *x)
++{
++	init_completion(x);
++}
++
++void mpsys_complete(struct completion *x)
++{
++	complete(x);
++}
++
++int mpsys_wait_for_completion_interruptible(struct completion *x)
++{
++	return wait_for_completion_interruptible(x);
++}
++
++int mpsys_wait_event_interruptible(wait_queue_head_t *wq, int (* state)(void))
++{
++	return wait_event_interruptible((*wq), state());
++}
++
++void mpsys_wake_up(wait_queue_head_t *q)
++{
++	wake_up(q);
++}
++
++/* mem ops */
++void* mpsys_kzalloc(size_t s, gfp_t gfp)
++{
++    return kzalloc(s, gfp);
++}
++
++void mpsys_kfree(void *p)
++{
++	kfree(p);
++}
++
++long mpsys_copy_from_user(void *to, const void __user *from, long size)
++{
++	return copy_from_user(to, from, size);
++}
++
++long mpsys_copy_to_user(void __user *to, const void *from, long size)
++{
++	return copy_to_user(to, from, size);
++}
++
++/* file ops */
++struct file *mpsys_filp_open(const char *filename, int flags, umode_t mode)
++{
++	return filp_open(filename, flags, mode);
++}
++
++int mpsys_filp_close(struct file *filp, fl_owner_t id)
++{
++	return filp_close(filp, id);
++}
++
++int mpsys_kernel_read(struct file *file, loff_t *offset, char *addr, size_t count)
++{
++    return kernel_read(file, addr, count, offset);
++}
++
++/* string ops */
++char* mpsys_strstr(const char *s1, const char *s2)
++{
++    return strstr(s1, s2);
++}
++
++size_t mpsys_strlen(const char *s)
++{
++    return strlen(s);
++}
++
++int mpsys_kstrtoint(const char *s, unsigned int base, int *res)
++{
++    return kstrtoint(s, base, res);
++}
++
++/* misc driver interfaces */
++int mpsys_misc_register(struct miscdevice *misc)
++{
++    return misc_register(misc);
++}
++
++void mpsys_misc_deregister(struct miscdevice *misc)
++{
++    misc_deregister(misc);
++}
++
++/* system interfaces */
++void mpsys_msleep(unsigned int msecs)
++{
++    msleep(msecs);
++}
++
++/* proc file interfaces */
++struct proc_dir_entry *mpsys_proc_create_data(const char *name, umode_t mode,
++						struct proc_dir_entry *parent,
++						const struct proc_ops *proc_fops,
++						void *data)
++{
++	return proc_create_data(name, mode, parent, proc_fops, data);
++}
++
++ssize_t mpsys_seq_read(struct file *file, char __user *buf, size_t size, loff_t *ppos)
++{
++	return seq_read(file, buf, size, ppos);
++}
++
++loff_t mpsys_seq_lseek(struct file *file, loff_t offset, int whence)
++{
++	return seq_lseek(file, offset, whence);
++}
++
++int mpsys_single_release(struct inode *inode, struct file *file)
++{
++	return single_release(inode, file);
++}
++
++int mpsys_single_open_size(struct file *file, int (*show)(struct seq_file *, void *), void *data, size_t size)
++{
++	return single_open_size(file, show, data, size);
++}
++
++struct proc_dir_entry* mpsys_jz_proc_mkdir(char *s)
++{
++	return jz_proc_mkdir(s);
++}
++
++void mpsys_proc_remove(struct proc_dir_entry *de)
++{
++	proc_remove(de);
++}
++
++void mpsys_remove_proc_entry(const char *name, struct proc_dir_entry *parent)
++{
++	remove_proc_entry(name, parent);
++}
++
++void mpsys_seq_printf(struct seq_file *m, const char *fmt, ...)
++{
++	struct va_format vaf;
++	va_list args;
++	int r = 0;
++	va_start(args, fmt);
++
++	vaf.fmt = fmt;
++	vaf.va = &args;
++
++	seq_printf(m, "%pV", &vaf);
++	r = m->count;
++	va_end(args);
++}
+diff --git a/module_drivers/drivers/video/ingenic-nna/mpsys-firmware/mpsys-funcs.h b/module_drivers/drivers/video/ingenic-nna/mpsys-firmware/mpsys-funcs.h
+new file mode 100755
+index 000000000..512c5c900
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic-nna/mpsys-firmware/mpsys-funcs.h
+@@ -0,0 +1,65 @@
++#ifndef __PRIVATE_FUNCS_H__
++#define __PRIVATE_FUNCS_H__
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/seq_file.h>
++#include <linux/sched.h>
++#include <linux/kernel.h>
++#include <linux/fs.h>
++#include <linux/semaphore.h>
++#include <linux/string.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/miscdevice.h>
++#include <linux/proc_fs.h>
++#include <ingenic_proc.h>
++
++/* semaphore and mutex interfaces */
++int mpsys_down_interruptible(struct semaphore *sem);
++void mpsys_up(struct semaphore *sem);
++void mpsys_mutex_lock(struct mutex *lock);
++void mpsys_mutex_unlock(struct mutex *lock);
++int mpsys_mutex_lock_interruptible(struct mutex *lock);
++
++/* wait interfaces */
++void mpsys_init_completion(struct completion *x);
++void mpsys_complete(struct completion *x);
++int mpsys_wait_for_completion_interruptible(struct completion *x);
++int mpsys_wait_event_interruptible(wait_queue_head_t *wq, int (* state)(void));
++void mpsys_wake_up(wait_queue_head_t *q);
++
++/* mem ops */
++void* mpsys_kzalloc(size_t s, gfp_t gfp);
++void mpsys_kfree(void *p);
++long mpsys_copy_from_user(void *to, const void __user *from, long size);
++long mpsys_copy_to_user(void __user *to, const void *from, long size);
++
++/* file ops */
++struct file* mpsys_filp_open(const char *, int, umode_t);
++int mpsys_filp_close(struct file *filp, fl_owner_t id);
++int mpsys_kernel_read(struct file *file, loff_t *offset, char *addr, size_t count);
++
++/* string ops */
++size_t mpsys_strlen(const char *s);
++int mpsys_kstrtoint(const char *s, unsigned int base, int *res);
++char* mpsys_strstr(const char *s1, const char *s2);
++
++/* misc driver interfaces */
++int mpsys_misc_register(struct miscdevice *misc);
++void mpsys_misc_deregister(struct miscdevice *misc);
++
++/* system interfaces */
++void mpsys_msleep(unsigned int msecs);
++
++/* proc file interfaces */
++struct proc_dir_entry *mpsys_proc_create_data(const char *name, umode_t mode, struct proc_dir_entry *parent,const struct proc_ops *proc_fops, void *data);
++ssize_t mpsys_seq_read(struct file *file, char __user *buf, size_t size, loff_t *ppos);
++loff_t mpsys_seq_lseek(struct file *file, loff_t offset, int whence);
++int mpsys_single_release(struct inode *inode, struct file *file);
++int mpsys_single_open_size(struct file *file, int (*show)(struct seq_file *, void *), void *data, size_t size);
++struct proc_dir_entry* mpsys_jz_proc_mkdir(char *s);
++void mpsys_proc_remove(struct proc_dir_entry *de);
++void mpsys_remove_proc_entry(const char *name, struct proc_dir_entry *parent);
++void mpsys_seq_printf(struct seq_file *m, const char *f, ...);
++
++#endif
+diff --git a/module_drivers/drivers/video/ingenic-nna/mpsys-firmware/mpsys_module.c b/module_drivers/drivers/video/ingenic-nna/mpsys-firmware/mpsys_module.c
+new file mode 100755
+index 000000000..389f5eebb
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic-nna/mpsys-firmware/mpsys_module.c
+@@ -0,0 +1,52 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/miscdevice.h>
++
++extern int mpsys_utils_init(void);
++extern void mpsys_utils_exit(void);
++extern int mpsys_data_init(void);
++extern void mpsys_data_exit(void);
++
++static int __init mpsys_init(void)
++{
++	int ret = 0;
++
++	printk("@@@@@ multi-process system driver init @@@@@\n");
++
++	ret = mpsys_utils_init();
++	if (ret)
++	{
++		printk("mpsys utils init failed!\n");
++		goto err_utils_init;
++	}
++
++	ret = mpsys_data_init();
++	if (ret)
++	{
++		printk("mpsys data init failed!\n");
++		goto err_data_init;
++	}
++
++	return ret;
++
++err_data_init:
++    mpsys_utils_exit();
++err_utils_init:
++	return ret;
++}
++
++static void __exit mpsys_exit(void)
++{
++	printk("@@@@@ multi-process system driver exit @@@@@\n");
++
++	mpsys_utils_exit();
++	mpsys_data_exit();
++}
++
++module_init(mpsys_init);
++module_exit(mpsys_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Wenjie Shi <scott.wjshi@ingenic.com>");
++MODULE_DESCRIPTION("Multi process system, contain lock/nmem alloc/process communication.");
+diff --git a/module_drivers/drivers/video/ingenic-nna/soc_nna.c b/module_drivers/drivers/video/ingenic-nna/soc_nna.c
+new file mode 100644
+index 000000000..76b0f95da
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic-nna/soc_nna.c
+@@ -0,0 +1,883 @@
++#include <linux/module.h>
++#include <linux/miscdevice.h>
++#include <linux/fs.h>
++#include <linux/clk.h>
++#include <linux/syscalls.h>
++#include <linux/slab.h>
++#include <linux/dma-mapping.h>
++#include <linux/version.h>
++#include <linux/dma-map-ops.h>
++#include <linux/dma-direct.h>
++#include <linux/uaccess.h>
++#include "soc_nna_common.h"
++#define MDEVNAME	"soc-nna"
++#define CPU_SIMULATOR
++#define CMD_LINE "/proc/cmdline"
++#define SOC_NNA_VERSION "H20220525"
++static uint64_t soc_nna_dma_mask = ~((uint64_t)0);
++static int nna_clk = 200000000;
++module_param(nna_clk, int, S_IRUGO);
++MODULE_PARM_DESC(nna_clk, "nna clock");
++
++struct buf{
++	uint32_t version_buf;
++	uint32_t nmem_extension_buf;
++	uint32_t nmem_paddr;
++	uint32_t nmem_size;
++};
++struct buf buf;
++struct buf buf_comparison;
++
++#define NNADMA_VA_2_PA(vaddr, paddr) \
++do {                                \
++    __asm__ __volatile__ (          \
++        ".set push\n"               \
++        ".set noreorder\n"          \
++        ".set mips32r2\n"           \
++        " ll %0, 0(%1)\n"           \
++        " rdhwr %0,$4\n"            \
++        ".set reorder\n"            \
++        ".set pop\n"                \
++        :"=r"(paddr)                \
++        :"r"(vaddr)                 \
++        :                           \
++    );                              \
++} while(0)
++
++struct soc_nna {
++    char                name[16];
++    struct miscdevice   mdev;       /* miscdevice */
++    struct device       *dev;
++    int                 refcnt;
++    void __iomem        *iomem;
++    dma_addr_t          dmamem;
++#ifndef CPU_SIMULATOR
++    struct clk          *clk;
++    struct clk          *clk_gate;
++#endif
++    struct mutex        mlock;
++    struct list_head    memory_list;
++    struct kmem_cache   *memory_cache;
++
++    nna_dma_des_info_t  des_info[2];
++};
++
++struct soc_nna_memory_cache {
++    struct list_head    list;
++    struct soc_nna_buf  buf;
++};
++
++int soc_nna_open(struct inode *inode, struct file *file)
++{
++    struct miscdevice *mdev = file->private_data;
++    struct soc_nna *pnna = list_entry(mdev, struct soc_nna, mdev);
++    bool b_first_open = false;
++	unsigned int cp0_status = 0;
++
++    mutex_lock(&pnna->mlock);
++    if (pnna->refcnt++ == 0) {
++        b_first_open = true;
++    }
++    mutex_unlock(&pnna->mlock);
++
++    if (b_first_open) {
++#ifndef CPU_SIMULATOR
++        clk_enable(pnna->clk);
++        clk_enable(pnna->clk_gate);
++#endif
++    }
++
++    __asm__ volatile (" li   $t8, 0xffffffff \n"
++                      " mtc0 $t8, $7, 0		\n"
++					  " mfc0 $t8, $12, 0	\n"
++					  " li $t9, 0x40000000 \n"
++					  " or	$t8, $t8, $t9 \n"
++					  " mtc0 $t8, $12, 0	\n"
++					  " mfc0 %0, $12, 0	\n"
++                      :"=r" (cp0_status):);
++    printk("-------%s(%d): cp0_status=0x%x------\n", __func__, __LINE__, cp0_status);
++
++    dev_info(pnna->mdev.this_device, "%s(%d) [%d:%d]: open sucess, refcnt=%d\n", __func__, __LINE__, current->tgid, current->pid, pnna->refcnt);
++
++    return 0;
++}
++
++int soc_nna_release(struct inode *inode, struct file *file)
++{
++    struct miscdevice *mdev = file->private_data;
++    struct soc_nna *pnna = list_entry(mdev, struct soc_nna, mdev);
++    bool b_last_release = false;
++
++    mutex_lock(&pnna->mlock);
++    if ((pnna->refcnt > 0) && (--pnna->refcnt == 0)) {
++        b_last_release = true;
++    }
++    mutex_unlock(&pnna->mlock);
++
++    if (b_last_release) {
++        struct soc_nna_memory_cache *pelem = NULL;
++        struct list_head *pos = NULL, *n = NULL;
++        mutex_lock(&pnna->mlock);
++        list_for_each_safe(pos, n, &pnna->memory_list) {
++            pelem = list_entry(pos, struct soc_nna_memory_cache, list);
++            list_del(pos);
++            dma_free_coherent(pnna->mdev.this_device, pelem->buf.size, pelem->buf.vaddr, (dma_addr_t)pelem->buf.paddr);
++            kmem_cache_free(pnna->memory_cache, pelem);
++        }
++        mutex_unlock(&pnna->mlock);
++#ifndef CPU_SIMULATOR
++        clk_disable(pnna->clk);
++        clk_disable(pnna->clk_gate);
++#endif
++    }
++
++    dev_info(pnna->mdev.this_device, "%s(%d) [%d:%d]: sucess\n", __func__, __LINE__, current->tgid, current->pid);
++
++    return 0;
++}
++
++static loff_t soc_nna_llseek(struct file *file, loff_t offset, int origin)
++{
++    //TODO
++    return 0;
++}
++
++static ssize_t soc_nna_read(struct file *file, char *buf, size_t size, loff_t *offset)
++{
++    //TODO
++    return 0;
++}
++
++static ssize_t soc_nna_write(struct file *file, const char *buf, size_t size, loff_t *offset)
++{
++    //TODO
++    return 0;
++}
++
++static unsigned int soc_nna_poll(struct file *file, struct poll_table_struct *poll_table)
++{
++    //TODO
++    return 0;
++}
++
++static long soc_nna_malloc(struct soc_nna *pnna, long usr_arg)
++{
++    long ret = 0;
++    struct soc_nna_buf buf;
++    struct soc_nna_memory_cache *pelem = NULL;
++    void *page = NULL, *endpage = NULL;
++	unsigned int cp0_status = 0;
++
++    __asm__ volatile (" li   $t8, 0xffffffff \n"
++                      " mtc0 $t8, $7, 0		\n"
++					  " mfc0 $t8, $12, 0	\n"
++					  " li $t9, 0x40000000 \n"
++					  " or	$t8, $t8, $t9 \n"
++					  " mtc0 $t8, $12, 0	\n"
++					  " mfc0 %0, $12, 0	\n"
++                      :"=r" (cp0_status):);
++    printk("-------%s(%d): cp0_status=0x%x------\n", __func__, __LINE__, cp0_status);
++
++
++	if (copy_from_user(&buf, (void *)usr_arg, sizeof(buf))) {
++        dev_err(pnna->mdev.this_device, "%s(%d) [%d:%d]:copy_from_user failed\n", __func__, __LINE__, current->tgid, current->pid);
++		ret = -EFAULT;
++        goto err_copy_from_user;
++	}
++
++    pelem = kmem_cache_alloc(pnna->memory_cache, GFP_ATOMIC);
++    if (!pelem) {
++        dev_err(pnna->mdev.this_device, "%s(%d) [%d:%d]:kmem_cache_alloc failed\n", __func__, __LINE__, current->tgid, current->pid);
++		ret = -ENOMEM;
++        goto err_kmem_cache_alloc;
++    }
++
++    buf.size = PAGE_ALIGN(buf.size);
++    buf.vaddr = dma_alloc_coherent(pnna->mdev.this_device, buf.size, (dma_addr_t *)&buf.paddr, GFP_KERNEL);
++    if (!buf.vaddr) {
++        dev_err(pnna->mdev.this_device, "%s(%d) [%d:%d]:dma_alloc_coherent failed\n", __func__, __LINE__, current->tgid, current->pid);
++		ret = -ENOMEM;
++        goto err_dma_alloc_coherent;
++    }
++
++    endpage = buf.vaddr + buf.size;
++	for (page = buf.vaddr; page < endpage; page += PAGE_SIZE) {
++		SetPageReserved(virt_to_page(page));
++	}
++    memcpy(&pelem->buf, &buf, sizeof(buf));
++
++    if (copy_to_user((void *)usr_arg, &buf, sizeof(buf))) {
++        dev_err(pnna->mdev.this_device, "%s(%d) [%d:%d]:copy_to_user failed\n", __func__, __LINE__, current->tgid, current->pid);
++		ret = -EFAULT;
++        goto err_copy_to_user;
++    }
++
++    mutex_lock(&pnna->mlock);
++    list_add_tail(&pelem->list, &pnna->memory_list);
++    mutex_unlock(&pnna->mlock);
++
++    dev_info(pnna->mdev.this_device, "%s(%d) [%d:%d]:malloc success, buf.vaddr=%p, buf.paddr=%p, buf.size=0x%x\n", __func__, __LINE__, current->tgid, current->pid, buf.vaddr, buf.paddr, buf.size);
++
++    return 0;
++
++err_copy_to_user:
++    dma_free_coherent(pnna->mdev.this_device, buf.size, buf.vaddr, (dma_addr_t)buf.paddr);
++err_dma_alloc_coherent:
++    kmem_cache_free(pnna->memory_cache, pelem);
++err_kmem_cache_alloc:
++err_copy_from_user:
++    return ret;
++}
++
++static long soc_nna_free(struct soc_nna *pnna, long usr_arg)
++{
++    long ret = -1;
++    struct soc_nna_buf buf;
++    struct soc_nna_memory_cache *pelem = NULL;
++	struct list_head *pos = NULL, *n = NULL;
++
++	if (copy_from_user(&buf, (void *)usr_arg, sizeof(buf))) {
++        dev_err(pnna->mdev.this_device, "%s(%d) [%d:%d]:copy_from_user failed\n", __func__, __LINE__, current->tgid, current->pid);
++		return -EFAULT;
++	}
++
++    mutex_lock(&pnna->mlock);
++	list_for_each_safe(pos, n, &pnna->memory_list) {
++		pelem = list_entry(pos, struct soc_nna_memory_cache, list);
++        if ((pelem->buf.vaddr == buf.vaddr) && (pelem->buf.paddr == buf.paddr)) {
++            list_del(pos);
++            dma_free_coherent(pnna->mdev.this_device, pelem->buf.size, pelem->buf.vaddr, (dma_addr_t)pelem->buf.paddr);
++            kmem_cache_free(pnna->memory_cache, pelem);
++            dev_info(pnna->mdev.this_device, "%s(%d) [%d:%d]:free success, buf.vaddr=%p, buf.paddr=%p, buf.size=0x%x\n", __func__, __LINE__, current->tgid, current->pid, buf.vaddr, buf.paddr, buf.size);
++            ret = 0;
++            break;
++        }
++	}
++    mutex_unlock(&pnna->mlock);
++
++    return ret;
++}
++
++long soc_nna_flushcache(struct soc_nna *pnna, long usr_arg)
++{
++	struct flush_cache_info info;
++	if (copy_from_user(&info, (void *)usr_arg, sizeof(info))) {
++        dev_err(pnna->mdev.this_device, "%s(%d) [%d:%d]:copy_from_user failed\n", __func__, __LINE__, current->tgid, current->pid);
++		return -EFAULT;
++	}
++	/* printk("cache dir = %d >>>>>>>>>>>\n",info.dir); */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,10, 0)
++		/* arch_sync_dma_for_device(paddr,info.len,info.dir); */
++		if(info.dir == DMA_BIDIRECTIONAL)
++			dma_cache_wback_inv(info.addr ,info.len);
++		else if(info.dir == DMA_TO_DEVICE){
++			dma_cache_wback(info.addr,info.len);
++		} else {
++			dma_cache_inv(info.addr,info.len);
++		}
++#else
++		dma_cache_sync(NULL, (void *)info.addr, info.len, info.dir);
++#endif
++    /* dev_err(pnna->mdev.this_device, "%s(%d) [%d:%d]:flush cache success\n", __func__, __LINE__, current->tgid, current->pid); */
++
++    return 0;
++}
++
++static void soc_nna_analysis_des(struct soc_nna *pnna, unsigned int st_idx, unsigned int cmd_cnt, nna_dma_cmd_t *d_va_cmd, nna_dma_des_info_t *des_info)
++{
++    int i = 0, j = 0;
++    int c64kcnt = 0;
++    unsigned int remain_bytes = 0, trans_bytes = 0, last_des = 0, cur_trans_bytes = 0, total_bytes = 0;
++    unsigned int d_pa_st_addr = 0, o_pa_st_addr = 0, o_pa_mlc_addr = 0, o_pa_mlc_end_addr = 0;
++    nna_dma_cmd_t *pcmd = NULL;
++    unsigned int widx = 0, des_num = 0, chain_st_idx = st_idx;
++
++    memset(des_info, 0, sizeof(nna_dma_des_info_t));
++
++    for (i = st_idx; i < cmd_cnt; i++) {
++        pcmd = d_va_cmd + i;
++        c64kcnt = ((pcmd->data_bytes - 1) >> 16) + 1;
++        remain_bytes = pcmd->data_bytes;
++        NNADMA_VA_2_PA(pcmd->d_va_st_addr, d_pa_st_addr);
++        NNADMA_VA_2_PA(pcmd->o_va_st_addr, o_pa_st_addr);
++        NNADMA_VA_2_PA(pcmd->o_va_mlc_addr, o_pa_mlc_addr);
++        o_pa_mlc_end_addr = o_pa_mlc_addr + pcmd->o_mlc_bytes;
++
++        for (j = 0; j < c64kcnt; j++) {
++            last_des = (j == (c64kcnt - 1)) ? 1 : 0;
++            trans_bytes = last_des ? remain_bytes : 65536;
++
++            if ((o_pa_st_addr + trans_bytes) <= o_pa_mlc_end_addr) {
++                des_info->des_data[widx++] = ((((last_des && !pcmd->des_link) ? DES_CFG_END : DES_CFG_LINK) << DES_CFG_FLAG) & DES_CFG_FLAG_MASK)
++                    | (((((unsigned long long int)trans_bytes >> SOC_NNA_ADDR_ALIGN_BIT) - 1ULL) << DES_DATA_LEN) & DES_DATA_LEN_MASK)
++                    | ((((unsigned long long int)o_pa_st_addr >> SOC_NNA_ADDR_ALIGN_BIT) << DES_ORAM_ADDR) & DES_ORAM_ADDR_MASK)
++                    | ((((unsigned long long int)d_pa_st_addr >> SOC_NNA_ADDR_ALIGN_BIT) << DES_DDR_ADDR) & DES_DDR_ADDR_MASK);
++                d_pa_st_addr += trans_bytes;
++                o_pa_st_addr += trans_bytes;
++                des_num++;
++            } else {
++                cur_trans_bytes = o_pa_mlc_end_addr - o_pa_st_addr;
++                des_info->des_data[widx++] = ((DES_CFG_LINK << DES_CFG_FLAG) & DES_CFG_FLAG_MASK)
++                    | (((((unsigned long long int)cur_trans_bytes >> SOC_NNA_ADDR_ALIGN_BIT) - 1ULL) << DES_DATA_LEN) & DES_DATA_LEN_MASK)
++                    | ((((unsigned long long int)o_pa_st_addr >> SOC_NNA_ADDR_ALIGN_BIT) << DES_ORAM_ADDR) & DES_ORAM_ADDR_MASK)
++                    | ((((unsigned long long int)d_pa_st_addr >> SOC_NNA_ADDR_ALIGN_BIT) << DES_DDR_ADDR) & DES_DDR_ADDR_MASK);
++
++                des_info->des_data[widx++] = ((((last_des && !pcmd->des_link) ? DES_CFG_END : DES_CFG_LINK) << DES_CFG_FLAG) & DES_CFG_FLAG_MASK)
++                    | (((((unsigned long long int)(trans_bytes - cur_trans_bytes) >> SOC_NNA_ADDR_ALIGN_BIT) - 1ULL) << DES_DATA_LEN) & DES_DATA_LEN_MASK)
++                    | ((((unsigned long long int)o_pa_mlc_addr >> SOC_NNA_ADDR_ALIGN_BIT) << DES_ORAM_ADDR) & DES_ORAM_ADDR_MASK)
++                    | ((((unsigned long long int)(d_pa_st_addr + cur_trans_bytes) >> SOC_NNA_ADDR_ALIGN_BIT) << DES_DDR_ADDR) & DES_DDR_ADDR_MASK);
++                d_pa_st_addr += trans_bytes;
++                o_pa_st_addr = o_pa_mlc_addr + (trans_bytes - cur_trans_bytes);
++                des_num += 2;
++            }
++            remain_bytes -= trans_bytes;
++        }
++
++        total_bytes += pcmd->data_bytes;
++        if (!pcmd->des_link) {
++            des_info->des_num[des_info->chain_num] = des_num;
++            des_info->total_bytes[des_info->chain_num] = total_bytes;
++            des_info->chain_st_idx[des_info->chain_num] = chain_st_idx;
++            des_info->chain_num++;
++            des_num = 0;
++            total_bytes = 0;
++            chain_st_idx = i + 1;
++        }
++    }
++}
++
++static void soc_nna_update_des(struct soc_nna *pnna, unsigned int *d_va_chn, des_gen_result_t *des_rslt)
++{
++    nna_dma_des_info_t *des_info = pnna->des_info;
++    int des_remain = 2048; //(16 * 1024) / sizeof(unsigned long long int);
++    int chnidx = 0, desidx = 0, destotal_chain = 0, rdidx = 0, wridx = 0;
++    int maxchnnum = des_info[0].chain_num > des_info[1].chain_num ? des_info[0].chain_num : des_info[1].chain_num;
++    unsigned long long int *vdma = (unsigned long long int *)pnna->dmamem;
++    memset(des_rslt, 0, sizeof(des_gen_result_t));
++
++    for (chnidx = 0; chnidx < maxchnnum; chnidx++) {
++        destotal_chain = des_info[0].des_num[chnidx] + des_info[1].des_num[chnidx] + 2;
++        if (destotal_chain > des_remain) {
++            des_rslt->rcmd_st_idx = des_info[0].chain_st_idx[chnidx];
++            des_rslt->wcmd_st_idx = des_info[1].chain_st_idx[chnidx];
++            des_rslt->dma_chn_num = chnidx;
++            des_rslt->finish = 0;
++            return;
++        }
++
++        /* rd chain */
++        *d_va_chn++ = desidx;
++        *(vdma + desidx++) = ((DES_CFG_CNT << DES_CFG_FLAG) & DES_CFG_FLAG_MASK)
++            | ((des_info[0].total_bytes[chnidx] << DES_TOTAL_BYTES) & DES_TOTAL_BYTES_MASK);
++        memcpy(vdma + desidx, &(des_info[0].des_data[rdidx]), 8 * des_info[0].des_num[chnidx]);
++        desidx += des_info[0].des_num[chnidx];
++        rdidx += des_info[0].des_num[chnidx];
++
++        /* wr chain */
++        *d_va_chn++ = desidx;
++        *(vdma + desidx++) = ((DES_CFG_CNT << DES_CFG_FLAG) & DES_CFG_FLAG_MASK)
++            | ((des_info[1].total_bytes[chnidx] << DES_TOTAL_BYTES) & DES_TOTAL_BYTES_MASK);
++        memcpy(vdma + desidx, &(des_info[1].des_data[wridx]), 8 * des_info[1].des_num[chnidx]);
++        desidx += des_info[1].des_num[chnidx];
++        wridx += des_info[1].des_num[chnidx];
++
++        des_remain -= destotal_chain;
++    }
++
++    des_rslt->dma_chn_num = maxchnnum;
++    des_rslt->finish = 1;
++}
++
++long soc_nna_setup_des(struct soc_nna *pnna, long usr_arg)
++{
++    long ret = 0;
++    nna_dma_cmd_set_t cmd_set;
++    nna_dma_cmd_t *d_va_cmd = NULL, *d_pa_cmd = NULL;
++    unsigned int d_pa_chn = 0;
++    unsigned int *d_va_chn = NULL;
++
++	if (copy_from_user(&cmd_set, (void *)usr_arg, sizeof(nna_dma_cmd_set_t))) {
++        dev_err(pnna->mdev.this_device, "%s(%d) [%d:%d]:copy_from_user failed\n", __func__, __LINE__, current->tgid, current->pid);
++		ret = -EFAULT;
++        goto err_copy_from_user;
++	}
++
++    mutex_lock(&pnna->mlock);
++
++    NNADMA_VA_2_PA((unsigned long)cmd_set.d_va_cmd, d_pa_cmd);      //convert user space vaddr to paddr
++    d_va_cmd = phys_to_virt((unsigned long)d_pa_cmd);               //map paddr to kernel space vaddr to be used by kernel
++
++    NNADMA_VA_2_PA((unsigned long)cmd_set.d_va_chn, d_pa_chn);      //convert user space vaddr to paddr
++    d_va_chn = phys_to_virt((unsigned long)d_pa_chn);               //map paddr to kernel space vaddr to be used by kernel
++
++    soc_nna_analysis_des(pnna, cmd_set.rd_cmd_st_idx, cmd_set.rd_cmd_cnt, d_va_cmd, &(pnna->des_info[0]));
++    soc_nna_analysis_des(pnna, cmd_set.wr_cmd_st_idx, cmd_set.wr_cmd_cnt, d_va_cmd + cmd_set.rd_cmd_cnt, &(pnna->des_info[1]));
++
++    soc_nna_update_des(pnna, d_va_chn, &cmd_set.des_rslt);
++    mutex_unlock(&pnna->mlock);
++
++	if (copy_to_user((void *)usr_arg, &cmd_set, sizeof(nna_dma_cmd_set_t))) {
++        dev_err(pnna->mdev.this_device, "%s(%d) [%d:%d]:copy_to_user failed\n", __func__, __LINE__, current->tgid, current->pid);
++		ret = -EFAULT;
++        goto err_copy_to_user;
++	}
++
++    return 0;
++
++err_copy_to_user:
++err_copy_from_user:
++    return ret;
++}
++
++long soc_nna_rdchn_start(struct soc_nna *pnna, long usr_arg)
++{
++    dma_addr_t dma_addr = 0;
++
++	if (copy_from_user(&dma_addr, (void *)usr_arg, sizeof(dma_addr_t))) {
++        dev_err(pnna->mdev.this_device, "%s(%d) [%d:%d]:copy_from_user failed\n", __func__, __LINE__, current->tgid, current->pid);
++		return -EFAULT;
++	}
++
++    soc_nna_writel(pnna, NNA_DMA_RCFG, ((dma_addr << RCFG_DES_ADDR) & RCFG_DES_ADDR_MASK) | (1 << RCFG_START));
++
++    return 0;
++}
++
++long soc_nna_wrchn_start(struct soc_nna *pnna, long usr_arg)
++{
++    dma_addr_t dma_addr = 0;
++
++	if (copy_from_user(&dma_addr, (void *)usr_arg, sizeof(dma_addr_t))) {
++        dev_err(pnna->mdev.this_device, "%s(%d) [%d:%d]:copy_from_user failed\n", __func__, __LINE__, current->tgid, current->pid);
++		return -EFAULT;
++	}
++
++    soc_nna_writel(pnna, NNA_DMA_WCFG, ((dma_addr << WCFG_DES_ADDR) & WCFG_DES_ADDR_MASK) | (1 << WCFG_START));
++
++    return 0;
++}
++int soc_nna_version(struct soc_nna *pnna, long usr_arg)
++{
++	long ret = 0;
++	uint32_t soc_version_buf = 0x20220525;
++	memcpy(&buf_comparison, (int *)usr_arg, sizeof(uint32_t));
++
++	if (copy_from_user(&buf, (void __user *)usr_arg, sizeof(struct buf))) {
++		printk("copy_from_user nmem_extension_size error %d\n", __LINE__);
++		ret = -EFAULT;
++	}
++
++	buf.version_buf = soc_version_buf;
++	if (copy_to_user((void __user *)usr_arg, &buf, sizeof(struct buf))) {
++		printk("copy_to_user version error %d\n", __LINE__);
++		ret = -EFAULT;
++	}
++	return ret;
++}
++
++static long soc_nna_unlocked_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
++{
++    long ret = -1;
++    struct miscdevice *mdev = file->private_data;
++    struct soc_nna *pnna = list_entry(mdev, struct soc_nna, mdev);
++
++	switch (cmd) {
++        case IOCTL_SOC_NNA_MALLOC:
++            ret = soc_nna_malloc(pnna, arg);
++            break;
++        case IOCTL_SOC_NNA_FREE:
++            ret = soc_nna_free(pnna, arg);
++            break;
++        case IOCTL_SOC_NNA_FLUSHCACHE:
++            ret = soc_nna_flushcache(pnna, arg);
++            break;
++        case IOCTL_SOC_NNA_SETUP_DES:
++            ret = soc_nna_setup_des(pnna, arg);
++            break;
++        case IOCTL_SOC_NNA_RDCH_START:
++            ret = soc_nna_rdchn_start(pnna, arg);
++            break;
++        case IOCTL_SOC_NNA_WRCH_START:
++            ret = soc_nna_wrchn_start(pnna, arg);
++			break;
++		case IOCTL_SOC_NNA_VERSION:
++			ret = soc_nna_version(pnna, arg);
++            break;
++        default:
++            dev_err(mdev->this_device, "%s(%d) [%d:%d]: unsupport cmd=0x%x\n", __func__, __LINE__, current->tgid, current->pid, cmd);
++            return -1;
++    }
++
++    return ret;
++}
++
++/**
++ * According to mips memory architecture, the user space range is [0x00000000 ~ 0x800000000], but the io memory is [0x10000000 to 0x20000000];
++ * the io memory should be mapped to uncached.
++ * Because nna dma descript memory [0x12500000 ~ 0x12504000 ] and oram memory [0x12600000 ~ 0x12700000] is data communication memory, so mmaps
++ * they to uncached accelerated
++ */
++#if 1
++
++static int get_nmem_info(uint32_t * nmem_addr, uint32_t * nmem_size)
++{
++	int ret;
++	char * cmdline = NULL;
++	char *p = NULL;
++	char *retptr;
++
++	cmdline = kzalloc(512, GFP_KERNEL);
++	if (!cmdline)
++	{
++		printk("%s: mpsys_kzalloc mem failed!\n", __func__);
++		ret = -ENOMEM;
++	}else{
++
++		sprintf(cmdline,"%s", saved_command_line);
++		//printk("%s\n", cmdline);
++		p = strstr(cmdline, "nmem");
++		if(p == NULL) {
++
++			printk("fread (%s) error\n", CMD_LINE);
++			ret = -EINVAL;
++		}
++
++		*nmem_size = memparse(p + 5, &retptr);
++
++		if (*retptr == '@')
++			*nmem_addr = memparse(retptr + 1, NULL);
++
++		kfree(cmdline);
++	}
++
++	return ret;
++}
++
++#endif
++static int soc_nna_mmap(struct file *file, struct vm_area_struct *vma)
++{
++	uint32_t nmem_addr = 0;
++	uint32_t nmem_size = 0;
++	uint32_t n = 0, set_oram_nums = 0;
++    struct miscdevice *mdev = file->private_data;
++	unsigned long paddr_start = vma->vm_pgoff << PAGE_SHIFT;
++	unsigned long paddr_end = paddr_start + vma->vm_end - vma->vm_start;
++	unsigned int oram_size_cmd_t = 0, oram_real_size = 0;
++	unsigned int l2cache_size = 0;
++	uint32_t mmap_type = 0;
++	uint32_t extend = 0;
++	/* 设置 pfn的属性 */
++	vma->vm_flags |= VM_IO;
++	get_nmem_info(&nmem_addr, &nmem_size);
++
++	/* 根�地�区分地�的类型 */
++	if(paddr_start == 0x12620000){
++		mmap_type = 1;//oram
++		extend = 0;
++	}else if(paddr_start == 0x12500000){
++		mmap_type = 2; //descram
++		extend = 0;
++	}else if((paddr_start < 0x12620000 ) && (paddr_end > 0x12620000)) {
++		mmap_type = 1; //oram
++		extend = 1;
++	} else {
++		mmap_type = 3;// nmem
++		if(paddr_start == nmem_addr)
++		{
++			extend = 0;
++		} else {
++			extend = 1;
++		}
++	}
++
++	/* l2cache_size + ORAM = 1*1024*1024 这里是获�l2cache size，根�l2cache size�得到ORAM size */
++	oram_size_cmd_t = *((volatile unsigned int *)(0xb2200060));
++	switch((oram_size_cmd_t & 0x1c00) >> 10)
++	{
++		case 1:
++			l2cache_size = 128;
++			oram_real_size = 1024 - l2cache_size;
++			break;
++		case 2:
++			l2cache_size = 256;
++			oram_real_size = 1024 - l2cache_size;
++			break;
++		case 3:
++			l2cache_size = 512;
++			oram_real_size = 1024 - l2cache_size;
++			break;
++		case 4:
++			l2cache_size = 1024;
++			oram_real_size = 1024 - l2cache_size;
++			break;
++		default:
++			break;
++	}
++
++	/* 根���虚拟地�的类型�设置属性 */
++	if(mmap_type != 3){
++		pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
++		pgprot_val(vma->vm_page_prot) |= _CACHE_UNCACHED_ACCELERATED;
++	}else{
++		pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
++		pgprot_val(vma->vm_page_prot) |= _CACHE_CACHABLE_WB_WA;
++	}
++
++	/* 根�上层传过�的地�，�判断需�需�扩充映射的虚拟地�的大�，extent=0 �需�扩充映射；extent=1 扩充映射 */
++	if (extend == 0){
++		if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, vma->vm_end - vma->vm_start, vma->vm_page_prot)) {
++			dev_err(mdev->this_device, "%s(%d) [%d:%d]: io_remap_pfn_range failed\n", __func__, __LINE__, current->tgid, current->pid);
++			return -EAGAIN;
++		}
++	}else {
++		unsigned int real_paddr = 0x12620000;
++		unsigned int real_size = oram_real_size * 1024;//896 * 1024
++		unsigned int before_s = 0;
++		unsigned int after_s = 0;
++		if(mmap_type !=1)//oram
++		{
++			if(buf_comparison.version_buf == 0)
++			{
++				real_size = nmem_size;
++				real_paddr = nmem_addr;
++			}else{
++				real_size = buf.nmem_size;
++				real_paddr = buf.nmem_paddr;
++			}
++		}
++			/*根�上层传过�扩充映射内存的大�和ORAM size，��处�，�次映射的区域�能超过实际的物�大�，�改�物�地�，根�虚拟地��移多次映射�达到扩充虚拟地�的目的 */
++			before_s = real_paddr - paddr_start;
++			//if(before_s > nmem_size)
++			//	goto error_set_nmem_size;
++			set_oram_nums = before_s / real_size;
++			set_oram_nums += before_s%real_size ? 1 : 0;
++			for(n = 0 ; n < set_oram_nums; n++){
++				if (io_remap_pfn_range(vma, vma->vm_start + n * real_size, real_paddr>>PAGE_SHIFT, (before_s % real_size)&&(n == (set_oram_nums -1)) ? before_s % real_size : real_size , vma->vm_page_prot)) {
++					dev_err(mdev->this_device, "%s(%d) [%d:%d]: io_remap_pfn_range failed\n", __func__, __LINE__, current->tgid, current->pid);
++					return -EAGAIN;
++				}
++			}
++			if (io_remap_pfn_range(vma, vma->vm_start + before_s, real_paddr>>PAGE_SHIFT, real_size, vma->vm_page_prot)) {
++				dev_err(mdev->this_device, "%s(%d) [%d:%d]: io_remap_pfn_range failed\n", __func__, __LINE__, current->tgid, current->pid);
++				return -EAGAIN;
++			}
++			after_s = paddr_end - real_paddr - real_size;
++			//if(after_s > nmem_size)
++			//	goto error_set_nmem_size;
++			set_oram_nums = after_s / real_size;
++			set_oram_nums += after_s % real_size ? 1 : 0;
++			for(n = 0; n < set_oram_nums ; n++){
++				if (io_remap_pfn_range(vma, vma->vm_start+ before_s + real_size * (n + 1) , real_paddr>>PAGE_SHIFT,(after_s % real_size)&&(n == (set_oram_nums -1)) ? after_s % real_size : real_size, vma->vm_page_prot)) {
++					dev_err(mdev->this_device, "%s(%d) [%d:%d]: io_remap_pfn_range failed\n", __func__, __LINE__, current->tgid, current->pid);
++					return -EAGAIN;
++				}
++			}
++	}
++	return 0;
++}
++
++static const struct file_operations soc_nna_fops = {
++	.owner          = THIS_MODULE,
++	.open           = soc_nna_open,
++	.release        = soc_nna_release,
++	.llseek         = soc_nna_llseek,
++	.read           = soc_nna_read,
++	.write          = soc_nna_write,
++	.poll           = soc_nna_poll,
++	.unlocked_ioctl	= soc_nna_unlocked_ioctl,
++	.mmap           = soc_nna_mmap,
++};
++
++static int soc_nna_probe(struct platform_device *pdev)
++{
++    int ret = 0;
++    struct soc_nna *pnna = NULL;
++    struct resource *res = NULL;
++    unsigned int oram_clk = 0;
++
++    pnna = (struct soc_nna *)kzalloc(sizeof(struct soc_nna), GFP_KERNEL);
++    if (!pnna) {
++        dev_err(&pdev->dev, "kzalloc struct soc_nna failed\n");
++        ret = -ENOMEM;
++        goto err_kzalloc_soc_nna;
++    }
++
++    pdev->dev.dma_mask = &soc_nna_dma_mask;
++    pdev->dev.coherent_dma_mask = 0xffffffff;
++
++    pnna->mdev.minor = MISC_DYNAMIC_MINOR;
++    pnna->mdev.name = MDEVNAME;
++    pnna->mdev.fops = &soc_nna_fops;
++    pnna->dev = &pdev->dev;
++
++    mutex_init(&pnna->mlock);
++
++    INIT_LIST_HEAD(&pnna->memory_list);
++    pnna->memory_cache = kmem_cache_create(pnna->name, sizeof(struct soc_nna_memory_cache), 0, SLAB_HWCACHE_ALIGN, NULL);
++    if (!pnna->memory_cache) {
++        printk("%s:kmem_cache_create failed\n", __func__);
++        ret = -ENOMEM;
++        goto err_kmem_cache_create;
++    }
++
++    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++    if (!res) {
++        dev_err(&pdev->dev, "no iomem resource\n");
++        ret = -ENXIO;
++        goto err_get_iomem_resource;
++    }
++
++    pnna->iomem = ioremap(res->start, resource_size(res));
++    if (!pnna->iomem) {
++        dev_err(&pdev->dev, "ioremap iomem resource failed\n");
++        ret = -EPERM;
++        goto err_ioremap_iomem;
++    }
++
++    res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++    if (!res) {
++        dev_err(&pdev->dev, "no dmamem resource\n");
++        ret = -ENXIO;
++        goto err_get_dmamem_resource;
++    }
++
++    pnna->dmamem = (dma_addr_t)ioremap(res->start, resource_size(res));
++    if (!pnna->iomem) {
++        dev_err(&pdev->dev, "ioremap dmamem resource failed\n");
++        ret = -EPERM;
++        goto err_ioremap_dmamem;
++    }
++
++#ifndef CPU_SIMULATOR
++    pnna->clk = clk_get(&pdev->dev, "cgu_nna");
++    if (IS_ERR(pnna->clk)) {
++        dev_err(&pdev->dev, "get cgu nna clk failed\n");
++        ret = PTR_ERR(pnna->clk);
++        goto err_clk_get_cgu_nna;
++    }
++    clk_set_rate(pnna->clk, nna_clk);
++
++    pnna->clk_gate = clk_get(&pdev->dev, "nna");
++    if (IS_ERR(pnna->clk_gate)) {
++        dev_err(&pdev->dev, "get gate nna clk failed\n");
++        ret = PTR_ERR(pnna->clk_gate);
++        goto err_clk_get_gate_nna;
++    }
++#endif
++
++    platform_set_drvdata(pdev, pnna);
++
++    ret = misc_register(&pnna->mdev);
++    if (ret < 0) {
++        dev_err(&pdev->dev, "register misc device failed\n");
++        goto err_misc_register;
++    }
++
++    oram_clk = *(volatile unsigned int*)0xb2200060;
++    *(volatile unsigned int *)0xb2200060 = oram_clk | (1 << 5);
++    printk("%s success\n", __func__);
++
++    return 0;
++
++err_misc_register:
++#ifndef CPU_SIMULATOR
++    clk_put(pnna->clk_gate);
++err_clk_get_gate_nna:
++    clk_put(pnna->clk);
++err_clk_get_cgu_nna:
++#endif
++    iounmap((void *)pnna->dmamem);
++err_ioremap_dmamem:
++err_get_dmamem_resource:
++    iounmap(pnna->iomem);
++err_ioremap_iomem:
++err_get_iomem_resource:
++    kmem_cache_destroy(pnna->memory_cache);
++err_kmem_cache_create:
++    kfree(pnna);
++err_kzalloc_soc_nna:
++    return ret;
++}
++
++static int __exit soc_nna_remove(struct platform_device *pdev)
++{
++    struct soc_nna *pnna = platform_get_drvdata(pdev);
++    if (pnna) {
++        misc_deregister(&pnna->mdev);
++#ifndef CPU_SIMULATOR
++        clk_put(pnna->clk_gate);
++        clk_put(pnna->clk);
++#endif
++        iounmap((void *)pnna->dmamem);
++        iounmap(pnna->iomem);
++        kmem_cache_destroy(pnna->memory_cache);
++        kfree(pnna);
++    }
++
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int soc_nna_suspend(struct device *pdev)
++{
++    //TODO
++	return 0;
++}
++
++static int soc_nna_resume(struct device *pdev)
++{
++    //TODO
++	return 0;
++}
++
++static const struct dev_pm_ops soc_nna_pm_ops = {
++    .suspend = soc_nna_suspend,
++    .resume = soc_nna_resume,
++};
++#endif
++static struct of_device_id soc_nna_match[] = {
++	{.compatible = "ingenic,soc-nna",.data = NULL},
++	{ },
++};
++static struct platform_driver soc_nna_driver = {
++    .probe = soc_nna_probe,
++    .remove = soc_nna_remove,
++    .driver = {
++        .name = "soc-nna",
++        .owner = THIS_MODULE,
++	.of_match_table = of_match_ptr(soc_nna_match),
++#ifdef CONFIG_PM
++        .pm = &soc_nna_pm_ops,
++#endif
++    },
++};
++
++static int __init soc_nna_init(void)
++{
++	int ret = 0;
++	ret = platform_driver_register(&soc_nna_driver);
++	if(ret){
++		printk("%s platform_driver_register failed:ret=0x%x\n", __func__, ret);
++		goto err;
++	}
++	//printk("%s success\n", __func__);
++
++	return 0;
++err:
++	return ret;
++}
++
++static void __exit soc_nna_exit(void)
++{
++	platform_driver_unregister(&soc_nna_driver);
++	printk("%s success\n", __func__);
++}
++
++module_init(soc_nna_init);
++module_exit(soc_nna_exit);
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Justin <pengtao.kang@ingenic.com>");
++MODULE_DESCRIPTION("Ingenic soc nna driver");
++MODULE_ALIAS("platform:soc-nna");
++MODULE_VERSION("20190724a");
+diff --git a/module_drivers/drivers/video/ingenic-nna/soc_nna.h b/module_drivers/drivers/video/ingenic-nna/soc_nna.h
+new file mode 100644
+index 000000000..01d871d61
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic-nna/soc_nna.h
+@@ -0,0 +1,65 @@
++#ifndef __SOC_NNA_H__
++#define __SOC_NNA_H__
++
++#include <stdbool.h>
++
++#define SOC_NNA_DEVICE_NAME         "/dev/soc-nna"
++#define SOC_NNA_MAX_CHN_CNT         2048    //16*1024/8=2048
++
++/* oram information */
++#define NNA_ORAM_BASE_ADDR      0x12600000
++#define NNA_ORAM_BASE_SIZE      0xe0000         //(1024-128)*1024
++
++/* IOCTL MACRO DEFINE PLACE */
++#define SOC_NNA_MAGIC               'c'
++#define IOCTL_SOC_NNA_MALLOC        _IOWR(SOC_NNA_MAGIC, 0, int)
++#define IOCTL_SOC_NNA_FREE          _IOWR(SOC_NNA_MAGIC, 1, int)
++#define IOCTL_SOC_NNA_FLUSHCACHE    _IOWR(SOC_NNA_MAGIC, 2, int)
++#define IOCTL_SOC_NNA_SETUP_DES     _IOWR(SOC_NNA_MAGIC, 3, int)
++#define IOCTL_SOC_NNA_RDCH_START    _IOWR(SOC_NNA_MAGIC, 4, int)
++#define IOCTL_SOC_NNA_WRCH_START    _IOWR(SOC_NNA_MAGIC, 5, int)
++#define IOCTL_SOC_NNA_VERSION    	_IOWR(SOC_NNA_MAGIC, 6, int)
++
++/*
++ * dir value defined in  enum dma_data_direction in linux/dma-direction.h
++ * 0:DMA_BIDIRECTIONAL, 1:DMA_TO_DEVICE, 2:DMA_FROM_DEVICE
++ */
++struct flush_cache_info {
++	unsigned int	addr;
++	unsigned int	len;
++	unsigned int	dir;
++};
++
++struct soc_nna_buf {
++    void        *vaddr;
++    void        *paddr;
++    int         size;
++};
++
++typedef struct nna_dma_cmd {
++    unsigned int    d_va_st_addr;
++    unsigned int    o_va_st_addr;
++    unsigned int    o_va_mlc_addr;
++    unsigned int    o_mlc_bytes;
++    unsigned int    data_bytes;
++    unsigned int    des_link;
++} nna_dma_cmd_t;
++
++typedef struct des_gen_result {
++    unsigned int    rcmd_st_idx;
++    unsigned int    wcmd_st_idx;
++    unsigned int    dma_chn_num;
++    unsigned int    finish;
++} des_gen_result_t;
++
++typedef struct nna_dma_cmd_set {
++    unsigned int        rd_cmd_cnt;
++    unsigned int        rd_cmd_st_idx;
++    unsigned int        wr_cmd_cnt;
++    unsigned int        wr_cmd_st_idx;
++    nna_dma_cmd_t       *d_va_cmd;
++    unsigned int        *d_va_chn;
++    des_gen_result_t    des_rslt;
++} nna_dma_cmd_set_t;
++
++#endif
+diff --git a/module_drivers/drivers/video/ingenic-nna/soc_nna_common.h b/module_drivers/drivers/video/ingenic-nna/soc_nna_common.h
+new file mode 100644
+index 000000000..c1369f435
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic-nna/soc_nna_common.h
+@@ -0,0 +1,24 @@
++#ifndef __SOC_NNA_COMMON_H__
++#define __SOC_NNA_COMMON_H__
++
++#include <linux/platform_device.h>
++
++#include "soc_nna.h"
++#include "soc_nna_hw.h"
++
++extern struct platform_device soc_nna_device;
++#define SOC_NNA_MAX_DES_CHN_CNT     2048        //16384 / 8 = 2048
++#define SOC_NNA_ADDR_ALIGN_BIT      6LL
++
++typedef struct nna_dma_des_info {
++    unsigned long long int      des_data[SOC_NNA_MAX_DES_CHN_CNT];
++    unsigned int                des_num[SOC_NNA_MAX_DES_CHN_CNT];
++    unsigned int                total_bytes[SOC_NNA_MAX_DES_CHN_CNT];
++    unsigned int                chain_st_idx[SOC_NNA_MAX_DES_CHN_CNT];
++    unsigned int                chain_num;
++} nna_dma_des_info_t;
++
++#define soc_nna_readl(pnna, offset)           __raw_readl((pnna)->iomem + (offset))
++#define soc_nna_writel(pnna, offset, value)   __raw_writel((value), (pnna)->iomem + (offset))
++
++#endif //__SOC_NNA_COMMON_H__
+diff --git a/module_drivers/drivers/video/ingenic-nna/soc_nna_hw.h b/module_drivers/drivers/video/ingenic-nna/soc_nna_hw.h
+new file mode 100644
+index 000000000..a84ef4c8e
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic-nna/soc_nna_hw.h
+@@ -0,0 +1,40 @@
++#ifndef __SOC_NNA_HW_H__
++#define __SOC_NNA_HW_H__
++
++#define SOC_NNA_DMA_IOBASE          0x12502000
++#define SOC_NNA_DMA_IOSIZE          0x1000
++
++#define SOC_NNA_DMA_DESRAM_ADDR     0x1250f000
++#define SOC_NNA_DMA_DESRAM_SIZE     0x4000          //16*1024
++
++#define NNA_DMA_RCFG            0x0
++#define NNA_DMA_WCFG            0x4
++#define NNA_DMA_RCNT            0x8
++#define NNA_DMA_WCNT            0xc
++
++/* NNA_DMA_RCFG */
++#define RCFG_START              0
++#define RCFG_DES_ADDR           1
++#define RCFG_DES_ADDR_MASK      (0x7ff << (RCFG_DES_ADDR))
++
++/* NNA_DMA_WCFG */
++#define WCFG_START              0
++#define WCFG_DES_ADDR           1
++#define WCFG_DES_ADDR_MASK      (0x7ff << (WCFG_DES_ADDR))
++
++#define DES_CFG_FLAG            50ULL
++#define DES_CFG_FLAG_MASK       (0x3ULL << (DES_CFG_FLAG))
++#define DES_CFG_CNT             0ULL
++#define DES_CFG_LINK            1ULL
++#define DES_CFG_END             2ULL
++
++#define DES_TOTAL_BYTES         0ULL
++#define DES_TOTAL_BYTES_MASK    (0xfffffULL << (DES_TOTAL_BYTES))
++#define DES_DATA_LEN            40ULL
++#define DES_DATA_LEN_MASK       (0x3ffULL << (DES_DATA_LEN))
++#define DES_ORAM_ADDR           26ULL
++#define DES_ORAM_ADDR_MASK      (0x3fffULL << (DES_ORAM_ADDR))
++#define DES_DDR_ADDR            0ULL
++#define DES_DDR_ADDR_MASK       (0x3ffffffULL << (DES_DDR_ADDR))
++
++#endif
+diff --git a/module_drivers/drivers/video/ingenic_avpu/Kconfig b/module_drivers/drivers/video/ingenic_avpu/Kconfig
+new file mode 100644
+index 000000000..ce2735359
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_avpu/Kconfig
+@@ -0,0 +1,9 @@
++config INGENIC_AVPU
++	tristate "[VPU] ingenic soc avpu module"
++	depends on SOC_X2500
++	default n
++	help
++		this is ingenic avpu for x2500, support h264/h265/jpeg encoder.
++
++
++
+diff --git a/module_drivers/drivers/video/ingenic_avpu/Makefile b/module_drivers/drivers/video/ingenic_avpu/Makefile
+new file mode 100644
+index 000000000..5f8927d80
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_avpu/Makefile
+@@ -0,0 +1,19 @@
++
++obj-$(CONFIG_INGENIC_AVPU) += avpu_alloc.o	\
++	  			avpu_alloc_ioctl.o \
++	  			avpu_dmabuf.o	\
++	  			avpu_ip.o	\
++	  			avpu_main.o
++
++#avpu_alloc.h
++#avpu_alloc_ioctl.c
++#avpu_alloc_ioctl.h
++#avpu_dmabuf.c
++#avpu_ioctl.h
++#avpu_ip.c
++#avpu_main.c
++#avpu_no_dmabuf.c
++
++
++
++
+diff --git a/module_drivers/drivers/video/ingenic_avpu/avpu_alloc.c b/module_drivers/drivers/video/ingenic_avpu/avpu_alloc.c
+new file mode 100644
+index 000000000..c8f3991dc
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_avpu/avpu_alloc.c
+@@ -0,0 +1,43 @@
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/dma-mapping.h>
++
++#include "avpu_alloc.h"
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Kevin Grandemange");
++MODULE_AUTHOR("Sebastien Alaiwan");
++MODULE_AUTHOR("Antoine Gruzelle");
++MODULE_DESCRIPTION("JZ Common");
++
++struct avpu_dma_buffer *avpu_alloc_dma(struct device *dev, size_t size)
++{
++	struct avpu_dma_buffer *buf =
++		kmalloc(sizeof(struct avpu_dma_buffer),
++			GFP_KERNEL);
++
++	if (!buf)
++		return NULL;
++
++	buf->size = size;
++	buf->cpu_handle = dma_alloc_coherent(dev, buf->size,
++					     &buf->dma_handle,
++					     GFP_KERNEL | GFP_DMA);
++
++	if (!buf->cpu_handle) {
++		kfree(buf);
++		return NULL;
++	}
++
++	return buf;
++}
++
++void avpu_free_dma(struct device *dev, struct avpu_dma_buffer *buf)
++{
++	if (buf)
++		dma_free_coherent(dev, buf->size, buf->cpu_handle,
++				  buf->dma_handle);
++	kfree(buf);
++}
++
++
+diff --git a/module_drivers/drivers/video/ingenic_avpu/avpu_alloc.h b/module_drivers/drivers/video/ingenic_avpu/avpu_alloc.h
+new file mode 100644
+index 000000000..c9b2d5245
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_avpu/avpu_alloc.h
+@@ -0,0 +1,15 @@
++#ifndef _AL_ALLOC_H_
++#define _AL_ALLOC_H_
++
++#include <linux/device.h>
++
++struct avpu_dma_buffer {
++	u32 size;
++	dma_addr_t dma_handle;
++	void *cpu_handle;
++};
++
++struct avpu_dma_buffer *avpu_alloc_dma(struct device *dev, size_t size);
++void avpu_free_dma(struct device *dev, struct avpu_dma_buffer *buf);
++
++#endif /* _AL_ALLOC_H_ */
+diff --git a/module_drivers/drivers/video/ingenic_avpu/avpu_alloc_ioctl.c b/module_drivers/drivers/video/ingenic_avpu/avpu_alloc_ioctl.c
+new file mode 100644
+index 000000000..d280535aa
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_avpu/avpu_alloc_ioctl.c
+@@ -0,0 +1,92 @@
++#include "avpu_alloc_ioctl.h"
++#include "avpu_alloc.h"
++
++#include <linux/uaccess.h>
++#include "avpu_dmabuf.h"
++
++int avpu_ioctl_get_dma_fd(struct device *dev, unsigned long arg)
++{
++	struct avpu_dma_info info;
++	int err;
++
++	if (copy_from_user(&info, (struct avpu_dma_info *)arg, sizeof(info)))
++		return -EFAULT;
++
++	err = avpu_allocate_dmabuf(dev, info.size, &info.fd);
++	if (err)
++		return err;
++
++	err = avpu_dmabuf_get_address(dev, info.fd, &info.phy_addr);
++	if (err)
++		return err;
++
++	if (copy_to_user((void *)arg, &info, sizeof(info)))
++		return -EFAULT;
++
++	return 0;
++}
++
++int add_buffer_to_list(struct avpu_codec_chan *chan, struct avpu_dma_buffer *buf)
++{
++	struct avpu_dma_buf_mmap *buf_mmap = kmalloc(sizeof(*buf_mmap), GFP_KERNEL);
++
++	if (!buf_mmap)
++		return -1;
++	buf_mmap->buf = buf;
++	spin_lock(&chan->lock);
++	list_add_tail(&buf_mmap->list, &chan->mem);
++	buf_mmap->buf_id = chan->num_bufs++;
++	spin_unlock(&chan->lock);
++	return buf_mmap->buf_id;
++}
++
++int avpu_ioctl_get_dma_mmap(struct device *dev, struct avpu_codec_chan *chan,
++			   unsigned long arg)
++{
++	struct avpu_dma_info info;
++	struct avpu_dma_buffer *buf = NULL;
++
++	if (copy_from_user(&info, (struct avpu_dma_info *)arg, sizeof(info)))
++		return -EFAULT;
++
++	buf = avpu_alloc_dma(dev, info.size);
++
++	if (!buf) {
++		dev_err(dev, "Can't alloc DMA buffer\n");
++		return -ENOMEM;
++	}
++
++	info.fd = add_buffer_to_list(chan, buf);
++	if (info.fd == -1)
++		return -ENOMEM;
++	/* offset for mmap needs to be a multiple of page size */
++	info.fd = info.fd << PAGE_SHIFT;
++
++	info.phy_addr = (__u32)buf->dma_handle;
++
++	pr_info("allocated buffer cpu: %p, phy:%d, offset:%d\n", buf->cpu_handle,
++		info.phy_addr, info.fd);
++
++	if (copy_to_user((void *)arg, &info, sizeof(info)))
++		return -EFAULT;
++
++	return 0;
++}
++
++int avpu_ioctl_get_dmabuf_dma_addr(struct device *dev, unsigned long arg)
++{
++	struct avpu_dma_info info;
++	int err;
++
++	if (copy_from_user(&info, (struct avpu_dma_info *)arg, sizeof(info)))
++		return -EFAULT;
++
++	err = avpu_dmabuf_get_address(dev, info.fd, &info.phy_addr);
++	if (err)
++		return err;
++
++	if (copy_to_user((void *)arg, &info, sizeof(info)))
++		return -EFAULT;
++
++	return 0;
++}
+diff --git a/module_drivers/drivers/video/ingenic_avpu/avpu_alloc_ioctl.h b/module_drivers/drivers/video/ingenic_avpu/avpu_alloc_ioctl.h
+new file mode 100644
+index 000000000..92f2efd6a
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_avpu/avpu_alloc_ioctl.h
+@@ -0,0 +1,8 @@
++#include <linux/device.h>
++#include "avpu_ip.h"
++
++int avpu_ioctl_get_dma_fd(struct device *dev, unsigned long arg);
++int avpu_ioctl_get_dmabuf_dma_addr(struct device *dev, unsigned long arg);
++int avpu_ioctl_get_dma_mmap(struct device *dev, struct avpu_codec_chan *chan,
++			   unsigned long arg);
++
+diff --git a/module_drivers/drivers/video/ingenic_avpu/avpu_dmabuf.c b/module_drivers/drivers/video/ingenic_avpu/avpu_dmabuf.c
+new file mode 100644
+index 000000000..541dce831
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_avpu/avpu_dmabuf.c
+@@ -0,0 +1,634 @@
++#include "avpu_dmabuf.h"
++
++#include <linux/uaccess.h>
++#include <linux/dma-buf.h>
++#include <linux/version.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/anon_inodes.h>
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Kevin Grandemange");
++MODULE_AUTHOR("Sebastien Alaiwan");
++MODULE_AUTHOR("Antoine Gruzelle");
++MODULE_DESCRIPTION("JZ Common");
++
++struct avpu_dmabuf_priv {
++	struct avpu_dma_buffer *buffer;
++
++	/* DMABUF related */
++	struct device *dev;
++	struct sg_table *sgt_base;
++	enum dma_data_direction dma_dir;
++
++};
++
++struct avpu_dmabuf_attachment {
++	struct sg_table sgt;
++	enum dma_data_direction dma_dir;
++};
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0)
++/* device argument was removed */
++static int avpu_dmabuf_attach(struct dma_buf *dbuf, struct dma_buf_attachment *dbuf_attach)
++#else
++static int avpu_dmabuf_attach(struct dma_buf *dbuf, struct device* dev, struct dma_buf_attachment *dbuf_attach)
++#endif
++{
++	struct avpu_dmabuf_priv *dinfo = dbuf->priv;
++
++	struct avpu_dmabuf_attachment *attach;
++
++	struct scatterlist *rd, *wr;
++	struct sg_table *sgt;
++	int ret, i;
++
++	attach = kzalloc(sizeof(*attach), GFP_KERNEL);
++	if (!attach)
++		return -ENOMEM;
++
++	sgt = &attach->sgt;
++
++	ret = sg_alloc_table(sgt, dinfo->sgt_base->orig_nents, GFP_KERNEL);
++	if (ret) {
++		kfree(attach);
++		return -ENOMEM;
++	}
++
++	rd = dinfo->sgt_base->sgl;
++	wr = sgt->sgl;
++
++	for (i = 0; i < sgt->orig_nents; ++i) {
++		sg_set_page(wr, sg_page(rd), rd->length, rd->offset);
++		rd = sg_next(rd);
++		wr = sg_next(wr);
++	}
++
++	attach->dma_dir = DMA_NONE;
++
++	dbuf_attach->priv = attach;
++
++	return 0;
++}
++
++#ifndef CONFIG_VIDEO_V4L2
++__weak int is_dma_buf_file(struct file *);
++
++struct dma_buf_list {
++	struct list_head head;
++	struct mutex lock;
++};
++
++static struct dma_buf_list db_list;
++
++__weak int dma_buf_release(struct inode *inode, struct file *file)
++{
++	struct dma_buf *dmabuf;
++
++	if (!is_dma_buf_file(file))
++		return -EINVAL;
++
++	dmabuf = file->private_data;
++
++	BUG_ON(dmabuf->vmapping_counter);
++
++	dmabuf->ops->release(dmabuf);
++
++	mutex_lock(&db_list.lock);
++	list_del(&dmabuf->list_node);
++	mutex_unlock(&db_list.lock);
++
++	kfree(dmabuf);
++	return 0;
++}
++
++__weak int dma_buf_mmap_internal(struct file *file, struct vm_area_struct *vma)
++{
++	struct dma_buf *dmabuf;
++
++	if (!is_dma_buf_file(file))
++		return -EINVAL;
++
++	dmabuf = file->private_data;
++
++	/* check for overflowing the buffer's size */
++	if (vma->vm_pgoff + ((vma->vm_end - vma->vm_start) >> PAGE_SHIFT) >
++	    dmabuf->size >> PAGE_SHIFT)
++		return -EINVAL;
++
++	return dmabuf->ops->mmap(dmabuf, vma);
++}
++
++static const struct file_operations dma_buf_fops = {
++	.release	= dma_buf_release,
++	.mmap		= dma_buf_mmap_internal,
++};
++
++/*
++ * is_dma_buf_file - Check if struct file* is associated with dma_buf
++ */
++__weak int is_dma_buf_file(struct file *file)
++{
++	return file->f_op == &dma_buf_fops;
++}
++
++/**
++ * dma_buf_export_named - Creates a new dma_buf, and associates an anon file
++ * with this buffer, so it can be exported.
++ * Also connect the allocator specific data and ops to the buffer.
++ * Additionally, provide a name string for exporter; useful in debugging.
++ *
++ * @priv:	[in]	Attach private data of allocator to this buffer
++ * @ops:	[in]	Attach allocator-defined dma buf ops to the new buffer.
++ * @size:	[in]	Size of the buffer
++ * @flags:	[in]	mode flags for the file.
++ * @exp_name:	[in]	name of the exporting module - useful for debugging.
++ *
++ * Returns, on success, a newly created dma_buf object, which wraps the
++ * supplied private data and operations for dma_buf_ops. On either missing
++ * ops, or error in allocating struct dma_buf, will return negative error.
++ *
++ */
++__weak struct dma_buf *dma_buf_export_named(void *priv, const struct dma_buf_ops *ops,
++				size_t size, int flags, const char *exp_name)
++{
++	struct dma_buf *dmabuf;
++	struct file *file;
++
++	if (WARN_ON(!priv || !ops
++			  || !ops->map_dma_buf
++			  || !ops->unmap_dma_buf
++			  || !ops->release
++			  || !ops->kmap_atomic
++			  || !ops->kmap
++			  || !ops->mmap)) {
++		return ERR_PTR(-EINVAL);
++	}
++
++	dmabuf = kzalloc(sizeof(struct dma_buf), GFP_KERNEL);
++	if (dmabuf == NULL)
++		return ERR_PTR(-ENOMEM);
++
++	dmabuf->priv = priv;
++	dmabuf->ops = ops;
++	dmabuf->size = size;
++	dmabuf->exp_name = exp_name;
++
++	file = anon_inode_getfile("dmabuf", &dma_buf_fops, dmabuf, flags);
++
++	dmabuf->file = file;
++
++	mutex_init(&dmabuf->lock);
++	INIT_LIST_HEAD(&dmabuf->attachments);
++
++	mutex_lock(&db_list.lock);
++	list_add(&dmabuf->list_node, &db_list.head);
++	mutex_unlock(&db_list.lock);
++
++	return dmabuf;
++}
++
++__weak int dma_buf_fd(struct dma_buf *dmabuf, int flags)
++{
++	int fd;
++
++	if (!dmabuf || !dmabuf->file)
++		return -EINVAL;
++
++	fd = get_unused_fd_flags(flags);
++	if (fd < 0)
++		return fd;
++
++	fd_install(fd, dmabuf->file);
++
++	return fd;
++}
++
++__weak struct dma_buf *dma_buf_get(int fd)
++{
++	struct file *file;
++
++	file = fget(fd);
++
++	if (!file)
++		return ERR_PTR(-EBADF);
++
++	if (!is_dma_buf_file(file)) {
++		fput(file);
++		return ERR_PTR(-EINVAL);
++	}
++
++	return file->private_data;
++}
++
++__weak void dma_buf_put(struct dma_buf *dmabuf)
++{
++	if (WARN_ON(!dmabuf || !dmabuf->file))
++		return;
++
++	fput(dmabuf->file);
++}
++
++/**
++ * dma_buf_attach - Add the device to dma_buf's attachments list; optionally,
++ * calls attach() of dma_buf_ops to allow device-specific attach functionality
++ * @dmabuf:	[in]	buffer to attach device to.
++ * @dev:	[in]	device to be attached.
++ *
++ * Returns struct dma_buf_attachment * for this attachment; may return negative
++ * error codes.
++ *
++ */
++__weak struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf,
++					  struct device *dev)
++{
++	struct dma_buf_attachment *attach;
++	int ret;
++
++	if (WARN_ON(!dmabuf || !dev))
++		return ERR_PTR(-EINVAL);
++
++	attach = kzalloc(sizeof(struct dma_buf_attachment), GFP_KERNEL);
++	if (attach == NULL)
++		return ERR_PTR(-ENOMEM);
++
++	attach->dev = dev;
++	attach->dmabuf = dmabuf;
++
++	mutex_lock(&dmabuf->lock);
++
++	if (dmabuf->ops->attach) {
++		ret = dmabuf->ops->attach(dmabuf, dev, attach);
++		if (ret)
++			goto err_attach;
++	}
++	list_add(&attach->node, &dmabuf->attachments);
++
++	mutex_unlock(&dmabuf->lock);
++	return attach;
++
++err_attach:
++	kfree(attach);
++	mutex_unlock(&dmabuf->lock);
++	return ERR_PTR(ret);
++}
++
++__weak void dma_buf_detach(struct dma_buf *dmabuf, struct dma_buf_attachment *attach)
++{
++	if (WARN_ON(!dmabuf || !attach))
++		return;
++
++	mutex_lock(&dmabuf->lock);
++	list_del(&attach->node);
++	if (dmabuf->ops->detach)
++		dmabuf->ops->detach(dmabuf, attach);
++
++	mutex_unlock(&dmabuf->lock);
++	kfree(attach);
++}
++
++/**
++ * dma_buf_map_attachment - Returns the scatterlist table of the attachment;
++ * mapped into _device_ address space. Is a wrapper for map_dma_buf() of the
++ * dma_buf_ops.
++ * @attach:	[in]	attachment whose scatterlist is to be returned
++ * @direction:	[in]	direction of DMA transfer
++ *
++ * Returns sg_table containing the scatterlist to be returned; may return NULL
++ * or ERR_PTR.
++ *
++ */
++__weak struct sg_table *dma_buf_map_attachment(struct dma_buf_attachment *attach,
++					enum dma_data_direction direction)
++{
++	struct sg_table *sg_table = ERR_PTR(-EINVAL);
++
++	might_sleep();
++
++	if (WARN_ON(!attach || !attach->dmabuf))
++		return ERR_PTR(-EINVAL);
++
++	sg_table = attach->dmabuf->ops->map_dma_buf(attach, direction);
++
++	return sg_table;
++}
++
++/**
++ * dma_buf_unmap_attachment - unmaps and decreases usecount of the buffer;might
++ * deallocate the scatterlist associated. Is a wrapper for unmap_dma_buf() of
++ * dma_buf_ops.
++ * @attach:	[in]	attachment to unmap buffer from
++ * @sg_table:	[in]	scatterlist info of the buffer to unmap
++ * @direction:  [in]    direction of DMA transfer
++ *
++ */
++__weak void dma_buf_unmap_attachment(struct dma_buf_attachment *attach,
++				struct sg_table *sg_table,
++				enum dma_data_direction direction)
++{
++	might_sleep();
++
++	if (WARN_ON(!attach || !attach->dmabuf || !sg_table))
++		return;
++
++	attach->dmabuf->ops->unmap_dma_buf(attach, sg_table,
++						direction);
++}
++#endif
++
++static void avpu_dmabuf_detach(struct dma_buf *dbuf,
++			      struct dma_buf_attachment *db_attach)
++{
++	struct avpu_dmabuf_attachment *attach = db_attach->priv;
++	struct sg_table *sgt;
++
++	if (!attach)
++		return;
++
++	sgt = &attach->sgt;
++
++	/* release the scatterlist cache */
++	if (attach->dma_dir != DMA_NONE)
++		dma_unmap_sg(db_attach->dev, sgt->sgl, sgt->orig_nents,
++			     attach->dma_dir);
++
++	sg_free_table(sgt);
++	kfree(attach);
++	db_attach->priv = NULL;
++}
++
++static struct sg_table *avpu_dmabuf_map(struct dma_buf_attachment *db_attach,
++				       enum dma_data_direction dma_dir)
++{
++	struct avpu_dmabuf_attachment *attach = db_attach->priv;
++	struct sg_table *sgt;
++	struct mutex *lock = &db_attach->dmabuf->lock;
++
++	mutex_lock(lock);
++
++	sgt = &attach->sgt;
++
++	if (attach->dma_dir == dma_dir) {
++		mutex_unlock(lock);
++		return sgt;
++	}
++
++	if (attach->dma_dir != DMA_NONE) {
++		dma_unmap_sg(db_attach->dev, sgt->sgl, sgt->orig_nents,
++			     attach->dma_dir);
++		attach->dma_dir = DMA_NONE;
++	}
++
++	sgt->nents = dma_map_sg(db_attach->dev, sgt->sgl, sgt->orig_nents,
++				dma_dir);
++
++	if (!sgt->nents) {
++		pr_err("failed to map scatterlist\n");
++		mutex_unlock(lock);
++		return ERR_PTR(-EIO);
++	}
++
++	attach->dma_dir = dma_dir;
++
++	mutex_unlock(lock);
++
++	return sgt;
++}
++
++static void avpu_dmabuf_unmap(struct dma_buf_attachment *at,
++			     struct sg_table *sg, enum dma_data_direction dir)
++{
++}
++
++static int avpu_dmabuf_mmap(struct dma_buf *buf, struct vm_area_struct *vma)
++{
++	struct avpu_dmabuf_priv *dinfo = buf->priv;
++	unsigned long start = vma->vm_start;
++	unsigned long vsize = vma->vm_end - start;
++	struct avpu_dma_buffer *buffer = dinfo->buffer;
++	int ret;
++
++	if (!dinfo) {
++		pr_err("No buffer to map\n");
++		return -EINVAL;
++	}
++
++	vma->vm_pgoff = 0;
++
++	ret = dma_mmap_coherent(dinfo->dev, vma, buffer->cpu_handle,
++				buffer->dma_handle, vsize);
++
++	if (ret < 0) {
++		pr_err("Remapping memory failed, error: %d\n", ret);
++		return ret;
++	}
++
++	vma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP;
++
++	return 0;
++}
++
++static void avpu_dmabuf_release(struct dma_buf *buf)
++{
++	struct avpu_dmabuf_priv *dinfo = buf->priv;
++	struct avpu_dma_buffer *buffer = dinfo->buffer;
++
++	if (dinfo->sgt_base) {
++		sg_free_table(dinfo->sgt_base);
++		kfree(dinfo->sgt_base);
++	}
++
++
++	dma_free_coherent(dinfo->dev, buffer->size, buffer->cpu_handle,
++			  buffer->dma_handle);
++
++	put_device(dinfo->dev);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,10, 0)
++	kfree_sensitive(buffer);
++#else
++	kzfree(buffer);
++#endif
++	kfree(dinfo);
++}
++
++static void *avpu_dmabuf_kmap(struct dma_buf *dmabuf, unsigned long page_num)
++{
++	struct avpu_dmabuf_priv *dinfo = dmabuf->priv;
++	void *vaddr = dinfo->buffer->cpu_handle;
++
++	return vaddr + page_num * PAGE_SIZE;
++}
++
++static void *avpu_dmabuf_vmap(struct dma_buf *dbuf)
++{
++	struct avpu_dmabuf_priv *dinfo = dbuf->priv;
++	void *vaddr = dinfo->buffer->cpu_handle;
++
++	return vaddr;
++}
++
++static const struct dma_buf_ops avpu_dmabuf_ops = {
++	.attach		= avpu_dmabuf_attach,
++	.detach		= avpu_dmabuf_detach,
++	.map_dma_buf	= avpu_dmabuf_map,
++	.unmap_dma_buf	= avpu_dmabuf_unmap,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)
++/* the map_atomic && map interface was removed after 5.10 */
++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,10, 0)
++	.map_atomic	= avpu_dmabuf_kmap,
++	.map		= avpu_dmabuf_kmap,
++#endif
++#else
++	.kmap_atomic	= avpu_dmabuf_kmap,
++	.kmap		= avpu_dmabuf_kmap,
++#endif
++	.vmap		= avpu_dmabuf_vmap,
++	.mmap		= avpu_dmabuf_mmap,
++	.release	= avpu_dmabuf_release,
++};
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)
++static void define_export_info(struct dma_buf_export_info *exp_info, int size, void *priv)
++{
++	exp_info->owner = THIS_MODULE;
++	exp_info->exp_name = KBUILD_MODNAME;
++	exp_info->ops = &avpu_dmabuf_ops;
++	exp_info->flags = O_RDWR;
++	exp_info->resv = NULL;
++	exp_info->size = size;
++	exp_info->priv = priv;
++}
++#endif
++
++static struct sg_table *avpu_get_base_sgt(struct avpu_dmabuf_priv *dinfo)
++{
++	int ret;
++	struct sg_table *sgt;
++	struct avpu_dma_buffer *buf = dinfo->buffer;
++	struct device *dev = dinfo->dev;
++
++	sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
++	if (!sgt)
++		return NULL;
++
++	ret = dma_get_sgtable(dev, sgt, buf->cpu_handle, buf->dma_handle,
++			      buf->size);
++	if (ret < 0) {
++		kfree(sgt);
++		return NULL;
++	}
++
++	return sgt;
++
++}
++
++static struct dma_buf *avpu_get_dmabuf(void *dma_info_priv)
++{
++	struct dma_buf *dbuf;
++	struct avpu_dmabuf_priv *dinfo = dma_info_priv;
++	struct avpu_dma_buffer *buf = dinfo->buffer;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)
++	struct dma_buf_export_info exp_info;
++#endif
++
++	if (!dinfo->sgt_base)
++		dinfo->sgt_base = avpu_get_base_sgt(dinfo);
++
++	if (WARN_ON(!dinfo->sgt_base))
++		return NULL;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)
++	define_export_info(&exp_info, buf->size, (void *)dinfo);
++	dbuf = dma_buf_export(&exp_info);
++	if (IS_ERR(dbuf)) {
++		pr_err("couldn't export dma buf\n");
++		return NULL;
++	}
++#else
++	dbuf = dma_buf_export((void *)dinfo, &avpu_dmabuf_ops, buf->size, O_RDWR);
++	if (IS_ERR(buf)) {
++		pr_err("couldn't export dma buf\n");
++		return NULL;
++	}
++#endif
++	return dbuf;
++}
++
++static void *avpu_dmabuf_wrap(struct device *dev, unsigned long size,
++			     struct avpu_dma_buffer *buffer)
++{
++	struct avpu_dmabuf_priv *dinfo;
++	struct dma_buf *dbuf;
++
++	dinfo = kzalloc(sizeof(*dinfo), GFP_KERNEL);
++	if (!dinfo)
++		return ERR_PTR(-ENOMEM);
++
++	dinfo->dev = get_device(dev);
++	dinfo->buffer = buffer;
++	dinfo->dma_dir = DMA_BIDIRECTIONAL;
++	dinfo->sgt_base = avpu_get_base_sgt(dinfo);
++
++	dbuf = avpu_get_dmabuf(dinfo);
++	if (IS_ERR_OR_NULL(dbuf))
++		return ERR_PTR(-EINVAL);
++
++	return dbuf;
++}
++
++int avpu_create_dmabuf_fd(struct device *dev, unsigned long size,
++			 struct avpu_dma_buffer *buffer)
++{
++	struct dma_buf *dbuf = avpu_dmabuf_wrap(dev, size, buffer);
++
++	if (IS_ERR(dbuf))
++		return PTR_ERR(dbuf);
++	return dma_buf_fd(dbuf, O_RDWR);
++}
++
++int avpu_allocate_dmabuf(struct device *dev, int size, u32 *fd)
++{
++	struct avpu_dma_buffer *buffer;
++
++	buffer = avpu_alloc_dma(dev, size);
++	if (!buffer) {
++		dev_err(dev, "Can't alloc DMA buffer\n");
++		return -ENOMEM;
++	}
++
++	*fd = avpu_create_dmabuf_fd(dev, size, buffer);
++	return 0;
++}
++
++int avpu_dmabuf_get_address(struct device *dev, u32 fd, u32 *bus_address)
++{
++	struct dma_buf *dbuf;
++	struct dma_buf_attachment *attach;
++	struct sg_table *sgt;
++	int err = 0;
++
++	dbuf = dma_buf_get(fd);
++	if (IS_ERR(dbuf))
++		return -EINVAL;
++	attach = dma_buf_attach(dbuf, dev);
++	if (IS_ERR(attach)) {
++		err = -EINVAL;
++		goto fail_attach;
++	}
++	sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
++	if (IS_ERR(sgt)) {
++		err = -EINVAL;
++		goto fail_map;
++	}
++
++	*bus_address = sg_dma_address(sgt->sgl);
++
++	dma_buf_unmap_attachment(attach, sgt, DMA_BIDIRECTIONAL);
++fail_map:
++	dma_buf_detach(dbuf, attach);
++fail_attach:
++	dma_buf_put(dbuf);
++	return err;
++}
++
+diff --git a/module_drivers/drivers/video/ingenic_avpu/avpu_dmabuf.h b/module_drivers/drivers/video/ingenic_avpu/avpu_dmabuf.h
+new file mode 100644
+index 000000000..4d6cb371f
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_avpu/avpu_dmabuf.h
+@@ -0,0 +1,13 @@
++#include <linux/device.h>
++#include "avpu_alloc.h"
++
++struct avpu_buffer_info {
++	u32 bus_address;
++	u32 size;
++};
++
++int avpu_create_dmabuf_fd(struct device *dev, unsigned long size,
++			 struct avpu_dma_buffer *buffer);
++int avpu_allocate_dmabuf(struct device *dev, int size, u32 *fd);
++int avpu_dmabuf_get_address(struct device *dev, u32 fd, u32 *bus_address);
++
+diff --git a/module_drivers/drivers/video/ingenic_avpu/avpu_ioctl.h b/module_drivers/drivers/video/ingenic_avpu/avpu_ioctl.h
+new file mode 100644
+index 000000000..33ede96f5
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_avpu/avpu_ioctl.h
+@@ -0,0 +1,22 @@
++#pragma once
++
++#define AL_CMD_UNBLOCK_CHANNEL _IO('q', 1)
++
++#define AL_CMD_IP_WRITE_REG        _IOWR('q', 10, struct avpu_reg)
++#define AL_CMD_IP_READ_REG         _IOWR('q', 11, struct avpu_reg)
++#define AL_CMD_IP_WAIT_IRQ         _IOWR('q', 12, int)
++#define GET_DMA_MMAP      _IOWR('q', 26, struct avpu_dma_info)
++#define GET_DMA_FD        _IOWR('q', 13, struct avpu_dma_info)
++#define GET_DMA_PHY       _IOWR('q', 18, struct avpu_dma_info)
++#define JZ_CMD_FLUSH_CACHE			_IOWR('q', 14, int)
++
++struct avpu_reg {
++	unsigned int id;
++	unsigned int value;
++};
++
++struct avpu_dma_info {
++	__u32 fd;
++	__u32 size;
++	__u32 phy_addr;
++};
+diff --git a/module_drivers/drivers/video/ingenic_avpu/avpu_ip.c b/module_drivers/drivers/video/ingenic_avpu/avpu_ip.c
+new file mode 100644
+index 000000000..f7a9a6f6c
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_avpu/avpu_ip.c
+@@ -0,0 +1,144 @@
++#include <linux/device.h>
++#include <linux/dma-mapping.h>
++#include <linux/err.h>
++#include <linux/firmware.h>
++#include <linux/fs.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++#include <linux/uaccess.h>
++#include <linux/wait.h>
++
++#include "avpu_ip.h"
++
++int avpu_codec_bind_channel(struct avpu_codec_chan *chan,
++			    struct inode *inode)
++{
++	struct avpu_codec_desc *codec;
++	unsigned long flags;
++	struct list_head *pos, *n;
++	struct r_irq *tmp;
++	int ret = 0;
++
++	codec = container_of(inode->i_cdev, struct avpu_codec_desc, cdev);
++
++	spin_lock_irqsave(&codec->i_lock, flags);
++
++	clk_enable(codec->clk);
++	clk_enable(codec->ahb1_gate);
++	clk_enable(codec->clk_gate);
++
++	chan->codec = codec;
++	/* No mcu, there is a one for one mapping */
++	if (codec->chan != NULL) {
++		ret = -ENODEV;
++		goto unlock;
++	}
++
++	list_for_each_safe(pos, n, &codec->irq_masks) {
++		tmp = list_entry(pos, struct r_irq, list);
++		avpu_err("Previous channel lost irq:%x\n", tmp->bitfield);
++		list_del(pos);
++		kmem_cache_free(codec->cache, tmp);
++	}
++
++	codec->chan = chan;
++
++unlock:
++	spin_unlock_irqrestore(&codec->i_lock, flags);
++	return ret;
++
++}
++
++void avpu_codec_unbind_channel(struct avpu_codec_chan *chan)
++{
++	struct avpu_codec_desc *codec;
++	unsigned long flags;
++
++	codec = chan->codec;
++	spin_lock_irqsave(&codec->i_lock, flags);
++
++	clk_disable(codec->clk);
++	clk_disable(codec->clk_gate);
++	clk_disable(codec->ahb1_gate);
++
++	codec->chan = NULL;
++
++	spin_unlock_irqrestore(&codec->i_lock, flags);
++}
++
++int avpu_codec_read_register(struct avpu_codec_chan *chan,
++			     struct avpu_reg *reg)
++{
++	struct avpu_codec_desc *codec = chan->codec;
++
++	if (!chan->codec->regs) {
++		avpu_err("Registers not mapped\n");
++		return -EINVAL;
++	}
++	reg->value = ioread32(chan->codec->regs + reg->id);
++
++	return 0;
++}
++
++void avpu_codec_write_register(struct avpu_codec_chan *chan,
++			       struct avpu_reg *reg)
++{
++	struct avpu_codec_desc *codec = chan->codec;
++
++	if (!chan->codec->regs) {
++		avpu_err("Registers not mapped\n");
++		return;
++	}
++	iowrite32(reg->value, chan->codec->regs + reg->id);
++
++}
++
++irqreturn_t avpu_hardirq_handler(int irq, void *data)
++{
++	struct avpu_codec_desc *codec = (struct avpu_codec_desc *)data;
++	u32 unmasked_irq_bitfield, irq_bitfield;
++	u32 mask;
++	unsigned long flags;
++	struct r_irq *i_callback;
++	int callback_nb;
++	int i = 0;
++	int avpu_interrupt_nb = 20;
++
++	mask = ioread32(codec->regs + AVPU_INTERRUPT_MASK);
++	unmasked_irq_bitfield = ioread32(codec->regs + AVPU_INTERRUPT);
++	irq_bitfield = unmasked_irq_bitfield & mask;
++	if (irq_bitfield == 0) {
++		avpu_dbg("bitfield is 0\n");
++		return IRQ_NONE;
++	}
++	iowrite32(unmasked_irq_bitfield, codec->regs + AVPU_INTERRUPT);
++	ioread32(codec->regs + AVPU_INTERRUPT);
++
++	for (i = 0; i < avpu_interrupt_nb; ++i) {
++		callback_nb = 1U << i;
++		if (irq_bitfield & callback_nb) {
++			i_callback = kmem_cache_alloc(codec->cache, GFP_ATOMIC);
++			if (!i_callback) {
++				avpu_dbg("ENOMEM: Missed interrupt\n");
++				return IRQ_NONE;
++			}
++			i_callback->bitfield = i;
++			spin_lock_irqsave(&codec->i_lock, flags);
++			list_add_tail(&i_callback->list, &codec->irq_masks);
++			spin_unlock_irqrestore(&codec->i_lock, flags);
++		}
++	}
++
++	spin_lock_irqsave(&codec->i_lock, flags);
++	if (codec->chan)
++		wake_up_interruptible(&codec->chan->irq_queue);
++	spin_unlock_irqrestore(&codec->i_lock, flags);
++
++	return IRQ_HANDLED;
++}
+diff --git a/module_drivers/drivers/video/ingenic_avpu/avpu_ip.h b/module_drivers/drivers/video/ingenic_avpu/avpu_ip.h
+new file mode 100644
+index 000000000..a2a0b9237
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_avpu/avpu_ip.h
+@@ -0,0 +1,84 @@
++#pragma once
++
++#include <linux/cdev.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/time.h>
++#include <linux/spinlock.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++
++#include "avpu_ioctl.h"
++#include "avpu_alloc.h"
++
++#define AVPU_NR_DEVS 4
++#define AVPU_BASE_OFFSET 0x8000
++
++#define AXI_ADDR_OFFSET_IP (AVPU_BASE_OFFSET + 0x1208)
++#define AVPU_INTERRUPT_MASK (AVPU_BASE_OFFSET + 0x14)
++#define AVPU_INTERRUPT (AVPU_BASE_OFFSET + 0x18)
++
++#define avpu_writel(val, reg) iowrite32(val, codec->regs + reg)
++#define avpu_readl(reg) ioread32(codec->regs + reg)
++
++#define avpu_dbg(format, ...) \
++	dev_dbg(codec->device, format, ## __VA_ARGS__)
++
++#define avpu_info(format, ...) \
++	dev_info(codec->device, format, ## __VA_ARGS__)
++
++#define avpu_err(format, ...) \
++	dev_err(codec->device, format, ## __VA_ARGS__)
++
++struct avpu_codec_desc;
++struct dma_buf_info {
++	struct avpu_dma_buffer *buffer;
++	struct avpu_codec_desc *codec;
++};
++
++struct r_irq {
++	struct list_head list;
++	u32 bitfield;
++};
++
++struct avpu_codec_desc {
++	struct device *device;
++	void __iomem *regs;             /* Base addr for regs */
++	unsigned long regs_size;        /* end addr for regs */
++	struct cdev cdev;
++	/* one for one mapping in the no mcu case */
++	struct avpu_codec_chan *chan;
++	struct list_head irq_masks;
++	spinlock_t i_lock;
++	struct kmem_cache *cache;
++	int minor;
++	struct clk          *clk;
++	struct clk          *clk_mux;
++	struct clk          *clk_gate;
++	struct clk          *ahb1_gate;
++};
++
++struct avpu_dma_buf_mmap {
++	struct list_head list;
++	struct avpu_dma_buffer *buf;
++	int buf_id;
++};
++
++struct avpu_codec_chan {
++	wait_queue_head_t irq_queue;
++	int unblock;
++	spinlock_t lock;
++	struct list_head mem;
++	int num_bufs;
++	struct avpu_codec_desc *codec;
++};
++
++int avpu_codec_bind_channel(struct avpu_codec_chan *chan,
++			    struct inode *inode);
++void avpu_codec_unbind_channel(struct avpu_codec_chan *chan);
++int avpu_codec_read_register(struct avpu_codec_chan *chan,
++			     struct avpu_reg *reg);
++void avpu_codec_write_register(struct avpu_codec_chan *chan,
++			       struct avpu_reg *reg);
++irqreturn_t avpu_irq_handler(int irq, void *data);
++irqreturn_t avpu_hardirq_handler(int irq, void *data);
+diff --git a/module_drivers/drivers/video/ingenic_avpu/avpu_main.c b/module_drivers/drivers/video/ingenic_avpu/avpu_main.c
+new file mode 100644
+index 000000000..ec71ccab3
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_avpu/avpu_main.c
+@@ -0,0 +1,706 @@
++#include <linux/cdev.h>
++#include <linux/debugfs.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/dma-mapping.h>
++#include <linux/err.h>
++#include <linux/fcntl.h>
++#include <linux/firmware.h>
++#include <linux/fs.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/kfifo.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++#include <linux/of_reserved_mem.h>
++#include <linux/sched.h>
++#include <linux/signal.h>
++#include <linux/slab.h>
++#include <linux/stddef.h>
++#include <linux/uaccess.h>
++#include <linux/vmalloc.h>
++#include <linux/resource.h>
++#include <linux/version.h>
++#include <linux/dma-map-ops.h>
++
++#include "avpu_ioctl.h"
++#include "avpu_alloc_ioctl.h"
++#include "avpu_ip.h"
++
++#define DEV_NAME "avpu"
++
++int avpu_codec_major;
++int avpu_codec_nr_devs = AVPU_NR_DEVS;
++module_param(avpu_codec_nr_devs, int, S_IRUGO);
++static char *clk_name = "mpll";
++module_param(clk_name, charp, S_IRUGO);
++MODULE_PARM_DESC(clk_name, "chose parent clk");
++static int avpu_clk = 440000000;
++module_param(avpu_clk, int, S_IRUGO);
++MODULE_PARM_DESC(avpu_clk, "avpu clock freq");
++static struct class *module_class;
++
++#if 1
++struct flush_cache_info {
++	unsigned int	addr;
++	unsigned int	len;
++#define WBACK		DMA_TO_DEVICE
++#define INV		DMA_FROM_DEVICE
++#define WBACK_INV	DMA_BIDIRECTIONAL
++	unsigned int	dir;
++};
++#endif
++
++static void jz_avpu_release(struct device *dev)
++{
++    return;
++}
++
++#define AVPU_IOBASE    0x13200000
++#define AVPU_IOBASE_UNIT(ID)	(AVPU_IOBASE + 0x400000 * ID)
++static u64 avpu_dmamask = ~(u64)0;
++static struct resource jz_avpu_irq_resources[] = {			\
++	[0] = {								\
++		.start          = AVPU_IOBASE_UNIT(0),			\
++		.end            = AVPU_IOBASE_UNIT(0) + 0x100000 - 1,	\
++		.flags          = IORESOURCE_MEM,			\
++	},								\
++	[1] = {								\
++		.start          = 32+30+8,		\
++		.end            = 32+30+8,	\
++		.flags          = IORESOURCE_IRQ,			\
++	},
++};
++
++struct platform_device jz_avpu_irq_device = {					\
++	.name = "avpu",							\
++	.id = 0,								\
++	.dev = {								\
++		.dma_mask				= &avpu_dmamask,			\
++		.coherent_dma_mask      = 0xffffffff,				\
++		.release                = jz_avpu_release,				\
++	},									\
++	.num_resources  = ARRAY_SIZE(jz_avpu_irq_resources),			\
++	.resource       = jz_avpu_irq_resources,				\
++};
++
++int channel_is_ready(struct avpu_codec_chan *chan)
++{
++	unsigned long flags;
++	int ret = chan->unblock;
++
++	spin_lock_irqsave(&chan->codec->i_lock, flags);
++	ret = ret || !list_empty(&chan->codec->irq_masks);
++	spin_unlock_irqrestore(&chan->codec->i_lock, flags);
++	return ret;
++}
++
++static int avpu_codec_open(struct inode *inode, struct file *filp)
++{
++	struct avpu_codec_chan *chan;
++	int ret;
++	/* initialize channel */
++//	printk("--------------%s(%d)-----------\n", __func__, __LINE__);
++	chan = kzalloc(sizeof(struct avpu_codec_chan), GFP_KERNEL);
++	if (!chan) {
++		ret = -ENOMEM;
++		goto fail;
++	}
++
++	INIT_LIST_HEAD(&chan->mem);
++	spin_lock_init(&chan->lock);
++	chan->num_bufs = 0;
++
++	filp->private_data = chan;
++
++	/* irq */
++	init_waitqueue_head(&chan->irq_queue);
++
++	ret = avpu_codec_bind_channel(chan, inode);
++	if (ret)
++		goto fail_codec_binding;
++//	printk("--------------%s(%d)-----------\n", __func__, __LINE__);
++	return 0;
++
++fail_codec_binding:
++//	printk("--------------%s(%d)-----------\n", __func__, __LINE__);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,10, 0)
++	kfree_sensitive(chan);
++#else
++	kzfree(chan);
++#endif
++fail:
++//	printk("--------------%s(%d)-----------\n", __func__, __LINE__);
++	return ret;
++}
++
++static int avpu_codec_release(struct inode *inode, struct file *filp)
++{
++	struct avpu_codec_chan *chan = filp->private_data;
++	struct avpu_dma_buf_mmap *tmp;
++	struct list_head *pos, *n;
++//	printk("--------------%s(%d)-----------\n", __func__, __LINE__);
++	avpu_codec_unbind_channel(chan);
++	list_for_each_safe(pos, n, &chan->mem){
++		tmp = list_entry(pos, struct avpu_dma_buf_mmap, list);
++		list_del(pos);
++		kfree(tmp);
++	}
++
++	kfree(chan);
++//	printk("--------------%s(%d)-----------\n", __func__, __LINE__);
++	return 0;
++}
++
++static long avpu_codec_compat_ioctl(struct file *file, unsigned int cmd,
++				    unsigned long arg)
++{
++	long ret = -ENOIOCTLCMD;
++
++	if (file->f_op->unlocked_ioctl)
++		ret = file->f_op->unlocked_ioctl(file, cmd, arg);
++
++	return ret;
++}
++
++static struct avpu_dma_buffer *find_buf_by_id(struct avpu_codec_chan *chan, int desc_id)
++{
++	struct avpu_dma_buf_mmap *cur_buf_mmap;
++
++	list_for_each_entry(cur_buf_mmap, &chan->mem, list){
++		if (cur_buf_mmap->buf_id == desc_id)
++			return cur_buf_mmap->buf;
++	}
++
++	return NULL;
++}
++
++static int avpu_dma_mmap(struct file *filp, struct vm_area_struct *vma)
++{
++	struct avpu_codec_chan *chan = filp->private_data;
++	unsigned long start = vma->vm_start;
++	unsigned long vsize = vma->vm_end - start;
++	/* offset if already in page */
++	int desc_id = vma->vm_pgoff;
++	int ret = 0;
++	struct avpu_dma_buffer *buf = find_buf_by_id(chan, desc_id);
++
++	if (!buf)
++		return -EINVAL;
++
++	vma->vm_pgoff = 0;
++
++	ret = dma_mmap_coherent(chan->codec->device, vma, buf->cpu_handle,
++				buf->dma_handle, vsize);
++	if (ret < 0) {
++		pr_err("Remapping memory failed, error: %d\n", ret);
++		return ret;
++	}
++
++	vma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP;
++
++	return 0;
++}
++
++static int unblock_channel(struct avpu_codec_chan *chan)
++{
++	chan->unblock = 1;
++//	printk("--------------%s(%d)-----------\n", __func__, __LINE__);
++	wake_up_interruptible(&chan->irq_queue);
++	return 0;
++}
++
++static int wait_irq(struct avpu_codec_chan *chan, unsigned long arg)
++{
++	struct avpu_codec_desc *codec = chan->codec;
++	int callback;
++	struct r_irq *i_callback;
++	unsigned long flags;
++	int ret;
++
++//	printk("--------------%s(%d)-----------\n", __func__, __LINE__);
++	ret = wait_event_interruptible(chan->irq_queue,
++				       channel_is_ready(chan));
++//	printk("--------------%s(%d)-----------\n", __func__, __LINE__);
++	if (ret == -ERESTARTSYS)
++		return ret;
++	if (chan->unblock) {
++		avpu_dbg("Unblocking channel\n");
++		return -EINTR;
++	}
++
++//	printk("--------------%s(%d)-----------\n", __func__, __LINE__);
++	spin_lock_irqsave(&codec->i_lock, flags);
++	i_callback = list_first_entry(&chan->codec->irq_masks,
++				      struct r_irq, list);
++	callback = i_callback->bitfield;
++	list_del(&i_callback->list);
++	kmem_cache_free(codec->cache, i_callback);
++	spin_unlock_irqrestore(&codec->i_lock, flags);
++//	printk("--------------%s(%d)-----------\n", __func__, __LINE__);
++
++	if (copy_to_user((void *)arg, &callback, sizeof(__u32)))
++		return -EFAULT;
++
++	return ret;
++}
++
++static int read_reg(struct avpu_codec_chan *chan, unsigned long arg)
++{
++	struct avpu_reg reg;
++	struct avpu_codec_desc *codec = chan->codec;
++	int err;
++
++	if (copy_from_user(&reg, (struct avpu_reg *)arg, sizeof(struct avpu_reg)))
++		return -EFAULT;
++
++	if (reg.id % 4) {
++		avpu_err("Unaligned register access: 0x%.4X\n",
++			reg.id);
++		return -EINVAL;
++	}
++	if (reg.id < 0x8000 || reg.id > chan->codec->regs_size) {
++		avpu_err("Out-of-range register read: 0x%.4X\n",
++			reg.id);
++		return -EINVAL;
++	}
++
++	err = avpu_codec_read_register(chan, &reg);
++	if (err)
++		return err;
++
++	if (copy_to_user((struct avpu_reg *)arg, &reg, sizeof(struct avpu_reg)))
++		return -EFAULT;
++
++	avpu_dbg("Reg read: 0x%.4X: 0x%.8x\n", reg.id, reg.value);
++
++	return 0;
++}
++
++static int write_reg(struct avpu_codec_chan *chan, unsigned long arg)
++{
++	struct avpu_reg reg;
++	struct avpu_codec_desc *codec = chan->codec;
++
++	if (copy_from_user(&reg, (struct avpu_reg *)arg, sizeof(struct avpu_reg)))
++		return -EFAULT;
++		avpu_dbg("Reg write: 0x%.4X: 0x%.8x\n", reg.id, reg.value);
++	if (reg.id == 0x8084 || reg.id == 0x8094)
++		avpu_dbg("Reg write: 0x%.4X: 0x%.8x\n", reg.id, reg.value);
++
++	if (reg.id % 4) {
++		avpu_err("Unaligned register access: 0x%.4X\n",
++			reg.id);
++		return -EINVAL;
++	}
++	if (reg.id < 0x8000 || reg.id > chan->codec->regs_size) {
++		avpu_dbg("Out-of-range register write: 0x%.4X\n", reg.id);
++		return -EINVAL;
++	}
++
++	avpu_codec_write_register(chan, &reg);
++
++	if (copy_to_user((struct avpu_reg *)arg, &reg, sizeof(struct avpu_reg)))
++		return -EFAULT;
++
++	return 0;
++}
++#if 1
++static long jz_cmd_flush_cache(long arg)
++{
++	struct flush_cache_info info;
++	long ret = 0;
++	if (copy_from_user(&info, (void *)arg, sizeof(info))) {
++		return -EFAULT;
++	}
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,10, 0)
++	if(info.dir == DMA_BIDIRECTIONAL)
++		dma_cache_wback_inv(info.addr ,info.len);
++	else if(info.dir == DMA_TO_DEVICE){
++		dma_cache_wback(info.addr,info.len);
++	} else {
++		dma_cache_inv(info.addr,info.len);
++	};
++#else
++	dma_cache_sync(NULL, (void *)info.addr, info.len, info.dir);
++#endif
++	return ret;
++}
++#endif
++static long avpu_codec_ioctl(struct file *filp, unsigned int cmd,
++			     unsigned long arg)
++{
++	struct avpu_codec_chan *chan = filp->private_data;
++	struct avpu_codec_desc *codec = chan->codec;
++
++	switch (cmd) {
++	case GET_DMA_MMAP:
++		return avpu_ioctl_get_dma_mmap(codec->device, chan, arg);
++	case GET_DMA_FD:
++		return avpu_ioctl_get_dma_fd(codec->device, arg);
++	case GET_DMA_PHY:
++		return avpu_ioctl_get_dmabuf_dma_addr(codec->device, arg);
++	case AL_CMD_UNBLOCK_CHANNEL:
++		return unblock_channel(chan);
++	case AL_CMD_IP_WAIT_IRQ:
++		return wait_irq(chan, arg);
++	case AL_CMD_IP_READ_REG:
++		return read_reg(chan, arg);
++	case AL_CMD_IP_WRITE_REG:
++		return write_reg(chan, arg);
++	case JZ_CMD_FLUSH_CACHE:
++		return jz_cmd_flush_cache(arg);
++	default:
++		avpu_err("Unknown ioctl: 0x%.8X\n", cmd);
++		return -EINVAL;
++	}
++}
++
++const struct file_operations avpu_codec_fops = {
++	.owner		= THIS_MODULE,
++	.open		= avpu_codec_open,
++	.release	= avpu_codec_release,
++	.unlocked_ioctl = avpu_codec_ioctl,
++	.compat_ioctl	= avpu_codec_compat_ioctl,
++	.mmap		= avpu_dma_mmap,
++};
++
++void clean_up_avpu_codec_cdev(struct avpu_codec_desc *dev)
++{
++	cdev_del(&dev->cdev);
++}
++
++int setup_chrdev_region(void)
++{
++	dev_t dev = 0;
++	int err;
++
++	if (avpu_codec_major == 0) {
++		err = alloc_chrdev_region(&dev, 0, avpu_codec_nr_devs, "avpu");
++		avpu_codec_major = MAJOR(dev);
++
++		if (err) {
++			pr_alert("Allegro codec: can't get major %d\n",
++				 avpu_codec_major);
++			return err;
++		}
++	}
++	return 0;
++}
++
++int avpu_setup_codec_cdev(struct avpu_codec_desc *codec, int minor,
++			  const char *device_name)
++{
++	struct device *device;
++	int err, devno =
++		MKDEV(avpu_codec_major, minor);
++
++	cdev_init(&codec->cdev, &avpu_codec_fops);
++	codec->cdev.owner = THIS_MODULE;
++	err = cdev_add(&codec->cdev, devno, 1);
++	if (err) {
++		avpu_err("Error %d adding avpu device number %d", err, minor);
++		return err;
++	}
++
++	if (device_name != NULL) {
++		device = device_create(module_class, NULL, devno, NULL,
++				       device_name);
++		if (IS_ERR(device)) {
++			pr_err("device not created\n");
++			clean_up_avpu_codec_cdev(codec);
++			return PTR_ERR(device);
++		}
++	}
++
++	return 0;
++}
++
++static int init_codec_desc(struct avpu_codec_desc *codec)
++{
++	INIT_LIST_HEAD(&codec->irq_masks);
++	spin_lock_init(&codec->i_lock);
++	/* make chan requirement explicit */
++	codec->chan = NULL;
++	codec->cache =  kmem_cache_create("avpu_codec_ram",
++					  sizeof(struct r_irq),
++					  0, SLAB_HWCACHE_ALIGN, NULL);
++	if (!codec->cache)
++		return -ENOMEM;
++
++	return 0;
++}
++
++static void deinit_codec_desc(struct avpu_codec_desc *codec)
++{
++	kmem_cache_destroy(codec->cache);
++}
++
++int avpu_codec_probe(struct platform_device *pdev)
++{
++	int err, irq;
++    int ret = -1;
++	static int current_minor;
++	struct resource *res;
++	struct avpu_codec_desc *codec
++		= devm_kzalloc(&pdev->dev, sizeof(*codec), GFP_KERNEL);
++	char *device_name;
++	bool has_irq = false;
++
++	if (!codec)
++		return -ENOMEM;
++
++	codec->device = &pdev->dev;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res) {
++		avpu_err("Can't get resource\n");
++		err = -ENODEV;
++		goto out_no_resource;
++	}
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,10, 0)
++	/* willd be marked as uncahable  */
++	codec->regs = devm_ioremap_wc(&pdev->dev,
++					   res->start, resource_size(res));
++#else
++	codec->regs = devm_ioremap_nocache(&pdev->dev,
++					   res->start, resource_size(res));
++#endif
++	codec->regs_size = res->end - res->start;
++
++	if (IS_ERR(codec->regs)) {
++		avpu_err("Can't map registers\n");
++		err = PTR_ERR(codec->regs);
++		goto out_map_register;
++	}
++
++	has_irq = true;
++	irq = platform_get_irq(pdev, 0);
++	if (irq < 0) {
++		avpu_info("No irq requested / Couldn't obtain request irq\n");
++		has_irq = false;
++	}
++
++#ifdef CONFIG_SOC_X2500
++	codec->ahb1_gate = clk_get(&pdev->dev, "gate_ahb1");
++	if (IS_ERR(codec->ahb1_gate)) {
++		avpu_err("ahb1_gate get failed\n");
++		err = PTR_ERR(codec->ahb1_gate);
++		goto out_get_ahb1_clk_gate;
++	}
++
++	codec->clk_gate = clk_get(&pdev->dev, "gate_el150");
++	if (IS_ERR(codec->clk_gate)) {
++		avpu_err("clk_gate get failed\n");
++		err = PTR_ERR(codec->clk_gate);
++		goto out_get_clk_gate;
++	}
++
++	codec->clk_mux = clk_get(&pdev->dev,"mux_el150");
++	if (IS_ERR(codec->clk_mux)) {
++		avpu_err("clk get failed\n");
++		err = PTR_ERR(codec->clk_mux);
++		goto out_get_vpu_clk_cgu;
++	}
++
++	ret = clk_set_parent(codec->clk_mux, clk_get(NULL, clk_name));
++    if (ret){
++        printk("clk_set_parent failed!!! parent name = %s\n", clk_name);
++    }
++	codec->clk = clk_get(&pdev->dev,"div_el150");
++	if (IS_ERR(codec->clk)) {
++		avpu_err("clk get failed\n");
++		err = PTR_ERR(codec->clk);
++		goto out_get_vpu_clk_cgu;
++	}
++	clk_set_rate(codec->clk, avpu_clk);
++
++	clk_prepare_enable(codec->ahb1_gate);
++	clk_prepare_enable(codec->clk_gate);
++	clk_prepare_enable(codec->clk);
++#else
++	codec->ahb1_gate = clk_get(&pdev->dev, "ahb1");
++	if (IS_ERR(codec->ahb1_gate)) {
++		avpu_err("ahb1_gate get failed\n");
++		err = PTR_ERR(codec->ahb1_gate);
++		goto out_get_ahb1_clk_gate;
++	}
++
++	codec->clk_gate = clk_get(&pdev->dev, "avpu");
++	if (IS_ERR(codec->clk_gate)) {
++		avpu_err("clk_gate get failed\n");
++		err = PTR_ERR(codec->clk_gate);
++		goto out_get_clk_gate;
++	}
++
++	codec->clk = clk_get(&pdev->dev,"cgu_vpu");
++	if (IS_ERR(codec->clk)) {
++		avpu_err("clk get failed\n");
++		err = PTR_ERR(codec->clk);
++		goto out_get_vpu_clk_cgu;
++	}
++	ret = clk_set_parent(codec->clk, clk_get(NULL, clk_name));
++	if (ret){
++		printk("clk_set_parent failed!!! parent name = %s\n", clk_name);
++	}
++	clk_set_rate(codec->clk, avpu_clk);
++#endif
++
++	err = init_codec_desc(codec);
++	if (err)
++		goto out_failed_request_irq;
++
++	if (has_irq) {
++		err = devm_request_irq(codec->device,
++				       irq,
++				       avpu_hardirq_handler,
++				       IRQF_SHARED, dev_name(&pdev->dev), codec);
++		if (err) {
++			avpu_err("Failed to request IRQ #%d -> :%d\n",
++				irq, err);
++			goto out_failed_request_irq;
++		}
++	}
++
++	platform_set_drvdata(pdev, codec);
++
++	if (of_property_read_string(codec->device->of_node, "t31,devicename",
++				    (const char **)&device_name) != 0)
++		device_name = NULL;
++
++	err = avpu_setup_codec_cdev(codec, current_minor, DEV_NAME);
++	if (err)
++		return err;
++
++	codec->minor = current_minor;
++	++current_minor;
++
++	ret = of_reserved_mem_device_init(codec->device);
++	if(ret)
++		    dev_warn(codec->device, "failed to init reserved mem\n");
++	return 0;
++
++out_failed_request_irq:
++out_get_vpu_clk_cgu:
++out_get_clk_gate:
++out_get_ahb1_clk_gate:
++out_map_register:
++out_no_resource:
++	return err;
++
++}
++
++int avpu_codec_remove(struct platform_device *pdev)
++{
++	struct avpu_codec_desc *codec = platform_get_drvdata(pdev);
++	dev_t dev = MKDEV(avpu_codec_major, codec->minor);
++
++#ifdef CONFIG_SOC_X2500
++	clk_disable_unprepare(codec->clk);
++	clk_disable_unprepare(codec->clk_gate);
++	clk_disable_unprepare(codec->ahb1_gate);
++#else
++	clk_put(codec->clk);
++	clk_put(codec->clk_gate);
++	clk_put(codec->ahb1_gate);
++#endif
++
++	device_destroy(module_class, dev);
++	clean_up_avpu_codec_cdev(codec);
++	deinit_codec_desc(codec);
++
++	return 0;
++}
++
++static const struct of_device_id avpu_codec_of_match[] = {
++	{ .compatible = "t31,avpu" },
++	{ .compatible = "ingenic,x2500-el150"},
++	{ /* sentinel */ },
++};
++
++MODULE_DEVICE_TABLE(of, avpu_codec_of_match);
++
++static struct platform_driver avpu_platform_driver = {
++	.probe			= avpu_codec_probe,
++	.remove			= avpu_codec_remove,
++	.driver			=       {
++		.name		= "avpu",
++		.of_match_table = of_match_ptr(avpu_codec_of_match),
++	},
++};
++
++static int create_module_class(void)
++{
++	module_class = class_create(THIS_MODULE, "avpu_class");
++	if (IS_ERR(module_class))
++		return PTR_ERR(module_class);
++
++	return 0;
++}
++
++static void destroy_module_class(void)
++{
++	class_destroy(module_class);
++}
++
++int avpu_module_init(void)
++{
++	int ret;
++	ret = platform_driver_register(&avpu_platform_driver);
++
++	return ret;
++}
++
++void avpu_module_deinit(void)
++{
++	platform_driver_unregister(&avpu_platform_driver);
++}
++
++static int __init avpu_codec_init(void)
++{
++	dev_t devno;
++	int err = setup_chrdev_region();
++
++	if (err)
++		return err;
++
++	err = create_module_class();
++	if (err)
++		goto fail;
++
++	err = avpu_module_init();
++	if (err)
++		goto fail;
++
++	return 0;
++
++fail:
++	devno = MKDEV(avpu_codec_major, 0);
++	unregister_chrdev_region(devno, avpu_codec_nr_devs);
++
++	return err;
++}
++
++static void __exit avpu_codec_exit(void)
++{
++	dev_t devno = MKDEV(avpu_codec_major, 0);
++
++	avpu_module_deinit();
++	destroy_module_class();
++	unregister_chrdev_region(devno, avpu_codec_nr_devs);
++}
++
++module_init(avpu_codec_init);
++module_exit(avpu_codec_exit);
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Kevin Grandemange");
++MODULE_AUTHOR("Sebastien Alaiwan");
++MODULE_DESCRIPTION("T31 Vpu Driver");
+diff --git a/module_drivers/drivers/video/ingenic_avpu/avpu_no_dmabuf.c b/module_drivers/drivers/video/ingenic_avpu/avpu_no_dmabuf.c
+new file mode 100644
+index 000000000..1777f6c68
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_avpu/avpu_no_dmabuf.c
+@@ -0,0 +1,21 @@
++#include "avpu_dmabuf.h"
++
++int avpu_create_dmabuf_fd(struct device *dev, unsigned long size,
++			 struct avpu_dma_buffer *buffer)
++{
++	pr_err("dmabuf interface not supported");
++	return -EINVAL;
++}
++
++int avpu_allocate_dmabuf(struct device *dev, int size, u32 *fd)
++{
++	pr_err("dmabuf interface not supported");
++	return -EINVAL;
++}
++
++int avpu_dmabuf_get_address(struct device *dev, u32 fd, u32 *bus_address)
++{
++	pr_err("dmabuf interface not supported");
++	return -EINVAL;
++}
++
+diff --git a/module_drivers/drivers/video/ingenic_bscaler/Kconfig b/module_drivers/drivers/video/ingenic_bscaler/Kconfig
+new file mode 100644
+index 000000000..f10706f27
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_bscaler/Kconfig
+@@ -0,0 +1,4 @@
++config INGENIC_BSCALER
++    bool "[BSCALER] jz bscaler driver"
++    depends on SOC_X2500
++    default n
+diff --git a/module_drivers/drivers/video/ingenic_bscaler/Makefile b/module_drivers/drivers/video/ingenic_bscaler/Makefile
+new file mode 100644
+index 000000000..c2bf093c7
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_bscaler/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_INGENIC_BSCALER) += ingenic_bscaler.o
+diff --git a/module_drivers/drivers/video/ingenic_bscaler/ingenic_bscaler.c b/module_drivers/drivers/video/ingenic_bscaler/ingenic_bscaler.c
+new file mode 100644
+index 000000000..da0b826bf
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_bscaler/ingenic_bscaler.c
+@@ -0,0 +1,387 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/fs.h>
++#include <linux/irq.h>
++#include <linux/mm.h>
++#include <linux/slab.h>
++#include <linux/miscdevice.h>
++#include <linux/dma-mapping.h>
++#include <linux/syscalls.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++#include <soc/base.h>
++#include <soc/cpm.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/completion.h>
++#include <asm/delay.h>
++#include <linux/proc_fs.h>
++
++#define JZ_BSCALER_NUM      2
++
++#define IOCTL_BSCALER0_IRQ_GET_STAT	0x000
++#define IOCTL_BSCALER1_IRQ_GET_STAT	0x100
++
++#define REG_BSCALER_STAT0       (0x00)
++#define REG_BSCALER_CTRL0       (0xb0)	//44*4 FRMT
++#define REG_BSCALER_STAT1       (0x80)
++#define REG_BSCALER_CTRL1       (0x30)	//12*4	FRMC
++
++struct jz_bscaler_context {
++	int			irq;
++	struct completion	done;
++	spinlock_t		slock;
++	unsigned int		status;
++};
++
++struct jz_bscaler {
++	char				name[16];
++	char				irq_name[32];;
++	int				idx;
++	void __iomem			*iomem;
++	struct clk			*clk;
++	struct clk			*clk_gate;
++	struct clk			*ahb0_gate;
++	pid_t				owner_pid;
++	struct jz_bscaler_context	ctx[JZ_BSCALER_NUM];
++	struct miscdevice		mdev;
++	struct mutex			openmutex;
++	int				opencnt;
++};
++
++#define jz_bscaler_readl(bscaler, offset)		__raw_readl((bscaler)->iomem + offset)
++#define jz_bscaler_writel(bscaler, offset, value)	__raw_writel((value), (bscaler)->iomem + offset)
++
++#define CLEAR_RADIX_BIT(bscaler,offset,bm)				\
++	do {							\
++		unsigned int stat;				\
++		stat = jz_bscaler_readl(bscaler,offset);			\
++		jz_bscaler_writel(bscaler,offset,stat & ~(bm));		\
++	} while(0)
++
++static irqreturn_t jz_bscaler_interrupt_t(int irq, void *data)
++{
++	struct jz_bscaler *bscaler = (struct jz_bscaler *)data;
++	struct jz_bscaler_context *ctx = NULL;
++	unsigned int reg_ctrl = 0, reg_stat = 0;
++
++
++	spin_lock(&bscaler->ctx[0].slock);
++	if (irq == bscaler->ctx[0].irq) {
++		ctx = &(bscaler->ctx[0]);
++		reg_ctrl = REG_BSCALER_CTRL0;
++	} else {
++		printk("irq error!\n");
++		return -1;
++	}
++
++	if (jz_bscaler_readl(bscaler, 0x80) & 0x100) {
++		jz_bscaler_writel(bscaler, 0x80 ,(jz_bscaler_readl(bscaler, 0x80) & ~0x100));
++	}
++
++	if (jz_bscaler_readl(bscaler, 0x84) & 0x4) {
++		jz_bscaler_writel(bscaler, 0x84 ,(jz_bscaler_readl(bscaler, 0x84) & ~0x4));
++	}
++	if (jz_bscaler_readl(bscaler, 0xb0) & 0x50) {
++		if (jz_bscaler_readl(bscaler, 0xb0) & 0x40) {
++			printk("ERROR: bscaler T irq timeout!!!\n");
++		}
++		jz_bscaler_writel(bscaler, 0xb0 ,(jz_bscaler_readl(bscaler, 0xb0) & ~0x50));
++	}
++
++
++	ctx->status = jz_bscaler_readl(bscaler, reg_stat);
++	dev_dbg(bscaler->mdev.this_device, "In bscaler0_interrupt : irq=%d, status = 0x%08x\n", irq, ctx->status);
++	complete(&ctx->done);
++
++	spin_unlock(&bscaler->ctx[0].slock);
++
++	return IRQ_HANDLED;
++}
++
++
++static irqreturn_t jz_bscaler_interrupt_c(int irq, void *data)
++{
++	struct jz_bscaler *bscaler = (struct jz_bscaler *)data;
++	struct jz_bscaler_context *ctx = NULL;
++	unsigned int reg_ctrl = 0, reg_stat = 0;
++
++
++	spin_lock(&bscaler->ctx[1].slock);
++	if (irq == bscaler->ctx[1].irq) {
++		ctx = &(bscaler->ctx[1]);
++		reg_ctrl = REG_BSCALER_CTRL1;
++	} else {
++		printk("irq error!\n");
++		return -1;
++	}
++
++	if (jz_bscaler_readl(bscaler, 0x0) & 0x100) {
++		jz_bscaler_writel(bscaler, 0x0 ,(jz_bscaler_readl(bscaler, 0x0) & ~0x100));
++	}
++
++	if (jz_bscaler_readl(bscaler, 0x30) & 0x50) {
++		if (jz_bscaler_readl(bscaler, 0x30) & 0x40) {
++			printk("ERROR: bscaler C irq timeout!!!\n");
++		}
++		jz_bscaler_writel(bscaler, 0x30 ,(jz_bscaler_readl(bscaler, 0x30) & ~0x50));
++	}
++
++	ctx->status = jz_bscaler_readl(bscaler, reg_stat);
++	dev_dbg(bscaler->mdev.this_device, "In bscaler0_interrupt : irq=%d, status = 0x%08x\n", irq, ctx->status);
++	complete(&ctx->done);
++
++	spin_unlock(&bscaler->ctx[1].slock);
++
++	return IRQ_HANDLED;
++}
++
++
++static int jz_bscaler_open(struct inode *inode, struct file *file)
++{
++	int i = 0;
++	struct miscdevice *mdev = file->private_data;
++	struct jz_bscaler *bscaler = list_entry(mdev, struct jz_bscaler, mdev);
++
++	clk_prepare_enable(bscaler->clk);
++	clk_prepare_enable(bscaler->clk_gate);
++	mutex_lock(&bscaler->openmutex);
++	if (!bscaler->opencnt) {
++		for (i = 0; i < JZ_BSCALER_NUM; i++) {
++			bscaler->ctx[i].done.done = 0;
++			enable_irq(bscaler->ctx[i].irq);
++		}
++	}
++	bscaler->opencnt++;
++	mutex_unlock(&bscaler->openmutex);
++
++	dev_dbg(mdev->this_device, "%s open successful, opencnt=%d!\n", __func__, bscaler->opencnt);
++
++	return 0;
++}
++
++static int jz_bscaler_release(struct inode *inode, struct file *file)
++{
++	int i = 0;
++	struct miscdevice *mdev = file->private_data;
++	struct jz_bscaler *bscaler = list_entry(mdev, struct jz_bscaler, mdev);
++
++	mutex_lock(&bscaler->openmutex);
++	if (bscaler->opencnt == 1) {
++		for (i = 0; i < JZ_BSCALER_NUM; i++) {
++			disable_irq(bscaler->ctx[i].irq);
++			bscaler->ctx[i].done.done = 0;
++		}
++		clk_disable(bscaler->clk);
++		clk_disable(bscaler->clk_gate);
++		bscaler->opencnt--;
++	}
++	mutex_unlock(&bscaler->openmutex);
++
++	dev_dbg(mdev->this_device, "%s close successful, opencnt=%d!\n", __func__, bscaler->opencnt);
++
++	return 0;
++}
++
++static ssize_t jz_bscaler_read(struct file *file, char __user * buffer, size_t count, loff_t * ppos)
++{
++	return 0;
++}
++
++static ssize_t jz_bscaler_write(struct file *file, const char __user * buffer, size_t count, loff_t * ppos)
++{
++	return 0;
++}
++
++static long jz_bscaler_wait_irq(struct jz_bscaler *bscaler, int bscaler_idx, unsigned long arg)
++{
++	long ret = 0;
++	dev_dbg(bscaler->mdev.this_device, "%s:bscaler index=%d start\n", __func__, bscaler_idx);
++	ret = wait_for_completion_timeout(&bscaler->ctx[bscaler_idx].done, msecs_to_jiffies(10*1000));
++	if (ret <= 0) {
++		dev_err(bscaler->mdev.this_device, "copy_to_user bscaler index=%d timeout!\n", bscaler_idx);
++		return -EFAULT;
++	}
++	if (copy_to_user((void *)arg, &bscaler->ctx[bscaler_idx].status, sizeof(unsigned int))) {
++		dev_err(bscaler->mdev.this_device, "copy_to_user bscaler index=%d, stat=0x%x failed!\n", bscaler_idx, bscaler->ctx[bscaler_idx].status);
++		return -EFAULT;
++	}
++	dev_dbg(bscaler->mdev.this_device, "%s:bscaler index=%d end\n", __func__, bscaler_idx);
++
++	return 0;
++}
++
++static long jz_bscaler_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
++{
++	struct miscdevice *mdev = file->private_data;
++	struct jz_bscaler *bscaler = list_entry(mdev, struct jz_bscaler, mdev);
++
++	switch(cmd) {
++		case IOCTL_BSCALER0_IRQ_GET_STAT:
++			return jz_bscaler_wait_irq(bscaler, 0, arg);
++		case IOCTL_BSCALER1_IRQ_GET_STAT:
++			return jz_bscaler_wait_irq(bscaler, 1, arg);
++		default:
++			dev_err(mdev->this_device, "%s:invalid cmd %u\n", __func__, cmd);
++			return -1;
++	}
++
++	return 0;
++}
++
++const struct file_operations jz_bscaler_fops = {
++	.owner = THIS_MODULE,
++	.open = jz_bscaler_open,
++	.release = jz_bscaler_release,
++	.read = jz_bscaler_read,
++	.write = jz_bscaler_write,
++	.unlocked_ioctl = jz_bscaler_ioctl,
++};
++
++static int jz_bscaler_probe(struct platform_device *pdev)
++{
++	int ret = 0, i = 0;
++	struct resource *regs = NULL;
++	struct jz_bscaler *bscaler = NULL;
++
++	bscaler = devm_kzalloc(&pdev->dev, sizeof(struct jz_bscaler), GFP_KERNEL);
++	if (!bscaler) {
++		dev_err(&pdev->dev, "kzalloc struct jz_bscaler failed\n");
++		ret = -ENOMEM;
++		goto err_kzalloc_bscaler;
++	}
++
++
++	pdev->id = of_alias_get_id(pdev->dev.of_node, "bscaler");
++	bscaler->idx = pdev->id;
++	sprintf(bscaler->name, "%s%d", "bscaler", pdev->id);
++
++	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!regs) {
++		dev_err(&pdev->dev, "No iomem resource\n");
++		ret = -ENXIO;
++		goto err_get_bscaler_resource;
++	}
++
++	bscaler->iomem = devm_ioremap_resource(&pdev->dev, regs);
++	if (!bscaler->iomem) {
++		dev_err(&pdev->dev, "ioremap failed\n");
++		ret = -ENXIO;
++		goto err_get_bscaler_iomem;
++	}
++	bscaler->clk_gate = devm_clk_get(&pdev->dev, "gate_bscaler");
++	if (IS_ERR(bscaler->clk_gate)) {
++		dev_err(&pdev->dev, "clk_gate get bscaler failed\n");
++		ret = PTR_ERR(bscaler->clk_gate);
++		goto err_get_bscaler_clk_gate;
++	}
++	bscaler->clk = devm_clk_get(&pdev->dev,"div_bscaler");
++	if (IS_ERR(bscaler->clk)) {
++		dev_err(&pdev->dev, "clk get cgu_bscaler failed\n");
++		ret = PTR_ERR(bscaler->clk);
++		goto err_get_bscaler_clk_cgu;
++	}
++
++	clk_set_parent(bscaler->clk, clk_get(NULL, "epll"));
++	clk_set_rate(bscaler->clk,400000000);
++
++	for (i = 0; i < JZ_BSCALER_NUM; i++) {
++		bscaler->ctx[i].irq = platform_get_irq(pdev, i);
++		if(bscaler->ctx[i].irq < 0) {
++			dev_err(&pdev->dev, "get irq %d failed\n", i);
++			goto err_get_bscaler_irq;
++		}
++		sprintf(bscaler->irq_name, "%s%d", bscaler->name, bscaler->ctx[i].irq);
++
++		ret = devm_request_irq(&pdev->dev, bscaler->ctx[i].irq, i == 0 ? jz_bscaler_interrupt_t:jz_bscaler_interrupt_c, 0, bscaler->irq_name, bscaler);
++		if (ret < 0) {
++			dev_err(&pdev->dev, "request_irq i=%d, irq=%d failed\n", i, bscaler->ctx[i].irq);
++			goto err_bscaler_helix_irq;
++		}
++		disable_irq_nosync(bscaler->ctx[i].irq);
++
++		init_completion(&bscaler->ctx[i].done);
++		spin_lock_init(&bscaler->ctx[i].slock);
++	}
++	mutex_init(&bscaler->openmutex);
++	bscaler->opencnt = 0;
++
++
++	bscaler->mdev.minor = MISC_DYNAMIC_MINOR;
++	bscaler->mdev.fops = &jz_bscaler_fops;
++	bscaler->mdev.name = bscaler->name;
++	ret = misc_register(&bscaler->mdev);
++	if(ret < 0) {
++		dev_err(&pdev->dev,"request bscaler misc device failed!\n");
++		goto err_bscaler_register;
++	}
++	platform_set_drvdata(pdev, bscaler);
++	return 0;
++
++err_bscaler_register:
++	i = JZ_BSCALER_NUM;
++err_bscaler_helix_irq:
++err_get_bscaler_irq:
++	for (--i; i >= 0; i--) {
++		free_irq(bscaler->ctx[i].irq, bscaler);
++	}
++	clk_put(bscaler->clk);
++err_get_bscaler_clk_cgu:
++	clk_put(bscaler->clk_gate);
++err_get_bscaler_clk_gate:
++	iounmap(bscaler->iomem);
++err_get_bscaler_iomem:
++err_get_bscaler_resource:
++	kfree(bscaler);
++	bscaler = NULL;
++err_kzalloc_bscaler:
++	return ret;
++}
++
++static int jz_bscaler_remove(struct platform_device *pdev)
++{
++	int i;
++	struct jz_bscaler *bscaler = platform_get_drvdata(pdev);
++
++	misc_deregister(&bscaler->mdev);
++
++	for (i = JZ_BSCALER_NUM - 1; i >= 0; i--) {
++		free_irq(bscaler->ctx[i].irq, bscaler);
++	}
++
++	clk_disable_unprepare(bscaler->clk);
++	clk_disable_unprepare(bscaler->clk_gate);
++
++	devm_iounmap(&pdev->dev, bscaler->iomem);
++
++	if (bscaler) {
++		kfree(bscaler);
++	}
++
++	bscaler = NULL;
++
++	return 0;
++}
++
++static const struct of_device_id ingenic_bscaler_dt_match[] = {
++	{ .compatible = "ingenic,x2500-bscaler", .data = NULL },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ingenic_bscaler_dt_match);
++
++static struct platform_driver jz_bscaler_driver = {
++	.probe		= jz_bscaler_probe,
++	.remove		= jz_bscaler_remove,
++	.driver		= {
++		.name	= "jz-bscaler",
++		.owner	= THIS_MODULE,
++		.of_match_table = of_match_ptr(ingenic_bscaler_dt_match),
++	},
++};
++
++module_platform_driver(jz_bscaler_driver);
++
++MODULE_DESCRIPTION("JZ BSCALER driver");
++MODULE_AUTHOR("Justin <pengtao.kang@ingenic.com>");
++MODULE_LICENSE("GPL v2");
++MODULE_VERSION("20200820");
+diff --git a/module_drivers/drivers/video/ingenic_ipu/Kconfig b/module_drivers/drivers/video/ingenic_ipu/Kconfig
+new file mode 100644
+index 000000000..46755d779
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_ipu/Kconfig
+@@ -0,0 +1,18 @@
++menuconfig JZ_IPU
++	bool "[IPU] JZ ipu unit"
++	depends on SOC_X2500
++	default n
++
++config INGENIC_IPU
++	tristate "Ingenic IPU Driver"
++	depends on JZ_IPU
++	default n
++	help
++	  Support for Ingenic ipu operations.
++
++config INGENIC_DRAWBOX
++	tristate "Ingenic draw box Driver"
++	depends on JZ_IPU
++	default n
++	help
++	  Support for Ingenic ipu operations.
+diff --git a/module_drivers/drivers/video/ingenic_ipu/Makefile b/module_drivers/drivers/video/ingenic_ipu/Makefile
+new file mode 100644
+index 000000000..45d437ef2
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_ipu/Makefile
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_INGENIC_IPU)        += ingenic_ipu_v13.o ipu_dmabuf.o
++obj-$(CONFIG_INGENIC_DRAWBOX)     += ingenic_drawbox.o
+diff --git a/module_drivers/drivers/video/ingenic_ipu/ingenic_drawbox.c b/module_drivers/drivers/video/ingenic_ipu/ingenic_drawbox.c
+new file mode 100644
+index 000000000..7848866d8
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_ipu/ingenic_drawbox.c
+@@ -0,0 +1,625 @@
++/*
++ * Copyright (c) 2015 Ingenic Semiconductor Co., Ltd.
++ *              http://www.ingenic.com/
++ *
++ * Input file for Ingenic DBOX driver
++ *
++ * This  program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++#include <linux/poll.h>
++#include <linux/wait.h>
++#include <linux/fs.h>
++#include <linux/irq.h>
++#include <linux/mm.h>
++#include <linux/fb.h>
++#include <linux/ctype.h>
++#include <linux/dma-mapping.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/memory.h>
++#include <linux/suspend.h>
++#include <linux/miscdevice.h>
++#include <linux/proc_fs.h>
++#include <linux/delay.h>
++#include <linux/completion.h>
++#include <linux/time.h>
++#include <soc/base.h>
++#include <linux/dma-buf.h>
++#include <linux/version.h>
++#include <linux/dma-map-ops.h>
++#include "ingenic_drawbox.h"
++
++// #define DEBUG
++#ifdef	DEBUG
++static int debug_dbox = 1;
++
++#define DBOX_DEBUG(format, ...) { if (debug_dbox) printk(format, ## __VA_ARGS__);}
++#else
++#define DBOX_DEBUG(format, ...) do{ } while(0)
++#endif
++
++#define DBOX_BUF_SIZE (1024 * 1024 * 2)
++
++struct dbox_reg_struct jz_dbox_regs_name[] = {
++	{"DBOX_CTRL", DBOX_CTRL},
++	{"DBOX_YB", DBOX_YB},
++	{"DBOX_CB", DBOX_CB},
++	{"DBOX_STRIDE", DBOX_STRIDE},
++	{"DBOX_IMG_WH", DBOX_IMG_WH},
++	{"DBOX_COLOR_Y", DBOX_COLOR_Y},
++	{"DBOX_COLOR_U", DBOX_COLOR_U},
++	{"DBOX_COLOR_V", DBOX_COLOR_V},
++	{"DBOX_RAM", DBOX_RAM},
++	{"DBOX_TIMEOUT", DBOX_TIMEOUT},
++};
++
++
++static void reg_bit_set(struct jz_dbox *dbox, int offset, unsigned int bit)
++{
++	unsigned int reg = 0;
++	reg = dbox_reg_read(dbox, offset);
++	reg |= bit;
++	dbox_reg_write(dbox, offset, reg);
++}
++
++static void reg_bit_clr(struct jz_dbox *dbox, int offset, unsigned int bit)
++{
++	unsigned int reg = 0;
++	reg= dbox_reg_read(dbox, offset);
++	reg &= ~(bit);
++	dbox_reg_write(dbox, offset, reg);
++}
++
++
++static int _dbox_dump_regs(struct jz_dbox *dbox)
++{
++	int i = 0;
++	int num = 0;
++
++	if (dbox == NULL) {
++		dev_err(dbox->dev, "dbox is NULL!\n");
++		return -1;
++	}
++	printk("----- dump regs -----\n");
++
++	num = sizeof(jz_dbox_regs_name) / sizeof(struct dbox_reg_struct);
++	for (i = 0; i < num; i++) {
++		printk("dbox_reg: %s: \t0x%08x\r\n", jz_dbox_regs_name[i].name, dbox_reg_read(dbox, jz_dbox_regs_name[i].addr));
++	}
++
++	return 0;
++}
++
++static void _dbox_dump_param(struct jz_dbox *dbox)
++{
++	return;
++}
++
++static int dbox_dump_info(struct jz_dbox *dbox)
++{
++	int ret = 0;
++	if (dbox == NULL) {
++		dev_err(dbox->dev, "dbox is NULL\n");
++		return -1;
++	}
++	printk("dbox: dbox->base: %p\n", dbox->iomem);
++	_dbox_dump_param(dbox);
++	ret = _dbox_dump_regs(dbox);
++
++	return ret;
++}
++
++static int dbox_reg_set(struct jz_dbox *dbox, struct dbox_param *dbox_param)
++{
++    unsigned int imgw = 0;
++    unsigned int imgh = 0;
++    unsigned int rectw[128];
++    unsigned int recth[128];
++    unsigned int rectx[128];
++    unsigned int recty[128];
++    unsigned int linew[128];
++    unsigned int linel[128];
++    // unsigned int imgstride = 0;
++    unsigned int img_pbuf_y = 0;
++    unsigned int img_pbuf_uv = 0;
++    unsigned int boxs_num = 0;
++    unsigned int is_rgba = 0;
++    unsigned int i = 0;
++
++    unsigned int dbox_colormode[128];
++    unsigned int dbox_mode[128];
++
++
++    struct dbox_param *ip = dbox_param;
++    if (dbox == NULL) {
++		dev_err(dbox->dev, "dbox: dbox is NULL or dbox_param is NULL\n");
++		return -1;
++	}
++
++    img_pbuf_y = ip->box_pbuf;
++
++    imgw = ip->img_w;
++    imgh = ip->img_h;
++    boxs_num = ip->boxs_num;
++    is_rgba = ip->is_rgba;
++
++    if (1 == is_rgba) {
++        reg_bit_set(dbox, DBOX_CTRL, DBOX_IS_BGRA);
++    } else {
++        reg_bit_clr(dbox, DBOX_CTRL, DBOX_IS_BGRA);
++    }
++
++    img_pbuf_y = ip->box_pbuf;
++    img_pbuf_uv = img_pbuf_y + imgw*imgh;
++    //printk("imgw = %d imgh = %d\n", imgw, imgh);
++
++    dbox_reg_write(dbox, DBOX_IMG_WH, (imgw << DBOX_WIDTH | imgh << DBOX_HEIGHT));
++
++    dbox_reg_write(dbox, DBOX_STRIDE, ((imgw << DBOX_Y_STRIDE) | (imgw << DBOX_C_STRIDE)) );
++
++    /* YUV[0] is red
++     * YUV[1] is black
++     * YUV[2] is green
++     * YUV[3] is yellow
++     * rgb2yuv ==> https://www.mikekohn.net/file_formats/yuv_rgb_converter.php */
++    dbox_reg_write(dbox, DBOX_COLOR_Y, 0xe195004c);
++    dbox_reg_write(dbox, DBOX_COLOR_U, 0x002b8054);
++    dbox_reg_write(dbox, DBOX_COLOR_V, 0x941580ff);
++
++    dbox_reg_write(dbox, DBOX_YB, (img_pbuf_y << DBOX_LUMA_BASE));
++    dbox_reg_write(dbox, DBOX_CB, (img_pbuf_uv << DBOX_CONCENTRATION_BASE));
++
++    for(i=0; i<boxs_num; i++) {
++        rectx[i] = ip->ram_para[i].box_x;
++        recty[i] = ip->ram_para[i].box_y;
++        rectw[i] = ip->ram_para[i].box_w;
++        recth[i] = ip->ram_para[i].box_h;
++        linew[i] = ip->ram_para[i].line_w;
++        linel[i] = ip->ram_para[i].line_l;
++        dbox_mode[i] = ip->ram_para[i].box_mode;
++        dbox_colormode[i] = ip->ram_para[i].color_mode;
++        dbox_reg_write(dbox, DBOX_RAM, (rectx[i] << DBOX_BOX_X) | (recty[i] << DBOX_BOX_Y) | (rectw[i] << DBOX_BOX_WIDTH));
++        dbox_reg_write(dbox, DBOX_RAM, (((rectw[i] >> 8) << 0) | (recth[i] << 4) | (dbox_colormode[i] << 16) | (dbox_mode[i] << 18) | (linew[i] << 20) | (linel[i] << 23)));
++    }
++
++    return 0;
++}
++
++static int dbox_start(struct jz_dbox *dbox, struct dbox_param *dbox_param)
++{
++	int ret = 0;
++	struct dbox_param *ip = dbox_param;
++
++	if ((dbox == NULL) || (dbox_param == NULL)) {
++		dev_err(dbox->dev, "dbox: dbox is NULL or dbox_param is NULL\n");
++		return -1;
++	}
++	DBOX_DEBUG("dbox: enter dbox_start %d\n", current->pid);
++
++#ifndef CONFIG_FPGA_TEST
++	clk_prepare_enable(dbox->clk);
++#endif
++
++	__reset_dbox();
++    /* wait reset complete */
++    while(dbox_reg_read(dbox, DBOX_CTRL) & 0x2) {
++        udelay(10);
++    }
++
++    ret = dbox_reg_set(dbox, ip);
++    __dbox_mask_irq();//mask 0
++
++
++	DBOX_DEBUG("dbox_start\n");
++	/* start dbox */
++	__start_dbox();
++
++#ifdef DEBUG
++	//dbox_dump_info(dbox);
++#endif
++	//DBOX_DEBUG("dbox_start\n");
++
++	ret = wait_for_completion_interruptible_timeout(&dbox->done_dbox, msecs_to_jiffies(5000));
++	if (ret < 0) {
++		printk("dbox: done_dbox wait_for_completion_interruptible_timeout err %d\n", ret);
++		goto err_dbox_wait_for_done;
++	} else if (ret == 0 ) {
++		ret = -1;
++		printk("dbox: done_dbox wait_for_completion_interruptible_timeout timeout %d\n", ret);
++		dbox_dump_info(dbox);
++		goto err_dbox_wait_for_done;
++	} else {
++		;
++	}
++
++    DBOX_DEBUG("dbox: exit dbox_start %d\n", current->pid);
++
++#ifndef CONFIG_FPGA_TEST
++	clk_disable_unprepare(dbox->clk);
++#endif
++
++    return 0;
++
++err_dbox_wait_for_done:
++#ifndef CONFIG_FPGA_TEST
++	clk_disable_unprepare(dbox->clk);
++#endif
++
++	return ret;
++
++}
++
++#ifdef CONFIG_VIDEO_V4L2
++static int dbox_dmabuf_get_phy(struct device *dev,int fd,unsigned int *phyaddr)
++{
++	struct dma_buf_attachment *attach;
++	struct dma_buf *dbuf;
++	struct sg_table *sgt;
++	int err = 0;
++	dbuf = dma_buf_get(fd);
++	if (IS_ERR(dbuf))
++		return -EINVAL;
++	attach = dma_buf_attach(dbuf, dev);
++	if (IS_ERR(attach)) {
++		err = -EINVAL;
++		goto fail_attach;
++	}
++	sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
++	if (IS_ERR(sgt)) {
++		err = -EINVAL;
++		goto fail_map;
++	}
++
++	*phyaddr = sg_dma_address(sgt->sgl);
++
++	dma_buf_unmap_attachment(attach, sgt, DMA_BIDIRECTIONAL);
++fail_map:
++	dma_buf_detach(dbuf, attach);
++fail_attach:
++	dma_buf_put(dbuf);
++	return err;
++}
++#endif
++static long dbox_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
++{
++	int ret = 0;
++	struct dbox_param iparam;
++	struct miscdevice *dev = filp->private_data;
++	struct jz_dbox *dbox = container_of(dev, struct jz_dbox, misc_dev);
++
++	DBOX_DEBUG("dbox: %s pid: %d, tgid: %d file: %p, cmd: 0x%08x\n",
++			__func__, current->pid, current->tgid, filp, cmd);
++
++	if (_IOC_TYPE(cmd) != JZDBOX_IOC_MAGIC) {
++		dev_err(dbox->dev, "invalid cmd!\n");
++		return -EFAULT;
++	}
++
++	mutex_lock(&dbox->mutex);
++
++	switch (cmd) {
++		case IOCTL_DBOX_START:
++			if (copy_from_user(&iparam, (void *)arg, sizeof(struct dbox_param))) {
++				dev_err(dbox->dev, "copy_from_user error!!!\n");
++				ret = -EFAULT;
++				break;
++			}
++			ret = dbox_start(dbox, &iparam);
++			if (ret) {
++				printk("dbox: error dbox start ret = %d\n", ret);
++			}
++			break;
++		case IOCTL_DBOX_GET_PBUFF:
++			if (dbox->pbuf.vaddr_alloc == 0) {
++				unsigned int size = DBOX_BUF_SIZE;
++				dbox->pbuf.vaddr_alloc = (unsigned int)kmalloc(size, GFP_KERNEL);
++				if (!dbox->pbuf.vaddr_alloc) {
++					printk("dbox kmalloc is error\n");
++					ret = -ENOMEM;
++				}
++				memset((void*)(dbox->pbuf.vaddr_alloc), 0x00, size);
++				dbox->pbuf.size = size;
++				dbox->pbuf.paddr = virt_to_phys((void *)(dbox->pbuf.vaddr_alloc));
++				dbox->pbuf.paddr_align = ((unsigned long)(dbox->pbuf.paddr));
++			}
++			DBOX_DEBUG("dbox: %s dbox->pbuf.vaddr_alloc = 0x%08x\ndbox->pbuf.vaddr_align = 0x%08x\ndbox->pbuf.size = 0x%x\ndbox->pbuf.paddr = 0x%08x\n"
++					, __func__, dbox->pbuf.vaddr_alloc, dbox->pbuf.paddr_align, dbox->pbuf.size, dbox->pbuf.paddr);
++			if (copy_to_user((void *)arg, &dbox->pbuf, sizeof(struct dbox_buf_info))) {
++				dev_err(dbox->dev, "copy_to_user error!!!\n");
++				ret = -EFAULT;
++			}
++			break;
++		case IOCTL_DBOX_RES_PBUFF:
++			if (dbox->pbuf.vaddr_alloc != 0) {
++				kfree((void *)dbox->pbuf.vaddr_alloc);
++				dbox->pbuf.vaddr_alloc = 0;
++				dbox->pbuf.size = 0;
++				dbox->pbuf.paddr = 0;
++				dbox->pbuf.paddr_align = 0;
++			} else {
++				dev_warn(dbox->dev, "buffer wanted to free is null\n");
++			}
++			break;
++		case IOCTL_DBOX_BUF_LOCK:
++			ret = wait_for_completion_interruptible_timeout(&dbox->done_buf, msecs_to_jiffies(2000));
++			if (ret < 0) {
++				printk("dbox: done_buf wait_for_completion_interruptible_timeout err %d\n", ret);
++			} else if (ret == 0 ) {
++				printk("dbox: done_buf wait_for_completion_interruptible_timeout timeout %d\n", ret);
++				ret = -1;
++				dbox_dump_info(dbox);
++			} else {
++				ret = 0;
++			}
++			break;
++		case IOCTL_DBOX_BUF_UNLOCK:
++			complete(&dbox->done_buf);
++			break;
++		case IOCTL_DBOX_BUF_FLUSH_CACHE:
++			{
++				struct dbox_flush_cache_para fc;
++				if (copy_from_user(&fc, (void *)arg, sizeof(fc))) {
++					dev_err(dbox->dev, "copy_from_user error!!!\n");
++					ret = -EFAULT;
++					break;
++				}
++				//dma_sync_single_for_device(NULL, fc.addr, fc.size, DMA_TO_DEVICE);
++				//dma_sync_single_for_device(NULL, fc.addr, fc.size, DMA_FROM_DEVICE);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,10, 0)
++				dma_cache_wback_inv((phys_addr_t)fc.addr ,fc.size);
++#else
++				dma_cache_sync(NULL, fc.addr, fc.size, DMA_BIDIRECTIONAL);
++#endif
++			}
++			break;
++#ifdef CONFIG_VIDEO_V4L2
++		case IOCTL_DBOX_GET_DMA_PHY:
++			{
++				unsigned int phyaddr = 0;
++				int fd = 0;
++				if (copy_from_user(&fd, (void *)arg, sizeof(fd))) {
++					dev_err(dbox->dev, "copy_from_user error!!!\n");
++					ret = -EFAULT;
++					break;
++				}
++				ret = dbox_dmabuf_get_phy(dbox->dev,fd,&phyaddr);
++				if (copy_to_user((void *)arg, &phyaddr, sizeof(phyaddr)))
++					return -EFAULT;
++			}
++			break;
++#endif
++	    default:
++			dev_err(dbox->dev, "invalid command: 0x%08x\n", cmd);
++			ret = -EINVAL;
++	}
++
++	mutex_unlock(&dbox->mutex);
++	return ret;
++}
++
++static int dbox_open(struct inode *inode, struct file *filp)
++{
++	int ret = 0;
++
++	struct miscdevice *dev = filp->private_data;
++	struct jz_dbox *dbox = container_of(dev, struct jz_dbox, misc_dev);
++
++	DBOX_DEBUG("dbox: %s pid: %d, tgid: %d filp: %p\n",
++			__func__, current->pid, current->tgid, filp);
++	mutex_lock(&dbox->mutex);
++
++	mutex_unlock(&dbox->mutex);
++	return ret;
++}
++
++static int dbox_release(struct inode *inode, struct file *filp)
++{
++	int ret = 0;
++
++	struct miscdevice *dev = filp->private_data;
++	struct jz_dbox *dbox = container_of(dev, struct jz_dbox, misc_dev);
++
++	DBOX_DEBUG("dbox: %s  pid: %d, tgid: %d filp: %p\n",
++			__func__, current->pid, current->tgid, filp);
++	mutex_lock(&dbox->mutex);
++
++	mutex_unlock(&dbox->mutex);
++	return ret;
++}
++
++static struct file_operations dbox_ops = {
++	.owner = THIS_MODULE,
++	.open = dbox_open,
++	.release = dbox_release,
++	.unlocked_ioctl = dbox_ioctl,
++};
++
++static irqreturn_t dbox_irq_handler(int irq, void *data)
++{
++	struct jz_dbox *dbox;
++	unsigned int status;
++
++	DBOX_DEBUG("dbox: %s\n", __func__);
++	dbox = (struct jz_dbox *)data;
++
++    status = dbox_reg_read(dbox, DBOX_CTRL);
++
++
++    DBOX_DEBUG("----- %s, status= 0x%08x\n", __func__, status);
++	 /* this status doesn't do anything including trigger interrupt,
++	 * just give a hint */
++    if (status & 0x10){
++        complete(&dbox->done_dbox);
++    }
++
++    __dbox_irq_clear();
++
++    return IRQ_HANDLED;
++}
++
++static int dbox_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	struct jz_dbox *dbox;
++
++	DBOX_DEBUG("%s\n", __func__);
++	dbox = (struct jz_dbox *)kzalloc(sizeof(struct jz_dbox), GFP_KERNEL);
++	if (!dbox) {
++		dev_err(&pdev->dev, "alloc jz_dbox failed!\n");
++		return -ENOMEM;
++	}
++
++	sprintf(dbox->name, "dbox");
++
++	dbox->misc_dev.minor = MISC_DYNAMIC_MINOR;
++	dbox->misc_dev.name = dbox->name;
++	dbox->misc_dev.fops = &dbox_ops;
++	dbox->dev = &pdev->dev;
++
++	mutex_init(&dbox->mutex);
++	init_completion(&dbox->done_dbox);
++	init_completion(&dbox->done_buf);
++	complete(&dbox->done_buf);
++
++	dbox->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!dbox->res) {
++		dev_err(&pdev->dev, "failed to get dev resources: %d\n", ret);
++		ret = -EINVAL;
++		goto err_get_platform_res;
++	}
++
++	dbox->res = request_mem_region(dbox->res->start,
++			dbox->res->end - dbox->res->start + 1,
++			pdev->name);
++	if (!dbox->res) {
++		dev_err(&pdev->dev, "failed to request regs memory region");
++		ret = -EINVAL;
++		goto err_get_mem_region;
++	}
++	dbox->iomem = ioremap(dbox->res->start, resource_size(dbox->res));
++	if (!dbox->iomem) {
++		dev_err(&pdev->dev, "failed to remap regs memory region: %d\n",ret);
++		ret = -EINVAL;
++		goto err_ioremap;
++	}
++
++	dbox->irq = platform_get_irq(pdev, 0);
++	if (request_irq(dbox->irq, dbox_irq_handler, IRQF_SHARED, dbox->name, dbox)) {
++		dev_err(&pdev->dev, "request irq failed\n");
++		ret = -EINVAL;
++		goto err_req_irq;
++	}
++
++#ifndef CONFIG_FPGA_TEST
++	dbox->clk = devm_clk_get(dbox->dev, "gate_drawbox");
++	if (IS_ERR(dbox->clk)) {
++		dev_err(&pdev->dev, "dbox clk get failed!\n");
++		ret = -EINVAL;
++		goto err_get_dbox_clk;
++	}
++#endif
++
++	dev_set_drvdata(&pdev->dev, dbox);
++
++	__reset_dbox();
++    /* wait reset complete */
++    while(dbox_reg_read(dbox, DBOX_CTRL) & 0x2) {
++        udelay(10);
++    }
++
++    ret = misc_register(&dbox->misc_dev);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "register misc device failed!\n");
++		goto err_misc_register;
++	}
++
++    printk("JZ DBOX probe ok!!!!\n");
++	return 0;
++
++err_misc_register:
++#ifndef CONFIG_FPGA_TEST
++	devm_clk_put(dbox->dev, dbox->clk);
++err_get_dbox_clk:
++#endif
++	free_irq(dbox->irq, dbox);
++err_req_irq:
++	iounmap(dbox->iomem);
++err_ioremap:
++	release_mem_region(dbox->res->start, dbox->res->end - dbox->res->start + 1);
++err_get_platform_res:
++err_get_mem_region:
++	kfree(dbox);
++
++	return ret;
++}
++
++static int dbox_remove(struct platform_device *pdev)
++{
++	struct jz_dbox *dbox;
++	struct resource *res;
++	DBOX_DEBUG("%s\n", __func__);
++
++	dbox = dev_get_drvdata(&pdev->dev);
++	misc_deregister(&dbox->misc_dev);
++#ifndef CONFIG_FPGA_TEST
++	devm_clk_put(dbox->dev, dbox->clk);
++#endif
++	res = dbox->res;
++	free_irq(dbox->irq, dbox);
++	iounmap(dbox->iomem);
++	release_mem_region(res->start, res->end - res->start + 1);
++
++	if (dbox->pbuf.vaddr_alloc) {
++		kfree((void *)(dbox->pbuf.vaddr_alloc));
++		dbox->pbuf.vaddr_alloc = 0;
++	}
++	if (dbox) {
++		kfree(dbox);
++	}
++
++	return 0;
++}
++
++static const struct of_device_id ingenic_dbox_dt_match[] = {
++    { .compatible = "ingenic,x2500-drawbox", .data = NULL },
++    {},
++};
++
++static struct platform_driver jz_dbox_driver = {
++	.probe	= dbox_probe,
++	.remove = dbox_remove,
++	.driver = {
++		.name = "jz-drawbox",
++		.owner  = THIS_MODULE,
++		.of_match_table = of_match_ptr(ingenic_dbox_dt_match),
++	},
++};
++
++static int __init dboxdev_init(void)
++{
++	DBOX_DEBUG("%s\n", __func__);
++	platform_driver_register(&jz_dbox_driver);
++	return 0;
++}
++
++static void __exit dboxdev_exit(void)
++{
++	DBOX_DEBUG("%s\n", __func__);
++	platform_driver_unregister(&jz_dbox_driver);
++}
++
++module_init(dboxdev_init);
++module_exit(dboxdev_exit);
++MODULE_DESCRIPTION("JZ IPU driver");
++MODULE_AUTHOR("Ferdinand Jia <bcjia@ingenic.cn>");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/ingenic_ipu/ingenic_drawbox.h b/module_drivers/drivers/video/ingenic_ipu/ingenic_drawbox.h
+new file mode 100644
+index 000000000..99dbe3dc1
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_ipu/ingenic_drawbox.h
+@@ -0,0 +1,161 @@
++#ifndef __DBOX__H__
++#define __DBOX__H__
++
++
++
++#define DBOX_BASE	0xB30D0000
++
++#define DBOX_CTRL	    0x00
++#define DBOX_YB         0x04
++#define DBOX_CB	        0x08
++#define DBOX_STRIDE	    0x0c
++#define DBOX_IMG_WH	    0x10
++#define DBOX_COLOR_Y	0x14
++#define DBOX_COLOR_U	0x18
++#define DBOX_COLOR_V	0x1c
++#define DBOX_RAM	    0x20
++#define DBOX_TIMEOUT	0x24
++
++#define u32 unsigned int
++
++struct dbox_reg_struct {
++	char *name;
++	unsigned int addr;
++};
++
++struct dbox_buf_info {
++	unsigned int vaddr_alloc;
++	unsigned int paddr;
++	unsigned int paddr_align;
++	unsigned int size;
++};
++
++struct jz_dbox {
++
++	int irq;
++	char name[16];
++
++	struct clk *clk;
++	struct clk *ahb0_gate; /* T40 drawbox mount at AHB0*/
++	void __iomem *iomem;
++	struct device *dev;
++	struct resource *res;
++	struct miscdevice misc_dev;
++
++	struct mutex mutex;
++	struct completion done_dbox;
++	struct completion done_buf;
++	struct dbox_buf_info pbuf;
++};
++
++struct dbox_flush_cache_para
++{
++	void *addr;
++	unsigned int size;
++};
++
++struct dbox_ram
++{
++    unsigned int 		box_x;
++	unsigned int 		box_y;
++    unsigned int 		box_w;
++	unsigned int 		box_h;
++    unsigned int 		line_w;
++	unsigned int 		line_l;
++    unsigned int 		box_mode;
++	unsigned int 		color_mode;
++};
++
++struct dbox_param
++{
++    unsigned int        box_pbuf;
++	unsigned int 		img_w;
++	unsigned int 		img_h;
++
++    unsigned int        boxs_num;
++    unsigned int        is_rgba;
++    struct dbox_ram ram_para[24];  //kernel stack overflow
++};
++
++#define JZDBOX_IOC_MAGIC  'X'
++#define IOCTL_DBOX_START			_IO(JZDBOX_IOC_MAGIC, 106)
++#define IOCTL_DBOX_RES_PBUFF		_IO(JZDBOX_IOC_MAGIC, 114)
++#define IOCTL_DBOX_GET_PBUFF		_IO(JZDBOX_IOC_MAGIC, 115)
++#define IOCTL_DBOX_BUF_LOCK		    _IO(JZDBOX_IOC_MAGIC, 116)
++#define IOCTL_DBOX_BUF_UNLOCK	    _IO(JZDBOX_IOC_MAGIC, 117)
++#define IOCTL_DBOX_BUF_FLUSH_CACHE	_IO(JZDBOX_IOC_MAGIC, 118)
++#define IOCTL_DBOX_GET_DMA_PHY	_IO(JZDBOX_IOC_MAGIC, 119)
++
++/* DBOX_CTRL*/
++#define DBOX_RAM_RP        (17)
++#define DBOX_RAM_WP        (9)
++#define DBOX_TIMEOUT_MASK  (1 << 8)
++#define DBOX_TIMEOUT_IRQ   (1 << 7)
++#define DBOX_IS_BGRA       (1 << 6)
++#define DBOX_CLOCK_GATE_MASK (1 << 5)
++#define DBOX_IRQ (4)
++#define DBOX_IRQ_OPEN  (1 << DBOX_IRQ)
++#define DBOX_IRQ_MASK (1 << 3)
++#define DBOX_COLOR_MASK (1 << 2)
++#define DBOX_RESET (1 << 1)
++#define DBOX_START (1 << 0)
++
++
++/* DBOX_YB luma base register */
++#define DBOX_LUMA_BASE (0)
++
++/* DBOX_CB */
++#define DBOX_CONCENTRATION_BASE (0)
++
++/* DBOX_STRIDE */
++#define DBOX_C_STRIDE       (16)
++#define DBOX_Y_STRIDE       (0)
++
++/* DBOX_IMG_WH */
++#define DBOX_WIDTH       (0)
++#define DBOX_HEIGHT      (16)
++
++/* DBOX_COLOR_Y */
++#define DBOX_COLOR_ADDR_Y            (0)
++
++/* DBOX_COLOR_U */
++#define DBOX_COLOR_ADDR_U       (0)
++
++/* DBOX_COLOR_V */
++#define DBOX_COLOR_ADDR_V      (0)
++
++/* DBOX_RAM */
++#define DBOX_BOX_LINE_WIDTH     (55)
++#define DBOX_BOX_LINE_LENGTH    (52)
++#define DBOX_BOX_MODE      (50)
++#define DBOX_MODE_RECT     (0 << DBOX_BOX_MODE)
++#define DBOX_MODE_HRECT    (1 << DBOX_BOX_MODE)
++#define DBOX_MODE_HLINE    (2 << DBOX_BOX_MODE)
++#define DBOX_MODE_VLINE    (3 << DBOX_BOX_MODE)
++#define DBOX_COLOR_MODE    (48)
++#define DBOX_BOX_HEIGHT    (36)
++#define DBOX_BOX_WIDTH     (24)
++#define DBOX_BOX_Y         (12)
++#define DBOX_BOX_X         (0)
++
++//extern void dboxdev_init(void);
++//extern void dboxdev_exit(void);
++
++static inline unsigned int dbox_reg_read(struct jz_dbox *jzdbox, int offset)
++{
++	return readl(jzdbox->iomem + offset);
++}
++
++static inline void dbox_reg_write(struct jz_dbox *jzdbox, int offset, unsigned int val)
++{
++	writel(val, jzdbox->iomem + offset);
++}
++
++#define __dbox_mask_irq()		reg_bit_clr(dbox, DBOX_CTRL, DBOX_IRQ_MASK)
++#define __dbox_irq_clear(value)		reg_bit_clr(dbox, DBOX_CTRL, DBOX_IRQ_OPEN)
++
++#define __start_dbox()			reg_bit_set(dbox, DBOX_CTRL, DBOX_START)
++#define __reset_dbox()			reg_bit_set(dbox, DBOX_CTRL, DBOX_RESET)
++#define __uv_mask_dbox()			reg_bit_set(dbox, DBOX_CTRL, DBOX_COLOR_MASK)
++
++#endif
+diff --git a/module_drivers/drivers/video/ingenic_ipu/ingenic_ipu_v13.c b/module_drivers/drivers/video/ingenic_ipu/ingenic_ipu_v13.c
+new file mode 100644
+index 000000000..7151c70fa
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_ipu/ingenic_ipu_v13.c
+@@ -0,0 +1,1206 @@
++/*
++ * Copyright (c) 2015 Ingenic Semiconductor Co., Ltd.
++ *              http://www.ingenic.com/
++ *
++ * Input file for Ingenic IPU driver
++ *
++ * This  program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++#include <linux/poll.h>
++#include <linux/wait.h>
++#include <linux/fs.h>
++#include <linux/irq.h>
++#include <linux/mm.h>
++#include <linux/fb.h>
++#include <linux/ctype.h>
++#include <linux/dma-mapping.h>
++#include <linux/interrupt.h>
++#include <linux/of_reserved_mem.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/memory.h>
++#include <linux/suspend.h>
++#include <linux/miscdevice.h>
++#include <linux/proc_fs.h>
++#include <linux/delay.h>
++#include <linux/completion.h>
++#include <linux/time.h>
++#include <linux/version.h>
++#include <linux/dma-map-ops.h>
++#include "ingenic_regs_v13.h"
++#include "ingenic_ipu_v13.h"
++#include "ingenic_drawbox.h"
++#include "ipu_dmabuf.h"
++// #define DEBUG
++#ifdef	DEBUG
++static int debug_ipu = 1;
++
++#define IPU_DEBUG(format, ...) { if (debug_ipu) printk(format, ## __VA_ARGS__);}
++#else
++#define IPU_DEBUG(format, ...) do{ } while(0)
++#endif
++
++#define IPU_BUF_SIZE (1024 * 1024 * 2)
++
++struct ipu_reg_struct jz_ipu_regs_name[] = {
++	{"IPU_FM_CTRL", IPU_FM_CTRL},
++	{"IPU_STATUS", IPU_STATUS},
++	{"IPU_D_FMT", IPU_D_FMT},
++	{"IPU_Y_ADDR", IPU_Y_ADDR},
++	{"IPU_U_ADDR", IPU_U_ADDR},
++	{"IPU_IN_FM_GS", IPU_IN_FM_GS},
++	{"IPU_Y_STRIDE", IPU_Y_STRIDE},
++	{"IPU_UV_STRIDE", IPU_UV_STRIDE},
++	{"IPU_OUT_ADDR", IPU_OUT_ADDR},
++	{"IPU_OUT_STRIDE", IPU_OUT_STRIDE},
++	{"IPU_OUT_V_ADDR", IPU_OUT_V_ADDR},
++	{"IPU_OUT_V_STRIDE", IPU_OUT_V_STRIDE},
++	{"IPU_REG_CTRL", IPU_REG_CTRL},
++	{"IPU_TRIGGER", IPU_TRIGGER},
++	{"IPU_GLB_CTRL", IPU_GLB_CTRL},
++
++	{"IPU_NV_OUT_ADDR", IPU_NV_OUT_ADDR},
++	{"IPU_NV_OUT_STRIDE", IPU_NV_OUT_STRIDE},
++	{"IPU_OSD_IN_CH0_Y_ADDR", IPU_OSD_IN_CH0_Y_ADDR},
++	{"IPU_OSD_IN_CH0_Y_STRIDE", IPU_OSD_IN_CH0_Y_STRIDE},
++	{"IPU_OSD_IN_CH0_UV_ADDR", IPU_OSD_IN_CH0_UV_ADDR},
++	{"IPU_OSD_IN_CH0_UV_STRIDE", IPU_OSD_IN_CH0_UV_STRIDE},
++	{"IPU_OSD_IN_CH1_Y_ADDR", IPU_OSD_IN_CH1_Y_ADDR},
++	{"IPU_OSD_IN_CH1_Y_STRIDE", IPU_OSD_IN_CH1_Y_STRIDE},
++	{"IPU_OSD_IN_CH1_UV_ADDR", IPU_OSD_IN_CH1_UV_ADDR},
++	{"IPU_OSD_IN_CH1_UV_STRIDE", IPU_OSD_IN_CH1_UV_STRIDE},
++	{"IPU_OSD_IN_CH2_Y_ADDR", IPU_OSD_IN_CH2_Y_ADDR},
++	{"IPU_OSD_IN_CH2_Y_STRIDE", IPU_OSD_IN_CH2_Y_STRIDE},
++	{"IPU_OSD_IN_CH2_UV_ADDR", IPU_OSD_IN_CH2_UV_ADDR},
++	{"IPU_OSD_IN_CH2_UV_STRIDE", IPU_OSD_IN_CH2_UV_STRIDE},
++	{"IPU_OSD_IN_CH3_Y_ADDR", IPU_OSD_IN_CH3_Y_ADDR},
++	{"IPU_OSD_IN_CH3_Y_STRIDE", IPU_OSD_IN_CH3_Y_STRIDE},
++	{"IPU_OSD_IN_CH3_UV_ADDR", IPU_OSD_IN_CH3_UV_ADDR},
++	{"IPU_OSD_IN_CH3_UV_STRIDE", IPU_OSD_IN_CH3_UV_STRIDE},
++	{"IPU_OSD_CH0_GS", IPU_OSD_CH0_GS},
++	{"IPU_OSD_CH1_GS", IPU_OSD_CH1_GS},
++	{"IPU_OSD_CH2_GS", IPU_OSD_CH2_GS},
++	{"IPU_OSD_CH3_GS", IPU_OSD_CH3_GS},
++	{"IPU_OSD_CH0_POS", IPU_OSD_CH0_POS},
++	{"IPU_OSD_CH1_POS", IPU_OSD_CH1_POS},
++	{"IPU_OSD_CH2_POS", IPU_OSD_CH2_POS},
++	{"IPU_OSD_CH3_POS", IPU_OSD_CH3_POS},
++	{"IPU_OSD_CH0_PARA", IPU_OSD_CH0_PARA},
++	{"IPU_OSD_CH1_PARA", IPU_OSD_CH1_PARA},
++	{"IPU_OSD_CH2_PARA", IPU_OSD_CH2_PARA},
++	{"IPU_OSD_CH3_PARA", IPU_OSD_CH3_PARA},
++	{"IPU_OSD_CH_BK_PARA", IPU_OSD_CH_BK_PARA},
++	{"IPU_OSD_CH0_BAK_ARGB", IPU_OSD_CH0_BAK_ARGB},
++	{"IPU_OSD_CH1_BAK_ARGB", IPU_OSD_CH1_BAK_ARGB},
++	{"IPU_OSD_CH2_BAK_ARGB", IPU_OSD_CH2_BAK_ARGB},
++	{"IPU_OSD_CH3_BAK_ARGB", IPU_OSD_CH3_BAK_ARGB},
++	{"IPU_OSD_CH_B_BAK_ARGB", IPU_OSD_CH_B_BAK_ARGB},
++	{"IPU_CH0_CSC_C0_COEF", IPU_CH0_CSC_C0_COEF},
++	{"IPU_CH0_CSC_C1_COEF", IPU_CH0_CSC_C1_COEF},
++	{"IPU_CH0_CSC_C2_COEF", IPU_CH0_CSC_C2_COEF},
++	{"IPU_CH0_CSC_C3_COEF", IPU_CH0_CSC_C3_COEF},
++	{"IPU_CH0_CSC_C4_COEF", IPU_CH0_CSC_C4_COEF},
++	{"IPU_CH0_CSC_OFSET_PARA", IPU_CH0_CSC_OFSET_PARA},
++	{"IPU_CH1_CSC_C0_COEF", IPU_CH1_CSC_C0_COEF},
++	{"IPU_CH1_CSC_C1_COEF", IPU_CH1_CSC_C1_COEF},
++	{"IPU_CH1_CSC_C2_COEF", IPU_CH1_CSC_C2_COEF},
++	{"IPU_CH1_CSC_C3_COEF", IPU_CH1_CSC_C3_COEF},
++	{"IPU_CH1_CSC_C4_COEF", IPU_CH1_CSC_C4_COEF},
++	{"IPU_CH1_CSC_OFSET_PARA", IPU_CH1_CSC_OFSET_PARA},
++	{"IPU_CH2_CSC_C0_COEF", IPU_CH2_CSC_C0_COEF},
++	{"IPU_CH2_CSC_C1_COEF", IPU_CH2_CSC_C1_COEF},
++	{"IPU_CH2_CSC_C2_COEF", IPU_CH2_CSC_C2_COEF},
++	{"IPU_CH2_CSC_C3_COEF", IPU_CH2_CSC_C3_COEF},
++	{"IPU_CH2_CSC_C4_COEF", IPU_CH2_CSC_C4_COEF},
++	{"IPU_CH2_CSC_OFSET_PARA", IPU_CH2_CSC_OFSET_PARA},
++	{"IPU_CH3_CSC_C0_COEF", IPU_CH3_CSC_C0_COEF},
++	{"IPU_CH3_CSC_C1_COEF", IPU_CH3_CSC_C1_COEF},
++	{"IPU_CH3_CSC_C2_COEF", IPU_CH3_CSC_C2_COEF},
++	{"IPU_CH3_CSC_C3_COEF", IPU_CH3_CSC_C3_COEF},
++	{"IPU_CH3_CSC_C4_COEF", IPU_CH3_CSC_C4_COEF},
++	{"IPU_CH3_CSC_OFSET_PARA", IPU_CH3_CSC_OFSET_PARA},
++	{"IPU_RD_ARB_CTL", IPU_RD_ARB_CTL},
++	{"IPU_CLK_NUM_ONE_FRA", IPU_CLK_NUM_ONE_FRA},
++	{"IPU_OSD_LAY_PADDING_ARGB", IPU_OSD_LAY_PADDING_ARGB},
++	{"IPU_TEST_1B4", IPU_TEST_1B4},
++};
++
++
++static void reg_bit_set(struct jz_ipu *ipu, int offset, unsigned int bit)
++{
++	unsigned int reg = 0;
++	reg = ipu_reg_read(ipu, offset);
++	reg |= bit;
++	ipu_reg_write(ipu, offset, reg);
++}
++
++static void reg_bit_clr(struct jz_ipu *ipu, int offset, unsigned int bit)
++{
++	unsigned int reg = 0;
++	reg= ipu_reg_read(ipu, offset);
++	reg &= ~(bit);
++	ipu_reg_write(ipu, offset, reg);
++}
++
++static unsigned int _hal_to_ipu_infmt(int hal_fmt, int *isrgb)
++{
++	unsigned int ipu_fmt = IN_FMT_YUV420;
++	int rgb = 0;
++
++	switch (hal_fmt) {
++		case HAL_PIXEL_FORMAT_YCbCr_422_SP:
++			ipu_fmt = IN_FMT_YUV422;
++			rgb = 0;
++			break;
++		case HAL_PIXEL_FORMAT_YCbCr_420_SP:
++			ipu_fmt = IN_FMT_YUV420;
++			rgb = 0;
++			break;
++		case HAL_PIXEL_FORMAT_YCbCr_422_P:
++			ipu_fmt = IN_FMT_YUV422;
++			rgb = 0;
++			break;
++		case HAL_PIXEL_FORMAT_YCbCr_422_I:
++			ipu_fmt = IN_FMT_YUV422;
++			rgb = 0;
++			break;
++		case HAL_PIXEL_FORMAT_YCbCr_420_I:
++			ipu_fmt = IN_FMT_YUV420;
++			rgb = 0;
++			break;
++		case HAL_PIXEL_FORMAT_YCbCr_420_B:
++		case HAL_PIXEL_FORMAT_JZ_YUV_420_B:
++			ipu_fmt = IN_FMT_YUV420_B;
++			rgb = 0;
++			break;
++		case HAL_PIXEL_FORMAT_RGBA_5551: //background is not support 5551 format
++		case HAL_PIXEL_FORMAT_BGRA_5551:
++			ipu_fmt = IN_FMT_RGB_555;
++			rgb = 1;
++			break;
++		case HAL_PIXEL_FORMAT_RGBA_8888:
++		case HAL_PIXEL_FORMAT_RGBX_8888:
++		case HAL_PIXEL_FORMAT_RGB_888:
++		case HAL_PIXEL_FORMAT_BGRA_8888:
++		case HAL_PIXEL_FORMAT_ARGB_8888:
++		case HAL_PIXEL_FORMAT_ABGR_8888:
++		case HAL_PIXEL_FORMAT_BGRX_8888:
++			ipu_fmt = IN_FMT_RGB_888;
++			rgb = 1;
++			break;
++		case HAL_PIXEL_FORMAT_RGB_565: //background is not support 565 format
++			ipu_fmt = IN_FMT_RGB_565;
++			rgb = 1;
++			break;
++		case HAL_PIXEL_FORMAT_NV12:
++		case HAL_PIXEL_FORMAT_NV21:
++		case HAL_PIXEL_FORMAT_YCbCr_420_P:
++		case HAL_PIXEL_FORMAT_JZ_YUV_420_P:
++		default:
++			ipu_fmt = IN_FMT_YUV420;
++			rgb = 0;
++			break;
++	}
++	if (isrgb != 0)
++		*isrgb = rgb;
++	return ipu_fmt;
++}
++
++static unsigned int _hal_to_ipu_outfmt(int hal_fmt)
++{
++	unsigned int ipu_fmt = OUT_FMT_RGB888;
++
++	switch (hal_fmt) {
++		case HAL_PIXEL_FORMAT_ARGB_8888:
++		case HAL_PIXEL_FORMAT_ABGR_8888:
++		case HAL_PIXEL_FORMAT_RGBA_8888:
++		case HAL_PIXEL_FORMAT_RGBX_8888:
++		case HAL_PIXEL_FORMAT_RGB_888:
++		case HAL_PIXEL_FORMAT_BGRA_8888:
++		case HAL_PIXEL_FORMAT_BGRX_8888:
++			ipu_fmt = OUT_FMT_RGB888;
++			break;
++		case HAL_PIXEL_FORMAT_RGB_565:  //It is not support
++			ipu_fmt = OUT_FMT_RGB565;
++			break;
++		case HAL_PIXEL_FORMAT_RGBA_5551:  //It is not support
++		case HAL_PIXEL_FORMAT_BGRA_5551:
++			ipu_fmt = OUT_FMT_RGB555;
++			break;
++		case HAL_PIXEL_FORMAT_YCbCr_422_I:
++			ipu_fmt = OUT_FMT_YUV422;
++			break;
++		case HAL_PIXEL_FORMAT_NV12:
++			ipu_fmt = OUT_FMT_NV12;
++			break;
++        case HAL_PIXEL_FORMAT_HSV:/*Add HSV*/
++            ipu_fmt = OUT_FMT_HSV;
++            break;
++		case HAL_PIXEL_FORMAT_NV21:
++			ipu_fmt = OUT_FMT_NV21;
++			break;
++	}
++	return ipu_fmt;
++}
++
++#define IPU_OSD_CH_BK_PARA_GLO_A(p, x) ((p)=(((p)&(~(0xff<<3)))|((x&0xff)<<3)))
++#define IPU_OSD_CH_BK_PARA_ALPHA_SEL(p, x) ((p)=(((p)&(~(0x3<<1)))|((x&0x3)<<1)))
++static int _ipu_set_bg_route(struct jz_ipu *ipu, struct ipu_param *ipu_param)
++{
++	int ret = 0;
++	unsigned int reg_val = 0;
++	unsigned int bgrgb = 0;
++	unsigned int srcw = 0;
++	unsigned int srch = 0;
++	unsigned int outw = 0;
++	unsigned int outh = 0;
++	unsigned int infmt = 0;
++	unsigned int outfmt = 0;
++
++	unsigned int outwstride = 0;
++
++	unsigned int infmt_bits = 0;
++	unsigned int outfmt_bits = 0;
++	unsigned int outrgb_bits = 0;
++
++	struct ipu_param *ip = ipu_param;
++
++	srcw = ip->bg_w;
++	srch = ip->bg_h;
++	outw = ip->bg_w;
++	outh = ip->bg_h;
++
++	IPU_DEBUG("ipu: %s, bgrgb = %d, srcw = %d, srch = %d, outw = %d, outh = %d \n",
++			__func__, bgrgb, srcw, srch, outw, outh);
++	infmt  = _hal_to_ipu_infmt(ip->bg_fmt, &bgrgb);
++	outfmt = _hal_to_ipu_outfmt(ip->out_fmt);
++	switch (outfmt) {
++		case OUT_FMT_RGB888:
++			outwstride = outw << 2;
++			break;
++		case OUT_FMT_RGB555:	//not used
++			outwstride = outw << 1;
++			break;
++		case OUT_FMT_RGB565:    //not used
++			outwstride = outw << 1;
++			break;
++		default:
++			outwstride = outw;
++			break;
++	}
++	ipu_reg_write(ipu, IPU_IN_FM_GS, (IN_FM_W(srcw) | IN_FM_H(srch)));
++
++   if (ip->cmd & IPU_CMD_OSD)
++    {
++	    ipu_reg_write(ipu, IPU_OSD_CH_B_BAK_ARGB, 0xffaa7733);
++    }
++
++	switch (ip->out_fmt) {
++		case HAL_PIXEL_FORMAT_RGBX_8888:
++			outrgb_bits = RGB_OUT_OFT_BGR;
++			break;
++		case HAL_PIXEL_FORMAT_RGB_888:
++		case HAL_PIXEL_FORMAT_RGB_565:
++		case HAL_PIXEL_FORMAT_BGRA_8888:
++		case HAL_PIXEL_FORMAT_BGRX_8888:
++		case HAL_PIXEL_FORMAT_RGBA_5551:
++		default:
++			outrgb_bits = RGB_OUT_OFT_RGB;    //outrgb_bits set 22st bit,this bit in IPU_D_FMT was not used
++			break;
++	}
++	infmt_bits = infmt;
++	outfmt_bits = outfmt;     //outfmt_bits set 19st bit,IPU_D_FMT was not used
++	if (infmt == IN_FMT_YUV422) {
++		infmt_bits |= IN_OFT_Y1UY0V;
++	}
++	if (outfmt == OUT_FMT_YUV422) {
++		outfmt_bits |= YUV_PKG_OUT_OFT_Y1UY0V;
++	}
++
++    /****** Add HSV *******/
++    if ((outfmt == OUT_FMT_HSV) || (ip->out_fmt == OUT_FMT_HSV)) {/* out format */
++        reg_val = 0x4;
++    } else if ((outfmt == OUT_FMT_RGB888) || (ip->out_fmt == OUT_FMT_RGB888)) {
++        reg_val = 0x40;
++    } else if ((outfmt == OUT_FMT_NV21) || (ip->out_fmt == OUT_FMT_NV21)) {
++        reg_val = 0x3;
++    }
++	ipu_reg_write(ipu, IPU_D_FMT, reg_val);
++
++    if (ip->cmd & IPU_CMD_OSD) {
++	    if (ip->bg_fmt == HAL_PIXEL_FORMAT_NV12) {
++		    reg_val = 0x2;
++	    } else if (ip->bg_fmt == HAL_PIXEL_FORMAT_NV21) {
++		    reg_val = 0x3;
++	    } else {
++		    reg_val = infmt_bits | outfmt_bits | outrgb_bits;
++	    }
++	    ipu_reg_write(ipu, IPU_D_FMT, reg_val);
++    }
++	/*
++	* IPU_D_FMT just use 0~6 bit, if IPU_OSD_CH_BK_PARA set CH_BK_PIC_TYPE ,
++	* and the IPU was use to do OSD, this register OUT_FMT bits was valueless,
++	* the OUT_FMT are automatically set equal to CH_BK_PIC_TYPE value;
++	* and if IPU was use to do conversion format, the OUT_FMT bits must be set to the
++	* format that you want to conversion.
++	*/
++	if (infmt == IN_FMT_YUV420_B) {
++		__enable_blk_mode();
++	}
++
++	if ((ip->out_fmt == HAL_PIXEL_FORMAT_NV12) || (ip->out_fmt == HAL_PIXEL_FORMAT_NV21)) {/*Add NV12 or NV21*/
++		ipu_reg_write(ipu, IPU_OUT_STRIDE,	srcw);
++        ipu_reg_write(ipu, IPU_NV_OUT_STRIDE, srcw);
++	} else if (ip->out_fmt == HAL_PIXEL_FORMAT_HSV) {/* Add HSV */
++        ipu_reg_write(ipu, IPU_OUT_STRIDE, srcw);
++        ipu_reg_write(ipu, IPU_NV_OUT_STRIDE, srcw*2);
++        ipu_reg_write(ipu, IPU_OUT_V_STRIDE, srcw);
++    } else if (ip->out_fmt == HAL_PIXEL_FORMAT_BGRA_8888 || ip->out_fmt == HAL_PIXEL_FORMAT_RGBA_8888) {/* Add ARGB */
++        ipu_reg_write(ipu, IPU_OUT_STRIDE, srcw<<2);
++    } else {
++		ipu_reg_write(ipu, IPU_OUT_STRIDE, outwstride);
++	}
++
++	if (infmt == IN_FMT_YUV420_B) {
++		ipu_reg_write(ipu, IPU_Y_STRIDE, srcw * 16);
++	} else if (ipu_reg_read(ipu, IPU_FM_CTRL) & (1 << 10)) {
++		ipu_reg_write(ipu, IPU_Y_STRIDE, srcw * 2);
++	} else {
++		ipu_reg_write(ipu, IPU_Y_STRIDE, srcw);
++	}
++	switch (infmt) {
++		case IN_FMT_YUV420:
++			reg_val = U_STRIDE(srcw) | V_STRIDE(srcw);
++			ipu_reg_write(ipu, IPU_UV_STRIDE, reg_val);
++			break;
++		case IN_FMT_YUV422:
++			reg_val = U_STRIDE(srcw / 2) | V_STRIDE(srcw / 2);
++			ipu_reg_write(ipu, IPU_UV_STRIDE, reg_val);
++			break;
++		case IN_FMT_YUV420_B:
++			reg_val = U_STRIDE(8 * srcw) | V_STRIDE(8 * srcw);
++			ipu_reg_write(ipu, IPU_UV_STRIDE, reg_val);
++			break;
++		case IN_FMT_YUV444:
++			reg_val = U_STRIDE(srcw) | V_STRIDE(srcw);
++			ipu_reg_write(ipu, IPU_UV_STRIDE, reg_val);
++			break;
++		case IN_FMT_YUV411:
++			reg_val = U_STRIDE(srcw / 4) | V_STRIDE(srcw / 4);
++			ipu_reg_write(ipu, IPU_UV_STRIDE, reg_val);
++			break;
++		default:
++			dev_err(ipu->dev, "Error: 222 Input data format isn't support\n");
++	}
++
++	reg_val = 0;
++	/*select bk ch input fmt*/
++	if (bgrgb) {
++		switch(ip->bg_fmt) {
++			case HAL_PIXEL_FORMAT_ARGB_8888:
++				reg_val |= CH_BK_ARGB_TYPE_ARGB;
++				break;
++			case HAL_PIXEL_FORMAT_ABGR_8888:
++				reg_val |= CH_BK_ARGB_TYPE_ABGR;
++				break;
++			case HAL_PIXEL_FORMAT_RGBA_8888:
++				reg_val |= CH_BK_ARGB_TYPE_RGBA;
++				break;
++			case HAL_PIXEL_FORMAT_BGRA_8888:
++				reg_val |= CH_BK_ARGB_TYPE_BGRA;
++				break;
++//			case HAL_PIXEL_FORMAT_BGRA_5551:   //bg_fmt is not support 5551
++			default:
++				reg_val |= CH_BK_ARGB_TYPE_BGRA;
++				break;
++		}
++		reg_val |= CH_BK_PIC_TYPE_ARGB;
++//		reg_val |= CH_BK_ARGB_TYPE_BGRA;	//Maybe it's have an other choice, but here I fix it.You can change it.
++	} else {
++		switch(ip->bg_fmt) {
++			case HAL_PIXEL_FORMAT_NV12:
++				reg_val |= CH_BK_PIC_TYPE_NV12;
++				break;
++			case HAL_PIXEL_FORMAT_NV21:
++				reg_val |= CH_BK_PIC_TYPE_NV21;
++				break;
++			default:
++				reg_val |= CH_BK_PIC_TYPE_NV12;
++				break;
++		}
++	}
++	if (ip->cmd & IPU_CMD_OSD) {
++		IPU_DEBUG("ipu: Attention!! Have some OSD CH will ENABLE!!!!\n");
++		reg_val |= CH_BK_PREM;
++	}
++
++	IPU_DEBUG("ipu: enable background ch!!! \n");
++	reg_val |= CH_BK_EN;
++
++	ipu_reg_write(ipu, IPU_OSD_CH_BK_PARA, reg_val);/* input bk format */
++	IPU_DEBUG("ipu: Background reg val = 0x%08x\n", ipu_reg_read(ipu, IPU_OSD_CH_BK_PARA));
++
++	return ret;
++}
++
++static int _ipu_osd_isrgb(unsigned int fmt)
++{
++	int isrgb = 0;
++	switch(fmt) {
++		case HAL_PIXEL_FORMAT_ARGB_8888:
++		case HAL_PIXEL_FORMAT_ABGR_8888:
++		case HAL_PIXEL_FORMAT_RGBA_8888:
++		case HAL_PIXEL_FORMAT_RGBX_8888:
++		case HAL_PIXEL_FORMAT_BGRA_8888:
++		case HAL_PIXEL_FORMAT_BGRX_8888:
++			isrgb = 1;
++			break;
++		case HAL_PIXEL_FORMAT_NV12:
++			isrgb = 0;
++			break;
++        case HAL_PIXEL_FORMAT_HSV:/*Add HSV*/
++            isrgb = 0;
++            break;
++		case HAL_PIXEL_FORMAT_NV21:
++			isrgb = 0;
++			break;
++		case HAL_PIXEL_FORMAT_BGRA_5551:
++		case HAL_PIXEL_FORMAT_RGBA_5551:
++			isrgb = 2;
++			break;
++		default:
++			isrgb = -1;
++			break;
++	}
++	return isrgb;
++}
++
++static int _ipu_set_osd_chx_route(struct jz_ipu *ipu, struct ipu_param *ip, int ch)
++{
++	unsigned int isrgb = 0;
++	unsigned int posx = 0;
++	unsigned int posy = 0;
++	unsigned int srcw = 0;
++	unsigned int srch = 0;
++	unsigned int para = 0;
++	unsigned int fmt = 0;
++	unsigned int bak_argb = 0;
++	unsigned int src_stride = 0;
++
++	if ((ch < 0) || (ch > 3)) {
++		printk("ipu: osd channel num err ch = %d\n", ch);
++		return -1;
++	}
++	switch(ch) {
++		case 0:
++			fmt	= ip->osd_ch0_fmt;
++			posx  = ip->osd_ch0_pos_x;
++			posy  = ip->osd_ch0_pos_y;
++            srcw  = ((ip->bg_w-1) > (ip->osd_ch0_pos_x + ip->osd_ch0_src_w)) ? (ip->osd_ch0_src_w) : (ip->bg_w-1-ip->osd_ch0_pos_x);
++            srch  = ((ip->bg_h-1) > (ip->osd_ch0_pos_y + ip->osd_ch0_src_h)) ? (ip->osd_ch0_src_h) : (ip->bg_h-1-ip->osd_ch0_pos_y);
++			para  = ip->osd_ch0_para;
++			bak_argb  = ip->osd_ch0_bak_argb;
++            src_stride = ip->osd_ch0_src_w;
++			break;
++		case 1:
++			fmt	= ip->osd_ch1_fmt;
++			posx  = ip->osd_ch1_pos_x;
++			posy  = ip->osd_ch1_pos_y;
++            srcw  = ((ip->bg_w-1) > (ip->osd_ch1_pos_x + ip->osd_ch1_src_w)) ? (ip->osd_ch1_src_w) : (ip->bg_w-1-ip->osd_ch1_pos_x);
++            srch  = ((ip->bg_h-1) > (ip->osd_ch1_pos_y + ip->osd_ch1_src_h)) ? (ip->osd_ch1_src_h) : (ip->bg_h-1-ip->osd_ch1_pos_y);
++			para  = ip->osd_ch1_para;
++			bak_argb  = ip->osd_ch1_bak_argb;
++            src_stride = ip->osd_ch1_src_w;
++			break;
++		case 2:
++			fmt	= ip->osd_ch2_fmt;
++			posx  = ip->osd_ch2_pos_x;
++			posy  = ip->osd_ch2_pos_y;
++            srcw  = ((ip->bg_w-1) > (ip->osd_ch2_pos_x + ip->osd_ch2_src_w)) ? (ip->osd_ch2_src_w) : (ip->bg_w-1-ip->osd_ch2_pos_x);
++            srch  = ((ip->bg_h-1) > (ip->osd_ch2_pos_y + ip->osd_ch2_src_h)) ? (ip->osd_ch2_src_h) : (ip->bg_h-1-ip->osd_ch2_pos_y);
++			para  = ip->osd_ch2_para;
++			bak_argb  = ip->osd_ch2_bak_argb;
++            src_stride = ip->osd_ch2_src_w;
++			break;
++		case 3:
++			fmt	= ip->osd_ch3_fmt;
++			posx  = ip->osd_ch3_pos_x;
++			posy  = ip->osd_ch3_pos_y;
++            srcw  = ((ip->bg_w-1) > (ip->osd_ch3_pos_x + ip->osd_ch3_src_w)) ? (ip->osd_ch3_src_w) : (ip->bg_w-1-ip->osd_ch3_pos_x);
++            srch  = ((ip->bg_h-1) > (ip->osd_ch3_pos_y + ip->osd_ch3_src_h)) ? (ip->osd_ch3_src_h) : (ip->bg_h-1-ip->osd_ch3_pos_y);
++			para  = ip->osd_ch3_para;
++			bak_argb  = ip->osd_ch3_bak_argb;
++            src_stride = ip->osd_ch3_src_w;
++			break;
++		default :
++			printk("ipu: osd channel num err ch = %d\n", ch);
++			return -1;
++			break;
++	}
++
++	isrgb = _ipu_osd_isrgb(fmt);
++	if (isrgb < 0) {
++		printk("ipu: osd fmt err fmt = %d\n", fmt);
++		return -1;
++	}
++	IPU_DEBUG("ipu: ch = %d, isrgb=%d, posx=%d, posy=%d, srcw=%d, srch=%d, para=%d src_stride= %d\n",
++			ch, isrgb, posx, posy, srcw, srch, para, src_stride);
++	if (isrgb == 1) {
++		ipu_reg_write(ipu, IPU_OSD_IN_CH0_Y_STRIDE+0x10*ch, src_stride*4);
++	} else if (isrgb == 2){        //The format is RGBA5551
++		ipu_reg_write(ipu, IPU_OSD_IN_CH0_Y_STRIDE+0x10*ch, src_stride*2);
++	} else {
++		ipu_reg_write(ipu, IPU_OSD_IN_CH0_Y_STRIDE+0x10*ch, src_stride);
++		ipu_reg_write(ipu, IPU_OSD_IN_CH0_UV_STRIDE+0x10*ch, src_stride);
++	}
++
++    if((srcw > 0) && (srch > 0)) {
++		if (isrgb == 1)
++			ipu_reg_write(ipu, IPU_OSD_CH0_GS+4*ch, (srcw << 16 << 2) | (srch << 0));
++		else if (isrgb == 2)       //The format is RGBA1555
++			ipu_reg_write(ipu, IPU_OSD_CH0_GS+4*ch, (srcw << 16 << 1) | (srch << 0));
++		else
++			ipu_reg_write(ipu, IPU_OSD_CH0_GS+4*ch, (srcw << 16) | (srch << 0));
++	}
++	else
++		ipu_reg_write(ipu, IPU_OSD_CH0_GS+4*ch, (100 << 16) | (100 << 0));
++
++	ipu_reg_write(ipu, IPU_OSD_CH0_POS+4*ch, (posx << 16) | (posy << 0));
++
++	if (isrgb > 0) {
++		ipu_reg_write(ipu, IPU_CH0_CSC_C0_COEF+0x18*ch, (0x133 << 0) | (0x25A << 20));
++		ipu_reg_write(ipu, IPU_CH0_CSC_C1_COEF+0x18*ch, (0x75 << 0) | (0x97 << 20));
++		ipu_reg_write(ipu, IPU_CH0_CSC_C2_COEF+0x18*ch, (0x128 << 0) | (0x1BF << 20));
++		ipu_reg_write(ipu, IPU_CH0_CSC_C3_COEF+0x18*ch, (0x276 << 0) | (0x210 << 20));
++		ipu_reg_write(ipu, IPU_CH0_CSC_C4_COEF+0x18*ch, 0x67 );
++		ipu_reg_write(ipu, IPU_CH0_CSC_OFSET_PARA+0x18*ch, (0x10 << 0) | (0x80 << 16));
++	} else {
++		ipu_reg_write(ipu, IPU_CH0_CSC_C0_COEF+0x18*ch, (0x400 << 0) | (0 << 20));
++		ipu_reg_write(ipu, IPU_CH0_CSC_C1_COEF+0x18*ch, (0x490 << 0) | (0x400 << 20));
++		ipu_reg_write(ipu, IPU_CH0_CSC_C2_COEF+0x18*ch, (0x190 << 0) | (0x252 << 20));
++		ipu_reg_write(ipu, IPU_CH0_CSC_C3_COEF+0x18*ch, (0x400 << 0) | (0x81f << 20));
++		ipu_reg_write(ipu, IPU_CH0_CSC_C4_COEF+0x18*ch, 0 );
++		ipu_reg_write(ipu, IPU_CH0_CSC_OFSET_PARA+0x18*ch, (0x10 << 0) | (0x80 << 16));
++	}
++	ipu_reg_write(ipu, IPU_OSD_CH0_BAK_ARGB+4*ch, bak_argb);
++	if (para > 0)
++		ipu_reg_write(ipu, IPU_OSD_CH0_PARA+4*ch, para);
++	else
++		ipu_reg_write(ipu, IPU_OSD_CH0_PARA+4*ch, (0x1 | (0x2 << 11) | (0x01 << 1) | (0x32 << 3) | (0 << 19) | (0 << 18)));
++
++    return 0;
++}
++
++static int _ipu_set_bg_buffer(struct jz_ipu *ipu, struct ipu_param *ipu_param)
++{
++	unsigned int bg_y_pbuf = 0;
++	unsigned int bg_u_pbuf = 0;
++	unsigned int bg_v_pbuf = 0;
++    unsigned int out_y_pbuf = 0;
++    unsigned int out_uv_pbuf = 0;
++    unsigned int out_v_pbuf = 0;
++    unsigned int out_nv21_y = 0;
++    unsigned int out_nv21_uv = 0;
++
++	struct ipu_param *ip = ipu_param;
++
++	IPU_DEBUG("ipu: %s:%d \n", __func__, __LINE__);
++	if (ipu == NULL) {
++		dev_err(ipu->dev, "ipu is NULL\n");
++		return -1;
++	}
++
++    /* nv12 */
++	bg_y_pbuf = ((unsigned int)ip->bg_buf_p);
++	bg_u_pbuf = ((unsigned int)ip->bg_buf_p) + ip->bg_w*ip->bg_h;
++	bg_v_pbuf = bg_u_pbuf;
++
++    if(ip->cmd & IPU_CMD_CSC) {
++        /* OUT HSV */
++        out_y_pbuf = ((unsigned int)ip->osd_ch0_buf_p) + (ip->bg_w*ip->bg_h)*2;
++        out_uv_pbuf = ((unsigned int)ip->osd_ch0_buf_p);
++        out_v_pbuf = ((unsigned int)ip->osd_ch0_buf_p) + (ip->bg_w*ip->bg_h)*3;
++
++        /* OUT NV21 */
++        out_nv21_y = ((unsigned int)ip->osd_ch0_buf_p);
++        out_nv21_uv = ((unsigned int)ip->osd_ch0_buf_p) + (ip->bg_w*ip->bg_h);
++    }
++
++	IPU_DEBUG("ipu: bg_y_pbuf = 0x%08x, bg_u_pbuf = 0x%08x, bg_v_pbuf = 0x%08x\n", bg_y_pbuf, bg_u_pbuf, bg_v_pbuf);
++	ipu_reg_write(ipu, IPU_Y_ADDR, bg_y_pbuf);
++	ipu_reg_write(ipu, IPU_U_ADDR, bg_u_pbuf);
++
++	/* set out buff */
++    if (ip->cmd & IPU_CMD_CSC) {/* out addr */
++        if (ip->out_fmt == HAL_PIXEL_FORMAT_HSV) {
++            ipu_reg_write(ipu, IPU_OUT_ADDR, out_y_pbuf);
++            ipu_reg_write(ipu, IPU_NV_OUT_ADDR, out_uv_pbuf);
++            ipu_reg_write(ipu, IPU_OUT_V_ADDR, out_v_pbuf);
++        } else if (ip->out_fmt == HAL_PIXEL_FORMAT_NV21) {
++            ipu_reg_write(ipu, IPU_OUT_ADDR, out_nv21_y);
++            ipu_reg_write(ipu, IPU_NV_OUT_ADDR, out_nv21_uv);
++        } else {
++            ipu_reg_write(ipu, IPU_OUT_ADDR, out_uv_pbuf);/* OUT BGRA */
++        }
++    } else {
++	    ipu_reg_write(ipu, IPU_OUT_ADDR, bg_y_pbuf);
++	    ipu_reg_write(ipu, IPU_NV_OUT_ADDR, bg_u_pbuf);
++    }
++
++    return 0;
++}
++
++static int _ipu_set_osdx_buffer(struct jz_ipu *ipu, struct ipu_param *ipu_param, int ch)
++{
++	unsigned int osdx_y_pbuf = 0;
++	unsigned int osdx_uv_pbuf = 0;
++	struct ipu_param *ip = ipu_param;
++
++	IPU_DEBUG("ipu: %s:%d \n", __func__, __LINE__);
++	if (ipu == NULL) {
++		dev_err(ipu->dev, "ipu is NULL\n");
++		return -1;
++	}
++	if ((ch < 0) || (ch > 3)) {
++		printk("ipu: osd channel num err ch = %d\n", ch);
++		return -1;
++	}
++	switch(ch) {
++		case 0:
++			osdx_y_pbuf = (unsigned int)ip->osd_ch0_buf_p;
++			osdx_uv_pbuf = (unsigned int)ip->osd_ch0_buf_p + ip->osd_ch0_src_w * ip->osd_ch0_src_h;
++			break;
++		case 1:
++			osdx_y_pbuf = (unsigned int)ip->osd_ch1_buf_p;
++			osdx_uv_pbuf = (unsigned int)ip->osd_ch1_buf_p + ip->osd_ch1_src_w * ip->osd_ch1_src_h;
++			break;
++		case 2:
++			osdx_y_pbuf = (unsigned int)ip->osd_ch2_buf_p;
++			osdx_uv_pbuf = (unsigned int)ip->osd_ch2_buf_p + ip->osd_ch2_src_w * ip->osd_ch2_src_h;
++			break;
++		case 3:
++			osdx_y_pbuf = (unsigned int)ip->osd_ch3_buf_p;
++			osdx_uv_pbuf = (unsigned int)ip->osd_ch3_buf_p + ip->osd_ch3_src_w * ip->osd_ch3_src_h;
++			break;
++		default :
++			printk("ipu: osd channel num err ch = %d\n", ch);
++			return -1;
++			break;
++	}
++
++    /* set osd chx addr */
++	IPU_DEBUG("ipu: ch = %d, osdx_y_pbuf = 0x%08x, osdx_uv_pbuf = 0x%08x\n", ch, osdx_y_pbuf, osdx_uv_pbuf);
++	ipu_reg_write(ipu, IPU_OSD_IN_CH0_Y_ADDR+0x10*ch, osdx_y_pbuf);
++	ipu_reg_write(ipu, IPU_OSD_IN_CH0_UV_ADDR+0x10*ch, osdx_uv_pbuf);
++
++	return 0;
++}
++
++static int _ipu_dump_regs(struct jz_ipu *ipu)
++{
++	int i = 0;
++	int num = 0;
++
++	if (ipu == NULL) {
++		dev_err(ipu->dev, "ipu is NULL!\n");
++		return -1;
++	}
++	printk("----- dump regs -----\n");
++
++	num = sizeof(jz_ipu_regs_name) / sizeof(struct ipu_reg_struct);
++	for (i = 0; i < num; i++) {
++		printk("ipu_reg: %s: \t0x%08x\r\n", jz_ipu_regs_name[i].name, ipu_reg_read(ipu, jz_ipu_regs_name[i].addr));
++	}
++
++	return 0;
++}
++
++static void _ipu_dump_param(struct jz_ipu *ipu)
++{
++	return;
++}
++
++static int ipu_dump_info(struct jz_ipu *ipu)
++{
++	int ret = 0;
++	if (ipu == NULL) {
++		dev_err(ipu->dev, "ipu is NULL\n");
++		return -1;
++	}
++	printk("ipu: ipu->base: %p\n", ipu->iomem);
++	_ipu_dump_param(ipu);
++	ret = _ipu_dump_regs(ipu);
++
++	return ret;
++}
++
++static int ipu_start(struct jz_ipu *ipu, struct ipu_param *ipu_param)
++{
++	int ret = 0;
++	struct ipu_param *ip = ipu_param;
++
++	if ((ipu == NULL) || (ipu_param == NULL)) {
++		dev_err(ipu->dev, "ipu: ipu is NULL or ipu_param is NULL\n");
++		return -1;
++	}
++	if ((0 == (ip->cmd & IPU_CMD_OSD))&((0 == (ip->cmd & IPU_CMD_CSC)))) {
++
++		printk("ipu: error cmd 0x%08x\n", ip->cmd);
++		ret = -1;
++		goto err_cmd;
++	}
++	IPU_DEBUG("ipu: enter ipu_start %d\n", current->pid);
++
++#ifndef CONFIG_FPGA_TEST
++	clk_prepare_enable(ipu->clk);
++#endif
++
++	__reset_ipu();
++
++	ret = _ipu_set_bg_route(ipu, ip);
++	if (ret) {
++		printk("ipu: error _ipu_set_bg_route %d\n", ret);
++		goto err_ipu_set_bg_route;
++	}
++	ret = _ipu_set_bg_buffer(ipu, ip);
++	if (ret) {
++		printk("ipu: error _ipu_set_bg_buffer %d\n", ret);
++		goto err_ipu_set_bg_buffer;
++	}
++
++    if (ip->cmd & IPU_CMD_CSC) {
++		ipu_reg_write(ipu, IPU_REG_CTRL, 0xffffffff);
++        ipu_reg_write(ipu, IPU_OSD_CH0_PARA, 0x010417fa);
++        ipu_reg_write(ipu, IPU_OSD_CH_BK_PARA, 0x141000);
++
++		ipu_reg_write(ipu, IPU_CH0_CSC_C0_COEF, (0x4ad << 0) | (0 << 20));
++		ipu_reg_write(ipu, IPU_CH0_CSC_C1_COEF, (0x669 << 0) | (0x4ad << 20));
++		ipu_reg_write(ipu, IPU_CH0_CSC_C2_COEF, (0x193 << 0) | (0x344 << 20));
++		ipu_reg_write(ipu, IPU_CH0_CSC_C3_COEF, (0x4ad << 0) | (0x81a << 20));
++		ipu_reg_write(ipu, IPU_CH0_CSC_C4_COEF, 0);
++		ipu_reg_write(ipu, IPU_CH0_CSC_OFSET_PARA, (0x10 << 0) | (0x80 << 16));
++    }
++
++	if (ip->cmd & IPU_CMD_OSD0) {
++		ret = _ipu_set_osd_chx_route(ipu, ip, 0);
++		if (ret) {
++			printk("ipu: error _ipu_set_osd_ch0_route %d\n", ret);
++			goto err_ipu_set_osd_chx_route;
++		}
++		ret = _ipu_set_osdx_buffer(ipu, ip, 0);
++		if (ret) {
++			printk("ipu: error _ipu_set_osdx_buffer %d\n", ret);
++			goto err_ipu_set_osdx_buffer;
++		}
++	}
++	if (ip->cmd & IPU_CMD_OSD1) {
++		ret = _ipu_set_osd_chx_route(ipu, ip, 1);
++		if (ret) {
++			printk("ipu: error _ipu_set_osd_ch1_route %d\n", ret);
++			goto err_ipu_set_osd_chx_route;
++		}
++		ret = _ipu_set_osdx_buffer(ipu, ip, 1);
++		if (ret) {
++			printk("ipu: error _ipu_set_osdx_buffer %d\n", ret);
++			goto err_ipu_set_osdx_buffer;
++		}
++	}
++	if (ip->cmd & IPU_CMD_OSD2) {
++		ret = _ipu_set_osd_chx_route(ipu, ip, 2);
++		if (ret) {
++			printk("ipu: error _ipu_set_osd_ch2_route %d\n", ret);
++			goto err_ipu_set_osd_chx_route;
++		}
++		ret = _ipu_set_osdx_buffer(ipu, ip, 2);
++		if (ret) {
++			printk("ipu: error _ipu_set_osdx_buffer %d\n", ret);
++			goto err_ipu_set_osdx_buffer;
++		}
++	}
++	if (ip->cmd & IPU_CMD_OSD3) {
++		ret = _ipu_set_osd_chx_route(ipu, ip, 3);
++		if (ret) {
++			printk("ipu: error _ipu_set_osd_ch3_route %d\n", ret);
++			goto err_ipu_set_osd_chx_route;
++		}
++		ret = _ipu_set_osdx_buffer(ipu, ip, 3);
++		if (ret) {
++			printk("ipu: error _ipu_set_osdx_buffer %d\n", ret);
++			goto err_ipu_set_osdx_buffer;
++		}
++	}
++
++	__clear_ipu_out_end();
++	__ipu_enable_irq();
++
++	ipu_reg_write(ipu, IPU_REG_CTRL, 0xffffffff);
++
++	/* reg_bit_set(ipu, IPU_TRIGGER, 6<<6); */
++	/* start ipu */
++	__start_ipu();
++
++#ifdef DEBUG
++	ipu_dump_info(ipu);
++#endif
++	IPU_DEBUG("ipu_start\n");
++
++	ret = wait_for_completion_interruptible_timeout(&ipu->done_ipu, msecs_to_jiffies(2000));
++	if (ret < 0) {
++		printk("ipu: done_ipu wait_for_completion_interruptible_timeout err %d\n", ret);
++		goto err_ipu_wait_for_done;
++	} else if (ret == 0 ) {
++		ret = -1;
++		printk("ipu: done_ipu wait_for_completion_interruptible_timeout timeout %d\n", ret);
++		ipu_dump_info(ipu);
++		goto err_ipu_wait_for_done;
++	} else {
++		;
++	}
++
++    IPU_DEBUG("ipu: exit ipu_start %d\n", current->pid);
++
++#ifndef CONFIG_FPGA_TEST
++	clk_disable_unprepare(ipu->clk);
++#endif
++
++    return 0;
++
++err_ipu_wait_for_done:
++err_ipu_set_osdx_buffer:
++err_ipu_set_bg_buffer:
++err_ipu_set_osd_chx_route:
++err_ipu_set_bg_route:
++#ifndef CONFIG_FPGA_TEST
++	clk_disable_unprepare(ipu->clk);
++#endif
++err_cmd:
++	return ret;
++}
++
++static long ipu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
++{
++	int ret = 0;
++	struct ipu_param iparam;
++	struct miscdevice *dev = filp->private_data;
++	struct jz_ipu *ipu = container_of(dev, struct jz_ipu, misc_dev);
++
++	IPU_DEBUG("ipu: %s pid: %d, tgid: %d file: %p, cmd: 0x%08x\n",
++			__func__, current->pid, current->tgid, filp, cmd);
++
++	if (_IOC_TYPE(cmd) != JZIPU_IOC_MAGIC) {
++		dev_err(ipu->dev, "invalid cmd!\n");
++		return -EFAULT;
++	}
++
++	mutex_lock(&ipu->mutex);
++
++	switch (cmd) {
++		case IOCTL_IPU_START:
++			if (copy_from_user(&iparam, (void *)arg, sizeof(struct ipu_param))) {
++				dev_err(ipu->dev, "copy_from_user error!!!\n");
++				ret = -EFAULT;
++				break;
++			}
++			ret = ipu_start(ipu, &iparam);
++			if (ret) {
++				printk("ipu: error ipu start ret = %d\n", ret);
++			}
++			break;
++		case IOCTL_IPU_GET_PBUFF:
++			if (ipu->pbuf.vaddr_alloc == 0) {
++				unsigned int size = IPU_BUF_SIZE;
++				ipu->pbuf.vaddr_alloc = (unsigned int)kmalloc(size, GFP_KERNEL);
++				if (!ipu->pbuf.vaddr_alloc) {
++					printk("ipu kmalloc is error\n");
++					ret = -ENOMEM;
++				}
++				memset((void*)(ipu->pbuf.vaddr_alloc), 0x00, size);
++				ipu->pbuf.size = size;
++				ipu->pbuf.paddr = virt_to_phys((void *)(ipu->pbuf.vaddr_alloc));
++				ipu->pbuf.paddr_align = ((unsigned long)(ipu->pbuf.paddr));
++			}
++			IPU_DEBUG("ipu: %s ipu->pbuf.vaddr_alloc = 0x%08x\nipu->pbuf.vaddr_align = 0x%08x\nipu->pbuf.size = 0x%x\nipu->pbuf.paddr = 0x%08x\n"
++					, __func__, ipu->pbuf.vaddr_alloc, ipu->pbuf.paddr_align, ipu->pbuf.size, ipu->pbuf.paddr);
++			if (copy_to_user((void *)arg, &ipu->pbuf, sizeof(struct ipu_buf_info))) {
++				dev_err(ipu->dev, "copy_to_user error!!!\n");
++				ret = -EFAULT;
++			}
++			break;
++		case IOCTL_IPU_RES_PBUFF:
++			if (ipu->pbuf.vaddr_alloc != 0) {
++				kfree((void *)ipu->pbuf.vaddr_alloc);
++				ipu->pbuf.vaddr_alloc = 0;
++				ipu->pbuf.size = 0;
++				ipu->pbuf.paddr = 0;
++				ipu->pbuf.paddr_align = 0;
++			} else {
++				dev_warn(ipu->dev, "buffer wanted to free is null\n");
++			}
++			break;
++		case IOCTL_IPU_BUF_LOCK:
++			ret = wait_for_completion_interruptible_timeout(&ipu->done_buf, msecs_to_jiffies(2000));
++			if (ret < 0) {
++				printk("ipu: done_buf wait_for_completion_interruptible_timeout err %d\n", ret);
++			} else if (ret == 0 ) {
++				printk("ipu: done_buf wait_for_completion_interruptible_timeout timeout %d\n", ret);
++				ret = -1;
++				ipu_dump_info(ipu);
++			} else {
++				ret = 0;
++			}
++			break;
++		case IOCTL_IPU_BUF_UNLOCK:
++			complete(&ipu->done_buf);
++			break;
++		case IOCTL_IPU_BUF_FLUSH_CACHE:
++			{
++				struct ipu_flush_cache_para fc;
++				if (copy_from_user(&fc, (void *)arg, sizeof(fc))) {
++					dev_err(ipu->dev, "copy_from_user error!!!\n");
++					ret = -EFAULT;
++					break;
++				}
++				//dma_sync_single_for_device(NULL, fc.addr, fc.size, DMA_TO_DEVICE);
++				//dma_sync_single_for_device(NULL, fc.addr, fc.size, DMA_FROM_DEVICE);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,10, 0)
++				dma_cache_wback_inv((phys_addr_t)fc.addr ,fc.size);
++#else
++				dma_cache_sync(NULL, fc.addr, fc.size, DMA_BIDIRECTIONAL);
++#endif
++			}
++			break;
++		case IOCTL_IPU_GET_DMA_FD:
++			ret = ipu_ioctl_get_dma_fd(ipu->dev,arg);break;
++		case IOCTL_IPU_GET_DMA_PHY:
++			ret = ipu_ioctl_get_dmabuf_dma_addr(ipu->dev,arg);break;
++	    default:
++			dev_err(ipu->dev, "invalid command: 0x%08x\n", cmd);
++			ret = -EINVAL;
++	}
++
++	mutex_unlock(&ipu->mutex);
++	return ret;
++}
++
++static int ipu_open(struct inode *inode, struct file *filp)
++{
++	int ret = 0;
++
++	struct miscdevice *dev = filp->private_data;
++	struct jz_ipu *ipu = container_of(dev, struct jz_ipu, misc_dev);
++
++	IPU_DEBUG("ipu: %s pid: %d, tgid: %d filp: %p\n",
++			__func__, current->pid, current->tgid, filp);
++	mutex_lock(&ipu->mutex);
++
++	mutex_unlock(&ipu->mutex);
++	return ret;
++}
++
++static int ipu_release(struct inode *inode, struct file *filp)
++{
++	int ret = 0;
++
++	struct miscdevice *dev = filp->private_data;
++	struct jz_ipu *ipu = container_of(dev, struct jz_ipu, misc_dev);
++
++	IPU_DEBUG("ipu: %s  pid: %d, tgid: %d filp: %p\n",
++			__func__, current->pid, current->tgid, filp);
++	mutex_lock(&ipu->mutex);
++
++	mutex_unlock(&ipu->mutex);
++	return ret;
++}
++
++static struct file_operations ipu_ops = {
++	.owner = THIS_MODULE,
++	.open = ipu_open,
++	.release = ipu_release,
++	.unlocked_ioctl = ipu_ioctl,
++};
++
++static irqreturn_t ipu_irq_handler(int irq, void *data)
++{
++	struct jz_ipu *ipu;
++	unsigned int status;
++
++	IPU_DEBUG("ipu: %s\n", __func__);
++	ipu = (struct jz_ipu *)data;
++	__ipu_disable_irq();
++	status = ipu_reg_read(ipu, IPU_STATUS);
++	IPU_DEBUG("----- %s, status= 0x%08x\n", __func__, status);
++	/* t10 supports 720P and max width 1280, but t20 supports 1080P and max width
++	 * is 1920; the width is limited to 1280 in hardware, so t20 status is 0x4,
++	 * and this status doesn't do anything including trigger interrupt,
++	 * just give a hint */
++    if (status & 0x1){
++        complete(&ipu->done_ipu);
++    }
++	return IRQ_HANDLED;
++}
++
++static int ipu_probe(struct platform_device *pdev)
++{
++	int ret = 0;
++	struct jz_ipu *ipu;
++
++	IPU_DEBUG("%s\n", __func__);
++	ipu = (struct jz_ipu *)kzalloc(sizeof(struct jz_ipu), GFP_KERNEL);
++	if (!ipu) {
++		dev_err(&pdev->dev, "alloc jz_ipu failed!\n");
++		return -ENOMEM;
++	}
++
++	sprintf(ipu->name, "ipu");
++
++	ipu->misc_dev.minor = MISC_DYNAMIC_MINOR;
++	ipu->misc_dev.name = ipu->name;
++	ipu->misc_dev.fops = &ipu_ops;
++	ipu->dev = &pdev->dev;
++
++	mutex_init(&ipu->mutex);
++	init_completion(&ipu->done_ipu);
++	init_completion(&ipu->done_buf);
++	complete(&ipu->done_buf);
++
++	ipu->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!ipu->res) {
++		dev_err(&pdev->dev, "failed to get dev resources: %d\n", ret);
++		ret = -EINVAL;
++		goto err_get_platform_res;
++	}
++	ipu->res = request_mem_region(ipu->res->start,
++			ipu->res->end - ipu->res->start + 1,
++			pdev->name);
++	if (!ipu->res) {
++		dev_err(&pdev->dev, "failed to request regs memory region");
++		ret = -EINVAL;
++		goto err_get_mem_region;
++	}
++	ipu->iomem = ioremap(ipu->res->start, resource_size(ipu->res));
++	if (!ipu->iomem) {
++		dev_err(&pdev->dev, "failed to remap regs memory region: %d\n",ret);
++		ret = -EINVAL;
++		goto err_ioremap;
++	}
++
++	ipu->irq = platform_get_irq(pdev, 0);
++	if (request_irq(ipu->irq, ipu_irq_handler, IRQF_SHARED, ipu->name, ipu)) {
++		dev_err(&pdev->dev, "request irq failed\n");
++		ret = -EINVAL;
++		goto err_req_irq;
++	}
++
++#ifndef CONFIG_FPGA_TEST
++	ipu->clk = devm_clk_get(ipu->dev, "gate_ipu");
++	if (IS_ERR(ipu->clk)) {
++		dev_err(&pdev->dev, "ipu clk get failed!\n");
++		ret = -EINVAL;
++		goto err_get_ipu_clk;
++	}
++#endif
++
++	dev_set_drvdata(&pdev->dev, ipu);
++
++	__reset_ipu();
++	ret = misc_register(&ipu->misc_dev);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "register misc device failed!\n");
++		goto err_misc_register;
++	}
++	ret = of_reserved_mem_device_init(ipu->dev);
++	if(ret)
++		    dev_warn(ipu->dev, "failed to init reserved mem\n");
++
++	return 0;
++
++err_misc_register:
++#ifndef CONFIG_FPGA_TEST
++	devm_clk_put(ipu->dev, ipu->clk);
++err_get_ipu_clk:
++#endif
++	free_irq(ipu->irq, ipu);
++err_req_irq:
++	iounmap(ipu->iomem);
++err_ioremap:
++	release_mem_region(ipu->res->start, ipu->res->end - ipu->res->start + 1);
++err_get_platform_res:
++err_get_mem_region:
++	kfree(ipu);
++
++	return ret;
++}
++
++static int ipu_remove(struct platform_device *pdev)
++{
++	struct jz_ipu *ipu;
++	struct resource *res;
++	IPU_DEBUG("%s\n", __func__);
++
++	ipu = dev_get_drvdata(&pdev->dev);
++	misc_deregister(&ipu->misc_dev);
++#ifndef CONFIG_FPGA_TEST
++	devm_clk_put(ipu->dev, ipu->clk);
++#endif
++	res = ipu->res;
++	free_irq(ipu->irq, ipu);
++	iounmap(ipu->iomem);
++	release_mem_region(res->start, res->end - res->start + 1);
++
++	if (ipu->pbuf.vaddr_alloc) {
++		kfree((void *)(ipu->pbuf.vaddr_alloc));
++		ipu->pbuf.vaddr_alloc = 0;
++	}
++	if (ipu) {
++		kfree(ipu);
++	}
++
++	return 0;
++}
++
++static const struct of_device_id ingenic_ipu_dt_match[] = {
++	{ .compatible = "ingenic,x2500-ipu", .data = NULL },
++	{},
++};
++
++MODULE_DEVICE_TABLE(of, ingenic_ipu_dt_match);
++
++static struct platform_driver jz_ipu_driver = {
++	.probe	= ipu_probe,
++	.remove = ipu_remove,
++	.driver = {
++		.name = "jz-ipu",
++		.owner  = THIS_MODULE,
++		.of_match_table = of_match_ptr(ingenic_ipu_dt_match),
++	},
++};
++
++static int __init ipudev_init(void)
++{
++	IPU_DEBUG("%s\n", __func__);
++	platform_driver_register(&jz_ipu_driver);
++	return 0;
++}
++
++static void __exit ipudev_exit(void)
++{
++	IPU_DEBUG("%s\n", __func__);
++	platform_driver_unregister(&jz_ipu_driver);
++}
++
++module_init(ipudev_init);
++module_exit(ipudev_exit);
++
++MODULE_DESCRIPTION("JZ IPU driver");
++MODULE_AUTHOR("Ferdinand Jia <bcjia@ingenic.cn>");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/drivers/video/ingenic_ipu/ingenic_ipu_v13.h b/module_drivers/drivers/video/ingenic_ipu/ingenic_ipu_v13.h
+new file mode 100644
+index 000000000..96010964d
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_ipu/ingenic_ipu_v13.h
+@@ -0,0 +1,210 @@
++#ifndef _JZ_IPU_H_
++#define _JZ_IPU_H_
++
++#define IPU_LUT_LEN      32
++
++/* ipu output mode */
++#define IPU_OUTPUT_TO_LCD_FG1           0x00000002
++#define IPU_OUTPUT_TO_LCD_FB0           0x00000004
++#define IPU_OUTPUT_TO_LCD_FB1           0x00000008
++#define IPU_OUTPUT_TO_FRAMEBUFFER       0x00000010 /* output to user defined buffer */
++#define IPU_OUTPUT_MODE_MASK            0x000000FF
++#define IPU_DST_USE_COLOR_KEY           0x00000100
++#define IPU_DST_USE_ALPHA               0x00000200
++#define IPU_OUTPUT_BLOCK_MODE           0x00000400
++#define IPU_OUTPUT_MODE_FG0_OFF         0x00000800
++#define IPU_OUTPUT_MODE_FG1_TVOUT       0x00001000
++#define IPU_DST_USE_PERPIXEL_ALPHA      0x00010000
++
++#ifdef __KERNEL__
++
++/* match HAL_PIXEL_FORMAT_ in system/core/include/system/graphics.h */
++enum {
++	HAL_PIXEL_FORMAT_RGBA_8888    = 1,
++	HAL_PIXEL_FORMAT_RGBX_8888    = 2,
++	HAL_PIXEL_FORMAT_RGB_888      = 3,
++	HAL_PIXEL_FORMAT_RGB_565      = 4,
++	HAL_PIXEL_FORMAT_BGRA_8888    = 5,
++	//HAL_PIXEL_FORMAT_BGRX_8888    = 0x8000, /* Add BGRX_8888, Wolfgang, 2010-07-24 */
++	HAL_PIXEL_FORMAT_BGRX_8888  	= 0x1ff, /* 2012-10-23 */
++	HAL_PIXEL_FORMAT_RGBA_5551    = 6,
++	HAL_PIXEL_FORMAT_RGBA_4444    = 7,
++	HAL_PIXEL_FORMAT_ABGR_8888    = 8,
++	HAL_PIXEL_FORMAT_ARGB_8888    = 9,
++	HAL_PIXEL_FORMAT_YCbCr_422_SP = 0x10,
++	HAL_PIXEL_FORMAT_YCbCr_420_SP = 0x11,
++	HAL_PIXEL_FORMAT_YCbCr_422_P  = 0x12,
++	HAL_PIXEL_FORMAT_YCbCr_420_P  = 0x13,
++	HAL_PIXEL_FORMAT_YCbCr_420_B  = 0x24,
++	HAL_PIXEL_FORMAT_YCbCr_422_I  = 0x14,
++	HAL_PIXEL_FORMAT_YCbCr_420_I  = 0x15,
++	HAL_PIXEL_FORMAT_CbYCrY_422_I = 0x16,
++	HAL_PIXEL_FORMAT_CbYCrY_420_I = 0x17,
++	HAL_PIXEL_FORMAT_NV12		  = 0x18,
++	HAL_PIXEL_FORMAT_NV21 		  = 0x19,
++	HAL_PIXEL_FORMAT_BGRA_5551    = 0x1a,
++    HAL_PIXEL_FORMAT_HSV          = 0x1b,/*Add HSV*/
++
++	/* suport for YUV420 */
++	HAL_PIXEL_FORMAT_JZ_YUV_420_P       = 0x47700001, // YUV_420_P
++	HAL_PIXEL_FORMAT_JZ_YUV_420_B       = 0x47700002, // YUV_420_P BLOCK MODE
++};
++
++typedef struct {
++	unsigned int coef;
++	unsigned short int in_n;
++	unsigned short int out_n;
++} rsz_lut;
++
++#endif /* ifdef __KERNEL__ */
++
++enum {
++	ZOOM_MODE_BILINEAR = 0,
++	ZOOM_MODE_BICUBE,
++	ZOOM_MODE_BILINEAR_ENHANCE,
++};
++
++struct YuvCsc
++{									// YUV(default)	or	YCbCr
++	unsigned int csc0;				//	0x400			0x4A8
++	unsigned int csc1;              //	0x59C   		0x662
++	unsigned int csc2;              //	0x161   		0x191
++	unsigned int csc3;              //	0x2DC   		0x341
++	unsigned int csc4;              //	0x718   		0x811
++	unsigned int chrom;             //	128				128
++	unsigned int luma;              //	0				16
++};
++
++struct YuvStride
++{
++	unsigned int y;
++	unsigned int u;
++	unsigned int v;
++	unsigned int out;
++	unsigned int out_uv;
++};
++
++struct ipu_param
++{
++	unsigned int		cmd;			/* IPU command */
++
++	unsigned int 		bg_w;			/* background weight */
++	unsigned int 		bg_h;			/* background hight */
++	unsigned int 		bg_fmt;			/* background format */
++	unsigned int		bg_buf_p;       /* background buffer physical addr */
++
++	unsigned int 		out_fmt;		/* out format */
++
++	unsigned int		osd_ch0_fmt;
++	unsigned int		osd_ch0_para;
++	unsigned int		osd_ch0_bak_argb;
++	unsigned int		osd_ch0_pos_x;
++	unsigned int		osd_ch0_pos_y;
++	unsigned int		osd_ch0_src_w;
++	unsigned int		osd_ch0_src_h;
++	unsigned int		osd_ch0_buf_p;
++
++
++	unsigned int		osd_ch1_fmt;
++	unsigned int		osd_ch1_para;
++	unsigned int		osd_ch1_bak_argb;
++	unsigned int		osd_ch1_pos_x;
++	unsigned int		osd_ch1_pos_y;
++	unsigned int		osd_ch1_src_w;
++	unsigned int		osd_ch1_src_h;
++	unsigned int		osd_ch1_buf_p;
++
++
++	unsigned int		osd_ch2_fmt;
++	unsigned int		osd_ch2_para;
++	unsigned int		osd_ch2_bak_argb;
++	unsigned int		osd_ch2_pos_x;
++	unsigned int		osd_ch2_pos_y;
++	unsigned int		osd_ch2_src_w;
++	unsigned int		osd_ch2_src_h;
++	unsigned int		osd_ch2_buf_p;
++
++	unsigned int		osd_ch3_fmt;
++	unsigned int		osd_ch3_para;
++	unsigned int		osd_ch3_bak_argb;
++	unsigned int		osd_ch3_pos_x;
++	unsigned int		osd_ch3_pos_y;
++	unsigned int		osd_ch3_src_w;
++	unsigned int		osd_ch3_src_h;
++	unsigned int		osd_ch3_buf_p;
++
++};
++
++
++#define IPU_CMD_OSD0		(1<<0)
++#define IPU_CMD_OSD1		(1<<1)
++#define IPU_CMD_OSD2		(1<<2)
++#define IPU_CMD_OSD3		(1<<3)
++#define IPU_CMD_OSD			(0xF<<0)
++#define IPU_CMD_CSC			(1<<4)
++
++#ifdef __KERNEL__
++
++/*
++ * IPU driver's native data
++ */
++
++struct ipu_reg_struct {
++	char *name;
++	unsigned int addr;
++};
++
++struct ipu_buf_info {
++	unsigned int vaddr_alloc;
++	unsigned int paddr;
++	unsigned int paddr_align;
++	unsigned int size;
++};
++
++struct jz_ipu {
++
++	int irq;
++	char name[16];
++
++	struct clk *clk;
++	struct clk *ahb0_gate; /* T31 IPU mount at AHB0*/
++	void __iomem *iomem;
++	struct device *dev;
++	struct resource *res;
++	struct miscdevice misc_dev;
++
++	struct mutex mutex;
++	struct completion done_ipu;
++	struct completion done_buf;
++	struct ipu_buf_info pbuf;
++};
++
++struct ipu_flush_cache_para
++{
++	void *addr;
++	unsigned int size;
++};
++
++#define JZIPU_IOC_MAGIC  'I'
++#define IOCTL_IPU_START			_IO(JZIPU_IOC_MAGIC, 106)
++#define IOCTL_IPU_RES_PBUFF		_IO(JZIPU_IOC_MAGIC, 114)
++#define IOCTL_IPU_GET_PBUFF		_IO(JZIPU_IOC_MAGIC, 115)
++#define IOCTL_IPU_BUF_LOCK		_IO(JZIPU_IOC_MAGIC, 116)
++#define IOCTL_IPU_BUF_UNLOCK	_IO(JZIPU_IOC_MAGIC, 117)
++#define IOCTL_IPU_BUF_FLUSH_CACHE	_IO(JZIPU_IOC_MAGIC, 118)
++#define IOCTL_IPU_GET_DMA_FD		_IO(JZIPU_IOC_MAGIC, 119)
++#define IOCTL_IPU_GET_DMA_PHY		_IO(JZIPU_IOC_MAGIC, 120)
++
++static inline unsigned int ipu_reg_read(struct jz_ipu *jzipu, int offset)
++{
++	return readl(jzipu->iomem + offset);
++}
++
++static inline void ipu_reg_write(struct jz_ipu *jzipu, int offset, unsigned int val)
++{
++	writel(val, jzipu->iomem + offset);
++}
++
++#endif	/* #ifdef __KERNEL__ */
++
++#endif // _JZ_IPU_H_
+diff --git a/module_drivers/drivers/video/ingenic_ipu/ingenic_regs_v13.h b/module_drivers/drivers/video/ingenic_ipu/ingenic_regs_v13.h
+new file mode 100644
+index 000000000..b00960c2e
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_ipu/ingenic_regs_v13.h
+@@ -0,0 +1,349 @@
++#ifndef _REGS_IPU_H_
++#define _REGS_IPU_H_
++
++#ifdef __KERNEL__
++
++/* Module for CLKGR */
++#define IDCT_CLOCK      (1 << 27)
++#define DBLK_CLOCK      (1 << 26)
++#define ME_CLOCK        (1 << 25)
++#define MC_CLOCK        (1 << 24)
++#define IPU_CLOCK       (1 << 13)
++
++
++/* Register offset */
++#define  IPU_FM_CTRL                0x0
++#define  IPU_STATUS                 0x4
++#define  IPU_D_FMT                  0x8
++#define  IPU_Y_ADDR                 0xc
++#define  IPU_U_ADDR                 0x10
++#define  IPU_IN_FM_GS               0x18
++#define  IPU_Y_STRIDE               0x1c
++#define  IPU_UV_STRIDE              0x20
++
++#define  IPU_OUT_ADDR               0x24
++#define  IPU_OUT_STRIDE             0x2c
++#define  IPU_OUT_V_ADDR             0x30
++#define  IPU_OUT_V_STRIDE           0x34
++
++#define  IPU_REG_CTRL               0x64
++#define  IPU_TRIGGER                0x74
++#define  IPU_GLB_CTRL               0x7C
++
++#define  IPU_NV_OUT_ADDR			0xb4
++#define  IPU_NV_OUT_STRIDE			0xb8
++#define  IPU_OSD_IN_CH0_Y_ADDR		0xbc
++#define  IPU_OSD_IN_CH0_Y_STRIDE	0xc0
++#define  IPU_OSD_IN_CH0_UV_ADDR		0xc4
++#define  IPU_OSD_IN_CH0_UV_STRIDE	0xc8
++#define  IPU_OSD_IN_CH1_Y_ADDR		0xcc
++#define  IPU_OSD_IN_CH1_Y_STRIDE	0xd0
++#define  IPU_OSD_IN_CH1_UV_ADDR		0xd4
++#define  IPU_OSD_IN_CH1_UV_STRIDE	0xd8
++#define  IPU_OSD_IN_CH2_Y_ADDR		0xdc
++#define  IPU_OSD_IN_CH2_Y_STRIDE	0xe0
++#define  IPU_OSD_IN_CH2_UV_ADDR		0xe4
++#define  IPU_OSD_IN_CH2_UV_STRIDE	0xe8
++#define  IPU_OSD_IN_CH3_Y_ADDR		0xec
++#define  IPU_OSD_IN_CH3_Y_STRIDE	0xf0
++#define  IPU_OSD_IN_CH3_UV_ADDR		0xf4
++#define  IPU_OSD_IN_CH3_UV_STRIDE	0xf8
++#define  IPU_OSD_CH0_GS				0xfc
++#define  IPU_OSD_CH1_GS				0x100
++#define  IPU_OSD_CH2_GS				0x104
++#define  IPU_OSD_CH3_GS				0x108
++#define  IPU_OSD_CH0_POS			0x10c
++#define  IPU_OSD_CH1_POS			0x110
++#define  IPU_OSD_CH2_POS			0x114
++#define  IPU_OSD_CH3_POS			0x118
++#define  IPU_OSD_CH0_PARA			0x11c
++#define  IPU_OSD_CH1_PARA			0x120
++#define  IPU_OSD_CH2_PARA			0x124
++#define  IPU_OSD_CH3_PARA			0x128
++#define  IPU_OSD_CH_BK_PARA			0x12c
++
++#define  IPU_OSD_CH0_BAK_ARGB		0x130
++#define  IPU_OSD_CH1_BAK_ARGB		0x134
++#define  IPU_OSD_CH2_BAK_ARGB		0x138
++#define  IPU_OSD_CH3_BAK_ARGB		0x13c
++#define  IPU_OSD_CH_B_BAK_ARGB		0x140
++
++#define  IPU_CH0_CSC_C0_COEF		0x148
++#define  IPU_CH0_CSC_C1_COEF		0x14c
++#define  IPU_CH0_CSC_C2_COEF		0x150
++#define  IPU_CH0_CSC_C3_COEF		0x154
++#define  IPU_CH0_CSC_C4_COEF		0x158
++#define  IPU_CH0_CSC_OFSET_PARA		0x15c
++
++#define  IPU_CH1_CSC_C0_COEF		0x160
++#define  IPU_CH1_CSC_C1_COEF		0x164
++#define  IPU_CH1_CSC_C2_COEF		0x168
++#define  IPU_CH1_CSC_C3_COEF		0x16c
++#define  IPU_CH1_CSC_C4_COEF		0x170
++#define  IPU_CH1_CSC_OFSET_PARA		0x174
++
++#define  IPU_CH2_CSC_C0_COEF		0x178
++#define  IPU_CH2_CSC_C1_COEF		0x17c
++#define  IPU_CH2_CSC_C2_COEF		0x180
++#define  IPU_CH2_CSC_C3_COEF		0x184
++#define  IPU_CH2_CSC_C4_COEF		0x188
++#define  IPU_CH2_CSC_OFSET_PARA		0x18c
++
++#define  IPU_CH3_CSC_C0_COEF		0x190
++#define  IPU_CH3_CSC_C1_COEF		0x194
++#define  IPU_CH3_CSC_C2_COEF		0x198
++#define  IPU_CH3_CSC_C3_COEF		0x19c
++#define  IPU_CH3_CSC_C4_COEF		0x1a0
++#define  IPU_CH3_CSC_OFSET_PARA		0x1a4
++
++#define  IPU_RD_ARB_CTL				0x1a8
++#define  IPU_CLK_NUM_ONE_FRA		0x1ac
++#define  IPU_OSD_LAY_PADDING_ARGB	0x1b0
++#define  IPU_TEST_1B4				0x1b4
++
++
++/* SET CH_BK_PARA Register*/
++#define  CH_BK_EN					(1 << 0)
++#define	 CH_BK_PIXEL_ALPHA			(0 << 2) //default
++#define  CH_BK_GLOBAL_ALPHA			(1 << 1)
++#define  CH_BK_PALPHA_X_GALPHA		(1 << 2)
++#define  CH_BKCH_BK_GLO_A(val)		((val) << 3)
++
++#define  CH_BK_PIC_TYPE				( 11 )
++#define  CH_BK_PIC_TYPE_ARGB		(0 << CH_BK_PIC_TYPE)
++#define  CH_BK_PIC_TYPE_RGB			(1 << CH_BK_PIC_TYPE)
++#define  CH_BK_PIC_TYPE_NV12		(2 << CH_BK_PIC_TYPE)
++#define  CH_BK_PIC_TYPE_NV21		(3 << CH_BK_PIC_TYPE)
++
++/*
++0000: ARGB          0001: ARBG
++0010: AGRB          0011: AGBR
++0100: ABRG          0101: ABGR
++1000: RGBA          1001: RBGA
++1010: GRBA          1011: GBRA
++1100: BRGA          1101: BGRA
++*/
++#define  CH_BK_ARGB_TYPE			( 14 )
++#define  CH_BK_ARGB_TYPE_ARGB		(0 << CH_BK_ARGB_TYPE)
++#define  CH_BK_ARGB_TYPE_ARBG		(1 << CH_BK_ARGB_TYPE)
++#define  CH_BK_ARGB_TYPE_AGRB		(2 << CH_BK_ARGB_TYPE)
++#define  CH_BK_ARGB_TYPE_AGBR		(3 << CH_BK_ARGB_TYPE)
++#define  CH_BK_ARGB_TYPE_ABRG		(4 << CH_BK_ARGB_TYPE)
++#define  CH_BK_ARGB_TYPE_ABGR		(5 << CH_BK_ARGB_TYPE)
++#define  CH_BK_ARGB_TYPE_RGBA		(8 << CH_BK_ARGB_TYPE)
++#define  CH_BK_ARGB_TYPE_RBGA		(9 << CH_BK_ARGB_TYPE)
++#define  CH_BK_ARGB_TYPE_GRBA		(0xa << CH_BK_ARGB_TYPE)
++#define  CH_BK_ARGB_TYPE_GBRA		(0xb << CH_BK_ARGB_TYPE)
++#define  CH_BK_ARGB_TYPE_BRGA		(0xc << CH_BK_ARGB_TYPE)
++#define  CH_BK_ARGB_TYPE_BGRA		(0xd << CH_BK_ARGB_TYPE)
++
++#define  CH_BK_PREM					(1 << 18)
++#define  CH_BK_MASK_EN				(1 << 19)
++#define  CH_BK_WHOLE_PIC_EN			(1 << 20)
++
++/*OSD_CHN_EN*/
++#define CHOOSE_OSD_CHN_RESIZE   (1 << 5)
++
++/* IPU_GLB_CTRL Register */
++#define IRQ_EN          (1 << 0)
++
++/* IPU_OSD_CTRL Register */
++#define OSD_PM          (1 << 2)
++
++/* IPU_TRIG Register */
++#define IPU_RUN         (1 << 0)
++#define IPU_STOP        (1 << 1)
++#define IPU_RESET       (1 << 3)
++
++/* IPU_D_FMT Register */
++#define BLK_SEL         (1 << 4)
++#define RGB_POS			(1 << 5)
++#define AL_PIX_EN		(1 << 6)
++
++/* REG_STATUS field define */
++#define OUT_END         (1 << 0)
++#define SIZE_ERR        (1 << 2)
++#define ID				(1 << 16)
++
++#define MSTATUS_SFT     (4)
++#define MSTATUS_MSK     (3)
++#define MSTATUS_IPU_FREE        (0 << MSTATUS_SFT)
++#define MSTATUS_IPU_RUNNING     (1 << MSTATUS_SFT)
++#define MSTATUS                 (2 << MSTATUS_SFT)
++
++/* REG_IPU_ADDR_CTRL */
++#define Y_RY            (1<<0)
++#define U_RY            (1<<1)
++#define V_RY            (1<<2)
++#define D_RY            (1<<3)
++#define PTS_RY          (1<<4)
++#define CTRL_RY         (1<<6)
++#define DF_RY           (1<<7)
++#define NV_D_RY			(1 << 17)
++#define NV_STR_RY		(1 << 20)
++#define OSD_CH0_RY		(1 << 21)
++#define OSD_CH1_RY		(1 << 22)
++#define OSD_CH2_RY		(1 << 23)
++#define OSD_CH3_RY		(1 << 24)
++#define RD_ARB_RY		(1 << 26)
++#define OSD_BK_RY		(1 << 27)
++
++/* REG_TLB_MONITOR */
++#define MIS_CNT_SFT     (1)
++#define MIS_CNT_MSK     (0x3FF)
++
++/* REG_TLB_CTRL */
++#define SRC_PAGE_SFT        (0)
++#define SRC_PAGE_MSK        (0xF)
++#define SRC_BURST_SFT       (4)
++#define SRC_BURST_MSK       (0xF)
++#define DEST_PAGE_SFT       (16)
++#define DEST_PAGE_MSK       (0xF)
++#define DEST_BURST_SFT      (20)
++#define DEST_BURST_MSK      (0xF)
++
++/* OSD_CTRL field define */
++#define GLB_ALPHA(val)  ((val) << 8)
++#define MOD_OSD(val)    ((val) << 0)
++
++/* FM_XYOFT field define */
++#define SCREEN_YOFT(val)    ((val) << 16)
++#define SCREEN_XOFT(val)    ((val) << 0)
++
++/* REG_IN_GS field define */
++#define IN_FM_W(val)    ((val) << 16)
++#define IN_FM_H(val)    ((val) << 0)
++
++/* REG_OUT_GS field define */
++#define OUT_FM_W(val)    ((val) << 16)
++#define OUT_FM_H(val)    ((val) << 0)
++
++/* REG_UV_STRIDE field define */
++#define U_STRIDE(val)     ((val) << 16)
++#define V_STRIDE(val)     ((val) << 0)
++
++/* REG_RSZ_COEF field definei */
++#define HCOEF(val)			((val) << 16)
++#define VCOEF(val)			((val) << 0)
++
++#if 1
++#define YUV_CSC_C0 0x4A8        /* 1.164 * 1024 */
++#define YUV_CSC_C1 0x662        /* 1.596 * 1024 */
++#define YUV_CSC_C2 0x191        /* 0.392 * 1024 */
++#define YUV_CSC_C3 0x341        /* 0.813 * 1024 */
++#define YUV_CSC_C4 0x811        /* 2.017 * 1024 */
++
++#define YUV_CSC_OFFSET_PARA         0x800010  /* chroma,luma */
++#else
++#define YUV_CSC_C0 0x400
++#define YUV_CSC_C1 0x59C
++#define YUV_CSC_C2 0x161
++#define YUV_CSC_C3 0x2DC
++#define YUV_CSC_C4 0x718
++#endif
++
++/* select ch */
++#define BK_OSD_PIC_MASK				(18)
++#define BK_OSD_PIC_NV21			( 1 << BK_OSD_PIC_MASK )
++#define BK_OSD_PIC_NV12			( 2 << BK_OSD_PIC_MASK )
++#define BK_OSD_PIC_ARGB			( 3 << BK_OSD_PIC_MASK )
++#define CH3_OSD_PIC_MASK			(15)
++#define CH3_OSD_PIC_NV21		( 1 << CH3_OSD_PIC_MASK )
++#define CH3_OSD_PIC_NV12		( 2 << CH3_OSD_PIC_MASK )
++#define CH3_OSD_PIC_ARGB		( 3 << CH3_OSD_PIC_MASK )
++#define CH2_OSD_PIC_MASK			(12)
++#define CH2_OSD_PIC_NV21		( 1 << CH2_OSD_PIC_MASK )
++#define CH2_OSD_PIC_NV12		( 2 << CH2_OSD_PIC_MASK )
++#define CH2_OSD_PIC_ARGB		( 3 << CH2_OSD_PIC_MASK )
++#define CH1_OSD_PIC_MASK			(9)
++#define CH1_OSD_PIC_NV21		( 1 << CH1_OSD_PIC_MASK )
++#define CH1_OSD_PIC_NV12		( 2 << CH1_OSD_PIC_MASK )
++#define CH1_OSD_PIC_ARGB		( 3 << CH1_OSD_PIC_MASK )
++#define CH0_OSD_PIC_MASK			(6)
++#define CH0_OSD_PIC_NV21		( 1 << CH0_OSD_PIC_MASK )
++#define CH0_OSD_PIC_NV12		( 2 << CH0_OSD_PIC_MASK )
++#define CH0_OSD_PIC_ARGB		( 3 << CH0_OSD_PIC_MASK )
++#define OSD_CHN_EN_MASK				(0)
++#define OSD_CHN_EN_CH0			( 1  << OSD_CHN_EN_MASK )
++#define OSD_CHN_EN_CH1			( 2  << OSD_CHN_EN_MASK )
++#define OSD_CHN_EN_CH2			( 4  << OSD_CHN_EN_MASK )
++#define OSD_CHN_EN_CH3			( 8  << OSD_CHN_EN_MASK )
++#define OSD_CHN_EN_BKG			( 16 << OSD_CHN_EN_MASK )
++#define OSD_CHN_EN_DST			( 32 << OSD_CHN_EN_MASK )
++
++#endif	/* #ifdef __KERNEL__ */
++
++///////////////////////////////////////////
++
++/* Data Format Register, export to libipu */
++#define RGB_888_OUT_FMT				( 1 << 25 )
++
++#define RGB_OUT_OFT_BIT				( 22 )
++#define RGB_OUT_OFT_MASK			( 7 << RGB_OUT_OFT_BIT )
++#define RGB_OUT_OFT_RGB				( 0 << RGB_OUT_OFT_BIT )
++#define RGB_OUT_OFT_RBG				( 1 << RGB_OUT_OFT_BIT )
++#define RGB_OUT_OFT_GBR				( 2 << RGB_OUT_OFT_BIT )
++#define RGB_OUT_OFT_GRB				( 3 << RGB_OUT_OFT_BIT )
++#define RGB_OUT_OFT_BRG				( 4 << RGB_OUT_OFT_BIT )
++#define RGB_OUT_OFT_BGR				( 5 << RGB_OUT_OFT_BIT )
++
++#define OUT_FMT_BIT					( 19 )
++#define OUT_FMT_MASK				( 3 <<  OUT_FMT_BIT )
++#define OUT_FMT_RGB555				( 0 <<  OUT_FMT_BIT )
++#define OUT_FMT_RGB565				( 1 <<  OUT_FMT_BIT )
++#define OUT_FMT_RGB888				( 2 <<  OUT_FMT_BIT )
++#define OUT_FMT_YUV422				( 3 <<  OUT_FMT_BIT )
++#define OUT_FMT_RGBAAA				( 4 <<  OUT_FMT_BIT )
++#define OUT_FMT_NV12				( 6 <<  OUT_FMT_BIT )
++#define OUT_FMT_NV21				( 7 <<  OUT_FMT_BIT )
++#define OUT_FMT_HSV                 ( 1 << 2 )                    /*Add HSV*/
++
++#define YUV_PKG_OUT_OFT_BIT			( 16 )
++#define YUV_PKG_OUT_OFT_MASK		( 7 << YUV_PKG_OUT_OFT_BIT )
++#define YUV_PKG_OUT_OFT_Y1UY0V		( 0 << YUV_PKG_OUT_OFT_BIT )
++#define YUV_PKG_OUT_OFT_Y1VY0U		( 1 << YUV_PKG_OUT_OFT_BIT )
++#define YUV_PKG_OUT_OFT_UY1VY0		( 2 << YUV_PKG_OUT_OFT_BIT )
++#define YUV_PKG_OUT_OFT_VY1UY0		( 3 << YUV_PKG_OUT_OFT_BIT )
++#define YUV_PKG_OUT_OFT_Y0UY1V		( 4 << YUV_PKG_OUT_OFT_BIT )
++#define YUV_PKG_OUT_OFT_Y0VY1U		( 5 << YUV_PKG_OUT_OFT_BIT )
++#define YUV_PKG_OUT_OFT_UY0VY1		( 6 << YUV_PKG_OUT_OFT_BIT )
++#define YUV_PKG_OUT_OFT_VY0UY1		( 7 << YUV_PKG_OUT_OFT_BIT )
++
++#define IN_OFT_BIT					( 2 )
++#define IN_OFT_MASK					( 3 << IN_OFT_BIT )
++#define IN_OFT_Y1UY0V				( 0 << IN_OFT_BIT )
++#define IN_OFT_Y1VY0U				( 1 << IN_OFT_BIT )
++#define IN_OFT_UY1VY0				( 2 << IN_OFT_BIT )
++#define IN_OFT_VY1UY0				( 3 << IN_OFT_BIT )
++
++#define IN_FMT_BIT					( 0 )
++#define IN_FMT_MASK					( 7 << IN_FMT_BIT )
++#define IN_FMT_YUV420				( 0 << IN_FMT_BIT )
++#define IN_FMT_YUV420_B				( 4 << IN_FMT_BIT )
++#define IN_FMT_YUV422				( 1 << IN_FMT_BIT )
++#define IN_FMT_YUV444				( 2 << IN_FMT_BIT )
++#define IN_FMT_RGB_555				( 0 << IN_FMT_BIT )
++#define IN_FMT_RGB_888			    ( 2 << IN_FMT_BIT )
++#define IN_FMT_RGB_565				( 3 << IN_FMT_BIT )
++#define IN_FMT_YUV411				( 3 << IN_FMT_BIT )
++
++//hwang add
++#define NV_SEL						( 1 << 7 )
++#define NV_MODE_NV12				( 0 << 8 )
++#define NV_MODE_NV21				( 1 << 8 )
++
++#define __enable_blk_mode()		reg_bit_set(ipu, IPU_D_FMT, BLK_SEL)
++#define __disable_blk_mode()	reg_bit_clr(ipu, IPU_D_FMT, BLK_SEL)
++#define __clear_ipu_out_end()	reg_bit_clr(ipu, IPU_STATUS, OUT_END)
++#define __ipu_enable_irq()						\
++	do {unsigned int val = IRQ_EN ;				\
++		reg_bit_set(ipu, IPU_GLB_CTRL, val);	\
++	}while(0)
++#define __ipu_disable_irq()						\
++	do {unsigned int val = IRQ_EN ;				\
++		reg_bit_clr(ipu, IPU_GLB_CTRL, val);	\
++	}while(0)
++#define __start_ipu()			reg_bit_set(ipu, IPU_TRIGGER, IPU_RUN)
++#define __reset_ipu()			reg_bit_set(ipu, IPU_TRIGGER, IPU_RESET)
++
++#endif // _REGS_IPU_H_
+diff --git a/module_drivers/drivers/video/ingenic_ipu/ipu_dmabuf.c b/module_drivers/drivers/video/ingenic_ipu/ipu_dmabuf.c
+new file mode 100644
+index 000000000..5f8e9c8ee
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_ipu/ipu_dmabuf.c
+@@ -0,0 +1,702 @@
++#include "ipu_dmabuf.h"
++
++#include <linux/uaccess.h>
++#include <linux/dma-buf.h>
++#include <linux/version.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/anon_inodes.h>
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Kevin Grandemange");
++MODULE_AUTHOR("Sebastien Alaiwan");
++MODULE_AUTHOR("Antoine Gruzelle");
++MODULE_DESCRIPTION("JZ Common");
++
++struct ipu_dmabuf_priv {
++	struct ipu_dma_buffer *buffer;
++
++	/* DMABUF related */
++	struct device *dev;
++	struct sg_table *sgt_base;
++	enum dma_data_direction dma_dir;
++
++};
++
++struct ipu_dmabuf_attachment {
++	struct sg_table sgt;
++	enum dma_data_direction dma_dir;
++};
++
++struct ipu_dma_buffer *ipu_alloc_dma(struct device *dev, size_t size)
++{
++	struct ipu_dma_buffer *buf =
++		kmalloc(sizeof(struct ipu_dma_buffer),
++			GFP_KERNEL);
++
++	if (!buf)
++		return NULL;
++
++	buf->size = size;
++	buf->cpu_handle = dma_alloc_coherent(dev, buf->size,
++					     &buf->dma_handle,
++					     GFP_KERNEL | GFP_DMA);
++
++	if (!buf->cpu_handle) {
++		kfree(buf);
++		return NULL;
++	}
++
++	return buf;
++}
++
++void ipu_free_dma(struct device *dev, struct ipu_dma_buffer *buf)
++{
++	if (buf)
++		dma_free_coherent(dev, buf->size, buf->cpu_handle,
++				  buf->dma_handle);
++	kfree(buf);
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0)
++/* device argument was removed */
++static int ipu_dmabuf_attach(struct dma_buf *dbuf, struct dma_buf_attachment *dbuf_attach)
++#else
++static int ipu_dmabuf_attach(struct dma_buf *dbuf, struct device* dev, struct dma_buf_attachment *dbuf_attach)
++#endif
++{
++	struct ipu_dmabuf_priv *dinfo = dbuf->priv;
++
++	struct ipu_dmabuf_attachment *attach;
++
++	struct scatterlist *rd, *wr;
++	struct sg_table *sgt;
++	int ret, i;
++
++	attach = kzalloc(sizeof(*attach), GFP_KERNEL);
++	if (!attach)
++		return -ENOMEM;
++
++	sgt = &attach->sgt;
++
++	ret = sg_alloc_table(sgt, dinfo->sgt_base->orig_nents, GFP_KERNEL);
++	if (ret) {
++		kfree(attach);
++		return -ENOMEM;
++	}
++
++	rd = dinfo->sgt_base->sgl;
++	wr = sgt->sgl;
++
++	for (i = 0; i < sgt->orig_nents; ++i) {
++		sg_set_page(wr, sg_page(rd), rd->length, rd->offset);
++		rd = sg_next(rd);
++		wr = sg_next(wr);
++	}
++
++	attach->dma_dir = DMA_NONE;
++
++	dbuf_attach->priv = attach;
++
++	return 0;
++}
++
++#ifndef CONFIG_VIDEO_V4L2
++__weak int is_dma_buf_file(struct file *);
++
++struct dma_buf_list {
++	struct list_head head;
++	struct mutex lock;
++};
++
++static struct dma_buf_list db_list;
++
++__weak int dma_buf_release(struct inode *inode, struct file *file)
++{
++	struct dma_buf *dmabuf;
++
++	if (!is_dma_buf_file(file))
++		return -EINVAL;
++
++	dmabuf = file->private_data;
++
++	BUG_ON(dmabuf->vmapping_counter);
++
++	dmabuf->ops->release(dmabuf);
++
++	mutex_lock(&db_list.lock);
++	list_del(&dmabuf->list_node);
++	mutex_unlock(&db_list.lock);
++
++	kfree(dmabuf);
++	return 0;
++}
++
++__weak int dma_buf_mmap_internal(struct file *file, struct vm_area_struct *vma)
++{
++	struct dma_buf *dmabuf;
++
++	if (!is_dma_buf_file(file))
++		return -EINVAL;
++
++	dmabuf = file->private_data;
++
++	/* check for overflowing the buffer's size */
++	if (vma->vm_pgoff + ((vma->vm_end - vma->vm_start) >> PAGE_SHIFT) >
++	    dmabuf->size >> PAGE_SHIFT)
++		return -EINVAL;
++
++	return dmabuf->ops->mmap(dmabuf, vma);
++}
++
++static const struct file_operations dma_buf_fops = {
++	.release	= dma_buf_release,
++	.mmap		= dma_buf_mmap_internal,
++};
++
++/*
++ * is_dma_buf_file - Check if struct file* is associated with dma_buf
++ */
++__weak int is_dma_buf_file(struct file *file)
++{
++	return file->f_op == &dma_buf_fops;
++}
++
++/**
++ * dma_buf_export_named - Creates a new dma_buf, and associates an anon file
++ * with this buffer, so it can be exported.
++ * Also connect the allocator specific data and ops to the buffer.
++ * Additionally, provide a name string for exporter; useful in debugging.
++ *
++ * @priv:	[in]	Attach private data of allocator to this buffer
++ * @ops:	[in]	Attach allocator-defined dma buf ops to the new buffer.
++ * @size:	[in]	Size of the buffer
++ * @flags:	[in]	mode flags for the file.
++ * @exp_name:	[in]	name of the exporting module - useful for debugging.
++ *
++ * Returns, on success, a newly created dma_buf object, which wraps the
++ * supplied private data and operations for dma_buf_ops. On either missing
++ * ops, or error in allocating struct dma_buf, will return negative error.
++ *
++ */
++__weak struct dma_buf *dma_buf_export_named(void *priv, const struct dma_buf_ops *ops,
++				size_t size, int flags, const char *exp_name)
++{
++	struct dma_buf *dmabuf;
++	struct file *file;
++
++	if (WARN_ON(!priv || !ops
++			  || !ops->map_dma_buf
++			  || !ops->unmap_dma_buf
++			  || !ops->release
++			  || !ops->kmap_atomic
++			  || !ops->kmap
++			  || !ops->mmap)) {
++		return ERR_PTR(-EINVAL);
++	}
++
++	dmabuf = kzalloc(sizeof(struct dma_buf), GFP_KERNEL);
++	if (dmabuf == NULL)
++		return ERR_PTR(-ENOMEM);
++
++	dmabuf->priv = priv;
++	dmabuf->ops = ops;
++	dmabuf->size = size;
++	dmabuf->exp_name = exp_name;
++
++	file = anon_inode_getfile("dmabuf", &dma_buf_fops, dmabuf, flags);
++
++	dmabuf->file = file;
++
++	mutex_init(&dmabuf->lock);
++	INIT_LIST_HEAD(&dmabuf->attachments);
++
++	mutex_lock(&db_list.lock);
++	list_add(&dmabuf->list_node, &db_list.head);
++	mutex_unlock(&db_list.lock);
++
++	return dmabuf;
++}
++
++__weak int dma_buf_fd(struct dma_buf *dmabuf, int flags)
++{
++	int fd;
++
++	if (!dmabuf || !dmabuf->file)
++		return -EINVAL;
++
++	fd = get_unused_fd_flags(flags);
++	if (fd < 0)
++		return fd;
++
++	fd_install(fd, dmabuf->file);
++
++	return fd;
++}
++
++__weak struct dma_buf *dma_buf_get(int fd)
++{
++	struct file *file;
++
++	file = fget(fd);
++
++	if (!file)
++		return ERR_PTR(-EBADF);
++
++	if (!is_dma_buf_file(file)) {
++		fput(file);
++		return ERR_PTR(-EINVAL);
++	}
++
++	return file->private_data;
++}
++
++__weak void dma_buf_put(struct dma_buf *dmabuf)
++{
++	if (WARN_ON(!dmabuf || !dmabuf->file))
++		return;
++
++	fput(dmabuf->file);
++}
++
++/**
++ * dma_buf_attach - Add the device to dma_buf's attachments list; optionally,
++ * calls attach() of dma_buf_ops to allow device-specific attach functionality
++ * @dmabuf:	[in]	buffer to attach device to.
++ * @dev:	[in]	device to be attached.
++ *
++ * Returns struct dma_buf_attachment * for this attachment; may return negative
++ * error codes.
++ *
++ */
++__weak struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf,
++					  struct device *dev)
++{
++	struct dma_buf_attachment *attach;
++	int ret;
++
++	if (WARN_ON(!dmabuf || !dev))
++		return ERR_PTR(-EINVAL);
++
++	attach = kzalloc(sizeof(struct dma_buf_attachment), GFP_KERNEL);
++	if (attach == NULL)
++		return ERR_PTR(-ENOMEM);
++
++	attach->dev = dev;
++	attach->dmabuf = dmabuf;
++
++	mutex_lock(&dmabuf->lock);
++
++	if (dmabuf->ops->attach) {
++		ret = dmabuf->ops->attach(dmabuf, dev, attach);
++		if (ret)
++			goto err_attach;
++	}
++	list_add(&attach->node, &dmabuf->attachments);
++
++	mutex_unlock(&dmabuf->lock);
++	return attach;
++
++err_attach:
++	kfree(attach);
++	mutex_unlock(&dmabuf->lock);
++	return ERR_PTR(ret);
++}
++
++__weak void dma_buf_detach(struct dma_buf *dmabuf, struct dma_buf_attachment *attach)
++{
++	if (WARN_ON(!dmabuf || !attach))
++		return;
++
++	mutex_lock(&dmabuf->lock);
++	list_del(&attach->node);
++	if (dmabuf->ops->detach)
++		dmabuf->ops->detach(dmabuf, attach);
++
++	mutex_unlock(&dmabuf->lock);
++	kfree(attach);
++}
++
++/**
++ * dma_buf_map_attachment - Returns the scatterlist table of the attachment;
++ * mapped into _device_ address space. Is a wrapper for map_dma_buf() of the
++ * dma_buf_ops.
++ * @attach:	[in]	attachment whose scatterlist is to be returned
++ * @direction:	[in]	direction of DMA transfer
++ *
++ * Returns sg_table containing the scatterlist to be returned; may return NULL
++ * or ERR_PTR.
++ *
++ */
++__weak struct sg_table *dma_buf_map_attachment(struct dma_buf_attachment *attach,
++					enum dma_data_direction direction)
++{
++	struct sg_table *sg_table = ERR_PTR(-EINVAL);
++
++	might_sleep();
++
++	if (WARN_ON(!attach || !attach->dmabuf))
++		return ERR_PTR(-EINVAL);
++
++	sg_table = attach->dmabuf->ops->map_dma_buf(attach, direction);
++
++	return sg_table;
++}
++
++/**
++ * dma_buf_unmap_attachment - unmaps and decreases usecount of the buffer;might
++ * deallocate the scatterlist associated. Is a wrapper for unmap_dma_buf() of
++ * dma_buf_ops.
++ * @attach:	[in]	attachment to unmap buffer from
++ * @sg_table:	[in]	scatterlist info of the buffer to unmap
++ * @direction:  [in]    direction of DMA transfer
++ *
++ */
++__weak void dma_buf_unmap_attachment(struct dma_buf_attachment *attach,
++				struct sg_table *sg_table,
++				enum dma_data_direction direction)
++{
++	might_sleep();
++
++	if (WARN_ON(!attach || !attach->dmabuf || !sg_table))
++		return;
++
++	attach->dmabuf->ops->unmap_dma_buf(attach, sg_table,
++						direction);
++}
++#endif
++
++static void ipu_dmabuf_detach(struct dma_buf *dbuf,
++			      struct dma_buf_attachment *db_attach)
++{
++	struct ipu_dmabuf_attachment *attach = db_attach->priv;
++	struct sg_table *sgt;
++
++	if (!attach)
++		return;
++
++	sgt = &attach->sgt;
++
++	/* release the scatterlist cache */
++	if (attach->dma_dir != DMA_NONE)
++		dma_unmap_sg(db_attach->dev, sgt->sgl, sgt->orig_nents,
++			     attach->dma_dir);
++
++	sg_free_table(sgt);
++	kfree(attach);
++	db_attach->priv = NULL;
++}
++
++static struct sg_table *ipu_dmabuf_map(struct dma_buf_attachment *db_attach,
++				       enum dma_data_direction dma_dir)
++{
++	struct ipu_dmabuf_attachment *attach = db_attach->priv;
++	struct sg_table *sgt;
++	struct mutex *lock = &db_attach->dmabuf->lock;
++
++	mutex_lock(lock);
++
++	sgt = &attach->sgt;
++
++	if (attach->dma_dir == dma_dir) {
++		mutex_unlock(lock);
++		return sgt;
++	}
++
++	if (attach->dma_dir != DMA_NONE) {
++		dma_unmap_sg(db_attach->dev, sgt->sgl, sgt->orig_nents,
++			     attach->dma_dir);
++		attach->dma_dir = DMA_NONE;
++	}
++
++	sgt->nents = dma_map_sg(db_attach->dev, sgt->sgl, sgt->orig_nents,
++				dma_dir);
++
++	if (!sgt->nents) {
++		pr_err("failed to map scatterlist\n");
++		mutex_unlock(lock);
++		return ERR_PTR(-EIO);
++	}
++
++	attach->dma_dir = dma_dir;
++
++	mutex_unlock(lock);
++
++	return sgt;
++}
++
++static void ipu_dmabuf_unmap(struct dma_buf_attachment *at,
++			     struct sg_table *sg, enum dma_data_direction dir)
++{
++}
++
++static int ipu_dmabuf_mmap(struct dma_buf *buf, struct vm_area_struct *vma)
++{
++	struct ipu_dmabuf_priv *dinfo = buf->priv;
++	unsigned long start = vma->vm_start;
++	unsigned long vsize = vma->vm_end - start;
++	struct ipu_dma_buffer *buffer = dinfo->buffer;
++	int ret;
++
++	if (!dinfo) {
++		pr_err("No buffer to map\n");
++		return -EINVAL;
++	}
++
++	vma->vm_pgoff = 0;
++
++	ret = dma_mmap_coherent(dinfo->dev, vma, buffer->cpu_handle,
++				buffer->dma_handle, vsize);
++
++	if (ret < 0) {
++		pr_err("Remapping memory failed, error: %d\n", ret);
++		return ret;
++	}
++
++	vma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP;
++
++	return 0;
++}
++
++static void ipu_dmabuf_release(struct dma_buf *buf)
++{
++	struct ipu_dmabuf_priv *dinfo = buf->priv;
++	struct ipu_dma_buffer *buffer = dinfo->buffer;
++
++	if (dinfo->sgt_base) {
++		sg_free_table(dinfo->sgt_base);
++		kfree(dinfo->sgt_base);
++	}
++
++	dma_free_coherent(dinfo->dev, buffer->size, buffer->cpu_handle,
++			  buffer->dma_handle);
++
++	put_device(dinfo->dev);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,10, 0)
++	kfree_sensitive(buffer);
++#else
++	kzfree(buffer);
++#endif
++	kfree(dinfo);
++}
++
++static void *ipu_dmabuf_kmap(struct dma_buf *dmabuf, unsigned long page_num)
++{
++	struct ipu_dmabuf_priv *dinfo = dmabuf->priv;
++	void *vaddr = dinfo->buffer->cpu_handle;
++
++	return vaddr + page_num * PAGE_SIZE;
++}
++
++static void *ipu_dmabuf_vmap(struct dma_buf *dbuf)
++{
++	struct ipu_dmabuf_priv *dinfo = dbuf->priv;
++	void *vaddr = dinfo->buffer->cpu_handle;
++
++	return vaddr;
++}
++
++static const struct dma_buf_ops ipu_dmabuf_ops = {
++	.attach		= ipu_dmabuf_attach,
++	.detach		= ipu_dmabuf_detach,
++	.map_dma_buf	= ipu_dmabuf_map,
++	.unmap_dma_buf	= ipu_dmabuf_unmap,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)
++/* the map_atomic interface was removed after 4.19 */
++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,10, 0)
++	.map_atomic	= ipu_dmabuf_kmap,
++	.map		= ipu_dmabuf_kmap,
++#endif
++#else
++	.kmap_atomic	= ipu_dmabuf_kmap,
++	.kmap		= ipu_dmabuf_kmap,
++#endif
++	.vmap		= ipu_dmabuf_vmap,
++	.mmap		= ipu_dmabuf_mmap,
++	.release	= ipu_dmabuf_release,
++};
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)
++static void define_export_info(struct dma_buf_export_info *exp_info, int size, void *priv)
++{
++	exp_info->owner = THIS_MODULE;
++	exp_info->exp_name = KBUILD_MODNAME;
++	exp_info->ops = &ipu_dmabuf_ops;
++	exp_info->flags = O_RDWR;
++	exp_info->resv = NULL;
++	exp_info->size = size;
++	exp_info->priv = priv;
++}
++#endif
++
++static struct sg_table *ipu_get_base_sgt(struct ipu_dmabuf_priv *dinfo)
++{
++	int ret;
++	struct sg_table *sgt;
++	struct ipu_dma_buffer *buf = dinfo->buffer;
++	struct device *dev = dinfo->dev;
++
++	sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
++	if (!sgt)
++		return NULL;
++
++	ret = dma_get_sgtable(dev, sgt, buf->cpu_handle, buf->dma_handle,
++			      buf->size);
++	if (ret < 0) {
++		kfree(sgt);
++		return NULL;
++	}
++
++	return sgt;
++
++}
++
++static struct dma_buf *ipu_get_dmabuf(void *dma_info_priv)
++{
++	struct dma_buf *dbuf;
++	struct ipu_dmabuf_priv *dinfo = dma_info_priv;
++	struct ipu_dma_buffer *buf = dinfo->buffer;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)
++	struct dma_buf_export_info exp_info;
++#endif
++
++	if (!dinfo->sgt_base)
++		dinfo->sgt_base = ipu_get_base_sgt(dinfo);
++
++	if (WARN_ON(!dinfo->sgt_base))
++		return NULL;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)
++	define_export_info(&exp_info, buf->size, (void *)dinfo);
++	dbuf = dma_buf_export(&exp_info);
++	if (IS_ERR(dbuf)) {
++		pr_err("couldn't export dma buf\n");
++		return NULL;
++	}
++#else
++	dbuf = dma_buf_export((void *)dinfo, &ipu_dmabuf_ops, buf->size, O_RDWR);
++	if (IS_ERR(buf)) {
++		pr_err("couldn't export dma buf\n");
++		return NULL;
++	}
++#endif
++	return dbuf;
++}
++
++static void *ipu_dmabuf_wrap(struct device *dev, unsigned long size,
++			     struct ipu_dma_buffer *buffer)
++{
++	struct ipu_dmabuf_priv *dinfo;
++	struct dma_buf *dbuf;
++
++	dinfo = kzalloc(sizeof(*dinfo), GFP_KERNEL);
++	if (!dinfo)
++		return ERR_PTR(-ENOMEM);
++
++	dinfo->dev = get_device(dev);
++	dinfo->buffer = buffer;
++	dinfo->dma_dir = DMA_BIDIRECTIONAL;
++	dinfo->sgt_base = ipu_get_base_sgt(dinfo);
++
++	dbuf = ipu_get_dmabuf(dinfo);
++	if (IS_ERR_OR_NULL(dbuf))
++		return ERR_PTR(-EINVAL);
++
++	return dbuf;
++}
++
++int ipu_create_dmabuf_fd(struct device *dev, unsigned long size,
++			 struct ipu_dma_buffer *buffer)
++{
++	struct dma_buf *dbuf = ipu_dmabuf_wrap(dev, size, buffer);
++
++	if (IS_ERR(dbuf))
++		return PTR_ERR(dbuf);
++	return dma_buf_fd(dbuf, O_RDWR);
++}
++
++int ipu_allocate_dmabuf(struct device *dev, int size, u32 *fd)
++{
++	struct ipu_dma_buffer *buffer;
++
++	buffer = ipu_alloc_dma(dev, size);
++	if (!buffer) {
++		dev_err(dev, "Can't alloc DMA buffer\n");
++		return -ENOMEM;
++	}
++
++	*fd = ipu_create_dmabuf_fd(dev, size, buffer);
++	return 0;
++}
++
++int ipu_dmabuf_get_address(struct device *dev, u32 fd, u32 *bus_address)
++{
++	struct dma_buf *dbuf;
++	struct dma_buf_attachment *attach;
++	struct sg_table *sgt;
++	int err = 0;
++
++	dbuf = dma_buf_get(fd);
++	if (IS_ERR(dbuf))
++		return -EINVAL;
++	attach = dma_buf_attach(dbuf, dev);
++	if (IS_ERR(attach)) {
++		err = -EINVAL;
++		goto fail_attach;
++	}
++	sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
++	if (IS_ERR(sgt)) {
++		err = -EINVAL;
++		goto fail_map;
++	}
++
++	*bus_address = sg_dma_address(sgt->sgl);
++
++	dma_buf_unmap_attachment(attach, sgt, DMA_BIDIRECTIONAL);
++fail_map:
++	dma_buf_detach(dbuf, attach);
++fail_attach:
++	dma_buf_put(dbuf);
++	return err;
++}
++
++int ipu_ioctl_get_dma_fd(struct device *dev, unsigned long arg)
++{
++	struct ipu_dma_info info;
++	int err;
++
++	if (copy_from_user(&info, (struct ipu_dma_info *)arg, sizeof(info)))
++		return -EFAULT;
++
++	err = ipu_allocate_dmabuf(dev, info.size, &info.fd);
++	if (err)
++		return err;
++
++	err = ipu_dmabuf_get_address(dev, info.fd, &info.phy_addr);
++	if (err)
++		return err;
++
++	if (copy_to_user((void *)arg, &info, sizeof(info)))
++		return -EFAULT;
++
++	return 0;
++}
++
++int ipu_ioctl_get_dmabuf_dma_addr(struct device *dev, unsigned long arg)
++{
++	struct ipu_dma_info info;
++	int err;
++
++	if (copy_from_user(&info, (struct ipu_dma_info *)arg, sizeof(info)))
++		return -EFAULT;
++
++	err = ipu_dmabuf_get_address(dev, info.fd, &info.phy_addr);
++	if (err)
++		return err;
++
++	if (copy_to_user((void *)arg, &info, sizeof(info)))
++		return -EFAULT;
++
++	return 0;
++}
+diff --git a/module_drivers/drivers/video/ingenic_ipu/ipu_dmabuf.h b/module_drivers/drivers/video/ingenic_ipu/ipu_dmabuf.h
+new file mode 100644
+index 000000000..280a82f7b
+--- /dev/null
++++ b/module_drivers/drivers/video/ingenic_ipu/ipu_dmabuf.h
+@@ -0,0 +1,22 @@
++#include <linux/device.h>
++
++struct ipu_dma_buffer {
++	u32 size;
++	dma_addr_t dma_handle;
++	void *cpu_handle;
++};
++
++struct ipu_buffer_info {
++	u32 bus_address;
++	u32 size;
++};
++
++struct ipu_dma_info {
++    __u32 fd;
++    __u32 size;
++    __u32 phy_addr;
++};
++
++
++int ipu_ioctl_get_dma_fd(struct device *dev, unsigned long arg);
++int ipu_ioctl_get_dmabuf_dma_addr(struct device *dev, unsigned long arg);
+diff --git a/module_drivers/drivers/video/logo-ingenic/.gitignore b/module_drivers/drivers/video/logo-ingenic/.gitignore
+new file mode 100644
+index 000000000..c13fd5203
+--- /dev/null
++++ b/module_drivers/drivers/video/logo-ingenic/.gitignore
+@@ -0,0 +1 @@
++logo.c
+diff --git a/module_drivers/drivers/video/logo-ingenic/Kconfig b/module_drivers/drivers/video/logo-ingenic/Kconfig
+new file mode 100644
+index 000000000..38a766ac7
+--- /dev/null
++++ b/module_drivers/drivers/video/logo-ingenic/Kconfig
+@@ -0,0 +1,19 @@
++
++menuconfig TRUE_COLOR_LOGO
++       bool "True Color Logo for Ingenic"
++       depends on LOGO
++       default n
++
++config TRUE_COLOR_LOGO_FILE
++       string "Logo File"
++       depends on TRUE_COLOR_LOGO
++       default "module_drivers/drivers/video/logo-ingenic/logo.png"
++       help
++         set a picture file, support png, jpg, bmp.
++
++config TRUE_COLOR_LOGO_BACKGROUND
++       hex "Background Color"
++       depends on TRUE_COLOR_LOGO
++       default '0x00ffffff'
++       help
++         set default background color.
+diff --git a/module_drivers/drivers/video/logo-ingenic/Makefile b/module_drivers/drivers/video/logo-ingenic/Makefile
+new file mode 100644
+index 000000000..6d08d2a7a
+--- /dev/null
++++ b/module_drivers/drivers/video/logo-ingenic/Makefile
+@@ -0,0 +1,4 @@
++# Makefile for true color logo.
++
++obj-y	+= logo.o
++obj-y	+= showlogo.o
+diff --git a/module_drivers/drivers/video/logo-ingenic/logo.c b/module_drivers/drivers/video/logo-ingenic/logo.c
+new file mode 100644
+index 000000000..c072863d9
+--- /dev/null
++++ b/module_drivers/drivers/video/logo-ingenic/logo.c
+@@ -0,0 +1,943 @@
++/*
++ * Automatically generated by "mklogo"
++ *
++ * DO NOT EDIT
++ *
++ */
++
++#include <linux/init.h>
++#include <video/ingenic_logo.h>
++
++extern unsigned char logo_buf_initdata[];
++
++struct _logo_info logo_info = {
++	134,
++	55,
++	32,
++	NULL,
++	0xffffffff,
++};
++
++unsigned char logo_buf_initdata[] __initdata = {
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xC7, 0x55, 0x01, 0xFF, 0xC7, 0x56, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC7, 0x56, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC7, 0x56, 0x00, 0xFF,
++ 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF,
++ 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF,
++ 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF,
++ 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF,
++ 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF,
++ 0xC9, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x01, 0xFF, 0xC8, 0x54, 0x00, 0xFF, 0xC7, 0x56, 0x00, 0xFF, 0xD6, 0x7F, 0x3F, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFD, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFB, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFB, 0xFF, 0xFC, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC7, 0x55, 0x01, 0xFF,
++ 0xC7, 0x56, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC9, 0x55, 0x01, 0xFF, 0xC7, 0x56, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC7, 0x56, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF,
++ 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF,
++ 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF,
++ 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF,
++ 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF,
++ 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC8, 0x54, 0x00, 0xFF, 0xC8, 0x54, 0x00, 0xFF,
++ 0xC7, 0x56, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xCB, 0x74, 0x34, 0xFF, 0xDC, 0xDC, 0xDC, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xEE, 0xCA, 0xB2, 0xFF,
++ 0xDF, 0x9D, 0x6D, 0xFF, 0xFB, 0xF7, 0xF2, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFD, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC5, 0x55, 0x01, 0xFF, 0xC7, 0x56, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF,
++ 0xC7, 0x55, 0x01, 0xFF, 0xC7, 0x56, 0x00, 0xFF, 0xC9, 0x55, 0x00, 0xFF, 0xC7, 0x55, 0x01, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF,
++ 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF,
++ 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF,
++ 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF,
++ 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF,
++ 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC7, 0x55, 0x01, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF,
++ 0xCB, 0x74, 0x34, 0xFF, 0xDC, 0xDC, 0xDC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xF3, 0xDC, 0xCC, 0xFF, 0xE0, 0x9F, 0x72, 0xFF, 0xE0, 0xA1, 0x6E, 0xFF, 0xE0, 0x9E, 0x6E, 0xFF, 0xE0, 0x9E, 0x6E, 0xFF, 0xE3, 0x9F, 0x70, 0xFF,
++ 0xDD, 0xA0, 0x6E, 0xFF, 0xDF, 0x9F, 0x6F, 0xFF, 0xDE, 0x9E, 0x6E, 0xFF, 0xDF, 0x9F, 0x6F, 0xFF, 0xE1, 0xA0, 0x6D, 0xFF, 0xE1, 0x9F, 0x6E, 0xFF, 0xDE, 0xA1, 0x6F, 0xFF, 0xDF, 0x9F, 0x6F, 0xFF,
++ 0xE1, 0x9E, 0x71, 0xFF, 0xE0, 0x9E, 0x6E, 0xFF, 0xDD, 0xA0, 0x6E, 0xFF, 0xE1, 0x9F, 0x6E, 0xFF, 0xDE, 0x9E, 0x6E, 0xFF, 0xC9, 0x5C, 0x07, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xCA, 0x69, 0x1F, 0xFF,
++ 0xF3, 0xDC, 0xCC, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFC, 0xFF, 0xFD, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFC, 0xFE, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFA, 0xF4, 0xED, 0xFF, 0xD6, 0x87, 0x4E, 0xFF, 0xEC, 0xC6, 0xA8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC5, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC4, 0x55, 0x00, 0xFF,
++ 0xC6, 0x55, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF,
++ 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF,
++ 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF,
++ 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF,
++ 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF,
++ 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC5, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xCA, 0x73, 0x35, 0xFF, 0xDC, 0xDC, 0xDC, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFE, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xE4, 0xA8, 0x7E, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC2, 0x55, 0x00, 0xFF, 0xC2, 0x55, 0x00, 0xFF, 0xC7, 0x56, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x02, 0xFF, 0xC5, 0x54, 0x00, 0xFF,
++ 0xC8, 0x54, 0x00, 0xFF, 0xC4, 0x55, 0x00, 0xFF, 0xC5, 0x56, 0x00, 0xFF, 0xC5, 0x52, 0x02, 0xFF, 0xC8, 0x53, 0x02, 0xFF, 0xC4, 0x55, 0x00, 0xFF, 0xC3, 0x54, 0x00, 0xFF, 0xC7, 0x55, 0x01, 0xFF,
++ 0xC5, 0x54, 0x00, 0xFF, 0xC6, 0x53, 0x02, 0xFF, 0xC4, 0x55, 0x00, 0xFF, 0xC3, 0x54, 0x00, 0xFF, 0xC7, 0x54, 0x03, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC6, 0x5D, 0x0E, 0xFF, 0xF8, 0xF6, 0xF5, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF,
++ 0xFB, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFE, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFE, 0xFB, 0xF7, 0xFF, 0xD5, 0x7D, 0x3D, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC2, 0x56, 0x04, 0xFF, 0xE4, 0xC5, 0xB0, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC3, 0x53, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF,
++ 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF,
++ 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF,
++ 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF,
++ 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF,
++ 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF,
++ 0xC4, 0x54, 0x00, 0xFF, 0xC3, 0x53, 0x00, 0xFF, 0xC4, 0x55, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC8, 0x73, 0x35, 0xFF, 0xDA, 0xDC, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFA, 0xFA, 0xFF, 0xCD, 0x81, 0x4C, 0xFF,
++ 0xC7, 0x58, 0x08, 0xFF, 0xCB, 0x72, 0x2F, 0xFF, 0xC6, 0x7C, 0x42, 0xFF, 0xCA, 0x84, 0x4F, 0xFF, 0xC9, 0x83, 0x4E, 0xFF, 0xC4, 0x67, 0x1C, 0xFF, 0xC3, 0x53, 0x00, 0xFF, 0xC7, 0x52, 0x01, 0xFF,
++ 0xC5, 0x60, 0x11, 0xFF, 0xCB, 0x84, 0x52, 0xFF, 0xCB, 0x81, 0x51, 0xFF, 0xC7, 0x84, 0x4D, 0xFF, 0xCA, 0x84, 0x4E, 0xFF, 0xC8, 0x84, 0x4F, 0xFF, 0xCB, 0x82, 0x4E, 0xFF, 0xC7, 0x82, 0x50, 0xFF,
++ 0xC8, 0x70, 0x30, 0xFF, 0xC4, 0x55, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC3, 0x53, 0x00, 0xFF, 0xCD, 0xA3, 0x80, 0xFF, 0xD4, 0xD4, 0xD4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xF4, 0xE8, 0xDE, 0xFF, 0xE2, 0xAB, 0x80, 0xFF, 0xE1, 0xAA, 0x7F, 0xFF, 0xE3, 0xA9, 0x7F, 0xFF, 0xDE, 0xA8, 0x7F, 0xFF, 0xDF, 0xAA, 0x7F, 0xFF, 0xE1, 0xAA, 0x7F, 0xFF, 0xE1, 0xA9, 0x80, 0xFF,
++ 0xE1, 0xAA, 0x7F, 0xFF, 0xE1, 0xAA, 0x7F, 0xFF, 0xE1, 0xAA, 0x7F, 0xFF, 0xE1, 0xAA, 0x7F, 0xFF, 0xE1, 0xA9, 0x80, 0xFF, 0xE1, 0xA9, 0x80, 0xFF, 0xE0, 0xA9, 0x7E, 0xFF, 0xE3, 0xA9, 0x7F, 0xFF,
++ 0xDF, 0xAA, 0x7F, 0xFF, 0xE3, 0xA8, 0x80, 0xFF, 0xE3, 0xA9, 0x7F, 0xFF, 0xE1, 0xA8, 0x81, 0xFF, 0xE3, 0xAA, 0x7D, 0xFF, 0xDF, 0xA9, 0x80, 0xFF, 0xD2, 0x81, 0x44, 0xFF, 0xC4, 0x54, 0x00, 0xFF,
++ 0xC4, 0x52, 0x00, 0xFF, 0xC5, 0x55, 0x01, 0xFF, 0xC5, 0x5C, 0x0D, 0xFF, 0xE8, 0xD8, 0xC7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC3, 0x53, 0x00, 0xFF,
++ 0xC3, 0x53, 0x00, 0xFF, 0xC3, 0x53, 0x00, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC1, 0x54, 0x00, 0xFF, 0xC3, 0x53, 0x00, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF,
++ 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF,
++ 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF,
++ 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF,
++ 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF,
++ 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x00, 0xFF, 0xC4, 0x54, 0x02, 0xFF,
++ 0xC3, 0x53, 0x00, 0xFF, 0xC2, 0x52, 0x00, 0xFF, 0xC7, 0x72, 0x34, 0xFF, 0xDB, 0xDD, 0xDE, 0xFF, 0xFD, 0xFD, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xDE, 0xE0, 0xE0, 0xFF, 0xD2, 0xD1, 0xD3, 0xFF,
++ 0xDD, 0xDB, 0xDB, 0xFF, 0xE0, 0xDF, 0xE1, 0xFF, 0xE0, 0xE2, 0xE2, 0xFF, 0xCD, 0x82, 0x4E, 0xFF, 0xC0, 0x53, 0x00, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC9, 0x7A, 0x41, 0xFF, 0xD7, 0xD5, 0xD4, 0xFF,
++ 0xE2, 0xE1, 0xE3, 0xFF, 0xE2, 0xE2, 0xE2, 0xFF, 0xE5, 0xE1, 0xE6, 0xFF, 0xE1, 0xE0, 0xE2, 0xFF, 0xE5, 0xE2, 0xE4, 0xFF, 0xE2, 0xE2, 0xE2, 0xFF, 0xD7, 0xAB, 0x8C, 0xFF, 0xC3, 0x53, 0x00, 0xFF,
++ 0xBE, 0x54, 0x01, 0xFF, 0xC6, 0x53, 0x02, 0xFF, 0xD3, 0xD1, 0xD0, 0xFF, 0xED, 0xED, 0xED, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFB, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xE5, 0xB7, 0x95, 0xFF, 0xC3, 0x53, 0x01, 0xFF,
++ 0xC6, 0x52, 0x00, 0xFF, 0xC3, 0x52, 0x02, 0xFF, 0xC1, 0x54, 0x00, 0xFF, 0xC2, 0x52, 0x00, 0xFF, 0xC6, 0x54, 0x00, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC2, 0x52, 0x00, 0xFF, 0xC3, 0x53, 0x00, 0xFF,
++ 0xBF, 0x54, 0x00, 0xFF, 0xC2, 0x52, 0x00, 0xFF, 0xC1, 0x54, 0x00, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x00, 0xFF, 0xC1, 0x54, 0x00, 0xFF, 0xC6, 0x53, 0x02, 0xFF, 0xC0, 0x52, 0x00, 0xFF,
++ 0xC5, 0x53, 0x00, 0xFF, 0xC6, 0x55, 0x00, 0xFF, 0xC3, 0x53, 0x00, 0xFF, 0xC3, 0x54, 0x00, 0xFF, 0xC1, 0x54, 0x00, 0xFF, 0xC2, 0x52, 0x00, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC2, 0x53, 0x00, 0xFF,
++ 0xC7, 0x52, 0x01, 0xFF, 0xC7, 0x62, 0x17, 0xFF, 0xF2, 0xF4, 0xF4, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF,
++ 0xC3, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF,
++ 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF,
++ 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF,
++ 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF,
++ 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF,
++ 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xC2, 0x52, 0x00, 0xFF, 0xC0, 0x53, 0x00, 0xFF, 0xC1, 0x53, 0x01, 0xFF,
++ 0xC7, 0x71, 0x35, 0xFF, 0xD9, 0xDB, 0xDC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xD4, 0x81, 0x49, 0xFF, 0xC3, 0x54, 0x00, 0xFF, 0xC1, 0x54, 0x00, 0xFF, 0xC7, 0x81, 0x4C, 0xFF, 0xDD, 0xDF, 0xDF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE8, 0xBF, 0x9F, 0xFF, 0xC1, 0x54, 0x00, 0xFF, 0xC3, 0x54, 0x00, 0xFF, 0xC4, 0x51, 0x00, 0xFF,
++ 0xCF, 0xD1, 0xD1, 0xFF, 0xFD, 0xFD, 0xFD, 0xFF, 0xD8, 0x99, 0x67, 0xFF, 0xD6, 0x93, 0x62, 0xFF, 0xFF, 0xFD, 0xFC, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFD, 0xFF, 0xCE, 0x8A, 0x55, 0xFF, 0xC3, 0x55, 0x03, 0xFF, 0xC2, 0x69, 0x26, 0xFF,
++ 0xC7, 0x74, 0x3C, 0xFF, 0xC7, 0x7B, 0x40, 0xFF, 0xC6, 0x78, 0x43, 0xFF, 0xC9, 0x7A, 0x41, 0xFF, 0xC6, 0x7B, 0x43, 0xFF, 0xC8, 0x79, 0x40, 0xFF, 0xC7, 0x7A, 0x41, 0xFF, 0xC9, 0x79, 0x42, 0xFF,
++ 0xC2, 0x59, 0x08, 0xFF, 0xC0, 0x53, 0x00, 0xFF, 0xC4, 0x54, 0x00, 0xFF, 0xC5, 0x62, 0x1E, 0xFF, 0xC5, 0x7B, 0x41, 0xFF, 0xC8, 0x7B, 0x42, 0xFF, 0xC5, 0x7A, 0x42, 0xFF, 0xC5, 0x7A, 0x42, 0xFF,
++ 0xC5, 0x7B, 0x41, 0xFF, 0xC7, 0x7A, 0x41, 0xFF, 0xC9, 0x79, 0x42, 0xFF, 0xC5, 0x7B, 0x41, 0xFF, 0xC7, 0x7A, 0x41, 0xFF, 0xC9, 0x7A, 0x41, 0xFF, 0xC5, 0x79, 0x44, 0xFF, 0xC9, 0x87, 0x57, 0xFF,
++ 0xD3, 0xD5, 0xD6, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xC0, 0x52, 0x00, 0xFF, 0xC0, 0x52, 0x00, 0xFF, 0xC0, 0x52, 0x00, 0xFF, 0xC1, 0x52, 0x02, 0xFF, 0xC0, 0x52, 0x00, 0xFF,
++ 0xC3, 0x53, 0x01, 0xFF, 0xC0, 0x52, 0x00, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF,
++ 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF,
++ 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF,
++ 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF,
++ 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF,
++ 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x53, 0x01, 0xFF, 0xC0, 0x52, 0x00, 0xFF, 0xC1, 0x52, 0x02, 0xFF, 0xC0, 0x52, 0x00, 0xFF, 0xC0, 0x52, 0x00, 0xFF, 0xC6, 0x70, 0x34, 0xFF, 0xDA, 0xDC, 0xDD, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF5, 0xE7, 0xDB, 0xFF, 0xF7, 0xDE, 0xCE, 0xFF, 0xEF, 0xDF, 0xCF, 0xFF,
++ 0xF3, 0xDE, 0xCF, 0xFF, 0xF5, 0xDD, 0xD1, 0xFF, 0xF5, 0xDE, 0xCF, 0xFF, 0xF3, 0xDF, 0xCE, 0xFF, 0xF5, 0xDD, 0xD1, 0xFF, 0xF1, 0xDE, 0xCF, 0xFF, 0xF3, 0xDF, 0xCE, 0xFF, 0xD0, 0x72, 0x30, 0xFF,
++ 0xC1, 0x53, 0x01, 0xFF, 0xC1, 0x52, 0x04, 0xFF, 0xC7, 0x7C, 0x48, 0xFF, 0xDA, 0xC8, 0xB7, 0xFF, 0xF1, 0xDE, 0xCF, 0xFF, 0xF3, 0xDE, 0xCF, 0xFF, 0xF3, 0xDF, 0xCE, 0xFF, 0xF1, 0xDE, 0xCF, 0xFF,
++ 0xF5, 0xDF, 0xCD, 0xFF, 0xF3, 0xDE, 0xCF, 0xFF, 0xE0, 0xAA, 0x81, 0xFF, 0xBF, 0x52, 0x04, 0xFF, 0xC0, 0x51, 0x03, 0xFF, 0xC3, 0x53, 0x01, 0xFF, 0xCA, 0xBA, 0xA9, 0xFF, 0xD7, 0x8E, 0x5C, 0xFF,
++ 0xC4, 0x51, 0x01, 0xFF, 0xC0, 0x52, 0x00, 0xFF, 0xD1, 0x94, 0x68, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFC, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFD, 0xFD, 0xFF, 0xE2, 0xDF, 0xDA, 0xFF, 0xD2, 0xD2, 0xD2, 0xFF, 0xDB, 0xD9, 0xD8, 0xFF, 0xDC, 0xDD, 0xE1, 0xFF,
++ 0xE0, 0xE0, 0xE0, 0xFF, 0xDD, 0xDF, 0xDF, 0xFF, 0xDD, 0xDF, 0xDF, 0xFF, 0xE0, 0xDF, 0xE1, 0xFF, 0xDF, 0xDF, 0xDF, 0xFF, 0xDD, 0xDF, 0xDF, 0xFF, 0xC7, 0x6B, 0x2A, 0xFF, 0xBE, 0x52, 0x01, 0xFF,
++ 0xC1, 0x52, 0x04, 0xFF, 0xC8, 0x8A, 0x5C, 0xFF, 0xDA, 0xD8, 0xD8, 0xFF, 0xDB, 0xDE, 0xE2, 0xFF, 0xE1, 0xDF, 0xDF, 0xFF, 0xDF, 0xDE, 0xE0, 0xFF, 0xDE, 0xE0, 0xE1, 0xFF, 0xE1, 0xDF, 0xDF, 0xFF,
++ 0xDF, 0xDF, 0xDF, 0xFF, 0xDD, 0xDF, 0xDF, 0xFF, 0xDF, 0xDF, 0xDF, 0xFF, 0xE0, 0xDF, 0xE1, 0xFF, 0xDD, 0xDF, 0xDF, 0xFF, 0xE1, 0xDF, 0xDF, 0xFF, 0xE4, 0xE3, 0xE5, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xBD, 0x51, 0x03, 0xFF, 0xC0, 0x51, 0x01, 0xFF, 0xC0, 0x51, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF,
++ 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF,
++ 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF,
++ 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF,
++ 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF,
++ 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF,
++ 0xBE, 0x52, 0x01, 0xFF, 0xC0, 0x51, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xC3, 0x71, 0x37, 0xFF, 0xDE, 0xDC, 0xDC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xF8, 0xE9, 0xE0, 0xFF, 0xC0, 0x51, 0x01, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBE, 0x51, 0x03, 0xFF, 0xC0, 0x51, 0x01, 0xFF, 0xC0, 0x51, 0x01, 0xFF,
++ 0xC0, 0x52, 0x00, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBE, 0x52, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xC1, 0x4F, 0x02, 0xFF, 0xC0, 0x53, 0x00, 0xFF, 0xC0, 0x51, 0x01, 0xFF, 0xBD, 0x50, 0x02, 0xFF,
++ 0xBE, 0x52, 0x01, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBE, 0x51, 0x03, 0xFF, 0xBF, 0x50, 0x02, 0xFF, 0xBF, 0x50, 0x00, 0xFF, 0xC0, 0x52, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xC0, 0x51, 0x03, 0xFF,
++ 0xC0, 0x51, 0x01, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBE, 0x51, 0x03, 0xFF, 0xC2, 0x52, 0x00, 0xFF, 0xBE, 0x52, 0x00, 0xFF, 0xBE, 0x52, 0x00, 0xFF, 0xC0, 0x51, 0x01, 0xFF, 0xC0, 0x51, 0x03, 0xFF,
++ 0xBF, 0x50, 0x00, 0xFF, 0xD7, 0xB0, 0x94, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xCB, 0x72, 0x2F, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBD, 0x51, 0x03, 0xFF, 0xC9, 0x88, 0x5C, 0xFF,
++ 0xE3, 0xE5, 0xE6, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBC, 0x50, 0x02, 0xFF,
++ 0xBE, 0x52, 0x01, 0xFF, 0xBF, 0x50, 0x00, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF,
++ 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF,
++ 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF,
++ 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF,
++ 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF,
++ 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBD, 0x51, 0x00, 0xFF,
++ 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xC2, 0x70, 0x36, 0xFF, 0xDC, 0xDC, 0xDC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xDA, 0x97, 0x6A, 0xFF, 0xBC, 0x51, 0x00, 0xFF, 0xC0, 0x51, 0x01, 0xFF, 0xBC, 0x51, 0x00, 0xFF, 0xBC, 0x51, 0x00, 0xFF, 0xBF, 0x50, 0x00, 0xFF, 0xBB, 0x52, 0x01, 0xFF,
++ 0xBD, 0x51, 0x00, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xBD, 0x51, 0x03, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBE, 0x51, 0x03, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xC0, 0x51, 0x01, 0xFF,
++ 0xBE, 0x51, 0x03, 0xFF, 0xBC, 0x51, 0x00, 0xFF, 0xBE, 0x52, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBC, 0x51, 0x00, 0xFF, 0xBC, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x03, 0xFF, 0xC0, 0x51, 0x01, 0xFF,
++ 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x52, 0x01, 0xFF, 0xBE, 0x51, 0x03, 0xFF, 0xBF, 0x50, 0x02, 0xFF, 0xBC, 0x51, 0x00, 0xFF, 0xBE, 0x52, 0x00, 0xFF, 0xBE, 0x52, 0x01, 0xFF, 0xC8, 0x89, 0x5D, 0xFF,
++ 0xED, 0xEE, 0xEC, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFC, 0xFF, 0xFD, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFC, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF,
++ 0xFD, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xCA, 0x71, 0x2E, 0xFF, 0xBD, 0x51, 0x03, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xC6, 0x8A, 0x5C, 0xFF, 0xE6, 0xE6, 0xE6, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBC, 0x50, 0x02, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x51, 0x00, 0xFF,
++ 0xBD, 0x50, 0x02, 0xFF, 0xBC, 0x50, 0x02, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF,
++ 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF,
++ 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF,
++ 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF,
++ 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF,
++ 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBC, 0x51, 0x00, 0xFF,
++ 0xC2, 0x70, 0x36, 0xFF, 0xDC, 0xDC, 0xDC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFD, 0xFD, 0xFF,
++ 0xD6, 0xB5, 0xA2, 0xFF, 0xCD, 0xB8, 0xA9, 0xFF, 0xD0, 0xCB, 0xC8, 0xFF, 0xCF, 0xD0, 0xD4, 0xFF, 0xD2, 0xD1, 0xD3, 0xFF, 0xD0, 0xCF, 0xD1, 0xFF, 0xD1, 0xD1, 0xD1, 0xFF, 0xD3, 0xD0, 0xD2, 0xFF,
++ 0xCC, 0xB9, 0xAA, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBC, 0x51, 0x00, 0xFF, 0xBC, 0x51, 0x00, 0xFF, 0xD0, 0xB8, 0xAC, 0xFF, 0xD6, 0xD2, 0xCD, 0xFF, 0xCD, 0xD1, 0xD2, 0xFF, 0xD4, 0xD1, 0xD3, 0xFF,
++ 0xD2, 0xD2, 0xD2, 0xFF, 0xD2, 0xD2, 0xD2, 0xFF, 0xD1, 0xD0, 0xD2, 0xFF, 0xD1, 0xD0, 0xD2, 0xFF, 0xCA, 0xA0, 0x83, 0xFF, 0xBD, 0x51, 0x00, 0xFF, 0xBA, 0x51, 0x02, 0xFF, 0xBC, 0x50, 0x02, 0xFF,
++ 0xD6, 0xD1, 0xD3, 0xFF, 0xD1, 0xD0, 0xD2, 0xFF, 0xCF, 0xD3, 0xCE, 0xFF, 0xD1, 0xD0, 0xD2, 0xFF, 0xD2, 0xD1, 0xD5, 0xFF, 0xD2, 0xD1, 0xD5, 0xFF, 0xE6, 0xE5, 0xE7, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFD, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFC, 0xFF, 0xFD, 0xFF,
++ 0xC8, 0x71, 0x31, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xBA, 0x51, 0x00, 0xFF, 0xC6, 0x87, 0x5B, 0xFF, 0xE7, 0xE4, 0xE6, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF,
++ 0xBB, 0x50, 0x00, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF,
++ 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF,
++ 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF,
++ 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF,
++ 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF,
++ 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xBB, 0x4F, 0x01, 0xFF, 0xC1, 0x71, 0x36, 0xFF, 0xDC, 0xDC, 0xDC, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xF0, 0xF0, 0xF0, 0xFF,
++ 0xF8, 0xF7, 0xF3, 0xFF, 0xFF, 0xFD, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE4, 0xC0, 0xA2, 0xFF, 0xBB, 0x4F, 0x01, 0xFF,
++ 0xBA, 0x4D, 0x03, 0xFF, 0xBD, 0x50, 0x02, 0xFF, 0xCA, 0xCE, 0xC9, 0xFF, 0xF6, 0xF6, 0xF6, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xE5, 0xBC, 0xA3, 0xFF, 0xBE, 0x4F, 0x01, 0xFF, 0xBC, 0x4F, 0x01, 0xFF, 0xBA, 0x4F, 0x00, 0xFF, 0xCF, 0xD0, 0xD4, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xF4, 0xF1, 0xFF, 0xCF, 0x82, 0x51, 0xFF, 0xE0, 0xB3, 0x91, 0xFF,
++ 0xFE, 0xF9, 0xF6, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xC9, 0x6F, 0x2F, 0xFF, 0xBB, 0x4E, 0x00, 0xFF,
++ 0xBB, 0x4F, 0x01, 0xFF, 0xC4, 0x87, 0x5B, 0xFF, 0xE6, 0xE6, 0xE6, 0xFF, 0xFA, 0xFF, 0xFD, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xB9, 0x4F, 0x02, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF,
++ 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF,
++ 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF,
++ 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF,
++ 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF,
++ 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF,
++ 0xB9, 0x4F, 0x02, 0xFF, 0xB9, 0x4F, 0x02, 0xFF, 0xB9, 0x4F, 0x02, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xC0, 0x6F, 0x36, 0xFF, 0xDD, 0xDC, 0xDE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFD, 0xF7, 0xF8, 0xFF, 0xF4, 0xEA, 0xE0, 0xFF, 0xF4, 0xE9, 0xE1, 0xFF,
++ 0xF6, 0xEA, 0xE0, 0xFF, 0xF7, 0xE8, 0xDF, 0xFF, 0xF5, 0xE9, 0xDF, 0xFF, 0xF9, 0xE9, 0xDD, 0xFF, 0xD4, 0x99, 0x6B, 0xFF, 0xBC, 0x4F, 0x01, 0xFF, 0xBA, 0x4F, 0x00, 0xFF, 0xBE, 0x5E, 0x1C, 0xFF,
++ 0xCE, 0xC1, 0xB9, 0xFF, 0xF6, 0xE7, 0xDE, 0xFF, 0xF5, 0xE9, 0xDF, 0xFF, 0xF6, 0xEA, 0xE0, 0xFF, 0xF6, 0xEA, 0xE0, 0xFF, 0xF4, 0xE9, 0xE1, 0xFF, 0xF3, 0xE8, 0xE0, 0xFF, 0xF8, 0xE9, 0xE0, 0xFF,
++ 0xDD, 0xB0, 0x8B, 0xFF, 0xB9, 0x50, 0x00, 0xFF, 0xBA, 0x4E, 0x01, 0xFF, 0xBA, 0x51, 0x02, 0xFF, 0xD1, 0xD0, 0xD2, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xF1, 0xDE, 0xD1, 0xFF, 0xB7, 0x50, 0x01, 0xFF, 0xB7, 0x50, 0x01, 0xFF, 0xC0, 0x59, 0x14, 0xFF, 0xDC, 0xAD, 0x87, 0xFF,
++ 0xFC, 0xFB, 0xF7, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC6, 0x6F, 0x31, 0xFF, 0xB9, 0x50, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xC4, 0x85, 0x5F, 0xFF,
++ 0xE3, 0xE4, 0xE8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xB8, 0x4E, 0x01, 0xFF,
++ 0xB6, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB6, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4F, 0x00, 0xFF, 0xB6, 0x4D, 0x03, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF,
++ 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF,
++ 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF,
++ 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF,
++ 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF,
++ 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB6, 0x4E, 0x01, 0xFF, 0xB8, 0x4E, 0x01, 0xFF,
++ 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4F, 0x00, 0xFF, 0xBD, 0x6E, 0x35, 0xFF, 0xDD, 0xDC, 0xDE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC4, 0x6F, 0x31, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB8, 0x4D, 0x03, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB6, 0x4E, 0x01, 0xFF,
++ 0xB8, 0x4D, 0x03, 0xFF, 0xB4, 0x4F, 0x00, 0xFF, 0xB9, 0x4C, 0x02, 0xFF, 0xB8, 0x4D, 0x03, 0xFF, 0xB7, 0x4E, 0x04, 0xFF, 0xB3, 0x4E, 0x03, 0xFF, 0xB6, 0x4E, 0x01, 0xFF, 0xB9, 0x50, 0x01, 0xFF,
++ 0xB8, 0x4E, 0x01, 0xFF, 0xB6, 0x4D, 0x03, 0xFF, 0xB6, 0x4D, 0x03, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB7, 0x4D, 0x00, 0xFF, 0xB7, 0x4E, 0x04, 0xFF, 0xB6, 0x4D, 0x03, 0xFF, 0xB7, 0x4F, 0x02, 0xFF,
++ 0xBA, 0x4E, 0x00, 0xFF, 0xB5, 0x4D, 0x00, 0xFF, 0xD2, 0xD0, 0xD0, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xF6, 0xE8, 0xDC, 0xFF, 0xB6, 0x4D, 0x03, 0xFF, 0xBB, 0x4E, 0x04, 0xFF, 0xB5, 0x4D, 0x00, 0xFF, 0xB9, 0x4F, 0x02, 0xFF, 0xE2, 0xC8, 0xB8, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xC4, 0x6F, 0x31, 0xFF, 0xB6, 0x4E, 0x01, 0xFF, 0xB3, 0x4F, 0x01, 0xFF, 0xC3, 0x88, 0x5A, 0xFF, 0xE6, 0xE6, 0xE6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xE2, 0xB3, 0x94, 0xFF, 0xDA, 0x9F, 0x77, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFC, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xB5, 0x4D, 0x00, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF,
++ 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4D, 0x00, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF,
++ 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF,
++ 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF,
++ 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF,
++ 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF,
++ 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4D, 0x00, 0xFF,
++ 0xBD, 0x6E, 0x35, 0xFF, 0xDB, 0xDD, 0xDE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xE4, 0xB8, 0x9B, 0xFF, 0xB4, 0x4F, 0x00, 0xFF, 0xB7, 0x4D, 0x00, 0xFF, 0xB5, 0x4C, 0x03, 0xFF, 0xB3, 0x4D, 0x02, 0xFF, 0xB4, 0x4F, 0x01, 0xFF, 0xB4, 0x4C, 0x00, 0xFF,
++ 0xBB, 0x4F, 0x02, 0xFF, 0xB3, 0x4E, 0x00, 0xFF, 0xB7, 0x4D, 0x00, 0xFF, 0xB7, 0x4D, 0x00, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB5, 0x4E, 0x00, 0xFF, 0xB6, 0x4F, 0x00, 0xFF,
++ 0xB7, 0x4D, 0x00, 0xFF, 0xB8, 0x4D, 0x03, 0xFF, 0xB4, 0x4E, 0x03, 0xFF, 0xB7, 0x4D, 0x00, 0xFF, 0xB6, 0x4D, 0x03, 0xFF, 0xB5, 0x4E, 0x00, 0xFF, 0xB6, 0x4E, 0x01, 0xFF, 0xB5, 0x4C, 0x02, 0xFF,
++ 0xD0, 0xC9, 0xC6, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFE, 0xFF, 0xFD, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xF7, 0xEC, 0xE4, 0xFF,
++ 0xB3, 0x4E, 0x00, 0xFF, 0xB3, 0x4E, 0x00, 0xFF, 0xB7, 0x4D, 0x00, 0xFF, 0xC5, 0x8F, 0x6C, 0xFF, 0xD1, 0xD0, 0xD2, 0xFF, 0xF1, 0xF5, 0xF6, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xC5, 0x6D, 0x31, 0xFF, 0xB8, 0x4E, 0x01, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xC4, 0x86, 0x5D, 0xFF, 0xE5, 0xE4, 0xE8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xEA, 0xC7, 0xAD, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB5, 0x4C, 0x03, 0xFF, 0xCC, 0x95, 0x6E, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF,
++ 0xB4, 0x4C, 0x00, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF,
++ 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF,
++ 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF,
++ 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF,
++ 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF,
++ 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB5, 0x4D, 0x00, 0xFF, 0xBC, 0x6D, 0x34, 0xFF, 0xDA, 0xDC, 0xDD, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xDE, 0xBE, 0xAB, 0xFF, 0xC6, 0xA4, 0x87, 0xFF, 0xCC, 0xBC, 0xAF, 0xFF, 0xD2, 0xC6, 0xC0, 0xFF, 0xCD, 0xC8, 0xC5, 0xFF, 0xBF, 0x85, 0x5B, 0xFF, 0xB4, 0x4B, 0x02, 0xFF, 0xB3, 0x4D, 0x02, 0xFF,
++ 0xB6, 0x56, 0x10, 0xFF, 0xD0, 0xC6, 0xBF, 0xFF, 0xD2, 0xCA, 0xC3, 0xFF, 0xCB, 0xC8, 0xC4, 0xFF, 0xCE, 0xC9, 0xC8, 0xFF, 0xD1, 0xC8, 0xC5, 0xFF, 0xD0, 0xCA, 0xC5, 0xFF, 0xCD, 0xC8, 0xC5, 0xFF,
++ 0xD0, 0xC9, 0xC6, 0xFF, 0xCE, 0xCA, 0xC5, 0xFF, 0xC7, 0x9A, 0x79, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB2, 0x4D, 0x02, 0xFF, 0xB6, 0x4B, 0x01, 0xFF, 0xD0, 0xC6, 0xBF, 0xFF, 0xFA, 0xFC, 0xFC, 0xFF,
++ 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFA, 0xF3, 0xF0, 0xFF, 0xB7, 0x4D, 0x00, 0xFF, 0xB2, 0x4C, 0x01, 0xFF,
++ 0xB2, 0x4C, 0x01, 0xFF, 0xC9, 0xB1, 0x9F, 0xFF, 0xE9, 0xE9, 0xE9, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC5, 0x6E, 0x2E, 0xFF, 0xB1, 0x4B, 0x02, 0xFF,
++ 0xB7, 0x4D, 0x00, 0xFF, 0xB8, 0x5E, 0x1D, 0xFF, 0xC3, 0x7D, 0x48, 0xFF, 0xCD, 0x81, 0x50, 0xFF, 0xCB, 0x82, 0x50, 0xFF, 0xCB, 0x85, 0x50, 0xFF, 0xCA, 0x83, 0x51, 0xFF, 0xB7, 0x52, 0x0D, 0xFF,
++ 0xB3, 0x4E, 0x00, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB2, 0x4C, 0x01, 0xFF, 0xD5, 0xAD, 0x91, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xB6, 0x4A, 0x02, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4B, 0x04, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB5, 0x4C, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB3, 0x4C, 0x03, 0xFF,
++ 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF,
++ 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF,
++ 0xB2, 0x4D, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB1, 0x4C, 0x01, 0xFF, 0xB3, 0x4B, 0x04, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB5, 0x4C, 0x03, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB2, 0x4C, 0x03, 0xFF,
++ 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF,
++ 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF,
++ 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xBB, 0x6D, 0x38, 0xFF, 0xDC, 0xDC, 0xDC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xF4, 0xF1, 0xF3, 0xFF,
++ 0xF1, 0xEE, 0xF0, 0xFF, 0xF7, 0xF8, 0xF6, 0xFF, 0xF6, 0xF3, 0xEF, 0xFF, 0xB7, 0x56, 0x12, 0xFF, 0xB2, 0x4C, 0x03, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xC1, 0x87, 0x63, 0xFF, 0xD4, 0xD4, 0xD4, 0xFF,
++ 0xFC, 0xFC, 0xFC, 0xFF, 0xFC, 0xFC, 0xFC, 0xFF, 0xFC, 0xFC, 0xFC, 0xFF, 0xFC, 0xFC, 0xFC, 0xFF, 0xFC, 0xFC, 0xFC, 0xFF, 0xFC, 0xFC, 0xFC, 0xFF, 0xFC, 0xFC, 0xFC, 0xFF, 0xFC, 0xFC, 0xFC, 0xFF,
++ 0xE2, 0xBA, 0xA1, 0xFF, 0xB0, 0x4C, 0x04, 0xFF, 0xB5, 0x4F, 0x06, 0xFF, 0xBD, 0x82, 0x55, 0xFF, 0xD0, 0xCF, 0xD1, 0xFF, 0xFA, 0xF9, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFA, 0xF4, 0xEF, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB3, 0x4C, 0x03, 0xFF, 0xCA, 0xB0, 0x9F, 0xFF,
++ 0xF3, 0xF3, 0xF3, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xC3, 0x6D, 0x31, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB4, 0x4B, 0x01, 0xFF, 0xB5, 0x4C, 0x03, 0xFF,
++ 0xB2, 0x4C, 0x01, 0xFF, 0xB3, 0x4D, 0x02, 0xFF, 0xB3, 0x4D, 0x02, 0xFF, 0xB2, 0x4C, 0x01, 0xFF, 0xB3, 0x4D, 0x02, 0xFF, 0xB3, 0x4D, 0x02, 0xFF, 0xB3, 0x4D, 0x02, 0xFF, 0xB3, 0x4D, 0x02, 0xFF,
++ 0xB3, 0x4C, 0x03, 0xFF, 0xB6, 0x4F, 0x06, 0xFF, 0xE5, 0xE0, 0xDF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xB2, 0x4A, 0x05, 0xFF,
++ 0xB0, 0x4A, 0x01, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB3, 0x49, 0x02, 0xFF, 0xB5, 0x4B, 0x04, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4A, 0x03, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF,
++ 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF,
++ 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB4, 0x4B, 0x02, 0xFF,
++ 0xB2, 0x4D, 0x02, 0xFF, 0xB2, 0x4C, 0x01, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB0, 0x4A, 0x01, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF,
++ 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF,
++ 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF,
++ 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xBA, 0x6C, 0x37, 0xFF, 0xDC, 0xDC, 0xDC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFD, 0xFE, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xDB, 0xA4, 0x7F, 0xFF, 0xB0, 0x4A, 0x01, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB0, 0x4E, 0x06, 0xFF, 0xCD, 0xC3, 0xB9, 0xFF, 0xE6, 0xE5, 0xE9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xF0, 0xEC, 0xFF, 0xD5, 0xA7, 0x85, 0xFF,
++ 0xC5, 0x9D, 0x84, 0xFF, 0xCE, 0xC0, 0xB4, 0xFF, 0xE0, 0xE3, 0xE1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFD, 0xFD, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFA, 0xF4, 0xEF, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xCA, 0xB0, 0x9F, 0xFF, 0xF3, 0xF3, 0xF3, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xC0, 0x6C, 0x32, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB6, 0x67, 0x2E, 0xFF, 0xC0, 0x8E, 0x6A, 0xFF, 0xC0, 0x8E, 0x6A, 0xFF,
++ 0xBF, 0x8D, 0x69, 0xFF, 0xC0, 0x8E, 0x6A, 0xFF, 0xC0, 0x8E, 0x6A, 0xFF, 0xBF, 0x8D, 0x69, 0xFF, 0xC0, 0x8E, 0x6A, 0xFF, 0xC0, 0x8E, 0x6A, 0xFF, 0xC0, 0x8E, 0x6A, 0xFF, 0xC6, 0x99, 0x78, 0xFF,
++ 0xD3, 0xD1, 0xD0, 0xFF, 0xF9, 0xFB, 0xFC, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB2, 0x4E, 0x00, 0xFF, 0xB1, 0x4B, 0x03, 0xFF,
++ 0xB1, 0x4C, 0x01, 0xFF, 0xB1, 0x4C, 0x01, 0xFF, 0xAF, 0x4C, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF,
++ 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF,
++ 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4A, 0x05, 0xFF, 0xB4, 0x4B, 0x02, 0xFF,
++ 0xB4, 0x4B, 0x02, 0xFF, 0xB0, 0x4A, 0x01, 0xFF, 0xB1, 0x4A, 0x01, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF,
++ 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF,
++ 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF,
++ 0xBA, 0x6C, 0x37, 0xFF, 0xDC, 0xDC, 0xDC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFD, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xF3, 0xE7, 0xDD, 0xFF, 0xB4, 0x51, 0x07, 0xFF, 0xB2, 0x4A, 0x03, 0xFF,
++ 0xB0, 0x4B, 0x00, 0xFF, 0xB6, 0x5D, 0x20, 0xFF, 0xC8, 0xAE, 0x9E, 0xFF, 0xE7, 0xCE, 0xBA, 0xFF, 0xEC, 0xD2, 0xC1, 0xFF, 0xEC, 0xD2, 0xC1, 0xFF, 0xEC, 0xD2, 0xC1, 0xFF, 0xEC, 0xD2, 0xC1, 0xFF,
++ 0xEC, 0xD2, 0xC1, 0xFF, 0xEC, 0xD2, 0xC1, 0xFF, 0xEC, 0xD2, 0xC1, 0xFF, 0xEC, 0xD2, 0xC1, 0xFF, 0xEC, 0xD2, 0xC1, 0xFF, 0xDB, 0xB4, 0x94, 0xFF, 0xB2, 0x4A, 0x03, 0xFF, 0xB4, 0x54, 0x12, 0xFF,
++ 0xE9, 0xCE, 0xBA, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFA, 0xF4, 0xEF, 0xFF,
++ 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xCA, 0xB0, 0x9F, 0xFF, 0xF1, 0xF4, 0xF2, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xBF, 0x6B, 0x31, 0xFF, 0xB0, 0x49, 0x00, 0xFF, 0xB0, 0x4C, 0x04, 0xFF, 0xBF, 0x85, 0x5B, 0xFF, 0xDB, 0xDA, 0xDC, 0xFF, 0xE8, 0xE7, 0xE9, 0xFF, 0xE8, 0xE7, 0xE9, 0xFF, 0xE8, 0xE7, 0xE9, 0xFF,
++ 0xE9, 0xE8, 0xEA, 0xFF, 0xE9, 0xE8, 0xEA, 0xFF, 0xE9, 0xE8, 0xEA, 0xFF, 0xE8, 0xE7, 0xE9, 0xFF, 0xE8, 0xE7, 0xE9, 0xFF, 0xE8, 0xE8, 0xE8, 0xFF, 0xEB, 0xEB, 0xEB, 0xFF, 0xFD, 0xFE, 0xFC, 0xFF,
++ 0xFD, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xB2, 0x4A, 0x03, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x00, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x03, 0xFF,
++ 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4A, 0x01, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF,
++ 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF,
++ 0xB2, 0x4B, 0x02, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB0, 0x4A, 0x01, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB1, 0x4B, 0x03, 0xFF,
++ 0xAF, 0x4B, 0x03, 0xFF, 0xB1, 0x4C, 0x01, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF,
++ 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF,
++ 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xBA, 0x6C, 0x37, 0xFF, 0xDA, 0xDC, 0xDC, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFB, 0xFA, 0xFF, 0xC2, 0x75, 0x3D, 0xFF, 0xAF, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF,
++ 0xAF, 0x4C, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF,
++ 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB0, 0x4A, 0x01, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB1, 0x4A, 0x01, 0xFF, 0xAF, 0x4C, 0x02, 0xFF, 0xB2, 0x4E, 0x06, 0xFF, 0xE4, 0xC6, 0xB5, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFA, 0xF4, 0xEF, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF,
++ 0xB1, 0x4B, 0x03, 0xFF, 0xCA, 0xB0, 0x9F, 0xFF, 0xF1, 0xF4, 0xF2, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBE, 0x6C, 0x32, 0xFF, 0xB2, 0x4D, 0x02, 0xFF,
++ 0xB0, 0x4B, 0x00, 0xFF, 0xBD, 0x85, 0x5C, 0xFF, 0xE5, 0xE5, 0xE5, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFC, 0xFF, 0xAC, 0x4C, 0x00, 0xFF, 0xAF, 0x4A, 0x05, 0xFF, 0xB4, 0x4A, 0x03, 0xFF, 0xB0, 0x49, 0x04, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xAF, 0x4B, 0x03, 0xFF,
++ 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF,
++ 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF,
++ 0xAF, 0x4B, 0x03, 0xFF, 0xAF, 0x4C, 0x02, 0xFF, 0xB0, 0x4B, 0x00, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4A, 0x01, 0xFF, 0xB2, 0x4C, 0x04, 0xFF, 0xB2, 0x4A, 0x03, 0xFF,
++ 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF,
++ 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF,
++ 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB8, 0x6C, 0x37, 0xFF, 0xDA, 0xDC, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xD3, 0x9B, 0x72, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB2, 0x4A, 0x03, 0xFF, 0xB0, 0x4A, 0x01, 0xFF, 0xB2, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xAF, 0x4E, 0x04, 0xFF, 0xB2, 0x53, 0x0D, 0xFF,
++ 0xB2, 0x53, 0x0E, 0xFF, 0xB2, 0x53, 0x0E, 0xFF, 0xB2, 0x53, 0x0E, 0xFF, 0xB2, 0x53, 0x0E, 0xFF, 0xB2, 0x53, 0x0E, 0xFF, 0xB2, 0x53, 0x0E, 0xFF, 0xB2, 0x53, 0x0E, 0xFF, 0xB2, 0x53, 0x0E, 0xFF,
++ 0xB3, 0x52, 0x10, 0xFF, 0xB0, 0x4C, 0x04, 0xFF, 0xB0, 0x4C, 0x04, 0xFF, 0xAF, 0x4B, 0x03, 0xFF, 0xB0, 0x4E, 0x02, 0xFF, 0xC8, 0xAB, 0x96, 0xFF, 0xF1, 0xF4, 0xF2, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFA, 0xF4, 0xEF, 0xFF, 0xB0, 0x4A, 0x01, 0xFF, 0xB0, 0x4A, 0x01, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xC9, 0xAF, 0x9E, 0xFF,
++ 0xF2, 0xF2, 0xF2, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xBD, 0x6B, 0x31, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xC1, 0x85, 0x5B, 0xFF,
++ 0xE5, 0xE5, 0xE5, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xAE, 0x49, 0x04, 0xFF,
++ 0xB1, 0x4B, 0x00, 0xFF, 0xAB, 0x4A, 0x00, 0xFF, 0xAE, 0x49, 0x04, 0xFF, 0xB1, 0x4B, 0x02, 0xFF, 0xAB, 0x4A, 0x00, 0xFF, 0xB0, 0x4A, 0x01, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF,
++ 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF,
++ 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB1, 0x49, 0x02, 0xFF, 0xAE, 0x49, 0x05, 0xFF,
++ 0xAC, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xAF, 0x4B, 0x03, 0xFF, 0xB0, 0x4A, 0x00, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF,
++ 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF,
++ 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xAE, 0x4B, 0x01, 0xFF, 0xB0, 0x4A, 0x02, 0xFF,
++ 0xAE, 0x4B, 0x01, 0xFF, 0xB0, 0x4A, 0x01, 0xFF, 0xB8, 0x6C, 0x37, 0xFF, 0xDA, 0xDC, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFE, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE0, 0xBE, 0xA1, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF,
++ 0xAF, 0x4A, 0x05, 0xFF, 0xB1, 0x52, 0x0D, 0xFF, 0xAE, 0x4B, 0x01, 0xFF, 0xAD, 0x4A, 0x00, 0xFF, 0xBC, 0x75, 0x43, 0xFF, 0xD3, 0xD3, 0xD3, 0xFF, 0xD4, 0xD4, 0xD4, 0xFF, 0xD4, 0xD4, 0xD4, 0xFF,
++ 0xD4, 0xD4, 0xD4, 0xFF, 0xD4, 0xD4, 0xD4, 0xFF, 0xD4, 0xD4, 0xD4, 0xFF, 0xD4, 0xD4, 0xD4, 0xFF, 0xD4, 0xD4, 0xD4, 0xFF, 0xD4, 0xD4, 0xD4, 0xFF, 0xD2, 0xD4, 0xD4, 0xFF, 0xB7, 0x6C, 0x38, 0xFF,
++ 0xAB, 0x4A, 0x00, 0xFF, 0xB0, 0x4A, 0x01, 0xFF, 0xB9, 0x7A, 0x4E, 0xFF, 0xD2, 0xD2, 0xD2, 0xFF, 0xF2, 0xF1, 0xF3, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFA, 0xF4, 0xEF, 0xFF, 0xB0, 0x4A, 0x01, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xC9, 0xAF, 0x9E, 0xFF, 0xF3, 0xF2, 0xF4, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xC0, 0x6C, 0x32, 0xFF, 0xB1, 0x49, 0x02, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xBF, 0x84, 0x5C, 0xFF, 0xE6, 0xE6, 0xE6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xE9, 0xC7, 0xB0, 0xFF, 0xC5, 0xA5, 0x8E, 0xFF, 0xC7, 0xA7, 0x90, 0xFF,
++ 0xC5, 0xA6, 0x91, 0xFF, 0xC5, 0xA6, 0x8F, 0xFF, 0xC6, 0xA7, 0x8E, 0xFF, 0xC6, 0xA5, 0x91, 0xFF, 0xC6, 0xA6, 0x8F, 0xFF, 0xC6, 0xA6, 0x8F, 0xFF, 0xC6, 0xA6, 0x8F, 0xFF, 0xC6, 0xA6, 0x8F, 0xFF,
++ 0xC6, 0xA6, 0x8F, 0xFF, 0xC6, 0xA6, 0x8F, 0xFF, 0xC6, 0xA6, 0x8F, 0xFF, 0xC6, 0xA6, 0x8F, 0xFF, 0xC6, 0xA6, 0x8F, 0xFF, 0xC6, 0xA6, 0x8F, 0xFF, 0xC6, 0xA6, 0x8F, 0xFF, 0xC6, 0xA6, 0x8F, 0xFF,
++ 0xC6, 0xA6, 0x8F, 0xFF, 0xC6, 0xA6, 0x8F, 0xFF, 0xC6, 0xA6, 0x8F, 0xFF, 0xC6, 0xA6, 0x8F, 0xFF, 0xC8, 0xA6, 0x8F, 0xFF, 0xC6, 0xA5, 0x91, 0xFF, 0xC5, 0xA6, 0x8F, 0xFF, 0xC5, 0xA6, 0x91, 0xFF,
++ 0xC6, 0xA7, 0x92, 0xFF, 0xC6, 0xA7, 0x8E, 0xFF, 0xB9, 0x68, 0x2F, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF,
++ 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF,
++ 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xAE, 0x4B, 0x01, 0xFF, 0xAE, 0x4A, 0x02, 0xFF,
++ 0xB8, 0x6C, 0x37, 0xFF, 0xDA, 0xDC, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFE, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xE6, 0xC6, 0xAF, 0xFF, 0xB2, 0x4D, 0x08, 0xFF, 0xAF, 0x49, 0x01, 0xFF, 0xB1, 0x4B, 0x03, 0xFF, 0xBF, 0x82, 0x56, 0xFF, 0xBC, 0x7E, 0x50, 0xFF,
++ 0xB0, 0x4A, 0x01, 0xFF, 0xAF, 0x4A, 0x05, 0xFF, 0xB9, 0x74, 0x43, 0xFF, 0xDF, 0xDE, 0xE0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC4, 0x77, 0x3F, 0xFF, 0xB0, 0x4A, 0x01, 0xFF, 0xB0, 0x49, 0x04, 0xFF,
++ 0xBD, 0x7C, 0x4F, 0xFF, 0xE0, 0xE2, 0xE3, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0xF4, 0xEF, 0xFF,
++ 0xAE, 0x4B, 0x01, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xC9, 0xAF, 0x9E, 0xFF, 0xF3, 0xF2, 0xF4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF,
++ 0xBF, 0x6A, 0x32, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xAE, 0x49, 0x04, 0xFF, 0xBB, 0x85, 0x5C, 0xFF, 0xE5, 0xE5, 0xE5, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xF2, 0xF2, 0xFF, 0xF3, 0xF0, 0xF2, 0xFF, 0xF3, 0xF1, 0xF0, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF,
++ 0xF3, 0xF0, 0xF2, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF,
++ 0xF1, 0xF1, 0xF1, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF,
++ 0xF1, 0xF1, 0xF1, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xF1, 0xF0, 0xF2, 0xFF, 0xF1, 0xF2, 0xF0, 0xFF, 0xF3, 0xF1, 0xF0, 0xFF, 0xF3, 0xF0, 0xF2, 0xFF, 0xF2, 0xF2, 0xF2, 0xFF,
++ 0xC5, 0x7E, 0x4C, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF,
++ 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF,
++ 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x4B, 0x01, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xB8, 0x6C, 0x37, 0xFF, 0xDA, 0xDC, 0xDD, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xDF, 0xB7, 0x9B, 0xFF,
++ 0xB1, 0x4B, 0x03, 0xFF, 0xAC, 0x4A, 0x04, 0xFF, 0xAC, 0x4A, 0x02, 0xFF, 0xBF, 0x81, 0x5B, 0xFF, 0xD2, 0xD0, 0xCF, 0xFF, 0xC0, 0x84, 0x56, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xAD, 0x48, 0x03, 0xFF,
++ 0xB9, 0x75, 0x40, 0xFF, 0xDF, 0xE0, 0xDE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC1, 0x77, 0x41, 0xFF, 0xAC, 0x4B, 0x01, 0xFF, 0xB0, 0x49, 0x04, 0xFF, 0xBE, 0x7E, 0x4E, 0xFF, 0xE0, 0xE2, 0xE2, 0xFF,
++ 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0xF4, 0xEF, 0xFF, 0xAE, 0x4B, 0x01, 0xFF, 0xAE, 0x4A, 0x02, 0xFF,
++ 0xB0, 0x4A, 0x02, 0xFF, 0xC9, 0xAF, 0x9E, 0xFF, 0xF3, 0xF3, 0xF3, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBF, 0x69, 0x33, 0xFF, 0xAC, 0x4B, 0x01, 0xFF,
++ 0xB0, 0x4A, 0x01, 0xFF, 0xBD, 0x86, 0x5B, 0xFF, 0xE6, 0xE6, 0xE6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC7, 0x82, 0x51, 0xFF, 0xAD, 0x49, 0x01, 0xFF,
++ 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF,
++ 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF,
++ 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xB7, 0x6B, 0x37, 0xFF, 0xDC, 0xDC, 0xDC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xD1, 0x9C, 0x77, 0xFF, 0xB0, 0x49, 0x04, 0xFF, 0xB0, 0x4A, 0x02, 0xFF, 0xAB, 0x49, 0x01, 0xFF,
++ 0xBC, 0x8D, 0x6D, 0xFF, 0xCF, 0xD2, 0xD0, 0xFF, 0xE6, 0xE6, 0xE6, 0xFF, 0xCE, 0x8D, 0x61, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xB9, 0x74, 0x43, 0xFF, 0xE1, 0xDE, 0xE0, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFE, 0xFF, 0xFD, 0xFF, 0xC1, 0x77, 0x41, 0xFF, 0xAF, 0x48, 0x03, 0xFF, 0xAC, 0x4A, 0x04, 0xFF, 0xB9, 0x7D, 0x4F, 0xFF, 0xE3, 0xE3, 0xE3, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF,
++ 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xF6, 0xEE, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAC, 0x4A, 0x04, 0xFF, 0xAC, 0x47, 0x02, 0xFF, 0xC9, 0xAF, 0x9E, 0xFF,
++ 0xF2, 0xF2, 0xF2, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBC, 0x6B, 0x32, 0xFF, 0xAF, 0x48, 0x03, 0xFF, 0xAD, 0x4A, 0x00, 0xFF, 0xBC, 0x84, 0x5B, 0xFF,
++ 0xE5, 0xE4, 0xE6, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFA, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFB, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC6, 0x81, 0x50, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF,
++ 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF,
++ 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x48, 0x03, 0xFF,
++ 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xB7, 0x6B, 0x37, 0xFF, 0xDC, 0xDC, 0xDC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFB, 0xFA, 0xF6, 0xFF, 0xC8, 0x84, 0x55, 0xFF, 0xB0, 0x4A, 0x01, 0xFF, 0xAB, 0x49, 0x01, 0xFF, 0xB2, 0x50, 0x10, 0xFF, 0xC6, 0xA6, 0x93, 0xFF, 0xD5, 0xD0, 0xD1, 0xFF, 0xE8, 0xE8, 0xEE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xC7, 0x83, 0x54, 0xFF, 0xAC, 0x4A, 0x04, 0xFF, 0xAB, 0x4B, 0x00, 0xFF, 0xB7, 0x75, 0x40, 0xFF, 0xDB, 0xE0, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xC1, 0x76, 0x3E, 0xFF,
++ 0xAB, 0x49, 0x01, 0xFF, 0xB0, 0x48, 0x03, 0xFF, 0xBD, 0x7C, 0x50, 0xFF, 0xE2, 0xE1, 0xE3, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0xF5, 0xED, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAE, 0x48, 0x00, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xC9, 0xAF, 0x9F, 0xFF, 0xF1, 0xF3, 0xF3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xBA, 0x6C, 0x31, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xBC, 0x83, 0x5C, 0xFF, 0xE5, 0xE6, 0xE4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0xE0, 0xD3, 0xFF,
++ 0xFB, 0xF8, 0xF0, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFC, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC7, 0x82, 0x51, 0xFF, 0xAE, 0x49, 0x04, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xAD, 0x48, 0x03, 0xFF,
++ 0xAD, 0x48, 0x03, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xAD, 0x48, 0x03, 0xFF,
++ 0xAD, 0x48, 0x03, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAB, 0x49, 0x03, 0xFF,
++ 0xB7, 0x6B, 0x37, 0xFF, 0xDC, 0xDC, 0xDC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xD3, 0xA3, 0x7F, 0xFF, 0xAC, 0x49, 0x05, 0xFF,
++ 0xAB, 0x49, 0x01, 0xFF, 0xB8, 0x76, 0x41, 0xFF, 0xCD, 0xC1, 0xBB, 0xFF, 0xD2, 0xD5, 0xD3, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xC5, 0x7C, 0x48, 0xFF,
++ 0xAC, 0x48, 0x00, 0xFF, 0xAC, 0x4A, 0x04, 0xFF, 0xB2, 0x57, 0x1A, 0xFF, 0xBC, 0x81, 0x54, 0xFF, 0xCC, 0x8E, 0x60, 0xFF, 0xCC, 0x8E, 0x60, 0xFF, 0xCC, 0x8E, 0x60, 0xFF, 0xCC, 0x8E, 0x60, 0xFF,
++ 0xCC, 0x8E, 0x60, 0xFF, 0xCC, 0x8E, 0x60, 0xFF, 0xCC, 0x8E, 0x60, 0xFF, 0xCC, 0x8E, 0x60, 0xFF, 0xCB, 0x8C, 0x60, 0xFF, 0xB1, 0x59, 0x19, 0xFF, 0xAB, 0x49, 0x01, 0xFF, 0xAD, 0x49, 0x01, 0xFF,
++ 0xB9, 0x7D, 0x4F, 0xFF, 0xE5, 0xE2, 0xE4, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xF5, 0xF0, 0xFF,
++ 0xAF, 0x47, 0x02, 0xFF, 0xAE, 0x4B, 0x01, 0xFF, 0xA9, 0x4A, 0x01, 0xFF, 0xC8, 0xAF, 0x9F, 0xFF, 0xF3, 0xF3, 0xF3, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xB9, 0x6B, 0x30, 0xFF, 0xAE, 0x4A, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xBC, 0x84, 0x5B, 0xFF, 0xE6, 0xE6, 0xE6, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xE5, 0xC5, 0xAE, 0xFF, 0xAA, 0x4B, 0x02, 0xFF, 0xBE, 0x6F, 0x3E, 0xFF, 0xF9, 0xF9, 0xF3, 0xFF,
++ 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFE, 0xFD, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xC6, 0x81, 0x50, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF,
++ 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF,
++ 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAD, 0x48, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xB5, 0x6A, 0x36, 0xFF, 0xDC, 0xDC, 0xDC, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF2, 0xDE, 0xD3, 0xFF, 0xBA, 0x72, 0x3C, 0xFF, 0xC6, 0xA7, 0x92, 0xFF, 0xCF, 0xD1, 0xD2, 0xFF,
++ 0xE1, 0xDF, 0xDF, 0xFF, 0xFA, 0xFA, 0xFA, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xBD, 0x71, 0x3C, 0xFF, 0xAC, 0x48, 0x00, 0xFF, 0xAC, 0x47, 0x02, 0xFF,
++ 0xAE, 0x47, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF,
++ 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAC, 0x47, 0x02, 0xFF, 0xAA, 0x47, 0x03, 0xFF, 0xAC, 0x47, 0x02, 0xFF, 0xAC, 0x49, 0x00, 0xFF, 0xB6, 0x74, 0x43, 0xFF, 0xE3, 0xE3, 0xE3, 0xFF,
++ 0xFF, 0xFF, 0xFC, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFC, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xF8, 0xF4, 0xEF, 0xFF, 0xAB, 0x48, 0x04, 0xFF, 0xAC, 0x47, 0x03, 0xFF,
++ 0xAC, 0x47, 0x02, 0xFF, 0xC9, 0xAE, 0xA0, 0xFF, 0xF5, 0xF3, 0xF3, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xBC, 0x6A, 0x33, 0xFF, 0xAC, 0x47, 0x02, 0xFF,
++ 0xA7, 0x49, 0x00, 0xFF, 0xBA, 0x84, 0x5B, 0xFF, 0xE4, 0xE3, 0xE5, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFA, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFB, 0xFF, 0xEC, 0xD5, 0xC5, 0xFF, 0xB0, 0x4F, 0x0D, 0xFF, 0xAD, 0x48, 0x04, 0xFF, 0xAC, 0x47, 0x02, 0xFF, 0xBC, 0x76, 0x47, 0xFF, 0xFB, 0xFB, 0xFB, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC4, 0x81, 0x50, 0xFF, 0xAA, 0x48, 0x02, 0xFF,
++ 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF,
++ 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF,
++ 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xB5, 0x6A, 0x36, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xF5, 0xF7, 0xF8, 0xFF, 0xDE, 0xDE, 0xDE, 0xFF, 0xF3, 0xF0, 0xF2, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFC, 0xFE, 0xFF, 0xFF, 0xB9, 0x6A, 0x31, 0xFF, 0xAB, 0x49, 0x01, 0xFF, 0xAA, 0x48, 0x00, 0xFF, 0xAD, 0x59, 0x1F, 0xFF, 0xBC, 0x84, 0x5B, 0xFF,
++ 0xBC, 0x83, 0x5C, 0xFF, 0xBC, 0x83, 0x5C, 0xFF, 0xBC, 0x83, 0x5C, 0xFF, 0xBC, 0x83, 0x5C, 0xFF, 0xBC, 0x83, 0x5C, 0xFF, 0xBC, 0x83, 0x5C, 0xFF, 0xBC, 0x83, 0x5C, 0xFF, 0xBC, 0x83, 0x5C, 0xFF,
++ 0xBC, 0x84, 0x5B, 0xFF, 0xB0, 0x57, 0x1A, 0xFF, 0xAA, 0x48, 0x00, 0xFF, 0xAF, 0x48, 0x03, 0xFF, 0xB5, 0x6F, 0x40, 0xFF, 0xDE, 0xE0, 0xE1, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xE5, 0xC8, 0xB3, 0xFF, 0xAC, 0x4B, 0x07, 0xFF,
++ 0xAB, 0x49, 0x03, 0xFF, 0xA9, 0x48, 0x04, 0xFF, 0xA9, 0x49, 0x03, 0xFF, 0xA9, 0x49, 0x03, 0xFF, 0xAC, 0x48, 0x00, 0xFF, 0xAA, 0x48, 0x00, 0xFF, 0xA9, 0x48, 0x04, 0xFF, 0xAC, 0x48, 0x00, 0xFF,
++ 0xA8, 0x48, 0x02, 0xFF, 0xA8, 0x49, 0x00, 0xFF, 0xAA, 0x47, 0x03, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xA8, 0x49, 0x00, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAE, 0x47, 0x02, 0xFF, 0xAA, 0x47, 0x03, 0xFF,
++ 0xAE, 0x4A, 0x02, 0xFF, 0xAA, 0x48, 0x00, 0xFF, 0xAD, 0x49, 0x01, 0xFF, 0xAD, 0x47, 0x00, 0xFF, 0xAC, 0x48, 0x00, 0xFF, 0xAC, 0x47, 0x02, 0xFF, 0xAE, 0x49, 0x04, 0xFF, 0xA9, 0x47, 0x01, 0xFF,
++ 0xAA, 0x48, 0x02, 0xFF, 0xAB, 0x48, 0x04, 0xFF, 0xAF, 0x49, 0x01, 0xFF, 0xA9, 0x4A, 0x01, 0xFF, 0xC2, 0x8C, 0x63, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xC3, 0x81, 0x51, 0xFF,
++ 0xC5, 0x82, 0x51, 0xFF, 0xC3, 0x81, 0x50, 0xFF, 0xC3, 0x82, 0x4F, 0xFF, 0xC2, 0x80, 0x4F, 0xFF, 0xC5, 0x83, 0x50, 0xFF, 0xC3, 0x81, 0x51, 0xFF, 0xC4, 0x81, 0x50, 0xFF, 0xC4, 0x81, 0x50, 0xFF,
++ 0xC4, 0x81, 0x50, 0xFF, 0xC4, 0x81, 0x50, 0xFF, 0xC4, 0x81, 0x50, 0xFF, 0xC4, 0x81, 0x50, 0xFF, 0xC4, 0x81, 0x50, 0xFF, 0xC4, 0x81, 0x50, 0xFF, 0xC3, 0x81, 0x50, 0xFF, 0xC7, 0x81, 0x52, 0xFF,
++ 0xC2, 0x80, 0x4F, 0xFF, 0xC6, 0x81, 0x50, 0xFF, 0xC4, 0x80, 0x51, 0xFF, 0xC4, 0x81, 0x50, 0xFF, 0xC2, 0x80, 0x4F, 0xFF, 0xEF, 0xDA, 0xC5, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC4, 0x81, 0x50, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF,
++ 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF,
++ 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF,
++ 0xAA, 0x48, 0x02, 0xFF, 0xA8, 0x48, 0x02, 0xFF, 0xB5, 0x6A, 0x36, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xB3, 0x5D, 0x21, 0xFF, 0xA9, 0x46, 0x02, 0xFF, 0xAB, 0x4A, 0x00, 0xFF, 0xBA, 0x77, 0x4A, 0xFF, 0xD9, 0xD7, 0xD7, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF,
++ 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE5, 0xE5, 0xE5, 0xFF, 0xB7, 0x6D, 0x3D, 0xFF,
++ 0xAB, 0x49, 0x03, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xB2, 0x77, 0x46, 0xFF, 0xE1, 0xDF, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFB, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xF2, 0xE6, 0xDC, 0xFF, 0xAF, 0x55, 0x15, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF,
++ 0xAB, 0x48, 0x04, 0xFF, 0xAC, 0x47, 0x02, 0xFF, 0xA9, 0x49, 0x03, 0xFF, 0xAA, 0x47, 0x03, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xA8, 0x49, 0x00, 0xFF, 0xA9, 0x49, 0x03, 0xFF, 0xAA, 0x48, 0x02, 0xFF,
++ 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAB, 0x48, 0x04, 0xFF, 0xA9, 0x47, 0x01, 0xFF, 0xAB, 0x49, 0x01, 0xFF, 0xA8, 0x48, 0x02, 0xFF, 0xA8, 0x48, 0x02, 0xFF, 0xA8, 0x47, 0x03, 0xFF,
++ 0xA8, 0x47, 0x03, 0xFF, 0xA9, 0x49, 0x03, 0xFF, 0xAC, 0x47, 0x02, 0xFF, 0xA8, 0x47, 0x05, 0xFF, 0xA6, 0x47, 0x02, 0xFF, 0xAB, 0x49, 0x01, 0xFF, 0xA8, 0x48, 0x02, 0xFF, 0xA8, 0x48, 0x02, 0xFF,
++ 0xAA, 0x48, 0x00, 0xFF, 0xA8, 0x49, 0x00, 0xFF, 0xA9, 0x49, 0x07, 0xFF, 0xDF, 0xDF, 0xDF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xA8, 0x47, 0x03, 0xFF, 0xA8, 0x47, 0x03, 0xFF,
++ 0xA8, 0x48, 0x02, 0xFF, 0xA6, 0x47, 0x01, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xA7, 0x48, 0x03, 0xFF, 0xA8, 0x48, 0x02, 0xFF, 0xA8, 0x48, 0x02, 0xFF, 0xA8, 0x48, 0x02, 0xFF, 0xA8, 0x48, 0x02, 0xFF,
++ 0xA8, 0x48, 0x02, 0xFF, 0xA8, 0x48, 0x02, 0xFF, 0xA8, 0x48, 0x02, 0xFF, 0xA8, 0x48, 0x02, 0xFF, 0xA8, 0x48, 0x02, 0xFF, 0xA8, 0x48, 0x02, 0xFF, 0xA7, 0x47, 0x01, 0xFF, 0xAD, 0x48, 0x04, 0xFF,
++ 0xA7, 0x48, 0x03, 0xFF, 0xA8, 0x49, 0x00, 0xFF, 0xA9, 0x49, 0x03, 0xFF, 0xCC, 0xAE, 0x9D, 0xFF, 0xF6, 0xF6, 0xF6, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC4, 0x81, 0x50, 0xFF, 0xAB, 0x49, 0x03, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF,
++ 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF,
++ 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xA8, 0x47, 0x03, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xA8, 0x48, 0x02, 0xFF,
++ 0xB5, 0x6A, 0x36, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBE, 0x79, 0x47, 0xFF,
++ 0xB4, 0x64, 0x2D, 0xFF, 0xBD, 0x95, 0x79, 0xFF, 0xCE, 0xC6, 0xC6, 0xFF, 0xDD, 0xE2, 0xE1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xD7, 0xA7, 0x85, 0xFF, 0xB8, 0x72, 0x3D, 0xFF, 0xC4, 0xA1, 0x8D, 0xFF,
++ 0xD1, 0xCF, 0xCF, 0xFF, 0xE1, 0xE0, 0xE2, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xED, 0xDB, 0xD0, 0xFF, 0xBD, 0x88, 0x63, 0xFF, 0xC3, 0xA0, 0x86, 0xFF, 0xC7, 0xB0, 0xA0, 0xFF, 0xC8, 0xB8, 0xAC, 0xFF,
++ 0xCC, 0xB9, 0xAC, 0xFF, 0xCB, 0xB8, 0xA9, 0xFF, 0xCB, 0xB8, 0xAB, 0xFF, 0xCA, 0xB9, 0xAC, 0xFF, 0xC9, 0xB7, 0xAC, 0xFF, 0xC8, 0xB8, 0xAC, 0xFF, 0xC9, 0xB8, 0xAB, 0xFF, 0xC9, 0xB8, 0xAB, 0xFF,
++ 0xC9, 0xB7, 0xAC, 0xFF, 0xC9, 0xB8, 0xAB, 0xFF, 0xC9, 0xB8, 0xAB, 0xFF, 0xC9, 0xB8, 0xAB, 0xFF, 0xC8, 0xB7, 0xAA, 0xFF, 0xCA, 0xB9, 0xAC, 0xFF, 0xC9, 0xB8, 0xAB, 0xFF, 0xC9, 0xB8, 0xAB, 0xFF,
++ 0xCA, 0xB7, 0xAA, 0xFF, 0xCB, 0xB8, 0xAB, 0xFF, 0xCA, 0xB9, 0xAC, 0xFF, 0xC8, 0xB8, 0xAC, 0xFF, 0xCB, 0xB7, 0xAC, 0xFF, 0xCD, 0xB7, 0xAB, 0xFF, 0xCB, 0xB7, 0xAC, 0xFF, 0xC8, 0xB9, 0xA9, 0xFF,
++ 0xCC, 0xBF, 0xB7, 0xFF, 0xD0, 0xD2, 0xD3, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xA7, 0x47, 0x01, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xA9, 0x47, 0x01, 0xFF, 0xA9, 0x45, 0x04, 0xFF, 0xAC, 0x47, 0x02, 0xFF,
++ 0xA9, 0x47, 0x01, 0xFF, 0xAA, 0x47, 0x03, 0xFF, 0xA9, 0x46, 0x02, 0xFF, 0xA9, 0x46, 0x02, 0xFF, 0xA9, 0x46, 0x02, 0xFF, 0xA9, 0x46, 0x02, 0xFF, 0xA9, 0x46, 0x02, 0xFF, 0xA9, 0x46, 0x02, 0xFF,
++ 0xA9, 0x46, 0x02, 0xFF, 0xA9, 0x46, 0x02, 0xFF, 0xAA, 0x47, 0x03, 0xFF, 0xA9, 0x47, 0x01, 0xFF, 0xAA, 0x47, 0x03, 0xFF, 0xA9, 0x46, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x46, 0x05, 0xFF,
++ 0xA9, 0x47, 0x01, 0xFF, 0xC5, 0xA4, 0x90, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xC3, 0x80, 0x4F, 0xFF, 0xA9, 0x46, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF,
++ 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF,
++ 0xAA, 0x48, 0x02, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xA7, 0x47, 0x01, 0xFF, 0xA8, 0x47, 0x03, 0xFF, 0xAA, 0x48, 0x02, 0xFF, 0xA7, 0x47, 0x01, 0xFF, 0xB4, 0x69, 0x35, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF,
++ 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xDD, 0xDC, 0xDE, 0xFF, 0xDD, 0xDB, 0xDB, 0xFF,
++ 0xEB, 0xEB, 0xEB, 0xFF, 0xFC, 0xFD, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xEC, 0xEA, 0xEA, 0xFF, 0xDB, 0xE0, 0xDF, 0xFF, 0xEE, 0xEE, 0xEE, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xF7, 0xF7, 0xF7, 0xFF, 0xE7, 0xE6, 0xE8, 0xFF, 0xF0, 0xEE, 0xED, 0xFF, 0xF4, 0xF4, 0xF4, 0xFF, 0xF7, 0xF5, 0xF5, 0xFF, 0xF6, 0xF5, 0xF7, 0xFF,
++ 0xF4, 0xF6, 0xF6, 0xFF, 0xF6, 0xF6, 0xF6, 0xFF, 0xF6, 0xF6, 0xF6, 0xFF, 0xF6, 0xF6, 0xF6, 0xFF, 0xF8, 0xF6, 0xF6, 0xFF, 0xF6, 0xF6, 0xF6, 0xFF, 0xF6, 0xF6, 0xF6, 0xFF, 0xF6, 0xF7, 0xF5, 0xFF,
++ 0xF8, 0xF5, 0xF7, 0xFF, 0xF8, 0xF5, 0xF7, 0xFF, 0xF6, 0xF6, 0xF6, 0xFF, 0xF4, 0xF6, 0xF6, 0xFF, 0xF8, 0xF6, 0xF6, 0xFF, 0xF8, 0xF6, 0xF6, 0xFF, 0xF5, 0xF7, 0xF7, 0xFF, 0xF3, 0xF6, 0xF4, 0xFF,
++ 0xF8, 0xF6, 0xF5, 0xFF, 0xF8, 0xF6, 0xF6, 0xFF, 0xF4, 0xF6, 0xF6, 0xFF, 0xF6, 0xF6, 0xF6, 0xFF, 0xF6, 0xF5, 0xF7, 0xFF, 0xF6, 0xF5, 0xF7, 0xFF, 0xF8, 0xF6, 0xF5, 0xFF, 0xFB, 0xF9, 0xF8, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA9, 0x46, 0x02, 0xFF, 0xA7, 0x47, 0x01, 0xFF, 0xA8, 0x47, 0x03, 0xFF, 0xA8, 0x47, 0x03, 0xFF,
++ 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF,
++ 0xA8, 0x48, 0x02, 0xFF, 0xA6, 0x47, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA8, 0x47, 0x03, 0xFF, 0xA8, 0x47, 0x03, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xC4, 0xA5, 0x90, 0xFF,
++ 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC2, 0x80, 0x50, 0xFF, 0xA7, 0x46, 0x02, 0xFF,
++ 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF,
++ 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF,
++ 0xA8, 0x47, 0x03, 0xFF, 0xA8, 0x47, 0x03, 0xFF, 0xA8, 0x48, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xB2, 0x69, 0x35, 0xFF, 0xDF, 0xDC, 0xDE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFB, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA7, 0x46, 0x02, 0xFF,
++ 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA9, 0x46, 0x02, 0xFF, 0xA7, 0x47, 0x01, 0xFF, 0xA8, 0x47, 0x03, 0xFF, 0xA8, 0x47, 0x03, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF,
++ 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA8, 0x47, 0x03, 0xFF, 0xA6, 0x47, 0x02, 0xFF,
++ 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA8, 0x47, 0x03, 0xFF, 0xA8, 0x47, 0x03, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xC4, 0xA5, 0x90, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC2, 0x80, 0x50, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF,
++ 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF,
++ 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF,
++ 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xB2, 0x69, 0x35, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFC, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA6, 0x47, 0x02, 0xFF,
++ 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x47, 0x01, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF,
++ 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF,
++ 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xC4, 0xA5, 0x90, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC2, 0x80, 0x50, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF,
++ 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF,
++ 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA7, 0x46, 0x02, 0xFF,
++ 0xB2, 0x69, 0x35, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFC, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA6, 0x45, 0x01, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x45, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF,
++ 0xA7, 0x46, 0x02, 0xFF, 0xA6, 0x47, 0x02, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF,
++ 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA7, 0x46, 0x02, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x45, 0x01, 0xFF, 0xA6, 0x47, 0x02, 0xFF, 0xA6, 0x47, 0x02, 0xFF, 0xA6, 0x47, 0x02, 0xFF,
++ 0xA6, 0x47, 0x02, 0xFF, 0xC4, 0xA5, 0x90, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xC2, 0x80, 0x50, 0xFF, 0xA7, 0x46, 0x04, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF,
++ 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF,
++ 0xA5, 0x46, 0x01, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA6, 0x47, 0x02, 0xFF, 0xA7, 0x46, 0x04, 0xFF, 0xA6, 0x47, 0x02, 0xFF, 0xA6, 0x47, 0x02, 0xFF, 0xB2, 0x69, 0x37, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xA7, 0x46, 0x04, 0xFF, 0xA7, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA7, 0x46, 0x04, 0xFF, 0xA6, 0x47, 0x02, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x47, 0x02, 0xFF,
++ 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF,
++ 0xA7, 0x46, 0x02, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x47, 0x02, 0xFF, 0xA6, 0x47, 0x02, 0xFF, 0xA6, 0x47, 0x02, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x47, 0x02, 0xFF, 0xC3, 0xA6, 0x91, 0xFF,
++ 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC2, 0x80, 0x50, 0xFF, 0xA6, 0x46, 0x04, 0xFF,
++ 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF,
++ 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF,
++ 0xA6, 0x46, 0x04, 0xFF, 0xA7, 0x46, 0x04, 0xFF, 0xA6, 0x47, 0x02, 0xFF, 0xA6, 0x47, 0x02, 0xFF, 0xB0, 0x69, 0x37, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xB6, 0x67, 0x2E, 0xFF, 0xB0, 0x5C, 0x22, 0xFF, 0xB9, 0x69, 0x2E, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF,
++ 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xEC, 0xD6, 0xCA, 0xFF,
++ 0xAE, 0x5C, 0x22, 0xFF, 0xB4, 0x5C, 0x26, 0xFF, 0xDF, 0xB7, 0x9E, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA7, 0x46, 0x04, 0xFF,
++ 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA5, 0x46, 0x01, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF,
++ 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF,
++ 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xC3, 0xA5, 0x92, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0x7F, 0x52, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF,
++ 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF,
++ 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF,
++ 0xA6, 0x46, 0x04, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xB0, 0x69, 0x37, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xA9, 0x51, 0x11, 0xFF, 0xA6, 0x45, 0x05, 0xFF, 0xA7, 0x4F, 0x0F, 0xFF, 0xDA, 0xD9, 0xDB, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFC, 0xFF, 0xFD, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFC, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE7, 0xD1, 0xBF, 0xFF, 0xA7, 0x45, 0x05, 0xFF, 0xA5, 0x46, 0x01, 0xFF,
++ 0xBF, 0x99, 0x7B, 0xFF, 0xEC, 0xEE, 0xEF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFC, 0xFE, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA6, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF,
++ 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF,
++ 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF,
++ 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xC2, 0xA4, 0x91, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBF, 0x7E, 0x51, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF,
++ 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF,
++ 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA5, 0x44, 0x04, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF,
++ 0xB0, 0x69, 0x37, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xAD, 0x50, 0x13, 0xFF, 0xA6, 0x46, 0x04, 0xFF, 0xA5, 0x4D, 0x0D, 0xFF, 0xD4, 0xD3, 0xD5, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xF0, 0xE3, 0xD5, 0xFF, 0xC6, 0x86, 0x5D, 0xFF, 0xB6, 0x7B, 0x4D, 0xFF, 0xC5, 0xAB, 0x9A, 0xFF, 0xEA, 0xE9, 0xEB, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA6, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA5, 0x44, 0x04, 0xFF, 0xA3, 0x45, 0x03, 0xFF,
++ 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF,
++ 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF,
++ 0xA5, 0x45, 0x03, 0xFF, 0xC3, 0xA5, 0x92, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xBF, 0x7E, 0x51, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF,
++ 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF,
++ 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x44, 0x04, 0xFF, 0xA5, 0x44, 0x04, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xB0, 0x69, 0x37, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xA9, 0x50, 0x13, 0xFF, 0xA5, 0x44, 0x04, 0xFF,
++ 0xA6, 0x4E, 0x0E, 0xFF, 0xD4, 0xD3, 0xD5, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0xF6, 0xFF, 0xF9, 0xF3, 0xEE, 0xFF, 0xF7, 0xF3, 0xF2, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFA, 0xFF,
++ 0xE9, 0xD9, 0xCC, 0xFF, 0xE6, 0xCB, 0xB6, 0xFF, 0xF1, 0xE6, 0xE2, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF,
++ 0xFE, 0xFF, 0xFD, 0xFF, 0xFD, 0xF4, 0xF1, 0xFF, 0xE9, 0xCE, 0xB9, 0xFF, 0xE2, 0xCF, 0xC2, 0xFF, 0xFC, 0xF8, 0xF3, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xF8, 0xF3, 0xF0, 0xFF, 0xFA, 0xF4, 0xEF, 0xFF,
++ 0xFA, 0xF9, 0xF5, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFA, 0xF3, 0xEA, 0xFF, 0xE5, 0xCC, 0xBC, 0xFF, 0xE7, 0xCD, 0xBC, 0xFF,
++ 0xF7, 0xED, 0xE3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFC, 0xFF, 0xF8, 0xF3, 0xF2, 0xFF, 0xF8, 0xF3, 0xF2, 0xFF,
++ 0xFE, 0xFA, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF4, 0xEA, 0xE0, 0xFF, 0xE6, 0xCB, 0xB7, 0xFF, 0xE9, 0xD9, 0xC9, 0xFF, 0xFF, 0xFE, 0xFA, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFC, 0xFF, 0xF0, 0xEB, 0xE8, 0xFF, 0xDD, 0xD8, 0xD5, 0xFF, 0xE2, 0xDD, 0xDE, 0xFF, 0xF4, 0xF2, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xF9, 0xF8, 0xFF, 0xE8, 0xD4, 0xC9, 0xFF, 0xE6, 0xC8, 0xAF, 0xFF, 0xEC, 0xD8, 0xCD, 0xFF, 0xFE, 0xFB, 0xF7, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xA2, 0x44, 0x02, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA3, 0x45, 0x03, 0xFF,
++ 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF,
++ 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xC3, 0xA6, 0x91, 0xFF,
++ 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBF, 0x7E, 0x51, 0xFF, 0xA5, 0x45, 0x03, 0xFF,
++ 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF,
++ 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF,
++ 0xA3, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xAF, 0x68, 0x36, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA9, 0x50, 0x13, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA5, 0x4C, 0x0F, 0xFF, 0xD4, 0xD4, 0xD4, 0xFF,
++ 0xFB, 0xFF, 0xFF, 0xFF, 0xD2, 0xA0, 0x82, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA4, 0x47, 0x02, 0xFF, 0xEC, 0xD6, 0xCA, 0xFF, 0xB3, 0x5E, 0x26, 0xFF, 0xA5, 0x44, 0x05, 0xFF, 0xA6, 0x45, 0x03, 0xFF,
++ 0xA5, 0x46, 0x01, 0xFF, 0xC2, 0x83, 0x5D, 0xFF, 0xFD, 0xFC, 0xF8, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xD5, 0xAE, 0x8E, 0xFF, 0xA6, 0x4C, 0x0C, 0xFF,
++ 0xA6, 0x44, 0x04, 0xFF, 0xA3, 0x46, 0x01, 0xFF, 0xA9, 0x51, 0x11, 0xFF, 0xE1, 0xC0, 0xAC, 0xFF, 0xA9, 0x50, 0x13, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xCC, 0x94, 0x71, 0xFF, 0xFD, 0xFD, 0xFD, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFA, 0xFB, 0xF7, 0xFF, 0xCE, 0x97, 0x72, 0xFF, 0xA5, 0x47, 0x05, 0xFF, 0xA5, 0x44, 0x05, 0xFF, 0xA6, 0x45, 0x03, 0xFF, 0xA1, 0x46, 0x03, 0xFF, 0xBE, 0x7F, 0x53, 0xFF,
++ 0xF9, 0xF3, 0xEE, 0xFF, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF5, 0xE8, 0xE0, 0xFF, 0xA3, 0x44, 0x05, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xD3, 0xA4, 0x84, 0xFF, 0xC3, 0x83, 0x5A, 0xFF,
++ 0xA5, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA6, 0x45, 0x01, 0xFF, 0xAE, 0x5D, 0x24, 0xFF, 0xED, 0xDF, 0xD3, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xEA, 0xD2, 0xC0, 0xFF,
++ 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x46, 0x01, 0xFF, 0xD5, 0xAA, 0x8F, 0xFF, 0xFD, 0xFD, 0xFD, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xD3, 0xA7, 0x88, 0xFF, 0xAB, 0x4D, 0x0C, 0xFF,
++ 0xA6, 0x46, 0x04, 0xFF, 0xA5, 0x44, 0x04, 0xFF, 0xA6, 0x45, 0x05, 0xFF, 0xAA, 0x53, 0x15, 0xFF, 0xDD, 0xB9, 0xA1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA3, 0x45, 0x03, 0xFF,
++ 0xA5, 0x44, 0x04, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA5, 0x44, 0x04, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF,
++ 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA5, 0x44, 0x04, 0xFF, 0xA5, 0x45, 0x03, 0xFF,
++ 0xA5, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xC3, 0xA6, 0x91, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBF, 0x7E, 0x51, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF,
++ 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF,
++ 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA5, 0x45, 0x03, 0xFF,
++ 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xAF, 0x68, 0x36, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA7, 0x50, 0x12, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA5, 0x4C, 0x0F, 0xFF, 0xD4, 0xD4, 0xD4, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xD6, 0xA3, 0x83, 0xFF,
++ 0xA3, 0x45, 0x03, 0xFF, 0xA1, 0x46, 0x03, 0xFF, 0xA7, 0x4D, 0x0D, 0xFF, 0xA5, 0x4E, 0x0E, 0xFF, 0xAD, 0x60, 0x27, 0xFF, 0xA2, 0x46, 0x05, 0xFF, 0xA1, 0x45, 0x04, 0xFF, 0xA3, 0x45, 0x04, 0xFF,
++ 0xC8, 0xA3, 0x89, 0xFF, 0xFB, 0xFD, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDE, 0xB8, 0xA0, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA5, 0x44, 0x00, 0xFF, 0xA2, 0x47, 0x04, 0xFF, 0xAC, 0x5F, 0x27, 0xFF,
++ 0xA5, 0x4E, 0x10, 0xFF, 0xA4, 0x48, 0x07, 0xFF, 0xA3, 0x47, 0x06, 0xFF, 0xA2, 0x45, 0x00, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xE8, 0xE5, 0xE7, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xC6, 0x8C, 0x62, 0xFF,
++ 0xA2, 0x44, 0x02, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA6, 0x4F, 0x11, 0xFF, 0xAB, 0x55, 0x1F, 0xFF, 0xA7, 0x46, 0x04, 0xFF, 0xA5, 0x44, 0x04, 0xFF, 0xB0, 0x67, 0x33, 0xFF, 0xFA, 0xFA, 0xFA, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xF5, 0xE8, 0xE0, 0xFF, 0xA3, 0x47, 0x00, 0xFF, 0xA4, 0x47, 0x02, 0xFF, 0xA3, 0x48, 0x0B, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xAA, 0x5D, 0x25, 0xFF, 0xA9, 0x4D, 0x12, 0xFF,
++ 0xA0, 0x45, 0x02, 0xFF, 0xA3, 0x44, 0x05, 0xFF, 0xB2, 0x64, 0x2F, 0xFF, 0xF7, 0xF6, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE7, 0xCF, 0xC3, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA4, 0x46, 0x05, 0xFF,
++ 0xBF, 0x93, 0x76, 0xFF, 0xEB, 0xEB, 0xEB, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xD3, 0xA1, 0x83, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA1, 0x47, 0x06, 0xFF, 0xA9, 0x54, 0x1C, 0xFF,
++ 0xA2, 0x47, 0x04, 0xFF, 0xA2, 0x47, 0x04, 0xFF, 0xA4, 0x44, 0x02, 0xFF, 0xDB, 0xC2, 0xAE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA4, 0x43, 0x03, 0xFF, 0xA3, 0x45, 0x04, 0xFF,
++ 0xA3, 0x45, 0x04, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x02, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA5, 0x45, 0x03, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xC2, 0xA5, 0x90, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBF, 0x7E, 0x51, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x02, 0xFF, 0xA2, 0x44, 0x02, 0xFF, 0xA2, 0x44, 0x02, 0xFF, 0xA3, 0x45, 0x04, 0xFF,
++ 0xAF, 0x67, 0x37, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xA7, 0x50, 0x12, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA5, 0x4C, 0x0F, 0xFF, 0xD4, 0xD4, 0xD4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xCF, 0xA1, 0x7F, 0xFF, 0xA2, 0x45, 0x00, 0xFF, 0xA4, 0x43, 0x03, 0xFF,
++ 0xAD, 0x60, 0x2F, 0xFF, 0xD2, 0xC9, 0xC5, 0xFF, 0xD3, 0xD2, 0xD4, 0xFF, 0xC6, 0xA1, 0x87, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xB2, 0x76, 0x4C, 0xFF, 0xED, 0xEC, 0xEE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xAB, 0x59, 0x1F, 0xFF, 0xA6, 0x44, 0x04, 0xFF, 0xA3, 0x47, 0x06, 0xFF, 0xC5, 0xAF, 0xA3, 0xFF, 0xD1, 0xD2, 0xD0, 0xFF, 0xD8, 0xD0, 0xD1, 0xFF, 0xAE, 0x66, 0x30, 0xFF,
++ 0xA3, 0x46, 0x01, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xB6, 0x83, 0x5B, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xED, 0xDF, 0xD3, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA5, 0x43, 0x03, 0xFF, 0xAD, 0x6B, 0x3A, 0xFF,
++ 0xCE, 0xCC, 0xCB, 0xFF, 0xD3, 0xD5, 0xD6, 0xFF, 0xBE, 0x98, 0x78, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA4, 0x44, 0x02, 0xFF, 0xCA, 0xAB, 0x96, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xF3, 0xE7, 0xE3, 0xFF,
++ 0xA4, 0x44, 0x02, 0xFF, 0xA5, 0x44, 0x02, 0xFF, 0xA5, 0x47, 0x06, 0xFF, 0xC5, 0xAC, 0x9C, 0xFF, 0xD2, 0xD3, 0xD1, 0xFF, 0xD6, 0xCB, 0xC7, 0xFF, 0xA6, 0x50, 0x14, 0xFF, 0xA4, 0x43, 0x03, 0xFF,
++ 0xA3, 0x45, 0x03, 0xFF, 0xDA, 0xD5, 0xD6, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xE9, 0xD1, 0xBF, 0xFF, 0xA5, 0x44, 0x04, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xBC, 0x92, 0x75, 0xFF, 0xEC, 0xEC, 0xEC, 0xFF,
++ 0xFA, 0xEF, 0xE7, 0xFF, 0xA6, 0x49, 0x0C, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xAA, 0x57, 0x1F, 0xFF, 0xCE, 0xC2, 0xBE, 0xFF, 0xD5, 0xD3, 0xD3, 0xFF, 0xC8, 0xB5, 0xA8, 0xFF, 0xA3, 0x45, 0x04, 0xFF,
++ 0xA3, 0x45, 0x03, 0xFF, 0xAC, 0x67, 0x36, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x02, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x02, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xC2, 0xA5, 0x90, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xBF, 0x7E, 0x51, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x02, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x02, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xAE, 0x66, 0x36, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA7, 0x50, 0x12, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA5, 0x4C, 0x0F, 0xFF, 0xD4, 0xD4, 0xD4, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xCF, 0xA0, 0x80, 0xFF, 0xA4, 0x43, 0x03, 0xFF, 0xA4, 0x43, 0x04, 0xFF, 0xC0, 0x9C, 0x84, 0xFF, 0xD6, 0xDB, 0xDA, 0xFF,
++ 0xFC, 0xFB, 0xFD, 0xFF, 0xF6, 0xF0, 0xE9, 0xFF, 0xA3, 0x44, 0x05, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xB3, 0x6F, 0x44, 0xFF, 0xDF, 0xE1, 0xE1, 0xFF, 0xF2, 0xE6, 0xDC, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA0, 0x43, 0x04, 0xFF, 0xAF, 0x6E, 0x41, 0xFF, 0xD3, 0xD3, 0xD3, 0xFF, 0xF3, 0xF5, 0xF5, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xE1, 0xCA, 0xBA, 0xFF, 0xA2, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x06, 0xFF,
++ 0xB6, 0x82, 0x5D, 0xFF, 0xE3, 0xE5, 0xE6, 0xFF, 0xD3, 0xA7, 0x88, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA2, 0x44, 0x02, 0xFF, 0xC4, 0xA9, 0x95, 0xFF, 0xE1, 0xDF, 0xDF, 0xFF, 0xF9, 0xFE, 0xFC, 0xFF,
++ 0xFF, 0xFB, 0xFD, 0xFF, 0xA6, 0x47, 0x08, 0xFF, 0xA2, 0x43, 0x04, 0xFF, 0xB6, 0x7B, 0x53, 0xFF, 0xF1, 0xEF, 0xEE, 0xFF, 0xF0, 0xE9, 0xE0, 0xFF, 0xA3, 0x44, 0x05, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xAF, 0x66, 0x34, 0xFF, 0xD0, 0xD2, 0xD2, 0xFF, 0xF1, 0xF3, 0xF4, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xBE, 0x7C, 0x4C, 0xFF, 0xA1, 0x44, 0x05, 0xFF, 0xA5, 0x44, 0x04, 0xFF, 0xCF, 0xC7, 0xC7, 0xFF,
++ 0xFF, 0xFE, 0xFD, 0xFF, 0xEA, 0xD0, 0xC2, 0xFF, 0xA2, 0x44, 0x02, 0xFF, 0xA3, 0x46, 0x01, 0xFF, 0xBC, 0x93, 0x7A, 0xFF, 0xEA, 0xE9, 0xEB, 0xFF, 0xDE, 0xBE, 0xA7, 0xFF, 0xA2, 0x44, 0x02, 0xFF,
++ 0xA4, 0x43, 0x03, 0xFF, 0xB7, 0x8F, 0x72, 0xFF, 0xDA, 0xD7, 0xD9, 0xFF, 0xF6, 0xF9, 0xF7, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xDD, 0xBF, 0xAC, 0xFF, 0xC8, 0xB7, 0xAE, 0xFF, 0xD0, 0xCE, 0xCE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA3, 0x45, 0x04, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x02, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xC2, 0xA4, 0x91, 0xFF,
++ 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBF, 0x7E, 0x51, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xAE, 0x66, 0x36, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA7, 0x50, 0x12, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA5, 0x4C, 0x0F, 0xFF, 0xD4, 0xD4, 0xD4, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xCF, 0xA0, 0x81, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xC5, 0xAE, 0x9E, 0xFF, 0xF0, 0xEE, 0xEE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFD, 0xFD, 0xFF,
++ 0xA4, 0x43, 0x04, 0xFF, 0xA2, 0x45, 0x00, 0xFF, 0xB2, 0x6F, 0x42, 0xFF, 0xE0, 0xE0, 0xE0, 0xFF, 0xEA, 0xD2, 0xC6, 0xFF, 0x9E, 0x45, 0x02, 0xFF, 0xA4, 0x43, 0x03, 0xFF, 0xB4, 0x80, 0x5B, 0xFF,
++ 0xDF, 0xDF, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xF2, 0xE9, 0xDF, 0xFF, 0xA2, 0x44, 0x02, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xB9, 0x82, 0x5D, 0xFF, 0xE6, 0xE6, 0xE6, 0xFF,
++ 0xC9, 0x90, 0x69, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA4, 0x43, 0x04, 0xFF, 0xA8, 0x4B, 0x0E, 0xFF, 0xA5, 0x4D, 0x11, 0xFF, 0xA8, 0x51, 0x13, 0xFF, 0xA6, 0x4E, 0x12, 0xFF, 0x9E, 0x45, 0x02, 0xFF,
++ 0xA3, 0x45, 0x04, 0xFF, 0xAC, 0x67, 0x35, 0xFF, 0xE2, 0xE4, 0xE4, 0xFF, 0xF2, 0xE9, 0xE0, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA1, 0x46, 0x03, 0xFF, 0xB5, 0x78, 0x50, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xC2, 0x8A, 0x61, 0xFF, 0xA2, 0x44, 0x02, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xCF, 0xC9, 0xC4, 0xFF, 0xFB, 0xFD, 0xFE, 0xFF, 0xE8, 0xD0, 0xBE, 0xFF,
++ 0xA0, 0x45, 0x02, 0xFF, 0xA6, 0x42, 0x07, 0xFF, 0xBC, 0x92, 0x75, 0xFF, 0xEA, 0xEC, 0xEC, 0xFF, 0xD4, 0xA8, 0x89, 0xFF, 0xA4, 0x44, 0x02, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xC1, 0xA2, 0x8D, 0xFF,
++ 0xEA, 0xEB, 0xE9, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xF3, 0xF1, 0xF0, 0xFF, 0xF6, 0xF6, 0xF6, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xA0, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xC2, 0xA4, 0x91, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBD, 0x7F, 0x51, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA1, 0x45, 0x04, 0xFF, 0xA3, 0x45, 0x04, 0xFF,
++ 0xA0, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xAC, 0x67, 0x36, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA7, 0x50, 0x12, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA4, 0x4D, 0x0F, 0xFF, 0xD4, 0xD3, 0xD5, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xD0, 0xA1, 0x81, 0xFF,
++ 0xA1, 0x46, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xC8, 0xAE, 0xA0, 0xFF, 0xF1, 0xF4, 0xF2, 0xFF, 0xFA, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA4, 0x43, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF,
++ 0xAF, 0x71, 0x43, 0xFF, 0xDF, 0xDE, 0xE2, 0xFF, 0xED, 0xD6, 0xC7, 0xFF, 0xA1, 0x45, 0x04, 0xFF, 0xA2, 0x44, 0x02, 0xFF, 0xB7, 0x7A, 0x52, 0xFF, 0xE7, 0xE5, 0xE5, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xF0, 0xE1, 0xD8, 0xFF, 0xA1, 0x45, 0x04, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xB6, 0x82, 0x5E, 0xFF, 0xE1, 0xE5, 0xE6, 0xFF, 0xC6, 0x8F, 0x68, 0xFF, 0xA1, 0x45, 0x04, 0xFF,
++ 0xA1, 0x46, 0x01, 0xFF, 0xA9, 0x60, 0x2E, 0xFF, 0xB1, 0x66, 0x38, 0xFF, 0xAA, 0x67, 0x36, 0xFF, 0xA9, 0x68, 0x35, 0xFF, 0xAE, 0x66, 0x36, 0xFF, 0xAF, 0x67, 0x37, 0xFF, 0xB4, 0x7A, 0x56, 0xFF,
++ 0xE0, 0xDE, 0xDD, 0xFF, 0xF7, 0xE7, 0xE1, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xB1, 0x78, 0x51, 0xFF, 0xE2, 0xE2, 0xE2, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xC6, 0x88, 0x62, 0xFF, 0xA2, 0x45, 0x00, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xD0, 0xC6, 0xC6, 0xFF, 0xF8, 0xFD, 0xFC, 0xFF, 0xE9, 0xCF, 0xC1, 0xFF, 0xA3, 0x44, 0x05, 0xFF, 0x9F, 0x43, 0x02, 0xFF,
++ 0xBC, 0x94, 0x77, 0xFF, 0xE9, 0xEC, 0xEA, 0xFF, 0xD3, 0xA7, 0x88, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xBF, 0x9B, 0x83, 0xFF, 0xEF, 0xEE, 0xF0, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF,
++ 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF,
++ 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF,
++ 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xC2, 0xA4, 0x91, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xBC, 0x7D, 0x51, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF,
++ 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF,
++ 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xAC, 0x67, 0x36, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xA7, 0x50, 0x12, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA3, 0x4C, 0x0E, 0xFF, 0xD2, 0xD4, 0xD5, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xCF, 0xA2, 0x81, 0xFF, 0xA3, 0x45, 0x04, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0xC6, 0xAE, 0xA2, 0xFF, 0xF3, 0xF2, 0xF4, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x9E, 0x44, 0x03, 0xFF, 0xA4, 0x44, 0x02, 0xFF, 0xB0, 0x6F, 0x42, 0xFF, 0xE0, 0xE0, 0xE0, 0xFF,
++ 0xF4, 0xF0, 0xEB, 0xFF, 0xA3, 0x43, 0x01, 0xFF, 0x9F, 0x45, 0x04, 0xFF, 0xA7, 0x59, 0x24, 0xFF, 0xE1, 0xE1, 0xE1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xD6, 0xAD, 0x8D, 0xFF,
++ 0xA3, 0x45, 0x04, 0xFF, 0x9F, 0x44, 0x01, 0xFF, 0xB7, 0x82, 0x5D, 0xFF, 0xE7, 0xE3, 0xE8, 0xFF, 0xD3, 0xA7, 0x8A, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0x9D, 0x42, 0x05, 0xFF, 0xC2, 0xA7, 0x93, 0xFF,
++ 0xDC, 0xD9, 0xDB, 0xFF, 0xDC, 0xDD, 0xDB, 0xFF, 0xDB, 0xD9, 0xD9, 0xFF, 0xD1, 0xC0, 0xB3, 0xFF, 0xDB, 0xD7, 0xD6, 0xFF, 0xDB, 0xDD, 0xDE, 0xFF, 0xE3, 0xE2, 0xE4, 0xFF, 0xF2, 0xE9, 0xE0, 0xFF,
++ 0xA1, 0x43, 0x02, 0xFF, 0xA5, 0x45, 0x03, 0xFF, 0xB0, 0x78, 0x4F, 0xFF, 0xE2, 0xE2, 0xE2, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xC3, 0x8C, 0x61, 0xFF, 0xA0, 0x44, 0x03, 0xFF,
++ 0xA0, 0x44, 0x03, 0xFF, 0xCE, 0xC7, 0xC4, 0xFF, 0xFD, 0xFD, 0xFD, 0xFF, 0xE8, 0xD0, 0xBE, 0xFF, 0x9E, 0x45, 0x02, 0xFF, 0xA2, 0x44, 0x02, 0xFF, 0xB8, 0x93, 0x77, 0xFF, 0xEB, 0xEA, 0xEC, 0xFF,
++ 0xE0, 0xC0, 0xAD, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA3, 0x45, 0x03, 0xFF, 0xB6, 0x83, 0x63, 0xFF, 0xF0, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBE, 0x80, 0x52, 0xFF,
++ 0xBE, 0x74, 0x44, 0xFF, 0xCA, 0x98, 0x74, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF,
++ 0x9F, 0x42, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF,
++ 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA1, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF,
++ 0x9F, 0x43, 0x02, 0xFF, 0xC1, 0xA3, 0x90, 0xFF, 0xF1, 0xF1, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xBC, 0x7D, 0x51, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF,
++ 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF,
++ 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xAC, 0x67, 0x36, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA6, 0x4F, 0x11, 0xFF, 0xA2, 0x43, 0x04, 0xFF,
++ 0xA3, 0x4B, 0x0F, 0xFF, 0xD2, 0xD4, 0xD5, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xCF, 0xA2, 0x81, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0xA2, 0x44, 0x02, 0xFF, 0xC5, 0xAE, 0x9E, 0xFF, 0xF3, 0xF2, 0xF6, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA1, 0x42, 0x03, 0xFF, 0x9E, 0x44, 0x04, 0xFF, 0xB1, 0x70, 0x44, 0xFF, 0xE0, 0xE0, 0xE0, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xB9, 0x74, 0x43, 0xFF,
++ 0xA1, 0x42, 0x03, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0xB4, 0x78, 0x4E, 0xFF, 0xE6, 0xCE, 0xBC, 0xFF, 0xD5, 0xAA, 0x8F, 0xFF, 0xA2, 0x4B, 0x0D, 0xFF, 0x9E, 0x41, 0x02, 0xFF, 0x9E, 0x45, 0x02, 0xFF,
++ 0xB8, 0x7F, 0x5F, 0xFF, 0xE4, 0xE6, 0xE6, 0xFF, 0xF0, 0xDF, 0xD6, 0xFF, 0xA3, 0x44, 0x00, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xAC, 0x61, 0x2D, 0xFF, 0xEB, 0xE5, 0xDE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xD5, 0xA9, 0x8C, 0xFF, 0xA2, 0x43, 0x04, 0xFF, 0xA1, 0x44, 0x05, 0xFF, 0xD1, 0xA8, 0x88, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xF3, 0xE7, 0xDD, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0x9F, 0x43, 0x02, 0xFF,
++ 0xB5, 0x77, 0x51, 0xFF, 0xE2, 0xE1, 0xE3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xC3, 0x88, 0x60, 0xFF, 0xA3, 0x42, 0x02, 0xFF, 0x9F, 0x42, 0x03, 0xFF, 0xCF, 0xC8, 0xC5, 0xFF,
++ 0xFA, 0xFB, 0xFF, 0xFF, 0xE7, 0xD0, 0xC0, 0xFF, 0xA1, 0x43, 0x02, 0xFF, 0xA1, 0x43, 0x02, 0xFF, 0xBD, 0x91, 0x79, 0xFF, 0xEC, 0xEA, 0xE9, 0xFF, 0xF8, 0xF5, 0xF0, 0xFF, 0xA5, 0x49, 0x0E, 0xFF,
++ 0xA2, 0x43, 0x04, 0xFF, 0xA2, 0x49, 0x0C, 0xFF, 0xCF, 0xB5, 0xA4, 0xFF, 0xF9, 0xF6, 0xEE, 0xFF, 0xD7, 0xB5, 0x9D, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0xA0, 0x43, 0x06, 0xFF, 0xB0, 0x6E, 0x3D, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x43, 0x06, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA1, 0x43, 0x02, 0xFF, 0xA0, 0x43, 0x06, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0xA3, 0x42, 0x02, 0xFF,
++ 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF,
++ 0x9F, 0x42, 0x03, 0xFF, 0xA1, 0x41, 0x05, 0xFF, 0x9E, 0x44, 0x03, 0xFF, 0xA1, 0x43, 0x02, 0xFF, 0xA2, 0x43, 0x04, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0xC2, 0xA4, 0x91, 0xFF,
++ 0xEF, 0xF2, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBD, 0x7C, 0x4F, 0xFF, 0x9E, 0x44, 0x03, 0xFF,
++ 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF,
++ 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF,
++ 0xA0, 0x43, 0x04, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0xAD, 0x66, 0x3A, 0xFF, 0xDC, 0xDB, 0xDD, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xA7, 0x4E, 0x15, 0xFF, 0xA1, 0x42, 0x03, 0xFF, 0xA3, 0x4C, 0x0E, 0xFF, 0xD4, 0xD3, 0xD5, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xCF, 0xA0, 0x81, 0xFF, 0xA1, 0x43, 0x02, 0xFF, 0xA1, 0x43, 0x02, 0xFF, 0xC3, 0xAE, 0x9F, 0xFF, 0xF5, 0xF3, 0xF3, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xA1, 0x42, 0x03, 0xFF, 0x9E, 0x44, 0x04, 0xFF, 0xB2, 0x6D, 0x45, 0xFF, 0xE0, 0xDF, 0xE1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xED, 0xDF, 0xD3, 0xFF, 0x9F, 0x4A, 0x0C, 0xFF, 0xA1, 0x42, 0x03, 0xFF,
++ 0xA4, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0x9D, 0x44, 0x01, 0xFF, 0xAB, 0x5B, 0x24, 0xFF, 0xA1, 0x42, 0x03, 0xFF, 0x9D, 0x43, 0x02, 0xFF, 0xB4, 0x82, 0x5E, 0xFF, 0xE5, 0xE5, 0xE5, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xC5, 0x8B, 0x67, 0xFF, 0x9F, 0x42, 0x03, 0xFF, 0x9D, 0x43, 0x03, 0xFF, 0xA1, 0x46, 0x09, 0xFF, 0xAC, 0x54, 0x1E, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA0, 0x43, 0x06, 0xFF,
++ 0xA5, 0x50, 0x18, 0xFF, 0xCB, 0xC5, 0xC0, 0xFF, 0xEC, 0xEA, 0xEA, 0xFF, 0xF2, 0xE7, 0xDF, 0xFF, 0xA2, 0x43, 0x04, 0xFF, 0x9F, 0x42, 0x03, 0xFF, 0xB3, 0x78, 0x51, 0xFF, 0xE0, 0xE2, 0xE3, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xC3, 0x89, 0x5F, 0xFF, 0x9F, 0x42, 0x03, 0xFF, 0x9E, 0x43, 0x06, 0xFF, 0xCF, 0xC8, 0xC5, 0xFF, 0xFC, 0xFC, 0xFC, 0xFF, 0xE8, 0xCF, 0xBF, 0xFF,
++ 0x9E, 0x43, 0x06, 0xFF, 0xA1, 0x43, 0x02, 0xFF, 0xBB, 0x93, 0x76, 0xFF, 0xEE, 0xEC, 0xEC, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xD5, 0xB0, 0x96, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0xA1, 0x43, 0x01, 0xFF,
++ 0x9F, 0x43, 0x02, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0xA1, 0x43, 0x02, 0xFF, 0xA1, 0x47, 0x07, 0xFF, 0xC8, 0xB2, 0xA6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xA1, 0x42, 0x03, 0xFF,
++ 0xA0, 0x44, 0x03, 0xFF, 0x9B, 0x43, 0x03, 0xFF, 0xA4, 0x43, 0x04, 0xFF, 0x9D, 0x44, 0x01, 0xFF, 0x9D, 0x43, 0x03, 0xFF, 0x9E, 0x44, 0x03, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF,
++ 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0x9D, 0x43, 0x02, 0xFF,
++ 0xA1, 0x42, 0x03, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0x9D, 0x44, 0x01, 0xFF, 0x9F, 0x42, 0x03, 0xFF, 0xA0, 0x43, 0x06, 0xFF, 0xC2, 0xA4, 0x93, 0xFF, 0xF3, 0xF1, 0xF1, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xBF, 0x7E, 0x51, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF,
++ 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF,
++ 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x44, 0x01, 0xFF, 0x9C, 0x43, 0x06, 0xFF,
++ 0x9F, 0x42, 0x03, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA8, 0x65, 0x34, 0xFF, 0xDD, 0xDE, 0xDC, 0xFF, 0xFA, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xA2, 0x4F, 0x12, 0xFF, 0xA2, 0x42, 0x06, 0xFF, 0xA0, 0x4A, 0x0E, 0xFF, 0xD3, 0xD5, 0xD5, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xCE, 0xA1, 0x80, 0xFF,
++ 0x9F, 0x43, 0x02, 0xFF, 0x9E, 0x44, 0x03, 0xFF, 0xC4, 0xAD, 0x9E, 0xFF, 0xF3, 0xF4, 0xF2, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0x9F, 0x44, 0x01, 0xFF,
++ 0xB0, 0x70, 0x40, 0xFF, 0xDC, 0xDE, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE7, 0xD4, 0xCC, 0xFF, 0xAF, 0x6B, 0x3C, 0xFF, 0xA0, 0x4D, 0x0F, 0xFF, 0xA4, 0x50, 0x16, 0xFF,
++ 0xB3, 0x7F, 0x5B, 0xFF, 0xC8, 0xB8, 0xAC, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0x9D, 0x43, 0x02, 0xFF, 0xB5, 0x7F, 0x5C, 0xFF, 0xE6, 0xE6, 0xE6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFC, 0xFC, 0xFF,
++ 0xC4, 0x95, 0x75, 0xFF, 0xA5, 0x4C, 0x13, 0xFF, 0x9E, 0x42, 0x01, 0xFF, 0x9E, 0x44, 0x03, 0xFF, 0x9D, 0x43, 0x02, 0xFF, 0xAE, 0x69, 0x38, 0xFF, 0xCC, 0xBD, 0xB4, 0xFF, 0xD4, 0xD7, 0xD5, 0xFF,
++ 0xFB, 0xFB, 0xFB, 0xFF, 0xF1, 0xE8, 0xDF, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0xB3, 0x78, 0x50, 0xFF, 0xE3, 0xE4, 0xE2, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xC6, 0x88, 0x62, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0x9D, 0x43, 0x02, 0xFF, 0xCE, 0xC8, 0xC1, 0xFF, 0xFD, 0xFD, 0xFD, 0xFF, 0xE9, 0xD0, 0xC0, 0xFF, 0xA0, 0x44, 0x03, 0xFF, 0xA1, 0x42, 0x03, 0xFF,
++ 0xBB, 0x93, 0x77, 0xFF, 0xE8, 0xEA, 0xEB, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xD0, 0xAE, 0x97, 0xFF, 0xA5, 0x52, 0x1B, 0xFF, 0x9E, 0x44, 0x04, 0xFF, 0x9F, 0x43, 0x02, 0xFF,
++ 0x9D, 0x43, 0x02, 0xFF, 0xA9, 0x5D, 0x29, 0xFF, 0xC6, 0xAD, 0x9D, 0xFF, 0xD3, 0xD2, 0xD4, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0x9C, 0x41, 0x04, 0xFF, 0xA0, 0x44, 0x03, 0xFF,
++ 0x9E, 0x45, 0x02, 0xFF, 0x9F, 0x42, 0x03, 0xFF, 0xA2, 0x42, 0x06, 0xFF, 0x9E, 0x44, 0x03, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF,
++ 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0xA1, 0x42, 0x03, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0x9D, 0x43, 0x03, 0xFF, 0xA1, 0x42, 0x03, 0xFF,
++ 0xA1, 0x41, 0x05, 0xFF, 0x9E, 0x43, 0x06, 0xFF, 0x9F, 0x42, 0x03, 0xFF, 0xC2, 0xA5, 0x90, 0xFF, 0xF1, 0xF2, 0xF0, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFB, 0xFF, 0xFE, 0xFF, 0xBC, 0x7E, 0x50, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF,
++ 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF,
++ 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x43, 0x02, 0xFF, 0x9F, 0x44, 0x01, 0xFF, 0x9E, 0x44, 0x03, 0xFF, 0xA0, 0x43, 0x04, 0xFF, 0x9D, 0x43, 0x02, 0xFF,
++ 0xAE, 0x66, 0x37, 0xFF, 0xDE, 0xDB, 0xDD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xD8, 0xD3, 0xD4, 0xFF, 0xD2, 0xD1, 0xD5, 0xFF, 0xD4, 0xD3, 0xD5, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xE8, 0xE7, 0xE9, 0xFF, 0xCF, 0xD0, 0xD4, 0xFF,
++ 0xD1, 0xD0, 0xD2, 0xFF, 0xF5, 0xF4, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xD1, 0xD2, 0xD0, 0xFF, 0xCF, 0xD2, 0xD0, 0xFF, 0xDE, 0xE0, 0xE1, 0xFF,
++ 0xFE, 0xFE, 0xFE, 0xFF, 0xDB, 0xBB, 0xA4, 0xFF, 0xE7, 0xCD, 0xBC, 0xFF, 0xE9, 0xDD, 0xD3, 0xFF, 0xDC, 0xDD, 0xD9, 0xFF, 0xD5, 0xD5, 0xD5, 0xFF, 0xD5, 0xD4, 0xD6, 0xFF, 0xD8, 0xC2, 0xB6, 0xFF,
++ 0x9C, 0x42, 0x02, 0xFF, 0xA1, 0x44, 0x05, 0xFF, 0xBA, 0x8B, 0x6F, 0xFF, 0xE3, 0xE5, 0xE6, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFD, 0xFD, 0xFF, 0xE5, 0xE4, 0xE6, 0xFF,
++ 0xCC, 0xBF, 0xB7, 0xFF, 0xC9, 0xB9, 0xAD, 0xFF, 0xCB, 0xC6, 0xC3, 0xFF, 0xD1, 0xD2, 0xD0, 0xFF, 0xDD, 0xDC, 0xDE, 0xFF, 0xF8, 0xF8, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF,
++ 0xFB, 0xF8, 0xFA, 0xFF, 0xD2, 0xD3, 0xD1, 0xFF, 0xD1, 0xD0, 0xD4, 0xFF, 0xE5, 0xE1, 0xE6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xE1, 0xE1, 0xE1, 0xFF,
++ 0xD2, 0xD1, 0xD3, 0xFF, 0xD2, 0xD1, 0xD3, 0xFF, 0xFB, 0xFB, 0xFB, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xF2, 0xF1, 0xF3, 0xFF, 0xD2, 0xD1, 0xD3, 0xFF, 0xD1, 0xD1, 0xD1, 0xFF, 0xEB, 0xEC, 0xEA, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xEE, 0xED, 0xEF, 0xFF, 0xCD, 0xC3, 0xBC, 0xFF, 0xC9, 0xB7, 0xAC, 0xFF, 0xCE, 0xC3, 0xBF, 0xFF, 0xD1, 0xD0, 0xD4, 0xFF,
++ 0xDA, 0xDA, 0xDA, 0xFF, 0xF4, 0xF1, 0xF3, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xC9, 0x95, 0x71, 0xFF, 0xB6, 0x80, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x80, 0x5B, 0xFF, 0xB3, 0x82, 0x5C, 0xFF,
++ 0xB6, 0x82, 0x5E, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF,
++ 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5C, 0xFF, 0xB3, 0x82, 0x5C, 0xFF, 0xB6, 0x82, 0x5E, 0xFF, 0xB7, 0x82, 0x5D, 0xFF, 0xB4, 0x83, 0x5D, 0xFF, 0xB3, 0x81, 0x5D, 0xFF,
++ 0xB6, 0x80, 0x5D, 0xFF, 0xC8, 0xB8, 0xAC, 0xFF, 0xF1, 0xF2, 0xF0, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xDA, 0xB6, 0x9E, 0xFF, 0xBC, 0x88, 0x64, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF,
++ 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF,
++ 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5D, 0xFF, 0xB5, 0x81, 0x5C, 0xFF, 0xB6, 0x81, 0x60, 0xFF, 0xB3, 0x81, 0x5D, 0xFF, 0xB6, 0x81, 0x5C, 0xFF, 0xBA, 0x95, 0x79, 0xFF, 0xDC, 0xDC, 0xDC, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xB0, 0x60, 0x2B, 0xFF,
++ 0x9C, 0x42, 0x02, 0xFF, 0xA2, 0x44, 0x03, 0xFF, 0xCB, 0x9C, 0x7D, 0xFF, 0xF7, 0xEE, 0xEA, 0xFF, 0xF0, 0xE0, 0xD9, 0xFF, 0xC0, 0x82, 0x5A, 0xFF, 0x9E, 0x45, 0x02, 0xFF, 0x9C, 0x42, 0x02, 0xFF,
++ 0xC4, 0xA9, 0x95, 0xFF, 0xE9, 0xE9, 0xE9, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFB, 0xF8, 0xFA, 0xFF,
++ 0xF6, 0xF6, 0xF6, 0xFF, 0xFE, 0xFC, 0xFB, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFC, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFA, 0xF8, 0xFF, 0xF6, 0xF6, 0xF6, 0xFF, 0xF9, 0xFA, 0xF8, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xE3, 0xE5, 0xE6, 0xFF, 0xE5, 0xE3, 0xE9, 0xFF, 0xE4, 0xE6, 0xE6, 0xFF, 0xE2, 0xE7, 0xE6, 0xFF, 0xE5, 0xE4, 0xE6, 0xFF, 0xE4, 0xE6, 0xE7, 0xFF,
++ 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF,
++ 0xE3, 0xE4, 0xE8, 0xFF, 0xE6, 0xE7, 0xE5, 0xFF, 0xE5, 0xE5, 0xE5, 0xFF, 0xE6, 0xE6, 0xE6, 0xFF, 0xE2, 0xE3, 0xE7, 0xFF, 0xE6, 0xE6, 0xE6, 0xFF, 0xE5, 0xE5, 0xE5, 0xFF, 0xE5, 0xE4, 0xE6, 0xFF,
++ 0xF8, 0xF7, 0xFB, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xED, 0xEE, 0xEC, 0xFF,
++ 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF,
++ 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF, 0xE3, 0xE5, 0xE5, 0xFF,
++ 0xE7, 0xE4, 0xE6, 0xFF, 0xE7, 0xE4, 0xE6, 0xFF, 0xE5, 0xE4, 0xE6, 0xFF, 0xE8, 0xE6, 0xE6, 0xFF, 0xE1, 0xE5, 0xE6, 0xFF, 0xEE, 0xEB, 0xED, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF,
++ 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xD6, 0xAF, 0x93, 0xFF, 0x9E, 0x43, 0x06, 0xFF, 0x9C, 0x43, 0x00, 0xFF,
++ 0x9D, 0x43, 0x03, 0xFF, 0x9A, 0x43, 0x01, 0xFF, 0x9E, 0x45, 0x02, 0xFF, 0x9D, 0x43, 0x02, 0xFF, 0x9D, 0x43, 0x03, 0xFF, 0xA6, 0x5D, 0x29, 0xFF, 0xCF, 0xCF, 0xCF, 0xFF, 0xF4, 0xF2, 0xF1, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFC, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF,
++ 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF,
++ 0xFC, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFD, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFC, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xD1, 0xAC, 0x98, 0xFF, 0xAA, 0x67, 0x30, 0xFF, 0xA0, 0x47, 0x0A, 0xFF, 0x9E, 0x44, 0x04, 0xFF,
++ 0x9F, 0x43, 0x02, 0xFF, 0xA5, 0x55, 0x1E, 0xFF, 0xB2, 0x82, 0x5E, 0xFF, 0xCF, 0xC6, 0xC3, 0xFF, 0xDC, 0xD9, 0xDB, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFE, 0xFF, 0xFD, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFA, 0xFF, 0xFD, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFC, 0xFF, 0xFC, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFE, 0xFF, 0xFB, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0xFF, 0xFF,
++ 0xFF, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xEE, 0xED, 0xEF, 0xFF, 0xD9, 0xDC, 0xDA, 0xFF, 0xD2, 0xD3, 0xD7, 0xFF, 0xCF, 0xD2, 0xD0, 0xFF, 0xCF, 0xD1, 0xD2, 0xFF,
++ 0xD9, 0xD6, 0xD8, 0xFF, 0xE6, 0xE6, 0xE6, 0xFF, 0xFC, 0xFD, 0xFB, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFB, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
++ 0xFD, 0xFF, 0xFC, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF,
++ 0xFD, 0xFF, 0xFF, 0xFF, 0xFD, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++ 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF,
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFB, 0xFF, 0xFE, 0xFF, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF,
++ 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF,};
+diff --git a/module_drivers/drivers/video/logo-ingenic/showlogo.c b/module_drivers/drivers/video/logo-ingenic/showlogo.c
+new file mode 100644
+index 000000000..03a931c3b
+--- /dev/null
++++ b/module_drivers/drivers/video/logo-ingenic/showlogo.c
+@@ -0,0 +1,133 @@
++#include <linux/fb.h>
++#include <video/ingenic_logo.h>
++
++
++static struct _logo_info *logo_early = NULL;
++
++static int __init logo_info_early(char *p)
++{
++	unsigned int pinfo = 0;
++	pinfo = simple_strtoul(p, NULL, 0);
++	logo_early = (struct _logo_info *)pinfo;
++	logo_early->p8 = (unsigned char *)(pinfo + sizeof(struct _logo_info));
++        return 0;
++}
++early_param("logo", logo_info_early);
++
++
++
++void show_logo(struct fb_info *info)
++{
++	unsigned int i, j;
++	int w, h, bpp;
++	int blank_left, blank_top;
++	void *buf;
++	unsigned int *p32;
++	unsigned int *p_logo;
++	struct fb_var_screeninfo *var = &info->var;
++	unsigned char *screen_base = info->screen_base;
++	struct _logo_info *pinfo = &logo_info;	//Kernel Built-in logo.
++
++	if(logo_early) {
++		pinfo = logo_early;
++	}
++
++	w = var->xres;
++	h = var->yres;
++	bpp = info->var.bits_per_pixel;
++	if ((w < pinfo->width) || (h < pinfo->height)) {
++		printk("\033[33mERROR: LOGO shouldn't bigger than panel! skip.\033[0m\n");
++		return;
++	}
++
++	buf = screen_base;
++	if (pinfo->bpp == bpp) {
++		blank_left = (w - pinfo->width) / 2;
++		blank_top = (h - pinfo->height) / 2;
++		// printk("\033[31m w = %d | pinfo->width = %d |\033[0m\n", w, pinfo->width);
++		// printk("\033[31m blank_left = %d | blank_top = %d |\033[0m\n", blank_left, blank_top);
++		if (bpp == 32) {
++			if (blank_top) {
++				p32 = (unsigned int *)buf;
++				for (i = 0; i < blank_top * w; ++i) {
++					*(p32 + i) = pinfo->background_color;
++				}
++				p32 = (unsigned int *)buf + (blank_top + pinfo->height) * w;
++				for (i = 0; i < (h - pinfo->height - blank_top) * w; ++i) {
++					*(p32 + i) = pinfo->background_color;
++				}
++			}
++			if (blank_left) {
++				for (i = 0; i < pinfo->height; ++i) {
++					p32 = (unsigned int *)buf + (blank_top + i) * w;
++					for (j = 0; j < blank_left; ++j) {
++						*(p32 + j) = pinfo->background_color;
++					}
++					p32 = (unsigned int *)buf + (blank_top + i) * w + pinfo->width + blank_left;
++					for (j = 0; j < w - pinfo->width - blank_left; ++j) {
++						*(p32 + j) = pinfo->background_color;
++					}
++				}
++			}
++			for (i = 0; i < pinfo->height; ++i) {
++				p32 = (unsigned int *)buf + (blank_top + i) * w + blank_left;
++				p_logo = (unsigned int*)pinfo->p8 + i * pinfo->width;
++				for (j = 0; j < pinfo->width; ++j) {
++					*(p32 + j) = *(p_logo + j);
++				}
++			}
++		} else if (bpp == 16) {
++			unsigned int background_color = pinfo->background_color << 16 | pinfo->background_color;
++
++			printk("\033[31m h = %d | blank_top = %d | pinfo->height = %d |\033[0m\n", h, blank_top, pinfo->height);
++			if (blank_top) {
++				int tmp = blank_top * ((w + 1) / 2);
++				p32 = (unsigned int *)buf;
++				for (i = 0; i < tmp; i++)
++					*(p32++) = background_color;
++
++				tmp = (h - blank_top - pinfo->height) * ((w + 1) / 2);
++				p32 = (unsigned int *)buf + (blank_top + pinfo->height) * ((w + 1) / 2);
++				for (i = 0; i < tmp; i++)
++					*(p32++) = background_color;
++			}
++
++			if (blank_left) {
++				int tmp;
++				for (i = 0; i < pinfo->height; ++i) {
++					tmp = (blank_left + 1) / 2;
++					p32 = (unsigned int *)buf + (blank_top + i) * ((w + 1) / 2);
++					for (j = 0; j < tmp; ++j) {
++						*(p32 + j) = background_color;
++					}
++
++					p32 = (unsigned int *)buf + (blank_top + i) * ((w + 1) / 2) + (pinfo->width + blank_left) / 2;
++					for (j = 0; j < tmp; ++j) {
++						*(p32 + j) = background_color;
++					}
++				}
++			}
++			if (pinfo->width%2) {
++				for (i = 0; i < pinfo->height; ++i) {
++					p32 = (unsigned int *)buf + (blank_top + i) * ((w + 1) / 2) + blank_left / 2;
++					p_logo = (unsigned int*)pinfo->p8 + i * pinfo->width/2;
++					for (j = 0; j < pinfo->width/2; ++j) {
++						*(p32 + j) = *(p_logo + j);
++					}
++					*(unsigned short*)(p32 + j) = *(unsigned short*)(p_logo + j);
++				}
++			} else {
++				for (i = 0; i < pinfo->height; ++i) {
++					p32 = (unsigned int *)buf + (blank_top + i) * ((w + 1) / 2) + blank_left / 2;
++					p_logo = (unsigned int*)pinfo->p8 + i * pinfo->width/2;
++					for (j = 0; j < pinfo->width/2; ++j) {
++						*(p32 + j) = *(p_logo + j);
++					}
++				}
++			}
++		}
++	}
++}
++EXPORT_SYMBOL(show_logo);
++EXPORT_SYMBOL(logo_info);
++EXPORT_SYMBOL(logo_buf_initdata);
+diff --git a/module_drivers/drivers/watchdog/Kconfig b/module_drivers/drivers/watchdog/Kconfig
+new file mode 100644
+index 000000000..01166f35d
+--- /dev/null
++++ b/module_drivers/drivers/watchdog/Kconfig
+@@ -0,0 +1,20 @@
++config INGENIC_WDT
++        tristate "Ingenic ingenic SoC hardware watchdog"
++        depends on SOC_X2000_V12 || SOC_X2000 || SOC_M300 || SOC_X2100 || SOC_X1600
++        select WATCHDOG_CORE
++        help
++          Hardware driver for the built-in watchdog timer on Ingenic all SoCs.
++
++config INGENIC_WDT_V1
++        tristate "Ingenic SoC hardware watchdog for X2500"
++        depends on SOC_X2500
++        select WATCHDOG_CORE
++        help
++          Hardware driver for the built-in watchdog timer on Ingenic all SoCs.
++
++config SGM820_WATCHDOG
++	tristate "SGM820 watchdog"
++	select WATCHDOG_CORE
++	help
++	  SGM820 watchdog timer
++
+diff --git a/module_drivers/drivers/watchdog/Makefile b/module_drivers/drivers/watchdog/Makefile
+new file mode 100644
+index 000000000..6041fd6e4
+--- /dev/null
++++ b/module_drivers/drivers/watchdog/Makefile
+@@ -0,0 +1,3 @@
++obj-$(CONFIG_INGENIC_WDT) += ingenic_wdt.o
++obj-$(CONFIG_INGENIC_WDT_V1) += ingenic_wdt_v1.o
++obj-$(CONFIG_SGM820_WATCHDOG) += sgm820_wdt.o
+diff --git a/module_drivers/drivers/watchdog/ingenic_wdt.c b/module_drivers/drivers/watchdog/ingenic_wdt.c
+new file mode 100644
+index 000000000..034c55b94
+--- /dev/null
++++ b/module_drivers/drivers/watchdog/ingenic_wdt.c
+@@ -0,0 +1,328 @@
++/*
++ *  Copyright (C) 2017, bo.liu <bo.liu@ingenic.com>
++ *  ingenic Watchdog driver
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under  the terms of the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the License, or (at your
++ *  option) any later version.
++ *
++ *  You should have received a copy of the GNU General Public License along
++ *  with this program; if not, write to the Free Software Foundation, Inc.,
++ *  675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/miscdevice.h>
++#include <linux/watchdog.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/reboot.h>
++#include <linux/io.h>
++#include <linux/device.h>
++#include <linux/clk.h>
++#include <linux/slab.h>
++#include <linux/err.h>
++#include <linux/interrupt.h>
++#include "ingenic_wdt.h"
++
++#define IRQ_SWITCH	0
++//#define WDT_DEBUG
++
++static  void wdt_set_half_and_full(struct ingenic_wdt_drvdata *drvdata, unsigned int value,char ch);
++
++static bool nowayout = WATCHDOG_NOWAYOUT;
++module_param(nowayout, bool, 0);
++MODULE_PARM_DESC(nowayout,
++		 "Watchdog cannot be stopped once started (default="
++		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
++
++static unsigned int heartbeat = DEFAULT_HEARTBEAT;
++module_param(heartbeat, uint, 0);
++MODULE_PARM_DESC(heartbeat,
++		"Watchdog heartbeat period in seconds from 1 to "
++		__MODULE_STRING(MAX_HEARTBEAT) ", default "
++		__MODULE_STRING(DEFAULT_HEARTBEAT));
++
++static int ingenic_restart_handler(struct notifier_block *this, unsigned long mode,
++		void *cmd)
++{
++	struct ingenic_wdt_drvdata *drvdata = container_of(this,struct ingenic_wdt_drvdata, restart_handler);
++	writew(INGENIC_WDT_CLOCK_RTC | INGENIC_WDT_CLOCK_CLRZ ,drvdata->base + INGENIC_REG_WDT_TIMER_CONTROL);
++	wdt_set_half_and_full(drvdata,0xa0,'F');
++	writeb(0x1, drvdata->base + INGENIC_REG_WDT_COUNTER_ENABLE);
++
++	return NOTIFY_DONE;
++}
++
++#ifdef WDT_DEBUG
++static void ingenic_wdt_pr_debug(struct ingenic_wdt_drvdata *drvdata)
++{
++	printk("\n*********************************************\n");
++	printk("half-full addr %08x value is %08x\n",(unsigned int)(drvdata->base + INGENIC_REG_WDT_TIMER_DATA),
++			readl(drvdata->base +INGENIC_REG_WDT_TIMER_DATA));
++	printk("enable    addr %x value is %08x\n",(unsigned int)(drvdata->base + INGENIC_REG_WDT_COUNTER_ENABLE),
++			readl(drvdata->base +INGENIC_REG_WDT_COUNTER_ENABLE));
++	printk("counter   addr %x value is %08x\n",(unsigned int)(drvdata->base + INGENIC_REG_WDT_TIMER_COUNTER),
++			readl(drvdata->base +INGENIC_REG_WDT_TIMER_COUNTER));
++	printk("control   addr %x value is %08x\n",(unsigned int)(drvdata->base + INGENIC_REG_WDT_TIMER_CONTROL),
++			readl(drvdata->base +INGENIC_REG_WDT_TIMER_CONTROL));
++	printk("flag      addr %x value is %08x\n",(unsigned int)(drvdata->base + INGENIC_REG_WDT_TIMER_FLAG_RD),
++			readl(drvdata->base +INGENIC_REG_WDT_TIMER_FLAG_RD));
++	printk("mask      addr %x value is %08x\n",(unsigned int)(drvdata->base + INGENIC_REG_WDT_TIMER_MASK_RD),
++			readl(drvdata->base +INGENIC_REG_WDT_TIMER_MASK_RD));
++	printk("stop      addr %x value is %08x\n",(unsigned int)(drvdata->base + INGENIC_REG_WDT_TIMER_STOP_RD),
++			readl(drvdata->base +INGENIC_REG_WDT_TIMER_STOP_RD));
++	printk("\n*********************************************\n");
++}
++#endif
++
++#if IRQ_SWITCH
++static irqreturn_t ingenic_wdt_interrupt(int irq, void *dev_id)
++{
++
++	struct ingenic_wdt_drvdata *drvdata = (struct ingenic_wdt_drvdata *)(dev_id);
++#if 1
++	if(readl(drvdata->base + INGENIC_REG_WDT_TIMER_FLAG_RD) & INGENIC_WDT_TIMER_FLAG){
++		writel(INGENIC_WDT_TIMER_FLAG,drvdata->base + INGENIC_REG_WDT_TIMER_FLAG_CLR);
++		writel(readl(drvdata->base + INGENIC_REG_WDT_TIMER_CONTROL) | INGENIC_WDT_CLOCK_CLRZ , drvdata->base + INGENIC_REG_WDT_TIMER_CONTROL);
++	}
++#else
++	printk("%s:%d ---------------enter interrupt ok ---------------\n",__func__,__LINE__);
++#endif
++	return IRQ_HANDLED;
++}
++#endif
++
++static int ingenic_wdt_ping(struct watchdog_device *wdt_dev)
++{
++	struct ingenic_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
++	writel(readl(drvdata->base + INGENIC_REG_WDT_TIMER_CONTROL) | INGENIC_WDT_CLOCK_CLRZ , drvdata->base + INGENIC_REG_WDT_TIMER_CONTROL);
++	return 0;
++}
++
++static  void wdt_set_half_and_full(struct ingenic_wdt_drvdata *drvdata, unsigned int value,char ch)
++{
++	int tmp ;
++	if (value > INGENIC_WDT_FULL_MAX)
++		value = INGENIC_WDT_FULL_MAX;
++	tmp =readl(drvdata->base + INGENIC_REG_WDT_TIMER_DATA);
++	if('H' == ch){
++		tmp &= ~(INGENIC_WDT_FULL_MAX << INGENIC_WDT_OFFSET_16);
++		tmp |= value << INGENIC_WDT_OFFSET_16;
++	}
++	if('F' == ch){
++		tmp &= ~(INGENIC_WDT_FULL_MAX);
++		tmp |= value;
++	}
++	writel(tmp,drvdata->base + INGENIC_REG_WDT_TIMER_DATA);
++}
++
++static int ingenic_wdt_set_timeout(struct watchdog_device *wdt_dev,
++		unsigned int new_timeout)
++{
++	struct ingenic_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
++	unsigned int rtc_clk_rate;
++	unsigned int timeout_value;
++	short clock_div = INGENIC_WDT_CLOCK_DIV_1;
++
++	if(drvdata->timeout != wdt_dev->timeout){
++
++		writeb(0x0, drvdata->base + INGENIC_REG_WDT_COUNTER_ENABLE);
++		rtc_clk_rate = clk_get_rate(drvdata->wdt_clk);
++
++		/*new_timeout max = 2047s */
++		clock_div = INGENIC_WDT_CLOCK_DIV_1024;
++		timeout_value = rtc_clk_rate * new_timeout / 1024;
++
++		if(timeout_value > INGENIC_WDT_FULL_MAX){
++			timeout_value = INGENIC_WDT_FULL_MAX;
++		}
++
++		writel(INGENIC_WDT_TIMER_FLAG,drvdata->base + INGENIC_REG_WDT_TIMER_FLAG_CLR);
++		writel(INGENIC_WDT_TIMER_STOP,drvdata->base + INGENIC_REG_WDT_TIMER_STOP_CLR);
++
++		/*Reach this value set to reboot*/
++		wdt_set_half_and_full(drvdata,timeout_value,'F');
++
++		/*When the set value is reached, the flag bit will be set to 1 and an interrupt will be triggered.*/
++		wdt_set_half_and_full(drvdata,timeout_value * 2/3,'H');
++
++		/*set prescal clzr rtc_en*/
++		writew(clock_div | INGENIC_WDT_CLOCK_RTC | INGENIC_WDT_CLOCK_CLRZ ,drvdata->base + INGENIC_REG_WDT_TIMER_CONTROL);
++		writeb(0x1, drvdata->base + INGENIC_REG_WDT_COUNTER_ENABLE);
++
++		drvdata->timeout = wdt_dev->timeout = new_timeout;
++	}
++	return 0;
++}
++
++static int ingenic_wdt_start(struct watchdog_device *wdt_dev)
++{
++	struct ingenic_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
++	writel(INGENIC_WDT_TIMER_FLAG,drvdata->base + INGENIC_REG_WDT_TIMER_FLAG_CLR);
++	writeb(0x1, drvdata->base + INGENIC_REG_WDT_COUNTER_ENABLE);
++	//ingenic_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
++
++	return 0;
++}
++
++static int ingenic_wdt_stop(struct watchdog_device *wdt_dev)
++{
++	struct ingenic_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
++	writeb(0x0, drvdata->base + INGENIC_REG_WDT_COUNTER_ENABLE);
++	return 0;
++}
++
++static const struct watchdog_info ingenic_wdt_info = {
++	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
++	.identity = "ingenic Watchdog",
++};
++
++static const struct watchdog_ops ingenic_wdt_ops = {
++	.owner = THIS_MODULE,
++	.start = ingenic_wdt_start,
++	.stop = ingenic_wdt_stop,
++	.ping = ingenic_wdt_ping,
++	.set_timeout = ingenic_wdt_set_timeout,
++};
++
++
++static const struct of_device_id ingenic_wdt_of_matches[] = {
++	{ .compatible = "ingenic,watchdog", .data = NULL },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ingenic_wdt_of_matches)
++
++static int ingenic_wdt_probe(struct platform_device *pdev)
++{
++	struct ingenic_wdt_drvdata *drvdata;
++	struct watchdog_device *ingenic_wdt;
++	struct resource	*res;
++	int ret;
++
++	drvdata = devm_kzalloc(&pdev->dev, sizeof(struct ingenic_wdt_drvdata),
++			GFP_KERNEL);
++	if (!drvdata) {
++		dev_err(&pdev->dev, "Unable to alloacate watchdog device\n");
++		return -ENOMEM;
++	}
++
++	drvdata->irq = platform_get_irq(pdev,0);
++	if (drvdata->irq < 0) {
++		dev_err(&pdev->dev, "no irq for watchdog tick\n");
++		ret = drvdata->irq;
++		goto err_nosrc;
++	}
++
++	if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
++		heartbeat = DEFAULT_HEARTBEAT;
++
++	ingenic_wdt = &drvdata->wdt;
++	ingenic_wdt->info = &ingenic_wdt_info;
++	ingenic_wdt->ops = &ingenic_wdt_ops;
++	ingenic_wdt->timeout = heartbeat;
++	ingenic_wdt->min_timeout = 1;
++	ingenic_wdt->max_timeout = MAX_HEARTBEAT;
++	watchdog_set_nowayout(ingenic_wdt, nowayout);
++	watchdog_set_drvdata(ingenic_wdt, drvdata);
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++	drvdata->base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(drvdata->base)) {
++		ret = PTR_ERR(drvdata->base);
++		goto err_out;
++	}
++
++	drvdata->wdt_clk = devm_clk_get(&pdev->dev, "mux_wdt");
++
++	if (IS_ERR(drvdata->wdt_clk)) {
++		dev_err(&pdev->dev, "cannot find WDT clock\n");
++		ret = PTR_ERR(drvdata->wdt_clk);
++		goto err_out;
++	}
++
++	drvdata->tcu_clk = devm_clk_get(&pdev->dev, "gate_tcu");
++	if (IS_ERR(drvdata->tcu_clk)) {
++		dev_err(&pdev->dev, "cannot find TCU clock\n");
++		ret = PTR_ERR(drvdata->tcu_clk);
++		goto err_out;
++	}
++
++	clk_prepare_enable(drvdata->wdt_clk);
++	clk_prepare_enable(drvdata->tcu_clk);
++
++	ret = watchdog_register_device(&drvdata->wdt);
++	if (ret < 0)
++		goto err_disable_clk;
++
++	drvdata->restart_handler.notifier_call = ingenic_restart_handler;
++	drvdata->restart_handler.priority = 128;
++	ret = register_restart_handler(&drvdata->restart_handler);
++	if (ret)
++		dev_err(&pdev->dev, "cannot register restart handler\n");
++
++	writel(INGENIC_WDT_TIMER_MASK,drvdata->base + INGENIC_REG_WDT_TIMER_MASK_CLR);
++	writel(INGENIC_WDT_TIMER_FLAG,drvdata->base + INGENIC_REG_WDT_TIMER_FLAG_CLR);
++#if IRQ_SWITCH
++	ret = request_irq(drvdata->irq,ingenic_wdt_interrupt,
++			IRQF_SHARED | IRQF_TRIGGER_LOW,"watchdog-int",drvdata);
++	if (ret) {
++		pr_debug("IRQ %d already in use.\n", drvdata->irq);
++		dev_err(&pdev->dev, "--request_irq error------irq = %d\n",drvdata->irq);
++		goto err_free_irq;
++	}
++#endif
++	platform_set_drvdata(pdev, drvdata);
++
++	printk("ingenic watchdog probe success\n");
++	return 0;
++#if IRQ_SWITCH
++err_free_irq:
++	free_irq(drvdata->irq,drvdata);
++#endif
++err_nosrc:
++	kfree(drvdata);
++err_disable_clk:
++	clk_put(drvdata->wdt_clk);
++	clk_put(drvdata->tcu_clk);
++err_out:
++	return ret;
++}
++
++static int ingenic_wdt_remove(struct platform_device *pdev)
++{
++	struct ingenic_wdt_drvdata *drvdata = platform_get_drvdata(pdev);
++
++	ingenic_wdt_stop(&drvdata->wdt);
++	unregister_restart_handler(&drvdata->restart_handler);
++#if IRQ_SWITCH
++	free_irq(drvdata->irq,drvdata);
++#endif
++	watchdog_unregister_device(&drvdata->wdt);
++	clk_put(drvdata->wdt_clk);
++	clk_put(drvdata->tcu_clk);
++
++	return 0;
++}
++
++static struct platform_driver ingenic_wdt_driver = {
++	.probe = ingenic_wdt_probe,
++	.remove = ingenic_wdt_remove,
++	.driver = {
++		.name = "ingenic-watchdog",
++		.of_match_table = of_match_ptr(ingenic_wdt_of_matches),
++	},
++};
++
++module_platform_driver(ingenic_wdt_driver);
++
++MODULE_AUTHOR("bo liu <bo.liu@ingenic.com>");
++MODULE_DESCRIPTION("ingenic xburst2 Watchdog Driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
++MODULE_ALIAS("platform:ingenic-wdt");
+diff --git a/module_drivers/drivers/watchdog/ingenic_wdt.h b/module_drivers/drivers/watchdog/ingenic_wdt.h
+new file mode 100644
+index 000000000..0f113d10b
+--- /dev/null
++++ b/module_drivers/drivers/watchdog/ingenic_wdt.h
+@@ -0,0 +1,65 @@
++/*
++ * ingenic watchdog_device register definition
++ * Copyright (C) 2014 Ingenic Semiconductor Co., Ltd.
++ *
++ */
++#ifndef __INGENIC_WDT_H__
++#define __INGENIC_WDT_H__
++/*
++ * watchdog registers offset address definition
++ */
++#define INGENIC_REG_WDT_TIMER_DATA     (0x0)
++#define INGENIC_REG_WDT_COUNTER_ENABLE (0x4)
++#define INGENIC_REG_WDT_TIMER_COUNTER  (0x8)
++#define INGENIC_REG_WDT_TIMER_CONTROL  (0xC)
++#define INGENIC_REG_WDT_TIMER_STOP_RD  (0x1C)
++#define INGENIC_REG_WDT_TIMER_STOP_SET (0x2C)
++#define INGENIC_REG_WDT_TIMER_STOP_CLR (0x3C)
++#define INGENIC_REG_WDT_TIMER_FLAG_RD  (0x20)
++#define INGENIC_REG_WDT_TIMER_FLAG_SET (0x24)
++#define INGENIC_REG_WDT_TIMER_FLAG_CLR (0x28)
++#define INGENIC_REG_WDT_TIMER_MASK_RD  (0x30)
++#define INGENIC_REG_WDT_TIMER_MASK_SET (0x34)
++#define INGENIC_REG_WDT_TIMER_MASK_CLR (0x38)
++
++#define INGENIC_WDT_OFFSET_16	  (16)
++#define INGENIC_WDT_FULL_MAX	  (0xffff)
++
++/*Watchdog timer stop Register(TCU_STOP_RD/SET/CLR,0x1C/0x2C/0x3C) bit*/
++#define INGENIC_WDT_TIMER_STOP	BIT(16)
++
++/*Watchdog timer flag Register(TCU_FLAG_RD/SET/CLR,0x20/0x24/0x28) bit*/
++#define INGENIC_WDT_TIMER_FLAG	BIT(24)
++
++/*Watchdog timer mask Register(TCU_MASK_RD/SET/CLR,0x30/0x34/0x38) bit*/
++#define INGENIC_WDT_TIMER_MASK	BIT(24)
++
++/*Watchdog Control Register(WDT_CONTROL,0x0C)*/
++#define INGENIC_WDT_CLOCK_RTC	BIT(1)
++#define INGENIC_WDT_CLOCK_CLRZ	BIT(10)
++
++#define INGENIC_WDT_CLOCK_DIV_SHIFT   (3)
++#define INGENIC_WDT_CLOCK_DIV_MAX  (0x7)
++#define INGENIC_WDT_CLOCK_DIV_1    (0 << INGENIC_WDT_CLOCK_DIV_SHIFT)
++#define INGENIC_WDT_CLOCK_DIV_4    (1 << INGENIC_WDT_CLOCK_DIV_SHIFT)
++#define INGENIC_WDT_CLOCK_DIV_16   (2 << INGENIC_WDT_CLOCK_DIV_SHIFT)
++#define INGENIC_WDT_CLOCK_DIV_64   (3 << INGENIC_WDT_CLOCK_DIV_SHIFT)
++#define INGENIC_WDT_CLOCK_DIV_256  (4 << INGENIC_WDT_CLOCK_DIV_SHIFT)
++#define INGENIC_WDT_CLOCK_DIV_1024 (5 << INGENIC_WDT_CLOCK_DIV_SHIFT)
++
++#define DEFAULT_HEARTBEAT (15)
++#define MAX_HEARTBEAT     (2047 * 1000)
++
++/*ingenic watchdog drvdata struct*/
++struct ingenic_wdt_drvdata {
++	int irq;
++	struct work_struct work;
++	struct watchdog_device wdt;
++	void __iomem *base;
++	struct clk *wdt_clk;
++	struct clk *tcu_clk;
++	unsigned int timeout;
++	struct notifier_block restart_handler;
++};
++
++#endif /* __INGENIC_WDT_H__*/
+diff --git a/module_drivers/drivers/watchdog/ingenic_wdt_v1.c b/module_drivers/drivers/watchdog/ingenic_wdt_v1.c
+new file mode 100644
+index 000000000..da7219820
+--- /dev/null
++++ b/module_drivers/drivers/watchdog/ingenic_wdt_v1.c
+@@ -0,0 +1,601 @@
++/*
++ *  Copyright (C) 2017, bo.liu <bo.liu@ingenic.com>
++ *  INGENIC Watchdog driver
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under  the terms of the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the License, or (at your
++ *  option) any later version.
++ *
++ *  You should have received a copy of the GNU General Public License along
++ *  with this program; if not, write to the Free Software Foundation, Inc.,
++ *  675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/watchdog.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/device.h>
++#include <linux/clk.h>
++#include <linux/reboot.h>
++#include <linux/slab.h>
++#include <linux/err.h>
++#include <linux/of.h>
++#include <linux/delay.h>
++#include <linux/sched.h>
++#include <linux/proc_fs.h>
++#include <linux/seq_file.h>
++#include <linux/delay.h>
++#include <linux/kthread.h>
++#include <linux/mfd/core.h>
++#include <linux/mfd/ingenic-tcu_v1.h>
++#include <uapi/linux/sched/types.h>
++/* #include <soc/xburst/reboot.h> */
++#include <ingenic_proc.h>
++#include <soc/base.h>
++#define DEFAULT_HEARTBEAT 5
++#define MAX_HEARTBEAT     2048
++
++
++
++
++enum restart_handler_priority {
++    WDT_RESET_PROR = 0,
++    RTC_HIBERNATE_RESET_PROR,
++};
++
++#define REBOOT_CMD_RECOVERY "recovery"
++#define REBOOT_CMD_SOFTBURN "softburn"
++
++void __weak ingenic_recovery_sign(void)
++{
++    pr_info("ingenic default recovery sign\n");
++    return;
++}
++
++void __weak ingenic_reboot_sign(void)
++{
++    pr_info("ingenic default reboot sign\n");
++    return;
++}
++
++void __weak ingenic_softburn_sign(void)
++{
++    pr_info("ingenic default softburn sign\n");
++    return;
++}
++
++
++static bool nowayout = WATCHDOG_NOWAYOUT;
++module_param(nowayout, bool, 0);
++MODULE_PARM_DESC(nowayout,
++		 "Watchdog cannot be stopped once started (default="
++		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
++
++static unsigned int heartbeat = DEFAULT_HEARTBEAT;
++module_param(heartbeat, uint, 0);
++MODULE_PARM_DESC(heartbeat,
++		"Watchdog heartbeat period in seconds from 1 to "
++		__MODULE_STRING(MAX_HEARTBEAT) ", default "
++		__MODULE_STRING(DEFAULT_HEARTBEAT));
++
++struct ingenic_wdt_drvdata {
++	struct watchdog_device wdt;
++	struct platform_device *pdev;
++	const struct mfd_cell *cell;
++
++	struct clk *ext_clk;
++	struct notifier_block restart_handler;
++};
++
++static int ingenic_wdt_ping(struct watchdog_device *wdt_dev)
++{
++	ingenic_watchdog_set_count(0);
++	return 0;
++}
++
++static inline int get_clk_div(unsigned int *timeout_value)
++{
++	int clk_div = TCU_PRESCALE_1;
++
++	while (*timeout_value > 0xffff) {
++		if (clk_div == TCU_PRESCALE_1024) {
++			/* Requested timeout too high;
++			 * use highest possible value. */
++			*timeout_value = 0xffff;
++			clk_div = -1;
++			break;
++		}
++		*timeout_value >>= 2;
++		clk_div += 1;
++	}
++
++	return clk_div;
++}
++static void wdt_config(struct ingenic_wdt_drvdata *drvdata,
++					   unsigned int new_timeout)
++{
++	unsigned int rtc_clk_rate;
++	//unsigned int ext_clk_rate;
++	unsigned int timeout_value;
++	unsigned int clk_src;
++	int clk_div = 0;
++
++	rtc_clk_rate = 24000000 / 512;
++	clk_src = TCU_CLKSRC_RTC;
++	//ext_clk_rate = clk_get_rate(drvdata->ext_clk);
++	//timeout_value = ext_clk_rate * new_timeout;
++	timeout_value = rtc_clk_rate * new_timeout;
++	clk_div = get_clk_div(&timeout_value);
++	if(clk_div < 0){
++		printk("Requested timeout too high, use highest possible value\n");
++		clk_div = TCU_PRESCALE_1024;
++		timeout_value = 0xffff;
++	}
++
++	ingenic_watchdog_config((clk_div << 3) | clk_src, timeout_value);
++}
++
++static int ingenic_wdt_set_timeout(struct watchdog_device *wdt_dev,
++								   unsigned int new_timeout)
++{
++	struct ingenic_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
++
++	wdt_config(drvdata, new_timeout);
++	wdt_dev->timeout = new_timeout;
++	return 0;
++}
++
++static int ingenic_wdt_start(struct watchdog_device *wdt_dev)
++{
++	struct ingenic_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
++
++	drvdata->cell->enable(drvdata->pdev);
++	ingenic_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
++	return 0;
++}
++
++static int ingenic_wdt_stop(struct watchdog_device *wdt_dev)
++{
++	struct ingenic_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
++	drvdata->cell->disable(drvdata->pdev);
++	return 0;
++}
++
++static const struct watchdog_info ingenic_wdt_info = {
++	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
++	.identity = "ingenic Watchdog",
++};
++
++static const struct watchdog_ops ingenic_wdt_ops = {
++	.owner = THIS_MODULE,
++	.start = ingenic_wdt_start,
++	.stop = ingenic_wdt_stop,
++	.ping = ingenic_wdt_ping,
++	.set_timeout = ingenic_wdt_set_timeout,
++};
++
++static int ingenic_reset_handler(struct notifier_block *this, unsigned long mode,
++		void *cmd)
++{
++	struct ingenic_wdt_drvdata *drvdata = container_of(this,
++			struct ingenic_wdt_drvdata, restart_handler);
++	/* struct watchdog_device *wdd = &drvdata->wdt; */
++
++	if (cmd && !strcmp(cmd, REBOOT_CMD_RECOVERY))
++		ingenic_recovery_sign();
++	else
++		ingenic_reboot_sign();
++
++	if (cmd && !strcmp(cmd, REBOOT_CMD_SOFTBURN))
++		ingenic_softburn_sign();
++
++
++	drvdata->cell->enable(drvdata->pdev);
++
++	ingenic_watchdog_config((3 << 3)|TCU_CLKSRC_RTC, 4);
++	while (1) {
++		mdelay(500);
++		pr_err("wdt reset failed, Never be here\n");
++	}
++	return NOTIFY_DONE;
++}
++
++#ifdef CONFIG_OF
++static const struct of_device_id ingenic_wdt_of_matches[] = {
++	{ .compatible = "ingenic,watchdog", },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, ingenic_wdt_of_matches)
++#endif
++
++static ssize_t watchdog_cmd_set(struct file *file, const char __user *buffer, size_t count, loff_t *f_pos);
++static int watchdog_cmd_open(struct inode *inode, struct file *file);
++static const struct proc_ops watchdog_cmd_fops ={
++	.proc_read = seq_read,
++	.proc_open = watchdog_cmd_open,
++	.proc_lseek = seq_lseek,
++	.proc_release = single_release,
++	.proc_write = watchdog_cmd_set,
++};
++
++
++static struct watchdog_device *m_wdt;
++static int ingenic_wdt_probe(struct platform_device *pdev)
++{
++	struct ingenic_wdt_drvdata *drvdata;
++	struct watchdog_device *ingenic_wdt;
++	int ret;
++	struct proc_dir_entry *proc;
++
++	drvdata = devm_kzalloc(&pdev->dev, sizeof(struct ingenic_wdt_drvdata),
++			       GFP_KERNEL);
++	if (!drvdata) {
++		dev_err(&pdev->dev, "Unable to alloacate watchdog device\n");
++		return -ENOMEM;
++	}
++
++	drvdata->cell = mfd_get_cell(pdev);
++	if (!drvdata->cell) {
++		dev_err(&pdev->dev, "Failed to get mfd cell\n");
++		return -ENOMEM;
++	}
++	drvdata->pdev = pdev;
++	if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
++		heartbeat = DEFAULT_HEARTBEAT;
++
++	m_wdt = ingenic_wdt = &drvdata->wdt;
++	ingenic_wdt->info = &ingenic_wdt_info;
++	ingenic_wdt->ops = &ingenic_wdt_ops;
++	ingenic_wdt->timeout = heartbeat;
++	ingenic_wdt->min_timeout = 1;
++	ingenic_wdt->max_timeout = MAX_HEARTBEAT;
++	ingenic_wdt->parent = &pdev->dev;
++	watchdog_set_nowayout(ingenic_wdt, nowayout);
++	watchdog_set_drvdata(ingenic_wdt, drvdata);
++
++	drvdata->ext_clk = devm_clk_get(&pdev->dev, "ext");
++	if (IS_ERR(drvdata->ext_clk)) {
++		dev_err(&pdev->dev, "cannot find EXT clock\n");
++		ret = PTR_ERR(drvdata->ext_clk);
++		goto err_out;
++	}
++
++	ret = watchdog_register_device(&drvdata->wdt);
++	if (ret < 0)
++		goto err_disable_ext_clk;
++
++	platform_set_drvdata(pdev, drvdata);
++
++	drvdata->restart_handler.notifier_call = ingenic_reset_handler;
++	drvdata->restart_handler.priority = WDT_RESET_PROR;
++	ret = register_restart_handler(&drvdata->restart_handler);
++	if (ret)
++		dev_warn(&pdev->dev,
++				 "cannot register restart handler (err=%d)\n", ret);
++
++	/* proc info */
++	proc = jz_proc_mkdir("watchdog");
++	if (!proc) {
++		printk("create mdio info failed!\n");
++	}
++	proc_create_data("reset", S_IRUGO, proc, &watchdog_cmd_fops, NULL);
++
++	return 0;
++
++err_disable_ext_clk:
++
++	clk_put(drvdata->ext_clk);
++err_out:
++	return ret;
++}
++
++static int ingenic_wdt_remove(struct platform_device *pdev)
++{
++	struct ingenic_wdt_drvdata *drvdata = platform_get_drvdata(pdev);
++
++	ingenic_wdt_stop(&drvdata->wdt);
++	watchdog_unregister_device(&drvdata->wdt);
++	clk_put(drvdata->ext_clk);
++	devm_kfree(&pdev->dev, drvdata);
++	return 0;
++}
++
++static struct platform_driver ingenic_wdt_driver = {
++	.probe = ingenic_wdt_probe,
++	.remove = ingenic_wdt_remove,
++	.driver = {
++		.name = "ingenic,watchdog",
++		.of_match_table = of_match_ptr(ingenic_wdt_of_matches),
++	},
++};
++
++module_platform_driver(ingenic_wdt_driver);
++
++/**********************ingenic utils(deprecated)*****************************************/
++struct wdt_utils {
++	struct watchdog_device *wdt;
++	unsigned msecs;
++
++	unsigned stop;
++	struct task_struct *task;
++	unsigned short count;
++};
++
++static __deprecated int reset_task(void *data) {
++	struct wdt_utils *wdt_utils = data;
++	const struct sched_param sc_param = {
++		.sched_priority = MAX_RT_PRIO-1,
++	};
++
++	sched_setscheduler(current,SCHED_RR,&sc_param);
++
++	if (test_and_set_bit(WDOG_ACTIVE, &wdt_utils->wdt->status)) {
++		pr_warn("watchdog conflict\n");
++		wdt_utils->stop = 1;
++		return 0;
++	}
++
++
++	ingenic_wdt_set_timeout(wdt_utils->wdt, (wdt_utils->msecs + 1000 - 1)/1000);
++	ingenic_wdt_start(wdt_utils->wdt);
++
++
++	while (1) {
++		if(kthread_should_stop()) {
++			clear_bit(WDOG_ACTIVE, &wdt_utils->wdt->status);
++
++			ingenic_wdt_stop(wdt_utils->wdt);
++
++			break;
++		}
++
++		ingenic_wdt_ping(wdt_utils->wdt);
++
++		msleep(wdt_utils->wdt->timeout / 3);
++	}
++
++	return 0;
++}
++
++static __deprecated ssize_t wdt_time_show(struct device *dev, struct device_attribute *attr,
++		char *buf)
++{
++	struct wdt_utils *wdt = dev_get_drvdata(dev);
++	return sprintf(buf, "%d msecs\n", wdt->msecs);
++}
++static __deprecated ssize_t wdt_time_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct wdt_utils *wdt = dev_get_drvdata(dev);
++	unsigned int msecs;
++
++	if(!wdt->stop)
++		return -EBUSY;
++
++	sscanf(buf,"%d\n",&msecs);
++
++	if(msecs < 1000)
++		msecs = 1000;
++	if(msecs > 30000)
++		msecs = 30000;
++
++	wdt->msecs = msecs;
++	return count;
++}
++static __deprecated DEVICE_ATTR_RW(wdt_time);
++
++static __deprecated ssize_t wdt_control_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct wdt_utils *wdt = dev_get_drvdata(dev);
++	return sprintf(buf, "%s\n", wdt->stop?">off<on\n":"off>on<\n");
++}
++
++static __deprecated ssize_t wdt_control_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t count)
++{
++	struct wdt_utils *wdt = dev_get_drvdata(dev);
++
++	if(!strncmp(buf,"on",2) && (wdt->stop == 1)) {
++		wdt->task = kthread_run(reset_task, wdt, "reset_task%d",wdt->count++);
++		wdt->stop = 0;
++	} else if(!strncmp(buf,"off",3) && (wdt->stop == 0)) {
++		kthread_stop(wdt->task);
++		wdt->stop = 1;
++	}
++	return count;
++}
++static __deprecated DEVICE_ATTR_RW(wdt_control);
++
++static __deprecated char *reset_command[] = {"wdt", "hibernate","recovery", "burnerboot"};
++static __deprecated ssize_t reset_show(struct device *dev, struct device_attribute *attr,
++						  char *buf)
++{
++	int len = 0, i;
++
++	for(i = 0; i < ARRAY_SIZE(reset_command); i++)
++		len += sprintf(buf + len, "%s\t", reset_command[i]);
++	len += sprintf(buf + len, "\n");
++
++	return len;
++}
++
++static __deprecated ssize_t reset_store(struct device *dev, struct device_attribute *attr,
++						   const char *buf, size_t count)
++{
++	int command_size = 0;
++	int i;
++	char *cmd = NULL;
++
++	if(count == 0)
++		return -EINVAL;
++
++	command_size = ARRAY_SIZE(reset_command);
++	for(i = 0;i < command_size; i++) {
++		if(!strncmp(buf, reset_command[i], strlen(reset_command[i])))
++			break;
++	}
++
++	switch(i) {
++	case 1:
++		reboot_mode = REBOOT_HARD;
++		break;
++	case 2:
++		cmd = "recovery";
++		break;
++	case 3:
++		cmd = "softburn";
++		break;
++	default:
++	case 0:
++		break;
++	}
++	kernel_restart(cmd);
++	return count;
++}
++static __deprecated DEVICE_ATTR_RW(reset);
++
++static __deprecated struct attribute *reset_attrs[] = {
++	&dev_attr_wdt_time.attr,
++	&dev_attr_wdt_control.attr,
++	&dev_attr_reset.attr,
++	NULL
++};
++
++static __deprecated const struct attribute_group attr_group = {
++	.attrs	= reset_attrs,
++};
++
++static __deprecated int wdt_utils_probe(struct platform_device *pdev)
++{
++	struct wdt_utils *wdt;
++	int ret;
++
++	wdt = devm_kzalloc(&pdev->dev, sizeof(struct wdt_utils),GFP_KERNEL);
++	if(!wdt)
++		return -ENOMEM;
++	wdt->wdt = m_wdt;
++	wdt->count = 0;
++	wdt->stop = 1;
++	wdt->msecs = heartbeat * 1000;
++	dev_set_drvdata(&pdev->dev, wdt);
++	ret = sysfs_create_group(&pdev->dev.kobj, &attr_group);
++	if (ret)
++		printk("watchdog utils regist failed\n");
++	return ret;
++}
++
++static __deprecated void wdt_utils_shutdown(struct platform_device *pdev)
++{
++	struct wdt_utils *wdt_utils = dev_get_drvdata(&pdev->dev);
++	ingenic_wdt_stop(wdt_utils->wdt);
++}
++
++static __deprecated int wdt_utils_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	struct wdt_utils *wdt = dev_get_drvdata(&pdev->dev);
++	if (wdt->stop)
++		return 0;
++	kthread_stop(wdt->task);
++	return 0;
++}
++
++
++static __deprecated int wdt_utils_resume(struct platform_device *pdev)
++{
++	struct wdt_utils *wdt = dev_get_drvdata(&pdev->dev);
++	if(wdt->stop)
++		return 0;
++	wdt->task = kthread_run(reset_task, wdt, "reset_task%d",wdt->count++);
++	return 0;
++}
++
++static __deprecated struct platform_device wdt_utils_pdev = {
++	.name		= "wdt_utils",
++};
++
++static __deprecated struct platform_driver wdt_utils_pdrv = {
++	.probe		= wdt_utils_probe,
++	.shutdown	= wdt_utils_shutdown,
++	.suspend	= wdt_utils_suspend,
++	.resume		= wdt_utils_resume,
++	.driver		= {
++		.name	= "wdt_utils",
++		.owner	= THIS_MODULE,
++	},
++};
++
++static __deprecated int __init init_reset(void)
++{
++	platform_driver_register(&wdt_utils_pdrv);
++	platform_device_register(&wdt_utils_pdev);
++	return 0;
++}
++device_initcall_sync(init_reset);
++MODULE_AUTHOR("bo.liu <bo.liu@ingenic.com>");
++MODULE_DESCRIPTION("ingenic Watchdog Driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-wdt");
++
++
++/* cmd */
++#define WATCHDOG_CMD_BUF_SIZE 100
++static uint8_t watchdog_cmd_buf[100];
++static int watchdog_cmd_show(struct seq_file *m, void *v)
++{
++	seq_printf(m ,"%s\n", watchdog_cmd_buf);
++	return 0;
++}
++
++static ssize_t watchdog_cmd_set(struct file *file, const char __user *buffer, size_t count, loff_t *f_pos)
++{
++    int cmd_value = 0;
++    unsigned int reg04 = 0,reglc = 0;
++
++	char *buf = kzalloc((count+1), GFP_KERNEL);
++	if(!buf)
++		return -ENOMEM;
++	if(copy_from_user(buf, buffer, count))
++	{
++		kfree(buf);
++		return EFAULT;
++	}
++	cmd_value = simple_strtoull(buf, NULL, 0);
++
++	mdelay(1000);
++	if(1 == cmd_value) {
++		reg04 = inl(TCU_IOBASE + 0x04);
++		if(reg04 & 0x1) {
++			outl(0 << 0, TCU_IOBASE + 0x4);
++		}
++
++		outl(0x1a, TCU_IOBASE + 0xc);
++
++		reglc = inl(TCU_IOBASE + 0x1c);
++		if(reglc & 0x10000) {
++			outl(1 << 16, TCU_IOBASE + 0x3c);
++			outl(1 << 16, TCU_IOBASE + 0x2c);
++		}
++		outl(0x0000, TCU_IOBASE + 0x0);
++		outl(0x0000, TCU_IOBASE + 0x8);
++
++		reg04 = inl(TCU_IOBASE + 0x04);
++		if(!(reg04 & 0x1)) {
++			outl(1 << 0, TCU_IOBASE + 0x4);
++		}
++		printk("watchdog reboot system!!!\n");
++	}
++
++	kfree(buf);
++	return count;
++}
++static int watchdog_cmd_open(struct inode *inode, struct file *file)
++{
++	return single_open_size(file, watchdog_cmd_show, PDE_DATA(inode),8192);
++}
+diff --git a/module_drivers/drivers/watchdog/sgm820_wdt.c b/module_drivers/drivers/watchdog/sgm820_wdt.c
+new file mode 100644
+index 000000000..9d52c9e62
+--- /dev/null
++++ b/module_drivers/drivers/watchdog/sgm820_wdt.c
+@@ -0,0 +1,107 @@
++/*
++ * drivers/watchdog/sgm820_wdt.c
++ *
++ * Watchdog driver for sgm820/Kirkwood processors
++ *
++ * Author: Sylver Bruneau <sylver.bruneau@googlemail.com>
++ *
++ * This file is licensed under  the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/watchdog.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/of.h>
++#include <linux/gpio.h>
++#include <linux/delay.h>
++#include <linux/kthread.h>
++#include <linux/of_device.h>
++#include <linux/of_gpio.h>
++
++
++
++struct sgm820_watchdog {
++	unsigned long wdi;
++};
++
++
++static struct task_struct *task;
++static int sgm820_feed_dog(void *pdata)
++{
++    int ret = 0;
++	struct sgm820_watchdog *sgm820_pdata = pdata;
++
++    ret = gpio_request(sgm820_pdata->wdi, "sgm820_wdi");
++    if(ret){
++        printk(KERN_ERR "sgm820 request wdi error!\n");
++        return -1;
++    }
++    while(1){
++        gpio_direction_output(sgm820_pdata->wdi, 1);
++        msleep(500);
++        gpio_direction_output(sgm820_pdata->wdi, 0);
++        msleep(500);
++    }
++    return 0;
++}
++
++static const struct of_device_id sgm820_wdt_of_match_table[] = {
++	{
++		.compatible = "sgm820-wdt",
++	},
++	{},
++};
++MODULE_DEVICE_TABLE(of, sgm820_wdt_of_match_table);
++
++static int sgm820_wdt_probe(struct platform_device *pdev)
++{
++	struct sgm820_watchdog *dev;
++	int ret;
++    enum of_gpio_flags flags;
++
++	dev = devm_kzalloc(&pdev->dev, sizeof(struct sgm820_watchdog),
++			   GFP_KERNEL);
++	if (!dev)
++		return -ENOMEM;
++
++    dev->wdi = of_get_named_gpio_flags(pdev->dev.of_node, "ingenic,sgm820-wdi",
++               0, &flags);
++    if(!gpio_is_valid(dev->wdi)){
++        printk("%s: request wdi pin err\n", __func__);
++    	return ret;
++    }
++    task = kthread_run(sgm820_feed_dog, dev, "sgm820");
++    if (IS_ERR(task)){
++        printk(KERN_ERR "create sgm820 thread failed!\n");
++    }
++    return 0;
++}
++
++static int sgm820_wdt_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++
++static struct platform_driver sgm820_wdt_driver = {
++	.probe		= sgm820_wdt_probe,
++	.remove		= sgm820_wdt_remove,
++	.driver		= {
++		.name	= "sgm820_wdt",
++		.of_match_table = sgm820_wdt_of_match_table,
++	},
++};
++
++module_platform_driver(sgm820_wdt_driver);
++MODULE_DESCRIPTION("sgm820 Processor Watchdog");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:sgm820_wdt");
+diff --git a/module_drivers/dts/Makefile b/module_drivers/dts/Makefile
+new file mode 100644
+index 000000000..fa46ff2a1
+--- /dev/null
++++ b/module_drivers/dts/Makefile
+@@ -0,0 +1,18 @@
++# SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_DT_HALLEY5_V20)	+= halley5_v20.dtb
++dtb-$(CONFIG_DT_HALLEY5_V30)	+= halley5_v30.dtb
++dtb-$(CONFIG_DT_VIOMI_V2000)	+= viomi_v2000.dtb
++dtb-$(CONFIG_DT_HIPPO_V10)	+= hippo_v10.dtb
++dtb-$(CONFIG_DT_HIPPO_V12)	+= hippo_v12.dtb
++dtb-$(CONFIG_DT_PANDA_V10)	+= panda_v10.dtb
++dtb-$(CONFIG_DT_HALLEY6_V10)	+= halley6_v10.dtb
++dtb-$(CONFIG_DT_HALLEY6_V20)	+= halley6_v20.dtb
++dtb-$(CONFIG_DT_GEWU_V10)	+= gewu_v10.dtb
++dtb-$(CONFIG_DT_KALE_V10)	+= kale_v10.dtb
++dtb-$(CONFIG_DT_X2000_LIFESMART_480P) += x2000_lifesmart_480p_harmony.dtb
++
++dtb-$(CONFIG_DT_X1000_MODULE)	+= x1000_module_base.dtb
++dtb-$(CONFIG_DT_X1600_MODULE)	+= x1600_module_base.dtb
++dtb-$(CONFIG_DT_X2000_MODULE)	+= x2000_module_base.dtb
++
++obj-$(CONFIG_BUILTIN_DTB)	+= $(addsuffix .o, $(dtb-y))
+diff --git a/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_2V1.dtsi b/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_2V1.dtsi
+new file mode 100644
+index 000000000..1c83e8920
+--- /dev/null
++++ b/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_2V1.dtsi
+@@ -0,0 +1,83 @@
++
++&i2c3 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default", "default";
++	pinctrl-0 = <&i2c3_pa>,<&cim_vic_mclk_pe>;
++
++	/*RD_X2000_HALLEY5_CAMERA_V4.2 DVP interface*/
++	ov2735_0:ov2735@0x3c {
++		status = "ok";
++		compatible = "ovti,ov2735b";
++		reg = <0x3c>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vic_pa_low_10bit>;
++
++		avdd-supply = <&cam_avdd>;
++		dvdd-supply = <&cam_dvdd>;
++		dovdd-supply = <&cam_dovdd>;
++		ingenic,rst-gpio = <&gpa 10 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutp-gpio = <&gpb 3 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutn-gpio = <&gpb 0 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov2735_ep0:endpoint {
++				remote-endpoint = <&isp0_ep>;
++				bus-width = <10>;	/* Used data lines */
++				data-shift = <0>;	/* Lines 9:0 are used */
++
++				/* If hsync-active/vsync-active are missing,
++				   embedded BT.656 sync is used */
++				hsync-active = <1>;	/* Active high */
++				vsync-active = <1>;	/* Active high */
++				data-active = <1>;	/* Active high */
++				pclk-sample = <1>;	/* Rising */
++			};
++		};
++	};
++
++
++	/*RD_X2000_HALLEY5_CAMERA_V4.2 MIPI interface*/
++	ov2735_1:ov2735@0x3d {
++		status = "ok";
++		compatible = "ovti,ov2735a";
++		reg = <0x3d>;
++
++		avdd-supply = <&cam_avdd>;
++		dvdd-supply = <&cam_dvdd>;
++		dovdd-supply = <&cam_dovdd>;
++		ingenic,rst-gpio = <&gpa 11 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutp-gpio = <&gpb 7 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutn-gpio = <&gpb 1 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov2735_ep1:endpoint {
++				remote-endpoint = <&isp1_ep>;
++			};
++		};
++	};
++};
++
++
++
++&isp0_ep {
++	remote-endpoint = <&ov2735_ep0>;
++	bus-width = <10>;	/* Used data lines */
++	data-shift = <0>;	/* Lines 9:0 are used */
++	bus-type = <5>;
++
++	/* If hsync-active/vsync-active are missing,
++	   embedded BT.656 sync is used */
++	hsync-active = <1>;	/* Active high */
++	vsync-active = <1>;	/* Active high */
++	data-active = <1>;	/* Active high */
++	pclk-sample = <1>;	/* Rising */
++};
++
++&isp1_ep {
++	remote-endpoint = <&ov2735_ep1>;
++	data-lanes = <3 4>;
++	clk-lanes = <5>;
++	bus-type = <4>;
++};
+diff --git a/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_3V2.dtsi b/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_3V2.dtsi
+new file mode 100644
+index 000000000..fea00106b
+--- /dev/null
++++ b/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_3V2.dtsi
+@@ -0,0 +1,38 @@
++
++&i2c3 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa>;
++
++	/*RD_X2000_HALLEY5_CAMERA_V3.2*/
++	ov4689_0:ov4689@0x21 {
++		status = "ok";
++		compatible = "ovti,ov4689";
++		reg = <0x21>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim_vic_mclk_pe>;
++
++		avdd-supply = <&cam_avdd>;
++		dvdd-supply = <&cam_dvdd>;
++		dovdd-supply = <&cam_dovdd>;
++		ingenic,rst-gpio = <&gpa 11 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutp-gpio = <&gpb 7 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutn-gpio = <&gpb 1 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov4689_ep0:endpoint {
++				remote-endpoint = <&isp0_ep>;
++			};
++		};
++	};
++};
++
++&isp0_ep {
++	remote-endpoint = <&ov4689_ep0>;
++	data-lanes = <0 1>;
++	clk-lanes = <2>;
++};
++
++
+diff --git a/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_3V2_4LANE.dtsi b/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_3V2_4LANE.dtsi
+new file mode 100644
+index 000000000..ce83e711c
+--- /dev/null
++++ b/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_3V2_4LANE.dtsi
+@@ -0,0 +1,35 @@
++
++&i2c3 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa>;
++
++	/*RD_X2000_HALLEY5_CAMERA_V3.2*/
++	ov4689_0:ov4689@0x21 {
++		status = "ok";
++		compatible = "ovti,ov4689";
++		reg = <0x21>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim_vic_mclk_pe>;
++
++		ingenic,rst-gpio = <&gpa 11 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutp-gpio = <&gpb 7 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutn-gpio = <&gpb 1 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov4689_ep0:endpoint {
++				remote-endpoint = <&isp0_ep>;
++			};
++		};
++	};
++};
++
++&isp0_ep {
++	remote-endpoint = <&ov4689_ep0>;
++	data-lanes = <0 1 3 4>;
++	clk-lanes = <2>;
++};
++
++
+diff --git a/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_4V2.dtsi b/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_4V2.dtsi
+new file mode 100644
+index 000000000..21a1ff204
+--- /dev/null
++++ b/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_4V2.dtsi
+@@ -0,0 +1,83 @@
++
++&i2c3 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default", "default";
++	pinctrl-0 = <&i2c3_pa>,<&cim_vic_mclk_pe>;
++
++	/*RD_X2000_HALLEY5_CAMERA_V4.2 DVP interface*/
++	ov2735_0:ov2735@0x3d {
++		status = "ok";
++		compatible = "ovti,ov2735b";
++		reg = <0x3d>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vic_pa_low_10bit>;
++
++		avdd-supply = <&cam_avdd>;
++		dvdd-supply = <&cam_dvdd>;
++		dovdd-supply = <&cam_dovdd>;
++		ingenic,rst-gpio = <&gpa 10 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutp-gpio = <&gpb 3 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutn-gpio = <&gpb 0 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov2735_ep0:endpoint {
++				remote-endpoint = <&isp0_ep>;
++				bus-width = <10>;	/* Used data lines */
++				data-shift = <0>;	/* Lines 9:0 are used */
++
++				/* If hsync-active/vsync-active are missing,
++				   embedded BT.656 sync is used */
++				hsync-active = <1>;	/* Active high */
++				vsync-active = <1>;	/* Active high */
++				data-active = <1>;	/* Active high */
++				pclk-sample = <1>;	/* Rising */
++			};
++		};
++	};
++
++
++	/*RD_X2000_HALLEY5_CAMERA_V4.2 MIPI interface*/
++	ov2735_1:ov2735@0x3c {
++		status = "ok";
++		compatible = "ovti,ov2735a";
++		reg = <0x3c>;
++
++		avdd-supply = <&cam_avdd>;
++		dvdd-supply = <&cam_dvdd>;
++		dovdd-supply = <&cam_dovdd>;
++		ingenic,rst-gpio = <&gpa 11 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutp-gpio = <&gpb 7 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutn-gpio = <&gpb 1 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov2735_ep1:endpoint {
++				remote-endpoint = <&isp1_ep>;
++			};
++		};
++	};
++};
++
++
++
++&isp0_ep {
++	remote-endpoint = <&ov2735_ep0>;
++	bus-width = <10>;	/* Used data lines */
++	data-shift = <0>;	/* Lines 9:0 are used */
++	bus-type = <5>;
++
++	/* If hsync-active/vsync-active are missing,
++	   embedded BT.656 sync is used */
++	hsync-active = <1>;	/* Active high */
++	vsync-active = <1>;	/* Active high */
++	data-active = <1>;	/* Active high */
++	pclk-sample = <1>;	/* Rising */
++};
++
++&isp1_ep {
++	remote-endpoint = <&ov2735_ep1>;
++	data-lanes = <3 4>;
++	clk-lanes = <5>;
++	bus-type = <4>;
++};
+diff --git a/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_4V3.dtsi b/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_4V3.dtsi
+new file mode 100644
+index 000000000..9ddf28ea4
+--- /dev/null
++++ b/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_4V3.dtsi
+@@ -0,0 +1,65 @@
++
++&i2c3 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa>, <&cim_vic_mclk_pe>;
++
++	/*RD_X2000_HALLEY5_CAMERA_V4.2 DVP interface*/
++	ov2735_0:ov2735@3d {
++		status = "ok";
++		compatible = "ovti,ov2735a";
++		reg = <0x3d>;
++
++		avdd-supply = <&cam_avdd>;
++		dvdd-supply = <&cam_dvdd>;
++		dovdd-supply = <&cam_dovdd>;
++		ingenic,rst-gpio = <&gpa 10 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutp-gpio = <&gpb 3 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutn-gpio = <&gpb 0 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov2735_ep0:endpoint {
++				remote-endpoint = <&isp0_ep>;
++			};
++		};
++	};
++
++
++	/*RD_X2000_HALLEY5_CAMERA_V4.2 MIPI interface*/
++	ov2735_1:ov2735@3c {
++		status = "ok";
++		compatible = "ovti,ov2735a";
++		reg = <0x3c>;
++
++		avdd-supply = <&cam_avdd>;
++		dvdd-supply = <&cam_dvdd>;
++		dovdd-supply = <&cam_dovdd>;
++		ingenic,rst-gpio = <&gpa 11 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutp-gpio = <&gpb 7 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutn-gpio = <&gpb 1 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov2735_ep1:endpoint {
++				remote-endpoint = <&isp1_ep>;
++			};
++		};
++	};
++};
++
++
++
++&isp0_ep {
++	remote-endpoint = <&ov2735_ep0>;
++	data-lanes = <0 1>;
++	clk-lanes = <2>;
++	bus-type = <4>;
++};
++
++&isp1_ep {
++	remote-endpoint = <&ov2735_ep1>;
++	data-lanes = <3 4>;
++	clk-lanes = <5>;
++	bus-type = <4>;
++};
+diff --git a/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_4V3_2KALE.dtsi b/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_4V3_2KALE.dtsi
+new file mode 100644
+index 000000000..ad3b2b175
+--- /dev/null
++++ b/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_4V3_2KALE.dtsi
+@@ -0,0 +1,58 @@
++
++&i2c3 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa>, <&cim_vic_mclk_pe>;
++
++	/*RD_X2000_HALLEY5_CAMERA_V4.2 DVP interface*/
++	ov2735_0:ov2735@3d {
++		status = "ok";
++		compatible = "ovti,ov2735a";
++		reg = <0x3d>;
++
++		ingenic,rst-gpio = <&gpa 10 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutp-gpio = <&gpb 31 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutn-gpio = <&gpb 28 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov2735_ep0:endpoint {
++				remote-endpoint = <&isp0_ep>;
++			};
++		};
++	};
++
++
++	/*RD_X2000_HALLEY5_CAMERA_V4.2 MIPI interface*/
++	ov2735_1:ov2735@3c {
++		status = "ok";
++		compatible = "ovti,ov2735a";
++		reg = <0x3c>;
++
++		ingenic,rst-gpio = <&gpa 11 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutp-gpio = <&gpb 29 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutn-gpio = <&gpb 30 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		port {
++			ov2735_ep1:endpoint {
++				remote-endpoint = <&isp1_ep>;
++			};
++		};
++	};
++};
++
++
++
++&isp0_ep {
++	remote-endpoint = <&ov2735_ep0>;
++	data-lanes = <0 1>;
++	clk-lanes = <2>;
++	bus-type = <4>;
++};
++
++&isp1_ep {
++	remote-endpoint = <&ov2735_ep1>;
++	data-lanes = <3 4>;
++	clk-lanes = <5>;
++	bus-type = <4>;
++};
+diff --git a/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_5V0.dtsi b/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_5V0.dtsi
+new file mode 100644
+index 000000000..49f1f501e
+--- /dev/null
++++ b/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_5V0.dtsi
+@@ -0,0 +1,38 @@
++
++&i2c3 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa>;
++
++	/*RD_X2000_HALLEY5_CAMERA_V3.2*/
++	AR0144_0:AR0144@0x18 {
++		status = "ok";
++		compatible = "onsemi,ar0144";
++		reg = <0x18>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim_vic_mclk_pe>;
++
++		avdd-supply = <&cam_avdd>;
++		dvdd-supply = <&cam_dvdd>;
++		dovdd-supply = <&cam_dovdd>;
++		ingenic,rst-gpio = <&gpa 11 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,expo-gpio = <&gpa 15 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,expo-oe = <&gpa 10 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			AR0144_ep0:endpoint {
++				remote-endpoint = <&isp0_ep>;
++			};
++		};
++	};
++};
++
++&isp0_ep {
++	remote-endpoint = <&AR0144_ep0>;
++	data-lanes = <0 1>;
++	clk-lanes = <2>;
++};
++
++
+diff --git a/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_cim.dtsi b/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_cim.dtsi
+new file mode 100644
+index 000000000..985db5224
+--- /dev/null
++++ b/module_drivers/dts/halley5_cameras/RD_X2000_HALLEY5_CAMERA_cim.dtsi
+@@ -0,0 +1,70 @@
++
++&i2c3 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa>;
++
++	/*HALLEY5_CAMERA_V4.2*/
++	ov2735_0:ov2735b@0x3d {
++		status = "ok";
++		compatible = "ovti,ov2735b";
++		reg = <0x3d>;
++		/*
++		pinctrl-names = "default","cim";
++		pinctrl-0 = <&cim_vic_mclk_pe>, <&cim_pa>;
++
++		resetb-gpios = <&gpa 10 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		*/
++
++		port {
++			ov2735b_ep0:endpoint {
++				remote-endpoint = <&cim_0>;
++			};
++		};
++	};
++
++	/*HALLEY5_CAMRERA_V5.0*/
++	AR0144:AR0144@0x18 {
++		status = "ok";
++		compatible = "onsemi,ar0144";
++		reg = <0x18>;
++		pinctrl-names = "default","cim";
++		pinctrl-0 = <&cim_vic_mclk_pe>, <&cim_pa>;
++
++		resetb-gpios = <&gpa 11 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		pwdn-gpios = <&gpa 10 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++
++
++		port {
++			AR0144_0:endpoint {
++				remote-endpoint = <&cim_1>;
++			};
++		};
++	};
++
++};
++
++
++&cim {
++	status = "okay";
++	port {
++		cim_0: endpoint0@0 {
++			remote-endpoint = <&ov2735b_ep0>;
++			bus-width = <8>;
++			data-shift = <0>;
++			bus-type = <5>;
++			hsync-active = <1>;
++			vsync-active = <0>;
++			data-active = <1>;
++			pclk-sample = <1>;
++		};
++		cim_1: endpoint1@1 {
++			remote-endpoint = <&AR0144_0>;
++			data-lanes = <0 1>;
++			clk-lanes = <2>;
++		};
++	};
++};
++
+diff --git a/module_drivers/dts/halley5_v20.dts b/module_drivers/dts/halley5_v20.dts
+new file mode 100644
+index 000000000..7dc708962
+--- /dev/null
++++ b/module_drivers/dts/halley5_v20.dts
+@@ -0,0 +1,500 @@
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include "x2000.dtsi"
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <generated/autoconf.h>
++
++#ifdef  CONFIG_RD_X2000_HALLEY5_CAMERA_2V1
++#include "halley5_cameras/RD_X2000_HALLEY5_CAMERA_2V1.dtsi"
++#elif CONFIG_RD_X2000_HALLEY5_CAMERA_3V2
++#include "halley5_cameras/RD_X2000_HALLEY5_CAMERA_3V2.dtsi"
++#elif CONFIG_RD_X2000_HALLEY5_CAMERA_4V2
++#include "halley5_cameras/RD_X2000_HALLEY5_CAMERA_4V2.dtsi"
++#elif CONFIG_RD_X2000_HALLEY5_CAMERA_4V3
++#include "halley5_cameras/RD_X2000_HALLEY5_CAMERA_4V3.dtsi"
++#elif CONFIG_RD_X2000_HALLEY5_CAMERA_5V0
++#include "halley5_cameras/RD_X2000_HALLEY5_CAMERA_5V0.dtsi"
++#endif
++
++/ {
++	compatible = "ingenic,halley5", "ingenic,x2000";
++
++	/*chosen {
++		bootargs = "console=ttyS1,115200 mem=128M@0x0ip=off init=/linuxrc ubi.mtd=3 root=ubi0:rootfs ubi.mtd=4 rootfstype=ubifs rw";
++	};*/
++
++	reserved-memory {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges =<>;
++
++		reserved_memory: reserved_mem@0x6000000{
++		      compatible = "shared-dma-pool";
++		      reg = <0x06000000 0x2000000>;
++		};
++	};
++
++		  cam_avdd: cam_regulator_avdd {
++			  compatible = "regulator-fixed";
++			  regulator-name = "cam_avdd";
++			  regulator-min-microvolt = <2800000>;
++			  regulator-max-microvolt = <2800000>;
++			  regulator-always-on;
++			  regulator-boot-on;
++		  };
++		  cam_dvdd: cam_regulator_dvdd {
++			  compatible = "regulator-fixed";
++			  regulator-name = "cam_dvdd";
++			  regulator-min-microvolt = <1200000>;
++			  regulator-max-microvolt = <1200000>;
++			  regulator-always-on;
++			  regulator-boot-on;
++		  };
++		  cam_dovdd: cam_regulator_dovdd {
++			   compatible = "regulator-fixed";
++			   regulator-name = "cam_dovdd";
++			   regulator-min-microvolt = <1800000>;
++			   regulator-max-microvolt = <1800000>;
++			   regulator-always-on;
++			   regulator-boot-on;
++		  };
++};
++
++&uart0 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pd>;
++};
++
++&uart2 {
++	status = "disable";
++};
++
++&uart3 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pc>;
++};
++
++&cpufreq {
++	status = "okay";
++	operating-points = <
++		/*KHZ uV */
++		1200000	900000
++		750000	900000
++		600000	900000
++		500000	900000
++		400000	900000
++		375000	900000
++		300000	900000
++		200000	900000
++			>;
++
++};
++
++&pinctrl {
++	ingenic,gpa_voltage = <GPIO_VOLTAGE_1V8>;
++};
++
++&i2c0 {
++	status = "okay";
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0_pc>;
++
++	focaltech@0x38{
++		compatible = "focaltech,fts"; /* do not modify */
++		reg = <0x38>; /* do not modify */
++		focaltech,reset-gpio = <&gpc 8 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>; /* RST pin */
++		focaltech,irq-gpio = <&gpc 9 IRQ_TYPE_EDGE_FALLING INGENIC_GPIO_NOBIAS>; /* INT pin */
++		focaltech,max-touch-number = <5>;
++		focaltech,display-coords = <0 0 1080 1920>;	/* resolution */
++
++		/* key settings */
++		focaltech,have-key;
++		focaltech,key-number = <3>;
++		focaltech,keys = <139 172 158>; /* key codes*/
++		focaltech,key-x-coords = <200 600 800>; /* keys x coords */
++		focaltech,key-y-coords = <2000 2000 2000>; /* keys y coords */
++
++	};
++
++};
++
++&i2c3 {
++	status = "okay";
++};
++
++&i2c4 {
++	status = "disable";
++};
++
++
++&felix {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&helix {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&ispcam0 {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&ispcam1 {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&rotate {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&pdma {
++	status = "okay";
++};
++
++&msc0 {
++	status = "disable";
++	/*mmc-hs200-1_8v;*/
++	cap-mmc-highspeed;
++	non-removable;
++	max-frequency = <50000000>;
++	bus-width = <4>;
++	non-removable;
++	voltage-ranges = <1800 3300>;
++
++	/* special property */
++	ingenic,rst-gpios = <0>;
++};
++
++&msc1 {
++	status = "okay";
++	pinctrl-names ="default","enable", "disable";
++	pinctrl-0 = <&msc1_4bit>;
++	pinctrl-1 = <&rtc32k_enable>;
++	pinctrl-2 = <&rtc32k_disable>;
++
++	sd-uhs-sdr104;
++	max-frequency = <100000000>;
++	bus-width = <4>;
++	voltage-ranges = <1800 3300>;
++	non-removable;
++
++	ingenic,sdio_clk = <1>;
++	keep-power-in-suspend;
++
++	/* special property */
++	ingenic,sdr-gpios = <0>;
++	ingenic,rst-gpios = <0>;
++	ingenic,removal-manual; /*removal-dontcare, removal-nonremovable, removal-removable, removal-manual*/
++
++	bcmdhd_wlan: bcmdhd_wlan {
++		 compatible = "android,bcmdhd_wlan";
++		 ingenic,sdio-irq = <&gpd 0 IRQ_TYPE_LEVEL_HIGH INGENIC_GPIO_NOBIAS>;
++		 ingenic,sdio-reset = <&gpd 1 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++};
++
++&msc2 {
++	status = "okay";
++	pinctrl-names ="default";
++	pinctrl-0 = <&msc2_4bit>;
++	sd-uhs-sdr104;
++	/*cap-mmc-highspeed;*/
++	max-frequency = <200000000>;
++	bus-width = <4>;
++	voltage-ranges = <1800 3300>;
++
++	/* special property */
++	cd-gpios = <&gpc 12 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	wp-gpios = <0>;
++	ingenic,sdr-gpios = <&gpc 0 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	ingenic,rst-gpios = <0>;
++};
++
++
++&mac1 {
++	pinctrl-names = "default", "reset";
++	pinctrl-0 = <&mac1_rgmii_p0_normal>, <&mac1_rgmii_p1_normal>;
++	pinctrl-1 = <&mac1_rgmii_p0_rst>, <&mac1_rgmii_p1_normal>;
++	status = "okay";
++	ingenic,rst-gpio = <&gpb 16 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,rst-ms = <10>;
++	ingenic,rst-delay-ms = <15>;
++	ingenic,mac-mode = <RGMII>;
++	ingenic,mode-reg = <0xb00000e8>;
++	ingenic,rx-clk-delay = <0x0>;
++	ingenic,tx-clk-delay = <0x3f>;
++};
++
++&sfc {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&sfc_pe>;
++	ingenic,sfc-init-frequency = <200000000>;
++	ingenic,sfc-max-frequency = <320000000>;
++	ingenic,use_ofpart_info  = /bits/ 8 <0>;
++	ingenic,spiflash_param_offset = <0>;
++
++	norflash@0 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nor flash partition */
++			uboot@0 {
++				label = "uboot";
++				reg = <0x0000000 0x40000>;
++				/*read-only;*/
++			};
++
++			kernel@40000 {
++				label = "kernel";
++				reg = <0x40000 0x300000>;
++			};
++
++			rootfs@360000 {
++				label = "rootfs";
++				reg = <0x360000 0xca0000>;
++			};
++		};
++	};
++
++	nandflash@1 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nand flash partition */
++			partition@0 {
++				label = "uboot";
++				reg = <0x0000000 0x100000>;
++				/*read-only;*/
++			};
++
++			partition@100000 {
++				label = "kernel";
++				reg = <0x100000 0x800000>;
++			};
++
++			partition@900000 {
++				label = "rootfs";
++				reg = <0x900000 0xf700000>;
++			};
++		};
++	};
++
++};
++
++&spi0 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pb>;
++
++	spi-max-frequency = <54000000>;
++	num-cs = <2>;
++	cs-gpios = <0>, <0>;
++	/*cs-gpios = <&gpa 27 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>, <&gpa 27 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;*/
++	ingenic,chnl = <0>;
++	ingenic,allow_cs_same = <1>;
++	ingenic,bus_num = <0>;
++	ingenic,has_dma_support = <0>;
++	ingenic,spi-src-clk = <1>;/*0.ext; 1.ssi*/
++
++	/* Add SPI interface device */
++	spidev: spidev@0 {
++		compatible = "rohm,dh2228fv";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++	};
++};
++
++&dtrng {
++	status = "okay";
++};
++
++&pwm {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm0_pd>;
++	status = "okay";
++};
++
++&otg {
++	g-use-dma;
++	dr_mode = "otg";
++	device-using-dma = <1>;
++	status = "okay";
++};
++
++&otg_phy {
++	dr_mode = "otg";
++	status = "okay";
++	ingenic,id-dete-gpio = <&gpc 27 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,vbus-dete-gpio = <&gpd 17 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,drvvbus-gpio = <&gpe 22 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++};
++
++&as_be_baic {
++	pinctrl-names = "default";
++	pinctrl-0 =  <&baic4_pd>;
++};
++
++&as_dmic {
++	pinctrl-names = "default";
++	pinctrl-0 = <&dmic_pc_4ch>;
++};
++
++&icodec {
++	ingenic,spken-gpio = <&gpb 2 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++};
++
++&dpu {
++	status = "okay";
++	ingenic,disable-rdma-fb = <1>;
++	/*Defines the init state of composer fb export infomations.*/
++	ingenic,layer-exported = <1 1 0 0>;
++	ingenic,layer-frames   = <2 2 2 2>;
++	ingenic,layer-framesize = <720 1280>, <720 1280>, <320 240>, <320 240>;   /*Max framesize for each layer.*/
++	layer,color_mode	= <0 0 0 0>;					/*src fmt,*/
++	layer,src-size       	= <720 1280>, <720 1280>, <320 240>, <240 200>;	/*Layer src size should smaller than framesize*/
++	layer,target-size	= <720 1280>, <720 640>, <160 240>, <240 200>;	/*Target Size should smaller than src_size.*/
++	layer,target-pos	= <0 0>, <0 640>, <340 480>, <100 980>;	/*target pos , the start point of the target panel.*/
++	layer,enable		= <1 1 1 1>;					/*layer enabled or disabled.*/
++	ingenic,logo-pan-layer	= <0>;						/*on which layer should init logo pan on.*/
++	port {
++		dpu_out_ep: endpoint {
++			remote-endpoint = <&panel_ma0060_ep>;
++	    };
++	};
++};
++
++
++/ {
++
++	extclk: extclk {
++		clock-frequency = <24000000>;
++	};
++
++	gpio_keys: gpio_keys {
++		   compatible = "gpio-keys";
++
++		   power {
++			   label = "Power";
++			   linux,code = <KEY_POWER>;
++			   gpios = <&gpe 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			   gpio-key,wakeup;
++		   };
++	   };
++
++	/*
++	 * gpd 21 bt wakeup host
++	 * gpd 22 host wakeup bt
++	 */
++	bt_power {
++		compatible = "ingenic,bt_power";
++		ingenic,reg-on-gpio = <&gpd 20 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,wake-gpio = <&gpd 21 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++
++	sound {
++		compatible = "ingenic,x2000-sound";
++		ingenic,model = "halley5_v20";
++		ingenic,spken-gpio = <&gpb 2 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	};
++
++	display-dbi {
++		compatible = "simple-bus";
++		#interrupt-cells = <1>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++		panel_ma0060 {
++			compatible = "ingenic,ma0060";
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&smart_lcd_pb_te>;
++			ingenic,vdd-en-gpio = <&gpc 3 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			ingenic,rst-gpio = <&gpc 4 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,oled-gpio = <&gpc 5 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,lcd-pwm-gpio = <&gpc 1 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,swire-gpio = <&gpc 7 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			port {
++				panel_ma0060_ep: endpoint {
++					remote-endpoint = <&dpu_out_ep>;
++				};
++			};
++		};
++	};
++/*	backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwm 1 1000000>;
++		brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
++		default-brightness-level = <4>;
++	};
++*/
++
++	spi_gpio {
++		status = "disable";
++		compatible = "spi-gpio";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		gpio-sck = <&gpb 28 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		gpio-miso = <&gpb 29 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		gpio-mosi = <&gpb 30 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		cs-gpios = <&gpb 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		num-chipselects = <1>;
++
++		/* clients */
++		spidev1: spidev1@0 {
++			status = "disable";
++			compatible = "rohm,dh2228fv";
++			reg = <0>;
++			spi-max-frequency = <500000>;
++		};
++	};
++};
++
++
++/* Board Sleep GPIO configuration. */
++/* <0 1 2 3 .... 31>, set one of the pin to state.*/
++&gpa {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpb {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpc {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpd {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
+diff --git a/module_drivers/dts/halley5_v30.dts b/module_drivers/dts/halley5_v30.dts
+new file mode 100644
+index 000000000..39018cd13
+--- /dev/null
++++ b/module_drivers/dts/halley5_v30.dts
+@@ -0,0 +1,556 @@
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include "x2000.dtsi"
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <generated/autoconf.h>
++
++#ifdef  CONFIG_RD_X2000_HALLEY5_CAMERA_2V1
++#include "halley5_cameras/RD_X2000_HALLEY5_CAMERA_2V1.dtsi"
++#elif CONFIG_RD_X2000_HALLEY5_CAMERA_3V2
++#ifdef CONFIG_OV4689_1080P_120FPS
++#include "halley5_cameras/RD_X2000_HALLEY5_CAMERA_3V2_4LANE.dtsi"
++#else
++#include "halley5_cameras/RD_X2000_HALLEY5_CAMERA_3V2.dtsi"
++#endif
++#elif CONFIG_RD_X2000_HALLEY5_CAMERA_4V2
++#include "halley5_cameras/RD_X2000_HALLEY5_CAMERA_4V2.dtsi"
++#elif CONFIG_RD_X2000_HALLEY5_CAMERA_4V3
++#include "halley5_cameras/RD_X2000_HALLEY5_CAMERA_4V3.dtsi"
++#elif CONFIG_RD_X2000_HALLEY5_CAMERA_5V0
++#include "halley5_cameras/RD_X2000_HALLEY5_CAMERA_5V0.dtsi"
++#endif
++
++/ {
++	compatible = "ingenic,halley5", "ingenic,x2000";
++
++	/*chosen {
++		bootargs = "console=ttyS1,115200 mem=128M@0x0ip=off init=/linuxrc ubi.mtd=3 root=ubi0:rootfs ubi.mtd=4 rootfstype=ubifs rw";
++	};*/
++
++	reserved-memory {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges =<>;
++
++		reserved_memory: reserved_mem@0xe000000{
++		      compatible = "shared-dma-pool";
++		      reg = <0x0e000000 0x2000000>;
++		};
++	};
++
++		  cam_avdd: cam_regulator_avdd {
++			  compatible = "regulator-fixed";
++			  regulator-name = "cam_avdd";
++			  regulator-min-microvolt = <2800000>;
++			  regulator-max-microvolt = <2800000>;
++			  regulator-always-on;
++			  regulator-boot-on;
++		  };
++		  cam_dvdd: cam_regulator_dvdd {
++			  compatible = "regulator-fixed";
++			  regulator-name = "cam_dvdd";
++			  regulator-min-microvolt = <1200000>;
++			  regulator-max-microvolt = <1200000>;
++			  regulator-always-on;
++			  regulator-boot-on;
++		  };
++		  cam_dovdd: cam_regulator_dovdd {
++			   compatible = "regulator-fixed";
++			   regulator-name = "cam_dovdd";
++			   regulator-min-microvolt = <1800000>;
++			   regulator-max-microvolt = <1800000>;
++			   regulator-always-on;
++			   regulator-boot-on;
++		  };
++};
++
++&uart0 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pd>;
++};
++
++&uart2 {
++	status = "disable";
++};
++
++&uart3 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pc>;
++};
++
++&cpufreq {
++	status = "okay";
++	operating-points = <
++		/*KHZ uV */
++		1200000	900000
++		750000	900000
++		600000	900000
++		500000	900000
++		400000	900000
++		375000	900000
++		300000	900000
++		200000	900000
++			>;
++
++};
++
++&pinctrl {
++	ingenic,gpa_voltage = <GPIO_VOLTAGE_1V8>;
++};
++
++&pinctrl {
++	touchscreen_pins:touchscreen-pins {
++		touchscreen_int_out_high:touchscreen-int-out-high {
++			ingenic,pinmux = <&gpc 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCHILVL>;
++		};
++		touchscreen_int_out_low:touchscreen-int-out-low {
++			ingenic,pinmux = <&gpc 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCLOLVL>;
++		};
++		touchscreen_int_input:touchscreen-int-input {
++			ingenic,pinmux = <&gpc 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT_FE>;
++		};
++		touchscreen_default:touchscreen-default {
++			ingenic,pinmux = <&gpc 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT>;
++		};
++	};
++};
++
++&i2c0 {
++	status = "okay";
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0_pc>;
++
++	goodix@14{
++		compatible = "goodix,gt9xx"; /* do not modify */
++		reg = <0x14>; /* do not modify */
++		reset-gpios = <&gpc 8 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>; /* RST pin */
++		irq-gpios = <&gpc 9 IRQ_TYPE_EDGE_FALLING INGENIC_GPIO_NOBIAS>; /* INT pin */
++		goodix,driver-send-cfg = <1>;
++		touchscreen-size-x = <1280>;
++		touchscreen-size-y = <720>;
++		goodix,slide-wakeup = <0>;
++		goodix,type-a-report = <0>;
++		goodix,resume-in-workqueue = <0>;
++		goodix,int-sync = <1>;
++		goodix,swap-x2y = <0>;
++		goodix,auto-update-cfg = <0>;
++		goodix,power-off-sleep = <0>;
++		goodix,pen-suppress-finger = <0>;
++		irq-flags = <2>; /* 1 rising, 2 falling */
++		pinctrl-names = "default", "int-output-high", "int-output-low", "int-input";
++		pinctrl-0 = <&touchscreen_default>;
++		pinctrl-1 = <&touchscreen_int_out_high>;
++		pinctrl-2 = <&touchscreen_int_out_low>;
++		pinctrl-3 = <&touchscreen_int_input>;
++		goodix,cfg-group0 = [
++			00 D0 02 00 05 0A 05 00 01 08 28
++			05 50 32 03 05 00 00 00 00 00 00
++			00 00 00 00 00 87 28 09 17 15 31
++			0D 00 00 02 9B 03 25 00 00 00 00
++			00 03 64 32 00 00 00 0F 36 94 C5
++			02 07 00 00 04 9B 11 00 7B 16 00
++			64 1C 00 50 25 00 42 2F 00 42 00
++			00 00 00 00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 00 00 00
++			00 00 12 10 0E 0C 0A 08 06 04 02
++			FF FF FF FF FF 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 00 00 26
++			24 22 21 20 1F 1E 1D 00 02 04 06
++			08 0A 0C FF FF FF FF FF FF FF FF
++			FF FF FF 00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 CF 01];
++	};
++
++};
++
++&i2c3 {
++	status = "okay";
++};
++
++&i2c4 {
++	status = "disable";
++};
++
++
++&felix {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&helix {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&ispcam0 {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&ispcam1 {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&rotate {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&pdma {
++	status = "okay";
++};
++
++&msc0 {
++	status = "disable";
++	/*mmc-hs200-1_8v;*/
++	cap-mmc-highspeed;
++	non-removable;
++	max-frequency = <50000000>;
++	bus-width = <4>;
++	non-removable;
++	voltage-ranges = <1800 3300>;
++
++	/* special property */
++	ingenic,rst-gpios = <0>;
++};
++
++&msc1 {
++	status = "okay";
++	pinctrl-names ="default","enable", "disable";
++	pinctrl-0 = <&msc1_4bit>;
++	pinctrl-1 = <&rtc32k_enable>;
++	pinctrl-2 = <&rtc32k_disable>;
++
++	sd-uhs-sdr104;
++	max-frequency = <100000000>;
++	bus-width = <4>;
++	voltage-ranges = <1800 3300>;
++	non-removable;
++
++	ingenic,sdio_clk = <1>;
++	keep-power-in-suspend;
++
++	/* special property */
++	ingenic,sdr-gpios = <0>;
++	ingenic,rst-gpios = <0>;
++	ingenic,removal-manual; /*removal-dontcare, removal-nonremovable, removal-removable, removal-manual*/
++
++	bcmdhd_wlan: bcmdhd_wlan {
++		 compatible = "android,bcmdhd_wlan";
++		 ingenic,sdio-irq = <&gpd 0 IRQ_TYPE_LEVEL_HIGH INGENIC_GPIO_NOBIAS>;
++		 ingenic,sdio-reset = <&gpd 1 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++};
++
++&msc2 {
++	status = "okay";
++	pinctrl-names ="default";
++	pinctrl-0 = <&msc2_4bit>;
++	sd-uhs-sdr104;
++	/*cap-mmc-highspeed;*/
++	max-frequency = <200000000>;
++	bus-width = <4>;
++	voltage-ranges = <1800 3300>;
++
++	/* special property */
++	cd-gpios = <&gpc 12 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	wp-gpios = <0>;
++	ingenic,sdr-gpios = <&gpc 0 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	ingenic,rst-gpios = <0>;
++};
++
++
++&mac1 {
++	pinctrl-names = "default", "reset";
++	pinctrl-0 = <&mac1_rgmii_p0_normal>, <&mac1_rgmii_p1_normal>;
++	pinctrl-1 = <&mac1_rgmii_p0_rst>, <&mac1_rgmii_p1_normal>;
++	status = "okay";
++	ingenic,rst-gpio = <&gpb 16 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,rst-ms = <10>;
++	ingenic,rst-delay-ms = <15>;
++	ingenic,mac-mode = <RGMII>;
++	ingenic,mode-reg = <0xb00000e8>;
++	ingenic,rx-clk-delay = <0x0>;
++	ingenic,tx-clk-delay = <0x3f>;
++	/*force mac mode*/
++	/*
++	ingenic,mac-force = <MAC_ON>;
++	ingenic,mac-autoneg = <MAC_ON>;
++	ingenic,mac-speed = <MAC_SPEED_1000M>;
++	ingenic,mac-duplex = <MAC_DUPLEX_HALF>;
++	ingenic,no_phy_connect;
++	*/
++};
++
++&sfc {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&sfc_pe>;
++	ingenic,sfc-init-frequency = <200000000>;
++	ingenic,sfc-max-frequency = <320000000>;
++	ingenic,use_ofpart_info  = /bits/ 8 <0>;
++	ingenic,spiflash_param_offset = <0>;
++
++	norflash@0 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nor flash partition */
++			uboot@0 {
++				label = "uboot";
++				reg = <0x0000000 0x40000>;
++				/*read-only;*/
++			};
++
++			kernel@40000 {
++				label = "kernel";
++				reg = <0x40000 0x300000>;
++			};
++
++			rootfs@360000 {
++				label = "rootfs";
++				reg = <0x360000 0xca0000>;
++			};
++		};
++	};
++
++	nandflash@1 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nand flash partition */
++			partition@0 {
++				label = "uboot";
++				reg = <0x0000000 0x100000>;
++				/*read-only;*/
++			};
++
++			partition@100000 {
++				label = "kernel";
++				reg = <0x100000 0x800000>;
++			};
++
++			partition@900000 {
++				label = "rootfs";
++				reg = <0x900000 0xf700000>;
++			};
++		};
++	};
++
++};
++
++&spi0 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pb>;
++
++	spi-max-frequency = <54000000>;
++	num-cs = <2>;
++	cs-gpios = <0>, <0>;
++	/*cs-gpios = <&gpa 27 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>, <&gpa 27 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;*/
++	ingenic,chnl = <0>;
++	ingenic,allow_cs_same = <1>;
++	ingenic,bus_num = <0>;
++	ingenic,has_dma_support = <0>;
++	ingenic,spi-src-clk = <1>;/*0.ext; 1.ssi*/
++
++	/* Add SPI interface device */
++	spidev: spidev@0 {
++		compatible = "rohm,dh2228fv";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++	};
++};
++
++&dtrng {
++	status = "okay";
++};
++
++&pwm {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm1_pc>;
++};
++
++&otg {
++	g-use-dma;
++	dr_mode = "otg";
++	device-using-dma = <1>;
++	status = "okay";
++};
++
++&otg_phy {
++	dr_mode = "otg";
++	status = "okay";
++	ingenic,id-dete-gpio = <&gpb 29 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,vbus-dete-gpio = <&gpd 17 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,drvvbus-gpio = <&gpe 22 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++};
++
++&as_be_baic {
++	pinctrl-names = "default";
++	pinctrl-0 =  <&baic4_pd>;
++};
++
++&as_dmic {
++	pinctrl-names = "default";
++	pinctrl-0 = <&dmic_pc_4ch>;
++};
++
++&icodec {
++	ingenic,spken-gpio = <&gpb 2 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++};
++
++&dpu {
++	status = "okay";
++	ingenic,disable-rdma-fb = <1>;
++	/*Defines the init state of composer fb export infomations.*/
++	ingenic,layer-exported = <1 1 0 0>;
++	ingenic,layer-frames   = <3 3 1 2>;
++	ingenic,layer-framesize = <720 1280>, <720 1280>, <720 1280>, <320 240>;   //Max framesize for each layer.
++	layer,color_mode	= <1 6 0 0>;					//src fmt
++	layer,src-size       	= <720 1280>, <720 1280>, <720 1280>, <240 200>;	//Layer src size should smaller than framesize
++	layer,target-size	= <720 1280>, <720 1280>, <720 1280>, <240 200>;	//Target Size should smaller than src_size.
++	layer,target-pos	= <0 0>, <0 0>, <0 0>, <100 980>;	//target pos , the start point of the target panel.
++	layer,enable		= <1 1 0 0>;					//layer enabled or disabled.
++	ingenic,logo-pan-layer	= <0>;						//on which layer should init logo pan on.
++	/*memory-region=<&reserved_memory>;*/
++	port {
++		dpu_out_ep: endpoint {
++			remote-endpoint = <&panel_kd050hdfia020_ep>;
++	    };
++	};
++};
++
++
++/ {
++
++	extclk: extclk {
++		clock-frequency = <24000000>;
++	};
++
++	gpio_keys: gpio_keys {
++		   compatible = "gpio-keys";
++
++		   power {
++			   label = "Power";
++			   linux,code = <KEY_POWER>;
++			   gpios = <&gpe 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			   gpio-key,wakeup;
++		   };
++	   };
++
++	/*
++	 * gpd 21 bt wakeup host
++	 * gpd 22 host wakeup bt
++	 */
++	bt_power {
++		compatible = "ingenic,bt_power";
++		ingenic,reg-on-gpio = <&gpd 20 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,wake-gpio = <&gpd 21 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++
++	sound {
++		compatible = "ingenic,x2000-sound";
++		ingenic,model = "halley5_v30";
++		ingenic,spken-gpio = <&gpb 2 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	};
++
++	display-dbi {
++		compatible = "simple-bus";
++		#interrupt-cells = <1>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++		panel_kd050hdfia020 {
++			compatible = "ingenic,kd050hdfia020";
++			status = "okay";
++			pinctrl-names = "default";
++			ingenic,vdd-en-gpio = <&gpc 3 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,rst-gpio = <&gpc 4 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		/*	ingenic,lcd-pwm-gpio = <&gpc 1 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;*/
++			port {
++				panel_kd050hdfia020_ep: endpoint {
++					remote-endpoint = <&dpu_out_ep>;
++				};
++			};
++		};
++	};
++	backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwm 1 1000000>;
++		brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
++		default-brightness-level = <4>;
++	};
++
++
++	spi_gpio {
++		status = "disable";
++		compatible = "spi-gpio";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		gpio-sck = <&gpb 28 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		gpio-miso = <&gpb 29 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		gpio-mosi = <&gpb 30 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		cs-gpios = <&gpb 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		num-chipselects = <1>;
++
++		/* clients */
++		spidev1: spidev1@0 {
++			status = "disable";
++			compatible = "rohm,dh2228fv";
++			reg = <0>;
++			spi-max-frequency = <500000>;
++		};
++	};
++};
++
++
++/* Board Sleep GPIO configuration. */
++/* <0 1 2 3 .... 31>, set one of the pin to state.*/
++&gpa {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpb {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpc {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpd {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
+diff --git a/module_drivers/dts/halley6_cameras/RD_X1600_HALLEY6_DVP_CAMERA.dtsi b/module_drivers/dts/halley6_cameras/RD_X1600_HALLEY6_DVP_CAMERA.dtsi
+new file mode 100644
+index 000000000..1966c5484
+--- /dev/null
++++ b/module_drivers/dts/halley6_cameras/RD_X1600_HALLEY6_DVP_CAMERA.dtsi
+@@ -0,0 +1,40 @@
++&i2c0 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0_pa>;
++
++	sc031gs_0:sc031gs@0x30 {
++		status = "okay";
++		compatible = "sc031gs";
++		reg = <0x30>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim_mipi_mclk_pc>, <&cim_pa>;
++
++		resetb-gpios = <&gpa 30 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		vcc-en-gpios = <&gpb 12 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			sc031gs_ep0:endpoint {
++				remote-endpoint = <&cim_0>;
++			};
++		};
++	};
++};
++
++&cim {
++	status = "okay";
++	port {
++		cim_0: endpoint@0 {
++			remote-endpoint = <&sc031gs_ep0>;
++			bus-width = <8>;
++			data-shift = <0>;
++			bus-type = <5>;
++			hsync-active = <1>;
++			vsync-active = <0>;
++			data-active = <1>;
++			pclk-sample = <1>;
++		};
++	};
++};
+diff --git a/module_drivers/dts/halley6_cameras/RD_X1600_HALLEY6_MIPI_CAMERA.dtsi b/module_drivers/dts/halley6_cameras/RD_X1600_HALLEY6_MIPI_CAMERA.dtsi
+new file mode 100644
+index 000000000..52128ffe7
+--- /dev/null
++++ b/module_drivers/dts/halley6_cameras/RD_X1600_HALLEY6_MIPI_CAMERA.dtsi
+@@ -0,0 +1,35 @@
++&i2c0 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0_pa>;
++
++	sc031gs_0:sc031gs@0x30 {
++		status = "okay";
++		compatible = "sc031gs";
++		reg = <0x30>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim_mipi_mclk_pc>;
++
++		resetb-gpios = <&gpa 30 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		vcc-en-gpios = <&gpb 12 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++
++		port {
++			sc031gs_ep0:endpoint {
++				remote-endpoint = <&cim_0>;
++			};
++		};
++	};
++};
++
++&cim {
++	status = "okay";
++	port {
++		cim_0: endpoint@0 {
++			remote-endpoint = <&sc031gs_ep0>;
++			data-lanes = <0 1>;
++			clk-lanes = <2>;
++		};
++	};
++};
+diff --git a/module_drivers/dts/halley6_lcd/RD_X1600_HALLEY6_RGB_LCD_1V0.dtsi b/module_drivers/dts/halley6_lcd/RD_X1600_HALLEY6_RGB_LCD_1V0.dtsi
+new file mode 100644
+index 000000000..810e110b2
+--- /dev/null
++++ b/module_drivers/dts/halley6_lcd/RD_X1600_HALLEY6_RGB_LCD_1V0.dtsi
+@@ -0,0 +1,117 @@
++/ {
++	display-dbi {
++		compatible = "simple-bus";
++		#interrupt-cells = <1>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++		panel_kd050wvfpa029 {
++			compatible = "ingenic,kd050wvfpa029-rgb";
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&tft_lcd_pa_rgb888>;
++/*			ingenic,lcd-pwm-gpio = <&gpc 0 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;*/
++			ingenic,vdd-en-gpio = <&gpa 31 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			port {
++				panel_kd050wvfpa029_ep: endpoint {
++					remote-endpoint = <&dpu_out_ep>;
++				};
++			};
++		};
++	};
++	backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwm 0 1000000>;
++	    brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
++	    default-brightness-level = <4>;
++	};
++};
++
++&dpu {
++	status = "okay";
++	port {
++		dpu_out_ep: endpoint {
++		remote-endpoint = <&panel_kd050wvfpa029_ep>;
++	    };
++	};
++};
++
++&i2c1 {
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	status = "okay";
++	pinctrl-0 = <&i2c1_pb_f2>;
++
++	goodix@0x14{
++		compatible = "goodix,gt9xx"; /* do not modify */
++		reg = <0x14>; /* do not modify */
++		interrupt-parent = <&gpa>; /* INT pin */
++		interrupts = <9>;
++		reset-gpios = <&gpb 14 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>; /* RST pin */
++		irq-gpios = <&gpb 17 IRQ_TYPE_EDGE_FALLING INGENIC_GPIO_NOBIAS>; /* INT pin */
++		goodix,driver-send-cfg = <1>;
++		touchscreen-size-x = <480>;
++		touchscreen-size-y = <800>;
++		goodix,slide-wakeup = <0>;
++		goodix,type-a-report = <0>;
++		goodix,resume-in-workqueue = <0>;
++		goodix,int-sync = <1>;
++		goodix,swap-x2y = <0>;
++		goodix,auto-update-cfg = <0>;
++		goodix,power-off-sleep = <0>;
++		goodix,pen-suppress-finger = <0>;
++		irq-flags = <2>; /* 1 rising, 2 falling */
++		pinctrl-names = "default", "int-output-high", "int-output-low", "int-input";
++		pinctrl-0 = <&touchscreen_default>;
++		pinctrl-1 = <&touchscreen_int_out_high>;
++		pinctrl-2 = <&touchscreen_int_out_low>;
++		pinctrl-3 = <&touchscreen_int_input>;
++		goodix,cfg-group0 = [
++			42 20 03 E0 01 0A 0D 00
++			01 08 28 05 50 32 03 05
++			00 00 00 00 00 00 00 00
++			00 00 00 87 28 09 17 15
++			31 0D 00 00 00 9A 03 1C
++			00 00 00 00 00 03 64 32
++			00 00 00 0F 23 94 C5 02
++			07 00 00 04 A3 10 00 8B
++			13 00 7A 16 00 66 1B 00
++			58 20 00 58 00 00 00 00
++			00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00
++			02 04 06 08 0A 0C 0E 10
++			12 FF FF FF FF FF FF FF
++			FF FF FF FF FF FF FF FF
++			FF FF FF FF FF FF 00 02
++			04 06 08 0A 0C 1D 1E 1F
++			20 21 22 24 26 FF FF FF
++			FF FF FF FF FF FF FF FF
++			FF FF FF FF FF FF FF FF
++			FF FF FF FF FF FF FF FF
++			4A 01];
++	};
++};
++
++&pinctrl {
++
++	touchscreen_pins:touchscreen-pins {
++		touchscreen_int_out_high:touchscreen-int-out-high {
++			ingenic,pinmux = <&gpb 17 17>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCHILVL>;
++		};
++		touchscreen_int_out_low:touchscreen-int-out-low {
++			ingenic,pinmux = <&gpb 17 17>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCLOLVL>;
++		};
++		touchscreen_int_input:touchscreen-int-input {
++			ingenic,pinmux = <&gpb 17 17>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT_FE>;
++		};
++		touchscreen_default:touchscreen-default {
++			ingenic,pinmux = <&gpb 17 17>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT>;
++		};
++	};
++};
+diff --git a/module_drivers/dts/halley6_lcd/RD_X1600_HALLEY6_RGB_SLCD_1V0.dtsi b/module_drivers/dts/halley6_lcd/RD_X1600_HALLEY6_RGB_SLCD_1V0.dtsi
+new file mode 100644
+index 000000000..1eadb47cf
+--- /dev/null
++++ b/module_drivers/dts/halley6_lcd/RD_X1600_HALLEY6_RGB_SLCD_1V0.dtsi
+@@ -0,0 +1,64 @@
++/ {
++
++	display-dbi {
++		compatible = "simple-bus";
++		#interrupt-cells = <1>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++		panel_fw035 {
++			compatible = "ingenic,fw035";
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&smart_lcd_pa_8bit>;
++/*			ingenic,pwm-gpio = <&gpc 0 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;*/
++			ingenic,cs-gpio = <&gpa 23 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,rd-gpio = <&gpa 16 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			ingenic,vdd-en-gpio = <&gpa 31 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			ingenic,rst-gpio = <&gpb 13 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			port {
++				panel_fw035_ep: endpoint {
++					remote-endpoint = <&dpu_out_ep>;
++				};
++			};
++		};
++	};
++	backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwm 0 1000000>;
++	    brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
++	    default-brightness-level = <4>;
++	};
++};
++
++&dpu {
++	status = "okay";
++	port {
++		dpu_out_ep: endpoint {
++		remote-endpoint = <&panel_fw035_ep>;
++	    };
++	};
++};
++
++&i2c1 {
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	status = "okay";
++	pinctrl-0 = <&i2c1_pb_f2>;
++
++	goodix@0x38{
++		compatible = "goodix,ft6236"; /* do not modify */
++		reg = <0x38>; /* do not modify */
++		interrupt-parent = <&gpa>; /* INT pin */
++		interrupts = <9>;
++		reset-gpios = <&gpb 14 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>; /* RST pin */
++		irq-gpios = <&gpb 17 IRQ_TYPE_EDGE_FALLING INGENIC_GPIO_NOBIAS>; /* INT pin */
++		touchscreen-max-x = <480>;
++		touchscreen-max-y = <800>;
++		touchscreen-invert-x = <0>;
++		touchscreen-invert-y = <0>;
++		ft6236,swap-x2y = <0>;
++		irq-flags = <2>; /* 1 rising, 2 falling */
++	};
++};
++
+diff --git a/module_drivers/dts/halley6_lcd/RD_X1600_HALLEY6_RGB_SPI_LCD_1V0.dtsi b/module_drivers/dts/halley6_lcd/RD_X1600_HALLEY6_RGB_SPI_LCD_1V0.dtsi
+new file mode 100644
+index 000000000..6219fe42b
+--- /dev/null
++++ b/module_drivers/dts/halley6_lcd/RD_X1600_HALLEY6_RGB_SPI_LCD_1V0.dtsi
+@@ -0,0 +1,110 @@
++/ {
++	display-dbi {
++		compatible = "simple-bus";
++		#interrupt-cells = <1>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++		panel_kd050wvfpa029 {
++			compatible = "ingenic,fw040";
++			status = "okay";
++			pinctrl-names = "default", "i2c-func";
++			pinctrl-0 = <&tft_lcd_pa_rgb888>;
++			pinctrl-1 = <&i2c1_pb_f2>;
++/*			ingenic,lcd-pwm-gpio = <&gpc 0 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;*/
++			ingenic,vdd-en-gpio = <&gpa 31 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			ingenic,rst-gpio = <&gpb 13 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,lcd-sdo-gpio = <&gpb 16 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,lcd-sck-gpio = <&gpb 15 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,lcd-cs-gpio = <&gpb 14 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			port {
++				panel_fw040_ep: endpoint {
++					remote-endpoint = <&dpu_out_ep>;
++				};
++			};
++		};
++	};
++	backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwm 0 1000000>;
++	    brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
++	    default-brightness-level = <4>;
++	};
++};
++&dpu {
++	status = "okay";
++	port {
++		dpu_out_ep: endpoint {
++		remote-endpoint = <&panel_fw040_ep>;
++	    };
++	};
++};
++
++&i2c1 {
++	clock-frequency = <400000>;
++	/* pinctrl-names = "default"; */
++	status = "okay";
++	/* pinctrl-0 = <&i2c1_pb_f2>; */
++
++	goodix@0x14{
++		compatible = "goodix,gt9xx"; /* do not modify */
++		reg = <0x14>; /* do not modify */
++		interrupt-parent = <&gpa>; /* INT pin */
++		interrupts = <9>;
++		reset-gpios = <&gpb 14 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>; /* RST pin */
++		irq-gpios = <&gpb 17 IRQ_TYPE_EDGE_FALLING INGENIC_GPIO_NOBIAS>; /* INT pin */
++		goodix,driver-send-cfg = <1>;
++		touchscreen-size-x = <480>;
++		touchscreen-size-y = <800>;
++		goodix,slide-wakeup = <0>;
++		goodix,type-a-report = <0>;
++		goodix,resume-in-workqueue = <0>;
++		goodix,int-sync = <1>;
++		goodix,swap-x2y = <0>;
++		goodix,auto-update-cfg = <0>;
++		goodix,power-off-sleep = <0>;
++		goodix,pen-suppress-finger = <0>;
++		irq-flags = <2>; /* 1 rising, 2 falling */
++		pinctrl-names = "default", "int-output-high", "int-output-low", "int-input";
++		pinctrl-0 = <&touchscreen_default>;
++		pinctrl-1 = <&touchscreen_int_out_high>;
++		pinctrl-2 = <&touchscreen_int_out_low>;
++		pinctrl-3 = <&touchscreen_int_input>;
++		goodix,cfg-group0 = [
++			53 E0 01 20 03 05 05 20 02 2A 19 0F 5A 3C 03
++			05 00 00 00 00 00 00 06 16 18 1E 14 86 26 07
++			7F 81 7C 06 00 00 00 00 02 1D 00 01 00 00 00
++			00 00 00 00 00 00 5A B4 94 C5 03 08 00 00 04
++			8B 60 00 85 6F 00 80 7F 00 7C 92 00 79 A8 00
++			79 00 00 00 00 00 00 00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 0E 0C 0A 08 06 04 02 FF
++			FF FF FF FF FF FF 00 00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 02 04 06 08 0A 22 21
++			20 1F 1E 1D FF FF FF FF FF FF FF FF FF FF FF
++			FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00
++			00 00 00 00 D8 01];
++	};
++};
++
++&pinctrl {
++
++	touchscreen_pins:touchscreen-pins {
++		touchscreen_int_out_high:touchscreen-int-out-high {
++			ingenic,pinmux = <&gpb 17 17>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCHILVL>;
++		};
++		touchscreen_int_out_low:touchscreen-int-out-low {
++			ingenic,pinmux = <&gpb 17 17>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCLOLVL>;
++		};
++		touchscreen_int_input:touchscreen-int-input {
++			ingenic,pinmux = <&gpb 17 17>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT_FE>;
++		};
++		touchscreen_default:touchscreen-default {
++			ingenic,pinmux = <&gpb 17 17>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT>;
++		};
++	};
++};
+diff --git a/module_drivers/dts/halley6_v10.dts b/module_drivers/dts/halley6_v10.dts
+new file mode 100644
+index 000000000..4787614a2
+--- /dev/null
++++ b/module_drivers/dts/halley6_v10.dts
+@@ -0,0 +1,396 @@
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include "x1600.dtsi"
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <generated/autoconf.h>
++
++#ifdef CONFIG_RD_X1600_HALLEY6_MIPI_CAMERA
++#include "halley6_cameras/RD_X1600_HALLEY6_MIPI_CAMERA.dtsi"
++#endif
++
++#ifdef CONFIG_RD_X1600_HALLEY6_DVP_CAMERA
++#include "halley6_cameras/RD_X1600_HALLEY6_DVP_CAMERA.dtsi"
++#endif
++
++#ifdef CONFIG_STAGE_FW040
++#include "halley6_lcd/RD_X1600_HALLEY6_RGB_SPI_LCD_1V0.dtsi"
++#endif
++
++#ifdef CONFIG_STAGE_FW035
++#include "halley6_lcd/RD_X1600_HALLEY6_RGB_SLCD_1V0.dtsi"
++#endif
++
++#ifdef CONFIG_STAGE_KD050WVFPA029
++#include "halley6_lcd/RD_X1600_HALLEY6_RGB_LCD_1V0.dtsi"
++#endif
++
++
++
++/ {
++	compatible = "ingenic,halley6_v10", "ingenic,halley6_v10";
++
++	/*chosen {
++		bootargs = "console=ttyS1,115200 mem=128M@0x0ip=off init=/linuxrc ubi.mtd=3 root=ubi0:rootfs ubi.mtd=4 rootfstype=ubifs rw";
++	};*/
++
++
++	reserved-memory {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges =<>;
++
++		reserved_memory: reserved_mem@0x2000000{
++		      compatible = "shared-dma-pool";
++		      reg = <0x02000000 0x2000000>;
++		};
++	};
++
++};
++
++&uart0 {
++	status = "okay";
++	/* dma-mode; */
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pb>;
++};
++
++&uart1 {
++	status = "disable";
++	/* dma-mode; */
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pb>;
++};
++
++&uart2 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pb>;
++};
++
++&uart3 {
++	status = "disable";
++};
++
++&cpufreq {
++	status = "okay";
++	operating-points = <
++		/*KHZ uV */
++		1200000	900000
++		750000	900000
++		600000	900000
++		500000	900000
++		400000	900000
++		375000	900000
++		300000	900000
++		200000	900000
++			>;
++
++};
++
++&pdma {
++	status = "okay";
++};
++
++&tcu {
++	status = "disable ";
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm_tcu_trig_pa>;
++};
++
++&can0 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&can0_pd>;
++	ingenic,clk-freq = <12000000>;
++};
++
++&can1 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&can1_pd>;
++	ingenic,clk-freq = <12000000>;
++};
++
++&cim {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&msc1 {
++	status = "okay";
++	pinctrl-names ="default", "enable", "disable";
++	pinctrl-0 = <&msc1_4bit>;
++	pinctrl-1 = <&rtc32k_enable>;
++	pinctrl-2 = <&rtc32k_disable>;
++
++	cap-sd-highspeed;
++	max-frequency = <50000000>;
++	bus-width = <4>;
++	voltage-ranges = <1800 3300>;
++	non-removable;
++
++	ingenic,sdio_clk = <1>;
++	keep-power-in-suspend;
++
++	/* special property */
++	ingenic,wp-gpios = <0>;
++	ingenic,cd-gpios = <0>;
++	ingenic,rst-gpios = <0>;
++	ingenic,removal-manual; /*removal-dontcare, removal-nonremovable, removal-removable, removal-manual*/
++	bcmdhd_wlan: bcmdhd_wlan {
++		 compatible = "android,bcmdhd_wlan";
++		 ingenic,sdio-irq = <&gpb 3 IRQ_TYPE_LEVEL_HIGH INGENIC_GPIO_NOBIAS>;
++		 ingenic,sdio-reset = <&gpb 4 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++};
++
++&mac0 {
++	pinctrl-names = "default", "reset";
++	pinctrl-0 = <&mac0_rmii_p0_normal>, <&mac0_rmii_p1_normal>;
++	pinctrl-1 = <&mac0_rmii_p0_rst>, <&mac0_rmii_p1_normal>;
++	status = "okay";
++	ingenic,pwr-gpio = <&gpb 30 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	ingenic,rst-gpio = <&gpb 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,rst-ms = <10>;
++	ingenic,mac-mode = <RMII>;
++	ingenic,mode-reg = <0xb0000054>;
++	ingenic,phy-clk-freq = <50000000>;
++};
++
++&sfc {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&sfc_pc>;
++	ingenic,sfc-init-frequency = <200000000>;
++	ingenic,sfc-max-frequency = <320000000>;
++	ingenic,use_ofpart_info  = /bits/ 8 <0>;
++	ingenic,spiflash_param_offset = <0>;
++
++	norflash@0 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nor flash partition */
++			uboot@0 {
++				label = "uboot";
++				reg = <0x0000000 0x40000>;
++				/*read-only;*/
++			};
++
++			kernel@40000 {
++				label = "kernel";
++				reg = <0x40000 0x300000>;
++			};
++
++			rootfs@360000 {
++				label = "rootfs";
++				reg = <0x360000 0xca0000>;
++			};
++		};
++	};
++
++	nandflash@1 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nand flash partition */
++			partition@0 {
++				label = "uboot";
++				reg = <0x0000000 0x100000>;
++				/*read-only;*/
++			};
++
++			partition@100000 {
++				label = "kernel";
++				reg = <0x100000 0x800000>;
++			};
++
++			partition@900000 {
++				label = "rootfs";
++				reg = <0x900000 0xf700000>;
++			};
++		};
++	};
++
++};
++
++&spi0 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pb>;
++	spi-max-frequency = <54000000>;
++	num-cs = <2>;
++	/* cs-gpios = <0>, <0>; */
++	/* cs-gpios = <&gpb 17 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>, <&gpb 16 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>; */
++	ingenic,chnl = <0>;
++	ingenic,allow_cs_same = <1>;
++	ingenic,bus_num = <0>;
++	ingenic,has_dma_support = <0>;
++	ingenic,spi-src-clk = <1>;/*0.ext; 1.ssi*/
++
++	/* Add SPI interface device */
++	spidev: spidev@0 {
++		compatible = "rohm,dh2228fv";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++	};
++};
++
++&spi_slv0 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi_slv_pa>;
++	ingenic,has_dma_support = <1>;
++};
++
++&dtrng {
++	status = "okay";
++};
++
++&pwm {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm0_pc>;
++};
++
++&otg {
++	g-use-dma;
++	dr_mode = "otg"; // host,peripheral,otg
++	device-using-dma = <1>;
++	status = "okay";
++};
++
++&otg_phy {
++	status = "okay";
++	ingenic,vbus-dete-gpio = <&gpc 24 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++};
++
++&aic {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&aic_pb>;
++};
++
++&efuse {
++	status = "disable";
++};
++
++
++/ {
++
++	extclk: extclk {
++		clock-frequency = <24000000>;
++	};
++
++	gpio_keys: gpio_keys {
++		   compatible = "gpio-keys";
++
++		   wakeup {
++			   label = "WAKEUP";
++			   linux,code = <KEY_WAKEUP>;
++			   gpios = <&gpc 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			   gpio-key,wakeup;
++		   };
++
++		   bootsel0 {
++			   label = "bootsel0";
++			   linux,code = <KEY_HOME>;
++			   gpios = <&gpc 27 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		   };
++
++		   bootsel1 {
++			   label = "bootsel1";
++			   linux,code = <KEY_BACK>;
++			   gpios = <&gpc 28 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		   };
++	   };
++
++	/*
++	 * gpb 2 bt wakeup host
++	 */
++	bt_power {
++		compatible = "ingenic,bt_power";
++		ingenic,reg-on-gpio = <&gpb 5 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,wake-gpio = <&gpb 2 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++
++	dump_pcm_codec:dump_pcm_codec{
++		compatible = "ingenic,pcm-dump-codec";
++		status = "disable";
++	};
++
++	sound_halley6_ecdc {
++		status = "disable";
++		compatible = "ingenic,x1600-sound";
++		ingenic,model = "halley6";
++		ingenic,dai-link = "i2s-ecodec", "i2s-tloop";
++		ingenic,stream = "i2s-ecodec", "i2s-tloop";
++		ingenic,cpu-dai = <&i2s>, <&i2s_tloop>;
++		ingenic,platform = <&aic>, <&i2s_tloop>;
++		ingenic,codec = <&dump_pcm_codec>, <&dump_pcm_codec>;
++		ingenic,codec-dai = "pcm-dump", "pcm-dump";
++		ingenic,en3v3-gpios = <&gpb 30 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	};
++
++#if 0
++	backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwm 2 100000>; /* arg1: pwm channel id [0~15]. arg2: period in ns. */
++		brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
++		default-brightness-level = <5>;
++	};
++#endif
++
++	spi_gpio {
++		status = "disable";
++	};
++
++#ifdef CONFIG_LINUX_PMEM
++	linux_pmem {
++		status = "okay";
++		compatible = "linux_pmem";
++		linux_pmem,name = "pmem";
++		linux_pmem,no_allocator = <0>;
++		linux_pmem,cached       = <1>;
++		linux_pmem,start        = <0>;
++		linux_pmem,size         = CONFIG_PMEM_RESERVE_SIZE;
++    };
++#endif
++};
++
++&gpa {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <26>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpb {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpc {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpd {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
+diff --git a/module_drivers/dts/halley6_v20.dts b/module_drivers/dts/halley6_v20.dts
+new file mode 100644
+index 000000000..e82ce9284
+--- /dev/null
++++ b/module_drivers/dts/halley6_v20.dts
+@@ -0,0 +1,396 @@
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include "x1600.dtsi"
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <generated/autoconf.h>
++
++#ifdef CONFIG_RD_X1600_HALLEY6_MIPI_CAMERA
++#include "halley6_cameras/RD_X1600_HALLEY6_MIPI_CAMERA.dtsi"
++#endif
++
++#ifdef CONFIG_RD_X1600_HALLEY6_DVP_CAMERA
++#include "halley6_cameras/RD_X1600_HALLEY6_DVP_CAMERA.dtsi"
++#endif
++
++#ifdef CONFIG_STAGE_FW040
++#include "halley6_lcd/RD_X1600_HALLEY6_RGB_SPI_LCD_1V0.dtsi"
++#endif
++
++#ifdef CONFIG_STAGE_FW035
++#include "halley6_lcd/RD_X1600_HALLEY6_RGB_SLCD_1V0.dtsi"
++#endif
++
++#ifdef CONFIG_STAGE_KD050WVFPA029
++#include "halley6_lcd/RD_X1600_HALLEY6_RGB_LCD_1V0.dtsi"
++#endif
++
++
++
++/ {
++	compatible = "ingenic,halley6_v20", "ingenic,halley6_v10";
++
++	/*chosen {
++		bootargs = "console=ttyS1,115200 mem=128M@0x0ip=off init=/linuxrc ubi.mtd=3 root=ubi0:rootfs ubi.mtd=4 rootfstype=ubifs rw";
++	};*/
++
++
++	reserved-memory {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges =<>;
++
++		reserved_memory: reserved_mem@0x2000000{
++		      compatible = "shared-dma-pool";
++		      reg = <0x02000000 0x2000000>;
++		};
++	};
++
++};
++
++&uart0 {
++	status = "disable";
++	/* dma-mode; */
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pb>;
++};
++
++&uart1 {
++	status = "disable";
++	/* dma-mode; */
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pb>;
++};
++
++&uart2 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pb>;
++};
++
++&uart3 {
++	status = "disable";
++};
++
++&cpufreq {
++	status = "okay";
++	operating-points = <
++		/*KHZ uV */
++		1200000	900000
++		750000	900000
++		600000	900000
++		500000	900000
++		400000	900000
++		375000	900000
++		300000	900000
++		200000	900000
++			>;
++
++};
++
++&pdma {
++	status = "okay";
++};
++
++&tcu {
++	status = "disable ";
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm_tcu_trig_pa>;
++};
++
++&can0 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&can0_pd>;
++	ingenic,clk-freq = <12000000>;
++};
++
++&can1 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&can1_pd>;
++	ingenic,clk-freq = <12000000>;
++};
++
++&cim {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&msc1 {
++	status = "okay";
++	pinctrl-names ="default", "enable", "disable";
++	pinctrl-0 = <&msc1_4bit>;
++	pinctrl-1 = <&rtc32k_enable>;
++	pinctrl-2 = <&rtc32k_disable>;
++
++	cap-sd-highspeed;
++	max-frequency = <50000000>;
++	bus-width = <4>;
++	voltage-ranges = <1800 3300>;
++	non-removable;
++
++	ingenic,sdio_clk = <1>;
++	keep-power-in-suspend;
++
++	/* special property */
++	ingenic,wp-gpios = <0>;
++	ingenic,cd-gpios = <0>;
++	ingenic,rst-gpios = <0>;
++	ingenic,removal-manual; /*removal-dontcare, removal-nonremovable, removal-removable, removal-manual*/
++	bcmdhd_wlan: bcmdhd_wlan {
++		 compatible = "android,bcmdhd_wlan";
++		 ingenic,sdio-irq = <&gpb 3 IRQ_TYPE_LEVEL_HIGH INGENIC_GPIO_NOBIAS>;
++		 ingenic,sdio-reset = <&gpb 4 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++};
++
++&mac0 {
++	pinctrl-names = "default", "reset";
++	pinctrl-0 = <&mac0_rmii_p0_normal>, <&mac0_rmii_p1_normal>;
++	pinctrl-1 = <&mac0_rmii_p0_rst>, <&mac0_rmii_p1_normal>;
++	status = "okay";
++	ingenic,pwr-gpio = <&gpb 30 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	ingenic,rst-gpio = <&gpb 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,rst-ms = <10>;
++	ingenic,mac-mode = <RMII>;
++	ingenic,mode-reg = <0xb0000054>;
++	ingenic,phy-clk-freq = <50000000>;
++};
++
++&sfc {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&sfc_pc>;
++	ingenic,sfc-init-frequency = <200000000>;
++	ingenic,sfc-max-frequency = <320000000>;
++	ingenic,use_ofpart_info  = /bits/ 8 <0>;
++	ingenic,spiflash_param_offset = <0>;
++
++	norflash@0 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nor flash partition */
++			uboot@0 {
++				label = "uboot";
++				reg = <0x0000000 0x40000>;
++				/*read-only;*/
++			};
++
++			kernel@40000 {
++				label = "kernel";
++				reg = <0x40000 0x300000>;
++			};
++
++			rootfs@360000 {
++				label = "rootfs";
++				reg = <0x360000 0xca0000>;
++			};
++		};
++	};
++
++	nandflash@1 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nand flash partition */
++			partition@0 {
++				label = "uboot";
++				reg = <0x0000000 0x100000>;
++				/*read-only;*/
++			};
++
++			partition@100000 {
++				label = "kernel";
++				reg = <0x100000 0x800000>;
++			};
++
++			partition@900000 {
++				label = "rootfs";
++				reg = <0x900000 0xf700000>;
++			};
++		};
++	};
++
++};
++
++&spi0 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pb>;
++	spi-max-frequency = <54000000>;
++	num-cs = <2>;
++	/* cs-gpios = <0>, <0>; */
++	/* cs-gpios = <&gpb 17 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>, <&gpb 16 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>; */
++	ingenic,chnl = <0>;
++	ingenic,allow_cs_same = <1>;
++	ingenic,bus_num = <0>;
++	ingenic,has_dma_support = <0>;
++	ingenic,spi-src-clk = <1>;/*0.ext; 1.ssi*/
++
++	/* Add SPI interface device */
++	spidev: spidev@0 {
++		compatible = "rohm,dh2228fv";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++	};
++};
++
++&spi_slv0 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi_slv_pa>;
++	ingenic,has_dma_support = <1>;
++};
++
++&dtrng {
++	status = "okay";
++};
++
++&pwm {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm0_pc>;
++};
++
++&otg {
++	g-use-dma;
++	dr_mode = "otg"; // host,peripheral,otg
++	device-using-dma = <1>;
++	status = "okay";
++};
++
++&otg_phy {
++	status = "okay";
++	ingenic,vbus-dete-gpio = <&gpc 24 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++};
++
++&aic {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&aic_pb>;
++};
++
++&efuse {
++	status = "disable";
++};
++
++
++/ {
++
++	extclk: extclk {
++		clock-frequency = <24000000>;
++	};
++
++	gpio_keys: gpio_keys {
++		   compatible = "gpio-keys";
++
++		   wakeup {
++			   label = "WAKEUP";
++			   linux,code = <KEY_WAKEUP>;
++			   gpios = <&gpc 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			   gpio-key,wakeup;
++		   };
++
++		   bootsel0 {
++			   label = "bootsel0";
++			   linux,code = <KEY_HOME>;
++			   gpios = <&gpc 27 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		   };
++
++		   bootsel1 {
++			   label = "bootsel1";
++			   linux,code = <KEY_BACK>;
++			   gpios = <&gpc 28 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		   };
++	   };
++
++	/*
++	 * gpb 2 bt wakeup host
++	 */
++	bt_power {
++		compatible = "ingenic,bt_power";
++		ingenic,reg-on-gpio = <&gpb 5 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,wake-gpio = <&gpb 2 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++
++	dump_pcm_codec:dump_pcm_codec{
++		compatible = "ingenic,pcm-dump-codec";
++		status = "okay";
++	};
++
++	sound_halley6_ecdc {
++		status = "okay";
++		compatible = "ingenic,x1600-sound";
++		ingenic,model = "halley6";
++		ingenic,dai-link = "i2s-ecodec", "i2s-tloop";
++		ingenic,stream = "i2s-ecodec", "i2s-tloop";
++		ingenic,cpu-dai = <&i2s>, <&i2s_tloop>;
++		ingenic,platform = <&aic>, <&i2s_tloop>;
++		ingenic,codec = <&dump_pcm_codec>, <&dump_pcm_codec>;
++		ingenic,codec-dai = "pcm-dump", "pcm-dump";
++		ingenic,en3v3-gpios = <&gpb 31 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	};
++
++#if 0
++	backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwm 2 100000>; /* arg1: pwm channel id [0~15]. arg2: period in ns. */
++		brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
++		default-brightness-level = <5>;
++	};
++#endif
++
++	spi_gpio {
++		status = "disable";
++	};
++
++#ifdef CONFIG_LINUX_PMEM
++	linux_pmem {
++		status = "okay";
++		compatible = "linux_pmem";
++		linux_pmem,name = "pmem";
++		linux_pmem,no_allocator = <0>;
++		linux_pmem,cached       = <1>;
++		linux_pmem,start        = <0>;
++		linux_pmem,size         = CONFIG_PMEM_RESERVE_SIZE;
++    };
++#endif
++};
++
++&gpa {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <26>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpb {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpc {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpd {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
+diff --git a/module_drivers/dts/hippo_cameras/RD_X2000_HALLEY5_CAMERA_3V2.dtsi b/module_drivers/dts/hippo_cameras/RD_X2000_HALLEY5_CAMERA_3V2.dtsi
+new file mode 100644
+index 000000000..c85ee7729
+--- /dev/null
++++ b/module_drivers/dts/hippo_cameras/RD_X2000_HALLEY5_CAMERA_3V2.dtsi
+@@ -0,0 +1,34 @@
++&i2c3 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa>;
++
++	ov2735_0:ov4689@0x21 {
++		status = "ok";
++		compatible = "ovti,ov4689";
++		reg = <0x21>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim1_vic_mclk_pc>;
++
++		ingenic,mclk = <1>;
++		ingenic,rst-gpio = <&gpa 11 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutp-gpio = <&gpa 19 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutn-gpio = <&gpa 20 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov4689_ep0:endpoint {
++				remote-endpoint = <&isp0_ep>;
++			};
++		};
++	};
++};
++
++
++&isp0_ep {
++	remote-endpoint = <&ov4689_ep0>;
++	data-lanes = <0 1>;
++	clk-lanes = <2>;
++};
++
+diff --git a/module_drivers/dts/hippo_cameras/RD_X2000_HALLEY5_CAMERA_4V3.dtsi b/module_drivers/dts/hippo_cameras/RD_X2000_HALLEY5_CAMERA_4V3.dtsi
+new file mode 100644
+index 000000000..0d044c283
+--- /dev/null
++++ b/module_drivers/dts/hippo_cameras/RD_X2000_HALLEY5_CAMERA_4V3.dtsi
+@@ -0,0 +1,58 @@
++&i2c3 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa>;
++
++	ov2735_0:ov2735@0x3d {
++		status = "ok";
++		compatible = "ovti,ov2735a";
++		reg = <0x3d>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim1_vic_mclk_pc>;
++
++		ingenic,mclk = <1>;
++		ingenic,rst-gpio = <&gpa 10 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutp-gpio = <&gpa 17 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutn-gpio = <&gpa 18 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov2735_ep0:endpoint {
++				remote-endpoint = <&isp0_ep>;
++			};
++		};
++	};
++
++	ov2735_1:ov2735@0x3c {
++		status = "ok";
++		compatible = "ovti,ov2735a";
++		reg = <0x3c>;
++		pinctrl-names = "default";
++
++		ingenic,mclk = <1>;
++		ingenic,rst-gpio = <&gpa 11 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutp-gpio = <&gpa 19 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutn-gpio = <&gpa 20 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov2735_ep1:endpoint {
++				remote-endpoint = <&isp1_ep>;
++			};
++		};
++	};
++};
++
++
++&isp0_ep {
++	remote-endpoint = <&ov2735_ep0>;
++	data-lanes = <0 1>;
++	clk-lanes = <2>;
++};
++
++&isp1_ep {
++	remote-endpoint = <&ov2735_ep1>;
++	data-lanes = <3 4>;
++	clk-lanes = <5>;
++};
++
+diff --git a/module_drivers/dts/hippo_cameras/RD_X2500_HIPPO_CAMERA_1V0.dtsi b/module_drivers/dts/hippo_cameras/RD_X2500_HIPPO_CAMERA_1V0.dtsi
+new file mode 100644
+index 000000000..ab59ee3c9
+--- /dev/null
++++ b/module_drivers/dts/hippo_cameras/RD_X2500_HIPPO_CAMERA_1V0.dtsi
+@@ -0,0 +1,105 @@
++&i2c3 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa>;
++
++	sc230ai_0:sc230ai@0x30 {
++		status = "ok";
++		compatible = "smartsens,sc230ai";
++		reg = <0x30>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim0_vic_mclk_pc>;
++
++		ingenic,mclk = <0>;
++		ingenic,pwdn-gpio = <&gpa 18 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,xshutdn-gpio = <&gpa 17 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,efsync-gpio = <&gpa 19 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++
++		port {
++			sc230ai_ep0:endpoint {
++				remote-endpoint = <&isp0_ep>;
++			};
++		};
++	};
++
++	sc230ai_1:sc230ai@0x32 {
++		status = "ok";
++		compatible = "smartsens,sc230ai";
++		reg = <0x32>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim2_vic_mclk_pc>;
++
++		ingenic,mclk = <2>;
++		ingenic,pwdn-gpio = <&gpa 8 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,xshutdn-gpio = <&gpa 11 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,efsync-gpio = <&gpa 20 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++
++		port {
++			sc230ai_ep1:endpoint {
++				remote-endpoint = <&isp1_ep>;
++			};
++		};
++	};
++};
++
++
++&i2c0 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0_pa>;
++
++	gc2155: gc2155@0x3c {
++		status = "ok";
++		compatible = "GalaxyCore,gc2155";
++		reg = <0x3c>;
++		pinctrl-names = "default", "default";
++
++		pinctrl-0 = <&cim1_vic_mclk_pc>;
++		pinctrl-1 = <&vic_pa_low_8bit>;
++
++		ingenic,mclk = <1>;
++
++		ingenic,pwdn-gpio = <&gpa 10 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,rst-gpio = <&gpa 9 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			gc2155_0: endpoint {
++				remote-endpoint = <&vic2_ep>;
++				bus-width = <8>;	/* Used data lines */
++				data-shift = <0>;	/* Lines 9:0 are used */
++				/* If hsync-active/vsync-active are missing,
++				   embedded BT.656 sync is used */
++				hsync-active = <1>;	/* Active high */
++				vsync-active = <0>;	/* Active high */
++				data-active = <1>;	/* Active high */
++				pclk-sample = <1>;	/* Rising */
++			};
++		};
++	};
++};
++
++&isp0_ep {
++	remote-endpoint = <&sc230ai_ep0>;
++	data-lanes = <0 1>;
++	clk-lanes = <2>;
++};
++
++&isp1_ep {
++	remote-endpoint = <&sc230ai_ep1>;
++	data-lanes = <3 4>;
++	clk-lanes = <5>;
++};
++
++&vic2_ep{
++	remote-endpoint = <&gc2155_0>;
++	bus-width = <8>;	/* Used data lines */
++	data-shift = <0>;	/* Lines 9:0 are used */
++	hsync-active = <1>;	/* Active high */
++	vsync-active = <0>;	/* Active low */
++	data-active = <1>;	/* Active high */
++	pclk-sample = <1>;	/* Rising */
++};
+diff --git a/module_drivers/dts/hippo_cameras/RD_X2500_HIPPO_CAMERA_1V1.dtsi b/module_drivers/dts/hippo_cameras/RD_X2500_HIPPO_CAMERA_1V1.dtsi
+new file mode 100644
+index 000000000..e64665ed0
+--- /dev/null
++++ b/module_drivers/dts/hippo_cameras/RD_X2500_HIPPO_CAMERA_1V1.dtsi
+@@ -0,0 +1,98 @@
++&i2c3 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa>;
++
++	sc230ai_0:sc230ai@0x30 {
++		status = "ok";
++		compatible = "smartsens,sc230ai";
++		reg = <0x30>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim1_vic_mclk_pc>;
++
++		ingenic,mclk = <1>;
++		ingenic,pwdn-gpio = <&gpa 18 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,xshutdn-gpio = <&gpa 17 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,efsync-gpio = <&gpa 19 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		/* ingenic,led-gpio = <&gpa 12 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>; */
++
++		port {
++			sc230ai_ep0:endpoint {
++				remote-endpoint = <&isp0_ep>;
++			};
++		};
++	};
++
++	sc230ai_1:sc230ai@0x32 {
++		status = "ok";
++		compatible = "smartsens,sc230ai";
++		reg = <0x32>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim0_vic_mclk_pc>;
++
++		ingenic,mclk = <0>;
++		ingenic,pwdn-gpio = <&gpa 8 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,xshutdn-gpio = <&gpa 11 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,efsync-gpio = <&gpa 20 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,led-gpio = <&gpa 13 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++
++		port {
++			sc230ai_ep1:endpoint {
++				remote-endpoint = <&isp1_ep>;
++			};
++		};
++	};
++
++	gc2155: gc2155@0x3c {
++		status = "ok";
++		compatible = "GalaxyCore,gc2155";
++		reg = <0x3c>;
++		pinctrl-names = "default", "default";
++
++		pinctrl-0 = <&cim2_vic_mclk_pc>;
++		pinctrl-1 = <&vic_pa_low_8bit>;
++
++		ingenic,mclk = <2>;
++
++		ingenic,pwdn-gpio = <&gpa 10 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,rst-gpio = <&gpa 9 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			gc2155_0: endpoint {
++				remote-endpoint = <&vic2_ep>;
++				bus-width = <8>;	/* Used data lines */
++				data-shift = <0>;	/* Lines 9:0 are used */
++				/* If hsync-active/vsync-active are missing,
++				   embedded BT.656 sync is used */
++				hsync-active = <1>;	/* Active high */
++				vsync-active = <0>;	/* Active high */
++				data-active = <1>;	/* Active high */
++				pclk-sample = <1>;	/* Rising */
++			};
++		};
++	};
++};
++
++&isp0_ep {
++	remote-endpoint = <&sc230ai_ep0>;
++	data-lanes = <0 1>;
++	clk-lanes = <2>;
++};
++
++&isp1_ep {
++	remote-endpoint = <&sc230ai_ep1>;
++	data-lanes = <3 4>;
++	clk-lanes = <5>;
++};
++
++&vic2_ep{
++	remote-endpoint = <&gc2155_0>;
++	bus-width = <8>;	/* Used data lines */
++	data-shift = <0>;	/* Lines 9:0 are used */
++	hsync-active = <1>;	/* Active high */
++	vsync-active = <0>;	/* Active low */
++	data-active = <1>;	/* Active high */
++	pclk-sample = <1>;	/* Rising */
++};
+diff --git a/module_drivers/dts/hippo_cameras/ov2735a.dtsi b/module_drivers/dts/hippo_cameras/ov2735a.dtsi
+new file mode 100644
+index 000000000..f9b8b2193
+--- /dev/null
++++ b/module_drivers/dts/hippo_cameras/ov2735a.dtsi
+@@ -0,0 +1,35 @@
++&i2c3 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa>;
++
++	ov2735_1:ov2735@0x3d {
++		status = "ok";
++		compatible = "ovti,ov2735a";
++		reg = <0x3d>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim1_vic_mclk_pc>;
++
++		ingenic,mclk = <1>;
++		ingenic,rst-gpio = <&gpa 11 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutp-gpio = <&gpa 17 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ingenic,ircutn-gpio = <&gpa 18 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov2735_ep0:endpoint {
++				remote-endpoint = <&isp0_ep>;
++			};
++		};
++	};
++
++};
++
++
++&isp0_ep {
++	remote-endpoint = <&ov2735_ep0>;
++	data-lanes = <0 1>;
++	clk-lanes = <2>;
++};
++
+diff --git a/module_drivers/dts/hippo_v10.dts b/module_drivers/dts/hippo_v10.dts
+new file mode 100644
+index 000000000..a318192f8
+--- /dev/null
++++ b/module_drivers/dts/hippo_v10.dts
+@@ -0,0 +1,421 @@
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include "x2500.dtsi"
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <generated/autoconf.h>
++
++
++#ifdef CONFIG_RD_X2000_HALLEY5_CAMERA_3V2
++#include "hippo_cameras/RD_X2000_HALLEY5_CAMERA_3V2.dtsi"
++#elif CONFIG_RD_X2000_HALLEY5_CAMERA_4V3
++#include "hippo_cameras/RD_X2000_HALLEY5_CAMERA_4V3.dtsi"
++#elif CONFIG_RD_X2500_HIPPO_CAMERA_1V0
++#include "hippo_cameras/RD_X2500_HIPPO_CAMERA_1V0.dtsi"
++#elif CONFIG_RD_X2500_HIPPO_CAMERA_1V1
++#include "hippo_cameras/RD_X2500_HIPPO_CAMERA_1V1.dtsi"
++#endif
++
++/ {
++	compatible = "ingenic,hippo", "ingenic,x2500";
++	reserved-memory {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges =<>;
++
++		reserved_memory: reserved_mem@0x9a00000{
++		      compatible = "shared-dma-pool";
++		      reg = <0x09a00000 0x3600000>;
++		};
++	};
++};
++
++&uart0 {
++	status = "okay";
++	pinctrl-names = "default", "default";
++	pinctrl-0 = <&uart0_pc1>;
++	pinctrl-1 = <&uart0_pc1_1>;
++};
++
++&uart1 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pb>;
++};
++
++&uart2 {
++	status = "disable";
++};
++
++&i2c0 {
++	pinctrl-0 = <&i2c0_pa>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&pinctrl {
++	touchscreen_pins:touchscreen-pins {
++		touchscreen_int_out_high:touchscreen-int-out-high {
++			ingenic,pinmux = <&gpc 6 6>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCHILVL>;
++		};
++		touchscreen_int_out_low:touchscreen-int-out-low {
++			ingenic,pinmux = <&gpc 6 6>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCLOLVL>;
++		};
++		touchscreen_int_input:touchscreen-int-input {
++			ingenic,pinmux = <&gpc 6 6>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT_FE>;
++		};
++		touchscreen_default:touchscreen-default {
++			ingenic,pinmux = <&gpc 6 6>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT>;
++		};
++	};
++};
++
++&i2c1 {
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	status = "okay";
++	pinctrl-0 = <&i2c1_pd>;
++
++	goodix@14{
++		compatible = "goodix,gt9xx"; /* do not modify */
++		reg = <0x14>; /* do not modify */
++		reset-gpios = <&gpc 7 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>; /* RST pin */
++		irq-gpios = <&gpc 6 IRQ_TYPE_EDGE_FALLING INGENIC_GPIO_NOBIAS>; /* INT pin */
++		goodix,driver-send-cfg = <1>;
++		touchscreen-size-x = <1280>;
++		touchscreen-size-y = <720>;
++		goodix,slide-wakeup = <0>;
++		goodix,type-a-report = <0>;
++		goodix,resume-in-workqueue = <0>;
++		goodix,int-sync = <1>;
++		goodix,swap-x2y = <0>;
++		goodix,auto-update-cfg = <0>;
++		goodix,power-off-sleep = <0>;
++		goodix,pen-suppress-finger = <0>;
++		irq-flags = <2>; /* 1 rising, 2 falling */
++		pinctrl-names = "default", "int-output-high", "int-output-low", "int-input";
++		pinctrl-0 = <&touchscreen_default>;
++		pinctrl-1 = <&touchscreen_int_out_high>;
++		pinctrl-2 = <&touchscreen_int_out_low>;
++		pinctrl-3 = <&touchscreen_int_input>;
++		goodix,cfg-group0 = [
++			00 D0 02 00 05 0A 05 00 01 08 28
++			05 50 32 03 05 00 00 00 00 00 00
++			00 00 00 00 00 87 28 09 17 15 31
++			0D 00 00 02 9B 03 25 00 00 00 00
++			00 03 64 32 00 00 00 0F 36 94 C5
++			02 07 00 00 04 9B 11 00 7B 16 00
++			64 1C 00 50 25 00 42 2F 00 42 00
++			00 00 00 00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 00 00 00
++			00 00 12 10 0E 0C 0A 08 06 04 02
++			FF FF FF FF FF 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 00 00 26
++			24 22 21 20 1F 1E 1D 00 02 04 06
++			08 0A 0C FF FF FF FF FF FF FF FF
++			FF FF FF 00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 CF 01];
++	};
++};
++
++&i2c2 {
++	clock-frequency = <100000>;
++	pinctrl-0 = <&i2c2_pb>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	rtc_pcf8563:rtc_pcf8563@51{
++		compatible = "nxp,pcf8563";
++		reg = <0x51>;
++		status = "ok";
++	    };
++};
++
++&i2c3 {
++	pinctrl-0 = <&i2c3_pa>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&ispcam0 {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&ispcam1 {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&ipu {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&i2d {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&el150 {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&cpufreq {
++	status = "disable";
++	operating-points = <
++		/*KHZ uV */
++		1200000	900000
++		750000	900000
++		600000	900000
++		500000	900000
++		400000	900000
++		375000	900000
++		300000	900000
++		200000	900000
++			>;
++
++};
++
++&pwmz {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm3_pb>;
++};
++
++&pdma {
++	status = "okay";
++};
++
++&msc0 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&msc0_pb>;
++	cap-mmc-highspeed;
++	max-frequency = <50000000>;
++	bus-width = <4>;
++	voltage-ranges = <1800 3300>;
++	cd-gpios = <&gpb 20 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	/* special property */
++	ingenic,rst-gpios = <0>;
++	ingenic,pwr-gpios = <0>;
++};
++
++&msc1 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&msc1_pc>;
++	cap-mmc-highspeed;
++	max-frequency = <100000000>;
++	bus-width = <4>;
++	voltage-ranges = <1800 3300>;
++	non-removable;
++
++	ingenic,sdio_clk = <1>;
++	keep-power-in-suspend;
++
++	/* special property */
++	ingenic,wp-gpios = <0>;
++	ingenic,removal-manual; /*removal-dontcare, removal-nonremovable, removal-removable, removal-manual*/
++
++	bcmdhd_wlan: bcmdhd_wlan {
++		 compatible = "android,bcmdhd_wlan";
++		 ingenic,sdio-irq = <&gpc 23 IRQ_TYPE_LEVEL_HIGH INGENIC_GPIO_NOBIAS>;
++		 ingenic,sdio-reset = <&gpc 20 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++};
++
++&mac0 {
++	pinctrl-names = "default", "reset";
++	pinctrl-0 = <&mac0_rmii_p0_normal>, <&mac0_rmii_p1_normal>;
++	pinctrl-1 = <&mac0_rmii_p0_rst>, <&mac0_rmii_p1_normal>;
++	status = "okay";
++	ingenic,rst-gpio = <&gpb 21 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,rst-ms = <10>;
++	ingenic,mac-mode = <RMII>;
++	ingenic,mode-reg = <0xb00000e8>;
++	ingenic,phy-clk-freq = <50000000>;
++};
++
++&sfc {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&sfc_pa>;
++	ingenic,sfc-init-frequency = <20000000>;
++	ingenic,sfc-max-frequency = <320000000>;
++	ingenic,use_ofpart_info      = /bits/ 8 <0>;
++	ingenic,spiflash_param_offset = <0>;
++};
++
++&spi0 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pc>;
++
++	spi-max-frequency = <48000000>;
++	num-cs = <2>;
++	cs-gpios = <0>, <0>;
++	ingenic,chnl = <0>;
++	ingenic,allow_cs_same = <1>;
++	ingenic,bus_num = <0>;
++	ingenic,has_dma_support = <1>;
++	ingenic,spi-src-clk = <1>;/*0.ext; 1.ssi*/
++
++	/* Add SPI interface device */
++	spidev: spidev@0 {
++		compatible = "rohm,dh2228fv";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++	};
++};
++
++&dtrng {
++	status = "okay";
++};
++
++&otg {
++	g-use-dma;
++	dr_mode = "otg";
++	device-using-dma = <1>;
++	status = "okay";
++};
++
++&otg_phy {
++	dr_mode = "otg";
++	status = "okay";
++	ingenic,vbus-dete-gpio = <&gpc 28 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,drvvbus-gpio = <&gpb 27 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	status = "okay";
++};
++
++/ {
++
++	extclk: extclk {
++		   clock-frequency = <24000000>;
++	};
++
++	gpio_keys: gpio_keys {
++		   compatible = "gpio-keys";
++
++		   power {
++			   label = "Power";
++			   linux,code = <KEY_POWER>;
++			   gpios = <&gpa 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			   gpio-key,wakeup;
++		   };
++
++		   bootsel0 {
++			   label = "bootsel0";
++			   linux,code = <KEY_HOME>;
++			   gpios = <&gpc 0 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			   gpio-key,wakeup;
++		   };
++
++		   bootsel1 {
++			   label = "bootsel1";
++			   linux,code = <KEY_BACK>;
++			   gpios = <&gpc 1 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			   gpio-key,wakeup;
++		   };
++
++	   };
++
++	bt_power {
++		compatible = "ingenic,bt_power";
++		ingenic,reg-on-gpio = <&gpc 27 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,wake-gpio = <&gpc 18 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++};
++
++&soc_nna{
++	status="okay";
++};
++
++
++
++&dpu {
++	status = "okay";
++	ingenic,disable-rdma-fb = <1>;
++	ingenic,layer-exported = <1 1 0 0>;
++	ingenic,layer-frames   = <3 3 1 2>;
++	ingenic,layer-framesize = <720 1280>, <720 1280>, <720 1280>, <320 240>;   //Max framesize for each layer.
++	layer,color_mode	= <1 6 0 0>;					//src fmt
++	layer,src-size       	= <720 1280>, <720 1280>, <720 1280>, <240 200>;	//Layer src size should smaller than framesize
++	layer,target-size	= <720 1280>, <720 1280>, <720 1280>, <240 200>;	//Target Size should smaller than src_size.
++	layer,target-pos	= <0 0>, <0 0>, <0 0>, <100 980>;	//target pos , the start point of the target panel.
++	layer,enable		= <1 1 0 0>;					//layer enabled or disabled.
++	ingenic,logo-pan-layer	= <0>;						//on which layer should init logo pan on.
++	port {
++		dpu_out_ep: endpoint {
++			remote-endpoint = <&panel_kd050hdfia020_ep>;
++	    };
++	};
++};
++
++/ {
++	display-dpi {
++		compatible = "simple-bus";
++		#interrupt-cells = <1>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++		panel_kd050hdfia020 {
++			compatible = "ingenic,kd050hdfia020";
++			status = "okay";
++			pinctrl-names = "default";
++			ingenic,vdd-en-gpio = <&gpc 3 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,rst-gpio = <&gpc 2 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	/*		ingenic,lcd-pwm-gpio = <&gpb 31 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;*/
++			port {
++				panel_kd050hdfia020_ep: endpoint {
++					remote-endpoint = <&dpu_out_ep>;
++				};
++			};
++		};
++
++	};
++
++	backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwmz 3 10000>; /* arg1: pwm channel id [0~15]. arg2: period in ns. */
++		brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
++		default-brightness-level = <5>;
++		/*default brightness is 5, you can echo x > /sys/devices/platform/backlight/backlight/backlight/brightness to adjust backlight*/
++	};
++};
++
++
++/ {
++	dump_dmic_codec:dump_dmic_codec{
++		compatible = "ingenic,dmic-dump-codec";
++		status = "ok";
++	};
++	dump_pcm_codec:dump_pcm_codec{
++		compatible = "ingenic,pcm-dump-codec";
++		status = "ok";
++	};
++
++	sound_hippo_icdc {
++		status = "ok";
++		compatible = "ingenic,x2500-sound";
++		ingenic,model = "hippo";
++		ingenic,dai-link = "i2s-icodec", "dmic", "i2s-tloop";
++		ingenic,stream = "i2s-icodec", "dmic", "i2s-tloop";
++		ingenic,cpu-dai = <&i2s>, <&dmic>, <&i2s_tloop>;
++		ingenic,platform = <&aic>, <&dmic>, <&i2s_tloop>;
++		ingenic,codec = <&icodec>, <&dmic>, <&dump_pcm_codec>;
++		ingenic,codec-dai = "icodec", "dmic-codec-hifi", "pcm-dump";
++		ingenic,audio-routing = "Speaker", "HPOUTL", "DACL", "MICBIAS" ,
++			"ADCL",  "MICL",
++			"ADCR",  "MICR";
++		ingenic,spken-gpio = <&gpb 22 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	};
++
++};
+diff --git a/module_drivers/dts/hippo_v12.dts b/module_drivers/dts/hippo_v12.dts
+new file mode 100644
+index 000000000..acb4ca134
+--- /dev/null
++++ b/module_drivers/dts/hippo_v12.dts
+@@ -0,0 +1,431 @@
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include "x2500.dtsi"
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <generated/autoconf.h>
++
++#ifdef CONFIG_RD_X2500_HIPPO_CAMERA_1V0
++#include "hippo_cameras/RD_X2500_HIPPO_CAMERA_1V0.dtsi"
++#elif CONFIG_RD_X2500_HIPPO_CAMERA_1V1
++#include "hippo_cameras/RD_X2500_HIPPO_CAMERA_1V1.dtsi"
++#elif CONFIG_RD_X2000_HALLEY5_CAMERA_3V2
++#include "hippo_cameras/RD_X2000_HALLEY5_CAMERA_3V2.dtsi"
++#elif CONFIG_RD_X2000_HALLEY5_CAMERA_4V3
++#include "hippo_cameras/RD_X2000_HALLEY5_CAMERA_4V3.dtsi"
++#endif
++
++/ {
++	compatible = "ingenic,hippo_v12", "ingenic,x2500";
++
++	reserved-memory {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges =<>;
++
++		reserved_memory: reserved_mem@0x9a00000{
++		      compatible = "shared-dma-pool";
++		      reg = <0x09a00000 0x3600000>;
++		};
++	};
++};
++
++&uart0 {
++	status = "okay";
++	pinctrl-names = "default", "default";
++	pinctrl-0 = <&uart0_pc1>;
++	pinctrl-1 = <&uart0_pc1_1>;
++};
++
++&uart1 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pb>;
++};
++
++&uart2 {
++	status = "disable";
++};
++
++&uart3 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pd>;
++};
++
++&i2c0 {
++	pinctrl-0 = <&i2c0_pa>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&pinctrl {
++	touchscreen_pins:touchscreen-pins {
++		touchscreen_int_out_high:touchscreen-int-out-high {
++			ingenic,pinmux = <&gpc 6 6>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCHILVL>;
++		};
++		touchscreen_int_out_low:touchscreen-int-out-low {
++			ingenic,pinmux = <&gpc 6 6>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCLOLVL>;
++		};
++		touchscreen_int_input:touchscreen-int-input {
++			ingenic,pinmux = <&gpc 6 6>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT_FE>;
++		};
++		touchscreen_default:touchscreen-default {
++			ingenic,pinmux = <&gpc 6 6>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT>;
++		};
++	};
++};
++
++&i2c1 {
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	status = "okay";
++	pinctrl-0 = <&i2c1_pd>;
++
++	goodix@14{
++		compatible = "goodix,gt9xx"; /* do not modify */
++		reg = <0x14>; /* do not modify */
++		reset-gpios = <&gpc 7 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>; /* RST pin */
++		irq-gpios = <&gpc 6 IRQ_TYPE_EDGE_FALLING INGENIC_GPIO_NOBIAS>; /* INT pin */
++		goodix,driver-send-cfg = <1>;
++		touchscreen-size-x = <1280>;
++		touchscreen-size-y = <720>;
++		goodix,slide-wakeup = <0>;
++		goodix,type-a-report = <0>;
++		goodix,resume-in-workqueue = <0>;
++		goodix,int-sync = <1>;
++		goodix,swap-x2y = <0>;
++		goodix,auto-update-cfg = <0>;
++		goodix,power-off-sleep = <0>;
++		goodix,pen-suppress-finger = <0>;
++		irq-flags = <2>; /* 1 rising, 2 falling */
++		pinctrl-names = "default", "int-output-high", "int-output-low", "int-input";
++		pinctrl-0 = <&touchscreen_default>;
++		pinctrl-1 = <&touchscreen_int_out_high>;
++		pinctrl-2 = <&touchscreen_int_out_low>;
++		pinctrl-3 = <&touchscreen_int_input>;
++		goodix,cfg-group0 = [
++			00 D0 02 00 05 0A 05 00 01 08 28
++			05 50 32 03 05 00 00 00 00 00 00
++			00 00 00 00 00 87 28 09 17 15 31
++			0D 00 00 02 9B 03 25 00 00 00 00
++			00 03 64 32 00 00 00 0F 36 94 C5
++			02 07 00 00 04 9B 11 00 7B 16 00
++			64 1C 00 50 25 00 42 2F 00 42 00
++			00 00 00 00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 00 00 00
++			00 00 12 10 0E 0C 0A 08 06 04 02
++			FF FF FF FF FF 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 00 00 26
++			24 22 21 20 1F 1E 1D 00 02 04 06
++			08 0A 0C FF FF FF FF FF FF FF FF
++			FF FF FF 00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 CF 01];
++	};
++};
++
++&i2c2 {
++	clock-frequency = <100000>;
++	pinctrl-0 = <&i2c2_pb>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	rtc_pcf8563:rtc_pcf8563@51{
++		compatible = "nxp,pcf8563";
++		reg = <0x51>;
++		status = "ok";
++	    };
++};
++
++&i2c3 {
++	pinctrl-0 = <&i2c3_pa>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&ispcam0 {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&ispcam1 {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&ipu {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&i2d {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&cpufreq {
++	status = "disable";
++	operating-points = <
++		/*KHZ uV */
++		1200000	900000
++		750000	900000
++		600000	900000
++		500000	900000
++		400000	900000
++		375000	900000
++		300000	900000
++		200000	900000
++			>;
++
++};
++
++&pwmz {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm3_pb>;
++};
++
++&pdma {
++	status = "okay";
++};
++
++&msc1 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&msc1_pc>;
++	cap-mmc-highspeed;
++	/*
++	enable_cpm_rx_tuning;
++	enable_cpm_tx_tuning;
++	*/
++	mmc-hs200-1_8v;
++	max-frequency = <200000000>;
++	bus-width = <4>;
++	voltage-ranges = <1800 3300>;
++	/* special property */
++	ingenic,cd-gpios = <0>;
++	ingenic,rst-gpios = <0>;
++	ingenic,pwr-gpios = <0>;
++};
++
++&msc0 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&msc0_pb>;
++	cap-mmc-highspeed;
++	max-frequency = <100000000>;
++	bus-width = <4>;
++	voltage-ranges = <1800 3300>;
++	non-removable;
++
++	ingenic,sdio_clk = <1>;
++	keep-power-in-suspend;
++
++	/* special property */
++	ingenic,wp-gpios = <0>;
++	ingenic,removal-manual; /*removal-dontcare, removal-nonremovable, removal-removable, removal-manual*/
++
++	bcmdhd_wlan: bcmdhd_wlan {
++		 compatible = "android,bcmdhd_wlan";
++		 ingenic,sdio-irq = <&gpa 23 IRQ_TYPE_LEVEL_HIGH INGENIC_GPIO_NOBIAS>;
++		 ingenic,sdio-reset = <&gpa 27 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++};
++
++&mac0 {
++	pinctrl-names = "default", "reset";
++	pinctrl-0 = <&mac0_rmii_p0_normal>, <&mac0_rmii_p1_normal>;
++	pinctrl-1 = <&mac0_rmii_p0_rst>, <&mac0_rmii_p1_normal>;
++	status = "okay";
++	ingenic,rst-gpio = <&gpb 21 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,rst-ms = <10>;
++	ingenic,mac-mode = <RMII>;
++	ingenic,mode-reg = <0xb00000e8>;
++	ingenic,phy-clk-freq = <50000000>;
++};
++
++&sfc {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&sfc_pa>;
++	ingenic,sfc-init-frequency = <20000000>;
++	ingenic,sfc-max-frequency = <320000000>;
++	ingenic,use_ofpart_info      = /bits/ 8 <0>;
++	ingenic,spiflash_param_offset = <0>;
++};
++
++&spi0 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pc>;
++
++	spi-max-frequency = <48000000>;
++	num-cs = <2>;
++	cs-gpios = <0>, <0>;
++	ingenic,chnl = <0>;
++	ingenic,allow_cs_same = <1>;
++	ingenic,bus_num = <0>;
++	ingenic,has_dma_support = <1>;
++	ingenic,spi-src-clk = <1>;/*0.ext; 1.ssi*/
++
++	/* Add SPI interface device */
++	spidev: spidev@0 {
++		compatible = "rohm,dh2228fv";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++	};
++};
++
++&dtrng {
++	status = "okay";
++};
++
++&otg {
++	g-use-dma;
++	dr_mode = "otg";
++	device-using-dma = <1>;
++	status = "okay";
++};
++
++&otg_phy {
++	dr_mode = "otg";
++	status = "okay";
++	ingenic,vbus-dete-gpio = <&gpc 28 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,drvvbus-gpio = <&gpb 27 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	status = "okay";
++};
++
++/ {
++
++	extclk: extclk {
++		   clock-frequency = <24000000>;
++	};
++
++	gpio_keys: gpio_keys {
++		   compatible = "gpio-keys";
++
++		   power {
++			   label = "Power";
++			   linux,code = <KEY_POWER>;
++			   gpios = <&gpa 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			   gpio-key,wakeup;
++		   };
++
++		   bootsel0 {
++			   label = "bootsel0";
++			   linux,code = <KEY_HOME>;
++			   gpios = <&gpc 0 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			   gpio-key,wakeup;
++		   };
++
++		   bootsel1 {
++			   label = "bootsel1";
++			   linux,code = <KEY_BACK>;
++			   gpios = <&gpc 1 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			   gpio-key,wakeup;
++		   };
++
++	   };
++
++	bt_power {
++		compatible = "ingenic,bt_power";
++		ingenic,reg-on-gpio = <&gpa 24 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,wake-gpio = <&gpa 25 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++};
++
++&soc_nna{
++	status="okay";
++};
++
++&el150 {
++	status = "disable";
++};
++
++
++&dpu {
++	status = "okay";
++	ingenic,disable-rdma-fb = <1>;
++	ingenic,layer-exported = <1 1 0 0>;
++	ingenic,layer-frames   = <3 3 1 2>;
++	ingenic,layer-framesize = <720 1280>, <720 1280>, <720 1280>, <320 240>;   //Max framesize for each layer.
++	layer,color_mode	= <1 6 0 0>;					//src fmt
++	layer,src-size       	= <720 1280>, <720 1280>, <720 1280>, <240 200>;	//Layer src size should smaller than framesize
++	layer,target-size	= <720 1280>, <720 1280>, <720 1280>, <240 200>;	//Target Size should smaller than src_size.
++	layer,target-pos	= <0 0>, <0 0>, <0 0>, <100 980>;	//target pos , the start point of the target panel.
++	layer,enable		= <1 1 0 0>;					//layer enabled or disabled.
++	ingenic,logo-pan-layer	= <0>;						//on which layer should init logo pan on.
++	/*memory-region=<&reserved_memory>;*/
++	port {
++		dpu_out_ep: endpoint {
++			remote-endpoint = <&panel_kd050hdfia020_ep>;
++	    };
++	};
++};
++
++/ {
++	display-dpi {
++		compatible = "simple-bus";
++		#interrupt-cells = <1>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++		panel_kd050hdfia020 {
++			compatible = "ingenic,kd050hdfia020";
++			status = "okay";
++			pinctrl-names = "default";
++			ingenic,vdd-en-gpio = <&gpc 3 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,rst-gpio = <&gpc 2 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	/*		ingenic,lcd-pwm-gpio = <&gpb 31 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;*/
++			port {
++				panel_kd050hdfia020_ep: endpoint {
++					remote-endpoint = <&dpu_out_ep>;
++				};
++			};
++		};
++
++	};
++
++	backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwmz 3 10000>; /* arg1: pwm channel id [0~15]. arg2: period in ns. */
++		brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
++		default-brightness-level = <5>;
++		/*default brightness is 5, you can echo x > /sys/devices/platform/backlight/backlight/backlight/brightness to adjust backlight*/
++	};
++};
++
++
++/ {
++	dump_dmic_codec:dump_dmic_codec{
++		compatible = "ingenic,dmic-dump-codec";
++		status = "ok";
++	};
++	dump_pcm_codec:dump_pcm_codec{
++		compatible = "ingenic,pcm-dump-codec";
++		status = "ok";
++	};
++
++	sound_hippo_icdc {
++		status = "ok";
++		compatible = "ingenic,x2500-sound";
++		ingenic,model = "hippo_v12";
++		ingenic,dai-link = "i2s-icodec", "dmic", "i2s-tloop";
++		ingenic,stream = "i2s-icodec", "dmic", "i2s-tloop";
++		ingenic,cpu-dai = <&i2s>, <&dmic>, <&i2s_tloop>;
++		ingenic,platform = <&aic>, <&dmic>, <&i2s_tloop>;
++		ingenic,codec = <&icodec>, <&dmic>, <&dump_pcm_codec>;
++		ingenic,codec-dai = "icodec", "dmic-codec-hifi", "pcm-dump";
++		ingenic,audio-routing = "Speaker", "HPOUTL", "DACL", "MICBIAS" ,
++			"ADCL",  "MICL",
++			"ADCR",  "MICR";
++		ingenic,spken-gpio = <&gpb 22 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	};
++
++};
+diff --git a/module_drivers/dts/kale_v10.dts b/module_drivers/dts/kale_v10.dts
+new file mode 100644
+index 000000000..f99e405d9
+--- /dev/null
++++ b/module_drivers/dts/kale_v10.dts
+@@ -0,0 +1,574 @@
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include "x2000.dtsi"
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <generated/autoconf.h>
++
++#include "halley5_cameras/RD_X2000_HALLEY5_CAMERA_4V3_2KALE.dtsi"
++
++#define LCD_PANEL_MA0060 0
++
++
++/ {
++	compatible = "ingenic,kale", "ingenic,x2000";
++	/*chosen {
++		bootargs = "console=ttyS1,115200 mem=128M@0x0ip=off init=/linuxrc ubi.mtd=3 root=ubi0:rootfs ubi.mtd=4 rootfstype=ubifs rw";
++	};*/
++
++	reserved-memory {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges =<>;
++
++		reserved_memory: reserved_mem@0x3000000{
++		      compatible = "shared-dma-pool";
++		      reg = <0x03000000 0x1000000>;
++		};
++	};
++};
++
++&uart0 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pd>;
++};
++
++&uart2 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pd>;
++};
++
++&uart3 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pc>;
++};
++
++&cpufreq {
++	status = "okay";
++	operating-points = <
++		/*KHZ uV */
++		1200000	900000
++		750000	900000
++		600000	900000
++		500000	900000
++		400000	900000
++		375000	900000
++		300000	900000
++		200000	900000
++			>;
++
++};
++
++&pinctrl {
++	ingenic,gpa_voltage = <GPIO_VOLTAGE_1V8>;
++};
++
++&pinctrl {
++	touchscreen_pins:touchscreen-pins {
++		touchscreen_int_out_high:touchscreen-int-out-high {
++			ingenic,pinmux = <&gpc 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCHILVL>;
++		};
++		touchscreen_int_out_low:touchscreen-int-out-low {
++			ingenic,pinmux = <&gpc 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCLOLVL>;
++		};
++		touchscreen_int_input:touchscreen-int-input {
++			ingenic,pinmux = <&gpc 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT_FE>;
++		};
++		touchscreen_default:touchscreen-default {
++			ingenic,pinmux = <&gpc 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT>;
++		};
++	};
++};
++
++&i2c1 {
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c1_pc>;
++	status = "okay";
++#if LCD_PANEL_MA0060
++	focaltech@0x38{
++		compatible = "focaltech,fts"; /* do not modify */
++		reg = <0x38>; /* do not modify */
++		interrupt-parent = <&gpc>; /* INT pin */
++		interrupts = <9>;
++		focaltech,reset-gpio = <&gpc 8 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>; /* RST pin */
++		focaltech,irq-gpio = <&gpc 9 IRQ_TYPE_EDGE_FALLING INGENIC_GPIO_NOBIAS>; /* INT pin */
++		focaltech,max-touch-number = <5>;
++		focaltech,display-coords = <0 0 1080 1920>;	/* resolution */
++
++		/* key settings */
++		focaltech,have-key;
++		focaltech,key-number = <3>;
++		focaltech,keys = <139 172 158>; /* key codes*/
++		focaltech,key-x-coords = <200 600 800>; /* keys x coords */
++		focaltech,key-y-coords = <2000 2000 2000>; /* keys y coords */
++
++	};
++#else
++	goodix@0x14{
++		compatible = "goodix,gt9xx"; /* do not modify */
++		reg = <0x14>; /* do not modify */
++		interrupt-parent = <&gpa>; /* INT pin */
++		interrupts = <9>;
++		reset-gpios = <&gpc 8 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>; /* RST pin */
++		irq-gpios = <&gpc 9 IRQ_TYPE_EDGE_FALLING INGENIC_GPIO_NOBIAS>; /* INT pin */
++		goodix,driver-send-cfg = <1>;
++		touchscreen-size-x = <480>;
++		touchscreen-size-y = <800>;
++		goodix,slide-wakeup = <0>;
++		goodix,type-a-report = <0>;
++		goodix,resume-in-workqueue = <0>;
++		goodix,int-sync = <1>;
++		goodix,swap-x2y = <0>;
++		goodix,auto-update-cfg = <0>;
++		goodix,power-off-sleep = <0>;
++		goodix,pen-suppress-finger = <0>;
++		irq-flags = <2>; /* 1 rising, 2 falling */
++		pinctrl-names = "default", "int-output-high", "int-output-low", "int-input";
++		pinctrl-0 = <&touchscreen_default>;
++		pinctrl-1 = <&touchscreen_int_out_high>;
++		pinctrl-2 = <&touchscreen_int_out_low>;
++		pinctrl-3 = <&touchscreen_int_input>;
++		goodix,cfg-group0 = [
++			42 20 03 E0 01 0A 0D 00
++			01 08 28 05 50 32 03 05
++			00 00 00 00 00 00 00 00
++			00 00 00 87 28 09 17 15
++			31 0D 00 00 00 9A 03 1C
++			00 00 00 00 00 03 64 32
++			00 00 00 0F 23 94 C5 02
++			07 00 00 04 A3 10 00 8B
++			13 00 7A 16 00 66 1B 00
++			58 20 00 58 00 00 00 00
++			00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00
++			02 04 06 08 0A 0C 0E 10
++			12 FF FF FF FF FF FF FF
++			FF FF FF FF FF FF FF FF
++			FF FF FF FF FF FF 00 02
++			04 06 08 0A 0C 1D 1E 1F
++			20 21 22 24 26 FF FF FF
++			FF FF FF FF FF FF FF FF
++			FF FF FF FF FF FF FF FF
++			FF FF FF FF FF FF FF FF
++			4A 01];
++	};
++#endif
++};
++
++
++&i2c3 {
++	status = "okay";
++};
++&i2c4 {
++	status = "disable";
++};
++
++&felix {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&helix {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&ispcam0 {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&ispcam1 {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&rotate {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&pdma {
++	status = "okay";
++};
++
++&msc0 {
++	status = "disable";
++};
++
++&msc1 {
++	status = "okay";
++	pinctrl-names ="default","enable", "disable";
++	pinctrl-0 = <&msc1_4bit>;
++	pinctrl-1 = <&rtc32k_enable>;
++	pinctrl-2 = <&rtc32k_disable>;
++
++	sd-uhs-sdr25;
++	cap-sd-highspeed;
++	max-frequency = <100000000>;
++	bus-width = <4>;
++	voltage-ranges = <1800 3300>;
++	non-removable;
++	keep-power-in-suspend;
++	ingenic,sdio_clk = <1>;
++	/* special property */
++	ingenic,sdr-gpios = <0>;
++	ingenic,rst-gpios = <0>;
++	ingenic,removal-manual; /*removal-dontcare, removal-nonremovable, removal-removable, removal-manual*/
++
++	bcmdhd_wlan: bcmdhd_wlan {
++		 compatible = "android,bcmdhd_wlan";
++		 ingenic,sdio-irq = <&gpd 0 IRQ_TYPE_LEVEL_HIGH INGENIC_GPIO_NOBIAS>;
++		 ingenic,sdio-reset = <&gpd 1 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++};
++
++&msc2 {
++	status = "okay";
++	pinctrl-names ="default";
++	pinctrl-0 = <&msc2_4bit>;
++	mmc-hs200-1_8v;
++	cap-mmc-highspeed;
++	non-removable;
++	max-frequency = <200000000>;
++	bus-width = <4>;
++	non-removable;
++	voltage-ranges = <1800 3300>;
++
++	/* special property */
++	ingenic,rst-gpios = <0>;
++	ingenic,sdr-gpios = <&gpc 0 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++};
++
++
++&mac0 {
++        pinctrl-names = "default", "reset";
++        pinctrl-0 = <&mac0_rmii_p0_normal>, <&mac0_rmii_p1_normal>,<&mac0_phy_clk>;
++        pinctrl-1 = <&mac0_rmii_p0_rst>, <&mac0_rmii_p1_normal>,<&mac0_phy_clk>;
++        status = "okay";
++        ingenic,rst-gpio = <&gpc 5 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++        ingenic,rst-ms = <10>;
++	ingenic,rst-delay-ms = <15>;
++        ingenic,mac-mode = <RMII>;
++        ingenic,mode-reg = <0xb00000e4>;
++        ingenic,phy-clk-freq = <50000000>;
++};
++
++&sfc {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&sfc_pe>;
++	ingenic,sfc-init-frequency = <200000000>;
++	ingenic,sfc-max-frequency = <320000000>;
++	ingenic,use_ofpart_info  = /bits/ 8 <0>;
++	ingenic,spiflash_param_offset = <0>;
++
++	norflash@0 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nor flash partition */
++			uboot@0 {
++				label = "uboot";
++				reg = <0x0000000 0x40000>;
++				/*read-only;*/
++			};
++
++			kernel@40000 {
++				label = "kernel";
++				reg = <0x40000 0x300000>;
++			};
++
++			rootfs@360000 {
++				label = "rootfs";
++				reg = <0x360000 0xca0000>;
++			};
++		};
++	};
++
++	nandflash@1 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nand flash partition */
++			partition@0 {
++				label = "uboot";
++				reg = <0x0000000 0x100000>;
++				/*read-only;*/
++			};
++
++			partition@100000 {
++				label = "kernel";
++				reg = <0x100000 0x800000>;
++			};
++
++			partition@900000 {
++				label = "rootfs";
++				reg = <0x900000 0xf700000>;
++			};
++		};
++	};
++
++};
++
++&spi0 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pb>;
++
++	spi-max-frequency = <54000000>;
++	num-cs = <2>;
++	cs-gpios = <0>, <0>;
++	/*cs-gpios = <&gpa 27 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>, <&gpa 27 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;*/
++	ingenic,chnl = <0>;
++	ingenic,allow_cs_same = <1>;
++	ingenic,bus_num = <0>;
++	ingenic,has_dma_support = <0>;
++	ingenic,spi-src-clk = <1>;/*0.ext; 1.ssi*/
++
++	/* Add SPI interface device */
++	spidev: spidev@0 {
++		compatible = "rohm,dh2228fv";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++	};
++};
++
++&dtrng {
++	status = "okay";
++};
++
++&pwm {
++	pinctrl-names = "default";
++/*	pinctrl-0 = <&pwm0_pd>; */
++/*	pinctrl-0 = <&pwm1_pc>; */
++	pinctrl-0 = <&pwm14_pc>;
++	status = "okay";
++};
++
++&otg {
++	g-use-dma;
++	dr_mode = "otg";
++	device-using-dma = <1>;
++	status = "okay";
++};
++
++
++&otg_phy {
++	status = "okay";
++	ingenic,vbus-dete-gpio = <&gpd 17 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,drvvbus-gpio = <&gpe 22 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++};
++
++&as_be_baic {
++	pinctrl-names = "default";
++	pinctrl-0 =  <&baic4_pd>;
++};
++
++&as_dmic {
++	pinctrl-names = "default";
++	pinctrl-0 = <&dmic_pc_4ch>;
++};
++
++&dpu {
++	status = "okay";
++	ingenic,disable-rdma-fb = <1>;
++	//[>Defines the init state of composer fb export infomations.<]
++	ingenic,layer-exported = <1 1 0 0>;
++	ingenic,layer-frames   = <2 2 2 2>;
++	ingenic,layer-framesize = <800 480>, <800 480>, <320 240>, <320 240>;   //[>Max framesize for each layer.<]
++	layer,color_mode	= <0 0 0 0>;					//[>src fmt,<]
++	layer,src-size       	= <800 480>, <800 480>, <320 240>, <240 200>;	//[>Layer src size should smaller than framesize<]
++	layer,target-size	= <800 480>, <800 240>, <160 240>, <240 200>;	//[>Target Size should smaller than src_size.<]
++	layer,target-pos	= <0 0>, <0 240>, <340 480>, <100 360>;	//[>target pos , the start point of the target panel.<]
++	layer,enable		= <1 1 1 1>;					//[>layer enabled or disabled.<]
++	ingenic,logo-pan-layer	= <0>;						//[>on which layer should init logo pan on.<]
++	port {
++		dpu_out_ep: endpoint {
++#if LCD_PANEL_MA0060
++			remote-endpoint = <&panel_ma0060_ep>;
++#else
++			remote-endpoint = <&panel_kd050wvfpa029_ep>;
++#endif
++	    };
++	};
++};
++
++&efuse {
++	status = "okay";
++	ingenic,efuse-en-gpio = <&gpd 19 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++};
++
++
++/ {
++
++	extclk: extclk {
++		clock-frequency = <24000000>;
++	};
++
++	gpio_keys: gpio_keys {
++		   compatible = "gpio-keys";
++
++		   wakeup {
++			   label = "WAKEUP";
++			   linux,code = <KEY_WAKEUP>;
++			   gpios = <&gpe 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			   gpio-key,wakeup;
++		   };
++
++		   bootsel0 {
++			   label = "bootsel0";
++			   linux,code = <KEY_HOME>;
++			   gpios = <&gpe 25 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		   };
++
++		   bootsel1 {
++			   label = "bootsel1";
++			   linux,code = <KEY_BACK>;
++			   gpios = <&gpe 26 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		   };
++	   };
++
++	/*
++	 * gpd 21 bt wakeup host
++	 * gpd 22 host wakeup bt
++	 */
++	bt_power {
++		compatible = "ingenic,bt_power";
++		ingenic,reg-on-gpio = <&gpd 20 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,wake-gpio = <&gpd 22 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++
++	sound {
++		compatible = "ingenic,x2000-sound";
++		ingenic,model = "kale_v10";
++		ingenic,spken-gpio = <&gpd 18 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	};
++
++	display-dbi {
++		compatible = "simple-bus";
++		#interrupt-cells = <1>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++
++#if LCD_PANEL_MA0060
++		panel_ma0060 {
++			compatible = "ingenic,ma0060";
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&smart_lcd_pb_te>;
++			ingenic,vdd-en-gpio = <&gpc 4 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,rst-gpio = <&gpc 25 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,lcd-pwm-gpio = <&gpc 14 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			port {
++				panel_ma0060_ep: endpoint {
++					remote-endpoint = <&dpu_out_ep>;
++				};
++			};
++		};
++#else
++		panel_kd050wvfpa029 {
++			compatible = "ingenic,kd050wvfpa029";
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&tft_lcd_pb_rgb888>;
++		//	ingenic,lcd-pwm-gpio = <&gpc 14 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			ingenic,vdd-en-gpio = <&gpc 26 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			port {
++				panel_kd050wvfpa029_ep: endpoint {
++					remote-endpoint = <&dpu_out_ep>;
++				};
++			};
++		};
++#endif
++	};
++backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwm 14 1000000>; /*[> arg1: pwm channel id [0~15]. arg2: period in ns. <]*/
++		brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
++		default-brightness-level = <4>;
++	};
++
++
++	spi_gpio {
++		status = "disable";
++		compatible = "spi-gpio";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		gpio-sck = <&gpb 28 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		gpio-miso = <&gpb 29 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		gpio-mosi = <&gpb 30 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		cs-gpios = <&gpb 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		num-chipselects = <1>;
++
++		/* clients */
++		spidev1: spidev1@0 {
++			status = "disable";
++			compatible = "rohm,dh2228fv";
++			reg = <0>;
++			spi-max-frequency = <500000>;
++		};
++	};
++#ifdef CONFIG_LINUX_PMEM
++	linux_pmem {
++		status = "ok";
++		compatible = "linux_pmem";
++		linux_pmem,name = "pmem";
++		linux_pmem,no_allocator = <0>;
++		linux_pmem,cached       = <1>;
++		linux_pmem,start        = <0>;
++		linux_pmem,size         = CONFIG_PMEM_RESERVE_SIZE;
++    };
++#endif
++};
++
++
++/* Board Sleep GPIO configuration. */
++/* <0 1 2 3 .... 31>, set one of the pin to state.*/
++&gpa {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpb {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpc {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpd {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
+diff --git a/module_drivers/dts/m300-pinctrl.dtsi b/module_drivers/dts/m300-pinctrl.dtsi
+new file mode 100644
+index 000000000..c9d1def2b
+--- /dev/null
++++ b/module_drivers/dts/m300-pinctrl.dtsi
+@@ -0,0 +1,658 @@
++#include <dt-bindings/pinctrl/ingenic-pinctrl.h>
++
++&pinctrl {
++	uart0_pin: uart0-pin {
++		uart0_pd: uart0-pd {
++			ingenic,pinmux = <&gpd 23 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++	uart1_pin: uart1-pin {
++		uart1_pc_rx_tx: uart1-pc-rx-tx {
++			ingenic,pinmux = <&gpc 23 24>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		uart1_pc: uart1-pc {
++			ingenic,pinmux = <&gpc 21 24>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++
++	uart2_pin: uart2-pin {
++		uart2_pd: uart2-pd {
++			ingenic,pinmux = <&gpd 30 31>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	uart3_pin: uart3-pin {
++		uart3_pc: uart3-pc {
++			ingenic,pinmux = <&gpc 25 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		uart3_pd: uart3-pd {
++			ingenic,pinmux = <&gpd 0 3>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++
++	uart4_pin: uart4-pin {
++		uart4_pa: uart4-pa {
++			ingenic,pinmux = <&gpa 0 3>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		uart4_pc: uart4-pc {
++			ingenic,pinmux = <&gpc 9 12>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++		};
++	};
++
++	uart5_pin: uart5-pin {
++		uart5_pa: uart5-pa {
++			ingenic,pinmux = <&gpa 4 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		uart5_pc: uart5-pc {
++			ingenic,pinmux = <&gpc 5 6>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++		};
++	};
++
++	uart6_pin: uart6-pin {
++		uart6_pa: uart6-pa {
++			ingenic,pinmux = <&gpa 6 7>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		uart6_pc: uart6-pc {
++			ingenic,pinmux = <&gpc 7 8>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++		};
++	};
++
++	uart7_pin: uart7-pin {
++		uart7_pa: uart7-pa {
++			ingenic,pinmux = <&gpa 8 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		uart7_pc: uart7-pc {
++			ingenic,pinmux = <&gpc 1 2>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++		};
++	};
++
++	uart8_pin: uart8-pin {
++		uart8_pb: uart8-pb {
++			ingenic,pinmux = <&gpb 28 29>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++		};
++	};
++
++	uart9_pin: uart9-pin {
++		uart9_pb: uart9-pb {
++			ingenic,pinmux = <&gpb 30 31>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++		};
++	};
++
++	i2c0_pin: i2c0-pin {
++		i2c0_pc: i2c0-pc {
++			ingenic,pinmux = <&gpc 13 14>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++		};
++	};
++
++	i2c1_pin: i2c1-pin {
++		i2c1_pc: i2c1-pc {
++			ingenic,pinmux = <&gpc 23 24>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	i2c2_pin: i2c2-pin {
++		i2c2_pb: i2c2-pb {
++			ingenic,pinmux = <&gpb 22 23>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	i2c3_pin: i2c3-pin {
++		i2c3_pd: i2c3-pd {
++			ingenic,pinmux = <&gpd 30 31>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		i2c3_pa: i2c3-pa {
++			ingenic,pinmux = <&gpa 16 17>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	i2c4_pin: i2c4-pin {
++		i2c4_pc: i2c4-pc {
++			ingenic,pinmux = <&gpc 25 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		i2c4_pd: i2c4-pd {
++			ingenic,pinmux = <&gpd 0 1>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	i2c5_pin: i2c5-pin {
++		i2c5_pc: i2c5-pc {
++			ingenic,pinmux = <&gpc 27 28>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		i2c5_pd: i2c5-pd {
++			ingenic,pinmux = <&gpd 4 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++
++	msc0_pin: msc0-pin {
++		msc0_4bit: msc0-4bit {
++			ingenic,pinmux = <&gpd 17 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		msc0_8bit: msc0-8bit {
++			ingenic,pinmux = <&gpd 17 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	msc1_pin: msc1-pin {
++		msc1_4bit: msc1-4bit {
++			ingenic,pinmux = <&gpd 8 13>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	msc2_pin: msc2-pin {
++		msc2_4bit: msc2-4bit {
++			ingenic,pinmux = <&gpe 0 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	mac0_phy_clk: mac0-phy-clk {
++		ingenic,pinmux = <&gpc 1 1>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		ingenic,pincfg = <&gpc 1 1 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++	};
++
++	mac0_rmii_p0: mac0-rmii-p0 {
++		mac0_rmii_p0_normal: mac0-rmii-normal {
++			ingenic,pinmux = <&gpc 6 7>, <&gpc 11 11>, <&gpc 15 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++			ingenic,pincfg = <&gpc 6 7 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>, \
++					 <&gpc 11 11 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>, \
++					 <&gpc 15 15 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>;
++		};
++		mac0_rmii_p0_rst: mac0-rmii-p0-rst {
++			ingenic,pinmux = <&gpc 6 7>, <&gpc 11 11>, <&gpc 15 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT>;
++			ingenic,pincfg = <&gpc 6 7 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>, \
++					 <&gpc 11 11 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>, \
++					 <&gpc 15 15 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>;
++		};
++	};
++
++	mac0_rmii_p1: mac0-rmii-p1 {
++		mac0_rmii_p1_normal: mac0-rmii-p1-normal {
++			ingenic,pinmux = <&gpc 2 3>, <&gpc 10 10>, <&gpc 12 13>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++			ingenic,pincfg = <&gpc 2 3 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpc 10 10 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpc 12 13 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++		};
++
++		mac0_rmii_p1_nomdio: mac0-rmii-p1-nomdio {
++			ingenic,pinmux = <&gpc 2 3>, <&gpc 10 10>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++			ingenic,pincfg = <&gpc 2 3 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpc 10 10 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++		};
++	};
++
++
++	mac0_rgmii_p0: mac0-rgmii-p0 {
++		mac0_rgmii_p0_normal: mac0-rgmii-normal {
++			ingenic,pinmux = <&gpc 6 9>, <&gpc 11 11>, <&gpc 15 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++			ingenic,pincfg = <&gpc 6 9 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>, \
++					 <&gpc 11 11 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>, \
++					 <&gpc 15 15 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>;
++		};
++		mac0_rgmii_p0_rst: mac0-rgmii-p0-rst {
++			ingenic,pinmux = <&gpc 6 9>, <&gpc 11 11>, <&gpc 15 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT>;
++			ingenic,pincfg = <&gpc 6 9 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>, \
++					 <&gpc 11 11 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>, \
++					 <&gpc 15 15 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>;
++		};
++	};
++
++	mac0_rgmii_p1: mac0-rgmii-p1 {
++		mac0_rgmii_p1_normal: mac0-rgmii-p1-normal {
++			ingenic,pinmux = <&gpc 2 5>, <&gpc 10 10>, <&gpc 12 14>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++			ingenic,pincfg = <&gpc 2 5 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpc 10 10 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>,\
++					 <&gpc 12 14 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++		};
++
++		mac0_rgmii_p1_nomdio: mac0-rgmii-p1-nomdio {
++			ingenic,pinmux = <&gpc 2 5>, <&gpc 10 10>, <&gpc 14 14>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++			ingenic,pincfg = <&gpc 2 5 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpc 10 10 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpc 14 14 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++		};
++	};
++
++	mac1_phy_clk: mac1-phy-clk {
++		ingenic,pinmux = <&gpb 23 23>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++		ingenic,pincfg = <&gpc 23 23 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++	};
++
++	mac1_rmii_p0: mac1-rmii-p0 {
++		mac1_rmii_p0_normal: mac1-rmii-normal {
++			ingenic,pinmux = <&gpb 12 13>, <&gpb 18 18>, <&gpb 22 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++			ingenic,pincfg = <&gpb 12 13 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>, \
++					 <&gpb 18 18 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>, \
++					 <&gpb 22 22 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>;
++		};
++		mac1_rmii_p0_rst: mac1-rmii-p0-rst {
++			ingenic,pinmux = <&gpb 12 13>, <&gpb 18 18>, <&gpb 22 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT>;
++			ingenic,pincfg = <&gpb 12 13 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>, \
++					 <&gpb 18 18 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>, \
++					 <&gpb 22 22 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>;
++		};
++	};
++
++	mac1_rmii_p1: mac1-rmii-p1 {
++		mac1_rmii_p1_normal: mac1-rmii-p1-normal {
++			ingenic,pinmux = <&gpb 8 9>, <&gpb 17 17>, <&gpb 19 20>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++			ingenic,pincfg = <&gpb 8 9 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpb 17 17 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpb 19 20 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++		};
++
++		mac1_rmii_p1_nomdio: mac1-rmii-p1-nomdio {
++			ingenic,pinmux = <&gpb 8 9>, <&gpb 17 17>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++			ingenic,pincfg = <&gpb 8 9 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpb 17 17 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++		};
++	};
++
++	mac1_rgmii_p0: mac1-rgmii-p0 {
++		mac1_rgmii_p0_normal: mac1-rgmii-normal {
++			ingenic,pinmux = <&gpb 12 15>, <&gpb 18 18>, <&gpb 22 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++			ingenic,pincfg = <&gpb 12 15 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>, \
++					 <&gpb 18 18 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>, \
++					 <&gpb 22 22 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>;
++		};
++		mac1_rgmii_p0_rst: mac1-rgmii-p0-rst {
++			ingenic,pinmux = <&gpb 12 15>, <&gpb 18 18>, <&gpb 22 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT>;
++			ingenic,pincfg = <&gpb 12 15 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>, \
++					 <&gpb 18 18 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>, \
++					 <&gpb 22 22 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>;
++		};
++	};
++
++	mac1_rgmii_p1: mac1-rgmii-p1 {
++		mac1_rgmii_p1_normal: mac1-rgmii-p1-normal {
++			ingenic,pinmux = <&gpb 8 11>, <&gpb 17 17>, <&gpb 19 21>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++			ingenic,pincfg = <&gpb 8 11 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>,\
++					 <&gpb 17 17 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpb 19 21 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++		};
++
++		mac1_rgmii_p1_nomdio: mac1-rgmii-p1-nomdio {
++			ingenic,pinmux = <&gpb 8 11>, <&gpb 17 17>, <&gpb 21 21>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++			ingenic,pincfg = <&gpb 8 11 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>,\
++					 <&gpb 17 17 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpb 21 21 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++		};
++	};
++
++	pwm_pin: pwm-pin{
++		pwm0_pc: pwm0_pc {
++			ingenic,pinmux = <&gpc 0 0>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm1_pc: pwm1_pc {
++			ingenic,pinmux = <&gpc 1 1>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm2_pc: pwm2_pc {
++			ingenic,pinmux = <&gpc 2 2>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm3_pc: pwm3_pc {
++			ingenic,pinmux = <&gpc 3 3>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm4_pc: pwm4_pc {
++			ingenic,pinmux = <&gpc 4 4>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm5_pc: pwm5_pc {
++			ingenic,pinmux = <&gpc 5 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm6_pc: pwm6_pc {
++			ingenic,pinmux = <&gpc 6 6>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm7_pc: pwm7_pc {
++			ingenic,pinmux = <&gpc 7 7>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm8_pc: pwm8_pc {
++			ingenic,pinmux = <&gpc 8 8>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm9_pc: pwm9_pc {
++			ingenic,pinmux = <&gpc 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm10_pc: pwm10_pc {
++			ingenic,pinmux = <&gpc 10 10>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm11_pc: pwm11_pc {
++			ingenic,pinmux = <&gpc 11 11>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm12_pc: pwm12_pc {
++			ingenic,pinmux = <&gpc 12 12>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm13_pc: pwm13_pc {
++			ingenic,pinmux = <&gpc 13 13>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm14_pc: pwm14_pc {
++			ingenic,pinmux = <&gpc 14 14>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm15_pc: pwm15_pc {
++			ingenic,pinmux = <&gpc 15 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm0_pd: pwm0_pd {
++			ingenic,pinmux = <&gpd 30 30>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	 };
++
++	sfc_pin: sfc-pin {
++		sfc_pd_8bit: sfc-pd_8bit {
++			ingenic,pinmux = <&gpd 17 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		sfc_pd_4bit: sfc-pd_4bit {
++			ingenic,pinmux = <&gpd 17 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++
++		sfc_pe: sfc-pe {
++			ingenic,pinmux = <&gpe 16 21>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	cim_pin: cim-pin {
++		cim_pa: cim-pa {
++			ingenic,pinmux = <&gpa 0 7>, <&gpa 12 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	 };
++	vic_pin: vic-pin {
++		vic_pa_low_10bit: vic-pa-low-10bit {
++			ingenic,pinmux = <&gpa 0 9>, <&gpa 12 14>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		vic_pa_high_10bit: vic-pa-high-10bit {
++			ingenic,pinmux = <&gpa 2 14>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		vic_pa_12bit: vic-pa-12bit {
++			ingenic,pinmux = <&gpa 0 14>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	 };
++	cim_vic_mclk: cim-vic-mclk {
++		/* extclk 24M.*/
++		cim_vic_mclk_pe_24M: cim-vic-mclk-pe-24M {
++			ingenic,pinmux = <&gpe 24 24>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		cim_vic_mclk_pe: cim-vic-mclk-pe {
++			ingenic,pinmux = <&gpe 24 24>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		cim_vic_mclk_pc: cim-vic-mclk-pc {
++			ingenic,pinmux = <&gpc 15 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	lcd_pins: lcd-pins {
++		tft_lcd_pb_rgb888: tft-lcd-pb-rgb888 {
++			ingenic,pinmux = <&gpb 0 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++
++		tft_lcd_pb_rgb565: tft-lcd-pb-rgb565 {
++			ingenic,pinmux = <&gpb 0 15>, <&gpb 24 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++
++		tft_lcd_pb_rgb666: tft-lcd-pb-rgb666 {
++			ingenic,pinmux = <&gpb 0 17>, <&gpb 24 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++
++		smart_lcd_pb_16bit: smart-lcd-pb-16bit {
++			ingenic,pinmux = <&gpb 0 15>, <&gpb 25 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		smart_lcd_pb_9bit: smart-lcd-pb-9bit {
++			ingenic,pinmux = <&gpb 0 8>, <&gpb 25 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		smart_lcd_pb_8bit: smart-lcd-pb-8bit {
++			ingenic,pinmux = <&gpb 0 7>, <&gpb 25 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		smart_lcd_spi: smart-lcd-pb-spi {
++			ingenic,pinmux = <&gpb 0 0>, <&gpb 25 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		smart_lcd_pb_te: smart-lcd-pb-te {
++			ingenic,pinmux = <&gpb 27 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	baic1_tmclk_pc: baic1-tmclk-pc {
++		ingenic,pinmux = <&gpc 8 8>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	baic1_rmclk_pc: baic1-rmclk-pc {
++		ingenic,pinmux = <&gpc 1 1>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	baic1_pin: baic1-pin {
++		baic1_pc: baic1-pin-pc {
++			ingenic,pinmux = <&gpc 2 7>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		baic1_combine_pc: baic1-cpin-pc {
++			ingenic,pinmux = <&gpc 4 7>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	baic2_mclk_pa: baic2-mclk-pa {
++		ingenic,pinmux = <&gpa 7 7>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	baic2_pa: baic2-pa {
++		ingenic,pinmux = <&gpa 9 13>, <&gpa 17 17>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++	baic2_pa_tdm1: baic2-pa-tdm1 {
++		ingenic,pinmux = <&gpa 9 10>, <&gpa 17 17>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++	baic2_pa_tdm2: baic2-pa-tdm2 {
++		ingenic,pinmux = <&gpa 9 11>, <&gpa 17 17>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	baic3_mclk_pa: baic3-mclk-pa {
++		ingenic,pinmux = <&gpa 0 0>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	baic3_pa: baic3-pa {
++		ingenic,pinmux = <&gpa 2 6>, <&gpa 16 16>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	baic3_pa_tdm1: baic3-pa-tdm1 {
++		ingenic,pinmux = <&gpa 2 3>, <&gpa 16 16>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	baic3_pa_tdm2: baic3-pa-tdm2 {
++		ingenic,pinmux = <&gpa 2 4>, <&gpa 16 16>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	baic4_pd: baic4-pd {
++		ingenic,pinmux = <&gpd 2 5>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		ingenic,pincfg = <&gpd 4 4 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>;
++	};
++
++	spdif_pc: spdif-pc {
++		ingenic,pinmux = <&gpc 13 14>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		ingenic,pincfg = <&gpc 14 14 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 7)>;
++	};
++	spdif_pc_in: spdif-pc-in {
++		ingenic,pinmux = <&gpc 13 13>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++	spdif_pc_out: spdif-pc-out {
++		ingenic,pinmux = <&gpc 14 14>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		ingenic,pincfg = <&gpc 14 14 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 7)>;
++	};
++
++	dmic_pc: dmic-pc {
++		ingenic,pinmux = <&gpc 20 24>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++	};
++	dmic_pc_2ch: dmic-pc-2ch {
++		ingenic,pinmux = <&gpc 20 21>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++	};
++	dmic_pc_4ch: dmic-pc-4ch {
++		ingenic,pinmux = <&gpc 20 22>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++	};
++	dmic_pc_6ch: dmic-pc-6ch {
++		ingenic,pinmux = <&gpc 20 23>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++	};
++
++	spi0_pb: spi0-pb {
++		ingenic,pinmux = <&gpb 28 31>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++	};
++
++	spi1_pc: spi0-pc {
++		ingenic,pinmux = <&gpc 9 12>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	tcu_pin: tcu-pin {
++		tcu0_pc: tcu0_pc {
++			ingenic,pinmux = <&gpc 0 1>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		tcu1_pc: tcu1_pc {
++			ingenic,pinmux = <&gpc 2 3>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		tcu2_pc: tcu2_pc {
++			ingenic,pinmux = <&gpc 4 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		tcu3_pc: tcu3_pc {
++			ingenic,pinmux = <&gpc 6 7>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		tcu4_pc: tcu4_pc {
++			ingenic,pinmux = <&gpc 8 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		tcu5_pc: tcu5_pc {
++			ingenic,pinmux = <&gpc 10 11>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		tcu5_pe: tcu5_pe {
++			ingenic,pinmux = <&gpe 16 17>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		tcu6_pc: tcu6_pc {
++			ingenic,pinmux = <&gpc 12 13>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		tcu6_pe: tcu6_pe {
++			ingenic,pinmux = <&gpe 18 19>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		tcu7_pc: tcu7_pc {
++			ingenic,pinmux = <&gpc 14 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		tcu7_pe: tcu7_pe {
++			ingenic,pinmux = <&gpe 20 21>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++
++	scc_pc: scc-pc {
++		ingenic,pinmux = <&gpc 3 4>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++	};
++
++	rtc32k_pins:rtc32k-pins {
++		rtc32k_enable:rtc32k-enable {
++			ingenic,pinmux = <&gpe 23 23>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		rtc32k_disable:rtc32k-disable {
++			ingenic,pinmux = <&gpe 23 23>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTIONS>;
++		};
++	};
++};
++
+diff --git a/module_drivers/dts/panda_cameras/RD_X1600_PANDA_CAMERA_3V2.dtsi b/module_drivers/dts/panda_cameras/RD_X1600_PANDA_CAMERA_3V2.dtsi
+new file mode 100644
+index 000000000..7afade42d
+--- /dev/null
++++ b/module_drivers/dts/panda_cameras/RD_X1600_PANDA_CAMERA_3V2.dtsi
+@@ -0,0 +1,38 @@
++&i2c0 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0_pa>;
++
++	/*RD_X2000_HALLEY5_CAMERA_V3.2*/
++	ov4689_0:ov4689@0x21 {
++		status = "okay";
++		compatible = "ovti,ov4689";
++		reg = <0x21>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim_mipi_mclk_pc>;
++
++		reset-gpios = <&gpb 3 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ircutp-gpios = <&gpb 4 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		ircutn-gpios = <&gpb 5 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov4689_ep0:endpoint {
++				remote-endpoint = <&cim_0>;
++			};
++		};
++	};
++};
++
++&cim {
++	status = "okay";
++	port {
++		cim_0: endpoint@0 {
++			remote-endpoint = <&ov4689_ep0>;
++			data-lanes = <0 1>;
++			clk-lanes = <2>;
++		};
++	};
++};
++
+diff --git a/module_drivers/dts/panda_cameras/RD_X1600_PANDA_DVP_CAMERA_1V0.dtsi b/module_drivers/dts/panda_cameras/RD_X1600_PANDA_DVP_CAMERA_1V0.dtsi
+new file mode 100644
+index 000000000..af4c06958
+--- /dev/null
++++ b/module_drivers/dts/panda_cameras/RD_X1600_PANDA_DVP_CAMERA_1V0.dtsi
+@@ -0,0 +1,41 @@
++&i2c0 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0_pa>;
++
++	sc031gs_0:sc031gs@0x30 {
++		status = "okay";
++		compatible = "sc031gs";
++		reg = <0x30>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim_pa>, <&cim_mclk_pa>;
++
++		resetb-gpios = <&gpa 16 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		pwdn-gpios = <&gpa 18 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		vcc-en-gpios = <&gpa 17 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			sc031gs_ep0:endpoint {
++				remote-endpoint = <&cim_0>;
++			};
++		};
++	};
++};
++
++&cim {
++	status = "okay";
++	port {
++		cim_0: endpoint@0 {
++			remote-endpoint = <&sc031gs_ep0>;
++			bus-width = <8>;
++			data-shift = <0>;
++			bus-type = <5>;
++			hsync-active = <1>;
++			vsync-active = <0>;
++			data-active = <1>;
++			pclk-sample = <1>;
++		};
++	};
++};
+diff --git a/module_drivers/dts/panda_cameras/RD_X1600_PANDA_DVP_CAMERA_2V0.dtsi b/module_drivers/dts/panda_cameras/RD_X1600_PANDA_DVP_CAMERA_2V0.dtsi
+new file mode 100644
+index 000000000..cdc63dbe7
+--- /dev/null
++++ b/module_drivers/dts/panda_cameras/RD_X1600_PANDA_DVP_CAMERA_2V0.dtsi
+@@ -0,0 +1,40 @@
++&i2c0 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0_pa>;
++
++	ov9281_0:ov9281@0x60 {
++		status = "okay";
++		compatible = "ovti,ov9281";
++		reg = <0x60>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim_pa>, <&cim_mclk_pa>;
++
++		pwdn-gpios = <&gpa 18 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov9281_ep0:endpoint {
++				remote-endpoint = <&cim_0>;
++			};
++		};
++	};
++};
++
++&cim {
++	status = "okay";
++	port {
++		cim_0: endpoint@0 {
++			remote-endpoint = <&ov9281_ep0>;
++			bus-width = <8>;
++			data-shift = <0>;
++			bus-type = <5>;
++			hsync-active = <1>;
++			vsync-active = <0>;
++			data-active = <1>;
++			pclk-sample = <1>;
++		};
++	};
++};
++
+diff --git a/module_drivers/dts/panda_cameras/RD_X1600_PANDA_DVP_CAMERA_AND_LCD_1V0.dtsi b/module_drivers/dts/panda_cameras/RD_X1600_PANDA_DVP_CAMERA_AND_LCD_1V0.dtsi
+new file mode 100644
+index 000000000..2e0d67be9
+--- /dev/null
++++ b/module_drivers/dts/panda_cameras/RD_X1600_PANDA_DVP_CAMERA_AND_LCD_1V0.dtsi
+@@ -0,0 +1,42 @@
++&i2c0 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0_pa>;
++
++	ov5640_0:ov5640@0x3c {
++		status = "okay";
++		compatible = "ovti,ov5640";
++		reg = <0x3c>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim_pa>, <&cim_mclk_pa>;
++
++		resetb-gpios = <&gpa 16 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		pwdn-gpios = <&gpa 18 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		vcc-en-gpios = <&gpa 17 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov5640_ep0:endpoint {
++				remote-endpoint = <&cim_0>;
++			};
++		};
++	};
++};
++
++&cim {
++	status = "okay";
++	port {
++		cim_0: endpoint@0 {
++			remote-endpoint = <&ov5640_ep0>;
++			bus-width = <8>;
++			data-shift = <0>;
++			bus-type = <5>;
++			hsync-active = <1>;
++			vsync-active = <0>;
++			data-active = <1>;
++			pclk-sample = <1>;
++		       };
++	};
++};
++
+diff --git a/module_drivers/dts/panda_cameras/RD_X1600_PANDA_MIPI_CAMERA_1V0.dtsi b/module_drivers/dts/panda_cameras/RD_X1600_PANDA_MIPI_CAMERA_1V0.dtsi
+new file mode 100644
+index 000000000..e0ef6a75c
+--- /dev/null
++++ b/module_drivers/dts/panda_cameras/RD_X1600_PANDA_MIPI_CAMERA_1V0.dtsi
+@@ -0,0 +1,37 @@
++&i2c0 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0_pa>;
++
++	ov5645:ov5645@0x3c {
++		status = "okay";
++		compatible = "ovti,ov5645";
++		reg = <0x3c>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim_mipi_mclk_pc>;
++
++		resetb-gpios = <&gpb 3 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		pwdn-gpios = <0>;
++		vcc-en-gpios = <&gpb 2 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov5645_ep0:endpoint {
++				remote-endpoint = <&cim_0>;
++			};
++		};
++	};
++};
++
++&cim {
++	status = "okay";
++	port {
++		cim_0: endpoint@0 {
++			remote-endpoint = <&ov5645_ep0>;
++			data-lanes = <1 2>;
++			clk-lanes = <3>;
++		};
++	};
++};
++
+diff --git a/module_drivers/dts/panda_cameras/RD_X1600_PANDA_MIPI_CAMERA_2V0.dtsi b/module_drivers/dts/panda_cameras/RD_X1600_PANDA_MIPI_CAMERA_2V0.dtsi
+new file mode 100644
+index 000000000..3f80c42cf
+--- /dev/null
++++ b/module_drivers/dts/panda_cameras/RD_X1600_PANDA_MIPI_CAMERA_2V0.dtsi
+@@ -0,0 +1,37 @@
++&i2c0 {
++	status = "okay";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0_pa>;
++
++	ov9281:ov9281@0x60 {
++		status = "okay";
++		compatible = "ovti,ov9281";
++		reg = <0x60>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&cim_mipi_mclk_pc>;
++
++		resetb-gpios = <&gpb 3 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		vcc-en-gpios = <0>;
++		pwdn-gpios = <&gpb 2 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++
++		port {
++			ov9281_ep0:endpoint {
++				remote-endpoint = <&cim_0>;
++			};
++		};
++	};
++};
++
++&cim {
++	status = "okay";
++	port {
++		cim_0: endpoint@0 {
++			remote-endpoint = <&ov9281_ep0>;
++			data-lanes = <0>;
++			clk-lanes = <2>;
++		};
++	};
++};
++
+diff --git a/module_drivers/dts/panda_lcd/RD_X1600_IRIS_RGB_LCD_1V0.dtsi b/module_drivers/dts/panda_lcd/RD_X1600_IRIS_RGB_LCD_1V0.dtsi
+new file mode 100644
+index 000000000..22067fba3
+--- /dev/null
++++ b/module_drivers/dts/panda_lcd/RD_X1600_IRIS_RGB_LCD_1V0.dtsi
+@@ -0,0 +1,70 @@
++/ {
++
++	display-dbi {
++		compatible = "simple-bus";
++		#interrupt-cells = <1>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++		panel_tl040wvs03ct {
++			compatible = "ingenic,tl040wvs03ct";
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&tft_lcd_pa_rgb666>;
++			ingenic,vdd-en-gpio = <&gpb 7 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			ingenic,rst-gpio = <&gpa 29 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		//	ingenic,lcd-pwm-gpio = <&gpc 2 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,lcd-sdo-gpio = <&gpa 30 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,lcd-sck-gpio = <&gpa 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,lcd-cs-gpio = <&gpa 28 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			port {
++				panel_tl040wvs03ct_ep: endpoint {
++					   remote-endpoint = <&dpu_out_ep>;
++			   };
++			};
++		};
++	};
++
++
++	backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwm 2 1000000>;
++	    brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
++	    default-brightness-level = <4>;
++    };
++};
++
++/*
++&pwm {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm2_pc>;
++	status = "okay";
++};
++*/
++
++&dpu {
++	port {
++		dpu_out_ep: endpoint {
++		remote-endpoint = <&panel_tl040wvs03ct_ep>;
++	    };
++	};
++};
++
++&i2c0 {
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0_pb>;
++
++	focaltech@0x48{
++		compatible = "focaltech,fts"; /* do not modify */
++		reg = <0x48>; /* do not modify */
++		interrupt-parent = <&gpc>; /* INT pin */
++		interrupts = <9>;
++		focaltech,reset-gpio = <&gpb 5 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>; /* RST pin */
++		focaltech,irq-gpio = <&gpb 4 IRQ_TYPE_EDGE_FALLING INGENIC_GPIO_NOBIAS>; /* INT pin */
++		focaltech,max-touch-number = <2>;
++		focaltech,display-coords = <0 0 480 480>;   /* resolution */
++	};
++
++};
++
+diff --git a/module_drivers/dts/panda_lcd/RD_X1600_PANDA_LCD_AND_DVP_CAMERA_1V0_KD037.dtsi b/module_drivers/dts/panda_lcd/RD_X1600_PANDA_LCD_AND_DVP_CAMERA_1V0_KD037.dtsi
+new file mode 100644
+index 000000000..ae7c30081
+--- /dev/null
++++ b/module_drivers/dts/panda_lcd/RD_X1600_PANDA_LCD_AND_DVP_CAMERA_1V0_KD037.dtsi
+@@ -0,0 +1,36 @@
++/ {
++
++	display-dbi {
++		compatible = "simple-bus";
++		#interrupt-cells = <1>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++		panel_kd035hvfbd037 {
++			compatible = "ingenic,kd035hvfbd037";
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&smart_lcd_pa_16bit>;
++			ingenic,pwm-gpio = <&gpc 2 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			ingenic,cs-gpio = <&gpa 23 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,vddio-en-gpio = <&gpa 20 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			ingenic,vdd-en-gpio = <&gpa 19 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			ingenic,rst-gpio = <&gpa 27 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			port {
++				panel_kd035hvfbd037_ep: endpoint {
++					remote-endpoint = <&dpu_out_ep>;
++				};
++			};
++		};
++	};
++
++};
++
++&dpu {
++	port {
++		dpu_out_ep: endpoint {
++		remote-endpoint = <&panel_kd035hvfbd037_ep>;
++	    };
++	};
++};
++
+diff --git a/module_drivers/dts/panda_lcd/RD_X1600_PANDA_LCD_AND_DVP_CAMERA_1V0_KD057.dtsi b/module_drivers/dts/panda_lcd/RD_X1600_PANDA_LCD_AND_DVP_CAMERA_1V0_KD057.dtsi
+new file mode 100644
+index 000000000..b1259dbc4
+--- /dev/null
++++ b/module_drivers/dts/panda_lcd/RD_X1600_PANDA_LCD_AND_DVP_CAMERA_1V0_KD057.dtsi
+@@ -0,0 +1,36 @@
++/ {
++
++	display-dbi {
++		compatible = "simple-bus";
++		#interrupt-cells = <1>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++		panel_kd035hvfmd057 {
++			compatible = "ingenic,kd035hvfmd057";
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&smart_lcd_pa_16bit>;
++			ingenic,pwm-gpio = <&gpc 2 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			ingenic,cs-gpio = <&gpa 23 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,vddio-en-gpio = <&gpa 20 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			ingenic,vdd-en-gpio = <&gpa 19 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			ingenic,rst-gpio = <&gpa 27 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			port {
++				panel_kd035hvfmd057_ep: endpoint {
++					remote-endpoint = <&dpu_out_ep>;
++				};
++			};
++		};
++	};
++
++};
++
++&dpu {
++	port {
++		dpu_out_ep: endpoint {
++		remote-endpoint = <&panel_kd035hvfmd057_ep>;
++	    };
++	};
++};
++
+diff --git a/module_drivers/dts/panda_lcd/RD_X1600_PANDA_RGB_LCD_1V0.dtsi b/module_drivers/dts/panda_lcd/RD_X1600_PANDA_RGB_LCD_1V0.dtsi
+new file mode 100644
+index 000000000..2b85dc42a
+--- /dev/null
++++ b/module_drivers/dts/panda_lcd/RD_X1600_PANDA_RGB_LCD_1V0.dtsi
+@@ -0,0 +1,124 @@
++/ {
++
++	display-dbi {
++		compatible = "simple-bus";
++		#interrupt-cells = <1>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++		panel_kd050wvfpa029 {
++			compatible = "ingenic,kd050wvfpa029";
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&tft_lcd_pa_rgb888>;
++		/*	ingenic,lcd-pwm-gpio = <&gpc 2 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;*/
++			port {
++				panel_kd050wvfpa029_ep: endpoint {
++					remote-endpoint = <&dpu_out_ep>;
++				};
++			};
++		};
++	};
++
++	backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwm 2 100000>; /* arg1: pwm channel id [0~15]. arg2: period in ns. */
++		brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
++		default-brightness-level = <5>;
++	};
++
++};
++
++&dpu {
++	port {
++		dpu_out_ep: endpoint {
++		remote-endpoint = <&panel_kd050wvfpa029_ep>;
++	    };
++	};
++};
++
++
++&i2c0 {
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	status = "okay";
++	pinctrl-0 = <&i2c0_pa>;
++
++	goodix@0x14{
++		compatible = "goodix,gt9xx"; /* do not modify */
++		reg = <0x14>; /* do not modify */
++		interrupt-parent = <&gpa>; /* INT pin */
++		interrupts = <9>;
++		reset-gpios = <&gpa 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>; /* RST pin */
++		irq-gpios = <&gpa 30 IRQ_TYPE_EDGE_FALLING INGENIC_GPIO_NOBIAS>; /* INT pin */
++		goodix,driver-send-cfg = <1>;
++		touchscreen-size-x = <480>;
++		touchscreen-size-y = <800>;
++		goodix,slide-wakeup = <0>;
++		goodix,type-a-report = <0>;
++		goodix,resume-in-workqueue = <0>;
++		goodix,int-sync = <1>;
++		goodix,swap-x2y = <0>;
++		goodix,auto-update-cfg = <0>;
++		goodix,power-off-sleep = <0>;
++		goodix,pen-suppress-finger = <0>;
++		irq-flags = <2>; /* 1 rising, 2 falling */
++		pinctrl-names = "default", "int-output-high", "int-output-low", "int-input";
++		pinctrl-0 = <&touchscreen_default>;
++		pinctrl-1 = <&touchscreen_int_out_high>;
++		pinctrl-2 = <&touchscreen_int_out_low>;
++		pinctrl-3 = <&touchscreen_int_input>;
++		goodix,cfg-group0 = [
++			42 20 03 E0 01 0A 0D 00
++			01 08 28 05 50 32 03 05
++			00 00 00 00 00 00 00 00
++			00 00 00 87 28 09 17 15
++			31 0D 00 00 00 9A 03 1C
++			00 00 00 00 00 03 64 32
++			00 00 00 0F 23 94 C5 02
++			07 00 00 04 A3 10 00 8B
++			13 00 7A 16 00 66 1B 00
++			58 20 00 58 00 00 00 00
++			00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00
++			02 04 06 08 0A 0C 0E 10
++			12 FF FF FF FF FF FF FF
++			FF FF FF FF FF FF FF FF
++			FF FF FF FF FF FF 00 02
++			04 06 08 0A 0C 1D 1E 1F
++			20 21 22 24 26 FF FF FF
++			FF FF FF FF FF FF FF FF
++			FF FF FF FF FF FF FF FF
++			FF FF FF FF FF FF FF FF
++			4A 01];
++	};
++};
++
++
++&pinctrl {
++
++	touchscreen_pins:touchscreen-pins {
++		touchscreen_int_out_high:touchscreen-int-out-high {
++			ingenic,pinmux = <&gpa 30 30>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCHILVL>;
++		};
++		touchscreen_int_out_low:touchscreen-int-out-low {
++			ingenic,pinmux = <&gpa 30 30>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCLOLVL>;
++		};
++		touchscreen_int_input:touchscreen-int-input {
++			ingenic,pinmux = <&gpa 30 30>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT_FE>;
++		};
++		touchscreen_default:touchscreen-default {
++			ingenic,pinmux = <&gpa 30 30>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT>;
++		};
++	};
++};
++
++
++
++
+diff --git a/module_drivers/dts/panda_lcd/RD_X1600_PANDA_SPI_LCD_1V0.dtsi b/module_drivers/dts/panda_lcd/RD_X1600_PANDA_SPI_LCD_1V0.dtsi
+new file mode 100644
+index 000000000..7a34a3376
+--- /dev/null
++++ b/module_drivers/dts/panda_lcd/RD_X1600_PANDA_SPI_LCD_1V0.dtsi
+@@ -0,0 +1,36 @@
++/ {
++
++	display-dbi {
++		compatible = "simple-bus";
++		#interrupt-cells = <1>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++		panel_gc9203 {
++			compatible = "ingenic,gc9203";
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&smart_lcd_spi>;
++			ingenic,pwm-gpio = <&gpc 2 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			ingenic,cs-gpio = <&gpa 23 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,vddio-en-gpio = <&gpa 20 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			ingenic,vdd-en-gpio = <&gpa 19 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			ingenic,rst-gpio = <&gpa 2 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			port {
++				panel_gc9203_ep: endpoint {
++					remote-endpoint = <&dpu_out_ep>;
++				};
++			};
++		};
++	};
++
++};
++
++&dpu {
++	port {
++		dpu_out_ep: endpoint {
++		remote-endpoint = <&panel_gc9203_ep>;
++	    };
++	};
++};
++
+diff --git a/module_drivers/dts/panda_v10.dts b/module_drivers/dts/panda_v10.dts
+new file mode 100644
+index 000000000..ec1fc85a9
+--- /dev/null
++++ b/module_drivers/dts/panda_v10.dts
+@@ -0,0 +1,423 @@
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include "x1600.dtsi"
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <generated/autoconf.h>
++
++#ifdef CONFIG_RD_X1600_PANDA_MIPI_CAMERA_1V0
++#include "panda_cameras/RD_X1600_PANDA_MIPI_CAMERA_1V0.dtsi"
++#endif
++
++#ifdef CONFIG_RD_X1600_PANDA_MIPI_CAMERA_2V0
++#include "panda_cameras/RD_X1600_PANDA_MIPI_CAMERA_2V0.dtsi"
++#endif
++
++#ifdef CONFIG_RD_X1600_PANDA_MIPI_CAMERA_3V2
++#include "panda_cameras/RD_X1600_PANDA_CAMERA_3V2.dtsi"
++#endif
++
++#ifdef CONFIG_RD_X1600_PANDA_DVP_CAMERA_2V0
++#include "panda_cameras/RD_X1600_PANDA_DVP_CAMERA_2V0.dtsi"
++#endif
++
++#ifdef CONFIG_RD_X1600_PANDA_DVP_CAMERA_AND_LCD_1V0
++#include "panda_cameras/RD_X1600_PANDA_DVP_CAMERA_AND_LCD_1V0.dtsi"
++#endif
++
++#ifdef CONFIG_RD_X1600_PANDA_DVP_CAMERA_1V0
++#include "panda_cameras/RD_X1600_PANDA_DVP_CAMERA_1V0.dtsi"
++#endif
++
++#ifdef CONFIG_STAGE_GC9203
++#include "panda_lcd/RD_X1600_PANDA_SPI_LCD_1V0.dtsi"
++#endif
++
++#ifdef CONFIG_STAGE_KD035HVFBD037
++#include "panda_lcd/RD_X1600_PANDA_LCD_AND_DVP_CAMERA_1V0_KD037.dtsi"
++#endif
++
++#ifdef CONFIG_STAGE_KD035HVFMD057
++#include "panda_lcd/RD_X1600_PANDA_LCD_AND_DVP_CAMERA_1V0_KD057.dtsi"
++#endif
++
++#ifdef CONFIG_STAGE_KD050WVFPA029
++#include "panda_lcd/RD_X1600_PANDA_RGB_LCD_1V0.dtsi"
++#endif
++
++/ {
++	compatible = "ingenic,panda", "ingenic,panda";
++
++	/*chosen {
++		bootargs = "console=ttyS1,115200 mem=128M@0x0ip=off init=/linuxrc ubi.mtd=3 root=ubi0:rootfs ubi.mtd=4 rootfstype=ubifs rw";
++	};*/
++
++
++	reserved-memory {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges =<>;
++
++		reserved_memory: reserved_mem@0x2000000{
++		      compatible = "shared-dma-pool";
++		      reg = <0x02000000 0x2000000>;
++		};
++	};
++
++
++};
++
++&uart0 {
++	status = "disable";
++	/* dma-mode; */
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pb>;
++};
++
++&uart1 {
++	status = "disable";
++	/* dma-mode; */
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pb>;
++};
++
++&uart2 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pb>;
++};
++
++&uart3 {
++	status = "disable";
++};
++
++&cpufreq {
++	status = "okay";
++	operating-points = <
++		/*KHZ uV */
++		1200000	900000
++		750000	900000
++		600000	900000
++		500000	900000
++		400000	900000
++		375000	900000
++		300000	900000
++		200000	900000
++			>;
++
++};
++
++&pdma {
++	status = "okay";
++};
++
++&msc0 {
++	status = "disable";
++	pinctrl-names ="default","enable", "disable";
++	pinctrl-0 = <&msc0_4bit_f0>;
++	pinctrl-1 = <&rtc32k_enable>;
++	pinctrl-2 = <&rtc32k_disable>;
++
++	cap-sd-highspeed;
++	max-frequency = <50000000>;
++	bus-width = <4>;
++	voltage-ranges = <1800 3300>;
++	non-removable;
++
++	ingenic,sdio_clk = <1>;
++	keep-power-in-suspend;
++
++	/* special property */
++	ingenic,sdr-gpios = <0>;
++	ingenic,wp-gpios = <0>;
++	ingenic,cd-gpios = <0>;
++	ingenic,rst-gpios = <0>;
++	ingenic,removal-manual; /*removal-dontcare, removal-nonremovable, removal-removable, removal-manual*/
++
++	bcmdhd_wlan: bcmdhd_wlan {
++		 compatible = "android,bcmdhd_wlan";
++		 ingenic,sdio-irq = <&gpb 4 IRQ_TYPE_LEVEL_HIGH INGENIC_GPIO_NOBIAS>;
++		 ingenic,sdio-reset = <&gpc 28 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++};
++
++&msc1 {
++	status = "okay";
++	pinctrl-names ="default";
++	pinctrl-0 = <&msc1_4bit>;
++	cap-sd-highspeed;
++	max-frequency = <50000000>;
++	bus-width = <4>;
++	voltage-ranges = <1800 3300>;
++	/* special property */
++	ingenic,wp-gpios = <0>;
++	ingneic,cd-gpios = <0>;
++	ingenic,rst-gpios = <0>;
++	ingenic,removal-dontcare; /*removal-dontcare, removal-nonremovable, removal-removable, removal-manual*/
++};
++
++&tcu {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm_tcu_trig_pa>;
++};
++
++&can0 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&can0_pd>;
++	ingenic,clk-freq = <12000000>;
++};
++
++&can1 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&can1_pd>;
++	ingenic,clk-freq = <12000000>;
++};
++
++&cdbus {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&cdbus_pd>, <&cdbus_tx_en>;
++};
++
++&cim {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&aic {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&aic_pb>;
++};
++
++&mac0 {
++	pinctrl-names = "default", "reset";
++	pinctrl-0 = <&mac0_rmii_p0_normal>, <&mac0_rmii_p1_normal>;
++	pinctrl-1 = <&mac0_rmii_p0_rst>, <&mac0_rmii_p1_normal>;
++	status = "disable";
++	ingenic,rst-gpio = <&gpb 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,rst-ms = <10>;
++	ingenic,mac-mode = <RMII>;
++	ingenic,mode-reg = <0xb0000054>;
++	ingenic,phy-clk-freq = <50000000>;
++};
++
++&sfc {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&sfc_pc>;
++	ingenic,sfc-init-frequency = <200000000>;
++	ingenic,sfc-max-frequency = <320000000>;
++	ingenic,use_ofpart_info  = /bits/ 8 <0>;
++	ingenic,spiflash_param_offset = <0>;
++
++	norflash@0 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nor flash partition */
++			uboot@0 {
++				label = "uboot";
++				reg = <0x0000000 0x40000>;
++				/*read-only;*/
++			};
++
++			kernel@40000 {
++				label = "kernel";
++				reg = <0x40000 0x300000>;
++			};
++
++			rootfs@360000 {
++				label = "rootfs";
++				reg = <0x360000 0xca0000>;
++			};
++		};
++	};
++
++	nandflash@1 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nand flash partition */
++			partition@0 {
++				label = "uboot";
++				reg = <0x0000000 0x100000>;
++				/*read-only;*/
++			};
++
++			partition@100000 {
++				label = "kernel";
++				reg = <0x100000 0x800000>;
++			};
++
++			partition@900000 {
++				label = "rootfs";
++				reg = <0x900000 0xf700000>;
++			};
++		};
++	};
++
++};
++
++&i2c1 {
++	status = "disable";
++	clock-frequency = <100000>;
++	timeout = <1000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c1_pb_f0>;
++
++	wm8594: adc@1a {
++		compatible = "wlf,wm8594";
++		status = "okay";
++		reg = <0x1a>;
++		reset-gpios = <&gpb 10 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		mute-gpios = <&gpb 7 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		pwdn-gpios = <&gpb 9 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	};
++};
++
++&spi0 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pb>;
++	spi-max-frequency = <54000000>;
++	num-cs = <2>;
++	/* cs-gpios = <0>, <0>; */
++	/* cs-gpios = <&gpb 17 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>, <&gpb 16 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>; */
++	ingenic,chnl = <0>;
++	ingenic,allow_cs_same = <1>;
++	ingenic,bus_num = <0>;
++	ingenic,has_dma_support = <0>;
++	ingenic,spi-src-clk = <1>;/*0.ext; 1.ssi*/
++
++	/* Add SPI interface device */
++	spidev: spidev@0 {
++		compatible = "rohm,dh2228fv";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++	};
++};
++
++&spi_slv0 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi_slv_pa>;
++	ingenic,has_dma_support = <1>;
++};
++
++&dtrng {
++	status = "okay";
++};
++
++&pwm {
++	pinctrl-names = "default", "pwm7_pb_21";
++	pinctrl-0 = <&pwm2_pc>,
++		<&pwm7_pb_21>;
++	status = "okay";
++};
++
++&otg {
++	g-use-dma;
++	dr_mode = "otg"; // host,peripheral,otg
++	device-using-dma = <1>;
++	status = "okay";
++};
++
++&otg_phy {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&drvvbus_pin>;
++};
++
++&dpu {
++	status = "okay";
++	/*ingenic,disable-rdma-fb = <0>;*/
++};
++
++&efuse {
++	status = "disable";
++	ingenic,efuse-en-gpio = <&gpc 1 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++};
++
++
++/ {
++
++	extclk: extclk {
++		clock-frequency = <24000000>;
++	};
++
++	gpio_keys: gpio_keys {
++		   compatible = "gpio-keys";
++
++		   wakeup {
++			   label = "WAKEUP";
++			   linux,code = <KEY_WAKEUP>;
++			   gpios = <&gpc 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			   gpio-key,wakeup;
++		   };
++
++		   bootsel0 {
++			   label = "bootsel0";
++			   linux,code = <KEY_HOME>;
++			   gpios = <&gpc 27 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		   };
++
++		   bootsel1 {
++			   label = "bootsel1";
++			   linux,code = <KEY_BACK>;
++			   gpios = <&gpc 28 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		   };
++	   };
++
++	/*
++	 * gpc 27 bt wakeup host
++	 */
++	bt_power {
++		compatible = "ingenic,bt_power";
++		ingenic,reg-on-gpio = <&gpb 5 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,wake-gpio = <&gpc 27 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++
++	spi_gpio {
++		status = "disable";
++	};
++
++#ifdef CONFIG_LINUX_PMEM
++	linux_pmem {
++		status = "okay";
++		compatible = "linux_pmem";
++		linux_pmem,name = "pmem";
++		linux_pmem,no_allocator = <0>;
++		linux_pmem,cached       = <1>;
++		linux_pmem,start        = <0>;
++		linux_pmem,size         = CONFIG_PMEM_RESERVE_SIZE;
++    };
++#endif
++
++	dump_pcm_codec:dump_pcm_codec{
++		compatible = "ingenic,pcm-dump-codec";
++		status = "disable";
++	};
++
++	sound_panda_ecdc {
++		status = "disable";
++		compatible = "ingenic,x1600-sound";
++		ingenic,model = "panda";
++		ingenic,dai-link = "i2s-ecodec", "i2s-tloop";
++		ingenic,stream = "i2s-ecodec", "i2s-tloop";
++		ingenic,cpu-dai = <&i2s>, <&i2s_tloop>;
++		ingenic,platform = <&aic>, <&i2s_tloop>;
++		ingenic,codec = <&wm8594>, <&dump_pcm_codec>;
++		ingenic,codec-dai = "wm8594-hifi", "pcm-dump";
++		en3v3-gpios = <&gpb 13 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++		en9v-gpios = <&gpb 12 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	};
++};
++
+diff --git a/module_drivers/dts/viomi_v2000.dts b/module_drivers/dts/viomi_v2000.dts
+new file mode 100644
+index 000000000..6a9790224
+--- /dev/null
++++ b/module_drivers/dts/viomi_v2000.dts
+@@ -0,0 +1,583 @@
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include "x2000.dtsi"
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <generated/autoconf.h>
++
++
++/ {
++	compatible = "ingenic,viomi_v2000", "ingenic,x2000";
++
++	/*chosen {
++		bootargs = "console=ttyS1,115200 mem=128M@0x0ip=off init=/linuxrc ubi.mtd=3 root=ubi0:rootfs ubi.mtd=4 rootfstype=ubifs rw";
++	};*/
++
++	reserved-memory {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges =<>;
++
++		reserved_memory: reserved_mem@0x6000000{
++		      compatible = "shared-dma-pool";
++		      reg = <0x06000000 0x2000000>;
++		};
++	};
++
++		  cam_avdd: cam_regulator_avdd {
++			  compatible = "regulator-fixed";
++			  regulator-name = "cam_avdd";
++			  regulator-min-microvolt = <2800000>;
++			  regulator-max-microvolt = <2800000>;
++			  regulator-always-on;
++			  regulator-boot-on;
++		  };
++		  cam_dvdd: cam_regulator_dvdd {
++			  compatible = "regulator-fixed";
++			  regulator-name = "cam_dvdd";
++			  regulator-min-microvolt = <1200000>;
++			  regulator-max-microvolt = <1200000>;
++			  regulator-always-on;
++			  regulator-boot-on;
++		  };
++		  cam_dovdd: cam_regulator_dovdd {
++			   compatible = "regulator-fixed";
++			   regulator-name = "cam_dovdd";
++			   regulator-min-microvolt = <1800000>;
++			   regulator-max-microvolt = <1800000>;
++			   regulator-always-on;
++			   regulator-boot-on;
++		  };
++};
++
++&uart0 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pd>;
++};
++
++&uart1 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pc>;
++};
++
++&uart2 {
++	status = "disable";
++};
++
++&uart3 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pc>;
++};
++
++&uart9 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart9_pb>;
++};
++
++
++&cpufreq {
++	status = "okay";
++	operating-points = <
++		/*KHZ uV */
++		1200000	900000
++		1000000	900000
++		750000	900000
++		600000	900000
++		500000	900000
++		400000	900000
++		375000	900000
++		300000	900000
++		200000	900000
++			>;
++
++};
++
++&pinctrl {
++	ingenic,gpa_voltage = <GPIO_VOLTAGE_1V8>;
++};
++
++&pinctrl {
++	touchscreen_pins:touchscreen-pins {
++		touchscreen_int_out_high:touchscreen-int-out-high {
++			ingenic,pinmux = <&gpc 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCHILVL>;
++		};
++		touchscreen_int_out_low:touchscreen-int-out-low {
++			ingenic,pinmux = <&gpc 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCLOLVL>;
++		};
++		touchscreen_int_input:touchscreen-int-input {
++			ingenic,pinmux = <&gpc 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT_FE>;
++		};
++		touchscreen_default:touchscreen-default {
++			ingenic,pinmux = <&gpc 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT>;
++		};
++	};
++};
++
++&i2c0 {
++	status = "disable";
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0_pc>;
++
++	goodix@14{
++		compatible = "goodix,gt9xx"; /* do not modify */
++		reg = <0x14>; /* do not modify */
++		reset-gpios = <&gpc 8 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>; /* RST pin */
++		irq-gpios = <&gpc 9 IRQ_TYPE_EDGE_FALLING INGENIC_GPIO_NOBIAS>; /* INT pin */
++		goodix,driver-send-cfg = <1>;
++		touchscreen-size-x = <1280>;
++		touchscreen-size-y = <720>;
++		goodix,slide-wakeup = <0>;
++		goodix,type-a-report = <0>;
++		goodix,resume-in-workqueue = <0>;
++		goodix,int-sync = <1>;
++		goodix,swap-x2y = <0>;
++		goodix,auto-update-cfg = <0>;
++		goodix,power-off-sleep = <0>;
++		goodix,pen-suppress-finger = <0>;
++		irq-flags = <2>; /* 1 rising, 2 falling */
++		pinctrl-names = "default", "int-output-high", "int-output-low", "int-input";
++		pinctrl-0 = <&touchscreen_default>;
++		pinctrl-1 = <&touchscreen_int_out_high>;
++		pinctrl-2 = <&touchscreen_int_out_low>;
++		pinctrl-3 = <&touchscreen_int_input>;
++		goodix,cfg-group0 = [
++			00 D0 02 00 05 0A 05 00 01 08 28
++			05 50 32 03 05 00 00 00 00 00 00
++			00 00 00 00 00 87 28 09 17 15 31
++			0D 00 00 02 9B 03 25 00 00 00 00
++			00 03 64 32 00 00 00 0F 36 94 C5
++			02 07 00 00 04 9B 11 00 7B 16 00
++			64 1C 00 50 25 00 42 2F 00 42 00
++			00 00 00 00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 00 00 00
++			00 00 12 10 0E 0C 0A 08 06 04 02
++			FF FF FF FF FF 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 00 00 26
++			24 22 21 20 1F 1E 1D 00 02 04 06
++			08 0A 0C FF FF FF FF FF FF FF FF
++			FF FF FF 00 00 00 00 00 00 00 00
++			00 00 00 00 00 00 00 00 CF 01];
++	};
++
++};
++
++&i2c1 {
++	status = "disable";
++};
++
++&i2c2 {
++	status = "disable";
++};
++
++&i2c3 {
++	status = "okay";
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa>;
++};
++
++&i2c4 {
++	status = "okay";
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c4_pc>;
++};
++
++&i2c5 {
++	status = "okay";
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c5_pc>;
++};
++
++&felix {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&helix {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&ispcam0 {
++	status = "disable";
++	memory-region=<&reserved_memory>;
++};
++
++&ispcam1 {
++	status = "disable";
++	memory-region=<&reserved_memory>;
++};
++
++&rotate {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&pdma {
++	status = "okay";
++};
++
++&msc0 {
++	status = "okay";
++	/*mmc-hs200-1_8v;*/
++	cap-mmc-highspeed;
++	non-removable;
++	max-frequency = <50000000>;
++	bus-width = <4>;
++	non-removable;
++	voltage-ranges = <1800 3300>;
++
++	/* special property */
++	ingenic,rst-gpios = <0>;
++};
++
++&msc1 {
++	status = "okay";
++	pinctrl-names ="default","enable", "disable";
++	pinctrl-0 = <&msc1_4bit>;
++	pinctrl-1 = <&rtc32k_enable>;
++	pinctrl-2 = <&rtc32k_disable>;
++
++	sd-uhs-sdr104;
++	max-frequency = <100000000>;
++	bus-width = <4>;
++	voltage-ranges = <1800 3300>;
++	non-removable;
++
++	ingenic,sdio_clk = <1>;
++	keep-power-in-suspend;
++
++	/* special property */
++	ingenic,sdr-gpios = <0>;
++	ingenic,rst-gpios = <0>;
++	ingenic,removal-manual; /*removal-dontcare, removal-nonremovable, removal-removable, removal-manual*/
++
++    rtl8723ds: rtl8723ds {
++               compatible = "rtk,rtl8723ds_wlan";
++               ingenic,sdio-irq = <&gpe 24 IRQ_TYPE_LEVEL_HIGH INGENIC_GPIO_NOBIAS>;
++               ingenic,sdio-reset = <&gpd 30 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++               /*ingenic,sdio-btreg = <&gpd 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;*/
++           };
++
++};
++
++&msc2 {
++	status = "okay";
++	pinctrl-names ="default";
++	pinctrl-0 = <&msc2_4bit>;
++	sd-uhs-sdr104;
++	/*cap-mmc-highspeed;*/
++	max-frequency = <200000000>;
++	bus-width = <4>;
++	voltage-ranges = <1800 3300>;
++
++	/* special property */
++	cd-gpios = <&gpc 12 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	wp-gpios = <0>;
++	ingenic,sdr-gpios = <&gpc 0 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	ingenic,rst-gpios = <0>;
++};
++
++
++&mac1 {
++	pinctrl-names = "default", "reset";
++	pinctrl-0 = <&mac1_rgmii_p0_normal>, <&mac1_rgmii_p1_normal>;
++	pinctrl-1 = <&mac1_rgmii_p0_rst>, <&mac1_rgmii_p1_normal>;
++	status = "disable";
++	ingenic,rst-gpio = <&gpb 16 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,rst-ms = <10>;
++	ingenic,rst-delay-ms = <15>;
++	ingenic,mac-mode = <RGMII>;
++	ingenic,mode-reg = <0xb00000e8>;
++	ingenic,rx-clk-delay = <0x0>;
++	ingenic,tx-clk-delay = <0x3f>;
++	/*force mac mode*/
++	/*
++	ingenic,mac-force = <MAC_ON>;
++	ingenic,mac-autoneg = <MAC_ON>;
++	ingenic,mac-speed = <MAC_SPEED_1000M>;
++	ingenic,mac-duplex = <MAC_DUPLEX_HALF>;
++	ingenic,no_phy_connect;
++	*/
++};
++
++&sfc {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&sfc_pe>;
++	ingenic,sfc-init-frequency = <200000000>;
++	ingenic,sfc-max-frequency = <320000000>;
++	ingenic,use_ofpart_info  = /bits/ 8 <0>;
++	ingenic,spiflash_param_offset = <0>;
++
++	norflash@0 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nor flash partition */
++			uboot@0 {
++				label = "uboot";
++				reg = <0x0000000 0x40000>;
++				/*read-only;*/
++			};
++
++			kernel@40000 {
++				label = "kernel";
++				reg = <0x40000 0x300000>;
++			};
++
++			rootfs@360000 {
++				label = "rootfs";
++				reg = <0x360000 0xca0000>;
++			};
++		};
++	};
++
++	nandflash@1 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nand flash partition */
++			partition@0 {
++				label = "uboot";
++				reg = <0x0000000 0x100000>;
++				/*read-only;*/
++			};
++
++			partition@100000 {
++				label = "kernel";
++				reg = <0x100000 0x800000>;
++			};
++
++			partition@900000 {
++				label = "rootfs";
++				reg = <0x900000 0xf700000>;
++			};
++		};
++	};
++
++};
++
++&spi0 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pb>;
++
++	spi-max-frequency = <54000000>;
++	num-cs = <2>;
++	cs-gpios = <0>, <0>;
++	/*cs-gpios = <&gpa 27 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>, <&gpa 27 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;*/
++	ingenic,chnl = <0>;
++	ingenic,allow_cs_same = <1>;
++	ingenic,bus_num = <0>;
++	ingenic,has_dma_support = <0>;
++	ingenic,spi-src-clk = <1>;/*0.ext; 1.ssi*/
++
++	/* Add SPI interface device */
++	spidev: spidev@0 {
++		compatible = "rohm,dh2228fv";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++	};
++};
++
++&dtrng {
++	status = "okay";
++};
++
++&pwm {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm1_pc>;
++};
++
++&otg {
++	g-use-dma;
++	dr_mode = "otg";
++	device-using-dma = <1>;
++	status = "okay";
++};
++
++&otg_phy {
++	dr_mode = "otg";
++	status = "okay";
++	ingenic,id-dete-gpio = <&gpb 19 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	/*ingenic,vbus-dete-gpio = <&gpd 17 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;*/
++	/*ingenic,drvvbus-gpio = <&gpe 22 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;*/
++};
++
++&as_be_baic {
++	pinctrl-names = "default";
++	pinctrl-0 =  <&baic4_pd>;
++};
++
++&as_dmic {
++	pinctrl-names = "default";
++	pinctrl-0 = <&dmic_pc_4ch>;
++};
++
++&icodec {
++	ingenic,spken-gpio = <&gpb 2 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++};
++
++&dpu {
++	status = "disable";
++	ingenic,disable-rdma-fb = <1>;
++	/*Defines the init state of composer fb export infomations.*/
++	ingenic,layer-exported = <1 1 0 0>;
++	ingenic,layer-frames   = <3 3 1 2>;
++	ingenic,layer-framesize = <720 1280>, <720 1280>, <720 1280>, <320 240>;   //Max framesize for each layer.
++	layer,color_mode	= <1 6 0 0>;					//src fmt
++	layer,src-size       	= <720 1280>, <640 480>, <720 1280>, <240 200>;	//Layer src size should smaller than framesize
++	layer,target-size	= <720 1280>, <720 640>, <720 1280>, <240 200>;	//Target Size should smaller than src_size.
++	layer,target-pos	= <0 0>, <0 320>, <0 0>, <100 980>;	//target pos , the start point of the target panel.
++	layer,enable		= <1 0 0 0>;					//layer enabled or disabled.
++	ingenic,logo-pan-layer	= <0>;						//on which layer should init logo pan on.
++	memory-region=<&reserved_memory>;
++	port {
++		dpu_out_ep: endpoint {
++			remote-endpoint = <&panel_kd050hdfia020_ep>;
++	    };
++	};
++};
++
++
++/ {
++
++	extclk: extclk {
++		clock-frequency = <24000000>;
++	};
++
++	gpio_keys: gpio_keys {
++		   compatible = "gpio-keys";
++
++		   power {
++			   label = "Power";
++			   linux,code = <KEY_POWER>;
++			   gpios = <&gpe 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			   gpio-key,wakeup;
++		   };
++	   };
++
++	/*
++	 * gpd 21 bt wakeup host
++	 * gpd 22 host wakeup bt
++	 */
++	bt_power {
++		compatible = "ingenic,bt_power";
++		ingenic,reg-on-gpio = <&gpd 20 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,wake-gpio = <&gpd 21 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++
++	sound {
++		compatible = "ingenic,x2000-sound";
++		ingenic,model = "halley5_v30";
++		ingenic,spken-gpio = <&gpb 2 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	};
++
++    watchdog {
++        compatible = "sgm820-wdt";
++        ingenic,sgm820-wdi = <&gpc 1 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++    };
++
++
++	display-dbi {
++		compatible = "simple-bus";
++		#interrupt-cells = <1>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++		panel_kd050hdfia020 {
++			compatible = "ingenic,kd050hdfia020";
++			status = "okay";
++			pinctrl-names = "default";
++			ingenic,vdd-en-gpio = <&gpc 3 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,rst-gpio = <&gpc 4 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		/*	ingenic,lcd-pwm-gpio = <&gpc 1 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;*/
++			port {
++				panel_kd050hdfia020_ep: endpoint {
++					remote-endpoint = <&dpu_out_ep>;
++				};
++			};
++		};
++	};
++	backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwm 1 1000000>;
++		brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
++		default-brightness-level = <4>;
++	};
++
++
++	spi_gpio {
++		status = "disable";
++		compatible = "spi-gpio";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		gpio-sck = <&gpb 28 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		gpio-miso = <&gpb 29 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		gpio-mosi = <&gpb 30 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		cs-gpios = <&gpb 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		num-chipselects = <1>;
++
++		/* clients */
++		spidev1: spidev1@0 {
++			status = "disable";
++			compatible = "rohm,dh2228fv";
++			reg = <0>;
++			spi-max-frequency = <500000>;
++		};
++	};
++};
++
++
++/* Board Sleep GPIO configuration. */
++/* <0 1 2 3 .... 31>, set one of the pin to state.*/
++&gpa {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpb {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpc {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpd {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
+diff --git a/module_drivers/dts/x1600-pinctrl.dtsi b/module_drivers/dts/x1600-pinctrl.dtsi
+new file mode 100644
+index 000000000..a4cc05d24
+--- /dev/null
++++ b/module_drivers/dts/x1600-pinctrl.dtsi
+@@ -0,0 +1,380 @@
++#include <dt-bindings/pinctrl/ingenic-pinctrl.h>
++
++&pinctrl {
++
++	uart0_pin: uart0-pin {
++		uart0_pb: uart0-pb {
++			ingenic,pinmux = <&gpb 7 10>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++	uart1_pin: uart1-pin {
++		uart1_pb: uart1-pb {
++			ingenic,pinmux = <&gpb 2 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++
++	uart2_pin: uart2-pin {
++		uart2_pa: uart2-pa {
++			ingenic,pinmux = <&gpa 30 31>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		uart2_pb: uart2-pb {
++			ingenic,pinmux = <&gpb 0 1>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++
++	uart3_pin: uart3-pin {
++		uart3_pb: uart3-pb {
++			ingenic,pinmux = <&gpb 4 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		uart3_pd: uart3-pd {
++			ingenic,pinmux = <&gpd 4 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	i2c0_pin: i2c0-pin {
++		i2c0_pa: i2c0-pa {
++			ingenic,pinmux = <&gpa 28 29>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		i2c0_pb: i2c0-pb {
++			ingenic,pinmux = <&gpb 30 31>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	i2c1_pin: i2c1-pin {
++		i2c1_pb_f2: i2c1-pb_f2 {
++			ingenic,pinmux = <&gpb 15 16>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		i2c1_pb_f0: i2c1-pb_f0 {
++			ingenic,pinmux = <&gpb 19 20>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++	msc0_pin: msc0-pin {
++		msc0_4bit_f0: msc0-4bit_f0 {
++			ingenic,pinmux = <&gpb 12 17>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		msc0_4bit_f1: msc0-4bit_f1 {
++			ingenic,pinmux = <&gpc 17 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++	msc1_pin: msc1-pin {
++		msc1_4bit: msc1-4bit {
++			ingenic,pinmux = <&gpd 0 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++
++	};
++
++	can0_pin: can0_pin {
++		can0_pd: can0_pd {
++			ingenic,pinmux = <&gpd 2 3>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++
++	can1_pin: can1_pin {
++		can1_pd: can1_pd {
++			ingenic,pinmux = <&gpd 4 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++
++	cdbus_pin: cdbus_pin {
++		cdbus_pd: cdbus_pd {
++			ingenic,pinmux = <&gpd 0 1>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		cdbus_tx_en: cdbus_tx_en {
++			ingenic,pinmux = <&gpb 30 30>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++
++	mac0_phy_clk: mac0-phy-clk {
++		ingenic,pinmux = <&gpb 22 22>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++	};
++
++	mac0_rmii_p0: mac0-rmii-p0 {
++		mac0_rmii_p0_normal: mac0-rmii-normal {
++			ingenic,pinmux = <&gpb 19 20>, <&gpb 23 24>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		mac0_rmii_p0_rst: mac0-rmii-p0-rst {
++			ingenic,pinmux = <&gpb 19 20>, <&gpb 23 24>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++	mac0_rmii_p1: mac0-rmii-p1 {
++		mac0_rmii_p1_normal: mac0-rmii-p1-normal {
++			ingenic,pinmux = <&gpb 21 21>, <&gpb 25 28>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++
++		mac0_rmii_p1_nomdio: mac0-rmii-p1-nomdio {
++			ingenic,pinmux = <&gpb 21 21>, <&gpb 25 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++
++	pwm_pin: pwm-pin {
++		pwm0_pc: pwm0_pc {
++			ingenic,pinmux = <&gpc 0 0>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++
++		pwm1_pc: pwm1_pc {
++			ingenic,pinmux = <&gpc 1 1>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++
++		pwm2_pc: pwm2_pc {
++			ingenic,pinmux = <&gpc 2 2>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++
++		pwm3_pc: pwm3_pc {
++			ingenic,pinmux = <&gpc 24 24>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++
++		pwm4_pc: pwm4_pc {
++			ingenic,pinmux = <&gpc 25 25>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++
++		pwm5_pc: pwm5_pc {
++			ingenic,pinmux = <&gpc 26 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++
++		pwm5_pb: pwm5_pb {
++			ingenic,pinmux = <&gpb 19 19>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++
++		pwm6_pb_9: pwm6_pb_9 {
++			ingenic,pinmux = <&gpb 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++
++		pwm6_pb_20: pwm6_pb_20 {
++			ingenic,pinmux = <&gpb 20 20>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++
++		pwm7_pb_10: pwm7_pb_10 {
++			ingenic,pinmux = <&gpb 10 10>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++
++		pwm7_pb_21: pwm7_pb_21 {
++			ingenic,pinmux = <&gpb 21 21>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	 };
++
++	sfc_pin: sfc-pin {
++		sfc_ce1_pb_4: sfc_ce1_pb4 {
++			ingenic,pinmux = <&gpb 4 4>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++
++		sfc_ce1_pb_31: sfc_ce1_pb31 {
++			ingenic,pinmux = <&gpb 31 31>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		sfc_pc: sfc-pc {
++			ingenic,pinmux = <&gpc 17 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	cim_pin: cim-pin {
++		cim_pa: cim-pa {
++			ingenic,pinmux = <&gpa 8 15>, <&gpa 19 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	 };
++
++	cim_mclk: cim-mclk {
++		cim_mclk_pa: cim-mclk-pa {
++			ingenic,pinmux = <&gpa 24 24>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	cim_mipi_mclk: cim-mipi-mclk {
++		cim_mipi_mclk_pc: cim-mipi-mclk-pc {
++			ingenic,pinmux = <&gpc 25 25>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	lcd_pins: lcd-pins {
++		tft_lcd_pa_rgb888: tft-lcd-pa-rgb888 {
++			ingenic,pinmux = <&gpa 0 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++
++		tft_lcd_pa_rgb666: tft-lcd-pa-rgb666 {
++			ingenic,pinmux = <&gpa 0 17>, <&gpa 24 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++
++		tft_lcd_pa_rgb565: tft-lcd-pa-rgb565 {
++			ingenic,pinmux = <&gpa 0 15>, <&gpa 24 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++
++		smart_lcd_pa_16bit: smart-lcd-pa-16bit {
++			ingenic,pinmux = <&gpa 0 15>, <&gpa 25 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		smart_lcd_pa_9bit: smart-lcd-pa-9bit {
++			ingenic,pinmux = <&gpa 0 8>, <&gpa 25 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		smart_lcd_pa_8bit: smart-lcd-pa-8bit {
++			ingenic,pinmux = <&gpa 0 7>, <&gpa 25 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		smart_lcd_spi: smart-lcd-pa-spi {
++			ingenic,pinmux = <&gpa 0 0>, <&gpa 25 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		smart_lcd_pa_te: smart-lcd-pa-te {
++			ingenic,pinmux = <&gpa 27 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++	fw040_pins:fw040-pins {
++		fw040_sck_out_high:fw040-sck-out-high {
++			ingenic,pinmux = <&gpb 15 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCHILVL>;
++		};
++		fw040_sck_out_low:fw040-sck-out-low {
++			ingenic,pinmux = <&gpb 15 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCLOLVL>;
++		};
++		fw040_sda_out_high:fw040-sda-out-high {
++			ingenic,pinmux = <&gpb 16 16>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCHILVL>;
++		};
++		fw040_sda_out_low:fw040-sda-out-low {
++			ingenic,pinmux = <&gpb 16 16>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCLOLVL>;
++		};
++	};
++
++	aic_pb: aic-pb {
++		ingenic,pinmux = <&gpb 21 28>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++	};
++
++	spi0_pa: spi0-pa {
++		ingenic,pinmux = <&gpa 28 31>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++	};
++
++	spi0_pb: spi0-pb {
++		ingenic,pinmux = <&gpb 12 14>, <&gpb 16 17>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++	};
++
++	spi_slv_pa: spi_slv-pa {
++		ingenic,pinmux = <&gpa 28 31>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++	};
++
++	spi_slv_pb: spi_slv-pb {
++		ingenic,pinmux = <&gpb 12 14>, <&gpb 17 17>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	pwm_tcu_trig_pa: pwm_tcu_trig_pa {
++		ingenic,pinmux = <&gpa 31 31>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++	};
++
++	pwm_tcu_trig_pb: pwm_tcu_trig_pb {
++		ingenic,pinmux = <&gpb 3 3>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	tcu_pin: tcu-pin {
++		tcu0_pa: tcu0_pc {
++			ingenic,pinmux = <&gpa 0 1>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++
++		tcu1_pa: tcu1_pc {
++			ingenic,pinmux = <&gpa 2 3>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++
++		tcu2_pa: tcu2_pc {
++			ingenic,pinmux = <&gpa 4 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++
++		tcu3_pa: tcu3_pc {
++			ingenic,pinmux = <&gpa 6 7>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++
++		tcu4_pc: tcu4_pc {
++			ingenic,pinmux = <&gpc 0 1>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++
++		tcu5_pc_in0: tcu5_pc_in0 {
++			ingenic,pinmux = <&gpc 2 2>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++
++		tcu5_pc_in1: tcu5_pc_in1 {
++			ingenic,pinmux = <&gpc 24 24>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++
++		tcu6_pc: tcu6_pc {
++			ingenic,pinmux = <&gpb 25 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++
++		tcu7_pb: tcu7_pb {
++			ingenic,pinmux = <&gpb 9 10>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	rtc32k_pins:rtc32k-pins {
++		rtc32k_enable:rtc32k-enable {
++			ingenic,pinmux = <&gpc 26 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		rtc32k_disable:rtc32k-disable {
++			ingenic,pinmux = <&gpc 26 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTIONS>;
++		};
++	};
++
++	drvvbus_pin: drvvbus-pin {
++		ingenic,pinmux = <&gpc 24 24>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++	};
++
++};
++
+diff --git a/module_drivers/dts/x1600.dtsi b/module_drivers/dts/x1600.dtsi
+new file mode 100644
+index 000000000..c5ddba08d
+--- /dev/null
++++ b/module_drivers/dts/x1600.dtsi
+@@ -0,0 +1,523 @@
++#include <dt-bindings/interrupt-controller/x1600-irq.h>
++#include <dt-bindings/clock/ingenic-tcu.h>
++#include <dt-bindings/clock/ingenic-x1600.h>
++#include <dt-bindings/sound/ingenic-baic.h>
++#include <dt-bindings/gpio/ingenic-gpio.h>
++#include <dt-bindings/net/ingenic_gmac.h>
++#include <dt-bindings/dma/ingenic-pdma.h>
++#include <generated/autoconf.h>
++
++/ {
++	#address-cells = <1>;
++	#size-cells = <1>;
++	compatible = "ingenic,x1600";
++
++	aliases: aliases {
++		i2c0 = &i2c0;
++		i2c1 = &i2c1;
++		uart0 = &uart0;
++		uart1 = &uart1;
++		uart2 = &uart2;
++		uart3 = &uart3;
++		mmc0 = &msc0;
++		mmc1 = &msc1;
++		mac0 = &mac0;
++		spi0 = &spi0;
++		spi_slv0 = &spi_slv0;
++		pwm = &pwm;
++		can0 = &can0;
++		can1 = &can1;
++	};
++
++	cpus: cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		cpu0: cpu@0 {
++			device_type = "cpu";
++			compatible = "ingenic,xburst";
++			reg = <0x000>;
++			clock-frequency = <800000000>;
++		};
++
++	};
++
++	cpufreq: cpufreq-dt {
++		 compatible = "ingenic,x1600-cpufreq";
++		 status = "okay";
++	};
++
++	cpuintc: interrupt-controller {
++		#address-cells = <0>;
++		#interrupt-cells = <1>;
++		interrupt-controller;
++		compatible = "mti,cpu-interrupt-controller";
++
++	};
++
++	core_intc: core-intc@0x10001000 {
++		compatible = "ingenic,ingenic-intc";
++		reg = <0x10001000 0x100>;
++		interrupt-controller;
++		#interrupt-cells = <1>;
++		interrupt-parent = <&cpuintc>;
++		interrupts = <CORE_INTC_IRQ>;
++		interrupt-names ="intc";
++	};
++
++	core_ost: core-ost@0x12000000 {
++		compatible = "ingenic,x1600-ost";
++		reg = <0x12000000 0x100>;
++		interrupt-parent = <&cpuintc>;
++		interrupt-names = "sys_ost";
++		interrupts = <CORE_SYS_OST_IRQ>;
++	};
++
++
++	extclk: extclk {
++		compatible = "ingenic,fixed-clock";
++		clock-output-names ="ext";
++		#clock-cells = <0>;
++		clock-frequency  = <24000000>;
++	};
++
++	rtcclk: rtcclk {
++		compatible = "ingenic,fixed-clock";
++		clock-output-names ="rtc_ext";
++		#clock-cells = <0>;
++		clock-frequency = <32768>;
++	};
++
++	apb {
++		compatible = "simple-bus";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++
++		clock: clock-controller@0x10000000 {
++			compatible = "ingenic,x1600-clocks";
++			reg = <0x10000000 0x100>;
++			clocks = <&extclk>, <&rtcclk>;
++			clock-names = "ext", "rtc_ext";
++			#clock-cells = <1>;
++			little-endian;
++		};
++
++		sadc: sadc@10070000 {
++			compatible = "ingenic,x1600-sadc";
++			reg = <0x10070000 0x32>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_SADC>;
++			interrupt-controller;
++			status = "ok";
++		};
++
++		tcu: tcu@0x10002000 {
++			compatible = "ingenic,tcu";
++			reg = <0x10002000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupt-names = "default";
++			interrupts = <IRQ_TCU0 IRQ_TCU1>;
++			status = "ok";
++		};
++
++		watchdog: watchdog@0x10002000 {
++			compatible = "ingenic,watchdog";
++			reg = <0x10002000 0x40>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_TCU0>;
++			status = "ok";
++		};
++
++		rtc: rtc@0x10003000 {
++			compatible = "ingenic,rtc-x1600";
++			reg = <0x10003000 0x4c>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_RTC>;
++			system-power-controller;
++			power-on-press-ms = <1000>;
++			status = "ok";
++		};
++
++		pinctrl: pinctrl@0x10010000 {
++			compatible = "ingenic,x1600-pinctrl";
++			reg = <0x10010000 0x1000>;
++			ingenic,num-chips = <4>;
++			ingenic,regs-offset = <0x100>;
++
++			gpa: gpa {
++				gpio-controller;
++				#gpio-cells = <3>;
++				#ingenic,pincfg-cells = <3>;
++				#ingenic,pinmux-cells = <2>;
++				interrupts = <IRQ_GPIO0>;
++				interrupt-parent = <&core_intc>;
++#ifndef CONFIG_DISABLE_GPIOA_IRQ_CONTROLLER
++				interrupt-controller;
++#endif
++				#interrupt-cells = <3>;
++				ingenic,pull-bitmap = <0xffffffff>;
++			};
++
++			gpb: gpb {
++				gpio-controller;
++				#gpio-cells = <3>;
++				#ingenic,pincfg-cells = <3>;
++				#ingenic,pinmux-cells = <2>;
++				interrupts = <IRQ_GPIO1>;
++				interrupt-parent = <&core_intc>;
++#ifndef CONFIG_DISABLE_GPIOB_IRQ_CONTROLLER
++				interrupt-controller;
++#endif
++				#interrupt-cells = <3>;
++				ingenic,pull-bitmap = <0xffffffff>;
++			};
++
++			gpc: gpc {
++				gpio-controller;
++				#gpio-cells = <3>;
++				#ingenic,pincfg-cells = <3>;
++				#ingenic,pinmux-cells = <2>;
++				interrupts = <IRQ_GPIO2>;
++				interrupt-parent = <&core_intc>;
++#ifndef CONFIG_DISABLE_GPIOC_IRQ_CONTROLLER
++				interrupt-controller;
++#endif
++				#interrupt-cells = <3>;
++				ingenic,pull-bitmap = <0xffffffff>;
++			};
++
++			gpd: gpd {
++				gpio-controller;
++				#gpio-cells = <3>;
++				#ingenic,pincfg-cells = <3>;
++				#ingenic,pinmux-cells = <2>;
++				interrupts = <IRQ_GPIO3>;
++				interrupt-parent = <&core_intc>;
++#ifndef CONFIG_DISABLE_GPIOD_IRQ_CONTROLLER
++				interrupt-controller;
++#endif
++				#interrupt-cells = <3>;
++				ingenic,pull-bitmap = <0xffffffff>;
++			};
++
++		};
++
++		uart0: serial@0x10030000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10030000 0x100>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART0>;
++			clocks = <&extclk 0>;
++			clock-names = "uart0";
++			dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_UART0_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_UART0_RX)>;
++			dma-names = "tx", "rx";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		uart1: serial@0x10031000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10031000 0x100>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART1>;
++			dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_UART1_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_UART1_RX)>;
++			dma-names = "tx", "rx";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		uart2: serial@0x10032000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10032000 0x100>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART2>;
++			dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_UART2_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_UART2_RX)>;
++			dma-names = "tx", "rx";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		uart3: serial@0x10033000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10033000 0x100>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART3>;
++			dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_UART3_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_UART3_RX)>;
++			dma-names = "tx", "rx";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		i2c0: i2c@0x10050000 {
++			compatible = "ingenic,x1600-i2c";
++			reg = <0x10050000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_I2C0>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "okay";
++		};
++
++		i2c1: i2c@0x10051000 {
++			compatible = "ingenic,x1600-i2c";
++			reg = <0x10051000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_I2C1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		spi0: spi@0x10043000 {
++			compatible = "ingenic,x1600-spi";
++			reg = <0x10043000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_SSI0>;
++			dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_SSI0_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_SSI0_RX)>;
++			dma-names = "tx", "rx";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++		spi_slv0: slv@0x10045000 {
++			compatible = "ingenic,slv";
++			reg = <0x10045000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_SSI_SLV>;
++			dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_SLV0_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_SLV0_RX)>;
++			dma-names = "tx", "rx";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		dtrng: dtrng@0x10072000 {
++			compatible = "ingenic,dtrng";
++			reg = <0x10072000 0x100>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_DTRNG>;
++			status = "disabled";
++		};
++
++		otg_phy: otg_phy {
++			#address-cells = <1>;
++			#size-cells = <1>;
++			compatible = "ingenic,usbphy-x1600";
++			reg = <0x10000000 0x100 0x10078000 0x110>;
++			#phy-cells = <0>;
++
++		};
++
++		aic: aic@0x10079000 {
++			compatible = "ingenic,x1600-aic";
++			reg = <0x10079000 0x100>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_AUDIO>;
++			dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_ASOC_AIC_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_ASOC_AIC_RX)>;
++			dma-names = "tx", "rx";
++
++			i2s: i2s {
++				compatible = "ingenic,x1600-i2s";
++				status = "ok";
++			};
++			i2s_tloop: i2s_tloop {
++				compatible = "ingenic,i2s-tloop";
++				dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_ASOC_AIC_LOOP)>;
++				dma-names = "rx";
++				status = "ok";
++			};
++		};
++	};
++
++	ahb2 {
++		compatible = "simple-bus";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++
++		msc0: msc@0x13450000 {
++			compatible = "ingenic,x1600-mmc";
++			reg = <0x13450000 0x10000>;
++			status = "disable";
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_MSC0>;
++		};
++
++		msc1: msc@0x13460000 {
++			compatible = "ingenic,x1600-mmc";
++			reg = <0x13460000 0x10000>;
++			status = "disable";
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_MSC1>;
++		};
++
++		can0: can@0x13560000 {
++			compatible = "ingenic,x1600-can";
++			reg = <0x13560000 0x10000>;
++			status = "okay";
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_CAN0>;
++			dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_CAN0_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_CAN0_RX)>;
++			dma-names = "tx", "rx";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		can1: can@0x13570000 {
++			compatible = "ingenic,x1600-can";
++			reg = <0x13570000 0x10000>;
++			status = "okay";
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_CAN1>;
++			dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_CAN1_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_CAN1_RX)>;
++			dma-names = "tx", "rx";
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		cdbus: cdbus@0x13430000 {
++			compatible = "ingenic,x1600-cdbus";
++			reg = <0x13550000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_CDBUS>;
++			status = "ok";
++		};
++
++		aes: aes@0x13430000 {
++			compatible = "ingenic,aes";
++			reg = <0x13430000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_AES>;
++			status = "ok";
++		};
++
++		hash: hash@0x13470000 {
++			compatible = "ingenic,hash";
++			reg = <0x13470000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_HASH>;
++			status = "ok";
++		};
++
++		mac0: mac@0x134b0000 {
++			compatible = "ingenic,x1600-mac";
++			reg = <0x134b0000 0x2000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_GMAC0>;
++			ingenic,rst-ms = <10>;
++		};
++
++		sfc: sfc@0x13440000 {
++			compatible = "ingenic,x1600-sfc";
++			reg = <0x13440000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_SFC>;
++		};
++
++		pdma: dma@0x13420000 {
++			compatible = "ingenic,x1600-pdma";
++			reg = <0x13420000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupt-names = "pdma", "pdmad";
++			interrupts = <IRQ_PDMA>, <IRQ_PDMAD>;
++			#dma-channels = <32>;
++			#dma-cells = <1>;
++			ingenic,reserved-chs = <0x3>;
++		};
++
++		mcu: mcu@0x13420000 {
++			compatible = "ingenic,x1600-mcu";
++			reg = <0x13420000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupt-names = "pdmam";
++			interrupts = <IRQ_PDMAM>;
++			ingenic,tcsm_size = <32768>;
++		};
++
++		pwm: pwm@0x134c0000 {
++			compatible = "ingenic,x1600-pwm";
++			#pwm-cells = <2>;
++			reg = <0x134c0000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_PWM>;
++			dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_PWM0_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_PWM1_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_PWM2_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_PWM3_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_PWM4_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_PWM5_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_PWM6_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_PWM7_TX)>;
++			dma-names = "0", "1", "2", "3", "4", "5", "6", "7";
++		};
++
++		otg: otg@0x13500000 {
++			compatible = "ingenic,x1600-dwc2-hsotg";
++			reg = <0x13500000 0x40000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_OTG>;
++			ingenic,usbphy=<&otg_phy>;
++
++			g-rx-fifo-size = <1096>;
++			g-np-tx-fifo-size = <512>;
++			g-tx-fifo-size = <16 16 16 128 256 256 512 768>;
++			status = "okay";
++		};
++
++		efuse: efuse@0x13540000 {
++			compatible = "ingenic,x1600-efuse";
++			reg = <0x13540000 0x10000>;
++			status = "okay";
++		};
++	};
++
++	ahb1 {
++		compatible = "simple-bus";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++
++	};
++
++	ahb0 {
++		compatible = "simple-bus";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++
++		cim: cim@0x13060000 {
++			compatible = "ingenic,x1600-cim";
++			reg = <0x13060000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_CIM>;
++			clocks = <&clock CLK_DIV_CIM>, <&clock CLK_GATE_CIM>, <&clock CLK_GATE_MIPI_CSI>;
++			clock-names = "div_cim", "gate_cim", "gate_mipi";
++			status = "disable";
++		};
++
++		dpu: dpu@0x13050000 {
++			compatible = "ingenic,x1600-dpu";
++			reg = <0x13050000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_LCD>;
++			status = "disabled";
++		};
++
++	};
++
++};
++#include "x1600-pinctrl.dtsi"
+diff --git a/module_drivers/dts/x1600_module_base.dts b/module_drivers/dts/x1600_module_base.dts
+new file mode 100644
+index 000000000..5f2715cdb
+--- /dev/null
++++ b/module_drivers/dts/x1600_module_base.dts
+@@ -0,0 +1,154 @@
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include "x1600.dtsi"
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <generated/autoconf.h>
++
++
++/ {
++	compatible = "ingenic,x1600";
++
++	/*chosen {
++		bootargs = "console=ttyS1,115200 mem=128M@0x0ip=off init=/linuxrc ubi.mtd=3 root=ubi0:rootfs ubi.mtd=4 rootfstype=ubifs rw";
++	};*/
++
++
++	reserved-memory {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges =<>;
++
++		reserved_memory: reserved_mem@0x2000000{
++		      compatible = "shared-dma-pool";
++		      reg = <0x02000000 0x2000000>;
++		};
++	};
++
++};
++
++&uart0 {
++	status = "disable";
++	/* dma-mode; */
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pb>;
++};
++
++&uart1 {
++	status = "disable";
++	/* dma-mode; */
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pb>;
++};
++
++&uart2 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pb>;
++};
++
++&uart3 {
++	status = "disable";
++};
++
++&cpufreq {
++	status = "okay";
++	operating-points = <
++		/*KHZ uV */
++		1200000	900000
++		750000	900000
++		600000	900000
++		500000	900000
++		400000	900000
++		375000	900000
++		300000	900000
++		200000	900000
++			>;
++
++};
++
++&pdma {
++	status = "okay";
++};
++
++&sfc {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&sfc_pc>;
++	ingenic,sfc-init-frequency = <200000000>;
++	ingenic,sfc-max-frequency = <320000000>;
++	ingenic,use_ofpart_info  = /bits/ 8 <0>;
++	ingenic,spiflash_param_offset = <0>;
++
++	norflash@0 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nor flash partition */
++			uboot@0 {
++				label = "uboot";
++				reg = <0x0000000 0x40000>;
++				/*read-only;*/
++			};
++
++			kernel@40000 {
++				label = "kernel";
++				reg = <0x40000 0x300000>;
++			};
++
++			rootfs@360000 {
++				label = "rootfs";
++				reg = <0x360000 0xca0000>;
++			};
++		};
++	};
++
++	nandflash@1 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nand flash partition */
++			partition@0 {
++				label = "uboot";
++				reg = <0x0000000 0x100000>;
++				/*read-only;*/
++			};
++
++			partition@100000 {
++				label = "kernel";
++				reg = <0x100000 0x800000>;
++			};
++
++			partition@900000 {
++				label = "rootfs";
++				reg = <0x900000 0xf700000>;
++			};
++		};
++	};
++
++};
++
++&otg {
++	g-use-dma;
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&otg_phy {
++	/*ingenic,id-dete-gpio = <&gpb 29 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;*/
++	/*ingenic,vbus-dete-gpio = <&gpd 17 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;*/
++	/*ingenic,drvvbus-gpio = <&gpe 22 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;*/
++	status = "okay";
++};
++
++/ {
++
++	extclk: extclk {
++		clock-frequency = <24000000>;
++	};
++};
++
+diff --git a/module_drivers/dts/x2000-pinctrl.dtsi b/module_drivers/dts/x2000-pinctrl.dtsi
+new file mode 100644
+index 000000000..65b176384
+--- /dev/null
++++ b/module_drivers/dts/x2000-pinctrl.dtsi
+@@ -0,0 +1,651 @@
++#include <dt-bindings/pinctrl/ingenic-pinctrl.h>
++
++&pinctrl {
++	uart0_pin: uart0-pin {
++		uart0_pd: uart0-pd {
++			ingenic,pinmux = <&gpd 23 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++	uart1_pin: uart1-pin {
++		uart1_pc: uart1-pc {
++			ingenic,pinmux = <&gpc 21 24>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++
++	uart2_pin: uart2-pin {
++		uart2_pd: uart2-pd {
++			ingenic,pinmux = <&gpd 30 31>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	uart3_pin: uart3-pin {
++		uart3_pc: uart3-pc {
++			ingenic,pinmux = <&gpc 25 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		uart3_pd: uart3-pd {
++			ingenic,pinmux = <&gpd 0 3>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++
++	uart4_pin: uart4-pin {
++		uart4_pa: uart4-pa {
++			ingenic,pinmux = <&gpa 0 3>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		uart4_pc: uart4-pc {
++			ingenic,pinmux = <&gpc 9 12>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++		};
++	};
++
++	uart5_pin: uart5-pin {
++		uart5_pa: uart5-pa {
++			ingenic,pinmux = <&gpa 4 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		uart5_pc: uart5-pc {
++			ingenic,pinmux = <&gpc 5 6>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++		};
++	};
++
++	uart6_pin: uart6-pin {
++		uart6_pa: uart6-pa {
++			ingenic,pinmux = <&gpa 6 7>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		uart6_pc: uart6-pc {
++			ingenic,pinmux = <&gpc 7 8>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++		};
++	};
++
++	uart7_pin: uart7-pin {
++		uart7_pa: uart7-pa {
++			ingenic,pinmux = <&gpa 8 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		uart7_pc: uart7-pc {
++			ingenic,pinmux = <&gpc 1 2>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++		};
++	};
++
++	uart8_pin: uart8-pin {
++		uart8_pb: uart8-pb {
++			ingenic,pinmux = <&gpb 28 29>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++		};
++	};
++
++	uart9_pin: uart9-pin {
++		uart9_pb: uart9-pb {
++			ingenic,pinmux = <&gpb 30 31>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++		};
++	};
++
++	i2c0_pin: i2c0-pin {
++		i2c0_pc: i2c0-pc {
++			ingenic,pinmux = <&gpc 13 14>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++		};
++	};
++
++	i2c1_pin: i2c1-pin {
++		i2c1_pc: i2c1-pc {
++			ingenic,pinmux = <&gpc 23 24>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	i2c2_pin: i2c2-pin {
++		i2c2_pb: i2c2-pb {
++			ingenic,pinmux = <&gpb 22 23>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	i2c3_pin: i2c3-pin {
++		i2c3_pd: i2c3-pd {
++			ingenic,pinmux = <&gpd 30 31>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		i2c3_pa: i2c3-pa {
++			ingenic,pinmux = <&gpa 16 17>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	i2c4_pin: i2c4-pin {
++		i2c4_pc: i2c4-pc {
++			ingenic,pinmux = <&gpc 25 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		i2c4_pd: i2c4-pd {
++			ingenic,pinmux = <&gpd 0 1>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	i2c5_pin: i2c5-pin {
++		i2c5_pd: i2c5-pd {
++			ingenic,pinmux = <&gpd 4 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++
++	msc0_pin: msc0-pin {
++		msc0_4bit: msc0-4bit {
++			ingenic,pinmux = <&gpd 17 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		msc0_8bit: msc0-8bit {
++			ingenic,pinmux = <&gpd 17 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	msc1_pin: msc1-pin {
++		msc1_4bit: msc1-4bit {
++			ingenic,pinmux = <&gpd 8 13>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	msc2_pin: msc2-pin {
++		msc2_4bit: msc2-4bit {
++			ingenic,pinmux = <&gpe 0 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	mac0_phy_clk: mac0-phy-clk {
++		ingenic,pinmux = <&gpc 1 1>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		ingenic,pincfg = <&gpc 1 1 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++	};
++
++	mac0_rmii_p0: mac0-rmii-p0 {
++		mac0_rmii_p0_normal: mac0-rmii-normal {
++			ingenic,pinmux = <&gpc 6 7>, <&gpc 11 11>, <&gpc 15 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++			ingenic,pincfg = <&gpc 6 7 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>, \
++					 <&gpc 11 11 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>, \
++					 <&gpc 15 15 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>;
++		};
++		mac0_rmii_p0_rst: mac0-rmii-p0-rst {
++			ingenic,pinmux = <&gpc 6 7>, <&gpc 11 11>, <&gpc 15 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT>;
++			ingenic,pincfg = <&gpc 6 7 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>, \
++					 <&gpc 11 11 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>, \
++					 <&gpc 15 15 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>;
++		};
++	};
++
++	mac0_rmii_p1: mac0-rmii-p1 {
++		mac0_rmii_p1_normal: mac0-rmii-p1-normal {
++			ingenic,pinmux = <&gpc 2 3>, <&gpc 10 10>, <&gpc 12 13>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++			ingenic,pincfg = <&gpc 2 3 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpc 10 10 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpc 12 13 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++		};
++
++		mac0_rmii_p1_nomdio: mac0-rmii-p1-nomdio {
++			ingenic,pinmux = <&gpc 2 3>, <&gpc 10 10>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++			ingenic,pincfg = <&gpc 2 3 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpc 10 10 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++		};
++	};
++
++
++	mac0_rgmii_p0: mac0-rgmii-p0 {
++		mac0_rgmii_p0_normal: mac0-rgmii-normal {
++			ingenic,pinmux = <&gpc 6 9>, <&gpc 11 11>, <&gpc 15 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++			ingenic,pincfg = <&gpc 6 9 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>, \
++					 <&gpc 11 11 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>, \
++					 <&gpc 15 15 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>;
++		};
++		mac0_rgmii_p0_rst: mac0-rgmii-p0-rst {
++			ingenic,pinmux = <&gpc 6 9>, <&gpc 11 11>, <&gpc 15 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT>;
++			ingenic,pincfg = <&gpc 6 9 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>, \
++					 <&gpc 11 11 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>, \
++					 <&gpc 15 15 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>;
++		};
++	};
++
++	mac0_rgmii_p1: mac0-rgmii-p1 {
++		mac0_rgmii_p1_normal: mac0-rgmii-p1-normal {
++			ingenic,pinmux = <&gpc 2 5>, <&gpc 10 10>, <&gpc 12 14>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++			ingenic,pincfg = <&gpc 2 5 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpc 10 10 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>,\
++					 <&gpc 12 14 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++		};
++
++		mac0_rgmii_p1_nomdio: mac0-rgmii-p1-nomdio {
++			ingenic,pinmux = <&gpc 2 5>, <&gpc 10 10>, <&gpc 14 14>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++			ingenic,pincfg = <&gpc 2 5 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpc 10 10 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpc 14 14 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++		};
++	};
++
++	mac1_phy_clk: mac1-phy-clk {
++		ingenic,pinmux = <&gpb 23 23>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++		ingenic,pincfg = <&gpc 23 23 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++	};
++
++	mac1_rmii_p0: mac1-rmii-p0 {
++		mac1_rmii_p0_normal: mac1-rmii-normal {
++			ingenic,pinmux = <&gpb 12 13>, <&gpb 18 18>, <&gpb 22 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++			ingenic,pincfg = <&gpb 12 13 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>, \
++					 <&gpb 18 18 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>, \
++					 <&gpb 22 22 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>;
++		};
++		mac1_rmii_p0_rst: mac1-rmii-p0-rst {
++			ingenic,pinmux = <&gpb 12 13>, <&gpb 18 18>, <&gpb 22 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT>;
++			ingenic,pincfg = <&gpb 12 13 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>, \
++					 <&gpb 18 18 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>, \
++					 <&gpb 22 22 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>;
++		};
++	};
++
++	mac1_rmii_p1: mac1-rmii-p1 {
++		mac1_rmii_p1_normal: mac1-rmii-p1-normal {
++			ingenic,pinmux = <&gpb 8 9>, <&gpb 17 17>, <&gpb 19 20>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++			ingenic,pincfg = <&gpb 8 9 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpb 17 17 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpb 19 20 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++		};
++
++		mac1_rmii_p1_nomdio: mac1-rmii-p1-nomdio {
++			ingenic,pinmux = <&gpb 8 9>, <&gpb 17 17>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++			ingenic,pincfg = <&gpb 8 9 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpb 17 17 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++		};
++	};
++
++	mac1_rgmii_p0: mac1-rgmii-p0 {
++		mac1_rgmii_p0_normal: mac1-rgmii-normal {
++			ingenic,pinmux = <&gpb 12 15>, <&gpb 18 18>, <&gpb 22 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++			ingenic,pincfg = <&gpb 12 15 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>, \
++					 <&gpb 18 18 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>, \
++					 <&gpb 22 22 PINCFG_PACK(PINCTL_CFG_INPUT_SCHMITT_ENABLE, 1)>;
++		};
++		mac1_rgmii_p0_rst: mac1-rgmii-p0-rst {
++			ingenic,pinmux = <&gpb 12 15>, <&gpb 18 18>, <&gpb 22 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCINPUT>;
++			ingenic,pincfg = <&gpb 12 15 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>, \
++					 <&gpb 18 18 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>, \
++					 <&gpb 22 22 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>;
++		};
++	};
++
++	mac1_rgmii_p1: mac1-rgmii-p1 {
++		mac1_rgmii_p1_normal: mac1-rgmii-p1-normal {
++			ingenic,pinmux = <&gpb 8 11>, <&gpb 17 17>, <&gpb 19 21>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++			ingenic,pincfg = <&gpb 8 11 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>,\
++					 <&gpb 17 17 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpb 19 21 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++		};
++
++		mac1_rgmii_p1_nomdio: mac1-rgmii-p1-nomdio {
++			ingenic,pinmux = <&gpb 8 11>, <&gpb 17 17>, <&gpb 21 21>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++			ingenic,pincfg = <&gpb 8 11 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>,\
++					 <&gpb 17 17 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++					 <&gpb 21 21 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>;
++		};
++	};
++
++	pwm_pin: pwm-pin{
++		pwm0_pc: pwm0_pc {
++			ingenic,pinmux = <&gpc 0 0>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm1_pc: pwm1_pc {
++			ingenic,pinmux = <&gpc 1 1>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm2_pc: pwm2_pc {
++			ingenic,pinmux = <&gpc 2 2>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm3_pc: pwm3_pc {
++			ingenic,pinmux = <&gpc 3 3>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm4_pc: pwm4_pc {
++			ingenic,pinmux = <&gpc 4 4>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm5_pc: pwm5_pc {
++			ingenic,pinmux = <&gpc 5 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm6_pc: pwm6_pc {
++			ingenic,pinmux = <&gpc 6 6>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm7_pc: pwm7_pc {
++			ingenic,pinmux = <&gpc 7 7>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm8_pc: pwm8_pc {
++			ingenic,pinmux = <&gpc 8 8>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm9_pc: pwm9_pc {
++			ingenic,pinmux = <&gpc 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm10_pc: pwm10_pc {
++			ingenic,pinmux = <&gpc 10 10>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm11_pc: pwm11_pc {
++			ingenic,pinmux = <&gpc 11 11>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm12_pc: pwm12_pc {
++			ingenic,pinmux = <&gpc 12 12>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm13_pc: pwm13_pc {
++			ingenic,pinmux = <&gpc 13 13>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm14_pc: pwm14_pc {
++			ingenic,pinmux = <&gpc 14 14>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm15_pc: pwm15_pc {
++			ingenic,pinmux = <&gpc 15 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm0_pd: pwm0_pd {
++			ingenic,pinmux = <&gpd 30 30>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	 };
++
++	sfc_pin: sfc-pin {
++		sfc_pd_8bit: sfc-pd_8bit {
++			ingenic,pinmux = <&gpd 17 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		sfc_pd_4bit: sfc-pd_4bit {
++			ingenic,pinmux = <&gpd 17 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++
++		sfc_pe: sfc-pe {
++			ingenic,pinmux = <&gpe 16 21>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	cim_pin: cim-pin {
++		cim_pa: cim-pa {
++			ingenic,pinmux = <&gpa 0 7>, <&gpa 12 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	 };
++	vic_pin: vic-pin {
++		vic_pa_low_10bit: vic-pa-low-10bit {
++			ingenic,pinmux = <&gpa 0 9>, <&gpa 12 14>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		vic_pa_high_10bit: vic-pa-high-10bit {
++			ingenic,pinmux = <&gpa 2 14>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		vic_pa_12bit: vic-pa-12bit {
++			ingenic,pinmux = <&gpa 0 14>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	 };
++	cim_vic_mclk: cim-vic-mclk {
++		/* extclk 24M.*/
++		cim_vic_mclk_pe_24M: cim-vic-mclk-pe-24M {
++			ingenic,pinmux = <&gpe 24 24>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		cim_vic_mclk_pe: cim-vic-mclk-pe {
++			ingenic,pinmux = <&gpe 24 24>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		cim_vic_mclk_pc: cim-vic-mclk-pc {
++			ingenic,pinmux = <&gpc 15 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	lcd_pins: lcd-pins {
++		tft_lcd_pb_rgb888: tft-lcd-pb-rgb888 {
++			ingenic,pinmux = <&gpb 0 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++
++		tft_lcd_pb_rgb565: tft-lcd-pb-rgb565 {
++			ingenic,pinmux = <&gpb 0 15>, <&gpb 24 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++
++		tft_lcd_pb_rgb666: tft-lcd-pb-rgb666 {
++			ingenic,pinmux = <&gpb 0 17>, <&gpb 24 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++
++		smart_lcd_pb_16bit: smart-lcd-pb-16bit {
++			ingenic,pinmux = <&gpb 0 15>, <&gpb 25 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		smart_lcd_pb_9bit: smart-lcd-pb-9bit {
++			ingenic,pinmux = <&gpb 0 8>, <&gpb 25 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		smart_lcd_pb_8bit: smart-lcd-pb-8bit {
++			ingenic,pinmux = <&gpb 0 7>, <&gpb 25 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		smart_lcd_spi: smart-lcd-pb-spi {
++			ingenic,pinmux = <&gpb 0 0>, <&gpb 25 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		smart_lcd_pb_te: smart-lcd-pb-te {
++			ingenic,pinmux = <&gpb 27 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	baic1_tmclk_pc: baic1-tmclk-pc {
++		ingenic,pinmux = <&gpc 8 8>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	baic1_rmclk_pc: baic1-rmclk-pc {
++		ingenic,pinmux = <&gpc 1 1>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	baic1_pin: baic1-pin {
++		baic1_pc: baic1-pin-pc {
++			ingenic,pinmux = <&gpc 2 7>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		baic1_combine_pc: baic1-cpin-pc {
++			ingenic,pinmux = <&gpc 4 7>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	baic2_mclk_pa: baic2-mclk-pa {
++		ingenic,pinmux = <&gpa 7 7>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	baic2_pa: baic2-pa {
++		ingenic,pinmux = <&gpa 9 13>, <&gpa 17 17>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++	baic2_pa_tdm1: baic2-pa-tdm1 {
++		ingenic,pinmux = <&gpa 9 10>, <&gpa 17 17>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++	baic2_pa_tdm2: baic2-pa-tdm2 {
++		ingenic,pinmux = <&gpa 9 11>, <&gpa 17 17>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	baic3_mclk_pa: baic3-mclk-pa {
++		ingenic,pinmux = <&gpa 0 0>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	baic3_pa: baic3-pa {
++		ingenic,pinmux = <&gpa 2 6>, <&gpa 16 16>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	baic3_pa_tdm1: baic3-pa-tdm1 {
++		ingenic,pinmux = <&gpa 2 3>, <&gpa 16 16>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	baic3_pa_tdm2: baic3-pa-tdm2 {
++		ingenic,pinmux = <&gpa 2 4>, <&gpa 16 16>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	baic4_pd: baic4-pd {
++		ingenic,pinmux = <&gpd 2 5>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		ingenic,pincfg = <&gpd 4 4 PINCFG_PACK(PINCTL_CFG_BIAS_HIGH_IMPEDANCE, 1)>;
++	};
++
++	spdif_pc: spdif-pc {
++		ingenic,pinmux = <&gpc 13 14>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		ingenic,pincfg = <&gpc 14 14 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 7)>;
++	};
++	spdif_pc_in: spdif-pc-in {
++		ingenic,pinmux = <&gpc 13 13>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++	spdif_pc_out: spdif-pc-out {
++		ingenic,pinmux = <&gpc 14 14>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		ingenic,pincfg = <&gpc 14 14 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 7)>;
++	};
++
++	dmic_pc: dmic-pc {
++		ingenic,pinmux = <&gpc 20 24>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++	};
++	dmic_pc_2ch: dmic-pc-2ch {
++		ingenic,pinmux = <&gpc 20 21>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++	};
++	dmic_pc_4ch: dmic-pc-4ch {
++		ingenic,pinmux = <&gpc 20 22>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++	};
++	dmic_pc_6ch: dmic-pc-6ch {
++		ingenic,pinmux = <&gpc 20 23>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++	};
++
++	spi0_pb: spi0-pb {
++		ingenic,pinmux = <&gpb 28 31>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++	};
++
++	spi1_pc: spi0-pc {
++		ingenic,pinmux = <&gpc 9 12>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	tcu_pin: tcu-pin {
++		tcu0_pc: tcu0_pc {
++			ingenic,pinmux = <&gpc 0 1>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		tcu1_pc: tcu1_pc {
++			ingenic,pinmux = <&gpc 2 3>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		tcu2_pc: tcu2_pc {
++			ingenic,pinmux = <&gpc 4 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		tcu3_pc: tcu3_pc {
++			ingenic,pinmux = <&gpc 6 7>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		tcu4_pc: tcu4_pc {
++			ingenic,pinmux = <&gpc 8 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		tcu5_pc: tcu5_pc {
++			ingenic,pinmux = <&gpc 10 11>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		tcu5_pe: tcu5_pe {
++			ingenic,pinmux = <&gpe 16 17>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		tcu6_pc: tcu6_pc {
++			ingenic,pinmux = <&gpc 12 13>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		tcu6_pe: tcu6_pe {
++			ingenic,pinmux = <&gpe 18 19>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		tcu7_pc: tcu7_pc {
++			ingenic,pinmux = <&gpc 14 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		tcu7_pe: tcu7_pe {
++			ingenic,pinmux = <&gpe 20 21>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++
++	scc_pc: scc-pc {
++		ingenic,pinmux = <&gpc 3 4>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++	};
++
++	rtc32k_pins:rtc32k-pins {
++		rtc32k_enable:rtc32k-enable {
++			ingenic,pinmux = <&gpe 23 23>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		rtc32k_disable:rtc32k-disable {
++			ingenic,pinmux = <&gpe 23 23>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTIONS>;
++		};
++	};
++
++};
++
+diff --git a/module_drivers/dts/x2000.dtsi b/module_drivers/dts/x2000.dtsi
+new file mode 100644
+index 000000000..de59959cd
+--- /dev/null
++++ b/module_drivers/dts/x2000.dtsi
+@@ -0,0 +1,800 @@
++#include <dt-bindings/interrupt-controller/x2000-irq.h>
++#include <dt-bindings/clock/ingenic-tcu.h>
++#include <dt-bindings/clock/ingenic-x2000.h>
++#include <dt-bindings/sound/ingenic-baic.h>
++#include <dt-bindings/gpio/ingenic-gpio.h>
++#include <dt-bindings/net/ingenic_gmac.h>
++#include <dt-bindings/dma/ingenic-pdma.h>
++
++/ {
++	#address-cells = <1>;
++	#size-cells = <1>;
++	compatible = "ingenic,x2000";
++
++	aliases: aliases {
++		i2c0 = &i2c0;
++		i2c1 = &i2c1;
++		i2c2 = &i2c2;
++		i2c3 = &i2c3;
++		i2c4 = &i2c4;
++		i2c5 = &i2c5;
++		uart0 = &uart0;
++		uart1 = &uart1;
++		uart2 = &uart2;
++		uart3 = &uart3;
++		uart4 = &uart4;
++		uart5 = &uart5;
++		uart6 = &uart6;
++		uart7 = &uart7;
++		uart8 = &uart8;
++		mmc0 = &msc0;
++		mmc1 = &msc1;
++		mmc2 = &msc2;
++		mac0 = &mac0;
++		mac1 = &mac1;
++		spi0 = &spi0;
++		spi1 = &spi1;
++		pwm = &pwm;
++	};
++
++	cpus: cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		cpu0: cpu@0 {
++			device_type = "cpu";
++			compatible = "ingenic,xburst2";
++			reg = <0x000>;
++			clock-frequency = <800000000>;
++			cpu-idle-states = <&CPU_IDLE_PD>;
++		};
++
++		cpu1: cpu@1 {
++			device_type = "cpu";
++			compatible = "ingenic,xburst2";
++			reg = <0x001>;
++			cpu-idle-states = <&CPU_IDLE_PD>;
++			clock-frequency = <800000000>;
++		};
++
++		idle-states {
++	/*		CPU_IDLE_NORMAL: normal {
++				compatible = "ingenic,idle-state";
++				entry-latency-us = <15>;
++				exit-latency-us = <20>;
++				min-residency-us = <200>;
++			};*/
++			CPU_IDLE_PD: pd {
++				compatible = "ingenic,idle-state";
++				idle-state-name = "idle pd";
++				entry-latency-us = <5>;
++				exit-latency-us = <5>;
++				min-residency-us = <10>;
++			};
++		};
++	};
++
++	cpufreq: cpufreq-dt {
++		 compatible = "ingenic,x2000-cpufreq";
++		 status = "okay";
++	};
++
++	cpuintc: interrupt-controller {
++		#address-cells = <0>;
++		#interrupt-cells = <1>;
++		interrupt-controller;
++		compatible = "ingenic,cpu-interrupt-controller";
++
++	};
++
++	core_intc: core-intc@0x12300000 {
++		compatible = "ingenic,core-intc";
++		reg = <0x12300000 0x1000>,
++		    <0x10001000 0x1000>;
++		interrupt-controller;
++		#interrupt-cells = <1>;
++		cpu-intc-map = <0 0x000>,
++			       <1 0x100>;
++
++		interrupt-parent = <&cpuintc>;
++		interrupts = <CORE_INTC_IRQ>;
++		interrupt-names ="intc";
++	};
++
++	core_ost: core-ost@0x12000000 {
++		compatible = "ingenic,core-ost";
++		reg = <0x12000000 0x10000>, /*Global ost*/
++		      <0x12100000 0x10000>; /*Core ost*/
++		interrupt-parent = <&cpuintc>;
++		interrupt-names = "sys_ost";
++		interrupts = <CORE_SYS_OST_IRQ>;
++		cpu-ost-map = 	<0 0x000>,
++				<1 0x100>;
++	};
++
++	extclk: extclk {
++		compatible = "ingenic,fixed-clock";
++		clock-output-names ="ext";
++		#clock-cells = <0>;
++		clock-frequency  = <24000000>;
++	};
++
++	rtcclk: rtcclk {
++		compatible = "ingenic,fixed-clock";
++		clock-output-names ="rtc_ext";
++		#clock-cells = <0>;
++		clock-frequency = <32768>;
++	};
++
++	apb {
++		compatible = "simple-bus";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++
++		clock: clock-controller@0x10000000 {
++			compatible = "ingenic,x2000-clocks";
++			reg = <0x10000000 0x100>;
++			clocks = <&extclk>, <&rtcclk>;
++			clock-names = "ext", "rtc_ext";
++			#clock-cells = <1>;
++			little-endian;
++		};
++
++		sadc: sadc@10070000 {
++			compatible = "ingenic,x2000-sadc";
++			reg = <0x10070000 0x32>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_SADC>;
++			status = "ok";
++		};
++
++		tcu: tcu@0x10002000 {
++			compatible = "ingenic,tcu";
++			reg = <0x10002000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupt-names = "default";
++			interrupts = <IRQ_TCU0>;
++			status = "ok";
++		};
++
++		watchdog: watchdog@0x10002000 {
++			compatible = "ingenic,watchdog";
++			reg = <0x10002000 0x40>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_TCU0>;
++			status = "ok";
++		};
++
++		rtc: rtc@0x10003000 {
++			compatible = "ingenic,rtc";
++			reg = <0x10003000 0x4c>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_RTC>;
++			system-power-controller;
++			power-on-press-ms = <1000>;
++			status = "ok";
++		};
++
++		pinctrl: pinctrl@0x10010000 {
++			compatible = "ingenic,x2000-pinctrl";
++			reg = <0x10010000 0x1000>;
++			ingenic,num-chips = <5>;
++			ingenic,regs-offset = <0x100>;
++
++			gpa: gpa {
++				gpio-controller;
++				#gpio-cells = <3>;
++				#ingenic,pincfg-cells = <3>;
++				#ingenic,pinmux-cells = <2>;
++				interrupts = <IRQ_GPIO0>;
++				interrupt-parent = <&core_intc>;
++				interrupt-controller;
++				#interrupt-cells = <2>;
++			};
++
++			gpb: gpb {
++				gpio-controller;
++				#gpio-cells = <3>;
++				#ingenic,pincfg-cells = <3>;
++				#ingenic,pinmux-cells = <2>;
++				interrupts = <IRQ_GPIO1>;
++				interrupt-parent = <&core_intc>;
++				interrupt-controller;
++				#interrupt-cells = <2>;
++			};
++
++			gpc: gpc {
++				gpio-controller;
++				#gpio-cells = <3>;
++				#ingenic,pincfg-cells = <3>;
++				#ingenic,pinmux-cells = <2>;
++				interrupts = <IRQ_GPIO2>;
++				interrupt-parent = <&core_intc>;
++				interrupt-controller;
++				#interrupt-cells = <2>;
++			};
++
++			gpd: gpd {
++				gpio-controller;
++				#gpio-cells = <3>;
++				#ingenic,pincfg-cells = <3>;
++				#ingenic,pinmux-cells = <2>;
++				interrupts = <IRQ_GPIO3>;
++				interrupt-parent = <&core_intc>;
++				interrupt-controller;
++				#interrupt-cells = <2>;
++			};
++
++			gpe: gpe {
++				gpio-controller;
++				#gpio-cells = <3>;
++				#ingenic,pincfg-cells = <3>;
++				#ingenic,pinmux-cells = <2>;
++				interrupts = <IRQ_GPIO4>;
++				interrupt-parent = <&core_intc>;
++				interrupt-controller;
++				#interrupt-cells = <2>;
++			};
++
++		};
++
++		uart0: serial@0x10030000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10030000 0x100>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART0>;
++			clocks = <&extclk 0>;
++			clock-names = "uart0";
++		};
++		uart1: serial@0x10031000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10031000 0x100>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART1>;
++		};
++		uart2: serial@0x10032000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10032000 0x100>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART2>;
++		};
++		uart3: serial@0x10033000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10033000 0x100>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART3>;
++		};
++
++		uart4: serial@0x10034000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10034000 0x100>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART4>;
++			status = "disabled";
++		};
++		uart5: serial@0x10035000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10035000 0x100>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART5>;
++			status = "disabled";
++		};
++		uart6: serial@0x10036000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10036000 0x100>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART6>;
++			status = "disabled";
++		};
++		uart7: serial@0x10037000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10037000 0x100>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART7>;
++			status = "disabled";
++		};
++
++		uart8: serial@0x10038000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10038000 0x100>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART8>;
++			status = "disabled";
++		};
++		uart9: serial@0x10039000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10039000 0x100>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART9>;
++			status = "disabled";
++		};
++
++		i2c0: i2c@0x10050000 {
++			compatible = "ingenic,x2000-i2c";
++			reg = <0x10050000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_I2C0>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		i2c1: i2c@0x10051000 {
++			compatible = "ingenic,x2000-i2c";
++			reg = <0x10051000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_I2C1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		i2c2: i2c@0x10052000 {
++			compatible = "ingenic,x2000-i2c";
++			reg = <0x10052000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_I2C2>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		i2c3: i2c@0x10053000 {
++			compatible = "ingenic,x2000-i2c";
++			reg = <0x10053000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_I2C3>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "okay";
++		};
++
++		i2c4: i2c@0x10054000 {
++			compatible = "ingenic,x2000-i2c";
++			reg = <0x10054000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_I2C4>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "okay";
++		};
++
++		i2c5: i2c@0x10055000 {
++			compatible = "ingenic,x2000-i2c";
++			reg = <0x10055000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_I2C5>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		spi0: spi@0x10043000 {
++			compatible = "ingenic,x2000-spi";
++			reg = <0x10043000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_SSI0>;
++			dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_SSI0_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_SSI0_RX)>;
++			dma-names = "tx", "rx";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		spi1: spi@0x10044000 {
++			compatible = "ingenic,spi";
++			reg = <0x10044000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_SSI1>;
++			dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_SSI1_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_SSI1_RX)>;
++			dma-names = "tx", "rx";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		scc: scc@0x10040000 {
++			compatible = "ingenic,scc";
++			reg = <0x10040000 0x100>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_SCC>;
++			status = "disabled";
++		};
++
++		dtrng: dtrng@0x10072000 {
++			compatible = "ingenic,dtrng";
++			reg = <0x10072000 0x100>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_DTRNG>;
++			status = "disabled";
++		};
++
++		otg_phy: otg_phy {
++			#address-cells = <1>;
++			#size-cells = <1>;
++			compatible = "ingenic,usbphy-x2000";
++			reg = <0x10000000 0x100 0x10078000 0x110>;
++			#phy-cells = <0>;
++
++		};
++
++		icodec: icodec@0x10020000 {
++			compatible = "ingenic,icodec";
++			reg = <0x10020000 0x1000>;
++			status = "okay";
++		};
++	};
++
++	ahb2 {
++		compatible = "simple-bus";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++
++		as:as {
++			compatible = "simple-bus";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <>;
++
++			as_platform: as-platform {
++				compatible = "ingenic,as-platform";
++				reg = <0x134d0000 0x114>, <0x134d1000 0x100>;
++				reg-names = "dma", "fifo";
++				ingenic,fifo-size = <4096>;
++				interrupt-parent = <&core_intc>;
++				interrupts = <IRQ_AUDIO>;
++				ingenic,fth_quirk;
++			};
++			as_virtual_fe: as-virtual-fe {
++				compatible = "ingenic,as-vir-fe";
++				reg = <0x00000000 0x0>;
++				ingenic,cap-dai-bm = <0xc>;
++				ingenic,num-dais = <4>;
++			};
++			as_fmtcov: as-fmtcov {
++				compatible = "ingenic,as-fmtcov";
++				reg = <0x134d2000 0x28>;
++			};
++			as_fe_dsp: as-dsp {
++				compatible = "ingenic,as-dsp";
++				reg = <0x134d4000 0x30>;
++				ingenic,li-port = <0 1 2 3 4 6 7 8 9 10 11 12>;
++				ingenic,lo-port = <0 1 2 3 4 5 6 7 8 9 10 11>;
++				ingenic,cap-dai-bm = <0x3e0>;
++				ingenic,num-dais = <10>;
++			};
++			as_be_baic: as-baic {
++				compatible = "ingenic,as-baic";
++				reg = <0x134d5000 0x5000>;
++				ingenic,num-dais = <5>;
++				/* using dai-array to determine which BAIC to use */
++				ingenic,dai-array = <0>, <1>, <2>, <3>, <4>;
++				ingenic,dai-mode = <BAIC_3AND(BAIC_PCM_MODE, BAIC_DSP_MODE, BAIC_I2S_MODE)>,
++					<BAIC_3AND(BAIC_PCM_MODE, BAIC_DSP_MODE, BAIC_I2S_MODE)>,
++					<BAIC_4AND(BAIC_I2S_MODE, BAIC_TDM1_MODE, BAIC_TDM2_MODE, BAIC_NO_REPLAY)>,
++					<BAIC_4AND(BAIC_I2S_MODE, BAIC_TDM1_MODE, BAIC_TDM2_MODE, BAIC_NO_RECORD)>,
++					<BAIC_3AND(BAIC_PCM_MODE, BAIC_DSP_MODE, BAIC_I2S_MODE)>;
++				ingenic,data-pin-num = <1>, <1>, <4>, <4>, <1>;
++				ingenic,clk-split = <1>, <1>, <1>, <1>, <0>;
++				ingenic,clk-rname = "div_i2s0","div_i2s0","div_i2s2","no_clk","mux_pcm";
++				ingenic,clk-tname = "div_i2s1","div_i2s1","no_clk","div_i2s3","mux_pcm";
++				ingenic,pcm-clk-parent = "div_i2s2";
++			};
++			as_dmic: as-dmic {
++				compatible = "ingenic,as-dmic";
++				reg = <0x134da000 0x10>;
++				ingenic,clk-name = "mux_dmic";
++				ingenic,clk-parent = "div_i2s3";
++			};
++
++			as_aux_mixer: as-mixer {
++				compatible = "ingenic,as-mixer";
++				reg = <0x134dc000 0x8>;
++				ingenic,num-mixers = <1>;
++			};
++			as_spdif: as-spdif {
++				compatible = "ingenic,as-spdif";
++				reg = <0x134db000 0x14>, <0x134db100 0x14>;
++				reg-names = "out", "in";
++				ingenic,clk-name = "mux_spdif";
++				ingenic,clk-parent = "div_i2s2";
++			};
++		};
++
++		msc0: msc@0x13450000 {
++			compatible = "ingenic,sdhci";
++			reg = <0x13450000 0x10000>;
++			status = "disabled";
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_MSC0>;
++		};
++
++		msc1: msc@0x13460000 {
++			compatible = "ingenic,sdhci";
++			reg = <0x13460000 0x10000>;
++			status = "disabled";
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_MSC1>;
++		};
++
++		msc2: msc@0x13490000 {
++			compatible = "ingenic,sdhci";
++			reg = <0x13490000 0x10000>;
++			status = "disabled";
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_MSC2>;
++		};
++
++		aes: aes@0x13430000 {
++			compatible = "ingenic,aes";
++			reg = <0x13430000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_AES>;
++			status = "ok";
++		};
++
++		hash: hash@0x13470000 {
++			compatible = "ingenic,hash";
++			reg = <0x13470000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_HASH>;
++			status = "ok";
++		};
++
++		rsa: rsa@0x13480000 {
++			compatible = "ingenic,rsa";
++			reg = <0x13480000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_RSA>;
++			status = "ok";
++		};
++
++		mac0: mac@0x134b0000 {
++			compatible = "ingenic,x2000-mac";
++			reg = <0x134b0000 0x2000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_GMAC0>;
++			status = "disabled";
++			ingenic,rst-ms = <10>;
++		};
++
++		mac1: mac@0x134a0000 {
++			compatible = "ingenic,x2000-mac";
++			reg = <0x134a0000 0x2000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_GMAC1>;
++			status = "disabled";
++			ingenic,rst-ms = <10>;
++		};
++
++		sfc: sfc@0x13440000 {
++			compatible = "ingenic,x2000-sfc";
++			reg = <0x13440000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_SFC>;
++		};
++
++		pdma: dma@0x13420000 {
++			compatible = "ingenic,x2000-pdma";
++			reg = <0x13420000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupt-names = "pdma", "pdmad";
++			interrupts = <IRQ_PDMA>, <IRQ_PDMAD>;
++			#dma-channels = <32>;
++			#dma-cells = <1>;
++			ingenic,reserved-chs = <0x3>;
++		};
++
++		mcu: mcu@0x13420000 {
++			compatible = "ingenic,x2000-mcu";
++			reg = <0x13420000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupt-names = "pdmam";
++			interrupts = <IRQ_PDMAM>;
++			ingenic,tcsm_size = <16384>;
++		};
++
++		pwm: pwm@0x134c0000 {
++			compatible = "ingenic,x2000-pwm";
++			#pwm-cells = <2>;
++			reg = <0x134c0000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_PWM>;
++		};
++
++		otg: otg@0x13500000 {
++			compatible = "ingenic,x2000-dwc2-hsotg";
++			reg = <0x13500000 0x40000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_OTG>;
++			phys = <&otg_phy>;
++
++			g-rx-fifo-size = <1096>;
++			g-np-tx-fifo-size = <512>;
++			g-tx-fifo-size = <16 16 16 128 256 256 512 768>;
++			status = "okay";
++		};
++
++		efuse: efuse@0x13540000 {
++			compatible = "ingenic,x2000-efuse";
++			reg = <0x13540000 0x10000>;
++			status = "okay";
++		};
++	};
++
++	ahb1 {
++		compatible = "simple-bus";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++
++	};
++
++	ahb0 {
++		compatible = "simple-bus";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++
++		cim: cim@0x13060000 {
++			compatible = "ingenic,x2000-cim";
++			reg = <0x13060000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_CIM>;
++			clocks = <&clock CLK_DIV_CIM>, <&clock CLK_GATE_CIM>, <&clock CLK_GATE_MIPI_CSI>;
++			clock-names = "div_cim", "gate_cim", "gate_mipi";
++			status = "disable";
++		};
++
++		ispcam0: isp-camera@0 {
++			compatible = "ingenic,x2000-isp-camera";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <>;
++
++			port {
++				isp0_ep:endpoint@0 {
++
++				};
++			};
++
++
++			csi0: csi@0x10074000 {
++				compatible = "ingenic,x2000-csi";
++				reg = <0x10074000 0x1000>;
++				interrupt-parent = <&core_intc>;
++				interrupts = <IRQ_MIPI_CSI_4>;	// 4lane csi
++				clocks = <&clock CLK_GATE_MIPI_CSI>;
++				clock-names = "gate_csi";
++			};
++
++			vic0: vic@0x13710000 {
++				compatible = "ingenic,x2000-vic";
++				reg = <0x13710000 0x10000>;
++				interrupt-parent = <&core_intc>;
++				interrupts = <IRQ_VIC0>;
++				status = "ok";
++			};
++			isp0: isp@0x13700000 {
++				compatible = "ingenic,x2000-isp";
++				reg = <0x13700000 0x2300>;
++				interrupt-parent = <&core_intc>;
++				interrupts = <IRQ_ISP0>;
++				clocks = <&clock CLK_DIV_ISP>, <&clock CLK_GATE_ISP0> , <&clock POWER_ISP0>;
++				clock-names = "div_isp", "gate_isp0", "power_isp0";
++				status = "ok";
++				ingenic,cpm_reset = <0xb00000c4>;
++				ingenic,bit_sr = <25>;
++				ingenic,bit_stp = <24>;
++				ingenic,bit_ack = <23>;
++			};
++
++			mscaler0: mscaler@0x13702300 {
++				compatible = "ingenic,x2000-mscaler";
++				reg = <0x13702300 0x400>;
++				status = "ok";
++			};
++
++
++		};
++		ispcam1: isp-camera@1 {
++			compatible = "ingenic,x2000-isp-camera";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <>;
++
++			port {
++				isp1_ep:endpoint@0 {
++
++				};
++			};
++
++
++			csi1: csi@0x10073000 {
++				compatible = "ingenic,x2000-csi";
++				reg = <0x10073000 0x1000>;
++				interrupt-parent = <&core_intc>;
++				interrupts = <IRQ_MIPI_CSI2>;	// 2lane csi
++				clocks = <&clock CLK_GATE_MIPI_CSI>;
++				clock-names = "gate_csi";
++			};
++
++			vic1: vic@0x13810000 {
++				compatible = "ingenic,x2000-vic";
++				reg = <0x13810000 0x10000>;
++				interrupt-parent = <&core_intc>;
++				interrupts = <IRQ_VIC1>;
++				status = "ok";
++			};
++
++			isp1: isp@0x13800000 {
++				compatible = "ingenic,x2000-isp";
++				reg = <0x13800000 0x2300>;
++				interrupt-parent = <&core_intc>;
++				interrupts = <IRQ_ISP1>;
++				clocks = <&clock CLK_DIV_ISP>, <&clock CLK_GATE_ISP1>, <&clock POWER_ISP1>;
++				clock-names = "div_isp", "gate_isp1", "power_isp1";
++				status = "ok";
++				ingenic,cpm_reset = <0xb00000c4>;
++				ingenic,bit_sr = <22>;
++				ingenic,bit_stp = <21>;
++				ingenic,bit_ack = <20>;
++			};
++
++			mscaler1: mscaler@0x13802300 {
++				compatible = "ingenic,x2000-mscaler";
++				reg = <0x13802300 0x400>;
++				status = "ok";
++			};
++		};
++
++		dpu: dpu@0x13050000 {
++			compatible = "ingenic,x2000-dpu";
++			reg = <0x13050000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_LCD>;
++			status = "disabled";
++		};
++
++		rotate: rotate@0x13070000 {
++			compatible = "ingenic,x2000-rotate";
++			reg = <0x13070000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_ROTATE>;
++			status = "okay";
++		};
++
++		helix: helix@0x13200000 {
++			compatible = "ingenic,x2000-helix";
++			reg = <0x13200000 0x100000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_HELIX>;
++			status = "disabled";
++		};
++
++		felix: felix@0x13300000 {
++			compatible = "ingenic,x2000-felix";
++			reg = <0x13300000 0x100000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_FELIX>;
++			status = "disabled";
++		};
++
++	};
++
++};
++#include "x2000-pinctrl.dtsi"
+diff --git a/module_drivers/dts/x2000_lifesmart_480p_harmony.dts b/module_drivers/dts/x2000_lifesmart_480p_harmony.dts
+new file mode 100644
+index 000000000..a4d5152ee
+--- /dev/null
++++ b/module_drivers/dts/x2000_lifesmart_480p_harmony.dts
+@@ -0,0 +1,423 @@
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include "x2000.dtsi"
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <generated/autoconf.h>
++
++/ {
++	compatible = "ingenic,lifesmart_480p", "ingenic,x2000-v12";
++
++
++	reserved-memory {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges =<>;
++
++		reserved_memory: reserved_mem@0x7000000{
++		      compatible = "shared-dma-pool";
++		      reg = <0x07000000 0x1000000>;
++		};
++	};
++	/*chosen {*/
++		/*bootargs = "console=ttyS3,115200 mem=128M@0x0ip=off init=/linuxrc ubi.mtd=3 root=ubi0:rootfs ubi.mtd=4 rootfstype=ubifs rw";*/
++	/*};*/
++};
++
++&uart0 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pd>;
++};
++
++&uart2 {
++	status = "disable";
++};
++
++&uart3 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pc>;
++};
++
++&cpufreq {
++	status = "okay";
++	operating-points = <
++		/*KHZ uV */
++		1200000	900000
++		750000	900000
++		600000	900000
++		500000	900000
++		400000	900000
++		375000	900000
++		300000	900000
++		200000	900000
++			>;
++
++};
++
++&pinctrl {
++	ingenic,gpa_voltage = <GPIO_VOLTAGE_1V8>;
++};
++
++&i2c0 {
++	status = "okay";
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0_pc>;
++
++//	focaltech@0x48{
++//		compatible = "focaltech,fts"; /* do not modify */
++//		reg = <0x48>; /* do not modify */
++//		interrupt-parent = <&gpc>; /* INT pin */
++//		interrupts = <9>;
++//		focaltech,reset-gpio = <&gpc 8 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>; /* RST pin */
++//		focaltech,irq-gpio = <&gpc 9 IRQ_TYPE_EDGE_FALLING INGENIC_GPIO_NOBIAS>; /* INT pin */
++//		focaltech,max-touch-number = <2>;
++  //  	focaltech,display-coords = <0 0 480 480>;	/* resolution */
++//	};
++
++};
++
++&i2c3 {
++	status = "okay";
++};
++
++&i2c4 {
++	status = "disable";
++};
++
++&felix {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&helix {
++	status = "okay";
++};
++
++&pdma {
++	status = "okay";
++};
++
++&msc0 {
++	status = "disable";
++	/*mmc-hs200-1_8v;*/
++	cap-mmc-highspeed;
++	non-removable;
++	max-frequency = <50000000>;
++	bus-width = <4>;
++	non-removable;
++	voltage-ranges = <1800 3300>;
++
++	/* special property */
++	ingenic,wp-gpios = <0>;
++	ingneic,cd-gpios = <0>;
++	ingenic,rst-gpios = <0>;
++};
++
++&msc1 {
++	status = "disable";
++	pinctrl-names ="default","enable", "disable";
++	pinctrl-0 = <&msc1_4bit>;
++	pinctrl-1 = <&rtc32k_enable>;
++	pinctrl-2 = <&rtc32k_disable>;
++
++	sd-uhs-sdr104;
++	max-frequency = <100000000>;
++	bus-width = <4>;
++	voltage-ranges = <1800 3300>;
++	non-removable;
++
++	ingenic,sdio_clk = <1>;
++	keep-power-in-suspend;
++
++	/* special property */
++	ingenic,sdr-gpios = <0>;
++	ingenic,wp-gpios = <0>;
++	ingneic,cd-gpios = <0>;
++	ingenic,rst-gpios = <0>;
++	ingenic,removal-manual; /*removal-dontcare, removal-nonremovable, removal-removable, removal-manual*/
++
++	bcmdhd_wlan: bcmdhd_wlan {
++		 compatible = "android,bcmdhd_wlan";
++		 ingenic,sdio-irq = <&gpd 0 IRQ_TYPE_LEVEL_HIGH INGENIC_GPIO_NOBIAS>;
++		 ingenic,sdio-reset = <&gpd 1 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++};
++
++&msc2 {
++	status = "disable";
++	pinctrl-names ="default";
++	pinctrl-0 = <&msc2_4bit>;
++	sd-uhs-sdr104;
++	/*cap-mmc-highspeed;*/
++	max-frequency = <200000000>;
++	cd-inverted;
++	ext-cd-inverted;
++	bus-width = <4>;
++	voltage-ranges = <1800 3300>;
++
++	/* special property */
++	ingenic,sdr-gpios = <&gpc 0 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	ingenic,cd-ext-gpios = <&gpc 12 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,wp-gpios = <0>;
++	ingneic,cd-gpios = <0>;
++	ingenic,rst-gpios = <0>;
++};
++
++
++&mac1 {
++	pinctrl-names = "default", "reset";
++	pinctrl-0 = <&mac1_rgmii_p0_normal>, <&mac1_rgmii_p1_normal>;
++	pinctrl-1 = <&mac1_rgmii_p0_rst>, <&mac1_rgmii_p1_normal>;
++	status = "okay";
++	ingenic,rst-gpio = <&gpb 16 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,rst-ms = <10>;
++	ingenic,rst-delay-ms = <15>;
++	ingenic,mac-mode = <RGMII>;
++	ingenic,mode-reg = <0xb00000e8>;
++	ingenic,rx-clk-delay = <0x0>;
++	ingenic,tx-clk-delay = <0x3f>;
++	/*force mac mode*/
++	/*
++	ingenic,mac-force = <MAC_ON>;
++	ingenic,mac-autoneg = <MAC_ON>;
++	ingenic,mac-speed = <MAC_SPEED_1000M>;
++	ingenic,mac-duplex = <MAC_DUPLEX_HALF>;
++	ingenic,no_phy_connect;
++	*/
++};
++
++&sfc {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&sfc_pe>;
++	ingenic,sfc-init-frequency = <200000000>;
++	ingenic,sfc-max-frequency = <320000000>;
++	ingenic,use_ofpart_info  = /bits/ 8 <0>;
++	ingenic,spiflash_param_offset = <0>;
++
++	norflash@0 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nor flash partition */
++			uboot@0 {
++				label = "uboot";
++				reg = <0x0000000 0x40000>;
++				/*read-only;*/
++			};
++
++			kernel@40000 {
++				label = "kernel";
++				reg = <0x40000 0x300000>;
++			};
++
++			rootfs@360000 {
++				label = "rootfs";
++				reg = <0x360000 0xca0000>;
++			};
++		};
++	};
++
++	nandflash@1 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nand flash partition */
++			partition@0 {
++				label = "uboot";
++				reg = <0x0000000 0x100000>;
++				/*read-only;*/
++			};
++
++			partition@100000 {
++				label = "kernel";
++				reg = <0x100000 0x800000>;
++			};
++
++			partition@900000 {
++				label = "rootfs";
++				reg = <0x900000 0xf700000>;
++			};
++		};
++	};
++
++};
++
++&spi0 {
++	status = "disable";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pb>;
++
++	spi-max-frequency = <54000000>;
++	num-cs = <2>;
++	cs-gpios = <0>, <0>;
++	/*cs-gpios = <&gpa 27 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>, <&gpa 27 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;*/
++	ingenic,chnl = <0>;
++	ingenic,allow_cs_same = <1>;
++	ingenic,bus_num = <0>;
++	ingenic,has_dma_support = <0>;
++	ingenic,spi-src-clk = <1>;/*0.ext; 1.ssi*/
++
++	/* Add SPI interface device */
++	spidev: spidev@0 {
++		compatible = "rohm,dh2228fv";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++	};
++};
++
++&dtrng {
++	status = "okay";
++};
++
++&pwm {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm1_pc>;
++};
++
++&otg {
++	g-use-dma;
++	dr_mode = "otg";
++	device-using-dma = <1>;
++	status = "okay";
++};
++
++&otg_phy {
++	dr_mode = "otg";
++	status = "okay";
++	ingenic,id-dete-gpio = <&gpb 29 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,vbus-dete-gpio = <&gpd 17 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	ingenic,drvvbus-gpio = <&gpe 22 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++};
++
++&as_be_baic {
++	pinctrl-names = "default";
++	pinctrl-0 =  <&baic4_pd>;
++};
++
++&as_dmic {
++	pinctrl-names = "default";
++	pinctrl-0 = <&dmic_pc_4ch>;
++};
++
++&icodec {
++//	ingenic,spken-gpio = <&gpc 10 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++};
++
++&dpu {
++	status = "okay";
++	ingenic,disable-rdma-fb = <1>;
++	/*Defines the init state of composer fb export infomations.*/
++	ingenic,layer-exported = <1 1 0 0>;
++	ingenic,layer-frames   = <3 3 2 2>;
++	ingenic,layer-framesize = <480 480>, <480 480>, <320 240>, <320 240>;   /*Max framesize for each layer.*/
++	layer,color_mode	= <1 6 0 0>;					/*src fmt,*/
++	layer,src-size       	= <480 480>, <480 480>, <320 240>, <240 200>;	/*Layer src size should smaller than framesize*/
++	layer,target-size	= <480 480>, <480 480>, <160 240>, <240 200>;	/*Target Size should smaller than src_size.*/
++	layer,target-pos	= <0 0>, <0 0>, <340 480>, <100 980>;	/*target pos , the start point of the target panel.*/
++	layer,enable		= <1 0 1 1>;					/*layer enabled or disabled.*/
++	ingenic,logo-pan-layer	= <0>;						/*on which layer should init logo pan on.*/
++	port {
++		dpu_out_ep: endpoint {
++		/*	remote-endpoint = <&panel_tl040wvs03ct_ep>; */
++	    };
++	};
++};
++
++
++   &tft_lcd_pb_rgb666 {
++    ingenic,pincfg = <&gpb 24 27 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 4)>, \
++                     <&gpb 0 17 PINCFG_PACK(PINCTL_CFG_DRIVE_STRENGTH, 0)>;
++};
++
++
++/ {
++
++	extclk: extclk {
++		clock-frequency = <24000000>;
++	};
++
++	gpio_keys: gpio_keys {
++		   compatible = "gpio-keys";
++
++		   power {
++			   label = "Power";
++			   linux,code = <KEY_POWER>;
++			   gpios = <&gpe 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			   gpio-key,wakeup;
++		   };
++	   };
++
++	/*
++	 * gpd 21 bt wakeup host
++	 * gpd 22 host wakeup bt
++	 */
++	bt_power {
++		compatible = "ingenic,bt_power";
++		ingenic,reg-on-gpio = <&gpd 20 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		ingenic,wake-gpio = <&gpd 21 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++	};
++
++	sound {
++		compatible = "ingenic,x2000-sound";
++		ingenic,model = "halley5_v20";
++		ingenic,spken-gpio = <&gpc 10 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++	};
++
++	display-dbi {
++		compatible = "simple-bus";
++		#interrupt-cells = <1>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++		panel_tl040wvs03ct {
++			compatible = "ingenic,tl040wvs03ct";
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&tft_lcd_pb_rgb666>;
++			ingenic,vdd-en-gpio = <&gpc 3 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			ingenic,rst-gpio = <&gpc 4 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++		    /* ingenic,lcd-pwm-gpio = <&gpc 1 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>; */
++			ingenic,lcd-sdo-gpio = <&gpb 30 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,lcd-sck-gpio = <&gpb 31 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			ingenic,lcd-cs-gpio = <&gpb 28 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			port {
++				panel_tl040wvs03ct_ep: endpoint {
++					remote-endpoint = <&dpu_out_ep>;
++				};
++			};
++		};
++		panel_tl040hds01ct {
++			compatible = "ingenic,tl040hds01ct";
++			status = "disable";
++			pinctrl-names = "default";
++			pinctrl-0 = <&tft_lcd_pb_rgb666>;
++			ingenic,vdd-en-gpio = <&gpc 3 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;
++			ingenic,rst-gpio = <&gpc 4 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;
++			/* ingenic,lcd-pwm-gpio = <&gpc 1 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>; */
++			port {
++				panel_tl040hds01ct_ep: endpoint {
++					remote-endpoint = <&dpu_out_ep>;
++				};
++			};
++		};
++	};
++
++	backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwm 1 1000000>;
++		brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
++		default-brightness-level = <5>;
++	};
++
++
++
++};
+diff --git a/module_drivers/dts/x2000_module_base.dts b/module_drivers/dts/x2000_module_base.dts
+new file mode 100644
+index 000000000..e8d0fc2f3
+--- /dev/null
++++ b/module_drivers/dts/x2000_module_base.dts
+@@ -0,0 +1,194 @@
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include "x2000.dtsi"
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <generated/autoconf.h>
++
++/ {
++	compatible = "ingenic,x2000";
++
++	/*chosen {
++		bootargs = "console=ttyS1,115200 mem=128M@0x0ip=off init=/linuxrc ubi.mtd=3 root=ubi0:rootfs ubi.mtd=4 rootfstype=ubifs rw";
++	};*/
++
++	reserved-memory {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges =<>;
++
++		reserved_memory: reserved_mem@0x6000000{
++		      compatible = "shared-dma-pool";
++		      reg = <0x06000000 0x2000000>;
++		};
++	};
++};
++
++&uart0 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pd>;
++};
++
++&uart2 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pd>;
++};
++
++&uart3 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pc>;
++};
++
++&cpufreq {
++	status = "okay";
++	operating-points = <
++		/*KHZ uV */
++		1200000	900000
++		750000	900000
++		600000	900000
++		500000	900000
++		400000	900000
++		375000	900000
++		300000	900000
++		200000	900000
++			>;
++
++};
++
++&pinctrl {
++	ingenic,gpa_voltage = <GPIO_VOLTAGE_1V8>;
++};
++
++&felix {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&helix {
++	status = "okay";
++	memory-region=<&reserved_memory>;
++};
++
++&pdma {
++	status = "okay";
++};
++
++&sfc {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&sfc_pe>;
++	ingenic,sfc-init-frequency = <200000000>;
++	ingenic,sfc-max-frequency = <320000000>;
++	ingenic,use_ofpart_info  = /bits/ 8 <0>;
++	ingenic,spiflash_param_offset = <0>;
++
++	norflash@0 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nor flash partition */
++			uboot@0 {
++				label = "uboot";
++				reg = <0x0000000 0x40000>;
++				/*read-only;*/
++			};
++
++			kernel@40000 {
++				label = "kernel";
++				reg = <0x40000 0x300000>;
++			};
++
++			rootfs@360000 {
++				label = "rootfs";
++				reg = <0x360000 0xca0000>;
++			};
++		};
++	};
++
++	nandflash@1 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			/* spi nand flash partition */
++			partition@0 {
++				label = "uboot";
++				reg = <0x0000000 0x100000>;
++				/*read-only;*/
++			};
++
++			partition@100000 {
++				label = "kernel";
++				reg = <0x100000 0x800000>;
++			};
++
++			partition@900000 {
++				label = "rootfs";
++				reg = <0x900000 0xf700000>;
++			};
++		};
++	};
++
++};
++
++&otg {
++	g-use-dma;
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&otg_phy {
++	/*ingenic,id-dete-gpio = <&gpb 29 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;*/
++	/*ingenic,vbus-dete-gpio = <&gpd 17 GPIO_ACTIVE_LOW INGENIC_GPIO_NOBIAS>;*/
++	/*ingenic,drvvbus-gpio = <&gpe 22 GPIO_ACTIVE_HIGH INGENIC_GPIO_NOBIAS>;*/
++	status = "okay";
++};
++
++/ {
++
++	extclk: extclk {
++		clock-frequency = <24000000>;
++	};
++
++};
++
++
++/* Board Sleep GPIO configuration. */
++/* <0 1 2 3 .... 31>, set one of the pin to state.*/
++&gpa {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpb {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpc {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
++
++&gpd {
++	ingenic,gpio-sleep-pullup 	= <>;
++	ingenic,gpio-sleep-pulldown 	= <>;
++	ingenic,gpio-sleep-hiz		= <>;
++	ingenic,gpio-sleep-low		= <>;
++	ingenic,gpio-sleep-high		= <>;
++};
+diff --git a/module_drivers/dts/x2500-pinctrl.dtsi b/module_drivers/dts/x2500-pinctrl.dtsi
+new file mode 100644
+index 000000000..5d507e91e
+--- /dev/null
++++ b/module_drivers/dts/x2500-pinctrl.dtsi
+@@ -0,0 +1,297 @@
++#include <dt-bindings/pinctrl/ingenic-pinctrl.h>
++
++&pinctrl {
++	uart0_pin: uart0-pin {
++		uart0_pc: uart0-pc {
++			ingenic,pinmux = <&gpc 2 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		uart0_pa: uart0-pa {
++			ingenic,pinmux = <&gpa 10 11>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		uart0_pc1: uart0-pc1 {
++			ingenic,pinmux = <&gpc 14 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		uart0_pc1_1: uart0-pc1-1 {
++			ingenic,pinmux = <&gpc 16 17>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++	uart1_pin: uart1-pin {
++		uart1_pb: uart1-pb {
++			ingenic,pinmux = <&gpb 23 24>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		uart1_pa: uart1-pa {
++			ingenic,pinmux = <&gpa 17 18>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	uart2_pin: uart2-pin {
++		uart2_pc: uart2-pc {
++			ingenic,pinmux = <&gpc 18 19>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		uart2_pb: uart2-pb {
++			ingenic,pinmux = <&gpb 28 29>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		uart2_pa: uart2-pa {
++			ingenic,pinmux = <&gpa 6 7>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	uart3_pin: uart3-pin {
++		uart3_pc: uart3-pc {
++			ingenic,pinmux = <&gpc 6 7>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		uart3_pd: uart3-pd {
++			ingenic,pinmux = <&gpd 22 25>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		uart3_pa: uart3-pa {
++			ingenic,pinmux = <&gpa 2 3>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	i2c0_pin: i2c0-pin {
++		i2c0_pa: i2c0-pa {
++			ingenic,pinmux = <&gpa 12 13>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		i2c0_pc: i2c0-pc {
++			ingenic,pinmux = <&gpc 16 17>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	i2c1_pin: i2c1-pin {
++		i2c1_pa: i2c1-pa {
++			ingenic,pinmux = <&gpa 17 18>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		i2c1_pb: i2c1-pb {
++			ingenic,pinmux = <&gpb 17 18>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		i2c1_pd: i2c1-pd {
++			ingenic,pinmux = <&gpd 26 27>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	i2c2_pin: i2c2-pin {
++		i2c2_pc: i2c2-pc {
++			ingenic,pinmux = <&gpc 14 15>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		i2c2_pb: i2c2-pb {
++			ingenic,pinmux = <&gpb 25 26>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	i2c3_pin: i2c3-pin {
++		i2c3_pb: i2c3-pb {
++			ingenic,pinmux = <&gpb 28 29>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		i2c3_pb1: i2c3-pb1 {
++			ingenic,pinmux = <&gpb 20 21>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		i2c3_pa: i2c3-pa {
++			ingenic,pinmux = <&gpa 21 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	msc0_pin: msc0-pin {
++		msc0_pb: msc0-pb {
++			ingenic,pinmux = <&gpb 0 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	msc1_pin: msc1-pin {
++		msc1_pb: msc1-pb {
++			ingenic,pinmux = <&gpb 17 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		msc1_pc: msc1-pc {
++			ingenic,pinmux = <&gpc 8 13>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++	mac0_rmii_p0: mac0-rmii-p0 {
++		mac0_rmii_p0_normal: mac0-rmii-normal {
++			ingenic,pinmux = <&gpb 15 16>, <&gpb 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		mac0_rmii_p0_rst: mac0-rmii-p0-rst {
++			ingenic,pinmux = <&gpb 15 16>, <&gpb 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCHILVL>;
++		};
++	};
++
++	mac0_rmii_p1: mac0-rmii-p1 {
++		mac0_rmii_p1_normal: mac0-rmii-p1-normal {
++			ingenic,pinmux = <&gpb 7 7>, <&gpb 13 14>, <&gpb 8 8>, <&gpb 10 11>, <&gpb 6 6>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++
++		mac0_rmii_p1_nomdio: mac0-rmii-p1-nomdio {
++			ingenic,pinmux = <&gpb 7 7>, <&gpb 13 14>, <&gpb 8 8>, <&gpb 6 6>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++
++
++	pwm_pin: pwm-pin{
++		pwm_pc: pwm-pc{
++			ingenic,pinmux = <&gpc 2 7>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	 };
++
++	sfc_pin: sfc-pin {
++		sfc_pa: sfc-pa {
++			ingenic,pinmux = <&gpa 23 28>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++
++	vic_pin: vic-pin {
++		vic_pa_low_8bit: vic-pa-low-8bit {
++			  ingenic,pinmux = <&gpa 0 7>, <&gpa 14 16>;
++			  ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		vic_pa_low_10bit: vic-pa-low-10bit {
++			ingenic,pinmux = <&gpa 0 9>, <&gpa 14 16>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		vic_pa_high_10bit: vic-pa-high-10bit {
++			ingenic,pinmux = <&gpa 2 11>, <&gpa 14 16>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		vic_pa_12bit: vic-pa-12bit {
++			ingenic,pinmux = <&gpa 0 11>, <&gpa 14 16>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	 };
++	cim_vic_mclk: cim-vic-mclk {
++		cim0_vic_mclk_pc: cim0-vic-mclk-pc {
++			ingenic,pinmux = <&gpc 31 31>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		cim1_vic_mclk_pc: cim1-vic-mclk-pc {
++			ingenic,pinmux = <&gpc 30 30>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++		cim2_vic_mclk_pc: cim2-vic-mclk-pc {
++			ingenic,pinmux = <&gpc 29 29>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++		};
++	};
++
++	lcd_pins: lcd-pins {
++		tft_lcd_pd: tft-lcd-pd {
++			ingenic,pinmux = <&gpd 0 21>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++
++		smart_lcd_pd: smart-lcd-pd {
++			ingenic,pinmux = <&gpd 0 8>, <&gpd 11 11>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++
++		smart_lcd_pd_te: smart-lcd-pd-te {
++			ingenic,pinmux = <&gpd 9 9>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	dmic_pc: dmic-pc {
++		ingenic,pinmux = <&gpc 24 26>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++
++	spi0_pc: spi0-pc {
++		ingenic,pinmux = <&gpc 2 5>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION1>;
++	};
++
++	spi1_pin: spi1_pin {
++		spi1_pb: spi1-pb {
++		    ingenic,pinmux = <&gpb 25 30>;
++		    ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		spi1_pc: spi1-pc {
++		    ingenic,pinmux = <&gpc 8 13>;
++		    ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++	};
++
++	pwm_pins: pwm-pins {
++		pwm0_pc: pwm0_pc {
++			ingenic,pinmux = <&gpc 2 2>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		pwm1_pc: pwm1_pc {
++			ingenic,pinmux = <&gpc 3 3>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		pwm2_pc: pwm2_pc {
++			ingenic,pinmux = <&gpc 4 4>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		pwm3_pc: pwm3_pc {
++			ingenic,pinmux = <&gpc 5 5>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		pwm4_pc: pwm4_pc {
++			ingenic,pinmux = <&gpc 6 6>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		pwm5_pc: pwm5_pc {
++			ingenic,pinmux = <&gpc 7 7>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		pwm6_pd: pwm6_pd {
++			ingenic,pinmux = <&gpd 22 22>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		pwm7_pd: pwm7_pd {
++			ingenic,pinmux = <&gpd 23 23>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++		};
++		pwm2_pb: pwm2_pb {
++			ingenic,pinmux = <&gpb 30 30>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++		pwm3_pb: pwm3_pb {
++			ingenic,pinmux = <&gpb 31 31>;
++			ingenic,pinmux-funcsel = <PINCTL_FUNCTION0>;
++		};
++	};
++	dmic0_pc:dmic0_pc {
++	    ingenic,pinmux = <&gpc 24 25 26>;
++	    ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};
++/*	dmic1_pa:dmic1_pa {
++	    ingenic,pinmux = <&gpa 13 14>;
++	    ingenic,pinmux-funcsel = <PINCTL_FUNCTION2>;
++	};*/
++/*	spdif_pins:spdif_pins {
++		ingenic,pinmux = <&gpb 1 1>;
++		ingenic,pinmux-funcsel = <PINCTL_FUNCTION3>;
++	}; */
++};
++
+diff --git a/module_drivers/dts/x2500.dtsi b/module_drivers/dts/x2500.dtsi
+new file mode 100644
+index 000000000..b2393f227
+--- /dev/null
++++ b/module_drivers/dts/x2500.dtsi
+@@ -0,0 +1,744 @@
++#include <dt-bindings/interrupt-controller/x2500-irq.h>
++#include <dt-bindings/clock/ingenic-x2500.h>
++#include <dt-bindings/clock/ingenic-tcu.h>
++#include <dt-bindings/sound/ingenic-baic.h>
++#include <dt-bindings/net/ingenic_gmac.h>
++#include <dt-bindings/dma/ingenic-pdma.h>
++
++/ {
++	#address-cells = <1>;
++	#size-cells = <1>;
++	compatible = "ingenic,x2500";
++
++	aliases: aliases {
++		i2c0 = &i2c0;
++		i2c1 = &i2c1;
++		i2c2 = &i2c2;
++		i2c3 = &i2c3;
++		uart0 = &uart0;
++		uart1 = &uart1;
++		uart2 = &uart2;
++		uart3 = &uart3;
++		mmc0 = &msc0;
++		mmc1 = &msc1;
++		mac0 = &mac0;
++		spi0 = &spi0;
++		spi1 = &spi1;
++		bscaler0 = &bscaler0;
++	};
++
++	cpus: cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		cpu0: cpu@0 {
++			device_type = "cpu";
++			compatible = "ingenic,xburst2";
++			reg = <0x000>;
++			clock-frequency = <1200000000>;
++		};
++
++		cpu1: cpu@1 {
++			device_type = "cpu";
++			compatible = "ingenic,xburst2";
++			reg = <0x001>;
++			clock-frequency = <1200000000>;
++		};
++	};
++
++	cpufreq: cpufreq-dt {
++		 compatible = "ingenic,x2500-cpufreq";
++		 status = "okay";
++	};
++
++	cpuintc: interrupt-controller {
++		#address-cells = <0>;
++		#interrupt-cells = <1>;
++		interrupt-controller;
++		compatible = "ingenic,cpu-interrupt-controller";
++
++	};
++
++	core_intc: core-intc@0x12300000 {
++		compatible = "ingenic,core-intc";
++		reg = <0x12300000 0x1000>,
++		    <0x10001000 0x1000>;
++		interrupt-controller;
++		#interrupt-cells = <1>;
++		cpu-intc-map = <0 0x000>,
++			           <1 0x100>;
++
++		interrupt-parent = <&cpuintc>;
++		interrupts = <CORE_INTC_IRQ>;
++		interrupt-names ="intc";
++	};
++
++	core_ost: core-ost@0x12000000 {
++		compatible = "ingenic,core-ost";
++		reg = <0x12000000 0x10000>, /*Global ost*/
++		      <0x12100000 0x10000>; /*Core ost*/
++		interrupt-parent = <&cpuintc>;
++		interrupt-names = "sys_ost";
++		interrupts = <CORE_SYS_OST_IRQ>;
++		cpu-ost-map = 	<0 0x000>,
++			<1 0x100>;
++	};
++
++	extclk: extclk {
++		compatible = "ingenic,fixed-clock";
++		clock-output-names ="ext";
++		#clock-cells = <0>;
++		clock-frequency  = <24000000>;
++	};
++
++	rtcclk: rtcclk {
++		compatible = "ingenic,fixed-clock";
++		clock-output-names ="rtc_ext";
++		#clock-cells = <0>;
++		clock-frequency = <32768>;
++    };
++
++	clock: clock-controller@0x10000000 {
++		compatible = "ingenic,x2500-clocks";
++		reg = <0x10000000 0x100>;
++		clocks = <&extclk>, <&rtcclk>;
++		clock-names = "ext", "rtc_ext";
++		#clock-cells = <1>;
++		little-endian;
++	};
++
++	apb {
++		compatible = "simple-bus";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++		tcu: tcu@0x10002000 {
++				compatible = "ingenic,x2500-tcu";
++				reg = <0x10002000 0x140>;
++				interrupt-parent = <&core_intc>;
++				interrupt-names = "tcu_int0", "tcu_int1", "tcu_int2";
++				interrupts = <IRQ_TCU0 IRQ_TCU1 IRQ_TCU2>;
++				interrupt-controller;
++				status = "ok";
++
++				channel0: channel0 {
++					compatible = "ingenic,tcu_chn0";
++					ingenic,channel-info = <CHANNEL_INFO(0, TCU_MODE1, PWM_FUNC, \
++					NO_PWM_IN,NOWORK_SLEEP)>;
++				};
++				channel1: channel1 {
++					compatible = "ingenic,tcu_chn1";
++					ingenic,channel-info = <CHANNEL_INFO(1, TCU_MODE2, PWM_FUNC, \
++					NO_PWM_IN,NOWORK_SLEEP)>;
++				};
++				channel2: channel2 {
++					compatible = "ingenic,tcu_chn2";
++					ingenic,channel-info = <CHANNEL_INFO(2, TCU_MODE2, PWM_FUNC, \
++					NO_PWM_IN,NOWORK_SLEEP)>;
++				};
++				channel3: channel3 {
++					compatible = "ingenic,tcu_chn3";
++					ingenic,channel-info = <CHANNEL_INFO(3, TCU_MODE1, \
++					PWM_FUNC, NO_PWM_IN,NOWORK_SLEEP)>;
++				};
++				channel4: channel4 {
++					compatible = "ingenic,tcu_chn4";
++					ingenic,channel-info = <CHANNEL_INFO(4, TCU_MODE1, \
++					PWM_FUNC, NO_PWM_IN,NOWORK_SLEEP)>;
++				};
++				channel5: channel5 {
++					compatible = "ingenic,tcu_chn5";
++					ingenic,channel-info = <CHANNEL_INFO(5, TCU_MODE1, \
++					PWM_FUNC, NO_PWM_IN,NOWORK_SLEEP)>;
++				};
++				channel6: channel6 {
++					compatible = "ingenic,tcu_chn6";
++					ingenic,channel-info = <CHANNEL_INFO(6, TCU_MODE1, \
++					PWM_FUNC, NO_PWM_IN,NOWORK_SLEEP)>;
++				};
++				channel7: channel7 {
++					compatible = "ingenic,tcu_chn7";
++					ingenic,channel-info = <CHANNEL_INFO(7, TCU_MODE1, \
++					PWM_FUNC, NO_PWM_IN,NOWORK_SLEEP)>;
++				};
++				channel15: channel15 {
++					compatible = "ingenic,tcu_chn15";
++					ingenic,channel-info = <CHANNEL_INFO(15, 0,0,0,NOWORK_SLEEP)>;
++				};
++				channel16: channel16 {
++					compatible = "ingenic,watchdog";
++					ingenic,channel-info = <CHANNEL_INFO(16, 0,0,0,NOWORK_SLEEP)>;
++				};
++		};
++
++        sadc: sadc@10070000 {
++			compatible = "ingenic,x2500-sadc";
++			reg = <0x10070000 0x32>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_SADC>;
++			interrupt-controller;
++			status = "disabled";
++		};
++
++		watchdog: watchdog@0x10002000 {
++			compatible = "ingenic,watchdog";
++			reg = <0x10002000 0x40>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_TCU0>;
++			status = "disabled";
++		};
++
++		pinctrl: pinctrl@0x10010000 {
++			compatible = "ingenic,x2500-pinctrl";
++			reg = <0x10010000 0x1000>;
++			ingenic,num-chips = <4>;
++			ingenic,regs-offset = <0x1000>;
++
++			gpa: gpa {
++				gpio-controller;
++				#gpio-cells = <3>;
++				#ingenic,pincfg-cells = <3>;
++				#ingenic,pinmux-cells = <2>;
++				interrupts = <IRQ_GPIO0>;
++				interrupt-parent = <&core_intc>;
++				interrupt-controller;
++				#interrupt-cells = <2>;
++			};
++
++			gpb: gpb {
++				gpio-controller;
++				#gpio-cells = <3>;
++				#ingenic,pincfg-cells = <3>;
++				#ingenic,pinmux-cells = <2>;
++				interrupts = <IRQ_GPIO1>;
++				interrupt-parent = <&core_intc>;
++				interrupt-controller;
++				#interrupt-cells = <2>;
++			};
++
++			gpc: gpc {
++				gpio-controller;
++				#gpio-cells = <3>;
++				#ingenic,pincfg-cells = <3>;
++				#ingenic,pinmux-cells = <2>;
++				interrupts = <IRQ_GPIO2>;
++				interrupt-parent = <&core_intc>;
++				interrupt-controller;
++				#interrupt-cells = <2>;
++			};
++
++			gpd: gpd {
++				gpio-controller;
++				#gpio-cells = <3>;
++				#ingenic,pincfg-cells = <3>;
++				#ingenic,pinmux-cells = <2>;
++				interrupts = <IRQ_GPIO3>;
++				interrupt-parent = <&core_intc>;
++				interrupt-controller;
++				#interrupt-cells = <2>;
++			};
++
++		};
++
++		uart0: serial@0x10030000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10030000 0x1000>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART0>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart0_pc>;
++			status = "disabled";
++		};
++		uart1: serial@0x10031000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10031000 0x1000>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART1>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart1_pb>;
++			status = "disabled";
++		};
++		uart2: serial@0x10032000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10032000 0x1000>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART2>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_pc>;
++			status = "disabled";
++		};
++		uart3: serial@0x10033000 {
++			compatible = "ingenic,8250-uart";
++			reg = <0x10033000 0x1000>;
++			reg-shift = <2>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_UART3>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart3_pc>;
++			status = "disabled";
++		};
++
++		i2c0: i2c@0x10050000 {
++			compatible = "ingenic,x2500-i2c";
++			reg = <0x10050000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_I2C0>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "okay";
++		};
++
++		i2c1: i2c@0x10051000 {
++			compatible = "ingenic,x2500-i2c";
++			reg = <0x10051000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_I2C1>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "okay";
++		};
++
++		i2c2: i2c@0x10052000 {
++			compatible = "ingenic,x2500-i2c";
++			reg = <0x10052000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_I2C2>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		i2c3: i2c@0x10053000 {
++			compatible = "ingenic,x2500-i2c";
++			reg = <0x10053000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_I2C3>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		spi0: spi@0x10043000 {
++			compatible = "ingenic,x2500-spi";
++			reg = <0x10043000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_SSI0>;
++			dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_SSI0_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_SSI0_RX)>;
++			dma-names = "tx", "rx";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		spi1: spi@0x10044000 {
++			compatible = "ingenic,x2500-spi";
++			reg = <0x10044000 0x1000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_SSI1>;
++			dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_SSI1_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_SSI1_RX)>;
++			dma-names = "tx", "rx";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		dtrng: dtrng@0x10072000 {
++			compatible = "ingenic,dtrng";
++			reg = <0x10072000 0x100>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_DTRNG>;
++			status = "disabled";
++		};
++
++		des: des@0x10061000 {
++			compatible = "ingenic,des";
++			reg = <0x10043000 0x1000>;
++			dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_DES_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_DES_RX)>;
++			dma-names = "tx", "rx";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "okay";
++		};
++
++		otg_phy: otg_phy {
++			#address-cells = <1>;
++			#size-cells = <1>;
++			compatible = "ingenic,usbphy-x2500";
++			reg = <0x10000000 0x1000 0x10060000 0x1000>;
++			#phy-cells = <0>;
++		};
++
++		aic: aic@0x10020000 {
++			compatible = "ingenic,x2500-aic";
++			reg = <0x10020000 0x100>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_AIC0>;
++			dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_I2S_TX)>,
++				   <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_I2S_RX)>;
++			dma-names = "tx", "rx";
++			i2s: i2s {
++				compatible = "ingenic,x2500-i2s";
++				status = "ok";
++			};
++			i2s_tloop: i2s_tloop {
++				compatible = "ingenic,i2s-tloop";
++				dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_AIC_LOOP_RX)>;
++				dma-names = "rx";
++				status = "ok";
++			};
++		};
++
++		dmic: dmic@0x10034000 {
++			compatible = "ingenic,dmic";
++			reg = <0x10034000 0x100>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_DMIC>;
++			dmas = <&pdma INGENIC_DMA_TYPE(INGENIC_DMA_REQ_DMIC_RX)>;
++			dma-names = "rx";
++			pinctrl-0 = <&dmic0_pc>;
++			pinctrl-names = "default";
++			status = "ok";
++		};
++		icodec: icodec@0x10020000 {
++			compatible = "ingenic,icodec";
++			reg = <0x10021000 0x140>;
++			status = "okay";
++		};
++
++	};
++
++	ahb2 {
++		compatible = "simple-bus";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++
++		aes: aes@0x13430000 {
++			compatible = "ingenic,aes";
++			reg = <0x13430000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_AES>;
++			status = "okay";
++		};
++
++		hash: hash@0x13480000 {
++			compatible = "ingenic,hash";
++			reg = <0x13480000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_HASH>;
++			status = "okay";
++		};
++
++		rsa: rsa@0x134c0000 {
++			compatible = "ingenic,rsa";
++			reg = <0x134c0000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_RSA>;
++			status = "okay";
++		};
++
++		mac0: mac@0x134b0000 {
++			compatible = "ingenic,x2500-mac";
++			reg = <0x134b0000 0x2000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_GMAC0>;
++			status = "disabled";
++			ingenic,rst-ms = <10>;
++		};
++
++		sfc: sfc@0x13440000 {
++			compatible = "ingenic,x2500-sfc";
++			reg = <0x13440000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_SFC>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&sfc_pa>;
++			status = "disabled";
++		};
++
++		pdma: dma@13420000 {
++			compatible = "ingenic,x2500-pdma";
++			reg = <0x13420000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupt-names = "pdma", "pdmam";
++			interrupts = <IRQ_PDMA>, <IRQ_PDMAM>;
++			#dma-channels = <32>;
++			#dma-cells = <1>;
++			ingenic,reserved-chs = <0x3>;
++		};
++
++		otg: otg@0x13500000 {
++			compatible = "ingenic,x2500-dwc2-hsotg";
++			reg = <0x13500000 0x40000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_OTG>;
++			ingenic,usbphy=<&otg_phy>;
++
++			g-rx-fifo-size = <1096>;
++			g-np-tx-fifo-size = <512>;
++			g-tx-fifo-size = <16 16 16 128 256 256 512 768>;
++			status = "disabled";
++		};
++
++		efuse: efuse@0x13540000 {
++			compatible = "ingenic,x2500-efuse";
++			reg = <0x13540000 0x10000>;
++			status = "okay";
++		};
++	};
++
++	ahb1 {
++		compatible = "simple-bus";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++
++        el150: el150@0x13200000 {
++			compatible = "ingenic,x2500-el150";
++			reg = <0x13200000 0x100000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_EL150>;
++			status = "disabled";
++		};
++
++	};
++
++	ahb0 {
++		compatible = "simple-bus";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <>;
++
++		dpu: dpu@0x13050000 {
++			compatible = "ingenic,x2500-dpu";
++			reg = <0x13050000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_LCD>;
++			status = "disabled";
++		};
++
++		msc0: msc@0x13060000 {
++			compatible = "ingenic,sdhci";
++			reg = <0x13060000 0x10000>;
++			status = "disabled";
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_MSC0>;
++			pinctrl-names ="default";
++			pinctrl-0 = <&msc0_4bit>;
++		};
++
++		msc1: msc@0x13070000 {
++			compatible = "ingenic,sdhci";
++			reg = <0x13070000 0x10000>;
++			status = "disabled";
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_MSC1>;
++			pinctrl-names ="default";
++			pinctrl-0 = <&msc1_4bit>;
++		};
++
++		ipu: ipu@0x13080000 {
++			compatible = "ingenic,x2500-ipu";
++			reg = <0x13080000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_IPU>;
++			status = "okay";
++		};
++
++		drawbox: drawbox@0x130d0000 {
++			 compatible = "ingenic,x2500-drawbox";
++			 reg = <0x130d0000 0x10000>;
++			 interrupt-parent = <&core_intc>;
++			 interrupts = <IRQ_DRAW_BOX>;
++			 status = "okay";
++		};
++
++        i2d: i2d@0x130b0000 {
++			compatible = "ingenic,x2500-i2d";
++			reg = <0x130b0000 0x10000>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_I2D>;
++			status = "okay";
++		};
++
++		ispcam0: isp-camera@0 {
++			compatible = "ingenic,x2500-isp-camera";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <>;
++
++			port {
++				isp0_ep:endpoint@0 {
++
++				};
++			};
++
++
++			csi0: csi@0x10054000 {
++				compatible = "ingenic,x2500-csi";
++				reg = <0x10054000 0x1000>;
++				clocks = <&clock CLK_GATE_MIPI_CSI>;
++				clock-names = "gate_csi";
++			};
++
++			vic0: vic@0x13380000 {
++				compatible = "ingenic,x2500-vic";
++				reg = <0x13380000 0x10000>;
++				interrupt-parent = <&core_intc>;
++				interrupts = <IRQ_S0_VIC>;
++				status = "ok";
++			};
++			isp0: isp@0x13300000 {
++				compatible = "ingenic,x2500-isp";
++				clocks = <&clock CLK_DIV_ISP>, <&clock CLK_GATE_ISP>;
++				clock-names = "gate_isp", "div_isp";
++				status = "ok";
++				ingenic,cpm_reset = <0xb00000c4>;
++				ingenic,bit_sr = <22>;
++				ingenic,bit_stp = <21>;
++				ingenic,bit_ack = <20>;
++				ingenic,index = <0>;
++			};
++
++			mscaler0: mscaler@0x13316000 {
++				compatible = "ingenic,x2500-mscaler";
++				reg = <0x13316000 0x10000>;
++				status = "ok";
++			};
++
++
++		};
++
++		ispcam1: isp-camera@1 {
++			compatible = "ingenic,x2500-isp-camera";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <>;
++
++			port {
++				isp1_ep:endpoint@0 {
++
++				};
++			};
++
++
++			csi1: csi@0x10023000 {
++				compatible = "ingenic,x2500-csi";
++				reg = <0x10023000 0x1000>;
++				clocks = <&clock CLK_GATE_MIPI_CSI>;
++				clock-names = "gate_csi";
++			};
++
++			vic1: vic@0x13390000 {
++				compatible = "ingenic,x2500-vic";
++				reg = <0x13390000 0x10000>;
++				interrupt-parent = <&core_intc>;
++				interrupts = <IRQ_S1_VIC>;
++				status = "ok";
++			};
++
++			isp1: isp@0x13300000 {
++				compatible = "ingenic,x2500-isp";
++				clocks = <&clock CLK_DIV_ISP>, <&clock CLK_GATE_ISP>;
++				clock-names = "gate_isp", "div_isp";
++				status = "ok";
++				ingenic,cpm_reset = <0xb00000c4>;
++				ingenic,bit_sr = <22>;
++				ingenic,bit_stp = <21>;
++				ingenic,bit_ack = <20>;
++				ingenic,index = <1>;
++			};
++
++			mscaler1: mscaler@0x13317000 {
++				compatible = "ingenic,x2500-mscaler";
++				reg = <0x13317000 0x10000>;
++				status = "ok";
++			};
++
++		};
++
++		ispcam2: isp-camera@2 {
++			compatible = "ingenic,x2500-isp-camera";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <>;
++
++			port {
++				vic2_ep:endpoint@0 {
++
++				};
++			};
++
++			vic2: vic@0x13390000 {
++				compatible = "ingenic,x2500-vic";
++				reg = <0x133a0000 0x10000>;
++				interrupt-parent = <&core_intc>;
++				interrupts = <IRQ_S2_VIC>;
++				status = "ok";
++			};
++		};
++
++
++		bscaler0: bscaler@0x13090000 {
++			compatible = "ingenic,x2500-bscaler";
++			reg = <0x13090000 0x100>;
++			interrupt-parent = <&core_intc>;
++			interrupts = <IRQ_BSCALER0>,
++                         <IRQ_BSCALER1>;
++			status = "okay";
++		};
++	};
++	pwmz:pwm {
++		compatible = "ingenic,pwm";
++		#pwm-cells = <2>;
++		pinctrl-names = "default";
++		pwm0:pwm@0 {
++			ingenic,timer-parent = <&channel0>;
++			status = "okay";
++		};
++		pwm1:pwm@1 {
++			ingenic,timer-parent = <&channel1>;
++			status = "okay";
++		};
++		pwm2:pwm@2 {
++			ingenic,timer-parent = <&channel2>;
++			status = "okay";
++		};
++		pwm3:pwm@3 {
++			ingenic,timer-parent = <&channel3>;
++			status = "okay";
++		};
++		pwm4:pwm@4 {
++			ingenic,timer-parent = <&channel4>;
++			status = "disabled";
++		};
++		pwm5:pwm@5 {
++			ingenic,timer-parent = <&channel5>;
++			status = "disabled";
++		};
++		pwm6:pwm@6 {
++			ingenic,timer-parent = <&channel6>;
++			status = "disabled";
++		};
++		pwm7:pwm@7 {
++			ingenic,timer-parent = <&channel7>;
++			status = "disabled";
++		};
++	};
++	soc_nna:soc-nna@0x12502000 {
++		compatible = "ingenic,soc-nna";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		reg = <0x12502000 0x1000 0x1250f000 0x4000>;
++		status = "disable";
++	};
++
++};
++
++#include "x2500-pinctrl.dtsi"
+diff --git a/module_drivers/sound/Makefile b/module_drivers/sound/Makefile
+new file mode 100644
+index 000000000..9c48265cc
+--- /dev/null
++++ b/module_drivers/sound/Makefile
+@@ -0,0 +1 @@
++obj-y += soc/
+diff --git a/module_drivers/sound/soc/Makefile b/module_drivers/sound/soc/Makefile
+new file mode 100644
+index 000000000..10e2febc6
+--- /dev/null
++++ b/module_drivers/sound/soc/Makefile
+@@ -0,0 +1 @@
++obj-y += ingenic/
+diff --git a/module_drivers/sound/soc/ingenic/Kconfig b/module_drivers/sound/soc/ingenic/Kconfig
+new file mode 100644
+index 000000000..ac7f78b1c
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/Kconfig
+@@ -0,0 +1,329 @@
++menuconfig SND_ASOC_INGENIC
++	tristate "[AUDIO] ASoC support for Ingenic"
++	depends on (MACH_XBURST=y || MACH_XBURST2=y)
++	select SND_SOC
++	select SND
++	select SOUND
++	help
++		Say 'Y' to enable Alsa drivers of xburst.
++
++if SND_ASOC_INGENIC
++config SND_ASOC_INGENIC_DEBUG
++	bool "enable ingenic debug message"
++	default n
++config SND_ASOC_INGENIC_VERBOSE
++	bool "enable ingenic verbose debug message"
++	default n
++config DMIC_AND_AMIC_SYNC
++	bool "enable dmic and amic sync"
++	default n
++
++choice
++	prompt "Audio Version:"
++	depends on SND_ASOC_INGENIC
++config SND_ASOC_INGENIC_AS_V1
++	bool "AudioSystem Version 1 For Ingenic SOCs"
++	depends on SOC_X1600 || SOC_X2500
++	help
++		Audio System Verison 1 for SOC X1000, X1600, X2500.
++
++config SND_ASOC_INGENIC_AS_V2
++	bool "AudioSystem Version 2 For Ingenic SOCs"
++	select SND_DYNAMIC_MINORS
++	depends on SOC_M300 || SOC_X2000 || SOC_X2100
++	help
++		Audio System Version 2 for SOC X2000,
++endchoice
++
++config SND_ASOC_INGENIC_DMA_PREALLOC_PAGES
++        int "Prealloc Dma buf pages[4..1024]"
++        depends on SND_ASOC_INGENIC_AS_V2
++        default 128
++        help
++	  Specifies the default pre-allocated buffer-size in pages(4096 bytes) for the
++	  ingenic-audio driver.
++
++if SND_ASOC_INGENIC_AS_V1
++
++config SND_ASOC_INGENIC_X1000_BOARD
++	tristate
++
++config SND_ASOC_INGENIC_AIC
++	tristate
++
++config SND_X1600_AIC_IF_SEND_INVALID_DATA
++	bool "Empty data needs to be transmitted first"
++	depends on SOC_X1600 && SND_ASOC_INGENIC_HALLEY6
++        default y
++	help
++		Does the external codec need to transmit null data to stable transmission before transmitting valid data
++
++config SND_X1600_AIC_IF_SEND_INVALID_DATA_EVERYTIME
++	bool "Empty data is transmitted first for each playback"
++	depends on SOC_X1600 && SND_ASOC_INGENIC_HALLEY6
++	default n
++	help
++	       If this option is not selected, only the first play after power on will transmit empty data to stable state
++
++config SND_X1600_AIC_SEND_INVALID_DATA_TIME_MS
++	int "Length of time to transmit null data (in MS)"
++	depends on SOC_X1600 && SND_ASOC_INGENIC_HALLEY6
++	range 0 720
++	default 120
++	help
++		The length of time (in ms) from transmitting empty data to stable transmission is required
++		Based on halley6_v10 When the playback audio measured by V10 board is 8K, the corresponding time is 720, 16K is 360, 48K is 120 and 96k is 60
++
++config SND_ASOC_PDMA
++	tristate
++	select DMADEVICES
++	select INGENIC_PDMAC
++	select SND_SOC_GENERIC_DMAENGINE_PCM
++
++config SND_ASOC_INGENIC_AIC_SPDIF
++	tristate
++	select SND_ASOC_INGENIC_AIC
++
++config SND_ASOC_INGENIC_AIC_I2S
++	tristate
++	select SND_ASOC_INGENIC_AIC
++
++config SND_ASOC_INGENIC_DMIC
++	tristate
++
++config SND_ASOC_INGENIC_PCM
++	tristate
++
++config SND_ASOC_INGENIC_ICDC_D3
++	tristate
++	select SND_ASOC_INGENIC_AIC
++	select SND_ASOC_INGENIC_INCODEC
++
++config SND_ASOC_INGENIC_DUMP_CODEC
++	tristate
++
++config SND_ASOC_INGENIC_ICDC_INNO_V2
++	tristate
++
++config SND_ASOC_INGENIC_AIC_I2S_TLOOP
++	tristate
++	select SND_ASOC_INGENIC_AIC
++
++choice
++	prompt "select aic clock mode"
++	depends on SOC_X1600
++	default SND_ASOC_INGENIC_INDEPENDENT_CLK
++
++config SND_ASOC_INGENIC_INDEPENDENT_CLK
++	bool "aic use independent clock mode"
++
++config SND_ASOC_INGENIC_SHARE_CLK
++	bool "aic use share clock mode"
++
++endchoice
++
++choice
++	prompt "select audio mono channel"
++	depends on SOC_X1600 || SOC_X2500
++	default SND_ASOC_INGENIC_MONO_RIGHT
++
++config SND_ASOC_INGENIC_MONO_RIGHT
++	bool "select audio mono channel right"
++	help
++		When recording mono audio, use the right channel
++
++config SND_ASOC_INGENIC_MONO_LEFT
++	bool "select audio mono channel left"
++	help
++		When recording mono audio, use the left channel
++endchoice
++
++choice
++	prompt "select aic clock direction"
++	depends on SOC_X1600
++	default	SND_ASOC_INGENIC_MASTER_MODE
++
++config SND_ASOC_INGENIC_MASTER_MODE
++	bool "aic as master mode"
++	help
++		aic provide clock to external codec.
++
++config SND_ASOC_INGENIC_SLAVE_MODE
++	bool "aic as slave mode"
++	help
++		aic get clock from external codec.
++endchoice
++
++choice
++	prompt "select aic protocol mode"
++        depends on SOC_X1600
++	default	SND_ASOC_INGENIC_I2S_MODE
++
++config SND_ASOC_INGENIC_I2S_MODE
++	bool "aic use i2s protocol"
++
++config SND_ASOC_INGENIC_LEFT_J_MODE
++	bool "aic use left justified protocol"
++endchoice
++
++endif
++
++if SND_ASOC_INGENIC_AS_V2
++
++config SND_ASOC_INGENIC_AS_FE
++        tristate "ingenic snd asoc as-fe"
++
++config SND_ASOC_INGENIC_AS_BAIC
++        tristate "ingenic snd asoc baic"
++
++config SND_ASOC_INGENIC_AS_SPDIF
++        tristate "ingenic snd asoc spdif"
++        default y
++
++config SND_ASOC_INGENIC_AS_DMIC
++        tristate "ingenic snd asoc dmic"
++        default y
++
++config SND_ASOC_INGENIC_ICDC_INNO
++        tristate "ingenic  inno audio codec"
++        default y
++
++config SND_ASOC_INGENIC_AS_VIR_FE
++	depends on SND_ASOC_INGENIC_AS_FE
++        bool "enable ingenic virtual FE"
++        default y
++endif
++
++
++menu "Ingenic Board Type Select"
++choice
++	prompt "SOC x2000 codec Type select"
++	depends on SOC_X2000
++	depends on SND_ASOC_INGENIC_AS_V2
++
++	config SND_ASOC_INGENIC_BOARD_EXTERNAL_SOURCE
++	tristate "Audio support for external source board"
++
++	config SND_ASOC_INGENIC_ZEBRA
++        tristate "Audio support for x2000 zebra board"
++        select SND_ASOC_INGENIC_AS_FE
++        select SND_ASOC_INGENIC_AS_BAIC
++	select SND_ASOC_INGENIC_ICDC_INNO
++        select SND_SOC_WM8594
++        select SND_SOC_AK4458
++        select SND_SOC_AK5558
++
++	config SND_ASOC_INGENIC_ZEBRA_DMIC_ICDC
++        tristate "Audio support for x2000 zebra dmic icodec board"
++        select SND_ASOC_INGENIC_AS_FE
++        select SND_ASOC_INGENIC_AS_BAIC
++	select SND_ASOC_INGENIC_ICDC_INNO
++
++	config SND_ASOC_INGENIC_HALLEY5_V20
++        tristate "Audio support for x2000 halley5_v20 board"
++        select SND_ASOC_INGENIC_AS_FE
++        select SND_ASOC_INGENIC_AS_BAIC
++	select SND_ASOC_INGENIC_ICDC_INNO
++endchoice
++
++choice
++	prompt "SOC m300 codec Type select"
++	depends on SOC_M300
++	depends on SND_ASOC_INGENIC_AS_V2
++	config SND_ASOC_INGENIC_GEWU
++        tristate "Audio support for m300 gewu board"
++        select SND_ASOC_INGENIC_AS_FE
++        select SND_ASOC_INGENIC_AS_BAIC
++	select SND_ASOC_INGENIC_ICDC_INNO
++endchoice
++
++choice
++        prompt "SOC x2100 codec Type select"
++	depends on SOC_X2100
++        depends on SND_ASOC_INGENIC_AS_V2
++        config SND_ASOC_INGENIC_KALE_V10
++        tristate "Audio support for x2100 kale board"
++        select SND_ASOC_INGENIC_AS_FE
++        select SND_ASOC_INGENIC_AS_BAIC
++        select SND_ASOC_INGENIC_ICDC_INNO
++endchoice
++
++choice
++	prompt "SOC x2500 codec Type select"
++	depends on SOC_X2500
++	depends on SND_ASOC_INGENIC_AS_V1
++	config SND_ASOC_INGENIC_HIPPO_BOARD
++        tristate "Audio support for x2500 hippo  board"
++        select SND_ASOC_INGENIC_ICDC_INNO_V2
++        select SND_ASOC_INGENIC_DUMP_CODEC
++	select SND_ASOC_INGENIC_AIC
++	select SND_ASOC_PDMA
++	select SND_ASOC_INGENIC_AIC_I2S
++	select SND_ASOC_INGENIC_AIC_I2S_TLOOP
++	select SND_ASOC_INGENIC_DMIC
++	select SND_ASOC_INGENIC_PCM
++	select SND_ASOC_INGENIC_MONO_RIGHT
++endchoice
++
++choice
++	prompt "SOC x1600 codec Type select"
++	depends on SOC_X1600
++	depends on SND_ASOC_INGENIC_AS_V1
++
++	config SND_ASOC_INGENIC_PANDA
++        bool "Audio support for x1600 panda board"
++        select SND_SOC_WM8594
++        select SND_ASOC_INGENIC_DUMP_CODEC
++	select SND_ASOC_INGENIC_AIC
++	select SND_ASOC_PDMA
++	select SND_ASOC_INGENIC_AIC_I2S
++	select SND_ASOC_INGENIC_AIC_I2S_TLOOP
++	select SND_ASOC_INGENIC_MONO_RIGHT
++
++	config SND_ASOC_INGENIC_HALLEY6
++        bool "Audio support for x1600 halley6 board"
++        select SND_ASOC_INGENIC_DUMP_CODEC
++	select SND_ASOC_INGENIC_AIC
++	select SND_ASOC_PDMA
++	select SND_ASOC_INGENIC_AIC_I2S
++	select SND_ASOC_INGENIC_AIC_I2S_TLOOP
++	select SND_ASOC_INGENIC_MONO_RIGHT
++
++	config SND_ASOC_INGENIC_X1600_IRIS
++        bool "Audio support for x1600 iris board"
++        select SND_ASOC_INGENIC_DUMP_CODEC
++	select SND_ASOC_INGENIC_AIC
++	select SND_ASOC_PDMA
++	select SND_ASOC_INGENIC_AIC_I2S
++	select SND_ASOC_INGENIC_AIC_I2S_TLOOP
++	select SND_ASOC_INGENIC_MONO_RIGHT
++
++endchoice
++
++endmenu
++
++config SND_ASOC_INGENIC_SPDIF_DUMMY_TIMES
++    int "SOC x2000 spdif out dummy times in ms."
++	range 0 2000
++	default 800
++	depends on SOC_X2000
++	depends on SND_ASOC_INGENIC_AS_V2
++	help
++	    Select spdif out dummy times.
++		Examples:
++			1000 =>  1000 ms
++
++config SND_ASOC_INGENIC_PLAYBACK_DUMMY_TIMES
++    int "SOC x2000 playback dummy times in ms."
++	range 0 500
++	default 20
++	depends on SOC_X2000
++	depends on SND_ASOC_INGENIC_AS_V2
++	help
++	    Select playback dummy times.
++		Examples:
++			20 =>  20 ms
++
++source "module_drivers/sound/soc/ingenic/ecodec/Kconfig"
++
++endif
+diff --git a/module_drivers/sound/soc/ingenic/Makefile b/module_drivers/sound/soc/ingenic/Makefile
+new file mode 100644
+index 000000000..e495b8948
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/Makefile
+@@ -0,0 +1,8 @@
++
++obj-$(CONFIG_SND_ASOC_INGENIC_AS_V2) += as-v2/
++obj-$(CONFIG_SND_ASOC_INGENIC_AS_V1) += as-v1/
++
++obj-y += icodec/
++obj-y += ecodec/
++obj-y += boards/
++
+diff --git a/module_drivers/sound/soc/ingenic/README b/module_drivers/sound/soc/ingenic/README
+new file mode 100644
+index 000000000..2368cb0df
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/README
+@@ -0,0 +1,31 @@
++DIRs:
++.
++├── as-v1/
++├── as-v2/
++├── boards/
++├── icodec/
++├── ecodec/
++├── Kconfig
++├── Makefile
++└── README
++
++---
++as-v1:
++	Audio System Version 1.
++	Support SOCs
++		-X1000 Series.
++---
++as-v2:	Audio System Version 2.
++	Support SOCs
++		-X2000 Series.
++---
++boards: Boards config.
++icodec: Internal Codecs.
++ecodec: External Codecs.
++
++
++## Tested Usable External codecs
++
++ak4458
++ak5558
++wm8594
+diff --git a/module_drivers/sound/soc/ingenic/as-v1/Makefile b/module_drivers/sound/soc/ingenic/as-v1/Makefile
+new file mode 100644
+index 000000000..3b975260a
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v1/Makefile
+@@ -0,0 +1,9 @@
++
++obj-$(CONFIG_SND_ASOC_INGENIC_DMIC) += asoc-dmic.o
++obj-$(CONFIG_SND_ASOC_INGENIC_PCM) += asoc-pcm.o
++
++obj-$(CONFIG_SND_ASOC_PDMA) += asoc-dma.o
++obj-$(CONFIG_SND_ASOC_INGENIC_AIC) += asoc-aic.o
++obj-$(CONFIG_SND_ASOC_INGENIC_AIC_I2S) += asoc-i2s.o
++obj-$(CONFIG_SND_ASOC_INGENIC_AIC_SPDIF) += asoc-spdif.o
++obj-$(CONFIG_SND_ASOC_INGENIC_AIC_I2S_TLOOP) += asoc-i2s-tloop.o
+diff --git a/module_drivers/sound/soc/ingenic/as-v1/asoc-aic.c b/module_drivers/sound/soc/ingenic/as-v1/asoc-aic.c
+new file mode 100644
+index 000000000..2363c4cbc
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v1/asoc-aic.c
+@@ -0,0 +1,430 @@
++/*
++ *  sound/soc/ingenic/asoc-aic.c
++ *  ALSA Soc Audio Layer -- ingenic aic device driver
++ *
++ *  Copyright 2014 Ingenic Semiconductor Co.,Ltd
++ *	cli <chen.li@ingenic.com>
++ *
++ *  This program is free software; you can redistribute  it and/or modify it
++ *  under  the terms of  the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the  License, or (at your
++ *  option) any later version.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++#include <linux/spinlock.h>
++#include <linux/err.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/mm.h>
++#include <linux/io.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/delay.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <sound/dmaengine_pcm.h>
++#include "asoc-aic.h"
++#include <linux/clk-provider.h>
++
++#define INGENIC_I2S_RATE (24*1000000)
++static const char *aic_no_mode = "no mode";
++static const char *aic_i2s_mode = "i2s mode";
++static const char *aic_spdif_mode = "spdif mode";
++static const char *aic_ac97_mode = "ac97 mode";
++
++static const struct of_device_id aic_dt_match[];
++static const struct ingenic_aic_priv common_priv_data[];
++
++const char* aic_work_mode_str(enum aic_mode mode)
++{
++	switch (mode) {
++	default:
++	case AIC_NO_MODE:
++		return aic_no_mode;
++	case AIC_I2S_MODE:
++		return aic_i2s_mode;
++	case AIC_SPDIF_MODE:
++		return aic_spdif_mode;
++	case AIC_AC97_MODE:
++		return aic_ac97_mode;
++	}
++}
++EXPORT_SYMBOL_GPL(aic_work_mode_str);
++
++enum aic_mode aic_set_work_mode(struct device *aic,
++		enum aic_mode module_mode, bool enable)
++{
++	struct ingenic_aic *ingenic_aic = dev_get_drvdata(aic);
++	enum aic_mode working_mode;
++
++	spin_lock(&ingenic_aic->mode_lock);
++	if  (module_mode != AIC_AC97_MODE &&
++			module_mode != AIC_I2S_MODE &&
++			module_mode != AIC_SPDIF_MODE)
++		goto out;
++
++	if (enable && ingenic_aic->aic_working_mode == AIC_NO_MODE) {
++		ingenic_aic->aic_working_mode = module_mode;
++	} else if (!enable && ingenic_aic->aic_working_mode == module_mode) {
++		ingenic_aic->aic_working_mode = AIC_NO_MODE;
++	}
++out:
++	working_mode = ingenic_aic->aic_working_mode;
++	spin_unlock(&ingenic_aic->mode_lock);
++	return working_mode;
++}
++EXPORT_SYMBOL_GPL(aic_set_work_mode);
++
++int aic_set_rate(struct device *aic, unsigned long freq, int stream)
++{
++	struct ingenic_aic *ingenic_aic = dev_get_drvdata(aic);
++	unsigned long clk_rate;
++	int ret;
++
++	if (stream == STREAM_PLAY) {
++		if (ingenic_aic->rate_t != freq) {
++		ret = clk_set_rate(ingenic_aic->clk_t, freq);
++			if (ret == -EBUSY) {
++				clk_disable_unprepare(ingenic_aic->clk_t);
++				ret = clk_set_rate(ingenic_aic->clk_t, freq);
++				clk_prepare_enable(ingenic_aic->clk_t);
++			}
++			ingenic_aic->rate_t = clk_get_rate(ingenic_aic->clk_t);
++		}
++		clk_rate = ingenic_aic->rate_t;
++	} else if (stream == STREAM_RECORD) {
++		if (ingenic_aic->rate_r != freq) {
++			ret = clk_set_rate(ingenic_aic->clk_r, freq);
++			if (ret == -EBUSY) {
++				clk_disable_unprepare(ingenic_aic->clk_r);
++				ret = clk_set_rate(ingenic_aic->clk_r, freq);
++				clk_prepare_enable(ingenic_aic->clk_r);
++			}
++			ingenic_aic->rate_r = clk_get_rate(ingenic_aic->clk_r);
++		}
++		clk_rate = ingenic_aic->rate_r;
++	} else if (stream == STREAM_COMMON) {
++		if (ingenic_aic->rate != freq) {
++			ret = clk_set_rate(ingenic_aic->clk, freq);
++			if (ret == -EBUSY) {
++				clk_disable_unprepare(ingenic_aic->clk);
++				ret = clk_set_rate(ingenic_aic->clk, freq);
++				clk_prepare_enable(ingenic_aic->clk);
++			}
++			ingenic_aic->rate = clk_get_rate(ingenic_aic->clk);
++		}
++		clk_rate = ingenic_aic->rate;
++	}
++
++	return clk_rate;
++}
++EXPORT_SYMBOL_GPL(aic_set_rate);
++
++int aic_clk_ctrl(struct device *aic, bool enable)
++{
++	struct ingenic_aic *ingenic_aic = dev_get_drvdata(aic);
++	int i;
++
++	for (i = 0; ingenic_aic->priv[i].clk_name != NULL; i++) {
++		if (ingenic_aic->priv[i].clk_mode == AIC_CLOCK_GATE) {
++			if (!ingenic_aic->priv[i].is_bus_clk) {
++				struct clk *clk = devm_clk_get(ingenic_aic->dev, ingenic_aic->priv[i].clk_name);
++				if (IS_ERR(clk))
++					return PTR_ERR(clk);
++				if (enable)
++					clk_prepare_enable(clk);
++				else
++					clk_disable_unprepare(clk);
++			}
++		}
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(aic_clk_ctrl);
++
++static irqreturn_t ingenic_aic_irq_thread(int irq, void *dev_id)
++{
++	struct ingenic_aic *ingenic_aic = (struct ingenic_aic *)dev_id;
++
++	if ((ingenic_aic->mask & 0x8) && __aic_test_ror(ingenic_aic->dev)) {
++		ingenic_aic->ror++;
++		dev_printk(KERN_DEBUG, ingenic_aic->dev,
++				"recieve fifo [overrun] interrupt time [%d]\n",
++				ingenic_aic->ror);
++	}
++
++	if ((ingenic_aic->mask & 0x4) && __aic_test_tur(ingenic_aic->dev)) {
++		ingenic_aic->tur++;
++		dev_printk(KERN_DEBUG, ingenic_aic->dev,
++				"transmit fifo [underrun] interrupt time [%d]\n",
++				ingenic_aic->tur);
++	}
++
++	if ((ingenic_aic->mask & 0x2) && __aic_test_rfs(ingenic_aic->dev)) {
++		dev_printk(KERN_DEBUG, ingenic_aic->dev,
++				"[recieve] fifo at or above threshold interrupt time\n");
++	}
++
++	if ((ingenic_aic->mask & 0x1) && __aic_test_tfs(ingenic_aic->dev)) {
++		dev_printk(KERN_DEBUG, ingenic_aic->dev,
++				"[transmit] fifo at or blow threshold interrupt time\n");
++	}
++
++	/*sleep, avoid frequently interrupt*/
++	msleep(200);
++	__aic_clear_all_irq_flag(ingenic_aic->dev);
++	__aic_set_irq_enmask(ingenic_aic->dev, ingenic_aic->mask);
++	return IRQ_HANDLED;
++}
++
++static irqreturn_t ingenic_aic_irq_handler(int irq, void *dev_id)
++{
++	struct ingenic_aic *ingenic_aic = (struct ingenic_aic *)dev_id;
++
++	ingenic_aic->mask = __aic_get_irq_enmask(ingenic_aic->dev);
++	if (ingenic_aic->mask && (ingenic_aic->mask & __aic_get_irq_flag(ingenic_aic->dev))) {
++		/*Disable all aic interrupt*/
++		__aic_set_irq_enmask(ingenic_aic->dev, 0);
++		return IRQ_WAKE_THREAD;
++	}
++	return IRQ_NONE;
++}
++
++extern int ingenic_dma_pcm_register(struct device *dev,  const struct snd_dmaengine_pcm_config *config, struct ingenic_dma_pcm *ingenic_pcm);
++extern void ingenic_dma_pcm_unregister(struct ingenic_dma_pcm *ingenic_pcm);
++
++static int ingenic_aic_probe(struct platform_device *pdev)
++{
++	struct ingenic_aic *ingenic_aic;
++	const struct of_device_id *match;
++	struct resource *res = NULL;
++	struct device_node *subdev_node = NULL;
++	int ret, nr_child, i = 0;
++
++	nr_child = of_get_child_count(pdev->dev.of_node);
++
++	ingenic_aic = devm_kzalloc(&pdev->dev, sizeof(struct ingenic_aic) + nr_child * sizeof(void *),
++			GFP_KERNEL);
++	if (!ingenic_aic)
++		return -ENOMEM;
++
++	match = of_match_node(aic_dt_match, pdev->dev.of_node);
++	if (!match)
++		return -ENODEV;
++
++	ingenic_aic->priv = !match->data ? common_priv_data : (struct ingenic_aic_priv *)match->data;
++
++	ingenic_aic->dev = &pdev->dev;
++	ingenic_aic->subdevs = nr_child;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res)
++		return -ENOENT;
++
++	ingenic_aic->vaddr_base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(ingenic_aic->vaddr_base))
++		return -ENOMEM;
++
++	for (i = 0; ingenic_aic->priv[i].clk_name != NULL; i++) {
++		if (ingenic_aic->priv[i].clk_mode == AIC_CLOCK_GATE) {
++			if (ingenic_aic->priv[i].is_bus_clk) {
++				struct clk *clk = devm_clk_get(ingenic_aic->dev, ingenic_aic->priv[i].clk_name);
++				if (IS_ERR(clk))
++					return PTR_ERR(clk);
++				clk_prepare_enable(clk);
++			}
++		}
++
++		if (ingenic_aic->priv[i].clk_mode == AIC_CLOCK_CE) {
++				struct clk *clk = devm_clk_get(ingenic_aic->dev, ingenic_aic->priv[i].clk_name);
++				if (IS_ERR(clk))
++					return PTR_ERR(clk);
++				clk_prepare_enable(clk);
++		}
++
++		if (ingenic_aic->priv[i].clk_mode == AIC_CLOCK_MUX) {
++			struct clk *clk = devm_clk_get(&pdev->dev, ingenic_aic->priv[i].clk_name);
++			if (IS_ERR(clk))
++				return PTR_ERR(clk);
++			clk_set_parent(clk_get(NULL, ingenic_aic->priv[i].clk_name), clk_get(NULL, ingenic_aic->priv[i].mux_select));
++		}
++
++		if (ingenic_aic->priv[i].clk_mode == AIC_CLOCK_DIV) {
++			if (ingenic_aic->priv[i].stream_mode == AIC_STREAM_PLAYBACK) {
++				ingenic_aic->clk_t = devm_clk_get(&pdev->dev, ingenic_aic->priv[i].clk_name);
++				if (IS_ERR(ingenic_aic->clk_t))
++					return PTR_ERR(ingenic_aic->clk_t);
++			} else if (ingenic_aic->priv[i].stream_mode == AIC_STREAM_RECORD) {
++				ingenic_aic->clk_r = devm_clk_get(&pdev->dev, ingenic_aic->priv[i].clk_name);
++				if (IS_ERR(ingenic_aic->clk_r))
++					return PTR_ERR(ingenic_aic->clk_r);
++			} else if (ingenic_aic->priv[i].stream_mode == AIC_STREAM_COMMON) {
++				ingenic_aic->clk = devm_clk_get(&pdev->dev, ingenic_aic->priv[i].clk_name);
++				if (IS_ERR(ingenic_aic->clk))
++					return PTR_ERR(ingenic_aic->clk);
++			}
++		}
++	}
++
++	spin_lock_init(&ingenic_aic->mode_lock);
++
++	ingenic_aic->irqno = platform_get_irq(pdev, 0);
++	if (ingenic_aic->irqno >= 0)
++		ret = devm_request_threaded_irq(&pdev->dev, ingenic_aic->irqno,
++				ingenic_aic_irq_handler, ingenic_aic_irq_thread,
++				IRQF_SHARED , pdev->name, (void *)ingenic_aic);
++	if (!ret)
++		dev_info(&pdev->dev, "register aic irq\n");
++
++	platform_set_drvdata(pdev, (void *)ingenic_aic);
++
++	for_each_child_of_node(pdev->dev.of_node, subdev_node)
++		ingenic_aic->psubdev[i++] = of_platform_device_create(subdev_node, NULL, &pdev->dev);
++
++	ret = ingenic_dma_pcm_register(&pdev->dev, NULL, ingenic_aic->ingenic_pcm);
++	if (ret) {
++		int i;
++		for (i = 0; i < ingenic_aic->subdevs; i++)
++			platform_device_unregister(ingenic_aic->psubdev[i]);
++
++		for (i = 0; ingenic_aic->priv[i].clk_name != NULL; i++) {
++			if (ingenic_aic->priv[i].clk_mode == AIC_CLOCK_GATE || ingenic_aic->priv[i].clk_mode == AIC_CLOCK_CE) {
++				struct clk *clk = devm_clk_get(&pdev->dev, ingenic_aic->priv[i].clk_name);
++				if (IS_ERR(clk))
++					return PTR_ERR(clk);
++				clk_disable_unprepare(clk);
++			}
++		}
++
++		return ret;
++	}
++
++	dev_info(&pdev->dev, "Aic core probe success\n");
++	return 0;
++}
++
++static int ingenic_aic_remove(struct platform_device *pdev)
++{
++	struct ingenic_aic * ingenic_aic = platform_get_drvdata(pdev);
++	int i;
++
++	ingenic_dma_pcm_unregister(ingenic_aic->ingenic_pcm);
++
++	if (!ingenic_aic)
++		return 0;
++
++	for (i = 0; i < ingenic_aic->subdevs; i++)
++		platform_device_unregister(ingenic_aic->psubdev[i]);
++
++	platform_set_drvdata(pdev, NULL);
++
++	for (i = 0; ingenic_aic->priv[i].clk_name != NULL; i++) {
++		if (ingenic_aic->priv[i].clk_mode == AIC_CLOCK_GATE || ingenic_aic->priv[i].clk_mode == AIC_CLOCK_CE) {
++			struct clk *clk = devm_clk_get(&pdev->dev, ingenic_aic->priv[i].clk_name);
++			if (IS_ERR(clk))
++				return PTR_ERR(clk);
++			clk_disable_unprepare(clk);
++		}
++	}
++
++	return 0;
++}
++
++#ifdef CONFIG_PM
++int ingenic_aic_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	struct ingenic_aic * ingenic_aic = platform_get_drvdata(pdev);
++	int i;
++
++	for (i = 0; ingenic_aic->priv[i].clk_name != NULL; i++) {
++		if (ingenic_aic->priv[i].clk_mode == AIC_CLOCK_GATE || ingenic_aic->priv[i].clk_mode == AIC_CLOCK_CE) {
++			struct clk *clk = devm_clk_get(&pdev->dev, ingenic_aic->priv[i].clk_name);
++			if (IS_ERR(clk))
++				return PTR_ERR(clk);
++			if (__clk_is_enabled(clk))
++				clk_disable_unprepare(clk);
++		}
++	}
++
++	return 0;
++}
++
++int ingenic_aic_resume(struct platform_device *pdev)
++{
++	struct ingenic_aic * ingenic_aic = platform_get_drvdata(pdev);
++	int i;
++
++	for (i = 0; ingenic_aic->priv[i].clk_name != NULL; i++) {
++		if (ingenic_aic->priv[i].clk_mode == AIC_CLOCK_GATE || ingenic_aic->priv[i].clk_mode == AIC_CLOCK_CE) {
++			struct clk *clk = devm_clk_get(&pdev->dev, ingenic_aic->priv[i].clk_name);
++			if (IS_ERR(clk))
++				return PTR_ERR(clk);
++			clk_prepare_enable(clk);
++		}
++	}
++
++	return 0;
++}
++#endif
++
++static const struct ingenic_aic_priv common_priv_data[] = {
++	{ .clk_mode = AIC_CLOCK_GATE, .clk_name = "gate_aic" },
++	{ .clk_mode = AIC_CLOCK_DIV,  .clk_name = "cgu_i2s", .stream_mode = AIC_STREAM_PLAYBACK },
++	{},
++};
++
++static const struct ingenic_aic_priv x1600_priv_data[] = {
++	{ .clk_mode = AIC_CLOCK_GATE, .clk_name = "gate_audio", .is_bus_clk = true },
++	{ .clk_mode = AIC_CLOCK_GATE, .clk_name = "gate_i2s0t", .is_bus_clk = false },
++	{ .clk_mode = AIC_CLOCK_GATE, .clk_name = "gate_i2s0r", .is_bus_clk = false },
++	{ .clk_mode = AIC_CLOCK_CE,   .clk_name = "ce_i2s0t" },
++	{ .clk_mode = AIC_CLOCK_CE,   .clk_name = "ce_i2s0r" },
++	{ .clk_mode = AIC_CLOCK_DIV,  .clk_name = "div_i2s0t", .stream_mode = AIC_STREAM_PLAYBACK },
++	{ .clk_mode = AIC_CLOCK_DIV,  .clk_name = "div_i2s0r", .stream_mode = AIC_STREAM_RECORD },
++	{ .clk_mode = AIC_CLOCK_MUX,  .clk_name = "mux_i2s0t", .mux_select = "epll" },
++	{ .clk_mode = AIC_CLOCK_MUX,  .clk_name = "mux_i2s0r", .mux_select = "epll" },
++	{},
++};
++
++static const struct ingenic_aic_priv x2500_priv_data[] = {
++	{ .clk_mode = AIC_CLOCK_GATE, .clk_name = "gate_aic" , .is_bus_clk = true },
++	{ .clk_mode = AIC_CLOCK_CE,   .clk_name = "ce_i2st" },
++	{ .clk_mode = AIC_CLOCK_CE,   .clk_name = "ce_i2sr" },
++	{ .clk_mode = AIC_CLOCK_DIV,  .clk_name = "div_i2st", .stream_mode = AIC_STREAM_PLAYBACK },
++	{ .clk_mode = AIC_CLOCK_DIV,  .clk_name = "div_i2sr", .stream_mode = AIC_STREAM_RECORD },
++	{},
++};
++
++static const struct of_device_id aic_dt_match[] = {
++	{ .compatible = "ingenic,aic", .data = (void *)common_priv_data },
++	{ .compatible = "ingenic,x1600-aic", .data = (void *)x1600_priv_data },
++	{ .compatible = "ingenic,x2500-aic", .data = (void *)x2500_priv_data },
++	{},
++};
++MODULE_DEVICE_TABLE(of, aic_dt_match);
++
++static struct platform_driver ingenic_asoc_aic_driver = {
++	.driver = {
++		.name   = "asoc-aic",
++		.owner  = THIS_MODULE,
++		.of_match_table = of_match_ptr(aic_dt_match),
++	},
++	.probe  = ingenic_aic_probe,
++	.remove = ingenic_aic_remove,
++#ifdef CONFIG_PM
++	.suspend = ingenic_aic_suspend,
++	.resume = ingenic_aic_resume,
++#endif
++};
++module_platform_driver(ingenic_asoc_aic_driver);
++
++MODULE_DESCRIPTION("INGENIC ASOC AIC core driver");
++MODULE_AUTHOR("cli<chen.li@ingenic.com>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-asoc-aic");
+diff --git a/module_drivers/sound/soc/ingenic/as-v1/asoc-aic.h b/module_drivers/sound/soc/ingenic/as-v1/asoc-aic.h
+new file mode 100644
+index 000000000..d3ff9c8ab
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v1/asoc-aic.h
+@@ -0,0 +1,793 @@
++/*
++ *  sound/soc/ingenic/asoc-aic.h
++ *  ALSA Soc Audio Layer -- ingenic aic platform driver
++ *
++ *  Copyright 2014 Ingenic Semiconductor Co.,Ltd
++ *	cli <chen.li@ingenic.com>
++ *
++ *  This program is free software; you can redistribute  it and/or modify it
++ *  under  the terms of  the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the  License, or (at your
++ *  option) any later version.
++ */
++#ifndef __ASOC_AIC_H__
++#define __ASOC_AIC_H__
++
++#include <linux/dmaengine.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++
++#define INGENIC_I2S_INNER_CODEC		(1 << 0)
++#define INGENIC_I2S_EX_CODEC		(1 << 1)
++#define INGENIC_I2S_CODEC_MASK		(0xF)
++
++#define INGENIC_I2S_PLAYBACK		(1 << 4)
++#define INGENIC_I2S_CAPTURE		(1 << 5)
++#define INGENIC_I2S_PLAY_MASK		(0xF0)
++
++
++#define STREAM_PLAY	0
++#define STREAM_RECORD	1
++#define STREAM_COMMON	2
++
++struct ingenic_aic_subdev_pdata {
++	dma_addr_t dma_base;
++};
++
++enum aic_mode {
++	AIC_NO_MODE = 0,
++	AIC_I2S_MODE,
++	AIC_SPDIF_MODE,
++	AIC_AC97_MODE
++};
++
++enum aic_stream_mode {
++	AIC_STREAM_PLAYBACK,
++	AIC_STREAM_RECORD,
++	AIC_STREAM_COMMON,
++};
++
++enum aic_clk_mode {
++	AIC_CLOCK_GATE,
++	AIC_CLOCK_CE,
++	AIC_CLOCK_DIV,
++	AIC_CLOCK_MUX,
++};
++
++struct ingenic_aic_priv {
++	enum aic_clk_mode clk_mode;
++	const char *clk_name;
++	const char *mux_select;
++	enum aic_stream_mode stream_mode;
++	bool is_bus_clk;
++};
++
++struct ingenic_aic {
++	struct device	*dev;
++	void __iomem	*vaddr_base;
++	struct ingenic_dma_pcm *ingenic_pcm;
++	/* for clock */
++	const struct ingenic_aic_priv *priv;
++	struct clk *clk;
++	struct clk *clk_t;
++	struct clk *clk_r;
++	int rate;
++	int rate_t;
++	int rate_r;
++	/*for interrupt*/
++	int irqno;
++	unsigned int ror;		/*counter for debug*/
++	unsigned int tur;
++	int mask;
++	/*for aic work mode protect*/
++	spinlock_t	mode_lock;
++	enum aic_mode aic_working_mode;
++	/*for subdev*/
++	int subdevs;
++	struct platform_device* psubdev[];
++};
++
++const char* aic_work_mode_str(enum aic_mode mode);
++int aic_set_rate(struct device *aic, unsigned long freq, int stream);
++int aic_clk_ctrl(struct device *aic, bool enable);
++enum aic_mode aic_set_work_mode(struct device *aic, enum aic_mode module_mode, bool enable);
++
++static void inline ingenic_aic_write_reg(struct device *dev, unsigned int reg,
++		unsigned int val)
++{
++	struct ingenic_aic *ingenic_aic = dev_get_drvdata(dev);
++	writel(val, ingenic_aic->vaddr_base + reg);
++}
++
++static unsigned int inline ingenic_aic_read_reg(struct device *dev, unsigned int reg)
++{
++	struct ingenic_aic *ingenic_aic = dev_get_drvdata(dev);
++	return readl(ingenic_aic->vaddr_base + reg);
++}
++
++/* For AC97 and I2S */
++#define AICFR		(0x00)
++#define AICCR		(0x04)
++#define ACCR1		(0x08)
++#define ACCR2		(0x0c)
++#define I2SCR		(0x10)
++#define AICSR		(0x14)
++#define ACSR		(0x18)
++#define I2SSR		(0x1c)
++#define ACCAR		(0x20)
++#define ACCDR		(0x24)
++#define ACSAR		(0x28)
++#define ACSDR		(0x2c)
++#define I2SDIV		(0x30)
++#define AICDR		(0x34)
++#define AICLR           (0x38)
++#define AICTFLR		(0x3c)
++
++/* For SPDIF */
++#define SPENA		(0x80)
++#define SPCTRL		(0x84)
++#define SPSTATE		(0x88)
++#define SPCFG1		(0x8c)
++#define SPCFG2		(0x90)
++#define SPFIFO		(0x94)
++
++/* For AICFR */
++#define AICFR_ENB_BIT		(0)
++#define AICFR_ENB_MASK		(1 << AICFR_ENB_BIT)
++#define AICFR_SYNCD_BIT		(1)
++#define AICFR_SYNCD_MASK	(1 << AICFR_SYNCD_BIT)
++#define AICFR_BCKD_BIT		(2)
++#define AICFR_BCKD_MASK		(1 << AICFR_BCKD_BIT)
++#define AICFR_RST_BIT		(3)
++#define AICFR_RST_MASK		(1 << AICFR_RST_BIT)
++#define AICFR_AUSEL_BIT		(4)
++#define AICFR_AUSEL_MASK	(1 << AICFR_AUSEL_BIT)
++#define AICFR_ICDC_BIT		(5)
++#define AICFR_ICDC_MASK		(1 << AICFR_ICDC_BIT)
++#define AICFR_LSMP_BIT		(6)
++#define AICFR_LSMP_MASK		(1 << AICFR_LSMP_BIT)
++#define AICFR_CDC_SLV_BIT	(7)
++#define AICFR_CDC_SLV_MASK	(1 << AICFR_CDC_SLV_BIT)
++#define AICFR_DMODE_BIT		(8)
++#define AICFR_DMODE_MASK	(1 << AICFR_DMODE_BIT)
++#define	AICFR_ISYNCD_BIT	(9)
++#define	AICFR_ISYNCD_MASK	(1 << AICFR_ISYNCD_BIT)
++#define AICFR_IBCKD_BIT		(10)
++#define AICFR_IBCKD_MASK	(1 << AICFR_IBCKD_BIT)
++#define AICFR_SYSCLKD_BIT	(11)
++#define AICFR_SYSCLKD_MASK	(1 << AICFR_SYSCLKD_BIT)
++#define AICFR_MSB_BIT		(12)
++#define AICFR_MSB_MASK		(1 << AICFR_MSB_BIT)
++#define AICFR_TFTH_BIT		(16)
++#define AICFR_TFTH_MASK		(0x1f << AICFR_TFTH_BIT)
++#define AICFR_RFTH_BIT		(24)
++#define AICFR_RFTH_MASK		(0x1f << AICFR_RFTH_BIT)
++
++/* For AICCR */
++#define AICCR_EREC_BIT		(0)
++#define AICCR_EREC_MASK		(1 << AICCR_EREC_BIT)
++#define AICCR_ERPL_BIT		(1)
++#define AICCR_ERPL_MASK		(1 << AICCR_ERPL_BIT)
++#define AICCR_ENLBF_BIT		(2)
++#define AICCR_ENLBF_MASK	(1 << AICCR_ENLBF_BIT)
++#define	AICCR_ETFS_BIT		(3)
++#define	AICCR_ETFS_MASK		(1 << AICCR_ETFS_BIT)
++#define AICCR_ERFS_BIT		(4)
++#define AICCR_ERFS_MASK		(1 << AICCR_ERFS_BIT)
++#define AICCR_ETUR_BIT		(5)
++#define AICCR_ETUR_MASK		(1 << AICCR_ETUR_BIT)
++#define AICCR_EROR_BIT		(6)
++#define AICCR_EROR_MASK		(1 << AICCR_EROR_BIT)
++#define AICCR_EALL_INT_MASK	(AICCR_EROR_MASK|AICCR_ETUR_MASK|AICCR_ERFS_MASK|AICCR_ETFS_MASK)
++#define AICCR_RFLUSH_BIT	(7)
++#define AICCR_RFLUSH_MASK	(1 << AICCR_RFLUSH_BIT)
++#define AICCR_TFLUSH_BIT	(8)
++#define AICCR_TFLUSH_MASK	(1 << AICCR_TFLUSH_BIT)
++#define AICCR_ASVTSU_BIT	(9)
++#define AICCR_ASVTSU_MASK	(1 << AICCR_ASVTSU_BIT)
++#define AICCR_ENDSW_BIT		(10)
++#define AICCR_ENDSW_MASK	(1 << AICCR_ENDSW_BIT)
++#define AICCR_M2S_BIT		(11)
++#define AICCR_M2S_MASK		(1 << AICCR_M2S_BIT)
++#define AICCR_MONOCTR_RIGHT_OFFSET	(12)
++#define AICCR_MONOCTR_RIGHT_MASK	(0x1 << AICCR_MONOCTR_RIGHT_OFFSET)
++#define AICCR_STEREOCTR_MASK	(0x3 << AICCR_MONOCTR_RIGHT_OFFSET)
++#define AICCR_MONOCTR_OFFSET	(13)
++#define AICCR_MONOCTR_MASK	(0x1 << AICCR_MONOCTR_OFFSET)
++#define AICCR_TDMS_BIT		(14)
++#define AICCR_TDMS_MASK		(1 << AICCR_TDMS_BIT)
++#define AICCR_RDMS_BIT		(15)
++#define AICCR_RDMS_MASK		(1 << AICCR_RDMS_BIT)
++#define AICCR_ISS_BIT		(16)
++#define AICCR_ISS_MASK		(0x7 << AICCR_ISS_BIT)
++#define AICCR_OSS_BIT		(19)
++#define AICCR_OSS_MASK		(0x7 << AICCR_OSS_BIT)
++#define AICCR_TLDMS_OFFSET      (22)
++#define AICCR_TLDMS_MASK        (0x1 << AICCR_TLDMS_OFFSET)
++#define AICCR_ETFL_OFFSET       (23)
++#define AICCR_ETFL_MASK         (0x1 << AICCR_ETFL_OFFSET)
++#define AICCR_CHANNEL_BIT	(24)
++#define AICCR_CHANNEL_MASK	(0x7 << AICCR_CHANNEL_BIT)
++#define AICCR_PACK16_BIT	(28)
++#define AICCR_PACK16_MASK	(1 << AICCR_PACK16_BIT)
++
++/* For ACCR1 */
++#define	ACCR1_XS_BIT		(0)
++#define ACCR1_XS_MASK		(0x3ff << ACCR1_XS_BIT)
++#define	ACCR1_RS_BIT		(16)
++#define ACCR1_RS_MASK		(0x3ff << ACCR1_RS_BIT)
++
++/* For ACCR2 */
++#define	ACCR2_SA_BIT		(0)
++#define	ACCR2_SA_MASK		(1 << ACCR2_SA_BIT)
++#define	ACCR2_SS_BIT		(1)
++#define	ACCR2_SS_MASK		(1 << ACCR2_SS_BIT)
++#define	ACCR2_SR_BIT		(2)
++#define	ACCR2_SR_MASK		(1 << ACCR2_SR_BIT)
++#define	ACCR2_SO_BIT		(3)
++#define	ACCR2_SO_MASK		(1 << ACCR2_SO_BIT)
++#define	ACCR2_ECADT_BIT		(16)
++#define	ACCR2_ECADT_MASK	(1 << ACCR2_ECADT_BIT)
++#define	ACCR2_ECADR_BIT		(17)
++#define	ACCR2_ECADR_MASK	(1 << ACCR2_ECADR_BIT)
++#define	ACCR2_ERSTO_BIT		(18)
++#define	ACCR2_ERSTO_MASK	(1 << ACCR2_ERSTO_BIT)
++
++/* For I2SCR */
++#define	I2SCR_AMSL_BIT		(0)
++#define	I2SCR_AMSL_MASK		(1 << I2SCR_AMSL_BIT)
++#define	I2SCR_ESCLK_BIT		(4)
++#define	I2SCR_ESCLK_MASK	(1 << I2SCR_ESCLK_BIT)
++#define	I2SCR_STPBK_BIT		(12)
++#define	I2SCR_STPBK_MASK	(1 << I2SCR_STPBK_BIT)
++#define	I2SCR_ISTPBK_BIT	(13)
++#define	I2SCR_ISTPBK_MASK	(1 << I2SCR_ISTPBK_BIT)
++#define	I2SCR_SWLH_BIT		(16)
++#define	I2SCR_SWLH_MASK		(1 << I2SCR_SWLH_BIT)
++#define	I2SCR_RFIRST_BIT	(17)
++#define	I2SCR_RFIRST_MASK	(1 << I2SCR_RFIRST_BIT)
++
++/* For AICSR */
++#define AICSR_TFS_BIT		(3)
++#define AICSR_TFS_MASK		(1 << AICSR_TFS_BIT)
++#define AICSR_RFS_BIT		(4)
++#define AICSR_RFS_MASK		(1 << AICSR_RFS_BIT)
++#define AICSR_TUR_BIT		(5)
++#define AICSR_TUR_MASK		(1 << AICSR_TUR_BIT)
++#define AICSR_ROR_BIT		(6)
++#define AICSR_ROR_MASK		(1 << AICSR_ROR_BIT)
++#define AICSR_ALL_INT_MASK	(AICSR_TFS_MASK|AICSR_RFS_MASK|AICSR_TUR_MASK|AICSR_ROR_MASK)
++#define AICSR_TFL_BIT		(8)
++#define AICSR_TFL_MASK		(0x3f << AICSR_TFL_BIT)
++#define AICSR_RFL_BIT		(24)
++#define AICSR_RFL_MASK		(0x3f << AICSR_RFL_BIT)
++
++/* For ACSR */
++#define ACSR_CADT_BIT		(16)
++#define ACSR_CADT_MASK		(1 << ACSR_CADT_BIT)
++#define ACSR_SADR_BIT		(17)
++#define ACSR_SADR_MASK		(1 << ACSR_SADR_BIT)
++#define ACSR_RSTO_BIT		(18)
++#define ACSR_RSTO_MASK		(1 << ACSR_RSTO_BIT)
++#define ACSR_CLPM_BIT		(19)
++#define ACSR_CLPM_MASK		(1 << ACSR_CLPM_BIT)
++#define ACSR_CRDY_BIT		(20)
++#define ACSR_CRDY_MASK		(1 << ACSR_CRDY_BIT)
++#define ACSR_SLTERR_BIT		(21)
++#define ACSR_SLTERR_MASK	(1 << ACSR_SLTERR_BIT)
++
++/* For I2SSR */
++#define I2SSR_BSY_BIT		(2)
++#define I2SSR_BSY_MASK		(1 << I2SSR_BSY_BIT)
++#define I2SSR_RBSY_BIT		(3)
++#define I2SSR_RBSY_MASK		(1 << I2SSR_RBSY_BIT)
++#define I2SSR_TBSY_BIT		(4)
++#define I2SSR_TBSY_MASK		(1 << I2SSR_TBSY_BIT)
++#define I2SSR_CHBSY_BIT		(5)
++#define I2SSR_CHBSY_MASK	(1 << I2SSR_CHBSY_BIT)
++
++/* For ACCAR */
++#define ACCAR_CAR_BIT		(0)
++#define ACCAR_CAR_MASK		(0xfffff << ACCAR_CAR_BIT)
++
++/* For ACCDR */
++#define ACCDR_CDR_BIT		(0)
++#define ACCDR_CDR_MASK		(0xfffff << ACCDR_CDR_BIT)
++
++/* For ACSAR */
++#define ACSAR_SAR_BIT		(0)
++#define ACSAR_SAR_MASK		(0xfffff << ACSAR_SAR_BIT)
++
++/* For ACSDR */
++#define ACSDR_SDR_BIT		(0)
++#define ACSDR_SDR_MASK		(0xfffff << ACSDR_SDR_BIT)
++
++/* For I2SDIV */
++#define I2SDIV_DV_BIT		(0)
++#define I2SDIV_DV_MASK		(0x1ff << I2SDIV_DV_BIT)
++#define I2SDIV_IDV_BIT		(16)
++#define I2SDIV_IDV_MASK		(0x1ff << I2SDIV_IDV_BIT)
++
++/* For AICDR */
++#define AICDR_DATA_BIT		(0)
++#define AICDR_DATA_MASK		(0xfffffff << AICDR_DATA_BIT)
++
++/* For SPENA */
++#define	SPENA_SPEN_BIT		(0)
++#define SPENA_SPEN_MASK		(1 << SPENA_SPEN_BIT)
++
++/* For AICTFLR */
++#define AICTFLR_TFTH_BIT		(0)
++#define AICTFLR_TFTH_MASK		(0xf << AICTFLR_TFTH_BIT)
++
++/* For SPCTRL */
++#define SPCTRL_M_FFUR_BIT	(0)
++#define SPCTRL_M_FFUR_MASK	(1 << SPCTRL_M_FFUR_BIT)
++#define SPCTRL_M_TRIG_BIT	(1)
++#define SPCTRL_M_TRIG_MASK	(1 << SPCTRL_M_TRIG_BIT)
++#define SPCTRL_SPDIF_I2S_BIT	(10)
++#define SPCTRL_SPDIF_I2S_MASK	(1 << SPCTRL_SPDIF_I2S_BIT)
++#define SPCTRL_SFT_RST_BIT	(11)
++#define SPCTRL_SFT_RST_MASK	(1 << SPCTRL_SFT_RST_BIT)
++#define SPCTRL_INVALID_BIT	(12)
++#define SPCTRL_INVALID_MASK	(1 << SPCTRL_INVALID_BIT)
++#define SPCTRL_SIGN_N_BIT	(13)
++#define SPCTRL_SIGN_N_MASK	(1 << SPCTRL_SIGN_N_BIT)
++#define SPCTRL_D_TYPE_BIT	(14)
++#define SPCTRL_D_TYPE_MASK	(1 << SPCTRL_D_TYPE_BIT)
++#define SPCTRL_DMA_EN_BIT	(15)
++#define SPCTRL_DMA_EN_MASK	(1 << SPCTRL_DMA_EN_BIT)
++
++/* For SPSTATE */
++#define SPSTATE_F_FFUR_BIT	(0)
++#define SPSTATE_F_FFUR_MASK	(1 << SPSTATE_F_FFUR_BIT)
++#define SPSTATE_F_TRIG_BIT	(1)
++#define SPSTATE_F_TRIG_MASK	(1 << SPSTATE_F_TRIG_BIT)
++#define SPSTATE_BUSY_BIT	(7)
++#define SPSTATE_BUSY_MASK	(1 << SPSTATE_BUSY_BIT)
++#define SPSTATE_FIFO_LVL_BIT	(8)
++#define SPSTATE_FIFO_LVL_MASK	(0x7f << SPSTATE_FIFO_LVL_BIT)
++
++/* For SPCFG1 */
++#define SPCFG1_CH2_NUM_BIT	(0)
++#define SPCFG1_CH2_NUM_MASK	(0xf << SPCFG1_CH2_NUM_BIT)
++#define SPCFG1_CH1_NUM_BIT	(4)
++#define SPCFG1_CH1_NUM_MASK	(0xf << SPCFG1_CH1_NUM_BIT)
++#define SPCFG1_SRC_NUM_BIT	(8)
++#define SPCFG1_SRC_NUM_MASK	(0xf << SPCFG1_SRC_NUM_BIT)
++#define SPCFG1_TRIG_BIT		(12)
++#define SPCFG1_TRIG_MASK	(0x3 << SPCFG1_TRIG_BIT)
++#define SPCFG1_ZRO_VLD_BIT	(16)
++#define SPCFG1_ZRO_VLD_MASK	(1 << SPCFG1_ZRO_VLD_BIT)
++#define SPCFG1_INIT_LVL_BIT	(17)
++#define SPCFG1_INIT_LVL_MASK	(1 << SPCFG1_INIT_LVL_BIT)
++
++/* For SPCFG2 */
++#define SPCFG2_CON_PRO_BIT	(0)
++#define SPCFG2_CON_PRO_MASK	(1 << SPCFG2_CON_PRO_BIT)
++#define SPCFG2_AUDIO_N_BIT	(1)
++#define SPCFG2_AUDIO_N_MASK	(1 << SPCFG2_AUDIO_N_BIT)
++#define SPCFG2_COPY_N_BIT	(2)
++#define SPCFG2_COPY_N_MASK	(1 << SPCFG2_COPY_N_BIT)
++#define SPCFG2_PRE_BIT		(3)
++#define SPCFG2_PRE_MASK		(1 << SPCFG2_PRE_BIT)
++#define SPCFG2_CH_MD_BIT	(6)
++#define SPCFG2_CH_MD_MASK	(0x3 << SPCFG2_CH_MD_BIT)
++#define SPCFG2_CAT_CODE_BIT	(8)
++#define SPCFG2_CAT_CODE_MASK	(0xff << SPCFG2_CAT_CODE_BIT)
++#define SPCFG2_CLK_ACU_BIT	(16)
++#define SPCFG2_CLK_ACU_MASK	(0x3 << SPCFG2_CLK_ACU_BIT)
++#define SPCFG2_MAX_WL_BIT	(18)
++#define SPCFG2_MAX_WL_MASK	(1 << SPCFG2_MAX_WL_BIT)
++#define SPCFG2_SAMPL_WL_BIT	(19)
++#define SPCFG2_SAMPL_WL_MASK	(0x7 << SPCFG2_SAMPL_WL_BIT)
++#define SPCFG2_SAMPL_WL_20BITM	(0x1 << SPCFG2_SAMPL_WL_BIT)
++#define SPCFG2_SAMPL_WL_21BIT	(0x6 << SPCFG2_SAMPL_WL_BIT)
++#define SPCFG2_SAMPL_WL_22BIT	(0x2 << SPCFG2_SAMPL_WL_BIT)
++#define SPCFG2_SAMPL_WL_23BIT	(0x4 << SPCFG2_SAMPL_WL_BIT)
++#define SPCFG2_SAMPL_WL_24BIT	(0x5 << SPCFG2_SAMPL_WL_BIT)
++#define SPCFG2_SAMPL_WL_16BIT	(0x1 << SPCFG2_SAMPL_WL_BIT)
++#define SPCFG2_SAMPL_WL_17BIT	(0x6 << SPCFG2_SAMPL_WL_BIT)
++#define SPCFG2_SAMPL_WL_18BIT	(0x2 << SPCFG2_SAMPL_WL_BIT)
++#define SPCFG2_SAMPL_WL_19BIT	(0x4 << SPCFG2_SAMPL_WL_BIT)
++#define SPCFG2_SAMPL_WL_20BITL	(0x5 << SPCFG2_SAMPL_WL_BIT)
++#define SPCFG2_ORG_FRQ_BIT	(22)
++#define SPCFG2_ORG_FRQ_MASK	(0xf << SPCFG2_ORG_FRQ_BIT)
++#define SPCFG2_FS_BIT		(26)
++#define SPCFG2_FS_MASK		(0xf << SPCFG2_FS_BIT)
++
++#define SPFIFO_DATA_BIT		(0)
++#define SPFIFO_DATA_MASK	(0xffffff << SPFIFO_DATA_BIT)
++
++#define ingenic_aic_set_reg(parent, addr, val, mask, offset)		\
++	do {							\
++		volatile unsigned int reg_tmp;				\
++		reg_tmp = ingenic_aic_read_reg(parent, addr);	\
++		reg_tmp &= ~(mask);				\
++		reg_tmp |= (val << offset) & mask;		\
++		ingenic_aic_write_reg(parent, addr, reg_tmp);	\
++	} while(0)
++
++/*
++ * Fix: FIFO status is not updated in time, And
++ * needs to be read twice to obtain the real value.
++ */
++#define ingenic_aic_get_reg(parent, addr, mask, offset)			\
++({									\
++	u32 reg = 0;							\
++	if (addr == AICSR) {						\
++		ingenic_aic_read_reg(parent, addr);			\
++	}								\
++	reg = (ingenic_aic_read_reg(parent, addr) & mask) >> offset;	\
++	reg;								\
++})
++
++/*For ALL*/
++/*aic fr*/
++#define __aic_enable_msb(parent)		\
++	ingenic_aic_set_reg(parent, AICFR, 1, AICFR_MSB_MASK, AICFR_MSB_BIT)
++#define __aic_disable_msb(parent)		\
++	ingenic_aic_set_reg(parent, AICFR, 0, AICFR_MSB_MASK, AICFR_MSB_BIT)
++#define __aic_reset(parent)	\
++	ingenic_aic_set_reg(parent, AICFR, 1, AICFR_RST_MASK, AICFR_RST_BIT)
++/*aic cr*/
++#define __aic_flush_rxfifo(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_RFLUSH_MASK, AICCR_RFLUSH_BIT)
++#define __aic_flush_txfifo(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_TFLUSH_MASK, AICCR_TFLUSH_BIT)
++#define __aic_en_ror_int(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_EROR_MASK, AICCR_EROR_BIT)
++#define __aic_dis_ror_int(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_EROR_MASK, AICCR_EROR_BIT)
++#define __aic_en_tur_int(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_ETUR_MASK, AICCR_ETUR_BIT)
++#define __aic_dis_tur_int(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_ETUR_MASK, AICCR_ETUR_BIT)
++#define __aic_en_rfs_int(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_ERFS_MASK, AICCR_ERFS_BIT)
++#define __aic_dis_rfs_int(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_ERFS_MASK, AICCR_ERFS_BIT)
++#define __aic_en_tfs_int(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_ETFS_MASK, AICCR_ETFS_BIT)
++#define __aic_dis_tfs_int(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_ETFS_MASK, AICCR_ETFS_BIT)
++#define __aic_get_irq_enmask(parent)	\
++	ingenic_aic_get_reg(parent, AICCR, AICCR_EALL_INT_MASK, AICCR_ETFS_BIT)
++#define __aic_set_irq_enmask(parent, mask)	\
++	ingenic_aic_set_reg(parent, AICCR, mask, AICCR_EALL_INT_MASK, AICCR_ETFS_BIT)
++/*aic sr*/
++#define __aic_read_rfl(parent)		\
++	ingenic_aic_get_reg(parent, AICSR ,AICSR_RFL_MASK, AICSR_RFL_BIT)
++#define __aic_read_tfl(parent)		\
++	ingenic_aic_get_reg(parent, AICSR, AICSR_TFL_MASK, AICSR_TFL_BIT)
++#define __aic_clear_ror(parent)		\
++	ingenic_aic_set_reg(parent, AICSR, 0, AICSR_ROR_MASK, AICSR_ROR_BIT)
++#define __aic_test_ror(parent)		\
++	ingenic_aic_get_reg(parent, AICSR, AICSR_ROR_MASK, AICSR_ROR_BIT)
++#define __aic_clear_tur(parent)		\
++	ingenic_aic_set_reg(parent, AICSR, 0, AICSR_TUR_MASK, AICSR_TUR_BIT)
++#define __aic_test_tur(parent)		\
++	ingenic_aic_get_reg(parent, AICSR, AICSR_TUR_MASK, AICSR_TUR_BIT)
++#define __aic_clear_rfs(parent)		\
++	ingenic_aic_set_reg(parent, AICSR, 0, AICSR_RFS_MASK, AICSR_RFS_BIT)
++#define __aic_test_rfs(parent)		\
++	ingenic_aic_get_reg(parent, AICSR, AICSR_RFS_MASK, AICSR_RFS_BIT)
++#define __aic_clear_tfs(parent)		\
++	ingenic_aic_set_reg(parent, AICSR, 0, AICSR_TFS_MASK, AICSR_TFS_BIT)
++#define __aic_test_tfs(parent)		\
++	ingenic_aic_get_reg(parent, AICSR, AICSR_TFS_MASK, AICSR_TFS_BIT)
++#define __aic_get_irq_flag(parent)	\
++	ingenic_aic_get_reg(parent, AICSR, AICSR_ALL_INT_MASK, AICSR_TFS_BIT)
++#define __aic_clear_all_irq_flag(parent)	\
++	ingenic_aic_set_reg(parent, AICSR, AICSR_ALL_INT_MASK, AICSR_ALL_INT_MASK, AICSR_TFS_BIT)
++/* aic dr*/
++#define __aic_write_txfifo(parent, n)	\
++	ingenic_aic_write_reg(parent, AICDR, (n))
++#define __aic_read_rxfifo(parent)	\
++	ingenic_aic_read_reg(parent, AICDR)
++/* For SPFIFO */
++#define __spdif_test_underrun(parent)     \
++	ingenic_aic_get_reg(parent, SPSTATE, SPSTATE_F_FFUR_MASK, SPSTATE_F_FFUR_BIT)
++#define __spdif_clear_underrun(parent)     \
++	ingenic_aic_set_reg(parent, SPSTATE, 0, SPSTATE_F_FFUR_MASK, SPSTATE_F_FFUR_BIT)
++#define __spdif_is_enable_transmit_dma(parent)    \
++	ingenic_aic_get_reg(parent, SPCTRL, SPCTRL_DMA_EN_MASK, SPCTRL_DMA_EN_BIT)
++#define __spdif_enable_transmit_dma(parent)    \
++	ingenic_aic_set_reg(parent, SPCTRL, 1, SPCTRL_DMA_EN_MASK, SPCTRL_DMA_EN_BIT)
++#define __spdif_disable_transmit_dma(parent)    \
++	ingenic_aic_set_reg(parent, SPCTRL, 0, SPCTRL_DMA_EN_MASK, SPCTRL_DMA_EN_BIT)
++#define __spdif_reset(parent)					\
++	ingenic_aic_set_reg(parent, SPCTRL, 1, SPCTRL_SFT_RST_MASK, SPCTRL_SFT_RST_BIT)
++#define __spdif_get_reset(parent)					\
++	ingenic_aic_get_reg(parent, SPCTRL,SPCTRL_SFT_RST_MASK, SPCTRL_SFT_RST_BIT)
++#define __spdif_enable(parent)					\
++	ingenic_aic_set_reg(parent, SPENA, 1, SPENA_SPEN_MASK, SPENA_SPEN_BIT)
++#define __spdif_disable(parent)					\
++	ingenic_aic_set_reg(parent, SPENA, 0, SPENA_SPEN_MASK, SPENA_SPEN_BIT)
++#define __spdif_set_dtype(parent, n)			\
++	ingenic_aic_set_reg(parent, SPCTRL, n, SPCTRL_D_TYPE_MASK, SPCTRL_D_TYPE_BIT)
++#define __spdif_set_trigger(parent, n)			\
++	ingenic_aic_set_reg(parent, SPCFG1, n, SPCFG1_TRIG_MASK, SPCFG1_TRIG_BIT)
++#define __spdif_set_ch1num(parent, n)		\
++	ingenic_aic_set_reg(parent, SPCFG1, n, SPCFG1_CH1_NUM_MASK, SPCFG1_CH1_NUM_BIT)
++#define __spdif_set_ch2num(parent, n)		\
++	ingenic_aic_set_reg(parent, SPCFG1, n, SPCFG1_CH2_NUM_MASK, SPCFG1_CH2_NUM_BIT)
++#define __spdif_set_srcnum(parent, n)		\
++	ingenic_aic_set_reg(parent, SPCFG1, n, SPCFG1_SRC_NUM_MASK, SPCFG1_SRC_NUM_BIT)
++#define __interface_select_spdif(parent)      \
++	ingenic_aic_set_reg(parent, SPCTRL, 1, SPCTRL_SPDIF_I2S_MASK, SPCTRL_SPDIF_I2S_BIT)
++#define __spdif_play_lastsample(parent)        \
++	ingenic_aic_set_reg(parent, SPCFG1, 1, SPCFG1_ZRO_VLD_MASK, SPCFG1_ZRO_VLD_BIT)
++#define __spdif_init_set_low(parent)			\
++	ingenic_aic_set_reg(parent, SPCFG1, 0, SPCFG1_INIT_LVL_MASK, SPCFG1_INIT_LVL_BIT)
++#define __spdif_choose_consumer(parent)					\
++	ingenic_aic_set_reg(parent, SPCFG2, 0, SPCFG2_CON_PRO_MASK, SPCFG2_CON_PRO_BIT)
++#define __spdif_clear_audion(parent)				\
++	ingenic_aic_set_reg(parent, SPCFG2, 0, SPCFG2_AUDIO_N_MASK, SPCFG2_AUDIO_N_BIT)
++#define __spdif_set_copyn(parent)					\
++	ingenic_aic_set_reg(parent, SPCFG2, 1, SPCFG2_COPY_N_MASK, SPCFG2_COPY_N_BIT)
++#define __spdif_clear_pre(parent)					\
++	ingenic_aic_set_reg(parent, SPCFG2, 0, SPCFG2_PRE_MASK, SPCFG2_PRE_BIT)
++#define __spdif_choose_chmd(parent)				\
++	ingenic_aic_set_reg(parent, SPCFG2, 0, SPCFG2_CH_MD_MASK, SPCFG2_CH_MD_BIT)
++#define __spdif_set_category_code_normal(parent)	\
++	ingenic_aic_set_reg(parent, SPCFG2, 0, SPCFG2_CAT_CODE_MASK, SPCFG2_CAT_CODE_BIT)
++#define __spdif_set_clkacu(parent, n)				\
++	ingenic_aic_set_reg(parent, SPCFG2, n, SPCFG2_CLK_ACU_MASK, SPCFG2_CLK_ACU_BIT)
++#define __spdif_set_sample_size(parent, n)		\
++	ingenic_aic_set_reg(parent, SPCFG2, n, SPCFG2_SAMPL_WL_MASK, SPCFG2_SAMPL_WL_BIT)
++#define __spdif_set_max_wl(parent, n)                           \
++	ingenic_aic_set_reg(parent, SPCFG2, n, SPCFG2_MAX_WL_MASK, SPCFG2_MAX_WL_BIT)
++#define	__spdif_set_ori_sample_freq(parent, org_frq_tmp)	\
++	ingenic_aic_set_reg(parent, SPCFG2, org_frq_tmp, SPCFG2_ORG_FRQ_MASK, SPCFG2_ORG_FRQ_BIT)
++#define	__spdif_set_sample_freq(parent, fs_tmp)			\
++	ingenic_aic_set_reg(parent, SPCFG2, fs_tmp, SPCFG2_FS_MASK, SPCFG2_FS_BIT)
++#define __spdif_set_valid(parent)				\
++	ingenic_aic_set_reg(parent, SPCTRL, 0, SPCTRL_INVALID_MASK, SPCTRL_INVALID_BIT)
++#define __spdif_mask_trig(parent)				\
++	ingenic_aic_set_reg(parent, SPCTRL, 1, SPCTRL_M_TRIG_MASK, SPCTRL_M_TRIG_BIT)
++#define __spdif_disable_underrun_intr(parent)  \
++	ingenic_aic_set_reg(parent, SPCTRL, 1, SPCTRL_M_FFUR_MASK, SPCTRL_M_FFUR_BIT)
++#define __spdif_set_signn(parent)                             \
++	ingenic_aic_set_reg(parent, SPCTRL, 1, SPCTRL_SIGN_N_MASK, SPCTRL_SIGN_N_BIT)
++#define __spdif_clear_signn(parent)                   \
++	ingenic_aic_set_reg(parent, SPCTRL, 0, SPCTRL_SIGN_N_MASK, SPCTRL_SIGN_N_BIT)
++
++/* For I2S */
++/*aic fr*/
++#define __i2s_is_enable(parent)	\
++	ingenic_aic_get_reg(parent, AICFR, AICFR_ENB_MASK, AICFR_ENB_BIT)
++#define __aic_enable(parent)			\
++	ingenic_aic_set_reg(parent, AICFR, 1, AICFR_ENB_MASK, AICFR_ENB_BIT)
++
++#define __aic_disable(parent)			\
++	ingenic_aic_set_reg(parent, AICFR, 0, AICFR_ENB_MASK, AICFR_ENB_BIT)
++
++#define __i2s_external_codec(parent)               \
++	ingenic_aic_set_reg(parent, AICFR, 0, AICFR_ICDC_MASK, AICFR_ICDC_BIT)
++
++#define __i2s_bclk_output(parent)            \
++	ingenic_aic_set_reg(parent, AICFR, 1, AICFR_BCKD_MASK, AICFR_BCKD_BIT)
++
++#define __i2s_bclk_input(parent)            \
++	ingenic_aic_set_reg(parent, AICFR, 0, AICFR_BCKD_MASK, AICFR_BCKD_BIT)
++
++#define __i2s_sync_output(parent)            \
++	ingenic_aic_set_reg(parent, AICFR, 1, AICFR_SYNCD_MASK, AICFR_SYNCD_BIT)
++
++#define __i2s_sync_input(parent)	\
++	ingenic_aic_set_reg(parent, AICFR, 0, AICFR_SYNCD_MASK, AICFR_SYNCD_BIT)
++
++#define __i2s_isync_input(parent)            \
++	ingenic_aic_set_reg(parent, AICFR , 0, AICFR_ISYNCD_MASK, AICFR_ISYNCD_BIT)
++
++#define __i2s_ibclk_input(parent)            \
++	ingenic_aic_set_reg(parent, AICFR, 0, AICFR_IBCKD_MASK, AICFR_IBCKD_BIT)
++
++#define __aic_select_i2s(parent)             \
++	ingenic_aic_set_reg(parent, AICFR, 1, AICFR_AUSEL_MASK, AICFR_AUSEL_BIT)
++
++#define __aic_select_internal_codec(parent)	\
++	ingenic_aic_set_reg(parent, AICFR, 1, AICFR_ICDC_MASK, AICFR_ICDC_BIT)
++
++#define __aic_select_external_codec(parent)	\
++	ingenic_aic_set_reg(parent, AICFR, 0, AICFR_ICDC_MASK, AICFR_ICDC_BIT)
++
++#define __i2s_play_zero(parent)              \
++	ingenic_aic_set_reg(parent, AICFR, 0, AICFR_LSMP_MASK, AICFR_LSMP_BIT)
++
++#define __i2s_play_lastsample(parent)        \
++	ingenic_aic_set_reg(parent, AICFR, 1, AICFR_LSMP_MASK, AICFR_LSMP_BIT)
++
++#define __i2s_codec_slave(parent)	\
++	ingenic_aic_set_reg(parent, AICFR, 1, AICFR_CDC_SLV_MASK, AICFR_CDC_SLV_BIT)
++
++#define __i2s_codec_master(parent)	\
++	ingenic_aic_set_reg(parent, AICFR, 0, AICFR_CDC_SLV_MASK, AICFR_CDC_SLV_BIT)
++
++#define __i2s_select_sysclk_output(parent)	\
++	ingenic_aic_set_reg(parent, AICFR, 0, AICFR_SYSCLKD_MASK, AICFR_SYSCLKD_BIT)
++
++#define __i2s_select_sysclk_input(parent)	\
++	ingenic_aic_set_reg(parent, AICFR, 1, AICFR_SYSCLKD_MASK, AICFR_SYSCLKD_BIT)
++
++#define __i2s_set_transmit_trigger(parent, n)  \
++	ingenic_aic_set_reg(parent, AICFR, n, AICFR_TFTH_MASK, AICFR_TFTH_BIT)
++
++#define __i2s_set_receive_trigger(parent, n)   \
++	ingenic_aic_set_reg(parent, AICFR, n, AICFR_RFTH_MASK, AICFR_RFTH_BIT)
++
++#define __i2s_set_tfifo_loop_trigger(parent, n)   \
++	ingenic_aic_set_reg(parent, AICTFLR, n, AICTFLR_TFTH_MASK, AICTFLR_TFTH_BIT)
++/*aiccr*/
++#define I2S_SS2REG(n)   (((n) > 18 ? (n)/6 : (n)/9))	/* n = 8, 16, 18, 20, 24 */
++#define __i2s_aic_packet16(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_PACK16_MASK, AICCR_PACK16_BIT)
++#define __i2s_aic_unpacket16(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_PACK16_MASK, AICCR_PACK16_BIT)
++#define __i2s_channel(parent, n)	\
++	ingenic_aic_set_reg(parent, AICCR, ((n) - 1), AICCR_CHANNEL_MASK, AICCR_CHANNEL_BIT)
++#define __i2s_set_oss(parent, n)	\
++	ingenic_aic_set_reg(parent, AICCR, I2S_SS2REG(n) , AICCR_OSS_MASK, AICCR_OSS_BIT)
++#define __i2s_set_iss(parent, n)	\
++	ingenic_aic_set_reg(parent, AICCR, I2S_SS2REG(n) , AICCR_ISS_MASK, AICCR_ISS_BIT)
++#define __i2s_transmit_dma_is_enable(parent)	\
++	ingenic_aic_get_reg(parent, AICCR, AICCR_TDMS_MASK,AICCR_TDMS_BIT)
++#define __i2s_disable_transmit_dma(parent)			\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_TDMS_MASK, AICCR_TDMS_BIT)
++#define __i2s_enable_transmit_dma(parent)			\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_TDMS_MASK, AICCR_TDMS_BIT)
++#define __i2s_receive_dma_is_enable(parent)	\
++	ingenic_aic_get_reg(parent, AICCR, AICCR_RDMS_MASK,AICCR_RDMS_BIT)
++#define __i2s_disable_receive_dma(parent)			\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_RDMS_MASK, AICCR_RDMS_BIT)
++#define __i2s_enable_receive_dma(parent)			\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_RDMS_MASK, AICCR_RDMS_BIT)
++#define __i2s_m2s_enable(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_M2S_MASK, AICCR_M2S_BIT)
++#define __i2s_m2s_disable(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_M2S_MASK, AICCR_M2S_BIT)
++#define __i2s_endsw_enable(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_ENDSW_MASK, AICCR_ENDSW_BIT)
++#define __i2s_endsw_disable(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_ENDSW_MASK, AICCR_ENDSW_BIT)
++#define __i2s_asvtsu_enable(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_ASVTSU_MASK, AICCR_ASVTSU_BIT)
++#define __i2s_asvtsu_disable(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_ASVTSU_MASK, AICCR_ASVTSU_BIT)
++#define __i2s_enable_replay(parent)				\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_ERPL_MASK, AICCR_ERPL_BIT)
++#define __i2s_enable_record(parent)				\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_EREC_MASK, AICCR_EREC_BIT)
++#define __i2s_enable_loopback(parent)				\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_ENLBF_MASK, AICCR_ENLBF_BIT)
++#define __i2s_disable_replay(parent)				\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_ERPL_MASK, AICCR_ERPL_BIT)
++#define __i2s_disable_record(parent)				\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_EREC_MASK, AICCR_EREC_BIT)
++#define __i2s_disable_loopback(parent)				\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_ENLBF_MASK, AICCR_ENLBF_BIT)
++#define __i2s_enable_monoctr_left(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 2, AICCR_STEREOCTR_MASK, AICCR_MONOCTR_RIGHT_OFFSET)
++#define __i2s_disable_monoctr_left(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_STEREOCTR_MASK, AICCR_MONOCTR_RIGHT_OFFSET)
++#define __i2s_enable_monoctr_right(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_STEREOCTR_MASK, AICCR_MONOCTR_RIGHT_OFFSET)
++#define __i2s_disable_monoctr_right(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_STEREOCTR_MASK, AICCR_MONOCTR_RIGHT_OFFSET)
++#define __i2s_enable_stereo(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_STEREOCTR_MASK, AICCR_MONOCTR_RIGHT_OFFSET)
++#define __i2s_enable_tloop(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_TLDMS_MASK, AICCR_TLDMS_OFFSET)
++#define __i2s_disable_tloop(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_TLDMS_MASK, AICCR_TLDMS_OFFSET)
++#define __i2s_enable_etfl(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_ETFL_MASK, AICCR_ETFL_OFFSET)
++#define __i2s_disable_etfl(parent)	\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_ETFL_MASK, AICCR_ETFL_OFFSET)
++/*i2scr*/
++#define __i2s_select_i2s_fmt(parent)	\
++	ingenic_aic_set_reg(parent, I2SCR, 0, I2SCR_AMSL_MASK, I2SCR_AMSL_BIT)
++#define __i2s_select_msb_fmt(parent)	\
++	ingenic_aic_set_reg(parent, I2SCR, 1, I2SCR_AMSL_MASK, I2SCR_AMSL_BIT)
++#define __i2s_enable_sysclk_output(parent)   \
++	ingenic_aic_set_reg(parent, I2SCR, 1, I2SCR_ESCLK_MASK, I2SCR_ESCLK_BIT)
++#define __i2s_disable_sysclk_output(parent)  \
++	ingenic_aic_set_reg(parent, I2SCR, 0, I2SCR_ESCLK_MASK, I2SCR_ESCLK_BIT)
++#define __i2s_send_rfirst(parent)            \
++	ingenic_aic_set_reg(parent, I2SCR, 1, I2SCR_RFIRST_MASK, I2SCR_RFIRST_BIT)
++#define __i2s_stop_bitclk(parent)            \
++	ingenic_aic_set_reg(parent, I2SCR, 1, I2SCR_STPBK_MASK, I2SCR_STPBK_BIT)
++#define __i2s_start_bitclk(parent)		\
++	ingenic_aic_set_reg(parent, I2SCR, 0, I2SCR_STPBK_MASK, I2SCR_STPBK_BIT)
++#define __i2s_select_packed_lrswap(parent)	\
++	ingenic_aic_set_reg(parent, I2SCR, 1, I2SCR_SWLH_MASK, I2SCR_SWLH_BIT)
++#define __i2s_select_packed_lrnorm(parent)	\
++	ingenic_aic_set_reg(parent, I2SCR, 0, I2SCR_SWLH_MASK, I2SCR_SWLH_BIT)
++#define __i2s_send_rfirst(parent)	\
++	ingenic_aic_set_reg(parent, I2SCR, 1, I2SCR_RFIRST_MASK, I2SCR_RFIRST_BIT)
++#define __i2s_send_lfirst(parent)	\
++	ingenic_aic_set_reg(parent, I2SCR, 0, I2SCR_RFIRST_MASK, I2SCR_RFIRST_BIT)
++/*i2ssr*/
++#define __i2s_transmiter_is_busy(parent)	\
++	(!!(ingenic_aic_read_reg(parent, I2SSR) & I2SSR_TBSY_MASK))
++#define __i2s_receiver_is_busy(parent)	\
++	(!!(ingenic_aic_read_reg(parent, I2SSR) & I2SSR_TBSY_MASK))
++
++#define __i2s_slave_clkset(parent)        \
++	do {                                            \
++		__i2s_bclk_input(parent);                    \
++		__i2s_sync_input(parent);                    \
++		__i2s_isync_input(parent);                   \
++		__i2s_ibclk_input(parent);                   \
++	}while(0)
++
++#define __i2s_master_clkset(parent)        \
++	do {                                            \
++		__i2s_bclk_output(parent);                    \
++		__i2s_sync_output(parent);                    \
++	}while(0)
++
++/*i2s_div*/
++#define __i2s_set_idv(parent, div)	\
++	ingenic_aic_set_reg(parent, I2SDIV, div, I2SDIV_IDV_MASK, I2SDIV_IDV_BIT)
++#define __i2s_set_dv(parent, div)	\
++	ingenic_aic_set_reg(parent, I2SDIV, div, I2SDIV_DV_MASK, I2SDIV_DV_BIT)
++
++/*AICTFLR*/
++#define AICFR_TFIFO_LOOP_OFFSET (0)
++#define AICFR_LOOP_DATA_OFFSET	(0)
++#define AICFR_TFIFO_LOOP_MASK   (0xf << AICFR_TFIFO_LOOP_OFFSET)
++
++#define __i2s_read_tfifo_loop(parent)		\
++	ingenic_aic_set_reg_get_reg(parent, AICTFLR, AICFR_TFIFO_LOOP_MASK, AICFR_LOOP_DATA_OFFSET)
++#define __i2s_write_tfifo_loop(parent, v)	\
++	ingenic_aic_set_reg(parent, AICTFLR, v, AICFR_TFIFO_LOOP_MASK, AICFR_LOOP_DATA_OFFSET)
++
++/* xzhang add */
++#define AICFR_RMASTER_BIT	(1)
++#define AICFR_RMASTER_MASK	(1 << AICFR_RMASTER_BIT)
++#define AICFR_TMASTER_BIT	(2)
++#define AICFR_TMASTER_MASK	(1 << AICFR_TMASTER_BIT)
++#define AICCR_MONOCTRL_BIT	(12)
++#define AICCR_MONOCTRL_MASK	(0x3 << AICCR_MONOCTRL_BIT)
++
++#define __i2s_codec_record_slave(parent)            \
++	ingenic_aic_set_reg(parent, AICFR, 0, AICFR_RMASTER_MASK, AICFR_RMASTER_BIT)
++
++#define __i2s_codec_record_master(parent)	\
++	ingenic_aic_set_reg(parent, AICFR, 1, AICFR_RMASTER_MASK, AICFR_RMASTER_BIT)
++
++#define __i2s_codec_playback_slave(parent)            \
++	ingenic_aic_set_reg(parent, AICFR, 0, AICFR_TMASTER_MASK, AICFR_TMASTER_BIT)
++
++#define __i2s_codec_playback_master(parent)            \
++	ingenic_aic_set_reg(parent, AICFR, 1, AICFR_TMASTER_MASK, AICFR_TMASTER_BIT)
++
++#define __i2s_independent_clk(parent)	\
++	ingenic_aic_set_reg(parent, AICFR, 1, AICFR_DMODE_MASK, AICFR_DMODE_BIT)
++#define __i2s_share_clk(parent)	\
++	ingenic_aic_set_reg(parent, AICFR, 0, AICFR_DMODE_MASK, AICFR_DMODE_BIT)
++
++#define __i2s_record_left_right_channel_work(parent)			\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_MONOCTRL_MASK, AICCR_MONOCTRL_BIT)
++#define __i2s_record_right_channel_work(parent)			\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_MONOCTRL_MASK, AICCR_MONOCTRL_BIT)
++#define __i2s_record_left_channel_work(parent)			\
++	ingenic_aic_set_reg(parent, AICCR, 2, AICCR_MONOCTRL_MASK, AICCR_MONOCTRL_BIT)
++
++#define __i2s_enable_tfifo_loop(parent)				\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_ETFL_MASK, AICCR_ETFL_OFFSET)
++#define __i2s_disable_tfifo_loop(parent)				\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_ETFL_MASK, AICCR_ETFL_OFFSET)
++
++#define __i2s_enable_tfifo_loop_dma(parent)				\
++	ingenic_aic_set_reg(parent, AICCR, 1, AICCR_TLDMS_MASK, AICCR_TLDMS_OFFSET)
++#define __i2s_disable_tfifo_loop_dma(parent)				\
++	ingenic_aic_set_reg(parent, AICCR, 0, AICCR_TLDMS_MASK, AICCR_TLDMS_OFFSET)
++
++/* xzhang add */
++
++#endif  /*__ASOC_AIC_H__*/
+diff --git a/module_drivers/sound/soc/ingenic/as-v1/asoc-dma.c b/module_drivers/sound/soc/ingenic/as-v1/asoc-dma.c
+new file mode 100644
+index 000000000..9a2ebbfb8
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v1/asoc-dma.c
+@@ -0,0 +1,744 @@
++/*
++ *  sound/soc/ingenic/asoc-dma.c
++ *  ALSA Soc Audio Layer -- ingenic audio dma platform driver
++ *
++ *  Copyright 2014 Ingenic Semiconductor Co.,Ltd
++ *	cli <chen.li@ingenic.com>
++ *
++ *  This program is free software; you can redistribute  it and/or modify it
++ *  under  the terms of  the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the  License, or (at your
++ *  option) any later version.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/spinlock.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/mm.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <sound/soc.h>
++#include <sound/pcm.h>
++#include <sound/soc-dai.h>
++#include <sound/pcm_params.h>
++#include <sound/dmaengine_pcm.h>
++#include <linux/of.h>
++#include <linux/of_dma.h>
++#include <linux/delay.h>
++#include "asoc-dma.h"
++#include "asoc-aic.h"
++#include "assert.h"
++
++#ifndef CONFIG_SND_X1600_AIC_IF_SEND_INVALID_DATA
++#define SEND_INVALID_DATA 0
++#else
++#define SEND_INVALID_DATA 1
++#endif
++
++#ifndef CONFIG_SND_X1600_AIC_IF_SEND_INVALID_DATA_EVERYTIME
++#define SEND_INVALID_DATA_EVERYTIME 0
++#else
++#define SEND_INVALID_DATA_EVERYTIME 1
++#endif
++
++#ifndef CONFIG_SND_X1600_AIC_SEND_INVALID_DATA_TIME_MS
++#define CONFIG_SND_X1600_AIC_SEND_INVALID_DATA_TIME_MS (0)
++#endif
++
++static int aic_if_send_invalid_data;
++static int aic_if_send_invalid_data_everytime;
++static int aic_send_invalid_data_time_ms;
++
++static int asoc_dma_debug = 0;
++module_param(asoc_dma_debug, int, 0644);
++
++#define DMA_DEBUG_MSG(msg...)			\
++	do {					\
++		if (asoc_dma_debug)		\
++			printk(KERN_DEBUG"ADMA: " msg);	\
++	} while(0)
++#define DMA_SUBSTREAM_MSG(substream, msg...)	\
++	do {					\
++		if (asoc_dma_debug) {		\
++			printk(KERN_DEBUG"ADMA[%s][%s]:", \
++					substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? \
++					"replay" : "record",	\
++					substream->pcm->id);	\
++			printk(KERN_DEBUG msg);		\
++		} \
++	} while(0)
++
++#define INGENIC_DMA_BUFFERSIZE_PREALLOC (32 * 1024)
++#define INGENIC_DMA_BUFFERSIZE_MAX (128 * 1024)
++struct ingenic_dma_pcm {
++	struct dma_chan *chan[SNDRV_PCM_STREAM_LAST + 1];
++	struct snd_soc_component_driver dai;
++	const struct snd_pcm_hardware *hardware;
++	unsigned int prealloc_buffersize;
++	int no_residue;
++};
++#define soc_platform_to_ingenicpcm(x) container_of(x, struct ingenic_dma_pcm, platform)
++
++#define BUFFER_ALIGN 32
++
++static inline void *pcm_alloc_coherent(struct device *dev, int size)
++{
++	dma_addr_t dma_handle;
++	void *mem = dma_alloc_coherent(dev, size, &dma_handle, GFP_KERNEL);
++	assert(mem);
++
++	return (void *)CKSEG0ADDR(mem);
++}
++
++static void pcm_start_playback(struct snd_pcm_substream *substream, struct device *aic)
++{
++	struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
++	int i;
++	int n;
++	int j;
++	mutex_lock(&aic->mutex);
++
++	__aic_enable(aic);
++	__i2s_enable_replay(aic);
++
++	for (i = 0; i < 32; i++) {
++		n = __aic_read_tfl(aic);
++		if (n > 32)
++			break;
++		__aic_write_txfifo(aic, 0);
++	}
++
++	__aic_clear_tur(aic);
++	__aic_flush_txfifo(aic);
++	int timeout = 1000;
++	while (__aic_read_tfl(aic)) {
++		printk("__aic_read_tfl(aic) = %x\n",__aic_read_tfl(aic));
++		if (--timeout < 0)
++			panic("AIC: failed to wait tx fifo empty: %x\n", ingenic_aic_read_reg(aic, AICSR));
++	}
++
++	__i2s_enable_transmit_dma(aic);
++	mutex_unlock(&aic->mutex);
++}
++
++static void pcm_stop_playback(struct snd_pcm_substream *substream, struct device *aic)
++{
++	int timeout = 15;
++
++	mutex_lock(&aic->mutex);
++	__i2s_disable_transmit_dma(aic);
++	__i2s_disable_replay(aic);
++	__aic_flush_txfifo(aic);
++	while (__aic_read_tfl(aic)) {
++		mdelay(1);
++		if (--timeout < 0)
++			panic("AIC: failed to wait tx fifo empty: %x\n", ingenic_aic_read_reg(aic, AICSR));
++	}
++
++	__aic_disable(aic);
++	snd_pcm_period_elapsed(substream);
++	mutex_unlock(&aic->mutex);
++}
++
++int ingenic_pcm_invalid_data_cyclic(struct ingenic_pcm_runtime_data *prtd, unsigned char *dma_buf,unsigned int size,struct snd_pcm_hw_params *params)
++{
++	struct dma_async_tx_descriptor *desc;
++	enum dma_transfer_direction direction;
++
++	desc = prtd->dma_chan->device->device_prep_dma_cyclic(prtd->dma_chan,
++			(unsigned long)(void *)virt_to_phys(dma_buf), size, size,
++			DMA_MEM_TO_DEV, DMA_CTRL_ACK);
++	if (!desc) {
++		printk(KERN_ERR "AIC: Failed to prepare dma desc\n");
++		return -1;
++	}
++
++	desc->callback = NULL;
++	desc->callback_param = NULL;
++
++	dmaengine_submit(desc);
++	dma_async_issue_pending(prtd->dma_chan);
++
++	return 0;
++}
++
++static void ingenic_pcm_adapt_sequence(struct snd_soc_component *component,
++			struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)
++{
++	void *dma_buf;
++	dma_addr_t dma_handle;
++	struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
++	struct device *aic = component->dev;
++	struct ingenic_pcm_runtime_data *prtd = substream_to_prtd(substream);
++	struct snd_pcm *pcm = substream->pcm;
++	int period_size = params_period_size(params);
++
++	aic_if_send_invalid_data = SEND_INVALID_DATA;
++	aic_if_send_invalid_data_everytime = SEND_INVALID_DATA_EVERYTIME;
++	aic_send_invalid_data_time_ms = CONFIG_SND_X1600_AIC_SEND_INVALID_DATA_TIME_MS;
++
++	if (!aic_if_send_invalid_data){
++		printk("!aic_if_send_invalid_data\n");
++		return;
++	}
++
++	aic_clk_ctrl(aic, true);
++	dma_buf = pcm_alloc_coherent(aic, period_size);
++	memset(dma_buf, 0, period_size);
++//	dma_cache_sync(NULL, dma_buf, period_size, DMA_MEM_TO_DEV);
++
++	mutex_lock(&pcm->open_mutex);
++	pcm_start_playback(substream, aic);
++	ingenic_pcm_invalid_data_cyclic(prtd, dma_buf, period_size, params);
++	mutex_unlock(&pcm->open_mutex);
++
++	usleep_range(1000 * aic_send_invalid_data_time_ms, 1000 * aic_send_invalid_data_time_ms);
++
++	mutex_lock(&pcm->open_mutex);
++	dmaengine_terminate_all(prtd->dma_chan);
++	pcm_stop_playback(substream, aic);
++	mutex_unlock(&pcm->open_mutex);
++
++	dma_handle = virt_to_phys(dma_buf);
++	dma_free_coherent(aic, period_size, (void *)CKSEG1ADDR(dma_buf), dma_handle);
++
++	if (aic_if_send_invalid_data_everytime == 0){
++		aic_if_send_invalid_data = 0;
++		__aic_enable(aic);
++		aic_clk_ctrl(aic, false);
++	}
++}
++
++static int ingenic_pcm_hw_params(struct snd_soc_component *component,struct snd_pcm_substream *substream,
++		struct snd_pcm_hw_params *params)
++{
++	struct snd_pcm_substream *pcm_substream = substream;
++	struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
++	struct ingenic_pcm_runtime_data *prtd = substream_to_prtd(substream);
++	struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd,0);
++	struct snd_dmaengine_dai_dma_data *dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
++	struct dma_slave_config slave_config;
++	int ret;
++
++	DMA_SUBSTREAM_MSG(substream, "%s enter\n", __func__);
++
++	memset(&slave_config, 0, sizeof(slave_config));
++
++	ret = snd_hwparams_to_dma_slave_config(substream, params, &slave_config);
++	if (ret)
++		return ret;
++	snd_dmaengine_pcm_set_config_from_dai_data(substream, dma_data, &slave_config);
++
++	ret = dmaengine_slave_config(prtd->dma_chan, &slave_config);
++	if (ret)
++		return ret;
++
++	while (atomic_read(&prtd->wait_stopdma))
++		msleep(10);
++
++	prtd->stopdma_delayed_jiffies =  2 * (params_period_size(params) * HZ /params_rate(params));
++	ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
++	if (ret < 0)
++		return ret;
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++		ingenic_pcm_adapt_sequence(component, pcm_substream, params);
++	return 0;
++}
++
++static int ingenic_pcm_hw_free(struct snd_soc_component *component,struct snd_pcm_substream *substream)
++{
++	struct ingenic_pcm_runtime_data *prtd = substream_to_prtd(substream);
++
++	DMA_SUBSTREAM_MSG(substream, "%s enter\n", __func__);
++
++	while (atomic_read(&prtd->wait_stopdma))
++		msleep(10);
++
++	return snd_pcm_lib_free_pages(substream);
++}
++
++static int ingenic_pcm_prepare(struct snd_soc_component* component,struct snd_pcm_substream *substream)
++{
++	struct ingenic_pcm_runtime_data *prtd = substream_to_prtd(substream);
++
++	DMA_SUBSTREAM_MSG(substream, "%s enter\n", __func__);
++
++	while (atomic_read(&prtd->wait_stopdma))
++		msleep(10);
++
++	return 0;
++}
++
++static void ingenic_pcm_dma_complete(void *data)
++{
++	struct snd_pcm_substream *substream = data;
++	struct ingenic_pcm_runtime_data *prtd = substream_to_prtd(substream);
++
++	DMA_SUBSTREAM_MSG(substream,"%s enter period interrupt %d\n", __func__,
++			atomic_read(&prtd->wait_stopdma));
++
++	if (!atomic_dec_if_positive(&prtd->wait_stopdma)) {
++		struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
++		struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd,0);
++		dmaengine_terminate_all(prtd->dma_chan);
++		if (cpu_dai->driver->ops->trigger)
++			cpu_dai->driver->ops->trigger(substream, SNDRV_PCM_TRIGGER_STOP, cpu_dai);
++		cancel_delayed_work(&prtd->stopdma_delayed_work);
++		return;
++	}
++
++	if (prtd->file) {
++		prtd->copy_start = substream->runtime->dma_area + prtd->pos;
++		prtd->copy_length = snd_pcm_lib_period_bytes(substream);
++		if (work_pending(&prtd->debug_work))
++			printk(KERN_WARNING"debug file %s may loss data\n", prtd->file_name);
++		schedule_work(&prtd->debug_work);
++	}
++
++	prtd->pos += snd_pcm_lib_period_bytes(substream);
++	if (prtd->pos >= snd_pcm_lib_buffer_bytes(substream))
++		prtd->pos = 0;
++	snd_pcm_period_elapsed(substream);
++	return;
++}
++
++static int ingenic_pcm_prepare_and_submit(struct snd_pcm_substream *substream)
++{
++	struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
++	struct ingenic_pcm_runtime_data *prtd = substream_to_prtd(substream);
++	enum dma_transfer_direction direction;
++	struct dma_async_tx_descriptor *desc;
++	unsigned long flags = DMA_CTRL_ACK;
++
++	direction = snd_pcm_substream_to_dma_direction(substream);
++
++	if (!substream->runtime->no_period_wakeup)
++		flags |= DMA_PREP_INTERRUPT;
++
++	prtd->pos = 0;
++	desc = dmaengine_prep_dma_cyclic(prtd->dma_chan,
++			substream->runtime->dma_addr,
++			snd_pcm_lib_buffer_bytes(substream),
++			snd_pcm_lib_period_bytes(substream), direction, flags);
++	if (!desc) {
++		dev_err(rtd->dev, "cannot prepare slave dma\n");
++		return -ENOMEM;
++	}
++
++	desc->callback = ingenic_pcm_dma_complete;
++	desc->callback_param = substream;
++	prtd->cookie = dmaengine_submit(desc);
++	return 0;
++}
++
++static int ingenic_pcm_trigger(struct snd_soc_component *component,struct snd_pcm_substream *substream, int cmd)
++{
++	struct snd_pcm_runtime *runtime = substream->runtime;
++	struct ingenic_pcm_runtime_data *prtd = substream_to_prtd(substream);
++	int ret;
++
++	DMA_SUBSTREAM_MSG(substream,"%s enter cmd %d\n", __func__, cmd);
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++		if (atomic_read(&prtd->wait_stopdma))
++			return -EPIPE;
++
++		ret = ingenic_pcm_prepare_and_submit(substream);
++		if (ret)
++			return ret;
++		dma_async_issue_pending(prtd->dma_chan);
++		break;
++	case SNDRV_PCM_TRIGGER_RESUME:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		dmaengine_resume(prtd->dma_chan);
++		break;
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++		if (runtime->info & SNDRV_PCM_INFO_PAUSE)
++			dmaengine_pause(prtd->dma_chan);
++		else
++			dmaengine_terminate_all(prtd->dma_chan);
++		break;
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++		dmaengine_pause(prtd->dma_chan);
++		break;
++	case SNDRV_PCM_TRIGGER_STOP:
++		if (atomic_read(&prtd->wait_stopdma))
++			schedule_delayed_work(&prtd->stopdma_delayed_work,
++					prtd->stopdma_delayed_jiffies);
++		break;
++	default:
++		return -EINVAL;
++	}
++	return 0;
++}
++
++static snd_pcm_uframes_t ingenic_pcm_pointer_no_residue(struct snd_pcm_substream *substream)
++{
++	struct ingenic_pcm_runtime_data *prtd = substream_to_prtd(substream);
++
++	return bytes_to_frames(substream->runtime, prtd->pos);
++}
++
++static snd_pcm_uframes_t ingenic_pcm_pointer_residue(struct snd_pcm_substream *substream)
++{
++	struct ingenic_pcm_runtime_data *prtd = substream_to_prtd(substream);
++	struct dma_tx_state state;
++	enum dma_status status;
++	size_t buf_size;
++	ssize_t pos = 0;
++
++	status = dmaengine_tx_status(prtd->dma_chan, prtd->cookie, &state);
++
++	if (status == DMA_IN_PROGRESS || status == DMA_PAUSED) {
++		buf_size = snd_pcm_lib_buffer_bytes(substream);
++		if (state.residue > 0 && state.residue <= buf_size)
++			pos = buf_size - state.residue;
++	}
++
++	DMA_SUBSTREAM_MSG(substream, "prtd->pos %x really pos %x\n", prtd->pos, pos);
++	return bytes_to_frames(substream->runtime, pos);
++}
++
++static snd_pcm_uframes_t ingenic_pcm_pointer(struct snd_soc_component *component,struct snd_pcm_substream *substream)
++{
++	struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
++	struct ingenic_dma_pcm *ingenic_pcm = snd_soc_component_get_drvdata(component);
++
++	if (ingenic_pcm->no_residue)
++		return ingenic_pcm_pointer_no_residue(substream);
++
++	return ingenic_pcm_pointer_residue(substream);
++}
++
++static void debug_work(struct work_struct *debug_work)
++{
++	struct ingenic_pcm_runtime_data *prtd =
++		container_of(debug_work, struct ingenic_pcm_runtime_data, debug_work);
++	if (!IS_ERR_OR_NULL(prtd->file)) {
++		prtd->old_fs = get_fs();
++		set_fs(KERNEL_DS);
++		vfs_write(prtd->file, prtd->copy_start,
++				prtd->copy_length,
++				&prtd->file_offset);
++		prtd->file_offset = prtd->file->f_pos;
++		set_fs(prtd->old_fs);
++	}
++}
++
++static void ingenic_pcm_open_debug_file(struct snd_pcm_substream *substream)
++{
++	struct ingenic_pcm_runtime_data *prtd = substream_to_prtd(substream);
++#ifdef CONFIG_ANDROID
++	char *file_dir = "/data";
++#else
++	char *file_dir = "/tmp";
++#endif
++	prtd->file_name = kzalloc(40*sizeof(char), GFP_KERNEL);
++	if (prtd->file_name) {
++		sprintf(prtd->file_name, "%s/%sd%is%i.pcm",
++				file_dir,
++				substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
++				"replay" : "record",
++				substream->pcm->device,
++				substream->number);
++		pr_info("open debug file %s \n", prtd->file_name);
++		prtd->file = filp_open(prtd->file_name,
++				O_RDWR | O_APPEND /*| O_CREAT*/, S_IRUSR | S_IWUSR);
++		if (IS_ERR(prtd->file)) {
++			kfree(prtd->file_name);
++			prtd->file_name = NULL;
++			prtd->file = NULL;
++			return;
++		}
++		pr_info("open debug %s success (Poor performance)\n",
++				prtd->file_name);
++		prtd->file_offset =prtd->file->f_pos;
++		INIT_WORK(&prtd->debug_work, debug_work);
++	}
++	return;
++}
++
++static void ingenic_pcm_close_debug_file(struct snd_pcm_substream *substream)
++{
++	struct ingenic_pcm_runtime_data *prtd = substream_to_prtd(substream);
++
++	if (!prtd || !prtd->file)
++		return;
++
++	flush_work(&prtd->debug_work);
++	filp_close(prtd->file, NULL);
++	kfree(prtd->file_name);
++	return;
++}
++
++static void stopdma_delayed_work(struct work_struct *work)
++{
++	struct ingenic_pcm_runtime_data *prtd = container_of(work, struct ingenic_pcm_runtime_data,
++			stopdma_delayed_work.work);
++
++	DMA_SUBSTREAM_MSG(prtd->substream,"%s delayed work stop dma %d\n", __func__, atomic_read(&prtd->wait_stopdma));
++	if (!atomic_dec_if_positive(&prtd->wait_stopdma)) {
++		struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(prtd->substream);
++		struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd,0);
++		dmaengine_terminate_all(prtd->dma_chan);
++		if (cpu_dai->driver->ops->trigger)
++			cpu_dai->driver->ops->trigger(prtd->substream, SNDRV_PCM_TRIGGER_STOP, cpu_dai);
++	}
++	return;
++}
++
++static int ingenic_pcm_open(struct snd_soc_component *component,struct snd_pcm_substream *substream)
++{
++	struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
++	struct snd_soc_component_driver *dai = component->driver;
++	struct ingenic_dma_pcm *ingenic_pcm = container_of(dai, struct ingenic_dma_pcm, dai);
++	struct dma_chan *chan = ingenic_pcm->chan[substream->stream];
++	struct dma_slave_caps dma_caps;
++	struct snd_pcm_hardware hw;
++	struct snd_dmaengine_dai_dma_data *dma_data;
++	struct ingenic_pcm_runtime_data *prtd = NULL;
++	u32 addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
++		BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
++		BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
++	int ret;
++
++	DMA_DEBUG_MSG("%s enter\n", __func__);
++	if (ingenic_pcm->hardware) {
++		ret = snd_soc_set_runtime_hwparams(substream, ingenic_pcm->hardware);
++		if (ret)
++			return ret;
++	} else {
++		int i;
++		struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd,0);
++		dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
++		memset(&hw, 0, sizeof(hw));
++		hw.buffer_bytes_max = INGENIC_DMA_BUFFERSIZE_MAX;
++		hw.period_bytes_max = (32 * 1024);
++		hw.period_bytes_min = 1024;
++		hw.periods_max = 64;	/*INGENIC PDMA LIMITE*/
++		hw.periods_min = 4;
++		hw.fifo_size = dma_data->fifo_size;
++		hw.info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
++			SNDRV_PCM_INFO_INTERLEAVED;
++		ret = dma_get_slave_caps(chan, &dma_caps);
++		if (ret == 0) {
++			if (dma_caps.residue_granularity <= DMA_RESIDUE_GRANULARITY_SEGMENT)
++				hw.info |= SNDRV_PCM_INFO_BATCH;
++			if (dma_caps.residue_granularity == DMA_RESIDUE_GRANULARITY_DESCRIPTOR)
++				ingenic_pcm->no_residue = 1;
++			if (dma_caps.cmd_pause)
++				hw.info |= SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME;
++			if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++				addr_widths = dma_caps.dst_addr_widths;
++			else
++				addr_widths = dma_caps.src_addr_widths;
++		}
++
++		for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
++			int bits = snd_pcm_format_physical_width(i);
++			switch (bits) {
++			case 8:
++			case 16:
++			case 24:
++			case 32:
++			case 64:
++				if (addr_widths & (1 << (bits / 8)))
++					hw.formats |= (1LL << i);
++				break;
++			default:
++				/* Unsupported types */
++				break;
++			}
++		}
++
++		ret = snd_soc_set_runtime_hwparams(substream, &hw);
++		if (ret)
++			return ret;
++	}
++
++	ret = snd_pcm_hw_constraint_integer(substream->runtime,
++			SNDRV_PCM_HW_PARAM_PERIODS);
++	if (ret < 0)
++		return ret;
++
++	prtd = kzalloc(sizeof(*prtd), GFP_KERNEL);
++	if (!prtd)
++		return -ENOMEM;
++
++	prtd->dma_chan = chan;
++	prtd->substream = substream;
++	INIT_DELAYED_WORK(&prtd->stopdma_delayed_work, stopdma_delayed_work);
++	prtd->stopdma_delayed_jiffies = 0;
++	atomic_set(&prtd->wait_stopdma, 0);
++	substream->runtime->private_data = prtd;
++
++//	ingenic_pcm_open_debug_file(substream);
++	return 0;
++}
++
++static int ingenic_pcm_close(struct snd_soc_component *component,struct snd_pcm_substream *substream)
++{
++	struct ingenic_pcm_runtime_data *prtd = substream_to_prtd(substream);
++
++	DMA_DEBUG_MSG("%s enter\n", __func__);
++
++	BUG_ON(atomic_read(&prtd->wait_stopdma));
++	flush_delayed_work(&prtd->stopdma_delayed_work);
++
++	ingenic_pcm_close_debug_file(substream);
++
++	substream->private_data = NULL;
++
++	kfree(prtd);
++	return 0;
++}
++
++/* struct snd_pcm_ops ingenic_pcm_ops = { */
++/* 	.open		= ingenic_pcm_open, */
++/* 	.close		= ingenic_pcm_close, */
++/* 	.ioctl		= snd_pcm_lib_ioctl, */
++/* 	.hw_params	= ingenic_pcm_hw_params, */
++/* 	.hw_free	= ingenic_pcm_hw_free, */
++/* 	.prepare	= ingenic_pcm_prepare, */
++/* 	.trigger	= ingenic_pcm_trigger, */
++/* 	.pointer	= ingenic_pcm_pointer, */
++/* }; */
++
++
++static void ingenic_pcm_free(struct snd_soc_component *component, struct snd_pcm *pcm)
++{
++	snd_pcm_lib_preallocate_free_for_all(pcm);
++}
++
++static int ingenic_pcm_new(struct snd_soc_component *component,struct snd_soc_pcm_runtime *rtd)
++{
++	struct snd_soc_component_driver *dai = component->driver;
++	struct ingenic_dma_pcm *ingenic_pcm = container_of(dai, struct ingenic_dma_pcm, dai);
++	struct snd_pcm_substream *substream;
++	int ret = -EINVAL;
++	int i;
++
++	DMA_DEBUG_MSG("%s enter\n", __func__);
++	for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE; i++) {
++		substream = rtd->pcm->streams[i].substream;
++		if (!substream)
++			continue;
++
++		if (!ingenic_pcm->chan[i]) {
++			dev_err(component->dev,
++					"Missing dma channel for stream: %d\n", i);
++			ret = -EINVAL;
++			goto err_free;
++		}
++
++		snd_pcm_lib_preallocate_pages(substream,
++				SNDRV_DMA_TYPE_DEV_IRAM,
++				ingenic_pcm->chan[i]->device->dev,
++				ingenic_pcm->prealloc_buffersize,
++				ingenic_pcm->hardware ?
++				ingenic_pcm->hardware->buffer_bytes_max :
++				INGENIC_DMA_BUFFERSIZE_MAX);
++	}
++	return 0;
++
++err_free:
++	dev_err(rtd->dev, "Failed to alloc dma buffer %d\n", ret);
++	ingenic_pcm_free(component, rtd->pcm);
++	return ret;
++}
++
++ static struct snd_soc_component_driver ingenic_pcm_platform_component = {
++ 	.open				= ingenic_pcm_open,
++ 	.close				= ingenic_pcm_close,
++ 	.hw_params			= ingenic_pcm_hw_params,
++ 	.hw_free			= ingenic_pcm_hw_free,
++ 	.prepare			= ingenic_pcm_prepare,
++ 	.trigger			= ingenic_pcm_trigger,
++ 	.pointer			= ingenic_pcm_pointer,
++ 	.pcm_construct        = ingenic_pcm_new,
++ 	.pcm_destruct       = ingenic_pcm_free,
++ };
++
++static void ingenic_pcm_release_dma_channel(struct ingenic_dma_pcm *ingenic_pcm)
++{
++	int i;
++
++	for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE; i++) {
++		if (!ingenic_pcm->chan[i])
++			continue;
++		dma_release_channel(ingenic_pcm->chan[i]);
++	}
++
++	return;
++}
++
++int ingenic_dma_pcm_register(struct device *dev,  const struct snd_dmaengine_pcm_config *config, struct ingenic_dma_pcm *ingenic_pcm)
++{
++	struct dma_chan *chan;
++	const char *name;
++	int ret, i;
++	const char * const ingenic_pcm_dma_channel_names[] = {
++		[SNDRV_PCM_STREAM_PLAYBACK] = "tx",
++		[SNDRV_PCM_STREAM_CAPTURE] = "rx",
++	};
++
++	ingenic_pcm = devm_kzalloc(dev, sizeof(struct ingenic_dma_pcm), GFP_KERNEL);
++	if (!ingenic_pcm)
++		return -ENOMEM;
++
++	if (config && config->pcm_hardware)
++		ingenic_pcm->hardware = config->pcm_hardware;
++
++	if (config && config->prealloc_buffer_size)
++		ingenic_pcm->prealloc_buffersize = config->prealloc_buffer_size;
++	else
++		ingenic_pcm->prealloc_buffersize = INGENIC_DMA_BUFFERSIZE_PREALLOC;
++
++	for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE; i++) {
++		if (config && config->chan_names[i])
++			name = config->chan_names[i];
++		else
++			name = ingenic_pcm_dma_channel_names[i];
++		chan = dma_request_slave_channel(dev, name);
++		if (IS_ERR(chan)) {
++			if (PTR_ERR(chan) == -EPROBE_DEFER)
++				return -EPROBE_DEFER;
++			ingenic_pcm->chan[i] = NULL;
++			dev_info(dev, "%s channel request failed\n", name);
++		} else {
++			ingenic_pcm->chan[i] = chan;
++		}
++	}
++
++	memcpy(&ingenic_pcm->dai, &ingenic_pcm_platform_component, sizeof(struct snd_soc_component_driver));
++
++	ret = devm_snd_soc_register_component(dev, &ingenic_pcm->dai,NULL,0);
++	if (ret) {
++		ingenic_pcm_release_dma_channel(ingenic_pcm);
++		dev_err(dev, "Failed to register platfrom\n");
++		return ret;
++	}
++	dev_info(dev, "Audio dma platfrom probe success\n");
++	return 0;
++}
++EXPORT_SYMBOL_GPL(ingenic_dma_pcm_register);
++
++void ingenic_dma_pcm_unregister(struct ingenic_dma_pcm *ingenic_pcm)
++{
++	ingenic_pcm_release_dma_channel(ingenic_pcm);
++	kfree(ingenic_pcm);
++	return;
++}
++EXPORT_SYMBOL_GPL(ingenic_dma_pcm_unregister);
++
++MODULE_DESCRIPTION("INGENIC ASOC Platform driver");
++MODULE_AUTHOR("cli<chen.li@ingenic.com>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-asoc-dma");
+diff --git a/module_drivers/sound/soc/ingenic/as-v1/asoc-dma.h b/module_drivers/sound/soc/ingenic/as-v1/asoc-dma.h
+new file mode 100644
+index 000000000..0576584a5
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v1/asoc-dma.h
+@@ -0,0 +1,31 @@
++#ifndef __ASOC_DMA_H__
++#define __ASOC_DMA_H__
++
++struct ingenic_pcm_runtime_data {
++	struct snd_pcm_substream *substream;
++	struct dma_chan *dma_chan;
++	dma_cookie_t cookie;
++	unsigned int pos;
++
++	/* some pdma can not be force stop, when a descriptor is transfering */
++	struct delayed_work stopdma_delayed_work;
++	unsigned long stopdma_delayed_jiffies;
++	atomic_t wait_stopdma;
++
++	/* debug interface just use in debug*/
++	void *copy_start;
++	unsigned int copy_length;
++	struct file *file;
++	loff_t file_offset;
++	mm_segment_t old_fs;
++	char* file_name;
++	struct work_struct debug_work;
++};
++
++static inline struct ingenic_pcm_runtime_data *substream_to_prtd(
++	const struct snd_pcm_substream *substream)
++{
++	return substream->runtime->private_data;
++}
++
++#endif
+diff --git a/module_drivers/sound/soc/ingenic/as-v1/asoc-dmic.c b/module_drivers/sound/soc/ingenic/as-v1/asoc-dmic.c
+new file mode 100644
+index 000000000..bc9c1bd9c
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v1/asoc-dmic.c
+@@ -0,0 +1,540 @@
++/*
++ *  sound/soc/ingenic/asoc-dmic.c
++ *  ALSA Soc Audio Layer -- ingenic dmic (part of aic controller) driver
++ *
++ *  Copyright 2014 Ingenic Semiconductor Co.,Ltd
++ *	syzhang <siyu.zhang@ingenic.com>
++ *
++ *  This program is free software; you can redistribute  it and/or modify it
++ *  under  the terms of  the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the  License, or (at your
++ *  option) any later version.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/initval.h>
++#include <linux/ctype.h>
++#include <linux/io.h>
++#include <sound/soc.h>
++#include <sound/soc-dai.h>
++#include <linux/slab.h>
++#include <linux/regulator/consumer.h>
++#include <sound/tlv.h>
++#include <linux/version.h>
++#include "asoc-dmic.h"
++#include "asoc-aic.h"
++
++static int ingenic_dmic_debug = 0;
++module_param(ingenic_dmic_debug, int, 0644);
++#define DMIC_DEBUG_MSG(msg...)			\
++	do {					\
++		if (ingenic_dmic_debug)		\
++			printk(KERN_DEBUG"dmic: " msg);	\
++	} while(0)
++
++#define DMIC_FIFO_DEPTH 64
++#define INGENIC_DMIC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
++#define INGENIC_DMIC_RATE (SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000)
++
++static void dump_registers(struct device *dev)
++{
++	struct ingenic_dmic *ingenic_dmic = dev_get_drvdata(dev);
++	pr_info("DMICCR0  %p : 0x%08x\n", (ingenic_dmic->vaddr_base+DMICCR0),dmic_read_reg(dev, DMICCR0));
++	pr_info("DMICGCR  %p : 0x%08x\n", (ingenic_dmic->vaddr_base+DMICGCR),dmic_read_reg(dev, DMICGCR));
++	pr_info("DMICIMR  %p : 0x%08x\n", (ingenic_dmic->vaddr_base+DMICIMR),dmic_read_reg(dev, DMICIMR));
++	pr_info("DMICINTCR  %p : 0x%08x\n", (ingenic_dmic->vaddr_base+DMICINTCR),dmic_read_reg(dev, DMICINTCR));
++	pr_info("DMICTRICR  %p : 0x%08x\n", (ingenic_dmic->vaddr_base+DMICTRICR),dmic_read_reg(dev, DMICTRICR));
++	pr_info("DMICTHRH  %p : 0x%08x\n", (ingenic_dmic->vaddr_base+DMICTHRH),dmic_read_reg(dev, DMICTHRH));
++	pr_info("DMICTHRL  %p : 0x%08x\n", (ingenic_dmic->vaddr_base+DMICTHRL),dmic_read_reg(dev, DMICTHRL));
++	pr_info("DMICTRIMMAX  %p : 0x%08x\n", (ingenic_dmic->vaddr_base+DMICTRIMMAX),dmic_read_reg(dev, DMICTRIMMAX));
++	pr_info("DMICTRINMAX  %p : 0x%08x\n", (ingenic_dmic->vaddr_base+DMICTRINMAX),dmic_read_reg(dev, DMICTRINMAX));
++	pr_info("DMICDR  %p : 0x%08x\n", (ingenic_dmic->vaddr_base+DMICDR),dmic_read_reg(dev, DMICDR));
++	pr_info("DMICFTHR  %p : 0x%08x\n", (ingenic_dmic->vaddr_base+DMICFTHR),dmic_read_reg(dev, DMICFTHR));
++	pr_info("DMICFSR  %p : 0x%08x\n", (ingenic_dmic->vaddr_base+DMICFSR),dmic_read_reg(dev, DMICFSR));
++	pr_info("DMICCGDIS  %p : 0x%08x\n", (ingenic_dmic->vaddr_base+DMICCGDIS),dmic_read_reg(dev, DMICCGDIS));
++	return;
++}
++
++static int ingenic_dmic_contoller_init(struct snd_soc_dai *dai)
++{
++	struct device *dev = dai->dev;
++	DMIC_DEBUG_MSG("enter %s\n", __func__);
++
++	dmic_write_reg(dev, DMICCR0, 0xC8);
++	dmic_write_reg(dev, DMICTRICR, 0x00030000);
++	/*gain: 0, ..., e*/
++	__dmic_reset(dev);
++	while(__dmic_get_reset(dev));
++	__dmic_set_sr_8k(dev);
++	__dmic_enable_hpf1(dev);
++	__dmic_set_gcr(dev,8);
++	__dmic_mask_all_int(dev);
++	__dmic_enable_pack(dev);
++	__dmic_disable_sw_lr(dev);
++	__dmic_enable_lp(dev);
++	__dmic_set_request(dev,48);
++	__dmic_set_thr_high(dev,32);
++	__dmic_set_thr_low(dev,16);
++
++	return 0;
++}
++
++static int ingenic_dmic_startup(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct ingenic_dmic *ingenic_dmic = dev_get_drvdata(dai->dev);
++
++	DMIC_DEBUG_MSG("enter %s, substream capture\n",__func__);
++
++	if (!ingenic_dmic->dmic_mode) {
++		__dmic_enable(ingenic_dmic->dev);
++	}
++	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
++		ingenic_dmic->dmic_mode |= DMIC_READ;
++	} else {
++		dev_err(dai->dev, "dmic is a capture device\n");
++		return -EINVAL;
++	}
++
++	clk_prepare_enable(ingenic_dmic->clk_gate_dmic);
++	if (!IS_ERR(ingenic_dmic->vcc_dmic))
++		regulator_enable(ingenic_dmic->vcc_dmic);
++
++	ingenic_dmic->en = 1;
++	printk("start set dmic register....\n");
++	return 0;
++}
++
++static int dmic_set_rate(struct device *dev, int rate){
++	DMIC_DEBUG_MSG("enter %s, rate = %d\n",__func__, rate);
++	switch(rate){
++		case 8000:
++			__dmic_set_sr_8k(dev);
++			break;
++		case 16000:
++			__dmic_set_sr_16k(dev);
++			break;
++		case 48000:
++			__dmic_set_sr_48k(dev);
++			break;
++		default:
++			dev_err(dev,"dmic unsupport rate %d\n",rate);
++	}
++	return 0;
++}
++
++static int ingenic_dmic_hw_params(struct snd_pcm_substream *substream,
++				struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
++{
++	struct device *dev = dai->dev;
++	int channels = params_channels(params);
++	int rate = params_rate(params);
++	struct ingenic_dmic *ingenic_dmic = dev_get_drvdata(dai->dev);
++	int fmt_width = snd_pcm_format_width(params_format(params));
++	enum dma_slave_buswidth buswidth;
++	int trigger;
++
++	DMIC_DEBUG_MSG("enter %s, substream = %s\n",__func__,"capture");
++
++	if (!((1 << params_format(params)) & INGENIC_DMIC_FORMATS)
++			||channels < 1||channels > 4|| rate > 48000||rate < 8000
++			||fmt_width != 16) {
++		dev_err(dai->dev, "hw params not inval channel %d params %x rate %d fmt_width %d\n",
++				channels, params_format(params),rate,fmt_width);
++		return -EINVAL;
++	}
++
++	if (ingenic_dmic->unpack_enable)
++		buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
++	else
++		buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
++
++	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
++		ingenic_dmic->capture_dma_data.addr_width = buswidth;
++		ingenic_dmic->capture_dma_data.maxburst = (DMIC_FIFO_DEPTH * buswidth)/2;
++		trigger = ingenic_dmic->capture_dma_data.maxburst/(int)buswidth;
++		__dmic_set_request(dev, trigger);
++		__dmic_set_chnum(dev, channels - 1);
++		dmic_set_rate(dev,rate);
++//		snd_soc_dai_set_dma_data(dai, substream, (void *)&ingenic_dmic->capture_dma_data);
++	} else {
++		dev_err(dai->dev, "DMIC is a capture device\n");
++	}
++	return 0;
++}
++
++static void ingenic_dmic_start_substream(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct ingenic_dmic *ingenic_dmic = dev_get_drvdata(dai->dev);
++	DMIC_DEBUG_MSG("enter %s, substream start capture\n", __func__);
++
++	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
++//		clk_enable(ingenic_dmic->dmic_enable);
++		clk_prepare_enable(ingenic_dmic->clk_gate_dmic);
++		__dmic_enable(ingenic_dmic->dev);
++		__dmic_enable_rdms(ingenic_dmic->dev);
++	} else {
++		dev_err(dai->dev, "DMIC is a capture device\n");
++	}
++	return;
++}
++
++static void ingenic_dmic_stop_substream(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct ingenic_dmic *ingenic_dmic = dev_get_drvdata(dai->dev);
++	struct device *dev = dai->dev;
++	DMIC_DEBUG_MSG("enter %s, substream stop capture\n",__func__);
++
++	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
++		if (__dmic_is_enable_rdms(dev)) {
++			__dmic_disable_rdms(dev);
++		}
++//		clk_disable(ingenic_dmic->dmic_enable);
++		clk_disable_unprepare(ingenic_dmic->clk_gate_dmic);
++		__dmic_disable(ingenic_dmic->dev);
++	}else{
++		dev_err(dai->dev, "DMIC is a capture device\n");
++	}
++	return;
++}
++
++static int ingenic_dmic_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
++{
++	struct ingenic_pcm_runtime_data *prtd = substream->runtime->private_data;
++	DMIC_DEBUG_MSG("enter %s, substream capture cmd = %d\n", __func__,cmd);
++	int ret = 0;
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		if (atomic_read(&prtd->wait_stopdma))
++			return -EPIPE;
++		printk(KERN_DEBUG"dmic start\n");
++		ingenic_dmic_start_substream(substream, dai);
++		break;
++	case SNDRV_PCM_TRIGGER_STOP:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++		ret = dmaengine_terminate_all(prtd->dma_chan);
++		if(ret == -EBUSY){
++			atomic_set(&prtd->wait_stopdma,1);
++			return 0;
++		}
++		printk(KERN_DEBUG"dmic stop\n");
++		ingenic_dmic_stop_substream(substream, dai);
++		break;
++	}
++	return 0;
++}
++
++static void ingenic_dmic_shutdown(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai) {
++	struct ingenic_dmic *ingenic_dmic = dev_get_drvdata(dai->dev);
++	struct device *dev = dai->dev;
++
++	DMIC_DEBUG_MSG("enter %s, substream = capture\n", __func__);
++
++	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++		ingenic_dmic->dmic_mode &= ~DMIC_READ;
++
++	if (!ingenic_dmic->dmic_mode) {
++		__dmic_disable(dev);
++	}
++	if (!IS_ERR(ingenic_dmic->vcc_dmic))
++		regulator_disable(ingenic_dmic->vcc_dmic);
++	clk_disable_unprepare(ingenic_dmic->clk_gate_dmic);
++	ingenic_dmic->en = 0;
++	return;
++}
++
++static int ingenic_dmic_probe(struct snd_soc_dai *dai)
++{
++	struct ingenic_dmic *ingenic_dmic = dev_get_drvdata(dai->dev);
++	snd_soc_dai_init_dma_data(dai, NULL,
++			&ingenic_dmic->capture_dma_data);
++
++	clk_prepare_enable(ingenic_dmic->clk_gate_dmic);
++	ingenic_dmic_contoller_init(dai);
++	clk_disable_unprepare(ingenic_dmic->clk_gate_dmic);
++	return 0;
++}
++
++
++static struct snd_soc_dai_ops ingenic_dmic_dai_ops = {
++	.startup	= ingenic_dmic_startup,
++	.trigger 	= ingenic_dmic_trigger,
++	.hw_params 	= ingenic_dmic_hw_params,
++	.shutdown	= ingenic_dmic_shutdown,
++};
++
++#define ingenic_dmic_suspend	NULL
++#define ingenic_dmic_resume	NULL
++
++static ssize_t ingenic_dmic_regs_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct ingenic_dmic *ingenic_dmic = dev_get_drvdata(dev);
++	dump_registers(ingenic_dmic->dev);
++	return 0;
++}
++
++static ssize_t ingenic_dmic_regs_store(struct device *dev,
++		struct device_attribute *attr, const char *buf,
++		size_t count)
++{
++	struct ingenic_dmic *ingenic_dmic = dev_get_drvdata(dev);
++	const char *start = buf;
++	unsigned int reg, val;
++	int ret_count = 0;
++
++	while(!isxdigit(*start)) {
++		start++;
++		if (++ret_count >= count)
++			return count;
++	}
++	reg = simple_strtoul(start, (char **)&start, 16);
++
++	while(!isxdigit(*start)) {
++		start++;
++		if (++ret_count >= count)
++			return count;
++	}
++	val = simple_strtoul(start, (char **)&start, 16);
++
++	clk_prepare_enable(ingenic_dmic->clk_gate_dmic);
++
++	if (!IS_ERR(ingenic_dmic->vcc_dmic))
++		regulator_enable(ingenic_dmic->vcc_dmic);
++	dmic_write_reg(ingenic_dmic->dev, reg, val);
++
++	if (!IS_ERR(ingenic_dmic->vcc_dmic))
++		regulator_disable(ingenic_dmic->vcc_dmic);
++	clk_disable_unprepare(ingenic_dmic->clk_gate_dmic);
++
++	return count;
++
++
++}
++
++static DEVICE_ATTR(dmic_regs, S_IRUGO | S_IWUSR, ingenic_dmic_regs_show, ingenic_dmic_regs_store);
++static const struct attribute *dump_attrs[] = {
++	&dev_attr_dmic_regs.attr,
++	NULL,
++};
++static const struct attribute_group dump_attr_group = {
++	.attrs = (struct attribute **)dump_attrs,
++};
++
++static struct snd_soc_dai_driver ingenic_dmic_dai = {
++		.probe   = ingenic_dmic_probe,
++		.capture = {
++			.channels_min = 1,
++			.channels_max = 4,
++			.rates = INGENIC_DMIC_RATE,
++			.formats = INGENIC_DMIC_FORMATS,
++		},
++		.ops = &ingenic_dmic_dai_ops,
++};
++
++static const struct snd_soc_component_driver ingenic_dmic_component = {
++	.name		= "ingenic-dmic",
++};
++
++static int dmic_gain_get(struct snd_kcontrol *kcontrol,
++			    struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
++	struct ingenic_dmic *ingenic_dmic = snd_soc_component_get_drvdata(codec);
++	unsigned int value;
++	clk_prepare_enable(ingenic_dmic->clk_gate_dmic);
++	value = dmic_read_reg(ingenic_dmic->dev, DMICGCR);
++	clk_disable_unprepare(ingenic_dmic->clk_gate_dmic);
++	ucontrol->value.integer.value[0] = value;
++
++	return 0;
++}
++static int dmic_gain_put(struct snd_kcontrol *kcontrol,
++			    struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
++	struct ingenic_dmic *ingenic_dmic = snd_soc_component_get_drvdata(codec);
++	unsigned int value = ucontrol->value.integer.value[0];
++
++	clk_prepare_enable(ingenic_dmic->clk_gate_dmic);
++	dmic_write_reg(ingenic_dmic->dev, DMICGCR, value);
++	clk_disable_unprepare(ingenic_dmic->clk_gate_dmic);
++
++	return 0;
++}
++
++/*
++ * DMIC GAIN volume control:
++ * from 0dB to 93dB in 3 dB steps
++ * */
++static const DECLARE_TLV_DB_SCALE(dmic_gain_tlv, 0, 300, 0);
++static const struct snd_kcontrol_new  dmic_codec_controls[] = {
++	SOC_SINGLE_EXT_TLV("DMIC GAIN", 0, 0, 0x1f, 0 , dmic_gain_get, dmic_gain_put, dmic_gain_tlv),
++};
++
++
++static struct snd_soc_dai_driver  dmic_codec_dai = {
++	.name = "dmic-codec-hifi",
++	.capture = {
++		.channels_min = 1,
++		.channels_max = 4,
++		.rates = SNDRV_PCM_RATE_48000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_8000,
++		.formats = SNDRV_PCM_FMTBIT_S16_LE,
++	},
++};
++
++static struct snd_soc_component_driver soc_codec_dev_dmic_component = {
++	.controls = 	dmic_codec_controls,
++	.num_controls = ARRAY_SIZE(dmic_codec_controls),
++};
++
++extern int ingenic_dma_pcm_register(struct device *dev,  const struct snd_dmaengine_pcm_config *config, struct ingenic_dma_pcm *ingenic_pcm);
++extern void ingenic_dma_pcm_unregister(struct ingenic_dma_pcm *ingenic_pcm);
++static int ingenic_dmic_platfrom_probe(struct platform_device *pdev)
++{
++	struct ingenic_dmic *ingenic_dmic;
++	struct resource *res = NULL;
++	int ret;
++
++	ingenic_dmic = devm_kzalloc(&pdev->dev, sizeof(struct ingenic_dmic), GFP_KERNEL);
++	if (!ingenic_dmic)
++		return -ENOMEM;
++
++	ingenic_dmic->dev = &pdev->dev;
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res)
++		return -ENOENT;
++	if (!devm_request_mem_region(&pdev->dev,
++				res->start, resource_size(res),pdev->name))
++		return -EBUSY;
++
++	ingenic_dmic->res_start = res->start;
++	ingenic_dmic->res_size = resource_size(res);
++	ingenic_dmic->vaddr_base = devm_ioremap(&pdev->dev,
++			ingenic_dmic->res_start, ingenic_dmic->res_size);
++	if (!ingenic_dmic->vaddr_base) {
++		dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
++		return -ENOMEM;
++	}
++
++	ingenic_dmic->dmic_mode = 0;
++	ingenic_dmic->capture_dma_data.addr = (dma_addr_t)ingenic_dmic->res_start + DMICDR;
++
++	ingenic_dmic->vcc_dmic = regulator_get(&pdev->dev,"vcc_dmic");
++
++	platform_set_drvdata(pdev, (void *)ingenic_dmic);
++
++	ret = sysfs_create_group(&pdev->dev.kobj, &dump_attr_group);
++	if (ret)
++		dev_info(&pdev->dev, "dmic attr create failed\n");
++
++	ingenic_dmic->clk_gate_dmic = clk_get(&pdev->dev, "gate_dmic");
++	if (IS_ERR_OR_NULL(ingenic_dmic->clk_gate_dmic)) {
++		ret = PTR_ERR(ingenic_dmic->clk_gate_dmic);
++		ingenic_dmic->clk_gate_dmic = NULL;
++		dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
++		return ret;
++	}
++//	clk_prepare_enable(ingenic_dmic->clk_gate_dmic);
++//	__dmic_enable(&pdev->dev);
++//	printk("XXXXXXXXXXXXXXXXXXXXcgu-i2s%x\n",*(volatile unsigned int*)0xb0000060);
++//	printk("XXXXXXXXXXXXXXXXXXXXgate-dmic%x\n",*(volatile unsigned int*)0xb0000020);
++//	ingenic_dmic->dmic_enable = clk_get(&pdev->dev, "dmic_enable");
++//	if (IS_ERR_OR_NULL(ingenic_dmic->dmic_enable)) {
++//		ret = PTR_ERR(ingenic_dmic->dmic_enable);
++//		ingenic_dmic->dmic_enable = NULL;
++//		dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
++//		return ret;
++//	}
++
++	ret = snd_soc_register_component(&pdev->dev,
++					&soc_codec_dev_dmic_component, &dmic_codec_dai, 1);
++	ret = snd_soc_register_component(&pdev->dev, &ingenic_dmic_component,
++					 &ingenic_dmic_dai, 1);
++	if (ret)
++		goto err_register_cpu_dai;
++	dev_dbg(&pdev->dev, "dmic platform probe success\n");
++
++	ret = ingenic_dma_pcm_register(&pdev->dev, NULL, ingenic_dmic->ingenic_pcm);
++
++	return ret;
++
++err_register_cpu_dai:
++	platform_set_drvdata(pdev, NULL);
++	return ret;
++}
++
++static int ingenic_dmic_platfom_remove(struct platform_device *pdev)
++{
++	struct ingenic_dmic *ingenic_dmic = platform_get_drvdata(pdev);
++	sysfs_remove_group(&pdev->dev.kobj, &dump_attr_group);
++	snd_soc_unregister_component(&pdev->dev);
++	platform_set_drvdata(pdev, NULL);
++	ingenic_dma_pcm_unregister(ingenic_dmic->ingenic_pcm);
++	return 0;
++}
++
++
++#ifdef CONFIG_PM
++static int ingenic_dmic_platfom_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	struct ingenic_dmic *ingenic_dmic = platform_get_drvdata(pdev);
++	if(ingenic_dmic->en){
++		if (!IS_ERR(ingenic_dmic->vcc_dmic))
++			regulator_disable(ingenic_dmic->vcc_dmic);
++
++		clk_disable_unprepare(ingenic_dmic->clk_gate_dmic);
++	}
++	return 0;
++}
++
++static int ingenic_dmic_platfom_resume(struct platform_device *pdev)
++{
++	struct ingenic_dmic *ingenic_dmic = platform_get_drvdata(pdev);
++	if(ingenic_dmic->en){
++		if (!IS_ERR(ingenic_dmic->vcc_dmic))
++			regulator_enable(ingenic_dmic->vcc_dmic);
++
++		clk_prepare_enable(ingenic_dmic->clk_gate_dmic);
++	}
++	return 0;
++}
++#endif
++
++static const struct of_device_id dmic_dt_match[] = {
++	{ .compatible = "ingenic,dmic", .data = NULL },
++	{},
++};
++MODULE_DEVICE_TABLE(of, dmic_dt_match);
++static struct platform_driver ingenic_dmic_plat_driver = {
++	.probe  = ingenic_dmic_platfrom_probe,
++	.remove = ingenic_dmic_platfom_remove,
++#ifdef CONFIG_PM
++	.suspend = ingenic_dmic_platfom_suspend,
++	.resume = ingenic_dmic_platfom_resume,
++#endif
++	.driver = {
++		.name = "ingenic-asoc-dmic",
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(dmic_dt_match),
++	},
++};
++
++module_platform_driver(ingenic_dmic_plat_driver);
++MODULE_AUTHOR("siyu.zhang@ingenic.com");
++MODULE_DESCRIPTION("INGENIC AIC dmic SoC Interface");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-dmic");
+diff --git a/module_drivers/sound/soc/ingenic/as-v1/asoc-dmic.h b/module_drivers/sound/soc/ingenic/as-v1/asoc-dmic.h
+new file mode 100644
+index 000000000..9472d63ca
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v1/asoc-dmic.h
+@@ -0,0 +1,301 @@
++#ifndef __ASOC_DMIC_H__
++#define __ASOC_DMIC_H__
++
++#include <linux/circ_buf.h>
++#include <sound/dmaengine_pcm.h>
++#include "asoc-dma.h"
++
++
++struct dma2ddr_info {
++	void *addr;
++	unsigned int cur_pos;
++	unsigned int len;
++};
++
++
++struct dma_fifo {
++	struct circ_buf xfer;
++	size_t n_size;
++	dma_addr_t paddr;
++};
++
++struct ingenic_dmic {
++	struct device	*dev;
++	resource_size_t res_start;
++	resource_size_t res_size;
++	void __iomem	*vaddr_base;
++#define DMIC_READ	0x1
++	int unpack_enable;
++	int dmic_mode;
++	int en;
++	struct regulator * vcc_dmic;
++	struct clk	*clk_gate_dmic;
++	struct clk	*dmic_enable;
++//	struct clk	*aic_clk;
++	/*for dma*/
++/*	struct ingenic_pcm_dma_params rx_dma_data;*/
++	struct snd_dmaengine_dai_dma_data capture_dma_data;
++
++	struct dma_fifo *record_fifo;
++
++	/* fifo transfer data from dma to tcsm */
++	struct dma_fifo *tcsm_fifo;
++
++	/* timer to trans data from tcsm to ddr */
++	struct timer_list record_timer;
++	struct ingenic_dma_pcm *ingenic_pcm;
++
++};
++
++static void inline dmic_write_reg(struct device *dev, unsigned int reg,
++		unsigned int val)
++{
++	struct ingenic_dmic *ingenic_dmic = dev_get_drvdata(dev);
++	writel(val, ingenic_dmic->vaddr_base + reg);
++}
++
++static unsigned int inline dmic_read_reg(struct device *dev, unsigned int reg)
++{
++	struct ingenic_dmic *ingenic_dmic = dev_get_drvdata(dev);
++	return readl(ingenic_dmic->vaddr_base + reg);
++}
++#define dmic_set_reg(dev, addr, val, mask, offset)\
++	do {	\
++		int tmp_val = val;							\
++		int read_val = dmic_read_reg(dev, addr);         \
++		read_val &= (~mask);                    \
++		tmp_val = ((tmp_val << offset) & mask); \
++		tmp_val |= read_val;                    \
++		dmic_write_reg(dev, addr, tmp_val);           \
++	}while(0)
++
++#define dmic_get_reg(dev, addr, mask, offset)  \
++	((dmic_read_reg(dev, addr) & mask) >> offset)
++
++
++#define DMICCR0		0x0
++#define DMICGCR		0x4
++#define DMICIMR		0x8
++#define DMICINTCR	0xc
++#define DMICTRICR	0x10
++#define DMICTHRH	0x14
++#define DMICTHRL	0x18
++#define DMICTRIMMAX	0x1c
++#define DMICTRINMAX 0x20
++#define DMICDR		0x30
++#define DMICFTHR	0x34
++#define DMICFSR		0x38
++#define DMICCGDIS	0x50
++
++
++/*    DMICCR0  */
++#define DMIC_RESET		31
++#define DMIC_RESET_MASK		(0x1 << DMIC_RESET)
++#define DMIC_RESET_TRI	30
++#define DMIC_RESET_TRI_MASK	(0x1 << DMIC_RESET_TRI)
++#define DMIC_CHNUM		16
++#define DMIC_CHNUM_MASK			(0x7 << DMIC_CHNUM)
++#define DMIC_UNPACK_MSB 13
++#define	DMIC_UNPACK_MSB_MASK	(0x1 << DMIC_UNPACK_MSB)
++#define DMIC_UNPACK_DIS	12
++#define DMIC_UNPACK_DIS_MASK	(0x1 << DMIC_UNPACK_DIS)
++#define DMIC_SW_LR		11
++#define DMIC_SW_LR_MASK		(0x1 << DMIC_SW_LR)
++#define DMIC_SPLIT_DI	10
++#define DMIC_SPLIT_DI_MASK	(0x1 << DMIC_SPLIT_DI)
++#define DMIC_PACK_EN	8
++#define DMIC_PACK_EN_MASK	(0x1 << DMIC_PACK_EN)
++#define DMIC_SR			6
++#define DMIC_SR_MASK		(0x3 << DMIC_SR)
++#define DMIC_LP_MODE	3
++#define DMIC_LP_MODE_MASK	(0x1 << DMIC_LP_MODE)
++#define DMIC_HPF1_MODE	2
++#define DMIC_HPF1_MODE_MASK	(0x1 << DMIC_HPF1_MODE)
++#define DMIC_TRI_EN		1
++#define DMIC_TRI_EN_MASK	(0x1 << DMIC_TRI_EN)
++#define DMIC_EN			0
++#define DMIC_EN_MASK		(0x1 << DMIC_EN)
++
++#define __dmic_reset(dev)\
++		dmic_set_reg(dev,DMICCR0,1,DMIC_RESET_MASK,DMIC_RESET)
++
++#define __dmic_get_reset(dev)\
++		dmic_get_reg(dev,DMICCR0,DMIC_RESET_MASK,DMIC_RESET)
++
++#define __dmic_reset_tri(dev)\
++		dmic_set_reg(dev,DMICCR0,1,DMIC_RESET_TRI_MASK,DMIC_RESET_TRI)
++
++#define __dmic_set_chnum(dev,n)\
++		dmic_set_reg(dev,DMICCR0,n,DMIC_CHNUM_MASK,DMIC_CHNUM)
++
++#define __dmic_get_chnum(dev,n)\
++		dmic_set_reg(dev,DMICCR0,DMIC_CHNUM_MASK,DMIC_CHNUM)
++
++#define __dmic_unpack_msb(dev)\
++		dmic_set_reg(dev,DMICCR0,1,DMIC_UNPACK_MSB_MASK,DMIC_UNPACK_MSB)
++
++#define __dmic_unpack_dis(dev)\
++		dmic_set_reg(dev,DMICCR0,1,DMIC_UNPACK_DIS_MASK,DMIC_UNPACK_DIS)
++
++#define __dmic_enable_sw_lr(dev)\
++		dmic_set_reg(dev,DMICCR0,1,DMIC_SW_LR_MASK,DMIC_SW_LR)
++
++#define __dmic_disable_sw_lr(dev)\
++		dmic_set_reg(dev,DMICCR0,0,DMIC_SW_LR_MASK,DMIC_SW_LR)
++
++#define __dmic_split(dev)\
++		dmic_set_reg(dev,DMICCR0,1,DMIC_SPLIT_DI_MASK,DMIC_SPLIT_DI)
++
++#define __dmic_enable_pack(dev)\
++		dmic_set_reg(dev,DMICCR0,1,DMIC_PACK_EN_MASK,DMIC_PACK_EN)
++
++#define __dmic_set_sr(dev,n)\
++		dmic_set_reg(dev,DMICCR0,n,DMIC_SR_MASK,DMIC_SR)
++
++#define __dmic_set_sr_8k(dev)\
++		__dmic_set_sr(dev,0)
++
++#define __dmic_set_sr_16k(dev)\
++		__dmic_set_sr(dev,1)
++
++#define __dmic_set_sr_48k(dev)\
++		__dmic_set_sr(dev,2)
++
++#define __dmic_enable_lp(dev)\
++		dmic_set_reg(dev,DMICCR0,1,DMIC_LP_MODE_MASK,DMIC_LP_MODE)
++
++#define __dmic_disable_lp(dev)\
++		dmic_set_reg(dev,DMICCR0,0,DMIC_LP_MODE_MASK,DMIC_LP_MODE)
++
++#define __dmic_enable_hpf1(dev)\
++		dmic_set_reg(dev,DMICCR0,1,DMIC_HPF1_MODE_MASK,DMIC_HPF1_MODE)
++
++#define __dmic_disable_hpf1(dev)\
++		dmic_set_reg(dev,DMICCR0,0,DMIC_HPF1_MODE_MASK,DMIC_HPF1_MODE)
++
++#define __dmic_is_enable_tri(dev)\
++		dmic_get_reg(dev,DMICCR0,DMIC_TRI_EN_MASK,DMIC_TRI_EN)
++
++#define __dmic_enable_tri(dev)\
++		dmic_set_reg(dev,DMICCR0,1,DMIC_TRI_EN_MASK,DMIC_TRI_EN)
++
++#define __dmic_disable_tri(dev)\
++		dmic_set_reg(dev,DMICCR0,0,DMIC_TRI_EN_MASK,DMIC_TRI_EN)
++
++#define __dmic_is_enable(dev)\
++		dmic_get_reg(dev,DMICCR0,DMIC_EN_MASK,DMIC_EN)
++
++#define __dmic_enable(dev)\
++		dmic_set_reg(dev,DMICCR0,1,DMIC_EN_MASK,DMIC_EN)
++
++#define __dmic_disable(dev)\
++		dmic_set_reg(dev,DMICCR0,0,DMIC_EN_MASK,DMIC_EN)
++
++/*DMICGCR*/
++#define DMIC_GCR	0
++#define DMIC_GCR_MASK	(0Xf << DMIC_GCR)
++
++#define __dmic_set_gcr(dev,n)\
++		dmic_set_reg(dev, DMICGCR, n, DMIC_GCR_MASK,DMIC_GCR)
++
++/* DMICIMR */
++#define DMIC_FIFO_TRIG_MASK	5
++#define DMIC_FIFO_TRIG_MSK		(1 << DMIC_FIFO_TRIG_MASK)
++#define DMIC_WAKE_MASK	4
++#define DMIC_WAKE_MSK		(1 << DMIC_WAKE_MASK)
++#define DMIC_EMPTY_MASK 3
++#define DMIC_EMPTY_MSK		(1 << DMIC_EMPTY_MASK)
++#define DMIC_FULL_MASK	2
++#define DMIC_FULL_MSK		(1 << DMIC_FULL_MASK)
++#define DMIC_PRERD_MASK	1
++#define DMIC_PRERD_MSK		(1 << DMIC_PRERD_MASK)
++#define DMIC_TRI_MASK	0
++#define DMIC_TRI_MSK		(1 << DMIC_TRI_MASK)
++
++#define __dmic_mask_all_int(dev)\
++	dmic_set_reg(dev,DMICIMR, 0x3f, 0x3f, 0)
++
++
++/*DMICINTCR*/
++#define DMIC_FIFO_TRIG_FLAG	4
++#define DMIC_FIFO_TRIG_FLAG_MASK		(1 << DMIC_WAKE_FLAG)
++#define DMIC_WAKE_FLAG	4
++#define DMIC_WAKE_FLAG_MASK		(1 << DMIC_WAKE_FLAG)
++#define DMIC_EMPTY_FLAG 3
++#define DMIC_EMPTY_FLAG_MASK	(1 << DMIC_EMPTY_FLAG)
++#define DMIC_FULL_FLAG	2
++#define DMIC_FULL_FLAG_MASK		(1 << DMIC_FULL_FLAG)
++#define DMIC_PRERD_FLAG	1
++#define DMIC_PRERD_FLAG_MASK	(1 << DMIC_PRERD_FLAG)
++#define DMIC_TRI_FLAG	0
++#define DMIC_TRI_FLAG_MASK		(1 << DMIC_TRI_FLAG)
++
++/*DMICTRICR*/
++#define DMIC_TRI_MODE	16
++#define DMIC_TRI_MODE_MASK	(0xf << DMIC_TRI_MODE)
++#define DMIC_TRI_DEBUG	4
++#define DMIC_TRI_DEBUG_MASK	(0x1 << DMIC_TRI_DEBUG)
++#define DMIC_HPF2_EN	3
++#define DMIC_HPF2_EN_MASK (0x1 << DMIC_HPF2_EN)
++#define DMIC_PREFETCH	1
++#define DMIC_PREFETCH_MASK	(0x3 << DMIC_PREFETCH)
++#define DMIC_TRI_CLR	0
++#define DMIC_TRI_CLR_MASK	(0x1 << DMIC_TRI_CLR)
++
++#define __dmic_enable_hpf2(dev)	\
++	dmic_set_reg(dev, DMICTRICR, 1, DMIC_HPF2_EN_MASK, DMIC_HPF2_EN)
++
++#define __dmic_disable_hpf2(dev)	\
++	dmic_set_reg(dev, DMICTRICR, 0, DMIC_HPF2_EN_MASK, DMIC_HPF2_EN)
++
++/*DMICTHRH*/
++#define DMIC_THR_H 0
++#define DMIC_THR_H_MASK (0xfffff << DMIC_THR_H)
++
++#define __dmic_set_thr_high(dev,n)	\
++	dmic_set_reg(dev, DMICTHRH, n, DMIC_THR_H_MASK, DMIC_THR_H)
++
++/*DMICTHRL*/
++#define DMIC_THR_L 0
++#define DMIC_THR_L_MASK (0xfffff << DMIC_THR_L)
++
++#define __dmic_set_thr_low(dev,n)	\
++	dmic_set_reg(dev, DMICTHRL, n, DMIC_THR_L_MASK, DMIC_THR_L)
++
++
++/* DMICTRIMMAX */
++#define DMIC_M_MAX	0
++#define DMIC_M_MAX_MASK	(0xffffff << DMIC_M_MAX)
++
++/* DMICTRINMAX */
++#define DMIC_N_MAX	0
++#define DMIC_N_MAX_MASK	(0xffff << DMIC_N_MAX)
++
++/* DMICFTHR */
++#define DMIC_RDMS	31
++#define DMIC_RDMS_MASK	(0x1 << DMIC_RDMS)
++#define DMIC_FIFO_THR	0
++#define DMIC_FIFO_THR_MASK	(0x3f << DMIC_FIFO_THR)
++
++#define __dmic_is_enable_rdms(dev)\
++	dmic_get_reg(dev, DMICFTHR,DMIC_RDMS_MASK,DMIC_RDMS)
++#define __dmic_enable_rdms(dev)\
++	dmic_set_reg(dev, DMICFTHR,1,DMIC_RDMS_MASK,DMIC_RDMS)
++#define __dmic_disable_rdms(dev)\
++	dmic_set_reg(dev, DMICFTHR,1,DMIC_RDMS_MASK,DMIC_RDMS)
++#define __dmic_set_request(dev,n)	\
++	dmic_set_reg(dev, DMICFTHR, n, DMIC_FIFO_THR_MASK, DMIC_FIFO_THR)
++
++/*DMICFSR*/
++#define DMIC_FULLS	19
++#define DMIC_FULLS_MASK	(0x1 << DMIC_FULLS)
++#define DMIC_TRIGS	18
++#define DMIC_TRIGS_MASK	(0x1 << DMIC_TRIGS)
++#define DMIC_PRERDS	17
++#define DMIC_PRERDS_MASK	(0x1 << DMIC_PRERDS)
++#define DMIC_EMPTYS	16
++#define DMIC_EMPTYS_MASK	(0x1 << DMIC_EMPTYS)
++#define DMIC_FIFO_LVL 0
++#define DMIC_FIFO_LVL_MASK	(0x3f << DMIC_FIFO_LVL)
++
++#endif /* __ASOC_DMIC_H__ */
+diff --git a/module_drivers/sound/soc/ingenic/as-v1/asoc-i2s-tloop.c b/module_drivers/sound/soc/ingenic/as-v1/asoc-i2s-tloop.c
+new file mode 100644
+index 000000000..b93bd406d
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v1/asoc-i2s-tloop.c
+@@ -0,0 +1,331 @@
++/*
++ *  sound/soc/ingenic/asoc-i2s-tloop.c
++ *  ALSA Soc Audio Layer -- ingenic i2s tloop (part of aic controller) driver
++ *
++ *  Copyright 2014 Ingenic Semiconductor Co.,Ltd
++ *	cli <chen.li@ingenic.com>
++ *
++ *  This program is free software; you can redistribute  it and/or modify it
++ *  under  the terms of  the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the  License, or (at your
++ *  option) any later version.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/initval.h>
++#include <sound/soc.h>
++#include <sound/soc-dai.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <sound/dmaengine_pcm.h>
++#include "asoc-aic.h"
++#include "asoc-dma.h"
++
++static int ingenic_i2s_tloop_debug = 0;
++module_param(ingenic_i2s_tloop_debug, int, 0644);
++#define I2S_DEBUG_MSG(msg...)					\
++	do {										\
++		if (ingenic_i2s_tloop_debug)					\
++			pr_debug("I2S: " msg);				\
++	} while(0)
++
++struct ingenic_i2s {
++	struct device *aic;	/*register access device*/
++#define I2S_WRITE 0x1
++#define I2S_READ  0x2
++	int i2s_mode;
++	struct snd_dmaengine_dai_dma_data playback_dma_data;
++	struct snd_dmaengine_dai_dma_data capture_dma_data;
++	struct snd_soc_dai_driver dai_driver;
++	dma_addr_t dma_base;
++	struct clk *cgu_clk;
++	int playback_channels;
++	struct ingenic_dma_pcm *ingenic_pcm;
++};
++
++#define I2S_RFIFO_DEPTH 32
++#define I2S_TFIFO_DEPTH 64
++#define TX_FIFO_LEVEL 16
++
++static void dump_registers(struct device *aic)
++{
++	struct ingenic_aic *ingenic_aic = dev_get_drvdata(aic);
++
++	pr_info("AIC_FR\t\t%p : 0x%08x\n", (ingenic_aic->vaddr_base+AICFR),ingenic_aic_read_reg(aic, AICFR));
++	pr_info("AIC_CR\t\t%p : 0x%08x\n", (ingenic_aic->vaddr_base+AICCR),ingenic_aic_read_reg(aic, AICCR));
++	pr_info("AIC_I2SCR\t%p : 0x%08x\n",(ingenic_aic->vaddr_base+I2SCR),ingenic_aic_read_reg(aic, I2SCR));
++	pr_info("AIC_SR\t\t%p : 0x%08x\n", (ingenic_aic->vaddr_base+AICSR),ingenic_aic_read_reg(aic, AICSR));
++	pr_info("AIC_I2SSR\t%p : 0x%08x\n",(ingenic_aic->vaddr_base+I2SSR),ingenic_aic_read_reg(aic, I2SSR));
++	pr_info("AIC_I2SDIV\t%p : 0x%08x\n",(ingenic_aic->vaddr_base+I2SDIV),ingenic_aic_read_reg(aic, I2SDIV));
++	pr_info("AIC_DR\t\t%p\n", (ingenic_aic->vaddr_base+AICDR));
++	return;
++}
++
++static int ingenic_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
++{
++
++	return 0;
++}
++
++static int ingenic_set_sysclk(struct snd_soc_dai *dai, int clk_id,
++		unsigned int freq, int dir)
++{
++	return 0;
++}
++
++static int ingenic_i2s_startup(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct ingenic_i2s *ingenic_i2s = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_i2s->aic;
++
++	if (!ingenic_i2s->i2s_mode) {
++
++		__i2s_set_tfifo_loop_trigger(aic, (I2S_RFIFO_DEPTH/4 - 1));
++	}
++
++	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
++		__i2s_disable_tloop(aic);
++		__i2s_disable_etfl(aic);
++	}
++
++	return 0;
++}
++
++
++static int ingenic_i2s_hw_params(struct snd_pcm_substream *substream,
++				struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
++{
++	int phys_width = snd_pcm_format_physical_width(params_format(params));
++	struct ingenic_i2s *ingenic_i2s = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_i2s->aic;
++	enum dma_slave_buswidth buswidth;
++	int trigger;
++
++
++	/* format */
++	if (phys_width == 8)
++		buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
++	else if (phys_width == 16)
++		buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
++	else if (phys_width == 24)
++		buswidth = DMA_SLAVE_BUSWIDTH_3_BYTES;
++	else if (phys_width == 32)
++		buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
++	else
++		return -EINVAL;
++
++	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
++		ingenic_i2s->capture_dma_data.addr_width = buswidth;
++		ingenic_i2s->capture_dma_data.maxburst = I2S_RFIFO_DEPTH/2;
++
++		trigger = ingenic_i2s->capture_dma_data.maxburst;
++
++		__i2s_set_tfifo_loop_trigger(aic, (trigger/2 - 1));
++	}
++
++	return 0;
++}
++
++static void ingenic_i2s_start_substream(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct ingenic_i2s *ingenic_i2s = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_i2s->aic;
++
++	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
++		__i2s_enable_tloop(aic);
++		__i2s_enable_etfl(aic);
++	}
++
++	return;
++}
++
++static void ingenic_i2s_stop_substream(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct ingenic_i2s *ingenic_i2s = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_i2s->aic;
++
++	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
++		__i2s_disable_tloop(aic);
++		__i2s_disable_etfl(aic);
++	}
++
++	return;
++}
++
++static int ingenic_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
++{
++	struct ingenic_pcm_runtime_data *prtd = substream_to_prtd(substream);
++
++	I2S_DEBUG_MSG("enter %s, substream = %s cmd = %d\n",  __func__,
++				  (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture",
++				  cmd);
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		if (atomic_read(&prtd->wait_stopdma))
++			return -EPIPE;
++		I2S_DEBUG_MSG("i2s start\n");
++		ingenic_i2s_start_substream(substream, dai);
++		break;
++	case SNDRV_PCM_TRIGGER_STOP:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++		if (atomic_read(&prtd->wait_stopdma))
++			return 0;
++		I2S_DEBUG_MSG("i2s stop\n");
++		ingenic_i2s_stop_substream(substream, dai);
++		break;
++	}
++	return 0;
++}
++
++static void ingenic_i2s_shutdown(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++
++	return;
++}
++
++static int ingenic_i2s_probe(struct snd_soc_dai *dai)
++{
++	struct ingenic_i2s *ingenic_i2s = dev_get_drvdata(dai->dev);
++
++	ingenic_i2s->capture_dma_data.addr = ingenic_i2s->dma_base + AICLR;
++	ingenic_i2s->capture_dma_data.fifo_size = I2S_RFIFO_DEPTH;
++
++	snd_soc_dai_init_dma_data(dai, NULL,
++			&ingenic_i2s->capture_dma_data);
++
++	return 0;
++}
++
++static struct snd_soc_dai_ops ingenic_i2s_dai_ops = {
++	.startup	= ingenic_i2s_startup,
++	.trigger 	= ingenic_i2s_trigger,
++	.hw_params 	= ingenic_i2s_hw_params,
++	.shutdown	= ingenic_i2s_shutdown,
++	.set_fmt	= ingenic_set_dai_fmt,
++	.set_sysclk	= ingenic_set_sysclk,
++};
++
++#define ingenic_i2s_suspend	NULL
++#define ingenic_i2s_resume	NULL
++
++static ssize_t ingenic_i2s_regs_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct ingenic_i2s *ingenic_i2s = dev_get_drvdata(dev);
++	dump_registers(ingenic_i2s->aic);
++	return 0;
++}
++
++static DEVICE_ATTR(i2s_regs, S_IRUGO, ingenic_i2s_regs_show, NULL);
++static const struct attribute *dump_attrs[] = {
++	&dev_attr_i2s_regs.attr,
++	NULL,
++};
++
++static const struct attribute_group dump_attr_group = {
++	.attrs = (struct attribute **)dump_attrs,
++};
++
++static const struct snd_soc_component_driver ingenic_i2s_component = {
++	.name		= "aic-i2s-tloop",
++};
++
++#define INGENIC_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | \
++		SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \
++		SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE | \
++		SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE | \
++		SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE | \
++		SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_U24_3LE | \
++		SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_U24_3BE | \
++		SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
++		SNDRV_PCM_FMTBIT_S20_3BE | SNDRV_PCM_FMTBIT_U20_3BE | \
++		SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
++		SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_U18_3BE )
++
++extern int ingenic_dma_pcm_register(struct device *dev,  const struct snd_dmaengine_pcm_config *config, struct ingenic_dma_pcm *ingenic_pcm);
++extern void ingenic_dma_pcm_unregister(struct ingenic_dma_pcm *ingenic_pcm);
++
++static int ingenic_i2s_platfrom_probe(struct platform_device *pdev)
++{
++	struct device_node *parent = of_get_parent(pdev->dev.of_node);
++	struct resource res;
++	struct ingenic_i2s *ingenic_i2s;
++	int ret;
++
++	if (!parent)
++		return -ENOMEM;
++
++	ingenic_i2s = devm_kzalloc(&pdev->dev, sizeof(struct ingenic_i2s), GFP_KERNEL);
++	if (!ingenic_i2s)
++		return -ENOMEM;
++
++	ret = of_address_to_resource(parent, 0, &res);
++	if (ret)
++		return ret;
++
++	ingenic_i2s->dma_base = res.start;
++	ingenic_i2s->aic = pdev->dev.parent;
++	ingenic_i2s->i2s_mode = 0;
++	ingenic_i2s->dai_driver.probe = ingenic_i2s_probe;
++	//ingenic_i2s->dai_driver.suspend = ingenic_i2s_suspend;
++	//ingenic_i2s->dai_driver.resume = ingenic_i2s_resume;
++	ingenic_i2s->dai_driver.ops = &ingenic_i2s_dai_ops;
++	ingenic_i2s->dai_driver.capture.channels_min = 1;
++	ingenic_i2s->dai_driver.capture.channels_max = 2;
++	ingenic_i2s->dai_driver.capture.rates = SNDRV_PCM_RATE_8000_192000;
++	ingenic_i2s->dai_driver.capture.formats = INGENIC_I2S_FORMATS;
++
++	platform_set_drvdata(pdev, (void *)ingenic_i2s);
++
++	ret = devm_snd_soc_register_component(&pdev->dev, &ingenic_i2s_component,
++			&ingenic_i2s->dai_driver, 1);
++	if (!ret)
++		dev_info(&pdev->dev, "i2s-tloop platform probe success\n");
++	else
++		dev_err(&pdev->dev, "i2s-tloop platform probe fail !\n");
++
++
++	ret = sysfs_create_group(&pdev->dev.kobj, &dump_attr_group);
++	if (ret)
++		dev_info(&pdev->dev, "i2s attr create failed\n");
++
++	ret = ingenic_dma_pcm_register(&pdev->dev, NULL, ingenic_i2s->ingenic_pcm);
++
++	return ret;
++}
++
++static const struct of_device_id i2s_dt_match[] = {
++	{ .compatible = "ingenic,i2s-tloop", .data = NULL },
++	{},
++};
++MODULE_DEVICE_TABLE(of, i2s_dt_match);
++
++static struct platform_driver ingenic_i2s_plat_driver = {
++	.probe  = ingenic_i2s_platfrom_probe,
++	.driver = {
++		.name = "asoc-aic-i2s-tloop",
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(i2s_dt_match),
++	},
++};
++module_platform_driver(ingenic_i2s_plat_driver);
++
++MODULE_AUTHOR("cli <chen.li@ingenic.com>");
++MODULE_DESCRIPTION("INGENIC AIC I2S SoC Interface");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-aic-i2s");
+diff --git a/module_drivers/sound/soc/ingenic/as-v1/asoc-i2s.c b/module_drivers/sound/soc/ingenic/as-v1/asoc-i2s.c
+new file mode 100644
+index 000000000..dac5c37ae
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v1/asoc-i2s.c
+@@ -0,0 +1,637 @@
++/*
++ *  sound/soc/ingenic/asoc-i2s.c
++ *  ALSA Soc Audio Layer -- ingenic i2s (part of aic controller) driver
++ *
++ *  Copyright 2014 Ingenic Semiconductor Co.,Ltd
++ *	cli <chen.li@ingenic.com>
++ *
++ *  This program is free software; you can redistribute  it and/or modify it
++ *  under  the terms of  the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the  License, or (at your
++ *  option) any later version.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/initval.h>
++#include <sound/soc.h>
++#include <sound/soc-dai.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <sound/dmaengine_pcm.h>
++#include "asoc-aic.h"
++#include "asoc-dma.h"
++
++static int ingenic_i2s_debug = 0;
++module_param(ingenic_i2s_debug, int, 0644);
++#define I2S_DEBUG_MSG(msg...)					\
++	do {										\
++		if (ingenic_i2s_debug)					\
++			pr_debug("I2S: " msg);				\
++	} while(0)
++
++struct ingenic_i2s_priv {
++	bool ctrl_sysclk_output;
++	bool have_internal_codec;
++	bool ctrl_stop_bitclk;
++	bool have_share_clk;
++	bool init_clk_direction;
++	bool ctrl_record_channel;
++};
++
++struct ingenic_i2s {
++	struct device *aic;	/*register access device*/
++#define I2S_WRITE 0x1
++#define I2S_READ  0x2
++	int i2s_mode;
++	struct snd_dmaengine_dai_dma_data playback_dma_data;
++	struct snd_dmaengine_dai_dma_data capture_dma_data;
++	struct snd_soc_dai_driver dai_driver;
++	dma_addr_t dma_base;
++	struct clk *cgu_clk;
++	int playback_channels;
++	const struct ingenic_i2s_priv *priv;
++};
++
++#define I2S_RFIFO_DEPTH 32
++#define I2S_TFIFO_DEPTH 64
++#define TX_FIFO_LEVEL 16
++
++static const struct ingenic_i2s_priv common_priv_data[];
++static const struct of_device_id i2s_dt_match[];
++
++static void dump_registers(struct device *aic)
++{
++	struct ingenic_aic *ingenic_aic = dev_get_drvdata(aic);
++
++	pr_info("AIC_FR\t\t%p : 0x%08x\n", (ingenic_aic->vaddr_base+AICFR),ingenic_aic_read_reg(aic, AICFR));
++	pr_info("AIC_CR\t\t%p : 0x%08x\n", (ingenic_aic->vaddr_base+AICCR),ingenic_aic_read_reg(aic, AICCR));
++	pr_info("AIC_I2SCR\t%p : 0x%08x\n",(ingenic_aic->vaddr_base+I2SCR),ingenic_aic_read_reg(aic, I2SCR));
++	pr_info("AIC_SR\t\t%p : 0x%08x\n", (ingenic_aic->vaddr_base+AICSR),ingenic_aic_read_reg(aic, AICSR));
++	pr_info("AIC_I2SSR\t%p : 0x%08x\n",(ingenic_aic->vaddr_base+I2SSR),ingenic_aic_read_reg(aic, I2SSR));
++	pr_info("AIC_I2SDIV\t%p : 0x%08x\n",(ingenic_aic->vaddr_base+I2SDIV),ingenic_aic_read_reg(aic, I2SDIV));
++	pr_info("AIC_DR\t\t%p\n", (ingenic_aic->vaddr_base+AICDR));
++	return;
++}
++
++static int ingenic_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
++{
++	struct ingenic_i2s *ingenic_i2s = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_i2s->aic;
++
++	I2S_DEBUG_MSG("enter %s dai fmt %x\n", __func__, fmt);
++
++	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_I2S:		/*i2s format*/
++		__i2s_select_i2s_fmt(aic);
++		break;
++	case SND_SOC_DAIFMT_MSB:
++		__i2s_select_msb_fmt(aic);	/*msb format*/
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++	case SND_SOC_DAIFMT_NB_NF:
++		__i2s_send_lfirst(aic);
++		break;
++	case SND_SOC_DAIFMT_NB_IF:
++		__i2s_send_rfirst(aic);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++	case SND_SOC_DAIFMT_CBM_CFM:	/*sync and bit clk (codec master : i2s slave)*/
++		__i2s_bclk_input(aic);
++	 	__i2s_sync_input(aic);
++		break;
++	case SND_SOC_DAIFMT_CBS_CFM:
++		__i2s_bclk_output(aic);
++	 	__i2s_sync_output(aic);
++		break;
++	default:
++	 	return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int ingenic_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
++{
++	struct ingenic_i2s *ingenic_i2s = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_i2s->aic;
++
++	I2S_DEBUG_MSG("enter %s div_id %d div %d\n", __func__, div_id, div);
++
++	if (ingenic_i2s->priv->have_share_clk) {
++		if (div_id & INGENIC_I2S_PLAYBACK) {
++			__i2s_set_dv(aic, div);
++		} else {
++#ifdef CONFIG_SND_ASOC_INGENIC_SHARE_CLK
++				__i2s_set_dv(aic, div);
++#else
++				__i2s_set_idv(aic, div);
++#endif
++		}
++	}
++
++	return 0;
++}
++
++static int ingenic_set_sysclk(struct snd_soc_dai *dai, int clk_id,
++		unsigned int freq, int dir)
++{
++	struct ingenic_i2s *ingenic_i2s = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_i2s->aic;
++
++	I2S_DEBUG_MSG("enter %s clk_id %d req %d clk dir %d\n", __func__,
++				  clk_id, freq, dir);
++
++	if (ingenic_i2s->priv->have_internal_codec) {
++		if (clk_id & INGENIC_I2S_INNER_CODEC) {
++			__aic_select_internal_codec(aic);
++			__i2s_codec_slave(aic);
++		} else {
++			__aic_select_external_codec(aic);
++			__i2s_codec_master(aic);
++		}
++	}
++
++	if (clk_id & INGENIC_I2S_PLAYBACK) {
++		aic_set_rate(aic, freq, STREAM_PLAY);
++	} else if (clk_id & INGENIC_I2S_CAPTURE) {
++		if (ingenic_i2s->priv->have_share_clk) {
++#ifdef CONFIG_SND_ASOC_INGENIC_SHARE_CLK
++			aic_set_rate(aic, freq, STREAM_PLAY);
++#else
++			aic_set_rate(aic, freq, STREAM_RECORD);
++#endif
++		} else {
++			aic_set_rate(aic, freq, STREAM_RECORD);
++		}
++	} else {
++		aic_set_rate(aic, freq, STREAM_COMMON);
++	}
++
++	if (ingenic_i2s->priv->ctrl_sysclk_output) {
++		if (dir  == SND_SOC_CLOCK_OUT)
++			__i2s_select_sysclk_output(aic);
++		else
++			__i2s_select_sysclk_input(aic);
++	}
++
++	return 0;
++}
++
++static int ingenic_i2s_startup(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct ingenic_i2s *ingenic_i2s = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_i2s->aic;
++	enum aic_mode work_mode = AIC_I2S_MODE;
++
++	I2S_DEBUG_MSG("enter %s, substream = %s\n", __func__,
++				  (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture");
++
++	work_mode = aic_set_work_mode(aic, work_mode, true);
++	if (work_mode != AIC_I2S_MODE) {
++		dev_warn(ingenic_i2s->aic, "Aic now is working on %s mode, open i2s mode failed\n",
++				aic_work_mode_str(work_mode));
++		return -EBUSY;
++	}
++
++	if (!ingenic_i2s->i2s_mode) {
++		__aic_select_i2s(aic);
++		__i2s_play_lastsample(aic);
++
++		if (ingenic_i2s->priv->have_share_clk) {
++#ifdef CONFIG_SND_ASOC_INGENIC_SHARE_CLK
++			__i2s_share_clk(aic);
++#else
++			__i2s_independent_clk(aic);
++#endif
++		}
++
++		__i2s_aic_unpacket16(aic);
++		__aic_enable(aic);
++	}
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		ingenic_i2s->i2s_mode |= I2S_WRITE;
++	} else {
++		ingenic_i2s->i2s_mode |= I2S_READ;
++	}
++	return 0;
++}
++
++
++static int ingenic_i2s_hw_params(struct snd_pcm_substream *substream,
++				struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
++{
++	int channels = params_channels(params);
++	int fmt_width = snd_pcm_format_width(params_format(params));
++	int phys_width = snd_pcm_format_physical_width(params_format(params));
++	struct ingenic_i2s *ingenic_i2s = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_i2s->aic;
++	enum dma_slave_buswidth buswidth;
++	int trigger;
++
++	I2S_DEBUG_MSG("enter %s, substream = %s\n", __func__,
++				  (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture");
++
++	/* format */
++	if (phys_width == 8)
++		buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
++	else if (phys_width == 16)
++		buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
++	else if (phys_width == 24)
++		buswidth = DMA_SLAVE_BUSWIDTH_3_BYTES;
++	else if (phys_width == 32)
++		buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
++	else
++		return -EINVAL;
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		/* channel */
++		ingenic_i2s->playback_channels = channels;
++		__i2s_channel(aic, ingenic_i2s->playback_channels);
++
++		if (channels == 1)
++			__i2s_m2s_enable(aic);	/*unavailed ??*/
++		else
++			__i2s_m2s_disable(aic);
++
++		ingenic_i2s->playback_dma_data.addr_width = buswidth;
++		ingenic_i2s->playback_dma_data.maxburst = I2S_TFIFO_DEPTH / 2;
++
++		trigger = I2S_TFIFO_DEPTH - (ingenic_i2s->playback_dma_data.maxburst);
++		__i2s_set_oss(aic, fmt_width);
++		__i2s_set_transmit_trigger(aic, (trigger/2));
++	} else {
++		ingenic_i2s->capture_dma_data.addr_width = buswidth;
++		ingenic_i2s->capture_dma_data.maxburst = I2S_TFIFO_DEPTH/2;
++
++		trigger = ingenic_i2s->capture_dma_data.maxburst;
++		__i2s_set_iss(aic, fmt_width);
++		__i2s_set_receive_trigger(aic, (trigger/2 - 1));
++
++		if (ingenic_i2s->priv->ctrl_record_channel) {
++			if (channels == 2) {
++				__i2s_enable_stereo(aic);
++			} else if (channels == 1) {
++#ifdef CONFIG_SND_ASOC_INGENIC_MONO_LEFT
++				__i2s_enable_monoctr_left(aic);
++#endif
++#ifdef CONFIG_SND_ASOC_INGENIC_MONO_RIGHT
++				__i2s_enable_monoctr_right(aic);
++#endif
++			}
++		}
++	}
++
++	return 0;
++}
++
++static void ingenic_i2s_start_substream(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct ingenic_i2s *ingenic_i2s = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_i2s->aic;
++	int level, i, level_d, discard;
++	I2S_DEBUG_MSG("enter %s, substream = %s\n", __func__,
++				  (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture");
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		int timeout = 1000;
++
++		__aic_clear_tur(aic);
++		__aic_flush_txfifo(aic);
++
++		/* Wait flush fifo complete */
++		while (__aic_read_tfl(aic)) {
++			if (--timeout < 0) {
++				dev_printk(KERN_DEBUG, dai->dev, "Flush transmit FIFO timeout !\n");
++				break;
++			}
++		}
++
++		__i2s_enable_transmit_dma(aic);
++		__i2s_enable_replay(aic);
++
++		I2S_DEBUG_MSG("aic dirty fifo size %d\n", level);
++		if (ingenic_i2s_debug) __aic_en_tur_int(aic);
++	} else {
++		level_d = level = __aic_read_rfl(aic);
++		__aic_clear_ror(aic);
++
++		__i2s_enable_record(aic);
++
++		/*Left and right channel will inversion, no sure, just makesure*/
++		for (i = 0; i < level; i++)
++			discard = __aic_read_rxfifo(aic);
++
++		__i2s_enable_receive_dma(aic);
++
++		I2S_DEBUG_MSG("aic dirty fifo size %d\n", level_d);
++
++		if (ingenic_i2s_debug)
++			__aic_en_ror_int(aic);
++	}
++	return;
++}
++
++static void ingenic_i2s_stop_substream(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct ingenic_i2s *ingenic_i2s = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_i2s->aic;
++	I2S_DEBUG_MSG("enter %s, substream = %s\n", __func__,
++				  (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture");
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		if (ingenic_i2s_debug) __aic_dis_tur_int(aic);
++		if (__i2s_transmit_dma_is_enable(aic))
++			__i2s_disable_transmit_dma(aic);
++		__i2s_disable_replay(aic);
++	} else {
++		if (ingenic_i2s_debug) __aic_dis_ror_int(aic);
++		if (__i2s_receive_dma_is_enable(aic))
++			__i2s_disable_receive_dma(aic);
++		__i2s_disable_record(aic);
++	}
++	return;
++}
++
++static int ingenic_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
++{
++	struct ingenic_pcm_runtime_data *prtd = substream_to_prtd(substream);
++	struct ingenic_i2s *ingenic_i2s = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_i2s->aic;
++	int ret;
++
++	I2S_DEBUG_MSG("enter %s, substream = %s cmd = %d\n",  __func__,
++				  (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture",
++				  cmd);
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		if (atomic_read(&prtd->wait_stopdma))
++			return -EPIPE;
++		I2S_DEBUG_MSG("i2s start\n");
++
++		aic_clk_ctrl(aic, true);
++
++		ingenic_i2s_start_substream(substream, dai);
++		break;
++	case SNDRV_PCM_TRIGGER_STOP:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++		ret = dmaengine_terminate_all(prtd->dma_chan);
++		if (ret == -EBUSY){
++			atomic_set(&prtd->wait_stopdma, 1);
++			return 0;
++		}
++		I2S_DEBUG_MSG("i2s stop\n");
++
++		ingenic_i2s_stop_substream(substream, dai);
++
++		aic_clk_ctrl(aic, false);
++		break;
++	}
++	return 0;
++}
++
++static void ingenic_i2s_shutdown(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai) {
++	struct ingenic_i2s *ingenic_i2s = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_i2s->aic;
++	enum aic_mode work_mode = AIC_I2S_MODE;
++
++	I2S_DEBUG_MSG("enter %s, substream = %s\n", __func__,
++				  (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture");
++
++	work_mode = aic_set_work_mode(ingenic_i2s->aic, work_mode, false);
++	BUG_ON((work_mode != AIC_NO_MODE));
++
++	ingenic_i2s_stop_substream(substream, dai);
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++		ingenic_i2s->i2s_mode &= ~I2S_WRITE;
++	else
++		ingenic_i2s->i2s_mode &= ~I2S_READ;
++
++	if (!ingenic_i2s->i2s_mode)
++		__aic_disable(aic);
++	return;
++}
++
++static int ingenic_i2s_probe(struct snd_soc_dai *dai)
++{
++	struct ingenic_i2s *ingenic_i2s = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_i2s->aic;
++
++	ingenic_i2s->playback_dma_data.addr = ingenic_i2s->dma_base + AICDR;
++	ingenic_i2s->playback_dma_data.fifo_size = I2S_TFIFO_DEPTH;
++	ingenic_i2s->capture_dma_data.addr = ingenic_i2s->dma_base + AICDR;
++	ingenic_i2s->capture_dma_data.fifo_size = I2S_RFIFO_DEPTH;
++
++	snd_soc_dai_init_dma_data(dai, &ingenic_i2s->playback_dma_data,
++			&ingenic_i2s->capture_dma_data);
++
++	/* inner codec(icdc) probe must have mclk*/
++	__aic_disable(aic);
++
++	if (ingenic_i2s->priv->ctrl_stop_bitclk) {
++		__i2s_stop_bitclk(aic);
++		__aic_select_i2s(aic);
++
++		if (ingenic_i2s->priv->init_clk_direction) {
++			__i2s_codec_slave(aic);
++			__i2s_slave_clkset(aic);
++		}
++
++		__aic_select_internal_codec(aic);
++		__i2s_enable_sysclk_output(aic);
++		__i2s_select_sysclk_output(aic);
++		__i2s_start_bitclk(aic);
++	} else {
++		__aic_select_i2s(aic);
++		if (ingenic_i2s->priv->init_clk_direction) {
++			__i2s_bclk_output(aic);
++			__i2s_sync_output(aic);
++		}
++	}
++
++	__aic_enable(aic);
++
++	return 0;
++}
++
++static struct snd_soc_dai_ops ingenic_i2s_dai_ops = {
++	.startup	= ingenic_i2s_startup,
++	.trigger 	= ingenic_i2s_trigger,
++	.hw_params 	= ingenic_i2s_hw_params,
++	.shutdown	= ingenic_i2s_shutdown,
++	.set_fmt	= ingenic_set_dai_fmt,
++	.set_sysclk	= ingenic_set_sysclk,
++	.set_clkdiv	= ingenic_set_clkdiv,
++};
++
++#define ingenic_i2s_suspend	NULL
++#define ingenic_i2s_resume	NULL
++
++static ssize_t ingenic_i2s_regs_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct ingenic_i2s *ingenic_i2s = dev_get_drvdata(dev);
++	dump_registers(ingenic_i2s->aic);
++	return 0;
++}
++
++static DEVICE_ATTR(i2s_regs, S_IRUGO, ingenic_i2s_regs_show, NULL);
++static const struct attribute *dump_attrs[] = {
++	&dev_attr_i2s_regs.attr,
++	NULL,
++};
++
++static const struct attribute_group dump_attr_group = {
++	.attrs = (struct attribute **)dump_attrs,
++};
++
++static const struct snd_soc_component_driver ingenic_i2s_component = {
++	.name		= "aic-i2s",
++};
++
++#define INGENIC_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | \
++		SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \
++		SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE | \
++		SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE | \
++		SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE | \
++		SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_U24_3LE | \
++		SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_U24_3BE | \
++		SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
++		SNDRV_PCM_FMTBIT_S20_3BE | SNDRV_PCM_FMTBIT_U20_3BE | \
++		SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
++		SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_U18_3BE )
++
++static int ingenic_i2s_platfrom_probe(struct platform_device *pdev)
++{
++	struct device_node *parent = of_get_parent(pdev->dev.of_node);
++	struct resource res;
++	struct ingenic_i2s *ingenic_i2s;
++	const struct of_device_id *match;
++	int ret;
++
++	if (!parent)
++		return -ENOMEM;
++
++	ingenic_i2s = devm_kzalloc(&pdev->dev, sizeof(struct ingenic_i2s), GFP_KERNEL);
++	if (!ingenic_i2s)
++		return -ENOMEM;
++
++	match = of_match_node(i2s_dt_match, pdev->dev.of_node);
++	if (!match)
++		return -ENODEV;
++
++	ingenic_i2s->priv = !match->data ? common_priv_data : (struct ingenic_i2s_priv *)match->data;
++	ret = of_address_to_resource(parent, 0, &res);
++	if (ret)
++		return ret;
++
++	ingenic_i2s->dma_base = res.start;
++	ingenic_i2s->aic = pdev->dev.parent;
++	ingenic_i2s->i2s_mode = 0;
++	ingenic_i2s->dai_driver.probe = ingenic_i2s_probe;
++	//ingenic_i2s->dai_driver.suspend = ingenic_i2s_suspend;
++	//ingenic_i2s->dai_driver.resume = ingenic_i2s_resume;
++	ingenic_i2s->dai_driver.ops = &ingenic_i2s_dai_ops;
++	ingenic_i2s->dai_driver.playback.channels_min = 1;
++	ingenic_i2s->dai_driver.playback.channels_max = 2;
++	ingenic_i2s->dai_driver.playback.rates = SNDRV_PCM_RATE_8000_192000;
++	ingenic_i2s->dai_driver.playback.formats = INGENIC_I2S_FORMATS;
++	ingenic_i2s->dai_driver.capture.channels_min = 1;
++	ingenic_i2s->dai_driver.capture.channels_max = 2;
++	ingenic_i2s->dai_driver.capture.rates = SNDRV_PCM_RATE_8000_192000;
++	ingenic_i2s->dai_driver.capture.formats = INGENIC_I2S_FORMATS;
++	ingenic_i2s->playback_channels = 2;	/*default value*/
++
++	platform_set_drvdata(pdev, (void *)ingenic_i2s);
++
++	ret = devm_snd_soc_register_component(&pdev->dev, &ingenic_i2s_component,
++			&ingenic_i2s->dai_driver, 1);
++	if (!ret)
++		dev_info(&pdev->dev, "i2s platform probe success\n");
++
++	ret = sysfs_create_group(&pdev->dev.kobj, &dump_attr_group);
++	if (ret)
++		dev_info(&pdev->dev, "i2s attr create failed\n");
++
++	return ret;
++}
++
++static const struct ingenic_i2s_priv common_priv_data[] = {
++	{
++		.ctrl_sysclk_output = true,
++		.have_internal_codec = true,
++		.ctrl_stop_bitclk = true,
++		.have_share_clk = false,
++		.init_clk_direction = false,
++		.ctrl_record_channel = false,
++	},
++};
++
++static const struct ingenic_i2s_priv x1600_priv_data[] = {
++	{
++		.ctrl_sysclk_output = false,
++		.have_internal_codec = false,
++		.ctrl_stop_bitclk = false,
++		.have_share_clk = true,
++		.init_clk_direction = true,
++		.ctrl_record_channel = true,
++	},
++};
++
++static const struct ingenic_i2s_priv x2500_priv_data[] = {
++	{
++		.ctrl_sysclk_output = true,
++		.have_internal_codec = true,
++		.ctrl_stop_bitclk = true,
++		.have_share_clk = false,
++		.init_clk_direction = true,
++		.ctrl_record_channel = true,
++	},
++};
++
++static const struct of_device_id i2s_dt_match[] = {
++	{ .compatible = "ingenic,i2s", .data = (void *)common_priv_data },
++	{ .compatible = "ingenic,x1600-i2s", .data = (void *)x1600_priv_data },
++	{ .compatible = "ingenic,x2500-i2s", .data = (void *)x2500_priv_data },
++	{},
++};
++MODULE_DEVICE_TABLE(of, i2s_dt_match);
++
++static struct platform_driver ingenic_i2s_plat_driver = {
++	.probe  = ingenic_i2s_platfrom_probe,
++	.driver = {
++		.name = "asoc-aic-i2s",
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(i2s_dt_match),
++	},
++};
++module_platform_driver(ingenic_i2s_plat_driver);
++
++MODULE_AUTHOR("cli <chen.li@ingenic.com>");
++MODULE_DESCRIPTION("INGENIC AIC I2S SoC Interface");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-aic-i2s");
+diff --git a/module_drivers/sound/soc/ingenic/as-v1/asoc-pcm.c b/module_drivers/sound/soc/ingenic/as-v1/asoc-pcm.c
+new file mode 100644
+index 000000000..cfbfd6442
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v1/asoc-pcm.c
+@@ -0,0 +1,417 @@
++/*
++ *  sound/soc/ingenic/asoc-pcm.c
++ *  ALSA Soc Audio Layer -- ingenic pcm (part of aic controller) driver
++ *
++ *  Copyright 2014 Ingenic Semiconductor Co.,Ltd
++ *	cscheng <shicheng.cheng@ingenic.com>
++ *
++ *  This program is free software; you can redistribute  it and/or modify it
++ *  under  the terms of  the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the  License, or (at your
++ *  option) any later version.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/initval.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <sound/soc.h>
++#include <sound/soc-dai.h>
++#include <linux/slab.h>
++#include "asoc-pcm.h"
++
++static int ingenic_pcm_debug = 0;
++module_param(ingenic_pcm_debug, int, 0644);
++#define PCM_DEBUG_MSG(msg...)			\
++	do {					\
++		if (ingenic_pcm_debug)		\
++			printk(KERN_DEBUG"PCM: " msg);	\
++	} while(0)
++
++#define PCM_RFIFO_DEPTH 16
++#define PCM_TFIFO_DEPTH 16
++#define INGENIC_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 |  SNDRV_PCM_FMTBIT_S16_LE)
++
++static void dump_registers(struct device *dev)
++{
++	struct ingenic_pcm *ingenic_pcm = dev_get_drvdata(dev);
++	pr_info("PCMCTL  %p : 0x%08x\n", (ingenic_pcm->vaddr_base+PCMCTL),pcm_read_reg(dev, PCMCTL));
++	pr_info("PCMCFG  %p : 0x%08x\n", (ingenic_pcm->vaddr_base+PCMCFG),pcm_read_reg(dev, PCMCFG));
++	pr_info("PCMINTC %p : 0x%08x\n", (ingenic_pcm->vaddr_base+PCMINTC),pcm_read_reg(dev,PCMINTC));
++	pr_info("PCMINTS %p : 0x%08x\n",(ingenic_pcm->vaddr_base+PCMINTS),pcm_read_reg(dev, PCMINTS));
++	pr_info("PCMDIV  %p : 0x%08x\n",(ingenic_pcm->vaddr_base+PCMDIV),pcm_read_reg(dev, PCMDIV));
++	return;
++}
++
++static int ingenic_pcm_startup(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct device *dev = dai->dev;
++	struct ingenic_pcm *ingenic_pcm = dev_get_drvdata(dai->dev);
++
++	PCM_DEBUG_MSG("enter %s, substream = %s\n",
++			__func__,
++			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture");
++
++	if (!ingenic_pcm->pcm_mode) {
++		clk_prepare_enable(ingenic_pcm->clk_gate);
++#if 1
++		__pcm_as_slaver(dev);
++#else
++		clk_set_rate(ingenic_pcm->clk, 9600000);
++		clk_prepare_enable(ingenic_pcm->clk);
++		__pcm_as_master(dev);
++		__pcm_set_clkdiv(dev, 9600000/20/8000 - 1);
++		__pcm_set_syndiv(dev, 20 - 1);
++#endif
++		__pcm_set_msb_one_shift_in(dev);
++		__pcm_set_msb_one_shift_out(dev);
++		__pcm_play_lastsample(dev);
++		__pcm_enable(dev);
++		__pcm_clock_enable(dev);
++	}
++
++	if (substream->stream ==
++			SNDRV_PCM_STREAM_PLAYBACK) {
++		__pcm_disable_transmit_dma(dev);
++		__pcm_disable_replay(dev);
++		__pcm_clear_tur(dev);
++		ingenic_pcm->pcm_mode |= PCM_WRITE;
++	} else {
++		__pcm_disable_receive_dma(dev);
++		__pcm_disable_record(dev);
++		__pcm_clear_ror(dev);
++		ingenic_pcm->pcm_mode |= PCM_READ;
++	}
++	printk("start set PCM register....\n");
++	return 0;
++}
++
++static int ingenic_pcm_hw_params(struct snd_pcm_substream *substream,
++				struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
++{
++	struct device *dev = dai->dev;
++	struct ingenic_pcm *ingenic_pcm = dev_get_drvdata(dai->dev);
++	int fmt_width = snd_pcm_format_width(params_format(params));
++	enum dma_slave_buswidth buswidth;
++	int trigger;
++
++	PCM_DEBUG_MSG("enter %s, substream = %s\n",
++			__func__,
++			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture");
++
++	if (!((1 << params_format(params)) & INGENIC_PCM_FORMATS) ||
++			params_channels(params) != 1) {
++		dev_err(dai->dev, "hw params not inval channel %d params %x\n",
++				params_channels(params), params_format(params));
++		return -EINVAL;
++	}
++
++	/* format 8 bit or 16 bit*/
++	if (fmt_width == 8)
++		buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
++	else
++		buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		ingenic_pcm->tx_dma_data.addr_width = buswidth;
++		ingenic_pcm->tx_dma_data.maxburst = (PCM_TFIFO_DEPTH * buswidth)/2;
++		trigger = PCM_TFIFO_DEPTH - (ingenic_pcm->tx_dma_data.maxburst/(int)buswidth);
++		__pcm_set_oss_sample_size(dev, fmt_width == 8 ? 0 : 1);
++		__pcm_set_transmit_trigger(dev, trigger);
++//		snd_soc_dai_set_dma_data(dai, substream, (void *)&ingenic_pcm->tx_dma_data);
++	} else {
++		ingenic_pcm->rx_dma_data.addr_width = buswidth;
++		ingenic_pcm->rx_dma_data.maxburst = (PCM_RFIFO_DEPTH * buswidth)/2;
++		trigger = ingenic_pcm->rx_dma_data.maxburst/(int)buswidth;
++		__pcm_set_iss_sample_size(dev, fmt_width == 8 ? 0 : 1);
++		__pcm_set_receive_trigger(dev, trigger);
++//		snd_soc_dai_set_dma_data(dai, substream, (void *)&ingenic_pcm->rx_dma_data);
++	}
++	return 0;
++}
++
++static void ingenic_pcm_start_substream(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct device *dev = dai->dev;
++	PCM_DEBUG_MSG("enter %s, substream = %s\n",
++			__func__,
++			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture");
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		__pcm_enable_transmit_dma(dev);
++		__pcm_enable_replay(dev);
++	} else {
++		__pcm_enable_record(dev);
++		__pcm_enable_receive_dma(dev);
++	}
++	return;
++}
++
++static void ingenic_pcm_stop_substream(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct device *dev = dai->dev;
++	int timeout = 150000;
++	PCM_DEBUG_MSG("enter %s, substream = %s\n",
++			__func__,
++			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture");
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		if (__pcm_transmit_dma_is_enable(dev)) {
++			__pcm_disable_transmit_dma(dev);
++			__pcm_clear_tur(dev);
++			/* Hrtimer mode: stop will be happen in any where, make sure there is
++			 *	no data transfer on ahb bus before stop dma
++			 * Harzard:
++			 *	In pcm slave mode, the clk maybe stop before here, we will dead here
++			 */
++			while((!__pcm_test_tur(dev)) && (timeout--)){
++				if(timeout == 0){
++					printk("wait tansmit fifo under run error\n");
++					return;
++				}
++			}
++		}
++		__pcm_disable_replay(dev);
++		__pcm_clear_tur(dev);
++	} else {
++		if (__pcm_receive_dma_is_enable(dev)) {
++			__pcm_disable_receive_dma(dev);
++			__pcm_clear_ror(dev);
++			while(!__pcm_test_ror(dev) && timeout--){
++				if(timeout == 0){
++					printk("wait tansmit fifo under run error\n");
++					return;
++				}
++			}
++		}
++		__pcm_disable_record(dev);
++		__pcm_clear_ror(dev);
++	}
++	return;
++}
++
++static int ingenic_pcm_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
++{
++	struct ingenic_pcm_runtime_data *prtd = substream->runtime->private_data;
++	PCM_DEBUG_MSG("enter %s, substream = %s cmd = %d\n",
++		      __func__,
++		      (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture",
++		      cmd);
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		if (atomic_read(&prtd->wait_stopdma))
++			return -EPIPE;
++		printk(KERN_DEBUG"pcm start\n");
++		ingenic_pcm_start_substream(substream, dai);
++		break;
++	case SNDRV_PCM_TRIGGER_STOP:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++		if (atomic_read(&prtd->wait_stopdma))
++			return 0;
++		printk(KERN_DEBUG"pcm stop\n");
++		ingenic_pcm_stop_substream(substream, dai);
++		break;
++	}
++	return 0;
++}
++
++static void ingenic_pcm_shutdown(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai) {
++	struct ingenic_pcm *ingenic_pcm = dev_get_drvdata(dai->dev);
++	struct device *dev = dai->dev;
++
++	PCM_DEBUG_MSG("enter %s, substream = %s\n",
++			__func__,
++			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture");
++	ingenic_pcm_stop_substream(substream, dai);
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++		ingenic_pcm->pcm_mode &= ~PCM_WRITE;
++	else
++		ingenic_pcm->pcm_mode &= ~PCM_READ;
++
++	if (!ingenic_pcm->pcm_mode) {
++		__pcm_disable(dev);
++		__pcm_clock_disable(dev);
++		clk_disable_unprepare(ingenic_pcm->clk_gate);
++	}
++	return;
++}
++
++static int ingenic_pcm_probe(struct snd_soc_dai *dai)
++{
++	struct ingenic_pcm *ingenic_pcm = dev_get_drvdata(dai->dev);
++	ingenic_pcm->rx_dma_data.fifo_size = PCM_RFIFO_DEPTH;
++	ingenic_pcm->tx_dma_data.fifo_size = PCM_TFIFO_DEPTH;
++	snd_soc_dai_init_dma_data(dai, &ingenic_pcm->tx_dma_data, &ingenic_pcm->rx_dma_data);
++	return 0;
++}
++
++
++static struct snd_soc_dai_ops ingenic_pcm_dai_ops = {
++	.startup	= ingenic_pcm_startup,
++	.trigger 	= ingenic_pcm_trigger,
++	.hw_params 	= ingenic_pcm_hw_params,
++	.shutdown	= ingenic_pcm_shutdown,
++};
++
++#define ingenic_pcm_suspend	NULL
++#define ingenic_pcm_resume	NULL
++
++static ssize_t ingenic_pcm_regs_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct ingenic_pcm *ingenic_pcm = dev_get_drvdata(dev);
++	dump_registers(ingenic_pcm->dev);
++	return 0;
++}
++
++static struct device_attribute ingenic_pcm_sysfs_attrs[] = {
++	__ATTR(pcm_regs, S_IRUGO, ingenic_pcm_regs_show, NULL),
++};
++
++static struct snd_soc_dai_driver ingenic_pcm_dai = {
++		.probe   = ingenic_pcm_probe,
++		.playback = {
++			.channels_min = 1,
++			.channels_max = 1,
++			.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
++			.formats = INGENIC_PCM_FORMATS,
++		},
++		.capture = {
++			.channels_min = 1,
++			.channels_max = 1,
++			.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
++			.formats = INGENIC_PCM_FORMATS,
++		},
++		.ops = &ingenic_pcm_dai_ops,
++};
++static const struct snd_soc_component_driver ingenic_pcm_component = {
++	.name		= "ingenic-pcm",
++};
++
++extern int ingenic_dma_pcm_register(struct device *dev,  const struct snd_dmaengine_pcm_config *config, struct ingenic_dma_pcm *ingenic_pcm);
++extern void ingenic_dma_pcm_unregister(struct ingenic_dma_pcm* ingenic_pcm);
++static int ingenic_pcm_platfrom_probe(struct platform_device *pdev)
++{
++	struct ingenic_pcm *ingenic_pcm;
++	struct resource *res = NULL;
++	int i = 0, ret;
++
++	ingenic_pcm = devm_kzalloc(&pdev->dev, sizeof(struct ingenic_pcm), GFP_KERNEL);
++	if (!ingenic_pcm)
++		return -ENOMEM;
++
++	ingenic_pcm->dev = &pdev->dev;
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res)
++		return -ENOENT;
++	if (!devm_request_mem_region(&pdev->dev,
++				res->start, resource_size(res),
++				pdev->name))
++		return -EBUSY;
++
++	ingenic_pcm->res_start = res->start;
++	ingenic_pcm->res_size = resource_size(res);
++	ingenic_pcm->vaddr_base = devm_ioremap_wc(&pdev->dev,
++			ingenic_pcm->res_start, ingenic_pcm->res_size);
++	if (!ingenic_pcm->vaddr_base) {
++		dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
++		return -ENOMEM;
++	}
++
++	ingenic_pcm->clk_gate = clk_get(&pdev->dev, "gate_pcm");
++	if (IS_ERR_OR_NULL(ingenic_pcm->clk_gate)) {
++		ret = PTR_ERR(ingenic_pcm->clk_gate);
++		dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
++		ingenic_pcm->clk_gate = NULL;
++		return ret;
++	}
++	ingenic_pcm->clk = clk_get(&pdev->dev, "cgu_pcm");
++	if (IS_ERR_OR_NULL(ingenic_pcm->clk)) {
++		ret = PTR_ERR(ingenic_pcm->clk);
++		dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
++		goto err_get_clk;
++	}
++	platform_set_drvdata(pdev, (void *)ingenic_pcm);
++
++	ingenic_pcm->pcm_mode = 0;
++	ingenic_pcm->tx_dma_data.addr = (dma_addr_t)ingenic_pcm->res_start + PCMDP;
++	ingenic_pcm->rx_dma_data.addr = (dma_addr_t)ingenic_pcm->res_start + PCMDP;
++	platform_set_drvdata(pdev, (void *)ingenic_pcm);
++
++	for (; i < ARRAY_SIZE(ingenic_pcm_sysfs_attrs); i++) {
++		ret = device_create_file(&pdev->dev, &ingenic_pcm_sysfs_attrs[i]);
++		if (ret)
++			dev_warn(&pdev->dev,"attribute create failed\n");
++	}
++
++	ret = snd_soc_register_component(&pdev->dev, &ingenic_pcm_component,
++					 &ingenic_pcm_dai, 1);
++	if (ret)
++		goto err_register_cpu_dai;
++	dev_info(&pdev->dev, "pcm platform probe success\n");
++
++	ret = ingenic_dma_pcm_register(&pdev->dev, NULL, ingenic_pcm->ingenic_pcm);
++
++	return ret;
++
++err_register_cpu_dai:
++	platform_set_drvdata(pdev, NULL);
++	clk_put(ingenic_pcm->clk);
++	ingenic_pcm->clk = NULL;
++err_get_clk:
++	clk_put(ingenic_pcm->clk_gate);
++	ingenic_pcm->clk_gate = NULL;
++	return ret;
++}
++
++static int ingenic_pcm_platfom_remove(struct platform_device *pdev)
++{
++	struct ingenic_pcm *ingenic_pcm = platform_get_drvdata(pdev);
++	int i;
++	for (i = 0; i < ARRAY_SIZE(ingenic_pcm_sysfs_attrs); i++)
++		device_remove_file(&pdev->dev, &ingenic_pcm_sysfs_attrs[i]);
++	snd_soc_unregister_component(&pdev->dev);
++	ingenic_dma_pcm_unregister(ingenic_pcm->ingenic_pcm);
++	clk_disable_unprepare(ingenic_pcm->clk_gate);
++	clk_disable_unprepare(ingenic_pcm->clk);
++	clk_put(ingenic_pcm->clk_gate);
++	clk_put(ingenic_pcm->clk);
++	platform_set_drvdata(pdev, NULL);
++	return 0;
++}
++
++static const struct of_device_id pcm_dt_match[] = {
++	{.compatible = "ingenic,pcm",},
++	{},
++};
++MODULE_DEVICE_TABLE(of, pcm_dt_match);
++static struct platform_driver ingenic_pcm_plat_driver = {
++	.probe  = ingenic_pcm_platfrom_probe,
++	.remove = ingenic_pcm_platfom_remove,
++	.driver = {
++		.name = "ingenic-asoc-pcm",
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(pcm_dt_match),
++	},
++};
++
++module_platform_driver(ingenic_pcm_plat_driver);
++MODULE_AUTHOR("shicheng.cheng@ingenic.com");
++MODULE_DESCRIPTION("INGENIC AIC PCM SoC Interface");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-pcm");
+diff --git a/module_drivers/sound/soc/ingenic/as-v1/asoc-pcm.h b/module_drivers/sound/soc/ingenic/as-v1/asoc-pcm.h
+new file mode 100644
+index 000000000..ff24b3fac
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v1/asoc-pcm.h
+@@ -0,0 +1,253 @@
++
++#ifndef __ASOC_PCM_H__
++#define __ASOC_PCM_H__
++
++#include <sound/dmaengine_pcm.h>
++#include "asoc-dma.h"
++
++#define PCMCTL		0x00
++#define PCMCFG		0x04
++#define PCMDP		0x08
++#define PCMINTC		0x0C
++#define PCMINTS		0x10
++#define PCMDIV		0x14
++
++struct ingenic_pcm {
++	struct device	*dev;
++	resource_size_t res_start;
++	resource_size_t res_size;
++	void __iomem	*vaddr_base;
++	struct clk	*clk;
++	struct clk	*clk_gate;
++#define PCM_READ	0x1
++#define PCM_WRITE	0X2
++	int pcm_mode;
++	/*for dma*/
++	struct snd_dmaengine_dai_dma_data tx_dma_data;
++	struct snd_dmaengine_dai_dma_data rx_dma_data;
++	struct ingenic_dma_pcm *ingenic_pcm;
++};
++
++static void inline pcm_write_reg(struct device *dev, unsigned int reg,
++		unsigned int val)
++{
++	struct ingenic_pcm *ingenic_pcm = dev_get_drvdata(dev);
++	writel(val, ingenic_pcm->vaddr_base + reg);
++}
++
++static unsigned int inline pcm_read_reg(struct device *dev, unsigned int reg)
++{
++	struct ingenic_pcm *ingenic_pcm = dev_get_drvdata(dev);
++	return readl(ingenic_pcm->vaddr_base + reg);
++}
++
++#define pcm_set_reg(dev, addr, val, mask, offset)\
++	do {	\
++		int tmp_val = val;							\
++		int read_val = pcm_read_reg(dev, addr);         \
++		read_val &= (~mask);                    \
++		tmp_val = ((tmp_val << offset) & mask); \
++		tmp_val |= read_val;                    \
++		pcm_write_reg(dev, addr, tmp_val);           \
++	}while(0)
++
++#define pcm_get_reg(dev, addr, mask, offset)  \
++	((pcm_read_reg(dev, addr) & mask) >> offset)
++
++/*PCMCTL*/
++#define PCM_ERDMA_OFFSET	(9)
++#define PCM_ERDMA_MASK			(0x1 << PCM_ERDMA_OFFSET)
++#define PCM_ETDMA_OFFSET	(8)
++#define PCM_ETDMA_MASK			(0x1 << PCM_ETDMA_OFFSET)
++#define PCM_LSMP_OFFSET		(7)
++#define PCM_LSMP_MASK			(0x1 << PCM_LSMP_OFFSET)
++#define PCM_ERPL_OFFSET		(6)
++#define PCM_ERPL_MASK			(0x1 << PCM_ERPL_OFFSET)
++#define PCM_EREC_OFFSET		(5)
++#define PCM_EREC_MASK			(0x1 << PCM_EREC_OFFSET)
++#define PCM_FLUSH_OFFSET	(4)
++#define PCM_FLUSH_MASK			(0x1 << PCM_FLUSH_OFFSET)
++#define PCM_RST_OFFSET		(3)
++#define PCM_RST_MASK			(0x1 << PCM_RST_OFFSET)
++#define PCM_CLKEN_OFFSET	(1)
++#define PCM_CLKEN_MASK			(0x1 << PCM_CLKEN_OFFSET)
++#define PCM_PCMEN_OFFSET	(0)
++#define PCM_PCMEN_MASK			(0x1 << PCM_PCMEN_OFFSET)
++
++#define __pcm_transmit_dma_is_enable(dev) \
++	pcm_get_reg(dev,PCMCTL,PCM_ETDMA_MASK,PCM_ETDMA_OFFSET)
++#define __pcm_enable_transmit_dma(dev)    \
++	pcm_set_reg(dev,PCMCTL,1,PCM_ETDMA_MASK,PCM_ETDMA_OFFSET)
++#define __pcm_disable_transmit_dma(dev)   \
++	pcm_set_reg(dev,PCMCTL,0,PCM_ETDMA_MASK,PCM_ETDMA_OFFSET)
++
++#define __pcm_receive_dma_is_enable(dev)  \
++	pcm_get_reg(dev,PCMCTL,PCM_ERDMA_MASK,PCM_ERDMA_OFFSET)
++#define __pcm_enable_receive_dma(dev)     \
++	pcm_set_reg(dev,PCMCTL,1,PCM_ERDMA_MASK,PCM_ERDMA_OFFSET)
++#define __pcm_disable_receive_dma(dev)    \
++	pcm_set_reg(dev,PCMCTL,0,PCM_ERDMA_MASK,PCM_ERDMA_OFFSET)
++
++#define __pcm_play_zero(dev)              \
++	pcm_set_reg(dev,PCMCTL,0,PCM_LSMP_MASK,PCM_LSMP_OFFSET)
++#define __pcm_play_lastsample(dev)        \
++	pcm_set_reg(dev,PCMCTL,1,PCM_LSMP_MASK,PCM_LSMP_OFFSET)
++
++#define __pcm_enable_replay(dev)          \
++	pcm_set_reg(dev,PCMCTL,1,PCM_ERPL_MASK,PCM_ERPL_OFFSET)
++#define __pcm_disable_replay(dev)         \
++	pcm_set_reg(dev,PCMCTL,0,PCM_ERPL_MASK,PCM_ERPL_OFFSET)
++#define __pcm_enable_record(dev)          \
++	pcm_set_reg(dev,PCMCTL,1,PCM_EREC_MASK,PCM_EREC_OFFSET)
++#define __pcm_disable_record(dev)         \
++	pcm_set_reg(dev,PCMCTL,0,PCM_EREC_MASK,PCM_EREC_OFFSET)
++
++#define __pcm_flush_fifo(dev)            \
++	pcm_set_reg(dev, PCMCTL,1,PCM_FLUSH_MASK,PCM_FLUSH_OFFSET)
++
++#define __pcm_reset(dev)                  \
++	pcm_set_reg(dev,PCMCTL,1,PCM_RST_MASK,PCM_RST_OFFSET)
++
++#define __pcm_clock_enable(dev)			\
++	pcm_set_reg(dev,PCMCTL,1,PCM_CLKEN_MASK,PCM_CLKEN_OFFSET)
++#define __pcm_clock_disable(dev)			\
++	pcm_set_reg(dev,PCMCTL,0,PCM_CLKEN_MASK,PCM_CLKEN_OFFSET)
++
++#define __pcm_enable(dev)                 \
++	pcm_set_reg(dev,PCMCTL,1,PCM_PCMEN_MASK,PCM_PCMEN_OFFSET)
++#define __pcm_disable(dev)                \
++	pcm_set_reg(dev,PCMCTL,0,PCM_PCMEN_MASK,PCM_PCMEN_OFFSET)
++
++/*PCMCFG*/
++#define PCM_SLOT_OFFSET		(13)
++#define PCM_SLOT_MASK			(0x3 << PCM_SLOT_OFFSET)
++#define PCM_ISS_OFFSET		(12)
++#define PCM_ISS_MASK			(0x1 << PCM_ISS_OFFSET)
++#define PCM_OSS_OFFSET		(11)
++#define PCM_OSS_MASK			(0x1 << PCM_OSS_OFFSET)
++#define PCM_IMSBPOS_OFFSET	(10)
++#define PCM_IMSBPOS_MASK		(0x1 << PCM_IMSBPOS_OFFSET)
++#define PCM_OMSBPOS_OFFSET	(9)
++#define PCM_OMSBPOS_MASK		(0x1 << PCM_OMSBPOS_OFFSET)
++#define PCM_RFTH_OFFSET		(5)
++#define PCM_RFTH_MASK			(0xf << PCM_RFTH_OFFSET)
++#define PCM_TFTH_OFFSET		(1)
++#define PCM_TFTH_MASK			(0xf << PCM_TFTH_OFFSET)
++#define PCM_PCMMOD_OFFSET	(0)
++#define PCM_PCMMOD_MASK			(0x1 << PCM_PCMMOD_OFFSET)
++
++#define __pcm_set_slot(dev,n)	\
++	pcm_set_reg(dev,PCMCFG,n,PCM_SLOT_MASK,PCM_SLOT_OFFSET)
++
++#define __pcm_set_oss_sample_size(dev,n)   \
++	pcm_set_reg(dev,PCMCFG,n,PCM_OSS_MASK,PCM_OSS_OFFSET)
++#define __pcm_set_iss_sample_size(dev,n)   \
++	pcm_set_reg(dev,PCMCFG,n,PCM_ISS_MASK,PCM_ISS_OFFSET)
++
++#define __pcm_set_msb_normal_in(dev)   \
++	pcm_set_reg(dev,PCMCFG,0,PCM_IMSBPOS_MASK,PCM_IMSBPOS_OFFSET)
++#define __pcm_set_msb_one_shift_in(dev)   \
++	pcm_set_reg(dev,PCMCFG,1,PCM_IMSBPOS_MASK,PCM_IMSBPOS_OFFSET)
++
++#define __pcm_set_msb_normal_out(dev)   \
++	pcm_set_reg(dev,PCMCFG,0,PCM_OMSBPOS_MASK,PCM_OMSBPOS_OFFSET)
++#define __pcm_set_msb_one_shift_out(dev)   \
++	pcm_set_reg(dev,PCMCFG,1,PCM_OMSBPOS_MASK,PCM_OMSBPOS_OFFSET)
++
++#define __pcm_set_transmit_trigger(dev,n)  \
++	pcm_set_reg(dev,PCMCFG,n,PCM_TFTH_MASK,PCM_TFTH_OFFSET)
++#define __pcm_set_receive_trigger(dev,n)   \
++	pcm_set_reg(dev,PCMCFG,n,PCM_RFTH_MASK,PCM_RFTH_OFFSET)
++
++#define __pcm_as_master(dev)             \
++	pcm_set_reg(dev,PCMCFG,0,PCM_PCMMOD_MASK,PCM_PCMMOD_OFFSET)
++#define __pcm_as_slaver(dev)             \
++	pcm_set_reg(dev,PCMCFG,1,PCM_PCMMOD_MASK,PCM_PCMMOD_OFFSET)
++
++/*PCMDP*/
++#define PCM_PCMDP_OFFSET		(0)
++#define PCM_PCMDP_MASK			(~0)
++
++#define __pcm_read_fifo(dev)		\
++	pcm_get_reg(dev,PCMDP,PCM_PCMDP_MASK,PCM_PCMDP_OFFSET);
++
++/*PCMINTC*/
++#define PCM_ETFS_OFFSET		(3)
++#define PCM_ETFS_MASK			(0X1 << PCM_ETFS_OFFSET)
++#define PCM_ETUR_OFFSET		(2)
++#define PCM_ETUR_MASK			(0x1 << PCM_ETUR_OFFSET)
++#define PCM_ERFS_OFFSET		(1)
++#define PCM_ERFS_MASK			(0x1 << PCM_ERFS_OFFSET)
++#define PCM_EROR_OFFSET		(0)
++#define PCM_EROR_MASK			(0x1 << PCM_EROR_OFFSET)
++
++#define __pcm_enable_receive_intr(dev)    \
++	pcm_set_reg(dev,PCMINTC,1,PCM_ERFS_MASK,PCM_ERFS_OFFSET)
++#define __pcm_disable_receive_intr(dev)   \
++	pcm_set_reg(dev,PCMINTC,0,PCM_ERFS_MASK,PCM_ERFS_OFFSET)
++
++#define __pcm_enable_underrun_intr(dev)   \
++	pcm_set_reg(dev,PCMINTC,1,PCM_ETUR_MASK,PCM_ETUR_OFFSET)
++#define __pcm_disable_underrun_intr(dev)  \
++	pcm_set_reg(dev,PCMINTC,0,PCM_ETUR_MASK,PCM_ETUR_OFFSET)
++
++#define __pcm_enable_transmit_intr(dev)   \
++	pcm_set_reg(dev,PCMINTC,1,PCM_ETFS_MASK,PCM_ETFS_OFFSET)
++#define __pcm_disable_transmit_intr(dev)  \
++	pcm_set_reg(dev,PCMINTC,0,PCM_ETFS_MASK,PCM_ETFS_OFFSET)
++
++#define __pcm_enable_overrun_intr(dev)    \
++	pcm_set_reg(dev,PCMINTC,1,PCM_EROR_MASK,PCM_EROR_OFFSET)
++#define __pcm_disable_overrun_intr(dev)   \
++	pcm_set_reg(dev,PCMINTC,0,PCM_EROR_MASK,PCM_EROR_OFFSET)
++
++/*PCMINTS*/
++#define PCM_RSTS_OFFSET		(14)
++#define PCM_RSTS_MASK			(0x1 << PCM_RSTS_OFFSET)
++#define PCM_TFL_OFFSET		(9)
++#define PCM_TFL_MASK			(0x1f << PCM_TFL_OFFSET)
++#define PCM_TFS_OFFSET		(8)
++#define PCM_TFS_MASK			(0x1 << PCM_TFS_OFFSET)
++#define PCM_TUR_OFFSET		(7)
++#define PCM_TUR_MASK			(0x1 << PCM_TUR_OFFSET)
++#define PCM_RFL_OFFSET		(2)
++#define PCM_RFL_MASK			(0x1f << PCM_RFL_OFFSET)
++#define PCM_RFS_OFFSET		(1)
++#define PCM_RFS_MASK			(0x1 << PCM_RFS_OFFSET)
++#define PCM_ROR_OFFSET		(0)
++#define PCM_ROR_MASK			(0X1 << PCM_ROR_OFFSET)
++
++#define __pcm_test_rst_complie(dev)	\
++	!pcm_get_reg(dev,PCMINTS,PCM_RSTS_MASK,PCM_RSTS_OFFSET)
++#define __pcm_test_tfl(dev)               \
++	pcm_get_reg(dev,PCMINTS,PCM_TFL_MASK,PCM_TFL_OFFSET)
++#define __pcm_test_tfs(dev)               \
++	pcm_get_reg(dev,PCMINTS,PCM_TFS_MASK,PCM_TFS_OFFSET)
++#define __pcm_test_tur(dev)               \
++	pcm_get_reg(dev,PCMINTS,PCM_TUR_MASK,PCM_TUR_OFFSET)
++#define __pcm_clear_tur(dev)	\
++	pcm_set_reg(dev,PCMINTS,0,PCM_TUR_MASK,PCM_TUR_OFFSET)
++#define __pcm_test_rfl(dev)               \
++	pcm_get_reg(dev,PCMINTS,PCM_RFL_MASK,PCM_RFL_OFFSET)
++#define __pcm_test_rfs(dev)               \
++	pcm_get_reg(dev,PCMINTS,PCM_RFS_MASK,PCM_RFS_OFFSET)
++#define __pcm_clear_ror(dev)	\
++	pcm_set_reg(dev,PCMINTS,0,PCM_ROR_MASK,PCM_ROR_OFFSET)
++#define __pcm_test_ror(dev)               \
++	pcm_get_reg(dev,PCMINTS,PCM_ROR_MASK,PCM_ROR_OFFSET)
++/* PCMDIV */
++#define PCM_SYNC_OFFSET		(11)
++#define PCM_SYNC_MASK			(0x3f << PCM_SYNC_OFFSET)
++#define PCM_SYNDIV_OFFSET	(6)
++#define PCM_SYNDIV_MASK			(0x1f << PCM_SYNDIV_OFFSET)
++#define PCM_CLKDIV_OFFSET	(0)
++#define PCM_CLKDIV_MASK			(0x3f << PCM_CLKDIV_OFFSET)
++
++#define __pcm_set_sync(dev,n)	\
++	pcm_set_reg(dev,PCMDIV,n,PCM_SYNC_MASK,PCM_SYNC_OFFSET)
++#define __pcm_set_syndiv(dev,n)	\
++	pcm_set_reg(dev,PCMDIV,n,PCM_SYNDIV_MASK,PCM_SYNDIV_OFFSET)
++#define __pcm_set_clkdiv(dev,n)	\
++	pcm_set_reg(dev,PCMDIV,n,PCM_CLKDIV_MASK,PCM_CLKDIV_OFFSET)
++
++#endif /* __ASOC_PCM_H__ */
+diff --git a/module_drivers/sound/soc/ingenic/as-v1/asoc-spdif.c b/module_drivers/sound/soc/ingenic/as-v1/asoc-spdif.c
+new file mode 100644
+index 000000000..75a7fbaec
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v1/asoc-spdif.c
+@@ -0,0 +1,490 @@
++/*
++ *  sound/soc/ingenic/asoc-spdif.c
++ *  ALSA Soc Audio Layer -- ingenic spdif (part of aic controller) driver
++ *
++ *  Copyright 2014 Ingenic Semiconductor Co.,Ltd
++ *	cscheng <shicheng.cheng@ingenic.com>
++ *
++ *  This program is free software; you can redistribute  it and/or modify it
++ *  under  the terms of  the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the  License, or (at your
++ *  option) any later version.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/initval.h>
++#include <sound/soc.h>
++#include <sound/soc-dai.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <sound/dmaengine_pcm.h>
++#include "asoc-aic.h"
++#include "asoc-dma.h"
++
++#define I2S_CPM_VALID 0xb0000070
++static int ingenic_spdif_debug = 0;
++module_param(ingenic_spdif_debug, int, 0644);
++#define spdif_DEBUG_MSG(msg...)			\
++	do {					\
++		if (ingenic_spdif_debug)		\
++			printk("SPDIF: " msg);	\
++	} while(0)
++
++struct ingenic_spdif {
++	struct device *aic;
++	struct snd_dmaengine_dai_dma_data playback_dma_data;
++};
++
++struct clk {
++	const char *name;
++	unsigned long rate;
++	struct clk *parent;
++	unsigned long flags;
++	struct clk_ops *ops;
++	int count;
++	struct clk *source;
++};
++
++#define SPDIF_TFIFO_DEPTH 32
++#define INGENIC_SPDIF_FORMATS (SNDRV_PCM_FMTBIT_S24_LE|SNDRV_PCM_FMTBIT_S16_LE)
++#define INGENIC_SPDIF_RATE (SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_44100|SNDRV_PCM_RATE_48000|SNDRV_PCM_RATE_96000|SNDRV_PCM_RATE_192000)
++
++static void dump_registers(struct device *aic)
++{
++	struct ingenic_aic *ingenic_aic = dev_get_drvdata(aic);
++
++	pr_info("AIC_FR\t\t%p : 0x%08x\n", (ingenic_aic->vaddr_base+AICFR),ingenic_aic_read_reg(aic, AICFR));
++	pr_info("AIC_CR\t\t%p : 0x%08x\n", (ingenic_aic->vaddr_base+AICCR),ingenic_aic_read_reg(aic, AICCR));
++	pr_info("AIC_SPCTRL\t%p : 0x%08x\n",(ingenic_aic->vaddr_base+SPCTRL),ingenic_aic_read_reg(aic, SPCTRL));
++	pr_info("AIC_SR\t\t%p : 0x%08x\n", (ingenic_aic->vaddr_base+AICSR),ingenic_aic_read_reg(aic, AICSR));
++	pr_info("AIC_SPSTATE\t%p : 0x%08x\n",(ingenic_aic->vaddr_base+SPSTATE),ingenic_aic_read_reg(aic, SPSTATE));
++	pr_info("AIC_SPCFG1\t%p : 0x%08x\n",(ingenic_aic->vaddr_base+SPCFG1),ingenic_aic_read_reg(aic, SPCFG1));
++	pr_info("AIC_SPCFG2\t%p : 0x%08x\n",(ingenic_aic->vaddr_base+SPCFG2),ingenic_aic_read_reg(aic, SPCFG2));
++	return;
++}
++
++static int ingenic_spdif_startup(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct ingenic_spdif *ingenic_spdif = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_spdif->aic;
++	enum aic_mode work_mode = AIC_SPDIF_MODE;
++
++	spdif_DEBUG_MSG("enter %s, substream = %s\n",
++			__func__,
++			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture");
++	work_mode = aic_set_work_mode(aic, work_mode, true);
++	if (work_mode != AIC_SPDIF_MODE) {
++		dev_warn(ingenic_spdif->aic, "Aic now is working on %s mode, open spdif mode failed\n",
++				aic_work_mode_str(work_mode));
++		return -EPERM;
++	}
++	printk("start set AIC register....\n");
++	return 0;
++}
++
++static unsigned long  spdif_select_ori_sample_freq(struct device *aic,unsigned long sync)
++{
++	int div = 0;
++	switch(sync) {
++		case 8000: div = 0x6;
++			break;
++		case 11025: div = 0xa;
++			break;
++		case 16000: div = 0x8;
++			break;
++		case 22050: div = 0xb;
++			break;
++		case 24000: div = 0x9;
++			break;
++		case 32000: div = 0xc;
++			break;
++		case 44100: div = 0xf;
++			break;
++		case 48000: div = 0xd;
++			break;
++		case 96000: div = 0x5;
++			break;
++		case 192000: div = 0x1;
++			break;
++		default :
++			div = 0xf;
++			break;
++	}
++	__spdif_set_ori_sample_freq(aic,div);
++	return div;
++}
++
++static unsigned long  spdif_select_sample_freq(struct device* aic,unsigned long sync)
++{
++	int div = 0;
++	switch(sync) {
++		case 8000: div = 0x9;
++			break;
++		case 11025: div = 0x5;
++			break;
++		case 16000: div = 0x7;
++			break;
++		case 22050: div = 0x4;
++			break;
++		case 24000: div = 0x6;
++			break;
++		case 32000: div = 0x3;
++			break;
++		case 44100: div = 0x0;
++			break;
++		case 48000: div = 0x2;
++			break;
++		case 96000: div = 0xa;
++			break;
++		case 192000: div = 0xe;
++			break;
++		default :
++			div = 0;
++			break;
++	}
++	__spdif_set_sample_freq(aic,div);
++	return div;
++}
++static int ingenic_spdif_set_rate(struct device *aic ,struct ingenic_aic* ingenic_aic, unsigned long sample_rate){
++	struct clk* cgu_aic_clk = ingenic_aic->clk;
++
++	__i2s_stop_bitclk(aic);
++	clk_set_rate(cgu_aic_clk, sample_rate);
++	writel(0xa,(volatile void *)I2S_CPM_VALID);
++	__i2s_start_bitclk(aic);
++	spdif_select_ori_sample_freq(aic,sample_rate);
++	spdif_select_sample_freq(aic,sample_rate);
++
++	return sample_rate;
++}
++
++static int ingenic_spdif_hw_params(struct snd_pcm_substream *substream,
++							  struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
++{
++	int channels = params_channels(params);
++	int fmt_width = snd_pcm_format_width(params_format(params));
++	struct ingenic_spdif *ingenic_spdif = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_spdif->aic;
++	struct ingenic_aic *ingenic_aic = dev_get_drvdata(aic);
++	enum dma_slave_buswidth buswidth;
++	int trigger;
++	unsigned long sample_rate = params_rate(params);
++	unsigned long tmp_rate = 0;
++
++	spdif_DEBUG_MSG("enter %s, substream = %s\n", __func__,
++			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture");
++
++	if (!((1 << params_format(params)) & INGENIC_SPDIF_FORMATS) || channels > 2) {
++		dev_err(dai->dev, "hw params not inval channel %d params %x\n",
++				channels, params_format(params));
++		return -EINVAL;
++	}
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		__i2s_channel(aic, channels);
++		/* format */
++		if (fmt_width == 16){
++			buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
++			__spdif_set_max_wl(aic,0);
++			__spdif_set_sample_size(aic,1);
++		}else if(fmt_width == 24){
++			buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
++			__spdif_set_max_wl(aic,1);
++			__spdif_set_sample_size(aic,5);
++		}else{
++			return -EINVAL;
++		}
++
++		ingenic_spdif->playback_dma_data.addr_width = buswidth;
++		ingenic_spdif->playback_dma_data.maxburst = (SPDIF_TFIFO_DEPTH * buswidth)/2;
++		trigger = SPDIF_TFIFO_DEPTH - (ingenic_spdif->playback_dma_data.maxburst/(int)buswidth);
++//		__i2s_set_transmit_trigger(aic,trigger/2);
++		__spdif_set_trigger(aic, 3);
++//		snd_soc_dai_set_dma_data(dai, substream, (void *)&ingenic_spdif->playback_dma_data);
++
++	} else {
++		printk("spdif is not a capture device!\n");
++		return -EINVAL;
++	}
++
++	/* sample rate */
++	tmp_rate = ingenic_spdif_set_rate(aic,ingenic_aic,sample_rate);
++	if(tmp_rate < 0)
++		printk("set spdif clk failed!!\n");
++	/* signed transfer */
++	if(snd_pcm_format_signed(params_format(params)))
++		__spdif_clear_signn(aic);
++	else
++		__spdif_set_signn(aic);
++	return 0;
++}
++
++static int ingenic_spdif_start_substream(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct ingenic_spdif *ingenic_spdif = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_spdif->aic;
++	int rst_test = 0xfff;
++	spdif_DEBUG_MSG("enter %s, substream = %s\n",
++			__func__,
++			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture");
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		__spdif_reset(aic);
++		while(__spdif_get_reset(aic)) {
++			if (rst_test-- <= 0){
++				printk("spdif rst err\n");
++				return -EINVAL;
++			}
++		}
++		__spdif_enable_transmit_dma(aic);
++		__spdif_clear_underrun(aic);
++		__spdif_enable(aic);
++		__aic_enable(aic);
++	} else {
++		printk("spdif is not a capture device!\n");
++		return -EINVAL;
++	}
++	return 0;
++}
++
++static int ingenic_spdif_stop_substream(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct ingenic_spdif *ingenic_spdif = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_spdif->aic;
++	spdif_DEBUG_MSG("enter %s, substream = %s\n",
++			__func__,
++			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture");
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		if (ingenic_spdif_debug) __aic_dis_tur_int(aic);
++		if (__spdif_is_enable_transmit_dma(aic)) {
++			__spdif_disable_transmit_dma(aic);
++			__spdif_clear_underrun(aic);
++			/*hrtime mode: stop will be happen in any where, make sure there is
++			 *	no data transfer on ahb bus before stop dma
++			 */
++			while(!__spdif_test_underrun(aic));
++		}
++		__spdif_disable(aic);
++		__spdif_clear_underrun(aic);
++	} else {
++		printk("spdif is not a capture device!\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int ingenic_spdif_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
++{
++	struct ingenic_pcm_runtime_data *prtd = substream->runtime->private_data;
++	spdif_DEBUG_MSG("enter %s, substream = %s cmd = %d\n",
++		      __func__,
++		      (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture",
++		      cmd);
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		if (atomic_read(&prtd->wait_stopdma))
++			return -EPIPE;
++		if(ingenic_spdif_start_substream(substream, dai))
++			return -EINVAL;
++		break;
++	case SNDRV_PCM_TRIGGER_STOP:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++		if (atomic_read(&prtd->wait_stopdma))
++			return 0;
++		ingenic_spdif_stop_substream(substream, dai);
++		break;
++	}
++	/*dump_registers(aic);*/
++	return 0;
++}
++
++static void ingenic_spdif_shutdown(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai) {
++	struct ingenic_spdif *ingenic_spdif = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_spdif->aic;
++	enum aic_mode work_mode = AIC_SPDIF_MODE;
++
++	spdif_DEBUG_MSG("enter %s, substream = %s\n",
++			__func__,(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture");
++	work_mode = aic_set_work_mode(ingenic_spdif->aic, work_mode, false);
++	BUG_ON((work_mode != AIC_NO_MODE));
++	ingenic_spdif_stop_substream(substream, dai);
++	__aic_disable(aic);
++	return;
++}
++
++static int ingenic_spdif_probe(struct snd_soc_dai *dai)
++{
++	struct ingenic_spdif *ingenic_spdif = dev_get_drvdata(dai->dev);
++	struct device *aic = ingenic_spdif->aic;
++	unsigned int reg_tmp;
++	snd_soc_dai_init_dma_data(dai, &ingenic_spdif->playback_dma_data, NULL);
++
++	spdif_DEBUG_MSG("enter %s\n", __func__);
++
++
++	__i2s_disable_transmit_dma(aic);
++	__i2s_disable_receive_dma(aic);
++	__i2s_disable_replay(aic);
++	__i2s_disable_record(aic);
++	__i2s_disable_loopback(aic);
++	__aic_disable(aic);
++
++
++	reg_tmp = ingenic_aic_read_reg(aic, SPCTRL);
++	reg_tmp |= (SPCTRL_SPDIF_I2S_MASK | SPCTRL_M_TRIG_MASK |
++			SPCTRL_M_FFUR_MASK | SPCTRL_INVALID_MASK);
++	ingenic_aic_write_reg(aic, SPCTRL, reg_tmp);
++
++	__i2s_stop_bitclk(aic);
++	__i2s_external_codec(aic);
++	__i2s_bclk_output(aic);
++	__i2s_sync_output(aic);
++	__aic_select_i2s(aic);
++	__i2s_send_rfirst(aic);
++
++	__spdif_set_dtype(aic,0);
++	__spdif_set_ch1num(aic,0);
++	__spdif_set_ch2num(aic,1);
++	__spdif_set_srcnum(aic,0);
++
++	__interface_select_spdif(aic);
++	__spdif_play_lastsample(aic);
++	__spdif_init_set_low(aic);
++	__spdif_choose_consumer(aic);
++	__spdif_clear_audion(aic);
++	__spdif_set_copyn(aic);
++	__spdif_clear_pre(aic);
++	__spdif_choose_chmd(aic);
++	__spdif_set_category_code_normal(aic);
++	__spdif_set_clkacu(aic, 0);
++	__spdif_set_sample_size(aic, 1);
++	__spdif_set_valid(aic);
++	__spdif_mask_trig(aic);
++	__spdif_disable_underrun_intr(aic);
++	/*select spdif trans*/
++	printk("spdif cpu dai prob ok\n");
++
++	return 0;
++}
++
++
++static struct snd_soc_dai_ops ingenic_spdif_dai_ops = {
++	.startup = ingenic_spdif_startup,
++	.trigger 	= ingenic_spdif_trigger,
++	.hw_params 	= ingenic_spdif_hw_params,
++	.shutdown	= ingenic_spdif_shutdown,
++};
++
++#define ingenic_spdif_suspend NULL
++#define ingenic_spdif_resume	NULL
++static struct snd_soc_dai_driver ingenic_spdif_dai = {
++		.probe   = ingenic_spdif_probe,
++		.suspend = ingenic_spdif_suspend,
++		.resume  = ingenic_spdif_resume,
++		.playback = {
++			.channels_min = 1,
++			.channels_max = 2,
++			.rates = INGENIC_SPDIF_RATE,
++			.formats = INGENIC_SPDIF_FORMATS,
++		},
++		.ops = &ingenic_spdif_dai_ops,
++};
++
++static ssize_t ingenic_spdif_regs_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct ingenic_spdif *ingenic_spdif = dev_get_drvdata(dev);
++	dump_registers(ingenic_spdif->aic);
++	return 0;
++}
++
++static struct device_attribute ingenic_spdif_sysfs_attrs[] = {
++	__ATTR(spdif_regs, S_IRUGO, ingenic_spdif_regs_show, NULL),
++};
++
++static const struct snd_soc_component_driver ingenic_spdif_component = {
++	.name		= "aic-spdif",
++};
++
++static int ingenic_spdif_platfrom_probe(struct platform_device *pdev){
++//	struct ingenic_aic_subdev_pdata *pdata = dev_get_platdata(&pdev->dev);
++	struct device_node *parent = of_get_parent(pdev->dev.of_node);
++	struct resource res;
++	struct ingenic_spdif *ingenic_spdif;
++	int i = 0, ret;
++
++	if (!parent)
++		return -ENOMEM;
++	ret = of_address_to_resource(parent, 0, &res);
++	if (ret)
++		return ret;
++
++	ingenic_spdif = devm_kzalloc(&pdev->dev, sizeof(struct ingenic_spdif), GFP_KERNEL);
++	if (!ingenic_spdif)
++		return -ENOMEM;
++
++	ingenic_spdif->aic = pdev->dev.parent;
++
++	ingenic_spdif->playback_dma_data.addr = res.start + SPFIFO;
++	platform_set_drvdata(pdev, (void *)ingenic_spdif);
++
++	for (; i < ARRAY_SIZE(ingenic_spdif_sysfs_attrs); i++) {
++		ret = device_create_file(&pdev->dev, &ingenic_spdif_sysfs_attrs[i]);
++		if (ret)
++			dev_warn(&pdev->dev,"attribute %s create failed %x",
++					ingenic_spdif_sysfs_attrs[i].attr.name, ret);
++	}
++	ret = snd_soc_register_component(&pdev->dev, &ingenic_spdif_component,
++					 &ingenic_spdif_dai, 1);
++	if (!ret)
++		dev_dbg(&pdev->dev, "spdif platform probe success\n");
++	return ret;
++}
++
++static int ingenic_spdif_platfom_remove(struct platform_device *pdev)
++{
++	int i;
++	for (i = 0; i < ARRAY_SIZE(ingenic_spdif_sysfs_attrs); i++)
++		device_remove_file(&pdev->dev, &ingenic_spdif_sysfs_attrs[i]);
++	platform_set_drvdata(pdev, NULL);
++	snd_soc_unregister_component(&pdev->dev);
++	return 0;
++}
++static const struct of_device_id spdif_dt_match[] = {
++	{ .compatible = "ingenic,spdif", .data = NULL },
++	{},
++};
++MODULE_DEVICE_TABLE(of, spdif_dt_match);
++static struct platform_driver ingenic_spdif_plat_driver = {
++	.probe  = ingenic_spdif_platfrom_probe,
++	.remove = ingenic_spdif_platfom_remove,
++	.driver = {
++		.name = "ingenic-asoc-aic-spdif",
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(spdif_dt_match),
++	},
++};
++
++module_platform_driver(ingenic_spdif_plat_driver);
++MODULE_AUTHOR("shicheng.cheng <shicheng.cheng@ingenic.com>");
++MODULE_DESCRIPTION("INGENIC AIC SPDIF SoC Interface");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-aic-spdif");
+diff --git a/module_drivers/sound/soc/ingenic/as-v1/assert.h b/module_drivers/sound/soc/ingenic/as-v1/assert.h
+new file mode 100644
+index 000000000..131553ef6
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v1/assert.h
+@@ -0,0 +1,16 @@
++#ifndef _ASSERT_H_
++#define _ASSERT_H_
++
++#include <linux/kernel.h>
++
++void __assert(const char *expr, const char *file, unsigned int line, const char *func);
++
++#ifndef assert
++#define assert(_expr) \
++    do { \
++        if (!(_expr)) \
++            __assert(#_expr, __FILE__, __LINE__, __func__); \
++    } while (0)
++#endif
++
++#endif /* _ASSERT_H_ */
+diff --git a/module_drivers/sound/soc/ingenic/as-v2/Makefile b/module_drivers/sound/soc/ingenic/as-v2/Makefile
+new file mode 100644
+index 000000000..6cea581c3
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v2/Makefile
+@@ -0,0 +1,17 @@
++ccflags-$(CONFIG_SND_ASOC_INGENIC_DEBUG) += -DDEBUG
++ccflags-$(CONFIG_SND_ASOC_INGENIC_VERBOSE) += -DVERBOSE_DEBUG
++
++
++obj-$(CONFIG_SND_ASOC_INGENIC_AS_FE) += snd-asoc-as-fe.o
++snd-asoc-as-fe-objs 		:= as-dma.o as-dsp.o as-mixer.o as-fmtcov.o
++
++ingenic_baic-y := as-baic.o
++obj-$(CONFIG_SND_ASOC_INGENIC_AS_BAIC)  += ingenic_baic.o
++
++ingenic_spdif-y := as-spdif.o
++obj-$(CONFIG_SND_ASOC_INGENIC_AS_SPDIF) += ingenic_spdif.o
++
++ingenic_dmic-y := as-dmic.o
++obj-$(CONFIG_SND_ASOC_INGENIC_AS_DMIC) += ingenic_dmic.o
++
++obj-$(CONFIG_SND_ASOC_INGENIC_AS_VIR_FE) += as-vir-fe.o
+diff --git a/module_drivers/sound/soc/ingenic/as-v2/as-baic.c b/module_drivers/sound/soc/ingenic/as-v2/as-baic.c
+new file mode 100644
+index 000000000..57c7a71db
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v2/as-baic.c
+@@ -0,0 +1,919 @@
++/*
++ * ALSA Soc Audio Layer -- ingenic as(audio system) baic(Basic Audio Inter-
++ * face Controller) driver
++ *
++ * Copyright 2017 - 2022 Ingenic Semiconductor Co.,Ltd
++ *   cli <chen.li@ingenic.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/initval.h>
++#include <sound/soc.h>
++#include <sound/soc-dai.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++#include <linux/types.h>
++#include <linux/clk.h>
++#include "as-baic.h"
++
++#ifdef DEBUG
++static int ingenic_baic_debug = 1;
++#else
++static int ingenic_baic_debug = 0;
++#endif
++module_param(ingenic_baic_debug, int, 0644);
++#define BAIC_DEBUG_MSG(msg...)					\
++	do {										\
++		if (ingenic_baic_debug)					\
++			printk(KERN_DEBUG"BAIC: " msg);				\
++	} while(0)
++
++static int ingenic_baic_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
++{
++	struct ingenic_baic *baic = dev_get_drvdata(dai->dev);
++	struct ingenic_baic_dai *idai = &baic->dai[dai->driver->id];
++	int id  = idai->id;
++	u32 baic_cfg = 0;
++	u16 select_mode = 0;
++	bool frame_master = false;
++
++	BAIC_DEBUG_MSG("enter [BAIC%d] %s dai fmt %x\n", id, __func__, fmt);
++
++	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++	case SND_SOC_DAIFMT_NB_NF:
++		break;
++	case SND_SOC_DAIFMT_NB_IF:
++		baic_cfg |= BAICCFG_ISYNC;
++		break;
++	case SND_SOC_DAIFMT_IB_NF:
++		baic_cfg |= BAICCFG_NEG;
++		break;
++	case SND_SOC_DAIFMT_IB_IF:
++		baic_cfg |= BAICCFG_ISYNC | BAICCFG_NEG;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_I2S:		/*i2s format*/
++		if (!(idai->support_mode & BAIC_DAIFMT_I2S_GRP))
++			return -EINVAL;
++		baic_cfg |= BAICCFG_MODE_I2S;
++		select_mode = BAIC_DAIFMT_I2S_GRP|BAIC_DAIFMT_I2S;
++		break;
++	case SND_SOC_DAIFMT_MSB:		/*msb/left_j format*/
++		if (!(idai->support_mode & BAIC_DAIFMT_I2S_GRP))
++			return -EINVAL;
++		baic_cfg |= BAICCFG_MODE_LEFTJ;
++		select_mode = BAIC_DAIFMT_I2S_GRP|BAIC_DAIFMT_LEFTJ;
++		break;
++	case SND_SOC_DAIFMT_LSB:		/*lsb/right_j format*/
++		if (!(idai->support_mode & BAIC_DAIFMT_I2S_GRP))
++			return -EINVAL;
++		baic_cfg |= BAICCFG_MODE_RIGHTJ;
++		select_mode = BAIC_DAIFMT_I2S_GRP|BAIC_DAIFMT_RIGHTJ;
++		break;
++	case SND_SOC_DAIFMT_DSP_A:		/*TDM/PCM/DSP A*/
++		if (!(idai->support_mode & BAIC_DAIFMT_DSP_GRP))
++			return -EINVAL;
++		if (!(idai->support_mode & BAIC_DAIFMT_MODEA))
++			return -EINVAL;
++
++		if ((idai->support_mode & BAIC_DAIFMT_TDM2) &&
++				(fmt & BAIC_DAIFMT_SEL_TDM2)) {
++			baic_cfg |= BAICCFG_MODE_TDM2A;
++			select_mode = BAIC_DAIFMT_TDM2|BAIC_DAIFMT_MODEA|BAIC_DAIFMT_DSP_GRP;
++			break;
++		}
++
++		if ((idai->support_mode & BAIC_DAIFMT_TDM1) &&
++				(fmt & BAIC_DAIFMT_SEL_TDM1)) {
++			baic_cfg |= BAICCFG_MODE_TDM1A;
++			select_mode = BAIC_DAIFMT_TDM1|BAIC_DAIFMT_MODEA|BAIC_DAIFMT_DSP_GRP;
++			break;
++		}
++
++		if ((idai->support_mode & BAIC_DAIFMT_DSP) &&
++				(fmt & BAIC_DAIFMT_SEL_DSP)) {
++			baic_cfg |= BAICCFG_MODE_DSPA;
++			select_mode = BAIC_DAIFMT_DSP|BAIC_DAIFMT_MODEA|BAIC_DAIFMT_DSP_GRP;
++			break;
++		}
++
++		if ((idai->support_mode & BAIC_DAIFMT_PCM) &&
++				(fmt & BAIC_DAIFMT_SEL_PCM)) {
++			baic_cfg |= BAICCFG_MODE_PCMA;
++			select_mode = BAIC_DAIFMT_PCM|BAIC_DAIFMT_MODEA|BAIC_DAIFMT_DSP_GRP;
++			break;
++		}
++		return -EINVAL;
++	case SND_SOC_DAIFMT_DSP_B:		/*TDM/PCM/DSP B*/
++		if (!(idai->support_mode & BAIC_DAIFMT_DSP_GRP))
++			return -EINVAL;
++
++		if (!(idai->support_mode & BAIC_DAIFMT_MODEB))
++			return -EINVAL;
++
++		if ((idai->support_mode & BAIC_DAIFMT_TDM2) &&
++				(fmt & BAIC_DAIFMT_SEL_TDM2)) {
++			baic_cfg |= BAICCFG_MODE_TDM2B;
++			select_mode = BAIC_DAIFMT_TDM2|BAIC_DAIFMT_MODEB|BAIC_DAIFMT_DSP_GRP;
++			break;
++		}
++
++		if ((idai->support_mode & BAIC_DAIFMT_TDM1) &&
++				(fmt & BAIC_DAIFMT_SEL_TDM1)) {
++			baic_cfg |= BAICCFG_MODE_TDM1B;
++			select_mode = BAIC_DAIFMT_TDM1|BAIC_DAIFMT_MODEB|BAIC_DAIFMT_DSP_GRP;
++			break;
++		}
++
++		if ((idai->support_mode & BAIC_DAIFMT_DSP) &&
++				(fmt & BAIC_DAIFMT_SEL_DSP)) {
++			baic_cfg |= BAICCFG_MODE_DSPB;
++			select_mode = BAIC_DAIFMT_DSP|BAIC_DAIFMT_MODEB|BAIC_DAIFMT_DSP_GRP;
++			break;
++		}
++
++		if ((idai->support_mode & BAIC_DAIFMT_PCM) &&
++				(fmt & BAIC_DAIFMT_SEL_PCM)) {
++			baic_cfg |= BAICCFG_MODE_PCMB;
++			select_mode = BAIC_DAIFMT_PCM|BAIC_DAIFMT_MODEB|BAIC_DAIFMT_DSP_GRP;
++			break;
++		}
++	default:
++		pr_err("%s:%d\n", __func__, __LINE__);
++		return -EINVAL;
++	}
++
++	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++	case SND_SOC_DAIFMT_CBM_CFM:
++		break;
++	case SND_SOC_DAIFMT_CBS_CFS:	/*codec frame slave */
++		baic_cfg |= BAICCFG_MASTER;
++		frame_master = true;
++		break;
++	default:
++		pr_err("%s:%d\n", __func__, __LINE__);
++		return -EINVAL;
++	}
++
++	if (fmt & BAIC_DAIFMT_R) {
++		idai->baic_rcfg = baic_cfg;
++		idai->select_rmode = select_mode;
++		idai->frame_rmaster = frame_master;
++	} else if (fmt & BAIC_DAIFMT_T) {
++		idai->baic_tcfg = baic_cfg;
++		idai->select_tmode = select_mode;
++		idai->frame_tmaster = frame_master;
++	} else {
++		idai->baic_rcfg = baic_cfg;
++		idai->baic_tcfg = baic_cfg;
++		idai->select_rmode = select_mode;
++		idai->select_tmode = select_mode;
++		idai->frame_tmaster = frame_master;
++		idai->frame_rmaster = frame_master;
++	}
++
++	return 0;
++}
++
++static int ingenic_baic_set_tdm_slot(struct snd_soc_dai *dai,
++		unsigned int tx_mask, unsigned int rx_mask,
++		int slots, int slot_width)
++{
++	struct ingenic_baic *baic = dev_get_drvdata(dai->dev);
++	struct ingenic_baic_dai *idai = &baic->dai[dai->driver->id];
++	int baic_cfg = 0, baic_msk = 0;
++
++	if (!slots)
++		return 0;
++	if (!(idai->support_mode & (BAIC_DAIFMT_TDM2|BAIC_DAIFMT_TDM1|BAIC_DAIFMT_DSP|BAIC_DAIFMT_PCM)))
++		goto error;
++	if (!(idai->select_tmode & (BAIC_DAIFMT_TDM2|BAIC_DAIFMT_TDM1|BAIC_DAIFMT_DSP|BAIC_DAIFMT_PCM)) && tx_mask)
++		goto error;
++	if (!(idai->select_rmode & (BAIC_DAIFMT_TDM2|BAIC_DAIFMT_TDM1|BAIC_DAIFMT_DSP|BAIC_DAIFMT_PCM)) && rx_mask)
++		goto error;
++
++	baic_cfg = BAICCFG_SLOT(slots)|BAICCFG_SLS(slot_width);
++	baic_msk = BAICCFG_SLOT_MSK|BAICCFG_SLS_MSK;
++
++	if (tx_mask) {
++		idai->baic_tcfg &= ~baic_msk;
++		idai->baic_tcfg |= baic_cfg;
++	}
++	if (rx_mask) {
++		idai->baic_rcfg &= ~baic_msk;
++		idai->baic_rcfg |= baic_cfg;
++	}
++	return 0;
++error:
++	pr_err("%s:%d\n", __func__, __LINE__);
++	return -EINVAL;
++}
++
++static int ingenic_baic_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
++{
++	struct ingenic_baic *baic = dev_get_drvdata(dai->dev);
++	struct ingenic_baic_dai *idai = &baic->dai[dai->driver->id];
++	struct ingenic_baic_div *idiv = (div_id & DIVID_DIR_T) ? &idai->tdiv.v : &idai->rdiv.v;
++	u16 select_mode = (div_id & DIVID_DIR_T) ? idai->select_tmode : idai->select_rmode;
++	u16 *bclk_ratio = (div_id & DIVID_DIR_T) ? &idai->bclk_tratio : &idai->bclk_rratio;
++	bool frame_master = (div_id & DIVID_DIR_T) ? idai->frame_tmaster : idai->frame_rmaster;
++
++	if (!frame_master)
++		return 0;
++
++	switch (div_id & DIVID_MSK) {
++	case DIVID_SYNC_W:
++		idiv->synl = (BAICDIV_SYNL(div) >> BAICDIV_SYNL_SFT);
++		break;
++	case DIVID_BCLK:
++		idiv->bclkdiv = (BAICDIV_BCLKDIV(div) >> BAICDIV_BCLKDIV_SFT);
++		break;
++	case DIVID_SYNC:
++		if (select_mode & BAIC_DAIFMT_I2S_GRP)
++			idiv->sync_div = BAICDIV_SYNLDIV_I2S(div) >> BAICDIV_SYNLDIV_SFT;
++		else
++			idiv->sync_div = BAICDIV_SYNLDIV_DSP(div) >> BAICDIV_SYNLDIV_SFT;
++		*bclk_ratio = div;
++		break;
++	default:
++		pr_err("%s:%d\n", __func__, __LINE__);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int ingenic_baic_set_sysclk(struct snd_soc_dai *dai, int clk_id,
++		unsigned int freq, int dir)
++{
++	struct ingenic_baic *baic = dev_get_drvdata(dai->dev);
++	struct ingenic_baic_dai *idai = &baic->dai[dai->driver->id];
++	int id  = idai->id;
++	struct clk *clk_r = NULL, *clk_t = NULL;
++
++	BAIC_DEBUG_MSG("enter [BAIC%d] %s clk_id %d req %d clk dir %d\n", id, __func__,
++			clk_id, freq, dir);
++	switch (clk_id) {
++	case CLKID_SYSCLK:
++		if(!idai->clk_r || !idai->clk_t) {
++			pr_err("baic clk set rate err!\n");
++			return -EINVAL;
++		}
++		clk_r = idai->clk_r;
++		clk_t = idai->clk_t;
++		break;
++	case CLKID_SYSCLK_R:
++		if(!idai->clk_r) {
++			pr_err("baic clk set rate err!\n");
++			return -EINVAL;
++		}
++		clk_r = idai->clk_r;
++		break;
++	case CLKID_SYSCLK_T:
++		if(!idai->clk_t) {
++			pr_err("baic clk set rate err!\n");
++			return -EINVAL;
++		}
++		clk_t = idai->clk_t;
++		break;
++	default:
++		pr_err("%s:%d\n", __func__, __LINE__);
++		return -EINVAL;
++	}
++
++	regmap_write(baic->regmap, BAICTLCR(id),
++			idai->clk_split ? BAICTLCR_CLK_SPLIT_EN : 0);
++
++	if(clk_r && (clk_get_rate(clk_r) != freq)) {
++		clk_set_rate(clk_r, freq);
++		idai->rsysclk = clk_get_rate(clk_r);
++	}
++	if(clk_t && (clk_get_rate(clk_t) != freq)) {
++		clk_set_rate(clk_t, freq);
++		idai->tsysclk = clk_get_rate(clk_t);
++	}
++
++	return 0;
++}
++
++static bool ingenic_baic_fmt_check(u16 select_mode, int stream,
++		int fmt_width, int channels, int pin_num)
++{
++	if (select_mode & BAIC_DAIFMT_I2S_GRP) {
++		if (channels != 1 && ((pin_num * 2) % channels))
++			return false;
++//		if (channels == 1 && stream == SNDRV_PCM_STREAM_CAPTURE)
++//			return false;
++		return true;
++	}
++	if (!(select_mode & BAIC_DAIFMT_DSP_GRP))
++		return false;
++
++
++	if (select_mode & BAIC_DAIFMT_TDM1) {
++		if (channels > 8 || (channels != 1 && (channels % 2)))
++			return false;
++		if (fmt_width % 8)
++			return false;
++		return true;
++	}
++
++	if (select_mode & BAIC_DAIFMT_TDM2) {
++		if (channels != 8)
++			return false;
++		if (fmt_width % 8)
++			return false;
++		return true;
++	}
++
++
++	if (select_mode & BAIC_DAIFMT_PCM) {
++		if (channels != 1)
++			return false;
++		switch (fmt_width) {
++		case 8: case 16: case 32: return true;
++		default:
++			return false;
++		}
++	}
++
++	if (select_mode & BAIC_DAIFMT_DSP) {
++		if (channels != 1 && channels != 2)
++			return false;
++		switch (fmt_width) {
++		case 8: case 16: case 32: return true;
++		default:
++			return false;
++		}
++	}
++	return false;
++}
++
++static int ingenic_baic_hw_params(struct snd_pcm_substream *substream,
++				struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
++{
++	int channels = params_channels(params);
++	int rate = params_rate(params);
++	int fmt_width = snd_pcm_format_width(params_format(params));
++	struct ingenic_baic *baic = dev_get_drvdata(dai->dev);
++	struct ingenic_baic_dai *idai = &baic->dai[dai->driver->id];
++	int id  = idai->id;
++	unsigned int divreg = BAICTDIV(id);
++	bool is_out = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? true : false;
++	struct ingenic_baic_div *idiv = is_out ? &idai->tdiv.v : &idai->rdiv.v;
++	u32 *baic_cfg = is_out ? &idai->baic_tcfg : &idai->baic_rcfg;
++	u16 select_mode = is_out ? idai->select_tmode : idai->select_rmode;
++	u16 bclk_ratio = is_out ? idai->bclk_tratio : idai->bclk_rratio;
++	u32 sysclk = is_out ? idai->tsysclk : idai->rsysclk;
++	bool frame_master = is_out ? idai->frame_tmaster : idai->frame_rmaster;
++
++	BAIC_DEBUG_MSG("enter [BAIC%d] %s, substream = %s, channels %d, rate %d, fmt_width %d\n",
++			id, __func__, (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture",
++			channels, rate, fmt_width);
++
++	if (!ingenic_baic_fmt_check(select_mode, substream->stream,
++				fmt_width, channels, idai->data_pin_num))
++		return -EINVAL;
++
++	if ((select_mode & BAIC_DAIFMT_I2S_GRP)) {
++		(*baic_cfg) &= ~BAICCFG_CHANNEL_MSK;
++		(*baic_cfg) |= BAICCFG_CHANNEL(channels);
++	} else if (select_mode & BAIC_DAIFMT_TDM2) {
++		(*baic_cfg) &= ~BAICCFG_CHANNEL_MSK;
++		(*baic_cfg) |= BAICCFG_CHANNEL(4);
++	}
++	(*baic_cfg) &= ~BAICCFG_SS_MSK;
++	(*baic_cfg) |= BAICCFG_SS(fmt_width);
++
++	if (idai->clk_split && !is_out) {
++		divreg = BAICRDIV(id);
++	}
++
++	if (!frame_master)
++		return 0;
++
++	if (!idiv->bclkdiv) {
++		int bclk, div;
++		bclk = rate * bclk_ratio;
++		div = ((sysclk + bclk - 1) / bclk) & (~0x1UL);
++		idiv->bclkdiv =  BAICDIV_BCLKDIV(div) >> BAICDIV_BCLKDIV_SFT;
++	}
++	regmap_write(baic->regmap, divreg, is_out ? idai->tdiv.r: idai->rdiv.r);
++
++	return 0;
++}
++
++void ingenic_baic_dump(struct snd_soc_dai *dai)
++{
++	struct ingenic_baic *baic = dev_get_drvdata(dai->dev);
++	struct ingenic_baic_dai *idai = &baic->dai[dai->driver->id];
++	int id  = idai->id;
++	unsigned int val;
++	printk("==>BAIC\n");
++	regmap_read(baic->regmap, BAICRCTL(id), &val);
++	printk("BAICRCTL\t\t%x : 0x%08x\n",BAICRCTL(id), val);
++	regmap_read(baic->regmap, BAICRCFG(id), &val);
++	printk("BAICRCFG\t\t%x : 0x%08x\n",BAICRCFG(id), val);
++	regmap_read(baic->regmap, BAICRDIV(id), &val);
++	printk("BAICRDIV\t\t%x : 0x%08x\n",BAICRDIV(id), val);
++	regmap_read(baic->regmap, BAICRCGR(id), &val);
++	printk("BAICRCGR\t\t%x : 0x%08x\n",BAICRCGR(id), val);
++	printk("\n");
++	regmap_read(baic->regmap, BAICTCTL(id), &val);
++	printk("BAICTCTL\t\t%x : 0x%08x\n",BAICTCTL(id), val);
++	regmap_read(baic->regmap, BAICTCFG(id), &val);
++	printk("BAICTCFG\t\t%x : 0x%08x\n",BAICTCFG(id), val);
++	regmap_read(baic->regmap, BAICTDIV(id), &val);
++	printk("BAICTDIV\t\t%x : 0x%08x\n",BAICTDIV(id), val);
++	regmap_read(baic->regmap, BAICTCGR(id), &val);
++	printk("BAICTCGR\t\t%x : 0x%08x\n",BAICTCGR(id), val);
++	printk("\n");
++	regmap_read(baic->regmap, BAICTLCR(id), &val);
++	printk("BAICTLCR\t\t%x : 0x%08x\n",BAICTLCR(id), val);
++	regmap_read(baic->regmap, BAICCCR(id), &val);
++	printk("BAICCCR \t\t%x : 0x%08x\n", BAICCCR(id), val);
++
++	printk("==>GGU CLK\n");
++	printk("I2S0 : 0x%08x\n", *(volatile unsigned int *)(0xb0000060));
++	printk("I2S1 : 0x%08x\n", *(volatile unsigned int *)(0xb000007c));
++	printk("I2S2 : 0x%08x\n", *(volatile unsigned int *)(0xb0000084));
++	printk("I2S3 : 0x%08x\n", *(volatile unsigned int *)(0xb000008c));
++}
++
++static int ingenic_baic_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
++{
++	struct ingenic_baic *baic = dev_get_drvdata(dai->dev);
++	struct ingenic_baic_dai *idai = &baic->dai[dai->driver->id];
++	int id  = idai->id;
++	unsigned int baic_ccr_val = 0;
++	unsigned int  cfgreg;
++
++	BAIC_DEBUG_MSG("enter [BAIC%d] %s, substream = %s cmd = %d\n",  id, __func__,
++			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture",
++			cmd);
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:
++		BAIC_DEBUG_MSG("baic start\n");
++		spin_lock(&idai->lock);
++
++		/* NO clk_split :Receiver shared Transmitter's registers. */
++		if(!idai->clk_split)
++			regmap_read(baic->regmap, BAICCCR(id), &baic_ccr_val);
++
++		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++			cfgreg = BAICTCFG(id);
++			regmap_write(baic->regmap, cfgreg, idai->baic_tcfg);
++			/* Reset */
++			if(!(!idai->clk_split && (baic_ccr_val & BAICCCR_REN)))
++				regmap_write(baic->regmap, BAICTCTL(id), BAICCTR_RST);
++
++			/* Transmitter enable */
++			regmap_update_bits(baic->regmap, BAICCCR(id), BAICCCR_TEN, BAICCCR_TEN);
++		} else {
++			/* Reset */
++			if (!idai->clk_split) {
++				cfgreg = BAICTCFG(id);
++				if (!(baic_ccr_val & BAICCCR_TEN))
++					regmap_write(baic->regmap, BAICTCTL(id), BAICCTR_RST);
++			} else {
++				cfgreg = BAICRCFG(id);
++			}
++			regmap_write(baic->regmap, cfgreg, idai->baic_rcfg);
++			regmap_write(baic->regmap, BAICRCTL(id), BAICCTR_RST);
++
++			/* Receiver enable */
++			regmap_update_bits(baic->regmap, BAICCCR(id), BAICCCR_REN, BAICCCR_REN);
++		}
++		spin_unlock(&idai->lock);
++		break;
++	case SNDRV_PCM_TRIGGER_STOP:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++		BAIC_DEBUG_MSG("baic stop\n");
++		spin_lock(&idai->lock);
++
++		/* NO clk_split :Receiver shared Transmitter's registers. */
++		if(!idai->clk_split)
++			regmap_read(baic->regmap, BAICCCR(id), &baic_ccr_val);
++
++		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++			/* Transmitter disable */
++			regmap_update_bits(baic->regmap, BAICCCR(id), BAICCCR_TEN, 0);
++
++			/* Close clk */
++			if (!(!idai->clk_split && (baic_ccr_val & BAICCCR_REN)))
++					regmap_update_bits(baic->regmap, BAICTCFG(id), BAICCFG_MASTER, 0);
++		} else {
++			/* Receiver disable */
++			regmap_update_bits(baic->regmap, BAICCCR(id), BAICCCR_REN, 0);
++
++			/* Close clk */
++			if (!idai->clk_split) {
++				if (!(baic_ccr_val & BAICCCR_TEN))
++					regmap_update_bits(baic->regmap, BAICTCFG(id), BAICCFG_MASTER, 0);
++			} else {
++				regmap_update_bits(baic->regmap, BAICRCFG(id), BAICCFG_MASTER, 0);
++			}
++		}
++		spin_unlock(&idai->lock);
++		break;
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++		BAIC_DEBUG_MSG("baic pause\n");
++		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++			/*regmap_update_bits(baic->regmap, BAICTCFG(id), BAICCFG_T_PAUSE, BAICCFG_T_PAUSE); */
++			regmap_update_bits(baic->regmap, BAICCCR(id), BAICCCR_TEN, 0);
++		}
++		break;
++	}
++	return 0;
++}
++
++static int ingenic_baic_set_startup(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct ingenic_baic *baic = dev_get_drvdata(dai->dev);
++	struct ingenic_baic_dai *idai = &baic->dai[dai->driver->id];
++
++	mutex_lock(&idai->clk_lock);
++	if (snd_soc_dai_active(dai)) {
++		mutex_unlock(&idai->clk_lock);
++		return 0;
++	}
++	clk_prepare_enable(idai->clk_gate);
++	idai->clk_gate_en = true;
++	mutex_unlock(&idai->clk_lock);
++
++	return 0;
++}
++
++static void ingenic_baic_set_shutdown(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai) {
++	struct ingenic_baic *baic = dev_get_drvdata(dai->dev);
++	struct ingenic_baic_dai *idai = &baic->dai[dai->driver->id];
++
++	mutex_lock(&idai->clk_lock);
++	if (snd_soc_dai_active(dai)) {
++		mutex_unlock(&idai->clk_lock);
++		return;
++	}
++	clk_disable_unprepare(idai->clk_gate);
++	idai->clk_gate_en = false;
++	mutex_unlock(&idai->clk_lock);
++}
++
++static struct snd_soc_dai_ops ingenic_baic_dai_ops = {
++	.trigger 	= ingenic_baic_trigger,
++	.hw_params 	= ingenic_baic_hw_params,
++	.set_fmt	= ingenic_baic_set_dai_fmt,
++	.set_sysclk	= ingenic_baic_set_sysclk,
++	.set_clkdiv	= ingenic_baic_set_clkdiv,
++	.set_tdm_slot	= ingenic_baic_set_tdm_slot,
++	.startup	= ingenic_baic_set_startup,
++	.shutdown	= ingenic_baic_set_shutdown,
++};
++
++static const struct snd_soc_component_driver ingenic_baic_component = {
++	.name		= "aic-baic",
++};
++
++#define INGENIC_BAIC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | \
++		SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \
++		SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE | \
++		SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE | \
++		SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE | \
++		SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE | \
++		SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE)
++
++static char *dai_name[] = {
++	"BAIC0",
++	"BAIC1",
++	"BAIC2",
++	"BAIC3",
++	"BAIC4",
++};
++
++static char *pname[] = {
++	"BAIC0 playback",
++	"BAIC1 playback",
++	"BAIC2 playback",
++	"BAIC3 playback",
++	"BAIC4 playback",
++};
++
++static char *cname[] = {
++	"BAIC0 capture",
++	"BAIC1 capture",
++	"BAIC2 capture",
++	"BAIC3 capture",
++	"BAIC4 capture",
++};
++
++static bool ingenic_baic_vailed_reg(struct device *dev, unsigned int reg)
++{
++	if (unlikely(reg%BAICOFF > BAICMAX))
++		return false;
++	return true;
++}
++
++static void ingenic_baic_set_func(struct ingenic_baic *baic, int i)
++{
++	int id = baic->dai[i].id;
++	u16 mode = baic->dai[i].support_mode;
++
++	if (mode & BAIC_NO_REPLAY) {
++		baic->dai_driver[i].capture.stream_name = cname[id];
++		baic->dai_driver[i].capture.channels_min = 1;
++		baic->dai_driver[i].capture.channels_max = 12;
++	} else if (mode & BAIC_NO_RECORD) {
++		baic->dai_driver[i].playback.stream_name = pname[id];
++		baic->dai_driver[i].playback.channels_min = 1;
++		baic->dai_driver[i].playback.channels_max = 8;
++	} else {
++		baic->dai_driver[i].capture.stream_name = cname[id];
++		baic->dai_driver[i].capture.channels_min = 1;
++		baic->dai_driver[i].capture.channels_max = 12;
++		baic->dai_driver[i].playback.stream_name = pname[id];
++		baic->dai_driver[i].playback.channels_min = 1;
++		baic->dai_driver[i].playback.channels_max = 8;
++	}
++}
++
++const char *clk_gate_name[] = {
++	"gate_i2s0",
++	"gate_i2s1",
++	"gate_i2s2",
++	"gate_i2s3",
++	"gate_pcm",
++};
++
++static int ingenic_baic_set_clk_rate(struct ingenic_baic *baic, int i, unsigned long rate)
++{
++	int ret = 0;
++	int id = baic->dai[i].id;
++	const char *clk_name;
++
++	baic->dai[i].clk_gate = clk_get(baic->dev, clk_gate_name[id]);
++	if(IS_ERR_OR_NULL(baic->dai[i].clk_gate)) {
++		dev_err(baic->dev, "Failed to get clk_gate: %s\n", clk_gate_name[id]);
++		return -EINVAL;
++	}
++
++	clk_name = baic->dai[i].clk_rname;
++	if(strncmp(clk_name, "no_clk", 6)) {
++		baic->dai[i].clk_r = devm_clk_get(baic->dev, clk_name);
++		if(IS_ERR_OR_NULL(baic->dai[i].clk_r)) {
++			dev_err(baic->dev, "Failed to get clk: %s\n", clk_name);
++			ret = -EINVAL;
++			goto err_clk_r;
++		}
++		clk_set_rate(baic->dai[i].clk_r, rate);
++		clk_prepare_enable(baic->dai[i].clk_r);
++		baic->dai[i].rsysclk = rate;
++	}
++	clk_name = baic->dai[i].clk_tname;
++	if(strncmp(clk_name, "no_clk", 6)) {
++		baic->dai[i].clk_t = devm_clk_get(baic->dev, clk_name);
++		if(IS_ERR_OR_NULL(baic->dai[i].clk_t)) {
++			dev_err(baic->dev, "Failed to get clk: %s\n", clk_name);
++			ret = -EINVAL;
++			goto err_clk_t;
++		}
++
++		if(id == 4) {
++			const char *parent_name;
++			struct clk *parent;
++			of_property_read_string(baic->dev->of_node, "ingenic,pcm-clk-parent", &parent_name);
++			parent = devm_clk_get(baic->dev, parent_name);
++			clk_set_parent(baic->dai[i].clk_t, parent);
++			devm_clk_put(baic->dev, parent);
++		}
++
++		clk_set_rate(baic->dai[i].clk_t, rate);
++		clk_prepare_enable(baic->dai[i].clk_t);
++		baic->dai[i].tsysclk = rate;
++	}
++
++	regmap_update_bits(baic->regmap, BAICTCFG(id), BAICCFG_MASTER, 0);
++	regmap_update_bits(baic->regmap, BAICRCFG(id), BAICCFG_MASTER, 0);
++
++
++	return ret;
++err_clk_t:
++	if(baic->dai[i].clk_r) {
++		devm_clk_put(baic->dev, baic->dai[i].clk_r);
++	}
++err_clk_r:
++	devm_clk_put(baic->dev, baic->dai[i].clk_gate);
++	return ret;
++}
++
++static int ingenic_baic_platform_probe(struct platform_device *pdev)
++{
++	struct ingenic_baic *baic;
++	struct resource *res;
++	int ret, i, id;
++	const __be32 *p;
++	struct property *prop;
++	u32 num_dais, tmp;
++	const char *clk_name;
++	char clk_ce_name[10];
++	struct clk *ce_clk;
++	struct regmap_config regmap_config = {
++		.reg_bits = 32,
++		.reg_stride = 4,
++		.val_bits = 32,
++		.writeable_reg = ingenic_baic_vailed_reg,
++		.readable_reg = ingenic_baic_vailed_reg,
++		.cache_type = REGCACHE_NONE,
++	};
++
++	if (of_property_read_u32(pdev->dev.of_node, "ingenic,num-dais", &num_dais))
++		num_dais = 1;
++
++	baic = devm_kzalloc(&pdev->dev, sizeof(*baic) +
++			num_dais * sizeof(struct ingenic_baic_dai) +
++			num_dais * sizeof(struct snd_soc_dai_driver), GFP_KERNEL);
++	if (!baic)
++		return -ENOMEM;
++
++	baic->dai = (struct ingenic_baic_dai *)(baic + 1);
++	baic->dai_driver = (struct snd_soc_dai_driver *)(baic->dai + num_dais);
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	baic->io_base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(baic->io_base))
++		return PTR_ERR(baic->io_base);
++	regmap_config.max_register = resource_size(res) - 0x4;
++	baic->regmap = devm_regmap_init_mmio(&pdev->dev,
++			baic->io_base,
++			&regmap_config);
++	if (IS_ERR(baic->regmap))
++		return PTR_ERR(baic->regmap);
++	baic->dev = &pdev->dev;
++	baic->num_dais = num_dais;
++
++	i = 0;
++	of_property_for_each_u32(pdev->dev.of_node, "ingenic,dai-array", prop, p, tmp) {
++		baic->dai[i++].id = (u16)tmp;
++		if (i >= num_dais)
++			break;
++	}
++
++
++	i = 0;
++	of_property_for_each_u32(pdev->dev.of_node, "ingenic,dai-mode", prop, p, tmp) {
++		baic->dai[i++].support_mode = (u16)tmp;
++		if (i >= num_dais)
++			break;
++	}
++
++	i = 0;
++	of_property_for_each_u32(pdev->dev.of_node, "ingenic,data-pin-num", prop, p, tmp) {
++		if ((u8)tmp <= 1)
++			baic->dai[i].support_mode &= ~BAIC_DAIFMT_TDM2;
++		baic->dai[i++].data_pin_num = (u8)tmp;
++		if (i >= num_dais)
++			break;
++	}
++
++	i = 0;
++	of_property_for_each_u32(pdev->dev.of_node, "ingenic,clk-split", prop, p, tmp) {
++		if(tmp)
++			baic->dai[i++].clk_split = true;
++		else
++			baic->dai[i++].clk_split = false;
++		if (i >= num_dais)
++			break;
++	}
++
++	i = 0;
++	of_property_for_each_string(pdev->dev.of_node, "ingenic,clk-rname", prop, clk_name) {
++		baic->dai[i++].clk_rname = clk_name;
++		if (i >= num_dais)
++			break;
++	}
++
++	i = 0;
++	of_property_for_each_string(pdev->dev.of_node, "ingenic,clk-tname", prop, clk_name) {
++		baic->dai[i++].clk_tname = clk_name;
++		if (i >= num_dais)
++			break;
++	}
++
++	for (i = 0; i < num_dais; i++) {
++		id = baic->dai[i].id;
++		baic->dai_driver[i].id = i;
++		baic->dai_driver[i].name = dai_name[id];
++		baic->dai_driver[i].ops = &ingenic_baic_dai_ops;
++		ingenic_baic_set_func(baic, i);
++		baic->dai_driver[i].symmetric_rates =  baic->dai[i].clk_split ? 0 : 1;
++		baic->dai_driver[i].symmetric_channels =  baic->dai[i].clk_split ? 0 : 1;
++		baic->dai_driver[i].symmetric_samplebits =  baic->dai[i].clk_split ? 0 : 1;
++
++		ingenic_baic_set_clk_rate(baic, i, 24000000);
++		spin_lock_init(&baic->dai[i].lock);
++		mutex_init(&baic->dai[i].clk_lock);
++	}
++
++	/* I2S clk enable */
++	for (i = 0; i < 4; i++) {
++		sprintf(clk_ce_name, "ce_i2s%d", i);
++
++		ce_clk = clk_get(baic->dev, clk_ce_name);
++		if(IS_ERR_OR_NULL(ce_clk)) {
++			dev_err(baic->dev, "Failed to get clk ce: %s\n", clk_ce_name);
++			return -EINVAL;
++		}
++
++		clk_prepare_enable(ce_clk);
++	}
++
++	platform_set_drvdata(pdev, (void *)baic);
++
++	ret = devm_snd_soc_register_component(&pdev->dev, &ingenic_baic_component,
++			baic->dai_driver, num_dais);
++	if (!ret)
++		dev_info(&pdev->dev, "baic platform probe success\n");
++
++	return ret;
++}
++
++static int ingenic_baic_platform_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id ingenic_baic_match_table[] = {
++	{ .compatible = "ingenic,as-baic", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, ingenic_baic_match_table);
++
++#ifdef CONFIG_PM
++static int ingenic_baic_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	struct ingenic_baic *baic = platform_get_drvdata(pdev);
++	struct ingenic_baic_dai *idai;
++	int i;
++
++	for(i = 0; i < baic->num_dais; i++) {
++		idai = &baic->dai[i];
++		mutex_lock(&idai->clk_lock);
++		if(idai->clk_gate_en) {
++			clk_disable_unprepare(idai->clk_gate);
++		}
++		mutex_unlock(&idai->clk_lock);
++	}
++	return 0;
++}
++
++static int ingenic_baic_resume(struct platform_device *pdev)
++{
++	struct ingenic_baic *baic = platform_get_drvdata(pdev);
++	struct ingenic_baic_dai *idai;
++	int i;
++
++	for(i = 0; i < baic->num_dais; i++) {
++		idai = &baic->dai[i];
++		mutex_lock(&idai->clk_lock);
++		if(idai->clk_gate_en) {
++			clk_prepare_enable(idai->clk_gate);
++		}
++		mutex_unlock(&idai->clk_lock);
++	}
++	return 0;
++}
++#endif
++
++static struct platform_driver ingenic_baic_platform_driver = {
++	.driver = {
++		.name = "as-baic",
++		.of_match_table = ingenic_baic_match_table,
++	},
++	.suspend = ingenic_baic_suspend,
++	.resume = ingenic_baic_resume,
++	.probe = ingenic_baic_platform_probe,
++	.remove = ingenic_baic_platform_remove,
++};
++module_platform_driver(ingenic_baic_platform_driver);
++
++MODULE_AUTHOR("cli <chen.li@ingenic.com>");
++MODULE_DESCRIPTION("Ingenic AS BAIC SoC Interface");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-as-baic");
+diff --git a/module_drivers/sound/soc/ingenic/as-v2/as-baic.h b/module_drivers/sound/soc/ingenic/as-v2/as-baic.h
+new file mode 100644
+index 000000000..7741bb3e1
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v2/as-baic.h
+@@ -0,0 +1,175 @@
++/*
++ * ALSA Soc Audio Layer -- Ingenic AS BAIC Controller
++ *
++ * Copyright 2017 - 2022 Ingenic Semiconductor Co.,Ltd
++ *     cli <chen.li@ingenic.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#ifndef __AS_BAIC_H__
++#define __AS_BAIC_H__
++
++#include <linux/bitops.h>
++#include <dt-bindings/sound/ingenic-baic.h>
++#define MAX_BAIC_NUM		(5)
++#define BAIC_SUPPORT_FORMAT_MAX	(11)
++/*CLKID*/
++#define CLKID_SYSCLK		0x1
++#define CLKID_SYSCLK_T		0x2
++#define CLKID_SYSCLK_R		0x3
++
++#define DIVID_DIR_T	BIT(0)
++#define DIVID_SFT	(1)
++#define DIVID_MSK	GENMASK(2, DIVID_SFT)
++#define DIVID_SYNC_W	(0x0 << DIVID_SFT)	/*divided by bclk*/
++#define	DIVID_SYNC	(0x1 << DIVID_SFT)	/*divided by bclk*/
++#define	DIVID_BCLK	(0x2 << DIVID_SFT)	/*divided by sysclk*/
++
++#define BAIC_DAIFMT_T		(0x1 << 16)
++#define BAIC_DAIFMT_R		(0x2 << 16)
++#define BAIC_DAIFMT_DIR_MSK	(0x3 << 16)
++
++#define BAIC_DAIFMT_SEL_PCM  (0x1 << 20)
++#define BAIC_DAIFMT_SEL_DSP  (0x2 << 20)
++#define BAIC_DAIFMT_SEL_TDM1 (0x3 << 20)
++#define BAIC_DAIFMT_SEL_TDM2 (0x4 << 20)
++#define BAIC_DAIFMT_SEL_MASK (0xf << 20)
++
++/*REGISTERS*/
++#define BAICRCTL0	(0x0)
++#define BAICRCFG0	(0x4)
++#define BAICRDIV0	(0x8)
++#define BAICRCGR0	(0xc)
++#define BAICTCTL0	(0x10)
++#define BAICTCFG0	(0x14)
++#define BAICTDIV0	(0x18)
++#define BAICTCGR0	(0x1c)
++#define BAICTLCR0	(0x20)
++#define BAICCCR0	(0x24)
++#define BAICMAX		BAICCCR0
++
++#define BAICOFF		(0x1000)
++#define BAICRCTL(n)	(BAICRCTL0 + BAICOFF * (n))	/*BAIC Receiver Control Register (BAICRCTL) description*/
++#define BAICRCFG(n)	(BAICRCFG0 + BAICOFF * (n))	/*BAIC Receiver Configuration Register (BAICRCFG) description*/
++#define BAICRDIV(n)	(BAICRDIV0 + BAICOFF * (n))	/*BAIC Receiver CLK divide register (BAICRDIV) description*/
++#define BAICRCGR(n)	(BAICRCGR0 + BAICOFF * (n))	/*BAIC Receiver CLK Gate Register (BAICRCGR) description(Unused)*/
++
++#define BAICTCTL(n)	(BAICTCTL0 + BAICOFF * (n))	/*BAIC Transmitter Control Register (BAICTCTL) description*/
++#define BAICTCFG(n)	(BAICTCFG0 + BAICOFF * (n))	/*BAIC Transmitter Configuration Register (BAICTCFG) description*/
++#define BAICTDIV(n)	(BAICTDIV0 + BAICOFF * (n))	/*BAIC Transmitter CLK divide register (BAICTDIV） description*/
++#define BAICTCGR(n)	(BAICTCGR0 + BAICOFF * (n))	/*BAIC Transmitter CLK Gate Register (BAICTCGR) description*/
++
++#define BAICTLCR(n)	(BAICTLCR0 + BAICOFF * (n))	/*BAIC Top Level Configure Register (BAICTLCR) description*/
++#define BAICCCR(n)	(BAICCCR0 + BAICOFF * (n))	/*BAIC Common Control Register (BAICCCR) description*/
++
++#define BAICCTR_RST	BIT(0)
++
++/*#define BAICCFG_T_PAUSE		BIT(31)*/
++#define BAICCFG_SLOT_SFT	(24)
++#define BAICCFG_SLOT_MSK	GENMASK(27, BAICCFG_SLOT_SFT)
++#define BAICCFG_SLOT(slot)	((((slot) - 1) << BAICCFG_SLOT_SFT) & BAICCFG_SLOT_MSK)
++#define BAICCFG_SWLR		BIT(20)
++#define BAICCFG_CHANNEL_SFT	(17)
++#define BAICCFG_CHANNEL_MSK	GENMASK(19, BAICCFG_CHANNEL_SFT)
++#define BAICCFG_CHANNEL(ch)	((((ch) >> 1) << BAICCFG_CHANNEL_SFT) & BAICCFG_CHANNEL_MSK)
++#define BAICCFG_SLS_SFT	(13)
++#define BAICCFG_SLS_MSK		GENMASK(14, BAICCFG_SLS_SFT)
++#define BAICCFG_SLS(sls)	(((sls%16) ? 0 : (((sls) >> 5) + 1) << BAICCFG_SLS_SFT) & BAICCFG_SLS_MSK)
++#define BAICCFG_ISYNC		BIT(12)
++#define BAICCFG_ASVTSU		BIT(11)
++#define BAICCFG_SS_SFT		(8)
++#define BAICCFG_SS_MSK		GENMASK(10, BAICCFG_SS_SFT)
++#define BAICCFG_SS_8		(0 << BAICCFG_SS_SFT)
++#define BAICCFG_SS_12		(1 << BAICCFG_SS_SFT)
++#define BAICCFG_SS_13		(2 << BAICCFG_SS_SFT)
++#define BAICCFG_SS_16		(3 << BAICCFG_SS_SFT)
++#define BAICCFG_SS_18		(4 << BAICCFG_SS_SFT)
++#define BAICCFG_SS_20		(5 << BAICCFG_SS_SFT)
++#define BAICCFG_SS_24		(6 << BAICCFG_SS_SFT)
++#define BAICCFG_SS_32		(7 << BAICCFG_SS_SFT)
++#define BAICCFG_SS(ss)		((ss <= 8) ? BAICCFG_SS_8 : (ss <= 12) ? BAICCFG_SS_12 : (ss == 13) ? BAICCFG_SS_13 : (ss <= 16) ? BAICCFG_SS_16 : (ss <= 18) ? BAICCFG_SS_18 : (ss <= 20) ? BAICCFG_SS_20 : (ss <= 24) ? BAICCFG_SS_24: BAICCFG_SS_32)
++#define BAICCFG_MODE_SFT	(2)
++#define BAICCFG_MODE_MSK	GENMASK(5, BAICCFG_MODE_SFT)
++#define BAICCFG_MODE_PCMA	(0 << BAICCFG_MODE_SFT)
++#define BAICCFG_MODE_PCMB	(1 << BAICCFG_MODE_SFT)
++#define BAICCFG_MODE_DSPA	(2 << BAICCFG_MODE_SFT)
++#define BAICCFG_MODE_DSPB	(3 << BAICCFG_MODE_SFT)
++#define BAICCFG_MODE_I2S	(4 << BAICCFG_MODE_SFT)
++#define BAICCFG_MODE_LEFTJ	(5 << BAICCFG_MODE_SFT)
++#define BAICCFG_MODE_RIGHTJ	(6 << BAICCFG_MODE_SFT)
++#define BAICCFG_MODE_TDM1A	(8 << BAICCFG_MODE_SFT)		/*one data pin*/
++#define BAICCFG_MODE_TDM1B	(9 << BAICCFG_MODE_SFT)
++#define BAICCFG_MODE_TDM2A	(10 << BAICCFG_MODE_SFT)		/*At most four data pin*/
++#define BAICCFG_MODE_TDM2B	(11 << BAICCFG_MODE_SFT)
++#define BAICCFG_NEG		BIT(1)		/*Use BCLK falling edge receive serial data Master mode*/
++#define BAICCFG_MASTER		BIT(0)
++
++#define BAICDIV_BCLKDIV_SFT	(16)		/*BCLK = SYS_CLK / BCLKDIV*/
++#define BAICDIV_BCLKDIV_MSK	GENMASK(23, BAICDIV_BCLKDIV_SFT)
++#define BAICDIV_BCLKDIV(div)	(((div) << BAICDIV_BCLKDIV_SFT) & BAICDIV_BCLKDIV_MSK)
++#define BAICDIV_SYNL_SFT	(8)		/*BAICSYN = ( SYNL + 1 ) * BCLK*/
++#define BAICDIV_SYNL_MSK	GENMASK(15, BAICDIV_SYNL_SFT)
++#define BAICDIV_SYNL(width)	((((width) - 1) << BAICDIV_SYNL_SFT) & BAICDIV_SYNL_MSK)
++#define BAICDIV_SYNLDIV_SFT	(0)		/*SYNC = BCLK/(8*(SYNCDIV+1))*/
++#define BAICDIV_SYNLDIV_MSK	GENMASK(7, BAICDIV_SYNLDIV_SFT)
++#define BAICDIV_SYNLDIV_I2S(div)   (((((div)/16) - 1) << BAICDIV_SYNLDIV_SFT) & BAICDIV_SYNLDIV_MSK)
++#define BAICDIV_SYNLDIV_DSP(div)   (((((div)/8) - 1) << BAICDIV_SYNLDIV_SFT) & BAICDIV_SYNLDIV_MSK)
++
++#define BAICTLCR_ICDC		BIT(1)
++#define BAICTLCR_CLK_SPLIT_EN	BIT(0)
++
++#define BAICCCR_TEN		BIT(3)
++#define BAICCCR_REN		BIT(2)
++
++/*struct*/
++struct ingenic_baic_div {
++	uint32_t sync_div:8;
++	uint32_t synl:8;
++	uint32_t bclkdiv:8;
++	uint32_t reserved24_31:8;
++} __attribute__ ((packed));
++
++struct ingenic_baic_dai {
++	u8 id;
++	u16 support_func;
++	u16 support_mode;
++	u8 data_pin_num;
++	bool clk_split;
++	bool frame_tmaster;
++	bool frame_rmaster;
++	u32 tsysclk;
++	u32 rsysclk;
++	u16 bclk_tratio;
++	u16 bclk_rratio;
++	u16 select_tmode;
++	u16 select_rmode;
++	u32 baic_tcfg;
++	u32 baic_rcfg;
++	union {
++		struct ingenic_baic_div v;
++		uint32_t r;
++	} rdiv, tdiv;
++
++	struct clk *clk_r;
++	const char *clk_rname;
++	struct clk *clk_t;
++	const char *clk_tname;
++	struct clk *clk_gate;
++	spinlock_t lock;
++	struct mutex clk_lock;
++	bool clk_gate_en;
++};
++
++struct ingenic_baic {
++	struct device *dev;	/*register access device*/
++	struct regmap *regmap;
++	void * __iomem io_base;
++	int num_dais;
++	struct snd_soc_dai_driver *dai_driver;
++	struct ingenic_baic_dai *dai;
++};
++
++#endif /*__AS_BAIC_H__*/
+diff --git a/module_drivers/sound/soc/ingenic/as-v2/as-dma.c b/module_drivers/sound/soc/ingenic/as-v2/as-dma.c
+new file mode 100644
+index 000000000..1848a4e47
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v2/as-dma.c
+@@ -0,0 +1,967 @@
++/*
++ * ALSA Soc Audio Layer -- ingenic as(audio system) dma driver
++ *
++ * Copyright 2017 - 2022 Ingenic Semiconductor Co.,Ltd
++ *     cli <chen.li@ingenic.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/list.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/vmalloc.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmapool.h>
++#include <linux/delay.h>
++#include <linux/lcm.h>
++#include <sound/soc.h>
++#include <linux/clk.h>
++#include <sound/pcm_params.h>
++#include "as-dma.h"
++
++
++/* normal */
++#ifndef CONFIG_SND_ASOC_INGENIC_SPDIF_DUMMY_TIMES
++#define CONFIG_SND_ASOC_INGENIC_SPDIF_DUMMY_TIMES (0) //ms
++#endif
++#ifndef CONFIG_SND_ASOC_INGENIC_PLAYBACK_DUMMY_TIMES
++#define CONFIG_SND_ASOC_INGENIC_PLAYBACK_DUMMY_TIMES (0) //ms
++#endif
++
++#ifdef DEBUG
++static int ingenic_dma_debug = 1;
++#else
++static int ingenic_dma_debug = 0;
++#endif
++
++#define GET_PHYADDR(a)  \
++({						\
++	unsigned int v;        \
++	if (unlikely((unsigned int)(a) & 0x40000000)) {    \
++	v = page_to_phys(vmalloc_to_page((const void *)(a))) | ((unsigned int)(a) & ~PAGE_MASK); \
++	} else     \
++	v = ((unsigned int)(a) & 0x1fffffff);                   \
++	v;                                             \
++ })
++
++module_param(ingenic_dma_debug, int, 0644);
++
++#define DMA_DEBUG_MSG(msg...)	\
++	do { \
++		if (ingenic_dma_debug)	\
++			printk(KERN_DEBUG"ADMA: " msg);	\
++	} while(0)
++
++#ifdef VERBOSE_DEBUG
++#define DMA_DEBUG_VERBOSE_MSG(msg...)	\
++	do {\
++		if (ingenic_dma_debug)	\
++			printk(KERN_DEBUG"ADMA: " msg);	\
++	} while(0)
++#else
++#define	DMA_DEBUG_VERBOSE_MSG(msg...) {}
++#endif
++
++int __attribute__((weak)) ingenic_as_fmtcov_cfg(struct snd_pcm_substream *substream,
++		struct snd_pcm_hw_params *params)
++{
++	return 0;
++}
++void __attribute__((weak)) ingenic_as_fmtcov_enable(u8 dai_id, bool enable){}
++
++static const struct snd_pcm_hardware ingenic_as_dma_pcm_hardware = {
++	.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
++			SNDRV_PCM_INFO_MMAP_VALID),
++	.buffer_bytes_max = INGENIC_DMA_BUFFERSIZE_MAX,
++	.period_bytes_min = INGENIC_PERIODS_BYTES_MIN,
++	.period_bytes_max = (INGENIC_DMA_BUFFERSIZE_MAX / INGENIC_PERIODS_MIN),
++	.periods_min = INGENIC_PERIODS_MIN,
++	.periods_max = (INGENIC_DMA_BUFFERSIZE_MAX/INGENIC_PERIODS_BYTES_MIN),
++	.fifo_size = 0,
++	.formats = ~0ULL,
++};
++
++static snd_pcm_uframes_t ingenic_as_dma_pointer(struct snd_soc_component *component, struct snd_pcm_substream *substream)
++{
++	struct ingenic_as_dma_runtime *prtd = substream_to_prtd(substream);
++	struct ingenic_as_dma *as_dma = prtd->as_dma;
++	dma_addr_t now;
++	ssize_t pos;
++
++	if (likely(substream->runtime && substream->runtime->dma_addr)) {
++//		now = readl_relaxed(as_dma->dma_base + DBA(prtd->dai_id));
++		now = prtd->hw_ptr;
++		if (now)
++			pos = (ssize_t)(now - substream->runtime->dma_addr);
++		else
++			pos = 0;
++	} else {
++		WARN("%s: %s has no runtime\n", substream->name);
++		pos = 0;
++	}
++	DMA_DEBUG_VERBOSE_MSG("enter %s[dai%d substream = %s] pos = %x(%d)(now %x dma %x)\n",
++			__func__, prtd->dai_id,
++			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
++			"playback" : "capture",
++			pos, pos, now, substream->runtime->dma_addr);
++	if (pos >= snd_pcm_lib_buffer_bytes(substream))
++		pos = 0;
++	return bytes_to_frames(substream->runtime, pos);
++}
++
++static int ingenic_as_dma_period_bytes_quirk(struct snd_pcm_hw_params *params,
++		struct snd_pcm_hw_rule *rule)
++{
++	struct snd_interval *iperiod_bytes = hw_param_interval(params,
++			SNDRV_PCM_HW_PARAM_PERIOD_BYTES);
++	struct snd_interval *iframe_bits = hw_param_interval(params,
++			SNDRV_PCM_HW_PARAM_FRAME_BITS);
++	int align_bytes = DCM_TSZ_MAX_WORD << 2;
++	int min_frame_bytes = iframe_bits->min >> 3;
++	int max_frame_bytes = iframe_bits->max >> 3;
++	int min_period_bytes = iperiod_bytes->min;
++	int max_period_bytes = iperiod_bytes->max;
++	int min_align_bytes, max_align_bytes;
++	struct snd_interval nperiod_bytes;
++
++	snd_interval_any(&nperiod_bytes);
++	min_align_bytes = lcm(align_bytes, min_frame_bytes);
++	min_period_bytes = (min_period_bytes + min_align_bytes - 1) / min_align_bytes;
++	nperiod_bytes.min = min_period_bytes * min_align_bytes;
++
++	max_align_bytes = lcm(align_bytes, max_frame_bytes);
++	max_period_bytes = max_period_bytes / max_align_bytes;
++	nperiod_bytes.max = max_period_bytes * max_align_bytes;
++
++	DMA_DEBUG_MSG("==> %s %d : align_bytes = %d \n\
++			frame_bytes.min (%d)\t\tframe_bytes.max (%d) \n\
++			period_bytes.min  [%d]\tperiod_bytes.max  [%d] \n\
++			nperiod_bytes.min [%d]\tnperiod_bytes.max [%d]\n",
++			__func__, __LINE__, align_bytes,
++			min_frame_bytes, max_frame_bytes, iperiod_bytes->min,
++			iperiod_bytes->max, nperiod_bytes.min, nperiod_bytes.max);
++	return snd_interval_refine(iperiod_bytes, &nperiod_bytes);
++}
++
++static int ingenic_as_dma_open(struct snd_soc_component *component, struct snd_pcm_substream *substream)
++{
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++	struct snd_pcm_runtime *runtime = substream->runtime;
++	struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
++	struct ingenic_as_dma *as_dma = snd_soc_component_get_drvdata(component);
++	struct ingenic_as_dma_runtime *prtd = NULL;
++	struct snd_pcm_hardware pcm_hardware = ingenic_as_dma_pcm_hardware;
++	int ret;
++
++	DMA_DEBUG_MSG("enter %s[dai%d substream = %s], process is \"%s\" (pid %i)\n",
++			__func__, cpu_dai->id,
++			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
++			"playback" : "capture", current->comm, current->pid);
++
++	prtd = kzalloc(sizeof(*prtd), GFP_KERNEL);
++	if (!prtd)
++		return -ENOMEM;
++
++	ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
++	if (ret < 0)
++		return ret;
++
++	ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIOD_BYTES);
++	if (ret < 0)
++		return ret;
++
++	if (as_dma->dma_fth_quirk) {
++		snd_pcm_hw_rule_add(substream->runtime, 0,
++				SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
++				ingenic_as_dma_period_bytes_quirk,
++				NULL,
++				SNDRV_PCM_HW_PARAM_FRAME_BITS,
++				SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
++				-1);
++	}
++
++	prtd->as_dma = as_dma;
++	prtd->substream = substream;
++	prtd->dai_id = cpu_dai->id;
++	runtime->private_data = prtd;
++
++	/* dummy desc */
++	prtd->dummy_descs = (struct ingenic_as_dma_desc *)dma_alloc_coherent(as_dma->dev, 
++			sizeof(struct ingenic_as_dma_desc), &prtd->dummy_descs_phy, GFP_KERNEL);
++	if (IS_ERR_OR_NULL(prtd->dummy_descs)) {
++		return -ENOMEM;
++	}
++
++	spin_lock(&as_dma->lock);
++	as_dma->rtd[prtd->dai_id] = prtd;
++	as_dma->refcnt++;
++	prtd->fifo_depth = as_dma->fifo_depth[prtd->dai_id];
++	spin_unlock(&as_dma->lock);
++
++	pcm_hardware.fifo_size = prtd->fifo_depth << 2;
++	snd_soc_set_runtime_hwparams(substream, &pcm_hardware);
++	return 0;
++}
++
++static int ingenic_as_dma_close(struct snd_soc_component *component, struct snd_pcm_substream *substream)
++{
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++	struct ingenic_as_dma_runtime *prtd = substream_to_prtd(substream);
++	struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
++	struct ingenic_as_dma *as_dma = snd_soc_component_get_drvdata(component);
++
++	DMA_DEBUG_MSG("enter %s[dai%d substream = %s] process is \"%s\" (pid %i)\n",
++			__func__, cpu_dai->id,
++			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
++			"playback" : "capture", current->comm, current->pid);
++
++	spin_lock(&as_dma->lock);
++	as_dma->refcnt--;
++	as_dma->rtd[cpu_dai->id] = NULL;
++	spin_unlock(&as_dma->lock);
++
++	dma_free_coherent(as_dma->dev, sizeof(struct ingenic_as_dma_desc), prtd->dummy_descs, prtd->dummy_descs_phy);
++	kfree(prtd);
++	substream->runtime->private_data = NULL;
++	return 0;
++}
++
++static int ingenic_as_dma_ioctl(struct snd_soc_component *component, struct snd_pcm_substream *substream, unsigned int cmd, void *arg)
++{
++	return snd_pcm_lib_ioctl(substream, cmd, arg);
++}
++
++/* RETURN 0 not change, 1 change, < 0 failed */
++static int ingenic_as_dma_alloc_descs(struct ingenic_as_dma_runtime *prtd, int cnt)
++{
++	struct ingenic_as_dma *as_dma = prtd->as_dma;
++	int i, old_cnts = prtd->desc_cnts;
++
++	if (cnt == prtd->desc_cnts)
++		return 0;
++
++	for (i = cnt; i < old_cnts; i++) {
++		dma_pool_free(as_dma->desc_pool, prtd->descs[i], prtd->descs_phy[i]);
++		prtd->descs[i] = NULL;
++		prtd->descs_phy[i] = 0;
++		prtd->desc_cnts--;
++	}
++	for (i = old_cnts; i < cnt; i++) {
++		prtd->descs[i] = dma_pool_alloc(as_dma->desc_pool,
++				GFP_KERNEL, &prtd->descs_phy[i]);
++		if (!prtd->descs[i])
++			return -ENOMEM;
++		prtd->desc_cnts++;
++	}
++
++	return 1;
++}
++
++static void ingenic_as_dma_free_descs(struct ingenic_as_dma_runtime *prtd)
++{
++	struct ingenic_as_dma *as_dma = prtd->as_dma;
++	int i;
++
++	for (i = 0; i < prtd->desc_cnts; i++) {
++		dma_pool_free(as_dma->desc_pool, prtd->descs[i], prtd->descs_phy[i]);
++		prtd->descs[i] = NULL;
++		prtd->descs_phy[i] = 0;
++	}
++	prtd->desc_cnts = 0;
++}
++
++extern int ingenic_dsp_is_spdif_out(uint32_t dma_device_id);
++
++static void ingenic_as_dma_cyclic_descs_init(struct ingenic_as_dma_runtime *prtd,
++		 dma_addr_t dma_addr, struct snd_pcm_hw_params *params)
++{
++	struct ingenic_as_dma *as_dma = prtd->as_dma;
++	int i, tsz, ts_size;
++	int period_bytes = params_period_bytes(params);
++
++	DMA_DEBUG_MSG("%s [dai%d substream %s] args: \n\
++			fifo_depth(words) = %d, periods_bytes = %d\n",
++			__func__, prtd->dai_id,
++			(prtd->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
++			"playback" : "capture",
++			prtd->fifo_depth, period_bytes);
++
++	if (unlikely(!as_dma->dma_fth_quirk)) {
++		tsz = ingenic_as_dma_get_tsz(prtd->fifo_depth, period_bytes, &ts_size);
++	} else {
++		ts_size = DCM_TSZ_MAX_WORD << 2;
++		tsz = DCM_TSZ_MAX;
++	}
++	prtd->tsz_words = ts_size >> 2;
++	DMA_DEBUG_MSG("%s [dai%d substream %s] tsz result: tsz(words) = %d\n",
++			__func__, prtd->dai_id,
++			(prtd->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
++			"playback" : "capture",
++			prtd->tsz_words);
++
++	if(prtd->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		uint32_t dummy_time;
++
++		dummy_time = (ingenic_dsp_is_spdif_out(prtd->dai_id) && CONFIG_SND_ASOC_INGENIC_SPDIF_DUMMY_TIMES) ?
++			CONFIG_SND_ASOC_INGENIC_SPDIF_DUMMY_TIMES : CONFIG_SND_ASOC_INGENIC_PLAYBACK_DUMMY_TIMES;
++
++		if(dummy_time) {
++			uint32_t rate = params_rate(params);
++			uint32_t channels = params_channels(params);
++			uint32_t fmt_width = snd_pcm_format_width(params_format(params));
++			uint32_t dummy_bytes = dummy_time * (rate * channels * fmt_width) / (8 * 1000);
++
++			prtd->dummy_data_flag = 1;
++			prtd->dummy_data_irq = 0;
++
++			memset(prtd->dummy_descs, 0, sizeof(*prtd->dummy_descs));
++			prtd->dummy_descs->link = 1;
++			prtd->dummy_descs->tie = prtd->dummy_descs->bai = 0;
++			prtd->dummy_descs->tsz = tsz;
++			prtd->dummy_descs->dba = GET_PHYADDR(as_dma->dummy_data);
++			prtd->dummy_descs->ndoa = *(prtd->descs_phy);
++			prtd->dummy_descs->dtc = ((dummy_bytes)/ts_size);
++		}
++	}
++
++	for (i = 0; i < prtd->desc_cnts; i++) {
++		memset(prtd->descs[i], 0, sizeof(prtd->descs[i]));
++		prtd->descs[i]->link = prtd->descs[i]->tie = prtd->descs[i]->bai = 1;
++		prtd->descs[i]->tsz = tsz;
++		prtd->descs[i]->dba = dma_addr + i * period_bytes;
++		prtd->descs[i]->ndoa = *(prtd->descs_phy + ((i + 1)%prtd->desc_cnts));
++		prtd->descs[i]->dtc = (period_bytes/ts_size);
++	}
++	iob();
++}
++
++static int ingenic_as_dma_hw_params(struct snd_soc_component *component, struct snd_pcm_substream *substream,
++		struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++	struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
++	struct ingenic_as_dma_runtime *prtd = substream_to_prtd(substream);
++	struct ingenic_as_dma *as_dma = prtd->as_dma;
++	bool is_out = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? true : false;
++	int dev_id = cpu_dai->id;
++	int *x = NULL;
++	int ret;
++
++	DMA_DEBUG_MSG("%s [dai%d substream %s] periodbyte = %u, rate= %u, channels=%u, \n\
++			bufferbyte %d, periods %d, fmtwidth %d, periodsize %d\n",
++			__func__, dev_id,
++			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
++			"playback" : "capture",
++			params_period_bytes(params), params_rate(params),
++			params_channels(params), params_buffer_bytes(params),
++			params_periods(params), params_width(params),
++			params_period_size(params));
++
++	ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
++	if (ret < 0)
++		return ret;
++
++	ret = ingenic_as_dma_alloc_descs(prtd, params_periods(params));
++	if (ret < 0)
++		return ret;
++	ingenic_as_dma_cyclic_descs_init(prtd,
++			substream->runtime->dma_addr,
++			params);
++
++	x = (int *)prtd->descs[0];
++	DMA_DEBUG_MSG("%s [dai%d substream %s] DMA buffer addr: 0x%08x \n\
++			DMA desc[0] addr(0x%p:0x%08x) \n\
++			DES0(%p: 0x%08x) DES1(%p: 0x%08x)\n\
++			DES2(%p: 0x%08x) DES3(%p: 0x%08x)\n",
++			__func__, dev_id,
++			(prtd->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
++			"playback" : "capture",
++			substream->runtime->dma_addr,
++			prtd->descs[0], prtd->descs_phy[0],
++			x, *(x),
++			x + 1, *(x + 1),
++			x + 2, *(x + 2),
++			x + 3, *(x + 3));
++	ret = ingenic_as_fmtcov_cfg(substream, params);
++	if (ret < 0)
++		return ret;
++
++	regmap_write(as_dma->fifo_regmap, FFR(dev_id), FFR_FTH(prtd->tsz_words) | (is_out ? 0 : FFR_FIFO_TD));
++	return 0;
++}
++
++static int ingenic_as_dma_hw_free(struct snd_soc_component *component, struct snd_pcm_substream *substream)
++{
++	struct ingenic_as_dma_runtime *prtd = substream_to_prtd(substream);
++
++	ingenic_as_dma_free_descs(prtd);
++
++	return snd_pcm_lib_free_pages(substream);
++}
++
++void ingenic_as_dma_reg_dump(struct ingenic_as_dma *as_dma, int dev_id)
++{
++	unsigned int val;
++
++	printk("==>DMA\n");
++	regmap_read(as_dma->dma_regmap, DBA(dev_id), &val);
++	printk("DBA\t\t%x : 0x%08x\n",DBA(dev_id), val);
++	regmap_read(as_dma->dma_regmap, DTC(dev_id), &val);
++	printk("DTC\t\t%x : 0x%08x\n",DTC(dev_id), val);
++	regmap_read(as_dma->dma_regmap, DCR(dev_id), &val);
++	printk("DCR\t\t%x : 0x%08x\n",DCR(dev_id), val);
++	regmap_read(as_dma->dma_regmap, DSR(dev_id), &val);
++	printk("DSR\t\t%x : 0x%08x\n",DSR(dev_id), val);
++	regmap_read(as_dma->dma_regmap, DCM(dev_id), &val);
++	printk("DCM\t\t%x : 0x%08x\n",DCM(dev_id), val);
++	regmap_read(as_dma->dma_regmap, DDA(dev_id), &val);
++	printk("DDA\t\t%x : 0x%08x\n",DDA(dev_id), val);
++	regmap_read(as_dma->dma_regmap, DGER, &val);
++	printk("DGER\t\t%x : 0x%08x\n",DGER, val);
++	regmap_read(as_dma->dma_regmap, AEER, &val);
++	printk("AEER\t\t%x : 0x%08x\n",AEER, val);
++	regmap_read(as_dma->dma_regmap, AESR, &val);
++	printk("AESR\t\t%x : 0x%08x\n",AESR, val);
++	regmap_read(as_dma->dma_regmap, AIPR, &val);
++	printk("AIPR\t\t%x : 0x%08x\n",AIPR, val);
++
++	printk("==>FIFO\n");
++	regmap_read(as_dma->fifo_regmap, FAS(dev_id), &val);
++	printk("FAS\t\t%x : 0x%08x\n",FAS(dev_id), val);
++	regmap_read(as_dma->fifo_regmap, FCR(dev_id), &val);
++	printk("FCR\t\t%x : 0x%08x\n",FCR(dev_id), val);
++	regmap_read(as_dma->fifo_regmap, FFR(dev_id), &val);
++	printk("FFR\t\t%x : 0x%08x\n",FFR(dev_id), val);
++	regmap_read(as_dma->fifo_regmap, FSR(dev_id), &val);
++	printk("FSR\t\t%x : 0x%08x\n",FSR(dev_id), val);
++}
++
++static int ingenic_as_dma_start(struct ingenic_as_dma *as_dma, int dev_id)
++{
++	struct ingenic_as_dma_runtime *prtd = as_dma->rtd[dev_id];
++
++	regmap_write(as_dma->dma_regmap, DSR(dev_id), DSR_TT_INT|DSR_LTT_INT|DSR_LTT|DSR_TT);
++
++	regmap_update_bits(as_dma->dma_regmap, DCM(dev_id), DCM_NDES|DCM_TIE, DCM_TIE);
++
++	/* Note: DMA enable first FIFO enable, read operation
++	 * to ensure that the DMA module work
++	 * */
++	if (prtd->dummy_data_flag) {
++		prtd->dummy_data_irq = 1;
++		regmap_write(as_dma->dma_regmap, DDA(dev_id), prtd->dummy_descs_phy);
++	} else {
++		regmap_write(as_dma->dma_regmap, DDA(dev_id), prtd->descs_phy[0]);
++	}
++	readl_relaxed(as_dma->dma_base + DDA(dev_id));
++
++	ingenic_as_fmtcov_enable(dev_id, true);
++
++	regmap_write(as_dma->dma_regmap, DCR(dev_id), DCR_CTE);
++
++//	regmap_write(as_dma->fifo_regmap, FCR(dev_id), FCR_FLUSH);
++
++	regmap_write(as_dma->fifo_regmap, FCR(dev_id), FCR_FIFO_EN);
++
++	DMA_DEBUG_MSG("%s [dai%d substream %s] dma trigger start dba reg val = 0x%08x\n",
++			__func__, dev_id,
++			(prtd->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
++			"playback" : "capture",
++			readl_relaxed(as_dma->dma_base + DBA(prtd->dai_id)));
++
++	if (IS_BUILTIN(CONFIG_FPGA_TEST) || ingenic_dma_debug) {
++		regmap_write(as_dma->fifo_regmap, FSR(dev_id), FSR_TURROR);
++		regmap_update_bits(as_dma->fifo_regmap, FFR(dev_id), FFR_TURRORE, FFR_TURRORE);
++	}
++	return 0;
++}
++
++static int ingenic_as_dma_stop(struct ingenic_as_dma *as_dma, int dev_id)
++{
++	u32 val, timeout = 0xfff;
++
++	if (IS_BUILTIN(CONFIG_FPGA_TEST) || ingenic_dma_debug) {
++		regmap_update_bits(as_dma->fifo_regmap, FFR(dev_id), FFR_TURRORE, 0);
++		regmap_write(as_dma->fifo_regmap, FSR(dev_id), FSR_TURROR);
++	}
++
++	regmap_update_bits(as_dma->dma_regmap, DCM(dev_id), DCM_TIE, 0);
++	regmap_write(as_dma->dma_regmap, DSR(dev_id), DSR_TT_INT|DSR_LTT_INT|DSR_LTT|DSR_TT);
++
++	regmap_write(as_dma->fifo_regmap, FCR(dev_id), 0);
++
++	regmap_write(as_dma->dma_regmap, DCR(dev_id), 0);
++	do {
++		regmap_read(as_dma->dma_regmap, DSR(dev_id), &val);
++	} while ((val & DSR_RST_EN) && (--timeout));
++
++	regmap_write(as_dma->dma_regmap, DCR(dev_id), DCR_RESET);
++	udelay(10);
++
++	ingenic_as_fmtcov_enable(dev_id, false);
++
++	return 0;
++}
++
++#ifdef CONFIG_DMIC_AND_AMIC_SYNC
++static int ingenic_as_dma_dmic_and_amic_sync_trigger(struct snd_soc_component *component, struct snd_pcm_substream *substream, int cmd)
++{
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++	struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
++	struct ingenic_as_dma *as_dma = snd_soc_platform_get_drvdata(component);
++	int ret;
++	static int dmic_arrive = 0, amic_arrive = 0;
++	int timeout = 10000;
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:	/*FIXME*/
++		DMA_DEBUG_MSG("enter %s[dai%d substream = %s] start\n", __func__,
++				cpu_dai->id,
++				(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
++				"playback" : "capture");
++		if((substream->stream == SNDRV_PCM_STREAM_CAPTURE) &&
++			(strcmp("DMA5", cpu_dai->name) == 0 || strcmp("DMA6", cpu_dai->name) == 0)) {
++			snd_pcm_stream_unlock_irq(substream);
++		}
++		if(substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
++			if(!(strcmp("DMA5", cpu_dai->name))) {
++				/*  dmic regular use DMA5 */
++				dmic_arrive = 1;
++				while(timeout --) {
++					if(amic_arrive == 1) {
++						amic_arrive = 0;
++						break;
++					}
++					msleep(1);
++				}
++			}
++
++			if(!(strcmp("DMA6", cpu_dai->name))) {
++				/*amic regular use DMA6 */
++				amic_arrive = 1;
++				while(timeout --) {
++					if(dmic_arrive == 1) {
++						dmic_arrive = 0;
++						break;
++					}
++					msleep(1);
++				}
++			}
++		}
++
++		ret = ingenic_as_dma_start(as_dma, cpu_dai->id);
++		if((substream->stream == SNDRV_PCM_STREAM_CAPTURE) &&
++			(strcmp("DMA5", cpu_dai->name) == 0 || strcmp("DMA6", cpu_dai->name) == 0)) {
++			snd_pcm_stream_lock_irq(substream);
++		}
++		return ret;
++	case SNDRV_PCM_TRIGGER_STOP:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++		DMA_DEBUG_MSG("enter %s[dai%d substream = %s] stop\n", __func__,
++				cpu_dai->id,
++				(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
++				"playback" : "capture");
++		ret = ingenic_as_dma_stop(as_dma, cpu_dai->id);
++		return ret;
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		/*JUST stop or resume the be dai*/
++		return 0;
++	default:
++		return -EINVAL;
++	}
++}
++#endif
++
++static int ingenic_as_dma_trigger(struct snd_soc_component *component, struct snd_pcm_substream *substream, int cmd)
++{
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++	struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
++	struct ingenic_as_dma *as_dma = snd_soc_component_get_drvdata(component);
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:	/*FIXME*/
++		DMA_DEBUG_MSG("enter %s[dai%d substream = %s] start\n", __func__,
++				cpu_dai->id,
++				(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
++				"playback" : "capture");
++		return ingenic_as_dma_start(as_dma, cpu_dai->id);
++	case SNDRV_PCM_TRIGGER_STOP:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++		DMA_DEBUG_MSG("enter %s[dai%d substream = %s] stop\n", __func__,
++				cpu_dai->id,
++				(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
++				"playback" : "capture");
++		return ingenic_as_dma_stop(as_dma, cpu_dai->id);
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		/*JUST stop or resume the be dai*/
++		return 0;
++	default:
++		return -EINVAL;
++	}
++}
++
++static int ingenic_as_dma_pcm_new(struct snd_soc_component *component, struct snd_soc_pcm_runtime *rtd)
++{
++	struct snd_card *card = rtd->card->snd_card;
++	struct snd_pcm *pcm = rtd->pcm;
++
++
++	snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, card->dev,
++			INGENIC_DMA_BUFFERSIZE_PREALLOC, INGENIC_DMA_BUFFERSIZE_MAX);
++
++	return 0;
++}
++
++static void ingenic_as_dma_pcm_free(struct snd_soc_component *component, struct snd_pcm *pcm)
++{
++	snd_pcm_lib_preallocate_free_for_all(pcm);
++}
++
++
++static const struct snd_soc_component_driver ingenic_as_dma_platform = {
++	.name		= "as-dma",
++	.open		= ingenic_as_dma_open,
++	.close		= ingenic_as_dma_close,
++	.ioctl		= ingenic_as_dma_ioctl,
++	.hw_params	= ingenic_as_dma_hw_params,
++	.hw_free	= ingenic_as_dma_hw_free,
++	.trigger	= ingenic_as_dma_trigger,
++#ifdef CONFIG_DMIC_AND_AMIC_SYNC
++	.trigger        = ingenic_as_dma_dmic_and_amic_sync_trigger,
++#endif
++	.pointer	= ingenic_as_dma_pointer,
++	.pcm_construct	= ingenic_as_dma_pcm_new,
++	.pcm_destruct	= ingenic_as_dma_pcm_free,
++};
++
++static irqreturn_t ingenic_as_dma_irq_handler(int irq, void *dev_id)
++{
++	struct ingenic_as_dma *as_dma = (void *)dev_id;
++	struct ingenic_as_dma_runtime *prtd = NULL;
++	unsigned int dma_status, fifo_status, pending, pending1;
++	struct snd_pcm_substream *substream = NULL;
++	int ch;
++
++	regmap_read(as_dma->dma_regmap, AIPR, &pending);
++	dev_dbg(as_dma->dev, "interrupt (irq%d) pending %x\n", irq, pending);
++	pending &= AIPR_DMA_INT_MSK;
++	pending1 = pending;
++
++	while((ch = ffs(pending1))) {
++		ch -= 1;
++		pending1 &= ~BIT(ch);
++		regmap_read(as_dma->dma_regmap, DSR(ch), &dma_status);
++		regmap_write(as_dma->dma_regmap, DSR(ch), dma_status);
++		if (!(dma_status & DSR_TT_INT))
++			continue;
++		dev_dbg(as_dma->dev, "dma ch(%x) pending %x\n", dma_status, ch);
++		spin_lock(&as_dma->lock);
++		substream = NULL;
++		prtd = as_dma->rtd[ch];
++		if (likely(prtd)) {
++			substream = prtd->substream;
++			spin_unlock(&as_dma->lock);
++			if (prtd->dummy_data_flag &&
++					prtd->dummy_data_irq) {
++				prtd->dummy_data_irq = 0;
++			} else {
++				prtd->hw_ptr = readl_relaxed(as_dma->dma_base + DBA(prtd->dai_id));
++				snd_pcm_period_elapsed(substream);
++			}
++
++		} else {
++			spin_unlock(&as_dma->lock);
++			dev_warn(as_dma->dev, "dma channel(%d) \
++					stream has been stopped\n", ch);
++		}
++	}
++
++	if (IS_BUILTIN(CONFIG_FPGA_TEST) || ingenic_dma_debug) {
++		while((ch = ffs(pending))) { /*handle ror/tur debug*/
++			ch -= 1;
++			pending &= ~BIT(ch);
++			regmap_read(as_dma->fifo_regmap, FSR(ch), &fifo_status);
++			regmap_write(as_dma->fifo_regmap, FSR(ch), fifo_status);
++			if (fifo_status & FSR_TURROR_INT)
++				dev_warn(as_dma->dev, "Fifo %d xrun\n", ch);
++		}
++	}
++
++	return IRQ_HANDLED;
++}
++
++ssize_t fifo_depth_show(struct device *dev, struct device_attribute *attr,
++		char *buf)
++{
++	struct ingenic_as_dma *as_dma = dev_get_drvdata(dev);
++	ssize_t len = 0;
++	int ch;
++
++	for (ch = 0;  ch < as_dma->chan_cnts; ch++) {
++		len += snprintf(buf + len, PAGE_SIZE - len, ch ? "-%d": "%d", as_dma->fifo_depth[ch]);
++	}
++	return len;
++}
++
++ssize_t fifo_depth_store(struct device *dev, struct device_attribute *attr,
++		const char *buf, size_t count)
++{
++	struct ingenic_as_dma *as_dma = dev_get_drvdata(dev);
++	char *val, *tmp = (char *)vmalloc(strlen(buf) + 1);
++	unsigned long depth, res_depth = as_dma->fifo_total_depth;
++	int ret, ch = 0, res_chs = as_dma->chan_cnts;
++
++	memcpy(tmp, buf, strlen(buf) + 1);
++
++	spin_lock(&as_dma->lock);
++	if (as_dma->refcnt) {
++		spin_unlock(&as_dma->lock);
++		return 0;
++	}
++
++	while (*tmp && res_chs && res_depth) {
++		val = strsep(&tmp, "-");
++		ret = kstrtoul(val, 10, &depth);
++		WARN_ON(ret);
++		as_dma->fifo_depth[ch++] = min(min(depth, res_depth),
++				(unsigned long)(FAS_FAD >> FAS_FAD_SFT));
++		res_depth -= depth;
++		res_chs--;
++	}
++
++	for (;ch < as_dma->chan_cnts; ch++)
++		as_dma->fifo_depth[ch++] = res_depth/res_chs;
++
++	for (ch = 0; ch < as_dma->chan_cnts; ch++)
++		regmap_write(as_dma->fifo_regmap, FAS(ch), as_dma->fifo_depth[ch]);
++	spin_unlock(&as_dma->lock);
++	return count;
++}
++
++static DEVICE_ATTR_RW(fifo_depth);
++
++static struct attribute *ingenic_as_dma_attrs[] = {
++	&dev_attr_fifo_depth.attr,
++	NULL,
++};
++
++static struct attribute_group ingenic_as_dma_attr_grp = {
++	.attrs = ingenic_as_dma_attrs,
++};
++
++static const struct attribute_group *ingenic_as_dma_groups[] = {
++	&ingenic_as_dma_attr_grp,
++	NULL,
++};
++
++static const struct of_device_id ingenic_as_dma_match_table[];
++static int ingenic_as_dma_probe(struct platform_device *pdev)
++{
++	struct ingenic_as_dma *as_dma;
++	const struct of_device_id *match;
++	struct resource *res;
++	int ret, chan_cnts, i;
++	u32 fifo_depth;
++	struct regmap_config regmap_config = {
++		.reg_bits = 32,
++		.reg_stride = 4,
++		.val_bits = 32,
++		.cache_type = REGCACHE_NONE,
++	};
++
++	match = of_match_node(ingenic_as_dma_match_table, pdev->dev.of_node);
++	if (!match)
++		return -ENODEV;
++	chan_cnts = (int)match->data;
++
++	as_dma = (struct ingenic_as_dma *)devm_kzalloc(&pdev->dev, sizeof(*as_dma) +
++			(sizeof (*as_dma->rtd) + sizeof(*as_dma->fifo_depth)) * chan_cnts,
++			GFP_KERNEL);
++	if (!as_dma)
++		return -ENOMEM;
++
++	as_dma->dev = &pdev->dev;
++	as_dma->rtd = (void *)(as_dma + 1);
++	as_dma->fifo_depth = (void *)(as_dma->rtd + chan_cnts);
++	as_dma->chan_cnts = chan_cnts;
++
++	/* dummy data */
++	as_dma->dummy_data = (uint8_t *)dma_alloc_coherent(&pdev->dev, 
++			sizeof(uint8_t) * 4 * 32, &as_dma->dummy_data_pyaddr, GFP_KERNEL);
++	if (IS_ERR_OR_NULL(as_dma->dummy_data)) {
++		return -ENOMEM;
++	}
++
++	spin_lock_init(&as_dma->lock);
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
++	as_dma->dma_base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(as_dma->dma_base))
++		return PTR_ERR(as_dma->dma_base);
++	regmap_config.max_register = resource_size(res) - 0x4;
++	regmap_config.name = res->name;
++	as_dma->dma_regmap = devm_regmap_init_mmio(&pdev->dev,
++			as_dma->dma_base,
++			&regmap_config);
++	if (IS_ERR(as_dma->dma_regmap))
++		return PTR_ERR(as_dma->dma_regmap);
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fifo");
++	as_dma->fifo_base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(as_dma->fifo_base))
++		return PTR_ERR(as_dma->fifo_base);
++	regmap_config.max_register = resource_size(res) - 0x4;
++	regmap_config.name = res->name;
++	as_dma->fifo_regmap = devm_regmap_init_mmio(&pdev->dev,
++			as_dma->fifo_base,
++			&regmap_config);
++	if (IS_ERR(as_dma->fifo_regmap))
++		return PTR_ERR(as_dma->fifo_regmap);
++
++	as_dma->irq = of_irq_get(pdev->dev.of_node, 0);
++	if (as_dma->irq < 0)
++		return as_dma->irq;
++
++	as_dma->audio_clk = devm_clk_get(&pdev->dev, "gate_audio");
++	if(IS_ERR_OR_NULL(as_dma->audio_clk)) {
++		dev_err(&pdev->dev, "Failed to get gate_audio clk!\n");
++	}
++	clk_prepare_enable(as_dma->audio_clk);
++
++	platform_set_drvdata(pdev, as_dma);
++
++	regmap_write(as_dma->dma_regmap, DGRR, DGRR_RESET);
++
++	/*INIT FIFO*/
++	if (of_property_read_u32(pdev->dev.of_node, "ingenic,fifo_size", &as_dma->fifo_total_depth))
++		as_dma->fifo_total_depth = INGENIC_DEF_FIFO_DEPTH;
++
++	as_dma->dma_fth_quirk = of_property_read_bool(pdev->dev.of_node, "ingenic,fth_quirk");
++
++	fifo_depth = 384;
++	for (i = 0; i < as_dma->chan_cnts; i++) {
++		as_dma->fifo_depth[i] = fifo_depth;
++		regmap_write(as_dma->fifo_regmap, FAS(i), fifo_depth);
++	}
++
++	ret = devm_request_threaded_irq(&pdev->dev, as_dma->irq, NULL,
++			ingenic_as_dma_irq_handler, IRQF_SHARED|IRQF_ONESHOT,
++			"as-dma", as_dma);
++	if (ret)
++		return ret;
++
++	as_dma->desc_pool = dma_pool_create("as_dma_desc_pool", &pdev->dev,
++			sizeof(struct ingenic_as_dma_desc),
++			__alignof__(struct ingenic_as_dma_desc), 0);
++	if (!as_dma->desc_pool)
++		return -ENOMEM;
++
++	ret = devm_snd_soc_register_component(&pdev->dev, &ingenic_as_dma_platform, NULL, 0);
++
++
++	if (ret) {
++		dma_pool_destroy(as_dma->desc_pool);
++		return ret;
++	}
++
++	ret = sysfs_create_groups(&pdev->dev.kobj, ingenic_as_dma_groups);
++	if (ret)
++		return ret;
++
++	dev_info(&pdev->dev, "probe success!!!\n");
++	return 0;
++}
++
++static int ingenic_as_dma_remove(struct platform_device *pdev)
++{
++	struct ingenic_as_dma *as_dma = platform_get_drvdata(pdev);
++
++	dma_pool_destroy(as_dma->desc_pool);
++	dma_free_coherent(&pdev->dev, sizeof(uint8_t) * 4 * 32, as_dma->dummy_data, as_dma->dummy_data_pyaddr);
++	platform_set_drvdata(pdev, NULL);
++
++	return 0;
++}
++
++static const struct of_device_id ingenic_as_dma_match_table[] = {
++#define INGENIC_AS_DMA_DEF_CHS (10)
++	{ .compatible = "ingenic,as-platform", .data = (void*)INGENIC_AS_DMA_DEF_CHS},
++#undef INGENIC_AS_DMA_DEF_CHS
++	{ }
++};
++MODULE_DEVICE_TABLE(of, ingenic_as_dma_match_table);
++
++#ifdef CONFIG_PM
++static int ingenic_as_dma_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	struct ingenic_as_dma *as_dma = platform_get_drvdata(pdev);
++	int i;
++	unsigned int fcr;
++
++	for(i = 0; i < as_dma->chan_cnts; i++) {
++		regmap_read(as_dma->fifo_regmap, FCR(i), &fcr);
++		if(fcr & FCR_FIFO_EN) {
++			return -1;
++		}
++	}
++	return 0;
++}
++
++static int ingenic_as_dma_resume(struct platform_device *pdev)
++{
++	return 0;
++}
++#endif
++
++static struct platform_driver ingenic_as_dma_platform_driver = {
++	.driver = {
++		.name = "as-platform",
++		.of_match_table = ingenic_as_dma_match_table,
++	},
++	.probe = ingenic_as_dma_probe,
++	.remove = ingenic_as_dma_remove,
++#ifdef CONFIG_PM
++	.suspend = ingenic_as_dma_suspend,
++	.resume = ingenic_as_dma_resume,
++#endif
++};
++
++extern int ingenic_as_fmtcov_platform_driver_modinit(void);
++extern int ingenic_as_dsp_platform_driver_modinit(void);
++extern int ingenic_as_mixer_platform_driver_modinit(void);
++static int ingenic_as_dma_platform_driver_modinit(void)
++{
++	platform_driver_register(&ingenic_as_dma_platform_driver);
++	ingenic_as_dsp_platform_driver_modinit();
++	ingenic_as_mixer_platform_driver_modinit();
++	return ingenic_as_fmtcov_platform_driver_modinit();
++}
++
++extern void ingenic_as_mixer_platform_driver_exit(void);
++extern void ingenic_as_fmtcov_platform_driver_exit(void);
++extern void ingenic_as_dsp_platform_driver_exit(void);
++static void ingenic_as_dma_platform_driver_exit(void)
++{
++	ingenic_as_fmtcov_platform_driver_exit();
++	ingenic_as_mixer_platform_driver_exit();
++	ingenic_as_dsp_platform_driver_exit();
++	platform_driver_unregister(&ingenic_as_dma_platform_driver);
++}
++
++module_init(ingenic_as_dma_platform_driver_modinit);
++module_exit(ingenic_as_dma_platform_driver_exit);
++/* module_platform_driver(ingenic_as_dma_platform_driver); */
++
++MODULE_AUTHOR("cli <chen.li@ingenic.com>");
++MODULE_DESCRIPTION("Ingenic AS DMA SoC Interface");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-as-dma");
+diff --git a/module_drivers/sound/soc/ingenic/as-v2/as-dma.h b/module_drivers/sound/soc/ingenic/as-v2/as-dma.h
+new file mode 100644
+index 000000000..4ab79d084
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v2/as-dma.h
+@@ -0,0 +1,205 @@
++/*
++ * ALSA Soc Audio Layer -- Ingenic AS DMA Controller
++ *
++ * Copyright 2017 - 2022 Ingenic Semiconductor Co.,Ltd
++ *     cli <chen.li@ingenic.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#ifndef __AS_DMA_H__
++#define __AS_DMA_H__
++
++#include <linux/bitops.h>
++
++/* DMA */
++#define DMA_CH_OFF	(0x18)
++#define DBA(ch)		(0x0 + (ch) * DMA_CH_OFF)
++#define DTC(ch)		(0x4 + (ch) * DMA_CH_OFF)
++#define DCR(ch)		(0x8 + (ch) * DMA_CH_OFF)
++#define DSR(ch)		(0xc + (ch) * DMA_CH_OFF)
++#define DCM(ch)		(0x10 + (ch) * DMA_CH_OFF)
++#define DDA(ch)		(0x14 + (ch) * DMA_CH_OFF)
++#define DGRR		(0x100)
++#define DGER		(0x104)
++#define AEER		(0x108)
++#define AESR		(0x10c)
++#define AIPR		(0x110)
++
++#define DTC_TC_SFT		(0)
++#define DTC_TC			GENMASK(23, DTC_TC_SFT)
++
++#define DCR_RESET		BIT(1)
++#define DCR_CTE			BIT(0)
++
++#define DSR_CDOA_SFT		(8)
++#define DSR_CDOA		GENMASK(15, DSR_CDOA_SFT)
++#define DSR_TT_INT		BIT(5)
++#define DSR_LTT_INT		BIT(4)
++#define DSR_TT			BIT(3)
++#define DSR_LTT			BIT(2)
++#define DSR_RST_EN		BIT(1)
++#define DSR_LINK		BIT(0)
++
++#define DCM_NDES		BIT(31)
++#define DCM_BAI			BIT(8)
++#define DCM_TSZ_SFT		(4)
++#define SET_DMA_BURST_SZ(burst) (0x1 << (burst + 1))
++#define DMA_BURST_4_WORD        (0x1)
++#define DMA_BURST_8_WORD        (0x2)
++#define DMA_BURST_16_WORD       (0x3)
++#define DMA_BURST_32_WORD       (0x4)
++#define DCM_TSZ_MAX		DMA_BURST_32_WORD
++#define DCM_TSZ_MAX_WORD	SET_DMA_BURST_SZ(DCM_TSZ_MAX)
++#define DCM_TSZ_MSK		GENMASK(6, DCM_TSZ_SFT)
++#define DCM_TIE			BIT(1)
++#define DCM_LTIE		BIT(0)
++
++#define DGRR_RESET		BIT(0)
++
++#define DGER_DMA_EN		BIT(0)
++
++#define AEER_EXP_EN		BIT(0)
++
++#define AESR_EXP		BIT(0)
++
++#define AIPR_MSK		GENMASK(11, 0)
++#define AIPR_EXP_INT		BIT(11)
++#define AIPR_DIMC_INT		BIT(10)
++#define AIPR_DMA_INT_MSK	GENMASK(9, 0)
++#define AIPR_DMA_INT(ch)	BIT((ch))
++
++/* FIFO */
++#define FIFO_CH_OFF	(0x10)
++#define FAS(ch)		(0x0 + (ch) * FIFO_CH_OFF)
++#define FCR(ch)		(0x4 + (ch) * FIFO_CH_OFF)
++#define FFR(ch)		(0x8 + (ch) * FIFO_CH_OFF)
++#define FSR(ch)		(0xc + (ch) * FIFO_CH_OFF)
++
++#define FAS_FAD_SFT	(0)
++#define FAS_FAD		GENMASK(12, FAS_FAD_SFT)
++
++#define FCR_FLUSH	BIT(2)
++#define FCR_FULL_EN	BIT(1)
++#define FCR_FIFO_EN	BIT(0)
++
++#define FFR_FTH_SFT	(16)
++#define FFR_FTH_MSK	GENMASK(28, FFR_FTH_SFT)
++#define FFR_FTH(n)	(((n) << FFR_FTH_SFT) & FFR_FTH_MSK)
++#define FFR_TURRORE	BIT(9)
++#define FFR_FSE		BIT(8)
++#define FFR_FIFO_TD	BIT(7)
++
++#define FSR_FLEVEL_SFT	(16)
++#define FSR_FLEVEL	GENMASK(28, FSR_FLEVEL_SFT)
++#define FSR_TURROR_INT	BIT(5)
++#define FSR_TFSRFS_INT	BIT(4)
++#define FSR_TURROR	BIT(2)
++#define FSR_TFSRFS	BIT(0)
++
++struct ingenic_as_dma_desc {
++	/*desc0*/
++	uint32_t ltie:1;	/* Last Transfer Interrupt Enable */
++	uint32_t tie:1;		/* Transfer Interrupt Enable */
++	uint32_t link:1;	/* Enable Descriptor Link Enable */
++	uint32_t lte:1;		/* Last Descriptor Transfer end Status */
++	uint32_t tsz:3;		/* Transfer Data Size (burst)*/
++	uint32_t reserved0_7:1;
++	uint32_t bai:1;		/* Target Address Increment */
++	uint32_t reserved0_9_31:23;
++	/*desc 1*/
++	uint32_t dba;		/* Bus Address (memory address)*/
++	/*desc 2*/
++	uint32_t ndoa;		/* Descriptor Next Offset address*/
++	/*desc 3*/
++	uint32_t dtc:24;	/*Transfer Counter(burst count)*/
++	uint32_t reserved3_24_31:8;
++} __attribute__ ((packed));
++
++#define INGENIC_DEF_FIFO_DEPTH (4096)
++#define INGENIC_PERIODS_MIN (4)
++#define INGENIC_PERIODS_BYTES_MIN (4096)
++#define INGENIC_DMA_BUFFERSIZE_MAX (CONFIG_SND_ASOC_INGENIC_DMA_PREALLOC_PAGES * 4096)
++#define INGENIC_DMA_BUFFERSIZE_PREALLOC INGENIC_DMA_BUFFERSIZE_MAX
++
++struct ingenic_as_dma_runtime {
++	struct snd_pcm_substream *substream;
++	u8 dai_id;
++	struct ingenic_as_dma_desc *descs[INGENIC_DMA_BUFFERSIZE_MAX/INGENIC_PERIODS_BYTES_MIN];
++	dma_addr_t descs_phy[INGENIC_DMA_BUFFERSIZE_MAX/INGENIC_PERIODS_BYTES_MIN];
++	unsigned int hw_ptr;
++
++	/* dumm desc */
++	struct ingenic_as_dma_desc *dummy_descs;
++	dma_addr_t dummy_descs_phy;
++	bool dummy_data_flag;
++	bool dummy_data_irq;
++
++	uint8_t	desc_cnts;
++	uint32_t fifo_depth;
++	uint32_t tsz_words;
++	struct ingenic_as_dma *as_dma;
++};
++
++struct ingenic_as_dma {
++	struct device *dev;
++	struct regmap *dma_regmap;
++	struct regmap *fifo_regmap;
++	void __iomem *dma_base;
++	void __iomem *fifo_base;
++	int irq;
++	int chan_cnts;
++	struct dma_pool *desc_pool;
++
++	/* dummy data */
++	uint8_t *dummy_data;
++	dma_addr_t dummy_data_pyaddr;
++
++	uint32_t fifo_total_depth;
++	bool dma_fth_quirk;
++
++	struct clk *audio_clk;
++
++	spinlock_t lock;
++	struct ingenic_as_dma_runtime **rtd;
++	uint32_t *fifo_depth;
++	int refcnt;
++};
++
++static inline struct ingenic_as_dma_runtime *substream_to_prtd(
++	const struct snd_pcm_substream *substream)
++{
++	return substream->runtime->private_data;
++}
++
++static inline int ingenic_as_dma_get_tsz(int fifo_depth,
++		int period_sz, int *ts_byte_sz)
++{
++	int tsz_reg = 0, ts_word_sz = 1;
++
++	if (period_sz & ((4 << 2) - 1)) {
++		*ts_byte_sz = ts_word_sz << 2;
++		return tsz_reg;
++	}
++	period_sz >>= 2;	/*word size*/
++
++	period_sz >>= 2;
++	ts_word_sz <<= 2;
++	tsz_reg++;
++
++	while ((!(period_sz & 0x1)) &&
++			(ts_word_sz << 1) <= fifo_depth) {
++		period_sz >>= 1;
++		ts_word_sz <<= 1;
++		tsz_reg++;
++		if (ts_word_sz >= DCM_TSZ_MAX_WORD)
++			break;
++	}
++
++	if (ts_byte_sz)
++		*ts_byte_sz = ts_word_sz << 2;
++	return tsz_reg;
++}
++#endif /*__AS_DMA_H__*/
+diff --git a/module_drivers/sound/soc/ingenic/as-v2/as-dmic.c b/module_drivers/sound/soc/ingenic/as-v2/as-dmic.c
+new file mode 100644
+index 000000000..e9d7c9e37
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v2/as-dmic.c
+@@ -0,0 +1,309 @@
++/*
++ * ALSA Soc Audio Layer -- ingenic as(audio system) dmic(Basic Audio Inter-
++ * face Controller) driver
++ *
++ * Copyright 2017 - 2022 Ingenic Semiconductor Co.,Ltd
++ *   wqshao <wangquan.shao@ingenic.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/initval.h>
++#include <sound/soc.h>
++#include <sound/soc-dai.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++#include <linux/types.h>
++#include <linux/clk.h>
++#include <sound/tlv.h>
++#include <sound/control.h>
++#include "as-dmic.h"
++
++#ifdef DEBUG
++static int ingenic_dmic_debug = 1;
++#else
++static int ingenic_dmic_debug = 0;
++#endif
++module_param(ingenic_dmic_debug, int, 0644);
++#define DMIC_DEBUG_MSG(msg...)					\
++	do {										\
++		if (ingenic_dmic_debug)					\
++			printk(KERN_DEBUG"DMIC: " msg);		\
++	} while(0)
++
++static int ingenic_dmic_reset(struct ingenic_dmic *dmic)
++{
++	unsigned int val, time_out = 0xfff;
++
++	regmap_update_bits(dmic->regmap, DMIC_CR0, DMIC_RESET, DMIC_RESET);
++	do {
++		regmap_read(dmic->regmap, DMIC_CR0, &val);
++	} while((val & DMIC_RESET) && (--time_out));
++	if(!time_out) {
++		dev_err(dmic->dev, "DMIC reset fail ...\n");
++		return -EIO;
++	}
++	return 0;
++}
++
++static int ingenic_dmic_startup(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct ingenic_dmic *dmic = dev_get_drvdata(dai->dev);
++
++	DMIC_DEBUG_MSG("enter %s\n", __func__);
++
++	return ingenic_dmic_reset(dmic);
++}
++
++static int ingenic_dmic_trigger(struct snd_pcm_substream *substream,
++		int cmd, struct snd_soc_dai *dai)
++{
++	struct ingenic_dmic *dmic = dev_get_drvdata(dai->dev);
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		DMIC_DEBUG_MSG("start\n");
++		regmap_update_bits(dmic->regmap, DMIC_CR0, DMIC_EN, DMIC_EN);
++		break;
++	case SNDRV_PCM_TRIGGER_STOP:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++		DMIC_DEBUG_MSG("stop\n");
++		regmap_update_bits(dmic->regmap, DMIC_CR0, DMIC_EN, 0);
++		return ingenic_dmic_reset(dmic);
++		break;
++	}
++	return 0;
++}
++
++static int ingenic_dmic_params_check(int channels, int rate, int fmt_width)
++{
++	if (channels < 1 && channels > 12)
++		goto error;
++
++	if ((rate != 8000) && (rate != 16000)
++			&& (rate != 48000) && (rate != 96000))
++		goto error;
++
++	if ((fmt_width != 16) && (fmt_width != 24))
++		goto error;
++
++	return true;
++error:
++	pr_err("%s %d, parameter is illegal!\n", __func__, __LINE__);
++	return false;
++}
++
++static int ingenic_dmic_hw_params(struct snd_pcm_substream *substream,
++		struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
++{
++	int channels = params_channels(params);
++	int rate = params_rate(params);
++	int fmt_width = snd_pcm_format_width(params_format(params));
++	struct ingenic_dmic *dmic = dev_get_drvdata(dai->dev);
++	u32 dmic_cr = 0;
++
++	DMIC_DEBUG_MSG("enter %s, substream = %s chl=%d, rate=%d, fmt_width=%d\n",__func__,
++			"capture", channels, rate, fmt_width);
++
++	if (!ingenic_dmic_params_check(channels, rate, fmt_width))
++		return -EINVAL;
++
++	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
++		dmic_cr = DMIC_SET_CHL(channels);
++		dmic_cr |= DMIC_SET_SR(rate);
++		dmic_cr |= DMIC_SET_OSS(fmt_width);
++		regmap_update_bits(dmic->regmap, DMIC_CR0, CHNUM_MASK|SR_MASK|OSS_MASK, dmic_cr);
++	} else {
++		dev_err(dmic->dev, "DMIC is a capture device\n");
++		return -ENXIO;
++	}
++
++	return 0;
++}
++
++static struct snd_soc_dai_ops ingenic_dmic_dai_ops = {
++	.startup	= ingenic_dmic_startup,
++	.trigger    = ingenic_dmic_trigger,
++	.hw_params  = ingenic_dmic_hw_params,
++};
++
++/*
++ * GAIN volume control:
++ * from 0 to 93 dB in 3 dB steps (0dB means no gain is used)
++ * */
++static const DECLARE_TLV_DB_SCALE(dmic_tlv, 0, 300, 0);
++
++static const struct snd_kcontrol_new ingenic_dmic_controls[] = {
++	SOC_SINGLE_TLV("DMIC Volume", DMIC_GCR, DGAIN_SFT, 31, 0, dmic_tlv),
++
++	SOC_SINGLE("DMIC High Pass Filter1 Switch", DMIC_CR0, HPF1_EN_SFT, 1, 0),
++	SOC_SINGLE("DMIC High Pass Filter2 Switch", DMIC_CR0, HPF2_EN_SFT, 1, 0),
++	SOC_SINGLE("DMIC Low Pass Filter Switch", DMIC_CR0, LPF_EN_SFT, 1, 0),
++
++	SOC_SINGLE("DMIC SW_LR Switch", DMIC_CR0, SW_LR_SFT, 1, 0),
++};
++
++struct snd_soc_component_driver ingenic_dmic_component = {
++	.name			= "as_dmic",
++	.controls		= ingenic_dmic_controls,
++	.num_controls	= ARRAY_SIZE(ingenic_dmic_controls),
++};
++
++static int ingenic_dmic_probe(struct snd_soc_dai *dai)
++{
++	struct ingenic_dmic *dmic = dev_get_drvdata(dai->dev);
++
++	regmap_update_bits(dmic->regmap, DMIC_CR0, HPF2_EN|LPF_EN|HPF1_EN,
++			HPF2_EN|LPF_EN|HPF1_EN);
++	/*gain: 0, ..., 1F*/
++	regmap_write(dmic->regmap, DMIC_GCR, DMIC_SET_GAIN(4));
++
++	return 0;
++}
++
++static int ingenic_dmic_clk_init(struct platform_device *pdev,
++	struct ingenic_dmic *dmic)
++{
++	const char *name;
++
++	of_property_read_string(dmic->dev->of_node, "ingenic,clk-name", &name);
++	dmic->clk = devm_clk_get(dmic->dev, name);
++	if(IS_ERR_OR_NULL(dmic->clk)) {
++		dev_warn(dmic->dev, "Warning ... Failed to get %s!\n", name);
++	}
++
++	/* Setup dmic's Parent clk, fix to i2s2 */
++	if(dmic->clk) {
++		struct clk *parent;
++		of_property_read_string(dmic->dev->of_node, "ingenic,clk-parent", &name);
++		parent =  devm_clk_get(dmic->dev, name);
++		if(IS_ERR_OR_NULL(parent)) {
++			dev_warn(dmic->dev, "Warning ... Failed to get %s!\n", name);
++		}
++		clk_set_parent(dmic->clk, parent);
++		devm_clk_put(dmic->dev, parent);
++	}
++
++	dmic->clk_gate = devm_clk_get(dmic->dev, "gate_dmic");
++	if(IS_ERR_OR_NULL(dmic->clk_gate)) {
++		dev_warn(dmic->dev, "Warning ... Failed to get gate_dmic!\n");
++	}
++
++	if(dmic->clk) {
++		clk_set_rate(dmic->clk, 24000000);
++		clk_prepare_enable(dmic->clk);
++	}
++	if(dmic->clk_gate) {
++		clk_prepare_enable(dmic->clk_gate);
++	}
++
++	return 0;
++}
++
++static int ingenic_dmic_platform_probe(struct platform_device *pdev)
++{
++	struct ingenic_dmic *dmic;
++	struct resource *res;
++	int ret;
++	struct regmap_config regmap_config = {
++		.reg_bits = 32,
++		.reg_stride = 4,
++		.val_bits = 32,
++		.cache_type = REGCACHE_NONE,
++	};
++
++	dmic = devm_kzalloc(&pdev->dev, sizeof(struct ingenic_dmic) +
++			sizeof(struct snd_soc_dai_driver), GFP_KERNEL);
++	if (!dmic)
++		return -ENOMEM;
++
++	dmic->dai_driver = (struct snd_soc_dai_driver*)(dmic + 1);
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	dmic->io_base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(dmic->io_base))
++		return PTR_ERR(dmic->io_base);
++	regmap_config.max_register = resource_size(res) - 0x4;
++	dmic->regmap = devm_regmap_init_mmio(&pdev->dev,
++			dmic->io_base,
++			&regmap_config);
++	if (IS_ERR(dmic->regmap))
++		return PTR_ERR(dmic->regmap);
++	dmic->dev = &pdev->dev;
++
++	dmic->dai_driver->id = 1;
++	dmic->dai_driver->name = "DMIC";
++	dmic->dai_driver->probe = ingenic_dmic_probe;;
++	dmic->dai_driver->ops = &ingenic_dmic_dai_ops;
++	dmic->dai_driver->capture.stream_name = "DMIC capture";
++	dmic->dai_driver->capture.channels_min = 1;
++	dmic->dai_driver->capture.channels_max = 8;
++
++	ingenic_dmic_clk_init(pdev, dmic);
++	platform_set_drvdata(pdev, dmic);
++
++	ret = devm_snd_soc_register_component(&pdev->dev, &ingenic_dmic_component,
++			dmic->dai_driver, 1);
++	if (!ret)
++		dev_info(&pdev->dev, "dmic platform probe success\n");
++
++	return ret;
++}
++
++static int ingenic_dmic_platform_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id ingenic_dmic_match_table[] = {
++	{ .compatible = "ingenic,as-dmic", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, ingenic_dmic_match_table);
++
++#ifdef CONFIG_PM
++static int ingenic_dmic_runtime_suspend(struct device *dev)
++{
++	return 0;
++}
++
++static int ingenic_dmic_runtime_resume(struct device *dev)
++{
++	return 0;
++}
++#endif
++
++static const struct dev_pm_ops ingenic_dmic_pm_ops = {
++	SET_RUNTIME_PM_OPS(ingenic_dmic_runtime_suspend,
++			ingenic_dmic_runtime_resume, NULL)
++};
++
++
++static struct platform_driver ingenic_dmic_platform_driver = {
++	.driver = {
++		.name = "as-dmic",
++		.of_match_table = ingenic_dmic_match_table,
++		.pm = &ingenic_dmic_pm_ops,
++	},
++	.probe = ingenic_dmic_platform_probe,
++	.remove = ingenic_dmic_platform_remove,
++};
++module_platform_driver(ingenic_dmic_platform_driver);
++
++MODULE_AUTHOR("wqshao <wangquan.shao@ingenic.com>");
++MODULE_DESCRIPTION("Ingenic AS dmic SoC Interface");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-as-dmic");
+diff --git a/module_drivers/sound/soc/ingenic/as-v2/as-dmic.h b/module_drivers/sound/soc/ingenic/as-v2/as-dmic.h
+new file mode 100644
+index 000000000..0ea9ed7f8
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v2/as-dmic.h
+@@ -0,0 +1,64 @@
++/*
++ * ALSA Soc Audio Layer -- ingenic as(audio system) dmic(Basic Audio Inter-
++ * face Controller) driver
++ *
++ * Copyright 2017 - 2022 Ingenic Semiconductor Co.,Ltd
++ *   wqshao <wangquan.shao@ingenic.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#ifndef __AS_DMIC_H__
++#define __AS_DMIC_H__
++
++#include <linux/bitops.h>
++
++struct ingenic_dmic {
++	struct device   *dev;
++	struct regmap *regmap;
++	void __iomem    *io_base;
++	struct snd_soc_dai_driver *dai_driver;
++	struct clk *clk;
++	struct clk *clk_gate;
++};
++
++#define DMIC_CR0	(0x0)
++#define DMIC_GCR	(0x4)
++#define DMIC_IER	(0x8)
++#define DMIC_ICR	(0xc)
++#define DMIC_TCR	(0x10)
++
++/* DMIC_CR0 */
++#define DMIC_RESET		BIT(31)
++#define HPF2_EN_SFT		(22)
++#define HPF2_EN			BIT(22)
++#define LPF_EN_SFT		(21)
++#define LPF_EN			BIT(21)
++#define HPF1_EN_SFT		(20)
++#define HPF1_EN			BIT(20)
++#define CHNUM_SFT		(16)
++#define CHNUM_MASK		GENMASK(19, CHNUM_SFT)
++#define DMIC_SET_CHL(chl)	(((chl) - 1) << CHNUM_SFT)
++#define OSS_SFT			(12)
++#define OSS_MASK		GENMASK(13, OSS_SFT)
++#define OSS_16BIT		(0x0 << OSS_SFT)
++#define OSS_24BIT		(0x1 << OSS_SFT)
++#define DMIC_SET_OSS(x) ((x == 16) ? OSS_16BIT : (x == 24) ? OSS_24BIT : OSS_16BIT)
++#define SW_LR_SFT		(11)
++#define SW_LR			BIT(11)
++#define SR_SFT			(6)
++#define SR_MASK			GENMASK(8, SR_SFT)
++#define SR_8k			(0x0 << SR_SFT)
++#define SR_16k			(0x1 << SR_SFT)
++#define SR_48k			(0x2 << SR_SFT)
++#define SR_96k			(0x3 << SR_SFT)
++#define DMIC_SET_SR(r)	((r) == 8000 ? SR_8k : (r == 16000) ? SR_16k : (r == 48000) ? SR_48k : (r == 96000) ? SR_96k : SR_48k)
++#define DMIC_EN			BIT(0)
++
++/* DMIC_GCR */
++#define DGAIN_SFT		(0)
++#define DMIC_SET_GAIN(x)	((x) << DGAIN_SFT)
++
++#endif //__AS_DMIC_H__
+diff --git a/module_drivers/sound/soc/ingenic/as-v2/as-dsp.c b/module_drivers/sound/soc/ingenic/as-v2/as-dsp.c
+new file mode 100644
+index 000000000..585ea2b81
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v2/as-dsp.c
+@@ -0,0 +1,585 @@
++/*
++ * ALSA Soc Audio Layer -- ingenic as(audio system) dsp (dbus) driver
++ *
++ * Copyright 2017 - 2022 Ingenic Semiconductor Co.,Ltd
++ *	cli <chen.li@ingenic.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/list.h>
++#include <sound/soc.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/regmap.h>
++#include <linux/thermal.h>
++
++#include "as-dsp.h"
++
++
++/* Global variables */
++struct ingenic_as_dsp *as_dsp_t;
++
++#ifdef DEBUG
++static int ingenic_dsp_debug = 1;
++#else
++static int ingenic_dsp_debug = 0;
++#endif
++
++module_param(ingenic_dsp_debug, int, 0644);
++
++#define DSP_DEBUG_MSG(msg...)	\
++	do { \
++		if (ingenic_dsp_debug)	\
++			printk(KERN_DEBUG"DSP: " msg);	\
++	} while(0)
++
++
++static const char *const lo_names[LI_PORT_MAX_NUM] = {
++	"LO0_MUX", "LO1_MUX", "LO2_MUX", "LO3_MUX", "LO4_MUX",
++	"LO5_MUX", "LO6_MUX", "LO7_MUX", "LO8_MUX", "LO9_MUX",
++	"LO10_MUX", "LO11_MUX", "LO12_MUX", "LO13_MUX", "LO14_MUX",
++	"LO15_MUX"
++};
++
++#define LO_MUX_ITEMS_CNT	(LI_PORT_MAX_NUM + 1)
++static const char *const mux_item_names[LO_MUX_ITEMS_CNT] = {
++	"UNUSED", "LI0", "LI1", "LI2", "LI3", "LI4",
++	"LI5", "LI6", "LI7", "LI8", "LI9",
++	"LI10", "LI11", "LI12", "LI13", "LI14",
++	"LI15"
++};
++#define LO_PORT_NAME(num)	lo_names[num]
++#define LI_PORT_NAME(num)	mux_item_names[(num) + 1]
++#define ITEMS_TO_LI_DEVID(item)	(u8)(item != 0 ? (item) - 1 : LI_PORT_MAX_NUM)
++
++static struct ingenic_dsp_port *ingenic_dsp_get_port(struct ingenic_as_dsp *as_dsp,
++		u8 dev_id, bool is_out)
++{
++	int idx;
++
++	if (!as_dsp)
++		return NULL;
++
++	if (!is_out) {
++		if (unlikely(dev_id >= LI_PORT_MAX_NUM))
++			return NULL;
++		idx = LI_DEVID_TO_IDX(dev_id);
++	} else {
++		if (unlikely(dev_id >= LO_PORT_MAX_NUM))
++			return NULL;
++		idx = LO_DEVID_TO_IDX(dev_id);
++	}
++
++	if (as_dsp->port[idx].vaild)
++		return &as_dsp->port[idx];
++	else
++		return NULL;
++}
++
++static inline u8 ingenic_timeslot_alloc(struct ingenic_as_dsp *as_dsp)
++{
++	int id;
++	id = find_first_zero_bit(as_dsp->slot_bitmap, SLOT_NUM);
++	bitmap_set(as_dsp->slot_bitmap, id, 1);
++	return id + 1;	/*skip unused slot id 0*/
++}
++
++static inline void ingenic_timeslot_free(struct ingenic_as_dsp *as_dsp, u8 id)
++{
++	if (!id)  /*skip unused slot id 0*/
++		return;
++	bitmap_clear(as_dsp->slot_bitmap, (id - 1), 1);
++}
++
++/*Must under as_dsp mutex*/
++static void ingenic_dsp_free_timesolt(struct ingenic_as_dsp *as_dsp,
++		struct ingenic_as_dsp_enum *e)
++{
++	struct ingenic_dsp_port *lo, *li;
++	unsigned long reg, sft;
++
++	lo = ingenic_dsp_get_port(as_dsp, e->dev_id, true);
++	if (!lo || !lo->timeslot)
++		return;
++
++	/*clear target device timeslot*/
++	reg = ingenic_get_dsp_port_register(e->dev_id, &sft, true);
++	regmap_update_bits(as_dsp->regmap, reg, BSORTT_MSK(sft), 0);
++	lo->timeslot = 0;
++	list_del(&lo->node);
++
++	li = (struct ingenic_dsp_port *)lo->private;
++	if (li && list_empty(&li->head)) {
++		/*clear source device timeslot*/
++		reg = ingenic_get_dsp_port_register(li->dev_id, &sft, false);
++		regmap_update_bits(as_dsp->regmap, reg, BSORTT_MSK(sft), 0);
++
++		/*disable and free timeslot*/
++		regmap_update_bits(as_dsp->regmap, BTCLR, BT_TSLOT(li->timeslot), BT_TSLOT(li->timeslot));
++
++		ingenic_timeslot_free(as_dsp, li->timeslot);
++
++		li->timeslot = 0;
++	}
++	lo->private = NULL;
++}
++
++static void dump_dsp_register (struct ingenic_as_dsp *as_dsp)
++{
++	unsigned int val;
++
++	printk("==>DSP\n");
++	regmap_read(as_dsp->regmap, BTSR, &val);
++	printk ("BTSR(0x%x):	0x%x\n", BTSR, val);
++	regmap_read(as_dsp->regmap, BFSR, &val);
++	printk ("BFSR(0x%x):	0x%x\n", BFSR, val);
++	regmap_read(as_dsp->regmap, BFCR0, &val);
++	printk ("BFCR0(0x%x):	0x%x\n", BFCR0, val);
++	regmap_read(as_dsp->regmap, BFCR1, &val);
++	printk ("BFCR1(0x%x):	0x%x\n", BFCR1, val);
++	regmap_read(as_dsp->regmap, BFCR2, &val);
++	printk ("BFCR2(0x%x):	0x%x\n", BFCR2, val);
++	regmap_read(as_dsp->regmap, BST0, &val);
++	printk ("BST0(0x%x):	0x%x\n", BST0, val);
++	regmap_read(as_dsp->regmap, BST1, &val);
++	printk ("BST1(0x%x):	0x%x\n", BST1, val);
++	regmap_read(as_dsp->regmap, BST2, &val);
++	printk ("BST2(0x%x):	0x%x\n", BST2, val);
++	regmap_read(as_dsp->regmap, BTT0, &val);
++	printk ("BTT0(0x%x):	0x%x\n", BTT0, val);
++	regmap_read(as_dsp->regmap, BTT1, &val);
++	printk ("BTT1(0x%x):	0x%x\n", BTT1, val);
++}
++
++int ingenic_dsp_is_spdif_out(uint32_t dma_device_id)
++{
++	unsigned long reg, sft;
++	unsigned int val, dma_timeslot, spdif_out_timeslot;
++	unsigned int dev_id;
++	unsigned int spdif_out_id;
++	struct ingenic_as_dsp *as_dsp = as_dsp_t;
++
++	if (dma_device_id < 5) {
++		/* DMA0 ~ DMA4 */
++		dev_id = dma_device_id + 8;
++
++		/* spdif out*/
++		spdif_out_id = 2;
++
++		/* get DMA device timeslot */
++		reg = ingenic_get_dsp_port_register(dev_id, &sft, false);
++
++		regmap_read(as_dsp->regmap, reg, &val);
++		val &= BSORTT_MSK(sft);
++		val >>= sft;
++		dma_timeslot = val;
++
++
++		/* get spdif out timeslot */
++		reg = ingenic_get_dsp_port_register(spdif_out_id, &sft, true);
++
++		regmap_read(as_dsp->regmap, reg, &val);
++		val &= BSORTT_MSK(sft);
++		val >>= sft;
++		spdif_out_timeslot = val;
++
++
++		if ((dma_timeslot == spdif_out_timeslot) && dma_timeslot)
++			return 1;
++	}
++
++	return 0;
++}
++
++
++static int ingenic_dsp_request_timesolt(struct ingenic_as_dsp *as_dsp,
++		struct ingenic_as_dsp_enum *e, int item)
++{
++	struct ingenic_dsp_port *lo, *li;
++	unsigned long reg, sft;
++
++	/*zero is unused*/
++	if (item == 0)
++		return 0;
++
++	li = ingenic_dsp_get_port(as_dsp, ITEMS_TO_LI_DEVID(item), false);
++	lo = ingenic_dsp_get_port(as_dsp, e->dev_id, true);
++	if (!li || !lo) {
++		dev_err(as_dsp->dev, "request timeslot: get %s port(%u) failed\n",
++				li ? "lo" : "li", li ? e->dev_id : ITEMS_TO_LI_DEVID(item));
++		return -ENODEV;
++	}
++
++	if (WARN(lo->timeslot, "[as-dsp]request timeslot: lo port (%u)has been request\n",
++				e->dev_id))
++		return -EBUSY;
++
++	if (li->timeslot == 0) {
++		/*config bus source timeslot*/
++		li->timeslot = ingenic_timeslot_alloc(as_dsp);
++		reg = ingenic_get_dsp_port_register(li->dev_id, &sft, false);
++		regmap_update_bits(as_dsp->regmap, reg, BSORTT_MSK(sft), BSORTT(li->timeslot, sft));
++	}
++
++	/*config bus target timeslot*/
++	lo->timeslot = li->timeslot;
++	reg = ingenic_get_dsp_port_register(lo->dev_id, &sft, true);
++	regmap_update_bits(as_dsp->regmap, reg, BSORTT_MSK(sft), BSORTT(lo->timeslot, sft));
++
++	/*enable timeslot*/
++	regmap_update_bits(as_dsp->regmap, BTSET, BT_TSLOT(li->timeslot), BT_TSLOT(li->timeslot));
++
++	list_add_tail(&lo->node, &li->head);
++	lo->private = (void *)li;
++	return 0;
++}
++
++static int ingenic_lomux_dapm_get_enum(struct snd_kcontrol *kcontrol,
++		struct snd_ctl_elem_value *ucontrol)
++{
++	struct ingenic_as_dsp_enum *e = (struct ingenic_as_dsp_enum *)kcontrol->private_value;
++	ucontrol->value.enumerated.item[0] = e->value;
++	return 0;
++}
++
++static int ingenic_lomux_dapm_put_enum(struct snd_kcontrol *kcontrol,
++		struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
++	struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
++	struct ingenic_as_dsp *as_dsp = (struct ingenic_as_dsp *)snd_soc_component_get_drvdata(component);
++	struct ingenic_as_dsp_enum *e = (struct ingenic_as_dsp_enum *)kcontrol->private_value;
++	unsigned int item = ucontrol->value.enumerated.item[0];
++	unsigned int change = 0;
++
++	if (item >= e->e.items)
++		return -EINVAL;
++
++	mutex_lock(&as_dsp->dapm_mutex);
++	if (e->value != item) {
++		change = 1;
++		e->value = item;
++	}
++	if (change) {
++		/*free old timeslot*/
++		ingenic_dsp_free_timesolt(as_dsp, e);
++
++		/*alloc new timeslot*/
++		ingenic_dsp_request_timesolt(as_dsp, e, item);
++
++		snd_soc_dapm_mux_update_power(dapm, kcontrol, item, (struct soc_enum *)e, NULL);
++	}
++	mutex_unlock(&as_dsp->dapm_mutex);
++
++	return change;
++}
++
++static struct ingenic_as_dsp_enum lomux_enum[] = {	/*not const*/
++#define LOMUX_SOC_ENUM(_dev_id)	\
++	{ \
++		.e = SOC_ENUM_SINGLE_EXT(LO_MUX_ITEMS_CNT, mux_item_names),	\
++		.dev_id = _dev_id,	\
++		.value = 0,	\
++	}
++	LOMUX_SOC_ENUM(0),
++	LOMUX_SOC_ENUM(1),
++	LOMUX_SOC_ENUM(2),
++	LOMUX_SOC_ENUM(3),
++	LOMUX_SOC_ENUM(4),
++	LOMUX_SOC_ENUM(5),
++	LOMUX_SOC_ENUM(6),
++	LOMUX_SOC_ENUM(7),
++	LOMUX_SOC_ENUM(8),
++	LOMUX_SOC_ENUM(9),
++	LOMUX_SOC_ENUM(10),
++	LOMUX_SOC_ENUM(11),
++	LOMUX_SOC_ENUM(12),
++	LOMUX_SOC_ENUM(13),
++	LOMUX_SOC_ENUM(14),
++	LOMUX_SOC_ENUM(15),
++#undef LOMUX_SOC_ENUM
++};
++
++static const struct snd_kcontrol_new lomux_controls[] = {
++#define LOMUX_SOC_DAPM_ENUM_EXT(dev_id)	\
++	SOC_DAPM_ENUM_EXT("route", lomux_enum[(dev_id)], \
++			ingenic_lomux_dapm_get_enum, \
++			ingenic_lomux_dapm_put_enum)
++	LOMUX_SOC_DAPM_ENUM_EXT(0),
++	LOMUX_SOC_DAPM_ENUM_EXT(1),
++	LOMUX_SOC_DAPM_ENUM_EXT(2),
++	LOMUX_SOC_DAPM_ENUM_EXT(3),
++	LOMUX_SOC_DAPM_ENUM_EXT(4),
++	LOMUX_SOC_DAPM_ENUM_EXT(5),
++	LOMUX_SOC_DAPM_ENUM_EXT(6),
++	LOMUX_SOC_DAPM_ENUM_EXT(7),
++	LOMUX_SOC_DAPM_ENUM_EXT(8),
++	LOMUX_SOC_DAPM_ENUM_EXT(9),
++	LOMUX_SOC_DAPM_ENUM_EXT(10),
++	LOMUX_SOC_DAPM_ENUM_EXT(11),
++	LOMUX_SOC_DAPM_ENUM_EXT(12),
++	LOMUX_SOC_DAPM_ENUM_EXT(13),
++	LOMUX_SOC_DAPM_ENUM_EXT(14),
++	LOMUX_SOC_DAPM_ENUM_EXT(15),
++#undef LOMUX_SOC_DAPM_ENUM_EXT
++};
++
++static int ingenic_as_dsp_widget_event(struct snd_soc_dapm_widget* widget,
++		struct snd_kcontrol *kcontrol, int event)
++{
++	if (event == SND_SOC_DAPM_PRE_PMU) {
++		struct snd_soc_dapm_context *dapm = widget->dapm;
++		struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
++		struct ingenic_as_dsp *as_dsp = (struct ingenic_as_dsp *)snd_soc_component_get_drvdata(component);
++		int id , is_out = true;
++
++		if (widget->id == snd_soc_dapm_aif_in)
++			is_out = false;
++		id =  (int)widget->priv;
++		DSP_DEBUG_MSG("flush %s fifo %d \n", is_out ? "tx" : "rx", id);
++		regmap_update_bits(as_dsp->regmap, BFCR0, BFCR0_DEV_TF_MSK|BFCR0_DEV_RF_MSK,
++				is_out ? BFCR0_DEV_TF(id) : BFCR0_DEV_RF(id));
++	}
++	return 0;
++}
++
++static const char *const dai_name[] = {
++	"DMA0", "DMA1", "DMA2", "DMA3", "DMA4",
++	"DMA5", "DMA6", "DMA7", "DMA8", "DMA9"
++};
++
++static int ingenic_as_dsp_probe(struct platform_device *pdev)
++{
++	int ret, i, num_routes, num_widgets, num_dais, id;
++	struct ingenic_as_dsp *as_dsp;
++	struct resource *res;
++	struct property *prop;
++	const __be32 *p;
++	bool full_path = false;
++	struct snd_soc_dapm_route *dapm_routes;
++	struct snd_soc_dapm_widget *dapm_widgets;
++	struct snd_soc_dai_driver *fe_dais;
++	struct regmap_config regmap_config = {
++		.reg_bits = 32,
++		.reg_stride = 4,
++		.val_bits = 32,
++		.cache_type = REGCACHE_NONE,
++	};
++
++	as_dsp = devm_kzalloc(&pdev->dev, sizeof(struct ingenic_as_dsp), GFP_KERNEL);
++	if (!as_dsp)
++		return -ENOMEM;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	as_dsp->base_addr = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(as_dsp->base_addr))
++		return PTR_ERR(as_dsp->base_addr);
++	regmap_config.max_register = resource_size(res) - 0x4;
++	as_dsp->regmap = devm_regmap_init_mmio(&pdev->dev, as_dsp->base_addr,
++			&regmap_config);
++	if (IS_ERR(as_dsp->regmap))
++		return PTR_ERR(as_dsp->regmap);
++
++	as_dsp->dev = &pdev->dev;
++	mutex_init(&as_dsp->dapm_mutex);
++	bitmap_zero(as_dsp->slot_bitmap, SLOT_NUM);
++
++	/*init dsp port*/
++	for (i = 0; i < LI_PORT_MAX_NUM; i++) {
++		as_dsp->port[LI_DEVID_TO_IDX(i)].dev_id = i;
++		INIT_LIST_HEAD(&as_dsp->port[LI_DEVID_TO_IDX(i)].head);
++	}
++
++	for (i = 0; i < LO_PORT_MAX_NUM; i++) {
++		as_dsp->port[LO_DEVID_TO_IDX(i)].dev_id = i;
++		as_dsp->port[LO_DEVID_TO_IDX(i)].is_out = true;
++		INIT_LIST_HEAD(&as_dsp->port[LO_DEVID_TO_IDX(i)].node);
++	}
++
++	as_dsp->num_li_ports = of_property_count_u32_elems(pdev->dev.of_node, "ingenic,li-port");
++	if (as_dsp->num_li_ports <= 0 || as_dsp->num_li_ports > LI_PORT_MAX_NUM)
++		return -EINVAL;
++	as_dsp->num_lo_ports = of_property_count_u32_elems(pdev->dev.of_node, "ingenic,lo-port");
++	if (as_dsp->num_lo_ports <= 0 || as_dsp->num_lo_ports > LO_PORT_MAX_NUM)
++		return -EINVAL;
++
++	/*init widgets*/
++	num_widgets = as_dsp->num_li_ports + as_dsp->num_lo_ports;
++	dapm_widgets = devm_kzalloc(&pdev->dev,
++			sizeof(struct snd_soc_dapm_widget) * num_widgets,
++			GFP_KERNEL);
++	i = 0;
++	of_property_for_each_u32(pdev->dev.of_node, "ingenic,li-port", prop, p, id) {
++		dapm_widgets[i].id = snd_soc_dapm_aif_in;
++		dapm_widgets[i].name = LI_PORT_NAME(id);
++		dapm_widgets[i].reg = SND_SOC_NOPM;
++		dapm_widgets[i].event = ingenic_as_dsp_widget_event;
++		dapm_widgets[i].priv = (void *)id;
++		dapm_widgets[i++].event_flags = SND_SOC_DAPM_PRE_PMU;
++		as_dsp->port[LI_DEVID_TO_IDX(id)].vaild = true;
++	}
++	of_property_for_each_u32(pdev->dev.of_node, "ingenic,lo-port", prop, p, id) {
++		dapm_widgets[i].id = snd_soc_dapm_mux;
++		dapm_widgets[i].name = LO_PORT_NAME(id);
++		dapm_widgets[i].reg = SND_SOC_NOPM;
++		dapm_widgets[i].kcontrol_news = &lomux_controls[id];
++		dapm_widgets[i].num_kcontrols = 1;
++		dapm_widgets[i].event = ingenic_as_dsp_widget_event;
++		dapm_widgets[i].priv = (void *)id;
++		dapm_widgets[i++].event_flags = SND_SOC_DAPM_PRE_PMU;
++		as_dsp->port[LO_DEVID_TO_IDX(id)].vaild = true;
++	}
++
++	/*init routes*/
++	num_routes = of_property_count_strings(pdev->dev.of_node, "ingenic,routes");
++	num_routes /= 2;
++	if (num_routes <= 0 || num_routes & 0x1) {
++		full_path = true;
++		num_routes = as_dsp->num_li_ports * as_dsp->num_lo_ports;
++	}
++
++	dapm_routes = devm_kzalloc(&pdev->dev,
++			sizeof(struct snd_soc_dapm_route) * num_routes,
++			GFP_KERNEL);
++	if (!dapm_routes)
++		return -ENOMEM;
++
++	if (full_path) {
++		struct property *prop1;
++		const __be32 *p1;
++		int id1;
++		i = 0;
++		of_property_for_each_u32(pdev->dev.of_node, "ingenic,lo-port", prop, p, id) {
++			of_property_for_each_u32(pdev->dev.of_node, "ingenic,li-port", prop1, p1, id1) {
++				dapm_routes[i].source = dapm_routes[i].control = LI_PORT_NAME(id1);
++				dapm_routes[i++].sink = LO_PORT_NAME(id);
++			}
++		}
++	} else {
++		for (i = 0; i < num_routes; i++) {
++			of_property_read_string_index(pdev->dev.of_node, "ingenic,routes",
++					2 * i, &dapm_routes[i].sink);
++			of_property_read_string_index(pdev->dev.of_node, "ingenic,routes",
++					(2 * i) + 1, &dapm_routes[i].source);
++			dapm_routes[i].control = dapm_routes[i].source;
++		}
++	}
++
++	/*init component driver*/
++	as_dsp->cmpnt_drv.name = "ingenic-as-dsp";
++	as_dsp->cmpnt_drv.dapm_widgets = dapm_widgets;
++	as_dsp->cmpnt_drv.num_dapm_widgets = num_widgets;
++	as_dsp->cmpnt_drv.dapm_routes = dapm_routes;
++	as_dsp->cmpnt_drv.num_dapm_routes = num_routes;
++	platform_set_drvdata(pdev, as_dsp);
++
++	/* init global variables */
++	as_dsp_t = as_dsp;
++
++	/*init dais*/
++	if (of_property_read_u32(pdev->dev.of_node, "ingenic,num-dais", &num_dais))
++		return -ENODEV;
++
++	if (of_property_read_u32(pdev->dev.of_node, "ingenic,cap-dai-bm", &as_dsp->cap_dai_bitmsk))
++		return -ENODEV;
++
++	fe_dais =  devm_kzalloc(&pdev->dev, sizeof(*fe_dais) * num_dais, GFP_KERNEL);
++	if (!fe_dais)
++		return -ENOMEM;
++
++	for (i = 0; i < num_dais; i++) {
++		fe_dais[i].name = dai_name[i];
++		fe_dais[i].id = i;
++		if ((BIT(i) & as_dsp->cap_dai_bitmsk)) {
++			fe_dais[i].capture.stream_name = dai_name[i];
++			fe_dais[i].capture.channels_min = 1;
++			fe_dais[i].capture.channels_max = 12;
++			fe_dais[i].capture.rates = SNDRV_PCM_RATE_8000_192000;
++			fe_dais[i].capture.formats = ~0ULL;
++		} else {
++			fe_dais[i].playback.stream_name = dai_name[i];
++			fe_dais[i].playback.channels_min = 1;
++			fe_dais[i].playback.channels_max = 8;
++			fe_dais[i].playback.rates = SNDRV_PCM_RATE_8000_192000;
++			fe_dais[i].playback.formats = ~0ULL;
++		}
++	}
++
++	regmap_write(as_dsp->regmap, BFCR1, BFCR1_DEV_DBE_MSK);
++	regmap_write(as_dsp->regmap, BFCR2, BFCR2_DEV_DBE_MSK);
++
++	ret = snd_soc_register_component(&pdev->dev,
++			&as_dsp->cmpnt_drv,
++			fe_dais, num_dais);
++	if (ret)
++		return ret;
++
++	dev_info(&pdev->dev, "probe success!!\n");
++	return 0;
++}
++
++static int ingenic_as_dsp_remove(struct platform_device *pdev)
++{
++	snd_soc_unregister_component(&pdev->dev);
++	platform_set_drvdata(pdev, NULL);
++	return 0;
++}
++
++static const struct of_device_id ingenic_as_dsp_match_table[] = {
++	{ .compatible = "ingenic,as-dsp", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, ingenic_as_dsp_match_table);
++
++#ifdef CONFIG_PM
++static int ingenic_as_dsp_runtime_suspend(struct device *dev)
++{
++	return 0;
++}
++
++static int ingenic_as_dsp_runtime_resume(struct device *dev)
++{
++	return 0;
++}
++#endif
++
++static const struct dev_pm_ops ingenic_as_dsp_pm_ops = {
++	SET_RUNTIME_PM_OPS(ingenic_as_dsp_runtime_suspend,
++			ingenic_as_dsp_runtime_resume, NULL)
++};
++
++static struct platform_driver ingenic_as_dsp_platform_driver = {
++	.driver = {
++		.name = "as-dsp",
++		.of_match_table = ingenic_as_dsp_match_table,
++		.pm = &ingenic_as_dsp_pm_ops,
++	},
++	.probe = ingenic_as_dsp_probe,
++	.remove = ingenic_as_dsp_remove,
++};
++
++int ingenic_as_dsp_platform_driver_modinit(void)
++{
++	return platform_driver_register(&ingenic_as_dsp_platform_driver);
++}
++EXPORT_SYMBOL(ingenic_as_dsp_platform_driver_modinit);
++
++void ingenic_as_dsp_platform_driver_exit(void)
++{
++	platform_driver_unregister(&ingenic_as_dsp_platform_driver);
++}
++EXPORT_SYMBOL(ingenic_as_dsp_platform_driver_exit);
++
++
++/* module_platform_driver(ingenic_as_dsp_platform_driver); */
++
++MODULE_AUTHOR("cli <chen.li@ingenic.com>");
++MODULE_DESCRIPTION("Ingenic AS DSP SoC Interface");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-as-dsp");
+diff --git a/module_drivers/sound/soc/ingenic/as-v2/as-dsp.h b/module_drivers/sound/soc/ingenic/as-v2/as-dsp.h
+new file mode 100644
+index 000000000..bc157c8a6
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v2/as-dsp.h
+@@ -0,0 +1,150 @@
++/*
++ * ALSA Soc Audio Layer -- Ingenic AS DBUS Controller
++ *
++ * Copyright 2017 - 2022 Ingenic Semiconductor Co.,Ltd
++ *	cli <chen.li@ingenic.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#ifndef __AS_FE_DSP_H__
++#define __AS_FE_DSP_H__
++
++#include <linux/bitops.h>
++/* BUS */
++#define BTSET		0x0	/* BUS TimeSlot Set Register */
++#define BTCLR		0x4	/* BUS TimeSlot Clear Register */
++#define BTSR		0x8	/* BUS TimeSlot Status Register */
++#define BFSR		0xc	/* BUS FIFO Status Register(TUR/ROR)*/
++#define BFCR0		0x10	/* BUS FIFO Control Register0(FLUSH FIFO)*/
++#define BFCR1		0X14	/* BUS FIFO Control Register1(TX ZERO SAMPLE<underrun>)*/
++#define BFCR2		0x18	/* BUS FIFO Control Register2(BLOKING RX FIFO<overrun>)*/
++#define BST0		0x1c	/* BUS Source Timeslot0 */
++#define BST1		0x20	/* BUS Source Timeslot1 */
++#define BST2		0x24	/* BUS Source Timeslot2 */
++#define BTT0		0x28	/* BUS Target Timeslot0 */
++#define BTT1		0x2c	/* BUS Target Timeslot1 */
++
++#define BT_TSLOT(slot)	BIT(slot)
++
++#define BFSR_DEV_TUR_SFT	(16)
++#define BFSR_DEV_TUR(lo_dev_id)	BIT(((lo_dev_id) + BFSR_DEV_TUR_SFT))
++#define BFSR_DEV_ROR_SFT	(0)
++#define BFSR_DEV_ROR(li_dev_id)	BIT(((li_dev_id) + BFSR_DEV_ROR_SFT))
++
++#define	BFCR0_DEV_TF_SFT	(16)
++#define BFCR0_DEV_TF_MSK	GENMASK(31, BFCR0_DEV_TF_SFT)
++#define	BFCR0_DEV_TF(lo_dev_id)	BIT(((lo_dev_id) + BFCR0_DEV_TF_SFT))
++#define BFCR0_DEV_RF_SFT	(0)
++#define BFCR0_DEV_RF_MSK	GENMASK(15, BFCR0_DEV_RF_SFT)
++#define BFCR0_DEV_RF(li_dev_id)	BIT(((li_dev_id) + BFCR0_DEV_RF_SFT))
++
++#define BFCR1_DEV_DBE_MSK	GENMASK(11, 0)
++#define BFCR1_DEV_LSMP(lo_dev_id)	BIT(lo_dev_id)
++
++#define BFCR2_DEV_DBE_MSK	GENMASK(14, 0)
++#define BFCR2_DEV_DBE(li_dev_id)	BIT(li_dev_id)
++
++#define BST0_DEV0_SUR_SFT	(0)
++#define BST0_DEV1_SUR_SFT	(5)
++#define BST0_DEV2_SUR_SFT	(10)
++#define BST0_DEV3_SUR_SFT	(16)
++#define BST0_DEV4_SUR_SFT	(21)
++#define BST0_DEV5_SUR_SFT	(26)
++
++#define BST1_DEV6_SUR_SFT	(0)
++#define BST1_DEV7_SUR_SFT	(5)
++#define BST1_DEV8_SUR_SFT	(10)
++#define BST1_DEV9_SUR_SFT	(16)
++#define BST1_DEV10_SUR_SFT	(21)
++
++#define BST2_DEV11_SUR_SFT	(0)
++#define BST2_DEV12_SUR_SFT	(5)
++#define BST2_DEV13_SUR_SFT	(10)
++#define BST2_DEV14_SUR_SFT	(16)
++
++#define BTT0_DEV0_TAR_SFT	(0)
++#define BTT0_DEV1_TAR_SFT	(5)
++#define BTT0_DEV2_TAR_SFT	(10)
++#define BTT0_DEV3_TAR_SFT	(16)
++#define BTT0_DEV4_TAR_SFT	(21)
++#define BTT0_DEV5_TAR_SFT	(26)
++
++#define BTT1_DEV6_TAR_SFT	(0)
++#define BTT1_DEV7_TAR_SFT	(5)
++#define BTT1_DEV8_TAR_SFT	(10)
++#define BTT1_DEV9_TAR_SFT	(16)
++#define BTT1_DEV10_TAR_SFT	(21)
++#define BTT1_DEV11_TAR_SFT	(26)
++
++#define BSORTT_WITDH		(5)
++#define BSORTT_MSK(shift)	GENMASK(((shift) + BSORTT_WITDH - 1), shift)
++#define BSORTT(slot, shift)	(((slot) << (shift)) & BSORTT_MSK(shift))
++
++static inline unsigned long ingenic_get_dsp_port_register(int dev_id,
++		unsigned long *shift, bool is_out)
++{
++	if (is_out) {
++		u8 reg[12] = {BTT0, BTT0, BTT0, BTT0, BTT0, BTT0,
++			BTT1, BTT1, BTT1, BTT1, BTT1, BTT1};
++		u8 sft[12] = {BTT0_DEV0_TAR_SFT, BTT0_DEV1_TAR_SFT, BTT0_DEV2_TAR_SFT,
++			BTT0_DEV3_TAR_SFT, BTT0_DEV4_TAR_SFT, BTT0_DEV5_TAR_SFT,
++			BTT1_DEV6_TAR_SFT, BTT1_DEV7_TAR_SFT, BTT1_DEV8_TAR_SFT,
++			BTT1_DEV9_TAR_SFT, BTT1_DEV10_TAR_SFT, BTT1_DEV11_TAR_SFT};
++		*shift = (unsigned long)sft[dev_id];
++		return (unsigned long)reg[dev_id];
++	} else {
++		u8 reg[15]  = {BST0, BST0, BST0, BST0, BST0, BST0,
++			BST1, BST1, BST1, BST1, BST1,
++			BST2, BST2, BST2, BST2};
++		u8 sft[15] = {BST0_DEV0_SUR_SFT, BST0_DEV1_SUR_SFT, BST0_DEV2_SUR_SFT,
++			BST0_DEV3_SUR_SFT, BST0_DEV4_SUR_SFT, BST0_DEV5_SUR_SFT,
++			BST1_DEV6_SUR_SFT, BST1_DEV7_SUR_SFT, BST1_DEV8_SUR_SFT,
++			BST1_DEV9_SUR_SFT, BST1_DEV10_SUR_SFT, BST2_DEV11_SUR_SFT,
++			BST2_DEV12_SUR_SFT, BST2_DEV13_SUR_SFT, BST2_DEV14_SUR_SFT
++		};
++		*shift = (unsigned long)sft[dev_id];
++		return (unsigned long)reg[dev_id];
++	}
++}
++
++struct ingenic_dsp_port {
++	union {
++		struct list_head node;	/* for lineout*/
++		struct list_head head;	/* for linein */
++	};
++	u8 dev_id;			/*port id*/
++	u8 timeslot;
++	bool is_out;
++	bool vaild;
++	void *private;
++};
++
++#define LI_PORT_MAX_NUM 16
++#define LO_PORT_MAX_NUM 16
++#define PORT_MAX_NUM (LI_PORT_MAX_NUM + LO_PORT_MAX_NUM)
++
++struct ingenic_as_dsp {
++	void * __iomem base_addr;
++	struct regmap *regmap;
++	struct device *dev;
++#define SLOT_NUM (31)
++	unsigned long slot_bitmap[BITS_TO_LONGS(SLOT_NUM)];
++#define LI_DEVID_TO_IDX(dev_id)	(dev_id)
++#define LO_DEVID_TO_IDX(dev_id)	((dev_id) + LI_PORT_MAX_NUM)
++	struct ingenic_dsp_port port[PORT_MAX_NUM];
++	int num_li_ports;
++	int num_lo_ports;
++	struct snd_soc_component_driver cmpnt_drv;
++	struct mutex dapm_mutex;
++	u32 cap_dai_bitmsk;
++};
++
++struct ingenic_as_dsp_enum {
++	struct soc_enum e;
++	u8 dev_id;
++	int value;
++};
++#endif	/*__AS_FE_DSP_H__*/
+diff --git a/module_drivers/sound/soc/ingenic/as-v2/as-fmtcov.c b/module_drivers/sound/soc/ingenic/as-v2/as-fmtcov.c
+new file mode 100644
+index 000000000..a0dabaec2
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v2/as-fmtcov.c
+@@ -0,0 +1,187 @@
++/*
++ * ALSA Soc Audio Layer -- Ingenic AS fmtcov driver
++ *
++ * Copyright 2017 - 2022 Ingenic Semiconductor Co.,Ltd
++ *	wqshao <wangquan.shao@ingenic.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/list.h>
++#include <sound/soc.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <sound/pcm_params.h>
++#include "as-fmtcov.h"
++#include "as-dma.h"
++
++#ifdef DEBUG
++static int ingenic_fmtcov_debug = 1;
++#else
++static int ingenic_fmtcov_debug = 0;
++#endif
++module_param(ingenic_fmtcov_debug, int, 0644);
++#define FMTCOV_DEBUG_MSG(msg...)				\
++	do {                        				\
++		if (ingenic_fmtcov_debug)				\
++			printk(KERN_DEBUG"FMTCOV: " msg);	\
++	} while(0)
++
++static struct ingenic_as_fmtcov *as_fmtcov;
++
++static bool ingenic_fmt_need_packen(snd_pcm_format_t format)
++{
++	switch (format) {
++	case SNDRV_PCM_FORMAT_S24_3LE:
++	case SNDRV_PCM_FORMAT_U24_3LE:
++	case SNDRV_PCM_FORMAT_S20_3LE:
++	case SNDRV_PCM_FORMAT_U20_3LE:
++	case SNDRV_PCM_FORMAT_S18_3LE:
++	case SNDRV_PCM_FORMAT_U18_3LE:
++	case SNDRV_PCM_FORMAT_S24_3BE:
++	case SNDRV_PCM_FORMAT_U24_3BE:
++	case SNDRV_PCM_FORMAT_S20_3BE:
++	case SNDRV_PCM_FORMAT_U20_3BE:
++	case SNDRV_PCM_FORMAT_S18_3BE:
++	case SNDRV_PCM_FORMAT_U18_3BE:
++		return true;
++	default:
++		break;
++	}
++
++	return false;
++}
++
++static void ingenic_as_fmtcov_fix_match_mod(u8 dai_id, u32 fmtcfg)
++{
++	as_fmtcov->fmtcfg[dai_id] = fmtcfg;
++}
++
++int ingenic_spdif_fmtcov_be_fix(struct snd_pcm_substream *substream,
++		struct snd_pcm_hw_params *params)
++{
++	struct ingenic_as_dma_runtime *prtd = substream_to_prtd(substream);
++	u32 fmtcfg = 0;
++
++	if (WARN(prtd->dai_id > FMT_CHL_NUM, "[as-fmtcov]: %s dai_id(%d) out of range\n",
++				__func__, prtd->dai_id))
++		return -ECHRNG;
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		fmtcfg = DFCR_SS(params_width(params)) | DFCR_CHNUM(1);
++	} else {
++		fmtcfg = DFCR_SS(32) | DFCR_CHNUM(1);
++	}
++	if (ingenic_fmt_need_packen(params_format(params)))
++		fmtcfg |= DFCR_PACKEN;
++
++	ingenic_as_fmtcov_fix_match_mod(prtd->dai_id, fmtcfg);
++	return 0;
++}
++EXPORT_SYMBOL_GPL(ingenic_spdif_fmtcov_be_fix);
++
++int ingenic_as_fmtcov_cfg(struct snd_pcm_substream *substream,
++		struct snd_pcm_hw_params *params)
++{
++	struct ingenic_as_dma_runtime *prtd = substream_to_prtd(substream);
++	u32 fmtcfg;
++
++	if (WARN(prtd->dai_id > FMT_CHL_NUM, "[as-fmtcov]: %s dai_id(%d) out of range\n",
++				__func__, prtd->dai_id))
++		return -ECHRNG;
++
++	fmtcfg = DFCR_SS(params_width(params)) | DFCR_CHNUM(params_channels(params));
++	if (ingenic_fmt_need_packen(params_format(params)))
++		fmtcfg |= DFCR_PACKEN;
++
++	if (as_fmtcov->fmtcfg[prtd->dai_id]) {
++		fmtcfg = as_fmtcov->fmtcfg[prtd->dai_id];
++		as_fmtcov->fmtcfg[prtd->dai_id] = 0;
++	}
++
++	FMTCOV_DEBUG_MSG("enter %s, fmtcov DFCR%d = 0x%08x\n", __func__, prtd->dai_id, fmtcfg);
++	writel_relaxed(fmtcfg, as_fmtcov->io_base + DFCR(prtd->dai_id));
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(ingenic_as_fmtcov_cfg);
++
++void ingenic_as_fmtcov_enable(u8 dai_id, bool enable)
++{
++	regmap_update_bits(as_fmtcov->regmap, DFCR(dai_id), DFCR_ENABLE, enable ? DFCR_ENABLE : 0);
++}
++EXPORT_SYMBOL_GPL(ingenic_as_fmtcov_enable);
++
++static int ingenic_as_fmtcov_platform_probe(struct platform_device *pdev)
++{
++	struct resource *res;
++	struct regmap_config regmap_config = {
++		.reg_bits = 32,
++		.reg_stride = 4,
++		.val_bits = 32,
++		.cache_type = REGCACHE_NONE,
++	};
++
++	as_fmtcov = devm_kzalloc(&pdev->dev, sizeof(struct ingenic_as_fmtcov), GFP_KERNEL);
++	if (!as_fmtcov)
++		return -ENOMEM;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	as_fmtcov->io_base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(as_fmtcov->io_base))
++		return PTR_ERR(as_fmtcov->io_base);
++	regmap_config.max_register = resource_size(res) - 0x4;
++	as_fmtcov->regmap = devm_regmap_init_mmio(&pdev->dev, as_fmtcov->io_base,
++			&regmap_config);
++	if (IS_ERR(as_fmtcov->regmap))
++		return PTR_ERR(as_fmtcov->regmap);
++	as_fmtcov->dev = &pdev->dev;
++
++	platform_set_drvdata(pdev, as_fmtcov);
++	return 0;
++}
++
++static int ingenic_as_fmtcov_platform_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id ingenic_as_fmtcov_match_table[] = {
++	{ .compatible = "ingenic,as-fmtcov", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, ingenic_as_fmtcov_match_table);
++
++static struct platform_driver ingenic_as_fmtcov_platform_driver = {
++	.driver = {
++		.name = "as-fmtcov",
++		.of_match_table = ingenic_as_fmtcov_match_table,
++	},
++	.probe = ingenic_as_fmtcov_platform_probe,
++	.remove = ingenic_as_fmtcov_platform_remove,
++};
++
++int ingenic_as_fmtcov_platform_driver_modinit(void)
++{
++	return platform_driver_register(&ingenic_as_fmtcov_platform_driver);
++}
++EXPORT_SYMBOL(ingenic_as_fmtcov_platform_driver_modinit);
++
++void ingenic_as_fmtcov_platform_driver_exit(void)
++{
++	platform_driver_unregister(&ingenic_as_fmtcov_platform_driver);
++}
++EXPORT_SYMBOL(ingenic_as_fmtcov_platform_driver_exit);
++
++
++
++/* module_platform_driver(ingenic_as_fmtcov_platform_driver); */
++
++MODULE_AUTHOR("wqshao <wangquan.shao@ingenic.com>");
++MODULE_DESCRIPTION("Ingenic AS fmtcov SoC Interface");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-as-fmtcov");
+diff --git a/module_drivers/sound/soc/ingenic/as-v2/as-fmtcov.h b/module_drivers/sound/soc/ingenic/as-v2/as-fmtcov.h
+new file mode 100644
+index 000000000..8a0db3bee
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v2/as-fmtcov.h
+@@ -0,0 +1,57 @@
++/*
++ * ALSA Soc Audio Layer -- Ingenic AS fmtcov driver
++ *
++ * Copyright 2017 - 2022 Ingenic Semiconductor Co.,Ltd
++ *	wqshao <wangquan.shao@ingenic.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#ifndef __AS_fmtcov__
++#define __AS_fmtcov__
++
++#include <linux/bitops.h>
++
++int ingenic_spdif_fmtcov_be_fix(struct snd_pcm_substream *substream,
++		struct snd_pcm_hw_params *params);
++
++int ingenic_as_fmtcov_cfg(struct snd_pcm_substream *substream,
++		struct snd_pcm_hw_params *params);
++void ingenic_as_fmtcov_enable(u8 dai_id, bool enable);
++
++struct ingenic_as_fmtcov {
++	struct regmap *regmap;
++	struct device *dev;
++	void *__iomem io_base;
++	u8 dai_id;
++#define FMT_CHL_NUM 10
++	u32 fmtcfg[FMT_CHL_NUM];
++	uint32_t fmtcov_bitmask;
++};
++
++/* FORMAT */
++#define DFCR0	(0x0)
++
++#define FMTCOV_OFFSET	(0x4)
++#define DFCR(n)	((n) * FMTCOV_OFFSET + DFCR0)
++
++#define DFCR_CHNUM_SFT	(12)
++#define DFCR_CHNUM_MSK	GENMASK(15, DFCR_CHNUM_SFT)
++#define DFCR_CHNUM(ch)	((((!((ch) % 2) || ((ch) == 1)) ? ((ch) - 1) : (ch)) << DFCR_CHNUM_SFT) & DFCR_CHNUM_MSK)
++#define DFCR_SS_SFT	(8)
++#define DFCR_SS_MSK	GENMASK(10, DFCR_SS_SFT)
++#define DFCR_SS_8	(0 << DFCR_SS_SFT)
++#define DFCR_SS_12	(1 << DFCR_SS_SFT)
++#define DFCR_SS_13	(2 << DFCR_SS_SFT)
++#define DFCR_SS_16	(3 << DFCR_SS_SFT)
++#define DFCR_SS_18	(4 << DFCR_SS_SFT)
++#define DFCR_SS_20	(5 << DFCR_SS_SFT)
++#define DFCR_SS_24	(6 << DFCR_SS_SFT)
++#define DFCR_SS_32	(7 << DFCR_SS_SFT)
++#define DFCR_SS(ss)	((ss <= 8) ? DFCR_SS_8 : (ss <= 12) ? DFCR_SS_12 : (ss == 13) ? DFCR_SS_13 : (ss <= 16) ? DFCR_SS_16 : (ss <= 18) ? DFCR_SS_18 : (ss <= 20) ? DFCR_SS_20 : (ss <= 24) ? DFCR_SS_24: DFCR_SS_32)
++#define DFCR_PACKEN	BIT(2)
++#define DFCR_ENABLE	BIT(0)
++
++#endif /*__AS_fmtcov__*/
+diff --git a/module_drivers/sound/soc/ingenic/as-v2/as-mixer.c b/module_drivers/sound/soc/ingenic/as-v2/as-mixer.c
+new file mode 100644
+index 000000000..648b8c0bc
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v2/as-mixer.c
+@@ -0,0 +1,186 @@
++/*
++ * ALSA Soc Audio Layer -- Ingenic AS MIXER driver
++ *
++ * Copyright 2017 - 2022 Ingenic Semiconductor Co.,Ltd
++ *	cli <chen.li@ingenic.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/list.h>
++#include <sound/soc.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include "as-mixer.h"
++
++static int ingenic_as_mixer_widget_event(struct snd_soc_dapm_widget* widget,
++		struct snd_kcontrol *kcontrol, int event)
++{
++	if (event == SND_SOC_DAPM_PRE_PMU) {
++		struct snd_soc_dapm_context *dapm = widget->dapm;
++		struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
++		struct ingenic_as_mixer *as_mixer = (struct ingenic_as_mixer *)
++			snd_soc_component_get_drvdata(component);
++		int id =  (int)widget->priv;
++		dev_dbg(as_mixer->dev, "reset mixer[%d]\n", id);
++		regmap_update_bits(as_mixer->regmap, MIX_CTL(id), MIX_RESET, MIX_RESET);
++	}
++	return 0;
++}
++
++static int ingenic_as_mixer_probe(struct snd_soc_component *cmpnt)
++{
++	struct ingenic_as_mixer *as_mixer = dev_get_drvdata(cmpnt->dev);
++	int i;
++
++	for (i = 0; i < as_mixer->num_mixers; i++) {
++		snd_soc_component_update_bits(cmpnt, MIX_CFG(i),
++				MIX_CH_MSK|MIX_MODE_MSK, MIX_CH(2)|MIX_MODE_AVG);
++	}
++	return 0;
++}
++
++static const char * const ingenic_mixer0_mode_src[] = {
++	"Linear weighted plus",
++	"Average",
++	"Clamping",
++	"Nonlinear Distort",
++};
++
++static int ingenic_mixer0_mode_values[] = {
++	0, 1, 2, 3,
++};
++
++static SOC_VALUE_ENUM_SINGLE_DECL(ingenic_mixer0_mode,
++		MIX_CFG(0), MIX_MODE_SFT,
++		0x3, ingenic_mixer0_mode_src,
++		ingenic_mixer0_mode_values);
++
++static const struct snd_kcontrol_new ingenic_mixer_controls[] = {
++	/* Mixer0 */
++	SOC_SINGLE("Mixer0 LR_MIX Switch", MIX_CFG(0), MIX_LR_MIX_SFT, 1, 0),
++	SOC_ENUM("Mixer0 MIX_MODE Option", ingenic_mixer0_mode),
++};
++
++static int ingenic_as_mixer_platform_probe(struct platform_device *pdev)
++{
++	struct ingenic_as_mixer *as_mixer;
++	struct resource *res;
++	struct snd_soc_dapm_widget *dapm_widgets;
++	char *dev_name;
++	int i, ret;
++	struct regmap_config regmap_config = {
++		.reg_bits = 32,
++		.reg_stride = 4,
++		.val_bits = 32,
++		.cache_type = REGCACHE_NONE,
++	};
++
++	as_mixer = devm_kzalloc(&pdev->dev, sizeof(struct ingenic_as_mixer), GFP_KERNEL);
++	if (!as_mixer)
++		return -ENOMEM;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	as_mixer->io_base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(as_mixer->io_base))
++		return PTR_ERR(as_mixer->io_base);
++	regmap_config.max_register = resource_size(res) - 0x4;
++	as_mixer->regmap = devm_regmap_init_mmio(&pdev->dev, as_mixer->io_base,
++			&regmap_config);
++	if (IS_ERR(as_mixer->regmap))
++		return PTR_ERR(as_mixer->regmap);
++	as_mixer->dev = &pdev->dev;
++
++	if (of_property_read_u32(pdev->dev.of_node, "ingenic,num-mixers",
++				&as_mixer->num_mixers))
++		return -ENODEV;
++
++	dapm_widgets = devm_kzalloc(&pdev->dev,
++			sizeof(struct snd_soc_dapm_widget) * as_mixer->num_mixers,
++			GFP_KERNEL);
++	if (!dapm_widgets)
++		return -ENOMEM;
++
++#define NAME_LEN 10
++	dev_name = devm_kzalloc(&pdev->dev,
++			sizeof(char)*as_mixer->num_mixers*NAME_LEN,
++			GFP_KERNEL);
++	if (!dev_name)
++		return -ENOMEM;
++
++	for (i = 0; i < as_mixer->num_mixers; i++) {
++		dapm_widgets[i].id = snd_soc_dapm_mixer;
++		snprintf(&dev_name[i * NAME_LEN], NAME_LEN, "MIX%d", i);
++		dapm_widgets[i].name = &dev_name[i * NAME_LEN];
++		dapm_widgets[i].reg = MIX_CTL(i);
++		dapm_widgets[i].mask = 1;
++		dapm_widgets[i].shift = MIX_EN_SFT;
++		dapm_widgets[i].on_val = 1;
++		dapm_widgets[i].event = ingenic_as_mixer_widget_event;
++		dapm_widgets[i].priv = (void *)i;
++		dapm_widgets[i++].event_flags = SND_SOC_DAPM_PRE_PMU;
++	}
++#undef  NAME_LEN
++
++	as_mixer->cmpnt_drv.name = "ingenic-as-mixer";
++	as_mixer->cmpnt_drv.controls = ingenic_mixer_controls;
++	as_mixer->cmpnt_drv.num_controls = ARRAY_SIZE(ingenic_mixer_controls);
++	as_mixer->cmpnt_drv.dapm_widgets = dapm_widgets;
++	as_mixer->cmpnt_drv.num_dapm_widgets = as_mixer->num_mixers;
++	as_mixer->cmpnt_drv.probe = ingenic_as_mixer_probe;
++
++	platform_set_drvdata(pdev, as_mixer);
++
++	ret = snd_soc_register_component(&pdev->dev, &as_mixer->cmpnt_drv,
++			NULL, 0);
++	if (!ret)
++		dev_info(&pdev->dev, "amixer platform probe success\n");
++
++	return ret;
++}
++
++static int ingenic_as_mixer_platform_remove(struct platform_device *pdev)
++{
++	snd_soc_unregister_component(&pdev->dev);
++	return 0;
++}
++
++static const struct of_device_id ingenic_as_mixer_match_table[] = {
++	{ .compatible = "ingenic,as-mixer", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, ingenic_as_mixer_match_table);
++
++static struct platform_driver ingenic_as_mixer_platform_driver = {
++	.driver = {
++		.name = "as-mixer",
++		.of_match_table = ingenic_as_mixer_match_table,
++	},
++	.probe = ingenic_as_mixer_platform_probe,
++	.remove = ingenic_as_mixer_platform_remove,
++};
++
++int ingenic_as_mixer_platform_driver_modinit(void)
++{
++	return platform_driver_register(&ingenic_as_mixer_platform_driver);
++}
++EXPORT_SYMBOL(ingenic_as_mixer_platform_driver_modinit);
++
++void ingenic_as_mixer_platform_driver_exit(void)
++{
++	platform_driver_unregister(&ingenic_as_mixer_platform_driver);
++}
++EXPORT_SYMBOL(ingenic_as_mixer_platform_driver_exit);
++
++
++
++/* module_platform_driver(ingenic_as_mixer_platform_driver); */
++
++MODULE_AUTHOR("cli <chen.li@ingenic.com>");
++MODULE_DESCRIPTION("Ingenic AS Mixer SoC Interface");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-as-mixer");
+diff --git a/module_drivers/sound/soc/ingenic/as-v2/as-mixer.h b/module_drivers/sound/soc/ingenic/as-v2/as-mixer.h
+new file mode 100644
+index 000000000..1df0b72ff
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v2/as-mixer.h
+@@ -0,0 +1,50 @@
++/*
++ * ALSA Soc Audio Layer -- Ingenic AS MIXER driver
++ *
++ * Copyright 2017 - 2022 Ingenic Semiconductor Co.,Ltd
++ *	cli <chen.li@ingenic.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#ifndef __AS_MIXER__
++#define __AS_MIXER__
++
++#include <linux/bitops.h>
++
++#define MIX_OFF		(0x4)
++#define MIX_CTL0	(0x0)
++#define MIX_CFG0	(0x4)
++
++#define MIX_CTL(n)	(MIX_CTL0 + (n) * MIX_OFF)
++#define MIX_CFG(n)	(MIX_CFG0 + (n) * MIX_OFF)
++
++#define MIX_RESET	BIT(1)
++#define MIX_EN_SFT	(0)
++#define MIX_EN		BIT(MIX_EN_SFT)
++
++#define MIX_CH_SFT	(5)
++#define MIX_CH_MSK	GENMASK(6, MIX_CH_SFT)
++#define MIX_CH(n)	((((n) - 1) << MIX_CH_SFT) & MIX_CH_MSK)
++
++#define MIX_MODE_SFT	(3)
++#define MIX_MODE_MSK	GENMASK(4, MIX_MODE_SFT)
++#define MIX_MODE_LWP	(0 << MIX_MODE_SFT)
++#define MIX_MODE_AVG	(1 << MIX_MODE_SFT)
++#define MIX_MODE_CLMP	(2 << MIX_MODE_SFT)
++#define MIX_MODE_NOL	(3 << MIX_MODE_SFT)
++
++#define MIX_LR_MIX_SFT	(1)
++#define MIX_LR_MIX		BIT(MIX_LR_MIX_SFT)
++#define MIX_LAST_SMP	BIT(0)
++
++struct ingenic_as_mixer {
++	struct regmap *regmap;
++	struct device *dev;
++	void *__iomem io_base;
++	u32 num_mixers;
++	struct snd_soc_component_driver cmpnt_drv;
++};
++#endif /*__AS_MIXER__*/
+diff --git a/module_drivers/sound/soc/ingenic/as-v2/as-spdif.c b/module_drivers/sound/soc/ingenic/as-v2/as-spdif.c
+new file mode 100644
+index 000000000..ebd1a8928
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v2/as-spdif.c
+@@ -0,0 +1,445 @@
++/*
++ * ALSA Soc Audio Layer -- ingenic as(audio system) spdif(Basic Audio Inter-
++ * face Controller) driver
++ *
++ * Copyright 2017 - 2022 Ingenic Semiconductor Co.,Ltd
++ *   wqshao <wangquan.shao@ingenic.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/initval.h>
++#include <sound/soc.h>
++#include <sound/soc-dai.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++#include <linux/types.h>
++#include <linux/clk.h>
++
++#include "as-spdif.h"
++
++#ifdef DEBUG
++static int ingenic_spdif_debug = 1;
++#else
++static int ingenic_spdif_debug = 0;
++#endif
++module_param(ingenic_spdif_debug, int, 0644);
++#define SPDIF_DEBUG_MSG(msg...)					\
++	do {										\
++		if (ingenic_spdif_debug)				\
++			printk("SPDIF: " msg);				\
++	} while(0)
++
++int __attribute__((weak)) ingenic_spdif_fmtcov_be_fix(struct snd_pcm_substream *substream,
++		struct snd_pcm_hw_params *params)
++{
++	return 0;
++}
++
++static int ingenic_spdif_startup(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct ingenic_spdif *spdif = dev_get_drvdata(dai->dev);
++	u32 ch_cfg;
++
++	SPDIF_DEBUG_MSG("enter %s, substream = %s\n",__func__,
++			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
++			"playback" : "capture");
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		regmap_update_bits(spdif->spdif_out_regmap, SPCFG2,
++				SPO_AUDIO_N|SPO_CON_PRO, spdif->non_pcm ? SPO_AUDIO_N : 0);
++		if (!spdif->non_pcm) {
++			ch_cfg = SPO_SET_SCR_NUM(1) | SPO_SET_CH1_NUM(1) | SPO_SET_CH2_NUM(1);
++			regmap_update_bits(spdif->spdif_out_regmap, SPCFG1,
++					SPO_SCR_NUM_MASK|SPO_CH1_NUM_MASK|SPO_CH2_NUM_MASK, ch_cfg);
++			regmap_update_bits(spdif->spdif_out_regmap, SPCFG2,
++					SPO_CAT_CODE_MASK|SPO_CH_MD_MASK, SPO_CAT_CODE_GEN|SPO_CH_MD_0);
++		}
++		regmap_update_bits(spdif->spdif_out_regmap, SPCTRL, SPO_INVALID, 0);
++	}
++
++	return 0;
++}
++
++static int ingenic_spdif_start_substream(struct snd_pcm_substream *substream,
++		struct ingenic_spdif *spdif)
++{
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++		regmap_write(spdif->spdif_out_regmap, SPENA, SPO_SPEN);
++	else {
++		regmap_update_bits(spdif->spdif_in_regmap, SPIENA, SPI_SPIEN, SPI_SPIEN);
++		ndelay(200);
++		regmap_update_bits(spdif->spdif_in_regmap, SPIENA, SPI_RESET, SPI_RESET);
++	}
++
++	return 0;
++}
++
++static int ingenic_spdif_stop_substream(struct snd_pcm_substream *substream,
++		struct ingenic_spdif *spdif)
++{
++	u32 val, timeout = 0xfff;
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		regmap_write(spdif->spdif_out_regmap, SPENA, 0);
++		do {
++			regmap_read(spdif->spdif_out_regmap, SPENA, &val);
++		} while((val & SPO_SPEN) && --timeout);
++		if (!timeout)
++			goto error;
++	} else {
++		regmap_update_bits(spdif->spdif_in_regmap, SPIENA, SPI_RESET, SPI_RESET);
++		ndelay(200);
++		regmap_update_bits(spdif->spdif_in_regmap, SPIENA, SPI_SPIEN, 0);
++	}
++
++	return 0;
++error:
++	pr_err("[ERROR]: %s,%d disable fail ...\n", __func__, __LINE__);
++	return -EIO;
++}
++
++static int ingenic_spdif_trigger(struct snd_pcm_substream *substream,
++		int cmd, struct snd_soc_dai *dai)
++{
++	struct ingenic_spdif *spdif = dev_get_drvdata(dai->dev);
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		SPDIF_DEBUG_MSG("start\n");
++		ingenic_spdif_start_substream(substream, spdif);
++		break;
++	case SNDRV_PCM_TRIGGER_STOP:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++		SPDIF_DEBUG_MSG("stop\n");
++		ingenic_spdif_stop_substream(substream, spdif);
++		break;
++	}
++
++	return 0;
++}
++
++static int ingenic_spdif_div(struct ingenic_spdif *spdif, int stream, unsigned long rate, int channels)
++{
++	int clk_ratio = stream ? 1280 : 32 * 2 * channels;  //fixed 2channels
++	int clk, div, sysclk = spdif->sysclk;
++
++	clk = rate * clk_ratio;
++	div = ((sysclk + clk - 1) / clk) & (~0x1UL);
++
++	return div;
++}
++
++struct sampl_freq {
++	u32 freq;
++#define SPDIF_OUT_FS		0
++#define SPDIF_OUT_ORG_FRQ	1
++	int flag;
++	u32 val;
++} sample[] = {
++	/* References : IEC 60958-3 configure */
++	{22050,	 SPDIF_OUT_FS, SPO_SET_FS(0x2)},
++	{24000,  SPDIF_OUT_FS, SPO_SET_FS(0x6)},
++	{32000,  SPDIF_OUT_FS, SPO_SET_FS(0xc)},
++	{44100,  SPDIF_OUT_FS, SPO_SET_FS(0x0)},
++	{48000,  SPDIF_OUT_FS, SPO_SET_FS(0x4)},
++	{88200,  SPDIF_OUT_FS, SPO_SET_FS(0x1)},
++	{96000,  SPDIF_OUT_FS, SPO_SET_FS(0x5)},
++	{192000, SPDIF_OUT_FS, SPO_SET_FS(0x7)},
++	{176400, SPDIF_OUT_FS, SPO_SET_FS(0x3)},
++	{768000, SPDIF_OUT_FS, SPO_SET_FS(0x9)},
++
++	{8000,   SPDIF_OUT_ORG_FRQ, SPO_SET_ORG_FRQ(0x6)},
++	{11025,  SPDIF_OUT_ORG_FRQ, SPO_SET_ORG_FRQ(0x5)},
++	{12000,  SPDIF_OUT_ORG_FRQ, SPO_SET_ORG_FRQ(0x4)},
++	{16000,  SPDIF_OUT_ORG_FRQ, SPO_SET_ORG_FRQ(0x1)},
++	{22050,  SPDIF_OUT_ORG_FRQ, SPO_SET_ORG_FRQ(0xb)},
++	{24000,  SPDIF_OUT_ORG_FRQ, SPO_SET_ORG_FRQ(0x9)},
++	{32000,  SPDIF_OUT_ORG_FRQ, SPO_SET_ORG_FRQ(0x3)},
++	{44100,  SPDIF_OUT_ORG_FRQ, SPO_SET_ORG_FRQ(0xf)},
++	{48000,  SPDIF_OUT_ORG_FRQ, SPO_SET_ORG_FRQ(0xd)},
++	{88200,  SPDIF_OUT_ORG_FRQ, SPO_SET_ORG_FRQ(0xe)},
++	{96000,  SPDIF_OUT_ORG_FRQ, SPO_SET_ORG_FRQ(0xa)},
++	{176400, SPDIF_OUT_ORG_FRQ, SPO_SET_ORG_FRQ(0xc)},
++	{192000, SPDIF_OUT_ORG_FRQ, SPO_SET_ORG_FRQ(0x8)},
++};
++
++
++static int ingenic_spdif_out_set_rate(struct ingenic_spdif *spdif, unsigned long sample_rate)
++{
++	int i;
++	u32 fs = SPO_SET_FS(0x8), orq_frq = 0;
++
++	for (i = 0; i < ARRAY_SIZE(sample); i++) {
++		if (sample[i].freq == sample_rate) {
++			if (sample[i].flag == SPDIF_OUT_FS)
++				fs = sample[i].val;
++			else
++				orq_frq = sample[i].val;
++		}
++	}
++	return fs | orq_frq;
++}
++
++static bool ingenic_spdif_params_check(int channels, int fmt_width)
++{
++	if (channels != 2)
++		goto error;
++	if (fmt_width < 16 || fmt_width > 24)
++		goto error;
++
++	return true;
++error:
++	pr_err("[ERROR]: %s %d\n", __func__, __LINE__);
++	return false;
++}
++
++
++static int ingenic_spdif_hw_params(struct snd_pcm_substream *substream,
++		struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
++{
++	int channels = params_channels(params);
++	int rate = params_rate(params);
++	int fmt_width = snd_pcm_format_width(params_format(params));
++	struct ingenic_spdif *spdif = dev_get_drvdata(dai->dev);
++	u32 max_wl = 0, div = 0, sampl_wl = 0, rate_reg = 0;
++
++	SPDIF_DEBUG_MSG("enter %s, substream = %s, channels %d, rate %d, fmt_width %d\n", __func__,
++			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture",
++			channels, rate, fmt_width);
++
++	if(!ingenic_spdif_params_check(channels, fmt_width))
++		return -EINVAL;
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		if (!spdif->non_pcm) {
++			max_wl = (1 == fmt_width/10) ? 0 : 1;
++			sampl_wl = SPO_SET_SAMPL_WL(fmt_width, max_wl);
++			rate_reg = ingenic_spdif_out_set_rate(spdif, rate);
++			regmap_update_bits(spdif->spdif_out_regmap, SPCFG2,
++					SPO_FS_MASK|SPO_ORG_FRQ_MASK|SPO_SAMPL_WL_MASK|SPO_MAX_WL,
++					rate_reg|sampl_wl|(max_wl ? SPO_MAX_WL : 0));
++		}
++		regmap_update_bits(spdif->spdif_out_regmap, SPCTRL, SPO_SIGN_N,
++				snd_pcm_format_signed(params_format(params)) ? 0 : 1);
++		div = ingenic_spdif_div(spdif, substream->stream, rate, channels);
++		if (spdif->out_clk_div)
++			div = spdif->out_clk_div;
++		SPDIF_DEBUG_MSG("SPDIF OUT's clk div %d\n", div);
++		regmap_write(spdif->spdif_out_regmap, SPDIV, SPO_SET_DV(div));
++	} else {
++		div = ingenic_spdif_div(spdif, substream->stream, rate, channels);
++		if (spdif->in_clk_div)
++			div = spdif->in_clk_div;
++		SPDIF_DEBUG_MSG("SPDIF IN's clk div %d\n", div);
++		regmap_write(spdif->spdif_in_regmap, SPIDIV, SPI_SET_DV(div));
++	}
++
++	return ingenic_spdif_fmtcov_be_fix(substream, params);
++}
++
++static int ingenic_spdif_set_sysclk(struct snd_soc_dai *dai, int clk_id,
++		unsigned int freq, int dir)
++{
++	struct ingenic_spdif *spdif = dev_get_drvdata(dai->dev);
++
++	SPDIF_DEBUG_MSG("enter %s, sysclk freq=%d\n", __func__, freq);
++	clk_set_rate(spdif->clk, freq);
++	spdif->sysclk = freq;
++
++	return 0;
++}
++
++static int ingenic_spdif_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
++{
++	struct ingenic_spdif *spdif = dev_get_drvdata(dai->dev);
++
++	switch (div_id) {
++	case SNDRV_PCM_STREAM_PLAYBACK:
++		spdif->out_clk_div = div;
++		break;
++	case SNDRV_PCM_STREAM_CAPTURE:
++		spdif->in_clk_div = div;
++		break;
++	default:
++		pr_err("%s:%d\n", __func__, __LINE__);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static struct snd_soc_dai_ops ingenic_spdif_dai_ops = {
++	.startup	= ingenic_spdif_startup,
++	.trigger    = ingenic_spdif_trigger,
++	.hw_params  = ingenic_spdif_hw_params,
++	.set_sysclk = ingenic_spdif_set_sysclk,
++	.set_clkdiv = ingenic_spdif_set_clkdiv,
++};
++
++struct snd_soc_component_driver ingenic_spdif_component = {
++	.name = "spdif",
++};
++
++/* TODO: replace by dts. */
++static int ingenic_spdif_clk_init(struct platform_device *pdev, struct ingenic_spdif *spdif)
++{
++	const char *name;
++
++	of_property_read_string(spdif->dev->of_node, "ingenic,clk-name", &name);
++	spdif->clk = devm_clk_get(spdif->dev, name);
++	if(IS_ERR_OR_NULL(spdif->clk)) {
++		dev_warn(spdif->dev, "Warning ... Failed to get %s\n", name);
++	}
++
++	if(spdif->clk) {
++		struct clk *parent;
++		of_property_read_string(spdif->dev->of_node, "ingenic,clk-parent", &name);
++		parent = devm_clk_get(spdif->dev, name);
++		if(IS_ERR_OR_NULL(parent)) {
++			dev_warn(spdif->dev, "Warning ... Failed to get %s\n",name);
++		}
++		clk_set_parent(spdif->clk, parent);
++		devm_clk_put(spdif->dev, parent);
++	}
++
++	spdif->clk_gate = devm_clk_get(spdif->dev, "gate_spdif");
++	if(IS_ERR_OR_NULL(spdif->clk_gate)) {
++		dev_warn(spdif->dev, "Warning ... Failed to get gate_spdif\n");
++	}
++
++	if(spdif->clk) {
++		clk_set_rate(spdif->clk, 24000000);
++		spdif->sysclk = 24000000;
++		clk_prepare_enable(spdif->clk);
++	}
++	if(spdif->clk_gate) {
++		clk_prepare_enable(spdif->clk_gate);
++	}
++
++	return 0;
++}
++
++static int ingenic_spdif_platform_probe(struct platform_device *pdev)
++{
++	struct ingenic_spdif *spdif;
++	struct resource *res;
++	int ret;
++	struct regmap_config regmap_config = {
++		.reg_bits = 32,
++		.reg_stride = 4,
++		.val_bits = 32,
++		.cache_type = REGCACHE_NONE,
++	};
++
++	spdif = devm_kzalloc(&pdev->dev, sizeof(struct ingenic_spdif) +
++			sizeof(struct snd_soc_dai_driver), GFP_KERNEL);
++	if (!spdif)
++		return -ENOMEM;
++
++	spdif->dai_driver = (struct snd_soc_dai_driver*)(spdif + 1);
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "out");
++	spdif->spdif_out_base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(spdif->spdif_out_base))
++		    return PTR_ERR(spdif->spdif_out_base);
++	regmap_config.max_register = resource_size(res) - 0x4;
++	regmap_config.name = res->name;
++	spdif->spdif_out_regmap = devm_regmap_init_mmio(&pdev->dev,
++			        spdif->spdif_out_base,
++					        &regmap_config);
++	if (IS_ERR(spdif->spdif_out_regmap))
++		    return PTR_ERR(spdif->spdif_out_regmap);
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "in");
++	spdif->spdif_in_base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(spdif->spdif_in_base))
++		    return PTR_ERR(spdif->spdif_in_base);
++	regmap_config.max_register = resource_size(res) - 0x4;
++	regmap_config.name = res->name;
++	spdif->spdif_in_regmap = devm_regmap_init_mmio(&pdev->dev,
++			        spdif->spdif_in_base,
++					        &regmap_config);
++	if (IS_ERR(spdif->spdif_in_regmap))
++		    return PTR_ERR(spdif->spdif_in_regmap);
++
++	spdif->non_pcm = of_property_read_bool(pdev->dev.of_node, "ingenic,non-pcm");
++
++	spdif->dev = &pdev->dev;
++
++	spdif->dai_driver->id = 1;
++	spdif->dai_driver->name = "SPDIF";
++	spdif->dai_driver->ops = &ingenic_spdif_dai_ops;
++	spdif->dai_driver->playback.stream_name = "SPDIF playback";
++	spdif->dai_driver->capture.stream_name = "SPDIF capture";
++
++	ingenic_spdif_clk_init(pdev, spdif);
++
++	platform_set_drvdata(pdev, spdif);
++
++
++	ret = devm_snd_soc_register_component(&pdev->dev, &ingenic_spdif_component,
++			spdif->dai_driver, 1);
++	if (!ret)
++		dev_info(&pdev->dev, "spdif platform probe success\n");
++
++	return ret;
++}
++
++static int ingenic_spdif_platform_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id ingenic_spdif_match_table[] = {
++	{ .compatible = "ingenic,as-spdif", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, ingenic_spdif_match_table);
++
++#ifdef CONFIG_PM
++static int ingenic_spdif_runtime_suspend(struct device *dev)
++{
++	return 0;
++}
++
++static int ingenic_spdif_runtime_resume(struct device *dev)
++{
++	return 0;
++}
++#endif
++
++static const struct dev_pm_ops ingenic_spdif_pm_ops = {
++	SET_RUNTIME_PM_OPS(ingenic_spdif_runtime_suspend,
++			ingenic_spdif_runtime_resume, NULL)
++};
++
++
++static struct platform_driver ingenic_spdif_platform_driver = {
++	.driver = {
++		.name = "as-spdif",
++		.of_match_table = ingenic_spdif_match_table,
++		.pm = &ingenic_spdif_pm_ops,
++	},
++	.probe = ingenic_spdif_platform_probe,
++	.remove = ingenic_spdif_platform_remove,
++};
++module_platform_driver(ingenic_spdif_platform_driver);
++
++MODULE_AUTHOR("wqshao <wangquan.shao@ingenic.com>");
++MODULE_DESCRIPTION("Ingenic AS spdif SoC Interface");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-as-spdif");
+diff --git a/module_drivers/sound/soc/ingenic/as-v2/as-spdif.h b/module_drivers/sound/soc/ingenic/as-v2/as-spdif.h
+new file mode 100644
+index 000000000..0c8ba59e1
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v2/as-spdif.h
+@@ -0,0 +1,99 @@
++/*
++ * ALSA Soc Audio Layer -- Ingenic AS BAIC Controller
++ *
++ * Copyright 2017 - 2022 Ingenic Semiconductor Co.,Ltd
++ *     wqshao <wangquan.shao@ingenic.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#ifndef __AS_SPDIF_H__
++#define __AS_SPDIF_H__
++
++#include <linux/bitops.h>
++
++struct ingenic_spdif {
++	struct device   *dev;
++	struct regmap *spdif_out_regmap;
++	struct regmap *spdif_in_regmap;
++	void __iomem    *spdif_out_base;
++	void __iomem    *spdif_in_base;
++	bool non_pcm;
++	u32 sysclk;
++	u32 out_clk_div;
++	u32 in_clk_div;
++	struct snd_soc_dai_driver *dai_driver;
++
++	struct clk *clk;
++	struct clk *clk_gate;
++};
++
++/* SPDIF OUT */
++#define SPENA	(0x0)
++#define SPO_SPEN			BIT(0)
++
++#define SPCTRL	(0x4)
++#define SPO_D_TYPE			BIT(14)
++#define SPO_SIGN_N			BIT(13)
++#define SPO_INVALID			BIT(12)
++#define SPO_SFT_RST			BIT(11)
++
++#define SPCFG1	(0x8)
++#define SPO_SCR_NUM_SFT		(8)
++#define SPO_SCR_NUM_MASK	GENMASK(11, SPO_SCR_NUM_SFT)
++#define SPO_SET_SCR_NUM(x)	((x) << SPO_SCR_NUM_SFT)
++#define SPO_CH1_NUM_SFT		(4)
++#define SPO_CH1_NUM_MASK	GENMASK(7, SPO_CH1_NUM_SFT)
++#define SPO_SET_CH1_NUM(x)	((x) << SPO_CH1_NUM_SFT)
++#define SPO_CH2_NUM_SFT		(0)
++#define SPO_CH2_NUM_MASK	GENMASK(3, SPO_CH2_NUM_SFT)
++#define SPO_SET_CH2_NUM(x)	((x) << SPO_CH2_NUM_SFT)
++
++#define SPCFG2	(0xc)
++#define SPO_FS_SFT			(26)
++#define SPO_FS_MASK			GENMASK(29, SPO_FS_SFT)
++#define SPO_SET_FS(x)		((x) << SPO_FS_SFT)
++#define SPO_ORG_FRQ_SFT		(22)
++#define SPO_ORG_FRQ_MASK	GENMASK(25, SPO_ORG_FRQ_SFT)
++#define SPO_SET_ORG_FRQ(x)	((x) << SPO_ORG_FRQ_SFT)
++
++#define SPO_SAMPL_WL_SFT	(19)
++#define SPO_SAMPL_WL_MASK	GENMASK(21, SPO_SAMPL_WL_SFT)
++#define SAMPL_WL_16			(0x1 << SPO_SAMPL_WL_SFT)
++#define SAMPL_WL_17_21		(0x6 << SPO_SAMPL_WL_SFT)
++#define SAMPL_WL_18_22		(0x2 << SPO_SAMPL_WL_SFT)
++#define SAMPL_WL_19_23		(0x4 << SPO_SAMPL_WL_SFT)
++#define SAMPL_WL_24			(0x6 << SPO_SAMPL_WL_SFT)
++#define SAMPL_WL0_20		(0x5 << SPO_SAMPL_WL_SFT)
++#define SAMPL_WL1_20		(0x1 << SPO_SAMPL_WL_SFT)
++#define SPO_SET_SAMPL_WL(wl, max_wl) (((wl == 16) && !max_wl) ? SAMPL_WL_16 : ((wl == 17) || ( wl == 21)) ? SAMPL_WL_17_21 : ((wl == 18) || (wl == 22)) ? SAMPL_WL_18_22 : ((wl == 19) || (wl == 23)) ? SAMPL_WL_19_23 : (wl == 24) ? SAMPL_WL_24 : (wl == 20) && max_wl ? SAMPL_WL1_20 : SAMPL_WL0_20)
++#define SPO_MAX_WL			BIT(18)
++#define SPO_CAT_CODE_SFT	(8)
++#define SPO_CAT_CODE_MASK	GENMASK(15, SPO_CAT_CODE_SFT)
++#define SPO_CAT_CODE_GEN	(0x0 << SPO_CAT_CODE_SFT)
++#define SPO_CAT_CODE_DVD	(0x4c << SPO_CAT_CODE_SFT)
++#define SPO_CH_MD_SFT		(6)
++#define SPO_CH_MD_MASK		GENMASK(7, SPO_CH_MD_SFT)
++#define SPO_CH_MD_0			(0x0 << SPO_CH_MD_SFT)
++#define SPO_AUDIO_N			BIT(1)
++#define SPO_CON_PRO			BIT(0)
++
++#define SPDIV	(0x10)
++#define SPO_DV_SFT			(0)
++#define SPO_SET_DV(x) (((x) > ((1 << 7) - 1) ? ((1 << 7) - 1) : (x)) << SPO_DV_SFT)
++
++/* SPDIF IN */
++#define SPIENA	(0x0)
++#define SPI_RESET			BIT(1)
++#define SPI_SPIEN			BIT(0)
++
++#define SPICFG1	(0x4)
++#define SPICFG2	(0x8)
++#define SPICFG3	(0xc)
++#define SPIDIV	(0x10)
++#define SPI_DV_SFT			(0)
++#define SPI_SET_DV(x)		SPO_SET_DV(x)
++
++#endif //__AS_SPDIF_H__
+diff --git a/module_drivers/sound/soc/ingenic/as-v2/as-vir-fe.c b/module_drivers/sound/soc/ingenic/as-v2/as-vir-fe.c
+new file mode 100644
+index 000000000..35fd9d81b
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/as-v2/as-vir-fe.c
+@@ -0,0 +1,148 @@
++/*
++ * ALSA Soc Audio Layer -- ingenic as(audio system) Virtual FE (Basic Audio
++ * Interface Controller) driver
++ *
++ * Copyright 2017 - 2022 Ingenic Semiconductor Co.,Ltd
++ *   wqshao <wangquan.shao@ingenic.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/of.h>
++#include <sound/soc.h>
++#include <sound/pcm_params.h>
++
++static const struct snd_pcm_hardware ingenic_vir_fe_hardware = {
++	/* Random values to keep userspace happy when checking constraints */
++	.info			= SNDRV_PCM_INFO_INTERLEAVED |
++				  SNDRV_PCM_INFO_BLOCK_TRANSFER,
++	.buffer_bytes_max	= 128*1024,
++	.period_bytes_min	= PAGE_SIZE,
++	.period_bytes_max	= PAGE_SIZE*2,
++	.periods_min		= 2,
++	.periods_max		= 128,
++};
++
++static int ingenic_vir_fe_open(struct snd_soc_component *component, struct snd_pcm_substream *substream)
++{
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++
++	/* BE's dont need virtual params */
++	if (!rtd->dai_link->no_pcm)
++		snd_soc_set_runtime_hwparams(substream, &ingenic_vir_fe_hardware);
++
++	return 0;
++}
++
++static int ingenic_vir_fe_ioctl(struct snd_soc_component *component, struct snd_pcm_substream *substream, unsigned int cmd, void *arg)
++{
++	return snd_pcm_lib_ioctl(substream, cmd, arg);
++}
++
++static int ingenic_vir_fe_prepare(struct snd_soc_component *component, struct snd_pcm_substream *substream)
++{
++	struct snd_pcm_runtime *runtime = substream->runtime;
++
++	/* The analog play buffer has data on play music */
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++		runtime->stop_threshold = runtime->boundary;
++
++	return 0;
++}
++
++static struct snd_soc_component_driver ingenic_vir_platform = {
++	.name	= "as-vir-fe",
++	.open = ingenic_vir_fe_open,
++	.ioctl = ingenic_vir_fe_ioctl,
++	.prepare = ingenic_vir_fe_prepare,
++};
++
++#define INGENIC_STUB_RATES	SNDRV_PCM_RATE_8000_192000
++#define INGENIC_STUB_FORMATS	(SNDRV_PCM_FMTBIT_S8 | \
++			SNDRV_PCM_FMTBIT_U8 | \
++			SNDRV_PCM_FMTBIT_S16_LE | \
++			SNDRV_PCM_FMTBIT_U16_LE | \
++			SNDRV_PCM_FMTBIT_S24_LE | \
++			SNDRV_PCM_FMTBIT_U24_LE | \
++			SNDRV_PCM_FMTBIT_S32_LE | \
++			SNDRV_PCM_FMTBIT_U32_LE | \
++			SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE)
++
++
++#define INGENIC_VIR_FE_MAX	10
++static int ingenic_as_vir_fe_probe(struct platform_device *pdev)
++{
++	struct snd_soc_dai_driver *vir_fe_dais;
++	static char dai_name[INGENIC_VIR_FE_MAX][20];
++	int i, ret, num_dais, cap_dai_bitmsk;
++
++	if (of_property_read_u32(pdev->dev.of_node, "ingenic,num-dais", &num_dais))
++		return -ENODEV;
++
++	if (of_property_read_u32(pdev->dev.of_node, "ingenic,cap-dai-bm", &cap_dai_bitmsk))
++		return -ENODEV;
++
++	vir_fe_dais =  devm_kzalloc(&pdev->dev, sizeof(*vir_fe_dais) * num_dais, GFP_KERNEL);
++	if (!vir_fe_dais)
++		return -ENOMEM;
++
++
++	for (i = 0; i < num_dais; i++) {
++		sprintf(dai_name[i], "Virtual-FE%d", i);
++		vir_fe_dais[i].name = dai_name[i];
++		vir_fe_dais[i].id = i;
++		if ((BIT(i) & cap_dai_bitmsk)) {
++			vir_fe_dais[i].capture.stream_name = dai_name[i];
++			vir_fe_dais[i].capture.channels_min = 1;
++			vir_fe_dais[i].capture.channels_max = 384;
++			vir_fe_dais[i].capture.rates = INGENIC_STUB_RATES;
++			vir_fe_dais[i].capture.formats = INGENIC_STUB_FORMATS;
++		} else {
++			vir_fe_dais[i].playback.stream_name = dai_name[i];
++			vir_fe_dais[i].playback.channels_min = 1;
++			vir_fe_dais[i].playback.channels_max = 384;
++			vir_fe_dais[i].playback.rates = INGENIC_STUB_RATES;
++			vir_fe_dais[i].playback.formats = INGENIC_STUB_FORMATS;
++		}
++	}
++
++	ret = snd_soc_register_component(&pdev->dev, &ingenic_vir_platform, vir_fe_dais, num_dais);
++
++	if (ret < 0) {
++		snd_soc_unregister_component(&pdev->dev);
++		return ret;
++	}
++
++	dev_info(&pdev->dev, "probe success!!!\n");
++	return ret;
++}
++
++static int ingenic_as_vir_fe_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id ingenic_as_vir_fe_match_table[] = {
++	{ .compatible = "ingenic,as-vir-fe", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, ingenic_as_vir_fe_match_table);
++
++static struct platform_driver ingenic_as_vir_fe_platform_driver = {
++	.driver = {
++		.name = "as-virtual-fe",
++		.of_match_table = ingenic_as_vir_fe_match_table,
++	},
++	.probe = ingenic_as_vir_fe_probe,
++	.remove = ingenic_as_vir_fe_remove,
++};
++module_platform_driver(ingenic_as_vir_fe_platform_driver);
++
++MODULE_AUTHOR("wqshao <wangquan.shao@ingenic.com>");
++MODULE_DESCRIPTION("Ingenic AS Virtual FE SoC Interface");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ingenic-as-vir-fe");
+diff --git a/module_drivers/sound/soc/ingenic/boards/Makefile b/module_drivers/sound/soc/ingenic/boards/Makefile
+new file mode 100644
+index 000000000..bac7cae58
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/boards/Makefile
+@@ -0,0 +1,19 @@
++## X2000 Supported Boards
++snd_halley5_v20-y := halley5_v20.o
++obj-$(CONFIG_SND_ASOC_INGENIC_HALLEY5_V20) += snd_halley5_v20.o
++snd_gewu-y := gewu.o
++obj-$(CONFIG_SND_ASOC_INGENIC_GEWU) += snd_gewu.o
++snd_kale_v10-y := kale_v10.o
++obj-$(CONFIG_SND_ASOC_INGENIC_KALE_V10) += snd_kale_v10.o
++
++## hippo Supported Boards
++snd_hippo-board-y := hippo-board.o
++obj-$(CONFIG_SND_ASOC_INGENIC_HIPPO_BOARD) += snd_hippo-board.o
++
++## x1600 Supported Boards
++snd_panda-y := panda.o
++obj-$(CONFIG_SND_ASOC_INGENIC_PANDA) += snd_panda.o
++snd_halley6-y := halley6.o
++obj-$(CONFIG_SND_ASOC_INGENIC_HALLEY6) += snd_halley6.o
++snd_x1600_iris-y := x1600_iris.o
++obj-$(CONFIG_SND_ASOC_INGENIC_X1600_IRIS) += snd_x1600_iris.o
+diff --git a/module_drivers/sound/soc/ingenic/boards/gewu.c b/module_drivers/sound/soc/ingenic/boards/gewu.c
+new file mode 100644
+index 000000000..af5afd2de
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/boards/gewu.c
+@@ -0,0 +1,547 @@
++ /*
++ * Copyright (C) 2017 Ingenic Semiconductor Co., Ltd.
++ *	http://www.ingenic.com
++ * Author: cli <chen.li@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <sound/soc.h>
++#include <sound/pcm_params.h>
++#include <linux/clk.h>
++#include "../as-v2/as-baic.h"
++
++static const struct snd_soc_dapm_route audio_map[] = {
++	{ "BAIC0 playback", NULL, "LO0_MUX" },
++
++	{ "LI2", NULL, "BAIC0 capture" },
++
++	{ "LI8", NULL, "DMA0" },
++	{ "LI9", NULL, "DMA1" },
++	{ "LI10", NULL, "DMA2" },
++	{ "LI11", NULL, "DMA3" },
++	{ "LI12", NULL, "DMA4" },
++
++	{ "DMA5", NULL, "LO5_MUX"},
++	{ "DMA6", NULL, "LO6_MUX"},
++	{ "DMA7", NULL, "LO7_MUX"},
++	{ "DMA8", NULL, "LO8_MUX"},
++	{ "DMA9", NULL, "LO9_MUX"},
++
++	{ "MIX0", NULL, "LO10_MUX"},
++	{ "MIX0", NULL, "LO11_MUX"},
++	{ "LI7",  NULL, "MIX0"},
++
++};
++
++static const struct snd_soc_dapm_widget dapm_widgets[] = {
++};
++
++struct codec_format_enum {
++	struct soc_enum e;
++	int baic_id;
++	unsigned int *format;
++};
++
++unsigned int codec_format[MAX_BAIC_NUM] = {
++	/*baic0 icodec format*/
++	SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF|SND_SOC_DAIFMT_CBS_CFS,
++	/*baic1 format*/
++	SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF|SND_SOC_DAIFMT_CBS_CFS,
++	/*baic2 format*/
++	SND_SOC_DAIFMT_DSP_B|SND_SOC_DAIFMT_NB_NF|SND_SOC_DAIFMT_CBS_CFS|BAIC_DAIFMT_SEL_TDM1,
++	/*baic3 format*/
++	SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF|SND_SOC_DAIFMT_CBS_CFS,
++	/*baic4 pcm format*/
++	SND_SOC_DAIFMT_DSP_B|SND_SOC_DAIFMT_NB_NF|SND_SOC_DAIFMT_CBS_CFS|BAIC_DAIFMT_SEL_DSP,
++};
++static const char *const baic_format_item_name[BAIC_SUPPORT_FORMAT_MAX] = {
++	"PCMA", "PCMB","DSPA","DSPB","TDM1A","TDM1B","TDM2A","TDM2B","I2S","LEFT","RIGHT"
++};
++static const unsigned int baic_format_item_value[BAIC_SUPPORT_FORMAT_MAX] = {
++	SND_SOC_DAIFMT_DSP_A|BAIC_DAIFMT_SEL_PCM,
++	SND_SOC_DAIFMT_DSP_B|BAIC_DAIFMT_SEL_PCM,
++	SND_SOC_DAIFMT_DSP_A|BAIC_DAIFMT_SEL_DSP,
++	SND_SOC_DAIFMT_DSP_B|BAIC_DAIFMT_SEL_DSP,
++	SND_SOC_DAIFMT_DSP_A|BAIC_DAIFMT_SEL_TDM1,
++	SND_SOC_DAIFMT_DSP_B|BAIC_DAIFMT_SEL_TDM1,
++	SND_SOC_DAIFMT_DSP_A|BAIC_DAIFMT_SEL_TDM2,
++	SND_SOC_DAIFMT_DSP_B|BAIC_DAIFMT_SEL_TDM2,
++	SND_SOC_DAIFMT_I2S,
++	SND_SOC_DAIFMT_LEFT_J,
++	SND_SOC_DAIFMT_RIGHT_J,
++};
++static int baic_format_get_enum(struct snd_kcontrol *kcontrol,
++		struct snd_ctl_elem_value *ucontrol)
++{
++	struct codec_format_enum *e = (struct codec_format_enum *)kcontrol->private_value;
++	unsigned int format = (*e->format) & (SND_SOC_DAIFMT_FORMAT_MASK | BAIC_DAIFMT_SEL_MASK);
++	int i;
++	for(i=0; i < BAIC_SUPPORT_FORMAT_MAX; i++) {
++		if(format == baic_format_item_value[i]) {
++			ucontrol->value.enumerated.item[0] = i;
++			return 0;
++		}
++	}
++	return -EINVAL;
++}
++
++static int baic_format_put_enum(struct snd_kcontrol *kcontrol,
++		struct snd_ctl_elem_value *ucontrol)
++{
++	struct codec_format_enum *e = (struct codec_format_enum *)kcontrol->private_value;
++	unsigned int item = ucontrol->value.enumerated.item[0];
++
++	(*e->format) &= ~(SND_SOC_DAIFMT_FORMAT_MASK | BAIC_DAIFMT_SEL_MASK);
++	(*e->format) |= baic_format_item_value[item];
++
++	return 0;
++}
++
++static struct codec_format_enum codec_format_enum[] = {	/*not const*/
++#define BAIC_FORMAT_ENUM(_baic_id)	\
++	{ \
++		.e = SOC_ENUM_SINGLE_EXT(BAIC_SUPPORT_FORMAT_MAX, baic_format_item_name), \
++		.baic_id = _baic_id,	\
++		.format = &codec_format[(_baic_id)],	\
++	}
++	BAIC_FORMAT_ENUM(0),
++	BAIC_FORMAT_ENUM(1),
++	BAIC_FORMAT_ENUM(2),
++	BAIC_FORMAT_ENUM(3),
++	BAIC_FORMAT_ENUM(4),
++#undef BAIC_FORMAT_ENUM
++};
++
++static const struct snd_kcontrol_new card_snd_controls[] = {
++#define FORMAT0 "baic0_fmt"
++#define FORMAT1 "baic1_fmt"
++#define FORMAT2 "baic2_fmt"
++#define FORMAT3 "baic3_fmt"
++#define FORMAT4 "baic4_fmt"
++#define CODEC_FORMAT_ENUM_EXT(N) \
++	SOC_ENUM_EXT(FORMAT##N,		\
++		codec_format_enum[(N)], \
++		baic_format_get_enum,	\
++		baic_format_put_enum)
++	CODEC_FORMAT_ENUM_EXT(0),
++	CODEC_FORMAT_ENUM_EXT(1),
++	CODEC_FORMAT_ENUM_EXT(2),
++	CODEC_FORMAT_ENUM_EXT(3),
++	CODEC_FORMAT_ENUM_EXT(4),
++#undef FORMAT0
++#undef FORMAT1
++#undef FORMAT2
++#undef FORMAT3
++#undef FORMAT4
++#undef CODEC_FORMAT_ENUM_EXT
++};
++
++typedef enum slot_width {
++	slot_width_auto = 0,
++	slot_width_16 = 16,
++	slot_width_32 = 32,
++	slot_width_64 = 64,
++} slot_width_t;
++
++slot_width_t codec_slot_width[MAX_BAIC_NUM] = {
++	slot_width_auto,
++	slot_width_auto,
++	slot_width_32,
++	slot_width_32,
++	slot_width_auto
++};
++
++static int  get_baic_id(struct snd_soc_dai *dai)
++{
++	int id = -1;
++	const char *name = dai->driver->name;
++
++	sscanf(&name[strlen("BAIC")], "%d", &id);
++
++	return id;
++}
++
++static int baic_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++	struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
++	struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
++	int bclk_div = 0, sysclk = 24000000, bclk = 0, codec_slots = 0,
++	    sync_div = 0, sync_w_div = 1, tx_msk = 0, rx_msk = 0;
++	bool is_playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? true : false;
++	int divid_dir = is_playback ? DIVID_DIR_T : 0;
++	int clkid = is_playback ? CLKID_SYSCLK_T : CLKID_SYSCLK_R;
++	int channels = params_channels(params);
++	int fmt_width = snd_pcm_format_width(params_format(params));
++	int id = get_baic_id(cpu_dai);
++	int slot_width = codec_slot_width[id];
++	unsigned int format = codec_format[id];
++	int ret;
++
++	format |= is_playback ? BAIC_DAIFMT_T : BAIC_DAIFMT_R;
++	ret = snd_soc_runtime_set_dai_fmt(rtd, format);
++	if (ret)
++		return ret;
++
++	switch(format & SND_SOC_DAIFMT_FORMAT_MASK){
++		case SND_SOC_DAIFMT_LEFT_J:
++		case SND_SOC_DAIFMT_I2S:
++		case SND_SOC_DAIFMT_RIGHT_J:
++			if(fmt_width > 16) {
++				sync_div = 64;
++			} else if(fmt_width > 8) {
++				sync_div = 32;
++			} else {
++				sync_div = 16;
++			}
++			break;
++		case SND_SOC_DAIFMT_DSP_B:
++		case SND_SOC_DAIFMT_DSP_A:
++			if(!slot_width) {
++				slot_width = (fmt_width > 16) ? 32 : 16;
++			}
++			if (is_playback)
++				tx_msk = (1 << channels) - 1;
++			else
++				rx_msk = (1 << channels) - 1;
++			ret = snd_soc_dai_set_clkdiv(cpu_dai, DIVID_SYNC_W|divid_dir, sync_w_div);
++			if (ret)
++				return ret;
++			ret = snd_soc_dai_set_tdm_slot(cpu_dai, tx_msk, rx_msk, channels, slot_width);
++			if (ret)
++				return ret;
++
++			if((channels == 8) && ((format&BAIC_DAIFMT_SEL_TDM2) == BAIC_DAIFMT_SEL_TDM2)) {
++				sync_div = slot_width * 4;
++				/*for ak4458/ak5558*/
++				codec_slots = 4;
++			} else {
++				sync_div = slot_width * channels;
++				codec_slots = channels;
++			}
++			ret = snd_soc_dai_set_tdm_slot(codec_dai, tx_msk, rx_msk, codec_slots, slot_width);
++			if (ret != 0 && ret != -ENOTSUPP) {
++				dev_warn(codec_dai->dev,
++					 "ASoC: Failed to set tdm slot: %d\n", ret);
++				return ret;
++			}
++			break;
++		default:
++			printk("%s codec config err!\n",__func__);
++			return -EPERM;
++
++	}
++
++	ret = snd_soc_dai_set_clkdiv(cpu_dai, DIVID_SYNC|divid_dir, sync_div);
++	if (ret)
++		return ret;
++
++	bclk = params_rate(params) * sync_div;
++	if(id == 0 || id == 1) {
++		/*for baic0: sysclk = 256 * sample_rate */
++		sysclk = 256 * params_rate(params);
++	}
++
++	bclk_div = (sysclk + bclk - 1) / bclk;
++	/* bclk div value must be even */
++	if(bclk_div%2) {
++		sysclk = (bclk_div+1)*bclk;
++		bclk_div += 1;
++	}
++
++	ret = snd_soc_dai_set_sysclk(cpu_dai, clkid, sysclk, SND_SOC_CLOCK_OUT);
++	if (ret)
++		return ret;
++
++	ret = snd_soc_dai_set_clkdiv(cpu_dai, DIVID_BCLK|divid_dir, bclk_div);
++	if (ret)
++		return ret;
++
++	return 0;
++};
++
++static struct snd_soc_ops baic_ops = {
++	.hw_params = baic_hw_params,
++};
++
++SND_SOC_DAILINK_DEFS(dma0_playback,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA0")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma1_playback,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA1")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma2_playback,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA2")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma3_playback,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA3")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma4_playback,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA4")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma5_capture,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA5")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma6_capture,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA6")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma7_capture,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA7")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma8_capture,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA8")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma9_capture,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA9")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(inno_icodec,
++		DAILINK_COMP_ARRAY(COMP_CPU("BAIC0")),
++		DAILINK_COMP_ARRAY(COMP_CODEC("10020000.icodec", "icodec")));
++
++static struct snd_soc_dai_link m300_dais[] = {
++	/*FE DAIS*/
++	[0] = {
++		.name = "DMA0 playback",
++		.stream_name = "DMA0 playback",
++		.dynamic = 1,
++		.dpcm_playback = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma0_playback),
++	},
++
++	[1] = {
++		.name = "DMA1 playback",
++		.stream_name = "DMA1 playback",
++		.dynamic = 1,
++		.dpcm_playback = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma1_playback),
++	},
++
++	[2] = {
++		.name = "DMA2 playback",
++		.stream_name = "DMA2 playback",
++		.dynamic = 1,
++		.dpcm_playback = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma2_playback),
++	},
++
++	[3] = {
++		.name = "DMA3 playback",
++		.stream_name = "DMA3 playback",
++		.dynamic = 1,
++		.dpcm_playback = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma3_playback),
++	},
++
++	[4] = {
++		.name = "DMA4 playback",
++		.stream_name = "DMA4 playback",
++		.dynamic = 1,
++		.dpcm_playback = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma4_playback),
++	},
++
++	[5] = {
++		.name = "DMA5 capture",
++		.stream_name = "DMA5 capture",
++		.dynamic = 1,
++		.dpcm_capture = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma5_capture),
++	},
++
++	[6] = {
++		.name = "DMA6 capture",
++		.stream_name = "DMA6 capture",
++		.dynamic = 1,
++		.dpcm_capture = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma6_capture),
++	},
++
++	[7] = {
++		.name = "DMA7 capture",
++		.stream_name = "DMA7 capture",
++		.dynamic = 1,
++		.dpcm_capture = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma7_capture),
++	},
++
++	[8] = {
++		.name = "DMA8 capture",
++		.stream_name = "DMA8 capture",
++		.dynamic = 1,
++		.dpcm_capture = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma8_capture),
++	},
++
++	[9] = {
++		.name = "DMA9 capture",
++		.stream_name = "DMA9 capture",
++		.dynamic = 1,
++		.dpcm_capture = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma9_capture),
++	},
++
++	/*BE DAIS*/
++	[10] = {
++		.name = "BAIC0",
++		.stream_name = "BAIC0",
++		.ops = &baic_ops,
++		.be_hw_params_fixup = NULL,
++		.no_pcm = 1,
++		.dpcm_capture = 1,
++		.dpcm_playback = 1,
++		SND_SOC_DAILINK_REG(inno_icodec),
++	},
++
++};
++
++static struct snd_soc_aux_dev m300_aux_dev = {
++	.dlc = COMP_AUX( "134dc000.as-mixer"),
++};
++
++static int audio_clk_init(struct device *dev)
++{
++	struct clk *clk, *parent;
++	char clk_name[16];
++	unsigned long rate;
++	int i;
++
++	parent = clk_get(dev, "epll");
++	if(IS_ERR_OR_NULL(parent)) {
++		dev_err(dev, "Get epll clk failed!\n");
++		return -EINVAL;
++	}
++	for(i = 0; i < 4; i++) {
++		sprintf(clk_name, "div_i2s%d", i);
++		clk = clk_get(dev, clk_name);
++		if(IS_ERR_OR_NULL(clk)) {
++			dev_err(dev, "Get %s clk failed!\n", clk_name);
++			return -EINVAL;
++		}
++		rate = clk_get_rate(clk);
++		clk_set_parent(clk, parent);
++		clk_set_rate(clk, rate);
++		clk_put(clk);
++	}
++	clk_put(parent);
++
++	return 0;
++}
++
++static int snd_m300_probe(struct platform_device *pdev)
++{
++	struct snd_soc_card *card;
++	int ret;
++
++	card = (struct snd_soc_card *)devm_kzalloc(&pdev->dev,
++			sizeof(struct snd_soc_card), GFP_KERNEL);
++	if (!card)
++		return -ENOMEM;
++
++	card->dapm_widgets = dapm_widgets;
++	card->num_dapm_widgets = ARRAY_SIZE(dapm_widgets);
++	card->dapm_routes = audio_map;
++	card->num_dapm_routes = ARRAY_SIZE(audio_map);
++	card->controls = card_snd_controls;
++	card->num_controls = ARRAY_SIZE(card_snd_controls);
++	card->dai_link = m300_dais;
++	card->num_links = ARRAY_SIZE(m300_dais);
++	card->owner = THIS_MODULE;
++	card->dev = &pdev->dev;
++	card->aux_dev = &m300_aux_dev;
++	card->num_aux_devs = 1;
++
++	ret = snd_soc_of_parse_card_name(card, "ingenic,model");
++	if (ret)
++		return ret;
++
++	ret = snd_soc_register_card(card);
++	if (ret) {
++		dev_err(&pdev->dev, "snd_soc_register_card failed %d\n", ret);
++		return ret;
++	}
++
++	ret = audio_clk_init(card->dev);
++	if(ret)
++		return ret;
++
++	platform_set_drvdata(pdev, card);
++	dev_info(&pdev->dev, "Sound Card successed\n");
++
++	return ret;
++}
++
++static int snd_m300_remove(struct platform_device *pdev)
++{
++	struct snd_soc_card *card = platform_get_drvdata(pdev);
++	snd_soc_unregister_card(card);
++	platform_set_drvdata(pdev, NULL);
++	return 0;
++}
++
++static const struct of_device_id m300_match_table[] = {
++	{ .compatible = "ingenic,m300-sound", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, m300_match_table);
++
++static struct platform_driver snd_m300_driver = {
++	.driver = {
++		.owner = THIS_MODULE,
++		.name = "m300-sound",
++		.of_match_table = m300_match_table
++	},
++	.probe = snd_m300_probe,
++	.remove = snd_m300_remove,
++};
++module_platform_driver(snd_m300_driver);
++
++MODULE_AUTHOR("cli<chen.li@ingenic.com>");
++MODULE_DESCRIPTION("ALSA SoC m300 Snd Card");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/sound/soc/ingenic/boards/halley5_v20.c b/module_drivers/sound/soc/ingenic/boards/halley5_v20.c
+new file mode 100644
+index 000000000..b842d732a
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/boards/halley5_v20.c
+@@ -0,0 +1,624 @@
++ /*
++ * Copyright (C) 2017 Ingenic Semiconductor Co., Ltd.
++ *	http://www.ingenic.com
++ * Author: cli <chen.li@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <sound/soc.h>
++#include <sound/pcm_params.h>
++#include <linux/clk.h>
++#include "../as-v2/as-baic.h"
++#include <linux/gpio.h>
++#include <linux/delay.h>
++#include <linux/of_gpio.h>
++
++struct icodec_spk_power {
++	int spk_gpio;
++	unsigned char spk_en_level;
++};
++static struct icodec_spk_power *icodec_spk_power;
++
++typedef void (*p_icodec_playback_power)(bool);
++extern void set_playback_pwr_callback(p_icodec_playback_power func);
++static const struct snd_soc_dapm_route audio_map[] = {
++	{ "BAIC0 playback", NULL, "LO0_MUX" },
++	{ "BAIC4 playback", NULL, "LO4_MUX" },
++
++	{ "LI0", NULL, "DMIC capture" },
++	{ "LI2", NULL, "BAIC0 capture" },
++	{ "LI6", NULL, "BAIC4 capture" },
++
++	{ "LI8", NULL, "DMA0" },
++	{ "LI9", NULL, "DMA1" },
++	{ "LI10", NULL, "DMA2" },
++	{ "LI11", NULL, "DMA3" },
++	{ "LI12", NULL, "DMA4" },
++
++	{ "DMA5", NULL, "LO5_MUX"},
++	{ "DMA6", NULL, "LO6_MUX"},
++	{ "DMA7", NULL, "LO7_MUX"},
++	{ "DMA8", NULL, "LO8_MUX"},
++	{ "DMA9", NULL, "LO9_MUX"},
++
++	{ "MIX0", NULL, "LO10_MUX"},
++	{ "MIX0", NULL, "LO11_MUX"},
++	{ "LI7",  NULL, "MIX0"},
++
++	{"DMIC capture", NULL, "DMIC"},
++	{"BAIC4 capture", NULL, "PCMIN"},
++	{"PCMOUT", NULL, "BAIC4 playback"},
++};
++
++static const struct snd_soc_dapm_widget dapm_widgets[] = {
++	SND_SOC_DAPM_INPUT("DMIC"),
++	SND_SOC_DAPM_INPUT("PCMIN"),
++	SND_SOC_DAPM_OUTPUT("PCMOUT"),
++};
++
++struct codec_format_enum {
++	struct soc_enum e;
++	int baic_id;
++	unsigned int *format;
++};
++
++unsigned int codec_format[MAX_BAIC_NUM] = {
++	/*baic0 icodec format*/
++	SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF|SND_SOC_DAIFMT_CBS_CFS,
++	/*baic1 format*/
++	SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF|SND_SOC_DAIFMT_CBS_CFS,
++	/*baic2 format*/
++	SND_SOC_DAIFMT_DSP_B|SND_SOC_DAIFMT_NB_NF|SND_SOC_DAIFMT_CBS_CFS|BAIC_DAIFMT_SEL_TDM1,
++	/*baic3 format*/
++	SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF|SND_SOC_DAIFMT_CBS_CFS,
++	/*baic4 pcm format*/
++	SND_SOC_DAIFMT_DSP_A|SND_SOC_DAIFMT_IB_NF|SND_SOC_DAIFMT_CBM_CFM|BAIC_DAIFMT_SEL_DSP,
++};
++static const char *const baic_format_item_name[BAIC_SUPPORT_FORMAT_MAX] = {
++	"PCMA", "PCMB","DSPA","DSPB","TDM1A","TDM1B","TDM2A","TDM2B","I2S","LEFT","RIGHT"
++};
++static const unsigned int baic_format_item_value[BAIC_SUPPORT_FORMAT_MAX] = {
++	SND_SOC_DAIFMT_DSP_A|BAIC_DAIFMT_SEL_PCM,
++	SND_SOC_DAIFMT_DSP_B|BAIC_DAIFMT_SEL_PCM,
++	SND_SOC_DAIFMT_DSP_A|BAIC_DAIFMT_SEL_DSP,
++	SND_SOC_DAIFMT_DSP_B|BAIC_DAIFMT_SEL_DSP,
++	SND_SOC_DAIFMT_DSP_A|BAIC_DAIFMT_SEL_TDM1,
++	SND_SOC_DAIFMT_DSP_B|BAIC_DAIFMT_SEL_TDM1,
++	SND_SOC_DAIFMT_DSP_A|BAIC_DAIFMT_SEL_TDM2,
++	SND_SOC_DAIFMT_DSP_B|BAIC_DAIFMT_SEL_TDM2,
++	SND_SOC_DAIFMT_I2S,
++	SND_SOC_DAIFMT_LEFT_J,
++	SND_SOC_DAIFMT_RIGHT_J,
++};
++static int baic_format_get_enum(struct snd_kcontrol *kcontrol,
++		struct snd_ctl_elem_value *ucontrol)
++{
++	struct codec_format_enum *e = (struct codec_format_enum *)kcontrol->private_value;
++	unsigned int format = (*e->format) & (SND_SOC_DAIFMT_FORMAT_MASK | BAIC_DAIFMT_SEL_MASK);
++	int i;
++	for(i=0; i < BAIC_SUPPORT_FORMAT_MAX; i++) {
++		if(format == baic_format_item_value[i]) {
++			ucontrol->value.enumerated.item[0] = i;
++			return 0;
++		}
++	}
++	return -EINVAL;
++}
++
++static int baic_format_put_enum(struct snd_kcontrol *kcontrol,
++		struct snd_ctl_elem_value *ucontrol)
++{
++	struct codec_format_enum *e = (struct codec_format_enum *)kcontrol->private_value;
++	unsigned int item = ucontrol->value.enumerated.item[0];
++
++	(*e->format) &= ~(SND_SOC_DAIFMT_FORMAT_MASK | BAIC_DAIFMT_SEL_MASK);
++	(*e->format) |= baic_format_item_value[item];
++
++	return 0;
++}
++
++static struct codec_format_enum codec_format_enum[] = {	/*not const*/
++#define BAIC_FORMAT_ENUM(_baic_id)	\
++	{ \
++		.e = SOC_ENUM_SINGLE_EXT(BAIC_SUPPORT_FORMAT_MAX, baic_format_item_name), \
++		.baic_id = _baic_id,	\
++		.format = &codec_format[(_baic_id)],	\
++	}
++	BAIC_FORMAT_ENUM(0),
++	BAIC_FORMAT_ENUM(1),
++	BAIC_FORMAT_ENUM(2),
++	BAIC_FORMAT_ENUM(3),
++	BAIC_FORMAT_ENUM(4),
++#undef BAIC_FORMAT_ENUM
++};
++
++static const struct snd_kcontrol_new card_snd_controls[] = {
++#define FORMAT0 "baic0_fmt"
++#define FORMAT1 "baic1_fmt"
++#define FORMAT2 "baic2_fmt"
++#define FORMAT3 "baic3_fmt"
++#define FORMAT4 "baic4_fmt"
++#define CODEC_FORMAT_ENUM_EXT(N) \
++	SOC_ENUM_EXT(FORMAT##N,		\
++		codec_format_enum[(N)], \
++		baic_format_get_enum,	\
++		baic_format_put_enum)
++	CODEC_FORMAT_ENUM_EXT(0),
++	CODEC_FORMAT_ENUM_EXT(1),
++	CODEC_FORMAT_ENUM_EXT(2),
++	CODEC_FORMAT_ENUM_EXT(3),
++	CODEC_FORMAT_ENUM_EXT(4),
++#undef FORMAT0
++#undef FORMAT1
++#undef FORMAT2
++#undef FORMAT3
++#undef FORMAT4
++#undef CODEC_FORMAT_ENUM_EXT
++};
++
++typedef enum slot_width {
++	slot_width_auto = 0,
++	slot_width_16 = 16,
++	slot_width_32 = 32,
++	slot_width_64 = 64,
++} slot_width_t;
++
++slot_width_t codec_slot_width[MAX_BAIC_NUM] = {
++	slot_width_auto,
++	slot_width_auto,
++	slot_width_32,
++	slot_width_32,
++	slot_width_auto
++};
++
++static int  get_baic_id(struct snd_soc_dai *dai)
++{
++	int id = -1;
++	const char *name = dai->driver->name;
++
++	sscanf(&name[strlen("BAIC")], "%d", &id);
++
++	return id;
++}
++
++static int baic_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++	struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
++	struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
++	int bclk_div = 0, sysclk = 24000000, bclk = 0, codec_slots = 0,
++	    sync_div = 0, sync_w_div = 1, tx_msk = 0, rx_msk = 0;
++	bool is_playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? true : false;
++	int divid_dir = is_playback ? DIVID_DIR_T : 0;
++	int clkid = is_playback ? CLKID_SYSCLK_T : CLKID_SYSCLK_R;
++	int channels = params_channels(params);
++	int fmt_width = snd_pcm_format_width(params_format(params));
++	int id = get_baic_id(cpu_dai);
++	int slot_width = codec_slot_width[id];
++	unsigned int format = codec_format[id];
++	int ret;
++
++	format |= is_playback ? BAIC_DAIFMT_T : BAIC_DAIFMT_R;
++	ret = snd_soc_runtime_set_dai_fmt(rtd, format);
++	if (ret)
++		return ret;
++
++	switch(format & SND_SOC_DAIFMT_FORMAT_MASK){
++		case SND_SOC_DAIFMT_LEFT_J:
++		case SND_SOC_DAIFMT_I2S:
++		case SND_SOC_DAIFMT_RIGHT_J:
++			if(fmt_width > 16) {
++				sync_div = 64;
++			} else if(fmt_width > 8) {
++				sync_div = 32;
++			} else {
++				sync_div = 16;
++			}
++			break;
++		case SND_SOC_DAIFMT_DSP_B:
++		case SND_SOC_DAIFMT_DSP_A:
++			if(!slot_width) {
++				slot_width = (fmt_width > 16) ? 32 : 16;
++			}
++			if (is_playback)
++				tx_msk = (1 << channels) - 1;
++			else
++				rx_msk = (1 << channels) - 1;
++			ret = snd_soc_dai_set_clkdiv(cpu_dai, DIVID_SYNC_W|divid_dir, sync_w_div);
++			if (ret)
++				return ret;
++			ret = snd_soc_dai_set_tdm_slot(cpu_dai, tx_msk, rx_msk, channels, slot_width);
++			if (ret)
++				return ret;
++
++			if((channels == 8) && ((format&BAIC_DAIFMT_SEL_TDM2) == BAIC_DAIFMT_SEL_TDM2)) {
++				sync_div = slot_width * 4;
++				/*for ak4458/ak5558*/
++				codec_slots = 4;
++			} else {
++				sync_div = slot_width * channels;
++				codec_slots = channels;
++			}
++			ret = snd_soc_dai_set_tdm_slot(codec_dai, tx_msk, rx_msk, codec_slots, slot_width);
++			if (ret != 0 && ret != -ENOTSUPP) {
++				dev_warn(codec_dai->dev,
++					 "ASoC: Failed to set tdm slot: %d\n", ret);
++				return ret;
++			}
++			break;
++		default:
++			printk("%s codec config err!\n",__func__);
++			return -EPERM;
++
++	}
++
++	ret = snd_soc_dai_set_clkdiv(cpu_dai, DIVID_SYNC|divid_dir, sync_div);
++	if (ret)
++		return ret;
++
++	bclk = params_rate(params) * sync_div;
++	if(id == 0 || id == 1) {
++		/*for baic0: sysclk = 256 * sample_rate */
++		sysclk = 256 * params_rate(params);
++	}
++
++	bclk_div = (sysclk + bclk - 1) / bclk;
++	/* bclk div value must be even */
++	if(bclk_div%2) {
++		sysclk = (bclk_div+1)*bclk;
++		bclk_div += 1;
++	}
++
++	ret = snd_soc_dai_set_sysclk(cpu_dai, clkid, sysclk, SND_SOC_CLOCK_OUT);
++	if (ret)
++		return ret;
++
++	ret = snd_soc_dai_set_clkdiv(cpu_dai, DIVID_BCLK|divid_dir, bclk_div);
++	if (ret)
++		return ret;
++
++	return 0;
++};
++
++
++void icodec_playback_power_ctr(bool enable)
++{
++	if (!gpio_is_valid(icodec_spk_power->spk_gpio))
++		return;
++
++	if (enable) {
++		gpio_direction_output(icodec_spk_power->spk_gpio, icodec_spk_power->spk_en_level);
++	} else {
++		gpio_direction_output(icodec_spk_power->spk_gpio, !icodec_spk_power->spk_en_level);
++	}
++}
++
++static struct snd_soc_ops baic_ops = {
++	.hw_params = baic_hw_params,
++};
++
++SND_SOC_DAILINK_DEFS(dma0_playback,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA0")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma1_playback,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA1")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma2_playback,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA2")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma3_playback,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA3")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma4_playback,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA4")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma5_capture,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA5")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma6_capture,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA6")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma7_capture,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA7")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma8_capture,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA8")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma9_capture,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA9")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(inno_icodec,
++		DAILINK_COMP_ARRAY(COMP_CPU("BAIC0")),
++		DAILINK_COMP_ARRAY(COMP_CODEC("10020000.icodec", "icodec")));
++
++SND_SOC_DAILINK_DEFS(dmic,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMIC")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()));
++
++SND_SOC_DAILINK_DEFS(baic4_bt,
++		DAILINK_COMP_ARRAY(COMP_CPU("BAIC4")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()));
++
++
++static struct snd_soc_dai_link x2000_dais[] = {
++	/*FE DAIS*/
++	[0] = {
++		.name = "DMA0 playback",
++		.stream_name = "DMA0 playback",
++		.dynamic = 1,
++		.dpcm_playback = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma0_playback),
++	},
++
++	[1] = {
++		.name = "DMA1 playback",
++		.stream_name = "DMA1 playback",
++		.dynamic = 1,
++		.dpcm_playback = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma1_playback),
++	},
++
++	[2] = {
++		.name = "DMA2 playback",
++		.stream_name = "DMA2 playback",
++		.dynamic = 1,
++		.dpcm_playback = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma2_playback),
++	},
++
++	[3] = {
++		.name = "DMA3 playback",
++		.stream_name = "DMA3 playback",
++		.dynamic = 1,
++		.dpcm_playback = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma3_playback),
++	},
++
++	[4] = {
++		.name = "DMA4 playback",
++		.stream_name = "DMA4 playback",
++		.dynamic = 1,
++		.dpcm_playback = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma4_playback),
++	},
++
++	[5] = {
++		.name = "DMA5 capture",
++		.stream_name = "DMA5 capture",
++		.dynamic = 1,
++		.dpcm_capture = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma5_capture),
++	},
++
++	[6] = {
++		.name = "DMA6 capture",
++		.stream_name = "DMA6 capture",
++		.dynamic = 1,
++		.dpcm_capture = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma6_capture),
++	},
++
++	[7] = {
++		.name = "DMA7 capture",
++		.stream_name = "DMA7 capture",
++		.dynamic = 1,
++		.dpcm_capture = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma7_capture),
++	},
++
++	[8] = {
++		.name = "DMA8 capture",
++		.stream_name = "DMA8 capture",
++		.dynamic = 1,
++		.dpcm_capture = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma8_capture),
++	},
++
++	[9] = {
++		.name = "DMA9 capture",
++		.stream_name = "DMA9 capture",
++		.dynamic = 1,
++		.dpcm_capture = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma9_capture),
++	},
++
++	/*BE DAIS*/
++	[10] = {
++		.name = "BAIC0",
++		.stream_name = "BAIC0",
++		.ops = &baic_ops,
++		.be_hw_params_fixup = NULL,
++		.no_pcm = 1,
++		.dpcm_capture = 1,
++		.dpcm_playback = 1,
++		SND_SOC_DAILINK_REG(inno_icodec),
++	},
++
++	[11] = {
++		.name = "DMIC",
++		.stream_name = "DMIC",
++		.no_pcm = 1,
++		.capture_only = 1,
++		SND_SOC_DAILINK_REG(dmic),
++	},
++
++	[12] = {
++		.name = "BAIC4",
++		.stream_name = "BAIC4",
++		.ops = &baic_ops,
++		.be_hw_params_fixup = NULL,
++		.no_pcm = 1,
++		.dpcm_capture = 1,
++		.dpcm_playback = 1,
++		SND_SOC_DAILINK_REG(baic4_bt),
++	},
++};
++
++static struct snd_soc_aux_dev x2000_aux_dev = {
++	.dlc = COMP_AUX( "134dc000.as-mixer"),
++};
++
++static int audio_clk_init(struct device *dev)
++{
++	struct clk *clk, *parent;
++	char clk_name[16];
++	unsigned long rate;
++	int i;
++
++	parent = clk_get(dev, "epll");
++	if(IS_ERR_OR_NULL(parent)) {
++		dev_err(dev, "Get epll clk failed!\n");
++		return -EINVAL;
++	}
++	for(i = 0; i < 4; i++) {
++		sprintf(clk_name, "div_i2s%d", i);
++		clk = clk_get(dev, clk_name);
++		if(IS_ERR_OR_NULL(clk)) {
++			dev_err(dev, "Get %s clk failed!\n", clk_name);
++			return -EINVAL;
++		}
++		rate = clk_get_rate(clk);
++		clk_set_parent(clk, parent);
++		clk_set_rate(clk, rate);
++		clk_put(clk);
++	}
++	clk_put(parent);
++
++	return 0;
++}
++
++
++static int snd_x2000_probe(struct platform_device *pdev)
++{
++	struct snd_soc_card *card;
++	int ret;
++	enum of_gpio_flags flags;
++	card = (struct snd_soc_card *)devm_kzalloc(&pdev->dev,
++			sizeof(struct snd_soc_card), GFP_KERNEL);
++	if (!card)
++		return -ENOMEM;
++
++	card->dapm_widgets = dapm_widgets;
++	card->num_dapm_widgets = ARRAY_SIZE(dapm_widgets);
++	card->dapm_routes = audio_map;
++	card->num_dapm_routes = ARRAY_SIZE(audio_map);
++	card->controls = card_snd_controls;
++	card->num_controls = ARRAY_SIZE(card_snd_controls);
++	card->dai_link = x2000_dais;
++	card->num_links = ARRAY_SIZE(x2000_dais);
++	card->owner = THIS_MODULE;
++	card->dev = &pdev->dev;
++	card->aux_dev = &x2000_aux_dev;
++	card->num_aux_devs = 1;
++
++	ret = snd_soc_of_parse_card_name(card, "ingenic,model");
++	if (ret)
++		return ret;
++
++	ret = snd_soc_register_card(card);
++	if (ret) {
++		dev_err(&pdev->dev, "snd_soc_register_card failed %d\n", ret);
++		return ret;
++	}
++
++	ret = audio_clk_init(card->dev);
++	if(ret)
++		return ret;
++	icodec_spk_power = kmalloc(sizeof(*icodec_spk_power), GFP_KERNEL);
++	if(!icodec_spk_power) {
++		return -ENOMEM;
++	}
++	icodec_spk_power->spk_gpio = of_get_named_gpio_flags(pdev->dev.of_node, "ingenic,spken-gpio", 0, &flags);
++	if (gpio_is_valid(icodec_spk_power->spk_gpio)) {
++		unsigned long init_flags;
++		icodec_spk_power->spk_en_level = (flags == OF_GPIO_ACTIVE_LOW ? 0 : 1);
++		init_flags = (flags == OF_GPIO_ACTIVE_LOW ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW);
++		ret = devm_gpio_request_one(&pdev->dev, icodec_spk_power->spk_gpio, init_flags, "Speaker_en");
++		if (ret)
++			pr_warn("Speaker enable pin(%d) request failed\n",icodec_spk_power->spk_gpio);
++		else
++			pr_info("Speaker enable pin(%d) request ok\n", icodec_spk_power->spk_gpio);
++		/* icodec_playback_power = icodec_playback_power_ctr; */
++		set_playback_pwr_callback(icodec_playback_power_ctr);
++	}
++	platform_set_drvdata(pdev, card);
++	dev_info(&pdev->dev, "Sound Card successed\n");
++
++	return ret;
++}
++
++static int snd_x2000_remove(struct platform_device *pdev)
++{
++	struct snd_soc_card *card = platform_get_drvdata(pdev);
++	snd_soc_unregister_card(card);
++	platform_set_drvdata(pdev, NULL);
++	return 0;
++}
++
++static const struct of_device_id x2000_match_table[] = {
++	{ .compatible = "ingenic,x2000-sound", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, x2000_match_table);
++
++static struct platform_driver snd_x2000_driver = {
++	.driver = {
++		.owner = THIS_MODULE,
++		.name = "x2000-sound",
++		.of_match_table = x2000_match_table
++	},
++	.probe = snd_x2000_probe,
++	.remove = snd_x2000_remove,
++};
++module_platform_driver(snd_x2000_driver);
++
++MODULE_AUTHOR("cli<chen.li@ingenic.com>");
++MODULE_DESCRIPTION("ALSA SoC X2000 Snd Card");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/sound/soc/ingenic/boards/halley6.c b/module_drivers/sound/soc/ingenic/boards/halley6.c
+new file mode 100644
+index 000000000..751d4b7a1
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/boards/halley6.c
+@@ -0,0 +1,225 @@
++ /*
++ * Copyright (C) 2014 Ingenic Semiconductor Co., Ltd.
++ *	http://www.ingenic.com
++ * Author: cli <chen.li@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <sound/soc.h>
++#include <sound/jack.h>
++#include <linux/gpio.h>
++#include "../as-v1/asoc-aic.h"
++#include <sound/soc.h>
++#include <linux/delay.h>
++
++static int x1600_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++/*	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;*/
++	struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd,0);
++	int ret;
++	int id = 0;
++	int sysclk = 24576000;
++	int div = 24576000 / params_rate(params) / 64;
++	int aic_mode = 0, codec_mode = 0;
++
++#ifdef CONFIG_SND_ASOC_INGENIC_MASTER_MODE
++	aic_mode |= SND_SOC_DAIFMT_CBS_CFM;
++	codec_mode |= SND_SOC_DAIFMT_CBS_CFM;
++#endif
++#ifdef CONFIG_SND_ASOC_INGENIC_SLAVE_MODE
++	aic_mode |= SND_SOC_DAIFMT_CBM_CFM;
++	codec_mode |= SND_SOC_DAIFMT_CBM_CFM;
++#endif
++#ifdef CONFIG_SND_ASOC_INGENIC_I2S_MODE
++	aic_mode |= SND_SOC_DAIFMT_I2S;
++	codec_mode |= SND_SOC_DAIFMT_I2S;
++#endif
++#ifdef CONFIG_SND_ASOC_INGENIC_LEFT_J_MODE
++	aic_mode |= SND_SOC_DAIFMT_MSB;
++	codec_mode |= SND_SOC_DAIFMT_LEFT_J;
++#endif
++
++	ret = snd_soc_dai_set_fmt(cpu_dai, aic_mode);
++	if (ret)
++		return ret;
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++		id |= INGENIC_I2S_PLAYBACK;
++	else
++		id |= INGENIC_I2S_CAPTURE;
++
++	ret = snd_soc_dai_set_sysclk(cpu_dai, id, sysclk, SND_SOC_CLOCK_OUT);
++	if (ret)
++		return ret;
++
++	ret = snd_soc_dai_set_clkdiv(cpu_dai, id, div);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static int x1600_i2s_hw_free(struct snd_pcm_substream *substream)
++{
++	/*notify release pll*/
++	return 0;
++};
++
++static struct snd_soc_ops x1600_i2s_ecdc_ops = {
++	.hw_params = x1600_i2s_hw_params,
++	.hw_free = x1600_i2s_hw_free,
++};
++
++struct gpio_desc *en_3v3_gpiod;
++
++static int x1600_i2s_ecdc_dai_link_init(struct snd_soc_pcm_runtime *rtd)
++{
++	if (IS_ERR(en_3v3_gpiod))
++		return PTR_ERR(en_3v3_gpiod);
++	gpiod_set_value_cansleep(en_3v3_gpiod, 1);
++
++	return 0;
++}
++
++static int snd_x1600_probe(struct platform_device *pdev)
++{
++	int i, ret = 0;
++	struct snd_soc_card *card;
++	struct snd_soc_dai_link *dai_link;
++	struct device_node *snd_node = pdev->dev.of_node;
++	struct snd_soc_dai_link_component *cpus_comp;
++	struct snd_soc_dai_link_component *platforms_comp;
++	struct snd_soc_dai_link_component *codecs_comp;
++	int num_links;
++
++	num_links = of_property_count_strings(snd_node, "ingenic,dai-link");
++	if (num_links < 0)
++		return num_links;
++	BUG_ON(!num_links);
++
++	card = (struct snd_soc_card *)devm_kzalloc(&pdev->dev,
++			sizeof(struct snd_soc_card), GFP_KERNEL);
++	if (!card)
++		return -ENOMEM;
++
++	dai_link = (struct snd_soc_dai_link *)devm_kzalloc(&pdev->dev,
++			sizeof(struct snd_soc_dai_link) * num_links, GFP_KERNEL);
++	if (!dai_link)
++		return -ENOMEM;
++
++	card->num_links = num_links;
++	card->dai_link = dai_link;
++	card->owner = THIS_MODULE;
++	card->dev = &pdev->dev;
++	ret = snd_soc_of_parse_card_name(card, "ingenic,model");
++	if (ret)
++		return ret;
++
++	en_3v3_gpiod = devm_gpiod_get_optional(card->dev, "ingenic,en3v3", GPIOD_OUT_LOW);
++
++	for (i = 0; i < card->num_links; i++) {
++		dai_link[i].cpus = devm_kzalloc(&pdev->dev,sizeof(struct snd_soc_dai_link_component), GFP_KERNEL);
++		dai_link[i].codecs = devm_kzalloc(&pdev->dev,sizeof(struct snd_soc_dai_link_component), GFP_KERNEL);
++		dai_link[i].platforms = devm_kzalloc(&pdev->dev,sizeof(struct snd_soc_dai_link_component), GFP_KERNEL);
++
++		dai_link[i].num_cpus = 1;
++		dai_link[i].num_platforms = 1;
++		dai_link[i].num_codecs = 1;
++		dai_link[i].cpus->of_node = of_parse_phandle(snd_node, "ingenic,cpu-dai" , i);
++		dai_link[i].platforms->of_node = of_parse_phandle(snd_node, "ingenic,platform", i);
++		dai_link[i].codecs->of_node = of_parse_phandle(snd_node, "ingenic,codec", i);
++
++		ret = of_property_read_string_index(snd_node, "ingenic,codec-dai", i,
++				&(dai_link[i].codecs->dai_name));
++
++		if (ret || !dai_link[i].cpus->of_node ||
++				!dai_link[i].codecs->of_node ||
++				!dai_link[i].platforms->of_node)
++			return -ENODEV;
++		ret = of_property_read_string_index(snd_node, "ingenic,dai-link", i,
++				&(dai_link[i].name));
++		if (ret)
++			return -ENODEV;
++		ret = of_property_read_string_index(snd_node, "ingenic,stream", i,
++				&(dai_link[i].stream_name));
++		if (ret)
++			dai_link[i].stream_name = dai_link[i].name;
++
++		dev_dbg(&pdev->dev, "dai_link %s\n", dai_link[i].name);
++		dev_dbg(&pdev->dev, "stream_name %s\n", dai_link[i].stream_name);
++		dev_dbg(&pdev->dev, "cpu %s(%s)\n", dai_link[i].cpus->of_node->name,
++				dai_link[i].cpus->of_node->full_name);
++		dev_dbg(&pdev->dev, "platform %s(%s)\n", dai_link[i].platforms->of_node->name,
++				dai_link[i].platforms->of_node->full_name);
++		dev_dbg(&pdev->dev, "codec dai %s\n", dai_link[i].codecs->dai_name);
++		dev_dbg(&pdev->dev, "codec %s(%s)\n", dai_link[i].codecs->of_node->name,
++				dai_link[i].codecs->of_node->full_name);
++
++		if (!strcmp(dai_link[i].name, "i2s-ecodec")) {
++			dai_link->ops = &x1600_i2s_ecdc_ops;
++			dai_link->init = x1600_i2s_ecdc_dai_link_init;
++		}
++	}
++
++	ret = snd_soc_register_card(card);
++	if (ret) {
++		dev_err(&pdev->dev, "snd_soc_register_card failed %d\n", ret);
++		return ret;
++	}
++
++	platform_set_drvdata(pdev, card);
++
++	dev_info(&pdev->dev, "Sound Card successed\n");
++
++	return ret;
++}
++
++static int snd_x1600_remove(struct platform_device *pdev)
++{
++	struct snd_soc_card *card = platform_get_drvdata(pdev);
++
++	snd_soc_unregister_card(card);
++	platform_set_drvdata(pdev, NULL);
++
++	return 0;
++}
++
++static const struct of_device_id sound_dt_match[] = {
++	{ .compatible = "ingenic,x1600-sound", .data = NULL },
++	{},
++};
++MODULE_DEVICE_TABLE(of, sound_dt_match);
++
++static struct platform_driver snd_x1600_driver = {
++	.driver = {
++		.owner = THIS_MODULE,
++		.name = "ingenic-halley6",
++		.pm = &snd_soc_pm_ops,
++		.of_match_table = of_match_ptr(sound_dt_match),
++	},
++	.probe = snd_x1600_probe,
++	.remove = snd_x1600_remove,
++};
++module_platform_driver(snd_x1600_driver);
++
++MODULE_AUTHOR("cli<chen.li@ingenic.com>");
++MODULE_DESCRIPTION("ALSA SoC FPGA Snd Card");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/sound/soc/ingenic/boards/hippo-board.c b/module_drivers/sound/soc/ingenic/boards/hippo-board.c
+new file mode 100644
+index 000000000..616d53056
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/boards/hippo-board.c
+@@ -0,0 +1,258 @@
++/*
++ * Copyright (C) 2014 Ingenic Semiconductor Co., Ltd.
++ *	http://www.ingenic.com
++ * Author: zhihao.xiao <zhihao.xiao@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <sound/soc.h>
++#include <sound/jack.h>
++#include <linux/gpio.h>
++#include <linux/of_gpio.h>
++#include <sound/soc.h>
++#include "../as-v1/asoc-aic.h"
++
++struct x2500_icdc {
++	struct snd_soc_card card;
++	int spk_gpio;
++	int spk_en_level;
++};
++
++static struct x2500_icdc *icodec_spk_power;
++typedef void (*p_icodec_playback_power)(bool);
++extern void set_playback_pwr_callback(p_icodec_playback_power func);
++
++int x2500_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) {
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++	struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd,0);
++	int ret;
++	int sysclk = 24000000;
++	int clk_id = 0;
++
++	ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_CBM_CFM);
++	if (ret)
++		return ret;
++
++	if(substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++		clk_id |= INGENIC_I2S_PLAYBACK;
++	else
++		clk_id |= INGENIC_I2S_CAPTURE;
++
++	clk_id |= INGENIC_I2S_INNER_CODEC;
++
++	sysclk = 256 * params_rate(params);
++	ret = snd_soc_dai_set_sysclk(cpu_dai, clk_id, sysclk, SND_SOC_CLOCK_OUT);
++	if (ret)
++		return ret;
++	return 0;
++};
++
++int x2500_i2s_hw_free(struct snd_pcm_substream *substream)
++{
++	/*notify release pll*/
++	return 0;
++};
++
++static struct snd_soc_ops x2500_i2s_cdc_ops = {
++	.hw_params = x2500_i2s_hw_params,
++	.hw_free = x2500_i2s_hw_free,
++};
++
++
++void icodec_playback_power_ctr(bool enable)
++{
++	if (!gpio_is_valid(icodec_spk_power->spk_gpio))
++		return;
++
++	if (enable) {
++		gpio_direction_output(icodec_spk_power->spk_gpio, icodec_spk_power->spk_en_level);
++	} else {
++		gpio_direction_output(icodec_spk_power->spk_gpio, !icodec_spk_power->spk_en_level);
++	}
++}
++
++
++static const struct snd_soc_dapm_widget x2500_dapm_widgets[] = {
++	SND_SOC_DAPM_SPK("Speaker", NULL),
++	SND_SOC_DAPM_MIC("MICBIAS", NULL),
++	SND_SOC_DAPM_MIC("MICL", NULL),
++	SND_SOC_DAPM_MIC("MICR", NULL),
++};
++
++static int x2500_i2s_cdc_dai_link_init(struct snd_soc_pcm_runtime *rtd)
++{
++	struct snd_soc_card *card = rtd->card;
++	struct snd_soc_dapm_context *dapm = &card->dapm;
++
++	snd_soc_dapm_enable_pin(dapm, "Speaker");
++	snd_soc_dapm_enable_pin(dapm, "MICBIAS");
++	snd_soc_dapm_enable_pin(dapm, "MICL");
++	snd_soc_dapm_enable_pin(dapm, "MICR");
++
++	return 0;
++}
++
++static int snd_x2500_probe(struct platform_device *pdev)
++{
++	struct device_node *snd_node = pdev->dev.of_node;
++	struct x2500_icdc *x2500;
++	struct snd_soc_card *card;
++	struct snd_soc_dai_link *dai_link;
++	struct snd_soc_dai_link_component *cpus_comp;
++	struct snd_soc_dai_link_component *platforms_comp;
++	struct snd_soc_dai_link_component *codecs_comp;
++
++	enum of_gpio_flags flags;
++	int num_links;
++	int ret = 0, i;
++
++	num_links = of_property_count_strings(snd_node, "ingenic,dai-link");
++	if (num_links < 0)
++		return num_links;
++	BUG_ON(!num_links);
++
++	x2500 = (struct x2500_icdc *)devm_kzalloc(&pdev->dev,
++			sizeof(struct x2500_icdc) +
++			sizeof(struct snd_soc_dai_link) * num_links,
++			GFP_KERNEL);
++	if (!x2500)
++		return -ENOMEM;
++	card = &x2500->card;
++	dai_link = (struct snd_soc_dai_link *)(x2500 + 1);
++
++	card->num_dapm_widgets = ARRAY_SIZE(x2500_dapm_widgets);
++	card->dapm_widgets = x2500_dapm_widgets;
++	card->num_links = num_links;
++	card->dai_link = dai_link;
++	card->owner = THIS_MODULE;
++	card->dev = &pdev->dev;
++
++
++	ret = snd_soc_of_parse_card_name(card, "ingenic,model");
++	if (ret)
++		return ret;
++
++	ret = snd_soc_of_parse_audio_routing(card, "ingenic,audio-routing");
++	if (ret)
++		return ret;
++
++	x2500->spk_gpio = of_get_named_gpio_flags(card->dev->of_node, "ingenic,spken-gpio", 0, &flags);
++	icodec_spk_power = x2500;
++	if (gpio_is_valid(x2500->spk_gpio)) {
++		unsigned long init_flags;
++		x2500->spk_en_level = (flags == OF_GPIO_ACTIVE_LOW ? 0 : 1);
++		init_flags = (flags == OF_GPIO_ACTIVE_LOW ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW);
++		ret = devm_gpio_request_one(card->dev, x2500->spk_gpio, init_flags, "Speaker_en");
++		if (ret)
++			printk("dorado speaker enable pin(%d) request failed\n",x2500->spk_gpio);
++		else
++			printk("dorado speaker enable pin(%d) request ok\n", x2500->spk_gpio);
++
++		/* icodec_playback_power = icodec_playback_power_ctr; */
++		set_playback_pwr_callback(icodec_playback_power_ctr);
++	}
++//TODO
++	for (i = 0; i < card->num_links; i++) {
++		dai_link[i].cpus = devm_kzalloc(&pdev->dev,sizeof(struct snd_soc_dai_link_component), GFP_KERNEL);
++		dai_link[i].codecs = devm_kzalloc(&pdev->dev,sizeof(struct snd_soc_dai_link_component), GFP_KERNEL);
++		dai_link[i].platforms = devm_kzalloc(&pdev->dev,sizeof(struct snd_soc_dai_link_component), GFP_KERNEL);
++
++		dai_link[i].num_cpus = 1;
++		dai_link[i].num_platforms = 1;
++		dai_link[i].num_codecs = 1;
++		dai_link[i].cpus->of_node = of_parse_phandle(snd_node, "ingenic,cpu-dai" , i);
++		dai_link[i].platforms->of_node = of_parse_phandle(snd_node, "ingenic,platform", i);
++		dai_link[i].codecs->of_node = of_parse_phandle(snd_node, "ingenic,codec", i);
++		ret = of_property_read_string_index(snd_node, "ingenic,codec-dai", i,
++				&(dai_link[i].codecs->dai_name));
++		if (ret || !dai_link[i].cpus->of_node ||
++				!dai_link[i].codecs->of_node ||
++				!dai_link[i].platforms->of_node)
++			return -ENODEV;
++		ret = of_property_read_string_index(snd_node, "ingenic,dai-link", i,
++				&(dai_link[i].name));
++		printk("%s:%d %s\n", __func__, __LINE__, dai_link[i].name);
++		if (ret)
++			return -ENODEV;
++		ret = of_property_read_string_index(snd_node, "ingenic,stream", i,
++				&(dai_link[i].stream_name));
++		if (ret)
++			dai_link[i].stream_name = dai_link[i].name;
++/*
++		dev_dbg(&pdev->dev, "dai_link %s\n", dai_link[i].name);
++		dev_dbg(&pdev->dev, "stream_name %s\n", dai_link[i].stream_name);
++		dev_dbg(&pdev->dev, "cpu %s(%s)\n", dai_link[i].cpus,
++				dai_link[i].cpu_of_node->full_name);
++		dev_dbg(&pdev->dev, "platform %s(%s)\n", dai_link[i].platform_of_node->name,
++				dai_link[i].platform_of_node->full_name);
++		dev_dbg(&pdev->dev, "codec dai %s\n", dai_link[i].codec_dai_name);
++		dev_dbg(&pdev->dev, "codec %s(%s)\n", dai_link[i].codec_of_node->name,
++				dai_link[i].codec_of_node->full_name);
++*/
++
++
++		if (!strcmp(dai_link[i].name, "i2s-icodec") ||
++				!strcmp(dai_link[i].codecs->dai_name, "dmic")) {
++			dai_link->ops = &x2500_i2s_cdc_ops;
++			dai_link->init = x2500_i2s_cdc_dai_link_init;
++		}
++	}
++	ret = snd_soc_register_card(card);
++	if (ret) {
++		dev_err(&pdev->dev, "snd_soc_register_card failed %d\n", ret);
++		return ret;
++	}
++
++	platform_set_drvdata(pdev, x2500);
++	dev_info(&pdev->dev, "Sound Card successed\n");
++
++	return ret;
++}
++
++static int snd_x2500_remove(struct platform_device *pdev)
++{
++	struct x2500_icdc *x2500 = platform_get_drvdata(pdev);
++	snd_soc_unregister_card(&x2500->card);
++	platform_set_drvdata(pdev, NULL);
++	devm_kfree(&pdev->dev, x2500);
++	return 0;
++}
++
++static const struct of_device_id sound_dt_match[] = {
++	{ .compatible = "ingenic,x2500-sound", .data = NULL },
++	{},
++};
++MODULE_DEVICE_TABLE(of, sound_dt_match);
++
++static struct platform_driver snd_x2500_driver = {
++	.driver = {
++		.owner = THIS_MODULE,
++		.name = "x2500-sound",
++		.pm = &snd_soc_pm_ops,
++		.of_match_table = of_match_ptr(sound_dt_match),
++	},
++	.probe = snd_x2500_probe,
++	.remove = snd_x2500_remove,
++};
++module_platform_driver(snd_x2500_driver);
++
++MODULE_AUTHOR("zhxiao<zhihao.xiao@ingenic.com>");
++MODULE_DESCRIPTION("ALSA SoC x2500 Snd Card");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/sound/soc/ingenic/boards/kale_v10.c b/module_drivers/sound/soc/ingenic/boards/kale_v10.c
+new file mode 100644
+index 000000000..ed3541066
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/boards/kale_v10.c
+@@ -0,0 +1,624 @@
++ /*
++ * Copyright (C) 2017 Ingenic Semiconductor Co., Ltd.
++ *	http://www.ingenic.com
++ * Author: cli <chen.li@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <sound/soc.h>
++#include <sound/pcm_params.h>
++#include <linux/clk.h>
++#include "../as-v2/as-baic.h"
++#include <linux/gpio.h>
++#include <linux/delay.h>
++#include <linux/of_gpio.h>
++
++struct icodec_spk_power {
++	int spk_gpio;
++	unsigned char spk_en_level;
++};
++static struct icodec_spk_power *icodec_spk_power;
++
++typedef void (*p_icodec_playback_power)(bool);
++extern void set_playback_pwr_callback(p_icodec_playback_power func);
++
++
++static const struct snd_soc_dapm_route audio_map[] = {
++	{ "BAIC0 playback", NULL, "LO0_MUX" },
++	{ "BAIC4 playback", NULL, "LO4_MUX" },
++
++	{ "LI0", NULL, "DMIC capture" },
++	{ "LI2", NULL, "BAIC0 capture" },
++	{ "LI6", NULL, "BAIC4 capture" },
++
++	{ "LI8", NULL, "DMA0" },
++	{ "LI9", NULL, "DMA1" },
++	{ "LI10", NULL, "DMA2" },
++	{ "LI11", NULL, "DMA3" },
++	{ "LI12", NULL, "DMA4" },
++
++	{ "DMA5", NULL, "LO5_MUX"},
++	{ "DMA6", NULL, "LO6_MUX"},
++	{ "DMA7", NULL, "LO7_MUX"},
++	{ "DMA8", NULL, "LO8_MUX"},
++	{ "DMA9", NULL, "LO9_MUX"},
++
++	{ "MIX0", NULL, "LO10_MUX"},
++	{ "MIX0", NULL, "LO11_MUX"},
++	{ "LI7",  NULL, "MIX0"},
++
++	{"DMIC capture", NULL, "DMIC"},
++	{"BAIC4 capture", NULL, "PCMIN"},
++	{"PCMOUT", NULL, "BAIC4 playback"},
++};
++
++static const struct snd_soc_dapm_widget dapm_widgets[] = {
++	SND_SOC_DAPM_INPUT("DMIC"),
++	SND_SOC_DAPM_INPUT("PCMIN"),
++	SND_SOC_DAPM_OUTPUT("PCMOUT"),
++};
++
++struct codec_format_enum {
++	struct soc_enum e;
++	int baic_id;
++	unsigned int *format;
++};
++
++unsigned int codec_format[MAX_BAIC_NUM] = {
++	/*baic0 icodec format*/
++	SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF|SND_SOC_DAIFMT_CBS_CFS,
++	/*baic1 format*/
++	SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF|SND_SOC_DAIFMT_CBS_CFS,
++	/*baic2 format*/
++	SND_SOC_DAIFMT_DSP_B|SND_SOC_DAIFMT_NB_NF|SND_SOC_DAIFMT_CBS_CFS|BAIC_DAIFMT_SEL_TDM1,
++	/*baic3 format*/
++	SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF|SND_SOC_DAIFMT_CBS_CFS,
++	/*baic4 pcm format*/
++	SND_SOC_DAIFMT_DSP_A|SND_SOC_DAIFMT_IB_NF|SND_SOC_DAIFMT_CBM_CFM|BAIC_DAIFMT_SEL_DSP,
++};
++static const char *const baic_format_item_name[BAIC_SUPPORT_FORMAT_MAX] = {
++	"PCMA", "PCMB","DSPA","DSPB","TDM1A","TDM1B","TDM2A","TDM2B","I2S","LEFT","RIGHT"
++};
++static const unsigned int baic_format_item_value[BAIC_SUPPORT_FORMAT_MAX] = {
++	SND_SOC_DAIFMT_DSP_A|BAIC_DAIFMT_SEL_PCM,
++	SND_SOC_DAIFMT_DSP_B|BAIC_DAIFMT_SEL_PCM,
++	SND_SOC_DAIFMT_DSP_A|BAIC_DAIFMT_SEL_DSP,
++	SND_SOC_DAIFMT_DSP_B|BAIC_DAIFMT_SEL_DSP,
++	SND_SOC_DAIFMT_DSP_A|BAIC_DAIFMT_SEL_TDM1,
++	SND_SOC_DAIFMT_DSP_B|BAIC_DAIFMT_SEL_TDM1,
++	SND_SOC_DAIFMT_DSP_A|BAIC_DAIFMT_SEL_TDM2,
++	SND_SOC_DAIFMT_DSP_B|BAIC_DAIFMT_SEL_TDM2,
++	SND_SOC_DAIFMT_I2S,
++	SND_SOC_DAIFMT_LEFT_J,
++	SND_SOC_DAIFMT_RIGHT_J,
++};
++static int baic_format_get_enum(struct snd_kcontrol *kcontrol,
++		struct snd_ctl_elem_value *ucontrol)
++{
++	struct codec_format_enum *e = (struct codec_format_enum *)kcontrol->private_value;
++	unsigned int format = (*e->format) & (SND_SOC_DAIFMT_FORMAT_MASK | BAIC_DAIFMT_SEL_MASK);
++	int i;
++	for(i=0; i < BAIC_SUPPORT_FORMAT_MAX; i++) {
++		if(format == baic_format_item_value[i]) {
++			ucontrol->value.enumerated.item[0] = i;
++			return 0;
++		}
++	}
++	return -EINVAL;
++}
++
++static int baic_format_put_enum(struct snd_kcontrol *kcontrol,
++		struct snd_ctl_elem_value *ucontrol)
++{
++	struct codec_format_enum *e = (struct codec_format_enum *)kcontrol->private_value;
++	unsigned int item = ucontrol->value.enumerated.item[0];
++
++	(*e->format) &= ~(SND_SOC_DAIFMT_FORMAT_MASK | BAIC_DAIFMT_SEL_MASK);
++	(*e->format) |= baic_format_item_value[item];
++
++	return 0;
++}
++
++static struct codec_format_enum codec_format_enum[] = {	/*not const*/
++#define BAIC_FORMAT_ENUM(_baic_id)	\
++	{ \
++		.e = SOC_ENUM_SINGLE_EXT(BAIC_SUPPORT_FORMAT_MAX, baic_format_item_name), \
++		.baic_id = _baic_id,	\
++		.format = &codec_format[(_baic_id)],	\
++	}
++	BAIC_FORMAT_ENUM(0),
++	BAIC_FORMAT_ENUM(1),
++	BAIC_FORMAT_ENUM(2),
++	BAIC_FORMAT_ENUM(3),
++	BAIC_FORMAT_ENUM(4),
++#undef BAIC_FORMAT_ENUM
++};
++
++static const struct snd_kcontrol_new card_snd_controls[] = {
++#define FORMAT0 "baic0_fmt"
++#define FORMAT1 "baic1_fmt"
++#define FORMAT2 "baic2_fmt"
++#define FORMAT3 "baic3_fmt"
++#define FORMAT4 "baic4_fmt"
++#define CODEC_FORMAT_ENUM_EXT(N) \
++	SOC_ENUM_EXT(FORMAT##N,		\
++		codec_format_enum[(N)], \
++		baic_format_get_enum,	\
++		baic_format_put_enum)
++	CODEC_FORMAT_ENUM_EXT(0),
++	CODEC_FORMAT_ENUM_EXT(1),
++	CODEC_FORMAT_ENUM_EXT(2),
++	CODEC_FORMAT_ENUM_EXT(3),
++	CODEC_FORMAT_ENUM_EXT(4),
++#undef FORMAT0
++#undef FORMAT1
++#undef FORMAT2
++#undef FORMAT3
++#undef FORMAT4
++#undef CODEC_FORMAT_ENUM_EXT
++};
++
++typedef enum slot_width {
++	slot_width_auto = 0,
++	slot_width_16 = 16,
++	slot_width_32 = 32,
++	slot_width_64 = 64,
++} slot_width_t;
++
++slot_width_t codec_slot_width[MAX_BAIC_NUM] = {
++	slot_width_auto,
++	slot_width_auto,
++	slot_width_32,
++	slot_width_32,
++	slot_width_auto
++};
++
++static int  get_baic_id(struct snd_soc_dai *dai)
++{
++	int id = -1;
++	const char *name = dai->driver->name;
++
++	sscanf(&name[strlen("BAIC")], "%d", &id);
++
++	return id;
++}
++
++static int baic_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++	struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
++	struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
++	int bclk_div = 0, sysclk = 24000000, bclk = 0, codec_slots = 0,
++	    sync_div = 0, sync_w_div = 1, tx_msk = 0, rx_msk = 0;
++	bool is_playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? true : false;
++	int divid_dir = is_playback ? DIVID_DIR_T : 0;
++	int clkid = is_playback ? CLKID_SYSCLK_T : CLKID_SYSCLK_R;
++	int channels = params_channels(params);
++	int fmt_width = snd_pcm_format_width(params_format(params));
++	int id = get_baic_id(cpu_dai);
++	int slot_width = codec_slot_width[id];
++	unsigned int format = codec_format[id];
++	int ret;
++
++	format |= is_playback ? BAIC_DAIFMT_T : BAIC_DAIFMT_R;
++	ret = snd_soc_runtime_set_dai_fmt(rtd, format);
++	if (ret)
++		return ret;
++
++	switch(format & SND_SOC_DAIFMT_FORMAT_MASK){
++		case SND_SOC_DAIFMT_LEFT_J:
++		case SND_SOC_DAIFMT_I2S:
++		case SND_SOC_DAIFMT_RIGHT_J:
++			if(fmt_width > 16) {
++				sync_div = 64;
++			} else if(fmt_width > 8) {
++				sync_div = 32;
++			} else {
++				sync_div = 16;
++			}
++			break;
++		case SND_SOC_DAIFMT_DSP_B:
++		case SND_SOC_DAIFMT_DSP_A:
++			if(!slot_width) {
++				slot_width = (fmt_width > 16) ? 32 : 16;
++			}
++			if (is_playback)
++				tx_msk = (1 << channels) - 1;
++			else
++				rx_msk = (1 << channels) - 1;
++			ret = snd_soc_dai_set_clkdiv(cpu_dai, DIVID_SYNC_W|divid_dir, sync_w_div);
++			if (ret)
++				return ret;
++			ret = snd_soc_dai_set_tdm_slot(cpu_dai, tx_msk, rx_msk, channels, slot_width);
++			if (ret)
++				return ret;
++
++			if((channels == 8) && ((format&BAIC_DAIFMT_SEL_TDM2) == BAIC_DAIFMT_SEL_TDM2)) {
++				sync_div = slot_width * 4;
++				/*for ak4458/ak5558*/
++				codec_slots = 4;
++			} else {
++				sync_div = slot_width * channels;
++				codec_slots = channels;
++			}
++			ret = snd_soc_dai_set_tdm_slot(codec_dai, tx_msk, rx_msk, codec_slots, slot_width);
++			if (ret != 0 && ret != -ENOTSUPP) {
++				dev_warn(codec_dai->dev,
++					 "ASoC: Failed to set tdm slot: %d\n", ret);
++				return ret;
++			}
++			break;
++		default:
++			printk("%s codec config err!\n",__func__);
++			return -EPERM;
++
++	}
++
++	ret = snd_soc_dai_set_clkdiv(cpu_dai, DIVID_SYNC|divid_dir, sync_div);
++	if (ret)
++		return ret;
++
++	bclk = params_rate(params) * sync_div;
++	if(id == 0 || id == 1) {
++		/*for baic0: sysclk = 256 * sample_rate */
++		sysclk = 256 * params_rate(params);
++	}
++
++	bclk_div = (sysclk + bclk - 1) / bclk;
++	/* bclk div value must be even */
++	if(bclk_div%2) {
++		sysclk = (bclk_div+1)*bclk;
++		bclk_div += 1;
++	}
++
++	ret = snd_soc_dai_set_sysclk(cpu_dai, clkid, sysclk, SND_SOC_CLOCK_OUT);
++	if (ret)
++		return ret;
++
++	ret = snd_soc_dai_set_clkdiv(cpu_dai, DIVID_BCLK|divid_dir, bclk_div);
++	if (ret)
++		return ret;
++
++	return 0;
++};
++
++
++void icodec_playback_power_ctr(bool enable)
++{
++	if (!gpio_is_valid(icodec_spk_power->spk_gpio))
++		return;
++	if (enable) {
++		gpio_direction_output(icodec_spk_power->spk_gpio, icodec_spk_power->spk_en_level);
++	} else{
++		gpio_direction_output(icodec_spk_power->spk_gpio, !icodec_spk_power->spk_en_level);
++	}
++}
++
++static struct snd_soc_ops baic_ops = {
++	.hw_params = baic_hw_params,
++};
++
++SND_SOC_DAILINK_DEFS(dma0_playback,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA0")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma1_playback,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA1")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma2_playback,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA2")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma3_playback,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA3")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma4_playback,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA4")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma5_capture,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA5")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma6_capture,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA6")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma7_capture,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA7")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma8_capture,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA8")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(dma9_capture,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMA9")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()),
++		DAILINK_COMP_ARRAY(COMP_PLATFORM("134d0000.as-platform")));
++
++SND_SOC_DAILINK_DEFS(inno_icodec,
++		DAILINK_COMP_ARRAY(COMP_CPU("BAIC0")),
++		DAILINK_COMP_ARRAY(COMP_CODEC("10020000.icodec", "icodec")));
++
++SND_SOC_DAILINK_DEFS(dmic,
++		DAILINK_COMP_ARRAY(COMP_CPU("DMIC")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()));
++
++SND_SOC_DAILINK_DEFS(baic4_bt,
++		DAILINK_COMP_ARRAY(COMP_CPU("BAIC4")),
++		DAILINK_COMP_ARRAY(COMP_DUMMY()));
++
++static struct snd_soc_dai_link x2000_dais[] = {
++	/*FE DAIS*/
++	[0] = {
++		.name = "DMA0 playback",
++		.stream_name = "DMA0 playback",
++		.dynamic = 1,
++		.dpcm_playback = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma0_playback),
++	},
++
++	[1] = {
++		.name = "DMA1 playback",
++		.stream_name = "DMA1 playback",
++		.dynamic = 1,
++		.dpcm_playback = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma1_playback),
++	},
++
++	[2] = {
++		.name = "DMA2 playback",
++		.stream_name = "DMA2 playback",
++		.dynamic = 1,
++		.dpcm_playback = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma2_playback),
++	},
++
++	[3] = {
++		.name = "DMA3 playback",
++		.stream_name = "DMA3 playback",
++		.dynamic = 1,
++		.dpcm_playback = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma3_playback),
++	},
++
++	[4] = {
++		.name = "DMA4 playback",
++		.stream_name = "DMA4 playback",
++		.dynamic = 1,
++		.dpcm_playback = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma4_playback),
++	},
++
++	[5] = {
++		.name = "DMA5 capture",
++		.stream_name = "DMA5 capture",
++		.dynamic = 1,
++		.dpcm_capture = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma5_capture),
++	},
++
++	[6] = {
++		.name = "DMA6 capture",
++		.stream_name = "DMA6 capture",
++		.dynamic = 1,
++		.dpcm_capture = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma6_capture),
++	},
++
++	[7] = {
++		.name = "DMA7 capture",
++		.stream_name = "DMA7 capture",
++		.dynamic = 1,
++		.dpcm_capture = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma7_capture),
++	},
++
++	[8] = {
++		.name = "DMA8 capture",
++		.stream_name = "DMA8 capture",
++		.dynamic = 1,
++		.dpcm_capture = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma8_capture),
++	},
++
++	[9] = {
++		.name = "DMA9 capture",
++		.stream_name = "DMA9 capture",
++		.dynamic = 1,
++		.dpcm_capture = 1,
++		.trigger =  {SND_SOC_DPCM_TRIGGER_PRE, SND_SOC_DPCM_TRIGGER_PRE},
++		SND_SOC_DAILINK_REG(dma9_capture),
++	},
++
++	/*BE DAIS*/
++	[10] = {
++		.name = "BAIC0",
++		.stream_name = "BAIC0",
++		.ops = &baic_ops,
++		.be_hw_params_fixup = NULL,
++		.no_pcm = 1,
++		.dpcm_capture = 1,
++		.dpcm_playback = 1,
++		SND_SOC_DAILINK_REG(inno_icodec),
++	},
++
++	[11] = {
++		.name = "DMIC",
++		.stream_name = "DMIC",
++		.no_pcm = 1,
++		.capture_only = 1,
++		SND_SOC_DAILINK_REG(dmic),
++	},
++
++	[12] = {
++		.name = "BAIC4",
++		.stream_name = "BAIC4",
++		.ops = &baic_ops,
++		.be_hw_params_fixup = NULL,
++		.no_pcm = 1,
++		.dpcm_capture = 1,
++		.dpcm_playback = 1,
++		SND_SOC_DAILINK_REG(baic4_bt),
++	},
++};
++
++static struct snd_soc_aux_dev x2000_aux_dev = {
++	.dlc = COMP_AUX( "134dc000.as-mixer"),
++};
++
++static int audio_clk_init(struct device *dev)
++{
++	struct clk *clk, *parent;
++	char clk_name[16];
++	unsigned long rate;
++	int i;
++
++	parent = clk_get(dev, "epll");
++	if(IS_ERR_OR_NULL(parent)) {
++		dev_err(dev, "Get epll clk failed!\n");
++		return -EINVAL;
++	}
++	for(i = 0; i < 4; i++) {
++		sprintf(clk_name, "div_i2s%d", i);
++		clk = clk_get(dev, clk_name);
++		if(IS_ERR_OR_NULL(clk)) {
++			dev_err(dev, "Get %s clk failed!\n", clk_name);
++			return -EINVAL;
++		}
++		rate = clk_get_rate(clk);
++		clk_set_parent(clk, parent);
++		clk_set_rate(clk, rate);
++		clk_put(clk);
++	}
++	clk_put(parent);
++
++	return 0;
++}
++
++
++static int snd_x2000_probe(struct platform_device *pdev)
++{
++	struct snd_soc_card *card;
++	int ret;
++	enum of_gpio_flags flags;
++	card = (struct snd_soc_card *)devm_kzalloc(&pdev->dev,
++			sizeof(struct snd_soc_card), GFP_KERNEL);
++	if (!card)
++		return -ENOMEM;
++
++	card->dapm_widgets = dapm_widgets;
++	card->num_dapm_widgets = ARRAY_SIZE(dapm_widgets);
++	card->dapm_routes = audio_map;
++	card->num_dapm_routes = ARRAY_SIZE(audio_map);
++	card->controls = card_snd_controls;
++	card->num_controls = ARRAY_SIZE(card_snd_controls);
++	card->dai_link = x2000_dais;
++	card->num_links = ARRAY_SIZE(x2000_dais);
++	card->owner = THIS_MODULE;
++	card->dev = &pdev->dev;
++	card->aux_dev = &x2000_aux_dev;
++	card->num_aux_devs = 1;
++
++	ret = snd_soc_of_parse_card_name(card, "ingenic,model");
++	if (ret)
++		return ret;
++
++	ret = snd_soc_register_card(card);
++	if (ret) {
++		dev_err(&pdev->dev, "snd_soc_register_card failed %d\n", ret);
++		return ret;
++	}
++
++	ret = audio_clk_init(card->dev);
++	if(ret)
++		return ret;
++	icodec_spk_power = kmalloc(sizeof(*icodec_spk_power), GFP_KERNEL);
++	if(!icodec_spk_power) {
++		return -ENOMEM;
++	}
++	icodec_spk_power->spk_gpio = of_get_named_gpio_flags(pdev->dev.of_node, "ingenic,spken-gpio", 0, &flags);
++	if (gpio_is_valid(icodec_spk_power->spk_gpio)) {
++		unsigned long init_flags;
++		icodec_spk_power->spk_en_level = (flags == OF_GPIO_ACTIVE_LOW ? 0 : 1);
++		init_flags = (flags == OF_GPIO_ACTIVE_LOW ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW);
++		ret = devm_gpio_request_one(&pdev->dev, icodec_spk_power->spk_gpio, init_flags, "Speaker_en");
++		if (ret)
++			pr_warn("Speaker enable pin(%d) request failed\n",icodec_spk_power->spk_gpio);
++		else
++			pr_info("Speaker enable pin(%d) request ok\n", icodec_spk_power->spk_gpio);
++		/* icodec_playback_power = icodec_playback_power_ctr; */
++		set_playback_pwr_callback(icodec_playback_power_ctr);
++	}
++	platform_set_drvdata(pdev, card);
++	dev_info(&pdev->dev, "Sound Card successed\n");
++
++	return ret;
++}
++
++static int snd_x2000_remove(struct platform_device *pdev)
++{
++	struct snd_soc_card *card = platform_get_drvdata(pdev);
++	snd_soc_unregister_card(card);
++	platform_set_drvdata(pdev, NULL);
++	return 0;
++}
++
++static const struct of_device_id x2000_match_table[] = {
++	{ .compatible = "ingenic,x2000-sound", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, x2000_match_table);
++
++static struct platform_driver snd_x2000_driver = {
++	.driver = {
++		.owner = THIS_MODULE,
++		.name = "x2000-sound",
++		.of_match_table = x2000_match_table
++	},
++	.probe = snd_x2000_probe,
++	.remove = snd_x2000_remove,
++};
++module_platform_driver(snd_x2000_driver);
++
++MODULE_AUTHOR("cli<chen.li@ingenic.com>");
++MODULE_DESCRIPTION("ALSA SoC X2000 Snd Card");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/sound/soc/ingenic/boards/panda.c b/module_drivers/sound/soc/ingenic/boards/panda.c
+new file mode 100644
+index 000000000..d5e73bc30
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/boards/panda.c
+@@ -0,0 +1,242 @@
++ /*
++ * Copyright (C) 2014 Ingenic Semiconductor Co., Ltd.
++ *	http://www.ingenic.com
++ * Author: cli <chen.li@ingenic.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <sound/soc.h>
++#include <sound/jack.h>
++#include <linux/gpio.h>
++#include "../as-v1/asoc-aic.h"
++#include <linux/delay.h>
++
++#define SND_SOC_WM8594_SHARE_CLOCK_PLAYBACK	(1 << 16)
++#define SND_SOC_WM8594_SHARE_CLOCK_RECORD	(2 << 16)
++
++static int x1600_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
++/*	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;*/
++	struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd,0);
++	struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
++	int ret;
++	int id = 0;
++	int sysclk = 24576000;
++	int div = 24576000 / params_rate(params) / 64;
++	int aic_mode = 0, codec_mode = 0;
++
++#ifdef CONFIG_SND_ASOC_INGENIC_MASTER_MODE
++	aic_mode |= SND_SOC_DAIFMT_CBS_CFM;
++	codec_mode |= SND_SOC_DAIFMT_CBS_CFM;
++#endif
++#ifdef CONFIG_SND_ASOC_INGENIC_SLAVE_MODE
++	aic_mode |= SND_SOC_DAIFMT_CBM_CFM;
++	codec_mode |= SND_SOC_DAIFMT_CBM_CFM;
++#endif
++#ifdef CONFIG_SND_ASOC_INGENIC_I2S_MODE
++	aic_mode |= SND_SOC_DAIFMT_I2S;
++	codec_mode |= SND_SOC_DAIFMT_I2S;
++#endif
++#ifdef CONFIG_SND_ASOC_INGENIC_LEFT_J_MODE
++	aic_mode |= SND_SOC_DAIFMT_MSB;
++	codec_mode |= SND_SOC_DAIFMT_LEFT_J;
++#endif
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		codec_mode |= SND_SOC_WM8594_SHARE_CLOCK_PLAYBACK;
++		id |= INGENIC_I2S_PLAYBACK;
++	} else {
++		codec_mode |= SND_SOC_WM8594_SHARE_CLOCK_RECORD;
++		id |= INGENIC_I2S_CAPTURE;
++	}
++
++	ret = snd_soc_dai_set_fmt(cpu_dai, aic_mode);
++	if (ret)
++		return ret;
++
++	ret = snd_soc_dai_set_fmt(codec_dai, codec_mode);
++	if (ret)
++		return ret;
++
++	ret = snd_soc_dai_set_sysclk(cpu_dai, id, sysclk, SND_SOC_CLOCK_OUT);
++	if (ret)
++		return ret;
++
++	ret = snd_soc_dai_set_clkdiv(cpu_dai, id, div);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static int x1600_i2s_hw_free(struct snd_pcm_substream *substream)
++{
++	/*notify release pll*/
++	return 0;
++};
++
++static struct snd_soc_ops x1600_i2s_ecdc_ops = {
++	.hw_params = x1600_i2s_hw_params,
++	.hw_free = x1600_i2s_hw_free,
++};
++
++struct gpio_desc *en_9v_gpiod;
++struct gpio_desc *en_3v3_gpiod;
++
++static int x1600_i2s_ecdc_dai_link_init(struct snd_soc_pcm_runtime *rtd)
++{
++	if (IS_ERR(en_3v3_gpiod))
++		return PTR_ERR(en_3v3_gpiod);
++	gpiod_set_value_cansleep(en_3v3_gpiod, 0);
++
++	if (IS_ERR(en_9v_gpiod))
++		return PTR_ERR(en_9v_gpiod);
++	gpiod_set_value_cansleep(en_9v_gpiod, 1);
++
++	return 0;
++}
++
++static struct snd_soc_card *panda_card;
++
++static int snd_x1600_probe(struct platform_device *pdev)
++{
++	int i, ret = 0;
++	struct snd_soc_card *card;
++	struct snd_soc_dai_link *dai_link;
++	struct device_node *snd_node = pdev->dev.of_node;
++	int num_links;
++
++	num_links = of_property_count_strings(snd_node, "ingenic,dai-link");
++	if (num_links < 0)
++		return num_links;
++	BUG_ON(!num_links);
++
++	card = (struct snd_soc_card *)devm_kzalloc(&pdev->dev,
++			sizeof(struct snd_soc_card), GFP_KERNEL);
++	if (!card)
++		return -ENOMEM;
++	panda_card = card;
++
++	dai_link = (struct snd_soc_dai_link *)devm_kzalloc(&pdev->dev,
++			sizeof(struct snd_soc_dai_link) * num_links, GFP_KERNEL);
++	if (!dai_link)
++		return -ENOMEM;
++
++	card->num_links = num_links;
++	card->dai_link = dai_link;
++	card->owner = THIS_MODULE;
++	card->dev = &pdev->dev;
++	ret = snd_soc_of_parse_card_name(card, "ingenic,model");
++	if (ret)
++		return ret;
++
++	en_3v3_gpiod = devm_gpiod_get_optional(card->dev, "en3v3", GPIOD_OUT_LOW);
++	en_9v_gpiod = devm_gpiod_get_optional(card->dev, "en9v", GPIOD_OUT_LOW);
++
++	for (i = 0; i < card->num_links; i++) {
++		dai_link[i].cpus = devm_kzalloc(&pdev->dev,sizeof(struct snd_soc_dai_link_component), GFP_KERNEL);
++		dai_link[i].codecs = devm_kzalloc(&pdev->dev,sizeof(struct snd_soc_dai_link_component), GFP_KERNEL);
++		dai_link[i].platforms = devm_kzalloc(&pdev->dev,sizeof(struct snd_soc_dai_link_component), GFP_KERNEL);
++
++		dai_link[i].num_cpus = 1;
++		dai_link[i].num_platforms = 1;
++		dai_link[i].num_codecs = 1;
++
++		dai_link[i].cpus->of_node = of_parse_phandle(snd_node, "ingenic,cpu-dai" , i);
++		dai_link[i].platforms->of_node = of_parse_phandle(snd_node, "ingenic,platform", i);
++		dai_link[i].codecs->of_node = of_parse_phandle(snd_node, "ingenic,codec", i);
++
++		ret = of_property_read_string_index(snd_node, "ingenic,codec-dai", i,
++				&(dai_link[i].codecs->dai_name));
++
++		if (ret || !dai_link[i].cpus->of_node ||
++				!dai_link[i].codecs->of_node ||
++				!dai_link[i].platforms->of_node)
++			return -ENODEV;
++		ret = of_property_read_string_index(snd_node, "ingenic,dai-link", i,
++				&(dai_link[i].name));
++		if (ret)
++			return -ENODEV;
++		ret = of_property_read_string_index(snd_node, "ingenic,stream", i,
++				&(dai_link[i].stream_name));
++		if (ret)
++			dai_link[i].stream_name = dai_link[i].name;
++
++		dev_dbg(&pdev->dev, "dai_link %s\n", dai_link[i].name);
++		dev_dbg(&pdev->dev, "stream_name %s\n", dai_link[i].stream_name);
++		dev_dbg(&pdev->dev, "cpu %s(%s)\n", dai_link[i].cpus->of_node->name,
++				dai_link[i].cpus->of_node->full_name);
++		dev_dbg(&pdev->dev, "platform %s(%s)\n", dai_link[i].platforms->of_node->name,
++				dai_link[i].platforms->of_node->full_name);
++		dev_dbg(&pdev->dev, "codec dai %s\n", dai_link[i].codecs->dai_name);
++		dev_dbg(&pdev->dev, "codec %s(%s)\n", dai_link[i].codecs->of_node->name,
++				dai_link[i].codecs->of_node->full_name);
++
++		if (!strcmp(dai_link[i].name, "i2s-ecodec")) {
++			dai_link->ops = &x1600_i2s_ecdc_ops;
++			dai_link->init = x1600_i2s_ecdc_dai_link_init;
++		}
++	}
++
++	ret = snd_soc_register_card(card);
++	if (ret) {
++		dev_err(&pdev->dev, "snd_soc_register_card failed %d\n", ret);
++		return ret;
++	}
++
++	platform_set_drvdata(pdev, card);
++
++	dev_info(&pdev->dev, "Sound Card successed\n");
++
++	return ret;
++}
++
++static int snd_x1600_remove(struct platform_device *pdev)
++{
++	struct snd_soc_card *card = platform_get_drvdata(pdev);
++
++	snd_soc_unregister_card(card);
++	platform_set_drvdata(pdev, NULL);
++
++	return 0;
++}
++
++static const struct of_device_id sound_dt_match[] = {
++	{ .compatible = "ingenic,x1600-sound", .data = NULL },
++	{},
++};
++MODULE_DEVICE_TABLE(of, sound_dt_match);
++
++static struct platform_driver snd_x1600_driver = {
++	.driver = {
++		.owner = THIS_MODULE,
++		.name = "ingenic-fpga-x1600",
++		.pm = &snd_soc_pm_ops,
++		.of_match_table = of_match_ptr(sound_dt_match),
++	},
++	.probe = snd_x1600_probe,
++	.remove = snd_x1600_remove,
++};
++module_platform_driver(snd_x1600_driver);
++
++MODULE_AUTHOR("cli<chen.li@ingenic.com>");
++MODULE_DESCRIPTION("ALSA SoC FPGA Snd Card");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/sound/soc/ingenic/ecodec/Kconfig b/module_drivers/sound/soc/ingenic/ecodec/Kconfig
+new file mode 100644
+index 000000000..31bb3b54c
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/ecodec/Kconfig
+@@ -0,0 +1,37 @@
++if SND_ASOC_INGENIC_AS_V1
++menu "ingenic external codec Type select"
++
++config SND_SOC_WM8594
++	depends on I2C
++        tristate "WM8594 ADC/DAC"
++
++config SND_SOC_NAU8822
++	depends on I2C
++        tristate "NAU8822 ADC/DAC"
++endmenu
++
++endif
++
++if SND_ASOC_INGENIC_AS_V2
++menu "ingenic external codec Type select"
++
++config SND_SOC_WM8594
++	depends on I2C
++        tristate "WM8594 ADC/DAC"
++
++config SND_SOC_AK4458
++	depends on I2C
++        tristate "AK4458 ADC/DAC"
++
++config SND_SOC_AK5558
++	depends on I2C
++        tristate "AK5558 ADC/DAC"
++
++config SND_SOC_NAU8822
++	depends on I2C
++        tristate "NAU8822 ADC/DAC"
++
++
++endmenu
++
++endif
+diff --git a/module_drivers/sound/soc/ingenic/ecodec/Makefile b/module_drivers/sound/soc/ingenic/ecodec/Makefile
+new file mode 100644
+index 000000000..a50c5da40
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/ecodec/Makefile
+@@ -0,0 +1,5 @@
++
++obj-$(CONFIG_SND_SOC_WM8594)	+= wm8594.o
++obj-$(CONFIG_SND_SOC_AK4458)	+= ak4458.o
++obj-$(CONFIG_SND_SOC_AK5558)	+= ak5558.o
++obj-$(CONFIG_SND_SOC_NAU8822)	+= nau8822.o
+diff --git a/module_drivers/sound/soc/ingenic/ecodec/ak4458.c b/module_drivers/sound/soc/ingenic/ecodec/ak4458.c
+new file mode 100644
+index 000000000..c4ed091dd
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/ecodec/ak4458.c
+@@ -0,0 +1,685 @@
++// SPDX-License-Identifier: GPL-2.0
++//
++// Audio driver for AK4458 DAC
++//
++// Copyright (C) 2016 Asahi Kasei Microdevices Corporation
++// Copyright 2018 NXP
++
++#include <linux/delay.h>
++#include <linux/gpio/consumer.h>
++#include <linux/i2c.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/of_gpio.h>
++#include <linux/pm_runtime.h>
++#include <linux/slab.h>
++#include <sound/initval.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++#include <sound/tlv.h>
++
++#include "ak4458.h"
++
++/* AK4458 Codec Private Data */
++struct ak4458_priv {
++	struct device *dev;
++	struct regmap *regmap;
++	struct gpio_desc *reset_gpiod;
++	struct gpio_desc *mute_gpiod;
++	int digfil;	/* SSLOW, SD, SLOW bits */
++	int fs;		/* sampling rate */
++	int fmt;
++	int slots;
++	int slot_width;
++};
++
++static const struct reg_default ak4458_reg_defaults[] = {
++	{ 0x00, 0x0C },	/*	0x00	AK4458_00_CONTROL1	*/
++	{ 0x01, 0x22 },	/*	0x01	AK4458_01_CONTROL2	*/
++	{ 0x02, 0x00 },	/*	0x02	AK4458_02_CONTROL3	*/
++	{ 0x03, 0xFF },	/*	0x03	AK4458_03_LCHATT	*/
++	{ 0x04, 0xFF },	/*	0x04	AK4458_04_RCHATT	*/
++	{ 0x05, 0x00 },	/*	0x05	AK4458_05_CONTROL4	*/
++	{ 0x06, 0x00 },	/*	0x06	AK4458_06_DSD1		*/
++	{ 0x07, 0x03 },	/*	0x07	AK4458_07_CONTROL5	*/
++	{ 0x08, 0x00 },	/*	0x08	AK4458_08_SOUND_CONTROL	*/
++	{ 0x09, 0x00 },	/*	0x09	AK4458_09_DSD2		*/
++	{ 0x0A, 0x0D },	/*	0x0A	AK4458_0A_CONTROL6	*/
++	{ 0x0B, 0x0C },	/*	0x0B	AK4458_0B_CONTROL7	*/
++	{ 0x0C, 0x00 },	/*	0x0C	AK4458_0C_CONTROL8	*/
++	{ 0x0D, 0x00 },	/*	0x0D	AK4458_0D_CONTROL9	*/
++	{ 0x0E, 0x50 },	/*	0x0E	AK4458_0E_CONTROL10	*/
++	{ 0x0F, 0xFF },	/*	0x0F	AK4458_0F_L2CHATT	*/
++	{ 0x10, 0xFF },	/*	0x10	AK4458_10_R2CHATT	*/
++	{ 0x11, 0xFF },	/*	0x11	AK4458_11_L3CHATT	*/
++	{ 0x12, 0xFF },	/*	0x12	AK4458_12_R3CHATT	*/
++	{ 0x13, 0xFF },	/*	0x13	AK4458_13_L4CHATT	*/
++	{ 0x14, 0xFF },	/*	0x14	AK4458_14_R4CHATT	*/
++};
++
++/*
++ * Volume control:
++ * from -127 to 0 dB in 0.5 dB steps (mute instead of -127.5 dB)
++ */
++static DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
++
++/*
++ * DEM1 bit DEM0 bit Mode
++ * 0 0 44.1kHz
++ * 0 1 OFF (default)
++ * 1 0 48kHz
++ * 1 1 32kHz
++ */
++static const char * const ak4458_dem_select_texts[] = {
++	"44.1kHz", "OFF", "48kHz", "32kHz"
++};
++
++/*
++ * SSLOW, SD, SLOW bits Digital Filter Setting
++ * 0, 0, 0 : Sharp Roll-Off Filter
++ * 0, 0, 1 : Slow Roll-Off Filter
++ * 0, 1, 0 : Short delay Sharp Roll-Off Filter
++ * 0, 1, 1 : Short delay Slow Roll-Off Filter
++ * 1, *, * : Super Slow Roll-Off Filter
++ */
++static const char * const ak4458_digfil_select_texts[] = {
++	"Sharp Roll-Off Filter",
++	"Slow Roll-Off Filter",
++	"Short delay Sharp Roll-Off Filter",
++	"Short delay Slow Roll-Off Filter",
++	"Super Slow Roll-Off Filter"
++};
++
++/*
++ * DZFB: Inverting Enable of DZF
++ * 0: DZF goes H at Zero Detection
++ * 1: DZF goes L at Zero Detection
++ */
++static const char * const ak4458_dzfb_select_texts[] = {"H", "L"};
++
++/*
++ * SC1-0 bits: Sound Mode Setting
++ * 0 0 : Sound Mode 0
++ * 0 1 : Sound Mode 1
++ * 1 0 : Sound Mode 2
++ * 1 1 : Reserved
++ */
++static const char * const ak4458_sc_select_texts[] = {
++	"Sound Mode 0", "Sound Mode 1", "Sound Mode 2"
++};
++
++/* FIR2-0 bits: FIR Filter Mode Setting */
++static const char * const ak4458_fir_select_texts[] = {
++	"Mode 0", "Mode 1", "Mode 2", "Mode 3",
++	"Mode 4", "Mode 5", "Mode 6", "Mode 7",
++};
++
++/* ATS1-0 bits Attenuation Speed */
++static const char * const ak4458_ats_select_texts[] = {
++	"4080/fs", "2040/fs", "510/fs", "255/fs",
++};
++
++/* DIF2 bit Audio Interface Format Setting(BICK fs) */
++static const char * const ak4458_dif_select_texts[] = {"32fs,48fs", "64fs",};
++
++static const struct soc_enum ak4458_dac1_dem_enum =
++	SOC_ENUM_SINGLE(AK4458_01_CONTROL2, 1,
++			ARRAY_SIZE(ak4458_dem_select_texts),
++			ak4458_dem_select_texts);
++static const struct soc_enum ak4458_dac2_dem_enum =
++	SOC_ENUM_SINGLE(AK4458_0A_CONTROL6, 0,
++			ARRAY_SIZE(ak4458_dem_select_texts),
++			ak4458_dem_select_texts);
++static const struct soc_enum ak4458_dac3_dem_enum =
++	SOC_ENUM_SINGLE(AK4458_0E_CONTROL10, 4,
++			ARRAY_SIZE(ak4458_dem_select_texts),
++			ak4458_dem_select_texts);
++static const struct soc_enum ak4458_dac4_dem_enum =
++	SOC_ENUM_SINGLE(AK4458_0E_CONTROL10, 6,
++			ARRAY_SIZE(ak4458_dem_select_texts),
++			ak4458_dem_select_texts);
++static const struct soc_enum ak4458_digfil_enum =
++	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ak4458_digfil_select_texts),
++			    ak4458_digfil_select_texts);
++static const struct soc_enum ak4458_dzfb_enum =
++	SOC_ENUM_SINGLE(AK4458_02_CONTROL3, 2,
++			ARRAY_SIZE(ak4458_dzfb_select_texts),
++			ak4458_dzfb_select_texts);
++static const struct soc_enum ak4458_sm_enum =
++	SOC_ENUM_SINGLE(AK4458_08_SOUND_CONTROL, 0,
++			ARRAY_SIZE(ak4458_sc_select_texts),
++			ak4458_sc_select_texts);
++static const struct soc_enum ak4458_fir_enum =
++	SOC_ENUM_SINGLE(AK4458_0C_CONTROL8, 0,
++			ARRAY_SIZE(ak4458_fir_select_texts),
++			ak4458_fir_select_texts);
++static const struct soc_enum ak4458_ats_enum =
++	SOC_ENUM_SINGLE(AK4458_0B_CONTROL7, 6,
++			ARRAY_SIZE(ak4458_ats_select_texts),
++			ak4458_ats_select_texts);
++static const struct soc_enum ak4458_dif_enum =
++	SOC_ENUM_SINGLE(AK4458_00_CONTROL1, 3,
++			ARRAY_SIZE(ak4458_dif_select_texts),
++			ak4458_dif_select_texts);
++
++static int get_digfil(struct snd_kcontrol *kcontrol,
++		      struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct ak4458_priv *ak4458 = snd_soc_component_get_drvdata(component);
++
++	ucontrol->value.enumerated.item[0] = ak4458->digfil;
++
++	return 0;
++}
++
++static int set_digfil(struct snd_kcontrol *kcontrol,
++		      struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct ak4458_priv *ak4458 = snd_soc_component_get_drvdata(component);
++	int num;
++
++	num = ucontrol->value.enumerated.item[0];
++	if (num > 4)
++		return -EINVAL;
++
++	ak4458->digfil = num;
++
++	/* write SD bit */
++	snd_soc_component_update_bits(component, AK4458_01_CONTROL2,
++			    AK4458_SD_MASK,
++			    ((ak4458->digfil & 0x02) << 4));
++
++	/* write SLOW bit */
++	snd_soc_component_update_bits(component, AK4458_02_CONTROL3,
++			    AK4458_SLOW_MASK,
++			    (ak4458->digfil & 0x01));
++
++	/* write SSLOW bit */
++	snd_soc_component_update_bits(component, AK4458_05_CONTROL4,
++			    AK4458_SSLOW_MASK,
++			    ((ak4458->digfil & 0x04) >> 2));
++
++	return 0;
++}
++
++static const struct snd_kcontrol_new ak4458_snd_controls[] = {
++	SOC_DOUBLE_R_TLV("AK4458 DAC1 Playback Volume", AK4458_03_LCHATT,
++			 AK4458_04_RCHATT, 0, 0xFF, 0, dac_tlv),
++	SOC_DOUBLE_R_TLV("AK4458 DAC2 Playback Volume", AK4458_0F_L2CHATT,
++			 AK4458_10_R2CHATT, 0, 0xFF, 0, dac_tlv),
++	SOC_DOUBLE_R_TLV("AK4458 DAC3 Playback Volume", AK4458_11_L3CHATT,
++			 AK4458_12_R3CHATT, 0, 0xFF, 0, dac_tlv),
++	SOC_DOUBLE_R_TLV("AK4458 DAC4 Playback Volume", AK4458_13_L4CHATT,
++			 AK4458_14_R4CHATT, 0, 0xFF, 0, dac_tlv),
++	SOC_ENUM("AK4458 De-emphasis Response DAC1", ak4458_dac1_dem_enum),
++	SOC_ENUM("AK4458 De-emphasis Response DAC2", ak4458_dac2_dem_enum),
++	SOC_ENUM("AK4458 De-emphasis Response DAC3", ak4458_dac3_dem_enum),
++	SOC_ENUM("AK4458 De-emphasis Response DAC4", ak4458_dac4_dem_enum),
++	SOC_ENUM_EXT("AK4458 Digital Filter Setting", ak4458_digfil_enum,
++		     get_digfil, set_digfil),
++	SOC_ENUM("AK4458 Inverting Enable of DZFB", ak4458_dzfb_enum),
++	SOC_ENUM("AK4458 Sound Mode", ak4458_sm_enum),
++	SOC_ENUM("AK4458 FIR Filter Mode Setting", ak4458_fir_enum),
++	SOC_ENUM("AK4458 Attenuation transition Time Setting",
++		 ak4458_ats_enum),
++	SOC_ENUM("AK4458 BICK fs Setting", ak4458_dif_enum),
++};
++
++/* ak4458 dapm widgets */
++static const struct snd_soc_dapm_widget ak4458_dapm_widgets[] = {
++	SND_SOC_DAPM_DAC("AK4458 DAC1", NULL, AK4458_0A_CONTROL6, 2, 0),/*pw*/
++	SND_SOC_DAPM_AIF_IN("AK4458 SDTI", "Playback", 0, SND_SOC_NOPM, 0, 0),
++	SND_SOC_DAPM_OUTPUT("AK4458 AOUTA"),
++
++	SND_SOC_DAPM_DAC("AK4458 DAC2", NULL, AK4458_0A_CONTROL6, 3, 0),/*pw*/
++	SND_SOC_DAPM_OUTPUT("AK4458 AOUTB"),
++
++	SND_SOC_DAPM_DAC("AK4458 DAC3", NULL, AK4458_0B_CONTROL7, 2, 0),/*pw*/
++	SND_SOC_DAPM_OUTPUT("AK4458 AOUTC"),
++
++	SND_SOC_DAPM_DAC("AK4458 DAC4", NULL, AK4458_0B_CONTROL7, 3, 0),/*pw*/
++	SND_SOC_DAPM_OUTPUT("AK4458 AOUTD"),
++};
++
++static const struct snd_soc_dapm_route ak4458_intercon[] = {
++	{"AK4458 DAC1",		NULL,	"AK4458 SDTI"},
++	{"AK4458 AOUTA",	NULL,	"AK4458 DAC1"},
++
++	{"AK4458 DAC2",		NULL,	"AK4458 SDTI"},
++	{"AK4458 AOUTB",	NULL,	"AK4458 DAC2"},
++
++	{"AK4458 DAC3",		NULL,	"AK4458 SDTI"},
++	{"AK4458 AOUTC",	NULL,	"AK4458 DAC3"},
++
++	{"AK4458 DAC4",		NULL,	"AK4458 SDTI"},
++	{"AK4458 AOUTD",	NULL,	"AK4458 DAC4"},
++};
++
++static int ak4458_rstn_control(struct snd_soc_component *component, int bit)
++{
++	int ret;
++
++	if (bit)
++		ret = snd_soc_component_update_bits(component,
++					  AK4458_00_CONTROL1,
++					  AK4458_RSTN_MASK,
++					  0x1);
++	else
++		ret = snd_soc_component_update_bits(component,
++					  AK4458_00_CONTROL1,
++					  AK4458_RSTN_MASK,
++					  0x0);
++	return ret;
++}
++
++static int ak4458_hw_params(struct snd_pcm_substream *substream,
++			    struct snd_pcm_hw_params *params,
++			    struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++	struct ak4458_priv *ak4458 = snd_soc_component_get_drvdata(component);
++	int pcm_width = max(params_physical_width(params), ak4458->slot_width);
++	int nfs1;
++	u8 format;
++
++	nfs1 = params_rate(params);
++	ak4458->fs = nfs1;
++
++	/* Master Clock Frequency Auto Setting Mode Enable */
++	snd_soc_component_update_bits(component, AK4458_00_CONTROL1, 0x80, 0x80);
++
++	switch (pcm_width) {
++	case 16:
++		if (ak4458->fmt == SND_SOC_DAIFMT_I2S)
++			format = AK4458_DIF_24BIT_I2S;
++		else
++			format = AK4458_DIF_16BIT_LSB;
++		break;
++	case 24:
++		switch (ak4458->fmt) {
++		case SND_SOC_DAIFMT_I2S:
++			format = AK4458_DIF_24BIT_I2S;
++			break;
++		case SND_SOC_DAIFMT_LEFT_J:
++			format = AK4458_DIF_24BIT_MSB;
++			break;
++		case SND_SOC_DAIFMT_RIGHT_J:
++			format = AK4458_DIF_24BIT_LSB;
++			break;
++		case SND_SOC_DAIFMT_DSP_B:
++			format = AK4458_DIF_24BIT_MSB;
++			break;
++		default:
++			return -EINVAL;
++		}
++	case 32:
++		switch (ak4458->fmt) {
++		case SND_SOC_DAIFMT_I2S:
++			format = AK4458_DIF_32BIT_I2S;
++			break;
++		case SND_SOC_DAIFMT_LEFT_J:
++			format = AK4458_DIF_32BIT_MSB;
++			break;
++		case SND_SOC_DAIFMT_RIGHT_J:
++			format = AK4458_DIF_32BIT_LSB;
++			break;
++		case SND_SOC_DAIFMT_DSP_B:
++			format = AK4458_DIF_32BIT_MSB;
++			break;
++		default:
++			return -EINVAL;
++		}
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	snd_soc_component_update_bits(component, AK4458_00_CONTROL1,
++			    AK4458_DIF_MASK, format);
++
++	ak4458_rstn_control(component, 0);
++	ak4458_rstn_control(component, 1);
++
++	return 0;
++}
++
++static int ak4458_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
++{
++	struct snd_soc_component *component = dai->component;
++	struct ak4458_priv *ak4458 = snd_soc_component_get_drvdata(component);
++
++	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++	case SND_SOC_DAIFMT_CBS_CFS: /* Slave Mode */
++		break;
++	case SND_SOC_DAIFMT_CBM_CFM: /* Master Mode is not supported */
++	case SND_SOC_DAIFMT_CBS_CFM:
++	case SND_SOC_DAIFMT_CBM_CFS:
++	default:
++		dev_err(component->dev, "Master mode unsupported\n");
++		return -EINVAL;
++	}
++
++	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_I2S:
++	case SND_SOC_DAIFMT_LEFT_J:
++	case SND_SOC_DAIFMT_RIGHT_J:
++	case SND_SOC_DAIFMT_DSP_B:
++		ak4458->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
++		break;
++	default:
++		dev_err(component->dev, "Audio format 0x%02X unsupported\n",
++			fmt & SND_SOC_DAIFMT_FORMAT_MASK);
++		return -EINVAL;
++	}
++
++	ak4458_rstn_control(component, 0);
++	ak4458_rstn_control(component, 1);
++
++	return 0;
++}
++
++static const int att_speed[] = { 4080, 2040, 510, 255 };
++
++static int ak4458_set_dai_mute(struct snd_soc_dai *dai, int mute)
++{
++	struct snd_soc_component *component = dai->component;
++	struct ak4458_priv *ak4458 = snd_soc_component_get_drvdata(component);
++	int nfs, ndt, ret, reg;
++	int ats;
++
++	nfs = ak4458->fs;
++
++	reg = snd_soc_component_read32(component, AK4458_0B_CONTROL7);
++	ats = (reg & AK4458_ATS_MASK) >> AK4458_ATS_SHIFT;
++
++	ndt = att_speed[ats] / (nfs / 1000);
++
++	if (mute) {
++		ret = snd_soc_component_update_bits(component, AK4458_01_CONTROL2,  0x01, 1);
++		mdelay(ndt);
++		if (ak4458->mute_gpiod)
++			gpiod_set_value_cansleep(ak4458->mute_gpiod, 1);
++	} else {
++		if (ak4458->mute_gpiod)
++			gpiod_set_value_cansleep(ak4458->mute_gpiod, 0);
++		ret = snd_soc_component_update_bits(component, AK4458_01_CONTROL2, 0x01, 0);
++		mdelay(ndt);
++	}
++
++	return 0;
++}
++
++static int ak4458_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
++			       unsigned int rx_mask, int slots, int slot_width)
++{
++	struct snd_soc_component *component = dai->component;
++	struct ak4458_priv *ak4458 = snd_soc_component_get_drvdata(component);
++	int mode;
++
++	ak4458->slots = slots;
++	ak4458->slot_width = slot_width;
++
++	switch (slots * slot_width) {
++	case 128:
++		mode = AK4458_MODE_TDM128;
++		break;
++	case 256:
++		mode = AK4458_MODE_TDM256;
++		break;
++	case 512:
++		mode = AK4458_MODE_TDM512;
++		break;
++	default:
++		mode = AK4458_MODE_NORMAL;
++		break;
++	}
++
++	snd_soc_component_update_bits(component, AK4458_0A_CONTROL6,
++			    AK4458_MODE_MASK,
++			    mode);
++
++	return 0;
++}
++
++#define AK4458_FORMATS	(SNDRV_PCM_FMTBIT_S16_LE |\
++			 SNDRV_PCM_FMTBIT_S24_LE |\
++			 SNDRV_PCM_FMTBIT_S32_LE)
++
++static const unsigned int ak4458_rates[] = {
++	8000, 11025,  16000, 22050,
++	32000, 44100, 48000, 88200,
++	96000, 176400, 192000, 352800,
++	384000, 705600, 768000, 1411200,
++	2822400,
++};
++
++static const struct snd_pcm_hw_constraint_list ak4458_rate_constraints = {
++	.count = ARRAY_SIZE(ak4458_rates),
++	.list = ak4458_rates,
++};
++
++static int ak4458_startup(struct snd_pcm_substream *substream,
++			  struct snd_soc_dai *dai)
++{
++	int ret;
++
++	ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
++					 SNDRV_PCM_HW_PARAM_RATE,
++					 &ak4458_rate_constraints);
++
++	return ret;
++}
++
++static struct snd_soc_dai_ops ak4458_dai_ops = {
++	.startup        = ak4458_startup,
++	.hw_params	= ak4458_hw_params,
++	.set_fmt	= ak4458_set_dai_fmt,
++	.digital_mute	= ak4458_set_dai_mute,
++	.set_tdm_slot	= ak4458_set_tdm_slot,
++};
++
++static struct snd_soc_dai_driver ak4458_dai = {
++	.name = "ak4458-aif",
++	.playback = {
++		.stream_name = "Playback",
++		.channels_min = 1,
++		.channels_max = 8,
++		.rates = SNDRV_PCM_RATE_KNOT,
++		.formats = AK4458_FORMATS,
++	},
++	.ops = &ak4458_dai_ops,
++};
++
++static void ak4458_power_off(struct ak4458_priv *ak4458)
++{
++	if (ak4458->reset_gpiod) {
++		gpiod_set_value_cansleep(ak4458->reset_gpiod, 0);
++		usleep_range(1000, 2000);
++	}
++}
++
++static void ak4458_power_on(struct ak4458_priv *ak4458)
++{
++	if (ak4458->reset_gpiod) {
++		gpiod_set_value_cansleep(ak4458->reset_gpiod, 1);
++		usleep_range(1000, 2000);
++	}
++}
++
++static void ak4458_init(struct snd_soc_component *component)
++{
++	struct ak4458_priv *ak4458 = snd_soc_component_get_drvdata(component);
++
++	/* External Mute ON */
++	if (ak4458->mute_gpiod)
++		gpiod_set_value_cansleep(ak4458->mute_gpiod, 1);
++
++	ak4458_power_on(ak4458);
++
++	snd_soc_component_update_bits(component, AK4458_00_CONTROL1,
++			    0x80, 0x80);   /* ACKS bit = 1; 10000000 */
++
++	ak4458_rstn_control(component, 1);
++}
++
++static int ak4458_probe(struct snd_soc_component *component)
++{
++	struct ak4458_priv *ak4458 = snd_soc_component_get_drvdata(component);
++
++	ak4458_init(component);
++
++	ak4458->fs = 48000;
++
++	return 0;
++}
++
++static void ak4458_remove(struct snd_soc_component *component)
++{
++	struct ak4458_priv *ak4458 = snd_soc_component_get_drvdata(component);
++
++	ak4458_power_off(ak4458);
++}
++
++#ifdef CONFIG_PM
++static int __maybe_unused ak4458_runtime_suspend(struct device *dev)
++{
++	struct ak4458_priv *ak4458 = dev_get_drvdata(dev);
++
++	regcache_cache_only(ak4458->regmap, true);
++
++	ak4458_power_off(ak4458);
++
++	if (ak4458->mute_gpiod)
++		gpiod_set_value_cansleep(ak4458->mute_gpiod, 0);
++
++	return 0;
++}
++
++static int __maybe_unused ak4458_runtime_resume(struct device *dev)
++{
++	struct ak4458_priv *ak4458 = dev_get_drvdata(dev);
++
++	if (ak4458->mute_gpiod)
++		gpiod_set_value_cansleep(ak4458->mute_gpiod, 1);
++
++	ak4458_power_off(ak4458);
++	ak4458_power_on(ak4458);
++
++	regcache_cache_only(ak4458->regmap, false);
++	regcache_mark_dirty(ak4458->regmap);
++
++	return regcache_sync(ak4458->regmap);
++}
++#endif /* CONFIG_PM */
++
++struct snd_soc_component_driver soc_codec_dev_ak4458 = {
++	.probe			= ak4458_probe,
++	.remove			= ak4458_remove,
++	.controls		= ak4458_snd_controls,
++	.num_controls		= ARRAY_SIZE(ak4458_snd_controls),
++	.dapm_widgets		= ak4458_dapm_widgets,
++	.num_dapm_widgets	= ARRAY_SIZE(ak4458_dapm_widgets),
++	.dapm_routes		= ak4458_intercon,
++	.num_dapm_routes	= ARRAY_SIZE(ak4458_intercon),
++#if 0
++	.idle_bias_on		= 1,
++	.use_pmdown_time	= 1,
++	.endianness		= 1,
++	.non_legacy_dai_naming	= 1,
++#endif
++};
++
++static const struct regmap_config ak4458_regmap = {
++	.reg_bits = 8,
++	.val_bits = 8,
++
++	.max_register = AK4458_14_R4CHATT,
++	.reg_defaults = ak4458_reg_defaults,
++	.num_reg_defaults = ARRAY_SIZE(ak4458_reg_defaults),
++	.cache_type = REGCACHE_RBTREE,
++};
++
++static const struct dev_pm_ops ak4458_pm = {
++	SET_RUNTIME_PM_OPS(ak4458_runtime_suspend, ak4458_runtime_resume, NULL)
++	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
++				pm_runtime_force_resume)
++};
++
++static int ak4458_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
++{
++	struct ak4458_priv *ak4458;
++	int ret;
++
++	ak4458 = devm_kzalloc(&i2c->dev, sizeof(*ak4458), GFP_KERNEL);
++	if (!ak4458)
++		return -ENOMEM;
++
++	ak4458->regmap = devm_regmap_init_i2c(i2c, &ak4458_regmap);
++	if (IS_ERR(ak4458->regmap))
++		return PTR_ERR(ak4458->regmap);
++
++	i2c_set_clientdata(i2c, ak4458);
++	ak4458->dev = &i2c->dev;
++
++	ak4458->reset_gpiod = devm_gpiod_get_optional(ak4458->dev, "reset",
++						      GPIOD_OUT_LOW);
++	if (IS_ERR(ak4458->reset_gpiod))
++		return PTR_ERR(ak4458->reset_gpiod);
++
++	ak4458->mute_gpiod = devm_gpiod_get_optional(ak4458->dev, "mute",
++						     GPIOD_OUT_LOW);
++	if (IS_ERR(ak4458->mute_gpiod))
++		return PTR_ERR(ak4458->mute_gpiod);
++
++	ret = devm_snd_soc_register_component(ak4458->dev, &soc_codec_dev_ak4458,
++				     &ak4458_dai, 1);
++	if (ret < 0) {
++		dev_err(ak4458->dev, "Failed to register CODEC: %d\n", ret);
++		return ret;
++	}
++
++	pm_runtime_enable(&i2c->dev);
++
++	printk("ak4458 probe ok, dev_name: %s\n", dev_name(ak4458->dev));
++
++	return 0;
++}
++
++static int ak4458_i2c_remove(struct i2c_client *i2c)
++{
++	pm_runtime_disable(&i2c->dev);
++
++	return 0;
++}
++
++static const struct i2c_device_id ak4458_i2c_table[] = {
++	{"ak4458", 0},
++	{}
++};
++MODULE_DEVICE_TABLE(i2c, ak4458_i2c_table);
++
++static const struct of_device_id ak4458_of_match[] = {
++	{ .compatible = "asahi-kasei,ak4458", },
++	{ },
++};
++
++static struct i2c_driver ak4458_i2c_driver = {
++	.driver = {
++		.name = "ak4458",
++		.pm = &ak4458_pm,
++		.of_match_table = ak4458_of_match,
++		},
++	.probe = ak4458_i2c_probe,
++	.remove = ak4458_i2c_remove,
++	.id_table = ak4458_i2c_table,
++};
++
++module_i2c_driver(ak4458_i2c_driver);
++
++MODULE_AUTHOR("Junichi Wakasugi <wakasugi.jb@om.asahi-kasei.co.jp>");
++MODULE_AUTHOR("Mihai Serban <mihai.serban@nxp.com>");
++MODULE_DESCRIPTION("ASoC AK4458 DAC driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/module_drivers/sound/soc/ingenic/ecodec/ak4458.h b/module_drivers/sound/soc/ingenic/ecodec/ak4458.h
+new file mode 100644
+index 000000000..a757df696
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/ecodec/ak4458.h
+@@ -0,0 +1,88 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Audio driver for AK4458
++ *
++ * Copyright (C) 2016 Asahi Kasei Microdevices Corporation
++ * Copyright 2018 NXP
++ */
++
++#ifndef _AK4458_H
++#define _AK4458_H
++
++#include <linux/regmap.h>
++
++/* Settings */
++
++#define AK4458_00_CONTROL1			0x00
++#define AK4458_01_CONTROL2			0x01
++#define AK4458_02_CONTROL3			0x02
++#define AK4458_03_LCHATT			0x03
++#define AK4458_04_RCHATT			0x04
++#define AK4458_05_CONTROL4			0x05
++#define AK4458_06_DSD1				0x06
++#define AK4458_07_CONTROL5			0x07
++#define AK4458_08_SOUND_CONTROL			0x08
++#define AK4458_09_DSD2				0x09
++#define AK4458_0A_CONTROL6			0x0A
++#define AK4458_0B_CONTROL7			0x0B
++#define AK4458_0C_CONTROL8			0x0C
++#define AK4458_0D_CONTROL9			0x0D
++#define AK4458_0E_CONTROL10			0x0E
++#define AK4458_0F_L2CHATT			0x0F
++#define AK4458_10_R2CHATT			0x10
++#define AK4458_11_L3CHATT			0x11
++#define AK4458_12_R3CHATT			0x12
++#define AK4458_13_L4CHATT			0x13
++#define AK4458_14_R4CHATT			0x14
++
++/* Bitfield Definitions */
++
++/* AK4458_00_CONTROL1 (0x00) Fields
++ * Addr Register Name  D7     D6    D5    D4    D3    D2    D1    D0
++ * 00H  Control 1      ACKS   0     0     0     DIF2  DIF1  DIF0  RSTN
++ */
++
++/* Digital Filter (SD, SLOW, SSLOW) */
++#define AK4458_SD_MASK		GENMASK(5, 5)
++#define AK4458_SLOW_MASK	GENMASK(0, 0)
++#define AK4458_SSLOW_MASK	GENMASK(0, 0)
++
++/* DIF2	1 0
++ *  x	1 0 MSB justified  Figure 3 (default)
++ *  x	1 1 I2S Compliment  Figure 4
++ */
++#define AK4458_DIF_SHIFT	1
++#define AK4458_DIF_MASK		GENMASK(3, 1)
++
++#define AK4458_DIF_16BIT_LSB	(0 << 1)
++#define AK4458_DIF_24BIT_MSB	(2 << 1)
++#define AK4458_DIF_24BIT_I2S	(3 << 1)
++#define AK4458_DIF_24BIT_LSB	(4 << 1)
++#define AK4458_DIF_32BIT_LSB	(5 << 1)
++#define AK4458_DIF_32BIT_MSB	(6 << 1)
++#define AK4458_DIF_32BIT_I2S	(7 << 1)
++
++/* AK4458_00_CONTROL1 (0x00) D0 bit */
++#define AK4458_RSTN_MASK	GENMASK(0, 0)
++#define AK4458_RSTN		(0x1 << 0)
++
++/* AK4458_0A_CONTROL6 Mode bits */
++#define AK4458_MODE_SHIFT	6
++#define AK4458_MODE_MASK	GENMASK(7, 6)
++#define AK4458_MODE_NORMAL	(0 << AK4458_MODE_SHIFT)
++#define AK4458_MODE_TDM128	(1 << AK4458_MODE_SHIFT)
++#define AK4458_MODE_TDM256	(2 << AK4458_MODE_SHIFT)
++#define AK4458_MODE_TDM512	(3 << AK4458_MODE_SHIFT)
++
++/* DAC Digital attenuator transition time setting
++ * Table 19
++ * Mode	ATS1	ATS2	ATT speed
++ * 0	0	0	4080/fs
++ * 1	0	1	2040/fs
++ * 2	1	0	510/fs
++ * 3	1	1	255/fs
++ * */
++#define AK4458_ATS_SHIFT	6
++#define AK4458_ATS_MASK		GENMASK(7, 6)
++
++#endif /* _AK4458_H */
+diff --git a/module_drivers/sound/soc/ingenic/ecodec/ak5558.c b/module_drivers/sound/soc/ingenic/ecodec/ak5558.c
+new file mode 100644
+index 000000000..1cd3093c1
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/ecodec/ak5558.c
+@@ -0,0 +1,425 @@
++// SPDX-License-Identifier: GPL-2.0
++//
++// Audio driver for AK5558 ADC
++//
++// Copyright (C) 2015 Asahi Kasei Microdevices Corporation
++// Copyright 2018 NXP
++
++#include <linux/delay.h>
++#include <linux/gpio/consumer.h>
++#include <linux/i2c.h>
++#include <linux/module.h>
++#include <linux/pm_runtime.h>
++#include <linux/regmap.h>
++#include <linux/slab.h>
++
++#include <sound/initval.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++#include <sound/tlv.h>
++
++#include "ak5558.h"
++
++/* AK5558 Codec Private Data */
++struct ak5558_priv {
++	struct snd_soc_component component;
++	struct regmap *regmap;
++	struct i2c_client *i2c;
++	struct gpio_desc *reset_gpiod; /* Reset & Power down GPIO */
++	int slots;
++	int slot_width;
++};
++
++/* ak5558 register cache & default register settings */
++static const struct reg_default ak5558_reg[] = {
++	{ 0x0, 0xFF },	/*	0x00	AK5558_00_POWER_MANAGEMENT1	*/
++	{ 0x1, 0x01 },	/*	0x01	AK5558_01_POWER_MANAGEMENT2	*/
++	{ 0x2, 0x01 },	/*	0x02	AK5558_02_CONTROL1		*/
++	{ 0x3, 0x00 },	/*	0x03	AK5558_03_CONTROL2		*/
++	{ 0x4, 0x00 },	/*	0x04	AK5558_04_CONTROL3		*/
++	{ 0x5, 0x00 }	/*	0x05	AK5558_05_DSD			*/
++};
++
++static const char * const mono_texts[] = {
++	"8 Slot", "2 Slot", "4 Slot", "1 Slot",
++};
++
++static const struct soc_enum ak5558_mono_enum[] = {
++	SOC_ENUM_SINGLE(AK5558_01_POWER_MANAGEMENT2, 1,
++			ARRAY_SIZE(mono_texts), mono_texts),
++};
++
++static const char * const digfil_texts[] = {
++	"Sharp Roll-Off", "Show Roll-Off",
++	"Short Delay Sharp Roll-Off", "Short Delay Show Roll-Off",
++};
++
++static const struct soc_enum ak5558_adcset_enum[] = {
++	SOC_ENUM_SINGLE(AK5558_04_CONTROL3, 0,
++			ARRAY_SIZE(digfil_texts), digfil_texts),
++};
++
++static const struct snd_kcontrol_new ak5558_snd_controls[] = {
++	SOC_ENUM("AK5558 Monaural Mode", ak5558_mono_enum[0]),
++	SOC_ENUM("AK5558 Digital Filter", ak5558_adcset_enum[0]),
++};
++
++static const struct snd_soc_dapm_widget ak5558_dapm_widgets[] = {
++	/* Analog Input */
++	SND_SOC_DAPM_INPUT("AIN1"),
++	SND_SOC_DAPM_INPUT("AIN2"),
++	SND_SOC_DAPM_INPUT("AIN3"),
++	SND_SOC_DAPM_INPUT("AIN4"),
++	SND_SOC_DAPM_INPUT("AIN5"),
++	SND_SOC_DAPM_INPUT("AIN6"),
++	SND_SOC_DAPM_INPUT("AIN7"),
++	SND_SOC_DAPM_INPUT("AIN8"),
++
++	SND_SOC_DAPM_ADC("ADC Ch1", NULL, AK5558_00_POWER_MANAGEMENT1, 0, 0),
++	SND_SOC_DAPM_ADC("ADC Ch2", NULL, AK5558_00_POWER_MANAGEMENT1, 1, 0),
++	SND_SOC_DAPM_ADC("ADC Ch3", NULL, AK5558_00_POWER_MANAGEMENT1, 2, 0),
++	SND_SOC_DAPM_ADC("ADC Ch4", NULL, AK5558_00_POWER_MANAGEMENT1, 3, 0),
++	SND_SOC_DAPM_ADC("ADC Ch5", NULL, AK5558_00_POWER_MANAGEMENT1, 4, 0),
++	SND_SOC_DAPM_ADC("ADC Ch6", NULL, AK5558_00_POWER_MANAGEMENT1, 5, 0),
++	SND_SOC_DAPM_ADC("ADC Ch7", NULL, AK5558_00_POWER_MANAGEMENT1, 6, 0),
++	SND_SOC_DAPM_ADC("ADC Ch8", NULL, AK5558_00_POWER_MANAGEMENT1, 7, 0),
++
++	SND_SOC_DAPM_AIF_OUT("SDTO", "Capture", 0, SND_SOC_NOPM, 0, 0),
++};
++
++static const struct snd_soc_dapm_route ak5558_intercon[] = {
++	{"ADC Ch1", NULL, "AIN1"},
++	{"SDTO", NULL, "ADC Ch1"},
++
++	{"ADC Ch2", NULL, "AIN2"},
++	{"SDTO", NULL, "ADC Ch2"},
++
++	{"ADC Ch3", NULL, "AIN3"},
++	{"SDTO", NULL, "ADC Ch3"},
++
++	{"ADC Ch4", NULL, "AIN4"},
++	{"SDTO", NULL, "ADC Ch4"},
++
++	{"ADC Ch5", NULL, "AIN5"},
++	{"SDTO", NULL, "ADC Ch5"},
++
++	{"ADC Ch6", NULL, "AIN6"},
++	{"SDTO", NULL, "ADC Ch6"},
++
++	{"ADC Ch7", NULL, "AIN7"},
++	{"SDTO", NULL, "ADC Ch7"},
++
++	{"ADC Ch8", NULL, "AIN8"},
++	{"SDTO", NULL, "ADC Ch8"},
++};
++
++static int ak5558_set_mcki(struct snd_soc_component *component)
++{
++	return snd_soc_component_update_bits(component, AK5558_02_CONTROL1, AK5558_CKS,
++				   AK5558_CKS_AUTO);
++}
++
++static int ak5558_hw_params(struct snd_pcm_substream *substream,
++			    struct snd_pcm_hw_params *params,
++			    struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++	struct ak5558_priv *ak5558 = snd_soc_component_get_drvdata(component);
++	u8 bits;
++	int pcm_width = max(params_physical_width(params), ak5558->slot_width);
++
++	/* set master/slave audio interface */
++	bits = snd_soc_component_read32(component, AK5558_02_CONTROL1);
++	bits &= ~AK5558_BITS;
++
++	switch (pcm_width) {
++	case 16:
++		bits |= AK5558_DIF_24BIT_MODE;
++		break;
++	case 32:
++		bits |= AK5558_DIF_32BIT_MODE;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	snd_soc_component_update_bits(component, AK5558_02_CONTROL1, AK5558_BITS, bits);
++
++	return 0;
++}
++
++static int ak5558_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
++{
++	struct snd_soc_component *component = dai->component;
++	u8 format;
++
++	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++	case SND_SOC_DAIFMT_CBS_CFS:
++		break;
++	case SND_SOC_DAIFMT_CBM_CFM:
++		break;
++	case SND_SOC_DAIFMT_CBS_CFM:
++	case SND_SOC_DAIFMT_CBM_CFS:
++	default:
++		dev_err(dai->dev, "Clock mode unsupported");
++		return -EINVAL;
++	}
++
++	/* set master/slave audio interface */
++	format = snd_soc_component_read32(component, AK5558_02_CONTROL1);
++	format &= ~AK5558_DIF;
++
++	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_I2S:
++		format |= AK5558_DIF_I2S_MODE;
++		break;
++	case SND_SOC_DAIFMT_LEFT_J:
++		format |= AK5558_DIF_MSB_MODE;
++		break;
++	case SND_SOC_DAIFMT_DSP_B:
++		format |= AK5558_DIF_MSB_MODE;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	snd_soc_component_update_bits(component, AK5558_02_CONTROL1, AK5558_DIF, format);
++
++	return 0;
++}
++
++static int ak5558_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
++			       unsigned int rx_mask, int slots,
++			       int slot_width)
++{
++	struct snd_soc_component *component = dai->component;
++	struct ak5558_priv *ak5558 = snd_soc_component_get_drvdata(component);
++	int tdm_mode;
++
++	ak5558->slots = slots;
++	ak5558->slot_width = slot_width;
++
++	switch (slots * slot_width) {
++	case 128:
++		tdm_mode = AK5558_MODE_TDM128;
++		break;
++	case 256:
++		tdm_mode = AK5558_MODE_TDM256;
++		break;
++	case 512:
++		tdm_mode = AK5558_MODE_TDM512;
++		break;
++	default:
++		tdm_mode = AK5558_MODE_NORMAL;
++		break;
++	}
++
++	snd_soc_component_update_bits(component, AK5558_03_CONTROL2, AK5558_MODE_BITS,
++			    tdm_mode);
++	return 0;
++}
++
++#define AK5558_FORMATS	(SNDRV_PCM_FMTBIT_S16_LE |\
++			 SNDRV_PCM_FMTBIT_S24_LE |\
++			 SNDRV_PCM_FMTBIT_S32_LE)
++
++static const unsigned int ak5558_rates[] = {
++	8000, 11025,  16000, 22050,
++	32000, 44100, 48000, 88200,
++	96000, 176400, 192000, 352800,
++	384000, 705600, 768000, 1411200,
++	2822400,
++};
++
++static const struct snd_pcm_hw_constraint_list ak5558_rate_constraints = {
++	.count = ARRAY_SIZE(ak5558_rates),
++	.list = ak5558_rates,
++};
++
++static int ak5558_startup(struct snd_pcm_substream *substream,
++			  struct snd_soc_dai *dai)
++{
++	return snd_pcm_hw_constraint_list(substream->runtime, 0,
++					  SNDRV_PCM_HW_PARAM_RATE,
++					  &ak5558_rate_constraints);
++}
++
++static struct snd_soc_dai_ops ak5558_dai_ops = {
++	.startup        = ak5558_startup,
++	.hw_params	= ak5558_hw_params,
++
++	.set_fmt	= ak5558_set_dai_fmt,
++	.set_tdm_slot   = ak5558_set_tdm_slot,
++};
++
++static struct snd_soc_dai_driver ak5558_dai = {
++	.name = "ak5558-aif",
++	.capture = {
++		.stream_name = "Capture",
++		.channels_min = 1,
++		.channels_max = 8,
++		.rates = SNDRV_PCM_RATE_KNOT,
++		.formats = AK5558_FORMATS,
++	},
++	.ops = &ak5558_dai_ops,
++};
++
++static void ak5558_power_off(struct ak5558_priv *ak5558)
++{
++	if (!ak5558->reset_gpiod)
++		return;
++
++	gpiod_set_value_cansleep(ak5558->reset_gpiod, 0);
++	usleep_range(1000, 2000);
++}
++
++static void ak5558_power_on(struct ak5558_priv *ak5558)
++{
++	if (!ak5558->reset_gpiod)
++		return;
++
++	gpiod_set_value_cansleep(ak5558->reset_gpiod, 1);
++	usleep_range(1000, 2000);
++}
++
++static int ak5558_probe(struct snd_soc_component *component)
++{
++	struct ak5558_priv *ak5558 = snd_soc_component_get_drvdata(component);
++
++	ak5558_power_on(ak5558);
++	ak5558_set_mcki(component);
++	return 0;
++}
++
++static void ak5558_remove(struct snd_soc_component *component)
++{
++	struct ak5558_priv *ak5558 = snd_soc_component_get_drvdata(component);
++
++	ak5558_power_off(ak5558);
++}
++
++static int __maybe_unused ak5558_runtime_suspend(struct device *dev)
++{
++	struct ak5558_priv *ak5558 = dev_get_drvdata(dev);
++
++	regcache_cache_only(ak5558->regmap, true);
++	ak5558_power_off(ak5558);
++
++	return 0;
++}
++
++static int __maybe_unused ak5558_runtime_resume(struct device *dev)
++{
++	struct ak5558_priv *ak5558 = dev_get_drvdata(dev);
++
++	ak5558_power_off(ak5558);
++	ak5558_power_on(ak5558);
++
++	regcache_cache_only(ak5558->regmap, false);
++	regcache_mark_dirty(ak5558->regmap);
++
++	return regcache_sync(ak5558->regmap);
++}
++
++const struct dev_pm_ops ak5558_pm = {
++	SET_RUNTIME_PM_OPS(ak5558_runtime_suspend, ak5558_runtime_resume, NULL)
++	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
++				pm_runtime_force_resume)
++};
++
++struct snd_soc_component_driver soc_codec_dev_ak5558 = {
++	.probe			= ak5558_probe,
++	.remove			= ak5558_remove,
++	.controls		= ak5558_snd_controls,
++	.num_controls		= ARRAY_SIZE(ak5558_snd_controls),
++	.dapm_widgets		= ak5558_dapm_widgets,
++	.num_dapm_widgets	= ARRAY_SIZE(ak5558_dapm_widgets),
++	.dapm_routes		= ak5558_intercon,
++	.num_dapm_routes	= ARRAY_SIZE(ak5558_intercon),
++#if 0
++	.idle_bias_on		= 1,
++	.use_pmdown_time	= 1,
++	.endianness		= 1,
++	.non_legacy_dai_naming	= 1,
++#endif
++};
++
++static const struct regmap_config ak5558_regmap = {
++	.reg_bits = 8,
++	.val_bits = 8,
++
++	.max_register = AK5558_05_DSD,
++	.reg_defaults = ak5558_reg,
++	.num_reg_defaults = ARRAY_SIZE(ak5558_reg),
++	.cache_type = REGCACHE_RBTREE,
++};
++
++static int ak5558_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
++{
++	struct ak5558_priv *ak5558;
++	int ret = 0;
++
++	ak5558 = devm_kzalloc(&i2c->dev, sizeof(*ak5558), GFP_KERNEL);
++	if (!ak5558)
++		return -ENOMEM;
++
++	ak5558->regmap = devm_regmap_init_i2c(i2c, &ak5558_regmap);
++	if (IS_ERR(ak5558->regmap))
++		return PTR_ERR(ak5558->regmap);
++
++	i2c_set_clientdata(i2c, ak5558);
++	ak5558->i2c = i2c;
++
++	ak5558->reset_gpiod = devm_gpiod_get_optional(&i2c->dev, "reset",
++						      GPIOD_OUT_LOW);
++	if (IS_ERR(ak5558->reset_gpiod))
++		return PTR_ERR(ak5558->reset_gpiod);
++
++	ret = devm_snd_soc_register_component(&i2c->dev,
++				     &soc_codec_dev_ak5558,
++				     &ak5558_dai, 1);
++	if (ret)
++		return ret;
++
++	pm_runtime_enable(&i2c->dev);
++
++	printk("ak5558 probe ok, dev_name: %s\n", dev_name(&i2c->dev));
++	return 0;
++}
++
++static int ak5558_i2c_remove(struct i2c_client *i2c)
++{
++	pm_runtime_disable(&i2c->dev);
++
++	return 0;
++}
++
++static const struct i2c_device_id ak5558_i2c_table[] = {
++	{"ak5558", 0},
++	{}
++};
++MODULE_DEVICE_TABLE(i2c, ak4458_i2c_table);
++static const struct of_device_id ak5558_i2c_dt_ids[] = {
++	{ .compatible = "asahi-kasei,ak5558"},
++	{ }
++};
++
++static struct i2c_driver ak5558_i2c_driver = {
++	.driver = {
++		.name = "ak5558",
++		.of_match_table = of_match_ptr(ak5558_i2c_dt_ids),
++		.pm = &ak5558_pm,
++	},
++	.probe = ak5558_i2c_probe,
++	.remove = ak5558_i2c_remove,
++	.id_table = ak5558_i2c_table,
++};
++
++module_i2c_driver(ak5558_i2c_driver);
++
++MODULE_AUTHOR("Junichi Wakasugi <wakasugi.jb@om.asahi-kasei.co.jp>");
++MODULE_AUTHOR("Mihai Serban <mihai.serban@nxp.com>");
++MODULE_DESCRIPTION("ASoC AK5558 ADC driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/module_drivers/sound/soc/ingenic/ecodec/ak5558.h b/module_drivers/sound/soc/ingenic/ecodec/ak5558.h
+new file mode 100644
+index 000000000..61059086f
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/ecodec/ak5558.h
+@@ -0,0 +1,52 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Audio driver header for AK5558
++ *
++ * Copyright (C) 2016 Asahi Kasei Microdevices Corporation
++ * Copyright 2018 NXP
++ */
++
++#ifndef _AK5558_H
++#define _AK5558_H
++
++#define AK5558_00_POWER_MANAGEMENT1    0x00
++#define AK5558_01_POWER_MANAGEMENT2    0x01
++#define AK5558_02_CONTROL1             0x02
++#define AK5558_03_CONTROL2             0x03
++#define AK5558_04_CONTROL3             0x04
++#define AK5558_05_DSD                  0x05
++
++/* AK5558_02_CONTROL1 fields */
++#define AK5558_DIF			GENMASK(1, 1)
++#define AK5558_DIF_MSB_MODE		(0 << 1)
++#define AK5558_DIF_I2S_MODE		(1 << 1)
++
++#define AK5558_BITS			GENMASK(2, 2)
++#define AK5558_DIF_24BIT_MODE		(0 << 2)
++#define AK5558_DIF_32BIT_MODE		(1 << 2)
++
++#define AK5558_CKS			GENMASK(6, 3)
++#define AK5558_CKS_128FS_192KHZ		(0 << 3)
++#define AK5558_CKS_192FS_192KHZ		(1 << 3)
++#define AK5558_CKS_256FS_48KHZ		(2 << 3)
++#define AK5558_CKS_256FS_96KHZ		(3 << 3)
++#define AK5558_CKS_384FS_96KHZ		(4 << 3)
++#define AK5558_CKS_384FS_48KHZ		(5 << 3)
++#define AK5558_CKS_512FS_48KHZ		(6 << 3)
++#define AK5558_CKS_768FS_48KHZ		(7 << 3)
++#define AK5558_CKS_64FS_384KHZ		(8 << 3)
++#define AK5558_CKS_32FS_768KHZ		(9 << 3)
++#define AK5558_CKS_96FS_384KHZ		(10 << 3)
++#define AK5558_CKS_48FS_768KHZ		(11 << 3)
++#define AK5558_CKS_64FS_768KHZ		(12 << 3)
++#define AK5558_CKS_1024FS_16KHZ		(13 << 3)
++#define AK5558_CKS_AUTO			(15 << 3)
++
++/* AK5558_03_CONTROL2 fields */
++#define AK5558_MODE_BITS	GENMASK(6, 5)
++#define AK5558_MODE_NORMAL	(0 << 5)
++#define AK5558_MODE_TDM128	(1 << 5)
++#define AK5558_MODE_TDM256	(2 << 5)
++#define AK5558_MODE_TDM512	(3 << 5)
++
++#endif
+diff --git a/module_drivers/sound/soc/ingenic/ecodec/nau8822.c b/module_drivers/sound/soc/ingenic/ecodec/nau8822.c
+new file mode 100644
+index 000000000..2da9d1914
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/ecodec/nau8822.c
+@@ -0,0 +1,1179 @@
++/*
++ * nau8822.c  --  NAU8822 ALSA Soc Audio Codec driver
++ *
++ * Copyright 2015 Nuvoton Technology Corp.
++ *
++ * Author: David Lin <ctlin0@nuvoton.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++//#define DEBUG
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/pm.h>
++#include <linux/i2c.h>
++#include <linux/regmap.h>
++#include <linux/of_device.h>
++#include <linux/of_gpio.h>
++#include <linux/slab.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/initval.h>
++#include <sound/tlv.h>
++#include <asm/div64.h>
++#include "nau8822.h"
++
++#if 0
++#define ENTER()								\
++	do {								\
++		printk("%03d nau8822 ENTER %s()\n", __LINE__, __PRETTY_FUNCTION__); \
++	} while (0)
++#define MYDBG(sss, aaa...)						\
++	do {								\
++		printk("%03d nau8822 debug %s() " sss "\n", __LINE__, __PRETTY_FUNCTION__, ##aaa); \
++	} while (0)
++#else
++#define ENTER()					\
++	do {					\
++	} while (0)
++#define LEAVE()					\
++	do {					\
++	} while (0)
++#define MYDBG(sss, aaa...)			\
++	do {					\
++	} while (0)
++#endif
++
++
++static int nau8822_reg_read2(void *context, unsigned int reg, unsigned int *value)
++{
++	struct i2c_client *client = (struct i2c_client *)context;
++	//struct nau8822_priv * nau8822 = (struct nau8822_priv *)i2c_get_clientdata(client);
++	uint8_t buf[2] = {(reg&0xff)<<1,};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 1,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 2,
++			.buf	= value,
++		}
++	};
++	int ret = 0;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	MYDBG("ret=%x, value=%x", ret, *value);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++static int nau8822_reg_read(struct nau8822_priv * nau8822, unsigned short reg,
++		unsigned short *value)
++{
++	struct i2c_client *client = nau8822->i2c;
++	uint8_t buf[2] = {(reg&0xff)<<1,};
++	struct i2c_msg msg[2] = {
++		[0] = {
++			.addr	= client->addr,
++			.flags	= 0,
++			.len	= 1,
++			.buf	= buf,
++		},
++		[1] = {
++			.addr	= client->addr,
++			.flags	= I2C_M_RD,
++			.len	= 2,
++			.buf	= value,
++		}
++	};
++	int ret = 0;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	MYDBG("ret=%x, value=%x", ret, *value);
++	if(ret > 0)
++		ret = 0;
++
++	return ret;
++}
++
++
++
++
++#define NAU_PLL_FREQ_MAX 100000000
++#define NAU_PLL_FREQ_MIN 90000000
++#define NAU_PLL_REF_MAX 33000000
++#define NAU_PLL_REF_MIN 8000000
++#define NAU_PLL_OPTOP_MIN 6
++
++static const int nau8822_mclk_scaler[] = { 10, 15, 20, 30, 40, 60, 80, 120 };
++
++static const struct reg_default nau8822_reg_defaults[] = {
++	{ NAU8822_REG_POWER_MANAGEMENT_1, 0x0000 },
++	{ NAU8822_REG_POWER_MANAGEMENT_2, 0x0000 },
++	{ NAU8822_REG_POWER_MANAGEMENT_3, 0x0000 },
++	{ NAU8822_REG_AUDIO_INTERFACE, 0x0050 },
++	{ NAU8822_REG_COMPANDING_CONTROL, 0x0000 },
++	{ NAU8822_REG_CLOCKING, 0x0140 },
++	{ NAU8822_REG_ADDITIONAL_CONTROL, 0x0000 },
++	{ NAU8822_REG_GPIO_CONTROL, 0x0000 },
++	{ NAU8822_REG_JACK_DETECT_CONTROL_1, 0x0000 },
++	{ NAU8822_REG_DAC_CONTROL, 0x0000 },
++	{ NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME, 0x00ff },
++	{ NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME, 0x00ff },
++	{ NAU8822_REG_JACK_DETECT_CONTROL_2, 0x0000 },
++	{ NAU8822_REG_ADC_CONTROL, 0x0100 },
++	{ NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME, 0x00ff },
++	{ NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME, 0x00ff },
++	{ NAU8822_REG_EQ1, 0x012c },
++	{ NAU8822_REG_EQ2, 0x002c },
++	{ NAU8822_REG_EQ3, 0x002c },
++	{ NAU8822_REG_EQ4, 0x002c },
++	{ NAU8822_REG_EQ5, 0x002c },
++	{ NAU8822_REG_DAC_LIMITER_1, 0x0032 },
++	{ NAU8822_REG_DAC_LIMITER_2, 0x0000 },
++	{ NAU8822_REG_NOTCH_FILTER_1, 0x0000 },
++	{ NAU8822_REG_NOTCH_FILTER_2, 0x0000 },
++	{ NAU8822_REG_NOTCH_FILTER_3, 0x0000 },
++	{ NAU8822_REG_NOTCH_FILTER_4, 0x0000 },
++	{ NAU8822_REG_ALC_CONTROL_1, 0x0038 },
++	{ NAU8822_REG_ALC_CONTROL_2, 0x000b },
++	{ NAU8822_REG_ALC_CONTROL_3, 0x0032 },
++	{ NAU8822_REG_NOISE_GATE, 0x0010 },
++	{ NAU8822_REG_PLL_N, 0x0008 },
++	{ NAU8822_REG_PLL_K1, 0x000c },
++	{ NAU8822_REG_PLL_K2, 0x0093 },
++	{ NAU8822_REG_PLL_K3, 0x00e9 },
++	{ NAU8822_REG_3D_CONTROL, 0x0000 },
++	{ NAU8822_REG_RIGHT_SPEAKER_CONTROL, 0x0000 },
++	{ NAU8822_REG_INPUT_CONTROL, 0x0033 },
++	{ NAU8822_REG_LEFT_INP_PGA_CONTROL, 0x0010 },
++	{ NAU8822_REG_RIGHT_INP_PGA_CONTROL, 0x0010 },
++	{ NAU8822_REG_LEFT_ADC_BOOST_CONTROL, 0x0100 },
++	{ NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 0x0100 },
++	{ NAU8822_REG_OUTPUT_CONTROL, 0x0002 },
++	{ NAU8822_REG_LEFT_MIXER_CONTROL, 0x0001 },
++	{ NAU8822_REG_RIGHT_MIXER_CONTROL, 0x0001 },
++	{ NAU8822_REG_LHP_VOLUME, 0x0039 },
++	{ NAU8822_REG_RHP_VOLUME, 0x0039 },
++	{ NAU8822_REG_LSPKOUT_VOLUME, 0x0039 },
++	{ NAU8822_REG_RSPKOUT_VOLUME, 0x0039 },
++	{ NAU8822_REG_AUX2_MIXER, 0x0001 },
++	{ NAU8822_REG_AUX1_MIXER, 0x0001 },
++	{ NAU8822_REG_POWER_MANAGEMENT_4, 0x0000 },
++	{ NAU8822_REG_LEFT_TIME_SLOT, 0x0000 },
++	{ NAU8822_REG_MISC, 0x0020 },
++	{ NAU8822_REG_RIGHT_TIME_SLOT, 0x0000 },
++	{ NAU8822_REG_DEVICE_REVISION, 0x007f },
++	{ NAU8822_REG_DEVICE_ID, 0x001a },
++	{ NAU8822_REG_DAC_DITHER, 0x0114 },
++	{ NAU8822_REG_ALC_ENHANCE_1, 0x0000 },
++	{ NAU8822_REG_ALC_ENHANCE_2, 0x0000 },
++	{ NAU8822_REG_192KHZ_SAMPLING, 0x0008 },
++	{ NAU8822_REG_MISC_CONTROL, 0x0000 },
++	{ NAU8822_REG_INPUT_TIEOFF, 0x0000 },
++	{ NAU8822_REG_POWER_REDUCTION, 0x0000 },
++	{ NAU8822_REG_AGC_PEAK2PEAK, 0x0000 },
++	{ NAU8822_REG_AGC_PEAK_DETECT, 0x0000 },
++	{ NAU8822_REG_AUTOMUTE_CONTROL, 0x0000 },
++	{ NAU8822_REG_OUTPUT_TIEOFF, 0x0000 },
++};
++
++static bool nau8822_readable_reg(struct device *dev, unsigned int reg)
++{
++	//MYDBG("reg=%x", reg);
++	switch (reg) {
++	case NAU8822_REG_RESET ... NAU8822_REG_JACK_DETECT_CONTROL_1:
++	case NAU8822_REG_DAC_CONTROL ... NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME:
++	case NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME:
++	case NAU8822_REG_EQ1 ... NAU8822_REG_EQ5:
++	case NAU8822_REG_DAC_LIMITER_1 ... NAU8822_REG_DAC_LIMITER_2:
++	case NAU8822_REG_NOTCH_FILTER_1 ... NAU8822_REG_NOTCH_FILTER_4:
++	case NAU8822_REG_ALC_CONTROL_1 ...NAU8822_REG_PLL_K3:
++	case NAU8822_REG_3D_CONTROL:
++	case NAU8822_REG_RIGHT_SPEAKER_CONTROL ... NAU8822_REG_LEFT_ADC_BOOST_CONTROL:
++	case NAU8822_REG_RIGHT_ADC_BOOST_CONTROL ... NAU8822_REG_AUX1_MIXER:
++	case NAU8822_REG_POWER_MANAGEMENT_4 ... NAU8822_REG_DEVICE_ID:
++	case NAU8822_REG_DAC_DITHER:
++	case NAU8822_REG_ALC_ENHANCE_1 ... NAU8822_REG_MISC_CONTROL:
++	case NAU8822_REG_INPUT_TIEOFF ... NAU8822_REG_OUTPUT_TIEOFF:
++		return true;
++	default:
++		return false;
++	}
++
++	return true;
++}
++
++static bool nau8822_writeable_reg(struct device *dev, unsigned int reg)
++{
++	//MYDBG("reg=%x", reg);
++	switch (reg) {
++	case NAU8822_REG_RESET ... NAU8822_REG_JACK_DETECT_CONTROL_1:
++	case NAU8822_REG_DAC_CONTROL ... NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME:
++	case NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME:
++	case NAU8822_REG_EQ1 ... NAU8822_REG_EQ5:
++	case NAU8822_REG_DAC_LIMITER_1 ... NAU8822_REG_DAC_LIMITER_2:
++	case NAU8822_REG_NOTCH_FILTER_1 ... NAU8822_REG_NOTCH_FILTER_4:
++	case NAU8822_REG_ALC_CONTROL_1 ...NAU8822_REG_PLL_K3:
++	case NAU8822_REG_3D_CONTROL:
++	case NAU8822_REG_RIGHT_SPEAKER_CONTROL ... NAU8822_REG_LEFT_ADC_BOOST_CONTROL:
++	case NAU8822_REG_RIGHT_ADC_BOOST_CONTROL ... NAU8822_REG_AUX1_MIXER:
++	case NAU8822_REG_POWER_MANAGEMENT_4 ... NAU8822_REG_DEVICE_ID:
++	case NAU8822_REG_DAC_DITHER:
++	case NAU8822_REG_ALC_ENHANCE_1 ... NAU8822_REG_MISC_CONTROL:
++	case NAU8822_REG_INPUT_TIEOFF ... NAU8822_REG_OUTPUT_TIEOFF:
++		return true;
++	default:
++		return false;
++	}
++
++	return true;
++}
++
++static bool nau8822_volatile(struct device *dev, unsigned int reg)
++{
++	//MYDBG("reg=%x", reg);
++	//return true;
++	switch (reg) {
++	case NAU8822_REG_RESET:
++	case NAU8822_REG_DEVICE_REVISION:
++	case NAU8822_REG_DEVICE_ID:
++	case NAU8822_REG_AGC_PEAK2PEAK:
++	case NAU8822_REG_AGC_PEAK_DETECT:
++	case NAU8822_REG_AUTOMUTE_CONTROL:
++		return true;
++	default:
++		return false;
++	}
++}
++
++static const char *nau8822_companding[] = {"Off", "NC", "u-law", "A-law"};
++static const char *nau8822_eqmode[] = {"Capture", "Playback"};
++static const char *nau8822_bw[] = {"Narrow", "Wide"};
++static const char *nau8822_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz"};
++static const char *nau8822_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz"};
++static const char *nau8822_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz"};
++static const char *nau8822_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"};
++static const char *nau8822_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"};
++static const char *nau8822_alc3[] = {"ALC", "Limiter"};
++static const char *nau8822_alc1[] = {"Off", "Right", "Left", "Both"};
++
++static const SOC_ENUM_SINGLE_DECL(adc_compand, NAU8822_REG_COMPANDING_CONTROL, 1,
++				  nau8822_companding);
++static const SOC_ENUM_SINGLE_DECL(dac_compand, NAU8822_REG_COMPANDING_CONTROL, 3,
++				  nau8822_companding);
++static const SOC_ENUM_SINGLE_DECL(eqmode, NAU8822_REG_EQ1, 8, nau8822_eqmode);
++static const SOC_ENUM_SINGLE_DECL(eq1, NAU8822_REG_EQ1, 5, nau8822_eq1);
++static const SOC_ENUM_SINGLE_DECL(eq2bw, NAU8822_REG_EQ2, 8, nau8822_bw);
++static const SOC_ENUM_SINGLE_DECL(eq2, NAU8822_REG_EQ2, 5, nau8822_eq2);
++static const SOC_ENUM_SINGLE_DECL(eq3bw, NAU8822_REG_EQ3, 8, nau8822_bw);
++static const SOC_ENUM_SINGLE_DECL(eq3, NAU8822_REG_EQ3, 5, nau8822_eq3);
++static const SOC_ENUM_SINGLE_DECL(eq4bw, NAU8822_REG_EQ4, 8, nau8822_bw);
++static const SOC_ENUM_SINGLE_DECL(eq4, NAU8822_REG_EQ4, 5, nau8822_eq4);
++static const SOC_ENUM_SINGLE_DECL(eq5, NAU8822_REG_EQ5, 5, nau8822_eq5);
++static const SOC_ENUM_SINGLE_DECL(alc3, NAU8822_REG_ALC_CONTROL_3, 8, nau8822_alc3);
++static const SOC_ENUM_SINGLE_DECL(alc1, NAU8822_REG_ALC_CONTROL_1, 7, nau8822_alc1);
++
++static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
++static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
++static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
++static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
++static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
++static const DECLARE_TLV_DB_SCALE(limiter_tlv, 0, 100, 0);
++
++static const struct snd_kcontrol_new nau8822_snd_controls[] = {
++
++	SOC_SINGLE("Digital Loopback Switch",
++		NAU8822_REG_COMPANDING_CONTROL, 0, 1, 0),
++
++	SOC_ENUM("ADC Companding", adc_compand),
++	SOC_ENUM("DAC Companding", dac_compand),
++
++	SOC_DOUBLE("DAC Inversion Switch", NAU8822_REG_DAC_CONTROL, 0, 1, 1, 0),
++
++	SOC_DOUBLE_R_TLV("PCM Volume",
++		NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME, NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME,
++		0, 255, 0, digital_tlv),
++
++	SOC_SINGLE("High Pass Filter Switch", NAU8822_REG_ADC_CONTROL, 8, 1, 0),
++	SOC_SINGLE("High Pass Cut Off", NAU8822_REG_ADC_CONTROL, 4, 7, 0),
++	SOC_DOUBLE("ADC Inversion Switch", NAU8822_REG_ADC_CONTROL, 0, 1, 1, 0),
++
++	SOC_DOUBLE_R_TLV("ADC Volume",
++		NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME, NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME,
++		0, 255, 0, digital_tlv),
++
++	SOC_ENUM("Equaliser Function", eqmode),
++	SOC_ENUM("EQ1 Cut Off", eq1),
++	SOC_SINGLE_TLV("EQ1 Volume", NAU8822_REG_EQ1,  0, 24, 1, eq_tlv),
++
++	SOC_ENUM("Equaliser EQ2 Bandwidth", eq2bw),
++	SOC_ENUM("EQ2 Cut Off", eq2),
++	SOC_SINGLE_TLV("EQ2 Volume", NAU8822_REG_EQ2,  0, 24, 1, eq_tlv),
++
++	SOC_ENUM("Equaliser EQ3 Bandwidth", eq3bw),
++	SOC_ENUM("EQ3 Cut Off", eq3),
++	SOC_SINGLE_TLV("EQ3 Volume", NAU8822_REG_EQ3,  0, 24, 1, eq_tlv),
++
++	SOC_ENUM("Equaliser EQ4 Bandwidth", eq4bw),
++	SOC_ENUM("EQ4 Cut Off", eq4),
++	SOC_SINGLE_TLV("EQ4 Volume", NAU8822_REG_EQ4,  0, 24, 1, eq_tlv),
++
++	SOC_ENUM("EQ5 Cut Off", eq5),
++	SOC_SINGLE_TLV("EQ5 Volume", NAU8822_REG_EQ5, 0, 24, 1, eq_tlv),
++
++	SOC_SINGLE("DAC Playback Limiter Switch",
++		NAU8822_REG_DAC_LIMITER_1, 8, 1, 0),
++	SOC_SINGLE("DAC Playback Limiter Decay",
++		NAU8822_REG_DAC_LIMITER_1, 4, 15, 0),
++	SOC_SINGLE("DAC Playback Limiter Attack",
++		NAU8822_REG_DAC_LIMITER_1, 0, 15, 0),
++
++	SOC_SINGLE("DAC Playback Limiter Threshold",
++		NAU8822_REG_DAC_LIMITER_2, 4, 7, 0),
++	SOC_SINGLE_TLV("DAC Playback Limiter Volume",
++		NAU8822_REG_DAC_LIMITER_2, 0, 12, 0, limiter_tlv),
++
++	SOC_ENUM("ALC Enable Switch", alc1),
++	SOC_SINGLE("ALC Capture Min Gain", NAU8822_REG_ALC_CONTROL_1, 0, 7, 0),
++	SOC_SINGLE("ALC Capture Max Gain", NAU8822_REG_ALC_CONTROL_1, 3, 7, 0),
++
++	SOC_SINGLE("ALC Capture Hold", NAU8822_REG_ALC_CONTROL_2, 4, 10, 0),
++	SOC_SINGLE("ALC Capture Target", NAU8822_REG_ALC_CONTROL_2, 0, 15, 0),
++
++	SOC_ENUM("ALC Capture Mode", alc3),
++	SOC_SINGLE("ALC Capture Decay", NAU8822_REG_ALC_CONTROL_3, 4, 10, 0),
++	SOC_SINGLE("ALC Capture Attack", NAU8822_REG_ALC_CONTROL_3, 0, 10, 0),
++
++	SOC_SINGLE("ALC Capture Noise Gate Switch", NAU8822_REG_NOISE_GATE, 3, 1, 0),
++	SOC_SINGLE("ALC Capture Noise Gate Threshold",
++		NAU8822_REG_NOISE_GATE, 0, 7, 0),
++
++	SOC_DOUBLE_R("Capture PGA ZC Switch",
++		NAU8822_REG_LEFT_INP_PGA_CONTROL, NAU8822_REG_RIGHT_INP_PGA_CONTROL,
++		7, 1, 0),
++
++	SOC_DOUBLE_R("Headphone Playback ZC Switch",
++		NAU8822_REG_LHP_VOLUME, NAU8822_REG_RHP_VOLUME, 7, 1, 0),
++
++	SOC_DOUBLE_R_TLV("Headphone Playback Volume",
++		NAU8822_REG_LHP_VOLUME, NAU8822_REG_RHP_VOLUME,	0, 63, 0, spk_tlv),
++
++	SOC_DOUBLE_R("Speaker Playback ZC Switch",
++		NAU8822_REG_LSPKOUT_VOLUME, NAU8822_REG_RSPKOUT_VOLUME, 7, 1, 0),
++
++	SOC_DOUBLE_R_TLV("Speaker Playback Volume",
++		NAU8822_REG_LSPKOUT_VOLUME, NAU8822_REG_RSPKOUT_VOLUME,
++		0, 63, 0, spk_tlv),
++
++	SOC_DOUBLE_R("Line Playback Switch",
++		NAU8822_REG_AUX2_MIXER, NAU8822_REG_AUX1_MIXER, 6, 1, 1),
++
++	SOC_DOUBLE_R("PGA Boost (+20dB)",
++		NAU8822_REG_LEFT_ADC_BOOST_CONTROL, NAU8822_REG_RIGHT_ADC_BOOST_CONTROL,
++		8, 1, 0),
++	SOC_DOUBLE_R_TLV("L2/R2 Boost Volume",
++		NAU8822_REG_LEFT_ADC_BOOST_CONTROL, NAU8822_REG_RIGHT_ADC_BOOST_CONTROL,
++		4, 7, 0, boost_tlv),
++	SOC_DOUBLE_R_TLV("Aux Boost Volume",
++		NAU8822_REG_LEFT_ADC_BOOST_CONTROL, NAU8822_REG_RIGHT_ADC_BOOST_CONTROL,
++		0, 7, 0, boost_tlv),
++
++	SOC_DOUBLE_R_TLV("Input PGA Volume",
++		NAU8822_REG_LEFT_INP_PGA_CONTROL, NAU8822_REG_RIGHT_INP_PGA_CONTROL,
++		0, 63, 0, inpga_tlv),
++
++	SOC_DOUBLE_R("Headphone Switch",
++		NAU8822_REG_LHP_VOLUME, NAU8822_REG_RHP_VOLUME, 6, 1, 1),
++
++	SOC_DOUBLE_R("Speaker Switch",
++		NAU8822_REG_LSPKOUT_VOLUME, NAU8822_REG_RSPKOUT_VOLUME, 6, 1, 1),
++
++	SOC_SINGLE("DAC 128x Oversampling Switch", NAU8822_REG_DAC_CONTROL,
++		   5, 1, 0),
++	SOC_SINGLE("ADC 128x Oversampling Switch", NAU8822_REG_ADC_CONTROL,
++		   5, 1, 0),
++};
++
++/* LMAIN and RMAIN Mixer */
++static const struct snd_kcontrol_new nau8822_left_out_mixer[] = {
++	SOC_DAPM_SINGLE("LINMIX Switch", NAU8822_REG_LEFT_MIXER_CONTROL, 1, 1, 0),
++	SOC_DAPM_SINGLE("LAUX Switch", NAU8822_REG_LEFT_MIXER_CONTROL, 5, 1, 0),
++	SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_LEFT_MIXER_CONTROL, 0, 1, 0),
++	SOC_DAPM_SINGLE("RDAC Switch", NAU8822_REG_OUTPUT_CONTROL, 5, 1, 0),
++};
++
++static const struct snd_kcontrol_new nau8822_right_out_mixer[] = {
++	SOC_DAPM_SINGLE("RINMIX Switch", NAU8822_REG_RIGHT_MIXER_CONTROL, 1, 1, 0),
++	SOC_DAPM_SINGLE("RAUX Switch", NAU8822_REG_RIGHT_MIXER_CONTROL, 5, 1, 0),
++	SOC_DAPM_SINGLE("RDAC Switch", NAU8822_REG_RIGHT_MIXER_CONTROL, 0, 1, 0),
++	SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_OUTPUT_CONTROL, 6, 1, 0),
++};
++
++/* AUX1 and AUX2 Mixer */
++static const struct snd_kcontrol_new nau8822_auxout1_mixer[] = {
++	SOC_DAPM_SINGLE("RDAC Switch", NAU8822_REG_AUX1_MIXER, 0, 1, 0),
++	SOC_DAPM_SINGLE("RMIX Switch", NAU8822_REG_AUX1_MIXER, 1, 1, 0),
++	SOC_DAPM_SINGLE("RINMIX Switch", NAU8822_REG_AUX1_MIXER, 2, 1, 0),
++	SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_AUX1_MIXER, 3, 1, 0),
++	SOC_DAPM_SINGLE("LMIX Switch", NAU8822_REG_AUX1_MIXER, 4, 1, 0),
++};
++
++static const struct snd_kcontrol_new nau8822_auxout2_mixer[] = {
++	SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_AUX2_MIXER, 0, 1, 0),
++	SOC_DAPM_SINGLE("LMIX Switch", NAU8822_REG_AUX2_MIXER, 1, 1, 0),
++	SOC_DAPM_SINGLE("LINMIX Switch", NAU8822_REG_AUX2_MIXER, 2, 1, 0),
++	SOC_DAPM_SINGLE("AUX1MIX Output Switch", NAU8822_REG_AUX1_MIXER, 3, 1, 0),
++};
++
++/* Input PGA */
++static const struct snd_kcontrol_new nau8822_left_input_mixer[] = {
++	SOC_DAPM_SINGLE("L2 Switch", NAU8822_REG_INPUT_CONTROL, 2, 1, 0),
++	SOC_DAPM_SINGLE("MicN Switch", NAU8822_REG_INPUT_CONTROL, 1, 1, 0),
++	SOC_DAPM_SINGLE("MicP Switch", NAU8822_REG_INPUT_CONTROL, 0, 1, 0),
++};
++static const struct snd_kcontrol_new nau8822_right_input_mixer[] = {
++	SOC_DAPM_SINGLE("R2 Switch", NAU8822_REG_INPUT_CONTROL, 6, 1, 0),
++	SOC_DAPM_SINGLE("MicN Switch", NAU8822_REG_INPUT_CONTROL, 5, 1, 0),
++	SOC_DAPM_SINGLE("MicP Switch", NAU8822_REG_INPUT_CONTROL, 4, 1, 0),
++};
++
++static int check_mclk_select_pll(struct snd_soc_dapm_widget *source,
++			 struct snd_soc_dapm_widget *sink)
++{
++	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
++	struct nau8822_priv *nau8822 = snd_soc_codec_get_drvdata(codec);
++	unsigned int value;
++
++	ENTER();
++	regmap_read(nau8822->regmap, NAU8822_REG_CLOCKING, &value);
++
++	return (value & NAU8822_CLKM_MASK);
++}
++
++static const struct snd_soc_dapm_widget nau8822_dapm_widgets[] = {
++	SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
++			 NAU8822_REG_POWER_MANAGEMENT_3, 0, 0),
++	SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
++			 NAU8822_REG_POWER_MANAGEMENT_3, 1, 0),
++	SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
++			 NAU8822_REG_POWER_MANAGEMENT_2, 0, 0),
++	SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
++			 NAU8822_REG_POWER_MANAGEMENT_2, 1, 0),
++
++	SOC_MIXER_ARRAY("Left Output Mixer", NAU8822_REG_POWER_MANAGEMENT_3,
++			2, 0, nau8822_left_out_mixer),
++	SOC_MIXER_ARRAY("Right Output Mixer", NAU8822_REG_POWER_MANAGEMENT_3,
++			3, 0, nau8822_right_out_mixer),
++	SOC_MIXER_ARRAY("AUX1 Output Mixer", NAU8822_REG_POWER_MANAGEMENT_1,
++			7, 0, nau8822_auxout1_mixer),
++	SOC_MIXER_ARRAY("AUX2 Output Mixer", NAU8822_REG_POWER_MANAGEMENT_1,
++			6, 0, nau8822_auxout2_mixer),
++
++	SOC_MIXER_ARRAY("Left Input Mixer", NAU8822_REG_POWER_MANAGEMENT_2,
++			2, 0, nau8822_left_input_mixer),
++	SOC_MIXER_ARRAY("Right Input Mixer", NAU8822_REG_POWER_MANAGEMENT_2,
++			3, 0, nau8822_right_input_mixer),
++
++	SND_SOC_DAPM_PGA("Left Boost Mixer", NAU8822_REG_POWER_MANAGEMENT_2,
++			 4, 0, NULL, 0),
++	SND_SOC_DAPM_PGA("Right Boost Mixer", NAU8822_REG_POWER_MANAGEMENT_2,
++			 5, 0, NULL, 0),
++
++	SND_SOC_DAPM_PGA("Left Capture PGA", NAU8822_REG_LEFT_INP_PGA_CONTROL,
++			 6, 1, NULL, 0),
++	SND_SOC_DAPM_PGA("Right Capture PGA", NAU8822_REG_RIGHT_INP_PGA_CONTROL,
++			 6, 1, NULL, 0),
++
++	SND_SOC_DAPM_PGA("Left Headphone Out", NAU8822_REG_POWER_MANAGEMENT_2,
++			 7, 0, NULL, 0),
++	SND_SOC_DAPM_PGA("Right Headphone Out", NAU8822_REG_POWER_MANAGEMENT_2,
++			 8, 0, NULL, 0),
++
++	SND_SOC_DAPM_PGA("Left Speaker Out", NAU8822_REG_POWER_MANAGEMENT_3,
++			 6, 0, NULL, 0),
++	SND_SOC_DAPM_PGA("Right Speaker Out", NAU8822_REG_POWER_MANAGEMENT_3,
++			 5, 0, NULL, 0),
++
++	SND_SOC_DAPM_PGA("AUX1 Out", NAU8822_REG_POWER_MANAGEMENT_3,
++			   8, 0, NULL, 0),
++	SND_SOC_DAPM_PGA("AUX2 Out", NAU8822_REG_POWER_MANAGEMENT_3,
++			   7, 0, NULL, 0),
++
++	SND_SOC_DAPM_SUPPLY("Mic Bias", NAU8822_REG_POWER_MANAGEMENT_1,
++			4, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("PLL", NAU8822_REG_POWER_MANAGEMENT_1,
++			5, 0, NULL, 0),
++
++	SND_SOC_DAPM_INPUT("LMICN"),
++	SND_SOC_DAPM_INPUT("LMICP"),
++	SND_SOC_DAPM_INPUT("RMICN"),
++	SND_SOC_DAPM_INPUT("RMICP"),
++	SND_SOC_DAPM_INPUT("LAUX"),
++	SND_SOC_DAPM_INPUT("RAUX"),
++	SND_SOC_DAPM_INPUT("L2"),
++	SND_SOC_DAPM_INPUT("R2"),
++	SND_SOC_DAPM_OUTPUT("LHP"),
++	SND_SOC_DAPM_OUTPUT("RHP"),
++	SND_SOC_DAPM_OUTPUT("LSPK"),
++	SND_SOC_DAPM_OUTPUT("RSPK"),
++	SND_SOC_DAPM_OUTPUT("AUXOUT1"),
++	SND_SOC_DAPM_OUTPUT("AUXOUT2"),
++};
++
++static const struct snd_soc_dapm_route nau8822_dapm_routes[] = {
++	{"Right DAC", NULL, "PLL", check_mclk_select_pll},
++	{"Left DAC", NULL, "PLL", check_mclk_select_pll},
++
++	/* LMAIN and RMAIN mixer */
++	{"Right Output Mixer", "LDAC Switch", "Left DAC"},
++	{"Right Output Mixer", "RDAC Switch", "Right DAC"},
++	{"Right Output Mixer", "RAUX Switch", "RAUX"},
++	{"Right Output Mixer", "RINMIX Switch", "Right Boost Mixer"},
++
++	{"Left Output Mixer", "LDAC Switch", "Left DAC"},
++	{"Left Output Mixer", "RDAC Switch", "Right DAC"},
++	{"Left Output Mixer", "LAUX Switch", "LAUX"},
++	{"Left Output Mixer", "LINMIX Switch", "Left Boost Mixer"},
++
++	/* AUX1 and AUX2 mixer */
++	{"AUX1 Output Mixer", "RDAC Switch", "Right DAC"},
++	{"AUX1 Output Mixer", "RMIX Switch", "Right Output Mixer"},
++	{"AUX1 Output Mixer", "RINMIX Switch", "Right Boost Mixer"},
++	{"AUX1 Output Mixer", "LDAC Switch", "Left DAC"},
++	{"AUX1 Output Mixer", "LMIX Switch", "Left Output Mixer"},
++
++	{"AUX2 Output Mixer", "LDAC Switch", "Left DAC"},
++	{"AUX2 Output Mixer", "LMIX Switch", "Left Output Mixer"},
++	{"AUX2 Output Mixer", "LINMIX Switch", "Left Boost Mixer"},
++	{"AUX2 Output Mixer", "AUX1MIX Output Switch", "AUX1 Output Mixer"},
++
++	/* Outputs */
++	{"Right Headphone Out", NULL, "Right Output Mixer"},
++	{"RHP", NULL, "Right Headphone Out"},
++
++	{"Left Headphone Out", NULL, "Left Output Mixer"},
++	{"LHP", NULL, "Left Headphone Out"},
++
++	{"Right Speaker Out", NULL, "Right Output Mixer"},
++	{"RSPK", NULL, "Right Speaker Out"},
++
++	{"Left Speaker Out", NULL, "Left Output Mixer"},
++	{"LSPK", NULL, "Left Speaker Out"},
++
++	{"AUX1 Out", NULL, "AUX1 Output Mixer"},
++	{"AUX2 Out", NULL, "AUX2 Output Mixer"},
++	{"AUXOUT1", NULL, "AUX1 Out"},
++	{"AUXOUT2", NULL, "AUX2 Out"},
++
++	/* Boost Mixer */
++	{"Right ADC", NULL, "PLL", check_mclk_select_pll},
++	{"Left ADC", NULL, "PLL", check_mclk_select_pll},
++
++	{"Right ADC", NULL, "Right Boost Mixer"},
++
++	{"Right Boost Mixer", NULL, "RAUX"},
++	{"Right Boost Mixer", NULL, "Right Capture PGA"},
++	{"Right Boost Mixer", NULL, "R2"},
++
++	{"Left ADC", NULL, "Left Boost Mixer"},
++
++	{"Left Boost Mixer", NULL, "LAUX"},
++	{"Left Boost Mixer", NULL, "Left Capture PGA"},
++	{"Left Boost Mixer", NULL, "L2"},
++
++	/* Input PGA */
++	{"Right Capture PGA", NULL, "Right Input Mixer"},
++	{"Left Capture PGA", NULL, "Left Input Mixer"},
++
++	/*enable microphone power*/
++	{"Right Capture PGA", NULL, "Mic Bias"},
++	{"Left Capture PGA", NULL, "Mic Bias"},
++
++	{"Right Input Mixer", "R2 Switch", "R2"},
++	{"Right Input Mixer", "MicN Switch", "RMICN"},
++	{"Right Input Mixer", "MicP Switch", "RMICP"},
++
++	{"Left Input Mixer", "L2 Switch", "L2"},
++	{"Left Input Mixer", "MicN Switch", "LMICN"},
++	{"Left Input Mixer", "MicP Switch", "LMICP"},
++};
++
++static int nau8822_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
++				 unsigned int freq, int dir)
++{
++	struct snd_soc_codec *codec = codec_dai->codec;
++	struct nau8822_priv *nau8822 = snd_soc_codec_get_drvdata(codec);
++	ENTER();
++
++		nau8822->div_id = clk_id;
++		nau8822->sysclk = freq;
++		dev_dbg(nau8822->dev, "master sysclk %dHz, source %s\n",freq,
++			clk_id == NAU8822_CLK_PLL ? "PLL" : "MCLK");
++
++	return 0;
++}
++
++static int nau8822_calc_pll(unsigned int pll_in, unsigned int fs,
++				struct nau8822_pll *pll_param)
++{
++	u64 f2, f2_max, pll_ratio;
++	int i, scal_sel;
++	ENTER();
++
++	if (pll_in > NAU_PLL_REF_MAX || pll_in < NAU_PLL_REF_MIN)
++		return -EINVAL;
++	f2_max = 0;
++	scal_sel = ARRAY_SIZE(nau8822_mclk_scaler);
++
++	for (i = 0; i < scal_sel; i++) {
++		f2 = 256 * fs * 4 * nau8822_mclk_scaler[i] / 10;
++
++	if (f2 > NAU_PLL_FREQ_MIN && f2 < NAU_PLL_FREQ_MAX && f2_max < f2) {
++			f2_max = f2;
++			scal_sel = i;
++		}
++	}
++
++		if (ARRAY_SIZE(nau8822_mclk_scaler) == scal_sel){
++			return -EINVAL;
++		}
++
++	/* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional
++	 * input; round up the 24+4bit.
++	 */
++	pll_ratio = div_u64(f2 << 28, pll_in);
++	pll_param->pre_factor = 0;
++	if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN)
++	{
++		pll_ratio <<= 1;
++		pll_param->pre_factor = 1;
++	}
++	pll_param->pll_int = (pll_ratio >> 28) & 0xF;
++	pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4);
++
++	return 0;
++}
++
++static int nau8822_config_clkdiv(struct nau8822_priv *nau8822, int div,
++				int rate)
++{
++	struct regmap *regmap = nau8822->regmap;
++	struct nau8822_pll *pll = &nau8822->pll;
++	int i, sclk, imclk;
++	ENTER();
++
++	switch (nau8822->div_id) {
++	case NAU8822_CLK_MCLK:
++		/* Configure the master clock prescaler div to make system
++		 * clock to approximate the internal master clock (IMCLK);
++		 * and large or equal to IMCLK.
++		 */
++		div = 0;
++//		imclk = rate * 256;
++		imclk = rate * 256 * 2;
++		for (i = 1; i < ARRAY_SIZE(nau8822_mclk_scaler); i++) {
++			sclk = (nau8822->sysclk * 10) /	nau8822_mclk_scaler[i];
++			if (sclk < imclk)
++				break;
++			div = i;
++		}
++		dev_dbg(nau8822->dev,"master clock prescaler %x for fs %d\n", div,
++			rate);
++
++		/* master clock from MCLK and disable PLL */
++		regmap_update_bits(regmap, NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
++			(div << NAU8822_MCLKSEL_SFT));
++		regmap_update_bits(regmap, NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK,
++			NAU8822_CLKM_MCLK);
++		break;
++
++	case NAU8822_CLK_PLL:
++		/* master clock from PLL and enable PLL */
++		if (pll->mclk_scaler != div) {
++			dev_err(nau8822->dev, "master clock prescaler not meet PLL parameters\n");
++			return -EINVAL;
++		}
++		regmap_update_bits(regmap, NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
++			(div << NAU8822_MCLKSEL_SFT));
++		regmap_update_bits(regmap, NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK,
++			NAU8822_CLKM_PLL);
++		break;
++
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int nau8822_set_pll(struct snd_soc_dai *codec_dai, int pll_id,
++				int source,unsigned int freq_in, unsigned int freq_out)
++{
++	struct snd_soc_codec *codec = codec_dai->codec;
++	struct nau8822_priv *nau8822 = snd_soc_codec_get_drvdata(codec);
++	struct regmap *map = nau8822->regmap;
++	struct nau8822_pll *pll_param = &nau8822->pll;
++	int ret, fs;
++	ENTER();
++
++	fs = freq_out / 256;
++
++	ret = nau8822_calc_pll(freq_in, fs, pll_param);
++	if (ret < 0) {
++		dev_err(codec->dev, "Unsupported input clock %d\n", freq_in);
++		return ret;
++	}
++
++	dev_info(nau8822->dev, "pll_int=%x pll_frac=%x mclk_scaler=%x\
++		pre_factor=%x\n",pll_param->pll_int, pll_param->pll_frac,
++		pll_param->mclk_scaler, pll_param->pre_factor);
++
++	regmap_update_bits(map, NAU8822_REG_PLL_N,NAU8822_PLLMCLK_DIV2 |
++		NAU8822_PLLN_MASK,(pll_param->pre_factor ? NAU8822_PLLMCLK_DIV2 : 0) |
++		pll_param->pll_int);
++	regmap_write(map, NAU8822_REG_PLL_K1,(pll_param->pll_frac >>
++		NAU8822_PLLK1_SFT) & NAU8822_PLLK1_MASK);
++	regmap_write(map, NAU8822_REG_PLL_K2,(pll_param->pll_frac >>
++		NAU8822_PLLK2_SFT) & NAU8822_PLLK2_MASK);
++	regmap_write(map, NAU8822_REG_PLL_K3, pll_param->pll_frac &
++		NAU8822_PLLK3_MASK);
++	regmap_update_bits(map, NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
++		pll_param->mclk_scaler << NAU8822_MCLKSEL_SFT);
++	regmap_update_bits(map, NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK,
++		NAU8822_CLKM_PLL);
++
++	return 0;
++}
++
++static int nau8822_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
++{
++	struct snd_soc_codec *codec = codec_dai->codec;
++	struct nau8822_priv *nau8822 = snd_soc_codec_get_drvdata(codec);
++	u16 ctrl1_val = 0, ctrl2_val = 0;
++
++	dev_dbg(codec->dev, "%s\n", __func__);
++
++	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++	case SND_SOC_DAIFMT_CBM_CFM:
++		ctrl2_val |= 1;
++		break;
++	case SND_SOC_DAIFMT_CBS_CFS:
++		ctrl2_val &= ~1;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_I2S:
++		ctrl1_val |= 0x10;
++		break;
++	case SND_SOC_DAIFMT_RIGHT_J:
++		break;
++	case SND_SOC_DAIFMT_LEFT_J:
++		ctrl1_val |= 0x8;
++		break;
++	case SND_SOC_DAIFMT_DSP_A:
++		ctrl1_val |= 0x18;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++	case SND_SOC_DAIFMT_NB_NF:
++		break;
++	case SND_SOC_DAIFMT_IB_IF:
++		ctrl1_val |= 0x180;
++		break;
++	case SND_SOC_DAIFMT_IB_NF:
++		ctrl1_val |= 0x100;
++		break;
++	case SND_SOC_DAIFMT_NB_IF:
++		ctrl1_val |= 0x80;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(nau8822->regmap, NAU8822_REG_AUDIO_INTERFACE,
++		NAU8822_AIFMT_MASK | NAU8822_LRP_MASK | NAU8822_BCLKP_MASK, ctrl1_val);
++	regmap_update_bits(nau8822->regmap, NAU8822_REG_CLOCKING,
++		NAU8822_CLKIOEN_MASK, ctrl2_val);
++
++	return 0;
++}
++
++static int nau8822_hw_params(struct snd_pcm_substream *substream,
++			    struct snd_pcm_hw_params *params,
++			    struct snd_soc_dai *dai)
++{
++	int val_len = 0, val_rate = 0;
++	struct snd_soc_codec *codec = dai->codec;
++	struct nau8822_priv *nau8822 = snd_soc_codec_get_drvdata(codec);
++	ENTER();
++
++	switch (params_format(params)) {
++	case SNDRV_PCM_FORMAT_S16_LE:
++		break;
++	case SNDRV_PCM_FORMAT_S20_3LE:
++		val_len |= NAU8822_WLEN_20;
++		break;
++	case SNDRV_PCM_FORMAT_S24_LE:
++		val_len |= NAU8822_WLEN_24;
++		break;
++	case SNDRV_PCM_FORMAT_S32_LE:
++		val_len |= NAU8822_WLEN_32;
++		break;
++	}
++
++	switch (params_rate(params)) {
++	case 8000:
++		val_rate |= NAU8822_SMPLR_8K;
++		break;
++	case 11025:
++		val_rate |= NAU8822_SMPLR_12K;
++		break;
++	case 16000:
++		val_rate |= NAU8822_SMPLR_16K;
++		break;
++	case 22050:
++		val_rate |= NAU8822_SMPLR_24K;
++		break;
++	case 32000:
++		val_rate |= NAU8822_SMPLR_32K;
++		break;
++	case 44100:
++	case 48000:
++		break;
++	}
++
++	regmap_update_bits(nau8822->regmap, NAU8822_REG_AUDIO_INTERFACE,
++		NAU8822_WLEN_MASK, val_len);
++	regmap_update_bits(nau8822->regmap, NAU8822_REG_ADDITIONAL_CONTROL,
++		NAU8822_SMPLR_MASK, val_rate);
++
++	/* If the master clock is from MCLK, provide the runtime FS for driver
++	 * to get the master clock prescaler configuration.
++	 */
++	if (nau8822->div_id == NAU8822_CLK_MCLK)
++		nau8822_config_clkdiv(nau8822, 0, params_rate(params));
++
++	return 0;
++}
++
++static int nau8822_mute(struct snd_soc_dai *dai, int mute)
++{
++	struct snd_soc_codec *codec = dai->codec;
++	struct nau8822_priv *nau8822 = snd_soc_codec_get_drvdata(codec);
++
++	dev_dbg(codec->dev, "%s: %d\n", __func__, mute);
++
++	if (mute)
++		regmap_update_bits(nau8822->regmap, NAU8822_REG_DAC_CONTROL, 0x40, 0x40);
++	else
++		regmap_update_bits(nau8822->regmap, NAU8822_REG_DAC_CONTROL, 0x40, 0);
++
++	return 0;
++}
++
++static int nau8822_set_bias_level(struct snd_soc_codec *codec,
++				 enum snd_soc_bias_level level)
++{
++	struct nau8822_priv *nau8822 = snd_soc_codec_get_drvdata(codec);
++	struct regmap *map = nau8822->regmap;
++	MYDBG("bias_leve=%x", level);
++	switch (level) {
++	case SND_SOC_BIAS_ON:
++	case SND_SOC_BIAS_PREPARE:
++		regmap_update_bits(map, NAU8822_REG_POWER_MANAGEMENT_1,
++			NAU8822_REFIMP_MASK, NAU8822_REFIMP_80K);
++		break;
++	case SND_SOC_BIAS_STANDBY:
++		regmap_update_bits(map, NAU8822_REG_POWER_MANAGEMENT_1,
++			NAU8822_IOBUF_EN | NAU8822_ABIAS_EN, NAU8822_IOBUF_EN | NAU8822_ABIAS_EN);
++
++		if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
++			regmap_update_bits(map, NAU8822_REG_POWER_MANAGEMENT_1,
++				NAU8822_REFIMP_MASK, NAU8822_REFIMP_3K);
++			mdelay(100);
++		}
++		regmap_update_bits(map, NAU8822_REG_POWER_MANAGEMENT_1,
++			NAU8822_REFIMP_MASK, NAU8822_REFIMP_300K);
++		break;
++	case SND_SOC_BIAS_OFF:
++		regmap_write(map, NAU8822_REG_POWER_MANAGEMENT_1, 0);
++		regmap_write(map, NAU8822_REG_POWER_MANAGEMENT_2, 0);
++		regmap_write(map, NAU8822_REG_POWER_MANAGEMENT_3, 0);
++		break;
++	}
++
++	return 0;
++}
++
++#define NAU8822_RATES (SNDRV_PCM_RATE_8000_48000)
++
++#define NAU8822_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
++	SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
++
++static const struct snd_soc_dai_ops nau8822_dai_ops = {
++	.hw_params	= nau8822_hw_params,
++	.digital_mute	= nau8822_mute,
++	.set_fmt	= nau8822_set_dai_fmt,
++	.set_sysclk	= nau8822_set_dai_sysclk,
++	.set_pll	= nau8822_set_pll,
++};
++
++static struct snd_soc_dai_driver nau8822_dai = {
++	.name = "nau8822-hifi",
++	.playback = {
++		.stream_name = "Playback",
++		.channels_min = 1,
++		.channels_max = 2,
++		.rates = NAU8822_RATES,
++		.formats = NAU8822_FORMATS,
++	},
++	.capture = {
++		.stream_name = "Capture",
++		.channels_min = 1,
++		.channels_max = 2,
++		.rates = NAU8822_RATES,
++		.formats = NAU8822_FORMATS,
++	},
++	.ops = &nau8822_dai_ops,
++	.symmetric_rates = 1,
++};
++
++static int nau8822_suspend(struct snd_soc_codec *codec)
++{
++	struct nau8822_priv *nau8822 = snd_soc_codec_get_drvdata(codec);
++
++	nau8822_set_bias_level(codec, SND_SOC_BIAS_OFF);
++	regmap_write(nau8822->regmap, NAU8822_REG_POWER_MANAGEMENT_1, 0);
++
++	regcache_mark_dirty(nau8822->regmap);
++	gpiod_direction_output(nau8822->pwdn_gpiod, 0);
++
++	return 0;
++}
++
++static int nau8822_resume(struct snd_soc_codec *codec)
++{
++	struct nau8822_priv *nau8822 = snd_soc_codec_get_drvdata(codec);
++	gpiod_direction_output(nau8822->pwdn_gpiod, 1);
++
++	regcache_sync(nau8822->regmap);
++
++	nau8822_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
++
++	return 0;
++}
++
++/*
++ * These registers contain an "update" bit - bit 8. This means, for example,
++ * that one can write new DAC digital volume for both channels, but only when
++ * the update bit is set, will also the volume be updated - simultaneously for
++ * both channels.
++ */
++static const int update_reg[] = {
++	NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME,
++	NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME,
++	NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME,
++	NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME,
++	NAU8822_REG_LEFT_INP_PGA_CONTROL,
++	NAU8822_REG_RIGHT_INP_PGA_CONTROL,
++	NAU8822_REG_LHP_VOLUME,
++	NAU8822_REG_RHP_VOLUME,
++	NAU8822_REG_LSPKOUT_VOLUME,
++	NAU8822_REG_RSPKOUT_VOLUME,
++};
++
++static int nau8822_probe(struct snd_soc_codec *codec)
++{
++	struct nau8822_priv *nau8822 = snd_soc_codec_get_drvdata(codec);
++	int i;
++
++	/*
++	 * Set the update bit in all registers, that have one. This way all
++	 * writes to those registers will also cause the update bit to be
++	 * written.
++	 */
++	for (i = 0; i < ARRAY_SIZE(update_reg); i++)
++		regmap_update_bits(nau8822->regmap, update_reg[i], 0x100, 0x100);
++
++	nau8822_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
++
++	return 0;
++}
++
++static int nau8822_remove(struct snd_soc_codec *codec)
++{
++	nau8822_set_bias_level(codec, SND_SOC_BIAS_OFF);
++
++	return 0;
++}
++
++static struct regmap *nau8822_get_regmap(struct device *dev)
++{
++	struct nau8822_priv *nau8822 = dev_get_drvdata(dev);
++	ENTER();
++	return nau8822->regmap;
++}
++
++static struct snd_soc_codec_driver soc_codec_dev_nau8822 = {
++	.probe =	nau8822_probe,
++	.get_regmap	   = nau8822_get_regmap,
++	.set_bias_level = nau8822_set_bias_level,
++
++	.remove =	nau8822_remove,
++	.suspend =	nau8822_suspend,
++	.resume =	nau8822_resume,
++
++	.controls = nau8822_snd_controls,
++	.num_controls = ARRAY_SIZE(nau8822_snd_controls),
++	.dapm_widgets = nau8822_dapm_widgets,
++	.num_dapm_widgets = ARRAY_SIZE(nau8822_dapm_widgets),
++	.dapm_routes = nau8822_dapm_routes,
++	.num_dapm_routes = ARRAY_SIZE(nau8822_dapm_routes),
++};
++
++static const struct regmap_config nau8822_regmap_config = {
++	.reg_bits = 7,
++	.val_bits = 9,
++
++	//.reg_read = nau8822_reg_read2,
++	.max_register = NAU8822_REG_MAX_REGISTER,
++	.volatile_reg = nau8822_volatile,
++
++	.readable_reg = nau8822_readable_reg,
++	.writeable_reg = nau8822_writeable_reg,
++
++	.cache_type = REGCACHE_RBTREE,
++	.reg_defaults = nau8822_reg_defaults,
++	.num_reg_defaults = ARRAY_SIZE(nau8822_reg_defaults),
++};
++
++static int nau8822_i2c_probe(struct i2c_client *i2c,
++			    const struct i2c_device_id *id)
++{
++	struct device *dev = &i2c->dev;
++	struct nau8822_priv *nau8822 = dev_get_platdata(dev);
++	int ret;
++	int value;
++	unsigned int flags;
++	ENTER();
++	if(!nau8822){
++		nau8822 = devm_kzalloc(dev, sizeof(struct nau8822_priv),GFP_KERNEL);
++		if(nau8822 == NULL)
++			return -ENOMEM;
++	}
++	nau8822->pwdn_gpiod = devm_gpiod_get_optional(&i2c->dev, "ingenic,pwdn",
++						     GPIOD_OUT_HIGH);
++	if (IS_ERR(nau8822->pwdn_gpiod))
++		return PTR_ERR(nau8822->pwdn_gpiod);
++
++	nau8822->i2c = i2c;
++	i2c_set_clientdata(i2c, nau8822);
++
++	ret = nau8822_reg_read(nau8822, NAU8822_REG_DEVICE_ID, &value);
++	dev_info(&i2c->dev, "NAU8822_REG_DEVICE_ID=%x , ret=%x\n", value, ret);
++
++
++	//nau8822->regmap = devm_regmap_init(dev, NULL, i2c, &nau8822_regmap_config);
++	nau8822->regmap = devm_regmap_init_i2c(i2c, &nau8822_regmap_config);
++	if (IS_ERR(nau8822->regmap)) {
++		ret = PTR_ERR(nau8822->regmap);
++		dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
++		return ret;
++	}
++
++	nau8822->dev = dev;
++#if 0
++	regcache_cache_bypass(nau8822->regmap, true);
++	MYDBG("nau8822=%p\n", nau8822);
++	MYDBG("nau8822->regmap=%p\n", nau8822->regmap);
++	ret=0;
++	ret = regmap_read(nau8822->regmap, NAU8822_REG_DEVICE_ID, &value);
++	MYDBG("NAU8822_REG_DEVICE_ID=%x , ret=%x\n", value, ret);
++	ret=0;
++	ret = regmap_read(nau8822->regmap, NAU8822_REG_DEVICE_REVISION, &value);
++	MYDBG("NAU8822_REG_DEVICE_REVISION=%x, ret=%x\n", value, ret);
++	regcache_cache_bypass(nau8822->regmap, false);
++
++
++	MYDBG("nau8822->regmap=%p\n", nau8822->regmap);
++	ret=0;
++	ret = regmap_read(nau8822->regmap, NAU8822_REG_DEVICE_ID, &value);
++	MYDBG("NAU8822_REG_DEVICE_ID=%x , ret=%x\n", value, ret);
++	ret=0;
++	ret = regmap_read(nau8822->regmap, NAU8822_REG_DEVICE_REVISION, &value);
++	MYDBG("NAU8822_REG_DEVICE_REVISION=%x, ret=%x\n", value, ret);
++	regcache_cache_bypass(nau8822->regmap, false);
++#endif
++
++	/* Reset the codec */
++	ret = regmap_write(nau8822->regmap, NAU8822_REG_RESET, 0x00);
++	if (ret != 0) {
++		dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
++		return ret;
++	}
++
++	ret = snd_soc_register_codec(dev,&soc_codec_dev_nau8822, &nau8822_dai, 1);
++	if (ret != 0) {
++		dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
++		return ret;
++	}
++
++	return 0;
++}
++
++static int nau8822_i2c_remove(struct i2c_client *client)
++{
++	snd_soc_unregister_codec(&client->dev);
++
++	return 0;
++}
++
++static const struct i2c_device_id nau8822_i2c_id[] = {
++	{ "nau8822", 0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, nau8822_i2c_id);
++
++#ifdef CONFIG_OF
++static const struct of_device_id nau8822_of_match[] = {
++	{ .compatible = "nuvoton,nau8822", },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, nau8822_of_match);
++#endif
++
++static struct i2c_driver nau8822_i2c_driver = {
++	.driver = {
++		.name = "nau8822",
++		.of_match_table = of_match_ptr(nau8822_of_match),
++	},
++	.probe =    nau8822_i2c_probe,
++	.remove =   nau8822_i2c_remove,
++	.id_table = nau8822_i2c_id,
++};
++module_i2c_driver(nau8822_i2c_driver);
++
++MODULE_DESCRIPTION("ASoC NAU8822 codec driver");
++MODULE_AUTHOR("Nuvoton CTLIN <ctlin0@nuvoton.com>");
++MODULE_LICENSE("GPL v2");
+diff --git a/module_drivers/sound/soc/ingenic/ecodec/nau8822.h b/module_drivers/sound/soc/ingenic/ecodec/nau8822.h
+new file mode 100644
+index 000000000..b61784ce6
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/ecodec/nau8822.h
+@@ -0,0 +1,161 @@
++/*
++ * nau8822.h  --  NAU8822 Soc Audio Codec driver
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __NAU8822_H__
++#define __NAU8822_H__
++
++/*
++ * Register values.
++ */
++#define NAU8822_REG_RESET						0x00
++#define NAU8822_REG_POWER_MANAGEMENT_1			0x01
++#define NAU8822_REG_POWER_MANAGEMENT_2			0x02
++#define NAU8822_REG_POWER_MANAGEMENT_3			0x03
++#define NAU8822_REG_AUDIO_INTERFACE				0x04
++#define NAU8822_REG_COMPANDING_CONTROL			0x05
++#define NAU8822_REG_CLOCKING					0x06
++#define NAU8822_REG_ADDITIONAL_CONTROL			0x07
++#define NAU8822_REG_GPIO_CONTROL				0x08
++#define NAU8822_REG_JACK_DETECT_CONTROL_1		0x09
++#define NAU8822_REG_DAC_CONTROL					0x0A
++#define NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME		0x0B
++#define NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME	0x0C
++#define NAU8822_REG_JACK_DETECT_CONTROL_2		0x0D
++#define NAU8822_REG_ADC_CONTROL					0x0E
++#define NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME		0x0F
++#define NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME	0x10
++#define NAU8822_REG_EQ1							0x12
++#define NAU8822_REG_EQ2							0x13
++#define NAU8822_REG_EQ3							0x14
++#define NAU8822_REG_EQ4							0x15
++#define NAU8822_REG_EQ5							0x16
++#define NAU8822_REG_DAC_LIMITER_1				0x18
++#define NAU8822_REG_DAC_LIMITER_2				0x19
++#define NAU8822_REG_NOTCH_FILTER_1				0x1B
++#define NAU8822_REG_NOTCH_FILTER_2				0x1C
++#define NAU8822_REG_NOTCH_FILTER_3				0x1D
++#define NAU8822_REG_NOTCH_FILTER_4				0x1E
++#define NAU8822_REG_ALC_CONTROL_1				0x20
++#define NAU8822_REG_ALC_CONTROL_2				0x21
++#define NAU8822_REG_ALC_CONTROL_3				0x22
++#define NAU8822_REG_NOISE_GATE					0x23
++#define NAU8822_REG_PLL_N						0x24
++#define NAU8822_REG_PLL_K1						0x25
++#define NAU8822_REG_PLL_K2						0x26
++#define NAU8822_REG_PLL_K3						0x27
++#define NAU8822_REG_3D_CONTROL					0x29
++#define NAU8822_REG_RIGHT_SPEAKER_CONTROL		0x2B
++#define NAU8822_REG_INPUT_CONTROL				0x2C
++#define NAU8822_REG_LEFT_INP_PGA_CONTROL		0x2D
++#define NAU8822_REG_RIGHT_INP_PGA_CONTROL		0x2E
++#define NAU8822_REG_LEFT_ADC_BOOST_CONTROL		0x2F
++#define NAU8822_REG_RIGHT_ADC_BOOST_CONTROL		0x30
++#define NAU8822_REG_OUTPUT_CONTROL				0x31
++#define NAU8822_REG_LEFT_MIXER_CONTROL			0x32
++#define NAU8822_REG_RIGHT_MIXER_CONTROL			0x33
++#define NAU8822_REG_LHP_VOLUME					0x34
++#define NAU8822_REG_RHP_VOLUME					0x35
++#define NAU8822_REG_LSPKOUT_VOLUME				0x36
++#define NAU8822_REG_RSPKOUT_VOLUME				0x37
++#define NAU8822_REG_AUX2_MIXER					0x38
++#define NAU8822_REG_AUX1_MIXER					0x39
++#define NAU8822_REG_POWER_MANAGEMENT_4			0x3A
++#define NAU8822_REG_LEFT_TIME_SLOT				0x3B
++#define NAU8822_REG_MISC						0x3C
++#define NAU8822_REG_RIGHT_TIME_SLOT				0x3D
++#define NAU8822_REG_DEVICE_REVISION				0x3E
++#define NAU8822_REG_DEVICE_ID					0x3F
++#define NAU8822_REG_DAC_DITHER					0x41
++#define NAU8822_REG_ALC_ENHANCE_1				0x46
++#define NAU8822_REG_ALC_ENHANCE_2				0x47
++#define NAU8822_REG_192KHZ_SAMPLING				0x48
++#define NAU8822_REG_MISC_CONTROL				0x49
++#define NAU8822_REG_INPUT_TIEOFF				0x4A
++#define NAU8822_REG_POWER_REDUCTION				0x4B
++#define NAU8822_REG_AGC_PEAK2PEAK				0x4C
++#define NAU8822_REG_AGC_PEAK_DETECT				0x4D
++#define NAU8822_REG_AUTOMUTE_CONTROL			0x4E
++#define NAU8822_REG_OUTPUT_TIEOFF				0x4F
++#define NAU8822_REG_MAX_REGISTER				NAU8822_REG_OUTPUT_TIEOFF
++
++/* NAU8822_REG_POWER_MANAGEMENT_1 (0x1) */
++#define NAU8822_REFIMP_MASK			0x3
++#define NAU8822_REFIMP_80K			0x1
++#define NAU8822_REFIMP_300K			0x2
++#define NAU8822_REFIMP_3K			0x3
++#define NAU8822_IOBUF_EN			(0x1 << 2)
++#define NAU8822_ABIAS_EN			(0x1 << 3)
++
++/* NAU8822_REG_AUDIO_INTERFACE (0x4) */
++#define NAU8822_AIFMT_MASK			(0x3 << 3)
++#define NAU8822_WLEN_MASK			(0x3 << 5)
++#define NAU8822_WLEN_20				(0x1 << 5)
++#define NAU8822_WLEN_24				(0x2 << 5)
++#define NAU8822_WLEN_32				(0x3 << 5)
++#define NAU8822_LRP_MASK			(0x1 << 7)
++#define NAU8822_BCLKP_MASK			(0x1 << 8)
++
++/* NAU8822_REG_CLOCKING (0x6) */
++#define NAU8822_CLKIOEN_MASK		0x1
++#define NAU8822_MCLKSEL_SFT			5
++#define NAU8822_MCLKSEL_MASK		(0x7 << 5)
++#define NAU8822_BCLKSEL_SFT			2
++#define NAU8822_BCLKSEL_MASK		(0x7 << 2)
++#define NAU8822_CLKM_MASK			(0x1 << 8)
++#define NAU8822_CLKM_MCLK			(0x0 << 8)
++#define NAU8822_CLKM_PLL			(0x1 << 8)
++
++/* NAU8822_REG_ADDITIONAL_CONTROL (0x08) */
++#define NAU8822_SMPLR_SFT			1
++#define NAU8822_SMPLR_MASK			(0x7 << 1)
++#define NAU8822_SMPLR_48K			(0x0 << 1)
++#define NAU8822_SMPLR_32K			(0x1 << 1)
++#define NAU8822_SMPLR_24K			(0x2 << 1)
++#define NAU8822_SMPLR_16K			(0x3 << 1)
++#define NAU8822_SMPLR_12K			(0x4 << 1)
++#define NAU8822_SMPLR_8K			(0x5 << 1)
++
++/* NAU8822_REG_PLL_N (0x24) */
++#define NAU8822_PLLMCLK_DIV2		(0x1 << 4)
++#define NAU8822_PLLN_MASK			0xF
++
++#define NAU8822_PLLK1_SFT			18
++#define NAU8822_PLLK1_MASK			0x3F
++
++/* NAU8822_REG_PLL_K2 (0x26) */
++#define NAU8822_PLLK2_SFT			9
++#define NAU8822_PLLK2_MASK			0x1FF
++
++/* NAU8822_REG_PLL_K3 (0x27) */
++#define NAU8822_PLLK3_MASK			0x1FF
++
++/* System Clock Source */
++enum {
++	NAU8822_CLK_MCLK,
++	NAU8822_CLK_PLL,
++};
++
++struct nau8822_pll {
++	int pre_factor;
++	int mclk_scaler;
++	int pll_frac;
++	int pll_int;
++};
++
++/* codec private data */
++struct nau8822_priv {
++	struct device *dev;
++	struct regmap *regmap;
++	int mclk_idx;
++	struct nau8822_pll pll;
++	int sysclk;
++	int div_id;
++	struct i2c_client *i2c;
++};
++
++#endif	/* __NAU8822_H__ */
+diff --git a/module_drivers/sound/soc/ingenic/ecodec/wm8594.c b/module_drivers/sound/soc/ingenic/ecodec/wm8594.c
+new file mode 100644
+index 000000000..3bff1c4af
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/ecodec/wm8594.c
+@@ -0,0 +1,1177 @@
++/*
++ *  sound/soc/ingenic/ecodec/wm8594.c
++ *	ALSA SoC driver for wm8594 ADC
++ *
++ *  Copyright 2017 Ingenic Semiconductor Co.,Ltd
++ *	wqshao <wangquan.shao@ingenic.com>
++ *
++ *  This program is free software; you can redistribute  it and/or modify it
++ *  under  the terms of  the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the  License, or (at your
++ *  option) any later version.
++ *
++ *  Only for x2000 FPGA Audio test.
++ */
++#include <linux/delay.h>
++#include <linux/gpio/consumer.h>
++#include <linux/i2c.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/regmap.h>
++#include <linux/of_device.h>
++#include <linux/of_gpio.h>
++#include <linux/slab.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++#include <sound/tlv.h>
++
++#include "wm8594.h"
++
++#define CODEC_NAME	"wm8594"
++
++#define wm8594_reset(c) wm8594_write(c, WM8594_RESET, 0)
++
++struct wm8594_priv {
++	struct regmap *regmap;
++	bool powered;
++	struct gpio_desc *reset_gpiod;
++	struct gpio_desc *mute_gpiod;
++	struct gpio_desc *pwdn_gpiod;
++};
++
++#define SND_SOC_WM8594_SHARE_CLOCK_MASK		0xf0000
++#define SND_SOC_WM8594_SHARE_CLOCK_PLAYBACK	(1 << 16)
++#define SND_SOC_WM8594_SHARE_CLOCK_RECORD	(2 << 16)
++
++static const struct reg_default wm8594_reg_defaults[] = {
++	{ 0x00, 0x8594 },
++	{ 0x01, 0x0004 },
++	{ 0x02, 0x008a },
++	{ 0x03, 0x0000 },
++	{ 0x04, 0x0000 },
++	{ 0x05, 0x00c8 },
++	{ 0x06, 0x00c8 },
++	{ 0x07, 0x008a },
++	{ 0x08, 0x0000 },
++	{ 0x09, 0x0000 },
++	{ 0x0a, 0x00c8 },
++	{ 0x0b, 0x00c8 },
++	{ 0x0c, 0x0000 },
++	{ 0x0d, 0x200a },
++	{ 0x0e, 0x0000 },
++	{ 0x0f, 0x0000 },
++	{ 0x10, 0x00c3 },
++	{ 0x11, 0x00c3 },
++	{ 0x13, 0x000c },
++	{ 0x14, 0x000c },
++	{ 0x15, 0x000c },
++	{ 0x16, 0x000c },
++	{ 0x17, 0x000c },
++	{ 0x18, 0x000c },
++	{ 0x19, 0x0003 },
++	{ 0x1a, 0x007e },
++	{ 0x1b, 0x0048 },
++	{ 0x1c, 0x0000 },
++	{ 0x1d, 0x0000 },
++	{ 0x1e, 0x0008 },
++	{ 0x1f, 0x0000 },
++	{ 0x20, 0x0088 },
++	{ 0x21, 0x0163 },
++	{ 0x22, 0x0040 },
++	{ 0x23, 0x0010 },
++	{ 0x24, 0x0002 },
++};
++
++static const struct reg_default wm8594_reg_init[] = {
++	{WM8594_DAC1_CTRL1,	0x008e}, /*
++					  * DAC1 cross enable
++					  * 32 bits i2s format
++					  */
++	{WM8594_DAC1_CTRL2,	0x001b}, /*
++					  * MCLK = 256 * Fs
++					  * BLCK = 64  * Fs
++					  */
++	{WM8594_ADC_CTRL1,	0x200a}, /*
++					  * ADC cross enable
++					  * 32 bits i2s format
++					  */
++	{WM8594_DAC2_CTRL1,	0x008e}, /*
++					  * DAC2 cross enable
++					  * 32 bits i2s format
++					  */
++	{WM8594_DAC2_CTRL2,	0x001b}, /*
++					  * MCLK = 256 * Fs
++					  * BLCK = 64  * Fs
++					  */
++	{WM8594_INPUT_CTRL1,	0x09a9},
++	{WM8594_INPUT_CTRL2,	0x0a9a}, /*
++					  * connect PGA1 and PGA2
++					  * to DAC1
++					  */
++	{WM8594_INPUT_CTRL3,	0x0480}, /* connect ADC to VIN1 */
++};
++
++
++static unsigned int wm8594_read(struct snd_soc_component *component,
++			unsigned int reg)
++{
++	return snd_soc_component_read(component, reg);
++}
++
++static int wm8594_write(struct snd_soc_component *component,
++			unsigned int reg,
++			unsigned int value)
++{
++	int ret = 0;
++	ret = snd_soc_component_update_bits(component, reg, 0xffff, value);
++	if (ret >= 0) {
++		dev_dbg(component->dev, "%s: reg = 0x%x ; value = 0x%x (change %x)success\n",
++				__func__, reg, value, ret);
++		ret = 0;
++	} else {
++		dev_err(component->dev, "%s: reg = 0x%x ; value = 0x%x error\n",
++				__func__, reg, value);
++		ret = -EIO;
++	}
++
++	return ret;
++}
++
++static int wm8594_vol_update(struct snd_kcontrol *kcontrol,
++			     struct snd_ctl_elem_value *ucontrol)
++{
++	struct soc_mixer_control *mc =
++		(struct soc_mixer_control *)kcontrol->private_value;
++	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++/*	struct snd_soc_codec *codec = component->codec;*/
++	unsigned int reg = mc->reg;
++	unsigned int reg2 = mc->rreg;
++	unsigned int shift = mc->shift;
++	unsigned int rshift = mc->rshift;
++	int max = mc->max;
++	unsigned int mask = (1 << fls(max)) - 1;
++	unsigned int invert = mc->invert;
++	int err;
++	bool type_2r = 0;
++	unsigned int val2 = 0;
++	unsigned int val, val_mask;
++
++	val = (ucontrol->value.integer.value[0] & mask);
++	if (invert)
++		val = max - val;
++	val_mask = mask << shift;
++	val = val << shift;
++	if (snd_soc_volsw_is_stereo(mc)) {
++		val2 = (ucontrol->value.integer.value[1] & mask);
++		if (invert)
++			val2 = max - val2;
++		if (reg == reg2) {
++			val_mask |= mask << rshift;
++			val |= val2 << rshift;
++		} else {
++			val2 = val2 << shift;
++			type_2r = 1;
++		}
++	}
++
++	err = snd_soc_component_update_bits(component,
++			reg,
++			val_mask | 0x100,
++			val | 0x100);
++	if (err < 0)
++		return err;
++
++	if (type_2r)
++		err = snd_soc_component_update_bits(component,
++				reg2,
++				val_mask | 0x100,
++				val2 | 0x100);
++
++	return err;
++}
++
++
++static int wm8594_adc_input_get_switch(struct snd_kcontrol *kcontrol,
++				       struct snd_ctl_elem_value *ucontrol)
++{
++
++	struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
++	struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
++	int ret = 0;
++	u16 sel = 0;
++	sel = snd_soc_component_read(component, WM8594_INPUT_CTRL3);
++	if (sel < 0)
++		return -EIO;
++	switch (sel & 0xf) {
++	case 0x0:
++		/* VIN1L */
++		ucontrol->value.enumerated.item[0] = 0;
++		break;
++	case 0x1:
++		/* VIN2L */
++		ucontrol->value.enumerated.item[0] = 1;
++		break;
++	case 0x2:
++		/* VIN3L */
++		ucontrol->value.enumerated.item[0] = 2;
++		break;
++	case 0x3:
++		/* VIN4L */
++		ucontrol->value.enumerated.item[0] = 3;
++		break;
++	case 0x4:
++		/* VIN5L */
++		ucontrol->value.enumerated.item[0] = 4;
++		break;
++	default:
++		ret = -EINVAL;
++		dev_err(component->dev, "%s: unexpected control value\n", __func__);
++		break;
++	};
++	return ret;
++}
++
++static int wm8594_adc_input_set_switch(struct snd_kcontrol *kcontrol,
++				       struct snd_ctl_elem_value *ucontrol)
++{
++
++	struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
++	struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
++	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
++	unsigned int *item = ucontrol->value.enumerated.item;
++	int ret = 0;
++	u16 sel = 0;
++
++	switch (item[0]) {
++	case 0:
++		/* VIN1 */
++		sel = 0x80;
++		break;
++	case 1:
++		/* VIN2 */
++		sel = 0x91;
++		break;
++	case 2:
++		/* VIN3 */
++		sel = 0xa2;
++		break;
++	case 3:
++		/* VIN4 */
++		sel = 0xb3;
++		break;
++	case 4:
++		/* VIN5 */
++		sel = 0xc4;
++		break;
++	default:
++		ret = -EINVAL;
++		dev_err(component->dev, "%s: unexpected control value\n", __func__);
++		goto error;
++		break;
++	}
++
++	ret = snd_soc_component_update_bits(component, WM8594_INPUT_CTRL3, 0xff, sel);
++	if (ret < 0)
++		goto error;
++	if (ret)
++		snd_soc_dapm_mux_update_power(dapm, kcontrol, item[0], e, NULL);
++	ret = 0;
++error:
++	return ret;
++}
++
++static int wm8594_pga_sel_get_switch(struct snd_kcontrol *kcontrol,
++				     struct snd_ctl_elem_value *ucontrol,
++				     u16 reg_left, u16 shift_left,
++				     u16 reg_right, u16 shift_right)
++{
++	struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
++	struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
++	int ret = 0;
++	u16 sel = 0;
++	sel = snd_soc_component_read(component, reg_left);
++	if (sel < 0)
++		sel = 0;
++	sel >>= shift_left;
++	sel &= 0xf;
++
++	switch (sel) {
++	case 0x0 ... 0x5:
++		ucontrol->value.enumerated.item[0] = sel;
++		break;
++	case 0x9:
++		ucontrol->value.enumerated.item[0] = 6;
++		break;
++	case 0xb:
++		ucontrol->value.enumerated.item[0] = 7;
++		break;
++	default:
++		ret = -EINVAL;
++		dev_err(component->dev, "%s: unexpected control value\n", __func__);
++		break;
++	};
++
++	return ret;
++}
++
++static int wm8594_pga_sel_set_switch(struct snd_kcontrol *kcontrol,
++				     struct snd_ctl_elem_value *ucontrol,
++				     u16 reg_left, u16 shift_left,
++				     u16 reg_right, u16 shift_right)
++{
++	struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
++	struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
++	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
++	unsigned int *item = ucontrol->value.enumerated.item;
++	int ret = 0, change = 0;
++	u16 lsel = 0, rsel = 0, lmsk = 0xf << shift_left,
++	    rmsk = 0xf << shift_right;
++
++	switch (item[0]) {
++	case 0: /* no input */
++		break;
++	case 1 ... 5: /* VIN1 - VIN5 */
++		lsel = item[0] << shift_left;
++		rsel = item[0] << shift_right;
++		break;
++	case 6: /* DAC1 */
++		lsel = 0x9 << shift_left;
++		rsel = 0xa << shift_right;
++		break;
++	case 7:
++		lsel = 0xb << shift_left;
++		rsel = 0xc << shift_right;
++		break;
++	default:
++		ret = -EINVAL;
++		dev_err(component->dev, "%s: unexpected control value\n", __func__);
++		goto error;
++	}
++
++	if (reg_left == reg_right) {
++		lsel |= rsel;
++		lmsk |= rmsk;
++		ret = snd_soc_component_update_bits(component, reg_left, lmsk, lsel);
++		if (ret < 0)
++			goto error;
++		change = ret;
++	} else {
++		ret = snd_soc_component_update_bits(component, reg_left, lmsk, lsel);
++		if (ret < 0)
++			goto error;
++		change = ret;
++		ret = snd_soc_component_update_bits(component, reg_right, rmsk, rsel);
++		if (ret < 0)
++			goto error;
++		change |= ret;
++	}
++
++	if (change) {
++		snd_soc_dapm_mux_update_power(dapm, kcontrol, item[0], e, NULL);
++	}
++error:
++	return ret;
++}
++
++static const DECLARE_TLV_DB_SCALE(dac_tlv, -10000, 50, 0);
++static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 0);
++static const DECLARE_TLV_DB_SCALE(pga_tlv, -7400, 50, 0xa0);
++
++
++static const struct snd_kcontrol_new wm8594_snd_controls[] = {
++	SOC_DOUBLE_R_EXT_TLV("WM8594 DAC1 Playback Volume",
++			     WM8594_DAC1L_VOL, WM8594_DAC1R_VOL, 0, 224, 0,
++			     snd_soc_get_volsw, wm8594_vol_update, dac_tlv),
++	SOC_SINGLE("WM8594 DAC1 Mute Switch", WM8594_DAC1_CTRL1, 9, 1, 1),
++
++	SOC_DOUBLE_R_EXT_TLV("WM8594 DAC2 Playback Volume",
++			     WM8594_DAC2L_VOL, WM8594_DAC2R_VOL, 0, 224, 0,
++			     snd_soc_get_volsw, wm8594_vol_update, dac_tlv),
++	SOC_SINGLE("WM8594 DAC2 Mute Switch", WM8594_DAC2_CTRL1, 9, 1, 1),
++
++	SOC_DOUBLE_R_EXT_TLV("WM8594 ADC Capture Volume",
++			     WM8594_ADCL_VOL, WM8594_ADCR_VOL, 0, 255, 0,
++			     snd_soc_get_volsw, wm8594_vol_update, adc_tlv),
++
++	SOC_DOUBLE_R_EXT_TLV("WM8594 PGA1 Volume",
++			     WM8594_PGA1L_VOL, WM8594_PGA1R_VOL, 0, 160, 1,
++			     snd_soc_get_volsw, wm8594_vol_update, pga_tlv),
++	SOC_DOUBLE("WM8594 PGA1 Mute Switch", WM8594_PGA_CTRL2, 1, 2, 1, 1),
++
++	SOC_DOUBLE_R_EXT_TLV("WM8594 PGA2 Volume",
++			     WM8594_PGA2L_VOL, WM8594_PGA2R_VOL, 0, 160, 1,
++			     snd_soc_get_volsw, wm8594_vol_update, pga_tlv),
++	SOC_DOUBLE("WM8594 PGA2 Mute Switch", WM8594_PGA_CTRL2, 3, 4, 1, 1),
++
++	SOC_DOUBLE_R_EXT_TLV("WM8594 PGA3 Volume",
++			     WM8594_PGA3L_VOL, WM8594_PGA3R_VOL, 0, 160, 1,
++			     snd_soc_get_volsw, wm8594_vol_update, pga_tlv),
++	SOC_DOUBLE("WM8594 PGA3 Mute Switch", WM8594_PGA_CTRL2, 5, 4, 1, 1),
++
++	SOC_SINGLE("WM8594 PGA Mute All Switch", WM8594_PGA_CTRL2, 0, 1, 1),
++
++	SOC_SINGLE("WM8594 ADC Gain Control", WM8594_INPUT_CTRL3, 8, 3, 0),
++};
++
++static int wm8594_pcm_hw_params(struct snd_pcm_substream *substream,
++				struct snd_pcm_hw_params *params,
++				struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++
++	u16 dac1_ctrl1 = wm8594_read(component, WM8594_DAC1_CTRL1) & ~0xc;
++	u16 dac1_ctrl2 = wm8594_read(component, WM8594_DAC1_CTRL2) & ~0x3f;
++	u16 dac2_ctrl1 = wm8594_read(component, WM8594_DAC2_CTRL1) & ~0xc;
++	u16 dac2_ctrl2 = wm8594_read(component, WM8594_DAC2_CTRL2) & ~0x3f;
++
++	u16 adc_ctrl1 = wm8594_read(component, WM8594_ADC_CTRL1) & ~0xc;
++	u16 adc_ctrl2 = wm8594_read(component, WM8594_ADC_CTRL2) & ~0x3f;
++
++	u16 add = wm8594_read(component, WM8594_ADD_CTRL1) & ~0x70;
++
++	switch (params_format(params)) {
++	case SNDRV_PCM_FORMAT_S16_LE:
++		break;
++	case SNDRV_PCM_FORMAT_S20_3LE:
++		dac1_ctrl1 |= 0x0004;
++		dac2_ctrl1 |= 0x0004;
++
++		adc_ctrl1 |= 0x0004;
++		break;
++	case SNDRV_PCM_FORMAT_S24_LE:
++		dac1_ctrl1 |= 0x0008;
++		dac2_ctrl1 |= 0x0008;
++
++		adc_ctrl1 |= 0x0008;
++		break;
++	case SNDRV_PCM_FORMAT_S32_LE:
++		dac1_ctrl1 |= 0x000c;
++		dac2_ctrl1 |= 0x000c;
++
++		adc_ctrl1 |= 0x000c;
++		break;
++	}
++
++	/* set sample rate */
++	switch (params_rate(params)) {
++	case SNDRV_PCM_RATE_32000:
++		break;
++	case SNDRV_PCM_RATE_44100:
++		add |= 0x10;
++		break;
++	case SNDRV_PCM_RATE_88200:
++		add |= 0x30;
++		break;
++	case SNDRV_PCM_RATE_96000:
++		add |= 0x40;
++		break;
++	case SNDRV_PCM_RATE_176400:
++		add |= 0x50;
++		break;
++	case SNDRV_PCM_RATE_192000:
++		add |= 0x60;
++		break;
++	/* 48000 is the default value */
++	case SNDRV_PCM_RATE_48000:
++	default:
++		add |= 0x20;
++		break;
++	}
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		switch (params_rate(params)) {
++		case 32000:
++			dac1_ctrl2 |= (6<<CTRL2_SR) | (3<<CTRL2_BCLKDIV); /*768*/
++			dac2_ctrl2 |= (6<<CTRL2_SR) | (3<<CTRL2_BCLKDIV);
++			break;
++		case 44100:
++			dac1_ctrl2 |= (0<<CTRL2_SR) | (3<<CTRL2_BCLKDIV); /*512 not sure*/
++			dac2_ctrl2 |= (0<<CTRL2_SR) | (3<<CTRL2_BCLKDIV);
++			break;
++			break;
++		case 96000:
++			dac1_ctrl2 |= (3<<CTRL2_SR) | (3<<CTRL2_BCLKDIV); /*256*/
++			dac2_ctrl2 |= (3<<CTRL2_SR) | (3<<CTRL2_BCLKDIV);
++			break;
++		case 48000:
++			dac1_ctrl2 |= (5<<CTRL2_SR) | (3<<CTRL2_BCLKDIV); /*512*/
++			dac2_ctrl2 |= (5<<CTRL2_SR) | (3<<CTRL2_BCLKDIV);
++		default:
++			dac1_ctrl2 |= (0<<CTRL2_SR) | (3<<CTRL2_BCLKDIV);
++			dac2_ctrl2 |= (0<<CTRL2_SR) | (3<<CTRL2_BCLKDIV);
++			break;
++		}
++	} else {
++		switch (params_rate(params)) {
++		case 32000:
++			adc_ctrl2 |= (6<<CTRL2_SR) | (3<<CTRL2_BCLKDIV);
++			break;
++		case 44100:
++			adc_ctrl2 = (5<<CTRL2_SR) | (3<<CTRL2_BCLKDIV);
++			break;
++			break;
++		case 96000:
++			adc_ctrl2 = (3<<CTRL2_SR) | (3<<CTRL2_BCLKDIV);
++			break;
++		case 48000:
++		default:
++			adc_ctrl2 = (5<<CTRL2_SR) | (3<<CTRL2_BCLKDIV);
++			break;
++		}
++	}
++
++	if(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		wm8594_write(component, WM8594_DAC1_CTRL1, dac1_ctrl1);
++		wm8594_write(component, WM8594_DAC1_CTRL2, dac1_ctrl2);
++		wm8594_write(component, WM8594_DAC2_CTRL1, dac2_ctrl1);
++		wm8594_write(component, WM8594_DAC2_CTRL2, dac2_ctrl2);
++	} else {
++		wm8594_write(component, WM8594_ADC_CTRL1, adc_ctrl1);
++		wm8594_write(component, WM8594_ADC_CTRL2, adc_ctrl2);
++	}
++	wm8594_write(component, WM8594_ADD_CTRL1, add);
++	return 0;
++}
++
++static int wm8594_set_dai_fmt(struct snd_soc_dai *component_dai,
++			      unsigned int fmt)
++{
++/*	struct snd_soc_component *component = component_dai->component;*/
++	struct snd_soc_component *component = component_dai->component;
++
++	u16 dac1_ctrl1 = wm8594_read(component, WM8594_DAC1_CTRL1)
++			 & ~0x33;
++	u16 dac1_ctrl3 = wm8594_read(component, WM8594_DAC1_CTRL3) & ~0x1;
++
++	u16 dac2_ctrl1 = wm8594_read(component, WM8594_DAC2_CTRL1)
++			 & ~0x33;
++	u16 dac2_ctrl3 = wm8594_read(component, WM8594_DAC2_CTRL3) & ~0x1;
++
++	u16 adc_ctrl1 = wm8594_read(component, WM8594_ADC_CTRL1) & ~0x33;
++	u16 adc_ctrl3 = wm8594_read(component, WM8594_ADC_CTRL3) & ~0x1;
++
++	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++	case SND_SOC_DAIFMT_CBM_CFM:
++#ifndef CONFIG_SND_ASOC_INGENIC_SHARE_CLK
++		dac1_ctrl3 |= 0x0001;
++		dac2_ctrl3 |= 0x0001;
++		adc_ctrl3 |= 0x0001;
++#else
++		switch (fmt & SND_SOC_WM8594_SHARE_CLOCK_MASK) {
++		case SND_SOC_WM8594_SHARE_CLOCK_PLAYBACK:
++			dac1_ctrl3 |= 0x0001;
++			dac2_ctrl3 |= 0x0001;
++			break;
++		case SND_SOC_WM8594_SHARE_CLOCK_RECORD:
++			adc_ctrl3 |= 0x0001;
++			break;
++		default:
++			dac1_ctrl3 |= 0x0001;
++			dac2_ctrl3 |= 0x0001;
++			break;
++		}
++#endif
++		break;
++
++	case SND_SOC_DAIFMT_CBS_CFM:
++		break;
++
++	default:
++		return -EINVAL;
++	}
++	/* interface format */
++	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_I2S:
++		dac1_ctrl1 |= 0x0002;
++		dac2_ctrl1 |= 0x0002;
++		adc_ctrl1 |= 0x0002;
++
++		break;
++
++	case SND_SOC_DAIFMT_RIGHT_J:
++
++		break;
++
++	case SND_SOC_DAIFMT_LEFT_J:
++		dac1_ctrl1 |= 0x0001;
++		dac2_ctrl1 |= 0x0001;
++		adc_ctrl1 |= 0x0001;
++
++		break;
++
++	case SND_SOC_DAIFMT_DSP_A:
++		dac1_ctrl1 |= 0x0003;
++		dac2_ctrl1 |= 0x0003;
++		adc_ctrl1 |= 0x0003;
++
++		break;
++
++	default:
++
++		return -EINVAL;
++	}
++
++	/* clock inversion */
++	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++	case SND_SOC_DAIFMT_NB_NF:
++		break;
++
++	case SND_SOC_DAIFMT_IB_IF:
++		dac1_ctrl1 |= 0x0030;
++		dac2_ctrl1 |= 0x0030;
++		adc_ctrl1 |= 0x0030;
++		break;
++
++	case SND_SOC_DAIFMT_IB_NF:
++		dac1_ctrl1 |= 0x0010;
++		dac2_ctrl1 |= 0x0010;
++		adc_ctrl1 |= 0x0010;
++		break;
++
++	case SND_SOC_DAIFMT_NB_IF:
++		dac1_ctrl1 |= 0x0020;
++		dac2_ctrl1 |= 0x0020;
++		adc_ctrl1 |= 0x0020;
++		break;
++
++	default:
++		return -EINVAL;
++	}
++
++	wm8594_write(component, WM8594_DAC1_CTRL1, dac1_ctrl1);
++	wm8594_write(component, WM8594_DAC1_CTRL3, dac1_ctrl3);
++
++	wm8594_write(component, WM8594_DAC2_CTRL1, dac2_ctrl1);
++	wm8594_write(component, WM8594_DAC2_CTRL3, dac2_ctrl3);
++
++	wm8594_write(component, WM8594_ADC_CTRL1, adc_ctrl1);
++	wm8594_write(component, WM8594_ADC_CTRL3, adc_ctrl3);
++	return 0;
++}
++
++static int wm8594_mute(struct snd_soc_dai *component_dai, int mute)
++{
++	return 0;
++}
++
++static struct snd_soc_dai_ops wm8594_dai_ops = {
++	.hw_params    = wm8594_pcm_hw_params,
++	.set_fmt      = wm8594_set_dai_fmt,
++};
++
++static int wm8594_power_up(struct snd_soc_component *component)
++{
++	struct wm8594_priv *wm8594 = snd_soc_component_get_drvdata(component);
++	u16 bias = 0;
++	u16 dac1 = wm8594_read(component, WM8594_DAC1_CTRL1) & ~0x100;
++	u16 dac2 = wm8594_read(component, WM8594_DAC2_CTRL1) & ~0x100;
++	u16 adc = wm8594_read(component, WM8594_ADC_CTRL1) & ~0x40;
++
++	if (wm8594->powered)
++		return 0;
++	wm8594->powered = true;
++
++	/*
++	 * set up initial biases
++	 * SOFT_ST | FAST_EN | POBCTRL | BUFIO_EN
++	 */
++	bias |= 0x1d;
++	wm8594_write(component, WM8594_BIAS, bias);
++
++	/*
++	 * enable output drivers to allow the AC coupling capacitors at the
++	 * output charge to be precharged to DACVMID
++	 * VOUTxL_EN | VOUTxR_EN
++	 */
++	wm8594_write(component, WM8594_OUTPUT_CTRL3, 0x1fc0);
++
++	/*
++	 * enable DACVMID, 750k selected for pop reduction
++	 * VMID_SEL = 10
++	 */
++	bias |= 0x80;
++	wm8594_write(component, WM8594_BIAS, bias);
++
++	/*
++	 * wait until DACVMID has fully charged
++	 */
++
++	mdelay(1500);
++
++	/*
++	 * enable master bias
++	 * BIAS_EN
++	 */
++	bias |= 0x20;
++	wm8594_write(component, WM8594_BIAS, bias);
++
++	/*
++	 * switch output drivers to use the master bias instead of the
++	 * power-up (fast) bias
++	 * POBCTRL = 0
++	 */
++	bias &= ~0x1;
++	wm8594_write(component, WM8594_BIAS, bias);
++
++	/*
++	 * enable all function required for use:
++	 * - enable all inputs
++	 * - enable component
++	 * - enable dac1, dac2 and adc
++	 */
++	wm8594_write(component, WM8594_INPUT_CTRL4, 0xff);
++	wm8594_write(component, WM8594_ENABLE, 0x1);
++	dac1 |= 0x100;
++	wm8594_write(component, WM8594_DAC1_CTRL1, dac1);
++	dac2 |= 0x100;
++	wm8594_write(component, WM8594_DAC2_CTRL1, dac2);
++	adc |= 0x40;
++	wm8594_write(component, WM8594_ADC_CTRL1, adc);
++
++	/*
++	 * unmute PGAs and switch DACVMID to 75k for normal operation
++	 */
++	bias &= ~0xc0;
++	bias |= 0x40;
++	wm8594_write(component, WM8594_PGA_CTRL2, 0x0);
++
++	return 0;
++}
++
++static int wm8594_power_down(struct snd_soc_component *component)
++{
++	struct wm8594_priv *wm8594 = snd_soc_component_get_drvdata(component);
++	u16 bias;
++	u16 dac1 = wm8594_read(component, WM8594_DAC1_CTRL1) & ~0x100;
++	u16 dac2 = wm8594_read(component, WM8594_DAC2_CTRL1) & ~0x100;
++	u16 adc = wm8594_read(component, WM8594_ADC_CTRL1) & ~0x40;
++	u16 output = wm8594_read(component, WM8594_OUTPUT_CTRL3) & ~0x40;
++
++	if (!wm8594->powered)
++		return 0;
++	wm8594->powered = false;
++	/*
++	 * mute all PGAs
++	 */
++	wm8594_write(component, WM8594_PGA_CTRL2, 0x7f);
++
++	/*
++	 * set biases for power down mode
++	 * FAST_EN = 1
++	 * VMID_SEL = 01
++	 * BIAS_EN = 1
++	 * BUFIO_EN = 1
++	 * VMIDTOG = 0
++	 * SOFT_ST = 1
++	 */
++	bias = 0x7c;
++	wm8594_write(component, WM8594_BIAS, bias);
++
++	/*
++	 * switch outputs to fast bias
++	 * POBCTRL = 1
++	 */
++	bias |= 0x2;
++	wm8594_write(component, WM8594_BIAS, bias);
++
++	/*
++	 * power down
++	 */
++	wm8594_write(component, WM8594_DAC1_CTRL1, dac1);
++	wm8594_write(component, WM8594_DAC2_CTRL1, dac2);
++	wm8594_write(component, WM8594_ADC_CTRL1, adc);
++	wm8594_write(component, WM8594_INPUT_CTRL4, 0x00);
++	wm8594_write(component, WM8594_ENABLE, 0x0);
++
++	/*
++	 * power down VMID
++	 * VMIDSEL = 00
++	 */
++	bias &= ~0xc0;
++	wm8594_write(component, WM8594_BIAS, bias);
++
++	/*
++	 * wait for DACVMID to be discharged
++	 */
++	mdelay(1500);
++
++
++	/*
++	 * clamp outputs to ground
++	 * power down outputs
++	 */
++	wm8594_write(component, WM8594_OUTPUT_CTRL3, output);
++	wm8594_write(component, WM8594_OUTPUT_CTRL3, 0);
++
++	/*
++	 * disable remaining bias controls
++	 */
++	bias = 0;
++	wm8594_write(component, WM8594_BIAS, bias);
++
++	return 0;
++}
++
++static int wm8594_set_bias_level(struct snd_soc_component *component,
++				 enum snd_soc_bias_level level)
++{
++	switch (level) {
++	case SND_SOC_BIAS_PREPARE:
++		break;
++	case SND_SOC_BIAS_STANDBY:
++		wm8594_power_up(component);
++		break;
++	case SND_SOC_BIAS_ON:
++		break;
++	case SND_SOC_BIAS_OFF:
++		wm8594_power_down(component);
++		break;
++	}
++	return 0;
++}
++
++static int wm8594_probe(struct snd_soc_component *component)
++{
++	int i;
++	int ret = 0;
++	dev_dbg(component->dev, "WM8594 Audio component");
++
++	ret = wm8594_reset(component);
++	if (ret != 0) {
++		dev_err(component->dev, "Failed to reset component: %d\n", ret);
++		return ret;
++	}
++
++	/* initialize component register */
++	for (i = 0; i < ARRAY_SIZE(wm8594_reg_init); i++) {
++		wm8594_write(component, wm8594_reg_init[i].reg,
++			     wm8594_reg_init[i].def);
++	}
++
++	return ret;
++}
++
++static int wm8594_resume(struct snd_soc_component *component)
++{
++	int i;
++	unsigned int value;
++	/* Sync reg_cache with the hardware */
++	for (i = 0; i < ARRAY_SIZE(wm8594_reg_defaults); i++) {
++		if (wm8594_reg_defaults[i].reg == WM8594_RESET)
++			continue;
++		value = snd_soc_component_read(component, wm8594_reg_defaults[i].reg);
++		snd_soc_component_write(component, wm8594_reg_defaults[i].reg, value);
++	}
++	return 0;
++}
++
++static struct regmap *wm8594_get_regmap(struct device *dev)
++{
++	struct wm8594_priv *wm8594 = dev_get_drvdata(dev);
++	return wm8594->regmap;
++}
++
++static int wm8594_pga1_sel_get_switch(struct snd_kcontrol *kcontrol,
++				      struct snd_ctl_elem_value *ucontrol)
++{
++	return wm8594_pga_sel_get_switch(kcontrol, ucontrol,
++					 WM8594_INPUT_CTRL1, 0,
++					 WM8594_INPUT_CTRL1, 4);
++}
++
++static int wm8594_pga1_sel_set_switch(struct snd_kcontrol *kcontrol,
++				      struct snd_ctl_elem_value *ucontrol)
++{
++	return wm8594_pga_sel_set_switch(kcontrol, ucontrol,
++					 WM8594_INPUT_CTRL1, 0,
++					 WM8594_INPUT_CTRL1, 4);
++}
++
++static int wm8594_pga2_sel_get_switch(struct snd_kcontrol *kcontrol,
++				      struct snd_ctl_elem_value *ucontrol)
++{
++	return wm8594_pga_sel_get_switch(kcontrol, ucontrol,
++					 WM8594_INPUT_CTRL1, 8,
++					 WM8594_INPUT_CTRL2, 0);
++}
++
++static int wm8594_pga2_sel_set_switch(struct snd_kcontrol *kcontrol,
++				      struct snd_ctl_elem_value *ucontrol)
++{
++	return wm8594_pga_sel_set_switch(kcontrol, ucontrol,
++					 WM8594_INPUT_CTRL1, 8,
++					 WM8594_INPUT_CTRL2, 0);
++}
++
++static int wm8594_pga3_sel_get_switch(struct snd_kcontrol *kcontrol,
++				      struct snd_ctl_elem_value *ucontrol)
++{
++	return wm8594_pga_sel_get_switch(kcontrol, ucontrol,
++					 WM8594_INPUT_CTRL2, 4,
++					 WM8594_INPUT_CTRL2, 8);
++}
++
++static int wm8594_pga3_sel_set_switch(struct snd_kcontrol *kcontrol,
++				      struct snd_ctl_elem_value *ucontrol)
++{
++	return wm8594_pga_sel_set_switch(kcontrol, ucontrol,
++					 WM8594_INPUT_CTRL2, 4,
++					 WM8594_INPUT_CTRL2, 8);
++}
++
++static const char * const wm8594_adc_input_sel_text[] = {
++	"VIN1", "VIN2", "VIN3", "VIN4", "VIN5"
++};
++
++static const char * const wm8594_pga_sel_text[] = {
++	"No Input", "VIN1", "VIN2", "VIN3", "VIN4", "VIN5", "DAC1", "DAC2"
++};
++
++static const struct soc_enum wm8594_adc_input_sel_enum =
++	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wm8594_adc_input_sel_text),
++			    wm8594_adc_input_sel_text);
++
++static const struct soc_enum wm8594_pga_sel_enum =
++	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wm8594_pga_sel_text),
++			    wm8594_pga_sel_text);
++
++static const struct snd_kcontrol_new wm8594_pga1_controls =
++	SOC_ENUM_EXT("PGA1 Input Selection", wm8594_pga_sel_enum,
++		     wm8594_pga1_sel_get_switch, wm8594_pga1_sel_set_switch);
++
++static const struct snd_kcontrol_new wm8594_pga2_controls =
++	SOC_ENUM_EXT("PGA2 Input Selection", wm8594_pga_sel_enum,
++		     wm8594_pga2_sel_get_switch, wm8594_pga2_sel_set_switch);
++
++static const struct snd_kcontrol_new wm8594_pga3_controls =
++	SOC_ENUM_EXT("PGA3 Input Selection", wm8594_pga_sel_enum,
++		     wm8594_pga3_sel_get_switch, wm8594_pga3_sel_set_switch);
++
++static const struct snd_kcontrol_new wm8594_adc_controls =
++	SOC_ENUM_EXT("ADC Input Selection", wm8594_adc_input_sel_enum,
++		     wm8594_adc_input_get_switch, wm8594_adc_input_set_switch);
++
++static const struct snd_soc_dapm_widget wm8594_dapm_widgets[] = {
++	SND_SOC_DAPM_DAC("DAC1", "Playback", SND_SOC_NOPM, 0, 0),
++	SND_SOC_DAPM_DAC("DAC2", "Playback", SND_SOC_NOPM, 0, 0),
++
++	SND_SOC_DAPM_MUX("VOUT1_MUX", SND_SOC_NOPM, 0, 0, &wm8594_pga1_controls),
++	SND_SOC_DAPM_MUX("VOUT2_MUX", SND_SOC_NOPM, 0, 0, &wm8594_pga2_controls),
++	SND_SOC_DAPM_MUX("VOUT3_MUX", SND_SOC_NOPM, 0, 0, &wm8594_pga3_controls),
++
++	SND_SOC_DAPM_OUTPUT("VOUT1"),
++	SND_SOC_DAPM_OUTPUT("VOUT2"),
++	SND_SOC_DAPM_OUTPUT("VOUT3"),
++
++	SND_SOC_DAPM_ADC("ADC", "Capture", SND_SOC_NOPM, 0, 0),
++
++	SND_SOC_DAPM_MUX("VIN_MUX", SND_SOC_NOPM, 0, 0, &wm8594_adc_controls),
++
++	SND_SOC_DAPM_INPUT("AIN1"),
++	SND_SOC_DAPM_INPUT("AIN2"),
++	SND_SOC_DAPM_INPUT("AIN3"),
++	SND_SOC_DAPM_INPUT("AIN4"),
++	SND_SOC_DAPM_INPUT("AIN5"),
++};
++
++static const struct snd_soc_dapm_route wm8594_dapm_routes[] = {
++	{ "VOUT1", NULL, "VOUT1_MUX" },
++	{ "VOUT2", NULL, "VOUT2_MUX" },
++	{ "VOUT3", NULL, "VOUT3_MUX" },
++
++	{ "VOUT1_MUX", NULL, "DAC1"},
++	{ "VOUT2_MUX", NULL, "DAC1"},
++	{ "VOUT3_MUX", NULL, "DAC1"},
++	{ "VOUT1_MUX", NULL, "DAC2"},
++	{ "VOUT2_MUX", NULL, "DAC2"},
++	{ "VOUT3_MUX", NULL, "DAC2"},
++
++	{ "VOUT1_MUX", "VIN1", "AIN1"},
++	{ "VOUT1_MUX", "VIN2", "AIN2"},
++	{ "VOUT1_MUX", "VIN3", "AIN3"},
++	{ "VOUT1_MUX", "VIN4", "AIN4"},
++	{ "VOUT1_MUX", "VIN5", "AIN5"},
++
++	{ "VOUT2_MUX", "VIN1", "AIN1"},
++	{ "VOUT2_MUX", "VIN2", "AIN2"},
++	{ "VOUT2_MUX", "VIN3", "AIN3"},
++	{ "VOUT2_MUX", "VIN4", "AIN4"},
++	{ "VOUT2_MUX", "VIN5", "AIN5"},
++
++	{ "VOUT3_MUX", "VIN1", "AIN1"},
++	{ "VOUT3_MUX", "VIN2", "AIN2"},
++	{ "VOUT3_MUX", "VIN3", "AIN3"},
++	{ "VOUT3_MUX", "VIN4", "AIN4"},
++	{ "VOUT3_MUX", "VIN5", "AIN5"},
++
++	{ "VIN_MUX", "VIN1", "AIN1"},
++	{ "VIN_MUX", "VIN2", "AIN2"},
++	{ "VIN_MUX", "VIN3", "AIN3"},
++	{ "VIN_MUX", "VIN4", "AIN4"},
++	{ "VIN_MUX", "VIN5", "AIN5"},
++
++	{ "ADC", NULL, "VIN_MUX" },
++};
++
++struct snd_soc_component_driver soc_component_dev_wm8594 = {
++	.probe             = wm8594_probe,
++	.resume            = wm8594_resume,
++	.set_bias_level    = wm8594_set_bias_level,
++	.controls          = wm8594_snd_controls,
++	.num_controls      = ARRAY_SIZE(wm8594_snd_controls),
++	.dapm_widgets      = wm8594_dapm_widgets,
++	.num_dapm_widgets  = ARRAY_SIZE(wm8594_dapm_widgets),
++	.dapm_routes       = wm8594_dapm_routes,
++	.num_dapm_routes   = ARRAY_SIZE(wm8594_dapm_routes),
++	.suspend_bias_off  = false,
++};
++
++#define WM8594_RATES (SNDRV_PCM_RATE_8000  |	\
++		      SNDRV_PCM_RATE_11025 |	\
++		      SNDRV_PCM_RATE_16000 |	\
++		      SNDRV_PCM_RATE_22050 |	\
++		      SNDRV_PCM_RATE_32000 |	\
++		      SNDRV_PCM_RATE_44100 |	\
++		      SNDRV_PCM_RATE_48000 |	\
++		      SNDRV_PCM_RATE_96000 |	\
++		      SNDRV_PCM_RATE_192000)
++
++#define WM8594_FORMATS (SNDRV_PCM_FMTBIT_S16_LE  |	\
++			SNDRV_PCM_FMTBIT_S20_3LE |	\
++			SNDRV_PCM_FMTBIT_S24_LE  |	\
++			SNDRV_PCM_FMTBIT_S24_3LE |	\
++			SNDRV_PCM_FMTBIT_S32_LE)
++
++static struct snd_soc_dai_driver wm8594_dai[] = {
++	{
++		.name     = "wm8594-hifi",
++		.id       = 0,
++		.playback = {
++			.stream_name  = "Playback",
++			.channels_min = 1,
++			.channels_max = 2,
++			.rates        = WM8594_RATES,
++			.formats      = WM8594_FORMATS,
++		},
++		.capture = {
++			.stream_name  = "Capture",
++			.channels_min = 1,
++			.channels_max = 2,
++			.rates        = WM8594_RATES,
++			.formats      = WM8594_FORMATS,
++		},
++		.ops = &wm8594_dai_ops,
++	},
++};
++
++static const struct regmap_config wm8903_regmap = {
++	.reg_bits = 8,
++	.val_bits = 16,
++	.max_register = WM8594_CACHEREG_NUM,
++	.cache_type = REGCACHE_RBTREE,
++	.reg_defaults = wm8594_reg_defaults,
++	.num_reg_defaults = ARRAY_SIZE(wm8594_reg_defaults),
++};
++
++static int wm8594_i2c_probe(struct i2c_client *i2c,
++			    const struct i2c_device_id *id)
++{
++	struct wm8594_priv *wm8594;
++	int ret;
++	unsigned int devid = 0, version = 0;
++
++	wm8594 = devm_kzalloc(&i2c->dev,
++			sizeof(struct wm8594_priv),
++			GFP_KERNEL);
++	if (!wm8594)
++		return -ENOMEM;
++
++	wm8594->regmap = devm_regmap_init_i2c(i2c, &wm8903_regmap);
++	if (IS_ERR(wm8594->regmap)) {
++		ret = PTR_ERR(wm8594->regmap);
++		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
++			ret);
++		return ret;
++	}
++	wm8594->powered = false;
++
++	wm8594->reset_gpiod = devm_gpiod_get_optional(&i2c->dev, "reset",
++						      GPIOD_OUT_LOW);
++	if (IS_ERR(wm8594->reset_gpiod))
++		return PTR_ERR(wm8594->reset_gpiod);
++	gpiod_set_value_cansleep(wm8594->reset_gpiod, 1);
++
++	wm8594->pwdn_gpiod = devm_gpiod_get_optional(&i2c->dev, "pwdn",
++						     GPIOD_OUT_LOW);
++	if (IS_ERR(wm8594->pwdn_gpiod))
++		return PTR_ERR(wm8594->pwdn_gpiod);
++	gpiod_set_value_cansleep(wm8594->pwdn_gpiod, 1);
++
++	wm8594->mute_gpiod = devm_gpiod_get_optional(&i2c->dev, "mute",
++						     GPIOD_OUT_LOW);
++	if (IS_ERR(wm8594->mute_gpiod))
++		return PTR_ERR(wm8594->mute_gpiod);
++	gpiod_set_value_cansleep(wm8594->mute_gpiod, 0);
++
++	regcache_cache_bypass(wm8594->regmap, true);
++	regmap_read(wm8594->regmap, WM8594_DEVICE_ID, &devid);
++	regmap_read(wm8594->regmap, WM8594_REVISION, &version);
++	regcache_cache_bypass(wm8594->regmap, false);
++	dev_info(&i2c->dev, "DEVID %x, VERSION %x\n", devid & 0xffff, version & 0xff);
++
++	i2c_set_clientdata(i2c, wm8594);
++
++	ret = snd_soc_register_component(&i2c->dev, &soc_component_dev_wm8594,
++				     wm8594_dai, ARRAY_SIZE(wm8594_dai));
++
++	if (ret < 0) {
++		pr_err(CODEC_NAME  ": %s failed: ret = %d\n", __func__, ret);
++		return ret;
++	}
++
++	dev_info(&i2c->dev, "probe success!!!\n");
++
++	return ret;
++}
++
++static int wm8594_i2c_remove(struct i2c_client *client)
++{
++	snd_soc_unregister_component(&client->dev);
++	return 0;
++}
++
++/*
++ * WM8594 2 wires address is determined by pin 45
++ * state during powerup.
++ *    low  = 0x1a
++ *    high = 0x1c
++ */
++static const struct i2c_device_id wm8594_i2c_table[] = {
++	{"wm8594", 0},
++	{}
++};
++MODULE_DEVICE_TABLE(i2c, wm8594_i2c_table);
++
++static const struct of_device_id wm8594_of_match[] = {
++	{.compatible = "wlf,wm8594", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, wm8594_of_match);
++
++static struct i2c_driver wm8594_i2c_driver = {
++	.driver = {
++		.name = "wm8594",
++		.of_match_table = of_match_ptr(wm8594_of_match),
++	},
++	.probe    = wm8594_i2c_probe,
++	.remove   = wm8594_i2c_remove,
++	.id_table = wm8594_i2c_table,
++};
++module_i2c_driver(wm8594_i2c_driver);
++
++MODULE_DESCRIPTION("ASoC wm8594 driver");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/sound/soc/ingenic/ecodec/wm8594.h b/module_drivers/sound/soc/ingenic/ecodec/wm8594.h
+new file mode 100644
+index 000000000..4d0b6d0ab
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/ecodec/wm8594.h
+@@ -0,0 +1,64 @@
++/*
++ *  sound/soc/ingenic/ecodec/wm8594.c
++ *	ALSA SoC driver for wm8594 ADC
++ *
++ *  Copyright 2017 Ingenic Semiconductor Co.,Ltd
++ *	wqshao <wangquan.shao@ingenic.com>
++ *
++ *  This program is free software; you can redistribute  it and/or modify it
++ *  under  the terms of  the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the  License, or (at your
++ *  option) any later version.
++ *
++ *  Only for x2000 FPGA SoCs test.
++ */
++
++#ifndef _WM8594_H_
++#define _WM8594_H_
++
++#define WM8594_RESET		0x00
++#define WM8594_DEVICE_ID	0x00
++#define WM8594_REVISION		0x01
++#define WM8594_DAC1_CTRL1	0x02
++#define WM8594_DAC1_CTRL2	0x03
++#define WM8594_DAC1_CTRL3	0x04
++#define WM8594_DAC1L_VOL	0x05
++#define WM8594_DAC1R_VOL	0x06
++#define WM8594_DAC2_CTRL1	0x07
++#define WM8594_DAC2_CTRL2	0x08
++#define WM8594_DAC2_CTRL3	0x09
++#define WM8594_DAC2L_VOL	0x0a
++#define WM8594_DAC2R_VOL	0x0b
++#define WM8594_ENABLE		0x0c
++#define WM8594_ADC_CTRL1	0x0d
++#define WM8594_ADC_CTRL2	0x0e
++#define WM8594_ADC_CTRL3	0x0f
++#define WM8594_ADCL_VOL		0x10
++#define WM8594_ADCR_VOL		0x11
++/* register 0x12 reserved */
++#define WM8594_PGA1L_VOL	0x13
++#define WM8594_PGA1R_VOL	0x14
++#define WM8594_PGA2L_VOL	0x15
++#define WM8594_PGA2R_VOL	0x16
++#define WM8594_PGA3L_VOL	0x17
++#define WM8594_PGA3R_VOL	0x18
++#define WM8594_PGA_CTRL1	0x19
++#define WM8594_PGA_CTRL2	0x1a
++#define WM8594_ADD_CTRL1	0x1b
++#define WM8594_INPUT_CTRL1	0x1c
++#define WM8594_INPUT_CTRL2	0x1d
++#define WM8594_INPUT_CTRL3	0x1e
++#define WM8594_INPUT_CTRL4	0x1f
++#define WM8594_OUTPUT_CTRL1	0x20
++#define WM8594_OUTPUT_CTRL2	0x21
++#define WM8594_OUTPUT_CTRL3	0x22
++#define WM8594_BIAS		0x23
++#define WM8594_PGA_CTRL3	0x24
++
++#define WM8594_CACHEREG_NUM	36
++
++#define  CTRL2_SR       0
++#define  CTRL2_BCLKDIV  3
++
++#endif
++
+diff --git a/module_drivers/sound/soc/ingenic/icodec/Makefile b/module_drivers/sound/soc/ingenic/icodec/Makefile
+new file mode 100644
+index 000000000..8629fee16
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/icodec/Makefile
+@@ -0,0 +1,6 @@
++
++obj-$(CONFIG_SND_ASOC_INGENIC_DUMP_CODEC) += dump.o
++obj-$(CONFIG_SND_ASOC_INGENIC_ICDC_D3) += icdc_d3.o
++obj-$(CONFIG_SND_ASOC_INGENIC_ICDC_INNO) += icdc_inno.o
++obj-$(CONFIG_SND_ASOC_INGENIC_ICDC_INNO_V2) += icdc_inno_v2.o
++
+diff --git a/module_drivers/sound/soc/ingenic/icodec/dump.c b/module_drivers/sound/soc/ingenic/icodec/dump.c
+new file mode 100644
+index 000000000..7416429fa
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/icodec/dump.c
+@@ -0,0 +1,119 @@
++/*
++ * sound/soc/ingenic/icodec/dump.c
++ * ALSA SoC Audio driver -- dump codec driver used for devices like bt, hdmi
++
++ * Copyright 2014 Ingenic Semiconductor Co.,Ltd
++ *	cli <chen.li@ingenic.com>
++ *
++ * Note: dlv4780 is an internal codec for ingenic SOC
++ *	 used for dlv4780 m200 and so on
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/pm.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <sound/soc.h>
++#include <sound/soc-dai.h>
++
++static const struct snd_soc_dai_driver pcm_dump_dai __initdata = {
++	.name = "pcm-dump",
++	.playback = {
++		.channels_min = 1,
++		.channels_max = 2,
++		.rates = SNDRV_PCM_RATE_8000_192000,
++		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE |
++			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8,
++	},
++	.capture = {
++		.channels_min = 1,
++		.channels_max = 2,
++		.rates = SNDRV_PCM_RATE_8000_192000,
++		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE |
++			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8,
++	},
++};
++
++static const struct snd_soc_dai_driver spdif_dump_dai __initdata = {
++	.name = "spdif-dump",
++	.playback = {
++		.channels_min = 1,
++		.channels_max = 2,
++		.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
++			SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
++		.formats = SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE,
++	},
++};
++
++static const struct snd_soc_dai_driver dmic_dump_dai __initdata = {
++	.name = "dmic-dump",
++	.capture = {
++		.channels_min = 1,
++		.channels_max = 4,
++		.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
++		.formats = SNDRV_PCM_FMTBIT_S16_LE,
++	},
++};
++
++static const struct of_device_id dump_dt_match[];
++static int dump_platform_probe(struct platform_device *pdev)
++{
++	struct snd_soc_component_driver *dump_codec;
++	struct snd_soc_dai_driver *dump_dai;
++	const struct of_device_id *match;
++	int ret = 0;
++
++	dump_dai = (struct snd_soc_dai_driver *)devm_kzalloc(&pdev->dev,
++			sizeof(struct snd_soc_dai_driver), GFP_KERNEL);
++	if (!dump_dai)
++		return -ENOMEM;
++	match = of_match_node(dump_dt_match, pdev->dev.of_node);
++	if (!match)
++		return -ENODEV;
++	memcpy(dump_dai, match->data, sizeof(struct snd_soc_dai_driver));
++
++	dump_codec = (struct snd_soc_component_driver *)devm_kzalloc(&pdev->dev,
++			sizeof(struct snd_soc_component_driver), GFP_KERNEL);
++	if (!dump_codec)
++		return -ENOMEM;
++
++	ret = snd_soc_register_component(&pdev->dev, dump_codec, dump_dai, 1);
++	dev_dbg(&pdev->dev, "codec dump codec platfrom probe success\n");
++	return ret;
++}
++
++static int dump_platform_remove(struct platform_device *pdev)
++{
++	snd_soc_unregister_component(&pdev->dev);
++	return 0;
++}
++
++static const struct of_device_id dump_dt_match[] = {
++	{ .compatible = "ingenic,pcm-dump-codec", .data = &pcm_dump_dai},
++	{ .compatible = "ingenic,spdif-dump-codec", .data = &spdif_dump_dai},
++	{ .compatible = "ingenic,dmic-dump-codec", .data = &dmic_dump_dai},
++	{},
++};
++MODULE_DEVICE_TABLE(of, dump_dt_match);
++
++static struct platform_driver dump_driver = {
++	.driver = {
++		.name = "dump codec",
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(dump_dt_match),
++	},
++	.probe = dump_platform_probe,
++	.remove = dump_platform_remove,
++};
++module_platform_driver(dump_driver);
++
++MODULE_DESCRIPTION("Dump Codec Driver");
++MODULE_AUTHOR("cli<chen.li@ingenic.com>");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/sound/soc/ingenic/icodec/icdc_d3.c b/module_drivers/sound/soc/ingenic/icodec/icdc_d3.c
+new file mode 100644
+index 000000000..59b83e8af
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/icodec/icdc_d3.c
+@@ -0,0 +1,762 @@
++/*
++ * sound/soc/ingenic/icodec/icdc_d3.c
++ * ALSA SoC Audio driver -- ingenic internal codec (icdc_d3) driver
++
++ * Copyright 2014 Ingenic Semiconductor Co.,Ltd
++ *	cscheng <shicheng.cheng@ingenic.com>
++ *
++ * Note: icdc_d3 is an internal codec for ingenic SOC
++ *	 used for x1000 and so on
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/pm.h>
++#include <linux/platform_device.h>
++#include <linux/vmalloc.h>
++#include <linux/slab.h>
++#include <linux/ctype.h>
++#include <linux/io.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/jack.h>
++#include <sound/soc-dapm.h>
++#include <sound/initval.h>
++#include <sound/tlv.h>
++#include <asm/div64.h>
++#include <sound/soc-dai.h>
++#include <linux/of_address.h>
++#include "icdc_d3.h"
++
++static int icdc_d3_debug = 0;
++module_param(icdc_d3_debug, int, 0644);
++#define DEBUG_MSG(msg...)			\
++	do {					\
++		if (icdc_d3_debug)		\
++			printk("ICDC: " msg);	\
++	} while(0)
++
++static u8 icdc_d3_reg_defcache[SCODA_MAX_REG_NUM] = {
++/* reg 0x0 ... 0x9 */
++		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xd3,0xd3,
++/* reg 0xa ... 0x13 */
++		0x00,0x30,0x30,0xb0,0xb1,0xb0,0x00,0x00,0x0f,0x40,
++/* reg 0x14 ... 0x1d */
++		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x00,0xff,
++/* reg 0x1e ... 0x27 */
++		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++/* reg 0x28 ... 0x31 */
++		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++/* reg 0x32 ... 0x39 */
++		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++/* extern reg */
++		0x00,0x00,0x00,0x00,0x00,
++		0x00,0x00,0x00,0x00,
++		0x00,0x00,0x00,0x00,
++		0x34,0x07,0x44,0x1f,0x00,
++};
++
++static int icdc_d3_volatile(struct snd_soc_codec *codec, unsigned int reg)
++{
++	if (reg > SCODA_MAX_REG_NUM)
++		return 1;
++
++	switch (reg) {
++	case SCODA_REG_SR:
++	case SCODA_REG_SR2:
++	case SCODA_REG_SIGR:
++	case SCODA_REG_SIGR3:
++	case SCODA_REG_SIGR5:
++	case SCODA_REG_SIGR7:
++	case SCODA_REG_MR:
++	case SCODA_REG_IFR:
++	case SCODA_REG_IFR2:
++	case SCODA_REG_SR_ADC_AGCDGL:
++	case SCODA_REG_SR_ADC_AGCDGR:
++	case SCODA_REG_SR_ADC_AGCAGL:
++	case SCODA_REG_SR_ADC_AGCAGR:
++	case SCODA_REG_SR_TR1:
++	case SCODA_REG_SR_TR2:
++	case SCODA_REG_SR_TR_SRCDAC:
++		return 1;
++	default:
++		return 0;
++	}
++}
++
++static int icdc_d3_writable(struct snd_soc_codec *codec, unsigned int reg)
++{
++	if (reg > SCODA_MAX_REG_NUM)
++		return 0;
++
++	switch (reg) {
++	case SCODA_REG_SR:
++	case SCODA_REG_SR2:
++	case SCODA_REG_SIGR:
++	case SCODA_REG_SIGR3:
++	case SCODA_REG_SIGR5:
++	case SCODA_REG_SIGR7:
++	case SCODA_REG_MR:
++	case SCODA_REG_SR_ADC_AGCDGL:
++	case SCODA_REG_SR_ADC_AGCDGR:
++	case SCODA_REG_SR_ADC_AGCAGL:
++	case SCODA_REG_SR_ADC_AGCAGR:
++	case SCODA_REG_SR_TR1:
++	case SCODA_REG_SR_TR2:
++	case SCODA_REG_SR_TR_SRCDAC:
++		return 0;
++	default:
++		return 1;
++	}
++}
++
++static int icdc_d3_readable(struct snd_soc_codec *codec, unsigned int reg)
++{
++	if (reg > SCODA_MAX_REG_NUM)
++		return 0;
++	else
++		return 1;
++}
++
++static void dump_registers_hazard(struct icdc_d3 *icdc_d3)
++{
++	int reg = 0;
++	dev_info(icdc_d3->dev, "-------------------register:");
++	for ( ; reg < SCODA_MAX_REG_NUM; reg++) {
++		if (reg % 8 == 0)
++			printk("\n");
++		if (icdc_d3_readable(icdc_d3->codec, reg))
++			printk(" 0x%02x:0x%02x,", reg, icdc_d3_hw_read(icdc_d3, reg));
++		else
++			printk(" 0x%02x:0x%02x,", reg, 0x0);
++	}
++	printk("\n");
++	printk("mix_0=%02x\n", icdc_d3_hw_read_extend(icdc_d3, SCODA_MIX_0));
++	printk("mix_1=%02x\n", icdc_d3_hw_read_extend(icdc_d3, SCODA_MIX_1));
++	printk("mix_2=%02x\n", icdc_d3_hw_read_extend(icdc_d3, SCODA_MIX_2));
++	printk("mix_3=%02x\n", icdc_d3_hw_read_extend(icdc_d3, SCODA_MIX_3));
++	printk("mix_4=%02x\n", icdc_d3_hw_read_extend(icdc_d3, SCODA_MIX_4));
++
++	printk("\n");
++	dev_info(icdc_d3->dev, "----------------------------\n");
++	return;
++}
++
++static int icdc_d3_write(struct snd_soc_codec *codec, unsigned int reg,
++			unsigned int value)
++{
++	struct icdc_d3 *icdc_d3 = snd_soc_codec_get_drvdata(codec);
++	int val = value;
++	BUG_ON(reg > SCODA_MAX_REG_NUM);
++	dev_dbg(icdc_d3->dev,"%s reg = %x value = %x \n",__func__,reg,val);
++
++	if (icdc_d3_writable(codec, reg)) {
++		if (!icdc_d3_volatile(codec,reg)) {
++			u8 *cache = codec->reg_cache;
++			if((reg == SCODA_REG_GCR_DACL) || (reg == SCODA_REG_GCR_DACR)){
++				if(val < 32)
++					val = 31 - val;
++				else
++					val = 95 - val;
++			}
++			cache[reg] = val;
++		}
++		return icdc_d3_hw_write(icdc_d3, reg, val);
++	}
++	return 0;
++}
++
++static unsigned int icdc_d3_read(struct snd_soc_codec *codec, unsigned int reg)
++{
++
++	struct icdc_d3 *icdc_d3 = snd_soc_codec_get_drvdata(codec);
++	int val = 0;
++	BUG_ON(reg > SCODA_MAX_REG_NUM);
++
++	if (!icdc_d3_volatile(codec, reg)) {
++		u8 *cache = codec->reg_cache;
++		val = cache[reg];
++		if((reg == SCODA_REG_GCR_DACL) || (reg == SCODA_REG_GCR_DACR)){
++			if(val < 32)
++				val = 31 - val;
++			else
++				val = 95 - val;
++		}
++		return val;
++	}
++
++	if (icdc_d3_readable(codec, reg))
++		return icdc_d3_hw_read(icdc_d3, reg);
++
++	return 0;
++}
++
++static int icdc_d3_hw_params(struct snd_pcm_substream *substream,
++			    struct snd_pcm_hw_params *params,
++			    struct snd_soc_dai *dai)
++{
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++	struct snd_soc_codec *codec = rtd->codec;
++	int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
++	int bit_width_sel = 3;
++	int speed_sel = 0;
++	int aicr_reg = playback ? SCODA_REG_AICR_DAC : SCODA_REG_AICR_ADC;
++	int fcr_reg = playback ? SCODA_REG_FCR_DAC : SCODA_REG_FCR_ADC;
++	int sample_attr[] = {	8000, 11025, 12000, 16000, 22050,  24000, 32000,44100,
++				48000, 88200,  96000, 176400, 192000,};
++	int speed = params_rate(params);
++	int bit_width = params_format(params);
++	DEBUG_MSG("%s enter  set bus width %d , sample rate %d\n",
++			__func__, bit_width, speed);
++	/* bit width */
++	switch (bit_width) {
++	case SNDRV_PCM_FORMAT_S16_LE:
++		bit_width_sel = 0;
++		break;
++	case SNDRV_PCM_FORMAT_S18_3LE:
++		bit_width_sel = 1;
++		break;
++	case SNDRV_PCM_FORMAT_S20_3LE:
++		bit_width_sel = 2;
++		break;
++	default:
++	case SNDRV_PCM_FORMAT_S24_3LE:
++		bit_width_sel = 3;
++		break;
++	}
++
++	/*sample rate*/
++	for (speed_sel = 0; speed > sample_attr[speed_sel]; speed_sel++)
++		;
++	snd_soc_update_bits(codec, aicr_reg, SCODA_AICR_DAC_ADWL_MASK,
++			(bit_width_sel << SCODA_AICR_DAC_ADWL_SHIFT));
++	snd_soc_update_bits(codec, fcr_reg, SCODA_FCR_FREQ_MASK,
++			(speed_sel << SCODA_FCR_FREQ_SHIFT));
++	return 0;
++}
++
++static int icdc_d3_trigger(struct snd_pcm_substream * stream, int cmd,
++		struct snd_soc_dai *dai)
++{
++#ifdef DEBUG
++	struct snd_soc_codec *codec = dai->codec;
++	struct icdc_d3 *icdc_d3 = snd_soc_codec_get_drvdata(codec);
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		dump_registers_hazard(icdc_d3);
++		break;
++	case SNDRV_PCM_TRIGGER_STOP:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++		dump_registers_hazard(icdc_d3);
++		break;
++	}
++#endif
++	return 0;
++}
++
++#define DLV4780_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
++			 SNDRV_PCM_FMTBIT_S20_3LE |SNDRV_PCM_FMTBIT_S24_LE)
++
++static int ingenic_icdc_startup(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct snd_soc_codec *codec = dai->codec;
++
++	/*power on codec*/
++	if (snd_soc_update_bits(codec, SCODA_REG_CR_VIC, SCODA_CR_VIC_SB_MASK, 0))
++		msleep(250);
++	if (snd_soc_update_bits(codec, SCODA_REG_CR_VIC, SCODA_CR_VIC_SB_SLEEP_MASK, 0))
++		msleep(400);
++
++	return 0;
++}
++
++
++static void ingenic_icdc_shutdown(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct snd_soc_codec *codec = dai->codec;
++	/*power off codec*/
++	snd_soc_update_bits(codec, SCODA_REG_CR_VIC, SCODA_CR_VIC_SB_SLEEP_MASK, 1);
++	snd_soc_update_bits(codec, SCODA_REG_CR_VIC, SCODA_CR_VIC_SB_MASK, 1);
++	return;
++}
++
++
++int icdc_d3_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
++{
++	struct snd_soc_codec *codec = dai->codec;
++
++	if(stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		snd_soc_update_bits(codec, SCODA_REG_CR_DAC, SCODA_CR_DAC_SMUTE_MASK, mute << SCODA_CR_DAC_SMUTE_SHIFT);
++	} else if(stream == SNDRV_PCM_STREAM_CAPTURE) {
++		snd_soc_update_bits(codec, SCODA_REG_CR_ADC, SCODA_CR_ADC_SMUTE_MASK, mute << SCODA_CR_ADC_SMUTE_SHIFT);
++	}
++	return 0;
++}
++
++
++static struct snd_soc_dai_ops icdc_d3_dai_ops = {
++	.hw_params	= icdc_d3_hw_params,
++	.mute_stream	= icdc_d3_mute_stream,
++	.trigger	= icdc_d3_trigger,
++	.shutdown	= ingenic_icdc_shutdown,
++	.startup	= ingenic_icdc_startup,
++};
++
++static struct snd_soc_dai_driver  icdc_d3_codec_dai = {
++	.name = "icdc-d3-hifi",
++	.playback = {
++		.stream_name = "Playback",
++		.channels_min = 2,
++		.channels_max = 2,
++		.rates = SNDRV_PCM_RATE_8000_192000,
++		.formats = DLV4780_FORMATS,
++	},
++	.capture = {
++		.stream_name = "Capture",
++		.channels_min = 2,
++		.channels_max = 2,
++		.rates = SNDRV_PCM_RATE_8000_192000,
++		.formats = DLV4780_FORMATS,
++	},
++	.ops = &icdc_d3_dai_ops,
++};
++
++/* unit: 0.01dB */
++static const DECLARE_TLV_DB_SCALE(dac_tlv, -3100, 100, 0);
++static const DECLARE_TLV_DB_SCALE(mix_tlv, -3100, 100, 0);
++static const DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0);
++static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 100, 0);
++
++static const unsigned int icdc_d3_adc_mic_sel_value[] = {0x0, 0x1,};
++static const unsigned int icdc_d3_mixer_input_sel_value[] = {0x0, 0x5, 0xa, 0xf,};
++static const unsigned int icdc_d3_mixer_input_sel_value_double[] = {0x0, 0x1, 0x2, 0x3,};
++static const unsigned int icdc_d3_mixer_mode_sel_value[] = {0x0, 0x1,};
++
++static const char *icdc_d3_mixer_input_sel[] = { "Normal Inputs", "Cross Inputs", "Mixed Inputs", "Zero Inputs"};
++static const char *icdc_d3_adc_mic_sel[] = { "AMIC ON", "DMIC ON"};
++static const char *icdc_d3_mercury_vir_sel[] = { "MERCURY ON", "MERCURY OFF"};
++static const char *icdc_d3_titanium_vir_sel[] = { "TITANIUM ON", "TITANIUM OFF"};
++static const char *icdc_d3_dac_mixer_mode_sel[] = { "PLAYBACK DAC", "PLAYBACK DAC + ADC"};
++static const char *icdc_d3_adc_mixer_mode_sel[] = { "RECORD INPUT", "RECORD INPUT + DAC"};
++
++static const struct soc_enum icdc_d3_enum[] = {
++	SOC_VALUE_ENUM_SINGLE(SCODA_REG_CR_ADC, 6, 0x1,  ARRAY_SIZE(icdc_d3_adc_mic_sel),icdc_d3_adc_mic_sel, icdc_d3_adc_mic_sel_value), /*0*/
++	SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(icdc_d3_mercury_vir_sel), icdc_d3_mercury_vir_sel), /*1*/
++	SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(icdc_d3_titanium_vir_sel), icdc_d3_titanium_vir_sel), /*2*/
++
++	/*select input method*/
++	SOC_VALUE_ENUM_DOUBLE(SCODA_MIX_0, 6, 4, 0x3,  ARRAY_SIZE(icdc_d3_mixer_input_sel),icdc_d3_mixer_input_sel, icdc_d3_mixer_input_sel_value_double), /*3*/
++	SOC_VALUE_ENUM_DOUBLE(SCODA_MIX_1, 6, 4, 0x3,  ARRAY_SIZE(icdc_d3_mixer_input_sel),icdc_d3_mixer_input_sel, icdc_d3_mixer_input_sel_value_double), /*4*/
++	SOC_VALUE_ENUM_DOUBLE(SCODA_MIX_2, 6, 4, 0x3,  ARRAY_SIZE(icdc_d3_mixer_input_sel),icdc_d3_mixer_input_sel, icdc_d3_mixer_input_sel_value_double),/*5*/
++	SOC_VALUE_ENUM_DOUBLE(SCODA_MIX_3, 6,4, 0x3,  ARRAY_SIZE(icdc_d3_mixer_input_sel),icdc_d3_mixer_input_sel, icdc_d3_mixer_input_sel_value_double),/*6*/
++	SOC_VALUE_ENUM_SINGLE(SCODA_MIX_4, 4, 0xf,  ARRAY_SIZE(icdc_d3_mixer_input_sel),icdc_d3_mixer_input_sel, icdc_d3_mixer_input_sel_value),/*7*/
++
++	/*select mix mode*/
++	SOC_VALUE_ENUM_SINGLE(SCODA_MIX_0, 0, 1,  ARRAY_SIZE(icdc_d3_dac_mixer_mode_sel),icdc_d3_dac_mixer_mode_sel, icdc_d3_mixer_mode_sel_value),/*8*/
++	SOC_VALUE_ENUM_SINGLE(SCODA_MIX_4, 0, 1,  ARRAY_SIZE(icdc_d3_dac_mixer_mode_sel),icdc_d3_dac_mixer_mode_sel, icdc_d3_mixer_mode_sel_value),/*9*/
++	SOC_VALUE_ENUM_SINGLE(SCODA_MIX_2, 0, 1,  ARRAY_SIZE(icdc_d3_adc_mixer_mode_sel),icdc_d3_adc_mixer_mode_sel, icdc_d3_mixer_mode_sel_value),/*10*/
++
++	SOC_VALUE_ENUM_SINGLE(SCODA_MIX_2, 6, 0x3,  ARRAY_SIZE(icdc_d3_mixer_input_sel),icdc_d3_mixer_input_sel, icdc_d3_mixer_input_sel_value),/*11*/
++	SOC_VALUE_ENUM_SINGLE(SCODA_MIX_2, 4, 0x3,  ARRAY_SIZE(icdc_d3_mixer_input_sel),icdc_d3_mixer_input_sel, icdc_d3_mixer_input_sel_value),/*12*/
++};
++
++
++static const struct snd_kcontrol_new icdc_d3_adc_controls =
++	SOC_DAPM_ENUM("Route",  icdc_d3_enum[0]);
++
++static const struct snd_kcontrol_new icdc_d3_mercury_vmux_controls =
++	SOC_DAPM_ENUM("Route", icdc_d3_enum[1]);
++
++static const struct snd_kcontrol_new icdc_d3_titanium_vmux_controls =
++	SOC_DAPM_ENUM("Route", icdc_d3_enum[2]);
++
++static const struct snd_kcontrol_new icdc_d3_mercury_aidac_input_sel_controls =
++	SOC_DAPM_ENUM("Route", icdc_d3_enum[3]);
++
++static const struct snd_kcontrol_new icdc_d3_dac_input_sel_controls =
++	SOC_DAPM_ENUM("Route", icdc_d3_enum[4]);
++
++static const struct snd_kcontrol_new icdc_d3_aiadc_input_sel_controls =
++	SOC_DAPM_ENUM("Route", icdc_d3_enum[5]);
++
++static const struct snd_kcontrol_new icdc_d3_adc_input_sel_controls =
++	SOC_DAPM_ENUM("Route", icdc_d3_enum[6]);
++
++static const struct snd_kcontrol_new icdc_d3_titanium_aidac_input_sel_controls =
++	SOC_DAPM_ENUM("Route", icdc_d3_enum[7]);
++
++static const struct snd_kcontrol_new icdc_d3_mercury_mixer_mode_sel_controls =
++	SOC_DAPM_ENUM("Route", icdc_d3_enum[8]);
++
++static const struct snd_kcontrol_new icdc_d3_titanium_mixer_mode_sel_controls =
++	SOC_DAPM_ENUM("Route", icdc_d3_enum[9]);
++
++static const struct snd_kcontrol_new icdc_d3_aiadc_mixer_mode_sel_controls =
++	SOC_DAPM_ENUM("Route", icdc_d3_enum[10]);
++
++static const struct snd_kcontrol_new icdc_d3_aiadc_input_sel_controls_l =
++	SOC_DAPM_ENUM("Route", icdc_d3_enum[11]);
++
++static const struct snd_kcontrol_new icdc_d3_aiadc_input_sel_controls_r =
++	SOC_DAPM_ENUM("Route", icdc_d3_enum[12]);
++
++static const struct snd_kcontrol_new icdc_d3_snd_controls[] = {
++	/* Volume controls */
++	SOC_DOUBLE_R_TLV("MERCURY Playback Volume", SCODA_REG_GCR_DACL, SCODA_REG_GCR_DACR, 0, 63, 0, dac_tlv),
++	SOC_DOUBLE_R_TLV("TITANIUM Playback Volume", SCODA_REG_GCR_DACL, SCODA_REG_GCR_DACR, 0, 63, 0, dac_tlv),
++	SOC_DOUBLE_R_TLV("Playback Mixer Volume", SCODA_REG_GCR_MIXDACL, SCODA_REG_GCR_MIXDACR, 0, 31, 1, mix_tlv),
++	SOC_DOUBLE_R_TLV("Digital Capture Volume", SCODA_REG_GCR_ADCL, SCODA_REG_GCR_ADCR, 0, 43, 0, adc_tlv),
++	SOC_DOUBLE_R_TLV("Digital Capture Mixer Volume", SCODA_REG_GCR_MIXADCL, SCODA_REG_GCR_MIXADCR, 0, 31, 1, mix_tlv),
++	SOC_SINGLE_TLV("Mic Volume", SCODA_REG_GCR_MIC1, 0, 4, 0, mic_tlv),
++
++	/* ADC private controls */
++	SOC_SINGLE("ADC High Pass Filter Switch", SCODA_REG_FCR_ADC, 6, 1, 0),
++
++	/* mic private controls */
++	SOC_SINGLE("Digital Playback mute", SCODA_REG_CR_DAC, 7, 1, 0),
++	/* mixer enable controls */
++	SOC_SINGLE("mixer Enable", SCODA_REG_CR_MIX, 7, 1, 0),
++};
++
++static const struct snd_soc_dapm_widget icdc_d3_dapm_widgets[] = {
++/* ADC */
++	SND_SOC_DAPM_ADC("ADC", "Capture" , SCODA_REG_AICR_ADC, 4, 1),
++	SND_SOC_DAPM_MUX("ADC Mux", SCODA_REG_CR_ADC, 4, 1, &icdc_d3_adc_controls),
++	SND_SOC_DAPM_MICBIAS("MICBIAS", SCODA_REG_CR_MIC1, 5, 1),
++	SND_SOC_DAPM_PGA("AMIC", SCODA_REG_CR_MIC1, 4, 1, NULL, 0),
++	SND_SOC_DAPM_PGA("DMIC", SCODA_REG_CR_DMIC, 7, 0, NULL, 0),
++
++/* DAC */
++	SND_SOC_DAPM_DAC("DAC", "Playback", SCODA_REG_AICR_DAC, 4, 1),
++
++	SND_SOC_DAPM_MUX("DAC_MERCURY VMux", SND_SOC_NOPM, 0, 0, &icdc_d3_mercury_vmux_controls),
++	SND_SOC_DAPM_PGA("DAC_MERCURY", SCODA_REG_CR_DAC, 4, 1, NULL, 0),
++
++/*	SND_SOC_DAPM_MUX("DAC_TITANIUM VMux", SND_SOC_NOPM, 0, 0, &icdc_d3_titanium_vmux_controls),*/
++/*	SND_SOC_DAPM_PGA("DAC_TITANIUM", SCODA_REG_CR_DAC2, 4, 1, NULL, 0),*/
++
++/* MIXER */
++	SND_SOC_DAPM_MUX("MERCURY AIDAC MIXER Mux", SND_SOC_NOPM, 0, 0, &icdc_d3_dac_input_sel_controls),
++	SND_SOC_DAPM_MUX("DAC Mode Mux", SND_SOC_NOPM, 0, 0, &icdc_d3_mercury_mixer_mode_sel_controls),
++	SND_SOC_DAPM_MUX("MERCURY AIDAC Mux", SND_SOC_NOPM, 0, 0, &icdc_d3_mercury_aidac_input_sel_controls),
++
++/* ADC */
++	SND_SOC_DAPM_MUX("ADC Mode Mux", SND_SOC_NOPM, 0, 0, &icdc_d3_aiadc_mixer_mode_sel_controls),
++	SND_SOC_DAPM_MUX("AIADC Mux", SND_SOC_NOPM, 0, 0, &icdc_d3_aiadc_input_sel_controls),
++	SND_SOC_DAPM_MUX("AIADC Mux L", SND_SOC_NOPM, 0, 0, &icdc_d3_aiadc_input_sel_controls_l),
++	SND_SOC_DAPM_MUX("AIADC Mux R", SND_SOC_NOPM, 0, 0, &icdc_d3_aiadc_input_sel_controls_r),
++	SND_SOC_DAPM_MUX("ADC MIXER Mux", SND_SOC_NOPM, 0, 0, &icdc_d3_adc_input_sel_controls),
++
++/* PINS */
++	SND_SOC_DAPM_INPUT("AIP"),
++	SND_SOC_DAPM_INPUT("AIN"),
++	SND_SOC_DAPM_INPUT("DMIC IN"),
++	SND_SOC_DAPM_OUTPUT("DO_LO_PWM"),
++	SND_SOC_DAPM_OUTPUT("DO_BO_PWM"),
++};
++
++static const struct snd_soc_dapm_route intercon[] = {
++
++	{ "MICBIAS",  NULL,  "AIP" },
++	{ "MICBIAS",  NULL,  "AIN" },
++	{ "AMIC",  NULL,  "MICBIAS" },
++	{ "AMIC",  NULL,  "MICBIAS" },
++
++	/*input*/
++	{ "ADC Mux", "AMIC ON", "AMIC" },
++	{ "ADC Mux", "DMIC ON", "DMIC IN" },
++
++	{ "ADC Mode Mux" , "RECORD INPUT","ADC Mux"},
++	{ "ADC Mode Mux" , "RECORD INPUT + DAC","ADC Mux"},
++
++	{ "AIADC Mux" , "Normal Inputs","ADC Mode Mux"},
++	{ "AIADC Mux" , "Cross Inputs","ADC Mode Mux"},
++	{ "AIADC Mux" , "Mixed Inputs","ADC Mode Mux"},
++	{ "AIADC Mux" , "Zero Inputs","ADC Mode Mux"},
++	{ "AIADC Mux L" , "Normal Inputs","ADC Mode Mux"},
++	{ "AIADC Mux L" , "Cross Inputs","ADC Mode Mux"},
++	{ "AIADC Mux L" , "Mixed Inputs","ADC Mode Mux"},
++	{ "AIADC Mux L" , "Zero Inputs","ADC Mode Mux"},
++	{ "AIADC Mux R" , "Normal Inputs","ADC Mode Mux"},
++	{ "AIADC Mux R" , "Cross Inputs","ADC Mode Mux"},
++	{ "AIADC Mux R" , "Mixed Inputs","ADC Mode Mux"},
++	{ "AIADC Mux R" , "Zero Inputs","ADC Mode Mux"},
++
++	{ "ADC", NULL, "AIADC Mux" },
++	{ "ADC", NULL, "AIADC Mux L" },
++	{ "ADC", NULL, "AIADC Mux R" },
++
++	{ "ADC MIXER Mux" , "Normal Inputs","ADC Mux"},
++	{ "ADC MIXER Mux" , "Cross Inputs","ADC Mux"},
++	{ "ADC MIXER Mux" , "Mixed Inputs","ADC Mux"},
++	{ "ADC MIXER Mux" , "Zero Inputs","ADC Mux"},
++
++	{"DAC Mode Mux", NULL, "ADC MIXER Mux"},
++	/*output*/
++	{ "DAC_MERCURY"  , NULL, "DAC" },
++	{ "DAC_MERCURY VMux"  , "MERCURY ON"  , "DAC_MERCURY" },
++
++	/* select mixer inputs*/
++	{"MERCURY AIDAC MIXER Mux", "Normal Inputs", "DAC_MERCURY VMux"},
++	{"MERCURY AIDAC MIXER Mux", "Cross Inputs", "DAC_MERCURY VMux"},
++	{"MERCURY AIDAC MIXER Mux", "Mixed Inputs", "DAC_MERCURY VMux"},
++	{"MERCURY AIDAC MIXER Mux", "Zero Inputs", "DAC_MERCURY VMux"},
++
++	/*select mixer mode*/
++	{"DAC Mode Mux", "PLAYBACK DAC", "DAC_MERCURY VMux"},
++	{"DAC Mode Mux", "PLAYBACK DAC + ADC", "MERCURY AIDAC MIXER Mux"},
++
++	/*	DAC_MERCURY Vmux->DAC Mux*/
++	/*select mixer output channels*/
++	{ "MERCURY AIDAC Mux"  , "Normal Inputs"  , "DAC Mode Mux" },
++	{ "MERCURY AIDAC Mux"  , "Cross Inputs"  , "DAC Mode Mux" },
++	{ "MERCURY AIDAC Mux"  , "Mixed Inputs"  , "DAC Mode Mux" },
++	{ "MERCURY AIDAC Mux"  , "Zero Inputs"  , "DAC Mode Mux" },
++
++	{ "DO_LO_PWM", NULL, "MERCURY AIDAC Mux" },
++};
++
++#ifdef CONFIG_PM
++static int icdc_d3_suspend(struct snd_soc_codec *codec)
++{
++	struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
++
++	snd_soc_update_bits(codec, SCODA_REG_AICR_ADC, SCODA_AICR_ADC_SB_MASK, 1);
++	snd_soc_update_bits(codec, SCODA_REG_AICR_DAC, SCODA_AICR_DAC_SB_MASK, 1);
++	snd_soc_update_bits(codec, SCODA_REG_CR_VIC, SCODA_CR_VIC_SB_SLEEP_MASK, 1);
++	snd_soc_update_bits(codec, SCODA_REG_CR_VIC, SCODA_CR_VIC_SB_MASK, 1);
++	snd_soc_update_bits(codec, SCODA_REG_CR_CK, SCODA_CR_CK_SDCLK_MASK, 1);
++	snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_OFF);
++	return 0;
++}
++
++static int icdc_d3_resume(struct snd_soc_codec *codec)
++{
++	struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
++
++	snd_soc_update_bits(codec, SCODA_REG_CR_CK, SCODA_CR_CK_SDCLK_MASK, 0);
++
++	if (snd_soc_update_bits(codec, SCODA_REG_CR_VIC, SCODA_CR_VIC_SB_MASK, 0))
++		msleep(250);
++	if (snd_soc_update_bits(codec, SCODA_REG_CR_VIC, SCODA_CR_VIC_SB_SLEEP_MASK, 0)) {
++		msleep(10);
++	}
++	snd_soc_update_bits(codec, SCODA_REG_AICR_ADC, SCODA_AICR_ADC_SB_MASK, 0);
++	snd_soc_update_bits(codec, SCODA_REG_AICR_DAC, SCODA_AICR_DAC_SB_MASK, 0);
++	snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_STANDBY);
++	return 0;
++}
++#endif
++
++static int icdc_d3_probe(struct snd_soc_codec *codec)
++{
++	struct icdc_d3 *icdc_d3 = snd_soc_codec_get_drvdata(codec);
++	dev_info(codec->dev, "codec icdc-d3 probe enter\n");
++
++	/* power off codec */
++	snd_soc_update_bits(codec, SCODA_REG_CR_VIC, SCODA_CR_VIC_SB_SLEEP_MASK, 1);
++	snd_soc_update_bits(codec, SCODA_REG_CR_VIC, SCODA_CR_VIC_SB_MASK, 1);
++
++#ifdef DEBUG
++	/*dump for debug*/
++	dump_registers_hazard(icdc_d3);
++#endif
++	/* codec select enable 24M clock*/
++	snd_soc_update_bits(codec, SCODA_REG_CR_CK , SCODA_CR_CK_MCLK_DIV_MASK, 1 << SCODA_CR_CK_MCLK_DIV_SHIFT);
++	snd_soc_update_bits(codec, SCODA_REG_CR_CK , SCODA_CR_CK_SDCLK_MASK, 0 << SCODA_CR_CK_SDCLK_SHIFT);
++	snd_soc_update_bits(codec, SCODA_REG_CR_CK , SCODA_CR_CRYSTAL_MASK, 0 << SCODA_CR_CRYSTAL_SHIFT);
++
++	/*codec select Dac/Adc i2s interface*/
++	snd_soc_update_bits(codec,SCODA_REG_AICR_DAC, SCODA_AICR_DAC_SLAVE_MASK, 0);
++	snd_soc_update_bits(codec,SCODA_REG_AICR_DAC, SCODA_AICR_DAC_AUDIO_MASK, SCODA_AICR_DAC_AUDIOIF_I2S);
++
++	/*codec generated IRQ is a high level */
++	snd_soc_update_bits(codec, SCODA_REG_ICR, SCODA_ICR_INT_FORM_MASK, SCODA_ICR_INT_FORM_LOW);
++
++	/*codec irq mask*/
++	snd_soc_write(codec, SCODA_REG_IMR, SCODA_IMR_COMMON_MASK);
++	snd_soc_write(codec, SCODA_REG_IMR2, SCODA_IMR2_COMMON_MASK);
++
++	/*codec clear all irq*/
++	snd_soc_write(codec, SCODA_REG_IFR, SCODA_IMR_COMMON_MASK);
++	snd_soc_write(codec, SCODA_REG_IFR2, SCODA_IMR2_COMMON_MASK);
++
++	icdc_d3_write(codec, SCODA_MIX_3, 0x5 << 4);
++	icdc_d3_write(codec, SCODA_MIX_2, 0x1 << 4);
++
++	icdc_d3->codec = codec;
++	return 0;
++}
++
++static int icdc_d3_remove(struct snd_soc_codec *codec)
++{
++	struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
++	dev_info(codec->dev, "codec icdc_d3 remove enter\n");
++	snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_OFF);
++	return 0;
++}
++
++static struct snd_soc_codec_driver soc_codec_dev_icdc_d3_codec = {
++	.probe = 	icdc_d3_probe,
++	.remove = 	icdc_d3_remove,
++#ifdef CONFIG_PM
++	.suspend =	icdc_d3_suspend,
++	.resume =	icdc_d3_resume,
++#endif
++
++	.read = 	icdc_d3_read,
++	.write = 	icdc_d3_write,
++	.reg_cache_default = icdc_d3_reg_defcache,
++	.reg_word_size = sizeof(u8),
++	.reg_cache_step = 1,
++	.reg_cache_size = SCODA_MAX_REG_NUM,
++
++	.controls = 	icdc_d3_snd_controls,
++	.num_controls = ARRAY_SIZE(icdc_d3_snd_controls),
++	.dapm_widgets = icdc_d3_dapm_widgets,
++	.num_dapm_widgets = ARRAY_SIZE(icdc_d3_dapm_widgets),
++	.dapm_routes = intercon,
++	.num_dapm_routes = ARRAY_SIZE(intercon),
++};
++
++/*Just for debug*/
++static ssize_t hw_regs_show(struct device *dev,
++		struct device_attribute *attr, char *buf)
++{
++	struct icdc_d3 *icdc_d3 = dev_get_drvdata(dev);
++	struct snd_soc_codec *codec = icdc_d3->codec;
++	if (!codec) {
++		dev_info(dev, "icdc_d3 is not probe, can not use %s function\n", __func__);
++		return 0;
++	}
++	mutex_lock(&codec->component.io_mutex);
++	dump_registers_hazard(icdc_d3);
++	mutex_unlock(&codec->component.io_mutex);
++	return 0;
++}
++
++static ssize_t hw_regs_store(struct device *dev,
++		struct device_attribute *attr, const char *buf,
++		size_t count)
++{
++	struct icdc_d3 *icdc_d3 = dev_get_drvdata(dev);
++	struct snd_soc_codec *codec = icdc_d3->codec;
++	const char *start = buf;
++	unsigned int reg, val;
++	int ret_count = 0;
++
++	if (!codec) {
++		dev_info(dev, "icdc_d3 is not probe, can not use %s function\n", __func__);
++		return count;
++	}
++
++	while(!isxdigit(*start)) {
++		start++;
++		if (++ret_count >= count)
++			return count;
++	}
++	reg = simple_strtoul(start, (char **)&start, 16);
++	while(!isxdigit(*start)) {
++		start++;
++		if (++ret_count >= count)
++			return count;
++	}
++	val = simple_strtoul(start, (char **)&start, 16);
++	mutex_lock(&codec->component.io_mutex);
++	icdc_d3_write(codec, reg, val);
++	mutex_unlock(&codec->component.io_mutex);
++	return count;
++}
++
++static struct device_attribute icdc_d3_sysfs_attrs =
++	__ATTR_RW(hw_regs);
++
++static int icdc_d3_platform_probe(struct platform_device *pdev)
++{
++	struct device_node *parent = of_get_parent(pdev->dev.of_node);
++	struct icdc_d3 *icdc_d3 = NULL;
++	int ret = 0;
++
++	icdc_d3 = (struct icdc_d3*)devm_kzalloc(&pdev->dev,
++			sizeof(struct icdc_d3), GFP_KERNEL);
++	if (!icdc_d3)
++		return -ENOMEM;
++
++	icdc_d3->mapped_base = of_iomap(parent, 0);
++	if (IS_ERR(icdc_d3->mapped_base)) {
++		dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
++		return PTR_ERR(icdc_d3->mapped_base);
++	}
++
++	icdc_d3->dev = &pdev->dev;
++	icdc_d3->dac_user_mute = 1;
++	icdc_d3->aohp_in_pwsq = 0;
++	spin_lock_init(&icdc_d3->io_lock);
++	platform_set_drvdata(pdev, (void *)icdc_d3);
++
++	ret = snd_soc_register_codec(&pdev->dev,
++			&soc_codec_dev_icdc_d3_codec, &icdc_d3_codec_dai, 1);
++	if (ret) {
++		dev_err(&pdev->dev, "Faild to register codec\n");
++		platform_set_drvdata(pdev, NULL);
++		return ret;
++	}
++
++	ret = device_create_file(&pdev->dev, &icdc_d3_sysfs_attrs);
++	dev_info(&pdev->dev, "codec icdc-d3 platfrom probe success\n");
++	return 0;
++}
++
++static int icdc_d3_platform_remove(struct platform_device *pdev)
++{
++	dev_info(&pdev->dev, "codec icdc-d3 platform remove\n");
++	snd_soc_unregister_codec(&pdev->dev);
++	platform_set_drvdata(pdev, NULL);
++	return 0;
++}
++
++static const struct of_device_id codec_dt_match[] = {
++	{ .compatible = "ingenic,icdc3", .data = NULL },
++	{},
++};
++MODULE_DEVICE_TABLE(of, codec_dt_match);
++
++static struct platform_driver icdc_d3_codec_driver = {
++	.driver = {
++		.name = "icdc-d3",
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(codec_dt_match),
++	},
++	.probe = icdc_d3_platform_probe,
++	.remove = icdc_d3_platform_remove,
++};
++
++static int icdc_d3_modinit(void)
++{
++	return platform_driver_register(&icdc_d3_codec_driver);
++}
++module_init(icdc_d3_modinit);
++
++static void icdc_d3_exit(void)
++{
++	platform_driver_unregister(&icdc_d3_codec_driver);
++}
++module_exit(icdc_d3_exit);
++
++MODULE_DESCRIPTION("iCdc d3 Codec Driver");
++MODULE_AUTHOR("sccheng<shicheng.cheng@ingenic.com>");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/sound/soc/ingenic/icodec/icdc_d3.h b/module_drivers/sound/soc/ingenic/icodec/icdc_d3.h
+new file mode 100644
+index 000000000..6224a1db3
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/icodec/icdc_d3.h
+@@ -0,0 +1,407 @@
++/*
++ * sound/soc/ingenic/icodec/icdc_d3.h
++ * ALSA SoC Audio driver -- ingenic internal codec (icdc_d3) driver
++
++ * Copyright 2015 Ingenic Semiconductor Co.,Ltd
++ *	cli <chen.li@ingenic.com>
++ *
++ * Note: icdc_d3 is an internal codec for ingenic SOC
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++
++#ifndef __ICDC_D3_REG_H__
++#define __ICDC_D3_REG_H__
++
++#include <linux/spinlock.h>
++#include <sound/soc.h>
++#include "../as-v1/asoc-aic.h"
++
++struct icdc_d3 {
++	struct device		*dev;		/*aic device used to access register*/
++	struct snd_soc_codec	*codec;
++	spinlock_t       io_lock;		/*codec hw io lock,
++							  Note codec cannot opt in irq context*/
++	void * __iomem mapped_base;				/*vir addr*/
++	resource_size_t mapped_resstart;				/*resource phy addr*/
++	resource_size_t mapped_ressize;				/*resource phy addr size*/
++
++	int dac_user_mute;				/*dac user mute state*/
++	/*aohp power on anti pop event*/
++	volatile int aohp_in_pwsq;				/*aohp in power up/down seq*/
++	int hpl_wished_gain;				/*keep original hpl/r gain register value*/
++	int hpr_wished_gain;
++	int linl_wished_gain;				/*keep original hpl/r gain register value*/
++	int linr_wished_gain;
++	/*codec irq*/
++	int irqno;
++	int irqflags;
++	int codec_imr;
++	struct work_struct irq_work;
++	/*headphone detect*/
++	struct snd_soc_jack *jack;
++	int report_mask;
++};
++
++/*
++ * Note: icdc_d3 codec just only support detect headphone jack
++ * detected_type: detect event treat as detected_type
++ *	 example: SND_JACK_HEADSET detect event treat as SND_JACK_HEADSET
++ */
++int icdc_d3_hp_detect(struct snd_soc_codec *codec,
++		struct snd_soc_jack *jack, int detected_type);
++
++/*  icdc_d3 internal register space */
++enum {
++	SCODA_REG_SR = 0x0,
++	SCODA_REG_SR2,
++	SCODA_REG_SIGR,
++	SCODA_REG_SIGR2,
++	SCODA_REG_SIGR3,
++	SCODA_REG_SIGR5,
++	SCODA_REG_SIGR7,
++	SCODA_REG_MR,
++	SCODA_REG_AICR_DAC,
++	SCODA_REG_AICR_ADC,
++	SCODA_REG_CR_DMIC,
++	SCODA_REG_CR_MIC1,
++	SCODA_REG_CR_MIC2,
++	SCODA_REG_CR_DAC,
++	SCODA_REG_CR_DAC2,
++	SCODA_REG_CR_ADC,
++	SCODA_REG_CR_MIX,
++	SCODA_REG_DR_MIX,
++	SCODA_REG_CR_VIC,
++	SCODA_REG_CR_CK,
++	SCODA_REG_FCR_DAC,
++	SCODA_REG_SFCCR_DAC,
++	SCODA_REG_SFFCR_DAC,
++	SCODA_REG_FCR_ADC,
++	SCODA_REG_CR_TIMER_MSB,
++	SCODA_REG_CR_TIMER_LSB,
++	SCODA_REG_ICR,
++	SCODA_REG_IMR,
++	SCODA_REG_IFR,
++	SCODA_REG_IMR2,
++	SCODA_REG_IFR2,
++	SCODA_REG_GCR_DACL,
++	SCODA_REG_GCR_DACR,
++	SCODA_REG_GCR_DACL2,
++	SCODA_REG_GCR_DACR2,
++	SCODA_REG_GCR_MIC1,
++	SCODA_REG_GCR_MIC2,
++	SCODA_REG_GCR_ADCL,
++	SCODA_REG_GCR_ADCR,
++	SCODA_REG_GCR_MIXDACL,
++	SCODA_REG_GCR_MIXDACR,
++	SCODA_REG_GCR_MIXADCL,
++	SCODA_REG_GCR_MIXADCR,
++	SCODA_REG_CR_DAC_AGC,
++	SCODA_REG_DR_DAC_AGC,
++	SCODA_REG_CR_DAC2_AGC,
++	SCODA_REG_DR_DAC2_AGC,
++	SCODA_REG_CR_ADC_AGC,
++	SCODA_REG_DR_ADC_AGC,
++	SCODA_REG_SR_ADC_AGCDGL,
++	SCODA_REG_SR_ADC_AGCDGR,
++	SCODA_REG_SR_ADC_AGCAGL,
++	SCODA_REG_SR_ADC_AGCAGR,
++	SCODA_REG_CR_TR,
++	SCODA_REG_DR_TR,
++	SCODA_REG_SR_TR1,
++	SCODA_REG_SR_TR2,
++	SCODA_REG_SR_TR_SRCDAC,
++
++/*  icdc_d3 internal register extend space */
++	SCODA_MIX_0,
++	SCODA_MIX_1,
++	SCODA_MIX_2,
++	SCODA_MIX_3,
++	SCODA_MIX_4,
++
++	SCODA_DAC_AGC0,
++	SCODA_DAC_AGC1,
++	SCODA_DAC_AGC2,
++	SCODA_DAC_AGC3,
++
++	SCODA_DAC2_AGC0,
++	SCODA_DAC2_AGC1,
++	SCODA_DAC2_AGC2,
++	SCODA_DAC2_AGC3,
++
++	SCODA_ADC_AGC0,
++	SCODA_ADC_AGC1,
++	SCODA_ADC_AGC2,
++	SCODA_ADC_AGC3,
++	SCODA_ADC_AGC4,
++	SCODA_MAX_REG_NUM,
++};
++
++/*aicr dac*/
++#define SCODA_AICR_DAC_ADWL_SHIFT (6)
++#define SCODA_AICR_DAC_ADWL_MASK (0x3 << SCODA_AICR_DAC_ADWL_SHIFT)
++#define SCODA_AICR_DAC_SLAVE_SHIFT (5)
++#define SCODA_AICR_DAC_SLAVE_MASK (0x1 << SCODA_AICR_DAC_SLAVE_SHIFT)
++#define SCODA_AICR_DAC_SLAVE (1 << 5)
++#define SCODA_AICR_DAC_SB_SHIFT (4)
++#define SCODA_AICR_DAC_SB_MASK (0x1 << SCODA_AICR_DAC_SB_SHIFT)
++#define SCODA_AICR_DAC_AUDIOIF_SHIFT (0)
++#define SCODA_AICR_DAC_AUDIO_MASK (0x3 << SCODA_AICR_DAC_AUDIOIF_SHIFT)
++#define SCODA_AICR_DAC_AUDIOIF_I2S (0x3)
++
++/* aicr adc */
++#define SCODA_AICR_ADC_ADWL_SHIFT (6)
++#define SCODA_AICR_ADC_ADWL_MASK (0x3 << SCODA_AICR_ADC_ADWL_SHIFT)
++#define SCODA_AICR_ADC_SB_SHIFT (4)
++#define SCODA_AICR_ADC_SB_MASK (0x1 << SCODA_AICR_ADC_SB_SHIFT)
++#define SCODA_AICR_ADC_AUDIOIF_SHIFT (0)
++#define SCODA_AICR_ADC_AUDIO_MASK (0x3 << SCODA_AICR_ADC_AUDIOIF_SHIFT)
++#define SCODA_AICR_ADC_AUDIOIF_I2S (0x3)
++
++/* cr vic */
++#define SCODA_CR_VIC_SB_SHIFT (0)
++#define SCODA_CR_VIC_SB_MASK (1 << SCODA_CR_VIC_SB_SHIFT)
++#define SCODA_CR_VIC_SB_SLEEP_SHIFT (1)
++#define SCODA_CR_VIC_SB_SLEEP_MASK (1 << SCODA_CR_VIC_SB_SLEEP_SHIFT)
++
++/* fcr adc/dac */
++#define SCODA_FCR_FREQ_SHIFT (0)
++#define SCODA_FCR_FREQ_MASK (0xf << SCODA_FCR_FREQ_SHIFT)
++
++/* cr dac */
++#define SCODA_CR_DAC_SMUTE_SHIFT (7)
++#define SCODA_CR_DAC_SMUTE_MASK (0x1 << SCODA_CR_DAC_SMUTE_SHIFT)
++#define SCODA_CR_DAC_SB_SHIFT (4)
++#define SCODA_CR_DAC_SB_MASK (0x1 << SCODA_CR_DAC_SB_SHIFT)
++#define SCODA_CR_DAC_ZERO_SHIFT (0)
++#define SCODA_CR_DAC_ZERO_MASK (0x1 << SCODA_CR_DAC_ZERO_SHIFT)
++
++/* cr dac */
++#define SCODA_CR_ADC_SMUTE_SHIFT (7)
++#define SCODA_CR_ADC_SMUTE_MASK (0x1 << SCODA_CR_ADC_SMUTE_SHIFT)
++#define SCODA_CR_ADC_MIC_SEL_SHIFT (6)
++#define SCODA_CR_ADC_MIC_SEL_MASK (0x1 << SCODA_CR_ADC_MIC_SEL_SHIFT)
++#define SCODA_CR_ADC_SB_SHIFT (4)
++#define SCODA_CR_ADC_SB_MASK (0x1 << SCODA_CR_ADC_SB_SHIFT)
++#define SCODA_CR_ADC_ZERO_SHIFT (0)
++#define SCODA_CR_ADC_ZERO_MASK (0x1 << SCODA_CR_ADC_ZERO_SHIFT)
++
++/* ifr */
++#define SCODA_IFR_DAC_MUTE_SHIFT (0)
++#define SCODA_IFR_DAC_MUTE_MASK (0x1 << SCODA_IFR_DAC_MUTE_SHIFT)
++#define SCODA_IFR_ADC_MUTE_SHIFT (2)
++#define SCODA_IFR_ADC_MUTE_MASK (0x1 << SCODA_IFR_ADC_MUTE_SHIFT)
++#define SCODA_IFR_ADAS_LOCK_SHIFT (7)
++#define SCODA_IFR_ADAS_LOCK_MASK (0x1 << SCODA_IFR_ADAS_LOCK_SHIFT)
++
++/* cr ck */
++#define SCODA_CR_CK_MCLK_DIV_SHIFT (6)
++#define SCODA_CR_CK_MCLK_DIV_MASK (0x1 << SCODA_CR_CK_MCLK_DIV_SHIFT)
++#define SCODA_CR_CK_SDCLK_SHIFT (4)
++#define SCODA_CR_CK_SDCLK_MASK (0x1 << SCODA_CR_CK_SDCLK_SHIFT)
++#define SCODA_CR_CRYSTAL_SHIFT (0)
++#define SCODA_CR_CRYSTAL_MASK (0xf << SCODA_CR_CRYSTAL_SHIFT)
++
++/* icr */
++#define SCODA_ICR_INT_FORM_SHIFT (6)
++#define SCODA_ICR_INT_FORM_MASK (0x3 << SCODA_ICR_INT_FORM_SHIFT)
++#define SCODA_ICR_INT_FORM_HIGH (0)
++#define SCODA_ICR_INT_FORM_LOW  (1)
++
++/* imr */
++#define SCODA_IMR_COMMON_MASK (0xff)
++#define SCODA_IMR2_COMMON_MASK (0xff)
++
++/*For Codec*/
++#define RGADW		(0xA4)
++#define RGDATA		(0xA8)
++
++static inline void icdc_d3_mapped_reg_set(void __iomem * xreg, int xmask, int xval)
++{
++	int val = readl(xreg);
++	val &= ~(xmask);
++	val |= xval;
++	writel(val, xreg);
++}
++
++static inline int icdc_d3_mapped_test_bits(void __iomem * xreg, int xmask, int xval)
++{
++	int val = readl(xreg);
++	val &= xmask;
++	return (val == xval);
++}
++
++/*
++ * RGADW
++ */
++#define SCODA_RGDIN_BIT		(0)
++#define SCODA_RGDIN_MASK		(0xff << SCODA_RGDIN_BIT)
++#define SCODA_RGADDR_BIT		(8)
++#define SCODA_RGADDR_MASK		(0x7f << SCODA_RGADDR_BIT)
++#define SCODA_RGWR_BIT		(16)
++#define SCODA_RGWR_MASK		(0x1  << SCODA_RGWR_BIT)
++
++#define icdc_d3_test_rw_inval(icdc_d3)      \
++	icdc_d3_mapped_test_bits((icdc_d3->mapped_base + RGADW), SCODA_RGWR_MASK, (1 << SCODA_RGWR_BIT))
++/*
++ * RGDATA
++ */
++#define SCODA_RGDOUT_BIT		(0)
++#define SCODA_RGDOUT_MASK		(0xff << SCODA_RGDOUT_BIT)
++#define SCODA_IRQ_BIT		(8)
++#define SCODA_IRQ_MASK		(0x1  << SCODA_IRQ_BIT)
++
++#define icdc_d3_test_irq(icdc_d3)	\
++	icdc_d3_mapped_test_bits((icdc_d3->mapped_base + RGDATA),	\
++			SCODA_IRQ_MASK, (1 << SCODA_IRQ_BIT))
++
++static inline u8 icdc_d3_hw_read_normal(struct icdc_d3 *icdc_d3, int reg)
++{
++	void __iomem * mapped_base = icdc_d3->mapped_base;
++	int reval;
++	int timeout = 0xfffff;
++	unsigned long flags;
++
++	spin_lock_irqsave(&icdc_d3->io_lock, flags);
++
++	while(icdc_d3_test_rw_inval(icdc_d3)) {
++		timeout--;
++		if (!timeout) pr_err("icdc_d3 test_rw_inval timeout\n");
++	}
++
++	icdc_d3_mapped_reg_set((mapped_base + RGADW), SCODA_RGWR_MASK,(0 << SCODA_RGWR_BIT));
++
++	icdc_d3_mapped_reg_set((mapped_base + RGADW), SCODA_RGADDR_MASK,(reg << SCODA_RGADDR_BIT));
++
++	reval = readl((mapped_base + RGDATA));
++	reval = readl((mapped_base + RGDATA));
++	reval = readl((mapped_base + RGDATA));
++	reval = readl((mapped_base + RGDATA));
++	reval = readl((mapped_base + RGDATA));
++	reval = ((reval & SCODA_RGDOUT_MASK) >> SCODA_RGDOUT_BIT);
++//	printk("reg %x = %x\n", reg, reval);
++	spin_unlock_irqrestore(&icdc_d3->io_lock, flags);
++	return (u8) reval;
++}
++
++static inline int icdc_d3_hw_write_normal(struct icdc_d3 *icdc_d3, int reg, int data)
++{
++	void __iomem * mapped_base = icdc_d3->mapped_base;
++	int ret = 0;
++	int timeout = 0xfffff;
++	unsigned long flags;
++
++	spin_lock_irqsave(&icdc_d3->io_lock, flags);
++
++	while(icdc_d3_test_rw_inval(icdc_d3)) {
++		timeout--;
++		if (!timeout) pr_err("icdc_d3 test_rw_inval timeout\n");
++	}
++	icdc_d3_mapped_reg_set((mapped_base + RGADW),SCODA_RGDIN_MASK|SCODA_RGADDR_MASK,
++			(data << SCODA_RGDIN_BIT)|(reg << SCODA_RGADDR_BIT));
++	icdc_d3_mapped_reg_set((mapped_base + RGADW), SCODA_RGWR_MASK , 1 << SCODA_RGWR_BIT);
++	spin_unlock_irqrestore(&icdc_d3->io_lock, flags);
++	if( reg != SCODA_REG_IFR && reg != SCODA_REG_IFR2 ){
++		ret = icdc_d3_hw_read_normal(icdc_d3, reg);
++		if (data != ret){
++			printk("icdc write reg %x err exp %x now is %x\n",reg,data,ret);
++			ret = -1;
++		}
++	}
++	return ret;
++}
++
++static int icdc_d3_hw_write_extend(struct icdc_d3 *icdc_d3, u8 sreg, u8 sdata){
++	int creg, cdata, dreg;
++	switch (sreg) {
++		case SCODA_MIX_0 ... SCODA_MIX_4:
++			creg = SCODA_REG_CR_MIX;
++			dreg = SCODA_REG_DR_MIX;
++			sreg -= SCODA_MIX_0;
++			break;
++		case SCODA_DAC_AGC0 ... SCODA_DAC_AGC3:
++			creg = SCODA_REG_CR_DAC_AGC;
++			dreg = SCODA_REG_DR_DAC_AGC;
++			sreg -= SCODA_DAC_AGC0;
++			break;
++		case SCODA_DAC2_AGC0 ... SCODA_DAC2_AGC3:
++			creg = SCODA_REG_CR_DAC2_AGC;
++			dreg = SCODA_REG_DR_DAC2_AGC;
++			sreg -= SCODA_DAC2_AGC0;
++			break;
++		case SCODA_ADC_AGC0 ... SCODA_ADC_AGC4:
++			creg = SCODA_REG_CR_ADC_AGC;
++			dreg = SCODA_REG_DR_ADC_AGC;
++			sreg -= SCODA_ADC_AGC0;
++			break;
++		default:
++			return 0;
++	}
++	printk("write extend : sreg: %d [0 - 4], creg: %x sdata: %d\n", sreg, creg, sdata);
++
++	cdata = (icdc_d3_hw_read_normal(icdc_d3,creg)&(~0x3f))|((sreg&0x3f)|0x40);
++
++	icdc_d3_hw_write_normal(icdc_d3, creg, cdata);
++	icdc_d3_hw_write_normal(icdc_d3, dreg, sdata);
++	if(sdata!=icdc_d3_hw_read_normal(icdc_d3,dreg))
++		return -1;
++	return 0;
++}
++
++
++static u8 icdc_d3_hw_read_extend(struct icdc_d3 *icdc_d3, u8 sreg)
++{
++	int creg, cdata, dreg, ddata;
++	switch (sreg) {
++
++		case SCODA_MIX_0 ... SCODA_MIX_4:
++			creg = SCODA_REG_CR_MIX;
++			dreg = SCODA_REG_DR_MIX;
++			sreg -= SCODA_MIX_0;
++			break;
++		case SCODA_DAC_AGC0 ... SCODA_DAC_AGC3:
++			creg = SCODA_REG_CR_DAC_AGC;
++			dreg = SCODA_REG_DR_DAC_AGC;
++			sreg -= SCODA_DAC_AGC0;
++			break;
++		case SCODA_DAC2_AGC0 ... SCODA_DAC2_AGC3:
++			creg = SCODA_REG_CR_DAC2_AGC;
++			dreg = SCODA_REG_DR_DAC2_AGC;
++			sreg -= SCODA_DAC2_AGC0;
++			break;
++		case SCODA_ADC_AGC0 ... SCODA_ADC_AGC4:
++			creg = SCODA_REG_CR_ADC_AGC;
++			dreg = SCODA_REG_DR_ADC_AGC;
++			sreg -= SCODA_ADC_AGC0;
++			break;
++		default:
++			return 0;
++	}
++	cdata = (icdc_d3_hw_read_normal(icdc_d3,creg)&(~0x7f))|(sreg&0x3f);
++	icdc_d3_hw_write_normal(icdc_d3, creg, cdata);
++	ddata = icdc_d3_hw_read_normal(icdc_d3, dreg);
++	return (u8) ddata;
++}
++
++
++static inline u8 icdc_d3_hw_read(struct icdc_d3 *icdc_d3, int reg)
++{
++	if (reg > SCODA_REG_SR_TR_SRCDAC)
++		return icdc_d3_hw_read_extend(icdc_d3, reg);
++	else
++		return icdc_d3_hw_read_normal(icdc_d3, reg);
++}
++static inline int icdc_d3_hw_write(struct icdc_d3 *icdc_d3, int reg, int data)
++{
++	if (reg > SCODA_REG_SR_TR_SRCDAC){
++		return icdc_d3_hw_write_extend(icdc_d3, reg, data);
++	} else {
++		return icdc_d3_hw_write_normal(icdc_d3, reg, data);
++	}
++}
++
++
++#endif	/* __ICDC_D3_REG_H__ */
+diff --git a/module_drivers/sound/soc/ingenic/icodec/icdc_inno.c b/module_drivers/sound/soc/ingenic/icodec/icdc_inno.c
+new file mode 100644
+index 000000000..1b0f7334b
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/icodec/icdc_inno.c
+@@ -0,0 +1,906 @@
++/*
++ * sound/soc/ingenic/icodec/icdc_inno.c
++ * ALSA SoC Audio driver -- ingenic internal codec (icodec) driver
++
++ * Copyright 2019 Ingenic Semiconductor Co.,Ltd
++ *	tjyang <taojiang.yang@ingenic.com>
++ *
++ * Note: icodec is an internal codec for ingenic SOC
++ *	 used for x2000 and so on
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/pm.h>
++#include <linux/platform_device.h>
++#include <linux/vmalloc.h>
++#include <linux/slab.h>
++#include <linux/ctype.h>
++#include <linux/io.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++#include <sound/initval.h>
++#include <sound/soc-dai.h>
++#include <linux/of_address.h>
++#include <linux/gpio.h>
++#include <linux/of_gpio.h>
++#include <sound/tlv.h>
++
++
++#define INNO_CODEC_BASE 0xb0020000
++static bool	    inno_codec_master = true;
++
++#define ICODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
++			 SNDRV_PCM_FMTBIT_S20_3LE |SNDRV_PCM_FMTBIT_S24_LE)
++
++
++
++/*icodec for ingenic*/
++#define RESET_REG_00			0x00  /*0x00 * 4*/
++#define ADC_DAC_CONFIG1_02		0x08  /*0x02 * 4*/
++#define ADC_DAC_CONFIG2_03		0x0c  /*0x03 * 4*/
++#define ADC_DAC_CONFIG3_04		0x10  /*0x04 * 4*/
++#define ADC_DAC_CONFIG4_05		0x14  /*0x05 * 4*/
++#define ALC_GAIN_0A			0x28  /*0x0a * 4*/
++#define PRE_DIS_CHARGE_21		0x84  /*0x21 * 4*/
++
++#define CONTROL_REG1_22			0x88  /*0x22 * 4*/
++#define CONTROL_REG2_23			0x8c  /*0x23 * 4*/
++#define CONTROL_REG3_24			0x90  /*0x24 * 4*/
++#define CONTROL_REG4_25			0x94  /*0x25 * 4*/
++#define CONTROL_REG5_26			0x98  /*0x26 * 4*/
++#define CONTROL_REG6_27			0x9c  /*0x27 * 4*/
++#define CONTROL_REG7_28			0xa0  /*0x28 * 4*/
++#define ALG_CONFIG1_44			0x110  /*0x44 * 4*/
++#define ALG_MAXL_45			0x114  /*0x45 * 4*/
++#define ALG_MAXH_46			0x118  /*0x46 * 4*/
++#define ALG_MINL_47			0x11c  /*0x47 * 4*/
++#define ALG_MINH_48			0x120  /*0x48 * 4*/
++#define ALG_CONFIG2_49			0x124  /*0x49 * 4*/
++
++
++static int icodec_mute = 0;    //1:�音； 0:��音
++
++struct icodec {
++	struct device		*dev;
++	struct snd_soc_component	*component;
++	spinlock_t		io_lock;
++	void * __iomem io_base;
++	bool powered;
++	int spk_gpio;
++	unsigned char spk_en_level;
++	unsigned char alcl_gain;
++	unsigned char hpoutl_gain;
++	unsigned char micbias;
++};
++
++typedef void (*p_icodec_playback_power)(bool);
++static p_icodec_playback_power g_icodec_playback_pwr;// playback power control funtion pointer assignment in boards
++
++unsigned int reg_tab[] = {0x00, 0x02, 0x03, 0x4, 0x5, 0x0a, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
++	0x27, 0x28, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49};
++
++void set_playback_pwr_callback(p_icodec_playback_power func)
++{
++	g_icodec_playback_pwr = func;
++}
++EXPORT_SYMBOL(set_playback_pwr_callback);
++
++static unsigned int icodec_read(struct snd_soc_component *component, unsigned int reg)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++	int value = readl(icodec->io_base + reg);
++	return value;
++}
++
++static int icodec_write(struct snd_soc_component *component, unsigned int reg , unsigned value)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++	writel(value ,icodec->io_base + reg);
++	return 0;
++}
++
++void dump_regs(struct snd_soc_component *component)
++{
++	int i;
++	for(i=0; i < ARRAY_SIZE(reg_tab); i++) {
++		printk("reg(0x%x) = 0x%x\n", reg_tab[i], *(volatile unsigned int *)(INNO_CODEC_BASE + 4 * reg_tab[i]));
++	}
++}
++
++
++static void inno_poweron(struct snd_soc_component *component)
++{
++	unsigned int reg = 0x00;
++	int i ;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) ;
++	reg &= ~(3<<0);
++	reg |= (1<<0);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) = reg;
++
++	reg  = 0x01;
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x21*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x22*4) ;
++	reg |= (1<<5);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x22*4) = reg;
++
++	for(i = 0; i < 0x100; i++) {
++		*(volatile unsigned int *)(INNO_CODEC_BASE + 0x21*4) = i;
++		udelay(200);
++	}
++}
++
++static int inno_dac_configure(struct snd_soc_component *component,
++			struct snd_pcm_hw_params *params)
++{
++	int fmt_width = snd_pcm_format_width(params_format(params));
++	unsigned int reg = 0x00;
++
++	reg = 0x02;
++	if(fmt_width > 16) {
++		reg |= (0x3 << 2);
++	} else if(fmt_width > 8) {
++		reg |= (0x0 << 2);
++	}
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x05*4) = reg;
++
++	reg = 0x10;
++	if(fmt_width == 32) {
++		reg |= (0x3 << 5);
++	} else if(fmt_width == 24) {
++		reg |= (0x2 << 5);
++	} else if(fmt_width == 20)  {
++		reg |= (0x1 << 5);
++	} else if(fmt_width == 16){
++		reg |= (0x0 << 5);
++	} else {
++		dev_err(component->dev, "icodec not support format width\n");
++		return -EINVAL;
++	}
++	reg |= (0x1 << 2);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x04*4) = reg;
++
++	return 0;
++}
++
++static void inno_dac_enable (struct snd_soc_component *component)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++	unsigned int reg = 0x00;
++
++	/* mdelay(30); */
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) = 0;
++	/* mdelay(30); */
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) ;
++	reg |= (1<<3);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) ;
++	reg |= (1<<2);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) = reg;
++
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) ;
++	reg &= ~(3<<0);
++	reg |= (2<<0);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) = reg;
++
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) ;
++	reg |= (1<<5);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) ;
++	reg |= (1<<6);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) = reg;
++
++
++/***3*/
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x27*4) ;
++	reg |= (1<<7);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x27*4) = reg;
++
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x27*4) ;
++	reg |= (1<<6);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x27*4) = reg;
++
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x27*4) ;
++	reg |= (1<<5);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x27*4) = reg;
++
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x27*4) ;
++	reg |= (1<<4);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x27*4) = reg;
++
++
++/***4*/
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) ;
++	reg |= (1<<7);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) = reg;
++
++/***5*/
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) ;
++	reg &= ~(0x1f<<0);
++	reg |= (icodec->hpoutl_gain << 0);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) = reg;
++}
++
++static void inno_dac_disable (struct snd_soc_component *component)
++{
++	unsigned int reg = 0x00;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) ;
++	reg &= ~(0x1f<<0);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) ;
++	reg &= ~(0x1<<7);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) ;
++	reg &= ~(0x1<<6);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) ;
++	reg &= ~(0x1<<5);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x27*4) ;
++	reg &= ~(0x1<<5);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x27*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x27*4) ;
++	reg &= ~(0x1<<6);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x27*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x27*4) ;
++	reg &= ~(0x1<<7);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x27*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) ;
++	reg &= ~(0x3<<0);
++	reg |= (0x1<<0);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) ;
++	reg &= ~(0x1<<2);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) ;
++	reg &= ~(0x1<<3);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x27*4) ;
++	reg &= ~(0x1<<4);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x27*4) = reg;
++}
++
++
++static void inno_poweroff(struct snd_soc_component *component)
++{
++	unsigned int reg = 0x00;
++	int i ;
++
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x21*4) = 0x01;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x22*4) ;
++	reg &= ~(0x1<<5);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x22*4) = reg;
++
++	for(i = 0; i < 0x100; i++) {
++		*(volatile unsigned int *)(INNO_CODEC_BASE + 0x21*4) = i;
++		udelay(200);
++	}
++
++	/*soft reset*/
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x00*4) = 0x0;
++	udelay(200);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x00*4) = 0x3;
++}
++
++static int inno_adc_configure(struct snd_soc_component *component,
++			struct snd_pcm_hw_params *params)
++{
++	int fmt_width = snd_pcm_format_width(params_format(params));
++	unsigned int reg = 0x00;
++
++	reg = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x03*4);
++	reg |= (0x1 << 1);
++	reg &= ~(0x1 << 0);
++	if(fmt_width > 16) {
++		reg |= (0x3 << 2);
++	} else if(fmt_width > 8) {
++		reg |= (0x0 << 2);
++	}
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x03*4) = reg;
++
++	reg = 0x10;
++	if(fmt_width == 32) {
++		reg |= (0x3 << 5);
++	} else if(fmt_width == 24) {
++		reg |= (0x2 << 5);
++	} else if(fmt_width == 20)  {
++		reg |= (0x1 << 5);
++	} else if(fmt_width == 16){
++		reg |= (0x0 << 5);
++	} else {
++		dev_err(component->dev, "icodec not support format width\n");
++		return -EINVAL;
++	}
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x02*4) = reg;
++
++	return 0;
++}
++
++
++
++static void inno_adc_enable (struct snd_soc_component *component)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++	unsigned int reg = 0x00;
++
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4) ;
++	reg |= (1<<7);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4) = reg;
++
++	/*add  enable signal  of  current source for ADC */
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x22*4) ;
++	reg |= (1<<4);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x22*4) = reg;
++
++	/* set adc current value*/
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x24*4) ;
++	reg &= ~(0xf<<0);
++	reg |= (0x8<<0);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x24*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4) ;
++	reg |= (1<<5);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4) = reg;
++
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x24*4) ;
++	reg |= (1<<4);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x24*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x24*4) ;
++	reg |= (1<<5);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x24*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) ;
++	reg |= (1<<6);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) ;
++	reg |= (1<<5);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) ;
++	reg |= (1<<4);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) ;
++	reg |= (1<<7);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) = reg;
++
++
++/**3***/
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4) ;
++	reg |= (1<<6);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4) = reg;
++
++	/*set high filter */
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0xa*4) ;
++	reg &= ~(0x7);
++	reg |= 0x1;
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0xa*4) = reg;
++
++	/*set gain of mic module in ADCL, invalid*/
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x24*4) ;
++	reg &= ~(3<<6);
++	reg |= (3<<6);  //30db
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x24*4) = reg;
++
++	/* slecet 0x25[0:4] set gain */
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0xa*4) ;
++	reg &= ~(1<<5);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0xa*4) = reg;
++
++	/* set gain of ALC */
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x25*4) ;
++	reg &= ~(0x1f<<0);
++	reg |= (icodec->alcl_gain << 0);   //28.5db
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x25*4) = reg;
++
++#if 0
++	/* slecet ALCL module to control gain*/
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0xa*4) ;
++	reg |= (1<<5);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0xa*4) = reg;
++
++	/*clwang test  do nothing */
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x49*4) ;
++	reg |= (1<<6);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x49*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x43*4) ;
++	reg &= ~(0x1f<<0);
++	reg |= (0x1f<<0);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x43*4) = reg;
++
++#endif
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x22*4) ;
++	reg |= (1<<3);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x22*4) = reg;
++
++
++	/*set maicbias*/
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x22*4) ;
++	reg &= ~(0x7<<0);
++	reg |= (icodec->micbias << 0);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x22*4) = reg;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4) ;
++	reg |= (1<<4);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4) = reg;
++
++	/* close adc mute */
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4) ;
++	reg &= ~(1<<7);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4) = reg;
++
++	udelay(100);
++
++	/* open adc mute */
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4) ;
++	reg |= (1<<7);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4) = reg;
++}
++
++static void inno_adc_disable (struct snd_soc_component *component)
++{
++/***1*/
++	unsigned int reg = 0x00;
++
++	reg = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4);
++	reg &= ~(0x1 << 4);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4) = reg;
++
++	reg = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4);
++	reg &= ~(0x1 << 5);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) = reg;
++
++	reg = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4);
++	reg &= ~(0x1 << 6);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) = reg;
++
++	reg = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x24*4);
++	reg &= ~(0x1 << 5);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x24*4) = reg;
++
++	reg = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x24*4);
++	reg &= ~(0x1 << 4);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x24*4) = reg;
++
++	reg = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4);
++	reg &= ~(0x1 << 5);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4) = reg;
++
++	reg = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x22*4);
++	reg &= ~(0x1 << 4);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x22*4) = reg;
++
++	reg = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4);
++	reg &= ~(0x1 << 4);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) = reg;
++
++	reg = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4);
++	reg &= ~(0x1 << 7);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x26*4) = reg;
++
++	reg = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4);
++	reg &= ~(0x1 << 6);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x23*4) = reg;
++}
++
++static int icodec_startup(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++
++	if (icodec->powered)
++		return 0;
++	icodec->powered = true;
++
++	inno_poweron(component);
++
++	return 0;
++}
++
++static int icodec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
++{
++
++
++	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++	case SND_SOC_DAIFMT_CBM_CFM:
++		inno_codec_master = true;
++		break;
++	case SND_SOC_DAIFMT_CBS_CFS:	/*codec frame slave */
++		inno_codec_master = false;
++		break;
++	default:
++		pr_err("%s:%d\n", __func__, __LINE__);
++		return -EINVAL;
++	}
++	return 0;
++}
++
++static int icodec_hw_params(struct snd_pcm_substream *substream,
++			    struct snd_pcm_hw_params *params,
++			    struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++	unsigned int reg = 0x00;
++	int ret;
++
++	reg = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x03*4);
++	if(inno_codec_master) {
++		reg |= (0xf << 4);
++	}else{
++		reg &= ~(0xf << 4);
++	}
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x03*4) = reg;
++
++	if(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		ret = inno_dac_configure(component, params);
++	} else {
++		ret = inno_adc_configure(component, params);
++	}
++
++	return ret;
++}
++
++static int icodec_trigger(struct snd_pcm_substream *substream, int cmd,
++		struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		if(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++			if(g_icodec_playback_pwr != NULL)
++				(*g_icodec_playback_pwr)(1);
++			inno_dac_enable(component);
++
++			if(icodec_mute == 1){
++				inno_dac_disable(component);
++			}
++		} else {
++			inno_adc_enable(component);
++		}
++		break;
++	case SNDRV_PCM_TRIGGER_STOP:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++		if(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++			if(g_icodec_playback_pwr != NULL)
++				(*g_icodec_playback_pwr)(0);
++			inno_dac_disable(component);
++			mdelay(25);
++		} else {
++			inno_adc_disable(component);
++		}
++		break;
++	}
++//	dump_regs(component);
++	return 0;
++}
++
++
++static void icodec_shutdown(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++
++	if (!icodec->powered || snd_soc_component_active(component))
++		return;
++	icodec->powered = false;
++
++	inno_poweroff(component);
++}
++
++static struct snd_soc_dai_ops icodec_dai_ops = {
++	.hw_params	= icodec_hw_params,
++	.set_fmt	= icodec_set_dai_fmt,
++	.trigger	= icodec_trigger,
++	.shutdown	= icodec_shutdown,
++	.startup	= icodec_startup,
++};
++
++static struct snd_soc_dai_driver  icodec_codec_dai = {
++	.name = "icodec",
++	.playback = {
++		.stream_name = "Playback",
++		.channels_min = 1,
++		.channels_max = 2,
++		.rates = SNDRV_PCM_RATE_8000_192000,
++		.formats = ICODEC_FORMATS,
++	},
++	.capture = {
++		.stream_name = "Capture",
++		.channels_min = 1,
++		.channels_max = 2,
++		.rates = SNDRV_PCM_RATE_8000_192000,
++		.formats = ICODEC_FORMATS,
++	},
++	.ops = &icodec_dai_ops,
++};
++
++#ifdef CONFIG_PM
++static int icodec_suspend(struct snd_soc_component *component)
++{
++	return 0;
++}
++
++static int icodec_resume(struct snd_soc_component *component)
++{
++	return 0;
++}
++#endif
++
++static int icodec_probe(struct snd_soc_component *component)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++	dev_info(component->dev, "icodec probe enter\n");
++
++	icodec->component = component;
++	return 0;
++}
++
++static void icodec_remove(struct snd_soc_component *component)
++{
++	dev_info(component->dev, "codec icodec remove enter\n");
++}
++
++static int icodec_controls_get(struct snd_kcontrol *kcontrol,
++			    struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++
++	if(!strcmp(kcontrol->id.name, "ICODEC MICL GAIN")) {
++		ucontrol->value.integer.value[0] = icodec->alcl_gain;
++	}
++	if(!strcmp(kcontrol->id.name, "ICODEC HPOUTL GAIN")) {
++		ucontrol->value.integer.value[0] = icodec->hpoutl_gain;
++	}
++	if(!strcmp(kcontrol->id.name, "ICODEC MICBIAS")) {
++		ucontrol->value.integer.value[0] = icodec->micbias;
++	}
++
++	return 0;
++}
++
++static int icodec_controls_put(struct snd_kcontrol *kcontrol,
++			    struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++	unsigned int reg = 0x00;
++
++	if(!strcmp(kcontrol->id.name, "ICODEC MICL GAIN")) {
++		icodec->alcl_gain = ucontrol->value.integer.value[0];
++		if(snd_soc_component_active(component)) {
++			reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x25*4) ;
++			reg &= ~(0x1f<<0);
++			reg |= (icodec->alcl_gain << 0);
++			*(volatile unsigned int *)(INNO_CODEC_BASE + 0x25*4) = reg;
++		}
++	}
++	if(!strcmp(kcontrol->id.name, "ICODEC HPOUTL GAIN")) {
++		icodec->hpoutl_gain = ucontrol->value.integer.value[0];
++		if(snd_soc_component_active(component)) {
++			reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) ;
++			reg &= ~(0x1f<<0);
++			reg |= (icodec->hpoutl_gain << 0);
++			*(volatile unsigned int *)(INNO_CODEC_BASE + 0x28*4) = reg;
++		}
++
++		if(!icodec->hpoutl_gain){
++			icodec_mute = 1;
++			inno_dac_disable(component);
++
++		}else if(icodec_mute ==1 && icodec->hpoutl_gain){
++			inno_dac_enable(component);
++			icodec_mute = 0;
++		}
++	}
++
++	if(!strcmp(kcontrol->id.name, "ICODEC MICBIAS")) {
++		icodec->micbias = ucontrol->value.integer.value[0];
++	}
++
++	return 0;
++}
++
++static int icodec_spk_power(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event)
++{
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++
++	if (g_icodec_playback_pwr == NULL)
++		return 0;
++
++	if (SND_SOC_DAPM_EVENT_ON(event)) {
++		(*g_icodec_playback_pwr)(1);
++	} else {
++		(*g_icodec_playback_pwr)(0);
++	}
++	return 0;
++}
++
++
++/*
++ * ALCL GAIN volume control:
++ * from -18dB to 28.5dB in 1.5 dB steps
++ * */
++static const DECLARE_TLV_DB_SCALE(alcl_gain_tlv, -1800, 150, 0);
++
++/*
++ * HPOUTL GAIN volume control:
++ * from -39dB to 6dB in 1.5 dB steps
++ * */
++static const DECLARE_TLV_DB_SCALE(hpoutl_gain_tlv, -3900, 150, 0);
++
++static const struct snd_kcontrol_new icodec_controls[] = {
++#if 1
++	SOC_SINGLE_EXT_TLV("ICODEC MICL GAIN", 0, 0, 0x1f, 0 , icodec_controls_get, icodec_controls_put, alcl_gain_tlv),
++	SOC_SINGLE_EXT_TLV("ICODEC HPOUTL GAIN", 0, 0, 0x1f, 0 , icodec_controls_get, icodec_controls_put, hpoutl_gain_tlv),
++	SOC_SINGLE_EXT("ICODEC MICBIAS", 0, 0, 0x7, 0 , icodec_controls_get, icodec_controls_put),
++#else
++	SOC_SINGLE_TLV("ICODEC MICL GAIN", 0x25*4, 0, 0x1f, 0, alcl_gain_tlv),
++	SOC_SINGLE_TLV("ICODEC HPOUTL GAIN", 0x28*4, 0, 0x1f, 0 , hpoutl_gain_tlv),
++	SOC_SINGLE("ICODEC MICBIAS", 0x22*4, 0, 0x7, 0),
++#endif
++};
++
++static const struct snd_soc_dapm_widget icodec_widgets[] = {
++	SND_SOC_DAPM_AIF_OUT("SDTO", "Capture", 0, SND_SOC_NOPM, 0, 0),
++	SND_SOC_DAPM_AIF_IN("SDTI", "Playback", 0, SND_SOC_NOPM, 0, 0),
++	SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),/*pw*/
++	SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 0, 0),
++	SND_SOC_DAPM_ADC("ALCL", NULL, SND_SOC_NOPM, 0, 0),
++	SND_SOC_DAPM_SPK("Speaker", icodec_spk_power),
++	SND_SOC_DAPM_OUTPUT("HPOUTL"),
++	SND_SOC_DAPM_INPUT("MICL"),
++};
++
++static const struct snd_soc_dapm_route icodec_route[] = {
++	{"DACL",		NULL,	"SDTI"},
++	{"HPOUTL",		NULL,	"DACL"},
++	{"Speaker",		NULL,	"HPOUTL"},
++	{"SDTO",		NULL,	"ADCL"},
++	{"ADCL",		NULL,	"ALCL"},
++	{"ALCL",		NULL,	"MICL"},
++};
++
++static struct snd_soc_component_driver soc_component_dev_icodec = {
++	.probe = 	icodec_probe,
++	.remove = 	icodec_remove,
++#ifdef CONFIG_PM
++	.suspend =	icodec_suspend,
++	.resume =	icodec_resume,
++#endif
++
++	.read = 	icodec_read,
++	.write = 	icodec_write,
++
++	.controls = 	icodec_controls,
++	.num_controls = ARRAY_SIZE(icodec_controls),
++	.dapm_widgets = icodec_widgets,
++	.num_dapm_widgets = ARRAY_SIZE(icodec_widgets),
++	.dapm_routes = icodec_route,
++	.num_dapm_routes = ARRAY_SIZE(icodec_route),
++};
++
++static int icodec_platform_probe(struct platform_device *pdev)
++{
++	struct icodec *icodec = NULL;
++	struct resource *res;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	icodec = (struct icodec*)devm_kzalloc(&pdev->dev,
++			sizeof(struct icodec), GFP_KERNEL);
++	if (!icodec)
++		return -ENOMEM;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	icodec->io_base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(icodec->io_base)) {
++		dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
++		return PTR_ERR(icodec->io_base);
++	}
++
++	icodec->dev = &pdev->dev;
++	icodec->alcl_gain = 0x1f;
++	icodec->hpoutl_gain = 0x1f;
++	icodec->micbias = 0;
++	printk(" alcl_gain = 0x%x hpoutl_gain = 0x%x micbias = 0x%x\n", icodec->alcl_gain, icodec->hpoutl_gain, icodec->micbias);
++	spin_lock_init(&icodec->io_lock);
++	platform_set_drvdata(pdev, (void *)icodec);
++
++	ret = snd_soc_register_component(&pdev->dev,
++			&soc_component_dev_icodec, &icodec_codec_dai, 1);
++	if (ret) {
++		dev_err(&pdev->dev, "Faild to register component\n");
++		platform_set_drvdata(pdev, NULL);
++		return ret;
++	}
++
++	dev_info(&pdev->dev, "component icodec platfrom probe success\n");
++	return 0;
++}
++
++static int icodec_platform_remove(struct platform_device *pdev)
++{
++	dev_info(&pdev->dev, "component icodec platform remove\n");
++	snd_soc_unregister_component(&pdev->dev);
++	platform_set_drvdata(pdev, NULL);
++	return 0;
++}
++
++static const struct of_device_id component_dt_match[] = {
++	{ .compatible = "ingenic,icodec", .data = NULL },
++	{},
++};
++MODULE_DEVICE_TABLE(of, component_dt_match);
++
++static struct platform_driver icodec_component_driver = {
++	.driver = {
++		.name = "icodec",
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(component_dt_match),
++	},
++	.probe = icodec_platform_probe,
++	.remove = icodec_platform_remove,
++};
++
++
++static int icodec_modinit(void)
++{
++	return platform_driver_register(&icodec_component_driver);
++}
++module_init(icodec_modinit);
++
++static void icodec_exit(void)
++{
++	platform_driver_unregister(&icodec_component_driver);
++}
++module_exit(icodec_exit);
++
++MODULE_DESCRIPTION("Icodec Codec Driver");
++MODULE_AUTHOR("tjyang<taojiang.yang@ingenic.com>");
++MODULE_LICENSE("GPL");
+diff --git a/module_drivers/sound/soc/ingenic/icodec/icdc_inno_v2.c b/module_drivers/sound/soc/ingenic/icodec/icdc_inno_v2.c
+new file mode 100644
+index 000000000..1eb1d35a8
+--- /dev/null
++++ b/module_drivers/sound/soc/ingenic/icodec/icdc_inno_v2.c
+@@ -0,0 +1,1239 @@
++/*
++ * sound/soc/ingenic/icodec/icdc_inno_v2.c
++ * ALSA SoC Audio driver -- ingenic internal codec (icodec) driver
++
++ * Copyright 2019 Ingenic Semiconductor Co.,Ltd
++ *	zhxiao <zhihao.xiao@ingenic.com>
++ *
++ * Note: icodec is an internal codec for ingenic SOC
++ *	 used for x2500
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/pm.h>
++#include <linux/platform_device.h>
++#include <linux/vmalloc.h>
++#include <linux/slab.h>
++#include <linux/ctype.h>
++#include <linux/io.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++#include <sound/initval.h>
++#include <sound/soc-dai.h>
++#include <linux/of_address.h>
++#include <linux/gpio.h>
++#include <linux/of_gpio.h>
++#include <sound/tlv.h>
++
++
++#define INNO_CODEC_BASE 0xb0021000
++static bool	    icodec_codec_master = true;
++
++#define ICODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
++			 SNDRV_PCM_FMTBIT_S20_3LE |SNDRV_PCM_FMTBIT_S24_LE)
++
++
++#define TS_CODEC_CGR_00			0x00
++#define TS_CODEC_CACR_02		0x08
++#define TS_CODEC_CACR2_03       0x0c
++#define TS_CODEC_CDCR1_04       0x10
++#define TS_CODEC_CDCR2_05       0x14
++#define TS_CODEC_CDCR2_06       0x18
++#define TS_CODEC_CAVR_08        0x20
++#define TS_CODEC_CGAINLR_09     0x24
++#define TS_CODEC_CGAINLR_0a     0x28
++#define TS_CODEC_POWER_20       0x80
++#define TS_CODEC_CCR_21         0x84
++#define TS_CODEC_CAACR_22       0x88
++#define TS_CODEC_CMICCR_23      0x8c
++#define TS_CODEC_CMICGAINR_24   0x90
++#define TS_CODEC_CALCGR_25      0x94
++#define TS_CODEC_CANACR_26      0x98
++#define TS_CODEC_CANACR2_27     0x9c
++#define TS_CODEC_CHR_28         0xA0
++#define TS_CODEC_CHR_29         0xA4
++#define TS_CODEC_CHR_2a         0xA8
++#define TS_CODEC_CHR_2b         0xAC
++#define TS_CODEC_CMR_40			0x100
++#define TS_CODEC_CTR_41			0x104
++#define TS_CODEC_CAGCCR_42		0x108
++#define TS_CODEC_CPGR_43		0x10c
++#define TS_CODEC_CSRR_44		0x110
++#define TS_CODEC_CALMR_45		0x114
++#define TS_CODEC_CAHMR_46		0x118
++#define TS_CODEC_CALMINR_47		0x11c
++#define TS_CODEC_CAHMINR_48		0x120
++#define TS_CODEC_CAFG_49		0x124
++#define TS_CODEC_CCAGVR_4c		0x130
++#define TS_CODEC_CMR_50			0x140
++#define TS_CODEC_CTR_51			0x144
++#define TS_CODEC_CAGCCR_52		0x148
++#define TS_CODEC_CPGR_53		0x14c
++#define TS_CODEC_CSRR_54		0x150
++#define TS_CODEC_CALMR_55		0x154
++#define TS_CODEC_CAHMR_56		0x158
++#define TS_CODEC_CALMINR_57		0x15c
++#define TS_CODEC_CAHMINR_58		0x160
++#define TS_CODEC_CAFG_59		0x164
++#define TS_CODEC_CCAGVR_5c		0x170
++
++
++#define MONO_LEFT   1
++#define MONO_RIGHT  2
++#define STEREO 3
++
++
++struct icodec {
++	struct device		*dev;
++	struct snd_soc_component	*component;
++	spinlock_t		io_lock;
++	void * __iomem io_base;
++	bool powered;
++	int spk_gpio;
++	int sgm8903_gpio;
++	unsigned char spk_en_level;
++	unsigned char alcl_gain;
++	unsigned char alcr_gain;
++	unsigned char micl_dgain;
++	unsigned char micr_dgain;
++	unsigned char hpoutl_again;
++	unsigned char hpoutl_dgain;
++	unsigned char micbias;
++	unsigned char michpf;
++	unsigned char channel;
++};
++
++typedef void (*p_icodec_playback_power)(bool);
++static p_icodec_playback_power g_icodec_playback_pwr;// playback power control funtion pointer assignment in boards
++
++unsigned int reg_tab[] = {0x00, 0x02, 0x03, 0x4, 0x5, 0x0a, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
++	0x27, 0x28, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49};
++
++void set_playback_pwr_callback(p_icodec_playback_power func)
++{
++	g_icodec_playback_pwr = func;
++}
++EXPORT_SYMBOL(set_playback_pwr_callback);
++
++static unsigned int icodec_read(struct snd_soc_component *component , unsigned int reg)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++	int value = readl(icodec->io_base + reg);
++	return value;
++}
++
++static int icodec_write(struct snd_soc_component *component , unsigned int reg , unsigned value)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++	writel(value ,icodec->io_base + reg);
++	return 0;
++}
++
++
++static inline unsigned int icodec_reg_read(struct icodec *icodec, int offset)
++{
++	return readl(icodec->io_base + offset);
++}
++
++static inline void icodec_reg_write(struct icodec *icodec, int offset, int data)
++{
++	writel(data, icodec->io_base + offset);
++}
++
++int icodec_reg_set(struct icodec *icodec, unsigned int reg, int start, int end, int val)
++{
++	int ret = 0;
++	int i = 0, mask = 0;
++	unsigned int oldv = 0;
++	unsigned int new = 0;
++	for (i = 0;  i < (end - start + 1); i++) {
++		mask += (1 << (start + i));
++	}
++
++	oldv = icodec_reg_read(icodec, reg);
++	new = oldv & (~mask);
++	new |= val << start;
++	icodec_reg_write(icodec, reg, new);
++
++	if ((new & 0x000000FF) != icodec_reg_read(icodec, reg)) {
++		printk("%s(%d):codec write  0x%08x error!!\n",__func__, __LINE__ ,reg);
++		printk("new = 0x%08x, read val = 0x%08x\n", new, icodec_reg_read(icodec, reg));
++		return -1;
++	}
++
++	return ret;
++}
++
++static void icodec_poweron(struct snd_soc_component *component)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++	int i = 0;
++	char value = 0;
++	/* step1. reset codec */
++	icodec_reg_set(icodec, TS_CODEC_CGR_00, 0, 1, 0);
++	msleep(1);
++	icodec_reg_set(icodec, TS_CODEC_CGR_00, 0, 1, 0x3);
++	/* step2. setup dc voltags of DAC channel output */
++	icodec_reg_set(icodec, TS_CODEC_CHR_2a, 0, 1, 0x1);
++	icodec_reg_set(icodec, TS_CODEC_CHR_2a, 4, 5, 0x1);
++	/* step3. no desc */
++	icodec_reg_set(icodec, TS_CODEC_CCR_21, 0, 7, 0x1);
++	icodec_reg_set(icodec, TS_CODEC_CAACR_22, 5, 5, 0x1);//setup reference voltage
++
++	for (i = 0; i <= 7; i++) {
++		value |= value<<1 | 0x01;
++		icodec_reg_set(icodec, TS_CODEC_CCR_21, 0, 7, value);
++		msleep(20);
++	}
++	msleep(20);
++	icodec_reg_set(icodec, TS_CODEC_CCR_21, 0, 7, 0x02);//Set the min charge current for reduce power.
++
++}
++
++static int icodec_set_sample_rate(struct icodec *icodec, unsigned int rate)
++{
++	int i = 0;
++	unsigned int mrate[8] = {8000, 12000, 16000, 24000, 32000, 44100, 48000, 96000};
++	unsigned int rate_fs[8] = {7, 6, 5, 4, 3, 2, 1, 0};
++	for (i = 0; i < 8; i++) {
++		if (rate <= mrate[i])
++			break;
++	}
++	if (i == 8)
++		i = 0;
++	icodec_reg_set(icodec, TS_CODEC_CSRR_44, 0, 2, rate_fs[i]);
++	icodec_reg_set(icodec, TS_CODEC_CSRR_54, 0, 2, rate_fs[i]);
++
++	return 0;
++}
++
++static int icodec_dac_configure(struct snd_soc_component *component,
++			struct snd_pcm_hw_params *params)
++{
++	int fmt_width = snd_pcm_format_width(params_format(params));
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++	unsigned int reg = 0x00;
++
++	reg = 0x10;
++	if(fmt_width == 32) {
++		reg |= (0x3 << 5);
++	} else if(fmt_width == 24) {
++		reg |= (0x2 << 5);
++	} else if(fmt_width == 20)  {
++		reg |= (0x1 << 5);
++	} else if(fmt_width == 16){
++		reg |= (0x0 << 5);
++	} else {
++		dev_err(component->dev, "icodec not support format width\n");
++		return -EINVAL;
++	}
++	icodec_reg_set(icodec,TS_CODEC_CDCR1_04, 5, 6, reg);
++
++
++	return 0;
++}
++
++static void icodec_dac_enable(struct snd_soc_component *component)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++
++	/* DAC i2S interface */
++	icodec_reg_set(icodec, TS_CODEC_CACR2_03, 6, 7, 0x3);
++	icodec_reg_set(icodec, TS_CODEC_CDCR1_04, 0, 7, 0x10);
++	icodec_reg_set(icodec, TS_CODEC_CDCR2_05, 0, 7, 0x0e);
++
++	/* enable current source */
++	icodec_reg_set(icodec, TS_CODEC_CHR_29, 7, 7, 0x1);
++	icodec_reg_set(icodec, TS_CODEC_POWER_20, 0, 3, 0x07);
++
++	/* enable reference voltage */
++	icodec_reg_set(icodec, TS_CODEC_CHR_29, 6, 6, 0x1);
++
++	/* enable POP sound */
++	icodec_reg_set(icodec, TS_CODEC_CHR_29, 4, 5, 0x2);
++
++	/* enable HPDRV module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_2a, 4, 4, 1);
++
++	/* end initialization HPDRV module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_2a, 5, 5, 1);
++
++	/* enable reference voltage */
++	icodec_reg_set(icodec, TS_CODEC_CHR_29, 3, 3, 1);
++
++	/* enable DACL clock module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_29, 2, 2, 1);
++
++	/* enable DACL module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_29, 1, 1, 1);
++
++	/* end initialization DAC module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_29, 0, 0, 1);
++
++	/* end mute station DRV module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_2a, 6, 6, 1);
++
++	/* set default again of HPDRV module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_2b, 0, 4, icodec->hpoutl_again);
++
++	/* set default dgain of HPDRV module */
++	icodec_reg_set(icodec, TS_CODEC_CDCR2_06, 0, 7, icodec->hpoutl_dgain);
++}
++
++static void icodec_dac_disable(struct snd_soc_component *component)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++
++	icodec_reg_set(icodec, TS_CODEC_CHR_2b, 0, 4, 0);
++
++	/* mute HPDRV module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_2a, 6, 6, 0);
++
++	/* initialize DAC module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_2a, 5, 5, 0);
++
++	/* disable HPDRV module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_2a, 4, 4, 0);
++
++	/* disable DACL module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_29, 1, 1, 0);
++
++	/* disable DACL clock module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_29, 2, 2, 0);
++
++	/* disable DACL reference voltage */
++	icodec_reg_set(icodec, TS_CODEC_CHR_29, 3, 3, 0);
++
++	/* initialize POP sound */
++	icodec_reg_set(icodec, TS_CODEC_CHR_29, 4, 5, 0x1);
++
++	/* disable reference voltage buffer */
++	icodec_reg_set(icodec, TS_CODEC_CHR_29, 6, 6, 0);
++
++	/* disable current source DAC */
++	icodec_reg_set(icodec, TS_CODEC_CHR_29, 7, 7, 0);
++
++	/* begin initialization HPDRV module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_29, 0, 0, 0);
++}
++
++
++
++static int icodec_adc_configure(struct snd_soc_component *component,
++			struct snd_pcm_hw_params *params)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++	unsigned int fmt_width = snd_pcm_format_width(params_format(params));
++	unsigned int samplerate = params_rate(params);
++	unsigned int channel = params_channels(params);
++	unsigned int reg = 0x00;
++
++	if(channel == 2)
++		icodec->channel = STEREO;
++	else if(channel == 1) {
++#ifdef CONFIG_AUDIO_MONO_LEFT
++		icodec->channel = MONO_LEFT;
++#endif
++#ifdef CONFIG_AUDIO_MONO_RIGHT
++		icodec->channel = MONO_RIGHT;
++#endif
++	} else {
++		dev_err(component->dev, "channel is not support !\n");
++	}
++
++	reg = 0x10;
++	if(fmt_width == 32) {
++		reg |= (0x3 << 5);
++	} else if(fmt_width == 24) {
++		reg |= (0x2 << 5);
++	} else if(fmt_width == 20) {
++		reg |= (0x1 << 5);
++	} else if(fmt_width == 16){
++		reg |= (0x0 << 5);
++	} else {
++		dev_err(component->dev, "icodec not support format width\n");
++		return -EINVAL;
++	}
++	icodec_reg_set(icodec, TS_CODEC_CACR_02, 5, 6, reg);
++
++	if(samplerate > 96000 || samplerate < 8000) {
++		dev_err(component->dev, "icodec not support samplerate %d \n", samplerate);
++		return -EINVAL;
++	}
++	icodec_set_sample_rate(icodec, samplerate);
++
++	return 0;
++}
++
++/* ADC left enable configuration */
++static int icodec_enable_left_record(struct snd_soc_component *component)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++
++	/* select ADC mono mode */
++	icodec_reg_set(icodec, TS_CODEC_CACR_02, 0, 0, 1);//mono
++
++	/* configure ADC I2S interface mode */
++	icodec_reg_set(icodec, TS_CODEC_CACR_02, 3, 4, 0x2);
++	icodec_reg_set(icodec, TS_CODEC_CACR2_03, 0, 5, 0x3e);
++
++	/* end mute station of ADC left channel */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 7, 7, 1);
++
++	/* enable current source of audio */
++	icodec_reg_set(icodec, TS_CODEC_CAACR_22, 4, 4, 1);
++
++	/* bias current:reduce power,max is 7*/
++	icodec_reg_set(icodec, TS_CODEC_CMICGAINR_24, 0, 3, 7);
++
++	icodec_reg_set(icodec, TS_CODEC_CAACR_22, 3, 3, 1);
++	icodec_reg_set(icodec, TS_CODEC_CAACR_22, 0, 2, icodec->micbias);
++
++	/* enable reference voltage buffer in ADC left channel */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 5, 5, 1);
++
++	/* enable MIC module in ADC left channel */
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 2, 2, 1);
++
++	/* enable ALC module in ADC left channel */
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 3, 3, 1);
++
++	/* enable clock module in ADC left channel */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 6, 6, 1);
++
++	/* enable ADC module in ADC left channel */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 5, 5, 1);
++
++	/* end initialization of ADCL module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 4, 4, 1);
++
++	/* end initialization of ALC left module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 7, 7, 1);
++
++	/* end initialization of mic left module */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 6, 6, 1);
++
++	/* set default mic gain of left module */
++	icodec_reg_set(icodec, TS_CODEC_CMICGAINR_24, 6, 7, 3);
++
++	/* set default codec gain of left module */
++	icodec_reg_set(icodec, TS_CODEC_CANACR_26, 0, 4, icodec->alcl_gain);
++
++	/* enable zero-crossing detection function in ADC left channel */
++	//if enable zero-crossing detection function,will cause small voice at first.
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 4, 4, 0);
++	icodec_reg_set(icodec, TS_CODEC_CMICGAINR_24, 0, 3, 3);
++
++	return 0;
++}
++
++
++/* ADC left disable cofiguration */
++static int icodec_disable_left_record(struct snd_soc_component *component)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++
++	/* disable zero-crossing detection function in ADC left channel */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 4, 4, 0);
++
++	/* disable ADC module for left channel */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 5, 5, 0);
++
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 6, 6, 0);
++
++	/* disable ALC module for left channel */
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 5, 5, 0);
++
++	/* disable MIC module for left channel */
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 4, 4, 0);
++
++	/* disable reference voltage buffer for left channel */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 5, 5, 0);
++
++	/* disable mic bias voltage buffer */
++	icodec_reg_set(icodec, TS_CODEC_CAACR_22, 4, 4, 0);
++
++	/* begin initiialization ADC left module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 4, 4, 0);
++
++	/* begin initialization ALC left module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 7, 7, 0);
++
++	/* begin initialization MIC left module */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 6, 6, 0);
++//	msleep(20);
++
++	return 0;
++}
++
++/* ADC right enable configuration */
++static int icodec_enable_right_record(struct snd_soc_component *codec)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(codec);
++
++	/* select ADC stereo mode */
++	icodec_reg_set(icodec, TS_CODEC_CACR_02, 0, 0, 0);
++
++	/* configure ADC I2S interface mode */
++	icodec_reg_set(icodec, TS_CODEC_CACR_02, 3, 4, 0x2);
++	icodec_reg_set(icodec, TS_CODEC_CACR2_03, 0, 5, 0x3e);
++
++	/* end mute station of ADC  right channel */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 7, 7, 1); //left
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 3, 3, 1); //right
++
++	/* enable current source of audio */
++	icodec_reg_set(icodec, TS_CODEC_CAACR_22, 4, 4, 1);
++	/* bias current:reduce power,max is 7*/
++	icodec_reg_set(icodec, TS_CODEC_CMICGAINR_24, 0, 3, 7);//add 10:57
++
++	icodec_reg_set(icodec, TS_CODEC_CAACR_22, 3, 3, 1);
++	icodec_reg_set(icodec, TS_CODEC_CAACR_22, 0, 2, icodec->micbias);
++
++	/* enable reference voltage buffer in ADC right channel */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 5, 5, 1);	//left
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 1, 1, 1); //right
++
++	/* enable MIC module in ADC right channel */
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 0, 0, 1);	//right
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 2, 2, 1);
++
++	/* enable ALC module in ADC right channel */
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 1, 1, 1);
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 3, 3, 1);
++
++	/* enable clock module in ADC  right channel */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 2, 2, 1);
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 6, 6, 1);
++
++	/* enable ADC module in ADC right channel */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 1, 1, 1);
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 5, 5, 1);
++
++	/* end initialization of ADCR module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 0, 0, 1);
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 4, 4, 1);
++
++	/* end initialization of ALC right module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 3, 3, 1);
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 7, 7, 1);
++
++	/* end initialization of mic right module */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 2, 2, 1);
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 6, 6, 1);
++
++	/* set default mic gain of right module */
++	icodec_reg_set(icodec, TS_CODEC_CMICGAINR_24, 4, 5, 3);
++	icodec_reg_set(icodec, TS_CODEC_CMICGAINR_24, 6, 7, 3);
++
++	/* set default codec gain of right module */
++	icodec_reg_set(icodec, TS_CODEC_CANACR_26, 0, 4, icodec->alcl_gain);
++	icodec_reg_set(icodec, TS_CODEC_CANACR2_27, 0, 4, icodec->alcr_gain);
++
++	/* disable zero-crossing detection function in ADC right channel */
++	//if enable zero-crossing detection function,will cause small voice at first.
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 0, 0, 0);
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 4, 4, 0);
++
++
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 0, 7, 0x0e);
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 0, 7, 0x03);
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 0, 7, 0x0F);
++	icodec_reg_set(icodec, TS_CODEC_CMICGAINR_24, 0, 3, 3);
++	/* now begin recording... */
++
++	return 0;
++}
++
++/* ADC right disable cofiguration */
++static int icodec_disable_right_record(struct snd_soc_component *codec)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(codec);
++
++	/* disable zero-crossing detection function in ADC right channel */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 0, 0, 0);
++
++	/* disable ADC module for right channel */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 1, 1, 0);
++
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 2, 2, 0);
++
++	/* disable ALC module for right channel */
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 1, 1, 0);
++
++	/* disable MIC module for right channel */
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 0, 0, 0);
++
++	/* disable reference voltage buffer for right channel */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 1, 1, 0);
++
++	/* disable mic bias voltage buffer */
++	icodec_reg_set(icodec, TS_CODEC_CAACR_22, 4, 4, 0);
++
++	/* begin initiialization ADC right module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 0, 0, 0);
++
++	/* begin initialization ALC right module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 3, 3, 0);
++
++	/* begin initialization MIC right module */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 2, 2, 0);
++
++	return 0;
++}
++
++/* ADC stereo enable configuration */
++static int icodec_enable_stereo_record(struct snd_soc_component *codec)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(codec);
++
++	/* select ADC stereo mode */
++	icodec_reg_set(icodec, TS_CODEC_CACR_02, 0, 0, 0);
++
++	/* configure ADC I2S interface mode */
++	icodec_reg_set(icodec, TS_CODEC_CACR_02, 3, 4, 0x2);
++	icodec_reg_set(icodec, TS_CODEC_CACR2_03, 0, 5, 0x3e);
++
++	/* end mute station of ADC left and right channel */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 7, 7, 1);
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 3, 3, 1);
++
++	/* enable current source of audio */
++	icodec_reg_set(icodec, TS_CODEC_CAACR_22, 4, 4, 1);
++	/* bias current:reduce power,max is 7*/
++	icodec_reg_set(icodec, TS_CODEC_CMICGAINR_24, 0, 3, 7);//add 10:57
++
++	icodec_reg_set(icodec, TS_CODEC_CAACR_22, 3, 3, 1);
++	icodec_reg_set(icodec, TS_CODEC_CAACR_22, 0, 2, icodec->micbias);
++
++	/* enable reference voltage buffer in ADC left and right channel */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 5, 5, 1);
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 1, 1, 1);
++
++	/* enable MIC module in ADC left and right channel */
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 0, 0, 1);
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 2, 2, 1);
++
++	/* enable ALC module in ADC left and right channel */
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 1, 1, 1);
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 3, 3, 1);
++
++	/* enable clock module in ADC left and right channel */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 2, 2, 1);
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 6, 6, 1);
++
++	/* enable ADC module in ADC left and right channel */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 1, 1, 1);
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 5, 5, 1);
++
++	/* end initialization of ADCR and ADCL module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 0, 0, 1);
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 4, 4, 1);
++
++	/* end initialization of ALC left and right module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 3, 3, 1);
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 7, 7, 1);
++
++	/* end initialization of mic left and right module */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 2, 2, 1);
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 6, 6, 1);
++
++	/* set default mic gain of left and right module */
++	icodec_reg_set(icodec, TS_CODEC_CMICGAINR_24, 4, 5, 3);
++	icodec_reg_set(icodec, TS_CODEC_CMICGAINR_24, 6, 7, 3);
++
++	/* set default icodec gain of left and right module */
++	icodec_reg_set(icodec, TS_CODEC_CANACR_26, 0, 4, icodec->alcl_gain);
++	icodec_reg_set(icodec, TS_CODEC_CANACR2_27, 0, 4, icodec->alcr_gain);
++
++	/* disable zero-crossing detection function in ADC left and right channel */
++	//if enable zero-crossing detection function,will cause small voice at first.
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 0, 0, 0);
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 4, 4, 0);
++
++	/* now begin recording... */
++	icodec_reg_set(icodec, TS_CODEC_CMICGAINR_24, 0, 3, 3);
++
++	return 0;
++}
++
++/* ADC stereo disable cofiguration */
++static int icodec_disable_stereo_record(struct snd_soc_component *codec)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(codec);
++
++	/* disable zero-crossing detection function in ADC left and right channel */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 0, 0, 0);
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 4, 4, 0);
++
++	/* disable ADC module for left and right channel */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 1, 1, 0);
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 5, 5, 0);
++
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 2, 2, 0);
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 6, 6, 0);
++
++	/* disable ALC module for left and right channel */
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 1, 1, 0);
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 5, 5, 0);
++
++	/* disable MIC module for left and right channel */
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 0, 0, 0);
++	icodec_reg_set(icodec, TS_CODEC_CALCGR_25, 4, 4, 0);
++
++	/* disable reference voltage buffer for left and right channel */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 1, 1, 0);
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 5, 5, 0);
++
++	/* disable mic bias voltage buffer */
++	icodec_reg_set(icodec, TS_CODEC_CAACR_22, 4, 4, 0);
++
++	/* begin initiialization ADC left and right module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 0, 0, 0);
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 4, 4, 0);
++
++	/* begin initialization ALC left and right module */
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 3, 3, 0);
++	icodec_reg_set(icodec, TS_CODEC_CHR_28, 7, 7, 0);
++
++	/* begin initialization MIC left and right module */
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 2, 2, 0);
++	icodec_reg_set(icodec, TS_CODEC_CMICCR_23, 6, 6, 0);
++
++	return 0;
++}
++
++static void icodec_adc_enable (struct snd_soc_component *codec)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(codec);
++
++	if(icodec->channel == STEREO)
++		icodec_enable_stereo_record(codec);
++	else if(icodec->channel == MONO_LEFT)
++		icodec_enable_left_record(codec);
++	else if(icodec->channel == MONO_RIGHT)
++		icodec_enable_right_record(codec);
++	else
++		dev_err(codec->dev, "%s channel not support\n",__func__);
++}
++
++static void icodec_adc_disable (struct snd_soc_component *codec)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(codec);
++
++	if(icodec->channel == STEREO)
++		icodec_disable_stereo_record(codec);
++	else if(icodec->channel == MONO_LEFT)
++		icodec_disable_left_record(codec);
++	else if(icodec->channel == MONO_RIGHT)
++		icodec_disable_right_record(codec);
++	else
++		dev_err(codec->dev, "%s channel not support\n",__func__);
++}
++
++static void icodec_poweroff(struct snd_soc_component *codec)
++{
++	unsigned int reg = 0x00;
++	int i ;
++
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x21*4) = 0x01;
++
++	reg  = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x22*4) ;
++	reg &= ~(0x1<<5);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x22*4) = reg;
++
++	for(i = 0; i < 0x100; i++) {
++		*(volatile unsigned int *)(INNO_CODEC_BASE + 0x21*4) = i;
++		udelay(200);
++	}
++
++	/*soft reset*/
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x00*4) = 0x0;
++	udelay(200);
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x00*4) = 0x3;
++}
++
++static int icodec_startup(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++
++	if (icodec->powered)
++		return 0;
++	icodec->powered = true;
++
++	icodec_poweron(component);
++
++	return 0;
++}
++
++static int icodec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
++{
++
++	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++	case SND_SOC_DAIFMT_CBM_CFM:
++		icodec_codec_master = true;
++		break;
++	case SND_SOC_DAIFMT_CBS_CFS:	/*codec frame slave */
++		icodec_codec_master = false;
++		break;
++	default:
++		pr_err("%s:%d\n", __func__, __LINE__);
++		return -EINVAL;
++	}
++	return 0;
++}
++
++static int icodec_hw_params(struct snd_pcm_substream *substream,
++			    struct snd_pcm_hw_params *params,
++			    struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++	unsigned int reg = 0x00;
++	int ret;
++
++	reg = *(volatile unsigned int *)(INNO_CODEC_BASE + 0x03*4);
++	if(icodec_codec_master) {
++		reg |= (0x3 << 4);
++	}else{
++		reg &= ~(0x3 << 4);
++	}
++	*(volatile unsigned int *)(INNO_CODEC_BASE + 0x03*4) = reg;
++
++	if(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		ret = icodec_dac_configure(component, params);
++	} else {
++		ret = icodec_adc_configure(component, params);
++	}
++
++	return ret;
++}
++
++static int icodec_trigger(struct snd_pcm_substream *substream, int cmd,
++		struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *codec = dai->component;
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		if(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++			icodec_dac_enable(codec);
++			if(g_icodec_playback_pwr != NULL)
++				(*g_icodec_playback_pwr)(1);
++		} else {
++			icodec_adc_enable(codec);
++		}
++		break;
++	case SNDRV_PCM_TRIGGER_STOP:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++		if(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++			if(g_icodec_playback_pwr != NULL)
++				(*g_icodec_playback_pwr)(0);
++			icodec_dac_disable(codec);
++		} else {
++			icodec_adc_disable(codec);
++		}
++		break;
++	}
++
++	return 0;
++}
++
++
++static void icodec_shutdown(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *codec = dai->component;
++	struct icodec *icodec = snd_soc_component_get_drvdata(codec);
++
++	if (!icodec->powered || snd_soc_component_active(codec))
++		return;
++	icodec->powered = false;
++
++	icodec_poweroff(codec);
++}
++
++static struct snd_soc_dai_ops icodec_dai_ops = {
++	.hw_params	= icodec_hw_params,
++	.set_fmt	= icodec_set_dai_fmt,
++	.trigger	= icodec_trigger,
++	.shutdown	= icodec_shutdown,
++	.startup	= icodec_startup,
++};
++
++static struct snd_soc_dai_driver  icodec_codec_dai = {
++	.name = "icodec",
++	.playback = {
++		.stream_name = "Playback",
++		.channels_min = 1,
++		.channels_max = 2,
++		.rates = SNDRV_PCM_RATE_8000_192000,
++		.formats = ICODEC_FORMATS,
++	},
++	.capture = {
++		.stream_name = "Capture",
++		.channels_min = 1,
++		.channels_max = 2,
++		.rates = SNDRV_PCM_RATE_8000_192000,
++		.formats = ICODEC_FORMATS,
++	},
++	.ops = &icodec_dai_ops,
++};
++
++#ifdef CONFIG_PM
++static int icodec_suspend(struct snd_soc_component *codec)
++{
++	return 0;
++}
++
++static int icodec_resume(struct snd_soc_component *codec)
++{
++	return 0;
++}
++#endif
++
++static int icodec_probe(struct snd_soc_component *component)
++{
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++	dev_info(component->dev, "icodec probe enter\n");
++
++	icodec->component = component;
++	return 0;
++}
++
++static void icodec_remove(struct snd_soc_component *component)
++{
++	dev_info(component->dev, "codec icodec remove enter\n");
++}
++
++static int icodec_controls_get(struct snd_kcontrol *kcontrol,
++			    struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++
++	if(!strcmp(kcontrol->id.name, "HPOUTL AGAIN")) {
++		ucontrol->value.integer.value[0] = icodec->hpoutl_again;
++	}
++	if(!strcmp(kcontrol->id.name, "HPOUTL DGAIN")) {
++		ucontrol->value.integer.value[0] = icodec->hpoutl_dgain;
++	}
++	if(!strcmp(kcontrol->id.name, "MICBIAS")) {
++		ucontrol->value.integer.value[0] = icodec->micbias;
++	}
++	if(!strcmp(kcontrol->id.name, "MIC HPF SWITCH")) {
++		ucontrol->value.integer.value[0] = icodec->michpf;
++	}
++	if(!strcmp(kcontrol->id.name, "Left ADC Digital Volume")) {
++		ucontrol->value.integer.value[0] = icodec->micl_dgain;
++	}
++	if(!strcmp(kcontrol->id.name, "Right ADC Digital Volume")) {
++		ucontrol->value.integer.value[0] = icodec->micr_dgain;
++	}
++	if(!strcmp(kcontrol->id.name, "ALCL GAIN")) {
++		ucontrol->value.integer.value[0] = icodec->alcl_gain;
++	}
++	if(!strcmp(kcontrol->id.name, "ALCR GAIN")) {
++		ucontrol->value.integer.value[0] = icodec->alcr_gain;
++	}
++
++	return 0;
++}
++
++static int icodec_controls_put(struct snd_kcontrol *kcontrol,
++			    struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++
++	if(!strcmp(kcontrol->id.name, "Left ADC Digital Volume")) {
++		icodec->micl_dgain = ucontrol->value.integer.value[0];
++			icodec_reg_set(icodec, TS_CODEC_CAVR_08, 0, 7, icodec->micl_dgain);
++	}
++	if(!strcmp(kcontrol->id.name, "Right ADC Digital Volume")) {
++		icodec->micr_dgain = ucontrol->value.integer.value[0];
++			icodec_reg_set(icodec, TS_CODEC_CGAINLR_09, 0, 7, icodec->micr_dgain);
++	}
++	if(!strcmp(kcontrol->id.name, "HPOUTL DGAIN")) {
++		icodec->hpoutl_dgain = ucontrol->value.integer.value[0];
++		if(snd_soc_component_active(component)) {
++			icodec_reg_set(icodec, TS_CODEC_CDCR2_06, 0, 7, icodec->hpoutl_dgain);
++		}
++	}
++	if(!strcmp(kcontrol->id.name, "HPOUTL AGAIN")) {
++		icodec->hpoutl_again = ucontrol->value.integer.value[0];
++		if(snd_soc_component_active(component)) {
++			icodec_reg_set(icodec, TS_CODEC_CHR_2b, 0, 4, icodec->hpoutl_again);
++		}
++	}
++	if(!strcmp(kcontrol->id.name, "MICBIAS")) {
++		icodec->micbias = ucontrol->value.integer.value[0];
++	}
++	if(!strcmp(kcontrol->id.name, "MIC HPF SWITCH")) {
++		icodec->michpf = ucontrol->value.integer.value[0];
++			icodec_reg_set(icodec, TS_CODEC_CGAINLR_0a, 2, 2, icodec->michpf);
++	}
++	if(!strcmp(kcontrol->id.name, "ALCL GAIN")) {
++		icodec->alcl_gain = ucontrol->value.integer.value[0];
++		if(snd_soc_component_active(component)) {
++			icodec_reg_set(icodec, TS_CODEC_CANACR_26, 0, 4, icodec->alcl_gain);
++		}
++	}
++	if(!strcmp(kcontrol->id.name, "ALCR GAIN")) {
++		icodec->alcr_gain = ucontrol->value.integer.value[0];
++		if(snd_soc_component_active(component)) {
++			icodec_reg_set(icodec, TS_CODEC_CANACR2_27, 0, 4, icodec->alcr_gain);
++		}
++	}
++
++	return 0;
++}
++
++static int icodec_spk_power(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event)
++{
++	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
++	struct icodec *icodec = snd_soc_component_get_drvdata(component);
++
++	if ((!gpio_is_valid(icodec->spk_gpio)) || (!gpio_is_valid(icodec->sgm8903_gpio)))
++		return 0;
++
++	if (SND_SOC_DAPM_EVENT_ON(event)) {
++			gpio_direction_output(icodec->spk_gpio, icodec->spk_en_level);
++			gpio_direction_output(icodec->sgm8903_gpio, icodec->spk_en_level);
++		} else {
++			gpio_direction_output(icodec->spk_gpio, !icodec->spk_en_level);
++			gpio_direction_output(icodec->sgm8903_gpio, !icodec->spk_en_level);
++	}
++	return 0;
++}
++
++
++
++/*
++ * ALCL GAIN volume control:
++ * from -18dB to 28.5dB in 1.5 dB steps
++ * */
++static const DECLARE_TLV_DB_SCALE(alcl_gain_tlv, -1800, 150, 0);
++
++/*
++ * ALCR GAIN volume control:
++ * from -18dB to 28.5dB in 1.5 dB steps
++ * */
++static const DECLARE_TLV_DB_SCALE(alcr_gain_tlv, -1800, 150, 0);
++
++/*
++ * MICL DGAIN volume control:
++ * from -97dB to 30dB in 0.5 dB steps
++ * */
++static const DECLARE_TLV_DB_SCALE(micl_dgain_tlv, -9700, 50, 0);
++
++/*
++ * MICL DGAIN volume control:
++ * from -97dB to 30dB in 0.5 dB steps
++ * */
++static const DECLARE_TLV_DB_SCALE(micr_dgain_tlv, -9700, 50, 0);
++
++/*
++ * HPOUTL AGAIN volume control:
++ * from -39dB to 6dB in 1.5 dB steps
++ * */
++static const DECLARE_TLV_DB_SCALE(hpoutl_again_tlv, -3900, 150, 0);
++
++/*
++ * HPOUTL DGAIN volume control:
++ * from -120dB to 7dB in 0.5 dB steps
++ * */
++static const DECLARE_TLV_DB_SCALE(hpoutl_dgain_tlv, -12000, 50, 0);
++
++static const struct snd_kcontrol_new icodec_controls[] = {
++#if 1
++	SOC_SINGLE_EXT_TLV("ALCL GAIN", TS_CODEC_CANACR_26, 0, 0x1f, 0 , icodec_controls_get, icodec_controls_put, alcl_gain_tlv),
++	SOC_SINGLE_EXT_TLV("ALCR GAIN", TS_CODEC_CANACR2_27, 0, 0x1f, 0 , icodec_controls_get, icodec_controls_put, alcr_gain_tlv),
++//	SOC_SINGLE_EXT_TLV("Left ADC Digital Volume", TS_CODEC_CAVR_08, 0, 0xff, 0 , icodec_controls_get, icodec_controls_put, micl_dgain_tlv),
++//	SOC_SINGLE_EXT_TLV("Right ADC Digital Volume", TS_CODEC_CGAINLR_09, 0, 0xff, 0 , icodec_controls_get, icodec_controls_put, micr_dgain_tlv),
++	SOC_SINGLE_EXT_TLV("HPOUTL DGAIN", TS_CODEC_CDCR2_06, 0, 0xff, 0 , icodec_controls_get, icodec_controls_put, hpoutl_dgain_tlv),
++	SOC_SINGLE_EXT_TLV("HPOUTL AGAIN", TS_CODEC_CHR_2b, 0, 0x1f, 0 , icodec_controls_get, icodec_controls_put, hpoutl_again_tlv),
++	SOC_SINGLE_EXT("MICBIAS", TS_CODEC_CAACR_22, 0, 0x7, 0 , icodec_controls_get, icodec_controls_put),
++	SOC_SINGLE_EXT("MIC HPF SWITCH", TS_CODEC_CGAINLR_0a, 2, 1, 0 , icodec_controls_get, icodec_controls_put),
++#else
++	SOC_SINGLE_TLV("ALCL GAIN MAX", TS_CODEC_CAFG_49, 3, 7, 0 , alcl_gain_max_tlv),
++	SOC_SINGLE_TLV("ALCL GAIN MIN", TS_CODEC_CAFG_49, 0, 7, 0 , alcl_gain_min_tlv),
++	SOC_SINGLE_TLV("ALCR GAIN MAX", TS_CODEC_CAFG_59, 3, 7, 0 , alcr_gain_max_tlv),
++	SOC_SINGLE_TLV("ALCR GAIN MIN", TS_CODEC_CAFG_59, 0, 7, 0 , alcr_gain_min_tlv),
++	SOC_SINGLE_TLV("ALCL GAIN", TS_CODEC_CANACR_26, 0, 0x1f, 0 ,alcl_gain_tlv),
++	SOC_SINGLE_TLV("ALCR GAIN", TS_CODEC_CANACR2_27, 0, 0x1f, 0 ,alcr_gain_tlv),
++	SOC_SINGLE_TLV("MICL DGAIN", TS_CODEC_CAVR_08, 0, 0xff, 0 ,micl_dgain_tlv),
++	SOC_SINGLE_TLV("MICR DGAIN", TS_CODEC_CGAINLR_09, 0, 0xff, 0 ,micr_dgain_tlv),
++	SOC_SINGLE_TLV("HPOUTL DGAIN", TS_CODEC_CDCR2_06, 0, 0xff, 0 ,hpoutl_dgain_tlv),
++	SOC_SINGLE_TLV("HPOUTL AGAIN", TS_CODEC_CHR_2b, 0, 0x1f, 0 ,hpoutl_again_tlv),
++	SOC_SINGLE("MICL GAIN", TS_CODEC_CMICGAINR_24, 6, 0x3, 0),
++	SOC_SINGLE("MICR GAIN", TS_CODEC_CMICGAINR_24, 4, 0x3, 0),
++	SOC_SINGLE("MICBIAS", TS_CODEC_CAACR_22, 0, 0x7, 0),
++	SOC_SINGLE("MIC HPF SWITCH", TS_CODEC_CGAINLR_0a, 2, 1, 0),
++	SOC_SINGLE_EXT("ALCL GAIN AUTO", 0, 0, 1, 0 , icodec_controls_get, icodec_controls_put),
++	SOC_SINGLE_EXT("ALCR GAIN AUTO", 0, 0, 1, 0 , icodec_controls_get, icodec_controls_put),
++#endif
++};
++
++static const struct snd_soc_dapm_widget icodec_widgets[] = {
++	SND_SOC_DAPM_AIF_OUT("SDTO", "Capture", 0, SND_SOC_NOPM, 0, 0),
++	SND_SOC_DAPM_AIF_IN("SDTI", "Playback", 0, SND_SOC_NOPM, 0, 0),
++	SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),/*pw*/
++	SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 0, 0),
++	SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
++	SND_SOC_DAPM_ADC("ALCL", NULL, SND_SOC_NOPM, 0, 0),
++	SND_SOC_DAPM_ADC("ALCR", NULL, SND_SOC_NOPM, 0, 0),
++	SND_SOC_DAPM_SPK("Speaker", icodec_spk_power),
++	SND_SOC_DAPM_OUTPUT("HPOUTL"),
++	SND_SOC_DAPM_INPUT("MICL"),
++	SND_SOC_DAPM_INPUT("MICR"),
++};
++
++static const struct snd_soc_dapm_route icodec_route[] = {
++	{"DACL",		NULL,	"SDTI"},
++	{"HPOUTL",		NULL,	"DACL"},
++	{"Speaker",		NULL,	"HPOUTL"},
++	{"SDTO",		NULL,	"ADCL"},
++	{"ADCL",		NULL,	"ALCL"},
++	{"ALCL",		NULL,	"MICL"},
++	{"SDTO",		NULL,	"ADCR"},
++	{"ADCR",		NULL,	"ALCR"},
++	{"ALCR",		NULL,	"MICR"},
++};
++
++static struct snd_soc_component_driver soc_codec_dev_icodec_component = {
++	.probe = 	icodec_probe,
++	.remove = 	icodec_remove,
++#ifdef CONFIG_PM
++	.suspend =	icodec_suspend,
++	.resume =	icodec_resume,
++#endif
++
++	.read = 	icodec_read,
++	.write = 	icodec_write,
++	//.reg_word_size = sizeof(u32),
++
++	.controls = 	icodec_controls,
++	.num_controls = ARRAY_SIZE(icodec_controls),
++	.dapm_widgets = icodec_widgets,
++	.num_dapm_widgets = ARRAY_SIZE(icodec_widgets),
++	.dapm_routes = icodec_route,
++	.num_dapm_routes = ARRAY_SIZE(icodec_route),
++};
++
++static int icodec_platform_probe(struct platform_device *pdev)
++{
++	struct icodec *icodec = NULL;
++	struct resource *res;
++	enum of_gpio_flags flags;
++	int ret = 0;
++
++	icodec = (struct icodec*)devm_kzalloc(&pdev->dev,
++			sizeof(struct icodec), GFP_KERNEL);
++	if (!icodec)
++		return -ENOMEM;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	icodec->io_base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(icodec->io_base)) {
++		dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
++		return PTR_ERR(icodec->io_base);
++	}
++
++	icodec->spk_gpio = of_get_named_gpio_flags(pdev->dev.of_node, "ingenic,spken-gpio", 0, &flags);
++	icodec->sgm8903_gpio = of_get_named_gpio_flags(pdev->dev.of_node, "ingenic,sgm8903en-gpio", 0, &flags);
++	if (gpio_is_valid(icodec->spk_gpio) && gpio_is_valid(icodec->sgm8903_gpio)) {
++		unsigned long init_flags;
++		icodec->spk_en_level = (flags == OF_GPIO_ACTIVE_LOW ? 0 : 1);
++		init_flags = (flags == OF_GPIO_ACTIVE_LOW ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW);
++		ret = devm_gpio_request_one(&pdev->dev, icodec->spk_gpio, init_flags, "Speaker_en");
++		if (ret)
++			pr_warn("Speaker enable pin(%d) request failed\n",icodec->spk_gpio);
++		else
++			pr_info("Speaker enable pin(%d) request ok\n", icodec->spk_gpio);
++
++		ret = devm_gpio_request_one(&pdev->dev, icodec->sgm8903_gpio, init_flags, "Sgm8903_en");
++		if (ret)
++			pr_warn("icodec: SGM8903 enable pin(%d) request failed\n",icodec->sgm8903_gpio);
++		else
++			pr_info("icodec: SGM8903 enable pin(%d) request ok\n", icodec->sgm8903_gpio);
++
++	}
++
++	icodec->dev = &pdev->dev;
++	icodec->alcl_gain = 0x1f;	//left record gain 0-0x1f
++	icodec->alcr_gain = 0x1f;	//right record gain 0-0x1f
++	icodec->hpoutl_again = 0x18;	//replay analog gain 0-0x1f
++	icodec->hpoutl_dgain = 0xf1;	//replay digital gain 0-0xff
++	icodec->micbias = 0;
++
++	spin_lock_init(&icodec->io_lock);
++	platform_set_drvdata(pdev, (void *)icodec);
++
++	ret = snd_soc_register_component(&pdev->dev,
++			&soc_codec_dev_icodec_component, &icodec_codec_dai, 1);
++	if (ret) {
++		dev_err(&pdev->dev, "Faild to register codec\n");
++		platform_set_drvdata(pdev, NULL);
++		return ret;
++	}
++
++	dev_info(&pdev->dev, "codec icodec platfrom probe success\n");
++	return 0;
++}
++
++static int icodec_platform_remove(struct platform_device *pdev)
++{
++	dev_info(&pdev->dev, "codec icodec platform remove\n");
++	snd_soc_unregister_component(&pdev->dev);
++	platform_set_drvdata(pdev, NULL);
++	return 0;
++}
++
++static const struct of_device_id codec_dt_match[] = {
++	{ .compatible = "ingenic,icodec", .data = NULL },
++	{},
++};
++MODULE_DEVICE_TABLE(of, codec_dt_match);
++
++static struct platform_driver icodec_codec_driver = {
++	.driver = {
++		.name = "icodec",
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(codec_dt_match),
++	},
++	.probe = icodec_platform_probe,
++	.remove = icodec_platform_remove,
++};
++
++
++static int icodec_modinit(void)
++{
++	return platform_driver_register(&icodec_codec_driver);
++}
++module_init(icodec_modinit);
++
++static void icodec_exit(void)
++{
++	platform_driver_unregister(&icodec_codec_driver);
++}
++module_exit(icodec_exit);
++
++MODULE_DESCRIPTION("Icodec Codec Driver");
++MODULE_AUTHOR("zhxiao<zhihao.xiao@ingenic.com>");
++MODULE_LICENSE("GPL");
+diff --git a/net/wireless/core.c b/net/wireless/core.c
+index 3b25b7889..14063f2c5 100644
+--- a/net/wireless/core.c
++++ b/net/wireless/core.c
+@@ -884,7 +884,7 @@ int wiphy_register(struct wiphy *wiphy)
+ 		WARN_ON(1);
+ 		return -EINVAL;
+ 	}
+-
++#if 0 /* To support wifi. */
+ 	for (i = 0; i < rdev->wiphy.n_vendor_commands; i++) {
+ 		/*
+ 		 * Validate we have a policy (can be explicitly set to
+@@ -897,6 +897,7 @@ int wiphy_register(struct wiphy *wiphy)
+ 			    !rdev->wiphy.vendor_commands[i].dumpit))
+ 			return -EINVAL;
+ 	}
++#endif
+ 
+ #ifdef CONFIG_PM
+ 	if (WARN_ON(rdev->wiphy.wowlan && rdev->wiphy.wowlan->n_patterns &&
+diff --git a/scripts/Makefile b/scripts/Makefile
+index 9adb6d247..877880612 100644
+--- a/scripts/Makefile
++++ b/scripts/Makefile
+@@ -14,8 +14,9 @@ hostprogs-always-$(CONFIG_ASN1)				+= asn1_compiler
+ hostprogs-always-$(CONFIG_MODULE_SIG_FORMAT)		+= sign-file
+ hostprogs-always-$(CONFIG_SYSTEM_TRUSTED_KEYRING)	+= extract-cert
+ hostprogs-always-$(CONFIG_SYSTEM_EXTRA_CERTIFICATE)	+= insert-sys-cert
+-hostprogs-always-$(CONFIG_SYSTEM_REVOCATION_LIST)	+= extract-cert
++hostprogs-always-$(CONFIG_TRUE_COLOR_LOGO) += pic2logo
+ 
++HOSTLDLIBS_pic2logo = -lm
+ HOSTCFLAGS_sorttable.o = -I$(srctree)/tools/include
+ HOSTCFLAGS_asn1_compiler.o = -I$(srctree)/include
+ HOSTCFLAGS_sign-file.o = $(CRYPTO_CFLAGS)
+diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
+index 53aa3e18c..8aab0dcb0 100644
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -213,9 +213,13 @@ cpp_flags      = -Wp,-MMD,$(depfile) $(NOSTDINC_FLAGS) $(LINUXINCLUDE)     \
+ ld_flags       = $(KBUILD_LDFLAGS) $(ldflags-y) $(LDFLAGS_$(@F))
+ 
+ DTC_INCLUDE    := $(srctree)/scripts/dtc/include-prefixes
++DTC_INCLUDE_ROOT   := $(objtree)/include
++DTC_INCLUDE_SRC := $(srctree)/include
+ 
+ dtc_cpp_flags  = -Wp,-MMD,$(depfile).pre.tmp -nostdinc                    \
+ 		 $(addprefix -I,$(DTC_INCLUDE))                          \
++		 $(addprefix -I,$(DTC_INCLUDE_ROOT))                          \
++		 $(addprefix -I,$(DTC_INCLUDE_SRC))                          \
+ 		 -undef -D__DTS__
+ 
+ # Useful for describing the dependency of composite objects
+diff --git a/scripts/pic2logo-include/stb_image/stb_image.h b/scripts/pic2logo-include/stb_image/stb_image.h
+new file mode 100644
+index 000000000..00e766689
+--- /dev/null
++++ b/scripts/pic2logo-include/stb_image/stb_image.h
+@@ -0,0 +1,7464 @@
++/* stb_image - v2.19 - public domain image loader - http://nothings.org/stb
++                                  no warranty implied; use at your own risk
++
++   Do this:
++      #define STB_IMAGE_IMPLEMENTATION
++   before you include this file in *one* C or C++ file to create the implementation.
++
++   // i.e. it should look like this:
++   #include ...
++   #include ...
++   #include ...
++   #define STB_IMAGE_IMPLEMENTATION
++   #include "stb_image.h"
++
++   You can #define STBI_ASSERT(x) before the #include to avoid using assert.h.
++   And #define STBI_MALLOC, STBI_REALLOC, and STBI_FREE to avoid using malloc,realloc,free
++
++
++   QUICK NOTES:
++      Primarily of interest to game developers and other people who can
++          avoid problematic images and only need the trivial interface
++
++      JPEG baseline & progressive (12 bpc/arithmetic not supported, same as stock IJG lib)
++      PNG 1/2/4/8/16-bit-per-channel
++
++      TGA (not sure what subset, if a subset)
++      BMP non-1bpp, non-RLE
++      PSD (composited view only, no extra channels, 8/16 bit-per-channel)
++
++      GIF (*comp always reports as 4-channel)
++      HDR (radiance rgbE format)
++      PIC (Softimage PIC)
++      PNM (PPM and PGM binary only)
++
++      Animated GIF still needs a proper API, but here's one way to do it:
++          http://gist.github.com/urraka/685d9a6340b26b830d49
++
++      - decode from memory or through FILE (define STBI_NO_STDIO to remove code)
++      - decode from arbitrary I/O callbacks
++      - SIMD acceleration on x86/x64 (SSE2) and ARM (NEON)
++
++   Full documentation under "DOCUMENTATION" below.
++
++
++LICENSE
++
++  See end of file for license information.
++
++RECENT REVISION HISTORY:
++
++      2.19  (2018-02-11) fix warning
++      2.18  (2018-01-30) fix warnings
++      2.17  (2018-01-29) bugfix, 1-bit BMP, 16-bitness query, fix warnings
++      2.16  (2017-07-23) all functions have 16-bit variants; optimizations; bugfixes
++      2.15  (2017-03-18) fix png-1,2,4; all Imagenet JPGs; no runtime SSE detection on GCC
++      2.14  (2017-03-03) remove deprecated STBI_JPEG_OLD; fixes for Imagenet JPGs
++      2.13  (2016-12-04) experimental 16-bit API, only for PNG so far; fixes
++      2.12  (2016-04-02) fix typo in 2.11 PSD fix that caused crashes
++      2.11  (2016-04-02) 16-bit PNGS; enable SSE2 in non-gcc x64
++                         RGB-format JPEG; remove white matting in PSD;
++                         allocate large structures on the stack;
++                         correct channel count for PNG & BMP
++      2.10  (2016-01-22) avoid warning introduced in 2.09
++      2.09  (2016-01-16) 16-bit TGA; comments in PNM files; STBI_REALLOC_SIZED
++
++   See end of file for full revision history.
++
++
++ ============================    Contributors    =========================
++
++ Image formats                          Extensions, features
++    Sean Barrett (jpeg, png, bmp)          Jetro Lauha (stbi_info)
++    Nicolas Schulz (hdr, psd)              Martin "SpartanJ" Golini (stbi_info)
++    Jonathan Dummer (tga)                  James "moose2000" Brown (iPhone PNG)
++    Jean-Marc Lienher (gif)                Ben "Disch" Wenger (io callbacks)
++    Tom Seddon (pic)                       Omar Cornut (1/2/4-bit PNG)
++    Thatcher Ulrich (psd)                  Nicolas Guillemot (vertical flip)
++    Ken Miller (pgm, ppm)                  Richard Mitton (16-bit PSD)
++    github:urraka (animated gif)           Junggon Kim (PNM comments)
++    Christopher Forseth (animated gif)     Daniel Gibson (16-bit TGA)
++                                           socks-the-fox (16-bit PNG)
++                                           Jeremy Sawicki (handle all ImageNet JPGs)
++ Optimizations & bugfixes                  Mikhail Morozov (1-bit BMP)
++    Fabian "ryg" Giesen                    Anael Seghezzi (is-16-bit query)
++    Arseny Kapoulkine
++    John-Mark Allen
++
++ Bug & warning fixes
++    Marc LeBlanc            David Woo          Guillaume George   Martins Mozeiko
++    Christpher Lloyd        Jerry Jansson      Joseph Thomson     Phil Jordan
++    Dave Moore              Roy Eltham         Hayaki Saito       Nathan Reed
++    Won Chun                Luke Graham        Johan Duparc       Nick Verigakis
++    the Horde3D community   Thomas Ruf         Ronny Chevalier    github:rlyeh
++    Janez Zemva             John Bartholomew   Michal Cichon      github:romigrou
++    Jonathan Blow           Ken Hamada         Tero Hanninen      github:svdijk
++    Laurent Gomila          Cort Stratton      Sergio Gonzalez    github:snagar
++    Aruelien Pocheville     Thibault Reuille   Cass Everitt       github:Zelex
++    Ryamond Barbiero        Paul Du Bois       Engin Manap        github:grim210
++    Aldo Culquicondor       Philipp Wiesemann  Dale Weiler        github:sammyhw
++    Oriol Ferrer Mesia      Josh Tobin         Matthew Gregan     github:phprus
++    Julian Raschke          Gregory Mullen     Baldur Karlsson    github:poppolopoppo
++    Christian Floisand      Kevin Schmidt                         github:darealshinji
++    Blazej Dariusz Roszkowski                                     github:Michaelangel007
++*/
++
++#ifndef STBI_INCLUDE_STB_IMAGE_H
++#define STBI_INCLUDE_STB_IMAGE_H
++
++// DOCUMENTATION
++//
++// Limitations:
++//    - no 12-bit-per-channel JPEG
++//    - no JPEGs with arithmetic coding
++//    - GIF always returns *comp=4
++//
++// Basic usage (see HDR discussion below for HDR usage):
++//    int x,y,n;
++//    unsigned char *data = stbi_load(filename, &x, &y, &n, 0);
++//    // ... process data if not NULL ...
++//    // ... x = width, y = height, n = # 8-bit components per pixel ...
++//    // ... replace '0' with '1'..'4' to force that many components per pixel
++//    // ... but 'n' will always be the number that it would have been if you said 0
++//    stbi_image_free(data)
++//
++// Standard parameters:
++//    int *x                 -- outputs image width in pixels
++//    int *y                 -- outputs image height in pixels
++//    int *channels_in_file  -- outputs # of image components in image file
++//    int desired_channels   -- if non-zero, # of image components requested in result
++//
++// The return value from an image loader is an 'unsigned char *' which points
++// to the pixel data, or NULL on an allocation failure or if the image is
++// corrupt or invalid. The pixel data consists of *y scanlines of *x pixels,
++// with each pixel consisting of N interleaved 8-bit components; the first
++// pixel pointed to is top-left-most in the image. There is no padding between
++// image scanlines or between pixels, regardless of format. The number of
++// components N is 'desired_channels' if desired_channels is non-zero, or
++// *channels_in_file otherwise. If desired_channels is non-zero,
++// *channels_in_file has the number of components that _would_ have been
++// output otherwise. E.g. if you set desired_channels to 4, you will always
++// get RGBA output, but you can check *channels_in_file to see if it's trivially
++// opaque because e.g. there were only 3 channels in the source image.
++//
++// An output image with N components has the following components interleaved
++// in this order in each pixel:
++//
++//     N=#comp     components
++//       1           grey
++//       2           grey, alpha
++//       3           red, green, blue
++//       4           red, green, blue, alpha
++//
++// If image loading fails for any reason, the return value will be NULL,
++// and *x, *y, *channels_in_file will be unchanged. The function
++// stbi_failure_reason() can be queried for an extremely brief, end-user
++// unfriendly explanation of why the load failed. Define STBI_NO_FAILURE_STRINGS
++// to avoid compiling these strings at all, and STBI_FAILURE_USERMSG to get slightly
++// more user-friendly ones.
++//
++// Paletted PNG, BMP, GIF, and PIC images are automatically depalettized.
++//
++// ===========================================================================
++//
++// Philosophy
++//
++// stb libraries are designed with the following priorities:
++//
++//    1. easy to use
++//    2. easy to maintain
++//    3. good performance
++//
++// Sometimes I let "good performance" creep up in priority over "easy to maintain",
++// and for best performance I may provide less-easy-to-use APIs that give higher
++// performance, in addition to the easy to use ones. Nevertheless, it's important
++// to keep in mind that from the standpoint of you, a client of this library,
++// all you care about is #1 and #3, and stb libraries DO NOT emphasize #3 above all.
++//
++// Some secondary priorities arise directly from the first two, some of which
++// make more explicit reasons why performance can't be emphasized.
++//
++//    - Portable ("ease of use")
++//    - Small source code footprint ("easy to maintain")
++//    - No dependencies ("ease of use")
++//
++// ===========================================================================
++//
++// I/O callbacks
++//
++// I/O callbacks allow you to read from arbitrary sources, like packaged
++// files or some other source. Data read from callbacks are processed
++// through a small internal buffer (currently 128 bytes) to try to reduce
++// overhead.
++//
++// The three functions you must define are "read" (reads some bytes of data),
++// "skip" (skips some bytes of data), "eof" (reports if the stream is at the end).
++//
++// ===========================================================================
++//
++// SIMD support
++//
++// The JPEG decoder will try to automatically use SIMD kernels on x86 when
++// supported by the compiler. For ARM Neon support, you must explicitly
++// request it.
++//
++// (The old do-it-yourself SIMD API is no longer supported in the current
++// code.)
++//
++// On x86, SSE2 will automatically be used when available based on a run-time
++// test; if not, the generic C versions are used as a fall-back. On ARM targets,
++// the typical path is to have separate builds for NEON and non-NEON devices
++// (at least this is true for iOS and Android). Therefore, the NEON support is
++// toggled by a build flag: define STBI_NEON to get NEON loops.
++//
++// If for some reason you do not want to use any of SIMD code, or if
++// you have issues compiling it, you can disable it entirely by
++// defining STBI_NO_SIMD.
++//
++// ===========================================================================
++//
++// HDR image support   (disable by defining STBI_NO_HDR)
++//
++// stb_image now supports loading HDR images in general, and currently
++// the Radiance .HDR file format, although the support is provided
++// generically. You can still load any file through the existing interface;
++// if you attempt to load an HDR file, it will be automatically remapped to
++// LDR, assuming gamma 2.2 and an arbitrary scale factor defaulting to 1;
++// both of these constants can be reconfigured through this interface:
++//
++//     stbi_hdr_to_ldr_gamma(2.2f);
++//     stbi_hdr_to_ldr_scale(1.0f);
++//
++// (note, do not use _inverse_ constants; stbi_image will invert them
++// appropriately).
++//
++// Additionally, there is a new, parallel interface for loading files as
++// (linear) floats to preserve the full dynamic range:
++//
++//    float *data = stbi_loadf(filename, &x, &y, &n, 0);
++//
++// If you load LDR images through this interface, those images will
++// be promoted to floating point values, run through the inverse of
++// constants corresponding to the above:
++//
++//     stbi_ldr_to_hdr_scale(1.0f);
++//     stbi_ldr_to_hdr_gamma(2.2f);
++//
++// Finally, given a filename (or an open file or memory block--see header
++// file for details) containing image data, you can query for the "most
++// appropriate" interface to use (that is, whether the image is HDR or
++// not), using:
++//
++//     stbi_is_hdr(char *filename);
++//
++// ===========================================================================
++//
++// iPhone PNG support:
++//
++// By default we convert iphone-formatted PNGs back to RGB, even though
++// they are internally encoded differently. You can disable this conversion
++// by by calling stbi_convert_iphone_png_to_rgb(0), in which case
++// you will always just get the native iphone "format" through (which
++// is BGR stored in RGB).
++//
++// Call stbi_set_unpremultiply_on_load(1) as well to force a divide per
++// pixel to remove any premultiplied alpha *only* if the image file explicitly
++// says there's premultiplied data (currently only happens in iPhone images,
++// and only if iPhone convert-to-rgb processing is on).
++//
++// ===========================================================================
++//
++// ADDITIONAL CONFIGURATION
++//
++//  - You can suppress implementation of any of the decoders to reduce
++//    your code footprint by #defining one or more of the following
++//    symbols before creating the implementation.
++//
++//        STBI_NO_JPEG
++//        STBI_NO_PNG
++//        STBI_NO_BMP
++//        STBI_NO_PSD
++//        STBI_NO_TGA
++//        STBI_NO_GIF
++//        STBI_NO_HDR
++//        STBI_NO_PIC
++//        STBI_NO_PNM   (.ppm and .pgm)
++//
++//  - You can request *only* certain decoders and suppress all other ones
++//    (this will be more forward-compatible, as addition of new decoders
++//    doesn't require you to disable them explicitly):
++//
++//        STBI_ONLY_JPEG
++//        STBI_ONLY_PNG
++//        STBI_ONLY_BMP
++//        STBI_ONLY_PSD
++//        STBI_ONLY_TGA
++//        STBI_ONLY_GIF
++//        STBI_ONLY_HDR
++//        STBI_ONLY_PIC
++//        STBI_ONLY_PNM   (.ppm and .pgm)
++//
++//   - If you use STBI_NO_PNG (or _ONLY_ without PNG), and you still
++//     want the zlib decoder to be available, #define STBI_SUPPORT_ZLIB
++//
++
++
++#ifndef STBI_NO_STDIO
++#include <stdio.h>
++#endif // STBI_NO_STDIO
++
++#define STBI_VERSION 1
++
++enum
++{
++   STBI_default = 0, // only used for desired_channels
++
++   STBI_grey       = 1,
++   STBI_grey_alpha = 2,
++   STBI_rgb        = 3,
++   STBI_rgb_alpha  = 4
++};
++
++typedef unsigned char stbi_uc;
++typedef unsigned short stbi_us;
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#ifdef STB_IMAGE_STATIC
++#define STBIDEF static inline
++#else
++#define STBIDEF extern
++#endif
++
++//////////////////////////////////////////////////////////////////////////////
++//
++// PRIMARY API - works on images of any type
++//
++
++//
++// load image by filename, open file, or memory buffer
++//
++
++typedef struct
++{
++   int      (*read)  (void *user,char *data,int size);   // fill 'data' with 'size' bytes.  return number of bytes actually read
++   void     (*skip)  (void *user,int n);                 // skip the next 'n' bytes, or 'unget' the last -n bytes if negative
++   int      (*eof)   (void *user);                       // returns nonzero if we are at end of file/data
++} stbi_io_callbacks;
++
++////////////////////////////////////
++//
++// 8-bits-per-channel interface
++//
++
++STBIDEF stbi_uc *stbi_load_from_memory   (stbi_uc           const *buffer, int len   , int *x, int *y, int *channels_in_file, int desired_channels);
++STBIDEF stbi_uc *stbi_load_from_callbacks(stbi_io_callbacks const *clbk  , void *user, int *x, int *y, int *channels_in_file, int desired_channels);
++#ifndef STBI_NO_GIF
++STBIDEF stbi_uc *stbi_load_gif_from_memory(stbi_uc const *buffer, int len, int **delays, int *x, int *y, int *z, int *comp, int req_comp);
++#endif
++
++
++#ifndef STBI_NO_STDIO
++STBIDEF stbi_uc *stbi_load            (char const *filename, int *x, int *y, int *channels_in_file, int desired_channels);
++STBIDEF stbi_uc *stbi_load_from_file  (FILE *f, int *x, int *y, int *channels_in_file, int desired_channels);
++// for stbi_load_from_file, file pointer is left pointing immediately after image
++#endif
++
++////////////////////////////////////
++//
++// 16-bits-per-channel interface
++//
++
++STBIDEF stbi_us *stbi_load_16_from_memory   (stbi_uc const *buffer, int len, int *x, int *y, int *channels_in_file, int desired_channels);
++STBIDEF stbi_us *stbi_load_16_from_callbacks(stbi_io_callbacks const *clbk, void *user, int *x, int *y, int *channels_in_file, int desired_channels);
++
++#ifndef STBI_NO_STDIO
++STBIDEF stbi_us *stbi_load_16          (char const *filename, int *x, int *y, int *channels_in_file, int desired_channels);
++STBIDEF stbi_us *stbi_load_from_file_16(FILE *f, int *x, int *y, int *channels_in_file, int desired_channels);
++#endif
++
++////////////////////////////////////
++//
++// float-per-channel interface
++//
++#ifndef STBI_NO_LINEAR
++   STBIDEF float *stbi_loadf_from_memory     (stbi_uc const *buffer, int len, int *x, int *y, int *channels_in_file, int desired_channels);
++   STBIDEF float *stbi_loadf_from_callbacks  (stbi_io_callbacks const *clbk, void *user, int *x, int *y,  int *channels_in_file, int desired_channels);
++
++   #ifndef STBI_NO_STDIO
++   STBIDEF float *stbi_loadf            (char const *filename, int *x, int *y, int *channels_in_file, int desired_channels);
++   STBIDEF float *stbi_loadf_from_file  (FILE *f, int *x, int *y, int *channels_in_file, int desired_channels);
++   #endif
++#endif
++
++#ifndef STBI_NO_HDR
++   STBIDEF void   stbi_hdr_to_ldr_gamma(float gamma);
++   STBIDEF void   stbi_hdr_to_ldr_scale(float scale);
++#endif // STBI_NO_HDR
++
++#ifndef STBI_NO_LINEAR
++   STBIDEF void   stbi_ldr_to_hdr_gamma(float gamma);
++   STBIDEF void   stbi_ldr_to_hdr_scale(float scale);
++#endif // STBI_NO_LINEAR
++
++// stbi_is_hdr is always defined, but always returns false if STBI_NO_HDR
++STBIDEF int    stbi_is_hdr_from_callbacks(stbi_io_callbacks const *clbk, void *user);
++STBIDEF int    stbi_is_hdr_from_memory(stbi_uc const *buffer, int len);
++#ifndef STBI_NO_STDIO
++STBIDEF int      stbi_is_hdr          (char const *filename);
++STBIDEF int      stbi_is_hdr_from_file(FILE *f);
++#endif // STBI_NO_STDIO
++
++
++// get a VERY brief reason for failure
++// NOT THREADSAFE
++STBIDEF const char *stbi_failure_reason  (void);
++
++// free the loaded image -- this is just free()
++STBIDEF void     stbi_image_free      (void *retval_from_stbi_load);
++
++// get image dimensions & components without fully decoding
++STBIDEF int      stbi_info_from_memory(stbi_uc const *buffer, int len, int *x, int *y, int *comp);
++STBIDEF int      stbi_info_from_callbacks(stbi_io_callbacks const *clbk, void *user, int *x, int *y, int *comp);
++STBIDEF int      stbi_is_16_bit_from_memory(stbi_uc const *buffer, int len);
++STBIDEF int      stbi_is_16_bit_from_callbacks(stbi_io_callbacks const *clbk, void *user);
++
++#ifndef STBI_NO_STDIO
++STBIDEF int      stbi_info               (char const *filename,     int *x, int *y, int *comp);
++STBIDEF int      stbi_info_from_file     (FILE *f,                  int *x, int *y, int *comp);
++STBIDEF int      stbi_is_16_bit          (char const *filename);
++STBIDEF int      stbi_is_16_bit_from_file(FILE *f);
++#endif
++
++
++
++// for image formats that explicitly notate that they have premultiplied alpha,
++// we just return the colors as stored in the file. set this flag to force
++// unpremultiplication. results are undefined if the unpremultiply overflow.
++STBIDEF void stbi_set_unpremultiply_on_load(int flag_true_if_should_unpremultiply);
++
++// indicate whether we should process iphone images back to canonical format,
++// or just pass them through "as-is"
++STBIDEF void stbi_convert_iphone_png_to_rgb(int flag_true_if_should_convert);
++
++// flip the image vertically, so the first pixel in the output array is the bottom left
++STBIDEF void stbi_set_flip_vertically_on_load(int flag_true_if_should_flip);
++
++// ZLIB client - used by PNG, available for other purposes
++
++STBIDEF char *stbi_zlib_decode_malloc_guesssize(const char *buffer, int len, int initial_size, int *outlen);
++STBIDEF char *stbi_zlib_decode_malloc_guesssize_headerflag(const char *buffer, int len, int initial_size, int *outlen, int parse_header);
++STBIDEF char *stbi_zlib_decode_malloc(const char *buffer, int len, int *outlen);
++STBIDEF int   stbi_zlib_decode_buffer(char *obuffer, int olen, const char *ibuffer, int ilen);
++
++STBIDEF char *stbi_zlib_decode_noheader_malloc(const char *buffer, int len, int *outlen);
++STBIDEF int   stbi_zlib_decode_noheader_buffer(char *obuffer, int olen, const char *ibuffer, int ilen);
++
++
++#ifdef __cplusplus
++}
++#endif
++
++//
++//
++////   end header file   /////////////////////////////////////////////////////
++#endif // STBI_INCLUDE_STB_IMAGE_H
++
++#ifdef STB_IMAGE_IMPLEMENTATION
++
++#if defined(STBI_ONLY_JPEG) || defined(STBI_ONLY_PNG) || defined(STBI_ONLY_BMP) \
++  || defined(STBI_ONLY_TGA) || defined(STBI_ONLY_GIF) || defined(STBI_ONLY_PSD) \
++  || defined(STBI_ONLY_HDR) || defined(STBI_ONLY_PIC) || defined(STBI_ONLY_PNM) \
++  || defined(STBI_ONLY_ZLIB)
++   #ifndef STBI_ONLY_JPEG
++   #define STBI_NO_JPEG
++   #endif
++   #ifndef STBI_ONLY_PNG
++   #define STBI_NO_PNG
++   #endif
++   #ifndef STBI_ONLY_BMP
++   #define STBI_NO_BMP
++   #endif
++   #ifndef STBI_ONLY_PSD
++   #define STBI_NO_PSD
++   #endif
++   #ifndef STBI_ONLY_TGA
++   #define STBI_NO_TGA
++   #endif
++   #ifndef STBI_ONLY_GIF
++   #define STBI_NO_GIF
++   #endif
++   #ifndef STBI_ONLY_HDR
++   #define STBI_NO_HDR
++   #endif
++   #ifndef STBI_ONLY_PIC
++   #define STBI_NO_PIC
++   #endif
++   #ifndef STBI_ONLY_PNM
++   #define STBI_NO_PNM
++   #endif
++#endif
++
++#if defined(STBI_NO_PNG) && !defined(STBI_SUPPORT_ZLIB) && !defined(STBI_NO_ZLIB)
++#define STBI_NO_ZLIB
++#endif
++
++
++#include <stdarg.h>
++#include <stddef.h> // ptrdiff_t on osx
++#include <stdlib.h>
++#include <string.h>
++#include <limits.h>
++
++#if !defined(STBI_NO_LINEAR) || !defined(STBI_NO_HDR)
++#include <math.h>  // ldexp, pow
++#endif
++
++#ifndef STBI_NO_STDIO
++#include <stdio.h>
++#endif
++
++#ifndef STBI_ASSERT
++#include <assert.h>
++#define STBI_ASSERT(x) assert(x)
++#endif
++
++
++#ifndef _MSC_VER
++   #ifdef __cplusplus
++   #define stbi_inline inline
++   #else
++   #define stbi_inline
++   #endif
++#else
++   #define stbi_inline __forceinline
++#endif
++
++
++#ifdef _MSC_VER
++typedef unsigned short stbi__uint16;
++typedef   signed short stbi__int16;
++typedef unsigned int   stbi__uint32;
++typedef   signed int   stbi__int32;
++#else
++#include <stdint.h>
++typedef uint16_t stbi__uint16;
++typedef int16_t  stbi__int16;
++typedef uint32_t stbi__uint32;
++typedef int32_t  stbi__int32;
++#endif
++
++// should produce compiler error if size is wrong
++typedef unsigned char validate_uint32[sizeof(stbi__uint32)==4 ? 1 : -1];
++
++#ifdef _MSC_VER
++#define STBI_NOTUSED(v)  (void)(v)
++#else
++#define STBI_NOTUSED(v)  (void)sizeof(v)
++#endif
++
++#ifdef _MSC_VER
++#define STBI_HAS_LROTL
++#endif
++
++#ifdef STBI_HAS_LROTL
++   #define stbi_lrot(x,y)  _lrotl(x,y)
++#else
++   #define stbi_lrot(x,y)  (((x) << (y)) | ((x) >> (32 - (y))))
++#endif
++
++#if defined(STBI_MALLOC) && defined(STBI_FREE) && (defined(STBI_REALLOC) || defined(STBI_REALLOC_SIZED))
++// ok
++#elif !defined(STBI_MALLOC) && !defined(STBI_FREE) && !defined(STBI_REALLOC) && !defined(STBI_REALLOC_SIZED)
++// ok
++#else
++#error "Must define all or none of STBI_MALLOC, STBI_FREE, and STBI_REALLOC (or STBI_REALLOC_SIZED)."
++#endif
++
++#ifndef STBI_MALLOC
++#define STBI_MALLOC(sz)           malloc(sz)
++#define STBI_REALLOC(p,newsz)     realloc(p,newsz)
++#define STBI_FREE(p)              free(p)
++#endif
++
++#ifndef STBI_REALLOC_SIZED
++#define STBI_REALLOC_SIZED(p,oldsz,newsz) STBI_REALLOC(p,newsz)
++#endif
++
++// x86/x64 detection
++#if defined(__x86_64__) || defined(_M_X64)
++#define STBI__X64_TARGET
++#elif defined(__i386) || defined(_M_IX86)
++#define STBI__X86_TARGET
++#endif
++
++#if defined(__GNUC__) && defined(STBI__X86_TARGET) && !defined(__SSE2__) && !defined(STBI_NO_SIMD)
++// gcc doesn't support sse2 intrinsics unless you compile with -msse2,
++// which in turn means it gets to use SSE2 everywhere. This is unfortunate,
++// but previous attempts to provide the SSE2 functions with runtime
++// detection caused numerous issues. The way architecture extensions are
++// exposed in GCC/Clang is, sadly, not really suited for one-file libs.
++// New behavior: if compiled with -msse2, we use SSE2 without any
++// detection; if not, we don't use it at all.
++#define STBI_NO_SIMD
++#endif
++
++#if defined(__MINGW32__) && defined(STBI__X86_TARGET) && !defined(STBI_MINGW_ENABLE_SSE2) && !defined(STBI_NO_SIMD)
++// Note that __MINGW32__ doesn't actually mean 32-bit, so we have to avoid STBI__X64_TARGET
++//
++// 32-bit MinGW wants ESP to be 16-byte aligned, but this is not in the
++// Windows ABI and VC++ as well as Windows DLLs don't maintain that invariant.
++// As a result, enabling SSE2 on 32-bit MinGW is dangerous when not
++// simultaneously enabling "-mstackrealign".
++//
++// See https://github.com/nothings/stb/issues/81 for more information.
++//
++// So default to no SSE2 on 32-bit MinGW. If you've read this far and added
++// -mstackrealign to your build settings, feel free to #define STBI_MINGW_ENABLE_SSE2.
++#define STBI_NO_SIMD
++#endif
++
++#if !defined(STBI_NO_SIMD) && (defined(STBI__X86_TARGET) || defined(STBI__X64_TARGET))
++#define STBI_SSE2
++#include <emmintrin.h>
++
++#ifdef _MSC_VER
++
++#if _MSC_VER >= 1400  // not VC6
++#include <intrin.h> // __cpuid
++static int stbi__cpuid3(void)
++{
++   int info[4];
++   __cpuid(info,1);
++   return info[3];
++}
++#else
++static int stbi__cpuid3(void)
++{
++   int res;
++   __asm {
++      mov  eax,1
++      cpuid
++      mov  res,edx
++   }
++   return res;
++}
++#endif
++
++#define STBI_SIMD_ALIGN(type, name) __declspec(align(16)) type name
++
++static int stbi__sse2_available(void)
++{
++   int info3 = stbi__cpuid3();
++   return ((info3 >> 26) & 1) != 0;
++}
++#else // assume GCC-style if not VC++
++#define STBI_SIMD_ALIGN(type, name) type name __attribute__((aligned(16)))
++
++static int stbi__sse2_available(void)
++{
++   // If we're even attempting to compile this on GCC/Clang, that means
++   // -msse2 is on, which means the compiler is allowed to use SSE2
++   // instructions at will, and so are we.
++   return 1;
++}
++#endif
++#endif
++
++// ARM NEON
++#if defined(STBI_NO_SIMD) && defined(STBI_NEON)
++#undef STBI_NEON
++#endif
++
++#ifdef STBI_NEON
++#include <arm_neon.h>
++// assume GCC or Clang on ARM targets
++#define STBI_SIMD_ALIGN(type, name) type name __attribute__((aligned(16)))
++#endif
++
++#ifndef STBI_SIMD_ALIGN
++#define STBI_SIMD_ALIGN(type, name) type name
++#endif
++
++///////////////////////////////////////////////
++//
++//  stbi__context struct and start_xxx functions
++
++// stbi__context structure is our basic context used by all images, so it
++// contains all the IO context, plus some basic image information
++typedef struct
++{
++   stbi__uint32 img_x, img_y;
++   int img_n, img_out_n;
++
++   stbi_io_callbacks io;
++   void *io_user_data;
++
++   int read_from_callbacks;
++   int buflen;
++   stbi_uc buffer_start[128];
++
++   stbi_uc *img_buffer, *img_buffer_end;
++   stbi_uc *img_buffer_original, *img_buffer_original_end;
++} stbi__context;
++
++
++static void stbi__refill_buffer(stbi__context *s);
++
++// initialize a memory-decode context
++static void stbi__start_mem(stbi__context *s, stbi_uc const *buffer, int len)
++{
++   s->io.read = NULL;
++   s->read_from_callbacks = 0;
++   s->img_buffer = s->img_buffer_original = (stbi_uc *) buffer;
++   s->img_buffer_end = s->img_buffer_original_end = (stbi_uc *) buffer+len;
++}
++
++// initialize a callback-based context
++static void stbi__start_callbacks(stbi__context *s, stbi_io_callbacks *c, void *user)
++{
++   s->io = *c;
++   s->io_user_data = user;
++   s->buflen = sizeof(s->buffer_start);
++   s->read_from_callbacks = 1;
++   s->img_buffer_original = s->buffer_start;
++   stbi__refill_buffer(s);
++   s->img_buffer_original_end = s->img_buffer_end;
++}
++
++#ifndef STBI_NO_STDIO
++
++static int stbi__stdio_read(void *user, char *data, int size)
++{
++   return (int) fread(data,1,size,(FILE*) user);
++}
++
++static void stbi__stdio_skip(void *user, int n)
++{
++   fseek((FILE*) user, n, SEEK_CUR);
++}
++
++static int stbi__stdio_eof(void *user)
++{
++   return feof((FILE*) user);
++}
++
++static stbi_io_callbacks stbi__stdio_callbacks =
++{
++   stbi__stdio_read,
++   stbi__stdio_skip,
++   stbi__stdio_eof,
++};
++
++static void stbi__start_file(stbi__context *s, FILE *f)
++{
++   stbi__start_callbacks(s, &stbi__stdio_callbacks, (void *) f);
++}
++
++//static void stop_file(stbi__context *s) { }
++
++#endif // !STBI_NO_STDIO
++
++static void stbi__rewind(stbi__context *s)
++{
++   // conceptually rewind SHOULD rewind to the beginning of the stream,
++   // but we just rewind to the beginning of the initial buffer, because
++   // we only use it after doing 'test', which only ever looks at at most 92 bytes
++   s->img_buffer = s->img_buffer_original;
++   s->img_buffer_end = s->img_buffer_original_end;
++}
++
++enum
++{
++   STBI_ORDER_RGB,
++   STBI_ORDER_BGR
++};
++
++typedef struct
++{
++   int bits_per_channel;
++   int num_channels;
++   int channel_order;
++} stbi__result_info;
++
++#ifndef STBI_NO_JPEG
++static int      stbi__jpeg_test(stbi__context *s);
++static void    *stbi__jpeg_load(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri);
++static int      stbi__jpeg_info(stbi__context *s, int *x, int *y, int *comp);
++#endif
++
++#ifndef STBI_NO_PNG
++static int      stbi__png_test(stbi__context *s);
++static void    *stbi__png_load(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri);
++static int      stbi__png_info(stbi__context *s, int *x, int *y, int *comp);
++static int      stbi__png_is16(stbi__context *s);
++#endif
++
++#ifndef STBI_NO_BMP
++static int      stbi__bmp_test(stbi__context *s);
++static void    *stbi__bmp_load(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri);
++static int      stbi__bmp_info(stbi__context *s, int *x, int *y, int *comp);
++#endif
++
++#ifndef STBI_NO_TGA
++static int      stbi__tga_test(stbi__context *s);
++static void    *stbi__tga_load(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri);
++static int      stbi__tga_info(stbi__context *s, int *x, int *y, int *comp);
++#endif
++
++#ifndef STBI_NO_PSD
++static int      stbi__psd_test(stbi__context *s);
++static void    *stbi__psd_load(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri, int bpc);
++static int      stbi__psd_info(stbi__context *s, int *x, int *y, int *comp);
++static int      stbi__psd_is16(stbi__context *s);
++#endif
++
++#ifndef STBI_NO_HDR
++static int      stbi__hdr_test(stbi__context *s);
++static float   *stbi__hdr_load(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri);
++static int      stbi__hdr_info(stbi__context *s, int *x, int *y, int *comp);
++#endif
++
++#ifndef STBI_NO_PIC
++static int      stbi__pic_test(stbi__context *s);
++static void    *stbi__pic_load(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri);
++static int      stbi__pic_info(stbi__context *s, int *x, int *y, int *comp);
++#endif
++
++#ifndef STBI_NO_GIF
++static int      stbi__gif_test(stbi__context *s);
++static void    *stbi__gif_load(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri);
++static void    *stbi__load_gif_main(stbi__context *s, int **delays, int *x, int *y, int *z, int *comp, int req_comp);
++static int      stbi__gif_info(stbi__context *s, int *x, int *y, int *comp);
++#endif
++
++#ifndef STBI_NO_PNM
++static int      stbi__pnm_test(stbi__context *s);
++static void    *stbi__pnm_load(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri);
++static int      stbi__pnm_info(stbi__context *s, int *x, int *y, int *comp);
++#endif
++
++// this is not threadsafe
++static const char *stbi__g_failure_reason;
++
++STBIDEF const char *stbi_failure_reason(void)
++{
++   return stbi__g_failure_reason;
++}
++
++static int stbi__err(const char *str)
++{
++   stbi__g_failure_reason = str;
++   return 0;
++}
++
++static void *stbi__malloc(size_t size)
++{
++    return STBI_MALLOC(size);
++}
++
++// stb_image uses ints pervasively, including for offset calculations.
++// therefore the largest decoded image size we can support with the
++// current code, even on 64-bit targets, is INT_MAX. this is not a
++// significant limitation for the intended use case.
++//
++// we do, however, need to make sure our size calculations don't
++// overflow. hence a few helper functions for size calculations that
++// multiply integers together, making sure that they're non-negative
++// and no overflow occurs.
++
++// return 1 if the sum is valid, 0 on overflow.
++// negative terms are considered invalid.
++static int stbi__addsizes_valid(int a, int b)
++{
++   if (b < 0) return 0;
++   // now 0 <= b <= INT_MAX, hence also
++   // 0 <= INT_MAX - b <= INTMAX.
++   // And "a + b <= INT_MAX" (which might overflow) is the
++   // same as a <= INT_MAX - b (no overflow)
++   return a <= INT_MAX - b;
++}
++
++// returns 1 if the product is valid, 0 on overflow.
++// negative factors are considered invalid.
++static int stbi__mul2sizes_valid(int a, int b)
++{
++   if (a < 0 || b < 0) return 0;
++   if (b == 0) return 1; // mul-by-0 is always safe
++   // portable way to check for no overflows in a*b
++   return a <= INT_MAX/b;
++}
++
++// returns 1 if "a*b + add" has no negative terms/factors and doesn't overflow
++static int stbi__mad2sizes_valid(int a, int b, int add)
++{
++   return stbi__mul2sizes_valid(a, b) && stbi__addsizes_valid(a*b, add);
++}
++
++// returns 1 if "a*b*c + add" has no negative terms/factors and doesn't overflow
++static int stbi__mad3sizes_valid(int a, int b, int c, int add)
++{
++   return stbi__mul2sizes_valid(a, b) && stbi__mul2sizes_valid(a*b, c) &&
++      stbi__addsizes_valid(a*b*c, add);
++}
++
++// returns 1 if "a*b*c*d + add" has no negative terms/factors and doesn't overflow
++#if !defined(STBI_NO_LINEAR) || !defined(STBI_NO_HDR)
++static int stbi__mad4sizes_valid(int a, int b, int c, int d, int add)
++{
++   return stbi__mul2sizes_valid(a, b) && stbi__mul2sizes_valid(a*b, c) &&
++      stbi__mul2sizes_valid(a*b*c, d) && stbi__addsizes_valid(a*b*c*d, add);
++}
++#endif
++
++// mallocs with size overflow checking
++static void *stbi__malloc_mad2(int a, int b, int add)
++{
++   if (!stbi__mad2sizes_valid(a, b, add)) return NULL;
++   return stbi__malloc(a*b + add);
++}
++
++static void *stbi__malloc_mad3(int a, int b, int c, int add)
++{
++   if (!stbi__mad3sizes_valid(a, b, c, add)) return NULL;
++   return stbi__malloc(a*b*c + add);
++}
++
++#if !defined(STBI_NO_LINEAR) || !defined(STBI_NO_HDR)
++static void *stbi__malloc_mad4(int a, int b, int c, int d, int add)
++{
++   if (!stbi__mad4sizes_valid(a, b, c, d, add)) return NULL;
++   return stbi__malloc(a*b*c*d + add);
++}
++#endif
++
++// stbi__err - error
++// stbi__errpf - error returning pointer to float
++// stbi__errpuc - error returning pointer to unsigned char
++
++#ifdef STBI_NO_FAILURE_STRINGS
++   #define stbi__err(x,y)  0
++#elif defined(STBI_FAILURE_USERMSG)
++   #define stbi__err(x,y)  stbi__err(y)
++#else
++   #define stbi__err(x,y)  stbi__err(x)
++#endif
++
++#define stbi__errpf(x,y)   ((float *)(size_t) (stbi__err(x,y)?NULL:NULL))
++#define stbi__errpuc(x,y)  ((unsigned char *)(size_t) (stbi__err(x,y)?NULL:NULL))
++
++STBIDEF void stbi_image_free(void *retval_from_stbi_load)
++{
++   STBI_FREE(retval_from_stbi_load);
++}
++
++#ifndef STBI_NO_LINEAR
++static float   *stbi__ldr_to_hdr(stbi_uc *data, int x, int y, int comp);
++#endif
++
++#ifndef STBI_NO_HDR
++static stbi_uc *stbi__hdr_to_ldr(float   *data, int x, int y, int comp);
++#endif
++
++static int stbi__vertically_flip_on_load = 0;
++
++STBIDEF void stbi_set_flip_vertically_on_load(int flag_true_if_should_flip)
++{
++    stbi__vertically_flip_on_load = flag_true_if_should_flip;
++}
++
++static void *stbi__load_main(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri, int bpc)
++{
++   memset(ri, 0, sizeof(*ri)); // make sure it's initialized if we add new fields
++   ri->bits_per_channel = 8; // default is 8 so most paths don't have to be changed
++   ri->channel_order = STBI_ORDER_RGB; // all current input & output are this, but this is here so we can add BGR order
++   ri->num_channels = 0;
++
++   #ifndef STBI_NO_JPEG
++   if (stbi__jpeg_test(s)) return stbi__jpeg_load(s,x,y,comp,req_comp, ri);
++   #endif
++   #ifndef STBI_NO_PNG
++   if (stbi__png_test(s))  return stbi__png_load(s,x,y,comp,req_comp, ri);
++   #endif
++   #ifndef STBI_NO_BMP
++   if (stbi__bmp_test(s))  return stbi__bmp_load(s,x,y,comp,req_comp, ri);
++   #endif
++   #ifndef STBI_NO_GIF
++   if (stbi__gif_test(s))  return stbi__gif_load(s,x,y,comp,req_comp, ri);
++   #endif
++   #ifndef STBI_NO_PSD
++   if (stbi__psd_test(s))  return stbi__psd_load(s,x,y,comp,req_comp, ri, bpc);
++   #endif
++   #ifndef STBI_NO_PIC
++   if (stbi__pic_test(s))  return stbi__pic_load(s,x,y,comp,req_comp, ri);
++   #endif
++   #ifndef STBI_NO_PNM
++   if (stbi__pnm_test(s))  return stbi__pnm_load(s,x,y,comp,req_comp, ri);
++   #endif
++
++   #ifndef STBI_NO_HDR
++   if (stbi__hdr_test(s)) {
++      float *hdr = stbi__hdr_load(s, x,y,comp,req_comp, ri);
++      return stbi__hdr_to_ldr(hdr, *x, *y, req_comp ? req_comp : *comp);
++   }
++   #endif
++
++   #ifndef STBI_NO_TGA
++   // test tga last because it's a crappy test!
++   if (stbi__tga_test(s))
++      return stbi__tga_load(s,x,y,comp,req_comp, ri);
++   #endif
++
++   return stbi__errpuc("unknown image type", "Image not of any known type, or corrupt");
++}
++
++static stbi_uc *stbi__convert_16_to_8(stbi__uint16 *orig, int w, int h, int channels)
++{
++   int i;
++   int img_len = w * h * channels;
++   stbi_uc *reduced;
++
++   reduced = (stbi_uc *) stbi__malloc(img_len);
++   if (reduced == NULL) return stbi__errpuc("outofmem", "Out of memory");
++
++   for (i = 0; i < img_len; ++i)
++      reduced[i] = (stbi_uc)((orig[i] >> 8) & 0xFF); // top half of each byte is sufficient approx of 16->8 bit scaling
++
++   STBI_FREE(orig);
++   return reduced;
++}
++
++static stbi__uint16 *stbi__convert_8_to_16(stbi_uc *orig, int w, int h, int channels)
++{
++   int i;
++   int img_len = w * h * channels;
++   stbi__uint16 *enlarged;
++
++   enlarged = (stbi__uint16 *) stbi__malloc(img_len*2);
++   if (enlarged == NULL) return (stbi__uint16 *) stbi__errpuc("outofmem", "Out of memory");
++
++   for (i = 0; i < img_len; ++i)
++      enlarged[i] = (stbi__uint16)((orig[i] << 8) + orig[i]); // replicate to high and low byte, maps 0->0, 255->0xffff
++
++   STBI_FREE(orig);
++   return enlarged;
++}
++
++static void stbi__vertical_flip(void *image, int w, int h, int bytes_per_pixel)
++{
++   int row;
++   size_t bytes_per_row = (size_t)w * bytes_per_pixel;
++   stbi_uc temp[2048];
++   stbi_uc *bytes = (stbi_uc *)image;
++
++   for (row = 0; row < (h>>1); row++) {
++      stbi_uc *row0 = bytes + row*bytes_per_row;
++      stbi_uc *row1 = bytes + (h - row - 1)*bytes_per_row;
++      // swap row0 with row1
++      size_t bytes_left = bytes_per_row;
++      while (bytes_left) {
++         size_t bytes_copy = (bytes_left < sizeof(temp)) ? bytes_left : sizeof(temp);
++         memcpy(temp, row0, bytes_copy);
++         memcpy(row0, row1, bytes_copy);
++         memcpy(row1, temp, bytes_copy);
++         row0 += bytes_copy;
++         row1 += bytes_copy;
++         bytes_left -= bytes_copy;
++      }
++   }
++}
++
++#ifndef STBI_NO_GIF
++static void stbi__vertical_flip_slices(void *image, int w, int h, int z, int bytes_per_pixel)
++{
++   int slice;
++   int slice_size = w * h * bytes_per_pixel;
++
++   stbi_uc *bytes = (stbi_uc *)image;
++   for (slice = 0; slice < z; ++slice) {
++      stbi__vertical_flip(bytes, w, h, bytes_per_pixel);
++      bytes += slice_size;
++   }
++}
++#endif
++
++static unsigned char *stbi__load_and_postprocess_8bit(stbi__context *s, int *x, int *y, int *comp, int req_comp)
++{
++   stbi__result_info ri;
++   void *result = stbi__load_main(s, x, y, comp, req_comp, &ri, 8);
++
++   if (result == NULL)
++      return NULL;
++
++   if (ri.bits_per_channel != 8) {
++      STBI_ASSERT(ri.bits_per_channel == 16);
++      result = stbi__convert_16_to_8((stbi__uint16 *) result, *x, *y, req_comp == 0 ? *comp : req_comp);
++      ri.bits_per_channel = 8;
++   }
++
++   // @TODO: move stbi__convert_format to here
++
++   if (stbi__vertically_flip_on_load) {
++      int channels = req_comp ? req_comp : *comp;
++      stbi__vertical_flip(result, *x, *y, channels * sizeof(stbi_uc));
++   }
++
++   return (unsigned char *) result;
++}
++
++static stbi__uint16 *stbi__load_and_postprocess_16bit(stbi__context *s, int *x, int *y, int *comp, int req_comp)
++{
++   stbi__result_info ri;
++   void *result = stbi__load_main(s, x, y, comp, req_comp, &ri, 16);
++
++   if (result == NULL)
++      return NULL;
++
++   if (ri.bits_per_channel != 16) {
++      STBI_ASSERT(ri.bits_per_channel == 8);
++      result = stbi__convert_8_to_16((stbi_uc *) result, *x, *y, req_comp == 0 ? *comp : req_comp);
++      ri.bits_per_channel = 16;
++   }
++
++   // @TODO: move stbi__convert_format16 to here
++   // @TODO: special case RGB-to-Y (and RGBA-to-YA) for 8-bit-to-16-bit case to keep more precision
++
++   if (stbi__vertically_flip_on_load) {
++      int channels = req_comp ? req_comp : *comp;
++      stbi__vertical_flip(result, *x, *y, channels * sizeof(stbi__uint16));
++   }
++
++   return (stbi__uint16 *) result;
++}
++
++#if !defined(STBI_NO_HDR) /* || !defined(STBI_NO_LINEAR) */
++static void stbi__float_postprocess(float *result, int *x, int *y, int *comp, int req_comp)
++{
++   if (stbi__vertically_flip_on_load && result != NULL) {
++      int channels = req_comp ? req_comp : *comp;
++      stbi__vertical_flip(result, *x, *y, channels * sizeof(float));
++   }
++}
++#endif
++
++#ifndef STBI_NO_STDIO
++
++static FILE *stbi__fopen(char const *filename, char const *mode)
++{
++   FILE *f;
++#if defined(_MSC_VER) && _MSC_VER >= 1400
++   if (0 != fopen_s(&f, filename, mode))
++      f=0;
++#else
++   f = fopen(filename, mode);
++#endif
++   return f;
++}
++
++
++STBIDEF stbi_uc *stbi_load(char const *filename, int *x, int *y, int *comp, int req_comp)
++{
++   FILE *f = stbi__fopen(filename, "rb");
++   unsigned char *result;
++   if (!f) return stbi__errpuc("can't fopen", "Unable to open file");
++   result = stbi_load_from_file(f,x,y,comp,req_comp);
++   fclose(f);
++   return result;
++}
++
++STBIDEF stbi_uc *stbi_load_from_file(FILE *f, int *x, int *y, int *comp, int req_comp)
++{
++   unsigned char *result;
++   stbi__context s;
++   stbi__start_file(&s,f);
++   result = stbi__load_and_postprocess_8bit(&s,x,y,comp,req_comp);
++   if (result) {
++      // need to 'unget' all the characters in the IO buffer
++      fseek(f, - (int) (s.img_buffer_end - s.img_buffer), SEEK_CUR);
++   }
++   return result;
++}
++
++STBIDEF stbi__uint16 *stbi_load_from_file_16(FILE *f, int *x, int *y, int *comp, int req_comp)
++{
++   stbi__uint16 *result;
++   stbi__context s;
++   stbi__start_file(&s,f);
++   result = stbi__load_and_postprocess_16bit(&s,x,y,comp,req_comp);
++   if (result) {
++      // need to 'unget' all the characters in the IO buffer
++      fseek(f, - (int) (s.img_buffer_end - s.img_buffer), SEEK_CUR);
++   }
++   return result;
++}
++
++STBIDEF stbi_us *stbi_load_16(char const *filename, int *x, int *y, int *comp, int req_comp)
++{
++   FILE *f = stbi__fopen(filename, "rb");
++   stbi__uint16 *result;
++   if (!f) return (stbi_us *) stbi__errpuc("can't fopen", "Unable to open file");
++   result = stbi_load_from_file_16(f,x,y,comp,req_comp);
++   fclose(f);
++   return result;
++}
++
++
++#endif //!STBI_NO_STDIO
++
++STBIDEF stbi_us *stbi_load_16_from_memory(stbi_uc const *buffer, int len, int *x, int *y, int *channels_in_file, int desired_channels)
++{
++   stbi__context s;
++   stbi__start_mem(&s,buffer,len);
++   return stbi__load_and_postprocess_16bit(&s,x,y,channels_in_file,desired_channels);
++}
++
++STBIDEF stbi_us *stbi_load_16_from_callbacks(stbi_io_callbacks const *clbk, void *user, int *x, int *y, int *channels_in_file, int desired_channels)
++{
++   stbi__context s;
++   stbi__start_callbacks(&s, (stbi_io_callbacks *)clbk, user);
++   return stbi__load_and_postprocess_16bit(&s,x,y,channels_in_file,desired_channels);
++}
++
++STBIDEF stbi_uc *stbi_load_from_memory(stbi_uc const *buffer, int len, int *x, int *y, int *comp, int req_comp)
++{
++   stbi__context s;
++   stbi__start_mem(&s,buffer,len);
++   return stbi__load_and_postprocess_8bit(&s,x,y,comp,req_comp);
++}
++
++STBIDEF stbi_uc *stbi_load_from_callbacks(stbi_io_callbacks const *clbk, void *user, int *x, int *y, int *comp, int req_comp)
++{
++   stbi__context s;
++   stbi__start_callbacks(&s, (stbi_io_callbacks *) clbk, user);
++   return stbi__load_and_postprocess_8bit(&s,x,y,comp,req_comp);
++}
++
++#ifndef STBI_NO_GIF
++STBIDEF stbi_uc *stbi_load_gif_from_memory(stbi_uc const *buffer, int len, int **delays, int *x, int *y, int *z, int *comp, int req_comp)
++{
++   unsigned char *result;
++   stbi__context s;
++   stbi__start_mem(&s,buffer,len);
++
++   result = (unsigned char*) stbi__load_gif_main(&s, delays, x, y, z, comp, req_comp);
++   if (stbi__vertically_flip_on_load) {
++      stbi__vertical_flip_slices( result, *x, *y, *z, *comp );
++   }
++
++   return result;
++}
++#endif
++
++#ifndef STBI_NO_LINEAR
++static float *stbi__loadf_main(stbi__context *s, int *x, int *y, int *comp, int req_comp)
++{
++   unsigned char *data;
++   #ifndef STBI_NO_HDR
++   if (stbi__hdr_test(s)) {
++      stbi__result_info ri;
++      float *hdr_data = stbi__hdr_load(s,x,y,comp,req_comp, &ri);
++      if (hdr_data)
++         stbi__float_postprocess(hdr_data,x,y,comp,req_comp);
++      return hdr_data;
++   }
++   #endif
++   data = stbi__load_and_postprocess_8bit(s, x, y, comp, req_comp);
++   if (data)
++      return stbi__ldr_to_hdr(data, *x, *y, req_comp ? req_comp : *comp);
++   return stbi__errpf("unknown image type", "Image not of any known type, or corrupt");
++}
++
++STBIDEF float *stbi_loadf_from_memory(stbi_uc const *buffer, int len, int *x, int *y, int *comp, int req_comp)
++{
++   stbi__context s;
++   stbi__start_mem(&s,buffer,len);
++   return stbi__loadf_main(&s,x,y,comp,req_comp);
++}
++
++STBIDEF float *stbi_loadf_from_callbacks(stbi_io_callbacks const *clbk, void *user, int *x, int *y, int *comp, int req_comp)
++{
++   stbi__context s;
++   stbi__start_callbacks(&s, (stbi_io_callbacks *) clbk, user);
++   return stbi__loadf_main(&s,x,y,comp,req_comp);
++}
++
++#ifndef STBI_NO_STDIO
++STBIDEF float *stbi_loadf(char const *filename, int *x, int *y, int *comp, int req_comp)
++{
++   float *result;
++   FILE *f = stbi__fopen(filename, "rb");
++   if (!f) return stbi__errpf("can't fopen", "Unable to open file");
++   result = stbi_loadf_from_file(f,x,y,comp,req_comp);
++   fclose(f);
++   return result;
++}
++
++STBIDEF float *stbi_loadf_from_file(FILE *f, int *x, int *y, int *comp, int req_comp)
++{
++   stbi__context s;
++   stbi__start_file(&s,f);
++   return stbi__loadf_main(&s,x,y,comp,req_comp);
++}
++#endif // !STBI_NO_STDIO
++
++#endif // !STBI_NO_LINEAR
++
++// these is-hdr-or-not is defined independent of whether STBI_NO_LINEAR is
++// defined, for API simplicity; if STBI_NO_LINEAR is defined, it always
++// reports false!
++
++STBIDEF int stbi_is_hdr_from_memory(stbi_uc const *buffer, int len)
++{
++   #ifndef STBI_NO_HDR
++   stbi__context s;
++   stbi__start_mem(&s,buffer,len);
++   return stbi__hdr_test(&s);
++   #else
++   STBI_NOTUSED(buffer);
++   STBI_NOTUSED(len);
++   return 0;
++   #endif
++}
++
++#ifndef STBI_NO_STDIO
++STBIDEF int      stbi_is_hdr          (char const *filename)
++{
++   FILE *f = stbi__fopen(filename, "rb");
++   int result=0;
++   if (f) {
++      result = stbi_is_hdr_from_file(f);
++      fclose(f);
++   }
++   return result;
++}
++
++STBIDEF int stbi_is_hdr_from_file(FILE *f)
++{
++   #ifndef STBI_NO_HDR
++   long pos = ftell(f);
++   int res;
++   stbi__context s;
++   stbi__start_file(&s,f);
++   res = stbi__hdr_test(&s);
++   fseek(f, pos, SEEK_SET);
++   return res;
++   #else
++   STBI_NOTUSED(f);
++   return 0;
++   #endif
++}
++#endif // !STBI_NO_STDIO
++
++STBIDEF int      stbi_is_hdr_from_callbacks(stbi_io_callbacks const *clbk, void *user)
++{
++   #ifndef STBI_NO_HDR
++   stbi__context s;
++   stbi__start_callbacks(&s, (stbi_io_callbacks *) clbk, user);
++   return stbi__hdr_test(&s);
++   #else
++   STBI_NOTUSED(clbk);
++   STBI_NOTUSED(user);
++   return 0;
++   #endif
++}
++
++#ifndef STBI_NO_LINEAR
++static float stbi__l2h_gamma=2.2f, stbi__l2h_scale=1.0f;
++
++STBIDEF void   stbi_ldr_to_hdr_gamma(float gamma) { stbi__l2h_gamma = gamma; }
++STBIDEF void   stbi_ldr_to_hdr_scale(float scale) { stbi__l2h_scale = scale; }
++#endif
++
++static float stbi__h2l_gamma_i=1.0f/2.2f, stbi__h2l_scale_i=1.0f;
++
++STBIDEF void   stbi_hdr_to_ldr_gamma(float gamma) { stbi__h2l_gamma_i = 1/gamma; }
++STBIDEF void   stbi_hdr_to_ldr_scale(float scale) { stbi__h2l_scale_i = 1/scale; }
++
++
++//////////////////////////////////////////////////////////////////////////////
++//
++// Common code used by all image loaders
++//
++
++enum
++{
++   STBI__SCAN_load=0,
++   STBI__SCAN_type,
++   STBI__SCAN_header
++};
++
++static void stbi__refill_buffer(stbi__context *s)
++{
++   int n = (s->io.read)(s->io_user_data,(char*)s->buffer_start,s->buflen);
++   if (n == 0) {
++      // at end of file, treat same as if from memory, but need to handle case
++      // where s->img_buffer isn't pointing to safe memory, e.g. 0-byte file
++      s->read_from_callbacks = 0;
++      s->img_buffer = s->buffer_start;
++      s->img_buffer_end = s->buffer_start+1;
++      *s->img_buffer = 0;
++   } else {
++      s->img_buffer = s->buffer_start;
++      s->img_buffer_end = s->buffer_start + n;
++   }
++}
++
++stbi_inline static stbi_uc stbi__get8(stbi__context *s)
++{
++   if (s->img_buffer < s->img_buffer_end)
++      return *s->img_buffer++;
++   if (s->read_from_callbacks) {
++      stbi__refill_buffer(s);
++      return *s->img_buffer++;
++   }
++   return 0;
++}
++
++stbi_inline static int stbi__at_eof(stbi__context *s)
++{
++   if (s->io.read) {
++      if (!(s->io.eof)(s->io_user_data)) return 0;
++      // if feof() is true, check if buffer = end
++      // special case: we've only got the special 0 character at the end
++      if (s->read_from_callbacks == 0) return 1;
++   }
++
++   return s->img_buffer >= s->img_buffer_end;
++}
++
++static void stbi__skip(stbi__context *s, int n)
++{
++   if (n < 0) {
++      s->img_buffer = s->img_buffer_end;
++      return;
++   }
++   if (s->io.read) {
++      int blen = (int) (s->img_buffer_end - s->img_buffer);
++      if (blen < n) {
++         s->img_buffer = s->img_buffer_end;
++         (s->io.skip)(s->io_user_data, n - blen);
++         return;
++      }
++   }
++   s->img_buffer += n;
++}
++
++static int stbi__getn(stbi__context *s, stbi_uc *buffer, int n)
++{
++   if (s->io.read) {
++      int blen = (int) (s->img_buffer_end - s->img_buffer);
++      if (blen < n) {
++         int res, count;
++
++         memcpy(buffer, s->img_buffer, blen);
++
++         count = (s->io.read)(s->io_user_data, (char*) buffer + blen, n - blen);
++         res = (count == (n-blen));
++         s->img_buffer = s->img_buffer_end;
++         return res;
++      }
++   }
++
++   if (s->img_buffer+n <= s->img_buffer_end) {
++      memcpy(buffer, s->img_buffer, n);
++      s->img_buffer += n;
++      return 1;
++   } else
++      return 0;
++}
++
++static int stbi__get16be(stbi__context *s)
++{
++   int z = stbi__get8(s);
++   return (z << 8) + stbi__get8(s);
++}
++
++static stbi__uint32 stbi__get32be(stbi__context *s)
++{
++   stbi__uint32 z = stbi__get16be(s);
++   return (z << 16) + stbi__get16be(s);
++}
++
++#if defined(STBI_NO_BMP) && defined(STBI_NO_TGA) && defined(STBI_NO_GIF)
++// nothing
++#else
++static int stbi__get16le(stbi__context *s)
++{
++   int z = stbi__get8(s);
++   return z + (stbi__get8(s) << 8);
++}
++#endif
++
++#ifndef STBI_NO_BMP
++static stbi__uint32 stbi__get32le(stbi__context *s)
++{
++   stbi__uint32 z = stbi__get16le(s);
++   return z + (stbi__get16le(s) << 16);
++}
++#endif
++
++#define STBI__BYTECAST(x)  ((stbi_uc) ((x) & 255))  // truncate int to byte without warnings
++
++
++//////////////////////////////////////////////////////////////////////////////
++//
++//  generic converter from built-in img_n to req_comp
++//    individual types do this automatically as much as possible (e.g. jpeg
++//    does all cases internally since it needs to colorspace convert anyway,
++//    and it never has alpha, so very few cases ). png can automatically
++//    interleave an alpha=255 channel, but falls back to this for other cases
++//
++//  assume data buffer is malloced, so malloc a new one and free that one
++//  only failure mode is malloc failing
++
++static stbi_uc stbi__compute_y(int r, int g, int b)
++{
++   return (stbi_uc) (((r*77) + (g*150) +  (29*b)) >> 8);
++}
++
++static unsigned char *stbi__convert_format(unsigned char *data, int img_n, int req_comp, unsigned int x, unsigned int y)
++{
++   int i,j;
++   unsigned char *good;
++
++   if (req_comp == img_n) return data;
++   STBI_ASSERT(req_comp >= 1 && req_comp <= 4);
++
++   good = (unsigned char *) stbi__malloc_mad3(req_comp, x, y, 0);
++   if (good == NULL) {
++      STBI_FREE(data);
++      return stbi__errpuc("outofmem", "Out of memory");
++   }
++
++   for (j=0; j < (int) y; ++j) {
++      unsigned char *src  = data + j * x * img_n   ;
++      unsigned char *dest = good + j * x * req_comp;
++
++      #define STBI__COMBO(a,b)  ((a)*8+(b))
++      #define STBI__CASE(a,b)   case STBI__COMBO(a,b): for(i=x-1; i >= 0; --i, src += a, dest += b)
++      // convert source image with img_n components to one with req_comp components;
++      // avoid switch per pixel, so use switch per scanline and massive macros
++      switch (STBI__COMBO(img_n, req_comp)) {
++         STBI__CASE(1,2) { dest[0]=src[0], dest[1]=255;                                     } break;
++         STBI__CASE(1,3) { dest[0]=dest[1]=dest[2]=src[0];                                  } break;
++         STBI__CASE(1,4) { dest[0]=dest[1]=dest[2]=src[0], dest[3]=255;                     } break;
++         STBI__CASE(2,1) { dest[0]=src[0];                                                  } break;
++         STBI__CASE(2,3) { dest[0]=dest[1]=dest[2]=src[0];                                  } break;
++         STBI__CASE(2,4) { dest[0]=dest[1]=dest[2]=src[0], dest[3]=src[1];                  } break;
++         STBI__CASE(3,4) { dest[0]=src[0],dest[1]=src[1],dest[2]=src[2],dest[3]=255;        } break;
++         STBI__CASE(3,1) { dest[0]=stbi__compute_y(src[0],src[1],src[2]);                   } break;
++         STBI__CASE(3,2) { dest[0]=stbi__compute_y(src[0],src[1],src[2]), dest[1] = 255;    } break;
++         STBI__CASE(4,1) { dest[0]=stbi__compute_y(src[0],src[1],src[2]);                   } break;
++         STBI__CASE(4,2) { dest[0]=stbi__compute_y(src[0],src[1],src[2]), dest[1] = src[3]; } break;
++         STBI__CASE(4,3) { dest[0]=src[0],dest[1]=src[1],dest[2]=src[2];                    } break;
++         default: STBI_ASSERT(0);
++      }
++      #undef STBI__CASE
++   }
++
++   STBI_FREE(data);
++   return good;
++}
++
++static stbi__uint16 stbi__compute_y_16(int r, int g, int b)
++{
++   return (stbi__uint16) (((r*77) + (g*150) +  (29*b)) >> 8);
++}
++
++static stbi__uint16 *stbi__convert_format16(stbi__uint16 *data, int img_n, int req_comp, unsigned int x, unsigned int y)
++{
++   int i,j;
++   stbi__uint16 *good;
++
++   if (req_comp == img_n) return data;
++   STBI_ASSERT(req_comp >= 1 && req_comp <= 4);
++
++   good = (stbi__uint16 *) stbi__malloc(req_comp * x * y * 2);
++   if (good == NULL) {
++      STBI_FREE(data);
++      return (stbi__uint16 *) stbi__errpuc("outofmem", "Out of memory");
++   }
++
++   for (j=0; j < (int) y; ++j) {
++      stbi__uint16 *src  = data + j * x * img_n   ;
++      stbi__uint16 *dest = good + j * x * req_comp;
++
++      #define STBI__COMBO(a,b)  ((a)*8+(b))
++      #define STBI__CASE(a,b)   case STBI__COMBO(a,b): for(i=x-1; i >= 0; --i, src += a, dest += b)
++      // convert source image with img_n components to one with req_comp components;
++      // avoid switch per pixel, so use switch per scanline and massive macros
++      switch (STBI__COMBO(img_n, req_comp)) {
++         STBI__CASE(1,2) { dest[0]=src[0], dest[1]=0xffff;                                     } break;
++         STBI__CASE(1,3) { dest[0]=dest[1]=dest[2]=src[0];                                     } break;
++         STBI__CASE(1,4) { dest[0]=dest[1]=dest[2]=src[0], dest[3]=0xffff;                     } break;
++         STBI__CASE(2,1) { dest[0]=src[0];                                                     } break;
++         STBI__CASE(2,3) { dest[0]=dest[1]=dest[2]=src[0];                                     } break;
++         STBI__CASE(2,4) { dest[0]=dest[1]=dest[2]=src[0], dest[3]=src[1];                     } break;
++         STBI__CASE(3,4) { dest[0]=src[0],dest[1]=src[1],dest[2]=src[2],dest[3]=0xffff;        } break;
++         STBI__CASE(3,1) { dest[0]=stbi__compute_y_16(src[0],src[1],src[2]);                   } break;
++         STBI__CASE(3,2) { dest[0]=stbi__compute_y_16(src[0],src[1],src[2]), dest[1] = 0xffff; } break;
++         STBI__CASE(4,1) { dest[0]=stbi__compute_y_16(src[0],src[1],src[2]);                   } break;
++         STBI__CASE(4,2) { dest[0]=stbi__compute_y_16(src[0],src[1],src[2]), dest[1] = src[3]; } break;
++         STBI__CASE(4,3) { dest[0]=src[0],dest[1]=src[1],dest[2]=src[2];                       } break;
++         default: STBI_ASSERT(0);
++      }
++      #undef STBI__CASE
++   }
++
++   STBI_FREE(data);
++   return good;
++}
++
++#ifndef STBI_NO_LINEAR
++static float   *stbi__ldr_to_hdr(stbi_uc *data, int x, int y, int comp)
++{
++   int i,k,n;
++   float *output;
++   if (!data) return NULL;
++   output = (float *) stbi__malloc_mad4(x, y, comp, sizeof(float), 0);
++   if (output == NULL) { STBI_FREE(data); return stbi__errpf("outofmem", "Out of memory"); }
++   // compute number of non-alpha components
++   if (comp & 1) n = comp; else n = comp-1;
++   for (i=0; i < x*y; ++i) {
++      for (k=0; k < n; ++k) {
++         output[i*comp + k] = (float) (pow(data[i*comp+k]/255.0f, stbi__l2h_gamma) * stbi__l2h_scale);
++      }
++      if (k < comp) output[i*comp + k] = data[i*comp+k]/255.0f;
++   }
++   STBI_FREE(data);
++   return output;
++}
++#endif
++
++#ifndef STBI_NO_HDR
++#define stbi__float2int(x)   ((int) (x))
++static stbi_uc *stbi__hdr_to_ldr(float   *data, int x, int y, int comp)
++{
++   int i,k,n;
++   stbi_uc *output;
++   if (!data) return NULL;
++   output = (stbi_uc *) stbi__malloc_mad3(x, y, comp, 0);
++   if (output == NULL) { STBI_FREE(data); return stbi__errpuc("outofmem", "Out of memory"); }
++   // compute number of non-alpha components
++   if (comp & 1) n = comp; else n = comp-1;
++   for (i=0; i < x*y; ++i) {
++      for (k=0; k < n; ++k) {
++         float z = (float) pow(data[i*comp+k]*stbi__h2l_scale_i, stbi__h2l_gamma_i) * 255 + 0.5f;
++         if (z < 0) z = 0;
++         if (z > 255) z = 255;
++         output[i*comp + k] = (stbi_uc) stbi__float2int(z);
++      }
++      if (k < comp) {
++         float z = data[i*comp+k] * 255 + 0.5f;
++         if (z < 0) z = 0;
++         if (z > 255) z = 255;
++         output[i*comp + k] = (stbi_uc) stbi__float2int(z);
++      }
++   }
++   STBI_FREE(data);
++   return output;
++}
++#endif
++
++//////////////////////////////////////////////////////////////////////////////
++//
++//  "baseline" JPEG/JFIF decoder
++//
++//    simple implementation
++//      - doesn't support delayed output of y-dimension
++//      - simple interface (only one output format: 8-bit interleaved RGB)
++//      - doesn't try to recover corrupt jpegs
++//      - doesn't allow partial loading, loading multiple at once
++//      - still fast on x86 (copying globals into locals doesn't help x86)
++//      - allocates lots of intermediate memory (full size of all components)
++//        - non-interleaved case requires this anyway
++//        - allows good upsampling (see next)
++//    high-quality
++//      - upsampled channels are bilinearly interpolated, even across blocks
++//      - quality integer IDCT derived from IJG's 'slow'
++//    performance
++//      - fast huffman; reasonable integer IDCT
++//      - some SIMD kernels for common paths on targets with SSE2/NEON
++//      - uses a lot of intermediate memory, could cache poorly
++
++#ifndef STBI_NO_JPEG
++
++// huffman decoding acceleration
++#define FAST_BITS   9  // larger handles more cases; smaller stomps less cache
++
++typedef struct
++{
++   stbi_uc  fast[1 << FAST_BITS];
++   // weirdly, repacking this into AoS is a 10% speed loss, instead of a win
++   stbi__uint16 code[256];
++   stbi_uc  values[256];
++   stbi_uc  size[257];
++   unsigned int maxcode[18];
++   int    delta[17];   // old 'firstsymbol' - old 'firstcode'
++} stbi__huffman;
++
++typedef struct
++{
++   stbi__context *s;
++   stbi__huffman huff_dc[4];
++   stbi__huffman huff_ac[4];
++   stbi__uint16 dequant[4][64];
++   stbi__int16 fast_ac[4][1 << FAST_BITS];
++
++// sizes for components, interleaved MCUs
++   int img_h_max, img_v_max;
++   int img_mcu_x, img_mcu_y;
++   int img_mcu_w, img_mcu_h;
++
++// definition of jpeg image component
++   struct
++   {
++      int id;
++      int h,v;
++      int tq;
++      int hd,ha;
++      int dc_pred;
++
++      int x,y,w2,h2;
++      stbi_uc *data;
++      void *raw_data, *raw_coeff;
++      stbi_uc *linebuf;
++      short   *coeff;   // progressive only
++      int      coeff_w, coeff_h; // number of 8x8 coefficient blocks
++   } img_comp[4];
++
++   stbi__uint32   code_buffer; // jpeg entropy-coded buffer
++   int            code_bits;   // number of valid bits
++   unsigned char  marker;      // marker seen while filling entropy buffer
++   int            nomore;      // flag if we saw a marker so must stop
++
++   int            progressive;
++   int            spec_start;
++   int            spec_end;
++   int            succ_high;
++   int            succ_low;
++   int            eob_run;
++   int            jfif;
++   int            app14_color_transform; // Adobe APP14 tag
++   int            rgb;
++
++   int scan_n, order[4];
++   int restart_interval, todo;
++
++// kernels
++   void (*idct_block_kernel)(stbi_uc *out, int out_stride, short data[64]);
++   void (*YCbCr_to_RGB_kernel)(stbi_uc *out, const stbi_uc *y, const stbi_uc *pcb, const stbi_uc *pcr, int count, int step);
++   stbi_uc *(*resample_row_hv_2_kernel)(stbi_uc *out, stbi_uc *in_near, stbi_uc *in_far, int w, int hs);
++} stbi__jpeg;
++
++static int stbi__build_huffman(stbi__huffman *h, int *count)
++{
++   int i,j,k=0;
++   unsigned int code;
++   // build size list for each symbol (from JPEG spec)
++   for (i=0; i < 16; ++i)
++      for (j=0; j < count[i]; ++j)
++         h->size[k++] = (stbi_uc) (i+1);
++   h->size[k] = 0;
++
++   // compute actual symbols (from jpeg spec)
++   code = 0;
++   k = 0;
++   for(j=1; j <= 16; ++j) {
++      // compute delta to add to code to compute symbol id
++      h->delta[j] = k - code;
++      if (h->size[k] == j) {
++         while (h->size[k] == j)
++            h->code[k++] = (stbi__uint16) (code++);
++         if (code-1 >= (1u << j)) return stbi__err("bad code lengths","Corrupt JPEG");
++      }
++      // compute largest code + 1 for this size, preshifted as needed later
++      h->maxcode[j] = code << (16-j);
++      code <<= 1;
++   }
++   h->maxcode[j] = 0xffffffff;
++
++   // build non-spec acceleration table; 255 is flag for not-accelerated
++   memset(h->fast, 255, 1 << FAST_BITS);
++   for (i=0; i < k; ++i) {
++      int s = h->size[i];
++      if (s <= FAST_BITS) {
++         int c = h->code[i] << (FAST_BITS-s);
++         int m = 1 << (FAST_BITS-s);
++         for (j=0; j < m; ++j) {
++            h->fast[c+j] = (stbi_uc) i;
++         }
++      }
++   }
++   return 1;
++}
++
++// build a table that decodes both magnitude and value of small ACs in
++// one go.
++static void stbi__build_fast_ac(stbi__int16 *fast_ac, stbi__huffman *h)
++{
++   int i;
++   for (i=0; i < (1 << FAST_BITS); ++i) {
++      stbi_uc fast = h->fast[i];
++      fast_ac[i] = 0;
++      if (fast < 255) {
++         int rs = h->values[fast];
++         int run = (rs >> 4) & 15;
++         int magbits = rs & 15;
++         int len = h->size[fast];
++
++         if (magbits && len + magbits <= FAST_BITS) {
++            // magnitude code followed by receive_extend code
++            int k = ((i << len) & ((1 << FAST_BITS) - 1)) >> (FAST_BITS - magbits);
++            int m = 1 << (magbits - 1);
++            if (k < m) k += (~0U << magbits) + 1;
++            // if the result is small enough, we can fit it in fast_ac table
++            if (k >= -128 && k <= 127)
++               fast_ac[i] = (stbi__int16) ((k * 256) + (run * 16) + (len + magbits));
++         }
++      }
++   }
++}
++
++static void stbi__grow_buffer_unsafe(stbi__jpeg *j)
++{
++   do {
++      unsigned int b = j->nomore ? 0 : stbi__get8(j->s);
++      if (b == 0xff) {
++         int c = stbi__get8(j->s);
++         while (c == 0xff) c = stbi__get8(j->s); // consume fill bytes
++         if (c != 0) {
++            j->marker = (unsigned char) c;
++            j->nomore = 1;
++            return;
++         }
++      }
++      j->code_buffer |= b << (24 - j->code_bits);
++      j->code_bits += 8;
++   } while (j->code_bits <= 24);
++}
++
++// (1 << n) - 1
++static const stbi__uint32 stbi__bmask[17]={0,1,3,7,15,31,63,127,255,511,1023,2047,4095,8191,16383,32767,65535};
++
++// decode a jpeg huffman value from the bitstream
++stbi_inline static int stbi__jpeg_huff_decode(stbi__jpeg *j, stbi__huffman *h)
++{
++   unsigned int temp;
++   int c,k;
++
++   if (j->code_bits < 16) stbi__grow_buffer_unsafe(j);
++
++   // look at the top FAST_BITS and determine what symbol ID it is,
++   // if the code is <= FAST_BITS
++   c = (j->code_buffer >> (32 - FAST_BITS)) & ((1 << FAST_BITS)-1);
++   k = h->fast[c];
++   if (k < 255) {
++      int s = h->size[k];
++      if (s > j->code_bits)
++         return -1;
++      j->code_buffer <<= s;
++      j->code_bits -= s;
++      return h->values[k];
++   }
++
++   // naive test is to shift the code_buffer down so k bits are
++   // valid, then test against maxcode. To speed this up, we've
++   // preshifted maxcode left so that it has (16-k) 0s at the
++   // end; in other words, regardless of the number of bits, it
++   // wants to be compared against something shifted to have 16;
++   // that way we don't need to shift inside the loop.
++   temp = j->code_buffer >> 16;
++   for (k=FAST_BITS+1 ; ; ++k)
++      if (temp < h->maxcode[k])
++         break;
++   if (k == 17) {
++      // error! code not found
++      j->code_bits -= 16;
++      return -1;
++   }
++
++   if (k > j->code_bits)
++      return -1;
++
++   // convert the huffman code to the symbol id
++   c = ((j->code_buffer >> (32 - k)) & stbi__bmask[k]) + h->delta[k];
++   STBI_ASSERT((((j->code_buffer) >> (32 - h->size[c])) & stbi__bmask[h->size[c]]) == h->code[c]);
++
++   // convert the id to a symbol
++   j->code_bits -= k;
++   j->code_buffer <<= k;
++   return h->values[c];
++}
++
++// bias[n] = (-1<<n) + 1
++static const int stbi__jbias[16] = {0,-1,-3,-7,-15,-31,-63,-127,-255,-511,-1023,-2047,-4095,-8191,-16383,-32767};
++
++// combined JPEG 'receive' and JPEG 'extend', since baseline
++// always extends everything it receives.
++stbi_inline static int stbi__extend_receive(stbi__jpeg *j, int n)
++{
++   unsigned int k;
++   int sgn;
++   if (j->code_bits < n) stbi__grow_buffer_unsafe(j);
++
++   sgn = (stbi__int32)j->code_buffer >> 31; // sign bit is always in MSB
++   k = stbi_lrot(j->code_buffer, n);
++   STBI_ASSERT(n >= 0 && n < (int) (sizeof(stbi__bmask)/sizeof(*stbi__bmask)));
++   j->code_buffer = k & ~stbi__bmask[n];
++   k &= stbi__bmask[n];
++   j->code_bits -= n;
++   return k + (stbi__jbias[n] & ~sgn);
++}
++
++// get some unsigned bits
++stbi_inline static int stbi__jpeg_get_bits(stbi__jpeg *j, int n)
++{
++   unsigned int k;
++   if (j->code_bits < n) stbi__grow_buffer_unsafe(j);
++   k = stbi_lrot(j->code_buffer, n);
++   j->code_buffer = k & ~stbi__bmask[n];
++   k &= stbi__bmask[n];
++   j->code_bits -= n;
++   return k;
++}
++
++stbi_inline static int stbi__jpeg_get_bit(stbi__jpeg *j)
++{
++   unsigned int k;
++   if (j->code_bits < 1) stbi__grow_buffer_unsafe(j);
++   k = j->code_buffer;
++   j->code_buffer <<= 1;
++   --j->code_bits;
++   return k & 0x80000000;
++}
++
++// given a value that's at position X in the zigzag stream,
++// where does it appear in the 8x8 matrix coded as row-major?
++static const stbi_uc stbi__jpeg_dezigzag[64+15] =
++{
++    0,  1,  8, 16,  9,  2,  3, 10,
++   17, 24, 32, 25, 18, 11,  4,  5,
++   12, 19, 26, 33, 40, 48, 41, 34,
++   27, 20, 13,  6,  7, 14, 21, 28,
++   35, 42, 49, 56, 57, 50, 43, 36,
++   29, 22, 15, 23, 30, 37, 44, 51,
++   58, 59, 52, 45, 38, 31, 39, 46,
++   53, 60, 61, 54, 47, 55, 62, 63,
++   // let corrupt input sample past end
++   63, 63, 63, 63, 63, 63, 63, 63,
++   63, 63, 63, 63, 63, 63, 63
++};
++
++// decode one 64-entry block--
++static int stbi__jpeg_decode_block(stbi__jpeg *j, short data[64], stbi__huffman *hdc, stbi__huffman *hac, stbi__int16 *fac, int b, stbi__uint16 *dequant)
++{
++   int diff,dc,k;
++   int t;
++
++   if (j->code_bits < 16) stbi__grow_buffer_unsafe(j);
++   t = stbi__jpeg_huff_decode(j, hdc);
++   if (t < 0) return stbi__err("bad huffman code","Corrupt JPEG");
++
++   // 0 all the ac values now so we can do it 32-bits at a time
++   memset(data,0,64*sizeof(data[0]));
++
++   diff = t ? stbi__extend_receive(j, t) : 0;
++   dc = j->img_comp[b].dc_pred + diff;
++   j->img_comp[b].dc_pred = dc;
++   data[0] = (short) (dc * dequant[0]);
++
++   // decode AC components, see JPEG spec
++   k = 1;
++   do {
++      unsigned int zig;
++      int c,r,s;
++      if (j->code_bits < 16) stbi__grow_buffer_unsafe(j);
++      c = (j->code_buffer >> (32 - FAST_BITS)) & ((1 << FAST_BITS)-1);
++      r = fac[c];
++      if (r) { // fast-AC path
++         k += (r >> 4) & 15; // run
++         s = r & 15; // combined length
++         j->code_buffer <<= s;
++         j->code_bits -= s;
++         // decode into unzigzag'd location
++         zig = stbi__jpeg_dezigzag[k++];
++         data[zig] = (short) ((r >> 8) * dequant[zig]);
++      } else {
++         int rs = stbi__jpeg_huff_decode(j, hac);
++         if (rs < 0) return stbi__err("bad huffman code","Corrupt JPEG");
++         s = rs & 15;
++         r = rs >> 4;
++         if (s == 0) {
++            if (rs != 0xf0) break; // end block
++            k += 16;
++         } else {
++            k += r;
++            // decode into unzigzag'd location
++            zig = stbi__jpeg_dezigzag[k++];
++            data[zig] = (short) (stbi__extend_receive(j,s) * dequant[zig]);
++         }
++      }
++   } while (k < 64);
++   return 1;
++}
++
++static int stbi__jpeg_decode_block_prog_dc(stbi__jpeg *j, short data[64], stbi__huffman *hdc, int b)
++{
++   int diff,dc;
++   int t;
++   if (j->spec_end != 0) return stbi__err("can't merge dc and ac", "Corrupt JPEG");
++
++   if (j->code_bits < 16) stbi__grow_buffer_unsafe(j);
++
++   if (j->succ_high == 0) {
++      // first scan for DC coefficient, must be first
++      memset(data,0,64*sizeof(data[0])); // 0 all the ac values now
++      t = stbi__jpeg_huff_decode(j, hdc);
++      diff = t ? stbi__extend_receive(j, t) : 0;
++
++      dc = j->img_comp[b].dc_pred + diff;
++      j->img_comp[b].dc_pred = dc;
++      data[0] = (short) (dc << j->succ_low);
++   } else {
++      // refinement scan for DC coefficient
++      if (stbi__jpeg_get_bit(j))
++         data[0] += (short) (1 << j->succ_low);
++   }
++   return 1;
++}
++
++// @OPTIMIZE: store non-zigzagged during the decode passes,
++// and only de-zigzag when dequantizing
++static int stbi__jpeg_decode_block_prog_ac(stbi__jpeg *j, short data[64], stbi__huffman *hac, stbi__int16 *fac)
++{
++   int k;
++   if (j->spec_start == 0) return stbi__err("can't merge dc and ac", "Corrupt JPEG");
++
++   if (j->succ_high == 0) {
++      int shift = j->succ_low;
++
++      if (j->eob_run) {
++         --j->eob_run;
++         return 1;
++      }
++
++      k = j->spec_start;
++      do {
++         unsigned int zig;
++         int c,r,s;
++         if (j->code_bits < 16) stbi__grow_buffer_unsafe(j);
++         c = (j->code_buffer >> (32 - FAST_BITS)) & ((1 << FAST_BITS)-1);
++         r = fac[c];
++         if (r) { // fast-AC path
++            k += (r >> 4) & 15; // run
++            s = r & 15; // combined length
++            j->code_buffer <<= s;
++            j->code_bits -= s;
++            zig = stbi__jpeg_dezigzag[k++];
++            data[zig] = (short) ((r >> 8) << shift);
++         } else {
++            int rs = stbi__jpeg_huff_decode(j, hac);
++            if (rs < 0) return stbi__err("bad huffman code","Corrupt JPEG");
++            s = rs & 15;
++            r = rs >> 4;
++            if (s == 0) {
++               if (r < 15) {
++                  j->eob_run = (1 << r);
++                  if (r)
++                     j->eob_run += stbi__jpeg_get_bits(j, r);
++                  --j->eob_run;
++                  break;
++               }
++               k += 16;
++            } else {
++               k += r;
++               zig = stbi__jpeg_dezigzag[k++];
++               data[zig] = (short) (stbi__extend_receive(j,s) << shift);
++            }
++         }
++      } while (k <= j->spec_end);
++   } else {
++      // refinement scan for these AC coefficients
++
++      short bit = (short) (1 << j->succ_low);
++
++      if (j->eob_run) {
++         --j->eob_run;
++         for (k = j->spec_start; k <= j->spec_end; ++k) {
++            short *p = &data[stbi__jpeg_dezigzag[k]];
++            if (*p != 0)
++               if (stbi__jpeg_get_bit(j))
++                  if ((*p & bit)==0) {
++                     if (*p > 0)
++                        *p += bit;
++                     else
++                        *p -= bit;
++                  }
++         }
++      } else {
++         k = j->spec_start;
++         do {
++            int r,s;
++            int rs = stbi__jpeg_huff_decode(j, hac); // @OPTIMIZE see if we can use the fast path here, advance-by-r is so slow, eh
++            if (rs < 0) return stbi__err("bad huffman code","Corrupt JPEG");
++            s = rs & 15;
++            r = rs >> 4;
++            if (s == 0) {
++               if (r < 15) {
++                  j->eob_run = (1 << r) - 1;
++                  if (r)
++                     j->eob_run += stbi__jpeg_get_bits(j, r);
++                  r = 64; // force end of block
++               } else {
++                  // r=15 s=0 should write 16 0s, so we just do
++                  // a run of 15 0s and then write s (which is 0),
++                  // so we don't have to do anything special here
++               }
++            } else {
++               if (s != 1) return stbi__err("bad huffman code", "Corrupt JPEG");
++               // sign bit
++               if (stbi__jpeg_get_bit(j))
++                  s = bit;
++               else
++                  s = -bit;
++            }
++
++            // advance by r
++            while (k <= j->spec_end) {
++               short *p = &data[stbi__jpeg_dezigzag[k++]];
++               if (*p != 0) {
++                  if (stbi__jpeg_get_bit(j))
++                     if ((*p & bit)==0) {
++                        if (*p > 0)
++                           *p += bit;
++                        else
++                           *p -= bit;
++                     }
++               } else {
++                  if (r == 0) {
++                     *p = (short) s;
++                     break;
++                  }
++                  --r;
++               }
++            }
++         } while (k <= j->spec_end);
++      }
++   }
++   return 1;
++}
++
++// take a -128..127 value and stbi__clamp it and convert to 0..255
++stbi_inline static stbi_uc stbi__clamp(int x)
++{
++   // trick to use a single test to catch both cases
++   if ((unsigned int) x > 255) {
++      if (x < 0) return 0;
++      if (x > 255) return 255;
++   }
++   return (stbi_uc) x;
++}
++
++#define stbi__f2f(x)  ((int) (((x) * 4096 + 0.5)))
++#define stbi__fsh(x)  ((x) * 4096)
++
++// derived from jidctint -- DCT_ISLOW
++#define STBI__IDCT_1D(s0,s1,s2,s3,s4,s5,s6,s7) \
++   int t0,t1,t2,t3,p1,p2,p3,p4,p5,x0,x1,x2,x3; \
++   p2 = s2;                                    \
++   p3 = s6;                                    \
++   p1 = (p2+p3) * stbi__f2f(0.5411961f);       \
++   t2 = p1 + p3*stbi__f2f(-1.847759065f);      \
++   t3 = p1 + p2*stbi__f2f( 0.765366865f);      \
++   p2 = s0;                                    \
++   p3 = s4;                                    \
++   t0 = stbi__fsh(p2+p3);                      \
++   t1 = stbi__fsh(p2-p3);                      \
++   x0 = t0+t3;                                 \
++   x3 = t0-t3;                                 \
++   x1 = t1+t2;                                 \
++   x2 = t1-t2;                                 \
++   t0 = s7;                                    \
++   t1 = s5;                                    \
++   t2 = s3;                                    \
++   t3 = s1;                                    \
++   p3 = t0+t2;                                 \
++   p4 = t1+t3;                                 \
++   p1 = t0+t3;                                 \
++   p2 = t1+t2;                                 \
++   p5 = (p3+p4)*stbi__f2f( 1.175875602f);      \
++   t0 = t0*stbi__f2f( 0.298631336f);           \
++   t1 = t1*stbi__f2f( 2.053119869f);           \
++   t2 = t2*stbi__f2f( 3.072711026f);           \
++   t3 = t3*stbi__f2f( 1.501321110f);           \
++   p1 = p5 + p1*stbi__f2f(-0.899976223f);      \
++   p2 = p5 + p2*stbi__f2f(-2.562915447f);      \
++   p3 = p3*stbi__f2f(-1.961570560f);           \
++   p4 = p4*stbi__f2f(-0.390180644f);           \
++   t3 += p1+p4;                                \
++   t2 += p2+p3;                                \
++   t1 += p2+p4;                                \
++   t0 += p1+p3;
++
++static void stbi__idct_block(stbi_uc *out, int out_stride, short data[64])
++{
++   int i,val[64],*v=val;
++   stbi_uc *o;
++   short *d = data;
++
++   // columns
++   for (i=0; i < 8; ++i,++d, ++v) {
++      // if all zeroes, shortcut -- this avoids dequantizing 0s and IDCTing
++      if (d[ 8]==0 && d[16]==0 && d[24]==0 && d[32]==0
++           && d[40]==0 && d[48]==0 && d[56]==0) {
++         //    no shortcut                 0     seconds
++         //    (1|2|3|4|5|6|7)==0          0     seconds
++         //    all separate               -0.047 seconds
++         //    1 && 2|3 && 4|5 && 6|7:    -0.047 seconds
++         int dcterm = d[0]*4;
++         v[0] = v[8] = v[16] = v[24] = v[32] = v[40] = v[48] = v[56] = dcterm;
++      } else {
++         STBI__IDCT_1D(d[ 0],d[ 8],d[16],d[24],d[32],d[40],d[48],d[56])
++         // constants scaled things up by 1<<12; let's bring them back
++         // down, but keep 2 extra bits of precision
++         x0 += 512; x1 += 512; x2 += 512; x3 += 512;
++         v[ 0] = (x0+t3) >> 10;
++         v[56] = (x0-t3) >> 10;
++         v[ 8] = (x1+t2) >> 10;
++         v[48] = (x1-t2) >> 10;
++         v[16] = (x2+t1) >> 10;
++         v[40] = (x2-t1) >> 10;
++         v[24] = (x3+t0) >> 10;
++         v[32] = (x3-t0) >> 10;
++      }
++   }
++
++   for (i=0, v=val, o=out; i < 8; ++i,v+=8,o+=out_stride) {
++      // no fast case since the first 1D IDCT spread components out
++      STBI__IDCT_1D(v[0],v[1],v[2],v[3],v[4],v[5],v[6],v[7])
++      // constants scaled things up by 1<<12, plus we had 1<<2 from first
++      // loop, plus horizontal and vertical each scale by sqrt(8) so together
++      // we've got an extra 1<<3, so 1<<17 total we need to remove.
++      // so we want to round that, which means adding 0.5 * 1<<17,
++      // aka 65536. Also, we'll end up with -128 to 127 that we want
++      // to encode as 0..255 by adding 128, so we'll add that before the shift
++      x0 += 65536 + (128<<17);
++      x1 += 65536 + (128<<17);
++      x2 += 65536 + (128<<17);
++      x3 += 65536 + (128<<17);
++      // tried computing the shifts into temps, or'ing the temps to see
++      // if any were out of range, but that was slower
++      o[0] = stbi__clamp((x0+t3) >> 17);
++      o[7] = stbi__clamp((x0-t3) >> 17);
++      o[1] = stbi__clamp((x1+t2) >> 17);
++      o[6] = stbi__clamp((x1-t2) >> 17);
++      o[2] = stbi__clamp((x2+t1) >> 17);
++      o[5] = stbi__clamp((x2-t1) >> 17);
++      o[3] = stbi__clamp((x3+t0) >> 17);
++      o[4] = stbi__clamp((x3-t0) >> 17);
++   }
++}
++
++#ifdef STBI_SSE2
++// sse2 integer IDCT. not the fastest possible implementation but it
++// produces bit-identical results to the generic C version so it's
++// fully "transparent".
++static void stbi__idct_simd(stbi_uc *out, int out_stride, short data[64])
++{
++   // This is constructed to match our regular (generic) integer IDCT exactly.
++   __m128i row0, row1, row2, row3, row4, row5, row6, row7;
++   __m128i tmp;
++
++   // dot product constant: even elems=x, odd elems=y
++   #define dct_const(x,y)  _mm_setr_epi16((x),(y),(x),(y),(x),(y),(x),(y))
++
++   // out(0) = c0[even]*x + c0[odd]*y   (c0, x, y 16-bit, out 32-bit)
++   // out(1) = c1[even]*x + c1[odd]*y
++   #define dct_rot(out0,out1, x,y,c0,c1) \
++      __m128i c0##lo = _mm_unpacklo_epi16((x),(y)); \
++      __m128i c0##hi = _mm_unpackhi_epi16((x),(y)); \
++      __m128i out0##_l = _mm_madd_epi16(c0##lo, c0); \
++      __m128i out0##_h = _mm_madd_epi16(c0##hi, c0); \
++      __m128i out1##_l = _mm_madd_epi16(c0##lo, c1); \
++      __m128i out1##_h = _mm_madd_epi16(c0##hi, c1)
++
++   // out = in << 12  (in 16-bit, out 32-bit)
++   #define dct_widen(out, in) \
++      __m128i out##_l = _mm_srai_epi32(_mm_unpacklo_epi16(_mm_setzero_si128(), (in)), 4); \
++      __m128i out##_h = _mm_srai_epi32(_mm_unpackhi_epi16(_mm_setzero_si128(), (in)), 4)
++
++   // wide add
++   #define dct_wadd(out, a, b) \
++      __m128i out##_l = _mm_add_epi32(a##_l, b##_l); \
++      __m128i out##_h = _mm_add_epi32(a##_h, b##_h)
++
++   // wide sub
++   #define dct_wsub(out, a, b) \
++      __m128i out##_l = _mm_sub_epi32(a##_l, b##_l); \
++      __m128i out##_h = _mm_sub_epi32(a##_h, b##_h)
++
++   // butterfly a/b, add bias, then shift by "s" and pack
++   #define dct_bfly32o(out0, out1, a,b,bias,s) \
++      { \
++         __m128i abiased_l = _mm_add_epi32(a##_l, bias); \
++         __m128i abiased_h = _mm_add_epi32(a##_h, bias); \
++         dct_wadd(sum, abiased, b); \
++         dct_wsub(dif, abiased, b); \
++         out0 = _mm_packs_epi32(_mm_srai_epi32(sum_l, s), _mm_srai_epi32(sum_h, s)); \
++         out1 = _mm_packs_epi32(_mm_srai_epi32(dif_l, s), _mm_srai_epi32(dif_h, s)); \
++      }
++
++   // 8-bit interleave step (for transposes)
++   #define dct_interleave8(a, b) \
++      tmp = a; \
++      a = _mm_unpacklo_epi8(a, b); \
++      b = _mm_unpackhi_epi8(tmp, b)
++
++   // 16-bit interleave step (for transposes)
++   #define dct_interleave16(a, b) \
++      tmp = a; \
++      a = _mm_unpacklo_epi16(a, b); \
++      b = _mm_unpackhi_epi16(tmp, b)
++
++   #define dct_pass(bias,shift) \
++      { \
++         /* even part */ \
++         dct_rot(t2e,t3e, row2,row6, rot0_0,rot0_1); \
++         __m128i sum04 = _mm_add_epi16(row0, row4); \
++         __m128i dif04 = _mm_sub_epi16(row0, row4); \
++         dct_widen(t0e, sum04); \
++         dct_widen(t1e, dif04); \
++         dct_wadd(x0, t0e, t3e); \
++         dct_wsub(x3, t0e, t3e); \
++         dct_wadd(x1, t1e, t2e); \
++         dct_wsub(x2, t1e, t2e); \
++         /* odd part */ \
++         dct_rot(y0o,y2o, row7,row3, rot2_0,rot2_1); \
++         dct_rot(y1o,y3o, row5,row1, rot3_0,rot3_1); \
++         __m128i sum17 = _mm_add_epi16(row1, row7); \
++         __m128i sum35 = _mm_add_epi16(row3, row5); \
++         dct_rot(y4o,y5o, sum17,sum35, rot1_0,rot1_1); \
++         dct_wadd(x4, y0o, y4o); \
++         dct_wadd(x5, y1o, y5o); \
++         dct_wadd(x6, y2o, y5o); \
++         dct_wadd(x7, y3o, y4o); \
++         dct_bfly32o(row0,row7, x0,x7,bias,shift); \
++         dct_bfly32o(row1,row6, x1,x6,bias,shift); \
++         dct_bfly32o(row2,row5, x2,x5,bias,shift); \
++         dct_bfly32o(row3,row4, x3,x4,bias,shift); \
++      }
++
++   __m128i rot0_0 = dct_const(stbi__f2f(0.5411961f), stbi__f2f(0.5411961f) + stbi__f2f(-1.847759065f));
++   __m128i rot0_1 = dct_const(stbi__f2f(0.5411961f) + stbi__f2f( 0.765366865f), stbi__f2f(0.5411961f));
++   __m128i rot1_0 = dct_const(stbi__f2f(1.175875602f) + stbi__f2f(-0.899976223f), stbi__f2f(1.175875602f));
++   __m128i rot1_1 = dct_const(stbi__f2f(1.175875602f), stbi__f2f(1.175875602f) + stbi__f2f(-2.562915447f));
++   __m128i rot2_0 = dct_const(stbi__f2f(-1.961570560f) + stbi__f2f( 0.298631336f), stbi__f2f(-1.961570560f));
++   __m128i rot2_1 = dct_const(stbi__f2f(-1.961570560f), stbi__f2f(-1.961570560f) + stbi__f2f( 3.072711026f));
++   __m128i rot3_0 = dct_const(stbi__f2f(-0.390180644f) + stbi__f2f( 2.053119869f), stbi__f2f(-0.390180644f));
++   __m128i rot3_1 = dct_const(stbi__f2f(-0.390180644f), stbi__f2f(-0.390180644f) + stbi__f2f( 1.501321110f));
++
++   // rounding biases in column/row passes, see stbi__idct_block for explanation.
++   __m128i bias_0 = _mm_set1_epi32(512);
++   __m128i bias_1 = _mm_set1_epi32(65536 + (128<<17));
++
++   // load
++   row0 = _mm_load_si128((const __m128i *) (data + 0*8));
++   row1 = _mm_load_si128((const __m128i *) (data + 1*8));
++   row2 = _mm_load_si128((const __m128i *) (data + 2*8));
++   row3 = _mm_load_si128((const __m128i *) (data + 3*8));
++   row4 = _mm_load_si128((const __m128i *) (data + 4*8));
++   row5 = _mm_load_si128((const __m128i *) (data + 5*8));
++   row6 = _mm_load_si128((const __m128i *) (data + 6*8));
++   row7 = _mm_load_si128((const __m128i *) (data + 7*8));
++
++   // column pass
++   dct_pass(bias_0, 10);
++
++   {
++      // 16bit 8x8 transpose pass 1
++      dct_interleave16(row0, row4);
++      dct_interleave16(row1, row5);
++      dct_interleave16(row2, row6);
++      dct_interleave16(row3, row7);
++
++      // transpose pass 2
++      dct_interleave16(row0, row2);
++      dct_interleave16(row1, row3);
++      dct_interleave16(row4, row6);
++      dct_interleave16(row5, row7);
++
++      // transpose pass 3
++      dct_interleave16(row0, row1);
++      dct_interleave16(row2, row3);
++      dct_interleave16(row4, row5);
++      dct_interleave16(row6, row7);
++   }
++
++   // row pass
++   dct_pass(bias_1, 17);
++
++   {
++      // pack
++      __m128i p0 = _mm_packus_epi16(row0, row1); // a0a1a2a3...a7b0b1b2b3...b7
++      __m128i p1 = _mm_packus_epi16(row2, row3);
++      __m128i p2 = _mm_packus_epi16(row4, row5);
++      __m128i p3 = _mm_packus_epi16(row6, row7);
++
++      // 8bit 8x8 transpose pass 1
++      dct_interleave8(p0, p2); // a0e0a1e1...
++      dct_interleave8(p1, p3); // c0g0c1g1...
++
++      // transpose pass 2
++      dct_interleave8(p0, p1); // a0c0e0g0...
++      dct_interleave8(p2, p3); // b0d0f0h0...
++
++      // transpose pass 3
++      dct_interleave8(p0, p2); // a0b0c0d0...
++      dct_interleave8(p1, p3); // a4b4c4d4...
++
++      // store
++      _mm_storel_epi64((__m128i *) out, p0); out += out_stride;
++      _mm_storel_epi64((__m128i *) out, _mm_shuffle_epi32(p0, 0x4e)); out += out_stride;
++      _mm_storel_epi64((__m128i *) out, p2); out += out_stride;
++      _mm_storel_epi64((__m128i *) out, _mm_shuffle_epi32(p2, 0x4e)); out += out_stride;
++      _mm_storel_epi64((__m128i *) out, p1); out += out_stride;
++      _mm_storel_epi64((__m128i *) out, _mm_shuffle_epi32(p1, 0x4e)); out += out_stride;
++      _mm_storel_epi64((__m128i *) out, p3); out += out_stride;
++      _mm_storel_epi64((__m128i *) out, _mm_shuffle_epi32(p3, 0x4e));
++   }
++
++#undef dct_const
++#undef dct_rot
++#undef dct_widen
++#undef dct_wadd
++#undef dct_wsub
++#undef dct_bfly32o
++#undef dct_interleave8
++#undef dct_interleave16
++#undef dct_pass
++}
++
++#endif // STBI_SSE2
++
++#ifdef STBI_NEON
++
++// NEON integer IDCT. should produce bit-identical
++// results to the generic C version.
++static void stbi__idct_simd(stbi_uc *out, int out_stride, short data[64])
++{
++   int16x8_t row0, row1, row2, row3, row4, row5, row6, row7;
++
++   int16x4_t rot0_0 = vdup_n_s16(stbi__f2f(0.5411961f));
++   int16x4_t rot0_1 = vdup_n_s16(stbi__f2f(-1.847759065f));
++   int16x4_t rot0_2 = vdup_n_s16(stbi__f2f( 0.765366865f));
++   int16x4_t rot1_0 = vdup_n_s16(stbi__f2f( 1.175875602f));
++   int16x4_t rot1_1 = vdup_n_s16(stbi__f2f(-0.899976223f));
++   int16x4_t rot1_2 = vdup_n_s16(stbi__f2f(-2.562915447f));
++   int16x4_t rot2_0 = vdup_n_s16(stbi__f2f(-1.961570560f));
++   int16x4_t rot2_1 = vdup_n_s16(stbi__f2f(-0.390180644f));
++   int16x4_t rot3_0 = vdup_n_s16(stbi__f2f( 0.298631336f));
++   int16x4_t rot3_1 = vdup_n_s16(stbi__f2f( 2.053119869f));
++   int16x4_t rot3_2 = vdup_n_s16(stbi__f2f( 3.072711026f));
++   int16x4_t rot3_3 = vdup_n_s16(stbi__f2f( 1.501321110f));
++
++#define dct_long_mul(out, inq, coeff) \
++   int32x4_t out##_l = vmull_s16(vget_low_s16(inq), coeff); \
++   int32x4_t out##_h = vmull_s16(vget_high_s16(inq), coeff)
++
++#define dct_long_mac(out, acc, inq, coeff) \
++   int32x4_t out##_l = vmlal_s16(acc##_l, vget_low_s16(inq), coeff); \
++   int32x4_t out##_h = vmlal_s16(acc##_h, vget_high_s16(inq), coeff)
++
++#define dct_widen(out, inq) \
++   int32x4_t out##_l = vshll_n_s16(vget_low_s16(inq), 12); \
++   int32x4_t out##_h = vshll_n_s16(vget_high_s16(inq), 12)
++
++// wide add
++#define dct_wadd(out, a, b) \
++   int32x4_t out##_l = vaddq_s32(a##_l, b##_l); \
++   int32x4_t out##_h = vaddq_s32(a##_h, b##_h)
++
++// wide sub
++#define dct_wsub(out, a, b) \
++   int32x4_t out##_l = vsubq_s32(a##_l, b##_l); \
++   int32x4_t out##_h = vsubq_s32(a##_h, b##_h)
++
++// butterfly a/b, then shift using "shiftop" by "s" and pack
++#define dct_bfly32o(out0,out1, a,b,shiftop,s) \
++   { \
++      dct_wadd(sum, a, b); \
++      dct_wsub(dif, a, b); \
++      out0 = vcombine_s16(shiftop(sum_l, s), shiftop(sum_h, s)); \
++      out1 = vcombine_s16(shiftop(dif_l, s), shiftop(dif_h, s)); \
++   }
++
++#define dct_pass(shiftop, shift) \
++   { \
++      /* even part */ \
++      int16x8_t sum26 = vaddq_s16(row2, row6); \
++      dct_long_mul(p1e, sum26, rot0_0); \
++      dct_long_mac(t2e, p1e, row6, rot0_1); \
++      dct_long_mac(t3e, p1e, row2, rot0_2); \
++      int16x8_t sum04 = vaddq_s16(row0, row4); \
++      int16x8_t dif04 = vsubq_s16(row0, row4); \
++      dct_widen(t0e, sum04); \
++      dct_widen(t1e, dif04); \
++      dct_wadd(x0, t0e, t3e); \
++      dct_wsub(x3, t0e, t3e); \
++      dct_wadd(x1, t1e, t2e); \
++      dct_wsub(x2, t1e, t2e); \
++      /* odd part */ \
++      int16x8_t sum15 = vaddq_s16(row1, row5); \
++      int16x8_t sum17 = vaddq_s16(row1, row7); \
++      int16x8_t sum35 = vaddq_s16(row3, row5); \
++      int16x8_t sum37 = vaddq_s16(row3, row7); \
++      int16x8_t sumodd = vaddq_s16(sum17, sum35); \
++      dct_long_mul(p5o, sumodd, rot1_0); \
++      dct_long_mac(p1o, p5o, sum17, rot1_1); \
++      dct_long_mac(p2o, p5o, sum35, rot1_2); \
++      dct_long_mul(p3o, sum37, rot2_0); \
++      dct_long_mul(p4o, sum15, rot2_1); \
++      dct_wadd(sump13o, p1o, p3o); \
++      dct_wadd(sump24o, p2o, p4o); \
++      dct_wadd(sump23o, p2o, p3o); \
++      dct_wadd(sump14o, p1o, p4o); \
++      dct_long_mac(x4, sump13o, row7, rot3_0); \
++      dct_long_mac(x5, sump24o, row5, rot3_1); \
++      dct_long_mac(x6, sump23o, row3, rot3_2); \
++      dct_long_mac(x7, sump14o, row1, rot3_3); \
++      dct_bfly32o(row0,row7, x0,x7,shiftop,shift); \
++      dct_bfly32o(row1,row6, x1,x6,shiftop,shift); \
++      dct_bfly32o(row2,row5, x2,x5,shiftop,shift); \
++      dct_bfly32o(row3,row4, x3,x4,shiftop,shift); \
++   }
++
++   // load
++   row0 = vld1q_s16(data + 0*8);
++   row1 = vld1q_s16(data + 1*8);
++   row2 = vld1q_s16(data + 2*8);
++   row3 = vld1q_s16(data + 3*8);
++   row4 = vld1q_s16(data + 4*8);
++   row5 = vld1q_s16(data + 5*8);
++   row6 = vld1q_s16(data + 6*8);
++   row7 = vld1q_s16(data + 7*8);
++
++   // add DC bias
++   row0 = vaddq_s16(row0, vsetq_lane_s16(1024, vdupq_n_s16(0), 0));
++
++   // column pass
++   dct_pass(vrshrn_n_s32, 10);
++
++   // 16bit 8x8 transpose
++   {
++// these three map to a single VTRN.16, VTRN.32, and VSWP, respectively.
++// whether compilers actually get this is another story, sadly.
++#define dct_trn16(x, y) { int16x8x2_t t = vtrnq_s16(x, y); x = t.val[0]; y = t.val[1]; }
++#define dct_trn32(x, y) { int32x4x2_t t = vtrnq_s32(vreinterpretq_s32_s16(x), vreinterpretq_s32_s16(y)); x = vreinterpretq_s16_s32(t.val[0]); y = vreinterpretq_s16_s32(t.val[1]); }
++#define dct_trn64(x, y) { int16x8_t x0 = x; int16x8_t y0 = y; x = vcombine_s16(vget_low_s16(x0), vget_low_s16(y0)); y = vcombine_s16(vget_high_s16(x0), vget_high_s16(y0)); }
++
++      // pass 1
++      dct_trn16(row0, row1); // a0b0a2b2a4b4a6b6
++      dct_trn16(row2, row3);
++      dct_trn16(row4, row5);
++      dct_trn16(row6, row7);
++
++      // pass 2
++      dct_trn32(row0, row2); // a0b0c0d0a4b4c4d4
++      dct_trn32(row1, row3);
++      dct_trn32(row4, row6);
++      dct_trn32(row5, row7);
++
++      // pass 3
++      dct_trn64(row0, row4); // a0b0c0d0e0f0g0h0
++      dct_trn64(row1, row5);
++      dct_trn64(row2, row6);
++      dct_trn64(row3, row7);
++
++#undef dct_trn16
++#undef dct_trn32
++#undef dct_trn64
++   }
++
++   // row pass
++   // vrshrn_n_s32 only supports shifts up to 16, we need
++   // 17. so do a non-rounding shift of 16 first then follow
++   // up with a rounding shift by 1.
++   dct_pass(vshrn_n_s32, 16);
++
++   {
++      // pack and round
++      uint8x8_t p0 = vqrshrun_n_s16(row0, 1);
++      uint8x8_t p1 = vqrshrun_n_s16(row1, 1);
++      uint8x8_t p2 = vqrshrun_n_s16(row2, 1);
++      uint8x8_t p3 = vqrshrun_n_s16(row3, 1);
++      uint8x8_t p4 = vqrshrun_n_s16(row4, 1);
++      uint8x8_t p5 = vqrshrun_n_s16(row5, 1);
++      uint8x8_t p6 = vqrshrun_n_s16(row6, 1);
++      uint8x8_t p7 = vqrshrun_n_s16(row7, 1);
++
++      // again, these can translate into one instruction, but often don't.
++#define dct_trn8_8(x, y) { uint8x8x2_t t = vtrn_u8(x, y); x = t.val[0]; y = t.val[1]; }
++#define dct_trn8_16(x, y) { uint16x4x2_t t = vtrn_u16(vreinterpret_u16_u8(x), vreinterpret_u16_u8(y)); x = vreinterpret_u8_u16(t.val[0]); y = vreinterpret_u8_u16(t.val[1]); }
++#define dct_trn8_32(x, y) { uint32x2x2_t t = vtrn_u32(vreinterpret_u32_u8(x), vreinterpret_u32_u8(y)); x = vreinterpret_u8_u32(t.val[0]); y = vreinterpret_u8_u32(t.val[1]); }
++
++      // sadly can't use interleaved stores here since we only write
++      // 8 bytes to each scan line!
++
++      // 8x8 8-bit transpose pass 1
++      dct_trn8_8(p0, p1);
++      dct_trn8_8(p2, p3);
++      dct_trn8_8(p4, p5);
++      dct_trn8_8(p6, p7);
++
++      // pass 2
++      dct_trn8_16(p0, p2);
++      dct_trn8_16(p1, p3);
++      dct_trn8_16(p4, p6);
++      dct_trn8_16(p5, p7);
++
++      // pass 3
++      dct_trn8_32(p0, p4);
++      dct_trn8_32(p1, p5);
++      dct_trn8_32(p2, p6);
++      dct_trn8_32(p3, p7);
++
++      // store
++      vst1_u8(out, p0); out += out_stride;
++      vst1_u8(out, p1); out += out_stride;
++      vst1_u8(out, p2); out += out_stride;
++      vst1_u8(out, p3); out += out_stride;
++      vst1_u8(out, p4); out += out_stride;
++      vst1_u8(out, p5); out += out_stride;
++      vst1_u8(out, p6); out += out_stride;
++      vst1_u8(out, p7);
++
++#undef dct_trn8_8
++#undef dct_trn8_16
++#undef dct_trn8_32
++   }
++
++#undef dct_long_mul
++#undef dct_long_mac
++#undef dct_widen
++#undef dct_wadd
++#undef dct_wsub
++#undef dct_bfly32o
++#undef dct_pass
++}
++
++#endif // STBI_NEON
++
++#define STBI__MARKER_none  0xff
++// if there's a pending marker from the entropy stream, return that
++// otherwise, fetch from the stream and get a marker. if there's no
++// marker, return 0xff, which is never a valid marker value
++static stbi_uc stbi__get_marker(stbi__jpeg *j)
++{
++   stbi_uc x;
++   if (j->marker != STBI__MARKER_none) { x = j->marker; j->marker = STBI__MARKER_none; return x; }
++   x = stbi__get8(j->s);
++   if (x != 0xff) return STBI__MARKER_none;
++   while (x == 0xff)
++      x = stbi__get8(j->s); // consume repeated 0xff fill bytes
++   return x;
++}
++
++// in each scan, we'll have scan_n components, and the order
++// of the components is specified by order[]
++#define STBI__RESTART(x)     ((x) >= 0xd0 && (x) <= 0xd7)
++
++// after a restart interval, stbi__jpeg_reset the entropy decoder and
++// the dc prediction
++static void stbi__jpeg_reset(stbi__jpeg *j)
++{
++   j->code_bits = 0;
++   j->code_buffer = 0;
++   j->nomore = 0;
++   j->img_comp[0].dc_pred = j->img_comp[1].dc_pred = j->img_comp[2].dc_pred = j->img_comp[3].dc_pred = 0;
++   j->marker = STBI__MARKER_none;
++   j->todo = j->restart_interval ? j->restart_interval : 0x7fffffff;
++   j->eob_run = 0;
++   // no more than 1<<31 MCUs if no restart_interal? that's plenty safe,
++   // since we don't even allow 1<<30 pixels
++}
++
++static int stbi__parse_entropy_coded_data(stbi__jpeg *z)
++{
++   stbi__jpeg_reset(z);
++   if (!z->progressive) {
++      if (z->scan_n == 1) {
++         int i,j;
++         STBI_SIMD_ALIGN(short, data[64]);
++         int n = z->order[0];
++         // non-interleaved data, we just need to process one block at a time,
++         // in trivial scanline order
++         // number of blocks to do just depends on how many actual "pixels" this
++         // component has, independent of interleaved MCU blocking and such
++         int w = (z->img_comp[n].x+7) >> 3;
++         int h = (z->img_comp[n].y+7) >> 3;
++         for (j=0; j < h; ++j) {
++            for (i=0; i < w; ++i) {
++               int ha = z->img_comp[n].ha;
++               if (!stbi__jpeg_decode_block(z, data, z->huff_dc+z->img_comp[n].hd, z->huff_ac+ha, z->fast_ac[ha], n, z->dequant[z->img_comp[n].tq])) return 0;
++               z->idct_block_kernel(z->img_comp[n].data+z->img_comp[n].w2*j*8+i*8, z->img_comp[n].w2, data);
++               // every data block is an MCU, so countdown the restart interval
++               if (--z->todo <= 0) {
++                  if (z->code_bits < 24) stbi__grow_buffer_unsafe(z);
++                  // if it's NOT a restart, then just bail, so we get corrupt data
++                  // rather than no data
++                  if (!STBI__RESTART(z->marker)) return 1;
++                  stbi__jpeg_reset(z);
++               }
++            }
++         }
++         return 1;
++      } else { // interleaved
++         int i,j,k,x,y;
++         STBI_SIMD_ALIGN(short, data[64]);
++         for (j=0; j < z->img_mcu_y; ++j) {
++            for (i=0; i < z->img_mcu_x; ++i) {
++               // scan an interleaved mcu... process scan_n components in order
++               for (k=0; k < z->scan_n; ++k) {
++                  int n = z->order[k];
++                  // scan out an mcu's worth of this component; that's just determined
++                  // by the basic H and V specified for the component
++                  for (y=0; y < z->img_comp[n].v; ++y) {
++                     for (x=0; x < z->img_comp[n].h; ++x) {
++                        int x2 = (i*z->img_comp[n].h + x)*8;
++                        int y2 = (j*z->img_comp[n].v + y)*8;
++                        int ha = z->img_comp[n].ha;
++                        if (!stbi__jpeg_decode_block(z, data, z->huff_dc+z->img_comp[n].hd, z->huff_ac+ha, z->fast_ac[ha], n, z->dequant[z->img_comp[n].tq])) return 0;
++                        z->idct_block_kernel(z->img_comp[n].data+z->img_comp[n].w2*y2+x2, z->img_comp[n].w2, data);
++                     }
++                  }
++               }
++               // after all interleaved components, that's an interleaved MCU,
++               // so now count down the restart interval
++               if (--z->todo <= 0) {
++                  if (z->code_bits < 24) stbi__grow_buffer_unsafe(z);
++                  if (!STBI__RESTART(z->marker)) return 1;
++                  stbi__jpeg_reset(z);
++               }
++            }
++         }
++         return 1;
++      }
++   } else {
++      if (z->scan_n == 1) {
++         int i,j;
++         int n = z->order[0];
++         // non-interleaved data, we just need to process one block at a time,
++         // in trivial scanline order
++         // number of blocks to do just depends on how many actual "pixels" this
++         // component has, independent of interleaved MCU blocking and such
++         int w = (z->img_comp[n].x+7) >> 3;
++         int h = (z->img_comp[n].y+7) >> 3;
++         for (j=0; j < h; ++j) {
++            for (i=0; i < w; ++i) {
++               short *data = z->img_comp[n].coeff + 64 * (i + j * z->img_comp[n].coeff_w);
++               if (z->spec_start == 0) {
++                  if (!stbi__jpeg_decode_block_prog_dc(z, data, &z->huff_dc[z->img_comp[n].hd], n))
++                     return 0;
++               } else {
++                  int ha = z->img_comp[n].ha;
++                  if (!stbi__jpeg_decode_block_prog_ac(z, data, &z->huff_ac[ha], z->fast_ac[ha]))
++                     return 0;
++               }
++               // every data block is an MCU, so countdown the restart interval
++               if (--z->todo <= 0) {
++                  if (z->code_bits < 24) stbi__grow_buffer_unsafe(z);
++                  if (!STBI__RESTART(z->marker)) return 1;
++                  stbi__jpeg_reset(z);
++               }
++            }
++         }
++         return 1;
++      } else { // interleaved
++         int i,j,k,x,y;
++         for (j=0; j < z->img_mcu_y; ++j) {
++            for (i=0; i < z->img_mcu_x; ++i) {
++               // scan an interleaved mcu... process scan_n components in order
++               for (k=0; k < z->scan_n; ++k) {
++                  int n = z->order[k];
++                  // scan out an mcu's worth of this component; that's just determined
++                  // by the basic H and V specified for the component
++                  for (y=0; y < z->img_comp[n].v; ++y) {
++                     for (x=0; x < z->img_comp[n].h; ++x) {
++                        int x2 = (i*z->img_comp[n].h + x);
++                        int y2 = (j*z->img_comp[n].v + y);
++                        short *data = z->img_comp[n].coeff + 64 * (x2 + y2 * z->img_comp[n].coeff_w);
++                        if (!stbi__jpeg_decode_block_prog_dc(z, data, &z->huff_dc[z->img_comp[n].hd], n))
++                           return 0;
++                     }
++                  }
++               }
++               // after all interleaved components, that's an interleaved MCU,
++               // so now count down the restart interval
++               if (--z->todo <= 0) {
++                  if (z->code_bits < 24) stbi__grow_buffer_unsafe(z);
++                  if (!STBI__RESTART(z->marker)) return 1;
++                  stbi__jpeg_reset(z);
++               }
++            }
++         }
++         return 1;
++      }
++   }
++}
++
++static void stbi__jpeg_dequantize(short *data, stbi__uint16 *dequant)
++{
++   int i;
++   for (i=0; i < 64; ++i)
++      data[i] *= dequant[i];
++}
++
++static void stbi__jpeg_finish(stbi__jpeg *z)
++{
++   if (z->progressive) {
++      // dequantize and idct the data
++      int i,j,n;
++      for (n=0; n < z->s->img_n; ++n) {
++         int w = (z->img_comp[n].x+7) >> 3;
++         int h = (z->img_comp[n].y+7) >> 3;
++         for (j=0; j < h; ++j) {
++            for (i=0; i < w; ++i) {
++               short *data = z->img_comp[n].coeff + 64 * (i + j * z->img_comp[n].coeff_w);
++               stbi__jpeg_dequantize(data, z->dequant[z->img_comp[n].tq]);
++               z->idct_block_kernel(z->img_comp[n].data+z->img_comp[n].w2*j*8+i*8, z->img_comp[n].w2, data);
++            }
++         }
++      }
++   }
++}
++
++static int stbi__process_marker(stbi__jpeg *z, int m)
++{
++   int L;
++   switch (m) {
++      case STBI__MARKER_none: // no marker found
++         return stbi__err("expected marker","Corrupt JPEG");
++
++      case 0xDD: // DRI - specify restart interval
++         if (stbi__get16be(z->s) != 4) return stbi__err("bad DRI len","Corrupt JPEG");
++         z->restart_interval = stbi__get16be(z->s);
++         return 1;
++
++      case 0xDB: // DQT - define quantization table
++         L = stbi__get16be(z->s)-2;
++         while (L > 0) {
++            int q = stbi__get8(z->s);
++            int p = q >> 4, sixteen = (p != 0);
++            int t = q & 15,i;
++            if (p != 0 && p != 1) return stbi__err("bad DQT type","Corrupt JPEG");
++            if (t > 3) return stbi__err("bad DQT table","Corrupt JPEG");
++
++            for (i=0; i < 64; ++i)
++               z->dequant[t][stbi__jpeg_dezigzag[i]] = (stbi__uint16)(sixteen ? stbi__get16be(z->s) : stbi__get8(z->s));
++            L -= (sixteen ? 129 : 65);
++         }
++         return L==0;
++
++      case 0xC4: // DHT - define huffman table
++         L = stbi__get16be(z->s)-2;
++         while (L > 0) {
++            stbi_uc *v;
++            int sizes[16],i,n=0;
++            int q = stbi__get8(z->s);
++            int tc = q >> 4;
++            int th = q & 15;
++            if (tc > 1 || th > 3) return stbi__err("bad DHT header","Corrupt JPEG");
++            for (i=0; i < 16; ++i) {
++               sizes[i] = stbi__get8(z->s);
++               n += sizes[i];
++            }
++            L -= 17;
++            if (tc == 0) {
++               if (!stbi__build_huffman(z->huff_dc+th, sizes)) return 0;
++               v = z->huff_dc[th].values;
++            } else {
++               if (!stbi__build_huffman(z->huff_ac+th, sizes)) return 0;
++               v = z->huff_ac[th].values;
++            }
++            for (i=0; i < n; ++i)
++               v[i] = stbi__get8(z->s);
++            if (tc != 0)
++               stbi__build_fast_ac(z->fast_ac[th], z->huff_ac + th);
++            L -= n;
++         }
++         return L==0;
++   }
++
++   // check for comment block or APP blocks
++   if ((m >= 0xE0 && m <= 0xEF) || m == 0xFE) {
++      L = stbi__get16be(z->s);
++      if (L < 2) {
++         if (m == 0xFE)
++            return stbi__err("bad COM len","Corrupt JPEG");
++         else
++            return stbi__err("bad APP len","Corrupt JPEG");
++      }
++      L -= 2;
++
++      if (m == 0xE0 && L >= 5) { // JFIF APP0 segment
++         static const unsigned char tag[5] = {'J','F','I','F','\0'};
++         int ok = 1;
++         int i;
++         for (i=0; i < 5; ++i)
++            if (stbi__get8(z->s) != tag[i])
++               ok = 0;
++         L -= 5;
++         if (ok)
++            z->jfif = 1;
++      } else if (m == 0xEE && L >= 12) { // Adobe APP14 segment
++         static const unsigned char tag[6] = {'A','d','o','b','e','\0'};
++         int ok = 1;
++         int i;
++         for (i=0; i < 6; ++i)
++            if (stbi__get8(z->s) != tag[i])
++               ok = 0;
++         L -= 6;
++         if (ok) {
++            stbi__get8(z->s); // version
++            stbi__get16be(z->s); // flags0
++            stbi__get16be(z->s); // flags1
++            z->app14_color_transform = stbi__get8(z->s); // color transform
++            L -= 6;
++         }
++      }
++
++      stbi__skip(z->s, L);
++      return 1;
++   }
++
++   return stbi__err("unknown marker","Corrupt JPEG");
++}
++
++// after we see SOS
++static int stbi__process_scan_header(stbi__jpeg *z)
++{
++   int i;
++   int Ls = stbi__get16be(z->s);
++   z->scan_n = stbi__get8(z->s);
++   if (z->scan_n < 1 || z->scan_n > 4 || z->scan_n > (int) z->s->img_n) return stbi__err("bad SOS component count","Corrupt JPEG");
++   if (Ls != 6+2*z->scan_n) return stbi__err("bad SOS len","Corrupt JPEG");
++   for (i=0; i < z->scan_n; ++i) {
++      int id = stbi__get8(z->s), which;
++      int q = stbi__get8(z->s);
++      for (which = 0; which < z->s->img_n; ++which)
++         if (z->img_comp[which].id == id)
++            break;
++      if (which == z->s->img_n) return 0; // no match
++      z->img_comp[which].hd = q >> 4;   if (z->img_comp[which].hd > 3) return stbi__err("bad DC huff","Corrupt JPEG");
++      z->img_comp[which].ha = q & 15;   if (z->img_comp[which].ha > 3) return stbi__err("bad AC huff","Corrupt JPEG");
++      z->order[i] = which;
++   }
++
++   {
++      int aa;
++      z->spec_start = stbi__get8(z->s);
++      z->spec_end   = stbi__get8(z->s); // should be 63, but might be 0
++      aa = stbi__get8(z->s);
++      z->succ_high = (aa >> 4);
++      z->succ_low  = (aa & 15);
++      if (z->progressive) {
++         if (z->spec_start > 63 || z->spec_end > 63  || z->spec_start > z->spec_end || z->succ_high > 13 || z->succ_low > 13)
++            return stbi__err("bad SOS", "Corrupt JPEG");
++      } else {
++         if (z->spec_start != 0) return stbi__err("bad SOS","Corrupt JPEG");
++         if (z->succ_high != 0 || z->succ_low != 0) return stbi__err("bad SOS","Corrupt JPEG");
++         z->spec_end = 63;
++      }
++   }
++
++   return 1;
++}
++
++static int stbi__free_jpeg_components(stbi__jpeg *z, int ncomp, int why)
++{
++   int i;
++   for (i=0; i < ncomp; ++i) {
++      if (z->img_comp[i].raw_data) {
++         STBI_FREE(z->img_comp[i].raw_data);
++         z->img_comp[i].raw_data = NULL;
++         z->img_comp[i].data = NULL;
++      }
++      if (z->img_comp[i].raw_coeff) {
++         STBI_FREE(z->img_comp[i].raw_coeff);
++         z->img_comp[i].raw_coeff = 0;
++         z->img_comp[i].coeff = 0;
++      }
++      if (z->img_comp[i].linebuf) {
++         STBI_FREE(z->img_comp[i].linebuf);
++         z->img_comp[i].linebuf = NULL;
++      }
++   }
++   return why;
++}
++
++static int stbi__process_frame_header(stbi__jpeg *z, int scan)
++{
++   stbi__context *s = z->s;
++   int Lf,p,i,q, h_max=1,v_max=1,c;
++   Lf = stbi__get16be(s);         if (Lf < 11) return stbi__err("bad SOF len","Corrupt JPEG"); // JPEG
++   p  = stbi__get8(s);            if (p != 8) return stbi__err("only 8-bit","JPEG format not supported: 8-bit only"); // JPEG baseline
++   s->img_y = stbi__get16be(s);   if (s->img_y == 0) return stbi__err("no header height", "JPEG format not supported: delayed height"); // Legal, but we don't handle it--but neither does IJG
++   s->img_x = stbi__get16be(s);   if (s->img_x == 0) return stbi__err("0 width","Corrupt JPEG"); // JPEG requires
++   c = stbi__get8(s);
++   if (c != 3 && c != 1 && c != 4) return stbi__err("bad component count","Corrupt JPEG");
++   s->img_n = c;
++   for (i=0; i < c; ++i) {
++      z->img_comp[i].data = NULL;
++      z->img_comp[i].linebuf = NULL;
++   }
++
++   if (Lf != 8+3*s->img_n) return stbi__err("bad SOF len","Corrupt JPEG");
++
++   z->rgb = 0;
++   for (i=0; i < s->img_n; ++i) {
++      static const unsigned char rgb[3] = { 'R', 'G', 'B' };
++      z->img_comp[i].id = stbi__get8(s);
++      if (s->img_n == 3 && z->img_comp[i].id == rgb[i])
++         ++z->rgb;
++      q = stbi__get8(s);
++      z->img_comp[i].h = (q >> 4);  if (!z->img_comp[i].h || z->img_comp[i].h > 4) return stbi__err("bad H","Corrupt JPEG");
++      z->img_comp[i].v = q & 15;    if (!z->img_comp[i].v || z->img_comp[i].v > 4) return stbi__err("bad V","Corrupt JPEG");
++      z->img_comp[i].tq = stbi__get8(s);  if (z->img_comp[i].tq > 3) return stbi__err("bad TQ","Corrupt JPEG");
++   }
++
++   if (scan != STBI__SCAN_load) return 1;
++
++   if (!stbi__mad3sizes_valid(s->img_x, s->img_y, s->img_n, 0)) return stbi__err("too large", "Image too large to decode");
++
++   for (i=0; i < s->img_n; ++i) {
++      if (z->img_comp[i].h > h_max) h_max = z->img_comp[i].h;
++      if (z->img_comp[i].v > v_max) v_max = z->img_comp[i].v;
++   }
++
++   // compute interleaved mcu info
++   z->img_h_max = h_max;
++   z->img_v_max = v_max;
++   z->img_mcu_w = h_max * 8;
++   z->img_mcu_h = v_max * 8;
++   // these sizes can't be more than 17 bits
++   z->img_mcu_x = (s->img_x + z->img_mcu_w-1) / z->img_mcu_w;
++   z->img_mcu_y = (s->img_y + z->img_mcu_h-1) / z->img_mcu_h;
++
++   for (i=0; i < s->img_n; ++i) {
++      // number of effective pixels (e.g. for non-interleaved MCU)
++      z->img_comp[i].x = (s->img_x * z->img_comp[i].h + h_max-1) / h_max;
++      z->img_comp[i].y = (s->img_y * z->img_comp[i].v + v_max-1) / v_max;
++      // to simplify generation, we'll allocate enough memory to decode
++      // the bogus oversized data from using interleaved MCUs and their
++      // big blocks (e.g. a 16x16 iMCU on an image of width 33); we won't
++      // discard the extra data until colorspace conversion
++      //
++      // img_mcu_x, img_mcu_y: <=17 bits; comp[i].h and .v are <=4 (checked earlier)
++      // so these muls can't overflow with 32-bit ints (which we require)
++      z->img_comp[i].w2 = z->img_mcu_x * z->img_comp[i].h * 8;
++      z->img_comp[i].h2 = z->img_mcu_y * z->img_comp[i].v * 8;
++      z->img_comp[i].coeff = 0;
++      z->img_comp[i].raw_coeff = 0;
++      z->img_comp[i].linebuf = NULL;
++      z->img_comp[i].raw_data = stbi__malloc_mad2(z->img_comp[i].w2, z->img_comp[i].h2, 15);
++      if (z->img_comp[i].raw_data == NULL)
++         return stbi__free_jpeg_components(z, i+1, stbi__err("outofmem", "Out of memory"));
++      // align blocks for idct using mmx/sse
++      z->img_comp[i].data = (stbi_uc*) (((size_t) z->img_comp[i].raw_data + 15) & ~15);
++      if (z->progressive) {
++         // w2, h2 are multiples of 8 (see above)
++         z->img_comp[i].coeff_w = z->img_comp[i].w2 / 8;
++         z->img_comp[i].coeff_h = z->img_comp[i].h2 / 8;
++         z->img_comp[i].raw_coeff = stbi__malloc_mad3(z->img_comp[i].w2, z->img_comp[i].h2, sizeof(short), 15);
++         if (z->img_comp[i].raw_coeff == NULL)
++            return stbi__free_jpeg_components(z, i+1, stbi__err("outofmem", "Out of memory"));
++         z->img_comp[i].coeff = (short*) (((size_t) z->img_comp[i].raw_coeff + 15) & ~15);
++      }
++   }
++
++   return 1;
++}
++
++// use comparisons since in some cases we handle more than one case (e.g. SOF)
++#define stbi__DNL(x)         ((x) == 0xdc)
++#define stbi__SOI(x)         ((x) == 0xd8)
++#define stbi__EOI(x)         ((x) == 0xd9)
++#define stbi__SOF(x)         ((x) == 0xc0 || (x) == 0xc1 || (x) == 0xc2)
++#define stbi__SOS(x)         ((x) == 0xda)
++
++#define stbi__SOF_progressive(x)   ((x) == 0xc2)
++
++static int stbi__decode_jpeg_header(stbi__jpeg *z, int scan)
++{
++   int m;
++   z->jfif = 0;
++   z->app14_color_transform = -1; // valid values are 0,1,2
++   z->marker = STBI__MARKER_none; // initialize cached marker to empty
++   m = stbi__get_marker(z);
++   if (!stbi__SOI(m)) return stbi__err("no SOI","Corrupt JPEG");
++   if (scan == STBI__SCAN_type) return 1;
++   m = stbi__get_marker(z);
++   while (!stbi__SOF(m)) {
++      if (!stbi__process_marker(z,m)) return 0;
++      m = stbi__get_marker(z);
++      while (m == STBI__MARKER_none) {
++         // some files have extra padding after their blocks, so ok, we'll scan
++         if (stbi__at_eof(z->s)) return stbi__err("no SOF", "Corrupt JPEG");
++         m = stbi__get_marker(z);
++      }
++   }
++   z->progressive = stbi__SOF_progressive(m);
++   if (!stbi__process_frame_header(z, scan)) return 0;
++   return 1;
++}
++
++// decode image to YCbCr format
++static int stbi__decode_jpeg_image(stbi__jpeg *j)
++{
++   int m;
++   for (m = 0; m < 4; m++) {
++      j->img_comp[m].raw_data = NULL;
++      j->img_comp[m].raw_coeff = NULL;
++   }
++   j->restart_interval = 0;
++   if (!stbi__decode_jpeg_header(j, STBI__SCAN_load)) return 0;
++   m = stbi__get_marker(j);
++   while (!stbi__EOI(m)) {
++      if (stbi__SOS(m)) {
++         if (!stbi__process_scan_header(j)) return 0;
++         if (!stbi__parse_entropy_coded_data(j)) return 0;
++         if (j->marker == STBI__MARKER_none ) {
++            // handle 0s at the end of image data from IP Kamera 9060
++            while (!stbi__at_eof(j->s)) {
++               int x = stbi__get8(j->s);
++               if (x == 255) {
++                  j->marker = stbi__get8(j->s);
++                  break;
++               }
++            }
++            // if we reach eof without hitting a marker, stbi__get_marker() below will fail and we'll eventually return 0
++         }
++      } else if (stbi__DNL(m)) {
++         int Ld = stbi__get16be(j->s);
++         stbi__uint32 NL = stbi__get16be(j->s);
++         if (Ld != 4) return stbi__err("bad DNL len", "Corrupt JPEG");
++         if (NL != j->s->img_y) return stbi__err("bad DNL height", "Corrupt JPEG");
++      } else {
++         if (!stbi__process_marker(j, m)) return 0;
++      }
++      m = stbi__get_marker(j);
++   }
++   if (j->progressive)
++      stbi__jpeg_finish(j);
++   return 1;
++}
++
++// static jfif-centered resampling (across block boundaries)
++
++typedef stbi_uc *(*resample_row_func)(stbi_uc *out, stbi_uc *in0, stbi_uc *in1,
++                                    int w, int hs);
++
++#define stbi__div4(x) ((stbi_uc) ((x) >> 2))
++
++static stbi_uc *resample_row_1(stbi_uc *out, stbi_uc *in_near, stbi_uc *in_far, int w, int hs)
++{
++   STBI_NOTUSED(out);
++   STBI_NOTUSED(in_far);
++   STBI_NOTUSED(w);
++   STBI_NOTUSED(hs);
++   return in_near;
++}
++
++static stbi_uc* stbi__resample_row_v_2(stbi_uc *out, stbi_uc *in_near, stbi_uc *in_far, int w, int hs)
++{
++   // need to generate two samples vertically for every one in input
++   int i;
++   STBI_NOTUSED(hs);
++   for (i=0; i < w; ++i)
++      out[i] = stbi__div4(3*in_near[i] + in_far[i] + 2);
++   return out;
++}
++
++static stbi_uc*  stbi__resample_row_h_2(stbi_uc *out, stbi_uc *in_near, stbi_uc *in_far, int w, int hs)
++{
++   // need to generate two samples horizontally for every one in input
++   int i;
++   stbi_uc *input = in_near;
++
++   if (w == 1) {
++      // if only one sample, can't do any interpolation
++      out[0] = out[1] = input[0];
++      return out;
++   }
++
++   out[0] = input[0];
++   out[1] = stbi__div4(input[0]*3 + input[1] + 2);
++   for (i=1; i < w-1; ++i) {
++      int n = 3*input[i]+2;
++      out[i*2+0] = stbi__div4(n+input[i-1]);
++      out[i*2+1] = stbi__div4(n+input[i+1]);
++   }
++   out[i*2+0] = stbi__div4(input[w-2]*3 + input[w-1] + 2);
++   out[i*2+1] = input[w-1];
++
++   STBI_NOTUSED(in_far);
++   STBI_NOTUSED(hs);
++
++   return out;
++}
++
++#define stbi__div16(x) ((stbi_uc) ((x) >> 4))
++
++static stbi_uc *stbi__resample_row_hv_2(stbi_uc *out, stbi_uc *in_near, stbi_uc *in_far, int w, int hs)
++{
++   // need to generate 2x2 samples for every one in input
++   int i,t0,t1;
++   if (w == 1) {
++      out[0] = out[1] = stbi__div4(3*in_near[0] + in_far[0] + 2);
++      return out;
++   }
++
++   t1 = 3*in_near[0] + in_far[0];
++   out[0] = stbi__div4(t1+2);
++   for (i=1; i < w; ++i) {
++      t0 = t1;
++      t1 = 3*in_near[i]+in_far[i];
++      out[i*2-1] = stbi__div16(3*t0 + t1 + 8);
++      out[i*2  ] = stbi__div16(3*t1 + t0 + 8);
++   }
++   out[w*2-1] = stbi__div4(t1+2);
++
++   STBI_NOTUSED(hs);
++
++   return out;
++}
++
++#if defined(STBI_SSE2) || defined(STBI_NEON)
++static stbi_uc *stbi__resample_row_hv_2_simd(stbi_uc *out, stbi_uc *in_near, stbi_uc *in_far, int w, int hs)
++{
++   // need to generate 2x2 samples for every one in input
++   int i=0,t0,t1;
++
++   if (w == 1) {
++      out[0] = out[1] = stbi__div4(3*in_near[0] + in_far[0] + 2);
++      return out;
++   }
++
++   t1 = 3*in_near[0] + in_far[0];
++   // process groups of 8 pixels for as long as we can.
++   // note we can't handle the last pixel in a row in this loop
++   // because we need to handle the filter boundary conditions.
++   for (; i < ((w-1) & ~7); i += 8) {
++#if defined(STBI_SSE2)
++      // load and perform the vertical filtering pass
++      // this uses 3*x + y = 4*x + (y - x)
++      __m128i zero  = _mm_setzero_si128();
++      __m128i farb  = _mm_loadl_epi64((__m128i *) (in_far + i));
++      __m128i nearb = _mm_loadl_epi64((__m128i *) (in_near + i));
++      __m128i farw  = _mm_unpacklo_epi8(farb, zero);
++      __m128i nearw = _mm_unpacklo_epi8(nearb, zero);
++      __m128i diff  = _mm_sub_epi16(farw, nearw);
++      __m128i nears = _mm_slli_epi16(nearw, 2);
++      __m128i curr  = _mm_add_epi16(nears, diff); // current row
++
++      // horizontal filter works the same based on shifted vers of current
++      // row. "prev" is current row shifted right by 1 pixel; we need to
++      // insert the previous pixel value (from t1).
++      // "next" is current row shifted left by 1 pixel, with first pixel
++      // of next block of 8 pixels added in.
++      __m128i prv0 = _mm_slli_si128(curr, 2);
++      __m128i nxt0 = _mm_srli_si128(curr, 2);
++      __m128i prev = _mm_insert_epi16(prv0, t1, 0);
++      __m128i next = _mm_insert_epi16(nxt0, 3*in_near[i+8] + in_far[i+8], 7);
++
++      // horizontal filter, polyphase implementation since it's convenient:
++      // even pixels = 3*cur + prev = cur*4 + (prev - cur)
++      // odd  pixels = 3*cur + next = cur*4 + (next - cur)
++      // note the shared term.
++      __m128i bias  = _mm_set1_epi16(8);
++      __m128i curs = _mm_slli_epi16(curr, 2);
++      __m128i prvd = _mm_sub_epi16(prev, curr);
++      __m128i nxtd = _mm_sub_epi16(next, curr);
++      __m128i curb = _mm_add_epi16(curs, bias);
++      __m128i even = _mm_add_epi16(prvd, curb);
++      __m128i odd  = _mm_add_epi16(nxtd, curb);
++
++      // interleave even and odd pixels, then undo scaling.
++      __m128i int0 = _mm_unpacklo_epi16(even, odd);
++      __m128i int1 = _mm_unpackhi_epi16(even, odd);
++      __m128i de0  = _mm_srli_epi16(int0, 4);
++      __m128i de1  = _mm_srli_epi16(int1, 4);
++
++      // pack and write output
++      __m128i outv = _mm_packus_epi16(de0, de1);
++      _mm_storeu_si128((__m128i *) (out + i*2), outv);
++#elif defined(STBI_NEON)
++      // load and perform the vertical filtering pass
++      // this uses 3*x + y = 4*x + (y - x)
++      uint8x8_t farb  = vld1_u8(in_far + i);
++      uint8x8_t nearb = vld1_u8(in_near + i);
++      int16x8_t diff  = vreinterpretq_s16_u16(vsubl_u8(farb, nearb));
++      int16x8_t nears = vreinterpretq_s16_u16(vshll_n_u8(nearb, 2));
++      int16x8_t curr  = vaddq_s16(nears, diff); // current row
++
++      // horizontal filter works the same based on shifted vers of current
++      // row. "prev" is current row shifted right by 1 pixel; we need to
++      // insert the previous pixel value (from t1).
++      // "next" is current row shifted left by 1 pixel, with first pixel
++      // of next block of 8 pixels added in.
++      int16x8_t prv0 = vextq_s16(curr, curr, 7);
++      int16x8_t nxt0 = vextq_s16(curr, curr, 1);
++      int16x8_t prev = vsetq_lane_s16(t1, prv0, 0);
++      int16x8_t next = vsetq_lane_s16(3*in_near[i+8] + in_far[i+8], nxt0, 7);
++
++      // horizontal filter, polyphase implementation since it's convenient:
++      // even pixels = 3*cur + prev = cur*4 + (prev - cur)
++      // odd  pixels = 3*cur + next = cur*4 + (next - cur)
++      // note the shared term.
++      int16x8_t curs = vshlq_n_s16(curr, 2);
++      int16x8_t prvd = vsubq_s16(prev, curr);
++      int16x8_t nxtd = vsubq_s16(next, curr);
++      int16x8_t even = vaddq_s16(curs, prvd);
++      int16x8_t odd  = vaddq_s16(curs, nxtd);
++
++      // undo scaling and round, then store with even/odd phases interleaved
++      uint8x8x2_t o;
++      o.val[0] = vqrshrun_n_s16(even, 4);
++      o.val[1] = vqrshrun_n_s16(odd,  4);
++      vst2_u8(out + i*2, o);
++#endif
++
++      // "previous" value for next iter
++      t1 = 3*in_near[i+7] + in_far[i+7];
++   }
++
++   t0 = t1;
++   t1 = 3*in_near[i] + in_far[i];
++   out[i*2] = stbi__div16(3*t1 + t0 + 8);
++
++   for (++i; i < w; ++i) {
++      t0 = t1;
++      t1 = 3*in_near[i]+in_far[i];
++      out[i*2-1] = stbi__div16(3*t0 + t1 + 8);
++      out[i*2  ] = stbi__div16(3*t1 + t0 + 8);
++   }
++   out[w*2-1] = stbi__div4(t1+2);
++
++   STBI_NOTUSED(hs);
++
++   return out;
++}
++#endif
++
++static stbi_uc *stbi__resample_row_generic(stbi_uc *out, stbi_uc *in_near, stbi_uc *in_far, int w, int hs)
++{
++   // resample with nearest-neighbor
++   int i,j;
++   STBI_NOTUSED(in_far);
++   for (i=0; i < w; ++i)
++      for (j=0; j < hs; ++j)
++         out[i*hs+j] = in_near[i];
++   return out;
++}
++
++// this is a reduced-precision calculation of YCbCr-to-RGB introduced
++// to make sure the code produces the same results in both SIMD and scalar
++#define stbi__float2fixed(x)  (((int) ((x) * 4096.0f + 0.5f)) << 8)
++static void stbi__YCbCr_to_RGB_row(stbi_uc *out, const stbi_uc *y, const stbi_uc *pcb, const stbi_uc *pcr, int count, int step)
++{
++   int i;
++   for (i=0; i < count; ++i) {
++      int y_fixed = (y[i] << 20) + (1<<19); // rounding
++      int r,g,b;
++      int cr = pcr[i] - 128;
++      int cb = pcb[i] - 128;
++      r = y_fixed +  cr* stbi__float2fixed(1.40200f);
++      g = y_fixed + (cr*-stbi__float2fixed(0.71414f)) + ((cb*-stbi__float2fixed(0.34414f)) & 0xffff0000);
++      b = y_fixed                                     +   cb* stbi__float2fixed(1.77200f);
++      r >>= 20;
++      g >>= 20;
++      b >>= 20;
++      if ((unsigned) r > 255) { if (r < 0) r = 0; else r = 255; }
++      if ((unsigned) g > 255) { if (g < 0) g = 0; else g = 255; }
++      if ((unsigned) b > 255) { if (b < 0) b = 0; else b = 255; }
++      out[0] = (stbi_uc)r;
++      out[1] = (stbi_uc)g;
++      out[2] = (stbi_uc)b;
++      out[3] = 255;
++      out += step;
++   }
++}
++
++#if defined(STBI_SSE2) || defined(STBI_NEON)
++static void stbi__YCbCr_to_RGB_simd(stbi_uc *out, stbi_uc const *y, stbi_uc const *pcb, stbi_uc const *pcr, int count, int step)
++{
++   int i = 0;
++
++#ifdef STBI_SSE2
++   // step == 3 is pretty ugly on the final interleave, and i'm not convinced
++   // it's useful in practice (you wouldn't use it for textures, for example).
++   // so just accelerate step == 4 case.
++   if (step == 4) {
++      // this is a fairly straightforward implementation and not super-optimized.
++      __m128i signflip  = _mm_set1_epi8(-0x80);
++      __m128i cr_const0 = _mm_set1_epi16(   (short) ( 1.40200f*4096.0f+0.5f));
++      __m128i cr_const1 = _mm_set1_epi16( - (short) ( 0.71414f*4096.0f+0.5f));
++      __m128i cb_const0 = _mm_set1_epi16( - (short) ( 0.34414f*4096.0f+0.5f));
++      __m128i cb_const1 = _mm_set1_epi16(   (short) ( 1.77200f*4096.0f+0.5f));
++      __m128i y_bias = _mm_set1_epi8((char) (unsigned char) 128);
++      __m128i xw = _mm_set1_epi16(255); // alpha channel
++
++      for (; i+7 < count; i += 8) {
++         // load
++         __m128i y_bytes = _mm_loadl_epi64((__m128i *) (y+i));
++         __m128i cr_bytes = _mm_loadl_epi64((__m128i *) (pcr+i));
++         __m128i cb_bytes = _mm_loadl_epi64((__m128i *) (pcb+i));
++         __m128i cr_biased = _mm_xor_si128(cr_bytes, signflip); // -128
++         __m128i cb_biased = _mm_xor_si128(cb_bytes, signflip); // -128
++
++         // unpack to short (and left-shift cr, cb by 8)
++         __m128i yw  = _mm_unpacklo_epi8(y_bias, y_bytes);
++         __m128i crw = _mm_unpacklo_epi8(_mm_setzero_si128(), cr_biased);
++         __m128i cbw = _mm_unpacklo_epi8(_mm_setzero_si128(), cb_biased);
++
++         // color transform
++         __m128i yws = _mm_srli_epi16(yw, 4);
++         __m128i cr0 = _mm_mulhi_epi16(cr_const0, crw);
++         __m128i cb0 = _mm_mulhi_epi16(cb_const0, cbw);
++         __m128i cb1 = _mm_mulhi_epi16(cbw, cb_const1);
++         __m128i cr1 = _mm_mulhi_epi16(crw, cr_const1);
++         __m128i rws = _mm_add_epi16(cr0, yws);
++         __m128i gwt = _mm_add_epi16(cb0, yws);
++         __m128i bws = _mm_add_epi16(yws, cb1);
++         __m128i gws = _mm_add_epi16(gwt, cr1);
++
++         // descale
++         __m128i rw = _mm_srai_epi16(rws, 4);
++         __m128i bw = _mm_srai_epi16(bws, 4);
++         __m128i gw = _mm_srai_epi16(gws, 4);
++
++         // back to byte, set up for transpose
++         __m128i brb = _mm_packus_epi16(rw, bw);
++         __m128i gxb = _mm_packus_epi16(gw, xw);
++
++         // transpose to interleave channels
++         __m128i t0 = _mm_unpacklo_epi8(brb, gxb);
++         __m128i t1 = _mm_unpackhi_epi8(brb, gxb);
++         __m128i o0 = _mm_unpacklo_epi16(t0, t1);
++         __m128i o1 = _mm_unpackhi_epi16(t0, t1);
++
++         // store
++         _mm_storeu_si128((__m128i *) (out + 0), o0);
++         _mm_storeu_si128((__m128i *) (out + 16), o1);
++         out += 32;
++      }
++   }
++#endif
++
++#ifdef STBI_NEON
++   // in this version, step=3 support would be easy to add. but is there demand?
++   if (step == 4) {
++      // this is a fairly straightforward implementation and not super-optimized.
++      uint8x8_t signflip = vdup_n_u8(0x80);
++      int16x8_t cr_const0 = vdupq_n_s16(   (short) ( 1.40200f*4096.0f+0.5f));
++      int16x8_t cr_const1 = vdupq_n_s16( - (short) ( 0.71414f*4096.0f+0.5f));
++      int16x8_t cb_const0 = vdupq_n_s16( - (short) ( 0.34414f*4096.0f+0.5f));
++      int16x8_t cb_const1 = vdupq_n_s16(   (short) ( 1.77200f*4096.0f+0.5f));
++
++      for (; i+7 < count; i += 8) {
++         // load
++         uint8x8_t y_bytes  = vld1_u8(y + i);
++         uint8x8_t cr_bytes = vld1_u8(pcr + i);
++         uint8x8_t cb_bytes = vld1_u8(pcb + i);
++         int8x8_t cr_biased = vreinterpret_s8_u8(vsub_u8(cr_bytes, signflip));
++         int8x8_t cb_biased = vreinterpret_s8_u8(vsub_u8(cb_bytes, signflip));
++
++         // expand to s16
++         int16x8_t yws = vreinterpretq_s16_u16(vshll_n_u8(y_bytes, 4));
++         int16x8_t crw = vshll_n_s8(cr_biased, 7);
++         int16x8_t cbw = vshll_n_s8(cb_biased, 7);
++
++         // color transform
++         int16x8_t cr0 = vqdmulhq_s16(crw, cr_const0);
++         int16x8_t cb0 = vqdmulhq_s16(cbw, cb_const0);
++         int16x8_t cr1 = vqdmulhq_s16(crw, cr_const1);
++         int16x8_t cb1 = vqdmulhq_s16(cbw, cb_const1);
++         int16x8_t rws = vaddq_s16(yws, cr0);
++         int16x8_t gws = vaddq_s16(vaddq_s16(yws, cb0), cr1);
++         int16x8_t bws = vaddq_s16(yws, cb1);
++
++         // undo scaling, round, convert to byte
++         uint8x8x4_t o;
++         o.val[0] = vqrshrun_n_s16(rws, 4);
++         o.val[1] = vqrshrun_n_s16(gws, 4);
++         o.val[2] = vqrshrun_n_s16(bws, 4);
++         o.val[3] = vdup_n_u8(255);
++
++         // store, interleaving r/g/b/a
++         vst4_u8(out, o);
++         out += 8*4;
++      }
++   }
++#endif
++
++   for (; i < count; ++i) {
++      int y_fixed = (y[i] << 20) + (1<<19); // rounding
++      int r,g,b;
++      int cr = pcr[i] - 128;
++      int cb = pcb[i] - 128;
++      r = y_fixed + cr* stbi__float2fixed(1.40200f);
++      g = y_fixed + cr*-stbi__float2fixed(0.71414f) + ((cb*-stbi__float2fixed(0.34414f)) & 0xffff0000);
++      b = y_fixed                                   +   cb* stbi__float2fixed(1.77200f);
++      r >>= 20;
++      g >>= 20;
++      b >>= 20;
++      if ((unsigned) r > 255) { if (r < 0) r = 0; else r = 255; }
++      if ((unsigned) g > 255) { if (g < 0) g = 0; else g = 255; }
++      if ((unsigned) b > 255) { if (b < 0) b = 0; else b = 255; }
++      out[0] = (stbi_uc)r;
++      out[1] = (stbi_uc)g;
++      out[2] = (stbi_uc)b;
++      out[3] = 255;
++      out += step;
++   }
++}
++#endif
++
++// set up the kernels
++static void stbi__setup_jpeg(stbi__jpeg *j)
++{
++   j->idct_block_kernel = stbi__idct_block;
++   j->YCbCr_to_RGB_kernel = stbi__YCbCr_to_RGB_row;
++   j->resample_row_hv_2_kernel = stbi__resample_row_hv_2;
++
++#ifdef STBI_SSE2
++   if (stbi__sse2_available()) {
++      j->idct_block_kernel = stbi__idct_simd;
++      j->YCbCr_to_RGB_kernel = stbi__YCbCr_to_RGB_simd;
++      j->resample_row_hv_2_kernel = stbi__resample_row_hv_2_simd;
++   }
++#endif
++
++#ifdef STBI_NEON
++   j->idct_block_kernel = stbi__idct_simd;
++   j->YCbCr_to_RGB_kernel = stbi__YCbCr_to_RGB_simd;
++   j->resample_row_hv_2_kernel = stbi__resample_row_hv_2_simd;
++#endif
++}
++
++// clean up the temporary component buffers
++static void stbi__cleanup_jpeg(stbi__jpeg *j)
++{
++   stbi__free_jpeg_components(j, j->s->img_n, 0);
++}
++
++typedef struct
++{
++   resample_row_func resample;
++   stbi_uc *line0,*line1;
++   int hs,vs;   // expansion factor in each axis
++   int w_lores; // horizontal pixels pre-expansion
++   int ystep;   // how far through vertical expansion we are
++   int ypos;    // which pre-expansion row we're on
++} stbi__resample;
++
++// fast 0..255 * 0..255 => 0..255 rounded multiplication
++static stbi_uc stbi__blinn_8x8(stbi_uc x, stbi_uc y)
++{
++   unsigned int t = x*y + 128;
++   return (stbi_uc) ((t + (t >>8)) >> 8);
++}
++
++static stbi_uc *load_jpeg_image(stbi__jpeg *z, int *out_x, int *out_y, int *comp, int req_comp)
++{
++   int n, decode_n, is_rgb;
++   z->s->img_n = 0; // make stbi__cleanup_jpeg safe
++
++   // validate req_comp
++   if (req_comp < 0 || req_comp > 4) return stbi__errpuc("bad req_comp", "Internal error");
++
++   // load a jpeg image from whichever source, but leave in YCbCr format
++   if (!stbi__decode_jpeg_image(z)) { stbi__cleanup_jpeg(z); return NULL; }
++
++   // determine actual number of components to generate
++   n = req_comp ? req_comp : z->s->img_n >= 3 ? 3 : 1;
++
++   is_rgb = z->s->img_n == 3 && (z->rgb == 3 || (z->app14_color_transform == 0 && !z->jfif));
++
++   if (z->s->img_n == 3 && n < 3 && !is_rgb)
++      decode_n = 1;
++   else
++      decode_n = z->s->img_n;
++
++   // resample and color-convert
++   {
++      int k;
++      unsigned int i,j;
++      stbi_uc *output;
++      stbi_uc *coutput[4];
++
++      stbi__resample res_comp[4];
++
++      for (k=0; k < decode_n; ++k) {
++         stbi__resample *r = &res_comp[k];
++
++         // allocate line buffer big enough for upsampling off the edges
++         // with upsample factor of 4
++         z->img_comp[k].linebuf = (stbi_uc *) stbi__malloc(z->s->img_x + 3);
++         if (!z->img_comp[k].linebuf) { stbi__cleanup_jpeg(z); return stbi__errpuc("outofmem", "Out of memory"); }
++
++         r->hs      = z->img_h_max / z->img_comp[k].h;
++         r->vs      = z->img_v_max / z->img_comp[k].v;
++         r->ystep   = r->vs >> 1;
++         r->w_lores = (z->s->img_x + r->hs-1) / r->hs;
++         r->ypos    = 0;
++         r->line0   = r->line1 = z->img_comp[k].data;
++
++         if      (r->hs == 1 && r->vs == 1) r->resample = resample_row_1;
++         else if (r->hs == 1 && r->vs == 2) r->resample = stbi__resample_row_v_2;
++         else if (r->hs == 2 && r->vs == 1) r->resample = stbi__resample_row_h_2;
++         else if (r->hs == 2 && r->vs == 2) r->resample = z->resample_row_hv_2_kernel;
++         else                               r->resample = stbi__resample_row_generic;
++      }
++
++      // can't error after this so, this is safe
++      output = (stbi_uc *) stbi__malloc_mad3(n, z->s->img_x, z->s->img_y, 1);
++      if (!output) { stbi__cleanup_jpeg(z); return stbi__errpuc("outofmem", "Out of memory"); }
++
++      // now go ahead and resample
++      for (j=0; j < z->s->img_y; ++j) {
++         stbi_uc *out = output + n * z->s->img_x * j;
++         for (k=0; k < decode_n; ++k) {
++            stbi__resample *r = &res_comp[k];
++            int y_bot = r->ystep >= (r->vs >> 1);
++            coutput[k] = r->resample(z->img_comp[k].linebuf,
++                                     y_bot ? r->line1 : r->line0,
++                                     y_bot ? r->line0 : r->line1,
++                                     r->w_lores, r->hs);
++            if (++r->ystep >= r->vs) {
++               r->ystep = 0;
++               r->line0 = r->line1;
++               if (++r->ypos < z->img_comp[k].y)
++                  r->line1 += z->img_comp[k].w2;
++            }
++         }
++         if (n >= 3) {
++            stbi_uc *y = coutput[0];
++            if (z->s->img_n == 3) {
++               if (is_rgb) {
++                  for (i=0; i < z->s->img_x; ++i) {
++                     out[0] = y[i];
++                     out[1] = coutput[1][i];
++                     out[2] = coutput[2][i];
++                     out[3] = 255;
++                     out += n;
++                  }
++               } else {
++                  z->YCbCr_to_RGB_kernel(out, y, coutput[1], coutput[2], z->s->img_x, n);
++               }
++            } else if (z->s->img_n == 4) {
++               if (z->app14_color_transform == 0) { // CMYK
++                  for (i=0; i < z->s->img_x; ++i) {
++                     stbi_uc m = coutput[3][i];
++                     out[0] = stbi__blinn_8x8(coutput[0][i], m);
++                     out[1] = stbi__blinn_8x8(coutput[1][i], m);
++                     out[2] = stbi__blinn_8x8(coutput[2][i], m);
++                     out[3] = 255;
++                     out += n;
++                  }
++               } else if (z->app14_color_transform == 2) { // YCCK
++                  z->YCbCr_to_RGB_kernel(out, y, coutput[1], coutput[2], z->s->img_x, n);
++                  for (i=0; i < z->s->img_x; ++i) {
++                     stbi_uc m = coutput[3][i];
++                     out[0] = stbi__blinn_8x8(255 - out[0], m);
++                     out[1] = stbi__blinn_8x8(255 - out[1], m);
++                     out[2] = stbi__blinn_8x8(255 - out[2], m);
++                     out += n;
++                  }
++               } else { // YCbCr + alpha?  Ignore the fourth channel for now
++                  z->YCbCr_to_RGB_kernel(out, y, coutput[1], coutput[2], z->s->img_x, n);
++               }
++            } else
++               for (i=0; i < z->s->img_x; ++i) {
++                  out[0] = out[1] = out[2] = y[i];
++                  out[3] = 255; // not used if n==3
++                  out += n;
++               }
++         } else {
++            if (is_rgb) {
++               if (n == 1)
++                  for (i=0; i < z->s->img_x; ++i)
++                     *out++ = stbi__compute_y(coutput[0][i], coutput[1][i], coutput[2][i]);
++               else {
++                  for (i=0; i < z->s->img_x; ++i, out += 2) {
++                     out[0] = stbi__compute_y(coutput[0][i], coutput[1][i], coutput[2][i]);
++                     out[1] = 255;
++                  }
++               }
++            } else if (z->s->img_n == 4 && z->app14_color_transform == 0) {
++               for (i=0; i < z->s->img_x; ++i) {
++                  stbi_uc m = coutput[3][i];
++                  stbi_uc r = stbi__blinn_8x8(coutput[0][i], m);
++                  stbi_uc g = stbi__blinn_8x8(coutput[1][i], m);
++                  stbi_uc b = stbi__blinn_8x8(coutput[2][i], m);
++                  out[0] = stbi__compute_y(r, g, b);
++                  out[1] = 255;
++                  out += n;
++               }
++            } else if (z->s->img_n == 4 && z->app14_color_transform == 2) {
++               for (i=0; i < z->s->img_x; ++i) {
++                  out[0] = stbi__blinn_8x8(255 - coutput[0][i], coutput[3][i]);
++                  out[1] = 255;
++                  out += n;
++               }
++            } else {
++               stbi_uc *y = coutput[0];
++               if (n == 1)
++                  for (i=0; i < z->s->img_x; ++i) out[i] = y[i];
++               else
++                  for (i=0; i < z->s->img_x; ++i) *out++ = y[i], *out++ = 255;
++            }
++         }
++      }
++      stbi__cleanup_jpeg(z);
++      *out_x = z->s->img_x;
++      *out_y = z->s->img_y;
++      if (comp) *comp = z->s->img_n >= 3 ? 3 : 1; // report original components, not output
++      return output;
++   }
++}
++
++static void *stbi__jpeg_load(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri)
++{
++   unsigned char* result;
++   stbi__jpeg* j = (stbi__jpeg*) stbi__malloc(sizeof(stbi__jpeg));
++   STBI_NOTUSED(ri);
++   j->s = s;
++   stbi__setup_jpeg(j);
++   result = load_jpeg_image(j, x,y,comp,req_comp);
++   STBI_FREE(j);
++   return result;
++}
++
++static int stbi__jpeg_test(stbi__context *s)
++{
++   int r;
++   stbi__jpeg* j = (stbi__jpeg*)stbi__malloc(sizeof(stbi__jpeg));
++   j->s = s;
++   stbi__setup_jpeg(j);
++   r = stbi__decode_jpeg_header(j, STBI__SCAN_type);
++   stbi__rewind(s);
++   STBI_FREE(j);
++   return r;
++}
++
++static int stbi__jpeg_info_raw(stbi__jpeg *j, int *x, int *y, int *comp)
++{
++   if (!stbi__decode_jpeg_header(j, STBI__SCAN_header)) {
++      stbi__rewind( j->s );
++      return 0;
++   }
++   if (x) *x = j->s->img_x;
++   if (y) *y = j->s->img_y;
++   if (comp) *comp = j->s->img_n >= 3 ? 3 : 1;
++   return 1;
++}
++
++static int stbi__jpeg_info(stbi__context *s, int *x, int *y, int *comp)
++{
++   int result;
++   stbi__jpeg* j = (stbi__jpeg*) (stbi__malloc(sizeof(stbi__jpeg)));
++   j->s = s;
++   result = stbi__jpeg_info_raw(j, x, y, comp);
++   STBI_FREE(j);
++   return result;
++}
++#endif
++
++// public domain zlib decode    v0.2  Sean Barrett 2006-11-18
++//    simple implementation
++//      - all input must be provided in an upfront buffer
++//      - all output is written to a single output buffer (can malloc/realloc)
++//    performance
++//      - fast huffman
++
++#ifndef STBI_NO_ZLIB
++
++// fast-way is faster to check than jpeg huffman, but slow way is slower
++#define STBI__ZFAST_BITS  9 // accelerate all cases in default tables
++#define STBI__ZFAST_MASK  ((1 << STBI__ZFAST_BITS) - 1)
++
++// zlib-style huffman encoding
++// (jpegs packs from left, zlib from right, so can't share code)
++typedef struct
++{
++   stbi__uint16 fast[1 << STBI__ZFAST_BITS];
++   stbi__uint16 firstcode[16];
++   int maxcode[17];
++   stbi__uint16 firstsymbol[16];
++   stbi_uc  size[288];
++   stbi__uint16 value[288];
++} stbi__zhuffman;
++
++stbi_inline static int stbi__bitreverse16(int n)
++{
++  n = ((n & 0xAAAA) >>  1) | ((n & 0x5555) << 1);
++  n = ((n & 0xCCCC) >>  2) | ((n & 0x3333) << 2);
++  n = ((n & 0xF0F0) >>  4) | ((n & 0x0F0F) << 4);
++  n = ((n & 0xFF00) >>  8) | ((n & 0x00FF) << 8);
++  return n;
++}
++
++stbi_inline static int stbi__bit_reverse(int v, int bits)
++{
++   STBI_ASSERT(bits <= 16);
++   // to bit reverse n bits, reverse 16 and shift
++   // e.g. 11 bits, bit reverse and shift away 5
++   return stbi__bitreverse16(v) >> (16-bits);
++}
++
++static int stbi__zbuild_huffman(stbi__zhuffman *z, const stbi_uc *sizelist, int num)
++{
++   int i,k=0;
++   int code, next_code[16], sizes[17];
++
++   // DEFLATE spec for generating codes
++   memset(sizes, 0, sizeof(sizes));
++   memset(z->fast, 0, sizeof(z->fast));
++   for (i=0; i < num; ++i)
++      ++sizes[sizelist[i]];
++   sizes[0] = 0;
++   for (i=1; i < 16; ++i)
++      if (sizes[i] > (1 << i))
++         return stbi__err("bad sizes", "Corrupt PNG");
++   code = 0;
++   for (i=1; i < 16; ++i) {
++      next_code[i] = code;
++      z->firstcode[i] = (stbi__uint16) code;
++      z->firstsymbol[i] = (stbi__uint16) k;
++      code = (code + sizes[i]);
++      if (sizes[i])
++         if (code-1 >= (1 << i)) return stbi__err("bad codelengths","Corrupt PNG");
++      z->maxcode[i] = code << (16-i); // preshift for inner loop
++      code <<= 1;
++      k += sizes[i];
++   }
++   z->maxcode[16] = 0x10000; // sentinel
++   for (i=0; i < num; ++i) {
++      int s = sizelist[i];
++      if (s) {
++         int c = next_code[s] - z->firstcode[s] + z->firstsymbol[s];
++         stbi__uint16 fastv = (stbi__uint16) ((s << 9) | i);
++         z->size [c] = (stbi_uc     ) s;
++         z->value[c] = (stbi__uint16) i;
++         if (s <= STBI__ZFAST_BITS) {
++            int j = stbi__bit_reverse(next_code[s],s);
++            while (j < (1 << STBI__ZFAST_BITS)) {
++               z->fast[j] = fastv;
++               j += (1 << s);
++            }
++         }
++         ++next_code[s];
++      }
++   }
++   return 1;
++}
++
++// zlib-from-memory implementation for PNG reading
++//    because PNG allows splitting the zlib stream arbitrarily,
++//    and it's annoying structurally to have PNG call ZLIB call PNG,
++//    we require PNG read all the IDATs and combine them into a single
++//    memory buffer
++
++typedef struct
++{
++   stbi_uc *zbuffer, *zbuffer_end;
++   int num_bits;
++   stbi__uint32 code_buffer;
++
++   char *zout;
++   char *zout_start;
++   char *zout_end;
++   int   z_expandable;
++
++   stbi__zhuffman z_length, z_distance;
++} stbi__zbuf;
++
++stbi_inline static stbi_uc stbi__zget8(stbi__zbuf *z)
++{
++   if (z->zbuffer >= z->zbuffer_end) return 0;
++   return *z->zbuffer++;
++}
++
++static void stbi__fill_bits(stbi__zbuf *z)
++{
++   do {
++      STBI_ASSERT(z->code_buffer < (1U << z->num_bits));
++      z->code_buffer |= (unsigned int) stbi__zget8(z) << z->num_bits;
++      z->num_bits += 8;
++   } while (z->num_bits <= 24);
++}
++
++stbi_inline static unsigned int stbi__zreceive(stbi__zbuf *z, int n)
++{
++   unsigned int k;
++   if (z->num_bits < n) stbi__fill_bits(z);
++   k = z->code_buffer & ((1 << n) - 1);
++   z->code_buffer >>= n;
++   z->num_bits -= n;
++   return k;
++}
++
++static int stbi__zhuffman_decode_slowpath(stbi__zbuf *a, stbi__zhuffman *z)
++{
++   int b,s,k;
++   // not resolved by fast table, so compute it the slow way
++   // use jpeg approach, which requires MSbits at top
++   k = stbi__bit_reverse(a->code_buffer, 16);
++   for (s=STBI__ZFAST_BITS+1; ; ++s)
++      if (k < z->maxcode[s])
++         break;
++   if (s == 16) return -1; // invalid code!
++   // code size is s, so:
++   b = (k >> (16-s)) - z->firstcode[s] + z->firstsymbol[s];
++   STBI_ASSERT(z->size[b] == s);
++   a->code_buffer >>= s;
++   a->num_bits -= s;
++   return z->value[b];
++}
++
++stbi_inline static int stbi__zhuffman_decode(stbi__zbuf *a, stbi__zhuffman *z)
++{
++   int b,s;
++   if (a->num_bits < 16) stbi__fill_bits(a);
++   b = z->fast[a->code_buffer & STBI__ZFAST_MASK];
++   if (b) {
++      s = b >> 9;
++      a->code_buffer >>= s;
++      a->num_bits -= s;
++      return b & 511;
++   }
++   return stbi__zhuffman_decode_slowpath(a, z);
++}
++
++static int stbi__zexpand(stbi__zbuf *z, char *zout, int n)  // need to make room for n bytes
++{
++   char *q;
++   int cur, limit, old_limit;
++   z->zout = zout;
++   if (!z->z_expandable) return stbi__err("output buffer limit","Corrupt PNG");
++   cur   = (int) (z->zout     - z->zout_start);
++   limit = old_limit = (int) (z->zout_end - z->zout_start);
++   while (cur + n > limit)
++      limit *= 2;
++   q = (char *) STBI_REALLOC_SIZED(z->zout_start, old_limit, limit);
++   STBI_NOTUSED(old_limit);
++   if (q == NULL) return stbi__err("outofmem", "Out of memory");
++   z->zout_start = q;
++   z->zout       = q + cur;
++   z->zout_end   = q + limit;
++   return 1;
++}
++
++static const int stbi__zlength_base[31] = {
++   3,4,5,6,7,8,9,10,11,13,
++   15,17,19,23,27,31,35,43,51,59,
++   67,83,99,115,131,163,195,227,258,0,0 };
++
++static const int stbi__zlength_extra[31]=
++{ 0,0,0,0,0,0,0,0,1,1,1,1,2,2,2,2,3,3,3,3,4,4,4,4,5,5,5,5,0,0,0 };
++
++static const int stbi__zdist_base[32] = { 1,2,3,4,5,7,9,13,17,25,33,49,65,97,129,193,
++257,385,513,769,1025,1537,2049,3073,4097,6145,8193,12289,16385,24577,0,0};
++
++static const int stbi__zdist_extra[32] =
++{ 0,0,0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13};
++
++static int stbi__parse_huffman_block(stbi__zbuf *a)
++{
++   char *zout = a->zout;
++   for(;;) {
++      int z = stbi__zhuffman_decode(a, &a->z_length);
++      if (z < 256) {
++         if (z < 0) return stbi__err("bad huffman code","Corrupt PNG"); // error in huffman codes
++         if (zout >= a->zout_end) {
++            if (!stbi__zexpand(a, zout, 1)) return 0;
++            zout = a->zout;
++         }
++         *zout++ = (char) z;
++      } else {
++         stbi_uc *p;
++         int len,dist;
++         if (z == 256) {
++            a->zout = zout;
++            return 1;
++         }
++         z -= 257;
++         len = stbi__zlength_base[z];
++         if (stbi__zlength_extra[z]) len += stbi__zreceive(a, stbi__zlength_extra[z]);
++         z = stbi__zhuffman_decode(a, &a->z_distance);
++         if (z < 0) return stbi__err("bad huffman code","Corrupt PNG");
++         dist = stbi__zdist_base[z];
++         if (stbi__zdist_extra[z]) dist += stbi__zreceive(a, stbi__zdist_extra[z]);
++         if (zout - a->zout_start < dist) return stbi__err("bad dist","Corrupt PNG");
++         if (zout + len > a->zout_end) {
++            if (!stbi__zexpand(a, zout, len)) return 0;
++            zout = a->zout;
++         }
++         p = (stbi_uc *) (zout - dist);
++         if (dist == 1) { // run of one byte; common in images.
++            stbi_uc v = *p;
++            if (len) { do *zout++ = v; while (--len); }
++         } else {
++            if (len) { do *zout++ = *p++; while (--len); }
++         }
++      }
++   }
++}
++
++static int stbi__compute_huffman_codes(stbi__zbuf *a)
++{
++   static const stbi_uc length_dezigzag[19] = { 16,17,18,0,8,7,9,6,10,5,11,4,12,3,13,2,14,1,15 };
++   stbi__zhuffman z_codelength;
++   stbi_uc lencodes[286+32+137];//padding for maximum single op
++   stbi_uc codelength_sizes[19];
++   int i,n;
++
++   int hlit  = stbi__zreceive(a,5) + 257;
++   int hdist = stbi__zreceive(a,5) + 1;
++   int hclen = stbi__zreceive(a,4) + 4;
++   int ntot  = hlit + hdist;
++
++   memset(codelength_sizes, 0, sizeof(codelength_sizes));
++   for (i=0; i < hclen; ++i) {
++      int s = stbi__zreceive(a,3);
++      codelength_sizes[length_dezigzag[i]] = (stbi_uc) s;
++   }
++   if (!stbi__zbuild_huffman(&z_codelength, codelength_sizes, 19)) return 0;
++
++   n = 0;
++   while (n < ntot) {
++      int c = stbi__zhuffman_decode(a, &z_codelength);
++      if (c < 0 || c >= 19) return stbi__err("bad codelengths", "Corrupt PNG");
++      if (c < 16)
++         lencodes[n++] = (stbi_uc) c;
++      else {
++         stbi_uc fill = 0;
++         if (c == 16) {
++            c = stbi__zreceive(a,2)+3;
++            if (n == 0) return stbi__err("bad codelengths", "Corrupt PNG");
++            fill = lencodes[n-1];
++         } else if (c == 17)
++            c = stbi__zreceive(a,3)+3;
++         else {
++            STBI_ASSERT(c == 18);
++            c = stbi__zreceive(a,7)+11;
++         }
++         if (ntot - n < c) return stbi__err("bad codelengths", "Corrupt PNG");
++         memset(lencodes+n, fill, c);
++         n += c;
++      }
++   }
++   if (n != ntot) return stbi__err("bad codelengths","Corrupt PNG");
++   if (!stbi__zbuild_huffman(&a->z_length, lencodes, hlit)) return 0;
++   if (!stbi__zbuild_huffman(&a->z_distance, lencodes+hlit, hdist)) return 0;
++   return 1;
++}
++
++static int stbi__parse_uncompressed_block(stbi__zbuf *a)
++{
++   stbi_uc header[4];
++   int len,nlen,k;
++   if (a->num_bits & 7)
++      stbi__zreceive(a, a->num_bits & 7); // discard
++   // drain the bit-packed data into header
++   k = 0;
++   while (a->num_bits > 0) {
++      header[k++] = (stbi_uc) (a->code_buffer & 255); // suppress MSVC run-time check
++      a->code_buffer >>= 8;
++      a->num_bits -= 8;
++   }
++   STBI_ASSERT(a->num_bits == 0);
++   // now fill header the normal way
++   while (k < 4)
++      header[k++] = stbi__zget8(a);
++   len  = header[1] * 256 + header[0];
++   nlen = header[3] * 256 + header[2];
++   if (nlen != (len ^ 0xffff)) return stbi__err("zlib corrupt","Corrupt PNG");
++   if (a->zbuffer + len > a->zbuffer_end) return stbi__err("read past buffer","Corrupt PNG");
++   if (a->zout + len > a->zout_end)
++      if (!stbi__zexpand(a, a->zout, len)) return 0;
++   memcpy(a->zout, a->zbuffer, len);
++   a->zbuffer += len;
++   a->zout += len;
++   return 1;
++}
++
++static int stbi__parse_zlib_header(stbi__zbuf *a)
++{
++   int cmf   = stbi__zget8(a);
++   int cm    = cmf & 15;
++   /* int cinfo = cmf >> 4; */
++   int flg   = stbi__zget8(a);
++   if ((cmf*256+flg) % 31 != 0) return stbi__err("bad zlib header","Corrupt PNG"); // zlib spec
++   if (flg & 32) return stbi__err("no preset dict","Corrupt PNG"); // preset dictionary not allowed in png
++   if (cm != 8) return stbi__err("bad compression","Corrupt PNG"); // DEFLATE required for png
++   // window = 1 << (8 + cinfo)... but who cares, we fully buffer output
++   return 1;
++}
++
++static const stbi_uc stbi__zdefault_length[288] =
++{
++   8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
++   8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
++   8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
++   8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
++   8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
++   9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
++   9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
++   9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9, 9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
++   7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7, 7,7,7,7,7,7,7,7,8,8,8,8,8,8,8,8
++};
++static const stbi_uc stbi__zdefault_distance[32] =
++{
++   5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5
++};
++/*
++Init algorithm:
++{
++   int i;   // use <= to match clearly with spec
++   for (i=0; i <= 143; ++i)     stbi__zdefault_length[i]   = 8;
++   for (   ; i <= 255; ++i)     stbi__zdefault_length[i]   = 9;
++   for (   ; i <= 279; ++i)     stbi__zdefault_length[i]   = 7;
++   for (   ; i <= 287; ++i)     stbi__zdefault_length[i]   = 8;
++
++   for (i=0; i <=  31; ++i)     stbi__zdefault_distance[i] = 5;
++}
++*/
++
++static int stbi__parse_zlib(stbi__zbuf *a, int parse_header)
++{
++   int final, type;
++   if (parse_header)
++      if (!stbi__parse_zlib_header(a)) return 0;
++   a->num_bits = 0;
++   a->code_buffer = 0;
++   do {
++      final = stbi__zreceive(a,1);
++      type = stbi__zreceive(a,2);
++      if (type == 0) {
++         if (!stbi__parse_uncompressed_block(a)) return 0;
++      } else if (type == 3) {
++         return 0;
++      } else {
++         if (type == 1) {
++            // use fixed code lengths
++            if (!stbi__zbuild_huffman(&a->z_length  , stbi__zdefault_length  , 288)) return 0;
++            if (!stbi__zbuild_huffman(&a->z_distance, stbi__zdefault_distance,  32)) return 0;
++         } else {
++            if (!stbi__compute_huffman_codes(a)) return 0;
++         }
++         if (!stbi__parse_huffman_block(a)) return 0;
++      }
++   } while (!final);
++   return 1;
++}
++
++static int stbi__do_zlib(stbi__zbuf *a, char *obuf, int olen, int exp, int parse_header)
++{
++   a->zout_start = obuf;
++   a->zout       = obuf;
++   a->zout_end   = obuf + olen;
++   a->z_expandable = exp;
++
++   return stbi__parse_zlib(a, parse_header);
++}
++
++STBIDEF char *stbi_zlib_decode_malloc_guesssize(const char *buffer, int len, int initial_size, int *outlen)
++{
++   stbi__zbuf a;
++   char *p = (char *) stbi__malloc(initial_size);
++   if (p == NULL) return NULL;
++   a.zbuffer = (stbi_uc *) buffer;
++   a.zbuffer_end = (stbi_uc *) buffer + len;
++   if (stbi__do_zlib(&a, p, initial_size, 1, 1)) {
++      if (outlen) *outlen = (int) (a.zout - a.zout_start);
++      return a.zout_start;
++   } else {
++      STBI_FREE(a.zout_start);
++      return NULL;
++   }
++}
++
++STBIDEF char *stbi_zlib_decode_malloc(char const *buffer, int len, int *outlen)
++{
++   return stbi_zlib_decode_malloc_guesssize(buffer, len, 16384, outlen);
++}
++
++STBIDEF char *stbi_zlib_decode_malloc_guesssize_headerflag(const char *buffer, int len, int initial_size, int *outlen, int parse_header)
++{
++   stbi__zbuf a;
++   char *p = (char *) stbi__malloc(initial_size);
++   if (p == NULL) return NULL;
++   a.zbuffer = (stbi_uc *) buffer;
++   a.zbuffer_end = (stbi_uc *) buffer + len;
++   if (stbi__do_zlib(&a, p, initial_size, 1, parse_header)) {
++      if (outlen) *outlen = (int) (a.zout - a.zout_start);
++      return a.zout_start;
++   } else {
++      STBI_FREE(a.zout_start);
++      return NULL;
++   }
++}
++
++STBIDEF int stbi_zlib_decode_buffer(char *obuffer, int olen, char const *ibuffer, int ilen)
++{
++   stbi__zbuf a;
++   a.zbuffer = (stbi_uc *) ibuffer;
++   a.zbuffer_end = (stbi_uc *) ibuffer + ilen;
++   if (stbi__do_zlib(&a, obuffer, olen, 0, 1))
++      return (int) (a.zout - a.zout_start);
++   else
++      return -1;
++}
++
++STBIDEF char *stbi_zlib_decode_noheader_malloc(char const *buffer, int len, int *outlen)
++{
++   stbi__zbuf a;
++   char *p = (char *) stbi__malloc(16384);
++   if (p == NULL) return NULL;
++   a.zbuffer = (stbi_uc *) buffer;
++   a.zbuffer_end = (stbi_uc *) buffer+len;
++   if (stbi__do_zlib(&a, p, 16384, 1, 0)) {
++      if (outlen) *outlen = (int) (a.zout - a.zout_start);
++      return a.zout_start;
++   } else {
++      STBI_FREE(a.zout_start);
++      return NULL;
++   }
++}
++
++STBIDEF int stbi_zlib_decode_noheader_buffer(char *obuffer, int olen, const char *ibuffer, int ilen)
++{
++   stbi__zbuf a;
++   a.zbuffer = (stbi_uc *) ibuffer;
++   a.zbuffer_end = (stbi_uc *) ibuffer + ilen;
++   if (stbi__do_zlib(&a, obuffer, olen, 0, 0))
++      return (int) (a.zout - a.zout_start);
++   else
++      return -1;
++}
++#endif
++
++// public domain "baseline" PNG decoder   v0.10  Sean Barrett 2006-11-18
++//    simple implementation
++//      - only 8-bit samples
++//      - no CRC checking
++//      - allocates lots of intermediate memory
++//        - avoids problem of streaming data between subsystems
++//        - avoids explicit window management
++//    performance
++//      - uses stb_zlib, a PD zlib implementation with fast huffman decoding
++
++#ifndef STBI_NO_PNG
++typedef struct
++{
++   stbi__uint32 length;
++   stbi__uint32 type;
++} stbi__pngchunk;
++
++static stbi__pngchunk stbi__get_chunk_header(stbi__context *s)
++{
++   stbi__pngchunk c;
++   c.length = stbi__get32be(s);
++   c.type   = stbi__get32be(s);
++   return c;
++}
++
++static int stbi__check_png_header(stbi__context *s)
++{
++   static const stbi_uc png_sig[8] = { 137,80,78,71,13,10,26,10 };
++   int i;
++   for (i=0; i < 8; ++i)
++      if (stbi__get8(s) != png_sig[i]) return stbi__err("bad png sig","Not a PNG");
++   return 1;
++}
++
++typedef struct
++{
++   stbi__context *s;
++   stbi_uc *idata, *expanded, *out;
++   int depth;
++} stbi__png;
++
++
++enum {
++   STBI__F_none=0,
++   STBI__F_sub=1,
++   STBI__F_up=2,
++   STBI__F_avg=3,
++   STBI__F_paeth=4,
++   // synthetic filters used for first scanline to avoid needing a dummy row of 0s
++   STBI__F_avg_first,
++   STBI__F_paeth_first
++};
++
++static stbi_uc first_row_filter[5] =
++{
++   STBI__F_none,
++   STBI__F_sub,
++   STBI__F_none,
++   STBI__F_avg_first,
++   STBI__F_paeth_first
++};
++
++static int stbi__paeth(int a, int b, int c)
++{
++   int p = a + b - c;
++   int pa = abs(p-a);
++   int pb = abs(p-b);
++   int pc = abs(p-c);
++   if (pa <= pb && pa <= pc) return a;
++   if (pb <= pc) return b;
++   return c;
++}
++
++static const stbi_uc stbi__depth_scale_table[9] = { 0, 0xff, 0x55, 0, 0x11, 0,0,0, 0x01 };
++
++// create the png data from post-deflated data
++static int stbi__create_png_image_raw(stbi__png *a, stbi_uc *raw, stbi__uint32 raw_len, int out_n, stbi__uint32 x, stbi__uint32 y, int depth, int color)
++{
++   int bytes = (depth == 16? 2 : 1);
++   stbi__context *s = a->s;
++   stbi__uint32 i,j,stride = x*out_n*bytes;
++   stbi__uint32 img_len, img_width_bytes;
++   int k;
++   int img_n = s->img_n; // copy it into a local for later
++
++   int output_bytes = out_n*bytes;
++   int filter_bytes = img_n*bytes;
++   int width = x;
++
++   STBI_ASSERT(out_n == s->img_n || out_n == s->img_n+1);
++   a->out = (stbi_uc *) stbi__malloc_mad3(x, y, output_bytes, 0); // extra bytes to write off the end into
++   if (!a->out) return stbi__err("outofmem", "Out of memory");
++
++   if (!stbi__mad3sizes_valid(img_n, x, depth, 7)) return stbi__err("too large", "Corrupt PNG");
++   img_width_bytes = (((img_n * x * depth) + 7) >> 3);
++   img_len = (img_width_bytes + 1) * y;
++
++   // we used to check for exact match between raw_len and img_len on non-interlaced PNGs,
++   // but issue #276 reported a PNG in the wild that had extra data at the end (all zeros),
++   // so just check for raw_len < img_len always.
++   if (raw_len < img_len) return stbi__err("not enough pixels","Corrupt PNG");
++
++   for (j=0; j < y; ++j) {
++      stbi_uc *cur = a->out + stride*j;
++      stbi_uc *prior;
++      int filter = *raw++;
++
++      if (filter > 4)
++         return stbi__err("invalid filter","Corrupt PNG");
++
++      if (depth < 8) {
++         STBI_ASSERT(img_width_bytes <= x);
++         cur += x*out_n - img_width_bytes; // store output to the rightmost img_len bytes, so we can decode in place
++         filter_bytes = 1;
++         width = img_width_bytes;
++      }
++      prior = cur - stride; // bugfix: need to compute this after 'cur +=' computation above
++
++      // if first row, use special filter that doesn't sample previous row
++      if (j == 0) filter = first_row_filter[filter];
++
++      // handle first byte explicitly
++      for (k=0; k < filter_bytes; ++k) {
++         switch (filter) {
++            case STBI__F_none       : cur[k] = raw[k]; break;
++            case STBI__F_sub        : cur[k] = raw[k]; break;
++            case STBI__F_up         : cur[k] = STBI__BYTECAST(raw[k] + prior[k]); break;
++            case STBI__F_avg        : cur[k] = STBI__BYTECAST(raw[k] + (prior[k]>>1)); break;
++            case STBI__F_paeth      : cur[k] = STBI__BYTECAST(raw[k] + stbi__paeth(0,prior[k],0)); break;
++            case STBI__F_avg_first  : cur[k] = raw[k]; break;
++            case STBI__F_paeth_first: cur[k] = raw[k]; break;
++         }
++      }
++
++      if (depth == 8) {
++         if (img_n != out_n)
++            cur[img_n] = 255; // first pixel
++         raw += img_n;
++         cur += out_n;
++         prior += out_n;
++      } else if (depth == 16) {
++         if (img_n != out_n) {
++            cur[filter_bytes]   = 255; // first pixel top byte
++            cur[filter_bytes+1] = 255; // first pixel bottom byte
++         }
++         raw += filter_bytes;
++         cur += output_bytes;
++         prior += output_bytes;
++      } else {
++         raw += 1;
++         cur += 1;
++         prior += 1;
++      }
++
++      // this is a little gross, so that we don't switch per-pixel or per-component
++      if (depth < 8 || img_n == out_n) {
++         int nk = (width - 1)*filter_bytes;
++         #define STBI__CASE(f) \
++             case f:     \
++                for (k=0; k < nk; ++k)
++         switch (filter) {
++            // "none" filter turns into a memcpy here; make that explicit.
++            case STBI__F_none:         memcpy(cur, raw, nk); break;
++            STBI__CASE(STBI__F_sub)          { cur[k] = STBI__BYTECAST(raw[k] + cur[k-filter_bytes]); } break;
++            STBI__CASE(STBI__F_up)           { cur[k] = STBI__BYTECAST(raw[k] + prior[k]); } break;
++            STBI__CASE(STBI__F_avg)          { cur[k] = STBI__BYTECAST(raw[k] + ((prior[k] + cur[k-filter_bytes])>>1)); } break;
++            STBI__CASE(STBI__F_paeth)        { cur[k] = STBI__BYTECAST(raw[k] + stbi__paeth(cur[k-filter_bytes],prior[k],prior[k-filter_bytes])); } break;
++            STBI__CASE(STBI__F_avg_first)    { cur[k] = STBI__BYTECAST(raw[k] + (cur[k-filter_bytes] >> 1)); } break;
++            STBI__CASE(STBI__F_paeth_first)  { cur[k] = STBI__BYTECAST(raw[k] + stbi__paeth(cur[k-filter_bytes],0,0)); } break;
++         }
++         #undef STBI__CASE
++         raw += nk;
++      } else {
++         STBI_ASSERT(img_n+1 == out_n);
++         #define STBI__CASE(f) \
++             case f:     \
++                for (i=x-1; i >= 1; --i, cur[filter_bytes]=255,raw+=filter_bytes,cur+=output_bytes,prior+=output_bytes) \
++                   for (k=0; k < filter_bytes; ++k)
++         switch (filter) {
++            STBI__CASE(STBI__F_none)         { cur[k] = raw[k]; } break;
++            STBI__CASE(STBI__F_sub)          { cur[k] = STBI__BYTECAST(raw[k] + cur[k- output_bytes]); } break;
++            STBI__CASE(STBI__F_up)           { cur[k] = STBI__BYTECAST(raw[k] + prior[k]); } break;
++            STBI__CASE(STBI__F_avg)          { cur[k] = STBI__BYTECAST(raw[k] + ((prior[k] + cur[k- output_bytes])>>1)); } break;
++            STBI__CASE(STBI__F_paeth)        { cur[k] = STBI__BYTECAST(raw[k] + stbi__paeth(cur[k- output_bytes],prior[k],prior[k- output_bytes])); } break;
++            STBI__CASE(STBI__F_avg_first)    { cur[k] = STBI__BYTECAST(raw[k] + (cur[k- output_bytes] >> 1)); } break;
++            STBI__CASE(STBI__F_paeth_first)  { cur[k] = STBI__BYTECAST(raw[k] + stbi__paeth(cur[k- output_bytes],0,0)); } break;
++         }
++         #undef STBI__CASE
++
++         // the loop above sets the high byte of the pixels' alpha, but for
++         // 16 bit png files we also need the low byte set. we'll do that here.
++         if (depth == 16) {
++            cur = a->out + stride*j; // start at the beginning of the row again
++            for (i=0; i < x; ++i,cur+=output_bytes) {
++               cur[filter_bytes+1] = 255;
++            }
++         }
++      }
++   }
++
++   // we make a separate pass to expand bits to pixels; for performance,
++   // this could run two scanlines behind the above code, so it won't
++   // intefere with filtering but will still be in the cache.
++   if (depth < 8) {
++      for (j=0; j < y; ++j) {
++         stbi_uc *cur = a->out + stride*j;
++         stbi_uc *in  = a->out + stride*j + x*out_n - img_width_bytes;
++         // unpack 1/2/4-bit into a 8-bit buffer. allows us to keep the common 8-bit path optimal at minimal cost for 1/2/4-bit
++         // png guarante byte alignment, if width is not multiple of 8/4/2 we'll decode dummy trailing data that will be skipped in the later loop
++         stbi_uc scale = (color == 0) ? stbi__depth_scale_table[depth] : 1; // scale grayscale values to 0..255 range
++
++         // note that the final byte might overshoot and write more data than desired.
++         // we can allocate enough data that this never writes out of memory, but it
++         // could also overwrite the next scanline. can it overwrite non-empty data
++         // on the next scanline? yes, consider 1-pixel-wide scanlines with 1-bit-per-pixel.
++         // so we need to explicitly clamp the final ones
++
++         if (depth == 4) {
++            for (k=x*img_n; k >= 2; k-=2, ++in) {
++               *cur++ = scale * ((*in >> 4)       );
++               *cur++ = scale * ((*in     ) & 0x0f);
++            }
++            if (k > 0) *cur++ = scale * ((*in >> 4)       );
++         } else if (depth == 2) {
++            for (k=x*img_n; k >= 4; k-=4, ++in) {
++               *cur++ = scale * ((*in >> 6)       );
++               *cur++ = scale * ((*in >> 4) & 0x03);
++               *cur++ = scale * ((*in >> 2) & 0x03);
++               *cur++ = scale * ((*in     ) & 0x03);
++            }
++            if (k > 0) *cur++ = scale * ((*in >> 6)       );
++            if (k > 1) *cur++ = scale * ((*in >> 4) & 0x03);
++            if (k > 2) *cur++ = scale * ((*in >> 2) & 0x03);
++         } else if (depth == 1) {
++            for (k=x*img_n; k >= 8; k-=8, ++in) {
++               *cur++ = scale * ((*in >> 7)       );
++               *cur++ = scale * ((*in >> 6) & 0x01);
++               *cur++ = scale * ((*in >> 5) & 0x01);
++               *cur++ = scale * ((*in >> 4) & 0x01);
++               *cur++ = scale * ((*in >> 3) & 0x01);
++               *cur++ = scale * ((*in >> 2) & 0x01);
++               *cur++ = scale * ((*in >> 1) & 0x01);
++               *cur++ = scale * ((*in     ) & 0x01);
++            }
++            if (k > 0) *cur++ = scale * ((*in >> 7)       );
++            if (k > 1) *cur++ = scale * ((*in >> 6) & 0x01);
++            if (k > 2) *cur++ = scale * ((*in >> 5) & 0x01);
++            if (k > 3) *cur++ = scale * ((*in >> 4) & 0x01);
++            if (k > 4) *cur++ = scale * ((*in >> 3) & 0x01);
++            if (k > 5) *cur++ = scale * ((*in >> 2) & 0x01);
++            if (k > 6) *cur++ = scale * ((*in >> 1) & 0x01);
++         }
++         if (img_n != out_n) {
++            int q;
++            // insert alpha = 255
++            cur = a->out + stride*j;
++            if (img_n == 1) {
++               for (q=x-1; q >= 0; --q) {
++                  cur[q*2+1] = 255;
++                  cur[q*2+0] = cur[q];
++               }
++            } else {
++               STBI_ASSERT(img_n == 3);
++               for (q=x-1; q >= 0; --q) {
++                  cur[q*4+3] = 255;
++                  cur[q*4+2] = cur[q*3+2];
++                  cur[q*4+1] = cur[q*3+1];
++                  cur[q*4+0] = cur[q*3+0];
++               }
++            }
++         }
++      }
++   } else if (depth == 16) {
++      // force the image data from big-endian to platform-native.
++      // this is done in a separate pass due to the decoding relying
++      // on the data being untouched, but could probably be done
++      // per-line during decode if care is taken.
++      stbi_uc *cur = a->out;
++      stbi__uint16 *cur16 = (stbi__uint16*)cur;
++
++      for(i=0; i < x*y*out_n; ++i,cur16++,cur+=2) {
++         *cur16 = (cur[0] << 8) | cur[1];
++      }
++   }
++
++   return 1;
++}
++
++static int stbi__create_png_image(stbi__png *a, stbi_uc *image_data, stbi__uint32 image_data_len, int out_n, int depth, int color, int interlaced)
++{
++   int bytes = (depth == 16 ? 2 : 1);
++   int out_bytes = out_n * bytes;
++   stbi_uc *final;
++   int p;
++   if (!interlaced)
++      return stbi__create_png_image_raw(a, image_data, image_data_len, out_n, a->s->img_x, a->s->img_y, depth, color);
++
++   // de-interlacing
++   final = (stbi_uc *) stbi__malloc_mad3(a->s->img_x, a->s->img_y, out_bytes, 0);
++   for (p=0; p < 7; ++p) {
++      int xorig[] = { 0,4,0,2,0,1,0 };
++      int yorig[] = { 0,0,4,0,2,0,1 };
++      int xspc[]  = { 8,8,4,4,2,2,1 };
++      int yspc[]  = { 8,8,8,4,4,2,2 };
++      int i,j,x,y;
++      // pass1_x[4] = 0, pass1_x[5] = 1, pass1_x[12] = 1
++      x = (a->s->img_x - xorig[p] + xspc[p]-1) / xspc[p];
++      y = (a->s->img_y - yorig[p] + yspc[p]-1) / yspc[p];
++      if (x && y) {
++         stbi__uint32 img_len = ((((a->s->img_n * x * depth) + 7) >> 3) + 1) * y;
++         if (!stbi__create_png_image_raw(a, image_data, image_data_len, out_n, x, y, depth, color)) {
++            STBI_FREE(final);
++            return 0;
++         }
++         for (j=0; j < y; ++j) {
++            for (i=0; i < x; ++i) {
++               int out_y = j*yspc[p]+yorig[p];
++               int out_x = i*xspc[p]+xorig[p];
++               memcpy(final + out_y*a->s->img_x*out_bytes + out_x*out_bytes,
++                      a->out + (j*x+i)*out_bytes, out_bytes);
++            }
++         }
++         STBI_FREE(a->out);
++         image_data += img_len;
++         image_data_len -= img_len;
++      }
++   }
++   a->out = final;
++
++   return 1;
++}
++
++static int stbi__compute_transparency(stbi__png *z, stbi_uc tc[3], int out_n)
++{
++   stbi__context *s = z->s;
++   stbi__uint32 i, pixel_count = s->img_x * s->img_y;
++   stbi_uc *p = z->out;
++
++   // compute color-based transparency, assuming we've
++   // already got 255 as the alpha value in the output
++   STBI_ASSERT(out_n == 2 || out_n == 4);
++
++   if (out_n == 2) {
++      for (i=0; i < pixel_count; ++i) {
++         p[1] = (p[0] == tc[0] ? 0 : 255);
++         p += 2;
++      }
++   } else {
++      for (i=0; i < pixel_count; ++i) {
++         if (p[0] == tc[0] && p[1] == tc[1] && p[2] == tc[2])
++            p[3] = 0;
++         p += 4;
++      }
++   }
++   return 1;
++}
++
++static int stbi__compute_transparency16(stbi__png *z, stbi__uint16 tc[3], int out_n)
++{
++   stbi__context *s = z->s;
++   stbi__uint32 i, pixel_count = s->img_x * s->img_y;
++   stbi__uint16 *p = (stbi__uint16*) z->out;
++
++   // compute color-based transparency, assuming we've
++   // already got 65535 as the alpha value in the output
++   STBI_ASSERT(out_n == 2 || out_n == 4);
++
++   if (out_n == 2) {
++      for (i = 0; i < pixel_count; ++i) {
++         p[1] = (p[0] == tc[0] ? 0 : 65535);
++         p += 2;
++      }
++   } else {
++      for (i = 0; i < pixel_count; ++i) {
++         if (p[0] == tc[0] && p[1] == tc[1] && p[2] == tc[2])
++            p[3] = 0;
++         p += 4;
++      }
++   }
++   return 1;
++}
++
++static int stbi__expand_png_palette(stbi__png *a, stbi_uc *palette, int len, int pal_img_n)
++{
++   stbi__uint32 i, pixel_count = a->s->img_x * a->s->img_y;
++   stbi_uc *p, *temp_out, *orig = a->out;
++
++   p = (stbi_uc *) stbi__malloc_mad2(pixel_count, pal_img_n, 0);
++   if (p == NULL) return stbi__err("outofmem", "Out of memory");
++
++   // between here and free(out) below, exitting would leak
++   temp_out = p;
++
++   if (pal_img_n == 3) {
++      for (i=0; i < pixel_count; ++i) {
++         int n = orig[i]*4;
++         p[0] = palette[n  ];
++         p[1] = palette[n+1];
++         p[2] = palette[n+2];
++         p += 3;
++      }
++   } else {
++      for (i=0; i < pixel_count; ++i) {
++         int n = orig[i]*4;
++         p[0] = palette[n  ];
++         p[1] = palette[n+1];
++         p[2] = palette[n+2];
++         p[3] = palette[n+3];
++         p += 4;
++      }
++   }
++   STBI_FREE(a->out);
++   a->out = temp_out;
++
++   STBI_NOTUSED(len);
++
++   return 1;
++}
++
++static int stbi__unpremultiply_on_load = 0;
++static int stbi__de_iphone_flag = 0;
++
++STBIDEF void stbi_set_unpremultiply_on_load(int flag_true_if_should_unpremultiply)
++{
++   stbi__unpremultiply_on_load = flag_true_if_should_unpremultiply;
++}
++
++STBIDEF void stbi_convert_iphone_png_to_rgb(int flag_true_if_should_convert)
++{
++   stbi__de_iphone_flag = flag_true_if_should_convert;
++}
++
++static void stbi__de_iphone(stbi__png *z)
++{
++   stbi__context *s = z->s;
++   stbi__uint32 i, pixel_count = s->img_x * s->img_y;
++   stbi_uc *p = z->out;
++
++   if (s->img_out_n == 3) {  // convert bgr to rgb
++      for (i=0; i < pixel_count; ++i) {
++         stbi_uc t = p[0];
++         p[0] = p[2];
++         p[2] = t;
++         p += 3;
++      }
++   } else {
++      STBI_ASSERT(s->img_out_n == 4);
++      if (stbi__unpremultiply_on_load) {
++         // convert bgr to rgb and unpremultiply
++         for (i=0; i < pixel_count; ++i) {
++            stbi_uc a = p[3];
++            stbi_uc t = p[0];
++            if (a) {
++               stbi_uc half = a / 2;
++               p[0] = (p[2] * 255 + half) / a;
++               p[1] = (p[1] * 255 + half) / a;
++               p[2] = ( t   * 255 + half) / a;
++            } else {
++               p[0] = p[2];
++               p[2] = t;
++            }
++            p += 4;
++         }
++      } else {
++         // convert bgr to rgb
++         for (i=0; i < pixel_count; ++i) {
++            stbi_uc t = p[0];
++            p[0] = p[2];
++            p[2] = t;
++            p += 4;
++         }
++      }
++   }
++}
++
++#define STBI__PNG_TYPE(a,b,c,d)  (((unsigned) (a) << 24) + ((unsigned) (b) << 16) + ((unsigned) (c) << 8) + (unsigned) (d))
++
++static int stbi__parse_png_file(stbi__png *z, int scan, int req_comp)
++{
++   stbi_uc palette[1024], pal_img_n=0;
++   stbi_uc has_trans=0, tc[3];
++   stbi__uint16 tc16[3];
++   stbi__uint32 ioff=0, idata_limit=0, i, pal_len=0;
++   int first=1,k,interlace=0, color=0, is_iphone=0;
++   stbi__context *s = z->s;
++
++   z->expanded = NULL;
++   z->idata = NULL;
++   z->out = NULL;
++
++   if (!stbi__check_png_header(s)) return 0;
++
++   if (scan == STBI__SCAN_type) return 1;
++
++   for (;;) {
++      stbi__pngchunk c = stbi__get_chunk_header(s);
++      switch (c.type) {
++         case STBI__PNG_TYPE('C','g','B','I'):
++            is_iphone = 1;
++            stbi__skip(s, c.length);
++            break;
++         case STBI__PNG_TYPE('I','H','D','R'): {
++            int comp,filter;
++            if (!first) return stbi__err("multiple IHDR","Corrupt PNG");
++            first = 0;
++            if (c.length != 13) return stbi__err("bad IHDR len","Corrupt PNG");
++            s->img_x = stbi__get32be(s); if (s->img_x > (1 << 24)) return stbi__err("too large","Very large image (corrupt?)");
++            s->img_y = stbi__get32be(s); if (s->img_y > (1 << 24)) return stbi__err("too large","Very large image (corrupt?)");
++            z->depth = stbi__get8(s);  if (z->depth != 1 && z->depth != 2 && z->depth != 4 && z->depth != 8 && z->depth != 16)  return stbi__err("1/2/4/8/16-bit only","PNG not supported: 1/2/4/8/16-bit only");
++            color = stbi__get8(s);  if (color > 6)         return stbi__err("bad ctype","Corrupt PNG");
++            if (color == 3 && z->depth == 16)                  return stbi__err("bad ctype","Corrupt PNG");
++            if (color == 3) pal_img_n = 3; else if (color & 1) return stbi__err("bad ctype","Corrupt PNG");
++            comp  = stbi__get8(s);  if (comp) return stbi__err("bad comp method","Corrupt PNG");
++            filter= stbi__get8(s);  if (filter) return stbi__err("bad filter method","Corrupt PNG");
++            interlace = stbi__get8(s); if (interlace>1) return stbi__err("bad interlace method","Corrupt PNG");
++            if (!s->img_x || !s->img_y) return stbi__err("0-pixel image","Corrupt PNG");
++            if (!pal_img_n) {
++               s->img_n = (color & 2 ? 3 : 1) + (color & 4 ? 1 : 0);
++               if ((1 << 30) / s->img_x / s->img_n < s->img_y) return stbi__err("too large", "Image too large to decode");
++               if (scan == STBI__SCAN_header) return 1;
++            } else {
++               // if paletted, then pal_n is our final components, and
++               // img_n is # components to decompress/filter.
++               s->img_n = 1;
++               if ((1 << 30) / s->img_x / 4 < s->img_y) return stbi__err("too large","Corrupt PNG");
++               // if SCAN_header, have to scan to see if we have a tRNS
++            }
++            break;
++         }
++
++         case STBI__PNG_TYPE('P','L','T','E'):  {
++            if (first) return stbi__err("first not IHDR", "Corrupt PNG");
++            if (c.length > 256*3) return stbi__err("invalid PLTE","Corrupt PNG");
++            pal_len = c.length / 3;
++            if (pal_len * 3 != c.length) return stbi__err("invalid PLTE","Corrupt PNG");
++            for (i=0; i < pal_len; ++i) {
++               palette[i*4+0] = stbi__get8(s);
++               palette[i*4+1] = stbi__get8(s);
++               palette[i*4+2] = stbi__get8(s);
++               palette[i*4+3] = 255;
++            }
++            break;
++         }
++
++         case STBI__PNG_TYPE('t','R','N','S'): {
++            if (first) return stbi__err("first not IHDR", "Corrupt PNG");
++            if (z->idata) return stbi__err("tRNS after IDAT","Corrupt PNG");
++            if (pal_img_n) {
++               if (scan == STBI__SCAN_header) { s->img_n = 4; return 1; }
++               if (pal_len == 0) return stbi__err("tRNS before PLTE","Corrupt PNG");
++               if (c.length > pal_len) return stbi__err("bad tRNS len","Corrupt PNG");
++               pal_img_n = 4;
++               for (i=0; i < c.length; ++i)
++                  palette[i*4+3] = stbi__get8(s);
++            } else {
++               if (!(s->img_n & 1)) return stbi__err("tRNS with alpha","Corrupt PNG");
++               if (c.length != (stbi__uint32) s->img_n*2) return stbi__err("bad tRNS len","Corrupt PNG");
++               has_trans = 1;
++               if (z->depth == 16) {
++                  for (k = 0; k < s->img_n; ++k) tc16[k] = (stbi__uint16)stbi__get16be(s); // copy the values as-is
++               } else {
++                  for (k = 0; k < s->img_n; ++k) tc[k] = (stbi_uc)(stbi__get16be(s) & 255) * stbi__depth_scale_table[z->depth]; // non 8-bit images will be larger
++               }
++            }
++            break;
++         }
++
++         case STBI__PNG_TYPE('I','D','A','T'): {
++            if (first) return stbi__err("first not IHDR", "Corrupt PNG");
++            if (pal_img_n && !pal_len) return stbi__err("no PLTE","Corrupt PNG");
++            if (scan == STBI__SCAN_header) { s->img_n = pal_img_n; return 1; }
++            if ((int)(ioff + c.length) < (int)ioff) return 0;
++            if (ioff + c.length > idata_limit) {
++               stbi__uint32 idata_limit_old = idata_limit;
++               stbi_uc *p;
++               if (idata_limit == 0) idata_limit = c.length > 4096 ? c.length : 4096;
++               while (ioff + c.length > idata_limit)
++                  idata_limit *= 2;
++               STBI_NOTUSED(idata_limit_old);
++               p = (stbi_uc *) STBI_REALLOC_SIZED(z->idata, idata_limit_old, idata_limit); if (p == NULL) return stbi__err("outofmem", "Out of memory");
++               z->idata = p;
++            }
++            if (!stbi__getn(s, z->idata+ioff,c.length)) return stbi__err("outofdata","Corrupt PNG");
++            ioff += c.length;
++            break;
++         }
++
++         case STBI__PNG_TYPE('I','E','N','D'): {
++            stbi__uint32 raw_len, bpl;
++            if (first) return stbi__err("first not IHDR", "Corrupt PNG");
++            if (scan != STBI__SCAN_load) return 1;
++            if (z->idata == NULL) return stbi__err("no IDAT","Corrupt PNG");
++            // initial guess for decoded data size to avoid unnecessary reallocs
++            bpl = (s->img_x * z->depth + 7) / 8; // bytes per line, per component
++            raw_len = bpl * s->img_y * s->img_n /* pixels */ + s->img_y /* filter mode per row */;
++            z->expanded = (stbi_uc *) stbi_zlib_decode_malloc_guesssize_headerflag((char *) z->idata, ioff, raw_len, (int *) &raw_len, !is_iphone);
++            if (z->expanded == NULL) return 0; // zlib should set error
++            STBI_FREE(z->idata); z->idata = NULL;
++            if ((req_comp == s->img_n+1 && req_comp != 3 && !pal_img_n) || has_trans)
++               s->img_out_n = s->img_n+1;
++            else
++               s->img_out_n = s->img_n;
++            if (!stbi__create_png_image(z, z->expanded, raw_len, s->img_out_n, z->depth, color, interlace)) return 0;
++            if (has_trans) {
++               if (z->depth == 16) {
++                  if (!stbi__compute_transparency16(z, tc16, s->img_out_n)) return 0;
++               } else {
++                  if (!stbi__compute_transparency(z, tc, s->img_out_n)) return 0;
++               }
++            }
++            if (is_iphone && stbi__de_iphone_flag && s->img_out_n > 2)
++               stbi__de_iphone(z);
++            if (pal_img_n) {
++               // pal_img_n == 3 or 4
++               s->img_n = pal_img_n; // record the actual colors we had
++               s->img_out_n = pal_img_n;
++               if (req_comp >= 3) s->img_out_n = req_comp;
++               if (!stbi__expand_png_palette(z, palette, pal_len, s->img_out_n))
++                  return 0;
++            } else if (has_trans) {
++               // non-paletted image with tRNS -> source image has (constant) alpha
++               ++s->img_n;
++            }
++            STBI_FREE(z->expanded); z->expanded = NULL;
++            return 1;
++         }
++
++         default:
++            // if critical, fail
++            if (first) return stbi__err("first not IHDR", "Corrupt PNG");
++            if ((c.type & (1 << 29)) == 0) {
++               #ifndef STBI_NO_FAILURE_STRINGS
++               // not threadsafe
++               static char invalid_chunk[] = "XXXX PNG chunk not known";
++               invalid_chunk[0] = STBI__BYTECAST(c.type >> 24);
++               invalid_chunk[1] = STBI__BYTECAST(c.type >> 16);
++               invalid_chunk[2] = STBI__BYTECAST(c.type >>  8);
++               invalid_chunk[3] = STBI__BYTECAST(c.type >>  0);
++               #endif
++               return stbi__err(invalid_chunk, "PNG not supported: unknown PNG chunk type");
++            }
++            stbi__skip(s, c.length);
++            break;
++      }
++      // end of PNG chunk, read and skip CRC
++      stbi__get32be(s);
++   }
++}
++
++static void *stbi__do_png(stbi__png *p, int *x, int *y, int *n, int req_comp, stbi__result_info *ri)
++{
++   void *result=NULL;
++   if (req_comp < 0 || req_comp > 4) return stbi__errpuc("bad req_comp", "Internal error");
++   if (stbi__parse_png_file(p, STBI__SCAN_load, req_comp)) {
++      if (p->depth < 8)
++         ri->bits_per_channel = 8;
++      else
++         ri->bits_per_channel = p->depth;
++      result = p->out;
++      p->out = NULL;
++      if (req_comp && req_comp != p->s->img_out_n) {
++         if (ri->bits_per_channel == 8)
++            result = stbi__convert_format((unsigned char *) result, p->s->img_out_n, req_comp, p->s->img_x, p->s->img_y);
++         else
++            result = stbi__convert_format16((stbi__uint16 *) result, p->s->img_out_n, req_comp, p->s->img_x, p->s->img_y);
++         p->s->img_out_n = req_comp;
++         if (result == NULL) return result;
++      }
++      *x = p->s->img_x;
++      *y = p->s->img_y;
++      if (n) *n = p->s->img_n;
++   }
++   STBI_FREE(p->out);      p->out      = NULL;
++   STBI_FREE(p->expanded); p->expanded = NULL;
++   STBI_FREE(p->idata);    p->idata    = NULL;
++
++   return result;
++}
++
++static void *stbi__png_load(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri)
++{
++   stbi__png p;
++   p.s = s;
++   return stbi__do_png(&p, x,y,comp,req_comp, ri);
++}
++
++static int stbi__png_test(stbi__context *s)
++{
++   int r;
++   r = stbi__check_png_header(s);
++   stbi__rewind(s);
++   return r;
++}
++
++static int stbi__png_info_raw(stbi__png *p, int *x, int *y, int *comp)
++{
++   if (!stbi__parse_png_file(p, STBI__SCAN_header, 0)) {
++      stbi__rewind( p->s );
++      return 0;
++   }
++   if (x) *x = p->s->img_x;
++   if (y) *y = p->s->img_y;
++   if (comp) *comp = p->s->img_n;
++   return 1;
++}
++
++static int stbi__png_info(stbi__context *s, int *x, int *y, int *comp)
++{
++   stbi__png p;
++   p.s = s;
++   return stbi__png_info_raw(&p, x, y, comp);
++}
++
++static int stbi__png_is16(stbi__context *s)
++{
++   stbi__png p;
++   p.s = s;
++   if (!stbi__png_info_raw(&p, NULL, NULL, NULL))
++	   return 0;
++   if (p.depth != 16) {
++      stbi__rewind(p.s);
++      return 0;
++   }
++   return 1;
++}
++#endif
++
++// Microsoft/Windows BMP image
++
++#ifndef STBI_NO_BMP
++static int stbi__bmp_test_raw(stbi__context *s)
++{
++   int r;
++   int sz;
++   if (stbi__get8(s) != 'B') return 0;
++   if (stbi__get8(s) != 'M') return 0;
++   stbi__get32le(s); // discard filesize
++   stbi__get16le(s); // discard reserved
++   stbi__get16le(s); // discard reserved
++   stbi__get32le(s); // discard data offset
++   sz = stbi__get32le(s);
++   r = (sz == 12 || sz == 40 || sz == 56 || sz == 108 || sz == 124);
++   return r;
++}
++
++static int stbi__bmp_test(stbi__context *s)
++{
++   int r = stbi__bmp_test_raw(s);
++   stbi__rewind(s);
++   return r;
++}
++
++
++// returns 0..31 for the highest set bit
++static int stbi__high_bit(unsigned int z)
++{
++   int n=0;
++   if (z == 0) return -1;
++   if (z >= 0x10000) n += 16, z >>= 16;
++   if (z >= 0x00100) n +=  8, z >>=  8;
++   if (z >= 0x00010) n +=  4, z >>=  4;
++   if (z >= 0x00004) n +=  2, z >>=  2;
++   if (z >= 0x00002) n +=  1, z >>=  1;
++   return n;
++}
++
++static int stbi__bitcount(unsigned int a)
++{
++   a = (a & 0x55555555) + ((a >>  1) & 0x55555555); // max 2
++   a = (a & 0x33333333) + ((a >>  2) & 0x33333333); // max 4
++   a = (a + (a >> 4)) & 0x0f0f0f0f; // max 8 per 4, now 8 bits
++   a = (a + (a >> 8)); // max 16 per 8 bits
++   a = (a + (a >> 16)); // max 32 per 8 bits
++   return a & 0xff;
++}
++
++// extract an arbitrarily-aligned N-bit value (N=bits)
++// from v, and then make it 8-bits long and fractionally
++// extend it to full full range.
++static int stbi__shiftsigned(unsigned int v, int shift, int bits)
++{
++   static unsigned int mul_table[9] = {
++      0,
++      0xff/*0b11111111*/, 0x55/*0b01010101*/, 0x49/*0b01001001*/, 0x11/*0b00010001*/,
++      0x21/*0b00100001*/, 0x41/*0b01000001*/, 0x81/*0b10000001*/, 0x01/*0b00000001*/,
++   };
++   static unsigned int shift_table[9] = {
++      0, 0,0,1,0,2,4,6,0,
++   };
++   if (shift < 0)
++      v <<= -shift;
++   else
++      v >>= shift;
++   STBI_ASSERT(v >= 0 && v < 256);
++   v >>= (8-bits);
++   STBI_ASSERT(bits >= 0 && bits <= 8);
++   return (int) ((unsigned) v * mul_table[bits]) >> shift_table[bits];
++}
++
++typedef struct
++{
++   int bpp, offset, hsz;
++   unsigned int mr,mg,mb,ma, all_a;
++} stbi__bmp_data;
++
++static void *stbi__bmp_parse_header(stbi__context *s, stbi__bmp_data *info)
++{
++   int hsz;
++   if (stbi__get8(s) != 'B' || stbi__get8(s) != 'M') return stbi__errpuc("not BMP", "Corrupt BMP");
++   stbi__get32le(s); // discard filesize
++   stbi__get16le(s); // discard reserved
++   stbi__get16le(s); // discard reserved
++   info->offset = stbi__get32le(s);
++   info->hsz = hsz = stbi__get32le(s);
++   info->mr = info->mg = info->mb = info->ma = 0;
++
++   if (hsz != 12 && hsz != 40 && hsz != 56 && hsz != 108 && hsz != 124) return stbi__errpuc("unknown BMP", "BMP type not supported: unknown");
++   if (hsz == 12) {
++      s->img_x = stbi__get16le(s);
++      s->img_y = stbi__get16le(s);
++   } else {
++      s->img_x = stbi__get32le(s);
++      s->img_y = stbi__get32le(s);
++   }
++   if (stbi__get16le(s) != 1) return stbi__errpuc("bad BMP", "bad BMP");
++   info->bpp = stbi__get16le(s);
++   if (hsz != 12) {
++      int compress = stbi__get32le(s);
++      if (compress == 1 || compress == 2) return stbi__errpuc("BMP RLE", "BMP type not supported: RLE");
++      stbi__get32le(s); // discard sizeof
++      stbi__get32le(s); // discard hres
++      stbi__get32le(s); // discard vres
++      stbi__get32le(s); // discard colorsused
++      stbi__get32le(s); // discard max important
++      if (hsz == 40 || hsz == 56) {
++         if (hsz == 56) {
++            stbi__get32le(s);
++            stbi__get32le(s);
++            stbi__get32le(s);
++            stbi__get32le(s);
++         }
++         if (info->bpp == 16 || info->bpp == 32) {
++            if (compress == 0) {
++               if (info->bpp == 32) {
++                  info->mr = 0xffu << 16;
++                  info->mg = 0xffu <<  8;
++                  info->mb = 0xffu <<  0;
++                  info->ma = 0xffu << 24;
++                  info->all_a = 0; // if all_a is 0 at end, then we loaded alpha channel but it was all 0
++               } else {
++                  info->mr = 31u << 10;
++                  info->mg = 31u <<  5;
++                  info->mb = 31u <<  0;
++               }
++            } else if (compress == 3) {
++               info->mr = stbi__get32le(s);
++               info->mg = stbi__get32le(s);
++               info->mb = stbi__get32le(s);
++               // not documented, but generated by photoshop and handled by mspaint
++               if (info->mr == info->mg && info->mg == info->mb) {
++                  // ?!?!?
++                  return stbi__errpuc("bad BMP", "bad BMP");
++               }
++            } else
++               return stbi__errpuc("bad BMP", "bad BMP");
++         }
++      } else {
++         int i;
++         if (hsz != 108 && hsz != 124)
++            return stbi__errpuc("bad BMP", "bad BMP");
++         info->mr = stbi__get32le(s);
++         info->mg = stbi__get32le(s);
++         info->mb = stbi__get32le(s);
++         info->ma = stbi__get32le(s);
++         stbi__get32le(s); // discard color space
++         for (i=0; i < 12; ++i)
++            stbi__get32le(s); // discard color space parameters
++         if (hsz == 124) {
++            stbi__get32le(s); // discard rendering intent
++            stbi__get32le(s); // discard offset of profile data
++            stbi__get32le(s); // discard size of profile data
++            stbi__get32le(s); // discard reserved
++         }
++      }
++   }
++   return (void *) 1;
++}
++
++
++static void *stbi__bmp_load(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri)
++{
++   stbi_uc *out;
++   unsigned int mr=0,mg=0,mb=0,ma=0, all_a;
++   stbi_uc pal[256][4];
++   int psize=0,i,j,width;
++   int flip_vertically, pad, target;
++   stbi__bmp_data info;
++   STBI_NOTUSED(ri);
++
++   info.all_a = 255;
++   if (stbi__bmp_parse_header(s, &info) == NULL)
++      return NULL; // error code already set
++
++   flip_vertically = ((int) s->img_y) > 0;
++   s->img_y = abs((int) s->img_y);
++
++   mr = info.mr;
++   mg = info.mg;
++   mb = info.mb;
++   ma = info.ma;
++   all_a = info.all_a;
++
++   if (info.hsz == 12) {
++      if (info.bpp < 24)
++         psize = (info.offset - 14 - 24) / 3;
++   } else {
++      if (info.bpp < 16)
++         psize = (info.offset - 14 - info.hsz) >> 2;
++   }
++
++   s->img_n = ma ? 4 : 3;
++   if (req_comp && req_comp >= 3) // we can directly decode 3 or 4
++      target = req_comp;
++   else
++      target = s->img_n; // if they want monochrome, we'll post-convert
++
++   // sanity-check size
++   if (!stbi__mad3sizes_valid(target, s->img_x, s->img_y, 0))
++      return stbi__errpuc("too large", "Corrupt BMP");
++
++   out = (stbi_uc *) stbi__malloc_mad3(target, s->img_x, s->img_y, 0);
++   if (!out) return stbi__errpuc("outofmem", "Out of memory");
++   if (info.bpp < 16) {
++      int z=0;
++      if (psize == 0 || psize > 256) { STBI_FREE(out); return stbi__errpuc("invalid", "Corrupt BMP"); }
++      for (i=0; i < psize; ++i) {
++         pal[i][2] = stbi__get8(s);
++         pal[i][1] = stbi__get8(s);
++         pal[i][0] = stbi__get8(s);
++         if (info.hsz != 12) stbi__get8(s);
++         pal[i][3] = 255;
++      }
++      stbi__skip(s, info.offset - 14 - info.hsz - psize * (info.hsz == 12 ? 3 : 4));
++      if (info.bpp == 1) width = (s->img_x + 7) >> 3;
++      else if (info.bpp == 4) width = (s->img_x + 1) >> 1;
++      else if (info.bpp == 8) width = s->img_x;
++      else { STBI_FREE(out); return stbi__errpuc("bad bpp", "Corrupt BMP"); }
++      pad = (-width)&3;
++      if (info.bpp == 1) {
++         for (j=0; j < (int) s->img_y; ++j) {
++            int bit_offset = 7, v = stbi__get8(s);
++            for (i=0; i < (int) s->img_x; ++i) {
++               int color = (v>>bit_offset)&0x1;
++               out[z++] = pal[color][0];
++               out[z++] = pal[color][1];
++               out[z++] = pal[color][2];
++               if((--bit_offset) < 0) {
++                  bit_offset = 7;
++                  v = stbi__get8(s);
++               }
++            }
++            stbi__skip(s, pad);
++         }
++      } else {
++         for (j=0; j < (int) s->img_y; ++j) {
++            for (i=0; i < (int) s->img_x; i += 2) {
++               int v=stbi__get8(s),v2=0;
++               if (info.bpp == 4) {
++                  v2 = v & 15;
++                  v >>= 4;
++               }
++               out[z++] = pal[v][0];
++               out[z++] = pal[v][1];
++               out[z++] = pal[v][2];
++               if (target == 4) out[z++] = 255;
++               if (i+1 == (int) s->img_x) break;
++               v = (info.bpp == 8) ? stbi__get8(s) : v2;
++               out[z++] = pal[v][0];
++               out[z++] = pal[v][1];
++               out[z++] = pal[v][2];
++               if (target == 4) out[z++] = 255;
++            }
++            stbi__skip(s, pad);
++         }
++      }
++   } else {
++      int rshift=0,gshift=0,bshift=0,ashift=0,rcount=0,gcount=0,bcount=0,acount=0;
++      int z = 0;
++      int easy=0;
++      stbi__skip(s, info.offset - 14 - info.hsz);
++      if (info.bpp == 24) width = 3 * s->img_x;
++      else if (info.bpp == 16) width = 2*s->img_x;
++      else /* bpp = 32 and pad = 0 */ width=0;
++      pad = (-width) & 3;
++      if (info.bpp == 24) {
++         easy = 1;
++      } else if (info.bpp == 32) {
++         if (mb == 0xff && mg == 0xff00 && mr == 0x00ff0000 && ma == 0xff000000)
++            easy = 2;
++      }
++      if (!easy) {
++         if (!mr || !mg || !mb) { STBI_FREE(out); return stbi__errpuc("bad masks", "Corrupt BMP"); }
++         // right shift amt to put high bit in position #7
++         rshift = stbi__high_bit(mr)-7; rcount = stbi__bitcount(mr);
++         gshift = stbi__high_bit(mg)-7; gcount = stbi__bitcount(mg);
++         bshift = stbi__high_bit(mb)-7; bcount = stbi__bitcount(mb);
++         ashift = stbi__high_bit(ma)-7; acount = stbi__bitcount(ma);
++      }
++      for (j=0; j < (int) s->img_y; ++j) {
++         if (easy) {
++            for (i=0; i < (int) s->img_x; ++i) {
++               unsigned char a;
++               out[z+2] = stbi__get8(s);
++               out[z+1] = stbi__get8(s);
++               out[z+0] = stbi__get8(s);
++               z += 3;
++               a = (easy == 2 ? stbi__get8(s) : 255);
++               all_a |= a;
++               if (target == 4) out[z++] = a;
++            }
++         } else {
++            int bpp = info.bpp;
++            for (i=0; i < (int) s->img_x; ++i) {
++               stbi__uint32 v = (bpp == 16 ? (stbi__uint32) stbi__get16le(s) : stbi__get32le(s));
++               unsigned int a;
++               out[z++] = STBI__BYTECAST(stbi__shiftsigned(v & mr, rshift, rcount));
++               out[z++] = STBI__BYTECAST(stbi__shiftsigned(v & mg, gshift, gcount));
++               out[z++] = STBI__BYTECAST(stbi__shiftsigned(v & mb, bshift, bcount));
++               a = (ma ? stbi__shiftsigned(v & ma, ashift, acount) : 255);
++               all_a |= a;
++               if (target == 4) out[z++] = STBI__BYTECAST(a);
++            }
++         }
++         stbi__skip(s, pad);
++      }
++   }
++
++   // if alpha channel is all 0s, replace with all 255s
++   if (target == 4 && all_a == 0)
++      for (i=4*s->img_x*s->img_y-1; i >= 0; i -= 4)
++         out[i] = 255;
++
++   if (flip_vertically) {
++      stbi_uc t;
++      for (j=0; j < (int) s->img_y>>1; ++j) {
++         stbi_uc *p1 = out +      j     *s->img_x*target;
++         stbi_uc *p2 = out + (s->img_y-1-j)*s->img_x*target;
++         for (i=0; i < (int) s->img_x*target; ++i) {
++            t = p1[i], p1[i] = p2[i], p2[i] = t;
++         }
++      }
++   }
++
++   if (req_comp && req_comp != target) {
++      out = stbi__convert_format(out, target, req_comp, s->img_x, s->img_y);
++      if (out == NULL) return out; // stbi__convert_format frees input on failure
++   }
++
++   *x = s->img_x;
++   *y = s->img_y;
++   if (comp) *comp = s->img_n;
++   return out;
++}
++#endif
++
++// Targa Truevision - TGA
++// by Jonathan Dummer
++#ifndef STBI_NO_TGA
++// returns STBI_rgb or whatever, 0 on error
++static int stbi__tga_get_comp(int bits_per_pixel, int is_grey, int* is_rgb16)
++{
++   // only RGB or RGBA (incl. 16bit) or grey allowed
++   if (is_rgb16) *is_rgb16 = 0;
++   switch(bits_per_pixel) {
++      case 8:  return STBI_grey;
++      case 16: if(is_grey) return STBI_grey_alpha;
++               // fallthrough
++      case 15: if(is_rgb16) *is_rgb16 = 1;
++               return STBI_rgb;
++      case 24: // fallthrough
++      case 32: return bits_per_pixel/8;
++      default: return 0;
++   }
++}
++
++static int stbi__tga_info(stbi__context *s, int *x, int *y, int *comp)
++{
++    int tga_w, tga_h, tga_comp, tga_image_type, tga_bits_per_pixel, tga_colormap_bpp;
++    int sz, tga_colormap_type;
++    stbi__get8(s);                   // discard Offset
++    tga_colormap_type = stbi__get8(s); // colormap type
++    if( tga_colormap_type > 1 ) {
++        stbi__rewind(s);
++        return 0;      // only RGB or indexed allowed
++    }
++    tga_image_type = stbi__get8(s); // image type
++    if ( tga_colormap_type == 1 ) { // colormapped (paletted) image
++        if (tga_image_type != 1 && tga_image_type != 9) {
++            stbi__rewind(s);
++            return 0;
++        }
++        stbi__skip(s,4);       // skip index of first colormap entry and number of entries
++        sz = stbi__get8(s);    //   check bits per palette color entry
++        if ( (sz != 8) && (sz != 15) && (sz != 16) && (sz != 24) && (sz != 32) ) {
++            stbi__rewind(s);
++            return 0;
++        }
++        stbi__skip(s,4);       // skip image x and y origin
++        tga_colormap_bpp = sz;
++    } else { // "normal" image w/o colormap - only RGB or grey allowed, +/- RLE
++        if ( (tga_image_type != 2) && (tga_image_type != 3) && (tga_image_type != 10) && (tga_image_type != 11) ) {
++            stbi__rewind(s);
++            return 0; // only RGB or grey allowed, +/- RLE
++        }
++        stbi__skip(s,9); // skip colormap specification and image x/y origin
++        tga_colormap_bpp = 0;
++    }
++    tga_w = stbi__get16le(s);
++    if( tga_w < 1 ) {
++        stbi__rewind(s);
++        return 0;   // test width
++    }
++    tga_h = stbi__get16le(s);
++    if( tga_h < 1 ) {
++        stbi__rewind(s);
++        return 0;   // test height
++    }
++    tga_bits_per_pixel = stbi__get8(s); // bits per pixel
++    stbi__get8(s); // ignore alpha bits
++    if (tga_colormap_bpp != 0) {
++        if((tga_bits_per_pixel != 8) && (tga_bits_per_pixel != 16)) {
++            // when using a colormap, tga_bits_per_pixel is the size of the indexes
++            // I don't think anything but 8 or 16bit indexes makes sense
++            stbi__rewind(s);
++            return 0;
++        }
++        tga_comp = stbi__tga_get_comp(tga_colormap_bpp, 0, NULL);
++    } else {
++        tga_comp = stbi__tga_get_comp(tga_bits_per_pixel, (tga_image_type == 3) || (tga_image_type == 11), NULL);
++    }
++    if(!tga_comp) {
++      stbi__rewind(s);
++      return 0;
++    }
++    if (x) *x = tga_w;
++    if (y) *y = tga_h;
++    if (comp) *comp = tga_comp;
++    return 1;                   // seems to have passed everything
++}
++
++static int stbi__tga_test(stbi__context *s)
++{
++   int res = 0;
++   int sz, tga_color_type;
++   stbi__get8(s);      //   discard Offset
++   tga_color_type = stbi__get8(s);   //   color type
++   if ( tga_color_type > 1 ) goto errorEnd;   //   only RGB or indexed allowed
++   sz = stbi__get8(s);   //   image type
++   if ( tga_color_type == 1 ) { // colormapped (paletted) image
++      if (sz != 1 && sz != 9) goto errorEnd; // colortype 1 demands image type 1 or 9
++      stbi__skip(s,4);       // skip index of first colormap entry and number of entries
++      sz = stbi__get8(s);    //   check bits per palette color entry
++      if ( (sz != 8) && (sz != 15) && (sz != 16) && (sz != 24) && (sz != 32) ) goto errorEnd;
++      stbi__skip(s,4);       // skip image x and y origin
++   } else { // "normal" image w/o colormap
++      if ( (sz != 2) && (sz != 3) && (sz != 10) && (sz != 11) ) goto errorEnd; // only RGB or grey allowed, +/- RLE
++      stbi__skip(s,9); // skip colormap specification and image x/y origin
++   }
++   if ( stbi__get16le(s) < 1 ) goto errorEnd;      //   test width
++   if ( stbi__get16le(s) < 1 ) goto errorEnd;      //   test height
++   sz = stbi__get8(s);   //   bits per pixel
++   if ( (tga_color_type == 1) && (sz != 8) && (sz != 16) ) goto errorEnd; // for colormapped images, bpp is size of an index
++   if ( (sz != 8) && (sz != 15) && (sz != 16) && (sz != 24) && (sz != 32) ) goto errorEnd;
++
++   res = 1; // if we got this far, everything's good and we can return 1 instead of 0
++
++errorEnd:
++   stbi__rewind(s);
++   return res;
++}
++
++// read 16bit value and convert to 24bit RGB
++static void stbi__tga_read_rgb16(stbi__context *s, stbi_uc* out)
++{
++   stbi__uint16 px = (stbi__uint16)stbi__get16le(s);
++   stbi__uint16 fiveBitMask = 31;
++   // we have 3 channels with 5bits each
++   int r = (px >> 10) & fiveBitMask;
++   int g = (px >> 5) & fiveBitMask;
++   int b = px & fiveBitMask;
++   // Note that this saves the data in RGB(A) order, so it doesn't need to be swapped later
++   out[0] = (stbi_uc)((r * 255)/31);
++   out[1] = (stbi_uc)((g * 255)/31);
++   out[2] = (stbi_uc)((b * 255)/31);
++
++   // some people claim that the most significant bit might be used for alpha
++   // (possibly if an alpha-bit is set in the "image descriptor byte")
++   // but that only made 16bit test images completely translucent..
++   // so let's treat all 15 and 16bit TGAs as RGB with no alpha.
++}
++
++static void *stbi__tga_load(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri)
++{
++   //   read in the TGA header stuff
++   int tga_offset = stbi__get8(s);
++   int tga_indexed = stbi__get8(s);
++   int tga_image_type = stbi__get8(s);
++   int tga_is_RLE = 0;
++   int tga_palette_start = stbi__get16le(s);
++   int tga_palette_len = stbi__get16le(s);
++   int tga_palette_bits = stbi__get8(s);
++   int tga_x_origin = stbi__get16le(s);
++   int tga_y_origin = stbi__get16le(s);
++   int tga_width = stbi__get16le(s);
++   int tga_height = stbi__get16le(s);
++   int tga_bits_per_pixel = stbi__get8(s);
++   int tga_comp, tga_rgb16=0;
++   int tga_inverted = stbi__get8(s);
++   // int tga_alpha_bits = tga_inverted & 15; // the 4 lowest bits - unused (useless?)
++   //   image data
++   unsigned char *tga_data;
++   unsigned char *tga_palette = NULL;
++   int i, j;
++   unsigned char raw_data[4] = {0};
++   int RLE_count = 0;
++   int RLE_repeating = 0;
++   int read_next_pixel = 1;
++   STBI_NOTUSED(ri);
++
++   //   do a tiny bit of precessing
++   if ( tga_image_type >= 8 )
++   {
++      tga_image_type -= 8;
++      tga_is_RLE = 1;
++   }
++   tga_inverted = 1 - ((tga_inverted >> 5) & 1);
++
++   //   If I'm paletted, then I'll use the number of bits from the palette
++   if ( tga_indexed ) tga_comp = stbi__tga_get_comp(tga_palette_bits, 0, &tga_rgb16);
++   else tga_comp = stbi__tga_get_comp(tga_bits_per_pixel, (tga_image_type == 3), &tga_rgb16);
++
++   if(!tga_comp) // shouldn't really happen, stbi__tga_test() should have ensured basic consistency
++      return stbi__errpuc("bad format", "Can't find out TGA pixelformat");
++
++   //   tga info
++   *x = tga_width;
++   *y = tga_height;
++   if (comp) *comp = tga_comp;
++
++   if (!stbi__mad3sizes_valid(tga_width, tga_height, tga_comp, 0))
++      return stbi__errpuc("too large", "Corrupt TGA");
++
++   tga_data = (unsigned char*)stbi__malloc_mad3(tga_width, tga_height, tga_comp, 0);
++   if (!tga_data) return stbi__errpuc("outofmem", "Out of memory");
++
++   // skip to the data's starting position (offset usually = 0)
++   stbi__skip(s, tga_offset );
++
++   if ( !tga_indexed && !tga_is_RLE && !tga_rgb16 ) {
++      for (i=0; i < tga_height; ++i) {
++         int row = tga_inverted ? tga_height -i - 1 : i;
++         stbi_uc *tga_row = tga_data + row*tga_width*tga_comp;
++         stbi__getn(s, tga_row, tga_width * tga_comp);
++      }
++   } else  {
++      //   do I need to load a palette?
++      if ( tga_indexed)
++      {
++         //   any data to skip? (offset usually = 0)
++         stbi__skip(s, tga_palette_start );
++         //   load the palette
++         tga_palette = (unsigned char*)stbi__malloc_mad2(tga_palette_len, tga_comp, 0);
++         if (!tga_palette) {
++            STBI_FREE(tga_data);
++            return stbi__errpuc("outofmem", "Out of memory");
++         }
++         if (tga_rgb16) {
++            stbi_uc *pal_entry = tga_palette;
++            STBI_ASSERT(tga_comp == STBI_rgb);
++            for (i=0; i < tga_palette_len; ++i) {
++               stbi__tga_read_rgb16(s, pal_entry);
++               pal_entry += tga_comp;
++            }
++         } else if (!stbi__getn(s, tga_palette, tga_palette_len * tga_comp)) {
++               STBI_FREE(tga_data);
++               STBI_FREE(tga_palette);
++               return stbi__errpuc("bad palette", "Corrupt TGA");
++         }
++      }
++      //   load the data
++      for (i=0; i < tga_width * tga_height; ++i)
++      {
++         //   if I'm in RLE mode, do I need to get a RLE stbi__pngchunk?
++         if ( tga_is_RLE )
++         {
++            if ( RLE_count == 0 )
++            {
++               //   yep, get the next byte as a RLE command
++               int RLE_cmd = stbi__get8(s);
++               RLE_count = 1 + (RLE_cmd & 127);
++               RLE_repeating = RLE_cmd >> 7;
++               read_next_pixel = 1;
++            } else if ( !RLE_repeating )
++            {
++               read_next_pixel = 1;
++            }
++         } else
++         {
++            read_next_pixel = 1;
++         }
++         //   OK, if I need to read a pixel, do it now
++         if ( read_next_pixel )
++         {
++            //   load however much data we did have
++            if ( tga_indexed )
++            {
++               // read in index, then perform the lookup
++               int pal_idx = (tga_bits_per_pixel == 8) ? stbi__get8(s) : stbi__get16le(s);
++               if ( pal_idx >= tga_palette_len ) {
++                  // invalid index
++                  pal_idx = 0;
++               }
++               pal_idx *= tga_comp;
++               for (j = 0; j < tga_comp; ++j) {
++                  raw_data[j] = tga_palette[pal_idx+j];
++               }
++            } else if(tga_rgb16) {
++               STBI_ASSERT(tga_comp == STBI_rgb);
++               stbi__tga_read_rgb16(s, raw_data);
++            } else {
++               //   read in the data raw
++               for (j = 0; j < tga_comp; ++j) {
++                  raw_data[j] = stbi__get8(s);
++               }
++            }
++            //   clear the reading flag for the next pixel
++            read_next_pixel = 0;
++         } // end of reading a pixel
++
++         // copy data
++         for (j = 0; j < tga_comp; ++j)
++           tga_data[i*tga_comp+j] = raw_data[j];
++
++         //   in case we're in RLE mode, keep counting down
++         --RLE_count;
++      }
++      //   do I need to invert the image?
++      if ( tga_inverted )
++      {
++         for (j = 0; j*2 < tga_height; ++j)
++         {
++            int index1 = j * tga_width * tga_comp;
++            int index2 = (tga_height - 1 - j) * tga_width * tga_comp;
++            for (i = tga_width * tga_comp; i > 0; --i)
++            {
++               unsigned char temp = tga_data[index1];
++               tga_data[index1] = tga_data[index2];
++               tga_data[index2] = temp;
++               ++index1;
++               ++index2;
++            }
++         }
++      }
++      //   clear my palette, if I had one
++      if ( tga_palette != NULL )
++      {
++         STBI_FREE( tga_palette );
++      }
++   }
++
++   // swap RGB - if the source data was RGB16, it already is in the right order
++   if (tga_comp >= 3 && !tga_rgb16)
++   {
++      unsigned char* tga_pixel = tga_data;
++      for (i=0; i < tga_width * tga_height; ++i)
++      {
++         unsigned char temp = tga_pixel[0];
++         tga_pixel[0] = tga_pixel[2];
++         tga_pixel[2] = temp;
++         tga_pixel += tga_comp;
++      }
++   }
++
++   // convert to target component count
++   if (req_comp && req_comp != tga_comp)
++      tga_data = stbi__convert_format(tga_data, tga_comp, req_comp, tga_width, tga_height);
++
++   //   the things I do to get rid of an error message, and yet keep
++   //   Microsoft's C compilers happy... [8^(
++   tga_palette_start = tga_palette_len = tga_palette_bits =
++         tga_x_origin = tga_y_origin = 0;
++   //   OK, done
++   return tga_data;
++}
++#endif
++
++// *************************************************************************************************
++// Photoshop PSD loader -- PD by Thatcher Ulrich, integration by Nicolas Schulz, tweaked by STB
++
++#ifndef STBI_NO_PSD
++static int stbi__psd_test(stbi__context *s)
++{
++   int r = (stbi__get32be(s) == 0x38425053);
++   stbi__rewind(s);
++   return r;
++}
++
++static int stbi__psd_decode_rle(stbi__context *s, stbi_uc *p, int pixelCount)
++{
++   int count, nleft, len;
++
++   count = 0;
++   while ((nleft = pixelCount - count) > 0) {
++      len = stbi__get8(s);
++      if (len == 128) {
++         // No-op.
++      } else if (len < 128) {
++         // Copy next len+1 bytes literally.
++         len++;
++         if (len > nleft) return 0; // corrupt data
++         count += len;
++         while (len) {
++            *p = stbi__get8(s);
++            p += 4;
++            len--;
++         }
++      } else if (len > 128) {
++         stbi_uc   val;
++         // Next -len+1 bytes in the dest are replicated from next source byte.
++         // (Interpret len as a negative 8-bit int.)
++         len = 257 - len;
++         if (len > nleft) return 0; // corrupt data
++         val = stbi__get8(s);
++         count += len;
++         while (len) {
++            *p = val;
++            p += 4;
++            len--;
++         }
++      }
++   }
++
++   return 1;
++}
++
++static void *stbi__psd_load(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri, int bpc)
++{
++   int pixelCount;
++   int channelCount, compression;
++   int channel, i;
++   int bitdepth;
++   int w,h;
++   stbi_uc *out;
++   STBI_NOTUSED(ri);
++
++   // Check identifier
++   if (stbi__get32be(s) != 0x38425053)   // "8BPS"
++      return stbi__errpuc("not PSD", "Corrupt PSD image");
++
++   // Check file type version.
++   if (stbi__get16be(s) != 1)
++      return stbi__errpuc("wrong version", "Unsupported version of PSD image");
++
++   // Skip 6 reserved bytes.
++   stbi__skip(s, 6 );
++
++   // Read the number of channels (R, G, B, A, etc).
++   channelCount = stbi__get16be(s);
++   if (channelCount < 0 || channelCount > 16)
++      return stbi__errpuc("wrong channel count", "Unsupported number of channels in PSD image");
++
++   // Read the rows and columns of the image.
++   h = stbi__get32be(s);
++   w = stbi__get32be(s);
++
++   // Make sure the depth is 8 bits.
++   bitdepth = stbi__get16be(s);
++   if (bitdepth != 8 && bitdepth != 16)
++      return stbi__errpuc("unsupported bit depth", "PSD bit depth is not 8 or 16 bit");
++
++   // Make sure the color mode is RGB.
++   // Valid options are:
++   //   0: Bitmap
++   //   1: Grayscale
++   //   2: Indexed color
++   //   3: RGB color
++   //   4: CMYK color
++   //   7: Multichannel
++   //   8: Duotone
++   //   9: Lab color
++   if (stbi__get16be(s) != 3)
++      return stbi__errpuc("wrong color format", "PSD is not in RGB color format");
++
++   // Skip the Mode Data.  (It's the palette for indexed color; other info for other modes.)
++   stbi__skip(s,stbi__get32be(s) );
++
++   // Skip the image resources.  (resolution, pen tool paths, etc)
++   stbi__skip(s, stbi__get32be(s) );
++
++   // Skip the reserved data.
++   stbi__skip(s, stbi__get32be(s) );
++
++   // Find out if the data is compressed.
++   // Known values:
++   //   0: no compression
++   //   1: RLE compressed
++   compression = stbi__get16be(s);
++   if (compression > 1)
++      return stbi__errpuc("bad compression", "PSD has an unknown compression format");
++
++   // Check size
++   if (!stbi__mad3sizes_valid(4, w, h, 0))
++      return stbi__errpuc("too large", "Corrupt PSD");
++
++   // Create the destination image.
++
++   if (!compression && bitdepth == 16 && bpc == 16) {
++      out = (stbi_uc *) stbi__malloc_mad3(8, w, h, 0);
++      ri->bits_per_channel = 16;
++   } else
++      out = (stbi_uc *) stbi__malloc(4 * w*h);
++
++   if (!out) return stbi__errpuc("outofmem", "Out of memory");
++   pixelCount = w*h;
++
++   // Initialize the data to zero.
++   //memset( out, 0, pixelCount * 4 );
++
++   // Finally, the image data.
++   if (compression) {
++      // RLE as used by .PSD and .TIFF
++      // Loop until you get the number of unpacked bytes you are expecting:
++      //     Read the next source byte into n.
++      //     If n is between 0 and 127 inclusive, copy the next n+1 bytes literally.
++      //     Else if n is between -127 and -1 inclusive, copy the next byte -n+1 times.
++      //     Else if n is 128, noop.
++      // Endloop
++
++      // The RLE-compressed data is preceeded by a 2-byte data count for each row in the data,
++      // which we're going to just skip.
++      stbi__skip(s, h * channelCount * 2 );
++
++      // Read the RLE data by channel.
++      for (channel = 0; channel < 4; channel++) {
++         stbi_uc *p;
++
++         p = out+channel;
++         if (channel >= channelCount) {
++            // Fill this channel with default data.
++            for (i = 0; i < pixelCount; i++, p += 4)
++               *p = (channel == 3 ? 255 : 0);
++         } else {
++            // Read the RLE data.
++            if (!stbi__psd_decode_rle(s, p, pixelCount)) {
++               STBI_FREE(out);
++               return stbi__errpuc("corrupt", "bad RLE data");
++            }
++         }
++      }
++
++   } else {
++      // We're at the raw image data.  It's each channel in order (Red, Green, Blue, Alpha, ...)
++      // where each channel consists of an 8-bit (or 16-bit) value for each pixel in the image.
++
++      // Read the data by channel.
++      for (channel = 0; channel < 4; channel++) {
++         if (channel >= channelCount) {
++            // Fill this channel with default data.
++            if (bitdepth == 16 && bpc == 16) {
++               stbi__uint16 *q = ((stbi__uint16 *) out) + channel;
++               stbi__uint16 val = channel == 3 ? 65535 : 0;
++               for (i = 0; i < pixelCount; i++, q += 4)
++                  *q = val;
++            } else {
++               stbi_uc *p = out+channel;
++               stbi_uc val = channel == 3 ? 255 : 0;
++               for (i = 0; i < pixelCount; i++, p += 4)
++                  *p = val;
++            }
++         } else {
++            if (ri->bits_per_channel == 16) {    // output bpc
++               stbi__uint16 *q = ((stbi__uint16 *) out) + channel;
++               for (i = 0; i < pixelCount; i++, q += 4)
++                  *q = (stbi__uint16) stbi__get16be(s);
++            } else {
++               stbi_uc *p = out+channel;
++               if (bitdepth == 16) {  // input bpc
++                  for (i = 0; i < pixelCount; i++, p += 4)
++                     *p = (stbi_uc) (stbi__get16be(s) >> 8);
++               } else {
++                  for (i = 0; i < pixelCount; i++, p += 4)
++                     *p = stbi__get8(s);
++               }
++            }
++         }
++      }
++   }
++
++   // remove weird white matte from PSD
++   if (channelCount >= 4) {
++      if (ri->bits_per_channel == 16) {
++         for (i=0; i < w*h; ++i) {
++            stbi__uint16 *pixel = (stbi__uint16 *) out + 4*i;
++            if (pixel[3] != 0 && pixel[3] != 65535) {
++               float a = pixel[3] / 65535.0f;
++               float ra = 1.0f / a;
++               float inv_a = 65535.0f * (1 - ra);
++               pixel[0] = (stbi__uint16) (pixel[0]*ra + inv_a);
++               pixel[1] = (stbi__uint16) (pixel[1]*ra + inv_a);
++               pixel[2] = (stbi__uint16) (pixel[2]*ra + inv_a);
++            }
++         }
++      } else {
++         for (i=0; i < w*h; ++i) {
++            unsigned char *pixel = out + 4*i;
++            if (pixel[3] != 0 && pixel[3] != 255) {
++               float a = pixel[3] / 255.0f;
++               float ra = 1.0f / a;
++               float inv_a = 255.0f * (1 - ra);
++               pixel[0] = (unsigned char) (pixel[0]*ra + inv_a);
++               pixel[1] = (unsigned char) (pixel[1]*ra + inv_a);
++               pixel[2] = (unsigned char) (pixel[2]*ra + inv_a);
++            }
++         }
++      }
++   }
++
++   // convert to desired output format
++   if (req_comp && req_comp != 4) {
++      if (ri->bits_per_channel == 16)
++         out = (stbi_uc *) stbi__convert_format16((stbi__uint16 *) out, 4, req_comp, w, h);
++      else
++         out = stbi__convert_format(out, 4, req_comp, w, h);
++      if (out == NULL) return out; // stbi__convert_format frees input on failure
++   }
++
++   if (comp) *comp = 4;
++   *y = h;
++   *x = w;
++
++   return out;
++}
++#endif
++
++// *************************************************************************************************
++// Softimage PIC loader
++// by Tom Seddon
++//
++// See http://softimage.wiki.softimage.com/index.php/INFO:_PIC_file_format
++// See http://ozviz.wasp.uwa.edu.au/~pbourke/dataformats/softimagepic/
++
++#ifndef STBI_NO_PIC
++static int stbi__pic_is4(stbi__context *s,const char *str)
++{
++   int i;
++   for (i=0; i<4; ++i)
++      if (stbi__get8(s) != (stbi_uc)str[i])
++         return 0;
++
++   return 1;
++}
++
++static int stbi__pic_test_core(stbi__context *s)
++{
++   int i;
++
++   if (!stbi__pic_is4(s,"\x53\x80\xF6\x34"))
++      return 0;
++
++   for(i=0;i<84;++i)
++      stbi__get8(s);
++
++   if (!stbi__pic_is4(s,"PICT"))
++      return 0;
++
++   return 1;
++}
++
++typedef struct
++{
++   stbi_uc size,type,channel;
++} stbi__pic_packet;
++
++static stbi_uc *stbi__readval(stbi__context *s, int channel, stbi_uc *dest)
++{
++   int mask=0x80, i;
++
++   for (i=0; i<4; ++i, mask>>=1) {
++      if (channel & mask) {
++         if (stbi__at_eof(s)) return stbi__errpuc("bad file","PIC file too short");
++         dest[i]=stbi__get8(s);
++      }
++   }
++
++   return dest;
++}
++
++static void stbi__copyval(int channel,stbi_uc *dest,const stbi_uc *src)
++{
++   int mask=0x80,i;
++
++   for (i=0;i<4; ++i, mask>>=1)
++      if (channel&mask)
++         dest[i]=src[i];
++}
++
++static stbi_uc *stbi__pic_load_core(stbi__context *s,int width,int height,int *comp, stbi_uc *result)
++{
++   int act_comp=0,num_packets=0,y,chained;
++   stbi__pic_packet packets[10];
++
++   // this will (should...) cater for even some bizarre stuff like having data
++    // for the same channel in multiple packets.
++   do {
++      stbi__pic_packet *packet;
++
++      if (num_packets==sizeof(packets)/sizeof(packets[0]))
++         return stbi__errpuc("bad format","too many packets");
++
++      packet = &packets[num_packets++];
++
++      chained = stbi__get8(s);
++      packet->size    = stbi__get8(s);
++      packet->type    = stbi__get8(s);
++      packet->channel = stbi__get8(s);
++
++      act_comp |= packet->channel;
++
++      if (stbi__at_eof(s))          return stbi__errpuc("bad file","file too short (reading packets)");
++      if (packet->size != 8)  return stbi__errpuc("bad format","packet isn't 8bpp");
++   } while (chained);
++
++   *comp = (act_comp & 0x10 ? 4 : 3); // has alpha channel?
++
++   for(y=0; y<height; ++y) {
++      int packet_idx;
++
++      for(packet_idx=0; packet_idx < num_packets; ++packet_idx) {
++         stbi__pic_packet *packet = &packets[packet_idx];
++         stbi_uc *dest = result+y*width*4;
++
++         switch (packet->type) {
++            default:
++               return stbi__errpuc("bad format","packet has bad compression type");
++
++            case 0: {//uncompressed
++               int x;
++
++               for(x=0;x<width;++x, dest+=4)
++                  if (!stbi__readval(s,packet->channel,dest))
++                     return 0;
++               break;
++            }
++
++            case 1://Pure RLE
++               {
++                  int left=width, i;
++
++                  while (left>0) {
++                     stbi_uc count,value[4];
++
++                     count=stbi__get8(s);
++                     if (stbi__at_eof(s))   return stbi__errpuc("bad file","file too short (pure read count)");
++
++                     if (count > left)
++                        count = (stbi_uc) left;
++
++                     if (!stbi__readval(s,packet->channel,value))  return 0;
++
++                     for(i=0; i<count; ++i,dest+=4)
++                        stbi__copyval(packet->channel,dest,value);
++                     left -= count;
++                  }
++               }
++               break;
++
++            case 2: {//Mixed RLE
++               int left=width;
++               while (left>0) {
++                  int count = stbi__get8(s), i;
++                  if (stbi__at_eof(s))  return stbi__errpuc("bad file","file too short (mixed read count)");
++
++                  if (count >= 128) { // Repeated
++                     stbi_uc value[4];
++
++                     if (count==128)
++                        count = stbi__get16be(s);
++                     else
++                        count -= 127;
++                     if (count > left)
++                        return stbi__errpuc("bad file","scanline overrun");
++
++                     if (!stbi__readval(s,packet->channel,value))
++                        return 0;
++
++                     for(i=0;i<count;++i, dest += 4)
++                        stbi__copyval(packet->channel,dest,value);
++                  } else { // Raw
++                     ++count;
++                     if (count>left) return stbi__errpuc("bad file","scanline overrun");
++
++                     for(i=0;i<count;++i, dest+=4)
++                        if (!stbi__readval(s,packet->channel,dest))
++                           return 0;
++                  }
++                  left-=count;
++               }
++               break;
++            }
++         }
++      }
++   }
++
++   return result;
++}
++
++static void *stbi__pic_load(stbi__context *s,int *px,int *py,int *comp,int req_comp, stbi__result_info *ri)
++{
++   stbi_uc *result;
++   int i, x,y, internal_comp;
++   STBI_NOTUSED(ri);
++
++   if (!comp) comp = &internal_comp;
++
++   for (i=0; i<92; ++i)
++      stbi__get8(s);
++
++   x = stbi__get16be(s);
++   y = stbi__get16be(s);
++   if (stbi__at_eof(s))  return stbi__errpuc("bad file","file too short (pic header)");
++   if (!stbi__mad3sizes_valid(x, y, 4, 0)) return stbi__errpuc("too large", "PIC image too large to decode");
++
++   stbi__get32be(s); //skip `ratio'
++   stbi__get16be(s); //skip `fields'
++   stbi__get16be(s); //skip `pad'
++
++   // intermediate buffer is RGBA
++   result = (stbi_uc *) stbi__malloc_mad3(x, y, 4, 0);
++   memset(result, 0xff, x*y*4);
++
++   if (!stbi__pic_load_core(s,x,y,comp, result)) {
++      STBI_FREE(result);
++      result=0;
++   }
++   *px = x;
++   *py = y;
++   if (req_comp == 0) req_comp = *comp;
++   result=stbi__convert_format(result,4,req_comp,x,y);
++
++   return result;
++}
++
++static int stbi__pic_test(stbi__context *s)
++{
++   int r = stbi__pic_test_core(s);
++   stbi__rewind(s);
++   return r;
++}
++#endif
++
++// *************************************************************************************************
++// GIF loader -- public domain by Jean-Marc Lienher -- simplified/shrunk by stb
++
++#ifndef STBI_NO_GIF
++typedef struct
++{
++   stbi__int16 prefix;
++   stbi_uc first;
++   stbi_uc suffix;
++} stbi__gif_lzw;
++
++typedef struct
++{
++   int w,h;
++   stbi_uc *out;                 // output buffer (always 4 components)
++   stbi_uc *background;          // The current "background" as far as a gif is concerned
++   stbi_uc *history;
++   int flags, bgindex, ratio, transparent, eflags;
++   stbi_uc  pal[256][4];
++   stbi_uc lpal[256][4];
++   stbi__gif_lzw codes[8192];
++   stbi_uc *color_table;
++   int parse, step;
++   int lflags;
++   int start_x, start_y;
++   int max_x, max_y;
++   int cur_x, cur_y;
++   int line_size;
++   int delay;
++} stbi__gif;
++
++static int stbi__gif_test_raw(stbi__context *s)
++{
++   int sz;
++   if (stbi__get8(s) != 'G' || stbi__get8(s) != 'I' || stbi__get8(s) != 'F' || stbi__get8(s) != '8') return 0;
++   sz = stbi__get8(s);
++   if (sz != '9' && sz != '7') return 0;
++   if (stbi__get8(s) != 'a') return 0;
++   return 1;
++}
++
++static int stbi__gif_test(stbi__context *s)
++{
++   int r = stbi__gif_test_raw(s);
++   stbi__rewind(s);
++   return r;
++}
++
++static void stbi__gif_parse_colortable(stbi__context *s, stbi_uc pal[256][4], int num_entries, int transp)
++{
++   int i;
++   for (i=0; i < num_entries; ++i) {
++      pal[i][2] = stbi__get8(s);
++      pal[i][1] = stbi__get8(s);
++      pal[i][0] = stbi__get8(s);
++      pal[i][3] = transp == i ? 0 : 255;
++   }
++}
++
++static int stbi__gif_header(stbi__context *s, stbi__gif *g, int *comp, int is_info)
++{
++   stbi_uc version;
++   if (stbi__get8(s) != 'G' || stbi__get8(s) != 'I' || stbi__get8(s) != 'F' || stbi__get8(s) != '8')
++      return stbi__err("not GIF", "Corrupt GIF");
++
++   version = stbi__get8(s);
++   if (version != '7' && version != '9')    return stbi__err("not GIF", "Corrupt GIF");
++   if (stbi__get8(s) != 'a')                return stbi__err("not GIF", "Corrupt GIF");
++
++   stbi__g_failure_reason = "";
++   g->w = stbi__get16le(s);
++   g->h = stbi__get16le(s);
++   g->flags = stbi__get8(s);
++   g->bgindex = stbi__get8(s);
++   g->ratio = stbi__get8(s);
++   g->transparent = -1;
++
++   if (comp != 0) *comp = 4;  // can't actually tell whether it's 3 or 4 until we parse the comments
++
++   if (is_info) return 1;
++
++   if (g->flags & 0x80)
++      stbi__gif_parse_colortable(s,g->pal, 2 << (g->flags & 7), -1);
++
++   return 1;
++}
++
++static int stbi__gif_info_raw(stbi__context *s, int *x, int *y, int *comp)
++{
++   stbi__gif* g = (stbi__gif*) stbi__malloc(sizeof(stbi__gif));
++   if (!stbi__gif_header(s, g, comp, 1)) {
++      STBI_FREE(g);
++      stbi__rewind( s );
++      return 0;
++   }
++   if (x) *x = g->w;
++   if (y) *y = g->h;
++   STBI_FREE(g);
++   return 1;
++}
++
++static void stbi__out_gif_code(stbi__gif *g, stbi__uint16 code)
++{
++   stbi_uc *p, *c;
++   int idx;
++
++   // recurse to decode the prefixes, since the linked-list is backwards,
++   // and working backwards through an interleaved image would be nasty
++   if (g->codes[code].prefix >= 0)
++      stbi__out_gif_code(g, g->codes[code].prefix);
++
++   if (g->cur_y >= g->max_y) return;
++
++   idx = g->cur_x + g->cur_y;
++   p = &g->out[idx];
++   g->history[idx / 4] = 1;
++
++   c = &g->color_table[g->codes[code].suffix * 4];
++   if (c[3] > 128) { // don't render transparent pixels;
++      p[0] = c[2];
++      p[1] = c[1];
++      p[2] = c[0];
++      p[3] = c[3];
++   }
++   g->cur_x += 4;
++
++   if (g->cur_x >= g->max_x) {
++      g->cur_x = g->start_x;
++      g->cur_y += g->step;
++
++      while (g->cur_y >= g->max_y && g->parse > 0) {
++         g->step = (1 << g->parse) * g->line_size;
++         g->cur_y = g->start_y + (g->step >> 1);
++         --g->parse;
++      }
++   }
++}
++
++static stbi_uc *stbi__process_gif_raster(stbi__context *s, stbi__gif *g)
++{
++   stbi_uc lzw_cs;
++   stbi__int32 len, init_code;
++   stbi__uint32 first;
++   stbi__int32 codesize, codemask, avail, oldcode, bits, valid_bits, clear;
++   stbi__gif_lzw *p;
++
++   lzw_cs = stbi__get8(s);
++   if (lzw_cs > 12) return NULL;
++   clear = 1 << lzw_cs;
++   first = 1;
++   codesize = lzw_cs + 1;
++   codemask = (1 << codesize) - 1;
++   bits = 0;
++   valid_bits = 0;
++   for (init_code = 0; init_code < clear; init_code++) {
++      g->codes[init_code].prefix = -1;
++      g->codes[init_code].first = (stbi_uc) init_code;
++      g->codes[init_code].suffix = (stbi_uc) init_code;
++   }
++
++   // support no starting clear code
++   avail = clear+2;
++   oldcode = -1;
++
++   len = 0;
++   for(;;) {
++      if (valid_bits < codesize) {
++         if (len == 0) {
++            len = stbi__get8(s); // start new block
++            if (len == 0)
++               return g->out;
++         }
++         --len;
++         bits |= (stbi__int32) stbi__get8(s) << valid_bits;
++         valid_bits += 8;
++      } else {
++         stbi__int32 code = bits & codemask;
++         bits >>= codesize;
++         valid_bits -= codesize;
++         // @OPTIMIZE: is there some way we can accelerate the non-clear path?
++         if (code == clear) {  // clear code
++            codesize = lzw_cs + 1;
++            codemask = (1 << codesize) - 1;
++            avail = clear + 2;
++            oldcode = -1;
++            first = 0;
++         } else if (code == clear + 1) { // end of stream code
++            stbi__skip(s, len);
++            while ((len = stbi__get8(s)) > 0)
++               stbi__skip(s,len);
++            return g->out;
++         } else if (code <= avail) {
++            if (first) {
++               return stbi__errpuc("no clear code", "Corrupt GIF");
++            }
++
++            if (oldcode >= 0) {
++               p = &g->codes[avail++];
++               if (avail > 8192) {
++                  return stbi__errpuc("too many codes", "Corrupt GIF");
++               }
++
++               p->prefix = (stbi__int16) oldcode;
++               p->first = g->codes[oldcode].first;
++               p->suffix = (code == avail) ? p->first : g->codes[code].first;
++            } else if (code == avail)
++               return stbi__errpuc("illegal code in raster", "Corrupt GIF");
++
++            stbi__out_gif_code(g, (stbi__uint16) code);
++
++            if ((avail & codemask) == 0 && avail <= 0x0FFF) {
++               codesize++;
++               codemask = (1 << codesize) - 1;
++            }
++
++            oldcode = code;
++         } else {
++            return stbi__errpuc("illegal code in raster", "Corrupt GIF");
++         }
++      }
++   }
++}
++
++// this function is designed to support animated gifs, although stb_image doesn't support it
++// two back is the image from two frames ago, used for a very specific disposal format
++static stbi_uc *stbi__gif_load_next(stbi__context *s, stbi__gif *g, int *comp, int req_comp, stbi_uc *two_back)
++{
++   int dispose;
++   int first_frame;
++   int pi;
++   int pcount;
++
++   // on first frame, any non-written pixels get the background colour (non-transparent)
++   first_frame = 0;
++   if (g->out == 0) {
++      if (!stbi__gif_header(s, g, comp,0))     return 0; // stbi__g_failure_reason set by stbi__gif_header
++      g->out = (stbi_uc *) stbi__malloc(4 * g->w * g->h);
++      g->background = (stbi_uc *) stbi__malloc(4 * g->w * g->h);
++      g->history = (stbi_uc *) stbi__malloc(g->w * g->h);
++      if (g->out == 0)                      return stbi__errpuc("outofmem", "Out of memory");
++
++      // image is treated as "tranparent" at the start - ie, nothing overwrites the current background;
++      // background colour is only used for pixels that are not rendered first frame, after that "background"
++      // color refers to teh color that was there the previous frame.
++      memset( g->out, 0x00, 4 * g->w * g->h );
++      memset( g->background, 0x00, 4 * g->w * g->h ); // state of the background (starts transparent)
++      memset( g->history, 0x00, g->w * g->h );        // pixels that were affected previous frame
++      first_frame = 1;
++   } else {
++      // second frame - how do we dispoase of the previous one?
++      dispose = (g->eflags & 0x1C) >> 2;
++      pcount = g->w * g->h;
++
++      if ((dispose == 3) && (two_back == 0)) {
++         dispose = 2; // if I don't have an image to revert back to, default to the old background
++      }
++
++      if (dispose == 3) { // use previous graphic
++         for (pi = 0; pi < pcount; ++pi) {
++            if (g->history[pi]) {
++               memcpy( &g->out[pi * 4], &two_back[pi * 4], 4 );
++            }
++         }
++      } else if (dispose == 2) {
++         // restore what was changed last frame to background before that frame;
++         for (pi = 0; pi < pcount; ++pi) {
++            if (g->history[pi]) {
++               memcpy( &g->out[pi * 4], &g->background[pi * 4], 4 );
++            }
++         }
++      } else {
++         // This is a non-disposal case eithe way, so just
++         // leave the pixels as is, and they will become the new background
++         // 1: do not dispose
++         // 0:  not specified.
++      }
++
++      // background is what out is after the undoing of the previou frame;
++      memcpy( g->background, g->out, 4 * g->w * g->h );
++   }
++
++   // clear my history;
++   memset( g->history, 0x00, g->w * g->h );        // pixels that were affected previous frame
++
++   for (;;) {
++      int tag = stbi__get8(s);
++      switch (tag) {
++         case 0x2C: /* Image Descriptor */
++         {
++            stbi__int32 x, y, w, h;
++            stbi_uc *o;
++
++            x = stbi__get16le(s);
++            y = stbi__get16le(s);
++            w = stbi__get16le(s);
++            h = stbi__get16le(s);
++            if (((x + w) > (g->w)) || ((y + h) > (g->h)))
++               return stbi__errpuc("bad Image Descriptor", "Corrupt GIF");
++
++            g->line_size = g->w * 4;
++            g->start_x = x * 4;
++            g->start_y = y * g->line_size;
++            g->max_x   = g->start_x + w * 4;
++            g->max_y   = g->start_y + h * g->line_size;
++            g->cur_x   = g->start_x;
++            g->cur_y   = g->start_y;
++
++            g->lflags = stbi__get8(s);
++
++            if (g->lflags & 0x40) {
++               g->step = 8 * g->line_size; // first interlaced spacing
++               g->parse = 3;
++            } else {
++               g->step = g->line_size;
++               g->parse = 0;
++            }
++
++            if (g->lflags & 0x80) {
++               stbi__gif_parse_colortable(s,g->lpal, 2 << (g->lflags & 7), g->eflags & 0x01 ? g->transparent : -1);
++               g->color_table = (stbi_uc *) g->lpal;
++            } else if (g->flags & 0x80) {
++               g->color_table = (stbi_uc *) g->pal;
++            } else
++               return stbi__errpuc("missing color table", "Corrupt GIF");
++
++            o = stbi__process_gif_raster(s, g);
++            if (o == NULL) return NULL;
++
++            // if this was the first frame,
++            pcount = g->w * g->h;
++            if (first_frame && (g->bgindex > 0)) {
++               // if first frame, any pixel not drawn to gets the background color
++               for (pi = 0; pi < pcount; ++pi) {
++                  if (g->history[pi] == 0) {
++                     g->pal[g->bgindex][3] = 255; // just in case it was made transparent, undo that; It will be reset next frame if need be;
++                     memcpy( &g->out[pi * 4], &g->pal[g->bgindex], 4 );
++                  }
++               }
++            }
++
++            return o;
++         }
++
++         case 0x21: // Comment Extension.
++         {
++            int len;
++            int ext = stbi__get8(s);
++            if (ext == 0xF9) { // Graphic Control Extension.
++               len = stbi__get8(s);
++               if (len == 4) {
++                  g->eflags = stbi__get8(s);
++                  g->delay = 10 * stbi__get16le(s); // delay - 1/100th of a second, saving as 1/1000ths.
++
++                  // unset old transparent
++                  if (g->transparent >= 0) {
++                     g->pal[g->transparent][3] = 255;
++                  }
++                  if (g->eflags & 0x01) {
++                     g->transparent = stbi__get8(s);
++                     if (g->transparent >= 0) {
++                        g->pal[g->transparent][3] = 0;
++                     }
++                  } else {
++                     // don't need transparent
++                     stbi__skip(s, 1);
++                     g->transparent = -1;
++                  }
++               } else {
++                  stbi__skip(s, len);
++                  break;
++               }
++            }
++            while ((len = stbi__get8(s)) != 0) {
++               stbi__skip(s, len);
++            }
++            break;
++         }
++
++         case 0x3B: // gif stream termination code
++            return (stbi_uc *) s; // using '1' causes warning on some compilers
++
++         default:
++            return stbi__errpuc("unknown code", "Corrupt GIF");
++      }
++   }
++}
++
++static void *stbi__load_gif_main(stbi__context *s, int **delays, int *x, int *y, int *z, int *comp, int req_comp)
++{
++   if (stbi__gif_test(s)) {
++      int layers = 0;
++      stbi_uc *u = 0;
++      stbi_uc *out = 0;
++      stbi_uc *two_back = 0;
++      stbi__gif g;
++      int stride;
++      memset(&g, 0, sizeof(g));
++      if (delays) {
++         *delays = 0;
++      }
++
++      do {
++         u = stbi__gif_load_next(s, &g, comp, req_comp, two_back);
++         if (u == (stbi_uc *) s) u = 0;  // end of animated gif marker
++
++         if (u) {
++            *x = g.w;
++            *y = g.h;
++            ++layers;
++            stride = g.w * g.h * 4;
++
++            if (out) {
++               out = (stbi_uc*) STBI_REALLOC( out, layers * stride );
++               if (delays) {
++                  *delays = (int*) STBI_REALLOC( *delays, sizeof(int) * layers );
++               }
++            } else {
++               out = (stbi_uc*)stbi__malloc( layers * stride );
++               if (delays) {
++                  *delays = (int*) stbi__malloc( layers * sizeof(int) );
++               }
++            }
++            memcpy( out + ((layers - 1) * stride), u, stride );
++            if (layers >= 2) {
++               two_back = out - 2 * stride;
++            }
++
++            if (delays) {
++               (*delays)[layers - 1U] = g.delay;
++            }
++         }
++      } while (u != 0);
++
++      // free temp buffer;
++      STBI_FREE(g.out);
++      STBI_FREE(g.history);
++      STBI_FREE(g.background);
++
++      // do the final conversion after loading everything;
++      if (req_comp && req_comp != 4)
++         out = stbi__convert_format(out, 4, req_comp, layers * g.w, g.h);
++
++      *z = layers;
++      return out;
++   } else {
++      return stbi__errpuc("not GIF", "Image was not as a gif type.");
++   }
++}
++
++static void *stbi__gif_load(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri)
++{
++   stbi_uc *u = 0;
++   stbi__gif g;
++   memset(&g, 0, sizeof(g));
++
++   u = stbi__gif_load_next(s, &g, comp, req_comp, 0);
++   if (u == (stbi_uc *) s) u = 0;  // end of animated gif marker
++   if (u) {
++      *x = g.w;
++      *y = g.h;
++
++      // moved conversion to after successful load so that the same
++      // can be done for multiple frames.
++      if (req_comp && req_comp != 4)
++         u = stbi__convert_format(u, 4, req_comp, g.w, g.h);
++   }
++
++   // free buffers needed for multiple frame loading;
++   STBI_FREE(g.history);
++   STBI_FREE(g.background);
++
++   return u;
++}
++
++static int stbi__gif_info(stbi__context *s, int *x, int *y, int *comp)
++{
++   return stbi__gif_info_raw(s,x,y,comp);
++}
++#endif
++
++// *************************************************************************************************
++// Radiance RGBE HDR loader
++// originally by Nicolas Schulz
++#ifndef STBI_NO_HDR
++static int stbi__hdr_test_core(stbi__context *s, const char *signature)
++{
++   int i;
++   for (i=0; signature[i]; ++i)
++      if (stbi__get8(s) != signature[i])
++          return 0;
++   stbi__rewind(s);
++   return 1;
++}
++
++static int stbi__hdr_test(stbi__context* s)
++{
++   int r = stbi__hdr_test_core(s, "#?RADIANCE\n");
++   stbi__rewind(s);
++   if(!r) {
++       r = stbi__hdr_test_core(s, "#?RGBE\n");
++       stbi__rewind(s);
++   }
++   return r;
++}
++
++#define STBI__HDR_BUFLEN  1024
++static char *stbi__hdr_gettoken(stbi__context *z, char *buffer)
++{
++   int len=0;
++   char c = '\0';
++
++   c = (char) stbi__get8(z);
++
++   while (!stbi__at_eof(z) && c != '\n') {
++      buffer[len++] = c;
++      if (len == STBI__HDR_BUFLEN-1) {
++         // flush to end of line
++         while (!stbi__at_eof(z) && stbi__get8(z) != '\n')
++            ;
++         break;
++      }
++      c = (char) stbi__get8(z);
++   }
++
++   buffer[len] = 0;
++   return buffer;
++}
++
++static void stbi__hdr_convert(float *output, stbi_uc *input, int req_comp)
++{
++   if ( input[3] != 0 ) {
++      float f1;
++      // Exponent
++      f1 = (float) ldexp(1.0f, input[3] - (int)(128 + 8));
++      if (req_comp <= 2)
++         output[0] = (input[0] + input[1] + input[2]) * f1 / 3;
++      else {
++         output[0] = input[0] * f1;
++         output[1] = input[1] * f1;
++         output[2] = input[2] * f1;
++      }
++      if (req_comp == 2) output[1] = 1;
++      if (req_comp == 4) output[3] = 1;
++   } else {
++      switch (req_comp) {
++         case 4: output[3] = 1; /* fallthrough */
++         case 3: output[0] = output[1] = output[2] = 0;
++                 break;
++         case 2: output[1] = 1; /* fallthrough */
++         case 1: output[0] = 0;
++                 break;
++      }
++   }
++}
++
++static float *stbi__hdr_load(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri)
++{
++   char buffer[STBI__HDR_BUFLEN];
++   char *token;
++   int valid = 0;
++   int width, height;
++   stbi_uc *scanline;
++   float *hdr_data;
++   int len;
++   unsigned char count, value;
++   int i, j, k, c1,c2, z;
++   const char *headerToken;
++   STBI_NOTUSED(ri);
++
++   // Check identifier
++   headerToken = stbi__hdr_gettoken(s,buffer);
++   if (strcmp(headerToken, "#?RADIANCE") != 0 && strcmp(headerToken, "#?RGBE") != 0)
++      return stbi__errpf("not HDR", "Corrupt HDR image");
++
++   // Parse header
++   for(;;) {
++      token = stbi__hdr_gettoken(s,buffer);
++      if (token[0] == 0) break;
++      if (strcmp(token, "FORMAT=32-bit_rle_rgbe") == 0) valid = 1;
++   }
++
++   if (!valid)    return stbi__errpf("unsupported format", "Unsupported HDR format");
++
++   // Parse width and height
++   // can't use sscanf() if we're not using stdio!
++   token = stbi__hdr_gettoken(s,buffer);
++   if (strncmp(token, "-Y ", 3))  return stbi__errpf("unsupported data layout", "Unsupported HDR format");
++   token += 3;
++   height = (int) strtol(token, &token, 10);
++   while (*token == ' ') ++token;
++   if (strncmp(token, "+X ", 3))  return stbi__errpf("unsupported data layout", "Unsupported HDR format");
++   token += 3;
++   width = (int) strtol(token, NULL, 10);
++
++   *x = width;
++   *y = height;
++
++   if (comp) *comp = 3;
++   if (req_comp == 0) req_comp = 3;
++
++   if (!stbi__mad4sizes_valid(width, height, req_comp, sizeof(float), 0))
++      return stbi__errpf("too large", "HDR image is too large");
++
++   // Read data
++   hdr_data = (float *) stbi__malloc_mad4(width, height, req_comp, sizeof(float), 0);
++   if (!hdr_data)
++      return stbi__errpf("outofmem", "Out of memory");
++
++   // Load image data
++   // image data is stored as some number of sca
++   if ( width < 8 || width >= 32768) {
++      // Read flat data
++      for (j=0; j < height; ++j) {
++         for (i=0; i < width; ++i) {
++            stbi_uc rgbe[4];
++           main_decode_loop:
++            stbi__getn(s, rgbe, 4);
++            stbi__hdr_convert(hdr_data + j * width * req_comp + i * req_comp, rgbe, req_comp);
++         }
++      }
++   } else {
++      // Read RLE-encoded data
++      scanline = NULL;
++
++      for (j = 0; j < height; ++j) {
++         c1 = stbi__get8(s);
++         c2 = stbi__get8(s);
++         len = stbi__get8(s);
++         if (c1 != 2 || c2 != 2 || (len & 0x80)) {
++            // not run-length encoded, so we have to actually use THIS data as a decoded
++            // pixel (note this can't be a valid pixel--one of RGB must be >= 128)
++            stbi_uc rgbe[4];
++            rgbe[0] = (stbi_uc) c1;
++            rgbe[1] = (stbi_uc) c2;
++            rgbe[2] = (stbi_uc) len;
++            rgbe[3] = (stbi_uc) stbi__get8(s);
++            stbi__hdr_convert(hdr_data, rgbe, req_comp);
++            i = 1;
++            j = 0;
++            STBI_FREE(scanline);
++            goto main_decode_loop; // yes, this makes no sense
++         }
++         len <<= 8;
++         len |= stbi__get8(s);
++         if (len != width) { STBI_FREE(hdr_data); STBI_FREE(scanline); return stbi__errpf("invalid decoded scanline length", "corrupt HDR"); }
++         if (scanline == NULL) {
++            scanline = (stbi_uc *) stbi__malloc_mad2(width, 4, 0);
++            if (!scanline) {
++               STBI_FREE(hdr_data);
++               return stbi__errpf("outofmem", "Out of memory");
++            }
++         }
++
++         for (k = 0; k < 4; ++k) {
++            int nleft;
++            i = 0;
++            while ((nleft = width - i) > 0) {
++               count = stbi__get8(s);
++               if (count > 128) {
++                  // Run
++                  value = stbi__get8(s);
++                  count -= 128;
++                  if (count > nleft) { STBI_FREE(hdr_data); STBI_FREE(scanline); return stbi__errpf("corrupt", "bad RLE data in HDR"); }
++                  for (z = 0; z < count; ++z)
++                     scanline[i++ * 4 + k] = value;
++               } else {
++                  // Dump
++                  if (count > nleft) { STBI_FREE(hdr_data); STBI_FREE(scanline); return stbi__errpf("corrupt", "bad RLE data in HDR"); }
++                  for (z = 0; z < count; ++z)
++                     scanline[i++ * 4 + k] = stbi__get8(s);
++               }
++            }
++         }
++         for (i=0; i < width; ++i)
++            stbi__hdr_convert(hdr_data+(j*width + i)*req_comp, scanline + i*4, req_comp);
++      }
++      if (scanline)
++         STBI_FREE(scanline);
++   }
++
++   return hdr_data;
++}
++
++static int stbi__hdr_info(stbi__context *s, int *x, int *y, int *comp)
++{
++   char buffer[STBI__HDR_BUFLEN];
++   char *token;
++   int valid = 0;
++   int dummy;
++
++   if (!x) x = &dummy;
++   if (!y) y = &dummy;
++   if (!comp) comp = &dummy;
++
++   if (stbi__hdr_test(s) == 0) {
++       stbi__rewind( s );
++       return 0;
++   }
++
++   for(;;) {
++      token = stbi__hdr_gettoken(s,buffer);
++      if (token[0] == 0) break;
++      if (strcmp(token, "FORMAT=32-bit_rle_rgbe") == 0) valid = 1;
++   }
++
++   if (!valid) {
++       stbi__rewind( s );
++       return 0;
++   }
++   token = stbi__hdr_gettoken(s,buffer);
++   if (strncmp(token, "-Y ", 3)) {
++       stbi__rewind( s );
++       return 0;
++   }
++   token += 3;
++   *y = (int) strtol(token, &token, 10);
++   while (*token == ' ') ++token;
++   if (strncmp(token, "+X ", 3)) {
++       stbi__rewind( s );
++       return 0;
++   }
++   token += 3;
++   *x = (int) strtol(token, NULL, 10);
++   *comp = 3;
++   return 1;
++}
++#endif // STBI_NO_HDR
++
++#ifndef STBI_NO_BMP
++static int stbi__bmp_info(stbi__context *s, int *x, int *y, int *comp)
++{
++   void *p;
++   stbi__bmp_data info;
++
++   info.all_a = 255;
++   p = stbi__bmp_parse_header(s, &info);
++   stbi__rewind( s );
++   if (p == NULL)
++      return 0;
++   if (x) *x = s->img_x;
++   if (y) *y = s->img_y;
++   if (comp) *comp = info.ma ? 4 : 3;
++   return 1;
++}
++#endif
++
++#ifndef STBI_NO_PSD
++static int stbi__psd_info(stbi__context *s, int *x, int *y, int *comp)
++{
++   int channelCount, dummy, depth;
++   if (!x) x = &dummy;
++   if (!y) y = &dummy;
++   if (!comp) comp = &dummy;
++   if (stbi__get32be(s) != 0x38425053) {
++       stbi__rewind( s );
++       return 0;
++   }
++   if (stbi__get16be(s) != 1) {
++       stbi__rewind( s );
++       return 0;
++   }
++   stbi__skip(s, 6);
++   channelCount = stbi__get16be(s);
++   if (channelCount < 0 || channelCount > 16) {
++       stbi__rewind( s );
++       return 0;
++   }
++   *y = stbi__get32be(s);
++   *x = stbi__get32be(s);
++   depth = stbi__get16be(s);
++   if (depth != 8 && depth != 16) {
++       stbi__rewind( s );
++       return 0;
++   }
++   if (stbi__get16be(s) != 3) {
++       stbi__rewind( s );
++       return 0;
++   }
++   *comp = 4;
++   return 1;
++}
++
++static int stbi__psd_is16(stbi__context *s)
++{
++   int channelCount, depth;
++   if (stbi__get32be(s) != 0x38425053) {
++       stbi__rewind( s );
++       return 0;
++   }
++   if (stbi__get16be(s) != 1) {
++       stbi__rewind( s );
++       return 0;
++   }
++   stbi__skip(s, 6);
++   channelCount = stbi__get16be(s);
++   if (channelCount < 0 || channelCount > 16) {
++       stbi__rewind( s );
++       return 0;
++   }
++   (void) stbi__get32be(s);
++   (void) stbi__get32be(s);
++   depth = stbi__get16be(s);
++   if (depth != 16) {
++       stbi__rewind( s );
++       return 0;
++   }
++   return 1;
++}
++#endif
++
++#ifndef STBI_NO_PIC
++static int stbi__pic_info(stbi__context *s, int *x, int *y, int *comp)
++{
++   int act_comp=0,num_packets=0,chained,dummy;
++   stbi__pic_packet packets[10];
++
++   if (!x) x = &dummy;
++   if (!y) y = &dummy;
++   if (!comp) comp = &dummy;
++
++   if (!stbi__pic_is4(s,"\x53\x80\xF6\x34")) {
++      stbi__rewind(s);
++      return 0;
++   }
++
++   stbi__skip(s, 88);
++
++   *x = stbi__get16be(s);
++   *y = stbi__get16be(s);
++   if (stbi__at_eof(s)) {
++      stbi__rewind( s);
++      return 0;
++   }
++   if ( (*x) != 0 && (1 << 28) / (*x) < (*y)) {
++      stbi__rewind( s );
++      return 0;
++   }
++
++   stbi__skip(s, 8);
++
++   do {
++      stbi__pic_packet *packet;
++
++      if (num_packets==sizeof(packets)/sizeof(packets[0]))
++         return 0;
++
++      packet = &packets[num_packets++];
++      chained = stbi__get8(s);
++      packet->size    = stbi__get8(s);
++      packet->type    = stbi__get8(s);
++      packet->channel = stbi__get8(s);
++      act_comp |= packet->channel;
++
++      if (stbi__at_eof(s)) {
++          stbi__rewind( s );
++          return 0;
++      }
++      if (packet->size != 8) {
++          stbi__rewind( s );
++          return 0;
++      }
++   } while (chained);
++
++   *comp = (act_comp & 0x10 ? 4 : 3);
++
++   return 1;
++}
++#endif
++
++// *************************************************************************************************
++// Portable Gray Map and Portable Pixel Map loader
++// by Ken Miller
++//
++// PGM: http://netpbm.sourceforge.net/doc/pgm.html
++// PPM: http://netpbm.sourceforge.net/doc/ppm.html
++//
++// Known limitations:
++//    Does not support comments in the header section
++//    Does not support ASCII image data (formats P2 and P3)
++//    Does not support 16-bit-per-channel
++
++#ifndef STBI_NO_PNM
++
++static int      stbi__pnm_test(stbi__context *s)
++{
++   char p, t;
++   p = (char) stbi__get8(s);
++   t = (char) stbi__get8(s);
++   if (p != 'P' || (t != '5' && t != '6')) {
++       stbi__rewind( s );
++       return 0;
++   }
++   return 1;
++}
++
++static void *stbi__pnm_load(stbi__context *s, int *x, int *y, int *comp, int req_comp, stbi__result_info *ri)
++{
++   stbi_uc *out;
++   STBI_NOTUSED(ri);
++
++   if (!stbi__pnm_info(s, (int *)&s->img_x, (int *)&s->img_y, (int *)&s->img_n))
++      return 0;
++
++   *x = s->img_x;
++   *y = s->img_y;
++   if (comp) *comp = s->img_n;
++
++   if (!stbi__mad3sizes_valid(s->img_n, s->img_x, s->img_y, 0))
++      return stbi__errpuc("too large", "PNM too large");
++
++   out = (stbi_uc *) stbi__malloc_mad3(s->img_n, s->img_x, s->img_y, 0);
++   if (!out) return stbi__errpuc("outofmem", "Out of memory");
++   stbi__getn(s, out, s->img_n * s->img_x * s->img_y);
++
++   if (req_comp && req_comp != s->img_n) {
++      out = stbi__convert_format(out, s->img_n, req_comp, s->img_x, s->img_y);
++      if (out == NULL) return out; // stbi__convert_format frees input on failure
++   }
++   return out;
++}
++
++static int      stbi__pnm_isspace(char c)
++{
++   return c == ' ' || c == '\t' || c == '\n' || c == '\v' || c == '\f' || c == '\r';
++}
++
++static void     stbi__pnm_skip_whitespace(stbi__context *s, char *c)
++{
++   for (;;) {
++      while (!stbi__at_eof(s) && stbi__pnm_isspace(*c))
++         *c = (char) stbi__get8(s);
++
++      if (stbi__at_eof(s) || *c != '#')
++         break;
++
++      while (!stbi__at_eof(s) && *c != '\n' && *c != '\r' )
++         *c = (char) stbi__get8(s);
++   }
++}
++
++static int      stbi__pnm_isdigit(char c)
++{
++   return c >= '0' && c <= '9';
++}
++
++static int      stbi__pnm_getinteger(stbi__context *s, char *c)
++{
++   int value = 0;
++
++   while (!stbi__at_eof(s) && stbi__pnm_isdigit(*c)) {
++      value = value*10 + (*c - '0');
++      *c = (char) stbi__get8(s);
++   }
++
++   return value;
++}
++
++static int      stbi__pnm_info(stbi__context *s, int *x, int *y, int *comp)
++{
++   int maxv, dummy;
++   char c, p, t;
++
++   if (!x) x = &dummy;
++   if (!y) y = &dummy;
++   if (!comp) comp = &dummy;
++
++   stbi__rewind(s);
++
++   // Get identifier
++   p = (char) stbi__get8(s);
++   t = (char) stbi__get8(s);
++   if (p != 'P' || (t != '5' && t != '6')) {
++       stbi__rewind(s);
++       return 0;
++   }
++
++   *comp = (t == '6') ? 3 : 1;  // '5' is 1-component .pgm; '6' is 3-component .ppm
++
++   c = (char) stbi__get8(s);
++   stbi__pnm_skip_whitespace(s, &c);
++
++   *x = stbi__pnm_getinteger(s, &c); // read width
++   stbi__pnm_skip_whitespace(s, &c);
++
++   *y = stbi__pnm_getinteger(s, &c); // read height
++   stbi__pnm_skip_whitespace(s, &c);
++
++   maxv = stbi__pnm_getinteger(s, &c);  // read max value
++
++   if (maxv > 255)
++      return stbi__err("max value > 255", "PPM image not 8-bit");
++   else
++      return 1;
++}
++#endif
++
++static int stbi__info_main(stbi__context *s, int *x, int *y, int *comp)
++{
++   #ifndef STBI_NO_JPEG
++   if (stbi__jpeg_info(s, x, y, comp)) return 1;
++   #endif
++
++   #ifndef STBI_NO_PNG
++   if (stbi__png_info(s, x, y, comp))  return 1;
++   #endif
++
++   #ifndef STBI_NO_GIF
++   if (stbi__gif_info(s, x, y, comp))  return 1;
++   #endif
++
++   #ifndef STBI_NO_BMP
++   if (stbi__bmp_info(s, x, y, comp))  return 1;
++   #endif
++
++   #ifndef STBI_NO_PSD
++   if (stbi__psd_info(s, x, y, comp))  return 1;
++   #endif
++
++   #ifndef STBI_NO_PIC
++   if (stbi__pic_info(s, x, y, comp))  return 1;
++   #endif
++
++   #ifndef STBI_NO_PNM
++   if (stbi__pnm_info(s, x, y, comp))  return 1;
++   #endif
++
++   #ifndef STBI_NO_HDR
++   if (stbi__hdr_info(s, x, y, comp))  return 1;
++   #endif
++
++   // test tga last because it's a crappy test!
++   #ifndef STBI_NO_TGA
++   if (stbi__tga_info(s, x, y, comp))
++       return 1;
++   #endif
++   return stbi__err("unknown image type", "Image not of any known type, or corrupt");
++}
++
++static int stbi__is_16_main(stbi__context *s)
++{
++   #ifndef STBI_NO_PNG
++   if (stbi__png_is16(s))  return 1;
++   #endif
++
++   #ifndef STBI_NO_PSD
++   if (stbi__psd_is16(s))  return 1;
++   #endif
++
++   return 0;
++}
++
++#ifndef STBI_NO_STDIO
++STBIDEF int stbi_info(char const *filename, int *x, int *y, int *comp)
++{
++    FILE *f = stbi__fopen(filename, "rb");
++    int result;
++    if (!f) return stbi__err("can't fopen", "Unable to open file");
++    result = stbi_info_from_file(f, x, y, comp);
++    fclose(f);
++    return result;
++}
++
++STBIDEF int stbi_info_from_file(FILE *f, int *x, int *y, int *comp)
++{
++   int r;
++   stbi__context s;
++   long pos = ftell(f);
++   stbi__start_file(&s, f);
++   r = stbi__info_main(&s,x,y,comp);
++   fseek(f,pos,SEEK_SET);
++   return r;
++}
++
++STBIDEF int stbi_is_16_bit(char const *filename)
++{
++    FILE *f = stbi__fopen(filename, "rb");
++    int result;
++    if (!f) return stbi__err("can't fopen", "Unable to open file");
++    result = stbi_is_16_bit_from_file(f);
++    fclose(f);
++    return result;
++}
++
++STBIDEF int stbi_is_16_bit_from_file(FILE *f)
++{
++   int r;
++   stbi__context s;
++   long pos = ftell(f);
++   stbi__start_file(&s, f);
++   r = stbi__is_16_main(&s);
++   fseek(f,pos,SEEK_SET);
++   return r;
++}
++#endif // !STBI_NO_STDIO
++
++STBIDEF int stbi_info_from_memory(stbi_uc const *buffer, int len, int *x, int *y, int *comp)
++{
++   stbi__context s;
++   stbi__start_mem(&s,buffer,len);
++   return stbi__info_main(&s,x,y,comp);
++}
++
++STBIDEF int stbi_info_from_callbacks(stbi_io_callbacks const *c, void *user, int *x, int *y, int *comp)
++{
++   stbi__context s;
++   stbi__start_callbacks(&s, (stbi_io_callbacks *) c, user);
++   return stbi__info_main(&s,x,y,comp);
++}
++
++STBIDEF int stbi_is_16_bit_from_memory(stbi_uc const *buffer, int len)
++{
++   stbi__context s;
++   stbi__start_mem(&s,buffer,len);
++   return stbi__is_16_main(&s);
++}
++
++STBIDEF int stbi_is_16_bit_from_callbacks(stbi_io_callbacks const *c, void *user)
++{
++   stbi__context s;
++   stbi__start_callbacks(&s, (stbi_io_callbacks *) c, user);
++   return stbi__is_16_main(&s);
++}
++
++#endif // STB_IMAGE_IMPLEMENTATION
++
++/*
++   revision history:
++      2.19  (2018-02-11) fix warning
++      2.18  (2018-01-30) fix warnings
++      2.17  (2018-01-29) change sbti__shiftsigned to avoid clang -O2 bug
++                         1-bit BMP
++                         *_is_16_bit api
++                         avoid warnings
++      2.16  (2017-07-23) all functions have 16-bit variants;
++                         STBI_NO_STDIO works again;
++                         compilation fixes;
++                         fix rounding in unpremultiply;
++                         optimize vertical flip;
++                         disable raw_len validation;
++                         documentation fixes
++      2.15  (2017-03-18) fix png-1,2,4 bug; now all Imagenet JPGs decode;
++                         warning fixes; disable run-time SSE detection on gcc;
++                         uniform handling of optional "return" values;
++                         thread-safe initialization of zlib tables
++      2.14  (2017-03-03) remove deprecated STBI_JPEG_OLD; fixes for Imagenet JPGs
++      2.13  (2016-11-29) add 16-bit API, only supported for PNG right now
++      2.12  (2016-04-02) fix typo in 2.11 PSD fix that caused crashes
++      2.11  (2016-04-02) allocate large structures on the stack
++                         remove white matting for transparent PSD
++                         fix reported channel count for PNG & BMP
++                         re-enable SSE2 in non-gcc 64-bit
++                         support RGB-formatted JPEG
++                         read 16-bit PNGs (only as 8-bit)
++      2.10  (2016-01-22) avoid warning introduced in 2.09 by STBI_REALLOC_SIZED
++      2.09  (2016-01-16) allow comments in PNM files
++                         16-bit-per-pixel TGA (not bit-per-component)
++                         info() for TGA could break due to .hdr handling
++                         info() for BMP to shares code instead of sloppy parse
++                         can use STBI_REALLOC_SIZED if allocator doesn't support realloc
++                         code cleanup
++      2.08  (2015-09-13) fix to 2.07 cleanup, reading RGB PSD as RGBA
++      2.07  (2015-09-13) fix compiler warnings
++                         partial animated GIF support
++                         limited 16-bpc PSD support
++                         #ifdef unused functions
++                         bug with < 92 byte PIC,PNM,HDR,TGA
++      2.06  (2015-04-19) fix bug where PSD returns wrong '*comp' value
++      2.05  (2015-04-19) fix bug in progressive JPEG handling, fix warning
++      2.04  (2015-04-15) try to re-enable SIMD on MinGW 64-bit
++      2.03  (2015-04-12) extra corruption checking (mmozeiko)
++                         stbi_set_flip_vertically_on_load (nguillemot)
++                         fix NEON support; fix mingw support
++      2.02  (2015-01-19) fix incorrect assert, fix warning
++      2.01  (2015-01-17) fix various warnings; suppress SIMD on gcc 32-bit without -msse2
++      2.00b (2014-12-25) fix STBI_MALLOC in progressive JPEG
++      2.00  (2014-12-25) optimize JPG, including x86 SSE2 & NEON SIMD (ryg)
++                         progressive JPEG (stb)
++                         PGM/PPM support (Ken Miller)
++                         STBI_MALLOC,STBI_REALLOC,STBI_FREE
++                         GIF bugfix -- seemingly never worked
++                         STBI_NO_*, STBI_ONLY_*
++      1.48  (2014-12-14) fix incorrectly-named assert()
++      1.47  (2014-12-14) 1/2/4-bit PNG support, both direct and paletted (Omar Cornut & stb)
++                         optimize PNG (ryg)
++                         fix bug in interlaced PNG with user-specified channel count (stb)
++      1.46  (2014-08-26)
++              fix broken tRNS chunk (colorkey-style transparency) in non-paletted PNG
++      1.45  (2014-08-16)
++              fix MSVC-ARM internal compiler error by wrapping malloc
++      1.44  (2014-08-07)
++              various warning fixes from Ronny Chevalier
++      1.43  (2014-07-15)
++              fix MSVC-only compiler problem in code changed in 1.42
++      1.42  (2014-07-09)
++              don't define _CRT_SECURE_NO_WARNINGS (affects user code)
++              fixes to stbi__cleanup_jpeg path
++              added STBI_ASSERT to avoid requiring assert.h
++      1.41  (2014-06-25)
++              fix search&replace from 1.36 that messed up comments/error messages
++      1.40  (2014-06-22)
++              fix gcc struct-initialization warning
++      1.39  (2014-06-15)
++              fix to TGA optimization when req_comp != number of components in TGA;
++              fix to GIF loading because BMP wasn't rewinding (whoops, no GIFs in my test suite)
++              add support for BMP version 5 (more ignored fields)
++      1.38  (2014-06-06)
++              suppress MSVC warnings on integer casts truncating values
++              fix accidental rename of 'skip' field of I/O
++      1.37  (2014-06-04)
++              remove duplicate typedef
++      1.36  (2014-06-03)
++              convert to header file single-file library
++              if de-iphone isn't set, load iphone images color-swapped instead of returning NULL
++      1.35  (2014-05-27)
++              various warnings
++              fix broken STBI_SIMD path
++              fix bug where stbi_load_from_file no longer left file pointer in correct place
++              fix broken non-easy path for 32-bit BMP (possibly never used)
++              TGA optimization by Arseny Kapoulkine
++      1.34  (unknown)
++              use STBI_NOTUSED in stbi__resample_row_generic(), fix one more leak in tga failure case
++      1.33  (2011-07-14)
++              make stbi_is_hdr work in STBI_NO_HDR (as specified), minor compiler-friendly improvements
++      1.32  (2011-07-13)
++              support for "info" function for all supported filetypes (SpartanJ)
++      1.31  (2011-06-20)
++              a few more leak fixes, bug in PNG handling (SpartanJ)
++      1.30  (2011-06-11)
++              added ability to load files via callbacks to accomidate custom input streams (Ben Wenger)
++              removed deprecated format-specific test/load functions
++              removed support for installable file formats (stbi_loader) -- would have been broken for IO callbacks anyway
++              error cases in bmp and tga give messages and don't leak (Raymond Barbiero, grisha)
++              fix inefficiency in decoding 32-bit BMP (David Woo)
++      1.29  (2010-08-16)
++              various warning fixes from Aurelien Pocheville
++      1.28  (2010-08-01)
++              fix bug in GIF palette transparency (SpartanJ)
++      1.27  (2010-08-01)
++              cast-to-stbi_uc to fix warnings
++      1.26  (2010-07-24)
++              fix bug in file buffering for PNG reported by SpartanJ
++      1.25  (2010-07-17)
++              refix trans_data warning (Won Chun)
++      1.24  (2010-07-12)
++              perf improvements reading from files on platforms with lock-heavy fgetc()
++              minor perf improvements for jpeg
++              deprecated type-specific functions so we'll get feedback if they're needed
++              attempt to fix trans_data warning (Won Chun)
++      1.23    fixed bug in iPhone support
++      1.22  (2010-07-10)
++              removed image *writing* support
++              stbi_info support from Jetro Lauha
++              GIF support from Jean-Marc Lienher
++              iPhone PNG-extensions from James Brown
++              warning-fixes from Nicolas Schulz and Janez Zemva (i.stbi__err. Janez (U+017D)emva)
++      1.21    fix use of 'stbi_uc' in header (reported by jon blow)
++      1.20    added support for Softimage PIC, by Tom Seddon
++      1.19    bug in interlaced PNG corruption check (found by ryg)
++      1.18  (2008-08-02)
++              fix a threading bug (local mutable static)
++      1.17    support interlaced PNG
++      1.16    major bugfix - stbi__convert_format converted one too many pixels
++      1.15    initialize some fields for thread safety
++      1.14    fix threadsafe conversion bug
++              header-file-only version (#define STBI_HEADER_FILE_ONLY before including)
++      1.13    threadsafe
++      1.12    const qualifiers in the API
++      1.11    Support installable IDCT, colorspace conversion routines
++      1.10    Fixes for 64-bit (don't use "unsigned long")
++              optimized upsampling by Fabian "ryg" Giesen
++      1.09    Fix format-conversion for PSD code (bad global variables!)
++      1.08    Thatcher Ulrich's PSD code integrated by Nicolas Schulz
++      1.07    attempt to fix C++ warning/errors again
++      1.06    attempt to fix C++ warning/errors again
++      1.05    fix TGA loading to return correct *comp and use good luminance calc
++      1.04    default float alpha is 1, not 255; use 'void *' for stbi_image_free
++      1.03    bugfixes to STBI_NO_STDIO, STBI_NO_HDR
++      1.02    support for (subset of) HDR files, float interface for preferred access to them
++      1.01    fix bug: possible bug in handling right-side up bmps... not sure
++              fix bug: the stbi__bmp_load() and stbi__tga_load() functions didn't work at all
++      1.00    interface to zlib that skips zlib header
++      0.99    correct handling of alpha in palette
++      0.98    TGA loader by lonesock; dynamically add loaders (untested)
++      0.97    jpeg errors on too large a file; also catch another malloc failure
++      0.96    fix detection of invalid v value - particleman@mollyrocket forum
++      0.95    during header scan, seek to markers in case of padding
++      0.94    STBI_NO_STDIO to disable stdio usage; rename all #defines the same
++      0.93    handle jpegtran output; verbose errors
++      0.92    read 4,8,16,24,32-bit BMP files of several formats
++      0.91    output 24-bit Windows 3.0 BMP files
++      0.90    fix a few more warnings; bump version number to approach 1.0
++      0.61    bugfixes due to Marc LeBlanc, Christopher Lloyd
++      0.60    fix compiling as c++
++      0.59    fix warnings: merge Dave Moore's -Wall fixes
++      0.58    fix bug: zlib uncompressed mode len/nlen was wrong endian
++      0.57    fix bug: jpg last huffman symbol before marker was >9 bits but less than 16 available
++      0.56    fix bug: zlib uncompressed mode len vs. nlen
++      0.55    fix bug: restart_interval not initialized to 0
++      0.54    allow NULL for 'int *comp'
++      0.53    fix bug in png 3->4; speedup png decoding
++      0.52    png handles req_comp=3,4 directly; minor cleanup; jpeg comments
++      0.51    obey req_comp requests, 1-component jpegs return as 1-component,
++              on 'test' only check type, not whether we support this variant
++      0.50  (2006-11-19)
++              first released version
++*/
++
++
++/*
++------------------------------------------------------------------------------
++This software is available under 2 licenses -- choose whichever you prefer.
++------------------------------------------------------------------------------
++ALTERNATIVE A - MIT License
++Copyright (c) 2017 Sean Barrett
++Permission is hereby granted, free of charge, to any person obtaining a copy of
++this software and associated documentation files (the "Software"), to deal in
++the Software without restriction, including without limitation the rights to
++use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++of the Software, and to permit persons to whom the Software is furnished to do
++so, subject to the following conditions:
++The above copyright notice and this permission notice shall be included in all
++copies or substantial portions of the Software.
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
++SOFTWARE.
++------------------------------------------------------------------------------
++ALTERNATIVE B - Public Domain (www.unlicense.org)
++This is free and unencumbered software released into the public domain.
++Anyone is free to copy, modify, publish, use, compile, sell, or distribute this
++software, either in source code form or as a compiled binary, for any purpose,
++commercial or non-commercial, and by any means.
++In jurisdictions that recognize copyright laws, the author or authors of this
++software dedicate any and all copyright interest in the software to the public
++domain. We make this dedication for the benefit of the public at large and to
++the detriment of our heirs and successors. We intend this dedication to be an
++overt act of relinquishment in perpetuity of all present and future rights to
++this software under copyright law.
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
++AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
++ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++------------------------------------------------------------------------------
++*/
+diff --git a/scripts/pic2logo-include/stb_image/stb_image_resize.h b/scripts/pic2logo-include/stb_image/stb_image_resize.h
+new file mode 100644
+index 000000000..031ca99dc
+--- /dev/null
++++ b/scripts/pic2logo-include/stb_image/stb_image_resize.h
+@@ -0,0 +1,2627 @@
++/* stb_image_resize - v0.95 - public domain image resizing
++   by Jorge L Rodriguez (@VinoBS) - 2014
++   http://github.com/nothings/stb
++
++   Written with emphasis on usability, portability, and efficiency. (No
++   SIMD or threads, so it be easily outperformed by libs that use those.)
++   Only scaling and translation is supported, no rotations or shears.
++   Easy API downsamples w/Mitchell filter, upsamples w/cubic interpolation.
++
++   COMPILING & LINKING
++      In one C/C++ file that #includes this file, do this:
++         #define STB_IMAGE_RESIZE_IMPLEMENTATION
++      before the #include. That will create the implementation in that file.
++
++   QUICKSTART
++      stbir_resize_uint8(      input_pixels , in_w , in_h , 0,
++                               output_pixels, out_w, out_h, 0, num_channels)
++      stbir_resize_float(...)
++      stbir_resize_uint8_srgb( input_pixels , in_w , in_h , 0,
++                               output_pixels, out_w, out_h, 0,
++                               num_channels , alpha_chan  , 0)
++      stbir_resize_uint8_srgb_edgemode(
++                               input_pixels , in_w , in_h , 0, 
++                               output_pixels, out_w, out_h, 0, 
++                               num_channels , alpha_chan  , 0, STBIR_EDGE_CLAMP)
++                                                            // WRAP/REFLECT/ZERO
++
++   FULL API
++      See the "header file" section of the source for API documentation.
++
++   ADDITIONAL DOCUMENTATION
++
++      SRGB & FLOATING POINT REPRESENTATION
++         The sRGB functions presume IEEE floating point. If you do not have
++         IEEE floating point, define STBIR_NON_IEEE_FLOAT. This will use
++         a slower implementation.
++
++      MEMORY ALLOCATION
++         The resize functions here perform a single memory allocation using
++         malloc. To control the memory allocation, before the #include that
++         triggers the implementation, do:
++
++            #define STBIR_MALLOC(size,context) ...
++            #define STBIR_FREE(ptr,context)   ...
++
++         Each resize function makes exactly one call to malloc/free, so to use
++         temp memory, store the temp memory in the context and return that.
++
++      ASSERT
++         Define STBIR_ASSERT(boolval) to override assert() and not use assert.h
++
++      OPTIMIZATION
++         Define STBIR_SATURATE_INT to compute clamp values in-range using
++         integer operations instead of float operations. This may be faster
++         on some platforms.
++
++      DEFAULT FILTERS
++         For functions which don't provide explicit control over what filters
++         to use, you can change the compile-time defaults with
++
++            #define STBIR_DEFAULT_FILTER_UPSAMPLE     STBIR_FILTER_something
++            #define STBIR_DEFAULT_FILTER_DOWNSAMPLE   STBIR_FILTER_something
++
++         See stbir_filter in the header-file section for the list of filters.
++
++      NEW FILTERS
++         A number of 1D filter kernels are used. For a list of
++         supported filters see the stbir_filter enum. To add a new filter,
++         write a filter function and add it to stbir__filter_info_table.
++
++      PROGRESS
++         For interactive use with slow resize operations, you can install
++         a progress-report callback:
++
++            #define STBIR_PROGRESS_REPORT(val)   some_func(val)
++
++         The parameter val is a float which goes from 0 to 1 as progress is made.
++
++         For example:
++
++            static void my_progress_report(float progress);
++            #define STBIR_PROGRESS_REPORT(val) my_progress_report(val)
++
++            #define STB_IMAGE_RESIZE_IMPLEMENTATION
++            #include "stb_image_resize.h"
++
++            static void my_progress_report(float progress)
++            {
++               printf("Progress: %f%%\n", progress*100);
++            }
++
++      MAX CHANNELS
++         If your image has more than 64 channels, define STBIR_MAX_CHANNELS
++         to the max you'll have.
++
++      ALPHA CHANNEL
++         Most of the resizing functions provide the ability to control how
++         the alpha channel of an image is processed. The important things
++         to know about this:
++
++         1. The best mathematically-behaved version of alpha to use is
++         called "premultiplied alpha", in which the other color channels
++         have had the alpha value multiplied in. If you use premultiplied
++         alpha, linear filtering (such as image resampling done by this
++         library, or performed in texture units on GPUs) does the "right
++         thing". While premultiplied alpha is standard in the movie CGI
++         industry, it is still uncommon in the videogame/real-time world.
++
++         If you linearly filter non-premultiplied alpha, strange effects
++         occur. (For example, the 50/50 average of 99% transparent bright green
++         and 1% transparent black produces 50% transparent dark green when
++         non-premultiplied, whereas premultiplied it produces 50%
++         transparent near-black. The former introduces green energy
++         that doesn't exist in the source image.)
++
++         2. Artists should not edit premultiplied-alpha images; artists
++         want non-premultiplied alpha images. Thus, art tools generally output
++         non-premultiplied alpha images.
++
++         3. You will get best results in most cases by converting images
++         to premultiplied alpha before processing them mathematically.
++
++         4. If you pass the flag STBIR_FLAG_ALPHA_PREMULTIPLIED, the
++         resizer does not do anything special for the alpha channel;
++         it is resampled identically to other channels. This produces
++         the correct results for premultiplied-alpha images, but produces
++         less-than-ideal results for non-premultiplied-alpha images.
++
++         5. If you do not pass the flag STBIR_FLAG_ALPHA_PREMULTIPLIED,
++         then the resizer weights the contribution of input pixels
++         based on their alpha values, or, equivalently, it multiplies
++         the alpha value into the color channels, resamples, then divides
++         by the resultant alpha value. Input pixels which have alpha=0 do
++         not contribute at all to output pixels unless _all_ of the input
++         pixels affecting that output pixel have alpha=0, in which case
++         the result for that pixel is the same as it would be without
++         STBIR_FLAG_ALPHA_PREMULTIPLIED. However, this is only true for
++         input images in integer formats. For input images in float format,
++         input pixels with alpha=0 have no effect, and output pixels
++         which have alpha=0 will be 0 in all channels. (For float images,
++         you can manually achieve the same result by adding a tiny epsilon
++         value to the alpha channel of every image, and then subtracting
++         or clamping it at the end.)
++
++         6. You can suppress the behavior described in #5 and make
++         all-0-alpha pixels have 0 in all channels by #defining
++         STBIR_NO_ALPHA_EPSILON.
++
++         7. You can separately control whether the alpha channel is
++         interpreted as linear or affected by the colorspace. By default
++         it is linear; you almost never want to apply the colorspace.
++         (For example, graphics hardware does not apply sRGB conversion
++         to the alpha channel.)
++
++   CONTRIBUTORS
++      Jorge L Rodriguez: Implementation
++      Sean Barrett: API design, optimizations
++      Aras Pranckevicius: bugfix
++      Nathan Reed: warning fixes
++
++   REVISIONS
++      0.95 (2017-07-23) fixed warnings
++      0.94 (2017-03-18) fixed warnings
++      0.93 (2017-03-03) fixed bug with certain combinations of heights
++      0.92 (2017-01-02) fix integer overflow on large (>2GB) images
++      0.91 (2016-04-02) fix warnings; fix handling of subpixel regions
++      0.90 (2014-09-17) first released version
++
++   LICENSE
++     See end of file for license information.
++
++   TODO
++      Don't decode all of the image data when only processing a partial tile
++      Don't use full-width decode buffers when only processing a partial tile
++      When processing wide images, break processing into tiles so data fits in L1 cache
++      Installable filters?
++      Resize that respects alpha test coverage
++         (Reference code: FloatImage::alphaTestCoverage and FloatImage::scaleAlphaToCoverage:
++         https://code.google.com/p/nvidia-texture-tools/source/browse/trunk/src/nvimage/FloatImage.cpp )
++*/
++
++#ifndef STBIR_INCLUDE_STB_IMAGE_RESIZE_H
++#define STBIR_INCLUDE_STB_IMAGE_RESIZE_H
++
++#ifdef _MSC_VER
++typedef unsigned char  stbir_uint8;
++typedef unsigned short stbir_uint16;
++typedef unsigned int   stbir_uint32;
++#else
++#include <stdint.h>
++typedef uint8_t  stbir_uint8;
++typedef uint16_t stbir_uint16;
++typedef uint32_t stbir_uint32;
++#endif
++
++#ifdef STB_IMAGE_RESIZE_STATIC
++#define STBIRDEF static
++#else
++#ifdef __cplusplus
++#define STBIRDEF extern "C"
++#else
++#define STBIRDEF extern
++#endif
++#endif
++
++
++//////////////////////////////////////////////////////////////////////////////
++//
++// Easy-to-use API:
++//
++//     * "input pixels" points to an array of image data with 'num_channels' channels (e.g. RGB=3, RGBA=4)
++//     * input_w is input image width (x-axis), input_h is input image height (y-axis)
++//     * stride is the offset between successive rows of image data in memory, in bytes. you can
++//       specify 0 to mean packed continuously in memory
++//     * alpha channel is treated identically to other channels.
++//     * colorspace is linear or sRGB as specified by function name
++//     * returned result is 1 for success or 0 in case of an error.
++//       #define STBIR_ASSERT() to trigger an assert on parameter validation errors.
++//     * Memory required grows approximately linearly with input and output size, but with
++//       discontinuities at input_w == output_w and input_h == output_h.
++//     * These functions use a "default" resampling filter defined at compile time. To change the filter,
++//       you can change the compile-time defaults by #defining STBIR_DEFAULT_FILTER_UPSAMPLE
++//       and STBIR_DEFAULT_FILTER_DOWNSAMPLE, or you can use the medium-complexity API.
++
++STBIRDEF int stbir_resize_uint8(     const unsigned char *input_pixels , int input_w , int input_h , int input_stride_in_bytes,
++                                           unsigned char *output_pixels, int output_w, int output_h, int output_stride_in_bytes,
++                                     int num_channels);
++
++STBIRDEF int stbir_resize_float(     const float *input_pixels , int input_w , int input_h , int input_stride_in_bytes,
++                                           float *output_pixels, int output_w, int output_h, int output_stride_in_bytes,
++                                     int num_channels);
++
++
++// The following functions interpret image data as gamma-corrected sRGB. 
++// Specify STBIR_ALPHA_CHANNEL_NONE if you have no alpha channel,
++// or otherwise provide the index of the alpha channel. Flags value
++// of 0 will probably do the right thing if you're not sure what
++// the flags mean.
++
++#define STBIR_ALPHA_CHANNEL_NONE       -1
++
++// Set this flag if your texture has premultiplied alpha. Otherwise, stbir will
++// use alpha-weighted resampling (effectively premultiplying, resampling,
++// then unpremultiplying).
++#define STBIR_FLAG_ALPHA_PREMULTIPLIED    (1 << 0)
++// The specified alpha channel should be handled as gamma-corrected value even
++// when doing sRGB operations.
++#define STBIR_FLAG_ALPHA_USES_COLORSPACE  (1 << 1)
++
++STBIRDEF int stbir_resize_uint8_srgb(const unsigned char *input_pixels , int input_w , int input_h , int input_stride_in_bytes,
++                                           unsigned char *output_pixels, int output_w, int output_h, int output_stride_in_bytes,
++                                     int num_channels, int alpha_channel, int flags);
++
++
++typedef enum
++{
++    STBIR_EDGE_CLAMP   = 1,
++    STBIR_EDGE_REFLECT = 2,
++    STBIR_EDGE_WRAP    = 3,
++    STBIR_EDGE_ZERO    = 4,
++} stbir_edge;
++
++// This function adds the ability to specify how requests to sample off the edge of the image are handled.
++STBIRDEF int stbir_resize_uint8_srgb_edgemode(const unsigned char *input_pixels , int input_w , int input_h , int input_stride_in_bytes,
++                                                    unsigned char *output_pixels, int output_w, int output_h, int output_stride_in_bytes,
++                                              int num_channels, int alpha_channel, int flags,
++                                              stbir_edge edge_wrap_mode);
++
++//////////////////////////////////////////////////////////////////////////////
++//
++// Medium-complexity API
++//
++// This extends the easy-to-use API as follows:
++//
++//     * Alpha-channel can be processed separately
++//       * If alpha_channel is not STBIR_ALPHA_CHANNEL_NONE
++//         * Alpha channel will not be gamma corrected (unless flags&STBIR_FLAG_GAMMA_CORRECT)
++//         * Filters will be weighted by alpha channel (unless flags&STBIR_FLAG_ALPHA_PREMULTIPLIED)
++//     * Filter can be selected explicitly
++//     * uint16 image type
++//     * sRGB colorspace available for all types
++//     * context parameter for passing to STBIR_MALLOC
++
++typedef enum
++{
++    STBIR_FILTER_DEFAULT      = 0,  // use same filter type that easy-to-use API chooses
++    STBIR_FILTER_BOX          = 1,  // A trapezoid w/1-pixel wide ramps, same result as box for integer scale ratios
++    STBIR_FILTER_TRIANGLE     = 2,  // On upsampling, produces same results as bilinear texture filtering
++    STBIR_FILTER_CUBICBSPLINE = 3,  // The cubic b-spline (aka Mitchell-Netrevalli with B=1,C=0), gaussian-esque
++    STBIR_FILTER_CATMULLROM   = 4,  // An interpolating cubic spline
++    STBIR_FILTER_MITCHELL     = 5,  // Mitchell-Netrevalli filter with B=1/3, C=1/3
++} stbir_filter;
++
++typedef enum
++{
++    STBIR_COLORSPACE_LINEAR,
++    STBIR_COLORSPACE_SRGB,
++
++    STBIR_MAX_COLORSPACES,
++} stbir_colorspace;
++
++// The following functions are all identical except for the type of the image data
++
++STBIRDEF int stbir_resize_uint8_generic( const unsigned char *input_pixels , int input_w , int input_h , int input_stride_in_bytes,
++                                               unsigned char *output_pixels, int output_w, int output_h, int output_stride_in_bytes,
++                                         int num_channels, int alpha_channel, int flags,
++                                         stbir_edge edge_wrap_mode, stbir_filter filter, stbir_colorspace space, 
++                                         void *alloc_context);
++
++STBIRDEF int stbir_resize_uint16_generic(const stbir_uint16 *input_pixels  , int input_w , int input_h , int input_stride_in_bytes,
++                                               stbir_uint16 *output_pixels , int output_w, int output_h, int output_stride_in_bytes,
++                                         int num_channels, int alpha_channel, int flags,
++                                         stbir_edge edge_wrap_mode, stbir_filter filter, stbir_colorspace space, 
++                                         void *alloc_context);
++
++STBIRDEF int stbir_resize_float_generic( const float *input_pixels         , int input_w , int input_h , int input_stride_in_bytes,
++                                               float *output_pixels        , int output_w, int output_h, int output_stride_in_bytes,
++                                         int num_channels, int alpha_channel, int flags,
++                                         stbir_edge edge_wrap_mode, stbir_filter filter, stbir_colorspace space, 
++                                         void *alloc_context);
++
++
++
++//////////////////////////////////////////////////////////////////////////////
++//
++// Full-complexity API
++//
++// This extends the medium API as follows:
++//
++//       * uint32 image type
++//     * not typesafe
++//     * separate filter types for each axis
++//     * separate edge modes for each axis
++//     * can specify scale explicitly for subpixel correctness
++//     * can specify image source tile using texture coordinates
++
++typedef enum
++{
++    STBIR_TYPE_UINT8 ,
++    STBIR_TYPE_UINT16,
++    STBIR_TYPE_UINT32,
++    STBIR_TYPE_FLOAT ,
++
++    STBIR_MAX_TYPES
++} stbir_datatype;
++
++STBIRDEF int stbir_resize(         const void *input_pixels , int input_w , int input_h , int input_stride_in_bytes,
++                                         void *output_pixels, int output_w, int output_h, int output_stride_in_bytes,
++                                   stbir_datatype datatype,
++                                   int num_channels, int alpha_channel, int flags,
++                                   stbir_edge edge_mode_horizontal, stbir_edge edge_mode_vertical, 
++                                   stbir_filter filter_horizontal,  stbir_filter filter_vertical,
++                                   stbir_colorspace space, void *alloc_context);
++
++STBIRDEF int stbir_resize_subpixel(const void *input_pixels , int input_w , int input_h , int input_stride_in_bytes,
++                                         void *output_pixels, int output_w, int output_h, int output_stride_in_bytes,
++                                   stbir_datatype datatype,
++                                   int num_channels, int alpha_channel, int flags,
++                                   stbir_edge edge_mode_horizontal, stbir_edge edge_mode_vertical, 
++                                   stbir_filter filter_horizontal,  stbir_filter filter_vertical,
++                                   stbir_colorspace space, void *alloc_context,
++                                   float x_scale, float y_scale,
++                                   float x_offset, float y_offset);
++
++STBIRDEF int stbir_resize_region(  const void *input_pixels , int input_w , int input_h , int input_stride_in_bytes,
++                                         void *output_pixels, int output_w, int output_h, int output_stride_in_bytes,
++                                   stbir_datatype datatype,
++                                   int num_channels, int alpha_channel, int flags,
++                                   stbir_edge edge_mode_horizontal, stbir_edge edge_mode_vertical, 
++                                   stbir_filter filter_horizontal,  stbir_filter filter_vertical,
++                                   stbir_colorspace space, void *alloc_context,
++                                   float s0, float t0, float s1, float t1);
++// (s0, t0) & (s1, t1) are the top-left and bottom right corner (uv addressing style: [0, 1]x[0, 1]) of a region of the input image to use.
++
++//
++//
++////   end header file   /////////////////////////////////////////////////////
++#endif // STBIR_INCLUDE_STB_IMAGE_RESIZE_H
++
++
++
++
++
++#ifdef STB_IMAGE_RESIZE_IMPLEMENTATION
++
++#ifndef STBIR_ASSERT
++#include <assert.h>
++#define STBIR_ASSERT(x) assert(x)
++#endif
++
++// For memset
++#include <string.h>
++
++#include <math.h>
++
++#ifndef STBIR_MALLOC
++#include <stdlib.h>
++// use comma operator to evaluate c, to avoid "unused parameter" warnings
++#define STBIR_MALLOC(size,c) ((void)(c), malloc(size))
++#define STBIR_FREE(ptr,c)    ((void)(c), free(ptr))
++#endif
++
++#ifndef _MSC_VER
++#ifdef __cplusplus
++#define stbir__inline inline
++#else
++#define stbir__inline
++#endif
++#else
++#define stbir__inline __forceinline
++#endif
++
++
++// should produce compiler error if size is wrong
++typedef unsigned char stbir__validate_uint32[sizeof(stbir_uint32) == 4 ? 1 : -1];
++
++#ifdef _MSC_VER
++#define STBIR__NOTUSED(v)  (void)(v)
++#else
++#define STBIR__NOTUSED(v)  (void)sizeof(v)
++#endif
++
++#define STBIR__ARRAY_SIZE(a) (sizeof((a))/sizeof((a)[0]))
++
++#ifndef STBIR_DEFAULT_FILTER_UPSAMPLE
++#define STBIR_DEFAULT_FILTER_UPSAMPLE    STBIR_FILTER_CATMULLROM
++#endif
++
++#ifndef STBIR_DEFAULT_FILTER_DOWNSAMPLE
++#define STBIR_DEFAULT_FILTER_DOWNSAMPLE  STBIR_FILTER_MITCHELL
++#endif
++
++#ifndef STBIR_PROGRESS_REPORT
++#define STBIR_PROGRESS_REPORT(float_0_to_1)
++#endif
++
++#ifndef STBIR_MAX_CHANNELS
++#define STBIR_MAX_CHANNELS 64
++#endif
++
++#if STBIR_MAX_CHANNELS > 65536
++#error "Too many channels; STBIR_MAX_CHANNELS must be no more than 65536."
++// because we store the indices in 16-bit variables
++#endif
++
++// This value is added to alpha just before premultiplication to avoid
++// zeroing out color values. It is equivalent to 2^-80. If you don't want
++// that behavior (it may interfere if you have floating point images with
++// very small alpha values) then you can define STBIR_NO_ALPHA_EPSILON to
++// disable it.
++#ifndef STBIR_ALPHA_EPSILON
++#define STBIR_ALPHA_EPSILON ((float)1 / (1 << 20) / (1 << 20) / (1 << 20) / (1 << 20))
++#endif
++
++
++
++#ifdef _MSC_VER
++#define STBIR__UNUSED_PARAM(v)  (void)(v)
++#else
++#define STBIR__UNUSED_PARAM(v)  (void)sizeof(v)
++#endif
++
++// must match stbir_datatype
++static unsigned char stbir__type_size[] = {
++    1, // STBIR_TYPE_UINT8
++    2, // STBIR_TYPE_UINT16
++    4, // STBIR_TYPE_UINT32
++    4, // STBIR_TYPE_FLOAT
++};
++
++// Kernel function centered at 0
++typedef float (stbir__kernel_fn)(float x, float scale);
++typedef float (stbir__support_fn)(float scale);
++
++typedef struct
++{
++    stbir__kernel_fn* kernel;
++    stbir__support_fn* support;
++} stbir__filter_info;
++
++// When upsampling, the contributors are which source pixels contribute.
++// When downsampling, the contributors are which destination pixels are contributed to.
++typedef struct
++{
++    int n0; // First contributing pixel
++    int n1; // Last contributing pixel
++} stbir__contributors;
++
++typedef struct
++{
++    const void* input_data;
++    int input_w;
++    int input_h;
++    int input_stride_bytes;
++
++    void* output_data;
++    int output_w;
++    int output_h;
++    int output_stride_bytes;
++
++    float s0, t0, s1, t1;
++
++    float horizontal_shift; // Units: output pixels
++    float vertical_shift;   // Units: output pixels
++    float horizontal_scale;
++    float vertical_scale;
++
++    int channels;
++    int alpha_channel;
++    stbir_uint32 flags;
++    stbir_datatype type;
++    stbir_filter horizontal_filter;
++    stbir_filter vertical_filter;
++    stbir_edge edge_horizontal;
++    stbir_edge edge_vertical;
++    stbir_colorspace colorspace;
++
++    stbir__contributors* horizontal_contributors;
++    float* horizontal_coefficients;
++
++    stbir__contributors* vertical_contributors;
++    float* vertical_coefficients;
++
++    int decode_buffer_pixels;
++    float* decode_buffer;
++
++    float* horizontal_buffer;
++
++    // cache these because ceil/floor are inexplicably showing up in profile
++    int horizontal_coefficient_width;
++    int vertical_coefficient_width;
++    int horizontal_filter_pixel_width;
++    int vertical_filter_pixel_width;
++    int horizontal_filter_pixel_margin;
++    int vertical_filter_pixel_margin;
++    int horizontal_num_contributors;
++    int vertical_num_contributors;
++
++    int ring_buffer_length_bytes;   // The length of an individual entry in the ring buffer. The total number of ring buffers is stbir__get_filter_pixel_width(filter)
++    int ring_buffer_num_entries;    // Total number of entries in the ring buffer.
++    int ring_buffer_first_scanline;
++    int ring_buffer_last_scanline;
++    int ring_buffer_begin_index;    // first_scanline is at this index in the ring buffer
++    float* ring_buffer;
++
++    float* encode_buffer; // A temporary buffer to store floats so we don't lose precision while we do multiply-adds.
++
++    int horizontal_contributors_size;
++    int horizontal_coefficients_size;
++    int vertical_contributors_size;
++    int vertical_coefficients_size;
++    int decode_buffer_size;
++    int horizontal_buffer_size;
++    int ring_buffer_size;
++    int encode_buffer_size;
++} stbir__info;
++
++
++static const float stbir__max_uint8_as_float  = 255.0f;
++static const float stbir__max_uint16_as_float = 65535.0f;
++static const double stbir__max_uint32_as_float = 4294967295.0;
++
++
++static stbir__inline int stbir__min(int a, int b)
++{
++    return a < b ? a : b;
++}
++
++static stbir__inline float stbir__saturate(float x)
++{
++    if (x < 0)
++        return 0;
++
++    if (x > 1)
++        return 1;
++
++    return x;
++}
++
++#ifdef STBIR_SATURATE_INT
++static stbir__inline stbir_uint8 stbir__saturate8(int x)
++{
++    if ((unsigned int) x <= 255)
++        return x;
++
++    if (x < 0)
++        return 0;
++
++    return 255;
++}
++
++static stbir__inline stbir_uint16 stbir__saturate16(int x)
++{
++    if ((unsigned int) x <= 65535)
++        return x;
++
++    if (x < 0)
++        return 0;
++
++    return 65535;
++}
++#endif
++
++static float stbir__srgb_uchar_to_linear_float[256] = {
++    0.000000f, 0.000304f, 0.000607f, 0.000911f, 0.001214f, 0.001518f, 0.001821f, 0.002125f, 0.002428f, 0.002732f, 0.003035f,
++    0.003347f, 0.003677f, 0.004025f, 0.004391f, 0.004777f, 0.005182f, 0.005605f, 0.006049f, 0.006512f, 0.006995f, 0.007499f,
++    0.008023f, 0.008568f, 0.009134f, 0.009721f, 0.010330f, 0.010960f, 0.011612f, 0.012286f, 0.012983f, 0.013702f, 0.014444f,
++    0.015209f, 0.015996f, 0.016807f, 0.017642f, 0.018500f, 0.019382f, 0.020289f, 0.021219f, 0.022174f, 0.023153f, 0.024158f,
++    0.025187f, 0.026241f, 0.027321f, 0.028426f, 0.029557f, 0.030713f, 0.031896f, 0.033105f, 0.034340f, 0.035601f, 0.036889f,
++    0.038204f, 0.039546f, 0.040915f, 0.042311f, 0.043735f, 0.045186f, 0.046665f, 0.048172f, 0.049707f, 0.051269f, 0.052861f,
++    0.054480f, 0.056128f, 0.057805f, 0.059511f, 0.061246f, 0.063010f, 0.064803f, 0.066626f, 0.068478f, 0.070360f, 0.072272f,
++    0.074214f, 0.076185f, 0.078187f, 0.080220f, 0.082283f, 0.084376f, 0.086500f, 0.088656f, 0.090842f, 0.093059f, 0.095307f,
++    0.097587f, 0.099899f, 0.102242f, 0.104616f, 0.107023f, 0.109462f, 0.111932f, 0.114435f, 0.116971f, 0.119538f, 0.122139f,
++    0.124772f, 0.127438f, 0.130136f, 0.132868f, 0.135633f, 0.138432f, 0.141263f, 0.144128f, 0.147027f, 0.149960f, 0.152926f,
++    0.155926f, 0.158961f, 0.162029f, 0.165132f, 0.168269f, 0.171441f, 0.174647f, 0.177888f, 0.181164f, 0.184475f, 0.187821f,
++    0.191202f, 0.194618f, 0.198069f, 0.201556f, 0.205079f, 0.208637f, 0.212231f, 0.215861f, 0.219526f, 0.223228f, 0.226966f,
++    0.230740f, 0.234551f, 0.238398f, 0.242281f, 0.246201f, 0.250158f, 0.254152f, 0.258183f, 0.262251f, 0.266356f, 0.270498f,
++    0.274677f, 0.278894f, 0.283149f, 0.287441f, 0.291771f, 0.296138f, 0.300544f, 0.304987f, 0.309469f, 0.313989f, 0.318547f,
++    0.323143f, 0.327778f, 0.332452f, 0.337164f, 0.341914f, 0.346704f, 0.351533f, 0.356400f, 0.361307f, 0.366253f, 0.371238f,
++    0.376262f, 0.381326f, 0.386430f, 0.391573f, 0.396755f, 0.401978f, 0.407240f, 0.412543f, 0.417885f, 0.423268f, 0.428691f,
++    0.434154f, 0.439657f, 0.445201f, 0.450786f, 0.456411f, 0.462077f, 0.467784f, 0.473532f, 0.479320f, 0.485150f, 0.491021f,
++    0.496933f, 0.502887f, 0.508881f, 0.514918f, 0.520996f, 0.527115f, 0.533276f, 0.539480f, 0.545725f, 0.552011f, 0.558340f,
++    0.564712f, 0.571125f, 0.577581f, 0.584078f, 0.590619f, 0.597202f, 0.603827f, 0.610496f, 0.617207f, 0.623960f, 0.630757f,
++    0.637597f, 0.644480f, 0.651406f, 0.658375f, 0.665387f, 0.672443f, 0.679543f, 0.686685f, 0.693872f, 0.701102f, 0.708376f,
++    0.715694f, 0.723055f, 0.730461f, 0.737911f, 0.745404f, 0.752942f, 0.760525f, 0.768151f, 0.775822f, 0.783538f, 0.791298f,
++    0.799103f, 0.806952f, 0.814847f, 0.822786f, 0.830770f, 0.838799f, 0.846873f, 0.854993f, 0.863157f, 0.871367f, 0.879622f,
++    0.887923f, 0.896269f, 0.904661f, 0.913099f, 0.921582f, 0.930111f, 0.938686f, 0.947307f, 0.955974f, 0.964686f, 0.973445f,
++    0.982251f, 0.991102f, 1.0f
++};
++
++static float stbir__srgb_to_linear(float f)
++{
++    if (f <= 0.04045f)
++        return f / 12.92f;
++    else
++        return (float)pow((f + 0.055f) / 1.055f, 2.4f);
++}
++
++static float stbir__linear_to_srgb(float f)
++{
++    if (f <= 0.0031308f)
++        return f * 12.92f;
++    else
++        return 1.055f * (float)pow(f, 1 / 2.4f) - 0.055f;
++}
++
++#ifndef STBIR_NON_IEEE_FLOAT
++// From https://gist.github.com/rygorous/2203834
++
++typedef union
++{
++    stbir_uint32 u;
++    float f;
++} stbir__FP32;
++
++static const stbir_uint32 fp32_to_srgb8_tab4[104] = {
++    0x0073000d, 0x007a000d, 0x0080000d, 0x0087000d, 0x008d000d, 0x0094000d, 0x009a000d, 0x00a1000d,
++    0x00a7001a, 0x00b4001a, 0x00c1001a, 0x00ce001a, 0x00da001a, 0x00e7001a, 0x00f4001a, 0x0101001a,
++    0x010e0033, 0x01280033, 0x01410033, 0x015b0033, 0x01750033, 0x018f0033, 0x01a80033, 0x01c20033,
++    0x01dc0067, 0x020f0067, 0x02430067, 0x02760067, 0x02aa0067, 0x02dd0067, 0x03110067, 0x03440067,
++    0x037800ce, 0x03df00ce, 0x044600ce, 0x04ad00ce, 0x051400ce, 0x057b00c5, 0x05dd00bc, 0x063b00b5,
++    0x06970158, 0x07420142, 0x07e30130, 0x087b0120, 0x090b0112, 0x09940106, 0x0a1700fc, 0x0a9500f2,
++    0x0b0f01cb, 0x0bf401ae, 0x0ccb0195, 0x0d950180, 0x0e56016e, 0x0f0d015e, 0x0fbc0150, 0x10630143,
++    0x11070264, 0x1238023e, 0x1357021d, 0x14660201, 0x156601e9, 0x165a01d3, 0x174401c0, 0x182401af,
++    0x18fe0331, 0x1a9602fe, 0x1c1502d2, 0x1d7e02ad, 0x1ed4028d, 0x201a0270, 0x21520256, 0x227d0240,
++    0x239f0443, 0x25c003fe, 0x27bf03c4, 0x29a10392, 0x2b6a0367, 0x2d1d0341, 0x2ebe031f, 0x304d0300,
++    0x31d105b0, 0x34a80555, 0x37520507, 0x39d504c5, 0x3c37048b, 0x3e7c0458, 0x40a8042a, 0x42bd0401,
++    0x44c20798, 0x488e071e, 0x4c1c06b6, 0x4f76065d, 0x52a50610, 0x55ac05cc, 0x5892058f, 0x5b590559,
++    0x5e0c0a23, 0x631c0980, 0x67db08f6, 0x6c55087f, 0x70940818, 0x74a007bd, 0x787d076c, 0x7c330723,
++};
++ 
++static stbir_uint8 stbir__linear_to_srgb_uchar(float in)
++{
++    static const stbir__FP32 almostone = { 0x3f7fffff }; // 1-eps
++    static const stbir__FP32 minval = { (127-13) << 23 };
++    stbir_uint32 tab,bias,scale,t;
++    stbir__FP32 f;
++ 
++    // Clamp to [2^(-13), 1-eps]; these two values map to 0 and 1, respectively.
++    // The tests are carefully written so that NaNs map to 0, same as in the reference
++    // implementation.
++    if (!(in > minval.f)) // written this way to catch NaNs
++        in = minval.f;
++    if (in > almostone.f)
++        in = almostone.f;
++ 
++    // Do the table lookup and unpack bias, scale
++    f.f = in;
++    tab = fp32_to_srgb8_tab4[(f.u - minval.u) >> 20];
++    bias = (tab >> 16) << 9;
++    scale = tab & 0xffff;
++ 
++    // Grab next-highest mantissa bits and perform linear interpolation
++    t = (f.u >> 12) & 0xff;
++    return (unsigned char) ((bias + scale*t) >> 16);
++}
++
++#else
++// sRGB transition values, scaled by 1<<28
++static int stbir__srgb_offset_to_linear_scaled[256] =
++{
++            0,     40738,    122216,    203693,    285170,    366648,    448125,    529603,
++       611080,    692557,    774035,    855852,    942009,   1033024,   1128971,   1229926,
++      1335959,   1447142,   1563542,   1685229,   1812268,   1944725,   2082664,   2226148,
++      2375238,   2529996,   2690481,   2856753,   3028870,   3206888,   3390865,   3580856,
++      3776916,   3979100,   4187460,   4402049,   4622919,   4850123,   5083710,   5323731,
++      5570236,   5823273,   6082892,   6349140,   6622065,   6901714,   7188133,   7481369,
++      7781466,   8088471,   8402427,   8723380,   9051372,   9386448,   9728650,  10078021,
++     10434603,  10798439,  11169569,  11548036,  11933879,  12327139,  12727857,  13136073,
++     13551826,  13975156,  14406100,  14844697,  15290987,  15745007,  16206795,  16676389,
++     17153826,  17639142,  18132374,  18633560,  19142734,  19659934,  20185196,  20718552,
++     21260042,  21809696,  22367554,  22933648,  23508010,  24090680,  24681686,  25281066,
++     25888850,  26505076,  27129772,  27762974,  28404716,  29055026,  29713942,  30381490,
++     31057708,  31742624,  32436272,  33138682,  33849884,  34569912,  35298800,  36036568,
++     36783260,  37538896,  38303512,  39077136,  39859796,  40651528,  41452360,  42262316,
++     43081432,  43909732,  44747252,  45594016,  46450052,  47315392,  48190064,  49074096,
++     49967516,  50870356,  51782636,  52704392,  53635648,  54576432,  55526772,  56486700,
++     57456236,  58435408,  59424248,  60422780,  61431036,  62449032,  63476804,  64514376,
++     65561776,  66619028,  67686160,  68763192,  69850160,  70947088,  72053992,  73170912,
++     74297864,  75434880,  76581976,  77739184,  78906536,  80084040,  81271736,  82469648,
++     83677792,  84896192,  86124888,  87363888,  88613232,  89872928,  91143016,  92423512,
++     93714432,  95015816,  96327688,  97650056,  98982952, 100326408, 101680440, 103045072,
++    104420320, 105806224, 107202800, 108610064, 110028048, 111456776, 112896264, 114346544,
++    115807632, 117279552, 118762328, 120255976, 121760536, 123276016, 124802440, 126339832,
++    127888216, 129447616, 131018048, 132599544, 134192112, 135795792, 137410592, 139036528,
++    140673648, 142321952, 143981456, 145652208, 147334208, 149027488, 150732064, 152447968,
++    154175200, 155913792, 157663776, 159425168, 161197984, 162982240, 164777968, 166585184,
++    168403904, 170234160, 172075968, 173929344, 175794320, 177670896, 179559120, 181458992,
++    183370528, 185293776, 187228736, 189175424, 191133888, 193104112, 195086128, 197079968,
++    199085648, 201103184, 203132592, 205173888, 207227120, 209292272, 211369392, 213458480,
++    215559568, 217672656, 219797792, 221934976, 224084240, 226245600, 228419056, 230604656,
++    232802400, 235012320, 237234432, 239468736, 241715280, 243974080, 246245120, 248528464,
++    250824112, 253132064, 255452368, 257785040, 260130080, 262487520, 264857376, 267239664,
++};
++
++static stbir_uint8 stbir__linear_to_srgb_uchar(float f)
++{
++    int x = (int) (f * (1 << 28)); // has headroom so you don't need to clamp
++    int v = 0;
++    int i;
++
++    // Refine the guess with a short binary search.
++    i = v + 128; if (x >= stbir__srgb_offset_to_linear_scaled[i]) v = i;
++    i = v +  64; if (x >= stbir__srgb_offset_to_linear_scaled[i]) v = i;
++    i = v +  32; if (x >= stbir__srgb_offset_to_linear_scaled[i]) v = i;
++    i = v +  16; if (x >= stbir__srgb_offset_to_linear_scaled[i]) v = i;
++    i = v +   8; if (x >= stbir__srgb_offset_to_linear_scaled[i]) v = i;
++    i = v +   4; if (x >= stbir__srgb_offset_to_linear_scaled[i]) v = i;
++    i = v +   2; if (x >= stbir__srgb_offset_to_linear_scaled[i]) v = i;
++    i = v +   1; if (x >= stbir__srgb_offset_to_linear_scaled[i]) v = i;
++
++    return (stbir_uint8) v;
++}
++#endif
++
++static float stbir__filter_trapezoid(float x, float scale)
++{
++    float halfscale = scale / 2;
++    float t = 0.5f + halfscale;
++    STBIR_ASSERT(scale <= 1);
++
++    x = (float)fabs(x);
++
++    if (x >= t)
++        return 0;
++    else
++    {
++        float r = 0.5f - halfscale;
++        if (x <= r)
++            return 1;
++        else
++            return (t - x) / scale;
++    }
++}
++
++static float stbir__support_trapezoid(float scale)
++{
++    STBIR_ASSERT(scale <= 1);
++    return 0.5f + scale / 2;
++}
++
++static float stbir__filter_triangle(float x, float s)
++{
++    STBIR__UNUSED_PARAM(s);
++
++    x = (float)fabs(x);
++
++    if (x <= 1.0f)
++        return 1 - x;
++    else
++        return 0;
++}
++
++static float stbir__filter_cubic(float x, float s)
++{
++    STBIR__UNUSED_PARAM(s);
++
++    x = (float)fabs(x);
++
++    if (x < 1.0f)
++        return (4 + x*x*(3*x - 6))/6;
++    else if (x < 2.0f)
++        return (8 + x*(-12 + x*(6 - x)))/6;
++
++    return (0.0f);
++}
++
++static float stbir__filter_catmullrom(float x, float s)
++{
++    STBIR__UNUSED_PARAM(s);
++
++    x = (float)fabs(x);
++
++    if (x < 1.0f)
++        return 1 - x*x*(2.5f - 1.5f*x);
++    else if (x < 2.0f)
++        return 2 - x*(4 + x*(0.5f*x - 2.5f));
++
++    return (0.0f);
++}
++
++static float stbir__filter_mitchell(float x, float s)
++{
++    STBIR__UNUSED_PARAM(s);
++
++    x = (float)fabs(x);
++
++    if (x < 1.0f)
++        return (16 + x*x*(21 * x - 36))/18;
++    else if (x < 2.0f)
++        return (32 + x*(-60 + x*(36 - 7*x)))/18;
++
++    return (0.0f);
++}
++
++static float stbir__support_zero(float s)
++{
++    STBIR__UNUSED_PARAM(s);
++    return 0;
++}
++
++static float stbir__support_one(float s)
++{
++    STBIR__UNUSED_PARAM(s);
++    return 1;
++}
++
++static float stbir__support_two(float s)
++{
++    STBIR__UNUSED_PARAM(s);
++    return 2;
++}
++
++static stbir__filter_info stbir__filter_info_table[] = {
++        { NULL,                     stbir__support_zero },
++        { stbir__filter_trapezoid,  stbir__support_trapezoid },
++        { stbir__filter_triangle,   stbir__support_one },
++        { stbir__filter_cubic,      stbir__support_two },
++        { stbir__filter_catmullrom, stbir__support_two },
++        { stbir__filter_mitchell,   stbir__support_two },
++};
++
++stbir__inline static int stbir__use_upsampling(float ratio)
++{
++    return ratio > 1;
++}
++
++stbir__inline static int stbir__use_width_upsampling(stbir__info* stbir_info)
++{
++    return stbir__use_upsampling(stbir_info->horizontal_scale);
++}
++
++stbir__inline static int stbir__use_height_upsampling(stbir__info* stbir_info)
++{
++    return stbir__use_upsampling(stbir_info->vertical_scale);
++}
++
++// This is the maximum number of input samples that can affect an output sample
++// with the given filter
++static int stbir__get_filter_pixel_width(stbir_filter filter, float scale)
++{
++    STBIR_ASSERT(filter != 0);
++    STBIR_ASSERT(filter < STBIR__ARRAY_SIZE(stbir__filter_info_table));
++
++    if (stbir__use_upsampling(scale))
++        return (int)ceil(stbir__filter_info_table[filter].support(1/scale) * 2);
++    else
++        return (int)ceil(stbir__filter_info_table[filter].support(scale) * 2 / scale);
++}
++
++// This is how much to expand buffers to account for filters seeking outside
++// the image boundaries.
++static int stbir__get_filter_pixel_margin(stbir_filter filter, float scale)
++{
++    return stbir__get_filter_pixel_width(filter, scale) / 2;
++}
++
++static int stbir__get_coefficient_width(stbir_filter filter, float scale)
++{
++    if (stbir__use_upsampling(scale))
++        return (int)ceil(stbir__filter_info_table[filter].support(1 / scale) * 2);
++    else
++        return (int)ceil(stbir__filter_info_table[filter].support(scale) * 2);
++}
++
++static int stbir__get_contributors(float scale, stbir_filter filter, int input_size, int output_size)
++{
++    if (stbir__use_upsampling(scale))
++        return output_size;
++    else
++        return (input_size + stbir__get_filter_pixel_margin(filter, scale) * 2);
++}
++
++static int stbir__get_total_horizontal_coefficients(stbir__info* info)
++{
++    return info->horizontal_num_contributors
++         * stbir__get_coefficient_width      (info->horizontal_filter, info->horizontal_scale);
++}
++
++static int stbir__get_total_vertical_coefficients(stbir__info* info)
++{
++    return info->vertical_num_contributors
++         * stbir__get_coefficient_width      (info->vertical_filter, info->vertical_scale);
++}
++
++static stbir__contributors* stbir__get_contributor(stbir__contributors* contributors, int n)
++{
++    return &contributors[n];
++}
++
++// For perf reasons this code is duplicated in stbir__resample_horizontal_upsample/downsample,
++// if you change it here change it there too.
++static float* stbir__get_coefficient(float* coefficients, stbir_filter filter, float scale, int n, int c)
++{
++    int width = stbir__get_coefficient_width(filter, scale);
++    return &coefficients[width*n + c];
++}
++
++static int stbir__edge_wrap_slow(stbir_edge edge, int n, int max)
++{
++    switch (edge)
++    {
++    case STBIR_EDGE_ZERO:
++        return 0; // we'll decode the wrong pixel here, and then overwrite with 0s later
++
++    case STBIR_EDGE_CLAMP:
++        if (n < 0)
++            return 0;
++
++        if (n >= max)
++            return max - 1;
++
++        return n; // NOTREACHED
++
++    case STBIR_EDGE_REFLECT:
++    {
++        if (n < 0)
++        {
++            if (n < max)
++                return -n;
++            else
++                return max - 1;
++        }
++
++        if (n >= max)
++        {
++            int max2 = max * 2;
++            if (n >= max2)
++                return 0;
++            else
++                return max2 - n - 1;
++        }
++
++        return n; // NOTREACHED
++    }
++
++    case STBIR_EDGE_WRAP:
++        if (n >= 0)
++            return (n % max);
++        else
++        {
++            int m = (-n) % max;
++
++            if (m != 0)
++                m = max - m;
++
++            return (m);
++        }
++        // NOTREACHED
++
++    default:
++        STBIR_ASSERT(!"Unimplemented edge type");
++        return 0;
++    }
++}
++
++stbir__inline static int stbir__edge_wrap(stbir_edge edge, int n, int max)
++{
++    // avoid per-pixel switch
++    if (n >= 0 && n < max)
++        return n;
++    return stbir__edge_wrap_slow(edge, n, max);
++}
++
++// What input pixels contribute to this output pixel?
++static void stbir__calculate_sample_range_upsample(int n, float out_filter_radius, float scale_ratio, float out_shift, int* in_first_pixel, int* in_last_pixel, float* in_center_of_out)
++{
++    float out_pixel_center = (float)n + 0.5f;
++    float out_pixel_influence_lowerbound = out_pixel_center - out_filter_radius;
++    float out_pixel_influence_upperbound = out_pixel_center + out_filter_radius;
++
++    float in_pixel_influence_lowerbound = (out_pixel_influence_lowerbound + out_shift) / scale_ratio;
++    float in_pixel_influence_upperbound = (out_pixel_influence_upperbound + out_shift) / scale_ratio;
++
++    *in_center_of_out = (out_pixel_center + out_shift) / scale_ratio;
++    *in_first_pixel = (int)(floor(in_pixel_influence_lowerbound + 0.5));
++    *in_last_pixel = (int)(floor(in_pixel_influence_upperbound - 0.5));
++}
++
++// What output pixels does this input pixel contribute to?
++static void stbir__calculate_sample_range_downsample(int n, float in_pixels_radius, float scale_ratio, float out_shift, int* out_first_pixel, int* out_last_pixel, float* out_center_of_in)
++{
++    float in_pixel_center = (float)n + 0.5f;
++    float in_pixel_influence_lowerbound = in_pixel_center - in_pixels_radius;
++    float in_pixel_influence_upperbound = in_pixel_center + in_pixels_radius;
++
++    float out_pixel_influence_lowerbound = in_pixel_influence_lowerbound * scale_ratio - out_shift;
++    float out_pixel_influence_upperbound = in_pixel_influence_upperbound * scale_ratio - out_shift;
++
++    *out_center_of_in = in_pixel_center * scale_ratio - out_shift;
++    *out_first_pixel = (int)(floor(out_pixel_influence_lowerbound + 0.5));
++    *out_last_pixel = (int)(floor(out_pixel_influence_upperbound - 0.5));
++}
++
++static void stbir__calculate_coefficients_upsample(stbir_filter filter, float scale, int in_first_pixel, int in_last_pixel, float in_center_of_out, stbir__contributors* contributor, float* coefficient_group)
++{
++    int i;
++    float total_filter = 0;
++    float filter_scale;
++
++    STBIR_ASSERT(in_last_pixel - in_first_pixel <= (int)ceil(stbir__filter_info_table[filter].support(1/scale) * 2)); // Taken directly from stbir__get_coefficient_width() which we can't call because we don't know if we're horizontal or vertical.
++
++    contributor->n0 = in_first_pixel;
++    contributor->n1 = in_last_pixel;
++
++    STBIR_ASSERT(contributor->n1 >= contributor->n0);
++
++    for (i = 0; i <= in_last_pixel - in_first_pixel; i++)
++    {
++        float in_pixel_center = (float)(i + in_first_pixel) + 0.5f;
++        coefficient_group[i] = stbir__filter_info_table[filter].kernel(in_center_of_out - in_pixel_center, 1 / scale);
++
++        // If the coefficient is zero, skip it. (Don't do the <0 check here, we want the influence of those outside pixels.)
++        if (i == 0 && !coefficient_group[i])
++        {
++            contributor->n0 = ++in_first_pixel;
++            i--;
++            continue;
++        }
++
++        total_filter += coefficient_group[i];
++    }
++
++    STBIR_ASSERT(stbir__filter_info_table[filter].kernel((float)(in_last_pixel + 1) + 0.5f - in_center_of_out, 1/scale) == 0);
++
++    STBIR_ASSERT(total_filter > 0.9);
++    STBIR_ASSERT(total_filter < 1.1f); // Make sure it's not way off.
++
++    // Make sure the sum of all coefficients is 1.
++    filter_scale = 1 / total_filter;
++
++    for (i = 0; i <= in_last_pixel - in_first_pixel; i++)
++        coefficient_group[i] *= filter_scale;
++
++    for (i = in_last_pixel - in_first_pixel; i >= 0; i--)
++    {
++        if (coefficient_group[i])
++            break;
++
++        // This line has no weight. We can skip it.
++        contributor->n1 = contributor->n0 + i - 1;
++    }
++}
++
++static void stbir__calculate_coefficients_downsample(stbir_filter filter, float scale_ratio, int out_first_pixel, int out_last_pixel, float out_center_of_in, stbir__contributors* contributor, float* coefficient_group)
++{
++    int i;
++
++     STBIR_ASSERT(out_last_pixel - out_first_pixel <= (int)ceil(stbir__filter_info_table[filter].support(scale_ratio) * 2)); // Taken directly from stbir__get_coefficient_width() which we can't call because we don't know if we're horizontal or vertical.
++
++    contributor->n0 = out_first_pixel;
++    contributor->n1 = out_last_pixel;
++
++    STBIR_ASSERT(contributor->n1 >= contributor->n0);
++
++    for (i = 0; i <= out_last_pixel - out_first_pixel; i++)
++    {
++        float out_pixel_center = (float)(i + out_first_pixel) + 0.5f;
++        float x = out_pixel_center - out_center_of_in;
++        coefficient_group[i] = stbir__filter_info_table[filter].kernel(x, scale_ratio) * scale_ratio;
++    }
++
++    STBIR_ASSERT(stbir__filter_info_table[filter].kernel((float)(out_last_pixel + 1) + 0.5f - out_center_of_in, scale_ratio) == 0);
++
++    for (i = out_last_pixel - out_first_pixel; i >= 0; i--)
++    {
++        if (coefficient_group[i])
++            break;
++
++        // This line has no weight. We can skip it.
++        contributor->n1 = contributor->n0 + i - 1;
++    }
++}
++
++static void stbir__normalize_downsample_coefficients(stbir__contributors* contributors, float* coefficients, stbir_filter filter, float scale_ratio, int input_size, int output_size)
++{
++    int num_contributors = stbir__get_contributors(scale_ratio, filter, input_size, output_size);
++    int num_coefficients = stbir__get_coefficient_width(filter, scale_ratio);
++    int i, j;
++    int skip;
++
++    for (i = 0; i < output_size; i++)
++    {
++        float scale;
++        float total = 0;
++
++        for (j = 0; j < num_contributors; j++)
++        {
++            if (i >= contributors[j].n0 && i <= contributors[j].n1)
++            {
++                float coefficient = *stbir__get_coefficient(coefficients, filter, scale_ratio, j, i - contributors[j].n0);
++                total += coefficient;
++            }
++            else if (i < contributors[j].n0)
++                break;
++        }
++
++        STBIR_ASSERT(total > 0.9f);
++        STBIR_ASSERT(total < 1.1f);
++
++        scale = 1 / total;
++
++        for (j = 0; j < num_contributors; j++)
++        {
++            if (i >= contributors[j].n0 && i <= contributors[j].n1)
++                *stbir__get_coefficient(coefficients, filter, scale_ratio, j, i - contributors[j].n0) *= scale;
++            else if (i < contributors[j].n0)
++                break;
++        }
++    }
++
++    // Optimize: Skip zero coefficients and contributions outside of image bounds.
++    // Do this after normalizing because normalization depends on the n0/n1 values.
++    for (j = 0; j < num_contributors; j++)
++    {
++        int range, max, width;
++
++        skip = 0;
++        while (*stbir__get_coefficient(coefficients, filter, scale_ratio, j, skip) == 0)
++            skip++;
++
++        contributors[j].n0 += skip;
++
++        while (contributors[j].n0 < 0)
++        {
++            contributors[j].n0++;
++            skip++;
++        }
++
++        range = contributors[j].n1 - contributors[j].n0 + 1;
++        max = stbir__min(num_coefficients, range);
++
++        width = stbir__get_coefficient_width(filter, scale_ratio);
++        for (i = 0; i < max; i++)
++        {
++            if (i + skip >= width)
++                break;
++
++            *stbir__get_coefficient(coefficients, filter, scale_ratio, j, i) = *stbir__get_coefficient(coefficients, filter, scale_ratio, j, i + skip);
++        }
++
++        continue;
++    }
++
++    // Using min to avoid writing into invalid pixels.
++    for (i = 0; i < num_contributors; i++)
++        contributors[i].n1 = stbir__min(contributors[i].n1, output_size - 1);
++}
++
++// Each scan line uses the same kernel values so we should calculate the kernel
++// values once and then we can use them for every scan line.
++static void stbir__calculate_filters(stbir__contributors* contributors, float* coefficients, stbir_filter filter, float scale_ratio, float shift, int input_size, int output_size)
++{
++    int n;
++    int total_contributors = stbir__get_contributors(scale_ratio, filter, input_size, output_size);
++
++    if (stbir__use_upsampling(scale_ratio))
++    {
++        float out_pixels_radius = stbir__filter_info_table[filter].support(1 / scale_ratio) * scale_ratio;
++
++        // Looping through out pixels
++        for (n = 0; n < total_contributors; n++)
++        {
++            float in_center_of_out; // Center of the current out pixel in the in pixel space
++            int in_first_pixel, in_last_pixel;
++
++            stbir__calculate_sample_range_upsample(n, out_pixels_radius, scale_ratio, shift, &in_first_pixel, &in_last_pixel, &in_center_of_out);
++
++            stbir__calculate_coefficients_upsample(filter, scale_ratio, in_first_pixel, in_last_pixel, in_center_of_out, stbir__get_contributor(contributors, n), stbir__get_coefficient(coefficients, filter, scale_ratio, n, 0));
++        }
++    }
++    else
++    {
++        float in_pixels_radius = stbir__filter_info_table[filter].support(scale_ratio) / scale_ratio;
++
++        // Looping through in pixels
++        for (n = 0; n < total_contributors; n++)
++        {
++            float out_center_of_in; // Center of the current out pixel in the in pixel space
++            int out_first_pixel, out_last_pixel;
++            int n_adjusted = n - stbir__get_filter_pixel_margin(filter, scale_ratio);
++
++            stbir__calculate_sample_range_downsample(n_adjusted, in_pixels_radius, scale_ratio, shift, &out_first_pixel, &out_last_pixel, &out_center_of_in);
++
++            stbir__calculate_coefficients_downsample(filter, scale_ratio, out_first_pixel, out_last_pixel, out_center_of_in, stbir__get_contributor(contributors, n), stbir__get_coefficient(coefficients, filter, scale_ratio, n, 0));
++        }
++
++        stbir__normalize_downsample_coefficients(contributors, coefficients, filter, scale_ratio, input_size, output_size);
++    }
++}
++
++static float* stbir__get_decode_buffer(stbir__info* stbir_info)
++{
++    // The 0 index of the decode buffer starts after the margin. This makes
++    // it okay to use negative indexes on the decode buffer.
++    return &stbir_info->decode_buffer[stbir_info->horizontal_filter_pixel_margin * stbir_info->channels];
++}
++
++#define STBIR__DECODE(type, colorspace) ((type) * (STBIR_MAX_COLORSPACES) + (colorspace))
++
++static void stbir__decode_scanline(stbir__info* stbir_info, int n)
++{
++    int c;
++    int channels = stbir_info->channels;
++    int alpha_channel = stbir_info->alpha_channel;
++    int type = stbir_info->type;
++    int colorspace = stbir_info->colorspace;
++    int input_w = stbir_info->input_w;
++    size_t input_stride_bytes = stbir_info->input_stride_bytes;
++    float* decode_buffer = stbir__get_decode_buffer(stbir_info);
++    stbir_edge edge_horizontal = stbir_info->edge_horizontal;
++    stbir_edge edge_vertical = stbir_info->edge_vertical;
++    size_t in_buffer_row_offset = stbir__edge_wrap(edge_vertical, n, stbir_info->input_h) * input_stride_bytes;
++    const void* input_data = (char *) stbir_info->input_data + in_buffer_row_offset;
++    int max_x = input_w + stbir_info->horizontal_filter_pixel_margin;
++    int decode = STBIR__DECODE(type, colorspace);
++
++    int x = -stbir_info->horizontal_filter_pixel_margin;
++
++    // special handling for STBIR_EDGE_ZERO because it needs to return an item that doesn't appear in the input,
++    // and we want to avoid paying overhead on every pixel if not STBIR_EDGE_ZERO
++    if (edge_vertical == STBIR_EDGE_ZERO && (n < 0 || n >= stbir_info->input_h))
++    {
++        for (; x < max_x; x++)
++            for (c = 0; c < channels; c++)
++                decode_buffer[x*channels + c] = 0;
++        return;
++    }
++
++    switch (decode)
++    {
++    case STBIR__DECODE(STBIR_TYPE_UINT8, STBIR_COLORSPACE_LINEAR):
++        for (; x < max_x; x++)
++        {
++            int decode_pixel_index = x * channels;
++            int input_pixel_index = stbir__edge_wrap(edge_horizontal, x, input_w) * channels;
++            for (c = 0; c < channels; c++)
++                decode_buffer[decode_pixel_index + c] = ((float)((const unsigned char*)input_data)[input_pixel_index + c]) / stbir__max_uint8_as_float;
++        }
++        break;
++
++    case STBIR__DECODE(STBIR_TYPE_UINT8, STBIR_COLORSPACE_SRGB):
++        for (; x < max_x; x++)
++        {
++            int decode_pixel_index = x * channels;
++            int input_pixel_index = stbir__edge_wrap(edge_horizontal, x, input_w) * channels;
++            for (c = 0; c < channels; c++)
++                decode_buffer[decode_pixel_index + c] = stbir__srgb_uchar_to_linear_float[((const unsigned char*)input_data)[input_pixel_index + c]];
++
++            if (!(stbir_info->flags&STBIR_FLAG_ALPHA_USES_COLORSPACE))
++                decode_buffer[decode_pixel_index + alpha_channel] = ((float)((const unsigned char*)input_data)[input_pixel_index + alpha_channel]) / stbir__max_uint8_as_float;
++        }
++        break;
++
++    case STBIR__DECODE(STBIR_TYPE_UINT16, STBIR_COLORSPACE_LINEAR):
++        for (; x < max_x; x++)
++        {
++            int decode_pixel_index = x * channels;
++            int input_pixel_index = stbir__edge_wrap(edge_horizontal, x, input_w) * channels;
++            for (c = 0; c < channels; c++)
++                decode_buffer[decode_pixel_index + c] = ((float)((const unsigned short*)input_data)[input_pixel_index + c]) / stbir__max_uint16_as_float;
++        }
++        break;
++
++    case STBIR__DECODE(STBIR_TYPE_UINT16, STBIR_COLORSPACE_SRGB):
++        for (; x < max_x; x++)
++        {
++            int decode_pixel_index = x * channels;
++            int input_pixel_index = stbir__edge_wrap(edge_horizontal, x, input_w) * channels;
++            for (c = 0; c < channels; c++)
++                decode_buffer[decode_pixel_index + c] = stbir__srgb_to_linear(((float)((const unsigned short*)input_data)[input_pixel_index + c]) / stbir__max_uint16_as_float);
++
++            if (!(stbir_info->flags&STBIR_FLAG_ALPHA_USES_COLORSPACE))
++                decode_buffer[decode_pixel_index + alpha_channel] = ((float)((const unsigned short*)input_data)[input_pixel_index + alpha_channel]) / stbir__max_uint16_as_float;
++        }
++        break;
++
++    case STBIR__DECODE(STBIR_TYPE_UINT32, STBIR_COLORSPACE_LINEAR):
++        for (; x < max_x; x++)
++        {
++            int decode_pixel_index = x * channels;
++            int input_pixel_index = stbir__edge_wrap(edge_horizontal, x, input_w) * channels;
++            for (c = 0; c < channels; c++)
++                decode_buffer[decode_pixel_index + c] = (float)(((double)((const unsigned int*)input_data)[input_pixel_index + c]) / stbir__max_uint32_as_float);
++        }
++        break;
++
++    case STBIR__DECODE(STBIR_TYPE_UINT32, STBIR_COLORSPACE_SRGB):
++        for (; x < max_x; x++)
++        {
++            int decode_pixel_index = x * channels;
++            int input_pixel_index = stbir__edge_wrap(edge_horizontal, x, input_w) * channels;
++            for (c = 0; c < channels; c++)
++                decode_buffer[decode_pixel_index + c] = stbir__srgb_to_linear((float)(((double)((const unsigned int*)input_data)[input_pixel_index + c]) / stbir__max_uint32_as_float));
++
++            if (!(stbir_info->flags&STBIR_FLAG_ALPHA_USES_COLORSPACE))
++                decode_buffer[decode_pixel_index + alpha_channel] = (float)(((double)((const unsigned int*)input_data)[input_pixel_index + alpha_channel]) / stbir__max_uint32_as_float);
++        }
++        break;
++
++    case STBIR__DECODE(STBIR_TYPE_FLOAT, STBIR_COLORSPACE_LINEAR):
++        for (; x < max_x; x++)
++        {
++            int decode_pixel_index = x * channels;
++            int input_pixel_index = stbir__edge_wrap(edge_horizontal, x, input_w) * channels;
++            for (c = 0; c < channels; c++)
++                decode_buffer[decode_pixel_index + c] = ((const float*)input_data)[input_pixel_index + c];
++        }
++        break;
++
++    case STBIR__DECODE(STBIR_TYPE_FLOAT, STBIR_COLORSPACE_SRGB):
++        for (; x < max_x; x++)
++        {
++            int decode_pixel_index = x * channels;
++            int input_pixel_index = stbir__edge_wrap(edge_horizontal, x, input_w) * channels;
++            for (c = 0; c < channels; c++)
++                decode_buffer[decode_pixel_index + c] = stbir__srgb_to_linear(((const float*)input_data)[input_pixel_index + c]);
++
++            if (!(stbir_info->flags&STBIR_FLAG_ALPHA_USES_COLORSPACE))
++                decode_buffer[decode_pixel_index + alpha_channel] = ((const float*)input_data)[input_pixel_index + alpha_channel];
++        }
++
++        break;
++
++    default:
++        STBIR_ASSERT(!"Unknown type/colorspace/channels combination.");
++        break;
++    }
++
++    if (!(stbir_info->flags & STBIR_FLAG_ALPHA_PREMULTIPLIED))
++    {
++        for (x = -stbir_info->horizontal_filter_pixel_margin; x < max_x; x++)
++        {
++            int decode_pixel_index = x * channels;
++
++            // If the alpha value is 0 it will clobber the color values. Make sure it's not.
++            float alpha = decode_buffer[decode_pixel_index + alpha_channel];
++#ifndef STBIR_NO_ALPHA_EPSILON
++            if (stbir_info->type != STBIR_TYPE_FLOAT) {
++                alpha += STBIR_ALPHA_EPSILON;
++                decode_buffer[decode_pixel_index + alpha_channel] = alpha;
++            }
++#endif
++            for (c = 0; c < channels; c++)
++            {
++                if (c == alpha_channel)
++                    continue;
++
++                decode_buffer[decode_pixel_index + c] *= alpha;
++            }
++        }
++    }
++
++    if (edge_horizontal == STBIR_EDGE_ZERO)
++    {
++        for (x = -stbir_info->horizontal_filter_pixel_margin; x < 0; x++)
++        {
++            for (c = 0; c < channels; c++)
++                decode_buffer[x*channels + c] = 0;
++        }
++        for (x = input_w; x < max_x; x++)
++        {
++            for (c = 0; c < channels; c++)
++                decode_buffer[x*channels + c] = 0;
++        }
++    }
++}
++
++static float* stbir__get_ring_buffer_entry(float* ring_buffer, int index, int ring_buffer_length)
++{
++    return &ring_buffer[index * ring_buffer_length];
++}
++
++static float* stbir__add_empty_ring_buffer_entry(stbir__info* stbir_info, int n)
++{
++    int ring_buffer_index;
++    float* ring_buffer;
++
++    stbir_info->ring_buffer_last_scanline = n;
++
++    if (stbir_info->ring_buffer_begin_index < 0)
++    {
++        ring_buffer_index = stbir_info->ring_buffer_begin_index = 0;
++        stbir_info->ring_buffer_first_scanline = n;
++    }
++    else
++    {
++        ring_buffer_index = (stbir_info->ring_buffer_begin_index + (stbir_info->ring_buffer_last_scanline - stbir_info->ring_buffer_first_scanline)) % stbir_info->ring_buffer_num_entries;
++        STBIR_ASSERT(ring_buffer_index != stbir_info->ring_buffer_begin_index);
++    }
++
++    ring_buffer = stbir__get_ring_buffer_entry(stbir_info->ring_buffer, ring_buffer_index, stbir_info->ring_buffer_length_bytes / sizeof(float));
++    memset(ring_buffer, 0, stbir_info->ring_buffer_length_bytes);
++
++    return ring_buffer;
++}
++
++
++static void stbir__resample_horizontal_upsample(stbir__info* stbir_info, float* output_buffer)
++{
++    int x, k;
++    int output_w = stbir_info->output_w;
++    int channels = stbir_info->channels;
++    float* decode_buffer = stbir__get_decode_buffer(stbir_info);
++    stbir__contributors* horizontal_contributors = stbir_info->horizontal_contributors;
++    float* horizontal_coefficients = stbir_info->horizontal_coefficients;
++    int coefficient_width = stbir_info->horizontal_coefficient_width;
++
++    for (x = 0; x < output_w; x++)
++    {
++        int n0 = horizontal_contributors[x].n0;
++        int n1 = horizontal_contributors[x].n1;
++
++        int out_pixel_index = x * channels;
++        int coefficient_group = coefficient_width * x;
++        int coefficient_counter = 0;
++
++        STBIR_ASSERT(n1 >= n0);
++        STBIR_ASSERT(n0 >= -stbir_info->horizontal_filter_pixel_margin);
++        STBIR_ASSERT(n1 >= -stbir_info->horizontal_filter_pixel_margin);
++        STBIR_ASSERT(n0 < stbir_info->input_w + stbir_info->horizontal_filter_pixel_margin);
++        STBIR_ASSERT(n1 < stbir_info->input_w + stbir_info->horizontal_filter_pixel_margin);
++
++        switch (channels) {
++            case 1:
++                for (k = n0; k <= n1; k++)
++                {
++                    int in_pixel_index = k * 1;
++                    float coefficient = horizontal_coefficients[coefficient_group + coefficient_counter++];
++                    STBIR_ASSERT(coefficient != 0);
++                    output_buffer[out_pixel_index + 0] += decode_buffer[in_pixel_index + 0] * coefficient;
++                }
++                break;
++            case 2:
++                for (k = n0; k <= n1; k++)
++                {
++                    int in_pixel_index = k * 2;
++                    float coefficient = horizontal_coefficients[coefficient_group + coefficient_counter++];
++                    STBIR_ASSERT(coefficient != 0);
++                    output_buffer[out_pixel_index + 0] += decode_buffer[in_pixel_index + 0] * coefficient;
++                    output_buffer[out_pixel_index + 1] += decode_buffer[in_pixel_index + 1] * coefficient;
++                }
++                break;
++            case 3:
++                for (k = n0; k <= n1; k++)
++                {
++                    int in_pixel_index = k * 3;
++                    float coefficient = horizontal_coefficients[coefficient_group + coefficient_counter++];
++                    STBIR_ASSERT(coefficient != 0);
++                    output_buffer[out_pixel_index + 0] += decode_buffer[in_pixel_index + 0] * coefficient;
++                    output_buffer[out_pixel_index + 1] += decode_buffer[in_pixel_index + 1] * coefficient;
++                    output_buffer[out_pixel_index + 2] += decode_buffer[in_pixel_index + 2] * coefficient;
++                }
++                break;
++            case 4:
++                for (k = n0; k <= n1; k++)
++                {
++                    int in_pixel_index = k * 4;
++                    float coefficient = horizontal_coefficients[coefficient_group + coefficient_counter++];
++                    STBIR_ASSERT(coefficient != 0);
++                    output_buffer[out_pixel_index + 0] += decode_buffer[in_pixel_index + 0] * coefficient;
++                    output_buffer[out_pixel_index + 1] += decode_buffer[in_pixel_index + 1] * coefficient;
++                    output_buffer[out_pixel_index + 2] += decode_buffer[in_pixel_index + 2] * coefficient;
++                    output_buffer[out_pixel_index + 3] += decode_buffer[in_pixel_index + 3] * coefficient;
++                }
++                break;
++            default:
++                for (k = n0; k <= n1; k++)
++                {
++                    int in_pixel_index = k * channels;
++                    float coefficient = horizontal_coefficients[coefficient_group + coefficient_counter++];
++                    int c;
++                    STBIR_ASSERT(coefficient != 0);
++                    for (c = 0; c < channels; c++)
++                        output_buffer[out_pixel_index + c] += decode_buffer[in_pixel_index + c] * coefficient;
++                }
++                break;
++        }
++    }
++}
++
++static void stbir__resample_horizontal_downsample(stbir__info* stbir_info, float* output_buffer)
++{
++    int x, k;
++    int input_w = stbir_info->input_w;
++    int channels = stbir_info->channels;
++    float* decode_buffer = stbir__get_decode_buffer(stbir_info);
++    stbir__contributors* horizontal_contributors = stbir_info->horizontal_contributors;
++    float* horizontal_coefficients = stbir_info->horizontal_coefficients;
++    int coefficient_width = stbir_info->horizontal_coefficient_width;
++    int filter_pixel_margin = stbir_info->horizontal_filter_pixel_margin;
++    int max_x = input_w + filter_pixel_margin * 2;
++
++    STBIR_ASSERT(!stbir__use_width_upsampling(stbir_info));
++
++    switch (channels) {
++        case 1:
++            for (x = 0; x < max_x; x++)
++            {
++                int n0 = horizontal_contributors[x].n0;
++                int n1 = horizontal_contributors[x].n1;
++
++                int in_x = x - filter_pixel_margin;
++                int in_pixel_index = in_x * 1;
++                int max_n = n1;
++                int coefficient_group = coefficient_width * x;
++
++                for (k = n0; k <= max_n; k++)
++                {
++                    int out_pixel_index = k * 1;
++                    float coefficient = horizontal_coefficients[coefficient_group + k - n0];
++                    STBIR_ASSERT(coefficient != 0);
++                    output_buffer[out_pixel_index + 0] += decode_buffer[in_pixel_index + 0] * coefficient;
++                }
++            }
++            break;
++
++        case 2:
++            for (x = 0; x < max_x; x++)
++            {
++                int n0 = horizontal_contributors[x].n0;
++                int n1 = horizontal_contributors[x].n1;
++
++                int in_x = x - filter_pixel_margin;
++                int in_pixel_index = in_x * 2;
++                int max_n = n1;
++                int coefficient_group = coefficient_width * x;
++
++                for (k = n0; k <= max_n; k++)
++                {
++                    int out_pixel_index = k * 2;
++                    float coefficient = horizontal_coefficients[coefficient_group + k - n0];
++                    STBIR_ASSERT(coefficient != 0);
++                    output_buffer[out_pixel_index + 0] += decode_buffer[in_pixel_index + 0] * coefficient;
++                    output_buffer[out_pixel_index + 1] += decode_buffer[in_pixel_index + 1] * coefficient;
++                }
++            }
++            break;
++
++        case 3:
++            for (x = 0; x < max_x; x++)
++            {
++                int n0 = horizontal_contributors[x].n0;
++                int n1 = horizontal_contributors[x].n1;
++
++                int in_x = x - filter_pixel_margin;
++                int in_pixel_index = in_x * 3;
++                int max_n = n1;
++                int coefficient_group = coefficient_width * x;
++
++                for (k = n0; k <= max_n; k++)
++                {
++                    int out_pixel_index = k * 3;
++                    float coefficient = horizontal_coefficients[coefficient_group + k - n0];
++                    STBIR_ASSERT(coefficient != 0);
++                    output_buffer[out_pixel_index + 0] += decode_buffer[in_pixel_index + 0] * coefficient;
++                    output_buffer[out_pixel_index + 1] += decode_buffer[in_pixel_index + 1] * coefficient;
++                    output_buffer[out_pixel_index + 2] += decode_buffer[in_pixel_index + 2] * coefficient;
++                }
++            }
++            break;
++
++        case 4:
++            for (x = 0; x < max_x; x++)
++            {
++                int n0 = horizontal_contributors[x].n0;
++                int n1 = horizontal_contributors[x].n1;
++
++                int in_x = x - filter_pixel_margin;
++                int in_pixel_index = in_x * 4;
++                int max_n = n1;
++                int coefficient_group = coefficient_width * x;
++
++                for (k = n0; k <= max_n; k++)
++                {
++                    int out_pixel_index = k * 4;
++                    float coefficient = horizontal_coefficients[coefficient_group + k - n0];
++                    STBIR_ASSERT(coefficient != 0);
++                    output_buffer[out_pixel_index + 0] += decode_buffer[in_pixel_index + 0] * coefficient;
++                    output_buffer[out_pixel_index + 1] += decode_buffer[in_pixel_index + 1] * coefficient;
++                    output_buffer[out_pixel_index + 2] += decode_buffer[in_pixel_index + 2] * coefficient;
++                    output_buffer[out_pixel_index + 3] += decode_buffer[in_pixel_index + 3] * coefficient;
++                }
++            }
++            break;
++
++        default:
++            for (x = 0; x < max_x; x++)
++            {
++                int n0 = horizontal_contributors[x].n0;
++                int n1 = horizontal_contributors[x].n1;
++
++                int in_x = x - filter_pixel_margin;
++                int in_pixel_index = in_x * channels;
++                int max_n = n1;
++                int coefficient_group = coefficient_width * x;
++
++                for (k = n0; k <= max_n; k++)
++                {
++                    int c;
++                    int out_pixel_index = k * channels;
++                    float coefficient = horizontal_coefficients[coefficient_group + k - n0];
++                    STBIR_ASSERT(coefficient != 0);
++                    for (c = 0; c < channels; c++)
++                        output_buffer[out_pixel_index + c] += decode_buffer[in_pixel_index + c] * coefficient;
++                }
++            }
++            break;
++    }
++}
++
++static void stbir__decode_and_resample_upsample(stbir__info* stbir_info, int n)
++{
++    // Decode the nth scanline from the source image into the decode buffer.
++    stbir__decode_scanline(stbir_info, n);
++
++    // Now resample it into the ring buffer.
++    if (stbir__use_width_upsampling(stbir_info))
++        stbir__resample_horizontal_upsample(stbir_info, stbir__add_empty_ring_buffer_entry(stbir_info, n));
++    else
++        stbir__resample_horizontal_downsample(stbir_info, stbir__add_empty_ring_buffer_entry(stbir_info, n));
++
++    // Now it's sitting in the ring buffer ready to be used as source for the vertical sampling.
++}
++
++static void stbir__decode_and_resample_downsample(stbir__info* stbir_info, int n)
++{
++    // Decode the nth scanline from the source image into the decode buffer.
++    stbir__decode_scanline(stbir_info, n);
++
++    memset(stbir_info->horizontal_buffer, 0, stbir_info->output_w * stbir_info->channels * sizeof(float));
++
++    // Now resample it into the horizontal buffer.
++    if (stbir__use_width_upsampling(stbir_info))
++        stbir__resample_horizontal_upsample(stbir_info, stbir_info->horizontal_buffer);
++    else
++        stbir__resample_horizontal_downsample(stbir_info, stbir_info->horizontal_buffer);
++
++    // Now it's sitting in the horizontal buffer ready to be distributed into the ring buffers.
++}
++
++// Get the specified scan line from the ring buffer.
++static float* stbir__get_ring_buffer_scanline(int get_scanline, float* ring_buffer, int begin_index, int first_scanline, int ring_buffer_num_entries, int ring_buffer_length)
++{
++    int ring_buffer_index = (begin_index + (get_scanline - first_scanline)) % ring_buffer_num_entries;
++    return stbir__get_ring_buffer_entry(ring_buffer, ring_buffer_index, ring_buffer_length);
++}
++
++
++static void stbir__encode_scanline(stbir__info* stbir_info, int num_pixels, void *output_buffer, float *encode_buffer, int channels, int alpha_channel, int decode)
++{
++    int x;
++    int n;
++    int num_nonalpha;
++    stbir_uint16 nonalpha[STBIR_MAX_CHANNELS];
++
++    if (!(stbir_info->flags&STBIR_FLAG_ALPHA_PREMULTIPLIED))
++    {
++        for (x=0; x < num_pixels; ++x)
++        {
++            int pixel_index = x*channels;
++
++            float alpha = encode_buffer[pixel_index + alpha_channel];
++            float reciprocal_alpha = alpha ? 1.0f / alpha : 0;
++
++            // unrolling this produced a 1% slowdown upscaling a large RGBA linear-space image on my machine - stb
++            for (n = 0; n < channels; n++)
++                if (n != alpha_channel)
++                    encode_buffer[pixel_index + n] *= reciprocal_alpha;
++
++            // We added in a small epsilon to prevent the color channel from being deleted with zero alpha.
++            // Because we only add it for integer types, it will automatically be discarded on integer
++            // conversion, so we don't need to subtract it back out (which would be problematic for
++            // numeric precision reasons).
++        }
++    }
++
++    // build a table of all channels that need colorspace correction, so
++    // we don't perform colorspace correction on channels that don't need it.
++    for (x = 0, num_nonalpha = 0; x < channels; ++x)
++    {
++        if (x != alpha_channel || (stbir_info->flags & STBIR_FLAG_ALPHA_USES_COLORSPACE))
++        {
++            nonalpha[num_nonalpha++] = (stbir_uint16)x;
++        }
++    }
++
++    #define STBIR__ROUND_INT(f)    ((int)          ((f)+0.5))
++    #define STBIR__ROUND_UINT(f)   ((stbir_uint32) ((f)+0.5))
++
++    #ifdef STBIR__SATURATE_INT
++    #define STBIR__ENCODE_LINEAR8(f)   stbir__saturate8 (STBIR__ROUND_INT((f) * stbir__max_uint8_as_float ))
++    #define STBIR__ENCODE_LINEAR16(f)  stbir__saturate16(STBIR__ROUND_INT((f) * stbir__max_uint16_as_float))
++    #else
++    #define STBIR__ENCODE_LINEAR8(f)   (unsigned char ) STBIR__ROUND_INT(stbir__saturate(f) * stbir__max_uint8_as_float )
++    #define STBIR__ENCODE_LINEAR16(f)  (unsigned short) STBIR__ROUND_INT(stbir__saturate(f) * stbir__max_uint16_as_float)
++    #endif
++
++    switch (decode)
++    {
++        case STBIR__DECODE(STBIR_TYPE_UINT8, STBIR_COLORSPACE_LINEAR):
++            for (x=0; x < num_pixels; ++x)
++            {
++                int pixel_index = x*channels;
++
++                for (n = 0; n < channels; n++)
++                {
++                    int index = pixel_index + n;
++                    ((unsigned char*)output_buffer)[index] = STBIR__ENCODE_LINEAR8(encode_buffer[index]);
++                }
++            }
++            break;
++
++        case STBIR__DECODE(STBIR_TYPE_UINT8, STBIR_COLORSPACE_SRGB):
++            for (x=0; x < num_pixels; ++x)
++            {
++                int pixel_index = x*channels;
++
++                for (n = 0; n < num_nonalpha; n++)
++                {
++                    int index = pixel_index + nonalpha[n];
++                    ((unsigned char*)output_buffer)[index] = stbir__linear_to_srgb_uchar(encode_buffer[index]);
++                }
++
++                if (!(stbir_info->flags & STBIR_FLAG_ALPHA_USES_COLORSPACE))
++                    ((unsigned char *)output_buffer)[pixel_index + alpha_channel] = STBIR__ENCODE_LINEAR8(encode_buffer[pixel_index+alpha_channel]);
++            }
++            break;
++
++        case STBIR__DECODE(STBIR_TYPE_UINT16, STBIR_COLORSPACE_LINEAR):
++            for (x=0; x < num_pixels; ++x)
++            {
++                int pixel_index = x*channels;
++
++                for (n = 0; n < channels; n++)
++                {
++                    int index = pixel_index + n;
++                    ((unsigned short*)output_buffer)[index] = STBIR__ENCODE_LINEAR16(encode_buffer[index]);
++                }
++            }
++            break;
++
++        case STBIR__DECODE(STBIR_TYPE_UINT16, STBIR_COLORSPACE_SRGB):
++            for (x=0; x < num_pixels; ++x)
++            {
++                int pixel_index = x*channels;
++
++                for (n = 0; n < num_nonalpha; n++)
++                {
++                    int index = pixel_index + nonalpha[n];
++                    ((unsigned short*)output_buffer)[index] = (unsigned short)STBIR__ROUND_INT(stbir__linear_to_srgb(stbir__saturate(encode_buffer[index])) * stbir__max_uint16_as_float);
++                }
++
++                if (!(stbir_info->flags&STBIR_FLAG_ALPHA_USES_COLORSPACE))
++                    ((unsigned short*)output_buffer)[pixel_index + alpha_channel] = STBIR__ENCODE_LINEAR16(encode_buffer[pixel_index + alpha_channel]);
++            }
++
++            break;
++
++        case STBIR__DECODE(STBIR_TYPE_UINT32, STBIR_COLORSPACE_LINEAR):
++            for (x=0; x < num_pixels; ++x)
++            {
++                int pixel_index = x*channels;
++
++                for (n = 0; n < channels; n++)
++                {
++                    int index = pixel_index + n;
++                    ((unsigned int*)output_buffer)[index] = (unsigned int)STBIR__ROUND_UINT(((double)stbir__saturate(encode_buffer[index])) * stbir__max_uint32_as_float);
++                }
++            }
++            break;
++
++        case STBIR__DECODE(STBIR_TYPE_UINT32, STBIR_COLORSPACE_SRGB):
++            for (x=0; x < num_pixels; ++x)
++            {
++                int pixel_index = x*channels;
++
++                for (n = 0; n < num_nonalpha; n++)
++                {
++                    int index = pixel_index + nonalpha[n];
++                    ((unsigned int*)output_buffer)[index] = (unsigned int)STBIR__ROUND_UINT(((double)stbir__linear_to_srgb(stbir__saturate(encode_buffer[index]))) * stbir__max_uint32_as_float);
++                }
++
++                if (!(stbir_info->flags&STBIR_FLAG_ALPHA_USES_COLORSPACE))
++                    ((unsigned int*)output_buffer)[pixel_index + alpha_channel] = (unsigned int)STBIR__ROUND_INT(((double)stbir__saturate(encode_buffer[pixel_index + alpha_channel])) * stbir__max_uint32_as_float);
++            }
++            break;
++
++        case STBIR__DECODE(STBIR_TYPE_FLOAT, STBIR_COLORSPACE_LINEAR):
++            for (x=0; x < num_pixels; ++x)
++            {
++                int pixel_index = x*channels;
++
++                for (n = 0; n < channels; n++)
++                {
++                    int index = pixel_index + n;
++                    ((float*)output_buffer)[index] = encode_buffer[index];
++                }
++            }
++            break;
++
++        case STBIR__DECODE(STBIR_TYPE_FLOAT, STBIR_COLORSPACE_SRGB):
++            for (x=0; x < num_pixels; ++x)
++            {
++                int pixel_index = x*channels;
++
++                for (n = 0; n < num_nonalpha; n++)
++                {
++                    int index = pixel_index + nonalpha[n];
++                    ((float*)output_buffer)[index] = stbir__linear_to_srgb(encode_buffer[index]);
++                }
++
++                if (!(stbir_info->flags&STBIR_FLAG_ALPHA_USES_COLORSPACE))
++                    ((float*)output_buffer)[pixel_index + alpha_channel] = encode_buffer[pixel_index + alpha_channel];
++            }
++            break;
++
++        default:
++            STBIR_ASSERT(!"Unknown type/colorspace/channels combination.");
++            break;
++    }
++}
++
++static void stbir__resample_vertical_upsample(stbir__info* stbir_info, int n)
++{
++    int x, k;
++    int output_w = stbir_info->output_w;
++    stbir__contributors* vertical_contributors = stbir_info->vertical_contributors;
++    float* vertical_coefficients = stbir_info->vertical_coefficients;
++    int channels = stbir_info->channels;
++    int alpha_channel = stbir_info->alpha_channel;
++    int type = stbir_info->type;
++    int colorspace = stbir_info->colorspace;
++    int ring_buffer_entries = stbir_info->ring_buffer_num_entries;
++    void* output_data = stbir_info->output_data;
++    float* encode_buffer = stbir_info->encode_buffer;
++    int decode = STBIR__DECODE(type, colorspace);
++    int coefficient_width = stbir_info->vertical_coefficient_width;
++    int coefficient_counter;
++    int contributor = n;
++
++    float* ring_buffer = stbir_info->ring_buffer;
++    int ring_buffer_begin_index = stbir_info->ring_buffer_begin_index;
++    int ring_buffer_first_scanline = stbir_info->ring_buffer_first_scanline;
++    int ring_buffer_length = stbir_info->ring_buffer_length_bytes/sizeof(float);
++
++    int n0,n1, output_row_start;
++    int coefficient_group = coefficient_width * contributor;
++
++    n0 = vertical_contributors[contributor].n0;
++    n1 = vertical_contributors[contributor].n1;
++
++    output_row_start = n * stbir_info->output_stride_bytes;
++
++    STBIR_ASSERT(stbir__use_height_upsampling(stbir_info));
++
++    memset(encode_buffer, 0, output_w * sizeof(float) * channels);
++
++    // I tried reblocking this for better cache usage of encode_buffer
++    // (using x_outer, k, x_inner), but it lost speed. -- stb
++
++    coefficient_counter = 0;
++    switch (channels) {
++        case 1:
++            for (k = n0; k <= n1; k++)
++            {
++                int coefficient_index = coefficient_counter++;
++                float* ring_buffer_entry = stbir__get_ring_buffer_scanline(k, ring_buffer, ring_buffer_begin_index, ring_buffer_first_scanline, ring_buffer_entries, ring_buffer_length);
++                float coefficient = vertical_coefficients[coefficient_group + coefficient_index];
++                for (x = 0; x < output_w; ++x)
++                {
++                    int in_pixel_index = x * 1;
++                    encode_buffer[in_pixel_index + 0] += ring_buffer_entry[in_pixel_index + 0] * coefficient;
++                }
++            }
++            break;
++        case 2:
++            for (k = n0; k <= n1; k++)
++            {
++                int coefficient_index = coefficient_counter++;
++                float* ring_buffer_entry = stbir__get_ring_buffer_scanline(k, ring_buffer, ring_buffer_begin_index, ring_buffer_first_scanline, ring_buffer_entries, ring_buffer_length);
++                float coefficient = vertical_coefficients[coefficient_group + coefficient_index];
++                for (x = 0; x < output_w; ++x)
++                {
++                    int in_pixel_index = x * 2;
++                    encode_buffer[in_pixel_index + 0] += ring_buffer_entry[in_pixel_index + 0] * coefficient;
++                    encode_buffer[in_pixel_index + 1] += ring_buffer_entry[in_pixel_index + 1] * coefficient;
++                }
++            }
++            break;
++        case 3:
++            for (k = n0; k <= n1; k++)
++            {
++                int coefficient_index = coefficient_counter++;
++                float* ring_buffer_entry = stbir__get_ring_buffer_scanline(k, ring_buffer, ring_buffer_begin_index, ring_buffer_first_scanline, ring_buffer_entries, ring_buffer_length);
++                float coefficient = vertical_coefficients[coefficient_group + coefficient_index];
++                for (x = 0; x < output_w; ++x)
++                {
++                    int in_pixel_index = x * 3;
++                    encode_buffer[in_pixel_index + 0] += ring_buffer_entry[in_pixel_index + 0] * coefficient;
++                    encode_buffer[in_pixel_index + 1] += ring_buffer_entry[in_pixel_index + 1] * coefficient;
++                    encode_buffer[in_pixel_index + 2] += ring_buffer_entry[in_pixel_index + 2] * coefficient;
++                }
++            }
++            break;
++        case 4:
++            for (k = n0; k <= n1; k++)
++            {
++                int coefficient_index = coefficient_counter++;
++                float* ring_buffer_entry = stbir__get_ring_buffer_scanline(k, ring_buffer, ring_buffer_begin_index, ring_buffer_first_scanline, ring_buffer_entries, ring_buffer_length);
++                float coefficient = vertical_coefficients[coefficient_group + coefficient_index];
++                for (x = 0; x < output_w; ++x)
++                {
++                    int in_pixel_index = x * 4;
++                    encode_buffer[in_pixel_index + 0] += ring_buffer_entry[in_pixel_index + 0] * coefficient;
++                    encode_buffer[in_pixel_index + 1] += ring_buffer_entry[in_pixel_index + 1] * coefficient;
++                    encode_buffer[in_pixel_index + 2] += ring_buffer_entry[in_pixel_index + 2] * coefficient;
++                    encode_buffer[in_pixel_index + 3] += ring_buffer_entry[in_pixel_index + 3] * coefficient;
++                }
++            }
++            break;
++        default:
++            for (k = n0; k <= n1; k++)
++            {
++                int coefficient_index = coefficient_counter++;
++                float* ring_buffer_entry = stbir__get_ring_buffer_scanline(k, ring_buffer, ring_buffer_begin_index, ring_buffer_first_scanline, ring_buffer_entries, ring_buffer_length);
++                float coefficient = vertical_coefficients[coefficient_group + coefficient_index];
++                for (x = 0; x < output_w; ++x)
++                {
++                    int in_pixel_index = x * channels;
++                    int c;
++                    for (c = 0; c < channels; c++)
++                        encode_buffer[in_pixel_index + c] += ring_buffer_entry[in_pixel_index + c] * coefficient;
++                }
++            }
++            break;
++    }
++    stbir__encode_scanline(stbir_info, output_w, (char *) output_data + output_row_start, encode_buffer, channels, alpha_channel, decode);
++}
++
++static void stbir__resample_vertical_downsample(stbir__info* stbir_info, int n)
++{
++    int x, k;
++    int output_w = stbir_info->output_w;
++    stbir__contributors* vertical_contributors = stbir_info->vertical_contributors;
++    float* vertical_coefficients = stbir_info->vertical_coefficients;
++    int channels = stbir_info->channels;
++    int ring_buffer_entries = stbir_info->ring_buffer_num_entries;
++    float* horizontal_buffer = stbir_info->horizontal_buffer;
++    int coefficient_width = stbir_info->vertical_coefficient_width;
++    int contributor = n + stbir_info->vertical_filter_pixel_margin;
++
++    float* ring_buffer = stbir_info->ring_buffer;
++    int ring_buffer_begin_index = stbir_info->ring_buffer_begin_index;
++    int ring_buffer_first_scanline = stbir_info->ring_buffer_first_scanline;
++    int ring_buffer_length = stbir_info->ring_buffer_length_bytes/sizeof(float);
++    int n0,n1;
++
++    n0 = vertical_contributors[contributor].n0;
++    n1 = vertical_contributors[contributor].n1;
++
++    STBIR_ASSERT(!stbir__use_height_upsampling(stbir_info));
++
++    for (k = n0; k <= n1; k++)
++    {
++        int coefficient_index = k - n0;
++        int coefficient_group = coefficient_width * contributor;
++        float coefficient = vertical_coefficients[coefficient_group + coefficient_index];
++
++        float* ring_buffer_entry = stbir__get_ring_buffer_scanline(k, ring_buffer, ring_buffer_begin_index, ring_buffer_first_scanline, ring_buffer_entries, ring_buffer_length);
++
++        switch (channels) {
++            case 1:
++                for (x = 0; x < output_w; x++)
++                {
++                    int in_pixel_index = x * 1;
++                    ring_buffer_entry[in_pixel_index + 0] += horizontal_buffer[in_pixel_index + 0] * coefficient;
++                }
++                break;
++            case 2:
++                for (x = 0; x < output_w; x++)
++                {
++                    int in_pixel_index = x * 2;
++                    ring_buffer_entry[in_pixel_index + 0] += horizontal_buffer[in_pixel_index + 0] * coefficient;
++                    ring_buffer_entry[in_pixel_index + 1] += horizontal_buffer[in_pixel_index + 1] * coefficient;
++                }
++                break;
++            case 3:
++                for (x = 0; x < output_w; x++)
++                {
++                    int in_pixel_index = x * 3;
++                    ring_buffer_entry[in_pixel_index + 0] += horizontal_buffer[in_pixel_index + 0] * coefficient;
++                    ring_buffer_entry[in_pixel_index + 1] += horizontal_buffer[in_pixel_index + 1] * coefficient;
++                    ring_buffer_entry[in_pixel_index + 2] += horizontal_buffer[in_pixel_index + 2] * coefficient;
++                }
++                break;
++            case 4:
++                for (x = 0; x < output_w; x++)
++                {
++                    int in_pixel_index = x * 4;
++                    ring_buffer_entry[in_pixel_index + 0] += horizontal_buffer[in_pixel_index + 0] * coefficient;
++                    ring_buffer_entry[in_pixel_index + 1] += horizontal_buffer[in_pixel_index + 1] * coefficient;
++                    ring_buffer_entry[in_pixel_index + 2] += horizontal_buffer[in_pixel_index + 2] * coefficient;
++                    ring_buffer_entry[in_pixel_index + 3] += horizontal_buffer[in_pixel_index + 3] * coefficient;
++                }
++                break;
++            default:
++                for (x = 0; x < output_w; x++)
++                {
++                    int in_pixel_index = x * channels;
++
++                    int c;
++                    for (c = 0; c < channels; c++)
++                        ring_buffer_entry[in_pixel_index + c] += horizontal_buffer[in_pixel_index + c] * coefficient;
++                }
++                break;
++        }
++    }
++}
++
++static void stbir__buffer_loop_upsample(stbir__info* stbir_info)
++{
++    int y;
++    float scale_ratio = stbir_info->vertical_scale;
++    float out_scanlines_radius = stbir__filter_info_table[stbir_info->vertical_filter].support(1/scale_ratio) * scale_ratio;
++
++    STBIR_ASSERT(stbir__use_height_upsampling(stbir_info));
++
++    for (y = 0; y < stbir_info->output_h; y++)
++    {
++        float in_center_of_out = 0; // Center of the current out scanline in the in scanline space
++        int in_first_scanline = 0, in_last_scanline = 0;
++
++        stbir__calculate_sample_range_upsample(y, out_scanlines_radius, scale_ratio, stbir_info->vertical_shift, &in_first_scanline, &in_last_scanline, &in_center_of_out);
++
++        STBIR_ASSERT(in_last_scanline - in_first_scanline + 1 <= stbir_info->ring_buffer_num_entries);
++
++        if (stbir_info->ring_buffer_begin_index >= 0)
++        {
++            // Get rid of whatever we don't need anymore.
++            while (in_first_scanline > stbir_info->ring_buffer_first_scanline)
++            {
++                if (stbir_info->ring_buffer_first_scanline == stbir_info->ring_buffer_last_scanline)
++                {
++                    // We just popped the last scanline off the ring buffer.
++                    // Reset it to the empty state.
++                    stbir_info->ring_buffer_begin_index = -1;
++                    stbir_info->ring_buffer_first_scanline = 0;
++                    stbir_info->ring_buffer_last_scanline = 0;
++                    break;
++                }
++                else
++                {
++                    stbir_info->ring_buffer_first_scanline++;
++                    stbir_info->ring_buffer_begin_index = (stbir_info->ring_buffer_begin_index + 1) % stbir_info->ring_buffer_num_entries;
++                }
++            }
++        }
++
++        // Load in new ones.
++        if (stbir_info->ring_buffer_begin_index < 0)
++            stbir__decode_and_resample_upsample(stbir_info, in_first_scanline);
++
++        while (in_last_scanline > stbir_info->ring_buffer_last_scanline)
++            stbir__decode_and_resample_upsample(stbir_info, stbir_info->ring_buffer_last_scanline + 1);
++
++        // Now all buffers should be ready to write a row of vertical sampling.
++        stbir__resample_vertical_upsample(stbir_info, y);
++
++        STBIR_PROGRESS_REPORT((float)y / stbir_info->output_h);
++    }
++}
++
++static void stbir__empty_ring_buffer(stbir__info* stbir_info, int first_necessary_scanline)
++{
++    int output_stride_bytes = stbir_info->output_stride_bytes;
++    int channels = stbir_info->channels;
++    int alpha_channel = stbir_info->alpha_channel;
++    int type = stbir_info->type;
++    int colorspace = stbir_info->colorspace;
++    int output_w = stbir_info->output_w;
++    void* output_data = stbir_info->output_data;
++    int decode = STBIR__DECODE(type, colorspace);
++
++    float* ring_buffer = stbir_info->ring_buffer;
++    int ring_buffer_length = stbir_info->ring_buffer_length_bytes/sizeof(float);
++
++    if (stbir_info->ring_buffer_begin_index >= 0)
++    {
++        // Get rid of whatever we don't need anymore.
++        while (first_necessary_scanline > stbir_info->ring_buffer_first_scanline)
++        {
++            if (stbir_info->ring_buffer_first_scanline >= 0 && stbir_info->ring_buffer_first_scanline < stbir_info->output_h)
++            {
++                int output_row_start = stbir_info->ring_buffer_first_scanline * output_stride_bytes;
++                float* ring_buffer_entry = stbir__get_ring_buffer_entry(ring_buffer, stbir_info->ring_buffer_begin_index, ring_buffer_length);
++                stbir__encode_scanline(stbir_info, output_w, (char *) output_data + output_row_start, ring_buffer_entry, channels, alpha_channel, decode);
++                STBIR_PROGRESS_REPORT((float)stbir_info->ring_buffer_first_scanline / stbir_info->output_h);
++            }
++
++            if (stbir_info->ring_buffer_first_scanline == stbir_info->ring_buffer_last_scanline)
++            {
++                // We just popped the last scanline off the ring buffer.
++                // Reset it to the empty state.
++                stbir_info->ring_buffer_begin_index = -1;
++                stbir_info->ring_buffer_first_scanline = 0;
++                stbir_info->ring_buffer_last_scanline = 0;
++                break;
++            }
++            else
++            {
++                stbir_info->ring_buffer_first_scanline++;
++                stbir_info->ring_buffer_begin_index = (stbir_info->ring_buffer_begin_index + 1) % stbir_info->ring_buffer_num_entries;
++            }
++        }
++    }
++}
++
++static void stbir__buffer_loop_downsample(stbir__info* stbir_info)
++{
++    int y;
++    float scale_ratio = stbir_info->vertical_scale;
++    int output_h = stbir_info->output_h;
++    float in_pixels_radius = stbir__filter_info_table[stbir_info->vertical_filter].support(scale_ratio) / scale_ratio;
++    int pixel_margin = stbir_info->vertical_filter_pixel_margin;
++    int max_y = stbir_info->input_h + pixel_margin;
++
++    STBIR_ASSERT(!stbir__use_height_upsampling(stbir_info));
++
++    for (y = -pixel_margin; y < max_y; y++)
++    {
++        float out_center_of_in; // Center of the current out scanline in the in scanline space
++        int out_first_scanline, out_last_scanline;
++
++        stbir__calculate_sample_range_downsample(y, in_pixels_radius, scale_ratio, stbir_info->vertical_shift, &out_first_scanline, &out_last_scanline, &out_center_of_in);
++
++        STBIR_ASSERT(out_last_scanline - out_first_scanline + 1 <= stbir_info->ring_buffer_num_entries);
++
++        if (out_last_scanline < 0 || out_first_scanline >= output_h)
++            continue;
++
++        stbir__empty_ring_buffer(stbir_info, out_first_scanline);
++
++        stbir__decode_and_resample_downsample(stbir_info, y);
++
++        // Load in new ones.
++        if (stbir_info->ring_buffer_begin_index < 0)
++            stbir__add_empty_ring_buffer_entry(stbir_info, out_first_scanline);
++
++        while (out_last_scanline > stbir_info->ring_buffer_last_scanline)
++            stbir__add_empty_ring_buffer_entry(stbir_info, stbir_info->ring_buffer_last_scanline + 1);
++
++        // Now the horizontal buffer is ready to write to all ring buffer rows.
++        stbir__resample_vertical_downsample(stbir_info, y);
++    }
++
++    stbir__empty_ring_buffer(stbir_info, stbir_info->output_h);
++}
++
++static void stbir__setup(stbir__info *info, int input_w, int input_h, int output_w, int output_h, int channels)
++{
++    info->input_w = input_w;
++    info->input_h = input_h;
++    info->output_w = output_w;
++    info->output_h = output_h;
++    info->channels = channels;
++}
++
++static void stbir__calculate_transform(stbir__info *info, float s0, float t0, float s1, float t1, float *transform)
++{
++    info->s0 = s0;
++    info->t0 = t0;
++    info->s1 = s1;
++    info->t1 = t1;
++
++    if (transform)
++    {
++        info->horizontal_scale = transform[0];
++        info->vertical_scale   = transform[1];
++        info->horizontal_shift = transform[2];
++        info->vertical_shift   = transform[3];
++    }
++    else
++    {
++        info->horizontal_scale = ((float)info->output_w / info->input_w) / (s1 - s0);
++        info->vertical_scale = ((float)info->output_h / info->input_h) / (t1 - t0);
++
++        info->horizontal_shift = s0 * info->output_w / (s1 - s0);
++        info->vertical_shift = t0 * info->output_h / (t1 - t0);
++    }
++}
++
++static void stbir__choose_filter(stbir__info *info, stbir_filter h_filter, stbir_filter v_filter)
++{
++    if (h_filter == 0)
++        h_filter = stbir__use_upsampling(info->horizontal_scale) ? STBIR_DEFAULT_FILTER_UPSAMPLE : STBIR_DEFAULT_FILTER_DOWNSAMPLE;
++    if (v_filter == 0)
++        v_filter = stbir__use_upsampling(info->vertical_scale)   ? STBIR_DEFAULT_FILTER_UPSAMPLE : STBIR_DEFAULT_FILTER_DOWNSAMPLE;
++    info->horizontal_filter = h_filter;
++    info->vertical_filter = v_filter;
++}
++
++static stbir_uint32 stbir__calculate_memory(stbir__info *info)
++{
++    int pixel_margin = stbir__get_filter_pixel_margin(info->horizontal_filter, info->horizontal_scale);
++    int filter_height = stbir__get_filter_pixel_width(info->vertical_filter, info->vertical_scale);
++
++    info->horizontal_num_contributors = stbir__get_contributors(info->horizontal_scale, info->horizontal_filter, info->input_w, info->output_w);
++    info->vertical_num_contributors   = stbir__get_contributors(info->vertical_scale  , info->vertical_filter  , info->input_h, info->output_h);
++
++    // One extra entry because floating point precision problems sometimes cause an extra to be necessary.
++    info->ring_buffer_num_entries = filter_height + 1;
++
++    info->horizontal_contributors_size = info->horizontal_num_contributors * sizeof(stbir__contributors);
++    info->horizontal_coefficients_size = stbir__get_total_horizontal_coefficients(info) * sizeof(float);
++    info->vertical_contributors_size = info->vertical_num_contributors * sizeof(stbir__contributors);
++    info->vertical_coefficients_size = stbir__get_total_vertical_coefficients(info) * sizeof(float);
++    info->decode_buffer_size = (info->input_w + pixel_margin * 2) * info->channels * sizeof(float);
++    info->horizontal_buffer_size = info->output_w * info->channels * sizeof(float);
++    info->ring_buffer_size = info->output_w * info->channels * info->ring_buffer_num_entries * sizeof(float);
++    info->encode_buffer_size = info->output_w * info->channels * sizeof(float);
++
++    STBIR_ASSERT(info->horizontal_filter != 0);
++    STBIR_ASSERT(info->horizontal_filter < STBIR__ARRAY_SIZE(stbir__filter_info_table)); // this now happens too late
++    STBIR_ASSERT(info->vertical_filter != 0);
++    STBIR_ASSERT(info->vertical_filter < STBIR__ARRAY_SIZE(stbir__filter_info_table)); // this now happens too late
++
++    if (stbir__use_height_upsampling(info))
++        // The horizontal buffer is for when we're downsampling the height and we
++        // can't output the result of sampling the decode buffer directly into the
++        // ring buffers.
++        info->horizontal_buffer_size = 0;
++    else
++        // The encode buffer is to retain precision in the height upsampling method
++        // and isn't used when height downsampling.
++        info->encode_buffer_size = 0;
++
++    return info->horizontal_contributors_size + info->horizontal_coefficients_size
++        + info->vertical_contributors_size + info->vertical_coefficients_size
++        + info->decode_buffer_size + info->horizontal_buffer_size
++        + info->ring_buffer_size + info->encode_buffer_size;
++}
++
++static int stbir__resize_allocated(stbir__info *info,
++    const void* input_data, int input_stride_in_bytes,
++    void* output_data, int output_stride_in_bytes,
++    int alpha_channel, stbir_uint32 flags, stbir_datatype type,
++    stbir_edge edge_horizontal, stbir_edge edge_vertical, stbir_colorspace colorspace,
++    void* tempmem, size_t tempmem_size_in_bytes)
++{
++    size_t memory_required = stbir__calculate_memory(info);
++
++    int width_stride_input = input_stride_in_bytes ? input_stride_in_bytes : info->channels * info->input_w * stbir__type_size[type];
++    int width_stride_output = output_stride_in_bytes ? output_stride_in_bytes : info->channels * info->output_w * stbir__type_size[type];
++
++#ifdef STBIR_DEBUG_OVERWRITE_TEST
++#define OVERWRITE_ARRAY_SIZE 8
++    unsigned char overwrite_output_before_pre[OVERWRITE_ARRAY_SIZE];
++    unsigned char overwrite_tempmem_before_pre[OVERWRITE_ARRAY_SIZE];
++    unsigned char overwrite_output_after_pre[OVERWRITE_ARRAY_SIZE];
++    unsigned char overwrite_tempmem_after_pre[OVERWRITE_ARRAY_SIZE];
++
++    size_t begin_forbidden = width_stride_output * (info->output_h - 1) + info->output_w * info->channels * stbir__type_size[type];
++    memcpy(overwrite_output_before_pre, &((unsigned char*)output_data)[-OVERWRITE_ARRAY_SIZE], OVERWRITE_ARRAY_SIZE);
++    memcpy(overwrite_output_after_pre, &((unsigned char*)output_data)[begin_forbidden], OVERWRITE_ARRAY_SIZE);
++    memcpy(overwrite_tempmem_before_pre, &((unsigned char*)tempmem)[-OVERWRITE_ARRAY_SIZE], OVERWRITE_ARRAY_SIZE);
++    memcpy(overwrite_tempmem_after_pre, &((unsigned char*)tempmem)[tempmem_size_in_bytes], OVERWRITE_ARRAY_SIZE);
++#endif
++
++    STBIR_ASSERT(info->channels >= 0);
++    STBIR_ASSERT(info->channels <= STBIR_MAX_CHANNELS);
++
++    if (info->channels < 0 || info->channels > STBIR_MAX_CHANNELS)
++        return 0;
++
++    STBIR_ASSERT(info->horizontal_filter < STBIR__ARRAY_SIZE(stbir__filter_info_table));
++    STBIR_ASSERT(info->vertical_filter < STBIR__ARRAY_SIZE(stbir__filter_info_table));
++
++    if (info->horizontal_filter >= STBIR__ARRAY_SIZE(stbir__filter_info_table))
++        return 0;
++    if (info->vertical_filter >= STBIR__ARRAY_SIZE(stbir__filter_info_table))
++        return 0;
++
++    if (alpha_channel < 0)
++        flags |= STBIR_FLAG_ALPHA_USES_COLORSPACE | STBIR_FLAG_ALPHA_PREMULTIPLIED;
++
++    if (!(flags&STBIR_FLAG_ALPHA_USES_COLORSPACE) || !(flags&STBIR_FLAG_ALPHA_PREMULTIPLIED))
++        STBIR_ASSERT(alpha_channel >= 0 && alpha_channel < info->channels);
++
++    if (alpha_channel >= info->channels)
++        return 0;
++
++    STBIR_ASSERT(tempmem);
++
++    if (!tempmem)
++        return 0;
++
++    STBIR_ASSERT(tempmem_size_in_bytes >= memory_required);
++
++    if (tempmem_size_in_bytes < memory_required)
++        return 0;
++
++    memset(tempmem, 0, tempmem_size_in_bytes);
++
++    info->input_data = input_data;
++    info->input_stride_bytes = width_stride_input;
++
++    info->output_data = output_data;
++    info->output_stride_bytes = width_stride_output;
++
++    info->alpha_channel = alpha_channel;
++    info->flags = flags;
++    info->type = type;
++    info->edge_horizontal = edge_horizontal;
++    info->edge_vertical = edge_vertical;
++    info->colorspace = colorspace;
++
++    info->horizontal_coefficient_width   = stbir__get_coefficient_width  (info->horizontal_filter, info->horizontal_scale);
++    info->vertical_coefficient_width     = stbir__get_coefficient_width  (info->vertical_filter  , info->vertical_scale  );
++    info->horizontal_filter_pixel_width  = stbir__get_filter_pixel_width (info->horizontal_filter, info->horizontal_scale);
++    info->vertical_filter_pixel_width    = stbir__get_filter_pixel_width (info->vertical_filter  , info->vertical_scale  );
++    info->horizontal_filter_pixel_margin = stbir__get_filter_pixel_margin(info->horizontal_filter, info->horizontal_scale);
++    info->vertical_filter_pixel_margin   = stbir__get_filter_pixel_margin(info->vertical_filter  , info->vertical_scale  );
++
++    info->ring_buffer_length_bytes = info->output_w * info->channels * sizeof(float);
++    info->decode_buffer_pixels = info->input_w + info->horizontal_filter_pixel_margin * 2;
++
++#define STBIR__NEXT_MEMPTR(current, newtype) (newtype*)(((unsigned char*)current) + current##_size)
++
++    info->horizontal_contributors = (stbir__contributors *) tempmem;
++    info->horizontal_coefficients = STBIR__NEXT_MEMPTR(info->horizontal_contributors, float);
++    info->vertical_contributors = STBIR__NEXT_MEMPTR(info->horizontal_coefficients, stbir__contributors);
++    info->vertical_coefficients = STBIR__NEXT_MEMPTR(info->vertical_contributors, float);
++    info->decode_buffer = STBIR__NEXT_MEMPTR(info->vertical_coefficients, float);
++
++    if (stbir__use_height_upsampling(info))
++    {
++        info->horizontal_buffer = NULL;
++        info->ring_buffer = STBIR__NEXT_MEMPTR(info->decode_buffer, float);
++        info->encode_buffer = STBIR__NEXT_MEMPTR(info->ring_buffer, float);
++
++        STBIR_ASSERT((size_t)STBIR__NEXT_MEMPTR(info->encode_buffer, unsigned char) == (size_t)tempmem + tempmem_size_in_bytes);
++    }
++    else
++    {
++        info->horizontal_buffer = STBIR__NEXT_MEMPTR(info->decode_buffer, float);
++        info->ring_buffer = STBIR__NEXT_MEMPTR(info->horizontal_buffer, float);
++        info->encode_buffer = NULL;
++
++        STBIR_ASSERT((size_t)STBIR__NEXT_MEMPTR(info->ring_buffer, unsigned char) == (size_t)tempmem + tempmem_size_in_bytes);
++    }
++
++#undef STBIR__NEXT_MEMPTR
++
++    // This signals that the ring buffer is empty
++    info->ring_buffer_begin_index = -1;
++
++    stbir__calculate_filters(info->horizontal_contributors, info->horizontal_coefficients, info->horizontal_filter, info->horizontal_scale, info->horizontal_shift, info->input_w, info->output_w);
++    stbir__calculate_filters(info->vertical_contributors, info->vertical_coefficients, info->vertical_filter, info->vertical_scale, info->vertical_shift, info->input_h, info->output_h);
++
++    STBIR_PROGRESS_REPORT(0);
++
++    if (stbir__use_height_upsampling(info))
++        stbir__buffer_loop_upsample(info);
++    else
++        stbir__buffer_loop_downsample(info);
++
++    STBIR_PROGRESS_REPORT(1);
++
++#ifdef STBIR_DEBUG_OVERWRITE_TEST
++    STBIR_ASSERT(memcmp(overwrite_output_before_pre, &((unsigned char*)output_data)[-OVERWRITE_ARRAY_SIZE], OVERWRITE_ARRAY_SIZE) == 0);
++    STBIR_ASSERT(memcmp(overwrite_output_after_pre, &((unsigned char*)output_data)[begin_forbidden], OVERWRITE_ARRAY_SIZE) == 0);
++    STBIR_ASSERT(memcmp(overwrite_tempmem_before_pre, &((unsigned char*)tempmem)[-OVERWRITE_ARRAY_SIZE], OVERWRITE_ARRAY_SIZE) == 0);
++    STBIR_ASSERT(memcmp(overwrite_tempmem_after_pre, &((unsigned char*)tempmem)[tempmem_size_in_bytes], OVERWRITE_ARRAY_SIZE) == 0);
++#endif
++
++    return 1;
++}
++
++
++static int stbir__resize_arbitrary(
++    void *alloc_context,
++    const void* input_data, int input_w, int input_h, int input_stride_in_bytes,
++    void* output_data, int output_w, int output_h, int output_stride_in_bytes,
++    float s0, float t0, float s1, float t1, float *transform,
++    int channels, int alpha_channel, stbir_uint32 flags, stbir_datatype type,
++    stbir_filter h_filter, stbir_filter v_filter,
++    stbir_edge edge_horizontal, stbir_edge edge_vertical, stbir_colorspace colorspace)
++{
++    stbir__info info;
++    int result;
++    size_t memory_required;
++    void* extra_memory;
++
++    stbir__setup(&info, input_w, input_h, output_w, output_h, channels);
++    stbir__calculate_transform(&info, s0,t0,s1,t1,transform);
++    stbir__choose_filter(&info, h_filter, v_filter);
++    memory_required = stbir__calculate_memory(&info);
++    extra_memory = STBIR_MALLOC(memory_required, alloc_context);
++
++    if (!extra_memory)
++        return 0;
++
++    result = stbir__resize_allocated(&info, input_data, input_stride_in_bytes,
++                                            output_data, output_stride_in_bytes, 
++                                            alpha_channel, flags, type,
++                                            edge_horizontal, edge_vertical,
++                                            colorspace, extra_memory, memory_required);
++
++    STBIR_FREE(extra_memory, alloc_context);
++
++    return result;
++}
++
++STBIRDEF int stbir_resize_uint8(     const unsigned char *input_pixels , int input_w , int input_h , int input_stride_in_bytes,
++                                           unsigned char *output_pixels, int output_w, int output_h, int output_stride_in_bytes,
++                                     int num_channels)
++{
++    return stbir__resize_arbitrary(NULL, input_pixels, input_w, input_h, input_stride_in_bytes,
++        output_pixels, output_w, output_h, output_stride_in_bytes,
++        0,0,1,1,NULL,num_channels,-1,0, STBIR_TYPE_UINT8, STBIR_FILTER_DEFAULT, STBIR_FILTER_DEFAULT,
++        STBIR_EDGE_CLAMP, STBIR_EDGE_CLAMP, STBIR_COLORSPACE_LINEAR);
++}
++
++STBIRDEF int stbir_resize_float(     const float *input_pixels , int input_w , int input_h , int input_stride_in_bytes,
++                                           float *output_pixels, int output_w, int output_h, int output_stride_in_bytes,
++                                     int num_channels)
++{
++    return stbir__resize_arbitrary(NULL, input_pixels, input_w, input_h, input_stride_in_bytes,
++        output_pixels, output_w, output_h, output_stride_in_bytes,
++        0,0,1,1,NULL,num_channels,-1,0, STBIR_TYPE_FLOAT, STBIR_FILTER_DEFAULT, STBIR_FILTER_DEFAULT,
++        STBIR_EDGE_CLAMP, STBIR_EDGE_CLAMP, STBIR_COLORSPACE_LINEAR);
++}
++
++STBIRDEF int stbir_resize_uint8_srgb(const unsigned char *input_pixels , int input_w , int input_h , int input_stride_in_bytes,
++                                           unsigned char *output_pixels, int output_w, int output_h, int output_stride_in_bytes,
++                                     int num_channels, int alpha_channel, int flags)
++{
++    return stbir__resize_arbitrary(NULL, input_pixels, input_w, input_h, input_stride_in_bytes,
++        output_pixels, output_w, output_h, output_stride_in_bytes,
++        0,0,1,1,NULL,num_channels,alpha_channel,flags, STBIR_TYPE_UINT8, STBIR_FILTER_DEFAULT, STBIR_FILTER_DEFAULT,
++        STBIR_EDGE_CLAMP, STBIR_EDGE_CLAMP, STBIR_COLORSPACE_SRGB);
++}
++
++STBIRDEF int stbir_resize_uint8_srgb_edgemode(const unsigned char *input_pixels , int input_w , int input_h , int input_stride_in_bytes,
++                                                    unsigned char *output_pixels, int output_w, int output_h, int output_stride_in_bytes,
++                                              int num_channels, int alpha_channel, int flags,
++                                              stbir_edge edge_wrap_mode)
++{
++    return stbir__resize_arbitrary(NULL, input_pixels, input_w, input_h, input_stride_in_bytes,
++        output_pixels, output_w, output_h, output_stride_in_bytes,
++        0,0,1,1,NULL,num_channels,alpha_channel,flags, STBIR_TYPE_UINT8, STBIR_FILTER_DEFAULT, STBIR_FILTER_DEFAULT,
++        edge_wrap_mode, edge_wrap_mode, STBIR_COLORSPACE_SRGB);
++}
++
++STBIRDEF int stbir_resize_uint8_generic( const unsigned char *input_pixels , int input_w , int input_h , int input_stride_in_bytes,
++                                               unsigned char *output_pixels, int output_w, int output_h, int output_stride_in_bytes,
++                                         int num_channels, int alpha_channel, int flags,
++                                         stbir_edge edge_wrap_mode, stbir_filter filter, stbir_colorspace space, 
++                                         void *alloc_context)
++{
++    return stbir__resize_arbitrary(alloc_context, input_pixels, input_w, input_h, input_stride_in_bytes,
++        output_pixels, output_w, output_h, output_stride_in_bytes,
++        0,0,1,1,NULL,num_channels,alpha_channel,flags, STBIR_TYPE_UINT8, filter, filter,
++        edge_wrap_mode, edge_wrap_mode, space);
++}
++
++STBIRDEF int stbir_resize_uint16_generic(const stbir_uint16 *input_pixels  , int input_w , int input_h , int input_stride_in_bytes,
++                                               stbir_uint16 *output_pixels , int output_w, int output_h, int output_stride_in_bytes,
++                                         int num_channels, int alpha_channel, int flags,
++                                         stbir_edge edge_wrap_mode, stbir_filter filter, stbir_colorspace space, 
++                                         void *alloc_context)
++{
++    return stbir__resize_arbitrary(alloc_context, input_pixels, input_w, input_h, input_stride_in_bytes,
++        output_pixels, output_w, output_h, output_stride_in_bytes,
++        0,0,1,1,NULL,num_channels,alpha_channel,flags, STBIR_TYPE_UINT16, filter, filter,
++        edge_wrap_mode, edge_wrap_mode, space);
++}
++
++
++STBIRDEF int stbir_resize_float_generic( const float *input_pixels         , int input_w , int input_h , int input_stride_in_bytes,
++                                               float *output_pixels        , int output_w, int output_h, int output_stride_in_bytes,
++                                         int num_channels, int alpha_channel, int flags,
++                                         stbir_edge edge_wrap_mode, stbir_filter filter, stbir_colorspace space, 
++                                         void *alloc_context)
++{
++    return stbir__resize_arbitrary(alloc_context, input_pixels, input_w, input_h, input_stride_in_bytes,
++        output_pixels, output_w, output_h, output_stride_in_bytes,
++        0,0,1,1,NULL,num_channels,alpha_channel,flags, STBIR_TYPE_FLOAT, filter, filter,
++        edge_wrap_mode, edge_wrap_mode, space);
++}
++
++
++STBIRDEF int stbir_resize(         const void *input_pixels , int input_w , int input_h , int input_stride_in_bytes,
++                                         void *output_pixels, int output_w, int output_h, int output_stride_in_bytes,
++                                   stbir_datatype datatype,
++                                   int num_channels, int alpha_channel, int flags,
++                                   stbir_edge edge_mode_horizontal, stbir_edge edge_mode_vertical, 
++                                   stbir_filter filter_horizontal,  stbir_filter filter_vertical,
++                                   stbir_colorspace space, void *alloc_context)
++{
++    return stbir__resize_arbitrary(alloc_context, input_pixels, input_w, input_h, input_stride_in_bytes,
++        output_pixels, output_w, output_h, output_stride_in_bytes,
++        0,0,1,1,NULL,num_channels,alpha_channel,flags, datatype, filter_horizontal, filter_vertical,
++        edge_mode_horizontal, edge_mode_vertical, space);
++}
++
++
++STBIRDEF int stbir_resize_subpixel(const void *input_pixels , int input_w , int input_h , int input_stride_in_bytes,
++                                         void *output_pixels, int output_w, int output_h, int output_stride_in_bytes,
++                                   stbir_datatype datatype,
++                                   int num_channels, int alpha_channel, int flags,
++                                   stbir_edge edge_mode_horizontal, stbir_edge edge_mode_vertical, 
++                                   stbir_filter filter_horizontal,  stbir_filter filter_vertical,
++                                   stbir_colorspace space, void *alloc_context,
++                                   float x_scale, float y_scale,
++                                   float x_offset, float y_offset)
++{
++    float transform[4];
++    transform[0] = x_scale;
++    transform[1] = y_scale;
++    transform[2] = x_offset;
++    transform[3] = y_offset;
++    return stbir__resize_arbitrary(alloc_context, input_pixels, input_w, input_h, input_stride_in_bytes,
++        output_pixels, output_w, output_h, output_stride_in_bytes,
++        0,0,1,1,transform,num_channels,alpha_channel,flags, datatype, filter_horizontal, filter_vertical,
++        edge_mode_horizontal, edge_mode_vertical, space);
++}
++
++STBIRDEF int stbir_resize_region(  const void *input_pixels , int input_w , int input_h , int input_stride_in_bytes,
++                                         void *output_pixels, int output_w, int output_h, int output_stride_in_bytes,
++                                   stbir_datatype datatype,
++                                   int num_channels, int alpha_channel, int flags,
++                                   stbir_edge edge_mode_horizontal, stbir_edge edge_mode_vertical, 
++                                   stbir_filter filter_horizontal,  stbir_filter filter_vertical,
++                                   stbir_colorspace space, void *alloc_context,
++                                   float s0, float t0, float s1, float t1)
++{
++    return stbir__resize_arbitrary(alloc_context, input_pixels, input_w, input_h, input_stride_in_bytes,
++        output_pixels, output_w, output_h, output_stride_in_bytes,
++        s0,t0,s1,t1,NULL,num_channels,alpha_channel,flags, datatype, filter_horizontal, filter_vertical,
++        edge_mode_horizontal, edge_mode_vertical, space);
++}
++
++#endif // STB_IMAGE_RESIZE_IMPLEMENTATION
++
++/*
++------------------------------------------------------------------------------
++This software is available under 2 licenses -- choose whichever you prefer.
++------------------------------------------------------------------------------
++ALTERNATIVE A - MIT License
++Copyright (c) 2017 Sean Barrett
++Permission is hereby granted, free of charge, to any person obtaining a copy of 
++this software and associated documentation files (the "Software"), to deal in 
++the Software without restriction, including without limitation the rights to 
++use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 
++of the Software, and to permit persons to whom the Software is furnished to do 
++so, subject to the following conditions:
++The above copyright notice and this permission notice shall be included in all 
++copies or substantial portions of the Software.
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 
++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 
++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 
++SOFTWARE.
++------------------------------------------------------------------------------
++ALTERNATIVE B - Public Domain (www.unlicense.org)
++This is free and unencumbered software released into the public domain.
++Anyone is free to copy, modify, publish, use, compile, sell, or distribute this 
++software, either in source code form or as a compiled binary, for any purpose, 
++commercial or non-commercial, and by any means.
++In jurisdictions that recognize copyright laws, the author or authors of this 
++software dedicate any and all copyright interest in the software to the public 
++domain. We make this dedication for the benefit of the public at large and to 
++the detriment of our heirs and successors. We intend this dedication to be an 
++overt act of relinquishment in perpetuity of all present and future rights to 
++this software under copyright law.
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 
++AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 
++ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++------------------------------------------------------------------------------
++*/
+diff --git a/scripts/pic2logo-include/stb_image/stb_image_write.h b/scripts/pic2logo-include/stb_image/stb_image_write.h
+new file mode 100644
+index 000000000..b6e717818
+--- /dev/null
++++ b/scripts/pic2logo-include/stb_image/stb_image_write.h
+@@ -0,0 +1,1568 @@
++/* stb_image_write - v1.09 - public domain - http://nothings.org/stb/stb_image_write.h
++   writes out PNG/BMP/TGA/JPEG/HDR images to C stdio - Sean Barrett 2010-2015
++                                     no warranty implied; use at your own risk
++
++   Before #including,
++
++       #define STB_IMAGE_WRITE_IMPLEMENTATION
++
++   in the file that you want to have the implementation.
++
++   Will probably not work correctly with strict-aliasing optimizations.
++
++   If using a modern Microsoft Compiler, non-safe versions of CRT calls may cause
++   compilation warnings or even errors. To avoid this, also before #including,
++
++       #define STBI_MSC_SECURE_CRT
++
++ABOUT:
++
++   This header file is a library for writing images to C stdio. It could be
++   adapted to write to memory or a general streaming interface; let me know.
++
++   The PNG output is not optimal; it is 20-50% larger than the file
++   written by a decent optimizing implementation; though providing a custom
++   zlib compress function (see STBIW_ZLIB_COMPRESS) can mitigate that.
++   This library is designed for source code compactness and simplicity,
++   not optimal image file size or run-time performance.
++
++BUILDING:
++
++   You can #define STBIW_ASSERT(x) before the #include to avoid using assert.h.
++   You can #define STBIW_MALLOC(), STBIW_REALLOC(), and STBIW_FREE() to replace
++   malloc,realloc,free.
++   You can #define STBIW_MEMMOVE() to replace memmove()
++   You can #define STBIW_ZLIB_COMPRESS to use a custom zlib-style compress function
++   for PNG compression (instead of the builtin one), it must have the following signature:
++   unsigned char * my_compress(unsigned char *data, int data_len, int *out_len, int quality);
++   The returned data will be freed with STBIW_FREE() (free() by default),
++   so it must be heap allocated with STBIW_MALLOC() (malloc() by default),
++
++USAGE:
++
++   There are five functions, one for each image file format:
++
++     int stbi_write_png(char const *filename, int w, int h, int comp, const void *data, int stride_in_bytes);
++     int stbi_write_bmp(char const *filename, int w, int h, int comp, const void *data);
++     int stbi_write_tga(char const *filename, int w, int h, int comp, const void *data);
++     int stbi_write_jpg(char const *filename, int w, int h, int comp, const void *data, int quality);
++     int stbi_write_hdr(char const *filename, int w, int h, int comp, const float *data);
++
++     void stbi_flip_vertically_on_write(int flag); // flag is non-zero to flip data vertically
++
++   There are also five equivalent functions that use an arbitrary write function. You are
++   expected to open/close your file-equivalent before and after calling these:
++
++     int stbi_write_png_to_func(stbi_write_func *func, void *context, int w, int h, int comp, const void  *data, int stride_in_bytes);
++     int stbi_write_bmp_to_func(stbi_write_func *func, void *context, int w, int h, int comp, const void  *data);
++     int stbi_write_tga_to_func(stbi_write_func *func, void *context, int w, int h, int comp, const void  *data);
++     int stbi_write_hdr_to_func(stbi_write_func *func, void *context, int w, int h, int comp, const float *data);
++     int stbi_write_jpg_to_func(stbi_write_func *func, void *context, int x, int y, int comp, const void *data, int quality);
++
++   where the callback is:
++      void stbi_write_func(void *context, void *data, int size);
++
++   You can configure it with these global variables:
++      int stbi_write_tga_with_rle;             // defaults to true; set to 0 to disable RLE
++      int stbi_write_png_compression_level;    // defaults to 8; set to higher for more compression
++      int stbi_write_force_png_filter;         // defaults to -1; set to 0..5 to force a filter mode
++
++
++   You can define STBI_WRITE_NO_STDIO to disable the file variant of these
++   functions, so the library will not use stdio.h at all. However, this will
++   also disable HDR writing, because it requires stdio for formatted output.
++
++   Each function returns 0 on failure and non-0 on success.
++
++   The functions create an image file defined by the parameters. The image
++   is a rectangle of pixels stored from left-to-right, top-to-bottom.
++   Each pixel contains 'comp' channels of data stored interleaved with 8-bits
++   per channel, in the following order: 1=Y, 2=YA, 3=RGB, 4=RGBA. (Y is
++   monochrome color.) The rectangle is 'w' pixels wide and 'h' pixels tall.
++   The *data pointer points to the first byte of the top-left-most pixel.
++   For PNG, "stride_in_bytes" is the distance in bytes from the first byte of
++   a row of pixels to the first byte of the next row of pixels.
++
++   PNG creates output files with the same number of components as the input.
++   The BMP format expands Y to RGB in the file format and does not
++   output alpha.
++
++   PNG supports writing rectangles of data even when the bytes storing rows of
++   data are not consecutive in memory (e.g. sub-rectangles of a larger image),
++   by supplying the stride between the beginning of adjacent rows. The other
++   formats do not. (Thus you cannot write a native-format BMP through the BMP
++   writer, both because it is in BGR order and because it may have padding
++   at the end of the line.)
++
++   PNG allows you to set the deflate compression level by setting the global
++   variable 'stbi_write_png_compression_level' (it defaults to 8).
++
++   HDR expects linear float data. Since the format is always 32-bit rgb(e)
++   data, alpha (if provided) is discarded, and for monochrome data it is
++   replicated across all three channels.
++
++   TGA supports RLE or non-RLE compressed data. To use non-RLE-compressed
++   data, set the global variable 'stbi_write_tga_with_rle' to 0.
++
++   JPEG does ignore alpha channels in input data; quality is between 1 and 100.
++   Higher quality looks better but results in a bigger image.
++   JPEG baseline (no JPEG progressive).
++
++CREDITS:
++
++
++   Sean Barrett           -    PNG/BMP/TGA
++   Baldur Karlsson        -    HDR
++   Jean-Sebastien Guay    -    TGA monochrome
++   Tim Kelsey             -    misc enhancements
++   Alan Hickman           -    TGA RLE
++   Emmanuel Julien        -    initial file IO callback implementation
++   Jon Olick              -    original jo_jpeg.cpp code
++   Daniel Gibson          -    integrate JPEG, allow external zlib
++   Aarni Koskela          -    allow choosing PNG filter
++
++   bugfixes:
++      github:Chribba
++      Guillaume Chereau
++      github:jry2
++      github:romigrou
++      Sergio Gonzalez
++      Jonas Karlsson
++      Filip Wasil
++      Thatcher Ulrich
++      github:poppolopoppo
++      Patrick Boettcher
++      github:xeekworx
++      Cap Petschulat
++      Simon Rodriguez
++      Ivan Tikhonov
++      github:ignotion
++      Adam Schackart
++
++LICENSE
++
++  See end of file for license information.
++
++*/
++
++#ifndef INCLUDE_STB_IMAGE_WRITE_H
++#define INCLUDE_STB_IMAGE_WRITE_H
++
++// if STB_IMAGE_WRITE_STATIC causes problems, try defining STBIWDEF to 'inline' or 'static inline'
++#ifndef STBIWDEF
++#ifdef STB_IMAGE_WRITE_STATIC
++#define STBIWDEF  static
++#else
++#ifdef __cplusplus
++#define STBIWDEF  extern "C"
++#else
++#define STBIWDEF  extern
++#endif
++#endif
++#endif
++
++#ifndef STB_IMAGE_WRITE_STATIC  // C++ forbids static forward declarations
++extern int stbi_write_tga_with_rle;
++extern int stbi_write_png_compression_level;
++extern int stbi_write_force_png_filter;
++#endif
++
++#ifndef STBI_WRITE_NO_STDIO
++STBIWDEF int stbi_write_png(char const *filename, int w, int h, int comp, const void  *data, int stride_in_bytes);
++STBIWDEF int stbi_write_bmp(char const *filename, int w, int h, int comp, const void  *data);
++STBIWDEF int stbi_write_tga(char const *filename, int w, int h, int comp, const void  *data);
++STBIWDEF int stbi_write_hdr(char const *filename, int w, int h, int comp, const float *data);
++STBIWDEF int stbi_write_jpg(char const *filename, int x, int y, int comp, const void  *data, int quality);
++#endif
++
++typedef void stbi_write_func(void *context, void *data, int size);
++
++STBIWDEF int stbi_write_png_to_func(stbi_write_func *func, void *context, int w, int h, int comp, const void  *data, int stride_in_bytes);
++STBIWDEF int stbi_write_bmp_to_func(stbi_write_func *func, void *context, int w, int h, int comp, const void  *data);
++STBIWDEF int stbi_write_tga_to_func(stbi_write_func *func, void *context, int w, int h, int comp, const void  *data);
++STBIWDEF int stbi_write_hdr_to_func(stbi_write_func *func, void *context, int w, int h, int comp, const float *data);
++STBIWDEF int stbi_write_jpg_to_func(stbi_write_func *func, void *context, int x, int y, int comp, const void  *data, int quality);
++
++STBIWDEF void stbi_flip_vertically_on_write(int flip_boolean);
++
++#endif//INCLUDE_STB_IMAGE_WRITE_H
++
++#ifdef STB_IMAGE_WRITE_IMPLEMENTATION
++
++#ifdef _WIN32
++   #ifndef _CRT_SECURE_NO_WARNINGS
++   #define _CRT_SECURE_NO_WARNINGS
++   #endif
++   #ifndef _CRT_NONSTDC_NO_DEPRECATE
++   #define _CRT_NONSTDC_NO_DEPRECATE
++   #endif
++#endif
++
++#ifndef STBI_WRITE_NO_STDIO
++#include <stdio.h>
++#endif // STBI_WRITE_NO_STDIO
++
++#include <stdarg.h>
++#include <stdlib.h>
++#include <string.h>
++#include <math.h>
++
++#if defined(STBIW_MALLOC) && defined(STBIW_FREE) && (defined(STBIW_REALLOC) || defined(STBIW_REALLOC_SIZED))
++// ok
++#elif !defined(STBIW_MALLOC) && !defined(STBIW_FREE) && !defined(STBIW_REALLOC) && !defined(STBIW_REALLOC_SIZED)
++// ok
++#else
++#error "Must define all or none of STBIW_MALLOC, STBIW_FREE, and STBIW_REALLOC (or STBIW_REALLOC_SIZED)."
++#endif
++
++#ifndef STBIW_MALLOC
++#define STBIW_MALLOC(sz)        malloc(sz)
++#define STBIW_REALLOC(p,newsz)  realloc(p,newsz)
++#define STBIW_FREE(p)           free(p)
++#endif
++
++#ifndef STBIW_REALLOC_SIZED
++#define STBIW_REALLOC_SIZED(p,oldsz,newsz) STBIW_REALLOC(p,newsz)
++#endif
++
++
++#ifndef STBIW_MEMMOVE
++#define STBIW_MEMMOVE(a,b,sz) memmove(a,b,sz)
++#endif
++
++
++#ifndef STBIW_ASSERT
++#include <assert.h>
++#define STBIW_ASSERT(x) assert(x)
++#endif
++
++#define STBIW_UCHAR(x) (unsigned char) ((x) & 0xff)
++
++#ifdef STB_IMAGE_WRITE_STATIC
++static int stbi__flip_vertically_on_write=0;
++static int stbi_write_png_compression_level = 8;
++static int stbi_write_tga_with_rle = 1;
++static int stbi_write_force_png_filter = -1;
++#else
++int stbi_write_png_compression_level = 8;
++int stbi__flip_vertically_on_write=0;
++int stbi_write_tga_with_rle = 1;
++int stbi_write_force_png_filter = -1;
++#endif
++
++STBIWDEF void stbi_flip_vertically_on_write(int flag)
++{
++   stbi__flip_vertically_on_write = flag;
++}
++
++typedef struct
++{
++   stbi_write_func *func;
++   void *context;
++} stbi__write_context;
++
++// initialize a callback-based context
++static void stbi__start_write_callbacks(stbi__write_context *s, stbi_write_func *c, void *context)
++{
++   s->func    = c;
++   s->context = context;
++}
++
++#ifndef STBI_WRITE_NO_STDIO
++
++static void stbi__stdio_write(void *context, void *data, int size)
++{
++   fwrite(data,1,size,(FILE*) context);
++}
++
++static int stbi__start_write_file(stbi__write_context *s, const char *filename)
++{
++   FILE *f;
++#ifdef STBI_MSC_SECURE_CRT
++   if (fopen_s(&f, filename, "wb"))
++      f = NULL;
++#else
++   f = fopen(filename, "wb");
++#endif
++   stbi__start_write_callbacks(s, stbi__stdio_write, (void *) f);
++   return f != NULL;
++}
++
++static void stbi__end_write_file(stbi__write_context *s)
++{
++   fclose((FILE *)s->context);
++}
++
++#endif // !STBI_WRITE_NO_STDIO
++
++typedef unsigned int stbiw_uint32;
++typedef int stb_image_write_test[sizeof(stbiw_uint32)==4 ? 1 : -1];
++
++static void stbiw__writefv(stbi__write_context *s, const char *fmt, va_list v)
++{
++   while (*fmt) {
++      switch (*fmt++) {
++         case ' ': break;
++         case '1': { unsigned char x = STBIW_UCHAR(va_arg(v, int));
++                     s->func(s->context,&x,1);
++                     break; }
++         case '2': { int x = va_arg(v,int);
++                     unsigned char b[2];
++                     b[0] = STBIW_UCHAR(x);
++                     b[1] = STBIW_UCHAR(x>>8);
++                     s->func(s->context,b,2);
++                     break; }
++         case '4': { stbiw_uint32 x = va_arg(v,int);
++                     unsigned char b[4];
++                     b[0]=STBIW_UCHAR(x);
++                     b[1]=STBIW_UCHAR(x>>8);
++                     b[2]=STBIW_UCHAR(x>>16);
++                     b[3]=STBIW_UCHAR(x>>24);
++                     s->func(s->context,b,4);
++                     break; }
++         default:
++            STBIW_ASSERT(0);
++            return;
++      }
++   }
++}
++
++static void stbiw__writef(stbi__write_context *s, const char *fmt, ...)
++{
++   va_list v;
++   va_start(v, fmt);
++   stbiw__writefv(s, fmt, v);
++   va_end(v);
++}
++
++static void stbiw__putc(stbi__write_context *s, unsigned char c)
++{
++   s->func(s->context, &c, 1);
++}
++
++static void stbiw__write3(stbi__write_context *s, unsigned char a, unsigned char b, unsigned char c)
++{
++   unsigned char arr[3];
++   arr[0] = a, arr[1] = b, arr[2] = c;
++   s->func(s->context, arr, 3);
++}
++
++static void stbiw__write_pixel(stbi__write_context *s, int rgb_dir, int comp, int write_alpha, int expand_mono, unsigned char *d)
++{
++   unsigned char bg[3] = { 255, 0, 255}, px[3];
++   int k;
++
++   if (write_alpha < 0)
++      s->func(s->context, &d[comp - 1], 1);
++
++   switch (comp) {
++      case 2: // 2 pixels = mono + alpha, alpha is written separately, so same as 1-channel case
++      case 1:
++         if (expand_mono)
++            stbiw__write3(s, d[0], d[0], d[0]); // monochrome bmp
++         else
++            s->func(s->context, d, 1);  // monochrome TGA
++         break;
++      case 4:
++         if (!write_alpha) {
++            // composite against pink background
++            for (k = 0; k < 3; ++k)
++               px[k] = bg[k] + ((d[k] - bg[k]) * d[3]) / 255;
++            stbiw__write3(s, px[1 - rgb_dir], px[1], px[1 + rgb_dir]);
++            break;
++         }
++         /* FALLTHROUGH */
++      case 3:
++         stbiw__write3(s, d[1 - rgb_dir], d[1], d[1 + rgb_dir]);
++         break;
++   }
++   if (write_alpha > 0)
++      s->func(s->context, &d[comp - 1], 1);
++}
++
++static void stbiw__write_pixels(stbi__write_context *s, int rgb_dir, int vdir, int x, int y, int comp, void *data, int write_alpha, int scanline_pad, int expand_mono)
++{
++   stbiw_uint32 zero = 0;
++   int i,j, j_end;
++
++   if (y <= 0)
++      return;
++
++   if (stbi__flip_vertically_on_write)
++      vdir *= -1;
++
++   if (vdir < 0)
++      j_end = -1, j = y-1;
++   else
++      j_end =  y, j = 0;
++
++   for (; j != j_end; j += vdir) {
++      for (i=0; i < x; ++i) {
++         unsigned char *d = (unsigned char *) data + (j*x+i)*comp;
++         stbiw__write_pixel(s, rgb_dir, comp, write_alpha, expand_mono, d);
++      }
++      s->func(s->context, &zero, scanline_pad);
++   }
++}
++
++static int stbiw__outfile(stbi__write_context *s, int rgb_dir, int vdir, int x, int y, int comp, int expand_mono, void *data, int alpha, int pad, const char *fmt, ...)
++{
++   if (y < 0 || x < 0) {
++      return 0;
++   } else {
++      va_list v;
++      va_start(v, fmt);
++      stbiw__writefv(s, fmt, v);
++      va_end(v);
++      stbiw__write_pixels(s,rgb_dir,vdir,x,y,comp,data,alpha,pad, expand_mono);
++      return 1;
++   }
++}
++
++static int stbi_write_bmp_core(stbi__write_context *s, int x, int y, int comp, const void *data)
++{
++   int pad = (-x*3) & 3;
++   return stbiw__outfile(s,-1,-1,x,y,comp,1,(void *) data,0,pad,
++           "11 4 22 4" "4 44 22 444444",
++           'B', 'M', 14+40+(x*3+pad)*y, 0,0, 14+40,  // file header
++            40, x,y, 1,24, 0,0,0,0,0,0);             // bitmap header
++}
++
++STBIWDEF int stbi_write_bmp_to_func(stbi_write_func *func, void *context, int x, int y, int comp, const void *data)
++{
++   stbi__write_context s;
++   stbi__start_write_callbacks(&s, func, context);
++   return stbi_write_bmp_core(&s, x, y, comp, data);
++}
++
++#ifndef STBI_WRITE_NO_STDIO
++STBIWDEF int stbi_write_bmp(char const *filename, int x, int y, int comp, const void *data)
++{
++   stbi__write_context s;
++   if (stbi__start_write_file(&s,filename)) {
++      int r = stbi_write_bmp_core(&s, x, y, comp, data);
++      stbi__end_write_file(&s);
++      return r;
++   } else
++      return 0;
++}
++#endif //!STBI_WRITE_NO_STDIO
++
++static int stbi_write_tga_core(stbi__write_context *s, int x, int y, int comp, void *data)
++{
++   int has_alpha = (comp == 2 || comp == 4);
++   int colorbytes = has_alpha ? comp-1 : comp;
++   int format = colorbytes < 2 ? 3 : 2; // 3 color channels (RGB/RGBA) = 2, 1 color channel (Y/YA) = 3
++
++   if (y < 0 || x < 0)
++      return 0;
++
++   if (!stbi_write_tga_with_rle) {
++      return stbiw__outfile(s, -1, -1, x, y, comp, 0, (void *) data, has_alpha, 0,
++         "111 221 2222 11", 0, 0, format, 0, 0, 0, 0, 0, x, y, (colorbytes + has_alpha) * 8, has_alpha * 8);
++   } else {
++      int i,j,k;
++      int jend, jdir;
++
++      stbiw__writef(s, "111 221 2222 11", 0,0,format+8, 0,0,0, 0,0,x,y, (colorbytes + has_alpha) * 8, has_alpha * 8);
++
++      if (stbi__flip_vertically_on_write) {
++         j = 0;
++         jend = y;
++         jdir = 1;
++      } else {
++         j = y-1;
++         jend = -1;
++         jdir = -1;
++      }
++      for (; j != jend; j += jdir) {
++         unsigned char *row = (unsigned char *) data + j * x * comp;
++         int len;
++
++         for (i = 0; i < x; i += len) {
++            unsigned char *begin = row + i * comp;
++            int diff = 1;
++            len = 1;
++
++            if (i < x - 1) {
++               ++len;
++               diff = memcmp(begin, row + (i + 1) * comp, comp);
++               if (diff) {
++                  const unsigned char *prev = begin;
++                  for (k = i + 2; k < x && len < 128; ++k) {
++                     if (memcmp(prev, row + k * comp, comp)) {
++                        prev += comp;
++                        ++len;
++                     } else {
++                        --len;
++                        break;
++                     }
++                  }
++               } else {
++                  for (k = i + 2; k < x && len < 128; ++k) {
++                     if (!memcmp(begin, row + k * comp, comp)) {
++                        ++len;
++                     } else {
++                        break;
++                     }
++                  }
++               }
++            }
++
++            if (diff) {
++               unsigned char header = STBIW_UCHAR(len - 1);
++               s->func(s->context, &header, 1);
++               for (k = 0; k < len; ++k) {
++                  stbiw__write_pixel(s, -1, comp, has_alpha, 0, begin + k * comp);
++               }
++            } else {
++               unsigned char header = STBIW_UCHAR(len - 129);
++               s->func(s->context, &header, 1);
++               stbiw__write_pixel(s, -1, comp, has_alpha, 0, begin);
++            }
++         }
++      }
++   }
++   return 1;
++}
++
++STBIWDEF int stbi_write_tga_to_func(stbi_write_func *func, void *context, int x, int y, int comp, const void *data)
++{
++   stbi__write_context s;
++   stbi__start_write_callbacks(&s, func, context);
++   return stbi_write_tga_core(&s, x, y, comp, (void *) data);
++}
++
++#ifndef STBI_WRITE_NO_STDIO
++STBIWDEF int stbi_write_tga(char const *filename, int x, int y, int comp, const void *data)
++{
++   stbi__write_context s;
++   if (stbi__start_write_file(&s,filename)) {
++      int r = stbi_write_tga_core(&s, x, y, comp, (void *) data);
++      stbi__end_write_file(&s);
++      return r;
++   } else
++      return 0;
++}
++#endif
++
++// *************************************************************************************************
++// Radiance RGBE HDR writer
++// by Baldur Karlsson
++
++#define stbiw__max(a, b)  ((a) > (b) ? (a) : (b))
++
++static void stbiw__linear_to_rgbe(unsigned char *rgbe, float *linear)
++{
++   int exponent;
++   float maxcomp = stbiw__max(linear[0], stbiw__max(linear[1], linear[2]));
++
++   if (maxcomp < 1e-32f) {
++      rgbe[0] = rgbe[1] = rgbe[2] = rgbe[3] = 0;
++   } else {
++      float normalize = (float) frexp(maxcomp, &exponent) * 256.0f/maxcomp;
++
++      rgbe[0] = (unsigned char)(linear[0] * normalize);
++      rgbe[1] = (unsigned char)(linear[1] * normalize);
++      rgbe[2] = (unsigned char)(linear[2] * normalize);
++      rgbe[3] = (unsigned char)(exponent + 128);
++   }
++}
++
++static void stbiw__write_run_data(stbi__write_context *s, int length, unsigned char databyte)
++{
++   unsigned char lengthbyte = STBIW_UCHAR(length+128);
++   STBIW_ASSERT(length+128 <= 255);
++   s->func(s->context, &lengthbyte, 1);
++   s->func(s->context, &databyte, 1);
++}
++
++static void stbiw__write_dump_data(stbi__write_context *s, int length, unsigned char *data)
++{
++   unsigned char lengthbyte = STBIW_UCHAR(length);
++   STBIW_ASSERT(length <= 128); // inconsistent with spec but consistent with official code
++   s->func(s->context, &lengthbyte, 1);
++   s->func(s->context, data, length);
++}
++
++static void stbiw__write_hdr_scanline(stbi__write_context *s, int width, int ncomp, unsigned char *scratch, float *scanline)
++{
++   unsigned char scanlineheader[4] = { 2, 2, 0, 0 };
++   unsigned char rgbe[4];
++   float linear[3];
++   int x;
++
++   scanlineheader[2] = (width&0xff00)>>8;
++   scanlineheader[3] = (width&0x00ff);
++
++   /* skip RLE for images too small or large */
++   if (width < 8 || width >= 32768) {
++      for (x=0; x < width; x++) {
++         switch (ncomp) {
++            case 4: /* fallthrough */
++            case 3: linear[2] = scanline[x*ncomp + 2];
++                    linear[1] = scanline[x*ncomp + 1];
++                    linear[0] = scanline[x*ncomp + 0];
++                    break;
++            default:
++                    linear[0] = linear[1] = linear[2] = scanline[x*ncomp + 0];
++                    break;
++         }
++         stbiw__linear_to_rgbe(rgbe, linear);
++         s->func(s->context, rgbe, 4);
++      }
++   } else {
++      int c,r;
++      /* encode into scratch buffer */
++      for (x=0; x < width; x++) {
++         switch(ncomp) {
++            case 4: /* fallthrough */
++            case 3: linear[2] = scanline[x*ncomp + 2];
++                    linear[1] = scanline[x*ncomp + 1];
++                    linear[0] = scanline[x*ncomp + 0];
++                    break;
++            default:
++                    linear[0] = linear[1] = linear[2] = scanline[x*ncomp + 0];
++                    break;
++         }
++         stbiw__linear_to_rgbe(rgbe, linear);
++         scratch[x + width*0] = rgbe[0];
++         scratch[x + width*1] = rgbe[1];
++         scratch[x + width*2] = rgbe[2];
++         scratch[x + width*3] = rgbe[3];
++      }
++
++      s->func(s->context, scanlineheader, 4);
++
++      /* RLE each component separately */
++      for (c=0; c < 4; c++) {
++         unsigned char *comp = &scratch[width*c];
++
++         x = 0;
++         while (x < width) {
++            // find first run
++            r = x;
++            while (r+2 < width) {
++               if (comp[r] == comp[r+1] && comp[r] == comp[r+2])
++                  break;
++               ++r;
++            }
++            if (r+2 >= width)
++               r = width;
++            // dump up to first run
++            while (x < r) {
++               int len = r-x;
++               if (len > 128) len = 128;
++               stbiw__write_dump_data(s, len, &comp[x]);
++               x += len;
++            }
++            // if there's a run, output it
++            if (r+2 < width) { // same test as what we break out of in search loop, so only true if we break'd
++               // find next byte after run
++               while (r < width && comp[r] == comp[x])
++                  ++r;
++               // output run up to r
++               while (x < r) {
++                  int len = r-x;
++                  if (len > 127) len = 127;
++                  stbiw__write_run_data(s, len, comp[x]);
++                  x += len;
++               }
++            }
++         }
++      }
++   }
++}
++
++static int stbi_write_hdr_core(stbi__write_context *s, int x, int y, int comp, float *data)
++{
++   if (y <= 0 || x <= 0 || data == NULL)
++      return 0;
++   else {
++      // Each component is stored separately. Allocate scratch space for full output scanline.
++      unsigned char *scratch = (unsigned char *) STBIW_MALLOC(x*4);
++      int i, len;
++      char buffer[128];
++      char header[] = "#?RADIANCE\n# Written by stb_image_write.h\nFORMAT=32-bit_rle_rgbe\n";
++      s->func(s->context, header, sizeof(header)-1);
++
++#ifdef STBI_MSC_SECURE_CRT
++      len = sprintf_s(buffer, "EXPOSURE=          1.0000000000000\n\n-Y %d +X %d\n", y, x);
++#else
++      len = sprintf(buffer, "EXPOSURE=          1.0000000000000\n\n-Y %d +X %d\n", y, x);
++#endif
++      s->func(s->context, buffer, len);
++
++      for(i=0; i < y; i++)
++         stbiw__write_hdr_scanline(s, x, comp, scratch, data + comp*x*(stbi__flip_vertically_on_write ? y-1-i : i)*x);
++      STBIW_FREE(scratch);
++      return 1;
++   }
++}
++
++STBIWDEF int stbi_write_hdr_to_func(stbi_write_func *func, void *context, int x, int y, int comp, const float *data)
++{
++   stbi__write_context s;
++   stbi__start_write_callbacks(&s, func, context);
++   return stbi_write_hdr_core(&s, x, y, comp, (float *) data);
++}
++
++#ifndef STBI_WRITE_NO_STDIO
++STBIWDEF int stbi_write_hdr(char const *filename, int x, int y, int comp, const float *data)
++{
++   stbi__write_context s;
++   if (stbi__start_write_file(&s,filename)) {
++      int r = stbi_write_hdr_core(&s, x, y, comp, (float *) data);
++      stbi__end_write_file(&s);
++      return r;
++   } else
++      return 0;
++}
++#endif // STBI_WRITE_NO_STDIO
++
++
++//////////////////////////////////////////////////////////////////////////////
++//
++// PNG writer
++//
++
++#ifndef STBIW_ZLIB_COMPRESS
++// stretchy buffer; stbiw__sbpush() == vector<>::push_back() -- stbiw__sbcount() == vector<>::size()
++#define stbiw__sbraw(a) ((int *) (a) - 2)
++#define stbiw__sbm(a)   stbiw__sbraw(a)[0]
++#define stbiw__sbn(a)   stbiw__sbraw(a)[1]
++
++#define stbiw__sbneedgrow(a,n)  ((a)==0 || stbiw__sbn(a)+n >= stbiw__sbm(a))
++#define stbiw__sbmaybegrow(a,n) (stbiw__sbneedgrow(a,(n)) ? stbiw__sbgrow(a,n) : 0)
++#define stbiw__sbgrow(a,n)  stbiw__sbgrowf((void **) &(a), (n), sizeof(*(a)))
++
++#define stbiw__sbpush(a, v)      (stbiw__sbmaybegrow(a,1), (a)[stbiw__sbn(a)++] = (v))
++#define stbiw__sbcount(a)        ((a) ? stbiw__sbn(a) : 0)
++#define stbiw__sbfree(a)         ((a) ? STBIW_FREE(stbiw__sbraw(a)),0 : 0)
++
++static void *stbiw__sbgrowf(void **arr, int increment, int itemsize)
++{
++   int m = *arr ? 2*stbiw__sbm(*arr)+increment : increment+1;
++   void *p = STBIW_REALLOC_SIZED(*arr ? stbiw__sbraw(*arr) : 0, *arr ? (stbiw__sbm(*arr)*itemsize + sizeof(int)*2) : 0, itemsize * m + sizeof(int)*2);
++   STBIW_ASSERT(p);
++   if (p) {
++      if (!*arr) ((int *) p)[1] = 0;
++      *arr = (void *) ((int *) p + 2);
++      stbiw__sbm(*arr) = m;
++   }
++   return *arr;
++}
++
++static unsigned char *stbiw__zlib_flushf(unsigned char *data, unsigned int *bitbuffer, int *bitcount)
++{
++   while (*bitcount >= 8) {
++      stbiw__sbpush(data, STBIW_UCHAR(*bitbuffer));
++      *bitbuffer >>= 8;
++      *bitcount -= 8;
++   }
++   return data;
++}
++
++static int stbiw__zlib_bitrev(int code, int codebits)
++{
++   int res=0;
++   while (codebits--) {
++      res = (res << 1) | (code & 1);
++      code >>= 1;
++   }
++   return res;
++}
++
++static unsigned int stbiw__zlib_countm(unsigned char *a, unsigned char *b, int limit)
++{
++   int i;
++   for (i=0; i < limit && i < 258; ++i)
++      if (a[i] != b[i]) break;
++   return i;
++}
++
++static unsigned int stbiw__zhash(unsigned char *data)
++{
++   stbiw_uint32 hash = data[0] + (data[1] << 8) + (data[2] << 16);
++   hash ^= hash << 3;
++   hash += hash >> 5;
++   hash ^= hash << 4;
++   hash += hash >> 17;
++   hash ^= hash << 25;
++   hash += hash >> 6;
++   return hash;
++}
++
++#define stbiw__zlib_flush() (out = stbiw__zlib_flushf(out, &bitbuf, &bitcount))
++#define stbiw__zlib_add(code,codebits) \
++      (bitbuf |= (code) << bitcount, bitcount += (codebits), stbiw__zlib_flush())
++#define stbiw__zlib_huffa(b,c)  stbiw__zlib_add(stbiw__zlib_bitrev(b,c),c)
++// default huffman tables
++#define stbiw__zlib_huff1(n)  stbiw__zlib_huffa(0x30 + (n), 8)
++#define stbiw__zlib_huff2(n)  stbiw__zlib_huffa(0x190 + (n)-144, 9)
++#define stbiw__zlib_huff3(n)  stbiw__zlib_huffa(0 + (n)-256,7)
++#define stbiw__zlib_huff4(n)  stbiw__zlib_huffa(0xc0 + (n)-280,8)
++#define stbiw__zlib_huff(n)  ((n) <= 143 ? stbiw__zlib_huff1(n) : (n) <= 255 ? stbiw__zlib_huff2(n) : (n) <= 279 ? stbiw__zlib_huff3(n) : stbiw__zlib_huff4(n))
++#define stbiw__zlib_huffb(n) ((n) <= 143 ? stbiw__zlib_huff1(n) : stbiw__zlib_huff2(n))
++
++#define stbiw__ZHASH   16384
++
++#endif // STBIW_ZLIB_COMPRESS
++
++static unsigned char * stbi_zlib_compress(unsigned char *data, int data_len, int *out_len, int quality)
++{
++#ifdef STBIW_ZLIB_COMPRESS
++   // user provided a zlib compress implementation, use that
++   return STBIW_ZLIB_COMPRESS(data, data_len, out_len, quality);
++#else // use builtin
++   static unsigned short lengthc[] = { 3,4,5,6,7,8,9,10,11,13,15,17,19,23,27,31,35,43,51,59,67,83,99,115,131,163,195,227,258, 259 };
++   static unsigned char  lengtheb[]= { 0,0,0,0,0,0,0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4,  4,  5,  5,  5,  5,  0 };
++   static unsigned short distc[]   = { 1,2,3,4,5,7,9,13,17,25,33,49,65,97,129,193,257,385,513,769,1025,1537,2049,3073,4097,6145,8193,12289,16385,24577, 32768 };
++   static unsigned char  disteb[]  = { 0,0,0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13 };
++   unsigned int bitbuf=0;
++   int i,j, bitcount=0;
++   unsigned char *out = NULL;
++   unsigned char ***hash_table = (unsigned char***) STBIW_MALLOC(stbiw__ZHASH * sizeof(char**));
++   if (hash_table == NULL)
++      return NULL;
++   if (quality < 5) quality = 5;
++
++   stbiw__sbpush(out, 0x78);   // DEFLATE 32K window
++   stbiw__sbpush(out, 0x5e);   // FLEVEL = 1
++   stbiw__zlib_add(1,1);  // BFINAL = 1
++   stbiw__zlib_add(1,2);  // BTYPE = 1 -- fixed huffman
++
++   for (i=0; i < stbiw__ZHASH; ++i)
++      hash_table[i] = NULL;
++
++   i=0;
++   while (i < data_len-3) {
++      // hash next 3 bytes of data to be compressed
++      int h = stbiw__zhash(data+i)&(stbiw__ZHASH-1), best=3;
++      unsigned char *bestloc = 0;
++      unsigned char **hlist = hash_table[h];
++      int n = stbiw__sbcount(hlist);
++      for (j=0; j < n; ++j) {
++         if (hlist[j]-data > i-32768) { // if entry lies within window
++            int d = stbiw__zlib_countm(hlist[j], data+i, data_len-i);
++            if (d >= best) best=d,bestloc=hlist[j];
++         }
++      }
++      // when hash table entry is too long, delete half the entries
++      if (hash_table[h] && stbiw__sbn(hash_table[h]) == 2*quality) {
++         STBIW_MEMMOVE(hash_table[h], hash_table[h]+quality, sizeof(hash_table[h][0])*quality);
++         stbiw__sbn(hash_table[h]) = quality;
++      }
++      stbiw__sbpush(hash_table[h],data+i);
++
++      if (bestloc) {
++         // "lazy matching" - check match at *next* byte, and if it's better, do cur byte as literal
++         h = stbiw__zhash(data+i+1)&(stbiw__ZHASH-1);
++         hlist = hash_table[h];
++         n = stbiw__sbcount(hlist);
++         for (j=0; j < n; ++j) {
++            if (hlist[j]-data > i-32767) {
++               int e = stbiw__zlib_countm(hlist[j], data+i+1, data_len-i-1);
++               if (e > best) { // if next match is better, bail on current match
++                  bestloc = NULL;
++                  break;
++               }
++            }
++         }
++      }
++
++      if (bestloc) {
++         int d = (int) (data+i - bestloc); // distance back
++         STBIW_ASSERT(d <= 32767 && best <= 258);
++         for (j=0; best > lengthc[j+1]-1; ++j);
++         stbiw__zlib_huff(j+257);
++         if (lengtheb[j]) stbiw__zlib_add(best - lengthc[j], lengtheb[j]);
++         for (j=0; d > distc[j+1]-1; ++j);
++         stbiw__zlib_add(stbiw__zlib_bitrev(j,5),5);
++         if (disteb[j]) stbiw__zlib_add(d - distc[j], disteb[j]);
++         i += best;
++      } else {
++         stbiw__zlib_huffb(data[i]);
++         ++i;
++      }
++   }
++   // write out final bytes
++   for (;i < data_len; ++i)
++      stbiw__zlib_huffb(data[i]);
++   stbiw__zlib_huff(256); // end of block
++   // pad with 0 bits to byte boundary
++   while (bitcount)
++      stbiw__zlib_add(0,1);
++
++   for (i=0; i < stbiw__ZHASH; ++i)
++      (void) stbiw__sbfree(hash_table[i]);
++   STBIW_FREE(hash_table);
++
++   {
++      // compute adler32 on input
++      unsigned int s1=1, s2=0;
++      int blocklen = (int) (data_len % 5552);
++      j=0;
++      while (j < data_len) {
++         for (i=0; i < blocklen; ++i) s1 += data[j+i], s2 += s1;
++         s1 %= 65521, s2 %= 65521;
++         j += blocklen;
++         blocklen = 5552;
++      }
++      stbiw__sbpush(out, STBIW_UCHAR(s2 >> 8));
++      stbiw__sbpush(out, STBIW_UCHAR(s2));
++      stbiw__sbpush(out, STBIW_UCHAR(s1 >> 8));
++      stbiw__sbpush(out, STBIW_UCHAR(s1));
++   }
++   *out_len = stbiw__sbn(out);
++   // make returned pointer freeable
++   STBIW_MEMMOVE(stbiw__sbraw(out), out, *out_len);
++   return (unsigned char *) stbiw__sbraw(out);
++#endif // STBIW_ZLIB_COMPRESS
++}
++
++static unsigned int stbiw__crc32(unsigned char *buffer, int len)
++{
++   static unsigned int crc_table[256] =
++   {
++      0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
++      0x0eDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
++      0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
++      0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
++      0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
++      0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
++      0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
++      0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
++      0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
++      0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
++      0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
++      0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
++      0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
++      0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
++      0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086, 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
++      0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
++      0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
++      0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
++      0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
++      0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
++      0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
++      0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
++      0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
++      0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04, 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
++      0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
++      0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
++      0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
++      0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
++      0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
++      0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0, 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
++      0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
++      0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
++   };
++
++   unsigned int crc = ~0u;
++   int i;
++   for (i=0; i < len; ++i)
++      crc = (crc >> 8) ^ crc_table[buffer[i] ^ (crc & 0xff)];
++   return ~crc;
++}
++
++#define stbiw__wpng4(o,a,b,c,d) ((o)[0]=STBIW_UCHAR(a),(o)[1]=STBIW_UCHAR(b),(o)[2]=STBIW_UCHAR(c),(o)[3]=STBIW_UCHAR(d),(o)+=4)
++#define stbiw__wp32(data,v) stbiw__wpng4(data, (v)>>24,(v)>>16,(v)>>8,(v));
++#define stbiw__wptag(data,s) stbiw__wpng4(data, s[0],s[1],s[2],s[3])
++
++static void stbiw__wpcrc(unsigned char **data, int len)
++{
++   unsigned int crc = stbiw__crc32(*data - len - 4, len+4);
++   stbiw__wp32(*data, crc);
++}
++
++static unsigned char stbiw__paeth(int a, int b, int c)
++{
++   int p = a + b - c, pa = abs(p-a), pb = abs(p-b), pc = abs(p-c);
++   if (pa <= pb && pa <= pc) return STBIW_UCHAR(a);
++   if (pb <= pc) return STBIW_UCHAR(b);
++   return STBIW_UCHAR(c);
++}
++
++// @OPTIMIZE: provide an option that always forces left-predict or paeth predict
++static void stbiw__encode_png_line(unsigned char *pixels, int stride_bytes, int width, int height, int y, int n, int filter_type, signed char *line_buffer)
++{
++   static int mapping[] = { 0,1,2,3,4 };
++   static int firstmap[] = { 0,1,0,5,6 };
++   int *mymap = (y != 0) ? mapping : firstmap;
++   int i;
++   int type = mymap[filter_type];
++   unsigned char *z = pixels + stride_bytes * (stbi__flip_vertically_on_write ? height-1-y : y);
++   int signed_stride = stbi__flip_vertically_on_write ? -stride_bytes : stride_bytes;
++   for (i = 0; i < n; ++i) {
++      switch (type) {
++         case 0: line_buffer[i] = z[i]; break;
++         case 1: line_buffer[i] = z[i]; break;
++         case 2: line_buffer[i] = z[i] - z[i-signed_stride]; break;
++         case 3: line_buffer[i] = z[i] - (z[i-signed_stride]>>1); break;
++         case 4: line_buffer[i] = (signed char) (z[i] - stbiw__paeth(0,z[i-signed_stride],0)); break;
++         case 5: line_buffer[i] = z[i]; break;
++         case 6: line_buffer[i] = z[i]; break;
++      }
++   }
++   for (i=n; i < width*n; ++i) {
++      switch (type) {
++         case 0: line_buffer[i] = z[i]; break;
++         case 1: line_buffer[i] = z[i] - z[i-n]; break;
++         case 2: line_buffer[i] = z[i] - z[i-signed_stride]; break;
++         case 3: line_buffer[i] = z[i] - ((z[i-n] + z[i-signed_stride])>>1); break;
++         case 4: line_buffer[i] = z[i] - stbiw__paeth(z[i-n], z[i-signed_stride], z[i-signed_stride-n]); break;
++         case 5: line_buffer[i] = z[i] - (z[i-n]>>1); break;
++         case 6: line_buffer[i] = z[i] - stbiw__paeth(z[i-n], 0,0); break;
++      }
++   }
++}
++
++static unsigned char *stbi_write_png_to_mem(unsigned char *pixels, int stride_bytes, int x, int y, int n, int *out_len)
++{
++   int force_filter = stbi_write_force_png_filter;
++   int ctype[5] = { -1, 0, 4, 2, 6 };
++   unsigned char sig[8] = { 137,80,78,71,13,10,26,10 };
++   unsigned char *out,*o, *filt, *zlib;
++   signed char *line_buffer;
++   int j,zlen;
++
++   if (stride_bytes == 0)
++      stride_bytes = x * n;
++
++   if (force_filter >= 5) {
++      force_filter = -1;
++   }
++
++   filt = (unsigned char *) STBIW_MALLOC((x*n+1) * y); if (!filt) return 0;
++   line_buffer = (signed char *) STBIW_MALLOC(x * n); if (!line_buffer) { STBIW_FREE(filt); return 0; }
++   for (j=0; j < y; ++j) {
++      int filter_type;
++      if (force_filter > -1) {
++         filter_type = force_filter;
++         stbiw__encode_png_line(pixels, stride_bytes, x, y, j, n, force_filter, line_buffer);
++      } else { // Estimate the best filter by running through all of them:
++         int best_filter = 0, best_filter_val = 0x7fffffff, est, i;
++         for (filter_type = 0; filter_type < 5; filter_type++) {
++            stbiw__encode_png_line(pixels, stride_bytes, x, y, j, n, filter_type, line_buffer);
++
++            // Estimate the entropy of the line using this filter; the less, the better.
++            est = 0;
++            for (i = 0; i < x*n; ++i) {
++               est += abs((signed char) line_buffer[i]);
++            }
++            if (est < best_filter_val) {
++               best_filter_val = est;
++               best_filter = filter_type;
++            }
++         }
++         if (filter_type != best_filter) {  // If the last iteration already got us the best filter, don't redo it
++            stbiw__encode_png_line(pixels, stride_bytes, x, y, j, n, best_filter, line_buffer);
++            filter_type = best_filter;
++         }
++      }
++      // when we get here, filter_type contains the filter type, and line_buffer contains the data
++      filt[j*(x*n+1)] = (unsigned char) filter_type;
++      STBIW_MEMMOVE(filt+j*(x*n+1)+1, line_buffer, x*n);
++   }
++   STBIW_FREE(line_buffer);
++   zlib = stbi_zlib_compress(filt, y*( x*n+1), &zlen, stbi_write_png_compression_level);
++   STBIW_FREE(filt);
++   if (!zlib) return 0;
++
++   // each tag requires 12 bytes of overhead
++   out = (unsigned char *) STBIW_MALLOC(8 + 12+13 + 12+zlen + 12);
++   if (!out) return 0;
++   *out_len = 8 + 12+13 + 12+zlen + 12;
++
++   o=out;
++   STBIW_MEMMOVE(o,sig,8); o+= 8;
++   stbiw__wp32(o, 13); // header length
++   stbiw__wptag(o, "IHDR");
++   stbiw__wp32(o, x);
++   stbiw__wp32(o, y);
++   *o++ = 8;
++   *o++ = STBIW_UCHAR(ctype[n]);
++   *o++ = 0;
++   *o++ = 0;
++   *o++ = 0;
++   stbiw__wpcrc(&o,13);
++
++   stbiw__wp32(o, zlen);
++   stbiw__wptag(o, "IDAT");
++   STBIW_MEMMOVE(o, zlib, zlen);
++   o += zlen;
++   STBIW_FREE(zlib);
++   stbiw__wpcrc(&o, zlen);
++
++   stbiw__wp32(o,0);
++   stbiw__wptag(o, "IEND");
++   stbiw__wpcrc(&o,0);
++
++   STBIW_ASSERT(o == out + *out_len);
++
++   return out;
++}
++
++#ifndef STBI_WRITE_NO_STDIO
++STBIWDEF int stbi_write_png(char const *filename, int x, int y, int comp, const void *data, int stride_bytes)
++{
++   FILE *f;
++   int len;
++   unsigned char *png = stbi_write_png_to_mem((unsigned char *) data, stride_bytes, x, y, comp, &len);
++   if (png == NULL) return 0;
++#ifdef STBI_MSC_SECURE_CRT
++   if (fopen_s(&f, filename, "wb"))
++      f = NULL;
++#else
++   f = fopen(filename, "wb");
++#endif
++   if (!f) { STBIW_FREE(png); return 0; }
++   fwrite(png, 1, len, f);
++   fclose(f);
++   STBIW_FREE(png);
++   return 1;
++}
++#endif
++
++STBIWDEF int stbi_write_png_to_func(stbi_write_func *func, void *context, int x, int y, int comp, const void *data, int stride_bytes)
++{
++   int len;
++   unsigned char *png = stbi_write_png_to_mem((unsigned char *) data, stride_bytes, x, y, comp, &len);
++   if (png == NULL) return 0;
++   func(context, png, len);
++   STBIW_FREE(png);
++   return 1;
++}
++
++
++/* ***************************************************************************
++ *
++ * JPEG writer
++ *
++ * This is based on Jon Olick's jo_jpeg.cpp:
++ * public domain Simple, Minimalistic JPEG writer - http://www.jonolick.com/code.html
++ */
++
++static const unsigned char stbiw__jpg_ZigZag[] = { 0,1,5,6,14,15,27,28,2,4,7,13,16,26,29,42,3,8,12,17,25,30,41,43,9,11,18,
++      24,31,40,44,53,10,19,23,32,39,45,52,54,20,22,33,38,46,51,55,60,21,34,37,47,50,56,59,61,35,36,48,49,57,58,62,63 };
++
++static void stbiw__jpg_writeBits(stbi__write_context *s, int *bitBufP, int *bitCntP, const unsigned short *bs) {
++   int bitBuf = *bitBufP, bitCnt = *bitCntP;
++   bitCnt += bs[1];
++   bitBuf |= bs[0] << (24 - bitCnt);
++   while(bitCnt >= 8) {
++      unsigned char c = (bitBuf >> 16) & 255;
++      stbiw__putc(s, c);
++      if(c == 255) {
++         stbiw__putc(s, 0);
++      }
++      bitBuf <<= 8;
++      bitCnt -= 8;
++   }
++   *bitBufP = bitBuf;
++   *bitCntP = bitCnt;
++}
++
++static void stbiw__jpg_DCT(float *d0p, float *d1p, float *d2p, float *d3p, float *d4p, float *d5p, float *d6p, float *d7p) {
++   float d0 = *d0p, d1 = *d1p, d2 = *d2p, d3 = *d3p, d4 = *d4p, d5 = *d5p, d6 = *d6p, d7 = *d7p;
++   float z1, z2, z3, z4, z5, z11, z13;
++
++   float tmp0 = d0 + d7;
++   float tmp7 = d0 - d7;
++   float tmp1 = d1 + d6;
++   float tmp6 = d1 - d6;
++   float tmp2 = d2 + d5;
++   float tmp5 = d2 - d5;
++   float tmp3 = d3 + d4;
++   float tmp4 = d3 - d4;
++
++   // Even part
++   float tmp10 = tmp0 + tmp3;   // phase 2
++   float tmp13 = tmp0 - tmp3;
++   float tmp11 = tmp1 + tmp2;
++   float tmp12 = tmp1 - tmp2;
++
++   d0 = tmp10 + tmp11;       // phase 3
++   d4 = tmp10 - tmp11;
++
++   z1 = (tmp12 + tmp13) * 0.707106781f; // c4
++   d2 = tmp13 + z1;       // phase 5
++   d6 = tmp13 - z1;
++
++   // Odd part
++   tmp10 = tmp4 + tmp5;       // phase 2
++   tmp11 = tmp5 + tmp6;
++   tmp12 = tmp6 + tmp7;
++
++   // The rotator is modified from fig 4-8 to avoid extra negations.
++   z5 = (tmp10 - tmp12) * 0.382683433f; // c6
++   z2 = tmp10 * 0.541196100f + z5; // c2-c6
++   z4 = tmp12 * 1.306562965f + z5; // c2+c6
++   z3 = tmp11 * 0.707106781f; // c4
++
++   z11 = tmp7 + z3;      // phase 5
++   z13 = tmp7 - z3;
++
++   *d5p = z13 + z2;         // phase 6
++   *d3p = z13 - z2;
++   *d1p = z11 + z4;
++   *d7p = z11 - z4;
++
++   *d0p = d0;  *d2p = d2;  *d4p = d4;  *d6p = d6;
++}
++
++static void stbiw__jpg_calcBits(int val, unsigned short bits[2]) {
++   int tmp1 = val < 0 ? -val : val;
++   val = val < 0 ? val-1 : val;
++   bits[1] = 1;
++   while(tmp1 >>= 1) {
++      ++bits[1];
++   }
++   bits[0] = val & ((1<<bits[1])-1);
++}
++
++static int stbiw__jpg_processDU(stbi__write_context *s, int *bitBuf, int *bitCnt, float *CDU, float *fdtbl, int DC, const unsigned short HTDC[256][2], const unsigned short HTAC[256][2]) {
++   const unsigned short EOB[2] = { HTAC[0x00][0], HTAC[0x00][1] };
++   const unsigned short M16zeroes[2] = { HTAC[0xF0][0], HTAC[0xF0][1] };
++   int dataOff, i, diff, end0pos;
++   int DU[64];
++
++   // DCT rows
++   for(dataOff=0; dataOff<64; dataOff+=8) {
++      stbiw__jpg_DCT(&CDU[dataOff], &CDU[dataOff+1], &CDU[dataOff+2], &CDU[dataOff+3], &CDU[dataOff+4], &CDU[dataOff+5], &CDU[dataOff+6], &CDU[dataOff+7]);
++   }
++   // DCT columns
++   for(dataOff=0; dataOff<8; ++dataOff) {
++      stbiw__jpg_DCT(&CDU[dataOff], &CDU[dataOff+8], &CDU[dataOff+16], &CDU[dataOff+24], &CDU[dataOff+32], &CDU[dataOff+40], &CDU[dataOff+48], &CDU[dataOff+56]);
++   }
++   // Quantize/descale/zigzag the coefficients
++   for(i=0; i<64; ++i) {
++      float v = CDU[i]*fdtbl[i];
++      // DU[stbiw__jpg_ZigZag[i]] = (int)(v < 0 ? ceilf(v - 0.5f) : floorf(v + 0.5f));
++      // ceilf() and floorf() are C99, not C89, but I /think/ they're not needed here anyway?
++      DU[stbiw__jpg_ZigZag[i]] = (int)(v < 0 ? v - 0.5f : v + 0.5f);
++   }
++
++   // Encode DC
++   diff = DU[0] - DC;
++   if (diff == 0) {
++      stbiw__jpg_writeBits(s, bitBuf, bitCnt, HTDC[0]);
++   } else {
++      unsigned short bits[2];
++      stbiw__jpg_calcBits(diff, bits);
++      stbiw__jpg_writeBits(s, bitBuf, bitCnt, HTDC[bits[1]]);
++      stbiw__jpg_writeBits(s, bitBuf, bitCnt, bits);
++   }
++   // Encode ACs
++   end0pos = 63;
++   for(; (end0pos>0)&&(DU[end0pos]==0); --end0pos) {
++   }
++   // end0pos = first element in reverse order !=0
++   if(end0pos == 0) {
++      stbiw__jpg_writeBits(s, bitBuf, bitCnt, EOB);
++      return DU[0];
++   }
++   for(i = 1; i <= end0pos; ++i) {
++      int startpos = i;
++      int nrzeroes;
++      unsigned short bits[2];
++      for (; DU[i]==0 && i<=end0pos; ++i) {
++      }
++      nrzeroes = i-startpos;
++      if ( nrzeroes >= 16 ) {
++         int lng = nrzeroes>>4;
++         int nrmarker;
++         for (nrmarker=1; nrmarker <= lng; ++nrmarker)
++            stbiw__jpg_writeBits(s, bitBuf, bitCnt, M16zeroes);
++         nrzeroes &= 15;
++      }
++      stbiw__jpg_calcBits(DU[i], bits);
++      stbiw__jpg_writeBits(s, bitBuf, bitCnt, HTAC[(nrzeroes<<4)+bits[1]]);
++      stbiw__jpg_writeBits(s, bitBuf, bitCnt, bits);
++   }
++   if(end0pos != 63) {
++      stbiw__jpg_writeBits(s, bitBuf, bitCnt, EOB);
++   }
++   return DU[0];
++}
++
++static int stbi_write_jpg_core(stbi__write_context *s, int width, int height, int comp, const void* data, int quality) {
++   // Constants that don't pollute global namespace
++   static const unsigned char std_dc_luminance_nrcodes[] = {0,0,1,5,1,1,1,1,1,1,0,0,0,0,0,0,0};
++   static const unsigned char std_dc_luminance_values[] = {0,1,2,3,4,5,6,7,8,9,10,11};
++   static const unsigned char std_ac_luminance_nrcodes[] = {0,0,2,1,3,3,2,4,3,5,5,4,4,0,0,1,0x7d};
++   static const unsigned char std_ac_luminance_values[] = {
++      0x01,0x02,0x03,0x00,0x04,0x11,0x05,0x12,0x21,0x31,0x41,0x06,0x13,0x51,0x61,0x07,0x22,0x71,0x14,0x32,0x81,0x91,0xa1,0x08,
++      0x23,0x42,0xb1,0xc1,0x15,0x52,0xd1,0xf0,0x24,0x33,0x62,0x72,0x82,0x09,0x0a,0x16,0x17,0x18,0x19,0x1a,0x25,0x26,0x27,0x28,
++      0x29,0x2a,0x34,0x35,0x36,0x37,0x38,0x39,0x3a,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4a,0x53,0x54,0x55,0x56,0x57,0x58,0x59,
++      0x5a,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6a,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7a,0x83,0x84,0x85,0x86,0x87,0x88,0x89,
++      0x8a,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9a,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7,0xa8,0xa9,0xaa,0xb2,0xb3,0xb4,0xb5,0xb6,
++      0xb7,0xb8,0xb9,0xba,0xc2,0xc3,0xc4,0xc5,0xc6,0xc7,0xc8,0xc9,0xca,0xd2,0xd3,0xd4,0xd5,0xd6,0xd7,0xd8,0xd9,0xda,0xe1,0xe2,
++      0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa
++   };
++   static const unsigned char std_dc_chrominance_nrcodes[] = {0,0,3,1,1,1,1,1,1,1,1,1,0,0,0,0,0};
++   static const unsigned char std_dc_chrominance_values[] = {0,1,2,3,4,5,6,7,8,9,10,11};
++   static const unsigned char std_ac_chrominance_nrcodes[] = {0,0,2,1,2,4,4,3,4,7,5,4,4,0,1,2,0x77};
++   static const unsigned char std_ac_chrominance_values[] = {
++      0x00,0x01,0x02,0x03,0x11,0x04,0x05,0x21,0x31,0x06,0x12,0x41,0x51,0x07,0x61,0x71,0x13,0x22,0x32,0x81,0x08,0x14,0x42,0x91,
++      0xa1,0xb1,0xc1,0x09,0x23,0x33,0x52,0xf0,0x15,0x62,0x72,0xd1,0x0a,0x16,0x24,0x34,0xe1,0x25,0xf1,0x17,0x18,0x19,0x1a,0x26,
++      0x27,0x28,0x29,0x2a,0x35,0x36,0x37,0x38,0x39,0x3a,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4a,0x53,0x54,0x55,0x56,0x57,0x58,
++      0x59,0x5a,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6a,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7a,0x82,0x83,0x84,0x85,0x86,0x87,
++      0x88,0x89,0x8a,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9a,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7,0xa8,0xa9,0xaa,0xb2,0xb3,0xb4,
++      0xb5,0xb6,0xb7,0xb8,0xb9,0xba,0xc2,0xc3,0xc4,0xc5,0xc6,0xc7,0xc8,0xc9,0xca,0xd2,0xd3,0xd4,0xd5,0xd6,0xd7,0xd8,0xd9,0xda,
++      0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa
++   };
++   // Huffman tables
++   static const unsigned short YDC_HT[256][2] = { {0,2},{2,3},{3,3},{4,3},{5,3},{6,3},{14,4},{30,5},{62,6},{126,7},{254,8},{510,9}};
++   static const unsigned short UVDC_HT[256][2] = { {0,2},{1,2},{2,2},{6,3},{14,4},{30,5},{62,6},{126,7},{254,8},{510,9},{1022,10},{2046,11}};
++   static const unsigned short YAC_HT[256][2] = {
++      {10,4},{0,2},{1,2},{4,3},{11,4},{26,5},{120,7},{248,8},{1014,10},{65410,16},{65411,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {12,4},{27,5},{121,7},{502,9},{2038,11},{65412,16},{65413,16},{65414,16},{65415,16},{65416,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {28,5},{249,8},{1015,10},{4084,12},{65417,16},{65418,16},{65419,16},{65420,16},{65421,16},{65422,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {58,6},{503,9},{4085,12},{65423,16},{65424,16},{65425,16},{65426,16},{65427,16},{65428,16},{65429,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {59,6},{1016,10},{65430,16},{65431,16},{65432,16},{65433,16},{65434,16},{65435,16},{65436,16},{65437,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {122,7},{2039,11},{65438,16},{65439,16},{65440,16},{65441,16},{65442,16},{65443,16},{65444,16},{65445,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {123,7},{4086,12},{65446,16},{65447,16},{65448,16},{65449,16},{65450,16},{65451,16},{65452,16},{65453,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {250,8},{4087,12},{65454,16},{65455,16},{65456,16},{65457,16},{65458,16},{65459,16},{65460,16},{65461,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {504,9},{32704,15},{65462,16},{65463,16},{65464,16},{65465,16},{65466,16},{65467,16},{65468,16},{65469,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {505,9},{65470,16},{65471,16},{65472,16},{65473,16},{65474,16},{65475,16},{65476,16},{65477,16},{65478,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {506,9},{65479,16},{65480,16},{65481,16},{65482,16},{65483,16},{65484,16},{65485,16},{65486,16},{65487,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {1017,10},{65488,16},{65489,16},{65490,16},{65491,16},{65492,16},{65493,16},{65494,16},{65495,16},{65496,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {1018,10},{65497,16},{65498,16},{65499,16},{65500,16},{65501,16},{65502,16},{65503,16},{65504,16},{65505,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {2040,11},{65506,16},{65507,16},{65508,16},{65509,16},{65510,16},{65511,16},{65512,16},{65513,16},{65514,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {65515,16},{65516,16},{65517,16},{65518,16},{65519,16},{65520,16},{65521,16},{65522,16},{65523,16},{65524,16},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {2041,11},{65525,16},{65526,16},{65527,16},{65528,16},{65529,16},{65530,16},{65531,16},{65532,16},{65533,16},{65534,16},{0,0},{0,0},{0,0},{0,0},{0,0}
++   };
++   static const unsigned short UVAC_HT[256][2] = {
++      {0,2},{1,2},{4,3},{10,4},{24,5},{25,5},{56,6},{120,7},{500,9},{1014,10},{4084,12},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {11,4},{57,6},{246,8},{501,9},{2038,11},{4085,12},{65416,16},{65417,16},{65418,16},{65419,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {26,5},{247,8},{1015,10},{4086,12},{32706,15},{65420,16},{65421,16},{65422,16},{65423,16},{65424,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {27,5},{248,8},{1016,10},{4087,12},{65425,16},{65426,16},{65427,16},{65428,16},{65429,16},{65430,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {58,6},{502,9},{65431,16},{65432,16},{65433,16},{65434,16},{65435,16},{65436,16},{65437,16},{65438,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {59,6},{1017,10},{65439,16},{65440,16},{65441,16},{65442,16},{65443,16},{65444,16},{65445,16},{65446,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {121,7},{2039,11},{65447,16},{65448,16},{65449,16},{65450,16},{65451,16},{65452,16},{65453,16},{65454,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {122,7},{2040,11},{65455,16},{65456,16},{65457,16},{65458,16},{65459,16},{65460,16},{65461,16},{65462,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {249,8},{65463,16},{65464,16},{65465,16},{65466,16},{65467,16},{65468,16},{65469,16},{65470,16},{65471,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {503,9},{65472,16},{65473,16},{65474,16},{65475,16},{65476,16},{65477,16},{65478,16},{65479,16},{65480,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {504,9},{65481,16},{65482,16},{65483,16},{65484,16},{65485,16},{65486,16},{65487,16},{65488,16},{65489,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {505,9},{65490,16},{65491,16},{65492,16},{65493,16},{65494,16},{65495,16},{65496,16},{65497,16},{65498,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {506,9},{65499,16},{65500,16},{65501,16},{65502,16},{65503,16},{65504,16},{65505,16},{65506,16},{65507,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {2041,11},{65508,16},{65509,16},{65510,16},{65511,16},{65512,16},{65513,16},{65514,16},{65515,16},{65516,16},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {16352,14},{65517,16},{65518,16},{65519,16},{65520,16},{65521,16},{65522,16},{65523,16},{65524,16},{65525,16},{0,0},{0,0},{0,0},{0,0},{0,0},
++      {1018,10},{32707,15},{65526,16},{65527,16},{65528,16},{65529,16},{65530,16},{65531,16},{65532,16},{65533,16},{65534,16},{0,0},{0,0},{0,0},{0,0},{0,0}
++   };
++   static const int YQT[] = {16,11,10,16,24,40,51,61,12,12,14,19,26,58,60,55,14,13,16,24,40,57,69,56,14,17,22,29,51,87,80,62,18,22,
++                             37,56,68,109,103,77,24,35,55,64,81,104,113,92,49,64,78,87,103,121,120,101,72,92,95,98,112,100,103,99};
++   static const int UVQT[] = {17,18,24,47,99,99,99,99,18,21,26,66,99,99,99,99,24,26,56,99,99,99,99,99,47,66,99,99,99,99,99,99,
++                              99,99,99,99,99,99,99,99,99,99,99,99,99,99,99,99,99,99,99,99,99,99,99,99,99,99,99,99,99,99,99,99};
++   static const float aasf[] = { 1.0f * 2.828427125f, 1.387039845f * 2.828427125f, 1.306562965f * 2.828427125f, 1.175875602f * 2.828427125f,
++                                 1.0f * 2.828427125f, 0.785694958f * 2.828427125f, 0.541196100f * 2.828427125f, 0.275899379f * 2.828427125f };
++
++   int row, col, i, k;
++   float fdtbl_Y[64], fdtbl_UV[64];
++   unsigned char YTable[64], UVTable[64];
++
++   if(!data || !width || !height || comp > 4 || comp < 1) {
++      return 0;
++   }
++
++   quality = quality ? quality : 90;
++   quality = quality < 1 ? 1 : quality > 100 ? 100 : quality;
++   quality = quality < 50 ? 5000 / quality : 200 - quality * 2;
++
++   for(i = 0; i < 64; ++i) {
++      int uvti, yti = (YQT[i]*quality+50)/100;
++      YTable[stbiw__jpg_ZigZag[i]] = (unsigned char) (yti < 1 ? 1 : yti > 255 ? 255 : yti);
++      uvti = (UVQT[i]*quality+50)/100;
++      UVTable[stbiw__jpg_ZigZag[i]] = (unsigned char) (uvti < 1 ? 1 : uvti > 255 ? 255 : uvti);
++   }
++
++   for(row = 0, k = 0; row < 8; ++row) {
++      for(col = 0; col < 8; ++col, ++k) {
++         fdtbl_Y[k]  = 1 / (YTable [stbiw__jpg_ZigZag[k]] * aasf[row] * aasf[col]);
++         fdtbl_UV[k] = 1 / (UVTable[stbiw__jpg_ZigZag[k]] * aasf[row] * aasf[col]);
++      }
++   }
++
++   // Write Headers
++   {
++      static const unsigned char head0[] = { 0xFF,0xD8,0xFF,0xE0,0,0x10,'J','F','I','F',0,1,1,0,0,1,0,1,0,0,0xFF,0xDB,0,0x84,0 };
++      static const unsigned char head2[] = { 0xFF,0xDA,0,0xC,3,1,0,2,0x11,3,0x11,0,0x3F,0 };
++      const unsigned char head1[] = { 0xFF,0xC0,0,0x11,8,(unsigned char)(height>>8),STBIW_UCHAR(height),(unsigned char)(width>>8),STBIW_UCHAR(width),
++                                      3,1,0x11,0,2,0x11,1,3,0x11,1,0xFF,0xC4,0x01,0xA2,0 };
++      s->func(s->context, (void*)head0, sizeof(head0));
++      s->func(s->context, (void*)YTable, sizeof(YTable));
++      stbiw__putc(s, 1);
++      s->func(s->context, UVTable, sizeof(UVTable));
++      s->func(s->context, (void*)head1, sizeof(head1));
++      s->func(s->context, (void*)(std_dc_luminance_nrcodes+1), sizeof(std_dc_luminance_nrcodes)-1);
++      s->func(s->context, (void*)std_dc_luminance_values, sizeof(std_dc_luminance_values));
++      stbiw__putc(s, 0x10); // HTYACinfo
++      s->func(s->context, (void*)(std_ac_luminance_nrcodes+1), sizeof(std_ac_luminance_nrcodes)-1);
++      s->func(s->context, (void*)std_ac_luminance_values, sizeof(std_ac_luminance_values));
++      stbiw__putc(s, 1); // HTUDCinfo
++      s->func(s->context, (void*)(std_dc_chrominance_nrcodes+1), sizeof(std_dc_chrominance_nrcodes)-1);
++      s->func(s->context, (void*)std_dc_chrominance_values, sizeof(std_dc_chrominance_values));
++      stbiw__putc(s, 0x11); // HTUACinfo
++      s->func(s->context, (void*)(std_ac_chrominance_nrcodes+1), sizeof(std_ac_chrominance_nrcodes)-1);
++      s->func(s->context, (void*)std_ac_chrominance_values, sizeof(std_ac_chrominance_values));
++      s->func(s->context, (void*)head2, sizeof(head2));
++   }
++
++   // Encode 8x8 macroblocks
++   {
++      static const unsigned short fillBits[] = {0x7F, 7};
++      const unsigned char *imageData = (const unsigned char *)data;
++      int DCY=0, DCU=0, DCV=0;
++      int bitBuf=0, bitCnt=0;
++      // comp == 2 is grey+alpha (alpha is ignored)
++      int ofsG = comp > 2 ? 1 : 0, ofsB = comp > 2 ? 2 : 0;
++      int x, y, pos;
++      for(y = 0; y < height; y += 8) {
++         for(x = 0; x < width; x += 8) {
++            float YDU[64], UDU[64], VDU[64];
++            for(row = y, pos = 0; row < y+8; ++row) {
++               for(col = x; col < x+8; ++col, ++pos) {
++                  int p = (stbi__flip_vertically_on_write ? height-1-row : row)*width*comp + col*comp;
++                  float r, g, b;
++                  if(row >= height) {
++                     p -= width*comp*(row+1 - height);
++                  }
++                  if(col >= width) {
++                     p -= comp*(col+1 - width);
++                  }
++
++                  r = imageData[p+0];
++                  g = imageData[p+ofsG];
++                  b = imageData[p+ofsB];
++                  YDU[pos]=+0.29900f*r+0.58700f*g+0.11400f*b-128;
++                  UDU[pos]=-0.16874f*r-0.33126f*g+0.50000f*b;
++                  VDU[pos]=+0.50000f*r-0.41869f*g-0.08131f*b;
++               }
++            }
++
++            DCY = stbiw__jpg_processDU(s, &bitBuf, &bitCnt, YDU, fdtbl_Y, DCY, YDC_HT, YAC_HT);
++            DCU = stbiw__jpg_processDU(s, &bitBuf, &bitCnt, UDU, fdtbl_UV, DCU, UVDC_HT, UVAC_HT);
++            DCV = stbiw__jpg_processDU(s, &bitBuf, &bitCnt, VDU, fdtbl_UV, DCV, UVDC_HT, UVAC_HT);
++         }
++      }
++
++      // Do the bit alignment of the EOI marker
++      stbiw__jpg_writeBits(s, &bitBuf, &bitCnt, fillBits);
++   }
++
++   // EOI
++   stbiw__putc(s, 0xFF);
++   stbiw__putc(s, 0xD9);
++
++   return 1;
++}
++
++STBIWDEF int stbi_write_jpg_to_func(stbi_write_func *func, void *context, int x, int y, int comp, const void *data, int quality)
++{
++   stbi__write_context s;
++   stbi__start_write_callbacks(&s, func, context);
++   return stbi_write_jpg_core(&s, x, y, comp, (void *) data, quality);
++}
++
++
++#ifndef STBI_WRITE_NO_STDIO
++STBIWDEF int stbi_write_jpg(char const *filename, int x, int y, int comp, const void *data, int quality)
++{
++   stbi__write_context s;
++   if (stbi__start_write_file(&s,filename)) {
++      int r = stbi_write_jpg_core(&s, x, y, comp, data, quality);
++      stbi__end_write_file(&s);
++      return r;
++   } else
++      return 0;
++}
++#endif
++
++#endif // STB_IMAGE_WRITE_IMPLEMENTATION
++
++/* Revision history
++      1.09  (2018-02-11)
++             fix typo in zlib quality API, improve STB_I_W_STATIC in C++
++      1.08  (2018-01-29)
++             add stbi__flip_vertically_on_write, external zlib, zlib quality, choose PNG filter
++      1.07  (2017-07-24)
++             doc fix
++      1.06 (2017-07-23)
++             writing JPEG (using Jon Olick's code)
++      1.05   ???
++      1.04 (2017-03-03)
++             monochrome BMP expansion
++      1.03   ???
++      1.02 (2016-04-02)
++             avoid allocating large structures on the stack
++      1.01 (2016-01-16)
++             STBIW_REALLOC_SIZED: support allocators with no realloc support
++             avoid race-condition in crc initialization
++             minor compile issues
++      1.00 (2015-09-14)
++             installable file IO function
++      0.99 (2015-09-13)
++             warning fixes; TGA rle support
++      0.98 (2015-04-08)
++             added STBIW_MALLOC, STBIW_ASSERT etc
++      0.97 (2015-01-18)
++             fixed HDR asserts, rewrote HDR rle logic
++      0.96 (2015-01-17)
++             add HDR output
++             fix monochrome BMP
++      0.95 (2014-08-17)
++		       add monochrome TGA output
++      0.94 (2014-05-31)
++             rename private functions to avoid conflicts with stb_image.h
++      0.93 (2014-05-27)
++             warning fixes
++      0.92 (2010-08-01)
++             casts to unsigned char to fix warnings
++      0.91 (2010-07-17)
++             first public release
++      0.90   first internal release
++*/
++
++/*
++------------------------------------------------------------------------------
++This software is available under 2 licenses -- choose whichever you prefer.
++------------------------------------------------------------------------------
++ALTERNATIVE A - MIT License
++Copyright (c) 2017 Sean Barrett
++Permission is hereby granted, free of charge, to any person obtaining a copy of
++this software and associated documentation files (the "Software"), to deal in
++the Software without restriction, including without limitation the rights to
++use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++of the Software, and to permit persons to whom the Software is furnished to do
++so, subject to the following conditions:
++The above copyright notice and this permission notice shall be included in all
++copies or substantial portions of the Software.
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
++SOFTWARE.
++------------------------------------------------------------------------------
++ALTERNATIVE B - Public Domain (www.unlicense.org)
++This is free and unencumbered software released into the public domain.
++Anyone is free to copy, modify, publish, use, compile, sell, or distribute this
++software, either in source code form or as a compiled binary, for any purpose,
++commercial or non-commercial, and by any means.
++In jurisdictions that recognize copyright laws, the author or authors of this
++software dedicate any and all copyright interest in the software to the public
++domain. We make this dedication for the benefit of the public at large and to
++the detriment of our heirs and successors. We intend this dedication to be an
++overt act of relinquishment in perpetuity of all present and future rights to
++this software under copyright law.
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
++AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
++ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++------------------------------------------------------------------------------
++*/
+diff --git a/scripts/pic2logo.c b/scripts/pic2logo.c
+new file mode 100644
+index 000000000..f08e74b17
+--- /dev/null
++++ b/scripts/pic2logo.c
+@@ -0,0 +1,147 @@
++#include <stdlib.h>
++#include <stdio.h>
++#include <sys/types.h>
++#include <sys/stat.h>
++#include <fcntl.h>
++#include <unistd.h>
++
++
++#define STB_IMAGE_IMPLEMENTATION
++#define STB_IMAGE_WRITE_IMPLEMENTATION
++#define STBI_ONLY_JPEG
++#define STBI_ONLY_PNG
++#define STBI_ONLY_BMP
++
++#include "pic2logo-include/stb_image/stb_image.h"
++#include "pic2logo-include/stb_image/stb_image_write.h"
++/* #include <stb_image/stb_image_resize.h> */
++
++struct _logo_info {
++	int width;
++	int height;
++	int bpp;
++	unsigned int p8;
++	unsigned int background_color;
++} __attribute__ ((packed));
++
++static void gen_info(int w, int h, int bpp, int backcolor)
++{
++	printf("/*\n"
++			" * Automatically generated by \"mklogo\"\n"
++			" *\n"
++			" * DO NOT EDIT\n"
++			" *\n"
++			" */\n\n"
++			"#include <linux/init.h>\n"
++			"#include <video/ingenic_logo.h>\n\n"
++			"extern unsigned char logo_buf_initdata[];\n\n"
++			"struct _logo_info logo_info = {\n"
++			"\t%d,\n"
++			"\t%d,\n"
++			"\t%d,\n"
++			"\tNULL,\n"
++			"\t0x%08x,\n"
++			"};\n\n"
++			"unsigned char logo_buf_initdata[] __initdata = {\n",
++			w, h, bpp, backcolor);
++}
++
++static int ReadPic(const char *pic_file, int real_bit_dep ,int backcolor, const char *output)
++{
++	int ret;
++	int i, j, k = 0;
++	int width, height, channels;
++	unsigned char *data, *p;
++
++	ret = stbi_info(pic_file, &width, &height, &channels);
++	if (ret == 0) {
++		return -1;
++	}
++
++	data = stbi_load(pic_file, &width, &height, &channels, 4);
++
++	if(output) {
++		unsigned int tmp = 0;
++		unsigned int *xdata = data;
++		struct _logo_info info;
++		info.width = width;
++		info.height = height;
++		info.bpp = real_bit_dep;
++		info.background_color = backcolor;
++		info.p8 = 0;
++
++		int fd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0644);
++		write(fd, &info, sizeof(info));
++
++		for(i = 0; i < width * height * real_bit_dep / 32; i++) {
++			tmp = ((xdata[i] & 0x000000ff) << 16) |
++				((xdata[i] & 0x00ff0000) >> 16) |
++				(xdata[i] & 0xff000000)|
++				(xdata[i] & 0x0000ff00);
++			xdata[i] = tmp;
++		}
++
++		write(fd, data, width * height * real_bit_dep / 8);
++		close(fd);
++
++		return 0;
++	}
++
++	// gen head file.
++	gen_info(width, height, real_bit_dep, backcolor);
++
++	if(real_bit_dep == 32) {
++		for(i = 0; i < height; i++) {
++			for(j = 0; j < ( 4 * width); j += 4 ) {
++				p = data + i * (4 * width) + j;
++
++				printf (" 0x%02X, 0x%02X, 0x%02X, 0x%02X,%s",
++						*(p + 2), *(p + 1),
++						*(p + 0), *(p + 3),
++						((k++%8) == 7) ? "\n" : "");
++			}
++		}
++
++	} else if(real_bit_dep == 16) {
++		unsigned short s16;
++		for(i = 0; i < height; i++) {
++			for(j = 0; j < ( 4 * width); j += 4 ) {
++				p = data + i * (4 * width) + j;
++				s16 = ((*(p + 0) & 0xf8) << 8)
++					| ((*(p + 1) & 0xfc) << 3)
++					| ((*(p + 2) & 0xf8) >> 3);
++				unsigned char *p8 = (unsigned char*)&s16;
++				printf (" 0x%02X, 0x%02X,%s", p8[0], p8[1], ((k++%8) == 7) ? "\n" : "");
++			}
++		}
++	}
++
++	printf("};\n");
++
++	return 0;
++}
++
++int main(int argc, char *argv[])
++{
++	int ret = 0;
++	int backcolor = 0x00000000;
++	unsigned char *output = NULL;
++
++	if (argc >= 4)
++		sscanf(argv[3], "%x", &backcolor);
++
++	if (argc >= 5) {
++		output = argv[4];
++	}
++
++	if (argc >= 3) {
++		ret = ReadPic(argv[1], atoi(argv[2]), backcolor, output);
++	} else {
++		printf("usage: pic2logo file bpp<32|16> [backcolor] [output]\n");
++		printf("       e.x.: pic2logo logo.png 32 0x000000ff > logo.c\n");
++		printf("       e.x.: pic2logo logo.png 32 0x000000ff  logo.out\n");
++		ret = -1;
++	}
++
++	return ret;
++}
+-- 
+2.34.1
+
diff --git a/linux-5.10/halley5_patch/hdf.patch b/linux-5.10/halley5_patch/hdf.patch
new file mode 100644
index 0000000..a995b8b
--- /dev/null
+++ b/linux-5.10/halley5_patch/hdf.patch
@@ -0,0 +1,341 @@
+From 2e6751015cdab6a612774f39e7df64153a7944f7 Mon Sep 17 00:00:00 2001
+From: "xiangren.yuan" <xiangren.yuan@ingenic.com>
+Date: Thu, 17 Nov 2022 10:54:06 +0800
+Subject: [PATCH 1/2] mips hdf patch
+
+---
+ arch/mips/kernel/vmlinux.lds.S |  7 +++
+ drivers/Kconfig                |  2 +
+ drivers/Makefile               |  1 +
+ drivers/hdf/Makefile           |  2 +
+ drivers/hid/Makefile           |  9 ++++
+ drivers/hid/hid-core.c         | 95 ++++++++++++++++++++++++++++++++++
+ drivers/hid/hid-input.c        | 50 ++++++++++++++++++
+ drivers/input/mousedev.c       |  2 +-
+ include/linux/hid.h            |  1 +
+ 9 files changed, 168 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/hdf/Makefile
+
+diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
+index 09fa4705c..75633c192 100644
+--- a/arch/mips/kernel/vmlinux.lds.S
++++ b/arch/mips/kernel/vmlinux.lds.S
+@@ -96,6 +96,13 @@ SECTIONS
+ 		DATA_DATA
+ 		CONSTRUCTORS
+ 	}
++#ifdef CONFIG_DRIVERS_HDF
++ .init.hdf_table : {
++	 _hdf_drivers_start = .;
++	 *(.hdf.driver)
++	 _hdf_drivers_end = .;
++ }
++#endif
+ 	BUG_TABLE
+ 	_gp = . + 0x8000;
+ 	.lit8 : {
+diff --git a/drivers/Kconfig b/drivers/Kconfig
+index 3584901f1..12e0cceac 100644
+--- a/drivers/Kconfig
++++ b/drivers/Kconfig
+@@ -236,6 +236,8 @@ source "drivers/interconnect/Kconfig"
+ 
+ source "drivers/counter/Kconfig"
+ 
++source "drivers/hdf/khdf/Kconfig"
++
+ source "drivers/most/Kconfig"
+ 
+ source "drivers/accesstokenid/Kconfig"
+diff --git a/drivers/Makefile b/drivers/Makefile
+index f13d70df6..8ec75883a 100644
+--- a/drivers/Makefile
++++ b/drivers/Makefile
+@@ -191,6 +191,7 @@ obj-$(CONFIG_SIOX)		+= siox/
+ obj-$(CONFIG_GNSS)		+= gnss/
+ obj-$(CONFIG_INTERCONNECT)	+= interconnect/
+ obj-$(CONFIG_COUNTER)		+= counter/
++obj-$(CONFIG_DRIVERS_HDF)	+= hdf/
+ obj-$(CONFIG_MOST)		+= most/
+ obj-$(CONFIG_ACCESS_TOKENID)	+= accesstokenid/
+ obj-$(CONFIG_VENDOR_HOOKS)	+= hooks/
+diff --git a/drivers/hdf/Makefile b/drivers/hdf/Makefile
+new file mode 100644
+index 000000000..5c5e1911c
+--- /dev/null
++++ b/drivers/hdf/Makefile
+@@ -0,0 +1,2 @@
++export PROJECT_ROOT := ../../../../../
++obj-$(CONFIG_DRIVERS_HDF) += khdf/
+diff --git a/drivers/hid/Makefile b/drivers/hid/Makefile
+index 4acb583c9..ddcaf4cdc 100644
+--- a/drivers/hid/Makefile
++++ b/drivers/hid/Makefile
+@@ -2,6 +2,15 @@
+ #
+ # Makefile for the HID driver
+ #
++HDF_ROOT_DIR = -I$(srctree)/drivers/hdf
++ccflags-$(CONFIG_DRIVERS_HDF_INPUT) += $(HDF_ROOT_DIR)/framework/model/input/driver \
++             $(HDF_ROOT_DIR)/framework/include/core \
++             $(HDF_ROOT_DIR)/framework/core/common/include/host \
++             $(HDF_ROOT_DIR)/framework/include/utils \
++             $(HDF_ROOT_DIR)/framework/include/osal \
++             $(HDF_ROOT_DIR)/framework/ability/sbuf/include \
++             $(HDF_ROOT_DIR)/khdf/osal/include \
++             $(HDF_ROOT_DIR)/evdev
+ hid-y			:= hid-core.o hid-input.o hid-quirks.o
+ hid-$(CONFIG_DEBUG_FS)		+= hid-debug.o
+ 
+diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c
+index 5550c943f..79df97fab 100644
+--- a/drivers/hid/hid-core.c
++++ b/drivers/hid/hid-core.c
+@@ -33,6 +33,9 @@
+ #include <linux/hid-debug.h>
+ #include <linux/hidraw.h>
+ 
++#if defined(CONFIG_DRIVERS_HDF_INPUT)
++#include "hdf_hid_adapter.h"
++#endif
+ #include "hid-ids.h"
+ 
+ /*
+@@ -1522,6 +1525,11 @@ static void hid_process_event(struct hid_device *hid, struct hid_field *field,
+ 		hidinput_hid_event(hid, field, usage, value);
+ 	if (hid->claimed & HID_CLAIMED_HIDDEV && interrupt && hid->hiddev_hid_event)
+ 		hid->hiddev_hid_event(hid, field, usage, value);
++#if defined(CONFIG_DRIVERS_HDF_INPUT)
++	if (hid->input_dev) {
++		HidReportEvent(hid->input_dev, usage->type, usage->code, value);
++	}
++#endif
+ }
+ 
+ /*
+@@ -1928,6 +1936,81 @@ static const struct device_attribute dev_attr_country = {
+ 	.show = show_country,
+ };
+ 
++#if defined(CONFIG_DRIVERS_HDF_INPUT)
++static bool check_mouse(char *name)
++{
++	static char *option[]={"Mouse", "mouse", "MOUSE", "Razer"};
++	for (int i = 0; i < 4; i++) {
++		if (strstr(name, option[i]))
++			return true;
++	}
++	return false;
++}
++static bool check_kbd(char *name)
++{
++	static char *option[]={"Keyboard", "keyboard"};
++	for (int i = 0; i < 2; i++) {
++		if (strstr(name, option[i]))
++			return true;
++	}
++	return false;
++}
++static bool check_rocker(char *name)
++{
++	static char *option[]={"Thrustmaster"};
++	for (int i = 0; i < 1; i++) {
++		if (strstr(name, option[i]))
++			return true;
++	}
++	return false;
++}
++static bool check_encoder(char *name)
++{
++	if (strcmp(name, "Wired KeyBoard") == 0) {
++		return true;
++	}
++	return false;
++}
++static bool check_trackball(char *name)
++{
++	static char *option[]={"Trackball"};
++	for (int i = 0; i < 1; i++) {
++		if (strstr(name, option[i]))
++			return true;
++	}
++	return false;
++}
++static void notify_connect_event(struct hid_device *hdev)
++{
++	bool check;
++	int type = -1;
++	HidInfo *dev = (HidInfo *)kmalloc(sizeof(HidInfo), GFP_KERNEL);
++	if (dev == NULL) {
++		printk("%s: malloc failed", __func__);
++		return;
++	}
++	type = check_mouse(hdev->name)?HID_TYPE_MOUSE:type;
++	type = check_kbd(hdev->name)?HID_TYPE_KEYBOARD:type;
++	type = check_rocker(hdev->name)?HID_TYPE_ROCKER:type;
++	type = check_encoder(hdev->name)?HID_TYPE_ENCODER:type;
++	type = check_trackball(hdev->name)?HID_TYPE_TRACKBALL:type;
++	if ( type < 0) {
++		kfree(dev);
++		dev = NULL;
++		return;
++	}
++
++	dev->devType = type;
++	dev->devName = hdev->name;
++	hdev->input_dev = HidRegisterHdfInputDev(dev);
++	if (hdev->input_dev == NULL) {
++		printk("%s: RegisterInputDevice failed\n", __func__);
++	}
++	kfree(dev);
++	dev = NULL;
++}
++#endif
++
+ int hid_connect(struct hid_device *hdev, unsigned int connect_mask)
+ {
+ 	static const char *types[] = { "Device", "Pointer", "Mouse", "Device",
+@@ -2020,6 +2103,9 @@ int hid_connect(struct hid_device *hdev, unsigned int connect_mask)
+ 	hid_info(hdev, "%s: %s HID v%x.%02x %s [%s] on %s\n",
+ 		 buf, bus, hdev->version >> 8, hdev->version & 0xff,
+ 		 type, hdev->name, hdev->phys);
++#if defined(CONFIG_DRIVERS_HDF_INPUT)
++	notify_connect_event(hdev);
++#endif
+ 
+ 	return 0;
+ }
+@@ -2035,6 +2121,10 @@ void hid_disconnect(struct hid_device *hdev)
+ 	if (hdev->claimed & HID_CLAIMED_HIDRAW)
+ 		hidraw_disconnect(hdev);
+ 	hdev->claimed = 0;
++#if defined(CONFIG_DRIVERS_HDF_INPUT)
++	if (hdev->input_dev)
++		HidUnregisterHdfInputDev(hdev->input_dev);
++#endif
+ }
+ EXPORT_SYMBOL_GPL(hid_disconnect);
+ 
+@@ -2119,6 +2209,11 @@ EXPORT_SYMBOL_GPL(hid_hw_open);
+  */
+ void hid_hw_close(struct hid_device *hdev)
+ {
++#if defined(CONFIG_DRIVERS_HDF_INPUT)
++	if (hdev->input_dev) {
++		return;
++	}
++#endif
+ 	mutex_lock(&hdev->ll_open_lock);
+ 	if (!--hdev->ll_open_count)
+ 		hdev->ll_driver->close(hdev);
+diff --git a/drivers/hid/hid-input.c b/drivers/hid/hid-input.c
+index 75a4d8d6b..721265a93 100644
+--- a/drivers/hid/hid-input.c
++++ b/drivers/hid/hid-input.c
+@@ -20,6 +20,10 @@
+ #include <linux/hid.h>
+ #include <linux/hid-debug.h>
+ 
++#if defined(CONFIG_DRIVERS_HDF_INPUT)
++#include "hdf_hid_adapter.h"
++#endif
++
+ #include "hid-ids.h"
+ 
+ #define unk	KEY_UNKNOWN
+@@ -1429,7 +1433,15 @@ void hidinput_report_event(struct hid_device *hid, struct hid_report *report)
+ 		return;
+ 
+ 	list_for_each_entry(hidinput, &hid->inputs, list)
++#if defined(CONFIG_DRIVERS_HDF_INPUT)
++	{
++#endif
+ 		input_sync(hidinput->input);
++#if defined(CONFIG_DRIVERS_HDF_INPUT)
++		if(hid->input_dev)
++			HidReportEvent(hid->input_dev, EV_SYN, SYN_REPORT, 0);
++	}
++#endif
+ }
+ EXPORT_SYMBOL_GPL(hidinput_report_event);
+ 
+@@ -1880,6 +1892,41 @@ static inline void hidinput_configure_usages(struct hid_input *hidinput,
+ 						 report->field[i]->usage + j);
+ }
+ 
++#if defined(CONFIG_DRIVERS_HDF_INPUT)
++static void transfer_info(struct input_dev *dev)
++{
++	HidInfo *info = (HidInfo *)kmalloc(sizeof(HidInfo),GFP_KERNEL);
++	if (info == NULL) {
++		printk("%s: malloc failed\n",__func__);
++		return;
++	}
++	info->devName = dev->name;
++	memcpy(info->devProp, dev->propbit, sizeof(unsigned long) * BITS_TO_LONGS(INPUT_PROP_CNT));
++	memcpy(info->eventType, dev->evbit, sizeof(unsigned long) * BITS_TO_LONGS(EV_CNT));
++	memcpy(info->keyCode, dev->keybit, sizeof(unsigned long) * BITS_TO_LONGS(KEY_CNT));
++	memcpy(info->relCode, dev->relbit, sizeof(unsigned long) * BITS_TO_LONGS(REL_CNT));
++	memcpy(info->absCode, dev->absbit, sizeof(unsigned long) * BITS_TO_LONGS(ABS_CNT));
++	memcpy(info->miscCode, dev->mscbit, sizeof(unsigned long) * BITS_TO_LONGS(MSC_CNT));
++	memcpy(info->ledCode, dev->ledbit, sizeof(unsigned long) * BITS_TO_LONGS(LED_CNT));
++	memcpy(info->soundCode, dev->sndbit, sizeof(unsigned long) * BITS_TO_LONGS(SND_CNT));
++	memcpy(info->forceCode, dev->ffbit, sizeof(unsigned long) * BITS_TO_LONGS(FF_CNT));
++	memcpy(info->switchCode, dev->swbit, sizeof(unsigned long) * BITS_TO_LONGS(SW_CNT));
++	for (int i = 0; i < BITS_TO_LONGS(ABS_CNT); i++) {
++		if (dev->absbit[i] != 0) {
++			memcpy(info->axisInfo, dev->absinfo, sizeof(struct input_absinfo) * ABS_CNT);
++			break;
++		}
++	}
++	info->bustype = dev->id.bustype;
++	info->vendor = dev->id.vendor;
++	info->product = dev->id.product;
++	info->version = dev->id.version;
++	SendInfoToHdf(info);
++	kfree(info);
++	info = NULL;
++}
++#endif
++
+ /*
+  * Register the input device; print a message.
+  * Configure the input layer interface
+@@ -1965,6 +2012,9 @@ int hidinput_connect(struct hid_device *hid, unsigned int force)
+ 			continue;
+ 		}
+ 
++#if defined(CONFIG_DRIVERS_HDF_INPUT)
++		transfer_info(hidinput->input);
++#endif
+ 		if (input_register_device(hidinput->input))
+ 			goto out_unwind;
+ 		hidinput->registered = true;
+diff --git a/drivers/input/mousedev.c b/drivers/input/mousedev.c
+index 505c562a5..67d451beb 100644
+--- a/drivers/input/mousedev.c
++++ b/drivers/input/mousedev.c
+@@ -869,7 +869,7 @@ static struct mousedev *mousedev_create(struct input_dev *dev,
+ 
+ 	if (mixdev) {
+ 		dev_set_name(&mousedev->dev, "mice");
+-
++		mousedev->open = 1;
+ 		mousedev->open_device = mixdev_open_devices;
+ 		mousedev->close_device = mixdev_close_devices;
+ 	} else {
+diff --git a/include/linux/hid.h b/include/linux/hid.h
+index 2ba33d708..76793a036 100644
+--- a/include/linux/hid.h
++++ b/include/linux/hid.h
+@@ -624,6 +624,7 @@ struct hid_device {							/* device report descriptor */
+ 	struct list_head debug_list;
+ 	spinlock_t  debug_list_lock;
+ 	wait_queue_head_t debug_wait;
++	void *input_dev;
+ };
+ 
+ #define to_hid_device(pdev) \
+-- 
+2.34.1
+
-- 
Gitee